<s> bool ix86_match_ccmode ( rtx insn , machine_mode req_mode ) { rtx set ; machine_mode set_mode ; set = PATTERN ( insn ) ; if ( GET_CODE ( set ) == PARALLEL ) set = XVECEXP ( set , 0 , 0 ) ; gcc_assert ( GET_CODE ( set ) == SET ) ; gcc_assert ( GET_CODE ( SET_SRC ( set ) ) == COMPARE ) ; set_mode = GET_MODE ( SET_DEST ( set ) ) ; switch ( set_mode ) { case E_CCNOmode : if ( req_mode != CCNOmode && ( req_mode != CCmode || XEXP ( SET_SRC ( set ) , 1 ) != const0_rtx ) ) return false ; break ; case E_CCmode : if ( req_mode == CCGCmode ) return false ; case E_CCGCmode : if ( req_mode == CCGOCmode || req_mode == CCNOmode ) return false ; case E_CCGOCmode : if ( req_mode == CCZmode ) return false ; case E_CCZmode : break ; case E_CCGZmode : case E_CCAmode : case E_CCCmode : case E_CCOmode : case E_CCPmode : case E_CCSmode : if ( set_mode != req_mode ) return false ; break ; default : gcc_unreachable ( ) ; } return GET_MODE ( SET_SRC ( set ) ) == set_mode ; } </s>

Return TRUE or FALSE depending on whether the first SET in INSN has source and destination with matching CC modes , and that the CC mode is at least as constrained as REQ_MODE .


<s> bool MemSelOpt :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getTarget ( ) . getInstrInfo ( ) ; bool Changed = false ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { Changed |= processBasicBlock ( MF , * I ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> unsigned getOpSize ( const MachineInstr & MI , unsigned OpNo ) const { return getOpRegClass ( MI , OpNo ) -> getSize ( ) ; } </s>

This form should usually be preferred since it handles operands with unknown register classes .


<s>
void
HexagonFrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
auto
&
HST
=
static_cast
<
const
HexagonSubtarget
&
>
(
MF
.
getSubtarget
(
)
)
;
auto
&
HRI
=
*
HST
.
getRegisterInfo
(
)
;
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
->
getCalleeSavedInfo
(
)
;
MachineBasicBlock
*
PrologB
=
&
MF
.
front
(
)
,
*
EpilogB
=
nullptr
;
if
(
EnableShrinkWrapping
)
findShrunkPrologEpilog
(
MF
,
PrologB
,
EpilogB
)
;
insertCSRSpillsInBlock
(
*
PrologB
,
CSI
,
HRI
)
;
insertPrologueInBlock
(
*
PrologB
)
;
if
(
EpilogB
)
{
insertCSRRestoresInBlock
(
*
EpilogB
,
CSI
,
HRI
)
;
insertEpilogueInBlock
(
*
EpilogB
)
;
}
else
{
for
(
auto
&
B
:
MF
)
if
(
B
.
isReturnBlock
(
)
)
insertCSRRestoresInBlock
(
B
,
CSI
,
HRI
)
;
for
(
auto
&
B
:
MF
)
if
(
B
.
isReturnBlock
(
)
)
insertEpilogueInBlock
(
B
)
;
}
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Hexagon
Hexagon
Hexagon
"Shrink-wrapping not yet supported"


<s> enum m32r_function_type m32r_compute_function_type ( tree decl ) { static enum m32r_function_type fn_type = M32R_FUNCTION_UNKNOWN ; static tree last_fn = NULL_TREE ; if ( decl == NULL_TREE ) { fn_type = M32R_FUNCTION_UNKNOWN ; last_fn = NULL_TREE ; return fn_type ; } if ( decl == last_fn && fn_type != M32R_FUNCTION_UNKNOWN ) return fn_type ; fn_type = ( lookup_attribute ( "interrupt" , DECL_ATTRIBUTES ( current_function_decl ) ) != NULL_TREE ? M32R_FUNCTION_INTERRUPT : M32R_FUNCTION_NORMAL ) ; last_fn = decl ; return fn_type ; } </s>

Type of function DECL . The result is cached . To reset the cache at the end of a function , call with DECL = NULL_TREE .


<s> static void swap_reorder ( rtx * a , int n ) { rtx insn = a [ n - 1 ] ; int i = n - 2 ; while ( i >= 0 && rank_for_reorder ( a + i , & insn ) >= 0 ) { a [ i + 1 ] = a [ i ] ; i -= 1 ; } a [ i + 1 ] = insn ; } </s>

Resort the array A in which only element at index N may be out of order .


<s> void GCNIterativeScheduler :: finalizeSchedule ( ) { if ( Regions . empty ( ) ) return ; switch ( Strategy ) { case SCHEDULE_MINREGONLY : scheduleMinReg ( ) ; break ; case SCHEDULE_MINREGFORCED : scheduleMinReg ( true ) ; break ; case SCHEDULE_LEGACYMAXOCCUPANCY : scheduleLegacyMaxOccupancy ( ) ; break ; case SCHEDULE_ILP : scheduleILP ( false ) ; break ; } } </s>

After the schedule has been formed , call this function to combine the instructions from the different stages/cycles .


<s> static unsigned findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const X86RegisterInfo * TRI , bool Is64Bit ) { const MachineFunction * MF = MBB . getParent ( ) ; if ( MF -> callsEHReturn ( ) ) return 0 ; const TargetRegisterClass & AvailableRegs = * TRI -> getGPRsForTailCall ( * MF ) ; if ( MBBI == MBB . end ( ) ) return 0 ; switch ( MBBI -> getOpcode ( ) ) { default : return 0 ; case TargetOpcode :: PATCHABLE_RET : case X86 :: RET : case X86 :: RETL : case X86 :: RETQ : case X86 :: RETIL : case X86 :: RETIQ : case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: TCRETURNmi64 : case X86 :: EH_RETURN : case X86 :: EH_RETURN64 : { SmallSet < uint16_t , 8 > Uses ; for ( unsigned i = 0 , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } for ( auto CS : AvailableRegs ) if ( ! Uses . count ( CS ) && CS != X86 :: RIP && CS != X86 :: RSP && CS != X86 :: ESP ) return CS ; } } return 0 ; } </s>

findDeadCallerSavedReg - Return a caller-saved register that is n't live when it reaches the `` return '' instruction .


<s> void function_expander :: add_address_operand ( rtx x ) { m_ops . safe_grow ( m_ops . length ( ) + 1 ) ; create_address_operand ( & m_ops . last ( ) , x ) ; } </s>

Add an address operand with value X . The static operand data says what mode and form the address must have .


<s> InstructionCost X86TTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind , Instruction * Inst ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; unsigned ImmIdx = ~ 0U ; switch ( Opcode ) { default : return TTI :: TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: Store : ImmIdx = 0 ; break ; case Instruction :: ICmp : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 ) { uint64_t ImmVal = Imm . getZExtValue ( ) ; if ( ImmVal == 0x100000000ULL || ImmVal == 0xffffffff ) return TTI :: TCC_Free ; } ImmIdx = 1 ; break ; case Instruction :: And : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 && isUInt < 32 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; ImmIdx = 1 ; break ; case Instruction :: Add : case Instruction :: Sub : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 && Imm . getZExtValue ( ) == 0x80000000 ) return TTI :: TCC_Free ; ImmIdx = 1 ; break ; case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : return TTI :: TCC_Free ; case Instruction :: Mul : case Instruction :: Or : case Instruction :: Xor : ImmIdx = 1 ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == 1 ) return TTI :: TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: IntToPtr : case Instruction :: PtrToInt : case Instruction :: BitCast : case Instruction :: PHI : case Instruction :: Call : case Instruction :: Select : case Instruction :: Ret : case Instruction :: Load : break ; } if ( Idx == ImmIdx ) { int NumConstants = divideCeil ( BitSize , 64 ) ; InstructionCost Cost = X86TTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ; return ( Cost <= NumConstants * TTI :: TCC_Basic ) ? static_cast < int > ( TTI :: TCC_Free ) : Cost ; } return X86TTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> static int uses_TOC ( void ) { rtx_insn * insn ; int ret = 1 ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( INSN_P ( insn ) ) { rtx pat = PATTERN ( insn ) ; int i ; if ( GET_CODE ( pat ) == PARALLEL ) for ( i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) { rtx sub = XVECEXP ( pat , 0 , i ) ; if ( GET_CODE ( sub ) == USE ) { sub = XEXP ( sub , 0 ) ; if ( GET_CODE ( sub ) == UNSPEC && XINT ( sub , 1 ) == UNSPEC_TOC ) return ret ; } } } else if ( crtl -> has_bb_partition && NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_SWITCH_TEXT_SECTIONS ) ret = 2 ; } return 0 ; } </s>

This retuns nonzero if the current function uses the TOC . This is determined by the presence of ( unspec ... 7 ) , which is generated by the various load_toc_ * patterns .


<s> bool AArch64InstrInfo :: isLdStPairSuppressed ( const MachineInstr & MI ) const { return any_of ( MI . memoperands ( ) , [ ] ( MachineMemOperand * MMO ) { return MMO -> getFlags ( ) & MOSuppressPair ; } ) ; } </s>

Return true if pairing the given load or store is hinted to be unprofitable .


"Unable to build a return instruction?!"

"The insertion did not happen where we expected"

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> const LanaiTargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


<s> const TargetRegisterClass * AArch64RegisterInfo :: getCrossCopyRegClass ( const TargetRegisterClass * RC ) const { if ( RC == & AArch64 :: CCRRegClass ) return & AArch64 :: GPR64RegClass ; return RC ; } </s>

getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or from .


<s> ARMSubtarget :: ARMSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const ARMBaseTargetMachine & TM , bool IsLittle ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , ARMProcClass ( None ) , stackAlignment ( 4 ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( ARMBaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( ARMBaseInstrInfo * ) new ARMInstrInfo ( * this ) : ( ARMBaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) { } </s>

This constructor initializes the data members to match that of the specified triple .

ARM ARM ARM ARM ARM ARM ARM 4 ARM ARM ARM ARM


<s> void SIMachineFunctionInfo :: removeDeadFrameIndices ( MachineFrameInfo & MFI ) { for ( auto & R : make_early_inc_range ( SGPRToVGPRSpills ) ) { if ( R . first != FramePointerSaveIndex && R . first != BasePointerSaveIndex ) { MFI . RemoveStackObject ( R . first ) ; SGPRToVGPRSpills . erase ( R . first ) ; } } for ( int i = MFI . getObjectIndexBegin ( ) , e = MFI . getObjectIndexEnd ( ) ; i != e ; ++ i ) if ( i != FramePointerSaveIndex && i != BasePointerSaveIndex ) MFI . setStackID ( i , TargetStackID :: Default ) ; for ( auto & R : VGPRToAGPRSpills ) { if ( R . second . FullyAllocated ) MFI . RemoveStackObject ( R . first ) ; } } </s>

If ResetSGPRSpillStackIDs is true , reset the stack ID from sgpr-spill to the default stack .


<s> static enum immediate_class classify_immediate ( rtx op , machine_mode mode ) { HOST_WIDE_INT val ; unsigned char arr [ 16 ] ; int i , j , repeated , fsmbi , repeat ; gcc_assert ( CONSTANT_P ( op ) ) ; if ( GET_MODE ( op ) != VOIDmode ) mode = GET_MODE ( op ) ; if ( ! flag_pic && mode == V4SImode && GET_CODE ( op ) == CONST_VECTOR && GET_CODE ( CONST_VECTOR_ELT ( op , 0 ) ) != CONST_INT && GET_CODE ( CONST_VECTOR_ELT ( op , 0 ) ) != CONST_DOUBLE ) op = unwrap_const_vec_duplicate ( op ) ; switch ( GET_CODE ( op ) ) { case SYMBOL_REF : case LABEL_REF : return TARGET_LARGE_MEM ? IC_IL2s : IC_IL1s ; case CONST : if ( ! TARGET_LARGE_MEM && GET_CODE ( XEXP ( op , 0 ) ) == PLUS ) { rtx sym = XEXP ( XEXP ( op , 0 ) , 0 ) ; rtx cst = XEXP ( XEXP ( op , 0 ) , 1 ) ; if ( GET_CODE ( sym ) == SYMBOL_REF && GET_CODE ( cst ) == CONST_INT && satisfies_constraint_K ( cst ) ) return IC_IL1s ; } return IC_IL2s ; case HIGH : return IC_IL1s ; case CONST_VECTOR : for ( i = 0 ; i < GET_MODE_NUNITS ( mode ) ; i ++ ) if ( GET_CODE ( CONST_VECTOR_ELT ( op , i ) ) != CONST_INT && GET_CODE ( CONST_VECTOR_ELT ( op , i ) ) != CONST_DOUBLE ) return IC_POOL ; case CONST_INT : case CONST_DOUBLE : constant_to_array ( mode , op , arr ) ; repeated = 1 ; for ( i = 4 ; i < 16 ; i += 4 ) for ( j = 0 ; j < 4 ; j ++ ) if ( arr [ j ] != arr [ i + j ] ) repeated = 0 ; if ( repeated ) { val = ( arr [ 0 ] << 24 ) | ( arr [ 1 ] << 16 ) | ( arr [ 2 ] << 8 ) | arr [ 3 ] ; val = trunc_int_for_mode ( val , SImode ) ; if ( which_immediate_load ( val ) != SPU_NONE ) return IC_IL1 ; } gcc_assert ( GET_MODE_SIZE ( mode ) > 2 ) ; fsmbi = 1 ; repeat = 0 ; for ( i = 0 ; i < 16 && fsmbi ; i ++ ) if ( arr [ i ] != 0 && repeat == 0 ) repeat = arr [ i ] ; else if ( arr [ i ] != 0 && arr [ i ] != repeat ) fsmbi = 0 ; if ( fsmbi ) return repeat == 0xff ? IC_FSMBI : IC_FSMBI2 ; if ( cpat_info ( arr , GET_MODE_SIZE ( mode ) , 0 , 0 ) ) return IC_CPAT ; if ( repeated ) return IC_IL2 ; return IC_POOL ; default : break ; } gcc_unreachable ( ) ; } </s>

OP is a CONSTANT_P . Determine what instructions can be used to load it into a register . MODE is only valid when OP is a CONST_INT .


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( PPC :: R0 ) ; Reserved . set ( PPC :: R1 ) ; Reserved . set ( PPC :: LR ) ; Reserved . set ( PPC :: LR8 ) ; Reserved . set ( PPC :: RM ) ; if ( ! Subtarget . isDarwin ( ) ) Reserved . set ( PPC :: R2 ) ; if ( Subtarget . isPPC64 ( ) ) { Reserved . set ( PPC :: R13 ) ; Reserved . set ( PPC :: R31 ) ; if ( ! EnableRegisterScavenging ) Reserved . set ( PPC :: R0 ) ; Reserved . set ( PPC :: X0 ) ; Reserved . set ( PPC :: X1 ) ; Reserved . set ( PPC :: X13 ) ; Reserved . set ( PPC :: X31 ) ; } if ( needsFP ( MF ) ) Reserved . set ( PPC :: R31 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


For stack frames that ca n't be allocated with a single ADDI instruction , compute the best value to initially allocate . It must at a minimum allocate enough space to spill the callee-saved registers .


<s> void BTFTypeTypeTag :: completeType ( BTFDebug & BDebug ) { if ( IsCompleted ) return ; IsCompleted = true ; BTFType . NameOff = BDebug . addString ( Tag ) ; if ( DTy ) { const DIType * ResolvedType = DTy -> getBaseType ( ) ; if ( ! ResolvedType ) BTFType . Type = 0 ; else BTFType . Type = BDebug . getTypeId ( ResolvedType ) ; } } </s>

Complete BTF type generation after all related DebugInfo types have been visited so their BTF type id 's are available for cross referece .


<s> bool Thumb2ITBlockPass :: runOnMachineFunction ( MachineFunction & Fn ) { const ARMSubtarget & STI = static_cast < const ARMSubtarget & > ( Fn . getSubtarget ( ) ) ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( STI . getInstrInfo ( ) ) ; TRI = STI . getRegisterInfo ( ) ; restrictIT = STI . restrictIT ( ) ; if ( ! AFI -> isThumbFunction ( ) ) return false ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ) { MachineBasicBlock & MBB = * MFI ; ++ MFI ; Modified |= InsertITInstructions ( MBB ) ; } if ( Modified ) AFI -> setHasITBlocks ( true ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool isInlineConstant ( const APFloat & Imm ) const { return isInlineConstant ( Imm . bitcastToAPInt ( ) ) ; } </s>

returns true if the operand OpIdx in MI is a valid inline immediate .


<s> void c6x_expand_call ( rtx retval , rtx address , bool sibcall ) { rtx callee = XEXP ( address , 0 ) ; rtx call_insn ; if ( ! c6x_call_operand ( callee , Pmode ) ) { callee = force_reg ( Pmode , callee ) ; address = change_address ( address , Pmode , callee ) ; } call_insn = gen_rtx_CALL ( VOIDmode , address , const0_rtx ) ; if ( sibcall ) { call_insn = emit_call_insn ( call_insn ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( call_insn ) , gen_rtx_REG ( Pmode , REG_B3 ) ) ; } else { if ( retval == NULL_RTX ) call_insn = emit_call_insn ( call_insn ) ; else call_insn = emit_call_insn ( gen_rtx_SET ( GET_MODE ( retval ) , retval , call_insn ) ) ; } if ( flag_pic ) use_reg ( & CALL_INSN_FUNCTION_USAGE ( call_insn ) , pic_offset_table_rtx ) ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"AVR Frame Analyzer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> DecodeStatus BPFDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & VStream , raw_ostream & CStream ) const { bool IsLittleEndian = getContext ( ) . getAsmInfo ( ) -> isLittleEndian ( ) ; uint64_t Insn , Hi ; DecodeStatus Result ; Result = readInstruction64 ( Bytes , Address , Size , Insn , IsLittleEndian ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; uint8_t InstClass = getInstClass ( Insn ) ; if ( ( InstClass == BPF_LDX || InstClass == BPF_STX ) && getInstSize ( Insn ) != BPF_DW && getInstMode ( Insn ) == BPF_MEM && STI . getFeatureBits ( ) [ BPF :: ALU32 ] ) Result = decodeInstruction ( DecoderTableBPFALU3264 , Instr , Insn , Address , this , STI ) ; else Result = decodeInstruction ( DecoderTableBPF64 , Instr , Insn , Address , this , STI ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; switch ( Instr . getOpcode ( ) ) { case BPF :: LD_imm64 : case BPF :: LD_pseudo : { if ( Bytes . size ( ) < 16 ) { Size = 0 ; return MCDisassembler :: Fail ; } Size = 16 ; if ( IsLittleEndian ) Hi = ( Bytes [ 12 ] << 0 ) | ( Bytes [ 13 ] << 8 ) | ( Bytes [ 14 ] << 16 ) | ( Bytes [ 15 ] << 24 ) ; else Hi = ( Bytes [ 12 ] << 24 ) | ( Bytes [ 13 ] << 16 ) | ( Bytes [ 14 ] << 8 ) | ( Bytes [ 15 ] << 0 ) ; auto & Op = Instr . getOperand ( 1 ) ; Op . setImm ( Make_64 ( Hi , Op . getImm ( ) ) ) ; break ; } case BPF :: LD_ABS_B : case BPF :: LD_ABS_H : case BPF :: LD_ABS_W : case BPF :: LD_IND_B : case BPF :: LD_IND_H : case BPF :: LD_IND_W : { auto Op = Instr . getOperand ( 0 ) ; Instr . clear ( ) ; Instr . addOperand ( MCOperand :: createReg ( BPF :: R6 ) ) ; Instr . addOperand ( Op ) ; break ; } } return Result ; } </s>

Returns the disassembly of a single instruction .


<s> bool MipsTargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> static void m32c_function_arg_advance ( cumulative_args_t ca_v , const function_arg_info & ) { CUMULATIVE_ARGS * ca = get_cumulative_args ( ca_v ) ; if ( ca -> force_mem ) ca -> force_mem = 0 ; else ca -> parm_num ++ ; } </s>

Implements FUNCTION_ARG_ADVANCE . force_mem is set for functions returning structures , so we always reset that . Otherwise , we only need to know the sequence number of the argument to know what to do with it .


<s> static bool already_contains ( rtx loc , rtx value ) { unsigned char index ; unsigned char val ; if ( ( index = get_content_index ( loc ) ) == NOT_KNOWN ) return false ; if ( ( val = get_content_index ( value ) ) == NOT_KNOWN ) return false ; if ( content_memory [ index ] != val ) return false ; if ( GET_MODE ( loc ) == HImode ) return content_memory [ index + 1 ] == val + 1 ; return true ; } </s>

Returns TRUE if LOC already contains a copy of VALUE .


<s> static int s390_register_move_cost ( machine_mode mode , reg_class_t from , reg_class_t to ) { if ( TARGET_Z10 && GET_MODE_SIZE ( mode ) == 8 ) { if ( reg_classes_intersect_p ( from , GENERAL_REGS ) && reg_classes_intersect_p ( to , FP_REGS ) ) return 1 ; if ( reg_classes_intersect_p ( to , GENERAL_REGS ) && reg_classes_intersect_p ( from , FP_REGS ) ) return 3 ; } if ( ( reg_classes_intersect_p ( from , GENERAL_REGS ) && reg_classes_intersect_p ( to , FP_REGS ) ) || ( reg_classes_intersect_p ( from , FP_REGS ) && reg_classes_intersect_p ( to , GENERAL_REGS ) ) ) return 10 ; if ( reg_classes_intersect_p ( from , CC_REGS ) || reg_classes_intersect_p ( to , CC_REGS ) ) return 5 ; return 1 ; } </s>


<s> void MSP430RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned BasePtr = ( TFI -> hasFP ( MF ) ? MSP430 :: FPW : MSP430 :: SPW ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; Offset += 2 ; if ( ! TFI -> hasFP ( MF ) ) Offset += MF . getFrameInfo ( ) -> getStackSize ( ) ; else Offset += 2 ; Offset += MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ; if ( MI . getOpcode ( ) == MSP430 :: ADD16ri ) { const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; MI . setDesc ( TII . get ( MSP430 :: MOV16rr ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; if ( Offset == 0 ) return ; unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ; if ( Offset < 0 ) BuildMI ( MBB , llvm :: next ( II ) , dl , TII . get ( MSP430 :: SUB16ri ) , DstReg ) . addReg ( DstReg ) . addImm ( - Offset ) ; else BuildMI ( MBB , llvm :: next ( II ) , dl , TII . get ( MSP430 :: ADD16ri ) , DstReg ) . addReg ( DstReg ) . addImm ( Offset ) ; return ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static int thumb_base_register_rtx_p ( rtx x , enum machine_mode mode , int strict_p ) { int regno ; if ( GET_CODE ( x ) != REG ) return 0 ; regno = REGNO ( x ) ; if ( strict_p ) return THUMB_REGNO_MODE_OK_FOR_BASE_P ( regno , mode ) ; return ( regno <= LAST_LO_REGNUM || regno > LAST_VIRTUAL_REGISTER || regno == FRAME_POINTER_REGNUM || ( GET_MODE_SIZE ( mode ) >= 4 && ( regno == STACK_POINTER_REGNUM || regno >= FIRST_PSEUDO_REGISTER || x == hard_frame_pointer_rtx || x == arg_pointer_rtx ) ) ) ; } </s>

Return nonzero if X is valid as a Thumb state base register .


<s> Reloc :: Model MipsSubtarget :: getRelocationModel ( ) const { return TM -> getRelocationModel ( ) ; } </s>

Returns the code generation relocation model .


<s> bool MipsAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < MipsSubtarget > ( ) ; MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; if ( Subtarget -> inMips16Mode ( ) ) for ( std :: map < const char * , const Mips16HardFloatInfo :: FuncSignature * > :: const_iterator it = MipsFI -> StubsNeeded . begin ( ) ; it != MipsFI -> StubsNeeded . end ( ) ; ++ it ) { const char * Symbol = it -> first ; const Mips16HardFloatInfo :: FuncSignature * Signature = it -> second ; if ( StubsNeeded . find ( Symbol ) == StubsNeeded . end ( ) ) StubsNeeded [ Symbol ] = Signature ; } MCP = MF . getConstantPool ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) NaClAlignIndirectJumpTargets ( MF ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; emitXRayTable ( ) ; return true ; } </s>

Mips Mips Mips Mips Mips Mips Mips16HardFloatInfo::FuncSignature Mips Mips Mips16HardFloatInfo::FuncSignature


<s> virtual unsigned int execute ( function * ) { return frame_header_opt ( ) ; } </s>


<s> static int rs6000_reassociation_width ( unsigned int opc ATTRIBUTE_UNUSED , machine_mode mode ) { switch ( rs6000_cpu ) { case PROCESSOR_POWER8 : case PROCESSOR_POWER9 : if ( DECIMAL_FLOAT_MODE_P ( mode ) ) return 1 ; if ( VECTOR_MODE_P ( mode ) ) return 4 ; if ( INTEGRAL_MODE_P ( mode ) ) return opc == MULT_EXPR ? 4 : 6 ; if ( FLOAT_MODE_P ( mode ) ) return 4 ; break ; default : break ; } return 1 ; } </s>

Determine the reassociation width to be used in reassociate_bb . This takes into account how many parallel operations we can actually do of a given type , and also the latency . P8 : int add/sub 6/cycle mul 2/cycle vect add/sub/mul 2/cycle fp add/sub/mul 2/cycle dfp 1/cycle


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LiveIntervals > ( ) ; AU . addPreserved < LiveIntervals > ( ) ; AU . addRequired < SlotIndexes > ( ) ; AU . addPreserved < SlotIndexes > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> virtual SMLoc getEndLoc ( ) const LLVM_OVERRIDE { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s>
void
AVRInstPrinter
::
printInst
(
const
MCInst
*
MI
,
uint64_t
Address
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
,
raw_ostream
&
O
)
{
unsigned
Opcode
=
MI
->
getOpcode
(
)
;
switch
(
Opcode
)
{
case
AVR
::
LDRdPtr
:
case
AVR
::
LDRdPtrPi
:
case
AVR
::
LDRdPtrPd
:
O
<<
"\tld\t"
;
printOperand
(
MI
,
0
,
O
)
;
O
<<
", "
;
if
(
Opcode
==
AVR
::
LDRdPtrPd
)
O
<<
'-'
;
printOperand
(
MI
,
1
,
O
)
;
if
(
Opcode
==
AVR
::
LDRdPtrPi
)
O
<<
'+'
;
break
;
case
AVR
::
STPtrRr
:
O
<<
"\tst\t"
;
printOperand
(
MI
,
0
,
O
)
;
O
<<
", "
;
printOperand
(
MI
,
1
,
O
)
;
break
;
case
AVR
::
STPtrPiRr
:
case
AVR
::
STPtrPdRr
:
O
<<
"\tst\t"
;
if
(
Opcode
==
AVR
::
STPtrPdRr
)
O
<<
'-'
;
printOperand
(
MI
,
1
,
O
)
;
if
(
Opcode
==
AVR
::
STPtrPiRr
)
O
<<
'+'
;
O
<<
", "
;
printOperand
(
MI
,
2
,
O
)
;
break
;
default
:
if
(
!
printAliasInstr
(
MI
,
O
)
)
printInstruction
(
MI
,
Address
,
O
)
;
printAnnotation
(
O
,
Annot
)
;
break
;
}
}
</s>

Print the specified MCInst to the specified raw_ostream .

AVR
AVR
AVR::LDRdPtr
AVR::LDRdPtrPi
AVR::LDRdPtrPd
"\tld\t"
0
", "
AVR::LDRdPtrPd
1
AVR::LDRdPtrPi
AVR::STPtrRr
"\tst\t"
0
", "
1
AVR::STPtrPiRr
AVR::STPtrPdRr
"\tst\t"
AVR::STPtrPdRr
1
AVR::STPtrPiRr
", "
2


<s>
int
AArch64FrameLowering
::
getFrameIndexReferencePreferSP
(
const
MachineFunction
&
MF
,
int
FI
,
unsigned
&
FrameReg
,
bool
IgnoreSPUpdates
)
const
{
const
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
if
(
IgnoreSPUpdates
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Offset from the SP for "
<<
FI
<<
" is "
<<
MFI
.
getObjectOffset
(
FI
)
<<
"\n"
)
;
FrameReg
=
AArch64
::
SP
;
return
MFI
.
getObjectOffset
(
FI
)
;
}
return
getFrameIndexReference
(
MF
,
FI
,
FrameReg
)
;
}
</s>

Same as getFrameIndexReference , except that the stack pointer ( as opposed to the frame pointer ) will be the preferred value for FrameReg .


<s> int HexagonConvergingVLIWScheduler :: SchedulingCost ( ReadyQueue & Q , SUnit * SU , SchedCandidate & Candidate , RegPressureDelta & Delta , bool verbose ) { int ResCount = ConvergingVLIWScheduler :: SchedulingCost ( Q , SU , Candidate , Delta , verbose ) ; if ( ! SU || SU -> isScheduled ) return ResCount ; auto & QST = DAG -> MF . getSubtarget < HexagonSubtarget > ( ) ; auto & QII = * QST . getInstrInfo ( ) ; if ( SU -> isInstr ( ) && QII . mayBeCurLoad ( * SU -> getInstr ( ) ) ) { if ( Q . getID ( ) == TopQID && Top . ResourceModel -> isResourceAvailable ( SU , true ) ) { ResCount += PriorityTwo ; LLVM_DEBUG ( if ( verbose ) dbgs ( ) << "C|" ) ; } else if ( Q . getID ( ) == BotQID && Bot . ResourceModel -> isResourceAvailable ( SU , false ) ) { ResCount += PriorityTwo ; LLVM_DEBUG ( if ( verbose ) dbgs ( ) << "C|" ) ; } } return ResCount ; } </s>

Single point to compute overall scheduling cost .


<s> bool SPIRVOCLRegularizer :: runOnFunction ( Function & F ) { visit ( F ) ; for ( auto & OldNew : Old2NewFuncs ) { auto * OldF = OldNew . first ; auto * NewF = OldNew . second ; NewF -> takeName ( OldF ) ; OldF -> eraseFromParent ( ) ; } return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static bool tilegx_current_function_is_leaf ( void ) { return crtl -> is_leaf && ! cfun -> machine -> calls_tls_get_addr ; } </s>

Return whether the current function is leaf . This takes into account whether the function calls tls_get_addr .


<s> static tree c6x_build_builtin_va_list ( void ) { return build_pointer_type ( char_type_node ) ; } </s>

Return the type to use as __builtin_va_list .


<s> void AMDGPUInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { } </s>

Insert a noop into the instruction stream at the specified point .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
Kind
==
KindTy
::
Register
&&
"Invalid type access!"
)
;
return
Reg
.
RegNum
.
id
(
)
;
}
</s>

Returns the register associated with this edge .


<s> bool AArch64TargetLowering :: isLegalICmpImmediate ( int64_t Immed ) const { if ( Immed < 0 ) Immed *= - 1 ; return isLegalAddImmediate ( Immed ) ; } </s>

Return true if the specified immediate is legal icmp immediate , that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register .


<s> static void ix86_emit_save_regs ( void ) { unsigned int regno ; rtx_insn * insn ; for ( regno = FIRST_PSEUDO_REGISTER - 1 ; regno -- > 0 ; ) if ( GENERAL_REGNO_P ( regno ) && ix86_save_reg ( regno , true , true ) ) { insn = emit_insn ( gen_push ( gen_rtx_REG ( word_mode , regno ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } </s>

Emit code to save registers in the prologue .


<s> bool Thumb2InstrInfo :: isLegalToSplitMBBAt ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) const { while ( MBBI -> isDebugValue ( ) ) { ++ MBBI ; if ( MBBI == MBB . end ( ) ) return false ; } unsigned PredReg = 0 ; return getITInstrPredicate ( MBBI , PredReg ) == ARMCC :: AL ; } </s>

Return true if it 's legal to split the given basic block at the specified instruction ( i.e .


<s> static void aarch64_emit_atomic_swap ( machine_mode mode , rtx dst , rtx value , rtx mem , rtx model ) { rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; switch ( mode ) { case QImode : gen = gen_aarch64_atomic_swpqi ; break ; case HImode : gen = gen_aarch64_atomic_swphi ; break ; case SImode : gen = gen_aarch64_atomic_swpsi ; break ; case DImode : gen = gen_aarch64_atomic_swpdi ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( dst , mem , value , model ) ) ; } </s>


<s> static bool cris_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { return ( ( mode == CCmode || regno != CRIS_CC0_REGNUM ) && ( GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD || regno != CRIS_MOF_REGNUM ) ) ; } </s>

Implement TARGET_HARD_REGNO_MODE_OK . CRIS permits all registers to hold all modes . Well , except for the condition-code register . And we ca n't hold larger-than-register size modes in the last special register that can hold a full 32 bits .


<s> static bool mips_load_call_address ( enum mips_call_type type , rtx dest , rtx addr ) { if ( TARGET_EXPLICIT_RELOCS && ! ( type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP ) && mips_ok_for_lazy_binding_p ( addr ) ) { addr = mips_got_load ( dest , addr , SYMBOL_GOTOFF_CALL ) ; emit_insn ( gen_rtx_SET ( dest , addr ) ) ; return true ; } else { mips_emit_move ( dest , addr ) ; return false ; } } </s>

Load function address ADDR into register DEST . SIBCALL_P is true if the address is needed for a sibling call .


"There must be a free register after frame setup"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s>
bool
ARM64MCInstLower
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
const
{
switch
(
MO
.
getType
(
)
)
{
default
:
assert
(
0
&&
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
)
return
false
;
MCOp
=
MCOperand
::
CreateReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_RegisterMask
:
return
false
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
CreateImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
CreateExpr
(
MCSymbolRefExpr
::
Create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
Ctx
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
LowerSymbolOperand
(
MO
,
GetGlobalAddressSymbol
(
MO
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
LowerSymbolOperand
(
MO
,
GetExternalSymbolSymbol
(
MO
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
MCOp
=
LowerSymbolOperand
(
MO
,
Printer
.
GetJTISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
MCOp
=
LowerSymbolOperand
(
MO
,
Printer
.
GetCPISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_BlockAddress
:
MCOp
=
LowerSymbolOperand
(
MO
,
Printer
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
)
;
break
;
}
return
true
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> bool SIAnnotateControlFlow :: runOnFunction ( Function & F ) { DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; LI = & getAnalysis < LoopInfo > ( ) ; for ( df_iterator < BasicBlock * > I = df_begin ( & F . getEntryBlock ( ) ) , E = df_end ( & F . getEntryBlock ( ) ) ; I != E ; ++ I ) { BranchInst * Term = dyn_cast < BranchInst > ( ( * I ) -> getTerminator ( ) ) ; if ( ! Term || Term -> isUnconditional ( ) ) { if ( isTopOfStack ( * I ) ) closeControlFlow ( * I ) ; continue ; } if ( I . nodeVisited ( Term -> getSuccessor ( 1 ) ) ) { if ( isTopOfStack ( * I ) ) closeControlFlow ( * I ) ; handleLoop ( Term ) ; continue ; } if ( isTopOfStack ( * I ) ) { PHINode * Phi = dyn_cast < PHINode > ( Term -> getCondition ( ) ) ; if ( Phi && Phi -> getParent ( ) == * I && isElse ( Phi ) ) { insertElse ( Term ) ; eraseIfUnused ( Phi ) ; continue ; } closeControlFlow ( * I ) ; } openIf ( Term ) ; } assert ( Stack . empty ( ) ) ; return true ; } </s>


<s>
bool
MipsCodeEmitter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
JTI
=
(
(
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getJITInfo
(
)
;
II
=
(
(
const
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getInstrInfo
(
)
;
TD
=
(
(
const
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getTargetData
(
)
;
Subtarget
=
&
TM
.
getSubtarget
<
MipsSubtarget
>
(
)
;
MCPEs
=
&
MF
.
getConstantPool
(
)
->
getConstants
(
)
;
MJTEs
=
0
;
if
(
MF
.
getJumpTableInfo
(
)
)
MJTEs
=
&
MF
.
getJumpTableInfo
(
)
->
getJumpTables
(
)
;
JTI
->
Initialize
(
MF
,
IsPIC
)
;
MCE
.
setModuleInfo
(
&
getAnalysis
<
MachineModuleInfo
>
(
)
)
;
do
{
DEBUG
(
errs
(
)
<<
"JITTing function '"
<<
MF
.
getFunction
(
)
->
getName
(
)
<<
"'\n"
)
;
MCE
.
startFunction
(
MF
)
;
for
(
MachineFunction
::
iterator
MBB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBB
!=
E
;
++
MBB
)
{
MCE
.
StartMachineBasicBlock
(
MBB
)
;
for
(
MachineBasicBlock
::
iterator
I
=
MBB
->
begin
(
)
,
E
=
MBB
->
end
(
)
;
I
!=
E
;
++
I
)
emitInstruction
(
*
I
)
;
}
}
while
(
MCE
.
finishFunction
(
MF
)
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .

Mips
Mips
Mips
Mips
Mips
Mips
0
"JITTing function '"
"'\n"


"LowerFormalArguments Unhandled argument type: "

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> void SystemZAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { printInstruction ( MI ) ; OutStreamer . AddBlankLine ( ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool PPCFastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Load : return SelectLoad ( I ) ; case Instruction :: Store : return SelectStore ( I ) ; case Instruction :: Br : return SelectBranch ( I ) ; case Instruction :: IndirectBr : return SelectIndirectBr ( I ) ; case Instruction :: FPExt : return SelectFPExt ( I ) ; case Instruction :: FPTrunc : return SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return SelectIToFP ( I , true ) ; case Instruction :: UIToFP : return SelectIToFP ( I , false ) ; case Instruction :: FPToSI : return SelectFPToI ( I , true ) ; case Instruction :: FPToUI : return SelectFPToI ( I , false ) ; case Instruction :: Add : return SelectBinaryIntOp ( I , ISD :: ADD ) ; case Instruction :: Or : return SelectBinaryIntOp ( I , ISD :: OR ) ; case Instruction :: Sub : return SelectBinaryIntOp ( I , ISD :: SUB ) ; case Instruction :: Call : if ( TM . getTargetTriple ( ) . isOSAIX ( ) ) break ; return selectCall ( I ) ; case Instruction :: Ret : return SelectRet ( I ) ; case Instruction :: Trunc : return SelectTrunc ( I ) ; case Instruction :: ZExt : case Instruction :: SExt : return SelectIntExt ( I ) ; default : break ; } return false ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> void ScheduleDAGPostRA :: placeDebugValues ( ) { if ( FirstDbgValue ) { BB -> splice ( RegionBegin , BB , FirstDbgValue ) ; RegionBegin = FirstDbgValue ; } for ( std :: vector < std :: pair < MachineInstr * , MachineInstr * > > :: iterator DI = DbgValues . end ( ) , DE = DbgValues . begin ( ) ; DI != DE ; -- DI ) { std :: pair < MachineInstr * , MachineInstr * > P = * prior ( DI ) ; MachineInstr * DbgValue = P . first ; MachineBasicBlock :: instr_iterator OrigPrevMI = P . second ; while ( OrigPrevMI -> isBundledWithSucc ( ) ) { OrigPrevMI ++ ; } moveInstruction ( DbgValue , ++ OrigPrevMI ) ; } DbgValues . clear ( ) ; FirstDbgValue = NULL ; } </s>

Reinsert debug_values recorded in ScheduleDAGInstrs : :DbgValues .


<s> const uint32_t * AVRRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return ( ( CC == CallingConv :: AVR_INTR || CC == CallingConv :: AVR_SIGNAL ) ? CSR_Interrupts_RegMask : CSR_Normal_RegMask ) ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool Z80oldRegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { return false ; const Z80oldSubtarget & STI = MBB . getParent ( ) -> getSubtarget < Z80oldSubtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; DebugLoc DL ; if ( Reg == Z80old :: AF ) { BuildMI ( MBB , MI , DL , TII . get ( Z80old :: PUSH16AF ) ) ; } else BuildMI ( MBB , MI , DL , TII . get ( Z80old :: PUSH16r ) ) . addReg ( Reg ) ; for ( MachineBasicBlock :: iterator II = MI ; II != UseMI ; ++ II ) { if ( II -> isDebugValue ( ) ) { continue ; } if ( II -> modifiesRegister ( Reg , TRI ) ) { UseMI = II ; } } if ( Reg == Z80old :: AF ) { BuildMI ( MBB , UseMI , DL , TII . get ( Z80old :: POP16AF ) ) ; } else { BuildMI ( MBB , UseMI , DL , TII . get ( Z80old :: POP16r ) , Reg ) ; } return true ; } </s>

Spill the register so it can be used by the register scavenger .


<s> static bool must_reload_pic_reg_p ( void ) { struct cgraph_local_info * i = NULL ; if ( ! TARGET_DSBT ) return false ; i = cgraph_node :: local_info ( current_function_decl ) ; if ( ( crtl -> uses_pic_offset_table || ! crtl -> is_leaf ) && ! i -> local ) return true ; return false ; } </s>

Return true if we need to save and modify the PIC register in the prologue .


<s>
bool
R600VectorRegMerger
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
TII
=
static_cast
<
const
R600InstrInfo
*
>
(
Fn
.
getTarget
(
)
.
getInstrInfo
(
)
)
;
MRI
=
&
(
Fn
.
getRegInfo
(
)
)
;
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
MachineBasicBlock
*
MB
=
MBB
;
PreviousRegSeq
.
clear
(
)
;
PreviousRegSeqByReg
.
clear
(
)
;
PreviousRegSeqByUndefCount
.
clear
(
)
;
for
(
MachineBasicBlock
::
iterator
MII
=
MB
->
begin
(
)
,
MIIE
=
MB
->
end
(
)
;
MII
!=
MIIE
;
++
MII
)
{
MachineInstr
*
MI
=
MII
;
if
(
MI
->
getOpcode
(
)
!=
AMDGPU
::
REG_SEQUENCE
)
{
if
(
TII
->
get
(
MI
->
getOpcode
(
)
)
.
TSFlags
&
R600_InstFlag
::
TEX_INST
)
{
unsigned
Reg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
for
(
MachineRegisterInfo
::
def_iterator
It
=
MRI
->
def_begin
(
Reg
)
,
E
=
MRI
->
def_end
(
)
;
It
!=
E
;
++
It
)
{
RemoveMI
(
&
(
*
It
)
)
;
}
}
continue
;
}
RegSeqInfo
RSI
(
*
MRI
,
MI
)
;
unsigned
Reg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
if
(
!
areAllUsesSwizzeable
(
Reg
)
)
continue
;
DEBUG
(
dbgs
(
)
<<
"Trying to optimize "
;
MI
->
dump
(
)
;
)
;
RegSeqInfo
CandidateRSI
;
std
::
vector
<
std
::
pair
<
unsigned
,
unsigned
>
>
RemapChan
;
DEBUG
(
dbgs
(
)
<<
"Using common slots...\n"
;
)
;
if
(
tryMergeUsingCommonSlot
(
RSI
,
CandidateRSI
,
RemapChan
)
)
{
RemoveMI
(
CandidateRSI
.
Instr
)
;
MII
=
RebuildVector
(
&
RSI
,
&
CandidateRSI
,
RemapChan
)
;
trackRSI
(
RSI
)
;
continue
;
}
DEBUG
(
dbgs
(
)
<<
"Using free slots...\n"
;
)
;
RemapChan
.
clear
(
)
;
if
(
tryMergeUsingFreeSlot
(
RSI
,
CandidateRSI
,
RemapChan
)
)
{
RemoveMI
(
CandidateRSI
.
Instr
)
;
MII
=
RebuildVector
(
&
RSI
,
&
CandidateRSI
,
RemapChan
)
;
trackRSI
(
RSI
)
;
continue
;
}
trackRSI
(
RSI
)
;
}
}
return
false
;
}
</s>

R600
R600_InstFlag::TEX_INST
1
SI
0
"Trying to optimize "
SI
"Using common slots...\n"
SI
SI
SI
SI
SI
SI
SI
"Using free slots...\n"
SI
SI
SI
SI
SI
SI
SI
SI
SI


<s> static tree gen_stdcall_or_fastcall_suffix ( tree decl , bool fastcall ) { int total = 0 ; const char * asmname = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; char * newsym ; char * p ; tree formal_type ; if ( * asmname == '*' || strchr ( asmname , '@' ) ) return DECL_ASSEMBLER_NAME ( decl ) ; formal_type = TYPE_ARG_TYPES ( TREE_TYPE ( decl ) ) ; if ( formal_type != NULL_TREE ) { if ( TREE_VALUE ( tree_last ( formal_type ) ) != void_type_node ) return DECL_ASSEMBLER_NAME ( decl ) ; while ( TREE_VALUE ( formal_type ) != void_type_node && COMPLETE_TYPE_P ( TREE_VALUE ( formal_type ) ) ) { int parm_size = TREE_INT_CST_LOW ( TYPE_SIZE ( TREE_VALUE ( formal_type ) ) ) ; parm_size = ( ( parm_size + PARM_BOUNDARY - 1 ) / PARM_BOUNDARY * PARM_BOUNDARY ) ; total += parm_size ; formal_type = TREE_CHAIN ( formal_type ) ; \ } } newsym = alloca ( 1 + strlen ( asmname ) + 1 + 8 + 1 ) ; p = newsym ; if ( fastcall ) * p ++ = FASTCALL_PREFIX ; sprintf ( p , "%s@%d" , asmname , total / BITS_PER_UNIT ) ; return get_identifier ( newsym ) ; } </s>

Return string which is the former assembler name modified with a suffix consisting of an atsign ( @ ) followed by the number of bytes of arguments . If FASTCALL is true , also add the FASTCALL_PREFIX .


<s> static bool is_cmp ( rtx_insn * insn ) { enum attr_type type ; type = get_attr_type ( insn ) ; return ( type == TYPE_TEST || type == TYPE_ICMP || type == TYPE_FCMP || GET_CODE ( PATTERN ( insn ) ) == COMPARE ) ; } </s>

Return true if insn is a compare instruction .


<s> bool AMDGPUAlwaysInline :: runOnModule ( Module & M ) { std :: vector < Function * > FuncsToClone ; for ( Function & F : M ) { if ( ! F . hasLocalLinkage ( ) && ! F . isDeclaration ( ) && ! F . use_empty ( ) && ! F . hasFnAttribute ( Attribute :: NoInline ) ) FuncsToClone . push_back ( & F ) ; } for ( Function * F : FuncsToClone ) { ValueToValueMapTy VMap ; Function * NewFunc = CloneFunction ( F , VMap , false ) ; NewFunc -> setLinkage ( GlobalValue :: InternalLinkage ) ; M . getFunctionList ( ) . push_back ( NewFunc ) ; F -> replaceAllUsesWith ( NewFunc ) ; } for ( Function & F : M ) { if ( F . hasLocalLinkage ( ) && ! F . hasFnAttribute ( Attribute :: NoInline ) ) { F . addFnAttr ( Attribute :: AlwaysInline ) ; } } return false ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> bool NyuziFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> static bool expand_vec_perm_pblendv ( struct expand_vec_perm_d * d ) { unsigned i , which , nelt = d -> nelt ; struct expand_vec_perm_d dcopy , dcopy1 ; machine_mode vmode = d -> vmode ; bool ok ; if ( d -> one_operand_p ) return false ; if ( TARGET_AVX2 && GET_MODE_SIZE ( vmode ) == 32 ) ; else if ( TARGET_AVX && ( vmode == V4DFmode || vmode == V8SFmode ) ) ; else if ( TARGET_SSE4_1 && ( GET_MODE_SIZE ( vmode ) == 4 || GET_MODE_SIZE ( vmode ) == 8 || GET_MODE_SIZE ( vmode ) == 16 ) ) ; else return false ; for ( i = 0 , which = 0 ; i < nelt ; ++ i ) { unsigned e = d -> perm [ i ] ; if ( e != i ) which |= ( e < nelt ? 1 : 2 ) ; } if ( which != 1 && which != 2 ) return false ; if ( d -> testing_p && GET_MODE_SIZE ( vmode ) == 16 ) return true ; dcopy = * d ; if ( which == 2 ) dcopy . op0 = dcopy . op1 = d -> op1 ; else dcopy . op0 = dcopy . op1 = d -> op0 ; if ( ! d -> testing_p ) dcopy . target = gen_reg_rtx ( vmode ) ; dcopy . one_operand_p = true ; for ( i = 0 ; i < nelt ; ++ i ) dcopy . perm [ i ] = d -> perm [ i ] & ( nelt - 1 ) ; ok = expand_vec_perm_1 ( & dcopy ) ; if ( GET_MODE_SIZE ( vmode ) != 16 && ! ok ) return false ; else gcc_assert ( ok ) ; if ( d -> testing_p ) return true ; dcopy1 = * d ; if ( which == 2 ) dcopy1 . op1 = dcopy . target ; else dcopy1 . op0 = dcopy . target ; for ( i = 0 ; i < nelt ; ++ i ) dcopy1 . perm [ i ] = ( ( d -> perm [ i ] >= nelt ) ? ( nelt + i ) : i ) ; ok = expand_vec_perm_blend ( & dcopy1 ) ; gcc_assert ( ok ) ; return true ; } </s>

A subroutine of ix86_expand_vec_perm_const_1 . Try to simplify the permutation using the SSE4_1 pblendv instruction . Potentially reduces permutation from 2 pshufb and or to 1 pshufb and pblendv .


"-mshared-library-id=%s is not between 0 and %d"


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addRequiredID ( LoopSimplifyID ) ; AU . addRequiredID ( LCSSAID ) ; AU . addRequired < AAResultsWrapperPass > ( ) ; AU . addRequired < ScalarEvolutionWrapperPass > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addRequired < TargetLibraryInfoWrapperPass > ( ) ; AU . addPreserved < TargetLibraryInfoWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static void arm_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain_value ) { rtx fnaddr , mem , a_tramp ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ; if ( TARGET_FDPIC ) { rtx funcdesc = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx fnaddr = gen_rtx_MEM ( Pmode , funcdesc ) ; rtx gotaddr = gen_rtx_MEM ( Pmode , plus_constant ( Pmode , funcdesc , 4 ) ) ; rtx trampoline_code_start = plus_constant ( Pmode , XEXP ( m_tramp , 0 ) , TARGET_THUMB2 ? 9 : 8 ) ; mem = adjust_address ( m_tramp , SImode , 0 ) ; emit_move_insn ( mem , trampoline_code_start ) ; mem = adjust_address ( m_tramp , SImode , 4 ) ; emit_move_insn ( mem , gen_rtx_REG ( Pmode , PIC_OFFSET_TABLE_REGNUM ) ) ; mem = adjust_address ( m_tramp , SImode , 20 ) ; emit_move_insn ( mem , chain_value ) ; mem = adjust_address ( m_tramp , SImode , 24 ) ; emit_move_insn ( mem , gotaddr ) ; mem = adjust_address ( m_tramp , SImode , 28 ) ; emit_move_insn ( mem , fnaddr ) ; } else { mem = adjust_address ( m_tramp , SImode , TARGET_32BIT ? 8 : 12 ) ; emit_move_insn ( mem , chain_value ) ; mem = adjust_address ( m_tramp , SImode , TARGET_32BIT ? 12 : 16 ) ; fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; emit_move_insn ( mem , fnaddr ) ; } a_tramp = XEXP ( m_tramp , 0 ) ; maybe_emit_call_builtin___clear_cache ( a_tramp , plus_constant ( ptr_mode , a_tramp , TRAMPOLINE_SIZE ) ) ; } </s>

Emit RTL insns to initialize the variable parts of a trampoline .


<s> bool BlackfinRegisterInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return DisableFramePointerElim ( MF ) || MFI -> adjustsStack ( ) || MFI -> hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static bool mips_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { if ( GET_MODE_SIZE ( from ) == 8 && GET_MODE_SIZE ( to ) == 8 && INTEGRAL_MODE_P ( from ) && INTEGRAL_MODE_P ( to ) ) return true ; if ( MSA_SUPPORTED_MODE_P ( from ) && MSA_SUPPORTED_MODE_P ( to ) ) return true ; return ! reg_classes_intersect_p ( FP_REGS , rclass ) ; } </s>


<s> enum reg_class secondary_output_reload_class ( enum reg_class class , enum machine_mode mode , rtx x ) { return secondary_input_reload_class ( class , mode , x ) ; } </s>

Like secondary_input_reload_class ; and all we do is call that function .


<s> bool nds32_n13_load_to_e1_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx def_reg = SET_DEST ( PATTERN ( producer ) ) ; gcc_assert ( get_attr_type ( producer ) == TYPE_LOAD ) ; gcc_assert ( REG_P ( def_reg ) || GET_CODE ( def_reg ) == SUBREG ) ; return n13_consumed_by_e1_dep_p ( consumer , def_reg ) ; } </s>

Check dependencies from Load-Store Unit ( E3 ) to E1 .


<s> const SDValue & getMask ( ) const { return getOperand ( 2 ) ; } </s>


<s> bool PPCInstrInfo :: getMemOperandWithOffsetWidth ( const MachineInstr & LdSt , const MachineOperand * & BaseReg , int64_t & Offset , unsigned & Width , const TargetRegisterInfo * TRI ) const { if ( ! LdSt . mayLoadOrStore ( ) ) return false ; if ( LdSt . getNumExplicitOperands ( ) != 3 ) return false ; if ( ! LdSt . getOperand ( 1 ) . isImm ( ) || ( ! LdSt . getOperand ( 2 ) . isReg ( ) && ! LdSt . getOperand ( 2 ) . isFI ( ) ) ) return false ; if ( ! LdSt . hasOneMemOperand ( ) ) return false ; Width = ( * LdSt . memoperands_begin ( ) ) -> getSize ( ) ; Offset = LdSt . getOperand ( 1 ) . getImm ( ) ; BaseReg = & LdSt . getOperand ( 2 ) ; return true ; } </s>

Return true if get the base operand , byte offset of an instruction and the memory width .


<s> bool SPIRVCallLowering :: lowerCall ( MachineIRBuilder & MIRBuilder , CallLoweringInfo & Info ) const { if ( Info . OrigRet . Regs . size ( ) > 1 ) return false ; Register ResVReg = Info . OrigRet . Regs . empty ( ) ? Register ( 0 ) : Info . OrigRet . Regs [ 0 ] ; if ( Info . Callee . isGlobal ( ) ) { auto * CF = dyn_cast_or_null < const Function > ( Info . Callee . getGlobal ( ) ) ; if ( CF == nullptr ) return false ; if ( CF -> isDeclaration ( ) ) { MachineBasicBlock :: iterator OldII = MIRBuilder . getInsertPt ( ) ; MachineBasicBlock & OldBB = MIRBuilder . getMBB ( ) ; MachineBasicBlock & FirstBB = * MIRBuilder . getMF ( ) . getBlockNumbered ( 0 ) ; MIRBuilder . setInsertPt ( FirstBB , FirstBB . instr_end ( ) ) ; SmallVector < ArrayRef < Register > , 8 > VRegArgs ; SmallVector < SmallVector < Register , 1 > , 8 > ToInsert ; for ( const Argument & Arg : CF -> args ( ) ) { if ( MIRBuilder . getDataLayout ( ) . getTypeStoreSize ( Arg . getType ( ) ) . isZero ( ) ) continue ; ToInsert . push_back ( { MIRBuilder . getMRI ( ) -> createGenericVirtualRegister ( LLT :: scalar ( 32 ) ) } ) ; VRegArgs . push_back ( ToInsert . back ( ) ) ; } FunctionLoweringInfo FuncInfo ; lowerFormalArguments ( MIRBuilder , * CF , VRegArgs , FuncInfo ) ; MIRBuilder . setInsertPt ( OldBB , OldII ) ; } } if ( ! ResVReg . isValid ( ) ) { ResVReg = MIRBuilder . getMRI ( ) -> createVirtualRegister ( & SPIRV :: IDRegClass ) ; } SPIRVType * RetType = GR -> assignTypeToVReg ( Info . OrigRet . Ty , ResVReg , MIRBuilder ) ; auto MIB = MIRBuilder . buildInstr ( SPIRV :: OpFunctionCall ) . addDef ( ResVReg ) . addUse ( GR -> getSPIRVTypeID ( RetType ) ) . add ( Info . Callee ) ; for ( const auto & Arg : Info . OrigArgs ) { if ( Arg . Regs . size ( ) > 1 ) return false ; MIB . addUse ( Arg . Regs [ 0 ] ) ; } return MIB . constrainAllUses ( MIRBuilder . getTII ( ) , * ST . getRegisterInfo ( ) , * ST . getRegBankInfo ( ) ) ; } </s>

This hook must be implemented to lower the given call instruction , including argument and return value marshalling .


<s> MachineInstrBuilder R600InstrInfo :: buildIndirectWrite ( MachineBasicBlock * MBB , MachineBasicBlock :: iterator I , unsigned ValueReg , unsigned Address , unsigned OffsetReg ) const { unsigned AddrReg = AMDGPU :: R600_AddrRegClass . getRegister ( Address ) ; MachineInstr * MOVA = buildDefaultInstruction ( * MBB , I , AMDGPU :: MOVA_INT_eg , AMDGPU :: AR_X , OffsetReg ) ; setImmOperand ( MOVA , AMDGPU :: OpName :: write , 0 ) ; MachineInstrBuilder Mov = buildDefaultInstruction ( * MBB , I , AMDGPU :: MOV , AddrReg , ValueReg ) . addReg ( AMDGPU :: AR_X , RegState :: Implicit | RegState :: Kill ) ; setImmOperand ( Mov , AMDGPU :: OpName :: dst_rel , 1 ) ; return Mov ; } </s>

Build instruction ( s ) for an indirect register write .


<s> void reset ( ) override { static_cast < RISCVTargetStreamer * > ( getTargetStreamer ( ) ) -> reset ( ) ; MCELFStreamer :: reset ( ) ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s> int avx_vpermilp_parallel ( rtx par , machine_mode mode ) { unsigned i , nelt = GET_MODE_NUNITS ( mode ) ; unsigned mask = 0 ; unsigned char ipar [ 16 ] = { } ; if ( XVECLEN ( par , 0 ) != ( int ) nelt ) return 0 ; for ( i = 0 ; i < nelt ; ++ i ) { rtx er = XVECEXP ( par , 0 , i ) ; unsigned HOST_WIDE_INT ei ; if ( ! CONST_INT_P ( er ) ) return 0 ; ei = INTVAL ( er ) ; if ( ei >= nelt ) return 0 ; ipar [ i ] = ei ; } switch ( mode ) { case V8DFmode : for ( i = 4 ; i < 6 ; ++ i ) { if ( ipar [ i ] < 4 || ipar [ i ] >= 6 ) return 0 ; mask |= ( ipar [ i ] - 4 ) << i ; } for ( i = 6 ; i < 8 ; ++ i ) { if ( ipar [ i ] < 6 ) return 0 ; mask |= ( ipar [ i ] - 6 ) << i ; } case V4DFmode : for ( i = 0 ; i < 2 ; ++ i ) { if ( ipar [ i ] >= 2 ) return 0 ; mask |= ipar [ i ] << i ; } for ( i = 2 ; i < 4 ; ++ i ) { if ( ipar [ i ] < 2 ) return 0 ; mask |= ( ipar [ i ] - 2 ) << i ; } break ; case V16SFmode : for ( i = 0 ; i < 8 ; ++ i ) if ( ipar [ i ] + 8 != ipar [ i + 8 ] ) return 0 ; case V8SFmode : for ( i = 0 ; i < 4 ; ++ i ) if ( ipar [ i ] + 4 != ipar [ i + 4 ] ) return 0 ; nelt = 4 ; case V2DFmode : case V4SFmode : for ( i = 0 ; i < nelt ; ++ i ) mask |= ipar [ i ] << ( i * ( nelt / 2 ) ) ; break ; default : gcc_unreachable ( ) ; } return mask + 1 ; } </s>

Helper for avx_vpermilps256_operand et al . This is also used by the expansion functions to turn the parallel back into a mask . The return value is 0 for no match and the imm8+1 for a match .


<s>
MCSymbol
*
Z80oldMCInstLower
::
GetExternalSymbolSymbol
(
const
MachineOperand
&
MO
)
const
{
assert
(
!
MO
.
getTargetFlags
(
)
&&
"Unknown target flag on GV operand"
)
;
return
AsmPrinter
.
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
;
}
</s>

Return the MCSymbol for the specified ExternalSymbol .


<s> uint64_t HexagonInstrInfo :: getType ( const MachineInstr * MI ) const { const uint64_t F = MI -> getDesc ( ) . TSFlags ; return ( F >> HexagonII :: TypePos ) & HexagonII :: TypeMask ; } </s>

Overload to return most specific vector type .

Hexagon Hexagon HexagonII::TypePos HexagonII::TypeMask


<s> bool isReg ( ) const override { return Kind == Register ; } </s>


<s> bool WebAssemblyAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( Count == 0 ) return true ; for ( uint64_t i = 0 ; i < Count ; ++ i ) OW -> write8 ( WebAssembly :: Nop ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> const char * RISCVTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( RISCVISD :: NodeType ) Opcode ) { case RISCVISD :: FIRST_NUMBER : break ; case RISCVISD :: RET_FLAG : return "RISCVISD::RET_FLAG" ; case RISCVISD :: CALL : return "RISCVISD::CALL" ; case RISCVISD :: SELECT_CC : return "RISCVISD::SELECT_CC" ; case RISCVISD :: BuildPairF64 : return "RISCVISD::BuildPairF64" ; case RISCVISD :: SplitF64 : return "RISCVISD::SplitF64" ; case RISCVISD :: TAIL : return "RISCVISD::TAIL" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> void HexagonPassConfig :: addPreEmitPass ( ) { bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) addPass ( createHexagonNewValueJump ( ) , false ) ; addPass ( createHexagonBranchRelaxation ( ) , false ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( createHexagonFixupHwLoops ( ) , false ) ; if ( EnableGenMux ) addPass ( createHexagonGenMux ( ) , false ) ; addPass ( createHexagonPacketizer ( ) , false ) ; } if ( EnableVectorPrint ) addPass ( createHexagonVectorPrint ( ) , false ) ; addPass ( createHexagonCallFrameInformation ( ) , false ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon


<s> const TargetRegisterClass * SITargetLowering :: getRegClassFor ( MVT VT , bool isDivergent ) const { const TargetRegisterClass * RC = TargetLoweringBase :: getRegClassFor ( VT , false ) ; const SIRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; if ( RC == & AMDGPU :: VReg_1RegClass && ! isDivergent ) return Subtarget -> getWavefrontSize ( ) == 64 ? & AMDGPU :: SReg_64RegClass : & AMDGPU :: SReg_32RegClass ; if ( ! TRI -> isSGPRClass ( RC ) && ! isDivergent ) return TRI -> getEquivalentSGPRClass ( RC ) ; else if ( TRI -> isSGPRClass ( RC ) && isDivergent ) return TRI -> getEquivalentVGPRClass ( RC ) ; return RC ; } </s>

Return the register class that should be used for the specified value type .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == 0 ) Inst . addOperand ( MCOperand :: CreateImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ; } </s>


<s> static bool arm_vectorize_vec_perm_const ( machine_mode vmode , rtx target , rtx op0 , rtx op1 , const vec_perm_indices & sel ) { struct expand_vec_perm_d d ; int i , nelt , which ; if ( ! VALID_NEON_DREG_MODE ( vmode ) && ! VALID_NEON_QREG_MODE ( vmode ) ) return false ; d . target = target ; if ( op0 ) { rtx nop0 = force_reg ( vmode , op0 ) ; if ( op0 == op1 ) op1 = nop0 ; op0 = nop0 ; } if ( op1 ) op1 = force_reg ( vmode , op1 ) ; d . op0 = op0 ; d . op1 = op1 ; d . vmode = vmode ; gcc_assert ( VECTOR_MODE_P ( d . vmode ) ) ; d . testing_p = ! target ; nelt = GET_MODE_NUNITS ( d . vmode ) ; for ( i = which = 0 ; i < nelt ; ++ i ) { int ei = sel [ i ] & ( 2 * nelt - 1 ) ; which |= ( ei < nelt ? 1 : 2 ) ; } switch ( which ) { default : gcc_unreachable ( ) ; case 3 : d . one_vector_p = false ; if ( d . testing_p || ! rtx_equal_p ( op0 , op1 ) ) break ; case 2 : d . op0 = op1 ; d . one_vector_p = true ; break ; case 1 : d . op1 = op0 ; d . one_vector_p = true ; break ; } d . perm . new_vector ( sel . encoding ( ) , d . one_vector_p ? 1 : 2 , nelt ) ; if ( ! d . testing_p ) return arm_expand_vec_perm_const_1 ( & d ) ; d . target = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 1 ) ; d . op1 = d . op0 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 2 ) ; if ( ! d . one_vector_p ) d . op1 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 3 ) ; start_sequence ( ) ; bool ret = arm_expand_vec_perm_const_1 ( & d ) ; end_sequence ( ) ; return ret ; } </s>


<s> static void set_reg_plus_d ( int reg , int base , HOST_WIDE_INT disp , int note ) { rtx_insn * insn ; if ( VAL_14_BITS_P ( disp ) ) { insn = emit_move_insn ( gen_rtx_REG ( Pmode , reg ) , plus_constant ( Pmode , gen_rtx_REG ( Pmode , base ) , disp ) ) ; } else if ( TARGET_64BIT && ! VAL_32_BITS_P ( disp ) ) { rtx basereg = gen_rtx_REG ( Pmode , base ) ; rtx delta = GEN_INT ( disp ) ; rtx tmpreg = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( tmpreg , delta ) ; insn = emit_move_insn ( gen_rtx_REG ( Pmode , reg ) , gen_rtx_PLUS ( Pmode , tmpreg , basereg ) ) ; if ( DO_FRAME_NOTES ) add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , tmpreg , gen_rtx_PLUS ( Pmode , basereg , delta ) ) ) ; } else { rtx basereg = gen_rtx_REG ( Pmode , base ) ; rtx delta = GEN_INT ( disp ) ; rtx tmpreg = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( tmpreg , gen_rtx_PLUS ( Pmode , basereg , gen_rtx_HIGH ( Pmode , delta ) ) ) ; insn = emit_move_insn ( gen_rtx_REG ( Pmode , reg ) , gen_rtx_LO_SUM ( Pmode , tmpreg , delta ) ) ; } if ( DO_FRAME_NOTES && note ) RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Emit RTL to set REG to the value specified by BASE+DISP . Handle case where DISP > 8k by using the add_high_const patterns . Note in DISP > 8k case , we will leave the high part of the address in % r1 . There is code in expand_hppa_ { prologue , epilogue } that knows this .


<s> OperandMatchResultTy AVRAsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { StartLoc = Parser . getTok ( ) . getLoc ( ) ; RegNo = parseRegister ( true ) ; EndLoc = Parser . getTok ( ) . getLoc ( ) ; if ( RegNo == AVR :: NoRegister ) return MatchOperand_NoMatch ; return MatchOperand_Success ; } </s>

tryParseRegister - parse one register if possible


<s> unsigned getNumFixupKinds ( ) const { return 1 ; } </s>

Get the number of target specific fixup kinds .


<s> bool WasmPEI :: runOnMachineFunction ( MachineFunction & Fn ) { const Function * F = Fn . getFunction ( ) ; const TargetRegisterInfo * TRI = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; const TargetFrameLowering * TFI = Fn . getSubtarget ( ) . getFrameLowering ( ) ; RS = TRI -> requiresRegisterScavenging ( Fn ) ? new RegScavenger ( ) : nullptr ; FrameIndexVirtualScavenging = TRI -> requiresFrameIndexScavenging ( Fn ) ; calculateCallsInformation ( Fn ) ; BitVector SavedRegs ; TFI -> determineCalleeSaves ( Fn , SavedRegs , RS ) ; assignCalleeSavedSpillSlots ( Fn , SavedRegs ) ; calculateSets ( Fn ) ; if ( ! F -> hasFnAttribute ( Attribute :: Naked ) ) insertCSRSpillsAndRestores ( Fn ) ; TFI -> processFunctionBeforeFrameFinalized ( Fn , RS ) ; calculateFrameObjectOffsets ( Fn ) ; if ( ! F -> hasFnAttribute ( Attribute :: Naked ) ) insertPrologEpilogCode ( Fn ) ; replaceFrameIndices ( Fn ) ; if ( TRI -> requiresRegisterScavenging ( Fn ) && FrameIndexVirtualScavenging ) { scavengeFrameVirtualRegs ( Fn ) ; Fn . getRegInfo ( ) . clearVirtRegs ( ) ; } MachineFrameInfo * MFI = Fn . getFrameInfo ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( WarnStackSize . getNumOccurrences ( ) > 0 && WarnStackSize < StackSize ) { DiagnosticInfoStackSize DiagStackSize ( * F , StackSize ) ; F -> getContext ( ) . diagnose ( DiagStackSize ) ; } delete RS ; SaveBlocks . clear ( ) ; RestoreBlocks . clear ( ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> void emitTableType ( const MCSymbolWasm * ) override { } </s>


<s> int SIFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const SIRegisterInfo * RI = MF . getSubtarget < GCNSubtarget > ( ) . getRegisterInfo ( ) ; FrameReg = RI -> getFrameRegister ( MF ) ; return MF . getFrameInfo ( ) . getObjectOffset ( FI ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> int HexagonMCInst :: getMinValue ( void ) const { const uint64_t F = getDesc ( ) . TSFlags ; unsigned isSigned = ( F >> HexagonII :: ExtentSignedPos ) & HexagonII :: ExtentSignedMask ; unsigned bits = ( F >> HexagonII :: ExtentBitsPos ) & HexagonII :: ExtentBitsMask ; if ( isSigned ) return - 1U << ( bits - 1 ) ; else return 0 ; } </s>

Return the minimal unsigned value possible given these KnownBits .

Hexagon Hexagon HexagonII::ExtentSignedPos HexagonII::ExtentSignedMask HexagonII::ExtentBitsPos HexagonII::ExtentBitsMask 1U 1 0


<s> static int avr_signal_function_p ( tree func ) { return avr_lookup_function_attribute1 ( func , "signal" ) ; } </s>

Return nonzero if FUNC is a signal function as specified by the `` signal '' attribute .


<s> InstructionCost getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { assert ( Ty -> isIntegerTy ( ) ) ; if ( Imm == 0 ) return TTI :: TCC_Free ; if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Basic ; if ( isInt < 21 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Basic ; if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) { if ( ( Imm . getSExtValue ( ) & 0xFFFF ) == 0 ) return TTI :: TCC_Basic ; return 2 * TTI :: TCC_Basic ; } return 4 * TTI :: TCC_Basic ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> MachineBasicBlock :: iterator VEFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr & MI = * I ; int Size = MI . getOperand ( 0 ) . getImm ( ) ; if ( MI . getOpcode ( ) == VE :: ADJCALLSTACKDOWN ) Size = - Size ; if ( Size ) emitSPAdjustment ( MF , MBB , I , Size ) ; } return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static void nios2_load_pic_register ( void ) { rtx tmp = gen_rtx_REG ( Pmode , TEMP_REG_NUM ) ; emit_insn ( gen_load_got_register ( pic_offset_table_rtx , tmp ) ) ; emit_insn ( gen_add3_insn ( pic_offset_table_rtx , pic_offset_table_rtx , tmp ) ) ; } </s>


<s> static void ia64_free_sched_context ( void * _sc ) { gcc_assert ( _sc != NULL ) ; free ( _sc ) ; } </s>


<s> void unicosmk_add_extern ( const char * name ) { struct unicosmk_extern_list * p ; p = ( struct unicosmk_extern_list * ) xmalloc ( sizeof ( struct unicosmk_extern_list ) ) ; p -> next = unicosmk_extern_head ; p -> name = name ; unicosmk_extern_head = p ; } </s>


<s>
bool
X86CallFrameOptimization
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
STI
=
&
MF
.
getSubtarget
<
X86Subtarget
>
(
)
;
TII
=
STI
->
getInstrInfo
(
)
;
TFL
=
STI
->
getFrameLowering
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
const
X86RegisterInfo
&
RegInfo
=
*
static_cast
<
const
X86RegisterInfo
*
>
(
STI
->
getRegisterInfo
(
)
)
;
SlotSize
=
RegInfo
.
getSlotSize
(
)
;
assert
(
isPowerOf2_32
(
SlotSize
)
&&
"Expect power of 2 stack slot size"
)
;
Log2SlotSize
=
Log2_32
(
SlotSize
)
;
if
(
skipFunction
(
*
MF
.
getFunction
(
)
)
||
!
isLegal
(
MF
)
)
return
false
;
unsigned
FrameSetupOpcode
=
TII
->
getCallFrameSetupOpcode
(
)
;
bool
Changed
=
false
;
ContextVector
CallSeqVector
;
for
(
auto
&
MBB
:
MF
)
for
(
auto
&
MI
:
MBB
)
if
(
MI
.
getOpcode
(
)
==
FrameSetupOpcode
)
{
CallContext
Context
;
collectCallInfo
(
MF
,
MBB
,
MI
,
Context
)
;
CallSeqVector
.
push_back
(
Context
)
;
}
if
(
!
isProfitable
(
MF
,
CallSeqVector
)
)
return
false
;
for
(
auto
CC
:
CallSeqVector
)
{
if
(
CC
.
UsePush
)
{
adjustCallSequence
(
MF
,
CC
)
;
Changed
=
true
;
}
}
return
Changed
;
}
</s>


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> virtual bool check ( function_checker & ) const { return true ; } </s>

Perform semantic checks on the call . Return true if the call is valid , otherwise report a suitable error .


<s>
static
void
seh_cfa_adjust_cfa
(
FILE
*
f
,
struct
seh_frame_state
*
seh
,
rtx
pat
)
{
rtx
dest
,
src
;
HOST_WIDE_INT
reg_offset
=
0
;
unsigned
int
dest_regno
;
dest
=
SET_DEST
(
pat
)
;
src
=
SET_SRC
(
pat
)
;
if
(
GET_CODE
(
src
)
==
PLUS
)
{
reg_offset
=
INTVAL
(
XEXP
(
src
,
1
)
)
;
src
=
XEXP
(
src
,
0
)
;
}
else
if
(
GET_CODE
(
src
)
==
MINUS
)
{
reg_offset
=
INTVAL
(
XEXP
(
src
,
1
)
)
;
src
=
XEXP
(
src
,
0
)
;
}
gcc_assert
(
src
==
stack_pointer_rtx
)
;
gcc_assert
(
seh
->
cfa_reg
==
stack_pointer_rtx
)
;
dest_regno
=
REGNO
(
dest
)
;
if
(
dest_regno
==
STACK_POINTER_REGNUM
)
seh_emit_stackalloc
(
f
,
seh
,
reg_offset
)
;
else
if
(
dest_regno
==
HARD_FRAME_POINTER_REGNUM
)
{
HOST_WIDE_INT
offset
;
seh
->
cfa_reg
=
dest
;
seh
->
cfa_offset
-=
reg_offset
;
offset
=
seh
->
sp_offset
seh
->
cfa_offset
;
gcc_assert
(
(
offset
&
15
)
==
0
)
;
gcc_assert
(
IN_RANGE
(
offset
,
0
,
240
)
)
;
fputs
(
"\t.seh_setframe\t"
,
f
)
;
print_reg
(
seh
->
cfa_reg
,
0
,
f
)
;
fprintf
(
f
,
", "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
offset
)
;
}
else
gcc_unreachable
(
)
;
}
</s>


<s> static void moxie_compute_frame ( void ) { int stack_alignment = STACK_BOUNDARY / BITS_PER_UNIT ; int padding_locals ; int regno ; cfun -> machine -> local_vars_size = get_frame_size ( ) ; padding_locals = cfun -> machine -> local_vars_size % stack_alignment ; if ( padding_locals ) padding_locals = stack_alignment - padding_locals ; cfun -> machine -> local_vars_size += padding_locals ; cfun -> machine -> callee_saved_reg_size = 0 ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ( ! call_used_regs [ regno ] ) ) cfun -> machine -> callee_saved_reg_size += 4 ; cfun -> machine -> size_for_adjusting_sp = crtl -> args . pretend_args_size + cfun -> machine -> local_vars_size + ( ACCUMULATE_OUTGOING_ARGS ? ( HOST_WIDE_INT ) crtl -> outgoing_args_size : 0 ) ; } </s>

Compute the size of the local area and the size to be adjusted by the * prologue and epilogue .


<s> BitVector MipsRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t ReservedGPR32 [ ] = { Mips :: ZERO , Mips :: K0 , Mips :: K1 , Mips :: SP } ; static const uint16_t ReservedGPR64 [ ] = { Mips :: ZERO_64 , Mips :: K0_64 , Mips :: K1_64 , Mips :: SP_64 } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: const_iterator RegIter ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedGPR32 ) ; ++ I ) Reserved . set ( ReservedGPR32 [ I ] ) ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedGPR64 ) ; ++ I ) Reserved . set ( ReservedGPR64 [ I ] ) ; if ( Subtarget . hasMips64 ( ) ) { for ( RegIter Reg = Mips :: AFGR64RegClass . begin ( ) , EReg = Mips :: AFGR64RegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } else { for ( RegIter Reg = Mips :: FGR64RegClass . begin ( ) , EReg = Mips :: FGR64RegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) ) { if ( Subtarget . inMips16Mode ( ) ) Reserved . set ( Mips :: S0 ) ; else { Reserved . set ( Mips :: FP ) ; Reserved . set ( Mips :: FP_64 ) ; } } Reserved . set ( Mips :: HWR29 ) ; Reserved . set ( Mips :: HWR29_64 ) ; Reserved . set ( Mips :: DSPPos ) ; Reserved . set ( Mips :: DSPSCount ) ; Reserved . set ( Mips :: DSPCarry ) ; Reserved . set ( Mips :: DSPEFI ) ; Reserved . set ( Mips :: DSPOutFlag ) ; if ( Subtarget . inMips16Mode ( ) ) { Reserved . set ( Mips :: RA ) ; Reserved . set ( Mips :: RA_64 ) ; Reserved . set ( Mips :: T0 ) ; Reserved . set ( Mips :: T1 ) ; } if ( Subtarget . useSmallSection ( ) ) { Reserved . set ( Mips :: GP ) ; Reserved . set ( Mips :: GP_64 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static int ix86_reassociation_width ( unsigned int , machine_mode mode ) { if ( VECTOR_MODE_P ( mode ) ) { if ( TARGET_VECTOR_PARALLEL_EXECUTION ) return 2 ; else return 1 ; } if ( INTEGRAL_MODE_P ( mode ) && TARGET_REASSOC_INT_TO_PARALLEL ) return 2 ; else if ( FLOAT_MODE_P ( mode ) && TARGET_REASSOC_FP_TO_PARALLEL ) return 2 ; else return 1 ; } </s>

Implementation of reassociation_width target hook used by reassoc phase to identify parallelism level in reassociated tree . Statements tree_code is passed in OPC . Arguments type is passed in MODE . Currently parallel reassociation is enabled for Atom processors only and we set reassociation width to be 2 because Atom may issue up to 2 instructions per cycle . Return value should be fixed if parallel reassociation is enabled for other processors .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; AVRMachineFunctionInfo * AFI = MF . getInfo < AVRMachineFunctionInfo > ( ) ; if ( MFI . getNumObjects ( ) != MFI . getNumFixedObjects ( ) ) { for ( unsigned i = 0 , e = MFI . getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( MFI . getObjectSize ( i ) ) { AFI -> setHasAllocas ( true ) ; break ; } } } if ( MFI . getNumFixedObjects ( ) == 0 ) { return false ; } for ( const MachineBasicBlock & BB : MF ) { for ( const MachineInstr & MI : BB ) { int Opcode = MI . getOpcode ( ) ; if ( ( Opcode != AVR :: LDDRdPtrQ ) && ( Opcode != AVR :: LDDWRdPtrQ ) && ( Opcode != AVR :: STDPtrQRr ) && ( Opcode != AVR :: STDWPtrQRr ) ) { continue ; } for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isFI ( ) ) { continue ; } if ( MFI . isFixedObjectIndex ( MO . getIndex ( ) ) ) { AFI -> setHasStackArgs ( true ) ; return false ; } } } } return false ; } </s>

AVR AVR AVR 0 0 AVR::LDDRdPtrQ AVR::LDDWRdPtrQ AVR::STDPtrQRr AVR::STDWPtrQRr


<s> bool BTFDebug :: InstLower ( const MachineInstr * MI , MCInst & OutMI ) { if ( MI -> getOpcode ( ) == BPF :: LD_imm64 ) { const MachineOperand & MO = MI -> getOperand ( 1 ) ; if ( MO . isGlobal ( ) ) { const GlobalValue * GVal = MO . getGlobal ( ) ; auto * GVar = dyn_cast < GlobalVariable > ( GVal ) ; if ( GVar && GVar -> hasAttribute ( BPFCoreSharedInfo :: AmaAttr ) ) { uint32_t Imm = PatchImms [ GVar -> getName ( ) . str ( ) ] ; OutMI . setOpcode ( BPF :: MOV_ri ) ; OutMI . addOperand ( MCOperand :: createReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ) ; OutMI . addOperand ( MCOperand :: createImm ( Imm ) ) ; return true ; } else if ( GVar && ! GVar -> hasInitializer ( ) && GVar -> hasExternalLinkage ( ) && GVar -> getSection ( ) == BPFCoreSharedInfo :: PatchableExtSecName ) { const IntegerType * IntTy = dyn_cast < IntegerType > ( GVar -> getValueType ( ) ) ; assert ( IntTy ) ; if ( IntTy -> getBitWidth ( ) == 64 ) OutMI . setOpcode ( BPF :: LD_imm64 ) ; else OutMI . setOpcode ( BPF :: MOV_ri ) ; OutMI . addOperand ( MCOperand :: createReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ) ; OutMI . addOperand ( MCOperand :: createImm ( 0 ) ) ; return true ; } } } return false ; } </s>


<s> unsigned getExceptionPointerRegister ( const Constant * PersonalityFn ) const override { return SystemZ :: R6D ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s> void HexagonSubtarget :: adjustSchedDependency ( SUnit * Src , SUnit * Dst , SDep & Dep ) const { MachineInstr * SrcInst = Src -> getInstr ( ) ; MachineInstr * DstInst = Dst -> getInstr ( ) ; if ( ! Src -> isInstr ( ) || ! Dst -> isInstr ( ) ) return ; const HexagonInstrInfo * QII = static_cast < const HexagonInstrInfo * > ( getInstrInfo ( ) ) ; if ( QII -> canExecuteInBundle ( SrcInst , DstInst ) && isBestZeroLatency ( Src , Dst , QII ) ) { Dep . setLatency ( 0 ) ; return ; } if ( ! hasV60TOps ( ) ) return ; if ( QII -> isPostIncrement ( SrcInst ) && Dep . isAssignedRegDep ( ) ) { if ( SrcInst -> mayStore ( ) ) return ; if ( Dep . getReg ( ) != SrcInst -> getOperand ( 0 ) . getReg ( ) ) return ; } else if ( QII -> isPostIncrement ( DstInst ) && Dep . getKind ( ) == SDep :: Anti ) { if ( DstInst -> mayStore ( ) ) return ; if ( Dep . getReg ( ) != DstInst -> getOperand ( 0 ) . getReg ( ) ) return ; } else if ( QII -> isPostIncrement ( DstInst ) && DstInst -> mayStore ( ) && Dep . isAssignedRegDep ( ) ) { MachineOperand & Op = DstInst -> getOperand ( DstInst -> getNumOperands ( ) - 1 ) ; if ( Op . isReg ( ) && Dep . getReg ( ) != Op . getReg ( ) ) return ; } if ( useBSBScheduling ( ) && SrcInst -> isPHI ( ) ) { changePhiLatency ( SrcInst , Dst , Dep ) ; return ; } if ( DstInst -> isRegSequence ( ) && Dst -> NumSuccs == 1 ) DstInst = Dst -> Succs [ 0 ] . getSUnit ( ) -> getInstr ( ) ; if ( EnableDotCurSched && QII -> isToBeScheduledASAP ( SrcInst , DstInst ) && isBestZeroLatency ( Src , Dst , QII ) ) { Dep . setLatency ( 0 ) ; return ; } updateLatency ( SrcInst , DstInst , Dep ) ; } </s>

Perform target specific adjustments to the latency of a schedule dependency .


"Do not know how to custom type legalize this operation!"

"Unexpected result type for CTR decrement intrinsic"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> static void h8300_print_operand_address ( FILE * file , machine_mode mode , rtx addr ) { rtx index ; int size ; switch ( GET_CODE ( addr ) ) { case REG : fprintf ( file , "%s" , h8_reg_names [ REGNO ( addr ) ] ) ; break ; case PRE_DEC : fprintf ( file , "-%s" , h8_reg_names [ REGNO ( XEXP ( addr , 0 ) ) ] ) ; break ; case POST_INC : fprintf ( file , "%s+" , h8_reg_names [ REGNO ( XEXP ( addr , 0 ) ) ] ) ; break ; case PRE_INC : fprintf ( file , "+%s" , h8_reg_names [ REGNO ( XEXP ( addr , 0 ) ) ] ) ; break ; case POST_DEC : fprintf ( file , "%s-" , h8_reg_names [ REGNO ( XEXP ( addr , 0 ) ) ] ) ; break ; case PLUS : fprintf ( file , "(" ) ; index = h8300_get_index ( XEXP ( addr , 0 ) , VOIDmode , & size ) ; if ( GET_CODE ( index ) == REG ) { h8300_print_operand_address ( file , mode , XEXP ( addr , 1 ) ) ; fprintf ( file , "," ) ; switch ( size ) { case 0 : h8300_print_operand_address ( file , mode , index ) ; break ; case 1 : h8300_print_operand ( file , index , 'X' ) ; fputs ( ".b" , file ) ; break ; case 2 : h8300_print_operand ( file , index , 'T' ) ; fputs ( ".w" , file ) ; break ; case 4 : h8300_print_operand ( file , index , 'S' ) ; fputs ( ".l" , file ) ; break ; } } else { h8300_print_operand_address ( file , mode , XEXP ( addr , 0 ) ) ; fprintf ( file , "+" ) ; h8300_print_operand_address ( file , mode , XEXP ( addr , 1 ) ) ; } fprintf ( file , ")" ) ; break ; case CONST_INT : { int n = INTVAL ( addr ) ; fprintf ( file , "%d" , n ) ; break ; } default : output_addr_const ( file , addr ) ; break ; } } </s>

Output assembly language output for the address ADDR to FILE .


<s> bool ShouldShrinkFPConstant ( EVT ) const override { return false ; } </s>

If true , then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime .


"internal error: %<cris_side_effect_mode_ok%> with bad operands"

Check various objections to the side-effect . Used in the test-part of an anonymous insn describing an insn with a possible side-effect . Returns nonzero if the implied side-effect is ok. code : PLUS or MULT ops : An array of rtx : es . lreg , rreg , rval , The variables multop and other_op are indexes into this , or -1 if they are not applicable . lreg : The register that gets assigned in the side-effect . rreg : One register in the side-effect expression rval : The other register , or an int . multop : An integer to multiply rval with . other_op : One of the entities of the main effect , whose mode we must consider .


<s> SDValue AArch64TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : case ISD :: SUB : return performAddSubLongCombine ( N , DCI , DAG ) ; case ISD :: XOR : return performXorCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: MUL : return performMulCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SINT_TO_FP : case ISD :: UINT_TO_FP : return performIntToFpCombine ( N , DAG , Subtarget ) ; case ISD :: OR : return performORCombine ( N , DCI , Subtarget ) ; case ISD :: INTRINSIC_WO_CHAIN : return performIntrinsicCombine ( N , DCI , Subtarget ) ; case ISD :: ANY_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: SIGN_EXTEND : return performExtendCombine ( N , DCI , DAG ) ; case ISD :: BITCAST : return performBitcastCombine ( N , DCI , DAG ) ; case ISD :: CONCAT_VECTORS : return performConcatVectorsCombine ( N , DCI , DAG ) ; case ISD :: SELECT : return performSelectCombine ( N , DCI ) ; case ISD :: VSELECT : return performVSelectCombine ( N , DCI . DAG ) ; case ISD :: STORE : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case AArch64ISD :: BRCOND : return performBRCONDCombine ( N , DCI , DAG ) ; case AArch64ISD :: CSEL : return performCONDCombine ( N , DCI , DAG , 2 , 3 ) ; case AArch64ISD :: DUP : return performPostLD1Combine ( N , DCI , false ) ; case AArch64ISD :: NVCAST : return performNVCASTCombine ( N ) ; case ISD :: INSERT_VECTOR_ELT : return performPostLD1Combine ( N , DCI , true ) ; case ISD :: EXTRACT_VECTOR_ELT : return performAcrossLaneReductionCombine ( N , DAG , Subtarget ) ; case ISD :: INTRINSIC_VOID : case ISD :: INTRINSIC_W_CHAIN : switch ( cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) -> getZExtValue ( ) ) { case Intrinsic :: aarch64_neon_ld2 : case Intrinsic :: aarch64_neon_ld3 : case Intrinsic :: aarch64_neon_ld4 : case Intrinsic :: aarch64_neon_ld1x2 : case Intrinsic :: aarch64_neon_ld1x3 : case Intrinsic :: aarch64_neon_ld1x4 : case Intrinsic :: aarch64_neon_ld2lane : case Intrinsic :: aarch64_neon_ld3lane : case Intrinsic :: aarch64_neon_ld4lane : case Intrinsic :: aarch64_neon_ld2r : case Intrinsic :: aarch64_neon_ld3r : case Intrinsic :: aarch64_neon_ld4r : case Intrinsic :: aarch64_neon_st2 : case Intrinsic :: aarch64_neon_st3 : case Intrinsic :: aarch64_neon_st4 : case Intrinsic :: aarch64_neon_st1x2 : case Intrinsic :: aarch64_neon_st1x3 : case Intrinsic :: aarch64_neon_st1x4 : case Intrinsic :: aarch64_neon_st2lane : case Intrinsic :: aarch64_neon_st3lane : case Intrinsic :: aarch64_neon_st4lane : return performNEONPostLDSTCombine ( N , DCI , DAG ) ; default : break ; } } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> int use_return_insn ( int iscond , rtx sibling ) { int regno ; unsigned int func_type ; unsigned long saved_int_regs ; unsigned HOST_WIDE_INT stack_adjust ; arm_stack_offsets * offsets ; if ( ! reload_completed ) return 0 ; func_type = arm_current_func_type ( ) ; if ( func_type & ( ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN ) ) return 0 ; if ( IS_INTERRUPT ( func_type ) && ( frame_pointer_needed || TARGET_THUMB ) ) return 0 ; if ( TARGET_LDRD && current_tune -> prefer_ldrd_strd && ! optimize_function_for_size_p ( cfun ) ) return 0 ; offsets = arm_get_frame_offsets ( ) ; stack_adjust = offsets -> outgoing_args - offsets -> saved_regs ; if ( crtl -> args . pretend_args_size || cfun -> machine -> uses_anonymous_args || crtl -> calls_eh_return || cfun -> calls_alloca || ! ( stack_adjust == 0 || ( TARGET_APCS_FRAME && frame_pointer_needed && stack_adjust == 4 ) ) ) return 0 ; saved_int_regs = offsets -> saved_regs_mask ; if ( stack_adjust == 4 && ! arm_arch5 && TARGET_ARM ) { if ( ! call_used_regs [ 3 ] ) return 0 ; if ( arm_size_return_regs ( ) >= ( 4 * UNITS_PER_WORD ) ) return 0 ; if ( sibling ) { gcc_assert ( CALL_P ( sibling ) ) ; if ( find_regno_fusage ( sibling , USE , 3 ) ) return 0 ; } if ( saved_int_regs & 0x7 ) return 0 ; } if ( TARGET_INTERWORK && saved_int_regs != 0 && ! IS_INTERRUPT ( func_type ) ) return 0 ; if ( iscond && arm_tune_strongarm ) { if ( saved_int_regs != 0 && saved_int_regs != ( 1 << LR_REGNUM ) ) return 0 ; if ( flag_pic && arm_pic_register != INVALID_REGNUM && df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) ) return 0 ; } if ( saved_int_regs && ! ( saved_int_regs & ( 1 << LR_REGNUM ) ) ) return 0 ; if ( TARGET_HARD_FLOAT && TARGET_VFP ) for ( regno = FIRST_VFP_REGNUM ; regno <= LAST_VFP_REGNUM ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) return 0 ; if ( TARGET_REALLY_IWMMXT ) for ( regno = FIRST_IWMMXT_REGNUM ; regno <= LAST_IWMMXT_REGNUM ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) return 0 ; return 1 ; } </s>

Return true if this function 's epilogue can be output as RTL .


<s>
static
void
adjust_xxpermdi
(
rtx_insn
*
insn
)
{
rtx
set
=
PATTERN
(
insn
)
;
rtx
select
=
XEXP
(
set
,
1
)
;
rtx
concat
=
XEXP
(
select
,
0
)
;
rtx
src0
=
XEXP
(
concat
,
0
)
;
XEXP
(
concat
,
0
)
=
XEXP
(
concat
,
1
)
;
XEXP
(
concat
,
1
)
=
src0
;
rtx
parallel
=
XEXP
(
select
,
1
)
;
int
lane0
=
INTVAL
(
XVECEXP
(
parallel
,
0
,
0
)
)
;
int
lane1
=
INTVAL
(
XVECEXP
(
parallel
,
0
,
1
)
)
;
int
new_lane0
=
3
lane1
;
int
new_lane1
=
3
lane0
;
XVECEXP
(
parallel
,
0
,
0
)
=
GEN_INT
(
new_lane0
)
;
XVECEXP
(
parallel
,
0
,
1
)
=
GEN_INT
(
new_lane1
)
;
INSN_CODE
(
insn
)
=
1
;
df_insn_rescan
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Changing lanes for xxpermdi %d\n"
,
INSN_UID
(
insn
)
)
;
}
</s>

Given OP that contains an XXPERMDI operation ( that is not a doubleword swap ) , reverse the order of the source operands and adjust the indices of the source lanes to account for doubleword reversal .


<s>
const
char
*
LC3bAsmPrinter
::
getCurrentABIString
(
)
const
{
llvm_unreachable
(
"Unknown LC3b ABI"
)
;
;
}
</s>


<s> static bool legitimate_scaled_address_p ( machine_mode mode , rtx op , bool strict ) { if ( GET_CODE ( op ) != PLUS ) return false ; if ( GET_CODE ( XEXP ( op , 0 ) ) != MULT ) return false ; if ( ! RTX_OK_FOR_INDEX_P ( XEXP ( XEXP ( op , 0 ) , 0 ) , strict ) ) return false ; if ( ! CONST_INT_P ( XEXP ( XEXP ( op , 0 ) , 1 ) ) ) return false ; switch ( GET_MODE_SIZE ( mode ) ) { case 2 : if ( INTVAL ( XEXP ( XEXP ( op , 0 ) , 1 ) ) != 2 ) return false ; break ; case 8 : if ( ! TARGET_LL64 ) return false ; case 4 : if ( INTVAL ( XEXP ( XEXP ( op , 0 ) , 1 ) ) != 4 ) return false ; default : return false ; } if ( RTX_OK_FOR_BASE_P ( XEXP ( op , 1 ) , ( strict ) ) ) return true ; if ( flag_pic ) { if ( CONST_INT_P ( XEXP ( op , 1 ) ) ) return true ; return false ; } if ( legitimate_small_data_address_p ( op ) ) return false ; if ( CONSTANT_P ( XEXP ( op , 1 ) ) ) return true ; return false ; } </s>


"ReadCycleWrite is only to be used on riscv32"

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> void addBlock ( MachineBasicBlock * MBB ) { Blocks . push_back ( MBB ) ; BlockSet . insert ( MBB ) ; } </s>


<s> const SparcSubtarget * SparcTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool softFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsBool ( ) ; if ( softFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < SparcSubtarget > ( TargetTriple , CPU , FS , * this , this -> is64Bit ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

Sparc Sparc Sparc "target-cpu" "target-features" "use-soft-float" "+soft-float" ",+soft-float" Sparc


<s>
StringRef
getPassName
(
)
const
override
{
return
"AGC Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool M68kOperand :: isImm ( ) const { return Kind == Kind :: Imm ; } </s>


Return 1 if X is all 0s and 2 if x is all 1s in supported SSE/AVX vector mode .


<s> bool BlackfinIntrinsicInfo :: isOverloaded ( unsigned IntrID ) const { const bool OTable [ ] = { } ; if ( IntrID == 0 ) return false ; else return OTable [ IntrID - Intrinsic :: num_intrinsics ] ; } </s>

Returns true if the intrinsic can be overloaded .


<s>
SDValue
AMDGPUTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
Op
->
dump
(
&
DAG
)
;
llvm_unreachable
(
"Custom lowering code for this"
"instruction is not implemented yet!"
)
;
break
;
case
ISD
::
SIGN_EXTEND_INREG
:
return
LowerSIGN_EXTEND_INREG
(
Op
,
DAG
)
;
case
ISD
::
CONCAT_VECTORS
:
return
LowerCONCAT_VECTORS
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_SUBVECTOR
:
return
LowerEXTRACT_SUBVECTOR
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
UDIVREM
:
return
LowerUDIVREM
(
Op
,
DAG
)
;
case
ISD
::
SDIVREM
:
return
LowerSDIVREM
(
Op
,
DAG
)
;
case
ISD
::
FREM
:
return
LowerFREM
(
Op
,
DAG
)
;
case
ISD
::
FCEIL
:
return
LowerFCEIL
(
Op
,
DAG
)
;
case
ISD
::
FTRUNC
:
return
LowerFTRUNC
(
Op
,
DAG
)
;
case
ISD
::
FRINT
:
return
LowerFRINT
(
Op
,
DAG
)
;
case
ISD
::
FNEARBYINT
:
return
LowerFNEARBYINT
(
Op
,
DAG
)
;
case
ISD
::
FROUND
:
return
LowerFROUND
(
Op
,
DAG
)
;
case
ISD
::
FFLOOR
:
return
LowerFFLOOR
(
Op
,
DAG
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerSINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
UINT_TO_FP
:
return
LowerUINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_SINT
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_UINT
(
Op
,
DAG
)
;
case
ISD
::
CTLZ
:
case
ISD
::
CTLZ_ZERO_UNDEF
:
return
LowerCTLZ
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
}
return
Op
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> static bool r10k_protected_bb_p ( basic_block bb , sbitmap protected_bbs ) { edge_iterator ei ; edge e ; FOR_EACH_EDGE ( e , ei , bb -> preds ) if ( ! single_succ_p ( e -> src ) || ! bitmap_bit_p ( protected_bbs , e -> src -> index ) || ( e -> flags & EDGE_COMPLEX ) != 0 ) return false ; return true ; } </s>

Return true if BB is only reached by blocks in PROTECTED_BBS and if every edge is unconditional .


"SPARC DAG->DAG Pattern Instruction Selection"


<s> bool convertSelectOfConstantsToMath ( EVT VT ) const override { return true ; } </s>

Return true if a select of constants ( select Cond , C1 , C2 ) should be transformed into simple math ops with the condition value .


<s> bool runOnFunction ( Function & F ) override { if ( skipFunction ( F ) ) return false ; bool Changed = false ; std :: set < Instruction * > WorkList ; for ( Instruction & I : instructions ( & F ) ) WorkList . insert ( & I ) ; while ( ! WorkList . empty ( ) ) { Instruction * I = * WorkList . begin ( ) ; WorkList . erase ( WorkList . begin ( ) ) ; if ( ! I -> use_empty ( ) ) { } } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> virtual const X86Subtarget * getSubtarget ( ) { return Subtarget ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


"Patmos Single-Path Bundling (machine code)"


<s> void ARMTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , APInt & KnownZero , APInt & KnownOne , const SelectionDAG & DAG , unsigned Depth ) const { unsigned BitWidth = KnownOne . getBitWidth ( ) ; KnownZero = KnownOne = APInt ( BitWidth , 0 ) ; switch ( Op . getOpcode ( ) ) { default : break ; case ARMISD :: ADDC : case ARMISD :: ADDE : case ARMISD :: SUBC : case ARMISD :: SUBE : if ( Op . getResNo ( ) == 0 ) break ; KnownZero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - 1 ) ; break ; case ARMISD :: CMOV : { DAG . computeKnownBits ( Op . getOperand ( 0 ) , KnownZero , KnownOne , Depth + 1 ) ; if ( KnownZero == 0 && KnownOne == 0 ) return ; APInt KnownZeroRHS , KnownOneRHS ; DAG . computeKnownBits ( Op . getOperand ( 1 ) , KnownZeroRHS , KnownOneRHS , Depth + 1 ) ; KnownZero &= KnownZeroRHS ; KnownOne &= KnownOneRHS ; return ; } case ISD :: INTRINSIC_W_CHAIN : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ; Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case Intrinsic :: arm_ldaex : case Intrinsic :: arm_ldrex : { EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarType ( ) . getSizeInBits ( ) ; KnownZero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } } } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s>
const
char
*
getPassName
(
)
const
{
return
"Hexagon Split Const32s and Const64s"
;
}
</s>

Hexagon
"Hexagon Split Const32s and Const64s"


"Expecting an ACC register for BUILD_UACC."

Get a list of 'hint ' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg .


"LowerFormalArguments Unhandled argument type: "

"functions with VarArgs or StructRet are not supported"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> static int arc_sched_adjust_priority ( rtx_insn * insn , int priority ) { rtx set = single_set ( insn ) ; if ( set && GET_MODE ( SET_SRC ( set ) ) == DFmode && GET_CODE ( SET_SRC ( set ) ) == REG ) { return priority + 20 ; } return priority ; } </s>

Try to keep the ( mov : DF _ , reg ) as early as possible so that the d < add/sub/mul > h-lr insns appear together and can use the peephole2 pattern .


<s>
const
MCPhysReg
*
X86RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"MachineFunction required"
)
;
const
X86Subtarget
&
Subtarget
=
MF
->
getSubtarget
<
X86Subtarget
>
(
)
;
bool
HasSSE
=
Subtarget
.
hasSSE1
(
)
;
bool
HasAVX
=
Subtarget
.
hasAVX
(
)
;
bool
HasAVX512
=
Subtarget
.
hasAVX512
(
)
;
bool
CallsEHReturn
=
MF
->
callsEHReturn
(
)
;
CallingConv
::
ID
CC
=
MF
->
getFunction
(
)
->
getCallingConv
(
)
;
if
(
MF
->
getFunction
(
)
->
hasFnAttribute
(
"no_caller_saved_registers"
)
)
CC
=
CallingConv
::
X86_INTR
;
switch
(
CC
)
{
case
CallingConv
::
GHC
:
case
CallingConv
::
HiPE
:
return
CSR_NoRegs_SaveList
;
case
CallingConv
::
AnyReg
:
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
return
CSR_64_AllRegs_SaveList
;
case
CallingConv
::
PreserveMost
:
return
CSR_64_RT_MostRegs_SaveList
;
case
CallingConv
::
PreserveAll
:
if
(
HasAVX
)
return
CSR_64_RT_AllRegs_AVX_SaveList
;
return
CSR_64_RT_AllRegs_SaveList
;
case
CallingConv
::
CXX_FAST_TLS
:
if
(
Is64Bit
)
return
MF
->
getInfo
<
X86MachineFunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_64_CXX_TLS_Darwin_PE_SaveList
:
CSR_64_TLS_Darwin_SaveList
;
break
;
case
CallingConv
::
Intel_OCL_BI
:
{
if
(
HasAVX512
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX512
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX_SaveList
;
if
(
HasAVX
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX_SaveList
;
if
(
!
HasAVX
&&
!
IsWin64
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_SaveList
;
break
;
}
case
CallingConv
::
HHVM
:
return
CSR_64_HHVM_SaveList
;
case
CallingConv
::
X86_RegCall
:
if
(
Is64Bit
)
{
if
(
IsWin64
)
{
return
(
HasSSE
CSR_Win64_RegCall_SaveList
:
CSR_Win64_RegCall_NoSSE_SaveList
)
;
}
else
{
return
(
HasSSE
CSR_SysV64_RegCall_SaveList
:
CSR_SysV64_RegCall_NoSSE_SaveList
)
;
}
}
else
{
return
(
HasSSE
CSR_32_RegCall_SaveList
:
CSR_32_RegCall_NoSSE_SaveList
)
;
}
case
CallingConv
::
Cold
:
if
(
Is64Bit
)
return
CSR_64_MostRegs_SaveList
;
break
;
case
CallingConv
::
Win64
:
if
(
!
HasSSE
)
return
CSR_Win64_NoSSE_SaveList
;
return
CSR_Win64_SaveList
;
case
CallingConv
::
X86_64_SysV
:
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
case
CallingConv
::
X86_INTR
:
if
(
Is64Bit
)
{
if
(
HasAVX512
)
return
CSR_64_AllRegs_AVX512_SaveList
;
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
if
(
HasSSE
)
return
CSR_64_AllRegs_SaveList
;
return
CSR_64_AllRegs_NoSSE_SaveList
;
}
else
{
if
(
HasAVX512
)
return
CSR_32_AllRegs_AVX512_SaveList
;
if
(
HasAVX
)
return
CSR_32_AllRegs_AVX_SaveList
;
if
(
HasSSE
)
return
CSR_32_AllRegs_SSE_SaveList
;
return
CSR_32_AllRegs_SaveList
;
}
default
:
break
;
}
if
(
Is64Bit
)
{
if
(
IsWin64
)
{
if
(
!
HasSSE
)
return
CSR_Win64_NoSSE_SaveList
;
return
CSR_Win64_SaveList
;
}
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
if
(
Subtarget
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
->
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_64_SwiftError_SaveList
;
return
CSR_64_SaveList
;
}
if
(
CallsEHReturn
)
return
CSR_32EHRet_SaveList
;
return
CSR_32_SaveList
;
}
</s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"Thumb IT blocks insertion pass"
;
}
</s>


<s>
SDValue
RISCVTargetLowering
::
BuildSDIVPow2
(
SDNode
*
N
,
const
APInt
&
Divisor
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDNode
*
>
&
Created
)
const
{
AttributeList
Attr
=
DAG
.
getMachineFunction
(
)
.
getFunction
(
)
.
getAttributes
(
)
;
if
(
isIntDivCheap
(
N
->
getValueType
(
0
)
,
Attr
)
)
return
SDValue
(
N
,
0
)
;
assert
(
(
Divisor
.
isPowerOf2
(
)
||
Divisor
.
isNegatedPowerOf2
(
)
)
&&
"Unexpected divisor!"
)
;
if
(
!
Subtarget
.
hasStdExtZbt
(
)
)
return
SDValue
(
)
;
unsigned
Lg2
=
Divisor
.
countTrailingZeros
(
)
;
if
(
Lg2
==
1
||
Lg2
>=
12
)
return
SDValue
(
)
;
EVT
VT
=
N
->
getValueType
(
0
)
;
if
(
VT
!=
MVT
::
i32
&&
!
(
Subtarget
.
is64Bit
(
)
&&
VT
==
MVT
::
i64
)
)
return
SDValue
(
)
;
SDLoc
DL
(
N
)
;
SDValue
N0
=
N
->
getOperand
(
0
)
;
SDValue
Zero
=
DAG
.
getConstant
(
0
,
DL
,
VT
)
;
SDValue
Pow2MinusOne
=
DAG
.
getConstant
(
(
1ULL
<<
Lg2
)
1
,
DL
,
VT
)
;
SDValue
Cmp
=
DAG
.
getSetCC
(
DL
,
VT
,
N0
,
Zero
,
ISD
::
SETLT
)
;
SDValue
Add
=
DAG
.
getNode
(
ISD
::
ADD
,
DL
,
VT
,
N0
,
Pow2MinusOne
)
;
SDValue
Sel
=
DAG
.
getNode
(
ISD
::
SELECT
,
DL
,
VT
,
Cmp
,
Add
,
N0
)
;
Created
.
push_back
(
Cmp
.
getNode
(
)
)
;
Created
.
push_back
(
Add
.
getNode
(
)
)
;
Created
.
push_back
(
Sel
.
getNode
(
)
)
;
SDValue
SRA
=
DAG
.
getNode
(
ISD
::
SRA
,
DL
,
VT
,
Sel
,
DAG
.
getConstant
(
Lg2
,
DL
,
VT
)
)
;
if
(
Divisor
.
isNonNegative
(
)
)
return
SRA
;
Created
.
push_back
(
SRA
.
getNode
(
)
)
;
return
DAG
.
getNode
(
ISD
::
SUB
,
DL
,
VT
,
DAG
.
getConstant
(
0
,
DL
,
VT
)
,
SRA
)
;
}
</s>

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators .


<s> SMLoc getEndLoc ( ) const override { return SMLoc ( ) ; } </s>

getEndLoc - Get the location of the last token of this operand .