<s> bool X86FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; const TargetRegisterInfo * RegInfo = MF . getTarget ( ) . getRegisterInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MFI -> hasInlineAsmWithSPAdjust ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) || MMI . callsEHReturn ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static inline bool save_reg_p ( int r ) { return ! call_used_regs [ r ] && df_regs_ever_live_p ( r ) ; } </s>

Determine whether the REG is really used .


<s> PPCSubtarget :: PPCSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , bool is64Bit ) : PPCGenSubtargetInfo ( TT , CPU , FS ) , StackAlignment ( 16 ) , DarwinDirective ( PPC :: DIR_NONE ) , HasMFOCRF ( false ) , Has64BitSupport ( false ) , Use64BitRegs ( false ) , IsPPC64 ( is64Bit ) , HasAltivec ( false ) , HasFSQRT ( false ) , HasSTFIWX ( false ) , HasISEL ( false ) , IsBookE ( false ) , HasLazyResolverStubs ( false ) , IsJITCodeModel ( false ) , TargetTriple ( TT ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "generic" ; ( defined ( __ppc__ ) || defined ( __powerpc__ ) ) if ( CPUName == "generic" ) CPUName = sys :: getHostCPUName ( ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; std :: string FullFS = FS ; if ( is64Bit ) { Has64BitSupport = true ; Use64BitRegs = true ; if ( ! FullFS . empty ( ) ) FullFS = "+64bit," + FullFS ; else FullFS = "+64bit" ; } ParseSubtargetFeatures ( CPUName , FullFS ) ; if ( use64BitRegs ( ) && ! has64BitSupport ( ) ) Use64BitRegs = false ; if ( isDarwin ( ) ) HasLazyResolverStubs = true ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s>
void
AVRMCInstLower
::
lowerInstruction
(
const
MachineInstr
&
MI
,
MCInst
&
OutMI
)
const
{
OutMI
.
setOpcode
(
MI
.
getOpcode
(
)
)
;
for
(
MachineOperand
const
&
MO
:
MI
.
operands
(
)
)
{
MCOperand
MCOp
;
switch
(
MO
.
getType
(
)
)
{
default
:
MI
.
dump
(
)
;
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
)
continue
;
MCOp
=
MCOperand
::
createReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
createImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
getSymbol
(
MO
.
getGlobal
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
createExpr
(
MCSymbolRefExpr
::
create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
Ctx
)
)
;
break
;
case
MachineOperand
::
MO_RegisterMask
:
continue
;
case
MachineOperand
::
MO_BlockAddress
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetJTISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetCPISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
}
OutMI
.
addOperand
(
MCOp
)
;
}
}
</s>


<s> bool MipsRegisterInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return NoFramePointerElim || MFI -> hasVarSizedObjects ( ) ; } </s>


"X86-64 PIC uses RIP relative addressing"

runOnMachineFunction - Emit the function body .


<s> TargetTransformInfo WebAssemblyTargetMachine :: getTargetTransformInfo ( const Function & F ) const { return TargetTransformInfo ( WebAssemblyTTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


"Unhandled instruction encoding format!"

Targets should implement this to emit instructions .


"parameter passing for argument of type "

Determine where to put an argument to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . On the ARM , normally the first 16 bytes are passed in registers r0-r3 ; all other arguments are passed on the stack . If ( NAMED == 0 ) ( which happens only in assign_parms , since TARGET_SETUP_INCOMING_VARARGS is defined ) , say it is passed in the stack ( function_prologue will indeed make it pass in the stack if necessary ) .


<s> void BPFDAGToDAGISel :: PreprocessISelDAG ( ) { for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * Node = & * I ++ ; unsigned Opcode = Node -> getOpcode ( ) ; if ( Opcode == ISD :: LOAD ) PreprocessLoad ( Node , I ) ; else if ( Opcode == ISD :: CopyToReg ) PreprocessCopyToReg ( Node ) ; else if ( Opcode == ISD :: AND ) PreprocessTrunc ( Node , I ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .

BPF BPF ISD::LOAD ISD::CopyToReg ISD::AND


<s> StringRef getPassName ( ) const override { return RISCV_EXPAND_ATOMIC_PSEUDO_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> static int frv_compare_insns ( const void * first , const void * second ) { rtx_insn * const * insn1 = ( rtx_insn * const * ) first ; rtx_insn * const * insn2 = ( rtx_insn * const * ) second ; return frv_insn_unit ( * insn1 ) - frv_insn_unit ( * insn2 ) ; } </s>

Compare two instructions by their frv_insn_unit .


<s> static void aarch64_output_mi_thunk ( FILE * file , tree thunk ATTRIBUTE_UNUSED , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { int this_regno = R0_REGNUM ; rtx this_rtx , temp0 , temp1 , addr , funexp ; rtx_insn * insn ; const char * fnname = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( thunk ) ) ; if ( aarch64_bti_enabled ( ) ) emit_insn ( gen_bti_c ( ) ) ; reload_completed = 1 ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; this_rtx = gen_rtx_REG ( Pmode , this_regno ) ; temp0 = gen_rtx_REG ( Pmode , EP0_REGNUM ) ; temp1 = gen_rtx_REG ( Pmode , EP1_REGNUM ) ; if ( vcall_offset == 0 ) aarch64_add_offset ( Pmode , this_rtx , this_rtx , delta , temp1 , temp0 , false ) ; else { gcc_assert ( ( vcall_offset & ( POINTER_BYTES - 1 ) ) == 0 ) ; addr = this_rtx ; if ( delta != 0 ) { if ( delta >= - 256 && delta < 256 ) addr = gen_rtx_PRE_MODIFY ( Pmode , this_rtx , plus_constant ( Pmode , this_rtx , delta ) ) ; else aarch64_add_offset ( Pmode , this_rtx , this_rtx , delta , temp1 , temp0 , false ) ; } if ( Pmode == ptr_mode ) aarch64_emit_move ( temp0 , gen_rtx_MEM ( ptr_mode , addr ) ) ; else aarch64_emit_move ( temp0 , gen_rtx_ZERO_EXTEND ( Pmode , gen_rtx_MEM ( ptr_mode , addr ) ) ) ; if ( vcall_offset >= - 256 && vcall_offset < 4096 * POINTER_BYTES ) addr = plus_constant ( Pmode , temp0 , vcall_offset ) ; else { aarch64_internal_mov_immediate ( temp1 , GEN_INT ( vcall_offset ) , true , Pmode ) ; addr = gen_rtx_PLUS ( Pmode , temp0 , temp1 ) ; } if ( Pmode == ptr_mode ) aarch64_emit_move ( temp1 , gen_rtx_MEM ( ptr_mode , addr ) ) ; else aarch64_emit_move ( temp1 , gen_rtx_SIGN_EXTEND ( Pmode , gen_rtx_MEM ( ptr_mode , addr ) ) ) ; emit_insn ( gen_add2_insn ( this_rtx , temp1 ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = 1 ; } funexp = XEXP ( DECL_RTL ( function ) , 0 ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; rtx callee_abi = gen_int_mode ( fndecl_abi ( function ) . id ( ) , DImode ) ; insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx , callee_abi ) ) ; SIBLING_CALL_P ( insn ) = 1 ; insn = get_insns ( ) ; shorten_branches ( insn ) ; assemble_start_function ( thunk , fnname ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; assemble_end_function ( thunk , fnname ) ; reload_completed = 0 ; } </s>

Output code to add DELTA to the first argument , and then jump to FUNCTION . Used for C++ multiple inheritance .


"We have a different number of location and args?!"

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> StackOffset RISCVFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const auto * RVFI = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; const auto & CSI = getNonLibcallCSI ( MFI . getCalleeSavedInfo ( ) ) ; int MinCSFI = 0 ; int MaxCSFI = - 1 ; int Offset = MFI . getObjectOffset ( FI ) - getOffsetOfLocalArea ( ) + MFI . getOffsetAdjustment ( ) ; uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( CSI . size ( ) ) { MinCSFI = CSI [ 0 ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - 1 ] . getFrameIdx ( ) ; } if ( FI >= MinCSFI && FI <= MaxCSFI ) { FrameReg = RISCV :: X2 ; if ( FirstSPAdjustAmount ) Offset += FirstSPAdjustAmount ; else Offset += MFI . getStackSize ( ) ; } else if ( RI -> needsStackRealignment ( MF ) && ! MFI . isFixedObjectIndex ( FI ) ) { if ( hasBP ( MF ) ) FrameReg = RISCVABI :: getBPReg ( ) ; else FrameReg = RISCV :: X2 ; Offset += MFI . getStackSize ( ) ; if ( FI < 0 ) Offset += RVFI -> getLibCallStackSize ( ) ; } else { FrameReg = RI -> getFrameRegister ( MF ) ; if ( hasFP ( MF ) ) { Offset += RVFI -> getVarArgsSaveSize ( ) ; if ( FI >= 0 ) Offset -= RVFI -> getLibCallStackSize ( ) ; } else { Offset += MFI . getStackSize ( ) ; if ( FI < 0 ) Offset += RVFI -> getLibCallStackSize ( ) ; } } return StackOffset :: getFixed ( Offset ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> static tree associated_type ( tree decl ) { return ( DECL_CONTEXT ( decl ) && TYPE_P ( DECL_CONTEXT ( decl ) ) ) ? DECL_CONTEXT ( decl ) : NULL_TREE ; } </s>

Return the type that we should use to determine if DECL is imported or exported .


<s> void AMDGPUInstructionSelector :: setupMF ( MachineFunction & MF , GISelKnownBits * KB , CodeGenCoverage & CoverageInfo , ProfileSummaryInfo * PSI , BlockFrequencyInfo * BFI ) { MRI = & MF . getRegInfo ( ) ; Subtarget = & MF . getSubtarget < GCNSubtarget > ( ) ; InstructionSelector :: setupMF ( MF , KB , CoverageInfo , PSI , BFI ) ; } </s>


<s> void changedInstr ( MachineInstr & MI ) override { } </s>

This instruction was mutated in some way .


<s> MachineBasicBlock * PIC16TargetLowering :: EmitInstrWithCustomInserter ( MachineInstr * MI , MachineBasicBlock * BB ) const { const TargetInstrInfo & TII = * getTargetMachine ( ) . getInstrInfo ( ) ; unsigned CC = ( PIC16CC :: CondCodes ) MI -> getOperand ( 3 ) . getImm ( ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; BuildMI ( BB , dl , TII . get ( PIC16 :: pic16brcond ) ) . addMBB ( sinkMBB ) . addImm ( CC ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , dl , TII . get ( PIC16 :: PHI ) , MI -> getOperand ( 0 ) . getReg ( ) ) . addReg ( MI -> getOperand ( 2 ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( 1 ) . getReg ( ) ) . addMBB ( thisMBB ) ; MI -> eraseFromParent ( ) ; return BB ; } </s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static bool riscv_tls_symbol_p ( const_rtx x ) { return SYMBOL_REF_P ( x ) && SYMBOL_REF_TLS_MODEL ( x ) != 0 ; } </s>

Return true if X is a thread-local symbol .


<s> const uint16_t * MandarinRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { 0 } ; return CalleeSavedRegs ; } </s>


<s> bool s390_split_ok_p ( rtx dst , rtx src , machine_mode mode , int first_subword ) { if ( FP_REG_P ( src ) || FP_REG_P ( dst ) || VECTOR_REG_P ( src ) || VECTOR_REG_P ( dst ) ) return false ; if ( s_operand ( src , mode ) || s_operand ( dst , mode ) ) return false ; if ( ( GET_CODE ( src ) == MEM && ! offsettable_memref_p ( src ) ) || ( GET_CODE ( dst ) == MEM && ! offsettable_memref_p ( dst ) ) ) return false ; if ( register_operand ( dst , mode ) ) { rtx subreg = operand_subword ( dst , first_subword , 0 , mode ) ; if ( reg_overlap_mentioned_p ( subreg , src ) ) return false ; } return true ; } </s>

Check whether we can ( and want to ) split a double-word move in mode MODE from SRC to DST into two single-word moves , moving the subword FIRST_SUBWORD first .


<s> void expand_fusion_gpr_load ( rtx * operands ) { rtx addis_value = operands [ 1 ] ; rtx target = operands [ 2 ] ; rtx orig_mem = operands [ 3 ] ; rtx new_addr , new_mem , orig_addr , offset ; enum rtx_code plus_or_lo_sum ; machine_mode target_mode = GET_MODE ( target ) ; machine_mode extend_mode = target_mode ; machine_mode ptr_mode = Pmode ; enum rtx_code extend = UNKNOWN ; if ( GET_CODE ( orig_mem ) == ZERO_EXTEND || ( TARGET_P8_FUSION_SIGN && GET_CODE ( orig_mem ) == SIGN_EXTEND ) ) { extend = GET_CODE ( orig_mem ) ; orig_mem = XEXP ( orig_mem , 0 ) ; target_mode = GET_MODE ( orig_mem ) ; } gcc_assert ( MEM_P ( orig_mem ) ) ; orig_addr = XEXP ( orig_mem , 0 ) ; plus_or_lo_sum = GET_CODE ( orig_addr ) ; gcc_assert ( plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM ) ; offset = XEXP ( orig_addr , 1 ) ; new_addr = gen_rtx_fmt_ee ( plus_or_lo_sum , ptr_mode , addis_value , offset ) ; new_mem = replace_equiv_address_nv ( orig_mem , new_addr , false ) ; if ( extend != UNKNOWN ) new_mem = gen_rtx_fmt_e ( ZERO_EXTEND , extend_mode , new_mem ) ; new_mem = gen_rtx_UNSPEC ( extend_mode , gen_rtvec ( 1 , new_mem ) , UNSPEC_FUSION_GPR ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , new_mem ) ) ; if ( extend == SIGN_EXTEND ) { int sub_off = ( ( BYTES_BIG_ENDIAN ) ? GET_MODE_SIZE ( extend_mode ) - GET_MODE_SIZE ( target_mode ) : 0 ) ; rtx sign_reg = simplify_subreg ( target_mode , target , extend_mode , sub_off ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_SIGN_EXTEND ( extend_mode , sign_reg ) ) ) ; } return ; } </s>

During the peephole2 pass , adjust and expand the insns for a load fusion sequence . We adjust the addis register to use the target register . If the load sign extends , we adjust the code to do the zero extending load , and an explicit sign extension later since the fusion only covers zero extending loads . The operands are : operands [ 0 ] register set with addis ( to be replaced with target ) operands [ 1 ] value set via addis operands [ 2 ] target register being loaded operands [ 3 ] D-form memory reference using operands [ 0 ] .


<s> void ix86_expand_lround ( rtx op0 , rtx op1 ) { machine_mode mode = GET_MODE ( op1 ) ; const struct real_format * fmt ; REAL_VALUE_TYPE pred_half , half_minus_pred_half ; rtx adj ; fmt = REAL_MODE_FORMAT ( mode ) ; real_2expN ( & half_minus_pred_half , - ( fmt -> p ) - 1 , mode ) ; real_arithmetic ( & pred_half , MINUS_EXPR , & dconsthalf , & half_minus_pred_half ) ; adj = force_reg ( mode , const_double_from_real_value ( pred_half , mode ) ) ; ix86_sse_copysign_to_positive ( adj , adj , force_reg ( mode , op1 ) , NULL_RTX ) ; adj = expand_simple_binop ( mode , PLUS , adj , op1 , NULL_RTX , 0 , OPTAB_DIRECT ) ; expand_fix ( op0 , adj , 0 ) ; } </s>

Expand SSE sequence for computing lround from OP1 storing into OP0 .


<s> void XCoreInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , get ( XCore :: LDWFI ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> bool ARMBaseInstrInfo :: hasLowDefLatency ( const TargetSchedModel & SchedModel , const MachineInstr * DefMI , unsigned DefIdx ) const { const InstrItineraryData * ItinData = SchedModel . getInstrItineraries ( ) ; if ( ! ItinData || ItinData -> isEmpty ( ) ) return false ; unsigned DDomain = DefMI -> getDesc ( ) . TSFlags & ARMII :: DomainMask ; if ( DDomain == ARMII :: DomainGeneral ) { unsigned DefClass = DefMI -> getDesc ( ) . getSchedClass ( ) ; int DefCycle = ItinData -> getOperandCycle ( DefClass , DefIdx ) ; return ( DefCycle != - 1 && DefCycle <= 2 ) ; } return false ; } </s>

Compute operand latency of a def of 'Reg ' .

ARM ARM ARMII::DomainMask ARMII::DomainGeneral 1 2


<s>
void
HexagonHazardRecognizer
::
EmitInstruction
(
SUnit
*
SU
)
{
MachineInstr
*
MI
=
SU
->
getInstr
(
)
;
if
(
!
MI
)
return
;
for
(
const
MachineOperand
&
MO
:
MI
->
operands
(
)
)
if
(
MO
.
isReg
(
)
&&
MO
.
isDef
(
)
&&
!
MO
.
isImplicit
(
)
)
RegDefs
.
insert
(
MO
.
getReg
(
)
)
;
if
(
TII
->
isZeroCost
(
MI
->
getOpcode
(
)
)
)
return
;
if
(
!
Resources
->
canReserveResources
(
*
MI
)
)
{
assert
(
TII
->
mayBeNewStore
(
*
MI
)
&&
"Expecting .new store"
)
;
MachineFunction
*
MF
=
MI
->
getParent
(
)
->
getParent
(
)
;
MachineInstr
*
NewMI
=
MF
->
CreateMachineInstr
(
TII
->
get
(
TII
->
getDotNewOp
(
*
MI
)
)
,
MI
->
getDebugLoc
(
)
)
;
assert
(
Resources
->
canReserveResources
(
*
NewMI
)
)
;
Resources
->
reserveResources
(
*
NewMI
)
;
MF
->
DeleteMachineInstr
(
NewMI
)
;
}
else
Resources
->
reserveResources
(
*
MI
)
;
DEBUG
(
dbgs
(
)
<<
" Add instruction "
<<
*
MI
)
;
if
(
TII
->
mayBeCurLoad
(
*
MI
)
)
for
(
auto
&
S
:
SU
->
Succs
)
if
(
S
.
isAssignedRegDep
(
)
&&
S
.
getLatency
(
)
==
0
&&
S
.
getSUnit
(
)
->
NumPredsLeft
==
1
)
{
UsesDotCur
=
S
.
getSUnit
(
)
;
DotCurPNum
=
PacketNum
;
break
;
}
if
(
SU
==
UsesDotCur
)
{
UsesDotCur
=
nullptr
;
DotCurPNum
=
1
;
}
UsesLoad
=
MI
->
mayLoad
(
)
;
if
(
TII
->
isHVXVec
(
*
MI
)
&&
!
MI
->
mayLoad
(
)
&&
!
MI
->
mayStore
(
)
)
for
(
auto
&
S
:
SU
->
Succs
)
if
(
S
.
isAssignedRegDep
(
)
&&
S
.
getLatency
(
)
==
0
&&
TII
->
mayBeNewStore
(
*
S
.
getSUnit
(
)
->
getInstr
(
)
)
&&
Resources
->
canReserveResources
(
*
S
.
getSUnit
(
)
->
getInstr
(
)
)
)
{
PrefVectorStoreNew
=
S
.
getSUnit
(
)
;
break
;
}
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> virtual bool isVirtualSection ( ) const { return false ; } </s>

Check whether this section is `` virtual '' , that is has no actual object file contents .


"Stack realignment in presence of dynamic allocas is not supported with"

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
StringRef
getPassName
(
)
const
override
{
return
"AVR Shift Expansion"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void altivec_expand_vec_perm_le ( rtx operands [ 4 ] ) { rtx notx , iorx , unspec ; rtx target = operands [ 0 ] ; rtx op0 = operands [ 1 ] ; rtx op1 = operands [ 2 ] ; rtx sel = operands [ 3 ] ; rtx tmp = target ; rtx norreg = gen_reg_rtx ( V16QImode ) ; machine_mode mode = GET_MODE ( target ) ; if ( ! REG_P ( op0 ) ) op0 = force_reg ( mode , op0 ) ; if ( ! REG_P ( op1 ) ) op1 = force_reg ( mode , op1 ) ; if ( ! REG_P ( sel ) ) sel = force_reg ( V16QImode , sel ) ; if ( ! REG_P ( target ) ) tmp = gen_reg_rtx ( mode ) ; if ( TARGET_P9_VECTOR ) { unspec = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , op0 , op1 , sel ) , UNSPEC_VPERMR ) ; } else { notx = gen_rtx_NOT ( V16QImode , sel ) ; iorx = ( TARGET_P8_VECTOR ? gen_rtx_IOR ( V16QImode , notx , notx ) : gen_rtx_AND ( V16QImode , notx , notx ) ) ; emit_insn ( gen_rtx_SET ( norreg , iorx ) ) ; unspec = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , op1 , op0 , norreg ) , UNSPEC_VPERM ) ; } if ( ! REG_P ( target ) ) { emit_move_insn ( tmp , unspec ) ; unspec = tmp ; } emit_move_insn ( target , unspec ) ; } </s>

Similarly to altivec_expand_vec_perm_const_le , we must adjust the permute control vector . But here it 's not a constant , so we must generate a vector NAND or NOR to do the adjustment .


<s> const uint32_t * ARMBaseRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; if ( CC == CallingConv :: GHC ) return CSR_NoRegs_RegMask ; if ( CC == CallingConv :: CFGuard_Check ) return CSR_Win_AAPCS_CFGuard_Check_RegMask ; if ( STI . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return STI . isTargetDarwin ( ) ? CSR_iOS_SwiftError_RegMask : CSR_AAPCS_SwiftError_RegMask ; if ( STI . isTargetDarwin ( ) && CC == CallingConv :: CXX_FAST_TLS ) return CSR_iOS_CXX_TLS_RegMask ; return STI . isTargetDarwin ( ) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


"Did not fully process a global variable"

Set up the AsmPrinter when we are working on a new module .


<s> static bool is_indirect_tailcall_p ( rtx call ) { rtx pat = PATTERN ( call ) ; pat = XVECEXP ( pat , 0 , 0 ) ; if ( GET_CODE ( pat ) == SET ) pat = SET_SRC ( pat ) ; pat = XEXP ( XEXP ( pat , 0 ) , 0 ) ; return REG_P ( pat ) ; } </s>

We do not know if r3 will be available because we do have an indirect tailcall happening in this particular case .


<s> static rtx riscv_add_offset ( rtx temp , rtx reg , HOST_WIDE_INT offset ) { if ( ! SMALL_OPERAND ( offset ) ) { rtx high ; high = gen_int_mode ( CONST_HIGH_PART ( offset ) , Pmode ) ; offset = CONST_LOW_PART ( offset ) ; high = riscv_force_temporary ( temp , high , FALSE ) ; reg = riscv_force_temporary ( temp , gen_rtx_PLUS ( Pmode , high , reg ) , FALSE ) ; } return plus_constant ( Pmode , reg , offset ) ; } </s>

Return a legitimate address for REG + OFFSET . TEMP is as for riscv_force_temporary ; it is only needed when OFFSET is not a SMALL_OPERAND .


<s> uint64_t SIProgramInfo :: getComputePGMRSrc1 ( ) const { return S_00B848_VGPRS ( VGPRBlocks ) | S_00B848_SGPRS ( SGPRBlocks ) | S_00B848_PRIORITY ( Priority ) | S_00B848_FLOAT_MODE ( FloatMode ) | S_00B848_PRIV ( Priv ) | S_00B848_DX10_CLAMP ( DX10Clamp ) | S_00B848_DEBUG_MODE ( DebugMode ) | S_00B848_IEEE_MODE ( IEEEMode ) | S_00B848_WGP_MODE ( WgpMode ) | S_00B848_MEM_ORDERED ( MemOrdered ) ; } </s>

Compute the value of the ComputePGMRsrc1 register .


<s> void HexagonFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { auto & HRI = * MF . getSubtarget < HexagonSubtarget > ( ) . getRegisterInfo ( ) ; SavedRegs . resize ( HRI . getNumRegs ( ) ) ; if ( MF . getInfo < HexagonMachineFunctionInfo > ( ) -> hasEHReturn ( ) ) for ( const MCPhysReg * R = HRI . getCalleeSavedRegs ( & MF ) ; * R ; ++ R ) SavedRegs . set ( * R ) ; SmallVector < unsigned , 8 > NewRegs ; expandSpillMacros ( MF , NewRegs ) ; if ( OptimizeSpillSlots && ! isOptNone ( MF ) ) optimizeSpillSlots ( MF , NewRegs ) ; if ( ! NewRegs . empty ( ) || mayOverflowFrameOffset ( MF ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; SetVector < const TargetRegisterClass * > SpillRCs ; SpillRCs . insert ( & Hexagon :: IntRegsRegClass ) ; for ( unsigned VR : NewRegs ) SpillRCs . insert ( MRI . getRegClass ( VR ) ) ; for ( auto * RC : SpillRCs ) { if ( ! needToReserveScavengingSpillSlots ( MF , HRI , RC ) ) continue ; unsigned Num = 1 ; switch ( RC -> getID ( ) ) { case Hexagon :: IntRegsRegClassID : Num = NumberScavengerSlots ; break ; case Hexagon :: HvxQRRegClassID : Num = 2 ; break ; } unsigned S = HRI . getSpillSize ( * RC ) , A = HRI . getSpillAlignment ( * RC ) ; for ( unsigned i = 0 ; i < Num ; i ++ ) { int NewFI = MFI . CreateSpillStackObject ( S , A ) ; RS -> addScavengingFrameIndex ( NewFI ) ; } } } TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> const char * CJGTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( CJGISD :: NodeType ) Opcode ) { case CJGISD :: FIRST_NUMBER : break ; case CJGISD :: CMP : return "CJGISD::CMP" ; case CJGISD :: RET_FLAG : return "CJGISD::RET_FLAG" ; case CJGISD :: BR_CC : return "CJGISD::BR_CC" ; case CJGISD :: SELECT_CC : return "CJGISD::SELECT_CC" ; case CJGISD :: Wrapper : return "CJGISD::Wrapper" ; case CJGISD :: CALL : return "CJGISD::CALL" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> MachineBasicBlock * TGSICFGStructurizer :: clone ( MachineBasicBlock * MBB ) { MachineFunction * Func = MBB -> getParent ( ) ; MachineBasicBlock * NewMBB = Func -> CreateMachineBasicBlock ( ) ; Func -> push_back ( NewMBB ) ; for ( const MachineInstr & It : * MBB ) NewMBB -> push_back ( Func -> CloneMachineInstr ( & It ) ) ; return NewMBB ; } </s>

Make a functionally equivalent copy of this MachineFunctionInfo in MF .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this , LittleEndian ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; } </s>


<s> void LoongArchFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


<s> static bool c6x_scalar_mode_supported_p ( scalar_mode mode ) { if ( ALL_FIXED_POINT_MODE_P ( mode ) && GET_MODE_PRECISION ( mode ) <= 2 * BITS_PER_WORD ) return true ; return default_scalar_mode_supported_p ( mode ) ; } </s>


<s> bool rs6000_must_pass_in_stack ( const function_arg_info & arg ) { if ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT ) return must_pass_in_stack_var_size ( arg ) ; else return must_pass_in_stack_var_size_or_pad ( arg ) ; } </s>

Return true if TYPE must be passed on the stack and not in registers .


"calling %qD with SSE calling convention without "

"this is a GCC bug that can be worked around by adding "

Define where to put the arguments to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) .


<s> std :: pair < unsigned , unsigned > RISCVInstrInfo :: decomposeMachineOperandsTargetFlags ( unsigned TF ) const { const unsigned Mask = RISCVII :: MO_DIRECT_FLAG_MASK ; return std :: make_pair ( TF & Mask , TF & ~ Mask ) ; } </s>

Decompose the machine operand 's target flags into two values - the direct target flag value and any of bit flags that are applied .


<s> static bool bfin_function_ok_for_sibcall ( tree decl ATTRIBUTE_UNUSED , tree exp ATTRIBUTE_UNUSED ) { e_funkind fkind = funkind ( TREE_TYPE ( current_function_decl ) ) ; return fkind == SUBROUTINE ; } </s>

Decide whether we can make a sibling call to a function . DECL is the declaration of the function being targeted by the call and EXP is the CALL_EXPR representing the call .


<s> unsigned getRsaSize ( ) const { return 176 ; } </s>

Get the size of RSA , return address , and frame pointer as described in VEFrameLowering.cpp .


<s> HOST_WIDE_INT alpha_vms_initial_elimination_offset ( unsigned int from , unsigned int to ) { HOST_WIDE_INT sa_size = alpha_sa_size ( ) ; if ( alpha_procedure_type == PT_NULL ) return 0 ; { HOST_WIDE_INT offset ; HOST_WIDE_INT pv_save_size = alpha_procedure_type == PT_STACK ? 8 : 0 ; switch ( from ) { case FRAME_POINTER_REGNUM : offset = ALPHA_ROUND ( sa_size + pv_save_size ) ; break ; case ARG_POINTER_REGNUM : offset = ( ALPHA_ROUND ( sa_size + pv_save_size + get_frame_size ( ) + crtl -> args . pretend_args_size ) - crtl -> args . pretend_args_size ) ; break ; default : gcc_unreachable ( ) ; } if ( to == STACK_POINTER_REGNUM ) offset += ALPHA_ROUND ( crtl -> outgoing_args_size ) ; return offset ; } } </s>

FROM is to be eliminated for TO . Return the offset so that TO+offset designates the same location as FROM .


<s> PLTEntryBase * X86PLT :: create ( ) { if ( LinkerConfig :: DynObj == m_Config . codeGenType ( ) ) return new X86_32DynPLT1 ( * m_pSectionData ) ; else return new X86_32ExecPLT1 ( * m_pSectionData ) ; } </s>


<s> const MCExpr * ARM64_MachoTargetObjectFile :: getTTypeGlobalReference ( const GlobalValue * GV , unsigned Encoding , Mangler & Mang , const TargetMachine & TM , MachineModuleInfo * MMI , MCStreamer & Streamer ) const { if ( Encoding & ( DW_EH_PE_indirect | DW_EH_PE_pcrel ) ) { const MCSymbol * Sym = TM . getSymbol ( GV , Mang ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_GOT , getContext ( ) ) ; MCSymbol * PCSym = getContext ( ) . CreateTempSymbol ( ) ; Streamer . EmitLabel ( PCSym ) ; const MCExpr * PC = MCSymbolRefExpr :: Create ( PCSym , getContext ( ) ) ; return MCBinaryExpr :: CreateSub ( Res , PC , getContext ( ) ) ; } return TargetLoweringObjectFileMachO :: getTTypeGlobalReference ( GV , Encoding , Mang , TM , MMI , Streamer ) ; } </s>

The mach-o version of this method defaults to returning a stub reference .


<s> const uint32_t * SHUXIRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return CC_Save_RegMask ; } </s>


<s> static bool rs6000_emit_move_si_sf_subreg ( rtx dest , rtx source , machine_mode mode ) { if ( TARGET_DIRECT_MOVE_64BIT && ! reload_completed && ( ! SUBREG_P ( dest ) || ! sf_subreg_operand ( dest , mode ) ) && SUBREG_P ( source ) && sf_subreg_operand ( source , mode ) ) { rtx inner_source = SUBREG_REG ( source ) ; machine_mode inner_mode = GET_MODE ( inner_source ) ; if ( mode == SImode && inner_mode == SFmode ) { emit_insn ( gen_movsi_from_sf ( dest , inner_source ) ) ; return true ; } if ( mode == SFmode && inner_mode == SImode ) { emit_insn ( gen_movsf_from_si ( dest , inner_source ) ) ; return true ; } } return false ; } </s>

Helper function to change moves with : ( SUBREG : SF ( REG : SI ) ) and ( SUBREG : SI ( REG : SF ) ) into separate UNSPEC insns . In the PowerPC architecture , scalar SFmode values are stored as DFmode values in the VSX registers . We need to convert the bits before we can use a direct move or operate on the bits in the vector register as an integer type . Skip things like ( set ( SUBREG : SI ( ... ) ( SUBREG : SI ( ... ) ) .


<s> bool AArch64FastISel :: isTypeLegal ( Type * Ty , MVT & VT ) { EVT evt = TLI . getValueType ( Ty , true ) ; if ( evt == MVT :: Other || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; if ( VT == MVT :: f128 ) return false ; return TLI . isTypeLegal ( VT ) ; } </s>


<s> int ix86_register_move_cost ( enum machine_mode mode , enum reg_class class1 , enum reg_class class2 ) { if ( ix86_secondary_memory_needed ( class1 , class2 , mode , 0 ) ) { int cost = 1 ; cost += MAX ( MEMORY_MOVE_COST ( mode , class1 , 0 ) , MEMORY_MOVE_COST ( mode , class1 , 1 ) ) ; cost += MAX ( MEMORY_MOVE_COST ( mode , class2 , 0 ) , MEMORY_MOVE_COST ( mode , class2 , 1 ) ) ; if ( CLASS_MAX_NREGS ( class1 , mode ) > CLASS_MAX_NREGS ( class2 , mode ) ) cost += 20 ; if ( ( MMX_CLASS_P ( class1 ) && MAYBE_FLOAT_CLASS_P ( class2 ) ) || ( MMX_CLASS_P ( class2 ) && MAYBE_FLOAT_CLASS_P ( class1 ) ) ) cost += 20 ; return cost ; } if ( MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class2 ) || SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class2 ) ) return ix86_cost -> mmxsse_to_integer ; if ( MAYBE_FLOAT_CLASS_P ( class1 ) ) return ix86_cost -> fp_move ; if ( MAYBE_SSE_CLASS_P ( class1 ) ) return ix86_cost -> sse_move ; if ( MAYBE_MMX_CLASS_P ( class1 ) ) return ix86_cost -> mmx_move ; return 2 ; } </s>

Return the cost of moving data from a register in class CLASS1 to one in class CLASS2 . It is not required that the cost always equal 2 when FROM is the same as TO ; on some machines it is expensive to move between registers if they are not general registers .


<s>
bool
R600VectorRegMerger
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
TII
=
static_cast
<
const
R600InstrInfo
*
>
(
Fn
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
MRI
=
&
(
Fn
.
getRegInfo
(
)
)
;
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
MachineBasicBlock
*
MB
=
MBB
;
PreviousRegSeq
.
clear
(
)
;
PreviousRegSeqByReg
.
clear
(
)
;
PreviousRegSeqByUndefCount
.
clear
(
)
;
for
(
MachineBasicBlock
::
iterator
MII
=
MB
->
begin
(
)
,
MIIE
=
MB
->
end
(
)
;
MII
!=
MIIE
;
++
MII
)
{
MachineInstr
*
MI
=
MII
;
if
(
MI
->
getOpcode
(
)
!=
AMDGPU
::
REG_SEQUENCE
)
{
if
(
TII
->
get
(
MI
->
getOpcode
(
)
)
.
TSFlags
&
R600_InstFlag
::
TEX_INST
)
{
unsigned
Reg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
for
(
MachineRegisterInfo
::
def_instr_iterator
It
=
MRI
->
def_instr_begin
(
Reg
)
,
E
=
MRI
->
def_instr_end
(
)
;
It
!=
E
;
++
It
)
{
RemoveMI
(
&
(
*
It
)
)
;
}
}
continue
;
}
RegSeqInfo
RSI
(
*
MRI
,
MI
)
;
unsigned
Reg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
if
(
!
areAllUsesSwizzeable
(
Reg
)
)
continue
;
DEBUG
(
dbgs
(
)
<<
"Trying to optimize "
;
MI
->
dump
(
)
;
)
;
RegSeqInfo
CandidateRSI
;
std
::
vector
<
std
::
pair
<
unsigned
,
unsigned
>
>
RemapChan
;
DEBUG
(
dbgs
(
)
<<
"Using common slots...\n"
;
)
;
if
(
tryMergeUsingCommonSlot
(
RSI
,
CandidateRSI
,
RemapChan
)
)
{
RemoveMI
(
CandidateRSI
.
Instr
)
;
MII
=
RebuildVector
(
&
RSI
,
&
CandidateRSI
,
RemapChan
)
;
trackRSI
(
RSI
)
;
continue
;
}
DEBUG
(
dbgs
(
)
<<
"Using free slots...\n"
;
)
;
RemapChan
.
clear
(
)
;
if
(
tryMergeUsingFreeSlot
(
RSI
,
CandidateRSI
,
RemapChan
)
)
{
RemoveMI
(
CandidateRSI
.
Instr
)
;
MII
=
RebuildVector
(
&
RSI
,
&
CandidateRSI
,
RemapChan
)
;
trackRSI
(
RSI
)
;
continue
;
}
trackRSI
(
RSI
)
;
}
}
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .

AMDGPU
R600
R600
AMDGPU::REG_SEQUENCE
R600_InstFlag::TEX_INST
1
SI
0
"Trying to optimize "
SI
"Using common slots...\n"
SI
SI
SI
SI
SI
SI
SI
"Using free slots...\n"
SI
SI
SI
SI
SI
SI
SI
SI
SI


<s> inline bool s390_restore_gpr_p ( int regno ) { return ( cfun_frame_layout . first_restore_gpr != - 1 && regno >= cfun_frame_layout . first_restore_gpr && regno <= cfun_frame_layout . last_restore_gpr ) ; } </s>

Return TRUE if GPR REGNO is supposed to be restored in the function epilogue .


<s> static void ft32_option_override ( void ) { init_machine_status = ft32_init_machine_status ; } </s>

The TARGET_OPTION_OVERRIDE worker . All this curently does is set init_machine_status .


<s>
TypedPointerType
*
TypedPointerType
::
get
(
Type
*
EltTy
,
unsigned
AddressSpace
)
{
assert
(
EltTy
&&
"Can't get a pointer to <null> type!"
)
;
assert
(
isValidElementType
(
EltTy
)
&&
"Invalid type for pointer element!"
)
;
llvm
::
Any
&
TargetData
=
EltTy
->
getContext
(
)
.
getTargetData
(
)
;
if
(
!
TargetData
.
hasValue
(
)
)
TargetData
=
Any
{
std
::
make_shared
<
TypedPointerTracking
>
(
)
}
;
assert
(
any_isa
<
std
::
shared_ptr
<
TypedPointerTracking
>>
(
TargetData
)
&&
"Unexpected target data type"
)
;
std
::
shared_ptr
<
TypedPointerTracking
>
Tracking
=
any_cast
<
std
::
shared_ptr
<
TypedPointerTracking
>>
(
TargetData
)
;
std
::
unique_ptr
<
TypedPointerType
>
&
Entry
=
AddressSpace
==
0
Tracking
->
PointerTypes
[
EltTy
]
:
Tracking
->
ASPointerTypes
[
std
::
make_pair
(
EltTy
,
AddressSpace
)
]
;
if
(
!
Entry
)
Entry
=
std
::
unique_ptr
<
TypedPointerType
>
(
new
TypedPointerType
(
EltTy
,
AddressSpace
)
)
;
return
Entry
.
get
(
)
;
}
</s>

Get the generated Value for a given VPValue and given Part and Lane .

DirectX
"Can't get a pointer to <null> type!"
"Invalid type for pointer element!"
"Unexpected target data type"
0


<s> const InstrItineraryData * getInstrItineraryData ( ) const { return Subtarget . getInstrItineraryData ( ) ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


";; %smode fixup for i%d; addr %lu, range (%ld,%ld): "

Record INSN , which will need fixing up to load a value from the minipool . ADDRESS is the offset of the insn since the start of the function ; LOC is a pointer to the part of the insn which requires fixing ; VALUE is the constant that must be loaded , which is of type MODE .


<s> void validate_condition_mode ( enum rtx_code code , machine_mode mode ) { gcc_assert ( ( GET_RTX_CLASS ( code ) == RTX_COMPARE || GET_RTX_CLASS ( code ) == RTX_COMM_COMPARE ) && GET_MODE_CLASS ( mode ) == MODE_CC ) ; gcc_assert ( ( code != GT && code != LT && code != GE && code != LE ) || mode != CCUNSmode ) ; gcc_assert ( ( code != GTU && code != LTU && code != GEU && code != LEU ) || mode == CCUNSmode ) ; gcc_assert ( mode == CCFPmode || ( code != ORDERED && code != UNORDERED && code != UNEQ && code != LTGT && code != UNGT && code != UNLT && code != UNGE && code != UNLE ) ) ; gcc_assert ( mode != CCEQmode || code == EQ || code == NE ) ; } </s>

A validation routine : say whether CODE , a condition code , and MODE match . The other alternatives either do n't make sense or should never be generated .


<s> bool OpenRISCPassConfig :: addInstSelector ( ) { PM . add ( createOpenRISCISelDag ( getOpenRISCTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static void ix86_add_cfa_restore_note ( rtx_insn * insn , rtx reg , HOST_WIDE_INT cfa_offset ) { if ( ! crtl -> shrink_wrapped && cfa_offset <= cfun -> machine -> fs . red_zone_offset ) return ; if ( insn ) { add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } else queued_cfa_restores = alloc_reg_note ( REG_CFA_RESTORE , reg , queued_cfa_restores ) ; } </s>

Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack manipulation insn . The value is on the stack at CFA - CFA_OFFSET . Do n't add the note if the previously saved value will be left untouched within stack red-zone till return , as unwinders can find the same value in the register and on the stack .


<s> StringRef SIRegisterInfo :: getRegAsmName ( unsigned Reg ) const { const TargetRegisterClass * RC = getMinimalPhysRegClass ( Reg ) ; unsigned Size = getRegSizeInBits ( * RC ) ; unsigned AltName = AMDGPU :: NoRegAltName ; switch ( Size ) { case 32 : AltName = AMDGPU :: Reg32 ; break ; case 64 : AltName = AMDGPU :: Reg64 ; break ; case 96 : AltName = AMDGPU :: Reg96 ; break ; case 128 : AltName = AMDGPU :: Reg128 ; break ; case 160 : AltName = AMDGPU :: Reg160 ; break ; case 256 : AltName = AMDGPU :: Reg256 ; break ; case 512 : AltName = AMDGPU :: Reg512 ; break ; case 1024 : AltName = AMDGPU :: Reg1024 ; break ; } return AMDGPUInstPrinter :: getRegisterName ( Reg , AltName ) ; } </s>


"Both vector needs to be equally scalable"

Try to calculate op costs for min/max reduction operations .


<s> const RegisterBankInfo :: InstructionMapping & X86RegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto Opc = MI . getOpcode ( ) ; if ( ! isPreISelGenericOpcode ( Opc ) ) { const InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; } switch ( Opc ) { case TargetOpcode :: G_ADD : case TargetOpcode :: G_SUB : return getSameOperandsMapping ( MI , false ) ; break ; case TargetOpcode :: G_FADD : case TargetOpcode :: G_FSUB : case TargetOpcode :: G_FMUL : case TargetOpcode :: G_FDIV : return getSameOperandsMapping ( MI , true ) ; break ; default : break ; } unsigned NumOperands = MI . getNumOperands ( ) ; SmallVector < PartialMappingIdx , 4 > OpRegBankIdx ( NumOperands ) ; getInstrPartialMappingIdxs ( MI , MRI , false , OpRegBankIdx ) ; SmallVector < const ValueMapping * , 8 > OpdsMapping ( NumOperands ) ; if ( ! getInstrValueMapping ( MI , OpRegBankIdx , OpdsMapping ) ) return getInvalidInstructionMapping ( ) ; return getInstructionMapping ( DefaultMappingID , 1 , getOperandsMapping ( OpdsMapping ) , NumOperands ) ; } </s>

Get the mapping of the different operands of MI on the register bank .


<s> static void nds32_setup_incoming_varargs ( cumulative_args_t ca , const function_arg_info & arg , int * pretend_args_size , int second_time ATTRIBUTE_UNUSED ) { unsigned int total_args_regs ; unsigned int num_of_used_regs ; unsigned int remaining_reg_count ; CUMULATIVE_ARGS * cum ; if ( TARGET_HARD_FLOAT ) return ; cum = get_cumulative_args ( ca ) ; total_args_regs = NDS32_MAX_GPR_REGS_FOR_ARGS + NDS32_GPR_ARG_FIRST_REGNUM ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) ) num_of_used_regs = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG ( cum -> gpr_offset , arg . mode , arg . type ) + NDS32_NEED_N_REGS_FOR_ARG ( arg . mode , arg . type ) ; else num_of_used_regs = cum -> gpr_offset + NDS32_GPR_ARG_FIRST_REGNUM ; remaining_reg_count = total_args_regs - num_of_used_regs ; * pretend_args_size = remaining_reg_count * UNITS_PER_WORD ; return ; } </s>


<s> bool AMDGPUCallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , unsigned VReg ) const { return true ; } </s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> static void aarch64_emit_sve_ptrue_op ( rtx target , rtx ptrue , rtx op ) { rtx unspec = gen_rtx_UNSPEC ( GET_MODE ( target ) , gen_rtvec ( 2 , ptrue , op ) , UNSPEC_MERGE_PTRUE ) ; rtx_insn * insn = emit_set_insn ( target , unspec ) ; set_unique_reg_note ( insn , REG_EQUAL , copy_rtx ( op ) ) ; } </s>

Use predicated SVE instructions to implement the equivalent of : ( set TARGET OP ) given that PTRUE is an all-true predicate of the appropriate mode .


<s> virtual MVT getShiftAmountTy ( EVT LHSTy ) const { return MVT :: i16 ; } </s>

Returns the type for the shift amount of a shift opcode .


<s> bool RISCVFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock & EntryBlock = * ( MF -> begin ( ) ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == RISCV :: ra || Reg == RISCV :: ra_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock . addLiveIn ( Reg ) ; bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> void StackFixup :: optimize ( bool IsCommutative ) { if ( Changes . empty ( ) ) return ; optimizeEqualXchgs ( ) ; if ( IsCommutative ) { if ( Changes . size ( ) == 1u ) { auto & Change = Changes [ 0 ] . first ; if ( auto * Xchg = std :: get_if < xchgTop > ( & Change ) ) { if ( Xchg -> i == 1u ) Changes . clear ( ) ; } } else if ( Changes . size ( ) == 2u && ( std :: holds_alternative < pushI > ( Changes [ 0 ] . first ) || std :: holds_alternative < pushUndef > ( Changes [ 0 ] . first ) ) ) { auto & Change = Changes [ 1 ] . first ; if ( auto * Xchg = std :: get_if < xchgTop > ( & Change ) ) { if ( Xchg -> i == 1u ) Changes . pop_back ( ) ; } } } } </s>

Apply VPlan-to-VPlan optimizations to Plan , including induction recipe optimizations , dead recipe removal , replicate region optimizations and block merging .


<s> void AMDGPUTargetLowering :: AnalyzeFormalArguments ( CCState & State , const SmallVectorImpl < ISD :: InputArg > & Ins ) const { State . AnalyzeFormalArguments ( Ins , CC_AMDGPU ) ; } </s>

AnalyzeFormalArguments - Analyze an array of argument values , incorporating info about the formals into this state .


"\t\tmul%s.u32 %%fstmp1, %%fstmp0, %d;\n"


<s> static machine_mode ix86_split_reduction ( machine_mode mode ) { switch ( mode ) { case E_V8DImode : case E_V4DImode : return V2DImode ; case E_V16SImode : case E_V8SImode : return V4SImode ; case E_V32HImode : case E_V16HImode : return V8HImode ; case E_V64QImode : case E_V32QImode : return V16QImode ; case E_V16SFmode : case E_V8SFmode : return V4SFmode ; case E_V8DFmode : case E_V4DFmode : return V2DFmode ; default : return mode ; } } </s>

All CPUs prefer to avoid cross-lane operations so perform reductions upper against lower halves up to SSE reg size .


<s> void LC2200InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
InfosBE
[
PPC
::
NumTargetFixupKinds
]
=
{
{
"fixup_ppc_br24"
,
6
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_brcond14"
,
16
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_br24abs"
,
6
,
24
,
0
}
,
{
"fixup_ppc_brcond14abs"
,
16
,
14
,
0
}
,
{
"fixup_ppc_half16"
,
0
,
16
,
0
}
,
{
"fixup_ppc_half16ds"
,
0
,
14
,
0
}
,
{
"fixup_ppc_nofixup"
,
0
,
0
,
0
}
}
;
const
static
MCFixupKindInfo
InfosLE
[
PPC
::
NumTargetFixupKinds
]
=
{
{
"fixup_ppc_br24"
,
2
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_brcond14"
,
2
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_br24abs"
,
2
,
24
,
0
}
,
{
"fixup_ppc_brcond14abs"
,
2
,
14
,
0
}
,
{
"fixup_ppc_half16"
,
0
,
16
,
0
}
,
{
"fixup_ppc_half16ds"
,
2
,
14
,
0
}
,
{
"fixup_ppc_nofixup"
,
0
,
0
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
(
IsLittleEndian
InfosLE
:
InfosBE
)
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> void LanaiFrameLowering :: emitEpilogue ( MachineFunction & , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; const LanaiInstrInfo & LII = * static_cast < const LanaiInstrInfo * > ( STI . getInstrInfo ( ) ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; BuildMI ( MBB , MBBI , DL , LII . get ( Lanai :: ADD_I_LO ) , Lanai :: SP ) . addReg ( Lanai :: FP ) . addImm ( 0 ) ; BuildMI ( MBB , MBBI , DL , LII . get ( Lanai :: LDW_RI ) , Lanai :: FP ) . addReg ( Lanai :: FP ) . addImm ( - 8 ) . addImm ( LPAC :: ADD ) ; } </s>

Lanai Lanai Lanai Lanai Lanai::ADD_I_LO Lanai::SP Lanai::FP 0 Lanai::LDW_RI Lanai::FP Lanai::FP 8


<s> bool xtensa_simm8 ( HOST_WIDE_INT v ) { return IN_RANGE ( v , - 128 , 127 ) ; } </s>

Functions to test Xtensa immediate operand validity .


<s> bool HexagonTargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { auto Attr = CI -> getParent ( ) -> getParent ( ) -> getFnAttribute ( "disable-tail-calls" ) ; if ( ! CI -> isTailCall ( ) || Attr . getValueAsString ( ) == "true" ) return false ; return true ; } </s>

Return true if the target may be able emit the call instruction as a tail call .

Hexagon Hexagon "disable-tail-calls" "true"


<s> int AArch64TargetLowering :: getScalingFactorCost ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( isLegalAddressingMode ( DL , AM , Ty , AS ) ) return AM . Scale != 0 && AM . Scale != 1 ; return - 1 ; } </s>

Return the cost of the scaling factor used in the addressing mode represented by AM for this target , for a load/store of the specified type .


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( Count % 4 ) return false ; uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> Write32 ( 0 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s>
MCOperand
RISCVMCInstLower
::
lowerOperand
(
const
MachineOperand
&
MO
)
const
{
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
)
return
MCOperand
(
)
;
return
MCOperand
::
createReg
(
MO
.
getReg
(
)
)
;
case
MachineOperand
::
MO_Immediate
:
return
MCOperand
::
createImm
(
MO
.
getImm
(
)
)
;
case
MachineOperand
::
MO_MachineBasicBlock
:
return
lowerSymbolOperand
(
MO
,
MO
.
getMBB
(
)
->
getSymbol
(
)
,
0
)
;
case
MachineOperand
::
MO_GlobalAddress
:
return
lowerSymbolOperand
(
MO
,
AsmPrinter
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
MO
.
getOffset
(
)
)
;
case
MachineOperand
::
MO_ExternalSymbol
:
{
StringRef
Name
=
MO
.
getSymbolName
(
)
;
return
lowerSymbolOperand
(
MO
,
AsmPrinter
.
GetExternalSymbolSymbol
(
Name
)
,
MO
.
getOffset
(
)
)
;
}
case
MachineOperand
::
MO_JumpTableIndex
:
return
lowerSymbolOperand
(
MO
,
AsmPrinter
.
GetJTISymbol
(
MO
.
getIndex
(
)
)
,
0
)
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
return
lowerSymbolOperand
(
MO
,
AsmPrinter
.
GetCPISymbol
(
MO
.
getIndex
(
)
)
,
MO
.
getOffset
(
)
)
;
case
MachineOperand
::
MO_BlockAddress
:
{
const
BlockAddress
*
BA
=
MO
.
getBlockAddress
(
)
;
return
lowerSymbolOperand
(
MO
,
AsmPrinter
.
GetBlockAddressSymbol
(
BA
)
,
MO
.
getOffset
(
)
)
;
}
}
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s>
bool
MipsAsmPrinter
::
doInitialization
(
Module
&
M
)
{
O
<<
"\t.section .mdebug."
<<
emitCurrentABIString
(
)
<<
'\n'
;
if
(
Subtarget
->
isABI_EABI
(
)
)
O
<<
"\t.section .gcc_compiled_long"
<<
(
Subtarget
->
isGP32bit
(
)
"32"
:
"64"
)
<<
'\n'
;
O
<<
"\t.previous"
<<
'\n'
;
return
AsmPrinter
::
doInitialization
(
M
)
;
}
</s>

Set up the AsmPrinter when we are working on a new module .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> std :: pair < SDValue , SDValue > SystemZSelectionDAGInfo :: EmitTargetCodeForMemchr ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Src , SDValue Char , SDValue Length , MachinePointerInfo SrcPtrInfo ) const { EVT PtrVT = Src . getValueType ( ) ; SDVTList VTs = DAG . getVTList ( PtrVT , MVT :: Other , MVT :: Glue ) ; Length = DAG . getZExtOrTrunc ( Length , DL , PtrVT ) ; Char = DAG . getZExtOrTrunc ( Char , DL , MVT :: i32 ) ; Char = DAG . getNode ( ISD :: AND , DL , MVT :: i32 , Char , DAG . getConstant ( 255 , DL , MVT :: i32 ) ) ; SDValue Limit = DAG . getNode ( ISD :: ADD , DL , PtrVT , Src , Length ) ; SDValue End = DAG . getNode ( SystemZISD :: SEARCH_STRING , DL , VTs , Chain , Limit , Src , Char ) ; Chain = End . getValue ( 1 ) ; SDValue Glue = End . getValue ( 2 ) ; SDValue Ops [ ] = { End , DAG . getConstant ( 0 , DL , PtrVT ) , DAG . getConstant ( SystemZ :: CCMASK_SRST , DL , MVT :: i32 ) , DAG . getConstant ( SystemZ :: CCMASK_SRST_FOUND , DL , MVT :: i32 ) , Glue } ; VTs = DAG . getVTList ( PtrVT , MVT :: Glue ) ; End = DAG . getNode ( SystemZISD :: SELECT_CCMASK , DL , VTs , Ops ) ; return std :: make_pair ( End , Chain ) ; } </s>

Emit target-specific code that performs a memchr , in cases where that is faster than a libcall .


<s> static unsigned spu_add_stmt_cost ( void * data , int count , enum vect_cost_for_stmt kind , struct _stmt_vec_info * stmt_info , int misalign , enum vect_cost_model_location where ) { unsigned * cost = ( unsigned * ) data ; unsigned retval = 0 ; if ( flag_vect_cost_model ) { tree vectype = stmt_info ? stmt_vectype ( stmt_info ) : NULL_TREE ; int stmt_cost = spu_builtin_vectorization_cost ( kind , vectype , misalign ) ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( stmt_info ) ) count *= 50 ; retval = ( unsigned ) ( count * stmt_cost ) ; cost [ where ] += retval ; } return retval ; } </s>


<s>
void
WebAssemblyInstPrinter
::
printRegName
(
raw_ostream
&
OS
,
unsigned
RegNo
)
const
{
assert
(
RegNo
!=
WebAssemblyFunctionInfo
::
UnusedReg
)
;
OS
<<
"(get_local "
<<
RegNo
<<
")"
;
}
</s>

WebAssembly
WebAssembly
WebAssembly
"(get_local "
")"


<s> EVT SITargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) { return MVT :: i1 ; } return MVT :: getVectorVT ( MVT :: i1 , VT . getVectorNumElements ( ) ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> const MipsRegisterInfo & MipsSEInstrInfo :: getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


"Pointer Checker requires MPX support on this target."

Return mode to be used for bounds or VOIDmode if bounds are not supported .


<s> void aarch64_general_init_builtins ( void ) { aarch64_init_fpsr_fpcr_builtins ( ) ; aarch64_init_fp16_types ( ) ; aarch64_init_bf16_types ( ) ; { aarch64_simd_switcher simd ; aarch64_init_simd_builtins ( ) ; } aarch64_init_crc32_builtins ( ) ; aarch64_init_builtin_rsqrt ( ) ; aarch64_init_rng_builtins ( ) ; aarch64_init_data_intrinsics ( ) ; tree ftype_jcvt = build_function_type_list ( intSI_type_node , double_type_node , NULL ) ; aarch64_builtin_decls [ AARCH64_JSCVT ] = aarch64_general_add_builtin ( "__builtin_aarch64_jcvtzs" , ftype_jcvt , AARCH64_JSCVT ) ; if ( ! TARGET_ILP32 ) aarch64_init_pauth_hint_builtins ( ) ; if ( TARGET_TME ) aarch64_init_tme_builtins ( ) ; if ( TARGET_MEMTAG ) aarch64_init_memtag_builtins ( ) ; } </s>

Initialize all builtins in the AARCH64_BUILTIN_GENERAL group .


<s> SDNode * PPCDAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc dl ; if ( PPCLowering -> getPointerTy ( ) == MVT :: i32 ) { if ( PPCSubTarget -> isTargetELF ( ) ) GlobalBaseReg = PPC :: R30 ; else GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: GPRC_NOR0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; if ( PPCSubTarget -> isTargetELF ( ) ) { unsigned TempReg = RegInfo -> createVirtualRegister ( & PPC :: GPRCRegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: GetGBRO ) , TempReg ) . addReg ( GlobalBaseReg ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: UpdateGBR ) ) . addReg ( GlobalBaseReg ) . addReg ( TempReg ) ; MF -> getInfo < PPCFunctionInfo > ( ) -> setUsesPICBase ( true ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: G8RC_NOX0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR8 ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR8 ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , PPCLowering -> getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

PowerPC PPC PPC MVT::i32 PPC PPC::R30 PPC::GPRC_NOR0RegClass PPC::MovePCtoLR PPC::MFLR PPC PPC::GPRCRegClass PPC::GetGBRO PPC::UpdateGBR PPC PPC::G8RC_NOX0RegClass PPC::MovePCtoLR8 PPC::MFLR8 PPC


<s> static bool tryAddingSymbolicOperand ( int64_t Value , bool isBranch , uint64_t Address , uint64_t Offset , uint64_t Width , MCInst & MI , const MCDisassembler * Decoder ) { return Decoder -> tryAddingSymbolicOperand ( MI , Value , Address , isBranch , Offset , Width ) ; } </s>

Try to add a symbolic operand instead of Value to the MCInst .


<s> bool ARMTargetLowering :: useLoadStackGuardNode ( ) const { return true ; } </s>

If this function returns true , SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic : :stackprotector .


<s>
void
AArch64FrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
const
AArch64InstrInfo
*
TII
=
static_cast
<
const
AArch64InstrInfo
*
>
(
MF
.
getTarget
(
)
.
getInstrInfo
(
)
)
;
DebugLoc
DL
=
I
->
getDebugLoc
(
)
;
int
Opc
=
I
->
getOpcode
(
)
;
bool
IsDestroy
=
Opc
==
TII
->
getCallFrameDestroyOpcode
(
)
;
uint64_t
CalleePopAmount
=
IsDestroy
I
->
getOperand
(
1
)
.
getImm
(
)
:
0
;
const
TargetFrameLowering
*
TFI
=
MF
.
getTarget
(
)
.
getFrameLowering
(
)
;
if
(
!
TFI
->
hasReservedCallFrame
(
MF
)
)
{
unsigned
Align
=
getStackAlignment
(
)
;
int64_t
Amount
=
I
->
getOperand
(
0
)
.
getImm
(
)
;
Amount
=
RoundUpToAlignment
(
Amount
,
Align
)
;
if
(
!
IsDestroy
)
Amount
=
Amount
;
if
(
CalleePopAmount
==
0
)
{
assert
(
Amount
>
0xffffff
&&
Amount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
Amount
,
TII
)
;
}
}
else
if
(
CalleePopAmount
!=
0
)
{
assert
(
CalleePopAmount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
CalleePopAmount
,
TII
)
;
}
MBB
.
erase
(
I
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool ARMAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'c' : case 'P' : printOperand ( MI , OpNo ) ; return false ; case 'Q' : if ( TM . getTargetData ( ) -> isLittleEndian ( ) ) break ; case 'R' : if ( TM . getTargetData ( ) -> isBigEndian ( ) ) break ; case 'H' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + 1 == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + 1 ) . isReg ( ) ) return true ; ++ OpNo ; } } printOperand ( MI , OpNo ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


"***** AArch64SpeculationHardening - automatic insertion of "

"***** AArch64SpeculationHardening - track control flow *****\n"

"***** AArch64SpeculationHardening - Lowering "

runOnMachineFunction - Emit the function body .


<s> void HexagonDAGToDAGISel :: Select ( SDNode * N ) { if ( N -> isMachineOpcode ( ) ) return N -> setNodeId ( - 1 ) ; switch ( N -> getOpcode ( ) ) { case ISD :: Constant : return SelectConstant ( N ) ; case ISD :: ConstantFP : return SelectConstantFP ( N ) ; case ISD :: FrameIndex : return SelectFrameIndex ( N ) ; case ISD :: BITCAST : return SelectBitcast ( N ) ; case ISD :: SHL : return SelectSHL ( N ) ; case ISD :: LOAD : return SelectLoad ( N ) ; case ISD :: STORE : return SelectStore ( N ) ; case ISD :: ZERO_EXTEND : return SelectZeroExtend ( N ) ; case ISD :: INTRINSIC_W_CHAIN : return SelectIntrinsicWChain ( N ) ; case ISD :: INTRINSIC_WO_CHAIN : return SelectIntrinsicWOChain ( N ) ; } if ( HST -> useHVXOps ( ) ) { switch ( N -> getOpcode ( ) ) { case ISD :: VECTOR_SHUFFLE : return SelectHvxShuffle ( N ) ; case HexagonISD :: VROR : return SelectHvxRor ( N ) ; } } SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .

Hexagon Hexagon 1 ISD::Constant ISD::ConstantFP ISD::FrameIndex ISD::BITCAST ISD::SHL ISD::LOAD ISD::STORE ISD::ZERO_EXTEND ISD::INTRINSIC_W_CHAIN ISD::INTRINSIC_WO_CHAIN ISD::VECTOR_SHUFFLE HexagonISD::VROR


"operation not permitted on type %<bfloat16_t%>"

Return the diagnostic message string if the binary operation OP is not permitted on TYPE1 and TYPE2 , NULL otherwise .


<s> static unsigned HOST_WIDE_INT compute_current_alignment ( unsigned HOST_WIDE_INT base_align , unsigned HOST_WIDE_INT offset ) { if ( offset == 0 ) return base_align ; return min ( base_align , offset & - offset ) ; } </s>

Compute the alignment of pointer+OFFSET where the original alignment of pointer was BASE_ALIGN .


<s> SDValue AArch64TargetLowering :: getSqrtResultForDenormInput ( SDValue Op , SelectionDAG & DAG ) const { return Op ; } </s>

Return a target-dependent result if the input operand is not suitable for use with a square root estimate calculation .


<s> static bool arc_vector_mode_supported_p ( machine_mode mode ) { switch ( mode ) { case E_V2HImode : return TARGET_PLUS_DMPY ; case E_V4HImode : case E_V2SImode : return TARGET_PLUS_QMACW ; case E_V4SImode : case E_V8HImode : return TARGET_SIMD_SET ; default : return false ; } } </s>

Implements target hook vector_mode_supported_p .


<s> static bool sparc_return_in_memory ( tree type , tree fntype ATTRIBUTE_UNUSED ) { if ( TARGET_ARCH32 ) return ( TYPE_MODE ( type ) == BLKmode || TYPE_MODE ( type ) == TFmode || ( TREE_CODE ( type ) == VECTOR_TYPE && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > 8 ) ) ; else return ( ( TYPE_MODE ( type ) == BLKmode && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > 32 ) ) ; } </s>

Handle the TARGET_RETURN_IN_MEMORY target hook . Specify whether to return the return value in memory .


"InlineAsmMemoryOperand 'v' constraint not handled."

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> static bool c6x_scalar_mode_supported_p ( machine_mode mode ) { if ( ALL_FIXED_POINT_MODE_P ( mode ) && GET_MODE_PRECISION ( mode ) <= 2 * BITS_PER_WORD ) return true ; return default_scalar_mode_supported_p ( mode ) ; } </s>


<s> void PPCAIXAsmPrinter :: emitEndOfAsmFile ( Module & M ) { if ( M . empty ( ) && TOCDataGlobalVars . empty ( ) ) return ; OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTOCBaseSection ( ) ) ; PPCTargetStreamer * TS = static_cast < PPCTargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; for ( auto & I : TOC ) { MCSectionXCOFF * TCEntry ; if ( I . first . second == MCSymbolRefExpr :: VariantKind :: VK_PPC_AIX_TLSGDM ) { SmallString < 128 > Name ; StringRef Prefix = "." ; Name += Prefix ; Name += I . first . first -> getName ( ) ; MCSymbol * S = OutContext . getOrCreateSymbol ( Name ) ; TCEntry = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForTOCEntry ( S , TM ) ) ; } else { TCEntry = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForTOCEntry ( I . first . first , TM ) ) ; } OutStreamer -> SwitchSection ( TCEntry ) ; OutStreamer -> emitLabel ( I . second ) ; if ( TS != nullptr ) TS -> emitTCEntry ( * I . first . first , I . first . second ) ; } for ( const auto * GV : TOCDataGlobalVars ) emitGlobalVariableHelper ( GV ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s>
void
print_operand_address
(
FILE
*
file
,
rtx
addr
)
{
struct
s390_address
ad
;
memset
(
&
ad
,
0
,
sizeof
(
s390_address
)
)
;
if
(
s390_loadrelative_operand_p
(
addr
,
,
)
)
{
if
(
!
TARGET_Z10
)
{
output_operand_lossage
(
"symbolic memory references are "
"only supported on z10 or later"
)
;
return
;
}
output_addr_const
(
file
,
addr
)
;
return
;
}
if
(
!
s390_decompose_address
(
addr
,
&
ad
)
||
(
ad
.
base
&&
!
REGNO_OK_FOR_BASE_P
(
REGNO
(
ad
.
base
)
)
)
||
(
ad
.
indx
&&
!
REGNO_OK_FOR_INDEX_P
(
REGNO
(
ad
.
indx
)
)
)
)
output_operand_lossage
(
"cannot decompose address"
)
;
if
(
ad
.
disp
)
output_addr_const
(
file
,
ad
.
disp
)
;
else
fprintf
(
file
,
"0"
)
;
if
(
ad
.
base
&&
ad
.
indx
)
fprintf
(
file
,
"(%s,%s)"
,
reg_names
[
REGNO
(
ad
.
indx
)
]
,
reg_names
[
REGNO
(
ad
.
base
)
]
)
;
else
if
(
ad
.
base
)
fprintf
(
file
,
"(%s)"
,
reg_names
[
REGNO
(
ad
.
base
)
]
)
;
}
</s>

Print the operand address represented by the rtx addr


<s>
SDValue
RISCVTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
report_fatal_error
(
"unimplemented operand"
)
;
case
ISD
::
GlobalAddress
:
return
lowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
lowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
lowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
lowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
lowerSELECT
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
lowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
lowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
lowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
SHL_PARTS
:
return
lowerShiftLeftParts
(
Op
,
DAG
)
;
case
ISD
::
SRA_PARTS
:
return
lowerShiftRightParts
(
Op
,
DAG
,
true
)
;
case
ISD
::
SRL_PARTS
:
return
lowerShiftRightParts
(
Op
,
DAG
,
false
)
;
case
ISD
::
BITCAST
:
{
assert
(
Subtarget
.
is64Bit
(
)
&&
Subtarget
.
hasStdExtF
(
)
&&
"Unexpected custom legalisation"
)
;
SDLoc
DL
(
Op
)
;
SDValue
Op0
=
Op
.
getOperand
(
0
)
;
if
(
Op
.
getValueType
(
)
!=
MVT
::
f32
||
Op0
.
getValueType
(
)
!=
MVT
::
i32
)
return
SDValue
(
)
;
SDValue
NewOp0
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
DL
,
MVT
::
i64
,
Op0
)
;
SDValue
FPConv
=
DAG
.
getNode
(
RISCVISD
::
FMV_W_X_RV64
,
DL
,
MVT
::
f32
,
NewOp0
)
;
return
FPConv
;
}
case
ISD
::
EXTRACT_VECTOR_ELT
:
assert
(
Subtarget
.
hasStdExtP
(
)
&&
"Unexpected custom legalisation"
)
;
return
lowerVectorExtract
(
Op
,
DAG
)
;
case
ISD
::
INSERT_VECTOR_ELT
:
assert
(
Subtarget
.
hasStdExtP
(
)
&&
"Unexpected custom legalisation"
)
;
return
lowerVectorInsert
(
Op
,
DAG
)
;
case
ISD
::
BUILD_VECTOR
:
assert
(
Subtarget
.
hasStdExtP
(
)
&&
"Unexpected custom legalisation"
)
;
return
lowerVectorBuild
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> void notice_update_cc ( rtx body , rtx_insn * insn ) { switch ( get_attr_cc ( insn ) ) { case CC_NONE : break ; case CC_NONE_0HIT : if ( cc_status . value1 != 0 && reg_overlap_mentioned_p ( recog_data . operand [ 0 ] , cc_status . value1 ) ) cc_status . value1 = 0 ; break ; case CC_SET_ZN : CC_STATUS_INIT ; cc_status . flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY ; cc_status . value1 = recog_data . operand [ 0 ] ; break ; case CC_SET_ZNV : CC_STATUS_INIT ; cc_status . flags |= CC_NO_CARRY ; cc_status . value1 = recog_data . operand [ 0 ] ; break ; case CC_COMPARE : CC_STATUS_INIT ; cc_status . value1 = SET_SRC ( body ) ; break ; case CC_CLOBBER : CC_STATUS_INIT ; break ; default : break ; } } </s>

On the 68000 , all the insns to store in an address register fail to set the cc 's . However , in some cases these instructions can make it possibly invalid to use the saved cc 's . In those cases we clear out some or all of the saved cc 's so they wo n't be used .


<s>
MachineInstr
*
RISCVInstrInfo
::
commuteInstructionImpl
(
MachineInstr
&
MI
,
bool
NewMI
,
unsigned
OpIdx1
,
unsigned
OpIdx2
)
const
{
auto
cloneIfNew
=
[
NewMI
]
(
MachineInstr
&
MI
)
->
MachineInstr
&
{
if
(
NewMI
)
return
*
MI
.
getParent
(
)
->
getParent
(
)
->
CloneMachineInstr
(
&
MI
)
;
return
MI
;
}
;
switch
(
MI
.
getOpcode
(
)
)
{
case
CASE_VFMA_SPLATS
(
FMACC
)
:
case
CASE_VFMA_SPLATS
(
FMADD
)
:
case
CASE_VFMA_SPLATS
(
FMSAC
)
:
case
CASE_VFMA_SPLATS
(
FMSUB
)
:
case
CASE_VFMA_SPLATS
(
FNMACC
)
:
case
CASE_VFMA_SPLATS
(
FNMADD
)
:
case
CASE_VFMA_SPLATS
(
FNMSAC
)
:
case
CASE_VFMA_SPLATS
(
FNMSUB
)
:
case
CASE_VFMA_OPCODE_LMULS
(
FMACC
,
VV
)
:
case
CASE_VFMA_OPCODE_LMULS
(
FMSAC
,
VV
)
:
case
CASE_VFMA_OPCODE_LMULS
(
FNMACC
,
VV
)
:
case
CASE_VFMA_OPCODE_LMULS
(
FNMSAC
,
VV
)
:
{
assert
(
(
OpIdx1
==
1
||
OpIdx2
==
1
)
&&
"Unexpected opcode index"
)
;
assert
(
(
OpIdx1
==
3
||
OpIdx2
==
3
)
&&
"Unexpected opcode index"
)
;
unsigned
Opc
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unexpected opcode"
)
;
CASE_VFMA_CHANGE_OPCODE_SPLATS
(
FMACC
,
FMADD
)
CASE_VFMA_CHANGE_OPCODE_SPLATS
(
FMADD
,
FMACC
)
CASE_VFMA_CHANGE_OPCODE_SPLATS
(
FMSAC
,
FMSUB
)
CASE_VFMA_CHANGE_OPCODE_SPLATS
(
FMSUB
,
FMSAC
)
CASE_VFMA_CHANGE_OPCODE_SPLATS
(
FNMACC
,
FNMADD
)
CASE_VFMA_CHANGE_OPCODE_SPLATS
(
FNMADD
,
FNMACC
)
CASE_VFMA_CHANGE_OPCODE_SPLATS
(
FNMSAC
,
FNMSUB
)
CASE_VFMA_CHANGE_OPCODE_SPLATS
(
FNMSUB
,
FNMSAC
)
CASE_VFMA_CHANGE_OPCODE_LMULS
(
FMACC
,
FMADD
,
VV
)
CASE_VFMA_CHANGE_OPCODE_LMULS
(
FMSAC
,
FMSUB
,
VV
)
CASE_VFMA_CHANGE_OPCODE_LMULS
(
FNMACC
,
FNMADD
,
VV
)
CASE_VFMA_CHANGE_OPCODE_LMULS
(
FNMSAC
,
FNMSUB
,
VV
)
}
auto
&
WorkingMI
=
cloneIfNew
(
MI
)
;
WorkingMI
.
setDesc
(
get
(
Opc
)
)
;
return
TargetInstrInfo
::
commuteInstructionImpl
(
WorkingMI
,
false
,
OpIdx1
,
OpIdx2
)
;
}
case
CASE_VFMA_OPCODE_LMULS
(
FMADD
,
VV
)
:
case
CASE_VFMA_OPCODE_LMULS
(
FMSUB
,
VV
)
:
case
CASE_VFMA_OPCODE_LMULS
(
FNMADD
,
VV
)
:
case
CASE_VFMA_OPCODE_LMULS
(
FNMSUB
,
VV
)
:
{
assert
(
(
OpIdx1
==
1
||
OpIdx2
==
1
)
&&
"Unexpected opcode index"
)
;
if
(
OpIdx1
==
3
||
OpIdx2
==
3
)
{
unsigned
Opc
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unexpected opcode"
)
;
CASE_VFMA_CHANGE_OPCODE_LMULS
(
FMADD
,
FMACC
,
VV
)
CASE_VFMA_CHANGE_OPCODE_LMULS
(
FMSUB
,
FMSAC
,
VV
)
CASE_VFMA_CHANGE_OPCODE_LMULS
(
FNMADD
,
FNMACC
,
VV
)
CASE_VFMA_CHANGE_OPCODE_LMULS
(
FNMSUB
,
FNMSAC
,
VV
)
}
auto
&
WorkingMI
=
cloneIfNew
(
MI
)
;
WorkingMI
.
setDesc
(
get
(
Opc
)
)
;
return
TargetInstrInfo
::
commuteInstructionImpl
(
WorkingMI
,
false
,
OpIdx1
,
OpIdx2
)
;
}
break
;
}
}
return
TargetInstrInfo
::
commuteInstructionImpl
(
MI
,
NewMI
,
OpIdx1
,
OpIdx2
)
;
}
</s>

Commutes the operands in the given instruction by changing the operands order and/or changing the instruction 's opcode and/or the immediate value operand .


<s> void SystemZPostRASchedStrategy :: initialize ( ScheduleDAGMI * dag ) { Available . clear ( ) ; LLVM_DEBUG ( HazardRec -> dumpState ( ) ; ) ; } </s>

Initialize the strategy after building the DAG for a new region .


<s> bool X86InstrInfo :: isCoalescableExtInstr ( const MachineInstr & MI , unsigned & SrcReg , unsigned & DstReg , unsigned & SubIdx ) const { switch ( MI . getOpcode ( ) ) { default : break ; case X86 :: MOVSX16rr8 : case X86 :: MOVZX16rr8 : case X86 :: MOVSX32rr8 : case X86 :: MOVZX32rr8 : case X86 :: MOVSX64rr8 : case X86 :: MOVZX64rr8 : if ( ! TM . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ) return false ; case X86 :: MOVSX32rr16 : case X86 :: MOVZX32rr16 : case X86 :: MOVSX64rr16 : case X86 :: MOVZX64rr16 : case X86 :: MOVSX64rr32 : case X86 :: MOVZX64rr32 : { if ( MI . getOperand ( 0 ) . getSubReg ( ) || MI . getOperand ( 1 ) . getSubReg ( ) ) return false ; SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; DstReg = MI . getOperand ( 0 ) . getReg ( ) ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( 0 ) ; break ; case X86 :: MOVSX16rr8 : case X86 :: MOVZX16rr8 : case X86 :: MOVSX32rr8 : case X86 :: MOVZX32rr8 : case X86 :: MOVSX64rr8 : case X86 :: MOVZX64rr8 : SubIdx = X86 :: sub_8bit ; break ; case X86 :: MOVSX32rr16 : case X86 :: MOVZX32rr16 : case X86 :: MOVSX64rr16 : case X86 :: MOVZX64rr16 : SubIdx = X86 :: sub_16bit ; break ; case X86 :: MOVSX64rr32 : case X86 :: MOVZX64rr32 : SubIdx = X86 :: sub_32bit ; break ; } return true ; } } return false ; } </s>

isCoalescableExtInstr - Return true if the instruction is a `` coalescable '' extension instruction .


<s> bool GCNTTIImpl :: areInlineCompatible ( const Function * Caller , const Function * Callee ) const { const TargetMachine & TM = getTLI ( ) -> getTargetMachine ( ) ; const GCNSubtarget * CallerST = static_cast < const GCNSubtarget * > ( TM . getSubtargetImpl ( * Caller ) ) ; const GCNSubtarget * CalleeST = static_cast < const GCNSubtarget * > ( TM . getSubtargetImpl ( * Callee ) ) ; const FeatureBitset & CallerBits = CallerST -> getFeatureBits ( ) ; const FeatureBitset & CalleeBits = CalleeST -> getFeatureBits ( ) ; FeatureBitset RealCallerBits = CallerBits & ~ InlineFeatureIgnoreList ; FeatureBitset RealCalleeBits = CalleeBits & ~ InlineFeatureIgnoreList ; if ( ( RealCallerBits & RealCalleeBits ) != RealCalleeBits ) return false ; AMDGPU :: SIModeRegisterDefaults CallerMode ( * Caller ) ; AMDGPU :: SIModeRegisterDefaults CalleeMode ( * Callee ) ; if ( ! CallerMode . isInlineCompatible ( CalleeMode ) ) return false ; if ( InlineMaxBB && ! Callee -> hasFnAttribute ( Attribute :: InlineHint ) ) { size_t BBSize = Caller -> size ( ) + Callee -> size ( ) - 1 ; return BBSize <= InlineMaxBB ; } return true ; } </s>

Determine whether a callee with the given TLI can be inlined into caller with this TLI , based on 'nobuiltin ' attributes .

AMDGPU AMDGPU::SIModeRegisterDefaults AMDGPU::SIModeRegisterDefaults 1


<s> static int cris_reg_saved_in_regsave_area ( unsigned int regno ) { return ( ( ( df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) ) ) && ( regno != HARD_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) && regno != CRIS_SRP_REGNUM ) || ( crtl -> calls_eh_return && ( regno == EH_RETURN_DATA_REGNO ( 0 ) || regno == EH_RETURN_DATA_REGNO ( 1 ) || regno == EH_RETURN_DATA_REGNO ( 2 ) || regno == EH_RETURN_DATA_REGNO ( 3 ) ) ) ; } </s>

Return nonzero if REGNO is an ordinary register that * needs * to be saved together with other registers , possibly by a MOVEM instruction , or is saved for target-independent reasons . There may be target-dependent reasons to save the register anyway ; this is just a wrapper for a complicated conditional .


<s> static bool fixed_reg_p ( int reg ) { if ( reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ( ( DEFAULT_ABI == ABI_V4 && flag_pic ) || ( DEFAULT_ABI == ABI_DARWIN && flag_pic ) || ( TARGET_TOC && TARGET_MINIMAL_TOC ) ) ) return false ; return fixed_regs [ reg ] ; } </s>

Return whether REG is a global user reg or has been specifed by -ffixed-REG . We should not restore these , and so can not use lmw or out-of-line restore functions if there are any . We also ca n't save them ( well , emit frame notes for them ) , because frame unwinding during exception handling will restore saved registers .


<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < 512 > Key ; Key . reserve ( CPU . size ( ) + FS . size ( ) ) ; Key += CPU ; Key += FS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) Key += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; unsigned CPUFSWidth = Key . size ( ) ; unsigned PreferVectorWidthOverride = 0 ; if ( F . hasFnAttribute ( "prefer-vector-width" ) ) { StringRef Val = F . getFnAttribute ( "prefer-vector-width" ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( 0 , Width ) ) { Key += ",prefer-vector-width=" ; Key += Val ; PreferVectorWidthOverride = Width ; } } FS = Key . slice ( CPU . size ( ) , CPUFSWidth ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < X86Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride , PreferVectorWidthOverride ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool AArch64AsmParser :: ParseDirective ( AsmToken DirectiveID ) { const MCObjectFileInfo :: Environment Format = getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ; bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; bool IsCOFF = Format == MCObjectFileInfo :: IsCOFF ; StringRef IDVal = DirectiveID . getIdentifier ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == ".hword" ) return parseDirectiveWord ( 2 , Loc ) ; if ( IDVal == ".word" ) return parseDirectiveWord ( 4 , Loc ) ; if ( IDVal == ".xword" ) return parseDirectiveWord ( 8 , Loc ) ; if ( IDVal == ".tlsdesccall" ) return parseDirectiveTLSDescCall ( Loc ) ; if ( IDVal == ".ltorg" || IDVal == ".pool" ) return parseDirectiveLtorg ( Loc ) ; if ( IDVal == ".unreq" ) return parseDirectiveUnreq ( Loc ) ; if ( ! IsMachO && ! IsCOFF ) { if ( IDVal == ".inst" ) return parseDirectiveInst ( Loc ) ; } return parseDirectiveLOH ( IDVal , Loc ) ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> static rtx altivec_expand_vec_ext_builtin ( tree exp , rtx target ) { machine_mode tmode , mode0 ; tree arg0 , arg1 ; rtx op0 ; rtx op1 ; arg0 = CALL_EXPR_ARG ( exp , 0 ) ; arg1 = CALL_EXPR_ARG ( exp , 1 ) ; op0 = expand_normal ( arg0 ) ; op1 = expand_normal ( arg1 ) ; if ( TREE_CODE ( arg1 ) == INTEGER_CST ) ( void ) get_element_number ( TREE_TYPE ( arg0 ) , arg1 ) ; tmode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( arg0 ) ) ) ; mode0 = TYPE_MODE ( TREE_TYPE ( arg0 ) ) ; gcc_assert ( VECTOR_MODE_P ( mode0 ) ) ; op0 = force_reg ( mode0 , op0 ) ; if ( optimize || ! target || ! register_operand ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; rs6000_expand_vector_extract ( target , op0 , op1 ) ; return target ; } </s>


<s> bool AArch64PassConfig :: addRegBankSelect ( ) { addPass ( new RegBankSelect ( ) ) ; return false ; } </s>

This method should install a register bank selector pass , which assigns register banks to virtual registers without a register class or register banks .


<s> static void mips_block_move_straight ( rtx dest , rtx src , HOST_WIDE_INT length ) { HOST_WIDE_INT offset , delta ; unsigned HOST_WIDE_INT bits ; int i ; machine_mode mode ; rtx * regs ; if ( ! ISA_HAS_LWL_LWR ) bits = MIN ( BITS_PER_WORD , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) ) ; else { if ( MEM_ALIGN ( src ) == BITS_PER_WORD / 2 && MEM_ALIGN ( dest ) == BITS_PER_WORD / 2 ) bits = BITS_PER_WORD / 2 ; else bits = BITS_PER_WORD ; } mode = mode_for_size ( bits , MODE_INT , 0 ) ; delta = bits / BITS_PER_UNIT ; regs = XALLOCAVEC ( rtx , length / delta ) ; for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) { regs [ i ] = gen_reg_rtx ( mode ) ; if ( MEM_ALIGN ( src ) >= bits ) mips_emit_move ( regs [ i ] , adjust_address ( src , mode , offset ) ) ; else { rtx part = adjust_address ( src , BLKmode , offset ) ; set_mem_size ( part , delta ) ; if ( ! mips_expand_ext_as_unaligned_load ( regs [ i ] , part , bits , 0 , 0 ) ) gcc_unreachable ( ) ; } } for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) if ( MEM_ALIGN ( dest ) >= bits ) mips_emit_move ( adjust_address ( dest , mode , offset ) , regs [ i ] ) ; else { rtx part = adjust_address ( dest , BLKmode , offset ) ; set_mem_size ( part , delta ) ; if ( ! mips_expand_ins_as_unaligned_store ( part , regs [ i ] , bits , 0 ) ) gcc_unreachable ( ) ; } if ( offset < length ) { src = adjust_address ( src , BLKmode , offset ) ; dest = adjust_address ( dest , BLKmode , offset ) ; move_by_pieces ( dest , src , length - offset , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) , 0 ) ; } } </s>

Emit straight-line code to move LENGTH bytes from SRC to DEST . Assume that the areas do not overlap .


<s> void HexagonInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { if ( Hexagon :: IntRegsRegClass . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: TFR ) , DestReg ) . addReg ( SrcReg ) ; return ; } if ( Hexagon :: DoubleRegsRegClass . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: TFR64 ) , DestReg ) . addReg ( SrcReg ) ; return ; } if ( Hexagon :: PredRegsRegClass . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: OR_pp ) , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg ) ; return ; } if ( Hexagon :: DoubleRegsRegClass . contains ( DestReg ) && Hexagon :: IntRegsRegClass . contains ( SrcReg ) ) { if ( SrcReg == RI . getSubReg ( DestReg , Hexagon :: subreg_loreg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: TFRI ) , ( RI . getSubReg ( DestReg , Hexagon :: subreg_hireg ) ) ) . addImm ( 0 ) ; } else { BuildMI ( MBB , I , DL , get ( Hexagon :: TFR ) , ( RI . getSubReg ( DestReg , Hexagon :: subreg_loreg ) ) ) . addReg ( SrcReg ) ; BuildMI ( MBB , I , DL , get ( Hexagon :: TFRI ) , ( RI . getSubReg ( DestReg , Hexagon :: subreg_hireg ) ) ) . addImm ( 0 ) ; } return ; } if ( Hexagon :: CRRegsRegClass . contains ( DestReg ) && Hexagon :: IntRegsRegClass . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: TFCR ) , DestReg ) . addReg ( SrcReg ) ; return ; } llvm_unreachable ( "Unimplemented" ) ; } </s>


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
)
;
break
;
case
ISD
::
SIGN_EXTEND
:
case
ISD
::
ZERO_EXTEND
:
Res
=
ExpandVectorExtension
(
N
,
DAG
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
READCYCLECOUNTER
:
ReplaceREADCYCLECOUNTER
(
N
,
Results
,
DAG
,
Subtarget
)
;
return
;
case
ISD
::
ATOMIC_STORE
:
case
ISD
::
ATOMIC_LOAD
:
case
ISD
::
ATOMIC_LOAD_ADD
:
case
ISD
::
ATOMIC_LOAD_AND
:
case
ISD
::
ATOMIC_LOAD_NAND
:
case
ISD
::
ATOMIC_LOAD_OR
:
case
ISD
::
ATOMIC_LOAD_SUB
:
case
ISD
::
ATOMIC_LOAD_XOR
:
case
ISD
::
ATOMIC_SWAP
:
case
ISD
::
ATOMIC_CMP_SWAP
:
case
ISD
::
ATOMIC_LOAD_MIN
:
case
ISD
::
ATOMIC_LOAD_UMIN
:
case
ISD
::
ATOMIC_LOAD_MAX
:
case
ISD
::
ATOMIC_LOAD_UMAX
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
)
;
return
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> bool isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const override { return true ; } </s>

Returns true if a cast between SrcAS and DestAS is a noop .


<s> static bool classof ( const SDNode * N ) { return N -> getOpcode ( ) == X86ISD :: MSCATTER ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> bool SIWholeQuadMode :: runOnMachineFunction ( MachineFunction & MF ) { Instructions . clear ( ) ; Blocks . clear ( ) ; LiveMaskQueries . clear ( ) ; LowerToCopyInstrs . clear ( ) ; CallingConv = MF . getFunction ( ) -> getCallingConv ( ) ; const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; LIS = & getAnalysis < LiveIntervals > ( ) ; char GlobalFlags = analyzeFunction ( MF ) ; unsigned LiveMaskReg = 0 ; if ( ! ( GlobalFlags & StateWQM ) ) { lowerLiveMaskQueries ( AMDGPU :: EXEC ) ; if ( ! ( GlobalFlags & StateWWM ) ) return ! LiveMaskQueries . empty ( ) ; } else { MachineBasicBlock & Entry = MF . front ( ) ; MachineBasicBlock :: iterator EntryMI = Entry . getFirstNonPHI ( ) ; if ( GlobalFlags & StateExact || ! LiveMaskQueries . empty ( ) ) { LiveMaskReg = MRI -> createVirtualRegister ( & AMDGPU :: SReg_64RegClass ) ; MachineInstr * MI = BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( AMDGPU :: COPY ) , LiveMaskReg ) . addReg ( AMDGPU :: EXEC ) ; LIS -> InsertMachineInstrInMaps ( * MI ) ; } lowerLiveMaskQueries ( LiveMaskReg ) ; if ( GlobalFlags == StateWQM ) { BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( AMDGPU :: S_WQM_B64 ) , AMDGPU :: EXEC ) . addReg ( AMDGPU :: EXEC ) ; lowerCopyInstrs ( ) ; return true ; } } DEBUG ( printInfo ( ) ) ; lowerCopyInstrs ( ) ; for ( auto BII : Blocks ) processBlock ( * BII . first , LiveMaskReg , BII . first == & * MF . begin ( ) ) ; LIS -> removeRegUnit ( * MCRegUnitIterator ( AMDGPU :: SCC , TRI ) ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .

AMDGPU SI SI SI 0 AMDGPU::EXEC AMDGPU::SReg_64RegClass AMDGPU::COPY AMDGPU::EXEC AMDGPU::S_WQM_B64 AMDGPU::EXEC AMDGPU::EXEC AMDGPU::SCC


<s> const ARMRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void AMDGPUFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


"Couldn't get MachineMemOperand for store to stack."

"Only support 4-byte loads from stack now."

"Only support GPR32 stores to stack now."

Load the specified register of the given register class from the specified stack frame index .


"BasePointer is not implemented on AIX yet."

getBasePointerSaveOffset - Return the previous frame offset to save the base pointer .


"%qE redeclared with conflicting %qs attributes"


<s> void ARMElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; if ( TM . getSubtarget < ARMSubtarget > ( ) . isAAPCS_ABI ( ) ) { StaticCtorSection = getContext ( ) . getELFSection ( ".init_array" , MCSectionELF :: SHT_INIT_ARRAY , MCSectionELF :: SHF_WRITE | MCSectionELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; StaticDtorSection = getContext ( ) . getELFSection ( ".fini_array" , MCSectionELF :: SHT_FINI_ARRAY , MCSectionELF :: SHF_WRITE | MCSectionELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; } } </s>

This method must be called before any actual lowering is done .


"block as it would convert a WLS from forward to a "

Checks if loop has a backwards branching WLS , and if possible , fixes it .


<s> SDValue X86SelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { if ( DstPtrInfo . getAddrSpace ( ) >= 256 || SrcPtrInfo . getAddrSpace ( ) >= 256 ) return SDValue ( ) ; const MCPhysReg ClobberSet [ ] = { X86 :: RCX , X86 :: RSI , X86 :: RDI , X86 :: ECX , X86 :: ESI , X86 :: EDI } ; if ( isBaseRegConflictPossible ( DAG , ClobberSet ) ) return SDValue ( ) ; const X86Subtarget & Subtarget = DAG . getMachineFunction ( ) . getSubtarget < X86Subtarget > ( ) ; if ( ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ) return emitConstantSizeRepmov ( DAG , Subtarget , dl , Chain , Dst , Src , ConstantSize -> getZExtValue ( ) , Size . getValueType ( ) , Alignment . value ( ) , isVolatile , AlwaysInline , DstPtrInfo , SrcPtrInfo ) ; return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .


<s> SDValue Z80TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , getRetCCAssignFn ( CallConv ) ) ; for ( unsigned I = 0 , E = RVLocs . size ( ) ; I != E ; ++ I ) { Chain = DAG . getCopyFromReg ( Chain , DL , RVLocs [ I ] . getLocReg ( ) , RVLocs [ I ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s>
void
X86InstrInfo
::
insertSelect
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DstReg
,
ArrayRef
<
MachineOperand
>
Cond
,
unsigned
TrueReg
,
unsigned
FalseReg
)
const
{
MachineRegisterInfo
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
const
TargetRegisterInfo
&
TRI
=
*
MRI
.
getTargetRegisterInfo
(
)
;
const
TargetRegisterClass
&
RC
=
*
MRI
.
getRegClass
(
DstReg
)
;
assert
(
Cond
.
size
(
)
==
1
&&
"Invalid Cond array"
)
;
unsigned
Opc
=
X86
::
getCMovOpcode
(
TRI
.
getRegSizeInBits
(
RC
)
/
8
,
false
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DstReg
)
.
addReg
(
FalseReg
)
.
addReg
(
TrueReg
)
.
addImm
(
Cond
[
0
]
.
getImm
(
)
)
;
}
</s>

Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true , and FalseReg to DstReg when Cond is false .


<s>
void
X86InstrInfo
::
reMaterialize
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
unsigned
SubIdx
,
const
MachineInstr
&
Orig
,
const
TargetRegisterInfo
&
TRI
)
const
{
bool
ClobbersEFLAGS
=
false
;
for
(
const
MachineOperand
&
MO
:
Orig
.
operands
(
)
)
{
if
(
MO
.
isReg
(
)
&&
MO
.
isDef
(
)
&&
MO
.
getReg
(
)
==
X86
::
EFLAGS
)
{
ClobbersEFLAGS
=
true
;
break
;
}
}
if
(
ClobbersEFLAGS
&&
!
isSafeToClobberEFLAGS
(
MBB
,
I
)
)
{
int
Value
;
switch
(
Orig
.
getOpcode
(
)
)
{
case
X86
::
MOV32r0
:
Value
=
0
;
break
;
case
X86
::
MOV32r1
:
Value
=
1
;
break
;
case
X86
::
MOV32r_1
:
Value
=
1
;
break
;
default
:
llvm_unreachable
(
"Unexpected instruction!"
)
;
}
const
DebugLoc
&
DL
=
Orig
.
getDebugLoc
(
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
X86
::
MOV32ri
)
)
.
add
(
Orig
.
getOperand
(
0
)
)
.
addImm
(
Value
)
;
}
else
{
MachineInstr
*
MI
=
MBB
.
getParent
(
)
->
CloneMachineInstr
(
&
Orig
)
;
MBB
.
insert
(
I
,
MI
)
;
}
MachineInstr
&
NewMI
=
*
std
::
prev
(
I
)
;
NewMI
.
substituteRegister
(
Orig
.
getOperand
(
0
)
.
getReg
(
)
,
DestReg
,
SubIdx
,
TRI
)
;
}
</s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s> EVT RISCVTargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & Context , EVT VT ) const { if ( ! VT . isVector ( ) ) return getPointerTy ( DL ) ; if ( Subtarget . hasStdExtV ( ) && ( VT . isScalableVector ( ) || Subtarget . useRVVForFixedLengthVectors ( ) ) ) return EVT :: getVectorVT ( Context , MVT :: i1 , VT . getVectorElementCount ( ) ) ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> StringRef X86TargetLowering :: getStackProbeSymbolName ( MachineFunction & MF ) const { if ( hasInlineStackProbe ( MF ) ) return "" ; if ( MF . getFunction ( ) . hasFnAttribute ( "probe-stack" ) ) return MF . getFunction ( ) . getFnAttribute ( "probe-stack" ) . getValueAsString ( ) ; if ( ! Subtarget . isOSWindows ( ) || Subtarget . isTargetMachO ( ) || MF . getFunction ( ) . hasFnAttribute ( "no-stack-arg-probe" ) ) return "" ; if ( Subtarget . is64Bit ( ) ) return Subtarget . isTargetCygMing ( ) ? "___chkstk_ms" : "__chkstk" ; return Subtarget . isTargetCygMing ( ) ? "_alloca" : "_chkstk" ; } </s>

Returns the name of the symbol used to emit stack probes or the empty string if not applicable .


<s> bool MipsHazardSchedule :: runOnMachineFunction ( MachineFunction & MF ) { const MipsSubtarget * STI = & static_cast < const MipsSubtarget & > ( MF . getSubtarget ( ) ) ; if ( ! STI -> hasMips32r6 ( ) || STI -> inMicroMipsMode ( ) ) return false ; bool Changed = false ; const MipsInstrInfo * TII = STI -> getInstrInfo ( ) ; for ( MachineFunction :: iterator FI = MF . begin ( ) ; FI != MF . end ( ) ; ++ FI ) { for ( Iter I = FI -> begin ( ) ; I != FI -> end ( ) ; ++ I ) { if ( ! TII -> HasForbiddenSlot ( * I ) ) continue ; bool InsertNop = false ; if ( std :: next ( I ) != FI -> end ( ) && ! TII -> SafeInForbiddenSlot ( * getNextMachineInstr ( std :: next ( I ) ) ) ) { InsertNop = true ; } else { for ( auto * Succ : FI -> successors ( ) ) { if ( FI -> isLayoutSuccessor ( Succ ) && getNextMachineInstr ( Succ -> begin ( ) ) != Succ -> end ( ) && ! TII -> SafeInForbiddenSlot ( * getNextMachineInstr ( Succ -> begin ( ) ) ) ) { InsertNop = true ; break ; } } } if ( InsertNop ) { Changed = true ; MIBundleBuilder ( & * I ) . append ( BuildMI ( MF , I -> getDebugLoc ( ) , TII -> get ( Mips :: NOP ) ) ) ; NumInsertedNops ++ ; } } } return Changed ; } </s>

Mips Mips Mips Mips Mips Mips Mips Mips::NOP


<s> iterator end ( ) { return ( Packet . end ( ) ) ; } </s>

Get a const_iterator to the end of the symbol table .


"insertBranch must not be told to insert a fallthrough"

"SystemZ branch conditions have one component!"

"Unconditional branch with multiple successors!"

Insert branch code into the end of the specified MachineBasicBlock .


<s>
virtual
bool
runOnMachineFunction
(
MachineFunction
&
MF
)
{
RootScope
=
getAnalysis
<
PatmosSPBundling
>
(
)
.
getRootScope
(
)
;
PMFI
=
MF
.
getInfo
<
PatmosMachineFunctionInfo
>
(
)
;
bool
changed
=
false
;
if
(
MF
.
getInfo
<
PatmosMachineFunctionInfo
>
(
)
->
isSinglePath
(
)
)
{
DEBUG
(
dbgs
(
)
<<
"[Single-Path] Reducing "
<<
MF
.
getFunction
(
)
->
getName
(
)
<<
"\n"
)
;
doReduceFunction
(
MF
)
;
changed
|=
true
;
}
return
changed
;
}
</s>

Patmos
Patmos
Patmos
Patmos
"[Single-Path] Reducing "
"\n"


<s> unsigned MipsFunctionInfo :: getGlobalBaseReg ( ) { if ( GlobalBaseReg ) return GlobalBaseReg ; const MipsSubtarget & ST = MF . getTarget ( ) . getSubtarget < MipsSubtarget > ( ) ; if ( FixGlobalBaseReg ) return GlobalBaseReg = ST . isABI_N64 ( ) ? Mips :: GP_64 : Mips :: GP ; const TargetRegisterClass * RC ; RC = ST . isABI_N64 ( ) ? Mips :: CPU64RegsRegisterClass : Mips :: CPURegsRegisterClass ; return GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

Mips Mips Mips Mips Mips::GP_64 Mips::GP Mips::CPU64RegsRegisterClass Mips::CPURegsRegisterClass


<s> void aarch64_register_fma_steering ( ) { opt_pass * pass_fma_steering = make_pass_fma_steering ( g ) ; struct register_pass_info fma_steering_info = { pass_fma_steering , "rnreg" , 1 , PASS_POS_INSERT_AFTER } ; register_pass ( & fma_steering_info ) ; } </s>

Register the FMA steering pass to the pass manager .


<s> void sparc_profile_hook ( int labelno ) { char buf [ 32 ] ; rtx lab , fun ; fun = gen_rtx_SYMBOL_REF ( Pmode , MCOUNT_FUNCTION ) ; if ( NO_PROFILE_COUNTERS ) { emit_library_call ( fun , LCT_NORMAL , VOIDmode ) ; } else { ASM_GENERATE_INTERNAL_LABEL ( buf , "LP" , labelno ) ; lab = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; emit_library_call ( fun , LCT_NORMAL , VOIDmode , lab , Pmode ) ; } } </s>

Output rtl to increment the profiler label LABELNO for profiling a function entry .


<s> static void mn10300_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain_value ) { rtx mem , disp , fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; disp = expand_binop ( SImode , sub_optab , fnaddr , plus_constant ( Pmode , XEXP ( m_tramp , 0 ) , 11 ) , NULL_RTX , 1 , OPTAB_DIRECT ) ; mem = adjust_address ( m_tramp , SImode , 0 ) ; emit_move_insn ( mem , gen_int_mode ( 0xddfc0028 , SImode ) ) ; mem = adjust_address ( m_tramp , SImode , 4 ) ; emit_move_insn ( mem , chain_value ) ; mem = adjust_address ( m_tramp , SImode , 8 ) ; emit_move_insn ( mem , gen_int_mode ( 0xdc00edf8 , SImode ) ) ; mem = adjust_address ( m_tramp , SImode , 12 ) ; emit_move_insn ( mem , disp ) ; } </s>

Worker function for TARGET_TRAMPOLINE_INIT .


<s> static unsigned int rs6000_parm_offset ( void ) { return ( DEFAULT_ABI == ABI_V4 ? 2 : DEFAULT_ABI == ABI_ELFv2 ? 4 : 6 ) ; } </s>

The offset in words to the start of the parameter save area .


"Unexpected data type for Gather/Scatter"

Calculate the cost of Gather / Scatter operation .


<s> static int neon_endian_lane_map ( machine_mode mode , int lane ) { if ( BYTES_BIG_ENDIAN ) { int nelems = GET_MODE_NUNITS ( mode ) ; lane = ( nelems - 1 - lane ) ; if ( GET_MODE_SIZE ( mode ) == 16 ) lane = lane ^ ( nelems / 2 ) ; } return lane ; } </s>

Map lane ordering between architectural lane order , and GCC lane order , taking into account ABI . See comment above output_move_neon for details .


This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly


<s> rtx avr_function_value ( tree type , tree func ATTRIBUTE_UNUSED ) { unsigned int offs ; if ( TYPE_MODE ( type ) != BLKmode ) return avr_libcall_value ( TYPE_MODE ( type ) ) ; offs = int_size_in_bytes ( type ) ; if ( offs < 2 ) offs = 2 ; if ( offs > 2 && offs < GET_MODE_SIZE ( SImode ) ) offs = GET_MODE_SIZE ( SImode ) ; else if ( offs > GET_MODE_SIZE ( SImode ) && offs < GET_MODE_SIZE ( DImode ) ) offs = GET_MODE_SIZE ( DImode ) ; return gen_rtx_REG ( BLKmode , RET_REGISTER + 2 - offs ) ; } </s>

Create an RTX representing the place where a function returns a value of data type VALTYPE .


<s>
void
pa_output_ascii
(
FILE
*
file
,
const
char
*
p
,
int
size
)
{
int
i
;
int
chars_output
;
unsigned
char
partial_output
[
16
]
;
fputs
(
"\t.STRING \""
,
file
)
;
chars_output
=
0
;
for
(
i
=
0
;
i
<
size
;
i
+=
4
)
{
int
co
=
0
;
int
io
=
0
;
for
(
io
=
0
,
co
=
0
;
io
<
MIN
(
4
,
size
i
)
;
io
++
)
{
unsigned
int
c
=
(
unsigned
char
)
p
[
i
+
io
]
;
if
(
c
==
'\"'
||
c
==
'\\'
)
partial_output
[
co
++
]
=
'\\'
;
if
(
c
>=
' '
&&
c
<
0177
)
partial_output
[
co
++
]
=
c
;
else
{
unsigned
int
hexd
;
partial_output
[
co
++
]
=
'\\'
;
partial_output
[
co
++
]
=
'x'
;
hexd
=
c
/
16
0
+
'0'
;
if
(
hexd
>
'9'
)
hexd
-=
'9'
'a'
+
1
;
partial_output
[
co
++
]
=
hexd
;
hexd
=
c
%
16
0
+
'0'
;
if
(
hexd
>
'9'
)
hexd
-=
'9'
'a'
+
1
;
partial_output
[
co
++
]
=
hexd
;
}
}
if
(
chars_output
+
co
>
243
)
{
fputs
(
"\"\n\t.STRING \""
,
file
)
;
chars_output
=
0
;
}
fwrite
(
partial_output
,
1
,
(
size_t
)
co
,
file
)
;
chars_output
+=
co
;
co
=
0
;
}
fputs
(
"\"\n"
,
file
)
;
}
</s>


<s> bool X86TargetLowering :: shouldUseStrictFP_TO_INT ( EVT FpVT , EVT IntVT , bool IsSigned ) const { return ! IsSigned && FpVT == MVT :: f80 && Subtarget . hasCMov ( ) ; } </s>

Return true if it is more correct/profitable to use strict FP_TO_INT conversion operations - canonicalizing the FP source value instead of converting all cases and then selecting based on value .