<s> bool MipsCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) { return false ; } for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( Arg . getType ( ) ) ) return false ; } MachineFunction & MF = MIRBuilder . getMF ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const MipsTargetLowering & TLI = * getTLI < MipsTargetLowering > ( ) ; SmallVector < ArgInfo , 8 > ArgInfos ; SmallVector < unsigned , 8 > OrigArgIndices ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ i ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , i + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( AInfo , i , ArgInfos , OrigArgIndices ) ; ++ i ; } SmallVector < ISD :: InputArg , 8 > Ins ; subTargetRegTypeForCallingConv ( MIRBuilder , ArgInfos , OrigArgIndices , [ & ] ( ISD :: ArgFlagsTy flags , EVT vt , EVT argvt , bool used , unsigned origIdx , unsigned partOffs ) { Ins . emplace_back ( flags , vt , argvt , used , origIdx , partOffs ) ; } ) ; SmallVector < CCValAssign , 16 > ArgLocs ; MipsCCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; const MipsTargetMachine & TM = static_cast < const MipsTargetMachine & > ( MF . getTarget ( ) ) ; const MipsABIInfo & ABI = TM . getABI ( ) ; CCInfo . AllocateStack ( ABI . GetCalleeAllocdArgSizeInBytes ( F . getCallingConv ( ) ) , 1 ) ; CCInfo . AnalyzeFormalArguments ( Ins , TLI . CCAssignFnForCall ( ) ) ; setLocInfo ( ArgLocs , Ins ) ; IncomingValueHandler Handler ( MIRBuilder , MF . getRegInfo ( ) ) ; if ( ! Handler . handle ( ArgLocs , ArgInfos ) ) return false ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> void ix86_split_fp_branch ( enum rtx_code code , rtx op1 , rtx op2 , rtx target1 , rtx target2 , rtx tmp ) { rtx condition ; rtx i ; if ( target2 != pc_rtx ) { std :: swap ( target1 , target2 ) ; code = reverse_condition_maybe_unordered ( code ) ; } condition = ix86_expand_fp_compare ( code , op1 , op2 , tmp ) ; i = emit_jump_insn ( gen_rtx_SET ( pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , condition , target1 , target2 ) ) ) ; if ( split_branch_probability >= 0 ) add_int_reg_note ( i , REG_BR_PROB , split_branch_probability ) ; } </s>

Split branch based on floating point condition .


<s> bool pa_cannot_change_mode_class ( machine_mode from , machine_mode to , enum reg_class rclass ) { if ( from == to ) return false ; if ( COMPLEX_MODE_P ( from ) || VECTOR_MODE_P ( from ) || COMPLEX_MODE_P ( to ) || VECTOR_MODE_P ( to ) ) return true ; if ( GET_MODE_SIZE ( from ) == GET_MODE_SIZE ( to ) ) return false ; if ( MAYBE_FP_REG_CLASS_P ( rclass ) ) return true ; if ( GET_MODE_SIZE ( to ) > UNITS_PER_WORD && GET_MODE_SIZE ( to ) > GET_MODE_SIZE ( from ) ) return true ; return false ; } </s>

Return true if a change from mode FROM to mode TO for a register in register class RCLASS is invalid .


<s>
bool
ARMBlockPlacement
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
const
ARMSubtarget
&
ST
=
static_cast
<
const
ARMSubtarget
&
>
(
MF
.
getSubtarget
(
)
)
;
if
(
!
ST
.
hasLOB
(
)
)
return
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
DEBUG_PREFIX
<<
"Running on "
<<
MF
.
getName
(
)
<<
"\n"
)
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
TII
=
static_cast
<
const
ARMBaseInstrInfo
*
>
(
ST
.
getInstrInfo
(
)
)
;
BBUtils
=
std
::
unique_ptr
<
ARMBasicBlockUtils
>
(
new
ARMBasicBlockUtils
(
MF
)
)
;
MF
.
RenumberBlocks
(
)
;
BBUtils
->
computeAllBlockSizes
(
)
;
BBUtils
->
adjustBBOffsetsAfter
(
&
MF
.
front
(
)
)
;
bool
Changed
=
false
;
RevertedWhileLoops
.
clear
(
)
;
for
(
auto
*
ML
:
*
MLI
)
Changed
|=
processPostOrderLoops
(
ML
)
;
for
(
auto
*
WlsInstr
:
RevertedWhileLoops
)
Changed
|=
revertWhileToDoLoop
(
WlsInstr
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

ARM
ARM
ARM
ARM
"Running on "
"\n"
ARM
ARM
ARM


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetOptions & Options ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , ARMProcClass ( None ) , stackAlignment ( 4 ) , CPUString ( CPU ) , TargetTriple ( TT ) , Options ( Options ) , TargetABI ( ARM_ABI_APCS ) { initializeEnvironment ( ) ; resetSubtargetFeatures ( CPU , FS ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static __inline unsigned long long sh_media_LDHI_L ( void * p , int s ) { return __builtin_sh_media_LDHI_L ( ( char * ) p + s ) ; } </s>


<s> StringRef getPassName ( ) const override { return TLSCLEANUP_PASS_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s>
static
void
avr_asm_function_begin_epilogue
(
FILE
*
file
)
{
app_disable
(
)
;
fprintf
(
file
,
"/* epilogue start */\n"
)
;
}
</s>

Implement ` TARGET_ASM_FUNCTION_BEGIN_EPILOGUE ' .


<s> MVT AArch64TargetLowering :: getScalarShiftAmountTy ( const DataLayout & DL , EVT ) const { return MVT :: i64 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> rtx function_arg ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int named ) { rtx result = 0 ; int size , align ; if ( TARGET_GHS && ! named ) return NULL_RTX ; if ( mode == BLKmode ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; if ( size < 1 ) return 0 ; if ( type ) align = TYPE_ALIGN ( type ) / BITS_PER_UNIT ; else align = size ; cum -> nbytes = ( cum -> nbytes + align - 1 ) & ~ ( align - 1 ) ; if ( cum -> nbytes > 4 * UNITS_PER_WORD ) return 0 ; if ( type == NULL_TREE && cum -> nbytes + size > 4 * UNITS_PER_WORD ) return 0 ; switch ( cum -> nbytes / UNITS_PER_WORD ) { case 0 : result = gen_rtx_REG ( mode , 6 ) ; break ; case 1 : result = gen_rtx_REG ( mode , 7 ) ; break ; case 2 : result = gen_rtx_REG ( mode , 8 ) ; break ; case 3 : result = gen_rtx_REG ( mode , 9 ) ; break ; default : result = 0 ; } return result ; } </s>

Return an RTL expression containing the register for the given mode , or 0 if the argument is to be passed on the stack . INCOMING_P is nonzero if this is an incoming argument to the current function .


"********** MI Converging Scheduling VLIW BB#"

Schedule - This is called back from ScheduleDAGInstrs : :Run ( ) when it 's time to do some work .


<s> unsigned SparcInstrInfo :: getGlobalBaseReg ( MachineFunction * MF ) const { SparcMachineFunctionInfo * SparcFI = MF -> getInfo < SparcMachineFunctionInfo > ( ) ; unsigned GlobalBaseReg = SparcFI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg != 0 ) return GlobalBaseReg ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; const TargetRegisterClass * PtrRC = Subtarget . is64Bit ( ) ? & SP :: I64RegsRegClass : & SP :: IntRegsRegClass ; GlobalBaseReg = RegInfo . createVirtualRegister ( PtrRC ) ; DebugLoc dl ; BuildMI ( FirstMBB , MBBI , dl , get ( SP :: GETPCX ) , GlobalBaseReg ) ; SparcFI -> setGlobalBaseReg ( GlobalBaseReg ) ; return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

Sparc Sparc Sparc Sparc Sparc Sparc 0 SP::I64RegsRegClass SP::IntRegsRegClass SP::GETPCX Sparc


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> static bool nios2_in_small_data_p ( const_tree exp ) { if ( TREE_CODE ( exp ) == STRING_CST ) return false ; if ( TREE_CODE ( exp ) == VAR_DECL ) { if ( DECL_SECTION_NAME ( exp ) ) { const char * section = DECL_SECTION_NAME ( exp ) ; if ( nios2_small_section_name_p ( section ) ) return true ; } else if ( flexible_array_type_p ( TREE_TYPE ( exp ) ) && ( ! TREE_PUBLIC ( exp ) || DECL_EXTERNAL ( exp ) ) ) { return false ; } else { HOST_WIDE_INT size = int_size_in_bytes ( TREE_TYPE ( exp ) ) ; if ( size > 0 && ( unsigned HOST_WIDE_INT ) size <= nios2_section_threshold ) return true ; } } return false ; } </s>

Return true if EXP should be placed in the small data section .


<s>
bool
AArch64TargetLowering
::
isLegalAddImmediate
(
int64_t
Immed
)
const
{
if
(
Immed
==
std
::
numeric_limits
<
int64_t
>
::
min
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Illegal add imm "
<<
Immed
<<
": avoid UB for INT64_MIN\n"
)
;
return
false
;
}
Immed
=
std
::
abs
(
Immed
)
;
bool
IsLegal
=
(
(
Immed
>>
12
)
==
0
||
(
(
Immed
&
0xfff
)
==
0
&&
Immed
>>
24
==
0
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Is "
<<
Immed
<<
" legal add imm: "
<<
(
IsLegal
"yes"
:
"no"
)
<<
"\n"
)
;
return
IsLegal
;
}
</s>

Return true if the specified immediate is legal add immediate , that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register .


<s> bool PPCTargetLowering :: SelectAddressRegRegOnly ( SDValue N , SDValue & Base , SDValue & Index , SelectionDAG & DAG ) const { if ( SelectAddressRegReg ( N , Base , Index , DAG ) ) return true ; int16_t imm = 0 ; if ( N . getOpcode ( ) == ISD :: ADD && ( ! isIntS16Immediate ( N . getOperand ( 1 ) , imm ) || ! N . getOperand ( 1 ) . hasOneUse ( ) || ! N . getOperand ( 0 ) . hasOneUse ( ) ) ) { Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } Base = DAG . getRegister ( Subtarget . isPPC64 ( ) ? PPC :: ZERO8 : PPC :: ZERO , N . getValueType ( ) ) ; Index = N ; return true ; } </s>

SelectAddressRegRegOnly - Given the specified addressed , force it to be represented as an indexed [ r+r ] operation .


<s>
static
X86Operand
*
CreateMem
(
unsigned
SegReg
,
const
MCExpr
*
Disp
,
unsigned
BaseReg
,
unsigned
IndexReg
,
unsigned
Scale
,
SMLoc
StartLoc
,
SMLoc
EndLoc
,
unsigned
Size
=
0
,
bool
NeedSizeDir
=
false
)
{
assert
(
(
SegReg
||
BaseReg
||
IndexReg
)
&&
"Invalid memory operand!"
)
;
assert
(
(
(
Scale
==
1
||
Scale
==
2
||
Scale
==
4
||
Scale
==
8
)
)
&&
"Invalid scale!"
)
;
X86Operand
*
Res
=
new
X86Operand
(
Memory
,
StartLoc
,
EndLoc
)
;
Res
->
Mem
.
SegReg
=
SegReg
;
Res
->
Mem
.
Disp
=
Disp
;
Res
->
Mem
.
BaseReg
=
BaseReg
;
Res
->
Mem
.
IndexReg
=
IndexReg
;
Res
->
Mem
.
Scale
=
Scale
;
Res
->
Mem
.
Size
=
Size
;
Res
->
Mem
.
NeedSizeDir
=
NeedSizeDir
;
return
Res
;
}
</s>


<s> static void s390_set_current_function ( tree fndecl ) { if ( fndecl == s390_previous_fndecl ) { s390_indirect_branch_settings ( fndecl ) ; return ; } tree old_tree ; if ( s390_previous_fndecl == NULL_TREE ) old_tree = target_option_current_node ; else if ( DECL_FUNCTION_SPECIFIC_TARGET ( s390_previous_fndecl ) ) old_tree = DECL_FUNCTION_SPECIFIC_TARGET ( s390_previous_fndecl ) ; else old_tree = target_option_default_node ; if ( fndecl == NULL_TREE ) { if ( old_tree != target_option_current_node ) s390_activate_target_options ( target_option_current_node ) ; return ; } tree new_tree = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( new_tree == NULL_TREE ) new_tree = target_option_default_node ; if ( old_tree != new_tree ) s390_activate_target_options ( new_tree ) ; s390_previous_fndecl = fndecl ; s390_indirect_branch_settings ( fndecl ) ; } </s>

Establish appropriate back-end context for processing the function FNDECL . The argument might be NULL to indicate processing at top level , outside of any function scope .


<s> static machine_mode sparc_preferred_simd_mode ( scalar_mode mode ) { if ( TARGET_VIS ) switch ( mode ) { case E_SImode : return V2SImode ; case E_HImode : return V4HImode ; case E_QImode : return V8QImode ; default : ; } return word_mode ; } </s>

Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook .


<s> static unsigned int rl78_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { int rs = register_sizes [ regno ] ; if ( rs < 1 ) rs = 1 ; return ( ( GET_MODE_SIZE ( mode ) + rs - 1 ) / rs ) ; } </s>


<s> static void loongarch_block_move_loop ( rtx dest , rtx src , HOST_WIDE_INT length , HOST_WIDE_INT bytes_per_iter ) { rtx_code_label * label ; rtx src_reg , dest_reg , final_src , test ; HOST_WIDE_INT leftover ; leftover = length % bytes_per_iter ; length -= leftover ; loongarch_adjust_block_mem ( src , bytes_per_iter , & src_reg , & src ) ; loongarch_adjust_block_mem ( dest , bytes_per_iter , & dest_reg , & dest ) ; final_src = expand_simple_binop ( Pmode , PLUS , src_reg , GEN_INT ( length ) , 0 , 0 , OPTAB_WIDEN ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; loongarch_block_move_straight ( dest , src , bytes_per_iter ) ; loongarch_emit_move ( src_reg , plus_constant ( Pmode , src_reg , bytes_per_iter ) ) ; loongarch_emit_move ( dest_reg , plus_constant ( Pmode , dest_reg , bytes_per_iter ) ) ; test = gen_rtx_NE ( VOIDmode , src_reg , final_src ) ; if ( Pmode == DImode ) emit_jump_insn ( gen_cbranchdi4 ( test , src_reg , final_src , label ) ) ; else emit_jump_insn ( gen_cbranchsi4 ( test , src_reg , final_src , label ) ) ; if ( leftover ) loongarch_block_move_straight ( dest , src , leftover ) ; else emit_insn ( gen_nop ( ) ) ; } </s>

Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER bytes at a time . LENGTH must be at least BYTES_PER_ITER . Assume that the memory regions do not overlap .


<s>
bool
PPCInstrInfo
::
isReallyTriviallyReMaterializable
(
const
MachineInstr
&
MI
,
AliasAnalysis
*
AA
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown rematerializable operation!"
)
;
break
;
case
PPC
::
LI
:
case
PPC
::
LI8
:
case
PPC
::
LIS
:
case
PPC
::
LIS8
:
case
PPC
::
ADDIStocHA
:
case
PPC
::
ADDIStocHA8
:
case
PPC
::
ADDItocL
:
case
PPC
::
LOAD_STACK_GUARD
:
case
PPC
::
XXLXORz
:
case
PPC
::
XXLXORspz
:
case
PPC
::
XXLXORdpz
:
case
PPC
::
XXLEQVOnes
:
case
PPC
::
V_SET0B
:
case
PPC
::
V_SET0H
:
case
PPC
::
V_SET0
:
case
PPC
::
V_SETALLONESB
:
case
PPC
::
V_SETALLONESH
:
case
PPC
::
V_SETALLONES
:
case
PPC
::
CRSET
:
case
PPC
::
CRUNSET
:
return
true
;
}
return
false
;
}
</s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> bool SITargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & CI , unsigned IntrID ) const { switch ( IntrID ) { case Intrinsic :: amdgcn_atomic_inc : case Intrinsic :: amdgcn_atomic_dec : Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: getVT ( CI . getType ( ) ) ; Info . ptrVal = CI . getOperand ( 0 ) ; Info . align = 0 ; Info . vol = false ; Info . readMem = true ; Info . writeMem = true ; return true ; default : return false ; } } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> unsigned getNumFixupKinds ( ) const override { return AVR :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> static rtx mips16e_collect_propagate_value ( rtx x , rtx * reg_values ) { x = avoid_constant_pool_reference ( x ) ; if ( UNARY_P ( x ) ) { rtx x0 = mips16e_collect_propagate_value ( XEXP ( x , 0 ) , reg_values ) ; return simplify_gen_unary ( GET_CODE ( x ) , GET_MODE ( x ) , x0 , GET_MODE ( XEXP ( x , 0 ) ) ) ; } if ( ARITHMETIC_P ( x ) ) { rtx x0 = mips16e_collect_propagate_value ( XEXP ( x , 0 ) , reg_values ) ; rtx x1 = mips16e_collect_propagate_value ( XEXP ( x , 1 ) , reg_values ) ; return simplify_gen_binary ( GET_CODE ( x ) , GET_MODE ( x ) , x0 , x1 ) ; } if ( REG_P ( x ) && reg_values [ REGNO ( x ) ] && ! rtx_unstable_p ( reg_values [ REGNO ( x ) ] ) ) return reg_values [ REGNO ( x ) ] ; return x ; } </s>

Return a simplified form of X using the register values in REG_VALUES . REG_VALUES [ R ] is the last value assigned to hard register R , or null if R has not been modified . This function is rather limited , but is good enough for our purposes .


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { unsigned Idx = Endian == support :: little ? i : 3 - i ; Data [ Offset + Idx ] |= uint8_t ( ( Value >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void clear ( ) { TagStores . clear ( ) ; } </s>


<s> static void aarch64_output_mi_thunk ( FILE * file , tree thunk ATTRIBUTE_UNUSED , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { int this_regno = R0_REGNUM ; rtx this_rtx , temp0 , temp1 , addr , funexp ; rtx_insn * insn ; reload_completed = 1 ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; if ( vcall_offset == 0 ) aarch64_add_constant ( Pmode , this_regno , IP1_REGNUM , delta ) ; else { gcc_assert ( ( vcall_offset & ( POINTER_BYTES - 1 ) ) == 0 ) ; this_rtx = gen_rtx_REG ( Pmode , this_regno ) ; temp0 = gen_rtx_REG ( Pmode , IP0_REGNUM ) ; temp1 = gen_rtx_REG ( Pmode , IP1_REGNUM ) ; addr = this_rtx ; if ( delta != 0 ) { if ( delta >= - 256 && delta < 256 ) addr = gen_rtx_PRE_MODIFY ( Pmode , this_rtx , plus_constant ( Pmode , this_rtx , delta ) ) ; else aarch64_add_constant ( Pmode , this_regno , IP1_REGNUM , delta ) ; } if ( Pmode == ptr_mode ) aarch64_emit_move ( temp0 , gen_rtx_MEM ( ptr_mode , addr ) ) ; else aarch64_emit_move ( temp0 , gen_rtx_ZERO_EXTEND ( Pmode , gen_rtx_MEM ( ptr_mode , addr ) ) ) ; if ( vcall_offset >= - 256 && vcall_offset < 4096 * POINTER_BYTES ) addr = plus_constant ( Pmode , temp0 , vcall_offset ) ; else { aarch64_internal_mov_immediate ( temp1 , GEN_INT ( vcall_offset ) , true , Pmode ) ; addr = gen_rtx_PLUS ( Pmode , temp0 , temp1 ) ; } if ( Pmode == ptr_mode ) aarch64_emit_move ( temp1 , gen_rtx_MEM ( ptr_mode , addr ) ) ; else aarch64_emit_move ( temp1 , gen_rtx_SIGN_EXTEND ( Pmode , gen_rtx_MEM ( ptr_mode , addr ) ) ) ; emit_insn ( gen_add2_insn ( this_rtx , temp1 ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = 1 ; } funexp = XEXP ( DECL_RTL ( function ) , 0 ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx , NULL_RTX ) ) ; SIBLING_CALL_P ( insn ) = 1 ; insn = get_insns ( ) ; shorten_branches ( insn ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; reload_completed = 0 ; } </s>

Output code to add DELTA to the first argument , and then jump to FUNCTION . Used for C++ multiple inheritance .


Prepare the OPERANDS array to emit a mempair instruction using the provided information . No checks are performed , the resulting array should be validated using th_mempair_operands_p ( ) .


<s>
const
char
*
getPassName
(
)
const
{
return
"PTX Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void i960_initialize ( ) { if ( TARGET_IC_COMPAT2_0 ) { i960_maxbitalignment = 8 ; i960_last_maxbitalignment = 128 ; } else { i960_maxbitalignment = 128 ; i960_last_maxbitalignment = 8 ; } } </s>

Initialize variables before compiling any files .


<s>
const
char
*
avr_out_round
(
rtx_insn
*
insn
ATTRIBUTE_UNUSED
,
rtx
*
xop
,
int
*
plen
)
{
scalar_mode
mode
=
as_a
<
scalar_mode
>
(
GET_MODE
(
xop
[
0
]
)
)
;
scalar_int_mode
imode
=
int_mode_for_mode
(
mode
)
.
require
(
)
;
int
fbit
=
(
int
)
GET_MODE_FBIT
(
mode
)
;
double_int
i_add
=
double_int_zero
.
set_bit
(
fbit
1
INTVAL
(
xop
[
2
]
)
)
;
wide_int
wi_add
=
wi
::
set_bit_in_zero
(
fbit
1
INTVAL
(
xop
[
2
]
)
,
GET_MODE_PRECISION
(
imode
)
)
;
int
len_add
=
0
,
*
plen_add
=
plen
&
len_add
:
;
int
len_and
=
0
,
*
plen_and
=
plen
&
len_and
:
;
rtx
xadd
=
const_fixed_from_double_int
(
i_add
,
mode
)
;
rtx
xpattern
,
xsrc
,
op
[
4
]
;
xsrc
=
SIGNED_FIXED_POINT_MODE_P
(
mode
)
gen_rtx_SS_PLUS
(
mode
,
xop
[
1
]
,
xadd
)
:
gen_rtx_US_PLUS
(
mode
,
xop
[
1
]
,
xadd
)
;
xpattern
=
gen_rtx_SET
(
xop
[
0
]
,
xsrc
)
;
op
[
0
]
=
xop
[
0
]
;
op
[
1
]
=
xop
[
1
]
;
op
[
2
]
=
xadd
;
avr_out_plus
(
xpattern
,
op
,
plen_add
,
,
false
)
;
avr_asm_len
(
"rjmp 1f"
CR_TAB
"0:"
,
,
plen_add
,
1
)
;
rtx
xreg
=
simplify_gen_subreg
(
imode
,
xop
[
0
]
,
mode
,
0
)
;
rtx
xmask
=
immed_wide_int_const
(
wi_add
wi_add
,
imode
)
;
xpattern
=
gen_rtx_SET
(
xreg
,
gen_rtx_AND
(
imode
,
xreg
,
xmask
)
)
;
op
[
0
]
=
xreg
;
op
[
1
]
=
xreg
;
op
[
2
]
=
xmask
;
op
[
3
]
=
gen_rtx_SCRATCH
(
QImode
)
;
avr_out_bitop
(
xpattern
,
op
,
plen_and
)
;
avr_asm_len
(
"1:"
,
,
plen
,
0
)
;
if
(
plen
)
*
plen
=
len_add
+
len_and
;
return
""
;
}
</s>

Output fixed-point rounding . XOP [ 0 ] = XOP [ 1 ] is the operand to round . XOP [ 2 ] is the rounding point , a CONST_INT . The function prints the instruction sequence if PLEN = NULL and computes the length in words of the sequence if PLEN ! = NULL . Most of this function deals with preparing operands for calls to ` avr_out_plus ' and ` avr_out_bitop ' .


<s>
const
char
*
mmix_data_section_asm_op
(
void
)
{
return
"\t.data ! mmixal:= 8H LOC 9B"
;
}
</s>


<s>
SDValue
PatmosTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_Patmos
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
auto
Opc
=
PatmosISD
::
RET_FLAG
;
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
Opc
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> SDValue HexagonTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SmallVectorImpl < SDValue > & OutVals , SDValue Callee ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_Hexagon ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> bool X86InstrInfo :: isCoalescableExtInstr ( const MachineInstr & MI , unsigned & SrcReg , unsigned & DstReg , unsigned & SubIdx ) const { switch ( MI . getOpcode ( ) ) { default : break ; case X86 :: MOVSX16rr8 : case X86 :: MOVZX16rr8 : case X86 :: MOVSX32rr8 : case X86 :: MOVZX32rr8 : case X86 :: MOVSX64rr8 : case X86 :: MOVZX64rr8 : if ( ! TM . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ) return false ; case X86 :: MOVSX32rr16 : case X86 :: MOVZX32rr16 : case X86 :: MOVSX64rr16 : case X86 :: MOVZX64rr16 : case X86 :: MOVSX64rr32 : case X86 :: MOVZX64rr32 : { if ( MI . getOperand ( 0 ) . getSubReg ( ) || MI . getOperand ( 1 ) . getSubReg ( ) ) return false ; SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; DstReg = MI . getOperand ( 0 ) . getReg ( ) ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( 0 ) ; break ; case X86 :: MOVSX16rr8 : case X86 :: MOVZX16rr8 : case X86 :: MOVSX32rr8 : case X86 :: MOVZX32rr8 : case X86 :: MOVSX64rr8 : case X86 :: MOVZX64rr8 : SubIdx = 1 ; break ; case X86 :: MOVSX32rr16 : case X86 :: MOVZX32rr16 : case X86 :: MOVSX64rr16 : case X86 :: MOVZX64rr16 : SubIdx = 3 ; break ; case X86 :: MOVSX64rr32 : case X86 :: MOVZX64rr32 : SubIdx = 4 ; break ; } return true ; } } return false ; } </s>

isCoalescableExtInstr - Return true if the instruction is a `` coalescable '' extension instruction .


<s> static bool aarch64_fixed_condition_code_regs ( unsigned int * p1 , unsigned int * p2 ) { * p1 = CC_REGNUM ; * p2 = INVALID_REGNUM ; return true ; } </s>

Return the fixed registers used for condition codes .


<s> void aarch64_gen_unlikely_cbranch ( enum rtx_code code , machine_mode cc_mode , rtx label_ref ) { rtx x ; x = gen_rtx_fmt_ee ( code , VOIDmode , gen_rtx_REG ( cc_mode , CC_REGNUM ) , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( VOIDmode , label_ref ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } </s>

Generate RTL for a conditional branch with rtx comparison CODE in mode CC_MODE . The destination of the unlikely conditional branch is LABEL_REF .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> bool UPTInstrInfo :: verifyInstruction ( const MachineInstr & MI , StringRef & ErrInfo ) const { return TargetInstrInfo :: verifyInstruction ( MI , ErrInfo ) ; } </s>

Perform target-specific instruction verification .


<s> pure_scalable_type_info :: analysis_result pure_scalable_type_info :: analyze ( const_tree type ) { gcc_assert ( pieces . is_empty ( ) ) ; if ( type == error_mark_node ) return NO_ABI_IDENTITY ; if ( TYPE_SIZE ( type ) && integer_zerop ( TYPE_SIZE ( type ) ) ) return NO_ABI_IDENTITY ; piece p = { } ; if ( aarch64_sve :: builtin_type_p ( type , & p . num_zr , & p . num_pr ) ) { machine_mode mode = TYPE_MODE_RAW ( type ) ; gcc_assert ( VECTOR_MODE_P ( mode ) && ( ! TARGET_SVE || aarch64_sve_mode_p ( mode ) ) ) ; p . mode = p . orig_mode = mode ; add_piece ( p ) ; return IS_PST ; } if ( TREE_CODE ( type ) == ARRAY_TYPE ) return analyze_array ( type ) ; if ( TREE_CODE ( type ) == RECORD_TYPE ) return analyze_record ( type ) ; return ISNT_PST ; } </s>

Count how many times each regno is referenced as base address for a memory access .


<s>
void
HexagonMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
MCInst
&
HMB
=
const_cast
<
MCInst
&
>
(
MI
)
;
assert
(
HexagonMCInstrInfo
::
isBundle
(
HMB
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Encoding bundle\n"
;
)
;
State
.
Addend
=
0
;
State
.
Extended
=
false
;
State
.
Bundle
=
&
MI
;
State
.
Index
=
0
;
size_t
Last
=
HexagonMCInstrInfo
::
bundleSize
(
HMB
)
1
;
uint64_t
Features
=
computeAvailableFeatures
(
STI
.
getFeatureBits
(
)
)
;
for
(
auto
&
I
:
HexagonMCInstrInfo
::
bundleInstructions
(
HMB
)
)
{
MCInst
&
HMI
=
const_cast
<
MCInst
&
>
(
*
I
.
getInst
(
)
)
;
verifyInstructionPredicates
(
HMI
,
Features
)
;
EncodeSingleInstruction
(
HMI
,
OS
,
Fixups
,
STI
,
parseBits
(
Last
,
HMB
,
HMI
)
)
;
State
.
Extended
=
HexagonMCInstrInfo
::
isImmext
(
HMI
)
;
State
.
Addend
+=
HEXAGON_INSTR_SIZE
;
++
State
.
Index
;
}
}
</s>

Encode the given Inst to bytes and append to CB .

Hexagon
Hexagon
Hexagon
"Encoding bundle\n"
0
0
Hexagon
1
Hexagon
Hexagon


<s> static int rs6000_hard_regno_mode_ok_uncached ( int regno , machine_mode mode ) { int last_regno = regno + rs6000_hard_regno_nregs [ mode ] [ regno ] - 1 ; if ( COMPLEX_MODE_P ( mode ) ) mode = GET_MODE_INNER ( mode ) ; if ( mode == OOmode ) return ( TARGET_MMA && VSX_REGNO_P ( regno ) && ( regno & 1 ) == 0 ) ; if ( mode == XOmode ) return ( TARGET_MMA && FP_REGNO_P ( regno ) && ( regno & 3 ) == 0 ) ; if ( mode == PTImode ) return ( IN_RANGE ( regno , FIRST_GPR_REGNO , LAST_GPR_REGNO ) && IN_RANGE ( last_regno , FIRST_GPR_REGNO , LAST_GPR_REGNO ) && ( ( regno & 1 ) == 0 ) ) ; if ( TARGET_VSX && VSX_REGNO_P ( regno ) && ( VECTOR_MEM_VSX_P ( mode ) || VECTOR_ALIGNMENT_P ( mode ) || reg_addr [ mode ] . scalar_in_vmx_p || mode == TImode || ( TARGET_VADDUQM && mode == V1TImode ) ) ) { if ( FP_REGNO_P ( regno ) ) return FP_REGNO_P ( last_regno ) ; if ( ALTIVEC_REGNO_P ( regno ) ) { if ( GET_MODE_SIZE ( mode ) < 16 && ! reg_addr [ mode ] . scalar_in_vmx_p ) return 0 ; return ALTIVEC_REGNO_P ( last_regno ) ; } } if ( INT_REGNO_P ( regno ) ) return INT_REGNO_P ( last_regno ) ; if ( FP_REGNO_P ( regno ) ) { if ( VECTOR_ALIGNMENT_P ( mode ) ) return false ; if ( SCALAR_FLOAT_MODE_P ( mode ) && ( mode != TDmode || ( regno % 2 ) == 0 ) && FP_REGNO_P ( last_regno ) ) return 1 ; if ( GET_MODE_CLASS ( mode ) == MODE_INT ) { if ( GET_MODE_SIZE ( mode ) == UNITS_PER_FP_WORD ) return 1 ; if ( TARGET_P8_VECTOR && ( mode == SImode ) ) return 1 ; if ( TARGET_P9_VECTOR && ( mode == QImode || mode == HImode ) ) return 1 ; } return 0 ; } if ( CR_REGNO_P ( regno ) ) return GET_MODE_CLASS ( mode ) == MODE_CC ; if ( CA_REGNO_P ( regno ) ) return mode == Pmode || mode == SImode ; if ( ALTIVEC_REGNO_P ( regno ) ) return ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) || mode == V1TImode ) ; return GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD ; } </s>

Value is 1 if hard register REGNO can hold a value of machine-mode MODE .


"PPC DAG preprocessing replacing:\nOld:    "

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> MachineInstr * MBlazeInstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , int FI ) const { if ( Ops . size ( ) != 1 ) return NULL ; MachineInstr * NewMI = NULL ; switch ( MI -> getOpcode ( ) ) { case MBlaze :: OR : case MBlaze :: ADD : if ( ( MI -> getOperand ( 0 ) . isReg ( ) ) && ( MI -> getOperand ( 2 ) . isReg ( ) ) && ( MI -> getOperand ( 2 ) . getReg ( ) == MBlaze :: R0 ) && ( MI -> getOperand ( 1 ) . isReg ( ) ) ) { if ( Ops [ 0 ] == 0 ) { unsigned SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; bool isKill = MI -> getOperand ( 1 ) . isKill ( ) ; bool isUndef = MI -> getOperand ( 1 ) . isUndef ( ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( MBlaze :: SW ) ) . addReg ( SrcReg , getKillRegState ( isKill ) | getUndefRegState ( isUndef ) ) . addImm ( 0 ) . addFrameIndex ( FI ) ; } else { unsigned DstReg = MI -> getOperand ( 0 ) . getReg ( ) ; bool isDead = MI -> getOperand ( 0 ) . isDead ( ) ; bool isUndef = MI -> getOperand ( 0 ) . isUndef ( ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( MBlaze :: LW ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( isDead ) | getUndefRegState ( isUndef ) ) . addImm ( 0 ) . addFrameIndex ( FI ) ; } } break ; } return NewMI ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s>
void
XCoreRegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected"
)
;
MachineInstr
&
MI
=
*
II
;
MachineOperand
&
FrameOp
=
MI
.
getOperand
(
FIOperandNum
)
;
int
FrameIndex
=
FrameOp
.
getIndex
(
)
;
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
const
XCoreInstrInfo
&
TII
=
*
static_cast
<
const
XCoreInstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
const
TargetFrameLowering
*
TFI
=
MF
.
getSubtarget
(
)
.
getFrameLowering
(
)
;
int
Offset
=
MF
.
getFrameInfo
(
)
->
getObjectOffset
(
FrameIndex
)
;
int
StackSize
=
MF
.
getFrameInfo
(
)
->
getStackSize
(
)
;
DEBUG
(
errs
(
)
<<
"\nFunction         : "
<<
MF
.
getName
(
)
<<
"\n"
)
;
DEBUG
(
errs
(
)
<<
"<--------->\n"
)
;
DEBUG
(
MI
.
print
(
errs
(
)
)
)
;
DEBUG
(
errs
(
)
<<
"FrameIndex         : "
<<
FrameIndex
<<
"\n"
)
;
DEBUG
(
errs
(
)
<<
"FrameOffset        : "
<<
Offset
<<
"\n"
)
;
DEBUG
(
errs
(
)
<<
"StackSize          : "
<<
StackSize
<<
"\n"
)
;
Offset
+=
StackSize
;
unsigned
FrameReg
=
getFrameRegister
(
MF
)
;
if
(
MI
.
isDebugValue
(
)
)
{
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
)
;
return
;
}
Offset
+=
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
0
)
;
assert
(
Offset
%
4
==
0
&&
"Misaligned stack offset"
)
;
DEBUG
(
errs
(
)
<<
"Offset             : "
<<
Offset
<<
"\n"
<<
"<--------->\n"
)
;
Offset
/=
4
;
unsigned
Reg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
assert
(
XCore
::
GRRegsRegClass
.
contains
(
Reg
)
&&
"Unexpected register operand"
)
;
if
(
TFI
->
hasFP
(
MF
)
)
{
if
(
isImmUs
(
Offset
)
)
InsertFPImmInst
(
II
,
TII
,
Reg
,
FrameReg
,
Offset
)
;
else
InsertFPConstInst
(
II
,
TII
,
Reg
,
FrameReg
,
Offset
,
RS
)
;
}
else
{
if
(
isImmU16
(
Offset
)
)
InsertSPImmInst
(
II
,
TII
,
Reg
,
Offset
)
;
else
InsertSPConstInst
(
II
,
TII
,
Reg
,
Offset
,
RS
)
;
}
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
MBB
.
erase
(
II
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .

XCore
XCore
0
"Unexpected"
XCore
XCore
"\nFunction         : "
"\n"
"<--------->\n"
"FrameIndex         : "
"\n"
"FrameOffset        : "
"\n"
"StackSize          : "
"\n"
1
1
1
0
4
0
"Misaligned stack offset"
"Offset             : "
"\n"
"<--------->\n"
4
0
XCore::GRRegsRegClass
"Unexpected register operand"


<s> bool aarch64_sve_float_arith_immediate_p ( rtx x , bool negate_p ) { rtx elt ; REAL_VALUE_TYPE r ; if ( ! const_vec_duplicate_p ( x , & elt ) || GET_CODE ( elt ) != CONST_DOUBLE ) return false ; r = * CONST_DOUBLE_REAL_VALUE ( elt ) ; if ( negate_p ) r = real_value_negate ( & r ) ; if ( real_equal ( & r , & dconst1 ) ) return true ; if ( real_equal ( & r , & dconsthalf ) ) return true ; return false ; } </s>

Return true if X is a valid immediate operand for an SVE FADD or FSUB instruction . Negate X first if NEGATE_P is true .


<s> bool runOnModule ( Module & M ) override { DEBUG ( dbgs ( ) << getPassName ( ) << '\n' ) ; bool Changed = false ; for ( auto & MF : M ) { Changed |= runOnFunction ( MF ) ; } return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


"Trying RISCV32Only_16 table (16-bit Instruction):\n"

"Trying RISCV_C table (16-bit Instruction):\n"

Returns the disassembly of a single instruction .


<s> int m68k_hard_regno_rename_ok ( unsigned int old_reg ATTRIBUTE_UNUSED , unsigned int new_reg ) { if ( ( m68k_get_function_kind ( current_function_decl ) == m68k_fk_interrupt_handler ) && ! df_regs_ever_live_p ( new_reg ) ) return 0 ; return 1 ; } </s>

Return nonzero if register old_reg can be renamed to register new_reg .


<s> static NodeType * getEntryNode ( const PatmosSinglePathInfo * PSPI ) { return PSPI -> getRootScope ( ) ; } </s>

Return the token chain corresponding to the entry of the function .


<s> static bool classof ( const AMDGPULibFuncImpl * F ) { return ! F -> isMangled ( ) ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> static bool mep_use_post_modify_for_set_p ( rtx set , rtx gpr , rtx offset ) { rtx * reg , * mem ; unsigned int reg_bytes , mem_bytes ; machine_mode reg_mode , mem_mode ; if ( GET_CODE ( set ) != SET ) return false ; if ( GET_CODE ( SET_DEST ( set ) ) == MEM ) { mem = & SET_DEST ( set ) ; reg = & SET_SRC ( set ) ; } else { reg = & SET_DEST ( set ) ; mem = & SET_SRC ( set ) ; if ( GET_CODE ( * mem ) == SIGN_EXTEND ) mem = & XEXP ( * mem , 0 ) ; } if ( GET_CODE ( * reg ) != REG || ! LOADABLE_CR_REGNO_P ( REGNO ( * reg ) ) ) return false ; if ( GET_CODE ( * mem ) != MEM || ! rtx_equal_p ( XEXP ( * mem , 0 ) , gpr ) ) return false ; mem_bytes = GET_MODE_SIZE ( GET_MODE ( * mem ) ) ; reg_bytes = GET_MODE_SIZE ( GET_MODE ( * reg ) ) ; if ( INTVAL ( offset ) & ( mem_bytes - 1 ) ) return false ; mem_mode = mode_for_size ( mem_bytes * BITS_PER_UNIT , MODE_INT , 0 ) ; * mem = change_address ( * mem , mem_mode , NULL ) ; * reg = shallow_copy_rtx ( * reg ) ; if ( reg == & SET_DEST ( set ) && reg_bytes < UNITS_PER_WORD ) { PUT_MODE ( * reg , SImode ) ; * mem = gen_rtx_SIGN_EXTEND ( SImode , * mem ) ; } else { reg_mode = mode_for_size ( reg_bytes * BITS_PER_UNIT , MODE_INT , 0 ) ; PUT_MODE ( * reg , reg_mode ) ; } return true ; } </s>

Return true if SET can be turned into a post-modify load or store that adds OFFSET to GPR . In other words , return true if SET can be changed into : ( parallel [ SET ( set GPR ( plus : SI GPR OFFSET ) ) ] ) . It 's OK to change SET to an equivalent operation in order to make it match .


<s>
StringRef
getPassName
(
)
const
override
{
return
"J2 Delay Slot Filler"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> unsigned SITargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( CC == CallingConv :: AMDGPU_KERNEL ) return TargetLowering :: getNumRegistersForCallingConv ( Context , CC , VT ) ; if ( VT . isVector ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; EVT ScalarVT = VT . getScalarType ( ) ; unsigned Size = ScalarVT . getSizeInBits ( ) ; if ( Size == 32 ) return NumElts ; if ( Size > 32 ) return NumElts * ( ( Size + 31 ) / 32 ) ; if ( Size == 16 && Subtarget -> has16BitInsts ( ) ) return ( NumElts + 1 ) / 2 ; } else if ( VT . getSizeInBits ( ) > 32 ) return ( VT . getSizeInBits ( ) + 31 ) / 32 ; return TargetLowering :: getNumRegistersForCallingConv ( Context , CC , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s> bool KudeyarFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; KudeyarMachineFunctionInfo * MFI = MF . getInfo < KudeyarMachineFunctionInfo > ( ) ; MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 4 ) ; if ( CSI . size ( ) > 1 ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( Kudeyar :: PUSHA ) ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; bool isKill = true ; if ( isKill ) MBB . addLiveIn ( Reg ) ; MIB . addReg ( Reg , getKillRegState ( isKill ) ) ; } MIB . setMIFlags ( MachineInstr :: FrameSetup ) ; } else { unsigned Reg = CSI [ 0 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( Kudeyar :: PUSH_R ) ) . addReg ( Reg , RegState :: Kill ) ; } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( Kudeyar :: PUSH_R ) ) . addReg ( Reg , RegState :: Kill ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> bool AArch64TargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( AM . BaseGV ) return false ; if ( AM . HasBaseReg && AM . BaseOffs && AM . Scale ) return false ; uint64_t NumBytes = 0 ; if ( Ty -> isSized ( ) ) { uint64_t NumBits = getDataLayout ( ) -> getTypeSizeInBits ( Ty ) ; NumBytes = NumBits / 8 ; if ( ! isPowerOf2_64 ( NumBits ) ) NumBytes = 0 ; } if ( ! AM . Scale ) { int64_t Offset = AM . BaseOffs ; if ( Offset >= - ( 1LL << 9 ) && Offset <= ( 1LL << 9 ) - 1 ) return true ; unsigned shift = Log2_64 ( NumBytes ) ; if ( NumBytes && Offset > 0 && ( Offset / NumBytes ) <= ( 1LL << 12 ) - 1 && ( Offset >> shift ) << shift == Offset ) return true ; return false ; } if ( ! AM . Scale || AM . Scale == 1 || ( AM . Scale > 0 && ( uint64_t ) AM . Scale == NumBytes ) ) return true ; return false ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> int xstormy16_splittable_below100_operand ( rtx x , enum machine_mode mode ) { if ( GET_CODE ( x ) == MEM && MEM_VOLATILE_P ( x ) ) return 0 ; return xstormy16_below100_operand ( x , mode ) ; } </s>

Likewise , but only for non-volatile MEMs , for patterns where the MEM will get split into smaller sized accesses .


"Custom lowering not defined for operation"

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool AMDGPUTargetLowering :: isFAbsFree ( EVT VT ) const { assert ( VT . isFloatingPoint ( ) ) ; return VT == MVT :: f32 ; } </s>

Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation .


"64-bit code requested on a subtarget that doesn't support it!"

This constructor initializes the data members to match that of the specified triple .


<s> bool FISCRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> bool SITargetLowering :: isFMAFasterThanFMulAndFAdd ( const MachineFunction & MF , LLT Ty ) const { switch ( Ty . getScalarSizeInBits ( ) ) { case 16 : return isFMAFasterThanFMulAndFAdd ( MF , MVT :: f16 ) ; case 32 : return isFMAFasterThanFMulAndFAdd ( MF , MVT :: f32 ) ; case 64 : return isFMAFasterThanFMulAndFAdd ( MF , MVT :: f64 ) ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> static std :: unique_ptr < P2Operand > CreateMem ( unsigned Base , const MCExpr * Off , SMLoc S , SMLoc E ) { auto Op = std :: make_unique < P2Operand > ( k_Memory ) ; Op -> Mem . Base = Base ; Op -> Mem . Off = Off ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>


"Alloca should always return a pointer."

Emit an alloca address in a register using target-specific logic .


<s> EVT ARMTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( ( ! IsMemset || ZeroMemset ) && Subtarget -> hasNEON ( ) && ! F -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoImplicitFloat ) ) { bool Fast ; if ( Size >= 16 && ( memOpAlign ( SrcAlign , DstAlign , 16 ) || ( allowsMisalignedMemoryAccesses ( MVT :: v2f64 , 0 , 1 , & Fast ) && Fast ) ) ) { return MVT :: v2f64 ; } else if ( Size >= 8 && ( memOpAlign ( SrcAlign , DstAlign , 8 ) || ( allowsMisalignedMemoryAccesses ( MVT :: f64 , 0 , 1 , & Fast ) && Fast ) ) ) { return MVT :: f64 ; } } if ( Size >= 4 ) return MVT :: i32 ; else if ( Size >= 2 ) return MVT :: i16 ; return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> bool PPCInstrInfo :: findCommutedOpIndices ( const MachineInstr & MI , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { int AltOpc = PPC :: getAltVSXFMAOpcode ( MI . getOpcode ( ) ) ; if ( AltOpc == - 1 ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , 2 , 3 ) ; } </s>

Returns true iff the routine could find two commutable operands in the given machine instruction .


<s> virtual const MCSection * getExplicitSectionGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler * Mang , const TargetMachine & TM ) const { return DataSection ; } </s>

Targets should implement this method to assign a section to globals with an explicit section specfied .


<s> static void riscv_expand_op ( enum rtx_code code , machine_mode mode , rtx op0 , rtx op1 , rtx op2 ) { if ( can_create_pseudo_p ( ) ) { rtx result ; if ( GET_RTX_CLASS ( code ) == RTX_UNARY ) result = expand_simple_unop ( mode , code , op1 , NULL_RTX , false ) ; else result = expand_simple_binop ( mode , code , op1 , op2 , NULL_RTX , false , OPTAB_DIRECT ) ; riscv_emit_move ( op0 , result ) ; } else { rtx pat ; if ( GET_RTX_CLASS ( code ) == RTX_UNARY ) pat = gen_rtx_fmt_e ( code , mode , op1 ) ; else pat = gen_rtx_fmt_ee ( code , mode , op1 , op2 ) ; emit_insn ( gen_rtx_SET ( op0 , pat ) ) ; } } </s>

Helper function to operation for rtx_code CODE .


<s> static rtx aarch64_simd_make_constant ( rtx vals ) { machine_mode mode = GET_MODE ( vals ) ; rtx const_dup ; rtx const_vec = NULL_RTX ; int n_elts = GET_MODE_NUNITS ( mode ) ; int n_const = 0 ; int i ; if ( GET_CODE ( vals ) == CONST_VECTOR ) const_vec = vals ; else if ( GET_CODE ( vals ) == PARALLEL ) { for ( i = 0 ; i < n_elts ; ++ i ) { rtx x = XVECEXP ( vals , 0 , i ) ; if ( CONST_INT_P ( x ) || CONST_DOUBLE_P ( x ) ) n_const ++ ; } if ( n_const == n_elts ) const_vec = gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , 0 ) ) ; } else gcc_unreachable ( ) ; if ( const_vec != NULL_RTX && aarch64_simd_valid_immediate ( const_vec , mode , false , NULL ) ) return const_vec ; else if ( ( const_dup = aarch64_simd_dup_constant ( vals ) ) != NULL_RTX ) return const_dup ; else if ( const_vec != NULL_RTX ) return const_vec ; else return NULL_RTX ; } </s>

Generate code to load VALS , which is a PARALLEL containing only constants ( for vec_init ) or CONST_VECTOR , efficiently into a register . Returns an RTX to copy into the register , or NULL_RTX for a PARALLEL that can not be converted into a CONST_VECTOR .


<s> void SIFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const SIMachineFunctionInfo * FuncInfo = MF . getInfo < SIMachineFunctionInfo > ( ) ; if ( FuncInfo -> isEntryFunction ( ) ) return ; unsigned StackPtrReg = FuncInfo -> getStackPtrOffsetReg ( ) ; if ( StackPtrReg == AMDGPU :: NoRegister ) return ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; uint32_t NumBytes = MFI . getStackSize ( ) ; const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; const SIInstrInfo * TII = ST . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; DebugLoc DL ; if ( NumBytes != 0 && hasSP ( MF ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( AMDGPU :: S_SUB_U32 ) , StackPtrReg ) . addReg ( StackPtrReg ) . addImm ( NumBytes * ST . getWavefrontSize ( ) ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } } </s>

AMDGPU SI SI SI AMDGPU::NoRegister SI SI SI 0 AMDGPU::S_SUB_U32


<s> SDValue LanaiSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & , const SDLoc & , SDValue , SDValue , SDValue , SDValue Size , Align , bool , bool , MachinePointerInfo , MachinePointerInfo ) const { ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; if ( ! ConstantSize ) return SDValue ( ) ; return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .


<s> bool M680x0InstrInfo :: getStackSlotRange ( const TargetRegisterClass * RC , unsigned SubIdx , unsigned & Size , unsigned & Offset , const MachineFunction & MF ) const { Size = 4 ; Offset = 0 ; return true ; } </s>

Compute the size in bytes and offset within a stack slot of a spilled register or subregister .


<s> SDNode * SparcDAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = TM . getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , getTargetLowering ( ) -> getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> const TargetRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> EVT ARM64TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { bool Fast ; const Function * F = MF . getFunction ( ) ; if ( Subtarget -> hasFPARMv8 ( ) && ! IsMemset && Size >= 16 && ! F -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoImplicitFloat ) && ( memOpAlign ( SrcAlign , DstAlign , 16 ) || ( allowsUnalignedMemoryAccesses ( MVT :: f128 , 0 , & Fast ) && Fast ) ) ) return MVT :: f128 ; return Size >= 8 ? MVT :: i64 : MVT :: i32 ; } </s>


<s>
void
HexagonInstPrinter
::
printSymbol
(
const
MCInst
*
MI
,
unsigned
OpNo
,
raw_ostream
&
O
,
bool
hi
)
const
{
assert
(
MI
->
getOperand
(
OpNo
)
.
isImm
(
)
&&
"Unknown symbol operand"
)
;
O
<<
'#'
<<
(
hi
"HI"
:
"LO"
)
<<
"(#"
;
printOperand
(
MI
,
OpNo
,
O
)
;
O
<<
')'
;
}
</s>

Hexagon
Hexagon
"Unknown symbol operand"
"HI"
"LO"
"(#"


<s> bool isLegalMaskedScatter ( Type * DataType ) { return ST -> hasSVE ( ) ; } </s>

Return true if the target supports masked scatter .


<s> bool AArch64TargetLowering :: isShuffleMaskLegal ( ArrayRef < int > M , EVT VT ) const { if ( VT . getVectorNumElements ( ) == 4 && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ 4 ] ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { if ( M [ i ] < 0 ) PFIndexes [ i ] = 8 ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ 0 ] * 9 * 9 * 9 + PFIndexes [ 1 ] * 9 * 9 + PFIndexes [ 2 ] * 9 + PFIndexes [ 3 ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> 30 ) ; if ( Cost <= 4 ) return true ; } bool DummyBool ; int DummyInt ; unsigned DummyUnsigned ; return ( ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isREVMask ( M , VT , 64 ) || isREVMask ( M , VT , 32 ) || isREVMask ( M , VT , 16 ) || isEXTMask ( M , VT , DummyBool , DummyUnsigned ) || isTRNMask ( M , VT , DummyUnsigned ) || isUZPMask ( M , VT , DummyUnsigned ) || isZIPMask ( M , VT , DummyUnsigned ) || isTRN_v_undef_Mask ( M , VT , DummyUnsigned ) || isUZP_v_undef_Mask ( M , VT , DummyUnsigned ) || isZIP_v_undef_Mask ( M , VT , DummyUnsigned ) || isINSMask ( M , VT . getVectorNumElements ( ) , DummyBool , DummyInt ) || isConcatMask ( M , VT , VT . getSizeInBits ( ) == 128 ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> virtual const Tile64InstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s>
void
HexagonInstPrinter
::
printInst
(
const
HexagonMCInst
*
MI
,
raw_ostream
&
O
,
StringRef
Annot
)
{
const
char
startPacket
=
'{'
,
endPacket
=
'}'
;
if
(
MI
->
getOpcode
(
)
==
Hexagon
::
ENDLOOP0
)
{
assert
(
MI
->
isPacketEnd
(
)
&&
"Loop-end must also end the packet"
)
;
if
(
MI
->
isPacketBegin
(
)
)
{
HexagonMCInst
Nop
;
StringRef
NoAnnot
;
Nop
.
setOpcode
(
Hexagon
::
A2_nop
)
;
Nop
.
setPacketBegin
(
MI
->
isPacketBegin
(
)
)
;
printInst
(
&
Nop
,
O
,
NoAnnot
)
;
}
if
(
MI
->
isPacketEnd
(
)
)
O
<<
PacketPadding
<<
endPacket
;
printInstruction
(
MI
,
O
)
;
}
else
{
if
(
MI
->
isPacketBegin
(
)
)
O
<<
PacketPadding
<<
startPacket
<<
'\n'
;
printInstruction
(
MI
,
O
)
;
if
(
MI
->
isPacketEnd
(
)
)
O
<<
'\n'
<<
PacketPadding
<<
endPacket
;
}
printAnnotation
(
O
,
Annot
)
;
}
</s>

Print the specified MCInst to the specified raw_ostream .

Hexagon
Hexagon
Hexagon
Hexagon::ENDLOOP0
"Loop-end must also end the packet"
Hexagon
Hexagon::A2_nop


<s>
static
void
output_asm_btfext_core_reloc
(
bpf_core_reloc_ref
bpfcr
)
{
bpfcr
->
bpfcr_astr_off
+=
ctfc_get_strtab_len
(
ctf_get_tu_ctfc
(
)
,
CTF_STRTAB
)
;
dw2_assemble_integer
(
4
,
gen_rtx_LABEL_REF
(
Pmode
,
bpfcr
->
bpfcr_insn_label
)
)
;
fprintf
(
asm_out_file
,
"\t%s bpfcr_insn\n"
,
ASM_COMMENT_START
)
;
dw2_asm_output_data
(
4
,
bpfcr
->
bpfcr_type
,
"bpfcr_type"
)
;
dw2_asm_output_data
(
4
,
bpfcr
->
bpfcr_astr_off
,
"bpfcr_astr_off"
)
;
dw2_asm_output_data
(
4
,
bpfcr
->
bpfcr_kind
,
"bpfcr_kind"
)
;
}
</s>

Output a single CO-RE relocation record .


<s>
Optional
<
RegImmPair
>
AArch64InstrInfo
::
isAddImmediate
(
const
MachineInstr
&
MI
,
Register
Reg
)
const
{
int
Sign
=
1
;
int64_t
Offset
=
0
;
if
(
Reg
!=
MI
.
getOperand
(
0
)
.
getReg
(
)
)
return
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
return
;
case
AArch64
::
SUBWri
:
case
AArch64
::
SUBXri
:
case
AArch64
::
SUBSWri
:
case
AArch64
::
SUBSXri
:
Sign
*=
1
;
LLVM_FALLTHROUGH
;
case
AArch64
::
ADDSWri
:
case
AArch64
::
ADDSXri
:
case
AArch64
::
ADDWri
:
case
AArch64
::
ADDXri
:
{
if
(
!
MI
.
getOperand
(
0
)
.
isReg
(
)
||
!
MI
.
getOperand
(
1
)
.
isReg
(
)
||
!
MI
.
getOperand
(
2
)
.
isImm
(
)
)
return
;
Offset
=
MI
.
getOperand
(
2
)
.
getImm
(
)
*
Sign
;
int
Shift
=
MI
.
getOperand
(
3
)
.
getImm
(
)
;
assert
(
(
Shift
==
0
||
Shift
==
12
)
&&
"Shift can be either 0 or 12"
)
;
Offset
=
Offset
<<
Shift
;
}
}
return
RegImmPair
{
MI
.
getOperand
(
1
)
.
getReg
(
)
,
Offset
}
;
}
</s>

If the specific machine instruction is an instruction that adds an immediate value and a register , and stores the result in the given register Reg , return a pair of the source register and the offset which has been added .


"Can't store this register to stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> void ARMPassConfig :: addPreEmitPass ( ) { addPass ( createThumb2SizeReductionPass ( ) ) ; if ( getARMSubtarget ( ) . isThumb2 ( ) ) addPass ( & UnpackMachineBundlesID ) ; addPass ( createARMOptimizeBarriersPass ( ) ) ; addPass ( createARMConstantIslandPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
static
void
pa_output_function_prologue
(
FILE
*
file
)
{
ASM_OUTPUT_LABEL
(
file
,
XSTR
(
XEXP
(
DECL_RTL
(
current_function_decl
)
,
0
)
,
0
)
)
;
fputs
(
"\t.PROC\n"
,
file
)
;
fprintf
(
file
,
"\t.CALLINFO FRAME="
HOST_WIDE_INT_PRINT_DEC
,
actual_fsize
)
;
if
(
crtl
->
is_leaf
)
fputs
(
",NO_CALLS"
,
file
)
;
else
fputs
(
",CALLS"
,
file
)
;
if
(
rp_saved
)
fputs
(
",SAVE_RP"
,
file
)
;
if
(
frame_pointer_needed
)
fputs
(
",SAVE_SP"
,
file
)
;
if
(
gr_saved
)
fprintf
(
file
,
",ENTRY_GR=%d"
,
gr_saved
+
2
)
;
if
(
fr_saved
)
fprintf
(
file
,
",ENTRY_FR=%d"
,
fr_saved
+
11
)
;
fputs
(
"\n\t.ENTRY\n"
,
file
)
;
remove_useless_addtr_insns
(
0
)
;
}
</s>

On HP-PA , move-double insns between fpu and cpu need an 8-byte block of memory . If any fpu reg is used in the function , we allocate such a block here , at the bottom of the frame , just in case it 's needed . If this function is a leaf procedure , then we may choose not to do a `` save '' insn . The decision about whether or not to do this is made in regclass.c .


<s> static bool rx_mode_dependent_address_p ( const_rtx addr , addr_space_t as ATTRIBUTE_UNUSED ) { if ( GET_CODE ( addr ) == CONST ) addr = XEXP ( addr , 0 ) ; switch ( GET_CODE ( addr ) ) { case PRE_DEC : case POST_INC : return true ; case MINUS : case PLUS : if ( ! REG_P ( XEXP ( addr , 0 ) ) ) return true ; addr = XEXP ( addr , 1 ) ; switch ( GET_CODE ( addr ) ) { case REG : return true ; case CONST_INT : if ( ( ( INTVAL ( addr ) & 3 ) == 0 ) && IN_RANGE ( INTVAL ( addr ) , 4 , 0xfffc ) ) return false ; return true ; case SYMBOL_REF : case LABEL_REF : return true ; case MULT : return true ; default : return true ; } case CONST_INT : case SYMBOL_REF : case LABEL_REF : case REG : return false ; default : return true ; } } </s>


<s> static int microblaze_version_to_int ( const char * version ) { const char * p , * v ; const char * tmpl = "vXX.YY.Z" ; int iver = 0 ; p = version ; v = tmpl ; while ( * p ) { if ( * v == 'X' ) { if ( * p == '.' ) { * v ++ ; } else { if ( ! ( * p >= '0' && * p <= '9' ) ) return - 1 ; iver += ( int ) ( * p - '0' ) ; iver *= 10 ; } } else if ( * v == 'Y' ) { if ( ! ( * p >= '0' && * p <= '9' ) ) return - 1 ; iver += ( int ) ( * p - '0' ) ; iver *= 10 ; } else if ( * v == 'Z' ) { if ( ! ( * p >= 'a' && * p <= 'z' ) ) return - 1 ; iver *= 10 ; iver += ( int ) ( * p - 'a' ) ; } else { if ( * p != * v ) return - 1 ; } v ++ ; p ++ ; } if ( * p ) return - 1 ; return iver ; } </s>

Convert a version number of the form `` vX.YY.Z '' to an integer encoding for easier range comparison .


<s>
bool
MMIXAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Operands
.
push_back
(
MMIXOperand
::
createToken
(
Name
,
NameLoc
)
)
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
return
false
;
if
(
parseOperand
(
Operands
)
)
return
true
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
getLexer
(
)
.
Lex
(
)
;
if
(
parseOperand
(
Operands
)
)
return
true
;
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
getParser
(
)
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
getParser
(
)
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

MMIX
MMIX
MMIXOperand::createToken
"unexpected token"


<s>
void
BPFInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
BPF
::
GPRRegClass
.
contains
(
DestReg
,
SrcReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
BPF
::
MOV_rr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
</s>

BPF
BPF
BPF::GPRRegClass
BPF::MOV_rr
"Impossible reg-to-reg copy"


<s> void ARMBankConflictHazardRecognizer :: Reset ( ) { Accesses . clear ( ) ; } </s>


<s> int mips_can_use_return_insn ( ) { if ( ! reload_completed ) return 0 ; if ( regs_ever_live [ 31 ] || current_function_profile ) return 0 ; if ( TARGET_MIPS16 && mips16_hard_float && ! aggregate_value_p ( DECL_RESULT ( current_function_decl ) ) && ( GET_MODE_CLASS ( DECL_MODE ( DECL_RESULT ( current_function_decl ) ) ) == MODE_FLOAT ) && ( ! TARGET_SINGLE_FLOAT || ( GET_MODE_SIZE ( DECL_MODE ( DECL_RESULT ( current_function_decl ) ) ) <= 4 ) ) ) return 0 ; if ( current_frame_info . initialized ) return current_frame_info . total_size == 0 ; return compute_frame_size ( get_frame_size ( ) ) == 0 ; } </s>

Return nonzero if this function is known to have a null epilogue . This allows the optimizer to omit jumps to jumps if no stack was created .


<s>
bool
AMDGPULegalizerInfo
::
legalizeCustom
(
MachineInstr
&
MI
,
MachineRegisterInfo
&
MRI
,
MachineIRBuilder
&
B
,
GISelChangeObserver
&
Observer
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
case
TargetOpcode
::
G_ADDRSPACE_CAST
:
return
legalizeAddrSpaceCast
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FRINT
:
return
legalizeFrint
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FCEIL
:
return
legalizeFceil
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_INTRINSIC_TRUNC
:
return
legalizeIntrinsicTrunc
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_SITOFP
:
return
legalizeITOFP
(
MI
,
MRI
,
B
,
true
)
;
case
TargetOpcode
::
G_UITOFP
:
return
legalizeITOFP
(
MI
,
MRI
,
B
,
false
)
;
case
TargetOpcode
::
G_FMINNUM
:
case
TargetOpcode
::
G_FMAXNUM
:
case
TargetOpcode
::
G_FMINNUM_IEEE
:
case
TargetOpcode
::
G_FMAXNUM_IEEE
:
return
legalizeMinNumMaxNum
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_EXTRACT_VECTOR_ELT
:
return
legalizeExtractVectorElt
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_INSERT_VECTOR_ELT
:
return
legalizeInsertVectorElt
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FSIN
:
case
TargetOpcode
::
G_FCOS
:
return
legalizeSinCos
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_GLOBAL_VALUE
:
return
legalizeGlobalValue
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_LOAD
:
return
legalizeLoad
(
MI
,
MRI
,
B
,
Observer
)
;
case
TargetOpcode
::
G_FMAD
:
return
legalizeFMad
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FDIV
:
return
legalizeFDIV
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_ATOMIC_CMPXCHG
:
return
legalizeAtomicCmpXChg
(
MI
,
MRI
,
B
)
;
default
:
return
false
;
}
llvm_unreachable
(
"expected switch to return"
)
;
}
</s>

Called for instructions with the Custom LegalizationAction .

AMDGPU
AMDGPU
SI
SI
SI
"expected switch to return"


<s> void reset ( ) { Packet . clear ( ) ; ResourcesModel -> clearResources ( ) ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s> bool PPCFastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { MVT VT ; if ( ! isLoadTypeLegal ( LI -> getType ( ) , VT ) ) return false ; bool IsZExt = false ; switch ( MI -> getOpcode ( ) ) { default : return false ; case PPC :: RLDICL : case PPC :: RLDICL_32_64 : { IsZExt = true ; unsigned MB = MI -> getOperand ( 3 ) . getImm ( ) ; if ( ( VT == MVT :: i8 && MB <= 56 ) || ( VT == MVT :: i16 && MB <= 48 ) || ( VT == MVT :: i32 && MB <= 32 ) ) break ; return false ; } case PPC :: RLWINM : case PPC :: RLWINM8 : { IsZExt = true ; unsigned MB = MI -> getOperand ( 3 ) . getImm ( ) ; if ( ( VT == MVT :: i8 && MB <= 24 ) || ( VT == MVT :: i16 && MB <= 16 ) ) break ; return false ; } case PPC :: EXTSB : case PPC :: EXTSB8 : case PPC :: EXTSB8_32_64 : return false ; case PPC :: EXTSH : case PPC :: EXTSH8 : case PPC :: EXTSH8_32_64 : { if ( VT != MVT :: i16 && VT != MVT :: i8 ) return false ; break ; } case PPC :: EXTSW : case PPC :: EXTSW_32_64 : { if ( VT != MVT :: i32 && VT != MVT :: i16 && VT != MVT :: i8 ) return false ; break ; } } Address Addr ; if ( ! PPCComputeAddress ( LI -> getOperand ( 0 ) , Addr ) ) return false ; unsigned ResultReg = MI -> getOperand ( 0 ) . getReg ( ) ; if ( ! PPCEmitLoad ( VT , ResultReg , Addr , 0 , IsZExt ) ) return false ; MI -> eraseFromParent ( ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> unsigned X86InstrInfo :: getUndefRegClearance ( const MachineInstr * MI , unsigned & OpNum , const TargetRegisterInfo * TRI ) const { if ( ! hasUndefRegUpdate ( MI -> getOpcode ( ) ) ) return 0 ; OpNum = 1 ; const MachineOperand & MO = MI -> getOperand ( OpNum ) ; if ( MO . isUndef ( ) && TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) ) { return 16 ; } return 0 ; } </s>

Inform the BreakFalseDeps pass how many idle instructions we would like before certain undef register reads .


<s> static void s390_init_frame_layout ( void ) { HOST_WIDE_INT frame_size ; int base_used ; gcc_assert ( ! reload_completed ) ; if ( ! TARGET_CPU_ZARCH ) cfun -> machine -> split_branches_pending_p = true ; do { frame_size = cfun_frame_layout . frame_size ; base_used = cfun -> machine -> split_branches_pending_p || crtl -> uses_const_pool || ( ! DISP_IN_RANGE ( frame_size ) && ! CONST_OK_FOR_K ( frame_size ) ) ; if ( ! base_used ) cfun -> machine -> base_reg = NULL_RTX ; else if ( crtl -> is_leaf && ! df_regs_ever_live_p ( 5 ) ) cfun -> machine -> base_reg = gen_rtx_REG ( Pmode , 5 ) ; else cfun -> machine -> base_reg = gen_rtx_REG ( Pmode , BASE_REGNUM ) ; s390_register_info ( ) ; s390_frame_info ( ) ; } while ( frame_size != cfun_frame_layout . frame_size ) ; } </s>

Generate frame layout . Fills in register and frame data for the current function in cfun- > machine . This routine can be called multiple times ; it will re-do the complete frame layout every time .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; initialize ( MF ) ; return removeLD ( ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool loongarch_canonicalize_int_order_test ( enum rtx_code * code , rtx * cmp1 , machine_mode mode ) { HOST_WIDE_INT plus_one ; if ( loongarch_int_order_operand_ok_p ( * code , * cmp1 ) ) return true ; if ( CONST_INT_P ( * cmp1 ) ) switch ( * code ) { case LE : plus_one = trunc_int_for_mode ( UINTVAL ( * cmp1 ) + 1 , mode ) ; if ( INTVAL ( * cmp1 ) < plus_one ) { * code = LT ; * cmp1 = force_reg ( mode , GEN_INT ( plus_one ) ) ; return true ; } break ; case LEU : plus_one = trunc_int_for_mode ( UINTVAL ( * cmp1 ) + 1 , mode ) ; if ( plus_one != 0 ) { * code = LTU ; * cmp1 = force_reg ( mode , GEN_INT ( plus_one ) ) ; return true ; } break ; default : break ; } return false ; } </s>

Return true if * CMP1 ( of mode MODE ) is a valid second operand for integer ordering test * CODE , or if an equivalent combination can be formed by adjusting * CODE and * CMP1 . When returning true , update * CODE and * CMP1 with the chosen code and operand , otherwise leave them alone .


<s> static rtx frv_expand_voidaccop_builtin ( enum insn_code icode , tree call ) { rtx pat ; rtx op0 = frv_read_argument ( call , 0 ) ; rtx op1 = frv_read_argument ( call , 1 ) ; rtx op2 ; rtx op3 ; op0 = frv_int_to_acc ( icode , 0 , op0 ) ; if ( ! op0 ) return NULL_RTX ; op1 = frv_int_to_acc ( icode , 1 , op1 ) ; if ( ! op1 ) return NULL_RTX ; op2 = frv_matching_accg_for_acc ( op0 ) ; op3 = frv_matching_accg_for_acc ( op1 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 , op2 , op3 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return NULL_RTX ; } </s>

Expand builtins that perform accumulator-to-accumulator operations . These builtins take two accumulator numbers as argument and return void .


<s>
const
char
*
nds32_output_casesi_pc_relative
(
rtx
*
operands
)
{
machine_mode
mode
;
rtx
diff_vec
;
diff_vec
=
PATTERN
(
NEXT_INSN
(
as_a
<
rtx_insn
*
>
(
operands
[
1
]
)
)
)
;
gcc_assert
(
GET_CODE
(
diff_vec
)
==
ADDR_DIFF_VEC
)
;
if
(
flag_pic
)
{
output_asm_insn
(
"sethi\t$ta, hi20(%l1@GOTOFF)"
,
operands
)
;
output_asm_insn
(
"ori\t$ta, $ta, lo12(%l1@GOTOFF)"
,
operands
)
;
output_asm_insn
(
"add\t$ta, $ta, $gp"
,
operands
)
;
}
else
output_asm_insn
(
"la\t$ta, %l1"
,
operands
)
;
mode
=
GET_MODE
(
diff_vec
)
;
switch
(
mode
)
{
case
E_QImode
:
output_asm_insn
(
"lb\t%2, [$ta + %0 << 0]"
,
operands
)
;
break
;
case
E_HImode
:
output_asm_insn
(
"lh\t%2, [$ta + %0 << 1]"
,
operands
)
;
break
;
case
E_SImode
:
output_asm_insn
(
"lw\t%2, [$ta + %0 << 2]"
,
operands
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
output_asm_insn
(
"add\t$ta, %2, $ta"
,
operands
)
;
if
(
TARGET_16_BIT
)
return
"jr5\t$ta"
;
else
return
"jr\t$ta"
;
}
</s>

Function to generate PC relative jump table . Refer to nds32.md for more details . The following is the sample for the case that diff value can be presented in '.short ' size . addi $ r1 , $ r1 , - ( case_lower_bound ) slti $ ta , $ r1 , ( case_number ) beqz $ ta , .L_skip_label la $ ta , .L35 ! get jump table address lh $ r1 , [ $ ta + $ r1 < < 1 ] ! load symbol diff from jump table entry addi $ ta , $ r1 , $ ta jr5 $ ta ! jump table entry L35 : .short .L25-.L35 .short .L26-.L35 .short .L27-.L35 .short .L28-.L35 .short .L29-.L35 .short .L30-.L35 .short .L31-.L35 .short .L32-.L35 .short .L33-.L35 .short .L34-.L35


<s> virtual const Cpu0Subtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> unsigned HexagonInstrInfo :: getSize ( const MachineInstr * MI ) const { if ( MI -> isDebugValue ( ) || MI -> isPosition ( ) ) return 0 ; unsigned Size = MI -> getDesc ( ) . getSize ( ) ; if ( ! Size ) Size = HEXAGON_INSTR_SIZE ; if ( isConstExtended ( MI ) || isExtended ( MI ) ) Size += HEXAGON_INSTR_SIZE ; return Size ; } </s>

Return the number of bytes in the encoding of this instruction , or zero if the encoding size can not be known from the opcode .


<s> DecodeStatus Cpu0Disassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & VStream , raw_ostream & CStream ) const { uint32_t Insn ; DecodeStatus Result ; Result = readInstruction32 ( Bytes , Address , Size , Insn , IsBigEndian ) ; if ( Result == MCDisassembler :: Fail ) return Result ; Result = decodeInstruction ( DecoderTableCpu032 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; } return Result ; } </s>

Returns the disassembly of a single instruction .


<s> static rtx avr_default_expand_builtin ( enum insn_code icode , tree exp , rtx target ) { rtx pat , xop [ 3 ] ; int n , n_args = call_expr_nargs ( exp ) ; machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; gcc_assert ( n_args >= 1 && n_args <= 3 ) ; if ( target == NULL_RTX || GET_MODE ( target ) != tmode || ! insn_data [ icode ] . operand [ 0 ] . predicate ( target , tmode ) ) { target = gen_reg_rtx ( tmode ) ; } for ( n = 0 ; n < n_args ; n ++ ) { tree arg = CALL_EXPR_ARG ( exp , n ) ; rtx op = expand_expr ( arg , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; machine_mode opmode = GET_MODE ( op ) ; machine_mode mode = insn_data [ icode ] . operand [ n + 1 ] . mode ; if ( ( opmode == SImode || opmode == VOIDmode ) && mode == HImode ) { opmode = HImode ; op = gen_lowpart ( HImode , op ) ; } gcc_assert ( opmode == mode || opmode == VOIDmode ) ; if ( ! insn_data [ icode ] . operand [ n + 1 ] . predicate ( op , mode ) ) op = copy_to_mode_reg ( mode , op ) ; xop [ n ] = op ; } switch ( n_args ) { case 1 : pat = GEN_FCN ( icode ) ( target , xop [ 0 ] ) ; break ; case 2 : pat = GEN_FCN ( icode ) ( target , xop [ 0 ] , xop [ 1 ] ) ; break ; case 3 : pat = GEN_FCN ( icode ) ( target , xop [ 0 ] , xop [ 1 ] , xop [ 2 ] ) ; break ; default : gcc_unreachable ( ) ; } if ( pat == NULL_RTX ) return NULL_RTX ; emit_insn ( pat ) ; return target ; } </s>

Subroutine of avr_expand_builtin to expand vanilla builtins with non-void result and 1 ... 3 arguments .


<s> static unsigned int insn_is_load_p ( rtx insn ) { rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) == SET ) { if ( GET_CODE ( SET_SRC ( body ) ) == MEM ) return 1 ; if ( GET_CODE ( SET_SRC ( body ) ) == VEC_SELECT && GET_CODE ( XEXP ( SET_SRC ( body ) , 0 ) ) == MEM ) return 1 ; return 0 ; } if ( GET_CODE ( body ) != PARALLEL ) return 0 ; rtx set = XVECEXP ( body , 0 , 0 ) ; if ( GET_CODE ( set ) == SET && GET_CODE ( SET_SRC ( set ) ) == MEM ) return 1 ; return 0 ; } </s>

Return 1 iff INSN is a load insn , including permuting loads that represent an lvxd2x instruction ; else return 0 .


<s>
void
SIInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
Register
DestReg
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
SIMachineFunctionInfo
*
MFI
=
MF
->
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MachineFrameInfo
&
FrameInfo
=
MF
->
getFrameInfo
(
)
;
const
DebugLoc
&
DL
=
MBB
.
findDebugLoc
(
MI
)
;
unsigned
SpillSize
=
TRI
->
getSpillSize
(
*
RC
)
;
MachinePointerInfo
PtrInfo
=
MachinePointerInfo
::
getFixedStack
(
*
MF
,
FrameIndex
)
;
MachineMemOperand
*
MMO
=
MF
->
getMachineMemOperand
(
PtrInfo
,
MachineMemOperand
::
MOLoad
,
FrameInfo
.
getObjectSize
(
FrameIndex
)
,
FrameInfo
.
getObjectAlign
(
FrameIndex
)
)
;
if
(
RI
.
isSGPRClass
(
RC
)
)
{
MFI
->
setHasSpilledSGPRs
(
)
;
assert
(
DestReg
!=
AMDGPU
::
M0
&&
"m0 should not be reloaded into"
)
;
const
MCInstrDesc
&
OpDesc
=
get
(
getSGPRSpillRestoreOpcode
(
SpillSize
)
)
;
if
(
DestReg
.
isVirtual
(
)
&&
SpillSize
==
4
)
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
MRI
.
constrainRegClass
(
DestReg
,
&
AMDGPU
::
SReg_32_XM0RegClass
)
;
}
if
(
RI
.
spillSGPRToVGPR
(
)
)
FrameInfo
.
setStackID
(
FrameIndex
,
TargetStackID
::
SGPRSpill
)
;
BuildMI
(
MBB
,
MI
,
DL
,
OpDesc
,
DestReg
)
.
addFrameIndex
(
FrameIndex
)
.
addMemOperand
(
MMO
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
,
RegState
::
Implicit
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
,
RegState
::
Implicit
)
;
return
;
}
unsigned
Opcode
=
RI
.
hasAGPRs
(
RC
)
getAGPRSpillRestoreOpcode
(
SpillSize
)
:
getVGPRSpillRestoreOpcode
(
SpillSize
)
;
auto
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opcode
)
,
DestReg
)
;
if
(
RI
.
hasAGPRs
(
RC
)
)
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
Register
Tmp
=
MRI
.
createVirtualRegister
(
&
AMDGPU
::
VGPR_32RegClass
)
;
MIB
.
addReg
(
Tmp
,
RegState
::
Define
)
;
}
MIB
.
addFrameIndex
(
FrameIndex
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> X86Subtarget :: X86Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , unsigned StackAlignOverride , bool is64Bit ) : X86GenSubtargetInfo ( TT , CPU , FS ) , X86ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , In64BitMode ( is64Bit ) { initializeEnvironment ( ) ; resetSubtargetFeatures ( CPU , FS ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"SI Shrink Instructions"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void R600InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { O . flush ( ) ; printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s>
MCSymbol
*
XNCMMCInstLower
::
GetExternalSymbolSymbol
(
const
MachineOperand
&
MO
)
const
{
switch
(
MO
.
getTargetFlags
(
)
)
{
default
:
llvm_unreachable
(
"Unknown target flag on GV operand"
)
;
case
0
:
break
;
}
return
Printer
.
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
;
}
</s>

Return the MCSymbol for the specified ExternalSymbol .

XNCM
XNCM
"Unknown target flag on GV operand"
0


<s> const char * host_detect_local_cpu ( int argc , const char * * argv ) { static const struct cpu_types { long implver ; long amask ; const char * const cpu ; } cpu_types [ ] = { { IMPLVER_EV7_FAMILY , AMASK_BWX | AMASK_MVI | AMASK_FIX | AMASK_CIX , "ev67" } , { IMPLVER_EV6_FAMILY , AMASK_BWX | AMASK_MVI | AMASK_FIX | AMASK_CIX , "ev67" } , { IMPLVER_EV6_FAMILY , AMASK_BWX | AMASK_MVI | AMASK_FIX , "ev6" } , { IMPLVER_EV5_FAMILY , AMASK_BWX | AMASK_MVI , "pca56" } , { IMPLVER_EV5_FAMILY , AMASK_BWX , "ev56" } , { IMPLVER_EV5_FAMILY , 0 , "ev5" } , { IMPLVER_EV4_FAMILY , 0 , "ev4" } , { 0 , 0 , NULL } } ; long implver ; long amask ; const char * cpu ; int i ; if ( argc < 1 ) return NULL ; if ( strcmp ( argv [ 0 ] , "cpu" ) && strcmp ( argv [ 0 ] , "tune" ) ) return NULL ; implver = __builtin_alpha_implver ( ) ; amask = __builtin_alpha_amask ( ~ 0L ) ; cpu = NULL ; for ( i = 0 ; cpu_types [ i ] . cpu != NULL ; i ++ ) if ( implver == cpu_types [ i ] . implver && ( ~ amask & cpu_types [ i ] . amask ) == cpu_types [ i ] . amask ) { cpu = cpu_types [ i ] . cpu ; break ; } if ( cpu == NULL ) return NULL ; return concat ( "-m" , argv [ 0 ] , "=" , cpu , NULL ) ; } </s>

This will be called by the spec parser in gcc.cc when it sees a % : local_cpu_detect ( args ) construct . Currently it will be called with either `` cpu '' or `` tune '' as argument depending on if -mcpu=native or -mtune=native is to be substituted . It returns a string containing new command line parameters to be put at the place of the above two options , depending on what CPU this is executed . E.g . `` -mcpu=ultrasparc3 '' on an UltraSPARC III for -mcpu=native . If the routine ca n't detect a known processor , the -mcpu or -mtune option is discarded . ARGC and ARGV are set depending on the actual arguments given in the spec .


<s> static rtx nios2_function_arg ( cumulative_args_t cum_v , machine_mode mode , const_tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; rtx return_rtx = NULL_RTX ; if ( cum -> regs_used < NUM_ARG_REGS ) return_rtx = gen_rtx_REG ( mode , FIRST_ARG_REGNO + cum -> regs_used ) ; return return_rtx ; } </s>

Define where to put the arguments to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) .


<s> unsigned postOffset ( unsigned LogAlign = 0 ) const { unsigned PO = Offset + Size ; unsigned LA = std :: max ( unsigned ( PostAlign ) , LogAlign ) ; if ( ! LA ) return PO ; return WorstCaseAlign ( PO , LA , internalKnownBits ( ) ) ; } </s>

Compute the offset immediately following this block .


<s> bool ARMTTIImpl :: isLegalMaskedGather ( Type * Ty , Align Alignment ) { if ( ! EnableMaskedGatherScatters || ! ST -> hasMVEIntegerOps ( ) ) return false ; unsigned EltWidth = Ty -> getScalarSizeInBits ( ) ; return ( ( EltWidth == 32 && Alignment >= 4 ) || ( EltWidth == 16 && Alignment >= 2 ) || EltWidth == 8 ) ; } </s>

Return true if the target supports masked gather .


<s> bool rs6000_pcrel_p ( ) { return ( DEFAULT_ABI == ABI_ELFv2 && ( rs6000_isa_flags & OPTION_MASK_PCREL ) != 0 && TARGET_CMODEL == CMODEL_MEDIUM ) ; } </s>

Return whether we should generate PC-relative code for the current function .


<s>
bool
SPScheduler
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
if
(
!
mf
.
getInfo
<
PatmosMachineFunctionInfo
>
(
)
->
isSinglePath
(
)
)
{
return
false
;
}
DEBUG
(
dbgs
(
)
<<
"Running SPScheduler on function '"
<<
mf
.
getName
(
)
<<
"'\n"
)
;
auto
reduceAnalysis
=
&
getAnalysis
<
PatmosSPReduce
>
(
)
;
auto
rootScope
=
reduceAnalysis
->
RootScope
;
for
(
auto
mbbIter
=
mf
.
begin
(
)
,
mbbEnd
=
mf
.
end
(
)
;
mbbIter
!=
mbbEnd
;
mbbIter
++
)
{
auto
mbb
=
&
(
*
mbbIter
)
;
DEBUG
(
dbgs
(
)
<<
"MBB: ["
<<
mbb
<<
"]: #"
<<
mbb
->
getNumber
(
)
<<
"\n"
)
;
for
(
auto
instrIter
=
mbb
->
begin
(
)
,
instrEnd
=
mbb
->
end
(
)
;
instrIter
!=
instrEnd
;
instrIter
++
)
{
SPInstructions
++
;
calculateLatency
(
instrIter
)
;
}
}
DEBUG
(
dbgs
(
)
<<
"AFTER Single-Path Schedule\n"
;
mf
.
dump
(
)
)
;
DEBUG
(
{
dbgs
(
)
<<
"Scope tree after scheduling:\n"
;
rootScope
->
dump
(
dbgs
(
)
,
0
,
true
)
;
}
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .

Patmos
Patmos
"Running SPScheduler on function '"
"'\n"
Patmos
"MBB: ["
"]: #"
"\n"
"AFTER Single-Path Schedule\n"
"Scope tree after scheduling:\n"
0


<s>
const
char
*
emit_fusion_p9_load
(
rtx
reg
,
rtx
mem
,
rtx
tmp_reg
)
{
enum
machine_mode
mode
=
GET_MODE
(
reg
)
;
rtx
hi
;
rtx
lo
;
rtx
addr
;
const
char
*
load_string
;
int
r
;
if
(
GET_CODE
(
mem
)
==
FLOAT_EXTEND
||
GET_CODE
(
mem
)
==
ZERO_EXTEND
)
{
mem
=
XEXP
(
mem
,
0
)
;
mode
=
GET_MODE
(
mem
)
;
}
if
(
GET_CODE
(
reg
)
==
SUBREG
)
{
gcc_assert
(
SUBREG_BYTE
(
reg
)
==
0
)
;
reg
=
SUBREG_REG
(
reg
)
;
}
if
(
!
REG_P
(
reg
)
)
fatal_insn
(
"emit_fusion_p9_load, bad reg #1"
,
reg
)
;
r
=
REGNO
(
reg
)
;
if
(
FP_REGNO_P
(
r
)
)
{
if
(
mode
==
SFmode
)
load_string
=
"lfs"
;
else
if
(
mode
==
DFmode
||
mode
==
DImode
)
load_string
=
"lfd"
;
else
gcc_unreachable
(
)
;
}
else
if
(
INT_REGNO_P
(
r
)
)
{
switch
(
mode
)
{
case
QImode
:
load_string
=
"lbz"
;
break
;
case
HImode
:
load_string
=
"lhz"
;
break
;
case
SImode
:
case
SFmode
:
load_string
=
"lwz"
;
break
;
case
DImode
:
case
DFmode
:
if
(
!
TARGET_POWERPC64
)
gcc_unreachable
(
)
;
load_string
=
"ld"
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
else
fatal_insn
(
"emit_fusion_p9_load, bad reg #2"
,
reg
)
;
if
(
!
MEM_P
(
mem
)
)
fatal_insn
(
"emit_fusion_p9_load not MEM"
,
mem
)
;
addr
=
XEXP
(
mem
,
0
)
;
fusion_split_address
(
addr
,
&
hi
,
&
lo
)
;
emit_fusion_addis
(
tmp_reg
,
hi
,
"power9 load fusion"
,
GET_MODE_NAME
(
mode
)
)
;
emit_fusion_load_store
(
reg
,
tmp_reg
,
lo
,
load_string
)
;
return
""
;
}
</s>

Return a string to fuse an addis instruction with a load using extended fusion . The address that is used is the logical address that was formed during peephole2 : ( lo_sum ( high ) ( low-part ) ) The code is complicated , so we call output_asm_insn directly , and just return `` '' .

rs6000
0
0
"emit_fusion_p9_load, bad reg #1"
"lfs"
"lfd"
"lbz"
"lhz"
"lwz"
"ld"
"emit_fusion_p9_load, bad reg #2"
"emit_fusion_p9_load not MEM"
0
"power9 load fusion"
""


<s> const uint16_t * NVPTXRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { 0 } ; return CalleeSavedRegs ; } </s>


<s> ix86_dependencies_evaluation_hook static int ix86_reassociation_width ( unsigned int op , machine_mode mode ) { int width = 1 ; if ( VECTOR_MODE_P ( mode ) ) { int div = 1 ; if ( INTEGRAL_MODE_P ( mode ) ) width = ix86_cost -> reassoc_vec_int ; else if ( FLOAT_MODE_P ( mode ) ) width = ix86_cost -> reassoc_vec_fp ; if ( width == 1 ) return 1 ; if ( ix86_tune == PROCESSOR_ZNVER1 && INTEGRAL_MODE_P ( mode ) && op != PLUS && op != MINUS ) return 1 ; if ( TARGET_AVX128_OPTIMAL && GET_MODE_BITSIZE ( mode ) > 128 ) div = GET_MODE_BITSIZE ( mode ) / 128 ; else if ( TARGET_SSE_SPLIT_REGS && GET_MODE_BITSIZE ( mode ) > 64 ) div = GET_MODE_BITSIZE ( mode ) / 64 ; width = ( width + div - 1 ) / div ; } else if ( INTEGRAL_MODE_P ( mode ) ) width = ix86_cost -> reassoc_int ; else if ( FLOAT_MODE_P ( mode ) ) width = ix86_cost -> reassoc_fp ; if ( ! TARGET_64BIT && width > 2 ) width = 2 ; return width ; } </s>

Implementation of reassociation_width target hook used by reassoc phase to identify parallelism level in reassociated tree . Statements tree_code is passed in OPC . Arguments type is passed in MODE . Currently parallel reassociation is enabled for Atom processors only and we set reassociation width to be 2 because Atom may issue up to 2 instructions per cycle . Return value should be fixed if parallel reassociation is enabled for other processors .


<s> bool SICAsmPrinter :: lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) { MCOp = MCInstLowering . LowerOperand ( MO ) ; return MCOp . isValid ( ) ; } </s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> void emitBundleAlignMode ( unsigned AlignPow2 ) override { } </s>

Set the bundle alignment mode from now on in the section .


<s> const Z80oldSubtarget * Z80oldTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < 512 > Key ; Key . reserve ( CPU . size ( ) + FS . size ( ) ) ; Key += CPU ; Key += FS ; bool SoftFloat = true ; if ( SoftFloat ) { Key += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; } unsigned CPUFSWidth = Key . size ( ) ; FS = Key . slice ( CPU . size ( ) , CPUFSWidth ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < Z80oldSubtarget > ( TargetTriple , CPU , FS , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


"Load should return a value and a chain"

LowerOperation - Provide custom lowering hooks for some operations .


<s> TargetLowering :: AtomicExpansionKind AMDGPUTargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * RMW ) const { switch ( RMW -> getOperation ( ) ) { case AtomicRMWInst :: Nand : case AtomicRMWInst :: FAdd : case AtomicRMWInst :: FSub : return AtomicExpansionKind :: CmpXChg ; default : return AtomicExpansionKind :: None ; } } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> SDValue PPCTargetLowering :: LowerCall ( TargetLowering :: CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const { SelectionDAG & DAG = CLI . DAG ; SDLoc & dl = CLI . DL ; SmallVectorImpl < ISD :: OutputArg > & Outs = CLI . Outs ; SmallVectorImpl < SDValue > & OutVals = CLI . OutVals ; SmallVectorImpl < ISD :: InputArg > & Ins = CLI . Ins ; SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; bool & isTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool isVarArg = CLI . IsVarArg ; if ( isTailCall ) isTailCall = IsEligibleForTailCallOptimization ( Callee , CallConv , isVarArg , Ins , DAG ) ; if ( PPCSubTarget . isSVR4ABI ( ) ) { if ( PPCSubTarget . isPPC64 ( ) ) return LowerCall_64SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; else return LowerCall_32SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; } return LowerCall_Darwin ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; } </s>

This hook must be implemented to lower calls into the specified DAG .

PowerPC PPC ISD::OutputArg ISD::InputArg PPC PPC PPC


<s> void NVPTXFrameLowering :: emitPrologue ( MachineFunction & MF ) const { if ( MF . getFrameInfo ( ) -> hasStackObjects ( ) ) { MachineBasicBlock & MBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = DebugLoc ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( is64bit ) { unsigned LocalReg = MRI . createVirtualRegister ( & NVPTX :: Int64RegsRegClass ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , dl , MF . getSubtarget ( ) . getInstrInfo ( ) -> get ( NVPTX :: cvta_local_yes_64 ) , NVPTX :: VRFrame ) . addReg ( LocalReg ) ; BuildMI ( MBB , MI , dl , MF . getSubtarget ( ) . getInstrInfo ( ) -> get ( NVPTX :: MOV_DEPOT_ADDR_64 ) , LocalReg ) . addImm ( MF . getFunctionNumber ( ) ) ; } else { unsigned LocalReg = MRI . createVirtualRegister ( & NVPTX :: Int32RegsRegClass ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , dl , MF . getSubtarget ( ) . getInstrInfo ( ) -> get ( NVPTX :: cvta_local_yes ) , NVPTX :: VRFrame ) . addReg ( LocalReg ) ; BuildMI ( MBB , MI , dl , MF . getSubtarget ( ) . getInstrInfo ( ) -> get ( NVPTX :: MOV_DEPOT_ADDR ) , LocalReg ) . addImm ( MF . getFunctionNumber ( ) ) ; } } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> void setMBB ( MachineBasicBlock * MBBv ) { MBB = MBBv ; } </s>

Set the insertion point to the end of MBB .


<s> void EmitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) override { EmitA64MappingSymbol ( ) ; MCELFStreamer :: EmitInstruction ( Inst , STI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


"JIT relocation model must be set to static or default!"


<s>
unsigned
M88kIncomingValueHandler
::
assignCustomValue
(
CallLowering
::
ArgInfo
&
Arg
,
ArrayRef
<
CCValAssign
>
VAs
,
std
::
function
<
void
(
)
>
*
Thunk
)
{
assert
(
Arg
.
Regs
.
size
(
)
==
1
&&
"Can't handle multple regs yet"
)
;
CCValAssign
VA
=
VAs
[
0
]
;
assert
(
VA
.
needsCustom
(
)
&&
"Value doesn't need custom handling"
)
;
if
(
VA
.
getValVT
(
)
!=
MVT
::
f64
)
return
0
;
CCValAssign
NextVA
=
VAs
[
1
]
;
assert
(
NextVA
.
needsCustom
(
)
&&
"Value doesn't need custom handling"
)
;
assert
(
NextVA
.
getValVT
(
)
==
MVT
::
f64
&&
"Unsupported type"
)
;
assert
(
VA
.
getValNo
(
)
==
NextVA
.
getValNo
(
)
&&
"Values belong to different arguments"
)
;
assert
(
VA
.
isRegLoc
(
)
&&
"Value should be in reg"
)
;
assert
(
NextVA
.
isRegLoc
(
)
&&
"Value should be in reg"
)
;
Register
NewRegs
[
]
=
{
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
32
)
)
,
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
32
)
)
}
;
assignValueToReg
(
NewRegs
[
0
]
,
VA
.
getLocReg
(
)
,
VA
)
;
assignValueToReg
(
NewRegs
[
1
]
,
NextVA
.
getLocReg
(
)
,
NextVA
)
;
MIRBuilder
.
buildMerge
(
Arg
.
Regs
[
0
]
,
NewRegs
)
;
return
1
;
}
</s>

Handle custom values , which may be passed into one or more of VAs .


<s> rtx loongarch_unspec_address ( rtx address , enum loongarch_symbol_type symbol_type ) { rtx base , offset ; split_const ( address , & base , & offset ) ; return loongarch_unspec_address_offset ( base , offset , symbol_type ) ; } </s>

Return an UNSPEC address with underlying address ADDRESS and symbol type SYMBOL_TYPE .


<s> const char * ARCompactTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case ARCISD :: CALL : return "ARCISD::CALL" ; case ARCISD :: CMP : return "ARCISD::CMP" ; case ARCISD :: BR_CC : return "ARCISD::BR_CC" ; case ARCISD :: SELECT_CC : return "ARCISD::SELECT_CC" ; case ARCISD :: Wrapper : return "ARCISD::Wrapper" ; case ARCISD :: RET_FLAG : return "ARCISD::RET_FLAG" ; default : return 0 ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s>
void
A57ChainingConstraint
::
apply
(
PBQPRAGraph
&
G
)
{
const
MachineFunction
&
MF
=
G
.
getMetadata
(
)
.
MF
;
LiveIntervals
&
LIs
=
G
.
getMetadata
(
)
.
LIS
;
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
LLVM_DEBUG
(
MF
.
dump
(
)
)
;
for
(
const
auto
&
MBB
:
MF
)
{
Chains
.
clear
(
)
;
for
(
const
auto
&
MI
:
MBB
)
{
for
(
auto
r
:
Chains
)
{
SmallVector
<
unsigned
,
8
>
toDel
;
if
(
regJustKilledBefore
(
LIs
,
r
,
MI
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Killing chain "
<<
printReg
(
r
,
TRI
)
<<
" at "
;
MI
.
print
(
dbgs
(
)
)
;
)
;
toDel
.
push_back
(
r
)
;
}
while
(
!
toDel
.
empty
(
)
)
{
Chains
.
remove
(
toDel
.
back
(
)
)
;
toDel
.
pop_back
(
)
;
}
}
switch
(
MI
.
getOpcode
(
)
)
{
case
AArch64
::
FMSUBSrrr
:
case
AArch64
::
FMADDSrrr
:
case
AArch64
::
FNMSUBSrrr
:
case
AArch64
::
FNMADDSrrr
:
case
AArch64
::
FMSUBDrrr
:
case
AArch64
::
FMADDDrrr
:
case
AArch64
::
FNMSUBDrrr
:
case
AArch64
::
FNMADDDrrr
:
{
Register
Rd
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
Register
Ra
=
MI
.
getOperand
(
3
)
.
getReg
(
)
;
if
(
addIntraChainConstraint
(
G
,
Rd
,
Ra
)
)
addInterChainConstraint
(
G
,
Rd
,
Ra
)
;
break
;
}
case
AArch64
::
FMLAv2f32
:
case
AArch64
::
FMLSv2f32
:
{
Register
Rd
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
addInterChainConstraint
(
G
,
Rd
,
Rd
)
;
break
;
}
default
:
break
;
}
}
}
}
</s>

Apply the profile inference algorithm for a given function .


"Builtin vec_step can only be used on vector types."

Expand builtins which can directly be mapped to tree expressions . LOC - location information FCODE - function code of the builtin ARGLIST - value supposed to be passed as arguments RETURN-TYPE - expected return type of the builtin


<s> bool mayNeedRelaxation ( MCInst const & Inst , const MCSubtargetInfo & STI ) const override { return true ; } </s>

Check whether the given instruction may need relaxation .


<s> void MOSTargetMachine :: registerPassBuilderCallbacks ( PassBuilder & PB ) { PB . registerPipelineParsingCallback ( [ ] ( StringRef Name , LoopPassManager & PM , ArrayRef < PassBuilder :: PipelineElement > ) { if ( Name == "mos-indexiv" ) { PM . addPass ( MOSIndexIV ( ) ) ; return true ; } return false ; } ) ; PB . registerLateLoopOptimizationsEPCallback ( [ ] ( LoopPassManager & PM , OptimizationLevel Level ) { if ( Level != OptimizationLevel :: O0 ) { PM . addPass ( MOSIndexIV ( ) ) ; PM . addPass ( IndVarSimplifyPass ( ) ) ; } } ) ; } </s>

Invoke the PassBuilder callback registration .


<s> int first_fp_reg_to_save ( void ) { int first_reg ; for ( first_reg = 14 + 32 ; first_reg <= 63 ; first_reg ++ ) if ( regs_ever_live [ first_reg ] ) break ; return first_reg ; } </s>


<s> int mcore_is_dead ( rtx first , rtx reg ) { rtx insn ; if ( GET_CODE ( reg ) == SUBREG ) reg = SUBREG_REG ( reg ) ; if ( dead_or_set_p ( first , reg ) ) return 1 ; for ( insn = NEXT_INSN ( first ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( GET_CODE ( insn ) == JUMP_INSN ) return 0 ; else if ( GET_CODE ( insn ) == CALL_INSN ) { if ( reg_referenced_p ( reg , PATTERN ( insn ) ) || find_reg_fusage ( insn , USE , reg ) ) return 0 ; else if ( dead_or_set_p ( insn , reg ) ) return 1 ; } else if ( GET_CODE ( insn ) == INSN ) { if ( reg_referenced_p ( reg , PATTERN ( insn ) ) ) return 0 ; else if ( dead_or_set_p ( insn , reg ) ) return 1 ; } } return 0 ; } </s>

Check whether reg is dead at first . This is done by searching ahead for either the next use ( i.e. , reg is live ) , a death note , or a set of reg . Do n't just use dead_or_set_p ( ) since reload does not always mark deaths ( especially if PRESERVE_DEATH_NOTES_REGNO_P is not defined ) . We can ignore subregs by extracting the actual register . BRC


<s> bool OR1KAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( ( Count % 4 ) != 0 ) return false ; for ( uint64_t i = 0 ; i < Count ; i += 4 ) OW -> Write32 ( 0x15000000 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> static reg_class_t reduce_class ( reg_class_t original_class , reg_class_t limiting_class , reg_class_t returned_if_empty ) { HARD_REG_SET cc ; int i ; reg_class_t best = NO_REGS ; unsigned int best_size = 0 ; if ( original_class == limiting_class ) return original_class ; cc = reg_class_contents [ original_class ] ; AND_HARD_REG_SET ( cc , reg_class_contents [ limiting_class ] ) ; for ( i = 0 ; i < LIM_REG_CLASSES ; i ++ ) { if ( hard_reg_set_subset_p ( reg_class_contents [ i ] , cc ) ) if ( best_size < reg_class_size [ i ] ) { best = ( reg_class_t ) i ; best_size = reg_class_size [ i ] ; } } if ( best == NO_REGS ) return returned_if_empty ; return best ; } </s>

Given two register classes , find the largest intersection between them . If there is no intersection , return RETURNED_IF_EMPTY instead .


<s>
static
bool
use_vfp_abi
(
enum
arm_pcs
pcs_variant
,
bool
is_double
)
{
if
(
pcs_variant
==
ARM_PCS_AAPCS_VFP
)
{
static
bool
seen_thumb1_vfp
=
false
;
if
(
TARGET_THUMB1
&&
!
seen_thumb1_vfp
)
{
sorry
(
"Thumb-1 hard-float VFP ABI"
)
;
seen_thumb1_vfp
=
true
;
}
return
true
;
}
if
(
pcs_variant
!=
ARM_PCS_AAPCS_LOCAL
)
return
false
;
return
(
TARGET_32BIT
&&
TARGET_VFP
&&
TARGET_HARD_FLOAT
&&
(
TARGET_VFP_DOUBLE
||
!
is_double
)
)
;
}
</s>

Return true if PCS_VARIANT should use VFP registers .


<s> bool isKMergeMasked ( ) const { return ( Attributes & KMergeMasked ) != 0 ; } </s>

Returns true iff the group of FMA opcodes holds k-merge-masked opcodes .


<s> bool partialVCCWritesUpdateVCCZ ( ) const { return getGeneration ( ) >= GFX10 ; } </s>

Writes to VCC_LO/VCC_HI update the VCCZ flag .


"RISCV DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s>
static
void
mips_output_function_prologue
(
FILE
*
file
)
{
const
char
*
fnname
;
if
(
TARGET_MIPS16
&&
TARGET_HARD_FLOAT_ABI
&&
crtl
->
args
.
info
.
fp_code
!=
0
)
mips16_build_function_stub
(
)
;
fnname
=
XSTR
(
XEXP
(
DECL_RTL
(
current_function_decl
)
,
0
)
,
0
)
;
mips_start_function_definition
(
fnname
,
TARGET_MIPS16
)
;
if
(
!
flag_inhibit_size_directive
)
{
const
struct
mips_frame_info
*
frame
;
frame
=
&
cfun
->
machine
->
frame
;
fprintf
(
file
,
"\t.frame\t%s,"
HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
"# vars= "
HOST_WIDE_INT_PRINT_DEC
", regs= %d/%d"
", args= "
HOST_WIDE_INT_PRINT_DEC
", gp= "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
reg_names
[
frame_pointer_needed
HARD_FRAME_POINTER_REGNUM
:
STACK_POINTER_REGNUM
]
,
(
frame_pointer_needed
frame
->
total_size
frame
->
hard_frame_pointer_offset
:
frame
->
total_size
)
,
reg_names
[
RETURN_ADDR_REGNUM
]
,
frame
->
var_size
,
frame
->
num_gp
,
frame
->
num_fp
,
frame
->
args_size
,
frame
->
cprestore_size
)
;
fprintf
(
file
,
"\t.mask\t0x%08x,"
HOST_WIDE_INT_PRINT_DEC
"\n"
,
frame
->
mask
,
frame
->
gp_save_offset
)
;
fprintf
(
file
,
"\t.fmask\t0x%08x,"
HOST_WIDE_INT_PRINT_DEC
"\n"
,
frame
->
fmask
,
frame
->
fp_save_offset
)
;
}
if
(
mips_must_initialize_gp_p
(
)
&&
mips_current_loadgp_style
(
)
==
LOADGP_OLDABI
)
{
if
(
TARGET_MIPS16
)
{
output_asm_insn
(
"li\t$2,%%hi(_gp_disp)"
,
0
)
;
output_asm_insn
(
"addiu\t$3,$pc,%%lo(_gp_disp)"
,
0
)
;
output_asm_insn
(
"sll\t$2,16"
,
0
)
;
output_asm_insn
(
"addu\t$2,$3"
,
0
)
;
}
else
{
mips_push_asm_switch
(
&
mips_noreorder
)
;
output_asm_insn
(
".cpload\t%^"
,
0
)
;
if
(
!
cfun
->
machine
->
all_noreorder_p
)
mips_pop_asm_switch
(
&
mips_noreorder
)
;
else
mips_push_asm_switch
(
&
mips_nomacro
)
;
}
}
else
if
(
cfun
->
machine
->
all_noreorder_p
)
{
mips_push_asm_switch
(
&
mips_noreorder
)
;
mips_push_asm_switch
(
&
mips_nomacro
)
;
}
mips_output_cplocal
(
)
;
}
</s>

Set up the stack and frame ( if desired ) for the function .


runOnMachineFunction - Emit the function body .


<s> TargetTransformInfo NVPTXTargetMachine :: getTargetTransformInfo ( const Function & F ) { return TargetTransformInfo ( NVPTXTTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> void PPCFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - 1 ; bool DisableRedZone = MF . getFunction ( ) -> getFnAttributes ( ) . hasNoRedZoneAttr ( ) ; if ( ! DisableRedZone && FrameSize <= 224 && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! ( Subtarget . isPPC64 ( ) && Subtarget . isSVR4ABI ( ) && spillsCR ( MF ) ) && ( ! ALIGN_STACK || MaxAlign <= TargetAlign ) ) { MFI -> setStackSize ( 0 ) ; return ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getMinCallFrameSize ( Subtarget . isPPC64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; MFI -> setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s> bool nds32_n9_2r1w_mm_to_ex_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx def_reg ; switch ( get_attr_type ( producer ) ) { case TYPE_LOAD : if ( post_update_insn_p ( producer ) ) return false ; def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; case TYPE_MUL : case TYPE_MAC : def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; default : gcc_unreachable ( ) ; } return n9_2r1w_consumed_by_ex_dep_p ( consumer , def_reg ) ; } </s>