<s> unsigned X86TargetLowering :: getByValTypeAlignment ( Type * Ty ) const { if ( Subtarget -> is64Bit ( ) ) { unsigned TyAlign = TD -> getABITypeAlignment ( Ty ) ; if ( TyAlign > 8 ) return TyAlign ; return 8 ; } unsigned Align = 4 ; if ( Subtarget -> hasXMM ( ) ) getMaxByValAlign ( Ty , Align ) ; return Align ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


"Splitting double registers in function: "

"Register partitioning: (partition #0 is fixed)\n"

runOnMachineFunction - Emit the function body .


<s> unsigned RISCVInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : { return get ( Opcode ) . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return 0 ; case RISCV :: PseudoCALL : case RISCV :: PseudoTAIL : return 8 ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const auto & TM = static_cast < const RISCVTargetMachine & > ( MF . getTarget ( ) ) ; return getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> static tree ix86_veclibabi_acml ( enum built_in_function fn , tree type_out , tree type_in ) { char name [ 20 ] = "__vr.._" ; tree fntype , new_fndecl , args ; unsigned arity ; const char * bname ; machine_mode el_mode , in_mode ; int n , in_n ; if ( ! TARGET_64BIT || ! flag_unsafe_math_optimizations ) return NULL_TREE ; el_mode = TYPE_MODE ( TREE_TYPE ( type_out ) ) ; n = TYPE_VECTOR_SUBPARTS ( type_out ) ; in_mode = TYPE_MODE ( TREE_TYPE ( type_in ) ) ; in_n = TYPE_VECTOR_SUBPARTS ( type_in ) ; if ( el_mode != in_mode || n != in_n ) return NULL_TREE ; switch ( fn ) { case BUILT_IN_SIN : case BUILT_IN_COS : case BUILT_IN_EXP : case BUILT_IN_LOG : case BUILT_IN_LOG2 : case BUILT_IN_LOG10 : name [ 4 ] = 'd' ; name [ 5 ] = '2' ; if ( el_mode != DFmode || n != 2 ) return NULL_TREE ; break ; case BUILT_IN_SINF : case BUILT_IN_COSF : case BUILT_IN_EXPF : case BUILT_IN_POWF : case BUILT_IN_LOGF : case BUILT_IN_LOG2F : case BUILT_IN_LOG10F : name [ 4 ] = 's' ; name [ 5 ] = '4' ; if ( el_mode != SFmode || n != 4 ) return NULL_TREE ; break ; default : return NULL_TREE ; } bname = IDENTIFIER_POINTER ( DECL_NAME ( builtin_decl_implicit ( fn ) ) ) ; sprintf ( name + 7 , "%s" , bname + 10 ) ; arity = 0 ; for ( args = DECL_ARGUMENTS ( builtin_decl_implicit ( fn ) ) ; args ; args = TREE_CHAIN ( args ) ) arity ++ ; if ( arity == 1 ) fntype = build_function_type_list ( type_out , type_in , NULL ) ; else fntype = build_function_type_list ( type_out , type_in , type_in , NULL ) ; new_fndecl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , fntype ) ; TREE_PUBLIC ( new_fndecl ) = 1 ; DECL_EXTERNAL ( new_fndecl ) = 1 ; DECL_IS_NOVOPS ( new_fndecl ) = 1 ; TREE_READONLY ( new_fndecl ) = 1 ; return new_fndecl ; } </s>

Handler for an ACML-style interface to a library with vectorized intrinsics .


<s> static void aarch64_expand_builtin_va_start ( tree valist , rtx nextarg ATTRIBUTE_UNUSED ) { const CUMULATIVE_ARGS * cum ; tree f_stack , f_grtop , f_vrtop , f_groff , f_vroff ; tree stack , grtop , vrtop , groff , vroff ; tree t ; int gr_save_area_size ; int vr_save_area_size ; int vr_offset ; cum = & crtl -> args . info ; gr_save_area_size = ( NUM_ARG_REGS - cum -> aapcs_ncrn ) * UNITS_PER_WORD ; vr_save_area_size = ( NUM_FP_ARG_REGS - cum -> aapcs_nvrn ) * UNITS_PER_VREG ; if ( ! TARGET_FLOAT ) { gcc_assert ( cum -> aapcs_nvrn == 0 ) ; vr_save_area_size = 0 ; } f_stack = TYPE_FIELDS ( va_list_type_node ) ; f_grtop = DECL_CHAIN ( f_stack ) ; f_vrtop = DECL_CHAIN ( f_grtop ) ; f_groff = DECL_CHAIN ( f_vrtop ) ; f_vroff = DECL_CHAIN ( f_groff ) ; stack = build3 ( COMPONENT_REF , TREE_TYPE ( f_stack ) , valist , f_stack , NULL_TREE ) ; grtop = build3 ( COMPONENT_REF , TREE_TYPE ( f_grtop ) , valist , f_grtop , NULL_TREE ) ; vrtop = build3 ( COMPONENT_REF , TREE_TYPE ( f_vrtop ) , valist , f_vrtop , NULL_TREE ) ; groff = build3 ( COMPONENT_REF , TREE_TYPE ( f_groff ) , valist , f_groff , NULL_TREE ) ; vroff = build3 ( COMPONENT_REF , TREE_TYPE ( f_vroff ) , valist , f_vroff , NULL_TREE ) ; t = make_tree ( TREE_TYPE ( stack ) , virtual_incoming_args_rtx ) ; if ( cum -> aapcs_stack_size > 0 ) t = fold_build_pointer_plus_hwi ( t , cum -> aapcs_stack_size * UNITS_PER_WORD ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( stack ) , stack , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( grtop ) , virtual_incoming_args_rtx ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( grtop ) , grtop , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( vrtop ) , virtual_incoming_args_rtx ) ; vr_offset = ROUND_UP ( gr_save_area_size , STACK_BOUNDARY / BITS_PER_UNIT ) ; if ( vr_offset ) t = fold_build_pointer_plus_hwi ( t , - vr_offset ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( vrtop ) , vrtop , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( groff ) , groff , build_int_cst ( TREE_TYPE ( groff ) , - gr_save_area_size ) ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( vroff ) , vroff , build_int_cst ( TREE_TYPE ( vroff ) , - vr_save_area_size ) ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; } </s>


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> bool AArch64PassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnablePromoteConstant ) addPass ( createAArch64PromoteConstantPass ( ) ) ; if ( ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE ) addPass ( createGlobalMergePass ( TM , 4095 ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createAArch64AddressTypePromotionPass ( ) ) ; return false ; } </s>


"Unexpected operand for inline assembly"

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> Nios2ExprKind getKind ( ) const { return Kind ; } </s>


<s> void SystemZPassConfig :: addPostRewrite ( ) { addPass ( createSystemZPostRewritePass ( getSystemZTargetMachine ( ) ) ) ; } </s>

Add passes to be run immediately after virtual registers are rewritten to physical registers .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Hexagon Hardware Loops"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool SystemZInstrInfo :: FoldImmediate ( MachineInstr & UseMI , MachineInstr & DefMI , unsigned Reg , MachineRegisterInfo * MRI ) const { unsigned DefOpc = DefMI . getOpcode ( ) ; if ( DefOpc != SystemZ :: LHIMux && DefOpc != SystemZ :: LHI && DefOpc != SystemZ :: LGHI ) return false ; if ( DefMI . getOperand ( 0 ) . getReg ( ) != Reg ) return false ; int32_t ImmVal = ( int32_t ) DefMI . getOperand ( 1 ) . getImm ( ) ; unsigned UseOpc = UseMI . getOpcode ( ) ; unsigned NewUseOpc ; unsigned UseIdx ; int CommuteIdx = - 1 ; switch ( UseOpc ) { case SystemZ :: LOCRMux : if ( ! STI . hasLoadStoreOnCond2 ( ) ) return false ; NewUseOpc = SystemZ :: LOCHIMux ; if ( UseMI . getOperand ( 2 ) . getReg ( ) == Reg ) UseIdx = 2 ; else if ( UseMI . getOperand ( 1 ) . getReg ( ) == Reg ) UseIdx = 2 , CommuteIdx = 1 ; else return false ; break ; case SystemZ :: LOCGR : if ( ! STI . hasLoadStoreOnCond2 ( ) ) return false ; NewUseOpc = SystemZ :: LOCGHI ; if ( UseMI . getOperand ( 2 ) . getReg ( ) == Reg ) UseIdx = 2 ; else if ( UseMI . getOperand ( 1 ) . getReg ( ) == Reg ) UseIdx = 2 , CommuteIdx = 1 ; else return false ; break ; default : return false ; } if ( CommuteIdx != - 1 ) if ( ! commuteInstruction ( UseMI , false , CommuteIdx , UseIdx ) ) return false ; bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ; UseMI . setDesc ( get ( NewUseOpc ) ) ; UseMI . getOperand ( UseIdx ) . ChangeToImmediate ( ImmVal ) ; if ( DeleteDef ) DefMI . eraseFromParent ( ) ; return true ; } </s>

Reg is known to be defined by a move immediate instruction , try to fold the immediate into the use instruction .


<s> void BPFPassConfig :: addIRPasses ( ) { addPass ( createBPFAbstractMemberAccess ( & getBPFTargetMachine ( ) ) ) ; addPass ( createBPFPreserveDIType ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> unsigned AMDGPUAsmParser :: checkTargetMatchPredicate ( MCInst & Inst ) { uint64_t TSFlags = MII . get ( Inst . getOpcode ( ) ) . TSFlags ; if ( ( getForcedEncodingSize ( ) == 32 && ( TSFlags & SIInstrFlags :: VOP3 ) ) || ( getForcedEncodingSize ( ) == 64 && ! ( TSFlags & SIInstrFlags :: VOP3 ) ) || ( isForcedDPP ( ) && ! ( TSFlags & SIInstrFlags :: DPP ) ) || ( isForcedSDWA ( ) && ! ( TSFlags & SIInstrFlags :: SDWA ) ) ) return Match_InvalidOperand ; if ( ( TSFlags & SIInstrFlags :: VOP3 ) && ( TSFlags & SIInstrFlags :: VOPAsmPrefer32Bit ) && getForcedEncodingSize ( ) != 64 ) return Match_PreferE32 ; if ( Inst . getOpcode ( ) == AMDGPU :: V_MAC_F32_sdwa_vi || Inst . getOpcode ( ) == AMDGPU :: V_MAC_F16_sdwa_vi ) { auto OpNum = AMDGPU :: getNamedOperandIdx ( Inst . getOpcode ( ) , AMDGPU :: OpName :: dst_sel ) ; const auto & Op = Inst . getOperand ( OpNum ) ; if ( ! Op . isImm ( ) || Op . getImm ( ) != AMDGPU :: SDWA :: SdwaSel :: DWORD ) { return Match_InvalidOperand ; } } return Match_Success ; } </s>

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


Return true if mn10300_output_mi_thunk would be able to output the assembler code for the thunk function specified by the arguments it is passed , and false otherwise .


<s> void MBlazeTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_WRITE | MCSectionELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , MCSectionELF :: SHT_NOBITS , MCSectionELF :: SHF_WRITE | MCSectionELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s> MachineInstr * Thumb2InstrInfo :: optimizeSelect ( MachineInstr & MI , SmallPtrSetImpl < MachineInstr * > & SeenMIs , bool PreferFalse ) const { MachineInstr * RV = ARMBaseInstrInfo :: optimizeSelect ( MI , SeenMIs , PreferFalse ) ; if ( ! RV && getSubtarget ( ) . hasV8_1MMainlineOps ( ) && ! PreferNoCSEL ) { Register DestReg = MI . getOperand ( 0 ) . getReg ( ) ; if ( ! DestReg . isVirtual ( ) ) return nullptr ; MachineInstrBuilder NewMI = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( ARM :: t2CSEL ) , DestReg ) . add ( MI . getOperand ( 2 ) ) . add ( MI . getOperand ( 1 ) ) . add ( MI . getOperand ( 3 ) ) ; SeenMIs . insert ( NewMI ) ; return NewMI ; } return RV ; } </s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


<s> bool X86InstrInfo :: isCoalescableExtInstr ( const MachineInstr & MI , unsigned & SrcReg , unsigned & DstReg , unsigned & SubIdx ) const { switch ( MI . getOpcode ( ) ) { default : break ; case X86 :: MOVSX16rr8 : case X86 :: MOVZX16rr8 : case X86 :: MOVSX32rr8 : case X86 :: MOVZX32rr8 : case X86 :: MOVSX64rr8 : if ( ! TM . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ) return false ; case X86 :: MOVSX32rr16 : case X86 :: MOVZX32rr16 : case X86 :: MOVSX64rr16 : case X86 :: MOVSX64rr32 : { if ( MI . getOperand ( 0 ) . getSubReg ( ) || MI . getOperand ( 1 ) . getSubReg ( ) ) return false ; SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; DstReg = MI . getOperand ( 0 ) . getReg ( ) ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( "Unreachable!" ) ; case X86 :: MOVSX16rr8 : case X86 :: MOVZX16rr8 : case X86 :: MOVSX32rr8 : case X86 :: MOVZX32rr8 : case X86 :: MOVSX64rr8 : SubIdx = X86 :: sub_8bit ; break ; case X86 :: MOVSX32rr16 : case X86 :: MOVZX32rr16 : case X86 :: MOVSX64rr16 : SubIdx = X86 :: sub_16bit ; break ; case X86 :: MOVSX64rr32 : SubIdx = X86 :: sub_32bit ; break ; } return true ; } } return false ; } </s>

isCoalescableExtInstr - Return true if the instruction is a `` coalescable '' extension instruction .


<s>
static
const
char
*
avr_out_load_psi_reg_no_disp_tiny
(
rtx_insn
*
insn
,
rtx
*
op
,
int
*
plen
)
{
rtx
dest
=
op
[
0
]
;
rtx
src
=
op
[
1
]
;
rtx
base
=
XEXP
(
src
,
0
)
;
int
reg_dest
=
true_regnum
(
dest
)
;
int
reg_base
=
true_regnum
(
base
)
;
if
(
reg_base
==
reg_dest
)
{
return
avr_asm_len
(
TINY_ADIW
(
%
E1
,
%
F1
,
2
)
CR_TAB
"ld %C0,%1"
CR_TAB
"ld __tmp_reg__,-%1"
CR_TAB
TINY_SBIW
(
%
E1
,
%
F1
,
1
)
CR_TAB
"ld %A0,%1"
CR_TAB
"mov %B0,__tmp_reg__"
,
op
,
plen
,
8
)
;
}
else
{
return
avr_asm_len
(
"ld %A0,%1+"
CR_TAB
"ld %B0,%1+"
CR_TAB
"ld %C0,%1"
,
op
,
plen
,
3
)
;
if
(
reg_dest
!=
reg_base
2
&&
!
reg_unused_after
(
insn
,
base
)
)
{
avr_asm_len
(
TINY_SBIW
(
%
E1
,
%
F1
,
2
)
,
op
,
plen
,
2
)
;
}
return
""
;
}
}
</s>

Handle loads of 24-bit types from memory to register .


<s> SDValue MSP430TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; AnalyzeReturnValues ( CCInfo , RVLocs , Ins ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> enum reg_class aarch64_regno_regclass ( unsigned regno ) { if ( STUB_REGNUM_P ( regno ) ) return STUB_REGS ; if ( GP_REGNUM_P ( regno ) ) return GENERAL_REGS ; if ( regno == SP_REGNUM ) return STACK_REG ; if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return POINTER_REGS ; if ( FP_REGNUM_P ( regno ) ) return ( FP_LO8_REGNUM_P ( regno ) ? FP_LO8_REGS : FP_LO_REGNUM_P ( regno ) ? FP_LO_REGS : FP_REGS ) ; if ( PR_REGNUM_P ( regno ) ) return PR_LO_REGNUM_P ( regno ) ? PR_LO_REGS : PR_HI_REGS ; if ( regno == FFR_REGNUM || regno == FFRT_REGNUM ) return FFR_REGS ; return NO_REGS ; } </s>


<s> bool mips_secondary_memory_needed ( enum reg_class class1 , enum reg_class class2 , machine_mode mode ) { if ( lra_in_progress && ( class1 == NO_REGS || class2 == NO_REGS ) ) return false ; if ( ( ( class1 == FP_REGS ) != ( class2 == FP_REGS ) ) && ( ( TARGET_FLOATXX && ! ISA_HAS_MXHC1 ) || TARGET_O32_FP64A_ABI ) && GET_MODE_SIZE ( mode ) >= 8 ) return true ; return false ; } </s>


<s> static rtx safe_vector_operand ( rtx x , machine_mode mode ) { if ( x != const0_rtx ) return x ; x = gen_reg_rtx ( mode ) ; emit_insn ( gen_iwmmxt_clrdi ( mode == DImode ? x : gen_rtx_SUBREG ( DImode , x , 0 ) ) ) ; return x ; } </s>

Errors in the source file can cause expand_expr to return const0_rtx where we expect a vector . To avoid crashing , use one of the vector clear instructions .


<s> unsigned AMDGPUInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


Output assembler code for a block containing the constant parts of a trampoline , leaving space for the variable parts.\ The trampoline sets the static chain pointer to STATIC_CHAIN_REGNUM and then branches to the specified routine . This code template is copied from text segment to stack location and then patched with pa_trampoline_init to contain valid values , and then entered as a subroutine . It is best to keep this as small as possible to avoid having to flush multiple lines in the cache .


<s> void rs6000_activate_target_options ( tree new_tree ) { cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( new_tree ) ) ; if ( TREE_TARGET_GLOBALS ( new_tree ) ) restore_target_globals ( TREE_TARGET_GLOBALS ( new_tree ) ) ; else if ( new_tree == target_option_default_node ) restore_target_globals ( & default_target_globals ) ; else TREE_TARGET_GLOBALS ( new_tree ) = save_target_globals_default_opts ( ) ; rs6000_previous_fndecl = NULL_TREE ; } </s>

Restore target 's globals from NEW_TREE and invalidate the rs6000_previous_fndecl cache .


<s> static void loongarch_extend_comparands ( rtx_code code , rtx * op0 , rtx * op1 ) { if ( GET_MODE_SIZE ( word_mode ) > GET_MODE_SIZE ( GET_MODE ( * op0 ) ) ) { if ( unsigned_condition ( code ) == code && GET_MODE ( * op0 ) == QImode ) { * op0 = gen_rtx_ZERO_EXTEND ( word_mode , * op0 ) ; if ( CONST_INT_P ( * op1 ) ) * op1 = GEN_INT ( ( uint8_t ) INTVAL ( * op1 ) ) ; else * op1 = gen_rtx_ZERO_EXTEND ( word_mode , * op1 ) ; } else { * op0 = gen_rtx_SIGN_EXTEND ( word_mode , * op0 ) ; if ( * op1 != const0_rtx ) * op1 = gen_rtx_SIGN_EXTEND ( word_mode , * op1 ) ; } } } </s>

Sign- or zero-extend OP0 and OP1 for integer comparisons .


<s> static void iq2000_emit_frame_related_store ( rtx mem , rtx reg , HOST_WIDE_INT offset ) { rtx dwarf_address = plus_constant ( Pmode , stack_pointer_rtx , offset ) ; rtx dwarf_mem = gen_rtx_MEM ( GET_MODE ( reg ) , dwarf_address ) ; iq2000_annotate_frame_insn ( emit_move_insn ( mem , reg ) , gen_rtx_SET ( GET_MODE ( reg ) , dwarf_mem , reg ) ) ; } </s>

Emit a move instruction that stores REG in MEM . Make the instruction frame related and note that it stores REG at ( SP + OFFSET ) .


<s> void visium_init_expanders ( void ) { init_machine_status = visium_init_machine_status ; } </s>

The per-function data machinery is needed to indicate when a frame is required .


"large return values not supported with %<-mabi=ti%> option"

"function pointers not supported with %<-mabi=ti%> option"

Check the function declaration FNTYPE for TI ABI compatibility .


<s> bool SNESFrameLowering :: canSimplifyCallFramePseudos ( const MachineFunction & MF ) const { return true ; } </s>

canSimplifyCallFramePseudos - If there is a reserved call frame , the call frame pseudos can be simplified .


<s>
void
BTFDebug
::
beginFunctionImpl
(
const
MachineFunction
*
MF
)
{
auto
*
SP
=
MF
->
getFunction
(
)
.
getSubprogram
(
)
;
auto
*
Unit
=
SP
->
getUnit
(
)
;
if
(
Unit
->
getEmissionKind
(
)
==
DICompileUnit
::
NoDebug
)
{
SkipInstruction
=
true
;
return
;
}
SkipInstruction
=
false
;
if
(
MapDefNotCollected
)
{
processGlobals
(
true
)
;
MapDefNotCollected
=
false
;
}
std
::
unordered_map
<
uint32_t
,
StringRef
>
FuncArgNames
;
for
(
const
DINode
*
DN
:
SP
->
getRetainedNodes
(
)
)
{
if
(
const
auto
*
DV
=
dyn_cast
<
DILocalVariable
>
(
DN
)
)
{
uint32_t
Arg
=
DV
->
getArg
(
)
;
if
(
Arg
)
{
visitTypeEntry
(
DV
->
getType
(
)
)
;
FuncArgNames
[
Arg
]
=
DV
->
getName
(
)
;
}
}
}
uint32_t
ProtoTypeId
;
visitSubroutineType
(
SP
->
getType
(
)
,
true
,
FuncArgNames
,
ProtoTypeId
)
;
uint8_t
Scope
=
SP
->
isLocalToUnit
(
)
BTF
::
FUNC_STATIC
:
BTF
::
FUNC_GLOBAL
;
auto
FuncTypeEntry
=
std
::
make_unique
<
BTFTypeFunc
>
(
SP
->
getName
(
)
,
ProtoTypeId
,
Scope
)
;
uint32_t
FuncTypeId
=
addType
(
std
::
move
(
FuncTypeEntry
)
)
;
for
(
const
DINode
*
DN
:
SP
->
getRetainedNodes
(
)
)
{
if
(
const
auto
*
DV
=
dyn_cast
<
DILocalVariable
>
(
DN
)
)
{
uint32_t
Arg
=
DV
->
getArg
(
)
;
if
(
Arg
)
processDeclAnnotations
(
DV
->
getAnnotations
(
)
,
FuncTypeId
,
Arg
1
)
;
}
}
processDeclAnnotations
(
SP
->
getAnnotations
(
)
,
FuncTypeId
,
1
)
;
for
(
const
auto
&
TypeEntry
:
TypeEntries
)
TypeEntry
->
completeType
(
*
this
)
;
MCSymbol
*
FuncLabel
=
Asm
->
getFunctionBegin
(
)
;
BTFFuncInfo
FuncInfo
;
FuncInfo
.
Label
=
FuncLabel
;
FuncInfo
.
TypeId
=
FuncTypeId
;
if
(
FuncLabel
->
isInSection
(
)
)
{
MCSection
&
Section
=
FuncLabel
->
getSection
(
)
;
const
MCSectionELF
*
SectionELF
=
dyn_cast
<
MCSectionELF
>
(
&
Section
)
;
assert
(
SectionELF
&&
"Null section for Function Label"
)
;
SecNameOff
=
addString
(
SectionELF
->
getName
(
)
)
;
}
else
{
SecNameOff
=
addString
(
".text"
)
;
}
FuncInfoTable
[
SecNameOff
]
.
push_back
(
FuncInfo
)
;
}
</s>


<s> unsigned char X86Subtarget :: classifyGlobalReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return X86II :: MO_NO_FLAG ; if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return classifyLocalReference ( GV ) ; if ( isTargetCOFF ( ) ) return X86II :: MO_DLLIMPORT ; if ( is64Bit ( ) ) return X86II :: MO_GOTPCREL ; if ( isTargetDarwin ( ) ) { if ( ! isPositionIndependent ( ) ) return X86II :: MO_DARWIN_NONLAZY ; return X86II :: MO_DARWIN_NONLAZY_PIC_BASE ; } return X86II :: MO_GOT ; } </s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s> SDValue R600TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; R600MachineFunctionInfo * MFI = MF . getInfo < R600MachineFunctionInfo > ( ) ; SmallVector < ISD :: InputArg , 8 > LocalIns ; if ( AMDGPU :: isShader ( CallConv ) ) { AnalyzeFormalArguments ( CCInfo , Ins ) ; } else { analyzeFormalArgumentsCompute ( CCInfo , Ins ) ; } for ( unsigned i = 0 , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const ISD :: InputArg & In = Ins [ i ] ; EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector ( ) ) { MemVT = MemVT . getVectorElementType ( ) ; } if ( AMDGPU :: isShader ( CallConv ) ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & AMDGPU :: R600_Reg128RegClass ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , AMDGPUASI . CONSTANT_BUFFER_0 ) ; ISD :: LoadExtType Ext = ISD :: NON_EXTLOAD ; if ( MemVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) { Ext = ISD :: SEXTLOAD ; } unsigned ValBase = ArgLocs [ In . getOrigArgIndex ( ) ] . getLocMemOffset ( ) ; unsigned PartOffset = VA . getLocMemOffset ( ) ; unsigned Offset = Subtarget -> getExplicitKernelArgOffset ( MF ) + VA . getLocMemOffset ( ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) , PartOffset - ValBase ) ; SDValue Arg = DAG . getLoad ( ISD :: UNINDEXED , Ext , VT , DL , Chain , DAG . getConstant ( Offset , DL , MVT :: i32 ) , DAG . getUNDEF ( MVT :: i32 ) , PtrInfo , MemVT , 4 , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; InVals . push_back ( Arg ) ; MFI -> setABIArgOffset ( Offset + MemVT . getStoreSize ( ) ) ; } return Chain ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> unsigned AArch64RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const AArch64FrameLowering * TFI = getFrameLowering ( MF ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case AArch64 :: GPR32RegClassID : case AArch64 :: GPR32spRegClassID : case AArch64 :: GPR32allRegClassID : case AArch64 :: GPR64spRegClassID : case AArch64 :: GPR64allRegClassID : case AArch64 :: GPR64RegClassID : case AArch64 :: GPR32commonRegClassID : case AArch64 :: GPR64commonRegClassID : return 32 - 1 - ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) - MF . getSubtarget < AArch64Subtarget > ( ) . isX18Reserved ( ) - hasBasePointer ( MF ) ; case AArch64 :: FPR8RegClassID : case AArch64 :: FPR16RegClassID : case AArch64 :: FPR32RegClassID : case AArch64 :: FPR64RegClassID : case AArch64 :: FPR128RegClassID : return 32 ; case AArch64 :: DDRegClassID : case AArch64 :: DDDRegClassID : case AArch64 :: DDDDRegClassID : case AArch64 :: QQRegClassID : case AArch64 :: QQQRegClassID : case AArch64 :: QQQQRegClassID : return 32 ; case AArch64 :: FPR128_loRegClassID : return 16 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> int pa_shadd_constant_p ( int val ) { if ( val == 2 || val == 4 || val == 8 ) return 1 ; else return 0 ; } </s>

Return 1 if the given constant is 2 , 4 , or 8 . These are the valid constants for shadd instructions .


<s> static void or1k_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain ) { const unsigned movhi_r13 = ( 0x06u << 26 ) | ( 13 << 21 ) ; const unsigned movhi_r11 = ( 0x06u << 26 ) | ( 11 << 21 ) ; const unsigned ori_r13_r13 = ( 0x2a << 26 ) | ( 13 << 21 ) | ( 13 << 16 ) ; const unsigned ori_r11_r11 = ( 0x2a << 26 ) | ( 11 << 21 ) | ( 11 << 16 ) ; const unsigned jr_r13 = ( 0x11 << 26 ) | ( 13 << 11 ) ; rtx tramp [ 5 ] , fnaddr , f_hi , f_lo , c_hi , c_lo ; fnaddr = force_operand ( XEXP ( DECL_RTL ( fndecl ) , 0 ) , NULL ) ; f_hi = expand_binop ( SImode , lshr_optab , fnaddr , GEN_INT ( 16 ) , NULL , true , OPTAB_DIRECT ) ; f_lo = expand_binop ( SImode , and_optab , fnaddr , GEN_INT ( 0xffff ) , NULL , true , OPTAB_DIRECT ) ; chain = force_operand ( chain , NULL ) ; c_hi = expand_binop ( SImode , lshr_optab , chain , GEN_INT ( 16 ) , NULL , true , OPTAB_DIRECT ) ; c_lo = expand_binop ( SImode , and_optab , chain , GEN_INT ( 0xffff ) , NULL , true , OPTAB_DIRECT ) ; tramp [ 0 ] = expand_binop ( SImode , ior_optab , f_hi , gen_int_mode ( movhi_r13 , SImode ) , f_hi , true , OPTAB_DIRECT ) ; tramp [ 1 ] = expand_binop ( SImode , ior_optab , c_hi , gen_int_mode ( movhi_r11 , SImode ) , c_hi , true , OPTAB_DIRECT ) ; tramp [ 2 ] = expand_binop ( SImode , ior_optab , f_lo , gen_int_mode ( ori_r13_r13 , SImode ) , f_lo , true , OPTAB_DIRECT ) ; tramp [ 4 ] = expand_binop ( SImode , ior_optab , c_lo , gen_int_mode ( ori_r11_r11 , SImode ) , c_lo , true , OPTAB_DIRECT ) ; tramp [ 3 ] = gen_int_mode ( jr_r13 , SImode ) ; for ( int i = 0 ; i < 5 ; ++ i ) { rtx mem = adjust_address ( m_tramp , SImode , i * 4 ) ; emit_move_insn ( mem , tramp [ i ] ) ; } } </s>

Worker for TARGET_TRAMPOLINE_INIT . This is called to initialize a trampoline . The argument M_TRAMP is an RTX for the memory block to be initialized with trampoline code . The argument FNDECL contains the definition of the nested function to be called , we use this to get the function 's address . The argument CHAIN is an RTX for the static chain value to be passed to the nested function .


<s> bool supportsEfficientVectorElementLoadStore ( ) { return false ; } </s>

If target has efficient vector element load/store instructions , it can return true here so that insertion/extraction costs are not added to the scalarization cost of a load/store .


<s>
bool
ARCFrameLowering
::
spillCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
ArrayRef
<
CalleeSavedInfo
>
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Spill callee saved registers: "
<<
MBB
.
getParent
(
)
->
getName
(
)
<<
"\n"
)
;
unsigned
Last
=
determineLastCalleeSave
(
CSI
)
;
if
(
UseSaveRestoreFunclet
&&
Last
>
ARC
::
R14
)
{
return
true
;
}
return
false
;
}
</s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .

ARC
ARC
"Spill callee saved registers: "
"\n"
ARC::R14


<s>
void
ARMTargetStreamer
::
emitInst
(
uint32_t
Inst
,
char
Suffix
)
{
unsigned
Size
;
char
Buffer
[
4
]
;
const
bool
LittleEndian
=
getStreamer
(
)
.
getContext
(
)
.
getAsmInfo
(
)
->
isLittleEndian
(
)
;
switch
(
Suffix
)
{
case
'\0'
:
Size
=
4
;
for
(
unsigned
II
=
0
,
IE
=
Size
;
II
!=
IE
;
II
++
)
{
const
unsigned
I
=
LittleEndian
(
Size
II
1
)
:
II
;
Buffer
[
Size
II
1
]
=
uint8_t
(
Inst
>>
I
*
CHAR_BIT
)
;
}
break
;
case
'n'
:
case
'w'
:
Size
=
(
Suffix
==
'n'
2
:
4
)
;
for
(
unsigned
II
=
0
,
IE
=
Size
;
II
!=
IE
;
II
=
II
+
2
)
{
const
unsigned
I0
=
LittleEndian
II
+
0
:
II
+
1
;
const
unsigned
I1
=
LittleEndian
II
+
1
:
II
+
0
;
Buffer
[
Size
II
2
]
=
uint8_t
(
Inst
>>
I0
*
CHAR_BIT
)
;
Buffer
[
Size
II
1
]
=
uint8_t
(
Inst
>>
I1
*
CHAR_BIT
)
;
}
break
;
default
:
llvm_unreachable
(
"Invalid Suffix"
)
;
}
getStreamer
(
)
.
emitBytes
(
StringRef
(
Buffer
,
Size
)
)
;
}
</s>

Callback used to implement the .inst directive .


<s> Instruction * PPCTargetLowering :: emitLeadingFence ( IRBuilderBase & Builder , Instruction * Inst , AtomicOrdering Ord ) const { if ( Ord == AtomicOrdering :: SequentiallyConsistent ) return callIntrinsic ( Builder , Intrinsic :: ppc_sync ) ; if ( isReleaseOrStronger ( Ord ) ) return callIntrinsic ( Builder , Intrinsic :: ppc_lwsync ) ; return nullptr ; } </s>


<s> bool PPCAsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { size_t Dot = Name . find ( '.' ) ; StringRef Mnemonic = Name . slice ( 0 , Dot ) ; Operands . push_back ( PPCOperand :: CreateToken ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; if ( Dot != StringRef :: npos ) { SMLoc DotLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Dot ) ; StringRef DotStr = Name . slice ( Dot , StringRef :: npos ) ; Operands . push_back ( PPCOperand :: CreateToken ( DotStr , DotLoc , isPPC64 ( ) ) ) ; } if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( ParseOperand ( Operands ) ) return true ; while ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) && getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( ParseOperand ( Operands ) ) return true ; } return false ; } </s>

ParseInstruction - Parse one assembly instruction .


<s> unsigned int aarch64_tlsdesc_abi_id ( ) { predefined_function_abi & tlsdesc_abi = function_abis [ ARM_PCS_TLSDESC ] ; if ( ! tlsdesc_abi . initialized_p ( ) ) { HARD_REG_SET full_reg_clobbers ; CLEAR_HARD_REG_SET ( full_reg_clobbers ) ; SET_HARD_REG_BIT ( full_reg_clobbers , R0_REGNUM ) ; SET_HARD_REG_BIT ( full_reg_clobbers , CC_REGNUM ) ; for ( int regno = P0_REGNUM ; regno <= P15_REGNUM ; ++ regno ) SET_HARD_REG_BIT ( full_reg_clobbers , regno ) ; tlsdesc_abi . initialize ( ARM_PCS_TLSDESC , full_reg_clobbers ) ; } return tlsdesc_abi . id ( ) ; } </s>

Return the ID of the TLDESC ABI , initializing the descriptor if has n't been already .


<s> const MCExpr * getSubExpr ( ) const { return SubExpr ; } </s>

getSubExpr - Get the child of this expression .


<s>
void
SystemZInstrInfo
::
insertSelect
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DstReg
,
ArrayRef
<
MachineOperand
>
Pred
,
unsigned
TrueReg
,
unsigned
FalseReg
)
const
{
MachineRegisterInfo
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
const
TargetRegisterClass
*
RC
=
MRI
.
getRegClass
(
DstReg
)
;
assert
(
Pred
.
size
(
)
==
2
&&
"Invalid condition"
)
;
unsigned
CCValid
=
Pred
[
0
]
.
getImm
(
)
;
unsigned
CCMask
=
Pred
[
1
]
.
getImm
(
)
;
unsigned
Opc
;
if
(
SystemZ
::
GRX32BitRegClass
.
hasSubClassEq
(
RC
)
)
{
if
(
STI
.
hasMiscellaneousExtensions3
(
)
)
Opc
=
SystemZ
::
SELRMux
;
else
if
(
STI
.
hasLoadStoreOnCond2
(
)
)
Opc
=
SystemZ
::
LOCRMux
;
else
{
Opc
=
SystemZ
::
LOCR
;
MRI
.
constrainRegClass
(
DstReg
,
&
SystemZ
::
GR32BitRegClass
)
;
unsigned
TReg
=
MRI
.
createVirtualRegister
(
&
SystemZ
::
GR32BitRegClass
)
;
unsigned
FReg
=
MRI
.
createVirtualRegister
(
&
SystemZ
::
GR32BitRegClass
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
TargetOpcode
::
COPY
)
,
TReg
)
.
addReg
(
TrueReg
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
TargetOpcode
::
COPY
)
,
FReg
)
.
addReg
(
FalseReg
)
;
TrueReg
=
TReg
;
FalseReg
=
FReg
;
}
}
else
if
(
SystemZ
::
GR64BitRegClass
.
hasSubClassEq
(
RC
)
)
{
if
(
STI
.
hasMiscellaneousExtensions3
(
)
)
Opc
=
SystemZ
::
SELGR
;
else
Opc
=
SystemZ
::
LOCGR
;
}
else
llvm_unreachable
(
"Invalid register class"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DstReg
)
.
addReg
(
FalseReg
)
.
addReg
(
TrueReg
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
;
}
</s>

Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true , and FalseReg to DstReg when Cond is false .


<s> enum reg_class secondary_input_reload_class ( enum reg_class class , enum machine_mode mode , rtx x ) { enum reg_class default_class = GET_MODE_SIZE ( mode ) >= 4 ? DPREGS : DREGS ; enum reg_class x_class = NO_REGS ; enum rtx_code code = GET_CODE ( x ) ; if ( code == SUBREG ) x = SUBREG_REG ( x ) , code = GET_CODE ( x ) ; if ( REG_P ( x ) ) { int regno = REGNO ( x ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) regno = reg_renumber [ regno ] ; if ( regno == - 1 ) code = MEM ; else x_class = REGNO_REG_CLASS ( regno ) ; } if ( fp_plus_const_operand ( x , mode ) ) { rtx op2 = XEXP ( x , 1 ) ; int large_constant_p = ! CONST_7BIT_IMM_P ( INTVAL ( op2 ) ) ; if ( class == PREGS || class == PREGS_CLOBBERED ) return NO_REGS ; if ( class == DREGS || class == DPREGS ) return large_constant_p ? PREGS : NO_REGS ; return PREGS ; } if ( x_class == AREGS ) return class == DREGS || class == AREGS ? NO_REGS : DREGS ; if ( class == AREGS ) { if ( x != const0_rtx && x_class != DREGS ) return DREGS ; else return NO_REGS ; } if ( class == CCREGS && x_class != DREGS ) return DREGS ; if ( x_class == CCREGS && class != DREGS ) return DREGS ; if ( code == MEM ) if ( ! reg_class_subset_p ( class , default_class ) ) return default_class ; return NO_REGS ; } </s>

Inform reload about cases where moving X with a mode MODE to a register in CLASS requires an extra scratch register . Return the class needed for the scratch register .


"internal error: instruction without _e64 suffix "

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s>
void
PTXInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DstReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
const
MachineRegisterInfo
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
for
(
int
i
=
0
,
e
=
sizeof
(
map
)
/
sizeof
(
map
[
0
]
)
;
i
!=
e
;
++
i
)
{
if
(
map
[
i
]
.
cls
==
MRI
.
getRegClass
(
DstReg
)
)
{
const
MCInstrDesc
&
MCID
=
get
(
map
[
i
]
.
opcode
)
;
MachineInstr
*
MI
=
BuildMI
(
MBB
,
I
,
DL
,
MCID
,
DstReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
AddDefaultPredicate
(
MI
)
;
return
;
}
}
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
</s>


<s>
void
X86AvoidSFBPass
::
buildCopy
(
MachineInstr
*
LoadInst
,
unsigned
NLoadOpcode
,
int64_t
LoadDisp
,
MachineInstr
*
StoreInst
,
unsigned
NStoreOpcode
,
int64_t
StoreDisp
,
unsigned
Size
,
int64_t
LMMOffset
,
int64_t
SMMOffset
)
{
MachineOperand
&
LoadBase
=
getBaseOperand
(
LoadInst
)
;
MachineOperand
&
StoreBase
=
getBaseOperand
(
StoreInst
)
;
MachineBasicBlock
*
MBB
=
LoadInst
->
getParent
(
)
;
MachineMemOperand
*
LMMO
=
*
LoadInst
->
memoperands_begin
(
)
;
MachineMemOperand
*
SMMO
=
*
StoreInst
->
memoperands_begin
(
)
;
unsigned
Reg1
=
MRI
->
createVirtualRegister
(
TII
->
getRegClass
(
TII
->
get
(
NLoadOpcode
)
,
0
,
TRI
,
*
(
MBB
->
getParent
(
)
)
)
)
;
MachineInstr
*
NewLoad
=
BuildMI
(
*
MBB
,
LoadInst
,
LoadInst
->
getDebugLoc
(
)
,
TII
->
get
(
NLoadOpcode
)
,
Reg1
)
.
add
(
LoadBase
)
.
addImm
(
1
)
.
addReg
(
X86
::
NoRegister
)
.
addImm
(
LoadDisp
)
.
addReg
(
X86
::
NoRegister
)
.
addMemOperand
(
MBB
->
getParent
(
)
->
getMachineMemOperand
(
LMMO
,
LMMOffset
,
Size
)
)
;
if
(
LoadBase
.
isReg
(
)
)
getBaseOperand
(
NewLoad
)
.
setIsKill
(
false
)
;
LLVM_DEBUG
(
NewLoad
->
dump
(
)
)
;
MachineInstr
*
StInst
=
StoreInst
;
if
(
StoreInst
->
getPrevNode
(
)
==
LoadInst
)
StInst
=
LoadInst
;
MachineInstr
*
NewStore
=
BuildMI
(
*
MBB
,
StInst
,
StInst
->
getDebugLoc
(
)
,
TII
->
get
(
NStoreOpcode
)
)
.
add
(
StoreBase
)
.
addImm
(
1
)
.
addReg
(
X86
::
NoRegister
)
.
addImm
(
StoreDisp
)
.
addReg
(
X86
::
NoRegister
)
.
addReg
(
Reg1
)
.
addMemOperand
(
MBB
->
getParent
(
)
->
getMachineMemOperand
(
SMMO
,
SMMOffset
,
Size
)
)
;
if
(
StoreBase
.
isReg
(
)
)
getBaseOperand
(
NewStore
)
.
setIsKill
(
false
)
;
MachineOperand
&
StoreSrcVReg
=
StoreInst
->
getOperand
(
X86
::
AddrNumOperands
)
;
assert
(
StoreSrcVReg
.
isReg
(
)
&&
"Expected virtual register"
)
;
NewStore
->
getOperand
(
X86
::
AddrNumOperands
)
.
setIsKill
(
StoreSrcVReg
.
isKill
(
)
)
;
LLVM_DEBUG
(
NewStore
->
dump
(
)
)
;
}
</s>


<s> static int ix86_vec_cost ( machine_mode mode , int cost ) { if ( ! VECTOR_MODE_P ( mode ) ) return cost ; if ( GET_MODE_BITSIZE ( mode ) == 128 && TARGET_SSE_SPLIT_REGS ) return cost * 2 ; if ( GET_MODE_BITSIZE ( mode ) > 128 && TARGET_AVX256_SPLIT_REGS ) return cost * GET_MODE_BITSIZE ( mode ) / 128 ; return cost ; } </s>

Return cost of vector operation in MODE given that scalar version has COST . If PARALLEL is true assume that CPU has more than one unit performing the operation .


<s>
AsmToken
LexToken
(
)
{
if
(
!
Lexer
)
{
SetError
(
SMLoc
(
)
,
"No MCAsmLexer installed"
)
;
return
AsmToken
(
AsmToken
::
Error
,
""
,
0
)
;
}
switch
(
AsmInfo
.
getAssemblerDialect
(
)
)
{
default
:
SetError
(
SMLoc
(
)
,
"Unhandled dialect"
)
;
return
AsmToken
(
AsmToken
::
Error
,
""
,
0
)
;
case
0
:
return
LexTokenUAL
(
)
;
}
}
</s>

LexToken - Read the next token and return its code .


<s> static void mips_emit_compare ( enum rtx_code * code , rtx * op0 , rtx * op1 , bool need_eq_ne_p ) { if ( GET_MODE_CLASS ( GET_MODE ( cmp_operands [ 0 ] ) ) == MODE_INT ) { if ( ! need_eq_ne_p && cmp_operands [ 1 ] == const0_rtx ) { * op0 = cmp_operands [ 0 ] ; * op1 = cmp_operands [ 1 ] ; } else if ( * code == EQ || * code == NE ) { if ( need_eq_ne_p ) { * op0 = mips_zero_if_equal ( cmp_operands [ 0 ] , cmp_operands [ 1 ] ) ; * op1 = const0_rtx ; } else { * op0 = cmp_operands [ 0 ] ; * op1 = force_reg ( GET_MODE ( * op0 ) , cmp_operands [ 1 ] ) ; } } else { bool invert = false ; * op0 = gen_reg_rtx ( GET_MODE ( cmp_operands [ 0 ] ) ) ; * op1 = const0_rtx ; mips_emit_int_relational ( * code , & invert , * op0 , cmp_operands [ 0 ] , cmp_operands [ 1 ] ) ; * code = ( invert ? EQ : NE ) ; } } else { enum rtx_code cmp_code ; switch ( * code ) { case NE : case LTGT : case ORDERED : cmp_code = reverse_condition_maybe_unordered ( * code ) ; * code = EQ ; break ; default : cmp_code = * code ; * code = NE ; break ; } * op0 = ( ISA_HAS_8CC ? gen_reg_rtx ( CCmode ) : gen_rtx_REG ( CCmode , FPSW_REGNUM ) ) ; * op1 = const0_rtx ; mips_emit_binary ( cmp_code , * op0 , cmp_operands [ 0 ] , cmp_operands [ 1 ] ) ; } } </s>

Convert a comparison into something that can be used in a branch or conditional move . On entry , * OP0 and * OP1 are the values being compared and * CODE is the code used to compare them . Update * CODE , * OP0 and * OP1 so that they describe the final comparison . If NEED_EQ_NE_P , then only EQ or NE comparisons against zero are possible , otherwise any standard branch condition can be used . The standard branch conditions are : - EQ or NE between two registers . - any comparison between a register and zero .


<s> unsigned MipsSEInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { unsigned Opc = MI . getOpcode ( ) ; if ( ( Opc == Mips :: LW ) || ( Opc == Mips :: LD ) || ( Opc == Mips :: LWC1 ) || ( Opc == Mips :: LDC1 ) || ( Opc == Mips :: LDC164 ) ) { if ( ( MI . getOperand ( 1 ) . isFI ( ) ) && ( MI . getOperand ( 2 ) . isImm ( ) ) && ( isZeroImm ( MI . getOperand ( 2 ) ) ) ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> static inline tree compound_expr ( tree t1 , tree t2 ) { return build2 ( COMPOUND_EXPR , void_type_node , t1 , t2 ) ; } </s>

Return the compound expression made of T1 and T2 .


<s> static void emit_unlikely_jump ( rtx insn ) { int very_unlikely = REG_BR_PROB_BASE / 100 - 1 ; rtx_insn * jump = emit_jump_insn ( insn ) ; add_int_reg_note ( jump , REG_BR_PROB , very_unlikely ) ; } </s>

Mark the previous jump instruction as unlikely .


<s>
const
char
*
ix86_output_ssemov
(
rtx_insn
*
insn
,
rtx
*
operands
)
{
machine_mode
mode
=
GET_MODE
(
operands
[
0
]
)
;
if
(
get_attr_type
(
insn
)
!=
TYPE_SSEMOV
||
mode
!=
GET_MODE
(
operands
[
1
]
)
)
gcc_unreachable
(
)
;
enum
attr_mode
insn_mode
=
get_attr_mode
(
insn
)
;
switch
(
insn_mode
)
{
case
MODE_XI
:
case
MODE_V8DF
:
case
MODE_V16SF
:
return
ix86_get_ssemov
(
operands
,
64
,
insn_mode
,
mode
)
;
case
MODE_OI
:
case
MODE_V4DF
:
case
MODE_V8SF
:
return
ix86_get_ssemov
(
operands
,
32
,
insn_mode
,
mode
)
;
case
MODE_TI
:
case
MODE_V2DF
:
case
MODE_V4SF
:
return
ix86_get_ssemov
(
operands
,
16
,
insn_mode
,
mode
)
;
case
MODE_DI
:
if
(
GENERAL_REG_P
(
operands
[
0
]
)
)
{
if
(
HAVE_AS_IX86_INTERUNIT_MOVQ
)
return
"%vmovq\t{%1, %q0|%q0, %1}"
;
else
return
"%vmovd\t{%1, %q0|%q0, %1}"
;
}
else
if
(
GENERAL_REG_P
(
operands
[
1
]
)
)
{
if
(
HAVE_AS_IX86_INTERUNIT_MOVQ
)
return
"%vmovq\t{%q1, %0|%0, %q1}"
;
else
return
"%vmovd\t{%q1, %0|%0, %q1}"
;
}
else
return
"%vmovq\t{%1, %0|%0, %1}"
;
case
MODE_SI
:
if
(
GENERAL_REG_P
(
operands
[
0
]
)
)
return
"%vmovd\t{%1, %k0|%k0, %1}"
;
else
if
(
GENERAL_REG_P
(
operands
[
1
]
)
)
return
"%vmovd\t{%k1, %0|%0, %k1}"
;
else
return
"%vmovd\t{%1, %0|%0, %1}"
;
case
MODE_HI
:
if
(
GENERAL_REG_P
(
operands
[
0
]
)
)
return
"vmovw\t{%1, %k0|%k0, %1}"
;
else
if
(
GENERAL_REG_P
(
operands
[
1
]
)
)
return
"vmovw\t{%k1, %0|%0, %k1}"
;
else
return
"vmovw\t{%1, %0|%0, %1}"
;
case
MODE_DF
:
if
(
TARGET_AVX
&&
REG_P
(
operands
[
0
]
)
&&
REG_P
(
operands
[
1
]
)
)
return
"vmovsd\t{%d1, %0|%0, %d1}"
;
else
return
"%vmovsd\t{%1, %0|%0, %1}"
;
case
MODE_SF
:
if
(
TARGET_AVX
&&
REG_P
(
operands
[
0
]
)
&&
REG_P
(
operands
[
1
]
)
)
return
"vmovss\t{%d1, %0|%0, %d1}"
;
else
return
"%vmovss\t{%1, %0|%0, %1}"
;
case
MODE_HF
:
if
(
REG_P
(
operands
[
0
]
)
&&
REG_P
(
operands
[
1
]
)
)
return
"vmovsh\t{%d1, %0|%0, %d1}"
;
else
return
"vmovsh\t{%1, %0|%0, %1}"
;
case
MODE_V1DF
:
gcc_assert
(
!
TARGET_AVX
)
;
return
"movlpd\t{%1, %0|%0, %1}"
;
case
MODE_V2SF
:
if
(
TARGET_AVX
&&
REG_P
(
operands
[
0
]
)
)
return
"vmovlps\t{%1, %d0|%d0, %1}"
;
else
return
"%vmovlps\t{%1, %0|%0, %1}"
;
default
:
gcc_unreachable
(
)
;
}
}
</s>

Return the template of the TYPE_SSEMOV instruction to move operands [ 1 ] into operands [ 0 ] .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addRequired < LegacyDivergenceAnalysis > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool SystemZRegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator SaveMBBI , MachineBasicBlock :: iterator & UseMBBI , const TargetRegisterClass * RC , unsigned Reg ) const { MachineFunction & MF = * MBB . getParent ( ) ; const SystemZInstrInfo & TII = * static_cast < const SystemZInstrInfo * > ( TM . getInstrInfo ( ) ) ; const SystemZFrameLowering * TFI = static_cast < const SystemZFrameLowering * > ( TM . getFrameLowering ( ) ) ; unsigned Base = getFrameRegister ( MF ) ; uint64_t Offset = TFI -> getEmergencySpillSlotOffset ( MF ) ; DebugLoc DL ; unsigned LoadOpcode , StoreOpcode ; TII . getLoadStoreOpcodes ( RC , LoadOpcode , StoreOpcode ) ; BuildMI ( MBB , SaveMBBI , DL , TII . get ( StoreOpcode ) ) . addReg ( Reg , RegState :: Kill ) . addReg ( Base ) . addImm ( Offset ) . addReg ( 0 ) ; BuildMI ( MBB , UseMBBI , DL , TII . get ( LoadOpcode ) , Reg ) . addReg ( Base ) . addImm ( Offset ) . addReg ( 0 ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .

SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ 0 0


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
]
=
{
{
"fixup_ppc_br24"
,
6
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_brcond14"
,
16
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_lo16"
,
16
,
16
,
0
}
,
{
"fixup_ppc_ha16"
,
16
,
16
,
0
}
,
{
"fixup_ppc_lo14"
,
16
,
14
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCCodeEmitter
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> const uint16_t * SystemZRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { SystemZ :: R6D , SystemZ :: R7D , SystemZ :: R8D , SystemZ :: R9D , SystemZ :: R10D , SystemZ :: R11D , SystemZ :: R12D , SystemZ :: R13D , SystemZ :: R14D , SystemZ :: R15D , SystemZ :: F8D , SystemZ :: F9D , SystemZ :: F10D , SystemZ :: F11D , SystemZ :: F12D , SystemZ :: F13D , SystemZ :: F14D , SystemZ :: F15D , 0 } ; return CalleeSavedRegs ; } </s>


<s> void X86PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; addPass ( createIndirectBrExpandPass ( ) ) ; const Triple & TT = TM -> getTargetTriple ( ) ; if ( TT . isOSWindows ( ) ) { if ( TT . getArch ( ) == Triple :: x86_64 ) { addPass ( createCFGuardDispatchPass ( ) ) ; } else { addPass ( createCFGuardCheckPass ( ) ) ; } } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> BitVector RISCVRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const RISCVFrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; for ( size_t Reg = 0 ; Reg < getNumRegs ( ) ; Reg ++ ) { if ( MF . getSubtarget < RISCVSubtarget > ( ) . isRegisterReservedByUser ( Reg ) ) markSuperRegs ( Reserved , Reg ) ; } markSuperRegs ( Reserved , RISCV :: X0 ) ; markSuperRegs ( Reserved , RISCV :: X2 ) ; markSuperRegs ( Reserved , RISCV :: X3 ) ; markSuperRegs ( Reserved , RISCV :: X4 ) ; auto & Subtarget = MF . getSubtarget < RISCVSubtarget > ( ) ; if ( Subtarget . hasStdExtV ( ) || TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , RISCV :: X8 ) ; if ( TFI -> hasBP ( MF ) ) markSuperRegs ( Reserved , RISCVABI :: getBPReg ( ) ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static rtx aarch64_move_pointer ( rtx pointer , poly_int64 amount ) { rtx next = plus_constant ( Pmode , XEXP ( pointer , 0 ) , amount ) ; return adjust_automodify_address ( pointer , GET_MODE ( pointer ) , next , amount ) ; } </s>

Return a new RTX holding the result of moving POINTER forward by AMOUNT bytes .


<s> void X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { bool reserveCallFrame = hasReservedCallFrame ( MF ) ; unsigned Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t InternalAmt = ( isDestroy || Amount ) ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { if ( Amount == 0 ) return ; unsigned StackAlign = getStackAlignment ( ) ; Amount = RoundUpToAlignment ( Amount , StackAlign ) ; Amount -= InternalAmt ; if ( Amount ) { int Offset = isDestroy ? Amount : - Amount ; BuildStackAdjustment ( MBB , I , DL , Offset , false ) ; } return ; } if ( isDestroy && InternalAmt ) { MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! std :: prev ( I ) -> isCall ( ) ) -- I ; BuildStackAdjustment ( MBB , I , DL , - InternalAmt , false ) ; } } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool SparcAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , O ) ; case 'f' : case 'r' : break ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s>
unsigned
X86InstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugInstr
(
)
)
continue
;
if
(
I
->
getOpcode
(
)
!=
X86
::
JMP_1
&&
X86
::
getCondFromBranchOpc
(
I
->
getOpcode
(
)
)
==
X86
::
COND_INVALID
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s>
MachineBasicBlock
::
iterator
ARMBaseInstrInfo
::
insertOutlinedCall
(
Module
&
M
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
&
It
,
MachineFunction
&
MF
,
const
outliner
::
Candidate
&
C
)
const
{
MachineInstrBuilder
MIB
;
MachineBasicBlock
::
iterator
CallPt
;
unsigned
Opc
;
bool
isThumb
=
Subtarget
.
isThumb
(
)
;
if
(
C
.
CallConstructionID
==
MachineOutlinerTailCall
)
{
Opc
=
isThumb
Subtarget
.
isTargetMachO
(
)
ARM
::
tTAILJMPd
:
ARM
::
tTAILJMPdND
:
ARM
::
TAILJMPd
;
MIB
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
Opc
)
)
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
;
if
(
isThumb
)
MIB
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
It
=
MBB
.
insert
(
It
,
MIB
)
;
return
It
;
}
Opc
=
isThumb
ARM
::
tBL
:
ARM
::
BL
;
MachineInstrBuilder
CallMIB
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
Opc
)
)
;
if
(
isThumb
)
CallMIB
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
CallMIB
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
;
if
(
C
.
CallConstructionID
==
MachineOutlinerNoLRSave
||
C
.
CallConstructionID
==
MachineOutlinerThunk
)
{
It
=
MBB
.
insert
(
It
,
CallMIB
)
;
return
It
;
}
if
(
C
.
CallConstructionID
==
MachineOutlinerRegSave
)
{
unsigned
Reg
=
findRegisterToSaveLRTo
(
C
)
;
assert
(
Reg
!=
0
&&
"No callee-saved register available?"
)
;
copyPhysReg
(
MBB
,
It
,
DebugLoc
(
)
,
Reg
,
ARM
::
LR
,
true
)
;
CallPt
=
MBB
.
insert
(
It
,
CallMIB
)
;
copyPhysReg
(
MBB
,
It
,
DebugLoc
(
)
,
ARM
::
LR
,
Reg
,
true
)
;
It
;
return
CallPt
;
}
saveLROnStack
(
MBB
,
It
)
;
CallPt
=
MBB
.
insert
(
It
,
CallMIB
)
;
restoreLRFromStack
(
MBB
,
It
)
;
It
;
return
CallPt
;
}
</s>

Insert a call to an outlined function into the program .

ARM
ARM
ARM::tTAILJMPd
ARM::tTAILJMPdND
ARM::TAILJMPd
ARMCC::AL
ARM::tBL
ARM::BL
ARMCC::AL
0
"No callee-saved register available?"
ARM::LR
ARM::LR


<s> void th_mempair_save_restore_regs ( rtx operands [ 4 ] , bool load_p , machine_mode mode ) { gcc_assert ( th_mempair_operands_p ( operands , load_p , mode ) ) ; th_mempair_order_operands ( operands , load_p , mode ) ; if ( load_p ) th_mempair_restore_regs ( operands ) ; else th_mempair_save_regs ( operands ) ; } </s>

Emit a mempair instruction to save/restore two registers to/from stack .


<s> bool X86AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : break ; case 'P' : printMemReference ( MI , OpNo , "no-rip" ) ; return false ; } } printMemReference ( MI , OpNo ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> static bool mips_vector_mode_supported_p ( enum machine_mode mode ) { switch ( mode ) { case V2SFmode : return TARGET_PAIRED_SINGLE_FLOAT ; case V2HImode : case V4QImode : return TARGET_DSP ; default : return false ; } } </s>

Target hook for vector_mode_supported_p .


<s>
void
R600SchedStrategy
::
releaseTopNode
(
SUnit
*
SU
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Top Releasing "
;
DAG
->
dumpNode
(
*
SU
)
)
;
}
</s>

SU has had all predecessor dependencies resolved .


<s> unsigned int get_ratio ( machine_mode mode ) { if ( TARGET_MIN_VLEN == 32 ) return mode_vtype_infos . ratio_for_min_vlen32 [ mode ] ; else return mode_vtype_infos . ratio_for_min_vlen64 [ mode ] ; } </s>


<s> bool PatmosSPBundling :: runOnMachineFunction ( MachineFunction & MF ) { PSPI = & getAnalysis < PatmosSinglePathInfo > ( ) ; PostDom = & getAnalysis < MachinePostDominatorTree > ( ) ; PMFI = MF . getInfo < PatmosMachineFunctionInfo > ( ) ; if ( PSPI -> isConverting ( MF ) && STC . enableBundling ( TM . getOptLevel ( ) ) ) { SPBlocks += MF . size ( ) ; doBundlingFunction ( PSPI -> getRootScope ( ) ) ; } return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> const char * KudeyarTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case KudeyarISD :: BR_CC_T : return "KudeyarISD::BR_CC_T" ; case KudeyarISD :: BR_CC_F : return "KudeyarISD::BR_CC_F" ; case KudeyarISD :: SELECT_CC_T : return "KudeyarISD::SELECT_CC_T" ; case KudeyarISD :: SELECT_CC_F : return "KudeyarISD::SELECT_CC_f" ; case KudeyarISD :: CMPEQ : return "KudeyarISD::CMPEQ" ; case KudeyarISD :: CMPGT : return "KudeyarISD::CMPGT" ; case KudeyarISD :: CMPLT : return "KudeyarISD::CMPLT" ; case KudeyarISD :: CMPGTU : return "KudeyarISD::CMPGTU" ; case KudeyarISD :: CMPLTU : return "KudeyarISD::CMPLTU" ; case KudeyarISD :: CALL : return "KudeyarISD::CALL" ; case KudeyarISD :: RET_FLAG : return "KudeyarISD::RET_FLAG" ; case KudeyarISD :: RETI_FLAG : return "KudeyarISD::RETI_FLAG" ; case KudeyarISD :: Wrapper : return "KudeyarISD::Wrapper" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> bool ARMBaseInstrInfo :: isFpMLxInstruction ( unsigned Opcode , unsigned & MulOpc , unsigned & AddSubOpc , bool & NegAcc , bool & HasLane ) const { DenseMap < unsigned , unsigned > :: const_iterator I = MLxEntryMap . find ( Opcode ) ; if ( I == MLxEntryMap . end ( ) ) return false ; const ARM_MLxEntry & Entry = ARM_MLxTable [ I -> second ] ; MulOpc = Entry . MulOpc ; AddSubOpc = Entry . AddSubOpc ; NegAcc = Entry . NegAcc ; HasLane = Entry . HasLane ; return true ; } </s>

isFpMLxInstruction - This version also returns the multiply opcode and the addition / subtraction opcode to expand to .


<s> static bool mips_expand_vselect ( rtx target , rtx op0 , const unsigned char * perm , unsigned nelt ) { rtx rperm [ MAX_VECT_LEN ] , x ; rtx_insn * insn ; unsigned i ; for ( i = 0 ; i < nelt ; ++ i ) rperm [ i ] = GEN_INT ( perm [ i ] ) ; x = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( nelt , rperm ) ) ; x = gen_rtx_VEC_SELECT ( GET_MODE ( target ) , op0 , x ) ; x = gen_rtx_SET ( target , x ) ; insn = emit_insn ( x ) ; if ( recog_memoized ( insn ) < 0 ) { remove_insn ( insn ) ; return false ; } return true ; } </s>

Construct ( set target ( vec_select op0 ( parallel perm ) ) ) and return true if that 's a valid instruction in the active ISA .


<s> bool ix86_secondary_memory_needed ( enum reg_class class1 , enum reg_class class2 , machine_mode mode , int strict ) { return inline_secondary_memory_needed ( class1 , class2 , mode , strict ) ; } </s>

If we are copying between general and FP registers , we need a memory location . The same is true for SSE and MMX registers . The macro ca n't work reliably when one of the CLASSES is class containing registers from multiple units ( SSE , MMX , integer ) . We avoid this by never combining those units in single alternative in the machine description . Ensure that this constraint holds to avoid unexpected surprises . When STRICT is false , we are being called from REGISTER_MOVE_COST , so do not enforce these sanity checks .


<s> void X86IntelInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( TSFlags & X86II :: LOCK ) OS << "\tlock\n" ; printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAnyX86InstComments ( MI , * CommentStream , getRegisterName ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> const std :: string & THMToTHMStub :: name ( ) const { return m_Name ; } </s>

Gets the name of the pass we are mixed into .


<s> static bool xtensa_can_use_doloop_p ( const widest_int & , const widest_int & , unsigned int loop_depth , bool entered_at_top ) { if ( loop_depth > 1 || ! entered_at_top ) return false ; return true ; } </s>


<s> rtx mips_function_value ( tree valtype , tree func ATTRIBUTE_UNUSED , enum machine_mode mode ) { if ( valtype ) { tree fields [ 2 ] ; int unsignedp ; mode = TYPE_MODE ( valtype ) ; unsignedp = TYPE_UNSIGNED ( valtype ) ; mode = promote_mode ( valtype , mode , & unsignedp , 1 ) ; switch ( mips_fpr_return_fields ( valtype , fields ) ) { case 1 : return gen_rtx_REG ( mode , FP_RETURN ) ; case 2 : return mips_return_fpr_pair ( mode , TYPE_MODE ( TREE_TYPE ( fields [ 0 ] ) ) , int_byte_position ( fields [ 0 ] ) , TYPE_MODE ( TREE_TYPE ( fields [ 1 ] ) ) , int_byte_position ( fields [ 1 ] ) ) ; } if ( mips_return_in_msb ( valtype ) ) { HOST_WIDE_INT size = int_size_in_bytes ( valtype ) ; if ( size % UNITS_PER_WORD != 0 ) { size += UNITS_PER_WORD - size % UNITS_PER_WORD ; mode = mode_for_size ( size * BITS_PER_UNIT , MODE_INT , 0 ) ; } } if ( mips_abi != ABI_EABI && ! FLOAT_TYPE_P ( valtype ) ) return gen_rtx_REG ( mode , GP_RETURN ) ; } if ( ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT ) && GET_MODE_SIZE ( mode ) <= UNITS_PER_HWFPVALUE ) return gen_rtx_REG ( mode , FP_RETURN ) ; if ( mode == TFmode ) return mips_return_fpr_pair ( mode , DImode , 0 , DImode , GET_MODE_SIZE ( mode ) / 2 ) ; if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT && GET_MODE_SIZE ( mode ) <= UNITS_PER_HWFPVALUE * 2 ) return mips_return_fpr_pair ( mode , GET_MODE_INNER ( mode ) , 0 , GET_MODE_INNER ( mode ) , GET_MODE_SIZE ( mode ) / 2 ) ; return gen_rtx_REG ( mode , GP_RETURN ) ; } </s>

Implement FUNCTION_VALUE and LIBCALL_VALUE . For normal calls , VALTYPE is the return type and MODE is VOIDmode . For libcalls , VALTYPE is null and MODE is the mode of the return value .


"Only one kind of pointer on WebAssembly"

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> const AMDGPURegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


"fixed register %s used to pass parameter to function"

Update the summarizer variable CUM to advance past an argument in the argument list .


<s> bool isImm ( ) const override { return Kind == k_Immediate ; } </s>


<s>
bool
runOnMachineFunction
(
MachineFunction
&
MF
)
override
{
Subtarget
=
&
MF
.
getSubtarget
<
X86Subtarget
>
(
)
;
IndirectTlsSegRefs
=
MF
.
getFunction
(
)
.
hasFnAttribute
(
"indirect-tls-seg-refs"
)
;
OptForMinSize
=
MF
.
getFunction
(
)
.
hasMinSize
(
)
;
assert
(
(
!
OptForMinSize
||
MF
.
getFunction
(
)
.
hasOptSize
(
)
)
&&
"OptForMinSize implies OptForSize"
)
;
SelectionDAGISel
::
runOnMachineFunction
(
MF
)
;
return
true
;
}
</s>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { AArch64FI = MF . getInfo < AArch64FunctionInfo > ( ) ; STI = & MF . getSubtarget < AArch64Subtarget > ( ) ; SetupMachineFunction ( MF ) ; if ( STI -> isTargetCOFF ( ) ) { bool Internal = MF . getFunction ( ) . hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> emitCOFFSymbolStorageClass ( Scl ) ; OutStreamer -> emitCOFFSymbolType ( Type ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } emitFunctionBody ( ) ; emitXRayTable ( ) ; return false ; } </s>


<s> Instruction * RISCVTargetLowering :: emitLeadingFence ( IRBuilderBase & Builder , Instruction * Inst , AtomicOrdering Ord ) const { if ( isa < LoadInst > ( Inst ) && Ord == AtomicOrdering :: SequentiallyConsistent ) return Builder . CreateFence ( Ord ) ; if ( isa < StoreInst > ( Inst ) && isReleaseOrStronger ( Ord ) ) return Builder . CreateFence ( AtomicOrdering :: Release ) ; return nullptr ; } </s>


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> bool BPFInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { if ( MI . getOpcode ( ) == BPF :: MEMCPY ) { expandMEMCPY ( MI ) ; return true ; } return false ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> StringRef getPassName ( ) const override { return AARCH64_CONDBR_TUNING_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> static unsigned getReg ( const void * D , unsigned RC , unsigned RegNo ) { const XCoreDisassembler * Dis = static_cast < const XCoreDisassembler * > ( D ) ; return * ( Dis -> getRegInfo ( ) -> getRegClass ( RC ) . begin ( ) + RegNo ) ; } </s>

Returns the register associated with this edge .


<s> bool X86TargetLowering :: shouldConvertPhiType ( Type * From , Type * To ) const { if ( ! Subtarget . is64Bit ( ) ) return false ; return TargetLowering :: shouldConvertPhiType ( From , To ) ; } </s>

Given a set in interconnected phis of type 'From ' that are loaded/stored or bitcast to type 'To ' , return true if the set should be converted to 'To ' .


<s> static void fr30_function_arg_advance ( cumulative_args_t cum , machine_mode mode , const_tree type , bool named ) { * get_cumulative_args ( cum ) += named * fr30_num_arg_regs ( mode , type ) ; } </s>

A C statement ( sans semicolon ) to update the summarizer variable CUM to advance past an argument in the argument list . The values MODE , TYPE and NAMED describe that argument . Once this is done , the variable CUM is suitable for analyzing the * following * argument with ` FUNCTION_ARG ' , etc . This macro need not do anything if the argument in question was passed on the stack . The compiler knows how to track the amount of stack space used for arguments without any special help .


<s> static void m68k_coff_asm_named_section ( const char * name , unsigned int flags , tree decl ATTRIBUTE_UNUSED ) { char flagchar ; if ( flags & SECTION_WRITE ) flagchar = 'd' ; else flagchar = 'x' ; fprintf ( asm_out_file , "\t.section\t%s,\"%c\"\n" , name , flagchar ) ; } </s>

Output assembly to switch to section NAME with attribute FLAGS .


<s> static bool csky_rtx_costs ( rtx x , machine_mode mode ATTRIBUTE_UNUSED , int outer_code , int opno ATTRIBUTE_UNUSED , int * total , bool speed ) { int code = GET_CODE ( x ) ; if ( CSKY_TARGET_ARCH ( CK802 ) || CSKY_TARGET_ARCH ( CK801 ) ) return ck802_ck801_rtx_costs ( x , code , outer_code , total , speed ) ; else if ( CSKY_TARGET_ARCH ( CK803 ) ) return ck803_rtx_costs ( x , code , outer_code , total , speed ) ; else if ( CSKY_TARGET_ARCH ( CK807 ) || CSKY_TARGET_ARCH ( CK810 ) ) return ck807_ck810_rtx_costs ( x , code , outer_code , total , speed ) ; else if ( CSKY_TARGET_ARCH ( CK860 ) ) return ck860_rtx_costs ( x , code , mode , outer_code , total , speed ) ; else gcc_unreachable ( ) ; } </s>

Implement TARGET_RTX_COSTS , to compute a ( partial ) cost for rtx X . Return true if the complete cost has been computed , and false if subexpressions should be scanned . In either case , * TOTAL contains the cost result .


<s> bool legitimate_constant_p ( rtx x ) { rtx inner ; switch ( GET_CODE ( x ) ) { case SYMBOL_REF : if ( SYMBOL_REF_TLS_MODEL ( x ) ) return false ; break ; case CONST : inner = XEXP ( x , 0 ) ; if ( GET_CODE ( inner ) == PLUS && SPARC_SYMBOL_REF_TLS_P ( XEXP ( inner , 0 ) ) ) return false ; break ; case CONST_DOUBLE : if ( GET_MODE ( x ) == VOIDmode ) return true ; if ( TARGET_VIS && SCALAR_FLOAT_MODE_P ( GET_MODE ( x ) ) && const_zero_operand ( x , GET_MODE ( x ) ) ) return true ; return false ; case CONST_VECTOR : if ( TARGET_VIS && const_zero_operand ( x , GET_MODE ( x ) ) ) return true ; return false ; default : break ; } return true ; } </s>

Nonzero if the constant value X is a legitimate general operand . It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE .


<s> const uint32_t * ARCRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return CSR_ARC_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void riscv_run_selftests ( void ) { run_poly_int_selftests ( ) ; run_const_vector_selftests ( ) ; run_broadcast_selftests ( ) ; } </s>


<s> void ix86_expand_convert_uns_didf_sse ( rtx target , rtx input ) { REAL_VALUE_TYPE bias_lo_rvt , bias_hi_rvt ; rtx int_xmm , fp_xmm ; rtx biases , exponents ; rtx x ; int_xmm = gen_reg_rtx ( V4SImode ) ; if ( TARGET_INTER_UNIT_MOVES_TO_VEC ) emit_insn ( gen_movdi_to_sse ( int_xmm , input ) ) ; else if ( TARGET_SSE_SPLIT_REGS ) { emit_clobber ( int_xmm ) ; emit_move_insn ( gen_lowpart ( DImode , int_xmm ) , input ) ; } else { x = gen_reg_rtx ( V2DImode ) ; ix86_expand_vector_init_one_nonzero ( false , V2DImode , x , input , 0 ) ; emit_move_insn ( int_xmm , gen_lowpart ( V4SImode , x ) ) ; } x = gen_rtx_CONST_VECTOR ( V4SImode , gen_rtvec ( 4 , GEN_INT ( 0x43300000UL ) , GEN_INT ( 0x45300000UL ) , const0_rtx , const0_rtx ) ) ; exponents = validize_mem ( force_const_mem ( V4SImode , x ) ) ; emit_insn ( gen_vec_interleave_lowv4si ( int_xmm , int_xmm , exponents ) ) ; fp_xmm = copy_to_mode_reg ( V2DFmode , gen_lowpart ( V2DFmode , int_xmm ) ) ; real_ldexp ( & bias_lo_rvt , & dconst1 , 52 ) ; real_ldexp ( & bias_hi_rvt , & dconst1 , 84 ) ; biases = const_double_from_real_value ( bias_lo_rvt , DFmode ) ; x = const_double_from_real_value ( bias_hi_rvt , DFmode ) ; biases = gen_rtx_CONST_VECTOR ( V2DFmode , gen_rtvec ( 2 , biases , x ) ) ; biases = validize_mem ( force_const_mem ( V2DFmode , biases ) ) ; emit_insn ( gen_subv2df3 ( fp_xmm , fp_xmm , biases ) ) ; if ( TARGET_SSE3 ) emit_insn ( gen_sse3_haddv2df3 ( fp_xmm , fp_xmm , fp_xmm ) ) ; else { x = copy_to_mode_reg ( V2DFmode , fp_xmm ) ; emit_insn ( gen_vec_interleave_highv2df ( fp_xmm , fp_xmm , fp_xmm ) ) ; emit_insn ( gen_addv2df3 ( fp_xmm , fp_xmm , x ) ) ; } ix86_expand_vector_extract ( false , target , fp_xmm , 0 ) ; } </s>

Convert an unsigned DImode value into a DFmode , using only SSE . Expects the 64-bit DImode to be supplied in a pair of integral registers . Requires SSE2 ; will use SSE3 if available . For x86_32 , -mfpmath=sse , ! optimize_size only .


<s> SDValue ARCTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { return { } ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> int fpuv3_const_double_rtx ( rtx x ) { REAL_VALUE_TYPE r , m ; r = * CONST_DOUBLE_REAL_VALUE ( x ) ; if ( REAL_VALUE_ISINF ( r ) || REAL_VALUE_ISNAN ( r ) || REAL_VALUE_MINUS_ZERO ( r ) || r . cl == rvc_zero ) return 0 ; int exponent ; r = real_value_abs ( & r ) ; exponent = REAL_EXP ( & r ) ; bool fail ; unsigned HOST_WIDE_INT mantissa , mant_hi ; unsigned HOST_WIDE_INT mask ; int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1 ; real_ldexp ( & m , & r , point_pos - exponent ) ; wide_int w = real_to_integer ( & m , & fail , HOST_BITS_PER_WIDE_INT * 2 ) ; mantissa = w . elt ( 0 ) ; mant_hi = w . elt ( 1 ) ; exponent -= 1 ; if ( ! IN_RANGE ( exponent , - 4 , 11 ) ) return 0 ; if ( mantissa != 0 ) return 0 ; point_pos -= HOST_BITS_PER_WIDE_INT ; mantissa = mant_hi ; mask = ( ( unsigned HOST_WIDE_INT ) 1 << ( point_pos - 9 ) ) - 1 ; if ( ( mantissa & mask ) != 0 ) return 0 ; return 1 ; } </s>

Check if a const_double can be used by a VFP fmovi instruction .


<s> SDValue SystemZTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , unsigned CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_SystemZ ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) . getValue ( 1 ) ; SDValue RetValue = Chain . getValue ( 0 ) ; InFlag = Chain . getValue ( 2 ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) RetValue = DAG . getNode ( ISD :: AssertSext , dl , VA . getLocVT ( ) , RetValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) RetValue = DAG . getNode ( ISD :: AssertZext , dl , VA . getLocVT ( ) , RetValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) RetValue = DAG . getNode ( ISD :: TRUNCATE , dl , VA . getValVT ( ) , RetValue ) ; InVals . push_back ( RetValue ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
KindTy
::
Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
KindTy
::
Register
:
OS
<<
"<register x"
;
OS
<<
getReg
(
)
<<
">"
;
break
;
case
KindTy
::
Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
case
KindTy
::
SystemRegister
:
OS
<<
"<sysreg: "
<<
getSysReg
(
)
<<
'>'
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

RISCV
"<register x"
">"
"'"
"'"
"<sysreg: "


<s> void PPCRegisterInfo :: lowerCRSpilling ( MachineBasicBlock :: iterator II , unsigned FrameIndex , int SPAdj , RegScavenger * RS ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; const TargetRegisterClass * G8RC = & PPC :: G8RCRegClass ; const TargetRegisterClass * GPRC = & PPC :: GPRCRegClass ; const TargetRegisterClass * RC = Subtarget . isPPC64 ( ) ? G8RC : GPRC ; unsigned Reg = findScratchRegister ( II , RS , RC , SPAdj ) ; if ( ! MI . getOperand ( 0 ) . isKill ( ) ) BuildMI ( MBB , II , dl , TII . get ( PPC :: MFCR ) , Reg ) ; else BuildMI ( MBB , II , dl , TII . get ( PPC :: MFCR ) , Reg ) . addReg ( MI . getOperand ( 0 ) . getReg ( ) , RegState :: ImplicitKill ) ; unsigned SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; if ( SrcReg != PPC :: CR0 ) BuildMI ( MBB , II , dl , TII . get ( PPC :: RLWINM ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( PPCRegisterInfo :: getRegisterNumbering ( SrcReg ) * 4 ) . addImm ( 0 ) . addImm ( 31 ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( PPC :: STW ) ) . addReg ( Reg , getKillRegState ( MI . getOperand ( 1 ) . getImm ( ) ) ) , FrameIndex ) ; MBB . erase ( II ) ; } </s>

lowerCRSpilling - Generate the code for spilling a CR register .


<s> static bool rs6000_discover_homogeneous_aggregate ( machine_mode mode , const_tree type , machine_mode * elt_mode , int * n_elts ) { if ( DEFAULT_ABI == ABI_ELFv2 && type && AGGREGATE_TYPE_P ( type ) ) { machine_mode field_mode = VOIDmode ; int field_count = rs6000_aggregate_candidate ( type , & field_mode ) ; if ( field_count > 0 ) { int n_regs = ( SCALAR_FLOAT_MODE_P ( field_mode ) ? ( GET_MODE_SIZE ( field_mode ) + 7 ) >> 3 : 1 ) ; if ( field_count * n_regs <= AGGR_ARG_NUM_REG ) { if ( elt_mode ) * elt_mode = field_mode ; if ( n_elts ) * n_elts = field_count ; return true ; } } } if ( elt_mode ) * elt_mode = mode ; if ( n_elts ) * n_elts = 1 ; return false ; } </s>

If an argument , whose type is described by TYPE and MODE , is a homogeneous float or vector aggregate that shall be passed in FP/vector registers according to the ELFv2 ABI , return the homogeneous element mode in * ELT_MODE and the number of elements in * N_ELTS , and return TRUE . Otherwise , set * ELT_MODE to MODE and * N_ELTS to 1 , and return FALSE .


<s> bool AMDGPUAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ! AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , O ) ) return false ; if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { case 'r' : break ; default : return true ; } } const MachineOperand & MO = MI -> getOperand ( OpNo ) ; if ( MO . isReg ( ) ) { AMDGPUInstPrinter :: printRegOperand ( MO . getReg ( ) , O , * MF -> getSubtarget ( ) . getRegisterInfo ( ) ) ; return false ; } return true ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


"selector must be an integer constant in the range 0..%wi"

Return the integer constant in ARG . Constrain it to be in the range of the subparts of VEC_TYPE ; issue an error if not .


<s> bool RISCVFrameLowering :: canUseAsEpilogue ( const MachineBasicBlock & MBB ) const { const MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ; const auto * RVFI = MF -> getInfo < RISCVMachineFunctionInfo > ( ) ; if ( ! RVFI -> useSaveRestoreLibCalls ( * MF ) ) return true ; if ( MBB . succ_size ( ) > 1 ) return false ; MachineBasicBlock * SuccMBB = MBB . succ_empty ( ) ? TmpMBB -> getFallThrough ( ) : * MBB . succ_begin ( ) ; if ( ! SuccMBB ) return true ; return SuccMBB -> isReturnBlock ( ) && SuccMBB -> size ( ) == 1 ; } </s>

Check whether or not the given MBB can be used as a epilogue for the target .


<s>
SDValue
AGCTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
report_fatal_error
(
"unimplemented operation"
)
;
case
ISD
::
MUL
:
return
LowerMUL
(
Op
,
DAG
)
;
case
ISD
::
SDIV
:
return
LowerSDIV
(
Op
,
DAG
)
;
case
ISD
::
SREM
:
return
LowerSREM
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

AGC
AGC
"unimplemented operation"
ISD::MUL
ISD::SDIV
ISD::SREM


<s> static bool alg_usable_p ( enum stringop_alg alg , bool memset ) { if ( alg == no_stringop ) return false ; if ( alg == vector_loop ) return TARGET_SSE || TARGET_AVX ; if ( alg == rep_prefix_1_byte || alg == rep_prefix_4_byte || alg == rep_prefix_8_byte ) return ! ( fixed_regs [ CX_REG ] || fixed_regs [ DI_REG ] || ( memset ? fixed_regs [ AX_REG ] : fixed_regs [ SI_REG ] ) ) ; return true ; } </s>

Return true if ALG can be used in current context . Assume we expand memset if MEMSET is true .


<s> bool arc_ccfsm_cond_exec_p ( void ) { return ( cfun -> machine -> prescan_initialized && ARC_CCFSM_COND_EXEC_P ( & arc_ccfsm_current ) ) ; } </s>

During insn output , indicate if the current insn is predicated .


<s> unsigned SIRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; unsigned Occupancy = ST . getOccupancyWithLocalMemSize ( MFI -> getLDSSize ( ) , MF . getFunction ( ) ) ; switch ( RC -> getID ( ) ) { default : return AMDGPUGenRegisterInfo :: getRegPressureLimit ( RC , MF ) ; case AMDGPU :: VGPR_32RegClassID : case AMDGPU :: VGPR_LO16RegClassID : case AMDGPU :: VGPR_HI16RegClassID : return std :: min ( ST . getMaxNumVGPRs ( Occupancy ) , ST . getMaxNumVGPRs ( MF ) ) ; case AMDGPU :: SGPR_32RegClassID : case AMDGPU :: SGPR_LO16RegClassID : return std :: min ( ST . getMaxNumSGPRs ( Occupancy , true ) , ST . getMaxNumSGPRs ( MF ) ) ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> static void add_to_reg ( rtx reg , HOST_WIDE_INT value , int frame , int epilogue_p ) { if ( value == 0 ) return ; if ( value > 120 || value < - 120 ) { rtx tmpreg ; rtx tmpreg2 ; rtx_insn * insn ; tmpreg2 = NULL_RTX ; if ( epilogue_p >= 0 ) tmpreg = gen_rtx_REG ( SImode , REG_P1 ) ; else { int i ; for ( i = REG_P0 ; i <= REG_P5 ; i ++ ) if ( ( df_regs_ever_live_p ( i ) && ! call_used_or_fixed_reg_p ( i ) ) || ( ! TARGET_FDPIC && i == PIC_OFFSET_TABLE_REGNUM && ( crtl -> uses_pic_offset_table || ( TARGET_ID_SHARED_LIBRARY && ! crtl -> is_leaf ) ) ) ) break ; if ( i <= REG_P5 ) tmpreg = gen_rtx_REG ( SImode , i ) ; else { tmpreg = gen_rtx_REG ( SImode , REG_P1 ) ; tmpreg2 = gen_rtx_REG ( SImode , REG_I0 ) ; emit_move_insn ( tmpreg2 , tmpreg ) ; } } if ( frame ) frame_related_constant_load ( tmpreg , value , TRUE ) ; else insn = emit_move_insn ( tmpreg , GEN_INT ( value ) ) ; insn = emit_insn ( gen_addsi3 ( reg , reg , tmpreg ) ) ; if ( frame ) RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( tmpreg2 != NULL_RTX ) emit_move_insn ( tmpreg , tmpreg2 ) ; } else do { int size = value ; rtx_insn * insn ; if ( size > 60 ) size = 60 ; else if ( size < - 60 ) size = - 60 ; insn = emit_insn ( gen_addsi3 ( reg , reg , GEN_INT ( size ) ) ) ; if ( frame ) RTX_FRAME_RELATED_P ( insn ) = 1 ; value -= size ; } while ( value != 0 ) ; } </s>

Generate efficient code to add a value to a P register . Set RTX_FRAME_RELATED_P on the generated insns if FRAME is nonzero . EPILOGUE_P is zero if this function is called for prologue , otherwise it 's nonzero . And it 's less than zero if this is for sibcall epilogue .


<s> static bool rs6000_scalar_mode_supported_p ( machine_mode mode ) { if ( TARGET_32BIT && mode == TImode ) return false ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) return default_decimal_float_supported_p ( ) ; else if ( TARGET_FLOAT128 && ( mode == KFmode || mode == IFmode ) ) return true ; else return default_scalar_mode_supported_p ( mode ) ; } </s>

Target hook for scalar_mode_supported_p .


<s> bool MipsSEInstrInfo :: isCopyInstr ( const MachineInstr & MI , MachineOperand & Src , MachineOperand & Dest ) const { bool isDSPControlWrite = false ; if ( isReadOrWritToDSPReg ( MI , isDSPControlWrite ) ) { if ( ! MI . getOperand ( 1 ) . isImm ( ) || ! ( MI . getOperand ( 1 ) . getImm ( ) == ( 1 << 4 ) ) ) return false ; else if ( isDSPControlWrite ) { Src = MI . getOperand ( 0 ) ; Dest = MI . getOperand ( 2 ) ; } else { Dest = MI . getOperand ( 0 ) ; Src = MI . getOperand ( 2 ) ; } return true ; } else if ( MI . isMoveReg ( ) || isORCopyInst ( MI ) ) { Dest = MI . getOperand ( 0 ) ; Src = MI . getOperand ( 1 ) ; return true ; } return false ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


<s> const uint32_t * PPCRegisterInfo :: getNoPreservedMask ( ) const { return CSR_NoRegs_RegMask ; } </s>

Return a register mask that clobbers everything .


<s> poly_int64 xstormy16_push_rounding ( poly_int64 bytes ) { return ( bytes + 1 ) & ~ 1 ; } </s>


<s> static reg_class_t mips_preferred_reload_class ( rtx x , reg_class_t rclass ) { if ( mips_dangerous_for_la25_p ( x ) && reg_class_subset_p ( LEA_REGS , rclass ) ) return LEA_REGS ; if ( reg_class_subset_p ( FP_REGS , rclass ) && mips_mode_ok_for_mov_fmt_p ( GET_MODE ( x ) ) ) return FP_REGS ; if ( reg_class_subset_p ( GR_REGS , rclass ) ) rclass = GR_REGS ; if ( TARGET_MIPS16 && reg_class_subset_p ( M16_REGS , rclass ) ) rclass = M16_REGS ; return rclass ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"StackPU2 Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
unsigned
getStackAddress
(
uint64_t
Size
,
int64_t
Offset
,
MachinePointerInfo
&
MPO
)
override
{
assert
(
(
Size
==
1
||
Size
==
2
||
Size
==
4
)
&&
"Unsupported size"
)
;
auto
&
MFI
=
MIRBuilder
.
getMF
(
)
.
getFrameInfo
(
)
;
int
FI
=
MFI
.
CreateFixedObject
(
Size
,
Offset
,
true
)
;
MPO
=
MachinePointerInfo
::
getFixedStack
(
MIRBuilder
.
getMF
(
)
,
FI
)
;
unsigned
AddrReg
=
MRI
.
createGenericVirtualRegister
(
LLT
::
pointer
(
MPO
.
getAddrSpace
(
)
,
32
)
)
;
MIRBuilder
.
buildFrameIndex
(
AddrReg
,
FI
)
;
return
AddrReg
;
}
</s>

Materialize a VReg containing the address of the specified stack-based object .


<s> static bool arm_sched_can_speculate_insn ( rtx_insn * insn ) { switch ( get_attr_type ( insn ) ) { case TYPE_SDIV : case TYPE_UDIV : case TYPE_FDIVS : case TYPE_FDIVD : case TYPE_FSQRTS : case TYPE_FSQRTD : case TYPE_NEON_FP_SQRT_S : case TYPE_NEON_FP_SQRT_D : case TYPE_NEON_FP_SQRT_S_Q : case TYPE_NEON_FP_SQRT_D_Q : case TYPE_NEON_FP_DIV_S : case TYPE_NEON_FP_DIV_D : case TYPE_NEON_FP_DIV_S_Q : case TYPE_NEON_FP_DIV_D_Q : return false ; default : return true ; } } </s>

Implement TARGET_SCHED_CAN_SPECULATE_INSN . Return true if INSN can be scheduled for speculative execution . Reject the long-running division and square-root instructions .


<s> void RISCVInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & O ) { bool Res = false ; const MCInst * NewMI = MI ; MCInst UncompressedMI ; if ( PrintAliases && ! NoAliases ) Res = uncompressInst ( UncompressedMI , * MI , MRI , STI ) ; if ( Res ) NewMI = const_cast < MCInst * > ( & UncompressedMI ) ; if ( ! PrintAliases || NoAliases || ! printAliasInstr ( NewMI , Address , STI , O ) ) printInstruction ( NewMI , Address , STI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> unsigned LM32RegisterInfo :: getRARegister ( ) const { return LM32 :: RRA ; } </s>

This method should return the register where the return address can be found .


<s> static bool mcore_reg_ok_for_base_p ( const_rtx reg , bool strict_p ) { if ( strict_p ) return REGNO_OK_FOR_BASE_P ( REGNO ( reg ) ) ; else return ( REGNO ( reg ) <= 16 || ! HARD_REGISTER_P ( reg ) ) ; } </s>

Helper function for ` mcore_legitimate_address_p ' .


<s> Register ( llvm :: Register R , unsigned S ) : Reg ( R ) , Sub ( S ) { } </s>


<s> bool ix86_expand_int_addcc ( rtx operands [ ] ) { enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; rtx flags ; rtx ( * insn ) ( rtx , rtx , rtx , rtx , rtx ) ; rtx compare_op ; rtx val = const0_rtx ; bool fpcmp = false ; machine_mode mode ; rtx op0 = XEXP ( operands [ 1 ] , 0 ) ; rtx op1 = XEXP ( operands [ 1 ] , 1 ) ; if ( operands [ 3 ] != const1_rtx && operands [ 3 ] != constm1_rtx ) return false ; if ( ! ix86_expand_carry_flag_compare ( code , op0 , op1 , & compare_op ) ) return false ; code = GET_CODE ( compare_op ) ; flags = XEXP ( compare_op , 0 ) ; if ( GET_MODE ( flags ) == CCFPmode ) { fpcmp = true ; code = ix86_fp_compare_code_to_integer ( code ) ; } if ( code != LTU ) { val = constm1_rtx ; if ( fpcmp ) PUT_CODE ( compare_op , reverse_condition_maybe_unordered ( GET_CODE ( compare_op ) ) ) ; else PUT_CODE ( compare_op , reverse_condition ( GET_CODE ( compare_op ) ) ) ; } mode = GET_MODE ( operands [ 0 ] ) ; if ( ( code == LTU ) == ( operands [ 3 ] == constm1_rtx ) ) { switch ( mode ) { case E_QImode : insn = gen_subqi3_carry ; break ; case E_HImode : insn = gen_subhi3_carry ; break ; case E_SImode : insn = gen_subsi3_carry ; break ; case E_DImode : insn = gen_subdi3_carry ; break ; default : gcc_unreachable ( ) ; } } else { switch ( mode ) { case E_QImode : insn = gen_addqi3_carry ; break ; case E_HImode : insn = gen_addhi3_carry ; break ; case E_SImode : insn = gen_addsi3_carry ; break ; case E_DImode : insn = gen_adddi3_carry ; break ; default : gcc_unreachable ( ) ; } } emit_insn ( insn ( operands [ 0 ] , operands [ 2 ] , val , flags , compare_op ) ) ; return true ; } </s>

Expand conditional increment or decrement using adb/sbb instructions . The default case using setcc followed by the conditional move can be done by generic code .


<s>
void
BT
::
run
(
)
{
reset
(
)
;
assert
(
FlowQ
.
empty
(
)
)
;
typedef
GraphTraits
<
const
MachineFunction
*
>
MachineFlowGraphTraits
;
const
MachineBasicBlock
*
Entry
=
MachineFlowGraphTraits
::
getEntryNode
(
&
MF
)
;
unsigned
MaxBN
=
0
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
assert
(
I
->
getNumber
(
)
>=
0
&&
"Disconnected block"
)
;
unsigned
BN
=
I
->
getNumber
(
)
;
if
(
BN
>
MaxBN
)
MaxBN
=
BN
;
}
BitVector
BlockScanned
(
MaxBN
+
1
)
;
int
EntryN
=
Entry
->
getNumber
(
)
;
FlowQ
.
push
(
CFGEdge
(
1
,
EntryN
)
)
;
while
(
!
FlowQ
.
empty
(
)
)
{
CFGEdge
Edge
=
FlowQ
.
front
(
)
;
FlowQ
.
pop
(
)
;
if
(
EdgeExec
.
count
(
Edge
)
)
continue
;
EdgeExec
.
insert
(
Edge
)
;
const
MachineBasicBlock
&
B
=
*
MF
.
getBlockNumbered
(
Edge
.
second
)
;
MachineBasicBlock
::
const_iterator
It
=
B
.
begin
(
)
,
End
=
B
.
end
(
)
;
while
(
It
!=
End
&&
It
->
isPHI
(
)
)
{
const
MachineInstr
&
PI
=
*
It
++
;
InstrExec
.
insert
(
&
PI
)
;
visitPHI
(
PI
)
;
}
if
(
BlockScanned
[
Edge
.
second
]
)
continue
;
BlockScanned
[
Edge
.
second
]
=
true
;
while
(
It
!=
End
&&
!
It
->
isBranch
(
)
)
{
const
MachineInstr
&
MI
=
*
It
++
;
InstrExec
.
insert
(
&
MI
)
;
visitNonBranch
(
MI
)
;
}
if
(
It
==
End
)
{
MachineFunction
::
const_iterator
BIt
=
B
.
getIterator
(
)
;
MachineFunction
::
const_iterator
Next
=
std
::
next
(
BIt
)
;
if
(
Next
!=
MF
.
end
(
)
&&
B
.
isSuccessor
(
&
*
Next
)
)
{
int
ThisN
=
B
.
getNumber
(
)
;
int
NextN
=
Next
->
getNumber
(
)
;
FlowQ
.
push
(
CFGEdge
(
ThisN
,
NextN
)
)
;
}
}
else
{
visitBranchesFrom
(
*
It
)
;
}
}
if
(
Trace
)
print_cells
(
dbgs
(
)
<<
"Cells after propagation:\n"
)
;
}
</s>

Run the analysis pass over a function and produce a dominator tree .


<s> std :: pair < unsigned , unsigned > AMDGPUSubtarget :: getWavesPerEU ( const Function & F ) const { std :: pair < unsigned , unsigned > Default ( 1 , getMaxWavesPerEU ( ) ) ; std :: pair < unsigned , unsigned > FlatWorkGroupSizes = getFlatWorkGroupSizes ( F ) ; unsigned MinImpliedByFlatWorkGroupSize = getMaxWavesPerEU ( FlatWorkGroupSizes . second ) ; bool RequestedFlatWorkGroupSize = false ; if ( F . hasFnAttribute ( "amdgpu-max-work-group-size" ) || F . hasFnAttribute ( "amdgpu-flat-work-group-size" ) ) { Default . first = MinImpliedByFlatWorkGroupSize ; RequestedFlatWorkGroupSize = true ; } std :: pair < unsigned , unsigned > Requested = AMDGPU :: getIntegerPairAttribute ( F , "amdgpu-waves-per-eu" , Default , true ) ; if ( Requested . second && Requested . first > Requested . second ) return Default ; if ( Requested . first < getMinWavesPerEU ( ) || Requested . first > getMaxWavesPerEU ( ) ) return Default ; if ( Requested . second > getMaxWavesPerEU ( ) ) return Default ; if ( RequestedFlatWorkGroupSize && Requested . first < MinImpliedByFlatWorkGroupSize ) return Default ; return Requested ; } </s>

Overload which uses the specified values for the flat work group sizes , rather than querying the function itself .

AMDGPU AMDGPU 1 "amdgpu-max-work-group-size" "amdgpu-flat-work-group-size" AMDGPU::getIntegerPairAttribute "amdgpu-waves-per-eu"


<s>
SDValue
Z80TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
LOAD
:
return
LowerLoad
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"Unable to lower Operation"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool X86InstrInfo :: hasStoreToStackSlot ( const MachineInstr * MI , const MachineMemOperand * & MMO , int & FrameIndex ) const { for ( MachineInstr :: mmo_iterator o = MI -> memoperands_begin ( ) , oe = MI -> memoperands_end ( ) ; o != oe ; ++ o ) { if ( ( * o ) -> isStore ( ) && ( * o ) -> getValue ( ) ) if ( const FixedStackPseudoSourceValue * Value = dyn_cast < const FixedStackPseudoSourceValue > ( ( * o ) -> getValue ( ) ) ) { FrameIndex = Value -> getFrameIndex ( ) ; MMO = * o ; return true ; } } return false ; } </s>

If the specified machine instruction has a store to a stack slot , return true along with the FrameIndices of the loaded stack slot and the machine mem operands containing the reference .


<s> void arc_asm_output_aligned_decl_local ( FILE * stream , tree decl , const char * name , unsigned HOST_WIDE_INT size , unsigned HOST_WIDE_INT align , unsigned HOST_WIDE_INT globalize_p ) { int in_small_data = arc_in_small_data_p ( decl ) ; rtx mem = decl == NULL_TREE ? NULL_RTX : DECL_RTL ( decl ) ; if ( mem != NULL_RTX && MEM_P ( mem ) && SYMBOL_REF_P ( XEXP ( mem , 0 ) ) && arc_is_aux_reg_p ( mem ) ) return ; if ( in_small_data ) switch_to_section ( get_named_section ( NULL , ".sbss" , 0 ) ) ; else switch_to_section ( bss_section ) ; if ( globalize_p ) ( * targetm . asm_out . globalize_label ) ( stream , name ) ; ASM_OUTPUT_ALIGN ( stream , floor_log2 ( ( align ) / BITS_PER_UNIT ) ) ; ASM_OUTPUT_TYPE_DIRECTIVE ( stream , name , "object" ) ; ASM_OUTPUT_SIZE_DIRECTIVE ( stream , name , size ) ; ASM_OUTPUT_LABEL ( stream , name ) ; if ( size != 0 ) ASM_OUTPUT_SKIP ( stream , size ) ; } </s>


<s> static MipsOperand * CreateMem ( MipsOperand * Base , const MCExpr * Off , SMLoc S , SMLoc E , MipsAsmParser & Parser ) { MipsOperand * Op = new MipsOperand ( k_Memory , Parser ) ; Op -> Mem . Base = Base ; Op -> Mem . Off = Off ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>


"You must enable NEON instructions (e.g. -mfloat-abi=softfp -mfpu=neon) to use these intrinsics."

"%Klane index must be a constant immediate"

Expand a Neon builtin , i.e . those registered only if TARGET_NEON holds . Most of these are `` special '' because they do n't have symbolic constants defined per-instruction or per instruction-variant . Instead , the required info is looked up in the table neon_builtin_data .


<s> bool RISCVTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( AM . BaseGV ) return false ; if ( Subtarget . hasVInstructions ( ) && isa < VectorType > ( Ty ) ) return AM . HasBaseReg && AM . Scale == 0 && ! AM . BaseOffs ; if ( ! isInt < 12 > ( AM . BaseOffs ) ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( ! AM . HasBaseReg ) break ; return false ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> static std :: unique_ptr < AMDGPUOperand > CreateReg ( unsigned RegNo , SMLoc S , SMLoc E , const MCRegisterInfo * TRI , bool ForceVOP3 ) { auto Op = llvm :: make_unique < AMDGPUOperand > ( Register ) ; Op -> Reg . RegNo = RegNo ; Op -> Reg . TRI = TRI ; Op -> Reg . Modifiers = - 1 ; Op -> Reg . IsForcedVOP3 = ForceVOP3 ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> bool ARMConstantPoolMBB :: hasSameValue ( ARMConstantPoolValue * ACPV ) { const ARMConstantPoolMBB * ACPMBB = dyn_cast < ARMConstantPoolMBB > ( ACPV ) ; return ACPMBB && ACPMBB -> MBB == MBB && ARMConstantPoolValue :: hasSameValue ( ACPV ) ; } </s>

hasSameValue - Return true if this ARM constpool value can share the same constantpool entry as another ARM constpool value .


<s> void ARMAsmPrinter :: emitInlineAsmEnd ( const MCSubtargetInfo & StartInfo , const MCSubtargetInfo * EndInfo ) const { const bool WasThumb = isThumb ( StartInfo ) ; if ( ! EndInfo || WasThumb != isThumb ( * EndInfo ) ) { OutStreamer . EmitAssemblerFlag ( WasThumb ? MCAF_Code16 : MCAF_Code32 ) ; } } </s>

Let the target do anything it needs to do after emitting inlineasm .


<s> static rtx get_jump_cond ( int n ) { if ( n >= 12 ) return NULL_RTX ; n += ss . jump_cycle_index ; if ( n >= 12 ) n -= 12 ; return ss . jump_cond [ n ] ; } </s>

Look up the jump condition with index N .


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { unsigned NumOps = Inst . getNumOperands ( ) ; if ( NumOps == 0 ) return false ; switch ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ NumOps - 1 ] . OperandType ) { case MCOI :: OPERAND_UNKNOWN : case MCOI :: OPERAND_IMMEDIATE : Target = Inst . getOperand ( NumOps - 1 ) . getImm ( ) ; return true ; case MCOI :: OPERAND_PCREL : Target = Addr + Inst . getOperand ( NumOps - 1 ) . getImm ( ) ; return true ; default : return false ; } } </s>

Given a branch instruction try to get the address the branch targets .


<s> bool HexagonAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; const MachineOperand & Base = MI -> getOperand ( OpNo ) ; const MachineOperand & Offset = MI -> getOperand ( OpNo + 1 ) ; if ( Base . isReg ( ) ) printOperand ( MI , OpNo , O ) ; else llvm_unreachable ( "Unimplemented" ) ; if ( Offset . isImm ( ) ) { if ( Offset . getImm ( ) ) O << "+#" << Offset . getImm ( ) ; } else { llvm_unreachable ( "Unimplemented" ) ; } return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .

Hexagon Hexagon 0 1 "Unimplemented" "+#" "Unimplemented"


<s> void arc_ccfsm_record_condition ( rtx cond , bool reverse , rtx_insn * jump , struct arc_ccfsm * state ) { rtx_insn * seq_insn = NEXT_INSN ( PREV_INSN ( jump ) ) ; if ( ! state ) state = & arc_ccfsm_current ; gcc_assert ( state -> state == 0 ) ; if ( seq_insn != jump ) { rtx insn = XVECEXP ( PATTERN ( seq_insn ) , 0 , 1 ) ; if ( ! as_a < rtx_insn * > ( insn ) -> deleted ( ) && INSN_ANNULLED_BRANCH_P ( jump ) && ( TARGET_AT_DBR_CONDEXEC || INSN_FROM_TARGET_P ( insn ) ) ) { state -> cond = cond ; state -> cc = get_arc_condition_code ( cond ) ; if ( ! reverse ) arc_ccfsm_current . cc = ARC_INVERSE_CONDITION_CODE ( state -> cc ) ; rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == COND_EXEC ) gcc_assert ( ( INSN_FROM_TARGET_P ( insn ) ? ARC_INVERSE_CONDITION_CODE ( state -> cc ) : state -> cc ) == get_arc_condition_code ( XEXP ( pat , 0 ) ) ) ; else state -> state = 5 ; } } } </s>

We are considering a conditional branch with the condition COND . Check if we want to conditionalize a delay slot insn , and if so modify the ccfsm state accordingly . REVERSE says branch will branch when the condition is false .


<s> SMLoc getStartLoc ( ) const { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s> bool X86TargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { auto Attr = CI -> getParent ( ) -> getParent ( ) -> getFnAttribute ( "disable-tail-calls" ) ; if ( ! CI -> isTailCall ( ) || Attr . getValueAsString ( ) == "true" ) return false ; CallSite CS ( CI ) ; CallingConv :: ID CalleeCC = CS . getCallingConv ( ) ; if ( ! IsTailCallConvention ( CalleeCC ) && ! IsCCallConvention ( CalleeCC ) ) return false ; return true ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> bool LoongArchAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


"FP elimination on a non-leaf function is not supported"

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool Error ( SMLoc L , const Twine & Msg , ArrayRef < SMRange > Ranges = ArrayRef < SMRange > ( ) , bool MatchingInlineAsm = false ) { if ( MatchingInlineAsm ) return true ; return Parser . Error ( L , Msg , Ranges ) ; } </s>

Return an error at the location L , with the message Msg .


<s> bool WinEHStatePass :: runOnFunction ( Function & F ) { if ( F . hasAvailableExternallyLinkage ( ) ) return false ; if ( ! F . hasPersonalityFn ( ) ) return false ; PersonalityFn = dyn_cast < Function > ( F . getPersonalityFn ( ) -> stripPointerCasts ( ) ) ; if ( ! PersonalityFn ) return false ; Personality = classifyEHPersonality ( PersonalityFn ) ; if ( ! isFuncletEHPersonality ( Personality ) ) return false ; bool HasPads = false ; for ( BasicBlock & BB : F ) { if ( BB . isEHPad ( ) ) { HasPads = true ; break ; } } if ( ! HasPads ) return false ; Type * Int8PtrType = Type :: getInt8PtrTy ( TheModule -> getContext ( ) ) ; SetJmp3 = TheModule -> getOrInsertFunction ( "_setjmp3" , FunctionType :: get ( Type :: getInt32Ty ( TheModule -> getContext ( ) ) , { Int8PtrType , Type :: getInt32Ty ( TheModule -> getContext ( ) ) } , true ) ) ; F . addFnAttr ( "no-frame-pointer-elim" , "true" ) ; emitExceptionRegistrationRecord ( & F ) ; WinEHFuncInfo FuncInfo ; addStateStores ( F , FuncInfo ) ; PersonalityFn = nullptr ; Personality = EHPersonality :: Unknown ; UseStackGuard = false ; RegNode = nullptr ; EHGuardNode = nullptr ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static const struct mips_cpu_info * mips_cpu_info_from_isa ( int isa ) { const struct mips_cpu_info * p ; for ( p = mips_cpu_info_table ; p -> name != 0 ; p ++ ) if ( p -> isa == isa ) return p ; return 0 ; } </s>

Return the processor associated with the given ISA level , or null if the ISA is n't valid .