<s> void ix86_split_copysign_var ( rtx operands [ ] ) { machine_mode mode , vmode ; rtx dest , scratch , op0 , op1 , mask , nmask , x ; dest = operands [ 0 ] ; scratch = operands [ 1 ] ; op0 = operands [ 2 ] ; op1 = operands [ 3 ] ; nmask = operands [ 4 ] ; mask = operands [ 5 ] ; mode = GET_MODE ( dest ) ; vmode = GET_MODE ( mask ) ; if ( rtx_equal_p ( op0 , op1 ) ) { emit_move_insn ( dest , op0 ) ; return ; } if ( REG_P ( mask ) && REGNO ( dest ) == REGNO ( mask ) ) { gcc_assert ( REGNO ( op1 ) == REGNO ( scratch ) ) ; x = gen_rtx_AND ( vmode , scratch , mask ) ; emit_insn ( gen_rtx_SET ( VOIDmode , scratch , x ) ) ; dest = mask ; op0 = simplify_gen_subreg ( vmode , op0 , mode , 0 ) ; x = gen_rtx_NOT ( vmode , dest ) ; x = gen_rtx_AND ( vmode , x , op0 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , x ) ) ; } else { if ( REGNO ( op1 ) == REGNO ( scratch ) ) { x = gen_rtx_AND ( vmode , scratch , mask ) ; } else { gcc_assert ( REGNO ( mask ) == REGNO ( scratch ) ) ; op1 = simplify_gen_subreg ( vmode , op1 , mode , 0 ) ; x = gen_rtx_AND ( vmode , scratch , op1 ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , scratch , x ) ) ; if ( REGNO ( op0 ) == REGNO ( dest ) ) { dest = simplify_gen_subreg ( vmode , op0 , mode , 0 ) ; x = gen_rtx_AND ( vmode , dest , nmask ) ; } else { gcc_assert ( REGNO ( nmask ) == REGNO ( dest ) ) ; dest = nmask ; op0 = simplify_gen_subreg ( vmode , op0 , mode , 0 ) ; x = gen_rtx_AND ( vmode , dest , op0 ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , dest , x ) ) ; } x = gen_rtx_IOR ( vmode , dest , scratch ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , x ) ) ; } </s>

Deconstruct a copysign operation into bit masks . Operand 0 is variable , so we have to do two masks .


<s> bool useLoadStackGuardNode ( ) const override { return true ; } </s>

If this function returns true , SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic : :stackprotector .


<s>
const
char
*
m68k_output_branch_integer_rev
(
rtx_code
code
)
{
switch
(
code
)
{
case
EQ
:
return
"jne %l3"
;
case
NE
:
return
"jeq %l3"
;
case
GT
:
return
"jle %l3"
;
case
GTU
:
return
"jls %l3"
;
case
LT
:
return
"jge %l3"
;
case
LTU
:
return
"jcc %l3"
;
case
GE
:
return
"jlt %l3"
;
case
GEU
:
return
"jcs %l3"
;
case
LE
:
return
"jgt %l3"
;
case
LEU
:
return
"jhi %l3"
;
case
PLUS
:
return
"jmi %l3"
;
case
MINUS
:
return
"jpl %l3"
;
default
:
gcc_unreachable
(
)
;
}
}
</s>

Return an output template for a reversed branch with CODE .

m68k
"jne %l3"
"jeq %l3"
"jle %l3"
"jls %l3"
"jge %l3"
"jcc %l3"
"jlt %l3"
"jcs %l3"
"jgt %l3"
"jhi %l3"
"jmi %l3"
"jpl %l3"


<s> SystemZConstantPoolValue * SystemZConstantPoolValue :: Create ( const GlobalValue * GV , SystemZCP :: SystemZCPModifier Modifier ) { return new SystemZConstantPoolValue ( GV , Modifier ) ; } </s>

Construct a unary instruction , given the opcode and an operand .

SystemZ SystemZ SystemZ SystemZCP::SystemZCPModifier SystemZ


<s> MMIXSubtarget & MMIXSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "generic-mmix" ; ParseSubtargetFeatures ( CPUName , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool runOnMachineFunction ( MachineFunction & Fn ) override { Subtarget = & Fn . getSubtarget < HexagonSubtarget > ( ) ; return AsmPrinter :: runOnMachineFunction ( Fn ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> unsigned PPCInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { unsigned Opcode = MI . getOpcode ( ) ; const unsigned * OpcodesForSpill = getStoreOpcodesForSpillArray ( ) ; const unsigned * End = OpcodesForSpill + SOK_LastOpcodeSpill ; if ( End != std :: find ( OpcodesForSpill , End , Opcode ) ) { if ( MI . getOperand ( 1 ) . isImm ( ) && ! MI . getOperand ( 1 ) . getImm ( ) && MI . getOperand ( 2 ) . isFI ( ) ) { FrameIndex = MI . getOperand ( 2 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> const Nios2FrameLowering * Nios2FrameLowering :: create ( const Nios2Subtarget & ST ) { return new Nios2FrameLowering ( ST , 4 ) ; } </s>


<s> rtx aarch64_expand_sve_dupq ( rtx target , machine_mode mode , rtx src ) { machine_mode src_mode = GET_MODE ( src ) ; gcc_assert ( GET_MODE_INNER ( mode ) == GET_MODE_INNER ( src_mode ) ) ; insn_code icode = ( BYTES_BIG_ENDIAN ? code_for_aarch64_vec_duplicate_vq_be ( mode ) : code_for_aarch64_vec_duplicate_vq_le ( mode ) ) ; unsigned int i = 0 ; expand_operand ops [ 3 ] ; create_output_operand ( & ops [ i ++ ] , target , mode ) ; create_output_operand ( & ops [ i ++ ] , src , src_mode ) ; if ( BYTES_BIG_ENDIAN ) { unsigned int nelts_per_vq = 128 / GET_MODE_UNIT_BITSIZE ( mode ) ; rtx sel = aarch64_gen_stepped_int_parallel ( nelts_per_vq , nelts_per_vq - 1 , - 1 ) ; create_fixed_operand ( & ops [ i ++ ] , sel ) ; } expand_insn ( icode , i , ops ) ; return ops [ 0 ] . value ; } </s>

Duplicate 128-bit Advanced SIMD vector SRC so that it fills an SVE register of mode MODE . Use TARGET for the result if it 's nonnull and convenient . The two vector modes must have the same element mode . The behavior is to duplicate architectural lane N of SRC into architectural lanes N + I * STEP of the result . On big-endian targets , architectural lane 0 of an Advanced SIMD vector is the last element of the vector in memory layout , so for big-endian targets this operation has the effect of reversing SRC before duplicating it . Callers need to account for this .


<s> bool HexagonAsmParser :: isLabel ( AsmToken & Token ) { MCAsmLexer & Lexer = getLexer ( ) ; AsmToken const & Second = Lexer . getTok ( ) ; AsmToken Third = Lexer . peekTok ( ) ; StringRef String = Token . getString ( ) ; if ( Token . is ( AsmToken :: TokenKind :: LCurly ) || Token . is ( AsmToken :: TokenKind :: RCurly ) ) return false ; if ( String . lower ( ) == "vwhist256" && Second . is ( AsmToken :: Colon ) && Third . getString ( ) . lower ( ) == "sat" ) return false ; if ( ! Token . is ( AsmToken :: TokenKind :: Identifier ) ) return true ; if ( ! matchRegister ( String . lower ( ) ) ) return true ; ( void ) Second ; assert ( Second . is ( AsmToken :: Colon ) ) ; StringRef Raw ( String . data ( ) , Third . getString ( ) . data ( ) - String . data ( ) + Third . getString ( ) . size ( ) ) ; std :: string Collapsed = Raw ; Collapsed . erase ( llvm :: remove_if ( Collapsed , isspace ) , Collapsed . end ( ) ) ; StringRef Whole = Collapsed ; std :: pair < StringRef , StringRef > DotSplit = Whole . split ( '.' ) ; if ( ! matchRegister ( DotSplit . first . lower ( ) ) ) return true ; return false ; } </s>

Returns true if the MachineInstr represents a label .


<s> bool GCNPassConfig :: addInstSelector ( ) { AMDGPUPassConfig :: addInstSelector ( ) ; addPass ( & SIFixSGPRCopiesID ) ; addPass ( createSILowerI1CopiesPass ( ) ) ; addPass ( createSIAddIMGInitPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void emitLocalCommonSymbol ( MCSymbol * Symbol , uint64_t Size , unsigned ByteAlignment ) override { } </s>


<s> unsigned M680x0Subtarget :: getJumpTableEncoding ( ) const { if ( isPositionIndependent ( ) ) { if ( TM . getCodeModel ( ) == CodeModel :: Medium && ! isM68020 ( ) ) return MachineJumpTableInfo :: EK_Custom32 ; return MachineJumpTableInfo :: EK_LabelDifference32 ; } return MachineJumpTableInfo :: EK_BlockAddress ; } </s>

Return the entry encoding for a jump table in the current function .


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const PPCFrameLowering * TFI = getFrameLowering ( MF ) ; markSuperRegs ( Reserved , PPC :: ZERO ) ; markSuperRegs ( Reserved , PPC :: FP ) ; markSuperRegs ( Reserved , PPC :: BP ) ; markSuperRegs ( Reserved , PPC :: CTR ) ; markSuperRegs ( Reserved , PPC :: CTR8 ) ; markSuperRegs ( Reserved , PPC :: R1 ) ; markSuperRegs ( Reserved , PPC :: LR ) ; markSuperRegs ( Reserved , PPC :: LR8 ) ; markSuperRegs ( Reserved , PPC :: RM ) ; markSuperRegs ( Reserved , PPC :: VRSAVE ) ; if ( Subtarget . isSVR4ABI ( ) ) { const PPCFunctionInfo * FuncInfo = MF . getInfo < PPCFunctionInfo > ( ) ; if ( ! TM . isPPC64 ( ) || FuncInfo -> usesTOCBasePtr ( ) || MF . hasInlineAsm ( ) ) markSuperRegs ( Reserved , PPC :: R2 ) ; markSuperRegs ( Reserved , PPC :: R13 ) ; } if ( Subtarget . isAIXABI ( ) ) markSuperRegs ( Reserved , PPC :: R2 ) ; if ( TM . isPPC64 ( ) ) markSuperRegs ( Reserved , PPC :: R13 ) ; if ( TFI -> needsFP ( MF ) ) markSuperRegs ( Reserved , PPC :: R31 ) ; bool IsPositionIndependent = TM . isPositionIndependent ( ) ; if ( hasBasePointer ( MF ) ) { if ( Subtarget . is32BitELFABI ( ) && IsPositionIndependent ) markSuperRegs ( Reserved , PPC :: R29 ) ; else markSuperRegs ( Reserved , PPC :: R30 ) ; } if ( Subtarget . is32BitELFABI ( ) && IsPositionIndependent ) markSuperRegs ( Reserved , PPC :: R30 ) ; if ( ! Subtarget . hasAltivec ( ) ) for ( TargetRegisterClass :: iterator I = PPC :: VRRCRegClass . begin ( ) , IE = PPC :: VRRCRegClass . end ( ) ; I != IE ; ++ I ) markSuperRegs ( Reserved , * I ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
static
bool
arm_rtx_costs
(
rtx
x
,
machine_mode
mode
ATTRIBUTE_UNUSED
,
int
outer_code
,
int
opno
ATTRIBUTE_UNUSED
,
int
*
total
,
bool
speed
)
{
bool
result
;
int
code
=
GET_CODE
(
x
)
;
gcc_assert
(
current_tune
->
insn_extra_cost
)
;
result
=
arm_rtx_costs_internal
(
x
,
(
enum
rtx_code
)
code
,
(
enum
rtx_code
)
outer_code
,
current_tune
->
insn_extra_cost
,
total
,
speed
)
;
if
(
dump_file
&&
(
dump_flags
&
TDF_DETAILS
)
)
{
print_rtl_single
(
dump_file
,
x
)
;
fprintf
(
dump_file
,
"\n%s cost: %d (%s)\n"
,
speed
"Hot"
:
"Cold"
,
*
total
,
result
"final"
:
"partial"
)
;
}
return
result
;
}
</s>

arm
"\n%s cost: %d (%s)\n"
"Hot"
"Cold"
"final"
"partial"


<s> void Thumb2HazardRecognizer :: Reset ( ) { ITBlockSize = 0 ; PostRAHazardRecognizer :: Reset ( ) ; } </s>


<s>
bool
AArch64FrameLowering
::
restoreCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
;
SmallVector
<
RegPairInfo
,
8
>
RegPairs
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
computeCalleeSaveRegisterPairs
(
MF
,
CSI
,
TRI
,
RegPairs
)
;
for
(
auto
RPII
=
RegPairs
.
begin
(
)
,
RPIE
=
RegPairs
.
end
(
)
;
RPII
!=
RPIE
;
++
RPII
)
{
RegPairInfo
RPI
=
*
RPII
;
unsigned
Reg1
=
RPI
.
Reg1
;
unsigned
Reg2
=
RPI
.
Reg2
;
unsigned
LdrOpc
;
if
(
RPI
.
IsGPR
)
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPXi
:
AArch64
::
LDRXui
;
else
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPDi
:
AArch64
::
LDRDui
;
DEBUG
(
dbgs
(
)
<<
"CSR restore: ("
<<
printReg
(
Reg1
,
TRI
)
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
printReg
(
Reg2
,
TRI
)
;
dbgs
(
)
<<
") -> fi#("
<<
RPI
.
FrameIdx
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
RPI
.
FrameIdx
+
1
;
dbgs
(
)
<<
")\n"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
LdrOpc
)
)
;
if
(
RPI
.
isPaired
(
)
)
{
MIB
.
addReg
(
Reg2
,
getDefRegState
(
true
)
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
+
1
)
,
MachineMemOperand
::
MOLoad
,
8
,
8
)
)
;
}
MIB
.
addReg
(
Reg1
,
getDefRegState
(
true
)
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
RPI
.
Offset
)
.
setMIFlag
(
MachineInstr
::
FrameDestroy
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
)
,
MachineMemOperand
::
MOLoad
,
8
,
8
)
)
;
}
return
true
;
}
</s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool ARMBaseInstrInfo :: hasHighOperandLatency ( const TargetSchedModel & SchedModel , const MachineRegisterInfo * MRI , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * UseMI , unsigned UseIdx ) const { unsigned DDomain = DefMI -> getDesc ( ) . TSFlags & ARMII :: DomainMask ; unsigned UDomain = UseMI -> getDesc ( ) . TSFlags & ARMII :: DomainMask ; if ( Subtarget . isCortexA8 ( ) && ( DDomain == ARMII :: DomainVFP || UDomain == ARMII :: DomainVFP ) ) return true ; unsigned Latency = SchedModel . computeOperandLatency ( DefMI , DefIdx , UseMI , UseIdx ) ; if ( Latency <= 3 ) return false ; return DDomain == ARMII :: DomainVFP || DDomain == ARMII :: DomainNEON || UDomain == ARMII :: DomainVFP || UDomain == ARMII :: DomainNEON ; } </s>

Compute operand latency between a def of 'Reg ' and a use in the current loop .

ARM ARM ARMII::DomainMask ARMII::DomainMask ARMII::DomainVFP ARMII::DomainVFP 3 ARMII::DomainVFP ARMII::DomainNEON ARMII::DomainVFP ARMII::DomainNEON


<s> MVT :: SimpleValueType Z80TargetLowering :: getCmpLibcallReturnType ( ) const { return MVT :: Other ; } </s>

Return the ValueType for comparison libcalls .


<s> static inline bool rs6000_builtin_type_compatible ( tree t , int id ) { tree builtin_type ; builtin_type = rs6000_builtin_type ( id ) ; if ( t == error_mark_node ) return false ; if ( INTEGRAL_TYPE_P ( t ) && INTEGRAL_TYPE_P ( builtin_type ) ) return true ; else return lang_hooks . types_compatible_p ( t , builtin_type ) ; } </s>

Return true iff ARGTYPE can be compatibly passed as PARMTYPE .


<s> int avx_vperm2f128_parallel ( rtx par , machine_mode mode ) { unsigned i , nelt = GET_MODE_NUNITS ( mode ) , nelt2 = nelt / 2 ; unsigned mask = 0 ; unsigned char ipar [ 8 ] = { } ; if ( XVECLEN ( par , 0 ) != ( int ) nelt ) return 0 ; for ( i = 0 ; i < nelt ; ++ i ) { rtx er = XVECEXP ( par , 0 , i ) ; unsigned HOST_WIDE_INT ei ; if ( ! CONST_INT_P ( er ) ) return 0 ; ei = INTVAL ( er ) ; if ( ei >= 2 * nelt ) return 0 ; ipar [ i ] = ei ; } for ( i = 0 ; i < nelt2 - 1 ; ++ i ) if ( ipar [ i ] + 1 != ipar [ i + 1 ] ) return 0 ; for ( i = nelt2 ; i < nelt - 1 ; ++ i ) if ( ipar [ i ] + 1 != ipar [ i + 1 ] ) return 0 ; for ( i = 0 ; i < 2 ; ++ i ) { unsigned e = ipar [ i * nelt2 ] ; if ( e % nelt2 ) return 0 ; e /= nelt2 ; mask |= e << ( i * 4 ) ; } return mask + 1 ; } </s>

Helper for avx_vperm2f128_v4df_operand et al . This is also used by the expansion functions to turn the parallel back into a mask . The return value is 0 for no match and the imm8+1 for a match .


<s> bool ARMCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { auto & TLI = * getTLI < ARMTargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb ( ) ) return false ; if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; auto DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasByValOrInAllocaAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , 8 > ArgInfos ; SmallVector < unsigned , 4 > SplitRegs ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; SplitRegs . clear ( ) ; splitToValueTypes ( AInfo , ArgInfos , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { SplitRegs . push_back ( Reg ) ; } ) ; if ( ! SplitRegs . empty ( ) ) MIRBuilder . buildMerge ( VRegs [ Idx ] , SplitRegs ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; return handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> bool XCoreDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Reg ; switch ( ConstraintCode ) { default : return true ; case 'm' : switch ( Op . getOpcode ( ) ) { default : return true ; case XCoreISD :: CPRelativeWrapper : Reg = CurDAG -> getRegister ( XCore :: CP , MVT :: i32 ) ; break ; case XCoreISD :: DPRelativeWrapper : Reg = CurDAG -> getRegister ( XCore :: DP , MVT :: i32 ) ; break ; } } OutOps . push_back ( Reg ) ; OutOps . push_back ( Op . getOperand ( 0 ) ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .

XCore XCore XCoreISD::CPRelativeWrapper XCore::CP MVT::i32 XCoreISD::DPRelativeWrapper XCore::DP MVT::i32 0


<s> static int arc_restore_callee_saves ( uint64_t gmask , bool restore_blink , bool restore_fp , HOST_WIDE_INT offset , HOST_WIDE_INT allocated ) { rtx reg ; int frame_deallocated = 0 ; HOST_WIDE_INT offs = cfun -> machine -> frame_info . reg_size ; unsigned int fn_type = arc_compute_function_type ( cfun ) ; bool early_blink_restore ; int i ; if ( arc_frame_pointer_needed ( ) && offset ) { frame_move ( stack_pointer_rtx , hard_frame_pointer_rtx ) ; frame_deallocated += offset ; offset = 0 ; } if ( restore_fp ) { gcc_assert ( offset == 0 ) ; frame_deallocated += frame_restore_reg ( hard_frame_pointer_rtx , 0 ) ; } if ( offset ) { frame_stack_add ( offset ) ; frame_deallocated += offset ; offset = 0 ; } early_blink_restore = restore_blink && ! optimize_size && offs && ! ARC_INTERRUPT_P ( fn_type ) ; if ( early_blink_restore ) { rtx addr = plus_constant ( Pmode , stack_pointer_rtx , offs ) ; reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; rtx insn = frame_move_inc ( reg , gen_frame_mem ( Pmode , addr ) , stack_pointer_rtx , NULL_RTX ) ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; restore_blink = false ; } if ( gmask ) for ( i = 0 ; i <= GMASK_LEN ; i ++ ) { machine_mode restore_mode = SImode ; if ( TARGET_LL64 && ( ( i % 2 ) == 0 ) && ( ( gmask & ( 1ULL << i ) ) != 0 ) && ( ( gmask & ( 1ULL << ( i + 1 ) ) ) != 0 ) ) restore_mode = DImode ; else if ( ( gmask & ( 1ULL << i ) ) == 0 ) continue ; reg = gen_rtx_REG ( restore_mode , i ) ; offs = 0 ; switch ( restore_mode ) { case E_DImode : if ( ( GMASK_LEN - __builtin_clzll ( gmask ) ) == ( i + 1 ) && early_blink_restore ) offs = 4 ; break ; case E_SImode : if ( ( GMASK_LEN - __builtin_clzll ( gmask ) ) == i && early_blink_restore ) offs = 4 ; break ; default : offs = 0 ; } frame_deallocated += frame_restore_reg ( reg , offs ) ; offset = 0 ; if ( restore_mode == DImode ) i ++ ; } if ( restore_blink ) { reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; frame_deallocated += frame_restore_reg ( reg , allocated - frame_deallocated - UNITS_PER_WORD ) ; } return frame_deallocated ; } </s>

ARC 's epilogue , restore any required call-saved regs ( and call-used if it is for an interrupt handler ) using LD/LDD instructions .


<s>
LLVM_DUMP_METHOD
void
dump
(
const
MachineRegisterInfo
*
MRI
)
const
{
dbgs
(
)
<<
"Registers: "
;
bool
First
=
true
;
for
(
unsigned
Reg
:
Edges
)
{
if
(
!
First
)
dbgs
(
)
<<
", "
;
First
=
false
;
dbgs
(
)
<<
printReg
(
Reg
,
MRI
->
getTargetRegisterInfo
(
)
)
;
}
dbgs
(
)
<<
"\n"
<<
"Instructions:"
;
for
(
MachineInstr
*
MI
:
Instrs
)
{
dbgs
(
)
<<
"\n  "
;
MI
->
print
(
dbgs
(
)
)
;
}
dbgs
(
)
<<
"\n"
;
}
</s>

Dump the plan to stderr ( for debugging ) .

X86
"Registers: "
", "
"\n"
"Instructions:"
"\n  "
"\n"


<s> bool HSAILAlwaysInline :: runOnModule ( Module & M ) { std :: vector < Function * > FuncsToClone ; for ( Module :: iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) { Function & F = * I ; if ( ! F . hasLocalLinkage ( ) && ! F . isDeclaration ( ) && ! F . use_empty ( ) && ! F . hasFnAttribute ( Attribute :: NoInline ) ) FuncsToClone . push_back ( & F ) ; } for ( Function * F : FuncsToClone ) { ValueToValueMapTy VMap ; Function * NewFunc = CloneFunction ( F , VMap , false ) ; NewFunc -> setLinkage ( GlobalValue :: InternalLinkage ) ; F -> getParent ( ) -> getFunctionList ( ) . push_back ( NewFunc ) ; F -> replaceAllUsesWith ( NewFunc ) ; } for ( Module :: iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) { Function & F = * I ; if ( F . hasLocalLinkage ( ) && ! F . hasFnAttribute ( Attribute :: NoInline ) ) { F . addFnAttr ( Attribute :: AlwaysInline ) ; } } return false ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


"when storing %qT, %qE requires a vector"

"%qE requires a vector base and a scalar"

"%qE does not support 32-bit vector type %qT"

"%qE does not support 32-bit sign-extended"

"passing %qT to argument %d of %qE, which when"

" loading %qT expects a vector of %d-bit integers"

" storing %qT expects a vector of %d-bit integers"

"passing %qT to argument %d of %qE, which"

Require argument ARGNO to be a vector displacement in a gather-style address . There are three possible uses : - for loading into elements of type TYPE ( when LOAD_P is true ) - for storing from elements of type TYPE ( when LOAD_P is false ) - for prefetching data ( when TYPE is NUM_TYPE_SUFFIXES ) The overloaded function 's mode suffix determines the units of the displacement ( bytes for `` _offset '' , elements for `` _index '' ) . Return the associated mode on success , otherwise report an error and return MODE_none .


<s> LoadInst * X86TargetLowering :: lowerIdempotentRMWIntoFencedLoad ( AtomicRMWInst * AI ) const { unsigned NativeWidth = Subtarget . is64Bit ( ) ? 64 : 32 ; Type * MemType = AI -> getType ( ) ; if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) return nullptr ; auto Builder = IRBuilder < > ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SSID = AI -> getSyncScopeID ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; auto Ptr = AI -> getPointerOperand ( ) ; if ( SSID == SyncScope :: SingleThread ) return nullptr ; if ( ! Subtarget . hasMFence ( ) ) return nullptr ; Function * MFence = llvm :: Intrinsic :: getDeclaration ( M , Intrinsic :: x86_sse2_mfence ) ; Builder . CreateCall ( MFence , { } ) ; LoadInst * Loaded = Builder . CreateAlignedLoad ( Ptr , AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ) ; Loaded -> setAtomic ( Order , SSID ) ; AI -> replaceAllUsesWith ( Loaded ) ; AI -> eraseFromParent ( ) ; return Loaded ; } </s>

On some platforms , an AtomicRMW that never actually modifies the value ( such as fetch_add of 0 ) can be turned into a fence followed by an atomic load .


<s> HOST_WIDE_INT compute_frame_size ( HOST_WIDE_INT size , int * fregs_live ) { int freg_saved = 0 ; int i , j ; size = ( size + UNITS_PER_WORD - 1 ) & ~ ( UNITS_PER_WORD - 1 ) ; if ( size || frame_pointer_needed ) size += STARTING_FRAME_OFFSET ; if ( DO_FRAME_NOTES && current_function_calls_eh_return ) { unsigned int i ; for ( i = 0 ; EH_RETURN_DATA_REGNO ( i ) != INVALID_REGNUM ; ++ i ) continue ; size += i * UNITS_PER_WORD ; } for ( i = 18 , j = frame_pointer_needed ? 4 : 3 ; i >= j ; i -- ) if ( regs_ever_live [ i ] ) size += UNITS_PER_WORD ; for ( i = FP_SAVED_REG_LAST ; i >= FP_SAVED_REG_FIRST ; i -= FP_REG_STEP ) if ( regs_ever_live [ i ] || ( ! TARGET_64BIT && regs_ever_live [ i + 1 ] ) ) { freg_saved = 1 ; size += 8 ; } if ( freg_saved ) { size = ( size + 7 ) & ~ 7 ; if ( fregs_live ) * fregs_live = 1 ; } size += current_function_outgoing_args_size ; if ( ! current_function_is_leaf || size ) size += TARGET_64BIT ? 48 : 32 ; return ( ( size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1 ) & ~ ( PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1 ) ) ; } </s>

Typical stack layout should looks like this after the function 's prologue : | | -- ^ | | \ | | | arguments saved | Increasing | | on the stack | addresses PARENT arg pointer - > | | / -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - | | - space for argument split between regs & stack -- CHILD | | \ < -- ( return address here ) | | other call | | saved registers | | / -- frame pointer - > | | \ ___ | | local | | | variables |f | | / |r -- |a | | \ |m | | outgoing |e | | arguments | | Decreasing ( hard ) frame pointer | | / | | addresses and stack pointer - > | | / _|_ | -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- V


<s> void MSP430InstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; if ( Desc . TSFlags & MSP430TSFlags :: RptCount ) printRptDirective ( MI , O ) ; if ( ! printAliasInstr ( MI , Address , O ) ) printInstruction ( MI , Address , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool ARMBaseInstrInfo :: shouldScheduleLoadsNear ( SDNode * Load1 , SDNode * Load2 , int64_t Offset1 , int64_t Offset2 , unsigned NumLoads ) const { if ( Subtarget . isThumb1Only ( ) ) return false ; assert ( Offset2 > Offset1 ) ; if ( ( Offset2 - Offset1 ) / 8 > 64 ) return false ; if ( Load1 -> getMachineOpcode ( ) != Load2 -> getMachineOpcode ( ) ) return false ; if ( NumLoads >= 3 ) return false ; return true ; } </s>

shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine ( in conjunction with areLoadsFromSameBasePtr ) if two loads should be scheduled togther .


<s>
void
RISCVInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MBBI
,
const
DebugLoc
&
DL
,
MCRegister
DstReg
,
MCRegister
SrcReg
,
bool
KillSrc
)
const
{
if
(
RISCV
::
GPRRegClass
.
contains
(
DstReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
RISCV
::
ADDI
)
,
DstReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
0
)
;
return
;
}
unsigned
Opc
;
bool
IsScalableVector
=
false
;
if
(
RISCV
::
FPR16RegClass
.
contains
(
DstReg
,
SrcReg
)
)
Opc
=
RISCV
::
FSGNJ_H
;
else
if
(
RISCV
::
FPR32RegClass
.
contains
(
DstReg
,
SrcReg
)
)
Opc
=
RISCV
::
FSGNJ_S
;
else
if
(
RISCV
::
FPR64RegClass
.
contains
(
DstReg
,
SrcReg
)
)
Opc
=
RISCV
::
FSGNJ_D
;
else
if
(
RISCV
::
VRRegClass
.
contains
(
DstReg
,
SrcReg
)
)
{
Opc
=
RISCV
::
PseudoVMV1R_V
;
IsScalableVector
=
true
;
}
else
if
(
RISCV
::
VRM2RegClass
.
contains
(
DstReg
,
SrcReg
)
)
{
Opc
=
RISCV
::
PseudoVMV2R_V
;
IsScalableVector
=
true
;
}
else
if
(
RISCV
::
VRM4RegClass
.
contains
(
DstReg
,
SrcReg
)
)
{
Opc
=
RISCV
::
PseudoVMV4R_V
;
IsScalableVector
=
true
;
}
else
if
(
RISCV
::
VRM8RegClass
.
contains
(
DstReg
,
SrcReg
)
)
{
Opc
=
RISCV
::
PseudoVMV8R_V
;
IsScalableVector
=
true
;
}
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
if
(
IsScalableVector
)
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
Opc
)
,
DstReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
Opc
)
,
DstReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> static void s390_encode_section_info ( tree decl , rtx rtl , int first ) { default_encode_section_info ( decl , rtl , first ) ; if ( TREE_CODE ( decl ) == VAR_DECL ) { if ( DECL_ALIGN ( decl ) % 64 ) SYMBOL_FLAG_SET_NOTALIGN8 ( XEXP ( rtl , 0 ) ) ; if ( DECL_ALIGN ( decl ) % 32 ) SYMBOL_FLAG_SET_NOTALIGN4 ( XEXP ( rtl , 0 ) ) ; if ( DECL_ALIGN ( decl ) == 0 || DECL_ALIGN ( decl ) % 16 ) SYMBOL_FLAG_SET_NOTALIGN2 ( XEXP ( rtl , 0 ) ) ; } if ( MEM_P ( rtl ) && GET_CODE ( XEXP ( rtl , 0 ) ) == SYMBOL_REF && TREE_CONSTANT_POOL_ADDRESS_P ( XEXP ( rtl , 0 ) ) && MEM_ALIGN ( rtl ) != 0 && GET_MODE_BITSIZE ( GET_MODE ( rtl ) ) != 0 ) { if ( MEM_ALIGN ( rtl ) % 64 ) SYMBOL_FLAG_SET_NOTALIGN8 ( XEXP ( rtl , 0 ) ) ; if ( MEM_ALIGN ( rtl ) % 32 ) SYMBOL_FLAG_SET_NOTALIGN4 ( XEXP ( rtl , 0 ) ) ; if ( MEM_ALIGN ( rtl ) == 0 || MEM_ALIGN ( rtl ) % 16 ) SYMBOL_FLAG_SET_NOTALIGN2 ( XEXP ( rtl , 0 ) ) ; } } </s>

Encode symbol attributes ( local vs. global , tls model ) of a SYMBOL_REF into its SYMBOL_REF_FLAGS .


<s> unsigned AArch64TTIImpl :: getPrefetchDistance ( ) { return ST -> getPrefetchDistance ( ) ; } </s>

Return the preferred prefetch distance in terms of instructions .


Return TRUE if changing mode from FROM to TO should not be allowed for register class CLASS .


<s> bool MipsAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < MipsSubtarget > ( ) ; MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; if ( Subtarget -> inMips16Mode ( ) ) for ( std :: map < const char * , const llvm :: Mips16HardFloatInfo :: FuncSignature * > :: const_iterator it = MipsFI -> StubsNeeded . begin ( ) ; it != MipsFI -> StubsNeeded . end ( ) ; ++ it ) { const char * Symbol = it -> first ; const llvm :: Mips16HardFloatInfo :: FuncSignature * Signature = it -> second ; if ( StubsNeeded . find ( Symbol ) == StubsNeeded . end ( ) ) StubsNeeded [ Symbol ] = Signature ; } MCP = MF . getConstantPool ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) NaClAlignIndirectJumpTargets ( MF ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; emitXRayTable ( ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .

Mips Mips Mips Mips Mips Mips Mips16HardFloatInfo::FuncSignature Mips Mips Mips16HardFloatInfo::FuncSignature


"getExplicitSectionGlobal not yet implemented!"

Targets should implement this method to assign a section to globals with an explicit section specfied .


<s> Optional < MCFixupKind > AArch64AsmBackend :: getFixupKind ( StringRef Name ) const { if ( ! TheTriple . isOSBinFormatELF ( ) ) return None ; unsigned Type = llvm :: StringSwitch < unsigned > ( Name ) . Default ( - 1u ) ; if ( Type == - 1u ) return None ; return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Fast Tile Register Configure"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool ARMTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( Subtarget -> isThumb ( ) ) return false ; MVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == ISD :: SEXTLOAD ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; } else return false ; bool isInc ; bool isLegal = getIndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( isLegal ) { AM = isInc ? ISD :: PRE_INC : ISD :: PRE_DEC ; return true ; } return false ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .

ARM ARM ISD::MemIndexedMode ISD::SEXTLOAD ISD::PRE_INC ISD::PRE_DEC


<s> unsigned VideocoreMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups ) const { if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; unsigned RegNo = getVideocoreRegisterNumbering ( Reg ) ; return RegNo ; } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isFPImm ( ) ) { return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( 32 ) . getLimitedValue ( ) ) ; } assert ( MO . isExpr ( ) ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; if ( Kind == MCExpr :: Binary ) { Expr = static_cast < const MCBinaryExpr * > ( Expr ) -> getLHS ( ) ; Kind = Expr -> getKind ( ) ; } assert ( Kind == MCExpr :: SymbolRef ) ; return 0 ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> static bool rs6000_vectorize_vec_perm_const ( machine_mode vmode , machine_mode op_mode , rtx target , rtx op0 , rtx op1 , const vec_perm_indices & sel ) { if ( vmode != op_mode ) return false ; bool testing_p = ! target ; if ( TARGET_ALTIVEC && testing_p ) return true ; if ( op0 ) { rtx nop0 = force_reg ( vmode , op0 ) ; if ( op0 == op1 ) op1 = nop0 ; op0 = nop0 ; } if ( op1 ) op1 = force_reg ( vmode , op1 ) ; if ( ( vmode == V2DFmode || vmode == V2DImode ) && VECTOR_MEM_VSX_P ( vmode ) ) { if ( testing_p ) { op0 = gen_raw_REG ( vmode , LAST_VIRTUAL_REGISTER + 1 ) ; op1 = gen_raw_REG ( vmode , LAST_VIRTUAL_REGISTER + 2 ) ; } if ( rs6000_expand_vec_perm_const_1 ( target , op0 , op1 , sel [ 0 ] , sel [ 1 ] ) ) return true ; } if ( TARGET_ALTIVEC ) { if ( vmode != V16QImode ) return false ; if ( altivec_expand_vec_perm_const ( target , op0 , op1 , sel ) ) return true ; } return false ; } </s>


<s> SDNode * PPCDAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * TM . getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc dl ; if ( PPCLowering . getPointerTy ( ) == MVT :: i32 ) { GlobalBaseReg = RegInfo -> createVirtualRegister ( PPC :: GPRCRegisterClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) , PPC :: LR ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( PPC :: G8RCRegisterClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR8 ) , PPC :: LR8 ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR8 ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , PPCLowering . getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s>
SDValue
AVRTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
auto
CCFunction
=
CCAssignFnForReturn
(
CallConv
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
CCFunction
)
;
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
unsigned
e
=
RVLocs
.
size
(
)
;
if
(
e
>
1
)
{
std
::
reverse
(
RVLocs
.
begin
(
)
,
RVLocs
.
end
(
)
)
;
}
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
if
(
MF
.
getFunction
(
)
->
getAttributes
(
)
.
hasAttribute
(
AttributeSet
::
FunctionIndex
,
Attribute
::
Naked
)
)
{
return
Chain
;
}
unsigned
RetOpc
=
(
CallConv
==
CallingConv
::
AVR_INTR
||
CallConv
==
CallingConv
::
AVR_SIGNAL
)
AVRISD
::
RETI_FLAG
:
AVRISD
::
RET_FLAG
;
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
{
RetOps
.
push_back
(
Flag
)
;
}
return
DAG
.
getNode
(
RetOpc
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static bool sparc_use_pseudo_pic_reg ( void ) { return ! TARGET_VXWORKS_RTP && flag_pic ; } </s>


<s> void WebAssemblyPassConfig :: addIRPasses ( ) { addPass ( new CoalesceFeaturesAndStripAtomics ( & getWebAssemblyTargetMachine ( ) ) ) ; addPass ( createAtomicExpandPass ( ) ) ; addPass ( createWebAssemblyAddMissingPrototypes ( ) ) ; addPass ( createWebAssemblyLowerGlobalDtors ( ) ) ; addPass ( createWebAssemblyFixFunctionBitcasts ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createWebAssemblyOptimizeReturned ( ) ) ; if ( ! EnableEmException && TM -> Options . ExceptionModel == ExceptionHandling :: None ) { addPass ( createLowerInvokePass ( ) ) ; addPass ( createUnreachableBlockEliminationPass ( ) ) ; } if ( EnableEmException || EnableEmSjLj ) addPass ( createWebAssemblyLowerEmscriptenEHSjLj ( EnableEmException , EnableEmSjLj ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly


<s> unsigned RISCVTargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT == MVT :: f16 && Subtarget . hasStdExtF ( ) && ! Subtarget . hasStdExtZfhmin ( ) ) return 1 ; return TargetLowering :: getNumRegistersForCallingConv ( Context , CC , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s> MachineInstr * foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , ArrayRef < unsigned > Ops , MachineBasicBlock :: iterator InsertPt , MachineInstr * LoadMI ) const override { return nullptr ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineBlockFrequencyInfo > ( ) ; AU . addPreserved < MachineBlockFrequencyInfo > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < LiveIntervals > ( ) ; AU . addPreserved < SlotIndexes > ( ) ; AU . addPreserved < LiveIntervals > ( ) ; AU . addRequired < TargetLibraryInfoWrapperPass > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool Error ( SMLoc L , const Twine & Msg ) { return Parser . Error ( L , Msg ) ; } </s>

Return an error at the location L , with the message Msg .


Given the pattern ( X & ( C l > > / < < Y ) ) ==/ ! = 0 return true if it should be transformed into : ( ( X < < /l > > Y ) & C ) ==/ ! = 0 WARNING : if ' X ' is a constant , the fold may deadlock ! FIXME : we could avoid passing XC , but we ca n't use isConstOrConstSplat ( ) here because it can end up being not linked in .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( AFI -> getGlobalBaseReg ( ) == 0 ) return false ; const ARMTargetMachine * TM = static_cast < const ARMTargetMachine * > ( & MF . getTarget ( ) ) ; if ( TM -> getRelocationModel ( ) != Reloc :: PIC_ ) return false ; LLVMContext * Context = & MF . getFunction ( ) -> getContext ( ) ; unsigned ARMPCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = TM -> getSubtarget < ARMSubtarget > ( ) . isThumb ( ) ? 4 : 8 ; ARMConstantPoolValue * CPV = ARMConstantPoolSymbol :: Create ( * Context , "_GLOBAL_OFFSET_TABLE_" , ARMPCLabelIndex , PCAdj ) ; unsigned Align = TM -> getSubtargetImpl ( ) -> getDataLayout ( ) -> getPrefTypeAlignment ( Type :: getInt32PtrTy ( * Context ) ) ; unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned TempReg = MF . getRegInfo ( ) . createVirtualRegister ( & ARM :: rGPRRegClass ) ; unsigned Opc = TM -> getSubtarget < ARMSubtarget > ( ) . isThumb2 ( ) ? ARM :: t2LDRpci : ARM :: LDRcp ; const TargetInstrInfo & TII = * TM -> getSubtargetImpl ( ) -> getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , TempReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == ARM :: LDRcp ) MIB . addImm ( 0 ) ; AddDefaultPred ( MIB ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; Opc = TM -> getSubtarget < ARMSubtarget > ( ) . isThumb2 ( ) ? ARM :: tPICADD : ARM :: PICADD ; MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addReg ( TempReg ) . addImm ( ARMPCLabelIndex ) ; if ( Opc == ARM :: PICADD ) AddDefaultPred ( MIB ) ; return true ; } </s>

ARM ARM ARM 0 ARM ARM ARM ARM 4 8 ARM ARM "_GLOBAL_OFFSET_TABLE_" ARM ARM::rGPRRegClass ARM ARM::t2LDRpci ARM::LDRcp ARM::LDRcp 0 ARM ARM::tPICADD ARM::PICADD ARM ARM::PICADD


<s> int rs6000_loop_align ( rtx label ) { basic_block bb ; int ninsns ; if ( ! can_override_loop_align ) return align_loops_log ; bb = BLOCK_FOR_INSN ( label ) ; ninsns = num_loop_insns ( bb -> loop_father ) ; if ( ninsns > 4 && ninsns <= 8 && ( rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5 || rs6000_cpu == PROCESSOR_POWER6 || rs6000_cpu == PROCESSOR_POWER7 || rs6000_cpu == PROCESSOR_POWER8 ) ) return 5 ; else return align_loops_log ; } </s>


<s> void GCNPassConfig :: addPreEmitPass ( ) { addPass ( & PostRAHazardRecognizerID ) ; addPass ( createSIInsertWaitsPass ( ) ) ; addPass ( createSIShrinkInstructionsPass ( ) ) ; addPass ( createSILowerControlFlowPass ( ) , false ) ; addPass ( createSIDebuggerInsertNopsPass ( ) , false ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


"internal error: instruction without _e64 suffix "

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s>
static
void
rs6000_xcoff_file_start
(
void
)
{
rs6000_gen_section_name
(
&
xcoff_bss_section_name
,
main_input_filename
,
".bss_"
)
;
rs6000_gen_section_name
(
&
xcoff_private_data_section_name
,
main_input_filename
,
".rw_"
)
;
rs6000_gen_section_name
(
&
xcoff_private_rodata_section_name
,
main_input_filename
,
".rop_"
)
;
rs6000_gen_section_name
(
&
xcoff_read_only_section_name
,
main_input_filename
,
".ro_"
)
;
rs6000_gen_section_name
(
&
xcoff_tls_data_section_name
,
main_input_filename
,
".tls_"
)
;
fputs
(
"\t.file\t"
,
asm_out_file
)
;
output_quoted_string
(
asm_out_file
,
main_input_filename
)
;
fputc
(
'\n'
,
asm_out_file
)
;
if
(
write_symbols
!=
NO_DEBUG
)
switch_to_section
(
private_data_section
)
;
switch_to_section
(
toc_section
)
;
switch_to_section
(
text_section
)
;
if
(
profile_flag
)
fprintf
(
asm_out_file
,
"\t.extern %s\n"
,
RS6000_MCOUNT
)
;
rs6000_file_start
(
)
;
}
</s>

Output at beginning of assembler file . Initialize the section names for the RS/6000 at this point . Specify filename , including full path , to assembler . We want to go into the TOC section so at least one .toc will be emitted . Also , in order to output proper .bs/.es pairs , we need at least one static [ RW ] section emitted . Finally , declare mcount when profiling to make the assembler happy .


<s> int SystemZFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; FrameReg = RI -> getFrameRegister ( MF ) ; int64_t Offset = ( MFFrame . getObjectOffset ( FI ) + MFFrame . getOffsetAdjustment ( ) ) ; Offset -= getOffsetOfLocalArea ( ) ; Offset += getAllocatedStackSize ( MF ) ; return Offset ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> unsigned PPCRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( ! Subtarget . isPPC64 ( ) ) return TFI -> hasFP ( MF ) ? PPC :: R31 : PPC :: R1 ; else return TFI -> hasFP ( MF ) ? PPC :: X31 : PPC :: X1 ; } </s>


<s>
const
MCPhysReg
*
AArch64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
CFGuard_Check
)
return
CSR_Win_AArch64_CFGuard_Check_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetWindows
(
)
)
return
CSR_Win_AArch64_AAPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_AArch64_NoRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_AArch64_AllRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_VectorCall
)
return
CSR_AArch64_AAVPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
CXX_FAST_TLS
)
return
MF
->
getInfo
<
AArch64FunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_AArch64_CXX_TLS_Darwin_PE_SaveList
:
CSR_AArch64_CXX_TLS_Darwin_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
.
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_AArch64_AAPCS_SwiftError_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
PreserveMost
)
return
CSR_AArch64_RT_MostRegs_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetDarwin
(
)
)
return
CSR_Darwin_AArch64_AAPCS_SaveList
;
return
CSR_AArch64_AAPCS_SaveList
;
}
</s>


<s> bool systemSupportsUnalignedAccess ( ) const { return true ; } </s>

Does the system support unaligned memory access .


"alias without a base object is not yet supported on AIX"

Set up the AsmPrinter when we are working on a new module .


<s> unsigned getGlobalBaseReg ( ) const { return GlobalBaseReg ; } </s>


<s>
void
m32c_override_options
(
void
)
{
if
(
target_memregs_set
)
{
if
(
target_memregs
<
0
||
target_memregs
>
16
)
error
(
"invalid target memregs value '%d'"
,
target_memregs
)
;
}
else
target_memregs
=
"16"
;
}
</s>

Implements OVERRIDE_OPTIONS . We limit memregs to 0 .. 16 , and provide a default .


<s> EVT BlackfinTargetLowering :: getSetCCResultType ( EVT VT ) const { return MVT :: i32 ; } </s>

Return the value type to use for ISD : :SETCC .


<s> bool RISCVTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { switch ( Intrinsic ) { default : return false ; case Intrinsic :: riscv_masked_atomicrmw_xchg_i32 : case Intrinsic :: riscv_masked_atomicrmw_add_i32 : case Intrinsic :: riscv_masked_atomicrmw_sub_i32 : case Intrinsic :: riscv_masked_atomicrmw_nand_i32 : case Intrinsic :: riscv_masked_atomicrmw_max_i32 : case Intrinsic :: riscv_masked_atomicrmw_min_i32 : case Intrinsic :: riscv_masked_atomicrmw_umax_i32 : case Intrinsic :: riscv_masked_atomicrmw_umin_i32 : PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 0 ) -> getType ( ) ) ; Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: getVT ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . align = 4 ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; } } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> int iq2000_initial_elimination_offset ( int from , int to ATTRIBUTE_UNUSED ) { int offset ; compute_frame_size ( get_frame_size ( ) ) ; if ( ( from ) == FRAME_POINTER_REGNUM ) ( offset ) = 0 ; else if ( ( from ) == ARG_POINTER_REGNUM ) ( offset ) = ( cfun -> machine -> total_size ) ; else if ( ( from ) == RETURN_ADDRESS_POINTER_REGNUM ) { if ( leaf_function_p ( ) ) ( offset ) = 0 ; else ( offset ) = cfun -> machine -> gp_sp_offset + ( ( UNITS_PER_WORD - ( POINTER_SIZE / BITS_PER_UNIT ) ) * ( BYTES_BIG_ENDIAN != 0 ) ) ; } else gcc_unreachable ( ) ; return offset ; } </s>

Implement INITIAL_ELIMINATION_OFFSET . FROM is either the frame pointer , argument pointer , or return address pointer . TO is either the stack pointer or hard frame pointer .


<s> int hard_regno_mode_ok ( int regno , machine_mode mode ) { enum reg_class rclass = REGNO_REG_CLASS ( regno ) ; if ( mode == CCmode ) return 0 ; if ( mode == V2HImode ) return D_REGNO_P ( regno ) ; if ( rclass == CCREGS ) return mode == BImode ; if ( mode == PDImode || mode == V2PDImode ) return regno == REG_A0 || regno == REG_A1 ; if ( mode == DImode ) return regno < REG_M3 ; if ( mode == SImode && TEST_HARD_REG_BIT ( reg_class_contents [ PROLOGUE_REGS ] , regno ) ) return 1 ; return TEST_HARD_REG_BIT ( reg_class_contents [ MOST_REGS ] , regno ) ; } </s>

Value is 1 if hard register REGNO can hold a value of machine-mode MODE .


<s> void finishLayout ( MCAssembler const & Asm , MCAsmLayout & Layout ) const override { for ( auto I : Layout . getSectionOrder ( ) ) { auto & Fragments = I -> getFragmentList ( ) ; for ( auto & J : Fragments ) { switch ( J . getKind ( ) ) { default : break ; case MCFragment :: FT_Align : { auto Size = Asm . computeFragmentSize ( Layout , J ) ; for ( auto K = J . getIterator ( ) ; K != Fragments . begin ( ) && Size >= HEXAGON_PACKET_SIZE ; ) { -- K ; switch ( K -> getKind ( ) ) { default : break ; case MCFragment :: FT_Align : { Size = 0 ; break ; } case MCFragment :: FT_Relaxable : { MCContext & Context = Asm . getContext ( ) ; auto & RF = cast < MCRelaxableFragment > ( * K ) ; auto & Inst = const_cast < MCInst & > ( RF . getInst ( ) ) ; while ( Size > 0 && HexagonMCInstrInfo :: bundleSize ( Inst ) < MaxPacketSize ) { MCInst * Nop = new ( Context ) MCInst ; Nop -> setOpcode ( Hexagon :: A2_nop ) ; Inst . addOperand ( MCOperand :: createInst ( Nop ) ) ; Size -= 4 ; if ( ! HexagonMCChecker ( Context , * MCII , * RF . getSubtargetInfo ( ) , Inst , * Context . getRegisterInfo ( ) , false ) . check ( ) ) { Inst . erase ( Inst . end ( ) - 1 ) ; Size = 0 ; } } bool Error = HexagonMCShuffle ( Context , true , * MCII , * RF . getSubtargetInfo ( ) , Inst ) ; ( void ) Error ; ReplaceInstruction ( Asm . getEmitter ( ) , RF , Inst ) ; Layout . invalidateFragmentsFrom ( & RF ) ; Size = 0 ; break ; } } } } } } } } </s>

Give backend an opportunity to finish layout after relaxation .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addPreserved ( "stack-protector" ) ; AU . addPreserved < MachineFunctionAnalysis > ( ) ; } </s>


<s>
SDValue
FISCTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_FISC
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
8
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
<
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
FISCISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool X86ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { STI = & static_cast < const X86Subtarget & > ( MF . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; X86FL = STI -> getFrameLowering ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : MF ) Modified |= ExpandMBB ( MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool rip_relative_addr_p ( struct ix86_address * parts ) { rtx base , index , disp ; base = parts -> base ; index = parts -> index ; disp = parts -> disp ; if ( disp && ! base && ! index ) { if ( TARGET_64BIT ) { rtx symbol = disp ; if ( GET_CODE ( disp ) == CONST ) symbol = XEXP ( disp , 0 ) ; if ( GET_CODE ( symbol ) == PLUS && CONST_INT_P ( XEXP ( symbol , 1 ) ) ) symbol = XEXP ( symbol , 0 ) ; if ( GET_CODE ( symbol ) == LABEL_REF || ( GET_CODE ( symbol ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( symbol ) == 0 ) || ( GET_CODE ( symbol ) == UNSPEC && ( XINT ( symbol , 1 ) == UNSPEC_GOTPCREL || XINT ( symbol , 1 ) == UNSPEC_PCREL || XINT ( symbol , 1 ) == UNSPEC_GOTNTPOFF ) ) ) return true ; } } return false ; } </s>

Check whether x86 address PARTS is a pc-relative address .


<s> const MipsInstrInfo * getInstrInfo ( ) { return getTargetMachine ( ) . getInstrInfo ( ) ; } </s>


<s> static const char * detect_caches_intel ( bool xeon_mp , unsigned max_level , unsigned max_ext_level , unsigned * l2sizekb ) { struct cache_desc level1 = { 0 , 0 , 0 } , level2 = { 0 , 0 , 0 } , level3 = { 0 , 0 , 0 } ; if ( max_level >= 4 ) detect_caches_cpuid4 ( & level1 , & level2 , & level3 ) ; else if ( max_level >= 2 ) detect_caches_cpuid2 ( xeon_mp , & level1 , & level2 ) ; else return "" ; if ( level1 . sizekb == 0 ) return "" ; if ( level3 . sizekb ) level2 = level3 ; if ( level2 . sizekb == 0 && max_ext_level >= 0x80000006 ) detect_l2_cache ( & level2 ) ; * l2sizekb = level2 . sizekb ; return describe_cache ( level1 , level2 ) ; } </s>

Returns the description of caches for an Intel processor .


<s> bool RISCVInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { TBB = FBB = nullptr ; Cond . clear ( ) ; MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) || ! isUnpredicatedTerminator ( * I ) ) return false ; MachineBasicBlock :: iterator FirstUncondOrIndirectBr = MBB . end ( ) ; int NumTerminators = 0 ; for ( auto J = I . getReverse ( ) ; J != MBB . rend ( ) && isUnpredicatedTerminator ( * J ) ; J ++ ) { NumTerminators ++ ; if ( J -> getDesc ( ) . isUnconditionalBranch ( ) || J -> getDesc ( ) . isIndirectBranch ( ) ) { FirstUncondOrIndirectBr = J . getReverse ( ) ; } } if ( AllowModify && FirstUncondOrIndirectBr != MBB . end ( ) ) { while ( std :: next ( FirstUncondOrIndirectBr ) != MBB . end ( ) ) { std :: next ( FirstUncondOrIndirectBr ) -> eraseFromParent ( ) ; NumTerminators -- ; } I = FirstUncondOrIndirectBr ; } if ( I -> getDesc ( ) . isIndirectBranch ( ) ) return true ; if ( NumTerminators > 2 ) return true ; if ( NumTerminators == 1 && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { TBB = I -> getOperand ( 0 ) . getMBB ( ) ; return false ; } if ( NumTerminators == 1 && I -> getDesc ( ) . isConditionalBranch ( ) ) { parseCondBranch ( * I , TBB , Cond ) ; return false ; } if ( NumTerminators == 2 && std :: prev ( I ) -> getDesc ( ) . isConditionalBranch ( ) && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { parseCondBranch ( * std :: prev ( I ) , TBB , Cond ) ; FBB = I -> getOperand ( 0 ) . getMBB ( ) ; return false ; } return true ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s>
void
mmix_override_options
(
void
)
{
if
(
flag_pic
)
{
warning
(
0
,
"-f%s not supported: ignored"
,
(
flag_pic
>
1
)
"PIC"
:
"pic"
)
;
flag_pic
=
0
;
}
}
</s>


<s>
bool
AMDGPUAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MF
.
setAlignment
(
8
)
;
SetupMachineFunction
(
MF
)
;
EmitFunctionHeader
(
)
;
MCContext
&
Context
=
getObjFileLowering
(
)
.
getContext
(
)
;
const
MCSectionELF
*
ConfigSection
=
Context
.
getELFSection
(
".AMDGPU.config"
,
ELF
::
SHT_PROGBITS
,
0
)
;
OutStreamer
.
SwitchSection
(
ConfigSection
)
;
const
AMDGPUSubtarget
&
STM
=
TM
.
getSubtarget
<
AMDGPUSubtarget
>
(
)
;
SIProgramInfo
KernelInfo
;
if
(
STM
.
isAmdHsaOS
(
)
)
{
getSIProgramInfo
(
KernelInfo
,
MF
)
;
EmitAmdKernelCodeT
(
MF
,
KernelInfo
)
;
OutStreamer
.
EmitCodeAlignment
(
2
<<
(
MF
.
getAlignment
(
)
1
)
)
;
}
else
if
(
STM
.
getGeneration
(
)
>=
AMDGPUSubtarget
::
SOUTHERN_ISLANDS
)
{
getSIProgramInfo
(
KernelInfo
,
MF
)
;
EmitProgramInfoSI
(
MF
,
KernelInfo
)
;
}
else
{
EmitProgramInfoR600
(
MF
)
;
}
DisasmLines
.
clear
(
)
;
HexLines
.
clear
(
)
;
DisasmLineMaxLen
=
0
;
OutStreamer
.
SwitchSection
(
getObjFileLowering
(
)
.
getTextSection
(
)
)
;
EmitFunctionBody
(
)
;
if
(
isVerbose
(
)
)
{
const
MCSectionELF
*
CommentSection
=
Context
.
getELFSection
(
".AMDGPU.csdata"
,
ELF
::
SHT_PROGBITS
,
0
)
;
OutStreamer
.
SwitchSection
(
CommentSection
)
;
if
(
STM
.
getGeneration
(
)
>=
AMDGPUSubtarget
::
SOUTHERN_ISLANDS
)
{
OutStreamer
.
emitRawComment
(
" Kernel info:"
,
false
)
;
OutStreamer
.
emitRawComment
(
" codeLenInByte = "
+
Twine
(
KernelInfo
.
CodeLen
)
,
false
)
;
OutStreamer
.
emitRawComment
(
" NumSgprs: "
+
Twine
(
KernelInfo
.
NumSGPR
)
,
false
)
;
OutStreamer
.
emitRawComment
(
" NumVgprs: "
+
Twine
(
KernelInfo
.
NumVGPR
)
,
false
)
;
OutStreamer
.
emitRawComment
(
" FloatMode: "
+
Twine
(
KernelInfo
.
FloatMode
)
,
false
)
;
OutStreamer
.
emitRawComment
(
" IeeeMode: "
+
Twine
(
KernelInfo
.
IEEEMode
)
,
false
)
;
OutStreamer
.
emitRawComment
(
" ScratchSize: "
+
Twine
(
KernelInfo
.
ScratchSize
)
,
false
)
;
}
else
{
R600MachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
R600MachineFunctionInfo
>
(
)
;
OutStreamer
.
emitRawComment
(
Twine
(
"SQ_PGM_RESOURCES:STACK_SIZE = "
+
Twine
(
MFI
->
StackSize
)
)
)
;
}
}
if
(
STM
.
dumpCode
(
)
&&
DisasmEnabled
)
{
OutStreamer
.
SwitchSection
(
Context
.
getELFSection
(
".AMDGPU.disasm"
,
ELF
::
SHT_NOTE
,
0
)
)
;
for
(
size_t
i
=
0
;
i
<
DisasmLines
.
size
(
)
;
++
i
)
{
std
::
string
Comment
(
DisasmLineMaxLen
DisasmLines
[
i
]
.
size
(
)
,
' '
)
;
Comment
+=
" ; "
+
HexLines
[
i
]
+
"\n"
;
OutStreamer
.
EmitBytes
(
StringRef
(
DisasmLines
[
i
]
)
)
;
OutStreamer
.
EmitBytes
(
StringRef
(
Comment
)
)
;
}
}
return
false
;
}
</s>


<s> Candidate ( MachineInstr * mi , unsigned reg , unsigned subreg , unsigned freebanks , unsigned weight ) : MI ( mi ) , Reg ( reg ) , SubReg ( subreg ) , FreeBanks ( freebanks ) , Weight ( weight ) { } </s>


<s> bool RISCVPassConfig :: addInstSelector ( ) { addPass ( createRISCVISelDag ( getRISCVTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void ARMELFStreamer :: Reset ( ) { ExTab = NULL ; FnStart = NULL ; Personality = NULL ; PersonalityIndex = NUM_PERSONALITY_INDEX ; FPReg = ARM :: SP ; FPOffset = 0 ; SPOffset = 0 ; PendingOffset = 0 ; UsedFP = false ; CantUnwind = false ; Opcodes . clear ( ) ; UnwindOpAsm . Reset ( ) ; } </s>


<s> StringRef getPassName ( ) const override { return PULP_HWLOOPS_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> int frv_emit_cond_move ( rtx dest , rtx test_rtx , rtx src1 , rtx src2 ) { rtx set ; rtx clobber_cc ; rtx test2 ; rtx cr_reg ; rtx if_rtx ; enum rtx_code test = GET_CODE ( test_rtx ) ; rtx cc_reg = frv_emit_comparison ( test , XEXP ( test_rtx , 0 ) , XEXP ( test_rtx , 1 ) ) ; machine_mode cc_mode = GET_MODE ( cc_reg ) ; if ( GET_CODE ( src1 ) == CONST_INT && GET_CODE ( src2 ) == CONST_INT ) { HOST_WIDE_INT value1 = INTVAL ( src1 ) ; HOST_WIDE_INT value2 = INTVAL ( src2 ) ; if ( value1 == 0 || value2 == 0 ) ; else if ( IN_RANGE ( value1 , - 2048 , 2047 ) && IN_RANGE ( value2 - value1 , - 2048 , 2047 ) ) ; else { src1 = force_reg ( GET_MODE ( dest ) , src1 ) ; src2 = force_reg ( GET_MODE ( dest ) , src2 ) ; } } else { if ( GET_CODE ( src1 ) == CONST_INT && INTVAL ( src1 ) != 0 ) src1 = force_reg ( GET_MODE ( dest ) , src1 ) ; if ( GET_CODE ( src2 ) == CONST_INT && INTVAL ( src2 ) != 0 ) src2 = force_reg ( GET_MODE ( dest ) , src2 ) ; } test2 = gen_rtx_fmt_ee ( test , cc_mode , cc_reg , const0_rtx ) ; if_rtx = gen_rtx_IF_THEN_ELSE ( GET_MODE ( dest ) , test2 , src1 , src2 ) ; set = gen_rtx_SET ( VOIDmode , dest , if_rtx ) ; cr_reg = ( ( TARGET_ALLOC_CC ) ? gen_reg_rtx ( CC_CCRmode ) : gen_rtx_REG ( CC_CCRmode , ( cc_mode == CC_FPmode ) ? FCR_FIRST : ICR_FIRST ) ) ; clobber_cc = gen_rtx_CLOBBER ( VOIDmode , cr_reg ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set , clobber_cc ) ) ) ; return TRUE ; } </s>

Emit the code for a conditional move , return TRUE if we could do the move .


Create the va_list data type . We keep 3 pointers , and two offsets . Two pointers are to the overflow area , which starts at the CFA . One of these is constant , for addressing into the GPR save area below it . The other is advanced up the stack through the overflow region . The third pointer is to the GPR save area . Since the FPR save area is just below it , we can address FPR slots off this pointer . We also keep two one-byte offsets , which are to be subtracted from the constant pointers to yield addresses in the GPR and FPR save areas . These are downcounted as float or non-float arguments are used , and when they get to zero , the argument must be obtained from the overflow region . If ! EABI_FLOAT_VARARGS_P , then no FPR save area exists , and a single pointer is enough . It 's started at the GPR save area , and is advanced , period . Note that the GPR save area is not constant size , due to optimization in the prologue . Hence , we ca n't use a design with two pointers and two offsets , although we could have designed this with two pointers and three offsets .


<s> bool mips_dangerous_for_la25_p ( rtx x ) { return ( ! TARGET_EXPLICIT_RELOCS && TARGET_USE_GOT && GET_CODE ( x ) == SYMBOL_REF && mips_global_symbol_p ( x ) ) ; } </s>

Return true if X should not be moved directly into register $ 25 . We need this because many versions of GAS will treat `` la $ 25 , foo '' as part of a call sequence and so allow a global `` foo '' to be lazily bound .


<s> bool AArch64_MC :: isQForm ( const MCInst & MI , const MCInstrInfo * MCII ) { const auto & FPR128 = AArch64MCRegisterClasses [ AArch64 :: FPR128RegClassID ] ; return llvm :: any_of ( MI , [ & ] ( const MCOperand & Op ) { return Op . isReg ( ) && FPR128 . contains ( Op . getReg ( ) ) ; } ) ; } </s>

Returns whether the instruction is in Q form ( 128 bit operands )


<s> void ARMTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , APInt & KnownZero , APInt & KnownOne , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { unsigned BitWidth = KnownOne . getBitWidth ( ) ; KnownZero = KnownOne = APInt ( BitWidth , 0 ) ; switch ( Op . getOpcode ( ) ) { default : break ; case ARMISD :: ADDC : case ARMISD :: ADDE : case ARMISD :: SUBC : case ARMISD :: SUBE : if ( Op . getResNo ( ) == 0 ) break ; KnownZero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - 1 ) ; break ; case ARMISD :: CMOV : { DAG . computeKnownBits ( Op . getOperand ( 0 ) , KnownZero , KnownOne , Depth + 1 ) ; if ( KnownZero == 0 && KnownOne == 0 ) return ; APInt KnownZeroRHS , KnownOneRHS ; DAG . computeKnownBits ( Op . getOperand ( 1 ) , KnownZeroRHS , KnownOneRHS , Depth + 1 ) ; KnownZero &= KnownZeroRHS ; KnownOne &= KnownOneRHS ; return ; } case ISD :: INTRINSIC_W_CHAIN : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ; Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case Intrinsic :: arm_ldaex : case Intrinsic :: arm_ldrex : { EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; KnownZero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } } } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> void VideoCore4InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = * MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; BuildMI ( MBB , I , DL , get ( VideoCore4 :: MEM32_ST_LI ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


"PPC hazards don't support scoreboard lookahead"

getHazardType - Return the hazard type of emitting this node .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( AFI -> getGlobalBaseReg ( ) == 0 ) return false ; const ARMSubtarget & STI = static_cast < const ARMSubtarget & > ( MF . getSubtarget ( ) ) ; if ( STI . isThumb1Only ( ) ) return false ; const TargetMachine & TM = MF . getTarget ( ) ; if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) return false ; LLVMContext * Context = & MF . getFunction ( ) -> getContext ( ) ; unsigned ARMPCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = STI . isThumb ( ) ? 4 : 8 ; ARMConstantPoolValue * CPV = ARMConstantPoolSymbol :: Create ( * Context , "_GLOBAL_OFFSET_TABLE_" , ARMPCLabelIndex , PCAdj ) ; unsigned Align = MF . getDataLayout ( ) . getPrefTypeAlignment ( Type :: getInt32PtrTy ( * Context ) ) ; unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned TempReg = MF . getRegInfo ( ) . createVirtualRegister ( & ARM :: rGPRRegClass ) ; unsigned Opc = STI . isThumb2 ( ) ? ARM :: t2LDRpci : ARM :: LDRcp ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , TempReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == ARM :: LDRcp ) MIB . addImm ( 0 ) ; AddDefaultPred ( MIB ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; Opc = STI . isThumb2 ( ) ? ARM :: tPICADD : ARM :: PICADD ; MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addReg ( TempReg ) . addImm ( ARMPCLabelIndex ) ; if ( Opc == ARM :: PICADD ) AddDefaultPred ( MIB ) ; return true ; } </s>

ARM ARM ARM 0 ARM ARM ARM 4 8 ARM ARM "_GLOBAL_OFFSET_TABLE_" ARM ARM::rGPRRegClass ARM::t2LDRpci ARM::LDRcp ARM::LDRcp 0 ARM::tPICADD ARM::PICADD ARM ARM::PICADD


<s> virtual MVT getScalarShiftAmountTy ( EVT LHSTy ) const { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s>
void
WebAssemblyAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"EmitInstruction: "
<<
*
MI
<<
'\n'
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
WebAssembly
::
ARGUMENT_I32
:
case
WebAssembly
::
ARGUMENT_I64
:
case
WebAssembly
::
ARGUMENT_F32
:
case
WebAssembly
::
ARGUMENT_F64
:
case
WebAssembly
::
ARGUMENT_v16i8
:
case
WebAssembly
::
ARGUMENT_v8i16
:
case
WebAssembly
::
ARGUMENT_v4i32
:
case
WebAssembly
::
ARGUMENT_v4f32
:
break
;
case
WebAssembly
::
FALLTHROUGH_RETURN_I32
:
case
WebAssembly
::
FALLTHROUGH_RETURN_I64
:
case
WebAssembly
::
FALLTHROUGH_RETURN_F32
:
case
WebAssembly
::
FALLTHROUGH_RETURN_F64
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v16i8
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v8i16
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v4i32
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v4f32
:
{
assert
(
MFI
->
isVRegStackified
(
MI
->
getOperand
(
0
)
.
getReg
(
)
)
)
;
if
(
isVerbose
(
)
)
{
OutStreamer
->
AddComment
(
"fallthrough-return: $pop"
+
Twine
(
MFI
->
getWARegStackId
(
MFI
->
getWAReg
(
MI
->
getOperand
(
0
)
.
getReg
(
)
)
)
)
)
;
OutStreamer
->
AddBlankLine
(
)
;
}
break
;
}
case
WebAssembly
::
FALLTHROUGH_RETURN_VOID
:
if
(
isVerbose
(
)
)
{
OutStreamer
->
AddComment
(
"fallthrough-return"
)
;
OutStreamer
->
AddBlankLine
(
)
;
}
break
;
default
:
{
WebAssemblyMCInstLower
MCInstLowering
(
OutContext
,
*
this
)
;
MCInst
TmpInst
;
MCInstLowering
.
Lower
(
MI
,
TmpInst
)
;
EmitToStreamer
(
*
OutStreamer
,
TmpInst
)
;
break
;
}
}
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static std :: unique_ptr < TPCOperand > CreateReg ( unsigned RegNo , int RegClassNo , SMLoc StartLoc , SMLoc EndLoc ) { auto Res = std :: make_unique < TPCOperand > ( OpKind :: Reg , StartLoc , EndLoc ) ; Res -> Reg . Num = RegNo ; Res -> Reg . Class = RegClassNo ; return Res ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> const char * mips_output_sync ( void ) { mips_start_ll_sc_sync_block ( ) ; output_asm_insn ( "sync" , 0 ) ; mips_end_ll_sc_sync_block ( ) ; return "" ; } </s>

Output and/or return the asm template for a sync instruction .


<s> static inline unsigned long ia64_rse_is_rnat_slot ( unsigned long * addr ) { return ia64_rse_slot_num ( addr ) == 0x3f ; } </s>

Return TRUE if ADDR is the address of an RNAT slot .


<s> bool isTarget64BitILP32 ( ) const { return In64BitMode && ( TargetTriple . getEnvironment ( ) == Triple :: GNUX32 ) ; } </s>

Is this x86_64 with the ILP32 programming model ( x32 ABI ) ?


<s> rtx expand ( function_expander & e ) const override { return e . use_exact_insn ( CODE_FOR_aarch64_wrffr ) ; } </s>


<s> void NVPTXTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { if ( Constraint . length ( ) > 1 ) return ; else TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; } </s>

Lower the specified operand into the Ops vector .


<s> static void sparc_emit_set_const64_longway ( rtx op0 , rtx temp , unsigned HOST_WIDE_INT high_bits , unsigned HOST_WIDE_INT low_bits ) { rtx sub_temp = op0 ; if ( can_create_pseudo_p ( ) ) sub_temp = gen_reg_rtx ( DImode ) ; if ( ( high_bits & 0xfffffc00 ) != 0 ) { emit_insn ( gen_safe_HIGH64 ( temp , high_bits ) ) ; if ( ( high_bits & ~ 0xfffffc00 ) != 0 ) emit_insn ( gen_rtx_SET ( VOIDmode , sub_temp , gen_safe_OR64 ( temp , ( high_bits & 0x3ff ) ) ) ) ; else sub_temp = temp ; } else { emit_insn ( gen_safe_SET64 ( temp , high_bits ) ) ; sub_temp = temp ; } if ( can_create_pseudo_p ( ) ) { rtx temp2 = gen_reg_rtx ( DImode ) ; rtx temp3 = gen_reg_rtx ( DImode ) ; rtx temp4 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , temp4 , gen_rtx_ASHIFT ( DImode , sub_temp , GEN_INT ( 32 ) ) ) ) ; emit_insn ( gen_safe_HIGH64 ( temp2 , low_bits ) ) ; if ( ( low_bits & ~ 0xfffffc00 ) != 0 ) { emit_insn ( gen_rtx_SET ( VOIDmode , temp3 , gen_safe_OR64 ( temp2 , ( low_bits & 0x3ff ) ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_PLUS ( DImode , temp4 , temp3 ) ) ) ; } else { emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_PLUS ( DImode , temp4 , temp2 ) ) ) ; } } else { rtx low1 = GEN_INT ( ( low_bits >> ( 32 - 12 ) ) & 0xfff ) ; rtx low2 = GEN_INT ( ( low_bits >> ( 32 - 12 - 12 ) ) & 0xfff ) ; rtx low3 = GEN_INT ( ( low_bits >> ( 32 - 12 - 12 - 8 ) ) & 0x0ff ) ; int to_shift = 12 ; if ( low1 != const0_rtx ) { emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_ASHIFT ( DImode , sub_temp , GEN_INT ( to_shift ) ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_IOR ( DImode , op0 , low1 ) ) ) ; sub_temp = op0 ; to_shift = 12 ; } else { to_shift += 12 ; } if ( low2 != const0_rtx ) { emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_ASHIFT ( DImode , sub_temp , GEN_INT ( to_shift ) ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_IOR ( DImode , op0 , low2 ) ) ) ; sub_temp = op0 ; to_shift = 8 ; } else { to_shift += 8 ; } emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_ASHIFT ( DImode , sub_temp , GEN_INT ( to_shift ) ) ) ) ; if ( low3 != const0_rtx ) emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_IOR ( DImode , op0 , low3 ) ) ) ; } } </s>

Full 64-bit constant decomposition . Even though this is the 'worst ' case , we still optimize a few things away .


"getIntImmCost can only estimate cost of materialising integers"

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> static bool is_store_insn1 ( rtx pat , rtx * str_mem ) { if ( ! pat || pat == NULL_RTX ) return false ; if ( GET_CODE ( pat ) == SET ) { if ( REG_P ( SET_SRC ( pat ) ) || SUBREG_P ( SET_SRC ( pat ) ) ) return find_mem_ref ( SET_DEST ( pat ) , str_mem ) ; else return false ; } if ( GET_CODE ( pat ) == PARALLEL ) { int i ; for ( i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) if ( is_store_insn1 ( XVECEXP ( pat , 0 , i ) , str_mem ) ) return true ; } return false ; } </s>

Determine if PAT is a PATTERN of a store insn .


<s> static tree va_list_skip_additions ( tree lhs ) { tree rhs , stmt ; if ( TREE_CODE ( lhs ) != SSA_NAME ) return lhs ; for ( ; ; ) { stmt = SSA_NAME_DEF_STMT ( lhs ) ; if ( TREE_CODE ( stmt ) == PHI_NODE ) return stmt ; if ( TREE_CODE ( stmt ) != MODIFY_EXPR || TREE_OPERAND ( stmt , 0 ) != lhs ) return lhs ; rhs = TREE_OPERAND ( stmt , 1 ) ; if ( TREE_CODE ( rhs ) == WITH_SIZE_EXPR ) rhs = TREE_OPERAND ( rhs , 0 ) ; if ( ( TREE_CODE ( rhs ) != NOP_EXPR && TREE_CODE ( rhs ) != CONVERT_EXPR && ( TREE_CODE ( rhs ) != PLUS_EXPR || TREE_CODE ( TREE_OPERAND ( rhs , 1 ) ) != INTEGER_CST || ! host_integerp ( TREE_OPERAND ( rhs , 1 ) , 1 ) ) ) || TREE_CODE ( TREE_OPERAND ( rhs , 0 ) ) != SSA_NAME ) return rhs ; lhs = TREE_OPERAND ( rhs , 0 ) ; } } </s>

Helper function for alpha_stdarg_optimize_hook . Skip over casts and constant additions .


<s> int direct_return ( void ) { if ( reload_completed ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; if ( info -> first_gp_reg_save == 32 && info -> first_fp_reg_save == 64 && info -> first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1 && ! info -> lr_save_p && ! info -> cr_save_p && info -> vrsave_size == 0 && ! info -> push_p ) return 1 ; } return 0 ; } </s>

Return non-zero if this function is known to have a null epilogue .


<s> inline static rtx_insn * emit_set_insn ( rtx x , rtx y ) { return emit_insn ( gen_rtx_SET ( VOIDmode , x , y ) ) ; } </s>

Emit an insn that 's a simple single-set . Both the operands must be known to be valid .


<s> const uint32_t * Z80RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CallConv ) const { return CSR_16_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
static
void
rs6000_file_start
(
void
)
{
char
buffer
[
80
]
;
const
char
*
start
=
buffer
;
FILE
*
file
=
asm_out_file
;
rs6000_default_cpu
=
TARGET_CPU_DEFAULT
;
default_file_start
(
)
;
if
(
flag_verbose_asm
)
{
sprintf
(
buffer
,
"\n%s rs6000/powerpc options:"
,
ASM_COMMENT_START
)
;
if
(
rs6000_default_cpu
!=
0
&&
rs6000_default_cpu
[
0
]
!=
'\0'
)
{
fprintf
(
file
,
"%s --with-cpu=%s"
,
start
,
rs6000_default_cpu
)
;
start
=
""
;
}
if
(
OPTION_SET_P
(
rs6000_cpu_index
)
)
{
fprintf
(
file
,
"%s -mcpu=%s"
,
start
,
processor_target_table
[
rs6000_cpu_index
]
.
name
)
;
start
=
""
;
}
if
(
OPTION_SET_P
(
rs6000_tune_index
)
)
{
fprintf
(
file
,
"%s -mtune=%s"
,
start
,
processor_target_table
[
rs6000_tune_index
]
.
name
)
;
start
=
""
;
}
if
(
PPC405_ERRATUM77
)
{
fprintf
(
file
,
"%s PPC405CR_ERRATUM77"
,
start
)
;
start
=
""
;
}
switch
(
rs6000_sdata
)
{
case
SDATA_NONE
:
fprintf
(
file
,
"%s -msdata=none"
,
start
)
;
start
=
""
;
break
;
case
SDATA_DATA
:
fprintf
(
file
,
"%s -msdata=data"
,
start
)
;
start
=
""
;
break
;
case
SDATA_SYSV
:
fprintf
(
file
,
"%s -msdata=sysv"
,
start
)
;
start
=
""
;
break
;
case
SDATA_EABI
:
fprintf
(
file
,
"%s -msdata=eabi"
,
start
)
;
start
=
""
;
break
;
}
if
(
rs6000_sdata
&&
g_switch_value
)
{
fprintf
(
file
,
"%s -G %d"
,
start
,
g_switch_value
)
;
start
=
""
;
}
if
(
*
start
==
'\0'
)
putc
(
'\n'
,
file
)
;
}
rs6000_machine
=
rs6000_machine_from_flags
(
)
;
emit_asm_machine
(
)
;
if
(
DEFAULT_ABI
==
ABI_ELFv2
)
fprintf
(
file
,
"\t.abiversion 2\n"
)
;
}
</s>

Do anything needed at the start of the asm file .

rs6000
80
"\n%s rs6000/powerpc options:"
0
0
"%s --with-cpu=%s"
""
"%s -mcpu=%s"
""
"%s -mtune=%s"
""
"%s PPC405CR_ERRATUM77"
""
"%s -msdata=none"
""
"%s -msdata=data"
""
"%s -msdata=sysv"
""
"%s -msdata=eabi"
""
"%s -G %d"
""
"\t.abiversion 2\n"


"-mdiv requires -march to subsume the %<M%> extension"

"requested ABI requires -march to subsume the %qc extension"


<s> bool ix86_force_load_from_GOT_p ( rtx x ) { return ( ( TARGET_64BIT || ( ! flag_pic && HAVE_AS_IX86_GOT32X ) ) && ! TARGET_PECOFF && ! TARGET_MACHO && ( ! flag_pic || this_is_asm_operands ) && ix86_cmodel != CM_LARGE && ix86_cmodel != CM_LARGE_PIC && GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( x ) && ( ! flag_plt || ( SYMBOL_REF_DECL ( x ) && lookup_attribute ( "noplt" , DECL_ATTRIBUTES ( SYMBOL_REF_DECL ( x ) ) ) ) ) && ! SYMBOL_REF_LOCAL_P ( x ) ) ; } </s>

True if the function symbol operand X should be loaded from GOT . NB : In 32-bit mode , only non-PIC is allowed in inline assembly statements , since a PIC register could not be available at the call site .


<s> const MipsFrameLowering * MipsFrameLowering :: create ( MipsTargetMachine & TM , const MipsSubtarget & ST ) { if ( TM . getSubtargetImpl ( ) -> inMips16Mode ( ) ) return llvm :: createMips16FrameLowering ( ST ) ; return llvm :: createMipsSEFrameLowering ( ST ) ; } </s>


<s> static unsigned int mips_seq_time ( struct mips_sim * state , rtx_insn * seq ) { mips_sim_reset ( state ) ; for ( rtx_insn * insn = seq ; insn ; insn = NEXT_INSN ( insn ) ) { mips_sim_wait_insn ( state , insn ) ; mips_sim_issue_insn ( state , insn ) ; } return state -> time ; } </s>

Use simulator state STATE to calculate the execution time of instruction sequence SEQ .


Return a function that will generate a load of mode MODE_NO with speculation types TS .


"reverse ARM hazard checking unsupported"

RecedeCycle - This callback is invoked whenever the next bottom-up instruction to be scheduled can not issue in the current cycle , either because of latency or resource conflicts .


<s> static bool avr_decl_maybe_lds_p ( tree node ) { if ( ! node || TREE_CODE ( node ) != VAR_DECL || DECL_SECTION_NAME ( node ) != NULL ) return false ; if ( TREE_READONLY ( node ) ) return false ; do node = TREE_TYPE ( node ) ; while ( ARRAY_TYPE == TREE_CODE ( node ) ) ; return ( node != error_mark_node && ! TYPE_READONLY ( node ) ) ; } </s>

A helper for the next function . NODE is a decl that is associated with a symbol . Return TRUE if the respective object may be accessed by LDS . There might still be other reasons for why LDS is not appropriate . This function is only appropriate for AVR_TINY .


<s> TargetLoweringBase :: AtomicExpansionKind AArch64TargetLowering :: shouldExpandAtomicStoreInIR ( StoreInst * SI ) const { unsigned Size = SI -> getValueOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size != 128 || isOpSuitableForLDPSTP ( SI ) ) return AtomicExpansionKind :: None ; return AtomicExpansionKind :: Expand ; } </s>

Returns how the given ( atomic ) store should be expanded by the IR-level AtomicExpand pass into .


<s>
static
void
rs6000_sched_finish
(
FILE
*
dump
,
int
sched_verbose
)
{
int
n_groups
;
if
(
sched_verbose
)
fprintf
(
dump
,
"=== Finishing schedule.\n"
)
;
if
(
reload_completed
&&
rs6000_sched_groups
)
{
if
(
rs6000_sched_insert_nops
==
sched_finish_none
)
return
;
if
(
rs6000_sched_insert_nops
==
sched_finish_pad_groups
)
n_groups
=
pad_groups
(
dump
,
sched_verbose
,
current_sched_info
->
prev_head
,
current_sched_info
->
next_tail
)
;
else
n_groups
=
redefine_groups
(
dump
,
sched_verbose
,
current_sched_info
->
prev_head
,
current_sched_info
->
next_tail
)
;
if
(
sched_verbose
>=
6
)
{
fprintf
(
dump
,
"ngroups = %d\n"
,
n_groups
)
;
print_rtl
(
dump
,
current_sched_info
->
prev_head
)
;
fprintf
(
dump
,
"Done finish_sched\n"
)
;
}
}
}
</s>

The following function is called at the end of scheduling BB . After reload , it inserts nops at insn group bundling .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
]
=
{
{
"reloc_pcrel_4byte"
,
0
,
4
*
8
}
,
{
"reloc_pcrel_1byte"
,
0
,
1
*
8
}
,
{
"reloc_riprel_4byte"
,
0
,
4
*
8
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCCodeEmitter
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> int csky_compute_pushpop_length ( rtx * operands ) { rtx parallel_op = operands [ 2 ] ; unsigned indx = XVECLEN ( parallel_op , 0 ) - 1 ; unsigned first_indx = 0 ; unsigned regno = REGNO ( operands [ 1 ] ) ; if ( regno > CSKY_LR_REGNUM ) return 4 ; for ( ; indx > first_indx ; indx -- ) { regno = REGNO ( XEXP ( XVECEXP ( parallel_op , 0 , indx ) , 0 ) ) ; if ( regno > CSKY_LR_REGNUM ) return 4 ; } return 2 ; } </s>

Compute the attribute `` length '' of push or pop insn , according to the registers it uses .


<s> bool easy_altivec_constant ( rtx op , machine_mode mode ) { unsigned step , copies ; if ( mode == VOIDmode ) mode = GET_MODE ( op ) ; else if ( mode != GET_MODE ( op ) ) return false ; if ( mode == V2DFmode ) return zero_constant ( op , mode ) ; else if ( mode == V2DImode ) { if ( GET_CODE ( CONST_VECTOR_ELT ( op , 0 ) ) != CONST_INT || GET_CODE ( CONST_VECTOR_ELT ( op , 1 ) ) != CONST_INT ) return false ; if ( zero_constant ( op , mode ) ) return true ; if ( INTVAL ( CONST_VECTOR_ELT ( op , 0 ) ) == - 1 && INTVAL ( CONST_VECTOR_ELT ( op , 1 ) ) == - 1 ) return true ; return false ; } else if ( mode == V1TImode ) return false ; step = GET_MODE_NUNITS ( mode ) / 4 ; copies = 1 ; if ( vspltis_constant ( op , step , copies ) ) return true ; if ( step == 1 ) copies <<= 1 ; else step >>= 1 ; if ( vspltis_constant ( op , step , copies ) ) return true ; if ( step == 1 ) copies <<= 1 ; else step >>= 1 ; if ( vspltis_constant ( op , step , copies ) ) return true ; return false ; } </s>

Return true if OP is of the given MODE and can be synthesized with a vspltisb , vspltish or vspltisw .


"can't use non gp relative absolute address"

A C compound statement to output to stdio stream STREAM the assembler syntax for an instruction operand that is a memory reference whose address is ADDR . ADDR is an RTL expression . On some machines , the syntax for a symbolic address depends on the section that the address refers to . On these machines , define the macro ` ENCODE_SECTION_INFO ' to store the information into the ` symbol_ref ' , and then check for it here .


<s> void SystemZMCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; uint64_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; unsigned Size = MCII . get ( MI . getOpcode ( ) ) . getSize ( ) ; unsigned ShiftValue = ( Size * 8 ) - 8 ; for ( unsigned I = 0 ; I != Size ; ++ I ) { OS << uint8_t ( Bits >> ShiftValue ) ; ShiftValue -= 8 ; } } </s>

Encode the given Inst to bytes and append to CB .


<s> virtual const TargetRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool HexagonGenMux :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; HII = MF . getSubtarget < HexagonSubtarget > ( ) . getInstrInfo ( ) ; HRI = MF . getSubtarget < HexagonSubtarget > ( ) . getRegisterInfo ( ) ; bool Changed = false ; for ( auto & I : MF ) Changed |= genMuxInBlock ( I ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> unsigned OutgoingValueHandler :: getStackAddress ( const CCValAssign & VA , MachineMemOperand * & MMO ) { LLT p0 = LLT :: pointer ( 0 , 32 ) ; LLT s32 = LLT :: scalar ( 32 ) ; unsigned SPReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildCopy ( SPReg , Mips :: SP ) ; unsigned OffsetReg = MRI . createGenericVirtualRegister ( s32 ) ; unsigned Offset = VA . getLocMemOffset ( ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildGEP ( AddrReg , SPReg , OffsetReg ) ; MachinePointerInfo MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ; unsigned Size = alignTo ( VA . getValVT ( ) . getSizeInBits ( ) , 8 ) / 8 ; MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , 0 ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> bool X86TargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { if ( ! CI -> isTailCall ( ) || getTargetMachine ( ) . Options . DisableTailCalls ) return false ; CallSite CS ( CI ) ; CallingConv :: ID CalleeCC = CS . getCallingConv ( ) ; if ( ! IsTailCallConvention ( CalleeCC ) && CalleeCC != CallingConv :: C ) return false ; return true ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> bool HexagonInstrInfo :: isDuplexPair ( const MachineInstr & MIa , const MachineInstr & MIb ) const { HexagonII :: SubInstructionGroup MIaG = getDuplexCandidateGroup ( MIa ) ; HexagonII :: SubInstructionGroup MIbG = getDuplexCandidateGroup ( MIb ) ; return ( isDuplexPairMatch ( MIaG , MIbG ) || isDuplexPairMatch ( MIbG , MIaG ) ) ; } </s>

Symmetrical . See if these two instructions are fit for duplex pair .

Hexagon Hexagon HexagonII::SubInstructionGroup HexagonII::SubInstructionGroup


Return an array that contains the direct target flag values and their names .

Hexagon Hexagon Hexagon "hexagon-pcrel" "hexagon-got" "hexagon-lo16" "hexagon-hi16" "hexagon-gprel" "hexagon-gdgot" "hexagon-gdplt" "hexagon-ie" "hexagon-iegot" "hexagon-tprel"


<s> rtx_code m68k_find_flags_value ( rtx op0 , rtx op1 , rtx_code code ) { if ( flags_compare_op0 != NULL_RTX ) { if ( rtx_equal_p ( op0 , flags_compare_op0 ) && rtx_equal_p ( op1 , flags_compare_op1 ) ) return code ; if ( rtx_equal_p ( op0 , flags_compare_op1 ) && rtx_equal_p ( op1 , flags_compare_op0 ) ) return swap_condition ( code ) ; return UNKNOWN ; } machine_mode mode = GET_MODE ( op0 ) ; if ( op1 != CONST0_RTX ( mode ) ) return UNKNOWN ; gcc_assert ( code != LTU && code != GEU ) ; if ( flags_valid == FLAGS_VALID_NOOV && ( code == GT || code == LE ) ) return UNKNOWN ; if ( rtx_equal_p ( flags_operand1 , op0 ) || rtx_equal_p ( flags_operand2 , op0 ) ) return ( FLOAT_MODE_P ( mode ) ? code : code == GE ? PLUS : code == LT ? MINUS : code ) ; if ( code != GE && code != LT ) return UNKNOWN ; if ( mode == SImode && flags_operand1 != NULL_RTX && GET_MODE ( flags_operand1 ) == DImode && REG_P ( flags_operand1 ) && REG_P ( op0 ) && hard_regno_nregs ( REGNO ( flags_operand1 ) , DImode ) == 2 && REGNO ( flags_operand1 ) == REGNO ( op0 ) ) return code == GE ? PLUS : MINUS ; if ( mode == SImode && flags_operand2 != NULL_RTX && GET_MODE ( flags_operand2 ) == DImode && REG_P ( flags_operand2 ) && REG_P ( op0 ) && hard_regno_nregs ( REGNO ( flags_operand2 ) , DImode ) == 2 && REGNO ( flags_operand2 ) == REGNO ( op0 ) ) return code == GE ? PLUS : MINUS ; return UNKNOWN ; } </s>

Return a code other than UNKNOWN if we can elide a CODE comparison of OP0 with OP1 .


Return 0 if the attributes for two types are incompatible , 1 if they are compatible , and 2 if they are nearly compatible ( which causes a warning to be generated ) .


<s> const char * VETargetLowering :: getTargetNodeName ( unsigned Opcode ) const { case VEISD :: NAME : \ return "VEISD::" # NAME ; switch ( ( VEISD :: NodeType ) Opcode ) { case VEISD :: FIRST_NUMBER : break ; TARGET_NODE_CASE ( CALL ) TARGET_NODE_CASE ( EH_SJLJ_LONGJMP ) TARGET_NODE_CASE ( EH_SJLJ_SETJMP ) TARGET_NODE_CASE ( EH_SJLJ_SETUP_DISPATCH ) TARGET_NODE_CASE ( GETFUNPLT ) TARGET_NODE_CASE ( GETSTACKTOP ) TARGET_NODE_CASE ( GETTLSADDR ) TARGET_NODE_CASE ( GLOBAL_BASE_REG ) TARGET_NODE_CASE ( Hi ) TARGET_NODE_CASE ( Lo ) TARGET_NODE_CASE ( MEMBARRIER ) TARGET_NODE_CASE ( RET_FLAG ) TARGET_NODE_CASE ( TS1AM ) TARGET_NODE_CASE ( VEC_BROADCAST ) } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

VE VE VEISD::NAME "VEISD::" VEISD::NodeType VEISD::FIRST_NUMBER VE


<s> const char * SPUTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case SPUISD :: RET_FLAG : return "SPUISD::RET_FLAG" ; case SPUISD :: Hi : return "SPUISD::Hi" ; case SPUISD :: Lo : return "SPUISD::Lo" ; case SPUISD :: PCRelAddr : return "SPUISD::PCRelAddr" ; case SPUISD :: AFormAddr : return "SPUISD::AFormAddr" ; case SPUISD :: IndirectAddr : return "SPUISD::IndirectAddr" ; case SPUISD :: LDRESULT : return "SPUISD::LDRESULT" ; case SPUISD :: CALL : return "SPUISD::CALL" ; case SPUISD :: SHUFB : return "SPUISD::SHUFB" ; case SPUISD :: SHUFFLE_MASK : return "SPUISD::SHUFFLE_MASK" ; case SPUISD :: CNTB : return "SPUISD::CNTB" ; case SPUISD :: PREFSLOT2VEC : return "SPUISD::PREFSLOT2VEC" ; case SPUISD :: VEC2PREFSLOT : return "SPUISD::VEC2PREFSLOT" ; case SPUISD :: SHL_BITS : return "SPUISD::SHL_BITS" ; case SPUISD :: SHL_BYTES : return "SPUISD::SHL_BYTES" ; case SPUISD :: VEC_ROTL : return "SPUISD::VEC_ROTL" ; case SPUISD :: VEC_ROTR : return "SPUISD::VEC_ROTR" ; case SPUISD :: ROTBYTES_LEFT : return "SPUISD::ROTBYTES_LEFT" ; case SPUISD :: ROTBYTES_LEFT_BITS : return "SPUISD::ROTBYTES_LEFT_BITS" ; case SPUISD :: SELECT_MASK : return "SPUISD::SELECT_MASK" ; case SPUISD :: SELB : return "SPUISD::SELB" ; case SPUISD :: ADD64_MARKER : return "SPUISD::ADD64_MARKER" ; case SPUISD :: SUB64_MARKER : return "SPUISD::SUB64_MARKER" ; case SPUISD :: MUL64_MARKER : return "SPUISD::MUL64_MARKER" ; } } </s>


<s> bool aarch64_offset_9bit_signed_unscaled_p ( machine_mode mode ATTRIBUTE_UNUSED , poly_int64 offset ) { HOST_WIDE_INT const_offset ; return ( offset . is_constant ( & const_offset ) && IN_RANGE ( const_offset , - 256 , 255 ) ) ; } </s>

Return true if OFFSET is a signed 9-bit value .


<s>
bool
R600Packetizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
const
R600Subtarget
&
ST
=
Fn
.
getSubtarget
<
R600Subtarget
>
(
)
;
const
R600InstrInfo
*
TII
=
ST
.
getInstrInfo
(
)
;
MachineLoopInfo
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
R600PacketizerList
Packetizer
(
Fn
,
ST
,
MLI
)
;
assert
(
Packetizer
.
getResourceTracker
(
)
&&
"Empty DFA table!"
)
;
assert
(
Packetizer
.
getResourceTracker
(
)
->
getInstrItins
(
)
)
;
if
(
Packetizer
.
getResourceTracker
(
)
->
getInstrItins
(
)
->
isEmpty
(
)
)
return
false
;
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
MachineBasicBlock
::
iterator
End
=
MBB
->
end
(
)
;
MachineBasicBlock
::
iterator
MI
=
MBB
->
begin
(
)
;
while
(
MI
!=
End
)
{
if
(
MI
->
isKill
(
)
||
MI
->
getOpcode
(
)
==
R600
::
IMPLICIT_DEF
||
(
MI
->
getOpcode
(
)
==
R600
::
CF_ALU
&&
!
MI
->
getOperand
(
8
)
.
getImm
(
)
)
)
{
MachineBasicBlock
::
iterator
DeleteMI
=
MI
;
++
MI
;
MBB
->
erase
(
DeleteMI
)
;
End
=
MBB
->
end
(
)
;
continue
;
}
++
MI
;
}
}
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
unsigned
RemainingCount
=
MBB
->
size
(
)
;
for
(
MachineBasicBlock
::
iterator
RegionEnd
=
MBB
->
end
(
)
;
RegionEnd
!=
MBB
->
begin
(
)
;
)
{
MachineBasicBlock
::
iterator
I
=
RegionEnd
;
for
(
;
I
!=
MBB
->
begin
(
)
;
I
,
RemainingCount
)
{
if
(
TII
->
isSchedulingBoundary
(
*
std
::
prev
(
I
)
,
&
*
MBB
,
Fn
)
)
break
;
}
I
=
MBB
->
begin
(
)
;
if
(
I
==
RegionEnd
)
{
RegionEnd
=
std
::
prev
(
RegionEnd
)
;
RemainingCount
;
continue
;
}
if
(
I
==
std
::
prev
(
RegionEnd
)
)
{
RegionEnd
=
std
::
prev
(
RegionEnd
)
;
continue
;
}
Packetizer
.
PacketizeMIs
(
&
*
MBB
,
&
*
I
,
RegionEnd
)
;
RegionEnd
=
I
;
}
}
return
true
;
}
</s>


Expand cpymem , as if from a __builtin_memcpy . Return true if we succeed , otherwise return false .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> MSP430Subtarget :: MSP430Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : MSP430GenSubtargetInfo ( TT , CPU , CPU , FS ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) { } </s>

This constructor initializes the data members to match that of the specified triple .


<s> static std :: unique_ptr < AMDGPUOperand > CreateReg ( unsigned RegNo , SMLoc S , SMLoc E , const MCRegisterInfo * TRI , bool ForceVOP3 ) { auto Op = llvm :: make_unique < AMDGPUOperand > ( Register ) ; Op -> Reg . RegNo = RegNo ; Op -> Reg . TRI = TRI ; Op -> Reg . Modifiers = - 1 ; Op -> Reg . IsForcedVOP3 = ForceVOP3 ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


"WebAssemblyDebugFixup: Pop: Register not matched!"

"WebAssemblyDebugFixup: Stack not empty at end of basic block!"


<s> bool PPCAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; assert ( MI -> getOperand ( OpNo ) . isReg ( ) ) ; O << "0(" ; printOperand ( MI , OpNo , O ) ; O << ")" ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> const MCPhysReg * SIRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { CallingConv :: ID CC = MF -> getFunction ( ) . getCallingConv ( ) ; switch ( CC ) { case CallingConv :: C : case CallingConv :: Fast : case CallingConv :: Cold : return ST . hasGFX90AInsts ( ) ? CSR_AMDGPU_HighRegs_With_AGPRs_SaveList : CSR_AMDGPU_HighRegs_SaveList ; case CallingConv :: AMDGPU_Gfx : return ST . hasGFX90AInsts ( ) ? CSR_AMDGPU_SI_Gfx_With_AGPRs_SaveList : CSR_AMDGPU_SI_Gfx_SaveList ; default : { static const MCPhysReg NoCalleeSavedReg = AMDGPU :: NoRegister ; return & NoCalleeSavedReg ; } } } </s>

AMDGPU SI AMDGPU AMDGPU AMDGPU SI SI AMDGPU::NoRegister


"X86-64 PIC uses RIP relative addressing"

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static bool mova_p ( rtx_insn * insn ) { return ( NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == SET && GET_CODE ( SET_SRC ( PATTERN ( insn ) ) ) == UNSPEC && XINT ( SET_SRC ( PATTERN ( insn ) ) , 1 ) == UNSPEC_MOVA && GET_CODE ( MOVA_LABELREF ( insn ) ) == LABEL_REF ) ; } </s>

Return true if the specified insn is a mova insn .


<s>
unsigned
PPCTTI
::
getArithmeticInstrCost
(
unsigned
Opcode
,
Type
*
Ty
)
const
{
assert
(
TLI
->
InstructionOpcodeToISD
(
Opcode
)
&&
"Invalid opcode"
)
;
return
TargetTransformInfo
::
getArithmeticInstrCost
(
Opcode
,
Ty
)
;
}
</s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> static bool ix86_scalar_mode_supported_p ( scalar_mode mode ) { if ( DECIMAL_FLOAT_MODE_P ( mode ) ) return default_decimal_float_supported_p ( ) ; else if ( mode == TFmode ) return true ; else if ( ( mode == HFmode || mode == BFmode ) && TARGET_SSE2 ) return true ; else return default_scalar_mode_supported_p ( mode ) ; } </s>

Target hook for scalar_mode_supported_p .


<s>
static
rtx
avr_legitimize_address
(
rtx
x
,
rtx
oldx
,
machine_mode
mode
)
{
bool
big_offset_p
=
false
;
x
=
oldx
;
if
(
GET_CODE
(
oldx
)
==
PLUS
&&
REG_P
(
XEXP
(
oldx
,
0
)
)
)
{
if
(
REG_P
(
XEXP
(
oldx
,
1
)
)
)
x
=
force_reg
(
GET_MODE
(
oldx
)
,
oldx
)
;
else
if
(
CONST_INT_P
(
XEXP
(
oldx
,
1
)
)
)
{
int
offs
=
INTVAL
(
XEXP
(
oldx
,
1
)
)
;
if
(
frame_pointer_rtx
!=
XEXP
(
oldx
,
0
)
&&
offs
>
MAX_LD_OFFSET
(
mode
)
)
{
big_offset_p
=
true
;
x
=
force_reg
(
GET_MODE
(
oldx
)
,
oldx
)
;
}
}
}
if
(
avr_log
.
legitimize_address
)
{
avr_edump
(
"\n%?: mode=%m\n %r\n"
,
mode
,
oldx
)
;
if
(
x
!=
oldx
)
avr_edump
(
" %s --> %r\n"
,
big_offset_p
"(big offset)"
:
""
,
x
)
;
}
return
x
;
}
</s>

Attempts to replace X with a valid memory address for an operand of mode MODE


"********** MI Converging Scheduling VLIW BB#"

Schedule - This is called back from ScheduleDAGInstrs : :Run ( ) when it 's time to do some work .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < PatmosSinglePathInfo > ( ) ; AU . addRequired < MachinePostDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> unsigned HexagonGenInsert :: distance ( MachineBasicBlock :: const_iterator FromI , MachineBasicBlock :: const_iterator ToI , const UnsignedMap & RPO , PairMapType & M ) const { const MachineBasicBlock * FB = FromI -> getParent ( ) , * TB = ToI -> getParent ( ) ; if ( FB == TB ) return std :: distance ( FromI , ToI ) ; unsigned D1 = std :: distance ( TB -> begin ( ) , ToI ) ; unsigned D2 = distance ( FB , TB , RPO , M ) ; unsigned D3 = std :: distance ( FromI , FB -> end ( ) ) ; return D1 + D2 + D3 ; } </s>

Return the distance from this index to the given one .