<s> static void m32c_function_arg_advance ( cumulative_args_t ca_v , machine_mode mode ATTRIBUTE_UNUSED , const_tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * ca = get_cumulative_args ( ca_v ) ; if ( ca -> force_mem ) ca -> force_mem = 0 ; else ca -> parm_num ++ ; } </s>

Implements FUNCTION_ARG_ADVANCE . force_mem is set for functions returning structures , so we always reset that . Otherwise , we only need to know the sequence number of the argument to know what to do with it .


<s> Sched :: Preference PPCTargetLowering :: getSchedulingPreference ( SDNode * N ) const { if ( DisableILPPref ) return TargetLowering :: getSchedulingPreference ( N ) ; return Sched :: ILP ; } </s>


<s> static int n_dregs_to_save ( bool is_inthandler ) { unsigned i ; for ( i = REG_R0 ; i <= REG_R7 ; i ++ ) { if ( regs_ever_live [ i ] && ( is_inthandler || ! call_used_regs [ i ] ) ) return REG_R7 - i + 1 ; if ( current_function_calls_eh_return ) { unsigned j ; for ( j = 0 ; ; j ++ ) { unsigned test = EH_RETURN_DATA_REGNO ( j ) ; if ( test == INVALID_REGNUM ) break ; if ( test == i ) return REG_R7 - i + 1 ; } } } return 0 ; } </s>

Compute the number of DREGS to save with a push_multiple operation . This could include registers that are n't modified in the function , since push_multiple only takes a range of registers . If IS_INTHANDLER , then everything that is live must be saved , even if normally call-clobbered .


"[Single-Path] Mark function reachable from single-path roots\n"

runOnMachineFunction - Emit the function body .


<s> const uint16_t * X86RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { bool callsEHReturn = false ; bool ghcCall = false ; if ( MF ) { callsEHReturn = MF -> getMMI ( ) . callsEHReturn ( ) ; const Function * F = MF -> getFunction ( ) ; ghcCall = ( F ? F -> getCallingConv ( ) == CallingConv :: GHC : false ) ; } if ( ghcCall ) return CSR_NoRegs_SaveList ; if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_SaveList ; if ( callsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; } if ( callsEHReturn ) return CSR_32EHRet_SaveList ; return CSR_32_SaveList ; } </s>


<s> unsigned MipsTargetLowering :: getJumpTableEncoding ( ) const { if ( isN64 ( ) ) return MachineJumpTableInfo :: EK_GPRel64BlockAddress ; return TargetLowering :: getJumpTableEncoding ( ) ; } </s>

Return the entry encoding for a jump table in the current function .


<s> bool X86FastPreTileConfig :: runOnMachineFunction ( MachineFunction & MFunc ) { MF = & MFunc ; MRI = & MFunc . getRegInfo ( ) ; ST = & MFunc . getSubtarget < X86Subtarget > ( ) ; TII = ST -> getInstrInfo ( ) ; X86FI = MFunc . getInfo < X86MachineFunctionInfo > ( ) ; MFI = & MFunc . getFrameInfo ( ) ; TRI = ST -> getRegisterInfo ( ) ; CfgSS = - 1 ; unsigned NumVirtRegs = MRI -> getNumVirtRegs ( ) ; bool HasVirtTileReg = false ; for ( unsigned I = 0 , E = NumVirtRegs ; I != E ; ++ I ) { Register VirtReg = Register :: index2VirtReg ( I ) ; if ( MRI -> getRegClass ( VirtReg ) -> getID ( ) == X86 :: TILERegClassID ) { HasVirtTileReg = true ; break ; } } if ( ! HasVirtTileReg ) return false ; StackSlotForVirtReg . resize ( NumVirtRegs ) ; MayLiveAcrossBlocks . clear ( ) ; MayLiveAcrossBlocks . resize ( NumVirtRegs * 3 ) ; bool Change = false ; assert ( MRI -> isSSA ( ) ) ; for ( MachineBasicBlock & MBB : MFunc ) canonicalizePHIs ( MBB ) ; ReversePostOrderTraversal < MachineFunction * > RPOT ( MF ) ; for ( MachineBasicBlock * MBB : RPOT ) { convertPHIs ( * MBB ) ; Change |= configBasicBlock ( * MBB ) ; } if ( Change ) InitializeTileConfigStackSpace ( ) ; StackSlotForVirtReg . clear ( ) ; return Change ; } </s>


<s> const Triple & getTargetTriple ( ) const { return TargetTriple ; } </s>

Get the target triple which is a string describing the target host .


<s> MachineInstr * HexagonInstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , ArrayRef < unsigned > Ops , int FI ) const { return nullptr ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> const node_value_type & getValue ( ) const { return Value ; } </s>


<s> static rtx v850_function_arg ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; rtx result = NULL_RTX ; int size , align ; if ( ! named ) return NULL_RTX ; if ( mode == BLKmode ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; size = ( size + UNITS_PER_WORD - 1 ) & ~ ( UNITS_PER_WORD - 1 ) ; if ( size < 1 ) { cum -> nbytes = 4 * UNITS_PER_WORD ; return NULL_RTX ; } if ( ! TARGET_GCC_ABI ) align = UNITS_PER_WORD ; else if ( size <= UNITS_PER_WORD && type ) align = TYPE_ALIGN ( type ) / BITS_PER_UNIT ; else align = size ; cum -> nbytes = ( cum -> nbytes + align - 1 ) & ~ ( align - 1 ) ; if ( cum -> nbytes > 4 * UNITS_PER_WORD ) return NULL_RTX ; if ( type == NULL_TREE && cum -> nbytes + size > 4 * UNITS_PER_WORD ) return NULL_RTX ; switch ( cum -> nbytes / UNITS_PER_WORD ) { case 0 : result = gen_rtx_REG ( mode , 6 ) ; break ; case 1 : result = gen_rtx_REG ( mode , 7 ) ; break ; case 2 : result = gen_rtx_REG ( mode , 8 ) ; break ; case 3 : result = gen_rtx_REG ( mode , 9 ) ; break ; default : result = NULL_RTX ; } return result ; } </s>

Return an RTX to represent where an argument with mode MODE and type TYPE will be passed to a function . If the result is NULL_RTX , the argument will be pushed .


<s> bool ARMBaseInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TBB , unsigned TCycles , unsigned TExtra , MachineBasicBlock & FBB , unsigned FCycles , unsigned FExtra , BranchProbability Probability ) const { if ( ! TCycles ) return false ; const unsigned ScalingUpFactor = 1024 ; unsigned PredCost = ( TCycles + FCycles + TExtra + FExtra ) * ScalingUpFactor ; unsigned UnpredCost ; if ( ! Subtarget . hasBranchPredictor ( ) ) { unsigned NotTakenBranchCost = 1 ; unsigned TakenBranchCost = Subtarget . getMispredictionPenalty ( ) ; unsigned TUnpredCycles , FUnpredCycles ; if ( ! FCycles ) { TUnpredCycles = TCycles + NotTakenBranchCost ; FUnpredCycles = TakenBranchCost ; } else { TUnpredCycles = TCycles + TakenBranchCost ; FUnpredCycles = FCycles + NotTakenBranchCost ; PredCost -= 1 * ScalingUpFactor ; } unsigned TUnpredCost = Probability . scale ( TUnpredCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FUnpredCycles * ScalingUpFactor ) ; UnpredCost = TUnpredCost + FUnpredCost ; if ( Subtarget . isThumb2 ( ) && TCycles + FCycles > 4 ) { PredCost += ( ( TCycles + FCycles - 4 ) / 4 ) * ScalingUpFactor ; } } else { unsigned TUnpredCost = Probability . scale ( TCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FCycles * ScalingUpFactor ) ; UnpredCost = TUnpredCost + FUnpredCost ; UnpredCost += 1 * ScalingUpFactor ; UnpredCost += Subtarget . getMispredictionPenalty ( ) * ScalingUpFactor / 10 ; } return PredCost <= UnpredCost ; } </s>


<s> static vl_vtype_info get_vl_vtype_info ( const insn_info * insn ) { set_info * set = nullptr ; rtx avl = :: get_avl ( insn -> rtl ( ) ) ; if ( avl && REG_P ( avl ) ) { if ( vlmax_avl_p ( avl ) && has_vl_op ( insn -> rtl ( ) ) ) set = find_access ( insn -> uses ( ) , REGNO ( get_vl ( insn -> rtl ( ) ) ) ) -> def ( ) ; else if ( ! vlmax_avl_p ( avl ) ) set = find_access ( insn -> uses ( ) , REGNO ( avl ) ) -> def ( ) ; else set = nullptr ; } uint8_t sew = get_sew ( insn -> rtl ( ) ) ; enum vlmul_type vlmul = get_vlmul ( insn -> rtl ( ) ) ; uint8_t ratio = get_attr_ratio ( insn -> rtl ( ) ) ; if ( ratio == INVALID_ATTRIBUTE ) ratio = calculate_ratio ( sew , vlmul ) ; bool ta = tail_agnostic_p ( insn -> rtl ( ) ) ; bool ma = mask_agnostic_p ( insn -> rtl ( ) ) ; int merge_op_idx = get_attr_merge_op_idx ( insn -> rtl ( ) ) ; if ( merge_op_idx != INVALID_ATTRIBUTE && satisfies_constraint_vu ( recog_data . operand [ merge_op_idx ] ) ) { ta = true ; ma = true ; } vl_vtype_info info ( avl_info ( avl , set ) , sew , vlmul , ratio , ta , ma ) ; return info ; } </s>


<s> static std :: unique_ptr < MipsOperand > CreateMem ( std :: unique_ptr < MipsOperand > Base , const MCExpr * Off , SMLoc S , SMLoc E , MipsAsmParser & Parser ) { auto Op = make_unique < MipsOperand > ( k_Memory , Parser ) ; Op -> Mem . Base = Base . release ( ) ; Op -> Mem . Off = Off ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ReserveXRegister ( AArch64 :: GPR64commonRegClass . getNumRegs ( ) ) , CustomCallSavedXRegs ( AArch64 :: GPR64commonRegClass . getNumRegs ( ) ) , IsLittle ( LittleEndian ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS , CPU ) ) , TSInfo ( ) , TLInfo ( TM , * this ) { if ( AArch64 :: isX18ReservedByDefault ( TT ) ) ReserveXRegister . set ( 18 ) ; ReserveXRegister . set ( 19 ) ; ReserveXRegister . set ( 20 ) ; CallLoweringInfo . reset ( new AArch64CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new AArch64LegalizerInfo ( * this ) ) ; auto * RBI = new AArch64RegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( createAArch64InstructionSelector ( * static_cast < const AArch64TargetMachine * > ( & TM ) , * this , * RBI ) ) ; RegBankInfo . reset ( RBI ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> bool RISCVTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { if ( VT == MVT :: f16 && ! Subtarget . hasStdExtZfh ( ) ) return false ; if ( VT == MVT :: f32 && ! Subtarget . hasStdExtF ( ) ) return false ; if ( VT == MVT :: f64 && ! Subtarget . hasStdExtD ( ) ) return false ; if ( Imm . isNegZero ( ) ) return false ; return Imm . isZero ( ) ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> static int ia64_arg_partial_bytes ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int words = ia64_function_arg_words ( arg . type , arg . mode ) ; int offset = ia64_function_arg_offset ( cum , arg . type , words ) ; if ( cum -> words + offset >= MAX_ARGUMENT_SLOTS ) return 0 ; if ( words + cum -> words + offset <= MAX_ARGUMENT_SLOTS ) return 0 ; return ( MAX_ARGUMENT_SLOTS - cum -> words - offset ) * UNITS_PER_WORD ; } </s>

Return number of bytes , at the beginning of the argument , that must be put in registers . 0 is the argument is entirely in registers or entirely in memory .


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> bool s390_can_eliminate ( int from , int to ) { if ( from == BASE_REGNUM && to == BASE_REGNUM ) { if ( TARGET_CPU_ZARCH ) { s390_init_frame_layout ( ) ; return cfun -> machine -> base_reg == NULL_RTX ; } return false ; } gcc_assert ( to == STACK_POINTER_REGNUM || to == HARD_FRAME_POINTER_REGNUM ) ; gcc_assert ( from == FRAME_POINTER_REGNUM || from == ARG_POINTER_REGNUM || from == RETURN_ADDRESS_POINTER_REGNUM ) ; if ( from == RETURN_ADDRESS_POINTER_REGNUM ) if ( ! current_function_calls_eh_return && ! current_function_stdarg && ! cfun_frame_layout . save_return_addr_p ) return false ; return true ; } </s>

Return true if register FROM can be eliminated via register TO .


<s> StringRef getString ( ) const { return Data ; } </s>


<s> static sbitmap rs6000_components_for_bb ( basic_block bb ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; bitmap in = DF_LIVE_IN ( bb ) ; bitmap gen = & DF_LIVE_BB_INFO ( bb ) -> gen ; bitmap kill = & DF_LIVE_BB_INFO ( bb ) -> kill ; sbitmap components = sbitmap_alloc ( cfun -> machine -> n_components ) ; bitmap_clear ( components ) ; for ( unsigned regno = info -> first_gp_reg_save ; regno < 32 ; regno ++ ) if ( bitmap_bit_p ( in , regno ) || bitmap_bit_p ( gen , regno ) || bitmap_bit_p ( kill , regno ) ) bitmap_set_bit ( components , regno ) ; for ( unsigned regno = info -> first_fp_reg_save ; regno < 64 ; regno ++ ) if ( bitmap_bit_p ( in , regno ) || bitmap_bit_p ( gen , regno ) || bitmap_bit_p ( kill , regno ) ) bitmap_set_bit ( components , regno ) ; if ( bitmap_bit_p ( in , LR_REGNO ) || bitmap_bit_p ( gen , LR_REGNO ) || bitmap_bit_p ( kill , LR_REGNO ) ) bitmap_set_bit ( components , 0 ) ; return components ; } </s>


<s> SDValue AAPTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , uint32_t * RegMask ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_AAP ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { unsigned Reg = RVLocs [ i ] . getLocReg ( ) ; RegMask [ Reg / 32 ] &= ~ ( 1u << ( Reg & 32 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static int ix86_mode_after ( int entity , int mode , rtx_insn * insn ) { switch ( entity ) { case AVX_U128 : return ix86_avx_u128_mode_after ( mode , insn ) ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : case I387_MASK_PM : return mode ; default : gcc_unreachable ( ) ; } } </s>

Return the mode that an insn results in .


<s> unsigned X86InstrInfo :: getUndefRegClearance ( const MachineInstr & MI , unsigned & OpNum , const TargetRegisterInfo * TRI ) const { if ( ! hasUndefRegUpdate ( MI . getOpcode ( ) , OpNum ) ) return 0 ; const MachineOperand & MO = MI . getOperand ( OpNum ) ; if ( MO . isUndef ( ) && Register :: isPhysicalRegister ( MO . getReg ( ) ) ) { return UndefRegClearance ; } return 0 ; } </s>

Inform the BreakFalseDeps pass how many idle instructions we would like before certain undef register reads .


<s> static void reorder_var_tracking_notes ( void ) { basic_block bb ; FOR_EACH_BB_FN ( bb , cfun ) { rtx_insn * insn , * next ; rtx_insn * queue = NULL ; bool in_bundle = false ; for ( insn = BB_HEAD ( bb ) ; insn != BB_END ( bb ) ; insn = next ) { next = NEXT_INSN ( insn ) ; if ( INSN_P ( insn ) ) { if ( GET_MODE ( insn ) == QImode ) { while ( queue ) { rtx_insn * next_queue = PREV_INSN ( queue ) ; SET_PREV_INSN ( NEXT_INSN ( insn ) ) = queue ; SET_NEXT_INSN ( queue ) = NEXT_INSN ( insn ) ; SET_NEXT_INSN ( insn ) = queue ; SET_PREV_INSN ( queue ) = insn ; queue = next_queue ; } in_bundle = false ; } else if ( GET_MODE ( insn ) == SImode ) in_bundle = true ; } else if ( NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_VAR_LOCATION ) { if ( in_bundle ) { rtx_insn * prev = PREV_INSN ( insn ) ; SET_PREV_INSN ( next ) = prev ; SET_NEXT_INSN ( prev ) = next ; SET_PREV_INSN ( insn ) = queue ; queue = insn ; } } } } } </s>

Ensure that no var tracking notes are emitted in the middle of a three-instruction bundle .


<s> bool X86FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || TRI -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MFI -> hasOpaqueSPAdjustment ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) || MMI . callsEHReturn ( ) || MFI -> hasStackMap ( ) || MFI -> hasPatchPoint ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


"rs6000_builtin_md_vectorized_function (%s, %s, %s)\n"


<s> static bool mn10300_pass_by_reference ( cumulative_args_t cum ATTRIBUTE_UNUSED , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { unsigned HOST_WIDE_INT size ; if ( type ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; return ( size > 8 || size == 0 ) ; } </s>

Return true when a parameter should be passed by reference .


<s> static bool is_microcoded_insn ( rtx_insn * insn ) { if ( ! insn || ! NONDEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; if ( rs6000_cpu_attr == CPU_CELL ) return get_attr_cell_micro ( insn ) == CELL_MICRO_ALWAYS ; if ( rs6000_sched_groups && ( rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5 ) ) { enum attr_type type = get_attr_type ( insn ) ; if ( ( type == TYPE_LOAD && get_attr_update ( insn ) == UPDATE_YES && get_attr_sign_extend ( insn ) == SIGN_EXTEND_YES ) || ( ( type == TYPE_LOAD || type == TYPE_STORE ) && get_attr_update ( insn ) == UPDATE_YES && get_attr_indexed ( insn ) == INDEXED_YES ) || type == TYPE_MFCR ) return true ; } return false ; } </s>

The function returns a true if INSN is microcoded . Return false otherwise .


<s> void optimization_options ( int level ATTRIBUTE_UNUSED , int size ATTRIBUTE_UNUSED ) { if ( DEFAULT_ABI == ABI_DARWIN ) flag_errno_math = 0 ; set_param_value ( "max-grow-copy-bb-insns" , 16 ) ; } </s>

Change optimizations to be performed , depending on the optimization level . LEVEL is the optimization level specified ; 2 if ` -O2 ' is specified , 1 if ` -O ' is specified , and 0 if neither is specified . SIZE is nonzero if ` -Os ' is specified and zero otherwise .


<s> bool c6x_block_reg_pad_upward ( machine_mode mode ATTRIBUTE_UNUSED , const_tree type , bool first ) { HOST_WIDE_INT size ; if ( ! TARGET_BIG_ENDIAN ) return true ; if ( ! first ) return true ; if ( ! type ) return true ; size = int_size_in_bytes ( type ) ; return size == 3 ; } </s>

Return true if BLOCK_REG_PADDING ( MODE , TYPE , FIRST ) should return upward rather than downward .


<s> TargetLowering :: AtomicExpansionKind PPCTargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { unsigned Size = AI -> getNewValOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( EnableQuadwordAtomics && Subtarget . hasQuadwordAtomics ( ) && Size == 128 ) return AtomicExpansionKind :: MaskedIntrinsic ; return TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AI ) ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> SDValue mprocTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { } </s>


<s> static bool sh_legitimate_constant_p ( machine_mode mode , rtx x ) { return ( TARGET_SHMEDIA ? ( ( mode != DFmode && GET_MODE_CLASS ( mode ) != MODE_VECTOR_FLOAT ) || x == CONST0_RTX ( mode ) || ! TARGET_SHMEDIA_FPU || TARGET_SHMEDIA64 ) : ( GET_CODE ( x ) != CONST_DOUBLE || mode == DFmode || mode == SFmode || mode == DImode || GET_MODE ( x ) == VOIDmode ) ) ; } </s>


"We have a different number of location and args?!"

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> const char * PIC16TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return NULL ; case PIC16ISD :: Lo : return "PIC16ISD::Lo" ; case PIC16ISD :: Hi : return "PIC16ISD::Hi" ; case PIC16ISD :: MTLO : return "PIC16ISD::MTLO" ; case PIC16ISD :: MTHI : return "PIC16ISD::MTHI" ; case PIC16ISD :: MTPCLATH : return "PIC16ISD::MTPCLATH" ; case PIC16ISD :: PIC16Connect : return "PIC16ISD::PIC16Connect" ; case PIC16ISD :: Banksel : return "PIC16ISD::Banksel" ; case PIC16ISD :: PIC16Load : return "PIC16ISD::PIC16Load" ; case PIC16ISD :: PIC16LdArg : return "PIC16ISD::PIC16LdArg" ; case PIC16ISD :: PIC16LdWF : return "PIC16ISD::PIC16LdWF" ; case PIC16ISD :: PIC16Store : return "PIC16ISD::PIC16Store" ; case PIC16ISD :: PIC16StWF : return "PIC16ISD::PIC16StWF" ; case PIC16ISD :: BCF : return "PIC16ISD::BCF" ; case PIC16ISD :: LSLF : return "PIC16ISD::LSLF" ; case PIC16ISD :: LRLF : return "PIC16ISD::LRLF" ; case PIC16ISD :: RLF : return "PIC16ISD::RLF" ; case PIC16ISD :: RRF : return "PIC16ISD::RRF" ; case PIC16ISD :: CALL : return "PIC16ISD::CALL" ; case PIC16ISD :: CALLW : return "PIC16ISD::CALLW" ; case PIC16ISD :: SUBCC : return "PIC16ISD::SUBCC" ; case PIC16ISD :: SELECT_ICC : return "PIC16ISD::SELECT_ICC" ; case PIC16ISD :: BRCOND : return "PIC16ISD::BRCOND" ; case PIC16ISD :: RET : return "PIC16ISD::RET" ; case PIC16ISD :: Dummy : return "PIC16ISD::Dummy" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> SDNode * X86DAGToDAGISel :: getGlobalBaseReg ( ) { MachineFunction * MF = CurBB -> getParent ( ) ; unsigned GlobalBaseReg = TM . getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI . getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> int mips_class_max_nregs ( enum reg_class rclass , machine_mode mode ) { int size ; HARD_REG_SET left ; size = 0x8000 ; COPY_HARD_REG_SET ( left , reg_class_contents [ ( int ) rclass ] ) ; if ( hard_reg_set_intersect_p ( left , reg_class_contents [ ( int ) ST_REGS ] ) ) { if ( mips_hard_regno_mode_ok ( ST_REG_FIRST , mode ) ) size = MIN ( size , 4 ) ; AND_COMPL_HARD_REG_SET ( left , reg_class_contents [ ( int ) ST_REGS ] ) ; } if ( hard_reg_set_intersect_p ( left , reg_class_contents [ ( int ) FP_REGS ] ) ) { if ( mips_hard_regno_mode_ok ( FP_REG_FIRST , mode ) ) { if ( MSA_SUPPORTED_MODE_P ( mode ) ) size = MIN ( size , UNITS_PER_MSA_REG ) ; else size = MIN ( size , UNITS_PER_FPREG ) ; } AND_COMPL_HARD_REG_SET ( left , reg_class_contents [ ( int ) FP_REGS ] ) ; } if ( ! hard_reg_set_empty_p ( left ) ) size = MIN ( size , UNITS_PER_WORD ) ; return ( GET_MODE_SIZE ( mode ) + size - 1 ) / size ; } </s>

Implement CLASS_MAX_NREGS . Usually all registers are word-sized . The only supported exception is -mgp64 -msingle-float , which has 64-bit words but 32-bit float registers . A word-based calculation is correct even in that case , since -msingle-float disallows multi-FPR values . The FP status registers are an exception to this rule . They are always 4 bytes wide as they only hold condition code modes , and CCmode is always considered to be 4 bytes wide .


<s> MachineBasicBlock :: iterator TeakFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s>
static
void
m68hc11_reassign_regs
(
rtx
first
)
{
rtx
insn
;
ix_reg
=
gen_rtx_REG
(
HImode
,
HARD_X_REGNUM
)
;
iy_reg
=
gen_rtx_REG
(
HImode
,
HARD_Y_REGNUM
)
;
z_reg
=
gen_rtx_REG
(
HImode
,
HARD_Z_REGNUM
)
;
z_reg_qi
=
gen_rtx_REG
(
QImode
,
HARD_Z_REGNUM
)
;
for
(
insn
=
first
;
insn
;
insn
=
NEXT_INSN
(
insn
)
)
{
rtx
body
;
if
(
GET_CODE
(
insn
)
==
CODE_LABEL
||
GET_CODE
(
insn
)
==
NOTE
||
GET_CODE
(
insn
)
==
BARRIER
)
continue
;
if
(
!
INSN_P
(
insn
)
)
continue
;
body
=
PATTERN
(
insn
)
;
if
(
GET_CODE
(
body
)
==
CLOBBER
||
GET_CODE
(
body
)
==
USE
)
continue
;
if
(
GET_CODE
(
body
)
==
CONST_INT
||
GET_CODE
(
body
)
==
ASM_INPUT
||
GET_CODE
(
body
)
==
ASM_OPERANDS
||
GET_CODE
(
body
)
==
UNSPEC
||
GET_CODE
(
body
)
==
UNSPEC_VOLATILE
)
continue
;
if
(
GET_CODE
(
body
)
==
SET
||
GET_CODE
(
body
)
==
PARALLEL
||
GET_CODE
(
insn
)
==
CALL_INSN
||
GET_CODE
(
insn
)
==
JUMP_INSN
)
{
if
(
reg_mentioned_p
(
z_reg
,
body
)
)
{
m68hc11_z_replacement
(
insn
)
;
}
}
else
{
printf
(
"insn not handled by Z replacement:\n"
)
;
fflush
(
stdout
)
;
debug_rtx
(
insn
)
;
}
}
}
</s>

Scan all the insn and re-affects some registers - The Z register ( if it was used ) , is affected to X or Y depending on the instruction .


"Unexpected instruction for custom inserter!"

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> const MCRegisterInfo * getRegInfo ( ) const { return RegInfo ; } </s>

getRegInfo - Return information about the registers currently in use .


<s> static void rs6000_set_up_by_prologue ( struct hard_reg_set_container * set ) { if ( ! TARGET_SINGLE_PIC_BASE && TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size ( ) != 0 ) add_to_hard_reg_set ( & set -> set , Pmode , RS6000_PIC_OFFSET_TABLE_REGNUM ) ; } </s>

Add r30 to hard reg set if the prologue sets it up and it is not pic_offset_table_rtx .


<s>
static
void
pa_output_pic_pcrel_sequence
(
rtx
*
operands
)
{
gcc_assert
(
SYMBOL_REF_P
(
operands
[
0
]
)
||
LABEL_P
(
operands
[
0
]
)
)
;
if
(
TARGET_PA_20
)
{
if
(
TARGET_SOM
||
!
TARGET_GAS
)
{
operands
[
3
]
=
gen_label_rtx
(
)
;
targetm
.
asm_out
.
internal_label
(
asm_out_file
,
"L"
,
CODE_LABEL_NUMBER
(
operands
[
3
]
)
)
;
output_asm_insn
(
"mfia %1"
,
operands
)
;
output_asm_insn
(
"addil L'%0-%l3,%1"
,
operands
)
;
output_asm_insn
(
"ldo R'%0-%l3(%%r1),%2"
,
operands
)
;
}
else
{
output_asm_insn
(
"mfia %1"
,
operands
)
;
output_asm_insn
(
"addil L'%0-$PIC_pcrel$0+12,%1"
,
operands
)
;
output_asm_insn
(
"ldo R'%0-$PIC_pcrel$0+16(%%r1),%2"
,
operands
)
;
}
}
else
{
output_asm_insn
(
"{bl|b,l} .+8,%1"
,
operands
)
;
if
(
TARGET_SOM
||
!
TARGET_GAS
)
{
operands
[
3
]
=
gen_label_rtx
(
)
;
output_asm_insn
(
"addil L'%0-%l3,%1"
,
operands
)
;
targetm
.
asm_out
.
internal_label
(
asm_out_file
,
"L"
,
CODE_LABEL_NUMBER
(
operands
[
3
]
)
)
;
output_asm_insn
(
"ldo R'%0-%l3(%%r1),%2"
,
operands
)
;
}
else
{
output_asm_insn
(
"addil L'%0-$PIC_pcrel$0+4,%1"
,
operands
)
;
output_asm_insn
(
"ldo R'%0-$PIC_pcrel$0+8(%%r1),%2"
,
operands
)
;
}
}
}
</s>

Output a PIC pc-relative instruction sequence to load the address of OPERANDS [ 0 ] to register OPERANDS [ 2 ] . OPERANDS [ 0 ] is a symbol ref or a code label . OPERANDS [ 1 ] specifies the register to use to load the program counter . OPERANDS [ 3 ] may be used for label generation The sequence is always three instructions in length . The program counter recorded for PA 1.X is eight bytes more than that for PA 2.0 . Register % r1 is clobbered .


<s> bool Thumb1FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( ARM :: tPUSH ) ) ; AddDefaultPred ( MIB ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; bool isKill = true ; if ( Reg == ARM :: LR ) { MachineFunction & MF = * MBB . getParent ( ) ; if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) && MF . getRegInfo ( ) . isLiveIn ( Reg ) ) isKill = false ; } if ( isKill ) MBB . addLiveIn ( Reg ) ; MIB . addReg ( Reg , getKillRegState ( isKill ) ) ; } MIB . setMIFlags ( MachineInstr :: FrameSetup ) ; return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s>
SDValue
BPFTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
unsigned
Opc
=
BPFISD
::
RET_FLAG
;
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
MF
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
if
(
MF
.
getFunction
(
)
.
getReturnType
(
)
->
isAggregateType
(
)
)
{
fail
(
DL
,
DAG
,
"only integer returns supported"
)
;
return
DAG
.
getNode
(
Opc
,
DL
,
MVT
::
Other
,
Chain
)
;
}
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_BPF64
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
Opc
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> X86TargetLowering :: ConstraintType X86TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'R' : case 'q' : case 'Q' : case 'f' : case 't' : case 'u' : case 'y' : case 'x' : case 'Y' : case 'l' : return C_RegisterClass ; case 'a' : case 'b' : case 'c' : case 'd' : case 'S' : case 'D' : case 'A' : return C_Register ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'G' : case 'C' : case 'e' : case 'Z' : return C_Other ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> const AMDGPUInstrInfo * getInstrInfo ( ) const { return InstrInfo . get ( ) ; } </s>


<s> static scalar_int_mode rs6000_eh_return_filter_mode ( void ) { return TARGET_32BIT ? SImode : word_mode ; } </s>


<s> bool SITargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & , EVT ) const { return false ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> static tree gcn_global_lock_addr ( ) { tree v = global_lock_var ; if ( ! v ) { tree name = get_identifier ( "__reduction_lock" ) ; tree type = build_qualified_type ( unsigned_type_node , TYPE_QUAL_VOLATILE ) ; v = build_decl ( BUILTINS_LOCATION , VAR_DECL , name , type ) ; global_lock_var = v ; DECL_ARTIFICIAL ( v ) = 1 ; DECL_EXTERNAL ( v ) = 1 ; TREE_STATIC ( v ) = 1 ; TREE_PUBLIC ( v ) = 1 ; TREE_USED ( v ) = 1 ; mark_addressable ( v ) ; mark_decl_referenced ( v ) ; } return build_fold_addr_expr ( v ) ; } </s>

Lazily generate the global_lock_var decl and return its address .


<s> bool isMem ( ) const override { return Kind == k_Memory ; } </s>


<s> void X86AsmParser :: EmitInstruction ( MCInst & Inst , OperandVector & Operands , MCStreamer & Out ) { Instrumentation -> InstrumentAndEmitInstruction ( Inst , Operands , getContext ( ) , MII , Out ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> MachineBasicBlock * MipsSETargetLowering :: EmitInstrWithCustomInserter ( MachineInstr * MI , MachineBasicBlock * BB ) const { switch ( MI -> getOpcode ( ) ) { default : return MipsTargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; case Mips :: BPOSGE32_PSEUDO : return emitBPOSGE32 ( MI , BB ) ; } } </s>


<s> void PPCRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , Register BaseReg , int FrameIdx , int64_t Offset ) const { unsigned ADDriOpc = TM . isPPC64 ( ) ? PPC :: ADDI8 : PPC :: ADDI ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , 0 , this , MF ) ) ; BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .

PowerPC PPC PPC PPC::ADDI8 PPC::ADDI PPC PPC 0


<s> ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const override { const AMDGPUSubtarget & ST = * getAMDGPUTargetMachine ( ) . getSubtargetImpl ( ) ; if ( ST . getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) return createR600MachineScheduler ( C ) ; return nullptr ; } </s>

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level .


<s> bool MOSAsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const { return true ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> rtx rx_maybe_pidify_operand ( rtx op , int copy_to_reg ) { if ( rx_pid_data_operand ( op ) == PID_UNENCODED ) { if ( GET_CODE ( op ) == MEM ) { rtx a = gen_pid_addr ( gen_rtx_REG ( SImode , rx_pid_base_regnum ( ) ) , XEXP ( op , 0 ) ) ; op = replace_equiv_address ( op , a ) ; } else { op = gen_pid_addr ( gen_rtx_REG ( SImode , rx_pid_base_regnum ( ) ) , op ) ; } if ( copy_to_reg ) op = copy_to_mode_reg ( GET_MODE ( op ) , op ) ; } return op ; } </s>

Maybe convert an operand into its PID format .


<s> void X86InstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , unsigned SubIdx , const MachineInstr * Orig , const TargetRegisterInfo & TRI ) const { unsigned Opc = Orig -> getOpcode ( ) ; if ( Opc == X86 :: MOV32r0 && ! isSafeToClobberEFLAGS ( MBB , I ) ) { DebugLoc DL = Orig -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , get ( X86 :: MOV32ri ) ) . addOperand ( Orig -> getOperand ( 0 ) ) . addImm ( 0 ) ; } else { MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( Orig ) ; MBB . insert ( I , MI ) ; } MachineInstr * NewMI = prior ( I ) ; NewMI -> substituteRegister ( Orig -> getOperand ( 0 ) . getReg ( ) , DestReg , SubIdx , TRI ) ; } </s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s> bool shouldFormOverflowOp ( unsigned Opcode , EVT VT , bool MathUsed ) const override { return TargetLowering :: shouldFormOverflowOp ( Opcode , VT , true ) ; } </s>

Overflow nodes should get combined/lowered to optimal instructions ( they should allow eliminating explicit compares by getting flags from math ops ) .


<s> virtual const ARCompactRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void RISCVPassConfig :: addPreRegAlloc ( ) { addPass ( createRISCVMergeBaseOffsetOptPass ( ) ) ; addPass ( createRISCVCoreVHwlpBlocksPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s>
bool
IA64AsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
this
->
MF
=
&
MF
;
SetupMachineFunction
(
MF
)
;
O
<<
"\n\n"
;
EmitConstantPool
(
MF
.
getConstantPool
(
)
)
;
const
Function
*
F
=
MF
.
getFunction
(
)
;
SwitchToSection
(
TAI
->
SectionForGlobal
(
F
)
)
;
EmitAlignment
(
5
)
;
O
<<
"\t.global\t"
<<
CurrentFnName
<<
'\n'
;
printVisibility
(
CurrentFnName
,
F
->
getVisibility
(
)
)
;
O
<<
"\t.type\t"
<<
CurrentFnName
<<
", @function\n"
;
O
<<
CurrentFnName
<<
":\n"
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
!
I
->
pred_empty
(
)
)
{
printBasicBlockLabel
(
I
,
true
,
true
)
;
O
<<
'\n'
;
}
for
(
MachineBasicBlock
::
const_iterator
II
=
I
->
begin
(
)
,
E
=
I
->
end
(
)
;
II
!=
E
;
++
II
)
{
printMachineInstruction
(
II
)
;
}
}
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


"PIC16 Does not have any return address register"

This method should return the register where the return address can be found .


<s>
bool
Emitter
<
CodeEmitter
>
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MMI
=
&
getAnalysis
<
MachineModuleInfo
>
(
)
;
MCE
.
setModuleInfo
(
MMI
)
;
II
=
TM
.
getInstrInfo
(
)
;
TD
=
TM
.
getTargetData
(
)
;
Is64BitMode
=
TM
.
getSubtarget
<
X86Subtarget
>
(
)
.
is64Bit
(
)
;
IsPIC
=
TM
.
getRelocationModel
(
)
==
Reloc
::
PIC_
;
do
{
DEBUG
(
dbgs
(
)
<<
"JITTing function '"
<<
MF
.
getFunction
(
)
->
getName
(
)
<<
"'\n"
)
;
MCE
.
startFunction
(
MF
)
;
for
(
MachineFunction
::
iterator
MBB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBB
!=
E
;
++
MBB
)
{
MCE
.
StartMachineBasicBlock
(
MBB
)
;
for
(
MachineBasicBlock
::
const_iterator
I
=
MBB
->
begin
(
)
,
E
=
MBB
->
end
(
)
;
I
!=
E
;
++
I
)
{
const
TargetInstrDesc
&
Desc
=
I
->
getDesc
(
)
;
emitInstruction
(
*
I
,
&
Desc
)
;
if
(
Desc
.
getOpcode
(
)
==
X86
::
MOVPC32r
)
emitInstruction
(
*
I
,
&
II
->
get
(
X86
::
POP32r
)
)
;
++
NumEmitted
;
}
}
}
while
(
MCE
.
finishFunction
(
MF
)
)
;
return
false
;
}
</s>


<s> void PPCPassConfig :: addPreEmitPass ( ) { addPass ( createPPCExpandISELPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCEarlyReturnPass ( ) , false ) ; addPass ( createPPCBranchSelectionPass ( ) , false ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool MOSFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , MutableArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { MachineIRBuilder Builder ( MBB , MI ) ; const MOSSubtarget & STI = MBB . getParent ( ) -> getSubtarget < MOSSubtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; const TargetRegisterClass & StackRegClass = STI . has65C02 ( ) ? MOS :: GPRRegClass : MOS :: AcRegClass ; for ( const CalleeSavedInfo & CI : reverse ( CSI ) ) { Register Reg = CI . getReg ( ) ; if ( CI . isTargetSpilled ( ) ) continue ; assert ( ! CI . isSpilledToReg ( ) ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , Builder . getInsertPt ( ) , Reg , CI . getFrameIdx ( ) , RC , TRI ) ; } MachineInstrSpan MIS ( MI , & MBB ) ; for ( const CalleeSavedInfo & CI : reverse ( CSI ) ) { Register Reg = CI . getReg ( ) ; if ( ! CI . isTargetSpilled ( ) ) continue ; if ( ! StackRegClass . contains ( Reg ) ) Reg = Builder . getMRI ( ) -> createVirtualRegister ( & StackRegClass ) ; Builder . buildInstr ( MOS :: PL , { Reg } , { } ) ; if ( Reg != CI . getReg ( ) ) Builder . buildCopy ( CI . getReg ( ) , Reg ) ; } visitReturnBlocks ( & MBB , [ & CSI ] ( MachineBasicBlock & MBB ) { assert ( MBB . rbegin ( ) -> isReturn ( ) ) ; for ( const CalleeSavedInfo & CI : CSI ) { MBB . rbegin ( ) -> addOperand ( MachineOperand :: CreateReg ( CI . getReg ( ) , false , true ) ) ; } } ) ; for ( auto & MI : make_range ( MIS . begin ( ) , MIS . getInitial ( ) ) ) MI . setFlag ( MachineInstr :: FrameDestroy ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .

MOS MOS MOS MOS MOS::GPRRegClass MOS::AcRegClass MOS::PL


<s> static void emit_unlikely_jump ( rtx cond , rtx label ) { int very_unlikely = REG_BR_PROB_BASE / 100 - 1 ; rtx x ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , cond , label , pc_rtx ) ; x = emit_jump_insn ( gen_rtx_SET ( pc_rtx , x ) ) ; add_int_reg_note ( x , REG_BR_PROB , very_unlikely ) ; } </s>

Mark the previous jump instruction as unlikely .


<s> bool WebAssemblyInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool ) const { const auto & MFI = * MBB . getParent ( ) -> getInfo < WebAssemblyFunctionInfo > ( ) ; if ( MFI . isCFGStackified ( ) ) return true ; bool HaveCond = false ; for ( MachineInstr & MI : MBB . terminators ( ) ) { switch ( MI . getOpcode ( ) ) { default : return true ; case WebAssembly :: BR_IF : if ( HaveCond ) return true ; Cond . push_back ( MachineOperand :: CreateImm ( true ) ) ; Cond . push_back ( MI . getOperand ( 1 ) ) ; TBB = MI . getOperand ( 0 ) . getMBB ( ) ; HaveCond = true ; break ; case WebAssembly :: BR_UNLESS : if ( HaveCond ) return true ; Cond . push_back ( MachineOperand :: CreateImm ( false ) ) ; Cond . push_back ( MI . getOperand ( 1 ) ) ; TBB = MI . getOperand ( 0 ) . getMBB ( ) ; HaveCond = true ; break ; case WebAssembly :: BR : if ( ! HaveCond ) TBB = MI . getOperand ( 0 ) . getMBB ( ) ; else FBB = MI . getOperand ( 0 ) . getMBB ( ) ; break ; } if ( MI . isBarrier ( ) ) break ; } return false ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


";;\tatom sched_reorder: put %d insn on top\n"

";;\tslm sched_reorder: swap %d and %d insns\n"

Perform possible reodering of ready list for Atom/Silvermont only . Return issue rate .


<s> static void loongarch_print_operand_address ( FILE * file , machine_mode , rtx x ) { struct loongarch_address_info addr ; if ( loongarch_classify_address ( & addr , x , word_mode , true ) ) switch ( addr . type ) { case ADDRESS_REG : fprintf ( file , "%s," , reg_names [ REGNO ( addr . reg ) ] ) ; loongarch_print_operand ( file , addr . offset , 0 ) ; return ; case ADDRESS_REG_REG : fprintf ( file , "%s,%s" , reg_names [ REGNO ( addr . reg ) ] , reg_names [ REGNO ( addr . offset ) ] ) ; return ; case ADDRESS_CONST_INT : fprintf ( file , "%s," , reg_names [ GP_REG_FIRST ] ) ; output_addr_const ( file , x ) ; return ; case ADDRESS_SYMBOLIC : output_addr_const ( file , loongarch_strip_unspec_address ( x ) ) ; return ; } if ( CONST_INT_P ( x ) ) output_addr_const ( file , x ) ; else gcc_unreachable ( ) ; } </s>


<s>
SDValue
F2003fTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_F2003f
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
F2003fISD
::
DOSNUD
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


"Dangerous instruction in branch delay slot!"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


Output assembly language to define a symbol as COMMON from a DECL , possibly with visibility .


<s> static int aarch64_reassociation_width ( unsigned opc , machine_mode mode ) { if ( VECTOR_MODE_P ( mode ) ) return aarch64_tune_params . vec_reassoc_width ; if ( INTEGRAL_MODE_P ( mode ) ) return aarch64_tune_params . int_reassoc_width ; if ( FLOAT_MODE_P ( mode ) && opc != PLUS_EXPR ) return aarch64_tune_params . fp_reassoc_width ; return 1 ; } </s>

Return the reassociation width of treeop OPC with mode MODE .


<s> const uint16_t * X86TargetLowering :: getScratchRegisters ( CallingConv :: ID ) const { static const uint16_t ScratchRegs [ ] = { X86 :: R11 , 0 } ; return ScratchRegs ; } </s>

Returns a 0 terminated array of registers that can be safely used as scratch registers .


<s> bool hasLowDefLatency ( const TargetSchedModel & SchedModel , const MachineInstr * DefMI , unsigned DefIdx ) const override { return false ; } </s>

Compute operand latency of a def of 'Reg ' .


<s> bool shouldInsertFencesForAtomic ( const Instruction * I ) const override { return true ; } </s>

Helper functions for atomic operations .


<s>
static
int
mt_arg_partial_bytes
(
CUMULATIVE_ARGS
*
pcum
,
enum
machine_mode
mode
,
tree
type
,
bool
named
ATTRIBUTE_UNUSED
)
{
int
cum
=
*
pcum
;
int
words
;
if
(
mode
==
BLKmode
)
words
=
(
(
int_size_in_bytes
(
type
)
+
UNITS_PER_WORD
1
)
/
UNITS_PER_WORD
)
;
else
words
=
(
GET_MODE_SIZE
(
mode
)
+
UNITS_PER_WORD
1
)
/
UNITS_PER_WORD
;
if
(
!
targetm
.
calls
.
pass_by_reference
(
&
cum
,
mode
,
type
,
named
)
&&
cum
<
MT_NUM_ARG_REGS
&&
(
cum
+
words
)
>
MT_NUM_ARG_REGS
)
{
int
bytes
=
(
MT_NUM_ARG_REGS
cum
)
*
UNITS_PER_WORD
;
if
(
TARGET_DEBUG
)
fprintf
(
stderr
,
"function_arg_partial_nregs = %d\n"
,
bytes
)
;
return
bytes
;
}
return
0
;
}
</s>

Implement hook TARGET_ARG_PARTIAL_BYTES . Returns the number of bytes at the beginning of an argument that must be put in registers . The value must be zero for arguments that are passed entirely in registers or that are entirely pushed on the stack .


<s>
bool
SystemZInstrInfo
::
PredicateInstruction
(
MachineInstr
&
MI
,
ArrayRef
<
MachineOperand
>
Pred
)
const
{
assert
(
Pred
.
size
(
)
==
2
&&
"Invalid condition"
)
;
unsigned
CCValid
=
Pred
[
0
]
.
getImm
(
)
;
unsigned
CCMask
=
Pred
[
1
]
.
getImm
(
)
;
assert
(
CCMask
>
0
&&
CCMask
<
15
&&
"Invalid predicate"
)
;
unsigned
Opcode
=
MI
.
getOpcode
(
)
;
if
(
Opcode
==
SystemZ
::
Trap
)
{
MI
.
setDesc
(
get
(
SystemZ
::
CondTrap
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
Return
)
{
MI
.
setDesc
(
get
(
SystemZ
::
CondReturn
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
CallJG
)
{
MachineOperand
FirstOp
=
MI
.
getOperand
(
0
)
;
const
uint32_t
*
RegMask
=
MI
.
getOperand
(
1
)
.
getRegMask
(
)
;
MI
.
RemoveOperand
(
1
)
;
MI
.
RemoveOperand
(
0
)
;
MI
.
setDesc
(
get
(
SystemZ
::
CallBRCL
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addOperand
(
FirstOp
)
.
addRegMask
(
RegMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
CallBR
)
{
const
uint32_t
*
RegMask
=
MI
.
getOperand
(
0
)
.
getRegMask
(
)
;
MI
.
RemoveOperand
(
0
)
;
MI
.
setDesc
(
get
(
SystemZ
::
CallBCR
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addRegMask
(
RegMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
return
false
;
}
</s>

Convert the instruction into a predicated instruction .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"FISC Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void riscv_d_target_versions ( void ) { if ( TARGET_64BIT ) d_add_builtin_version ( "RISCV64" ) ; else d_add_builtin_version ( "RISCV32" ) ; if ( TARGET_HARD_FLOAT ) d_add_builtin_version ( "D_HardFloat" ) ; else d_add_builtin_version ( "D_SoftFloat" ) ; } </s>

Implement TARGET_D_CPU_VERSIONS for RISC-V targets .


<s> StringRef getPassName ( ) const override { return AARCH64_VECTOR_BY_ELEMENT_OPT_NAME ; } </s>


<s> const VESubtarget * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> const char * TMS320C64XLowering :: getTargetNodeName ( unsigned op ) const { switch ( op ) { default : return NULL ; case TMSISD :: BRCOND : return "TMSISD::BRCOND" ; case TMSISD :: CALL : return "TMSISD::CALL" ; case TMSISD :: CMPEQ : return "TMSISD::CMPEQ" ; case TMSISD :: CMPNE : return "TMSISD::CMPNE" ; case TMSISD :: CMPGT : return "TMSISD::CMPGT" ; case TMSISD :: CMPGTU : return "TMSISD::CMPGTU" ; case TMSISD :: CMPLT : return "TMSISD::CMPLT" ; case TMSISD :: CMPLTU : return "TMSISD::CMPLTU" ; case TMSISD :: RETURN_FLAG : return "TMSISD::RETURN_FLAG" ; case TMSISD :: RETURN_LABEL : return "TMSISD::RETURN_LABEL" ; case TMSISD :: RETURN_LABEL_OPERAND : return "TMSISD::RETURN_LABEL_OPERAND" ; case TMSISD :: WRAPPER : return "TMSISD::WRAPPER" ; case TMSISD :: TSC_START : return "TMSISD::TSC_START" ; case TMSISD :: TSC_END : return "TMSISD::TSC_END" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s>
CCAssignFn
*
AArch64TargetLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
const
{
switch
(
CC
)
{
default
:
report_fatal_error
(
"Unsupported calling convention."
)
;
case
CallingConv
::
WebKit_JS
:
return
CC_AArch64_WebKit_JS
;
case
CallingConv
::
GHC
:
return
CC_AArch64_GHC
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
case
CallingConv
::
PreserveMost
:
case
CallingConv
::
CXX_FAST_TLS
:
case
CallingConv
::
Swift
:
case
CallingConv
::
SwiftTail
:
case
CallingConv
::
Tail
:
if
(
Subtarget
->
isTargetWindows
(
)
&&
IsVarArg
)
return
CC_AArch64_Win64_VarArg
;
if
(
!
Subtarget
->
isTargetDarwin
(
)
)
return
CC_AArch64_AAPCS
;
if
(
!
IsVarArg
)
return
CC_AArch64_DarwinPCS
;
return
Subtarget
->
isTargetILP32
(
)
CC_AArch64_DarwinPCS_ILP32_VarArg
:
CC_AArch64_DarwinPCS_VarArg
;
case
CallingConv
::
Win64
:
return
IsVarArg
CC_AArch64_Win64_VarArg
:
CC_AArch64_AAPCS
;
case
CallingConv
::
CFGuard_Check
:
return
CC_AArch64_Win64_CFGuard_Check
;
case
CallingConv
::
AArch64_VectorCall
:
case
CallingConv
::
AArch64_SVE_VectorCall
:
return
CC_AArch64_AAPCS
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> bool Thumb2InstrInfo :: isLegalToSplitMBBAt ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) const { while ( MBBI -> isDebugValue ( ) ) { ++ MBBI ; if ( MBBI == MBB . end ( ) ) return false ; } unsigned PredReg = 0 ; return llvm :: getITInstrPredicate ( MBBI , PredReg ) == ARMCC :: AL ; } </s>

Return true if it 's legal to split the given basic block at the specified instruction ( i.e .


<s> bool ARMConstantPoolValue :: hasSameValue ( ARMConstantPoolValue * ACPV ) { if ( ACPV -> Kind == Kind && ACPV -> PCAdjust == PCAdjust && ACPV -> Modifier == Modifier && ACPV -> LabelId == LabelId && ACPV -> AddCurrentAddress == AddCurrentAddress ) { if ( Kind == ARMCP :: CPValue || Kind == ARMCP :: CPExtSymbol ) return true ; } return false ; } </s>

hasSameValue - Return true if this ARM constpool value can share the same constantpool entry as another ARM constpool value .

ARM ARM ARM ARMCP::CPValue ARMCP::CPExtSymbol


<s> std :: string Stack :: toString ( ) const { std :: string buf ; raw_string_ostream os ( buf ) ; print ( os ) ; os . flush ( ) ; return buf ; } </s>

Convert to a decimal representation in a string .


Implement TARGET_REMOVE_EXTRA_CALL_PRESERVED_REGS . If INSN calls a function that uses the SIMD ABI , take advantage of the extra call-preserved registers that the ABI provides .


<s> bool isImm ( ) const { return Kind == Immediate ; } </s>


<s> bool aarch64_sve_prefetch_operand_p ( rtx op , machine_mode mode ) { struct aarch64_address_info addr ; if ( ! aarch64_classify_address ( & addr , op , mode , false ) ) return false ; if ( addr . type == ADDRESS_REG_IMM ) return known_eq ( addr . const_offset , 0 ) ; return addr . type == ADDRESS_REG_REG ; } </s>

Return true if OP is a valid address for an SVE PRF [ BHWD ] instruction , addressing memory of mode MODE .


<s>
static
rtx
pru_expand_builtin
(
tree
exp
,
rtx
target
,
rtx
subtarget
ATTRIBUTE_UNUSED
,
machine_mode
mode
,
int
ignore
ATTRIBUTE_UNUSED
)
{
tree
fndecl
=
TREE_OPERAND
(
CALL_EXPR_FN
(
exp
)
,
0
)
;
unsigned
int
fcode
=
DECL_MD_FUNCTION_CODE
(
fndecl
)
;
switch
(
fcode
)
{
case
PRU_BUILTIN_DELAY_CYCLES
:
{
rtx
arg1
=
expand_normal
(
CALL_EXPR_ARG
(
exp
,
0
)
)
;
return
pru_expand_delay_cycles
(
arg1
)
;
}
break
;
case
PRU_BUILTIN_HALT
:
{
emit_insn
(
gen_pru_halt
(
)
)
;
return
NULL_RTX
;
}
break
;
case
PRU_BUILTIN_LMBD
:
{
rtx
arg1
=
expand_normal
(
CALL_EXPR_ARG
(
exp
,
0
)
)
;
rtx
arg2
=
expand_normal
(
CALL_EXPR_ARG
(
exp
,
1
)
)
;
if
(
target
==
NULL_RTX
||
GET_MODE
(
target
)
!=
mode
)
{
target
=
gen_reg_rtx
(
mode
)
;
}
emit_insn
(
gen_pru_lmbd
(
mode
,
target
,
arg1
,
arg2
)
)
;
return
target
;
}
break
;
default
:
internal_error
(
"bad builtin code"
)
;
}
return
NULL_RTX
;
}
</s>

Implement TARGET_EXPAND_BUILTIN . Expand an expression EXP that calls a built-in function , with result going to TARGET if that 's convenient ( and in mode MODE if that 's convenient ) . SUBTARGET may be used as the target for computing one of EXP 's operands . IGNORE is nonzero if the value is to be ignored .


<s>
MCSection
*
XCoreTargetObjectFile
::
getSectionForConstant
(
SectionKind
Kind
,
const
Constant
*
C
)
const
{
if
(
Kind
.
isMergeableConst4
(
)
)
return
MergeableConst4Section
;
if
(
Kind
.
isMergeableConst8
(
)
)
return
MergeableConst8Section
;
if
(
Kind
.
isMergeableConst16
(
)
)
return
MergeableConst16Section
;
assert
(
(
Kind
.
isReadOnly
(
)
||
Kind
.
isReadOnlyWithRel
(
)
)
&&
"Unknown section kind"
)
;
return
ReadOnlySection
;
}
</s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> static bool loongarch_index_address_p ( rtx addr , machine_mode mode ATTRIBUTE_UNUSED ) { if ( GET_CODE ( addr ) != PLUS || ! REG_P ( XEXP ( addr , 0 ) ) || ! REG_P ( XEXP ( addr , 1 ) ) ) return false ; return true ; } </s>

Return true if ADDR matches the pattern for the indexed address instruction .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"NVPTX specific alloca hoisting"
;
}
</s>


<s> bool riscv_can_use_return_insn ( void ) { return reload_completed && cfun -> machine -> frame . total_size == 0 ; } </s>

Return nonzero if this function is known to have a null epilogue . This allows the optimizer to omit jumps to jumps if no stack was created .


<s> bool check_colliding_tags ( const rtx & t , const insn_info_list_t & v , arg_pair_t * arg ) { HARD_REG_SET * unavailable = arg -> second ; unsigned orig_tag = arg -> first -> tag ( ) ; unsigned tag = INTVAL ( t ) ; machine_mode mode = GET_MODE ( arg -> first -> dest ) ; if ( v . length ( ) == 0 ) return true ; if ( TAG_UPDATE_DEST ( tag , 0 ) == TAG_UPDATE_DEST ( orig_tag , 0 ) ) ignore_all_aliases ( unavailable , mode , TAG_GET_DEST ( tag ) ) ; return true ; } </s>

Callback to check which destination registers are unavailable to us for renaming because of the base and offset colliding . This is a callback that gets called for every name value pair ( T , V ) in the TAG_MAP . The ARG is an std : :pair of the tag_insn_info of the original insn and the hard register set UNAVAILABLE that is used to record hard register numbers that can not be used for the renaming . This always returns true since we want to traverse through the entire TAG_MAP .


<s> static void ft32_setup_incoming_varargs ( cumulative_args_t cum_v , enum machine_mode mode ATTRIBUTE_UNUSED , tree type ATTRIBUTE_UNUSED , int * pretend_size , int no_rtl ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int regno ; int regs = 8 - * cum ; * pretend_size = regs < 0 ? 0 : GET_MODE_SIZE ( SImode ) * regs ; if ( no_rtl ) return ; for ( regno = * cum ; regno < 8 ; regno ++ ) { rtx reg = gen_rtx_REG ( SImode , regno ) ; rtx slot = gen_rtx_PLUS ( Pmode , gen_rtx_REG ( SImode , ARG_POINTER_REGNUM ) , GEN_INT ( UNITS_PER_WORD * ( regno - FT32_R0 ) ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , slot ) , reg ) ; } } </s>

Worker function for TARGET_SETUP_INCOMING_VARARGS .


<s>
void
SIInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
SIMachineFunctionInfo
*
MFI
=
MF
->
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MachineFrameInfo
&
FrameInfo
=
MF
->
getFrameInfo
(
)
;
const
DebugLoc
&
DL
=
MBB
.
findDebugLoc
(
MI
)
;
unsigned
Size
=
FrameInfo
.
getObjectSize
(
FrameIndex
)
;
unsigned
Align
=
FrameInfo
.
getObjectAlignment
(
FrameIndex
)
;
MachinePointerInfo
PtrInfo
=
MachinePointerInfo
::
getFixedStack
(
*
MF
,
FrameIndex
)
;
MachineMemOperand
*
MMO
=
MF
->
getMachineMemOperand
(
PtrInfo
,
MachineMemOperand
::
MOStore
,
Size
,
Align
)
;
unsigned
SpillSize
=
TRI
->
getSpillSize
(
*
RC
)
;
if
(
RI
.
isSGPRClass
(
RC
)
)
{
MFI
->
setHasSpilledSGPRs
(
)
;
assert
(
SrcReg
!=
AMDGPU
::
M0
&&
"m0 should not be spilled"
)
;
const
MCInstrDesc
&
OpDesc
=
get
(
getSGPRSpillSaveOpcode
(
SpillSize
)
)
;
if
(
Register
::
isVirtualRegister
(
SrcReg
)
&&
SpillSize
==
4
)
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
MRI
.
constrainRegClass
(
SrcReg
,
&
AMDGPU
::
SReg_32_XM0RegClass
)
;
}
BuildMI
(
MBB
,
MI
,
DL
,
OpDesc
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIndex
)
.
addMemOperand
(
MMO
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
,
RegState
::
Implicit
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
,
RegState
::
Implicit
)
;
if
(
RI
.
spillSGPRToVGPR
(
)
)
FrameInfo
.
setStackID
(
FrameIndex
,
TargetStackID
::
SGPRSpill
)
;
return
;
}
unsigned
Opcode
=
RI
.
hasAGPRs
(
RC
)
getAGPRSpillSaveOpcode
(
SpillSize
)
:
getVGPRSpillSaveOpcode
(
SpillSize
)
;
MFI
->
setHasSpilledVGPRs
(
)
;
auto
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opcode
)
)
;
if
(
RI
.
hasAGPRs
(
RC
)
)
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
Register
Tmp
=
MRI
.
createVirtualRegister
(
&
AMDGPU
::
VGPR_32RegClass
)
;
MIB
.
addReg
(
Tmp
,
RegState
::
Define
)
;
}
MIB
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIndex
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> unsigned SIInstrInfo :: getAddressSpaceForPseudoSourceKind ( PseudoSourceValue :: PSVKind Kind ) const { switch ( Kind ) { case PseudoSourceValue :: Stack : case PseudoSourceValue :: FixedStack : return ST . getAMDGPUAS ( ) . PRIVATE_ADDRESS ; case PseudoSourceValue :: ConstantPool : case PseudoSourceValue :: GOT : case PseudoSourceValue :: JumpTable : case PseudoSourceValue :: GlobalValueCallEntry : case PseudoSourceValue :: ExternalSymbolCallEntry : case PseudoSourceValue :: TargetCustom : return ST . getAMDGPUAS ( ) . CONSTANT_ADDRESS ; } return ST . getAMDGPUAS ( ) . FLAT_ADDRESS ; } </s>

getAddressSpaceForPseudoSourceKind - Given the kind of memory ( e.g .


<s> const uint16_t * XNCMRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { XNCM :: LR , 0 } ; return CalleeSavedRegs ; } </s>


<s>
void
AArch64AsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
,
MCContext
&
Ctx
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
Ctx
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
unsigned
FulleSizeInBytes
=
getFixupKindContainereSizeInBytes
(
Fixup
.
getKind
(
)
)
;
if
(
FulleSizeInBytes
==
0
)
{
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
else
{
assert
(
(
Offset
+
FulleSizeInBytes
)
<=
DataSize
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FulleSizeInBytes
&&
"Invalid fixup size!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
FulleSizeInBytes
1
i
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> unsigned HexagonInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { case Hexagon :: LDriw : case Hexagon :: LDrid : case Hexagon :: LDrih : case Hexagon :: LDrib : case Hexagon :: LDriub : if ( MI -> getOperand ( 2 ) . isFI ( ) && MI -> getOperand ( 1 ) . isImm ( ) && ( MI -> getOperand ( 1 ) . getImm ( ) == 0 ) ) { FrameIndex = MI -> getOperand ( 2 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; default : break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> void FISCInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( FISC :: LDR ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s>
unsigned
getReg
(
)
const
{
assert
(
Kind
==
Register
&&
"Invalid access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s>
void
ft32_print_operand
(
FILE
*
file
,
rtx
x
,
int
code
)
{
rtx
operand
=
x
;
switch
(
code
)
{
case
0
:
break
;
case
'h'
:
if
(
GET_CODE
(
operand
)
!=
REG
)
internal_error
(
"'h' applied to non-register operand"
)
;
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
operand
)
+
1
]
)
;
return
;
case
'm'
:
fprintf
(
file
,
"%ld"
,
(
long
)
(
INTVAL
(
x
)
)
)
;
return
;
case
'd'
:
{
int
i
=
INTVAL
(
x
)
;
char
dwspec
;
switch
(
i
)
{
case
1
:
dwspec
=
'b'
;
break
;
case
2
:
dwspec
=
's'
;
break
;
case
4
:
dwspec
=
'l'
;
break
;
default
:
if
(
(
i
%
4
)
!=
0
)
internal_error
(
"bad alignment: %d"
,
i
)
;
else
dwspec
=
'l'
;
break
;
}
fprintf
(
file
,
"%c"
,
dwspec
)
;
return
;
}
case
'f'
:
{
int
bf
=
ft32_as_bitfield
(
INTVAL
(
x
)
)
;
fprintf
(
file
,
"512|(%d<<5)|%d"
,
bf
>>
5
,
bf
&
31
)
;
return
;
}
case
'g'
:
{
int
bf
=
ft32_as_bitfield
(
0xffffffff
^
INTVAL
(
x
)
)
;
fprintf
(
file
,
"(%d<<5)|%d"
,
bf
>>
5
,
bf
&
31
)
;
return
;
}
case
'b'
:
{
ft32_print_operand
(
file
,
XEXP
(
x
,
0
)
,
0
)
;
return
;
}
default
:
LOSE_AND_RETURN
(
"invalid operand modifier letter"
,
x
)
;
}
switch
(
GET_CODE
(
operand
)
)
{
case
REG
:
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
operand
)
]
)
;
return
;
case
MEM
:
output_address
(
GET_MODE
(
XEXP
(
operand
,
0
)
)
,
XEXP
(
operand
,
0
)
)
;
return
;
default
:
if
(
CONSTANT_P
(
operand
)
)
{
output_addr_const
(
file
,
operand
)
;
return
;
}
LOSE_AND_RETURN
(
"unexpected operand"
,
x
)
;
}
}
</s>


<s> bool canOpTrap ( unsigned Op , EVT VT ) const override { return false ; } </s>

Returns true if the operation can trap for the value type .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"R600 Texture Intrinsics Replacer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool rx_is_restricted_memory_address ( rtx mem , machine_mode mode ) { if ( ! rx_is_legitimate_address ( mode , mem , reload_in_progress || reload_completed ) ) return false ; switch ( GET_CODE ( mem ) ) { case REG : return true ; case SUBREG : return RX_REG_P ( SUBREG_REG ( mem ) ) ; case PRE_DEC : case POST_INC : return false ; case PLUS : { rtx base , index ; base = XEXP ( mem , 0 ) ; index = XEXP ( mem , 1 ) ; if ( ! RX_REG_P ( base ) || ! CONST_INT_P ( index ) ) return false ; return IN_RANGE ( INTVAL ( index ) , 0 , ( 0x10000 * GET_MODE_SIZE ( mode ) ) - 1 ) ; } case SYMBOL_REF : return true ; default : gcc_unreachable ( ) ; } } </s>

Returns TRUE for simple memory addreses , ie ones that do not involve register indirect addressing or pre/post increment/decrement .


<s> static void push_regs ( unsigned int high , unsigned int low ) { rtx insn ; if ( low == high ) insn = emit_insn ( gen_stack_push ( gen_rtx_REG ( SImode , low ) ) ) ; else insn = emit_insn ( gen_stack_pushm ( GEN_INT ( ( ( high - low ) + 1 ) * UNITS_PER_WORD ) , gen_rx_store_vector ( low , high ) ) ) ; mark_frame_related ( insn ) ; } </s>

Generate code to push the regs specified in the mask . remember that the mask is of the internal shape of the regs , not the external shape - so go through the renumber vector


<s> unsigned int compute_a_shift_length ( rtx insn ATTRIBUTE_UNUSED , rtx * operands ) { rtx shift = operands [ 3 ] ; machine_mode mode = GET_MODE ( shift ) ; enum rtx_code code = GET_CODE ( shift ) ; enum shift_type shift_type ; enum shift_mode shift_mode ; struct shift_info info ; unsigned int wlength = 0 ; switch ( mode ) { case QImode : shift_mode = QIshift ; break ; case HImode : shift_mode = HIshift ; break ; case SImode : shift_mode = SIshift ; break ; default : gcc_unreachable ( ) ; } switch ( code ) { case ASHIFTRT : shift_type = SHIFT_ASHIFTRT ; break ; case LSHIFTRT : shift_type = SHIFT_LSHIFTRT ; break ; case ASHIFT : shift_type = SHIFT_ASHIFT ; break ; default : gcc_unreachable ( ) ; } if ( GET_CODE ( operands [ 2 ] ) != CONST_INT ) { get_shift_alg ( shift_type , shift_mode , 1 , & info ) ; return ( 4 + h8300_asm_insn_count ( info . shift1 ) ) * 2 ; } else { int n = INTVAL ( operands [ 2 ] ) ; if ( n < 0 ) n = 0 ; else if ( ( unsigned int ) n > GET_MODE_BITSIZE ( mode ) ) n = GET_MODE_BITSIZE ( mode ) ; get_shift_alg ( shift_type , shift_mode , n , & info ) ; switch ( info . alg ) { case SHIFT_SPECIAL : wlength += h8300_asm_insn_count ( info . special ) ; if ( strstr ( info . special , "xor.l" ) != NULL ) wlength ++ ; case SHIFT_INLINE : n = info . remainder ; if ( info . shift2 != NULL ) { wlength += h8300_asm_insn_count ( info . shift2 ) * ( n / 2 ) ; n = n % 2 ; } wlength += h8300_asm_insn_count ( info . shift1 ) * n ; return 2 * wlength ; case SHIFT_ROT_AND : { int m = GET_MODE_BITSIZE ( mode ) - n ; gcc_assert ( info . shift1 ) ; if ( info . shift2 != NULL ) { wlength += h8300_asm_insn_count ( info . shift2 ) * ( m / 2 ) ; m = m % 2 ; } wlength += h8300_asm_insn_count ( info . shift1 ) * m ; switch ( mode ) { case QImode : wlength += 1 ; break ; case HImode : wlength += 2 ; break ; case SImode : gcc_assert ( ! TARGET_H8300 ) ; wlength += 3 ; break ; default : gcc_unreachable ( ) ; } return 2 * wlength ; } case SHIFT_LOOP : if ( info . shift2 != NULL ) { wlength += 3 + h8300_asm_insn_count ( info . shift2 ) ; if ( n % 2 ) wlength += h8300_asm_insn_count ( info . shift1 ) ; } else { wlength += 3 + h8300_asm_insn_count ( info . shift1 ) ; } return 2 * wlength ; default : gcc_unreachable ( ) ; } } } </s>


<s> static unsigned selectBinaryOp ( unsigned GenericOpc , unsigned RegBankID , unsigned OpSize ) { switch ( RegBankID ) { case AArch64 :: GPRRegBankID : switch ( OpSize ) { case 32 : switch ( GenericOpc ) { case TargetOpcode :: G_OR : return AArch64 :: ORRWrr ; case TargetOpcode :: G_XOR : return AArch64 :: EORWrr ; case TargetOpcode :: G_AND : return AArch64 :: ANDWrr ; case TargetOpcode :: G_ADD : return AArch64 :: ADDWrr ; case TargetOpcode :: G_SUB : return AArch64 :: SUBWrr ; default : return GenericOpc ; } case 64 : switch ( GenericOpc ) { case TargetOpcode :: G_OR : return AArch64 :: ORRXrr ; case TargetOpcode :: G_XOR : return AArch64 :: EORXrr ; case TargetOpcode :: G_AND : return AArch64 :: ANDXrr ; case TargetOpcode :: G_ADD : return AArch64 :: ADDXrr ; case TargetOpcode :: G_SUB : return AArch64 :: SUBXrr ; default : return GenericOpc ; } } } ; return GenericOpc ; } </s>

Select and emit code for a binary operator instruction , which has an opcode which directly corresponds to the given ISD opcode .


<s> uint64_t HexagonGNUInfo :: flags ( ) const { return llvm :: StringSwitch < uint64_t > ( m_Options . getTargetCPU ( ) ) . Case ( "hexagonv4" , V4 ) . Case ( "hexagonv5" , V5 ) . Default ( V4 ) ; } </s>

Get the flags for this GlobalValue ( see struct GVFlags ) .


<s> Value * RISCVTargetLowering :: emitMaskedAtomicCmpXchgIntrinsic ( IRBuilder < > & Builder , AtomicCmpXchgInst * CI , Value * AlignedAddr , Value * CmpVal , Value * NewVal , Value * Mask , AtomicOrdering Ord ) const { unsigned XLen = Subtarget . getXLen ( ) ; Value * Ordering = Builder . getIntN ( XLen , static_cast < uint64_t > ( Ord ) ) ; Intrinsic :: ID CmpXchgIntrID = Intrinsic :: riscv_masked_cmpxchg_i32 ; if ( XLen == 64 ) { CmpVal = Builder . CreateSExt ( CmpVal , Builder . getInt64Ty ( ) ) ; NewVal = Builder . CreateSExt ( NewVal , Builder . getInt64Ty ( ) ) ; Mask = Builder . CreateSExt ( Mask , Builder . getInt64Ty ( ) ) ; CmpXchgIntrID = Intrinsic :: riscv_masked_cmpxchg_i64 ; } Type * Tys [ ] = { AlignedAddr -> getType ( ) } ; Function * MaskedCmpXchg = Intrinsic :: getDeclaration ( CI -> getModule ( ) , CmpXchgIntrID , Tys ) ; Value * Result = Builder . CreateCall ( MaskedCmpXchg , { AlignedAddr , CmpVal , NewVal , Mask , Ordering } ) ; if ( XLen == 64 ) Result = Builder . CreateTrunc ( Result , Builder . getInt32Ty ( ) ) ; return Result ; } </s>

Perform a masked cmpxchg using a target-specific intrinsic .


<s> bool X86TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { for ( unsigned i = 0 , e = LegalFPImmediates . size ( ) ; i != e ; ++ i ) { if ( Imm . bitwiseIsEqual ( LegalFPImmediates [ i ] ) ) return true ; } return false ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> bool ARMAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == ".word" ) return parseDirectiveWord ( 4 , DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".thumb" ) return parseDirectiveThumb ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".thumb_func" ) return parseDirectiveThumbFunc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".code" ) return parseDirectiveCode ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".syntax" ) return parseDirectiveSyntax ( DirectiveID . getLoc ( ) ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> void BPFAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const { if ( Fixup . getKind ( ) == FK_SecRel_4 || Fixup . getKind ( ) == FK_SecRel_8 ) { assert ( Value == 0 ) ; } else if ( Fixup . getKind ( ) == FK_Data_4 || Fixup . getKind ( ) == FK_Data_8 ) { unsigned Size = Fixup . getKind ( ) == FK_Data_4 ? 4 : 8 ; for ( unsigned i = 0 ; i != Size ; ++ i ) { unsigned Idx = IsLittleEndian ? i : Size - i - 1 ; Data [ Fixup . getOffset ( ) + Idx ] = uint8_t ( Value >> ( i * 8 ) ) ; } } else if ( Fixup . getKind ( ) == FK_PCRel_4 ) { Value = ( uint32_t ) ( ( Value - 8 ) / 8 ) ; if ( IsLittleEndian ) { Data [ Fixup . getOffset ( ) + 1 ] = 0x10 ; support :: endian :: write32le ( & Data [ Fixup . getOffset ( ) + 4 ] , Value ) ; } else { Data [ Fixup . getOffset ( ) + 1 ] = 0x1 ; support :: endian :: write32be ( & Data [ Fixup . getOffset ( ) + 4 ] , Value ) ; } } else { assert ( Fixup . getKind ( ) == FK_PCRel_2 ) ; Value = ( uint16_t ) ( ( Value - 8 ) / 8 ) ; if ( IsLittleEndian ) { Data [ Fixup . getOffset ( ) + 2 ] = Value & 0xFF ; Data [ Fixup . getOffset ( ) + 3 ] = Value >> 8 ; } else { Data [ Fixup . getOffset ( ) + 2 ] = Value >> 8 ; Data [ Fixup . getOffset ( ) + 3 ] = Value & 0xFF ; } } } </s>


<s>
bool
LC2200AsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
if
(
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MatchingInlineAsm
)
)
{
Out
.
EmitInstruction
(
Inst
,
this
->
STI
)
;
return
false
;
}
else
{
return
Error
(
IDLoc
,
"Error Parsing Instruction"
)
;
}
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s>
static
uint16_t
name
(
struct
InternalInstruction
*
insn
,
\
OperandType
type
,
\
uint8_t
index
,
\
uint8_t
*
valid
)
{
\
*
valid
=
1
;
\
switch
(
type
)
{
\
default
:
\
debug
(
"Unhandled register type"
)
;
\
*
valid
=
0
;
\
return
0
;
\
case
TYPE_Rv
:
\
return
base
+
index
;
\
case
TYPE_R8
:
\
if
(
insn
->
rexPrefix
&&
\
index
>=
4
&&
index
<=
7
)
{
\
return
prefix
##
_SPL
+
(
index
4
)
;
\
}
else
{
\
return
prefix
##
_AL
+
index
;
\
}
\
case
TYPE_R16
:
\
return
prefix
##
_AX
+
index
;
\
case
TYPE_R32
:
\
return
prefix
##
_EAX
+
index
;
\
case
TYPE_R64
:
\
return
prefix
##
_RAX
+
index
;
\
case
TYPE_ZMM
:
\
return
prefix
##
_ZMM0
+
index
;
\
case
TYPE_YMM
:
\
return
prefix
##
_YMM0
+
index
;
\
case
TYPE_XMM
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_VK
:
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_K0
+
index
;
\
case
TYPE_MM64
:
\
return
prefix
##
_MM0
+
(
index
&
0x7
)
;
\
case
TYPE_SEGMENTREG
:
\
if
(
index
>
5
)
\
*
valid
=
0
;
\
return
prefix
##
_ES
+
index
;
\
case
TYPE_DEBUGREG
:
\
return
prefix
##
_DR0
+
index
;
\
case
TYPE_CONTROLREG
:
\
return
prefix
##
_CR0
+
index
;
\
case
TYPE_BNDR
:
\
if
(
index
>
3
)
\
*
valid
=
0
;
\
return
prefix
##
_BND0
+
index
;
\
}
\
}
</s>

Gets the name of the pass we are mixed into .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
PPC
::
NumTargetFixupKinds
]
=
{
{
"fixup_ppc_br24"
,
6
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_brcond14"
,
16
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_br24abs"
,
6
,
24
,
0
}
,
{
"fixup_ppc_brcond14abs"
,
16
,
14
,
0
}
,
{
"fixup_ppc_half16"
,
0
,
16
,
0
}
,
{
"fixup_ppc_half16ds"
,
0
,
14
,
0
}
,
{
"fixup_ppc_tlsreg"
,
0
,
0
,
0
}
,
{
"fixup_ppc_nofixup"
,
0
,
0
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


"FPDelta isn't aligned per the Win64 ABI!"

"VLAs and dynamic stack realign, but no FP?!"

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> bool SIAnnotateControlFlow :: isUniform ( BranchInst * T ) { return DA -> isUniform ( T -> getCondition ( ) ) || T -> getMetadata ( "structurizecfg.uniform" ) != nullptr ; } </s>

Returns true if value V is uniform across VF lanes , when VF is provided , and otherwise if V is invariant across all loop iterations .


<s> bool xlogue_layout :: is_stub_managed_reg ( unsigned regno , unsigned count ) { bool hfp = frame_pointer_needed || stack_realign_fp ; unsigned i ; for ( i = 0 ; i < count ; ++ i ) { gcc_assert ( i < MAX_REGS ) ; if ( REG_ORDER [ i ] == BP_REG && hfp ) ++ count ; else if ( REG_ORDER [ i ] == regno ) return true ; } return false ; } </s>

Determine if register REGNO is a stub managed register given the total COUNT of stub managed registers .


<s> bool X86InstrInfo :: shouldScheduleLoadsNear ( SDNode * Load1 , SDNode * Load2 , int64_t Offset1 , int64_t Offset2 , unsigned NumLoads ) const { assert ( Offset2 > Offset1 ) ; if ( ( Offset2 - Offset1 ) / 8 > 64 ) return false ; unsigned Opc1 = Load1 -> getMachineOpcode ( ) ; unsigned Opc2 = Load2 -> getMachineOpcode ( ) ; if ( Opc1 != Opc2 ) return false ; switch ( Opc1 ) { default : break ; case X86 :: LD_Fp32m : case X86 :: LD_Fp64m : case X86 :: LD_Fp80m : case X86 :: MMX_MOVD64rm : case X86 :: MMX_MOVQ64rm : return false ; } EVT VT = Load1 -> getValueType ( 0 ) ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : if ( Subtarget . is64Bit ( ) ) { if ( NumLoads >= 3 ) return false ; } else if ( NumLoads ) { return false ; } break ; case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : case MVT :: i64 : case MVT :: f32 : case MVT :: f64 : if ( NumLoads ) return false ; break ; } return true ; } </s>

shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine ( in conjunction with areLoadsFromSameBasePtr ) if two loads should be scheduled togther .


<s> void RV16KFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( hasFP ( MF ) ) { SavedRegs . set ( RV16K :: X0 ) ; SavedRegs . set ( RV16K :: X2 ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


"256-bit vector operations only available in AVX2"

"256-bit insert/extract only available in AVX2"

Change the opcode of MI to execute in Domain .


<s> static void rs6000_finish_cost ( void * data , unsigned * prologue_cost , unsigned * body_cost , unsigned * epilogue_cost ) { rs6000_cost_data * cost_data = ( rs6000_cost_data * ) data ; if ( cost_data -> loop_info ) rs6000_density_test ( cost_data ) ; if ( cost_data -> loop_info ) { loop_vec_info vec_info = loop_vec_info_for_loop ( cost_data -> loop_info ) ; if ( ! rs6000_vect_nonmem && LOOP_VINFO_VECT_FACTOR ( vec_info ) == 2 && LOOP_REQUIRES_VERSIONING ( vec_info ) ) cost_data -> cost [ vect_body ] += 10000 ; } * prologue_cost = cost_data -> cost [ vect_prologue ] ; * body_cost = cost_data -> cost [ vect_body ] ; * epilogue_cost = cost_data -> cost [ vect_epilogue ] ; } </s>


<s> void AArch64TargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( Subtarget -> getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) ) { M . getOrInsertGlobal ( "__security_cookie" , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; FunctionCallee SecurityCheckCookie = M . getOrInsertFunction ( "__security_check_cookie" , Type :: getVoidTy ( M . getContext ( ) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; if ( Function * F = dyn_cast < Function > ( SecurityCheckCookie . getCallee ( ) ) ) { F -> setCallingConv ( CallingConv :: Win64 ) ; F -> addParamAttr ( 0 , Attribute :: AttrKind :: InReg ) ; } return ; } TargetLowering :: insertSSPDeclarations ( M ) ; } </s>

Inserts necessary declarations for SSP ( stack protection ) purpose .


<s> bool iq2000_can_eliminate ( const int from , const int to ) { return ( from == RETURN_ADDRESS_POINTER_REGNUM && ( ! leaf_function_p ( ) || ( to == GP_REG_FIRST + 31 && leaf_function_p ( ) ) ) ) || ( from != RETURN_ADDRESS_POINTER_REGNUM && ( to == HARD_FRAME_POINTER_REGNUM || ( to == STACK_POINTER_REGNUM && ! frame_pointer_needed ) ) ) ; } </s>

We can always eliminate to the frame pointer . We can eliminate to the stack pointer unless a frame pointer is needed .


<s> bool HexagonCopyToCombine :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; if ( IsCombinesDisabled ) return false ; bool HasChanged = false ; ST = & MF . getSubtarget < HexagonSubtarget > ( ) ; TRI = ST -> getRegisterInfo ( ) ; TII = ST -> getInstrInfo ( ) ; const Function & F = MF . getFunction ( ) ; bool OptForSize = F . hasFnAttribute ( Attribute :: OptimizeForSize ) ; ShouldCombineAggressively = MF . getTarget ( ) . getOptLevel ( ) <= CodeGenOpt :: Default ; if ( ! OptForSize && ST -> isTinyCore ( ) ) IsConst64Disabled = true ; for ( MachineBasicBlock & MBB : MF ) { PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( MBB ) ; for ( MachineBasicBlock :: iterator MI = MBB . begin ( ) , End = MBB . end ( ) ; MI != End ; ) { MachineInstr & I1 = * MI ++ ; if ( I1 . isDebugInstr ( ) ) continue ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( & I1 ) ) continue ; if ( ! isCombinableInstType ( I1 , TII , ShouldCombineAggressively ) ) continue ; bool DoInsertAtI1 = false ; DbgMItoMove . clear ( ) ; MachineInstr * I2 = findPairable ( I1 , DoInsertAtI1 , OptForSize ) ; if ( I2 ) { HasChanged = true ; combine ( I1 , * I2 , MI , DoInsertAtI1 , OptForSize ) ; } } } return HasChanged ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool AArch64InstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF , bool OutlineFromLinkOnceODRs ) const { const Function & F = MF . getFunction ( ) ; if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) ) return false ; if ( F . hasSection ( ) ) return false ; AArch64FunctionInfo * AFI = MF . getInfo < AArch64FunctionInfo > ( ) ; if ( ! AFI || AFI -> hasRedZone ( ) . getValueOr ( true ) ) return false ; return true ; } </s>

Return true if the function can safely be outlined from .


<s> void LC3FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( I -> getOpcode ( ) == LC3 :: ADJCALLSTACKUP || I -> getOpcode ( ) == LC3 :: ADJCALLSTACKDOWN ) { MBB . erase ( I ) ; } return ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static int visium_memory_move_cost ( enum machine_mode mode , reg_class_t to ATTRIBUTE_UNUSED , bool in ) { if ( in ) { if ( GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD ) return 7 ; else return 13 ; } else { if ( GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD ) return 6 ; else return 12 ; } } </s>

Return the cost of moving data of mode MODE between a register of class CLASS and memory . IN is zero if the value is to be written to memory , non-zero if it is to be read in . This cost is relative to those in visium_register_move_cost .


<s> rtx ix86_find_base_term ( rtx x ) { rtx term ; if ( TARGET_64BIT ) { if ( GET_CODE ( x ) != CONST ) return x ; term = XEXP ( x , 0 ) ; if ( GET_CODE ( term ) == PLUS && CONST_INT_P ( XEXP ( term , 1 ) ) ) term = XEXP ( term , 0 ) ; if ( GET_CODE ( term ) != UNSPEC || ( XINT ( term , 1 ) != UNSPEC_GOTPCREL && XINT ( term , 1 ) != UNSPEC_PCREL ) ) return x ; return XVECEXP ( term , 0 , 0 ) ; } return ix86_delegitimize_address ( x ) ; } </s>

If X is a machine specific address ( i.e . a symbol or label being referenced as a displacement from the GOT implemented using an UNSPEC ) , then return the base term . Otherwise return X .


<s> const AGCInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> bool tilegx_can_use_return_insn_p ( void ) { return ( reload_completed && ! cfun -> static_chain_decl && ! compute_total_frame_size ( ) && tilegx_current_function_is_leaf ( ) && ! crtl -> profile && ! df_regs_ever_live_p ( TILEGX_LINK_REGNUM ) ) ; } </s>

Return nonzero if this function is known to have a null epilogue . This allows the optimizer to omit jumps to jumps if no stack was created .


<s> unsigned getEUsPerCU ( const FeatureBitset & Features ) { return 4 ; } </s>

Number of SIMDs/EUs ( execution units ) per `` CU '' ( `` compute unit '' ) , where the `` CU '' is the unit onto which workgroups are mapped .


<s>
SDValue
X86TargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
bool
Is64Bit
=
Subtarget
->
is64Bit
(
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
DAG
.
getTarget
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_X86
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
CopyVT
=
VA
.
getValVT
(
)
;
if
(
(
CopyVT
==
MVT
::
f32
||
CopyVT
==
MVT
::
f64
)
&&
(
(
Is64Bit
||
Ins
[
i
]
.
Flags
.
isInReg
(
)
)
&&
!
Subtarget
->
hasSSE1
(
)
)
)
{
report_fatal_error
(
"SSE register return with SSE disabled"
)
;
}
SDValue
Val
;
if
(
VA
.
getLocReg
(
)
==
X86
::
ST0
||
VA
.
getLocReg
(
)
==
X86
::
ST1
)
{
if
(
isScalarFPTypeInSSEReg
(
VA
.
getValVT
(
)
)
)
CopyVT
=
MVT
::
f80
;
SDValue
Ops
[
]
=
{
Chain
,
InFlag
}
;
Chain
=
SDValue
(
DAG
.
getMachineNode
(
X86
::
FpPOP_RETVAL
,
dl
,
CopyVT
,
MVT
::
Other
,
MVT
::
Glue
,
Ops
)
,
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
if
(
CopyVT
!=
VA
.
getValVT
(
)
)
Val
=
DAG
.
getNode
(
ISD
::
FP_ROUND
,
dl
,
VA
.
getValVT
(
)
,
Val
,
DAG
.
getIntPtrConstant
(
1
)
)
;
}
else
{
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
CopyVT
,
InFlag
)
.
getValue
(
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
}
InFlag
=
Chain
.
getValue
(
2
)
;
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s>
Value
*
PPCTargetLowering
::
emitMaskedAtomicCmpXchgIntrinsic
(
IRBuilderBase
&
Builder
,
AtomicCmpXchgInst
*
CI
,
Value
*
AlignedAddr
,
Value
*
CmpVal
,
Value
*
NewVal
,
Value
*
Mask
,
AtomicOrdering
Ord
)
const
{
assert
(
EnableQuadwordAtomics
&&
Subtarget
.
hasQuadwordAtomics
(
)
&&
"Only support quadword now"
)
;
Module
*
M
=
Builder
.
GetInsertBlock
(
)
->
getParent
(
)
->
getParent
(
)
;
Type
*
ValTy
=
cast
<
PointerType
>
(
AlignedAddr
->
getType
(
)
)
->
getElementType
(
)
;
assert
(
ValTy
->
getPrimitiveSizeInBits
(
)
==
128
)
;
Function
*
IntCmpXchg
=
Intrinsic
::
getDeclaration
(
M
,
Intrinsic
::
ppc_cmpxchg_i128
)
;
Type
*
Int64Ty
=
Type
::
getInt64Ty
(
M
->
getContext
(
)
)
;
Value
*
CmpLo
=
Builder
.
CreateTrunc
(
CmpVal
,
Int64Ty
,
"cmp_lo"
)
;
Value
*
CmpHi
=
Builder
.
CreateTrunc
(
Builder
.
CreateLShr
(
CmpVal
,
64
)
,
Int64Ty
,
"cmp_hi"
)
;
Value
*
NewLo
=
Builder
.
CreateTrunc
(
NewVal
,
Int64Ty
,
"new_lo"
)
;
Value
*
NewHi
=
Builder
.
CreateTrunc
(
Builder
.
CreateLShr
(
NewVal
,
64
)
,
Int64Ty
,
"new_hi"
)
;
Value
*
Addr
=
Builder
.
CreateBitCast
(
AlignedAddr
,
Type
::
getInt8PtrTy
(
M
->
getContext
(
)
)
)
;
emitLeadingFence
(
Builder
,
CI
,
Ord
)
;
Value
*
LoHi
=
Builder
.
CreateCall
(
IntCmpXchg
,
{
Addr
,
CmpLo
,
CmpHi
,
NewLo
,
NewHi
}
)
;
emitTrailingFence
(
Builder
,
CI
,
Ord
)
;
Value
*
Lo
=
Builder
.
CreateExtractValue
(
LoHi
,
0
,
"lo"
)
;
Value
*
Hi
=
Builder
.
CreateExtractValue
(
LoHi
,
1
,
"hi"
)
;
Lo
=
Builder
.
CreateZExt
(
Lo
,
ValTy
,
"lo64"
)
;
Hi
=
Builder
.
CreateZExt
(
Hi
,
ValTy
,
"hi64"
)
;
return
Builder
.
CreateOr
(
Lo
,
Builder
.
CreateShl
(
Hi
,
ConstantInt
::
get
(
ValTy
,
64
)
)
,
"val64"
)
;
}
</s>

Perform a masked cmpxchg using a target-specific intrinsic .


<s> bool HexagonEarlyIfConversion :: isPredicate ( unsigned R ) const { const TargetRegisterClass * RC = MRI -> getRegClass ( R ) ; return RC == & Hexagon :: PredRegsRegClass || RC == & Hexagon :: HvxQRRegClass ; } </s>

Set if this is one of the operands that made up of the predicate operand that controls an isPredicable ( ) instruction .

Hexagon Hexagon Hexagon::PredRegsRegClass Hexagon::HvxQRRegClass


<s>
void
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsPCRel
)
const
override
{
unsigned
Size
=
1
<<
getFixupKindLog2Size
(
Fixup
.
getKind
(
)
)
;
assert
(
Fixup
.
getOffset
(
)
+
Size
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
assert
(
isIntN
(
Size
*
8
+
1
,
Value
)
&&
"Value does not fit in the Fixup field"
)
;
for
(
unsigned
i
=
0
;
i
!=
Size
;
++
i
)
Data
[
Fixup
.
getOffset
(
)
+
i
]
=
uint8_t
(
Value
>>
(
i
*
8
)
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static int rs6000_use_sched_lookahead ( void ) { switch ( rs6000_cpu_attr ) { case CPU_PPC8540 : case CPU_PPC8548 : return 4 ; case CPU_CELL : return ( reload_completed ? 8 : 0 ) ; default : return 0 ; } } </s>

Return how many instructions to look ahead for better insn scheduling .


<s> bool aarch64_reinterpret_float_as_int ( rtx value , unsigned HOST_WIDE_INT * intval ) { if ( aarch64_float_const_zero_rtx_p ( value ) ) { * intval = 0 ; return true ; } scalar_float_mode mode ; if ( ! CONST_DOUBLE_P ( value ) || ! is_a < scalar_float_mode > ( GET_MODE ( value ) , & mode ) || GET_MODE_BITSIZE ( mode ) > HOST_BITS_PER_WIDE_INT || GET_MODE_BITSIZE ( mode ) > GET_MODE_BITSIZE ( DFmode ) ) return false ; unsigned HOST_WIDE_INT ival = 0 ; long res [ 2 ] ; real_to_target ( res , CONST_DOUBLE_REAL_VALUE ( value ) , REAL_MODE_FORMAT ( mode ) ) ; if ( mode == DFmode ) { int order = BYTES_BIG_ENDIAN ? 1 : 0 ; ival = zext_hwi ( res [ order ] , 32 ) ; ival |= ( zext_hwi ( res [ 1 - order ] , 32 ) << 32 ) ; } else ival = zext_hwi ( res [ 0 ] , 32 ) ; * intval = ival ; return true ; } </s>

Return the binary representation of floating point constant VALUE in INTVAL . If the value can not be converted , return false without setting INTVAL . The conversion is done in the given MODE .


<s> void PPCAIXAsmPrinter :: emitEndOfAsmFile ( Module & M ) { if ( M . empty ( ) && TOCDataGlobalVars . empty ( ) ) return ; emitPGORefs ( ) ; OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTOCBaseSection ( ) ) ; PPCTargetStreamer * TS = static_cast < PPCTargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; for ( auto & I : TOC ) { MCSectionXCOFF * TCEntry ; if ( I . first . second == MCSymbolRefExpr :: VariantKind :: VK_PPC_AIX_TLSGDM ) { SmallString < 128 > Name ; StringRef Prefix = "." ; Name += Prefix ; Name += I . first . first -> getName ( ) ; MCSymbol * S = OutContext . getOrCreateSymbol ( Name ) ; TCEntry = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForTOCEntry ( S , TM ) ) ; } else { TCEntry = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForTOCEntry ( I . first . first , TM ) ) ; } OutStreamer -> SwitchSection ( TCEntry ) ; OutStreamer -> emitLabel ( I . second ) ; if ( TS != nullptr ) TS -> emitTCEntry ( * I . first . first , I . first . second ) ; } for ( const auto * GV : TOCDataGlobalVars ) emitGlobalVariableHelper ( GV ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> bool sh_symbian_dllexport_name_p ( const char * symbol ) { return strncmp ( DLL_EXPORT_PREFIX , symbol , strlen ( DLL_EXPORT_PREFIX ) ) == 0 ; } </s>

Return nonzero if SYMBOL is marked as being dllexport 'd .


<s> void ARMHazardRecognizer :: Reset ( ) { LastMI = nullptr ; FpMLxStalls = 0 ; ScoreboardHazardRecognizer :: Reset ( ) ; } </s>


<s> bool isImm ( ) const override { return Kind == Immediate ; } </s>


<s> const ARCInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> bool ARMInstrInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( ! AFI -> isThumbFunction ( ) || CSI . empty ( ) ) return false ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( ARM :: tPUSH ) ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; MIB . addReg ( Reg , false , false , true ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> void VEFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; int NumBytes = ( int ) MFI . getStackSize ( ) ; emitEpilogueInsns ( MF , MBB , MBBI , NumBytes , true ) ; } </s>


<s> int const_int_pow2_p ( rtx x ) { if ( GET_CODE ( x ) == CONST_INT ) { HOST_WIDE_INT d = INTVAL ( x ) ; HOST_WIDE_INT abs_d = ( d >= 0 ) ? d : - d ; return exact_log2 ( abs_d ) + 1 ; } return 0 ; } </s>

Returns nonzero ( bit number + 1 ) if X , or -X , is a constant power of 2 .


<s> bool PPCFunctionInfo :: isLiveInSExt ( unsigned VReg ) const { for ( const std :: pair < unsigned , ISD :: ArgFlagsTy > & LiveIn : LiveInAttrs ) if ( LiveIn . first == VReg ) return LiveIn . second . isSExt ( ) ; return false ; } </s>

This function returns true if the specified vreg is a live-in register and sign-extended .


<s> std :: pair < const TargetRegisterClass * , uint8_t > X86TargetLowering :: findRepresentativeClass ( const TargetRegisterInfo * TRI , MVT VT ) const { const TargetRegisterClass * RRC = nullptr ; uint8_t Cost = 1 ; switch ( VT . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( TRI , VT ) ; case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : case MVT :: i64 : RRC = Subtarget . is64Bit ( ) ? & X86 :: GR64RegClass : & X86 :: GR32RegClass ; break ; case MVT :: x86mmx : RRC = & X86 :: VR64RegClass ; break ; case MVT :: f32 : case MVT :: f64 : case MVT :: v16i8 : case MVT :: v8i16 : case MVT :: v4i32 : case MVT :: v2i64 : case MVT :: v4f32 : case MVT :: v2f64 : case MVT :: v32i8 : case MVT :: v16i16 : case MVT :: v8i32 : case MVT :: v4i64 : case MVT :: v8f32 : case MVT :: v4f64 : case MVT :: v64i8 : case MVT :: v32i16 : case MVT :: v16i32 : case MVT :: v8i64 : case MVT :: v16f32 : case MVT :: v8f64 : RRC = & X86 :: VR128XRegClass ; break ; } return std :: make_pair ( RRC , Cost ) ; } </s>

Return the largest legal super-reg register class of the register class for the specified type and its associated `` cost '' .


<s> bool SystemZTargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createSystemZISelDag ( * this , OptLevel ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> BitVector ARMBaseRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( ARM :: SP ) ; Reserved . set ( ARM :: PC ) ; if ( STI . isTargetDarwin ( ) || hasFP ( MF ) ) Reserved . set ( FramePtr ) ; if ( STI . isR9Reserved ( ) ) Reserved . set ( ARM :: R9 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
void
Z80InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
Z80
::
GR8RegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
Z80
::
LD8rr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
return
;
}
else
if
(
Z80
::
BR16RegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
if
(
Z80
::
EXR16RegClass
.
contains
(
DestReg
,
SrcReg
)
&&
KillSrc
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
Z80
::
EX_DE_HL
)
)
;
}
else
{
unsigned
DestSubReg
,
SrcSubReg
;
DestSubReg
=
RI
.
getSubReg
(
DestReg
,
Z80
::
subreg_hi
)
;
SrcSubReg
=
RI
.
getSubReg
(
SrcReg
,
Z80
::
subreg_hi
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Z80
::
LD8rr
)
,
DestSubReg
)
.
addReg
(
SrcSubReg
)
;
DestSubReg
=
RI
.
getSubReg
(
DestReg
,
Z80
::
subreg_lo
)
;
SrcSubReg
=
RI
.
getSubReg
(
SrcReg
,
Z80
::
subreg_lo
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Z80
::
LD8rr
)
,
DestSubReg
)
.
addReg
(
SrcSubReg
)
;
}
if
(
KillSrc
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
Z80
::
KILL
)
)
.
addReg
(
SrcReg
)
;
return
;
}
else
if
(
Z80
::
GR16RegClass
.
contains
(
DestReg
)
||
Z80
::
GR16RegClass
.
contains
(
SrcReg
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
Z80
::
PUSH16r
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Z80
::
POP16r
)
,
DestReg
)
;
return
;
}
llvm_unreachable
(
"Imposible reg-to-reg copy"
)
;
}
</s>


<s> SDValue AArch64TargetLowering :: getSqrtEstimate ( SDValue Operand , SelectionDAG & DAG , int Enabled , int & ExtraSteps , bool & UseOneConst , bool Reciprocal ) const { if ( Enabled == ReciprocalEstimate :: Enabled || ( Enabled == ReciprocalEstimate :: Unspecified && Subtarget -> useRSqrt ( ) ) ) if ( SDValue Estimate = getEstimate ( Subtarget , AArch64ISD :: FRSQRTE , Operand , DAG , ExtraSteps ) ) { SDLoc DL ( Operand ) ; EVT VT = Operand . getValueType ( ) ; SDNodeFlags Flags ; Flags . setAllowReassociation ( true ) ; for ( int i = ExtraSteps ; i > 0 ; -- i ) { SDValue Step = DAG . getNode ( ISD :: FMUL , DL , VT , Estimate , Estimate , Flags ) ; Step = DAG . getNode ( AArch64ISD :: FRSQRTS , DL , VT , Operand , Step , Flags ) ; Estimate = DAG . getNode ( ISD :: FMUL , DL , VT , Estimate , Step , Flags ) ; } if ( ! Reciprocal ) Estimate = DAG . getNode ( ISD :: FMUL , DL , VT , Operand , Estimate , Flags ) ; ExtraSteps = 0 ; return Estimate ; } return SDValue ( ) ; } </s>

Hooks for building estimates in place of slower divisions and square roots .


<s> bool X86TTIImpl :: isLegalMaskedLoad ( Type * DataTy ) { Type * ScalarTy = DataTy -> getScalarType ( ) ; int DataWidth = isa < PointerType > ( ScalarTy ) ? DL . getPointerSizeInBits ( ) : ScalarTy -> getPrimitiveSizeInBits ( ) ; return ( DataWidth >= 32 && ST -> hasAVX2 ( ) ) ; } </s>

Return true if the target supports masked load .


<s> static machine_mode rs6000_translate_mode_attribute ( machine_mode mode ) { if ( ( FLOAT128_IEEE_P ( mode ) && ieee128_float_type_node == long_double_type_node ) || ( FLOAT128_IBM_P ( mode ) && ibm128_float_type_node == long_double_type_node ) ) return COMPLEX_MODE_P ( mode ) ? E_TCmode : E_TFmode ; return mode ; } </s>

Target hook for translate_mode_attribute .