<s> bool prepare_move_operands ( rtx * operands , machine_mode mode ) { if ( ! TARGET_NO_SDATA_SET && small_data_pattern ( operands [ 0 ] , Pmode ) ) operands [ 0 ] = arc_rewrite_small_data ( operands [ 0 ] ) ; if ( mode == SImode && SYMBOLIC_CONST ( operands [ 1 ] ) ) { prepare_pic_move ( operands , SImode ) ; } if ( GET_CODE ( operands [ 0 ] ) != MEM && ! TARGET_NO_SDATA_SET && small_data_pattern ( operands [ 1 ] , Pmode ) ) { operands [ 1 ] = arc_rewrite_small_data ( operands [ 1 ] ) ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , operands [ 1 ] ) ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , operands [ 1 ] ) ; emit_move_insn ( operands [ 0 ] , operands [ 0 ] ) ; return true ; } if ( MEM_P ( operands [ 0 ] ) && ! ( reload_in_progress || reload_completed ) ) { operands [ 1 ] = force_reg ( mode , operands [ 1 ] ) ; if ( ! move_dest_operand ( operands [ 0 ] , mode ) ) { rtx addr = copy_to_mode_reg ( Pmode , XEXP ( operands [ 0 ] , 0 ) ) ; rtx pat = change_address ( operands [ 0 ] , mode , addr ) ; MEM_COPY_ATTRIBUTES ( pat , operands [ 0 ] ) ; operands [ 0 ] = pat ; } if ( ! cse_not_expected ) { rtx pat = XEXP ( operands [ 0 ] , 0 ) ; pat = arc_legitimize_address_0 ( pat , pat , mode ) ; if ( pat ) { pat = change_address ( operands [ 0 ] , mode , pat ) ; MEM_COPY_ATTRIBUTES ( pat , operands [ 0 ] ) ; operands [ 0 ] = pat ; } } } if ( MEM_P ( operands [ 1 ] ) && ! cse_not_expected ) { rtx pat = XEXP ( operands [ 1 ] , 0 ) ; pat = arc_legitimize_address_0 ( pat , pat , mode ) ; if ( pat ) { pat = change_address ( operands [ 1 ] , mode , pat ) ; MEM_COPY_ATTRIBUTES ( pat , operands [ 1 ] ) ; operands [ 1 ] = pat ; } } return false ; } </s>

Prepare operands for a move define_expand in MODE .


<s> void AMDGPUPassConfig :: addPreRegAlloc ( ) { const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) { addPass ( createR600VectorRegMerger ( * TM ) ) ; } else { if ( getOptLevel ( ) > CodeGenOpt :: None && ST . loadStoreOptEnabled ( ) ) { initializeSILoadStoreOptimizerPass ( * PassRegistry :: getPassRegistry ( ) ) ; insertPass ( & MachineSchedulerID , & SILoadStoreOptimizerID ) ; } addPass ( createSIShrinkInstructionsPass ( ) , false ) ; addPass ( createSIFixSGPRLiveRangesPass ( ) , false ) ; } } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> bool isMBB ( ) { return getMBBMRT ( ) != nullptr ; } </s>

isMBB - Tests if this is a MO_MachineBasicBlock operand .


"Hexagon relaxInstruction only works on bundles"

"No room to insert extender for relaxation"

Relax the instruction in the given fragment to the next wider instruction .


<s> unsigned X86TargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) const { assert ( ! isFuncletEHPersonality ( classifyEHPersonality ( PersonalityFn ) ) ) ; return Subtarget -> isTarget64BitLP64 ( ) ? X86 :: RDX : X86 :: EDX ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .


<s> static bool chain_already_loaded ( rtx_insn * last ) { for ( ; last != NULL ; last = PREV_INSN ( last ) ) { if ( NONJUMP_INSN_P ( last ) ) { rtx patt = PATTERN ( last ) ; if ( GET_CODE ( patt ) == SET ) { rtx lhs = XEXP ( patt , 0 ) ; if ( REG_P ( lhs ) && REGNO ( lhs ) == STATIC_CHAIN_REGNUM ) return true ; } } } return false ; } </s>

Return TRUE iff the sequence ending in LAST sets the static chain .


<s> TargetPassConfig * TOYTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new TOYPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> bool XCoreRegisterInfo :: hasFP ( const MachineFunction & MF ) const { return DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static reg_class_t mn10300_preferred_reload_class ( rtx x , reg_class_t rclass ) { if ( x == stack_pointer_rtx && rclass != SP_REGS ) return ( TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS ) ; else if ( MEM_P ( x ) || ( REG_P ( x ) && ! HARD_REGISTER_P ( x ) ) || ( GET_CODE ( x ) == SUBREG && REG_P ( SUBREG_REG ( x ) ) && ! HARD_REGISTER_P ( SUBREG_REG ( x ) ) ) ) return LIMIT_RELOAD_CLASS ( GET_MODE ( x ) , rclass ) ; else return rclass ; } </s>


<s> static int rs6000_use_sched_lookahead_guard ( rtx_insn * insn , int ready_index ) { if ( ready_index == 0 ) return 0 ; if ( rs6000_cpu_attr != CPU_CELL ) return 0 ; gcc_assert ( insn != NULL_RTX && INSN_P ( insn ) ) ; if ( ! reload_completed || is_nonpipeline_insn ( insn ) || is_microcoded_insn ( insn ) ) return 1 ; return 0 ; } </s>

We are choosing insn from the ready queue . Return zero if INSN can be chosen .


"instruction use requires an option to be enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> int X86TTIImpl :: getIntImmCost ( Intrinsic :: ID IID , unsigned Idx , const APInt & Imm , Type * Ty ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; switch ( IID ) { default : return TTI :: TCC_Free ; case Intrinsic :: sadd_with_overflow : case Intrinsic :: uadd_with_overflow : case Intrinsic :: ssub_with_overflow : case Intrinsic :: usub_with_overflow : case Intrinsic :: smul_with_overflow : case Intrinsic :: umul_with_overflow : if ( ( Idx == 1 ) && Imm . getBitWidth ( ) <= 64 && isInt < 32 > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; break ; case Intrinsic :: experimental_stackmap : if ( ( Idx < 2 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; case Intrinsic :: experimental_patchpoint_void : case Intrinsic :: experimental_patchpoint_i64 : if ( ( Idx < 4 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; } return X86TTIImpl :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


"Unexpected instruction type for reassociation"

"Must have dead EFLAGS operand in reassociable instruction"

"Unexpected operand in reassociable instruction"

This is an architecture-specific helper function of reassociateOps .


<s> static bool rs6000_attribute_takes_identifier_p ( const_tree attr_id ) { return is_attribute_p ( "altivec" , attr_id ) ; } </s>

Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain identifier as an argument , so the front end should n't look it up .


<s> unsigned ARMFastISel :: fastEmitInst_rr ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , bool Op0IsKill , unsigned Op1 , bool Op1IsKill ) { unsigned ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , 1 ) ; Op1 = constrainOperandRegClass ( II , Op1 , 2 ) ; if ( II . getNumDefs ( ) >= 1 ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ 0 ] ) ) ; } return ResultReg ; } </s>

Emit a MachineInstr with two register operands and a result register in the given register class .


<s> void AArch64FrameLowering :: emitZeroCallUsedRegs ( BitVector RegsToZero , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; DebugLoc DL ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB . getParent ( ) ; const AArch64Subtarget & STI = MF . getSubtarget < AArch64Subtarget > ( ) ; const AArch64RegisterInfo & TRI = * STI . getRegisterInfo ( ) ; BitVector GPRsToZero ( TRI . getNumRegs ( ) ) ; BitVector FPRsToZero ( TRI . getNumRegs ( ) ) ; bool HasSVE = STI . hasSVE ( ) ; for ( MCRegister Reg : RegsToZero . set_bits ( ) ) { if ( TRI . isGeneralPurposeRegister ( MF , Reg ) ) { if ( MCRegister XReg = getRegisterOrZero ( Reg , HasSVE ) ) GPRsToZero . set ( XReg ) ; } else if ( AArch64 :: FPR128RegClass . contains ( Reg ) || AArch64 :: FPR64RegClass . contains ( Reg ) || AArch64 :: FPR32RegClass . contains ( Reg ) || AArch64 :: FPR16RegClass . contains ( Reg ) || AArch64 :: FPR8RegClass . contains ( Reg ) ) { if ( MCRegister XReg = getRegisterOrZero ( Reg , HasSVE ) ) FPRsToZero . set ( XReg ) ; } } const AArch64InstrInfo & TII = * STI . getInstrInfo ( ) ; for ( MCRegister Reg : GPRsToZero . set_bits ( ) ) BuildMI ( MBB , MBBI , DL , TII . get ( AArch64 :: MOVi64imm ) , Reg ) . addImm ( 0 ) ; for ( MCRegister Reg : FPRsToZero . set_bits ( ) ) if ( HasSVE ) BuildMI ( MBB , MBBI , DL , TII . get ( AArch64 :: DUP_ZI_D ) , Reg ) . addImm ( 0 ) . addImm ( 0 ) ; else BuildMI ( MBB , MBBI , DL , TII . get ( AArch64 :: MOVIv2d_ns ) , Reg ) . addImm ( 0 ) ; if ( HasSVE ) { for ( MCRegister PReg : { AArch64 :: P0 , AArch64 :: P1 , AArch64 :: P2 , AArch64 :: P3 , AArch64 :: P4 , AArch64 :: P5 , AArch64 :: P6 , AArch64 :: P7 , AArch64 :: P8 , AArch64 :: P9 , AArch64 :: P10 , AArch64 :: P11 , AArch64 :: P12 , AArch64 :: P13 , AArch64 :: P14 , AArch64 :: P15 } ) { if ( RegsToZero [ PReg ] ) BuildMI ( MBB , MBBI , DL , TII . get ( AArch64 :: PFALSE ) , PReg ) ; } } } </s>

emitZeroCallUsedRegs - Zeros out call used registers .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { const X86TargetMachine * TM = static_cast < const X86TargetMachine * > ( & MF . getTarget ( ) ) ; if ( TM -> getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ) return false ; if ( TM -> getRelocationModel ( ) != Reloc :: PIC_ ) return false ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned GlobalBaseReg = X86FI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg == 0 ) return false ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; const X86InstrInfo * TII = TM -> getSubtargetImpl ( ) -> getInstrInfo ( ) ; unsigned PC ; if ( TM -> getSubtarget < X86Subtarget > ( ) . isPICStyleGOT ( ) ) PC = RegInfo . createVirtualRegister ( & X86 :: GR32RegClass ) ; else PC = GlobalBaseReg ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( X86 :: MOVPC32r ) , PC ) . addImm ( 0 ) ; if ( TM -> getSubtarget < X86Subtarget > ( ) . isPICStyleGOT ( ) ) { BuildMI ( FirstMBB , MBBI , DL , TII -> get ( X86 :: ADD32ri ) , GlobalBaseReg ) . addReg ( PC ) . addExternalSymbol ( "_GLOBAL_OFFSET_TABLE_" , X86II :: MO_GOT_ABSOLUTE_ADDRESS ) ; } return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> static int str_prefix_p ( const char * str , const char * prefix ) { return strncmp ( str , prefix , strlen ( prefix ) ) == 0 ; } </s>

Return true iff STR starts with PREFIX .


<s> void assignValueToReg ( Register ValVReg , Register PhysReg , CCValAssign VA ) override { markPhysRegUsed ( PhysReg ) ; IncomingValueHandler :: assignValueToReg ( ValVReg , PhysReg , VA ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


Return an array that contains the bitmask target flag values and their names .

PowerPC PPC PPC "ppc-plt" "ppc-pic" "ppc-pcrel" "ppc-got" "ppc-opt-pcrel" "ppc-tlsgd" "ppc-tprel" "ppc-got-tlsgd-pcrel" "ppc-got-tprel-pcrel"


<s> static rtx sparc_got ( void ) { if ( ! sparc_got_symbol ) sparc_got_symbol = gen_rtx_SYMBOL_REF ( Pmode , "_GLOBAL_OFFSET_TABLE_" ) ; return sparc_got_symbol ; } </s>

Return the SYMBOL_REF for the Global Offset Table .


<s> bool runOnModule ( Module & M ) override { FeatureBitset Features = coalesceFeatures ( M ) ; std :: string FeatureStr = getFeatureString ( Features ) ; for ( auto & F : M ) replaceFeatures ( F , FeatureStr ) ; bool StrippedAtomics = false ; bool StrippedTLS = false ; if ( ! Features [ WebAssembly :: FeatureAtomics ] ) StrippedAtomics = stripAtomics ( M ) ; if ( ! Features [ WebAssembly :: FeatureBulkMemory ] ) StrippedTLS = stripThreadLocals ( M ) ; if ( StrippedAtomics && ! StrippedTLS ) stripThreadLocals ( M ) ; else if ( StrippedTLS && ! StrippedAtomics ) stripAtomics ( M ) ; recordFeatures ( M , Features , StrippedAtomics || StrippedTLS ) ; return true ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> unsigned PPCRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const PPCFrameLowering * TFI = getFrameLowering ( MF ) ; const unsigned DefaultSafety = 1 ; switch ( RC -> getID ( ) ) { default : return 0 ; case PPC :: G8RC_NOX0RegClassID : case PPC :: GPRC_NOR0RegClassID : case PPC :: SPERCRegClassID : case PPC :: SPE4RCRegClassID : case PPC :: G8RCRegClassID : case PPC :: GPRCRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 32 - FP - DefaultSafety ; } case PPC :: F8RCRegClassID : case PPC :: F4RCRegClassID : case PPC :: QFRCRegClassID : case PPC :: QSRCRegClassID : case PPC :: QBRCRegClassID : case PPC :: VRRCRegClassID : case PPC :: VFRCRegClassID : case PPC :: VSLRCRegClassID : return 32 - DefaultSafety ; case PPC :: VSRCRegClassID : case PPC :: VSFRCRegClassID : case PPC :: VSSRCRegClassID : return 64 - DefaultSafety ; case PPC :: CRRCRegClassID : return 8 - DefaultSafety ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> bool AGCExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const AGCInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; bool Modified = false ; for ( auto & MBB : MF ) Modified |= expandMBB ( MBB ) ; return Modified ; } </s>


<s> bool SparcPassConfig :: addInstSelector ( ) { addPass ( createSparcISelDag ( getSparcTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> StringRef getAddress ( ) const { return Address ; } </s>

Returns the address of this pointer in this block .


<s> static rtx mark_constant_pool_use ( rtx x ) { rtx insn , lab , pattern ; if ( x == NULL ) return x ; switch ( GET_CODE ( x ) ) { case LABEL_REF : x = XEXP ( x , 0 ) ; case CODE_LABEL : break ; default : return x ; } lab = x ; for ( insn = PREV_INSN ( x ) ; insn ; insn = PREV_INSN ( insn ) ) { if ( GET_CODE ( insn ) != CODE_LABEL || LABEL_REFS ( insn ) != NEXT_INSN ( insn ) ) break ; lab = insn ; } for ( insn = LABEL_REFS ( lab ) ; insn ; insn = LABEL_REFS ( insn ) ) INSN_DELETED_P ( insn ) = 1 ; for ( insn = NEXT_INSN ( x ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( GET_CODE ( insn ) != INSN ) continue ; pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) != UNSPEC_VOLATILE ) continue ; switch ( XINT ( pattern , 1 ) ) { case UNSPECV_CONST2 : case UNSPECV_CONST4 : case UNSPECV_CONST8 : XVECEXP ( pattern , 0 , 1 ) = const1_rtx ; break ; case UNSPECV_WINDOW_END : if ( XVECEXP ( pattern , 0 , 0 ) == x ) return lab ; break ; case UNSPECV_CONST_END : return lab ; default : break ; } } return lab ; } </s>

Mark the use of a constant in the literal table . If the constant has multiple labels , make it unique .


<s> static rtx_insn * mep_make_bundle ( rtx core_insn_or_pat , rtx_insn * cop ) { rtx seq ; rtx_insn * core_insn ; rtx_insn * insn ; if ( INSN_P ( core_insn_or_pat ) ) { core_insn = as_a < rtx_insn * > ( core_insn_or_pat ) ; remove_insn ( core_insn ) ; } else core_insn = make_insn_raw ( core_insn_or_pat ) ; seq = gen_rtx_SEQUENCE ( VOIDmode , gen_rtvec ( 2 , core_insn , cop ) ) ; insn = emit_insn_after ( seq , cop ) ; remove_insn ( cop ) ; SET_PREV_INSN ( core_insn ) = PREV_INSN ( insn ) ; SET_NEXT_INSN ( core_insn ) = cop ; SET_PREV_INSN ( cop ) = core_insn ; SET_NEXT_INSN ( cop ) = NEXT_INSN ( insn ) ; PUT_MODE ( core_insn , VOIDmode ) ; PUT_MODE ( cop , BImode ) ; INSN_LOCATION ( insn ) = INSN_LOCATION ( INSN_LOCATION ( core_insn ) ? core_insn : cop ) ; INSN_LOCATION ( core_insn ) = 0 ; INSN_LOCATION ( cop ) = 0 ; return insn ; } </s>

Create a VLIW bundle from core instruction CORE and coprocessor instruction COP . COP always satisfies INSN_P , but CORE can be either a new pattern or an existing instruction . Emit the bundle in place of COP and return it .


<s> bool X86IntelAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; printMemReference ( MI , OpNo ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> static tree bpf_core_compute ( tree node , vec < unsigned int > * accessors ) { if ( TREE_CODE ( node ) == ADDR_EXPR ) node = TREE_OPERAND ( node , 0 ) ; else if ( TREE_CODE ( node ) == INDIRECT_REF || TREE_CODE ( node ) == POINTER_PLUS_EXPR ) { accessors -> safe_push ( 0 ) ; return TREE_OPERAND ( node , 0 ) ; } while ( 1 ) { switch ( TREE_CODE ( node ) ) { case COMPONENT_REF : accessors -> safe_push ( bpf_core_get_index ( TREE_OPERAND ( node , 1 ) ) ) ; break ; case ARRAY_REF : case ARRAY_RANGE_REF : accessors -> safe_push ( bpf_core_get_index ( node ) ) ; break ; case MEM_REF : accessors -> safe_push ( bpf_core_get_index ( node ) ) ; if ( TREE_CODE ( TREE_OPERAND ( node , 0 ) ) == ADDR_EXPR ) node = TREE_OPERAND ( TREE_OPERAND ( node , 0 ) , 0 ) ; goto done ; default : goto done ; } node = TREE_OPERAND ( node , 0 ) ; } done : return node ; } </s>

Traverse the subtree under NODE , which is expected to be some form of aggregate access the CO-RE machinery cares about ( like a read of a member of a struct or union ) , collecting access indices for the components and storing them in the vector referenced by ACCESSORS . Return the ultimate ( top-level ) container of the aggregate access . In general , this will be a VAR_DECL or some kind of REF . Note that the accessors are computed * in reverse order * of how the BPF CO-RE machinery defines them . The vector needs to be reversed ( or simply output in reverse order ) for the .BTF.ext relocation information .


<s> void load_got_register ( void ) { rtx insn ; if ( TARGET_VXWORKS_RTP ) { if ( ! got_register_rtx ) got_register_rtx = pic_offset_table_rtx ; insn = gen_vxworks_load_got ( ) ; } else { if ( ! got_register_rtx ) got_register_rtx = gen_rtx_REG ( Pmode , GLOBAL_OFFSET_TABLE_REGNUM ) ; if ( ! got_helper_rtx ) { char name [ 32 ] ; if ( USE_HIDDEN_LINKONCE ) sprintf ( name , "__sparc_get_pc_thunk.%s" , reg_names [ REGNO ( got_register_rtx ) ] + 1 ) ; else ASM_GENERATE_INTERNAL_LABEL ( name , "LADDPC" , REGNO ( got_register_rtx ) ) ; got_helper_rtx = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( name ) ) ; } const int orig_flag_pic = flag_pic ; flag_pic = 0 ; insn = gen_load_pcrel_sym ( Pmode , got_register_rtx , sparc_got ( ) , got_helper_rtx , GEN_INT ( GLOBAL_OFFSET_TABLE_REGNUM ) ) ; flag_pic = orig_flag_pic ; } emit_insn ( insn ) ; } </s>


"Cannot query height of unvisited/RAUW'd node!"

The height , in the dependence graph , for a node .


<s> void reset ( ) override { MappingSymbolCounter = 0 ; State = EMS_None ; MCELFStreamer :: reset ( ) ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s> int sh_dwarf_calling_convention ( const_tree func ) { if ( sh_attr_renesas_p ( func ) ) return DW_CC_GNU_renesas_sh ; return DW_CC_normal ; } </s>

Implements target hook dwarf_calling_convention . Return an enum of dwarf_calling_convention .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


Called to register all of our global variables with the garbage collector .


<s> static int ix86_i387_mode_needed ( int entity , rtx_insn * insn ) { enum attr_i387_cw mode ; if ( CALL_P ( insn ) || ( NONJUMP_INSN_P ( insn ) && ( asm_noperands ( PATTERN ( insn ) ) >= 0 || GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT ) ) ) return I387_CW_UNINITIALIZED ; if ( recog_memoized ( insn ) < 0 ) return I387_CW_ANY ; mode = get_attr_i387_cw ( insn ) ; switch ( entity ) { case I387_TRUNC : if ( mode == I387_CW_TRUNC ) return mode ; break ; case I387_FLOOR : if ( mode == I387_CW_FLOOR ) return mode ; break ; case I387_CEIL : if ( mode == I387_CW_CEIL ) return mode ; break ; default : gcc_unreachable ( ) ; } return I387_CW_ANY ; } </s>

Return mode that i387 must be switched into prior to the execution of insn .


<s> bool RISCVTargetLowering :: isEligibleForTailCallOptimization ( CCState & CCInfo , CallLoweringInfo & CLI , MachineFunction & MF , const SmallVector < CCValAssign , 16 > & ArgLocs ) const { auto & Callee = CLI . Callee ; auto CalleeCC = CLI . CallConv ; auto & Outs = CLI . Outs ; auto & Caller = MF . getFunction ( ) ; auto CallerCC = Caller . getCallingConv ( ) ; if ( Caller . hasFnAttribute ( "interrupt" ) ) return false ; if ( CCInfo . getNextStackOffset ( ) != 0 ) return false ; for ( auto & VA : ArgLocs ) if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; auto IsCallerStructRet = Caller . hasStructRetAttr ( ) ; auto IsCalleeStructRet = Outs . empty ( ) ? false : Outs [ 0 ] . Flags . isSRet ( ) ; if ( IsCallerStructRet || IsCalleeStructRet ) return false ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; if ( GV -> hasExternalWeakLinkage ( ) ) return false ; } const RISCVRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( CalleeCC != CallerCC ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } for ( auto & Arg : Outs ) if ( Arg . Flags . isByVal ( ) ) return false ; return true ; } </s>

Returns true if the call can be lowered as a tail call .


<s> unsigned X86FastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( DL , C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const auto * CI = dyn_cast < ConstantInt > ( C ) ) return X86MaterializeInt ( CI , VT ) ; else if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return X86MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return X86MaterializeGV ( GV , VT ) ; return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s>
SDNode
*
MSP430DAGToDAGISel
::
Select
(
SDValue
Op
)
{
SDNode
*
Node
=
Op
.
getNode
(
)
;
DebugLoc
dl
=
Op
.
getDebugLoc
(
)
;
DOUT
<<
std
::
string
(
Indent
,
' '
)
<<
"Selecting: "
;
DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
DOUT
<<
"\n"
;
Indent
+=
2
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DOUT
<<
std
::
string
(
Indent
2
,
' '
)
<<
"== "
;
DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
DOUT
<<
"\n"
;
Indent
-=
2
;
return
;
}
switch
(
Node
->
getOpcode
(
)
)
{
default
:
break
;
case
ISD
::
FrameIndex
:
{
assert
(
Op
.
getValueType
(
)
==
MVT
::
i16
)
;
int
FI
=
cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
MVT
::
i16
)
;
if
(
Node
->
hasOneUse
(
)
)
return
CurDAG
->
SelectNodeTo
(
Node
,
MSP430
::
ADD16ri
,
MVT
::
i16
,
TFI
,
CurDAG
->
getTargetConstant
(
0
,
MVT
::
i16
)
)
;
return
CurDAG
->
getTargetNode
(
MSP430
::
ADD16ri
,
dl
,
MVT
::
i16
,
TFI
,
CurDAG
->
getTargetConstant
(
0
,
MVT
::
i16
)
)
;
}
}
SDNode
*
ResNode
=
SelectCode
(
Op
)
;
DOUT
<<
std
::
string
(
Indent
2
,
' '
)
<<
"=> "
;
if
(
ResNode
==
||
ResNode
==
Op
.
getNode
(
)
)
DEBUG
(
Op
.
getNode
(
)
->
dump
(
CurDAG
)
)
;
else
DEBUG
(
ResNode
->
dump
(
CurDAG
)
)
;
DOUT
<<
"\n"
;
Indent
-=
2
;
return
ResNode
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> static const char * read_file ( FILE * stream ) { size_t alloc = 16384 ; size_t base = 0 ; char * buffer ; if ( ! fseek ( stream , 0 , SEEK_END ) ) { long s = ftell ( stream ) ; if ( s >= 0 ) alloc = s + 100 ; fseek ( stream , 0 , SEEK_SET ) ; } buffer = XNEWVEC ( char , alloc ) ; for ( ; ; ) { size_t n = fread ( buffer + base , 1 , alloc - base - 1 , stream ) ; if ( ! n ) break ; base += n ; if ( base + 1 == alloc ) { alloc *= 2 ; buffer = XRESIZEVEC ( char , buffer , alloc ) ; } } buffer [ base ] = 0 ; return buffer ; } </s>

Read the whole input file . It will be NUL terminated ( but remember , there could be a NUL in the file itself .


<s> hashval_t toc_hasher :: hash ( toc_hash_struct * thc ) { return rs6000_hash_constant ( thc -> key ) ^ thc -> key_mode ; } </s>

Hash function for builtin functions with up to 3 arguments and a return type .


<s> virtual MVT getScalarShiftAmountTy ( EVT LHSTy ) const { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> bool AArch64CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) . isZero ( ) ) continue ; ArgInfo OrigArg { VRegs [ i ] , Arg , i } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; if ( Arg . hasAttribute ( Attribute :: SwiftAsync ) ) MF . getInfo < AArch64FunctionInfo > ( ) -> setHasSwiftAsyncContext ( true ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , F . getCallingConv ( ) ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; AArch64IncomingValueAssigner Assigner ( AssignFn , AssignFn ) ; FormalArgHandler Handler ( MIRBuilder , MRI ) ; if ( ! determineAndHandleAssignments ( Handler , Assigner , SplitArgs , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ) return false ; AArch64FunctionInfo * FuncInfo = MF . getInfo < AArch64FunctionInfo > ( ) ; uint64_t StackOffset = Assigner . StackOffset ; if ( F . isVarArg ( ) ) { auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; if ( ! Subtarget . isTargetDarwin ( ) ) { return false ; } StackOffset = alignTo ( Assigner . StackOffset , Subtarget . isTargetILP32 ( ) ? 4 : 8 ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( 4 , StackOffset , true ) ) ; } if ( doesCalleeRestoreStack ( F . getCallingConv ( ) , MF . getTarget ( ) . Options . GuaranteedTailCallOpt ) ) { StackOffset = alignTo ( StackOffset , 16 ) ; FuncInfo -> setArgumentStackToRestore ( StackOffset ) ; } FuncInfo -> setBytesInStackArgArea ( StackOffset ) ; auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; if ( Subtarget . hasCustomCallingConv ( ) ) Subtarget . getRegisterInfo ( ) -> UpdateCustomCalleeSavedRegs ( MF ) ; handleMustTailForwardedRegisters ( MIRBuilder , AssignFn ) ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> static int riscv_build_integer_1 ( struct riscv_integer_op codes [ RISCV_MAX_INTEGER_OPS ] , HOST_WIDE_INT value , enum machine_mode mode ) { HOST_WIDE_INT low_part = CONST_LOW_PART ( value ) ; int cost = RISCV_MAX_INTEGER_OPS + 1 , alt_cost ; struct riscv_integer_op alt_codes [ RISCV_MAX_INTEGER_OPS ] ; if ( SMALL_OPERAND ( value ) || LUI_OPERAND ( value ) ) { codes [ 0 ] . code = UNKNOWN ; codes [ 0 ] . value = value ; return 1 ; } if ( low_part != 0 && ( mode != HImode || value - low_part <= ( ( 1 << ( GET_MODE_BITSIZE ( HImode ) - 1 ) ) - 1 ) ) ) { alt_cost = 1 + riscv_build_integer_1 ( alt_codes , value - low_part , mode ) ; if ( alt_cost < cost ) { alt_codes [ alt_cost - 1 ] . code = PLUS ; alt_codes [ alt_cost - 1 ] . value = low_part ; memcpy ( codes , alt_codes , sizeof ( alt_codes ) ) ; cost = alt_cost ; } } if ( cost > 2 && ( low_part < 0 || mode == HImode ) ) { alt_cost = 1 + riscv_build_integer_1 ( alt_codes , value ^ low_part , mode ) ; if ( alt_cost < cost ) { alt_codes [ alt_cost - 1 ] . code = XOR ; alt_codes [ alt_cost - 1 ] . value = low_part ; memcpy ( codes , alt_codes , sizeof ( alt_codes ) ) ; cost = alt_cost ; } } if ( cost > 2 && ( value & 1 ) == 0 ) { int shift = ctz_hwi ( value ) ; unsigned HOST_WIDE_INT x = value ; x = sext_hwi ( x >> shift , HOST_BITS_PER_WIDE_INT - shift ) ; if ( shift > IMM_BITS && ! SMALL_OPERAND ( x ) && LUI_OPERAND ( x << IMM_BITS ) ) shift -= IMM_BITS , x <<= IMM_BITS ; alt_cost = 1 + riscv_build_integer_1 ( alt_codes , x , mode ) ; if ( alt_cost < cost ) { alt_codes [ alt_cost - 1 ] . code = ASHIFT ; alt_codes [ alt_cost - 1 ] . value = shift ; memcpy ( codes , alt_codes , sizeof ( alt_codes ) ) ; cost = alt_cost ; } } gcc_assert ( cost <= RISCV_MAX_INTEGER_OPS ) ; return cost ; } </s>

Helper function for riscv_build_integer ; arguments are as for riscv_build_integer .


<s> LoadInst * X86TargetLowering :: lowerIdempotentRMWIntoFencedLoad ( AtomicRMWInst * AI ) const { unsigned NativeWidth = Subtarget -> is64Bit ( ) ? 64 : 32 ; const Type * MemType = AI -> getType ( ) ; if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) return nullptr ; auto Builder = IRBuilder < > ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SynchScope = AI -> getSynchScope ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; auto Ptr = AI -> getPointerOperand ( ) ; if ( SynchScope == SingleThread ) return nullptr ; if ( ! hasMFENCE ( * Subtarget ) ) return nullptr ; Function * MFence = llvm :: Intrinsic :: getDeclaration ( M , Intrinsic :: x86_sse2_mfence ) ; Builder . CreateCall ( MFence , { } ) ; LoadInst * Loaded = Builder . CreateAlignedLoad ( Ptr , AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ) ; Loaded -> setAtomic ( Order , SynchScope ) ; AI -> replaceAllUsesWith ( Loaded ) ; AI -> eraseFromParent ( ) ; return Loaded ; } </s>

On some platforms , an AtomicRMW that never actually modifies the value ( such as fetch_add of 0 ) can be turned into a fence followed by an atomic load .


<s> const SparcInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> static bool is_power9_pairable_vec_type ( enum attr_type type ) { switch ( type ) { case TYPE_VECSIMPLE : case TYPE_VECCOMPLEX : case TYPE_VECDIV : case TYPE_VECCMP : case TYPE_VECPERM : case TYPE_VECFLOAT : case TYPE_VECFDIV : case TYPE_VECDOUBLE : return true ; default : break ; } return false ; } </s>

Return whether TYPE is a Power9 pairable vector instruction type .


<s> static bool hasTailCall ( const MachineBasicBlock & MBB ) { MachineBasicBlock :: const_iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return false ; unsigned RetOpc = I -> getOpcode ( ) ; return RetOpc == Hexagon :: PS_tailcall_i || RetOpc == Hexagon :: PS_tailcall_r ; } </s>

Returns true if the function contains a tail call .


<s>
void
SystemZInstrInfo
::
insertSelect
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DstReg
,
ArrayRef
<
MachineOperand
>
Pred
,
unsigned
TrueReg
,
unsigned
FalseReg
)
const
{
MachineRegisterInfo
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
const
TargetRegisterClass
*
RC
=
MRI
.
getRegClass
(
DstReg
)
;
assert
(
Pred
.
size
(
)
==
2
&&
"Invalid condition"
)
;
unsigned
CCValid
=
Pred
[
0
]
.
getImm
(
)
;
unsigned
CCMask
=
Pred
[
1
]
.
getImm
(
)
;
unsigned
Opc
;
if
(
SystemZ
::
GRX32BitRegClass
.
hasSubClassEq
(
RC
)
)
{
if
(
STI
.
hasMiscellaneousExtensions3
(
)
)
Opc
=
SystemZ
::
SELRMux
;
else
if
(
STI
.
hasLoadStoreOnCond2
(
)
)
Opc
=
SystemZ
::
LOCRMux
;
else
{
Opc
=
SystemZ
::
LOCR
;
MRI
.
constrainRegClass
(
DstReg
,
&
SystemZ
::
GR32BitRegClass
)
;
Register
TReg
=
MRI
.
createVirtualRegister
(
&
SystemZ
::
GR32BitRegClass
)
;
Register
FReg
=
MRI
.
createVirtualRegister
(
&
SystemZ
::
GR32BitRegClass
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
TargetOpcode
::
COPY
)
,
TReg
)
.
addReg
(
TrueReg
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
TargetOpcode
::
COPY
)
,
FReg
)
.
addReg
(
FalseReg
)
;
TrueReg
=
TReg
;
FalseReg
=
FReg
;
}
}
else
if
(
SystemZ
::
GR64BitRegClass
.
hasSubClassEq
(
RC
)
)
{
if
(
STI
.
hasMiscellaneousExtensions3
(
)
)
Opc
=
SystemZ
::
SELGR
;
else
Opc
=
SystemZ
::
LOCGR
;
}
else
llvm_unreachable
(
"Invalid register class"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DstReg
)
.
addReg
(
FalseReg
)
.
addReg
(
TrueReg
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
;
}
</s>

Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true , and FalseReg to DstReg when Cond is false .


<s> static bool tilegx_truly_noop_truncation ( poly_uint64 outprec , poly_uint64 inprec ) { return inprec <= 32 || outprec > 32 ; } </s>

Implement TARGET_TRULY_NOOP_TRUNCATION . We represent all SI values as sign-extended DI values in registers .


<s> static void i386_solaris_elf_named_section ( const char * name , unsigned int flags , tree decl ) { if ( TARGET_64BIT && strcmp ( name , ".eh_frame" ) == 0 ) { fprintf ( asm_out_file , "\t.section\t%s,\"%s\",@unwind\n" , name , flags & SECTION_WRITE ? "aw" : "a" ) ; return ; } if ( HAVE_COMDAT_GROUP && flags & SECTION_LINKONCE ) { solaris_elf_asm_comdat_section ( name , flags , decl ) ; return ; } if ( flags & SECTION_EXCLUDE ) { fprintf ( asm_out_file , "\t.section\t%s,#exclude\n" , name ) ; return ; } default_elf_asm_named_section ( name , flags , decl ) ; } </s>

Solaris named-section hook . Parameters are as for named_section_real .


<s> unsigned AArch64RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const AArch64FrameLowering * TFI = getFrameLowering ( MF ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case AArch64 :: GPR32RegClassID : case AArch64 :: GPR32spRegClassID : case AArch64 :: GPR32allRegClassID : case AArch64 :: GPR64spRegClassID : case AArch64 :: GPR64allRegClassID : case AArch64 :: GPR64RegClassID : case AArch64 :: GPR32commonRegClassID : case AArch64 :: GPR64commonRegClassID : return 32 - 1 - ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) - MF . getSubtarget < AArch64Subtarget > ( ) . getNumXRegisterReserved ( ) - hasBasePointer ( MF ) ; case AArch64 :: FPR8RegClassID : case AArch64 :: FPR16RegClassID : case AArch64 :: FPR32RegClassID : case AArch64 :: FPR64RegClassID : case AArch64 :: FPR128RegClassID : return 32 ; case AArch64 :: DDRegClassID : case AArch64 :: DDDRegClassID : case AArch64 :: DDDDRegClassID : case AArch64 :: QQRegClassID : case AArch64 :: QQQRegClassID : case AArch64 :: QQQQRegClassID : return 32 ; case AArch64 :: FPR128_loRegClassID : case AArch64 :: FPR64_loRegClassID : case AArch64 :: FPR16_loRegClassID : return 16 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> ScheduleHazardRecognizer * TPCInstrInfo :: CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II , const ScheduleDAG * DAG ) const { return createTPCHazardRecognizer ( II , DAG , true ) ; } </s>

Allocate and return a hazard recognizer to use for by non-scheduling passes .


<s> const Nios2InstrInfo * Nios2InstrInfo :: create ( Nios2Subtarget & STI ) { return new Nios2InstrInfo ( STI ) ; } </s>


<s>
static
void
seh_emit_save
(
FILE
*
f
,
struct
seh_frame_state
*
seh
,
rtx
reg
,
HOST_WIDE_INT
cfa_offset
)
{
const
unsigned
int
regno
=
REGNO
(
reg
)
;
HOST_WIDE_INT
offset
;
seh
->
reg_offset
[
regno
]
=
cfa_offset
;
gcc_assert
(
seh
->
sp_offset
>=
cfa_offset
)
;
offset
=
seh
->
sp_offset
cfa_offset
;
fputs
(
(
SSE_REGNO_P
(
regno
)
"\t.seh_savexmm\t"
:
GENERAL_REGNO_P
(
regno
)
"\t.seh_savereg\t"
:
(
gcc_unreachable
(
)
,
""
)
)
,
f
)
;
print_reg
(
reg
,
0
,
f
)
;
fprintf
(
f
,
", "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
offset
)
;
}
</s>

Emit an assembler directive to save REG at CFA - CFA_OFFSET .


<s>
static
bool
rs6000_declare_alias
(
struct
symtab_node
*
n
,
void
*
d
)
{
struct
declare_alias_data
*
data
=
(
struct
declare_alias_data
*
)
d
;
if
(
!
n
->
alias
||
n
->
weakref
)
return
false
;
if
(
lookup_attribute
(
"ifunc"
,
DECL_ATTRIBUTES
(
n
->
decl
)
)
)
return
false
;
TREE_ASM_WRITTEN
(
n
->
decl
)
=
true
;
const
char
*
name
=
IDENTIFIER_POINTER
(
DECL_ASSEMBLER_NAME
(
n
->
decl
)
)
;
char
*
buffer
=
(
char
*
)
alloca
(
strlen
(
name
)
+
2
)
;
char
*
p
;
int
dollar_inside
=
0
;
strcpy
(
buffer
,
name
)
;
p
=
strchr
(
buffer
,
'$'
)
;
while
(
p
)
{
*
p
=
'_'
;
dollar_inside
++
;
p
=
strchr
(
p
+
1
,
'$'
)
;
}
if
(
TREE_PUBLIC
(
n
->
decl
)
)
{
if
(
!
RS6000_WEAK
||
!
DECL_WEAK
(
n
->
decl
)
)
{
if
(
dollar_inside
)
{
if
(
data
->
function_descriptor
)
fprintf
(
data
->
file
,
"\t.rename .%s,\".%s\"\n"
,
buffer
,
name
)
;
fprintf
(
data
->
file
,
"\t.rename %s,\"%s\"\n"
,
buffer
,
name
)
;
}
if
(
data
->
function_descriptor
)
{
fputs
(
"\t.globl ."
,
data
->
file
)
;
RS6000_OUTPUT_BASENAME
(
data
->
file
,
buffer
)
;
putc
(
'\n'
,
data
->
file
)
;
}
fputs
(
"\t.globl "
,
data
->
file
)
;
RS6000_OUTPUT_BASENAME
(
data
->
file
,
buffer
)
;
putc
(
'\n'
,
data
->
file
)
;
}
else
if
(
DECL_WEAK
(
n
->
decl
)
&&
!
data
->
function_descriptor
)
ASM_WEAKEN_DECL
(
data
->
file
,
n
->
decl
,
name
,
)
;
}
else
{
if
(
dollar_inside
)
{
if
(
data
->
function_descriptor
)
fprintf
(
data
->
file
,
"\t.rename .%s,\".%s\"\n"
,
buffer
,
name
)
;
fprintf
(
data
->
file
,
"\t.rename %s,\"%s\"\n"
,
buffer
,
name
)
;
}
if
(
data
->
function_descriptor
)
{
fputs
(
"\t.lglobl ."
,
data
->
file
)
;
RS6000_OUTPUT_BASENAME
(
data
->
file
,
buffer
)
;
putc
(
'\n'
,
data
->
file
)
;
}
fputs
(
"\t.lglobl "
,
data
->
file
)
;
RS6000_OUTPUT_BASENAME
(
data
->
file
,
buffer
)
;
putc
(
'\n'
,
data
->
file
)
;
}
if
(
data
->
function_descriptor
)
fputs
(
"."
,
data
->
file
)
;
RS6000_OUTPUT_BASENAME
(
data
->
file
,
buffer
)
;
fputs
(
":\n"
,
data
->
file
)
;
return
false
;
}
</s>

Declare alias N. A helper function for for_node_and_aliases .

powerpcspe
"ifunc"
2
0
1
"\t.rename .%s,\".%s\"\n"
"\t.rename %s,\"%s\"\n"
"\t.globl ."
"\t.globl "
"\t.rename .%s,\".%s\"\n"
"\t.rename %s,\"%s\"\n"
"\t.lglobl ."
"\t.lglobl "
"."
":\n"


<s> bool RISCVFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static const X86MCExpr * create ( int64_t RegNo , MCContext & Ctx ) { return new ( Ctx ) X86MCExpr ( RegNo ) ; } </s>


<s>
void
xstormy16_asm_output_aligned_common
(
FILE
*
stream
,
tree
decl
,
const
char
*
name
,
int
size
,
int
align
,
int
global
)
{
rtx
mem
=
DECL_RTL
(
decl
)
;
rtx
symbol
;
if
(
mem
!=
NULL_RTX
&&
GET_CODE
(
mem
)
==
MEM
&&
GET_CODE
(
symbol
=
XEXP
(
mem
,
0
)
)
==
SYMBOL_REF
&&
SYMBOL_REF_FLAGS
(
symbol
)
&
SYMBOL_FLAG_XSTORMY16_BELOW100
)
{
const
char
*
name2
;
int
p2align
=
0
;
bss100_section
(
)
;
while
(
align
>
8
)
{
align
/=
2
;
p2align
++
;
}
name2
=
default_strip_name_encoding
(
name
)
;
if
(
global
)
fprintf
(
stream
,
"\t.globl\t%s\n"
,
name2
)
;
if
(
p2align
)
fprintf
(
stream
,
"\t.p2align %d\n"
,
p2align
)
;
fprintf
(
stream
,
"\t.type\t%s, @object\n"
,
name2
)
;
fprintf
(
stream
,
"\t.size\t%s, %d\n"
,
name2
,
size
)
;
fprintf
(
stream
,
"%s:\n\t.space\t%d\n"
,
name2
,
size
)
;
return
;
}
if
(
!
global
)
{
fprintf
(
stream
,
"\t.local\t"
)
;
assemble_name
(
stream
,
name
)
;
fprintf
(
stream
,
"\n"
)
;
}
fprintf
(
stream
,
"\t.comm\t"
)
;
assemble_name
(
stream
,
name
)
;
fprintf
(
stream
,
",%u,%u\n"
,
size
,
align
/
BITS_PER_UNIT
)
;
}
</s>

The purpose of this function is to override the default behavior of BSS objects . Normally , they go into .bss or .sbss via `` .common '' directives , but we need to override that and put them in .bss_below100 . We ca n't just use a section override ( like we do for .data_below100 ) , because that makes them initialized rather than uninitialized .


<s> bool isMem ( ) const override { if ( Kind != k_Memory ) return false ; if ( Memory . BaseRegNum && ! ARMMCRegisterClasses [ ARM :: GPRRegClassID ] . contains ( Memory . BaseRegNum ) ) return false ; if ( Memory . OffsetRegNum && ! ARMMCRegisterClasses [ ARM :: GPRRegClassID ] . contains ( Memory . OffsetRegNum ) ) return false ; return true ; } </s>

ARM ARM ARM::GPRRegClassID ARM ARM::GPRRegClassID


<s>
StringRef
getPassName
(
)
const
override
{
return
"NVPTX lower atomics of local memory"
;
}
</s>

getPassName - Return a nice clean name for a pass .

NVPTX
"NVPTX lower atomics of local memory"


<s> Register MipsOutgoingValueHandler :: getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO , ISD :: ArgFlagsTy Flags ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; MPO = MachinePointerInfo :: getStack ( MF , Offset ) ; LLT p0 = LLT :: pointer ( 0 , 32 ) ; LLT s32 = LLT :: scalar ( 32 ) ; auto SPReg = MIRBuilder . buildCopy ( p0 , Register ( Mips :: SP ) ) ; auto OffsetReg = MIRBuilder . buildConstant ( s32 , Offset ) ; auto AddrReg = MIRBuilder . buildPtrAdd ( p0 , SPReg , OffsetReg ) ; return AddrReg . getReg ( 0 ) ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


"internal error: instruction without _e64 suffix "

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ; AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool isReg ( ) const { return Kind == Register ; } </s>


"MSP430 DAG->DAG Pattern Instruction Selection"


<s>
const
char
*
output_probe_stack_range
(
rtx
reg1
,
rtx
reg2
)
{
static
int
labelno
=
0
;
char
loop_lab
[
32
]
;
rtx
xops
[
2
]
;
ASM_GENERATE_INTERNAL_LABEL
(
loop_lab
,
"LPSRL"
,
labelno
++
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
loop_lab
)
;
xops
[
0
]
=
reg1
;
xops
[
1
]
=
GEN_INT
(
PROBE_INTERVAL
)
;
output_asm_insn
(
"addi %0,%0,%1"
,
xops
)
;
xops
[
1
]
=
gen_rtx_REG
(
Pmode
,
0
)
;
output_asm_insn
(
"stw %1,0(%0)"
,
xops
)
;
xops
[
1
]
=
reg2
;
if
(
TARGET_64BIT
)
output_asm_insn
(
"cmpd 0,%0,%1"
,
xops
)
;
else
output_asm_insn
(
"cmpw 0,%0,%1"
,
xops
)
;
fputs
(
"\tbne 0,"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
loop_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
return
""
;
}
</s>

Wrapper around the output_probe_stack_range routines .


<s>
void
NodeAllocator
::
startNewBlock
(
)
{
void
*
T
=
MemPool
.
Allocate
(
NodesPerBlock
*
NodeMemSize
,
NodeMemSize
)
;
char
*
P
=
static_cast
<
char
*
>
(
T
)
;
Blocks
.
push_back
(
P
)
;
assert
(
(
Blocks
.
size
(
)
<
(
(
size_t
)
1
<<
(
8
*
sizeof
(
NodeId
)
BitsPerIndex
)
)
)
&&
"Out of bits for block index"
)
;
ActiveEnd
=
P
;
}
</s>

Set the current block to which generated machine instructions will be appended .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { const auto & Subtarget = MF . getSubtarget < WebAssemblySubtarget > ( ) ; TII = Subtarget . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; NumArgs = MF . getInfo < WebAssemblyFunctionInfo > ( ) -> getNumArguments ( ) ; return AsmPrinter :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


"AVR dynalloca stack pointer save/restore"


<s> bool isMachineVerifierClean ( ) const override { return false ; } </s>

Returns true if the target is expected to pass all machine verifier checks .


"AppendingLinkage is not supported by this target!"

Emit the specified global variable to the .s file .


"variable %q+D must be const in order to be put into"

Add the section attribute if the variable is in progmem .


<s> SDValue X86TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: VECTOR_SHUFFLE : return PerformShuffleCombine ( N , DAG , * this ) ; case ISD :: BUILD_VECTOR : return PerformBuildVectorCombine ( N , DAG , DCI , Subtarget , * this ) ; case ISD :: SELECT : return PerformSELECTCombine ( N , DAG , Subtarget ) ; case X86ISD :: CMOV : return PerformCMOVCombine ( N , DAG , DCI ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DAG , Subtarget ) ; case ISD :: STORE : return PerformSTORECombine ( N , DAG , Subtarget ) ; case X86ISD :: FXOR : case X86ISD :: FOR : return PerformFORCombine ( N , DAG ) ; case X86ISD :: FAND : return PerformFANDCombine ( N , DAG ) ; case X86ISD :: BT : return PerformBTCombine ( N , DAG , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; AU . addRequired < MachineDominatorTree > ( ) ; } </s>


<s>
void
HexagonHazardRecognizer
::
Reset
(
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Reset hazard recognizer\n"
)
;
Resources
->
clearResources
(
)
;
PacketNum
=
0
;
UsesDotCur
=
nullptr
;
DotCurPNum
=
1
;
UsesLoad
=
false
;
PrefVectorStoreNew
=
nullptr
;
RegDefs
.
clear
(
)
;
}
</s>


<s> static bool is_called_in_ARM_mode ( tree func ) { gcc_assert ( TREE_CODE ( func ) == FUNCTION_DECL ) ; if ( TARGET_CALLEE_INTERWORKING && TREE_PUBLIC ( func ) ) return true ; return lookup_attribute ( "interfacearm" , DECL_ATTRIBUTES ( func ) ) != NULL_TREE ; return false ; } </s>

Return non-zero if FUNC must be entered in ARM mode .


<s> machine_mode pdp11_cc_mode ( enum rtx_code op ATTRIBUTE_UNUSED , rtx x , rtx y ATTRIBUTE_UNUSED ) { if ( FLOAT_MODE_P ( GET_MODE ( x ) ) ) { switch ( GET_CODE ( x ) ) { case ABS : case NEG : case REG : case MEM : return CCmode ; default : return CCNZmode ; } } else { switch ( GET_CODE ( x ) ) { case XOR : case AND : case IOR : case MULT : case NOT : case REG : case MEM : return CCmode ; default : return CCNZmode ; } } } </s>

Select the CC mode to be used for the side effect compare with zero , given the compare operation code in op and the compare operands in x in and y .


<s> const uint16_t * AArch64RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_PCS_SaveList ; } </s>


<s> static bool cdx_shift_immed ( rtx op ) { if ( CONST_INT_P ( op ) ) { HOST_WIDE_INT ival = INTVAL ( op ) ; return ( ival == 1 || ival == 2 || ival == 3 || ival == 8 || ival == 12 || ival == 16 || ival == 24 || ival == 31 ) ; } return false ; } </s>

Returns true if OP is within range of CDX slli.n/srli.n immediates .


<s> void ValueReplacer :: schedule ( Value * Old , Value * New ) { WorkList . push_back ( std :: make_pair ( Old , New ) ) ; } </s>

Schedule - This is called back from ScheduleDAGInstrs : :Run ( ) when it 's time to do some work .


<s> static int function_arg_slotno ( const struct sparc_args * cum , machine_mode mode , const_tree type , bool named , bool incoming_p , int * pregno , int * ppadding ) { int regbase = ( incoming_p ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST ) ; int slotno = cum -> words ; enum mode_class mclass ; int regno ; * ppadding = 0 ; if ( type && TREE_ADDRESSABLE ( type ) ) return - 1 ; if ( TARGET_ARCH32 && mode == BLKmode && type && TYPE_ALIGN ( type ) % PARM_BOUNDARY != 0 ) return - 1 ; if ( TARGET_ARCH64 && ( type ? TYPE_ALIGN ( type ) : GET_MODE_ALIGNMENT ( mode ) ) >= 128 && ( slotno & 1 ) != 0 ) slotno ++ , * ppadding = 1 ; mclass = GET_MODE_CLASS ( mode ) ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) { if ( TREE_CODE ( TREE_TYPE ( type ) ) == REAL_TYPE ) { gcc_assert ( mode == BLKmode ) ; } else { gcc_assert ( mode != BLKmode ) ; mclass = MODE_FLOAT ; } } switch ( mclass ) { case MODE_FLOAT : case MODE_COMPLEX_FLOAT : case MODE_VECTOR_INT : if ( TARGET_ARCH64 && TARGET_FPU && named ) { if ( slotno >= SPARC_FP_ARG_MAX ) return - 1 ; regno = SPARC_FP_ARG_FIRST + slotno * 2 ; if ( GET_MODE_SIZE ( mode ) <= 4 ) regno ++ ; break ; } case MODE_INT : case MODE_COMPLEX_INT : if ( slotno >= SPARC_INT_ARG_MAX ) return - 1 ; regno = regbase + slotno ; break ; case MODE_RANDOM : if ( mode == VOIDmode ) return - 1 ; gcc_assert ( mode == BLKmode ) ; if ( TARGET_ARCH32 || ! type || ( TREE_CODE ( type ) != VECTOR_TYPE && TREE_CODE ( type ) != RECORD_TYPE ) ) { if ( slotno >= SPARC_INT_ARG_MAX ) return - 1 ; regno = regbase + slotno ; } else { int intregs_p = 0 , fpregs_p = 0 , packed_p = 0 ; if ( TREE_CODE ( type ) == VECTOR_TYPE ) fpregs_p = 1 ; else scan_record_type ( type , & intregs_p , & fpregs_p , & packed_p ) ; if ( packed_p || ! named ) fpregs_p = 0 , intregs_p = 1 ; if ( fpregs_p && slotno >= SPARC_FP_ARG_MAX ) return - 1 ; if ( ! fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX ) return - 1 ; return slotno ; } break ; default : gcc_unreachable ( ) ; } * pregno = regno ; return slotno ; } </s>

Compute the slot number to pass an argument in . Return the slot number or -1 if passing on the stack . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . INCOMING_P is zero for FUNCTION_ARG , nonzero for FUNCTION_INCOMING_ARG . * PREGNO records the register number to use if scalar type . * PPADDING records the amount of padding needed in words .


<s> bool SIInstrInfo :: modifiesModeRegister ( const MachineInstr & MI ) { if ( const MCPhysReg * ImpDef = MI . getDesc ( ) . getImplicitDefs ( ) ) { for ( ; ImpDef && * ImpDef ; ++ ImpDef ) { if ( * ImpDef == AMDGPU :: MODE ) return true ; } } return false ; } </s>

Return true if the instruction modifies the mode register.q .


<s> static bool rs6000_emit_move_si_sf_subreg ( rtx dest , rtx source , machine_mode mode ) { if ( TARGET_DIRECT_MOVE_64BIT && ! reload_in_progress && ! reload_completed && ! lra_in_progress && ( ! SUBREG_P ( dest ) || ! sf_subreg_operand ( dest , mode ) ) && SUBREG_P ( source ) && sf_subreg_operand ( source , mode ) ) { rtx inner_source = SUBREG_REG ( source ) ; machine_mode inner_mode = GET_MODE ( inner_source ) ; if ( mode == SImode && inner_mode == SFmode ) { emit_insn ( gen_movsi_from_sf ( dest , inner_source ) ) ; return true ; } if ( mode == SFmode && inner_mode == SImode ) { emit_insn ( gen_movsf_from_si ( dest , inner_source ) ) ; return true ; } } return false ; } </s>

Helper function to change moves with : ( SUBREG : SF ( REG : SI ) ) and ( SUBREG : SI ( REG : SF ) ) into separate UNSPEC insns . In the PowerPC architecture , scalar SFmode values are stored as DFmode values in the VSX registers . We need to convert the bits before we can use a direct move or operate on the bits in the vector register as an integer type . Skip things like ( set ( SUBREG : SI ( ... ) ( SUBREG : SI ( ... ) ) .


<s> const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s>
const
TargetRegisterClass
*
MipsRegisterInfo
::
getPointerRegClass
(
const
MachineFunction
&
MF
,
unsigned
Kind
)
const
{
MipsABIInfo
ABI
=
MF
.
getSubtarget
<
MipsSubtarget
>
(
)
.
getABI
(
)
;
MipsPtrClass
PtrClassKind
=
static_cast
<
MipsPtrClass
>
(
Kind
)
;
switch
(
PtrClassKind
)
{
case
MipsPtrClass
::
Default
:
return
ABI
.
ArePtrs64bit
(
)
&
Mips
::
GPR64RegClass
:
&
Mips
::
GPR32RegClass
;
case
MipsPtrClass
::
GPR16MM
:
return
ABI
.
ArePtrs64bit
(
)
&
Mips
::
GPRMM16_64RegClass
:
&
Mips
::
GPRMM16RegClass
;
case
MipsPtrClass
::
StackPointer
:
return
ABI
.
ArePtrs64bit
(
)
&
Mips
::
SP64RegClass
:
&
Mips
::
SP32RegClass
;
case
MipsPtrClass
::
GlobalPointer
:
return
ABI
.
ArePtrs64bit
(
)
&
Mips
::
GP64RegClass
:
&
Mips
::
GP32RegClass
;
}
llvm_unreachable
(
"Unknown pointer kind"
)
;
}
</s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> int neon_immediate_valid_for_move ( rtx op , machine_mode mode , rtx * modconst , int * elementwidth ) { rtx tmpconst ; int tmpwidth ; int retval = neon_valid_immediate ( op , mode , 0 , & tmpconst , & tmpwidth ) ; if ( retval == - 1 ) return 0 ; if ( modconst ) * modconst = tmpconst ; if ( elementwidth ) * elementwidth = tmpwidth ; return 1 ; } </s>

Return TRUE if rtx X is legal for use as either a Neon VMOV ( or , implicitly , VMVN ) immediate . Write back width per element to * ELEMENTWIDTH ( or zero for float elements ) , and a modified constant ( whatever should be output for a VMOV ) in * MODCONST .


<s> bool X86TTIImpl :: isLegalBroadcastLoad ( Type * ElementTy , ElementCount NumElements ) const { return ST -> hasSSE3 ( ) && ! NumElements . isScalable ( ) && NumElements . getFixedValue ( ) == 2 && ElementTy == Type :: getDoubleTy ( ElementTy -> getContext ( ) ) ; } </s>

\Returns true if the target supports broadcasting a load to a vector of type < NumElements x ElementTy > .


<s> bool AlphaAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; O << "0(" ; printOperand ( MI , OpNo , O ) ; O << ")" ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> static unsigned estimateStackSize ( MachineFunction & MF , MachineFrameInfo * MFI ) { const MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; int Offset = 0 ; for ( int i = FFI -> getObjectIndexBegin ( ) ; i != 0 ; ++ i ) { int FixedOff = - FFI -> getObjectOffset ( i ) ; if ( FixedOff > Offset ) Offset = FixedOff ; } for ( unsigned i = 0 , e = FFI -> getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( FFI -> isDeadObjectIndex ( i ) ) continue ; Offset += FFI -> getObjectSize ( i ) ; unsigned Align = FFI -> getObjectAlignment ( i ) ; Offset = ( Offset + Align - 1 ) / Align * Align ; } return ( unsigned ) Offset ; } </s>

Estimate and return the size of the stack frame .


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( 1 , true , true , false , true ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


"The .note.gnu.property is not emitted because it is already present."

Callback used to implement the .note.gnu.property section .


<s>
void
SNESMCInstLower
::
lowerInstruction
(
const
MachineInstr
&
MI
,
MCInst
&
OutMI
)
const
{
OutMI
.
setOpcode
(
MI
.
getOpcode
(
)
)
;
for
(
MachineOperand
const
&
MO
:
MI
.
operands
(
)
)
{
MCOperand
MCOp
;
switch
(
MO
.
getType
(
)
)
{
default
:
MI
.
print
(
errs
(
)
)
;
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
)
continue
;
MCOp
=
MCOperand
::
createReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
createImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
getSymbol
(
MO
.
getGlobal
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
createExpr
(
MCSymbolRefExpr
::
create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
Ctx
)
)
;
break
;
case
MachineOperand
::
MO_RegisterMask
:
continue
;
case
MachineOperand
::
MO_BlockAddress
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetJTISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetCPISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
}
OutMI
.
addOperand
(
MCOp
)
;
}
}
</s>


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: CreateImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ; } </s>


<s> static void push_regs ( HARD_REG_SET * mask , int interrupt_handler ) { int i = interrupt_handler ? LAST_BANKED_REG + 1 : 0 ; int skip_fpscr = 0 ; for ( ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { if ( i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD && hard_reg_set_intersect_p ( * mask , reg_class_contents [ DF_REGS ] ) ) { HARD_REG_SET unsaved ; push ( FPSCR_REG ) ; COMPL_HARD_REG_SET ( unsaved , * mask ) ; fpscr_set_from_mem ( NORMAL_MODE ( FP_MODE ) , unsaved ) ; skip_fpscr = 1 ; } if ( i != PR_REG && ( i != FPSCR_REG || ! skip_fpscr ) && TEST_HARD_REG_BIT ( * mask , i ) ) { if ( ! ( sh_cfun_resbank_handler_p ( ) && ( ( i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG ) || i == MACH_REG || i == MACL_REG || i == GBR_REG ) ) ) push ( i ) ; } } if ( interrupt_handler ) { bool use_movml = false ; if ( TARGET_SH2A ) { unsigned int count = 0 ; for ( i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) if ( TEST_HARD_REG_BIT ( * mask , i ) ) count ++ ; else break ; if ( count == LAST_BANKED_REG - FIRST_BANKED_REG + 1 ) use_movml = true ; } if ( sh_cfun_resbank_handler_p ( ) ) ; else if ( use_movml ) { rtx x , mem , reg , set ; rtx sp_reg = gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) ; emit_insn ( gen_blockage ( ) ) ; x = gen_movml_push_banked ( sp_reg ) ; x = frame_insn ( x ) ; for ( i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) { mem = gen_rtx_MEM ( SImode , plus_constant ( Pmode , sp_reg , i * 4 ) ) ; reg = gen_rtx_REG ( SImode , i ) ; add_reg_note ( x , REG_CFA_OFFSET , gen_rtx_SET ( mem , reg ) ) ; } set = gen_rtx_SET ( sp_reg , plus_constant ( Pmode , sp_reg , - 32 ) ) ; add_reg_note ( x , REG_CFA_ADJUST_CFA , set ) ; emit_insn ( gen_blockage ( ) ) ; } else for ( i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) if ( TEST_HARD_REG_BIT ( * mask , i ) ) push ( i ) ; } if ( TEST_HARD_REG_BIT ( * mask , PR_REG ) && ! sh_cfun_resbank_handler_p ( ) ) push ( PR_REG ) ; } </s>

Generate code to push the regs specified in the mask . remember that the mask is of the internal shape of the regs , not the external shape - so go through the renumber vector


<s> bool AArch64AsmParser :: ParseDirective ( AsmToken DirectiveID ) { const MCObjectFileInfo :: Environment Format = getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ; bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; auto IDVal = DirectiveID . getIdentifier ( ) . lower ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == ".arch" ) parseDirectiveArch ( Loc ) ; else if ( IDVal == ".cpu" ) parseDirectiveCPU ( Loc ) ; else if ( IDVal == ".tlsdesccall" ) parseDirectiveTLSDescCall ( Loc ) ; else if ( IDVal == ".ltorg" || IDVal == ".pool" ) parseDirectiveLtorg ( Loc ) ; else if ( IDVal == ".unreq" ) parseDirectiveUnreq ( Loc ) ; else if ( IDVal == ".inst" ) parseDirectiveInst ( Loc ) ; else if ( IDVal == ".cfi_negate_ra_state" ) parseDirectiveCFINegateRAState ( ) ; else if ( IDVal == ".cfi_b_key_frame" ) parseDirectiveCFIBKeyFrame ( ) ; else if ( IDVal == ".arch_extension" ) parseDirectiveArchExtension ( Loc ) ; else if ( IDVal == ".variant_pcs" ) parseDirectiveVariantPCS ( Loc ) ; else if ( IsMachO ) { if ( IDVal == MCLOHDirectiveName ( ) ) parseDirectiveLOH ( IDVal , Loc ) ; else return true ; } else return true ; return false ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


"Unexpected register class in CSRsViaCopy!"

"Function should be nounwind in insertCopiesSplitCSR!"

Insert explicit copies in entry and exit blocks .


<s> static bool rs6000_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE ( mode ) ) return true ; if ( TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) return true ; else if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) && ! FLOAT128_IEEE_P ( mode ) ) return true ; else return false ; } </s>

Target hook for vector_mode_supported_p .


"%<-fsplit-stack%> does not support fastcall with "

"%<-fsplit-stack%> does not support 2 register "

"%<-fsplit-stack%> does not support 3 register parameters"

Return a scratch register to use in the split stack prologue . The split stack prologue is used for -fsplit-stack . It is the first instructions in the function , even before the regular prologue . The scratch register can be any caller-saved register which is not used for parameters or for the static chain .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , LittleEndian ) , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( createTLOF ( Triple ( getTargetTriple ( ) ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; } </s>


<s> bool isMultiStoresCheaperThanBitsMerge ( EVT LTy , EVT HTy ) const override { if ( ( LTy . isFloatingPoint ( ) && HTy . isInteger ( ) ) || ( LTy . isInteger ( ) && HTy . isFloatingPoint ( ) ) ) return true ; return false ; } </s>

Return true if it is cheaper to split the store of a merged int val from a pair of smaller values into multiple stores .


<s> void AArch64TargetStreamer :: finish ( ) { ConstantPools -> emitAll ( Streamer ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s>
SDNode
*
TriCoreDAGToDAGISel
::
Select
(
SDNode
*
N
)
{
SDLoc
dl
(
N
)
;
DEBUG
(
errs
(
)
.
changeColor
(
raw_ostream
::
GREEN
)
<<
"Selecting: "
)
;
DEBUG
(
N
->
dump
(
CurDAG
)
)
;
DEBUG
(
errs
(
)
<<
"\n"
)
;
switch
(
N
->
getOpcode
(
)
)
{
case
ISD
::
Constant
:
return
SelectConstant
(
N
)
;
case
ISD
::
FrameIndex
:
{
int
FI
=
cast
<
FrameIndexSDNode
>
(
N
)
->
getIndex
(
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
MVT
::
i32
)
;
if
(
N
->
hasOneUse
(
)
)
{
return
CurDAG
->
SelectNodeTo
(
N
,
TriCore
::
ADDrc
,
MVT
::
i32
,
TFI
,
CurDAG
->
getTargetConstant
(
0
,
dl
,
MVT
::
i32
)
)
;
}
return
CurDAG
->
getMachineNode
(
TriCore
::
ADDrc
,
dl
,
MVT
::
i32
,
TFI
,
CurDAG
->
getTargetConstant
(
0
,
dl
,
MVT
::
i32
)
)
;
}
case
ISD
::
STORE
:
{
ptyType
=
false
;
ptyType
=
(
N
->
getOperand
(
1
)
.
getValueType
(
)
==
MVT
::
iPTR
)
true
:
false
;
break
;
}
}
SDNode
*
ResNode
=
SelectCode
(
N
)
;
DEBUG
(
errs
(
)
<<
"=> "
)
;
if
(
ResNode
==
nullptr
||
ResNode
==
N
)
DEBUG
(
N
->
dump
(
CurDAG
)
)
;
else
DEBUG
(
ResNode
->
dump
(
CurDAG
)
)
;
DEBUG
(
errs
(
)
<<
"\n"
)
;
return
ResNode
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> unsigned getNumFixupKinds ( ) const { return ARM :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s>
int
AlphaRegisterInfo
::
getDwarfRegNum
(
unsigned
RegNum
,
bool
isEH
)
const
{
llvm_unreachable
(
"What is the dwarf register number"
)
;
return
1
;
}
</s>

Map a target register to an equivalent dwarf register number .

Alpha
Alpha
"What is the dwarf register number"
1


<s> const SICInstrInfo * getInstrInfo ( ) const override { return InstrInfo . get ( ) ; } </s>


<s> bool LanaiAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] ) return true ; switch ( ExtraCode [ 0 ] ) { case 'H' : { if ( OpNo == 0 ) return true ; const MachineOperand & FlagsOP = MI -> getOperand ( OpNo - 1 ) ; if ( ! FlagsOP . isImm ( ) ) return true ; unsigned Flags = FlagsOP . getImm ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; if ( NumVals != 2 ) return true ; unsigned RegOp = OpNo + 1 ; if ( RegOp >= MI -> getNumOperands ( ) ) return true ; const MachineOperand & MO = MI -> getOperand ( RegOp ) ; if ( ! MO . isReg ( ) ) return true ; unsigned Reg = MO . getReg ( ) ; O << LanaiInstPrinter :: getRegisterName ( Reg ) ; return false ; } default : return true ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> hasFnAttribute ( Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( ( N -> getOpcode ( ) == X86ISD :: CALL && ! Subtarget -> callRegIndirect ( ) ) || ( N -> getOpcode ( ) == X86ISD :: TC_RETURN && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; MVT SrcVT = N -> getOperand ( 0 ) . getSimpleValueType ( ) ; MVT DstVT = N -> getSimpleValueType ( 0 ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const X86TargetLowering * X86Lowering = static_cast < const X86TargetLowering * > ( TLI ) ; bool SrcIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } MVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> void ix86_expand_vector_init ( bool mmx_ok , rtx target , rtx vals ) { machine_mode mode = GET_MODE ( target ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; int n_elts = GET_MODE_NUNITS ( mode ) ; int n_var = 0 , one_var = - 1 ; bool all_same = true , all_const_zero = true ; int i ; rtx x ; for ( i = 0 ; i < n_elts ; ++ i ) { x = XVECEXP ( vals , 0 , i ) ; if ( ! ( CONST_INT_P ( x ) || GET_CODE ( x ) == CONST_DOUBLE || GET_CODE ( x ) == CONST_FIXED ) ) n_var ++ , one_var = i ; else if ( x != CONST0_RTX ( inner_mode ) ) all_const_zero = false ; if ( i > 0 && ! rtx_equal_p ( x , XVECEXP ( vals , 0 , 0 ) ) ) all_same = false ; } if ( n_var == 0 ) { emit_move_insn ( target , gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , 0 ) ) ) ; return ; } if ( all_same && ix86_expand_vector_init_duplicate ( mmx_ok , mode , target , XVECEXP ( vals , 0 , 0 ) ) ) return ; if ( n_var == 1 ) { if ( all_const_zero && ix86_expand_vector_init_one_nonzero ( mmx_ok , mode , target , XVECEXP ( vals , 0 , one_var ) , one_var ) ) return ; if ( ix86_expand_vector_init_one_var ( mmx_ok , mode , target , vals , one_var ) ) return ; } ix86_expand_vector_init_general ( mmx_ok , mode , target , vals ) ; } </s>

Initialize vector TARGET via VALS . Suppress the use of MMX instructions unless MMX_OK is true .


"Malformed basic block: unconditional branch not last"

Remove the branching code at the end of the specific MBB .


<s> void AArch64AsmPrinter :: emitEndOfAsmFile ( Module & M ) { EmitHwasanMemaccessSymbols ( M ) ; const Triple & TT = TM . getTargetTriple ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { OutStreamer -> emitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } emitStackMaps ( SM ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> void AMDGPUTTIImpl :: getUnrollingPreferences ( Loop * L , TTI :: UnrollingPreferences & UP ) { UP . Threshold = 300 ; UP . MaxCount = UINT_MAX ; UP . Partial = true ; const unsigned MaxAlloca = ( 256 - 16 ) * 4 ; for ( const BasicBlock * BB : L -> getBlocks ( ) ) { const DataLayout & DL = BB -> getModule ( ) -> getDataLayout ( ) ; for ( const Instruction & I : * BB ) { const GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( & I ) ; if ( ! GEP || GEP -> getAddressSpace ( ) != AMDGPUAS :: PRIVATE_ADDRESS ) continue ; const Value * Ptr = GEP -> getPointerOperand ( ) ; const AllocaInst * Alloca = dyn_cast < AllocaInst > ( GetUnderlyingObject ( Ptr , DL ) ) ; if ( Alloca && Alloca -> isStaticAlloca ( ) ) { Type * Ty = Alloca -> getAllocatedType ( ) ; unsigned AllocaSize = Ty -> isSized ( ) ? DL . getTypeAllocSize ( Ty ) : 0 ; if ( AllocaSize > MaxAlloca ) continue ; bool HasLoopDef = false ; for ( const Value * Op : GEP -> operands ( ) ) { const Instruction * Inst = dyn_cast < Instruction > ( Op ) ; if ( ! Inst || L -> isLoopInvariant ( Op ) ) continue ; if ( any_of ( L -> getSubLoops ( ) , [ Inst ] ( const Loop * SubLoop ) { return SubLoop -> contains ( Inst ) ; } ) ) continue ; HasLoopDef = true ; break ; } if ( ! HasLoopDef ) continue ; UP . Threshold = UnrollThresholdPrivate ; return ; } } } } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> static void rs6000_elf_unique_section ( tree decl , int reloc ) { default_unique_section_1 ( decl , reloc , flag_pic || DEFAULT_ABI == ABI_AIX ) ; } </s>

A C statement to build up a unique section name , expressed as a STRING_CST node , and assign it to DECL_SECTION_NAME ( decl ) . RELOC indicates whether the initial value of EXP requires link-time relocations . If you do not define this macro , GCC will use the symbol name prefixed by ` . ' as the section name . Note - this macro can now be called for uninitialized data items as well as initialized data and functions .


<s>
void
relaxInstruction
(
const
MCInst
&
Inst
,
MCInst
&
Res
)
const
override
{
assert
(
!
"Not implemented"
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> unsigned PatmosInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == Patmos :: SWC || MI -> getOpcode ( ) == Patmos :: SHC || MI -> getOpcode ( ) == Patmos :: SBC ) { if ( MI -> getOperand ( 2 ) . isFI ( ) && MI -> getOperand ( 3 ) . isImm ( ) && MI -> getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 2 ) . getIndex ( ) ; return MI -> getOperand ( 4 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> rtx xtensa_copy_incoming_a7 ( rtx opnd ) { rtx entry_insns = 0 ; rtx reg , tmp ; machine_mode mode ; if ( ! cfun -> machine -> need_a7_copy ) return opnd ; gcc_assert ( ! cfun -> machine -> set_frame_ptr_insn ) ; mode = GET_MODE ( opnd ) ; reg = opnd ; if ( GET_CODE ( reg ) == SUBREG ) { gcc_assert ( SUBREG_BYTE ( reg ) == 0 ) ; reg = SUBREG_REG ( reg ) ; } if ( GET_CODE ( reg ) != REG || REGNO ( reg ) > A7_REG || REGNO ( reg ) + hard_regno_nregs ( A7_REG , mode ) <= A7_REG ) return opnd ; gcc_assert ( REGNO ( reg ) + hard_regno_nregs ( A7_REG , mode ) - 1 == A7_REG ) ; cfun -> machine -> need_a7_copy = false ; start_sequence ( ) ; tmp = gen_reg_rtx ( mode ) ; switch ( mode ) { case E_DFmode : case E_DImode : emit_insn ( gen_movsi_internal ( gen_rtx_SUBREG ( SImode , tmp , 4 ) , gen_raw_REG ( SImode , A7_REG ) ) ) ; break ; case E_SFmode : emit_insn ( gen_movsf_internal ( tmp , gen_raw_REG ( mode , A7_REG ) ) ) ; break ; case E_SImode : emit_insn ( gen_movsi_internal ( tmp , gen_raw_REG ( mode , A7_REG ) ) ) ; break ; case E_HImode : emit_insn ( gen_movhi_internal ( tmp , gen_raw_REG ( mode , A7_REG ) ) ) ; break ; case E_QImode : emit_insn ( gen_movqi_internal ( tmp , gen_raw_REG ( mode , A7_REG ) ) ) ; break ; default : gcc_unreachable ( ) ; } cfun -> machine -> set_frame_ptr_insn = emit_insn ( gen_set_frame_ptr ( ) ) ; if ( mode == DFmode || mode == DImode ) emit_insn ( gen_movsi_internal ( gen_rtx_SUBREG ( SImode , tmp , 0 ) , gen_rtx_REG ( SImode , A7_REG - 1 ) ) ) ; entry_insns = get_insns ( ) ; end_sequence ( ) ; if ( cfun -> machine -> vararg_a7 ) { cfun -> machine -> vararg_a7_copy = entry_insns ; } else { push_topmost_sequence ( ) ; emit_insn_after ( entry_insns , get_insns ( ) ) ; pop_topmost_sequence ( ) ; } return tmp ; } </s>

Check if an incoming argument in a7 is expected to be used soon and if OPND is a register or register pair that includes a7 . If so , create a new pseudo and copy a7 into that pseudo at the very beginning of the function , followed by the special `` set_frame_ptr '' unspec_volatile insn . The return value is either the original operand , if it is not a7 , or the new pseudo containing a copy of the incoming argument . This is necessary because the register allocator will ignore conflicts with a7 and may either assign some other pseudo to a7 or use a7 as the hard_frame_pointer , clobbering the incoming argument in a7 . By copying the argument out of a7 as the very first thing , and then immediately following that with an unspec_volatile to keep the scheduler away , we should avoid any problems . Putting the set_frame_ptr insn at the beginning , with only the a7 copy before it , also makes it easier for the prologue expander to initialize the frame pointer after the a7 copy and to fix up the a7 copy to use the stack pointer instead of the frame pointer .


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> static const char * get_some_local_dynamic_name ( void ) { rtx insn ; if ( cfun -> machine -> some_ld_name ) return cfun -> machine -> some_ld_name ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) && for_each_rtx ( & PATTERN ( insn ) , get_some_local_dynamic_name_1 , 0 ) ) return cfun -> machine -> some_ld_name ; gcc_unreachable ( ) ; } </s>

Locate some local-dynamic symbol still in use by this function so that we can print its name in local-dynamic base patterns .


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , TargetMachine & TM , bool IsLittle , const TargetOptions & Options ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , ARMProcClass ( None ) , stackAlignment ( 4 ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( Options ) , TargetABI ( ARM_ABI_UNKNOWN ) , DL ( computeDataLayout ( initializeSubtargetDependencies ( CPU , FS ) ) ) , TSInfo ( DL ) , InstrInfo ( isThumb1Only ( ) ? ( ARMBaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( ARMBaseInstrInfo * ) new ARMInstrInfo ( * this ) : ( ARMBaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM ) , FrameLowering ( ! isThumb1Only ( ) ? new ARMFrameLowering ( * this ) : ( ARMFrameLowering * ) new Thumb1FrameLowering ( * this ) ) { } </s>

This constructor initializes the data members to match that of the specified triple .

ARM ARM ARM ARM ARM ARM 4 ARM ARM ARM ARM ARM ARM ARM


<s> void PPCAsmPrinter :: PrintSymbolOperand ( const MachineOperand & MO , raw_ostream & O ) { const GlobalValue * GV = MO . getGlobal ( ) ; MCSymbol * SymToPrint ; if ( Subtarget -> hasLazyResolverStub ( GV ) ) { SymToPrint = getSymbolWithGlobalValueBase ( GV , "$non_lazy_ptr" ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( SymToPrint ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else { SymToPrint = getSymbol ( GV ) ; } SymToPrint -> print ( O , MAI ) ; printOffset ( MO . getOffset ( ) , O ) ; } </s>


<s> static bool valid_bL_core_p ( unsigned int * core , unsigned int bL_core ) { return AARCH64_BIG_LITTLE ( core [ 0 ] , core [ 1 ] ) == bL_core || AARCH64_BIG_LITTLE ( core [ 1 ] , core [ 0 ] ) == bL_core ; } </s>

Check wether the CORE array is the same as the big.LITTLE BL_CORE . For an example CORE= { 0xd08 , 0xd03 } and BL_CORE=AARCH64_BIG_LITTLE ( 0xd08 , 0xd03 ) will return true .


<s> static int noncall_uses_reg ( rtx reg , rtx insn , rtx * set ) { rtx pattern , reg2 ; * set = NULL_RTX ; reg2 = sfunc_uses_reg ( insn ) ; if ( reg2 && REGNO ( reg2 ) == REGNO ( reg ) ) { pattern = single_set ( insn ) ; if ( pattern && GET_CODE ( SET_DEST ( pattern ) ) == REG && REGNO ( reg ) == REGNO ( SET_DEST ( pattern ) ) ) * set = pattern ; return 0 ; } if ( GET_CODE ( insn ) != CALL_INSN ) { pattern = single_set ( insn ) ; if ( pattern && GET_CODE ( SET_DEST ( pattern ) ) == REG && REGNO ( reg ) == REGNO ( SET_DEST ( pattern ) ) ) { rtx par , part ; int i ; * set = pattern ; par = PATTERN ( insn ) ; if ( GET_CODE ( par ) == PARALLEL ) for ( i = XVECLEN ( par , 0 ) - 1 ; i >= 0 ; i -- ) { part = XVECEXP ( par , 0 , i ) ; if ( GET_CODE ( part ) != SET && reg_mentioned_p ( reg , part ) ) return 1 ; } return reg_mentioned_p ( reg , SET_SRC ( pattern ) ) ; } return 1 ; } pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) == PARALLEL ) { int i ; for ( i = XVECLEN ( pattern , 0 ) - 1 ; i >= 1 ; i -- ) if ( reg_mentioned_p ( reg , XVECEXP ( pattern , 0 , i ) ) ) return 1 ; pattern = XVECEXP ( pattern , 0 , 0 ) ; } if ( GET_CODE ( pattern ) == SET ) { if ( reg_mentioned_p ( reg , SET_DEST ( pattern ) ) ) { if ( GET_CODE ( SET_DEST ( pattern ) ) != REG || REGNO ( reg ) != REGNO ( SET_DEST ( pattern ) ) ) return 1 ; * set = pattern ; } pattern = SET_SRC ( pattern ) ; } if ( GET_CODE ( pattern ) != CALL || GET_CODE ( XEXP ( pattern , 0 ) ) != MEM || ! rtx_equal_p ( reg , XEXP ( XEXP ( pattern , 0 ) , 0 ) ) ) return 1 ; return 0 ; } </s>

See if the only way in which INSN uses REG is by calling it , or by setting it while calling it . Set * SET to a SET rtx if the register is set by INSN .


<s> inline static void aarch64_print_hint_for_arch ( const char * str ) { aarch64_print_hint_for_core_or_arch ( str , true ) ; } </s>

Print a hint with a suggestion for an architecture name that most closely resembles what the user passed in STR .


<s> bool aarch64_sve_float_mul_immediate_p ( rtx x ) { rtx elt ; return ( const_vec_duplicate_p ( x , & elt ) && GET_CODE ( elt ) == CONST_DOUBLE && real_equal ( CONST_DOUBLE_REAL_VALUE ( elt ) , & dconsthalf ) ) ; } </s>

Return true if X is a valid immediate operand for an SVE FMUL instruction .


<s> bool MipsRegisterInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
void
SystemZPostRASchedStrategy
::
leaveMBB
(
)
{
DEBUG
(
dbgs
(
)
<<
"** Leaving "
<<
printMBBReference
(
*
MBB
)
<<
"\n"
;
)
;
advanceTo
(
MBB
->
getFirstTerminator
(
)
)
;
}
</s>

Tell the strategy that current MBB is done .


<s> void rs6000_emit_sCOND ( machine_mode mode , rtx operands [ ] ) { rtx condition_rtx ; machine_mode op_mode ; enum rtx_code cond_code ; rtx result = operands [ 0 ] ; condition_rtx = rs6000_generate_compare ( operands [ 1 ] , mode ) ; cond_code = GET_CODE ( condition_rtx ) ; if ( FLOAT_MODE_P ( mode ) && ! TARGET_FPRS && TARGET_HARD_FLOAT ) { rtx t ; PUT_MODE ( condition_rtx , SImode ) ; t = XEXP ( condition_rtx , 0 ) ; gcc_assert ( cond_code == NE || cond_code == EQ ) ; if ( cond_code == NE ) emit_insn ( gen_e500_flip_gt_bit ( t , t ) ) ; emit_insn ( gen_move_from_CR_gt_bit ( result , t ) ) ; return ; } if ( cond_code == NE || cond_code == GE || cond_code == LE || cond_code == GEU || cond_code == LEU || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE ) { rtx not_result = gen_reg_rtx ( CCEQmode ) ; rtx not_op , rev_cond_rtx ; machine_mode cc_mode ; cc_mode = GET_MODE ( XEXP ( condition_rtx , 0 ) ) ; rev_cond_rtx = gen_rtx_fmt_ee ( rs6000_reverse_condition ( cc_mode , cond_code ) , SImode , XEXP ( condition_rtx , 0 ) , const0_rtx ) ; not_op = gen_rtx_COMPARE ( CCEQmode , rev_cond_rtx , const0_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , not_result , not_op ) ) ; condition_rtx = gen_rtx_EQ ( VOIDmode , not_result , const0_rtx ) ; } op_mode = GET_MODE ( XEXP ( operands [ 1 ] , 0 ) ) ; if ( op_mode == VOIDmode ) op_mode = GET_MODE ( XEXP ( operands [ 1 ] , 1 ) ) ; if ( TARGET_POWERPC64 && ( op_mode == DImode || FLOAT_MODE_P ( mode ) ) ) { PUT_MODE ( condition_rtx , DImode ) ; convert_move ( result , condition_rtx , 0 ) ; } else { PUT_MODE ( condition_rtx , SImode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , result , condition_rtx ) ) ; } } </s>


<s>
void
dump
(
)
{
dbgs
(
)
<<
"Start is "
;
if
(
StartSel
)
{
dbgs
(
)
<<
Start
.
ImmVal
<<
"\n"
;
}
else
{
dbgs
(
)
<<
"%vreg"
<<
Start
.
Reg
<<
"\n"
;
}
dbgs
(
)
<<
"Boundary is "
;
if
(
BoundarySel
)
{
dbgs
(
)
<<
Boundary
.
ImmVal
<<
"\n"
;
}
else
{
dbgs
(
)
<<
"%vreg"
<<
Boundary
.
Reg
<<
"\n"
;
}
dbgs
(
)
<<
"Step is "
;
if
(
StepSel
)
{
dbgs
(
)
<<
Step
.
ImmVal
<<
"\n"
;
}
else
{
dbgs
(
)
<<
"%vreg"
<<
Step
.
Reg
<<
"\n"
;
}
dbgs
(
)
<<
"Cmp mode is "
<<
Mode
<<
"\n"
;
}
</s>

Dump the plan to stderr ( for debugging ) .

TPC
"Start is "
"\n"
"%vreg"
"\n"
"Boundary is "
"\n"
"%vreg"
"\n"
"Step is "
"\n"
"%vreg"
"\n"
"Cmp mode is "
"\n"


Create a MODE vector constant from 4 ints .


<s> enum attr_cc compute_a_shift_cc ( rtx insn ATTRIBUTE_UNUSED , rtx * operands ) { rtx shift = operands [ 3 ] ; machine_mode mode = GET_MODE ( shift ) ; enum rtx_code code = GET_CODE ( shift ) ; enum shift_type shift_type ; enum shift_mode shift_mode ; struct shift_info info ; int n ; switch ( mode ) { case QImode : shift_mode = QIshift ; break ; case HImode : shift_mode = HIshift ; break ; case SImode : shift_mode = SIshift ; break ; default : gcc_unreachable ( ) ; } switch ( code ) { case ASHIFTRT : shift_type = SHIFT_ASHIFTRT ; break ; case LSHIFTRT : shift_type = SHIFT_LSHIFTRT ; break ; case ASHIFT : shift_type = SHIFT_ASHIFT ; break ; default : gcc_unreachable ( ) ; } gcc_assert ( GET_CODE ( operands [ 2 ] ) == CONST_INT ) ; n = INTVAL ( operands [ 2 ] ) ; if ( n < 0 ) n = 0 ; else if ( ( unsigned int ) n > GET_MODE_BITSIZE ( mode ) ) n = GET_MODE_BITSIZE ( mode ) ; get_shift_alg ( shift_type , shift_mode , n , & info ) ; switch ( info . alg ) { case SHIFT_SPECIAL : if ( info . remainder == 0 ) return info . cc_special ; case SHIFT_INLINE : return info . cc_inline ; case SHIFT_ROT_AND : return CC_SET_ZNV ; case SHIFT_LOOP : if ( info . shift2 != NULL ) { if ( n % 2 ) return info . cc_inline ; } return CC_CLOBBER ; default : gcc_unreachable ( ) ; } } </s>

Compute which flag bits are valid after a shift insn .


<s> StringRef getPassName ( ) const override { return RISCV_INSERT_VSETVLI_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> static int unspec_cond_fcmla ( int rot ) { switch ( rot ) { case 0 : return UNSPEC_COND_FCMLA ; case 90 : return UNSPEC_COND_FCMLA90 ; case 180 : return UNSPEC_COND_FCMLA180 ; case 270 : return UNSPEC_COND_FCMLA270 ; default : gcc_unreachable ( ) ; } } </s>

Return the UNSPEC_COND_FCMLA * unspec for rotation amount ROT .


<s> bool small_data_pattern ( rtx op , machine_mode ) { if ( GET_CODE ( op ) == SEQUENCE ) return false ; rtx rgp = gen_rtx_REG ( Pmode , SDATA_BASE_REGNUM ) ; subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , op , ALL ) { const_rtx x = * iter ; if ( GET_CODE ( x ) == PLUS && rtx_equal_p ( XEXP ( x , 0 ) , rgp ) ) iter . skip_subrtxes ( ) ; else if ( arc_rewrite_small_data_p ( x ) ) return true ; } return false ; } </s>

Return true if OP refers to small data symbols directly , not through a PLUS .


<s> static inline int multcosts ( rtx x ATTRIBUTE_UNUSED ) { if ( sh_multcost >= 0 ) return sh_multcost ; if ( TARGET_SHMEDIA ) return TARGET_SMALLCODE ? 2 : 3 ; if ( TARGET_SH2 ) { if ( TARGET_SMALLCODE ) return 2 ; return 3 ; } if ( TARGET_SMALLCODE ) return 5 ; return 20 ; } </s>


<s>
void
XCoreFrameLowering
::
emitEpilogue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
getLastNonDebugInstr
(
)
;
const
XCoreInstrInfo
&
TII
=
*
static_cast
<
const
XCoreInstrInfo
*
>
(
MF
.
getTarget
(
)
.
getInstrInfo
(
)
)
;
DebugLoc
dl
=
MBBI
->
getDebugLoc
(
)
;
bool
FP
=
hasFP
(
MF
)
;
if
(
FP
)
{
unsigned
FramePtr
=
XCore
::
R10
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
XCore
::
SETSP_1r
)
)
.
addReg
(
FramePtr
)
;
}
int
FrameSize
=
MFI
->
getStackSize
(
)
;
assert
(
FrameSize
%
4
==
0
&&
"Misaligned frame size"
)
;
FrameSize
/=
4
;
bool
isU6
=
isImmU6
(
FrameSize
)
;
if
(
!
isU6
&&
!
isImmU16
(
FrameSize
)
)
{
report_fatal_error
(
"emitEpilogue Frame size too big: "
+
Twine
(
FrameSize
)
)
;
}
if
(
FrameSize
)
{
XCoreFunctionInfo
*
XFI
=
MF
.
getInfo
<
XCoreFunctionInfo
>
(
)
;
if
(
FP
)
{
int
FPSpillOffset
=
MFI
->
getObjectOffset
(
XFI
->
getFPSpillSlot
(
)
)
;
FPSpillOffset
+=
FrameSize
*
4
;
loadFromStack
(
MBB
,
MBBI
,
XCore
::
R10
,
FPSpillOffset
,
dl
,
TII
)
;
}
bool
restoreLR
=
XFI
->
getUsesLR
(
)
;
if
(
restoreLR
&&
MFI
->
getObjectOffset
(
XFI
->
getLRSpillSlot
(
)
)
!=
0
)
{
int
LRSpillOffset
=
MFI
->
getObjectOffset
(
XFI
->
getLRSpillSlot
(
)
)
;
LRSpillOffset
+=
FrameSize
*
4
;
loadFromStack
(
MBB
,
MBBI
,
XCore
::
LR
,
LRSpillOffset
,
dl
,
TII
)
;
restoreLR
=
false
;
}
if
(
restoreLR
)
{
assert
(
MBBI
->
getOpcode
(
)
==
XCore
::
RETSP_u6
||
MBBI
->
getOpcode
(
)
==
XCore
::
RETSP_lu6
)
;
int
Opcode
=
(
isU6
)
XCore
::
RETSP_u6
:
XCore
::
RETSP_lu6
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Opcode
)
)
.
addImm
(
FrameSize
)
;
MBB
.
erase
(
MBBI
)
;
}
else
{
int
Opcode
=
(
isU6
)
XCore
::
LDAWSP_ru6_RRegs
:
XCore
::
LDAWSP_lru6_RRegs
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Opcode
)
,
XCore
::
SP
)
.
addImm
(
FrameSize
)
;
}
}
}
</s>


<s> static rtx get_vector_offset ( rtx mem , rtx element , rtx base_tmp , unsigned scalar_size ) { if ( CONST_INT_P ( element ) ) return GEN_INT ( INTVAL ( element ) * scalar_size ) ; gcc_assert ( satisfies_constraint_Q ( mem ) ) ; rtx num_ele_m1 = GEN_INT ( GET_MODE_NUNITS ( GET_MODE ( mem ) ) - 1 ) ; rtx and_op = gen_rtx_AND ( Pmode , element , num_ele_m1 ) ; emit_insn ( gen_rtx_SET ( base_tmp , and_op ) ) ; int shift = exact_log2 ( scalar_size ) ; gcc_assert ( shift >= 0 ) ; if ( shift > 0 ) { rtx shift_op = gen_rtx_ASHIFT ( Pmode , base_tmp , GEN_INT ( shift ) ) ; emit_insn ( gen_rtx_SET ( base_tmp , shift_op ) ) ; } return base_tmp ; } </s>

Return the offset within a memory object ( MEM ) of a vector type to a given element within the vector ( ELEMENT ) with an element size ( SCALAR_SIZE ) . If the element is constant , we return a constant integer . Otherwise , we use a base register temporary to calculate the offset after masking it to fit within the bounds of the vector and scaling it . The masking is required by the 64-bit ELF version 2 ABI for the vec_extract built-in function .


"\t%@ Function supports interworking.\n"

"\t%@ Fast Interrupt Service Routine.\n"

"\t%@ Naked Function: prologue and epilogue provided by programmer.\n"

"\t%@ Volatile: function does not return.\n"

"\t%@ Nested: function declared inside another function.\n"

"\t%@ Stack Align: May be called with mis-aligned SP.\n"

"\t%@ Non-secure entry function: called from non-secure code.\n"

"\t%@ args = %d, pretend = %d, frame = %wd\n"

"\t%@ frame_needed = %d, uses_anonymous_args = %d\n"

Place some comments into the assembler stream describing the current function .


<s> bool isZero ( ) const { return K == ConstZero ; } </s>

Return true if the expression is a constant zero .


<s> bool ix86_expand_fp_vcond ( rtx operands [ ] ) { enum rtx_code code = GET_CODE ( operands [ 3 ] ) ; rtx cmp ; code = ix86_prepare_sse_fp_compare_args ( operands [ 0 ] , code , & operands [ 4 ] , & operands [ 5 ] ) ; if ( code == UNKNOWN ) { rtx temp ; switch ( GET_CODE ( operands [ 3 ] ) ) { case LTGT : temp = ix86_expand_sse_cmp ( operands [ 0 ] , ORDERED , operands [ 4 ] , operands [ 5 ] , operands [ 0 ] , operands [ 0 ] ) ; cmp = ix86_expand_sse_cmp ( operands [ 0 ] , NE , operands [ 4 ] , operands [ 5 ] , operands [ 1 ] , operands [ 2 ] ) ; code = AND ; break ; case UNEQ : temp = ix86_expand_sse_cmp ( operands [ 0 ] , UNORDERED , operands [ 4 ] , operands [ 5 ] , operands [ 0 ] , operands [ 0 ] ) ; cmp = ix86_expand_sse_cmp ( operands [ 0 ] , EQ , operands [ 4 ] , operands [ 5 ] , operands [ 1 ] , operands [ 2 ] ) ; code = IOR ; break ; default : gcc_unreachable ( ) ; } cmp = expand_simple_binop ( GET_MODE ( cmp ) , code , temp , cmp , cmp , 1 , OPTAB_DIRECT ) ; ix86_expand_sse_movcc ( operands [ 0 ] , cmp , operands [ 1 ] , operands [ 2 ] ) ; return true ; } if ( ix86_expand_sse_fp_minmax ( operands [ 0 ] , code , operands [ 4 ] , operands [ 5 ] , operands [ 1 ] , operands [ 2 ] ) ) return true ; cmp = ix86_expand_sse_cmp ( operands [ 0 ] , code , operands [ 4 ] , operands [ 5 ] , operands [ 1 ] , operands [ 2 ] ) ; ix86_expand_sse_movcc ( operands [ 0 ] , cmp , operands [ 1 ] , operands [ 2 ] ) ; return true ; } </s>

Expand a floating-point vector conditional move ; a vcond operation rather than a movcc operation .


<s>
static
void
aarch64_emit_probe_stack_range
(
HOST_WIDE_INT
first
,
poly_int64
poly_size
)
{
HOST_WIDE_INT
size
;
if
(
!
poly_size
.
is_constant
(
&
size
)
)
{
sorry
(
"stack probes for SVE frames"
)
;
return
;
}
rtx
reg1
=
gen_rtx_REG
(
Pmode
,
PROBE_STACK_FIRST_REG
)
;
gcc_assert
(
(
first
%
ARITH_FACTOR
)
==
0
)
;
if
(
size
<=
PROBE_INTERVAL
)
{
const
HOST_WIDE_INT
base
=
ROUND_UP
(
size
,
ARITH_FACTOR
)
;
emit_set_insn
(
reg1
,
plus_constant
(
Pmode
,
stack_pointer_rtx
,
(
first
+
base
)
)
)
;
emit_stack_probe
(
plus_constant
(
Pmode
,
reg1
,
base
size
)
)
;
}
else
if
(
size
<=
4
*
PROBE_INTERVAL
)
{
HOST_WIDE_INT
i
,
rem
;
emit_set_insn
(
reg1
,
plus_constant
(
Pmode
,
stack_pointer_rtx
,
(
first
+
PROBE_INTERVAL
)
)
)
;
emit_stack_probe
(
reg1
)
;
for
(
i
=
2
*
PROBE_INTERVAL
;
i
<
size
;
i
+=
PROBE_INTERVAL
)
{
emit_set_insn
(
reg1
,
plus_constant
(
Pmode
,
reg1
,
PROBE_INTERVAL
)
)
;
emit_stack_probe
(
reg1
)
;
}
rem
=
size
(
i
PROBE_INTERVAL
)
;
if
(
rem
>
256
)
{
const
HOST_WIDE_INT
base
=
ROUND_UP
(
rem
,
ARITH_FACTOR
)
;
emit_set_insn
(
reg1
,
plus_constant
(
Pmode
,
reg1
,
base
)
)
;
emit_stack_probe
(
plus_constant
(
Pmode
,
reg1
,
base
rem
)
)
;
}
else
emit_stack_probe
(
plus_constant
(
Pmode
,
reg1
,
rem
)
)
;
}
else
{
rtx
reg2
=
gen_rtx_REG
(
Pmode
,
PROBE_STACK_SECOND_REG
)
;
HOST_WIDE_INT
rounded_size
=
size
&
PROBE_INTERVAL
;
emit_set_insn
(
reg1
,
plus_constant
(
Pmode
,
stack_pointer_rtx
,
first
)
)
;
HOST_WIDE_INT
adjustment
=
(
first
+
rounded_size
)
;
if
(
!
aarch64_uimm12_shift
(
adjustment
)
)
{
aarch64_internal_mov_immediate
(
reg2
,
GEN_INT
(
adjustment
)
,
true
,
Pmode
)
;
emit_set_insn
(
reg2
,
gen_rtx_PLUS
(
Pmode
,
stack_pointer_rtx
,
reg2
)
)
;
}
else
emit_set_insn
(
reg2
,
plus_constant
(
Pmode
,
stack_pointer_rtx
,
adjustment
)
)
;
emit_insn
(
gen_probe_stack_range
(
reg1
,
reg1
,
reg2
)
)
;
if
(
size
!=
rounded_size
)
{
HOST_WIDE_INT
rem
=
size
rounded_size
;
if
(
rem
>
256
)
{
const
HOST_WIDE_INT
base
=
ROUND_UP
(
rem
,
ARITH_FACTOR
)
;
emit_set_insn
(
reg2
,
plus_constant
(
Pmode
,
reg2
,
base
)
)
;
emit_stack_probe
(
plus_constant
(
Pmode
,
reg2
,
base
rem
)
)
;
}
else
emit_stack_probe
(
plus_constant
(
Pmode
,
reg2
,
rem
)
)
;
}
}
emit_insn
(
gen_blockage
(
)
)
;
}
</s>

Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE , inclusive . These are offsets from the current stack pointer .


<s> unsigned AAPInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : return 0 ; case AAP :: LDB : case AAP :: LDW : case AAP :: LDB_postinc : case AAP :: LDW_postinc : case AAP :: LDB_predec : case AAP :: LDW_predec : break ; } if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> bool AArch64InstrInfo :: isFpOrNEON ( const MachineInstr & MI ) { auto IsFPR = [ & ] ( const MachineOperand & Op ) { if ( ! Op . isReg ( ) ) return false ; auto Reg = Op . getReg ( ) ; if ( Reg . isPhysical ( ) ) return AArch64 :: FPR128RegClass . contains ( Reg ) || AArch64 :: FPR64RegClass . contains ( Reg ) || AArch64 :: FPR32RegClass . contains ( Reg ) || AArch64 :: FPR16RegClass . contains ( Reg ) || AArch64 :: FPR8RegClass . contains ( Reg ) ; const TargetRegisterClass * TRC = :: getRegClass ( MI , Reg ) ; return TRC == & AArch64 :: FPR128RegClass || TRC == & AArch64 :: FPR128_loRegClass || TRC == & AArch64 :: FPR64RegClass || TRC == & AArch64 :: FPR64_loRegClass || TRC == & AArch64 :: FPR32RegClass || TRC == & AArch64 :: FPR16RegClass || TRC == & AArch64 :: FPR8RegClass ; } ; return llvm :: any_of ( MI . operands ( ) , IsFPR ) ; } </s>

Returns whether the instruction is FP or NEON .


<s> bool ix86_use_lea_for_mov ( rtx_insn * insn , rtx operands [ ] ) { unsigned int regno0 , regno1 ; if ( ! TARGET_OPT_AGU || optimize_function_for_size_p ( cfun ) ) return false ; if ( ! REG_P ( operands [ 0 ] ) || ! REG_P ( operands [ 1 ] ) ) return false ; regno0 = true_regnum ( operands [ 0 ] ) ; regno1 = true_regnum ( operands [ 1 ] ) ; return ix86_lea_outperforms ( insn , regno0 , regno1 , INVALID_REGNUM , 0 , false ) ; } </s>

Return true if we should emit lea instruction instead of mov instruction .


"Too many temporary registers allocated\n"

Return a register which will be loaded with a value if an IF block is converted to conditional execution . This is used to rewrite instructions that use constants to ones that just use registers .


<s>
bool
SIInstrInfo
::
isInlineConstant
(
const
MachineOperand
&
MO
,
uint8_t
OperandType
)
const
{
if
(
!
MO
.
isImm
(
)
||
OperandType
<
AMDGPU
::
OPERAND_SRC_FIRST
||
OperandType
>
AMDGPU
::
OPERAND_SRC_LAST
)
return
false
;
int64_t
Imm
=
MO
.
getImm
(
)
;
switch
(
OperandType
)
{
case
AMDGPU
::
OPERAND_REG_IMM_INT32
:
case
AMDGPU
::
OPERAND_REG_IMM_FP32
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_INT32
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_FP32
:
{
int32_t
Trunc
=
static_cast
<
int32_t
>
(
Imm
)
;
return
Trunc
==
Imm
&&
AMDGPU
::
isInlinableLiteral32
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
case
AMDGPU
::
OPERAND_REG_IMM_INT64
:
case
AMDGPU
::
OPERAND_REG_IMM_FP64
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_INT64
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_FP64
:
return
AMDGPU
::
isInlinableLiteral64
(
MO
.
getImm
(
)
,
ST
.
hasInv2PiInlineImm
(
)
)
;
case
AMDGPU
::
OPERAND_REG_IMM_INT16
:
case
AMDGPU
::
OPERAND_REG_IMM_FP16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_INT16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_FP16
:
{
if
(
isInt
<
16
>
(
Imm
)
||
isUInt
<
16
>
(
Imm
)
)
{
int16_t
Trunc
=
static_cast
<
int16_t
>
(
Imm
)
;
return
ST
.
has16BitInsts
(
)
&&
AMDGPU
::
isInlinableLiteral16
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
return
false
;
}
case
AMDGPU
::
OPERAND_REG_INLINE_C_V2INT16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_V2FP16
:
{
uint32_t
Trunc
=
static_cast
<
uint32_t
>
(
Imm
)
;
return
AMDGPU
::
isInlinableLiteralV216
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
default
:
llvm_unreachable
(
"invalid bitwidth"
)
;
}
}
</s>

returns true if the operand OpIdx in MI is a valid inline immediate .