"\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n"

Internal function to add a potential insn to the list of insns to be inserted if the conditional execution conversion is successful .


<s> unsigned X86TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i1 && Subtarget . hasAVX512 ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; MVT RegisterVT ; unsigned NumRegisters ; std :: tie ( RegisterVT , NumRegisters ) = handleMaskRegisterForCallingConv ( NumElts , CC , Subtarget ) ; if ( RegisterVT != MVT :: INVALID_SIMPLE_VALUE_TYPE ) return NumRegisters ; } if ( VT == MVT :: v3f16 && Subtarget . hasFP16 ( ) ) return 1 ; return TargetLowering :: getNumRegistersForCallingConv ( Context , CC , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s> enum rtx_code xtensa_shlrd_which_direction ( rtx op0 , rtx op1 ) { if ( GET_CODE ( op0 ) == ASHIFT && GET_CODE ( op1 ) == LSHIFTRT ) return ASHIFT ; if ( GET_CODE ( op0 ) == LSHIFTRT && GET_CODE ( op1 ) == ASHIFT ) return LSHIFTRT ; return UNKNOWN ; } </s>

Helper function for `` * shlrd_ ... '' patterns .


"Load and store instructions have exactly one mem operand"

"Default p2align value should be natural"

"Load and store instructions should have a p2align operand"

runOnMachineFunction - Emit the function body .


<s> TargetLowering :: ConstraintType HexagonTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'q' : case 'v' : if ( Subtarget . useHVXOps ( ) ) return C_Register ; break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> int floating_exact_log2 ( rtx x ) { REAL_VALUE_TYPE r , r1 ; int exp ; REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; if ( REAL_VALUES_LESS ( r , dconst1 ) ) return 0 ; exp = real_exponent ( & r ) ; real_2expN ( & r1 , exp , DFmode ) ; if ( REAL_VALUES_EQUAL ( r1 , r ) ) return exp ; return 0 ; } </s>

If X is a floating-point constant , return the logarithm of X base 2 , or 0 if X is not a power of 2 .


<s>
void
BT
::
run
(
)
{
reset
(
)
;
assert
(
FlowQ
.
empty
(
)
)
;
typedef
GraphTraits
<
const
MachineFunction
*
>
MachineFlowGraphTraits
;
const
MachineBasicBlock
*
Entry
=
MachineFlowGraphTraits
::
getEntryNode
(
&
MF
)
;
unsigned
MaxBN
=
0
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
assert
(
I
->
getNumber
(
)
>=
0
&&
"Disconnected block"
)
;
unsigned
BN
=
I
->
getNumber
(
)
;
if
(
BN
>
MaxBN
)
MaxBN
=
BN
;
}
BitVector
BlockScanned
(
MaxBN
+
1
)
;
int
EntryN
=
Entry
->
getNumber
(
)
;
FlowQ
.
push
(
CFGEdge
(
1
,
EntryN
)
)
;
while
(
!
FlowQ
.
empty
(
)
)
{
CFGEdge
Edge
=
FlowQ
.
front
(
)
;
FlowQ
.
pop
(
)
;
if
(
EdgeExec
.
count
(
Edge
)
)
continue
;
EdgeExec
.
insert
(
Edge
)
;
const
MachineBasicBlock
&
B
=
*
MF
.
getBlockNumbered
(
Edge
.
second
)
;
MachineBasicBlock
::
const_iterator
It
=
B
.
begin
(
)
,
End
=
B
.
end
(
)
;
while
(
It
!=
End
&&
It
->
isPHI
(
)
)
{
const
MachineInstr
&
PI
=
*
It
++
;
InstrExec
.
insert
(
&
PI
)
;
visitPHI
(
PI
)
;
}
if
(
BlockScanned
[
Edge
.
second
]
)
continue
;
BlockScanned
[
Edge
.
second
]
=
true
;
while
(
It
!=
End
&&
!
It
->
isBranch
(
)
)
{
const
MachineInstr
&
MI
=
*
It
++
;
InstrExec
.
insert
(
&
MI
)
;
visitNonBranch
(
MI
)
;
}
if
(
It
==
End
)
{
MachineFunction
::
const_iterator
BIt
=
B
.
getIterator
(
)
;
MachineFunction
::
const_iterator
Next
=
std
::
next
(
BIt
)
;
if
(
Next
!=
MF
.
end
(
)
&&
B
.
isSuccessor
(
&
*
Next
)
)
{
int
ThisN
=
B
.
getNumber
(
)
;
int
NextN
=
Next
->
getNumber
(
)
;
FlowQ
.
push
(
CFGEdge
(
ThisN
,
NextN
)
)
;
}
}
else
{
visitBranchesFrom
(
*
It
)
;
}
}
if
(
Trace
)
{
dbgs
(
)
<<
"Cells after propagation:\n"
;
for
(
CellMapType
::
iterator
I
=
Map
.
begin
(
)
,
E
=
Map
.
end
(
)
;
I
!=
E
;
++
I
)
dbgs
(
)
<<
PrintReg
(
I
->
first
,
&
ME
.
TRI
)
<<
" -> "
<<
I
->
second
<<
"\n"
;
}
}
</s>

Run the analysis pass over a function and produce a dominator tree .


<s> static void loongarch_print_operand_address ( FILE * file , machine_mode , rtx x ) { struct loongarch_address_info addr ; if ( loongarch_classify_address ( & addr , x , word_mode , true ) ) switch ( addr . type ) { case ADDRESS_REG : fprintf ( file , "%s," , reg_names [ REGNO ( addr . reg ) ] ) ; loongarch_print_operand ( file , addr . offset , 0 ) ; return ; case ADDRESS_REG_REG : fprintf ( file , "%s,%s" , reg_names [ REGNO ( addr . reg ) ] , reg_names [ REGNO ( addr . offset ) ] ) ; return ; case ADDRESS_LO_SUM : fprintf ( file , "%s," , reg_names [ REGNO ( addr . reg ) ] ) ; loongarch_print_operand_reloc ( file , addr . offset , false , false ) ; return ; case ADDRESS_CONST_INT : fprintf ( file , "%s," , reg_names [ GP_REG_FIRST ] ) ; output_addr_const ( file , x ) ; return ; case ADDRESS_SYMBOLIC : output_addr_const ( file , loongarch_strip_unspec_address ( x ) ) ; return ; } if ( CONST_INT_P ( x ) ) output_addr_const ( file , x ) ; else gcc_unreachable ( ) ; } </s>


<s> static rtx mmix_struct_value_rtx ( tree fntype ATTRIBUTE_UNUSED , int incoming ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( Pmode , MMIX_STRUCT_VALUE_REGNUM ) ; } </s>

Worker function for TARGET_STRUCT_VALUE_RTX .


<s> static bool sh_return_in_memory ( const_tree type , const_tree fndecl ) { return TYPE_MODE ( type ) == BLKmode || ( ( TARGET_HITACHI || sh_attr_renesas_p ( fndecl ) ) && TREE_CODE ( type ) == RECORD_TYPE ) ; } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> const char * AVRTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { case AVRISD :: name : \ return # name switch ( Opcode ) { default : return nullptr ; NODE ( RET_FLAG ) ; NODE ( RETI_FLAG ) ; NODE ( CALL ) ; NODE ( WRAPPER ) ; NODE ( LSL ) ; NODE ( LSR ) ; NODE ( ROL ) ; NODE ( ROR ) ; NODE ( ASR ) ; NODE ( LSLLOOP ) ; NODE ( LSRLOOP ) ; NODE ( ROLLOOP ) ; NODE ( RORLOOP ) ; NODE ( ASRLOOP ) ; NODE ( BRCOND ) ; NODE ( CMP ) ; NODE ( CMPC ) ; NODE ( TST ) ; NODE ( SELECT_CC ) ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> const RegisterBankInfo :: InstructionMapping & X86RegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto Opc = MI . getOpcode ( ) ; if ( ! isPreISelGenericOpcode ( Opc ) || Opc == TargetOpcode :: G_PHI ) { const InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; } switch ( Opc ) { case TargetOpcode :: G_ADD : case TargetOpcode :: G_SUB : case TargetOpcode :: G_MUL : case TargetOpcode :: G_SHL : case TargetOpcode :: G_LSHR : case TargetOpcode :: G_ASHR : return getSameOperandsMapping ( MI , false ) ; break ; case TargetOpcode :: G_FADD : case TargetOpcode :: G_FSUB : case TargetOpcode :: G_FMUL : case TargetOpcode :: G_FDIV : return getSameOperandsMapping ( MI , true ) ; break ; default : break ; } unsigned NumOperands = MI . getNumOperands ( ) ; SmallVector < PartialMappingIdx , 4 > OpRegBankIdx ( NumOperands ) ; switch ( Opc ) { case TargetOpcode :: G_FPEXT : case TargetOpcode :: G_FCONSTANT : getInstrPartialMappingIdxs ( MI , MRI , true , OpRegBankIdx ) ; break ; case TargetOpcode :: G_TRUNC : case TargetOpcode :: G_ANYEXT : { auto & Op0 = MI . getOperand ( 0 ) ; auto & Op1 = MI . getOperand ( 1 ) ; const LLT Ty0 = MRI . getType ( Op0 . getReg ( ) ) ; const LLT Ty1 = MRI . getType ( Op1 . getReg ( ) ) ; bool isFPTrunc = ( Ty0 . getSizeInBits ( ) == 32 || Ty0 . getSizeInBits ( ) == 64 ) && Ty1 . getSizeInBits ( ) == 128 && Opc == TargetOpcode :: G_TRUNC ; bool isFPAnyExt = Ty0 . getSizeInBits ( ) == 128 && ( Ty1 . getSizeInBits ( ) == 32 || Ty1 . getSizeInBits ( ) == 64 ) && Opc == TargetOpcode :: G_ANYEXT ; getInstrPartialMappingIdxs ( MI , MRI , isFPTrunc || isFPAnyExt , OpRegBankIdx ) ; } break ; default : getInstrPartialMappingIdxs ( MI , MRI , false , OpRegBankIdx ) ; break ; } SmallVector < const ValueMapping * , 8 > OpdsMapping ( NumOperands ) ; if ( ! getInstrValueMapping ( MI , OpRegBankIdx , OpdsMapping ) ) return getInvalidInstructionMapping ( ) ; return getInstructionMapping ( DefaultMappingID , 1 , getOperandsMapping ( OpdsMapping ) , NumOperands ) ; } </s>

Get the mapping of the different operands of MI on the register bank .


<s> bool TGSITTIImpl :: isSourceOfDivergence ( const Value * V ) { if ( const Argument * Arg = dyn_cast < Argument > ( V ) ) return ! isKernelFunction ( Arg -> getParent ( ) ) ; if ( const Instruction * I = dyn_cast < Instruction > ( V ) ) { if ( const LoadInst * LI = dyn_cast < LoadInst > ( I ) ) { unsigned AS = LI -> getPointerAddressSpace ( ) ; return AS == tgsi :: PRIVATE || AS == tgsi :: LOCAL ; } if ( I -> isAtomic ( ) ) return true ; if ( const IntrinsicInst * II = dyn_cast < IntrinsicInst > ( I ) ) { switch ( II -> getIntrinsicID ( ) ) { case Intrinsic :: tgsi_read_blockid_x : case Intrinsic :: tgsi_read_blockid_y : case Intrinsic :: tgsi_read_blockid_z : case Intrinsic :: tgsi_read_threadid_x : case Intrinsic :: tgsi_read_threadid_y : case Intrinsic :: tgsi_read_threadid_z : return true ; default : return false ; } } if ( isa < CallInst > ( V ) || isa < InvokeInst > ( V ) ) return true ; } return false ; } </s>

Returns whether V is a source of divergence .


<s> StackOffset NVPTXFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; FrameReg = NVPTX :: VRDepot ; return StackOffset :: getFixed ( MFI . getObjectOffset ( FI ) - getOffsetOfLocalArea ( ) ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> static int cbranch_predicted_taken_p ( rtx insn ) { rtx x = find_reg_note ( insn , REG_BR_PROB , 0 ) ; if ( x ) { return profile_probability :: from_reg_br_prob_note ( XINT ( x , 0 ) ) >= profile_probability :: even ( ) ; } return 0 ; } </s>

Return nonzero if INSN is annotated with a REG_BR_PROB note that indicates it 's a branch that 's predicted taken .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


"\nEntering Lazy VSETVL PASS and Handling %d basic blocks for "

"\nPhase 1: Compute local backward vector infos\n"

"\nPhase 2: Emit vsetvl instruction within each block\n"

"\nPhase 3: Demands propagation across blocks\n"

"\nPhase 4: PRE vsetvl by Lazy code motion (LCM)\n"

"\nPhase 5: Cleanup AVL and VL operands\n"

"\nPhase 6: Rebuild RTL_SSA to propagate AVL between vsetvls\n"

Lazy vsetvl insertion for optimize > 0 .


<s> static rtx find_addr_reg ( rtx addr ) { while ( GET_CODE ( addr ) == PLUS ) { if ( GET_CODE ( XEXP ( addr , 0 ) ) == REG ) addr = XEXP ( addr , 0 ) ; else if ( GET_CODE ( XEXP ( addr , 1 ) ) == REG ) addr = XEXP ( addr , 1 ) ; else if ( CONSTANT_P ( XEXP ( addr , 0 ) ) ) addr = XEXP ( addr , 1 ) ; else if ( CONSTANT_P ( XEXP ( addr , 1 ) ) ) addr = XEXP ( addr , 0 ) ; else gcc_unreachable ( ) ; } gcc_assert ( GET_CODE ( addr ) == REG ) ; return addr ; } </s>

Return a REG that occurs in ADDR with coefficient 1 . ADDR can be effectively incremented by incrementing REG . r0 is special and we must not select it as an address register by this routine since our caller will try to increment the returned register via an `` la '' instruction .


<s> static bool have_compare_and_set_mask ( machine_mode mode ) { switch ( mode ) { case E_SFmode : case E_DFmode : return TARGET_P9_MINMAX ; default : break ; } return false ; } </s>

Helper function to return true if the target has instructions to do a compare and set mask instruction that can be used with XXSEL to implement a conditional move . It is also assumed that such a target also supports the `` C '' minimum and maximum instructions .


<s> static bool aarch64_legitimate_address_hook_p ( machine_mode mode , rtx x , bool strict_p ) { struct aarch64_address_info addr ; return aarch64_classify_address ( & addr , x , mode , MEM , strict_p ) ; } </s>

Return TRUE if X is a legitimate address for accessing memory in mode MODE .


<s> bool AZPRAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { const MachineOperand & MO = MI -> getOperand ( OpNum ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : O << '$' << StringRef ( AZPRInstPrinter :: getRegisterName ( MO . getReg ( ) ) ) . lower ( ) ; return false ; } return true ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> void addOptimizedRegAlloc ( ) override { addPass ( createTPCExpandHWRegCopies ( ) ) ; TargetPassConfig :: addOptimizedRegAlloc ( ) ; } </s>

addOptimizedRegAlloc - Add passes related to register allocation .


<s> bool frv_const_unspec_p ( rtx x , struct frv_unspec * unspec ) { if ( GET_CODE ( x ) == CONST ) { unspec -> offset = 0 ; x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) { unspec -> offset += INTVAL ( XEXP ( x , 1 ) ) ; x = XEXP ( x , 0 ) ; } if ( GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNSPEC_GOT ) { unspec -> symbol = XVECEXP ( x , 0 , 0 ) ; unspec -> reloc = INTVAL ( XVECEXP ( x , 0 , 1 ) ) ; if ( unspec -> offset == 0 ) return true ; if ( frv_small_data_reloc_p ( unspec -> symbol , unspec -> reloc ) && unspec -> offset > 0 && unspec -> offset < g_switch_value ) return true ; } } return false ; } </s>

Return true if X is a valid relocation unspec . If it is , fill in UNSPEC appropriately .


<s> static void alpha_canonicalize_comparison ( int * code , rtx * op0 , rtx * op1 , bool op0_preserve_value ) { if ( ! op0_preserve_value && ( * code == GE || * code == GT || * code == GEU || * code == GTU ) && ( REG_P ( * op1 ) || * op1 == const0_rtx ) ) { rtx tem = * op0 ; * op0 = * op1 ; * op1 = tem ; * code = ( int ) swap_condition ( ( enum rtx_code ) * code ) ; } if ( ( * code == LT || * code == LTU ) && CONST_INT_P ( * op1 ) && INTVAL ( * op1 ) == 256 ) { * code = * code == LT ? LE : LEU ; * op1 = GEN_INT ( 255 ) ; } } </s>

Canonicalize a comparison from one we do n't have to one we do have .


"\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "

"type = %d, ind_levels = %d, win = %d, original addr:\n"

Debug version of rs6000_legitimize_reload_address .


<s> bool runOnModule ( Module & M ) override { SetVector < Function * > Functions ; AnalysisGetter AG ; for ( Function & F : M ) { if ( ! F . isIntrinsic ( ) ) Functions . insert ( & F ) ; } CallGraphUpdater CGUpdater ; BumpPtrAllocator Allocator ; AMDGPUInformationCache InfoCache ( M , AG , Allocator , nullptr , * TM ) ; DenseSet < const char * > Allowed ( { & AAAMDAttributes :: ID , & AAUniformWorkGroupSize :: ID , & AAAMDFlatWorkGroupSize :: ID , & AACallEdges :: ID } ) ; Attributor A ( Functions , InfoCache , CGUpdater , & Allowed ) ; for ( Function & F : M ) { if ( ! F . isIntrinsic ( ) ) { A . getOrCreateAAFor < AAAMDAttributes > ( IRPosition :: function ( F ) ) ; A . getOrCreateAAFor < AAUniformWorkGroupSize > ( IRPosition :: function ( F ) ) ; if ( ! AMDGPU :: isEntryFunctionCC ( F . getCallingConv ( ) ) ) { A . getOrCreateAAFor < AAAMDFlatWorkGroupSize > ( IRPosition :: function ( F ) ) ; } } } ChangeStatus Change = A . run ( ) ; return Change == ChangeStatus :: CHANGED ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> bool ix86_use_pseudo_pic_reg ( void ) { if ( ( TARGET_64BIT && ( ix86_cmodel == CM_SMALL_PIC || TARGET_PECOFF ) ) || ! flag_pic ) return false ; return true ; } </s>

Return 1 if pseudo register should be created and used to hold GOT address for PIC code .


<s> rtx ix86_libcall_value ( enum machine_mode mode ) { if ( TARGET_64BIT ) { switch ( mode ) { case SFmode : case SCmode : case DFmode : case DCmode : case TFmode : return gen_rtx_REG ( mode , FIRST_SSE_REG ) ; case XFmode : case XCmode : return gen_rtx_REG ( mode , FIRST_FLOAT_REG ) ; case TCmode : return NULL ; default : return gen_rtx_REG ( mode , 0 ) ; } } else return gen_rtx_REG ( mode , ix86_value_regno ( mode , NULL , NULL ) ) ; } </s>

Define how to find the value returned by a library function assuming the value has mode MODE .


<s> ScheduleHazardRecognizer :: HazardType GCNHazardRecognizer :: getHazardType ( SUnit * SU , int Stalls ) { MachineInstr * MI = SU -> getInstr ( ) ; if ( MI -> isBundle ( ) ) return NoHazard ; if ( SIInstrInfo :: isSMRD ( * MI ) && checkSMRDHazards ( MI ) > 0 ) return NoopHazard ; if ( ( SIInstrInfo :: isVMEM ( * MI ) || SIInstrInfo :: isFLAT ( * MI ) ) && checkVMEMHazards ( MI ) > 0 ) return NoopHazard ; if ( ST . hasNSAtoVMEMBug ( ) && checkNSAtoVMEMHazard ( MI ) > 0 ) return NoopHazard ; if ( checkFPAtomicToDenormModeHazard ( MI ) > 0 ) return NoopHazard ; if ( ST . hasNoDataDepHazard ( ) ) return NoHazard ; if ( SIInstrInfo :: isVALU ( * MI ) && checkVALUHazards ( MI ) > 0 ) return NoopHazard ; if ( SIInstrInfo :: isDPP ( * MI ) && checkDPPHazards ( MI ) > 0 ) return NoopHazard ; if ( isDivFMas ( MI -> getOpcode ( ) ) && checkDivFMasHazards ( MI ) > 0 ) return NoopHazard ; if ( isRWLane ( MI -> getOpcode ( ) ) && checkRWLaneHazards ( MI ) > 0 ) return NoopHazard ; if ( isSGetReg ( MI -> getOpcode ( ) ) && checkGetRegHazards ( MI ) > 0 ) return NoopHazard ; if ( isSSetReg ( MI -> getOpcode ( ) ) && checkSetRegHazards ( MI ) > 0 ) return NoopHazard ; if ( isRFE ( MI -> getOpcode ( ) ) && checkRFEHazards ( MI ) > 0 ) return NoopHazard ; if ( ST . hasReadM0MovRelInterpHazard ( ) && ( TII . isVINTRP ( * MI ) || isSMovRel ( MI -> getOpcode ( ) ) ) && checkReadM0Hazards ( MI ) > 0 ) return NoopHazard ; if ( ST . hasReadM0SendMsgHazard ( ) && isSendMsgTraceDataOrGDS ( TII , * MI ) && checkReadM0Hazards ( MI ) > 0 ) return NoopHazard ; if ( MI -> isInlineAsm ( ) && checkInlineAsmHazards ( MI ) > 0 ) return NoopHazard ; if ( checkAnyInstHazards ( MI ) > 0 ) return NoopHazard ; return NoHazard ; } </s>

getHazardType - Return the hazard type of emitting this node .


<s> bool isValid ( unsigned Val ) const { return Val <= Max ; } </s>

Returns true if this iterator is still pointing at a valid entry .


<s> bool Comet2PassConfig :: addInstSelector ( ) { addPass ( createComet2ISelDag ( getComet2TargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static void mmix_target_asm_function_epilogue ( FILE * stream , HOST_WIDE_INT locals_size ATTRIBUTE_UNUSED ) { fputc ( '\n' , stream ) ; } </s>


"JIT relocation model must be set to static or default!"

runOnMachineFunction - Emit the function body .


<s> bool llvm :: getAlign ( const CallInst & I , unsigned index , unsigned & align ) { if ( MDNode * alignNode = I . getMetadata ( "callalign" ) ) { for ( int i = 0 , n = alignNode -> getNumOperands ( ) ; i < n ; i ++ ) { if ( const ConstantInt * CI = mdconst :: dyn_extract < ConstantInt > ( alignNode -> getOperand ( i ) ) ) { unsigned v = CI -> getZExtValue ( ) ; if ( ( v >> 16 ) == index ) { align = v & 0xFFFF ; return true ; } if ( ( v >> 16 ) > index ) { return false ; } } } } return false ; } </s>

Return the minimum known alignment in bytes of the actual memory reference .


<s> static bool darwin_local_data_pic ( rtx disp ) { return ( GET_CODE ( disp ) == UNSPEC && XINT ( disp , 1 ) == UNSPEC_MACHOPIC_OFFSET ) ; } </s>

Allow { LABEL | SYMBOL } _REF - SYMBOL_REF-FOR-PICBASE for Mach-O as this is used for to form addresses to local data when -fPIC is in use .


<s> const unsigned * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { bool ghcCall = false ; if ( MF ) { const Function * F = MF -> getFunction ( ) ; ghcCall = ( F ? F -> getCallingConv ( ) == CallingConv :: GHC : false ) ; } static const unsigned CalleeSavedRegs [ ] = { ARM :: LR , ARM :: R11 , ARM :: R10 , ARM :: R9 , ARM :: R8 , ARM :: R7 , ARM :: R6 , ARM :: R5 , ARM :: R4 , ARM :: D15 , ARM :: D14 , ARM :: D13 , ARM :: D12 , ARM :: D11 , ARM :: D10 , ARM :: D9 , ARM :: D8 , 0 } ; static const unsigned DarwinCalleeSavedRegs [ ] = { ARM :: LR , ARM :: R7 , ARM :: R6 , ARM :: R5 , ARM :: R4 , ARM :: R11 , ARM :: R10 , ARM :: R8 , ARM :: D15 , ARM :: D14 , ARM :: D13 , ARM :: D12 , ARM :: D11 , ARM :: D10 , ARM :: D9 , ARM :: D8 , 0 } ; static const unsigned GhcCalleeSavedRegs [ ] = { 0 } ; return ghcCall ? GhcCalleeSavedRegs : STI . isTargetDarwin ( ) ? DarwinCalleeSavedRegs : CalleeSavedRegs ; } </s>


<s> static void ix86_expand_ashl_const ( rtx operand , int count , machine_mode mode ) { if ( count == 1 || ( count * ix86_cost -> add <= ix86_cost -> shift_const && ! optimize_insn_for_size_p ( ) ) ) { while ( count -- > 0 ) emit_insn ( gen_add2_insn ( operand , operand ) ) ; } else { rtx ( * insn ) ( rtx , rtx , rtx ) ; insn = mode == DImode ? gen_ashlsi3 : gen_ashldi3 ; emit_insn ( insn ( operand , operand , GEN_INT ( count ) ) ) ; } } </s>

Helper function of ix86_split_ashl used to generate an SImode/DImode left shift by a constant , either using a single shift or a sequence of add instructions .


<s> void RISCVInstrInfo :: loadImmediate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned * Reg , int64_t Value ) const { DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned Opcode ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = STI . isRV64 ( ) ? & RISCV :: GR64BitRegClass : & RISCV :: GR32BitRegClass ; unsigned ZERO = STI . isRV64 ( ) ? RISCV :: zero_64 : RISCV :: zero ; * Reg = RegInfo . createVirtualRegister ( RC ) ; if ( isInt < 12 > ( Value ) ) { Opcode = STI . isRV64 ( ) ? RISCV :: ADDI64 : RISCV :: ADDI ; BuildMI ( MBB , MBBI , DL , get ( Opcode ) , * Reg ) . addReg ( ZERO ) . addImm ( Value ) ; } else { BuildMI ( MBB , MBBI , DL , get ( RISCV :: LI ) , * Reg ) . addImm ( Value ) ; } } </s>

Emit a series of instructions to load an immediate .


<s>
rtx_code
m68k_output_bftst
(
rtx
zxop0
,
rtx
zxop1
,
rtx
zxop2
,
rtx_code
code
)
{
if
(
zxop1
==
const1_rtx
&&
GET_CODE
(
zxop2
)
==
CONST_INT
)
{
int
width
=
GET_CODE
(
zxop0
)
==
REG
31
:
7
;
return
m68k_output_btst
(
GEN_INT
(
width
INTVAL
(
zxop2
)
)
,
zxop0
,
code
,
1000
)
;
}
rtx
ops
[
3
]
=
{
zxop0
,
zxop1
,
zxop2
}
;
output_asm_insn
(
"bftst %0{%b2:%b1}"
,
ops
)
;
return
code
;
}
</s>

Output a bftst instruction for a zero_extract with ZXOP0 , ZXOP1 and ZXOP2 operands . CODE is the code of the comparison , and we return the code to be actually used in the jump .


<s> void HexagonMCShuffler :: init ( MCInst & MCB , MCInst const & AddMI , bool bInsertAtFront ) { if ( HexagonMCInstrInfo :: isBundle ( MCB ) ) { if ( bInsertAtFront ) append ( AddMI , nullptr , HexagonMCInstrInfo :: getUnits ( MCII , STI , AddMI ) ) ; MCInst const * Extender = nullptr ; for ( auto const & I : HexagonMCInstrInfo :: bundleInstructions ( MCB ) ) { assert ( ! HexagonMCInstrInfo :: getDesc ( MCII , * I . getInst ( ) ) . isPseudo ( ) ) ; MCInst & MI = * const_cast < MCInst * > ( I . getInst ( ) ) ; if ( ! HexagonMCInstrInfo :: isImmext ( MI ) ) { append ( MI , Extender , HexagonMCInstrInfo :: getUnits ( MCII , STI , MI ) ) ; Extender = nullptr ; } else Extender = & MI ; } if ( ! bInsertAtFront ) append ( AddMI , nullptr , HexagonMCInstrInfo :: getUnits ( MCII , STI , AddMI ) ) ; } Loc = MCB . getLoc ( ) ; BundleFlags = MCB . getOperand ( 0 ) . getImm ( ) ; } </s>

Initialize the machine model for instruction scheduling .

Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon 0


<s> bool AMDGPUTargetLowering :: isZExtFree ( SDValue Val , EVT VT2 ) const { return isZExtFree ( Val . getValueType ( ) , VT2 ) ; } </s>

Return true if zero-extending the specific node Val to type VT2 is free ( either because it 's implicitly zero-extended such as ARM ldrb / ldrh or because it 's folded such as X86 zero-extending loads ) .


<s> virtual const PPCSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool Thumb1InstrInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( CSI . empty ( ) ) return false ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > 0 ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( ARM :: tPOP ) ) ; AddDefaultPred ( MIB ) ; bool NumRegs = false ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( Reg == ARM :: LR ) { if ( isVarArg ) continue ; Reg = ARM :: PC ; ( * MIB ) . setDesc ( get ( ARM :: tPOP_RET ) ) ; MI = MBB . erase ( MI ) ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; NumRegs = true ; } if ( NumRegs ) MBB . insert ( MI , & * MIB ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> void ia64_expand_compare ( rtx * expr , rtx * op0 , rtx * op1 ) { enum rtx_code code = GET_CODE ( * expr ) ; rtx cmp ; if ( GET_MODE ( * op0 ) == BImode ) { gcc_assert ( ( code == NE || code == EQ ) && * op1 == const0_rtx ) ; cmp = * op0 ; } else if ( TARGET_HPUX && GET_MODE ( * op0 ) == TFmode ) { enum qfcmp_magic { QCMP_INV = 1 , QCMP_UNORD = 2 , QCMP_EQ = 4 , QCMP_LT = 8 , QCMP_GT = 16 } ; int magic ; enum rtx_code ncode ; rtx ret , insns ; gcc_assert ( cmptf_libfunc && GET_MODE ( * op1 ) == TFmode ) ; switch ( code ) { case EQ : magic = QCMP_EQ ; ncode = NE ; break ; case NE : magic = QCMP_EQ ; ncode = EQ ; break ; case UNORDERED : magic = QCMP_UNORD ; ncode = NE ; break ; case ORDERED : magic = QCMP_UNORD ; ncode = EQ ; break ; case LT : magic = QCMP_LT | QCMP_INV ; ncode = NE ; break ; case LE : magic = QCMP_LT | QCMP_EQ | QCMP_INV ; ncode = NE ; break ; case GT : magic = QCMP_GT | QCMP_INV ; ncode = NE ; break ; case GE : magic = QCMP_GT | QCMP_EQ | QCMP_INV ; ncode = NE ; break ; case UNLT : magic = QCMP_LT | QCMP_UNORD ; ncode = NE ; break ; case UNLE : magic = QCMP_LT | QCMP_EQ | QCMP_UNORD ; ncode = NE ; break ; case UNGT : magic = QCMP_GT | QCMP_UNORD ; ncode = NE ; break ; case UNGE : magic = QCMP_GT | QCMP_EQ | QCMP_UNORD ; ncode = NE ; break ; case UNEQ : case LTGT : default : gcc_unreachable ( ) ; } start_sequence ( ) ; ret = emit_library_call_value ( cmptf_libfunc , 0 , LCT_CONST , DImode , 3 , * op0 , TFmode , * op1 , TFmode , GEN_INT ( magic ) , DImode ) ; cmp = gen_reg_rtx ( BImode ) ; emit_insn ( gen_rtx_SET ( cmp , gen_rtx_fmt_ee ( ncode , BImode , ret , const0_rtx ) ) ) ; insns = get_insns ( ) ; end_sequence ( ) ; emit_libcall_block ( insns , cmp , cmp , gen_rtx_fmt_ee ( code , BImode , * op0 , * op1 ) ) ; code = NE ; } else { cmp = gen_reg_rtx ( BImode ) ; emit_insn ( gen_rtx_SET ( cmp , gen_rtx_fmt_ee ( code , BImode , * op0 , * op1 ) ) ) ; code = NE ; } * expr = gen_rtx_fmt_ee ( code , VOIDmode , cmp , const0_rtx ) ; * op0 = cmp ; * op1 = const0_rtx ; } </s>

Emit comparison instruction if necessary , returning the expression that holds the compare result in the proper mode .


<s> HOST_WIDE_INT rs6000_builtin_mask_calculate ( void ) { return ( ( ( TARGET_ALTIVEC ) ? RS6000_BTM_ALTIVEC : 0 ) | ( ( TARGET_CMPB ) ? RS6000_BTM_CMPB : 0 ) | ( ( TARGET_VSX ) ? RS6000_BTM_VSX : 0 ) | ( ( TARGET_PAIRED_FLOAT ) ? RS6000_BTM_PAIRED : 0 ) | ( ( TARGET_FRE ) ? RS6000_BTM_FRE : 0 ) | ( ( TARGET_FRES ) ? RS6000_BTM_FRES : 0 ) | ( ( TARGET_FRSQRTE ) ? RS6000_BTM_FRSQRTE : 0 ) | ( ( TARGET_FRSQRTES ) ? RS6000_BTM_FRSQRTES : 0 ) | ( ( TARGET_POPCNTD ) ? RS6000_BTM_POPCNTD : 0 ) | ( ( rs6000_cpu == PROCESSOR_CELL ) ? RS6000_BTM_CELL : 0 ) | ( ( TARGET_P8_VECTOR ) ? RS6000_BTM_P8_VECTOR : 0 ) | ( ( TARGET_P9_VECTOR ) ? RS6000_BTM_P9_VECTOR : 0 ) | ( ( TARGET_P9_MISC ) ? RS6000_BTM_P9_MISC : 0 ) | ( ( TARGET_MODULO ) ? RS6000_BTM_MODULO : 0 ) | ( ( TARGET_64BIT ) ? RS6000_BTM_64BIT : 0 ) | ( ( TARGET_POWERPC64 ) ? RS6000_BTM_POWERPC64 : 0 ) | ( ( TARGET_CRYPTO ) ? RS6000_BTM_CRYPTO : 0 ) | ( ( TARGET_HTM ) ? RS6000_BTM_HTM : 0 ) | ( ( TARGET_DFP ) ? RS6000_BTM_DFP : 0 ) | ( ( TARGET_HARD_FLOAT ) ? RS6000_BTM_HARD_FLOAT : 0 ) | ( ( TARGET_LONG_DOUBLE_128 ) ? RS6000_BTM_LDBL128 : 0 ) | ( ( TARGET_FLOAT128_TYPE ) ? RS6000_BTM_FLOAT128 : 0 ) | ( ( TARGET_FLOAT128_HW ) ? RS6000_BTM_FLOAT128_HW : 0 ) ) ; } </s>

Return the builtin mask of the various options used that could affect which builtins were used . In the past we used target_flags , but we 've run out of bits , and some options like PAIRED are no longer in target_flags .


<s> rtx m32c_eh_return_stackadj_rtx ( void ) { if ( ! cfun -> machine -> eh_stack_adjust ) { rtx sa ; sa = gen_reg_rtx ( Pmode ) ; cfun -> machine -> eh_stack_adjust = sa ; } return cfun -> machine -> eh_stack_adjust ; } </s>

Implements EH_RETURN_STACKADJ_RTX . Saved and used later in m32c_emit_eh_epilogue .


<s> bool SPUAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'L' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + 1 == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + 1 ) . isReg ( ) ) return true ; ++ OpNo ; break ; } } printOperand ( MI , OpNo ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


"There must be a free register after frame setup"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> bool SITargetLowering :: isFMAFasterThanFMulAndFAdd ( EVT VT ) const { VT = VT . getScalarType ( ) ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f32 : { if ( Subtarget -> hasFP32Denormals ( ) ) return Subtarget -> hasFastFMAF32 ( ) || Subtarget -> hasDLInsts ( ) ; return Subtarget -> hasFastFMAF32 ( ) && Subtarget -> hasDLInsts ( ) ; } case MVT :: f64 : return true ; case MVT :: f16 : return Subtarget -> has16BitInsts ( ) && Subtarget -> hasFP16Denormals ( ) ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s>
const
MCPhysReg
*
AArch64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetWindows
(
)
)
return
CSR_Win_AArch64_AAPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_AArch64_NoRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_AArch64_AllRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_VectorCall
)
return
CSR_AArch64_AAVPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
CXX_FAST_TLS
)
return
MF
->
getInfo
<
AArch64FunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_AArch64_CXX_TLS_Darwin_PE_SaveList
:
CSR_AArch64_CXX_TLS_Darwin_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
.
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_AArch64_AAPCS_SwiftError_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
PreserveMost
)
return
CSR_AArch64_RT_MostRegs_SaveList
;
else
return
CSR_AArch64_AAPCS_SaveList
;
}
</s>


<s>
bool
MipsCodeEmitter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
JTI
=
(
(
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getJITInfo
(
)
;
II
=
(
(
const
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getInstrInfo
(
)
;
TD
=
(
(
const
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getTargetData
(
)
;
Subtarget
=
&
TM
.
getSubtarget
<
MipsSubtarget
>
(
)
;
MCPEs
=
&
MF
.
getConstantPool
(
)
->
getConstants
(
)
;
MJTEs
=
0
;
if
(
MF
.
getJumpTableInfo
(
)
)
MJTEs
=
&
MF
.
getJumpTableInfo
(
)
->
getJumpTables
(
)
;
JTI
->
Initialize
(
MF
,
IsPIC
)
;
MCE
.
setModuleInfo
(
&
getAnalysis
<
MachineModuleInfo
>
(
)
)
;
do
{
DEBUG
(
errs
(
)
<<
"JITTing function '"
<<
MF
.
getFunction
(
)
->
getName
(
)
<<
"'\n"
)
;
MCE
.
startFunction
(
MF
)
;
for
(
MachineFunction
::
iterator
MBB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBB
!=
E
;
++
MBB
)
{
MCE
.
StartMachineBasicBlock
(
MBB
)
;
for
(
MachineBasicBlock
::
const_iterator
I
=
MBB
->
begin
(
)
,
E
=
MBB
->
end
(
)
;
I
!=
E
;
++
I
)
emitInstruction
(
*
I
)
;
}
}
while
(
MCE
.
finishFunction
(
MF
)
)
;
return
false
;
}
</s>

Mips
Mips
Mips
Mips
Mips
Mips
0
"JITTing function '"
"'\n"


<s> T get ( uint32_t Idx ) const { assert ( Idx != 0 && ! Map . empty ( ) && Idx - 1 < Map . size ( ) ) ; return Map [ Idx - 1 ] ; } </s>

Get the generated Value for a given VPValue and given Part and Lane .


<s>
void
CSKYDAGToDAGISel
::
Select
(
SDNode
*
N
)
{
if
(
N
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
N
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;
N
->
setNodeId
(
1
)
;
return
;
}
SDLoc
Dl
(
N
)
;
unsigned
Opcode
=
N
->
getOpcode
(
)
;
bool
IsSelected
=
false
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
ADDCARRY
:
IsSelected
=
selectAddCarry
(
N
)
;
break
;
case
ISD
::
SUBCARRY
:
IsSelected
=
selectSubCarry
(
N
)
;
break
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
{
Register
GP
=
Subtarget
->
getInstrInfo
(
)
->
getGlobalBaseReg
(
*
MF
)
;
ReplaceNode
(
N
,
CurDAG
->
getRegister
(
GP
,
N
->
getValueType
(
0
)
)
.
getNode
(
)
)
;
IsSelected
=
true
;
break
;
}
case
ISD
::
FrameIndex
:
{
SDValue
Imm
=
CurDAG
->
getTargetConstant
(
0
,
Dl
,
MVT
::
i32
)
;
int
FI
=
cast
<
FrameIndexSDNode
>
(
N
)
->
getIndex
(
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
MVT
::
i32
)
;
ReplaceNode
(
N
,
CurDAG
->
getMachineNode
(
Subtarget
->
hasE2
(
)
CSKY
::
ADDI32
:
CSKY
::
ADDI16XZ
,
Dl
,
MVT
::
i32
,
TFI
,
Imm
)
)
;
IsSelected
=
true
;
break
;
}
case
CSKYISD
::
BITCAST_TO_LOHI
:
IsSelected
=
selectBITCAST_TO_LOHI
(
N
)
;
break
;
case
ISD
::
INLINEASM
:
case
ISD
::
INLINEASM_BR
:
IsSelected
=
selectInlineAsm
(
N
)
;
break
;
}
if
(
IsSelected
)
return
;
SelectCode
(
N
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> static bool classof ( const PIC16Section * ) { return true ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> bool RISCVTargetLowering :: isLegalAddImmediate ( int64_t Imm ) const { return isInt < 12 > ( Imm ) ; } </s>

Return true if the specified immediate is legal add immediate , that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register .


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


"va_start: n_gpr = %d, n_fpr = %d off %d\n"

Implement va_start by filling the va_list structure VALIST . STDARG_P is always true , and ignored . NEXTARG points to the first anonymous stack argument . The following global variables are used to initialize the va_list structure : current_function_args_info : holds number of gprs and fprs used for named arguments . current_function_arg_offset_rtx : holds the offset of the first anonymous stack argument ( relative to the virtual arg pointer ) .


<s> void ix86_expand_sse2_abs ( rtx target , rtx input ) { machine_mode mode = GET_MODE ( target ) ; rtx tmp0 , tmp1 , x ; switch ( mode ) { case V4SImode : tmp0 = expand_simple_binop ( mode , ASHIFTRT , input , GEN_INT ( GET_MODE_BITSIZE ( GET_MODE_INNER ( mode ) ) - 1 ) , NULL , 0 , OPTAB_DIRECT ) ; tmp1 = expand_simple_binop ( mode , XOR , tmp0 , input , NULL , 0 , OPTAB_DIRECT ) ; x = expand_simple_binop ( mode , MINUS , tmp1 , tmp0 , target , 0 , OPTAB_DIRECT ) ; break ; case V8HImode : tmp0 = expand_unop ( mode , neg_optab , input , NULL_RTX , 0 ) ; x = expand_simple_binop ( mode , SMAX , tmp0 , input , target , 0 , OPTAB_DIRECT ) ; break ; case V16QImode : tmp0 = expand_unop ( mode , neg_optab , input , NULL_RTX , 0 ) ; x = expand_simple_binop ( V16QImode , UMIN , tmp0 , input , target , 0 , OPTAB_DIRECT ) ; break ; default : gcc_unreachable ( ) ; } if ( x != target ) emit_move_insn ( target , x ) ; } </s>

Calculate integer abs ( ) using only SSE2 instructions .


<s> void SIFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedVGPRs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedVGPRs , RS ) ; SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; if ( MFI -> isEntryFunction ( ) ) return ; MachineFrameInfo & FrameInfo = MF . getFrameInfo ( ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const SIRegisterInfo * TRI = ST . getRegisterInfo ( ) ; SavedVGPRs . clearBitsNotInMask ( TRI -> getAllVGPRRegMask ( ) ) ; const bool WillHaveFP = FrameInfo . hasCalls ( ) && ( SavedVGPRs . any ( ) || ! allStackObjectsAreDead ( FrameInfo ) ) ; for ( auto SSpill : MFI -> getSGPRSpillVGPRs ( ) ) SavedVGPRs . reset ( SSpill . VGPR ) ; LivePhysRegs LiveRegs ; LiveRegs . init ( * TRI ) ; if ( WillHaveFP || hasFP ( MF ) ) { getVGPRSpillLaneOrTempRegister ( MF , LiveRegs , MFI -> SGPRForFPSaveRestoreCopy , MFI -> FramePointerSaveIndex , true ) ; } if ( TRI -> hasBasePointer ( MF ) ) { if ( MFI -> SGPRForFPSaveRestoreCopy ) LiveRegs . addReg ( MFI -> SGPRForFPSaveRestoreCopy ) ; getVGPRSpillLaneOrTempRegister ( MF , LiveRegs , MFI -> SGPRForBPSaveRestoreCopy , MFI -> BasePointerSaveIndex , false ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> static void s390_set_current_function ( tree fndecl ) { if ( fndecl == s390_previous_fndecl ) return ; tree old_tree ; if ( s390_previous_fndecl == NULL_TREE ) old_tree = target_option_current_node ; else if ( DECL_FUNCTION_SPECIFIC_TARGET ( s390_previous_fndecl ) ) old_tree = DECL_FUNCTION_SPECIFIC_TARGET ( s390_previous_fndecl ) ; else old_tree = target_option_default_node ; if ( fndecl == NULL_TREE ) { if ( old_tree != target_option_current_node ) s390_activate_target_options ( target_option_current_node ) ; return ; } tree new_tree = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( new_tree == NULL_TREE ) new_tree = target_option_default_node ; if ( old_tree != new_tree ) s390_activate_target_options ( new_tree ) ; s390_previous_fndecl = fndecl ; } </s>

Establish appropriate back-end context for processing the function FNDECL . The argument might be NULL to indicate processing at top level , outside of any function scope .


<s> bool ARMGlobalMerge :: doInitialization ( Module & M ) { SmallVector < GlobalVariable * , 16 > Globals , ConstGlobals , BSSGlobals ; const TargetData * TD = TLI -> getTargetData ( ) ; unsigned MaxOffset = TLI -> getMaximalGlobalOffset ( ) ; bool Changed = false ; for ( Module :: global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ; I != E ; ++ I ) { if ( ! I -> hasLocalLinkage ( ) || I -> isThreadLocal ( ) || I -> hasSection ( ) ) continue ; unsigned Alignment = I -> getAlignment ( ) ; Type * Ty = I -> getType ( ) -> getElementType ( ) ; if ( Alignment > TD -> getABITypeAlignment ( Ty ) ) continue ; if ( I -> getName ( ) . startswith ( "llvm." ) || I -> getName ( ) . startswith ( ".llvm." ) ) continue ; if ( TD -> getTypeAllocSize ( Ty ) < MaxOffset ) { const TargetLoweringObjectFile & TLOF = TLI -> getObjFileLowering ( ) ; if ( TLOF . getKindForGlobal ( I , TLI -> getTargetMachine ( ) ) . isBSSLocal ( ) ) BSSGlobals . push_back ( I ) ; else if ( I -> isConstant ( ) ) ConstGlobals . push_back ( I ) ; else Globals . push_back ( I ) ; } } if ( Globals . size ( ) > 1 ) Changed |= doMerge ( Globals , M , false ) ; if ( BSSGlobals . size ( ) > 1 ) Changed |= doMerge ( BSSGlobals , M , false ) ; return Changed ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s>
NVPTXTargetLowering
::
AtomicExpansionKind
NVPTXTargetLowering
::
shouldExpandAtomicRMWInIR
(
AtomicRMWInst
*
AI
)
const
{
Type
*
Ty
=
AI
->
getValOperand
(
)
->
getType
(
)
;
if
(
AI
->
isFloatingPointOperation
(
)
)
{
if
(
AI
->
getOperation
(
)
==
AtomicRMWInst
::
BinOp
::
FAdd
)
{
if
(
Ty
->
isFloatTy
(
)
)
return
AtomicExpansionKind
::
;
if
(
Ty
->
isDoubleTy
(
)
&&
STI
.
hasAtomAddF64
(
)
)
return
AtomicExpansionKind
::
;
}
return
AtomicExpansionKind
::
CmpXChg
;
}
assert
(
Ty
->
isIntegerTy
(
)
&&
"Ty should be integer at this point"
)
;
auto
ITy
=
cast
<
llvm
::
IntegerType
>
(
Ty
)
;
switch
(
AI
->
getOperation
(
)
)
{
default
:
return
AtomicExpansionKind
::
CmpXChg
;
case
AtomicRMWInst
::
BinOp
::
And
:
case
AtomicRMWInst
::
BinOp
::
Or
:
case
AtomicRMWInst
::
BinOp
::
Xor
:
case
AtomicRMWInst
::
BinOp
::
Xchg
:
switch
(
ITy
->
getBitWidth
(
)
)
{
case
8
:
case
16
:
return
AtomicExpansionKind
::
CmpXChg
;
case
32
:
return
AtomicExpansionKind
::
;
case
64
:
if
(
STI
.
hasAtomBitwise64
(
)
)
return
AtomicExpansionKind
::
;
return
AtomicExpansionKind
::
CmpXChg
;
default
:
llvm_unreachable
(
"unsupported width encountered"
)
;
}
case
AtomicRMWInst
::
BinOp
::
Add
:
case
AtomicRMWInst
::
BinOp
::
Sub
:
case
AtomicRMWInst
::
BinOp
::
Max
:
case
AtomicRMWInst
::
BinOp
::
Min
:
case
AtomicRMWInst
::
BinOp
::
UMax
:
case
AtomicRMWInst
::
BinOp
::
UMin
:
switch
(
ITy
->
getBitWidth
(
)
)
{
case
8
:
case
16
:
return
AtomicExpansionKind
::
CmpXChg
;
case
32
:
return
AtomicExpansionKind
::
;
case
64
:
if
(
STI
.
hasAtomMinMax64
(
)
)
return
AtomicExpansionKind
::
;
return
AtomicExpansionKind
::
CmpXChg
;
default
:
llvm_unreachable
(
"unsupported width encountered"
)
;
}
}
return
AtomicExpansionKind
::
CmpXChg
;
}
</s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> bool PPCInstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( MI . getOpcode ( ) == PPC :: MFFS || MI . getOpcode ( ) == PPC :: MTFSF ) return true ; return TargetInstrInfo :: isSchedulingBoundary ( MI , MBB , MF ) ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> static bool visium_pass_by_reference ( cumulative_args_t ca ATTRIBUTE_UNUSED , enum machine_mode mode ATTRIBUTE_UNUSED , const_tree type , bool named ATTRIBUTE_UNUSED ) { return type && ( AGGREGATE_TYPE_P ( type ) || TREE_CODE ( type ) == VECTOR_TYPE ) ; } </s>

Return true if an argument must be passed by indirect reference .


<s> SDValue SITargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( N ) ; EVT VT = N -> getValueType ( 0 ) ; switch ( N -> getOpcode ( ) ) { default : return AMDGPUTargetLowering :: PerformDAGCombine ( N , DCI ) ; case ISD :: SELECT_CC : { ConstantSDNode * True , * False ; if ( ( True = dyn_cast < ConstantSDNode > ( N -> getOperand ( 2 ) ) ) && ( False = dyn_cast < ConstantSDNode > ( N -> getOperand ( 3 ) ) ) && True -> isAllOnesValue ( ) && False -> isNullValue ( ) && VT == MVT :: i1 ) { return DAG . getNode ( ISD :: SETCC , DL , VT , N -> getOperand ( 0 ) , N -> getOperand ( 1 ) , N -> getOperand ( 4 ) ) ; } break ; } case ISD :: SETCC : { SDValue Arg0 = N -> getOperand ( 0 ) ; SDValue Arg1 = N -> getOperand ( 1 ) ; SDValue CC = N -> getOperand ( 2 ) ; ConstantSDNode * C = nullptr ; ISD :: CondCode CCOp = dyn_cast < CondCodeSDNode > ( CC ) -> get ( ) ; if ( VT == MVT :: i1 && Arg0 . getOpcode ( ) == ISD :: SIGN_EXTEND && Arg0 . getOperand ( 0 ) . getValueType ( ) == MVT :: i1 && ( C = dyn_cast < ConstantSDNode > ( Arg1 ) ) && C -> isNullValue ( ) && CCOp == ISD :: SETNE ) { return SimplifySetCC ( VT , Arg0 . getOperand ( 0 ) , DAG . getConstant ( 0 , MVT :: i1 ) , CCOp , true , DCI , DL ) ; } break ; } } return AMDGPUTargetLowering :: PerformDAGCombine ( N , DCI ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> static void visium_function_arg_advance ( cumulative_args_t pcum_v , const function_arg_info & arg ) { int size = ( GET_MODE_SIZE ( arg . mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; int stack_size = 0 ; CUMULATIVE_ARGS * ca = get_cumulative_args ( pcum_v ) ; if ( TARGET_FPU && ( ( GET_MODE_CLASS ( arg . mode ) == MODE_FLOAT && GET_MODE_SIZE ( arg . mode ) <= UNITS_PER_HWFPVALUE ) || ( GET_MODE_CLASS ( arg . mode ) == MODE_COMPLEX_FLOAT && GET_MODE_SIZE ( arg . mode ) <= UNITS_PER_HWFPVALUE * 2 ) ) ) { if ( ca -> frcount + size <= MAX_ARGS_IN_FP_REGISTERS ) ca -> frcount += size ; else { stack_size = size ; ca -> frcount = MAX_ARGS_IN_FP_REGISTERS ; } } else { if ( ca -> grcount + size <= MAX_ARGS_IN_GP_REGISTERS ) ca -> grcount += size ; else { stack_size = size ; ca -> grcount = MAX_ARGS_IN_GP_REGISTERS ; } } if ( arg . named ) ca -> stack_words += stack_size ; } </s>

Update the summarizer variable pointed to by PCUM_V to advance past an argument in the argument list . The values MODE , TYPE and NAMED describe that argument . Once this is done , the variable CUM is suitable for analyzing the _following_ argument with visium_function_arg .


<s>
MachineInstr
*
ARMBaseInstrInfo
::
optimizeSelect
(
MachineInstr
*
MI
,
SmallPtrSetImpl
<
MachineInstr
*
>
&
SeenMIs
,
bool
PreferFalse
)
const
{
assert
(
(
MI
->
getOpcode
(
)
==
ARM
::
MOVCCr
||
MI
->
getOpcode
(
)
==
ARM
::
t2MOVCCr
)
&&
"Unknown select instruction"
)
;
MachineRegisterInfo
&
MRI
=
MI
->
getParent
(
)
->
getParent
(
)
->
getRegInfo
(
)
;
MachineInstr
*
DefMI
=
canFoldIntoMOVCC
(
MI
->
getOperand
(
2
)
.
getReg
(
)
,
MRI
,
this
)
;
bool
Invert
=
!
DefMI
;
if
(
!
DefMI
)
DefMI
=
canFoldIntoMOVCC
(
MI
->
getOperand
(
1
)
.
getReg
(
)
,
MRI
,
this
)
;
if
(
!
DefMI
)
return
nullptr
;
MachineOperand
FalseReg
=
MI
->
getOperand
(
Invert
2
:
1
)
;
unsigned
DestReg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
const
TargetRegisterClass
*
PreviousClass
=
MRI
.
getRegClass
(
FalseReg
.
getReg
(
)
)
;
if
(
!
MRI
.
constrainRegClass
(
DestReg
,
PreviousClass
)
)
return
nullptr
;
MachineInstrBuilder
NewMI
=
BuildMI
(
*
MI
->
getParent
(
)
,
MI
,
MI
->
getDebugLoc
(
)
,
DefMI
->
getDesc
(
)
,
DestReg
)
;
const
MCInstrDesc
&
DefDesc
=
DefMI
->
getDesc
(
)
;
for
(
unsigned
i
=
1
,
e
=
DefDesc
.
getNumOperands
(
)
;
i
!=
e
&&
!
DefDesc
.
OpInfo
[
i
]
.
isPredicate
(
)
;
++
i
)
NewMI
.
addOperand
(
DefMI
->
getOperand
(
i
)
)
;
unsigned
CondCode
=
MI
->
getOperand
(
3
)
.
getImm
(
)
;
if
(
Invert
)
NewMI
.
addImm
(
ARMCC
::
getOppositeCondition
(
ARMCC
::
CondCodes
(
CondCode
)
)
)
;
else
NewMI
.
addImm
(
CondCode
)
;
NewMI
.
addOperand
(
MI
->
getOperand
(
4
)
)
;
if
(
NewMI
->
hasOptionalDef
(
)
)
AddDefaultCC
(
NewMI
)
;
FalseReg
.
setImplicit
(
)
;
NewMI
.
addOperand
(
FalseReg
)
;
NewMI
->
tieOperands
(
0
,
NewMI
->
getNumOperands
(
)
1
)
;
SeenMIs
.
insert
(
NewMI
)
;
SeenMIs
.
erase
(
DefMI
)
;
DefMI
->
eraseFromParent
(
)
;
return
NewMI
;
}
</s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


<s> const MipsGOT & MipsGNULDBackend :: getGOT ( ) const { assert ( m_pGOT != NULL ) ; return * m_pGOT ; } </s>

Return a pseudo source value referencing the global offset table ( or something the like ) .


<s> const char * MipsTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case MipsISD :: JmpLink : return "MipsISD::JmpLink" ; case MipsISD :: Hi : return "MipsISD::Hi" ; case MipsISD :: Lo : return "MipsISD::Lo" ; case MipsISD :: GPRel : return "MipsISD::GPRel" ; case MipsISD :: Ret : return "MipsISD::Ret" ; case MipsISD :: CMov : return "MipsISD::CMov" ; case MipsISD :: SelectCC : return "MipsISD::SelectCC" ; case MipsISD :: FPSelectCC : return "MipsISD::FPSelectCC" ; case MipsISD :: FPBrcond : return "MipsISD::FPBrcond" ; case MipsISD :: FPCmp : return "MipsISD::FPCmp" ; case MipsISD :: FPRound : return "MipsISD::FPRound" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific

Mips Mips MipsISD::JmpLink "MipsISD::JmpLink" MipsISD::Hi "MipsISD::Hi" MipsISD::Lo "MipsISD::Lo" MipsISD::GPRel "MipsISD::GPRel" MipsISD::Ret "MipsISD::Ret" MipsISD::CMov "MipsISD::CMov" MipsISD::SelectCC "MipsISD::SelectCC" MipsISD::FPSelectCC "MipsISD::FPSelectCC" MipsISD::FPBrcond "MipsISD::FPBrcond" MipsISD::FPCmp "MipsISD::FPCmp" MipsISD::FPRound "MipsISD::FPRound"


<s> static void expand_set_or_movmem_via_rep ( rtx destmem , rtx srcmem , rtx destptr , rtx srcptr , rtx value , rtx orig_value , rtx count , machine_mode mode , bool issetmem ) { rtx destexp ; rtx srcexp ; rtx countreg ; HOST_WIDE_INT rounded_count ; if ( mode == QImode && CONST_INT_P ( count ) && ! ( INTVAL ( count ) & 3 ) && ( ! issetmem || orig_value == const0_rtx ) ) mode = SImode ; if ( destptr != XEXP ( destmem , 0 ) || GET_MODE ( destmem ) != BLKmode ) destmem = adjust_automodify_address_nv ( destmem , BLKmode , destptr , 0 ) ; countreg = ix86_zero_extend_to_Pmode ( scale_counter ( count , GET_MODE_SIZE ( mode ) ) ) ; if ( mode != QImode ) { destexp = gen_rtx_ASHIFT ( Pmode , countreg , GEN_INT ( exact_log2 ( GET_MODE_SIZE ( mode ) ) ) ) ; destexp = gen_rtx_PLUS ( Pmode , destexp , destptr ) ; } else destexp = gen_rtx_PLUS ( Pmode , destptr , countreg ) ; if ( ( ! issetmem || orig_value == const0_rtx ) && CONST_INT_P ( count ) ) { rounded_count = ROUND_DOWN ( INTVAL ( count ) , ( HOST_WIDE_INT ) GET_MODE_SIZE ( mode ) ) ; destmem = shallow_copy_rtx ( destmem ) ; set_mem_size ( destmem , rounded_count ) ; } else if ( MEM_SIZE_KNOWN_P ( destmem ) ) clear_mem_size ( destmem ) ; if ( issetmem ) { value = force_reg ( mode , gen_lowpart ( mode , value ) ) ; emit_insn ( gen_rep_stos ( destptr , countreg , destmem , value , destexp ) ) ; } else { if ( srcptr != XEXP ( srcmem , 0 ) || GET_MODE ( srcmem ) != BLKmode ) srcmem = adjust_automodify_address_nv ( srcmem , BLKmode , srcptr , 0 ) ; if ( mode != QImode ) { srcexp = gen_rtx_ASHIFT ( Pmode , countreg , GEN_INT ( exact_log2 ( GET_MODE_SIZE ( mode ) ) ) ) ; srcexp = gen_rtx_PLUS ( Pmode , srcexp , srcptr ) ; } else srcexp = gen_rtx_PLUS ( Pmode , srcptr , countreg ) ; if ( CONST_INT_P ( count ) ) { rounded_count = ROUND_DOWN ( INTVAL ( count ) , ( HOST_WIDE_INT ) GET_MODE_SIZE ( mode ) ) ; srcmem = shallow_copy_rtx ( srcmem ) ; set_mem_size ( srcmem , rounded_count ) ; } else { if ( MEM_SIZE_KNOWN_P ( srcmem ) ) clear_mem_size ( srcmem ) ; } emit_insn ( gen_rep_mov ( destptr , destmem , srcptr , srcmem , countreg , destexp , srcexp ) ) ; } } </s>

Output `` rep ; mov '' or `` rep ; stos '' instruction depending on ISSETMEM argument . When ISSETMEM is true , arguments SRCMEM and SRCPTR are ignored . When ISSETMEM is false , arguments VALUE and ORIG_VALUE are ignored . For setmem case , VALUE is a promoted to a wider size ORIG_VALUE . ORIG_VALUE is the original value passed to memset to fill the memory with . Other arguments have same meaning as for previous function .


<s>
void
assignValueToReg
(
Register
ValVReg
,
Register
PhysReg
,
CCValAssign
&
VA
)
override
{
MIB
.
addUse
(
PhysReg
,
RegState
::
Implicit
)
;
Register
ExtReg
;
unsigned
PhysRegSize
=
MRI
.
getTargetRegisterInfo
(
)
->
getRegSizeInBits
(
PhysReg
,
MRI
)
;
unsigned
ValSize
=
VA
.
getValVT
(
)
.
getSizeInBits
(
)
;
unsigned
LocSize
=
VA
.
getLocVT
(
)
.
getSizeInBits
(
)
;
if
(
PhysRegSize
>
ValSize
&&
LocSize
==
ValSize
)
{
assert
(
(
PhysRegSize
==
128
||
PhysRegSize
==
80
)
&&
"We expect that to be 128 bit"
)
;
auto
MIB
=
MIRBuilder
.
buildAnyExt
(
LLT
::
scalar
(
PhysRegSize
)
,
ValVReg
)
;
ExtReg
=
MIB
.
getReg
(
0
)
;
}
else
ExtReg
=
extendRegister
(
ValVReg
,
VA
)
;
MIRBuilder
.
buildCopy
(
PhysReg
,
ExtReg
)
;
}
</s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> static void rs6000_emit_prologue_components ( sbitmap components ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; rtx ptr_reg = gen_rtx_REG ( Pmode , frame_pointer_needed ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ) ; int reg_size = TARGET_32BIT ? 4 : 8 ; if ( bitmap_bit_p ( components , 0 ) ) { rtx reg = gen_rtx_REG ( Pmode , 0 ) ; rtx_insn * insn = emit_move_insn ( reg , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_REGISTER , NULL ) ; int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; rtx lr = gen_rtx_REG ( Pmode , LR_REGNO ) ; rtx mem = copy_rtx ( SET_DEST ( single_set ( insn ) ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , gen_rtx_SET ( mem , lr ) ) ; } int offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_gp_reg_save ; i < 32 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( Pmode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; rtx set = copy_rtx ( single_set ( insn ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , set ) ; } offset += reg_size ; } } </s>


<s> static unsigned int frv_insn_unit ( rtx_insn * insn ) { enum attr_type type ; type = get_attr_type ( insn ) ; if ( frv_type_to_unit [ type ] == ARRAY_SIZE ( frv_unit_codes ) ) { state_t state ; unsigned int unit ; state = alloca ( state_size ( ) ) ; state_reset ( state ) ; state_transition ( state , insn ) ; for ( unit = 0 ; unit < ARRAY_SIZE ( frv_unit_codes ) ; unit ++ ) if ( cpu_unit_reservation_p ( state , frv_unit_codes [ unit ] ) ) break ; gcc_assert ( unit != ARRAY_SIZE ( frv_unit_codes ) ) ; frv_type_to_unit [ type ] = unit ; } return frv_type_to_unit [ type ] ; } </s>

Return the index of the DFA unit in FRV_UNIT_NAMES [ ] that instruction INSN will try to claim first . Since this value depends only on the type attribute , we can cache the results in FRV_TYPE_TO_UNIT [ ] .


<s> static void s390_emit_stack_tie ( void ) { rtx mem = gen_frame_mem ( BLKmode , stack_pointer_rtx ) ; if ( frame_pointer_needed ) emit_insn ( gen_stack_tie ( Pmode , mem , hard_frame_pointer_rtx ) ) ; else emit_insn ( gen_stack_tie ( Pmode , mem , stack_pointer_rtx ) ) ; } </s>

This ties together stack memory ( MEM with an alias set of frame_alias_set ) and the change to the stack pointer .


<s>
int
AArch64InstrInfo
::
getMemScale
(
unsigned
Opc
)
{
switch
(
Opc
)
{
default
:
llvm_unreachable
(
"Opcode has unknown scale!"
)
;
case
AArch64
::
LDRBBui
:
case
AArch64
::
LDURBBi
:
case
AArch64
::
LDRSBWui
:
case
AArch64
::
LDURSBWi
:
case
AArch64
::
STRBBui
:
case
AArch64
::
STURBBi
:
return
1
;
case
AArch64
::
LDRHHui
:
case
AArch64
::
LDURHHi
:
case
AArch64
::
LDRSHWui
:
case
AArch64
::
LDURSHWi
:
case
AArch64
::
STRHHui
:
case
AArch64
::
STURHHi
:
return
2
;
case
AArch64
::
LDRSui
:
case
AArch64
::
LDURSi
:
case
AArch64
::
LDRSWui
:
case
AArch64
::
LDURSWi
:
case
AArch64
::
LDRWui
:
case
AArch64
::
LDURWi
:
case
AArch64
::
STRSui
:
case
AArch64
::
STURSi
:
case
AArch64
::
STRWui
:
case
AArch64
::
STURWi
:
case
AArch64
::
LDPSi
:
case
AArch64
::
LDPSWi
:
case
AArch64
::
LDPWi
:
case
AArch64
::
STPSi
:
case
AArch64
::
STPWi
:
return
4
;
case
AArch64
::
LDRDui
:
case
AArch64
::
LDURDi
:
case
AArch64
::
LDRXui
:
case
AArch64
::
LDURXi
:
case
AArch64
::
STRDui
:
case
AArch64
::
STURDi
:
case
AArch64
::
STRXui
:
case
AArch64
::
STURXi
:
case
AArch64
::
LDPDi
:
case
AArch64
::
LDPXi
:
case
AArch64
::
STPDi
:
case
AArch64
::
STPXi
:
return
8
;
case
AArch64
::
LDRQui
:
case
AArch64
::
LDURQi
:
case
AArch64
::
STRQui
:
case
AArch64
::
STURQi
:
case
AArch64
::
LDPQi
:
case
AArch64
::
STPQi
:
case
AArch64
::
STGOffset
:
case
AArch64
::
STZGOffset
:
case
AArch64
::
ST2GOffset
:
case
AArch64
::
STZ2GOffset
:
case
AArch64
::
STGPi
:
return
16
;
}
}
</s>

Scaling factor for ( scaled or unscaled ) load or store .


<s> void m32c_print_operand_address ( FILE * stream , rtx address ) { gcc_assert ( GET_CODE ( address ) == MEM ) ; m32c_print_operand ( stream , XEXP ( address , 0 ) , 0 ) ; } </s>

Implements PRINT_OPERAND_ADDRESS . Nothing unusual here .


<s> static void do_load_for_compare ( rtx reg , rtx mem , machine_mode mode ) { switch ( GET_MODE ( reg ) ) { case E_V16QImode : switch ( mode ) { case E_V16QImode : if ( ! BYTES_BIG_ENDIAN ) { if ( TARGET_P9_VECTOR ) emit_insn ( gen_vsx_ld_elemrev_v16qi_internal ( reg , mem ) ) ; else { rtx reg_v2di = simplify_gen_subreg ( V2DImode , reg , V16QImode , 0 ) ; gcc_assert ( MEM_P ( mem ) ) ; rtx addr = XEXP ( mem , 0 ) ; rtx mem_v2di = gen_rtx_MEM ( V2DImode , addr ) ; MEM_COPY_ATTRIBUTES ( mem_v2di , mem ) ; set_mem_size ( mem , GET_MODE_SIZE ( V2DImode ) ) ; emit_insn ( gen_vsx_ld_elemrev_v2di ( reg_v2di , mem_v2di ) ) ; } } else emit_insn ( gen_vsx_movv2di_64bit ( reg , mem ) ) ; break ; default : gcc_unreachable ( ) ; } break ; case E_DImode : switch ( mode ) { case E_QImode : emit_insn ( gen_zero_extendqidi2 ( reg , mem ) ) ; break ; case E_HImode : { rtx src = mem ; if ( ! BYTES_BIG_ENDIAN ) { src = gen_reg_rtx ( HImode ) ; emit_insn ( gen_bswaphi2 ( src , mem ) ) ; } emit_insn ( gen_zero_extendhidi2 ( reg , src ) ) ; break ; } case E_SImode : { rtx src = mem ; if ( ! BYTES_BIG_ENDIAN ) { src = gen_reg_rtx ( SImode ) ; emit_insn ( gen_bswapsi2 ( src , mem ) ) ; } emit_insn ( gen_zero_extendsidi2 ( reg , src ) ) ; } break ; case E_DImode : if ( ! BYTES_BIG_ENDIAN ) emit_insn ( gen_bswapdi2 ( reg , mem ) ) ; else emit_insn ( gen_movdi ( reg , mem ) ) ; break ; default : gcc_unreachable ( ) ; } break ; case E_SImode : switch ( mode ) { case E_QImode : emit_insn ( gen_zero_extendqisi2 ( reg , mem ) ) ; break ; case E_HImode : { rtx src = mem ; if ( ! BYTES_BIG_ENDIAN ) { src = gen_reg_rtx ( HImode ) ; emit_insn ( gen_bswaphi2 ( src , mem ) ) ; } emit_insn ( gen_zero_extendhisi2 ( reg , src ) ) ; break ; } case E_SImode : if ( ! BYTES_BIG_ENDIAN ) emit_insn ( gen_bswapsi2 ( reg , mem ) ) ; else emit_insn ( gen_movsi ( reg , mem ) ) ; break ; case E_DImode : gcc_unreachable ( ) ; break ; default : gcc_unreachable ( ) ; } break ; case E_QImode : gcc_assert ( mode == E_QImode ) ; emit_move_insn ( reg , mem ) ; break ; default : gcc_unreachable ( ) ; break ; } } </s>

Figure out the correct instructions to generate to load data for block compare . MODE is used for the read from memory , and data is zero extended if REG is wider than MODE . If LE code is being generated , bswap loads are used . REG is the destination register to move the data into . MEM is the memory block being read . MODE is the mode of memory to use for the read .


<s>
bool
HCE
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
DEBUG
(
MF
.
print
(
dbgs
(
)
<<
"Before "
<<
getPassName
(
)
<<
'\n'
,
nullptr
)
)
;
HII
=
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getInstrInfo
(
)
;
HRI
=
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getRegisterInfo
(
)
;
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
AssignmentMap
IMap
;
collect
(
MF
)
;
llvm
::
sort
(
Extenders
.
begin
(
)
,
Extenders
.
end
(
)
,
[
]
(
const
ExtDesc
&
A
,
const
ExtDesc
&
B
)
{
return
ExtValue
(
A
)
<
ExtValue
(
B
)
;
}
)
;
bool
Changed
=
false
;
DEBUG
(
dbgs
(
)
<<
"Collected "
<<
Extenders
.
size
(
)
<<
" extenders\n"
)
;
for
(
unsigned
I
=
0
,
E
=
Extenders
.
size
(
)
;
I
!=
E
;
)
{
unsigned
B
=
I
;
const
ExtRoot
&
T
=
Extenders
[
B
]
.
getOp
(
)
;
while
(
I
!=
E
&&
ExtRoot
(
Extenders
[
I
]
.
getOp
(
)
)
==
T
)
++
I
;
IMap
.
clear
(
)
;
assignInits
(
T
,
B
,
I
,
IMap
)
;
Changed
|=
replaceExtenders
(
IMap
)
;
}
DEBUG
(
{
if
(
Changed
)
MF
.
print
(
dbgs
(
)
<<
"After "
<<
getPassName
(
)
<<
'\n'
,
nullptr
)
;
else
dbgs
(
)
<<
"No changes\n"
;
}
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

Hexagon
"Before "
Hexagon
Hexagon
"Collected "
" extenders\n"
0
"After "
"No changes\n"


"force: group count = %d, can_issue_more = %d\n"

"done force: group count = %d, can_issue_more = %d\n"

Utility of the function redefine_groups . Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS in the same dispatch group . If so , insert nops before NEXT_INSN , in order to keep it `` far '' ( in a separate group ) from GROUP_INSNS , following one of the following schemes , depending on the value of the flag -minsert_sched_nops = X : ( 1 ) X == sched_finish_regroup_exact : insert exactly as many nops as needed in order to force NEXT_INSN into a separate group . ( 2 ) X < sched_finish_regroup_exact : insert exactly X nops . GROUP_END , CAN_ISSUE_MORE and GROUP_COUNT record the state after nop insertion ( has a group just ended , how many vacant issue slots remain in the last group , and how many dispatch groups were encountered so far ) .


<s> const Z80oldInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> static bool split_stack_arg_pointer_used_p ( void ) { if ( cfun -> machine -> split_stack_arg_pointer != NULL_RTX && ( ! REG_P ( cfun -> machine -> split_stack_arg_pointer ) || HARD_REGISTER_P ( cfun -> machine -> split_stack_arg_pointer ) ) ) return true ; rtx_insn * insn ; basic_block bb = ENTRY_BLOCK_PTR_FOR_FN ( cfun ) -> next_bb ; FOR_BB_INSNS ( bb , insn ) if ( NONDEBUG_INSN_P ( insn ) ) { if ( CALL_P ( insn ) ) return false ; df_ref use ; FOR_EACH_INSN_USE ( use , insn ) { rtx x = DF_REF_REG ( use ) ; if ( REG_P ( x ) && REGNO ( x ) == 12 ) return true ; } df_ref def ; FOR_EACH_INSN_DEF ( def , insn ) { rtx x = DF_REF_REG ( def ) ; if ( REG_P ( x ) && REGNO ( x ) == 12 ) return false ; } } return bitmap_bit_p ( DF_LR_OUT ( bb ) , 12 ) ; } </s>

Return whether the split-stack arg pointer ( r12 ) is used .


"  Skipping pass: no machine model present.\n"


<s> bool isReg ( ) const override { return Kind == k_Reg ; } </s>


<s> const char * PPCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return nullptr ; case PPCISD :: FSEL : return "PPCISD::FSEL" ; case PPCISD :: FCFID : return "PPCISD::FCFID" ; case PPCISD :: FCTIDZ : return "PPCISD::FCTIDZ" ; case PPCISD :: FCTIWZ : return "PPCISD::FCTIWZ" ; case PPCISD :: FRE : return "PPCISD::FRE" ; case PPCISD :: FRSQRTE : return "PPCISD::FRSQRTE" ; case PPCISD :: STFIWX : return "PPCISD::STFIWX" ; case PPCISD :: VMADDFP : return "PPCISD::VMADDFP" ; case PPCISD :: VNMSUBFP : return "PPCISD::VNMSUBFP" ; case PPCISD :: VPERM : return "PPCISD::VPERM" ; case PPCISD :: Hi : return "PPCISD::Hi" ; case PPCISD :: Lo : return "PPCISD::Lo" ; case PPCISD :: TOC_ENTRY : return "PPCISD::TOC_ENTRY" ; case PPCISD :: TOC_RESTORE : return "PPCISD::TOC_RESTORE" ; case PPCISD :: LOAD : return "PPCISD::LOAD" ; case PPCISD :: LOAD_TOC : return "PPCISD::LOAD_TOC" ; case PPCISD :: DYNALLOC : return "PPCISD::DYNALLOC" ; case PPCISD :: GlobalBaseReg : return "PPCISD::GlobalBaseReg" ; case PPCISD :: SRL : return "PPCISD::SRL" ; case PPCISD :: SRA : return "PPCISD::SRA" ; case PPCISD :: SHL : return "PPCISD::SHL" ; case PPCISD :: CALL : return "PPCISD::CALL" ; case PPCISD :: CALL_NOP : return "PPCISD::CALL_NOP" ; case PPCISD :: MTCTR : return "PPCISD::MTCTR" ; case PPCISD :: BCTRL : return "PPCISD::BCTRL" ; case PPCISD :: RET_FLAG : return "PPCISD::RET_FLAG" ; case PPCISD :: EH_SJLJ_SETJMP : return "PPCISD::EH_SJLJ_SETJMP" ; case PPCISD :: EH_SJLJ_LONGJMP : return "PPCISD::EH_SJLJ_LONGJMP" ; case PPCISD :: MFOCRF : return "PPCISD::MFOCRF" ; case PPCISD :: VCMP : return "PPCISD::VCMP" ; case PPCISD :: VCMPo : return "PPCISD::VCMPo" ; case PPCISD :: LBRX : return "PPCISD::LBRX" ; case PPCISD :: STBRX : return "PPCISD::STBRX" ; case PPCISD :: LARX : return "PPCISD::LARX" ; case PPCISD :: STCX : return "PPCISD::STCX" ; case PPCISD :: COND_BRANCH : return "PPCISD::COND_BRANCH" ; case PPCISD :: BDNZ : return "PPCISD::BDNZ" ; case PPCISD :: BDZ : return "PPCISD::BDZ" ; case PPCISD :: MFFS : return "PPCISD::MFFS" ; case PPCISD :: FADDRTZ : return "PPCISD::FADDRTZ" ; case PPCISD :: TC_RETURN : return "PPCISD::TC_RETURN" ; case PPCISD :: CR6SET : return "PPCISD::CR6SET" ; case PPCISD :: CR6UNSET : return "PPCISD::CR6UNSET" ; case PPCISD :: ADDIS_TOC_HA : return "PPCISD::ADDIS_TOC_HA" ; case PPCISD :: LD_TOC_L : return "PPCISD::LD_TOC_L" ; case PPCISD :: ADDI_TOC_L : return "PPCISD::ADDI_TOC_L" ; case PPCISD :: PPC32_GOT : return "PPCISD::PPC32_GOT" ; case PPCISD :: ADDIS_GOT_TPREL_HA : return "PPCISD::ADDIS_GOT_TPREL_HA" ; case PPCISD :: LD_GOT_TPREL_L : return "PPCISD::LD_GOT_TPREL_L" ; case PPCISD :: ADD_TLS : return "PPCISD::ADD_TLS" ; case PPCISD :: ADDIS_TLSGD_HA : return "PPCISD::ADDIS_TLSGD_HA" ; case PPCISD :: ADDI_TLSGD_L : return "PPCISD::ADDI_TLSGD_L" ; case PPCISD :: GET_TLS_ADDR : return "PPCISD::GET_TLS_ADDR" ; case PPCISD :: ADDIS_TLSLD_HA : return "PPCISD::ADDIS_TLSLD_HA" ; case PPCISD :: ADDI_TLSLD_L : return "PPCISD::ADDI_TLSLD_L" ; case PPCISD :: GET_TLSLD_ADDR : return "PPCISD::GET_TLSLD_ADDR" ; case PPCISD :: ADDIS_DTPREL_HA : return "PPCISD::ADDIS_DTPREL_HA" ; case PPCISD :: ADDI_DTPREL_L : return "PPCISD::ADDI_DTPREL_L" ; case PPCISD :: VADD_SPLAT : return "PPCISD::VADD_SPLAT" ; case PPCISD :: SC : return "PPCISD::SC" ; } } </s>


<s> void RISCVInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { if ( NoAliases || ! printAliasInstr ( MI , STI , O ) ) printInstruction ( MI , STI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> void X86TargetLowering :: finalizeLowering ( MachineFunction & MF ) const { if ( hasCopyImplyingStackAdjustment ( MF ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setHasCopyImplyingStackAdjustment ( true ) ; } TargetLoweringBase :: finalizeLowering ( MF ) ; } </s>

Execute target specific actions to finalize target lowering .


<s> static bool use_skip_p ( rtx_insn * insn ) { rtx_insn * jump_insn = next_active_insn ( JUMP_LABEL ( insn ) ) ; while ( insn ) { insn = next_active_insn ( insn ) ; if ( ! insn || GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT || extract_asm_operands ( PATTERN ( insn ) ) != NULL_RTX ) break ; if ( get_attr_length ( insn ) == 4 && jump_insn == next_active_insn ( insn ) ) return TRUE ; if ( get_attr_length ( insn ) > 0 ) break ; } return FALSE ; } </s>

Return TRUE if INSN , a forward jump insn , can use nullification to skip the following instruction . This avoids an extra cycle due to a mis-predicted branch when we fall through .


<s> void MipsAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; if ( MI -> isDebugValue ( ) ) { PrintDebugValueComment ( MI , OS ) ; return ; } MipsMCInstLower MCInstLowering ( Mang , * MF , * this ) ; unsigned Opc = MI -> getOpcode ( ) ; MCInst TmpInst0 ; SmallVector < MCInst , 4 > MCInsts ; MCInstLowering . Lower ( MI , TmpInst0 ) ; if ( ! OutStreamer . hasRawTextSupport ( ) && isDirective ( Opc ) ) return ; if ( isUnalignedLoadStore ( Opc ) ) { if ( OutStreamer . hasRawTextSupport ( ) ) { MCInst Directive ; Directive . setOpcode ( Mips :: MACRO ) ; OutStreamer . EmitInstruction ( Directive ) ; OutStreamer . EmitInstruction ( TmpInst0 ) ; Directive . setOpcode ( Mips :: NOMACRO ) ; OutStreamer . EmitInstruction ( Directive ) ; } else { MCInstLowering . LowerUnalignedLoadStore ( MI , MCInsts ) ; for ( SmallVector < MCInst , 4 > :: iterator I = MCInsts . begin ( ) ; I != MCInsts . end ( ) ; ++ I ) OutStreamer . EmitInstruction ( * I ) ; } return ; } if ( ! OutStreamer . hasRawTextSupport ( ) ) { if ( Opc == Mips :: CPLOAD ) { MCInstLowering . LowerCPLOAD ( MI , MCInsts ) ; for ( SmallVector < MCInst , 4 > :: iterator I = MCInsts . begin ( ) ; I != MCInsts . end ( ) ; ++ I ) OutStreamer . EmitInstruction ( * I ) ; return ; } if ( Opc == Mips :: CPRESTORE ) { MCInstLowering . LowerCPRESTORE ( MI , TmpInst0 ) ; OutStreamer . EmitInstruction ( TmpInst0 ) ; return ; } } OutStreamer . EmitInstruction ( TmpInst0 ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> const uint16_t * BPFRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_SaveList ; } </s>


<s> rtx msp430_subreg ( machine_mode mode , rtx r , machine_mode omode , int byte ) { rtx rv ; if ( GET_CODE ( r ) == SUBREG && SUBREG_BYTE ( r ) == 0 ) { rtx ireg = SUBREG_REG ( r ) ; machine_mode imode = GET_MODE ( ireg ) ; if ( imode == PSImode && mode == HImode && byte == 0 ) rv = gen_rtx_SUBREG ( mode , ireg , byte ) ; else rv = simplify_gen_subreg ( mode , ireg , imode , byte ) ; } else if ( GET_CODE ( r ) == MEM ) rv = adjust_address ( r , mode , byte ) ; else if ( GET_CODE ( r ) == SYMBOL_REF && ( byte == 0 || byte == 2 ) && mode == HImode ) { rv = gen_rtx_ZERO_EXTRACT ( HImode , r , GEN_INT ( 16 ) , GEN_INT ( 8 * byte ) ) ; rv = gen_rtx_CONST ( HImode , r ) ; } else rv = simplify_gen_subreg ( mode , r , omode , byte ) ; if ( ! rv ) gcc_unreachable ( ) ; return rv ; } </s>

Simplify_gen_subreg ( ) does n't handle memory references the way we need it to below , so we use this function for when we must get a valid subreg in a `` natural '' state .


<s>
bool
HexagonRDFOpt
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
RDFLimit
.
getPosition
(
)
)
{
if
(
RDFCount
>=
RDFLimit
)
return
false
;
RDFCount
++
;
}
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
const
auto
&
MDF
=
getAnalysis
<
MachineDominanceFrontier
>
(
)
;
const
auto
&
HII
=
*
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getInstrInfo
(
)
;
const
auto
&
HRI
=
*
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getRegisterInfo
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
HexagonRegisterAliasInfo
HAI
(
HRI
)
;
TargetOperandInfo
TOI
(
HII
)
;
if
(
RDFDump
)
MF
.
print
(
dbgs
(
)
<<
"Before "
<<
getPassName
(
)
<<
"\n"
,
nullptr
)
;
DataFlowGraph
G
(
MF
,
HII
,
HRI
,
*
MDT
,
MDF
,
HAI
,
TOI
)
;
G
.
build
(
)
;
if
(
RDFDump
)
{
dbgs
(
)
<<
PrintNode
<
FuncNode
*
>
(
G
.
getFunc
(
)
,
G
)
<<
'\n'
;
dbgs
(
)
<<
MF
.
getName
(
)
<<
'\n'
;
}
bool
Changed
;
CopyPropagation
CP
(
G
)
;
CP
.
trace
(
RDFDump
)
;
Changed
=
CP
.
run
(
)
;
if
(
Changed
)
G
.
build
(
)
;
HexagonDCE
DCE
(
G
,
*
MRI
)
;
DCE
.
trace
(
RDFDump
)
;
Changed
|=
DCE
.
run
(
)
;
if
(
Changed
)
{
Liveness
LV
(
*
MRI
,
G
)
;
LV
.
trace
(
RDFDump
)
;
LV
.
computeLiveIns
(
)
;
LV
.
resetLiveIns
(
)
;
LV
.
resetKills
(
)
;
}
if
(
RDFDump
)
MF
.
print
(
dbgs
(
)
<<
"After "
<<
getPassName
(
)
<<
"\n"
,
nullptr
)
;
return
false
;
}
</s>

Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
"Before "
"\n"
Hexagon
"After "
"\n"


<s> unsigned PPCFastISel :: fastMaterializeAlloca ( const AllocaInst * AI ) { if ( ! FuncInfo . StaticAllocaMap . count ( AI ) ) return 0 ; MVT VT ; if ( ! isLoadTypeLegal ( AI -> getType ( ) , VT ) ) return 0 ; DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( AI ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { unsigned ResultReg = createResultReg ( & PPC :: G8RC_and_G8RC_NOX0RegClass ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( PPC :: ADDI8 ) , ResultReg ) . addFrameIndex ( SI -> second ) . addImm ( 0 ) ; return ResultReg ; } return 0 ; } </s>

Emit an alloca address in a register using target-specific logic .


<s> static bool rs6000_real_tls_symbol_ref_p ( rtx x ) { return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) >= TLS_MODEL_REAL ) ; } </s>

Return true if X is a symbol that refers to real ( rather than emulated ) TLS .


<s> bool rs6000_emit_int_cmove ( rtx dest , rtx op , rtx true_cond , rtx false_cond ) { rtx condition_rtx , cr ; machine_mode mode = GET_MODE ( dest ) ; enum rtx_code cond_code ; rtx ( * isel_func ) ( rtx , rtx , rtx , rtx , rtx ) ; bool signedp ; if ( mode != SImode && ( ! TARGET_POWERPC64 || mode != DImode ) ) return false ; if ( GET_MODE_CLASS ( GET_MODE ( XEXP ( op , 0 ) ) ) == MODE_CC ) return false ; condition_rtx = rs6000_generate_compare ( op , mode ) ; cond_code = GET_CODE ( condition_rtx ) ; cr = XEXP ( condition_rtx , 0 ) ; signedp = GET_MODE ( cr ) == CCmode ; isel_func = ( mode == SImode ? ( signedp ? gen_isel_signed_si : gen_isel_unsigned_si ) : ( signedp ? gen_isel_signed_di : gen_isel_unsigned_di ) ) ; switch ( cond_code ) { case LT : case GT : case LTU : case GTU : case EQ : break ; default : { std :: swap ( false_cond , true_cond ) ; PUT_CODE ( condition_rtx , reverse_condition ( cond_code ) ) ; } break ; } false_cond = force_reg ( mode , false_cond ) ; if ( true_cond != const0_rtx ) true_cond = force_reg ( mode , true_cond ) ; emit_insn ( isel_func ( dest , condition_rtx , true_cond , false_cond , cr ) ) ; return true ; } </s>


<s> static int ix86_mode_after ( int entity , int mode , rtx_insn * insn ) { switch ( entity ) { case X86_DIRFLAG : return mode ; case AVX_U128 : return ix86_avx_u128_mode_after ( mode , insn ) ; case I387_ROUNDEVEN : case I387_TRUNC : case I387_FLOOR : case I387_CEIL : return mode ; default : gcc_unreachable ( ) ; } } </s>

Return the mode that an insn results in .


<s> enum mips_loadgp_style mips_current_loadgp_style ( void ) { if ( ! TARGET_USE_GOT || cfun -> machine -> global_pointer == INVALID_REGNUM ) return LOADGP_NONE ; if ( TARGET_RTP_PIC ) return LOADGP_RTP ; if ( TARGET_ABSOLUTE_ABICALLS ) return LOADGP_ABSOLUTE ; return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI ; } </s>

Return the style of GP load sequence that is being used for the current function .


"\tnop // between mem op and mult-accumulate\n"


<s> int arm_split_constant ( enum rtx_code code , enum machine_mode mode , rtx insn , HOST_WIDE_INT val , rtx target , rtx source , int subtargets ) { rtx cond ; if ( insn && GET_CODE ( PATTERN ( insn ) ) == COND_EXEC ) cond = COND_EXEC_TEST ( PATTERN ( insn ) ) ; else cond = NULL_RTX ; if ( subtargets || code == SET || ( GET_CODE ( target ) == REG && GET_CODE ( source ) == REG && REGNO ( target ) != REGNO ( source ) ) ) { if ( ! after_arm_reorg && ! cond && ( arm_gen_constant ( code , mode , NULL_RTX , val , target , source , 1 , 0 ) > arm_constant_limit + ( code != SET ) ) ) { if ( code == SET ) { emit_insn ( gen_rtx_SET ( VOIDmode , target , GEN_INT ( val ) ) ) ; return 1 ; } else { rtx temp = subtargets ? gen_reg_rtx ( mode ) : target ; emit_insn ( gen_rtx_SET ( VOIDmode , temp , GEN_INT ( val ) ) ) ; if ( code == MINUS ) emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_MINUS ( mode , temp , source ) ) ) ; else emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_fmt_ee ( code , mode , source , temp ) ) ) ; return 2 ; } } } return arm_gen_constant ( code , mode , cond , val , target , source , subtargets , 1 ) ; } </s>

Emit a sequence of insns to handle a large constant . CODE is the code of the operation required , it can be any of SET , PLUS , IOR , AND , XOR , MINUS ; MODE is the mode in which the operation is being performed ; VAL is the integer to operate on ; SOURCE is the other operand ( a register , or a null-pointer for SET ) ; SUBTARGETS means it is safe to create scratch registers if that will either produce a simpler sequence , or we will want to cse the values . Return value is the number of insns emitted .


"LC3b DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> void X86PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; addPass ( createX86LowerAMXIntrinsicsPass ( ) ) ; addPass ( createX86LowerAMXTypePass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: None ) addPass ( createX86PreAMXConfigPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedAccessPass ( ) ) ; addPass ( createX86PartialReductionPass ( ) ) ; } addPass ( createIndirectBrExpandPass ( ) ) ; const Triple & TT = TM -> getTargetTriple ( ) ; if ( TT . isOSWindows ( ) ) { if ( TT . getArch ( ) == Triple :: x86_64 ) { addPass ( createCFGuardDispatchPass ( ) ) ; } else { addPass ( createCFGuardCheckPass ( ) ) ; } } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static int set_src_needs_barrier ( rtx x , struct reg_flags flags , int pred ) { int need_barrier = 0 ; rtx dst ; rtx src = SET_SRC ( x ) ; if ( GET_CODE ( src ) == CALL ) return rtx_needs_barrier ( src , flags , pred ) ; else if ( SET_DEST ( x ) == pc_rtx ) { if ( ! ia64_spec_check_src_p ( src ) ) flags . is_branch = 1 ; return rtx_needs_barrier ( src , flags , pred ) ; } if ( ia64_spec_check_src_p ( src ) ) { gcc_assert ( REG_P ( XEXP ( src , 2 ) ) ) ; need_barrier = rtx_needs_barrier ( XEXP ( src , 2 ) , flags , pred ) ; src = XEXP ( src , 1 ) ; } need_barrier |= rtx_needs_barrier ( src , flags , pred ) ; dst = SET_DEST ( x ) ; if ( GET_CODE ( dst ) == ZERO_EXTRACT ) { need_barrier |= rtx_needs_barrier ( XEXP ( dst , 1 ) , flags , pred ) ; need_barrier |= rtx_needs_barrier ( XEXP ( dst , 2 ) , flags , pred ) ; } return need_barrier ; } </s>

Subroutine of rtx_needs_barrier ; this function determines whether the source of a given SET rtx found in X needs a barrier . FLAGS and PRED are as in rtx_needs_barrier . COND is an rtx that holds the condition for this insn .


"Unrecognized Hexagon processor version"

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s>
CCAssignFn
*
AMDGPUTargetLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
{
switch
(
CC
)
{
case
CallingConv
::
C
:
case
CallingConv
::
AMDGPU_KERNEL
:
case
CallingConv
::
SPIR_KERNEL
:
return
CC_AMDGPU_Kernel
;
case
CallingConv
::
AMDGPU_VS
:
case
CallingConv
::
AMDGPU_GS
:
case
CallingConv
::
AMDGPU_PS
:
case
CallingConv
::
AMDGPU_CS
:
return
CC_AMDGPU
;
default
:
report_fatal_error
(
"Unsupported calling convention."
)
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .

AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
"Unsupported calling convention."


"%qE attribute ignored without %<-mistack%>"

"%qE attribute only applies to functions"

Handle an `` interrupt '' or `` isr '' attribute ; arguments as in struct attribute_spec.handler .


<s> bool X86InstrInfo :: analyzeCompare ( const MachineInstr & MI , unsigned & SrcReg , unsigned & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI . getOpcode ( ) ) { default : break ; case X86 :: CMP64ri32 : case X86 :: CMP64ri8 : case X86 :: CMP32ri : case X86 :: CMP32ri8 : case X86 :: CMP16ri : case X86 :: CMP16ri8 : case X86 :: CMP8ri : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 1 ) . getImm ( ) ; return true ; case X86 :: SUB64rm : case X86 :: SUB32rm : case X86 :: SUB16rm : case X86 :: SUB8rm : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case X86 :: SUB64rr : case X86 :: SUB32rr : case X86 :: SUB16rr : case X86 :: SUB8rr : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 2 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case X86 :: SUB64ri32 : case X86 :: SUB64ri8 : case X86 :: SUB32ri : case X86 :: SUB32ri8 : case X86 :: SUB16ri : case X86 :: SUB16ri8 : case X86 :: SUB8ri : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 2 ) . getImm ( ) ; return true ; case X86 :: CMP64rr : case X86 :: CMP32rr : case X86 :: CMP16rr : case X86 :: CMP8rr : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 1 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case X86 :: TEST8rr : case X86 :: TEST16rr : case X86 :: TEST32rr : case X86 :: TEST64rr : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; if ( MI . getOperand ( 1 ) . getReg ( ) != SrcReg ) return false ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> static void or1k_compute_frame_layout ( void ) { HOST_WIDE_INT local_vars_size , args_size , save_reg_size ; local_vars_size = get_frame_size ( ) ; local_vars_size = ROUND_UP ( local_vars_size , UNITS_PER_WORD ) ; args_size = crtl -> outgoing_args_size ; args_size = ROUND_UP ( args_size , UNITS_PER_WORD ) ; save_reg_size = 0 ; for ( int regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( callee_saved_regno_p ( regno ) ) save_reg_size += UNITS_PER_WORD ; cfun -> machine -> local_vars_size = local_vars_size ; cfun -> machine -> args_size = args_size ; cfun -> machine -> callee_saved_reg_size = save_reg_size ; cfun -> machine -> total_size = save_reg_size + local_vars_size + args_size ; } </s>

Worker for TARGET_COMPUTE_FRAME_LAYOUT . Compute and populate machine specific function attributes which are globally accessible via cfun- > machine . These include the sizes needed for stack stored local variables , callee saved registers and space for stack arguments which may be passed to a next function . The values are used for the epilogue , prologue and eliminations . OpenRISC stack grows downwards and contains : -- -- previous frame -- -- -- -- current func arg [ n ] current func arg [ 0 ] < -- r2 [ HFP , AP ] -- -- current stack frame -- - ^ -- -\ return address r9 | | old frame pointer r2 ( + ) | -- machine- > total_size callee saved regs | | > machine- > callee_saved_reg_size local variables | | > machine- > local_vars_size < -FP next function args < -- r1 [ SP ] -- -/ > machine- > args_size -- -- -- -- -- -- -- -- -- -- -- -- -- -- | ( - ) ( future ) | V All of these contents are optional .


"Unexpected data type for Gather/Scatter"

Calculate the cost of Gather / Scatter operation .


<s>
bool
FixupLEAPass
::
runOnMachineFunction
(
MachineFunction
&
Func
)
{
MF
=
&
Func
;
const
X86Subtarget
&
ST
=
Func
.
getSubtarget
<
X86Subtarget
>
(
)
;
if
(
!
ST
.
LEAusesAG
(
)
&&
!
ST
.
slowLEA
(
)
)
return
false
;
TII
=
ST
.
getInstrInfo
(
)
;
DEBUG
(
dbgs
(
)
<<
"Start X86FixupLEAs\n"
;
)
;
for
(
MachineFunction
::
iterator
I
=
Func
.
begin
(
)
,
E
=
Func
.
end
(
)
;
I
!=
E
;
++
I
)
processBasicBlock
(
Func
,
I
)
;
DEBUG
(
dbgs
(
)
<<
"End X86FixupLEAs\n"
;
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


"  Skipping pass: no machine model present.\n"


<s>
SDValue
OR1KTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
CTTZ
:
return
LowerCTTZ
(
Op
,
DAG
)
;
case
ISD
::
CTTZ_ZERO_UNDEF
:
return
LowerCTTZ_ZERO_UNDEF
(
Op
,
DAG
)
;
case
ISD
::
CTLZ
:
case
ISD
::
CTLZ_ZERO_UNDEF
:
return
LowerCTLZ
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
SUBE
:
return
LowerSUBE
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> void MipsOutgoingValueHandler :: assignValueToReg ( Register ValVReg , Register PhysReg , CCValAssign & VA ) { Register ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildCopy ( PhysReg , ExtReg ) ; MIB . addUse ( PhysReg , RegState :: Implicit ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s>
bool
SystemZDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
SystemZAddressingMode
::
AddrForm
Form
;
SystemZAddressingMode
::
DispRange
DispRange
;
SDValue
Base
,
Disp
,
Index
;
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
case
InlineAsm
::
Constraint_Q
:
Form
=
SystemZAddressingMode
::
FormBD
;
DispRange
=
SystemZAddressingMode
::
Disp12Only
;
break
;
case
InlineAsm
::
Constraint_R
:
Form
=
SystemZAddressingMode
::
FormBDXNormal
;
DispRange
=
SystemZAddressingMode
::
Disp12Only
;
break
;
case
InlineAsm
::
Constraint_S
:
Form
=
SystemZAddressingMode
::
FormBD
;
DispRange
=
SystemZAddressingMode
::
Disp20Only
;
break
;
case
InlineAsm
::
Constraint_T
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_o
:
Form
=
SystemZAddressingMode
::
FormBDXNormal
;
DispRange
=
SystemZAddressingMode
::
Disp20Only
;
break
;
}
if
(
selectBDXAddr
(
Form
,
DispRange
,
Op
,
Base
,
Disp
,
Index
)
)
{
const
TargetRegisterClass
*
TRC
=
Subtarget
->
getRegisterInfo
(
)
->
getPointerRegClass
(
*
MF
)
;
SDLoc
DL
(
Base
)
;
SDValue
RC
=
CurDAG
->
getTargetConstant
(
TRC
->
getID
(
)
,
DL
,
MVT
::
i32
)
;
if
(
Base
.
getOpcode
(
)
!=
ISD
::
TargetFrameIndex
&&
Base
.
getOpcode
(
)
!=
ISD
::
Register
)
{
Base
=
SDValue
(
CurDAG
->
getMachineNode
(
TargetOpcode
::
COPY_TO_REGCLASS
,
DL
,
Base
.
getValueType
(
)
,
Base
,
RC
)
,
0
)
;
}
if
(
Index
.
getOpcode
(
)
!=
ISD
::
Register
)
{
Index
=
SDValue
(
CurDAG
->
getMachineNode
(
TargetOpcode
::
COPY_TO_REGCLASS
,
DL
,
Index
.
getValueType
(
)
,
Index
,
RC
)
,
0
)
;
}
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Disp
)
;
OutOps
.
push_back
(
Index
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s>
void
MipsInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
O
,
StringRef
Annot
)
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
Mips
::
RDHWR
:
case
Mips
::
RDHWR64
:
O
<<
"\t.set\tpush\n"
;
O
<<
"\t.set\tmips32r2\n"
;
break
;
case
Mips
::
Save16
:
O
<<
"\tsave\t"
;
printSaveRestore
(
MI
,
O
)
;
O
<<
" # 16 bit inst\n"
;
return
;
case
Mips
::
SaveX16
:
O
<<
"\tsave\t"
;
printSaveRestore
(
MI
,
O
)
;
O
<<
"\n"
;
return
;
case
Mips
::
Restore16
:
O
<<
"\trestore\t"
;
printSaveRestore
(
MI
,
O
)
;
O
<<
" # 16 bit inst\n"
;
return
;
case
Mips
::
RestoreX16
:
O
<<
"\trestore\t"
;
printSaveRestore
(
MI
,
O
)
;
O
<<
"\n"
;
return
;
}
if
(
!
printAliasInstr
(
MI
,
O
)
&&
!
printAlias
(
*
MI
,
O
)
)
printInstruction
(
MI
,
O
)
;
printAnnotation
(
O
,
Annot
)
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
Mips
::
RDHWR
:
case
Mips
::
RDHWR64
:
O
<<
"\n\t.set\tpop"
;
}
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s> unsigned PPCTargetLowering :: getPrefLoopAlignment ( MachineLoop * ML ) const { switch ( Subtarget . getDarwinDirective ( ) ) { default : break ; case PPC :: DIR_970 : case PPC :: DIR_PWR4 : case PPC :: DIR_PWR5 : case PPC :: DIR_PWR5X : case PPC :: DIR_PWR6 : case PPC :: DIR_PWR6X : case PPC :: DIR_PWR7 : case PPC :: DIR_PWR8 : case PPC :: DIR_PWR9 : { if ( ! ML ) break ; const PPCInstrInfo * TII = Subtarget . getInstrInfo ( ) ; uint64_t LoopSize = 0 ; for ( auto I = ML -> block_begin ( ) , IE = ML -> block_end ( ) ; I != IE ; ++ I ) for ( auto J = ( * I ) -> begin ( ) , JE = ( * I ) -> end ( ) ; J != JE ; ++ J ) { LoopSize += TII -> GetInstSizeInBytes ( * J ) ; if ( LoopSize > 32 ) break ; } if ( LoopSize > 16 && LoopSize <= 32 ) return 5 ; break ; } } return TargetLowering :: getPrefLoopAlignment ( ML ) ; } </s>


"Can only merge with a valid VSETVLInfo"


<s> static bool convertible_comparison_p ( rtx_insn * insn , enum machine_mode mode ) { if ( TARGET_64BIT || mode != DImode ) return false ; if ( ! TARGET_SSE4_1 ) return false ; rtx def_set = single_set ( insn ) ; gcc_assert ( def_set ) ; rtx src = SET_SRC ( def_set ) ; rtx dst = SET_DEST ( def_set ) ; gcc_assert ( GET_CODE ( src ) == COMPARE ) ; if ( GET_CODE ( dst ) != REG || REGNO ( dst ) != FLAGS_REG || GET_MODE ( dst ) != CCZmode ) return false ; rtx op1 = XEXP ( src , 0 ) ; rtx op2 = XEXP ( src , 1 ) ; if ( op2 != CONST0_RTX ( GET_MODE ( op2 ) ) ) return false ; if ( GET_CODE ( op1 ) != IOR ) return false ; op2 = XEXP ( op1 , 1 ) ; op1 = XEXP ( op1 , 0 ) ; if ( ! SUBREG_P ( op1 ) || ! SUBREG_P ( op2 ) || GET_MODE ( op1 ) != SImode || GET_MODE ( op2 ) != SImode || ( ( SUBREG_BYTE ( op1 ) != 0 || SUBREG_BYTE ( op2 ) != GET_MODE_SIZE ( SImode ) ) && ( SUBREG_BYTE ( op2 ) != 0 || SUBREG_BYTE ( op1 ) != GET_MODE_SIZE ( SImode ) ) ) ) return false ; op1 = SUBREG_REG ( op1 ) ; op2 = SUBREG_REG ( op2 ) ; if ( op1 != op2 || ! REG_P ( op1 ) || GET_MODE ( op1 ) != DImode ) return false ; return true ; } </s>

Check if comparison INSN may be transformed into vector comparison . Currently we transform equality/inequality checks which look like : ( set ( reg : CCZ 17 flags ) ( compare : CCZ ( reg : TI x ) ( reg : TI y ) ) )


"%<fast_interrupt%> attribute directive ignored"

Likewise , for the epilogue . The only exception is that , for interrupts , we must manually unwind the frame as the REIT opcode does n't do that .


<s> bool AArch64LoadStoreOpt :: isCandidateToMergeOrPair ( MachineInstr * MI ) { if ( MI -> hasOrderedMemoryRef ( ) ) return false ; if ( ! getLdStOffsetOp ( MI ) . isImm ( ) ) return false ; unsigned BaseReg = getLdStBaseOp ( MI ) . getReg ( ) ; if ( MI -> modifiesRegister ( BaseReg , TRI ) ) return false ; if ( TII -> isLdStPairSuppressed ( MI ) ) return false ; return true ; } </s>

Return true if this is a load/store that can be potentially paired/merged .


<s> static SDNode * getInt64 ( SelectionDAG * CurDAG , const SDLoc & dl , int64_t Imm ) { unsigned Count = getInt64CountDirect ( Imm ) ; if ( Count == 1 ) return getInt64Direct ( CurDAG , dl , Imm ) ; unsigned RMin = 0 ; int64_t MatImm ; unsigned MaskEnd ; for ( unsigned r = 1 ; r < 63 ; ++ r ) { uint64_t RImm = Rot64 ( Imm , r ) ; unsigned RCount = getInt64CountDirect ( RImm ) + 1 ; if ( RCount < Count ) { Count = RCount ; RMin = r ; MatImm = RImm ; MaskEnd = 63 ; } unsigned LS = findLastSet ( RImm ) ; if ( LS != r - 1 ) continue ; uint64_t OnesMask = - ( int64_t ) ( UINT64_C ( 1 ) << ( LS + 1 ) ) ; uint64_t RImmWithOnes = RImm | OnesMask ; RCount = getInt64CountDirect ( RImmWithOnes ) + 1 ; if ( RCount < Count ) { Count = RCount ; RMin = r ; MatImm = RImmWithOnes ; MaskEnd = LS ; } } if ( ! RMin ) return getInt64Direct ( CurDAG , dl , Imm ) ; auto getI32Imm = [ CurDAG , dl ] ( unsigned Imm ) { return CurDAG -> getTargetConstant ( Imm , dl , MVT :: i32 ) ; } ; SDValue Val = SDValue ( getInt64Direct ( CurDAG , dl , MatImm ) , 0 ) ; return CurDAG -> getMachineNode ( PPC :: RLDICR , dl , MVT :: i64 , Val , getI32Imm ( 64 - RMin ) , getI32Imm ( MaskEnd ) ) ; } </s>


<s>
unsigned
getReg
(
)
const
override
{
assert
(
Kind
==
k_Register
&&
"Invalid access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s> EVT HexagonTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , const AttributeList & FuncAttributes ) const { auto Aligned = [ ] ( unsigned GivenA , unsigned MinA ) -> bool { return ( GivenA % MinA ) == 0 ; } ; if ( Size >= 8 && Aligned ( DstAlign , 8 ) && ( IsMemset || Aligned ( SrcAlign , 8 ) ) ) return MVT :: i64 ; if ( Size >= 4 && Aligned ( DstAlign , 4 ) && ( IsMemset || Aligned ( SrcAlign , 4 ) ) ) return MVT :: i32 ; if ( Size >= 2 && Aligned ( DstAlign , 2 ) && ( IsMemset || Aligned ( SrcAlign , 2 ) ) ) return MVT :: i16 ; return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> bool GBZ80TargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { EVT VT ; SDLoc DL ( N ) ; if ( const LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; if ( LD -> getExtensionType ( ) != ISD :: NON_EXTLOAD ) return false ; } else if ( const StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; } else { return false ; } if ( VT != MVT :: i8 ) { return false ; } if ( Op -> getOpcode ( ) != ISD :: ADD && Op -> getOpcode ( ) != ISD :: SUB ) { return false ; } if ( const ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ) { int RHSC = RHS -> getSExtValue ( ) ; if ( Op -> getOpcode ( ) == ISD :: SUB ) RHSC = - RHSC ; if ( RHSC == 1 ) { Base = Op -> getOperand ( 0 ) ; Offset = DAG . getConstant ( RHSC , DL , MVT :: i16 ) ; AM = ISD :: POST_INC ; return true ; } else if ( RHSC == - 1 ) { Base = Op -> getOperand ( 0 ) ; Offset = DAG . getConstant ( RHSC , DL , MVT :: i16 ) ; AM = ISD :: POST_DEC ; return true ; } } return false ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .


<s> static void cr16_compute_save_regs ( void ) { unsigned int regno ; current_frame_info . last_reg_to_save = - 1 ; current_frame_info . reg_size = 0 ; if ( FUNC_IS_NORETURN_P ( current_function_decl ) && ! MUST_SAVE_REGS_P ( ) ) return ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) { if ( fixed_regs [ regno ] ) { current_frame_info . save_regs [ regno ] = 0 ; continue ; } if ( cr16_interrupt_function_p ( ) ) { if ( ! crtl -> is_leaf && call_used_or_fixed_reg_p ( regno ) ) current_frame_info . save_regs [ regno ] = 1 ; else if ( df_regs_ever_live_p ( regno ) ) current_frame_info . save_regs [ regno ] = 1 ; else current_frame_info . save_regs [ regno ] = 0 ; } else { if ( df_regs_ever_live_p ( regno ) && ( ! call_used_or_fixed_reg_p ( regno ) || regno == RETURN_ADDRESS_REGNUM ) ) current_frame_info . save_regs [ regno ] = 1 ; else current_frame_info . save_regs [ regno ] = 0 ; } } if ( crtl -> calls_eh_return ) { unsigned int i ; for ( i = 0 ; ; ++ i ) { regno = EH_RETURN_DATA_REGNO ( i ) ; if ( INVALID_REGNUM == regno ) break ; current_frame_info . save_regs [ regno ] = 1 ; } } for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( current_frame_info . save_regs [ regno ] == 1 ) { current_frame_info . last_reg_to_save = regno ; if ( regno >= CR16_FIRST_DWORD_REGISTER ) current_frame_info . reg_size += CR16_UNITS_PER_DWORD ; else current_frame_info . reg_size += UNITS_PER_WORD ; } } </s>

Compute values for the array current_frame_info.save_regs and the variable current_frame_info.reg_size . The index of current_frame_info.save_regs is numbers of register , each will get 1 if we need to save it in the current function , 0 if not . current_frame_info.reg_size is the total sum of the registers being saved .


<s> MCExpr const & HexagonMCInstrInfo :: getExpr ( MCExpr const & Expr ) { const auto & HExpr = cast < HexagonMCExpr > ( Expr ) ; assert ( HExpr . getExpr ( ) ) ; return * HExpr . getExpr ( ) ; } </s>

Implementation of the SCEVPredicate interface .


<s>
bool
ARMBaseInstrInfo
::
getExtractSubregLikeInputs
(
const
MachineInstr
&
MI
,
unsigned
DefIdx
,
RegSubRegPairAndIdx
&
InputReg
)
const
{
assert
(
DefIdx
<
MI
.
getDesc
(
)
.
getNumDefs
(
)
&&
"Invalid definition index"
)
;
assert
(
MI
.
isExtractSubregLike
(
)
&&
"Invalid kind of instruction"
)
;
switch
(
MI
.
getOpcode
(
)
)
{
case
ARM
::
VMOVRRD
:
const
MachineOperand
&
MOReg
=
MI
.
getOperand
(
2
)
;
if
(
MOReg
.
isUndef
(
)
)
return
false
;
InputReg
.
Reg
=
MOReg
.
getReg
(
)
;
InputReg
.
SubReg
=
MOReg
.
getSubReg
(
)
;
InputReg
.
SubIdx
=
DefIdx
==
0
ARM
::
ssub_0
:
ARM
::
ssub_1
;
return
true
;
}
llvm_unreachable
(
"Target dependent opcode missing"
)
;
}
</s>

Target-dependent implementation of getExtractSubregInputs .


<s> const char * Nios2TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case Nios2ISD :: Hi : return "Nios2ISD::Hi" ; case Nios2ISD :: Lo : return "Nios2ISD::Lo" ; case Nios2ISD :: Ret : return "Nios2ISD::Ret" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> bool nds32_rtx_costs_impl ( rtx x , int code , int outer_code , int opno ATTRIBUTE_UNUSED , int * total , bool speed ) { if ( speed ) goto performance_cost ; else goto size_cost ; performance_cost : switch ( code ) { case SET : return false ; case USE : * total = 0 ; break ; case MULT : * total = COSTS_N_INSNS ( 1 ) ; break ; case DIV : case UDIV : case MOD : case UMOD : * total = COSTS_N_INSNS ( 7 ) ; break ; default : * total = COSTS_N_INSNS ( 1 ) ; break ; } return true ; size_cost : switch ( code ) { case SET : return false ; case USE : * total = 0 ; break ; case CONST_INT : if ( outer_code == SET ) { if ( satisfies_constraint_Is05 ( x ) ) * total = COSTS_N_INSNS ( 1 ) - 2 ; else if ( satisfies_constraint_Is20 ( x ) ) * total = COSTS_N_INSNS ( 1 ) ; else * total = COSTS_N_INSNS ( 2 ) ; } else if ( outer_code == PLUS || outer_code == MINUS ) { if ( satisfies_constraint_Iu05 ( x ) ) * total = COSTS_N_INSNS ( 1 ) - 2 ; else * total = COSTS_N_INSNS ( 1 ) ; } else if ( outer_code == ASHIFT ) { if ( satisfies_constraint_Iu03 ( x ) ) * total = COSTS_N_INSNS ( 1 ) - 2 ; else * total = COSTS_N_INSNS ( 1 ) ; } else if ( outer_code == ASHIFTRT || outer_code == LSHIFTRT ) { if ( satisfies_constraint_Iu05 ( x ) ) * total = COSTS_N_INSNS ( 1 ) - 2 ; else * total = COSTS_N_INSNS ( 1 ) ; } else { * total = COSTS_N_INSNS ( 1 ) ; } break ; case CONST_DOUBLE : * total = COSTS_N_INSNS ( 2 ) ; break ; default : * total = COSTS_N_INSNS ( 1 ) ; break ; } return true ; } </s>

This target hook describes the relative costs of RTL expressions . Return 'true ' when all subexpressions of x have been processed . Return 'false ' to sum the costs of sub-rtx , plus cost of this operation . Refer to gcc/rtlanal.cc for more information .