<s>
BitVector
HSAILRegisterInfo
::
getReservedRegs
(
const
MachineFunction
&
MF
)
const
{
BitVector
Reserved
(
getNumRegs
(
)
)
;
HSAILMachineFunctionInfo
*
MFI
=
const_cast
<
HSAILMachineFunctionInfo
*
>
(
MF
.
getInfo
<
HSAILMachineFunctionInfo
>
(
)
)
;
unsigned
NumSlotsTotal
=
HSAIL
::
GPR64RegClass
.
getNumRegs
(
)
;
unsigned
RegSlots
=
NumSlotsTotal
/
2
;
if
(
MFI
->
getRegisterPartitioning
(
)
==
0
)
{
const
MachineRegisterInfo
&
RI
=
MF
.
getRegInfo
(
)
;
unsigned
rc32
=
0
,
rc64
=
0
;
for
(
unsigned
i
=
0
,
e
=
RI
.
getNumVirtRegs
(
)
;
i
!=
e
;
++
i
)
{
switch
(
RI
.
getRegClass
(
index2VirtReg
(
i
)
)
->
getSize
(
)
)
{
case
4
:
rc32
++
;
break
;
case
8
:
rc64
++
;
break
;
}
}
if
(
HSAILRegSlots
>
0
)
{
RegSlots
=
HSAILRegSlots
;
}
else
{
if
(
rc64
<
(
NumSlotsTotal
RegSlots
)
&&
rc32
>
(
RegSlots
*
2
)
)
{
RegSlots
=
NumSlotsTotal
rc64
;
}
else
if
(
rc32
<
(
RegSlots
*
2
)
&&
rc64
>
(
NumSlotsTotal
RegSlots
)
)
{
RegSlots
=
(
rc32
+
1
)
/
2
;
}
}
if
(
RegSlots
<
8
)
RegSlots
=
8
;
else
if
(
RegSlots
>
(
NumSlotsTotal
8
)
)
RegSlots
=
NumSlotsTotal
8
;
MFI
->
setRegisterPartitioning
(
RegSlots
)
;
DEBUG
(
dbgs
(
)
<<
"\nFunction: "
<<
MF
.
getFunction
(
)
->
getName
(
)
<<
" VR count: 32 bit = "
<<
rc32
<<
", 64 bit = "
<<
rc64
<<
", register file partitioning: "
<<
RegSlots
*
2
<<
" $s + "
<<
NumSlotsTotal
RegSlots
<<
" $d\n\n"
)
;
}
else
{
RegSlots
=
MFI
->
getRegisterPartitioning
(
)
;
}
unsigned
Reg
;
unsigned
LastSReg
=
HSAIL
::
S0
+
HSAIL
::
GPR32RegClass
.
getNumRegs
(
)
1
;
for
(
Reg
=
HSAIL
::
S0
+
RegSlots
*
2
;
Reg
<=
LastSReg
;
++
Reg
)
{
Reserved
.
set
(
Reg
)
;
}
unsigned
LastDReg
=
HSAIL
::
D0
+
HSAIL
::
GPR64RegClass
.
getNumRegs
(
)
1
;
for
(
Reg
=
HSAIL
::
D0
+
(
NumSlotsTotal
RegSlots
)
;
Reg
<=
LastDReg
;
++
Reg
)
{
Reserved
.
set
(
Reg
)
;
}
return
Reserved
;
}
</s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
StringRef
getPassName
(
)
const
override
{
return
"WebAssembly Argument Move"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> MCInst RISCVInstrInfo :: getNop ( ) const { if ( STI . getFeatureBits ( ) [ RISCV :: FeatureStdExtC ] ) return MCInstBuilder ( RISCV :: C_NOP ) ; return MCInstBuilder ( RISCV :: ADDI ) . addReg ( RISCV :: X0 ) . addReg ( RISCV :: X0 ) . addImm ( 0 ) ; } </s>

Return the noop instruction to use for a noop .


<s> const char * output_branch ( int logic , rtx_insn * insn , rtx * operands ) { switch ( get_attr_length ( insn ) ) { case 6 : if ( ! TARGET_RELAX ) { int label = lf ++ ; rtx op0 = operands [ 0 ] ; if ( final_sequence && ! INSN_ANNULLED_BRANCH_P ( final_sequence -> insn ( 0 ) ) && get_attr_length ( final_sequence -> insn ( 1 ) ) ) { asm_fprintf ( asm_out_file , "\tb%s%ss\t%LLF%d\n" , logic ? "f" : "t" , ASSEMBLER_DIALECT ? "/" : "." , label ) ; print_slot ( final_sequence ) ; } else asm_fprintf ( asm_out_file , "\tb%s\t%LLF%d\n" , logic ? "f" : "t" , label ) ; output_asm_insn ( "bra\t%l0" , & op0 ) ; fprintf ( asm_out_file , "\tnop\n" ) ; ( * targetm . asm_out . internal_label ) ( asm_out_file , "LF" , label ) ; return "" ; } case 2 : return logic ? "bt%.\t%l0" : "bf%.\t%l0" ; case 8 : if ( ! TARGET_RELAX ) { int label = lf ++ ; gcc_assert ( ! final_sequence || ! ( INSN_ANNULLED_BRANCH_P ( XVECEXP ( final_sequence , 0 , 0 ) ) ) ) ; asm_fprintf ( asm_out_file , "b%s%ss\t%LLF%d\n" , logic ? "f" : "t" , ASSEMBLER_DIALECT ? "/" : "." , label ) ; fprintf ( asm_out_file , "\tnop\n" ) ; output_asm_insn ( "bra\t%l0" , operands ) ; fprintf ( asm_out_file , "\tnop\n" ) ; ( * targetm . asm_out . internal_label ) ( asm_out_file , "LF" , label ) ; return "" ; } case 4 : { char buffer [ 10 ] ; sprintf ( buffer , "b%s%ss\t%%l0" , logic ? "t" : "f" , ASSEMBLER_DIALECT ? "/" : "." ) ; output_asm_insn ( buffer , & operands [ 0 ] ) ; return "nop" ; } default : gcc_unreachable ( ) ; } } </s>

Output a conditional/unconditional branch to LABEL . COND is the string condition . INSN is the instruction .


<s> bool isReg ( ) const { return Kind == Register ; } </s>


<s> bool VEAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , O ) ; case 'r' : case 'v' : break ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> bool ARMPreAllocLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { if ( AssumeMisalignedLoadStores || skipFunction ( * Fn . getFunction ( ) ) ) return false ; TD = & Fn . getDataLayout ( ) ; STI = & static_cast < const ARMSubtarget & > ( Fn . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; MF = & Fn ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; bool Modified = false ; for ( MachineBasicBlock & MFI : Fn ) Modified |= RescheduleLoadStoreInstrs ( & MFI ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> SDNode * MBlazeDAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI -> getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static rtx emit_multi_reg_push ( unsigned long mask , unsigned long dwarf_regs_mask ) { int num_regs = 0 ; int num_dwarf_regs = 0 ; int i , j ; rtx par ; rtx dwarf ; int dwarf_par_index ; rtx tmp , reg ; dwarf_regs_mask &= ~ ( 1 << PC_REGNUM ) ; for ( i = 0 ; i <= LAST_ARM_REGNUM ; i ++ ) { if ( mask & ( 1 << i ) ) num_regs ++ ; if ( dwarf_regs_mask & ( 1 << i ) ) num_dwarf_regs ++ ; } gcc_assert ( num_regs && num_regs <= 16 ) ; gcc_assert ( ( dwarf_regs_mask & ~ mask ) == 0 ) ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs ) ) ; dwarf = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( num_dwarf_regs + 1 ) ) ; dwarf_par_index = 1 ; for ( i = 0 ; i <= LAST_ARM_REGNUM ; i ++ ) { if ( mask & ( 1 << i ) ) { reg = gen_rtx_REG ( SImode , i ) ; XVECEXP ( par , 0 , 0 ) = gen_rtx_SET ( gen_frame_mem ( BLKmode , gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - 4 * num_regs ) ) ) , gen_rtx_UNSPEC ( BLKmode , gen_rtvec ( 1 , reg ) , UNSPEC_PUSH_MULT ) ) ; if ( dwarf_regs_mask & ( 1 << i ) ) { tmp = gen_rtx_SET ( gen_frame_mem ( SImode , stack_pointer_rtx ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , dwarf_par_index ++ ) = tmp ; } break ; } } for ( j = 1 , i ++ ; j < num_regs ; i ++ ) { if ( mask & ( 1 << i ) ) { reg = gen_rtx_REG ( SImode , i ) ; XVECEXP ( par , 0 , j ) = gen_rtx_USE ( VOIDmode , reg ) ; if ( dwarf_regs_mask & ( 1 << i ) ) { tmp = gen_rtx_SET ( gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , 4 * j ) ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , dwarf_par_index ++ ) = tmp ; } j ++ ; } } par = emit_insn ( par ) ; tmp = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - 4 * num_regs ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , 0 ) = tmp ; add_reg_note ( par , REG_FRAME_RELATED_EXPR , dwarf ) ; return par ; } </s>

Generate and emit an insn that we will recognize as a push_multi . Unfortunately , since this insn does not reflect very well the actual semantics of the operation , we need to annotate the insn for the benefit of DWARF2 frame unwind information .


<s>
SDValue
MMIXTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
report_fatal_error
(
"unimplemented operand"
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
LowerSELECT
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

MMIX
MMIX
"unimplemented operand"
ISD::GlobalAddress
ISD::SELECT


<s>
bool
MCS51ExpandPseudo
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
bool
Modified
=
false
;
const
MCS51Subtarget
&
STI
=
MF
.
getSubtarget
<
MCS51Subtarget
>
(
)
;
TRI
=
STI
.
getRegisterInfo
(
)
;
TII
=
STI
.
getInstrInfo
(
)
;
MF
.
getProperties
(
)
.
set
(
MachineFunctionProperties
::
Property
::
TracksLiveness
)
;
for
(
Block
&
MBB
:
MF
)
{
bool
ContinueExpanding
=
true
;
unsigned
ExpandCount
=
0
;
do
{
assert
(
ExpandCount
<
10
&&
"pseudo expand limit reached"
)
;
bool
BlockModified
=
expandMBB
(
MBB
)
;
Modified
|=
BlockModified
;
ExpandCount
++
;
ContinueExpanding
=
BlockModified
;
}
while
(
ContinueExpanding
)
;
}
return
Modified
;
}
</s>


"Unexpected Kind in getPointerRegClass!"

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> bool PPCTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { switch ( Intrinsic ) { case Intrinsic :: ppc_altivec_lvx : case Intrinsic :: ppc_altivec_lvxl : case Intrinsic :: ppc_altivec_lvebx : case Intrinsic :: ppc_altivec_lvehx : case Intrinsic :: ppc_altivec_lvewx : case Intrinsic :: ppc_vsx_lxvd2x : case Intrinsic :: ppc_vsx_lxvw4x : case Intrinsic :: ppc_vsx_lxvd2x_be : case Intrinsic :: ppc_vsx_lxvw4x_be : case Intrinsic :: ppc_vsx_lxvl : case Intrinsic :: ppc_vsx_lxvll : { EVT VT ; switch ( Intrinsic ) { case Intrinsic :: ppc_altivec_lvebx : VT = MVT :: i8 ; break ; case Intrinsic :: ppc_altivec_lvehx : VT = MVT :: i16 ; break ; case Intrinsic :: ppc_altivec_lvewx : VT = MVT :: i32 ; break ; case Intrinsic :: ppc_vsx_lxvd2x : case Intrinsic :: ppc_vsx_lxvd2x_be : VT = MVT :: v2f64 ; break ; default : VT = MVT :: v4i32 ; break ; } Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = VT ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = - VT . getStoreSize ( ) + 1 ; Info . size = 2 * VT . getStoreSize ( ) - 1 ; Info . align = Align ( 1 ) ; Info . flags = MachineMemOperand :: MOLoad ; return true ; } case Intrinsic :: ppc_altivec_stvx : case Intrinsic :: ppc_altivec_stvxl : case Intrinsic :: ppc_altivec_stvebx : case Intrinsic :: ppc_altivec_stvehx : case Intrinsic :: ppc_altivec_stvewx : case Intrinsic :: ppc_vsx_stxvd2x : case Intrinsic :: ppc_vsx_stxvw4x : case Intrinsic :: ppc_vsx_stxvd2x_be : case Intrinsic :: ppc_vsx_stxvw4x_be : case Intrinsic :: ppc_vsx_stxvl : case Intrinsic :: ppc_vsx_stxvll : { EVT VT ; switch ( Intrinsic ) { case Intrinsic :: ppc_altivec_stvebx : VT = MVT :: i8 ; break ; case Intrinsic :: ppc_altivec_stvehx : VT = MVT :: i16 ; break ; case Intrinsic :: ppc_altivec_stvewx : VT = MVT :: i32 ; break ; case Intrinsic :: ppc_vsx_stxvd2x : case Intrinsic :: ppc_vsx_stxvd2x_be : VT = MVT :: v2f64 ; break ; default : VT = MVT :: v4i32 ; break ; } Info . opc = ISD :: INTRINSIC_VOID ; Info . memVT = VT ; Info . ptrVal = I . getArgOperand ( 1 ) ; Info . offset = - VT . getStoreSize ( ) + 1 ; Info . size = 2 * VT . getStoreSize ( ) - 1 ; Info . align = Align ( 1 ) ; Info . flags = MachineMemOperand :: MOStore ; return true ; } default : break ; } return false ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s>
bool
SITargetLowering
::
isLegalAddressingMode
(
const
AddrMode
&
AM
,
Type
*
Ty
,
unsigned
AS
)
const
{
if
(
AM
.
BaseGV
)
return
false
;
switch
(
AS
)
{
case
AMDGPUAS
::
GLOBAL_ADDRESS
:
case
AMDGPUAS
::
CONSTANT_ADDRESS
:
case
AMDGPUAS
::
PRIVATE_ADDRESS
:
case
AMDGPUAS
::
UNKNOWN_ADDRESS_SPACE
:
{
if
(
!
isUInt
<
12
>
(
AM
.
BaseOffs
)
)
return
false
;
switch
(
AM
.
Scale
)
{
case
0
:
return
true
;
case
1
:
return
true
;
case
2
:
if
(
AM
.
HasBaseReg
)
{
return
false
;
}
return
true
;
default
:
return
false
;
}
}
case
AMDGPUAS
::
LOCAL_ADDRESS
:
case
AMDGPUAS
::
REGION_ADDRESS
:
{
if
(
!
isUInt
<
16
>
(
AM
.
BaseOffs
)
)
return
false
;
if
(
AM
.
Scale
==
0
)
return
true
;
if
(
AM
.
Scale
==
1
&&
AM
.
HasBaseReg
)
return
true
;
return
false
;
}
case
AMDGPUAS
::
FLAT_ADDRESS
:
{
return
AM
.
BaseOffs
==
0
&&
(
AM
.
Scale
==
0
||
AM
.
Scale
==
1
)
;
}
default
:
llvm_unreachable
(
"unhandled address space"
)
;
}
}
</s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> static parallel * nvptx_find_par ( bb_insn_map_t * map , parallel * par , basic_block block ) { if ( block -> flags & BB_VISITED ) return par ; block -> flags |= BB_VISITED ; if ( rtx_insn * * endp = map -> get ( block ) ) { rtx_insn * end = * endp ; switch ( recog_memoized ( end ) ) { case CODE_FOR_return : return par ; case CODE_FOR_nvptx_forked : { unsigned mask = UINTVAL ( XVECEXP ( PATTERN ( end ) , 0 , 0 ) ) ; gcc_assert ( mask ) ; par = new parallel ( par , mask ) ; par -> forked_block = block ; par -> forked_insn = end ; if ( ! ( mask & GOMP_DIM_MASK ( GOMP_DIM_MAX ) ) && ( mask & GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ) ) par -> fork_insn = nvptx_discover_pre ( block , CODE_FOR_nvptx_fork ) ; } break ; case CODE_FOR_nvptx_join : { unsigned mask = UINTVAL ( XVECEXP ( PATTERN ( end ) , 0 , 0 ) ) ; gcc_assert ( par -> mask == mask ) ; par -> join_block = block ; par -> join_insn = end ; if ( ! ( mask & GOMP_DIM_MASK ( GOMP_DIM_MAX ) ) && ( mask & GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ) ) par -> joining_insn = nvptx_discover_pre ( block , CODE_FOR_nvptx_joining ) ; par = par -> parent ; } break ; default : gcc_unreachable ( ) ; } } if ( par ) par -> blocks . safe_push ( block ) ; else par = new parallel ( 0 , 0 ) ; edge e ; edge_iterator ei ; FOR_EACH_EDGE ( e , ei , block -> succs ) nvptx_find_par ( map , par , e -> dest ) ; return par ; } </s>

See also 'gcc/omp-oacc-neuter-broadcast.cc : omp_sese_find_par ' .


<s>
TargetTransformInfo
::
PopcntSupportKind
X86TTIImpl
::
getPopcntSupport
(
unsigned
TyWidth
)
{
assert
(
isPowerOf2_32
(
TyWidth
)
&&
"Ty width must be power of 2"
)
;
return
ST
->
hasPOPCNT
(
)
TTI
::
PSK_FastHardware
:
TTI
::
PSK_Software
;
}
</s>

Return hardware support for population count .


<s> const MCPhysReg * HexagonRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const MCPhysReg CalleeSavedRegsV3 [ ] = { Hexagon :: R16 , Hexagon :: R17 , Hexagon :: R18 , Hexagon :: R19 , Hexagon :: R20 , Hexagon :: R21 , Hexagon :: R22 , Hexagon :: R23 , Hexagon :: R24 , Hexagon :: R25 , Hexagon :: R26 , Hexagon :: R27 , 0 } ; static const MCPhysReg CalleeSavedRegsV3EHReturn [ ] = { Hexagon :: R0 , Hexagon :: R1 , Hexagon :: R2 , Hexagon :: R3 , Hexagon :: R16 , Hexagon :: R17 , Hexagon :: R18 , Hexagon :: R19 , Hexagon :: R20 , Hexagon :: R21 , Hexagon :: R22 , Hexagon :: R23 , Hexagon :: R24 , Hexagon :: R25 , Hexagon :: R26 , Hexagon :: R27 , 0 } ; bool HasEHReturn = MF -> getInfo < HexagonMachineFunctionInfo > ( ) -> hasEHReturn ( ) ; return HasEHReturn ? CalleeSavedRegsV3EHReturn : CalleeSavedRegsV3 ; } </s>


<s> bool SystemZTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { return Imm . isZero ( ) || Imm . isNegZero ( ) ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> void XCoreTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; DataSection = MCSectionXCore :: Create ( ".dp.data" , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_ALLOC | MCSectionELF :: SHF_WRITE | MCSectionXCore :: SHF_DP_SECTION , SectionKind :: getDataRel ( ) , false , getContext ( ) ) ; BSSSection = MCSectionXCore :: Create ( ".dp.bss" , MCSectionELF :: SHT_NOBITS , MCSectionELF :: SHF_ALLOC | MCSectionELF :: SHF_WRITE | MCSectionXCore :: SHF_DP_SECTION , SectionKind :: getBSS ( ) , false , getContext ( ) ) ; MergeableConst4Section = MCSectionXCore :: Create ( ".cp.rodata.cst4" , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_ALLOC | MCSectionELF :: SHF_MERGE | MCSectionXCore :: SHF_CP_SECTION , SectionKind :: getMergeableConst4 ( ) , false , getContext ( ) ) ; MergeableConst8Section = MCSectionXCore :: Create ( ".cp.rodata.cst8" , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_ALLOC | MCSectionELF :: SHF_MERGE | MCSectionXCore :: SHF_CP_SECTION , SectionKind :: getMergeableConst8 ( ) , false , getContext ( ) ) ; MergeableConst16Section = MCSectionXCore :: Create ( ".cp.rodata.cst16" , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_ALLOC | MCSectionELF :: SHF_MERGE | MCSectionXCore :: SHF_CP_SECTION , SectionKind :: getMergeableConst16 ( ) , false , getContext ( ) ) ; TLSDataSection = DataSection ; TLSBSSSection = BSSSection ; if ( TM . getSubtarget < XCoreSubtarget > ( ) . isXS1A ( ) ) ReadOnlySection = MCSectionXCore :: Create ( ".dp.rodata" , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_ALLOC | MCSectionELF :: SHF_WRITE | MCSectionXCore :: SHF_DP_SECTION , SectionKind :: getDataRel ( ) , false , getContext ( ) ) ; else ReadOnlySection = MCSectionXCore :: Create ( ".cp.rodata" , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_ALLOC | MCSectionXCore :: SHF_CP_SECTION , SectionKind :: getReadOnlyWithRel ( ) , false , getContext ( ) ) ; DataRelSection = DataRelLocalSection = DataSection ; DataRelROSection = DataRelROLocalSection = ReadOnlySection ; } </s>

This method must be called before any actual lowering is done .

XCore XCore XCore ".dp.data" XCore XCore ".dp.bss" XCore XCore ".cp.rodata.cst4" XCore XCore ".cp.rodata.cst8" XCore XCore ".cp.rodata.cst16" XCore XCore XCore ".dp.rodata" XCore XCore ".cp.rodata" XCore


<s> bool SIInstrInfo :: isInlineConstant ( const MachineOperand & MO ) const { if ( MO . isImm ( ) ) return isInlineConstant ( APInt ( 32 , MO . getImm ( ) , true ) ) ; return false ; } </s>

returns true if the operand OpIdx in MI is a valid inline immediate .


<s> XCoreSubtarget :: XCoreSubtarget ( const std :: string & TT , const std :: string & FS ) : IsXS1A ( false ) , IsXS1B ( false ) { std :: string CPU = "xs1a-generic" ; ParseSubtargetFeatures ( FS , CPU ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> static rtx gen_tlsmoff ( rtx addr , rtx reg ) { rtx dest = gen_reg_rtx ( Pmode ) ; if ( TARGET_BIG_TLS ) { dest = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_tlsoff_hilo ( dest , addr , GEN_INT ( R_FRV_TLSMOFFHI ) ) ) ; dest = gen_rtx_PLUS ( Pmode , dest , reg ) ; } else { dest = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_symGOTOFF2reg_i ( dest , addr , reg , GEN_INT ( R_FRV_TLSMOFF12 ) ) ) ; } return dest ; } </s>

Emit a TLSMOFF or TLSMOFF12 offset , depending on -mTLS . Returns the destination address .


<s> bool isMachineVerifierClean ( ) const override { return false ; } </s>

Returns true if the target is expected to pass all machine verifier checks .


<s>
SDValue
RISCVTargetLowering
::
getAddr
(
NodeTy
*
N
,
SelectionDAG
&
DAG
,
bool
IsLocal
)
const
{
SDLoc
DL
(
N
)
;
EVT
Ty
=
getPointerTy
(
DAG
.
getDataLayout
(
)
)
;
if
(
isPositionIndependent
(
)
)
{
SDValue
Addr
=
getTargetNode
(
N
,
DL
,
Ty
,
DAG
,
0
)
;
if
(
IsLocal
)
return
SDValue
(
DAG
.
getMachineNode
(
RISCV
::
PseudoLLA
,
DL
,
Ty
,
Addr
)
,
0
)
;
return
SDValue
(
DAG
.
getMachineNode
(
RISCV
::
PseudoLA
,
DL
,
Ty
,
Addr
)
,
0
)
;
}
switch
(
getTargetMachine
(
)
.
getCodeModel
(
)
)
{
default
:
report_fatal_error
(
"Unsupported code model for lowering"
)
;
case
CodeModel
::
Small
:
{
SDValue
AddrHi
=
getTargetNode
(
N
,
DL
,
Ty
,
DAG
,
RISCVII
::
MO_HI
)
;
SDValue
AddrLo
=
getTargetNode
(
N
,
DL
,
Ty
,
DAG
,
RISCVII
::
MO_LO
)
;
SDValue
MNHi
=
SDValue
(
DAG
.
getMachineNode
(
RISCV
::
LUI
,
DL
,
Ty
,
AddrHi
)
,
0
)
;
return
SDValue
(
DAG
.
getMachineNode
(
RISCV
::
ADDI
,
DL
,
Ty
,
MNHi
,
AddrLo
)
,
0
)
;
}
case
CodeModel
::
Medium
:
{
SDValue
Addr
=
getTargetNode
(
N
,
DL
,
Ty
,
DAG
,
0
)
;
return
SDValue
(
DAG
.
getMachineNode
(
RISCV
::
PseudoLLA
,
DL
,
Ty
,
Addr
)
,
0
)
;
}
}
}
</s>

Return the address accessed by this recipe .


<s> bool isValidState ( ) const override { return true ; } </s>

See AbstractState : :isValidState ( ... )


" was Pass-through, is now Dirty-out.\n"

runOnMachineFunction - Emit the function body .


<s> bool AMDGPUPromoteAllocaToVector :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; if ( auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ) { return promoteAllocasToVector ( F , TPC -> getTM < TargetMachine > ( ) ) ; } return false ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static rtx sparc_delegitimize_address ( rtx x ) { x = delegitimize_mem_from_attrs ( x ) ; if ( GET_CODE ( x ) == LO_SUM && GET_CODE ( XEXP ( x , 1 ) ) == UNSPEC ) switch ( XINT ( XEXP ( x , 1 ) , 1 ) ) { case UNSPEC_MOVE_PIC : case UNSPEC_TLSLE : x = XVECEXP ( XEXP ( x , 1 ) , 0 , 0 ) ; gcc_assert ( GET_CODE ( x ) == SYMBOL_REF ) ; break ; default : break ; } if ( GET_CODE ( x ) == MINUS && REG_P ( XEXP ( x , 0 ) ) && REGNO ( XEXP ( x , 0 ) ) == PIC_OFFSET_TABLE_REGNUM && GET_CODE ( XEXP ( x , 1 ) ) == LO_SUM && GET_CODE ( XEXP ( XEXP ( x , 1 ) , 1 ) ) == UNSPEC && XINT ( XEXP ( XEXP ( x , 1 ) , 1 ) , 1 ) == UNSPEC_MOVE_PIC_LABEL ) { x = XVECEXP ( XEXP ( XEXP ( x , 1 ) , 1 ) , 0 , 0 ) ; gcc_assert ( GET_CODE ( x ) == LABEL_REF ) ; } return x ; } </s>

Delegitimize an address that was legitimized by the above function .


<s> const X86InstrInfo * getInstrInfo ( ) const { return getTargetMachine ( ) -> getSubtargetImpl ( ) -> getInstrInfo ( ) ; } </s>


<s> static void pro_epilogue_adjust_stack ( rtx dest , rtx src , rtx offset , int style , bool set_cfa ) { struct machine_function * m = cfun -> machine ; rtx insn ; bool add_frame_related_expr = false ; if ( Pmode == SImode ) insn = gen_pro_epilogue_adjust_stack_si_add ( dest , src , offset ) ; else if ( x86_64_immediate_operand ( offset , DImode ) ) insn = gen_pro_epilogue_adjust_stack_di_add ( dest , src , offset ) ; else { rtx tmp ; if ( style ) tmp = gen_rtx_REG ( DImode , R11_REG ) ; else { gcc_assert ( src != hard_frame_pointer_rtx && dest != hard_frame_pointer_rtx ) ; tmp = hard_frame_pointer_rtx ; } insn = emit_insn ( gen_rtx_SET ( tmp , offset ) ) ; if ( style < 0 ) add_frame_related_expr = true ; insn = gen_pro_epilogue_adjust_stack_di_add ( dest , src , tmp ) ; } insn = emit_insn ( insn ) ; if ( style >= 0 ) ix86_add_queued_cfa_restore_notes ( insn ) ; if ( set_cfa ) { rtx r ; gcc_assert ( m -> fs . cfa_reg == src ) ; m -> fs . cfa_offset += INTVAL ( offset ) ; m -> fs . cfa_reg = dest ; r = gen_rtx_PLUS ( Pmode , src , offset ) ; r = gen_rtx_SET ( dest , r ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , r ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } else if ( style < 0 ) { RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( add_frame_related_expr ) { rtx r = gen_rtx_PLUS ( Pmode , src , offset ) ; r = gen_rtx_SET ( dest , r ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , r ) ; } } if ( dest == stack_pointer_rtx ) { HOST_WIDE_INT ooffset = m -> fs . sp_offset ; bool valid = m -> fs . sp_valid ; if ( src == hard_frame_pointer_rtx ) { valid = m -> fs . fp_valid ; ooffset = m -> fs . fp_offset ; } else if ( src == crtl -> drap_reg ) { valid = m -> fs . drap_valid ; ooffset = 0 ; } else { gcc_checking_assert ( src == stack_pointer_rtx || offset == const0_rtx ) ; } m -> fs . sp_offset = ooffset - INTVAL ( offset ) ; m -> fs . sp_valid = valid ; } } </s>

Expand prologue or epilogue stack adjustment . The pattern exist to put a dependency on all ebp-based memory accesses . STYLE should be negative if instructions should be marked as frame related , zero if % r11 register is live and can not be freely used and positive otherwise .


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> unsigned X86InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( isFrameStoreOpcode ( MI -> getOpcode ( ) ) ) if ( MI -> getOperand ( X86 :: AddrNumOperands ) . getSubReg ( ) == 0 && isFrameOperand ( MI , 0 , FrameIndex ) ) return MI -> getOperand ( X86 :: AddrNumOperands ) . getReg ( ) ; return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> void rl78_expand_compare ( rtx * operands ) { if ( GET_CODE ( operands [ 2 ] ) == MEM ) operands [ 2 ] = copy_to_mode_reg ( GET_MODE ( operands [ 2 ] ) , operands [ 2 ] ) ; } </s>

Expander for cbranchqi4 and cbranchhi4 . RL78 is missing some of the `` normal '' compares , specifically , it only has unsigned compares , so we must synthesize the missing ones .


<s>
bool
FixupLEAPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
const
X86Subtarget
&
ST
=
MF
.
getSubtarget
<
X86Subtarget
>
(
)
;
bool
IsSlowLEA
=
ST
.
slowLEA
(
)
;
bool
IsSlow3OpsLEA
=
ST
.
slow3OpsLEA
(
)
;
bool
LEAUsesAG
=
ST
.
LEAusesAG
(
)
;
bool
OptIncDec
=
!
ST
.
slowIncDec
(
)
||
MF
.
getFunction
(
)
.
hasOptSize
(
)
;
bool
UseLEAForSP
=
ST
.
useLeaForSP
(
)
;
TSM
.
init
(
&
ST
)
;
TII
=
ST
.
getInstrInfo
(
)
;
TRI
=
ST
.
getRegisterInfo
(
)
;
auto
*
PSI
=
&
getAnalysis
<
ProfileSummaryInfoWrapperPass
>
(
)
.
getPSI
(
)
;
auto
*
MBFI
=
(
PSI
&&
PSI
->
hasProfileSummary
(
)
)
&
getAnalysis
<
LazyMachineBlockFrequencyInfoPass
>
(
)
.
getBFI
(
)
:
nullptr
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Start X86FixupLEAs\n"
;
)
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
bool
OptIncDecPerBB
=
OptIncDec
||
llvm
::
shouldOptimizeForSize
(
&
MBB
,
PSI
,
MBFI
)
;
for
(
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
;
I
!=
MBB
.
end
(
)
;
++
I
)
{
if
(
!
isLEA
(
I
->
getOpcode
(
)
)
)
continue
;
if
(
optTwoAddrLEA
(
I
,
MBB
,
OptIncDecPerBB
,
UseLEAForSP
)
)
continue
;
if
(
IsSlowLEA
)
processInstructionForSlowLEA
(
I
,
MBB
)
;
else
if
(
IsSlow3OpsLEA
)
processInstrForSlow3OpLEA
(
I
,
MBB
,
OptIncDecPerBB
)
;
}
if
(
LEAUsesAG
)
{
for
(
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
;
I
!=
MBB
.
end
(
)
;
++
I
)
processInstruction
(
I
,
MBB
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
"End X86FixupLEAs\n"
;
)
;
return
true
;
}
</s>


"Builtin function %s is only valid for the cell processor"

"Builtin function %s requires the -mvsx option"

"Builtin function %s requires the -mhtm option"

"Builtin function %s requires the -maltivec option"

"Builtin function %s requires the -mpaired option"

"Builtin function %s requires the -mspe option"

"Builtin function %s requires the -mhard-dfp and"

"Builtin function %s requires the -mhard-dfp option"

"Builtin function %s requires the -mpower8-vector option"

"Builtin function %s requires the -mhard-float and"

"Builtin function %s requires the -mhard-float option"

"Builtin function %s is not supported with the current options"

Raise an error message for a builtin function that is called without the appropriate target options being set .


<s> static rtx arm_expand_binop_builtin ( enum insn_code icode , tree arglist , rtx target ) { rtx pat ; tree arg0 = TREE_VALUE ( arglist ) ; tree arg1 = TREE_VALUE ( TREE_CHAIN ( arglist ) ) ; rtx op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , 0 ) ; rtx op1 = expand_expr ( arg1 , NULL_RTX , VOIDmode , 0 ) ; enum machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; enum machine_mode mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; enum machine_mode mode1 = insn_data [ icode ] . operand [ 2 ] . mode ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; gcc_assert ( GET_MODE ( op0 ) == mode0 && GET_MODE ( op1 ) == mode1 ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ 2 ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>

Subroutine of arm_expand_builtin to take care of binop insns .


<s> unsigned ARMBaseInstrInfo :: getNumLDMAddresses ( const MachineInstr & MI ) const { unsigned Size = 0 ; for ( MachineInstr :: mmo_iterator I = MI . memoperands_begin ( ) , E = MI . memoperands_end ( ) ; I != E ; ++ I ) { Size += ( * I ) -> getSize ( ) ; } return Size / 4 ; } </s>

Get the number of addresses by LDM or VLDM or zero for unknown .


<s> DecodeStatus XtensaDisassembler :: getInstruction ( MCInst & instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & vStream , raw_ostream & cStream ) const { return Fail ; } </s>

Returns the disassembly of a single instruction .


<s> bool aarch_bti_j_insn_p ( rtx_insn * insn ) { if ( ! insn || ! INSN_P ( insn ) ) return false ; rtx pat = PATTERN ( insn ) ; return GET_CODE ( pat ) == UNSPEC_VOLATILE && XINT ( pat , 1 ) == VUNSPEC_BTI_NOP ; } </s>


<s> bool RISCVAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { if ( ! AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , OS ) ) return false ; if ( ! ExtraCode ) { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate : OS << MO . getImm ( ) ; return false ; case MachineOperand :: MO_Register : OS << RISCVInstPrinter :: getRegisterName ( MO . getReg ( ) ) ; return false ; default : break ; } } return true ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> void assignValueToReg ( Register ValVReg , Register PhysReg , CCValAssign & VA ) override { Register ExtReg ; if ( VA . getLocVT ( ) . getSizeInBits ( ) < 32 ) { ExtReg = MIRBuilder . buildAnyExt ( LLT :: scalar ( 32 ) , ValVReg ) . getReg ( 0 ) ; } else ExtReg = extendRegister ( ValVReg , VA ) ; const SIRegisterInfo * TRI = static_cast < const SIRegisterInfo * > ( MRI . getTargetRegisterInfo ( ) ) ; if ( TRI -> isSGPRReg ( MRI , PhysReg ) ) { auto ToSGPR = MIRBuilder . buildIntrinsic ( Intrinsic :: amdgcn_readfirstlane , { MRI . getType ( ExtReg ) } , false ) . addReg ( ExtReg ) ; ExtReg = ToSGPR . getReg ( 0 ) ; } MIRBuilder . buildCopy ( PhysReg , ExtReg ) ; MIB . addUse ( PhysReg , RegState :: Implicit ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


"GCC does not currently support mixed size types "

"GCC does not currently support return type %qT "

"unsupported return type %qT for %<simd%> functions"

"GCC does not currently support argument type %qT "

"GCC does not currently support simdlen %wd for type %qT"


<s> void ARMDAGToDAGISel :: PreprocessISelDAG ( ) { if ( ! Subtarget -> hasV6T2Ops ( ) ) return ; bool isThumb2 = Subtarget -> isThumb ( ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( N -> getOpcode ( ) != ISD :: ADD ) continue ; SDValue N0 = N -> getOperand ( 0 ) ; SDValue N1 = N -> getOperand ( 1 ) ; unsigned And_imm = 0 ; if ( ! isOpcWithIntImmediate ( N1 . getNode ( ) , ISD :: AND , And_imm ) ) { if ( isOpcWithIntImmediate ( N0 . getNode ( ) , ISD :: AND , And_imm ) ) std :: swap ( N0 , N1 ) ; } if ( ! And_imm ) continue ; unsigned TZ = countTrailingZeros ( And_imm ) ; if ( TZ != 1 && TZ != 2 ) continue ; And_imm >>= TZ ; if ( And_imm & ( And_imm + 1 ) ) continue ; SDValue Srl = N1 . getOperand ( 0 ) ; unsigned Srl_imm = 0 ; if ( ! isOpcWithIntImmediate ( Srl . getNode ( ) , ISD :: SRL , Srl_imm ) || ( Srl_imm <= 2 ) ) continue ; SDValue CPTmp0 ; SDValue CPTmp1 ; SDValue CPTmp2 ; if ( isThumb2 ) { if ( SelectT2ShifterOperandReg ( N0 , CPTmp0 , CPTmp1 ) ) continue ; } else { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) || SelectRegShifterOperand ( N0 , CPTmp0 , CPTmp1 , CPTmp2 ) ) continue ; } Srl = CurDAG -> getNode ( ISD :: SRL , SDLoc ( Srl ) , MVT :: i32 , Srl . getOperand ( 0 ) , CurDAG -> getConstant ( Srl_imm + TZ , MVT :: i32 ) ) ; N1 = CurDAG -> getNode ( ISD :: AND , SDLoc ( N1 ) , MVT :: i32 , Srl , CurDAG -> getConstant ( And_imm , MVT :: i32 ) ) ; N1 = CurDAG -> getNode ( ISD :: SHL , SDLoc ( N1 ) , MVT :: i32 , N1 , CurDAG -> getConstant ( TZ , MVT :: i32 ) ) ; CurDAG -> UpdateNodeOperands ( N , N0 , N1 ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> bool PPCTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , bool * Fast ) const { if ( DisablePPCUnaligned ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( VT . getSimpleVT ( ) . isVector ( ) ) { if ( Subtarget . hasVSX ( ) ) { if ( VT != MVT :: v2f64 && VT != MVT :: v2i64 ) return false ; } else { return false ; } } if ( VT == MVT :: ppcf128 ) return false ; if ( Fast ) * Fast = true ; return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> int check_use_sfunc_addr ( rtx insn , rtx reg ) { while ( ( insn = NEXT_INSN ( insn ) ) ) { if ( GET_CODE ( insn ) == CODE_LABEL || GET_CODE ( insn ) == JUMP_INSN ) break ; if ( ! INSN_P ( insn ) ) continue ; if ( GET_CODE ( PATTERN ( insn ) ) == SEQUENCE ) insn = XVECEXP ( PATTERN ( insn ) , 0 , 0 ) ; if ( GET_CODE ( PATTERN ( insn ) ) != PARALLEL || get_attr_type ( insn ) != TYPE_SFUNC ) continue ; return rtx_equal_p ( extract_sfunc_addr ( insn ) , reg ) ; } gcc_unreachable ( ) ; } </s>

Verify that the register in use_sfunc_addr still agrees with the address used in the sfunc . This prevents fill_slots_from_thread from changing use_sfunc_addr . INSN is the use_sfunc_addr instruction , and REG is the register it guards .


"ARM MVE TailPred and VPT Optimisation Pass"

getPassName - Return a nice clean name for a pass .


<s> static void tilepro_setup_incoming_varargs ( cumulative_args_t cum , const function_arg_info & arg , int * pretend_args , int no_rtl ) { CUMULATIVE_ARGS local_cum = * get_cumulative_args ( cum ) ; int first_reg ; targetm . calls . function_arg_advance ( pack_cumulative_args ( & local_cum ) , arg ) ; first_reg = local_cum ; if ( local_cum < TILEPRO_NUM_ARG_REGS ) { * pretend_args = UNITS_PER_WORD * ( TILEPRO_NUM_ARG_REGS - first_reg ) ; if ( ! no_rtl ) { alias_set_type set = get_varargs_alias_set ( ) ; rtx tmp = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , \ virtual_incoming_args_rtx , - STACK_POINTER_OFFSET - UNITS_PER_WORD * ( TILEPRO_NUM_ARG_REGS - first_reg ) ) ) ; MEM_NOTRAP_P ( tmp ) = 1 ; set_mem_alias_set ( tmp , set ) ; move_block_from_reg ( first_reg , tmp , TILEPRO_NUM_ARG_REGS - first_reg ) ; } } else * pretend_args = 0 ; } </s>


<s> unsigned AMDGPURegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return AMDGPU :: NoRegister ; } </s>


<s> bool legitimate_constant_address_p ( rtx x ) { if ( GET_CODE ( x ) == LABEL_REF || GET_CODE ( x ) == SYMBOL_REF || CONST_INT_P ( x ) || GET_CODE ( x ) == HIGH ) return true ; if ( GET_CODE ( x ) != CONST ) return false ; if ( flag_pic && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P ( XEXP ( XEXP ( x , 0 ) , 0 ) ) ) return false ; return true ; } </s>

1 if X is an rtx for a constant that is a valid address .


<s> static void s390_trampoline_init ( rtx m_tramp , tree fndecl , rtx cxt ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx mem ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( 2 * UNITS_PER_LONG ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp , Pmode , 2 * UNITS_PER_LONG ) ; emit_move_insn ( mem , cxt ) ; mem = adjust_address ( m_tramp , Pmode , 3 * UNITS_PER_LONG ) ; emit_move_insn ( mem , fnaddr ) ; } </s>

Emit RTL insns to initialize the variable parts of a trampoline . FNADDR is an RTX for the address of the function 's pure code . CXT is an RTX for the static chain value for the function .


<s> char * ix86_offload_options ( void ) { if ( TARGET_LP64 ) return xstrdup ( "-foffload-abi=lp64" ) ; return xstrdup ( "-foffload-abi=ilp32" ) ; } </s>

Implement the TARGET_OFFLOAD_OPTIONS hook .


<s>
void
SICDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
if
(
trySelect
(
Node
)
)
return
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
ReplaceNode
(
Node
,
getGlobalBaseReg
(
)
)
;
return
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

SIC
SIC
"Selecting: "
"\n"
"== "
"\n"
1
ISD::GLOBAL_OFFSET_TABLE


Output the assembly for a call instruction .


<s>
MachineBasicBlock
*
HexagonTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
case
Hexagon
::
ADJDYNALLOC
:
{
MachineFunction
*
MF
=
BB
->
getParent
(
)
;
HexagonMachineFunctionInfo
*
FuncInfo
=
MF
->
getInfo
<
HexagonMachineFunctionInfo
>
(
)
;
FuncInfo
->
addAllocaAdjustInst
(
MI
)
;
return
BB
;
}
default
:
assert
(
false
&&
"Unexpected instr type to insert"
)
;
}
return
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .

Hexagon
Hexagon
Hexagon::ADJDYNALLOC
Hexagon
Hexagon
"Unexpected instr type to insert"


"StoreResults expects liveness tracking"

runOnMachineFunction - Emit the function body .


<s> bool ARMBaseTargetMachine :: addInstSelector ( PassManagerBase & PM ) { PM . add ( createARMISelDag ( * this , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void releaseMemory ( ) override { } </s>

releaseMemory ( ) - This member can be implemented by a pass if it wants to be able to release its memory when it is no longer needed .


<s> bool SystemZTargetLowering :: isTruncateFree ( EVT FromVT , EVT ToVT ) const { if ( ! FromVT . isInteger ( ) || ! ToVT . isInteger ( ) ) return false ; unsigned FromBits = FromVT . getFixedSizeInBits ( ) ; unsigned ToBits = ToVT . getFixedSizeInBits ( ) ; return FromBits > ToBits ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s> void ix86_emit_fp_unordered_jump ( rtx label ) { rtx reg = gen_reg_rtx ( HImode ) ; rtx_insn * insn ; rtx temp ; emit_insn ( gen_x86_fnstsw_1 ( reg ) ) ; if ( TARGET_SAHF && ( TARGET_USE_SAHF || optimize_insn_for_size_p ( ) ) ) { emit_insn ( gen_x86_sahf_1 ( reg ) ) ; temp = gen_rtx_REG ( CCmode , FLAGS_REG ) ; temp = gen_rtx_UNORDERED ( VOIDmode , temp , const0_rtx ) ; } else { emit_insn ( gen_testqi_ext_1_ccno ( reg , GEN_INT ( 0x04 ) ) ) ; temp = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; temp = gen_rtx_NE ( VOIDmode , temp , const0_rtx ) ; } temp = gen_rtx_IF_THEN_ELSE ( VOIDmode , temp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , temp ) ) ; predict_jump ( REG_BR_PROB_BASE * 10 / 100 ) ; JUMP_LABEL ( insn ) = label ; } </s>

Output code to perform a conditional jump to LABEL , if C2 flag in FP status register is set .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addRequired < AliasAnalysis > ( ) ; AU . addRequired < TargetPassConfig > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool M68kInstrInfo :: isPCRelRegisterOperandLegal ( const MachineOperand & MO ) const { assert ( MO . isReg ( ) ) ; const MachineInstr * MI = MO . getParent ( ) ; const unsigned NameIndices = M68kInstrNameIndices [ MI -> getOpcode ( ) ] ; StringRef InstrName ( & M68kInstrNameData [ NameIndices ] ) ; const unsigned OperandNo = MI -> getOperandNo ( & MO ) ; if ( OperandNo == 1 ) return Regex ( "[A-Z]+(8|16|32)k[a-z](_TC)?$" ) . match ( InstrName ) ; if ( OperandNo == MI -> getNumExplicitOperands ( ) - 1 ) return Regex ( "[A-Z]+(8|16|32)[a-z]k(_TC)?$" ) . match ( InstrName ) ; return false ; } </s>

Allow targets to tell MachineVerifier whether a specific register MachineOperand can be used as part of PC-relative addressing .


<s> void LEGInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( LEG :: MOVrr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } </s>


<s> bool BPFAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { if ( ( Count % 8 ) != 0 ) return false ; for ( uint64_t i = 0 ; i < Count ; i += 8 ) support :: endian :: write < uint64_t > ( OS , 0x15000000 , Endian ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s>
AsmToken
LexToken
(
)
{
if
(
!
Lexer
)
{
SetError
(
SMLoc
(
)
,
"No MCAsmLexer installed"
)
;
return
AsmToken
(
AsmToken
::
Error
,
""
,
0
)
;
}
switch
(
AsmInfo
.
getAssemblerDialect
(
)
)
{
default
:
SetError
(
SMLoc
(
)
,
"Unhandled dialect"
)
;
return
AsmToken
(
AsmToken
::
Error
,
""
,
0
)
;
case
0
:
return
LexTokenATT
(
)
;
case
1
:
return
LexTokenIntel
(
)
;
}
}
</s>

LexToken - Read the next token and return its code .


<s> BitVector Z80oldRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const Z80oldFrameLowering * TFI = getFrameLowering ( MF ) ; Reserved . set ( Z80old :: SPS ) ; Reserved . set ( Z80old :: PC ) ; if ( TFI -> hasFP ( MF ) ) { for ( MCSubRegIterator I ( Z80old :: IX , this , true ) ; I . isValid ( ) ; ++ I ) { Reserved . set ( * I ) ; } } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool hasExtractInsert ( ) const { return ! inMips16Mode ( ) && hasMips32r2 ( ) ; } </s>

Features related to the presence of specific instructions .


<s> static void alpha_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; bool onstack = targetm . calls . must_pass_in_stack ( arg ) ; int increment = onstack ? 6 : ALPHA_ARG_SIZE ( arg . mode , arg . type ) ; * cum += increment ; if ( ! onstack && cum -> num_args < 6 ) cum -> atypes [ cum -> num_args ] = alpha_arg_type ( arg . mode ) ; cum -> num_args += increment ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> static struct machine_function * nvptx_init_machine_status ( void ) { struct machine_function * p = ggc_cleared_alloc < machine_function > ( ) ; p -> ret_reg_mode = VOIDmode ; return p ; } </s>

Allocate a new , cleared machine_function structure .


"InsertBranch cannot insert a fallthrough"

"Unconditional branch cannot have multiple successors"

Insert branch code into the end of the specified MachineBasicBlock .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"ARM Machine Code Emitter"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool hasDomain ( unsigned domain ) const { return AvailableDomains & ( 1u << domain ) ; } </s>


<s> void ARMAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( EnableMCInst ) { printInstructionThroughMCStreamer ( MI ) ; return ; } if ( MI -> getOpcode ( ) == ARM :: CONSTPOOL_ENTRY ) EmitAlignment ( 2 ) ; SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; printInstruction ( MI , OS ) ; OutStreamer . EmitRawText ( OS . str ( ) ) ; if ( MI -> getOpcode ( ) == ARM :: t2TBB ) EmitAlignment ( 1 ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static bool isEqual ( const CvtDirection & LHS , const CvtDirection & RHS ) { return LHS . SourceType == RHS . SourceType && LHS . DestinationType == RHS . DestinationType ; } </s>

isEqual - Compares two trees for structural equality and returns true if they are equal .


<s> static void arc_internal_label ( FILE * stream , const char * prefix , unsigned long labelno ) { arc_ccfsm_at_label ( prefix , labelno ) ; default_internal_label ( stream , prefix , labelno ) ; } </s>

This is how to output a definition of an internal numbered label where PREFIX is the class of label and NUM is the number within the class .


<s> int m32r_hard_regno_rename_ok ( unsigned int old_reg ATTRIBUTE_UNUSED , unsigned int new_reg ) { if ( lookup_attribute ( "interrupt" , DECL_ATTRIBUTES ( current_function_decl ) ) && ! df_regs_ever_live_p ( new_reg ) ) return 0 ; return 1 ; } </s>

Return true if using NEW_REG in place of OLD_REG is ok .


<s> std :: pair < int , MVT > SITargetLowering :: getTypeLegalizationCost ( const DataLayout & DL , Type * Ty ) const { auto Cost = TargetLoweringBase :: getTypeLegalizationCost ( DL , Ty ) ; auto Size = DL . getTypeSizeInBits ( Ty ) ; if ( Size <= 256 ) return Cost ; Cost . first = ( Size + 255 ) / 256 ; return Cost ; } </s>

Estimate the cost of type-legalization and the legalized type .


<s> static void frv_frame_access ( frv_frame_accessor_t * accessor , rtx reg , int stack_offset ) { machine_mode mode = GET_MODE ( reg ) ; rtx mem = frv_frame_mem ( mode , accessor -> base , stack_offset - accessor -> base_offset ) ; if ( accessor -> op == FRV_LOAD ) { if ( SPR_P ( REGNO ( reg ) ) ) { rtx temp = gen_rtx_REG ( mode , TEMP_REGNO ) ; emit_insn ( gen_rtx_SET ( VOIDmode , temp , mem ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , reg , temp ) ) ; } else { if ( mode == DImode && GET_CODE ( XEXP ( mem , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( mem , 0 ) , 0 ) ) == REG && GET_CODE ( XEXP ( XEXP ( mem , 0 ) , 1 ) ) == REG ) { rtx temp = gen_rtx_REG ( SImode , TEMP_REGNO ) ; emit_move_insn ( temp , gen_rtx_PLUS ( SImode , XEXP ( XEXP ( mem , 0 ) , 0 ) , XEXP ( XEXP ( mem , 0 ) , 1 ) ) ) ; mem = gen_rtx_MEM ( DImode , temp ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , reg , mem ) ) ; } emit_use ( reg ) ; } else { if ( SPR_P ( REGNO ( reg ) ) ) { rtx temp = gen_rtx_REG ( mode , TEMP_REGNO ) ; emit_insn ( gen_rtx_SET ( VOIDmode , temp , reg ) ) ; frv_frame_insn ( gen_rtx_SET ( Pmode , mem , temp ) , frv_dwarf_store ( reg , stack_offset ) ) ; } else if ( mode == DImode ) { rtx reg1 = gen_rtx_REG ( SImode , REGNO ( reg ) ) ; rtx reg2 = gen_rtx_REG ( SImode , REGNO ( reg ) + 1 ) ; rtx set1 = frv_dwarf_store ( reg1 , stack_offset ) ; rtx set2 = frv_dwarf_store ( reg2 , stack_offset + 4 ) ; if ( GET_CODE ( XEXP ( mem , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( mem , 0 ) , 0 ) ) == REG && GET_CODE ( XEXP ( XEXP ( mem , 0 ) , 1 ) ) == REG ) { rtx temp = gen_rtx_REG ( SImode , TEMP_REGNO ) ; emit_move_insn ( temp , gen_rtx_PLUS ( SImode , XEXP ( XEXP ( mem , 0 ) , 0 ) , XEXP ( XEXP ( mem , 0 ) , 1 ) ) ) ; mem = gen_rtx_MEM ( DImode , temp ) ; } frv_frame_insn ( gen_rtx_SET ( Pmode , mem , reg ) , gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set1 , set2 ) ) ) ; } else frv_frame_insn ( gen_rtx_SET ( Pmode , mem , reg ) , frv_dwarf_store ( reg , stack_offset ) ) ; } } </s>

Emit instructions that transfer REG to or from the memory location ( sp + STACK_OFFSET ) . The register is stored in memory if ACCESSOR- > OP is FRV_STORE and loaded if it is FRV_LOAD . Only the prologue uses this function to store registers and only the epilogue uses it to load them . The caller sets up ACCESSOR so that BASE is equal to ( sp + BASE_OFFSET ) . The generated instruction will use BASE as its base register . BASE may simply be the stack pointer , but if several accesses are being made to a region far away from the stack pointer , it may be more efficient to set up a temporary instead . Store instructions will be frame-related and will be annotated with the overall effect of the store . Load instructions will be followed by a ( use ) to prevent later optimizations from zapping them . The function takes care of the moves to and from SPRs , using TEMP_REGNO as a temporary in such cases .


"Unable to get the legal offset for nil instruction."

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s> bool PPCTargetLowering :: SelectAddressRegReg ( SDValue N , SDValue & Base , SDValue & Index , SelectionDAG & DAG ) const { short imm = 0 ; if ( N . getOpcode ( ) == ISD :: ADD ) { if ( isIntS16Immediate ( N . getOperand ( 1 ) , imm ) ) return false ; if ( N . getOperand ( 1 ) . getOpcode ( ) == PPCISD :: Lo ) return false ; Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } else if ( N . getOpcode ( ) == ISD :: OR ) { if ( isIntS16Immediate ( N . getOperand ( 1 ) , imm ) ) return false ; APInt LHSKnownZero , LHSKnownOne ; APInt RHSKnownZero , RHSKnownOne ; DAG . ComputeMaskedBits ( N . getOperand ( 0 ) , APInt :: getAllOnesValue ( N . getOperand ( 0 ) . getValueSizeInBits ( ) ) , LHSKnownZero , LHSKnownOne ) ; if ( LHSKnownZero . getBoolValue ( ) ) { DAG . ComputeMaskedBits ( N . getOperand ( 1 ) , APInt :: getAllOnesValue ( N . getOperand ( 1 ) . getValueSizeInBits ( ) ) , RHSKnownZero , RHSKnownOne ) ; if ( ~ ( LHSKnownZero | RHSKnownZero ) == 0 ) { Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } } } return false ; } </s>

SelectAddressRegReg - Given the specified addressed , check to see if it can be more efficiently represented as [ r+imm ] .


<s>
void
X86ATTInstPrinter
::
printPCRelImm
(
const
MCInst
*
MI
,
unsigned
OpNo
,
raw_ostream
&
O
)
{
const
MCOperand
&
Op
=
MI
->
getOperand
(
OpNo
)
;
if
(
Op
.
isImm
(
)
)
O
<<
formatImm
(
Op
.
getImm
(
)
)
;
else
{
assert
(
Op
.
isExpr
(
)
&&
"unknown pcrel immediate operand"
)
;
const
MCConstantExpr
*
BranchTarget
=
dyn_cast
<
MCConstantExpr
>
(
Op
.
getExpr
(
)
)
;
int64_t
Address
;
if
(
BranchTarget
&&
BranchTarget
->
EvaluateAsAbsolute
(
Address
)
)
{
O
<<
"0x"
;
O
.
write_hex
(
Address
)
;
}
else
{
O
<<
*
Op
.
getExpr
(
)
;
}
}
}
</s>


<s>
void
aarch64_simd_lane_bounds
(
rtx
operand
,
HOST_WIDE_INT
low
,
HOST_WIDE_INT
high
,
const_tree
exp
)
{
HOST_WIDE_INT
lane
;
gcc_assert
(
CONST_INT_P
(
operand
)
)
;
lane
=
INTVAL
(
operand
)
;
if
(
lane
<
low
||
lane
>=
high
)
{
if
(
exp
)
error
(
"%Klane %ld out of range %ld - %ld"
,
exp
,
lane
,
low
,
high
1
)
;
else
error
(
"lane %ld out of range %ld - %ld"
,
lane
,
low
,
high
1
)
;
}
}
</s>

Bounds-check lanes . Ensure OPERAND lies between LOW ( inclusive ) and HIGH ( exclusive ) .


<s> unsigned getFirstDomain ( ) const { return CountTrailingZeros_32 ( AvailableDomains ) ; } </s>


<s> static rtx or1k_restore_reg ( int regno , HOST_WIDE_INT offset , rtx cfa_restores ) { rtx reg = gen_rtx_REG ( Pmode , regno ) ; rtx mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; emit_move_insn ( reg , mem ) ; return alloc_reg_note ( REG_CFA_RESTORE , reg , cfa_restores ) ; } </s>

Emit rtl to restore register REGNO contents from stack memory at the given OFFSET from the current stack pointer .


<s> bool AMDGPUAsmPrinter :: lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) const { const AMDGPUSubtarget & STI = MF -> getSubtarget < AMDGPUSubtarget > ( ) ; AMDGPUMCInstLower MCInstLowering ( OutContext , STI , * this ) ; return MCInstLowering . lowerOperand ( MO , MCOp ) ; } </s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
Mips
::
NumTargetFixupKinds
]
=
{
{
"fixup_Mips_NONE"
,
0
,
0
,
0
}
,
{
"fixup_Mips_16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_32"
,
0
,
32
,
0
}
,
{
"fixup_Mips_REL32"
,
0
,
32
,
0
}
,
{
"fixup_Mips_26"
,
0
,
26
,
0
}
,
{
"fixup_Mips_HI16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_LO16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GPREL16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_LITERAL"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GOT16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_PC16"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_Mips_CALL16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GPREL32"
,
0
,
32
,
0
}
,
{
"fixup_Mips_SHIFT5"
,
6
,
5
,
0
}
,
{
"fixup_Mips_SHIFT6"
,
6
,
5
,
0
}
,
{
"fixup_Mips_64"
,
0
,
64
,
0
}
,
{
"fixup_Mips_TLSGD"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GOTTPREL"
,
0
,
16
,
0
}
,
{
"fixup_Mips_TPREL_HI"
,
0
,
16
,
0
}
,
{
"fixup_Mips_TPREL_LO"
,
0
,
16
,
0
}
,
{
"fixup_Mips_Branch_PCRel"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> int rs6000_emit_vector_cond_expr ( rtx dest , rtx op_true , rtx op_false , rtx cond , rtx cc_op0 , rtx cc_op1 ) { machine_mode dest_mode = GET_MODE ( dest ) ; machine_mode mask_mode = GET_MODE ( cc_op0 ) ; enum rtx_code rcode = GET_CODE ( cond ) ; machine_mode cc_mode = CCmode ; rtx mask ; rtx cond2 ; rtx tmp ; bool invert_move = false ; if ( VECTOR_UNIT_NONE_P ( dest_mode ) ) return 0 ; gcc_assert ( GET_MODE_SIZE ( dest_mode ) == GET_MODE_SIZE ( mask_mode ) && GET_MODE_NUNITS ( dest_mode ) == GET_MODE_NUNITS ( mask_mode ) ) ; switch ( rcode ) { case NE : case UNLE : case UNLT : case UNGE : case UNGT : invert_move = true ; rcode = reverse_condition_maybe_unordered ( rcode ) ; if ( rcode == UNKNOWN ) return 0 ; break ; case GTU : case GEU : case LTU : case LEU : cc_mode = CCUNSmode ; break ; default : break ; } mask = rs6000_emit_vector_compare ( rcode , cc_op0 , cc_op1 , mask_mode ) ; if ( ! mask ) return 0 ; if ( invert_move ) { tmp = op_true ; op_true = op_false ; op_false = tmp ; } cond2 = gen_rtx_fmt_ee ( NE , cc_mode , gen_lowpart ( dest_mode , mask ) , CONST0_RTX ( dest_mode ) ) ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_IF_THEN_ELSE ( dest_mode , cond2 , op_true , op_false ) ) ) ; return 1 ; } </s>

Emit vector conditional expression . DEST is destination . OP1 and OP2 are two VEC_COND_EXPR operands . CC_OP0 and CC_OP1 are the two operands for the relation operation COND .


<s> const DataLayout * getDataLayout ( ) const override { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> bool SNESTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; auto CCFunction = CCAssignFnForReturn ( CallConv ) ; return CCInfo . CheckReturn ( Outs , CCFunction ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> void MMIXAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; MCInst TmpInst ; LowerMMIXMachineInstrToMCInst ( MI , TmpInst , * this ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>


<s> Sched :: Preference ARMTargetLowering :: getSchedulingPreference ( SDNode * N ) const { unsigned NumVals = N -> getNumValues ( ) ; if ( ! NumVals ) return Sched :: RegPressure ; for ( unsigned i = 0 ; i != NumVals ; ++ i ) { EVT VT = N -> getValueType ( i ) ; if ( VT == MVT :: Flag || VT == MVT :: Other ) continue ; if ( VT . isFloatingPoint ( ) || VT . isVector ( ) ) return Sched :: Latency ; } if ( ! N -> isMachineOpcode ( ) ) return Sched :: RegPressure ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; const TargetInstrDesc & TID = TII -> get ( N -> getMachineOpcode ( ) ) ; if ( TID . getNumDefs ( ) == 0 ) return Sched :: RegPressure ; if ( ! Itins -> isEmpty ( ) && Itins -> getOperandCycle ( TID . getSchedClass ( ) , 0 ) > 2 ) return Sched :: Latency ; return Sched :: RegPressure ; } </s>


"enabling backtrace support is only meaningful when compiling for the Thumb"

"enabling callee interworking support is only meaningful when compiling for the Thumb"

"-g with -mno-apcs-frame may not give sensible debugging"

"can not use -mtp=cp15 with 16-bit Thumb"

"%s only supports non-pic code on M-profile targets with the "

Check any incompatible options that the user has specified .


<s> static void cris_file_end ( void ) { if ( TARGET_LINUX && trampolines_created ) file_end_indicate_exec_stack ( ) ; } </s>

Output that goes at the end of the file , similarly .


<s>
SUnit
*
R600SchedStrategy
::
pickNode
(
bool
&
IsTopNode
)
{
SUnit
*
SU
=
0
;
NextInstKind
=
IDOther
;
IsTopNode
=
false
;
bool
AllowSwitchToAlu
=
(
CurEmitted
>=
InstKindLimit
[
CurInstKind
]
)
||
(
Available
[
CurInstKind
]
.
empty
(
)
)
;
bool
AllowSwitchFromAlu
=
(
CurEmitted
>=
InstKindLimit
[
CurInstKind
]
)
&&
(
!
Available
[
IDFetch
]
.
empty
(
)
||
!
Available
[
IDOther
]
.
empty
(
)
)
;
if
(
CurInstKind
==
IDAlu
&&
!
Available
[
IDFetch
]
.
empty
(
)
)
{
float
ALUFetchRationEstimate
=
(
AluInstCount
+
AvailablesAluCount
(
)
+
Pending
[
IDAlu
]
.
size
(
)
)
/
(
FetchInstCount
+
Available
[
IDFetch
]
.
size
(
)
)
;
unsigned
NeededWF
=
62.5f
/
ALUFetchRationEstimate
;
DEBUG
(
dbgs
(
)
<<
NeededWF
<<
" approx. Wavefronts Required\n"
)
;
unsigned
NearRegisterRequirement
=
2
*
Available
[
IDFetch
]
.
size
(
)
;
if
(
NeededWF
>
getWFCountLimitedByGPR
(
NearRegisterRequirement
)
)
AllowSwitchFromAlu
=
true
;
}
if
(
!
SU
&&
!
UnscheduledARDefs
.
empty
(
)
)
{
SU
=
UnscheduledARDefs
[
0
]
;
UnscheduledARDefs
.
erase
(
UnscheduledARDefs
.
begin
(
)
)
;
NextInstKind
=
IDAlu
;
}
if
(
!
SU
&&
(
(
AllowSwitchToAlu
&&
CurInstKind
!=
IDAlu
)
||
(
!
AllowSwitchFromAlu
&&
CurInstKind
==
IDAlu
)
)
)
{
SU
=
pickAlu
(
)
;
if
(
!
SU
&&
!
PhysicalRegCopy
.
empty
(
)
)
{
SU
=
PhysicalRegCopy
.
front
(
)
;
PhysicalRegCopy
.
erase
(
PhysicalRegCopy
.
begin
(
)
)
;
}
if
(
SU
)
{
if
(
CurEmitted
>=
InstKindLimit
[
IDAlu
]
)
CurEmitted
=
0
;
NextInstKind
=
IDAlu
;
}
}
if
(
!
SU
)
{
SU
=
pickOther
(
IDFetch
)
;
if
(
SU
)
NextInstKind
=
IDFetch
;
}
if
(
!
SU
)
{
SU
=
pickOther
(
IDOther
)
;
if
(
SU
)
NextInstKind
=
IDOther
;
}
if
(
!
SU
&&
!
UnscheduledARUses
.
empty
(
)
)
{
SU
=
UnscheduledARUses
[
0
]
;
UnscheduledARUses
.
erase
(
UnscheduledARUses
.
begin
(
)
)
;
NextInstKind
=
IDAlu
;
}
DEBUG
(
if
(
SU
)
{
dbgs
(
)
<<
" ** Pick node **\n"
;
SU
->
dump
(
DAG
)
;
}
else
{
dbgs
(
)
<<
"NO NODE \n"
;
for
(
unsigned
i
=
0
;
i
<
DAG
->
SUnits
.
size
(
)
;
i
++
)
{
const
SUnit
&
S
=
DAG
->
SUnits
[
i
]
;
if
(
!
S
.
isScheduled
)
S
.
dump
(
DAG
)
;
}
}
</s>

Pick the next node to schedule , or return NULL .


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> rtx aarch64_gen_compare_reg ( RTX_CODE code , rtx x , rtx y ) { machine_mode cmp_mode = GET_MODE ( x ) ; machine_mode cc_mode ; rtx cc_reg ; if ( cmp_mode == TImode ) { gcc_assert ( code == NE ) ; cc_mode = CCmode ; cc_reg = gen_rtx_REG ( cc_mode , CC_REGNUM ) ; rtx x_lo = operand_subword ( x , 0 , 0 , TImode ) ; rtx y_lo = operand_subword ( y , 0 , 0 , TImode ) ; emit_set_insn ( cc_reg , gen_rtx_COMPARE ( cc_mode , x_lo , y_lo ) ) ; rtx x_hi = operand_subword ( x , 1 , 0 , TImode ) ; rtx y_hi = operand_subword ( y , 1 , 0 , TImode ) ; emit_insn ( gen_ccmpccdi ( cc_reg , cc_reg , x_hi , y_hi , gen_rtx_EQ ( cc_mode , cc_reg , const0_rtx ) , GEN_INT ( AARCH64_EQ ) ) ) ; } else { cc_mode = SELECT_CC_MODE ( code , x , y ) ; cc_reg = gen_rtx_REG ( cc_mode , CC_REGNUM ) ; emit_set_insn ( cc_reg , gen_rtx_COMPARE ( cc_mode , x , y ) ) ; } return cc_reg ; } </s>

X and Y are two things to compare using CODE . Emit the compare insn and return the rtx for register 0 in the proper mode .


<s> bool convertSetCCLogicToBitwiseLogic ( EVT VT ) const override { return VT . isScalarInteger ( ) ; } </s>

Use bitwise logic to make pairs of compares more efficient .


<s> static int mn10300_address_cost ( rtx x , machine_mode mode ATTRIBUTE_UNUSED , addr_space_t as ATTRIBUTE_UNUSED , bool speed ) { HOST_WIDE_INT i ; rtx base , index ; switch ( GET_CODE ( x ) ) { case CONST : case SYMBOL_REF : case LABEL_REF : return speed ? 1 : 4 ; case REG : case SUBREG : case POST_INC : return 0 ; case POST_MODIFY : i = ( CONST_INT_P ( XEXP ( x , 1 ) ) ? INTVAL ( XEXP ( x , 1 ) ) : 0x12345678 ) ; if ( IN_RANGE ( i , - 128 , 127 ) ) return speed ? 0 : 1 ; if ( speed ) return 1 ; if ( IN_RANGE ( i , - 0x800000 , 0x7fffff ) ) return 3 ; return 4 ; case PLUS : base = XEXP ( x , 0 ) ; index = XEXP ( x , 1 ) ; if ( register_operand ( index , SImode ) ) { if ( register_operand ( base , SImode ) ) return 1 ; base = XEXP ( x , 1 ) ; index = XEXP ( x , 0 ) ; } i = ( CONST_INT_P ( XEXP ( x , 1 ) ) ? INTVAL ( XEXP ( x , 1 ) ) : 0x12345678 ) ; if ( IN_RANGE ( i , - 128 , 127 ) ) return speed ? 0 : 1 ; if ( IN_RANGE ( i , - 32768 , 32767 ) ) return speed ? 0 : 2 ; return speed ? 2 : 6 ; default : return rtx_cost ( x , Pmode , MEM , 0 , speed ) ; } } </s>

For addresses , costs are relative to `` MOV ( Rm ) , Rn '' . For AM33 this is the 3-byte fully general instruction ; for MN103 this is the 2-byte form with an address register .


<s> bool AArch64CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) . isZero ( ) ) continue ; ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , F . getCallingConv ( ) ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; AArch64FunctionInfo * FuncInfo = MF . getInfo < AArch64FunctionInfo > ( ) ; uint64_t StackOffset = Handler . StackUsed ; if ( F . isVarArg ( ) ) { auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; if ( ! Subtarget . isTargetDarwin ( ) ) { return false ; } StackOffset = alignTo ( Handler . StackUsed , Subtarget . isTargetILP32 ( ) ? 4 : 8 ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( 4 , StackOffset , true ) ) ; } if ( doesCalleeRestoreStack ( F . getCallingConv ( ) , MF . getTarget ( ) . Options . GuaranteedTailCallOpt ) ) { StackOffset = alignTo ( StackOffset , 16 ) ; FuncInfo -> setArgumentStackToRestore ( StackOffset ) ; } FuncInfo -> setBytesInStackArgArea ( StackOffset ) ; auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; if ( Subtarget . hasCustomCallingConv ( ) ) Subtarget . getRegisterInfo ( ) -> UpdateCustomCalleeSavedRegs ( MF ) ; handleMustTailForwardedRegisters ( MIRBuilder , AssignFn ) ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


"sret virtual register not created in entry block"


<s> void WinEHStatePass :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool riscv_gpr_save_operation_p ( rtx op ) { unsigned len = XVECLEN ( op , 0 ) ; if ( len > ARRAY_SIZE ( gpr_save_reg_order ) ) return false ; for ( unsigned i = 0 ; i < len ; i ++ ) { rtx elt = XVECEXP ( op , 0 , i ) ; if ( i == 0 ) { if ( GET_CODE ( elt ) != UNSPEC_VOLATILE || GET_CODE ( XVECEXP ( elt , 0 , 0 ) ) != CONST_INT || XINT ( elt , 1 ) != UNSPECV_GPR_SAVE ) return false ; } else { unsigned expect_code = i < 3 ? CLOBBER : USE ; if ( GET_CODE ( elt ) != expect_code || ! REG_P ( XEXP ( elt , 1 ) ) || ( REGNO ( XEXP ( elt , 1 ) ) != gpr_save_reg_order [ i ] ) ) return false ; } break ; } return true ; } </s>

Return true if it 's valid gpr_save pattern .


<s> FastISel * MipsTargetLowering :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) const { if ( ! funcInfo . MF -> getTarget ( ) . Options . EnableFastISel ) return TargetLowering :: createFastISel ( funcInfo , libInfo ) ; return Mips :: createFastISel ( funcInfo , libInfo ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> bool fusion_gpr_load_p ( rtx addis_reg , rtx addis_value , rtx target , rtx mem ) { rtx addr ; rtx base_reg ; if ( ! base_reg_operand ( addis_reg , GET_MODE ( addis_reg ) ) ) return false ; if ( ! base_reg_operand ( target , GET_MODE ( target ) ) ) return false ; if ( ! fusion_gpr_addis ( addis_value , GET_MODE ( addis_value ) ) ) return false ; if ( GET_CODE ( mem ) == ZERO_EXTEND || ( GET_CODE ( mem ) == SIGN_EXTEND && TARGET_P8_FUSION_SIGN ) ) mem = XEXP ( mem , 0 ) ; if ( ! MEM_P ( mem ) ) return false ; if ( ! fusion_gpr_mem_load ( mem , GET_MODE ( mem ) ) ) return false ; addr = XEXP ( mem , 0 ) ; if ( GET_CODE ( addr ) != PLUS && GET_CODE ( addr ) != LO_SUM ) return false ; if ( REGNO ( addis_reg ) != REGNO ( target ) ) { if ( reg_mentioned_p ( target , mem ) ) return false ; if ( ! peep2_reg_dead_p ( 2 , addis_reg ) ) return false ; if ( REG_P ( target ) && REGNO ( target ) == STACK_POINTER_REGNUM ) return false ; } base_reg = XEXP ( addr , 0 ) ; return REGNO ( addis_reg ) == REGNO ( base_reg ) ; } </s>

Return true if the peephole2 can combine a load involving a combination of an addis instruction and a load with an offset that can be fused together on a power8 .


<s> static void single_move_for_movmem ( rtx dst , rtx src , machine_mode mode , HOST_WIDE_INT offset ) { rtx scratch = gen_reg_rtx ( mode ) ; rtx srcmem , dstmem ; srcmem = adjust_address_nv ( src , mode , offset ) ; dstmem = adjust_address_nv ( dst , mode , offset ) ; emit_move_insn ( scratch , srcmem ) ; emit_move_insn ( dstmem , scratch ) ; } </s>

Adjust DST and SRC by OFFSET bytes , and generate one move in mode MODE .


<s> void NVPTXRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( NVPTX :: VRFrame , false ) ; MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


"sh_try_split_insn_simple n = %d i = \n"

Given an rtx x , which is assumed to be some expression that has been matched by the 'treg_set_expr ' predicate before , split and emit the insns that are necessary to calculate the expression and store the result in the T bit . The splitting is done recursively similar to 'try_split ' in emit-rt.c . Unfortunately we ca n't use 'try_split ' here directly , as it tries to invoke 'delete_insn ' which then causes the DF parts to bail out , because we currently are inside another gen_split * function and would invoke 'try_split ' in a reentrant way .


<s> bool PPCTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( Ty -> isVectorTy ( ) && AM . BaseOffs != 0 && ! Subtarget . hasP9Vector ( ) ) return false ; if ( AM . BaseOffs <= - ( 1LL << 16 ) || AM . BaseOffs >= ( 1LL << 16 ) - 1 ) return false ; if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( AM . HasBaseReg && AM . BaseOffs ) return false ; break ; case 2 : if ( AM . HasBaseReg || AM . BaseOffs ) return false ; break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> const TPCAAResult & getResult ( ) const { return * Result ; } </s>

Get the result of an analysis pass for a given IR unit .


<s>
ARMBaseTargetMachine
::
ARMBaseTargetMachine
(
const
Target
&
T
,
const
Triple
&
TT
,
StringRef
CPU
,
StringRef
FS
,
const
TargetOptions
&
Options
,
Optional
<
Reloc
::
Model
>
RM
,
CodeModel
::
Model
CM
,
CodeGenOpt
::
Level
OL
,
bool
isLittle
)
:
LLVMTargetMachine
(
T
,
computeDataLayout
(
TT
,
CPU
,
Options
,
isLittle
)
,
TT
,
CPU
,
FS
,
Options
,
getEffectiveRelocModel
(
TT
,
RM
)
,
CM
,
OL
)
,
TargetABI
(
computeTargetABI
(
TT
,
CPU
,
Options
)
)
,
TLOF
(
createTLOF
(
getTargetTriple
(
)
)
)
,
Subtarget
(
TT
,
CPU
,
FS
,
*
this
,
isLittle
)
,
isLittle
(
isLittle
)
{
if
(
Options
.
FloatABIType
==
FloatABI
::
Default
)
this
->
Options
.
FloatABIType
=
Subtarget
.
isTargetHardFloat
(
)
FloatABI
::
Hard
:
FloatABI
::
Soft
;
if
(
Options
.
EABIVersion
==
EABI
::
Default
||
Options
.
EABIVersion
==
EABI
::
Unknown
)
{
if
(
Subtarget
.
isTargetGNUAEABI
(
)
||
Subtarget
.
isTargetMuslAEABI
(
)
)
this
->
Options
.
EABIVersion
=
EABI
::
GNU
;
else
this
->
Options
.
EABIVersion
=
EABI
::
EABI5
;
}
initAsmInfo
(
)
;
if
(
!
Subtarget
.
isThumb
(
)
&&
!
Subtarget
.
hasARMOps
(
)
)
report_fatal_error
(
"CPU: '"
+
Subtarget
.
getCPUString
(
)
+
"' does not "
"support ARM mode execution!"
)
;
}
</s>

ARM
ARM
ARM
ARM
"CPU: '"
"' does not "
"support ARM mode execution!"


<s>
void
RISCVMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
unsigned
Size
=
Desc
.
getSize
(
)
;
if
(
MI
.
getOpcode
(
)
==
RISCV
::
PseudoCALL
||
MI
.
getOpcode
(
)
==
RISCV
::
PseudoTAIL
)
{
expandFunctionCall
(
MI
,
OS
,
Fixups
,
STI
)
;
MCNumEmitted
+=
2
;
return
;
}
if
(
MI
.
getOpcode
(
)
==
RISCV
::
PseudoAddTPRel
)
{
expandAddTPRel
(
MI
,
OS
,
Fixups
,
STI
)
;
MCNumEmitted
+=
1
;
return
;
}
switch
(
Size
)
{
default
:
llvm_unreachable
(
"Unhandled encodeInstruction length!"
)
;
case
2
:
{
uint16_t
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
support
::
endian
::
write
<
uint16_t
>
(
OS
,
Bits
,
support
::
little
)
;
break
;
}
case
4
:
{
uint32_t
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
support
::
endian
::
write
(
OS
,
Bits
,
support
::
little
)
;
break
;
}
}
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .

RISCV
RISCV
RISCV::PseudoCALL
RISCV::PseudoTAIL
2
RISCV::PseudoAddTPRel
1
"Unhandled encodeInstruction length!"
2
support::endian
support::little
4
support::endian
support::little


<s> int frv_acc_group ( rtx insn ) { if ( frv_cpu_type == FRV_CPU_FR550 ) { subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , NONCONST ) if ( REG_P ( * iter ) ) { unsigned int regno = REGNO ( * iter ) ; if ( ACC_P ( regno ) ) return ( regno - ACC_FIRST ) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN ; if ( ACCG_P ( regno ) ) return ( regno - ACCG_FIRST ) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN ; } } return ACC_GROUP_NONE ; } </s>

Return the value of INSN 's acc_group attribute .


<s> bool X86FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( MI ) ; if ( MBB . isEHFuncletEntry ( ) && STI . is32Bit ( ) && STI . isOSWindows ( ) ) return true ; const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Opc = STI . is64Bit ( ) ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool isLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! isLiveIn ) MBB . addLiveIn ( Reg ) ; bool CanKill = ! isLiveIn ; if ( CanKill ) { for ( MCRegAliasIterator AReg ( Reg , TRI , false ) ; AReg . isValid ( ) ; ++ AReg ) { if ( MRI . isLiveIn ( * AReg ) ) { CanKill = false ; break ; } } } BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , getKillRegState ( CanKill ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MVT VT = MVT :: Other ; if ( X86 :: VK16RegClass . contains ( Reg ) ) VT = STI . hasBWI ( ) ? MVT :: v64i1 : MVT :: v16i1 ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg , VT ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - 1 ] . getFrameIdx ( ) , RC , TRI ) ; -- MI ; MI -> setFlag ( MachineInstr :: FrameSetup ) ; ++ MI ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static rtx frv_expand_load_builtin ( enum insn_code icode , enum machine_mode target_mode , tree arglist , rtx target ) { rtx op0 = frv_read_argument ( & arglist ) ; rtx cookie = frv_io_address_cookie ( op0 ) ; if ( target == 0 || ! REG_P ( target ) ) target = gen_reg_rtx ( target_mode ) ; op0 = frv_volatile_memref ( insn_data [ icode ] . operand [ 0 ] . mode , op0 ) ; convert_move ( target , op0 , 1 ) ; emit_insn ( GEN_FCN ( icode ) ( copy_rtx ( op0 ) , cookie , GEN_INT ( FRV_IO_READ ) ) ) ; cfun -> machine -> has_membar_p = 1 ; return target ; } </s>

Expand a __builtin_read * function . ICODE is the instruction code for the membar and TARGET_MODE is the mode that the loaded value should have .


<s>
const
MCPhysReg
*
AArch64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_AArch64_NoRegs_SaveList
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_AArch64_AllRegs_SaveList
;
else
return
CSR_AArch64_AAPCS_SaveList
;
}
</s>


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s>
bool
MOSAsmPrinter
::
PrintAsmOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
const
char
*
ExtraCode
,
raw_ostream
&
OS
)
{
if
(
!
AsmPrinter
::
PrintAsmOperand
(
MI
,
OpNo
,
ExtraCode
,
OS
)
)
return
false
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNo
)
;
const
MOSRegisterInfo
&
TRI
=
*
MO
.
getParent
(
)
->
getMF
(
)
->
getSubtarget
<
MOSSubtarget
>
(
)
.
getRegisterInfo
(
)
;
switch
(
MO
.
getType
(
)
)
{
default
:
errs
(
)
<<
"Unsupported inline asm operand: "
<<
MO
<<
"\n"
;
return
true
;
case
MachineOperand
::
MO_Immediate
:
OS
<<
MO
.
getImm
(
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
OS
<<
MO
.
getGlobal
(
)
->
getName
(
)
;
break
;
case
MachineOperand
::
MO_Register
:
Register
Reg
=
MO
.
getReg
(
)
;
if
(
MOS
::
Imag16RegClass
.
contains
(
Reg
)
||
MOS
::
Imag8RegClass
.
contains
(
Reg
)
)
OS
<<
"mos8("
<<
TRI
.
getImag8SymbolName
(
Reg
)
<<
")"
;
else
OS
<<
TRI
.
getRegAsmName
(
Reg
)
;
break
;
}
return
false
;
}
</s>

PrintAsmOperand - Print out an operand for an inline asm expression .

MOS
MOS
MOS
MOS
"Unsupported inline asm operand: "
"\n"
MOS::Imag16RegClass
MOS::Imag8RegClass
"mos8("
")"


<s> void AMDGPUAsmPrinter :: emitFunctionBodyEnd ( ) { const SIMachineFunctionInfo & MFI = * MF -> getInfo < SIMachineFunctionInfo > ( ) ; if ( ! MFI . isEntryFunction ( ) ) return ; if ( TM . getTargetTriple ( ) . getOS ( ) != Triple :: AMDHSA || isHsaAbiVersion2 ( getGlobalSTI ( ) ) ) return ; auto & Streamer = getTargetStreamer ( ) -> getStreamer ( ) ; auto & Context = Streamer . getContext ( ) ; auto & ObjectFileInfo = * Context . getObjectFileInfo ( ) ; auto & ReadOnlySection = * ObjectFileInfo . getReadOnlySection ( ) ; Streamer . PushSection ( ) ; Streamer . SwitchSection ( & ReadOnlySection ) ; Streamer . emitValueToAlignment ( 64 , 0 , 1 , 0 ) ; if ( ReadOnlySection . getAlignment ( ) < 64 ) ReadOnlySection . setAlignment ( Align ( 64 ) ) ; const GCNSubtarget & STM = MF -> getSubtarget < GCNSubtarget > ( ) ; SmallString < 128 > KernelName ; getNameWithPrefix ( KernelName , & MF -> getFunction ( ) ) ; getTargetStreamer ( ) -> EmitAmdhsaKernelDescriptor ( STM , KernelName , getAmdhsaKernelDescriptor ( * MF , CurrentProgramInfo ) , CurrentProgramInfo . NumVGPRsForWavesPerEU , CurrentProgramInfo . NumSGPRsForWavesPerEU - IsaInfo :: getNumExtraSGPRs ( & STM , CurrentProgramInfo . VCCUsed , CurrentProgramInfo . FlatUsed ) , CurrentProgramInfo . VCCUsed , CurrentProgramInfo . FlatUsed ) ; Streamer . PopSection ( ) ; } </s>

Targets can override this to emit stuff after the last basic block in the function .


<s> static bool aarch64_pragma_target_parse ( tree args , tree pop_target ) { if ( args ) { if ( ! aarch64_process_target_attr ( args ) ) return false ; aarch64_override_options_internal ( & global_options ) ; } else { pop_target = pop_target ? pop_target : target_option_default_node ; cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( pop_target ) ) ; } target_option_current_node = build_target_option_node ( & global_options , & global_options_set ) ; aarch64_reset_previous_fndecl ( ) ; cpp_options * cpp_opts = cpp_get_options ( parse_in ) ; unsigned char saved_warn_unused_macros = cpp_opts -> warn_unused_macros ; cpp_opts -> warn_unused_macros = 0 ; cpp_force_token_locations ( parse_in , BUILTINS_LOCATION ) ; aarch64_update_cpp_builtins ( parse_in ) ; cpp_stop_forcing_token_locations ( parse_in ) ; cpp_opts -> warn_unused_macros = saved_warn_unused_macros ; if ( pop_target ) aarch64_save_restore_target_globals ( pop_target ) ; return true ; } </s>

Hook to validate the current # pragma GCC target and set the state , and update the macros based on what was changed . If ARGS is NULL , then POP_TARGET is used to reset the options .


<s> Optional < unsigned > AArch64InstrInfo :: getUnscaledLdSt ( unsigned Opc ) { switch ( Opc ) { default : return { } ; case AArch64 :: PRFMui : return AArch64 :: PRFUMi ; case AArch64 :: LDRXui : return AArch64 :: LDURXi ; case AArch64 :: LDRWui : return AArch64 :: LDURWi ; case AArch64 :: LDRBui : return AArch64 :: LDURBi ; case AArch64 :: LDRHui : return AArch64 :: LDURHi ; case AArch64 :: LDRSui : return AArch64 :: LDURSi ; case AArch64 :: LDRDui : return AArch64 :: LDURDi ; case AArch64 :: LDRQui : return AArch64 :: LDURQi ; case AArch64 :: LDRBBui : return AArch64 :: LDURBBi ; case AArch64 :: LDRHHui : return AArch64 :: LDURHHi ; case AArch64 :: LDRSBXui : return AArch64 :: LDURSBXi ; case AArch64 :: LDRSBWui : return AArch64 :: LDURSBWi ; case AArch64 :: LDRSHXui : return AArch64 :: LDURSHXi ; case AArch64 :: LDRSHWui : return AArch64 :: LDURSHWi ; case AArch64 :: LDRSWui : return AArch64 :: LDURSWi ; case AArch64 :: STRXui : return AArch64 :: STURXi ; case AArch64 :: STRWui : return AArch64 :: STURWi ; case AArch64 :: STRBui : return AArch64 :: STURBi ; case AArch64 :: STRHui : return AArch64 :: STURHi ; case AArch64 :: STRSui : return AArch64 :: STURSi ; case AArch64 :: STRDui : return AArch64 :: STURDi ; case AArch64 :: STRQui : return AArch64 :: STURQi ; case AArch64 :: STRBBui : return AArch64 :: STURBBi ; case AArch64 :: STRHHui : return AArch64 :: STURHHi ; } } </s>

Returns the unscaled load/store for the scaled load/store opcode , if there is a corresponding unscaled variant available .


<s> static tree add_attribute ( const char * name , tree attrs ) { return tree_cons ( get_identifier ( name ) , NULL_TREE , attrs ) ; } </s>


<s>
void
AVRInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
;
if
(
AVR
::
GPR8RegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
Opc
=
AVR
::
MOVRdRr
;
}
else
if
(
AVR
::
DREGSRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
Opc
=
AVR
::
MOVWRdRr
;
}
else
if
(
SrcReg
==
AVR
::
SP
&&
AVR
::
DREGSRegClass
.
contains
(
DestReg
)
)
{
Opc
=
AVR
::
SPREAD
;
}
else
if
(
DestReg
==
AVR
::
SP
&&
AVR
::
DREGSRegClass
.
contains
(
SrcReg
)
)
{
Opc
=
AVR
::
SPWRITE
;
}
else
{
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>

AVR
AVR
AVR::GPR8RegClass
AVR::MOVRdRr
AVR::DREGSRegClass
AVR::MOVWRdRr
AVR::SP
AVR::DREGSRegClass
AVR::SPREAD
AVR::SP
AVR::DREGSRegClass
AVR::SPWRITE
"Impossible reg-to-reg copy"


"Copy structure (byval *) arguments to stack"

getPassName - Return a nice clean name for a pass .


<s> static rtx nvptx_function_value ( const_tree type , const_tree func ATTRIBUTE_UNUSED , bool outgoing ) { int unsignedp = TYPE_UNSIGNED ( type ) ; machine_mode orig_mode = TYPE_MODE ( type ) ; machine_mode mode = promote_function_mode ( type , orig_mode , & unsignedp , NULL_TREE , 1 ) ; if ( outgoing ) return gen_rtx_REG ( mode , NVPTX_RETURN_REGNUM ) ; if ( cfun -> machine -> start_call == NULL_RTX ) return gen_rtx_REG ( mode , NVPTX_RETURN_REGNUM ) ; return gen_reg_rtx ( mode ) ; } </s>

TARGET_FUNCTION_VALUE implementation . Returns an RTX representing the place where function FUNC returns or receives a value of data type TYPE .


<s> static bool pdp11_rtx_costs ( rtx x , machine_mode mode , int outer_code ATTRIBUTE_UNUSED , int opno ATTRIBUTE_UNUSED , int * total , bool speed ATTRIBUTE_UNUSED ) { int code = GET_CODE ( x ) ; switch ( code ) { case CONST_INT : if ( INTVAL ( x ) == 0 || INTVAL ( x ) == - 1 || INTVAL ( x ) == 1 ) { * total = 0 ; return true ; } case CONST : case LABEL_REF : case SYMBOL_REF : * total = 2 ; return true ; case CONST_DOUBLE : * total = 4 ; return true ; case MULT : if ( optimize_size ) * total = COSTS_N_INSNS ( 2 ) ; else * total = COSTS_N_INSNS ( 11 ) ; return false ; case DIV : if ( optimize_size ) * total = COSTS_N_INSNS ( 2 ) ; else * total = COSTS_N_INSNS ( 25 ) ; return false ; case MOD : if ( optimize_size ) * total = COSTS_N_INSNS ( 2 ) ; else * total = COSTS_N_INSNS ( 26 ) ; return false ; case ABS : * total = COSTS_N_INSNS ( 3 ) ; return false ; case ZERO_EXTEND : * total = COSTS_N_INSNS ( 1 ) ; return false ; case SIGN_EXTEND : if ( mode == HImode ) * total = COSTS_N_INSNS ( 1 ) ; else if ( mode == SImode ) * total = COSTS_N_INSNS ( 6 ) ; else * total = COSTS_N_INSNS ( 2 ) ; return false ; case ASHIFT : case LSHIFTRT : case ASHIFTRT : if ( optimize_size ) * total = COSTS_N_INSNS ( 1 ) ; else if ( mode == QImode ) { if ( GET_CODE ( XEXP ( x , 1 ) ) != CONST_INT ) * total = COSTS_N_INSNS ( 8 ) ; else * total = COSTS_N_INSNS ( INTVAL ( XEXP ( x , 1 ) ) ) ; } else if ( mode == HImode ) { if ( GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) { if ( abs ( INTVAL ( XEXP ( x , 1 ) ) ) == 1 ) * total = COSTS_N_INSNS ( 1 ) ; else * total = COSTS_N_INSNS ( 2.5 + 0.5 * INTVAL ( XEXP ( x , 1 ) ) ) ; } else * total = COSTS_N_INSNS ( 10 ) ; } else if ( mode == SImode ) { if ( GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) * total = COSTS_N_INSNS ( 2.5 + 0.5 * INTVAL ( XEXP ( x , 1 ) ) ) ; else * total = COSTS_N_INSNS ( 18 ) ; } return false ; default : return false ; } } </s>

This tries to approximate what pdp11_insn_cost would do , but without visibility into the actual instruction being generated it 's inevitably a rough approximation .


<s> void init_cumulative_args ( CUMULATIVE_ARGS * cum , tree fntype , rtx libname , tree fndecl , int caller ) { struct cgraph_local_info * i = NULL ; struct cgraph_node * target = NULL ; memset ( cum , 0 , sizeof ( * cum ) ) ; if ( fndecl ) { target = cgraph_node :: get ( fndecl ) ; if ( target ) { target = target -> function_symbol ( ) ; i = cgraph_node :: local_info ( target -> decl ) ; cum -> call_abi = ix86_function_abi ( target -> decl ) ; } else cum -> call_abi = ix86_function_abi ( fndecl ) ; } else cum -> call_abi = ix86_function_type_abi ( fntype ) ; cum -> caller = caller ; cum -> nregs = ix86_regparm ; if ( TARGET_64BIT ) { cum -> nregs = ( cum -> call_abi == SYSV_ABI ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX ) ; } if ( TARGET_SSE ) { cum -> sse_nregs = SSE_REGPARM_MAX ; if ( TARGET_64BIT ) { cum -> sse_nregs = ( cum -> call_abi == SYSV_ABI ? X86_64_SSE_REGPARM_MAX : X86_64_MS_SSE_REGPARM_MAX ) ; } } if ( TARGET_MMX ) cum -> mmx_nregs = MMX_REGPARM_MAX ; cum -> warn_avx512f = true ; cum -> warn_avx = true ; cum -> warn_sse = true ; cum -> warn_mmx = true ; if ( i && i -> local && i -> can_change_signature ) fntype = TREE_TYPE ( target -> decl ) ; cum -> stdarg = stdarg_p ( fntype ) ; cum -> maybe_vaarg = ( fntype ? ( ! prototype_p ( fntype ) || stdarg_p ( fntype ) ) : ! libname ) ; cum -> bnd_regno = FIRST_BND_REG ; cum -> bnds_in_bt = 0 ; cum -> force_bnd_pass = 0 ; if ( ! TARGET_64BIT ) { if ( stdarg_p ( fntype ) ) { cum -> nregs = 0 ; cum -> sse_nregs = 0 ; cum -> mmx_nregs = 0 ; cum -> warn_avx512f = false ; cum -> warn_avx = false ; cum -> warn_sse = false ; cum -> warn_mmx = false ; return ; } if ( fntype ) { unsigned int ccvt = ix86_get_callcvt ( fntype ) ; if ( ( ccvt & IX86_CALLCVT_THISCALL ) != 0 ) { cum -> nregs = 1 ; cum -> fastcall = 1 ; } else if ( ( ccvt & IX86_CALLCVT_FASTCALL ) != 0 ) { cum -> nregs = 2 ; cum -> fastcall = 1 ; } else cum -> nregs = ix86_function_regparm ( fntype , fndecl ) ; } cum -> float_in_sse = ix86_function_sseregparm ( fntype , fndecl , true ) ; } } </s>

Handle the INIT_CUMULATIVE_ARGS macro . Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is 0 .


<s> static int find_gr_spill ( enum ia64_frame_regs r , int try_locals ) { int regno ; if ( emitted_frame_related_regs [ r ] != 0 ) { regno = emitted_frame_related_regs [ r ] ; if ( regno >= LOC_REG ( 0 ) && regno < LOC_REG ( 80 - frame_pointer_needed ) && current_frame_info . n_local_regs < regno - LOC_REG ( 0 ) + 1 ) current_frame_info . n_local_regs = regno - LOC_REG ( 0 ) + 1 ; else if ( crtl -> is_leaf && regno >= GR_REG ( 1 ) && regno <= GR_REG ( 31 ) ) current_frame_info . gr_used_mask |= 1 << regno ; return regno ; } if ( crtl -> is_leaf ) { for ( regno = GR_REG ( 1 ) ; regno <= GR_REG ( 31 ) ; regno ++ ) if ( ! df_regs_ever_live_p ( regno ) && call_used_or_fixed_reg_p ( regno ) && ! fixed_regs [ regno ] && ! global_regs [ regno ] && ( ( current_frame_info . gr_used_mask >> regno ) & 1 ) == 0 && ! is_emitted ( regno ) ) { current_frame_info . gr_used_mask |= 1 << regno ; return regno ; } } if ( try_locals ) { regno = current_frame_info . n_local_regs ; while ( regno < ( 80 - frame_pointer_needed ) ) if ( ! is_emitted ( LOC_REG ( regno ++ ) ) ) { current_frame_info . n_local_regs = regno ; return LOC_REG ( regno - 1 ) ; } } return 0 ; } </s>

Helper function for ia64_compute_frame_size : find an appropriate general register to spill some special register to . SPECIAL_SPILL_MASK contains bits in GR0 to GR31 that have already been allocated by this routine . TRY_LOCALS is true if we should attempt to locate a local regnum .


<s> int mips_adjust_insn_length ( rtx_insn * insn , int length ) { if ( length == MAX_PIC_BRANCH_LENGTH && JUMP_P ( insn ) && INSN_CODE ( insn ) >= 0 && get_attr_type ( insn ) == TYPE_BRANCH ) { length = simplejump_p ( insn ) ? 0 : 8 ; length += BASE_INSN_LENGTH * mips_load_label_num_insns ( ) ; length += TARGET_COMPRESSION ? 2 : 4 ; } if ( CALL_P ( insn ) || ( TARGET_MIPS16 ? simplejump_p ( insn ) : JUMP_P ( insn ) ) ) length += TARGET_MIPS16 ? 2 : 4 ; if ( ! cfun -> machine -> ignore_hazard_length_p && INSN_P ( insn ) && INSN_CODE ( insn ) >= 0 ) switch ( get_attr_hazard ( insn ) ) { case HAZARD_NONE : break ; case HAZARD_DELAY : case HAZARD_FORBIDDEN_SLOT : length += NOP_INSN_LENGTH ; break ; case HAZARD_HILO : length += NOP_INSN_LENGTH * 2 ; break ; } return length ; } </s>

Return the length of INSN . LENGTH is the initial length computed by attributes in the machine-description file .


<s> void M680x0RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const M680x0FrameLowering * TFI = getFrameLowering ( MF ) ; MachineOperand & Disp = MI . getOperand ( FIOperandNum - 1 ) ; MachineOperand & Base = MI . getOperand ( FIOperandNum ) ; int Imm = ( int ) ( Disp . getImm ( ) ) ; int FIndex = ( int ) ( Base . getIndex ( ) ) ; bool AfterFPPop = false ; unsigned BasePtr ; if ( hasBasePointer ( MF ) ) BasePtr = ( FIndex < 0 ? FramePtr : getBaseRegister ( ) ) ; else if ( needsStackRealignment ( MF ) ) BasePtr = ( FIndex < 0 ? FramePtr : StackPtr ) ; else if ( AfterFPPop ) BasePtr = StackPtr ; else BasePtr = ( TFI -> hasFP ( MF ) ? FramePtr : StackPtr ) ; Base . ChangeToRegister ( BasePtr , false ) ; int FIOffset ; unsigned IgnoredFrameReg ; if ( AfterFPPop ) { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; FIOffset = MFI . getObjectOffset ( FIndex ) - TFI -> getOffsetOfLocalArea ( ) ; } else { FIOffset = TFI -> getFrameIndexReference ( MF , FIndex , IgnoredFrameReg ) ; } if ( BasePtr == StackPtr ) FIOffset += SPAdj ; long long Offset = FIOffset + Imm ; Disp . ChangeToImmediate ( Offset ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
Kind
==
OpKind
::
Reg
&&
"Invalid access!"
)
;
return
Reg
.
Num
;
}
</s>

Returns the register associated with this edge .


<s>
const
MCPhysReg
*
PPCRegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
const
PPCSubtarget
&
Subtarget
=
MF
->
getSubtarget
<
PPCSubtarget
>
(
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
{
if
(
!
TM
.
isPPC64
(
)
&&
Subtarget
.
isAIXABI
(
)
)
report_fatal_error
(
"AnyReg unimplemented on 32-bit AIX."
)
;
if
(
Subtarget
.
hasVSX
(
)
)
return
CSR_64_AllRegs_VSX_SaveList
;
if
(
Subtarget
.
hasAltivec
(
)
)
return
CSR_64_AllRegs_Altivec_SaveList
;
return
CSR_64_AllRegs_SaveList
;
}
if
(
TM
.
isPPC64
(
)
&&
MF
->
getInfo
<
PPCFunctionInfo
>
(
)
->
isSplitCSR
(
)
)
{
if
(
Subtarget
.
isAIXABI
(
)
)
report_fatal_error
(
"SplitCSR unimplemented on AIX."
)
;
return
CSR_SRV464_TLS_PE_SaveList
;
}
bool
SaveR2
=
MF
->
getRegInfo
(
)
.
isAllocatable
(
PPC
::
X2
)
&&
!
Subtarget
.
isUsingPCRelativeCalls
(
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
Cold
)
{
if
(
Subtarget
.
isAIXABI
(
)
)
report_fatal_error
(
"Cold calling unimplemented on AIX."
)
;
if
(
TM
.
isPPC64
(
)
)
{
if
(
Subtarget
.
hasAltivec
(
)
)
return
SaveR2
CSR_SVR64_ColdCC_R2_Altivec_SaveList
:
CSR_SVR64_ColdCC_Altivec_SaveList
;
return
SaveR2
CSR_SVR64_ColdCC_R2_SaveList
:
CSR_SVR64_ColdCC_SaveList
;
}
if
(
Subtarget
.
hasAltivec
(
)
)
return
CSR_SVR32_ColdCC_Altivec_SaveList
;
else
if
(
Subtarget
.
hasSPE
(
)
)
return
CSR_SVR32_ColdCC_SPE_SaveList
;
return
CSR_SVR32_ColdCC_SaveList
;
}
if
(
TM
.
isPPC64
(
)
)
{
if
(
Subtarget
.
hasAltivec
(
)
)
return
SaveR2
CSR_PPC64_R2_Altivec_SaveList
:
CSR_PPC64_Altivec_SaveList
;
return
SaveR2
CSR_PPC64_R2_SaveList
:
CSR_PPC64_SaveList
;
}
if
(
Subtarget
.
isAIXABI
(
)
)
return
CSR_AIX32_SaveList
;
if
(
Subtarget
.
hasAltivec
(
)
)
return
CSR_SVR432_Altivec_SaveList
;
else
if
(
Subtarget
.
hasSPE
(
)
)
return
CSR_SVR432_SPE_SaveList
;
return
CSR_SVR432_SaveList
;
}
</s>

PowerPC
PPC
PPC
PPC
PPC
"AnyReg unimplemented on 32-bit AIX."
PPC
PPC
"SplitCSR unimplemented on AIX."
PPC::X2
"Cold calling unimplemented on AIX."
PPC
PPC
PPC
PPC
PPC
PPC


<s> int AArch64FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { return resolveFrameIndexReference ( MF , FI , FrameReg , MF . getFunction ( ) . hasFnAttribute ( Attribute :: SanitizeHWAddress ) , false ) . getBytes ( ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> bool ARMTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( Subtarget -> isThumb1Only ( ) ) return false ; const bool restrict_addressing_modes_for_nacl = Subtarget -> isTargetNaCl ( ) && ( N -> getOpcode ( ) == ISD :: LOAD || N -> getOpcode ( ) == ISD :: STORE ) ; if ( restrict_addressing_modes_for_nacl ) { return false ; } EVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == ISD :: SEXTLOAD ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; } else return false ; bool isInc ; bool isLegal = false ; if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = getARMIndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( ! isLegal ) return false ; if ( Ptr != Base ) { if ( Ptr == Offset && Op -> getOpcode ( ) == ISD :: ADD && ! Subtarget -> isThumb2 ( ) ) std :: swap ( Base , Offset ) ; if ( Ptr != Base ) return false ; } AM = isInc ? ISD :: POST_INC : ISD :: POST_DEC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .

ARM ARM ISD::MemIndexedMode ISD::LOAD ISD::STORE ISD::SEXTLOAD ARM ISD::ADD ISD::POST_INC ISD::POST_DEC


<s> bool AMDGPUTTIImpl :: getTgtMemIntrinsic ( IntrinsicInst * Inst , MemIntrinsicInfo & Info ) const { switch ( Inst -> getIntrinsicID ( ) ) { case Intrinsic :: amdgcn_atomic_inc : case Intrinsic :: amdgcn_atomic_dec : { auto * Ordering = dyn_cast < ConstantInt > ( Inst -> getArgOperand ( 2 ) ) ; auto * Volatile = dyn_cast < ConstantInt > ( Inst -> getArgOperand ( 4 ) ) ; if ( ! Ordering || ! Volatile ) return false ; unsigned OrderingVal = Ordering -> getZExtValue ( ) ; if ( OrderingVal > static_cast < unsigned > ( AtomicOrdering :: SequentiallyConsistent ) ) return false ; Info . PtrVal = Inst -> getArgOperand ( 0 ) ; Info . Ordering = static_cast < AtomicOrdering > ( OrderingVal ) ; Info . ReadMem = true ; Info . WriteMem = true ; Info . IsVolatile = ! Volatile -> isNullValue ( ) ; return true ; } default : return false ; } } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> StringRef getPassName ( ) const override { return ARM_BRANCH_TARGETS_NAME ; } </s>


<s> static rtx mips_force_address ( rtx x , machine_mode mode ) { if ( ! mips_legitimate_address_p ( mode , x , false ) ) x = force_reg ( Pmode , x ) ; return x ; } </s>

If X is not a valid address for mode MODE , force it into a register .


"Instruction should be in a basic block!"

"Generic instruction has unexpected implicit operands\n"

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s> uint64_t PPCFrameLowering :: getBasePointerSaveOffset ( ) const { return BasePointerSaveOffset ; } </s>

getBasePointerSaveOffset - Return the previous frame offset to save the base pointer .


<s> bool legitimate_pic_operand_p ( rtx x ) { rtx inner ; switch ( GET_CODE ( x ) ) { case CONST : inner = XEXP ( x , 0 ) ; if ( GET_CODE ( inner ) == PLUS && GET_CODE ( XEXP ( inner , 1 ) ) == CONST_INT ) inner = XEXP ( inner , 0 ) ; if ( GET_CODE ( inner ) == UNSPEC ) switch ( XINT ( inner , 1 ) ) { case UNSPEC_GOTOFF : return TARGET_64BIT ; case UNSPEC_TPOFF : x = XVECEXP ( inner , 0 , 0 ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_EXEC ) ; default : return false ; } case SYMBOL_REF : case LABEL_REF : return legitimate_pic_address_disp_p ( x ) ; default : return true ; } } </s>

Return true if OP is a legitimate general operand when generating PIC code . It is given that flag_pic is on and that OP satisfies CONSTANT_P or is a CONST_DOUBLE .


<s> bool AArch64PassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnablePromoteConstant ) addPass ( createAArch64PromoteConstantPass ( ) ) ; if ( ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE ) { bool OnlyOptimizeForSize = ( TM -> getOptLevel ( ) < CodeGenOpt :: Aggressive ) && ( EnableGlobalMerge == cl :: BOU_UNSET ) ; addPass ( createGlobalMergePass ( TM , 4095 , OnlyOptimizeForSize ) ) ; } if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createAArch64AddressTypePromotionPass ( ) ) ; return false ; } </s>


<s> static rtx loongarch_legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , machine_mode mode ) { rtx base , addr ; HOST_WIDE_INT offset ; if ( loongarch_tls_symbol_p ( x ) ) return loongarch_legitimize_tls_address ( x ) ; loongarch_split_plus ( x , & base , & offset ) ; if ( offset != 0 ) { if ( ! loongarch_valid_base_register_p ( base , mode , false ) ) base = copy_to_mode_reg ( Pmode , base ) ; addr = loongarch_add_offset ( NULL , base , offset ) ; return loongarch_force_address ( addr , mode ) ; } return x ; } </s>

This function is used to implement LEGITIMIZE_ADDRESS . If X can be legitimized in a way that the generic machinery might not expect , return a new address , otherwise return NULL . MODE is the mode of the memory being accessed .


<s>
static
void
fatal
(
const
char
*
msg
)
{
fprintf
(
stderr
,
"FATAL: %s\n"
,
msg
)
;
abort
(
)
;
}
</s>


<s>
void
XtensaRegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
MachineInstr
&
MI
=
*
II
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Couldn't reach here"
)
;
return
;
}
}
</s>