<s> bool ARM64AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { const MachineOperand & MO = MI -> getOperand ( OpNum ) ; if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'w' : case 'x' : if ( MO . isReg ( ) ) return printAsmMRegister ( MO , ExtraCode [ 0 ] , O ) ; if ( MO . isImm ( ) && MO . getImm ( ) == 0 ) { unsigned Reg = ExtraCode [ 0 ] == 'w' ? ARM64 :: WZR : ARM64 :: XZR ; O << ARM64InstPrinter :: getRegisterName ( Reg ) ; return false ; } printOperand ( MI , OpNum , O ) ; return false ; case 'b' : case 'h' : case 's' : case 'd' : case 'q' : if ( MO . isReg ( ) ) { const TargetRegisterClass * RC ; switch ( ExtraCode [ 0 ] ) { case 'b' : RC = & ARM64 :: FPR8RegClass ; break ; case 'h' : RC = & ARM64 :: FPR16RegClass ; break ; case 's' : RC = & ARM64 :: FPR32RegClass ; break ; case 'd' : RC = & ARM64 :: FPR64RegClass ; break ; case 'q' : RC = & ARM64 :: FPR128RegClass ; break ; default : return true ; } return printAsmRegInClass ( MO , RC , false , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } } if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; if ( ARM64 :: GPR32allRegClass . contains ( Reg ) || ARM64 :: GPR64allRegClass . contains ( Reg ) ) return printAsmMRegister ( MO , 'x' , O ) ; return printAsmRegInClass ( MO , & ARM64 :: FPR128RegClass , true , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> const VEMCExpr * VEMCExpr :: create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { return new ( Ctx ) VEMCExpr ( Kind , Expr ) ; } </s>


<s> bool PPCTargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { if ( ! Subtarget . isSVR4ABI ( ) || ! Subtarget . isPPC64 ( ) ) return false ; if ( ! CI -> isTailCall ( ) ) return false ; const Function * Caller = CI -> getParent ( ) -> getParent ( ) ; auto Attr = Caller -> getFnAttribute ( "disable-tail-calls" ) ; if ( Attr . getValueAsString ( ) == "true" ) return false ; auto & TM = getTargetMachine ( ) ; if ( ! TM . Options . GuaranteedTailCallOpt && DisableSCO ) return false ; const Function * Callee = CI -> getCalledFunction ( ) ; if ( ! Callee || Callee -> isVarArg ( ) ) return false ; if ( ! areCallingConvEligibleForTCO_64SVR4 ( Caller -> getCallingConv ( ) , CI -> getCallingConv ( ) ) ) return false ; return getTargetMachine ( ) . shouldAssumeDSOLocal ( * Caller -> getParent ( ) , Callee ) ; } </s>

Return true if the target may be able emit the call instruction as a tail call .

PowerPC PPC PPC "disable-tail-calls" "true"


<s> bool PPCRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & ) const { return ( ( EnablePPC32RS && ! Subtarget . isPPC64 ( ) ) || ( EnablePPC64RS && Subtarget . isPPC64 ( ) ) ) ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> AArch64GenInstrInfo :: MachineOutlinerInstrType AArch64InstrInfo :: getOutliningType ( MachineInstr & MI ) const { MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; AArch64FunctionInfo * FuncInfo = MF -> getInfo < AArch64FunctionInfo > ( ) ; if ( FuncInfo -> getLOHRelated ( ) . count ( & MI ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . isDebugValue ( ) || MI . isIndirectDebugValue ( ) ) return MachineOutlinerInstrType :: Invisible ; if ( MI . isTerminator ( ) ) { if ( MI . getParent ( ) -> succ_empty ( ) ) return MachineOutlinerInstrType :: Legal ; return MachineOutlinerInstrType :: Illegal ; } if ( MI . isPosition ( ) ) return MachineOutlinerInstrType :: Illegal ; for ( const MachineOperand & MOP : MI . operands ( ) ) if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . modifiesRegister ( AArch64 :: LR , & RI ) || MI . readsRegister ( AArch64 :: LR , & RI ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . modifiesRegister ( AArch64 :: SP , & RI ) || MI . readsRegister ( AArch64 :: SP , & RI ) ) { if ( MI . mayLoadOrStore ( ) ) { unsigned Base ; int64_t Offset ; unsigned DummyWidth ; if ( ! getMemOpBaseRegImmOfsWidth ( MI , Base , Offset , DummyWidth , & RI ) || Base != AArch64 :: SP ) return MachineOutlinerInstrType :: Illegal ; int64_t MinOffset , MaxOffset ; unsigned DummyScale ; getMemOpInfo ( MI . getOpcode ( ) , DummyScale , DummyWidth , MinOffset , MaxOffset ) ; if ( Offset + 16 < MinOffset || Offset + 16 > MaxOffset ) return MachineOutlinerInstrType :: Illegal ; return MachineOutlinerInstrType :: Legal ; } return MachineOutlinerInstrType :: Illegal ; } return MachineOutlinerInstrType :: Legal ; } </s>

Returns how or if MIT should be outlined .


<s> void ix86_expand_vector_logical_operator ( enum rtx_code code , machine_mode mode , rtx operands [ ] ) { rtx op1 = NULL_RTX , op2 = NULL_RTX ; if ( GET_CODE ( operands [ 1 ] ) == SUBREG ) { op1 = operands [ 1 ] ; op2 = operands [ 2 ] ; } else if ( GET_CODE ( operands [ 2 ] ) == SUBREG ) { op1 = operands [ 2 ] ; op2 = operands [ 1 ] ; } if ( op1 && ! TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL && ( ( GET_CODE ( op2 ) == SUBREG || GET_CODE ( op2 ) == CONST_VECTOR ) ) && GET_MODE_CLASS ( GET_MODE ( SUBREG_REG ( op1 ) ) ) == MODE_VECTOR_FLOAT && GET_MODE_SIZE ( GET_MODE ( SUBREG_REG ( op1 ) ) ) == GET_MODE_SIZE ( mode ) && SUBREG_BYTE ( op1 ) == 0 && ( GET_CODE ( op2 ) == CONST_VECTOR || ( GET_MODE ( SUBREG_REG ( op1 ) ) == GET_MODE ( SUBREG_REG ( op2 ) ) && SUBREG_BYTE ( op2 ) == 0 ) ) && can_create_pseudo_p ( ) ) { rtx dst ; switch ( GET_MODE ( SUBREG_REG ( op1 ) ) ) { case V4SFmode : case V8SFmode : case V16SFmode : case V2DFmode : case V4DFmode : case V8DFmode : dst = gen_reg_rtx ( GET_MODE ( SUBREG_REG ( op1 ) ) ) ; if ( GET_CODE ( op2 ) == CONST_VECTOR ) { op2 = gen_lowpart ( GET_MODE ( dst ) , op2 ) ; op2 = force_reg ( GET_MODE ( dst ) , op2 ) ; } else { op1 = operands [ 1 ] ; op2 = SUBREG_REG ( operands [ 2 ] ) ; if ( ! nonimmediate_operand ( op2 , GET_MODE ( dst ) ) ) op2 = force_reg ( GET_MODE ( dst ) , op2 ) ; } op1 = SUBREG_REG ( op1 ) ; if ( ! nonimmediate_operand ( op1 , GET_MODE ( dst ) ) ) op1 = force_reg ( GET_MODE ( dst ) , op1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dst , gen_rtx_fmt_ee ( code , GET_MODE ( dst ) , op1 , op2 ) ) ) ; emit_move_insn ( operands [ 0 ] , gen_lowpart ( mode , dst ) ) ; return ; default : break ; } } if ( ! nonimmediate_operand ( operands [ 1 ] , mode ) ) operands [ 1 ] = force_reg ( mode , operands [ 1 ] ) ; if ( ! nonimmediate_operand ( operands [ 2 ] , mode ) ) operands [ 2 ] = force_reg ( mode , operands [ 2 ] ) ; ix86_fixup_binary_operands_no_copy ( code , mode , operands ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , gen_rtx_fmt_ee ( code , mode , operands [ 1 ] , operands [ 2 ] ) ) ) ; } </s>

Expand vector logical operation CODE ( AND , IOR , XOR ) in MODE with the given OPERANDS .


<s> void cris_reduce_compare ( rtx * relp , rtx * , rtx * op1p ) { rtx op1 = * op1p ; rtx_code code = GET_CODE ( * relp ) ; switch ( code ) { case LT : if ( op1 == const1_rtx ) code = LE ; break ; case LE : if ( op1 == constm1_rtx ) code = LT ; break ; case GE : if ( op1 == const1_rtx ) code = GT ; break ; case GT : if ( op1 == constm1_rtx ) code = GE ; break ; case GEU : if ( op1 == const1_rtx ) code = NE ; break ; case LTU : if ( op1 == const1_rtx ) code = EQ ; break ; case GTU : if ( op1 == const0_rtx ) code = NE ; break ; case LEU : if ( op1 == const0_rtx ) code = EQ ; break ; default : break ; } if ( code != GET_CODE ( * relp ) ) { * op1p = const0_rtx ; PUT_CODE ( * relp , code ) ; } } </s>

Try to change a comparison against a constant to be against zero , and an unsigned compare against zero to be an equality test . Beware : only valid for compares of integer-type operands . Also , note that we do n't use operand 0 at the moment .


<s> Relocator :: Result abs ( Relocation & pReloc , AArch64Relocator & pParent ) { ResolveInfo * rsym = pReloc . symInfo ( ) ; Relocator :: DWord A = pReloc . target ( ) + pReloc . addend ( ) ; Relocator :: DWord S = pReloc . symValue ( ) ; Relocation * dyn_rel = pParent . getRelRelMap ( ) . lookUp ( pReloc ) ; bool has_dyn_rel = ( dyn_rel != NULL ) ; LDSection & target_sect = pReloc . targetRef ( ) . frag ( ) -> getParent ( ) -> getSection ( ) ; if ( 0x0 == ( llvm :: ELF :: SHF_ALLOC & target_sect . flag ( ) ) ) { pReloc . target ( ) = S + A ; return Relocator :: OK ; } if ( rsym -> isLocal ( ) && has_dyn_rel ) { dyn_rel -> setAddend ( S + A ) ; } if ( ! rsym -> isLocal ( ) ) { if ( rsym -> reserved ( ) & AArch64Relocator :: ReservePLT ) { S = helper_get_PLT_address ( * rsym , pParent ) ; } if ( has_dyn_rel ) { if ( llvm :: ELF :: R_AARCH64_ABS64 == pReloc . type ( ) && llvm :: ELF :: R_AARCH64_RELATIVE == dyn_rel -> type ( ) ) { dyn_rel -> setAddend ( S + A ) ; } else { dyn_rel -> setAddend ( A ) ; return Relocator :: OK ; } } } pReloc . target ( ) = S + A ; return Relocator :: OK ; } </s>

Compute known bits for the absolute value .


<s> rtx mep_function_value ( const_tree type , const_tree func ATTRIBUTE_UNUSED ) { if ( TARGET_IVC2 && VECTOR_TYPE_P ( type ) ) return gen_rtx_REG ( TYPE_MODE ( type ) , 48 ) ; return gen_rtx_REG ( TYPE_MODE ( type ) , RETURN_VALUE_REGNUM ) ; } </s>

Implement FUNCTION_VALUE . All values are returned in $ 0 .


<s> static void mips_set_fast_mult_zero_zero_p ( struct mips_sim * state ) { if ( TARGET_MIPS16 || ! ISA_HAS_HILO ) mips_tuning_info . fast_mult_zero_zero_p = true ; else { unsigned int true_time = mips_mult_zero_zero_cost ( state , true ) ; unsigned int false_time = mips_mult_zero_zero_cost ( state , false ) ; mips_tuning_info . fast_mult_zero_zero_p = ( true_time <= false_time ) ; } } </s>

Check the relative speeds of `` MULT $ 0 , $ 0 '' and `` MTLO $ 0 ; MTHI $ 0 '' and set up mips_tuning_info.fast_mult_zero_zero_p accordingly . Prefer MULT -- which is shorter -- in the event of a tie .


<s> BitVector XtensaRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector reserved ( getNumRegs ( ) ) ; return reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool isUndef ( SDValue Op ) const { if ( Op . isMachineOpcode ( ) ) return Op . getMachineOpcode ( ) == TargetOpcode :: IMPLICIT_DEF ; return Op . getOpcode ( ) == ISD :: UNDEF ; } </s>

Return true if the result of this operation is always undefined .


<s>
void
CAHPInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MBBI
,
const
DebugLoc
&
DL
,
unsigned
DstReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
assert
(
CAHP
::
GPRRegClass
.
contains
(
DstReg
,
SrcReg
)
&&
"Impossible reg-to-reg copy"
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
CAHP
::
MOV
)
,
DstReg
)
.
addReg
(
SrcReg
)
;
}
</s>

CAHP
CAHP
CAHP::GPRRegClass
"Impossible reg-to-reg copy"
CAHP::MOV


<s> void buildLoad ( Register Val , const CCValAssign & VA ) { MachineMemOperand * MMO ; Register Addr = getStackAddress ( VA , MMO ) ; MIRBuilder . buildLoad ( Val , Addr , * MMO ) ; } </s>

Build and insert a G_LOAD instruction , while constructing the MachineMemOperand .


<s> bool MipsFastISel :: fastSelectInstruction ( const Instruction * I ) { if ( ! TargetSupported ) return false ; switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Load : return selectLoad ( I ) ; case Instruction :: Store : return selectStore ( I ) ; case Instruction :: SDiv : if ( ! selectBinaryOp ( I , ISD :: SDIV ) ) return selectDivRem ( I , ISD :: SDIV ) ; return true ; case Instruction :: UDiv : if ( ! selectBinaryOp ( I , ISD :: UDIV ) ) return selectDivRem ( I , ISD :: UDIV ) ; return true ; case Instruction :: SRem : if ( ! selectBinaryOp ( I , ISD :: SREM ) ) return selectDivRem ( I , ISD :: SREM ) ; return true ; case Instruction :: URem : if ( ! selectBinaryOp ( I , ISD :: UREM ) ) return selectDivRem ( I , ISD :: UREM ) ; return true ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return selectShift ( I ) ; case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : return selectLogicalOp ( I ) ; case Instruction :: Br : return selectBranch ( I ) ; case Instruction :: Ret : return selectRet ( I ) ; case Instruction :: Trunc : return selectTrunc ( I ) ; case Instruction :: ZExt : case Instruction :: SExt : return selectIntExt ( I ) ; case Instruction :: FPTrunc : return selectFPTrunc ( I ) ; case Instruction :: FPExt : return selectFPExt ( I ) ; case Instruction :: FPToSI : return selectFPToInt ( I , true ) ; case Instruction :: FPToUI : return selectFPToInt ( I , false ) ; case Instruction :: ICmp : case Instruction :: FCmp : return selectCmp ( I ) ; case Instruction :: Select : return selectSelect ( I ) ; } return false ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .

Mips Mips ISD::SDIV ISD::SDIV ISD::UDIV ISD::UDIV ISD::SREM ISD::SREM ISD::UREM ISD::UREM


<s> void TriCoreInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << "%" << StringRef ( getRegisterName ( RegNo ) ) . lower ( ) ; } </s>


<s> static bool rx_mode_dependent_address_p ( const_rtx addr , addr_space_t as ATTRIBUTE_UNUSED ) { if ( GET_CODE ( addr ) == CONST ) addr = XEXP ( addr , 0 ) ; switch ( GET_CODE ( addr ) ) { case PRE_DEC : case POST_INC : return true ; case MINUS : case PLUS : if ( ! REG_P ( XEXP ( addr , 0 ) ) ) return true ; addr = XEXP ( addr , 1 ) ; switch ( GET_CODE ( addr ) ) { case REG : return true ; case CONST_INT : if ( ( ( INTVAL ( addr ) & 3 ) == 0 ) && IN_RANGE ( INTVAL ( addr ) , 4 , 0xfffc ) ) return false ; return true ; case SYMBOL_REF : case LABEL_REF : return true ; case MULT : gcc_assert ( REG_P ( XEXP ( addr , 0 ) ) ) ; gcc_assert ( CONST_INT_P ( XEXP ( addr , 1 ) ) ) ; return true ; default : return true ; } case CONST_INT : case SYMBOL_REF : case LABEL_REF : case REG : return false ; default : return true ; } } </s>


"Basic block should contain at least a RET but is empty"

runOnMachineFunction - Emit the function body .


<s> static unsigned rs6000_add_stmt_cost ( class vec_info * vinfo , void * data , int count , enum vect_cost_for_stmt kind , struct _stmt_vec_info * stmt_info , tree vectype , int misalign , enum vect_cost_model_location where ) { rs6000_cost_data * cost_data = ( rs6000_cost_data * ) data ; unsigned retval = 0 ; if ( flag_vect_cost_model ) { int stmt_cost = rs6000_builtin_vectorization_cost ( kind , vectype , misalign ) ; stmt_cost += rs6000_adjust_vect_cost_per_stmt ( kind , stmt_info ) ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( vinfo , stmt_info ) ) count *= 50 ; retval = ( unsigned ) ( count * stmt_cost ) ; cost_data -> cost [ where ] += retval ; if ( ( kind == vec_to_scalar || kind == vec_perm || kind == vec_promote_demote || kind == vec_construct || kind == scalar_to_vec ) || ( where == vect_body && kind == vector_stmt ) ) rs6000_vect_nonmem = true ; } return retval ; } </s>


<s> static rtx_insn * rs6000_frame_related ( rtx_insn * insn , rtx reg , HOST_WIDE_INT val , rtx reg2 , rtx repl2 ) { rtx repl ; if ( REGNO ( reg ) == STACK_POINTER_REGNUM ) { gcc_checking_assert ( val == 0 ) ; repl = NULL_RTX ; } else repl = gen_rtx_PLUS ( Pmode , gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) , GEN_INT ( val ) ) ; rtx pat = PATTERN ( insn ) ; if ( ! repl && ! reg2 ) { if ( GET_CODE ( pat ) == PARALLEL ) for ( int i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) if ( GET_CODE ( XVECEXP ( pat , 0 , i ) ) == SET ) { rtx set = XVECEXP ( pat , 0 , i ) ; if ( ! REG_P ( SET_SRC ( set ) ) || ! fixed_reg_p ( REGNO ( SET_SRC ( set ) ) ) ) RTX_FRAME_RELATED_P ( set ) = 1 ; } RTX_FRAME_RELATED_P ( insn ) = 1 ; return insn ; } set_used_flags ( pat ) ; if ( GET_CODE ( pat ) == SET ) { if ( repl ) pat = simplify_replace_rtx ( pat , reg , repl ) ; if ( reg2 ) pat = simplify_replace_rtx ( pat , reg2 , repl2 ) ; } else if ( GET_CODE ( pat ) == PARALLEL ) { pat = shallow_copy_rtx ( pat ) ; XVEC ( pat , 0 ) = shallow_copy_rtvec ( XVEC ( pat , 0 ) ) ; for ( int i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) if ( GET_CODE ( XVECEXP ( pat , 0 , i ) ) == SET ) { rtx set = XVECEXP ( pat , 0 , i ) ; if ( repl ) set = simplify_replace_rtx ( set , reg , repl ) ; if ( reg2 ) set = simplify_replace_rtx ( set , reg2 , repl2 ) ; XVECEXP ( pat , 0 , i ) = set ; if ( ! REG_P ( SET_SRC ( set ) ) || ! fixed_reg_p ( REGNO ( SET_SRC ( set ) ) ) ) RTX_FRAME_RELATED_P ( set ) = 1 ; } } else gcc_unreachable ( ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , copy_rtx_if_shared ( pat ) ) ; return insn ; } </s>

Add to 'insn ' a note which is PATTERN ( INSN ) but with REG replaced with ( plus : P ( reg 1 ) VAL ) , and with REG2 replaced with RREG if REG2 is not NULL . It would be nice if dwarf2out_frame_debug_expr could deduce these equivalences by itself so it was n't necessary to hold its hand so much . Do n't be tempted to always supply d2_f_d_e with the actual cfa register , ie . r31 when we are using a hard frame pointer . That fails when saving regs off r1 , and sched moves the r31 setup past the reg saves .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> void PPCTTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP , OptimizationRemarkEmitter * ORE ) { if ( ST -> getCPUDirective ( ) == PPC :: DIR_A2 ) { UP . Partial = UP . Runtime = true ; UP . AllowExpensiveTripCount = true ; } BaseT :: getUnrollingPreferences ( L , SE , UP , ORE ) ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> static bool frv_registers_conflict_p ( rtx x ) { regstate_t flags ; flags = 0 ; if ( GET_CODE ( x ) == COND_EXEC ) { if ( for_each_rtx ( & XEXP ( x , 0 ) , frv_registers_conflict_p_1 , & flags ) ) return true ; flags |= frv_cond_flags ( XEXP ( x , 0 ) ) ; x = XEXP ( x , 1 ) ; } return for_each_rtx ( & x , frv_registers_conflict_p_1 , & flags ) ; } </s>

Return true if something in X might depend on an instruction in the current packet .


<s> const uint16_t * XCoreRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { XCore :: R4 , XCore :: R5 , XCore :: R6 , XCore :: R7 , XCore :: R8 , XCore :: R9 , XCore :: R10 , XCore :: LR , 0 } ; return CalleeSavedRegs ; } </s>


<s> void SystemZPassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createSystemZShortenInstPass ( getSystemZTargetMachine ( ) ) , false ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createSystemZElimComparePass ( getSystemZTargetMachine ( ) ) , false ) ; addPass ( createSystemZLongBranchPass ( getSystemZTargetMachine ( ) ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ


<s> static tree pdp11_guard_type ( void ) { return short_integer_type_node ; } </s>


"lr %%4,[status]\n\tadd %%4,%%4,6\t%s single insn loop start"

"mov %%4,%%%%st(1f)\t%s (single insn loop start) >> 2"

FIXME : This probably can be done using a define_split in arc.md . Alternately , generate rtx rather than output instructions .


"_reflect function should not have a body"

"_reflect's return type should be integer"

"Wrong number of operands to __nvvm_reflect function"

"Format of __nvvm__reflect function not recognized"

"Format of __nvvm_reflect function not recognized"

"Format of _reflect function not recognized"

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> std :: unique_ptr < MCObjectWriter > RISCVAsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { return createRISCVELFObjectWriter ( OS , OSABI , Is64Bit ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> X86TargetLowering :: ConstraintType X86TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'R' : case 'q' : case 'Q' : case 'f' : case 't' : case 'u' : case 'y' : case 'x' : case 'v' : case 'Y' : case 'l' : case 'k' : return C_RegisterClass ; case 'a' : case 'b' : case 'c' : case 'd' : case 'S' : case 'D' : case 'A' : return C_Register ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'G' : case 'C' : case 'e' : case 'Z' : return C_Other ; default : break ; } } else if ( Constraint . size ( ) == 2 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'Y' : switch ( Constraint [ 1 ] ) { default : break ; case 'z' : case '0' : return C_Register ; case 'i' : case 'm' : case 'k' : case 't' : case '2' : return C_RegisterClass ; } } } else if ( parseConstraintCode ( Constraint ) != X86 :: COND_INVALID ) return C_Other ; return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> unsigned X86TargetLowering :: getByValTypeAlignment ( Type * Ty , const DataLayout & DL ) const { if ( Subtarget -> is64Bit ( ) ) { unsigned TyAlign = DL . getABITypeAlignment ( Ty ) ; if ( TyAlign > 8 ) return TyAlign ; return 8 ; } unsigned Align = 4 ; if ( Subtarget -> hasSSE1 ( ) ) getMaxByValAlign ( Ty , Align ) ; return Align ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


<s> bool WebAssemblyAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { if ( Count == 0 ) return true ; for ( uint64_t i = 0 ; i < Count ; ++ i ) OS << char ( WebAssembly :: Nop ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> SMLoc getStartLoc ( ) const { return Start ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> bool AMDGPUPassConfig :: addPreISel ( ) { const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; addPass ( createFlattenCFGPass ( ) ) ; if ( ST . getGeneration ( ) > AMDGPUSubtarget :: NORTHERN_ISLANDS ) { addPass ( createStructurizeCFGPass ( ) ) ; addPass ( createSIAnnotateControlFlowPass ( ) ) ; } else { addPass ( createR600TextureIntrinsicsReplacer ( ) ) ; } return false ; } </s>


<s>
static
void
rs6000_file_start
(
void
)
{
char
buffer
[
80
]
;
const
char
*
start
=
buffer
;
FILE
*
file
=
asm_out_file
;
rs6000_default_cpu
=
TARGET_CPU_DEFAULT
;
default_file_start
(
)
;
if
(
flag_verbose_asm
)
{
sprintf
(
buffer
,
"\n%s rs6000/powerpc options:"
,
ASM_COMMENT_START
)
;
if
(
rs6000_default_cpu
!=
0
&&
rs6000_default_cpu
[
0
]
!=
'\0'
)
{
fprintf
(
file
,
"%s --with-cpu=%s"
,
start
,
rs6000_default_cpu
)
;
start
=
""
;
}
if
(
global_options_set
.
x_rs6000_cpu_index
)
{
fprintf
(
file
,
"%s -mcpu=%s"
,
start
,
processor_target_table
[
rs6000_cpu_index
]
.
name
)
;
start
=
""
;
}
if
(
global_options_set
.
x_rs6000_tune_index
)
{
fprintf
(
file
,
"%s -mtune=%s"
,
start
,
processor_target_table
[
rs6000_tune_index
]
.
name
)
;
start
=
""
;
}
if
(
PPC405_ERRATUM77
)
{
fprintf
(
file
,
"%s PPC405CR_ERRATUM77"
,
start
)
;
start
=
""
;
}
switch
(
rs6000_sdata
)
{
case
SDATA_NONE
:
fprintf
(
file
,
"%s -msdata=none"
,
start
)
;
start
=
""
;
break
;
case
SDATA_DATA
:
fprintf
(
file
,
"%s -msdata=data"
,
start
)
;
start
=
""
;
break
;
case
SDATA_SYSV
:
fprintf
(
file
,
"%s -msdata=sysv"
,
start
)
;
start
=
""
;
break
;
case
SDATA_EABI
:
fprintf
(
file
,
"%s -msdata=eabi"
,
start
)
;
start
=
""
;
break
;
}
if
(
rs6000_sdata
&&
g_switch_value
)
{
fprintf
(
file
,
"%s -G %d"
,
start
,
g_switch_value
)
;
start
=
""
;
}
if
(
*
start
==
'\0'
)
putc
(
'\n'
,
file
)
;
}
if
(
rs6000_default_cpu
==
0
||
rs6000_default_cpu
[
0
]
==
'\0'
||
!
global_options_set
.
x_rs6000_cpu_index
)
{
fputs
(
"\t.machine "
,
asm_out_file
)
;
if
(
(
rs6000_isa_flags
&
OPTION_MASK_MODULO
)
!=
0
)
fputs
(
"power9\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_DIRECT_MOVE
)
!=
0
)
fputs
(
"power8\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_POPCNTD
)
!=
0
)
fputs
(
"power7\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_CMPB
)
!=
0
)
fputs
(
"power6\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_POPCNTB
)
!=
0
)
fputs
(
"power5\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_MFCRF
)
!=
0
)
fputs
(
"power4\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_POWERPC64
)
!=
0
)
fputs
(
"ppc64\n"
,
asm_out_file
)
;
else
fputs
(
"ppc\n"
,
asm_out_file
)
;
}
if
(
DEFAULT_ABI
==
ABI_ELFv2
)
fprintf
(
file
,
"\t.abiversion 2\n"
)
;
}
</s>

Do anything needed at the start of the asm file .


<s> void VEInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << '%' << StringRef ( getRegisterName ( RegNo ) ) . lower ( ) ; } </s>


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createAMDGPUELFObjectWriter ( OS ) ; } </s>


<s> X86TargetMachine :: X86TargetMachine ( const Module & M , const std :: string & FS , bool is64Bit ) : Subtarget ( M , FS , is64Bit ) , DataLayout ( Subtarget . getDataLayout ( ) ) , FrameInfo ( TargetFrameInfo :: StackGrowsDown , Subtarget . getStackAlignment ( ) , Subtarget . is64Bit ( ) ? - 8 : - 4 ) , InstrInfo ( * this ) , JITInfo ( * this ) , TLInfo ( * this ) { DefRelocModel = getRelocationModel ( ) ; if ( getRelocationModel ( ) == Reloc :: Default ) { if ( Subtarget . isTargetDarwin ( ) || ( Subtarget . isTargetCygMing ( ) && ! Subtarget . isTargetWin64 ( ) ) ) setRelocationModel ( Reloc :: DynamicNoPIC ) ; else setRelocationModel ( Reloc :: Static ) ; } if ( Subtarget . isTargetELF ( ) && getRelocationModel ( ) == Reloc :: DynamicNoPIC ) setRelocationModel ( Reloc :: Static ) ; if ( Subtarget . is64Bit ( ) ) { if ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) setRelocationModel ( Reloc :: PIC_ ) ; if ( getCodeModel ( ) == CodeModel :: Default ) setCodeModel ( CodeModel :: Small ) ; } if ( Subtarget . isTargetCygMing ( ) ) Subtarget . setPICStyle ( PICStyles :: WinPIC ) ; else if ( Subtarget . isTargetDarwin ( ) ) { if ( Subtarget . is64Bit ( ) ) Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; else Subtarget . setPICStyle ( PICStyles :: Stub ) ; } else if ( Subtarget . isTargetELF ( ) ) { if ( Subtarget . is64Bit ( ) ) Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; else Subtarget . setPICStyle ( PICStyles :: GOT ) ; } } </s>


<s> static bool sh_handle_option ( size_t code , const char * arg ATTRIBUTE_UNUSED , int value ATTRIBUTE_UNUSED ) { switch ( code ) { case OPT_m1 : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH1 ; return true ; case OPT_m2 : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH2 ; return true ; case OPT_m2a : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH2A ; return true ; case OPT_m2a_nofpu : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH2A_NOFPU ; return true ; case OPT_m2a_single : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH2A_SINGLE ; return true ; case OPT_m2a_single_only : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH2A_SINGLE_ONLY ; return true ; case OPT_m2e : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH2E ; return true ; case OPT_m3 : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH3 ; return true ; case OPT_m3e : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH3E ; return true ; case OPT_m4 : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH4 ; return true ; case OPT_m4_nofpu : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH4_NOFPU ; return true ; case OPT_m4_single : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH4_SINGLE ; return true ; case OPT_m4_single_only : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH4_SINGLE_ONLY ; return true ; case OPT_m4a : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH4A ; return true ; case OPT_m4a_nofpu : case OPT_m4al : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH4A_NOFPU ; return true ; case OPT_m4a_single : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH4A_SINGLE ; return true ; case OPT_m4a_single_only : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH4A_SINGLE_ONLY ; return true ; case OPT_m5_32media : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH5_32MEDIA ; return true ; case OPT_m5_32media_nofpu : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH5_32MEDIA_NOFPU ; return true ; case OPT_m5_64media : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH5_64MEDIA ; return true ; case OPT_m5_64media_nofpu : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH5_64MEDIA_NOFPU ; return true ; case OPT_m5_compact : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH5_COMPACT ; return true ; case OPT_m5_compact_nofpu : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH5_COMPACT_NOFPU ; return true ; default : return true ; } } </s>


<s> const char * m68k_cpp_cpu_family ( const char * prefix ) { if ( ! m68k_cpu_entry ) return NULL ; return concat ( "__m" , prefix , "_family_" , m68k_cpu_entry -> family , NULL ) ; } </s>

Generate a macro of the form __mPREFIX_family_NAME , where PREFIX is the given argument and NAME is the name of the representative device for the -mcpu argument 's family . Return NULL if -mcpu was not passed .


<s> const RegisterBankInfo * getRegBankInfo ( ) const override { return RegBankInfo . get ( ) ; } </s>

If the information for the register banks is available , return it .


"value of -mfixed-range must have form REG1-REG2"

Parse the -mfixed-range= option string .


"Odd number of callee-saved regs to spill!"

"Expected GPR64 callee-saved register pair!"

"Expected FPR64 callee-saved register pair!"

"Offset out of bounds for LDP immediate"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> void HexagonPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; addPass ( createAtomicExpandPass ( TM ) ) ; if ( ! NoOpt ) { if ( EnableLoopPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableCommGEP ) addPass ( createHexagonCommonGEP ( ) ) ; if ( EnableGenExtract ) addPass ( createHexagonGenExtract ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static void restore_saved_cr ( rtx reg , int using_mfcr_multiple , bool exit_func ) { int count = 0 ; int i ; if ( using_mfcr_multiple ) { for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) count ++ ; gcc_assert ( count ) ; } if ( using_mfcr_multiple && count > 1 ) { rtx_insn * insn ; rtvec p ; int ndx ; p = rtvec_alloc ( count ) ; ndx = 0 ; for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) { rtvec r = rtvec_alloc ( 2 ) ; RTVEC_ELT ( r , 0 ) = reg ; RTVEC_ELT ( r , 1 ) = GEN_INT ( 1 << ( 7 - i ) ) ; RTVEC_ELT ( p , ndx ) = gen_rtx_SET ( gen_rtx_REG ( CCmode , CR0_REGNO + i ) , gen_rtx_UNSPEC ( CCmode , r , UNSPEC_MOVESI_TO_CR ) ) ; ndx ++ ; } insn = emit_insn ( gen_rtx_PARALLEL ( VOIDmode , p ) ) ; gcc_assert ( ndx == count ) ; if ( ! exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap ) { for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) add_reg_note ( insn , REG_CFA_RESTORE , gen_rtx_REG ( SImode , CR0_REGNO + i ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } else for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) { rtx insn = emit_insn ( gen_movsi_to_cr_one ( gen_rtx_REG ( CCmode , CR0_REGNO + i ) , reg ) ) ; if ( ! exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap ) { add_reg_note ( insn , REG_CFA_RESTORE , gen_rtx_REG ( SImode , CR0_REGNO + i ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } if ( ! exit_func && DEFAULT_ABI != ABI_ELFv2 && ( DEFAULT_ABI == ABI_V4 || flag_shrink_wrap ) ) { rtx_insn * insn = get_last_insn ( ) ; rtx cr = gen_rtx_REG ( SImode , CR2_REGNO ) ; add_reg_note ( insn , REG_CFA_RESTORE , cr ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } </s>


<s> bool SITargetLowering :: enableAggressiveFMAFusion ( EVT VT ) const { return true ; } </s>

Return true if target always benefits from combining into FMA for a given value type .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
k_Immediate
:
OS
<<
"Imm<"
<<
*
Imm
.
Val
<<
">"
;
break
;
case
k_Memory
:
OS
<<
"Mem<"
;
OS
<<
Mem
.
Base
;
OS
<<
", "
;
OS
<<
*
Mem
.
Off
;
OS
<<
">"
;
break
;
case
k_Register
:
OS
<<
"Register<"
<<
Reg
.
RegNum
<<
">"
;
break
;
case
k_Token
:
OS
<<
Tok
.
Data
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s>
bool
AMDGPUAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
SetupMachineFunction
(
MF
)
;
if
(
OutStreamer
.
hasRawTextSupport
(
)
)
{
OutStreamer
.
EmitRawText
(
"@"
+
MF
.
getName
(
)
+
":"
)
;
}
MCContext
&
Context
=
getObjFileLowering
(
)
.
getContext
(
)
;
const
MCSectionELF
*
ConfigSection
=
Context
.
getELFSection
(
".AMDGPU.config"
,
ELF
::
SHT_PROGBITS
,
0
,
SectionKind
::
getReadOnly
(
)
)
;
OutStreamer
.
SwitchSection
(
ConfigSection
)
;
const
AMDGPUSubtarget
&
STM
=
TM
.
getSubtarget
<
AMDGPUSubtarget
>
(
)
;
if
(
STM
.
getGeneration
(
)
>
AMDGPUSubtarget
::
NORTHERN_ISLANDS
)
{
EmitProgramInfoSI
(
MF
)
;
}
else
{
EmitProgramInfoR600
(
MF
)
;
}
DisasmLines
.
clear
(
)
;
HexLines
.
clear
(
)
;
DisasmLineMaxLen
=
0
;
OutStreamer
.
SwitchSection
(
getObjFileLowering
(
)
.
getTextSection
(
)
)
;
EmitFunctionBody
(
)
;
if
(
STM
.
dumpCode
(
)
)
{
MF
.
dump
(
)
;
if
(
DisasmEnabled
)
{
OutStreamer
.
SwitchSection
(
Context
.
getELFSection
(
".AMDGPU.disasm"
,
ELF
::
SHT_NOTE
,
0
,
SectionKind
::
getReadOnly
(
)
)
)
;
for
(
size_t
i
=
0
;
i
<
DisasmLines
.
size
(
)
;
++
i
)
{
std
::
string
Comment
(
DisasmLineMaxLen
DisasmLines
[
i
]
.
size
(
)
,
' '
)
;
Comment
+=
" ; "
+
HexLines
[
i
]
+
"\n"
;
OutStreamer
.
EmitBytes
(
StringRef
(
DisasmLines
[
i
]
)
)
;
OutStreamer
.
EmitBytes
(
StringRef
(
Comment
)
)
;
}
}
}
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> void PPCPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & IfConverterID ) ; if ( ! DisableQPXLoadSplat ) addPass ( createPPCQPXLoadSplatPass ( ) ) ; } } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> static rtx s390_pool_offset ( struct constant_pool * pool , rtx x ) { rtx label ; label = gen_rtx_LABEL_REF ( GET_MODE ( x ) , pool -> label ) ; x = gen_rtx_UNSPEC ( GET_MODE ( x ) , gen_rtvec ( 2 , x , label ) , UNSPEC_POOL_OFFSET ) ; return gen_rtx_CONST ( GET_MODE ( x ) , x ) ; } </s>

Return an rtx that represents the offset of X from the start of pool POOL .


<s> const char * output_move_multiple ( rtx * operands ) { rtx inops [ 2 ] ; rtx exops [ 4 ] [ 2 ] ; rtx adjops [ 2 ] ; pdp11_action action [ 2 ] ; int i , words ; words = GET_MODE_BITSIZE ( GET_MODE ( operands [ 0 ] ) ) / 16 ; adjops [ 1 ] = gen_rtx_CONST_INT ( HImode , words * 2 ) ; inops [ 0 ] = operands [ 0 ] ; inops [ 1 ] = operands [ 1 ] ; pdp11_expand_operands ( inops , exops , 2 , words , action , either ) ; if ( action [ 0 ] == dec_before ) { adjops [ 0 ] = XEXP ( XEXP ( operands [ 0 ] , 0 ) , 0 ) ; output_asm_insn ( "sub\t%1,%0" , adjops ) ; } if ( action [ 1 ] == dec_before ) { adjops [ 0 ] = XEXP ( XEXP ( operands [ 1 ] , 0 ) , 0 ) ; output_asm_insn ( "sub\t%1,%0" , adjops ) ; } for ( i = 0 ; i < words ; i ++ ) output_asm_insn ( singlemove_string ( exops [ i ] ) , exops [ i ] ) ; if ( action [ 0 ] == inc_after ) { adjops [ 0 ] = XEXP ( XEXP ( operands [ 0 ] , 0 ) , 0 ) ; output_asm_insn ( "add\t%1,%0" , adjops ) ; } if ( action [ 1 ] == inc_after ) { adjops [ 0 ] = XEXP ( XEXP ( operands [ 1 ] , 0 ) , 0 ) ; output_asm_insn ( "add\t%1,%0" , adjops ) ; } return "" ; } </s>

Output assembler code to perform a multiple-word move insn with operands OPERANDS . This moves 2 or 4 words depending on the machine mode of the operands .


<s> const TriCoreRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> SDValue SystemZSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool IsVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { if ( IsVolatile ) return SDValue ( ) ; if ( auto * CSize = dyn_cast < ConstantSDNode > ( Size ) ) return emitMemMemImm ( DAG , DL , SystemZISD :: MVC , Chain , Dst , Src , CSize -> getZExtValue ( ) ) ; return emitMemMemReg ( DAG , DL , SystemZISD :: MVC , Chain , Dst , Src , Size ) ; } </s>

Emit target-specific code that performs a memcpy .

SystemZ SystemZ SystemZISD::MVC SystemZISD::MVC


<s> void SPIRVPassConfig :: addPostRegAlloc ( ) { disablePass ( & MachineCopyPropagationID ) ; disablePass ( & PostRAMachineSinkingID ) ; disablePass ( & PostRASchedulerID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & StackMapLivenessID ) ; disablePass ( & PatchableFunctionID ) ; disablePass ( & ShrinkWrapID ) ; disablePass ( & LiveDebugValuesID ) ; disablePass ( & BranchFolderPassID ) ; disablePass ( & MachineBlockPlacementID ) ; TargetPassConfig :: addPostRegAlloc ( ) ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> static bool mips_tls_symbol_p ( rtx x ) { return GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) != 0 ; } </s>

Return true if X is a thread-local symbol .


<s> int arm_address_offset_is_imm ( rtx_insn * insn ) { rtx mem , addr ; extract_insn_cached ( insn ) ; if ( REG_P ( recog_data . operand [ 0 ] ) ) return 0 ; mem = recog_data . operand [ 0 ] ; gcc_assert ( MEM_P ( mem ) ) ; addr = XEXP ( mem , 0 ) ; if ( REG_P ( addr ) || ( GET_CODE ( addr ) == PLUS && REG_P ( XEXP ( addr , 0 ) ) && CONST_INT_P ( XEXP ( addr , 1 ) ) ) ) return 1 ; else return 0 ; } </s>

Return nonzero if the offset in the address is an immediate . Otherwise , return zero .


<s> int visium_expand_block_move ( rtx * operands ) { rtx dst = operands [ 0 ] ; rtx src = operands [ 1 ] ; rtx bytes_rtx = operands [ 2 ] ; rtx align_rtx = operands [ 3 ] ; const int align = INTVAL ( align_rtx ) ; rtx dst_reg , src_reg ; tree dst_expr , src_expr ; if ( ! CONST_INT_P ( bytes_rtx ) || INTVAL ( bytes_rtx ) <= 0 ) return 0 ; dst_reg = copy_addr_to_reg ( XEXP ( dst , 0 ) ) ; src_reg = copy_addr_to_reg ( XEXP ( src , 0 ) ) ; if ( align >= 4 ) expand_block_move_4 ( dst , dst_reg , src , src_reg , bytes_rtx ) ; else if ( align >= 2 ) expand_block_move_2 ( dst , dst_reg , src , src_reg , bytes_rtx ) ; else expand_block_move_1 ( dst_reg , src_reg , bytes_rtx ) ; dst_expr = MEM_EXPR ( dst ) ; src_expr = MEM_EXPR ( src ) ; if ( dst_expr ) mark_addressable ( dst_expr ) ; if ( src_expr ) mark_addressable ( src_expr ) ; return 1 ; } </s>

Expand string/block move operations . operands [ 0 ] is the pointer to the destination . operands [ 1 ] is the pointer to the source . operands [ 2 ] is the number of bytes to move . operands [ 3 ] is the alignment . Return 1 upon success , 0 otherwise .


<s> void AArch64AsmPrinter :: emitEndOfAsmFile ( Module & M ) { emitHwasanMemaccessSymbols ( M ) ; const Triple & TT = TM . getTargetTriple ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { OutStreamer -> emitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } emitStackMaps ( SM ) ; FM . serializeToFaultMapSection ( ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s>
void
MipsInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineMemOperand
*
MMO
=
GetMemOperand
(
MBB
,
FI
,
MachineMemOperand
::
MOStore
)
;
unsigned
Opc
=
0
;
if
(
Mips
::
CPURegsRegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
IsN64
Mips
::
SW_P8
:
Mips
::
SW
;
else
if
(
Mips
::
CPU64RegsRegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
IsN64
Mips
::
SD_P8
:
Mips
::
SD
;
else
if
(
Mips
::
FGR32RegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
IsN64
Mips
::
SWC1_P8
:
Mips
::
SWC1
;
else
if
(
Mips
::
AFGR64RegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
Mips
::
SDC1
;
else
if
(
Mips
::
FGR64RegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
IsN64
Mips
::
SDC164_P8
:
Mips
::
SDC164
;
assert
(
Opc
&&
"Register class not handled!"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> virtual const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> unsigned AArch64RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const AArch64FrameLowering * TFI = getFrameLowering ( MF ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case AArch64 :: GPR32RegClassID : case AArch64 :: GPR32spRegClassID : case AArch64 :: GPR32allRegClassID : case AArch64 :: GPR64spRegClassID : case AArch64 :: GPR64allRegClassID : case AArch64 :: GPR64RegClassID : case AArch64 :: GPR32commonRegClassID : case AArch64 :: GPR64commonRegClassID : return 32 - 1 - ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) - ( TT . isOSDarwin ( ) || ReserveX18 ) - hasBasePointer ( MF ) ; case AArch64 :: FPR8RegClassID : case AArch64 :: FPR16RegClassID : case AArch64 :: FPR32RegClassID : case AArch64 :: FPR64RegClassID : case AArch64 :: FPR128RegClassID : return 32 ; case AArch64 :: DDRegClassID : case AArch64 :: DDDRegClassID : case AArch64 :: DDDDRegClassID : case AArch64 :: QQRegClassID : case AArch64 :: QQQRegClassID : case AArch64 :: QQQQRegClassID : return 32 ; case AArch64 :: FPR128_loRegClassID : return 16 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> bool PPCInstrInfo :: isAssociativeAndCommutative ( const MachineInstr & Inst ) const { switch ( Inst . getOpcode ( ) ) { case PPC :: FADD : case PPC :: FADDS : case PPC :: FMUL : case PPC :: FMULS : case PPC :: VADDFP : case PPC :: XSADDDP : case PPC :: XVADDDP : case PPC :: XVADDSP : case PPC :: XSADDSP : case PPC :: XSMULDP : case PPC :: XVMULDP : case PPC :: XVMULSP : case PPC :: XSMULSP : case PPC :: QVFADD : case PPC :: QVFADDS : case PPC :: QVFADDSs : case PPC :: QVFMUL : case PPC :: QVFMULS : case PPC :: QVFMULSs : return Inst . getFlag ( MachineInstr :: MIFlag :: FmReassoc ) && Inst . getFlag ( MachineInstr :: MIFlag :: FmNsz ) ; case PPC :: MULHD : case PPC :: MULLD : case PPC :: MULHW : case PPC :: MULLW : return true ; default : return false ; } } </s>

Return true when \P Inst is both associative and commutative .

PowerPC PPC PPC::FADD PPC::FADDS PPC::FMUL PPC::FMULS PPC::VADDFP PPC::XSADDDP PPC::XVADDDP PPC::XVADDSP PPC::XSADDSP PPC::XSMULDP PPC::XVMULDP PPC::XVMULSP PPC::XSMULSP PPC::QVFADD PPC::QVFADDS PPC::QVFADDSs PPC::QVFMUL PPC::QVFMULS PPC::QVFMULSs PPC::MULHD PPC::MULLD PPC::MULHW PPC::MULLW


<s>
unsigned
Mips16InstrInfo
::
getInlineAsmLength
(
const
char
*
Str
,
const
MCAsmInfo
&
MAI
)
const
{
bool
atInsnStart
=
true
;
unsigned
Length
=
0
;
for
(
;
*
Str
;
++
Str
)
{
if
(
*
Str
==
'\n'
||
strncmp
(
Str
,
MAI
.
getSeparatorString
(
)
,
strlen
(
MAI
.
getSeparatorString
(
)
)
)
==
0
)
atInsnStart
=
true
;
if
(
atInsnStart
&&
!
std
::
isspace
(
static_cast
<
unsigned
char
>
(
*
Str
)
)
)
{
if
(
strncmp
(
Str
,
".space"
,
6
)
==
0
)
{
char
*
EStr
;
int
Sz
;
Sz
=
strtol
(
Str
+
6
,
&
EStr
,
10
)
;
while
(
isspace
(
*
EStr
)
)
++
EStr
;
if
(
*
EStr
==
'\0'
)
{
DEBUG
(
dbgs
(
)
<<
"parsed .space "
<<
Sz
<<
'\n'
)
;
return
Sz
;
}
}
Length
+=
MAI
.
getMaxInstLength
(
)
;
atInsnStart
=
false
;
}
if
(
atInsnStart
&&
strncmp
(
Str
,
MAI
.
getCommentString
(
)
.
data
(
)
,
MAI
.
getCommentString
(
)
.
size
(
)
)
==
0
)
atInsnStart
=
false
;
}
return
Length
;
}
</s>

Measure the specified inline asm to determine an approximation of its length .


<s> void SystemZHazardRecognizer :: Reset ( ) { CurrGroupSize = 0 ; clearProcResCounters ( ) ; GrpCount = 0 ; LastFPdOpCycleIdx = UINT_MAX ; LastEmittedMI = nullptr ; DEBUG ( CurGroupDbg = "" ; ) ; } </s>


Copy one MODE sized block from SRC to DST , then progress SRC and DST by MODE bytes .


<s> bool runOnMachineFunction ( MachineFunction & F ) { bool Changed = false ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , JIT , RM ) , getEffectiveX86CodeModel ( CM , JIT , TT . getArch ( ) == Triple :: x86_64 ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) { if ( ( TT . isOSWindows ( ) && TT . getArch ( ) == Triple :: x86_64 ) || TT . isPS4 ( ) || TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = TT . isOSBinFormatMachO ( ) ; } if ( TT . getArch ( ) == Triple :: x86_64 ) setMachineOutliner ( true ) ; initAsmInfo ( ) ; } </s>


<s> static bool rs6000_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { if ( RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p ) { static int recurse = 0 ; if ( DEFAULT_ABI == ABI_V4 && ( TARGET_RELOCATABLE || flag_pic > 1 ) && in_section != toc_section && ! recurse && ! CONST_SCALAR_INT_P ( x ) && CONSTANT_P ( x ) ) { char buf [ 256 ] ; recurse = 1 ; ASM_GENERATE_INTERNAL_LABEL ( buf , "LCP" , fixuplabelno ) ; fixuplabelno ++ ; ASM_OUTPUT_LABEL ( asm_out_file , buf ) ; fprintf ( asm_out_file , "\t.long\t(" ) ; output_addr_const ( asm_out_file , x ) ; fprintf ( asm_out_file , ")@fixup\n" ) ; fprintf ( asm_out_file , "\t.section\t\".fixup\",\"aw\"\n" ) ; ASM_OUTPUT_ALIGN ( asm_out_file , 2 ) ; fprintf ( asm_out_file , "\t.long\t" ) ; assemble_name ( asm_out_file , buf ) ; fprintf ( asm_out_file , "\n\t.previous\n" ) ; recurse = 0 ; return true ; } else if ( GET_CODE ( x ) == SYMBOL_REF && XSTR ( x , 0 ) [ 0 ] == '.' && DEFAULT_ABI == ABI_AIX ) { const char * name = XSTR ( x , 0 ) ; while ( * name == '.' ) name ++ ; fprintf ( asm_out_file , "\t.long\t%s\n" , name ) ; return true ; } } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . The powerpc version has to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP is defined . It also needs to handle DI-mode objects on 64-bit targets .


<s> EVT AArch64TargetLowering :: getSetCCResultType ( EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> static rtx_insn * csky_call_tls_get_addr ( rtx x , rtx reg , rtx * valuep , int reloc ) { rtx label , labelno , unspec , tmp ; rtx_insn * insns ; start_sequence ( ) ; labelno = GEN_INT ( tls_labelno ++ ) ; label = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , labelno ) , UNSPEC_TLS_LABEL ) ; unspec = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 3 , x , GEN_INT ( reloc ) , label ) , UNSPEC_TLS ) ; tmp = gen_reg_rtx ( SImode ) ; emit_move_insn ( reg , unspec ) ; emit_move_insn ( tmp , label ) ; emit_insn ( gen_addsi3 ( reg , reg , tmp ) ) ; * valuep = emit_library_call_value ( get_tls_get_addr ( ) , NULL_RTX , LCT_PURE , Pmode , reg , Pmode ) ; insns = get_insns ( ) ; end_sequence ( ) ; return insns ; } </s>


<s> bool RISCVFrameLowering :: canUseAsEpilogue ( const MachineBasicBlock & MBB ) const { const MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ; const auto * RVFI = MF -> getInfo < RISCVMachineFunctionInfo > ( ) ; if ( ! RVFI -> useSaveRestoreLibCalls ( * MF ) ) return true ; if ( MBB . succ_size ( ) > 1 ) return false ; MachineBasicBlock * SuccMBB = MBB . succ_empty ( ) ? TmpMBB -> getFallThrough ( ) : * MBB . succ_begin ( ) ; if ( ! SuccMBB ) return true ; return SuccMBB -> isReturnBlock ( ) && SuccMBB -> size ( ) == 1 ; } </s>

Check whether or not the given MBB can be used as a epilogue for the target .


<s> static bool s390_pragma_target_parse ( tree args , tree pop_target ) { tree prev_tree = build_target_option_node ( & global_options , & global_options_set ) ; tree cur_tree ; if ( ! args ) cur_tree = pop_target ; else { cur_tree = s390_valid_target_attribute_tree ( args , & global_options , & global_options_set , true ) ; if ( ! cur_tree || cur_tree == error_mark_node ) { cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( prev_tree ) ) ; return false ; } } target_option_current_node = cur_tree ; s390_activate_target_options ( target_option_current_node ) ; { struct cl_target_option * prev_opt ; struct cl_target_option * cur_opt ; prev_opt = TREE_TARGET_OPTION ( prev_tree ) ; cur_opt = TREE_TARGET_OPTION ( cur_tree ) ; cpp_options * cpp_opts = cpp_get_options ( parse_in ) ; unsigned char saved_warn_unused_macros = cpp_opts -> warn_unused_macros ; cpp_opts -> warn_unused_macros = 0 ; cpp_force_token_locations ( parse_in , BUILTINS_LOCATION ) ; s390_cpu_cpp_builtins_internal ( parse_in , cur_opt , prev_opt ) ; cpp_stop_forcing_token_locations ( parse_in ) ; cpp_opts -> warn_unused_macros = saved_warn_unused_macros ; } return true ; } </s>

Hook to validate the current # pragma GCC target and set the state , and update the macros based on what was changed . If ARGS is NULL , then POP_TARGET is used to reset the options .


<s> static tree aarch64_get_attributes ( aarch64_simd_builtin_datum * d ) { tree attrs = NULL_TREE ; if ( ! aarch64_modifies_global_state_p ( d ) ) { if ( aarch64_reads_global_state_p ( d ) ) attrs = aarch64_add_attribute ( "pure" , attrs ) ; else attrs = aarch64_add_attribute ( "const" , attrs ) ; } if ( ! flag_non_call_exceptions || ! aarch64_could_trap_p ( d ) ) attrs = aarch64_add_attribute ( "nothrow" , attrs ) ; return aarch64_add_attribute ( "leaf" , attrs ) ; } </s>

Return the appropriate function attributes .


<s> bool LanaiAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] ) return true ; switch ( ExtraCode [ 0 ] ) { case 'H' : { if ( OpNo == 0 ) return true ; const MachineOperand & FlagsOP = MI -> getOperand ( OpNo - 1 ) ; if ( ! FlagsOP . isImm ( ) ) return true ; unsigned Flags = FlagsOP . getImm ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; if ( NumVals != 2 ) return true ; unsigned RegOp = OpNo + 1 ; if ( RegOp >= MI -> getNumOperands ( ) ) return true ; const MachineOperand & MO = MI -> getOperand ( RegOp ) ; if ( ! MO . isReg ( ) ) return true ; unsigned Reg = MO . getReg ( ) ; O << LanaiInstPrinter :: getRegisterName ( Reg ) ; return false ; } default : return true ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> void GBZ80TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { SDLoc DL ( N ) ; switch ( N -> getOpcode ( ) ) { case ISD :: ADD : { if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) ) { SDValue Sub = DAG . getNode ( ISD :: SUB , DL , N -> getValueType ( 0 ) , N -> getOperand ( 0 ) , DAG . getConstant ( - C -> getAPIntValue ( ) , DL , C -> getValueType ( 0 ) ) ) ; Results . push_back ( Sub ) ; } break ; } default : { SDValue Res = LowerOperation ( SDValue ( N , 0 ) , DAG ) ; for ( unsigned I = 0 , E = Res -> getNumValues ( ) ; I != E ; ++ I ) Results . push_back ( Res . getValue ( I ) ) ; break ; } } } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> static bool csky_class_likely_spilled_p ( reg_class_t rclass ) { if ( ( TARGET_MINI_REGISTERS && rclass == MINI_REGS ) || rclass == C_REGS ) return true ; return false ; } </s>

Implement TARGET_CLASS_LIKELY_SPILLED_P . We need to define this for MINI_REGS when we only use r0 - r7 . Otherwise we can end up using r0-r4 for function arguments , and do n't have enough left over to do doubleword arithmetic .


<s> bool reg_unused_after ( rtx reg , rtx_insn * insn ) { rtx set = single_set ( insn ) ; if ( set && ! MEM_P ( SET_DEST ( set ) ) && reg_overlap_mentioned_p ( reg , SET_DEST ( set ) ) ) return true ; while ( ( insn = NEXT_INSN ( insn ) ) ) { if ( ! INSN_P ( insn ) ) continue ; rtx_code code = GET_CODE ( insn ) ; if ( code == CODE_LABEL ) return 1 ; if ( code == JUMP_INSN ) return false ; else if ( code == INSN && GET_CODE ( PATTERN ( insn ) ) == SEQUENCE ) { rtx_sequence * seq = as_a < rtx_sequence * > ( PATTERN ( insn ) ) ; bool retval = false ; for ( int i = 0 ; i < seq -> len ( ) ; i ++ ) { rtx_insn * this_insn = seq -> insn ( i ) ; rtx set = single_set ( this_insn ) ; if ( CALL_P ( this_insn ) ) code = CALL_INSN ; else if ( JUMP_P ( this_insn ) ) { if ( INSN_ANNULLED_BRANCH_P ( this_insn ) ) return false ; code = JUMP_INSN ; } if ( set && reg_overlap_mentioned_p ( reg , SET_SRC ( set ) ) ) return false ; if ( set && reg_overlap_mentioned_p ( reg , SET_DEST ( set ) ) ) { if ( ! MEM_P ( SET_DEST ( set ) ) ) retval = true ; else return false ; } if ( set == NULL_RTX && reg_overlap_mentioned_p ( reg , PATTERN ( this_insn ) ) ) return false ; } if ( retval ) return true ; else if ( code == JUMP_INSN ) return false ; } rtx set = single_set ( insn ) ; if ( set && reg_overlap_mentioned_p ( reg , SET_SRC ( set ) ) ) return false ; if ( set && reg_overlap_mentioned_p ( reg , SET_DEST ( set ) ) ) return ! MEM_P ( SET_DEST ( set ) ) ; if ( set == NULL && reg_overlap_mentioned_p ( reg , PATTERN ( insn ) ) ) return false ; if ( code == CALL_INSN && call_really_used_regs [ REGNO ( reg ) ] ) return true ; } return true ; } </s>

Return nonzero if REG is not used after INSN . We assume REG is a reload reg , and therefore does not live past labels or calls or jumps .


<s> SDValue NVPTXTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , SDLoc dl , SelectionDAG & DAG ) const { bool isABI = ( nvptxSubtarget . getSmVersion ( ) >= 20 ) ; unsigned sizesofar = 0 ; unsigned idx = 0 ; for ( unsigned i = 0 , e = Outs . size ( ) ; i != e ; ++ i ) { SDValue theVal = OutVals [ i ] ; EVT theValType = theVal . getValueType ( ) ; unsigned numElems = 1 ; if ( theValType . isVector ( ) ) numElems = theValType . getVectorNumElements ( ) ; for ( unsigned j = 0 , je = numElems ; j != je ; ++ j ) { SDValue tmpval = theVal ; if ( theValType . isVector ( ) ) tmpval = DAG . getNode ( ISD :: EXTRACT_VECTOR_ELT , dl , theValType . getVectorElementType ( ) , tmpval , DAG . getIntPtrConstant ( j ) ) ; Chain = DAG . getNode ( isABI ? NVPTXISD :: StoreRetval : NVPTXISD :: MoveToRetval , dl , MVT :: Other , Chain , DAG . getConstant ( isABI ? sizesofar : idx , MVT :: i32 ) , tmpval ) ; if ( theValType . isVector ( ) ) sizesofar += theValType . getVectorElementType ( ) . getStoreSizeInBits ( ) / 8 ; else sizesofar += theValType . getStoreSizeInBits ( ) / 8 ; ++ idx ; } } return DAG . getNode ( NVPTXISD :: RET_FLAG , dl , MVT :: Other , Chain ) ; } </s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static void arm_output_dwarf_dtprel ( FILE * file , int size , rtx x ) { gcc_assert ( size == 4 ) ; fputs ( "\t.word\t" , file ) ; output_addr_const ( file , x ) ; fputs ( "(tlsldo)" , file ) ; } </s>

ARM implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL .


<s> inline static bool isMem ( const MachineInstr * MI , unsigned Op ) { if ( MI -> getOperand ( Op ) . isFI ( ) ) return true ; return Op + X86 :: AddrNumOperands <= MI -> getNumOperands ( ) && MI -> getOperand ( Op + X86 :: AddrSegmentReg ) . isReg ( ) && isLeaMem ( MI , Op ) ; } </s>


<s> static void add_sched_insns_for_speculation ( void ) { rtx_insn * insn ; if ( ! ENABLE_WA_SPECULATIVE_LOADS && ! ENABLE_WA_SPECULATIVE_SYNCS && ! ENABLE_WA_INDIRECT_CALLS ) return ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { rtx pat ; if ( NOTE_P ( insn ) || BARRIER_P ( insn ) || LABEL_P ( insn ) ) continue ; if ( JUMP_TABLE_DATA_P ( insn ) ) continue ; pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == USE || GET_CODE ( pat ) == CLOBBER || GET_CODE ( pat ) == ASM_INPUT || asm_noperands ( pat ) >= 0 ) continue ; if ( JUMP_P ( insn ) ) { if ( any_condjump_p ( insn ) && ! cbranch_predicted_taken_p ( insn ) ) { rtx n = next_real_insn ( insn ) ; emit_insn_before ( gen_stall ( GEN_INT ( 3 ) ) , n ) ; } } } for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( JUMP_P ( insn ) && any_condjump_p ( insn ) && ( cbranch_predicted_taken_p ( insn ) ) ) { rtx target = JUMP_LABEL ( insn ) ; rtx_insn * next = next_real_insn ( target ) ; if ( GET_CODE ( PATTERN ( next ) ) == UNSPEC_VOLATILE && get_attr_type ( next ) == TYPE_STALL ) continue ; emit_insn_before ( gen_stall ( GEN_INT ( 1 ) ) , next ) ; } } } </s>

Called just before the final scheduling pass . If we need to insert NOPs later on to work around speculative loads , insert special placeholder insns that cause loads to be delayed for as many cycles as necessary ( and possible ) . This reduces the number of NOPs we need to add . The dummy insns we generate are later removed by bfin_gen_bundles .


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { bool HasAVX = TM . getSubtarget < X86Subtarget > ( ) . hasAVX ( ) ; bool HasAVX512 = TM . getSubtarget < X86Subtarget > ( ) . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; default : break ; } if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_RegMask ; return CSR_64_RegMask ; } return CSR_32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool X86RegisterInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; return ( NoFramePointerElim || needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool MCS51TargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { EVT VT ; SDLoc DL ( N ) ; if ( const LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; if ( LD -> getExtensionType ( ) != ISD :: NON_EXTLOAD ) return false ; } else if ( const StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; if ( MCS51 :: isProgramMemoryAccess ( ST ) ) { return false ; } } else { return false ; } if ( VT != MVT :: i8 && VT != MVT :: i16 ) { return false ; } if ( Op -> getOpcode ( ) != ISD :: ADD && Op -> getOpcode ( ) != ISD :: SUB ) { return false ; } if ( const ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ) { int RHSC = RHS -> getSExtValue ( ) ; if ( Op -> getOpcode ( ) == ISD :: SUB ) RHSC = - RHSC ; if ( ( VT == MVT :: i16 && RHSC != 2 ) || ( VT == MVT :: i8 && RHSC != 1 ) ) { return false ; } Base = Op -> getOperand ( 0 ) ; Offset = DAG . getConstant ( RHSC , DL , MVT :: i8 ) ; AM = ISD :: POST_INC ; return true ; } return false ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .


<s> bool HexagonAsmParser :: isLabel ( AsmToken & Token ) { MCAsmLexer & Lexer = getLexer ( ) ; AsmToken const & Second = Lexer . getTok ( ) ; AsmToken Third = Lexer . peekTok ( ) ; StringRef String = Token . getString ( ) ; if ( Token . is ( AsmToken :: TokenKind :: LCurly ) || Token . is ( AsmToken :: TokenKind :: RCurly ) ) return false ; if ( String . lower ( ) == "vwhist256" && Second . is ( AsmToken :: Colon ) && Third . getString ( ) . lower ( ) == "sat" ) return false ; if ( ! Token . is ( AsmToken :: TokenKind :: Identifier ) ) return true ; if ( ! matchRegister ( String . lower ( ) ) ) return true ; assert ( Second . is ( AsmToken :: Colon ) ) ; StringRef Raw ( String . data ( ) , Third . getString ( ) . data ( ) - String . data ( ) + Third . getString ( ) . size ( ) ) ; std :: string Collapsed = Raw ; Collapsed . erase ( llvm :: remove_if ( Collapsed , isspace ) , Collapsed . end ( ) ) ; StringRef Whole = Collapsed ; std :: pair < StringRef , StringRef > DotSplit = Whole . split ( '.' ) ; if ( ! matchRegister ( DotSplit . first . lower ( ) ) ) return true ; return false ; } </s>

Returns true if the MachineInstr represents a label .


<s> static rtx mips_legitimize_tls_address ( rtx loc ) { rtx dest , v0 , tp , tmp1 , tmp2 , eqv , offset ; enum tls_model model ; model = SYMBOL_REF_TLS_MODEL ( loc ) ; if ( ! TARGET_ABICALLS ) model = TLS_MODEL_LOCAL_EXEC ; switch ( model ) { case TLS_MODEL_GLOBAL_DYNAMIC : { v0 = gen_rtx_REG ( Pmode , GP_RETURN ) ; rtx_insn * insn = mips_call_tls_get_addr ( loc , SYMBOL_TLSGD , v0 ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insn , dest , v0 , loc ) ; break ; } case TLS_MODEL_LOCAL_DYNAMIC : { v0 = gen_rtx_REG ( Pmode , GP_RETURN ) ; rtx_insn * insn = mips_call_tls_get_addr ( loc , SYMBOL_TLSLDM , v0 ) ; tmp1 = gen_reg_rtx ( Pmode ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , const0_rtx ) , UNSPEC_TLS_LDM ) ; emit_libcall_block ( insn , tmp1 , v0 , eqv ) ; offset = mips_unspec_address ( loc , SYMBOL_DTPREL ) ; if ( mips_split_p [ SYMBOL_DTPREL ] ) { tmp2 = mips_unspec_offset_high ( NULL , tmp1 , loc , SYMBOL_DTPREL ) ; dest = gen_rtx_LO_SUM ( Pmode , tmp2 , offset ) ; } else dest = expand_binop ( Pmode , add_optab , tmp1 , offset , 0 , 0 , OPTAB_DIRECT ) ; break ; } case TLS_MODEL_INITIAL_EXEC : tp = mips_get_tp ( ) ; tmp1 = gen_reg_rtx ( Pmode ) ; tmp2 = mips_unspec_address ( loc , SYMBOL_GOTTPREL ) ; if ( Pmode == DImode ) emit_insn ( gen_load_gotdi ( tmp1 , pic_offset_table_rtx , tmp2 ) ) ; else emit_insn ( gen_load_gotsi ( tmp1 , pic_offset_table_rtx , tmp2 ) ) ; dest = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_add3_insn ( dest , tmp1 , tp ) ) ; break ; case TLS_MODEL_LOCAL_EXEC : tmp1 = mips_get_tp ( ) ; offset = mips_unspec_address ( loc , SYMBOL_TPREL ) ; if ( mips_split_p [ SYMBOL_TPREL ] ) { tmp2 = mips_unspec_offset_high ( NULL , tmp1 , loc , SYMBOL_TPREL ) ; dest = gen_rtx_LO_SUM ( Pmode , tmp2 , offset ) ; } else dest = expand_binop ( Pmode , add_optab , tmp1 , offset , 0 , 0 , OPTAB_DIRECT ) ; break ; default : gcc_unreachable ( ) ; } return dest ; } </s>

Generate the code to access LOC , a thread local SYMBOL_REF . The return value will be a valid address and move_operand ( either a REG or a LO_SUM ) .


<s> bool PPCTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( Ty -> isVectorTy ( ) && AM . BaseOffs != 0 ) return false ; if ( AM . BaseOffs <= - ( 1LL << 16 ) || AM . BaseOffs >= ( 1LL << 16 ) - 1 ) return false ; if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( AM . HasBaseReg && AM . BaseOffs ) return false ; break ; case 2 : if ( AM . HasBaseReg || AM . BaseOffs ) return false ; break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> bool X86TTIImpl :: isLegalMaskedExpandLoad ( Type * DataTy ) { if ( ! isa < VectorType > ( DataTy ) ) return false ; if ( ! ST -> hasAVX512 ( ) ) return false ; if ( cast < FixedVectorType > ( DataTy ) -> getNumElements ( ) == 1 ) return false ; Type * ScalarTy = cast < VectorType > ( DataTy ) -> getElementType ( ) ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == 32 || IntWidth == 64 || ( ( IntWidth == 8 || IntWidth == 16 ) && ST -> hasVBMI2 ( ) ) ; } </s>

Return true if the target supports masked expand load .


<s>
static
void
split_words
(
const
std
::
string
&
val
,
std
::
set
<
std
::
string
>
&
result
)
{
size_t
cur
,
prev
=
0
;
std
::
string
word
;
while
(
(
cur
=
val
.
find_first_of
(
" \n"
,
prev
)
)
!=
std
::
string
::
npos
)
{
word
=
val
.
substr
(
prev
,
cur
prev
)
;
if
(
!
word
.
empty
(
)
)
result
.
insert
(
word
)
;
prev
=
cur
+
1
;
}
if
(
prev
!=
cur
)
result
.
insert
(
val
.
substr
(
prev
)
)
;
}
</s>

Splits and returns a string based on whitespace and return it as part of a set . Empty strings are ignored .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
KindTy
::
Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
KindTy
::
Register
:
OS
<<
"<register x"
;
OS
<<
getReg
(
)
<<
">"
;
break
;
case
KindTy
::
Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
case
KindTy
::
SystemRegister
:
OS
<<
"<sysreg: "
<<
getSysReg
(
)
<<
'>'
;
break
;
case
KindTy
::
VType
:
SmallString
<
32
>
VTypeBuf
;
OS
<<
"<vtype: "
<<
getVType
(
VTypeBuf
)
<<
'>'
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

RISCV
"<register x"
">"
"'"
"'"
"<sysreg: "
32
"<vtype: "


<s> const ARMSubtarget * ARMBaseTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < ARMSubtarget > ( TargetTriple , CPU , FS , * this , isLittle ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; ARMGISelActualAccessor * GISel = new ARMGISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new ARMCallLowering ( * I -> getTargetLowering ( ) ) ) ; GISel -> Legalizer . reset ( new ARMLegalizerInfo ( ) ) ; auto * RBI = new ARMRegisterBankInfo ( * I -> getRegisterInfo ( ) ) ; GISel -> InstSelector . reset ( new ARMInstructionSelector ( * I , * RBI ) ) ; GISel -> RegBankInfo . reset ( RBI ) ; I -> setGISelAccessor ( * GISel ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

ARM ARM ARM "target-cpu" "target-features" "use-soft-float" "true" "+soft-float" ",+soft-float" ARM ARM ARM ARM ARM ARM ARM


<s> bool AMDGPUTTIImpl :: isAlwaysUniform ( const Value * V ) const { if ( const IntrinsicInst * Intrinsic = dyn_cast < IntrinsicInst > ( V ) ) { switch ( Intrinsic -> getIntrinsicID ( ) ) { default : return false ; case Intrinsic :: amdgcn_readfirstlane : case Intrinsic :: amdgcn_readlane : return true ; } } return false ; } </s>

Whether Val will always return a uniform value regardless of its operands .


<s> int sh_register_move_cost ( enum machine_mode mode , enum reg_class srcclass , enum reg_class dstclass ) { if ( dstclass == T_REGS || dstclass == PR_REGS ) return 10 ; if ( dstclass == MAC_REGS && srcclass == MAC_REGS ) return 4 ; if ( mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD && REGCLASS_HAS_FP_REG ( srcclass ) && REGCLASS_HAS_FP_REG ( dstclass ) ) return 4 ; if ( REGCLASS_HAS_FP_REG ( dstclass ) && srcclass == T_REGS ) return ( ( TARGET_HARD_SH4 && ! optimize_size ) ? 10 : 7 ) ; if ( ( REGCLASS_HAS_FP_REG ( dstclass ) && srcclass == MAC_REGS ) || ( dstclass == MAC_REGS && REGCLASS_HAS_FP_REG ( srcclass ) ) ) return 9 ; if ( ( REGCLASS_HAS_FP_REG ( dstclass ) && REGCLASS_HAS_GENERAL_REG ( srcclass ) ) || ( REGCLASS_HAS_GENERAL_REG ( dstclass ) && REGCLASS_HAS_FP_REG ( srcclass ) ) ) return ( ( TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12 ) * ( ( GET_MODE_SIZE ( mode ) + 7 ) / 8U ) ) ; if ( ( dstclass == FPUL_REGS && REGCLASS_HAS_GENERAL_REG ( srcclass ) ) || ( srcclass == FPUL_REGS && REGCLASS_HAS_GENERAL_REG ( dstclass ) ) ) return 5 ; if ( ( dstclass == FPUL_REGS && ( srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS ) ) || ( srcclass == FPUL_REGS && ( dstclass == PR_REGS || dstclass == MAC_REGS ) ) ) return 7 ; if ( ( srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG ( dstclass ) ) || ( ( dstclass ) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG ( srcclass ) ) ) return 20 ; if ( TARGET_SHMEDIA && ( ( srcclass ) == TARGET_REGS || ( srcclass ) == SIBCALL_REGS ) ) { if ( sh_gettrcost >= 0 ) return sh_gettrcost ; else if ( ! TARGET_PT_FIXED ) return 100 ; } if ( ( srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG ( dstclass ) ) || ( dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG ( srcclass ) ) ) return 4 ; if ( TARGET_SHMEDIA || ( TARGET_FMOVD && ! REGCLASS_HAS_GENERAL_REG ( srcclass ) && ! REGCLASS_HAS_GENERAL_REG ( dstclass ) ) ) return 2 * ( ( GET_MODE_SIZE ( mode ) + 7 ) / 8U ) ; return 2 * ( ( GET_MODE_SIZE ( mode ) + 3 ) / 4U ) ; } </s>

If SECONDARY * _RELOAD_CLASS says something about the src/dst pair , regclass uses this information . Hence , the general register < - > floating point register information here is not used for SFmode .


<s>
bool
HexagonExpandCondsets
::
split
(
MachineInstr
&
MI
,
std
::
set
<
Register
>
&
UpdRegs
)
{
if
(
TfrLimitActive
)
{
if
(
TfrCounter
>=
TfrLimit
)
return
false
;
TfrCounter
++
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"\nsplitting "
<<
printMBBReference
(
*
MI
.
getParent
(
)
)
<<
": "
<<
MI
)
;
MachineOperand
&
MD
=
MI
.
getOperand
(
0
)
;
MachineOperand
&
MP
=
MI
.
getOperand
(
1
)
;
assert
(
MD
.
isDef
(
)
)
;
Register
DR
=
MD
.
getReg
(
)
,
DSR
=
MD
.
getSubReg
(
)
;
bool
ReadUndef
=
MD
.
isUndef
(
)
;
MachineBasicBlock
::
iterator
At
=
MI
;
auto
updateRegs
=
[
&
UpdRegs
]
(
const
MachineInstr
&
MI
)
->
void
{
for
(
auto
&
Op
:
MI
.
operands
(
)
)
if
(
Op
.
isReg
(
)
)
UpdRegs
.
insert
(
Op
.
getReg
(
)
)
;
}
;
MachineOperand
&
ST
=
MI
.
getOperand
(
2
)
;
MachineOperand
&
SF
=
MI
.
getOperand
(
3
)
;
if
(
ST
.
isReg
(
)
&&
SF
.
isReg
(
)
)
{
RegisterRef
RT
(
ST
)
;
if
(
RT
==
RegisterRef
(
SF
)
)
{
updateRegs
(
MI
)
;
MI
.
setDesc
(
HII
->
get
(
TargetOpcode
::
COPY
)
)
;
unsigned
S
=
getRegState
(
ST
)
;
while
(
MI
.
getNumOperands
(
)
>
1
)
MI
.
removeOperand
(
MI
.
getNumOperands
(
)
1
)
;
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
MachineInstrBuilder
(
MF
,
MI
)
.
addReg
(
RT
.
Reg
,
S
,
RT
.
Sub
)
;
return
true
;
}
}
MachineInstr
*
TfrT
=
genCondTfrFor
(
ST
,
At
,
DR
,
DSR
,
MP
,
true
,
ReadUndef
,
false
)
;
MachineInstr
*
TfrF
=
genCondTfrFor
(
SF
,
At
,
DR
,
DSR
,
MP
,
false
,
ReadUndef
,
true
)
;
LIS
->
InsertMachineInstrInMaps
(
*
TfrT
)
;
LIS
->
InsertMachineInstrInMaps
(
*
TfrF
)
;
updateRegs
(
MI
)
;
removeInstr
(
MI
)
;
return
true
;
}
</s>

Split into substrings around the occurrences of a separator character .


Implement ` MODE_CODE_BASE_REG_CLASS ' .


<s> SDValue X86TargetLowering :: getNegatedExpression ( SDValue Op , SelectionDAG & DAG , bool LegalOperations , bool ForCodeSize , NegatibleCost & Cost , unsigned Depth ) const { if ( SDValue Arg = isFNEG ( DAG , Op . getNode ( ) , Depth ) ) { Cost = NegatibleCost :: Cheaper ; return DAG . getBitcast ( Op . getValueType ( ) , Arg ) ; } EVT VT = Op . getValueType ( ) ; EVT SVT = VT . getScalarType ( ) ; unsigned Opc = Op . getOpcode ( ) ; SDNodeFlags Flags = Op . getNode ( ) -> getFlags ( ) ; switch ( Opc ) { case ISD :: FMA : case X86ISD :: FMSUB : case X86ISD :: FNMADD : case X86ISD :: FNMSUB : case X86ISD :: FMADD_RND : case X86ISD :: FMSUB_RND : case X86ISD :: FNMADD_RND : case X86ISD :: FNMSUB_RND : { if ( ! Op . hasOneUse ( ) || ! Subtarget . hasAnyFMA ( ) || ! isTypeLegal ( VT ) || ! ( SVT == MVT :: f32 || SVT == MVT :: f64 ) || ! isOperationLegal ( ISD :: FMA , VT ) ) break ; if ( ! Flags . hasNoSignedZeros ( ) ) break ; SmallVector < SDValue , 4 > NewOps ( Op . getNumOperands ( ) , SDValue ( ) ) ; for ( int i = 0 ; i != 3 ; ++ i ) NewOps [ i ] = getCheaperNegatedExpression ( Op . getOperand ( i ) , DAG , LegalOperations , ForCodeSize , Depth + 1 ) ; bool NegA = ! ! NewOps [ 0 ] ; bool NegB = ! ! NewOps [ 1 ] ; bool NegC = ! ! NewOps [ 2 ] ; unsigned NewOpc = negateFMAOpcode ( Opc , NegA != NegB , NegC , true ) ; Cost = ( NegA || NegB || NegC ) ? NegatibleCost :: Cheaper : NegatibleCost :: Neutral ; for ( int i = 0 , e = Op . getNumOperands ( ) ; i != e ; ++ i ) if ( ! NewOps [ i ] ) NewOps [ i ] = Op . getOperand ( i ) ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , VT , NewOps ) ; } case X86ISD :: FRCP : if ( SDValue NegOp0 = getNegatedExpression ( Op . getOperand ( 0 ) , DAG , LegalOperations , ForCodeSize , Cost , Depth + 1 ) ) return DAG . getNode ( Opc , SDLoc ( Op ) , VT , NegOp0 ) ; break ; } return TargetLowering :: getNegatedExpression ( Op , DAG , LegalOperations , ForCodeSize , Cost , Depth ) ; } </s>

Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate that if it is cheaper or neutral to do the negation .


"Pseudo opcode found in EmitInstruction()"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static void build_32_64 ( function_builder & b , const char * signature , const function_group_info & group , mode_suffix_index mode32 , mode_suffix_index mode64 , bool force_direct_overloads = false ) { for ( unsigned int pi = 0 ; group . preds [ pi ] != NUM_PREDS ; ++ pi ) if ( group . types [ 0 ] [ 0 ] == NUM_TYPE_SUFFIXES ) { gcc_assert ( mode32 != MODE_none && mode64 != MODE_none ) ; build_one ( b , signature , group , mode32 , 0 , pi , force_direct_overloads ) ; build_one ( b , signature , group , mode64 , 0 , pi , force_direct_overloads ) ; } else for ( unsigned int ti = 0 ; group . types [ ti ] [ 0 ] != NUM_TYPE_SUFFIXES ; ++ ti ) { unsigned int bits = type_suffixes [ group . types [ ti ] [ 0 ] ] . element_bits ; gcc_assert ( bits == 32 || bits == 64 ) ; mode_suffix_index mode = bits == 32 ? mode32 : mode64 ; if ( mode != MODE_none ) build_one ( b , signature , group , mode , ti , pi , force_direct_overloads ) ; } } </s>

GROUP describes some sort of gather or scatter operation . There are two cases : - If the function has any type suffixes ( as for loads and stores ) , the first function type suffix specifies either a 32-bit or a 64-bit type , which in turn selects either MODE32 or MODE64 as the addressing mode . Add a function instance for every type and predicate combination in GROUP for which the associated addressing mode is not MODE_none . - If the function has no type suffixes ( as for prefetches ) , add one MODE32 form and one MODE64 form for each predication type . The other arguments are as for build_all .


"getRegForInlineAsmConstraint Unhandled data type"

Given a physical register constraint ( e.g .


<s> void initializePass ( ) override { pushTTIStack ( this ) ; } </s>

initializePass - This method may be overriden by immutable passes to allow them to perform various initialization actions they require .


" Instructions Emitted in this clause\n"

ScheduleDAGMI has scheduled an instruction - tell HazardRec about it .


<s>
const
RegisterBank
&
X86RegisterBankInfo
::
getRegBankFromRegClass
(
const
TargetRegisterClass
&
RC
,
LLT
)
const
{
if
(
X86
::
GR8RegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
GR16RegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
GR32RegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
GR64RegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
LOW32_ADDR_ACCESSRegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
LOW32_ADDR_ACCESS_RBPRegClass
.
hasSubClassEq
(
&
RC
)
)
return
getRegBank
(
X86
::
GPRRegBankID
)
;
if
(
X86
::
FR32XRegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
FR64XRegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
VR128XRegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
VR256XRegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
VR512RegClass
.
hasSubClassEq
(
&
RC
)
)
return
getRegBank
(
X86
::
VECRRegBankID
)
;
llvm_unreachable
(
"Unsupported register kind yet."
)
;
}
</s>


<s> const RegisterBankInfo * getRegBankInfo ( ) const override { return nullptr ; } </s>

If the information for the register banks is available , return it .


<s> bool SystemZTargetLowering :: isFMAFasterThanFMulAndFAdd ( const MachineFunction & MF , EVT VT ) const { VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f32 : case MVT :: f64 : return true ; case MVT :: f128 : return Subtarget . hasVectorEnhancements1 ( ) ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const override { ScheduleDAGMILive * DAG = createGenericSchedLive ( C ) ; DAG -> addMutation ( createLoadClusterDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; DAG -> addMutation ( createStoreClusterDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; DAG -> addMutation ( createMacroFusionDAGMutation ( DAG -> TII ) ) ; return DAG ; } </s>

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level .


"Attempting to lower call as tail call\n"

"... Cannot handle tail calls with swifterror yet.\n"

"... Cannot handle non-void return types yet.\n"

"... Calling convention cannot be tail called.\n"

"... Tail calling varargs not supported yet.\n"

"... Cannot tail call from callers with byval or "

"... Cannot tail call externally-defined function "

"Unexpected variadic calling convention"

"... Cannot tail call with mismatched calling conventions yet.\n"

"... Cannot tail call callees with outgoing arguments yet.\n"

"... Call is eligible for tail call optimization.\n"

Returns true if the call can be lowered as a tail call .


<s>
bool
ARMTargetLowering
::
ExpandInlineAsm
(
CallInst
*
CI
)
const
{
if
(
!
Subtarget
->
hasV6Ops
(
)
)
return
false
;
InlineAsm
*
IA
=
cast
<
InlineAsm
>
(
CI
->
getCalledValue
(
)
)
;
std
::
string
AsmStr
=
IA
->
getAsmString
(
)
;
SmallVector
<
StringRef
,
4
>
AsmPieces
;
SplitString
(
AsmStr
,
AsmPieces
,
";\n"
)
;
switch
(
AsmPieces
.
size
(
)
)
{
default
:
return
false
;
case
1
:
AsmStr
=
AsmPieces
[
0
]
;
AsmPieces
.
clear
(
)
;
SplitString
(
AsmStr
,
AsmPieces
,
" \t,"
)
;
if
(
AsmPieces
.
size
(
)
==
3
&&
AsmPieces
[
0
]
==
"rev"
&&
AsmPieces
[
1
]
==
"$0"
&&
AsmPieces
[
2
]
==
"$1"
&&
IA
->
getConstraintString
(
)
.
compare
(
0
,
4
,
"=l,l"
)
==
0
)
{
IntegerType
*
Ty
=
dyn_cast
<
IntegerType
>
(
CI
->
getType
(
)
)
;
if
(
Ty
&&
Ty
->
getBitWidth
(
)
==
32
)
return
IntrinsicLowering
::
LowerToByteSwap
(
CI
)
;
}
break
;
}
return
false
;
}
</s>

This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to .


<s> bool ARMCodeGenPrepare :: doInitialization ( Module & M ) { Promoter = new IRPromoter ( & M ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> static rtx c6x_expand_builtin ( tree exp , rtx target ATTRIBUTE_UNUSED , rtx subtarget ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , int ignore ATTRIBUTE_UNUSED ) { size_t i ; const struct builtin_description * d ; tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , 0 ) ; unsigned int fcode = DECL_MD_FUNCTION_CODE ( fndecl ) ; for ( i = 0 , d = bdesc_2arg ; i < ARRAY_SIZE ( bdesc_2arg ) ; i ++ , d ++ ) if ( d -> code == fcode ) return c6x_expand_binop_builtin ( d -> icode , exp , target , fcode == C6X_BUILTIN_CLRR ) ; for ( i = 0 , d = bdesc_1arg ; i < ARRAY_SIZE ( bdesc_1arg ) ; i ++ , d ++ ) if ( d -> code == fcode ) return c6x_expand_unop_builtin ( d -> icode , exp , target ) ; gcc_unreachable ( ) ; } </s>

Expand an expression EXP that calls a built-in function , with result going to TARGET if that 's convenient ( and in mode MODE if that 's convenient ) . SUBTARGET may be used as the target for computing one of EXP 's operands . IGNORE is nonzero if the value is to be ignored .


"register number must be a compile-time constant. Try giving higher optimization levels"

Returns true if the operands [ opno ] is a valid compile-time constant to be used as register number in the code for builtins . Else it flags an error and returns false .


<s> unsigned CSKYInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { default : return MI . getDesc ( ) . getSize ( ) ; case CSKY :: CONSTPOOL_ENTRY : return MI . getOperand ( 2 ) . getImm ( ) ; case CSKY :: SPILL_CARRY : case CSKY :: RESTORE_CARRY : case CSKY :: PseudoTLSLA32 : return 8 ; case TargetOpcode :: INLINEASM_BR : case TargetOpcode :: INLINEASM : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> bool AMDGPUPassConfig :: addPreRegAlloc ( ) { addPass ( createAMDGPUConvertToISAPass ( * TM ) ) ; const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) { addPass ( createR600VectorRegMerger ( * TM ) ) ; } return false ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> MachineInstr * SIInstrInfo :: convertToThreeAddress ( MachineFunction :: iterator & MBB , MachineBasicBlock :: iterator & MI , LiveVariables * LV ) const { switch ( MI -> getOpcode ( ) ) { default : return nullptr ; case AMDGPU :: V_MAC_F32_e64 : break ; case AMDGPU :: V_MAC_F32_e32 : { const MachineOperand * Src0 = getNamedOperand ( * MI , AMDGPU :: OpName :: src0 ) ; if ( Src0 -> isImm ( ) && ! isInlineConstant ( * Src0 , 4 ) ) return nullptr ; break ; } } const MachineOperand * Dst = getNamedOperand ( * MI , AMDGPU :: OpName :: dst ) ; const MachineOperand * Src0 = getNamedOperand ( * MI , AMDGPU :: OpName :: src0 ) ; const MachineOperand * Src1 = getNamedOperand ( * MI , AMDGPU :: OpName :: src1 ) ; const MachineOperand * Src2 = getNamedOperand ( * MI , AMDGPU :: OpName :: src2 ) ; return BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( AMDGPU :: V_MAD_F32 ) ) . addOperand ( * Dst ) . addImm ( 0 ) . addOperand ( * Src0 ) . addImm ( 0 ) . addOperand ( * Src1 ) . addImm ( 0 ) . addOperand ( * Src2 ) . addImm ( 0 ) . addImm ( 0 ) ; } </s>

convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag .


<s>
int
ix86_attr_length_immediate_default
(
rtx_insn
*
insn
,
bool
shortform
)
{
int
len
=
0
;
int
i
;
extract_insn_cached
(
insn
)
;
for
(
i
=
recog_data
.
n_operands
1
;
i
>=
0
;
i
)
if
(
CONSTANT_P
(
recog_data
.
operand
[
i
]
)
)
{
enum
attr_mode
mode
=
get_attr_mode
(
insn
)
;
gcc_assert
(
!
len
)
;
if
(
shortform
&&
CONST_INT_P
(
recog_data
.
operand
[
i
]
)
)
{
HOST_WIDE_INT
ival
=
INTVAL
(
recog_data
.
operand
[
i
]
)
;
switch
(
mode
)
{
case
MODE_QI
:
len
=
1
;
continue
;
case
MODE_HI
:
ival
=
trunc_int_for_mode
(
ival
,
HImode
)
;
break
;
case
MODE_SI
:
ival
=
trunc_int_for_mode
(
ival
,
SImode
)
;
break
;
default
:
break
;
}
if
(
IN_RANGE
(
ival
,
128
,
127
)
)
{
len
=
1
;
continue
;
}
}
switch
(
mode
)
{
case
MODE_QI
:
len
=
1
;
break
;
case
MODE_HI
:
len
=
2
;
break
;
case
MODE_SI
:
len
=
4
;
break
;
case
MODE_DI
:
len
=
4
;
break
;
default
:
fatal_insn
(
"unknown insn mode"
,
insn
)
;
}
}
return
len
;
}
</s>

Compute default value for `` length_immediate '' attribute . When SHORTFORM is set expect that insn have 8bit immediate alternative .


<s> static rtx expand_set_or_cpymem_constant_prologue ( rtx dst , rtx * srcp , rtx destreg , rtx srcreg , rtx value , rtx vec_value , int desired_align , int align_bytes , bool issetmem ) { rtx src = NULL ; rtx orig_dst = dst ; rtx orig_src = NULL ; int piece_size = 1 ; int copied_bytes = 0 ; if ( ! issetmem ) { gcc_assert ( srcp != NULL ) ; src = * srcp ; orig_src = src ; } for ( piece_size = 1 ; piece_size <= desired_align && copied_bytes < align_bytes ; piece_size <<= 1 ) { if ( align_bytes & piece_size ) { if ( issetmem ) { if ( vec_value && piece_size > GET_MODE_SIZE ( GET_MODE ( value ) ) ) dst = emit_memset ( dst , destreg , vec_value , piece_size ) ; else dst = emit_memset ( dst , destreg , value , piece_size ) ; } else dst = emit_memmov ( dst , & src , destreg , srcreg , piece_size ) ; copied_bytes += piece_size ; } } if ( MEM_ALIGN ( dst ) < ( unsigned int ) desired_align * BITS_PER_UNIT ) set_mem_align ( dst , desired_align * BITS_PER_UNIT ) ; if ( MEM_SIZE_KNOWN_P ( orig_dst ) ) set_mem_size ( dst , MEM_SIZE ( orig_dst ) - align_bytes ) ; if ( ! issetmem ) { int src_align_bytes = get_mem_align_offset ( src , desired_align * BITS_PER_UNIT ) ; if ( src_align_bytes >= 0 ) src_align_bytes = desired_align - src_align_bytes ; if ( src_align_bytes >= 0 ) { unsigned int src_align ; for ( src_align = desired_align ; src_align >= 2 ; src_align >>= 1 ) { if ( ( src_align_bytes & ( src_align - 1 ) ) == ( align_bytes & ( src_align - 1 ) ) ) break ; } if ( src_align > ( unsigned int ) desired_align ) src_align = desired_align ; if ( MEM_ALIGN ( src ) < src_align * BITS_PER_UNIT ) set_mem_align ( src , src_align * BITS_PER_UNIT ) ; } if ( MEM_SIZE_KNOWN_P ( orig_src ) ) set_mem_size ( src , MEM_SIZE ( orig_src ) - align_bytes ) ; * srcp = src ; } return dst ; } </s>

This function is like the previous one , except here we know how many bytes need to be copied . That allows us to update alignment not only of DST , which is returned , but also of SRC , which is passed as a pointer for that reason .


<s> static bool nvptx_goacc_validate_dims ( tree decl , int dims [ ] , int fn_level , unsigned used ) { int old_dims [ GOMP_DIM_MAX ] ; unsigned int i ; for ( i = 0 ; i < GOMP_DIM_MAX ; ++ i ) old_dims [ i ] = dims [ i ] ; nvptx_goacc_validate_dims_1 ( decl , dims , fn_level , used ) ; gcc_assert ( dims [ GOMP_DIM_VECTOR ] != 0 ) ; if ( dims [ GOMP_DIM_WORKER ] > 0 && dims [ GOMP_DIM_VECTOR ] > 0 ) gcc_assert ( dims [ GOMP_DIM_WORKER ] * dims [ GOMP_DIM_VECTOR ] <= PTX_CTA_SIZE ) ; for ( i = 0 ; i < GOMP_DIM_MAX ; ++ i ) if ( old_dims [ i ] != dims [ i ] ) return true ; return false ; } </s>

Validate compute dimensions of an OpenACC offload or routine , fill in non-unity defaults . FN_LEVEL indicates the level at which a routine might spawn a loop . It is negative for non-routines . If DECL is null , we are validating the default dimensions .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> SDValue XCoreSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { unsigned SizeBitWidth = Size . getValueType ( ) . getSizeInBits ( ) ; if ( ! AlwaysInline && ( Align & 3 ) == 0 && DAG . MaskedValueIsZero ( Size , APInt ( SizeBitWidth , 3 ) ) ) { const TargetLowering & TLI = * DAG . getSubtarget ( ) . getTargetLowering ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = TLI . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; Entry . Node = Src ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMCPY ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( "__memcpy_4" , TLI . getPointerTy ( ) ) , std :: move ( Args ) , 0 ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .


<s> bool has ( unsigned R ) const { unsigned Idx = v2x ( R ) ; if ( Idx >= size ( ) ) return false ; return BitVector :: test ( Idx ) ; } </s>

Tests whether a library function is available .


<s> bool rs6000_return_in_msb ( const_tree valtype ) { return ( DEFAULT_ABI == ABI_ELFv2 && BYTES_BIG_ENDIAN && AGGREGATE_TYPE_P ( valtype ) && ( rs6000_function_arg_padding ( TYPE_MODE ( valtype ) , valtype ) == PAD_UPWARD ) ) ; } </s>

Specify whether values returned in registers should be at the most significant end of a register . We want aggregates returned by value to match the way aggregates are passed to functions .


<s> static rtx mips_unspec_offset_high ( rtx temp , rtx base , rtx addr , enum mips_symbol_type symbol_type ) { if ( mips_split_p [ symbol_type ] ) { addr = gen_rtx_HIGH ( Pmode , mips_unspec_address ( addr , symbol_type ) ) ; addr = mips_force_temporary ( temp , addr ) ; base = mips_force_temporary ( temp , gen_rtx_PLUS ( Pmode , addr , base ) ) ; } return base ; } </s>

If mips_unspec_address ( ADDR , SYMBOL_TYPE ) is a 32-bit value , add the high part to BASE and return the result . Just return BASE otherwise . TEMP is available as a temporary register if needed . The returned expression can be used as the first operand to a LO_SUM .


<s> void X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { bool reserveCallFrame = hasReservedCallFrame ( MF ) ; unsigned Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t InternalAmt = ( isDestroy || Amount ) ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { unsigned StackAlign = getStackAlignment ( ) ; Amount = alignTo ( Amount , StackAlign ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const Function * Fn = MF . getFunction ( ) ; bool WindowsCFI = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool DwarfCFI = ! WindowsCFI && ( MMI . hasDebugInfo ( ) || Fn -> needsUnwindTableEntry ( ) ) ; bool HasDwarfEHHandlers = ! WindowsCFI && ! MF . getMMI ( ) . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < X86MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , I , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == 0 ) return ; Amount -= InternalAmt ; if ( isDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) ) BuildCFI ( MBB , I , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ; if ( Amount ) { int Offset = isDestroy ? Amount : - Amount ; if ( ! ( Fn -> optForMinSize ( ) && adjustStackWithPops ( MBB , I , DL , Offset ) ) ) BuildStackAdjustment ( MBB , I , DL , Offset , false ) ; } if ( DwarfCFI && ! hasFP ( MF ) ) { int CFAOffset = Amount ; if ( CFAOffset ) { CFAOffset = isDestroy ? - CFAOffset : CFAOffset ; BuildCFI ( MBB , I , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , CFAOffset ) ) ; } } return ; } if ( isDestroy && InternalAmt ) { MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! std :: prev ( I ) -> isCall ( ) ) -- I ; BuildStackAdjustment ( MBB , I , DL , - InternalAmt , false ) ; } } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static void microblaze_block_move_straight ( rtx dest , rtx src , HOST_WIDE_INT length ) { HOST_WIDE_INT offset , delta ; unsigned HOST_WIDE_INT bits ; int i ; machine_mode mode ; rtx * regs ; bits = BITS_PER_WORD ; mode = int_mode_for_size ( bits , 0 ) . require ( ) ; delta = bits / BITS_PER_UNIT ; regs = XALLOCAVEC ( rtx , length / delta ) ; for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) { regs [ i ] = gen_reg_rtx ( mode ) ; emit_move_insn ( regs [ i ] , adjust_address ( src , mode , offset ) ) ; } for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) emit_move_insn ( adjust_address ( dest , mode , offset ) , regs [ i ] ) ; if ( offset < length ) { src = adjust_address ( src , BLKmode , offset ) ; dest = adjust_address ( dest , BLKmode , offset ) ; move_by_pieces ( dest , src , length - offset , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) , 0 ) ; } } </s>

Emit straight-line code to move LENGTH bytes from SRC to DEST . Assume that the areas do not overlap .


<s> static int mn10300_arg_partial_bytes ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int size ; int nregs = 2 ; size = arg . promoted_size_in_bytes ( ) ; cum -> nbytes = ( cum -> nbytes + 3 ) & ~ 3 ; if ( cum -> nbytes > nregs * UNITS_PER_WORD ) return 0 ; if ( cum -> nbytes + size <= nregs * UNITS_PER_WORD ) return 0 ; if ( arg . type == NULL_TREE && cum -> nbytes + size > nregs * UNITS_PER_WORD ) return 0 ; return nregs * UNITS_PER_WORD - cum -> nbytes ; } </s>

Return the number of bytes of registers to use for an argument passed partially in registers and partially in memory .


"Scale factor in address must be 1, 2, 4 or 8"

"Displacement in address must fit into 32-bit signed "

Perform target-specific instruction verification .


<s> bool ARMPassConfig :: addPreISel ( ) { const ARMSubtarget * Subtarget = & getARMSubtarget ( ) ; if ( Subtarget -> hasAnyDataBarrier ( ) && ! Subtarget -> isThumb1Only ( ) ) addPass ( createAtomicExpandLoadLinkedPass ( TM ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createGlobalMergePass ( TM ) ) ; return false ; } </s>


<s> bool isMem ( ) const override { return false ; } </s>


<s> SDValue ARMTargetLowering :: BuildSDIVPow2 ( SDNode * N , const APInt & Divisor , SelectionDAG & DAG , SmallVectorImpl < SDNode * > & Created ) const { if ( N -> getOpcode ( ) != ISD :: SDIV ) return SDValue ( ) ; const auto & ST = static_cast < const ARMSubtarget & > ( DAG . getSubtarget ( ) ) ; const auto & MF = DAG . getMachineFunction ( ) ; const bool MinSize = MF . getFunction ( ) . optForMinSize ( ) ; const bool HasDivide = ST . isThumb ( ) ? ST . hasDivideInThumbMode ( ) : ST . hasDivideInARMMode ( ) ; if ( N -> getOperand ( 0 ) . getValueType ( ) . isVector ( ) ) return SDValue ( ) ; if ( ! ( MinSize && HasDivide ) ) return SDValue ( ) ; if ( ! ST . isThumb ( ) ) return SDValue ( N , 0 ) ; if ( Divisor . sgt ( 128 ) ) return SDValue ( ) ; return SDValue ( N , 0 ) ; } </s>

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators .


"Copy one register into another with a different width"


<s> static machine_mode nvptx_promote_function_mode ( const_tree type , machine_mode mode , int * punsignedp , const_tree funtype , int for_return ) { if ( type == NULL_TREE ) return mode ; if ( for_return ) return promote_mode ( type , mode , punsignedp ) ; if ( TYPE_ARG_TYPES ( funtype ) == NULL_TREE && type != NULL_TREE && ! AGGREGATE_TYPE_P ( type ) ) { if ( mode == SFmode ) mode = DFmode ; mode = arg_promotion ( mode ) ; } return mode ; } </s>


Choose the order in which to allocate hard registers for pseudo-registers local to a basic block . Store the desired register order in the array ` reg_alloc_order ' . Element 0 should be the register to allocate first ; element 1 , the next register ; and so on .


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> unsigned AMDGPUAsmParser :: checkTargetMatchPredicate ( MCInst & Inst ) { uint64_t TSFlags = MII . get ( Inst . getOpcode ( ) ) . TSFlags ; if ( ( getForcedEncodingSize ( ) == 32 && ( TSFlags & SIInstrFlags :: VOP3 ) ) || ( getForcedEncodingSize ( ) == 64 && ! ( TSFlags & SIInstrFlags :: VOP3 ) ) ) return Match_InvalidOperand ; if ( ( TSFlags & SIInstrFlags :: VOP3 ) && ( TSFlags & SIInstrFlags :: VOPAsmPrefer32Bit ) && getForcedEncodingSize ( ) != 64 ) return Match_PreferE32 ; return Match_Success ; } </s>

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .