<s> bool X86InstrInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; unsigned FPReg = RI . getFrameRegister ( MF ) ; bool is64Bit = TM . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ; bool isWin64 = TM . getSubtarget < X86Subtarget > ( ) . isTargetWin64 ( ) ; unsigned Opc = is64Bit ? X86 :: POP64r : X86 :: POP32r ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg == FPReg ) continue ; const TargetRegisterClass * RegClass = CSI [ i ] . getRegClass ( ) ; if ( RegClass != & X86 :: VR128RegClass && ! isWin64 ) { BuildMI ( MBB , MI , DL , get ( Opc ) , Reg ) ; } else { loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RegClass ) ; } } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


"  Vector-arith=%-10s Vector-mem=%-10s Reload=%c%c Upper=%c"

Print the address masks in a human readble fashion .


<s> void function_expander :: add_fixed_operand ( rtx x ) { m_ops . safe_grow ( m_ops . length ( ) + 1 ) ; create_fixed_operand ( & m_ops . last ( ) , x ) ; } </s>

Add an operand that must be X . The only way of legitimizing an invalid X is to reload the address of a MEM .


<s> void mips_output_aligned_decl_common ( FILE * stream , tree decl , const char * name , unsigned HOST_WIDE_INT size , unsigned int align ) { if ( TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA && TREE_CODE ( decl ) == VAR_DECL && TREE_READONLY ( decl ) && ( DECL_INITIAL ( decl ) == 0 || DECL_INITIAL ( decl ) == error_mark_node ) ) { if ( TREE_PUBLIC ( decl ) && DECL_NAME ( decl ) ) targetm . asm_out . globalize_label ( stream , name ) ; readonly_data_section ( ) ; ASM_OUTPUT_ALIGN ( stream , floor_log2 ( align / BITS_PER_UNIT ) ) ; mips_declare_object ( stream , name , "" , ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n" , size ) ; } else mips_declare_common_object ( stream , name , "\n\t.comm\t" , size , align , true ) ; } </s>

Implement ASM_OUTPUT_ALIGNED_DECL_COMMON . This is usually the same as the elfos.h version , but we also need to handle -muninit-const-in-rodata .


<s> static unsigned HOST_WIDE_INT mips_shift_truncation_mask ( machine_mode mode ) { if ( TARGET_LOONGSON_VECTORS && VECTOR_MODE_P ( mode ) ) return 0 ; return GET_MODE_BITSIZE ( mode ) - 1 ; } </s>

Implement TARGET_SHIFT_TRUNCATION_MASK . We want to keep the default behavior of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even when TARGET_LOONGSON_VECTORS is true .


<s> HOST_WIDE_INT alpha_vms_initial_elimination_offset ( unsigned int from , unsigned int to ) { HOST_WIDE_INT sa_size = cfun -> machine -> sa_size ; if ( alpha_procedure_type == PT_NULL ) return 0 ; { HOST_WIDE_INT offset ; HOST_WIDE_INT pv_save_size = alpha_procedure_type == PT_STACK ? 8 : 0 ; switch ( from ) { case FRAME_POINTER_REGNUM : offset = ALPHA_ROUND ( sa_size + pv_save_size ) ; break ; case ARG_POINTER_REGNUM : offset = ( ALPHA_ROUND ( sa_size + pv_save_size + get_frame_size ( ) + crtl -> args . pretend_args_size ) - crtl -> args . pretend_args_size ) ; break ; default : gcc_unreachable ( ) ; } if ( to == STACK_POINTER_REGNUM ) offset += ALPHA_ROUND ( crtl -> outgoing_args_size ) ; return offset ; } } </s>

FROM is to be eliminated for TO . Return the offset so that TO+offset designates the same location as FROM .


<s>
bool
ARMAsmBackend
::
shouldForceRelocation
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
)
{
const
MCSymbolRefExpr
*
A
=
Target
.
getSymA
(
)
;
const
MCSymbol
*
Sym
=
A
&
A
->
getSymbol
(
)
:
nullptr
;
const
unsigned
FixupKind
=
Fixup
.
getKind
(
)
;
if
(
FixupKind
>=
FirstLiteralRelocationKind
)
return
true
;
if
(
FixupKind
==
ARM
::
fixup_arm_thumb_bl
)
{
assert
(
Sym
&&
"How did we resolve this?"
)
;
if
(
Sym
->
isExternal
(
)
)
return
true
;
}
if
(
Sym
&&
Sym
->
isELF
(
)
)
{
unsigned
Type
=
cast
<
MCSymbolELF
>
(
Sym
)
->
getType
(
)
;
if
(
(
Type
==
ELF
::
STT_FUNC
||
Type
==
ELF
::
STT_GNU_IFUNC
)
)
{
if
(
Asm
.
isThumbFunc
(
Sym
)
&&
(
FixupKind
==
ARM
::
fixup_arm_uncondbranch
)
)
return
true
;
if
(
!
Asm
.
isThumbFunc
(
Sym
)
&&
(
FixupKind
==
ARM
::
fixup_arm_thumb_br
||
FixupKind
==
ARM
::
fixup_arm_thumb_bl
||
FixupKind
==
ARM
::
fixup_t2_condbranch
||
FixupKind
==
ARM
::
fixup_t2_uncondbranch
)
)
return
true
;
}
}
if
(
A
&&
(
FixupKind
==
ARM
::
fixup_arm_thumb_blx
||
FixupKind
==
ARM
::
fixup_arm_blx
||
FixupKind
==
ARM
::
fixup_arm_uncondbl
||
FixupKind
==
ARM
::
fixup_arm_condbl
)
)
return
true
;
return
false
;
}
</s>

Hook to check if a relocation is needed for some target specific reason .


<s>
void
WebAssemblyAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"EmitInstruction: "
<<
*
MI
<<
'\n'
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
WebAssembly
::
ARGUMENT_i32
:
case
WebAssembly
::
ARGUMENT_i32_S
:
case
WebAssembly
::
ARGUMENT_i64
:
case
WebAssembly
::
ARGUMENT_i64_S
:
case
WebAssembly
::
ARGUMENT_f32
:
case
WebAssembly
::
ARGUMENT_f32_S
:
case
WebAssembly
::
ARGUMENT_f64
:
case
WebAssembly
::
ARGUMENT_f64_S
:
case
WebAssembly
::
ARGUMENT_v16i8
:
case
WebAssembly
::
ARGUMENT_v16i8_S
:
case
WebAssembly
::
ARGUMENT_v8i16
:
case
WebAssembly
::
ARGUMENT_v8i16_S
:
case
WebAssembly
::
ARGUMENT_v4i32
:
case
WebAssembly
::
ARGUMENT_v4i32_S
:
case
WebAssembly
::
ARGUMENT_v2i64
:
case
WebAssembly
::
ARGUMENT_v2i64_S
:
case
WebAssembly
::
ARGUMENT_v4f32
:
case
WebAssembly
::
ARGUMENT_v4f32_S
:
case
WebAssembly
::
ARGUMENT_v2f64
:
case
WebAssembly
::
ARGUMENT_v2f64_S
:
break
;
case
WebAssembly
::
FALLTHROUGH_RETURN
:
{
if
(
isVerbose
(
)
)
{
OutStreamer
->
AddComment
(
"fallthrough-return"
)
;
OutStreamer
->
AddBlankLine
(
)
;
}
break
;
}
case
WebAssembly
::
COMPILER_FENCE
:
break
;
case
WebAssembly
::
EXTRACT_EXCEPTION_I32
:
case
WebAssembly
::
EXTRACT_EXCEPTION_I32_S
:
if
(
!
WasmKeepRegisters
)
break
;
LLVM_FALLTHROUGH
;
default
:
{
WebAssemblyMCInstLower
MCInstLowering
(
OutContext
,
*
this
)
;
MCInst
TmpInst
;
MCInstLowering
.
lower
(
MI
,
TmpInst
)
;
EmitToStreamer
(
*
OutStreamer
,
TmpInst
)
;
break
;
}
}
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static bool sparc_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { if ( aligned_p && size == 8 && GET_CODE ( x ) != CONST_INT ) { if ( TARGET_V9 ) { assemble_integer_with_op ( "\t.xword\t" , x ) ; return true ; } else { assemble_aligned_integer ( 4 , const0_rtx ) ; assemble_aligned_integer ( 4 , x ) ; return true ; } } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . The sparc version has special handling for aligned DI-mode objects .


<s>
SDNode
*
Z80DAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
DebugLoc
dl
=
Node
->
getDebugLoc
(
)
;
DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
return
;
}
switch
(
Node
->
getOpcode
(
)
)
{
default
:
break
;
}
SDNode
*
ResNode
=
SelectCode
(
Node
)
;
if
(
ResNode
==
||
ResNode
==
Node
)
DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
else
DEBUG
(
errs
(
)
<<
"\n"
)
;
return
ResNode
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> const Thumb1RegisterInfo & getRegisterInfo ( ) const override { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> Register X86FrameLowering :: getInitialCFARegister ( const MachineFunction & MF ) const { return TRI -> getDwarfRegNum ( StackPtr , true ) ; } </s>


<s> static bool mayAlias ( MachineInstr & MIa , SmallVectorImpl < MachineInstr * > & MemInsns , AliasAnalysis * AA ) { for ( MachineInstr * MIb : MemInsns ) if ( MIa . mayAlias ( AA , * MIb , false ) ) return true ; return false ; } </s>

Returns true if this instruction 's memory access aliases the memory access of Other .


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override { if ( ( Count % 2 ) != 0 ) return false ; for ( uint64_t i = 0 ; i < Count ; i += 2 ) OW -> write16 ( 0x9 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> rtx extract_nth_access_rtx ( rtx_insn * insn , int n ) { int n_elems = parallel_elements ( insn ) ; int post_update_rtx_index = find_post_update_rtx ( insn ) ; memory_access_direction direction = determine_access_direction ( insn ) ; gcc_assert ( direction != MEM_ACCESS_DIR_UNKNOWN ) ; if ( direction == MEM_ACCESS_DIR_NEG ) n = - 1 * n - 1 ; if ( post_update_rtx_index != - 1 ) { if ( n >= 0 && post_update_rtx_index <= n ) ++ n ; else if ( n < 0 && post_update_rtx_index >= n + n_elems ) -- n ; } return parallel_element ( insn , n ) ; } </s>

Return the nth load/store operation in the real micro-operation accessing order .


<s>
bool
X86InstrInfo
::
isReallyTriviallyReMaterializable
(
const
MachineInstr
*
MI
,
AliasAnalysis
*
AA
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
X86
::
MOV8rm
:
case
X86
::
MOV16rm
:
case
X86
::
MOV32rm
:
case
X86
::
MOV64rm
:
case
X86
::
LD_Fp64m
:
case
X86
::
MOVSSrm
:
case
X86
::
MOVSDrm
:
case
X86
::
MOVAPSrm
:
case
X86
::
MOVUPSrm
:
case
X86
::
MOVUPSrm_Int
:
case
X86
::
MOVAPDrm
:
case
X86
::
MOVDQArm
:
case
X86
::
MMX_MOVD64rm
:
case
X86
::
MMX_MOVQ64rm
:
case
X86
::
FsMOVAPSrm
:
case
X86
::
FsMOVAPDrm
:
{
if
(
MI
->
getOperand
(
1
)
.
isReg
(
)
&&
MI
->
getOperand
(
2
)
.
isImm
(
)
&&
MI
->
getOperand
(
3
)
.
isReg
(
)
&&
MI
->
getOperand
(
3
)
.
getReg
(
)
==
0
&&
MI
->
isInvariantLoad
(
AA
)
)
{
unsigned
BaseReg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
if
(
BaseReg
==
0
||
BaseReg
==
X86
::
RIP
)
return
true
;
if
(
!
ReMatPICStubLoad
&&
MI
->
getOperand
(
4
)
.
isGlobal
(
)
)
return
false
;
const
MachineFunction
&
MF
=
*
MI
->
getParent
(
)
->
getParent
(
)
;
const
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
bool
isPICBase
=
false
;
for
(
MachineRegisterInfo
::
def_iterator
I
=
MRI
.
def_begin
(
BaseReg
)
,
E
=
MRI
.
def_end
(
)
;
I
!=
E
;
++
I
)
{
MachineInstr
*
DefMI
=
I
.
getOperand
(
)
.
getParent
(
)
;
if
(
DefMI
->
getOpcode
(
)
!=
X86
::
MOVPC32r
)
return
false
;
assert
(
!
isPICBase
&&
"More than one PIC base?"
)
;
isPICBase
=
true
;
}
return
isPICBase
;
}
return
false
;
}
case
X86
::
LEA32r
:
case
X86
::
LEA64r
:
{
if
(
MI
->
getOperand
(
2
)
.
isImm
(
)
&&
MI
->
getOperand
(
3
)
.
isReg
(
)
&&
MI
->
getOperand
(
3
)
.
getReg
(
)
==
0
&&
!
MI
->
getOperand
(
4
)
.
isReg
(
)
)
{
if
(
!
MI
->
getOperand
(
1
)
.
isReg
(
)
)
return
true
;
unsigned
BaseReg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
if
(
BaseReg
==
0
)
return
true
;
const
MachineFunction
&
MF
=
*
MI
->
getParent
(
)
->
getParent
(
)
;
const
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
return
regIsPICBase
(
BaseReg
,
MRI
)
;
}
return
false
;
}
}
return
true
;
}
</s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s>
bool
RISCVAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Operands
.
push_back
(
RISCVOperand
::
createToken
(
Name
,
NameLoc
,
isRV64
(
)
)
)
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
return
false
;
if
(
parseOperand
(
Operands
,
shouldForceImediateOperand
(
Name
,
0
)
)
)
return
true
;
unsigned
OperandIdx
=
1
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
getLexer
(
)
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
shouldForceImediateOperand
(
Name
,
OperandIdx
)
)
)
return
true
;
++
OperandIdx
;
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
getParser
(
)
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
getParser
(
)
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

RISCV
RISCV
RISCV
0
1
"unexpected token"


<s> bool VEFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool X86PassConfig :: addPreEmitPass ( ) { bool ShouldPrint = false ; if ( getOptLevel ( ) != CodeGenOpt :: None && getX86Subtarget ( ) . hasSSE2 ( ) ) { addPass ( createExecutionDependencyFixPass ( & X86 :: VR128RegClass ) ) ; ShouldPrint = true ; } if ( getX86Subtarget ( ) . hasAVX ( ) && UseVZeroUpper ) { addPass ( createX86IssueVZeroUpperPass ( ) ) ; ShouldPrint = true ; } if ( getOptLevel ( ) != CodeGenOpt :: None && getX86Subtarget ( ) . padShortFunctions ( ) ) { addPass ( createX86PadShortFunctions ( ) ) ; ShouldPrint = true ; } if ( getOptLevel ( ) != CodeGenOpt :: None && getX86Subtarget ( ) . LEAusesAG ( ) ) { addPass ( createX86FixupLEAs ( ) ) ; ShouldPrint = true ; } return ShouldPrint ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
static
void
rs6000_xcoff_file_end
(
void
)
{
switch_to_section
(
text_section
)
;
fputs
(
"_section_.text:\n"
,
asm_out_file
)
;
switch_to_section
(
data_section
)
;
fputs
(
TARGET_32BIT
"\t.long _section_.text\n"
:
"\t.llong _section_.text\n"
,
asm_out_file
)
;
}
</s>

Output at end of assembler file . On the RS/6000 , referencing data should automatically pull in text .

powerpcspe
"_section_.text:\n"
"\t.long _section_.text\n"
"\t.llong _section_.text\n"


<s> void buildLoad ( unsigned Val , unsigned Addr , uint64_t Size , unsigned Alignment , MachinePointerInfo & MPO ) { MachineMemOperand * MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , Size , Alignment ) ; MIRBuilder . buildLoad ( Val , Addr , * MMO ) ; } </s>

Build and insert a G_LOAD instruction , while constructing the MachineMemOperand .


<s> static void tilegx_print_operand_address ( FILE * file , rtx addr ) { if ( GET_CODE ( addr ) == POST_DEC || GET_CODE ( addr ) == POST_INC ) { int offset = GET_MODE_SIZE ( output_memory_reference_mode ) ; gcc_assert ( output_memory_reference_mode != VOIDmode ) ; if ( output_memory_autoinc_first ) fprintf ( file , "%s" , reg_names [ REGNO ( XEXP ( addr , 0 ) ) ] ) ; else fprintf ( file , "%d" , GET_CODE ( addr ) == POST_DEC ? - offset : offset ) ; } else if ( GET_CODE ( addr ) == POST_MODIFY ) { gcc_assert ( output_memory_reference_mode != VOIDmode ) ; gcc_assert ( GET_CODE ( XEXP ( addr , 1 ) ) == PLUS ) ; if ( output_memory_autoinc_first ) fprintf ( file , "%s" , reg_names [ REGNO ( XEXP ( addr , 0 ) ) ] ) ; else fprintf ( file , HOST_WIDE_INT_PRINT_DEC , INTVAL ( XEXP ( XEXP ( addr , 1 ) , 1 ) ) ) ; } else tilegx_print_operand ( file , addr , 'r' ) ; } </s>


<s> static bool expand_vec_perm_2vperm2f128_vshuf ( struct expand_vec_perm_d * d ) { struct expand_vec_perm_d dfirst , dsecond , dthird ; bool ok ; if ( ! TARGET_AVX || ( d -> vmode != V4DFmode ) ) return false ; if ( d -> testing_p ) return true ; dfirst = * d ; dsecond = * d ; dthird = * d ; dfirst . perm [ 0 ] = ( d -> perm [ 0 ] & ~ 1 ) ; dfirst . perm [ 1 ] = ( d -> perm [ 0 ] & ~ 1 ) + 1 ; dfirst . perm [ 2 ] = ( d -> perm [ 2 ] & ~ 1 ) ; dfirst . perm [ 3 ] = ( d -> perm [ 2 ] & ~ 1 ) + 1 ; dsecond . perm [ 0 ] = ( d -> perm [ 1 ] & ~ 1 ) ; dsecond . perm [ 1 ] = ( d -> perm [ 1 ] & ~ 1 ) + 1 ; dsecond . perm [ 2 ] = ( d -> perm [ 3 ] & ~ 1 ) ; dsecond . perm [ 3 ] = ( d -> perm [ 3 ] & ~ 1 ) + 1 ; dthird . perm [ 0 ] = ( d -> perm [ 0 ] % 2 ) ; dthird . perm [ 1 ] = ( d -> perm [ 1 ] % 2 ) + 4 ; dthird . perm [ 2 ] = ( d -> perm [ 2 ] % 2 ) + 2 ; dthird . perm [ 3 ] = ( d -> perm [ 3 ] % 2 ) + 6 ; dfirst . target = gen_reg_rtx ( dfirst . vmode ) ; dsecond . target = gen_reg_rtx ( dsecond . vmode ) ; dthird . op0 = dfirst . target ; dthird . op1 = dsecond . target ; dthird . one_operand_p = false ; canonicalize_perm ( & dfirst ) ; canonicalize_perm ( & dsecond ) ; ok = expand_vec_perm_1 ( & dfirst ) && expand_vec_perm_1 ( & dsecond ) && expand_vec_perm_1 ( & dthird ) ; gcc_assert ( ok ) ; return true ; } </s>

A subroutine of ix86_expand_vec_perm_builtin_1 . Implement a V4DF permutation using two vperm2f128 , followed by a vshufpd insn blending the two vectors together .


"eliminateCallFramePseudoInstr not implemented yet"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


"Cannot store this register to stack slot!"


<s> bool GBZ80MCExpr :: evaluateAsConstant ( int64_t & Result ) const { MCValue Value ; bool isRelocatable = getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ; if ( ! isRelocatable ) return false ; if ( Value . isAbsolute ( ) ) { Result = evaluateAsInt64 ( Value . getConstant ( ) ) ; return true ; } return false ; } </s>

Evaluates the fixup as a constant value .


<s> void X86PassConfig :: addMachineSSAOptimization ( ) { addPass ( createX86DomainReassignmentPass ( ) ) ; TargetPassConfig :: addMachineSSAOptimization ( ) ; } </s>

Methods with trivial inline returns are convenient points in the common codegen pass pipeline where targets may insert passes .


<s>
bool
X86TargetLowering
::
shouldFoldConstantShiftPairToMask
(
const
SDNode
*
N
,
CombineLevel
Level
)
const
{
assert
(
(
(
N
->
getOpcode
(
)
==
ISD
::
SHL
&&
N
->
getOperand
(
0
)
.
getOpcode
(
)
==
ISD
::
SRL
)
||
(
N
->
getOpcode
(
)
==
ISD
::
SRL
&&
N
->
getOperand
(
0
)
.
getOpcode
(
)
==
ISD
::
SHL
)
)
&&
"Expected shift-shift mask"
)
;
EVT
VT
=
N
->
getValueType
(
0
)
;
if
(
(
Subtarget
.
hasFastVectorShiftMasks
(
)
&&
VT
.
isVector
(
)
)
||
(
Subtarget
.
hasFastScalarShiftMasks
(
)
&&
!
VT
.
isVector
(
)
)
)
{
return
N
->
getOperand
(
1
)
==
N
->
getOperand
(
0
)
.
getOperand
(
1
)
;
}
return
TargetLoweringBase
::
shouldFoldConstantShiftPairToMask
(
N
,
Level
)
;
}
</s>

Return true if it is profitable to fold a pair of shifts into a mask .


<s> static bool fr30_must_pass_in_stack ( const function_arg_info & arg ) { return arg . mode == BLKmode || arg . aggregate_type_p ( ) ; } </s>

Return true if we should pass an argument on the stack rather than in registers .


<s> bool writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const override { uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) support :: endian :: write < uint32_t > ( OS , 0x60000000 , Endian ) ; OS . write_zeros ( Count % 4 ) ; return true ; } </s>


<s>
static
void
rs6000_function_specific_print
(
FILE
*
file
,
int
indent
,
struct
cl_target_option
*
ptr
)
{
rs6000_print_isa_options
(
file
,
indent
,
"Isa options set"
,
ptr
->
x_rs6000_isa_flags
)
;
rs6000_print_isa_options
(
file
,
indent
,
"Isa options explicit"
,
ptr
->
x_rs6000_isa_flags_explicit
)
;
}
</s>

powerpcspe
"Isa options set"
"Isa options explicit"


<s> static HOST_WIDE_INT alpha_extract_integer ( rtx x ) { if ( GET_CODE ( x ) == CONST_VECTOR ) x = simplify_subreg ( DImode , x , GET_MODE ( x ) , 0 ) ; gcc_assert ( CONST_INT_P ( x ) ) ; return INTVAL ( x ) ; } </s>

Given an integral CONST_INT , CONST_DOUBLE , or CONST_VECTOR , return the low 64 bits .


<s> bool runOnMachineFunction ( MachineFunction & F ) { bool Changed = false ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool Dcpu16PassConfig :: addInstSelector ( ) { PM . add ( createDcpu16ISelDag ( getDcpu16TargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static scalar_int_mode avr_addr_space_pointer_mode ( addr_space_t as ) { return avr_addr_space_address_mode ( as ) ; } </s>

Implement ` TARGET_ADDR_SPACE_POINTER_MODE ' .


initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


"Odd number of callee-saved regs to spill!"

"Expected GPR64 callee-saved register pair!"

"Expected FPR64 callee-saved register pair!"

"Offset out of bounds for STP immediate"

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> void SystemZFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; SystemZMachineFunctionInfo * ZFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; bool BackChain = MF . getFunction ( ) . hasFnAttribute ( "backchain" ) ; if ( ! usePackedStack ( MF ) || BackChain ) getOrCreateFramePointerSaveIndex ( MF ) ; uint64_t StackSize = ( MFFrame . estimateStackSize ( MF ) + SystemZMC :: CallFrameSize ) ; int64_t MaxArgOffset = 0 ; for ( int I = MFFrame . getObjectIndexBegin ( ) ; I != 0 ; ++ I ) if ( MFFrame . getObjectOffset ( I ) >= 0 ) { int64_t ArgOffset = MFFrame . getObjectOffset ( I ) + MFFrame . getObjectSize ( I ) ; MaxArgOffset = std :: max ( MaxArgOffset , ArgOffset ) ; } uint64_t MaxReach = StackSize + MaxArgOffset ; if ( ! isUInt < 12 > ( MaxReach ) ) { RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( 8 , Align ( 8 ) , false ) ) ; RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( 8 , Align ( 8 ) , false ) ) ; } if ( MF . front ( ) . isLiveIn ( SystemZ :: R6D ) && ZFI -> getRestoreGPRRegs ( ) . LowGPR != SystemZ :: R6D ) for ( auto & MO : MRI -> use_nodbg_operands ( SystemZ :: R6D ) ) MO . setIsKill ( false ) ; } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> void GBZ80PassConfig :: addPreEmitPass ( ) { addPass ( createGBZ80PreEmitPass ( ) ) ; addPass ( & BranchRelaxationPassID ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static machine_mode riscv_promote_function_mode ( const_tree type ATTRIBUTE_UNUSED , machine_mode mode , int * punsignedp ATTRIBUTE_UNUSED , const_tree fntype ATTRIBUTE_UNUSED , int for_return ATTRIBUTE_UNUSED ) { int unsignedp ; if ( type != NULL_TREE ) return promote_mode ( type , mode , punsignedp ) ; unsignedp = * punsignedp ; PROMOTE_MODE ( as_a < scalar_mode > ( mode ) , unsignedp , type ) ; * punsignedp = unsignedp ; return mode ; } </s>


<s> TargetPassConfig * SparcTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new SparcPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> const char * Z80TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case Z80ISD :: CALL : return "Z80ISD::CALL" ; case Z80ISD :: RET : return "Z80ISD::RET" ; case Z80ISD :: SEXTLOAD_I8 : return "Z80ISD::SEXTLOAD_i8" ; case Z80ISD :: ZEXTLOAD_I8 : return "Z80ISD::ZEXTLOAD_i8" ; default : return nullptr ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> bool Z80TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( AM . Scale ) return false ; if ( AM . BaseGV && AM . HasBaseReg ) return false ; if ( AM . BaseGV ) return AM . BaseOffs == 0 ; if ( AM . HasBaseReg ) return isInt < 8 > ( AM . BaseOffs ) ; return false ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> bool mcore_r15_operand_p ( rtx x ) { switch ( GET_CODE ( x ) ) { case CONST_INT : return mcore_const_ok_for_inline ( INTVAL ( x ) ) ; case REG : case SUBREG : case MEM : return 1 ; default : return 0 ; } } </s>

Return true if X is something that can be moved directly into r15 .


<s> const uint32_t * ARMBaseRegisterInfo :: getThisReturnPreservedMask ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return nullptr ; return STI . isTargetDarwin ( ) ? CSR_iOS_ThisReturn_RegMask : CSR_AAPCS_ThisReturn_RegMask ; } </s>

getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned ' is on an i32 first argument if the calling convention is one that can ( partially ) model this attribute with a preserved mask ( i.e .


<s> void EmitInstruction ( MCStreamer & Out , const MCInst & Inst ) { Out . EmitInstruction ( Inst , STI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool isVerboseAsm ( ) const override { return IsVerboseAsm ; } </s>

Return true if this streamer supports verbose assembly and if it is enabled .


<s>
const
MCFixupKindInfo
&
MINA32AsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
MINA32
::
NumTargetFixupKinds
]
=
{
{
"fixup_u8"
,
0
,
8
,
0
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> static bool visium_legitimate_constant_p ( enum machine_mode mode ATTRIBUTE_UNUSED , rtx x ATTRIBUTE_UNUSED ) { return true ; } </s>

Return true if X is a legitimate constant for a MODE immediate operand . X is guaranteed to satisfy the CONSTANT_P predicate .


<s> static void workaround_arc_anomaly ( void ) { rtx_insn * insn , * succ0 ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { succ0 = next_real_insn ( insn ) ; if ( arc_hazard ( insn , succ0 ) || arc_check_release31a ( insn , succ0 ) ) emit_insn_before ( gen_nopv ( ) , succ0 ) ; } if ( ! TARGET_ARC700 ) return ; if ( arc_tune != ARC_TUNE_ARC7XX ) check_store_cacheline_hazard ( ) ; } </s>

The same functionality as arc_hazard . It is called in machine reorg before any other optimization . Hence , the NOP size is taken into account when doing branch shortening .


<s> int pdp10_first_parm_offset ( ) { tree attr = DECL_ATTRIBUTES ( current_function_decl ) ; if ( attr != NULL_TREE && lookup_attribute ( "noreturn" , attr ) ) return 0 ; return - 1 ; } </s>


This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool X86TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( VT . getSizeInBits ( ) == 64 ) return false ; return ( VT . getVectorNumElements ( ) == 2 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isMOVLMask ( M , VT ) || isSHUFPMask ( M , VT ) || isPSHUFDMask ( M , VT ) || isPSHUFHWMask ( M , VT ) || isPSHUFLWMask ( M , VT ) || isUNPCKLMask ( M , VT ) || isUNPCKHMask ( M , VT ) || isUNPCKL_v_undef_Mask ( M , VT ) || isUNPCKH_v_undef_Mask ( M , VT ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> unsigned postOffset ( Align Alignment = Align ( 1 ) ) const { unsigned PO = Offset + Size ; const Align PA = std :: max ( PostAlign , Alignment ) ; if ( PA == Align ( 1 ) ) return PO ; return PO + UnknownPadding ( PA , internalKnownBits ( ) ) ; } </s>

Compute the offset immediately following this block .


<s> unsigned AArch64RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case AArch64 :: GPR32RegClassID : case AArch64 :: GPR32spRegClassID : case AArch64 :: GPR32allRegClassID : case AArch64 :: GPR64spRegClassID : case AArch64 :: GPR64allRegClassID : case AArch64 :: GPR64RegClassID : case AArch64 :: GPR32commonRegClassID : case AArch64 :: GPR64commonRegClassID : return 32 - 1 - ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) - ( TT . isOSDarwin ( ) || ReserveX18 ) - hasBasePointer ( MF ) ; case AArch64 :: FPR8RegClassID : case AArch64 :: FPR16RegClassID : case AArch64 :: FPR32RegClassID : case AArch64 :: FPR64RegClassID : case AArch64 :: FPR128RegClassID : return 32 ; case AArch64 :: DDRegClassID : case AArch64 :: DDDRegClassID : case AArch64 :: DDDDRegClassID : case AArch64 :: QQRegClassID : case AArch64 :: QQQRegClassID : case AArch64 :: QQQQRegClassID : return 32 ; case AArch64 :: FPR128_loRegClassID : return 16 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> static scalar_int_mode avr_addr_space_address_mode ( addr_space_t as ) { return avr_addrspace [ as ] . pointer_size == 3 ? PSImode : HImode ; } </s>

Implement ` TARGET_ADDR_SPACE_ADDRESS_MODE ' .


<s>
void
X86InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
assert
(
MF
.
getFrameInfo
(
)
->
getObjectSize
(
FrameIdx
)
>=
RC
->
getSize
(
)
&&
"Stack slot too small for store"
)
;
unsigned
Alignment
=
std
::
max
<
uint32_t
>
(
RC
->
getSize
(
)
,
16
)
;
bool
isAligned
=
(
TM
.
getFrameLowering
(
)
->
getStackAlignment
(
)
>=
Alignment
)
||
RI
.
canRealignStack
(
MF
)
;
unsigned
Opc
=
getStoreRegOpcode
(
SrcReg
,
RC
,
isAligned
,
TM
)
;
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> static void push ( int rn ) { rtx reg = gen_rtx_REG ( word_mode , rn ) ; rtx x ; if ( TARGET_H8300 ) x = gen_push_h8300 ( reg ) ; else if ( ! TARGET_NORMAL_MODE ) x = gen_push_h8300hs_advanced ( reg ) ; else x = gen_push_h8300hs_normal ( reg ) ; x = emit_insn ( x ) ; REG_NOTES ( x ) = gen_rtx_EXPR_LIST ( REG_INC , stack_pointer_rtx , 0 ) ; } </s>

Output RTL to push register RN onto the stack .


<s> int getCallFrameSize ( ) override final { return SystemZMC :: ELFCallFrameSize ; } </s>

Return the call frame size on entry to this basic block .


<s>
void
RISCVTTIImpl
::
getUnrollingPreferences
(
Loop
*
L
,
ScalarEvolution
&
SE
,
TTI
::
UnrollingPreferences
&
UP
,
OptimizationRemarkEmitter
*
ORE
)
{
bool
UseDefaultPreferences
=
true
;
if
(
ST
->
getProcFamily
(
)
==
RISCVSubtarget
::
SiFive7
)
UseDefaultPreferences
=
false
;
if
(
UseDefaultPreferences
)
return
BasicTTIImplBase
::
getUnrollingPreferences
(
L
,
SE
,
UP
,
ORE
)
;
UP
.
UpperBound
=
true
;
UP
.
OptSizeThreshold
=
0
;
UP
.
PartialOptSizeThreshold
=
0
;
if
(
L
->
getHeader
(
)
->
getParent
(
)
->
hasOptSize
(
)
)
return
;
SmallVector
<
BasicBlock
*
,
4
>
ExitingBlocks
;
L
->
getExitingBlocks
(
ExitingBlocks
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Loop has:\n"
<<
"Blocks: "
<<
L
->
getNumBlocks
(
)
<<
"\n"
<<
"Exit blocks: "
<<
ExitingBlocks
.
size
(
)
<<
"\n"
)
;
if
(
ExitingBlocks
.
size
(
)
>
2
)
return
;
if
(
L
->
getNumBlocks
(
)
>
4
)
return
;
if
(
getBooleanLoopAttribute
(
L
,
"llvm.loop.isvectorized"
)
)
return
;
InstructionCost
Cost
=
0
;
for
(
auto
*
BB
:
L
->
getBlocks
(
)
)
{
for
(
auto
&
I
:
*
BB
)
{
if
(
I
.
getType
(
)
->
isVectorTy
(
)
)
return
;
if
(
isa
<
CallInst
>
(
I
)
||
isa
<
InvokeInst
>
(
I
)
)
{
if
(
const
Function
*
F
=
cast
<
CallBase
>
(
I
)
.
getCalledFunction
(
)
)
{
if
(
!
isLoweredToCall
(
F
)
)
continue
;
}
return
;
}
SmallVector
<
const
Value
*
>
Operands
(
I
.
operand_values
(
)
)
;
Cost
+=
getUserCost
(
&
I
,
Operands
,
TargetTransformInfo
::
TCK_SizeAndLatency
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Cost of loop: "
<<
Cost
<<
"\n"
)
;
UP
.
Partial
=
true
;
UP
.
Runtime
=
true
;
UP
.
UnrollRemainder
=
true
;
UP
.
UnrollAndJam
=
true
;
UP
.
UnrollAndJamInnerLoopThreshold
=
60
;
if
(
Cost
<
12
)
UP
.
Force
=
true
;
}
</s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> std :: unique_ptr < SystemZFrameLowering > SystemZFrameLowering :: create ( const SystemZSubtarget & STI ) { if ( STI . isTargetXPLINK64 ( ) ) return std :: make_unique < SystemZXPLINKFrameLowering > ( ) ; return std :: make_unique < SystemZELFFrameLowering > ( ) ; } </s>

SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ


<s> static const char * ia64_mangle_type ( const_tree type ) { type = TYPE_MAIN_VARIANT ( type ) ; if ( TREE_CODE ( type ) != VOID_TYPE && TREE_CODE ( type ) != BOOLEAN_TYPE && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE ) return NULL ; if ( ! TARGET_HPUX && TYPE_MODE ( type ) == TFmode ) return "g" ; if ( TYPE_MODE ( type ) == XFmode ) return TARGET_HPUX ? "u9__float80" : "e" ; if ( TYPE_MODE ( type ) == RFmode ) return "u7__fpreg" ; return NULL ; } </s>

Return the mangling of TYPE if it is an extended fundamental type .


<s>
const
MipsMCExpr
*
MipsMCExpr
::
Create
(
MCSymbolRefExpr
::
VariantKind
VK
,
const
MCExpr
*
Expr
,
MCContext
&
Ctx
)
{
VariantKind
Kind
;
switch
(
VK
)
{
case
MCSymbolRefExpr
::
VK_Mips_ABS_LO
:
Kind
=
VK_Mips_LO
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_ABS_HI
:
Kind
=
VK_Mips_HI
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_HIGHER
:
Kind
=
VK_Mips_HIGHER
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_HIGHEST
:
Kind
=
VK_Mips_HIGHEST
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_IJMP_HI
:
Kind
=
VK_Mips_IJMP_HI
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_IJMP_LO
:
Kind
=
VK_Mips_IJMP_LO
;
break
;
default
:
llvm_unreachable
(
"Invalid kind!"
)
;
}
return
new
(
Ctx
)
MipsMCExpr
(
Kind
,
Expr
)
;
}
</s>

Construct a unary instruction , given the opcode and an operand .

Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
"Invalid kind!"
Mips


<s> unsigned AVRInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { case AVR :: STDPtrQRr : case AVR :: STDWPtrQRr : { if ( MI . getOperand ( 0 ) . isFI ( ) && MI . getOperand ( 1 ) . isImm ( ) && MI . getOperand ( 1 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 0 ) . getIndex ( ) ; return MI . getOperand ( 2 ) . getReg ( ) ; } break ; } default : break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


"%s expects a compile time integer constant"

"%s expects a compile time long integer constant"

"rounding to %d bits has no effect for "

"fixed-point value with %d fractional bits"

Expand an expression EXP that calls a built-in function , with result going to TARGET if that 's convenient ( and in mode MODE if that 's convenient ) . SUBTARGET may be used as the target for computing one of EXP 's operands . IGNORE is nonzero if the value is to be ignored .


<s> MCObjectWriter * MipsAsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { return createMipsELFObjectWriter ( OS , TheTriple , IsN32 ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> TargetLowering :: ConstraintWeight ARMTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'l' : if ( type -> isIntegerTy ( ) ) { if ( Subtarget -> isThumb ( ) ) weight = CW_SpecificReg ; else weight = CW_Register ; } break ; case 'w' : if ( type -> isFloatingPointTy ( ) ) weight = CW_Register ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s>
bool
AArch64PostSelectOptimize
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
MF
.
getProperties
(
)
.
hasProperty
(
MachineFunctionProperties
::
Property
::
FailedISel
)
)
return
false
;
assert
(
MF
.
getProperties
(
)
.
hasProperty
(
MachineFunctionProperties
::
Property
::
Selected
)
&&
"Expected a selected MF"
)
;
bool
Changed
=
false
;
for
(
auto
&
BB
:
MF
)
Changed
|=
optimizeNZCVDefs
(
BB
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool X86TargetLowering :: isFMAFasterThanFMulAndFAdd ( EVT VT ) const { if ( ! Subtarget . hasAnyFMA ( ) ) return false ; VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f32 : case MVT :: f64 : return true ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


"Couldn't get MachineMemOperand for store to stack."

"Only support 4-byte stores to stack now."

"Only support GPR32 stores to stack now."


<s> static void ia64_h_i_d_extended ( void ) { if ( stops_p != NULL ) { int new_clocks_length = get_max_uid ( ) * 3 / 2 ; stops_p = ( char * ) xrecalloc ( stops_p , new_clocks_length , clocks_length , 1 ) ; clocks_length = new_clocks_length ; } } </s>

Implement targetm.sched.h_i_d_extended hook . Extend internal data structures .


<s> void s390_expand_vcond ( rtx target , rtx then , rtx els , enum rtx_code cond , rtx cmp_op1 , rtx cmp_op2 ) { rtx tmp ; machine_mode result_mode ; rtx result_target ; machine_mode target_mode = GET_MODE ( target ) ; machine_mode cmp_mode = GET_MODE ( cmp_op1 ) ; rtx op = ( cond == LT ) ? els : then ; if ( ( cond == LT || cond == GE ) && target_mode == cmp_mode && cmp_op2 == CONST0_RTX ( cmp_mode ) && op == CONST0_RTX ( target_mode ) && s390_vector_mode_supported_p ( target_mode ) && GET_MODE_CLASS ( target_mode ) == MODE_VECTOR_INT ) { rtx negop = ( cond == LT ) ? then : els ; int shift = GET_MODE_BITSIZE ( GET_MODE_INNER ( target_mode ) ) - 1 ; if ( negop == CONST1_RTX ( target_mode ) ) { rtx res = expand_simple_binop ( cmp_mode , LSHIFTRT , cmp_op1 , GEN_INT ( shift ) , target , 1 , OPTAB_DIRECT ) ; if ( res != target ) emit_move_insn ( target , res ) ; return ; } else if ( all_ones_operand ( negop , target_mode ) ) { rtx res = expand_simple_binop ( cmp_mode , ASHIFTRT , cmp_op1 , GEN_INT ( shift ) , target , 0 , OPTAB_DIRECT ) ; if ( res != target ) emit_move_insn ( target , res ) ; return ; } } result_mode = related_int_vector_mode ( cmp_mode ) . require ( ) ; result_target = gen_reg_rtx ( result_mode ) ; if ( ! REG_P ( cmp_op1 ) ) cmp_op1 = force_reg ( GET_MODE ( cmp_op1 ) , cmp_op1 ) ; s390_expand_vec_compare ( result_target , cond , cmp_op1 , cmp_op2 ) ; if ( all_ones_operand ( then , GET_MODE ( then ) ) && const0_operand ( els , GET_MODE ( els ) ) ) { emit_move_insn ( target , gen_rtx_SUBREG ( target_mode , result_target , 0 ) ) ; return ; } if ( ! REG_P ( then ) ) then = force_reg ( target_mode , then ) ; if ( ! REG_P ( els ) ) els = force_reg ( target_mode , els ) ; tmp = gen_rtx_fmt_ee ( EQ , VOIDmode , result_target , CONST0_RTX ( result_mode ) ) ; tmp = gen_rtx_IF_THEN_ELSE ( target_mode , tmp , els , then ) ; gcc_assert ( target_mode == GET_MODE ( then ) ) ; emit_insn ( gen_rtx_SET ( target , tmp ) ) ; } </s>

Generate a vector comparison expression loading either elements of THEN or ELS into TARGET depending on the comparison COND of CMP_OP1 and CMP_OP2 .


<s> void doInitialization ( Module & M ) { } </s>

Set up the AsmPrinter when we are working on a new module .


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCRelaxableFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
override
{
llvm_unreachable
(
"RelaxInstruction() unimplemented"
)
;
return
false
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> static void c6x_init_sched_context ( void * _sc , bool clean_p ) { c6x_sched_context_t sc = ( c6x_sched_context_t ) _sc ; if ( clean_p ) { init_sched_state ( sc ) ; } else { * sc = ss ; sc -> prev_cycle_state_ctx = xmalloc ( dfa_state_size ) ; memcpy ( sc -> prev_cycle_state_ctx , prev_cycle_state , dfa_state_size ) ; } } </s>

If CLEAN_P is true then initializes _SC with clean data , and from the global context otherwise .


<s> HOST_WIDE_INT iq2000_debugger_offset ( rtx addr , HOST_WIDE_INT offset ) { rtx offset2 = const0_rtx ; rtx reg = eliminate_constant_term ( addr , & offset2 ) ; if ( offset == 0 ) offset = INTVAL ( offset2 ) ; if ( reg == stack_pointer_rtx || reg == frame_pointer_rtx || reg == hard_frame_pointer_rtx ) { HOST_WIDE_INT frame_size = ( ! cfun -> machine -> initialized ) ? compute_frame_size ( get_frame_size ( ) ) : cfun -> machine -> total_size ; offset = offset - frame_size ; } return offset ; } </s>

The arg pointer ( which is eliminated ) points to the virtual frame pointer , while the frame pointer ( which may be eliminated ) points to the stack pointer after the initial adjustments .


<s> const TriCoreRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> bool hasUsableDivScaleConditionOutput ( ) const { return getGeneration ( ) != SOUTHERN_ISLANDS ; } </s>

Condition output from div_scale is usable .


<s>
bool
AArch64MIPeepholeOpt
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
TII
=
static_cast
<
const
AArch64InstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
TRI
=
static_cast
<
const
AArch64RegisterInfo
*
>
(
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
)
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
assert
(
MRI
->
isSSA
(
)
&&
"Expected to be run on SSA form!"
)
;
bool
Changed
=
false
;
SmallSetVector
<
MachineInstr
*
,
8
>
ToBeRemoved
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
for
(
MachineInstr
&
MI
:
MBB
)
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
AArch64
::
ANDWrr
:
Changed
=
visitAND
<
uint32_t
>
(
AArch64
::
ANDWri
,
MI
,
ToBeRemoved
)
;
break
;
case
AArch64
::
ANDXrr
:
Changed
=
visitAND
<
uint64_t
>
(
AArch64
::
ANDXri
,
MI
,
ToBeRemoved
)
;
break
;
case
AArch64
::
ORRWrs
:
Changed
=
visitORR
(
MI
,
ToBeRemoved
)
;
break
;
case
AArch64
::
ADDWrr
:
Changed
=
visitADDSUB
<
uint32_t
>
(
AArch64
::
ADDWri
,
AArch64
::
SUBWri
,
MI
,
ToBeRemoved
)
;
break
;
case
AArch64
::
SUBWrr
:
Changed
=
visitADDSUB
<
uint32_t
>
(
AArch64
::
SUBWri
,
AArch64
::
ADDWri
,
MI
,
ToBeRemoved
)
;
break
;
case
AArch64
::
ADDXrr
:
Changed
=
visitADDSUB
<
uint64_t
>
(
AArch64
::
ADDXri
,
AArch64
::
SUBXri
,
MI
,
ToBeRemoved
)
;
break
;
case
AArch64
::
SUBXrr
:
Changed
=
visitADDSUB
<
uint64_t
>
(
AArch64
::
SUBXri
,
AArch64
::
ADDXri
,
MI
,
ToBeRemoved
)
;
break
;
}
}
}
for
(
MachineInstr
*
MI
:
ToBeRemoved
)
MI
->
eraseFromParent
(
)
;
return
Changed
;
}
</s>


<s> static rtx riscv_split_integer ( HOST_WIDE_INT val , machine_mode mode ) { unsigned HOST_WIDE_INT loval = sext_hwi ( val , 32 ) ; unsigned HOST_WIDE_INT hival = sext_hwi ( ( val - loval ) >> 32 , 32 ) ; rtx hi = gen_reg_rtx ( mode ) , lo = gen_reg_rtx ( mode ) ; riscv_move_integer ( hi , hi , hival , mode , FALSE ) ; riscv_move_integer ( lo , lo , loval , mode , FALSE ) ; hi = gen_rtx_fmt_ee ( ASHIFT , mode , hi , GEN_INT ( 32 ) ) ; hi = force_reg ( mode , hi ) ; return gen_rtx_fmt_ee ( PLUS , mode , hi , lo ) ; } </s>

Try to split a 64b integer into 32b parts , then reassemble .


<s> static section * pa_function_section ( tree decl , enum node_frequency freq , bool startup , bool exit ) { if ( ! targetm_common . have_named_sections ) return text_section ; if ( decl && DECL_SECTION_NAME ( decl ) == NULL && DECL_CONTEXT ( decl ) != NULL_TREE && TREE_CODE ( DECL_CONTEXT ( decl ) ) == FUNCTION_DECL && DECL_SECTION_NAME ( DECL_CONTEXT ( decl ) ) == NULL ) return function_section ( DECL_CONTEXT ( decl ) ) ; return default_function_section ( decl , freq , startup , exit ) ; } </s>


<s> void PPCHazardRecognizer970 :: Reset ( ) { LastWasBL8_ELF = false ; EndDispatchGroup ( ) ; } </s>


<s> static rtx riscv_function_arg ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; struct riscv_arg_info info ; if ( arg . end_marker_p ( ) ) return NULL ; return riscv_get_arg_info ( & info , cum , arg . mode , arg . type , arg . named , false ) ; } </s>


<s> static inline bool is_float128_p ( tree t ) { return ( t == float128_type_node || ( TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 && t == long_double_type_node ) ) ; } </s>

Check whether the type of an argument , T , is compatible with a type ID stored into a struct altivec_builtin_types . Integer types are considered compatible ; otherwise , the language hook lang_hooks.types_compatible_p makes the decision . Also allow long double and _Float128 to be compatible if -mabi=ieeelongdouble .


<s> EVT AArch64TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { bool Fast ; const Function * F = MF . getFunction ( ) ; if ( Subtarget -> hasFPARMv8 ( ) && ! IsMemset && Size >= 16 && ! F -> hasFnAttribute ( Attribute :: NoImplicitFloat ) && ( memOpAlign ( SrcAlign , DstAlign , 16 ) || ( allowsMisalignedMemoryAccesses ( MVT :: f128 , 0 , 1 , & Fast ) && Fast ) ) ) return MVT :: f128 ; if ( Size >= 8 && ( memOpAlign ( SrcAlign , DstAlign , 8 ) || ( allowsMisalignedMemoryAccesses ( MVT :: i64 , 0 , 1 , & Fast ) && Fast ) ) ) return MVT :: i64 ; if ( Size >= 4 && ( memOpAlign ( SrcAlign , DstAlign , 4 ) || ( allowsMisalignedMemoryAccesses ( MVT :: i32 , 0 , 1 , & Fast ) && Fast ) ) ) return MVT :: i32 ; return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s>
void
SystemZMCAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsPCRel
)
const
{
MCFixupKind
Kind
=
Fixup
.
getKind
(
)
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
unsigned
BitSize
=
getFixupKindInfo
(
Kind
)
.
TargetSize
;
unsigned
Size
=
(
BitSize
+
7
)
/
8
;
assert
(
Offset
+
Size
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
Value
=
extractBitsForFixup
(
Kind
,
Value
)
;
if
(
BitSize
<
64
)
Value
&=
(
(
uint64_t
)
1
<<
BitSize
)
1
;
unsigned
ShiftValue
=
(
Size
*
8
)
8
;
for
(
unsigned
I
=
0
;
I
!=
Size
;
++
I
)
{
Data
[
Offset
+
I
]
|=
uint8_t
(
Value
>>
ShiftValue
)
;
ShiftValue
-=
8
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> SDValue PPCTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { if ( Subtarget . isAIXABI ( ) ) return LowerFormalArguments_AIX ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; if ( Subtarget . is64BitELFABI ( ) ) return LowerFormalArguments_64SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; assert ( Subtarget . is32BitELFABI ( ) ) ; return LowerFormalArguments_32SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> void P2InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << StringRef ( getRegisterName ( RegNo ) ) . lower ( ) ; } </s>


"Switch should handle all register classes"


<s> InstructionCost HexagonTTIImpl :: getIntrinsicInstrCost ( const IntrinsicCostAttributes & ICA , TTI :: TargetCostKind CostKind ) { if ( ICA . getID ( ) == Intrinsic :: bswap ) { std :: pair < InstructionCost , MVT > LT = TLI . getTypeLegalizationCost ( DL , ICA . getReturnType ( ) ) ; return LT . first + 2 ; } return BaseT :: getIntrinsicInstrCost ( ICA , CostKind ) ; } </s>


<s> void avr_init_expanders ( void ) { int regno ; for ( regno = 0 ; regno < 32 ; regno ++ ) all_regs_rtx [ regno ] = gen_rtx_REG ( QImode , regno ) ; lpm_reg_rtx = all_regs_rtx [ LPM_REGNO ] ; tmp_reg_rtx = all_regs_rtx [ AVR_TMP_REGNO ] ; zero_reg_rtx = all_regs_rtx [ AVR_ZERO_REGNO ] ; lpm_addr_reg_rtx = gen_rtx_REG ( HImode , REG_Z ) ; sreg_rtx = gen_rtx_MEM ( QImode , GEN_INT ( avr_addr . sreg ) ) ; rampd_rtx = gen_rtx_MEM ( QImode , GEN_INT ( avr_addr . rampd ) ) ; rampx_rtx = gen_rtx_MEM ( QImode , GEN_INT ( avr_addr . rampx ) ) ; rampy_rtx = gen_rtx_MEM ( QImode , GEN_INT ( avr_addr . rampy ) ) ; rampz_rtx = gen_rtx_MEM ( QImode , GEN_INT ( avr_addr . rampz ) ) ; xstring_empty = gen_rtx_CONST_STRING ( VOIDmode , "" ) ; xstring_e = gen_rtx_CONST_STRING ( VOIDmode , "e" ) ; if ( AVR_TINY ) avr_have_dimode = false ; } </s>


<s>
void
PPCInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
;
if
(
PPC
::
GPRCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
OR
;
else
if
(
PPC
::
G8RCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
OR8
;
else
if
(
PPC
::
F4RCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
FMR
;
else
if
(
PPC
::
CRRCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
MCRF
;
else
if
(
PPC
::
VRRCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
VOR
;
else
if
(
PPC
::
CRBITRCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
CROR
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
const
TargetInstrDesc
&
TID
=
get
(
Opc
)
;
if
(
TID
.
getNumOperands
(
)
==
3
)
BuildMI
(
MBB
,
I
,
DL
,
TID
,
DestReg
)
.
addReg
(
SrcReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
BuildMI
(
MBB
,
I
,
DL
,
TID
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>

PowerPC
PPC
PPC::GPRCRegClass
PPC::OR
PPC::G8RCRegClass
PPC::OR8
PPC::F4RCRegClass
PPC::FMR
PPC::CRRCRegClass
PPC::MCRF
PPC::VRRCRegClass
PPC::VOR
PPC::CRBITRCRegClass
PPC::CROR
"Impossible reg-to-reg copy"
3


<s> void Thumb1FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const Thumb1InstrInfo & TII = * static_cast < const Thumb1InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; const Thumb1RegisterInfo * RegInfo = static_cast < const Thumb1RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; DebugLoc dl = Old -> getDebugLoc ( ) ; unsigned Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { unsigned Align = getStackAlignment ( ) ; Amount = ( Amount + Align - 1 ) / Align * Align ; unsigned Opc = Old -> getOpcode ( ) ; if ( Opc == ARM :: ADJCALLSTACKDOWN || Opc == ARM :: tADJCALLSTACKDOWN ) { emitSPUpdate ( MBB , I , TII , dl , * RegInfo , - Amount ) ; } else { assert ( Opc == ARM :: ADJCALLSTACKUP || Opc == ARM :: tADJCALLSTACKUP ) ; emitSPUpdate ( MBB , I , TII , dl , * RegInfo , Amount ) ; } } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


"Not all fixup kinds added to Infos array"


"Replacing load %d with permuted load\n"

Convert the non-permuting load INSN to a permuting one .


<s> void NodeBase :: append ( NodeAddr < NodeBase * > NA ) { NodeId Nx = Next ; if ( Next != NA . Id ) { Next = NA . Id ; NA . Addr -> Next = Nx ; } } </s>


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override { ScheduleDAGMI * DAG = createGenericSchedPostRA ( C ) ; const GCNSubtarget & ST = C -> MF -> getSubtarget < GCNSubtarget > ( ) ; DAG -> addMutation ( createLoadClusterDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; DAG -> addMutation ( ST . createFillMFMAShadowMutation ( DAG -> TII ) ) ; return DAG ; } </s>

Similar to createMachineScheduler but used when postRA machine scheduling is enabled .


<s> void JVMPassConfig :: addPostRegAlloc ( ) { disablePass ( & ShrinkWrapID ) ; disablePass ( & MachineCopyPropagationID ) ; disablePass ( & PostRASchedulerID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & StackMapLivenessID ) ; disablePass ( & LiveDebugValuesID ) ; disablePass ( & PatchableFunctionID ) ; disablePass ( & PrologEpilogCodeInserterID ) ; TargetPassConfig :: addPostRegAlloc ( ) ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s>
void
PPCTargetLowering
::
LowerAsmOperandForConstraint
(
SDValue
Op
,
char
Letter
,
bool
hasMemory
,
std
::
vector
<
SDValue
>
&
Ops
,
SelectionDAG
&
DAG
)
const
{
SDValue
Result
(
0
,
0
)
;
switch
(
Letter
)
{
default
:
break
;
case
'I'
:
case
'J'
:
case
'K'
:
case
'L'
:
case
'M'
:
case
'N'
:
case
'O'
:
case
'P'
:
{
ConstantSDNode
*
CST
=
dyn_cast
<
ConstantSDNode
>
(
Op
)
;
if
(
!
CST
)
return
;
unsigned
Value
=
CST
->
getZExtValue
(
)
;
switch
(
Letter
)
{
default
:
llvm_unreachable
(
"Unknown constraint letter!"
)
;
case
'I'
:
if
(
(
short
)
Value
==
(
int
)
Value
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'J'
:
case
'L'
:
if
(
(
short
)
Value
==
0
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'K'
:
if
(
(
Value
>>
16
)
==
0
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'M'
:
if
(
Value
>
31
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'N'
:
if
(
(
int
)
Value
>
0
&&
isPowerOf2_32
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'O'
:
if
(
Value
==
0
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'P'
:
if
(
(
short
)
Value
==
(
int
)
Value
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
}
break
;
}
}
if
(
Result
.
getNode
(
)
)
{
Ops
.
push_back
(
Result
)
;
return
;
}
TargetLowering
::
LowerAsmOperandForConstraint
(
Op
,
Letter
,
hasMemory
,
Ops
,
DAG
)
;
}
</s>

Lower the specified operand into the Ops vector .


<s> static bool mips_expand_vpc_loongson_pshufh ( struct expand_vec_perm_d * d ) { unsigned i , mask ; rtx rmask ; if ( ! ( TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS ) ) return false ; if ( d -> vmode != V4HImode ) return false ; if ( d -> testing_p ) return true ; for ( i = mask = 0 ; i < 4 ; i ++ ) mask |= ( d -> perm [ i ] & 3 ) << ( i * 2 ) ; rmask = force_reg ( SImode , GEN_INT ( mask ) ) ; if ( d -> one_vector_p ) emit_insn ( gen_loongson_pshufh ( d -> target , d -> op0 , rmask ) ) ; else { rtx t0 , t1 , x , merge , rmerge [ 4 ] ; t0 = gen_reg_rtx ( V4HImode ) ; t1 = gen_reg_rtx ( V4HImode ) ; emit_insn ( gen_loongson_pshufh ( t1 , d -> op1 , rmask ) ) ; emit_insn ( gen_loongson_pshufh ( t0 , d -> op0 , rmask ) ) ; for ( i = 0 ; i < 4 ; ++ i ) rmerge [ i ] = ( d -> perm [ i ] & 4 ? constm1_rtx : const0_rtx ) ; merge = gen_rtx_CONST_VECTOR ( V4HImode , gen_rtvec_v ( 4 , rmerge ) ) ; merge = force_reg ( V4HImode , merge ) ; x = gen_rtx_AND ( V4HImode , merge , t1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , t1 , x ) ) ; x = gen_rtx_NOT ( V4HImode , merge ) ; x = gen_rtx_AND ( V4HImode , x , t0 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , t0 , x ) ) ; x = gen_rtx_IOR ( V4HImode , t0 , t1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , d -> target , x ) ) ; } return true ; } </s>

Recognize patterns for the Loongson PSHUFH instruction .


"Can't load this register from stack slot"


<s> void mmix_setup_frame_addresses ( void ) { } </s>


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> unsigned ARMBaseRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; if ( TFI -> hasFP ( MF ) ) return FramePtr ; return ARM :: SP ; } </s>


<s> const WebAssemblySubtarget * WebAssemblyTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; resetTargetOptions ( F ) ; return getSubtargetImpl ( CPU , FS ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

WebAssembly WebAssembly WebAssembly "target-cpu" "target-features"


<s> unsigned getNumFixupKinds ( ) const override { return Xtensa :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> void BTFTypeEnum :: completeType ( BTFDebug & BDebug ) { if ( IsCompleted ) return ; IsCompleted = true ; BTFType . NameOff = BDebug . addString ( ETy -> getName ( ) ) ; DINodeArray Elements = ETy -> getElements ( ) ; for ( const auto Element : Elements ) { const auto * Enum = cast < DIEnumerator > ( Element ) ; struct BTF :: BTFEnum BTFEnum ; BTFEnum . NameOff = BDebug . addString ( Enum -> getName ( ) ) ; BTFEnum . Val = static_cast < uint32_t > ( Enum -> getValue ( ) ) ; EnumValues . push_back ( BTFEnum ) ; } } </s>

Complete BTF type generation after all related DebugInfo types have been visited so their BTF type id 's are available for cross referece .


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( N -> getOpcode ( ) == X86ISD :: CALL || ( N -> getOpcode ( ) == X86ISD :: TC_RETURN && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; EVT SrcVT = N -> getOperand ( 0 ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( 0 ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; bool SrcIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> static rtx dump_constants_1 ( enum machine_mode mode , rtx value , rtx insn ) { switch ( GET_MODE_CLASS ( mode ) ) { case MODE_INT : { rtx size = GEN_INT ( GET_MODE_SIZE ( mode ) ) ; return emit_insn_after ( gen_consttable_int ( value , size ) , insn ) ; } case MODE_FLOAT : return emit_insn_after ( gen_consttable_float ( value ) , insn ) ; case MODE_VECTOR_FLOAT : case MODE_VECTOR_INT : { int i ; for ( i = 0 ; i < CONST_VECTOR_NUNITS ( value ) ; i ++ ) insn = dump_constants_1 ( GET_MODE_INNER ( mode ) , CONST_VECTOR_ELT ( value , i ) , insn ) ; return insn ; } default : gcc_unreachable ( ) ; } } </s>

Output constant VALUE after instruction INSN and return the last instruction emitted . MODE is the mode of the constant .


<s> void emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const override { } </s>


<s>
const
char
*
mcore_output_move
(
rtx
insn
ATTRIBUTE_UNUSED
,
rtx
operands
[
]
,
machine_mode
mode
ATTRIBUTE_UNUSED
)
{
rtx
dst
=
operands
[
0
]
;
rtx
src
=
operands
[
1
]
;
if
(
GET_CODE
(
dst
)
==
REG
)
{
if
(
GET_CODE
(
src
)
==
REG
)
{
if
(
REGNO
(
src
)
==
CC_REG
)
return
"mvc\t%0"
;
else
return
"mov\t%0,%1"
;
}
else
if
(
GET_CODE
(
src
)
==
MEM
)
{
if
(
GET_CODE
(
XEXP
(
src
,
0
)
)
==
LABEL_REF
)
return
"lrw\t%0,[%1]"
;
else
switch
(
GET_MODE
(
src
)
)
{
case
E_SImode
:
return
"ldw\t%0,%1"
;
case
E_HImode
:
return
"ld.h\t%0,%1"
;
case
E_QImode
:
return
"ld.b\t%0,%1"
;
default
:
gcc_unreachable
(
)
;
}
}
else
if
(
GET_CODE
(
src
)
==
CONST_INT
)
{
HOST_WIDE_INT
x
,
y
;
if
(
CONST_OK_FOR_I
(
INTVAL
(
src
)
)
)
return
"movi\t%0,%1"
;
else
if
(
CONST_OK_FOR_M
(
INTVAL
(
src
)
)
)
return
"bgeni\t%0,%P1\t// %1 %x1"
;
else
if
(
CONST_OK_FOR_N
(
INTVAL
(
src
)
)
)
return
"bmaski\t%0,%N1\t// %1 %x1"
;
else
if
(
try_constant_tricks
(
INTVAL
(
src
)
,
&
x
,
&
y
)
)
return
output_inline_const
(
SImode
,
operands
)
;
else
return
"lrw\t%0,%x1\t// %1"
;
}
else
return
"lrw\t%0, %1"
;
}
else
if
(
GET_CODE
(
dst
)
==
MEM
)
switch
(
GET_MODE
(
dst
)
)
{
case
E_SImode
:
return
"stw\t%1,%0"
;
case
E_HImode
:
return
"st.h\t%1,%0"
;
case
E_QImode
:
return
"st.b\t%1,%0"
;
default
:
gcc_unreachable
(
)
;
}
gcc_unreachable
(
)
;
}
</s>


<s> static int access_check ( const char * name , int mode ) { if ( mode == X_OK ) { struct stat st ; if ( stat ( name , & st ) < 0 || S_ISDIR ( st . st_mode ) ) return - 1 ; } return access ( name , mode ) ; } </s>

Check whether NAME can be accessed in MODE . This is like access , except that it never considers directories to be executable .


<s> static void pa_hpux_file_end ( void ) { unsigned int i ; extern_symbol * p ; if ( ! NO_DEFERRED_PROFILE_COUNTERS ) output_deferred_profile_counters ( ) ; output_deferred_plabels ( ) ; for ( i = 0 ; VEC_iterate ( extern_symbol , extern_symbols , i , p ) ; i ++ ) { tree decl = p -> decl ; if ( ! TREE_ASM_WRITTEN ( decl ) && SYMBOL_REF_REFERENCED_P ( XEXP ( DECL_RTL ( decl ) , 0 ) ) ) ASM_OUTPUT_EXTERNAL_REAL ( asm_out_file , decl , p -> name ) ; } VEC_free ( extern_symbol , gc , extern_symbols ) ; } </s>

Output text required at the end of an assembler file . This includes deferred plabels and .import directives for all external symbols that were actually referenced .


<s> virtual void print ( raw_ostream & OS ) const { llvm_unreachable ( "unimplemented!" ) ; } </s>

print - Print a debug representation of the operand to the given stream .


<s> static void c6x_reorg ( void ) { basic_block bb ; bool do_selsched = ( c6x_flag_schedule_insns2 && flag_selective_scheduling2 && ! maybe_skip_selective_scheduling ( ) ) ; compute_bb_for_insn ( ) ; df_clear_flags ( DF_LR_RUN_DCE ) ; df_note_add_problem ( ) ; if ( optimize == 0 ) split_all_insns ( ) ; df_analyze ( ) ; if ( c6x_flag_schedule_insns2 ) { int sz = get_max_uid ( ) * 3 / 2 + 1 ; insn_info . create ( sz ) ; } sched_no_dce = true ; c6x_hwloops ( ) ; if ( c6x_flag_schedule_insns2 ) { split_delayed_insns ( ) ; timevar_push ( TV_SCHED2 ) ; if ( do_selsched ) run_selective_scheduling ( ) ; else schedule_ebbs ( ) ; conditionalize_after_sched ( ) ; timevar_pop ( TV_SCHED2 ) ; free_delay_pairs ( ) ; } sched_no_dce = false ; rtx_code_label * * call_labels = XCNEWVEC ( rtx_code_label * , get_max_uid ( ) + 1 ) ; reorg_split_calls ( call_labels ) ; if ( c6x_flag_schedule_insns2 ) { FOR_EACH_BB_FN ( bb , cfun ) if ( ( bb -> flags & BB_DISABLE_SCHEDULE ) == 0 ) assign_reservations ( BB_HEAD ( bb ) , BB_END ( bb ) ) ; } if ( c6x_flag_var_tracking ) { timevar_push ( TV_VAR_TRACKING ) ; variable_tracking_main ( ) ; timevar_pop ( TV_VAR_TRACKING ) ; } reorg_emit_nops ( call_labels ) ; if ( c6x_flag_schedule_insns2 ) { free_delay_pairs ( ) ; c6x_gen_bundles ( ) ; } df_finish_pass ( false ) ; } </s>

Implement the TARGET_MACHINE_DEPENDENT_REORG pass . We split call insns here into a sequence that loads the return register and performs the call , and emit the return label . If scheduling after reload is requested , it happens here .


<s> void AArch64ConditionOptimizer :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool AArch64FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> int ix86_min_insn_size ( rtx_insn * insn ) { int l = 0 , len ; if ( ! INSN_P ( insn ) || ! active_insn_p ( insn ) ) return 0 ; if ( GET_CODE ( PATTERN ( insn ) ) == UNSPEC_VOLATILE && XINT ( PATTERN ( insn ) , 1 ) == UNSPECV_ALIGN ) return 0 ; if ( CALL_P ( insn ) && symbolic_reference_mentioned_p ( PATTERN ( insn ) ) && ! SIBLING_CALL_P ( insn ) ) return 5 ; len = get_attr_length ( insn ) ; if ( len <= 1 ) return 1 ; if ( ! JUMP_P ( insn ) ) { enum attr_type type = get_attr_type ( insn ) ; switch ( type ) { case TYPE_MULTI : if ( GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT || asm_noperands ( PATTERN ( insn ) ) >= 0 ) return 0 ; break ; case TYPE_OTHER : case TYPE_FCMP : break ; default : return len ; } l = get_attr_length_address ( insn ) ; if ( l < 4 && symbolic_reference_mentioned_p ( PATTERN ( insn ) ) ) l = 4 ; } if ( l ) return 1 + l ; else return 2 ; } </s>

We do n't have exact information about the insn sizes , but we may assume quite safely that we are informed about all 1 byte insns and memory address sizes . This is enough to eliminate unnecessary padding in 99 % of cases .


<s> static void ix86_test_loading_dump_fragment_1 ( ) { rtl_dump_test t ( SELFTEST_LOCATION , locate_file ( "x86_64/copy-hard-reg-into-frame.rtl" ) ) ; rtx_insn * insn = get_insn_by_uid ( 1 ) ; tree mem_expr ; { rtx pat = PATTERN ( insn ) ; ASSERT_EQ ( SET , GET_CODE ( pat ) ) ; { rtx dest = SET_DEST ( pat ) ; ASSERT_EQ ( MEM , GET_CODE ( dest ) ) ; ASSERT_TRUE ( RTX_FLAG ( dest , call ) ) ; ASSERT_EQ ( SImode , GET_MODE ( dest ) ) ; { rtx addr = XEXP ( dest , 0 ) ; ASSERT_EQ ( PLUS , GET_CODE ( addr ) ) ; ASSERT_EQ ( DImode , GET_MODE ( addr ) ) ; { rtx lhs = XEXP ( addr , 0 ) ; ASSERT_RTX_PTR_EQ ( frame_pointer_rtx , lhs ) ; } { rtx rhs = XEXP ( addr , 1 ) ; ASSERT_EQ ( CONST_INT , GET_CODE ( rhs ) ) ; ASSERT_EQ ( - 4 , INTVAL ( rhs ) ) ; } } ASSERT_EQ ( 1 , MEM_ALIAS_SET ( dest ) ) ; mem_expr = MEM_EXPR ( dest ) ; ASSERT_NE ( mem_expr , NULL ) ; ASSERT_EQ ( VAR_DECL , TREE_CODE ( mem_expr ) ) ; ASSERT_EQ ( integer_type_node , TREE_TYPE ( mem_expr ) ) ; ASSERT_EQ ( IDENTIFIER_NODE , TREE_CODE ( DECL_NAME ( mem_expr ) ) ) ; ASSERT_STREQ ( "i" , IDENTIFIER_POINTER ( DECL_NAME ( mem_expr ) ) ) ; ASSERT_TRUE ( MEM_OFFSET_KNOWN_P ( dest ) ) ; ASSERT_EQ ( 0 , MEM_OFFSET ( dest ) ) ; ASSERT_EQ ( 4 , MEM_SIZE ( dest ) ) ; ASSERT_EQ ( 32 , MEM_ALIGN ( dest ) ) ; } { rtx src = SET_SRC ( pat ) ; ASSERT_EQ ( REG , GET_CODE ( src ) ) ; ASSERT_EQ ( SImode , GET_MODE ( src ) ) ; ASSERT_EQ ( 5 , REGNO ( src ) ) ; tree reg_expr = REG_EXPR ( src ) ; ASSERT_EQ ( reg_expr , mem_expr ) ; } } } </s>

Verify loading an RTL dump ; specifically a dump of copying a param on x86_64 from a hard reg into the frame . This test is target-specific since the dump contains target-specific hard reg names .


<s> int s390_mem_constraint ( const char * str , rtx op ) { char c = str [ 0 ] ; switch ( c ) { case 'A' : if ( ! MEM_P ( op ) || MEM_VOLATILE_P ( op ) ) return 0 ; if ( ( reload_completed || reload_in_progress ) ? ! offsettable_memref_p ( op ) : ! offsettable_nonstrict_memref_p ( op ) ) return 0 ; return s390_check_qrst_address ( str [ 1 ] , XEXP ( op , 0 ) , true ) ; case 'B' : if ( ! MEM_P ( op ) ) return 0 ; return s390_check_qrst_address ( str [ 1 ] , XEXP ( op , 0 ) , false ) ; case 'Q' : case 'R' : case 'S' : case 'T' : if ( GET_CODE ( op ) != MEM ) return 0 ; return s390_check_qrst_address ( c , XEXP ( op , 0 ) , true ) ; case 'U' : return ( s390_check_qrst_address ( 'Q' , op , true ) || s390_check_qrst_address ( 'R' , op , true ) ) ; case 'W' : return ( s390_check_qrst_address ( 'S' , op , true ) || s390_check_qrst_address ( 'T' , op , true ) ) ; case 'Y' : if ( ! s390_decompose_shift_count ( op , NULL , NULL ) ) return 0 ; break ; case 'Z' : return s390_check_qrst_address ( str [ 1 ] , op , true ) ; default : return 0 ; } return 1 ; } </s>

Evaluates constraint strings described by the regular expression ( [ A|B|Z ] ( Q|R|S|T ) ) |U|W|Y and returns 1 if OP is a valid operand for the constraint given in STR , or 0 else .


<s> static const char * get_some_local_dynamic_name ( void ) { rtx insn ; if ( cfun -> machine -> some_ld_name ) return cfun -> machine -> some_ld_name ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) && for_each_rtx ( & PATTERN ( insn ) , get_some_local_dynamic_name_1 , 0 ) ) return cfun -> machine -> some_ld_name ; gcc_unreachable ( ) ; } </s>

Locate some local-dynamic symbol still in use by this function so that we can print its name in local-dynamic base patterns .


<s>
static
int
aarch64_comp_type_attributes
(
const_tree
type1
,
const_tree
type2
)
{
auto
check_attr
=
[
&
]
(
const
char
*
name
)
{
tree
attr1
=
lookup_attribute
(
name
,
TYPE_ATTRIBUTES
(
type1
)
)
;
tree
attr2
=
lookup_attribute
(
name
,
TYPE_ATTRIBUTES
(
type2
)
)
;
if
(
!
attr1
&&
!
attr2
)
return
true
;
return
attr1
&&
attr2
&&
attribute_value_equal
(
attr1
,
attr2
)
;
}
;
if
(
!
check_attr
(
"aarch64_vector_pcs"
)
)
return
0
;
if
(
!
check_attr
(
"Advanced SIMD type"
)
)
return
0
;
return
1
;
}
</s>


<s>
bool
MOSLowerSelect
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"\n\nHandling G_SELECTs in: "
<<
MF
.
getName
(
)
<<
"\n\n"
)
;
moveAwayFromCalls
(
MF
)
;
sinkSelectsToBranchUses
(
MF
)
;
bool
Changed
=
false
;
for
(
auto
I
=
MF
.
rbegin
(
)
,
E
=
MF
.
rend
(
)
;
I
!=
E
;
++
I
)
{
for
(
MachineInstr
&
MBBI
:
mbb_reverse
(
*
I
)
)
{
if
(
MBBI
.
getOpcode
(
)
==
MOS
::
G_SELECT
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Lowering: "
<<
MBBI
)
;
Changed
=
true
;
I
=
lowerSelect
(
MBBI
)
;
break
;
}
}
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

MOS
MOS
"\n\nHandling G_SELECTs in: "
"\n\n"
MOS::G_SELECT
"Lowering: "


<s> rtx rs6000_address_for_fpconvert ( rtx x ) { int strict_p = ( reload_in_progress || reload_completed ) ; rtx addr ; gcc_assert ( MEM_P ( x ) ) ; addr = XEXP ( x , 0 ) ; if ( ! legitimate_indirect_address_p ( addr , strict_p ) && ! legitimate_indexed_address_p ( addr , strict_p ) ) { if ( GET_CODE ( addr ) == PRE_INC || GET_CODE ( addr ) == PRE_DEC ) { rtx reg = XEXP ( addr , 0 ) ; HOST_WIDE_INT size = GET_MODE_SIZE ( GET_MODE ( x ) ) ; rtx size_rtx = GEN_INT ( ( GET_CODE ( addr ) == PRE_DEC ) ? - size : size ) ; gcc_assert ( REG_P ( reg ) ) ; emit_insn ( gen_add3_insn ( reg , reg , size_rtx ) ) ; addr = reg ; } else if ( GET_CODE ( addr ) == PRE_MODIFY ) { rtx reg = XEXP ( addr , 0 ) ; rtx expr = XEXP ( addr , 1 ) ; gcc_assert ( REG_P ( reg ) ) ; gcc_assert ( GET_CODE ( expr ) == PLUS ) ; emit_insn ( gen_add3_insn ( reg , XEXP ( expr , 0 ) , XEXP ( expr , 1 ) ) ) ; addr = reg ; } x = replace_equiv_address ( x , copy_addr_to_reg ( addr ) ) ; } return x ; } </s>

Given a memory reference , if it is not a reg or reg+reg addressing , convert to such a form to deal with memory reference instructions like STFIWX that only take reg+reg addressing .


"static initialization of variable %q+D in %<.shared%>"

Encode the PTX data area that DECL ( which might not actually be a _DECL ) should reside in .


<s> bool HexagonInstrInfo :: areMemAccessesTriviallyDisjoint ( MachineInstr & MIa , MachineInstr & MIb , AliasAnalysis * AA ) const { if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) || MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; if ( MIa . mayLoad ( ) && ! isMemOp ( MIa ) && MIb . mayLoad ( ) && ! isMemOp ( MIb ) ) return true ; unsigned BasePosA , OffsetPosA ; if ( ! getBaseAndOffsetPosition ( MIa , BasePosA , OffsetPosA ) ) return false ; const MachineOperand & BaseA = MIa . getOperand ( BasePosA ) ; unsigned BaseRegA = BaseA . getReg ( ) ; unsigned BaseSubA = BaseA . getSubReg ( ) ; unsigned BasePosB , OffsetPosB ; if ( ! getBaseAndOffsetPosition ( MIb , BasePosB , OffsetPosB ) ) return false ; const MachineOperand & BaseB = MIb . getOperand ( BasePosB ) ; unsigned BaseRegB = BaseB . getReg ( ) ; unsigned BaseSubB = BaseB . getSubReg ( ) ; if ( BaseRegA != BaseRegB || BaseSubA != BaseSubB ) return false ; unsigned SizeA = ( 1u << ( getMemAccessSize ( MIa ) - 1 ) ) ; unsigned SizeB = ( 1u << ( getMemAccessSize ( MIb ) - 1 ) ) ; const MachineOperand & OffA = MIa . getOperand ( OffsetPosA ) ; const MachineOperand & OffB = MIb . getOperand ( OffsetPosB ) ; if ( ! MIa . getOperand ( OffsetPosA ) . isImm ( ) || ! MIb . getOperand ( OffsetPosB ) . isImm ( ) ) return false ; int OffsetA = isPostIncrement ( MIa ) ? 0 : OffA . getImm ( ) ; int OffsetB = isPostIncrement ( MIb ) ? 0 : OffB . getImm ( ) ; if ( OffsetA > OffsetB ) { uint64_t OffDiff = ( uint64_t ) ( ( int64_t ) OffsetA - ( int64_t ) OffsetB ) ; return SizeB <= OffDiff ; } if ( OffsetA < OffsetB ) { uint64_t OffDiff = ( uint64_t ) ( ( int64_t ) OffsetB - ( int64_t ) OffsetA ) ; return SizeA <= OffDiff ; } return false ; } </s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> bool mips_use_ins_ext_p ( rtx op , HOST_WIDE_INT width , HOST_WIDE_INT bitpos ) { if ( ! ISA_HAS_EXT_INS || ! register_operand ( op , VOIDmode ) || GET_MODE_BITSIZE ( GET_MODE ( op ) ) > BITS_PER_WORD ) return false ; if ( ! IN_RANGE ( width , 1 , GET_MODE_BITSIZE ( GET_MODE ( op ) ) - 1 ) ) return false ; if ( bitpos < 0 || bitpos + width > GET_MODE_BITSIZE ( GET_MODE ( op ) ) ) return false ; return true ; } </s>

Return true if ( zero_extract OP SIZE POSITION ) can be used as the source of an `` ext '' instruction or the destination of an `` ins '' instruction . OP must be a register operand and the following conditions must hold : 0 < = POSITION < GET_MODE_BITSIZE ( GET_MODE ( op ) ) 0 < SIZE < = GET_MODE_BITSIZE ( GET_MODE ( op ) ) 0 < POSITION + SIZE < = GET_MODE_BITSIZE ( GET_MODE ( op ) ) Also reject lengths equal to a word as they are better handled by the move patterns .


<s> BitVector VERegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const Register ReservedRegs [ ] = { VE :: SX8 , VE :: SX9 , VE :: SX10 , VE :: SX11 , VE :: SX12 , VE :: SX13 , VE :: SX14 , VE :: SX15 , VE :: SX16 , VE :: SX17 , } ; for ( auto R : ReservedRegs ) for ( MCRegAliasIterator ItAlias ( R , this , true ) ; ItAlias . isValid ( ) ; ++ ItAlias ) Reserved . set ( * ItAlias ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> SDValue AArch64TargetLowering :: getSqrtEstimate ( SDValue Operand , SelectionDAG & DAG , int Enabled , int & ExtraSteps , bool & UseOneConst , bool Reciprocal ) const { if ( Enabled == ReciprocalEstimate :: Enabled || ( Enabled == ReciprocalEstimate :: Unspecified && Subtarget -> useRSqrt ( ) ) ) if ( SDValue Estimate = getEstimate ( Subtarget , AArch64ISD :: FRSQRTE , Operand , DAG , ExtraSteps ) ) { SDLoc DL ( Operand ) ; EVT VT = Operand . getValueType ( ) ; SDNodeFlags Flags ; Flags . setUnsafeAlgebra ( true ) ; for ( int i = ExtraSteps ; i > 0 ; -- i ) { SDValue Step = DAG . getNode ( ISD :: FMUL , DL , VT , Estimate , Estimate , Flags ) ; Step = DAG . getNode ( AArch64ISD :: FRSQRTS , DL , VT , Operand , Step , Flags ) ; Estimate = DAG . getNode ( ISD :: FMUL , DL , VT , Estimate , Step , Flags ) ; } if ( ! Reciprocal ) { EVT CCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue FPZero = DAG . getConstantFP ( 0.0 , DL , VT ) ; SDValue Eq = DAG . getSetCC ( DL , CCVT , Operand , FPZero , ISD :: SETEQ ) ; Estimate = DAG . getNode ( ISD :: FMUL , DL , VT , Operand , Estimate , Flags ) ; Estimate = DAG . getNode ( VT . isVector ( ) ? ISD :: VSELECT : ISD :: SELECT , DL , VT , Eq , Operand , Estimate ) ; } ExtraSteps = 0 ; return Estimate ; } return SDValue ( ) ; } </s>

Hooks for building estimates in place of slower divisions and square roots .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"LM32 Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
static
rtx
frv_int_to_acc
(
enum
insn_code
icode
,
int
opnum
,
rtx
opval
)
{
rtx
reg
;
int
i
;
for
(
i
=
0
;
i
<=
ACC_MASK
;
i
++
)
if
(
(
i
&
ACC_MASK
)
==
i
)
global_regs
[
i
+
ACC_FIRST
]
=
global_regs
[
i
+
ACCG_FIRST
]
=
1
;
if
(
GET_CODE
(
opval
)
!=
CONST_INT
)
{
error
(
"accumulator is not a constant integer"
)
;
return
NULL_RTX
;
}
if
(
(
INTVAL
(
opval
)
&
~
ACC_MASK
)
!=
0
)
{
error
(
"accumulator number is out of bounds"
)
;
return
NULL_RTX
;
}
reg
=
gen_rtx_REG
(
insn_data
[
icode
]
.
operand
[
opnum
]
.
mode
,
ACC_FIRST
+
INTVAL
(
opval
)
)
;
if
(
!
(
*
insn_data
[
icode
]
.
operand
[
opnum
]
.
predicate
)
(
reg
,
VOIDmode
)
)
REGNO
(
reg
)
=
ACCG_FIRST
+
INTVAL
(
opval
)
;
if
(
!
(
*
insn_data
[
icode
]
.
operand
[
opnum
]
.
predicate
)
(
reg
,
VOIDmode
)
)
{
error
(
"inappropriate accumulator for %qs"
,
insn_data
[
icode
]
.
name
)
;
return
NULL_RTX
;
}
return
reg
;
}
</s>

Convert an integer constant to an accumulator register . ICODE is the code of the target instruction , OPNUM is the number of the accumulator operand and OPVAL is the constant integer . Try both ACC and ACCG registers ; only report an error if neither fit the instruction .


<s> void X86FrameLowering :: orderFrameObjects ( const MachineFunction & MF , SmallVectorImpl < int > & ObjectsToAllocate ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ObjectsToAllocate . empty ( ) ) return ; std :: vector < X86FrameSortingObject > SortingObjects ( MFI . getObjectIndexEnd ( ) ) ; for ( auto & Obj : ObjectsToAllocate ) { SortingObjects [ Obj ] . IsValid = true ; SortingObjects [ Obj ] . ObjectIndex = Obj ; SortingObjects [ Obj ] . ObjectAlignment = MFI . getObjectAlignment ( Obj ) ; int ObjectSize = MFI . getObjectSize ( Obj ) ; if ( ObjectSize == 0 ) SortingObjects [ Obj ] . ObjectSize = 4 ; else SortingObjects [ Obj ] . ObjectSize = ObjectSize ; } for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( MI . isDebugInstr ( ) ) continue ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isFI ( ) ) continue ; int Index = MO . getIndex ( ) ; if ( Index >= 0 && Index < MFI . getObjectIndexEnd ( ) && SortingObjects [ Index ] . IsValid ) SortingObjects [ Index ] . ObjectNumUses ++ ; } } } llvm :: stable_sort ( SortingObjects , X86FrameSortingComparator ( ) ) ; int i = 0 ; for ( auto & Obj : SortingObjects ) { if ( ! Obj . IsValid ) break ; ObjectsToAllocate [ i ++ ] = Obj . ObjectIndex ; } if ( ! TRI -> needsStackRealignment ( MF ) && hasFP ( MF ) ) std :: reverse ( ObjectsToAllocate . begin ( ) , ObjectsToAllocate . end ( ) ) ; } </s>


<s>
const
char
*
nds32_output_float_load
(
rtx
*
operands
)
{
char
buff
[
100
]
;
const
char
*
pattern
;
rtx
addr
,
addr_op0
,
addr_op1
;
int
dp
=
GET_MODE_SIZE
(
GET_MODE
(
operands
[
0
]
)
)
==
8
;
addr
=
XEXP
(
operands
[
1
]
,
0
)
;
switch
(
GET_CODE
(
addr
)
)
{
case
REG
:
pattern
=
"fl%ci\t%%0, %%1"
;
break
;
case
PLUS
:
addr_op0
=
XEXP
(
addr
,
0
)
;
addr_op1
=
XEXP
(
addr
,
1
)
;
if
(
REG_P
(
addr_op0
)
&&
REG_P
(
addr_op1
)
)
pattern
=
"fl%c\t%%0, %%1"
;
else
if
(
REG_P
(
addr_op0
)
&&
CONST_INT_P
(
addr_op1
)
)
pattern
=
"fl%ci\t%%0, %%1"
;
else
if
(
GET_CODE
(
addr_op0
)
==
MULT
&&
REG_P
(
addr_op1
)
&&
REG_P
(
XEXP
(
addr_op0
,
0
)
)
&&
CONST_INT_P
(
XEXP
(
addr_op0
,
1
)
)
)
pattern
=
"fl%c\t%%0, %%1"
;
else
gcc_unreachable
(
)
;
break
;
case
POST_MODIFY
:
addr_op0
=
XEXP
(
addr
,
0
)
;
addr_op1
=
XEXP
(
addr
,
1
)
;
if
(
REG_P
(
addr_op0
)
&&
GET_CODE
(
addr_op1
)
==
PLUS
&&
REG_P
(
XEXP
(
addr_op1
,
1
)
)
)
pattern
=
"fl%c.bi\t%%0, %%1"
;
else
if
(
REG_P
(
addr_op0
)
&&
GET_CODE
(
addr_op1
)
==
PLUS
&&
CONST_INT_P
(
XEXP
(
addr_op1
,
1
)
)
)
pattern
=
"fl%ci.bi\t%%0, %%1"
;
else
gcc_unreachable
(
)
;
break
;
case
POST_INC
:
if
(
REG_P
(
XEXP
(
addr
,
0
)
)
)
{
if
(
dp
)
pattern
=
"fl%ci.bi\t%%0, %%1, 8"
;
else
pattern
=
"fl%ci.bi\t%%0, %%1, 4"
;
}
else
gcc_unreachable
(
)
;
break
;
case
POST_DEC
:
if
(
REG_P
(
XEXP
(
addr
,
0
)
)
)
{
if
(
dp
)
pattern
=
"fl%ci.bi\t%%0, %%1, -8"
;
else
pattern
=
"fl%ci.bi\t%%0, %%1, -4"
;
}
else
gcc_unreachable
(
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
sprintf
(
buff
,
pattern
,
dp
'd'
:
's'
)
;
output_asm_insn
(
buff
,
operands
)
;
return
""
;
}
</s>


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , RM , CM , OL ) , TargetABI ( computeTargetABI ( Triple ( TT ) , CPU , Options ) ) , TLOF ( createTLOF ( Triple ( getTargetTriple ( ) ) ) ) , Subtarget ( TT , CPU , FS , * this , isLittle ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = Subtarget . isTargetHardFloat ( ) ? FloatABI :: Hard : FloatABI :: Soft ; } </s>


<s> const TargetSubtargetInfo * Z80TargetMachine :: getSubtargetImpl ( const Function & function ) const { return & DefaultSubtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
void
HexagonInstPrinter
::
printInst
(
MCInst
const
*
MI
,
raw_ostream
&
OS
,
StringRef
Annot
,
MCSubtargetInfo
const
&
STI
)
{
assert
(
HexagonMCInstrInfo
::
isBundle
(
*
MI
)
)
;
assert
(
HexagonMCInstrInfo
::
bundleSize
(
*
MI
)
<=
HEXAGON_PACKET_SIZE
)
;
HasExtender
=
false
;
for
(
auto
const
&
I
:
HexagonMCInstrInfo
::
bundleInstructions
(
*
MI
)
)
{
MCInst
const
&
MCI
=
*
I
.
getInst
(
)
;
if
(
HexagonMCInstrInfo
::
isDuplex
(
MII
,
MCI
)
)
{
printInstruction
(
MCI
.
getOperand
(
1
)
.
getInst
(
)
,
OS
)
;
OS
<<
'\v'
;
HasExtender
=
false
;
printInstruction
(
MCI
.
getOperand
(
0
)
.
getInst
(
)
,
OS
)
;
}
else
printInstruction
(
&
MCI
,
OS
)
;
setExtender
(
MCI
)
;
OS
<<
"\n"
;
}
auto
Separator
=
""
;
if
(
HexagonMCInstrInfo
::
isInnerLoop
(
*
MI
)
)
{
OS
<<
Separator
;
Separator
=
" "
;
MCInst
ME
;
ME
.
setOpcode
(
Hexagon
::
ENDLOOP0
)
;
printInstruction
(
&
ME
,
OS
)
;
}
if
(
HexagonMCInstrInfo
::
isOuterLoop
(
*
MI
)
)
{
OS
<<
Separator
;
Separator
=
" "
;
MCInst
ME
;
ME
.
setOpcode
(
Hexagon
::
ENDLOOP1
)
;
printInstruction
(
&
ME
,
OS
)
;
}
}
</s>

Print the specified MCInst to the specified raw_ostream .

Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
1
0
"\n"
""
Hexagon
" "
Hexagon::ENDLOOP0
Hexagon
" "
Hexagon::ENDLOOP1


<s> void s390_expand_vec_compare_cc ( rtx target , enum rtx_code code , rtx cmp1 , rtx cmp2 , bool all_p ) { machine_mode cc_producer_mode , cc_consumer_mode , scratch_mode ; rtx tmp_reg = gen_reg_rtx ( SImode ) ; bool swap_p = false ; if ( GET_MODE_CLASS ( GET_MODE ( cmp1 ) ) == MODE_VECTOR_INT ) { switch ( code ) { case EQ : case NE : cc_producer_mode = CCVEQmode ; break ; case GE : case LT : code = swap_condition ( code ) ; swap_p = true ; case GT : case LE : cc_producer_mode = CCVIHmode ; break ; case GEU : case LTU : code = swap_condition ( code ) ; swap_p = true ; case GTU : case LEU : cc_producer_mode = CCVIHUmode ; break ; default : gcc_unreachable ( ) ; } scratch_mode = GET_MODE ( cmp1 ) ; if ( code == NE || code == LE || code == LEU ) all_p = ! all_p ; cc_consumer_mode = all_p ? CCVIALLmode : CCVIANYmode ; } else if ( GET_MODE_CLASS ( GET_MODE ( cmp1 ) ) == MODE_VECTOR_FLOAT ) { bool inv_p = false ; switch ( code ) { case EQ : cc_producer_mode = CCVEQmode ; break ; case NE : cc_producer_mode = CCVEQmode ; inv_p = true ; break ; case GT : cc_producer_mode = CCVFHmode ; break ; case GE : cc_producer_mode = CCVFHEmode ; break ; case UNLE : cc_producer_mode = CCVFHmode ; inv_p = true ; break ; case UNLT : cc_producer_mode = CCVFHEmode ; inv_p = true ; break ; case LT : cc_producer_mode = CCVFHmode ; code = GT ; swap_p = true ; break ; case LE : cc_producer_mode = CCVFHEmode ; code = GE ; swap_p = true ; break ; default : gcc_unreachable ( ) ; } scratch_mode = related_int_vector_mode ( GET_MODE ( cmp1 ) ) . require ( ) ; if ( inv_p ) all_p = ! all_p ; cc_consumer_mode = all_p ? CCVFALLmode : CCVFANYmode ; } else gcc_unreachable ( ) ; if ( swap_p ) { rtx tmp = cmp2 ; cmp2 = cmp1 ; cmp1 = tmp ; } emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , gen_rtx_SET ( gen_rtx_REG ( cc_producer_mode , CC_REGNUM ) , gen_rtx_COMPARE ( cc_producer_mode , cmp1 , cmp2 ) ) , gen_rtx_CLOBBER ( VOIDmode , gen_rtx_SCRATCH ( scratch_mode ) ) ) ) ) ; emit_move_insn ( target , const0_rtx ) ; emit_move_insn ( tmp_reg , const1_rtx ) ; emit_move_insn ( target , gen_rtx_IF_THEN_ELSE ( SImode , gen_rtx_fmt_ee ( code , VOIDmode , gen_rtx_REG ( cc_consumer_mode , CC_REGNUM ) , const0_rtx ) , tmp_reg , target ) ) ; } </s>

Expand the comparison CODE of CMP1 and CMP2 and copy 1 or 0 into TARGET if either all ( ALL_P is true ) or any ( ALL_P is false ) of the elements in CMP1 and CMP2 fulfill the comparison .


"%<__delay_cycles%> only takes constant arguments"

"%<__delay_cycles%> only takes non-negative cycle counts"

"%<__delay_cycles%> is limited to 32-bit loop counts"

Emit a sequence of one or more delay_cycles_X insns , in order to generate code that delays exactly ARG cycles .


<s> static bool pdp11_rtx_costs ( rtx x , int code , int outer_code ATTRIBUTE_UNUSED , int * total ) { switch ( code ) { case CONST_INT : if ( INTVAL ( x ) == 0 || INTVAL ( x ) == - 1 || INTVAL ( x ) == 1 ) { * total = 0 ; return true ; } case CONST : case LABEL_REF : case SYMBOL_REF : * total = 2 ; return true ; case CONST_DOUBLE : * total = 4 ; return true ; case MULT : if ( optimize_size ) * total = COSTS_N_INSNS ( 2 ) ; else * total = COSTS_N_INSNS ( 11 ) ; return false ; case DIV : if ( optimize_size ) * total = COSTS_N_INSNS ( 2 ) ; else * total = COSTS_N_INSNS ( 25 ) ; return false ; case MOD : if ( optimize_size ) * total = COSTS_N_INSNS ( 2 ) ; else * total = COSTS_N_INSNS ( 26 ) ; return false ; case ABS : * total = COSTS_N_INSNS ( 3 ) ; return false ; case ZERO_EXTEND : * total = COSTS_N_INSNS ( 1 ) ; return false ; case SIGN_EXTEND : if ( GET_MODE ( x ) == HImode ) * total = COSTS_N_INSNS ( 1 ) ; else if ( GET_MODE ( x ) == SImode ) * total = COSTS_N_INSNS ( 6 ) ; else * total = COSTS_N_INSNS ( 2 ) ; return false ; case ASHIFT : case LSHIFTRT : case ASHIFTRT : if ( optimize_size ) * total = COSTS_N_INSNS ( 1 ) ; else if ( GET_MODE ( x ) == QImode ) { if ( GET_CODE ( XEXP ( x , 1 ) ) != CONST_INT ) * total = COSTS_N_INSNS ( 8 ) ; else * total = COSTS_N_INSNS ( INTVAL ( XEXP ( x , 1 ) ) ) ; } else if ( GET_MODE ( x ) == HImode ) { if ( GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) { if ( abs ( INTVAL ( XEXP ( x , 1 ) ) ) == 1 ) * total = COSTS_N_INSNS ( 1 ) ; else * total = COSTS_N_INSNS ( 2.5 + 0.5 * INTVAL ( XEXP ( x , 1 ) ) ) ; } else * total = COSTS_N_INSNS ( 10 ) ; } else if ( GET_MODE ( x ) == SImode ) { if ( GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) * total = COSTS_N_INSNS ( 2.5 + 0.5 * INTVAL ( XEXP ( x , 1 ) ) ) ; else * total = COSTS_N_INSNS ( 18 ) ; } return false ; default : return false ; } } </s>

This tries to approximate what pdp11_insn_cost would do , but without visibility into the actual instruction being generated it 's inevitably a rough approximation .


<s> bool AMDGPUAsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s>
bool
F2003fInstrInfo
::
reverseBranchCondition
(
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
assert
(
!
Cond
.
empty
(
)
&&
"Invalid 2003f branch condition!"
)
;
F2003fCC
::
CondCode
CC
=
static_cast
<
F2003fCC
::
CondCode
>
(
Cond
.
back
(
)
.
getImm
(
)
)
;
Cond
.
back
(
)
=
MachineOperand
::
CreateImm
(
OppositeF2003fCC
(
CC
)
)
;
return
false
;
}
</s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> bool X86TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , bool * Fast ) const { if ( Fast ) * Fast = Subtarget -> isUnalignedMemAccessFast ( ) ; return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> bool X86TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( VT . getSizeInBits ( ) == 64 ) return false ; return ( VT . getVectorNumElements ( ) == 2 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isMOVLMask ( M , VT ) || isSHUFPMask ( M , VT ) || isPSHUFDMask ( M , VT ) || isPSHUFHWMask ( M , VT ) || isPSHUFLWMask ( M , VT ) || isPALIGNRMask ( M , VT , Subtarget -> hasSSSE3 ( ) ) || isUNPCKLMask ( M , VT ) || isUNPCKHMask ( M , VT ) || isUNPCKL_v_undef_Mask ( M , VT ) || isUNPCKH_v_undef_Mask ( M , VT ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> enum direction ia64_hpux_function_arg_padding ( machine_mode mode , const_tree type ) { if ( type && AGGREGATE_TYPE_P ( type ) && int_size_in_bytes ( type ) < UNITS_PER_WORD ) return upward ; return DEFAULT_FUNCTION_ARG_PADDING ( mode , type ) ; } </s>

For the HP-UX IA64 aggregate parameters are passed stored in the most significant bits of the stack slot .


<s> const AArch64Subtarget * AArch64TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < AArch64Subtarget > ( TargetTriple , CPU , FS , * this , isLittle ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; AArch64GISelActualAccessor * GISel = new AArch64GISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new AArch64CallLowering ( * I -> getTargetLowering ( ) ) ) ; GISel -> Legalizer . reset ( new AArch64LegalizerInfo ( ) ) ; auto * RBI = new AArch64RegisterBankInfo ( * I -> getRegisterInfo ( ) ) ; GISel -> InstSelector . reset ( new AArch64InstructionSelector ( * this , * I , * RBI ) ) ; GISel -> RegBankInfo . reset ( RBI ) ; I -> setGISelAccessor ( * GISel ) ; } return I . get ( ) ; } </s>


"instruction requires a WASM feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> bool convertSetCCLogicToBitwiseLogic ( EVT VT ) const override { return VT . isScalarInteger ( ) ; } </s>

Use bitwise logic to make pairs of compares more efficient .


<s> static bool mips_scalar_mode_supported_p ( machine_mode mode ) { if ( ALL_FIXED_POINT_MODE_P ( mode ) && GET_MODE_PRECISION ( mode ) <= 2 * BITS_PER_WORD ) return true ; return default_scalar_mode_supported_p ( mode ) ; } </s>


"MMIX Internal: %s is not a shiftable int"

Print operator suitable for doing something with a shiftable wyde . The type of operator is passed as an asm output modifier .


<s>
static
rtx
alpha_expand_builtin
(
tree
exp
,
rtx
target
,
rtx
subtarget
ATTRIBUTE_UNUSED
,
machine_mode
mode
ATTRIBUTE_UNUSED
,
int
ignore
ATTRIBUTE_UNUSED
)
{
tree
fndecl
=
TREE_OPERAND
(
CALL_EXPR_FN
(
exp
)
,
0
)
;
unsigned
int
fcode
=
DECL_MD_FUNCTION_CODE
(
fndecl
)
;
tree
arg
;
call_expr_arg_iterator
iter
;
enum
insn_code
icode
;
rtx
op
[
MAX_ARGS
]
,
pat
;
int
arity
;
bool
nonvoid
;
if
(
fcode
>=
ALPHA_BUILTIN_max
)
internal_error
(
"bad builtin fcode"
)
;
icode
=
code_for_builtin
[
fcode
]
;
if
(
icode
==
0
)
internal_error
(
"bad builtin fcode"
)
;
nonvoid
=
TREE_TYPE
(
TREE_TYPE
(
fndecl
)
)
!=
void_type_node
;
arity
=
0
;
FOR_EACH_CALL_EXPR_ARG
(
arg
,
iter
,
exp
)
{
const
struct
insn_operand_data
*
insn_op
;
if
(
arg
==
error_mark_node
)
return
NULL_RTX
;
if
(
arity
>
MAX_ARGS
)
return
NULL_RTX
;
insn_op
=
&
insn_data
[
icode
]
.
operand
[
arity
+
nonvoid
]
;
op
[
arity
]
=
expand_expr
(
arg
,
NULL_RTX
,
insn_op
->
mode
,
EXPAND_NORMAL
)
;
if
(
!
(
*
insn_op
->
predicate
)
(
op
[
arity
]
,
insn_op
->
mode
)
)
op
[
arity
]
=
copy_to_mode_reg
(
insn_op
->
mode
,
op
[
arity
]
)
;
arity
++
;
}
if
(
nonvoid
)
{
machine_mode
tmode
=
insn_data
[
icode
]
.
operand
[
0
]
.
mode
;
if
(
!
target
||
GET_MODE
(
target
)
!=
tmode
||
!
(
*
insn_data
[
icode
]
.
operand
[
0
]
.
predicate
)
(
target
,
tmode
)
)
target
=
gen_reg_rtx
(
tmode
)
;
}
switch
(
arity
)
{
case
0
:
pat
=
GEN_FCN
(
icode
)
(
target
)
;
break
;
case
1
:
if
(
nonvoid
)
pat
=
GEN_FCN
(
icode
)
(
target
,
op
[
0
]
)
;
else
pat
=
GEN_FCN
(
icode
)
(
op
[
0
]
)
;
break
;
case
2
:
pat
=
GEN_FCN
(
icode
)
(
target
,
op
[
0
]
,
op
[
1
]
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
if
(
!
pat
)
return
NULL_RTX
;
emit_insn
(
pat
)
;
if
(
nonvoid
)
return
target
;
else
return
const0_rtx
;
}
</s>

Expand an expression EXP that calls a built-in function , with result going to TARGET if that 's convenient ( and in mode MODE if that 's convenient ) . SUBTARGET may be used as the target for computing one of EXP 's operands . IGNORE is nonzero if the value is to be ignored .


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { unsigned NumOps = Inst . getNumOperands ( ) ; if ( NumOps == 0 ) return false ; switch ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ NumOps - 1 ] . OperandType ) { case MCOI :: OPERAND_UNKNOWN : case MCOI :: OPERAND_IMMEDIATE : { uint64_t Region = Addr & ~ uint64_t ( 0xfffffff ) ; Target = Region + Inst . getOperand ( NumOps - 1 ) . getImm ( ) ; return true ; } case MCOI :: OPERAND_PCREL : Target = Addr + Inst . getOperand ( NumOps - 1 ) . getImm ( ) ; return true ; default : return false ; } } </s>

Given a branch instruction try to get the address the branch targets .


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const PPCFrameLowering * TFI = getFrameLowering ( MF ) ; markSuperRegs ( Reserved , PPC :: ZERO ) ; markSuperRegs ( Reserved , PPC :: FP ) ; markSuperRegs ( Reserved , PPC :: BP ) ; markSuperRegs ( Reserved , PPC :: CTR ) ; markSuperRegs ( Reserved , PPC :: CTR8 ) ; markSuperRegs ( Reserved , PPC :: R1 ) ; markSuperRegs ( Reserved , PPC :: LR ) ; markSuperRegs ( Reserved , PPC :: LR8 ) ; markSuperRegs ( Reserved , PPC :: RM ) ; markSuperRegs ( Reserved , PPC :: VRSAVE ) ; if ( Subtarget . isSVR4ABI ( ) ) { const PPCFunctionInfo * FuncInfo = MF . getInfo < PPCFunctionInfo > ( ) ; if ( ! TM . isPPC64 ( ) || FuncInfo -> usesTOCBasePtr ( ) || MF . hasInlineAsm ( ) ) markSuperRegs ( Reserved , PPC :: R2 ) ; markSuperRegs ( Reserved , PPC :: R13 ) ; } if ( Subtarget . isAIXABI ( ) ) markSuperRegs ( Reserved , PPC :: R2 ) ; if ( TM . isPPC64 ( ) ) markSuperRegs ( Reserved , PPC :: R13 ) ; if ( TFI -> needsFP ( MF ) ) markSuperRegs ( Reserved , PPC :: R31 ) ; bool IsPositionIndependent = TM . isPositionIndependent ( ) ; if ( hasBasePointer ( MF ) ) { if ( Subtarget . is32BitELFABI ( ) && IsPositionIndependent ) markSuperRegs ( Reserved , PPC :: R29 ) ; else markSuperRegs ( Reserved , PPC :: R30 ) ; } if ( Subtarget . is32BitELFABI ( ) && IsPositionIndependent ) markSuperRegs ( Reserved , PPC :: R30 ) ; if ( ! Subtarget . hasAltivec ( ) ) for ( TargetRegisterClass :: iterator I = PPC :: VRRCRegClass . begin ( ) , IE = PPC :: VRRCRegClass . end ( ) ; I != IE ; ++ I ) markSuperRegs ( Reserved , * I ) ; if ( Subtarget . isAIXABI ( ) && Subtarget . hasAltivec ( ) && ! TM . getAIXExtendedAltivecABI ( ) ) { for ( auto Reg : CSR_Altivec_SaveList ) { if ( Reg == 0 ) break ; markSuperRegs ( Reserved , Reg ) ; for ( MCRegAliasIterator AS ( Reg , this , true ) ; AS . isValid ( ) ; ++ AS ) { Reserved . set ( * AS ) ; } } } assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


"function versions cannot be marked as gnu_inline,"

"virtual function multiversioning not supported"

This function changes the assembler name for functions that are versions . If DECL is a function version and has a `` target '' attribute , it appends the attribute string to its assembler name .