<s>
bool
VLIWResourceModel
::
reserveResources
(
SUnit
*
SU
)
{
bool
startNewCycle
=
false
;
if
(
!
SU
)
{
ResourcesModel
->
clearResources
(
)
;
Packet
.
clear
(
)
;
TotalPackets
++
;
return
false
;
}
if
(
!
isResourceAvailable
(
SU
)
)
{
ResourcesModel
->
clearResources
(
)
;
Packet
.
clear
(
)
;
TotalPackets
++
;
startNewCycle
=
true
;
}
switch
(
SU
->
getInstr
(
)
->
getOpcode
(
)
)
{
default
:
ResourcesModel
->
reserveResources
(
SU
->
getInstr
(
)
)
;
break
;
case
TargetOpcode
::
EXTRACT_SUBREG
:
case
TargetOpcode
::
INSERT_SUBREG
:
case
TargetOpcode
::
SUBREG_TO_REG
:
case
TargetOpcode
::
REG_SEQUENCE
:
case
TargetOpcode
::
IMPLICIT_DEF
:
case
TargetOpcode
::
KILL
:
case
TargetOpcode
::
PROLOG_LABEL
:
case
TargetOpcode
::
EH_LABEL
:
case
TargetOpcode
::
COPY
:
case
TargetOpcode
::
INLINEASM
:
break
;
}
Packet
.
push_back
(
SU
)
;
DEBUG
(
dbgs
(
)
<<
"Packet["
<<
TotalPackets
<<
"]:\n"
)
;
for
(
unsigned
i
=
0
,
e
=
Packet
.
size
(
)
;
i
!=
e
;
++
i
)
{
DEBUG
(
dbgs
(
)
<<
"\t["
<<
i
<<
"] SU("
)
;
DEBUG
(
dbgs
(
)
<<
Packet
[
i
]
->
NodeNum
<<
")\t"
)
;
DEBUG
(
Packet
[
i
]
->
getInstr
(
)
->
dump
(
)
)
;
}
if
(
Packet
.
size
(
)
>=
SchedModel
->
getIssueWidth
(
)
)
{
ResourcesModel
->
clearResources
(
)
;
Packet
.
clear
(
)
;
TotalPackets
++
;
startNewCycle
=
true
;
}
return
startNewCycle
;
}
</s>


<s> bool PPCTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , getTargetMachine ( ) , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_PPC ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s>
bool
WebAssemblyArgumentMove
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
LLVM_DEBUG
(
{
dbgs
(
)
<<
"********** Argument Move **********\n"
<<
"********** Function: "
<<
MF
.
getName
(
)
<<
'\n'
;
}
)
;
bool
Changed
=
false
;
MachineBasicBlock
&
EntryMBB
=
MF
.
front
(
)
;
MachineBasicBlock
::
iterator
InsertPt
=
EntryMBB
.
end
(
)
;
for
(
MachineInstr
&
MI
:
EntryMBB
)
{
if
(
!
WebAssembly
::
isArgument
(
MI
.
getOpcode
(
)
)
)
{
InsertPt
=
MI
;
break
;
}
}
for
(
MachineInstr
&
MI
:
llvm
::
make_range
(
InsertPt
,
EntryMBB
.
end
(
)
)
)
{
if
(
WebAssembly
::
isArgument
(
MI
.
getOpcode
(
)
)
)
{
EntryMBB
.
insert
(
InsertPt
,
MI
.
removeFromParent
(
)
)
;
Changed
=
true
;
}
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

WebAssembly
WebAssembly
"********** Argument Move **********\n"
"********** Function: "
WebAssembly::isArgument
WebAssembly::isArgument


<s> bool SparcDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintID ) { default : return true ; case InlineAsm :: Constraint_i : case InlineAsm :: Constraint_o : case InlineAsm :: Constraint_m : if ( ! SelectADDRrr ( Op , Op0 , Op1 ) ) SelectADDRri ( Op , Op0 , Op1 ) ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> bool M68kCallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < Register > VRegs , FunctionLoweringInfo & FLI , Register SwiftErrorVReg ) const { auto MIB = MIRBuilder . buildInstrNoInsert ( M68k :: RTS ) ; bool Success = true ; MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const M68kTargetLowering & TLI = * getTLI < M68kTargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . getCCAssignFn ( F . getCallingConv ( ) , true , F . isVarArg ( ) ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; if ( ! VRegs . empty ( ) ) { SmallVector < ArgInfo , 8 > SplitArgs ; ArgInfo OrigArg { VRegs , Val -> getType ( ) , 0 } ; setArgFlags ( OrigArg , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , F . getCallingConv ( ) ) ; OutgoingValueAssigner ArgAssigner ( AssignFn ) ; OutgoingArgHandler ArgHandler ( MIRBuilder , MRI , MIB ) ; Success = determineAndHandleAssignments ( ArgHandler , ArgAssigner , SplitArgs , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ; } MIRBuilder . insertInstr ( MIB ) ; return Success ; } </s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


"Frame index should only be used for address operands"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool tilepro_expand_mulsi ( rtx op0 , rtx op1 , rtx op2 ) { if ( CONST_INT_P ( op2 ) ) { HOST_WIDE_INT n = trunc_int_for_mode ( INTVAL ( op2 ) , SImode ) ; return tilepro_expand_const_mulsi ( op0 , op1 , n ) ; } return false ; } </s>


<s> void alpha_split_compare_and_swap ( rtx operands [ ] ) { rtx cond , retval , mem , oldval , newval ; bool is_weak ; enum memmodel mod_s , mod_f ; machine_mode mode ; rtx label1 , label2 , x ; cond = operands [ 0 ] ; retval = operands [ 1 ] ; mem = operands [ 2 ] ; oldval = operands [ 3 ] ; newval = operands [ 4 ] ; is_weak = ( operands [ 5 ] != const0_rtx ) ; mod_s = memmodel_from_int ( INTVAL ( operands [ 6 ] ) ) ; mod_f = memmodel_from_int ( INTVAL ( operands [ 7 ] ) ) ; mode = GET_MODE ( mem ) ; alpha_pre_atomic_barrier ( mod_s ) ; label1 = NULL_RTX ; if ( ! is_weak ) { label1 = gen_rtx_LABEL_REF ( DImode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label1 , 0 ) ) ; } label2 = gen_rtx_LABEL_REF ( DImode , gen_label_rtx ( ) ) ; emit_insn ( gen_load_locked ( mode , retval , mem ) ) ; x = gen_lowpart ( DImode , retval ) ; if ( oldval == const0_rtx ) { emit_move_insn ( cond , const0_rtx ) ; x = gen_rtx_NE ( DImode , x , const0_rtx ) ; } else { x = gen_rtx_EQ ( DImode , x , oldval ) ; emit_insn ( gen_rtx_SET ( cond , x ) ) ; x = gen_rtx_EQ ( DImode , cond , const0_rtx ) ; } emit_unlikely_jump ( x , label2 ) ; emit_move_insn ( cond , newval ) ; emit_insn ( gen_store_conditional ( mode , cond , mem , gen_lowpart ( mode , cond ) ) ) ; if ( ! is_weak ) { x = gen_rtx_EQ ( DImode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label1 ) ; } if ( ! is_mm_relaxed ( mod_f ) ) emit_label ( XEXP ( label2 , 0 ) ) ; alpha_post_atomic_barrier ( mod_s ) ; if ( is_mm_relaxed ( mod_f ) ) emit_label ( XEXP ( label2 , 0 ) ) ; } </s>


<s> void arc_init ( void ) { char * tmp ; arc_text_section = tmp = xmalloc ( strlen ( arc_text_string ) + sizeof ( ARC_SECTION_FORMAT ) + 1 ) ; sprintf ( tmp , ARC_SECTION_FORMAT , arc_text_string ) ; arc_data_section = tmp = xmalloc ( strlen ( arc_data_string ) + sizeof ( ARC_SECTION_FORMAT ) + 1 ) ; sprintf ( tmp , ARC_SECTION_FORMAT , arc_data_string ) ; arc_rodata_section = tmp = xmalloc ( strlen ( arc_rodata_string ) + sizeof ( ARC_SECTION_FORMAT ) + 1 ) ; sprintf ( tmp , ARC_SECTION_FORMAT , arc_rodata_string ) ; arc_init_reg_tables ( ) ; memset ( arc_punct_chars , 0 , sizeof ( arc_punct_chars ) ) ; arc_punct_chars [ '#' ] = 1 ; arc_punct_chars [ '*' ] = 1 ; arc_punct_chars [ '?' ] = 1 ; arc_punct_chars [ '!' ] = 1 ; arc_punct_chars [ '~' ] = 1 ; } </s>

Called by OVERRIDE_OPTIONS to initialize various things .


<s> static bool sh_asm_output_addr_const_extra ( FILE * file , rtx x ) { if ( GET_CODE ( x ) == UNSPEC ) { switch ( XINT ( x , 1 ) ) { case UNSPEC_PIC : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; break ; case UNSPEC_GOT : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fputs ( "@GOT" , file ) ; break ; case UNSPEC_GOTOFF : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fputs ( "@GOTOFF" , file ) ; break ; case UNSPEC_PLT : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fputs ( "@PLT" , file ) ; break ; case UNSPEC_GOTPLT : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fputs ( "@GOTPLT" , file ) ; break ; case UNSPEC_PCREL : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fputs ( "@PCREL" , file ) ; break ; case UNSPEC_DTPOFF : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fputs ( "@DTPOFF" , file ) ; break ; case UNSPEC_GOTTPOFF : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fputs ( "@GOTTPOFF" , file ) ; break ; case UNSPEC_TPOFF : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fputs ( "@TPOFF" , file ) ; break ; case UNSPEC_CALLER : { char name [ 32 ] ; targetm . asm_out . generate_internal_label ( name , "LPCS" , INTVAL ( XVECEXP ( x , 0 , 0 ) ) ) ; assemble_name ( file , name ) ; } break ; case UNSPEC_SYMOFF : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fputc ( '-' , file ) ; if ( GET_CODE ( XVECEXP ( x , 0 , 1 ) ) == CONST ) { fputc ( '(' , file ) ; output_addr_const ( file , XVECEXP ( x , 0 , 1 ) ) ; fputc ( ')' , file ) ; } else output_addr_const ( file , XVECEXP ( x , 0 , 1 ) ) ; break ; case UNSPEC_PCREL_SYMOFF : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fputs ( "-(" , file ) ; output_addr_const ( file , XVECEXP ( x , 0 , 1 ) ) ; fputs ( "-.)" , file ) ; break ; case UNSPEC_GOTFUNCDESC : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fputs ( "@GOTFUNCDESC" , file ) ; break ; case UNSPEC_GOTOFFFUNCDESC : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fputs ( "@GOTOFFFUNCDESC" , file ) ; break ; default : return false ; } return true ; } else return false ; } </s>


<s> static NodeType * getEntryNode ( const SpillCostAnalysisGraph & G ) { return G . getRoot ( ) ; } </s>

Return the token chain corresponding to the entry of the function .


<s> void TriCoreAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> MCDisassembler :: DecodeStatus X86GenericDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & VStream , raw_ostream & CStream ) const { CommentStream = & CStream ; InternalInstruction InternalInstr ; dlog_t LoggerFn = logger ; if ( & VStream == & nulls ( ) ) LoggerFn = nullptr ; Region R ( Bytes , Address ) ; int Ret = decodeInstruction ( & InternalInstr , regionReader , ( const void * ) & R , LoggerFn , ( void * ) & VStream , ( const void * ) MII . get ( ) , Address , fMode ) ; if ( Ret ) { Size = InternalInstr . readerCursor - Address ; return Fail ; } else { Size = InternalInstr . length ; bool Ret = translateInstruction ( Instr , InternalInstr , this ) ; if ( ! Ret ) { unsigned Flags = X86 :: IP_NO_PREFIX ; if ( InternalInstr . hasAdSize ) Flags |= X86 :: IP_HAS_AD_SIZE ; if ( ! InternalInstr . mandatoryPrefix ) { if ( InternalInstr . hasOpSize ) Flags |= X86 :: IP_HAS_OP_SIZE ; if ( InternalInstr . repeatPrefix == 0xf2 ) Flags |= X86 :: IP_HAS_REPEAT_NE ; else if ( InternalInstr . repeatPrefix == 0xf3 && InternalInstr . opcode != 0x90 ) Flags |= X86 :: IP_HAS_REPEAT ; } Instr . setFlags ( Flags ) ; } return ( ! Ret ) ? Success : Fail ; } } </s>

Returns the disassembly of a single instruction .


<s> void MipsPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; addPass ( createAtomicExpandPass ( & getMipsTargetMachine ( ) ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> const char * ARMRelocator :: getName ( Relocator :: Type pType ) const { return ApplyFunctions [ pType ] . name ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s>
bool
PIC16AsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
SetupMachineFunction
(
MF
)
;
const
Function
*
F
=
MF
.
getFunction
(
)
;
ColorAutoSection
(
F
)
;
EmitFunctionFrame
(
MF
)
;
DbgInfo
.
BeginFunction
(
MF
)
;
const
MCSection
*
fCodeSection
=
getObjFileLowering
(
)
.
SectionForCode
(
CurrentFnSym
->
getName
(
)
,
PAN
::
isISR
(
F
->
getSection
(
)
)
)
;
OutStreamer
.
SwitchSection
(
fCodeSection
)
;
OutStreamer
.
EmitRawText
(
"\tretlw  low("
+
Twine
(
PAN
::
getFrameLabel
(
CurrentFnSym
->
getName
(
)
)
)
+
")"
)
;
OutStreamer
.
EmitRawText
(
"\tretlw  high("
+
Twine
(
PAN
::
getFrameLabel
(
CurrentFnSym
->
getName
(
)
)
)
+
")"
)
;
OutStreamer
.
EmitLabel
(
CurrentFnSym
)
;
DebugLoc
CurDL
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
I
!=
MF
.
begin
(
)
)
EmitBasicBlockStart
(
I
)
;
for
(
MachineBasicBlock
::
const_iterator
II
=
I
->
begin
(
)
,
E
=
I
->
end
(
)
;
II
!=
E
;
++
II
)
{
DebugLoc
DL
=
II
->
getDebugLoc
(
)
;
if
(
!
DL
.
isUnknown
(
)
&&
DL
!=
CurDL
)
{
DbgInfo
.
ChangeDebugLoc
(
MF
,
DL
)
;
CurDL
=
DL
;
}
EmitInstruction
(
II
)
;
}
}
DbgInfo
.
EndFunction
(
MF
)
;
return
false
;
}
</s>

PIC16
PIC16
"\tretlw  low("
")"
"\tretlw  high("
")"


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addPreservedID ( MachineLoopInfoID ) ; AU . addPreservedID ( MachineDominatorsID ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


"%qs function cannot have different interrupt type"


<s> int regs_used ( rtx x , int is_dest ) { enum rtx_code code ; const char * fmt ; int used = 0 ; if ( ! x ) return used ; code = GET_CODE ( x ) ; switch ( code ) { case REG : if ( REGNO ( x ) < 16 ) return ( ( ( 1 << hard_regno_nregs ( 0 , GET_MODE ( x ) ) ) - 1 ) << ( REGNO ( x ) + is_dest ) ) ; return 0 ; case SUBREG : { rtx y = SUBREG_REG ( x ) ; if ( ! REG_P ( y ) ) break ; if ( REGNO ( y ) < 16 ) return ( ( ( 1 << hard_regno_nregs ( 0 , GET_MODE ( x ) ) ) - 1 ) << ( REGNO ( y ) + subreg_regno_offset ( REGNO ( y ) , GET_MODE ( y ) , SUBREG_BYTE ( x ) , GET_MODE ( x ) ) + is_dest ) ) ; return 0 ; } case SET : return regs_used ( SET_SRC ( x ) , 0 ) | regs_used ( SET_DEST ( x ) , 16 ) ; case RETURN : return 0x00ffff00 ; case CLOBBER : is_dest = 1 ; break ; case MEM : is_dest = 0 ; break ; case CALL : used |= 0x00ff00f0 ; break ; default : break ; } fmt = GET_RTX_FORMAT ( code ) ; for ( int i = GET_RTX_LENGTH ( code ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { for ( int j = XVECLEN ( x , i ) - 1 ; j >= 0 ; j -- ) used |= regs_used ( XVECEXP ( x , i , j ) , is_dest ) ; } else if ( fmt [ i ] == 'e' ) used |= regs_used ( XEXP ( x , i ) , is_dest ) ; } return used ; } </s>

Given a X , a pattern of an insn or a part of it , return a mask of used general registers . Bits 0 .. 15 mean that the respective registers are used as inputs in the instruction . Bits 16 .. 31 mean that the registers 0 .. 15 , respectively , are used as outputs , or are clobbered . IS_DEST should be set to 16 if X is the destination of a SET , else to 0 .


<s> EVT ARMTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( ( ! IsMemset || ZeroMemset ) && Subtarget -> hasNEON ( ) && ! F -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoImplicitFloat ) ) { bool Fast ; if ( Size >= 16 && ( memOpAlign ( SrcAlign , DstAlign , 16 ) || ( allowsUnalignedMemoryAccesses ( MVT :: v2f64 , 0 , & Fast ) && Fast ) ) ) { return MVT :: v2f64 ; } else if ( Size >= 8 && ( memOpAlign ( SrcAlign , DstAlign , 8 ) || ( allowsUnalignedMemoryAccesses ( MVT :: f64 , 0 , & Fast ) && Fast ) ) ) { return MVT :: f64 ; } } if ( Size >= 4 ) return MVT :: i32 ; else if ( Size >= 2 ) return MVT :: i16 ; return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> void setKind ( BaseKind K ) { Kind = K ; } </s>


<s> int mmix_constant_address_p ( rtx x ) { RTX_CODE code = GET_CODE ( x ) ; int addend = 0 ; int constant_ok = TARGET_BASE_ADDRESSES != 0 ; switch ( code ) { case LABEL_REF : case SYMBOL_REF : return 1 ; case HIGH : return constant_ok ; case CONST_INT : addend = INTVAL ( x ) ; break ; case CONST_DOUBLE : if ( GET_MODE ( x ) != VOIDmode ) return constant_ok ; addend = CONST_DOUBLE_LOW ( x ) ; break ; case CONST : if ( GET_CODE ( XEXP ( x , 0 ) ) == PLUS ) { rtx x0 = XEXP ( XEXP ( x , 0 ) , 0 ) ; rtx x1 = XEXP ( XEXP ( x , 0 ) , 1 ) ; if ( ( GET_CODE ( x0 ) == SYMBOL_REF || GET_CODE ( x0 ) == LABEL_REF ) && ( GET_CODE ( x1 ) == CONST_INT || ( GET_CODE ( x1 ) == CONST_DOUBLE && GET_MODE ( x1 ) == VOIDmode ) ) ) addend = mmix_intval ( x1 ) ; else return constant_ok ; } else return constant_ok ; break ; default : return 0 ; } return constant_ok || ( addend & 3 ) == 0 ; } </s>

We must exclude constant addresses that have an increment that is not a multiple of four bytes because of restrictions of the GETA instruction , unless TARGET_BASE_ADDRESSES .


<s> const AAPInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"TGSI Always Inline Pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool TPCTargetLowering :: canMergeStoresTo ( unsigned AS , EVT MemVT , const SelectionDAG & DAG ) const { return AS == AddressSpace :: GLOBAL && MemVT . getSizeInBits ( ) <= 4 ; } </s>

Returns if it 's reasonable to merge stores to MemVT size .


<s> DecodeStatus SparcDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & VStream , raw_ostream & CStream ) const { uint32_t Insn ; bool isLittleEndian = getContext ( ) . getAsmInfo ( ) -> isLittleEndian ( ) ; DecodeStatus Result = readInstruction32 ( Bytes , Address , Size , Insn , isLittleEndian ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTableSparc32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>


<s> char * function_builder :: finish_name ( ) { obstack_1grow ( & m_string_obstack , 0 ) ; return ( char * ) obstack_finish ( & m_string_obstack ) ; } </s>

Zero-terminate and complete the function name being built .


<s> static void ix86_emit_save_reg_using_mov ( machine_mode mode , unsigned int regno , HOST_WIDE_INT cfa_offset ) { struct machine_function * m = cfun -> machine ; rtx reg = gen_rtx_REG ( mode , regno ) ; rtx mem , addr , base , insn ; addr = choose_baseaddr ( cfa_offset ) ; mem = gen_frame_mem ( mode , addr ) ; set_mem_align ( mem , GET_MODE_ALIGNMENT ( mode ) ) ; insn = emit_move_insn ( mem , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; base = addr ; if ( GET_CODE ( base ) == PLUS ) base = XEXP ( base , 0 ) ; gcc_checking_assert ( REG_P ( base ) ) ; if ( m -> fs . realigned ) { gcc_checking_assert ( stack_realign_drap ) ; if ( regno == REGNO ( crtl -> drap_reg ) ) { gcc_checking_assert ( cfun -> machine -> fs . fp_valid ) ; addr = plus_constant ( Pmode , hard_frame_pointer_rtx , cfun -> machine -> fs . fp_offset - cfa_offset ) ; mem = gen_rtx_MEM ( mode , addr ) ; add_reg_note ( insn , REG_CFA_DEF_CFA , mem ) ; } else { gcc_checking_assert ( cfun -> machine -> fs . fp_valid ) ; addr = plus_constant ( Pmode , hard_frame_pointer_rtx , cfun -> machine -> fs . fp_offset - cfa_offset ) ; mem = gen_rtx_MEM ( mode , addr ) ; add_reg_note ( insn , REG_CFA_EXPRESSION , gen_rtx_SET ( VOIDmode , mem , reg ) ) ; } } else if ( base != m -> fs . cfa_reg ) { addr = plus_constant ( Pmode , m -> fs . cfa_reg , m -> fs . cfa_offset - cfa_offset ) ; mem = gen_rtx_MEM ( mode , addr ) ; add_reg_note ( insn , REG_CFA_OFFSET , gen_rtx_SET ( VOIDmode , mem , reg ) ) ; } } </s>

Emit a single register save at CFA - CFA_OFFSET .


<s> InstructionCost RISCVTTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * DataTy , const Value * Ptr , bool VariableMask , Align Alignment , TTI :: TargetCostKind CostKind , const Instruction * I ) { if ( CostKind != TTI :: TCK_RecipThroughput ) return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , CostKind , I ) ; if ( ( Opcode == Instruction :: Load && ! isLegalMaskedGather ( DataTy , Align ( Alignment ) ) ) || ( Opcode == Instruction :: Store && ! isLegalMaskedScatter ( DataTy , Align ( Alignment ) ) ) ) return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , CostKind , I ) ; if ( ! isa < FixedVectorType > ( DataTy ) ) return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , CostKind , I ) ; auto * VTy = cast < FixedVectorType > ( DataTy ) ; unsigned NumLoads = VTy -> getNumElements ( ) ; InstructionCost MemOpCost = getMemoryOpCost ( Opcode , VTy -> getElementType ( ) , Alignment , 0 , CostKind , I ) ; return NumLoads * MemOpCost ; } </s>

Calculate the cost of Gather / Scatter operation .


<s> int get_dest_uid ( rtx label , int max_uid ) { rtx_insn * dest = next_real_insn ( label ) ; if ( ! dest ) return 0 ; int dest_uid = INSN_UID ( dest ) ; while ( dest_uid >= max_uid ) { dest = NEXT_INSN ( dest ) ; dest_uid = INSN_UID ( dest ) ; } if ( JUMP_P ( dest ) && GET_CODE ( PATTERN ( dest ) ) == RETURN ) return 0 ; return dest_uid ; } </s>

Return the UID of the insn that follows the specified label .


<s>
SDValue
XCoreTargetLowering
::
LowerCall
(
SDValue
Chain
,
SDValue
Callee
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
bool
doesNotRet
,
bool
&
isTailCall
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
OutVals
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .

XCore
XCore
ISD::OutputArg
ISD::InputArg
"Unsupported calling convention"


<s> unsigned size ( ) const { return Insts . size ( ) ; } </s>

The number of name/type pairs is returned .


<s> const TargetRegisterClass * ARMTargetLowering :: getRegClassFor ( EVT VT ) const { if ( Subtarget -> hasNEON ( ) ) { if ( VT == MVT :: v4i64 ) return & ARM :: QQPRRegClass ; if ( VT == MVT :: v8i64 ) return & ARM :: QQQQPRRegClass ; } return TargetLowering :: getRegClassFor ( VT ) ; } </s>

Return the register class that should be used for the specified value type .

ARM ARM MVT::v4i64 ARM::QQPRRegClass MVT::v8i64 ARM::QQQQPRRegClass


<s> bool TVMPassConfig :: addILPOpts ( ) { addPass ( createTVMIfConversionTerm ( ) ) ; return true ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .


<s> void MipsTargetELFStreamer :: emitDirectiveCpRestore ( SmallVector < MCInst , 3 > & StoreInsts , int Offset ) { MipsTargetStreamer :: emitDirectiveCpRestore ( StoreInsts , Offset ) ; if ( ! Pic || ( getABI ( ) . IsN32 ( ) || getABI ( ) . IsN64 ( ) ) ) return ; for ( const MCInst & Inst : StoreInsts ) getStreamer ( ) . EmitInstruction ( Inst , STI ) ; } </s>


<s>
virtual
StringRef
getPassName
(
)
const
{
return
"P2 Del Useless jmp"
;
}
</s>


<s> static bool hppa_rtx_costs_shadd_p ( rtx x ) { if ( GET_CODE ( x ) != PLUS || ! REG_P ( XEXP ( x , 1 ) ) ) return false ; rtx op0 = XEXP ( x , 0 ) ; if ( GET_CODE ( op0 ) == ASHIFT && CONST_INT_P ( XEXP ( op0 , 1 ) ) && REG_P ( XEXP ( op0 , 0 ) ) ) { unsigned HOST_WIDE_INT x = UINTVAL ( XEXP ( op0 , 1 ) ) ; return x == 1 || x == 2 || x == 3 ; } if ( GET_CODE ( op0 ) == MULT && CONST_INT_P ( XEXP ( op0 , 1 ) ) && REG_P ( XEXP ( op0 , 0 ) ) ) { unsigned HOST_WIDE_INT x = UINTVAL ( XEXP ( op0 , 1 ) ) ; return x == 2 || x == 4 || x == 8 ; } return false ; } </s>

Return true if X represents a ( possibly non-canonical ) shNadd pattern . The machine mode of X is known to be SImode or DImode .


<s> static unsigned int riscv_next_saved_reg ( unsigned int regno , unsigned int limit , HOST_WIDE_INT * offset , bool inc = true ) { if ( inc ) regno ++ ; while ( regno <= limit ) { if ( BITSET_P ( cfun -> machine -> frame . mask , regno - GP_REG_FIRST ) ) { * offset = * offset - UNITS_PER_WORD ; return regno ; } regno ++ ; } return INVALID_REGNUM ; } </s>

Return the next register up from REGNO up to LIMIT for the callee to save or restore . OFFSET will be adjusted accordingly . If INC is set , then REGNO will be incremented first . Returns INVALID_REGNUM if there is no such next register .


<s> SDValue XCoreSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { unsigned SizeBitWidth = Size . getValueSizeInBits ( ) ; if ( ! AlwaysInline && Alignment >= Align ( 4 ) && DAG . MaskedValueIsZero ( Size , APInt ( SizeBitWidth , 3 ) ) ) { const TargetLowering & TLI = * DAG . getSubtarget ( ) . getTargetLowering ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; Entry . Node = Src ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMCPY ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( "__memcpy_4" , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) , std :: move ( Args ) ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .


<s> virtual const AMDGPUInstrInfo * getInstrInfo ( ) const { return InstrInfo ; } </s>


<s> bool PPCLoopPreIncPrep :: runOnFunction ( Function & F ) { LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolution > ( ) ; bool MadeChange = false ; for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L = df_begin ( * I ) , LE = df_end ( * I ) ; L != LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ; return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


"unknown base architecture %<0x%x%>, %qs failed"

"some tuning parameters will fall back to default"


<s>
bool
X86AsmPrinter
::
PrintAsmOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
{
if
(
ExtraCode
[
1
]
!=
0
)
return
true
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNo
)
;
switch
(
ExtraCode
[
0
]
)
{
default
:
return
AsmPrinter
::
PrintAsmOperand
(
MI
,
OpNo
,
ExtraCode
,
O
)
;
case
'a'
:
switch
(
MO
.
getType
(
)
)
{
default
:
return
true
;
case
MachineOperand
::
MO_Immediate
:
O
<<
MO
.
getImm
(
)
;
return
false
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
case
MachineOperand
::
MO_JumpTableIndex
:
case
MachineOperand
::
MO_ExternalSymbol
:
llvm_unreachable
(
"unexpected operand type!"
)
;
case
MachineOperand
::
MO_GlobalAddress
:
PrintSymbolOperand
(
MO
,
O
)
;
if
(
Subtarget
->
isPICStyleRIPRel
(
)
)
O
<<
"(%rip)"
;
return
false
;
case
MachineOperand
::
MO_Register
:
O
<<
'('
;
PrintOperand
(
MI
,
OpNo
,
O
)
;
O
<<
')'
;
return
false
;
}
case
'c'
:
switch
(
MO
.
getType
(
)
)
{
default
:
PrintOperand
(
MI
,
OpNo
,
O
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
O
<<
MO
.
getImm
(
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
case
MachineOperand
::
MO_JumpTableIndex
:
case
MachineOperand
::
MO_ExternalSymbol
:
llvm_unreachable
(
"unexpected operand type!"
)
;
case
MachineOperand
::
MO_GlobalAddress
:
PrintSymbolOperand
(
MO
,
O
)
;
break
;
}
return
false
;
case
'A'
:
if
(
MO
.
isReg
(
)
)
{
O
<<
'*'
;
PrintOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
}
return
true
;
case
'b'
:
case
'h'
:
case
'w'
:
case
'k'
:
case
'q'
:
case
'V'
:
if
(
MO
.
isReg
(
)
)
return
printAsmMRegister
(
*
this
,
MO
,
ExtraCode
[
0
]
,
O
)
;
PrintOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
case
'P'
:
PrintPCRelImm
(
MI
,
OpNo
,
O
)
;
return
false
;
case
'n'
:
if
(
MO
.
isImm
(
)
)
{
O
<<
MO
.
getImm
(
)
;
return
false
;
}
O
<<
'-'
;
}
}
PrintOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
}
</s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> void R600MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; if ( MI . getOpcode ( ) == AMDGPU :: RETURN || MI . getOpcode ( ) == AMDGPU :: FETCH_CLAUSE || MI . getOpcode ( ) == AMDGPU :: ALU_CLAUSE || MI . getOpcode ( ) == AMDGPU :: BUNDLE || MI . getOpcode ( ) == AMDGPU :: KILL ) { return ; } else if ( IS_VTX ( Desc ) ) { uint64_t InstWord01 = getBinaryCodeForInstr ( MI , Fixups , STI ) ; uint32_t InstWord2 = MI . getOperand ( 2 ) . getImm ( ) ; if ( ! ( STI . getFeatureBits ( ) [ AMDGPU :: FeatureCaymanISA ] ) ) { InstWord2 |= 1 << 19 ; } Emit ( InstWord01 , OS ) ; Emit ( InstWord2 , OS ) ; Emit ( ( uint32_t ) 0 , OS ) ; } else if ( IS_TEX ( Desc ) ) { int64_t Sampler = MI . getOperand ( 14 ) . getImm ( ) ; int64_t SrcSelect [ 4 ] = { MI . getOperand ( 2 ) . getImm ( ) , MI . getOperand ( 3 ) . getImm ( ) , MI . getOperand ( 4 ) . getImm ( ) , MI . getOperand ( 5 ) . getImm ( ) } ; int64_t Offsets [ 3 ] = { MI . getOperand ( 6 ) . getImm ( ) & 0x1F , MI . getOperand ( 7 ) . getImm ( ) & 0x1F , MI . getOperand ( 8 ) . getImm ( ) & 0x1F } ; uint64_t Word01 = getBinaryCodeForInstr ( MI , Fixups , STI ) ; uint32_t Word2 = Sampler << 15 | SrcSelect [ ELEMENT_X ] << 20 | SrcSelect [ ELEMENT_Y ] << 23 | SrcSelect [ ELEMENT_Z ] << 26 | SrcSelect [ ELEMENT_W ] << 29 | Offsets [ 0 ] << 0 | Offsets [ 1 ] << 5 | Offsets [ 2 ] << 10 ; Emit ( Word01 , OS ) ; Emit ( Word2 , OS ) ; Emit ( ( uint32_t ) 0 , OS ) ; } else { uint64_t Inst = getBinaryCodeForInstr ( MI , Fixups , STI ) ; if ( ( STI . getFeatureBits ( ) [ AMDGPU :: FeatureR600ALUInst ] ) && ( ( Desc . TSFlags & R600_InstFlag :: OP1 ) || Desc . TSFlags & R600_InstFlag :: OP2 ) ) { uint64_t ISAOpCode = Inst & ( 0x3FFULL << 39 ) ; Inst &= ~ ( 0x3FFULL << 39 ) ; Inst |= ISAOpCode << 1 ; } Emit ( Inst , OS ) ; } } </s>

Encode the given Inst to bytes and append to CB .


<s> bool X86InstrInfo :: findCommutedOpIndices ( MachineInstr & MI , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { if ( ! MI . isCommutable ( ) ) return false ; switch ( MI . getOpcode ( ) ) { case X86 :: CMPPDrri : case X86 :: CMPPSrri : case X86 :: VCMPPDrri : case X86 :: VCMPPSrri : case X86 :: VCMPPDYrri : case X86 :: VCMPPSYrri : { unsigned Imm = MI . getOperand ( 3 ) . getImm ( ) & 0x7 ; switch ( Imm ) { case 0x00 : case 0x03 : case 0x04 : case 0x07 : return fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , 1 , 2 ) ; } return false ; } default : const X86InstrFMA3Group * FMA3Group = X86InstrFMA3Info :: getFMA3Group ( MI . getOpcode ( ) ) ; if ( FMA3Group ) return findFMA3CommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 , * FMA3Group ) ; return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; } return false ; } </s>

Returns true iff the routine could find two commutable operands in the given machine instruction .


<s>
bool
MipsSEDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
SDValue
Base
,
Offset
;
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
OutOps
.
push_back
(
Op
)
;
OutOps
.
push_back
(
CurDAG
->
getTargetConstant
(
0
,
MVT
::
i32
)
)
;
return
false
;
case
InlineAsm
::
Constraint_m
:
if
(
selectAddrRegImm16
(
Op
,
Base
,
Offset
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
return
false
;
}
OutOps
.
push_back
(
Op
)
;
OutOps
.
push_back
(
CurDAG
->
getTargetConstant
(
0
,
MVT
::
i32
)
)
;
return
false
;
case
InlineAsm
::
Constraint_R
:
if
(
selectAddrRegImm9
(
Op
,
Base
,
Offset
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
return
false
;
}
OutOps
.
push_back
(
Op
)
;
OutOps
.
push_back
(
CurDAG
->
getTargetConstant
(
0
,
MVT
::
i32
)
)
;
return
false
;
case
InlineAsm
::
Constraint_ZC
:
if
(
Subtarget
->
inMicroMipsMode
(
)
)
{
if
(
selectAddrRegImm12
(
Op
,
Base
,
Offset
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
return
false
;
}
}
else
if
(
Subtarget
->
hasMips32r6
(
)
)
{
if
(
selectAddrRegImm9
(
Op
,
Base
,
Offset
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
return
false
;
}
}
else
if
(
selectAddrRegImm16
(
Op
,
Base
,
Offset
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
return
false
;
}
OutOps
.
push_back
(
Op
)
;
OutOps
.
push_back
(
CurDAG
->
getTargetConstant
(
0
,
MVT
::
i32
)
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> bool supportsEfficientVectorElementLoadStore ( ) { return true ; } </s>

If target has efficient vector element load/store instructions , it can return true here so that insertion/extraction costs are not added to the scalarization cost of a load/store .


<s> Type * getElementType ( ) const { return PointeeTy ; } </s>

Returns the vector 's element type . Only valid for vector types .


<s> SDValue XCoreSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { unsigned SizeBitWidth = Size . getValueSizeInBits ( ) ; if ( ! AlwaysInline && ( Align & 3 ) == 0 && DAG . MaskedValueIsZero ( Size , APInt ( SizeBitWidth , 3 ) ) ) { const TargetLowering & TLI = * DAG . getSubtarget ( ) . getTargetLowering ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; Entry . Node = Src ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMCPY ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( "__memcpy_4" , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) , std :: move ( Args ) ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>


<s> PPCSubtarget :: PPCSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const PPCTargetMachine & TM ) : PPCGenSubtargetInfo ( TT , CPU , FS ) , TargetTriple ( TT ) , IsPPC64 ( TargetTriple . getArch ( ) == Triple :: ppc64 || TargetTriple . getArch ( ) == Triple :: ppc64le ) , TM ( TM ) , FrameLowering ( initializeSubtargetDependencies ( CPU , FS ) ) , InstrInfo ( * this ) , TLInfo ( TM , * this ) { } </s>

This constructor initializes the data members to match that of the specified triple .


<s> static tree spu_build_builtin_va_list ( void ) { tree f_args , f_skip , record , type_decl ; bool owp ; record = ( * lang_hooks . types . make_type ) ( RECORD_TYPE ) ; type_decl = build_decl ( BUILTINS_LOCATION , TYPE_DECL , get_identifier ( "__va_list_tag" ) , record ) ; f_args = build_decl ( BUILTINS_LOCATION , FIELD_DECL , get_identifier ( "__args" ) , ptr_type_node ) ; f_skip = build_decl ( BUILTINS_LOCATION , FIELD_DECL , get_identifier ( "__skip" ) , ptr_type_node ) ; DECL_FIELD_CONTEXT ( f_args ) = record ; SET_DECL_ALIGN ( f_args , 128 ) ; DECL_USER_ALIGN ( f_args ) = 1 ; DECL_FIELD_CONTEXT ( f_skip ) = record ; SET_DECL_ALIGN ( f_skip , 128 ) ; DECL_USER_ALIGN ( f_skip ) = 1 ; TYPE_STUB_DECL ( record ) = type_decl ; TYPE_NAME ( record ) = type_decl ; TYPE_FIELDS ( record ) = f_args ; DECL_CHAIN ( f_args ) = f_skip ; owp = warn_padded ; warn_padded = false ; layout_type ( record ) ; warn_padded = owp ; return build_array_type ( record , build_index_type ( size_zero_node ) ) ; } </s>

Create and return the va_list datatype . On SPU , va_list is an array type equivalent to typedef struct __va_list_tag { void * __args __attribute__ ( ( __aligned ( 16 ) ) ) ; void * __skip __attribute__ ( ( __aligned ( 16 ) ) ) ; } va_list [ 1 ] ; where __args points to the arg that will be returned by the next va_arg ( ) , and __skip points to the previous stack frame such that when __args == __skip we should advance __args by 32 bytes .


<s>
void
LanaiDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
return
;
}
switch
(
Opcode
)
{
case
ISD
::
FrameIndex
:
selectFrameIndex
(
Node
)
;
return
;
default
:
break
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

Lanai
Lanai
"Selecting: "
"\n"
"== "
"\n"
ISD::FrameIndex


<s> void ARM64InstPrinter :: printImplicitlyTypedVectorList ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { printVectorList ( MI , OpNum , O , "" ) ; } </s>

Print a list of vector registers where the type suffix is implicit ( i.e .


<s>
unsigned
Cpu0ABIInfo
::
GetCalleeAllocdArgSizeInBytes
(
CallingConv
::
ID
CC
)
const
{
if
(
IsO32
(
)
)
return
CC
!=
0
;
if
(
IsS32
(
)
)
return
0
;
llvm_unreachable
(
"Unhandled ABI"
)
;
}
</s>

Obtain the size of the area allocated by the callee for arguments .


<s> bool RISCVInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { TBB = FBB = nullptr ; Cond . clear ( ) ; MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) || ! isUnpredicatedTerminator ( * I ) ) return false ; MachineBasicBlock :: iterator FirstUncondOrIndirectBr = MBB . end ( ) ; int NumTerminators = 0 ; for ( auto J = I . getReverse ( ) ; J != MBB . rend ( ) && isUnpredicatedTerminator ( * J ) ; J ++ ) { NumTerminators ++ ; if ( J -> getDesc ( ) . isUnconditionalBranch ( ) || J -> getDesc ( ) . isIndirectBranch ( ) ) { FirstUncondOrIndirectBr = J . getReverse ( ) ; } } if ( AllowModify && FirstUncondOrIndirectBr != MBB . end ( ) ) { while ( std :: next ( FirstUncondOrIndirectBr ) != MBB . end ( ) ) { std :: next ( FirstUncondOrIndirectBr ) -> eraseFromParent ( ) ; NumTerminators -- ; } I = FirstUncondOrIndirectBr ; } if ( I -> getDesc ( ) . isIndirectBranch ( ) ) return true ; if ( NumTerminators > 2 ) return true ; if ( NumTerminators == 1 && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { TBB = getBranchDestBlock ( * I ) ; return false ; } if ( NumTerminators == 1 && I -> getDesc ( ) . isConditionalBranch ( ) ) { parseCondBranch ( * I , TBB , Cond ) ; return false ; } if ( NumTerminators == 2 && std :: prev ( I ) -> getDesc ( ) . isConditionalBranch ( ) && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { parseCondBranch ( * std :: prev ( I ) , TBB , Cond ) ; FBB = getBranchDestBlock ( * I ) ; return false ; } return true ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> const char * MipsTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case MipsISD :: JmpLink : return "MipsISD::JmpLink" ; case MipsISD :: TailCall : return "MipsISD::TailCall" ; case MipsISD :: Hi : return "MipsISD::Hi" ; case MipsISD :: Lo : return "MipsISD::Lo" ; case MipsISD :: GPRel : return "MipsISD::GPRel" ; case MipsISD :: ThreadPointer : return "MipsISD::ThreadPointer" ; case MipsISD :: Ret : return "MipsISD::Ret" ; case MipsISD :: EH_RETURN : return "MipsISD::EH_RETURN" ; case MipsISD :: FPBrcond : return "MipsISD::FPBrcond" ; case MipsISD :: FPCmp : return "MipsISD::FPCmp" ; case MipsISD :: CMovFP_T : return "MipsISD::CMovFP_T" ; case MipsISD :: CMovFP_F : return "MipsISD::CMovFP_F" ; case MipsISD :: TruncIntFP : return "MipsISD::TruncIntFP" ; case MipsISD :: ExtractLOHI : return "MipsISD::ExtractLOHI" ; case MipsISD :: InsertLOHI : return "MipsISD::InsertLOHI" ; case MipsISD :: Mult : return "MipsISD::Mult" ; case MipsISD :: Multu : return "MipsISD::Multu" ; case MipsISD :: MAdd : return "MipsISD::MAdd" ; case MipsISD :: MAddu : return "MipsISD::MAddu" ; case MipsISD :: MSub : return "MipsISD::MSub" ; case MipsISD :: MSubu : return "MipsISD::MSubu" ; case MipsISD :: DivRem : return "MipsISD::DivRem" ; case MipsISD :: DivRemU : return "MipsISD::DivRemU" ; case MipsISD :: DivRem16 : return "MipsISD::DivRem16" ; case MipsISD :: DivRemU16 : return "MipsISD::DivRemU16" ; case MipsISD :: BuildPairF64 : return "MipsISD::BuildPairF64" ; case MipsISD :: ExtractElementF64 : return "MipsISD::ExtractElementF64" ; case MipsISD :: Wrapper : return "MipsISD::Wrapper" ; case MipsISD :: Sync : return "MipsISD::Sync" ; case MipsISD :: Ext : return "MipsISD::Ext" ; case MipsISD :: Ins : return "MipsISD::Ins" ; case MipsISD :: LWL : return "MipsISD::LWL" ; case MipsISD :: LWR : return "MipsISD::LWR" ; case MipsISD :: SWL : return "MipsISD::SWL" ; case MipsISD :: SWR : return "MipsISD::SWR" ; case MipsISD :: LDL : return "MipsISD::LDL" ; case MipsISD :: LDR : return "MipsISD::LDR" ; case MipsISD :: SDL : return "MipsISD::SDL" ; case MipsISD :: SDR : return "MipsISD::SDR" ; case MipsISD :: EXTP : return "MipsISD::EXTP" ; case MipsISD :: EXTPDP : return "MipsISD::EXTPDP" ; case MipsISD :: EXTR_S_H : return "MipsISD::EXTR_S_H" ; case MipsISD :: EXTR_W : return "MipsISD::EXTR_W" ; case MipsISD :: EXTR_R_W : return "MipsISD::EXTR_R_W" ; case MipsISD :: EXTR_RS_W : return "MipsISD::EXTR_RS_W" ; case MipsISD :: SHILO : return "MipsISD::SHILO" ; case MipsISD :: MTHLIP : return "MipsISD::MTHLIP" ; case MipsISD :: MULT : return "MipsISD::MULT" ; case MipsISD :: MULTU : return "MipsISD::MULTU" ; case MipsISD :: MADD_DSP : return "MipsISD::MADD_DSP" ; case MipsISD :: MADDU_DSP : return "MipsISD::MADDU_DSP" ; case MipsISD :: MSUB_DSP : return "MipsISD::MSUB_DSP" ; case MipsISD :: MSUBU_DSP : return "MipsISD::MSUBU_DSP" ; case MipsISD :: SHLL_DSP : return "MipsISD::SHLL_DSP" ; case MipsISD :: SHRA_DSP : return "MipsISD::SHRA_DSP" ; case MipsISD :: SHRL_DSP : return "MipsISD::SHRL_DSP" ; case MipsISD :: SETCC_DSP : return "MipsISD::SETCC_DSP" ; case MipsISD :: SELECT_CC_DSP : return "MipsISD::SELECT_CC_DSP" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific


"X86 Load Value Injection (LVI) Ret-Hardening"

getPassName - Return a nice clean name for a pass .


<s>
bool
RISCVInstrInfo
::
reverseBranchCondition
(
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
assert
(
(
Cond
.
size
(
)
==
3
)
&&
"Invalid branch condition!"
)
;
if
(
Cond
[
0
]
.
getImm
(
)
==
RISCV
::
LoopBranch
)
return
true
;
Cond
[
0
]
.
setImm
(
getOppositeBranchOpcode
(
Cond
[
0
]
.
getImm
(
)
)
)
;
return
false
;
}
</s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


"Alternative MOS backend expected, but none was given!"


<s> bool Cpu0RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> const DataLayout * getDataLayout ( ) const override { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> static bool isBranch ( const MCInst & Inst ) { unsigned Opcode = Inst . getOpcode ( ) ; switch ( Opcode ) { default : return false ; break ; case AArch64 :: B : case AArch64 :: Bcc : case AArch64 :: BR : case AArch64 :: BRAA : case AArch64 :: BRAAZ : case AArch64 :: BRAB : case AArch64 :: BRABZ : case AArch64 :: BL : case AArch64 :: BLR : case AArch64 :: BLRAA : case AArch64 :: BLRAAZ : case AArch64 :: BLRAB : case AArch64 :: BLRABZ : case AArch64 :: CBZW : case AArch64 :: CBZX : case AArch64 :: CBNZW : case AArch64 :: CBNZX : case AArch64 :: CCMPWr : case AArch64 :: CCMPXr : case AArch64 :: G_FCMP : case AArch64 :: G_ICMP : case AArch64 :: TBZW : case AArch64 :: TBZX : case AArch64 :: TBNZW : case AArch64 :: TBNZX : case AArch64 :: RET : case AArch64 :: RETAA : case AArch64 :: RETAB : case AArch64 :: SVC : return true ; break ; } return false ; } </s>

Returns true if this is a conditional , unconditional , or indirect branch .


<s> static bool arc_no_speculation_in_delay_slots_p ( ) { return true ; } </s>


<s> int m68hc11_page0_symbol_p ( rtx x ) { switch ( GET_CODE ( x ) ) { case SYMBOL_REF : return XSTR ( x , 0 ) != 0 && XSTR ( x , 0 ) [ 0 ] == '@' ; case CONST : return m68hc11_page0_symbol_p ( XEXP ( x , 0 ) ) ; case PLUS : if ( ! m68hc11_page0_symbol_p ( XEXP ( x , 0 ) ) ) return 0 ; return GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT && INTVAL ( XEXP ( x , 1 ) ) < 256 && INTVAL ( XEXP ( x , 1 ) ) >= 0 ; default : return 0 ; } } </s>


<s> TargetLowering :: ConstraintType TLCS900TargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return C_RegisterClass ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> void ARMBaseRegisterInfo :: updateRegAllocHint ( Register Reg , Register NewReg , MachineFunction & MF ) const { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; std :: pair < Register , Register > Hint = MRI -> getRegAllocationHint ( Reg ) ; if ( ( Hint . first == ARMRI :: RegPairOdd || Hint . first == ARMRI :: RegPairEven ) && Hint . second . isVirtual ( ) ) { Register OtherReg = Hint . second ; Hint = MRI -> getRegAllocationHint ( OtherReg ) ; if ( Hint . second == Reg ) { MRI -> setRegAllocationHint ( OtherReg , Hint . first , NewReg ) ; if ( Register :: isVirtualRegister ( NewReg ) ) MRI -> setRegAllocationHint ( NewReg , Hint . first == ARMRI :: RegPairOdd ? ARMRI :: RegPairEven : ARMRI :: RegPairOdd , OtherReg ) ; } } } </s>

A callback to allow target a chance to update register allocation hints when a register is `` changed '' ( e.g .

ARM ARM ARMRI::RegPairOdd ARMRI::RegPairEven ARMRI::RegPairOdd ARMRI::RegPairEven ARMRI::RegPairOdd


<s>
bool
SIShrinkInstructions
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
const
SIInstrInfo
*
TII
=
static_cast
<
const
SIInstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
const
SIRegisterInfo
&
TRI
=
TII
->
getRegisterInfo
(
)
;
std
::
vector
<
unsigned
>
I1Defs
;
for
(
MachineFunction
::
iterator
BI
=
MF
.
begin
(
)
,
BE
=
MF
.
end
(
)
;
BI
!=
BE
;
++
BI
)
{
MachineBasicBlock
&
MBB
=
*
BI
;
MachineBasicBlock
::
iterator
I
,
Next
;
for
(
I
=
MBB
.
begin
(
)
;
I
!=
MBB
.
end
(
)
;
I
=
Next
)
{
Next
=
std
::
next
(
I
)
;
MachineInstr
&
MI
=
*
I
;
if
(
!
TII
->
hasVALU32BitEncoding
(
MI
.
getOpcode
(
)
)
)
continue
;
if
(
!
canShrink
(
MI
,
TII
,
TRI
,
MRI
)
)
{
if
(
!
MI
.
isCommutable
(
)
||
!
TII
->
commuteInstruction
(
&
MI
)
||
!
canShrink
(
MI
,
TII
,
TRI
,
MRI
)
)
continue
;
}
int
Op32
=
AMDGPU
::
getVOPe32
(
MI
.
getOpcode
(
)
)
;
if
(
Op32
==
1
)
continue
;
if
(
TII
->
isVOPC
(
Op32
)
)
{
unsigned
DstReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
if
(
TargetRegisterInfo
::
isVirtualRegister
(
DstReg
)
)
{
MRI
.
setRegAllocationHint
(
MI
.
getOperand
(
0
)
.
getReg
(
)
,
0
,
AMDGPU
::
VCC
)
;
continue
;
}
if
(
DstReg
!=
AMDGPU
::
VCC
)
continue
;
}
DEBUG
(
dbgs
(
)
<<
"Shrinking "
;
MI
.
dump
(
)
;
dbgs
(
)
<<
'\n'
;
)
;
MachineInstrBuilder
Inst32
=
BuildMI
(
MBB
,
I
,
MI
.
getDebugLoc
(
)
,
TII
->
get
(
Op32
)
)
;
Inst32
.
addOperand
(
MI
.
getOperand
(
0
)
)
;
Inst32
.
addOperand
(
*
TII
->
getNamedOperand
(
MI
,
AMDGPU
::
OpName
::
src0
)
)
;
const
MachineOperand
*
Src1
=
TII
->
getNamedOperand
(
MI
,
AMDGPU
::
OpName
::
src1
)
;
if
(
Src1
)
Inst32
.
addOperand
(
*
Src1
)
;
++
NumInstructionsShrunk
;
MI
.
eraseFromParent
(
)
;
foldImmediates
(
*
Inst32
,
TII
,
MRI
)
;
DEBUG
(
dbgs
(
)
<<
"e32 MI = "
<<
*
Inst32
<<
'\n'
)
;
}
}
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static void mips_print_operand_reloc ( FILE * file , rtx op , enum mips_symbol_context context , const char * * relocs ) { enum mips_symbol_type symbol_type ; const char * p ; symbol_type = mips_classify_symbolic_expression ( op , context ) ; gcc_assert ( relocs [ symbol_type ] ) ; fputs ( relocs [ symbol_type ] , file ) ; output_addr_const ( file , mips_strip_unspec_address ( op ) ) ; for ( p = relocs [ symbol_type ] ; * p != 0 ; p ++ ) if ( * p == '(' ) fputc ( ')' , file ) ; } </s>

Print symbolic operand OP , which is part of a HIGH or LO_SUM in context CONTEXT . RELOCS is the array of relocations to use .


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < SparcELFTargetObjectFile > ( ) ) , DL ( computeDataLayout ( is64bit ) ) , Subtarget ( TT , CPU , FS , * this , is64bit ) { initAsmInfo ( ) ; } </s>


<s> bool SIInstrInfo :: isOperandLegal ( const MachineInstr * MI , unsigned OpIdx , const MachineOperand * MO ) const { const MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const MCInstrDesc & InstDesc = get ( MI -> getOpcode ( ) ) ; const MCOperandInfo & OpInfo = InstDesc . OpInfo [ OpIdx ] ; const TargetRegisterClass * DefinedRC = OpInfo . RegClass != - 1 ? RI . getRegClass ( OpInfo . RegClass ) : nullptr ; if ( ! MO ) MO = & MI -> getOperand ( OpIdx ) ; if ( usesConstantBus ( MRI , * MO ) ) { unsigned SGPRUsed = MO -> isReg ( ) ? MO -> getReg ( ) : ( unsigned ) AMDGPU :: NoRegister ; for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i == OpIdx ) continue ; if ( usesConstantBus ( MRI , MI -> getOperand ( i ) ) && MI -> getOperand ( i ) . isReg ( ) && MI -> getOperand ( i ) . getReg ( ) != SGPRUsed ) { return false ; } } } if ( MO -> isReg ( ) ) { assert ( DefinedRC ) ; const TargetRegisterClass * RC = MRI . getRegClass ( MO -> getReg ( ) ) ; return RI . getCommonSubClass ( RC , RI . getRegClass ( OpInfo . RegClass ) ) ; } assert ( MO -> isImm ( ) || MO -> isFPImm ( ) || MO -> isTargetIndex ( ) || MO -> isFI ( ) ) ; if ( ! DefinedRC ) { return true ; } return isImmOperandLegal ( MI , OpIdx , * MO ) ; } </s>

Check if MO is a legal operand if it was the OpIdx Operand for MI .


<s> static void arm_setup_incoming_varargs ( cumulative_args_t pcum_v , machine_mode mode , tree type , int * pretend_size , int second_time ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * pcum = get_cumulative_args ( pcum_v ) ; int nregs ; cfun -> machine -> uses_anonymous_args = 1 ; if ( pcum -> pcs_variant <= ARM_PCS_AAPCS_LOCAL ) { nregs = pcum -> aapcs_ncrn ; if ( ( nregs & 1 ) && arm_needs_doubleword_align ( mode , type ) ) nregs ++ ; } else nregs = pcum -> nregs ; if ( nregs < NUM_ARG_REGS ) * pretend_size = ( NUM_ARG_REGS - nregs ) * UNITS_PER_WORD ; } </s>

Worker function for TARGET_SETUP_INCOMING_VARARGS . On the ARM , PRETEND_SIZE is set in order to have the prologue push the last named arg and all anonymous args onto the stack . XXX I know the prologue should n't be pushing registers , but it is faster that way .


<s> rtx mt_return_addr_rtx ( int count ) { if ( count != 0 ) return NULL_RTX ; return get_hard_reg_initial_val ( Pmode , GPR_LINK ) ; } </s>


<s> void KudeyarInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> const MCExpr * X86TargetLowering :: getPICJumpTableRelocBaseExpr ( const MachineFunction * MF , unsigned JTI , MCContext & Ctx ) const { if ( Subtarget . isPICStyleRIPRel ( ) ) return TargetLowering :: getPICJumpTableRelocBaseExpr ( MF , JTI , Ctx ) ; return MCSymbolRefExpr :: create ( MF -> getPICBaseSymbol ( ) , Ctx ) ; } </s>

This returns the relocation base for the given PIC jumptable , the same as getPICJumpTableRelocBase , but as an MCExpr .


<s> static void find_constant_pool_ref ( rtx_insn * insn , rtx * ref ) { if ( s390_safe_relative_long_p ( insn ) ) return ; find_constant_pool_ref_1 ( PATTERN ( insn ) , ref ) ; } </s>

Find an annotated literal pool symbol referenced in RTX X , and store it at REF . Will abort if X contains references to more than one such pool symbol ; multiple references to the same symbol are allowed , however . The rtx pointed to by REF must be initialized to NULL_RTX by the caller before calling this routine .


<s> const char * PPCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case PPCISD :: FSEL : return "PPCISD::FSEL" ; case PPCISD :: FCFID : return "PPCISD::FCFID" ; case PPCISD :: FCTIDZ : return "PPCISD::FCTIDZ" ; case PPCISD :: FCTIWZ : return "PPCISD::FCTIWZ" ; case PPCISD :: STFIWX : return "PPCISD::STFIWX" ; case PPCISD :: VMADDFP : return "PPCISD::VMADDFP" ; case PPCISD :: VNMSUBFP : return "PPCISD::VNMSUBFP" ; case PPCISD :: VPERM : return "PPCISD::VPERM" ; case PPCISD :: Hi : return "PPCISD::Hi" ; case PPCISD :: Lo : return "PPCISD::Lo" ; case PPCISD :: TOC_ENTRY : return "PPCISD::TOC_ENTRY" ; case PPCISD :: TOC_RESTORE : return "PPCISD::TOC_RESTORE" ; case PPCISD :: LOAD : return "PPCISD::LOAD" ; case PPCISD :: LOAD_TOC : return "PPCISD::LOAD_TOC" ; case PPCISD :: DYNALLOC : return "PPCISD::DYNALLOC" ; case PPCISD :: GlobalBaseReg : return "PPCISD::GlobalBaseReg" ; case PPCISD :: SRL : return "PPCISD::SRL" ; case PPCISD :: SRA : return "PPCISD::SRA" ; case PPCISD :: SHL : return "PPCISD::SHL" ; case PPCISD :: EXTSW_32 : return "PPCISD::EXTSW_32" ; case PPCISD :: STD_32 : return "PPCISD::STD_32" ; case PPCISD :: CALL_SVR4 : return "PPCISD::CALL_SVR4" ; case PPCISD :: CALL_NOP_SVR4 : return "PPCISD::CALL_NOP_SVR4" ; case PPCISD :: CALL_Darwin : return "PPCISD::CALL_Darwin" ; case PPCISD :: NOP : return "PPCISD::NOP" ; case PPCISD :: MTCTR : return "PPCISD::MTCTR" ; case PPCISD :: BCTRL_Darwin : return "PPCISD::BCTRL_Darwin" ; case PPCISD :: BCTRL_SVR4 : return "PPCISD::BCTRL_SVR4" ; case PPCISD :: RET_FLAG : return "PPCISD::RET_FLAG" ; case PPCISD :: MFCR : return "PPCISD::MFCR" ; case PPCISD :: VCMP : return "PPCISD::VCMP" ; case PPCISD :: VCMPo : return "PPCISD::VCMPo" ; case PPCISD :: LBRX : return "PPCISD::LBRX" ; case PPCISD :: STBRX : return "PPCISD::STBRX" ; case PPCISD :: LARX : return "PPCISD::LARX" ; case PPCISD :: STCX : return "PPCISD::STCX" ; case PPCISD :: COND_BRANCH : return "PPCISD::COND_BRANCH" ; case PPCISD :: MFFS : return "PPCISD::MFFS" ; case PPCISD :: MTFSB0 : return "PPCISD::MTFSB0" ; case PPCISD :: MTFSB1 : return "PPCISD::MTFSB1" ; case PPCISD :: FADDRTZ : return "PPCISD::FADDRTZ" ; case PPCISD :: MTFSF : return "PPCISD::MTFSF" ; case PPCISD :: TC_RETURN : return "PPCISD::TC_RETURN" ; case PPCISD :: CR6SET : return "PPCISD::CR6SET" ; case PPCISD :: CR6UNSET : return "PPCISD::CR6UNSET" ; case PPCISD :: ADDIS_TOC_HA : return "PPCISD::ADDIS_TOC_HA" ; case PPCISD :: LD_TOC_L : return "PPCISD::LD_TOC_L" ; case PPCISD :: ADDI_TOC_L : return "PPCISD::ADDI_TOC_L" ; case PPCISD :: ADDIS_GOT_TPREL_HA : return "PPCISD::ADDIS_GOT_TPREL_HA" ; case PPCISD :: LD_GOT_TPREL_L : return "PPCISD::LD_GOT_TPREL_L" ; case PPCISD :: ADD_TLS : return "PPCISD::ADD_TLS" ; case PPCISD :: ADDIS_TLSGD_HA : return "PPCISD::ADDIS_TLSGD_HA" ; case PPCISD :: ADDI_TLSGD_L : return "PPCISD::ADDI_TLSGD_L" ; case PPCISD :: GET_TLS_ADDR : return "PPCISD::GET_TLS_ADDR" ; case PPCISD :: ADDIS_TLSLD_HA : return "PPCISD::ADDIS_TLSLD_HA" ; case PPCISD :: ADDI_TLSLD_L : return "PPCISD::ADDI_TLSLD_L" ; case PPCISD :: GET_TLSLD_ADDR : return "PPCISD::GET_TLSLD_ADDR" ; case PPCISD :: ADDIS_DTPREL_HA : return "PPCISD::ADDIS_DTPREL_HA" ; case PPCISD :: ADDI_DTPREL_L : return "PPCISD::ADDI_DTPREL_L" ; } } </s>


<s> static void ix86_sse_copysign_to_positive ( rtx result , rtx abs_value , rtx sign , rtx mask ) { machine_mode mode = GET_MODE ( sign ) ; rtx sgn = gen_reg_rtx ( mode ) ; if ( mask == NULL_RTX ) { machine_mode vmode ; if ( mode == SFmode ) vmode = V4SFmode ; else if ( mode == DFmode ) vmode = V2DFmode ; else vmode = mode ; mask = ix86_build_signbit_mask ( vmode , VECTOR_MODE_P ( mode ) , false ) ; if ( ! VECTOR_MODE_P ( mode ) ) { rtx tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 1 , const0_rtx ) ) ; tmp = gen_rtx_VEC_SELECT ( mode , mask , tmp ) ; mask = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( mask , tmp ) ) ; } } else mask = gen_rtx_NOT ( mode , mask ) ; emit_insn ( gen_rtx_SET ( sgn , gen_rtx_AND ( mode , mask , sign ) ) ) ; emit_insn ( gen_rtx_SET ( result , gen_rtx_IOR ( mode , abs_value , sgn ) ) ) ; } </s>

Expand copysign from SIGN to the positive value ABS_VALUE storing in RESULT . If MASK is non-null , it shall be a mask to mask out the sign-bit .


"value of -mfixed-range must have form REG1-REG2"

Parse the -mfixed-range= option string .


"optionally flag setting instruction missing optional def operand"

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


<s> const RISCVInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> static bool aarch64_hard_regno_call_part_clobbered ( rtx_insn * insn , unsigned int regno , machine_mode mode ) { bool simd_p = insn && CALL_P ( insn ) && aarch64_simd_call_p ( insn ) ; return FP_REGNUM_P ( regno ) && maybe_gt ( GET_MODE_SIZE ( mode ) , simd_p ? 16 : 8 ) ; } </s>

Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED . The callee only saves the lower 64 bits of a 128-bit register . Tell the compiler the callee clobbers the top 64 bits when restoring the bottom 64 bits .


<s>
const
char
*
nds32_output_16bit_load
(
rtx
*
operands
,
int
byte
)
{
char
pattern
[
100
]
;
unsigned
char
size
;
rtx
code
=
XEXP
(
operands
[
1
]
,
0
)
;
size
=
nds32_byte_to_size
(
byte
)
;
switch
(
nds32_mem_format
(
operands
[
1
]
)
)
{
case
ADDRESS_REG
:
operands
[
1
]
=
code
;
output_asm_insn
(
"lwi450\t%0, [%1]"
,
operands
)
;
break
;
case
ADDRESS_LO_REG_IMM3U
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%ci333\t%%0, %%1"
,
size
)
;
output_asm_insn
(
pattern
,
operands
)
;
break
;
case
ADDRESS_POST_INC_LO_REG_IMM3U
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%ci333.bi\t%%0, %%1"
,
size
)
;
output_asm_insn
(
pattern
,
operands
)
;
break
;
case
ADDRESS_FP_IMM7U
:
output_asm_insn
(
"lwi37\t%0, %1"
,
operands
)
;
break
;
case
ADDRESS_SP_IMM7U
:
operands
[
1
]
=
XEXP
(
code
,
1
)
;
output_asm_insn
(
"lwi37.sp\t%0, [ + (%1)]"
,
operands
)
;
break
;
default
:
break
;
}
return
""
;
}
</s>


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & OS ) { if ( CommentStream ) HasCustomInstComment = EmitAnyX86InstComments ( MI , * CommentStream , MII ) ; printInstFlags ( MI , OS ) ; if ( MI -> getOpcode ( ) == X86 :: CALLpcrel32 && ( STI . getFeatureBits ( ) [ X86 :: Mode64Bit ] ) ) { OS << "\tcallq\t" ; printPCRelImm ( MI , Address , 0 , OS ) ; } else if ( MI -> getOpcode ( ) == X86 :: DATA16_PREFIX && STI . getFeatureBits ( ) [ X86 :: Mode16Bit ] ) { OS << "\tdata32" ; } else if ( ! printAliasInstr ( MI , Address , OS ) && ! printVecCompareInstr ( MI , OS ) ) printInstruction ( MI , Address , OS ) ; printAnnotation ( OS , Annot ) ; } </s>


<s>
bool
X86CmovConverterPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
if
(
!
EnableCmovConverter
)
return
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"********** "
<<
getPassName
(
)
<<
" : "
<<
MF
.
getName
(
)
<<
"**********\n"
)
;
bool
Changed
=
false
;
MachineLoopInfo
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
const
TargetSubtargetInfo
&
STI
=
MF
.
getSubtarget
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
TII
=
STI
.
getInstrInfo
(
)
;
TRI
=
STI
.
getRegisterInfo
(
)
;
TSchedModel
.
init
(
&
STI
)
;
if
(
ForceMemOperand
)
{
CmovGroups
AllCmovGroups
;
SmallVector
<
MachineBasicBlock
*
,
4
>
Blocks
;
for
(
auto
&
MBB
:
MF
)
Blocks
.
push_back
(
&
MBB
)
;
if
(
collectCmovCandidates
(
Blocks
,
AllCmovGroups
,
true
)
)
{
for
(
auto
&
Group
:
AllCmovGroups
)
{
if
(
!
llvm
::
any_of
(
Group
,
[
&
]
(
MachineInstr
*
I
)
{
return
I
->
mayLoad
(
)
;
}
)
)
continue
;
Changed
=
true
;
convertCmovInstsToBranches
(
Group
)
;
}
}
}
SmallVector
<
MachineLoop
*
,
4
>
Loops
(
MLI
.
begin
(
)
,
MLI
.
end
(
)
)
;
for
(
int
i
=
0
;
i
<
(
int
)
Loops
.
size
(
)
;
++
i
)
for
(
MachineLoop
*
Child
:
Loops
[
i
]
->
getSubLoops
(
)
)
Loops
.
push_back
(
Child
)
;
for
(
MachineLoop
*
CurrLoop
:
Loops
)
{
if
(
!
CurrLoop
->
getSubLoops
(
)
.
empty
(
)
)
continue
;
CmovGroups
CmovInstGroups
;
if
(
!
collectCmovCandidates
(
CurrLoop
->
getBlocks
(
)
,
CmovInstGroups
)
)
continue
;
if
(
!
checkForProfitableCmovCandidates
(
CurrLoop
->
getBlocks
(
)
,
CmovInstGroups
)
)
continue
;
Changed
=
true
;
for
(
auto
&
Group
:
CmovInstGroups
)
convertCmovInstsToBranches
(
Group
)
;
}
return
Changed
;
}
</s>


<s> TargetLowering :: ConstraintType SystemZTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'a' : case 'd' : case 'f' : case 'h' : case 'r' : case 'v' : return C_RegisterClass ; case 'Q' : case 'R' : case 'S' : case 'T' : case 'm' : return C_Memory ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : return C_Immediate ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>


"Couldn't get MachineMemOperand for store to stack."

"Only support 4-byte stores to stack now."

"Only support GPR32 stores to stack now."

Store the specified register of the given register class to the specified stack frame index .


<s> SDNode * SITargetLowering :: PostISelFolding ( MachineSDNode * Node , SelectionDAG & DAG ) const { const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( getTargetMachine ( ) . getInstrInfo ( ) ) ; Node = AdjustRegClass ( Node , DAG ) ; if ( TII -> isMIMG ( Node -> getMachineOpcode ( ) ) ) adjustWritemask ( Node , DAG ) ; return foldOperands ( Node , DAG ) ; } </s>

Fold the instructions after selecting them .


<s> bool RISCVExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const RISCVInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; bool Modified = false ; for ( auto & MBB : MF ) Modified |= expandMBB ( MBB ) ; return Modified ; } </s>


<s> AArch64DCFunction & getParent ( ) { return static_cast < AArch64DCFunction & > ( DCBasicBlock :: getParent ( ) ) ; } </s>

getParent - Return the last analyzed interval .


<s> static MCAsmInfo * createMCAsmInfo ( const Target & T , StringRef TT ) { Triple TheTriple ( TT ) ; bool isPPC64 = TheTriple . getArch ( ) == Triple :: ppc64 ; if ( TheTriple . getOS ( ) == Triple :: Darwin ) return new PPCMCAsmInfoDarwin ( isPPC64 ) ; return new PPCLinuxMCAsmInfo ( isPPC64 ) ; } </s>

createMCAsmInfo - Create a MCAsmInfo implementation for the specified target triple .


<s> int rbt_insert ( struct rbt_strings * t , char * str ) { struct rbt_string_node * curr = t -> rbt_root ; struct rbt_string_node * trail = t -> rbt_nil ; while ( curr != t -> rbt_nil ) { trail = curr ; int cmp = strcmp ( str , curr -> str ) ; if ( cmp < 0 ) curr = curr -> left ; else if ( cmp > 0 ) curr = curr -> right ; else return 0 ; } struct rbt_string_node * fresh = rbt_create_node ( t , str ) ; fresh -> par = trail ; if ( trail == t -> rbt_nil ) t -> rbt_root = fresh ; else if ( strcmp ( fresh -> str , trail -> str ) < 0 ) trail -> left = fresh ; else trail -> right = fresh ; fresh -> left = t -> rbt_nil ; fresh -> right = t -> rbt_nil ; curr = fresh ; while ( curr -> par -> color == RBT_RED ) if ( curr -> par == curr -> par -> par -> left ) { struct rbt_string_node * uncle = curr -> par -> par -> right ; if ( uncle -> color == RBT_RED ) { curr -> par -> color = RBT_BLACK ; uncle -> color = RBT_BLACK ; curr -> par -> par -> color = RBT_RED ; curr = curr -> par -> par ; } else if ( curr == curr -> par -> right ) { curr = curr -> par ; rbt_left_rotate ( t , curr ) ; } else { curr -> par -> color = RBT_BLACK ; curr -> par -> par -> color = RBT_RED ; rbt_right_rotate ( t , curr -> par -> par ) ; } } else { struct rbt_string_node * aunt = curr -> par -> par -> left ; if ( aunt -> color == RBT_RED ) { curr -> par -> color = RBT_BLACK ; aunt -> color = RBT_BLACK ; curr -> par -> par -> color = RBT_RED ; curr = curr -> par -> par ; } else if ( curr == curr -> par -> left ) { curr = curr -> par ; rbt_right_rotate ( t , curr ) ; } else { curr -> par -> color = RBT_BLACK ; curr -> par -> par -> color = RBT_RED ; rbt_left_rotate ( t , curr -> par -> par ) ; } } t -> rbt_root -> color = RBT_BLACK ; return 1 ; } </s>

Insert STR into the tree , returning 1 for success and 0 if STR already appears in the tree .


<s> bool RISCVTargetLowering :: isDesirableToCommuteWithShift ( const SDNode * N , CombineLevel Level ) const { SDValue N0 = N -> getOperand ( 0 ) ; EVT Ty = N0 . getValueType ( ) ; if ( Ty . isScalarInteger ( ) && ( N0 . getOpcode ( ) == ISD :: ADD || N0 . getOpcode ( ) == ISD :: OR ) ) { auto * C1 = dyn_cast < ConstantSDNode > ( N0 -> getOperand ( 1 ) ) ; auto * C2 = dyn_cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) ; if ( C1 && C2 ) { APInt C1Int = C1 -> getAPIntValue ( ) ; APInt ShiftedC1Int = C1Int << C2 -> getAPIntValue ( ) ; if ( ShiftedC1Int . getMinSignedBits ( ) <= 64 && isLegalAddImmediate ( ShiftedC1Int . getSExtValue ( ) ) ) return true ; if ( C1Int . getMinSignedBits ( ) <= 64 && isLegalAddImmediate ( C1Int . getSExtValue ( ) ) ) return false ; int C1Cost = RISCVMatInt :: getIntMatCost ( C1Int , Ty . getSizeInBits ( ) , Subtarget . is64Bit ( ) ) ; int ShiftedC1Cost = RISCVMatInt :: getIntMatCost ( ShiftedC1Int , Ty . getSizeInBits ( ) , Subtarget . is64Bit ( ) ) ; if ( C1Cost < ShiftedC1Cost ) return false ; } } return true ; } </s>

Return true if it is profitable to move this shift by a constant amount through its operand , adjusting any immediate operands as necessary to preserve semantics .


<s> bool AArch64InstrInfo :: isPreLdSt ( const MachineInstr & MI ) { return isPreLd ( MI ) || isPreSt ( MI ) ; } </s>

Returns whether the instruction is a pre-indexed load/store .


<s> static machine_mode loongarch_promote_function_mode ( const_tree type ATTRIBUTE_UNUSED , machine_mode mode , int * punsignedp ATTRIBUTE_UNUSED , const_tree fntype ATTRIBUTE_UNUSED , int for_return ATTRIBUTE_UNUSED ) { int unsignedp ; if ( type != NULL_TREE ) return promote_mode ( type , mode , punsignedp ) ; unsignedp = * punsignedp ; PROMOTE_MODE ( mode , unsignedp , type ) ; * punsignedp = unsignedp ; return mode ; } </s>


"shouldAssumeDSOLocal gave inconsistent answer"

Classify a global function reference for the current subtarget .


<s> static tree ix86_handle_tm_regparm_attribute ( tree * node , tree , tree , int flags , bool * no_add_attrs ) { tree alt ; * no_add_attrs = true ; if ( TARGET_64BIT ) return NULL_TREE ; if ( CHECK_STACK_LIMIT > 0 ) alt = tree_cons ( get_identifier ( "fastcall" ) , NULL , NULL ) ; else { alt = tree_cons ( NULL , build_int_cst ( NULL , 2 ) , NULL ) ; alt = tree_cons ( get_identifier ( "regparm" ) , alt , NULL ) ; } decl_attributes ( node , alt , flags ) ; return NULL_TREE ; } </s>

The transactional memory builtins are implicitly regparm or fastcall depending on the ABI . Override the generic do-nothing attribute that these builtins were declared with , and replace it with one of the two attributes that we expect elsewhere .


<s> void SITargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { if ( isImmConstraint ( Constraint ) ) { uint64_t Val ; if ( getAsmOperandConstVal ( Op , Val ) && checkAsmConstraintVal ( Op , Constraint , Val ) ) { Val = clearUnusedBits ( Val , Op . getScalarValueSizeInBits ( ) ) ; Ops . push_back ( DAG . getTargetConstant ( Val , SDLoc ( Op ) , MVT :: i64 ) ) ; } } else { TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; } } </s>

Lower the specified operand into the Ops vector .


<s>
const
char
*
output_ubranch
(
rtx
dest
,
int
label
,
rtx
insn
)
{
static
char
string
[
64
]
;
bool
v9_form
=
false
;
char
*
p
;
if
(
TARGET_V9
&&
INSN_ADDRESSES_SET_P
(
)
)
{
int
delta
=
(
INSN_ADDRESSES
(
INSN_UID
(
dest
)
)
INSN_ADDRESSES
(
INSN_UID
(
insn
)
)
)
;
if
(
delta
>=
260000
&&
delta
<
260000
)
v9_form
=
true
;
}
if
(
v9_form
)
strcpy
(
string
,
"ba%*,pt\t%%xcc, "
)
;
else
strcpy
(
string
,
"b%*\t"
)
;
p
=
strchr
(
string
,
'\0'
)
;
*
p
++
=
'%'
;
*
p
++
=
'l'
;
*
p
++
=
'0'
+
label
;
*
p
++
=
'%'
;
*
p
++
=
'('
;
*
p
=
'\0'
;
return
string
;
}
</s>

Output an unconditional branch to LABEL . INSN is the instruction .


<s> const Z80RegisterInfo * getRegisterInfo ( ) const override { return & getInstrInfo ( ) -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"XCore Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static machine_mode rs6000_c_mode_for_suffix ( char suffix ) { if ( TARGET_FLOAT128_TYPE ) { if ( suffix == 'q' || suffix == 'Q' ) return ( FLOAT128_IEEE_P ( TFmode ) ) ? TFmode : KFmode ; } return VOIDmode ; } </s>


<s> static void loongarch_print_operand_reloc ( FILE * file , rtx op , bool hi64_part , bool hi_reloc ) { const char * reloc ; enum loongarch_symbol_type symbol_type = loongarch_classify_symbolic_expression ( op ) ; if ( loongarch_symbol_extreme_p ( symbol_type ) ) gcc_assert ( TARGET_EXPLICIT_RELOCS ) ; switch ( symbol_type ) { case SYMBOL_PCREL64 : if ( hi64_part ) { reloc = hi_reloc ? "%pc64_hi12" : "%pc64_lo20" ; break ; } case SYMBOL_PCREL : reloc = hi_reloc ? "%pc_hi20" : "%pc_lo12" ; break ; case SYMBOL_GOT_DISP : if ( hi64_part ) { if ( TARGET_CMODEL_EXTREME ) reloc = hi_reloc ? "%got64_pc_hi12" : "%got64_pc_lo20" ; else gcc_unreachable ( ) ; } else reloc = hi_reloc ? "%got_pc_hi20" : "%got_pc_lo12" ; break ; case SYMBOL_TLS_IE : if ( hi64_part ) { if ( TARGET_CMODEL_EXTREME ) reloc = hi_reloc ? "%ie64_pc_hi12" : "%ie64_pc_lo20" ; else gcc_unreachable ( ) ; } else reloc = hi_reloc ? "%ie_pc_hi20" : "%ie_pc_lo12" ; break ; case SYMBOL_TLS_LE : if ( hi64_part ) { if ( TARGET_CMODEL_EXTREME ) reloc = hi_reloc ? "%le64_hi12" : "%le64_lo20" ; else gcc_unreachable ( ) ; } else reloc = hi_reloc ? "%le_hi20" : "%le_lo12" ; break ; case SYMBOL_TLSGD : if ( hi64_part ) { if ( TARGET_CMODEL_EXTREME ) reloc = hi_reloc ? "%got64_pc_hi12" : "%got64_pc_lo20" ; else gcc_unreachable ( ) ; } else reloc = hi_reloc ? "%gd_pc_hi20" : "%got_pc_lo12" ; break ; case SYMBOL_TLSLDM : if ( hi64_part ) { if ( TARGET_CMODEL_EXTREME ) reloc = hi_reloc ? "%got64_pc_hi12" : "%got64_pc_lo20" ; else gcc_unreachable ( ) ; } else reloc = hi_reloc ? "%ld_pc_hi20" : "%got_pc_lo12" ; break ; default : gcc_unreachable ( ) ; } fprintf ( file , "%s(" , reloc ) ; output_addr_const ( file , loongarch_strip_unspec_address ( op ) ) ; fputc ( ')' , file ) ; } </s>

Print symbolic operand OP , which is part of a HIGH or LO_SUM in context CONTEXT . HI_RELOC indicates a high-part reloc .


<s>
void
dump
(
)
{
errs
(
)
<<
"KudeyarISelAddressMode "
<<
this
<<
'\n'
;
if
(
BaseType
==
RegBase
&&
Base
.
Reg
.
getNode
(
)
!=
0
)
{
errs
(
)
<<
"Base.Reg "
;
Base
.
Reg
.
getNode
(
)
->
dump
(
)
;
}
else
if
(
BaseType
==
FrameIndexBase
)
{
errs
(
)
<<
" Base.FrameIndex "
<<
Base
.
FrameIndex
<<
'\n'
;
}
errs
(
)
<<
" Disp "
<<
Disp
<<
'\n'
;
if
(
GV
)
{
errs
(
)
<<
"GV "
;
GV
->
dump
(
)
;
}
else
if
(
CP
)
{
errs
(
)
<<
" CP "
;
CP
->
dump
(
)
;
errs
(
)
<<
" Align"
<<
Align
<<
'\n'
;
}
else
if
(
ES
)
{
errs
(
)
<<
"ES "
;
errs
(
)
<<
ES
<<
'\n'
;
}
else
if
(
JT
!=
1
)
errs
(
)
<<
" JT"
<<
JT
<<
" Align"
<<
Align
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

Kudeyar
"KudeyarISelAddressMode "
0
"Base.Reg "
" Base.FrameIndex "
" Disp "
"GV "
" CP "
" Align"
"ES "
1
" JT"
" Align"


<s> bool ARMTargetLowering :: shouldFoldConstantShiftPairToMask ( const SDNode * N , CombineLevel Level ) const { if ( ! Subtarget -> isThumb1Only ( ) ) return true ; if ( Level == BeforeLegalizeTypes ) return true ; return false ; } </s>

Return true if it is profitable to fold a pair of shifts into a mask .


<s>
void
SIFrameLowering
::
processFunctionBeforeFrameFinalized
(
MachineFunction
&
MF
,
RegScavenger
*
RS
)
const
{
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
if
(
!
MFI
.
hasStackObjects
(
)
)
return
;
bool
MayNeedScavengingEmergencySlot
=
MFI
.
hasStackObjects
(
)
;
assert
(
(
RS
||
!
MayNeedScavengingEmergencySlot
)
&&
"RegScavenger required if spilling"
)
;
if
(
MayNeedScavengingEmergencySlot
)
{
int
ScavengeFI
=
MFI
.
CreateStackObject
(
AMDGPU
::
SGPR_32RegClass
.
getSize
(
)
,
AMDGPU
::
SGPR_32RegClass
.
getAlignment
(
)
,
false
)
;
RS
->
addScavengingFrameIndex
(
ScavengeFI
)
;
}
}
</s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> SDValue NVPTXTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , DebugLoc dl , SelectionDAG & DAG ) const { bool isABI = ( nvptxSubtarget . getSmVersion ( ) >= 20 ) ; unsigned sizesofar = 0 ; unsigned idx = 0 ; for ( unsigned i = 0 , e = Outs . size ( ) ; i != e ; ++ i ) { SDValue theVal = OutVals [ i ] ; EVT theValType = theVal . getValueType ( ) ; unsigned numElems = 1 ; if ( theValType . isVector ( ) ) numElems = theValType . getVectorNumElements ( ) ; for ( unsigned j = 0 , je = numElems ; j != je ; ++ j ) { SDValue tmpval = theVal ; if ( theValType . isVector ( ) ) tmpval = DAG . getNode ( ISD :: EXTRACT_VECTOR_ELT , dl , theValType . getVectorElementType ( ) , tmpval , DAG . getIntPtrConstant ( j ) ) ; Chain = DAG . getNode ( isABI ? NVPTXISD :: StoreRetval : NVPTXISD :: MoveToRetval , dl , MVT :: Other , Chain , DAG . getConstant ( isABI ? sizesofar : idx , MVT :: i32 ) , tmpval ) ; if ( theValType . isVector ( ) ) sizesofar += theValType . getVectorElementType ( ) . getStoreSizeInBits ( ) / 8 ; else sizesofar += theValType . getStoreSizeInBits ( ) / 8 ; ++ idx ; } } return DAG . getNode ( NVPTXISD :: RET_FLAG , dl , MVT :: Other , Chain ) ; } </s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s>
static
void
write_worker_buffer
(
FILE
*
file
,
rtx
sym
,
unsigned
align
,
unsigned
size
)
{
const
char
*
name
=
XSTR
(
sym
,
0
)
;
write_var_marker
(
file
,
true
,
false
,
name
)
;
fprintf
(
file
,
".shared .align %d .u8 %s[%d];\n"
,
align
,
name
,
size
)
;
}
</s>

Emit a declaration for a worker-level buffer in .shared memory .

nvptx
0
".shared .align %d .u8 %s[%d];\n"


<s> bool X86CondBrFoldingPass :: runOnMachineFunction ( MachineFunction & MF ) { const X86Subtarget & ST = MF . getSubtarget < X86Subtarget > ( ) ; if ( ! ST . threewayBranchProfitable ( ) ) return false ; const X86InstrInfo * TII = ST . getInstrInfo ( ) ; const MachineBranchProbabilityInfo * MBPI = & getAnalysis < MachineBranchProbabilityInfo > ( ) ; X86CondBrFolding CondBr ( TII , MBPI , MF ) ; return CondBr . optimize ( ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> int rbt_find ( struct rbt_strings * t , char * str ) { struct rbt_string_node * curr = t -> rbt_root ; while ( curr != t -> rbt_nil ) { int cmp = strcmp ( str , curr -> str ) ; if ( cmp < 0 ) curr = curr -> left ; else if ( cmp > 0 ) curr = curr -> right ; else return 1 ; } return 0 ; } </s>

Return 1 if STR is in the red-black tree , else 0 .


<s> void pass_shorten_memrefs :: transform ( regno_map * m , basic_block bb ) { rtx_insn * insn ; FOR_BB_INSNS ( bb , insn ) { if ( ! NONJUMP_INSN_P ( insn ) ) continue ; rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) != SET ) continue ; start_sequence ( ) ; for ( int i = 0 ; i < 2 ; i ++ ) { rtx mem = XEXP ( pat , i ) ; rtx addr ; bool extend = false ; if ( get_si_mem_base_reg ( mem , & addr , & extend ) ) { HOST_WIDE_INT regno = REGNO ( XEXP ( addr , 0 ) ) ; if ( i == 0 ) { if ( XEXP ( pat , 1 ) == CONST0_RTX ( GET_MODE ( XEXP ( pat , 1 ) ) ) ) continue ; } if ( m -> get_or_insert ( regno ) > 3 ) { if ( extend ) { addr = targetm . legitimize_address ( addr , addr , GET_MODE ( XEXP ( mem , 0 ) ) ) ; XEXP ( XEXP ( pat , i ) , 0 ) = replace_equiv_address ( XEXP ( mem , 0 ) , addr ) ; } else { addr = targetm . legitimize_address ( addr , addr , GET_MODE ( mem ) ) ; XEXP ( pat , i ) = replace_equiv_address ( mem , addr ) ; } df_insn_rescan ( insn ) ; } } } rtx_insn * seq = get_insns ( ) ; end_sequence ( ) ; emit_insn_before ( seq , insn ) ; } } </s>

Convert BASE + LARGE_OFFSET to NEW_BASE + SMALL_OFFSET for each load/store with a base reg referenced at least 4 times .


<s> bool AlphaRegisterInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MFI -> hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
void
SIInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
SIMachineFunctionInfo
*
MFI
=
MF
->
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MachineFrameInfo
&
FrameInfo
=
MF
->
getFrameInfo
(
)
;
const
DebugLoc
&
DL
=
MBB
.
findDebugLoc
(
MI
)
;
unsigned
Size
=
FrameInfo
.
getObjectSize
(
FrameIndex
)
;
unsigned
Align
=
FrameInfo
.
getObjectAlignment
(
FrameIndex
)
;
MachinePointerInfo
PtrInfo
=
MachinePointerInfo
::
getFixedStack
(
*
MF
,
FrameIndex
)
;
MachineMemOperand
*
MMO
=
MF
->
getMachineMemOperand
(
PtrInfo
,
MachineMemOperand
::
MOStore
,
Size
,
Align
)
;
unsigned
SpillSize
=
TRI
->
getSpillSize
(
*
RC
)
;
if
(
RI
.
isSGPRClass
(
RC
)
)
{
MFI
->
setHasSpilledSGPRs
(
)
;
const
MCInstrDesc
&
OpDesc
=
get
(
getSGPRSpillSaveOpcode
(
SpillSize
)
)
;
if
(
TargetRegisterInfo
::
isVirtualRegister
(
SrcReg
)
&&
SpillSize
==
4
)
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
MRI
.
constrainRegClass
(
SrcReg
,
&
AMDGPU
::
SReg_32_XM0RegClass
)
;
}
MachineInstrBuilder
Spill
=
BuildMI
(
MBB
,
MI
,
DL
,
OpDesc
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIndex
)
.
addMemOperand
(
MMO
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
,
RegState
::
Implicit
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
,
RegState
::
Implicit
)
;
FrameInfo
.
setStackID
(
FrameIndex
,
SIStackID
::
SGPR_SPILL
)
;
if
(
ST
.
hasScalarStores
(
)
)
{
Spill
.
addReg
(
AMDGPU
::
M0
,
RegState
::
ImplicitDefine
|
RegState
::
Dead
)
;
}
return
;
}
assert
(
RI
.
hasVGPRs
(
RC
)
&&
"Only VGPR spilling expected"
)
;
unsigned
Opcode
=
getVGPRSpillSaveOpcode
(
SpillSize
)
;
MFI
->
setHasSpilledVGPRs
(
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opcode
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIndex
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> EVT AArch64TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , const AttributeList & FuncAttributes ) const { bool CanImplicitFloat = ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; bool CanUseNEON = Subtarget -> hasNEON ( ) && CanImplicitFloat ; bool CanUseFP = Subtarget -> hasFPARMv8 ( ) && CanImplicitFloat ; bool IsSmallMemset = IsMemset && Size < 32 ; auto AlignmentIsAcceptable = [ & ] ( EVT VT , unsigned AlignCheck ) { if ( memOpAlign ( SrcAlign , DstAlign , AlignCheck ) ) return true ; bool Fast ; return allowsMisalignedMemoryAccesses ( VT , 0 , 1 , & Fast ) && Fast ; } ; if ( CanUseNEON && IsMemset && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: v2i64 , 16 ) ) return MVT :: v2i64 ; if ( CanUseFP && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: f128 , 16 ) ) return MVT :: f128 ; if ( Size >= 8 && AlignmentIsAcceptable ( MVT :: i64 , 8 ) ) return MVT :: i64 ; if ( Size >= 4 && AlignmentIsAcceptable ( MVT :: i32 , 4 ) ) return MVT :: i32 ; return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


"Cannot store this register into a stack slot!"


<s>
static
tree
lookup_sve_type_attribute
(
const_tree
type
)
{
if
(
type
==
error_mark_node
)
return
NULL_TREE
;
return
lookup_attribute
(
"SVE type"
,
TYPE_ATTRIBUTES
(
type
)
)
;
}
</s>

If TYPE is an ABI-defined SVE type , return its attribute descriptor , otherwise return null .


<s> static void ix86_setup_incoming_varargs ( cumulative_args_t cum_v , const function_arg_info & arg , int * , int no_rtl ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; CUMULATIVE_ARGS next_cum ; tree fntype ; gcc_assert ( ! no_rtl ) ; if ( ! TARGET_64BIT ) return ; fntype = TREE_TYPE ( current_function_decl ) ; next_cum = * cum ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) && stdarg_p ( fntype ) ) ix86_function_arg_advance ( pack_cumulative_args ( & next_cum ) , arg ) ; if ( cum -> call_abi == MS_ABI ) setup_incoming_varargs_ms_64 ( & next_cum ) ; else setup_incoming_varargs_64 ( & next_cum ) ; } </s>

Worker function for TARGET_SETUP_INCOMING_VARARGS .


<s> const char * mcore_output_bseti ( rtx dst , int mask ) { rtx out_operands [ 2 ] ; int bit ; out_operands [ 0 ] = dst ; for ( bit = 0 ; bit < 32 ; bit ++ ) { if ( ( mask & 0x1 ) == 0x1 ) { out_operands [ 1 ] = GEN_INT ( bit ) ; output_asm_insn ( "bseti\t%0,%1" , out_operands ) ; } mask >>= 1 ; } return "" ; } </s>

Output a series of bseti 's corresponding to mask .


<s>
void
HexagonDCE
::
removeOperand
(
NodeAddr
<
InstrNode
*
>
IA
,
unsigned
OpNum
)
{
MachineInstr
*
MI
=
NodeAddr
<
StmtNode
*
>
(
IA
)
.
Addr
->
getCode
(
)
;
auto
getOpNum
=
[
MI
]
(
MachineOperand
&
Op
)
->
unsigned
{
for
(
unsigned
i
=
0
,
n
=
MI
->
getNumOperands
(
)
;
i
!=
n
;
++
i
)
if
(
&
MI
->
getOperand
(
i
)
==
&
Op
)
return
i
;
llvm_unreachable
(
"Invalid operand"
)
;
}
;
DenseMap
<
NodeId
,
unsigned
>
OpMap
;
DataFlowGraph
&
DFG
=
getDFG
(
)
;
NodeList
Refs
=
IA
.
Addr
->
members
(
DFG
)
;
for
(
NodeAddr
<
RefNode
*
>
RA
:
Refs
)
OpMap
.
insert
(
std
::
make_pair
(
RA
.
Id
,
getOpNum
(
RA
.
Addr
->
getOp
(
)
)
)
)
;
MI
->
RemoveOperand
(
OpNum
)
;
for
(
NodeAddr
<
RefNode
*
>
RA
:
Refs
)
{
unsigned
N
=
OpMap
[
RA
.
Id
]
;
if
(
N
<
OpNum
)
RA
.
Addr
->
setRegRef
(
&
MI
->
getOperand
(
N
)
,
DFG
)
;
else
if
(
N
>
OpNum
)
RA
.
Addr
->
setRegRef
(
&
MI
->
getOperand
(
N
1
)
,
DFG
)
;
}
}
</s>

Erase an operand from an instruction , leaving it with one fewer operand than it started with .


<s>
bool
WebAssemblyCFGSort
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"********** CFG Sorting **********\n"
"********** Function: "
<<
MF
.
getName
(
)
<<
'\n'
)
;
const
auto
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
const
auto
&
WEI
=
getAnalysis
<
WebAssemblyExceptionInfo
>
(
)
;
auto
&
MDT
=
getAnalysis
<
MachineDominatorTree
>
(
)
;
MF
.
getRegInfo
(
)
.
invalidateLiveness
(
)
;
SortBlocks
(
MF
,
MLI
,
WEI
,
MDT
)
;
return
true
;
}
</s>

WebAssembly
WebAssembly
"********** CFG Sorting **********\n"
"********** Function: "
WebAssembly


<s> bool X86FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( MI ) ; if ( MBB . isEHFuncletEntry ( ) && STI . is32Bit ( ) && STI . isOSWindows ( ) ) return true ; const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Opc = STI . is64Bit ( ) ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( const CalleeSavedInfo & I : llvm :: reverse ( CSI ) ) { Register Reg = I . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool isLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! isLiveIn ) MBB . addLiveIn ( Reg ) ; bool CanKill = ! isLiveIn ; if ( CanKill ) { for ( MCRegAliasIterator AReg ( Reg , TRI , false ) ; AReg . isValid ( ) ; ++ AReg ) { if ( MRI . isLiveIn ( * AReg ) ) { CanKill = false ; break ; } } } BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , getKillRegState ( CanKill ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( const CalleeSavedInfo & I : llvm :: reverse ( CSI ) ) { Register Reg = I . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MVT VT = MVT :: Other ; if ( X86 :: VK16RegClass . contains ( Reg ) ) VT = STI . hasBWI ( ) ? MVT :: v64i1 : MVT :: v16i1 ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg , VT ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , I . getFrameIdx ( ) , RC , TRI ) ; -- MI ; MI -> setFlag ( MachineInstr :: FrameSetup ) ; ++ MI ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s>
void
execute_tag_collision_avoidance
(
)
{
struct
loop
*
loop
;
df_set_flags
(
DF_RD_PRUNE_DEAD_DEFS
)
;
df_chain_add_problem
(
DF_UD_CHAIN
)
;
df_compute_regs_ever_live
(
true
)
;
df_note_add_problem
(
)
;
df_analyze
(
)
;
df_set_flags
(
DF_DEFER_INSN_RESCAN
)
;
regrename_init
(
true
)
;
regrename_analyze
(
)
;
compute_bb_for_insn
(
)
;
calculate_dominance_info
(
CDI_DOMINATORS
)
;
loop_optimizer_init
(
AVOID_CFG_MODIFICATIONS
)
;
FOR_EACH_LOOP
(
loop
,
LI_FROM_INNERMOST
)
{
tag_map_t
tag_map
(
512
)
;
record_loads
(
tag_map
,
loop
)
;
avoid_collisions
(
tag_map
)
;
if
(
dump_file
)
{
fprintf
(
dump_file
,
"Loop %d: Completed rename.\n"
,
loop
->
num
)
;
tag_map
.
traverse
<
void
*
,
dump_insn_list
>
(
)
;
}
tag_map
.
traverse
<
void
*
,
free_insn_info
>
(
)
;
}
loop_optimizer_finalize
(
)
;
free_dominance_info
(
CDI_DOMINATORS
)
;
regrename_finish
(
)
;
}
</s>

Tag collision avoidance pass for Falkor . The pass runs in two phases for each loop ; the first phase collects all loads that we consider as interesting for renaming into a tag-indexed map of lists . The second phase renames the destination register of the loads in an attempt to spread out the loads into different tags .


<s> int cpat_const_p ( rtx x , machine_mode mode ) { if ( CONSTANT_P ( x ) ) { enum immediate_class c = classify_immediate ( x , mode ) ; return c == IC_CPAT ; } return 0 ; } </s>

Return TRUE if x is a CONST_INT , CONST_DOUBLE or CONST_VECTOR that can be generated using the cbd , chd , cwd or cdd instruction .


<s> static bool s390_lra_p ( void ) { return s390_lra_flag ; } </s>

Return true if we use LRA instead of reload pass .


<s> void Z80InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s>
bool
MOSStaticStackAlloc
::
runOnModule
(
Module
&
M
)
{
MachineModuleInfo
&
MMI
=
getAnalysis
<
MachineModuleInfoWrapperPass
>
(
)
.
getMMI
(
)
;
bool
Changed
=
false
;
for
(
Function
&
F
:
M
)
{
MachineFunction
*
MF
=
MMI
.
getMachineFunction
(
F
)
;
if
(
!
MF
)
continue
;
const
MOSFrameLowering
&
TFL
=
*
MF
->
getSubtarget
<
MOSSubtarget
>
(
)
.
getFrameLowering
(
)
;
uint64_t
Size
=
TFL
.
staticSize
(
MF
->
getFrameInfo
(
)
)
;
if
(
!
Size
)
continue
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Found static stack for "
<<
F
.
getName
(
)
<<
"\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Size "
<<
Size
<<
"\n"
)
;
Type
*
Typ
=
ArrayType
::
get
(
Type
::
getInt8Ty
(
M
.
getContext
(
)
)
,
Size
)
;
GlobalVariable
*
Stack
=
new
GlobalVariable
(
M
,
Typ
,
false
,
GlobalValue
::
PrivateLinkage
,
UndefValue
::
get
(
Typ
)
,
Twine
(
F
.
getName
(
)
)
+
"_sstk"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Allocated: "
<<
*
Stack
<<
"\n"
)
;
Changed
=
true
;
MOSFunctionInfo
&
MFI
=
*
MF
->
getInfo
<
MOSFunctionInfo
>
(
)
;
MFI
.
setStaticStackVariable
(
Stack
)
;
for
(
MachineBasicBlock
&
MBB
:
*
MF
)
{
for
(
MachineInstr
&
MI
:
MBB
)
{
for
(
MachineOperand
&
MO
:
MI
.
operands
(
)
)
{
if
(
!
MO
.
isTargetIndex
(
)
)
continue
;
MO
.
ChangeToGA
(
Stack
,
MO
.
getOffset
(
)
,
MO
.
getTargetFlags
(
)
)
;
}
}
}
}
return
Changed
;
}
</s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .

MOS
MOS
MOS
MOS
"Found static stack for "
"\n"
"Size "
"\n"
"_sstk"
"Allocated: "
"\n"
MOS
MOS


<s>
bool
SystemZDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
char
ConstraintCode
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
assert
(
ConstraintCode
==
'm'
&&
"Unexpected constraint code"
)
;
SDValue
Base
,
Disp
,
Index
;
if
(
!
selectBDXAddr
(
SystemZAddressingMode
::
FormBD
,
SystemZAddressingMode
::
Disp12Only
,
Op
,
Base
,
Disp
,
Index
)
)
return
true
;
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Disp
)
;
OutOps
.
push_back
(
Index
)
;
return
false
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .

SystemZ
SystemZ
"Unexpected constraint code"
SystemZAddressingMode::FormBD
SystemZAddressingMode::Disp12Only


<s> static bool loongarch_classify_address ( struct loongarch_address_info * info , rtx x , machine_mode mode , bool strict_p ) { switch ( GET_CODE ( x ) ) { case REG : case SUBREG : info -> type = ADDRESS_REG ; info -> reg = x ; info -> offset = const0_rtx ; return loongarch_valid_base_register_p ( info -> reg , mode , strict_p ) ; case PLUS : if ( loongarch_valid_base_register_p ( XEXP ( x , 0 ) , mode , strict_p ) && loongarch_valid_index_p ( info , XEXP ( x , 1 ) , mode , strict_p ) ) { info -> reg = XEXP ( x , 0 ) ; return true ; } if ( loongarch_valid_base_register_p ( XEXP ( x , 1 ) , mode , strict_p ) && loongarch_valid_index_p ( info , XEXP ( x , 0 ) , mode , strict_p ) ) { info -> reg = XEXP ( x , 1 ) ; return true ; } info -> type = ADDRESS_REG ; info -> reg = XEXP ( x , 0 ) ; info -> offset = XEXP ( x , 1 ) ; return ( loongarch_valid_base_register_p ( info -> reg , mode , strict_p ) && loongarch_valid_offset_p ( info -> offset , mode ) ) ; case LO_SUM : info -> type = ADDRESS_LO_SUM ; info -> reg = XEXP ( x , 0 ) ; info -> offset = XEXP ( x , 1 ) ; info -> symbol_type = loongarch_classify_symbolic_expression ( info -> offset ) ; return ( loongarch_valid_base_register_p ( info -> reg , mode , strict_p ) && loongarch_valid_lo_sum_p ( info -> symbol_type , mode , info -> offset ) ) ; case CONST_INT : info -> type = ADDRESS_CONST_INT ; return IMM12_OPERAND ( INTVAL ( x ) ) ; default : return false ; } } </s>

Return true if X is a valid address for machine mode MODE . If it is , fill in INFO appropriately . STRICT_P is true if REG_OK_STRICT is in effect .


<s> void LinearizedRegion :: setEntry ( MachineBasicBlock * NewEntry ) { Entry = NewEntry ; } </s>

Set EntryBlock as the entry VPBlockBase of this VPRegionBlock .


<s> outliner :: InstrType X86InstrInfo :: getOutliningType ( MachineBasicBlock :: iterator & MIT , unsigned Flags ) const { MachineInstr & MI = * MIT ; if ( MI . isDebugInstr ( ) || MI . isIndirectDebugValue ( ) ) return outliner :: InstrType :: Invisible ; if ( MI . isKill ( ) ) return outliner :: InstrType :: Invisible ; if ( isTailCall ( MI ) ) return outliner :: InstrType :: Legal ; if ( MI . isTerminator ( ) || MI . isReturn ( ) ) { if ( MI . getParent ( ) -> succ_empty ( ) ) return outliner :: InstrType :: Legal ; return outliner :: InstrType :: Illegal ; } if ( MI . modifiesRegister ( X86 :: RSP , & RI ) || MI . readsRegister ( X86 :: RSP , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( X86 :: RSP ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( X86 :: RSP ) ) return outliner :: InstrType :: Illegal ; if ( MI . readsRegister ( X86 :: RIP , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( X86 :: RIP ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( X86 :: RIP ) ) return outliner :: InstrType :: Illegal ; if ( MI . isPosition ( ) ) return outliner :: InstrType :: Illegal ; for ( const MachineOperand & MOP : MI . operands ( ) ) if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return outliner :: InstrType :: Illegal ; return outliner :: InstrType :: Legal ; } </s>

Returns how or if MIT should be outlined .


<s> EVT X86TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( ( ! IsMemset || ZeroMemset ) && ! F -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoImplicitFloat ) ) { if ( Size >= 16 && ( Subtarget -> isUnalignedMemAccessFast ( ) || ( ( DstAlign == 0 || DstAlign >= 16 ) && ( SrcAlign == 0 || SrcAlign >= 16 ) ) ) ) { if ( Size >= 32 ) { if ( Subtarget -> hasInt256 ( ) ) return MVT :: v8i32 ; if ( Subtarget -> hasFp256 ( ) ) return MVT :: v8f32 ; } if ( Subtarget -> hasSSE2 ( ) ) return MVT :: v4i32 ; if ( Subtarget -> hasSSE1 ( ) ) return MVT :: v4f32 ; } else if ( ! MemcpyStrSrc && Size >= 8 && ! Subtarget -> is64Bit ( ) && Subtarget -> hasSSE2 ( ) ) { return MVT :: f64 ; } } if ( Subtarget -> is64Bit ( ) && Size >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>


<s>
bool
R600VectorRegMerger
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
if
(
skipFunction
(
*
Fn
.
getFunction
(
)
)
)
return
false
;
const
R600Subtarget
&
ST
=
Fn
.
getSubtarget
<
R600Subtarget
>
(
)
;
TII
=
ST
.
getInstrInfo
(
)
;
MRI
=
&
Fn
.
getRegInfo
(
)
;
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
MachineBasicBlock
*
MB
=
&
*
MBB
;
PreviousRegSeq
.
clear
(
)
;
PreviousRegSeqByReg
.
clear
(
)
;
PreviousRegSeqByUndefCount
.
clear
(
)
;
for
(
MachineBasicBlock
::
iterator
MII
=
MB
->
begin
(
)
,
MIIE
=
MB
->
end
(
)
;
MII
!=
MIIE
;
++
MII
)
{
MachineInstr
&
MI
=
*
MII
;
if
(
MI
.
getOpcode
(
)
!=
AMDGPU
::
REG_SEQUENCE
)
{
if
(
TII
->
get
(
MI
.
getOpcode
(
)
)
.
TSFlags
&
R600_InstFlag
::
TEX_INST
)
{
unsigned
Reg
=
MI
.
getOperand
(
1
)
.
getReg
(
)
;
for
(
MachineRegisterInfo
::
def_instr_iterator
It
=
MRI
->
def_instr_begin
(
Reg
)
,
E
=
MRI
->
def_instr_end
(
)
;
It
!=
E
;
++
It
)
{
RemoveMI
(
&
(
*
It
)
)
;
}
}
continue
;
}
RegSeqInfo
RSI
(
*
MRI
,
&
MI
)
;
unsigned
Reg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
if
(
!
areAllUsesSwizzeable
(
Reg
)
)
continue
;
DEBUG
(
{
dbgs
(
)
<<
"Trying to optimize "
;
MI
.
dump
(
)
;
}
)
;
RegSeqInfo
CandidateRSI
;
std
::
vector
<
std
::
pair
<
unsigned
,
unsigned
>
>
RemapChan
;
DEBUG
(
dbgs
(
)
<<
"Using common slots...\n"
;
)
;
if
(
tryMergeUsingCommonSlot
(
RSI
,
CandidateRSI
,
RemapChan
)
)
{
RemoveMI
(
CandidateRSI
.
Instr
)
;
MII
=
RebuildVector
(
&
RSI
,
&
CandidateRSI
,
RemapChan
)
;
trackRSI
(
RSI
)
;
continue
;
}
DEBUG
(
dbgs
(
)
<<
"Using free slots...\n"
;
)
;
RemapChan
.
clear
(
)
;
if
(
tryMergeUsingFreeSlot
(
RSI
,
CandidateRSI
,
RemapChan
)
)
{
RemoveMI
(
CandidateRSI
.
Instr
)
;
MII
=
RebuildVector
(
&
RSI
,
&
CandidateRSI
,
RemapChan
)
;
trackRSI
(
RSI
)
;
continue
;
}
trackRSI
(
RSI
)
;
}
}
</s>

runOnMachineFunction - Emit the function body .

AMDGPU
R600
R600
R600
AMDGPU::REG_SEQUENCE
R600_InstFlag::TEX_INST
1
SI
0
"Trying to optimize "
SI
"Using common slots...\n"
SI
SI
SI
SI
SI
SI
SI
"Using free slots...\n"
SI
SI
SI
SI
SI
SI
SI
SI
SI


<s> enum reg_class nds32_regno_reg_class ( int regno ) { if ( regno >= 0 && regno <= 7 ) return LOW_REGS ; else if ( regno >= 8 && regno <= 11 ) return MIDDLE_REGS ; else if ( regno >= 12 && regno <= 14 ) return HIGH_REGS ; else if ( regno == 15 ) return R15_TA_REG ; else if ( regno >= 16 && regno <= 19 ) return MIDDLE_REGS ; else if ( regno >= 20 && regno <= 31 ) return HIGH_REGS ; else if ( regno == 32 || regno == 33 ) { return GENERAL_REGS ; } else if ( regno >= 34 && regno <= 97 ) return FP_REGS ; else return NO_REGS ; } </s>


<s> static bool aarch64_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t ) { unsigned int from_flags = aarch64_classify_vector_mode ( from ) ; unsigned int to_flags = aarch64_classify_vector_mode ( to ) ; bool from_sve_p = ( from_flags & VEC_ANY_SVE ) ; bool to_sve_p = ( to_flags & VEC_ANY_SVE ) ; bool from_partial_sve_p = from_sve_p && ( from_flags & VEC_PARTIAL ) ; bool to_partial_sve_p = to_sve_p && ( to_flags & VEC_PARTIAL ) ; bool from_pred_p = ( from_flags & VEC_SVE_PRED ) ; bool to_pred_p = ( to_flags & VEC_SVE_PRED ) ; if ( from_pred_p != to_pred_p ) return false ; if ( from_partial_sve_p != to_partial_sve_p ) return false ; if ( from_partial_sve_p && ( aarch64_sve_container_bits ( from ) != aarch64_sve_container_bits ( to ) || GET_MODE_UNIT_SIZE ( from ) != GET_MODE_UNIT_SIZE ( to ) ) ) return false ; if ( maybe_ne ( BITS_PER_SVE_VECTOR , 128u ) ) { if ( from_sve_p && ! to_sve_p && maybe_gt ( GET_MODE_BITSIZE ( to ) , 128 ) ) return false ; if ( to_sve_p && ! from_sve_p && maybe_gt ( GET_MODE_BITSIZE ( from ) , 128 ) ) return false ; } if ( BYTES_BIG_ENDIAN ) { if ( from_sve_p != to_sve_p ) return false ; if ( from_sve_p && GET_MODE_UNIT_SIZE ( from ) != GET_MODE_UNIT_SIZE ( to ) ) return false ; } return true ; } </s>


<s> bool SIInstrInfo :: isHighLatencyDef ( int Opc ) const { return get ( Opc ) . mayLoad ( ) && ( isMUBUF ( Opc ) || isMTBUF ( Opc ) || isMIMG ( Opc ) || isFLAT ( Opc ) ) ; } </s>

Return true if this opcode has high latency to its result .


<s> bool PPCRegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , Register Reg , int & FrameIdx ) const { if ( PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ) { FrameIdx = MF . getInfo < PPCFunctionInfo > ( ) -> getCRSpillFrameIndex ( ) ; return true ; } return false ; } </s>

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register .