<s>
static
void
complete_base_type
(
typeinfo
*
typeptr
,
char
*
buf
,
int
*
bufi
)
{
switch
(
typeptr
->
base
)
{
case
BT_CHAR
:
memcpy
(
&
buf
[
*
bufi
]
,
"qi"
,
2
)
;
break
;
case
BT_SHORT
:
memcpy
(
&
buf
[
*
bufi
]
,
"hi"
,
2
)
;
break
;
case
BT_INT
:
memcpy
(
&
buf
[
*
bufi
]
,
"si"
,
2
)
;
break
;
case
BT_LONG
:
memcpy
(
&
buf
[
*
bufi
]
,
"lg"
,
2
)
;
break
;
case
BT_LONGLONG
:
memcpy
(
&
buf
[
*
bufi
]
,
"di"
,
2
)
;
break
;
case
BT_FLOAT
:
memcpy
(
&
buf
[
*
bufi
]
,
"sf"
,
2
)
;
break
;
case
BT_DOUBLE
:
memcpy
(
&
buf
[
*
bufi
]
,
"df"
,
2
)
;
break
;
case
BT_LONGDOUBLE
:
memcpy
(
&
buf
[
*
bufi
]
,
"ld"
,
2
)
;
break
;
case
BT_INT128
:
memcpy
(
&
buf
[
*
bufi
]
,
"ti"
,
2
)
;
break
;
case
BT_FLOAT128
:
memcpy
(
&
buf
[
*
bufi
]
,
"tf"
,
2
)
;
break
;
case
BT_BOOL
:
memcpy
(
&
buf
[
*
bufi
]
,
"bi"
,
2
)
;
break
;
case
BT_STRING
:
memcpy
(
&
buf
[
*
bufi
]
,
"st"
,
2
)
;
break
;
case
BT_DECIMAL32
:
memcpy
(
&
buf
[
*
bufi
]
,
"sd"
,
2
)
;
break
;
case
BT_DECIMAL64
:
memcpy
(
&
buf
[
*
bufi
]
,
"dd"
,
2
)
;
break
;
case
BT_DECIMAL128
:
memcpy
(
&
buf
[
*
bufi
]
,
"td"
,
2
)
;
break
;
case
BT_IBM128
:
memcpy
(
&
buf
[
*
bufi
]
,
"if"
,
2
)
;
break
;
default
:
diag
(
pos
,
"unhandled basetype %d.\n"
,
typeptr
->
base
)
;
exit
(
1
)
;
}
*
bufi
+=
2
;
}
</s>

Convert a base type into a mode string .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < AAResultsWrapperPass > ( ) ; AU . addRequired < AssumptionCacheTracker > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addRequired < TargetLibraryInfoWrapperPass > ( ) ; AU . addRequired < TargetPassConfig > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool AArch64FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RI = MF . getTarget ( ) . getRegisterInfo ( ) ; if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) && MFI -> hasCalls ( ) ) return true ; return ( RI -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static int s390_non_addr_reg_read_p ( rtx reg , rtx_insn * insn ) { return reg_referenced_p ( reg , PATTERN ( insn ) ) && ! reg_used_in_mem_p ( REGNO ( reg ) , PATTERN ( insn ) ) ; } </s>

Returns 1 if INSN reads the value of REG for purposes not related to addressing of memory , and 0 otherwise .


<s> static bool classof ( const ARMConstantPoolValue * ACPV ) { return ACPV -> isMachineBasicBlock ( ) ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> BitVector LM32RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( LM32 :: R0 ) ; Reserved . set ( LM32 :: RGP ) ; Reserved . set ( LM32 :: RFP ) ; Reserved . set ( LM32 :: RSP ) ; Reserved . set ( LM32 :: RRA ) ; Reserved . set ( LM32 :: REA ) ; Reserved . set ( LM32 :: RBA ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool AMDGPUTargetLowering :: storeOfVectorConstantIsCheap ( EVT MemVT , unsigned NumElem , unsigned AS ) const { return true ; } </s>

Return true if it is expected to be cheaper to do a store of vector constant with the given size and type for the address space than to store the individual scalar element constants .


<s>
bool
HexagonPacketizer
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
DisablePacketizer
||
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
HII
=
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getInstrInfo
(
)
;
HRI
=
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getRegisterInfo
(
)
;
auto
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
auto
*
AA
=
&
getAnalysis
<
AAResultsWrapperPass
>
(
)
.
getAAResults
(
)
;
auto
*
MBPI
=
&
getAnalysis
<
MachineBranchProbabilityInfo
>
(
)
;
if
(
EnableGenAllInsnClass
)
HII
->
genAllInsnTimingClasses
(
MF
)
;
HexagonPacketizerList
Packetizer
(
MF
,
MLI
,
AA
,
MBPI
)
;
assert
(
Packetizer
.
getResourceTracker
(
)
&&
"Empty DFA table!"
)
;
for
(
auto
&
MB
:
MF
)
{
auto
End
=
MB
.
end
(
)
;
auto
MI
=
MB
.
begin
(
)
;
while
(
MI
!=
End
)
{
auto
NextI
=
std
::
next
(
MI
)
;
if
(
MI
->
isKill
(
)
)
{
MB
.
erase
(
MI
)
;
End
=
MB
.
end
(
)
;
}
MI
=
NextI
;
}
}
for
(
auto
&
MB
:
MF
)
{
auto
Begin
=
MB
.
begin
(
)
,
End
=
MB
.
end
(
)
;
while
(
Begin
!=
End
)
{
MachineBasicBlock
::
iterator
RB
=
Begin
;
while
(
RB
!=
End
&&
HII
->
isSchedulingBoundary
(
*
RB
,
&
MB
,
MF
)
)
++
RB
;
MachineBasicBlock
::
iterator
RE
=
RB
;
while
(
RE
!=
End
&&
!
HII
->
isSchedulingBoundary
(
*
RE
,
&
MB
,
MF
)
)
++
RE
;
if
(
RE
!=
End
)
++
RE
;
if
(
RB
!=
End
)
Packetizer
.
PacketizeMIs
(
&
MB
,
RB
,
RE
)
;
Begin
=
RE
;
}
}
Packetizer
.
unpacketizeSoloInstrs
(
MF
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .

Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
"Empty DFA table!"


"Didn't find MI in its own basic block?"

getOffsetOf - Return the current offset of the specified machine instruction from the start of the function .


<s> const PPCInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> bool X86FixupSetCCPass :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; MRI = & MF . getRegInfo ( ) ; TII = MF . getSubtarget < X86Subtarget > ( ) . getInstrInfo ( ) ; SmallVector < MachineInstr * , 4 > ToErase ; for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( MI . getOpcode ( ) != X86 :: SETCCr ) continue ; MachineInstr * ZExt = nullptr ; for ( auto & Use : MRI -> use_instructions ( MI . getOperand ( 0 ) . getReg ( ) ) ) if ( Use . getOpcode ( ) == X86 :: MOVZX32rr8 ) ZExt = & Use ; if ( ! ZExt ) continue ; MachineInstr * FlagsDefMI = findFlagsImpDef ( MI . getParent ( ) , MachineBasicBlock :: reverse_iterator ( & MI ) ) ; if ( ! FlagsDefMI ) continue ; if ( impUsesFlags ( FlagsDefMI ) ) continue ; ++ NumSubstZexts ; Changed = true ; const TargetRegisterClass * RC = MF . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ? & X86 :: GR32RegClass : & X86 :: GR32_ABCDRegClass ; unsigned ZeroReg = MRI -> createVirtualRegister ( RC ) ; unsigned InsertReg = MRI -> createVirtualRegister ( RC ) ; BuildMI ( MBB , FlagsDefMI , MI . getDebugLoc ( ) , TII -> get ( X86 :: MOV32r0 ) , ZeroReg ) ; BuildMI ( * ZExt -> getParent ( ) , ZExt , ZExt -> getDebugLoc ( ) , TII -> get ( X86 :: INSERT_SUBREG ) , InsertReg ) . addReg ( ZeroReg ) . addReg ( MI . getOperand ( 0 ) . getReg ( ) ) . addImm ( X86 :: sub_8bit ) ; MRI -> replaceRegWith ( ZExt -> getOperand ( 0 ) . getReg ( ) , InsertReg ) ; ToErase . push_back ( ZExt ) ; } } for ( auto & I : ToErase ) I -> eraseFromParent ( ) ; return Changed ; } </s>


<s> static bool msp430_rtx_costs ( rtx x ATTRIBUTE_UNUSED , int code , int outer_code ATTRIBUTE_UNUSED , int opno ATTRIBUTE_UNUSED , int * total , bool speed ATTRIBUTE_UNUSED ) { switch ( code ) { case SIGN_EXTEND : if ( GET_MODE ( x ) == SImode && outer_code == SET ) { * total = COSTS_N_INSNS ( 4 ) ; return true ; } break ; case ASHIFT : case ASHIFTRT : case LSHIFTRT : if ( ! msp430x ) { * total = COSTS_N_INSNS ( 100 ) ; return true ; } break ; } return false ; } </s>

This target hook describes the relative costs of RTL expressions . The function recurses to just before the lowest level of the expression , when both of the operands of the expression can be examined at the same time . This is because the cost of the expression depends on the specific addressing mode combination of the operands . The hook returns true when all subexpressions of X have been processed , and false when rtx_cost should recurse .


<s> static bool rs6000_global_entry_point_needed_p ( void ) { if ( DEFAULT_ABI != ABI_ELFv2 ) return false ; if ( TARGET_SINGLE_PIC_BASE ) return false ; if ( cfun -> is_thunk ) return true ; return cfun -> machine -> r2_setup_needed ; } </s>

Return whether we need to emit an ELFv2 global entry point prologue .


<s> bool shouldKeepZExtForFP16Conv ( ) const override { return true ; } </s>

Does this target require the clearing of high-order bits in a register passed to the fp16 to fp conversion library function .


<s> unsigned AVRInstrInfo :: insertIndirectBranch ( MachineBasicBlock & MBB , MachineBasicBlock & NewDestBB , const DebugLoc & DL , int64_t BrOffset , RegScavenger * RS ) const { auto & MI = * BuildMI ( & MBB , DL , get ( AVR :: JMPk ) ) . addMBB ( & NewDestBB ) ; return getInstSizeInBytes ( MI ) ; } </s>

Insert an unconditional indirect branch at the end of MBB to NewDestBB .


<s>
const
MCPhysReg
*
X86RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
const
X86Subtarget
&
Subtarget
=
MF
->
getSubtarget
<
X86Subtarget
>
(
)
;
bool
HasSSE
=
Subtarget
.
hasSSE1
(
)
;
bool
HasAVX
=
Subtarget
.
hasAVX
(
)
;
bool
HasAVX512
=
Subtarget
.
hasAVX512
(
)
;
bool
CallsEHReturn
=
MF
->
getMMI
(
)
.
callsEHReturn
(
)
;
assert
(
MF
&&
"MachineFunction required"
)
;
switch
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
)
{
case
CallingConv
::
GHC
:
case
CallingConv
::
HiPE
:
return
CSR_NoRegs_SaveList
;
case
CallingConv
::
AnyReg
:
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
return
CSR_64_AllRegs_SaveList
;
case
CallingConv
::
PreserveMost
:
return
CSR_64_RT_MostRegs_SaveList
;
case
CallingConv
::
PreserveAll
:
if
(
HasAVX
)
return
CSR_64_RT_AllRegs_AVX_SaveList
;
return
CSR_64_RT_AllRegs_SaveList
;
case
CallingConv
::
CXX_FAST_TLS
:
if
(
Is64Bit
)
return
CSR_64_TLS_Darwin_SaveList
;
break
;
case
CallingConv
::
Intel_OCL_BI
:
{
if
(
HasAVX512
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX512
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX_SaveList
;
if
(
HasAVX
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX_SaveList
;
if
(
!
HasAVX
&&
!
IsWin64
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_SaveList
;
break
;
}
case
CallingConv
::
HHVM
:
return
CSR_64_HHVM_SaveList
;
case
CallingConv
::
Cold
:
if
(
Is64Bit
)
return
CSR_64_MostRegs_SaveList
;
break
;
case
CallingConv
::
X86_64_Win64
:
return
CSR_Win64_SaveList
;
case
CallingConv
::
X86_64_SysV
:
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
case
CallingConv
::
X86_INTR
:
if
(
Is64Bit
)
{
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
else
return
CSR_64_AllRegs_SaveList
;
}
else
{
if
(
HasSSE
)
return
CSR_32_AllRegs_SSE_SaveList
;
else
return
CSR_32_AllRegs_SaveList
;
}
default
:
break
;
}
if
(
Is64Bit
)
{
if
(
IsWin64
)
return
CSR_Win64_SaveList
;
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
}
if
(
CallsEHReturn
)
return
CSR_32EHRet_SaveList
;
return
CSR_32_SaveList
;
}
</s>


<s> bool X86TTIImpl :: enableInterleavedAccessVectorization ( ) { return ! ( ST -> isAtom ( ) ) ; } </s>

Enable matching of interleaved access groups .


<s> void MSP430FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const MSP430InstrInfo & TII = * static_cast < const MSP430InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; unsigned StackAlign = getStackAlignment ( ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; uint64_t Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = nullptr ; if ( Old -> getOpcode ( ) == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( MSP430 :: SUB16ri ) , MSP430 :: SP ) . addReg ( MSP430 :: SP ) . addImm ( Amount ) ; } else { assert ( Old -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) ; uint64_t CalleeAmt = Old -> getOperand ( 1 ) . getImm ( ) ; Amount -= CalleeAmt ; if ( Amount ) New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( MSP430 :: ADD16ri ) , MSP430 :: SP ) . addReg ( MSP430 :: SP ) . addImm ( Amount ) ; } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { MachineInstr * Old = I ; MachineInstr * New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( MSP430 :: SUB16ri ) , MSP430 :: SP ) . addReg ( MSP430 :: SP ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s>
int
AArch64FrameLowering
::
getFrameIndexReferencePreferSP
(
const
MachineFunction
&
MF
,
int
FI
,
unsigned
&
FrameReg
,
bool
IgnoreSPUpdates
)
const
{
const
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Offset from the SP for "
<<
FI
<<
" is "
<<
MFI
.
getObjectOffset
(
FI
)
<<
"\n"
)
;
FrameReg
=
AArch64
::
SP
;
return
MFI
.
getObjectOffset
(
FI
)
;
}
</s>

Same as getFrameIndexReference , except that the stack pointer ( as opposed to the frame pointer ) will be the preferred value for FrameReg .


<s> bool mayNeedRelaxation ( MCInst const & Inst ) const override { assert ( HexagonMCInstrInfo :: isBundle ( Inst ) ) ; bool PreviousIsExtender = false ; for ( auto const & I : HexagonMCInstrInfo :: bundleInstructions ( Inst ) ) { auto const & Inst = * I . getInst ( ) ; if ( ! PreviousIsExtender ) { if ( isInstRelaxable ( Inst ) ) return true ; } PreviousIsExtender = HexagonMCInstrInfo :: isImmext ( Inst ) ; } return false ; } </s>

Check whether the given instruction may need relaxation .


<s>
bool
LanaiInstrInfo
::
areMemAccessesTriviallyDisjoint
(
MachineInstr
&
MIa
,
MachineInstr
&
MIb
,
AliasAnalysis
*
AA
)
const
{
assert
(
MIa
.
mayLoadOrStore
(
)
&&
"MIa must be a load or store."
)
;
assert
(
MIb
.
mayLoadOrStore
(
)
&&
"MIb must be a load or store."
)
;
if
(
MIa
.
hasUnmodeledSideEffects
(
)
||
MIb
.
hasUnmodeledSideEffects
(
)
||
MIa
.
hasOrderedMemoryRef
(
)
||
MIb
.
hasOrderedMemoryRef
(
)
)
return
false
;
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
unsigned
BaseRegA
=
0
,
BaseRegB
=
0
;
int64_t
OffsetA
=
0
,
OffsetB
=
0
;
unsigned
int
WidthA
=
0
,
WidthB
=
0
;
if
(
getMemOpBaseRegImmOfsWidth
(
MIa
,
BaseRegA
,
OffsetA
,
WidthA
,
TRI
)
&&
getMemOpBaseRegImmOfsWidth
(
MIb
,
BaseRegB
,
OffsetB
,
WidthB
,
TRI
)
)
{
if
(
BaseRegA
==
BaseRegB
)
{
int
LowOffset
=
std
::
min
(
OffsetA
,
OffsetB
)
;
int
HighOffset
=
std
::
max
(
OffsetA
,
OffsetB
)
;
int
LowWidth
=
(
LowOffset
==
OffsetA
)
WidthA
:
WidthB
;
if
(
LowOffset
+
LowWidth
<=
HighOffset
)
return
true
;
}
}
return
false
;
}
</s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s>
const
char
*
PTXTargetLowering
::
getTargetNodeName
(
unsigned
Opcode
)
const
{
switch
(
Opcode
)
{
default
:
llvm_unreachable
(
"Unknown opcode"
)
;
case
PTXISD
::
COPY_ADDRESS
:
return
"PTXISD::COPY_ADDRESS"
;
case
PTXISD
::
READ_PARAM
:
return
"PTXISD::READ_PARAM"
;
case
PTXISD
::
EXIT
:
return
"PTXISD::EXIT"
;
case
PTXISD
::
RET
:
return
"PTXISD::RET"
;
}
}
</s>

getTargetNodeName - This method returns the name of a target specific


<s> bool mips_expand_unaligned_load ( rtx dest , rtx src , unsigned int width , int bitpos ) { rtx left , right , temp ; if ( GET_CODE ( dest ) == SUBREG && GET_MODE ( dest ) == DImode && SUBREG_BYTE ( dest ) == 0 && GET_MODE ( SUBREG_REG ( dest ) ) == SImode ) dest = SUBREG_REG ( dest ) ; if ( GET_MODE_BITSIZE ( GET_MODE ( dest ) ) != width ) return false ; if ( ! mips_get_unaligned_mem ( & src , width , bitpos , & left , & right ) ) return false ; temp = gen_reg_rtx ( GET_MODE ( dest ) ) ; if ( GET_MODE ( dest ) == DImode ) { emit_insn ( gen_mov_ldl ( temp , src , left ) ) ; emit_insn ( gen_mov_ldr ( dest , copy_rtx ( src ) , right , temp ) ) ; } else { emit_insn ( gen_mov_lwl ( temp , src , left ) ) ; emit_insn ( gen_mov_lwr ( dest , copy_rtx ( src ) , right , temp ) ) ; } return true ; } </s>

Try to emit the equivalent of ( set DEST ( zero_extract SRC WIDTH BITPOS ) ) . Return true on success . We only handle cases where zero_extract is equivalent to sign_extract .


<s> const TargetRegisterClass * X86RegisterInfo :: getGPRsForTailCall ( const MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( F && F -> getCallingConv ( ) == CallingConv :: GHC ) { if ( Is64Bit ) return & X86 :: GR64RegClass ; else return & X86 :: GR32RegClass ; } if ( IsWin64 || ( F && F -> getCallingConv ( ) == CallingConv :: X86_64_Win64 ) ) return & X86 :: GR64_TCW64RegClass ; else if ( Is64Bit ) return & X86 :: GR64_TCRegClass ; bool hasHipeCC = ( F ? F -> getCallingConv ( ) == CallingConv :: HiPE : false ) ; if ( hasHipeCC ) return & X86 :: GR32RegClass ; return & X86 :: GR32_TCRegClass ; } </s>

getGPRsForTailCall - Returns a register class with registers that can be used in forming tail calls .


<s> bool AArch64TargetLowering :: isProfitableToHoist ( Instruction * I ) const { if ( I -> getOpcode ( ) != Instruction :: FMul ) return true ; if ( I -> getNumUses ( ) != 1 ) return true ; Instruction * User = I -> user_back ( ) ; if ( User && ! ( User -> getOpcode ( ) == Instruction :: FSub || User -> getOpcode ( ) == Instruction :: FAdd ) ) return true ; const TargetOptions & Options = getTargetMachine ( ) . Options ; EVT VT = getValueType ( User -> getOperand ( 0 ) -> getType ( ) ) ; if ( isFMAFasterThanFMulAndFAdd ( VT ) && isOperationLegalOrCustom ( ISD :: FMA , VT ) && ( Options . AllowFPOpFusion == FPOpFusion :: Fast || Options . UnsafeFPMath ) ) return false ; return true ; } </s>

Return true if it is profitable to hoist instruction in the then/else to before if .


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64Bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , Options . StackAlignmentOverride , is64Bit ) , FrameLowering ( * this , Subtarget ) , ELFWriterInfo ( is64Bit , true ) { if ( getRelocationModel ( ) == Reloc :: Static ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . is64Bit ( ) ) { Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; } else if ( Subtarget . isTargetCygMing ( ) ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . isTargetDarwin ( ) ) { if ( getRelocationModel ( ) == Reloc :: PIC_ ) Subtarget . setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; Subtarget . setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( Subtarget . isTargetELF ( ) ) { Subtarget . setPICStyle ( PICStyles :: GOT ) ; } if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = FloatABI :: Hard ; } </s>


Enable AARCH64_FL_ * flags EXTRA_FLAGS on top of the base Advanced SIMD set .


"Function has local memory argument. Promoting to "

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


"getMemOperandWithOffset only supports base "

Get the base operand and byte offset of an instruction that reads/writes memory .


<s> bool ARMPassConfig :: addInstSelector ( ) { addPass ( createARMISelDag ( getARMTargetMachine ( ) , getOptLevel ( ) ) ) ; if ( TM -> getTargetTriple ( ) . isOSBinFormatELF ( ) && TM -> Options . EnableFastISel ) addPass ( createARMGlobalBaseRegPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> int nonvol_nonimm_operand ( rtx op , enum machine_mode mode ) { if ( GET_CODE ( op ) == MEM && MEM_VOLATILE_P ( op ) ) return 0 ; return nonimmediate_operand ( op , mode ) ; } </s>

Return true if OP is a non-volatile non-immediate operand . Volatile memory refs require a special `` cache-bypass '' instruction and only the standard movXX patterns are set up to handle them .


<s>
static
void
pa_asm_trampoline_template
(
FILE
*
f
)
{
if
(
!
TARGET_64BIT
)
{
fputs
(
"\tldw	36(%r22),%r21\n"
,
f
)
;
fputs
(
"\tbb,>=,n	%r21,30,.+16\n"
,
f
)
;
if
(
ASSEMBLER_DIALECT
==
0
)
fputs
(
"\tdepi	0,31,2,%r21\n"
,
f
)
;
else
fputs
(
"\tdepwi	0,31,2,%r21\n"
,
f
)
;
fputs
(
"\tldw	4(%r21),%r19\n"
,
f
)
;
fputs
(
"\tldw	0(%r21),%r21\n"
,
f
)
;
if
(
TARGET_PA_20
)
{
fputs
(
"\tbve	(%r21)\n"
,
f
)
;
fputs
(
"\tldw	40(%r22),%r29\n"
,
f
)
;
fputs
(
"\t.word	0\n"
,
f
)
;
fputs
(
"\t.word	0\n"
,
f
)
;
}
else
{
fputs
(
"\tldsid	(%r21),%r1\n"
,
f
)
;
fputs
(
"\tmtsp	%r1,%sr0\n"
,
f
)
;
fputs
(
"\tbe	0(%sr0,%r21)\n"
,
f
)
;
fputs
(
"\tldw	40(%r22),%r29\n"
,
f
)
;
}
fputs
(
"\t.word	0\n"
,
f
)
;
fputs
(
"\t.word	0\n"
,
f
)
;
fputs
(
"\t.word	0\n"
,
f
)
;
fputs
(
"\t.word	0\n"
,
f
)
;
}
else
{
fputs
(
"\t.dword 0\n"
,
f
)
;
fputs
(
"\t.dword 0\n"
,
f
)
;
fputs
(
"\t.dword 0\n"
,
f
)
;
fputs
(
"\t.dword 0\n"
,
f
)
;
fputs
(
"\tmfia	%r31\n"
,
f
)
;
fputs
(
"\tldd	24(%r31),%r1\n"
,
f
)
;
fputs
(
"\tldd	24(%r1),%r27\n"
,
f
)
;
fputs
(
"\tldd	16(%r1),%r1\n"
,
f
)
;
fputs
(
"\tbve	(%r1)\n"
,
f
)
;
fputs
(
"\tldd	32(%r31),%r31\n"
,
f
)
;
fputs
(
"\t.dword 0  ; fptr\n"
,
f
)
;
fputs
(
"\t.dword 0  ; static link\n"
,
f
)
;
}
}
</s>

Output assembler code for a block containing the constant parts of a trampoline , leaving space for the variable parts.\ The trampoline sets the static chain pointer to STATIC_CHAIN_REGNUM and then branches to the specified routine . This code template is copied from text segment to stack location and then patched with pa_trampoline_init to contain valid values , and then entered as a subroutine . It is best to keep this as small as possible to avoid having to flush multiple lines in the cache .


<s>
StringRef
getPassName
(
)
const
override
{
return
"P2 Expand Pseudos"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> unsigned size ( ) const { return ( Packet . size ( ) ) ; } </s>

The number of name/type pairs is returned .


<s> void X86IntelInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; unsigned Flags = MI -> getFlags ( ) ; if ( ( TSFlags & X86II :: LOCK ) || ( Flags & X86 :: IP_HAS_LOCK ) ) OS << "\tlock\t" ; if ( Flags & X86 :: IP_HAS_REPEAT_NE ) OS << "\trepne\t" ; else if ( Flags & X86 :: IP_HAS_REPEAT ) OS << "\trep\t" ; printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAnyX86InstComments ( MI , * CommentStream , getRegisterName ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static tree bpf_core_walk ( tree * tp , int * walk_subtrees , void * data ) { struct core_walk_data * dat = ( struct core_walk_data * ) data ; if ( TYPE_P ( * tp ) ) { * walk_subtrees = 0 ; return NULL_TREE ; } tree newdecl = bpf_core_newdecl ( TREE_TYPE ( * tp ) , dat -> which ) ; if ( dat -> which == BPF_BUILTIN_PRESERVE_ACCESS_INDEX ) { if ( bpf_core_is_maybe_aggregate_access ( * tp ) ) { * tp = build_call_expr_loc ( dat -> loc , newdecl , 1 , * tp ) ; * walk_subtrees = 0 ; } } else { * tp = build_call_expr_loc ( dat -> loc , newdecl , 2 , * tp , dat -> arg ) ; * walk_subtrees = 0 ; } return NULL_TREE ; } </s>

Callback function used with walk_tree from bpf_resolve_overloaded_builtin .


<s> bool MVEGatherScatterLowering :: runOnFunction ( Function & F ) { if ( ! EnableMaskedGatherScatters ) return false ; auto & TPC = getAnalysis < TargetPassConfig > ( ) ; auto & TM = TPC . getTM < TargetMachine > ( ) ; auto * ST = & TM . getSubtarget < ARMSubtarget > ( F ) ; if ( ! ST -> hasMVEIntegerOps ( ) ) return false ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SmallVector < IntrinsicInst * , 4 > Gathers ; SmallVector < IntrinsicInst * , 4 > Scatters ; bool Changed = false ; for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & I ) ; if ( II && II -> getIntrinsicID ( ) == Intrinsic :: masked_gather ) { Gathers . push_back ( II ) ; if ( isa < GetElementPtrInst > ( II -> getArgOperand ( 0 ) ) ) Changed |= optimiseOffsets ( cast < Instruction > ( II -> getArgOperand ( 0 ) ) -> getOperand ( 1 ) , II -> getParent ( ) , LI ) ; } else if ( II && II -> getIntrinsicID ( ) == Intrinsic :: masked_scatter ) { Scatters . push_back ( II ) ; if ( isa < GetElementPtrInst > ( II -> getArgOperand ( 1 ) ) ) Changed |= optimiseOffsets ( cast < Instruction > ( II -> getArgOperand ( 1 ) ) -> getOperand ( 1 ) , II -> getParent ( ) , LI ) ; } } } for ( unsigned i = 0 ; i < Gathers . size ( ) ; i ++ ) { IntrinsicInst * I = Gathers [ i ] ; Value * L = lowerGather ( I ) ; if ( L == nullptr ) continue ; SimplifyInstructionsInBlock ( cast < Instruction > ( L ) -> getParent ( ) ) ; Changed = true ; } for ( unsigned i = 0 ; i < Scatters . size ( ) ; i ++ ) { IntrinsicInst * I = Scatters [ i ] ; Value * S = lowerScatter ( I ) ; if ( S == nullptr ) continue ; SimplifyInstructionsInBlock ( cast < Instruction > ( S ) -> getParent ( ) ) ; Changed = true ; } return Changed ; } </s>


<s>
bool
HCE
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
if
(
MF
.
getFunction
(
)
.
hasPersonalityFn
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
getPassName
(
)
<<
": skipping "
<<
MF
.
getName
(
)
<<
" due to exception handling\n"
)
;
return
false
;
}
LLVM_DEBUG
(
MF
.
print
(
dbgs
(
)
<<
"Before "
<<
getPassName
(
)
<<
'\n'
,
nullptr
)
)
;
HII
=
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getInstrInfo
(
)
;
HRI
=
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getRegisterInfo
(
)
;
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
AssignmentMap
IMap
;
collect
(
MF
)
;
llvm
::
sort
(
Extenders
,
[
]
(
const
ExtDesc
&
A
,
const
ExtDesc
&
B
)
{
return
ExtValue
(
A
)
<
ExtValue
(
B
)
;
}
)
;
bool
Changed
=
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Collected "
<<
Extenders
.
size
(
)
<<
" extenders\n"
)
;
for
(
unsigned
I
=
0
,
E
=
Extenders
.
size
(
)
;
I
!=
E
;
)
{
unsigned
B
=
I
;
const
ExtRoot
&
T
=
Extenders
[
B
]
.
getOp
(
)
;
while
(
I
!=
E
&&
ExtRoot
(
Extenders
[
I
]
.
getOp
(
)
)
==
T
)
++
I
;
IMap
.
clear
(
)
;
assignInits
(
T
,
B
,
I
,
IMap
)
;
Changed
|=
replaceExtenders
(
IMap
)
;
}
LLVM_DEBUG
(
{
if
(
Changed
)
MF
.
print
(
dbgs
(
)
<<
"After "
<<
getPassName
(
)
<<
'\n'
,
nullptr
)
;
else
dbgs
(
)
<<
"No changes\n"
;
}
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

Hexagon
": skipping "
" due to exception handling\n"
"Before "
Hexagon
Hexagon
"Collected "
" extenders\n"
0
"After "
"No changes\n"


"declaration as dllimport: attribute ignored"

"definition of static data member %q+D of dllimport'd class"

Return nonzero if DECL is a dllimport 'd object .


<s> bool isLegalMaskedLoad ( Type * DataType , MaybeAlign Alignment ) { return isLegalMaskedLoadStore ( DataType , Alignment ) ; } </s>

Return true if the target supports masked load .


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


"optionally flag setting instruction missing optional def operand"

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


<s> void AArch64PostLegalizerLowering :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < TargetPassConfig > ( ) ; AU . setPreservesCFG ( ) ; getSelectionDAGFallbackAnalysisUsage ( AU ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static rtx arc_legitimize_tls_address ( rtx addr , enum tls_model model ) { if ( ! flag_pic && model == TLS_MODEL_LOCAL_DYNAMIC ) model = TLS_MODEL_LOCAL_EXEC ; switch ( model ) { case TLS_MODEL_LOCAL_DYNAMIC : rtx base ; tree decl ; const char * base_name ; rtvec v ; decl = SYMBOL_REF_DECL ( addr ) ; base_name = DTPOFF_ZERO_SYM ; if ( decl && bss_initializer_p ( decl ) ) base_name = ".tbss" ; base = gen_rtx_SYMBOL_REF ( Pmode , base_name ) ; if ( strcmp ( base_name , DTPOFF_ZERO_SYM ) == 0 ) { if ( ! flag_pic ) goto local_exec ; v = gen_rtvec ( 1 , addr ) ; } else v = gen_rtvec ( 2 , addr , base ) ; addr = gen_rtx_UNSPEC ( Pmode , v , UNSPEC_TLS_OFF ) ; addr = gen_rtx_CONST ( Pmode , addr ) ; base = arc_legitimize_tls_address ( base , TLS_MODEL_GLOBAL_DYNAMIC ) ; return gen_rtx_PLUS ( Pmode , force_reg ( Pmode , base ) , addr ) ; case TLS_MODEL_GLOBAL_DYNAMIC : return arc_emit_call_tls_get_addr ( addr , UNSPEC_TLS_GD , addr ) ; case TLS_MODEL_INITIAL_EXEC : addr = arc_unspec_offset ( addr , UNSPEC_TLS_IE ) ; addr = copy_to_mode_reg ( Pmode , gen_const_mem ( Pmode , addr ) ) ; return gen_rtx_PLUS ( Pmode , arc_get_tp ( ) , addr ) ; case TLS_MODEL_LOCAL_EXEC : local_exec : addr = arc_unspec_offset ( addr , UNSPEC_TLS_OFF ) ; return gen_rtx_PLUS ( Pmode , arc_get_tp ( ) , addr ) ; default : gcc_unreachable ( ) ; } } </s>

Return a legitimized address for ADDR , which is a SYMBOL_REF with tls_model MODEL .


<s> bool aarch64_bitmask_imm ( HOST_WIDE_INT val , machine_mode mode ) { if ( GET_MODE_SIZE ( mode ) < 8 ) { val &= ( HOST_WIDE_INT ) 0xffffffff ; val |= val << 32 ; } return bsearch ( & val , aarch64_bitmasks , AARCH64_NUM_BITMASKS , sizeof ( aarch64_bitmasks [ 0 ] ) , aarch64_bitmasks_cmp ) != NULL ; } </s>

Return true if val is a valid bitmask immediate .


<s>
rtx
iq2000_legitimize_address
(
rtx
xinsn
,
rtx
old_x
ATTRIBUTE_UNUSED
,
machine_mode
mode
)
{
if
(
TARGET_DEBUG_B_MODE
)
{
GO_PRINTF
(
"\n========== LEGITIMIZE_ADDRESS\n"
)
;
GO_DEBUG_RTX
(
xinsn
)
;
}
if
(
iq2000_check_split
(
xinsn
,
mode
)
)
{
return
gen_rtx_LO_SUM
(
Pmode
,
copy_to_mode_reg
(
Pmode
,
gen_rtx_HIGH
(
Pmode
,
xinsn
)
)
,
xinsn
)
;
}
if
(
GET_CODE
(
xinsn
)
==
PLUS
)
{
rtx
xplus0
=
XEXP
(
xinsn
,
0
)
;
rtx
xplus1
=
XEXP
(
xinsn
,
1
)
;
enum
rtx_code
code0
=
GET_CODE
(
xplus0
)
;
enum
rtx_code
code1
=
GET_CODE
(
xplus1
)
;
if
(
code0
!=
REG
&&
code1
==
REG
)
{
xplus0
=
XEXP
(
xinsn
,
1
)
;
xplus1
=
XEXP
(
xinsn
,
0
)
;
code0
=
GET_CODE
(
xplus0
)
;
code1
=
GET_CODE
(
xplus1
)
;
}
if
(
code0
==
REG
&&
REG_MODE_OK_FOR_BASE_P
(
xplus0
,
mode
)
&&
code1
==
CONST_INT
&&
!
SMALL_INT
(
xplus1
)
)
{
rtx
int_reg
=
gen_reg_rtx
(
Pmode
)
;
rtx
ptr_reg
=
gen_reg_rtx
(
Pmode
)
;
emit_move_insn
(
int_reg
,
GEN_INT
(
INTVAL
(
xplus1
)
&
~
0x7fff
)
)
;
emit_insn
(
gen_rtx_SET
(
ptr_reg
,
gen_rtx_PLUS
(
Pmode
,
xplus0
,
int_reg
)
)
)
;
return
plus_constant
(
Pmode
,
ptr_reg
,
INTVAL
(
xplus1
)
&
0x7fff
)
;
}
}
if
(
TARGET_DEBUG_B_MODE
)
GO_PRINTF
(
"LEGITIMIZE_ADDRESS could not fix.\n"
)
;
return
xinsn
;
}
</s>

For the IQ2000 , transform : memory ( X + < large int > ) into : Y = < large int > & ~0x7fff ; Z = X + Y memory ( Z + ( < large int > & 0x7fff ) ) ;


<s>
const
char
*
avr_out_movpsi
(
rtx_insn
*
insn
,
rtx
*
op
,
int
*
plen
)
{
rtx
dest
=
op
[
0
]
;
rtx
src
=
op
[
1
]
;
if
(
avr_mem_flash_p
(
src
)
||
avr_mem_flash_p
(
dest
)
)
{
return
avr_out_lpm
(
insn
,
op
,
plen
)
;
}
if
(
register_operand
(
dest
,
VOIDmode
)
)
{
if
(
register_operand
(
src
,
VOIDmode
)
)
{
if
(
true_regnum
(
dest
)
>
true_regnum
(
src
)
)
{
avr_asm_len
(
"mov %C0,%C1"
,
op
,
plen
,
1
)
;
if
(
AVR_HAVE_MOVW
)
return
avr_asm_len
(
"movw %A0,%A1"
,
op
,
plen
,
1
)
;
else
return
avr_asm_len
(
"mov %B0,%B1"
CR_TAB
"mov %A0,%A1"
,
op
,
plen
,
2
)
;
}
else
{
if
(
AVR_HAVE_MOVW
)
avr_asm_len
(
"movw %A0,%A1"
,
op
,
plen
,
1
)
;
else
avr_asm_len
(
"mov %A0,%A1"
CR_TAB
"mov %B0,%B1"
,
op
,
plen
,
2
)
;
return
avr_asm_len
(
"mov %C0,%C1"
,
op
,
plen
,
1
)
;
}
}
else
if
(
CONSTANT_P
(
src
)
)
{
return
avr_out_reload_inpsi
(
op
,
NULL_RTX
,
plen
)
;
}
else
if
(
MEM_P
(
src
)
)
return
avr_out_load_psi
(
insn
,
op
,
plen
)
;
}
else
if
(
MEM_P
(
dest
)
)
{
rtx
xop
[
2
]
;
xop
[
0
]
=
dest
;
xop
[
1
]
=
src
==
CONST0_RTX
(
GET_MODE
(
dest
)
)
zero_reg_rtx
:
src
;
return
avr_out_store_psi
(
insn
,
xop
,
plen
)
;
}
fatal_insn
(
"invalid insn:"
,
insn
)
;
return
""
;
}
</s>


<s> bool DLXInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TrueBlock , MachineBasicBlock * & FalseBlock , SmallVectorImpl < MachineOperand > & Condition , bool AllowModify ) const { return false ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> int X86FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const X86RegisterInfo * RegInfo = static_cast < const X86RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; if ( RegInfo -> hasBasePointer ( MF ) ) FrameReg = RegInfo -> getBaseRegister ( ) ; else if ( RegInfo -> needsStackRealignment ( MF ) ) FrameReg = RegInfo -> getStackRegister ( ) ; else FrameReg = RegInfo -> getFrameRegister ( MF ) ; return getFrameIndexOffset ( MF , FI ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s>
static
rtx
avr_legitimize_address
(
rtx
x
,
rtx
oldx
,
machine_mode
mode
)
{
bool
big_offset_p
=
false
;
x
=
oldx
;
if
(
AVR_TINY
)
{
if
(
CONSTANT_ADDRESS_P
(
x
)
&&
!
avr_address_tiny_absdata_p
(
x
,
mode
)
)
{
x
=
force_reg
(
Pmode
,
x
)
;
}
}
if
(
GET_CODE
(
oldx
)
==
PLUS
&&
REG_P
(
XEXP
(
oldx
,
0
)
)
)
{
if
(
REG_P
(
XEXP
(
oldx
,
1
)
)
)
x
=
force_reg
(
GET_MODE
(
oldx
)
,
oldx
)
;
else
if
(
CONST_INT_P
(
XEXP
(
oldx
,
1
)
)
)
{
int
offs
=
INTVAL
(
XEXP
(
oldx
,
1
)
)
;
if
(
frame_pointer_rtx
!=
XEXP
(
oldx
,
0
)
&&
offs
>
MAX_LD_OFFSET
(
mode
)
)
{
big_offset_p
=
true
;
x
=
force_reg
(
GET_MODE
(
oldx
)
,
oldx
)
;
}
}
}
if
(
avr_log
.
legitimize_address
)
{
avr_edump
(
"\n%?: mode=%m\n %r\n"
,
mode
,
oldx
)
;
if
(
x
!=
oldx
)
avr_edump
(
" %s --> %r\n"
,
big_offset_p
"(big offset)"
:
""
,
x
)
;
}
return
x
;
}
</s>

Attempts to replace X with a valid memory address for an operand of mode MODE


<s> static void conditionalize_optimization ( void ) { rtx_insn * insn ; for ( insn = get_insns ( ) ; insn ; insn = conditionalize_block ( insn ) ) continue ; } </s>

Apply the conditionalization of blocks optimization . This is the outer loop that traverses through the insns scanning for a branch that signifies an opportunity to apply the optimization . Note that this optimization is applied late . If we could apply it earlier , say before cse 2 , it may expose more optimization opportunities . but , the pay back probably is n't really worth the effort ( we 'd have to update all reg/flow/notes/links/etc to make it work - and stick it in before cse 2 ) .


<s>
void
addExpr
(
MCInst
&
Inst
,
const
MCExpr
*
Expr
)
const
{
assert
(
Expr
&&
"Expr shouldn't be null!"
)
;
if
(
auto
*
CE
=
dyn_cast
<
MCConstantExpr
>
(
Expr
)
)
Inst
.
addOperand
(
MCOperand
::
createImm
(
CE
->
getValue
(
)
)
)
;
else
Inst
.
addOperand
(
MCOperand
::
createExpr
(
Expr
)
)
;
}
</s>


<s> MachineInstrBuilder SIInstrInfo :: buildIndirectRead ( MachineBasicBlock * MBB , MachineBasicBlock :: iterator I , unsigned ValueReg , unsigned Address , unsigned OffsetReg ) const { llvm_unreachable ( "Unimplemented" ) ; } </s>

Build instruction ( s ) for an indirect register read .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s>
bool
ARMBaseInstrInfo
::
getRegSequenceLikeInputs
(
const
MachineInstr
&
MI
,
unsigned
DefIdx
,
SmallVectorImpl
<
RegSubRegPairAndIdx
>
&
InputRegs
)
const
{
assert
(
DefIdx
<
MI
.
getDesc
(
)
.
getNumDefs
(
)
&&
"Invalid definition index"
)
;
assert
(
MI
.
isRegSequenceLike
(
)
&&
"Invalid kind of instruction"
)
;
switch
(
MI
.
getOpcode
(
)
)
{
case
ARM
::
VMOVDRR
:
const
MachineOperand
*
MOReg
=
&
MI
.
getOperand
(
1
)
;
InputRegs
.
push_back
(
RegSubRegPairAndIdx
(
MOReg
->
getReg
(
)
,
MOReg
->
getSubReg
(
)
,
ARM
::
ssub_0
)
)
;
MOReg
=
&
MI
.
getOperand
(
2
)
;
InputRegs
.
push_back
(
RegSubRegPairAndIdx
(
MOReg
->
getReg
(
)
,
MOReg
->
getSubReg
(
)
,
ARM
::
ssub_1
)
)
;
return
true
;
}
llvm_unreachable
(
"Target dependent opcode missing"
)
;
}
</s>

Target-dependent implementation of getRegSequenceInputs .


<s> static void avr_reorg ( void ) { rtx_insn * insn = get_insns ( ) ; for ( insn = next_real_insn ( insn ) ; insn ; insn = next_real_insn ( insn ) ) { rtx pattern = avr_compare_pattern ( insn ) ; if ( ! pattern ) continue ; if ( optimize && avr_reorg_remove_redundant_compare ( insn ) ) { continue ; } if ( compare_diff_p ( insn ) ) { rtx_insn * next = next_real_insn ( insn ) ; rtx pat = PATTERN ( next ) ; pattern = SET_SRC ( pattern ) ; if ( true_regnum ( XEXP ( pattern , 0 ) ) >= 0 && true_regnum ( XEXP ( pattern , 1 ) ) >= 0 ) { rtx x = XEXP ( pattern , 0 ) ; rtx src = SET_SRC ( pat ) ; rtx t = XEXP ( src , 0 ) ; PUT_CODE ( t , swap_condition ( GET_CODE ( t ) ) ) ; XEXP ( pattern , 0 ) = XEXP ( pattern , 1 ) ; XEXP ( pattern , 1 ) = x ; INSN_CODE ( next ) = - 1 ; } else if ( true_regnum ( XEXP ( pattern , 0 ) ) >= 0 && XEXP ( pattern , 1 ) == const0_rtx ) { rtx src = SET_SRC ( pat ) ; rtx t = XEXP ( src , 0 ) ; PUT_CODE ( t , swap_condition ( GET_CODE ( t ) ) ) ; XEXP ( pattern , 1 ) = XEXP ( pattern , 0 ) ; XEXP ( pattern , 0 ) = const0_rtx ; INSN_CODE ( next ) = - 1 ; INSN_CODE ( insn ) = - 1 ; } else if ( true_regnum ( XEXP ( pattern , 0 ) ) >= 0 && CONST_INT_P ( XEXP ( pattern , 1 ) ) ) { rtx x = XEXP ( pattern , 1 ) ; rtx src = SET_SRC ( pat ) ; rtx t = XEXP ( src , 0 ) ; machine_mode mode = GET_MODE ( XEXP ( pattern , 0 ) ) ; if ( avr_simplify_comparison_p ( mode , GET_CODE ( t ) , x ) ) { XEXP ( pattern , 1 ) = gen_int_mode ( INTVAL ( x ) + 1 , mode ) ; PUT_CODE ( t , avr_normalize_condition ( GET_CODE ( t ) ) ) ; INSN_CODE ( next ) = - 1 ; INSN_CODE ( insn ) = - 1 ; } } } } } </s>

This function optimizes conditional jumps .


<s> void SparcRegisterInfo :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const { } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s>
void
AMDGPUAsmPrinter
::
emitEndOfAsmFile
(
Module
&
M
)
{
if
(
!
getTargetStreamer
(
)
)
return
;
if
(
TM
.
getTargetTriple
(
)
.
getOS
(
)
!=
Triple
::
AMDHSA
||
isHsaAbiVersion2
(
getGlobalSTI
(
)
)
)
{
std
::
string
ISAVersionString
;
raw_string_ostream
ISAVersionStream
(
ISAVersionString
)
;
IsaInfo
::
streamIsaVersion
(
getGlobalSTI
(
)
,
ISAVersionStream
)
;
getTargetStreamer
(
)
->
EmitISAVersion
(
ISAVersionStream
.
str
(
)
)
;
}
if
(
TM
.
getTargetTriple
(
)
.
getOS
(
)
==
Triple
::
AMDHSA
)
{
HSAMetadataStream
->
end
(
)
;
bool
Success
=
HSAMetadataStream
->
emitTo
(
*
getTargetStreamer
(
)
)
;
(
void
)
Success
;
assert
(
Success
&&
"Malformed HSA Metadata"
)
;
}
}
</s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> static bool ix86_check_avx_upper_register ( const_rtx exp ) { if ( SUBREG_P ( exp ) ) exp = SUBREG_REG ( exp ) ; return ( REG_P ( exp ) && ( VALID_AVX256_REG_OR_OI_MODE ( GET_MODE ( exp ) ) || VALID_AVX512F_REG_OR_XI_MODE ( GET_MODE ( exp ) ) ) ) ; } </s>

Check if a 256bit or 512 bit AVX register is referenced inside of EXP .


<s> const uint32_t * ARMBaseRegisterInfo :: getCallPreservedMask ( CallingConv :: ID ) const { return ( STI . isTargetIOS ( ) ) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


"Trying to spill a register in naked function "

Store the specified register of the given register class to the specified stack frame index .


<s> void assignValueToReg ( Register ValVReg , Register PhysReg , CCValAssign VA ) override { MIB . addUse ( PhysReg , RegState :: Implicit ) ; Register ExtReg = extendRegisterMin32 ( * this , ValVReg , VA ) ; MIRBuilder . buildCopy ( PhysReg , ExtReg ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> const MCPhysReg * XCoreRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const MCPhysReg CalleeSavedRegs [ ] = { XCore :: R4 , XCore :: R5 , XCore :: R6 , XCore :: R7 , XCore :: R8 , XCore :: R9 , XCore :: R10 , 0 } ; static const MCPhysReg CalleeSavedRegsFP [ ] = { XCore :: R4 , XCore :: R5 , XCore :: R6 , XCore :: R7 , XCore :: R8 , XCore :: R9 , 0 } ; const TargetFrameLowering * TFI = MF -> getSubtarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( * MF ) ) return CalleeSavedRegsFP ; return CalleeSavedRegs ; } </s>


<s>
SDNode
*
MipsDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
nullptr
;
}
std
::
pair
<
bool
,
SDNode
*
>
Ret
=
selectNode
(
Node
)
;
if
(
Ret
.
first
)
return
Ret
.
second
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
return
getGlobalBaseReg
(
)
;
case
ISD
::
LOAD
:
case
ISD
::
STORE
:
assert
(
(
Subtarget
->
systemSupportsUnalignedAccess
(
)
||
cast
<
MemSDNode
>
(
Node
)
->
getMemoryVT
(
)
.
getSizeInBits
(
)
/
8
<=
cast
<
MemSDNode
>
(
Node
)
->
getAlignment
(
)
)
&&
"Unexpected unaligned loads/stores."
)
;
break
;
}
SDNode
*
ResNode
=
SelectCode
(
Node
)
;
DEBUG
(
errs
(
)
<<
"=> "
)
;
if
(
ResNode
==
nullptr
||
ResNode
==
Node
)
DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
else
DEBUG
(
ResNode
->
dump
(
CurDAG
)
)
;
DEBUG
(
errs
(
)
<<
"\n"
)
;
return
ResNode
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

Mips
Mips
"Selecting: "
"\n"
"== "
"\n"
1
ISD::GLOBAL_OFFSET_TABLE
ISD::LOAD
ISD::STORE
8
"Unexpected unaligned loads/stores."
"=> "
"\n"


<s> const RISCVSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
SDValue
MSP430TargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
if
(
CallConv
==
CallingConv
::
MSP430_INTR
&&
!
Outs
.
empty
(
)
)
{
llvm_report_error
(
"ISRs cannot return any value"
)
;
return
SDValue
(
)
;
}
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_MSP430
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
if
(
RVLocs
[
i
]
.
isRegLoc
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
Outs
[
i
]
.
Val
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
unsigned
Opc
=
(
CallConv
==
CallingConv
::
MSP430_INTR
MSP430ISD
::
RETI_FLAG
:
MSP430ISD
::
RET_FLAG
)
;
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
Opc
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
return
DAG
.
getNode
(
Opc
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> SDValue MipsTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SDNode * CallNode , const Type * RetTy ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; MipsCC MipsCCInfo ( CallConv , IsO32 , CCInfo ) ; MipsCCInfo . analyzeCallResult ( Ins , getTargetMachine ( ) . Options . UseSoftFloat , CallNode , RetTy ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( 1 ) ; InFlag = Val . getValue ( 2 ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( ISD :: BITCAST , DL , RVLocs [ i ] . getValVT ( ) , Val ) ; InVals . push_back ( Val ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> Status merge ( const Status & S ) const { return Status ( ( Mask | S . Mask ) , ( ( Mode & ~ S . Mask ) | ( S . Mode & S . Mask ) ) ) ; } </s>


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( ( unsigned ) Kind , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { case Cpu0 :: fixup_Cpu0_16 : FullSize = 2 ; break ; default : FullSize = 4 ; break ; } uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - 1 - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> gimple * gimple_folder :: fold_to_vl_pred ( unsigned int vl ) { tree vectype = TREE_TYPE ( lhs ) ; tree element_type = TREE_TYPE ( vectype ) ; tree minus_one = build_all_ones_cst ( element_type ) ; tree zero = build_zero_cst ( element_type ) ; unsigned int element_bytes = type_suffix ( 0 ) . element_bytes ; unsigned int count = constant_lower_bound ( TYPE_VECTOR_SUBPARTS ( vectype ) ) ; gcc_assert ( vl * element_bytes <= count ) ; tree_vector_builder builder ( vectype , count , 2 ) ; for ( unsigned int i = 0 ; i < count * 2 ; ++ i ) { bool bit = ( i & ( element_bytes - 1 ) ) == 0 && i < vl * element_bytes ; builder . quick_push ( bit ? minus_one : zero ) ; } return gimple_build_assign ( lhs , builder . build ( ) ) ; } </s>

Fold an operation to a constant predicate in which the first VL elements are set and the rest are clear . Take the element size from type suffix 0 .


<s> int xt_true_regnum ( rtx x ) { if ( GET_CODE ( x ) == REG ) { if ( reg_renumber && REGNO ( x ) >= FIRST_PSEUDO_REGISTER && reg_renumber [ REGNO ( x ) ] >= 0 ) return reg_renumber [ REGNO ( x ) ] ; return REGNO ( x ) ; } if ( GET_CODE ( x ) == SUBREG ) { int base = xt_true_regnum ( SUBREG_REG ( x ) ) ; if ( base >= 0 && base < FIRST_PSEUDO_REGISTER ) return base + subreg_regno_offset ( REGNO ( SUBREG_REG ( x ) ) , GET_MODE ( SUBREG_REG ( x ) ) , SUBREG_BYTE ( x ) , GET_MODE ( x ) ) ; } return - 1 ; } </s>

This is just like the standard true_regnum ( ) function except that it works even when reg_renumber is not initialized .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Thumb IT blocks insertion pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
const
char
*
getImageHandleSymbol
(
unsigned
Idx
)
const
{
assert
(
ImageHandleList
.
size
(
)
>
Idx
&&
"Bad index"
)
;
return
ImageHandleList
[
Idx
]
.
c_str
(
)
;
}
</s>

Returns the symbol name at the given index .


"MSA requires a 64-bit FPU register file (FR=1 mode). "

This constructor initializes the data members to match that of the specified triple .


<s> static rtx restore_gprs ( rtx base , int offset , int first , int last ) { rtx addr , insn ; addr = plus_constant ( Pmode , base , offset ) ; addr = gen_frame_mem ( Pmode , addr ) ; if ( first == last ) { if ( TARGET_64BIT ) insn = gen_movdi ( gen_rtx_REG ( Pmode , first ) , addr ) ; else insn = gen_movsi ( gen_rtx_REG ( Pmode , first ) , addr ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; return insn ; } insn = gen_load_multiple ( gen_rtx_REG ( Pmode , first ) , addr , GEN_INT ( last - first + 1 ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; return insn ; } </s>

Generate insn to restore registers FIRST to LAST from the register save area located at offset OFFSET relative to register BASE .


<s> void BTFDebug :: emitCommonHeader ( ) { OS . AddComment ( "0x" + Twine :: utohexstr ( BTF :: MAGIC ) ) ; OS . EmitIntValue ( BTF :: MAGIC , 2 ) ; OS . EmitIntValue ( BTF :: VERSION , 1 ) ; OS . EmitIntValue ( 0 , 1 ) ; } </s>

Emit the common part of the header for this unit .


<s> void X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; const X86RegisterInfo & RegInfo = * static_cast < const X86RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; unsigned StackPtr = RegInfo . getStackRegister ( ) ; bool reseveCallFrame = hasReservedCallFrame ( MF ) ; int Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; const X86Subtarget & STI = MF . getTarget ( ) . getSubtarget < X86Subtarget > ( ) ; bool IsLP64 = STI . isTarget64BitLP64 ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reseveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t CalleeAmt = isDestroy ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reseveCallFrame ) { if ( Amount == 0 ) return ; unsigned StackAlign = MF . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = nullptr ; if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( IsLP64 , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; Amount -= CalleeAmt ; if ( Amount ) { unsigned Opc = getADDriOpcode ( IsLP64 , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } return ; } if ( Opcode == TII . getCallFrameDestroyOpcode ( ) && CalleeAmt ) { unsigned Opc = getSUBriOpcode ( IsLP64 , CalleeAmt ) ; MachineInstr * New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! std :: prev ( I ) -> isCall ( ) ) -- I ; MBB . insert ( I , New ) ; } } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static ARMOperand * CreateMem ( unsigned BaseRegNum , const MCConstantExpr * OffsetImm , unsigned OffsetRegNum , ARM_AM :: ShiftOpc ShiftType , unsigned ShiftImm , unsigned Alignment , bool isNegative , SMLoc S , SMLoc E ) { ARMOperand * Op = new ARMOperand ( k_Memory ) ; Op -> Memory . BaseRegNum = BaseRegNum ; Op -> Memory . OffsetImm = OffsetImm ; Op -> Memory . OffsetRegNum = OffsetRegNum ; Op -> Memory . ShiftType = ShiftType ; Op -> Memory . ShiftImm = ShiftImm ; Op -> Memory . Alignment = Alignment ; Op -> Memory . isNegative = isNegative ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>


"Running spec function '%s' with %d args\n\n"

"strange device name %qs after %qs: bad character %qc"

Implement spec function ` device-specs-file麓 . Compose -specs= < specs-file-name > % s . If everything went well then argv [ 0 ] is the inflated ( absolute ) specs directory and argv [ 1 ] is a device or core name as supplied by -mmcu= * . When building GCC the path might be relative .


<s> static int mcore_and_cost ( rtx x ) { int val ; if ( GET_CODE ( XEXP ( x , 1 ) ) != CONST_INT ) return 2 ; val = INTVAL ( XEXP ( x , 1 ) ) ; if ( CONST_OK_FOR_K ( val ) || CONST_OK_FOR_M ( ~ val ) ) return 2 ; else if ( const_ok_for_mcore ( val ) ) return 3 ; else if ( TARGET_HARDLIT && mcore_const_ok_for_inline ( val ) ) return 4 ; return 5 ; } </s>

What does an and instruction cost - we do this b/c immediates may have been relaxed . We want to ensure that cse will cse relaxed immeds out . Otherwise we 'll get bad code ( multiple reloads of the same const ) .


<s> bool AMDGPUAlwaysInline :: runOnModule ( Module & M ) { std :: vector < Function * > FuncsToClone ; for ( Module :: iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) { Function & F = * I ; if ( ! F . hasLocalLinkage ( ) && ! F . isDeclaration ( ) && ! F . use_empty ( ) && ! F . hasFnAttribute ( Attribute :: NoInline ) ) FuncsToClone . push_back ( & F ) ; } for ( Function * F : FuncsToClone ) { ValueToValueMapTy VMap ; Function * NewFunc = CloneFunction ( F , VMap , false ) ; NewFunc -> setLinkage ( GlobalValue :: InternalLinkage ) ; F -> getParent ( ) -> getFunctionList ( ) . push_back ( NewFunc ) ; F -> replaceAllUsesWith ( NewFunc ) ; } for ( Module :: iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) { Function & F = * I ; if ( F . hasLocalLinkage ( ) && ! F . hasFnAttribute ( Attribute :: NoInline ) ) { F . addFnAttr ( Attribute :: AlwaysInline ) ; } } return false ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s>
bool
runOnMachineFunction
(
MachineFunction
&
MF
)
override
{
LLVM_DEBUG
(
dbgs
(
)
<<
"### runOnMachineFunction\n"
)
;
Subtarget
=
&
MF
.
getSubtarget
<
Comet2Subtarget
>
(
)
;
return
SelectionDAGISel
::
runOnMachineFunction
(
MF
)
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> rtx function_expander :: use_ternop_insn ( bool vd_accum_p , insn_code icode ) { machine_mode mode = TYPE_MODE ( builtin_types [ type . index ] . vector ) ; int arg_offset = 0 ; if ( use_real_mask_p ( pred ) ) add_input_operand ( arg_offset ++ ) ; else add_all_one_mask_operand ( mask_mode ( ) ) ; rtx vd = expand_normal ( CALL_EXPR_ARG ( exp , arg_offset ++ ) ) ; rtx vs1 = expand_normal ( CALL_EXPR_ARG ( exp , arg_offset ++ ) ) ; rtx vs2 = expand_normal ( CALL_EXPR_ARG ( exp , arg_offset ++ ) ) ; if ( VECTOR_MODE_P ( GET_MODE ( vs1 ) ) ) { if ( ! vd_accum_p ) add_input_operand ( mode , vd ) ; add_input_operand ( mode , vs1 ) ; add_input_operand ( mode , vs2 ) ; if ( vd_accum_p ) add_input_operand ( mode , vd ) ; add_input_operand ( mode , vd ) ; } else { add_input_operand ( GET_MODE_INNER ( mode ) , vs1 ) ; if ( vd_accum_p ) { add_input_operand ( mode , vs2 ) ; add_input_operand ( mode , vd ) ; } else { add_input_operand ( mode , vd ) ; add_input_operand ( mode , vs2 ) ; } add_input_operand ( mode , vd ) ; } for ( int argno = arg_offset ; argno < call_expr_nargs ( exp ) ; argno ++ ) add_input_operand ( argno ) ; add_input_operand ( Pmode , get_tail_policy_for_pred ( pred ) ) ; add_input_operand ( Pmode , get_mask_policy_for_pred ( pred ) ) ; add_input_operand ( Pmode , get_avl_type_rtx ( avl_type :: NONVLMAX ) ) ; return generate_insn ( icode ) ; } </s>

Implement the call using instruction ICODE , with a 1:1 mapping between arguments and input operands .


<s> function_sym_iterator HSACodeObject :: functions_begin ( ) const { auto TextIdxOr = getTextSectionIdx ( ) ; if ( ! TextIdxOr ) return functions_end ( ) ; auto TextIdx = TextIdxOr . get ( ) ; return function_sym_iterator ( symbol_begin ( ) , symbol_end ( ) , [ this , TextIdx ] ( const SymbolRef & Sym ) -> bool { auto ExpectedFunction = FunctionSym :: asFunctionSym ( getSymbol ( Sym . getRawDataRefImpl ( ) ) ) ; if ( ! ExpectedFunction ) { consumeError ( ExpectedFunction . takeError ( ) ) ; return false ; } auto Function = ExpectedFunction . get ( ) ; if ( Function -> st_shndx != TextIdx ) return false ; return true ; } ) ; } </s>


"All AArch64 cmps should have 2 operands"

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> bool runOnFunction ( Function & F ) override { Func = & F ; DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; return ProcessFunction ( ) ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void MBlazeFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MBlazeFunctionInfo * MBlazeFI = MF . getInfo < MBlazeFunctionInfo > ( ) ; const MBlazeInstrInfo & TII = * static_cast < const MBlazeInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; llvm :: CallingConv :: ID CallConv = MF . getFunction ( ) -> getCallingConv ( ) ; bool requiresRA = CallConv == llvm :: CallingConv :: MBLAZE_INTR ; int FPOffset = MBlazeFI -> getFPStackOffset ( ) ; int RAOffset = MBlazeFI -> getRAStackOffset ( ) ; if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( MBlaze :: ADD ) , MBlaze :: R1 ) . addReg ( MBlaze :: R19 ) . addReg ( MBlaze :: R0 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( MBlaze :: LWI ) , MBlaze :: R19 ) . addReg ( MBlaze :: R1 ) . addImm ( FPOffset ) ; } if ( MFI -> adjustsStack ( ) || requiresRA ) { BuildMI ( MBB , MBBI , dl , TII . get ( MBlaze :: LWI ) , MBlaze :: R15 ) . addReg ( MBlaze :: R1 ) . addImm ( RAOffset ) ; } int StackSize = ( int ) MFI -> getStackSize ( ) ; if ( StackSize ) { BuildMI ( MBB , MBBI , dl , TII . get ( MBlaze :: ADDIK ) , MBlaze :: R1 ) . addReg ( MBlaze :: R1 ) . addImm ( StackSize ) ; } } </s>


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { LLT p0 = LLT :: pointer ( 0 , DL . getPointerSizeInBits ( 0 ) ) ; LLT SType = LLT :: scalar ( DL . getPointerSizeInBits ( 0 ) ) ; Register SPReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildCopy ( SPReg , STI . getRegisterInfo ( ) -> getStackRegister ( ) ) ; Register OffsetReg = MRI . createGenericVirtualRegister ( SType ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; Register AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildPtrAdd ( AddrReg , SPReg , OffsetReg ) ; MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s>
StringRef
getPassName
(
)
const
override
{
return
"RV16K Assembly Printer"
;
}
</s>


<s> bool AArch64Subtarget :: supportsAddressTopByteIgnored ( ) const { if ( ! UseAddressTopByteIgnored ) return false ; if ( TargetTriple . isiOS ( ) ) { return TargetTriple . getiOSVersion ( ) >= VersionTuple ( 8 ) ; } return false ; } </s>

CPU has TBI ( top byte of addresses is ignored during HW address translation ) and OS enables it .


<s> void aarch64_emit_sve_pred_move ( rtx dest , rtx pred , rtx src ) { emit_insn ( gen_rtx_SET ( dest , gen_rtx_UNSPEC ( GET_MODE ( dest ) , gen_rtvec ( 2 , pred , src ) , UNSPEC_MERGE_PTRUE ) ) ) ; } </s>

Emit an SVE predicated move from SRC to DEST . PRED is a predicate that is known to contain PTRUE .


"Missing call preserved mask for calling convention"

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


<s> bool isMachineVerifierClean ( ) const override { return false ; } </s>

Returns true if the target is expected to pass all machine verifier checks .


<s> static bool pdp11_scalar_mode_supported_p ( scalar_mode mode ) { if ( mode == SFmode ) return true ; return default_scalar_mode_supported_p ( mode ) ; } </s>


<s> bool AMDGPUAnnotateKernelFeatures :: runOnSCC ( CallGraphSCC & SCC ) { Module & M = SCC . getCallGraph ( ) . getModule ( ) ; Triple TT ( M . getTargetTriple ( ) ) ; bool Changed = false ; for ( CallGraphNode * I : SCC ) { Function * F = I -> getFunction ( ) ; if ( ! F || F -> isDeclaration ( ) ) continue ; Changed |= addFeatureAttributes ( * F ) ; } return Changed ; } </s>

runOnSCC - This method should be implemented by the subclass to perform whatever action is necessary for the specified SCC .


<s> MCSection * getExplicitSectionGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler & Mang , const TargetMachine & TM ) const override { return DataSection ; } </s>

Targets should implement this method to assign a section to globals with an explicit section specfied .


<s> const MachineBasicBlock * getMBB ( ) const { return MBB ; } </s>

Return a reference to the basic block containing this bundle .


<s> bool ARMBaseInstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { ARMCC :: CondCodes CC = ( ARMCC :: CondCodes ) ( int ) Cond [ 0 ] . getImm ( ) ; Cond [ 0 ] . setImm ( ARMCC :: getOppositeCondition ( CC ) ) ; return false ; } </s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .

ARM ARM ARMCC::CondCodes ARMCC::CondCodes 0 0 ARMCC::getOppositeCondition


<s> bool WinEHStatePass :: doInitialization ( Module & M ) { TheModule = & M ; FrameEscape = Intrinsic :: getDeclaration ( TheModule , Intrinsic :: localescape ) ; FrameRecover = Intrinsic :: getDeclaration ( TheModule , Intrinsic :: localrecover ) ; FrameAddress = Intrinsic :: getDeclaration ( TheModule , Intrinsic :: frameaddress ) ; RestoreFrame = Intrinsic :: getDeclaration ( TheModule , Intrinsic :: x86_seh_restoreframe ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .

X86 Intrinsic::getDeclaration Intrinsic::localescape Intrinsic::getDeclaration Intrinsic::localrecover Intrinsic::getDeclaration Intrinsic::frameaddress Intrinsic::getDeclaration Intrinsic::x86_seh_restoreframe


<s> int visium_interrupt_function_p ( void ) { return lookup_attribute ( "interrupt" , DECL_ATTRIBUTES ( current_function_decl ) ) != NULL_TREE ; } </s>

Return non-zero if the current function is an interrupt function .


<s> bool intersects ( const RegisterSet & Rs ) const { return Bits . anyCommon ( Rs . Bits ) ; } </s>


<s> static int do_reorder_for_imul ( rtx_insn * * ready , int n_ready ) { rtx_insn * insn ; rtx set , insn1 , insn2 ; sd_iterator_def sd_it ; dep_t dep ; int index = - 1 ; int i ; if ( ! TARGET_BONNELL ) return index ; insn = ready [ n_ready - 1 ] ; set = single_set ( insn ) ; if ( ! set ) return index ; if ( ! ( GET_CODE ( SET_SRC ( set ) ) == MULT && GET_MODE ( SET_SRC ( set ) ) == SImode ) ) return index ; for ( i = n_ready - 2 ; i >= 0 ; i -- ) { insn = ready [ i ] ; if ( ! NONDEBUG_INSN_P ( insn ) ) continue ; insn2 = PATTERN ( insn ) ; if ( GET_CODE ( insn2 ) == PARALLEL ) insn2 = XVECEXP ( insn2 , 0 , 0 ) ; if ( GET_CODE ( insn2 ) == SET && GET_CODE ( SET_SRC ( insn2 ) ) == MULT && GET_MODE ( SET_SRC ( insn2 ) ) == SImode ) continue ; FOR_EACH_DEP ( insn , SD_LIST_FORW , sd_it , dep ) { rtx con ; con = DEP_CON ( dep ) ; if ( ! NONDEBUG_INSN_P ( con ) ) continue ; insn1 = PATTERN ( con ) ; if ( GET_CODE ( insn1 ) == PARALLEL ) insn1 = XVECEXP ( insn1 , 0 , 0 ) ; if ( GET_CODE ( insn1 ) == SET && GET_CODE ( SET_SRC ( insn1 ) ) == MULT && GET_MODE ( SET_SRC ( insn1 ) ) == SImode ) { sd_iterator_def sd_it1 ; dep_t dep1 ; index = i ; FOR_EACH_DEP ( con , SD_LIST_BACK , sd_it1 , dep1 ) { rtx pro ; pro = DEP_PRO ( dep1 ) ; if ( ! NONDEBUG_INSN_P ( pro ) ) continue ; if ( pro != insn ) index = - 1 ; } if ( index >= 0 ) break ; } } if ( index >= 0 ) break ; } return index ; } </s>

Try to reorder ready list to take advantage of Atom pipelined IMUL execution . It is applied if ( 1 ) IMUL instruction is on the top of list ; ( 2 ) There exists the only producer of independent IMUL instruction in ready list . Return index of IMUL producer if it was found and -1 otherwise .


<s> void mips_expand_epilogue ( int sibcall_p ) { HOST_WIDE_INT step1 , step2 ; rtx base , target ; if ( ! sibcall_p && mips_can_use_return_insn ( ) ) { emit_jump_insn ( gen_return ( ) ) ; return ; } step1 = cfun -> machine -> frame . total_size ; step2 = 0 ; if ( ! frame_pointer_needed ) base = stack_pointer_rtx ; else { base = hard_frame_pointer_rtx ; if ( TARGET_MIPS16 ) step1 -= cfun -> machine -> frame . args_size ; } if ( ( cfun -> machine -> frame . mask | cfun -> machine -> frame . fmask ) != 0 ) { step2 = MIN ( step1 , MIPS_MAX_FIRST_STACK_STEP ) ; step1 -= step2 ; } target = base ; if ( step1 > 0 ) { rtx adjust ; adjust = GEN_INT ( step1 ) ; if ( ! SMALL_OPERAND ( step1 ) ) { emit_move_insn ( MIPS_EPILOGUE_TEMP ( Pmode ) , adjust ) ; adjust = MIPS_EPILOGUE_TEMP ( Pmode ) ; } if ( ! TARGET_MIPS16 ) target = stack_pointer_rtx ; emit_insn ( gen_add3_insn ( target , base , adjust ) ) ; } if ( target != stack_pointer_rtx ) emit_move_insn ( stack_pointer_rtx , target ) ; if ( TARGET_ABICALLS && TARGET_NEWABI && ! TARGET_EXPLICIT_RELOCS ) emit_insn ( gen_blockage ( ) ) ; mips_for_each_saved_reg ( cfun -> machine -> frame . total_size - step2 , mips_restore_reg ) ; if ( step2 > 0 ) emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( step2 ) ) ) ; if ( current_function_calls_eh_return ) { if ( TARGET_MIPS16 ) { emit_move_insn ( MIPS_EPILOGUE_TEMP ( Pmode ) , stack_pointer_rtx ) ; emit_insn ( gen_add3_insn ( MIPS_EPILOGUE_TEMP ( Pmode ) , MIPS_EPILOGUE_TEMP ( Pmode ) , EH_RETURN_STACKADJ_RTX ) ) ; emit_move_insn ( stack_pointer_rtx , MIPS_EPILOGUE_TEMP ( Pmode ) ) ; } else emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , EH_RETURN_STACKADJ_RTX ) ) ; } if ( ! sibcall_p ) { if ( TARGET_MIPS16 && ( cfun -> machine -> frame . mask & RA_MASK ) != 0 ) emit_jump_insn ( gen_return_internal ( gen_rtx_REG ( Pmode , GP_REG_FIRST + 7 ) ) ) ; else emit_jump_insn ( gen_return_internal ( gen_rtx_REG ( Pmode , GP_REG_FIRST + 31 ) ) ) ; } } </s>

Expand the epilogue into a bunch of separate insns . SIBCALL_P is true if this epilogue precedes a sibling call , false if it is for a normal `` epilogue '' pattern .


<s> bool runOnMachineFunction ( MachineFunction & F ) override { AArch64FI = F . getInfo < AArch64FunctionInfo > ( ) ; STI = static_cast < const AArch64Subtarget * > ( & F . getSubtarget ( ) ) ; bool Result = AsmPrinter :: runOnMachineFunction ( F ) ; emitXRayTable ( ) ; return Result ; } </s>

runOnMachineFunction - Emit the function body .


<s> const TargetRegisterClass * SIRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { if ( ST . hasMAIInsts ( ) && ( isVGPRClass ( RC ) || isAGPRClass ( RC ) ) ) { if ( RC == & AMDGPU :: VGPR_32RegClass || RC == & AMDGPU :: AGPR_32RegClass ) return & AMDGPU :: AV_32RegClass ; if ( RC == & AMDGPU :: VReg_64RegClass || RC == & AMDGPU :: AReg_64RegClass ) return & AMDGPU :: AV_64RegClass ; if ( RC == & AMDGPU :: VReg_64_Align2RegClass || RC == & AMDGPU :: AReg_64_Align2RegClass ) return & AMDGPU :: AV_64_Align2RegClass ; if ( RC == & AMDGPU :: VReg_96RegClass || RC == & AMDGPU :: AReg_96RegClass ) return & AMDGPU :: AV_96RegClass ; if ( RC == & AMDGPU :: VReg_96_Align2RegClass || RC == & AMDGPU :: AReg_96_Align2RegClass ) return & AMDGPU :: AV_96_Align2RegClass ; if ( RC == & AMDGPU :: VReg_128RegClass || RC == & AMDGPU :: AReg_128RegClass ) return & AMDGPU :: AV_128RegClass ; if ( RC == & AMDGPU :: VReg_128_Align2RegClass || RC == & AMDGPU :: AReg_128_Align2RegClass ) return & AMDGPU :: AV_128_Align2RegClass ; if ( RC == & AMDGPU :: VReg_160RegClass || RC == & AMDGPU :: AReg_160RegClass ) return & AMDGPU :: AV_160RegClass ; if ( RC == & AMDGPU :: VReg_160_Align2RegClass || RC == & AMDGPU :: AReg_160_Align2RegClass ) return & AMDGPU :: AV_160_Align2RegClass ; if ( RC == & AMDGPU :: VReg_192RegClass || RC == & AMDGPU :: AReg_192RegClass ) return & AMDGPU :: AV_192RegClass ; if ( RC == & AMDGPU :: VReg_192_Align2RegClass || RC == & AMDGPU :: AReg_192_Align2RegClass ) return & AMDGPU :: AV_192_Align2RegClass ; if ( RC == & AMDGPU :: VReg_256RegClass || RC == & AMDGPU :: AReg_256RegClass ) return & AMDGPU :: AV_256RegClass ; if ( RC == & AMDGPU :: VReg_256_Align2RegClass || RC == & AMDGPU :: AReg_256_Align2RegClass ) return & AMDGPU :: AV_256_Align2RegClass ; if ( RC == & AMDGPU :: VReg_512RegClass || RC == & AMDGPU :: AReg_512RegClass ) return & AMDGPU :: AV_512RegClass ; if ( RC == & AMDGPU :: VReg_512_Align2RegClass || RC == & AMDGPU :: AReg_512_Align2RegClass ) return & AMDGPU :: AV_512_Align2RegClass ; if ( RC == & AMDGPU :: VReg_1024RegClass || RC == & AMDGPU :: AReg_1024RegClass ) return & AMDGPU :: AV_1024RegClass ; if ( RC == & AMDGPU :: VReg_1024_Align2RegClass || RC == & AMDGPU :: AReg_1024_Align2RegClass ) return & AMDGPU :: AV_1024_Align2RegClass ; } return TargetRegisterInfo :: getLargestLegalSuperClass ( RC , MF ) ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .


<s> void ARMTargetStreamer :: finish ( ) { ConstantPools -> emitAll ( Streamer ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> const MCSymbol * NVPTXAsmPrinter :: getFunctionFrameSymbol ( int ) const { SmallString < 128 > Str ; raw_svector_ostream ( Str ) << DEPOTNAME << getFunctionNumber ( ) ; return OutContext . getOrCreateSymbol ( Str ) ; } </s>

Return symbol for the function pseudo stack if the stack frame is not a register based .


<s>
MCFragment
*
AArch64AuthMCExpr
::
findAssociatedFragment
(
)
const
{
llvm_unreachable
(
"FIXME: what goes here?"
)
;
}
</s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s> bool SIInstrInfo :: hasVALU32BitEncoding ( unsigned Opcode ) const { if ( Opcode == AMDGPU :: V_MUL_LEGACY_F32_e64 && ST . hasGFX90AInsts ( ) ) return false ; int Op32 = AMDGPU :: getVOPe32 ( Opcode ) ; if ( Op32 == - 1 ) return false ; return pseudoToMCOpcode ( Op32 ) != - 1 ; } </s>

Return true if this 64-bit VALU instruction has a 32-bit encoding .


"WebAssembly does not use MCFixupKindInfo flags"

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool Cpu0TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( ! AM . HasBaseReg ) break ; return false ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> void rs6000_emit_cbranch ( machine_mode mode , rtx operands [ ] ) { rtx condition_rtx = rs6000_generate_compare ( operands [ 0 ] , mode ) ; rtx loc_ref = gen_rtx_LABEL_REF ( VOIDmode , operands [ 3 ] ) ; rtx ite = gen_rtx_IF_THEN_ELSE ( VOIDmode , condition_rtx , loc_ref , pc_rtx ) ; emit_jump_insn ( gen_rtx_SET ( pc_rtx , ite ) ) ; } </s>

Emit a branch of kind CODE to location LOC .


<s> bool FalkorHWPFFix :: runOnMachineFunction ( MachineFunction & Fn ) { auto & ST = static_cast < const AArch64Subtarget & > ( Fn . getSubtarget ( ) ) ; if ( ST . getProcFamily ( ) != AArch64Subtarget :: Falkor ) return false ; if ( skipFunction ( Fn . getFunction ( ) ) ) return false ; TII = static_cast < const AArch64InstrInfo * > ( ST . getInstrInfo ( ) ) ; TRI = ST . getRegisterInfo ( ) ; MachineLoopInfo & LI = getAnalysis < MachineLoopInfo > ( ) ; Modified = false ; for ( MachineLoop * I : LI ) for ( auto L = df_begin ( I ) , LE = df_end ( I ) ; L != LE ; ++ L ) if ( L -> empty ( ) ) runOnLoop ( * * L , Fn ) ; return Modified ; } </s>


<s> bool SITargetLowering :: getAddrModeArguments ( IntrinsicInst * II , SmallVectorImpl < Value * > & Ops , Type * & AccessTy ) const { switch ( II -> getIntrinsicID ( ) ) { case Intrinsic :: amdgcn_atomic_inc : case Intrinsic :: amdgcn_atomic_dec : case Intrinsic :: amdgcn_ds_ordered_add : case Intrinsic :: amdgcn_ds_ordered_swap : case Intrinsic :: amdgcn_ds_fadd : case Intrinsic :: amdgcn_ds_fmin : case Intrinsic :: amdgcn_ds_fmax : { Value * Ptr = II -> getArgOperand ( 0 ) ; AccessTy = II -> getType ( ) ; Ops . push_back ( Ptr ) ; return true ; } default : return false ; } } </s>

CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address .


"data area attributes cannot be specified for "

"data area of %q+D conflicts with previous declaration"

Handle a `` sda '' , `` tda '' or `` zda '' attribute ; arguments as in struct attribute_spec.handler .


<s> bool LEGInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { bool HasCondBranch = false ; TBB = nullptr ; FBB = nullptr ; for ( MachineInstr & MI : MBB ) { if ( MI . getOpcode ( ) == LEG :: B ) { MachineBasicBlock * TargetBB = MI . getOperand ( 0 ) . getMBB ( ) ; if ( HasCondBranch ) { FBB = TargetBB ; } else { TBB = TargetBB ; } } else if ( MI . getOpcode ( ) == LEG :: Bcc ) { MachineBasicBlock * TargetBB = MI . getOperand ( 1 ) . getMBB ( ) ; TBB = TargetBB ; Cond . push_back ( MI . getOperand ( 0 ) ) ; HasCondBranch = true ; } } return false ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> bool riscv_symbolic_constant_p ( rtx x , enum riscv_symbol_type * symbol_type ) { rtx offset ; split_const ( x , & x , & offset ) ; if ( UNSPEC_ADDRESS_P ( x ) ) { * symbol_type = UNSPEC_ADDRESS_TYPE ( x ) ; x = UNSPEC_ADDRESS ( x ) ; } else if ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF ) * symbol_type = riscv_classify_symbol ( x ) ; else return false ; if ( offset == const0_rtx ) return true ; switch ( * symbol_type ) { case SYMBOL_ABSOLUTE : case SYMBOL_PCREL : case SYMBOL_TLS_LE : return sext_hwi ( INTVAL ( offset ) , 32 ) == INTVAL ( offset ) ; default : return false ; } } </s>

Return true if X is a symbolic constant . If it is , store the type of the symbol in * SYMBOL_TYPE .


<s> static bool ix86_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( CC_REGNO_P ( regno ) ) return GET_MODE_CLASS ( mode ) == MODE_CC ; if ( GET_MODE_CLASS ( mode ) == MODE_CC || GET_MODE_CLASS ( mode ) == MODE_RANDOM || GET_MODE_CLASS ( mode ) == MODE_PARTIAL_INT ) return false ; if ( STACK_REGNO_P ( regno ) ) return VALID_FP_MODE_P ( mode ) ; if ( MASK_REGNO_P ( regno ) ) return ( VALID_MASK_REG_MODE ( mode ) || ( TARGET_AVX512BW && VALID_MASK_AVX512BW_MODE ( mode ) ) ) ; if ( BND_REGNO_P ( regno ) ) return VALID_BND_REG_MODE ( mode ) ; if ( SSE_REGNO_P ( regno ) ) { if ( TARGET_AVX512F && ( mode == XImode || VALID_AVX512F_REG_MODE ( mode ) || VALID_AVX512F_SCALAR_MODE ( mode ) ) ) return true ; if ( ( TARGET_AVX5124FMAPS || TARGET_AVX5124VNNIW ) && MOD4_SSE_REGNO_P ( regno ) && mode == V64SFmode ) return true ; if ( ( TARGET_AVX5124FMAPS || TARGET_AVX5124VNNIW ) && MOD4_SSE_REGNO_P ( regno ) && mode == V64SImode ) return true ; if ( TARGET_AVX512VL && ( mode == OImode || mode == TImode || VALID_AVX256_REG_MODE ( mode ) || VALID_AVX512VL_128_REG_MODE ( mode ) ) ) return true ; if ( EXT_REX_SSE_REGNO_P ( regno ) ) return false ; return ( ( TARGET_AVX && VALID_AVX256_REG_OR_OI_MODE ( mode ) ) || VALID_SSE_REG_MODE ( mode ) || VALID_SSE2_REG_MODE ( mode ) || VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( MMX_REGNO_P ( regno ) ) { return ( VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( mode == QImode ) { if ( ANY_QI_REGNO_P ( regno ) ) return true ; if ( ! TARGET_PARTIAL_REG_STALL ) return true ; if ( lra_in_progress ) return true ; return ! can_create_pseudo_p ( ) ; } else if ( VALID_INT_MODE_P ( mode ) ) return true ; else if ( VALID_FP_MODE_P ( mode ) ) return true ; else if ( VALID_DFP_MODE_P ( mode ) ) return true ; else if ( VALID_MMX_REG_MODE_3DNOW ( mode ) || VALID_MMX_REG_MODE ( mode ) ) return true ; return false ; } </s>

Return TRUE if hard register REGNO can hold a value of machine-mode MODE .


<s> const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> unsigned GCNSubtarget :: getOccupancyWithNumVGPRs ( unsigned VGPRs ) const { unsigned MaxWaves = getMaxWavesPerEU ( ) ; unsigned Granule = getVGPRAllocGranule ( ) ; if ( VGPRs < Granule ) return MaxWaves ; unsigned RoundedRegs = ( ( VGPRs + Granule - 1 ) / Granule ) * Granule ; return std :: min ( std :: max ( getTotalNumVGPRs ( ) / RoundedRegs , 1u ) , MaxWaves ) ; } </s>

Return the maximum number of waves per SIMD for kernels using VGPRs VGPRs .


<s>
LLVM_DUMP_METHOD
void
dump
(
)
{
errs
(
)
<<
"MSP430ISelAddressMode "
<<
this
<<
'\n'
;
if
(
BaseType
==
RegBase
&&
Base
.
Reg
.
getNode
(
)
!=
nullptr
)
{
errs
(
)
<<
"Base.Reg "
;
Base
.
Reg
.
getNode
(
)
->
dump
(
)
;
}
else
if
(
BaseType
==
FrameIndexBase
)
{
errs
(
)
<<
" Base.FrameIndex "
<<
Base
.
FrameIndex
<<
'\n'
;
}
errs
(
)
<<
" Disp "
<<
Disp
<<
'\n'
;
if
(
GV
)
{
errs
(
)
<<
"GV "
;
GV
->
dump
(
)
;
}
else
if
(
CP
)
{
errs
(
)
<<
" CP "
;
CP
->
dump
(
)
;
errs
(
)
<<
" Align"
<<
Alignment
.
value
(
)
<<
'\n'
;
}
else
if
(
ES
)
{
errs
(
)
<<
"ES "
;
errs
(
)
<<
ES
<<
'\n'
;
}
else
if
(
JT
!=
1
)
errs
(
)
<<
" JT"
<<
JT
<<
" Align"
<<
Alignment
.
value
(
)
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

MSP430
"MSP430ISelAddressMode "
"Base.Reg "
" Base.FrameIndex "
" Disp "
"GV "
" CP "
" Align"
"ES "
1
" JT"
" Align"


<s> int ix86_mode_needed ( int entity , rtx insn ) { enum attr_i387_cw mode ; if ( CALL_P ( insn ) || ( NONJUMP_INSN_P ( insn ) && ( asm_noperands ( PATTERN ( insn ) ) >= 0 || GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT ) ) ) return I387_CW_UNINITIALIZED ; if ( recog_memoized ( insn ) < 0 ) return I387_CW_ANY ; mode = get_attr_i387_cw ( insn ) ; switch ( entity ) { case I387_TRUNC : if ( mode == I387_CW_TRUNC ) return mode ; break ; case I387_FLOOR : if ( mode == I387_CW_FLOOR ) return mode ; break ; case I387_CEIL : if ( mode == I387_CW_CEIL ) return mode ; break ; case I387_MASK_PM : if ( mode == I387_CW_MASK_PM ) return mode ; break ; default : gcc_unreachable ( ) ; } return I387_CW_ANY ; } </s>

Return needed mode for entity in optimize_mode_switching pass .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"ARM64 Promote Constant"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> std :: pair < unsigned , const TargetRegisterClass * > NyuziTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 's' : case 'r' : return std :: make_pair ( 0U , & Nyuzi :: GPR32RegClass ) ; case 'v' : return std :: make_pair ( 0U , & Nyuzi :: VR512RegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> static void aarch64_set_current_function ( tree fndecl ) { if ( ! fndecl || fndecl == aarch64_previous_fndecl ) return ; tree old_tree = ( aarch64_previous_fndecl ? DECL_FUNCTION_SPECIFIC_TARGET ( aarch64_previous_fndecl ) : NULL_TREE ) ; tree new_tree = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( ! new_tree && old_tree ) new_tree = target_option_default_node ; if ( old_tree == new_tree ) return ; aarch64_previous_fndecl = fndecl ; cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( new_tree ) ) ; aarch64_save_restore_target_globals ( new_tree ) ; } </s>

Implement TARGET_SET_CURRENT_FUNCTION . Unpack the codegen decisions like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET of the function , if such exists . This function may be called multiple times on a single function so use aarch64_previous_fndecl to avoid setting up identical state .


<s> void GCNSubtarget :: overrideSchedPolicy ( MachineSchedPolicy & Policy , unsigned NumRegionInstrs ) const { Policy . ShouldTrackPressure = true ; Policy . OnlyTopDown = false ; Policy . OnlyBottomUp = false ; if ( ! enableSIScheduler ( ) ) Policy . ShouldTrackLaneMasks = true ; } </s>

Override generic scheduling policy within a region .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"AArch64 Promote Constant"
;
}
</s>


<s> bool X86InstrInfo :: hasLoadFromStackSlot ( const MachineInstr * MI , const MachineMemOperand * & MMO , int & FrameIndex ) const { for ( MachineInstr :: mmo_iterator o = MI -> memoperands_begin ( ) , oe = MI -> memoperands_end ( ) ; o != oe ; ++ o ) { if ( ( * o ) -> isLoad ( ) && ( * o ) -> getValue ( ) ) if ( const FixedStackPseudoSourceValue * Value = dyn_cast < const FixedStackPseudoSourceValue > ( ( * o ) -> getValue ( ) ) ) { FrameIndex = Value -> getFrameIndex ( ) ; MMO = * o ; return true ; } } return false ; } </s>

If the specified machine instruction has a load from a stack slot , return true along with the FrameIndices of the loaded stack slot and the machine mem operands containing the reference .


<s> TargetIRAnalysis XCoreTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( const Function & F ) { return TargetTransformInfo ( XCoreTTIImpl ( this , F ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


<s> unsigned int darwin_rs6000_special_round_type_align ( tree type , unsigned int computed , unsigned int specified ) { unsigned int align = MAX ( computed , specified ) ; if ( TYPE_PACKED ( type ) ) return align ; do { tree field = TYPE_FIELDS ( type ) ; while ( field != NULL && TREE_CODE ( field ) != FIELD_DECL ) field = DECL_CHAIN ( field ) ; if ( ! field ) break ; if ( DECL_PACKED ( field ) ) return align ; type = TREE_TYPE ( field ) ; while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; } while ( AGGREGATE_TYPE_P ( type ) ) ; if ( ! AGGREGATE_TYPE_P ( type ) && type != error_mark_node ) align = MAX ( align , TYPE_ALIGN ( type ) ) ; return align ; } </s>

Darwin increases record alignment to the natural alignment of the first field .


<s> static bool mem_ok_for_ldrd_strd ( rtx mem , rtx * base , rtx * offset ) { rtx addr ; gcc_assert ( base != NULL && offset != NULL ) ; if ( side_effects_p ( mem ) ) return false ; if ( GET_CODE ( mem ) == SUBREG ) return false ; gcc_assert ( MEM_P ( mem ) ) ; * offset = const0_rtx ; addr = XEXP ( mem , 0 ) ; if ( ! arm_legitimate_address_p ( DImode , addr , reload_in_progress || reload_completed ) ) return false ; if ( REG_P ( addr ) ) { * base = addr ; return true ; } else if ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == MINUS ) { * base = XEXP ( addr , 0 ) ; * offset = XEXP ( addr , 1 ) ; return ( REG_P ( * base ) && CONST_INT_P ( * offset ) ) ; } return false ; } </s>

Helper for gen_operands_ldrd_strd . Returns true iff the memory operand MEM 's address contains an immediate offset from the base register and has no side effects , in which case it sets BASE and OFFSET accordingly .


<s> bool X86GenericDisassembler :: getInstruction ( MCInst & instr , uint64_t & size , const MemoryObject & region , uint64_t address , raw_ostream & vStream ) const { InternalInstruction internalInstr ; int ret = decodeInstruction ( & internalInstr , regionReader , ( void * ) & region , logger , ( void * ) & vStream , address , fMode ) ; if ( ret ) { size = internalInstr . readerCursor - address ; return false ; } else { size = internalInstr . length ; translateInstruction ( instr , internalInstr ) ; return true ; } } </s>

Returns the disassembly of a single instruction .


<s> static bool ix86_class_likely_spilled_p ( reg_class_t rclass ) { switch ( rclass ) { case AREG : case DREG : case CREG : case BREG : case AD_REGS : case SIREG : case DIREG : case SSE_FIRST_REG : case FP_TOP_REG : case FP_SECOND_REG : case BND_REGS : return true ; default : break ; } return false ; } </s>


<s> bool OR1KPassConfig :: addPreEmitPass ( ) { addPass ( createOR1KDelaySlotFillerPass ( getOR1KTargetMachine ( ) ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static pad_direction s390_function_arg_padding ( machine_mode mode , const_tree type ) { if ( s390_function_arg_vector ( mode , type ) ) return PAD_UPWARD ; return default_function_arg_padding ( mode , type ) ; } </s>

Implement TARGET_FUNCTION_ARG_BOUNDARY . Vector arguments are left-justified when placed on the stack during parameter passing .


<s>
bool
SystemZInstrInfo
::
PredicateInstruction
(
MachineInstr
*
MI
,
ArrayRef
<
MachineOperand
>
Pred
)
const
{
assert
(
Pred
.
size
(
)
==
2
&&
"Invalid condition"
)
;
unsigned
CCValid
=
Pred
[
0
]
.
getImm
(
)
;
unsigned
CCMask
=
Pred
[
1
]
.
getImm
(
)
;
assert
(
CCMask
>
0
&&
CCMask
<
15
&&
"Invalid predicate"
)
;
unsigned
Opcode
=
MI
->
getOpcode
(
)
;
if
(
STI
.
hasLoadStoreOnCond
(
)
)
{
if
(
unsigned
CondOpcode
=
getConditionalMove
(
Opcode
)
)
{
MI
->
setDesc
(
get
(
CondOpcode
)
)
;
MachineInstrBuilder
(
*
MI
->
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
}
return
false
;
}
</s>

Convert the instruction into a predicated instruction .


<s> bool toc_relative_expr_p ( const_rtx op , bool strict ) { if ( ! TARGET_TOC ) return false ; if ( TARGET_CMODEL != CMODEL_SMALL ) { if ( strict && ! ( GET_CODE ( op ) == LO_SUM && REG_P ( XEXP ( op , 0 ) ) && INT_REG_OK_FOR_BASE_P ( XEXP ( op , 0 ) , strict ) ) ) return false ; if ( GET_CODE ( op ) == LO_SUM ) op = XEXP ( op , 1 ) ; } tocrel_base = op ; tocrel_offset = const0_rtx ; if ( GET_CODE ( op ) == PLUS && add_cint_operand ( XEXP ( op , 1 ) , GET_MODE ( op ) ) ) { tocrel_base = XEXP ( op , 0 ) ; tocrel_offset = XEXP ( op , 1 ) ; } return ( GET_CODE ( tocrel_base ) == UNSPEC && XINT ( tocrel_base , 1 ) == UNSPEC_TOCREL ) ; } </s>

Return true if OP is a toc pointer relative address ( the output of create_TOC_reference ) . If STRICT , do not match high part or non-split -mcmodel=large/medium toc pointer relative addresses .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"ARM A15 S->D optimizer"
;
}
</s>


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCInstFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
{
assert
(
0
&&
"relaxInstruction() unimplemented"
)
;
return
false
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .

PowerPC
0
"relaxInstruction() unimplemented"


<s> tree rs6000_builtin_decl ( unsigned code , bool ) { rs6000_gen_builtins fcode = ( rs6000_gen_builtins ) code ; if ( fcode >= RS6000_OVLD_MAX ) return error_mark_node ; return rs6000_builtin_decls [ code ] ; } </s>

Returns the rs6000 builtin decl for CODE .


<s>
StringRef
getPassName
(
)
const
override
{
return
"MCS51 Assembly Printer"
;
}
</s>


<s>
const
char
*
ashrsi3_out
(
rtx_insn
*
insn
,
rtx
operands
[
]
,
int
*
len
)
{
if
(
GET_CODE
(
operands
[
2
]
)
==
CONST_INT
)
{
int
k
;
int
*
t
=
len
;
if
(
!
len
)
len
=
&
k
;
switch
(
INTVAL
(
operands
[
2
]
)
)
{
case
8
:
{
int
reg0
=
true_regnum
(
operands
[
0
]
)
;
int
reg1
=
true_regnum
(
operands
[
1
]
)
;
*
len
=
6
;
if
(
reg0
<=
reg1
)
return
(
"mov %A0,%B1"
CR_TAB
"mov %B0,%C1"
CR_TAB
"mov %C0,%D1"
CR_TAB
"clr %D0"
CR_TAB
"sbrc %C0,7"
CR_TAB
"dec %D0"
)
;
else
return
(
"clr %D0"
CR_TAB
"sbrc %D1,7"
CR_TAB
"dec %D0"
CR_TAB
"mov %C0,%D1"
CR_TAB
"mov %B0,%C1"
CR_TAB
"mov %A0,%B1"
)
;
}
case
16
:
{
int
reg0
=
true_regnum
(
operands
[
0
]
)
;
int
reg1
=
true_regnum
(
operands
[
1
]
)
;
if
(
reg0
==
reg1
+
2
)
return
*
len
=
4
,
(
"clr %D0"
CR_TAB
"sbrc %B0,7"
CR_TAB
"com %D0"
CR_TAB
"mov %C0,%D0"
)
;
if
(
AVR_HAVE_MOVW
)
return
*
len
=
5
,
(
"movw %A0,%C1"
CR_TAB
"clr %D0"
CR_TAB
"sbrc %B0,7"
CR_TAB
"com %D0"
CR_TAB
"mov %C0,%D0"
)
;
else
return
*
len
=
6
,
(
"mov %B0,%D1"
CR_TAB
"mov %A0,%C1"
CR_TAB
"clr %D0"
CR_TAB
"sbrc %B0,7"
CR_TAB
"com %D0"
CR_TAB
"mov %C0,%D0"
)
;
}
case
24
:
return
*
len
=
6
,
(
"mov %A0,%D1"
CR_TAB
"clr %D0"
CR_TAB
"sbrc %A0,7"
CR_TAB
"com %D0"
CR_TAB
"mov %B0,%D0"
CR_TAB
"mov %C0,%D0"
)
;
default
:
if
(
INTVAL
(
operands
[
2
]
)
<
32
)
break
;
case
31
:
if
(
AVR_HAVE_MOVW
)
return
*
len
=
4
,
(
"lsl %D0"
CR_TAB
"sbc %A0,%A0"
CR_TAB
"mov %B0,%A0"
CR_TAB
"movw %C0,%A0"
)
;
else
return
*
len
=
5
,
(
"lsl %D0"
CR_TAB
"sbc %A0,%A0"
CR_TAB
"mov %B0,%A0"
CR_TAB
"mov %C0,%A0"
CR_TAB
"mov %D0,%A0"
)
;
}
len
=
t
;
}
out_shift_with_cnt
(
"asr %D0"
CR_TAB
"ror %C0"
CR_TAB
"ror %B0"
CR_TAB
"ror %A0"
,
insn
,
operands
,
len
,
4
)
;
return
""
;
}
</s>

32bit arithmetic shift right ( ( signed long ) x > > i )


<s> bool Z80TargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const { return isInt < 8 > ( Imm ) ; } </s>

Return true if the specified immediate is legal icmp immediate , that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register .


<s> inline bool isCatch ( unsigned Opc ) { switch ( Opc ) { case WebAssembly :: CATCH : case WebAssembly :: CATCH_S : case WebAssembly :: CATCH_ALL : case WebAssembly :: CATCH_ALL_S : return true ; default : return false ; } } </s>

Return 'true ' if the clause and index Idx is a catch clause .


<s> static bool lm32_hard_regno_mode_ok ( unsigned int regno , machine_mode ) { return G_REG_P ( regno ) ; } </s>


<s> bool PPCTargetMachine :: addPreEmitPass ( PassManagerBase & PM , bool Fast ) { PM . add ( createPPCBranchSelectionPass ( ) ) ; return false ; } </s>


<s> bool RISCVTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; for ( unsigned i = 0 , e = Outs . size ( ) ; i != e ; ++ i ) { MVT VT = Outs [ i ] . VT ; ISD :: ArgFlagsTy ArgFlags = Outs [ i ] . Flags ; if ( CC_RISCV ( MF . getDataLayout ( ) , i , VT , VT , CCValAssign :: Full , ArgFlags , CCInfo , true , true , nullptr ) ) return false ; } return true ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .

RISCV RISCV ISD::OutputArg 16 0 ISD::ArgFlagsTy RISCV


<s> void AAPPassConfig :: addPreEmitPass ( ) { addPass ( & BranchRelaxationPassID ) ; addPass ( createAAPShortInstrPeepholePass ( getAAPTargetMachine ( ) ) , false ) ; } </s>


<s> bool HexagonTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { EVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == ISD :: SEXTLOAD ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; if ( ST -> getValue ( ) . getValueType ( ) == MVT :: i64 && ST -> isTruncatingStore ( ) ) { return false ; } } else { return false ; } bool isInc = false ; bool isLegal = getIndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( isLegal ) { auto & HII = * Subtarget . getInstrInfo ( ) ; int32_t OffsetVal = cast < ConstantSDNode > ( Offset . getNode ( ) ) -> getSExtValue ( ) ; if ( HII . isValidAutoIncImm ( VT , OffsetVal ) ) { AM = isInc ? ISD :: POST_INC : ISD :: POST_DEC ; return true ; } } return false ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .


<s> bool enableMachineScheduler ( ) const override { return true ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


<s> static rtx frv_io_address_cookie ( rtx address ) { return ( GET_CODE ( address ) == CONST_INT ? GEN_INT ( INTVAL ( address ) / 8 * 8 ) : const0_rtx ) ; } </s>

Given that a __builtin_read or __builtin_write function is accessing address ADDRESS , return the value that should be used as operand 1 of the membar .


<s>
SDValue
PPCTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
unsigned
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCRetInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCRetInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_PPC
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
VT
=
VA
.
getValVT
(
)
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
VT
,
InFlag
)
.
getValue
(
1
)
;
InVals
.
push_back
(
Chain
.
getValue
(
0
)
)
;
InFlag
=
Chain
.
getValue
(
2
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> MachineInstr * X86InstrInfo :: optimizeLoadInstr ( MachineInstr * MI , const MachineRegisterInfo * MRI , unsigned & FoldAsLoadDefReg , MachineInstr * & DefMI ) const { if ( FoldAsLoadDefReg == 0 ) return 0 ; if ( MI -> mayLoad ( ) ) { FoldAsLoadDefReg = 0 ; return 0 ; } DefMI = MRI -> getVRegDef ( FoldAsLoadDefReg ) ; assert ( DefMI ) ; bool SawStore = false ; if ( ! DefMI -> isSafeToMove ( this , 0 , SawStore ) ) return 0 ; unsigned IdxEnd = ( MI -> isCommutable ( ) ) ? 2 : 1 ; for ( unsigned Idx = 0 ; Idx < IdxEnd ; Idx ++ ) { unsigned SrcOperandId = 0 ; bool FoundSrcOperand = false ; for ( unsigned i = 0 , e = MI -> getDesc ( ) . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg != FoldAsLoadDefReg ) continue ; if ( MO . getSubReg ( ) || MO . isDef ( ) || FoundSrcOperand ) return 0 ; SrcOperandId = i ; FoundSrcOperand = true ; } if ( ! FoundSrcOperand ) return 0 ; SmallVector < unsigned , 8 > Ops ; Ops . push_back ( SrcOperandId ) ; MachineInstr * FoldMI = foldMemoryOperand ( MI , Ops , DefMI ) ; if ( FoldMI ) { FoldAsLoadDefReg = 0 ; return FoldMI ; } if ( Idx == 1 ) { commuteInstruction ( MI , false ) ; return 0 ; } if ( MI -> isCommutable ( ) ) { MachineInstr * NewMI = commuteInstruction ( MI , false ) ; if ( ! NewMI ) return 0 ; if ( NewMI != MI ) { NewMI -> eraseFromParent ( ) ; return 0 ; } } } return 0 ; } </s>

optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use .


<s> int getInstrLatency ( const InstrItineraryData * ItinData , SDNode * Node ) const override { return 1 ; } </s>

Compute the instruction latency of a given instruction .


<s> void X86AsmPrinter :: emitBasicBlockEnd ( const MachineBasicBlock & MBB ) { if ( Subtarget -> hardenSlsRet ( ) || Subtarget -> hardenSlsIJmp ( ) ) { auto I = MBB . getLastNonDebugInstr ( ) ; if ( I != MBB . end ( ) ) { if ( ( Subtarget -> hardenSlsRet ( ) && isSimpleReturn ( * I ) ) || ( Subtarget -> hardenSlsIJmp ( ) && isIndirectBranchOrTailCall ( * I ) ) ) { MCInst TmpInst ; TmpInst . setOpcode ( X86 :: INT3 ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } } } AsmPrinter :: emitBasicBlockEnd ( MBB ) ; SMShadowTracker . emitShadowPadding ( * OutStreamer , getSubtargetInfo ( ) ) ; } </s>

Targets can override this to emit stuff at the end of a basic block .


<s> SMLoc getEndLoc ( ) const { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s>
bool
SILoadStoreOptimizer
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
*
MF
.
getFunction
(
)
)
)
return
false
;
const
SISubtarget
&
STM
=
MF
.
getSubtarget
<
SISubtarget
>
(
)
;
if
(
!
STM
.
loadStoreOptEnabled
(
)
)
return
false
;
TII
=
STM
.
getInstrInfo
(
)
;
TRI
=
&
TII
->
getRegisterInfo
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
AA
=
&
getAnalysis
<
AAResultsWrapperPass
>
(
)
.
getAAResults
(
)
;
assert
(
MRI
->
isSSA
(
)
&&
"Must be run on SSA"
)
;
DEBUG
(
dbgs
(
)
<<
"Running SILoadStoreOptimizer\n"
)
;
bool
Modified
=
false
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
Modified
|=
optimizeBlock
(
MBB
)
;
return
Modified
;
}
</s>

runOnMachineFunction - Emit the function body .

AMDGPU
SI
SI
SI
"Must be run on SSA"
"Running SILoadStoreOptimizer\n"


<s> bool M68kInstrInfo :: ExpandPUSH_POP ( MachineInstrBuilder & MIB , const MCInstrDesc & Desc , bool IsPush ) const { MachineBasicBlock :: iterator I = MIB . getInstr ( ) ; I ++ ; MachineBasicBlock & MBB = * MIB -> getParent ( ) ; MachineOperand MO = MIB -> getOperand ( 0 ) ; DebugLoc DL = MIB -> getDebugLoc ( ) ; if ( IsPush ) BuildMI ( MBB , I , DL , Desc ) . addReg ( RI . getStackRegister ( ) ) . add ( MO ) ; else BuildMI ( MBB , I , DL , Desc , MO . getReg ( ) ) . addReg ( RI . getStackRegister ( ) ) ; MIB -> eraseFromParent ( ) ; return true ; } </s>


<s> void Z80AsmBackend :: relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const { llvm_unreachable ( "Unimplemented" ) ; } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> TargetPassConfig * SparcTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new SparcPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .