<s> void s390_expand_atomic ( machine_mode mode , enum rtx_code code , rtx target , rtx mem , rtx val , bool after ) { struct alignment_context ac ; rtx cmp ; rtx new_rtx = gen_reg_rtx ( SImode ) ; rtx orig = gen_reg_rtx ( SImode ) ; rtx_code_label * csloop = gen_label_rtx ( ) ; gcc_assert ( ! target || register_operand ( target , VOIDmode ) ) ; gcc_assert ( MEM_P ( mem ) ) ; init_alignment_context ( & ac , mem , mode ) ; if ( ! ( ac . aligned && code == SET && MEM_P ( val ) ) ) val = s390_expand_mask_and_shift ( val , mode , ac . shift ) ; if ( code == PLUS || code == MINUS ) emit_move_insn ( orig , val ) ; else if ( code == MULT || code == AND ) val = expand_simple_binop ( SImode , XOR , val , ac . modemaski , NULL_RTX , 1 , OPTAB_DIRECT ) ; cmp = force_reg ( SImode , ac . memsi ) ; emit_label ( csloop ) ; emit_move_insn ( new_rtx , cmp ) ; switch ( code ) { case PLUS : case MINUS : val = expand_simple_binop ( SImode , code , new_rtx , orig , NULL_RTX , 1 , OPTAB_DIRECT ) ; val = expand_simple_binop ( SImode , AND , val , ac . modemask , NULL_RTX , 1 , OPTAB_DIRECT ) ; case SET : if ( ac . aligned && MEM_P ( val ) ) store_bit_field ( new_rtx , GET_MODE_BITSIZE ( mode ) , 0 , 0 , 0 , SImode , val , false , false ) ; else { new_rtx = expand_simple_binop ( SImode , AND , new_rtx , ac . modemaski , NULL_RTX , 1 , OPTAB_DIRECT ) ; new_rtx = expand_simple_binop ( SImode , IOR , new_rtx , val , NULL_RTX , 1 , OPTAB_DIRECT ) ; } break ; case AND : case IOR : case XOR : new_rtx = expand_simple_binop ( SImode , code , new_rtx , val , NULL_RTX , 1 , OPTAB_DIRECT ) ; break ; case MULT : new_rtx = expand_simple_binop ( SImode , AND , new_rtx , val , NULL_RTX , 1 , OPTAB_DIRECT ) ; new_rtx = expand_simple_binop ( SImode , XOR , new_rtx , ac . modemask , NULL_RTX , 1 , OPTAB_DIRECT ) ; break ; default : gcc_unreachable ( ) ; } s390_emit_jump ( csloop , s390_emit_compare_and_swap ( NE , cmp , ac . memsi , cmp , new_rtx , CCZ1mode ) ) ; if ( target ) convert_move ( target , expand_simple_binop ( SImode , LSHIFTRT , after ? new_rtx : cmp , ac . shift , NULL_RTX , 1 , OPTAB_DIRECT ) , 1 ) ; } </s>

Expand an atomic operation CODE of mode MODE . MEM is the memory location and VAL the value to play with . If AFTER is true then store the the value MEM holds after the operation , if AFTER is false then store the value MEM holds before the operation . If TARGET is zero then discard that value , else store it to TARGET .


<s> void AMDGPUAsmPrinter :: emitBasicBlockStart ( const MachineBasicBlock & MBB ) { if ( DumpCodeInstEmitter && ! isBlockOnlyReachableByFallthrough ( & MBB ) ) { DisasmLines . push_back ( ( Twine ( "BB" ) + Twine ( getFunctionNumber ( ) ) + "_" + Twine ( MBB . getNumber ( ) ) + ":" ) . str ( ) ) ; DisasmLineMaxLen = std :: max ( DisasmLineMaxLen , DisasmLines . back ( ) . size ( ) ) ; HexLines . push_back ( "" ) ; } AsmPrinter :: emitBasicBlockStart ( MBB ) ; } </s>

Targets can override this to emit stuff at the start of a basic block .


<s> void M68kInstrInfo :: AddZExt ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned Reg , MVT From , MVT To ) const { unsigned Mask , And ; if ( From == MVT :: i8 ) Mask = 0xFF ; else Mask = 0xFFFF ; if ( To == MVT :: i16 ) And = M68k :: AND16di ; else And = M68k :: AND32di ; BuildMI ( MBB , I , DL , get ( And ) , Reg ) . addReg ( Reg ) . addImm ( Mask ) ; } </s>


<s> static bool v2df_reduction_p ( rtx op ) { if ( GET_MODE ( op ) != V2DFmode ) return false ; enum rtx_code code = GET_CODE ( op ) ; if ( code != PLUS && code != SMIN && code != SMAX ) return false ; rtx concat = XEXP ( op , 0 ) ; if ( GET_CODE ( concat ) != VEC_CONCAT ) return false ; rtx select0 = XEXP ( concat , 0 ) ; rtx select1 = XEXP ( concat , 1 ) ; if ( GET_CODE ( select0 ) != VEC_SELECT || GET_CODE ( select1 ) != VEC_SELECT ) return false ; rtx reg0 = XEXP ( select0 , 0 ) ; rtx reg1 = XEXP ( select1 , 0 ) ; if ( ! rtx_equal_p ( reg0 , reg1 ) || ! REG_P ( reg0 ) ) return false ; rtx parallel0 = XEXP ( select0 , 1 ) ; rtx parallel1 = XEXP ( select1 , 1 ) ; if ( GET_CODE ( parallel0 ) != PARALLEL || GET_CODE ( parallel1 ) != PARALLEL ) return false ; if ( ! rtx_equal_p ( XVECEXP ( parallel0 , 0 , 0 ) , const1_rtx ) || ! rtx_equal_p ( XVECEXP ( parallel1 , 0 , 0 ) , const0_rtx ) ) return false ; return true ; } </s>

Return TRUE iff OP matches a V2DF reduction pattern . See the definition of vsx_reduc_ < VEC_reduc_name > _v2df in vsx.md .


<s> ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const override { ScheduleDAGMILive * DAG = createGenericSchedLive ( C ) ; DAG -> addMutation ( createMacroFusionDAGMutation ( DAG -> TII ) ) ; return DAG ; } </s>

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level .


<s> void PPCVSXSwapRemoval :: initialize ( MachineFunction & MFParm ) { MF = & MFParm ; MRI = & MF -> getRegInfo ( ) ; TII = MF -> getSubtarget < PPCSubtarget > ( ) . getInstrInfo ( ) ; const int InitialVectorSize ( 256 ) ; SwapVector . clear ( ) ; SwapVector . reserve ( InitialVectorSize ) ; EC = new EquivalenceClasses < int > ; } </s>

Initialize the strategy after building the DAG for a new region .


<s> static void mips_emit_binary ( enum rtx_code code , rtx target , rtx op0 , rtx op1 ) { emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_fmt_ee ( code , GET_MODE ( target ) , op0 , op1 ) ) ) ; } </s>

Emit an instruction of the form ( set TARGET ( CODE OP0 OP1 ) ) .


<s> tree find_instance ( bool * unsupported_builtin , ovlddata * * instance , rs6000_gen_builtins instance_code , rs6000_gen_builtins fcode , tree * types , tree * args ) { while ( * instance && ( * instance ) -> bifid != instance_code ) * instance = ( * instance ) -> next ; ovlddata * inst = * instance ; gcc_assert ( inst != NULL ) ; if ( ! inst -> fntype ) return error_mark_node ; tree fntype = rs6000_builtin_info [ inst -> bifid ] . fntype ; tree parmtype0 = TREE_VALUE ( TYPE_ARG_TYPES ( fntype ) ) ; tree parmtype1 = TREE_VALUE ( TREE_CHAIN ( TYPE_ARG_TYPES ( fntype ) ) ) ; if ( rs6000_builtin_type_compatible ( types [ 0 ] , parmtype0 ) && rs6000_builtin_type_compatible ( types [ 1 ] , parmtype1 ) ) { if ( rs6000_builtin_decl ( inst -> bifid , false ) != error_mark_node && rs6000_builtin_is_supported ( inst -> bifid ) ) { tree ret_type = TREE_TYPE ( inst -> fntype ) ; return altivec_build_resolved_builtin ( args , 2 , fntype , ret_type , inst -> bifid , fcode ) ; } else * unsupported_builtin = true ; } return error_mark_node ; } </s>

Look for a matching instance in a chain of instances . INSTANCE points to the chain of instances ; INSTANCE_CODE is the code identifying the specific built-in being searched for ; FCODE is the overloaded function code ; TYPES contains an array of two types that must match the types of the instance 's parameters ; and ARGS contains an array of two arguments to be passed to the instance . If found , resolve the built-in and return it , unless the built-in is not supported in context . In that case , set UNSUPPORTED_BUILTIN to true . If we do n't match , return error_mark_node and leave UNSUPPORTED_BUILTIN alone .


<s> void SparcELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; } </s>

This method must be called before any actual lowering is done .


<s>
bool
ARMTargetLowering
::
lowerInterleavedStore
(
StoreInst
*
SI
,
ShuffleVectorInst
*
SVI
,
unsigned
Factor
)
const
{
assert
(
Factor
>=
2
&&
Factor
<=
getMaxSupportedInterleaveFactor
(
)
&&
"Invalid interleave factor"
)
;
VectorType
*
VecTy
=
SVI
->
getType
(
)
;
assert
(
VecTy
->
getVectorNumElements
(
)
%
Factor
==
0
&&
"Invalid interleaved store"
)
;
unsigned
NumSubElts
=
VecTy
->
getVectorNumElements
(
)
/
Factor
;
Type
*
EltTy
=
VecTy
->
getVectorElementType
(
)
;
VectorType
*
SubVecTy
=
VectorType
::
get
(
EltTy
,
NumSubElts
)
;
const
DataLayout
&
DL
=
SI
->
getModule
(
)
->
getDataLayout
(
)
;
unsigned
SubVecSize
=
DL
.
getTypeAllocSizeInBits
(
SubVecTy
)
;
bool
EltIs64Bits
=
DL
.
getTypeAllocSizeInBits
(
EltTy
)
==
64
;
if
(
!
Subtarget
->
hasNEON
(
)
||
(
SubVecSize
!=
64
&&
SubVecSize
!=
128
)
||
EltIs64Bits
)
return
false
;
Value
*
Op0
=
SVI
->
getOperand
(
0
)
;
Value
*
Op1
=
SVI
->
getOperand
(
1
)
;
IRBuilder
<
>
Builder
(
SI
)
;
if
(
EltTy
->
isPointerTy
(
)
)
{
Type
*
IntTy
=
DL
.
getIntPtrType
(
EltTy
)
;
Type
*
IntVecTy
=
VectorType
::
get
(
IntTy
,
Op0
->
getType
(
)
->
getVectorNumElements
(
)
)
;
Op0
=
Builder
.
CreatePtrToInt
(
Op0
,
IntVecTy
)
;
Op1
=
Builder
.
CreatePtrToInt
(
Op1
,
IntVecTy
)
;
SubVecTy
=
VectorType
::
get
(
IntTy
,
NumSubElts
)
;
}
static
Intrinsic
::
ID
StoreInts
[
3
]
=
{
Intrinsic
::
arm_neon_vst2
,
Intrinsic
::
arm_neon_vst3
,
Intrinsic
::
arm_neon_vst4
}
;
SmallVector
<
Value
*
,
6
>
Ops
;
Type
*
Int8Ptr
=
Builder
.
getInt8PtrTy
(
SI
->
getPointerAddressSpace
(
)
)
;
Ops
.
push_back
(
Builder
.
CreateBitCast
(
SI
->
getPointerOperand
(
)
,
Int8Ptr
)
)
;
Type
*
Tys
[
]
=
{
Int8Ptr
,
SubVecTy
}
;
Function
*
VstNFunc
=
Intrinsic
::
getDeclaration
(
SI
->
getModule
(
)
,
StoreInts
[
Factor
2
]
,
Tys
)
;
for
(
unsigned
i
=
0
;
i
<
Factor
;
i
++
)
Ops
.
push_back
(
Builder
.
CreateShuffleVector
(
Op0
,
Op1
,
getSequentialMask
(
Builder
,
NumSubElts
*
i
,
NumSubElts
)
)
)
;
Ops
.
push_back
(
Builder
.
getInt32
(
SI
->
getAlignment
(
)
)
)
;
Builder
.
CreateCall
(
VstNFunc
,
Ops
)
;
return
true
;
}
</s>

Lower interleaved store ( s ) into target specific instructions/intrinsics .


<s>
bool
LanaiInstrInfo
::
areMemAccessesTriviallyDisjoint
(
const
MachineInstr
&
MIa
,
const
MachineInstr
&
MIb
)
const
{
assert
(
MIa
.
mayLoadOrStore
(
)
&&
"MIa must be a load or store."
)
;
assert
(
MIb
.
mayLoadOrStore
(
)
&&
"MIb must be a load or store."
)
;
if
(
MIa
.
hasUnmodeledSideEffects
(
)
||
MIb
.
hasUnmodeledSideEffects
(
)
||
MIa
.
hasOrderedMemoryRef
(
)
||
MIb
.
hasOrderedMemoryRef
(
)
)
return
false
;
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
const
MachineOperand
*
BaseOpA
=
nullptr
,
*
BaseOpB
=
nullptr
;
int64_t
OffsetA
=
0
,
OffsetB
=
0
;
unsigned
int
WidthA
=
0
,
WidthB
=
0
;
if
(
getMemOperandWithOffsetWidth
(
MIa
,
BaseOpA
,
OffsetA
,
WidthA
,
TRI
)
&&
getMemOperandWithOffsetWidth
(
MIb
,
BaseOpB
,
OffsetB
,
WidthB
,
TRI
)
)
{
if
(
BaseOpA
->
isIdenticalTo
(
*
BaseOpB
)
)
{
int
LowOffset
=
std
::
min
(
OffsetA
,
OffsetB
)
;
int
HighOffset
=
std
::
max
(
OffsetA
,
OffsetB
)
;
int
LowWidth
=
(
LowOffset
==
OffsetA
)
WidthA
:
WidthB
;
if
(
LowOffset
+
LowWidth
<=
HighOffset
)
return
true
;
}
}
return
false
;
}
</s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> static rtx_insn * find_prev_insn_start ( rtx_insn * insn ) { insn = PREV_INSN ( insn ) ; gcc_assert ( GET_MODE ( insn ) != SImode ) ; if ( GET_MODE ( insn ) == QImode ) { while ( GET_MODE ( PREV_INSN ( insn ) ) == SImode ) insn = PREV_INSN ( insn ) ; } return insn ; } </s>

This function acts like PREV_INSN , but is aware of three-insn bundles and skips all subsequent parallel instructions if INSN is the start of such a group .


<s> static void m32c_print_operand_address ( FILE * stream , rtx address ) { if ( GET_CODE ( address ) == MEM ) address = XEXP ( address , 0 ) ; else gcc_assert ( GET_CODE ( address ) == REG ) ; m32c_print_operand ( stream , address , 0 ) ; } </s>

Implements PRINT_OPERAND_ADDRESS . Nothing unusual here .


<s> static void core2i7_first_cycle_multipass_backtrack ( const void * _data , signed char * ready_try , int n_ready ATTRIBUTE_UNUSED ) { const_ix86_first_cycle_multipass_data_t data = ( const_ix86_first_cycle_multipass_data_t ) _data ; unsigned int i = 0 ; sbitmap_iterator sbi ; gcc_assert ( bitmap_last_set_bit ( data -> ready_try_change ) < n_ready ) ; EXECUTE_IF_SET_IN_BITMAP ( data -> ready_try_change , 0 , i , sbi ) { ready_try [ i ] = 0 ; } } </s>


"Check for a non-legal type in this operation\n"

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool LC3TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; if ( ! CCInfo . CheckReturn ( Outs , RetCC_LC3 ) ) { return false ; } if ( CCInfo . getNextStackOffset ( ) != 0 && isVarArg ) { return false ; } return true ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


"Thumb1 does not have ldr to high register"

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


"Encoding of this operand type is not supported yet."

getMachineOpValue - Return binary encoding of operand .


<s> const NVPTXFloatMCExpr * NVPTXFloatMCExpr :: Create ( VariantKind Kind , APFloat Flt , MCContext & Ctx ) { return new ( Ctx ) NVPTXFloatMCExpr ( Kind , Flt ) ; } </s>

Construct a unary instruction , given the opcode and an operand .


<s> bool ARMTargetLowering :: isLegalAddImmediate ( int64_t Imm ) const { int64_t AbsImm = llvm :: abs64 ( Imm ) ; if ( ! Subtarget -> isThumb ( ) ) return ARM_AM :: getSOImmVal ( AbsImm ) != - 1 ; if ( Subtarget -> isThumb2 ( ) ) return ARM_AM :: getT2SOImmVal ( AbsImm ) != - 1 ; return AbsImm >= 0 && AbsImm <= 255 ; } </s>

Return true if the specified immediate is legal add immediate , that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register .


<s> static int ix86_nsaved_sseregs ( void ) { int nregs = 0 ; int regno ; if ( ! TARGET_64BIT_MS_ABI ) return 0 ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( SSE_REGNO_P ( regno ) && ix86_save_reg ( regno , true , true ) ) nregs ++ ; return nregs ; } </s>


<s> virtual void EmitInstruction ( const MCInst & Inst ) { if ( InstPrinter ) InstPrinter -> printInst ( & Inst , OS , "" ) ; else Inst . print ( OS , & MAI ) ; EmitEOL ( ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void sh_emit_compare_and_branch ( rtx * operands , machine_mode mode ) { enum rtx_code code = GET_CODE ( operands [ 0 ] ) ; enum rtx_code branch_code ; rtx op0 = operands [ 1 ] ; rtx op1 = operands [ 2 ] ; rtx insn ; bool need_ccmpeq = false ; if ( TARGET_SH2E && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { op0 = force_reg ( mode , op0 ) ; op1 = force_reg ( mode , op1 ) ; } else { if ( code != EQ || mode == DImode ) { op0 = force_reg ( mode , op0 ) ; if ( op1 != const0_rtx || code == GTU || code == GEU ) op1 = force_reg ( mode , op1 ) ; } } if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { if ( code == LT || ( code == LE && TARGET_IEEE && TARGET_SH2E ) || ( code == GE && ! ( TARGET_IEEE && TARGET_SH2E ) ) ) { std :: swap ( op0 , op1 ) ; code = swap_condition ( code ) ; } if ( code == GE ) { gcc_assert ( TARGET_IEEE && TARGET_SH2E ) ; need_ccmpeq = true ; code = GT ; } gcc_assert ( code == EQ || code == GT || code == NE || code == LE ) ; } switch ( code ) { case EQ : case GT : case GE : case GTU : case GEU : branch_code = code ; break ; case NE : case LT : case LE : case LTU : case LEU : branch_code = reverse_condition ( code ) ; break ; default : gcc_unreachable ( ) ; } insn = gen_rtx_SET ( VOIDmode , get_t_reg_rtx ( ) , gen_rtx_fmt_ee ( branch_code , SImode , op0 , op1 ) ) ; sh_emit_set_t_insn ( insn , mode ) ; if ( need_ccmpeq ) sh_emit_set_t_insn ( gen_ieee_ccmpeqsf_t ( op0 , op1 ) , mode ) ; if ( branch_code == code ) emit_jump_insn ( gen_branch_true ( operands [ 3 ] ) ) ; else emit_jump_insn ( gen_branch_false ( operands [ 3 ] ) ) ; } </s>

Called from the md file , set up the operands of a compare instruction .


<s> bool ARCompactTargetMachine :: addPreSched2 ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt :: None ) { PM . add ( createIfConverterPass ( ) ) ; } return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


"SGPR spill should have been removed in SILowerSGPRSpills"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> bool SystemZShortenInst :: runOnMachineFunction ( MachineFunction & F ) { const SystemZSubtarget & ST = F . getSubtarget < SystemZSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; LiveRegs . init ( TRI ) ; bool Changed = false ; for ( auto & MBB : F ) Changed |= processBlock ( MBB ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> static HOST_WIDE_INT rs6000_starting_frame_offset ( void ) { if ( FRAME_GROWS_DOWNWARD ) return 0 ; return RS6000_STARTING_FRAME_OFFSET ; } </s>


<s>
MCDisassembler
::
DecodeStatus
X86GenericDisassembler
::
getInstruction
(
MCInst
&
Instr
,
uint64_t
&
Size
,
ArrayRef
<
uint8_t
>
Bytes
,
uint64_t
Address
,
raw_ostream
&
CStream
)
const
{
CommentStream
=
&
CStream
;
InternalInstruction
Insn
;
memset
(
&
Insn
,
0
,
sizeof
(
InternalInstruction
)
)
;
Insn
.
bytes
=
Bytes
;
Insn
.
startLocation
=
Address
;
Insn
.
readerCursor
=
Address
;
Insn
.
mode
=
fMode
;
if
(
Bytes
.
empty
(
)
||
readPrefixes
(
&
Insn
)
||
readOpcode
(
&
Insn
)
||
getInstructionID
(
&
Insn
,
MII
.
get
(
)
)
||
Insn
.
instructionID
==
0
||
readOperands
(
&
Insn
)
)
{
Size
=
Insn
.
readerCursor
Address
;
return
Fail
;
}
Insn
.
operands
=
x86OperandSets
[
Insn
.
spec
->
operands
]
;
Insn
.
length
=
Insn
.
readerCursor
Insn
.
startLocation
;
Size
=
Insn
.
length
;
if
(
Size
>
15
)
LLVM_DEBUG
(
dbgs
(
)
<<
"Instruction exceeds 15-byte limit"
)
;
bool
Ret
=
translateInstruction
(
Instr
,
Insn
,
this
)
;
if
(
!
Ret
)
{
unsigned
Flags
=
X86
::
IP_NO_PREFIX
;
if
(
Insn
.
hasAdSize
)
Flags
|=
X86
::
IP_HAS_AD_SIZE
;
if
(
!
Insn
.
mandatoryPrefix
)
{
if
(
Insn
.
hasOpSize
)
Flags
|=
X86
::
IP_HAS_OP_SIZE
;
if
(
Insn
.
repeatPrefix
==
0xf2
)
Flags
|=
X86
::
IP_HAS_REPEAT_NE
;
else
if
(
Insn
.
repeatPrefix
==
0xf3
&&
Insn
.
opcode
!=
0x90
)
Flags
|=
X86
::
IP_HAS_REPEAT
;
if
(
Insn
.
hasLockPrefix
)
Flags
|=
X86
::
IP_HAS_LOCK
;
}
Instr
.
setFlags
(
Flags
)
;
}
return
(
!
Ret
)
Success
:
Fail
;
}
</s>

Returns the disassembly of a single instruction .


<s> void addPreSched2 ( ) override { if ( PatmosSinglePathInfo :: isEnabled ( ) ) { addPass ( createPatmosSinglePathInfoPass ( getPatmosTargetMachine ( ) ) ) ; addPass ( createPatmosSPBundlingPass ( getPatmosTargetMachine ( ) ) ) ; addPass ( createPatmosSPReducePass ( getPatmosTargetMachine ( ) ) ) ; addPass ( createSPSchedulerPass ( getPatmosTargetMachine ( ) ) ) ; } else { if ( getOptLevel ( ) != CodeGenOpt :: None && ! DisableIfConverter ) { addPass ( & IfConverterID ) ; addPass ( & UnreachableMachineBlockElimID ) ; } } addPass ( createPatmosStackCacheAnalysisInfo ( getPatmosTargetMachine ( ) ) ) ; if ( EnableStackCacheAnalysis ) { addPass ( createPatmosStackCacheAnalysis ( getPatmosTargetMachine ( ) ) ) ; } } </s>

Patmos Patmos Patmos Patmos Patmos Patmos Patmos Patmos Patmos Patmos Patmos Patmos Patmos


<s> int expand_block_clear ( rtx operands [ ] ) { rtx orig_dest = operands [ 0 ] ; rtx bytes_rtx = operands [ 1 ] ; rtx align_rtx = operands [ 3 ] ; bool constp = ( GET_CODE ( bytes_rtx ) == CONST_INT ) ; HOST_WIDE_INT align ; HOST_WIDE_INT bytes ; int offset ; int clear_bytes ; int clear_step ; if ( ! constp ) return 0 ; gcc_assert ( GET_CODE ( align_rtx ) == CONST_INT ) ; align = INTVAL ( align_rtx ) * BITS_PER_UNIT ; bytes = INTVAL ( bytes_rtx ) ; if ( bytes <= 0 ) return 1 ; if ( TARGET_ALTIVEC && align >= 128 ) clear_step = 16 ; else if ( TARGET_POWERPC64 && ( align >= 64 || ! STRICT_ALIGNMENT ) ) clear_step = 8 ; else if ( TARGET_SPE && align >= 64 ) clear_step = 8 ; else clear_step = 4 ; if ( optimize_size && bytes > 3 * clear_step ) return 0 ; if ( ! optimize_size && bytes > 8 * clear_step ) return 0 ; for ( offset = 0 ; bytes > 0 ; offset += clear_bytes , bytes -= clear_bytes ) { machine_mode mode = BLKmode ; rtx dest ; if ( bytes >= 16 && TARGET_ALTIVEC && align >= 128 ) { clear_bytes = 16 ; mode = V4SImode ; } else if ( bytes >= 8 && TARGET_SPE && align >= 64 ) { clear_bytes = 8 ; mode = V2SImode ; } else if ( bytes >= 8 && TARGET_POWERPC64 && ( align >= 64 || ! STRICT_ALIGNMENT ) ) { clear_bytes = 8 ; mode = DImode ; if ( offset == 0 && align < 64 ) { rtx addr ; addr = XEXP ( orig_dest , 0 ) ; if ( ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) && GET_CODE ( XEXP ( addr , 1 ) ) == CONST_INT && ( INTVAL ( XEXP ( addr , 1 ) ) & 3 ) != 0 ) { addr = copy_addr_to_reg ( addr ) ; orig_dest = replace_equiv_address ( orig_dest , addr ) ; } } } else if ( bytes >= 4 && ( align >= 32 || ! STRICT_ALIGNMENT ) ) { clear_bytes = 4 ; mode = SImode ; } else if ( bytes >= 2 && ( align >= 16 || ! STRICT_ALIGNMENT ) ) { clear_bytes = 2 ; mode = HImode ; } else { clear_bytes = 1 ; mode = QImode ; } dest = adjust_address ( orig_dest , mode , offset ) ; emit_move_insn ( dest , CONST0_RTX ( mode ) ) ; } return 1 ; } </s>

Expand a block clear operation , and return 1 if successful . Return 0 if we should let the compiler generate normal code . operands [ 0 ] is the destination operands [ 1 ] is the length operands [ 3 ] is the alignment


<s> static int mips_symbol_insns_1 ( enum mips_symbol_type type , machine_mode mode ) { if ( mips_use_pcrel_pool_p [ ( int ) type ] ) { if ( mode == MAX_MACHINE_MODE ) type = SYMBOL_PC_RELATIVE ; else return 0 ; } switch ( type ) { case SYMBOL_ABSOLUTE : return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2 ; case SYMBOL_GP_RELATIVE : return 1 ; case SYMBOL_PC_RELATIVE : if ( mode == MAX_MACHINE_MODE || GET_MODE_SIZE ( mode ) == 4 || GET_MODE_SIZE ( mode ) == 8 ) return 1 ; return 0 ; case SYMBOL_GOT_DISP : if ( mode != MAX_MACHINE_MODE ) return 0 ; case SYMBOL_GOT_PAGE_OFST : return 3 ; case SYMBOL_GOTOFF_PAGE : case SYMBOL_GOTOFF_DISP : case SYMBOL_GOTOFF_CALL : case SYMBOL_GOTOFF_LOADGP : case SYMBOL_64_HIGH : case SYMBOL_64_MID : case SYMBOL_64_LOW : case SYMBOL_TLSGD : case SYMBOL_TLSLDM : case SYMBOL_DTPREL : case SYMBOL_GOTTPREL : case SYMBOL_TPREL : case SYMBOL_HALF : return ! mips_split_p [ type ] ? 1 : TARGET_MIPS16 ? 3 : 2 ; case SYMBOL_TLS : return 0 ; } gcc_unreachable ( ) ; } </s>

Like mips_symbol_insns , but treat extended MIPS16 instructions as a single instruction . We rely on the fact that , in the worst case , all instructions involved in a MIPS16 address calculation are usually extended ones .


<s> Align getStackAlignment ( ) const { return stackAlignment ; } </s>

Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget .


<s> void output_global_address ( FILE * file , rtx x , int round_constant ) { if ( GET_CODE ( x ) == HIGH ) x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == SYMBOL_REF && read_only_operand ( x , VOIDmode ) ) output_addr_const ( file , x ) ; else if ( GET_CODE ( x ) == SYMBOL_REF && ! flag_pic ) { output_addr_const ( file , x ) ; fputs ( "-$global$" , file ) ; } else if ( GET_CODE ( x ) == CONST ) { const char * sep = "" ; int offset = 0 ; rtx base = NULL_RTX ; switch ( GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) ) { case SYMBOL_REF : base = XEXP ( XEXP ( x , 0 ) , 0 ) ; output_addr_const ( file , base ) ; break ; case CONST_INT : offset = INTVAL ( XEXP ( XEXP ( x , 0 ) , 0 ) ) ; break ; default : gcc_unreachable ( ) ; } switch ( GET_CODE ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ) { case SYMBOL_REF : base = XEXP ( XEXP ( x , 0 ) , 1 ) ; output_addr_const ( file , base ) ; break ; case CONST_INT : offset = INTVAL ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ; break ; default : gcc_unreachable ( ) ; } if ( round_constant ) offset = ( ( offset + 0x1000 ) & ~ 0x1fff ) ; switch ( GET_CODE ( XEXP ( x , 0 ) ) ) { case PLUS : if ( offset < 0 ) { offset = - offset ; sep = "-" ; } else sep = "+" ; break ; case MINUS : gcc_assert ( GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == SYMBOL_REF ) ; sep = "-" ; break ; default : gcc_unreachable ( ) ; } if ( ! read_only_operand ( base , VOIDmode ) && ! flag_pic ) fputs ( "-$global$" , file ) ; if ( offset ) fprintf ( file , "%s%d" , sep , offset ) ; } else output_addr_const ( file , x ) ; } </s>

output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF .


<s> static int mips_rewrite_small_data_1 ( rtx * loc , void * data ATTRIBUTE_UNUSED ) { if ( mips_rewrite_small_data_p ( * loc ) ) * loc = gen_rtx_LO_SUM ( Pmode , pic_offset_table_rtx , * loc ) ; if ( GET_CODE ( * loc ) == LO_SUM ) return - 1 ; return 0 ; } </s>

A for_each_rtx callback , used by mips_rewrite_small_data .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Lower AMX intrinsics"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> const char * rvexTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case rvexISD :: JmpLink : return "rvexISD::JmpLink" ; case rvexISD :: Hi : return "rvexISD::Hi" ; case rvexISD :: Lo : return "rvexISD::Lo" ; case rvexISD :: GPRel : return "rvexISD::GPRel" ; case rvexISD :: Ret : return "rvexISD::Ret" ; case rvexISD :: DivRem : return "rvexISD::DivRem" ; case rvexISD :: DivRemU : return "rvexISD::DivRemU" ; case rvexISD :: Wrapper : return "rvexISD::Wrapper" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific

rvex rvex rvexISD::JmpLink "rvexISD::JmpLink" rvexISD::Hi "rvexISD::Hi" rvexISD::Lo "rvexISD::Lo" rvexISD::GPRel "rvexISD::GPRel" rvexISD::Ret "rvexISD::Ret" rvexISD::DivRem "rvexISD::DivRem" rvexISD::DivRemU "rvexISD::DivRemU" rvexISD::Wrapper "rvexISD::Wrapper"


<s>
bool
MSP430InstrInfo
::
reverseBranchCondition
(
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
assert
(
Cond
.
size
(
)
==
1
&&
"Invalid Xbranch condition!"
)
;
MSP430CC
::
CondCodes
CC
=
static_cast
<
MSP430CC
::
CondCodes
>
(
Cond
[
0
]
.
getImm
(
)
)
;
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Invalid branch condition!"
)
;
case
MSP430CC
::
COND_E
:
CC
=
MSP430CC
::
COND_NE
;
break
;
case
MSP430CC
::
COND_NE
:
CC
=
MSP430CC
::
COND_E
;
break
;
case
MSP430CC
::
COND_L
:
CC
=
MSP430CC
::
COND_GE
;
break
;
case
MSP430CC
::
COND_GE
:
CC
=
MSP430CC
::
COND_L
;
break
;
case
MSP430CC
::
COND_HS
:
CC
=
MSP430CC
::
COND_LO
;
break
;
case
MSP430CC
::
COND_LO
:
CC
=
MSP430CC
::
COND_HS
;
break
;
}
Cond
[
0
]
.
setImm
(
CC
)
;
return
false
;
}
</s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s>
int
AArch64TTIImpl
::
getArithmeticReductionCost
(
unsigned
Opcode
,
VectorType
*
ValTy
,
bool
IsPairwiseForm
,
TTI
::
TargetCostKind
CostKind
)
{
if
(
isa
<
ScalableVectorType
>
(
ValTy
)
)
return
getArithmeticReductionCostSVE
(
Opcode
,
ValTy
,
IsPairwiseForm
,
CostKind
)
;
if
(
IsPairwiseForm
)
return
BaseT
::
getArithmeticReductionCost
(
Opcode
,
ValTy
,
IsPairwiseForm
,
CostKind
)
;
std
::
pair
<
int
,
MVT
>
LT
=
TLI
->
getTypeLegalizationCost
(
DL
,
ValTy
)
;
MVT
MTy
=
LT
.
second
;
int
ISD
=
TLI
->
InstructionOpcodeToISD
(
Opcode
)
;
assert
(
ISD
&&
"Invalid opcode"
)
;
static
const
CostTblEntry
CostTblNoPairwise
[
]
{
{
ISD
::
ADD
,
MVT
::
v8i8
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v16i8
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v4i16
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v8i16
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v4i32
,
1
}
,
}
;
if
(
const
auto
*
Entry
=
CostTableLookup
(
CostTblNoPairwise
,
ISD
,
MTy
)
)
return
LT
.
first
*
Entry
->
Cost
;
return
BaseT
::
getArithmeticReductionCost
(
Opcode
,
ValTy
,
IsPairwiseForm
,
CostKind
)
;
}
</s>

Calculate the cost of vector reduction intrinsics .


<s> static bool mips16_cfun_returns_in_fpr_p ( void ) { tree return_type = DECL_RESULT ( current_function_decl ) ; return ( TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI && ! aggregate_value_p ( return_type , current_function_decl ) && mips_return_mode_in_fpr_p ( DECL_MODE ( return_type ) ) ) ; } </s>

Return true if the current function returns its value in a floating-point register in MIPS16 mode .


<s> const_iterator end ( ) const { return Map . end ( ) ; } </s>

Get a const_iterator to the end of the symbol table .


<s> rtx ix86_memtag_add_tag ( rtx base , poly_int64 offset , unsigned char tag_offset ) { rtx base_tag = gen_reg_rtx ( QImode ) ; rtx base_addr = gen_reg_rtx ( Pmode ) ; rtx tagged_addr = gen_reg_rtx ( Pmode ) ; rtx new_tag = gen_reg_rtx ( QImode ) ; unsigned HOST_WIDE_INT and_imm = ( HOST_WIDE_INT_1U << IX86_HWASAN_SHIFT ) - 1 ; emit_move_insn ( base_tag , ix86_memtag_extract_tag ( base , NULL_RTX ) ) ; emit_move_insn ( base_addr , ix86_memtag_untagged_pointer ( base , NULL_RTX ) ) ; emit_insn ( gen_add2_insn ( base_tag , gen_int_mode ( tag_offset , QImode ) ) ) ; emit_move_insn ( new_tag , base_tag ) ; emit_insn ( gen_andqi3 ( new_tag , new_tag , gen_int_mode ( and_imm , QImode ) ) ) ; emit_move_insn ( tagged_addr , ix86_memtag_set_tag ( base_addr , new_tag , NULL_RTX ) ) ; return plus_constant ( Pmode , tagged_addr , offset ) ; } </s>


<s> static rtx function_arg_32 ( const CUMULATIVE_ARGS * cum , machine_mode mode , machine_mode orig_mode , const_tree type , HOST_WIDE_INT bytes , HOST_WIDE_INT words ) { if ( mode == VOIDmode ) return constm1_rtx ; switch ( mode ) { default : break ; case BLKmode : if ( bytes < 0 ) break ; case DImode : case SImode : case HImode : case QImode : if ( words <= cum -> nregs ) { int regno = cum -> regno ; if ( cum -> fastcall ) { if ( mode == BLKmode || mode == DImode || ( type && AGGREGATE_TYPE_P ( type ) ) ) break ; if ( regno == AX_REG ) regno = CX_REG ; } return gen_rtx_REG ( mode , regno ) ; } break ; case DFmode : if ( cum -> float_in_sse < 2 ) break ; case SFmode : if ( cum -> float_in_sse < 1 ) break ; case TImode : case V16QImode : case V8HImode : case V4SImode : case V2DImode : case V4SFmode : case V2DFmode : if ( ! type || ! AGGREGATE_TYPE_P ( type ) ) { if ( cum -> sse_nregs ) return gen_reg_or_parallel ( mode , orig_mode , cum -> sse_regno + FIRST_SSE_REG ) ; } break ; case OImode : case XImode : gcc_unreachable ( ) ; case V64QImode : case V32HImode : case V16SImode : case V8DImode : case V16SFmode : case V8DFmode : case V8SFmode : case V8SImode : case V32QImode : case V16HImode : case V4DFmode : case V4DImode : if ( ! type || ! AGGREGATE_TYPE_P ( type ) ) { if ( cum -> sse_nregs ) return gen_reg_or_parallel ( mode , orig_mode , cum -> sse_regno + FIRST_SSE_REG ) ; } break ; case V8QImode : case V4HImode : case V2SImode : case V2SFmode : case V1TImode : case V1DImode : if ( ! type || ! AGGREGATE_TYPE_P ( type ) ) { if ( cum -> mmx_nregs ) return gen_reg_or_parallel ( mode , orig_mode , cum -> mmx_regno + FIRST_MMX_REG ) ; } break ; } return NULL_RTX ; } </s>

Define where to put the arguments to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) .


<s> static bool msp430_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( ( mode1 == PSImode || mode2 == SImode ) || ( mode1 == SImode || mode2 == PSImode ) ) return false ; return ( ( GET_MODE_CLASS ( mode1 ) == MODE_FLOAT || GET_MODE_CLASS ( mode1 ) == MODE_COMPLEX_FLOAT ) == ( GET_MODE_CLASS ( mode2 ) == MODE_FLOAT || GET_MODE_CLASS ( mode2 ) == MODE_COMPLEX_FLOAT ) ) ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"BPF Abstract Member Access"
;
}
</s>


<s>
unsigned
SparcRegisterInfo
::
getRARegister
(
)
const
{
assert
(
0
&&
"What is the return address register"
)
;
return
0
;
}
</s>

This method should return the register where the return address can be found .


<s> bool X86InstrInfo :: classifyLEAReg ( MachineInstr & MI , const MachineOperand & Src , unsigned Opc , bool AllowSP , unsigned & NewSrc , bool & isKill , bool & isUndef , MachineOperand & ImplicitOp , LiveVariables * LV ) const { MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const TargetRegisterClass * RC ; if ( AllowSP ) { RC = Opc != X86 :: LEA32r ? & X86 :: GR64RegClass : & X86 :: GR32RegClass ; } else { RC = Opc != X86 :: LEA32r ? & X86 :: GR64_NOSPRegClass : & X86 :: GR32_NOSPRegClass ; } unsigned SrcReg = Src . getReg ( ) ; if ( Opc != X86 :: LEA64_32r ) { NewSrc = SrcReg ; isKill = Src . isKill ( ) ; isUndef = Src . isUndef ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( NewSrc ) && ! MF . getRegInfo ( ) . constrainRegClass ( NewSrc , RC ) ) return false ; return true ; } if ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) ) { ImplicitOp = Src ; ImplicitOp . setImplicit ( ) ; NewSrc = getX86SubSuperRegister ( Src . getReg ( ) , 64 ) ; MachineBasicBlock :: LivenessQueryResult LQR = MI . getParent ( ) -> computeRegisterLiveness ( & getRegisterInfo ( ) , NewSrc , MI ) ; switch ( LQR ) { case MachineBasicBlock :: LQR_Unknown : return false ; case MachineBasicBlock :: LQR_Live : isKill = MI . killsRegister ( SrcReg ) ; isUndef = false ; break ; default : isKill = false ; isUndef = true ; break ; } } else { NewSrc = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MachineInstr * Copy = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( NewSrc , RegState :: Define | RegState :: Undef , X86 :: sub_32bit ) . addOperand ( Src ) ; isKill = true ; isUndef = false ; if ( LV ) LV -> replaceKillInstruction ( SrcReg , MI , * Copy ) ; } return true ; } </s>

Given an operand within a MachineInstr , insert preceding code to put it into the right format for a particular kind of LEA instruction .


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ReserveX18 ( TT . isOSDarwin ( ) ) , IsLittle ( LittleEndian ) , CPUString ( CPU ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS ) ) , TSInfo ( ) , TLInfo ( TM , * this ) , GISel ( ) { } </s>

This constructor initializes the data members to match that of the specified triple .


<s> bool Cpu0TargetObjectFile :: IsGlobalInSmallSection ( const GlobalObject * GO , const TargetMachine & TM , SectionKind Kind ) const { return ( IsGlobalInSmallSectionImpl ( GO , TM ) && ( Kind . isData ( ) || Kind . isBSS ( ) || Kind . isCommon ( ) || Kind . isReadOnly ( ) ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> bool PPCSubtarget :: enableSubRegLiveness ( ) const { return UseSubRegLiveness ; } </s>

Enable tracking of subregister liveness in register allocator .


<s> bool RISCVTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { return Imm . isPosZero ( ) ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s>
ChangeStatus
updateImpl
(
Attributor
&
A
)
override
{
Function
*
F
=
getAssociatedFunction
(
)
;
auto
OrigAssumed
=
getAssumed
(
)
;
const
AACallEdges
&
AAEdges
=
A
.
getAAFor
<
AACallEdges
>
(
*
this
,
this
->
getIRPosition
(
)
,
DepClassTy
::
REQUIRED
)
;
if
(
AAEdges
.
hasNonAsmUnknownCallee
(
)
)
return
indicatePessimisticFixpoint
(
)
;
bool
IsNonEntryFunc
=
!
AMDGPU
::
isEntryFunctionCC
(
F
->
getCallingConv
(
)
)
;
bool
NeedsImplicit
=
false
;
auto
&
InfoCache
=
static_cast
<
AMDGPUInformationCache
&
>
(
A
.
getInfoCache
(
)
)
;
bool
HasApertureRegs
=
InfoCache
.
hasApertureRegs
(
*
F
)
;
bool
SupportsGetDoorbellID
=
InfoCache
.
supportsGetDoorbellID
(
*
F
)
;
for
(
Function
*
Callee
:
AAEdges
.
getOptimisticEdges
(
)
)
{
Intrinsic
::
ID
IID
=
Callee
->
getIntrinsicID
(
)
;
if
(
IID
==
Intrinsic
::
not_intrinsic
)
{
const
AAAMDAttributes
&
AAAMD
=
A
.
getAAFor
<
AAAMDAttributes
>
(
*
this
,
IRPosition
::
function
(
*
Callee
)
,
DepClassTy
::
REQUIRED
)
;
*
this
&=
AAAMD
;
continue
;
}
bool
NonKernelOnly
=
false
;
ImplicitArgumentMask
AttrMask
=
intrinsicToAttrMask
(
IID
,
NonKernelOnly
,
NeedsImplicit
,
HasApertureRegs
,
SupportsGetDoorbellID
)
;
if
(
AttrMask
!=
NOT_IMPLICIT_INPUT
)
{
if
(
(
IsNonEntryFunc
||
!
NonKernelOnly
)
)
removeAssumedBits
(
AttrMask
)
;
}
}
if
(
NeedsImplicit
)
removeAssumedBits
(
IMPLICIT_ARG_PTR
)
;
if
(
isAssumed
(
QUEUE_PTR
)
&&
checkForQueuePtr
(
A
)
)
{
if
(
AMDGPU
::
getAmdhsaCodeObjectVersion
(
)
==
5
)
removeAssumedBits
(
IMPLICIT_ARG_PTR
)
;
else
removeAssumedBits
(
QUEUE_PTR
)
;
}
if
(
funcRetrievesHostcallPtr
(
A
)
)
{
assert
(
!
isAssumed
(
IMPLICIT_ARG_PTR
)
&&
"hostcall needs implicitarg_ptr"
)
;
removeAssumedBits
(
HOSTCALL_PTR
)
;
}
if
(
funcRetrievesHeapPtr
(
A
)
)
{
assert
(
!
isAssumed
(
IMPLICIT_ARG_PTR
)
&&
"heap_ptr needs implicitarg_ptr"
)
;
removeAssumedBits
(
HEAP_PTR
)
;
}
if
(
isAssumed
(
QUEUE_PTR
)
&&
funcRetrievesQueuePtr
(
A
)
)
{
assert
(
!
isAssumed
(
IMPLICIT_ARG_PTR
)
&&
"queue_ptr needs implicitarg_ptr"
)
;
removeAssumedBits
(
QUEUE_PTR
)
;
}
return
getAssumed
(
)
!=
OrigAssumed
ChangeStatus
::
CHANGED
:
ChangeStatus
::
UNCHANGED
;
}
</s>

The actual update/transfer function which has to be implemented by the derived classes .

AMDGPU
AMDGPU::isEntryFunctionCC
AMDGPU
Intrinsic::ID
Intrinsic::not_intrinsic
AMDGPU::getAmdhsaCodeObjectVersion
5
"hostcall needs implicitarg_ptr"
"heap_ptr needs implicitarg_ptr"
"queue_ptr needs implicitarg_ptr"


<s> rtx function_arg ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int incoming_p ) { int regbase , words , max ; int * arg_words ; int regno ; arg_words = & cum -> arg_words ; regbase = ( incoming_p ? GP_ARG_FIRST : GP_OUTGOING_ARG_FIRST ) ; max = MAX_ARGS_IN_REGISTERS ; words = ( ( ( mode != BLKmode ) ? ( int ) GET_MODE_SIZE ( mode ) : int_size_in_bytes ( type ) ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; if ( type && ( TYPE_ALIGN ( type ) > BITS_PER_WORD ) ) { int align = TYPE_ALIGN ( type ) / BITS_PER_WORD ; * arg_words = ( * arg_words + align - 1 ) & - align ; } if ( * arg_words + words > max ) return ( rtx ) 0 ; regno = regbase + * arg_words ; if ( cum -> incoming && regno <= A7_REG && regno + words > A7_REG ) cfun -> machine -> need_a7_copy = true ; return gen_rtx_REG ( mode , regno ) ; } </s>

Return an RTL expression containing the register for the given mode , or 0 if the argument is to be passed on the stack . INCOMING_P is nonzero if this is an incoming argument to the current function .


<s>
unsigned
X86VectorTargetTransformInfo
::
getArithmeticInstrCost
(
unsigned
Opcode
,
Type
*
Ty
)
const
{
std
::
pair
<
unsigned
,
MVT
>
LT
=
getTypeLegalizationCost
(
Ty
)
;
int
ISD
=
InstructionOpcodeToISD
(
Opcode
)
;
assert
(
ISD
&&
"Invalid opcode"
)
;
const
X86Subtarget
&
ST
=
TLI
->
getTargetMachine
(
)
.
getSubtarget
<
X86Subtarget
>
(
)
;
static
const
X86CostTblEntry
AVX1CostTable
[
]
=
{
{
ISD
::
MUL
,
MVT
::
v8i32
,
4
}
,
{
ISD
::
SUB
,
MVT
::
v8i32
,
4
}
,
{
ISD
::
ADD
,
MVT
::
v8i32
,
4
}
,
{
ISD
::
MUL
,
MVT
::
v4i64
,
4
}
,
{
ISD
::
SUB
,
MVT
::
v4i64
,
4
}
,
{
ISD
::
ADD
,
MVT
::
v4i64
,
4
}
,
}
;
if
(
ST
.
hasAVX
(
)
)
{
int
Idx
=
FindInTable
(
AVX1CostTable
,
array_lengthof
(
AVX1CostTable
)
,
ISD
,
LT
.
second
)
;
if
(
Idx
!=
1
)
return
LT
.
first
*
AVX1CostTable
[
Idx
]
.
Cost
;
}
return
VectorTargetTransformImpl
::
getArithmeticInstrCost
(
Opcode
,
Ty
)
;
}
</s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> static void c6x_set_sched_flags ( spec_info_t spec_info ) { unsigned int * flags = & ( current_sched_info -> flags ) ; if ( * flags & SCHED_EBB ) { * flags |= DO_BACKTRACKING | DO_PREDICATION ; } if ( in_hwloop ) * flags |= DONT_BREAK_DEPENDENCIES ; spec_info -> mask = 0 ; } </s>

Provide information about speculation capabilities , and set the DO_BACKTRACKING flag .


<s>
bool
HexagonInstrInfo
::
PredicateInstruction
(
MachineInstr
*
MI
,
ArrayRef
<
MachineOperand
>
Cond
)
const
{
if
(
Cond
.
empty
(
)
||
isEndLoopN
(
Cond
[
0
]
.
getImm
(
)
)
)
{
DEBUG
(
dbgs
(
)
<<
"\nCannot predicate:"
;
MI
->
dump
(
)
;
)
;
return
false
;
}
int
Opc
=
MI
->
getOpcode
(
)
;
assert
(
isPredicable
(
MI
)
&&
"Expected predicable instruction"
)
;
bool
invertJump
=
predOpcodeHasNot
(
Cond
)
;
MachineBasicBlock
&
B
=
*
MI
->
getParent
(
)
;
DebugLoc
DL
=
MI
->
getDebugLoc
(
)
;
unsigned
PredOpc
=
getCondOpcode
(
Opc
,
invertJump
)
;
MachineInstrBuilder
T
=
BuildMI
(
B
,
MI
,
DL
,
get
(
PredOpc
)
)
;
unsigned
NOp
=
0
,
NumOps
=
MI
->
getNumOperands
(
)
;
while
(
NOp
<
NumOps
)
{
MachineOperand
&
Op
=
MI
->
getOperand
(
NOp
)
;
if
(
!
Op
.
isReg
(
)
||
!
Op
.
isDef
(
)
||
Op
.
isImplicit
(
)
)
break
;
T
.
addOperand
(
Op
)
;
NOp
++
;
}
unsigned
PredReg
,
PredRegPos
,
PredRegFlags
;
bool
GotPredReg
=
getPredReg
(
Cond
,
PredReg
,
PredRegPos
,
PredRegFlags
)
;
(
void
)
GotPredReg
;
assert
(
GotPredReg
)
;
T
.
addReg
(
PredReg
,
PredRegFlags
)
;
while
(
NOp
<
NumOps
)
T
.
addOperand
(
MI
->
getOperand
(
NOp
++
)
)
;
MI
->
setDesc
(
get
(
PredOpc
)
)
;
while
(
unsigned
n
=
MI
->
getNumOperands
(
)
)
MI
->
RemoveOperand
(
n
1
)
;
for
(
unsigned
i
=
0
,
n
=
T
->
getNumOperands
(
)
;
i
<
n
;
++
i
)
MI
->
addOperand
(
T
->
getOperand
(
i
)
)
;
MachineBasicBlock
::
instr_iterator
TI
=
T
->
getIterator
(
)
;
B
.
erase
(
TI
)
;
MachineRegisterInfo
&
MRI
=
B
.
getParent
(
)
->
getRegInfo
(
)
;
MRI
.
clearKillFlags
(
PredReg
)
;
return
true
;
}
</s>

Convert the instruction into a predicated instruction .


<s> bool isLittleEndian ( ) const { return isLittle ; } </s>

Tests whether the target triple is little endian .


"Tiny codesize model not supported on X86"

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s> bool LanaiInstrInfo :: getMemOperandWithOffset ( const MachineInstr & LdSt , const MachineOperand * & BaseOp , int64_t & Offset , const TargetRegisterInfo * TRI ) const { switch ( LdSt . getOpcode ( ) ) { default : return false ; case Lanai :: LDW_RI : case Lanai :: LDW_RR : case Lanai :: SW_RR : case Lanai :: SW_RI : case Lanai :: LDHs_RI : case Lanai :: LDHz_RI : case Lanai :: STH_RI : case Lanai :: LDBs_RI : case Lanai :: LDBz_RI : unsigned Width ; return getMemOperandWithOffsetWidth ( LdSt , BaseOp , Offset , Width , TRI ) ; } } </s>

Get the base operand and byte offset of an instruction that reads/writes memory .


<s>
void
MipsInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineMemOperand
*
MMO
=
GetMemOperand
(
MBB
,
FI
,
MachineMemOperand
::
MOLoad
)
;
unsigned
Opc
=
0
;
if
(
RC
==
Mips
::
CPURegsRegisterClass
)
Opc
=
IsN64
Mips
::
LW_P8
:
Mips
::
LW
;
else
if
(
RC
==
Mips
::
CPU64RegsRegisterClass
)
Opc
=
IsN64
Mips
::
LD_P8
:
Mips
::
LD
;
else
if
(
RC
==
Mips
::
FGR32RegisterClass
)
Opc
=
IsN64
Mips
::
LWC1_P8
:
Mips
::
LWC1
;
else
if
(
RC
==
Mips
::
AFGR64RegisterClass
)
Opc
=
Mips
::
LDC1
;
else
if
(
RC
==
Mips
::
FGR64RegisterClass
)
Opc
=
IsN64
Mips
::
LDC164_P8
:
Mips
::
LDC164
;
assert
(
Opc
&&
"Register class not handled!"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> outliner :: OutlinedFunction X86InstrInfo :: getOutliningCandidateInfo ( std :: vector < outliner :: Candidate > & RepeatedSequenceLocs ) const { unsigned SequenceSize = std :: accumulate ( RepeatedSequenceLocs [ 0 ] . front ( ) , std :: next ( RepeatedSequenceLocs [ 0 ] . back ( ) ) , 0 , [ ] ( unsigned Sum , const MachineInstr & MI ) { if ( MI . isDebugInstr ( ) || MI . isKill ( ) ) return Sum ; return Sum + 1 ; } ) ; if ( RepeatedSequenceLocs [ 0 ] . back ( ) -> isTerminator ( ) ) { for ( outliner :: Candidate & C : RepeatedSequenceLocs ) C . setCallInfo ( MachineOutlinerTailCall , 1 ) ; return outliner :: OutlinedFunction ( RepeatedSequenceLocs , SequenceSize , 0 , MachineOutlinerTailCall ) ; } for ( outliner :: Candidate & C : RepeatedSequenceLocs ) C . setCallInfo ( MachineOutlinerDefault , 1 ) ; return outliner :: OutlinedFunction ( RepeatedSequenceLocs , SequenceSize , 1 , MachineOutlinerDefault ) ; } </s>

Returns a outliner : :OutlinedFunction struct containing target-specific information for a set of outlining candidates .


<s> TargetIRAnalysis XCoreTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( Function & F ) { return TargetTransformInfo ( XCoreTTIImpl ( this , F ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


"%<-mcall-ms2sysv-xlogues%> is not compatible with %s"

Emits a warning for unsupported msabi to sysv pro/epilogues .


<s> static rtx mips_expand_builtin_movtf ( enum mips_builtin_type type , enum insn_code icode , enum mips_fp_condition cond , rtx target , tree exp ) { struct expand_operand ops [ 4 ] ; rtx cmp_result ; cmp_result = mips_expand_builtin_compare_1 ( icode , cond , exp , 2 ) ; create_output_operand ( & ops [ 0 ] , target , TYPE_MODE ( TREE_TYPE ( exp ) ) ) ; if ( type == MIPS_BUILTIN_MOVT ) { mips_prepare_builtin_arg ( & ops [ 2 ] , exp , 2 ) ; mips_prepare_builtin_arg ( & ops [ 1 ] , exp , 3 ) ; } else { mips_prepare_builtin_arg ( & ops [ 1 ] , exp , 2 ) ; mips_prepare_builtin_arg ( & ops [ 2 ] , exp , 3 ) ; } create_fixed_operand ( & ops [ 3 ] , cmp_result ) ; return mips_expand_builtin_insn ( CODE_FOR_mips_cond_move_tf_ps , 4 , ops , true ) ; } </s>

Expand a __builtin_mips_movt_ * _ps ( ) or __builtin_mips_movf_ * _ps ( ) function ( TYPE says which ) . ARGLIST is the list of arguments to the function , ICODE is the instruction that should be used to compare the first two arguments , and COND is the condition it should test . TARGET , if nonnull , suggests a good place to put the result .


<s> bool RISCVInstrInfo :: isAsCheapAsAMove ( const MachineInstr & MI ) const { const unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : break ; case RISCV :: FSGNJ_D : case RISCV :: FSGNJ_S : return MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 2 ) . isReg ( ) && MI . getOperand ( 1 ) . getReg ( ) == MI . getOperand ( 2 ) . getReg ( ) ; case RISCV :: ADDI : case RISCV :: ORI : case RISCV :: XORI : return ( MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 1 ) . getReg ( ) == RISCV :: X0 ) || ( MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) ; } return MI . isAsCheapAsAMove ( ) ; } </s>

Return true if the instruction is as cheap as a move instruction .


<s> unsigned getNumRegisters ( LLVMContext & Context , EVT VT , Optional < MVT > RegisterVT ) const override { if ( VT == MVT :: i128 && RegisterVT . hasValue ( ) && RegisterVT . getValue ( ) == MVT :: Untyped ) return 1 ; return TargetLowering :: getNumRegisters ( Context , VT ) ; } </s>

Return the number of registers that this ValueType will eventually require .


<s> void emitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) override { if ( IsThumb ) EmitThumbMappingSymbol ( ) ; else EmitARMMappingSymbol ( ) ; MCELFStreamer :: emitInstruction ( Inst , STI ) ; } </s>

Targets should implement this to emit instructions .


runOnMachineFunction - Emit the function body .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { STI = & static_cast < const M68kSubtarget & > ( MF . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; MFI = MF . getInfo < M68kMachineFunctionInfo > ( ) ; FL = STI -> getFrameLowering ( ) ; bool Modified = false ; MOVEMState State ; unsigned Mask = 0 ; unsigned Reg = 0 ; int Offset = 0 ; for ( auto & MBB : MF ) { auto MI = MBB . begin ( ) , E = MBB . end ( ) ; while ( MI != E ) { auto NMI = std :: next ( MI ) ; switch ( MI -> getOpcode ( ) ) { default : if ( State . hasBase ( ) ) { State . setEnd ( MI ) ; Finish ( MBB , State ) ; Modified = true ; } break ; case M68k :: MOVM32jm : Mask = MI -> getOperand ( 1 ) . getImm ( ) ; Reg = MI -> getOperand ( 0 ) . getReg ( ) ; Offset = 0 ; Modified |= ProcessMI ( MBB , MI , State , Mask , Offset , Reg , true ) ; break ; case M68k :: MOVM32pm : Mask = MI -> getOperand ( 2 ) . getImm ( ) ; Reg = MI -> getOperand ( 1 ) . getReg ( ) ; Offset = MI -> getOperand ( 0 ) . getImm ( ) ; Modified |= ProcessMI ( MBB , MI , State , Mask , Offset , Reg , true ) ; break ; case M68k :: MOVM32mj : Mask = MI -> getOperand ( 0 ) . getImm ( ) ; Reg = MI -> getOperand ( 1 ) . getReg ( ) ; Offset = 0 ; Modified |= ProcessMI ( MBB , MI , State , Mask , Offset , Reg , false ) ; break ; case M68k :: MOVM32mp : Mask = MI -> getOperand ( 0 ) . getImm ( ) ; Reg = MI -> getOperand ( 2 ) . getReg ( ) ; Offset = MI -> getOperand ( 1 ) . getImm ( ) ; Modified |= ProcessMI ( MBB , MI , State , Mask , Offset , Reg , false ) ; break ; } MI = NMI ; } if ( State . hasBase ( ) ) { State . setEnd ( MI ) ; Finish ( MBB , State ) ; } } return Modified ; } </s>


"WebAssembly doesn't support non-C calling conventions"

"WebAssembly hasn't implemented inalloca arguments"

"WebAssembly hasn't implemented nest arguments"

"WebAssembly hasn't implemented cons regs arguments"

"WebAssembly hasn't implemented cons regs last arguments"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> bool ProtectReturnSupportPass :: runOnMachineFunction ( MachineFunction & Func ) { if ( ! Func . protectReturnPtr ( ) ) return false ; bool modified = false ; if ( ! Func . getName ( ) . equals ( "main" ) ) { const TargetInstrInfo & TII = * Func . getTarget ( ) . getInstrInfo ( ) ; const X86Subtarget & STI = Func . getTarget ( ) . getSubtarget < X86Subtarget > ( ) ; unsigned Reg = STI . is64Bit ( ) ? X86 :: RBX : X86 :: EBX ; unsigned PushOpc = STI . is64Bit ( ) ? X86 :: PUSH64r : X86 :: PUSH32r ; MachineBasicBlock * MBB = Func . begin ( ) ; MachineBasicBlock :: iterator MI = MBB -> begin ( ) ; const DebugLoc & DL = MI -> getDebugLoc ( ) ; BuildMI ( * MBB , MI , DL , TII . get ( PushOpc ) ) . addReg ( Reg , RegState :: Kill ) ; modified = true ; for ( auto MBBI = Func . begin ( ) , MBBE = Func . end ( ) ; MBBI != MBBE ; MBBI ++ ) { if ( ! isReturnBlock ( MBBI ) ) continue ; modified |= handleReturnInst ( * MBBI , MBBI -> getFirstTerminator ( ) ) ; } } SmallVector < MachineInstr * , 16 > worklist ; for ( auto MBBI = Func . begin ( ) , MBBE = Func . end ( ) ; MBBI != MBBE ; MBBI ++ ) { for ( auto MI = MBBI -> begin ( ) , ME = MBBI -> end ( ) ; MI != ME ; MI ++ ) if ( MI -> isCall ( ) ) worklist . push_back ( MI ) ; } while ( ! worklist . empty ( ) ) { MachineInstr * mi = worklist . pop_back_val ( ) ; modified |= handleCallInst ( mi ) ; } return modified ; } </s>


"This resolveFrameIndex does not support Thumb1!"

"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> bool SystemZInstrInfo :: isPredicable ( MachineInstr * MI ) const { unsigned Opcode = MI -> getOpcode ( ) ; if ( STI . hasLoadStoreOnCond ( ) && getConditionalMove ( Opcode ) ) return true ; return false ; } </s>

Return true if the specified instruction can be predicated .


<s> void ix86_bd_do_dispatch ( rtx_insn * insn , int mode ) { if ( mode == DISPATCH_INIT ) init_dispatch_sched ( ) ; else if ( mode == ADD_TO_DISPATCH_WINDOW ) add_to_dispatch_window ( insn ) ; } </s>

This routine is the driver of the dispatch scheduler .


";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n"


<s> void X86TargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( Subtarget . getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) || Subtarget . getTargetTriple ( ) . isWindowsItaniumEnvironment ( ) ) { M . getOrInsertGlobal ( "__security_cookie" , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; auto * SecurityCheckCookie = cast < Function > ( M . getOrInsertFunction ( "__security_check_cookie" , Type :: getVoidTy ( M . getContext ( ) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ) ; SecurityCheckCookie -> setCallingConv ( CallingConv :: X86_FastCall ) ; SecurityCheckCookie -> addAttribute ( 1 , Attribute :: AttrKind :: InReg ) ; return ; } if ( hasStackGuardSlotTLS ( Subtarget . getTargetTriple ( ) ) ) return ; TargetLowering :: insertSSPDeclarations ( M ) ; } </s>

Inserts necessary declarations for SSP ( stack protection ) purpose .


<s> static void arm_init_acle_builtins ( void ) { unsigned int i , fcode = ARM_BUILTIN_ACLE_PATTERN_START ; tree sat_check_fpr = build_function_type_list ( void_type_node , intSI_type_node , intSI_type_node , intSI_type_node , NULL ) ; arm_builtin_decls [ ARM_BUILTIN_SAT_IMM_CHECK ] = add_builtin_function ( "__builtin_sat_imm_check" , sat_check_fpr , ARM_BUILTIN_SAT_IMM_CHECK , BUILT_IN_MD , NULL , NULL_TREE ) ; for ( i = 0 ; i < ARRAY_SIZE ( acle_builtin_data ) ; i ++ , fcode ++ ) { arm_builtin_datum * d = & acle_builtin_data [ i ] ; arm_init_builtin ( fcode , d , "__builtin_arm" ) ; } } </s>

Set up ACLE builtins , even builtins for instructions that are not in the current target ISA to allow the user to compile particular modules with different target specific options that differ from the command line options . Such builtins will be rejected in arm_expand_builtin .


<s> virtual const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> Value * Simplifier :: simplify ( Context & C ) { WorkListType Q ; Q . push_back ( C . Root ) ; unsigned Count = 0 ; const unsigned Limit = SimplifyLimit ; while ( ! Q . empty ( ) ) { if ( Count ++ >= Limit ) break ; Instruction * U = dyn_cast < Instruction > ( Q . pop_front_val ( ) ) ; if ( ! U || U -> getParent ( ) || ! C . Used . count ( U ) ) continue ; bool Changed = false ; for ( Rule & R : Rules ) { Value * W = R ( U , C . Ctx ) ; if ( ! W ) continue ; Changed = true ; C . record ( W ) ; C . replace ( U , W ) ; Q . push_back ( C . Root ) ; break ; } if ( ! Changed ) { for ( Value * Op : U -> operands ( ) ) Q . push_back ( Op ) ; } } return Count < Limit ? C . Root : nullptr ; } </s>

Go through all the nodes in the graph and collapse any two nodes ' a ' and ' b ' if all of the following are true :


<s> static void arm_emit_ldrd_pop ( unsigned long saved_regs_mask ) { int j = 0 ; int offset = 0 ; rtx par = NULL_RTX ; rtx dwarf = NULL_RTX ; rtx tmp , mem ; gcc_assert ( ! ( ( saved_regs_mask & ( 1 << SP_REGNUM ) ) ) ) ; j = 0 ; while ( j <= LAST_ARM_REGNUM ) if ( saved_regs_mask & ( 1 << j ) ) { if ( ( j % 2 ) == 0 && ( saved_regs_mask & ( 1 << ( j + 1 ) ) ) && ( j + 1 ) != PC_REGNUM ) { if ( offset > 0 ) mem = gen_frame_mem ( DImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; else mem = gen_frame_mem ( DImode , stack_pointer_rtx ) ; tmp = gen_rtx_SET ( DImode , gen_rtx_REG ( DImode , j ) , mem ) ; tmp = emit_insn ( tmp ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( SImode , j ) , NULL_RTX ) ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( SImode , j + 1 ) , dwarf ) ; REG_NOTES ( tmp ) = dwarf ; offset += 8 ; j += 2 ; } else if ( j != PC_REGNUM ) { if ( offset > 0 ) mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; else mem = gen_frame_mem ( SImode , stack_pointer_rtx ) ; tmp = gen_rtx_SET ( SImode , gen_rtx_REG ( SImode , j ) , mem ) ; tmp = emit_insn ( tmp ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; REG_NOTES ( tmp ) = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( SImode , j ) , NULL_RTX ) ; offset += 4 ; j += 1 ; } else j ++ ; } else j ++ ; if ( offset > 0 ) { tmp = gen_rtx_SET ( Pmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; tmp = emit_insn ( tmp ) ; arm_add_cfa_adjust_cfa_note ( tmp , offset , stack_pointer_rtx , stack_pointer_rtx ) ; offset = 0 ; } if ( saved_regs_mask & ( 1 << PC_REGNUM ) ) { par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( 2 ) ) ; XVECEXP ( par , 0 , 0 ) = ret_rtx ; tmp = gen_rtx_SET ( SImode , gen_rtx_REG ( SImode , PC_REGNUM ) , gen_frame_mem ( SImode , gen_rtx_POST_INC ( SImode , stack_pointer_rtx ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , 1 ) = tmp ; par = emit_jump_insn ( par ) ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( SImode , PC_REGNUM ) , NULL_RTX ) ; REG_NOTES ( par ) = dwarf ; arm_add_cfa_adjust_cfa_note ( par , UNITS_PER_WORD , stack_pointer_rtx , stack_pointer_rtx ) ; } } </s>

LDRD in ARM mode needs consecutive registers as operands . This function emits LDRD whenever possible , otherwise it emits single-word loads . It uses offset addressing and then generates one separate stack udpate . This provides more scheduling freedom , compared to writeback on every load . However , if the function returns using load into PC directly ( i.e. , if PC is in SAVED_REGS_MASK ) , the stack needs to be updated before the last load . TODO : Add a peephole optimization to recognize the new epilogue sequence as an LDM instruction whenever possible . TODO : Add peephole optimization to merge the load at stack-offset zero with the stack update instruction using load with writeback in post-index addressing mode .


"AMDGPU Code Object Metadata Parser Test: "


<s>
void
setReg
(
unsigned
Reg
)
{
assert
(
isRegBase
(
)
&&
"Invalid base register access!"
)
;
assert
(
Base
.
Reg
==
0
&&
"Overwriting non-zero register"
)
;
Base
.
Reg
=
Reg
;
}
</s>

Assigns the associated register for this edge .

WebAssembly
"Invalid base register access!"
0
"Overwriting non-zero register"


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < AssumptionCacheTracker > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . setPreservesCFG ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static void s390_indirect_branch_settings ( tree fndecl ) { tree attr ; if ( ! fndecl ) return ; cfun -> machine -> indirect_branch_jump = s390_indirect_branch_jump ; cfun -> machine -> indirect_branch_call = s390_indirect_branch_call ; cfun -> machine -> function_return_reg = s390_function_return_reg ; cfun -> machine -> function_return_mem = s390_function_return_mem ; if ( ( attr = lookup_attribute ( "indirect_branch" , DECL_ATTRIBUTES ( fndecl ) ) ) ) { s390_indirect_branch_attrvalue ( attr , & cfun -> machine -> indirect_branch_jump ) ; s390_indirect_branch_attrvalue ( attr , & cfun -> machine -> indirect_branch_call ) ; } if ( ( attr = lookup_attribute ( "indirect_branch_jump" , DECL_ATTRIBUTES ( fndecl ) ) ) ) s390_indirect_branch_attrvalue ( attr , & cfun -> machine -> indirect_branch_jump ) ; if ( ( attr = lookup_attribute ( "indirect_branch_call" , DECL_ATTRIBUTES ( fndecl ) ) ) ) s390_indirect_branch_attrvalue ( attr , & cfun -> machine -> indirect_branch_call ) ; if ( ( attr = lookup_attribute ( "function_return" , DECL_ATTRIBUTES ( fndecl ) ) ) ) { s390_indirect_branch_attrvalue ( attr , & cfun -> machine -> function_return_reg ) ; s390_indirect_branch_attrvalue ( attr , & cfun -> machine -> function_return_mem ) ; } if ( ( attr = lookup_attribute ( "function_return_reg" , DECL_ATTRIBUTES ( fndecl ) ) ) ) s390_indirect_branch_attrvalue ( attr , & cfun -> machine -> function_return_reg ) ; if ( ( attr = lookup_attribute ( "function_return_mem" , DECL_ATTRIBUTES ( fndecl ) ) ) ) s390_indirect_branch_attrvalue ( attr , & cfun -> machine -> function_return_mem ) ; } </s>

Memorize the setting for -mindirect-branch * and -mfunction-return * from either the cmdline or the function attributes in cfun- > machine .


<s> MachineInstrBuilder SIInstrInfo :: getAddNoCarry ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , Register DestReg , RegScavenger & RS ) const { if ( ST . hasAddNoCarry ( ) ) return BuildMI ( MBB , I , DL , get ( AMDGPU :: V_ADD_U32_e32 ) , DestReg ) ; Register UnusedCarry = RS . scavengeRegister ( RI . getBoolRC ( ) , I , 0 , false ) ; if ( ! UnusedCarry . isValid ( ) ) return MachineInstrBuilder ( ) ; return BuildMI ( MBB , I , DL , get ( AMDGPU :: V_ADD_I32_e64 ) , DestReg ) . addReg ( UnusedCarry , RegState :: Define | RegState :: Dead ) ; } </s>

Return a partially built integer add instruction without carry .


<s> SDNode * SparcDAGToDAGISel :: Select ( SDNode * N ) { SDLoc dl ( N ) ; if ( N -> isMachineOpcode ( ) ) { N -> setNodeId ( - 1 ) ; return nullptr ; } switch ( N -> getOpcode ( ) ) { default : break ; case SPISD :: GLOBAL_BASE_REG : return getGlobalBaseReg ( ) ; case ISD :: SDIV : case ISD :: UDIV : { if ( N -> getValueType ( 0 ) == MVT :: i64 ) break ; SDValue DivLHS = N -> getOperand ( 0 ) ; SDValue DivRHS = N -> getOperand ( 1 ) ; SDValue TopPart ; if ( N -> getOpcode ( ) == ISD :: SDIV ) { TopPart = SDValue ( CurDAG -> getMachineNode ( SP :: SRAri , dl , MVT :: i32 , DivLHS , CurDAG -> getTargetConstant ( 31 , dl , MVT :: i32 ) ) , 0 ) ; } else { TopPart = CurDAG -> getRegister ( SP :: G0 , MVT :: i32 ) ; } TopPart = SDValue ( CurDAG -> getMachineNode ( SP :: WRASRrr , dl , MVT :: i32 , TopPart , CurDAG -> getRegister ( SP :: G0 , MVT :: i32 ) ) , 0 ) ; TopPart = CurDAG -> getCopyToReg ( TopPart , dl , SP :: Y , TopPart , SDValue ( ) ) . getValue ( 1 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: SDIV ? SP :: SDIVrr : SP :: UDIVrr ; return CurDAG -> SelectNodeTo ( N , Opcode , MVT :: i32 , DivLHS , DivRHS , TopPart ) ; } case ISD :: MULHU : case ISD :: MULHS : { SDValue MulLHS = N -> getOperand ( 0 ) ; SDValue MulRHS = N -> getOperand ( 1 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: MULHU ? SP :: UMULrr : SP :: SMULrr ; SDNode * Mul = CurDAG -> getMachineNode ( Opcode , dl , MVT :: i32 , MVT :: Glue , MulLHS , MulRHS ) ; return CurDAG -> SelectNodeTo ( N , SP :: RDASR , MVT :: i32 , CurDAG -> getRegister ( SP :: Y , MVT :: i32 ) , SDValue ( Mul , 1 ) ) ; } } return SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> bool PPCAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( ! isDarwin ( ) ) { if ( IDVal == ".word" ) return ParseDirectiveWord ( 2 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".llong" ) return ParseDirectiveWord ( 8 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".tc" ) return ParseDirectiveTC ( isPPC64 ( ) ? 8 : 4 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".machine" ) return ParseDirectiveMachine ( DirectiveID . getLoc ( ) ) ; } else { if ( IDVal == ".machine" ) return ParseDarwinDirectiveMachine ( DirectiveID . getLoc ( ) ) ; } return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> rtx rs6000_libcall_value ( machine_mode mode ) { unsigned int regno ; if ( TARGET_32BIT && TARGET_POWERPC64 && mode == DImode ) return rs6000_parallel_return ( mode , 2 , SImode , GP_ARG_RETURN , 1 ) ; if ( DECIMAL_FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = ( mode == TDmode ) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN ; else if ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS && ( ( TARGET_SINGLE_FLOAT && mode == SFmode ) || TARGET_DOUBLE_FLOAT ) ) regno = FP_ARG_RETURN ; else if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI ) regno = ALTIVEC_ARG_RETURN ; else if ( COMPLEX_MODE_P ( mode ) && targetm . calls . split_complex_arg ) return rs6000_complex_function_value ( mode ) ; else if ( TARGET_E500_DOUBLE && TARGET_HARD_FLOAT && ( mode == DFmode || mode == DCmode || FLOAT128_IBM_P ( mode ) || mode == TCmode ) ) return spe_build_register_parallel ( mode , GP_ARG_RETURN ) ; else regno = GP_ARG_RETURN ; return gen_rtx_REG ( mode , regno ) ; } </s>

Define how to find the value returned by a library function assuming the value has mode MODE .


"Not keeping track of debug information yet!!"

Map a target register to an equivalent dwarf register number .


<s> bool X86PassConfig :: addPreEmitPass ( ) { bool ShouldPrint = false ; if ( getOptLevel ( ) != CodeGenOpt :: None && getX86Subtarget ( ) . hasSSE2 ( ) ) { PM . add ( createExecutionDependencyFixPass ( & X86 :: VR128RegClass ) ) ; ShouldPrint = true ; } if ( getX86Subtarget ( ) . hasAVX ( ) && UseVZeroUpper ) { PM . add ( createX86IssueVZeroUpperPass ( ) ) ; ShouldPrint = true ; } return ShouldPrint ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void AMDGPUDAGToDAGISel :: PostprocessISelDAG ( ) { if ( Subtarget . getGeneration ( ) < AMDGPUSubtarget :: SOUTHERN_ISLANDS ) { return ; } const AMDGPUTargetLowering & Lowering = ( * ( const AMDGPUTargetLowering * ) getTargetLowering ( ) ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ++ I ) { SDNode * Node = I ; MachineSDNode * MachineNode = dyn_cast < MachineSDNode > ( I ) ; if ( ! MachineNode ) continue ; SDNode * ResNode = Lowering . PostISelFolding ( MachineNode , * CurDAG ) ; if ( ResNode != Node ) { ReplaceUses ( Node , ResNode ) ; } } } </s>

PostprocessISelDAG ( ) - This hook allows the target to hack on the graph right after selection .


<s> bool ARM64TargetLowering :: isEligibleForTailCallOptimization ( SDValue Callee , CallingConv :: ID CalleeCC , bool isVarArg , bool isCalleeStructRet , bool isCallerStructRet , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SmallVectorImpl < ISD :: InputArg > & Ins , SelectionDAG & DAG ) const { if ( isVarArg && ! Outs . empty ( ) ) return false ; if ( isCalleeStructRet || isCallerStructRet ) return false ; if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , 16 > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCAssignFn * AssignFn = CCAssignFnForCall ( CalleeCC , false ) ; CCInfo . AnalyzeCallOperands ( Outs , AssignFn ) ; if ( CCInfo . getNextStackOffset ( ) ) { for ( unsigned i = 0 , realArgIdx = 0 , e = ArgLocs . size ( ) ; i != e ; ++ i , ++ realArgIdx ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( VA . needsCustom ( ) ) { return false ; } else if ( ! VA . isRegLoc ( ) ) { return false ; } } } } return true ; } </s>

Returns true if the call can be lowered as a tail call .


<s> static void compute_save_world_info ( rs6000_stack_t * info_ptr ) { info_ptr -> world_save_p = 1 ; info_ptr -> world_save_p = ( WORLD_SAVE_P ( info_ptr ) && DEFAULT_ABI == ABI_DARWIN && ! cfun -> has_nonlocal_label && info_ptr -> first_fp_reg_save == FIRST_SAVED_FP_REGNO && info_ptr -> first_gp_reg_save == FIRST_SAVED_GP_REGNO && info_ptr -> first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO && info_ptr -> cr_save_p ) ; if ( WORLD_SAVE_P ( info_ptr ) ) { rtx_insn * insn ; for ( insn = get_last_insn_anywhere ( ) ; insn ; insn = PREV_INSN ( insn ) ) if ( CALL_P ( insn ) && SIBLING_CALL_P ( insn ) ) { info_ptr -> world_save_p = 0 ; break ; } } if ( WORLD_SAVE_P ( info_ptr ) ) { info_ptr -> vrsave_size = 4 ; info_ptr -> lr_save_p = 1 ; if ( info_ptr -> vrsave_mask == 0 ) info_ptr -> vrsave_mask = compute_vrsave_mask ( ) ; gcc_assert ( info_ptr -> first_fp_reg_save >= FIRST_SAVED_FP_REGNO && ( info_ptr -> first_altivec_reg_save >= FIRST_SAVED_ALTIVEC_REGNO ) ) ; } return ; } </s>

For a very restricted set of circumstances , we can cut down the size of prologues/epilogues by calling our own save/restore-the-world routines .


<s> bool Z80AsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { llvm_unreachable ( "Unimplemented" ) ; } </s>

ParseInstruction - Parse one assembly instruction .


"Trying RISCV32Only_16 table (16-bit Instruction):\n"

"Trying RVBC32 table (BitManip 16-bit Instruction):\n"

"Trying RISCV_C table (16-bit Instruction):\n"

Returns the disassembly of a single instruction .


<s> static bool moxie_fixed_condition_code_regs ( unsigned int * p1 , unsigned int * p2 ) { * p1 = CC_REG ; * p2 = INVALID_REGNUM ; return true ; } </s>

Return the fixed registers used for condition codes .


<s> static void frv_trampoline_init ( rtx m_tramp , tree fndecl , rtx static_chain ) { rtx addr = XEXP ( m_tramp , 0 ) ; rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx sc_reg = force_reg ( Pmode , static_chain ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( SImode , "__trampoline_setup" ) , LCT_NORMAL , VOIDmode , addr , Pmode , GEN_INT ( frv_trampoline_size ( ) ) , SImode , fnaddr , Pmode , sc_reg , Pmode ) ; } </s>

A C statement to initialize the variable parts of a trampoline . ADDR is an RTX for the address of the trampoline ; FNADDR is an RTX for the address of the nested function ; STATIC_CHAIN is an RTX for the static chain value that should be passed to the function when it is called . The template is : setlo # 0 , < jmp_reg > setlo # 0 , < static_chain > sethi # 0 , < jmp_reg > sethi # 0 , < static_chain > jmpl @ ( gr0 , < jmp_reg > )


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Hexagon Expand Condsets"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static void or1k_print_operand_address ( FILE * file , machine_mode , rtx addr ) { rtx offset ; switch ( GET_CODE ( addr ) ) { case REG : fputc ( '0' , file ) ; break ; case PLUS : offset = XEXP ( addr , 1 ) ; addr = XEXP ( addr , 0 ) ; gcc_assert ( CONST_INT_P ( offset ) ) ; if ( GET_CODE ( addr ) == LO_SUM ) { print_reloc ( file , XEXP ( addr , 1 ) , INTVAL ( offset ) , RKIND_LO ) ; addr = XEXP ( addr , 0 ) ; } else output_addr_const ( file , offset ) ; break ; case LO_SUM : offset = XEXP ( addr , 1 ) ; addr = XEXP ( addr , 0 ) ; print_reloc ( file , offset , 0 , RKIND_LO ) ; break ; default : output_addr_const ( file , addr ) ; return ; } fprintf ( file , "(%s)" , reg_names [ REGNO ( addr ) ] ) ; } </s>

Worker for TARGET_PRINT_OPERAND_ADDRESS . Prints the argument ADDR , an address RTX , to the file FILE . The output is formed as expected by the OpenRISC assembler . Examples : RTX OUTPUT ( reg : SI 3 ) 0 ( r3 ) ( plus : SI ( reg : SI 3 ) ( const_int 4 ) ) 0x4 ( r3 ) ( lo_sum : SI ( reg : SI 3 ) ( symbol_ref : SI ( `` x '' ) ) ) ) lo ( x ) ( r3 )


"Should be loading %r15 and something else"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s>
char
*
aarch64_output_sve_mov_immediate
(
rtx
const_vector
)
{
static
char
templ
[
40
]
;
struct
simd_immediate_info
info
;
char
element_char
;
bool
is_valid
=
aarch64_simd_valid_immediate
(
const_vector
,
&
info
)
;
gcc_assert
(
is_valid
)
;
element_char
=
sizetochar
(
GET_MODE_BITSIZE
(
info
.
elt_mode
)
)
;
machine_mode
vec_mode
=
GET_MODE
(
const_vector
)
;
if
(
aarch64_sve_pred_mode_p
(
vec_mode
)
)
{
static
char
buf
[
sizeof
(
"ptrue\t%0.N, vlNNNNN"
)
]
;
if
(
info
.
insn
==
simd_immediate_info
::
MOV
)
{
gcc_assert
(
info
.
u
.
mov
.
value
==
const0_rtx
)
;
snprintf
(
buf
,
sizeof
(
buf
)
,
"pfalse\t%%0.b"
)
;
}
else
{
gcc_assert
(
info
.
insn
==
simd_immediate_info
::
PTRUE
)
;
unsigned
int
total_bytes
;
if
(
info
.
u
.
pattern
==
AARCH64_SV_ALL
&&
BYTES_PER_SVE_VECTOR
.
is_constant
(
&
total_bytes
)
)
snprintf
(
buf
,
sizeof
(
buf
)
,
"ptrue\t%%0.%c, vl%d"
,
element_char
,
total_bytes
/
GET_MODE_SIZE
(
info
.
elt_mode
)
)
;
else
snprintf
(
buf
,
sizeof
(
buf
)
,
"ptrue\t%%0.%c, %s"
,
element_char
,
svpattern_token
(
info
.
u
.
pattern
)
)
;
}
return
buf
;
}
if
(
info
.
insn
==
simd_immediate_info
::
INDEX
)
{
snprintf
(
templ
,
sizeof
(
templ
)
,
"index\t%%0.%c, #"
HOST_WIDE_INT_PRINT_DEC
", #"
HOST_WIDE_INT_PRINT_DEC
,
element_char
,
INTVAL
(
info
.
u
.
index
.
base
)
,
INTVAL
(
info
.
u
.
index
.
step
)
)
;
return
templ
;
}
if
(
GET_MODE_CLASS
(
info
.
elt_mode
)
==
MODE_FLOAT
)
{
if
(
aarch64_float_const_zero_rtx_p
(
info
.
u
.
mov
.
value
)
)
info
.
u
.
mov
.
value
=
GEN_INT
(
0
)
;
else
{
const
int
buf_size
=
20
;
char
float_buf
[
buf_size
]
=
{
}
;
real_to_decimal_for_mode
(
float_buf
,
CONST_DOUBLE_REAL_VALUE
(
info
.
u
.
mov
.
value
)
,
buf_size
,
buf_size
,
1
,
info
.
elt_mode
)
;
snprintf
(
templ
,
sizeof
(
templ
)
,
"fmov\t%%0.%c, #%s"
,
element_char
,
float_buf
)
;
return
templ
;
}
}
snprintf
(
templ
,
sizeof
(
templ
)
,
"mov\t%%0.%c, #"
HOST_WIDE_INT_PRINT_DEC
,
element_char
,
INTVAL
(
info
.
u
.
mov
.
value
)
)
;
return
templ
;
}
</s>

Return the output string to use for moving immediate CONST_VECTOR into an SVE register .


<s> int CompositeHandler :: getNumElements ( Type * Ty , bool AccessMemFormFlatStruct ) { int NumElems = 0 ; Type * TyKey = reinterpret_cast < Type * > ( reinterpret_cast < char * > ( Ty ) + ( int ) AccessMemFormFlatStruct ) ; if ( typeNumElemCache . find ( TyKey ) != typeNumElemCache . end ( ) ) return typeNumElemCache [ TyKey ] ; if ( isa < StructType > ( Ty ) ) { StructType * STy = cast < StructType > ( Ty ) ; for ( StructType :: element_iterator EB = STy -> element_begin ( ) , EI = EB , EE = STy -> element_end ( ) ; EI != EE ; ++ EI ) { if ( CompositeType :: classof ( * EI ) ) NumElems += getNumElements ( * EI , AccessMemFormFlatStruct ) ; else NumElems += 1 ; } } else if ( isa < ArrayType > ( Ty ) ) { Type * ElmTy = cast < ArrayType > ( Ty ) -> getElementType ( ) ; bool exploreArr = ! CheckIfFlattendType ( ElmTy ) || ! AccessMemFormFlatStruct ; if ( isa < StructType > ( ElmTy ) || ( isa < ArrayType > ( ElmTy ) && exploreArr ) ) { int NumArrElems = cast < ArrayType > ( Ty ) -> getNumElements ( ) ; NumElems += NumArrElems * getNumElements ( ElmTy , AccessMemFormFlatStruct ) ; } else NumElems += exploreArr ? cast < ArrayType > ( Ty ) -> getNumElements ( ) : 1 ; } else if ( isa < PointerType > ( Ty ) ) { NumElems += getNumElements ( cast < PointerType > ( Ty ) -> getElementType ( ) , AccessMemFormFlatStruct ) ; } else NumElems += 1 ; typeNumElemCache [ TyKey ] = NumElems ; return NumElems ; } </s>


<s> Loc ( MachineBasicBlock * B , MachineBasicBlock :: iterator It ) : Block ( B ) , At ( It ) { if ( B -> end ( ) == It ) { Pos = - 1 ; } else { assert ( It -> getParent ( ) == B ) ; Pos = std :: distance ( B -> begin ( ) , It ) ; } } </s>

The location in the match file that the check string was specified .


<s> TargetStackID :: Value getStackIDForScalableVectors ( ) const override { return TargetStackID :: RISCVVector ; } </s>

Returns the StackID that scalable vectors should be associated with .


<s> static reg_class_t alpha_secondary_reload ( bool in_p , rtx x , reg_class_t rclass_i , machine_mode mode , secondary_reload_info * sri ) { enum reg_class rclass = ( enum reg_class ) rclass_i ; if ( ! TARGET_BWX && ( mode == QImode || mode == HImode || mode == CQImode ) ) { if ( any_memory_operand ( x , mode ) ) { if ( in_p ) { if ( ! aligned_memory_operand ( x , mode ) ) sri -> icode = direct_optab_handler ( reload_in_optab , mode ) ; } else sri -> icode = direct_optab_handler ( reload_out_optab , mode ) ; return NO_REGS ; } } if ( rclass == FLOAT_REGS ) { if ( MEM_P ( x ) && GET_CODE ( XEXP ( x , 0 ) ) == AND ) return GENERAL_REGS ; if ( in_p && INTEGRAL_MODE_P ( mode ) && ! MEM_P ( x ) && ! REG_P ( x ) && ! CONST_INT_P ( x ) ) return GENERAL_REGS ; } return NO_REGS ; } </s>

Inform reload about cases where moving X with a mode MODE to a register in RCLASS requires an extra scratch or immediate register . Return the class needed for the immediate register .


<s> void h8300_swap_into_er6 ( rtx addr ) { rtx insn = push ( HARD_FRAME_POINTER_REGNUM , false ) ; if ( frame_pointer_needed ) add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , gen_rtx_MEM ( Pmode , stack_pointer_rtx ) , 2 * UNITS_PER_WORD ) ) ; else add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , 4 ) ) ) ; emit_move_insn ( hard_frame_pointer_rtx , addr ) ; if ( REGNO ( addr ) == SP_REG ) emit_move_insn ( hard_frame_pointer_rtx , plus_constant ( Pmode , hard_frame_pointer_rtx , GET_MODE_SIZE ( word_mode ) ) ) ; } </s>

Move ADDR into er6 after pushing its old value onto the stack .


<s> bool HexagonTargetLowering :: hasBitTest ( SDValue X , SDValue Y ) const { return X . getValueType ( ) . isScalarInteger ( ) ; } </s>

Return true if the target has a bit-test instruction : ( X & ( 1 < < Y ) ) ==/ ! = 0 This knowledge can be used to prevent breaking the pattern , or creating it if it could be recognized .


<s>
bool
SNESExpandPseudo
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
bool
Modified
=
false
;
const
SNESSubtarget
&
STI
=
MF
.
getSubtarget
<
SNESSubtarget
>
(
)
;
TRI
=
STI
.
getRegisterInfo
(
)
;
TII
=
STI
.
getInstrInfo
(
)
;
MF
.
getProperties
(
)
.
set
(
MachineFunctionProperties
::
Property
::
TracksLiveness
)
;
for
(
Block
&
MBB
:
MF
)
{
bool
ContinueExpanding
=
true
;
unsigned
ExpandCount
=
0
;
do
{
assert
(
ExpandCount
<
10
&&
"pseudo expand limit reached"
)
;
bool
BlockModified
=
expandMBB
(
MBB
)
;
Modified
|=
BlockModified
;
ExpandCount
++
;
ContinueExpanding
=
BlockModified
;
}
while
(
ContinueExpanding
)
;
}
return
Modified
;
}
</s>

runOnMachineFunction - Emit the function body .

SNES
SNES
SNES
SNES
0
10
"pseudo expand limit reached"


<s> int loongarch_regno_mode_ok_for_base_p ( int regno , machine_mode mode ATTRIBUTE_UNUSED , bool strict_p ) { if ( ! HARD_REGISTER_NUM_P ( regno ) ) { if ( ! strict_p ) return true ; regno = reg_renumber [ regno ] ; } if ( regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM ) return true ; return GP_REG_P ( regno ) ; } </s>

Return true if register REGNO is a valid base register for mode MODE . STRICT_P is true if REG_OK_STRICT is in effect .


"frame pointer should not have been eliminated"


"Cannot store this register to stack slot!"

Load the specified register of the given register class from the specified stack frame index .


<s> bool SIFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MFI . hasStackObjects ( ) && ! allStackObjectsAreDead ( MFI ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> EVT X86TargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i8 ; const TargetMachine & TM = getTargetMachine ( ) ; if ( ! TM . Options . UseSoftFloat && Subtarget -> hasAVX512 ( ) ) switch ( VT . getVectorNumElements ( ) ) { case 8 : return MVT :: v8i1 ; case 16 : return MVT :: v16i1 ; } return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> bool TeakFrameLowering :: hasFP ( const MachineFunction & MF ) const { return true ; } </s>


<s> std :: pair < unsigned , const TargetRegisterClass * > PPCTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'b' : if ( VT == MVT :: i64 && Subtarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RC_NOX0RegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRC_NOR0RegClass ) ; case 'r' : if ( VT == MVT :: i64 && Subtarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RCRegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRCRegClass ) ; case 'f' : if ( VT == MVT :: f32 || VT == MVT :: i32 ) return std :: make_pair ( 0U , & PPC :: F4RCRegClass ) ; if ( VT == MVT :: f64 || VT == MVT :: i64 ) return std :: make_pair ( 0U , & PPC :: F8RCRegClass ) ; break ; case 'v' : return std :: make_pair ( 0U , & PPC :: VRRCRegClass ) ; case 'y' : return std :: make_pair ( 0U , & PPC :: CRRCRegClass ) ; } } else if ( Constraint == "wc" ) { return std :: make_pair ( 0U , & PPC :: CRBITRCRegClass ) ; } else if ( Constraint == "wa" || Constraint == "wd" || Constraint == "wf" ) { return std :: make_pair ( 0U , & PPC :: VSRCRegClass ) ; } else if ( Constraint == "ws" ) { return std :: make_pair ( 0U , & PPC :: VSFRCRegClass ) ; } std :: pair < unsigned , const TargetRegisterClass * > R = TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; if ( R . first && VT == MVT :: i64 && Subtarget . isPPC64 ( ) && PPC :: GPRCRegClass . contains ( R . first ) ) { const TargetRegisterInfo * TRI = getTargetMachine ( ) . getRegisterInfo ( ) ; return std :: make_pair ( TRI -> getMatchingSuperReg ( R . first , PPC :: sub_32 , & PPC :: G8RCRegClass ) , & PPC :: G8RCRegClass ) ; } if ( ! R . second && StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) { R . first = PPC :: CR0 ; R . second = & PPC :: CRRCRegClass ; } return R ; } </s>

Given a physical register constraint ( e.g .


<s> static unsigned getReg ( const void * D , unsigned RC , unsigned RegNo ) { const AArch64Disassembler * Dis = static_cast < const AArch64Disassembler * > ( D ) ; const MCRegisterInfo * RegInfo = Dis -> getContext ( ) . getRegisterInfo ( ) ; return RegInfo -> getRegClass ( RC ) . getRegister ( RegNo ) ; } </s>

Returns the register associated with this edge .


<s>
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
Cpu0TargetLowering
::
getRegForInlineAsmConstraint
(
const
TargetRegisterInfo
*
TRI
,
StringRef
Constraint
,
MVT
VT
)
const
{
if
(
Constraint
.
size
(
)
==
1
)
{
switch
(
Constraint
[
0
]
)
{
case
'r'
:
if
(
VT
==
MVT
::
i32
||
VT
==
MVT
::
i16
||
VT
==
MVT
::
i8
)
{
return
std
::
make_pair
(
0U
,
&
Cpu0
::
CPURegsRegClass
)
;
}
if
(
VT
==
MVT
::
i64
)
return
std
::
make_pair
(
0U
,
&
Cpu0
::
CPURegsRegClass
)
;
return
std
::
make_pair
(
0U
,
static_cast
<
const
TargetRegisterClass
*
>
(
0
)
)
;
case
'c'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
(
unsigned
)
Cpu0
::
T9
,
&
Cpu0
::
CPURegsRegClass
)
;
assert
(
false
&&
"Unexpected type."
)
;
}
}
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
R
;
R
=
ParseRegForInlineAsmConstraint
(
Constraint
,
VT
)
;
if
(
R
.
second
)
return
R
;
return
TargetLowering
::
getRegForInlineAsmConstraint
(
TRI
,
Constraint
,
VT
)
;
}
</s>


<s> static rtx rs6000_function_value ( const_tree valtype , const_tree fn_decl_or_type ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode mode ; unsigned int regno ; machine_mode elt_mode ; int n_elts ; if ( TARGET_MACHO && rs6000_darwin64_struct_check_p ( TYPE_MODE ( valtype ) , valtype ) ) { CUMULATIVE_ARGS valcum ; rtx valret ; valcum . words = 0 ; valcum . fregno = FP_ARG_MIN_REG ; valcum . vregno = ALTIVEC_ARG_MIN_REG ; valret = rs6000_darwin64_record_arg ( & valcum , valtype , true , true ) ; if ( valret ) return valret ; } mode = TYPE_MODE ( valtype ) ; if ( rs6000_discover_homogeneous_aggregate ( mode , valtype , & elt_mode , & n_elts ) ) { int first_reg , n_regs ; if ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( elt_mode ) ) { first_reg = ( elt_mode == TDmode ) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN ; n_regs = ( GET_MODE_SIZE ( elt_mode ) + 7 ) >> 3 ; } else { first_reg = ALTIVEC_ARG_RETURN ; n_regs = 1 ; } return rs6000_parallel_return ( mode , n_elts , elt_mode , first_reg , n_regs ) ; } if ( TARGET_32BIT && TARGET_POWERPC64 ) switch ( mode ) { default : break ; case E_DImode : case E_SCmode : case E_DCmode : case E_TCmode : int count = GET_MODE_SIZE ( mode ) / 4 ; return rs6000_parallel_return ( mode , count , SImode , GP_ARG_RETURN , 1 ) ; } if ( ( INTEGRAL_TYPE_P ( valtype ) && GET_MODE_BITSIZE ( mode ) < ( TARGET_32BIT ? 32 : 64 ) ) || POINTER_TYPE_P ( valtype ) ) mode = TARGET_32BIT ? SImode : DImode ; if ( DECIMAL_FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = ( mode == TDmode ) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN ; else if ( SCALAR_FLOAT_TYPE_P ( valtype ) && TARGET_HARD_FLOAT && TARGET_FPRS && ! FLOAT128_VECTOR_P ( mode ) && ( ( TARGET_SINGLE_FLOAT && ( mode == SFmode ) ) || TARGET_DOUBLE_FLOAT ) ) regno = FP_ARG_RETURN ; else if ( TREE_CODE ( valtype ) == COMPLEX_TYPE && targetm . calls . split_complex_arg ) return rs6000_complex_function_value ( mode ) ; else if ( ( TREE_CODE ( valtype ) == VECTOR_TYPE || FLOAT128_VECTOR_P ( mode ) ) && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI && ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) ) regno = ALTIVEC_ARG_RETURN ; else if ( TARGET_E500_DOUBLE && TARGET_HARD_FLOAT && ( mode == DFmode || mode == DCmode || FLOAT128_IBM_P ( mode ) || mode == TCmode ) ) return spe_build_register_parallel ( mode , GP_ARG_RETURN ) ; else regno = GP_ARG_RETURN ; return gen_rtx_REG ( mode , regno ) ; } </s>

Define how to find the value returned by a function . VALTYPE is the data type of the value ( as a tree ) . If the precise function being called is known , FUNC is its FUNCTION_DECL ; otherwise , FUNC is 0 . On the SPE , both FPs and vectors are returned in r3 . On RS/6000 an integer value is in r3 and a floating-point value is in fp1 , unless -msoft-float .


<s>
void
LoongArchMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
unsigned
Size
=
Desc
.
getSize
(
)
;
switch
(
Size
)
{
default
:
llvm_unreachable
(
"Unhandled encodeInstruction length!"
)
;
case
4
:
{
uint32_t
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
support
::
endian
::
write
(
OS
,
Bits
,
support
::
little
)
;
break
;
}
}
}
</s>

Encode the given Inst to bytes and append to CB .

LoongArch
LoongArch
"Unhandled encodeInstruction length!"
4
support::endian
support::little


<s> static unsigned int aarch64_classify_vector_mode ( machine_mode mode ) { if ( aarch64_advsimd_struct_mode_p ( mode ) ) return VEC_ADVSIMD | VEC_STRUCT ; if ( aarch64_sve_pred_mode_p ( mode ) ) return VEC_SVE_PRED ; switch ( mode ) { case E_VNx2QImode : case E_VNx4QImode : case E_VNx8QImode : case E_VNx2HImode : case E_VNx4HImode : case E_VNx2SImode : case E_VNx2HFmode : case E_VNx4HFmode : case E_VNx2BFmode : case E_VNx4BFmode : case E_VNx2SFmode : return TARGET_SVE ? VEC_SVE_DATA | VEC_PARTIAL : 0 ; case E_VNx16QImode : case E_VNx8HImode : case E_VNx4SImode : case E_VNx2DImode : case E_VNx8BFmode : case E_VNx8HFmode : case E_VNx4SFmode : case E_VNx2DFmode : return TARGET_SVE ? VEC_SVE_DATA : 0 ; case E_VNx32QImode : case E_VNx16HImode : case E_VNx8SImode : case E_VNx4DImode : case E_VNx16BFmode : case E_VNx16HFmode : case E_VNx8SFmode : case E_VNx4DFmode : case E_VNx48QImode : case E_VNx24HImode : case E_VNx12SImode : case E_VNx6DImode : case E_VNx24BFmode : case E_VNx24HFmode : case E_VNx12SFmode : case E_VNx6DFmode : case E_VNx64QImode : case E_VNx32HImode : case E_VNx16SImode : case E_VNx8DImode : case E_VNx32BFmode : case E_VNx32HFmode : case E_VNx16SFmode : case E_VNx8DFmode : return TARGET_SVE ? VEC_SVE_DATA | VEC_STRUCT : 0 ; case E_V8QImode : case E_V4HImode : case E_V2SImode : case E_V4HFmode : case E_V4BFmode : case E_V2SFmode : case E_V1DFmode : case E_V16QImode : case E_V8HImode : case E_V4SImode : case E_V2DImode : case E_V8HFmode : case E_V8BFmode : case E_V4SFmode : case E_V2DFmode : return TARGET_SIMD ? VEC_ADVSIMD : 0 ; default : return 0 ; } } </s>

Return a set of flags describing the vector properties of mode MODE . Ignore modes that are not supported by the current target .


<s> bool riscv_hard_regno_mode_ok_p ( unsigned int regno , enum machine_mode mode ) { unsigned int nregs = riscv_hard_regno_nregs ( regno , mode ) ; if ( GP_REG_P ( regno ) ) { if ( ! GP_REG_P ( regno + nregs - 1 ) ) return false ; } else if ( FP_REG_P ( regno ) ) { if ( ! FP_REG_P ( regno + nregs - 1 ) ) return false ; if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && GET_MODE_CLASS ( mode ) != MODE_COMPLEX_FLOAT ) return false ; if ( GET_MODE_UNIT_SIZE ( mode ) > UNITS_PER_FP_REG || ( ! call_used_regs [ regno ] && GET_MODE_UNIT_SIZE ( mode ) > UNITS_PER_FP_ARG ) ) return false ; } else return false ; for ( unsigned i = 1 ; i < nregs ; i ++ ) if ( call_used_regs [ regno ] != call_used_regs [ regno + i ] ) return false ; return true ; } </s>

Return true if register REGNO can store a value of mode MODE .


<s> SparcSubtarget & SparcSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { UseSoftMulDiv = false ; IsV9 = false ; IsLeon = false ; V8DeprecatedInsts = false ; IsVIS = false ; IsVIS2 = false ; IsVIS3 = false ; HasHardQuad = false ; UsePopc = false ; UseSoftFloat = false ; HasNoFSMULD = false ; HasNoFMULS = false ; HasLeonCasa = false ; HasUmacSmac = false ; HasPWRPSR = false ; InsertNOPLoad = false ; FixAllFDIVSQRT = false ; DetectRoundChange = false ; HasLeonCycleCounter = false ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? "v9" : "v8" ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( ! IsV9 ) UsePopc = false ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


"loadRegFromStackSlot didn't insert any code!"

"Save/restore libcall not implemented for purecap"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static bool arm_9e_rtx_costs ( rtx x , enum rtx_code code , enum rtx_code outer_code , int * total , bool speed ) { machine_mode mode = GET_MODE ( x ) ; if ( TARGET_THUMB1 ) { switch ( code ) { case MULT : if ( arm_arch6m && arm_m_profile_small_mul ) * total = COSTS_N_INSNS ( 32 ) ; else * total = COSTS_N_INSNS ( 3 ) ; return true ; default : * total = thumb1_rtx_costs ( x , code , outer_code ) ; return true ; } } switch ( code ) { case MULT : if ( mode == DImode && ( GET_CODE ( XEXP ( x , 0 ) ) == GET_CODE ( XEXP ( x , 1 ) ) ) && ( GET_CODE ( XEXP ( x , 0 ) ) == ZERO_EXTEND || GET_CODE ( XEXP ( x , 0 ) ) == SIGN_EXTEND ) ) { * total = COSTS_N_INSNS ( 2 ) ; return false ; } if ( mode == DImode ) { * total = COSTS_N_INSNS ( 5 ) ; return false ; } if ( mode == SImode ) { * total = COSTS_N_INSNS ( 2 ) ; return false ; } if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { if ( TARGET_HARD_FLOAT && ( mode == SFmode || ( mode == DFmode && ! TARGET_VFP_SINGLE ) ) ) { * total = COSTS_N_INSNS ( 1 ) ; return false ; } } * total = COSTS_N_INSNS ( 20 ) ; return false ; default : return arm_rtx_costs_1 ( x , outer_code , total , speed ) ; } } </s>


<s> bool shouldFormOverflowOp ( unsigned Opcode , EVT VT , bool MathUsed ) const override { return TargetLowering :: shouldFormOverflowOp ( Opcode , VT , true ) ; } </s>

Overflow nodes should get combined/lowered to optimal instructions ( they should allow eliminating explicit compares by getting flags from math ops ) .


<s>
virtual
StringRef
getPassName
(
)
const
{
return
"TGSI Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> int mips_regno_mode_ok_for_base_p ( int regno , machine_mode mode , bool strict_p ) { if ( ! HARD_REGISTER_NUM_P ( regno ) ) { if ( ! strict_p ) return true ; regno = reg_renumber [ regno ] ; } if ( regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM ) return true ; if ( TARGET_MIPS16 && regno == STACK_POINTER_REGNUM ) return GET_MODE_SIZE ( mode ) == 4 || GET_MODE_SIZE ( mode ) == 8 ; return TARGET_MIPS16 ? M16_REG_P ( regno ) : GP_REG_P ( regno ) ; } </s>

This function is used to implement REG_MODE_OK_FOR_BASE_P .


"Interrupt handlers cannot return any value"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void function_expander :: prepare_gather_address_operands ( unsigned int argno , bool scaled_p ) { machine_mode mem_mode = memory_vector_mode ( ) ; tree vector_type = base_vector_type ( ) ; units_index units = displacement_units ( ) ; int shift_idx = - 1 ; if ( units == UNITS_none ) { args . quick_insert ( argno , const0_rtx ) ; units = UNITS_bytes ; } else if ( vector_type ) { std :: swap ( args [ argno ] , args [ argno + 1 ] ) ; if ( units == UNITS_elements ) shift_idx = argno ; } else { args [ argno ] = convert_to_pmode ( args [ argno ] ) ; vector_type = displacement_vector_type ( ) ; if ( units == UNITS_elements && ! scaled_p ) shift_idx = argno + 1 ; } tree scalar_displacement_type = TREE_TYPE ( vector_type ) ; if ( shift_idx >= 0 ) { machine_mode arg_mode = GET_MODE ( args [ shift_idx ] ) ; if ( arg_mode == VOIDmode ) arg_mode = DImode ; unsigned int elt_bytes = GET_MODE_UNIT_SIZE ( mem_mode ) ; rtx shift = gen_int_mode ( exact_log2 ( elt_bytes ) , DImode ) ; args [ shift_idx ] = simplify_gen_binary ( ASHIFT , arg_mode , args [ shift_idx ] , shift ) ; units = UNITS_bytes ; } bool uxtw_p = ( TYPE_PRECISION ( scalar_displacement_type ) == 64 || TYPE_UNSIGNED ( scalar_displacement_type ) ) ; unsigned int scale = ( units == UNITS_bytes ? 1 : GET_MODE_UNIT_SIZE ( mem_mode ) ) ; if ( scaled_p ) { args . quick_insert ( argno + 2 , GEN_INT ( uxtw_p ) ) ; args . quick_insert ( argno + 3 , GEN_INT ( scale ) ) ; } else gcc_assert ( uxtw_p && scale == 1 ) ; } </s>

Convert the arguments to a gather/scatter function into the associated md operands . Argument ARGNO is the scalar or vector base and argument ARGNO + 1 is the scalar or vector displacement ( if applicable ) . The md pattern expects : - a scalar base - a vector displacement If SCALED_P is true , it also expects : - a const_int that is 1 if the displacement is zero-extended from 32 bits - a scaling multiplier ( 1 for bytes , 2 for .h indices , etc. ) . If SCALED_P is false , the displacement is implicitly zero-extended and the scaling multiplier is implicitly 1 .


<s> DiagnosticInfoUnsupported ( const Function & Fn , const Twine & Desc , DiagnosticSeverity Severity = DS_Error ) : DiagnosticInfo ( getKindID ( ) , Severity ) , Description ( Desc ) , Fn ( Fn ) { } </s>

Fn is the function where the diagnostic is being emitted .


<s> void M68kIncomingValueHandler :: assignValueToReg ( Register ValVReg , Register PhysReg , CCValAssign VA ) { MIRBuilder . getMRI ( ) -> addLiveIn ( PhysReg ) ; MIRBuilder . getMBB ( ) . addLiveIn ( PhysReg ) ; IncomingValueHandler :: assignValueToReg ( ValVReg , PhysReg , VA ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> bool arc_eh_uses ( int regno ) { if ( regno == arc_tp_regno ) return true ; return false ; } </s>


<s> unsigned GCNSubtarget :: getOccupancyWithNumSGPRs ( unsigned SGPRs ) const { if ( getGeneration ( ) >= AMDGPUSubtarget :: GFX10 ) return getMaxWavesPerEU ( ) ; if ( getGeneration ( ) >= AMDGPUSubtarget :: VOLCANIC_ISLANDS ) { if ( SGPRs <= 80 ) return 10 ; if ( SGPRs <= 88 ) return 9 ; if ( SGPRs <= 100 ) return 8 ; return 7 ; } if ( SGPRs <= 48 ) return 10 ; if ( SGPRs <= 56 ) return 9 ; if ( SGPRs <= 64 ) return 8 ; if ( SGPRs <= 72 ) return 7 ; if ( SGPRs <= 80 ) return 6 ; return 5 ; } </s>

Return the maximum number of waves per SIMD for kernels using SGPRs SGPRs .


<s> static inline tree def_builtin2 ( HOST_WIDE_INT mask , const char * name , enum ix86_builtin_func_type tcode , enum ix86_builtins code ) { tree decl = NULL_TREE ; ix86_builtins_isa [ ( int ) code ] . isa2 = mask ; if ( mask == 0 || ( mask & ix86_isa_flags2 ) != 0 || ( lang_hooks . builtin_function == lang_hooks . builtin_function_ext_scope ) ) { tree type = ix86_get_builtin_func_type ( tcode ) ; decl = add_builtin_function ( name , type , code , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ ( int ) code ] = decl ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = false ; } else { deferred_isa_values2 |= mask ; ix86_builtins [ ( int ) code ] = NULL_TREE ; ix86_builtins_isa [ ( int ) code ] . tcode = tcode ; ix86_builtins_isa [ ( int ) code ] . name = name ; ix86_builtins_isa [ ( int ) code ] . leaf_p = false ; ix86_builtins_isa [ ( int ) code ] . nothrow_p = false ; ix86_builtins_isa [ ( int ) code ] . const_p = false ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = true ; } return decl ; } </s>

Like def_builtin , but for additional isa2 flags .


<s> SDValue X86TargetLowering :: getRecipEstimate ( SDValue Op , DAGCombinerInfo & DCI , unsigned & RefinementSteps ) const { if ( ! Subtarget -> useReciprocalEst ( ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; if ( ( Subtarget -> hasSSE1 ( ) && ( VT == MVT :: f32 || VT == MVT :: v4f32 ) ) || ( Subtarget -> hasAVX ( ) && VT == MVT :: v8f32 ) ) { RefinementSteps = ReciprocalEstimateRefinementSteps ; return DCI . DAG . getNode ( X86ISD :: FRCP , SDLoc ( Op ) , VT , Op ) ; } return SDValue ( ) ; } </s>

Return a reciprocal estimate value for the input operand .


<s> bool HexagonLoopRescheduling :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; auto & HST = MF . getSubtarget < HexagonSubtarget > ( ) ; HII = HST . getInstrInfo ( ) ; HRI = HST . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; const HexagonEvaluator HE ( * HRI , * MRI , * HII , MF ) ; BitTracker BT ( HE , MF ) ; LLVM_DEBUG ( BT . trace ( true ) ) ; BT . run ( ) ; BTP = & BT ; std :: vector < LoopCand > Cand ; for ( auto & B : MF ) { if ( B . pred_size ( ) != 2 || B . succ_size ( ) != 2 ) continue ; MachineBasicBlock * PB = nullptr ; bool IsLoop = false ; for ( MachineBasicBlock * Pred : B . predecessors ( ) ) { if ( Pred != & B ) PB = Pred ; else IsLoop = true ; } if ( ! IsLoop ) continue ; MachineBasicBlock * EB = nullptr ; for ( MachineBasicBlock * Succ : B . successors ( ) ) { if ( Succ == & B ) continue ; if ( Succ -> pred_size ( ) == 1 ) EB = Succ ; break ; } Cand . push_back ( LoopCand ( & B , PB , EB ) ) ; } bool Changed = false ; for ( auto & C : Cand ) Changed |= processLoop ( C ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool M88kPreLegalizerCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: FailedISel ) ) return false ; auto & TPC = getAnalysis < TargetPassConfig > ( ) ; GISelCSEAnalysisWrapper & Wrapper = getAnalysis < GISelCSEAnalysisWrapperPass > ( ) . getCSEWrapper ( ) ; auto * CSEInfo = & Wrapper . get ( TPC . getCSEConfig ( ) ) ; const Function & F = MF . getFunction ( ) ; bool EnableOpt = MF . getTarget ( ) . getOptLevel ( ) != CodeGenOpt :: None && ! skipFunction ( F ) ; GISelKnownBits * KB = & getAnalysis < GISelKnownBitsAnalysis > ( ) . get ( MF ) ; MachineDominatorTree * MDT = & getAnalysis < MachineDominatorTree > ( ) ; M88kPreLegalizerCombinerInfo PCInfo ( EnableOpt , F . hasOptSize ( ) , F . hasMinSize ( ) , KB , MDT ) ; Combiner C ( PCInfo , & TPC ) ; return C . combineMachineInstrs ( MF , CSEInfo ) ; } </s>