<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; Attribute SFAttr = F . getFnAttribute ( "use-soft-float" ) ; bool SoftFloat = ! SFAttr . hasAttribute ( Attribute :: None ) ? SFAttr . getValueAsString ( ) == "true" : Options . UseSoftFloat ; auto & I = SubtargetMap [ CPU + FS + ( SoftFloat ? "use-soft-float=true" : "use-soft-float=false" ) ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < X86Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> void SparcFrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const SparcInstrInfo & TII = * static_cast < const SparcInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; NumBytes += 92 ; NumBytes = ( NumBytes + 7 ) & ~ 7 ; NumBytes = - NumBytes ; if ( NumBytes >= - 4096 ) { BuildMI ( MBB , MBBI , dl , TII . get ( SP :: SAVEri ) , SP :: O6 ) . addReg ( SP :: O6 ) . addImm ( NumBytes ) ; } else { unsigned OffHi = ( unsigned ) NumBytes >> 10U ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: SETHIi ) , SP :: G1 ) . addImm ( OffHi ) ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: ORri ) , SP :: G1 ) . addReg ( SP :: G1 ) . addImm ( NumBytes & ( ( 1 << 10 ) - 1 ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: SAVErr ) , SP :: O6 ) . addReg ( SP :: O6 ) . addReg ( SP :: G1 ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> void xtensa_expand_atomic ( enum rtx_code code , rtx target , rtx mem , rtx val , bool after ) { machine_mode mode = GET_MODE ( mem ) ; struct alignment_context ac ; rtx_code_label * csloop = gen_label_rtx ( ) ; rtx cmp , tmp ; rtx old = gen_reg_rtx ( SImode ) ; rtx new_rtx = gen_reg_rtx ( SImode ) ; rtx orig = NULL_RTX ; init_alignment_context ( & ac , mem ) ; if ( ac . shift != NULL_RTX ) val = xtensa_expand_mask_and_shift ( val , mode , ac . shift ) ; switch ( code ) { case PLUS : case MINUS : orig = gen_reg_rtx ( SImode ) ; convert_move ( orig , val , 1 ) ; break ; case SET : case IOR : case XOR : break ; case MULT : case AND : val = expand_simple_binop ( SImode , XOR , val , ac . modemaski , NULL_RTX , 1 , OPTAB_DIRECT ) ; break ; default : gcc_unreachable ( ) ; } cmp = force_reg ( SImode , ac . memsi ) ; emit_label ( csloop ) ; emit_move_insn ( old , cmp ) ; switch ( code ) { case PLUS : case MINUS : val = expand_simple_binop ( SImode , code , old , orig , NULL_RTX , 1 , OPTAB_DIRECT ) ; val = expand_simple_binop ( SImode , AND , val , ac . modemask , NULL_RTX , 1 , OPTAB_DIRECT ) ; case SET : tmp = expand_simple_binop ( SImode , AND , old , ac . modemaski , NULL_RTX , 1 , OPTAB_DIRECT ) ; tmp = expand_simple_binop ( SImode , IOR , tmp , val , new_rtx , 1 , OPTAB_DIRECT ) ; break ; case AND : case IOR : case XOR : tmp = expand_simple_binop ( SImode , code , old , val , new_rtx , 1 , OPTAB_DIRECT ) ; break ; case MULT : tmp = expand_simple_binop ( SImode , XOR , old , ac . modemask , NULL_RTX , 1 , OPTAB_DIRECT ) ; tmp = expand_simple_binop ( SImode , AND , tmp , val , new_rtx , 1 , OPTAB_DIRECT ) ; break ; default : gcc_unreachable ( ) ; } if ( tmp != new_rtx ) emit_move_insn ( new_rtx , tmp ) ; emit_insn ( gen_sync_compare_and_swapsi ( cmp , ac . memsi , old , new_rtx ) ) ; emit_cmp_and_jump_insns ( cmp , old , NE , const0_rtx , SImode , true , csloop ) ; if ( target ) { tmp = ( after ? new_rtx : cmp ) ; convert_move ( target , ( ac . shift == NULL_RTX ? tmp : expand_simple_binop ( SImode , LSHIFTRT , tmp , ac . shift , NULL_RTX , 1 , OPTAB_DIRECT ) ) , 1 ) ; } } </s>

Expand an atomic operation CODE of mode MODE ( either HImode or QImode -- the default expansion works fine for SImode ) . MEM is the memory location and VAL the value to play with . If AFTER is true then store the value MEM holds after the operation , if AFTER is false then store the value MEM holds before the operation . If TARGET is zero then discard that value , else store it to TARGET .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> const char * OR1KTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return NULL ; case OR1KISD :: ADJDYNALLOC : return "OR1KISD::ADJDYNALLOC" ; case OR1KISD :: RET_FLAG : return "OR1KISD::RET_FLAG" ; case OR1KISD :: CALL : return "OR1KISD::CALL" ; case OR1KISD :: SELECT_CC : return "OR1KISD::SELECT_CC" ; case OR1KISD :: SET_FLAG : return "OR1KISD::SET_FLAG" ; case OR1KISD :: BR_CC : return "OR1KISD::BR_CC" ; case OR1KISD :: Wrapper : return "OR1KISD::Wrapper" ; case OR1KISD :: FF1 : return "OR1KISD::FF1" ; case OR1KISD :: FL1 : return "OR1KISD::FL1" ; case OR1KISD :: HI : return "OR1KISD::HI" ; case OR1KISD :: LO : return "OR1KISD::LO" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


"Callee saved registers requested for unknown architecture "


"WebAssembly hasn't implemented computed gotos"

LowerOperation - Provide custom lowering hooks for some operations .


Returns the number of bytes offset between the frame pointer and the stack pointer for the current function . SIZE is the number of bytes of space needed for local variables .


<s> static void emit_unlikely_jump ( rtx insn ) { int very_unlikely = REG_BR_PROB_BASE / 100 - 1 ; insn = emit_jump_insn ( insn ) ; add_int_reg_note ( insn , REG_BR_PROB , very_unlikely ) ; } </s>

Mark the previous jump instruction as unlikely .


<s> static void prepare_pic_move ( rtx * operands , machine_mode ) { if ( GET_CODE ( operands [ 0 ] ) == MEM && SYMBOLIC_CONST ( operands [ 1 ] ) && flag_pic ) operands [ 1 ] = force_reg ( Pmode , operands [ 1 ] ) ; else { rtx temp = ( reload_in_progress ? operands [ 0 ] : flag_pic ? gen_reg_rtx ( Pmode ) : NULL_RTX ) ; operands [ 1 ] = arc_legitimize_pic_address ( operands [ 1 ] , temp ) ; } } </s>

Emit insns to move operands [ 1 ] into operands [ 0 ] .


"There are no defined alternate asm variants"

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> void AArch64PassConfig :: addPreEmitPass ( ) { if ( EnableA53Fix835769 ) addPass ( createAArch64A53Fix835769 ( ) ) ; if ( BranchRelaxation ) addPass ( & BranchRelaxationPassID ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


Print a memory address as an operand to reference that memory location .


<s>
bool
Mips16HardFloat
::
runOnModule
(
Module
&
M
)
{
DEBUG
(
errs
(
)
<<
"Run on Module Mips16HardFloat\n"
)
;
bool
Modified
=
false
;
for
(
Module
::
iterator
F
=
M
.
begin
(
)
,
E
=
M
.
end
(
)
;
F
!=
E
;
++
F
)
{
if
(
F
->
hasFnAttribute
(
"nomips16"
)
&&
F
->
hasFnAttribute
(
"use-soft-float"
)
)
{
removeUseSoftFloat
(
*
F
)
;
continue
;
}
if
(
F
->
isDeclaration
(
)
||
F
->
hasFnAttribute
(
"mips16_fp_stub"
)
||
F
->
hasFnAttribute
(
"nomips16"
)
)
continue
;
Modified
|=
fixupFPReturnAndCall
(
*
F
,
&
M
,
TM
)
;
FPParamVariant
V
=
whichFPParamVariantNeeded
(
*
F
)
;
if
(
V
!=
NoSig
)
{
Modified
=
true
;
createFPFnStub
(
&
*
F
,
&
M
,
V
,
TM
)
;
}
}
return
Modified
;
}
</s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> bool X86PassConfig :: addPreEmitPass ( ) { bool ShouldPrint = false ; if ( getOptLevel ( ) != CodeGenOpt :: None && getX86Subtarget ( ) . hasSSE2 ( ) ) { addPass ( createExecutionDependencyFixPass ( & X86 :: VR128RegClass ) ) ; ShouldPrint = true ; } if ( getX86Subtarget ( ) . hasAVX ( ) && UseVZeroUpper ) { addPass ( createX86IssueVZeroUpperPass ( ) ) ; ShouldPrint = true ; } if ( getOptLevel ( ) != CodeGenOpt :: None && getX86Subtarget ( ) . padShortFunctions ( ) ) { addPass ( createX86PadShortFunctions ( ) ) ; ShouldPrint = true ; } if ( getOptLevel ( ) != CodeGenOpt :: None && getX86Subtarget ( ) . LEAusesAG ( ) ) { addPass ( createX86FixupLEAs ( ) ) ; ShouldPrint = true ; } if ( getX86Subtarget ( ) . isTargetNaCl ( ) ) { addPass ( createX86NaClRewritePass ( ) ) ; ShouldPrint = true ; } return ShouldPrint ; } </s>


<s> bool runOnFunction ( Function & F ) override { this -> F = & F ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; TTI = & getAnalysis < TargetTransformInfoWrapperPass > ( ) . getTTI ( F ) ; bool Changed = false ; for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L = po_begin ( * I ) , LE = po_end ( * I ) ; L != LE ; ++ L ) Changed |= runOnLoop ( * L ) ; VisitedBlocks . clear ( ) ; return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool HSAILDAGToDAGISel :: IsProfitableToFold ( SDValue N , SDNode * U , SDNode * Root ) const { return true ; } </s>

IsProfitableToFold - Returns true if it 's profitable to fold the specific operand node N of U during instruction selection that starts at Root .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS ) , JITInfo ( ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = FloatABI :: Soft ; } </s>


<s>
unsigned
AArch64TargetLowering
::
getRegisterByName
(
const
char
*
RegName
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"sp"
,
AArch64
::
XSP
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> TargetPassConfig * TVMTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new TVMPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s>
unsigned
J2MCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
if
(
MO
.
isImm
(
)
)
<
unsigned
>
(
MO
.
getImm
(
)
)
;
assert
(
MO
.
isExpr
(
)
&&
MO
.
getExpr
(
)
->
getKind
(
)
==
MCExpr
::
SymbolRef
)
;
J2
::
Fixups
FixupKind
=
J2
::
fixup_J2_NONE
;
switch
(
MI
.
getOpcode
(
)
)
{
case
J2
::
BSR
:
case
J2
::
BRA
:
FixupKind
=
J2
::
fixup_J2_PC2_12
;
break
;
case
J2
::
BT
:
FixupKind
=
J2
::
fixup_J2_PC2_8
;
break
;
case
J2
::
MOV32PCR
:
FixupKind
=
J2
::
fixup_J2_PC4_8
;
break
;
default
:
llvm_unreachable
(
"Opcode not handled."
)
;
}
Fixups
.
push_back
(
MCFixup
::
create
(
0
,
MO
.
getExpr
(
)
,
MCFixupKind
(
FixupKind
)
,
MI
.
getLoc
(
)
)
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> static machine_mode rs6000_preferred_simd_mode ( scalar_mode mode ) { opt_machine_mode vmode = mode_for_vector ( mode , 16 / GET_MODE_SIZE ( mode ) ) ; if ( vmode . exists ( ) && ! VECTOR_MEM_NONE_P ( vmode . require ( ) ) ) return vmode . require ( ) ; return word_mode ; } </s>


<s> bool sh_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( SPECIAL_REGISTER_P ( regno ) ) return mode == SImode ; if ( regno == FPUL_REG ) return ( mode == SImode || mode == SFmode ) ; if ( FP_REGISTER_P ( regno ) && mode == SFmode ) return true ; if ( mode == V2SFmode ) { if ( ( ( FP_REGISTER_P ( regno ) && ( regno - FIRST_FP_REG ) % 2 == 0 ) || GENERAL_REGISTER_P ( regno ) ) ) return true ; else return false ; } if ( mode == V4SFmode ) { if ( ( FP_REGISTER_P ( regno ) && ( regno - FIRST_FP_REG ) % 4 == 0 ) || GENERAL_REGISTER_P ( regno ) ) return true ; else return false ; } if ( mode == V16SFmode ) return regno == FIRST_XD_REG ; if ( FP_REGISTER_P ( regno ) ) { if ( mode == SFmode || mode == SImode || ( ( TARGET_SH2E ) && mode == SCmode ) || ( ( ( TARGET_FPU_DOUBLE && mode == DFmode ) || mode == DCmode ) && ( ( regno - FIRST_FP_REG ) & 1 ) == 0 ) || ( TARGET_SH4 && mode == TImode && ( ( regno - FIRST_FP_REG ) & 3 ) == 0 ) ) return true ; else return false ; } if ( XD_REGISTER_P ( regno ) ) return mode == DFmode ; if ( regno == PR_REG ) return mode == SImode ; if ( regno == FPSCR_REG ) return mode == SImode ; return true ; } </s>

Return true if hard register REGNO can hold a value of machine-mode MODE . We can allow any mode in any general register . The special registers only allow SImode . Do n't allow any mode in the PR . We can not hold DCmode values in the XD registers because alter_reg handles subregs of them incorrectly . We could work around this by spacing the XD registers like the DR registers , but this would require additional memory in every compilation to hold larger register vectors . We could hold SFmode / SCmode values in XD registers , but that would require a tertiary reload when reloading from / to memory , and a secondary reload to reload from / to general regs ; that seems to be a losing proposition . We want to allow TImode FP regs so that when V4SFmode is loaded as TImode , it wo n't be ferried through GP registers first .


<s> static SDValue getSplatValue ( SDNode * N ) { if ( auto * BuildVec = dyn_cast < BuildVectorSDNode > ( N ) ) { return BuildVec -> getSplatValue ( ) ; } return SDValue ( ) ; } </s>

If V is a splat vector , return its scalar source operand by extracting that element from the source vector .


<s> const uint32_t * SystemZRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { if ( MF . getSubtarget ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_SystemZ_SwiftError_RegMask ; return CSR_SystemZ_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static void emit_soft_tfmode_libcall ( const char * func_name , int nargs , rtx * operands ) { rtx ret_slot = NULL , arg [ 3 ] , func_sym ; int i ; gcc_assert ( nargs == 2 || nargs == 3 ) ; for ( i = 0 ; i < nargs ; ++ i ) { rtx this_arg = operands [ i ] ; rtx this_slot ; if ( GET_MODE ( this_arg ) == TFmode ) { int force_stack_temp ; force_stack_temp = 0 ; if ( TARGET_BUGGY_QP_LIB && i == 0 ) force_stack_temp = 1 ; if ( GET_CODE ( this_arg ) == MEM && ! force_stack_temp ) { tree expr = MEM_EXPR ( this_arg ) ; if ( expr ) mark_addressable ( expr ) ; this_arg = XEXP ( this_arg , 0 ) ; } else if ( CONSTANT_P ( this_arg ) && ! force_stack_temp ) { this_slot = force_const_mem ( TFmode , this_arg ) ; this_arg = XEXP ( this_slot , 0 ) ; } else { this_slot = assign_stack_temp ( TFmode , GET_MODE_SIZE ( TFmode ) ) ; if ( i > 0 ) emit_move_insn ( this_slot , this_arg ) ; else ret_slot = this_slot ; this_arg = XEXP ( this_slot , 0 ) ; } } arg [ i ] = this_arg ; } func_sym = gen_rtx_SYMBOL_REF ( Pmode , func_name ) ; if ( GET_MODE ( operands [ 0 ] ) == TFmode ) { if ( nargs == 2 ) emit_library_call ( func_sym , LCT_NORMAL , VOIDmode , 2 , arg [ 0 ] , GET_MODE ( arg [ 0 ] ) , arg [ 1 ] , GET_MODE ( arg [ 1 ] ) ) ; else emit_library_call ( func_sym , LCT_NORMAL , VOIDmode , 3 , arg [ 0 ] , GET_MODE ( arg [ 0 ] ) , arg [ 1 ] , GET_MODE ( arg [ 1 ] ) , arg [ 2 ] , GET_MODE ( arg [ 2 ] ) ) ; if ( ret_slot ) emit_move_insn ( operands [ 0 ] , ret_slot ) ; } else { rtx ret ; gcc_assert ( nargs == 2 ) ; ret = emit_library_call_value ( func_sym , operands [ 0 ] , LCT_NORMAL , GET_MODE ( operands [ 0 ] ) , 1 , arg [ 1 ] , GET_MODE ( arg [ 1 ] ) ) ; if ( ret != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , ret ) ; } } </s>

Generate a call to FUNC with OPERANDS . Operand 0 is the return value . Unlike normal calls , TFmode operands are passed by reference . It is assumed that no more than 3 operands are required .


"Peephole: call to builtin function with "

runOnMachineFunction - Emit the function body .


<s> bool AArch64InstrInfo :: isThroughputPattern ( MachineCombinerPattern Pattern ) const { switch ( Pattern ) { default : break ; case MachineCombinerPattern :: FMULADDH_OP1 : case MachineCombinerPattern :: FMULADDH_OP2 : case MachineCombinerPattern :: FMULSUBH_OP1 : case MachineCombinerPattern :: FMULSUBH_OP2 : case MachineCombinerPattern :: FMULADDS_OP1 : case MachineCombinerPattern :: FMULADDS_OP2 : case MachineCombinerPattern :: FMULSUBS_OP1 : case MachineCombinerPattern :: FMULSUBS_OP2 : case MachineCombinerPattern :: FMULADDD_OP1 : case MachineCombinerPattern :: FMULADDD_OP2 : case MachineCombinerPattern :: FMULSUBD_OP1 : case MachineCombinerPattern :: FMULSUBD_OP2 : case MachineCombinerPattern :: FNMULSUBH_OP1 : case MachineCombinerPattern :: FNMULSUBS_OP1 : case MachineCombinerPattern :: FNMULSUBD_OP1 : case MachineCombinerPattern :: FMLAv4i16_indexed_OP1 : case MachineCombinerPattern :: FMLAv4i16_indexed_OP2 : case MachineCombinerPattern :: FMLAv8i16_indexed_OP1 : case MachineCombinerPattern :: FMLAv8i16_indexed_OP2 : case MachineCombinerPattern :: FMLAv1i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv1i32_indexed_OP2 : case MachineCombinerPattern :: FMLAv1i64_indexed_OP1 : case MachineCombinerPattern :: FMLAv1i64_indexed_OP2 : case MachineCombinerPattern :: FMLAv4f16_OP2 : case MachineCombinerPattern :: FMLAv4f16_OP1 : case MachineCombinerPattern :: FMLAv8f16_OP1 : case MachineCombinerPattern :: FMLAv8f16_OP2 : case MachineCombinerPattern :: FMLAv2f32_OP2 : case MachineCombinerPattern :: FMLAv2f32_OP1 : case MachineCombinerPattern :: FMLAv2f64_OP1 : case MachineCombinerPattern :: FMLAv2f64_OP2 : case MachineCombinerPattern :: FMLAv2i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv2i32_indexed_OP2 : case MachineCombinerPattern :: FMLAv2i64_indexed_OP1 : case MachineCombinerPattern :: FMLAv2i64_indexed_OP2 : case MachineCombinerPattern :: FMLAv4f32_OP1 : case MachineCombinerPattern :: FMLAv4f32_OP2 : case MachineCombinerPattern :: FMLAv4i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv4i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv4i16_indexed_OP1 : case MachineCombinerPattern :: FMLSv4i16_indexed_OP2 : case MachineCombinerPattern :: FMLSv8i16_indexed_OP1 : case MachineCombinerPattern :: FMLSv8i16_indexed_OP2 : case MachineCombinerPattern :: FMLSv1i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv1i64_indexed_OP2 : case MachineCombinerPattern :: FMLSv2i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv2i64_indexed_OP2 : case MachineCombinerPattern :: FMLSv4f16_OP1 : case MachineCombinerPattern :: FMLSv4f16_OP2 : case MachineCombinerPattern :: FMLSv8f16_OP1 : case MachineCombinerPattern :: FMLSv8f16_OP2 : case MachineCombinerPattern :: FMLSv2f32_OP2 : case MachineCombinerPattern :: FMLSv2f64_OP2 : case MachineCombinerPattern :: FMLSv4i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv4f32_OP2 : return true ; } return false ; } </s>

Return true when a code sequence can improve throughput .


<s> bool MipsCallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < Register > VRegs ) const { MachineInstrBuilder Ret = MIRBuilder . buildInstrNoInsert ( Mips :: RetRA ) ; if ( Val != nullptr && ! isSupportedReturnType ( Val -> getType ( ) ) ) return false ; if ( ! VRegs . empty ( ) ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const MipsTargetLowering & TLI = * getTLI < MipsTargetLowering > ( ) ; SmallVector < ArgInfo , 8 > RetInfos ; SmallVector < unsigned , 8 > OrigArgIndices ; ArgInfo ArgRetInfo ( VRegs , Val -> getType ( ) ) ; setArgFlags ( ArgRetInfo , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( DL , ArgRetInfo , 0 , RetInfos , OrigArgIndices ) ; SmallVector < ISD :: OutputArg , 8 > Outs ; subTargetRegTypeForCallingConv ( F , RetInfos , OrigArgIndices , Outs ) ; SmallVector < CCValAssign , 16 > ArgLocs ; MipsCCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , TLI . CCAssignFnForReturn ( ) ) ; setLocInfo ( ArgLocs , Outs ) ; MipsOutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , Ret ) ; if ( ! RetHandler . handle ( ArgLocs , RetInfos ) ) { return false ; } } MIRBuilder . insertInstr ( Ret ) ; return true ; } </s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s>
const
char
*
nvptx_output_return
(
void
)
{
machine_mode
mode
=
(
machine_mode
)
cfun
->
machine
->
return_mode
;
if
(
mode
!=
VOIDmode
)
fprintf
(
asm_out_file
,
"\tst.param%s\t[%s_out], %s;\n"
,
nvptx_ptx_type_from_mode
(
mode
,
false
)
,
reg_names
[
NVPTX_RETURN_REGNUM
]
,
reg_names
[
NVPTX_RETURN_REGNUM
]
)
;
return
"ret;"
;
}
</s>

Output a return instruction . Also copy the return value to its outgoing location .

nvptx
"\tst.param%s\t[%s_out], %s;\n"
"ret;"


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return CSR_Ghc_RegMask ; if ( ! Is64Bit ) return CSR_32_RegMask ; if ( IsWin64 ) return CSR_Win64_RegMask ; return CSR_64_RegMask ; } </s>


"Object file emission is not supported with PTX"

Add passes to the specified pass manager to get the specified file emitted .


<s> const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> rtx tilegx_eh_return_handler_rtx ( void ) { rtx tmp = gen_frame_mem ( Pmode , hard_frame_pointer_rtx ) ; MEM_VOLATILE_P ( tmp ) = true ; return tmp ; } </s>

Implement EH_RETURN_HANDLER_RTX . The MEM needs to be volatile to prevent it from being deleted .


<s> bool R600MachineCFGStructurizer :: prepare ( ) { bool Changed = false ; LLVM_DEBUG ( dbgs ( ) << "R600MachineCFGStructurizer::prepare\n" ; ) ; orderBlocks ( FuncRep ) ; SmallVector < MachineBasicBlock * , DEFAULT_VEC_SLOTS > RetBlks ; for ( MachineLoop * LoopRep : * MLI ) { MBBVector ExitingMBBs ; LoopRep -> getExitingBlocks ( ExitingMBBs ) ; if ( ExitingMBBs . size ( ) == 0 ) { MachineBasicBlock * DummyExitBlk = normalizeInfiniteLoopExit ( LoopRep ) ; if ( DummyExitBlk ) RetBlks . push_back ( DummyExitBlk ) ; } } for ( MachineBasicBlock * MBB : OrderedBlks ) { removeUnconditionalBranch ( MBB ) ; removeRedundantConditionalBranch ( MBB ) ; if ( isReturnBlock ( MBB ) ) { RetBlks . push_back ( MBB ) ; } assert ( MBB -> succ_size ( ) <= 2 ) ; } if ( RetBlks . size ( ) >= 2 ) { addDummyExitBlock ( RetBlks ) ; Changed = true ; } return Changed ; } </s>

prepare - Reset state and prepare for a new spill placement computation .


<s> const TargetRegisterClass * X86RegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { if ( RC == & X86 :: GR8_NOREXRegClass ) return RC ; const TargetRegisterClass * Super = RC ; TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case X86 :: GR8RegClassID : case X86 :: GR16RegClassID : case X86 :: GR32RegClassID : case X86 :: GR64RegClassID : case X86 :: FR32RegClassID : case X86 :: FR64RegClassID : case X86 :: RFP32RegClassID : case X86 :: RFP64RegClassID : case X86 :: RFP80RegClassID : case X86 :: VR128RegClassID : case X86 :: VR256RegClassID : if ( Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; } Super = * I ++ ; } while ( Super ) ; return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .


<s>
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
MipsTargetLowering
::
getRegForInlineAsmConstraint
(
const
std
::
string
&
Constraint
,
EVT
VT
)
const
{
if
(
Constraint
.
size
(
)
==
1
)
{
switch
(
Constraint
[
0
]
)
{
case
'd'
:
case
'y'
:
case
'r'
:
if
(
VT
==
MVT
::
i32
||
VT
==
MVT
::
i16
||
VT
==
MVT
::
i8
)
{
if
(
Subtarget
->
inMips16Mode
(
)
)
return
std
::
make_pair
(
0U
,
&
Mips
::
CPU16RegsRegClass
)
;
return
std
::
make_pair
(
0U
,
&
Mips
::
CPURegsRegClass
)
;
}
if
(
VT
==
MVT
::
i64
&&
!
HasMips64
)
return
std
::
make_pair
(
0U
,
&
Mips
::
CPURegsRegClass
)
;
if
(
VT
==
MVT
::
i64
&&
HasMips64
)
return
std
::
make_pair
(
0U
,
&
Mips
::
CPU64RegsRegClass
)
;
return
std
::
make_pair
(
0u
,
static_cast
<
const
TargetRegisterClass
*
>
(
0
)
)
;
case
'f'
:
if
(
VT
==
MVT
::
f32
)
return
std
::
make_pair
(
0U
,
&
Mips
::
FGR32RegClass
)
;
if
(
(
VT
==
MVT
::
f64
)
&&
(
!
Subtarget
->
isSingleFloat
(
)
)
)
{
if
(
Subtarget
->
isFP64bit
(
)
)
return
std
::
make_pair
(
0U
,
&
Mips
::
FGR64RegClass
)
;
return
std
::
make_pair
(
0U
,
&
Mips
::
AFGR64RegClass
)
;
}
break
;
case
'c'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
(
unsigned
)
Mips
::
T9
,
&
Mips
::
CPURegsRegClass
)
;
assert
(
VT
==
MVT
::
i64
&&
"Unexpected type."
)
;
return
std
::
make_pair
(
(
unsigned
)
Mips
::
T9_64
,
&
Mips
::
CPU64RegsRegClass
)
;
case
'l'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
(
unsigned
)
Mips
::
LO
,
&
Mips
::
LORegsRegClass
)
;
return
std
::
make_pair
(
(
unsigned
)
Mips
::
LO64
,
&
Mips
::
LORegs64RegClass
)
;
case
'x'
:
return
std
::
make_pair
(
0u
,
static_cast
<
const
TargetRegisterClass
*
>
(
0
)
)
;
}
}
return
TargetLowering
::
getRegForInlineAsmConstraint
(
Constraint
,
VT
)
;
}
</s>

Given a physical register constraint ( e.g .


<s> int arm_no_early_mul_dep ( rtx producer , rtx consumer ) { rtx value = PATTERN ( producer ) ; rtx op = PATTERN ( consumer ) ; if ( GET_CODE ( value ) == COND_EXEC ) value = COND_EXEC_CODE ( value ) ; if ( GET_CODE ( value ) == PARALLEL ) value = XVECEXP ( value , 0 , 0 ) ; value = XEXP ( value , 0 ) ; if ( GET_CODE ( op ) == COND_EXEC ) op = COND_EXEC_CODE ( op ) ; if ( GET_CODE ( op ) == PARALLEL ) op = XVECEXP ( op , 0 , 0 ) ; op = XEXP ( op , 1 ) ; return ( GET_CODE ( op ) == PLUS && ! reg_overlap_mentioned_p ( value , XEXP ( op , 0 ) ) ) ; } </s>

Return nonzero if the CONSUMER ( a mul or mac op ) does not have an early register mult dependency on the result of PRODUCER .


<s> static rtx lxvrse_expand_builtin ( rtx target , insn_code icode , rtx * op , machine_mode tmode , machine_mode smode ) { rtx pat , addr ; op [ 1 ] = copy_to_mode_reg ( Pmode , op [ 1 ] ) ; if ( op [ 0 ] == const0_rtx ) addr = gen_rtx_MEM ( tmode , op [ 1 ] ) ; else { op [ 0 ] = copy_to_mode_reg ( Pmode , op [ 0 ] ) ; addr = gen_rtx_MEM ( smode , gen_rtx_PLUS ( Pmode , op [ 1 ] , op [ 0 ] ) ) ; } rtx discratch = gen_reg_rtx ( V2DImode ) ; rtx tiscratch = gen_reg_rtx ( TImode ) ; pat = GEN_FCN ( icode ) ( tiscratch , addr ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; rtx temp1 ; if ( icode == CODE_FOR_vsx_lxvrbx ) { temp1 = simplify_gen_subreg ( V16QImode , tiscratch , TImode , 0 ) ; emit_insn ( gen_vsx_sign_extend_v16qi_v2di ( discratch , temp1 ) ) ; } else if ( icode == CODE_FOR_vsx_lxvrhx ) { temp1 = simplify_gen_subreg ( V8HImode , tiscratch , TImode , 0 ) ; emit_insn ( gen_vsx_sign_extend_v8hi_v2di ( discratch , temp1 ) ) ; } else if ( icode == CODE_FOR_vsx_lxvrwx ) { temp1 = simplify_gen_subreg ( V4SImode , tiscratch , TImode , 0 ) ; emit_insn ( gen_vsx_sign_extend_v4si_v2di ( discratch , temp1 ) ) ; } else if ( icode == CODE_FOR_vsx_lxvrdx ) discratch = simplify_gen_subreg ( V2DImode , tiscratch , TImode , 0 ) ; else gcc_unreachable ( ) ; rtx temp2 = simplify_gen_subreg ( TImode , discratch , V2DImode , 0 ) ; emit_insn ( gen_extendditi2_vector ( target , temp2 ) ) ; return target ; } </s>

Expand a builtin function that loads a scalar into a vector register with sign extension , and return the expanded rtx .


<s> unsigned getNumFixupKinds ( ) const override { return 0 ; } </s>

Get the number of target specific fixup kinds .


<s> static void replace_ltrel_base ( rtx * x ) { int i , j ; const char * fmt ; if ( GET_CODE ( * x ) == UNSPEC && XINT ( * x , 1 ) == UNSPEC_LTREL_BASE ) { * x = XVECEXP ( * x , 0 , 1 ) ; return ; } fmt = GET_RTX_FORMAT ( GET_CODE ( * x ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( * x ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'e' ) { replace_ltrel_base ( & XEXP ( * x , i ) ) ; } else if ( fmt [ i ] == 'E' ) { for ( j = 0 ; j < XVECLEN ( * x , i ) ; j ++ ) replace_ltrel_base ( & XVECEXP ( * x , i , j ) ) ; } } } </s>

Replace any occurrence of UNSPEC_LTREL_BASE in X with its base .


<s> bool PPCInstrInfo :: findCommutedOpIndices ( MachineInstr * MI , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { int AltOpc = PPC :: getAltVSXFMAOpcode ( MI -> getOpcode ( ) ) ; if ( AltOpc == - 1 ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; SrcOpIdx1 = 2 ; SrcOpIdx2 = 3 ; return true ; } </s>

Returns true iff the routine could find two commutable operands in the given machine instruction .


<s> MachineBasicBlock :: iterator M88kFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static void rws_update ( int regno , struct reg_flags flags , int pred ) { if ( pred ) rws_sum [ regno ] . write_count ++ ; else rws_sum [ regno ] . write_count = 2 ; rws_sum [ regno ] . written_by_fp |= flags . is_fp ; rws_sum [ regno ] . written_by_and = flags . is_and ; rws_sum [ regno ] . written_by_or = flags . is_or ; rws_sum [ regno ] . first_pred = pred ; } </s>

Update * RWS for REGNO , which is being written by the current instruction , with predicate PRED , and associated register flags in FLAGS .


<s>
bool
PPCAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
{
if
(
ExtraCode
[
1
]
!=
0
)
return
true
;
switch
(
ExtraCode
[
0
]
)
{
default
:
return
true
;
case
'y'
:
{
O
<<
"0, "
;
printOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
}
case
'U'
:
case
'X'
:
{
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
return
false
;
}
}
}
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
O
<<
"0("
;
printOperand
(
MI
,
OpNo
,
O
)
;
O
<<
")"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> static int thumb2_legitimate_index_p ( machine_mode mode , rtx index , int strict_p ) { enum rtx_code code = GET_CODE ( index ) ; if ( TARGET_HARD_FLOAT && TARGET_VFP && ( mode == SFmode || mode == DFmode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 256 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE ( mode ) ) { if ( ! TARGET_LDRD || mode != DImode ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; } if ( TARGET_NEON && VALID_NEON_QREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1016 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( TARGET_NEON && VALID_NEON_DREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( arm_address_register_rtx_p ( index , strict_p ) && ( GET_MODE_SIZE ( mode ) <= 4 ) ) return 1 ; if ( mode == DImode || mode == DFmode ) { if ( code == CONST_INT ) { HOST_WIDE_INT val = INTVAL ( index ) ; return val > - 256 && val < 256 && ( val & 3 ) == 0 ; } else return 0 ; } if ( code == MULT ) { rtx xiop0 = XEXP ( index , 0 ) ; rtx xiop1 = XEXP ( index , 1 ) ; return ( ( arm_address_register_rtx_p ( xiop0 , strict_p ) && thumb2_index_mul_operand ( xiop1 ) ) || ( arm_address_register_rtx_p ( xiop1 , strict_p ) && thumb2_index_mul_operand ( xiop0 ) ) ) ; } else if ( code == ASHIFT ) { rtx op = XEXP ( index , 1 ) ; return ( arm_address_register_rtx_p ( XEXP ( index , 0 ) , strict_p ) && CONST_INT_P ( op ) && INTVAL ( op ) > 0 && INTVAL ( op ) <= 3 ) ; } return ( code == CONST_INT && INTVAL ( index ) < 4096 && INTVAL ( index ) > - 256 ) ; } </s>

Return nonzero if INDEX is a valid Thumb-2 address index operand .


<s> unsigned getStackAlignment ( ) const { return stackAlignment ; } </s>

Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget .


<s> void ARMPassConfig :: addPreEmitPass ( ) { addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( createUnpackMachineBundles ( [ ] ( const MachineFunction & MF ) { return MF . getSubtarget < ARMSubtarget > ( ) . isThumb2 ( ) ; } ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createARMOptimizeBarriersPass ( ) ) ; addPass ( createARMConstantIslandPass ( ) ) ; addPass ( createARMLowOverheadLoopsPass ( ) ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardLongjmpPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static enum tls_model tls_symbolic_operand_type ( rtx addr ) { enum tls_model tls_kind = TLS_MODEL_NONE ; if ( GET_CODE ( addr ) == CONST ) { if ( GET_CODE ( XEXP ( addr , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) == SYMBOL_REF ) tls_kind = SYMBOL_REF_TLS_MODEL ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) ; } else if ( GET_CODE ( addr ) == SYMBOL_REF ) tls_kind = SYMBOL_REF_TLS_MODEL ( addr ) ; return tls_kind ; } </s>

Return the TLS model to use for SYMBOL .


<s> BitVector MSP430RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( MSP430 :: PCW ) ; Reserved . set ( MSP430 :: SPW ) ; Reserved . set ( MSP430 :: SRW ) ; Reserved . set ( MSP430 :: CGW ) ; if ( hasFP ( MF ) ) Reserved . set ( MSP430 :: FPW ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static void xputenv ( const char * string ) { if ( verbose ) fprintf ( stderr , "%s\n" , string ) ; putenv ( CONST_CAST ( char * , string ) ) ; } </s>

Add or change the value of an environment variable , outputting the change to standard error if in verbose mode .


<s> void PPCOperand :: print ( raw_ostream & OS ) const { switch ( Kind ) { case Token : OS << "'" << getToken ( ) << "'" ; break ; case Immediate : case ContextImmediate : OS << getImm ( ) ; break ; case Expression : getExpr ( ) -> print ( OS ) ; break ; case TLSRegister : getTLSReg ( ) -> print ( OS ) ; break ; } } </s>

print - Print a debug representation of the operand to the given stream .


<s> int num_insns_constant_wide ( HOST_WIDE_INT value ) { if ( CONST_OK_FOR_LETTER_P ( value , 'I' ) ) return 1 ; else if ( CONST_OK_FOR_LETTER_P ( value , 'L' ) ) return 1 ; else if ( TARGET_POWERPC64 ) { HOST_WIDE_INT low = ( ( value & 0xffffffff ) ^ 0x80000000 ) - 0x80000000 ; HOST_WIDE_INT high = value >> 31 ; if ( high == 0 || high == - 1 ) return 2 ; high >>= 1 ; if ( low == 0 ) return num_insns_constant_wide ( high ) + 1 ; else return ( num_insns_constant_wide ( high ) + num_insns_constant_wide ( low ) + 1 ) ; } else return 2 ; } </s>

Return the number of instructions it takes to form a constant in an integer register .


<s> bool X86AsmParser :: OmitRegisterFromClobberLists ( unsigned RegNo ) { return X86MCRegisterClasses [ X86 :: SEGMENT_REGRegClassID ] . contains ( RegNo ) ; } </s>

Allows targets to let registers opt out of clobber lists .


<s>
void
moxie_print_operand
(
FILE
*
file
,
rtx
x
,
int
code
)
{
rtx
operand
=
x
;
switch
(
code
)
{
case
0
:
break
;
default
:
LOSE_AND_RETURN
(
"invalid operand modifier letter"
,
x
)
;
}
switch
(
GET_CODE
(
operand
)
)
{
case
REG
:
if
(
REGNO
(
operand
)
>
MOXIE_R13
)
internal_error
(
"internal error: bad register: %d"
,
REGNO
(
operand
)
)
;
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
operand
)
]
)
;
return
;
case
MEM
:
output_address
(
XEXP
(
operand
,
0
)
)
;
return
;
default
:
if
(
CONSTANT_P
(
operand
)
)
{
output_addr_const
(
file
,
operand
)
;
return
;
}
LOSE_AND_RETURN
(
"unexpected operand"
,
x
)
;
}
}
</s>

moxie
0
"invalid operand modifier letter"
"internal error: bad register: %d"
"%s"
0
"unexpected operand"


<s> bool AGCAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { if ( Count % 2 != 0 ) return false ; uint64_t NopCount = Count / 2 ; for ( uint64_t i = 0 ; i < NopCount ; i ++ ) AGCMCCodeEmitter :: emitBitsWithParity ( OS , 0x3000 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> bool MipsMulMulBugFix :: runOnMachineFunction ( MachineFunction & MF ) { const MipsInstrInfo & MipsII = * static_cast < const MipsInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; bool Modified = false ; for ( auto & MBB : MF ) Modified |= fixMulMulBB ( MBB , MipsII ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


"convert address space of alloca'ed memory to local"

getPassName - Return a nice clean name for a pass .


" Instructions Emitted in this clause\n"

ScheduleDAGMI has scheduled an instruction - tell HazardRec about it .


<s> bool X86FastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { const Value * Ptr = LI -> getPointerOperand ( ) ; X86AddressMode AM ; if ( ! X86SelectAddress ( Ptr , AM ) ) return false ; const X86InstrInfo & XII = ( const X86InstrInfo & ) TII ; unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; unsigned Alignment = LI -> getAlignment ( ) ; if ( Alignment == 0 ) Alignment = DL . getABITypeAlignment ( LI -> getType ( ) ) ; SmallVector < MachineOperand , 8 > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , MI , OpNo , AddrOps , Size , Alignment , true ) ; if ( ! Result ) return false ; unsigned OperandNo = 0 ; for ( MachineInstr :: mop_iterator I = Result -> operands_begin ( ) , E = Result -> operands_end ( ) ; I != E ; ++ I , ++ OperandNo ) { MachineOperand & MO = * I ; if ( ! MO . isReg ( ) || MO . isDef ( ) || MO . getReg ( ) != AM . IndexReg ) continue ; unsigned IndexReg = constrainOperandRegClass ( Result -> getDesc ( ) , MO . getReg ( ) , OperandNo ) ; if ( IndexReg == MO . getReg ( ) ) continue ; MO . setReg ( IndexReg ) ; } Result -> addMemOperand ( * FuncInfo . MF , createMachineMemOperandFor ( LI ) ) ; FuncInfo . MBB -> insert ( FuncInfo . InsertPt , Result ) ; MI -> eraseFromParent ( ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> static int reg_push_size ( int regno ) { switch ( regno ) { case R0_REGNO : case R1_REGNO : return 2 ; case R2_REGNO : case R3_REGNO : case FLG_REGNO : return 2 ; case A0_REGNO : case A1_REGNO : case SB_REGNO : case FB_REGNO : case SP_REGNO : if ( TARGET_A16 ) return 2 ; else return 3 ; default : gcc_unreachable ( ) ; } } </s>

How many bytes a register uses on stack when it 's pushed . We need to know this because the push opcode needs to explicitly indicate the size of the register , even though the name of the register already tells it that . Used by m32c_output_reg_ { push , pop } , which is only used through calls to ASM_OUTPUT_REG_ { PUSH , POP } .


<s> bool BlackfinAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'r' : break ; } } printOperand ( MI , OpNo ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> void M68kOperand :: addExpr ( MCInst & Inst , const MCExpr * Expr ) { if ( auto Const = dyn_cast < MCConstantExpr > ( Expr ) ) { Inst . addOperand ( MCOperand :: createImm ( Const -> getValue ( ) ) ) ; return ; } Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"Hexagon Split Double Registers"
;
}
</s>

Hexagon
"Hexagon Split Double Registers"


<s> void PPCFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - 1 ; bool DisableRedZone = MF . getFunction ( ) -> hasFnAttr ( Attribute :: NoRedZone ) ; if ( ! DisableRedZone && FrameSize <= 224 && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ( ! ALIGN_STACK || MaxAlign <= TargetAlign ) ) { MFI -> setStackSize ( 0 ) ; return ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getMinCallFrameSize ( Subtarget . isPPC64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; MFI -> setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s> bool isTargetEHABICompatible ( ) const { return TargetTriple . isTargetEHABICompatible ( ) ; } </s>

Tests whether the target supports the EHABI exception handling standard .


<s> static int bfin_address_cost ( rtx addr ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , addr_space_t as ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { return 1 ; } </s>

Return cost of the memory address ADDR . All addressing modes are equally cheap on the Blackfin .


<s> static reg_class_t aarch64_ira_change_pseudo_allocno_class ( int regno , reg_class_t allocno_class , reg_class_t best_class ) { machine_mode mode ; if ( allocno_class != ALL_REGS ) return allocno_class ; if ( best_class != ALL_REGS ) return best_class ; mode = PSEUDO_REGNO_MODE ( regno ) ; return FLOAT_MODE_P ( mode ) || VECTOR_MODE_P ( mode ) ? FP_REGS : GENERAL_REGS ; } </s>

Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS . The register allocator chooses ALL_REGS if FP_REGS and GENERAL_REGS have the same cost even if ALL_REGS has a much larger cost . ALL_REGS is also used if the cost of both FP_REGS and GENERAL_REGS is lower than the memory cost ( in this case the best class is the lowest cost one ) . Using ALL_REGS irrespectively of its cost results in bad allocations with many redundant int < - > FP moves which are expensive on various cores . To avoid this we do n't allow ALL_REGS as the allocno class , but force a decision between FP_REGS and GENERAL_REGS . We use the allocno class if it is n't ALL_REGS . Similarly , use the best class if it is n't ALL_REGS . Otherwise set the allocno class depending on the mode . The result of this is that it is no longer inefficient to have a higher memory move cost than the register move cost .


<s>
static
const
char
*
avr_out_movhi_r_mr_reg_disp_tiny
(
rtx
op
[
]
,
int
*
plen
)
{
rtx
dest
=
op
[
0
]
;
rtx
src
=
op
[
1
]
;
rtx
base
=
XEXP
(
src
,
0
)
;
int
reg_dest
=
true_regnum
(
dest
)
;
int
reg_base
=
true_regnum
(
XEXP
(
base
,
0
)
)
;
if
(
reg_base
==
reg_dest
)
{
return
avr_asm_len
(
TINY_ADIW
(
%
I1
,
%
J1
,
%
o1
)
CR_TAB
"ld __tmp_reg__,%b1+"
CR_TAB
"ld %B0,%b1"
CR_TAB
"mov %A0,__tmp_reg__"
,
op
,
plen
,
5
)
;
}
else
{
return
avr_asm_len
(
TINY_ADIW
(
%
I1
,
%
J1
,
%
o1
)
CR_TAB
"ld %A0,%b1+"
CR_TAB
"ld %B0,%b1"
CR_TAB
TINY_SBIW
(
%
I1
,
%
J1
,
%
o1
+
1
)
,
op
,
plen
,
6
)
;
}
}
</s>

Same as movhi_r_mr , but TINY does not have ADIW , SBIW and LDD


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> virtual unsigned int execute ( function * ) { return convert_scalars_to_vector ( ) ; } </s>


<s> tree memory_scalar_type ( const function_instance & fi ) const OVERRIDE { return fi . scalar_type ( 0 ) ; } </s>

If the function addresses memory , return the type of a single scalar memory element .


<s> BitVector AArch64RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const AArch64FrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AArch64 :: SP ) ; Reserved . set ( AArch64 :: XZR ) ; Reserved . set ( AArch64 :: WSP ) ; Reserved . set ( AArch64 :: WZR ) ; if ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) { Reserved . set ( AArch64 :: FP ) ; Reserved . set ( AArch64 :: W29 ) ; } if ( TT . isOSDarwin ( ) || ReserveX18 ) { Reserved . set ( AArch64 :: X18 ) ; Reserved . set ( AArch64 :: W18 ) ; } if ( hasBasePointer ( MF ) ) { Reserved . set ( AArch64 :: X19 ) ; Reserved . set ( AArch64 :: W19 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static void mcore_setup_incoming_varargs ( CUMULATIVE_ARGS * args_so_far , enum machine_mode mode , tree type , int * ptr_pretend_size ATTRIBUTE_UNUSED , int second_time ATTRIBUTE_UNUSED ) { current_function_anonymous_args = 1 ; number_of_regs_before_varargs = * args_so_far + mcore_num_arg_regs ( mode , type ) ; number_of_regs_before_varargs = * args_so_far ; if ( number_of_regs_before_varargs > NPARM_REGS ) number_of_regs_before_varargs = NPARM_REGS ; } </s>

Keep track of some information about varargs for the prolog .


<s>
unsigned
HexagonInstrInfo
::
getSize
(
const
MachineInstr
*
MI
)
const
{
if
(
MI
->
isDebugValue
(
)
||
MI
->
isPosition
(
)
)
return
0
;
unsigned
Size
=
MI
->
getDesc
(
)
.
getSize
(
)
;
if
(
!
Size
)
Size
=
HEXAGON_INSTR_SIZE
;
if
(
isConstExtended
(
MI
)
||
isExtended
(
MI
)
)
Size
+=
HEXAGON_INSTR_SIZE
;
if
(
BranchRelaxAsmLarge
&&
MI
->
getOpcode
(
)
==
Hexagon
::
INLINEASM
)
{
const
MachineBasicBlock
&
MBB
=
*
MI
->
getParent
(
)
;
const
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
const
MCAsmInfo
*
MAI
=
MF
->
getTarget
(
)
.
getMCAsmInfo
(
)
;
unsigned
NumDefs
=
0
;
for
(
;
MI
->
getOperand
(
NumDefs
)
.
isReg
(
)
&&
MI
->
getOperand
(
NumDefs
)
.
isDef
(
)
;
++
NumDefs
)
assert
(
NumDefs
!=
MI
->
getNumOperands
(
)
2
&&
"No asm string?"
)
;
assert
(
MI
->
getOperand
(
NumDefs
)
.
isSymbol
(
)
&&
"No asm string?"
)
;
const
char
*
AsmStr
=
MI
->
getOperand
(
NumDefs
)
.
getSymbolName
(
)
;
Size
=
getInlineAsmLength
(
AsmStr
,
*
MAI
)
;
}
return
Size
;
}
</s>

Return the number of bytes in the encoding of this instruction , or zero if the encoding size can not be known from the opcode .


<s>
static
tree
get_arm_sve_vector_bits_attributes
(
tree
old_attrs
,
tree
new_sve_type_args
)
{
tree
new_attrs
=
NULL_TREE
;
tree
*
ptr
=
&
new_attrs
;
for
(
tree
attr
=
old_attrs
;
attr
;
attr
=
TREE_CHAIN
(
attr
)
)
{
tree
name
=
get_attribute_name
(
attr
)
;
if
(
is_attribute_p
(
"SVE sizeless type"
,
name
)
)
continue
;
tree
args
=
TREE_VALUE
(
attr
)
;
if
(
is_attribute_p
(
"SVE type"
,
name
)
)
args
=
new_sve_type_args
;
*
ptr
=
tree_cons
(
TREE_PURPOSE
(
attr
)
,
args
,
NULL_TREE
)
;
ptr
=
&
TREE_CHAIN
(
*
ptr
)
;
}
return
new_attrs
;
}
</s>

ATTRS is the attribute list for a sizeless SVE type . Return the attributes of the associated fixed-length SVE type , taking the `` SVE type '' attributes from NEW_SVE_TYPE_ARGS .


<s> static rtx sh_trampoline_adjust_address ( rtx tramp ) { return tramp ; } </s>

On SH5 , trampolines are SHmedia code , so add 1 to the address .


<s> static void spu_unique_section ( tree decl , int reloc ) { if ( TREE_TYPE ( decl ) != error_mark_node && TYPE_ADDR_SPACE ( TREE_TYPE ( decl ) ) != 0 ) return ; default_unique_section ( decl , reloc ) ; } </s>


<s> static section * riscv_elf_select_rtx_section ( machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ) { section * s = default_elf_select_rtx_section ( mode , x , align ) ; if ( riscv_size_ok_for_small_data_p ( GET_MODE_SIZE ( mode ) ) ) { if ( startswith ( s -> named . name , ".rodata.cst" ) ) { char * name = ( char * ) alloca ( strlen ( s -> named . name ) + 2 ) ; sprintf ( name , ".s%s" , s -> named . name + 1 ) ; return get_section ( name , s -> named . common . flags , NULL ) ; } if ( s == data_section ) return sdata_section ; } return s ; } </s>

Return a section for X , handling small data .


<s> TargetPassConfig * LM32TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new LM32PassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> bool SIInstrInfo :: usesConstantBus ( const MachineRegisterInfo & MRI , const MachineOperand & MO , unsigned OpSize ) const { if ( isLiteralConstant ( MO , OpSize ) ) return true ; if ( ! MO . isReg ( ) || ! MO . isUse ( ) ) return false ; if ( TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) return RI . isSGPRClass ( MRI . getRegClass ( MO . getReg ( ) ) ) ; if ( ! MO . isImplicit ( ) && ( MO . getReg ( ) == AMDGPU :: FLAT_SCR ) ) return true ; if ( ! MO . isImplicit ( ) && MO . getReg ( ) == AMDGPU :: EXEC ) return true ; return ( MO . getReg ( ) == AMDGPU :: VCC || MO . getReg ( ) == AMDGPU :: M0 || ( ! MO . isImplicit ( ) && ( AMDGPU :: SGPR_32RegClass . contains ( MO . getReg ( ) ) || AMDGPU :: SGPR_64RegClass . contains ( MO . getReg ( ) ) ) ) ) ; } </s>

Returns true if this operand uses the constant bus .


<s> bool X86FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; const X86Subtarget & STI = MF . getSubtarget < X86Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; unsigned Opc = STI . is64Bit ( ) ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - 1 ] . getFrameIdx ( ) , RC , TRI ) ; -- MI ; MI -> setFlag ( MachineInstr :: FrameSetup ) ; ++ MI ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> bool NVPTXLowerAlloca :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; bool Changed = false ; for ( auto & BB : F ) for ( auto & I : BB ) { if ( auto allocaInst = dyn_cast < AllocaInst > ( & I ) ) { Changed = true ; auto PTy = dyn_cast < PointerType > ( allocaInst -> getType ( ) ) ; auto ETy = PTy -> getElementType ( ) ; auto LocalAddrTy = PointerType :: get ( ETy , ADDRESS_SPACE_LOCAL ) ; auto NewASCToLocal = new AddrSpaceCastInst ( allocaInst , LocalAddrTy , "" ) ; auto GenericAddrTy = PointerType :: get ( ETy , ADDRESS_SPACE_GENERIC ) ; auto NewASCToGeneric = new AddrSpaceCastInst ( NewASCToLocal , GenericAddrTy , "" ) ; NewASCToLocal -> insertAfter ( allocaInst ) ; NewASCToGeneric -> insertAfter ( NewASCToLocal ) ; for ( Value :: use_iterator UI = allocaInst -> use_begin ( ) , UE = allocaInst -> use_end ( ) ; UI != UE ; ) { const auto & AllocaUse = * UI ++ ; auto LI = dyn_cast < LoadInst > ( AllocaUse . getUser ( ) ) ; if ( LI && LI -> getPointerOperand ( ) == allocaInst && ! LI -> isVolatile ( ) ) { LI -> setOperand ( LI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; } auto SI = dyn_cast < StoreInst > ( AllocaUse . getUser ( ) ) ; if ( SI && SI -> getPointerOperand ( ) == allocaInst && ! SI -> isVolatile ( ) ) { SI -> setOperand ( SI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; } auto GI = dyn_cast < GetElementPtrInst > ( AllocaUse . getUser ( ) ) ; if ( GI && GI -> getPointerOperand ( ) == allocaInst ) { GI -> setOperand ( GI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; } auto BI = dyn_cast < BitCastInst > ( AllocaUse . getUser ( ) ) ; if ( BI && BI -> getOperand ( 0 ) == allocaInst ) { BI -> setOperand ( 0 , NewASCToGeneric ) ; continue ; } } } } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s>
void
xtensa_emit_loop_end
(
rtx
insn
,
rtx
*
operands
)
{
char
done
=
0
;
for
(
insn
=
PREV_INSN
(
insn
)
;
insn
&&
!
done
;
insn
=
PREV_INSN
(
insn
)
)
{
switch
(
GET_CODE
(
insn
)
)
{
case
NOTE
:
case
BARRIER
:
break
;
case
CODE_LABEL
:
output_asm_insn
(
TARGET_DENSITY
"nop.n"
:
"nop"
,
operands
)
;
done
=
1
;
break
;
default
:
{
rtx
body
=
PATTERN
(
insn
)
;
if
(
GET_CODE
(
body
)
==
JUMP_INSN
)
{
output_asm_insn
(
TARGET_DENSITY
"nop.n"
:
"nop"
,
operands
)
;
done
=
1
;
}
else
if
(
(
GET_CODE
(
body
)
!=
USE
)
&&
(
GET_CODE
(
body
)
!=
CLOBBER
)
)
done
=
1
;
}
break
;
}
}
output_asm_insn
(
"# loop end for %0"
,
operands
)
;
}
</s>

Emit the assembly for the end of a zero-cost loop . Normally we just emit a comment showing where the end of the loop is . However , if there is a label or a branch at the end of the loop then we need to place a nop there . If the loop ends with a label we need the nop so that branches targetting that label will target the nop ( and thus remain in the loop ) , instead of targetting the instruction after the loop ( and thus exiting the loop ) . If the loop ends with a branch , we need the nop in case the branch is targetting a location inside the loop . When the branch executes it will cause the loop count to be decremented even if it is taken ( because it is the last instruction in the loop ) , so we need to nop after the branch to prevent the loop count from being decremented when the branch is taken .


<s> static rtx mep_function_arg ( cumulative_args_t cum_v , machine_mode mode , const_tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( mode == VOIDmode ) return GEN_INT ( cum -> vliw ) ; if ( cum -> nregs < 4 ) { if ( type && TARGET_IVC2 && VECTOR_TYPE_P ( type ) ) return gen_rtx_REG ( mode , cum -> nregs + 49 ) ; else return gen_rtx_REG ( mode , cum -> nregs + 1 ) ; } return NULL_RTX ; } </s>

The ABI is thus : Arguments are in $ 1 , $ 2 , $ 3 , $ 4 , stack . Arguments larger than 4 bytes are passed indirectly . Return value in 0 , unless bigger than 4 bytes , then the caller passes a pointer as the first arg . For varargs , we copy $ 1 .. $ 4 to the stack .


<s> uint32_t generateCompactUnwindEncoding ( ArrayRef < MCCFIInstruction > Instrs ) const override { return SupportsCU ? generateCompactUnwindEncodingImpl ( Instrs ) : 0 ; } </s>

Generate compact unwind encoding for the function based on the CFI instructions .


<s> void Clear ( ) { Stack . clear ( ) ; LocalTypes . clear ( ) ; ReturnTypes . clear ( ) ; TypeErrorThisFunction = false ; } </s>

Clear value data entries and edge counters .


<s>
void
HexagonInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
OS
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
)
{
assert
(
HexagonMCInstrInfo
::
isBundle
(
*
MI
)
)
;
assert
(
HexagonMCInstrInfo
::
bundleSize
(
*
MI
)
<=
HEXAGON_PACKET_SIZE
)
;
assert
(
HexagonMCInstrInfo
::
bundleSize
(
*
MI
)
>
0
)
;
HasExtender
=
false
;
for
(
auto
const
&
I
:
HexagonMCInstrInfo
::
bundleInstructions
(
*
MI
)
)
{
MCInst
const
&
MCI
=
*
I
.
getInst
(
)
;
if
(
HexagonMCInstrInfo
::
isDuplex
(
MII
,
MCI
)
)
{
printInstruction
(
MCI
.
getOperand
(
1
)
.
getInst
(
)
,
OS
)
;
OS
<<
'\v'
;
HasExtender
=
false
;
printInstruction
(
MCI
.
getOperand
(
0
)
.
getInst
(
)
,
OS
)
;
}
else
printInstruction
(
&
MCI
,
OS
)
;
setExtender
(
MCI
)
;
OS
<<
"\n"
;
}
auto
Separator
=
""
;
if
(
HexagonMCInstrInfo
::
isInnerLoop
(
*
MI
)
)
{
OS
<<
Separator
;
Separator
=
" "
;
MCInst
ME
;
ME
.
setOpcode
(
Hexagon
::
ENDLOOP0
)
;
printInstruction
(
&
ME
,
OS
)
;
}
if
(
HexagonMCInstrInfo
::
isOuterLoop
(
*
MI
)
)
{
OS
<<
Separator
;
MCInst
ME
;
ME
.
setOpcode
(
Hexagon
::
ENDLOOP1
)
;
printInstruction
(
&
ME
,
OS
)
;
}
}
</s>

Print the specified MCInst to the specified raw_ostream .

Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
0
Hexagon
Hexagon
1
0
"\n"
""
Hexagon
" "
Hexagon::ENDLOOP0
Hexagon
Hexagon::ENDLOOP1


<s> static const char * getName ( ) { return DEBUG_TYPE ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> EVT PPCTargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return PPCSubTarget . useCRBits ( ) ? MVT :: i1 : MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> bool HexagonGenPredicate :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; TII = MF . getSubtarget < HexagonSubtarget > ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget < HexagonSubtarget > ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; PredGPRs . clear ( ) ; PUsers . clear ( ) ; G2P . clear ( ) ; bool Changed = false ; collectPredicateGPR ( MF ) ; for ( SetOfReg :: iterator I = PredGPRs . begin ( ) , E = PredGPRs . end ( ) ; I != E ; ++ I ) processPredicateGPR ( * I ) ; bool Again ; do { Again = false ; VectOfInst Processed , Copy ; typedef VectOfInst :: iterator iterator ; Copy = PUsers ; for ( iterator I = Copy . begin ( ) , E = Copy . end ( ) ; I != E ; ++ I ) { MachineInstr * MI = * I ; bool Done = convertToPredForm ( MI ) ; if ( Done ) { Processed . insert ( MI ) ; Again = true ; } } Changed |= Again ; auto Done = [ Processed ] ( MachineInstr * MI ) -> bool { return Processed . count ( MI ) ; } ; PUsers . remove_if ( Done ) ; } while ( Again ) ; Changed |= eliminatePredCopies ( MF ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool RISCVInstructionSelector :: select ( MachineInstr & I ) { if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) { return true ; } if ( selectImpl ( I , * CoverageInfo ) ) return true ; return false ; } </s>

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s> bool AlphaTargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createAlphaISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


"Expected one implicit def for call instruction"

Initialize the machine model for instruction scheduling .


<s> bool ARMTargetLowering :: isUsedByReturnOnly ( SDNode * N , SDValue & Chain ) const { if ( N -> getNumValues ( ) != 1 ) return false ; if ( ! N -> hasNUsesOfValue ( 1 , 0 ) ) return false ; SDValue TCChain = Chain ; SDNode * Copy = * N -> use_begin ( ) ; if ( Copy -> getOpcode ( ) == ISD :: CopyToReg ) { if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - 1 ) . getValueType ( ) == MVT :: Glue ) return false ; TCChain = Copy -> getOperand ( 0 ) ; } else if ( Copy -> getOpcode ( ) == ARMISD :: VMOVRRD ) { SDNode * VMov = Copy ; SmallPtrSet < SDNode * , 2 > Copies ; for ( SDNode :: use_iterator UI = VMov -> use_begin ( ) , UE = VMov -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != ISD :: CopyToReg ) return false ; Copies . insert ( * UI ) ; } if ( Copies . size ( ) > 2 ) return false ; for ( SDNode :: use_iterator UI = VMov -> use_begin ( ) , UE = VMov -> use_end ( ) ; UI != UE ; ++ UI ) { SDValue UseChain = UI -> getOperand ( 0 ) ; if ( Copies . count ( UseChain . getNode ( ) ) ) Copy = * UI ; else TCChain = UseChain ; } } else if ( Copy -> getOpcode ( ) == ISD :: BITCAST ) { if ( ! Copy -> hasOneUse ( ) ) return false ; Copy = * Copy -> use_begin ( ) ; if ( Copy -> getOpcode ( ) != ISD :: CopyToReg || ! Copy -> hasNUsesOfValue ( 1 , 0 ) ) return false ; Chain = Copy -> getOperand ( 0 ) ; } else { return false ; } bool HasRet = false ; for ( SDNode :: use_iterator UI = Copy -> use_begin ( ) , UE = Copy -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != ARMISD :: RET_FLAG ) return false ; HasRet = true ; } if ( ! HasRet ) return false ; Chain = TCChain ; return true ; } </s>

Return true if result of the specified node is used by a return node only .


<s>
unsigned
SHUXIMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
{
return
CTX
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
}
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
if
(
MO
.
isExpr
(
)
)
{
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
MCExpr
::
ExprKind
Kind
=
Expr
->
getKind
(
)
;
if
(
Kind
==
MCExpr
::
Constant
)
{
return
cast
<
MCConstantExpr
>
(
Expr
)
->
getValue
(
)
;
}
if
(
Kind
==
MCExpr
::
Binary
)
{
Expr
=
static_cast
<
const
MCBinaryExpr
*
>
(
Expr
)
->
getLHS
(
)
;
Kind
=
Expr
->
getKind
(
)
;
}
assert
(
Kind
==
MCExpr
::
SymbolRef
&&
"unknown MCExpr kind"
)
;
SHUXI
::
Fixups
FixupKind
=
SHUXI
::
Fixups
(
0
)
;
switch
(
cast
<
MCSymbolRefExpr
>
(
Expr
)
->
getKind
(
)
)
{
default
:
llvm_unreachable
(
"Unknown fixup kind!"
)
;
case
MCSymbolRefExpr
::
VK_None
:
FixupKind
=
SHUXI
::
fixup_SHUXI_32
;
break
;
}
Fixups
.
push_back
(
MCFixup
::
create
(
0
,
Expr
,
MCFixupKind
(
FixupKind
)
)
)
;
return
0
;
}
llvm_unreachable
(
"Unhandled expression!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> bool SITargetLowering :: canMergeStoresTo ( unsigned AS , EVT MemVT , const SelectionDAG & DAG ) const { if ( AS == AMDGPUAS :: GLOBAL_ADDRESS || AS == AMDGPUAS :: FLAT_ADDRESS ) { return ( MemVT . getSizeInBits ( ) <= 4 * 32 ) ; } else if ( AS == AMDGPUAS :: PRIVATE_ADDRESS ) { unsigned MaxPrivateBits = 8 * getSubtarget ( ) -> getMaxPrivateElementSize ( ) ; return ( MemVT . getSizeInBits ( ) <= MaxPrivateBits ) ; } else if ( AS == AMDGPUAS :: LOCAL_ADDRESS ) { return ( MemVT . getSizeInBits ( ) <= 2 * 32 ) ; } return true ; } </s>

Returns if it 's reasonable to merge stores to MemVT size .


<s> static bool use_32bit_hwmult ( void ) { static const char * cached_match = NULL ; static bool cached_result ; if ( msp430_hwmult_type == MSP430_HWMULT_LARGE ) return true ; if ( target_mcu == NULL || msp430_hwmult_type != MSP430_HWMULT_AUTO ) return false ; if ( target_mcu == cached_match ) return cached_result ; cached_match = target_mcu ; msp430_extract_mcu_data ( target_mcu ) ; if ( extracted_mcu_data . name != NULL ) return cached_result = extracted_mcu_data . hwmpy == 4 ; return cached_result = false ; } </s>

Returns true if the current MCU has a second generation 32-bit hardware multiplier .


The AVR backend 's rtx_cost function . X is rtx expression whose cost is to be calculated . Return true if the complete cost has been computed , and false if subexpressions should be scanned . In either case , * TOTAL contains the cost result .


<s> void ix86_expand_xorsign ( rtx operands [ ] ) { rtx ( * xorsign_insn ) ( rtx , rtx , rtx , rtx ) ; machine_mode mode , vmode ; rtx dest , op0 , op1 , mask ; dest = operands [ 0 ] ; op0 = operands [ 1 ] ; op1 = operands [ 2 ] ; mode = GET_MODE ( dest ) ; if ( mode == SFmode ) { xorsign_insn = gen_xorsignsf3_1 ; vmode = V4SFmode ; } else if ( mode == DFmode ) { xorsign_insn = gen_xorsigndf3_1 ; vmode = V2DFmode ; } else gcc_unreachable ( ) ; mask = ix86_build_signbit_mask ( vmode , 0 , 0 ) ; emit_insn ( xorsign_insn ( dest , op0 , op1 , mask ) ) ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addPreserved < StackProtector > ( ) ; AU . addRequired < TargetTransformInfoWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
Optional
<
DestSourcePair
>
AArch64InstrInfo
::
isAddImmediate
(
const
MachineInstr
&
MI
,
int64_t
&
Offset
)
const
{
int
Sign
=
1
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
return
;
case
AArch64
::
SUBWri
:
case
AArch64
::
SUBXri
:
case
AArch64
::
SUBSWri
:
case
AArch64
::
SUBSXri
:
Sign
*=
1
;
LLVM_FALLTHROUGH
;
case
AArch64
::
ADDSWri
:
case
AArch64
::
ADDSXri
:
case
AArch64
::
ADDWri
:
case
AArch64
::
ADDXri
:
{
if
(
!
MI
.
getOperand
(
0
)
.
isReg
(
)
||
!
MI
.
getOperand
(
1
)
.
isReg
(
)
||
!
MI
.
getOperand
(
2
)
.
isImm
(
)
)
return
;
Offset
=
MI
.
getOperand
(
2
)
.
getImm
(
)
*
Sign
;
int
Shift
=
MI
.
getOperand
(
3
)
.
getImm
(
)
;
assert
(
(
Shift
==
0
||
Shift
==
12
)
&&
"Shift can be either 0 or 12"
)
;
Offset
=
Offset
<<
Shift
;
}
}
return
DestSourcePair
{
MI
.
getOperand
(
0
)
,
MI
.
getOperand
(
1
)
}
;
}
</s>

If the specific machine instruction is an instruction that adds an immediate value and a register , and stores the result in the given register Reg , return a pair of the source register and the offset which has been added .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineModuleInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> static void s390_frame_area ( int * area_bottom , int * area_top ) { int b , t ; b = INT_MAX ; t = INT_MIN ; if ( cfun_frame_layout . first_restore_gpr != - 1 ) { b = ( cfun_frame_layout . gprs_offset + cfun_frame_layout . first_restore_gpr * UNITS_PER_LONG ) ; t = b + ( cfun_frame_layout . last_restore_gpr - cfun_frame_layout . first_restore_gpr + 1 ) * UNITS_PER_LONG ; } if ( TARGET_64BIT && cfun_save_high_fprs_p ) { b = MIN ( b , cfun_frame_layout . f8_offset ) ; t = MAX ( t , ( cfun_frame_layout . f8_offset + cfun_frame_layout . high_fprs * 8 ) ) ; } if ( ! TARGET_64BIT ) { if ( cfun_fpr_save_p ( FPR4_REGNUM ) ) { b = MIN ( b , cfun_frame_layout . f4_offset ) ; t = MAX ( t , cfun_frame_layout . f4_offset + 8 ) ; } if ( cfun_fpr_save_p ( FPR6_REGNUM ) ) { b = MIN ( b , cfun_frame_layout . f4_offset + 8 ) ; t = MAX ( t , cfun_frame_layout . f4_offset + 16 ) ; } } * area_bottom = b ; * area_top = t ; } </s>

Determine the frame area which actually has to be accessed in the function epilogue . The values are stored at the given pointers AREA_BOTTOM ( address of the lowest used stack address ) and AREA_TOP ( address of the first item which does not belong to the stack frame ) .


<s>
StringRef
getPassName
(
)
const
override
{
return
"AAP Short Instruction Peephole"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
void
SystemZInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MBBI
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
SystemZ
::
GR128BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
copyPhysReg
(
MBB
,
MBBI
,
DL
,
RI
.
getSubReg
(
DestReg
,
SystemZ
::
subreg_high
)
,
RI
.
getSubReg
(
SrcReg
,
SystemZ
::
subreg_high
)
,
KillSrc
)
;
copyPhysReg
(
MBB
,
MBBI
,
DL
,
RI
.
getSubReg
(
DestReg
,
SystemZ
::
subreg_low
)
,
RI
.
getSubReg
(
SrcReg
,
SystemZ
::
subreg_low
)
,
KillSrc
)
;
return
;
}
unsigned
Opcode
;
if
(
SystemZ
::
GR32BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LR
;
else
if
(
SystemZ
::
GR64BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LGR
;
else
if
(
SystemZ
::
FP32BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LER
;
else
if
(
SystemZ
::
FP64BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LDR
;
else
if
(
SystemZ
::
FP128BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LXR
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
Opcode
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> bool splitFramePushPop ( const MachineFunction & MF ) const { return ( getFramePointerReg ( ) == ARM :: R7 && MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) || isThumb1Only ( ) ; } </s>

Returns true if the frame setup is split into two separate pushes ( first r0-r7 , lr then r8-r11 ) , principally so that the frame pointer is adjacent to lr .


<s>
void
NVPTXTargetStreamer
::
changeSection
(
const
MCSection
*
CurSection
,
MCSection
*
Section
,
const
MCExpr
*
SubSection
,
raw_ostream
&
OS
)
{
assert
(
!
SubSection
&&
"SubSection is not null!"
)
;
const
MCObjectFileInfo
*
FI
=
getStreamer
(
)
.
getContext
(
)
.
getObjectFileInfo
(
)
;
if
(
isDwarfSection
(
FI
,
CurSection
)
)
OS
<<
"\t}\n"
;
if
(
isDwarfSection
(
FI
,
Section
)
)
{
outputDwarfFileDirectives
(
)
;
OS
<<
"\t.section"
;
Section
->
PrintSwitchToSection
(
*
getStreamer
(
)
.
getContext
(
)
.
getAsmInfo
(
)
,
getStreamer
(
)
.
getContext
(
)
.
getTargetTriple
(
)
,
OS
,
SubSection
)
;
OS
<<
"\t{\n"
;
HasSections
=
true
;
}
}
</s>

Update streamer for a new active section .

NVPTX
NVPTX
"SubSection is not null!"
"\t}\n"
"\t.section"
"\t{\n"


<s> static rtx pseudo_reg_set ( rtx_insn * insn ) { rtx set = single_set ( insn ) ; if ( ! set ) return NULL ; machine_mode mode = TARGET_64BIT ? TImode : DImode ; if ( REG_P ( SET_SRC ( set ) ) && ! HARD_REGISTER_P ( SET_SRC ( set ) ) && push_operand ( SET_DEST ( set ) , mode ) ) return set ; df_ref ref ; FOR_EACH_INSN_DEF ( ref , insn ) if ( HARD_REGISTER_P ( DF_REF_REAL_REG ( ref ) ) && ! DF_REF_FLAGS_IS_SET ( ref , DF_REF_MUST_CLOBBER ) && DF_REF_REGNO ( ref ) != FLAGS_REG ) return NULL ; FOR_EACH_INSN_USE ( ref , insn ) if ( ! DF_REF_REG_MEM_P ( ref ) && HARD_REGISTER_P ( DF_REF_REAL_REG ( ref ) ) ) return NULL ; return set ; } </s>

Return the SET expression if INSN does n't reference hard register . Return NULL if INSN uses or defines a hard register , excluding pseudo register pushes , hard register uses in a memory address , clobbers and flags definitions .


<s> static bool mips16e_collect_argument_save_p ( rtx dest , rtx src , rtx * reg_values , unsigned int * regno_ptr ) { unsigned int argno , regno ; HOST_WIDE_INT offset , required_offset ; rtx addr , base ; if ( ! MEM_P ( dest ) || ! REG_P ( src ) || GET_MODE ( dest ) != word_mode ) return false ; regno = REGNO ( src ) ; if ( ! IN_RANGE ( regno , GP_ARG_FIRST , GP_ARG_LAST ) || reg_values [ regno ] ) return false ; argno = regno - GP_ARG_FIRST ; addr = mips16e_collect_propagate_value ( XEXP ( dest , 0 ) , reg_values ) ; mips_split_plus ( addr , & base , & offset ) ; required_offset = cfun -> machine -> frame . total_size + argno * UNITS_PER_WORD ; if ( base == hard_frame_pointer_rtx ) required_offset -= cfun -> machine -> frame . hard_frame_pointer_offset ; else if ( base != stack_pointer_rtx ) return false ; if ( offset != required_offset ) return false ; * regno_ptr = regno ; return true ; } </s>

Return true if ( set DEST SRC ) stores an argument register into its caller-allocated save slot , storing the number of that argument register in * REGNO_PTR if so . REG_VALUES is as for mips16e_collect_propagate_value .


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( ARM :: GPRRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( ARM :: t2LDRi12 ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; return ; } if ( ARM :: GPRPairRegClass . hasSubClassEq ( RC ) ) { if ( Register :: isVirtualRegister ( DestReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( DestReg , & ARM :: GPRPairnospRegClass ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( ARM :: t2LDRDi8 ) ) ; AddDReg ( MIB , DestReg , ARM :: gsub_0 , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , ARM :: gsub_1 , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; if ( Register :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; } ARMBaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC , TRI ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> static bool alpha_scalar_mode_supported_p ( enum machine_mode mode ) { switch ( mode ) { case QImode : case HImode : case SImode : case DImode : case TImode : return true ; case SFmode : case DFmode : return true ; case TFmode : return TARGET_HAS_XFLOATING_LIBS ; default : return false ; } } </s>

The scalar modes supported differs from the default check-what-c-supports version in that sometimes TFmode is available even when long double indicates only DFmode . On unicosmk , we have the situation that HImode does n't map to any C type , but of course we still support that .


<s> void NVPTXAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; if ( static_cast < NVPTXTargetMachine & > ( TM ) . getDrvInterface ( ) == NVPTX :: CUDA ) emitLineNumberAsDotLoc ( * MI ) ; MCInst Inst ; lowerToMCInst ( MI , Inst ) ; EmitToStreamer ( OutStreamer , Inst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
StringRef
getPassName
(
)
const
override
{
return
"ARM Indirect Thunks"
;
}
</s>


<s> static bool is_branch_slot_insn ( rtx_insn * insn ) { if ( ! insn || ! NONDEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; if ( rs6000_sched_groups ) { enum attr_type type = get_attr_type ( insn ) ; if ( type == TYPE_BRANCH || type == TYPE_JMPREG ) return true ; return false ; } return false ; } </s>

The function returns true if INSN can be issued only from the branch slot .


<s> void MBlazeAsmBackend :: relaxInstruction ( const MCInst & Inst , MCInst & Res ) const { Res = Inst ; Res . setOpcode ( getRelaxedOpcode ( Inst . getOpcode ( ) ) ) ; } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s>
bool
AMDGPUOpenCLEnqueuedBlockLowering
::
runOnModule
(
Module
&
M
)
{
DenseSet
<
Function
*
>
Callers
;
auto
&
C
=
M
.
getContext
(
)
;
bool
Changed
=
false
;
for
(
auto
&
F
:
M
.
functions
(
)
)
{
if
(
F
.
hasFnAttribute
(
"enqueued-block"
)
)
{
if
(
!
F
.
hasName
(
)
)
{
SmallString
<
64
>
Name
;
Mangler
::
getNameWithPrefix
(
Name
,
"__amdgpu_enqueued_kernel"
,
M
.
getDataLayout
(
)
)
;
F
.
setName
(
Name
)
;
}
auto
RuntimeHandle
=
(
F
.
getName
(
)
+
".runtime_handle"
)
.
str
(
)
;
auto
*
GV
=
new
GlobalVariable
(
M
,
Type
::
getInt8Ty
(
C
)
->
getPointerTo
(
AMDGPUAS
::
GLOBAL_ADDRESS
)
,
true
,
GlobalValue
::
ExternalLinkage
,
nullptr
,
RuntimeHandle
,
nullptr
,
GlobalValue
::
NotThreadLocal
,
AMDGPUAS
::
GLOBAL_ADDRESS
,
true
)
;
DEBUG
(
dbgs
(
)
<<
"runtime handle created: "
<<
*
GV
<<
'\n'
)
;
for
(
auto
U
:
F
.
users
(
)
)
{
if
(
!
isa
<
ConstantExpr
>
(
&
*
U
)
)
continue
;
auto
*
BitCast
=
cast
<
ConstantExpr
>
(
&
*
U
)
;
auto
*
NewPtr
=
ConstantExpr
::
getPointerCast
(
GV
,
BitCast
->
getType
(
)
)
;
BitCast
->
replaceAllUsesWith
(
NewPtr
)
;
F
.
addFnAttr
(
"runtime-handle"
,
RuntimeHandle
)
;
F
.
setLinkage
(
GlobalValue
::
ExternalLinkage
)
;
for
(
auto
U
:
NewPtr
->
users
(
)
)
{
if
(
auto
*
I
=
dyn_cast
<
Instruction
>
(
&
*
U
)
)
{
auto
*
F
=
I
->
getParent
(
)
->
getParent
(
)
;
Callers
.
insert
(
F
)
;
collectCallers
(
F
,
Callers
)
;
}
}
Changed
=
true
;
}
}
}
for
(
auto
F
:
Callers
)
{
if
(
F
->
getCallingConv
(
)
!=
CallingConv
::
AMDGPU_KERNEL
)
continue
;
F
->
addFnAttr
(
"calls-enqueue-kernel"
)
;
}
return
Changed
;
}
</s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .

AMDGPU
AMDGPU
"enqueued-block"
64
"__amdgpu_enqueued_kernel"
".runtime_handle"
AMDGPU
AMDGPU
"runtime handle created: "
"runtime-handle"
AMDGPU
"calls-enqueue-kernel"


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> int simple_memory_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { rtx addr ; if ( GET_CODE ( op ) != MEM ) return FALSE ; if ( GET_MODE_SIZE ( GET_MODE ( op ) ) > ( HAVE_64BIT_P ( ) ? 8 : 4 ) ) return FALSE ; indirection : addr = XEXP ( op , 0 ) ; switch ( GET_CODE ( addr ) ) { case REG : return 1 ; case PRE_DEC : case POST_INC : return 0 ; case MEM : if ( GET_CODE ( XEXP ( addr , 0 ) ) == REG ) return 0 ; op = addr ; goto indirection ; case CONST_INT : case LABEL_REF : case CONST : case SYMBOL_REF : return 0 ; case PLUS : return 0 ; default : break ; } return FALSE ; } </s>

Return truth value if a memory operand fits in a single instruction ( ie , register + small offset ) .


<s> static rtx pa_function_value ( const_tree valtype , const_tree func ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode valmode ; if ( AGGREGATE_TYPE_P ( valtype ) || TREE_CODE ( valtype ) == COMPLEX_TYPE || TREE_CODE ( valtype ) == VECTOR_TYPE ) { HOST_WIDE_INT valsize = int_size_in_bytes ( valtype ) ; if ( valsize == UNITS_PER_WORD || valsize == 2 * UNITS_PER_WORD ) return gen_rtx_REG ( TYPE_MODE ( valtype ) , 28 ) ; if ( TARGET_64BIT ) { rtx loc [ 2 ] ; int i , offset = 0 ; int ub = valsize <= UNITS_PER_WORD ? 1 : 2 ; for ( i = 0 ; i < ub ; i ++ ) { loc [ i ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , 28 + i ) , GEN_INT ( offset ) ) ; offset += 8 ; } return gen_rtx_PARALLEL ( BLKmode , gen_rtvec_v ( ub , loc ) ) ; } else if ( valsize > UNITS_PER_WORD ) { rtx loc = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , 28 ) , const0_rtx ) ; return gen_rtx_PARALLEL ( BLKmode , gen_rtvec ( 1 , loc ) ) ; } } if ( ( INTEGRAL_TYPE_P ( valtype ) && GET_MODE_BITSIZE ( TYPE_MODE ( valtype ) ) < BITS_PER_WORD ) || POINTER_TYPE_P ( valtype ) ) valmode = word_mode ; else valmode = TYPE_MODE ( valtype ) ; if ( TREE_CODE ( valtype ) == REAL_TYPE && ! AGGREGATE_TYPE_P ( valtype ) && TYPE_MODE ( valtype ) != TFmode && ! TARGET_SOFT_FLOAT ) return gen_rtx_REG ( valmode , 32 ) ; return gen_rtx_REG ( valmode , 28 ) ; } </s>

On the HP-PA the value is found in register ( s ) 28 ( -29 ) , unless the mode is SF or DF . Then the value is returned in fr4 ( 32 ) . This must perform the same promotions as PROMOTE_MODE , else promoting return values in TARGET_PROMOTE_FUNCTION_MODE will not work correctly . Small structures must be returned in a PARALLEL on PA64 in order to match the HP Compiler ABI .


<s> int arc_delay_slots_for_epilogue ( void ) { if ( arc_compute_function_type ( current_function_decl ) != ARC_FUNCTION_NORMAL ) return 0 ; if ( ! current_frame_info . initialized ) ( void ) arc_compute_frame_size ( get_frame_size ( ) ) ; if ( current_frame_info . total_size == 0 ) return 1 ; return 0 ; } </s>

Define the number of delay slots needed for the function epilogue . Interrupt handlers ca n't have any epilogue delay slots ( it 's always needed for something else , I think ) . For normal functions , we have to worry about using call-saved regs as they 'll be restored before the delay slot insn . Functions with non-empty frames already have enough choices for the epilogue delay slot so for now we only consider functions with empty frames .


<s> bool isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const override { return true ; } </s>

Returns true if a cast between SrcAS and DestAS is a noop .


<s> static bool pdp11_return_in_memory ( tree type , tree fntype ATTRIBUTE_UNUSED ) { return ( TYPE_MODE ( type ) == DImode || ( TYPE_MODE ( type ) == DFmode && ! TARGET_AC0 ) ) ; } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


<s> ARMCC :: CondCodes getPredicate ( const MachineInstr & MI ) const { int PIdx = MI . findFirstPredOperandIdx ( ) ; return PIdx != - 1 ? ( ARMCC :: CondCodes ) MI . getOperand ( PIdx ) . getImm ( ) : ARMCC :: AL ; } </s>

Returns the comparison predicate underlying the intrinsic .

ARM ARMCC::CondCodes 1 ARMCC::CondCodes ARMCC::AL


<s> bool isInterruptOrSignalHandler ( ) const { return isInterruptHandler ( ) || isSignalHandler ( ) ; } </s>

Checks if the function is some form of interrupt service routine .


<s> InstructionCost SystemZTTIImpl :: getIntrinsicInstrCost ( const IntrinsicCostAttributes & ICA , TTI :: TargetCostKind CostKind ) { InstructionCost Cost = getVectorIntrinsicInstrCost ( ICA . getID ( ) , ICA . getReturnType ( ) ) ; if ( Cost != - 1 ) return Cost ; return BaseT :: getIntrinsicInstrCost ( ICA , CostKind ) ; } </s>


<s> void initialize ( MCContext & Context ) { Ctx = & Context ; MSTI = Ctx -> getSubtargetInfo ( ) ; usesSgprAt ( SgprIndexUnusedMin = - 1 ) ; usesVgprAt ( VgprIndexUnusedMin = - 1 ) ; if ( hasMAIInsts ( * MSTI ) ) { usesAgprAt ( AgprIndexUnusedMin = - 1 ) ; } } </s>

Initialize the strategy after building the DAG for a new region .


"COPY with other register classes is not supported"


<s> static inline int inline_memory_move_cost ( machine_mode mode , enum reg_class regclass , int in ) { int cost ; if ( FLOAT_CLASS_P ( regclass ) ) { int index ; switch ( mode ) { case E_SFmode : index = 0 ; break ; case E_DFmode : index = 1 ; break ; case E_XFmode : index = 2 ; break ; default : return 100 ; } if ( in == 2 ) return MAX ( ix86_cost -> fp_load [ index ] , ix86_cost -> fp_store [ index ] ) ; return in ? ix86_cost -> fp_load [ index ] : ix86_cost -> fp_store [ index ] ; } if ( SSE_CLASS_P ( regclass ) ) { int index = sse_store_index ( mode ) ; if ( index == - 1 ) return 100 ; if ( in == 2 ) return MAX ( ix86_cost -> sse_load [ index ] , ix86_cost -> sse_store [ index ] ) ; return in ? ix86_cost -> sse_load [ index ] : ix86_cost -> sse_store [ index ] ; } if ( MMX_CLASS_P ( regclass ) ) { int index ; switch ( GET_MODE_SIZE ( mode ) ) { case 4 : index = 0 ; break ; case 8 : index = 1 ; break ; default : return 100 ; } if ( in == 2 ) return MAX ( ix86_cost -> mmx_load [ index ] , ix86_cost -> mmx_store [ index ] ) ; return in ? ix86_cost -> mmx_load [ index ] : ix86_cost -> mmx_store [ index ] ; } switch ( GET_MODE_SIZE ( mode ) ) { case 1 : if ( Q_CLASS_P ( regclass ) || TARGET_64BIT ) { if ( ! in ) return ix86_cost -> int_store [ 0 ] ; if ( TARGET_PARTIAL_REG_DEPENDENCY && optimize_function_for_speed_p ( cfun ) ) cost = ix86_cost -> movzbl_load ; else cost = ix86_cost -> int_load [ 0 ] ; if ( in == 2 ) return MAX ( cost , ix86_cost -> int_store [ 0 ] ) ; return cost ; } else { if ( in == 2 ) return MAX ( ix86_cost -> movzbl_load , ix86_cost -> int_store [ 0 ] + 4 ) ; if ( in ) return ix86_cost -> movzbl_load ; else return ix86_cost -> int_store [ 0 ] + 4 ; } break ; case 2 : if ( in == 2 ) return MAX ( ix86_cost -> int_load [ 1 ] , ix86_cost -> int_store [ 1 ] ) ; return in ? ix86_cost -> int_load [ 1 ] : ix86_cost -> int_store [ 1 ] ; default : if ( in == 2 ) cost = MAX ( ix86_cost -> int_load [ 2 ] , ix86_cost -> int_store [ 2 ] ) ; else if ( in ) cost = ix86_cost -> int_load [ 2 ] ; else cost = ix86_cost -> int_store [ 2 ] ; return cost * CEIL ( ( int ) GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ; } } </s>

Return the cost of moving data of mode M between a register and memory . A value of 2 is the default ; this cost is relative to those in ` REGISTER_MOVE_COST ' . This function is used extensively by register_move_cost that is used to build tables at startup . Make it inline in this case . When IN is 2 , return maximum of in and out move cost . If moving between registers and memory is more expensive than between two registers , you should define this macro to express the relative cost . Model also increased moving costs of QImode registers in non Q_REGS classes .


<s> bool legitimize_move ( rtx dest , rtx src , machine_mode mask_mode ) { machine_mode mode = GET_MODE ( dest ) ; if ( CONST_VECTOR_P ( src ) ) { expand_const_vector ( dest , src , mask_mode ) ; return true ; } if ( ( known_lt ( GET_MODE_SIZE ( mode ) , BYTES_PER_RISCV_VECTOR ) || GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL ) && lra_in_progress ) { emit_insn ( gen_mov_lra ( mode , Pmode , dest , src ) ) ; return true ; } if ( known_ge ( GET_MODE_SIZE ( mode ) , BYTES_PER_RISCV_VECTOR ) && GET_MODE_CLASS ( mode ) != MODE_VECTOR_BOOL ) { if ( MEM_P ( dest ) && ! REG_P ( src ) ) src = force_reg ( mode , src ) ; return false ; } if ( register_operand ( src , mode ) && register_operand ( dest , mode ) ) { emit_insn ( gen_rtx_SET ( dest , src ) ) ; return true ; } if ( ! register_operand ( src , mode ) && ! register_operand ( dest , mode ) ) { rtx tmp = gen_reg_rtx ( mode ) ; if ( MEM_P ( src ) ) emit_vlmax_op ( code_for_pred_mov ( mode ) , tmp , src , mask_mode ) ; else emit_move_insn ( tmp , src ) ; src = tmp ; } if ( satisfies_constraint_vu ( src ) ) return false ; emit_vlmax_op ( code_for_pred_mov ( mode ) , dest , src , mask_mode ) ; return true ; } </s>

Expand a pre-RA RVV data move from SRC to DEST . It expands move for RVV fractional vector modes .


<s> Register AArch64RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const AArch64FrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? AArch64 :: FP : AArch64 :: SP ; } </s>


<s> bool ARMPreAllocLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { if ( AssumeMisalignedLoadStores ) return false ; TD = & Fn . getDataLayout ( ) ; STI = & static_cast < const ARMSubtarget & > ( Fn . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; MF = & Fn ; bool Modified = false ; for ( MachineBasicBlock & MFI : Fn ) Modified |= RescheduleLoadStoreInstrs ( & MFI ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s>
static
void
walk_args_for_param
(
FILE
*
file
,
tree
argtypes
,
tree
args
,
bool
write_copy
,
bool
return_in_mem
)
{
int
i
;
bool
args_from_decl
=
false
;
if
(
argtypes
==
0
)
args_from_decl
=
true
;
else
args
=
argtypes
;
for
(
i
=
return_in_mem
1
:
0
;
args
!=
NULL_TREE
;
args
=
TREE_CHAIN
(
args
)
)
{
tree
type
=
args_from_decl
TREE_TYPE
(
args
)
:
TREE_VALUE
(
args
)
;
machine_mode
mode
=
TYPE_MODE
(
type
)
;
if
(
mode
==
VOIDmode
)
break
;
if
(
!
PASS_IN_REG_P
(
mode
,
type
)
)
mode
=
Pmode
;
int
count
=
maybe_split_mode
(
&
mode
)
;
if
(
count
==
1
)
{
if
(
argtypes
==
&&
!
AGGREGATE_TYPE_P
(
type
)
)
{
if
(
mode
==
SFmode
)
mode
=
DFmode
;
}
mode
=
arg_promotion
(
mode
)
;
}
while
(
count
>
0
)
{
i
++
;
if
(
write_copy
)
fprintf
(
file
,
"\tld.param%s %%ar%d, [%%in_ar%d];\n"
,
nvptx_ptx_type_from_mode
(
mode
,
false
)
,
i
,
i
)
;
else
fprintf
(
file
,
"\t.reg%s %%ar%d;\n"
,
nvptx_ptx_type_from_mode
(
mode
,
false
)
,
i
)
;
}
}
}
</s>

Walk either ARGTYPES or ARGS if the former is null , and write out part of the function header to FILE . If WRITE_COPY is false , write reg declarations , otherwise write the copy from the incoming argument to that reg . RETURN_IN_MEM indicates whether to start counting arg numbers at 1 instead of 0 .


<s>
void
AlphaTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
DebugLoc
dl
=
N
->
getDebugLoc
(
)
;
assert
(
N
->
getValueType
(
0
)
==
MVT
::
i32
&&
N
->
getOpcode
(
)
==
ISD
::
VAARG
&&
"Unknown node to custom promote!"
)
;
SDValue
Chain
,
DataPtr
;
LowerVAARG
(
N
,
Chain
,
DataPtr
,
DAG
)
;
SDValue
Res
=
DAG
.
getLoad
(
N
->
getValueType
(
0
)
,
dl
,
Chain
,
DataPtr
,
MachinePointerInfo
(
)
,
false
,
false
,
0
)
;
Results
.
push_back
(
Res
)
;
Results
.
push_back
(
SDValue
(
Res
.
getNode
(
)
,
1
)
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> static int xtensa_constantsynth_2insn ( rtx dst , HOST_WIDE_INT srcval , rtx ( * gen_op ) ( rtx , HOST_WIDE_INT ) , HOST_WIDE_INT op_imm ) { HOST_WIDE_INT imm = INT_MAX ; rtx x = NULL_RTX ; int shift ; gcc_assert ( REG_P ( dst ) ) ; shift = exact_log2 ( srcval + 1 ) ; if ( IN_RANGE ( shift , 1 , 31 ) ) { imm = - 1 ; x = gen_lshrsi3 ( dst , dst , GEN_INT ( 32 - shift ) ) ; } shift = ctz_hwi ( srcval ) ; if ( ( ! x || ( TARGET_DENSITY && ! IN_RANGE ( imm , - 32 , 95 ) ) ) && xtensa_simm12b ( srcval >> shift ) ) { imm = srcval >> shift ; x = gen_ashlsi3 ( dst , dst , GEN_INT ( shift ) ) ; } if ( ( ! x || ( TARGET_DENSITY && ! IN_RANGE ( imm , - 32 , 95 ) ) ) && IN_RANGE ( srcval , ( - 2048 - 32768 ) , ( 2047 + 32512 ) ) ) { HOST_WIDE_INT imm0 , imm1 ; if ( srcval < - 32768 ) imm1 = - 32768 ; else if ( srcval > 32512 ) imm1 = 32512 ; else imm1 = srcval & ~ 255 ; imm0 = srcval - imm1 ; if ( TARGET_DENSITY && imm1 < 32512 && IN_RANGE ( imm0 , 224 , 255 ) ) imm0 -= 256 , imm1 += 256 ; imm = imm0 ; x = gen_addsi3 ( dst , dst , GEN_INT ( imm1 ) ) ; } if ( ! x ) return 0 ; emit_move_insn ( dst , GEN_INT ( imm ) ) ; emit_insn ( x ) ; if ( gen_op ) emit_move_insn ( dst , gen_op ( dst , op_imm ) ) ; return 1 ; } </s>

Try to emit insns to load srcval ( that can not fit into signed 12-bit ) into dst with synthesizing a such constant value from a sequence of load-immediate / arithmetic ones , instead of a L32R instruction ( plus a constant in litpool ) .


getTargetNodeName - This method returns the name of a target specific


<s> void mips_finish_declare_object ( FILE * stream , tree decl , int top_level , int at_end ) { const char * name ; name = XSTR ( XEXP ( DECL_RTL ( decl ) , 0 ) , 0 ) ; if ( ! flag_inhibit_size_directive && DECL_SIZE ( decl ) != 0 && ! at_end && top_level && DECL_INITIAL ( decl ) == error_mark_node && ! size_directive_output ) { HOST_WIDE_INT size ; size_directive_output = 1 ; size = int_size_in_bytes ( TREE_TYPE ( decl ) ) ; ASM_OUTPUT_SIZE_DIRECTIVE ( stream , name , size ) ; } } </s>

Implement ASM_FINISH_DECLARE_OBJECT . This is generic ELF stuff .


<s> void WebAssemblyInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { assert ( RegNo != WebAssemblyFunctionInfo :: UnusedReg ) ; OS << "$" << RegNo ; } </s>


"Can only insert epilogue into returning blocks"


<s>
void
avr_final_prescan_insn
(
rtx_insn
*
insn
,
rtx
*
operand
ATTRIBUTE_UNUSED
,
int
num_operands
ATTRIBUTE_UNUSED
)
{
if
(
avr_log
.
rtx_costs
)
{
rtx
set
=
single_set
(
insn
)
;
if
(
set
)
fprintf
(
asm_out_file
,
"/* DEBUG: cost = %d.  */\n"
,
set_src_cost
(
SET_SRC
(
set
)
,
GET_MODE
(
SET_DEST
(
set
)
)
,
optimize_insn_for_speed_p
(
)
)
)
;
else
fprintf
(
asm_out_file
,
"/* DEBUG: pattern-cost = %d.  */\n"
,
rtx_cost
(
PATTERN
(
insn
)
,
VOIDmode
,
INSN
,
0
,
optimize_insn_for_speed_p
(
)
)
)
;
}
}
</s>

avr
"/* DEBUG: cost = %d.  */\n"
"/* DEBUG: pattern-cost = %d.  */\n"
0


<s> void HexagonMCShuffler :: init ( MCInst & MCB , MCInst const * AddMI , bool bInsertAtFront ) { if ( HexagonMCInstrInfo :: isBundle ( MCB ) ) { if ( bInsertAtFront && AddMI ) append ( AddMI , nullptr , HexagonMCInstrInfo :: getUnits ( MCII , STI , * AddMI ) , false ) ; MCInst const * Extender = nullptr ; for ( auto const & I : HexagonMCInstrInfo :: bundleInstructions ( MCB ) ) { assert ( ! HexagonMCInstrInfo :: getDesc ( MCII , * I . getInst ( ) ) . isPseudo ( ) ) ; MCInst * MI = const_cast < MCInst * > ( I . getInst ( ) ) ; if ( ! HexagonMCInstrInfo :: isImmext ( * MI ) ) { append ( MI , Extender , HexagonMCInstrInfo :: getUnits ( MCII , STI , * MI ) , false ) ; Extender = nullptr ; } else Extender = MI ; } if ( ! bInsertAtFront && AddMI ) append ( AddMI , nullptr , HexagonMCInstrInfo :: getUnits ( MCII , STI , * AddMI ) , false ) ; } BundleFlags = MCB . getOperand ( 0 ) . getImm ( ) ; } </s>

Initialize the machine model for instruction scheduling .

Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon 0


<s>
ARM64TTI
::
PopcntSupportKind
ARM64TTI
::
getPopcntSupport
(
unsigned
TyWidth
)
const
{
assert
(
isPowerOf2_32
(
TyWidth
)
&&
"Ty width must be power of 2"
)
;
if
(
TyWidth
==
32
||
TyWidth
==
64
)
return
PSK_FastHardware
;
return
PSK_Software
;
}
</s>

Return hardware support for population count .


"XtensaInstPrinter::printInst not yet implemented\n"

Print the specified MCInst to the specified raw_ostream .


<s> bool XtensaFrameLowering :: hasFP ( const MachineFunction & MF ) const { return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> int m32c_memory_move_cost ( enum machine_mode mode ATTRIBUTE_UNUSED , int reg_class ATTRIBUTE_UNUSED , int in ATTRIBUTE_UNUSED ) { return COSTS_N_INSNS ( 10 ) ; } </s>


<s> unsigned LoongArchAsmParser :: checkTargetMatchPredicate ( MCInst & Inst ) { switch ( Inst . getOpcode ( ) ) { default : break ; case LoongArch :: CSRXCHG : { unsigned Rj = Inst . getOperand ( 2 ) . getReg ( ) ; if ( Rj == LoongArch :: R0 || Rj == LoongArch :: R1 ) return Match_RequiresOpnd2NotR0R1 ; return Match_Success ; } case LoongArch :: BSTRINS_W : case LoongArch :: BSTRINS_D : case LoongArch :: BSTRPICK_W : case LoongArch :: BSTRPICK_D : { unsigned Opc = Inst . getOpcode ( ) ; const signed Msb = ( Opc == LoongArch :: BSTRINS_W || Opc == LoongArch :: BSTRINS_D ) ? Inst . getOperand ( 3 ) . getImm ( ) : Inst . getOperand ( 2 ) . getImm ( ) ; const signed Lsb = ( Opc == LoongArch :: BSTRINS_W || Opc == LoongArch :: BSTRINS_D ) ? Inst . getOperand ( 4 ) . getImm ( ) : Inst . getOperand ( 3 ) . getImm ( ) ; if ( Msb < Lsb ) return Match_RequiresMsbNotLessThanLsb ; return Match_Success ; } } return Match_Success ; } </s>

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


<s> bool AMDGPUCodeGenPrepare :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; const AMDGPUTargetMachine & TM = TPC -> getTM < AMDGPUTargetMachine > ( ) ; ST = & TM . getSubtarget < GCNSubtarget > ( F ) ; AC = & getAnalysis < AssumptionCacheTracker > ( ) . getAssumptionCache ( F ) ; DA = & getAnalysis < LegacyDivergenceAnalysis > ( ) ; auto * DTWP = getAnalysisIfAvailable < DominatorTreeWrapperPass > ( ) ; DT = DTWP ? & DTWP -> getDomTree ( ) : nullptr ; HasUnsafeFPMath = hasUnsafeFPMath ( F ) ; AMDGPU :: SIModeRegisterDefaults Mode ( F ) ; HasFP32Denormals = Mode . allFP32Denormals ( ) ; bool MadeChange = false ; Function :: iterator NextBB ; for ( Function :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; FI = NextBB ) { BasicBlock * BB = & * FI ; NextBB = std :: next ( FI ) ; BasicBlock :: iterator Next ; for ( BasicBlock :: iterator I = BB -> begin ( ) , E = BB -> end ( ) ; I != E ; I = Next ) { Next = std :: next ( I ) ; MadeChange |= visit ( * I ) ; if ( Next != E ) { BasicBlock * NextInstBB = Next -> getParent ( ) ; if ( NextInstBB != BB ) { BB = NextInstBB ; E = BB -> end ( ) ; FE = F . end ( ) ; } } } } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU::SIModeRegisterDefaults


<s> static rtx gen_safe_HIGH64 ( rtx dest , HOST_WIDE_INT val ) { return gen_rtx_SET ( VOIDmode , dest , GEN_INT ( val & ~ ( HOST_WIDE_INT ) 0x3ff ) ) ; } </s>

The optimizer is not to assume anything about exactly which bits are set for a HIGH , they are unspecified . Unfortunately this leads to many missed optimizations during CSE . We mask out the non-HIGH bits , and matches a plain movdi , to alleviate this problem .


<s> virtual const Z80Subtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool Cpu0TargetObjectFile :: IsGlobalInSmallSection ( const GlobalObject * GO , const TargetMachine & TM , SectionKind Kind ) const { return IsGlobalInSmallSectionImpl ( GO , TM ) && ( Kind . isData ( ) || Kind . isBSS ( ) || Kind . isCommon ( ) || Kind . isReadOnly ( ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> Reloc :: Model getRelocationModel ( ) const { return RM ; } </s>

Returns the code generation relocation model .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < MachinePostDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
void
AVRDAGToDAGISel
::
Select
(
SDNode
*
N
)
{
if
(
N
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
N
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
N
->
setNodeId
(
1
)
;
return
;
}
if
(
trySelect
(
N
)
)
return
;
SelectCode
(
N
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> MCInst const * getDesc ( ) const { return ( ID ) ; } </s>

Returns the target instruction descriptor of this MachineInstr .


<s> void TriCoreMCInstLower :: Initialize ( Mangler * M , MCContext * C ) { Mang = M ; Ctx = C ; } </s>

This method must be called before any actual lowering is done .


<s> bool X86TargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { auto Attr = CI -> getParent ( ) -> getParent ( ) -> getFnAttribute ( "disable-tail-calls" ) ; if ( ! CI -> isTailCall ( ) || Attr . getValueAsString ( ) == "true" ) return false ; CallSite CS ( CI ) ; CallingConv :: ID CalleeCC = CS . getCallingConv ( ) ; if ( ! mayTailCallThisCC ( CalleeCC ) ) return false ; return true ; } </s>

Return true if the target may be able emit the call instruction as a tail call .