<s> bool aarch64_expand_sve_vec_cmp_float ( rtx target , rtx_code code , rtx op0 , rtx op1 , bool can_invert_p ) { machine_mode pred_mode = GET_MODE ( target ) ; machine_mode data_mode = GET_MODE ( op0 ) ; rtx ptrue = force_reg ( pred_mode , CONSTM1_RTX ( pred_mode ) ) ; switch ( code ) { case UNORDERED : op1 = force_reg ( data_mode , op1 ) ; case LT : case LE : case GT : case GE : case EQ : case NE : { rtx cond = gen_rtx_fmt_ee ( code , pred_mode , op0 , op1 ) ; aarch64_emit_sve_ptrue_op ( target , ptrue , cond ) ; return false ; } case LTGT : aarch64_emit_sve_or_conds ( target , LT , GT , ptrue , op0 , op1 ) ; return false ; case UNEQ : if ( ! flag_trapping_math ) { op1 = force_reg ( data_mode , op1 ) ; aarch64_emit_sve_or_conds ( target , UNORDERED , EQ , ptrue , op0 , op1 ) ; return false ; } case UNLT : case UNLE : case UNGT : case UNGE : if ( flag_trapping_math ) { rtx ordered = gen_reg_rtx ( pred_mode ) ; op1 = force_reg ( data_mode , op1 ) ; aarch64_emit_sve_inverted_cond ( ordered , ptrue , UNORDERED , op0 , op1 ) ; if ( code == UNEQ ) code = NE ; else code = reverse_condition_maybe_unordered ( code ) ; if ( can_invert_p ) { aarch64_emit_sve_predicated_cond ( target , code , ordered , op0 , op1 ) ; return true ; } rtx tmp = gen_reg_rtx ( pred_mode ) ; aarch64_emit_sve_predicated_cond ( tmp , code , ordered , op0 , op1 ) ; aarch64_emit_unop ( target , one_cmpl_optab , tmp ) ; return false ; } break ; case ORDERED : op1 = force_reg ( data_mode , op1 ) ; break ; default : gcc_unreachable ( ) ; } code = reverse_condition_maybe_unordered ( code ) ; if ( can_invert_p ) { rtx cond = gen_rtx_fmt_ee ( code , pred_mode , op0 , op1 ) ; aarch64_emit_sve_ptrue_op ( target , ptrue , cond ) ; return true ; } aarch64_emit_sve_inverted_cond ( target , ptrue , code , op0 , op1 ) ; return false ; } </s>

Expand an SVE floating-point comparison : TARGET = CODE ( OP0 , OP1 ) If CAN_INVERT_P is true , the caller can also handle inverted results ; return true if the result is in fact inverted .


<s> static void x86_64_elf_select_section ( tree decl , int reloc , unsigned HOST_WIDE_INT align ) { if ( ( ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC ) && ix86_in_large_data_p ( decl ) ) { const char * sname = NULL ; unsigned int flags = SECTION_WRITE ; switch ( categorize_decl_for_section ( decl , reloc , flag_pic ) ) { case SECCAT_DATA : sname = ".ldata" ; break ; case SECCAT_DATA_REL : sname = ".ldata.rel" ; break ; case SECCAT_DATA_REL_LOCAL : sname = ".ldata.rel.local" ; break ; case SECCAT_DATA_REL_RO : sname = ".ldata.rel.ro" ; break ; case SECCAT_DATA_REL_RO_LOCAL : sname = ".ldata.rel.ro.local" ; break ; case SECCAT_BSS : sname = ".lbss" ; flags |= SECTION_BSS ; break ; case SECCAT_RODATA : case SECCAT_RODATA_MERGE_STR : case SECCAT_RODATA_MERGE_STR_INIT : case SECCAT_RODATA_MERGE_CONST : sname = ".lrodata" ; flags = 0 ; break ; case SECCAT_SRODATA : case SECCAT_SDATA : case SECCAT_SBSS : gcc_unreachable ( ) ; case SECCAT_TEXT : case SECCAT_TDATA : case SECCAT_TBSS : break ; } if ( sname ) { if ( ! DECL_P ( decl ) ) named_section_flags ( sname , flags ) ; else named_section ( decl , sname , reloc ) ; return ; } } default_elf_select_section ( decl , reloc , align ) ; } </s>

switch to the appropriate section for output of DECL . DECL is either a ` VAR_DECL ' node or a constant of some sort . RELOC indicates whether forming the initial value of DECL requires link-time relocations .


<s> const Cpu0TargetLowering * Cpu0TargetLowering :: create ( const Cpu0TargetMachine & TM , const Cpu0Subtarget & STI ) { return createCpu0SETargetLowering ( TM , STI ) ; } </s>


<s> tree gimple_folder :: force_vector ( gimple_seq & stmts , tree vectype , tree value ) { if ( ! VECTOR_TYPE_P ( TREE_TYPE ( value ) ) ) value = gimple_build_vector_from_val ( & stmts , vectype , value ) ; return value ; } </s>

VALUE might be a vector of type VECTYPE or a single scalar element . Duplicate it into a vector of type VECTYPE in the latter case , adding any new statements to STMTS .


<s>
char
*
output_call
(
rtx
insn
,
rtx
*
operands
,
int
dest_operand_number
,
int
cookie_operand_number
)
{
static
char
buf
[
256
]
;
if
(
GET_CODE
(
operands
[
dest_operand_number
]
)
==
SYMBOL_REF
&&
(
INTVAL
(
operands
[
cookie_operand_number
]
)
&
CALL_LONG
)
)
{
tree
labelname
;
tree
funname
=
get_identifier
(
XSTR
(
operands
[
dest_operand_number
]
,
0
)
)
;
if
(
no_previous_def
(
funname
)
)
{
int
line_number
=
0
;
rtx
label_rtx
=
gen_label_rtx
(
)
;
char
*
label_buf
,
temp_buf
[
256
]
;
ASM_GENERATE_INTERNAL_LABEL
(
temp_buf
,
"L"
,
CODE_LABEL_NUMBER
(
label_rtx
)
)
;
label_buf
=
temp_buf
[
0
]
==
'*'
temp_buf
+
1
:
temp_buf
;
labelname
=
get_identifier
(
label_buf
)
;
for
(
;
insn
&&
GET_CODE
(
insn
)
!=
NOTE
;
insn
=
PREV_INSN
(
insn
)
)
;
if
(
insn
)
line_number
=
NOTE_LINE_NUMBER
(
insn
)
;
add_compiler_branch_island
(
labelname
,
funname
,
line_number
)
;
}
else
labelname
=
get_prev_label
(
funname
)
;
sprintf
(
buf
,
"jbsr %%z%d,%.246s"
,
dest_operand_number
,
IDENTIFIER_POINTER
(
labelname
)
)
;
}
else
sprintf
(
buf
,
"bl %%z%d"
,
dest_operand_number
)
;
return
buf
;
}
</s>

INSN is either a function call or a millicode call . It may have an unconditional jump in its delay slot . CALL_DEST is the routine we are calling .


<s> void PPC64LinuxTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; } </s>

This method must be called before any actual lowering is done .


Return a mask of call-preserved registers for the given calling convention on the current function .


<s> PPCTargetLowering :: ConstraintType PPCTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'b' : case 'r' : case 'f' : case 'd' : case 'v' : case 'y' : return C_RegisterClass ; case 'Z' : return C_Memory ; } } else if ( Constraint == "wc" ) { return C_RegisterClass ; } else if ( Constraint == "wa" || Constraint == "wd" || Constraint == "wf" || Constraint == "ws" || Constraint == "wi" ) { return C_RegisterClass ; } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .

PowerPC PPC PPC 1 0 "wc" "wa" "wd" "wf" "ws" "wi"


<s> bool direct_return ( void ) { return ( TARGET_ABI_OSF && reload_completed && cfun -> machine -> frame_size == 0 ) ; } </s>

Return non-zero if this function is known to have a null epilogue .


<s> void MipsAsmPrinter :: emitInlineAsmEnd ( const MCSubtargetInfo & StartInfo , const MCSubtargetInfo * EndInfo ) const { OutStreamer -> AddBlankLine ( ) ; getTargetStreamer ( ) . emitDirectiveSetPop ( ) ; } </s>

Let the target do anything it needs to do after emitting inlineasm .


<s> bool LEGFrameLowering :: hasFP ( const MachineFunction & MF ) const { return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


"%qE attribute requires a string constant argument"

Part of the low level implementation of DEC Ada pragma Common_Object which enables the shared use of variables stored in overlaid linker areas corresponding to the use of Fortran COMMON .


<s> StringRef getPassName ( ) const override { return X86_REGISTER_ALLOCATOR_PASS_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasV4TOps ( false ) , HasV5TOps ( false ) , HasV5TEOps ( false ) , HasV6Ops ( false ) , HasV6T2Ops ( false ) , HasV7Ops ( false ) , HasVFPv2 ( false ) , HasVFPv3 ( false ) , HasNEON ( false ) , UseNEONForSinglePrecisionFP ( false ) , SlowFPVMLx ( false ) , HasVMLxForwarding ( false ) , SlowFPBrcc ( false ) , InThumbMode ( false ) , InNaClMode ( false ) , HasThumb2 ( false ) , IsMClass ( false ) , NoARM ( false ) , PostRAScheduler ( false ) , IsR9Reserved ( ReserveR9 ) , UseMovt ( false ) , SupportsTailCall ( false ) , HasFP16 ( false ) , HasD16 ( false ) , HasHardwareDivide ( false ) , HasT2ExtractPack ( false ) , HasDataBarrier ( false ) , Pref32BitThumb ( false ) , AvoidCPSRPartialUpdate ( false ) , HasMPExtension ( false ) , FPOnlySP ( false ) , AllowsUnalignedMem ( false ) , Thumb2DSP ( false ) , stackAlignment ( 4 ) , CPUString ( CPU ) , TargetTriple ( TT ) , TargetABI ( ARM_ABI_APCS ) { if ( CPUString . empty ( ) ) CPUString = "generic" ; std :: string ArchFS = ARM_MC :: ParseARMTriple ( TT ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ArchFS + "," + FS ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; if ( ! HasV6T2Ops && hasThumb2 ( ) ) HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; computeIssueWidth ( ) ; if ( TT . find ( "eabi" ) != std :: string :: npos ) TargetABI = ARM_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = 8 ; if ( ! isTargetDarwin ( ) ) UseMovt = hasV6T2Ops ( ) ; else { IsR9Reserved = ReserveR9 | ! HasV6Ops ; UseMovt = DarwinUseMOVT && hasV6T2Ops ( ) ; const Triple & T = getTargetTriple ( ) ; SupportsTailCall = T . getOS ( ) == Triple :: IOS && ! T . isOSVersionLT ( 5 , 0 ) ; } if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; if ( ! StrictAlign && hasV6Ops ( ) && isTargetDarwin ( ) ) AllowsUnalignedMem = true ; } </s>

This constructor initializes the data members to match that of the specified triple .

ARM ARM ARM ARM ARM ARM 4 ARM "generic" ARM ARM "," "eabi" ARM 8 5 0


<s>
void
Thumb1InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
assert
(
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
PseudoSourceValue
::
getFixedStack
(
FI
)
,
MachineMemOperand
::
MOStore
,
0
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tSpill
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .

ARM
ARM::tGPRRegisterClass
ARM
"Unknown regclass!"
ARM::tGPRRegisterClass
ARM
0
ARM::tSpill
0


<s>
SDValue
SystemZTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_SystemZ
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
if
(
RVLocs
[
i
]
.
isRegLoc
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
SDValue
ResValue
=
OutVals
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
SExt
)
ResValue
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
ResValue
)
;
else
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExt
)
ResValue
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
ResValue
)
;
else
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
AExt
)
ResValue
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
ResValue
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
ResValue
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static void s390_expand_cs_tdsi ( machine_mode mode , rtx btarget , rtx vtarget , rtx mem , rtx cmp , rtx new_rtx , bool is_weak ) { rtx output = vtarget ; rtx_code_label * skip_cs_label = NULL ; bool do_const_opt = false ; if ( ! register_operand ( output , mode ) ) output = gen_reg_rtx ( mode ) ; if ( TARGET_Z196 && ( mode == SImode || mode == DImode ) ) do_const_opt = ( is_weak && CONST_INT_P ( cmp ) ) ; if ( do_const_opt ) { rtx cc = gen_rtx_REG ( CCZmode , CC_REGNUM ) ; skip_cs_label = gen_label_rtx ( ) ; emit_move_insn ( btarget , const0_rtx ) ; if ( CONST_INT_P ( cmp ) && INTVAL ( cmp ) == 0 ) { rtvec lt = rtvec_alloc ( 2 ) ; RTVEC_ELT ( lt , 0 ) = gen_rtx_SET ( cc , gen_rtx_COMPARE ( CCZmode , mem , cmp ) ) ; RTVEC_ELT ( lt , 1 ) = gen_rtx_SET ( output , mem ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , lt ) ) ; } else { emit_move_insn ( output , mem ) ; emit_insn ( gen_rtx_SET ( cc , gen_rtx_COMPARE ( CCZmode , output , cmp ) ) ) ; } s390_emit_jump ( skip_cs_label , gen_rtx_NE ( VOIDmode , cc , const0_rtx ) ) ; add_reg_br_prob_note ( get_last_insn ( ) , profile_probability :: very_unlikely ( ) ) ; cmp = output ; } else cmp = force_reg ( mode , cmp ) ; new_rtx = force_reg ( mode , new_rtx ) ; s390_emit_compare_and_swap ( EQ , output , mem , cmp , new_rtx , ( do_const_opt ) ? CCZmode : CCZ1mode ) ; if ( skip_cs_label != NULL ) emit_label ( skip_cs_label ) ; if ( output != vtarget ) emit_move_insn ( vtarget , output ) ; if ( do_const_opt ) { rtx cc , cond , ite ; cc = gen_rtx_REG ( CCZmode , CC_REGNUM ) ; cond = gen_rtx_EQ ( VOIDmode , cc , const0_rtx ) ; ite = gen_rtx_IF_THEN_ELSE ( SImode , cond , const1_rtx , btarget ) ; emit_insn ( gen_rtx_SET ( btarget , ite ) ) ; } else { rtx cc , cond ; cc = gen_rtx_REG ( CCZ1mode , CC_REGNUM ) ; cond = gen_rtx_EQ ( SImode , cc , const0_rtx ) ; emit_insn ( gen_cstorecc4 ( btarget , cond , cc , const0_rtx ) ) ; } } </s>

Variant of s390_expand_cs for SI , DI and TI modes .


<s> unsigned getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info = TTI :: OK_AnyValue , TTI :: OperandValueKind Opd2Info = TTI :: OK_AnyValue , TTI :: OperandValueProperties Opd1PropInfo = TTI :: OP_None , TTI :: OperandValueProperties Opd2PropInfo = TTI :: OP_None , ArrayRef < const Value * > Args = ArrayRef < const Value * > ( ) ) { int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: MUL : case ISD :: SDIV : case ISD :: UDIV : case ISD :: UREM : return 64 * BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .

DLX ISD::MUL ISD::SDIV ISD::UDIV ISD::UREM 64


"AMDGPU Control Flow Graph structurizer Pass"


<s> void mips_set_return_address ( rtx address , rtx scratch ) { rtx slot_address ; compute_frame_size ( get_frame_size ( ) ) ; gcc_assert ( ( cfun -> machine -> frame . mask >> 31 ) & 1 ) ; slot_address = mips_add_offset ( scratch , stack_pointer_rtx , cfun -> machine -> frame . gp_sp_offset ) ; emit_move_insn ( gen_rtx_MEM ( GET_MODE ( address ) , slot_address ) , address ) ; } </s>

Emit code to change the current function 's return address to ADDRESS . SCRATCH is available as a scratch register , if needed . ADDRESS and SCRATCH are both word-mode GPRs .


<s> int size ( ) const { return Blocks . size ( ) ; } </s>

The number of name/type pairs is returned .


<s> bool isImm ( ) const override { return Kind == k_Immediate ; } </s>


<s> MachineInstr * AMDGPUInstrInfo :: convertToThreeAddress ( MachineFunction :: iterator & MFI , MachineBasicBlock :: iterator & MBBI , LiveVariables * LV ) const { return nullptr ; } </s>

convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag .


<s> static rtx frv_expand_voidbinop_builtin ( enum insn_code icode , tree call ) { rtx pat ; rtx op0 = frv_read_argument ( call , 0 ) ; rtx op1 = frv_read_argument ( call , 1 ) ; machine_mode mode0 = insn_data [ icode ] . operand [ 0 ] . mode ; rtx addr ; if ( GET_CODE ( op0 ) != MEM ) { rtx reg = op0 ; if ( ! offsettable_address_p ( 0 , mode0 , op0 ) ) { reg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( reg , op0 ) ) ; } op0 = gen_rtx_MEM ( SImode , reg ) ; } addr = XEXP ( op0 , 0 ) ; if ( ! offsettable_address_p ( 0 , mode0 , addr ) ) addr = copy_to_mode_reg ( Pmode , op0 ) ; op0 = change_address ( op0 , V4SImode , addr ) ; op1 = frv_legitimize_argument ( icode , 1 , op1 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return 0 ; } </s>

Expand builtins that take two operands , the first operand being a pointer to ints and return void .


<s> static bool m32c_modes_tieable_p ( machine_mode m1 , machine_mode m2 ) { if ( GET_MODE_SIZE ( m1 ) == GET_MODE_SIZE ( m2 ) ) return 1 ; if ( m1 == QImode || m2 == QImode ) return 0 ; return 1 ; } </s>

Implements MODES_TIEABLE_P . In general , modes are n't tieable since registers are all different sizes . However , since most modes are bigger than our registers anyway , it 's easier to implement this function that way , leaving QImode as the only unique case .


<s> void MOSPassConfig :: addPreLegalizeMachineIR ( ) { addPass ( createMOSCombiner ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before legalization .


<s> static bool arc_process_double_reg_moves ( rtx * operands ) { rtx dest = operands [ 0 ] ; rtx src = operands [ 1 ] ; enum usesDxState { none , srcDx , destDx , maxDx } ; enum usesDxState state = none ; if ( refers_to_regno_p ( 40 , 44 , src , 0 ) ) state = srcDx ; if ( refers_to_regno_p ( 40 , 44 , dest , 0 ) ) { gcc_assert ( state == none ) ; state = destDx ; } if ( state == none ) return false ; if ( state == srcDx ) { if ( TARGET_DPFP_DISABLE_LRSR ) { rtx set = gen_rtx_SET ( dest , src ) ; rtx use1 = gen_rtx_USE ( VOIDmode , const1_rtx ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set , use1 ) ) ) ; } else { rtx destHigh = simplify_gen_subreg ( SImode , dest , DFmode , TARGET_BIG_ENDIAN ? 0 : 4 ) ; rtx destLow = simplify_gen_subreg ( SImode , dest , DFmode , TARGET_BIG_ENDIAN ? 4 : 0 ) ; emit_insn ( gen_rtx_SET ( destHigh , gen_rtx_UNSPEC_VOLATILE ( Pmode , gen_rtvec ( 1 , src ) , VUNSPEC_ARC_LR_HIGH ) ) ) ; emit_insn ( gen_rtx_SET ( destLow , gen_rtx_UNSPEC_VOLATILE ( Pmode , gen_rtvec ( 1 , src ) , VUNSPEC_ARC_LR ) ) ) ; } } else if ( state == destDx ) { rtx srcHigh = simplify_gen_subreg ( SImode , src , DFmode , TARGET_BIG_ENDIAN ? 0 : 4 ) ; rtx srcLow = simplify_gen_subreg ( SImode , src , DFmode , TARGET_BIG_ENDIAN ? 4 : 0 ) ; emit_insn ( gen_dexcl_2op ( dest , srcHigh , srcLow ) ) ; } else gcc_unreachable ( ) ; return true ; } </s>

Handle DOUBLE_REGS uses . Operand 0 : destination register Operand 1 : source register


<s>
bool
AVRFrameLowering
::
spillCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
if
(
CSI
.
empty
(
)
)
{
return
false
;
}
unsigned
CalleeFrameSize
=
0
;
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
AVRSubtarget
&
STI
=
MF
.
getSubtarget
<
AVRSubtarget
>
(
)
;
const
TargetInstrInfo
&
TII
=
*
STI
.
getInstrInfo
(
)
;
AVRMachineFunctionInfo
*
AVRFI
=
MF
.
getInfo
<
AVRMachineFunctionInfo
>
(
)
;
for
(
unsigned
i
=
CSI
.
size
(
)
;
i
!=
0
;
i
)
{
unsigned
Reg
=
CSI
[
i
1
]
.
getReg
(
)
;
bool
IsNotLiveIn
=
!
MBB
.
isLiveIn
(
Reg
)
;
assert
(
TRI
->
getMinimalPhysRegClass
(
Reg
)
->
getSize
(
)
==
1
&&
"Invalid register size"
)
;
if
(
IsNotLiveIn
)
{
MBB
.
addLiveIn
(
Reg
)
;
}
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
PUSHRr
)
)
.
addReg
(
Reg
,
getKillRegState
(
IsNotLiveIn
)
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
++
CalleeFrameSize
;
}
AVRFI
->
setCalleeSavedFrameSize
(
CalleeFrameSize
)
;
return
true
;
}
</s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .

AVR
AVR
0
AVR
AVR
AVR
AVR
AVR
0
1
1
"Invalid register size"
AVR::PUSHRr
AVR


<s>
bool
SIRegisterInfo
::
eliminateSGPRToVGPRSpillFrameIndex
(
MachineBasicBlock
::
iterator
MI
,
int
FI
,
RegScavenger
*
RS
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
case
AMDGPU
::
SI_SPILL_S1024_SAVE
:
case
AMDGPU
::
SI_SPILL_S512_SAVE
:
case
AMDGPU
::
SI_SPILL_S256_SAVE
:
case
AMDGPU
::
SI_SPILL_S192_SAVE
:
case
AMDGPU
::
SI_SPILL_S160_SAVE
:
case
AMDGPU
::
SI_SPILL_S128_SAVE
:
case
AMDGPU
::
SI_SPILL_S96_SAVE
:
case
AMDGPU
::
SI_SPILL_S64_SAVE
:
case
AMDGPU
::
SI_SPILL_S32_SAVE
:
return
spillSGPR
(
MI
,
FI
,
RS
,
true
)
;
case
AMDGPU
::
SI_SPILL_S1024_RESTORE
:
case
AMDGPU
::
SI_SPILL_S512_RESTORE
:
case
AMDGPU
::
SI_SPILL_S256_RESTORE
:
case
AMDGPU
::
SI_SPILL_S192_RESTORE
:
case
AMDGPU
::
SI_SPILL_S160_RESTORE
:
case
AMDGPU
::
SI_SPILL_S128_RESTORE
:
case
AMDGPU
::
SI_SPILL_S96_RESTORE
:
case
AMDGPU
::
SI_SPILL_S64_RESTORE
:
case
AMDGPU
::
SI_SPILL_S32_RESTORE
:
return
restoreSGPR
(
MI
,
FI
,
RS
,
true
)
;
default
:
llvm_unreachable
(
"not an SGPR spill instruction"
)
;
}
}
</s>


<s> unsigned X86RegisterInfo :: findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI ) const { const MachineFunction * MF = MBB . getParent ( ) ; if ( MF -> callsEHReturn ( ) ) return 0 ; const TargetRegisterClass & AvailableRegs = * getGPRsForTailCall ( * MF ) ; if ( MBBI == MBB . end ( ) ) return 0 ; switch ( MBBI -> getOpcode ( ) ) { default : return 0 ; case TargetOpcode :: PATCHABLE_RET : case X86 :: RET : case X86 :: RETL : case X86 :: RETQ : case X86 :: RETIL : case X86 :: RETIQ : case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: TCRETURNmi64 : case X86 :: EH_RETURN : case X86 :: EH_RETURN64 : { SmallSet < uint16_t , 8 > Uses ; for ( unsigned I = 0 , E = MBBI -> getNumOperands ( ) ; I != E ; ++ I ) { MachineOperand & MO = MBBI -> getOperand ( I ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , this , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } for ( auto CS : AvailableRegs ) if ( ! Uses . count ( CS ) && CS != X86 :: RIP && CS != X86 :: RSP && CS != X86 :: ESP ) return CS ; } } return 0 ; } </s>

findDeadCallerSavedReg - Return a caller-saved register that is n't live when it reaches the `` return '' instruction .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , CM , OL ) , TargetABI ( computeTargetABI ( TT , CPU , Options ) ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , Subtarget ( TT , CPU , FS , * this , isLittle ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = Subtarget . isTargetHardFloat ( ) ? FloatABI :: Hard : FloatABI :: Soft ; if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( Subtarget . isTargetGNUAEABI ( ) ) this -> Options . EABIVersion = EABI :: GNU ; else this -> Options . EABIVersion = EABI :: EABI5 ; } } </s>


<s> ScheduleHazardRecognizer * ARMBaseInstrInfo :: CreateTargetHazardRecognizer ( const TargetMachine * TM , const ScheduleDAG * DAG ) const { if ( usePreRAHazardRecognizer ( ) ) { const InstrItineraryData * II = TM -> getInstrItineraryData ( ) ; return new ScoreboardHazardRecognizer ( II , DAG , "pre-RA-sched" ) ; } return TargetInstrInfoImpl :: CreateTargetHazardRecognizer ( TM , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .


<s> virtual const X86RegisterInfo * getRegisterInfo ( ) const { return & getInstrInfo ( ) -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void PPCAIXAsmPrinter :: emitTTypeReference ( const GlobalValue * GV , unsigned Encoding ) { if ( GV ) { MCSymbol * TypeInfoSym = TM . getSymbol ( GV ) ; MCSymbol * TOCEntry = lookUpOrCreateTOCEntry ( TypeInfoSym ) ; const MCSymbol * TOCBaseSym = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getTOCBaseSection ( ) ) -> getQualNameSymbol ( ) ; auto & Ctx = OutStreamer -> getContext ( ) ; const MCExpr * Exp = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( TOCEntry , Ctx ) , MCSymbolRefExpr :: create ( TOCBaseSym , Ctx ) , Ctx ) ; OutStreamer -> emitValue ( Exp , GetSizeOfEncodedValue ( Encoding ) ) ; } else OutStreamer -> emitIntValue ( 0 , GetSizeOfEncodedValue ( Encoding ) ) ; } </s>

Emit reference to a ttype global with a specified encoding .


<s> bool sh_legitimate_index_p ( machine_mode mode , rtx op , bool consider_sh2a , bool allow_zero ) { if ( ! CONST_INT_P ( op ) ) return false ; { const HOST_WIDE_INT offset = INTVAL ( op ) ; const int max_disp = sh_max_mov_insn_displacement ( mode , consider_sh2a ) ; const int align_mask = mov_insn_alignment_mask ( mode , consider_sh2a ) ; if ( ! allow_zero && max_disp < 1 ) return false ; return offset >= 0 && offset <= max_disp && ( offset & align_mask ) == 0 ; } } </s>

Return TRUE for a valid displacement for the REG+disp addressing with MODE .


<s> DFAPacketizer * R600InstrInfo :: CreateTargetScheduleState ( const TargetSubtargetInfo & STI ) const { const InstrItineraryData * II = STI . getInstrItineraryData ( ) ; return static_cast < const AMDGPUSubtarget & > ( STI ) . createDFAPacketizer ( II ) ; } </s>

Create machine specific model for scheduling .


<s>
void
AMDGPUAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
)
const
{
switch
(
(
unsigned
)
Fixup
.
getKind
(
)
)
{
default
:
llvm_unreachable
(
"Unknown fixup kind"
)
;
case
AMDGPU
::
fixup_si_sopp_br
:
{
uint16_t
*
Dst
=
(
uint16_t
*
)
(
Data
+
Fixup
.
getOffset
(
)
)
;
*
Dst
=
(
Value
4
)
/
4
;
break
;
}
case
AMDGPU
::
fixup_si_rodata
:
{
uint32_t
*
Dst
=
(
uint32_t
*
)
(
Data
+
Fixup
.
getOffset
(
)
)
;
*
Dst
=
Value
;
break
;
}
case
AMDGPU
::
fixup_si_end_of_text
:
{
uint32_t
*
Dst
=
(
uint32_t
*
)
(
Data
+
Fixup
.
getOffset
(
)
)
;
*
Dst
=
Value
+
4
;
break
;
}
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> const DataLayout * getDataLayout ( ) const override { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> static bool sh_legitimate_constant_p ( machine_mode mode , rtx x ) { if ( SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P ) { rtx base , offset ; split_const ( x , & base , & offset ) ; if ( GET_CODE ( base ) == SYMBOL_REF && ! offset_within_block_p ( base , INTVAL ( offset ) ) ) return false ; } if ( TARGET_FDPIC && ( SYMBOLIC_CONST_P ( x ) || ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && SYMBOLIC_CONST_P ( XEXP ( XEXP ( x , 0 ) , 0 ) ) ) ) ) return false ; if ( TARGET_SHMEDIA && ( ( mode != DFmode && GET_MODE_CLASS ( mode ) != MODE_VECTOR_FLOAT ) || x == CONST0_RTX ( mode ) || ! TARGET_SHMEDIA_FPU || TARGET_SHMEDIA64 ) ) return false ; return GET_CODE ( x ) != CONST_DOUBLE || mode == DFmode || mode == SFmode || mode == DImode || GET_MODE ( x ) == VOIDmode ; } </s>


<s> void notice_update_cc ( rtx body , rtx_insn * insn ) { rtx set ; switch ( get_attr_cc ( insn ) ) { case CC_NONE : break ; case CC_NONE_0HIT : if ( cc_status . value1 != 0 && reg_overlap_mentioned_p ( recog_data . operand [ 0 ] , cc_status . value1 ) ) cc_status . value1 = 0 ; if ( cc_status . value2 != 0 && reg_overlap_mentioned_p ( recog_data . operand [ 0 ] , cc_status . value2 ) ) cc_status . value2 = 0 ; break ; case CC_SET_ZN : CC_STATUS_INIT ; cc_status . flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY ; set = single_set ( insn ) ; cc_status . value1 = SET_SRC ( set ) ; if ( SET_DEST ( set ) != cc0_rtx ) cc_status . value2 = SET_DEST ( set ) ; break ; case CC_SET_ZNV : CC_STATUS_INIT ; cc_status . flags |= CC_NO_CARRY ; set = single_set ( insn ) ; cc_status . value1 = SET_SRC ( set ) ; if ( SET_DEST ( set ) != cc0_rtx ) { if ( GET_CODE ( SET_DEST ( set ) ) == STRICT_LOW_PART ) cc_status . value2 = XEXP ( SET_DEST ( set ) , 0 ) ; else cc_status . value2 = SET_DEST ( set ) ; } break ; case CC_COMPARE : CC_STATUS_INIT ; cc_status . value1 = SET_SRC ( body ) ; break ; case CC_CLOBBER : CC_STATUS_INIT ; break ; } } </s>

On the 68000 , all the insns to store in an address register fail to set the cc 's . However , in some cases these instructions can make it possibly invalid to use the saved cc 's . In those cases we clear out some or all of the saved cc 's so they wo n't be used .


<s> bool BPFAdjustOpt :: runOnModule ( Module & M ) { return BPFAdjustOptImpl ( & M ) . run ( ) ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> static rtx bfin_load_pic_reg ( rtx dest ) { rtx addr ; cgraph_node * local_info_node = cgraph_node :: local_info_node ( current_function_decl ) ; if ( local_info_node && local_info_node -> local ) return pic_offset_table_rtx ; if ( OPTION_SET_P ( bfin_library_id ) ) addr = plus_constant ( Pmode , pic_offset_table_rtx , - 4 - bfin_library_id * 4 ) ; else addr = gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , const0_rtx ) , UNSPEC_LIBRARY_OFFSET ) ) ; emit_insn ( gen_movsi ( dest , gen_rtx_MEM ( Pmode , addr ) ) ) ; return dest ; } </s>

Used while emitting the prologue to generate code to load the correct value into the PIC register , which is passed in DEST .


<s> SDValue AArch64SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; ConstantSDNode * SizeValue = dyn_cast < ConstantSDNode > ( Size ) ; const char * bzeroEntry = ( V && V -> isNullValue ( ) ) ? Subtarget -> getBZeroEntry ( ) : nullptr ; if ( bzeroEntry && ( ! SizeValue || SizeValue -> getZExtValue ( ) > 256 ) ) { const AArch64TargetLowering & TLI = * static_cast < const AArch64TargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; EVT IntPtr = TLI . getPointerTy ( ) ; Type * IntPtrTy = getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroEntry , IntPtr ) , & Args , 0 ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memset .


<s>
bool
PPCInstrInfo
::
isReallyTriviallyReMaterializable
(
const
MachineInstr
&
MI
,
AliasAnalysis
*
AA
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown rematerializable operation!"
)
;
break
;
case
PPC
::
LI
:
case
PPC
::
LI8
:
case
PPC
::
LIS
:
case
PPC
::
LIS8
:
case
PPC
::
ADDIStocHA
:
case
PPC
::
ADDIStocHA8
:
case
PPC
::
ADDItocL
:
case
PPC
::
LOAD_STACK_GUARD
:
case
PPC
::
XXLXORz
:
case
PPC
::
XXLXORspz
:
case
PPC
::
XXLXORdpz
:
case
PPC
::
XXLEQVOnes
:
case
PPC
::
V_SET0B
:
case
PPC
::
V_SET0H
:
case
PPC
::
V_SET0
:
case
PPC
::
V_SETALLONESB
:
case
PPC
::
V_SETALLONESH
:
case
PPC
::
V_SETALLONES
:
case
PPC
::
CRSET
:
case
PPC
::
CRUNSET
:
case
PPC
::
XXSETACCZ
:
return
true
;
}
return
false
;
}
</s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> bool MOSAsmBackend :: mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const { return visitRelaxableOperand ( Inst , STI , [ ] ( const MCOperand & Operand , unsigned RelaxTo , bool BankRelax ) { return Operand . isExpr ( ) ; } ) ; } </s>

Check whether the given instruction may need relaxation .


<s> static bool is_power9_pairable_vec_type ( enum attr_type type ) { switch ( type ) { case TYPE_VECSIMPLE : case TYPE_VECCOMPLEX : case TYPE_VECDIV : case TYPE_VECCMP : case TYPE_VECPERM : case TYPE_VECFLOAT : case TYPE_VECFDIV : case TYPE_VECDOUBLE : return true ; default : break ; } return false ; } </s>

Return whether TYPE is a Power9 pairable vector instruction type .


<s> static bool visium_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { return ( AGGREGATE_TYPE_P ( type ) || TREE_CODE ( type ) == VECTOR_TYPE ) ; } </s>

Specify whether to return the return value in memory .


<s> static ArrayRef < MCPhysReg > getAllSGPR128 ( const MachineFunction & MF , const SIRegisterInfo * TRI ) { return makeArrayRef ( AMDGPU :: SGPR_128RegClass . begin ( ) , TRI -> getMaxNumSGPRs ( MF ) / 4 ) ; } </s>

Return all SGPR128 which satisfy the waves per execution unit requirement of the subtarget .


<s> EVT RISCVTargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return getPointerTy ( DL ) ; if ( Subtarget . hasStdExtV ( ) ) return MVT :: getVectorVT ( MVT :: i1 , VT . getVectorElementCount ( ) ) ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> static section * loongarch_function_rodata_section ( tree decl , bool ) { return default_function_rodata_section ( decl , false ) ; } </s>

Implement TARGET_ASM_FUNCTION_RODATA_SECTION . The complication here is that jump tables will use absolute addresses , and should therefore not be included in the read-only part of a DSO . Handle such cases by selecting a normal data section instead of a read-only one . The logic apes that in default_function_rodata_section .


"MMIX Internal: %s is not a shiftable int"

Print operator suitable for doing something with a shiftable wyde . The type of operator is passed as an asm output modifier .


<s> unsigned getMaxNumElements ( ElementCount VF ) const { if ( ! VF . isScalable ( ) ) return VF . getFixedValue ( ) ; return VF . getKnownMinValue ( ) * ST -> getVScaleForTuning ( ) ; } </s>

Try to return an estimate cost factor that can be used as a multiplier when scalarizing an operation for a vector with ElementCount VF .


<s> static void s390_free_pool ( struct constant_pool * pool ) { struct constant * c , * next ; size_t i ; for ( i = 0 ; i < NR_C_MODES ; i ++ ) for ( c = pool -> constants [ i ] ; c ; c = next ) { next = c -> next ; free ( c ) ; } for ( c = pool -> execute ; c ; c = next ) { next = c -> next ; free ( c ) ; } BITMAP_FREE ( pool -> insns ) ; free ( pool ) ; } </s>


<s> bool RISCVTargetLowering :: isCheapToSpeculateCttz ( ) const { return Subtarget . hasStdExtZbb ( ) ; } </s>

Return true if it is cheap to speculate a call to intrinsic cttz .


"emitting conditional microcode insn %s\t[%s] #%d"

Define FINAL_PRESCAN_INSN if some processing needs to be done before outputting the assembler code . On the PowerPC , we remember if the current insn is a prefixed insn where we need to emit a ' p ' before the insn . In addition , if the insn is part of a PC-relative reference to an external label optimization , this is recorded also .


<s>
bool
SIShrinkInstructions
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
const
SIInstrInfo
*
TII
=
static_cast
<
const
SIInstrInfo
*
>
(
MF
.
getTarget
(
)
.
getInstrInfo
(
)
)
;
const
SIRegisterInfo
&
TRI
=
TII
->
getRegisterInfo
(
)
;
std
::
vector
<
unsigned
>
I1Defs
;
for
(
MachineFunction
::
iterator
BI
=
MF
.
begin
(
)
,
BE
=
MF
.
end
(
)
;
BI
!=
BE
;
++
BI
)
{
MachineBasicBlock
&
MBB
=
*
BI
;
MachineBasicBlock
::
iterator
I
,
Next
;
for
(
I
=
MBB
.
begin
(
)
;
I
!=
MBB
.
end
(
)
;
I
=
Next
)
{
Next
=
std
::
next
(
I
)
;
MachineInstr
&
MI
=
*
I
;
if
(
!
TII
->
hasVALU32BitEncoding
(
MI
.
getOpcode
(
)
)
)
continue
;
if
(
!
canShrink
(
MI
,
TII
,
TRI
,
MRI
)
)
{
if
(
!
MI
.
isCommutable
(
)
||
!
TII
->
commuteInstruction
(
&
MI
)
||
!
canShrink
(
MI
,
TII
,
TRI
,
MRI
)
)
continue
;
}
int
Op32
=
AMDGPU
::
getVOPe32
(
MI
.
getOpcode
(
)
)
;
if
(
Op32
==
1
)
continue
;
if
(
TII
->
isVOPC
(
Op32
)
)
{
unsigned
DstReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
if
(
TargetRegisterInfo
::
isVirtualRegister
(
DstReg
)
)
{
MRI
.
setRegAllocationHint
(
MI
.
getOperand
(
0
)
.
getReg
(
)
,
0
,
AMDGPU
::
VCC
)
;
continue
;
}
if
(
DstReg
!=
AMDGPU
::
VCC
)
continue
;
}
DEBUG
(
dbgs
(
)
<<
"Shrinking "
;
MI
.
dump
(
)
;
dbgs
(
)
<<
"\n"
;
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
I
,
MI
.
getDebugLoc
(
)
,
TII
->
get
(
Op32
)
)
;
MIB
.
addOperand
(
MI
.
getOperand
(
0
)
)
;
MIB
.
addOperand
(
*
TII
->
getNamedOperand
(
MI
,
AMDGPU
::
OpName
::
src0
)
)
;
const
MachineOperand
*
Src1
=
TII
->
getNamedOperand
(
MI
,
AMDGPU
::
OpName
::
src1
)
;
if
(
Src1
)
MIB
.
addOperand
(
*
Src1
)
;
for
(
const
MachineOperand
&
MO
:
MI
.
implicit_operands
(
)
)
MIB
.
addOperand
(
MO
)
;
DEBUG
(
dbgs
(
)
<<
"e32 MI = "
;
MI
.
dump
(
)
;
dbgs
(
)
<<
"\n"
;
)
;
++
NumInstructionsShrunk
;
MI
.
eraseFromParent
(
)
;
}
}
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s>
SDValue
SystemZTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
unsigned
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
isVarArg
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .

SystemZ
SystemZ
ISD::InputArg
"Unsupported calling convention"


<s>
const
char
*
output_jump_label_table
(
void
)
{
if
(
pool_size
)
{
fprintf
(
asm_out_file
,
"\t.align 2\n"
)
;
for
(
int
i
=
0
;
i
<
pool_size
;
i
++
)
{
pool_node
*
p
=
&
pool_vector
[
i
]
;
(
*
targetm
.
asm_out
.
internal_label
)
(
asm_out_file
,
"L"
,
CODE_LABEL_NUMBER
(
p
->
label
)
)
;
output_asm_insn
(
".long	%O0"
,
&
p
->
value
)
;
}
pool_size
=
0
;
}
return
""
;
}
</s>

Dump out any constants accumulated in the final pass . These will only be labels .


<s> void SPIRVPassConfig :: addPreLegalizeMachineIR ( ) { addPass ( createSPIRVPreLegalizerPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before legalization .


<s> outliner :: InstrType RISCVInstrInfo :: getOutliningType ( MachineBasicBlock :: iterator & MBBI , unsigned Flags ) const { MachineInstr & MI = * MBBI ; MachineBasicBlock * MBB = MI . getParent ( ) ; const TargetRegisterInfo * TRI = MBB -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; if ( MI . isPosition ( ) ) { if ( MI . isCFIInstruction ( ) ) return MI . getMF ( ) -> getFunction ( ) . needsUnwindTableEntry ( ) ? outliner :: InstrType :: Illegal : outliner :: InstrType :: Invisible ; return outliner :: InstrType :: Illegal ; } if ( MI . isInlineAsm ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . isTerminator ( ) && ! MBB -> succ_empty ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . isReturn ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . modifiesRegister ( RISCV :: X5 , TRI ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( RISCV :: X5 ) ) return outliner :: InstrType :: Illegal ; for ( const auto & MO : MI . operands ( ) ) if ( MO . isMBB ( ) || MO . isBlockAddress ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . isMetaInstruction ( ) ) return outliner :: InstrType :: Invisible ; return outliner :: InstrType :: Legal ; } </s>

Returns how or if MIT should be outlined .


<s>
bool
AArch64MCInstLower
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
const
{
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
)
return
false
;
MCOp
=
MCOperand
::
createReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_RegisterMask
:
return
false
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
createImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
createExpr
(
MCSymbolRefExpr
::
create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
Ctx
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
LowerSymbolOperand
(
MO
,
GetGlobalAddressSymbol
(
MO
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
LowerSymbolOperand
(
MO
,
GetExternalSymbolSymbol
(
MO
)
)
;
break
;
case
MachineOperand
::
MO_MCSymbol
:
MCOp
=
LowerSymbolOperand
(
MO
,
MO
.
getMCSymbol
(
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
MCOp
=
LowerSymbolOperand
(
MO
,
Printer
.
GetJTISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
MCOp
=
LowerSymbolOperand
(
MO
,
Printer
.
GetCPISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_BlockAddress
:
MCOp
=
LowerSymbolOperand
(
MO
,
Printer
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
)
;
break
;
}
return
true
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> bool isThumb ( ) const { return STI . getFeatureBits ( ) [ ARM :: ModeThumb ] ; } </s>

Tests whether the target is Thumb ( little and big endian ) .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> size_type size ( ) const { return V . size ( ) ; } </s>

The number of name/type pairs is returned .


<s> bool arc_legitimate_constant_p ( machine_mode mode , rtx x ) { if ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) ) return false ; if ( ! flag_pic && mode != Pmode ) return true ; switch ( GET_CODE ( x ) ) { case CONST : x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == PLUS ) { if ( flag_pic ? GET_CODE ( XEXP ( x , 1 ) ) != CONST_INT : ! arc_legitimate_constant_p ( mode , XEXP ( x , 1 ) ) ) return false ; x = XEXP ( x , 0 ) ; } if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , 1 ) ) { case ARC_UNSPEC_PLT : case ARC_UNSPEC_GOTOFF : case ARC_UNSPEC_GOTOFFPC : case ARC_UNSPEC_GOT : case UNSPEC_TLS_GD : case UNSPEC_TLS_IE : case UNSPEC_TLS_OFF : return true ; default : gcc_unreachable ( ) ; } if ( arc_raw_symbolic_reference_mentioned_p ( x , false ) ) return false ; break ; case SYMBOL_REF : if ( SYMBOL_REF_TLS_MODEL ( x ) ) return false ; case LABEL_REF : if ( flag_pic ) return false ; default : break ; } return true ; } </s>

Determine if a given RTX is a valid constant . We already know this satisfies CONSTANT_P .


<s> bool ARMTargetLowering :: isUsedByReturnOnly ( SDNode * N ) const { if ( N -> getNumValues ( ) != 1 ) return false ; if ( ! N -> hasNUsesOfValue ( 1 , 0 ) ) return false ; unsigned NumCopies = 0 ; SDNode * Copies [ 2 ] = { 0 , 0 } ; SDNode * Use = * N -> use_begin ( ) ; if ( Use -> getOpcode ( ) == ISD :: CopyToReg ) { Copies [ NumCopies ++ ] = Use ; } else if ( Use -> getOpcode ( ) == ARMISD :: VMOVRRD ) { for ( SDNode :: use_iterator UI = Use -> use_begin ( ) , UE = Use -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != ISD :: CopyToReg ) return false ; Copies [ UI . getUse ( ) . getResNo ( ) ] = * UI ; ++ NumCopies ; } } else if ( Use -> getOpcode ( ) == ISD :: BITCAST ) { if ( ! Use -> hasNUsesOfValue ( 1 , 0 ) ) return false ; Use = * Use -> use_begin ( ) ; if ( Use -> getOpcode ( ) != ISD :: CopyToReg || ! Use -> hasNUsesOfValue ( 1 , 0 ) ) return false ; Copies [ NumCopies ++ ] = Use ; } else { return false ; } if ( NumCopies != 1 && NumCopies != 2 ) return false ; bool HasRet = false ; for ( unsigned i = 0 ; i < NumCopies ; ++ i ) { SDNode * Copy = Copies [ i ] ; for ( SDNode :: use_iterator UI = Copy -> use_begin ( ) , UE = Copy -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) == ISD :: CopyToReg ) { SDNode * Use = * UI ; if ( Use == Copies [ 0 ] || ( ( NumCopies == 2 ) && ( Use == Copies [ 1 ] ) ) ) continue ; return false ; } if ( UI -> getOpcode ( ) != ARMISD :: RET_FLAG ) return false ; HasRet = true ; } } return HasRet ; } </s>

Return true if result of the specified node is used by a return node only .


<s> bool Thumb2ITBlockPass :: runOnMachineFunction ( MachineFunction & Fn ) { const TargetMachine & TM = Fn . getTarget ( ) ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( TM . getInstrInfo ( ) ) ; TRI = TM . getRegisterInfo ( ) ; hasV8Ops = TM . getSubtarget < ARMSubtarget > ( ) . hasV8Ops ( ) ; if ( ! AFI -> isThumbFunction ( ) ) return false ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ) { MachineBasicBlock & MBB = * MFI ; ++ MFI ; Modified |= InsertITInstructions ( MBB ) ; } if ( Modified ) AFI -> setHasITBlocks ( true ) ; return Modified ; } </s>


<s> void Cpu0TargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s> unsigned SPUInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case SPU :: STQDv16i8 : case SPU :: STQDv8i16 : case SPU :: STQDv4i32 : case SPU :: STQDv4f32 : case SPU :: STQDv2f64 : case SPU :: STQDr128 : case SPU :: STQDr64 : case SPU :: STQDr32 : case SPU :: STQDr16 : case SPU :: STQDr8 : { const MachineOperand MOp1 = MI -> getOperand ( 1 ) ; const MachineOperand MOp2 = MI -> getOperand ( 2 ) ; if ( MOp1 . isImm ( ) && MOp2 . isFI ( ) ) { FrameIndex = MOp2 . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s>
static
avr_map_op_t
avr_map_decompose
(
unsigned
int
f
,
const
avr_map_op_t
*
g
,
bool
val_const_p
)
{
int
i
;
bool
val_used_p
=
0
!=
avr_map_metric
(
f
,
MAP_MASK_PREIMAGE_F
)
;
avr_map_op_t
f_ginv
=
*
g
;
unsigned
int
ginv
=
g
->
ginv
;
f_ginv
.
cost
=
1
;
for
(
i
=
7
;
i
>=
0
;
i
)
{
int
x
=
avr_map
(
f
,
i
)
;
if
(
x
<=
7
)
{
x
=
avr_map
(
ginv
,
x
)
;
if
(
x
>
7
)
return
f_ginv
;
}
f_ginv
.
map
=
(
f_ginv
.
map
<<
4
)
+
x
;
}
if
(
0
==
avr_map_metric
(
f_ginv
.
map
,
MAP_NONFIXED_0_7
)
)
{
f_ginv
.
cost
=
2
+
(
val_used_p
&&
!
val_const_p
)
;
}
else
{
rtx
xop
[
4
]
;
xop
[
0
]
=
all_regs_rtx
[
24
]
;
xop
[
1
]
=
gen_int_mode
(
f_ginv
.
map
,
SImode
)
;
xop
[
2
]
=
all_regs_rtx
[
25
]
;
xop
[
3
]
=
val_used_p
xop
[
0
]
:
const0_rtx
;
avr_out_insert_bits
(
xop
,
&
f_ginv
.
cost
)
;
f_ginv
.
cost
+=
val_const_p
&&
val_used_p
1
:
0
;
}
f_ginv
.
cost
+=
g
->
cost
;
if
(
avr_log
.
builtin
)
avr_edump
(
" %s%d=%d"
,
g
->
str
,
g
->
arg
,
f_ginv
.
cost
)
;
return
f_ginv
;
}
</s>

Try to decompose F as F = ( F o G^-1 ) o G as described above . The result is a struct representing F o G^-1 and G. If result.cost < 0 then such a decomposition does not exist .


<s> int pa_function_arg_size ( machine_mode mode , const_tree type ) { HOST_WIDE_INT size ; size = mode != BLKmode ? GET_MODE_SIZE ( mode ) : int_size_in_bytes ( type ) ; if ( size >= ( 1 << ( HOST_BITS_PER_INT - 2 ) ) ) size = 0 ; return ( int ) CEIL ( size , UNITS_PER_WORD ) ; } </s>

Figure out the size in words of the function argument .


<s> void LC3bInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static void mcore_reorg ( void ) { current_function_anonymous_args = 0 ; if ( saved_warn_return_type != - 1 ) { if ( -- saved_warn_return_type_count == 0 ) { warn_return_type = saved_warn_return_type ; saved_warn_return_type = - 1 ; } } if ( optimize == 0 ) return ; conditionalize_optimization ( ) ; } </s>

This is to handle loads from the constant pool .


<s> static unsigned int arc_compute_function_type ( struct function * fun ) { tree attr , decl = fun -> decl ; unsigned int fn_type = fun -> machine -> fn_type ; if ( fn_type != ARC_FUNCTION_UNKNOWN ) return fn_type ; if ( lookup_attribute ( "naked" , DECL_ATTRIBUTES ( decl ) ) != NULL_TREE ) fn_type |= ARC_FUNCTION_NAKED ; else fn_type |= ARC_FUNCTION_NORMAL ; attr = lookup_attribute ( "interrupt" , DECL_ATTRIBUTES ( decl ) ) ; if ( attr != NULL_TREE ) { tree value , args = TREE_VALUE ( attr ) ; gcc_assert ( list_length ( args ) == 1 ) ; value = TREE_VALUE ( args ) ; gcc_assert ( TREE_CODE ( value ) == STRING_CST ) ; if ( ! strcmp ( TREE_STRING_POINTER ( value ) , "ilink1" ) || ! strcmp ( TREE_STRING_POINTER ( value ) , "ilink" ) ) fn_type |= ARC_FUNCTION_ILINK1 ; else if ( ! strcmp ( TREE_STRING_POINTER ( value ) , "ilink2" ) ) fn_type |= ARC_FUNCTION_ILINK2 ; else if ( ! strcmp ( TREE_STRING_POINTER ( value ) , "firq" ) ) fn_type |= ARC_FUNCTION_FIRQ ; else gcc_unreachable ( ) ; } return fun -> machine -> fn_type = fn_type ; } </s>

Type of function DECL . The result is cached . To reset the cache at the end of a function , call with DECL = NULL_TREE .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addPreserved < MachineBlockFrequencyInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
void
RISCVInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MBBI
,
const
DebugLoc
&
DL
,
MCRegister
DstReg
,
MCRegister
SrcReg
,
bool
KillSrc
)
const
{
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
const
TargetRegisterInfo
*
TRI
=
MF
->
getSubtarget
(
)
.
getRegisterInfo
(
)
;
if
(
RISCV
::
GPRRegClass
.
contains
(
DstReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
RISCV
::
ADDI
)
,
DstReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
0
)
;
return
;
}
unsigned
Opc
;
if
(
RISCV
::
FPR32RegClass
.
contains
(
DstReg
,
SrcReg
)
)
Opc
=
RISCV
::
FSGNJ_S
;
else
if
(
RISCV
::
FPR64RegClass
.
contains
(
DstReg
,
SrcReg
)
)
Opc
=
RISCV
::
FSGNJ_D
;
else
if
(
RISCV
::
VRRegClass
.
contains
(
DstReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
RISCV
::
VMV1R_V
)
,
DstReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
return
;
}
else
if
(
RISCV
::
VRM2RegClass
.
contains
(
DstReg
,
SrcReg
)
||
RISCV
::
VRM4RegClass
.
contains
(
DstReg
,
SrcReg
)
||
RISCV
::
VRM8RegClass
.
contains
(
DstReg
,
SrcReg
)
)
{
unsigned
Opcode
;
if
(
RISCV
::
VRM2RegClass
.
contains
(
DstReg
,
SrcReg
)
)
Opcode
=
RISCV
::
VMV2R_V
;
else
if
(
RISCV
::
VRM4RegClass
.
contains
(
DstReg
,
SrcReg
)
)
Opcode
=
RISCV
::
VMV4R_V
;
else
Opcode
=
RISCV
::
VMV8R_V
;
DstReg
=
TRI
->
getSubReg
(
DstReg
,
RISCV
::
sub_vrm2
)
;
SrcReg
=
TRI
->
getSubReg
(
SrcReg
,
RISCV
::
sub_vrm2
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
Opcode
)
,
DstReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
return
;
}
else
{
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
Opc
)
,
DstReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> unsigned HSAILRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return HSAIL :: NoRegister ; } </s>


<s> static bool swap_top_of_ready_list ( rtx_insn * * ready , int n_ready ) { rtx_insn * top = ready [ n_ready - 1 ] ; rtx_insn * next = ready [ n_ready - 2 ] ; rtx set ; sd_iterator_def sd_it ; dep_t dep ; int clock1 = - 1 ; int clock2 = - 1 ; if ( ! TARGET_SILVERMONT && ! TARGET_INTEL ) return false ; if ( ! NONDEBUG_INSN_P ( top ) ) return false ; if ( ! NONJUMP_INSN_P ( top ) ) return false ; if ( ! NONDEBUG_INSN_P ( next ) ) return false ; if ( ! NONJUMP_INSN_P ( next ) ) return false ; set = single_set ( top ) ; if ( ! set ) return false ; set = single_set ( next ) ; if ( ! set ) return false ; if ( INSN_PRIORITY_KNOWN ( top ) && INSN_PRIORITY_KNOWN ( next ) ) { if ( INSN_PRIORITY ( top ) != INSN_PRIORITY ( next ) ) return false ; FOR_EACH_DEP ( top , SD_LIST_RES_BACK , sd_it , dep ) { rtx pro ; pro = DEP_PRO ( dep ) ; if ( ! NONDEBUG_INSN_P ( pro ) ) continue ; if ( INSN_TICK ( pro ) > clock1 ) clock1 = INSN_TICK ( pro ) ; } FOR_EACH_DEP ( next , SD_LIST_RES_BACK , sd_it , dep ) { rtx pro ; pro = DEP_PRO ( dep ) ; if ( ! NONDEBUG_INSN_P ( pro ) ) continue ; if ( INSN_TICK ( pro ) > clock2 ) clock2 = INSN_TICK ( pro ) ; } if ( clock1 == clock2 ) { enum attr_memory memory1 , memory2 ; memory1 = get_attr_memory ( top ) ; memory2 = get_attr_memory ( next ) ; if ( memory2 == MEMORY_LOAD && memory1 != MEMORY_LOAD ) return true ; } return ( bool ) ( clock2 < clock1 ) ; } return false ; } </s>

Try to find the best candidate on the top of ready list if two insns have the same priority - candidate is best if its dependees were scheduled earlier . Applied for Silvermont only . Return true if top 2 insns must be interchanged .


<s> SDValue MBlazeTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_MBlaze ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static void reshuffle_units ( basic_block loop ) { rtx_insn * head = BB_HEAD ( loop ) ; rtx_insn * tail = BB_END ( loop ) ; rtx_insn * insn ; unit_req_table reqs ; edge e ; edge_iterator ei ; bitmap_head bbs ; count_unit_reqs ( reqs , head , PREV_INSN ( tail ) ) ; merge_unit_reqs ( reqs ) ; regrename_init ( true ) ; bitmap_initialize ( & bbs , & bitmap_default_obstack ) ; FOR_EACH_EDGE ( e , ei , loop -> preds ) bitmap_set_bit ( & bbs , e -> src -> index ) ; bitmap_set_bit ( & bbs , loop -> index ) ; regrename_analyze ( & bbs ) ; for ( insn = head ; insn != NEXT_INSN ( tail ) ; insn = NEXT_INSN ( insn ) ) { enum attr_units units ; int count , side1 , side2 , req1 , req2 ; unsigned int mask1 , mask2 ; insn_rr_info * info ; if ( ! NONDEBUG_INSN_P ( insn ) ) continue ; count = get_unit_reqs ( insn , & req1 , & side1 , & req2 , & side2 ) ; if ( count == 0 ) continue ; if ( ! get_unit_operand_masks ( insn , & mask1 , & mask2 ) ) continue ; info = & insn_rr [ INSN_UID ( insn ) ] ; if ( info -> op_info == NULL ) continue ; if ( reqs [ side1 ] [ req1 ] > 1 && reqs [ side1 ] [ req1 ] > 2 * reqs [ side1 ^ 1 ] [ req1 ] ) { try_rename_operands ( head , tail , reqs , insn , info , mask1 , side1 ) ; } units = get_attr_units ( insn ) ; if ( units == UNITS_D_ADDR ) { gcc_assert ( count == 2 ) ; if ( reqs [ side2 ] [ req2 ] > 1 && reqs [ side2 ] [ req2 ] > 2 * reqs [ side2 ^ 1 ] [ req2 ] ) { try_rename_operands ( head , tail , reqs , insn , info , mask2 , side2 ) ; } } } regrename_finish ( ) ; } </s>

Find insns in LOOP which would , if shifted to the other side of the machine , reduce an imbalance in the unit reservations .


<s>
StringRef
getPassName
(
)
const
override
{
return
"NVPTX specific alloca hoisting"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool XNCMFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> virtual MachineInstr * foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const { return 0 ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s>
bool
LoongArchAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Operands
.
push_back
(
LoongArchOperand
::
createToken
(
Name
,
NameLoc
)
)
;
if
(
parseOptionalToken
(
AsmToken
::
EndOfStatement
)
)
return
false
;
if
(
parseOperand
(
Operands
,
Name
)
)
return
true
;
while
(
parseOptionalToken
(
AsmToken
::
Comma
)
)
if
(
parseOperand
(
Operands
,
Name
)
)
return
true
;
if
(
parseOptionalToken
(
AsmToken
::
EndOfStatement
)
)
return
false
;
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
getParser
(
)
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
</s>

ParseInstruction - Parse one assembly instruction .

LoongArch
LoongArch
LoongArchOperand::createToken
"unexpected token"


<s> unsigned SIRegisterInfo :: findUnusedRegister ( const MachineRegisterInfo & MRI , const TargetRegisterClass * RC ) const { for ( unsigned Reg : * RC ) if ( ! MRI . isPhysRegUsed ( Reg ) ) return Reg ; return AMDGPU :: NoRegister ; } </s>

Returns a lowest register that is not used at any point in the function .


<s> static tree pa_d_handle_target_float_abi ( void ) { const char * abi ; if ( TARGET_SOFT_FLOAT ) abi = "soft" ; else abi = "hard" ; return build_string_literal ( strlen ( abi ) + 1 , abi ) ; } </s>

Handle a call to ` __traits ( getTargetInfo , `` floatAbi '' ) ' .


<s>
void
WebAssemblyAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"EmitInstruction: "
<<
*
MI
<<
'\n'
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
WebAssembly
::
ARGUMENT_i32
:
case
WebAssembly
::
ARGUMENT_i32_S
:
case
WebAssembly
::
ARGUMENT_i64
:
case
WebAssembly
::
ARGUMENT_i64_S
:
case
WebAssembly
::
ARGUMENT_f32
:
case
WebAssembly
::
ARGUMENT_f32_S
:
case
WebAssembly
::
ARGUMENT_f64
:
case
WebAssembly
::
ARGUMENT_f64_S
:
case
WebAssembly
::
ARGUMENT_v16i8
:
case
WebAssembly
::
ARGUMENT_v16i8_S
:
case
WebAssembly
::
ARGUMENT_v8i16
:
case
WebAssembly
::
ARGUMENT_v8i16_S
:
case
WebAssembly
::
ARGUMENT_v4i32
:
case
WebAssembly
::
ARGUMENT_v4i32_S
:
case
WebAssembly
::
ARGUMENT_v2i64
:
case
WebAssembly
::
ARGUMENT_v2i64_S
:
case
WebAssembly
::
ARGUMENT_v4f32
:
case
WebAssembly
::
ARGUMENT_v4f32_S
:
case
WebAssembly
::
ARGUMENT_v2f64
:
case
WebAssembly
::
ARGUMENT_v2f64_S
:
break
;
case
WebAssembly
::
FALLTHROUGH_RETURN_I32
:
case
WebAssembly
::
FALLTHROUGH_RETURN_I32_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_I64
:
case
WebAssembly
::
FALLTHROUGH_RETURN_I64_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_F32
:
case
WebAssembly
::
FALLTHROUGH_RETURN_F32_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_F64
:
case
WebAssembly
::
FALLTHROUGH_RETURN_F64_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v16i8
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v16i8_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v8i16
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v8i16_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v4i32
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v4i32_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v2i64
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v2i64_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v4f32
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v4f32_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v2f64
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v2f64_S
:
{
if
(
isVerbose
(
)
)
{
OutStreamer
->
AddComment
(
"fallthrough-return-value"
)
;
OutStreamer
->
AddBlankLine
(
)
;
}
break
;
}
case
WebAssembly
::
FALLTHROUGH_RETURN_VOID
:
case
WebAssembly
::
FALLTHROUGH_RETURN_VOID_S
:
if
(
isVerbose
(
)
)
{
OutStreamer
->
AddComment
(
"fallthrough-return-void"
)
;
OutStreamer
->
AddBlankLine
(
)
;
}
break
;
case
WebAssembly
::
COMPILER_FENCE
:
break
;
case
WebAssembly
::
EXTRACT_EXCEPTION_I32
:
case
WebAssembly
::
EXTRACT_EXCEPTION_I32_S
:
if
(
!
WasmKeepRegisters
)
break
;
LLVM_FALLTHROUGH
;
default
:
{
WebAssemblyMCInstLower
MCInstLowering
(
OutContext
,
*
this
)
;
MCInst
TmpInst
;
MCInstLowering
.
lower
(
MI
,
TmpInst
)
;
EmitToStreamer
(
*
OutStreamer
,
TmpInst
)
;
break
;
}
}
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
MipsTargetLowering
::
getRegForInlineAsmConstraint
(
const
std
::
string
&
Constraint
,
EVT
VT
)
const
{
if
(
Constraint
.
size
(
)
==
1
)
{
switch
(
Constraint
[
0
]
)
{
case
'd'
:
case
'y'
:
case
'r'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
0U
,
Mips
::
CPURegsRegisterClass
)
;
assert
(
VT
==
MVT
::
i64
&&
"Unexpected type."
)
;
return
std
::
make_pair
(
0U
,
Mips
::
CPU64RegsRegisterClass
)
;
case
'f'
:
if
(
VT
==
MVT
::
f32
)
return
std
::
make_pair
(
0U
,
Mips
::
FGR32RegisterClass
)
;
if
(
(
VT
==
MVT
::
f64
)
&&
(
!
Subtarget
->
isSingleFloat
(
)
)
)
{
if
(
Subtarget
->
isFP64bit
(
)
)
return
std
::
make_pair
(
0U
,
Mips
::
FGR64RegisterClass
)
;
else
return
std
::
make_pair
(
0U
,
Mips
::
AFGR64RegisterClass
)
;
}
}
}
return
TargetLowering
::
getRegForInlineAsmConstraint
(
Constraint
,
VT
)
;
}
</s>

Given a physical register constraint ( e.g .


<s> static void sh_add_function_attribute ( const char * attr ) { tree id = get_identifier ( attr ) ; if ( current_function_decl ) decl_attributes ( & current_function_decl , tree_cons ( id , NULL_TREE , NULL_TREE ) , 0 ) ; else { * sh_deferred_function_attributes_tail = tree_cons ( id , NULL_TREE , * sh_deferred_function_attributes_tail ) ; sh_deferred_function_attributes_tail = & TREE_CHAIN ( * sh_deferred_function_attributes_tail ) ; } } </s>

Add ATTR to the attributes of the current function . If there is no such function , save it to be added to the attributes of the next function .


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( EnableSVEIntrinsicOpts && TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( createSVEIntrinsicOptsPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( SimplifyCFGOptions ( ) . forwardSwitchCondToPhi ( true ) . convertSwitchRangeToICmp ( true ) . convertSwitchToLookupTable ( true ) . needCanonicalLoops ( false ) . hoistCommonInsts ( true ) . sinkCommonInsts ( true ) ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; addPass ( createAArch64StackTaggingPass ( TM -> getOptLevel ( ) == CodeGenOpt :: None ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedLoadCombinePass ( ) ) ; addPass ( createInterleavedAccessPass ( ) ) ; } if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardCheckPass ( ) ) ; if ( TM -> Options . JMCInstrument ) addPass ( createJMCInstrumenterPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> void TPCLatencyResolver :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LiveIntervals > ( ) ; AU . addRequired < VirtRegMap > ( ) ; AU . addRequired < LiveRegMatrix > ( ) ; AU . setPreservesAll ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> bool HexagonEarlyIfConversion :: runOnMachineFunction ( MachineFunction & MF ) { auto & ST = MF . getSubtarget ( ) ; TII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; MFN = & MF ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MBPI = EnableHexagonBP ? & getAnalysis < MachineBranchProbabilityInfo > ( ) : nullptr ; Deleted . clear ( ) ; bool Changed = false ; for ( MachineLoopInfo :: iterator I = MLI -> begin ( ) , E = MLI -> end ( ) ; I != E ; ++ I ) Changed |= visitLoop ( * I ) ; Changed |= visitLoop ( 0 ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> void MSP430AsmPrinter :: PrintSymbolOperand ( const MachineOperand & MO , raw_ostream & O ) { uint64_t Offset = MO . getOffset ( ) ; if ( Offset ) O << '(' << Offset << '+' ; getSymbol ( MO . getGlobal ( ) ) -> print ( O , MAI ) ; if ( Offset ) O << ')' ; } </s>


<s> bool isUnconditionalBranch ( const MCInst & Inst ) const override { if ( Inst . getOpcode ( ) == ARM :: Bcc && Inst . getOperand ( 1 ) . getImm ( ) == ARMCC :: AL ) return true ; return MCInstrAnalysis :: isUnconditionalBranch ( Inst ) ; } </s>

Return true if this is a branch which always transfers control flow to some other block .


<s>
void
AArch64RegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected"
)
;
MachineInstr
&
MI
=
*
II
;
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
AArch64FrameLowering
*
TFI
=
static_cast
<
const
AArch64FrameLowering
*
>
(
MF
.
getTarget
(
)
.
getFrameLowering
(
)
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
unsigned
FrameReg
;
int
Offset
;
if
(
MI
.
isDebugValue
(
)
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
STACKMAP
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
PATCHPOINT
)
{
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
,
true
)
;
Offset
+=
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
)
;
return
;
}
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
)
;
if
(
rewriteAArch64FrameIndex
(
MI
,
FIOperandNum
,
FrameReg
,
Offset
,
TII
)
)
return
;
assert
(
(
!
RS
||
!
RS
->
isScavengingFrameIndex
(
FrameIndex
)
)
&&
"Emergency spill slot is out of reach"
)
;
unsigned
ScratchReg
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
&
AArch64
::
GPR64RegClass
)
;
emitFrameOffset
(
MBB
,
II
,
MI
.
getDebugLoc
(
)
,
ScratchReg
,
FrameReg
,
Offset
,
TII
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
ScratchReg
,
false
,
false
,
true
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> void buildLoad ( unsigned Val , const CCValAssign & VA ) { MachineMemOperand * MMO ; unsigned Addr = getStackAddress ( VA , MMO ) ; MIRBuilder . buildLoad ( Val , Addr , * MMO ) ; } </s>

Build and insert a G_LOAD instruction , while constructing the MachineMemOperand .


"Unexpected instruction for custom inserter!"

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> void Nios2PassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; } </s>


<s>
unsigned
getReg
(
)
const
override
{
assert
(
Kind
==
k_Register
&&
"Invalid access!"
)
;
return
Reg
.
Num
;
}
</s>

Returns the register associated with this edge .


<s> int HexagonInstrInfo :: getOperandLatency ( const InstrItineraryData * ItinData , const MachineInstr & DefMI , unsigned DefIdx , const MachineInstr & UseMI , unsigned UseIdx ) const { const HexagonRegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; const MachineOperand & DefMO = DefMI . getOperand ( DefIdx ) ; if ( DefMO . isReg ( ) && HRI . isPhysicalRegister ( DefMO . getReg ( ) ) ) { if ( DefMO . isImplicit ( ) ) { for ( MCSuperRegIterator SR ( DefMO . getReg ( ) , & HRI ) ; SR . isValid ( ) ; ++ SR ) { int Idx = DefMI . findRegisterDefOperandIdx ( * SR , false , false , & HRI ) ; if ( Idx != - 1 ) { DefIdx = Idx ; break ; } } } const MachineOperand & UseMO = UseMI . getOperand ( UseIdx ) ; if ( UseMO . isImplicit ( ) ) { for ( MCSuperRegIterator SR ( UseMO . getReg ( ) , & HRI ) ; SR . isValid ( ) ; ++ SR ) { int Idx = UseMI . findRegisterUseOperandIdx ( * SR , false , & HRI ) ; if ( Idx != - 1 ) { UseIdx = Idx ; break ; } } } } int Latency = TargetInstrInfo :: getOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ; if ( ! Latency ) Latency = 1 ; return Latency ; } </s>

Compute and return the use operand latency of a given pair of def and use .


<s>
bool
RISCVInsertVSETVLI
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
const
RISCVSubtarget
&
ST
=
MF
.
getSubtarget
<
RISCVSubtarget
>
(
)
;
if
(
!
ST
.
hasVInstructions
(
)
)
return
false
;
TII
=
ST
.
getInstrInfo
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
assert
(
BlockInfo
.
empty
(
)
&&
"Expect empty block infos"
)
;
BlockInfo
.
resize
(
MF
.
getNumBlockIDs
(
)
)
;
bool
HaveVectorOp
=
false
;
for
(
const
MachineBasicBlock
&
MBB
:
MF
)
HaveVectorOp
|=
computeVLVTYPEChanges
(
MBB
)
;
if
(
HaveVectorOp
)
{
for
(
const
MachineBasicBlock
&
MBB
:
MF
)
{
WorkList
.
push
(
&
MBB
)
;
BlockInfo
[
MBB
.
getNumber
(
)
]
.
InQueue
=
true
;
}
while
(
!
WorkList
.
empty
(
)
)
{
const
MachineBasicBlock
&
MBB
=
*
WorkList
.
front
(
)
;
WorkList
.
pop
(
)
;
computeIncomingVLVTYPE
(
MBB
)
;
}
for
(
MachineBasicBlock
&
MBB
:
MF
)
emitVSETVLIs
(
MBB
)
;
}
BlockInfo
.
clear
(
)
;
return
HaveVectorOp
;
}
</s>

RISCV
RISCV
RISCV
RISCV
"Expect empty block infos"


<s>
static
tree
ix86_canonical_va_list_type
(
tree
type
)
{
if
(
TARGET_64BIT
)
{
if
(
lookup_attribute
(
"ms_abi va_list"
,
TYPE_ATTRIBUTES
(
type
)
)
)
return
ms_va_list_type_node
;
if
(
(
TREE_CODE
(
type
)
==
ARRAY_TYPE
&&
integer_zerop
(
array_type_nelts
(
type
)
)
)
||
POINTER_TYPE_P
(
type
)
)
{
tree
elem_type
=
TREE_TYPE
(
type
)
;
if
(
TREE_CODE
(
elem_type
)
==
RECORD_TYPE
&&
lookup_attribute
(
"sysv_abi va_list"
,
TYPE_ATTRIBUTES
(
elem_type
)
)
)
return
sysv_va_list_type_node
;
}
return
NULL_TREE
;
}
return
std_canonical_va_list_type
(
type
)
;
}
</s>

Returns the canonical va_list type specified by TYPE . If there is no valid TYPE provided , it return NULL_TREE .

i386
"ms_abi va_list"
"sysv_abi va_list"


<s>
bool
ARMBaseInstrInfo
::
expandPostRAPseudo
(
MachineBasicBlock
::
iterator
MI
)
const
{
if
(
!
WidenVMOVS
||
!
MI
->
isCopy
(
)
)
return
false
;
unsigned
DstRegS
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
unsigned
SrcRegS
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
if
(
!
ARM
::
SPRRegClass
.
contains
(
DstRegS
,
SrcRegS
)
)
return
false
;
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
unsigned
DstRegD
=
TRI
->
getMatchingSuperReg
(
DstRegS
,
ARM
::
ssub_0
,
&
ARM
::
DPRRegClass
)
;
unsigned
SrcRegD
=
TRI
->
getMatchingSuperReg
(
SrcRegS
,
ARM
::
ssub_0
,
&
ARM
::
DPRRegClass
)
;
if
(
!
DstRegD
||
!
SrcRegD
)
return
false
;
if
(
!
MI
->
definesRegister
(
DstRegD
,
TRI
)
||
MI
->
readsRegister
(
DstRegD
,
TRI
)
)
return
false
;
if
(
MI
->
getOperand
(
0
)
.
isDead
(
)
)
return
false
;
DEBUG
(
dbgs
(
)
<<
"widening:    "
<<
*
MI
)
;
int
ImpDefIdx
=
MI
->
findRegisterDefOperandIdx
(
DstRegD
)
;
if
(
ImpDefIdx
!=
1
)
MI
->
RemoveOperand
(
ImpDefIdx
)
;
MI
->
setDesc
(
get
(
ARM
::
VMOVD
)
)
;
MI
->
getOperand
(
0
)
.
setReg
(
DstRegD
)
;
MI
->
getOperand
(
1
)
.
setReg
(
SrcRegD
)
;
AddDefaultPred
(
MachineInstrBuilder
(
MI
)
)
;
MI
->
getOperand
(
1
)
.
setIsUndef
(
)
;
MachineInstrBuilder
(
MI
)
.
addReg
(
SrcRegS
,
RegState
::
Implicit
)
;
if
(
MI
->
getOperand
(
1
)
.
isKill
(
)
)
{
MI
->
getOperand
(
1
)
.
setIsKill
(
false
)
;
MI
->
addRegisterKilled
(
SrcRegS
,
TRI
,
true
)
;
}
DEBUG
(
dbgs
(
)
<<
"replaced by: "
<<
*
MI
)
;
return
true
;
}
</s>

This function is called for all pseudo instructions that remain after register allocation .


<s> const AArch64Subtarget * AArch64TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < AArch64Subtarget > ( TargetTriple , CPU , FS , * this , isLittle ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static void replace_mov_pcrel_step1 ( rtx_insn * insn ) { rtx pattern = PATTERN ( insn ) ; rtx unspec ; rtx opnds [ 2 ] ; rtx_insn * new_insns ; gcc_assert ( GET_CODE ( pattern ) == SET ) ; opnds [ 0 ] = SET_DEST ( pattern ) ; gcc_assert ( GET_CODE ( SET_SRC ( pattern ) ) == CONST ) ; unspec = XEXP ( SET_SRC ( pattern ) , 0 ) ; gcc_assert ( GET_CODE ( unspec ) == UNSPEC ) ; gcc_assert ( XINT ( unspec , 1 ) == UNSPEC_HW1_LAST_PCREL ) ; opnds [ 1 ] = XVECEXP ( unspec , 0 , 0 ) ; if ( GET_CODE ( opnds [ 1 ] ) != SYMBOL_REF ) return ; start_sequence ( ) ; if ( flag_pic != 1 ) { if ( TARGET_32BIT ) emit_insn ( gen_mov_got32_step1_32bit ( opnds [ 0 ] , opnds [ 1 ] ) ) ; else emit_insn ( gen_mov_got32_step1 ( opnds [ 0 ] , opnds [ 1 ] ) ) ; } new_insns = get_insns ( ) ; end_sequence ( ) ; replace_insns ( insn , new_insns ) ; } </s>

Do the first replacement step in tilegx_fixup_pcrel_references .


<s> bool function_checker :: require_immediate_enum ( unsigned int rel_argno , tree type ) { unsigned int argno = m_base_arg + rel_argno ; if ( ! argument_exists_p ( argno ) ) return true ; HOST_WIDE_INT actual ; if ( ! require_immediate ( argno , actual ) ) return false ; for ( tree entry = TYPE_VALUES ( type ) ; entry ; entry = TREE_CHAIN ( entry ) ) { tree value = TREE_VALUE ( entry ) ; if ( TREE_CODE ( value ) == CONST_DECL ) value = DECL_INITIAL ( value ) ; if ( wi :: to_widest ( value ) == actual ) return true ; } report_not_enum ( location , fndecl , argno , actual , type ) ; return false ; } </s>

Check that argument REL_ARGNO is an integer constant expression that has a valid value for enumeration type TYPE . REL_ARGNO counts from the end of the predication arguments .


<s> TargetLoweringBase :: LegalizeTypeAction HexagonTargetLowering :: getPreferredVectorAction ( MVT VT ) const { unsigned VecLen = VT . getVectorNumElements ( ) ; MVT ElemTy = VT . getVectorElementType ( ) ; if ( VecLen == 1 || VT . isScalableVector ( ) ) return TargetLoweringBase :: TypeScalarizeVector ; if ( Subtarget . useHVXOps ( ) ) { unsigned Action = getPreferredHvxVectorAction ( VT ) ; if ( Action != ~ 0u ) return static_cast < TargetLoweringBase :: LegalizeTypeAction > ( Action ) ; } if ( ElemTy == MVT :: i1 ) return TargetLoweringBase :: TypeWidenVector ; return TargetLoweringBase :: TypeSplitVector ; } </s>

Customize the preferred legalization strategy for certain types .


<s> TargetLowering :: AtomicExpansionKind AArch64TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { if ( Subtarget -> hasLSE ( ) ) return AtomicExpansionKind :: None ; if ( getTargetMachine ( ) . getOptLevel ( ) == 0 ) return AtomicExpansionKind :: None ; return AtomicExpansionKind :: LLSC ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LiveIntervals > ( ) ; AU . addPreservedID ( LiveVariablesID ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; AU . addRequired < AAResultsWrapperPass > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> const int * SIRegisterInfo :: getRegUnitPressureSets ( unsigned RegUnit ) const { static const int Empty [ ] = { - 1 } ; if ( hasRegUnit ( AMDGPU :: M0 , RegUnit ) ) return Empty ; return AMDGPUGenRegisterInfo :: getRegUnitPressureSets ( RegUnit ) ; } </s>

Get the dimensions of register pressure impacted by this register unit .


<s> bool isReg ( ) const override { if ( isGPRAsmReg ( ) && RegIdx . Index == 0 ) return true ; return Kind == k_PhysRegister ; } </s>


<s> unsigned LEGRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return LEG :: SP ; } </s>


<s> MCELFStreamer & Comet2TargetELFStreamer :: getStreamer ( ) { return static_cast < MCELFStreamer & > ( Streamer ) ; } </s>

Return the output streamer for the assembler .


<s> bool BlackfinFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return true ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> void print ( raw_ostream & OS ) const override { } </s>

print - Print a debug representation of the operand to the given stream .


<s> void ix86_expand_rounddf_32 ( rtx operand0 , rtx operand1 ) { machine_mode mode = GET_MODE ( operand0 ) ; rtx xa , xa2 , dxa , TWO52 , tmp , half , mhalf , one , res , mask ; rtx_code_label * label ; TWO52 = ix86_gen_TWO52 ( mode ) ; res = copy_to_reg ( operand1 ) ; xa = ix86_expand_sse_fabs ( res , & mask ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; xa2 = expand_simple_binop ( mode , PLUS , xa , TWO52 , NULL_RTX , 0 , OPTAB_DIRECT ) ; xa2 = expand_simple_binop ( mode , MINUS , xa2 , TWO52 , xa2 , 0 , OPTAB_DIRECT ) ; dxa = expand_simple_binop ( mode , MINUS , xa2 , xa , NULL_RTX , 0 , OPTAB_DIRECT ) ; half = force_reg ( mode , const_double_from_real_value ( dconsthalf , mode ) ) ; one = expand_simple_binop ( mode , PLUS , half , half , NULL_RTX , 0 , OPTAB_DIRECT ) ; mhalf = expand_simple_binop ( mode , MINUS , half , one , NULL_RTX , 0 , OPTAB_DIRECT ) ; tmp = ix86_expand_sse_compare_mask ( UNGT , dxa , half , false ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_AND ( mode , tmp , one ) ) ) ; xa2 = expand_simple_binop ( mode , MINUS , xa2 , tmp , NULL_RTX , 0 , OPTAB_DIRECT ) ; tmp = ix86_expand_sse_compare_mask ( UNGE , mhalf , dxa , false ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_AND ( mode , tmp , one ) ) ) ; xa2 = expand_simple_binop ( mode , PLUS , xa2 , tmp , NULL_RTX , 0 , OPTAB_DIRECT ) ; ix86_sse_copysign_to_positive ( res , xa2 , res , mask ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; emit_move_insn ( operand0 , res ) ; } </s>

Expand SSE sequence for computing round from OPERAND1 storing into OPERAND0 . Sequence that works without relying on DImode truncation via cvttsd2siq that is only available on 64bit targets .


"Unknown fence ordering in emitLeadingFence"


<s> static bool isAllOnes ( SDValue V ) { ConstantSDNode * C = dyn_cast < ConstantSDNode > ( V ) ; return C && C -> isAllOnesValue ( ) ; } </s>


<s> void ARMPassConfig :: addIRPasses ( ) { if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( 1 , false , false , true , true , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < ARMSubtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST . isThumb1Only ( ) ; } ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( createARMParallelDSPPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> MachineBasicBlock :: iterator XCoreInstrInfo :: loadImmediate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned Reg , uint64_t Value ) const { DebugLoc dl ; if ( MI != MBB . end ( ) && ! MI -> isDebugValue ( ) ) dl = MI -> getDebugLoc ( ) ; if ( isImmMskBitp ( Value ) ) { int N = Log2_32 ( Value ) + 1 ; return BuildMI ( MBB , MI , dl , get ( XCore :: MKMSK_rus ) , Reg ) . addImm ( N ) ; } if ( isImmU16 ( Value ) ) { int Opcode = isImmU6 ( Value ) ? XCore :: LDC_ru6 : XCore :: LDC_lru6 ; return BuildMI ( MBB , MI , dl , get ( Opcode ) , Reg ) . addImm ( Value ) ; } MachineConstantPool * ConstantPool = MBB . getParent ( ) -> getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Value ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; return BuildMI ( MBB , MI , dl , get ( XCore :: LDWCP_lru6 ) , Reg ) . addConstantPoolIndex ( Idx ) ; } </s>

Emit a series of instructions to load an immediate .


"Unexpected type for the widened instruction"

Called for instructions with the Custom LegalizationAction .


<s>
const
char
*
avr_out_insert_bits
(
rtx
*
op
,
int
*
plen
)
{
unsigned
int
map
=
UINTVAL
(
op
[
1
]
)
&
GET_MODE_MASK
(
SImode
)
;
unsigned
mask_fixed
;
bool
fixp_p
=
true
;
rtx
xop
[
4
]
;
xop
[
0
]
=
op
[
0
]
;
xop
[
1
]
=
op
[
2
]
;
xop
[
2
]
=
op
[
3
]
;
gcc_assert
(
REG_P
(
xop
[
2
]
)
||
CONST_INT_P
(
xop
[
2
]
)
)
;
if
(
plen
)
*
plen
=
0
;
else
if
(
flag_print_asm_name
)
fprintf
(
asm_out_file
,
ASM_COMMENT_START
"map = 0x%08x\n"
,
map
)
;
mask_fixed
=
avr_map_metric
(
map
,
MAP_MASK_FIXED_0_7
)
;
if
(
REGNO
(
xop
[
0
]
)
==
REGNO
(
xop
[
1
]
)
)
{
avr_asm_len
(
"mov __tmp_reg__,%1"
,
xop
,
plen
,
1
)
;
xop
[
1
]
=
tmp_reg_rtx
;
fixp_p
=
false
;
}
if
(
avr_map_metric
(
map
,
MAP_MASK_PREIMAGE_F
)
)
{
int
n_fix
=
0
,
n_nofix
=
0
;
gcc_assert
(
REG_P
(
xop
[
2
]
)
)
;
avr_move_bits
(
xop
,
map
,
true
,
&
n_fix
)
;
avr_move_bits
(
xop
,
map
,
false
,
&
n_nofix
)
;
if
(
fixp_p
&&
n_fix
n_nofix
>
3
)
{
xop
[
3
]
=
gen_int_mode
(
~
mask_fixed
,
QImode
)
;
avr_asm_len
(
"eor %0,%1"
CR_TAB
"andi %0,%3"
CR_TAB
"eor %0,%1"
,
xop
,
plen
,
3
)
;
fixp_p
=
false
;
}
}
else
{
if
(
fixp_p
&&
mask_fixed
)
{
avr_asm_len
(
"mov %0,%1"
,
xop
,
plen
,
1
)
;
fixp_p
=
false
;
}
}
avr_move_bits
(
xop
,
map
,
fixp_p
,
plen
)
;
return
""
;
}
</s>

PLEN == 0 : Print assembler code for ` insert_bits ' . PLEN ! = 0 : Compute code length in bytes . OP [ 0 ] : Result OP [ 1 ] : The mapping composed of nibbles . If nibble no . N is 0 : Bit N of result is copied from bit OP [ 2 ] .0 ... ... 7 : Bit N of result is copied from bit OP [ 2 ] .7 0xf : Bit N of result is copied from bit OP [ 3 ] .N OP [ 2 ] : Bits to be inserted OP [ 3 ] : Target value


"passing %qT to argument %d of %qE, which"

Like infer_vector_type , but also require the type to be integral .


<s> static void mips_promote_ready ( rtx * ready , int lower , int higher ) { rtx new_head ; int i ; new_head = ready [ lower ] ; for ( i = lower ; i < higher ; i ++ ) ready [ i ] = ready [ i + 1 ] ; ready [ i ] = new_head ; } </s>

Remove the instruction at index LOWER from ready queue READY and reinsert it in front of the instruction at index HIGHER . LOWER must be < = HIGHER .


<s> BitVector ARMBaseRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( ARM :: SP ) ; Reserved . set ( ARM :: PC ) ; Reserved . set ( ARM :: FPSCR ) ; if ( hasFP ( MF ) ) Reserved . set ( FramePtr ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( BasePtr ) ; if ( STI . isR9Reserved ( ) ) Reserved . set ( ARM :: R9 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .

ARM ARM ARM::SP ARM::PC ARM::FPSCR ARM::R9


<s>
const
char
*
host_detect_local_cpu
(
int
argc
,
const
char
*
*
argv
)
{
const
char
*
val
=
;
char
buf
[
128
]
;
FILE
*
f
=
;
bool
arch
;
const
struct
vendor_cpu
*
cpu_table
=
;
char
*
fcpu_info
=
;
if
(
argc
<
1
)
goto
not_found
;
arch
=
strcmp
(
argv
[
0
]
,
"arch"
)
==
0
;
if
(
!
arch
&&
strcmp
(
argv
[
0
]
,
"cpu"
)
!=
0
&&
strcmp
(
argv
[
0
]
,
"tune"
)
)
goto
not_found
;
fcpu_info
=
getenv
(
"GCC_CPUINFO"
)
;
if
(
fcpu_info
)
f
=
fopen
(
fcpu_info
,
"r"
)
;
else
f
=
fopen
(
"/proc/cpuinfo"
,
"r"
)
;
if
(
f
==
)
goto
not_found
;
while
(
fgets
(
buf
,
sizeof
(
buf
)
,
f
)
!=
)
{
if
(
startswith
(
buf
,
"CPU implementer"
)
)
{
int
i
;
for
(
i
=
0
;
vendors_table
[
i
]
.
vendor_no
!=
;
i
++
)
if
(
strstr
(
buf
,
vendors_table
[
i
]
.
vendor_no
)
!=
)
{
cpu_table
=
vendors_table
[
i
]
.
vendor_parts
;
break
;
}
}
if
(
startswith
(
buf
,
"CPU part"
)
)
{
int
i
;
if
(
cpu_table
==
)
goto
not_found
;
for
(
i
=
0
;
cpu_table
[
i
]
.
part_no
!=
;
i
++
)
if
(
strstr
(
buf
,
cpu_table
[
i
]
.
part_no
)
!=
)
{
val
=
arch
cpu_table
[
i
]
.
arch_name
:
cpu_table
[
i
]
.
cpu_name
;
break
;
}
break
;
}
}
if
(
val
)
{
fclose
(
f
)
;
return
concat
(
"-m"
,
argv
[
0
]
,
"="
,
val
,
)
;
}
not_found
:
{
unsigned
int
i
;
unsigned
int
opt
;
const
char
*
search
[
]
=
{
,
"arch"
}
;
if
(
f
)
fclose
(
f
)
;
search
[
0
]
=
argv
[
0
]
;
for
(
opt
=
0
;
opt
<
ARRAY_SIZE
(
search
)
;
opt
++
)
for
(
i
=
0
;
i
<
ARRAY_SIZE
(
configure_default_options
)
;
i
++
)
if
(
strcmp
(
configure_default_options
[
i
]
.
name
,
search
[
opt
]
)
==
0
)
return
concat
(
"-m"
,
search
[
opt
]
,
"="
,
configure_default_options
[
i
]
.
value
,
)
;
return
;
}
}
</s>

This will be called by the spec parser in gcc.cc when it sees a % : local_cpu_detect ( args ) construct . Currently it will be called with either `` cpu '' or `` tune '' as argument depending on if -mcpu=native or -mtune=native is to be substituted . It returns a string containing new command line parameters to be put at the place of the above two options , depending on what CPU this is executed . E.g . `` -mcpu=ultrasparc3 '' on an UltraSPARC III for -mcpu=native . If the routine ca n't detect a known processor , the -mcpu or -mtune option is discarded . ARGC and ARGV are set depending on the actual arguments given in the spec .


<s> bool AArch64InstrInfo :: isLdStPairSuppressed ( const MachineInstr & MI ) const { return llvm :: any_of ( MI . memoperands ( ) , [ ] ( MachineMemOperand * MMO ) { return MMO -> getFlags ( ) & MOSuppressPair ; } ) ; } </s>

Return true if pairing the given load or store is hinted to be unprofitable .


<s> bool rl78_virt_insns_ok ( void ) { if ( cfun ) return cfun -> machine -> virt_insns_ok ; return true ; } </s>

Predicates used in the MD patterns . This one is true when virtual insns may be matched , which typically means before ( or during ) the devirt pass .


<s> static tree ix86_md_asm_clobbers ( tree outputs ATTRIBUTE_UNUSED , tree inputs ATTRIBUTE_UNUSED , tree clobbers ) { clobbers = tree_cons ( NULL_TREE , build_string ( 5 , "flags" ) , clobbers ) ; clobbers = tree_cons ( NULL_TREE , build_string ( 4 , "fpsr" ) , clobbers ) ; clobbers = tree_cons ( NULL_TREE , build_string ( 7 , "dirflag" ) , clobbers ) ; return clobbers ; } </s>

Worker function for TARGET_MD_ASM_CLOBBERS . We do this in the new i386 backend to maintain source compatibility with the old cc0-based compiler .


<s>
bool
X86AsmParser
::
ParseDirective
(
AsmToken
DirectiveID
)
{
MCAsmParser
&
Parser
=
getParser
(
)
;
StringRef
IDVal
=
DirectiveID
.
getIdentifier
(
)
;
if
(
IDVal
==
".word"
)
return
ParseDirectiveWord
(
2
,
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
.
startswith
(
".code"
)
)
return
ParseDirectiveCode
(
IDVal
,
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
.
startswith
(
".att_syntax"
)
)
{
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.att_syntax noprefix' is not "
"supported: registers must have a "
"'%' prefix in .att_syntax"
)
;
}
getParser
(
)
.
setAssemblerDialect
(
0
)
;
return
false
;
}
else
if
(
IDVal
.
startswith
(
".intel_syntax"
)
)
{
getParser
(
)
.
setAssemblerDialect
(
1
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.intel_syntax prefix' is not "
"supported: registers must not have "
"a '%' prefix in .intel_syntax"
)
;
}
return
false
;
}
else
if
(
IDVal
==
".even"
)
return
parseDirectiveEven
(
DirectiveID
.
getLoc
(
)
)
;
return
true
;
}
</s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> virtual const OpenRISCSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> AVRSubtarget & AVRSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS , const TargetMachine & TM ) { ParseSubtargetFeatures ( CPU , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> static void register_builtin_types ( ) { scalar_types [ VECTOR_TYPE_ ## ACLE_NAME ] = SCALAR_TYPE ; for ( unsigned int i = 0 ; i < NUM_VECTOR_TYPES ; ++ i ) { tree eltype = scalar_types [ i ] ; tree vectype ; unsigned int num_zr = 0 , num_pr = 0 ; if ( eltype == boolean_type_node ) { vectype = build_truth_vector_type_for_mode ( BYTES_PER_SVE_VECTOR , VNx16BImode ) ; gcc_assert ( TYPE_MODE ( vectype ) == VNx16BImode && TYPE_MODE ( vectype ) == TYPE_MODE_RAW ( vectype ) && TYPE_ALIGN ( vectype ) == 16 && known_eq ( wi :: to_poly_offset ( TYPE_SIZE ( vectype ) ) , BYTES_PER_SVE_VECTOR ) ) ; num_pr = 1 ; } else { scalar_mode elmode = SCALAR_TYPE_MODE ( eltype ) ; unsigned int elbytes = GET_MODE_SIZE ( elmode ) ; poly_uint64 nunits = exact_div ( BYTES_PER_SVE_VECTOR , elbytes ) ; machine_mode mode = aarch64_sve_data_mode ( elmode , nunits ) . require ( ) ; vectype = build_vector_type_for_mode ( eltype , mode ) ; gcc_assert ( VECTOR_MODE_P ( TYPE_MODE ( vectype ) ) && TYPE_MODE ( vectype ) == mode && TYPE_MODE_RAW ( vectype ) == mode && TYPE_ALIGN ( vectype ) == 128 && known_eq ( wi :: to_poly_offset ( TYPE_SIZE ( vectype ) ) , BITS_PER_SVE_VECTOR ) ) ; num_zr = 1 ; } vectype = build_distinct_type_copy ( vectype ) ; gcc_assert ( vectype == TYPE_MAIN_VARIANT ( vectype ) ) ; SET_TYPE_STRUCTURAL_EQUALITY ( vectype ) ; TYPE_ARTIFICIAL ( vectype ) = 1 ; TYPE_INDIVISIBLE_P ( vectype ) = 1 ; add_sve_type_attribute ( vectype , num_zr , num_pr , vector_types [ i ] . mangled_name , vector_types [ i ] . acle_name ) ; make_type_sizeless ( vectype ) ; abi_vector_types [ i ] = vectype ; lang_hooks . types . register_builtin_type ( vectype , vector_types [ i ] . abi_name ) ; } } </s>

Register the built-in RVV ABI types , such as __rvv_int32m1_t .


<s> bool mep_epilogue_uses ( int regno ) { if ( regno == LP_REGNO && ( profile_arc_flag > 0 || profile_flag > 0 ) ) return true ; return ( reload_completed && mep_interrupt_saved_reg ( regno ) ) ; } </s>

Return true if epilogue uses register REGNO .


<s>
static
void
nds32_asm_function_begin_epilogue
(
FILE
*
file
)
{
fprintf
(
file
,
"\t! BEGIN EPILOGUE\n"
)
;
}
</s>

Before rtl epilogue has been expanded , this function is used .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"R600 Vector Registers Merge Pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .

AMDGPU
"R600 Vector Registers Merge Pass"


<s> int reg_unused_after ( rtx reg , rtx insn ) { enum rtx_code code , prev_code = UNKNOWN ; while ( ( insn = NEXT_INSN ( insn ) ) ) { if ( prev_code == CALL_INSN && call_used_regs [ REGNO ( reg ) ] ) return 1 ; code = GET_CODE ( insn ) ; if ( GET_CODE ( insn ) == CODE_LABEL ) return 1 ; if ( INSN_P ( insn ) ) { rtx set = single_set ( insn ) ; int in_src = set && reg_overlap_mentioned_p ( reg , SET_SRC ( set ) ) ; if ( set && in_src ) return 0 ; if ( set && reg_overlap_mentioned_p ( reg , SET_DEST ( set ) ) ) return 1 ; if ( set == 0 && reg_overlap_mentioned_p ( reg , PATTERN ( insn ) ) ) return 0 ; } prev_code = code ; } return 1 ; } </s>

Return nonzero if REG is not used after INSN . We assume REG is a reload reg , and therefore does not live past labels or calls or jumps .


<s> static tree s390_handle_vectorbool_attribute ( tree * node , tree name ATTRIBUTE_UNUSED , tree args ATTRIBUTE_UNUSED , int flags ATTRIBUTE_UNUSED , bool * no_add_attrs ) { tree type = * node , result = NULL_TREE ; machine_mode mode ; while ( POINTER_TYPE_P ( type ) || TREE_CODE ( type ) == FUNCTION_TYPE || TREE_CODE ( type ) == METHOD_TYPE || TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; mode = TYPE_MODE ( type ) ; switch ( mode ) { case E_DImode : case E_V2DImode : result = s390_builtin_types [ BT_BV2DI ] ; break ; case E_SImode : case E_V4SImode : result = s390_builtin_types [ BT_BV4SI ] ; break ; case E_HImode : case E_V8HImode : result = s390_builtin_types [ BT_BV8HI ] ; break ; case E_QImode : case E_V16QImode : result = s390_builtin_types [ BT_BV16QI ] ; break ; default : break ; } * no_add_attrs = true ; if ( result ) * node = lang_hooks . types . reconstruct_complex_type ( * node , result ) ; return NULL_TREE ; } </s>

Expand the s390_vector_bool type attribute .


<s>
void
SNESMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
unsigned
Size
=
Desc
.
getSize
(
)
;
assert
(
Size
>
0
&&
"Instruction size cannot be zero"
)
;
uint64_t
BinaryOpCode
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
emitInstruction
(
BinaryOpCode
,
Size
,
STI
,
OS
)
;
}
</s>

Encode the given Inst to bytes and append to CB .

SNES
SNES
0
"Instruction size cannot be zero"


<s> bool X86DynAllocaExpander :: runOnMachineFunction ( MachineFunction & MF ) { if ( ! MF . getInfo < X86MachineFunctionInfo > ( ) -> hasDynAlloca ( ) ) return false ; MRI = & MF . getRegInfo ( ) ; STI = & MF . getSubtarget < X86Subtarget > ( ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; StackPtr = TRI -> getStackRegister ( ) ; SlotSize = TRI -> getSlotSize ( ) ; StackProbeSize = 4096 ; if ( MF . getFunction ( ) . hasFnAttribute ( "stack-probe-size" ) ) { MF . getFunction ( ) . getFnAttribute ( "stack-probe-size" ) . getValueAsString ( ) . getAsInteger ( 0 , StackProbeSize ) ; } NoStackArgProbe = MF . getFunction ( ) . hasFnAttribute ( "no-stack-arg-probe" ) ; if ( NoStackArgProbe ) StackProbeSize = INT64_MAX ; LoweringMap Lowerings ; computeLowerings ( MF , Lowerings ) ; for ( auto & P : Lowerings ) lower ( P . first , P . second ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


"64-bit code requested on a subtarget that doesn't "


<s> SDValue AArch64SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; ConstantSDNode * SizeValue = dyn_cast < ConstantSDNode > ( Size ) ; const AArch64Subtarget & STI = DAG . getMachineFunction ( ) . getSubtarget < AArch64Subtarget > ( ) ; const char * bzeroEntry = ( V && V -> isNullValue ( ) ) ? STI . getBZeroEntry ( ) : nullptr ; if ( bzeroEntry && ( ! SizeValue || SizeValue -> getZExtValue ( ) > 256 ) ) { const AArch64TargetLowering & TLI = * STI . getTargetLowering ( ) ; EVT IntPtr = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; Type * IntPtrTy = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroEntry , IntPtr ) , std :: move ( Args ) ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memset .


<s> static bool isNot ( const MachineRegisterInfo & MRI , const MachineInstr & MI ) { if ( MI . getOpcode ( ) != TargetOpcode :: G_XOR ) return false ; auto ConstVal = getConstantVRegSExtVal ( MI . getOperand ( 2 ) . getReg ( ) , MRI ) ; return ConstVal && * ConstVal == - 1 ; } </s>