<s>
bool
MipsDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_R
:
case
InlineAsm
::
Constraint_ZC
:
OutOps
.
push_back
(
Op
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .

Mips
Mips
"Unexpected asm memory constraint"


<s> virtual const OR1KRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool mep_cannot_change_mode_class ( machine_mode from , machine_mode to , enum reg_class regclass ) { if ( from == to ) return false ; if ( TARGET_64BIT_CR_REGS && ( regclass == CR_REGS || regclass == LOADABLE_CR_REGS ) && ( GET_MODE_SIZE ( to ) < 8 || GET_MODE_SIZE ( from ) < 8 ) ) return true ; return false ; } </s>

Return true if the registers in CLASS can not represent the change from modes FROM to TO .


<s> BitVector SIRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; reserveRegisterTuples ( Reserved , AMDGPU :: EXEC ) ; reserveRegisterTuples ( Reserved , AMDGPU :: FLAT_SCR ) ; reserveRegisterTuples ( Reserved , AMDGPU :: M0 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_SHARED_BASE ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_SHARED_LIMIT ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_PRIVATE_BASE ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_PRIVATE_LIMIT ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TBA ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TMA ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP0_TTMP1 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP2_TTMP3 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP4_TTMP5 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP6_TTMP7 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP8_TTMP9 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP10_TTMP11 ) ; const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; unsigned MaxNumSGPRs = ST . getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = AMDGPU :: SGPR_32RegClass . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = AMDGPU :: SGPR_32RegClass . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } unsigned MaxNumVGPRs = ST . getMaxNumVGPRs ( MF ) ; unsigned TotalNumVGPRs = AMDGPU :: VGPR_32RegClass . getNumRegs ( ) ; for ( unsigned i = MaxNumVGPRs ; i < TotalNumVGPRs ; ++ i ) { unsigned Reg = AMDGPU :: VGPR_32RegClass . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } const SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , ScratchWaveOffsetReg ) ; } unsigned ScratchRSrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRSrcReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , ScratchRSrcReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , ScratchWaveOffsetReg ) ) ; } unsigned StackPtrReg = MFI -> getStackPtrOffsetReg ( ) ; if ( StackPtrReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , StackPtrReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , StackPtrReg ) ) ; } unsigned FrameReg = MFI -> getFrameOffsetReg ( ) ; if ( FrameReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , FrameReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , FrameReg ) ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static int m32r_is_insn ( rtx insn ) { return ( INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER && GET_CODE ( PATTERN ( insn ) ) != ADDR_VEC ) ; } </s>

Return true if INSN is real instruction bearing insn .


"rs6000_register_move_cost: ret=%d, mode=%s, from=%s, to=%s\n"

A C expression returning the cost of moving data from a register of class CLASS1 to one of CLASS2 .


<s> const MCExpr * createExprForCAPIVariantKind ( const MCExpr * SubExpr , unsigned VariantKind ) override { switch ( VariantKind ) { case LLVMDisassembler_VariantKind_ARM_HI16 : return ARMMCExpr :: createUpper16 ( SubExpr , Ctx ) ; case LLVMDisassembler_VariantKind_ARM_LO16 : return ARMMCExpr :: createLower16 ( SubExpr , Ctx ) ; default : return MCRelocationInfo :: createExprForCAPIVariantKind ( SubExpr , VariantKind ) ; } } </s>

Create an MCExpr for the target-specific VariantKind .


runOnMachineFunction - Emit the function body .


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool AArch64InstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF ) const { return MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoRedZone ) ; } </s>

Return true if the function can safely be outlined from .


<s> static int s390_builtin_vectorization_cost ( enum vect_cost_for_stmt type_of_cost , tree vectype , int misalign ATTRIBUTE_UNUSED ) { switch ( type_of_cost ) { case scalar_stmt : case scalar_load : case scalar_store : case vector_stmt : case vector_load : case vector_store : case vector_gather_load : case vector_scatter_store : case vec_to_scalar : case scalar_to_vec : case cond_branch_not_taken : case vec_perm : case vec_promote_demote : case unaligned_load : case unaligned_store : return 1 ; case cond_branch_taken : return 3 ; case vec_construct : return TYPE_VECTOR_SUBPARTS ( vectype ) - 1 ; default : gcc_unreachable ( ) ; } } </s>


<s> void MBlazeRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; if ( ! TFI -> hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; int Amount = Old -> getOperand ( 0 ) . getImm ( ) + 4 ; if ( Amount != 0 ) { unsigned Align = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; Amount = ( Amount + Align - 1 ) / Align * Align ; MachineInstr * New ; if ( Old -> getOpcode ( ) == MBlaze :: ADJCALLSTACKDOWN ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( MBlaze :: ADDI ) , MBlaze :: R1 ) . addReg ( MBlaze :: R1 ) . addImm ( - Amount ) ; } else { assert ( Old -> getOpcode ( ) == MBlaze :: ADJCALLSTACKUP ) ; New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( MBlaze :: ADDI ) , MBlaze :: R1 ) . addReg ( MBlaze :: R1 ) . addImm ( Amount ) ; } MBB . insert ( I , New ) ; } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool AArch64TargetLowering :: isZExtFree ( SDValue Val , EVT VT2 ) const { EVT VT1 = Val . getValueType ( ) ; if ( isZExtFree ( VT1 , VT2 ) ) { return true ; } if ( Val . getOpcode ( ) != ISD :: LOAD ) return false ; return ( VT1 . isSimple ( ) && VT1 . isInteger ( ) && VT2 . isSimple ( ) && VT2 . isInteger ( ) && VT1 . getSizeInBits ( ) <= 32 ) ; } </s>

Return true if zero-extending the specific node Val to type VT2 is free ( either because it 's implicitly zero-extended such as ARM ldrb / ldrh or because it 's folded such as X86 zero-extending loads ) .


<s> bool X86FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned CalleeSavedFrameSize = 0 ; int SpillSlotOffset = getOffsetOfLocalArea ( ) + X86FI -> getTCReturnAddrDelta ( ) ; if ( hasFP ( MF ) ) { SpillSlotOffset -= SlotSize ; MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; unsigned FPReg = TRI -> getFrameRegister ( MF ) ; for ( unsigned i = 0 ; i < CSI . size ( ) ; ++ i ) { if ( TRI -> regsOverlap ( CSI [ i ] . getReg ( ) , FPReg ) ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - 1 ] . setFrameIdx ( SlotIndex ) ; } X86FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; unsigned Size = TRI -> getSpillSize ( * RC ) ; unsigned Align = TRI -> getSpillAlignment ( * RC ) ; SpillSlotOffset -= std :: abs ( SpillSlotOffset ) % Align ; SpillSlotOffset -= Size ; int SlotIndex = MFI . CreateFixedSpillStackObject ( Size , SpillSlotOffset ) ; CSI [ i - 1 ] . setFrameIdx ( SlotIndex ) ; MFI . ensureMaxAlignment ( Align ) ; } return true ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> bool ARMTargetLowering :: isCheapToSpeculateCtlz ( ) const { return Subtarget -> hasV6T2Ops ( ) ; } </s>

Return true if it is cheap to speculate a call to intrinsic ctlz .


<s> int ix86_memory_move_cost ( enum machine_mode mode , enum reg_class class , int in ) { if ( FLOAT_CLASS_P ( class ) ) { int index ; switch ( mode ) { case SFmode : index = 0 ; break ; case DFmode : index = 1 ; break ; case XFmode : index = 2 ; break ; default : return 100 ; } return in ? ix86_cost -> fp_load [ index ] : ix86_cost -> fp_store [ index ] ; } if ( SSE_CLASS_P ( class ) ) { int index ; switch ( GET_MODE_SIZE ( mode ) ) { case 4 : index = 0 ; break ; case 8 : index = 1 ; break ; case 16 : index = 2 ; break ; default : return 100 ; } return in ? ix86_cost -> sse_load [ index ] : ix86_cost -> sse_store [ index ] ; } if ( MMX_CLASS_P ( class ) ) { int index ; switch ( GET_MODE_SIZE ( mode ) ) { case 4 : index = 0 ; break ; case 8 : index = 1 ; break ; default : return 100 ; } return in ? ix86_cost -> mmx_load [ index ] : ix86_cost -> mmx_store [ index ] ; } switch ( GET_MODE_SIZE ( mode ) ) { case 1 : if ( in ) return ( Q_CLASS_P ( class ) ? ix86_cost -> int_load [ 0 ] : ix86_cost -> movzbl_load ) ; else return ( Q_CLASS_P ( class ) ? ix86_cost -> int_store [ 0 ] : ix86_cost -> int_store [ 0 ] + 4 ) ; break ; case 2 : return in ? ix86_cost -> int_load [ 1 ] : ix86_cost -> int_store [ 1 ] ; default : if ( mode == TFmode ) mode = XFmode ; return ( ( in ? ix86_cost -> int_load [ 2 ] : ix86_cost -> int_store [ 2 ] ) * ( ( ( int ) GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ) ) ; } } </s>

Return the cost of moving data of mode M between a register and memory . A value of 2 is the default ; this cost is relative to those in ` REGISTER_MOVE_COST ' . If moving between registers and memory is more expensive than between two registers , you should define this macro to express the relative cost . Model also increased moving costs of QImode registers in non Q_REGS classes .


<s> int X86FrameLowering :: getInitialCFAOffset ( const MachineFunction & MF ) const { return TRI -> getSlotSize ( ) ; } </s>


<s> bool MOSCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: FailedISel ) ) return false ; auto * TPC = & getAnalysis < TargetPassConfig > ( ) ; GISelCSEAnalysisWrapper & Wrapper = getAnalysis < GISelCSEAnalysisWrapperPass > ( ) . getCSEWrapper ( ) ; auto * CSEInfo = & Wrapper . get ( TPC -> getCSEConfig ( ) ) ; const Function & F = MF . getFunction ( ) ; bool EnableOpt = MF . getTarget ( ) . getOptLevel ( ) != CodeGenOpt :: None && ! skipFunction ( F ) ; GISelKnownBits * KB = & getAnalysis < GISelKnownBitsAnalysis > ( ) . get ( MF ) ; MachineDominatorTree * MDT = & getAnalysis < MachineDominatorTree > ( ) ; MOSCombinerInfo PCInfo ( EnableOpt , F . hasOptSize ( ) , F . hasMinSize ( ) , KB , MDT ) ; Combiner C ( PCInfo , TPC ) ; return C . combineMachineInstrs ( MF , CSEInfo ) ; } </s>


<s> unsigned ARMFastISel :: constrainOperandRegClass ( const MCInstrDesc & II , unsigned Op , unsigned OpNum ) { if ( TargetRegisterInfo :: isVirtualRegister ( Op ) ) { const TargetRegisterClass * RegClass = TII . getRegClass ( II , OpNum , & TRI , * FuncInfo . MF ) ; if ( ! MRI . constrainRegClass ( Op , RegClass ) ) { unsigned NewOp = createResultReg ( RegClass ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , NewOp ) . addReg ( Op ) ) ; return NewOp ; } } return Op ; } </s>

Try to constrain Op so that it is usable by argument OpNum of the provided MCInstrDesc .


<s> BitVector XtensaRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; return Reserved ; } </s>


<s> TargetPassConfig * PatmosTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new PatmosPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s>
bool
WebAssemblyStoreResults
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
DEBUG
(
{
dbgs
(
)
<<
"********** Store Results **********\n"
<<
"********** Function: "
<<
MF
.
getName
(
)
<<
'\n'
;
}
)
;
const
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
MachineDominatorTree
&
MDT
=
getAnalysis
<
MachineDominatorTree
>
(
)
;
const
WebAssemblyTargetLowering
&
TLI
=
*
MF
.
getSubtarget
<
WebAssemblySubtarget
>
(
)
.
getTargetLowering
(
)
;
const
auto
&
LibInfo
=
getAnalysis
<
TargetLibraryInfoWrapperPass
>
(
)
.
getTLI
(
)
;
bool
Changed
=
false
;
assert
(
MRI
.
isSSA
(
)
&&
"StoreResults depends on SSA form"
)
;
for
(
auto
&
MBB
:
MF
)
{
DEBUG
(
dbgs
(
)
<<
"Basic Block: "
<<
MBB
.
getName
(
)
<<
'\n'
)
;
for
(
auto
&
MI
:
MBB
)
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
WebAssembly
::
STORE8_I32
:
case
WebAssembly
::
STORE16_I32
:
case
WebAssembly
::
STORE8_I64
:
case
WebAssembly
::
STORE16_I64
:
case
WebAssembly
::
STORE32_I64
:
case
WebAssembly
::
STORE_F32
:
case
WebAssembly
::
STORE_F64
:
case
WebAssembly
::
STORE_I32
:
case
WebAssembly
::
STORE_I64
:
Changed
|=
optimizeStore
(
MBB
,
MI
,
MRI
,
MDT
)
;
break
;
case
WebAssembly
::
CALL_I32
:
case
WebAssembly
::
CALL_I64
:
Changed
|=
optimizeCall
(
MBB
,
MI
,
MRI
,
MDT
,
TLI
,
LibInfo
)
;
break
;
}
}
return
Changed
;
}
</s>


This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly


<s>
void
HexagonCommonGEP
::
materialize
(
NodeToValueMap
&
Loc
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Nodes before materialization:\n"
<<
Nodes
<<
'\n'
)
;
NodeChildrenMap
NCM
;
NodeVect
Roots
;
invert_find_roots
(
Nodes
,
NCM
,
Roots
)
;
while
(
!
Roots
.
empty
(
)
)
{
NodeVect
::
iterator
First
=
Roots
.
begin
(
)
;
GepNode
*
Root
=
*
First
,
*
Last
=
*
First
;
Roots
.
erase
(
First
)
;
NodeVect
;
bool
LastUsed
=
false
;
unsigned
LastCN
=
0
;
Value
*
LocV
=
Loc
[
Last
]
;
if
(
!
LocV
)
continue
;
BasicBlock
*
LastB
=
cast
<
BasicBlock
>
(
LocV
)
;
do
{
.
push_back
(
Last
)
;
LastUsed
=
(
Last
->
Flags
&
GepNode
::
Used
)
;
if
(
LastUsed
)
break
;
NodeChildrenMap
::
iterator
CF
=
NCM
.
find
(
Last
)
;
LastCN
=
(
CF
!=
NCM
.
end
(
)
)
CF
->
second
.
size
(
)
:
0
;
if
(
LastCN
!=
1
)
break
;
GepNode
*
Child
=
CF
->
second
.
front
(
)
;
BasicBlock
*
ChildB
=
cast_or_null
<
BasicBlock
>
(
Loc
[
Child
]
)
;
if
(
ChildB
!=
nullptr
&&
LastB
!=
ChildB
)
break
;
Last
=
Child
;
}
while
(
true
)
;
BasicBlock
::
iterator
InsertAt
=
LastB
->
getTerminator
(
)
->
getIterator
(
)
;
if
(
LastUsed
||
LastCN
>
0
)
{
ValueVect
Urs
;
getAllUsersForNode
(
Root
,
Urs
,
NCM
)
;
BasicBlock
::
iterator
FirstUse
=
first_use_of_in_block
(
Urs
,
LastB
)
;
if
(
FirstUse
!=
LastB
->
end
(
)
)
InsertAt
=
FirstUse
;
}
Value
*
NewInst
=
fabricateGEP
(
,
InsertAt
,
LastB
)
;
if
(
LastCN
>
0
)
{
NodeVect
&
Cs
=
NCM
[
Last
]
;
for
(
NodeVect
::
iterator
I
=
Cs
.
begin
(
)
,
E
=
Cs
.
end
(
)
;
I
!=
E
;
++
I
)
{
GepNode
*
CN
=
*
I
;
CN
->
Flags
&=
~
GepNode
::
Internal
;
CN
->
Flags
|=
GepNode
::
Root
;
CN
->
BaseVal
=
NewInst
;
Roots
.
push_back
(
CN
)
;
}
}
if
(
LastUsed
)
{
NodeToUsesMap
::
iterator
UF
=
Uses
.
find
(
Last
)
;
assert
(
UF
!=
Uses
.
end
(
)
&&
"No use information found"
)
;
UseSet
&
Us
=
UF
->
second
;
for
(
UseSet
::
iterator
I
=
Us
.
begin
(
)
,
E
=
Us
.
end
(
)
;
I
!=
E
;
++
I
)
{
Use
*
U
=
*
I
;
U
->
set
(
NewInst
)
;
}
}
}
}
</s>

This method can be implemented to generate a mapped Value on demand .


<s> BaseType :: const_iterator begin ( ) const { return List . begin ( ) ; } </s>


<s> const MBlazeTargetMachine & getTargetMachine ( ) { return static_cast < const MBlazeTargetMachine & > ( TM ) ; } </s>

Return the target machine ( if available ) .


<s> bool SIRegisterInfo :: needsFrameBaseReg ( MachineInstr * MI , int64_t Offset ) const { if ( ! MI -> mayLoadOrStore ( ) ) return false ; int64_t FullOffset = Offset + getMUBUFInstrOffset ( MI ) ; return ! SIInstrInfo :: isLegalMUBUFImmOffset ( FullOffset ) ; } </s>

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s>
void
ARMTTIImpl
::
getUnrollingPreferences
(
Loop
*
L
,
ScalarEvolution
&
SE
,
TTI
::
UnrollingPreferences
&
UP
)
{
UP
.
UpperBound
=
true
;
if
(
!
ST
->
isMClass
(
)
)
return
BasicTTIImplBase
::
getUnrollingPreferences
(
L
,
SE
,
UP
)
;
UP
.
OptSizeThreshold
=
0
;
UP
.
PartialOptSizeThreshold
=
0
;
if
(
L
->
getHeader
(
)
->
getParent
(
)
->
hasOptSize
(
)
)
return
;
SmallVector
<
BasicBlock
*
,
4
>
ExitingBlocks
;
L
->
getExitingBlocks
(
ExitingBlocks
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Loop has:\n"
<<
"Blocks: "
<<
L
->
getNumBlocks
(
)
<<
"\n"
<<
"Exit blocks: "
<<
ExitingBlocks
.
size
(
)
<<
"\n"
)
;
if
(
ExitingBlocks
.
size
(
)
>
2
)
return
;
if
(
ST
->
hasBranchPredictor
(
)
&&
L
->
getNumBlocks
(
)
>
4
)
return
;
if
(
getBooleanLoopAttribute
(
L
,
"llvm.loop.isvectorized"
)
)
return
;
InstructionCost
Cost
=
0
;
for
(
auto
*
BB
:
L
->
getBlocks
(
)
)
{
for
(
auto
&
I
:
*
BB
)
{
if
(
I
.
getType
(
)
->
isVectorTy
(
)
)
return
;
if
(
isa
<
CallInst
>
(
I
)
||
isa
<
InvokeInst
>
(
I
)
)
{
if
(
const
Function
*
F
=
cast
<
CallBase
>
(
I
)
.
getCalledFunction
(
)
)
{
if
(
!
isLoweredToCall
(
F
)
)
continue
;
}
return
;
}
SmallVector
<
const
Value
*
,
4
>
Operands
(
I
.
operand_values
(
)
)
;
Cost
+=
getUserCost
(
&
I
,
Operands
,
TargetTransformInfo
::
TCK_SizeAndLatency
)
;
}
}
unsigned
UnrollCount
=
4
;
if
(
ST
->
isThumb1Only
(
)
)
{
unsigned
ExitingValues
=
0
;
SmallVector
<
BasicBlock
*
,
4
>
ExitBlocks
;
L
->
getExitBlocks
(
ExitBlocks
)
;
for
(
auto
*
Exit
:
ExitBlocks
)
{
unsigned
LiveOuts
=
count_if
(
Exit
->
phis
(
)
,
[
]
(
auto
&
PH
)
{
return
PH
.
getNumOperands
(
)
!=
1
||
!
isa
<
GetElementPtrInst
>
(
PH
.
getOperand
(
0
)
)
;
}
)
;
ExitingValues
=
ExitingValues
<
LiveOuts
LiveOuts
:
ExitingValues
;
}
if
(
ExitingValues
)
UnrollCount
/=
ExitingValues
;
if
(
UnrollCount
<=
1
)
return
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Cost of loop: "
<<
Cost
<<
"\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Default Runtime Unroll Count: "
<<
UnrollCount
<<
"\n"
)
;
UP
.
Partial
=
true
;
UP
.
Runtime
=
true
;
UP
.
UnrollRemainder
=
true
;
UP
.
DefaultUnrollRuntimeCount
=
UnrollCount
;
UP
.
UnrollAndJam
=
true
;
UP
.
UnrollAndJamInnerLoopThreshold
=
60
;
if
(
Cost
<
12
)
UP
.
Force
=
true
;
}
</s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> static void ix86_emit_save_sse_regs_using_mov ( HOST_WIDE_INT cfa_offset ) { unsigned int regno ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( SSE_REGNO_P ( regno ) && ix86_save_reg ( regno , true , true ) ) { ix86_emit_save_reg_using_mov ( V4SFmode , regno , cfa_offset ) ; cfa_offset -= GET_MODE_SIZE ( V4SFmode ) ; } } </s>

Emit code to save SSE registers using MOV insns . First register is stored at CFA - CFA_OFFSET .


<s>
Register
MCS51TargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
LLT
VT
,
const
MachineFunction
&
MF
)
const
{
Register
Reg
;
if
(
VT
==
LLT
::
scalar
(
8
)
)
{
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"r0"
,
MCS51
::
R0
)
.
Case
(
"r1"
,
MCS51
::
R1
)
.
Default
(
0
)
;
}
else
{
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"r0"
,
MCS51
::
R1R0
)
.
Case
(
"sp"
,
MCS51
::
SP
)
.
Default
(
0
)
;
}
if
(
Reg
)
return
Reg
;
report_fatal_error
(
Twine
(
"Invalid register name \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;
}
</s>

Return the register ID of the name passed in .


"No InstrInfo? Can not create a hazard recognizer!"

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .


<s> bool MipsAsmPrinter :: isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { const MachineBasicBlock * Pred = * MBB -> pred_begin ( ) ; if ( const BasicBlock * bb = Pred -> getBasicBlock ( ) ) if ( isa < SwitchInst > ( bb -> getTerminator ( ) ) ) return false ; if ( MBB -> isLandingPad ( ) || MBB -> pred_empty ( ) ) return false ; MachineBasicBlock :: const_pred_iterator PI = MBB -> pred_begin ( ) , PI2 = PI ; ++ PI2 ; if ( PI2 != MBB -> pred_end ( ) ) return false ; if ( ! Pred -> isLayoutSuccessor ( MBB ) ) return false ; if ( Pred -> empty ( ) ) return true ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> getDesc ( ) . isTerminator ( ) ) ; return ! I -> getDesc ( ) . isBarrier ( ) ; } </s>

isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


<s> void HexagonInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned SlotAlign = MFI . getObjectAlignment ( FI ) ; unsigned KillFlag = getKillRegState ( isKill ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , SlotAlign ) ; if ( Hexagon :: IntRegsRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: S2_storeri_io ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( Hexagon :: DoubleRegsRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: S2_storerd_io ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( Hexagon :: PredRegsRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: STriw_pred ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( Hexagon :: ModRegsRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: STriw_ctr ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( Hexagon :: HvxQRRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: PS_vstorerq_ai ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( Hexagon :: HvxVRRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: PS_vstorerv_ai ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( Hexagon :: HvxWRRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: PS_vstorerw_ai ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else { llvm_unreachable ( "Unimplemented" ) ; } } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> int num_insns_constant_wide ( HOST_WIDE_INT value ) { if ( ( ( unsigned HOST_WIDE_INT ) value + 0x8000 ) < 0x10000 ) return 1 ; else if ( ( value & 0xffff ) == 0 && ( value >> 31 == - 1 || value >> 31 == 0 ) ) return 1 ; else if ( TARGET_POWERPC64 ) { HOST_WIDE_INT low = ( ( value & 0xffffffff ) ^ 0x80000000 ) - 0x80000000 ; HOST_WIDE_INT high = value >> 31 ; if ( high == 0 || high == - 1 ) return 2 ; high >>= 1 ; if ( low == 0 ) return num_insns_constant_wide ( high ) + 1 ; else if ( high == 0 ) return num_insns_constant_wide ( low ) + 1 ; else return ( num_insns_constant_wide ( high ) + num_insns_constant_wide ( low ) + 1 ) ; } else return 2 ; } </s>

Return the number of instructions it takes to form a constant in an integer register .


<s> static rtx wprop_gen ( rtx reg , propagate_mask pm , unsigned rep , void * data_ ) { wcast_data_t * data = ( wcast_data_t * ) data_ ; if ( pm & PM_loop_begin ) { unsigned align = GET_MODE_ALIGNMENT ( GET_MODE ( reg ) ) / BITS_PER_UNIT ; if ( align > worker_bcast_align ) worker_bcast_align = align ; data -> offset = ( data -> offset + align - 1 ) & ~ ( align - 1 ) ; data -> ptr = gen_reg_rtx ( Pmode ) ; return gen_adddi3 ( data -> ptr , data -> base , GEN_INT ( data -> offset ) ) ; } else if ( pm & PM_loop_end ) { rtx clobber = gen_rtx_CLOBBER ( GET_MODE ( data -> ptr ) , data -> ptr ) ; data -> ptr = NULL_RTX ; return clobber ; } else return nvptx_gen_wcast ( reg , pm , rep , data ) ; } </s>


<s> bool XCoreTargetLowering :: isZExtFree ( SDValue Val , EVT VT2 ) const { if ( Val . getOpcode ( ) != ISD :: LOAD ) return false ; EVT VT1 = Val . getValueType ( ) ; if ( ! VT1 . isSimple ( ) || ! VT1 . isInteger ( ) || ! VT2 . isSimple ( ) || ! VT2 . isInteger ( ) ) return false ; switch ( VT1 . getSimpleVT ( ) . SimpleTy ) { default : break ; case MVT :: i8 : return true ; } return false ; } </s>

Return true if zero-extending the specific node Val to type VT2 is free ( either because it 's implicitly zero-extended such as ARM ldrb / ldrh or because it 's folded such as X86 zero-extending loads ) .


<s>
std
::
unique_ptr
<
LanaiOperand
>
LanaiAsmParser
::
parseIdentifier
(
)
{
SMLoc
Start
=
Parser
.
getTok
(
)
.
getLoc
(
)
;
SMLoc
End
=
SMLoc
::
getFromPointer
(
Parser
.
getTok
(
)
.
getLoc
(
)
.
getPointer
(
)
1
)
;
const
MCExpr
*
Res
,
*
RHS
=
nullptr
;
LanaiMCExpr
::
VariantKind
Kind
=
LanaiMCExpr
::
VK_Lanai_None
;
if
(
Lexer
.
getKind
(
)
!=
AsmToken
::
Identifier
)
return
nullptr
;
StringRef
Identifier
;
if
(
Parser
.
parseIdentifier
(
Identifier
)
)
return
nullptr
;
if
(
Identifier
.
equals_insensitive
(
"hi"
)
)
Kind
=
LanaiMCExpr
::
VK_Lanai_ABS_HI
;
else
if
(
Identifier
.
equals_insensitive
(
"lo"
)
)
Kind
=
LanaiMCExpr
::
VK_Lanai_ABS_LO
;
if
(
Kind
!=
LanaiMCExpr
::
VK_Lanai_None
)
{
if
(
Lexer
.
getKind
(
)
!=
AsmToken
::
LParen
)
{
Error
(
Lexer
.
getLoc
(
)
,
"Expected '('"
)
;
return
nullptr
;
}
Lexer
.
Lex
(
)
;
if
(
Parser
.
parseIdentifier
(
Identifier
)
)
return
nullptr
;
}
if
(
Lexer
.
getKind
(
)
==
AsmToken
::
Plus
&&
Parser
.
parseExpression
(
RHS
)
)
return
nullptr
;
if
(
Kind
!=
LanaiMCExpr
::
VK_Lanai_None
)
{
if
(
Lexer
.
getKind
(
)
!=
AsmToken
::
RParen
)
{
Error
(
Lexer
.
getLoc
(
)
,
"Expected ')'"
)
;
return
nullptr
;
}
Lexer
.
Lex
(
)
;
}
End
=
SMLoc
::
getFromPointer
(
Parser
.
getTok
(
)
.
getLoc
(
)
.
getPointer
(
)
1
)
;
MCSymbol
*
Sym
=
getContext
(
)
.
getOrCreateSymbol
(
Identifier
)
;
const
MCExpr
*
Expr
=
MCSymbolRefExpr
::
create
(
Sym
,
getContext
(
)
)
;
Res
=
LanaiMCExpr
::
create
(
Kind
,
Expr
,
getContext
(
)
)
;
if
(
RHS
)
Res
=
MCBinaryExpr
::
createAdd
(
Res
,
RHS
,
getContext
(
)
)
;
return
LanaiOperand
::
createImm
(
Res
,
Start
,
End
)
;
}
</s>

Parse an identifier or string ( as a quoted identifier ) and set Res to the identifier contents .

Lanai
Lanai
Lanai
1
Lanai
Lanai
Lanai
"hi"
Lanai
Lanai
"lo"
Lanai
Lanai
Lanai
Lanai
"Expected '('"
Lanai
Lanai
"Expected ')'"
1
Lanai
LanaiOperand::createImm


<s> bool alpha_expand_mov ( machine_mode mode , rtx * operands ) { rtx tmp ; if ( MEM_P ( operands [ 0 ] ) && ! reg_or_0_operand ( operands [ 1 ] , mode ) ) operands [ 1 ] = force_reg ( mode , operands [ 1 ] ) ; if ( mode == Pmode && symbolic_operand ( operands [ 1 ] , mode ) ) { tmp = alpha_legitimize_address_1 ( operands [ 1 ] , operands [ 0 ] , mode ) ; if ( tmp ) { if ( tmp == operands [ 0 ] ) return true ; operands [ 1 ] = tmp ; return false ; } } if ( ! CONSTANT_P ( operands [ 1 ] ) || input_operand ( operands [ 1 ] , mode ) ) return false ; if ( CONST_INT_P ( operands [ 1 ] ) || GET_CODE ( operands [ 1 ] ) == CONST_VECTOR ) { if ( alpha_split_const_mov ( mode , operands ) ) return true ; } tmp = force_const_mem ( mode , operands [ 1 ] ) ; if ( tmp == NULL_RTX ) return false ; if ( reload_in_progress ) { emit_move_insn ( operands [ 0 ] , XEXP ( tmp , 0 ) ) ; operands [ 1 ] = replace_equiv_address ( tmp , operands [ 0 ] ) ; } else operands [ 1 ] = validize_mem ( tmp ) ; return false ; } </s>

Expand a move instruction ; return true if all work is done . We do n't handle non-bwx subword loads here .


<s> static short high_pressure ( enum machine_mode mode ) { if ( ( REG_N_SETS ( 0 ) - REG_N_DEATHS ( 0 ) ) >= R0_MAX_LIFE_REGIONS && REG_LIVE_LENGTH ( 0 ) >= R0_MAX_LIVE_LENGTH ) return 1 ; if ( mode == SFmode ) return ( CURR_REGMODE_PRESSURE ( SFmode ) > SFMODE_MAX_WEIGHT ) ; else return ( CURR_REGMODE_PRESSURE ( SImode ) > SIMODE_MAX_WEIGHT ) ; } </s>

Return true if the pressure is high for MODE .


<s> bool msp430_is_interrupt_func ( void ) { return is_interrupt_func ( current_function_decl ) ; } </s>

Returns true if the current function has the `` interrupt '' attribute .


<s> int system_reg_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { switch ( REGNO ( op ) ) { case PR_REG : case MACL_REG : case MACH_REG : return 1 ; } return 0 ; } </s>

Returns 1 if OP is MACL , MACH or PR . The input must be a REG rtx . Used only in general_movsrc_operand .


<s> bool SIInstrInfo :: hasUnwantedEffectsWhenEXECEmpty ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( MI . mayStore ( ) && isSMRD ( MI ) ) return true ; if ( MI . isReturn ( ) ) return true ; if ( Opcode == AMDGPU :: S_SENDMSG || Opcode == AMDGPU :: S_SENDMSGHALT || Opcode == AMDGPU :: EXP || Opcode == AMDGPU :: EXP_DONE || Opcode == AMDGPU :: DS_ORDERED_COUNT || Opcode == AMDGPU :: S_TRAP ) return true ; if ( MI . isCall ( ) || MI . isInlineAsm ( ) ) return true ; if ( Opcode == AMDGPU :: V_READFIRSTLANE_B32 || Opcode == AMDGPU :: V_READLANE_B32 ) return true ; return false ; } </s>

Whether we must prevent this instruction from executing with EXEC = 0 .


<s>
void
output_addr_const_pdp11
(
FILE
*
file
,
rtx
x
)
{
char
buf
[
256
]
;
restart
:
switch
(
GET_CODE
(
x
)
)
{
case
PC
:
gcc_assert
(
flag_pic
)
;
putc
(
'.'
,
file
)
;
break
;
case
SYMBOL_REF
:
assemble_name
(
file
,
XSTR
(
x
,
0
)
)
;
break
;
case
LABEL_REF
:
ASM_GENERATE_INTERNAL_LABEL
(
buf
,
"L"
,
CODE_LABEL_NUMBER
(
XEXP
(
x
,
0
)
)
)
;
assemble_name
(
file
,
buf
)
;
break
;
case
CODE_LABEL
:
ASM_GENERATE_INTERNAL_LABEL
(
buf
,
"L"
,
CODE_LABEL_NUMBER
(
x
)
)
;
assemble_name
(
file
,
buf
)
;
break
;
case
CONST_INT
:
fprintf
(
file
,
"%#ho"
,
(
unsigned
short
)
INTVAL
(
x
)
)
;
break
;
case
CONST
:
output_addr_const_pdp11
(
file
,
XEXP
(
x
,
0
)
)
;
break
;
case
CONST_DOUBLE
:
if
(
GET_MODE
(
x
)
==
VOIDmode
)
{
gcc_assert
(
!
CONST_DOUBLE_HIGH
(
x
)
)
;
fprintf
(
file
,
"%#ho"
,
(
unsigned
short
)
CONST_DOUBLE_LOW
(
x
)
)
;
}
else
output_operand_lossage
(
"floating constant misused"
)
;
break
;
case
PLUS
:
if
(
GET_CODE
(
XEXP
(
x
,
0
)
)
==
CONST_INT
)
{
output_addr_const_pdp11
(
file
,
XEXP
(
x
,
1
)
)
;
if
(
INTVAL
(
XEXP
(
x
,
0
)
)
>=
0
)
fprintf
(
file
,
"+"
)
;
output_addr_const_pdp11
(
file
,
XEXP
(
x
,
0
)
)
;
}
else
{
output_addr_const_pdp11
(
file
,
XEXP
(
x
,
0
)
)
;
if
(
INTVAL
(
XEXP
(
x
,
1
)
)
>=
0
)
fprintf
(
file
,
"+"
)
;
output_addr_const_pdp11
(
file
,
XEXP
(
x
,
1
)
)
;
}
break
;
case
MINUS
:
x
=
simplify_subtraction
(
x
)
;
if
(
GET_CODE
(
x
)
!=
MINUS
)
goto
restart
;
output_addr_const_pdp11
(
file
,
XEXP
(
x
,
0
)
)
;
fprintf
(
file
,
"-"
)
;
if
(
GET_CODE
(
XEXP
(
x
,
1
)
)
==
CONST_INT
&&
INTVAL
(
XEXP
(
x
,
1
)
)
<
0
)
{
fprintf
(
file
,
targetm
.
asm_out
.
open_paren
)
;
output_addr_const_pdp11
(
file
,
XEXP
(
x
,
1
)
)
;
fprintf
(
file
,
targetm
.
asm_out
.
close_paren
)
;
}
else
output_addr_const_pdp11
(
file
,
XEXP
(
x
,
1
)
)
;
break
;
case
ZERO_EXTEND
:
case
SIGN_EXTEND
:
output_addr_const_pdp11
(
file
,
XEXP
(
x
,
0
)
)
;
break
;
default
:
output_operand_lossage
(
"invalid expression as operand"
)
;
}
}
</s>

A copy of output_addr_const modified for pdp11 expression syntax . output_addr_const also gets called for % cDIGIT and % nDIGIT , which we do n't use , and for debugging output , which we do n't support with this port either . So this copy should get called whenever needed .


<s> static rtx ix86_expand_store_builtin ( enum insn_code icode , tree arglist ) { rtx pat ; tree arg0 = TREE_VALUE ( arglist ) ; tree arg1 = TREE_VALUE ( TREE_CHAIN ( arglist ) ) ; rtx op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , 0 ) ; rtx op1 = expand_expr ( arg1 , NULL_RTX , VOIDmode , 0 ) ; enum machine_mode mode0 = insn_data [ icode ] . operand [ 0 ] . mode ; enum machine_mode mode1 = insn_data [ icode ] . operand [ 1 ] . mode ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( pat ) emit_insn ( pat ) ; return 0 ; } </s>

Subroutine of ix86_expand_builtin to take care of stores .


<s> std :: pair < unsigned , const TargetRegisterClass * > MBlazeTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , MBlaze :: CPURegsRegisterClass ) ; case 'f' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , MBlaze :: FGR32RegisterClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> static int mcore_and_cost ( rtx x ) { HOST_WIDE_INT val ; if ( GET_CODE ( XEXP ( x , 1 ) ) != CONST_INT ) return 2 ; val = INTVAL ( XEXP ( x , 1 ) ) ; if ( CONST_OK_FOR_K ( val ) || CONST_OK_FOR_M ( ~ val ) ) return 2 ; else if ( const_ok_for_mcore ( val ) ) return 3 ; else if ( TARGET_HARDLIT && mcore_const_ok_for_inline ( val ) ) return 4 ; return 5 ; } </s>

What does an and instruction cost - we do this b/c immediates may have been relaxed . We want to ensure that cse will cse relaxed immeds out . Otherwise we 'll get bad code ( multiple reloads of the same const ) .


<s> bool VLIWResourceModel :: isResourceAvailable ( SUnit * SU ) { if ( ! SU || ! SU -> getInstr ( ) ) return false ; switch ( SU -> getInstr ( ) -> getOpcode ( ) ) { default : if ( ! ResourcesModel -> canReserveResources ( SU -> getInstr ( ) ) ) return false ; case TargetOpcode :: EXTRACT_SUBREG : case TargetOpcode :: INSERT_SUBREG : case TargetOpcode :: SUBREG_TO_REG : case TargetOpcode :: REG_SEQUENCE : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: COPY : case TargetOpcode :: INLINEASM : break ; } for ( unsigned i = 0 , e = Packet . size ( ) ; i != e ; ++ i ) { if ( Packet [ i ] -> Succs . size ( ) == 0 ) continue ; for ( SUnit :: const_succ_iterator I = Packet [ i ] -> Succs . begin ( ) , E = Packet [ i ] -> Succs . end ( ) ; I != E ; ++ I ) { if ( I -> isCtrl ( ) ) continue ; if ( I -> getSUnit ( ) == SU ) return false ; } } return true ; } </s>

Check if scheduling of this SU is possible in the current packet .


<s> bool arc_check_mov_const ( HOST_WIDE_INT ival ) { ival = ival & 0xffffffff ; if ( SIGNED_INT12 ( ival ) ) return false ; if ( ( ival & ~ 0x8000001f ) == 0 ) return true ; if ( IS_POWEROF2_P ( ival + 1 ) ) return true ; if ( ! TARGET_BARREL_SHIFTER ) return false ; if ( ( ( ival >> ( __builtin_ffs ( ival ) - 1 ) ) & 0xffffff00 ) == 0 ) return true ; if ( ( ival & ~ 0x3f00 ) == 0 ) return true ; if ( ( ival & ~ 0x3f0000 ) == 0 ) return true ; if ( ( ival & ~ 0x3f000000 ) == 0 ) return true ; return false ; } </s>


Implement ASM_DECLARE_FUNCTION_NAME . Output the ISA features used by the function fndecl .

aarch64
"\t.arch %s\n"
"\t"
".tune %s\n"
"function"


<s> bool WebAssemblyPassConfig :: addInstSelector ( ) { ( void ) TargetPassConfig :: addInstSelector ( ) ; addPass ( createWebAssemblyISelDag ( getWebAssemblyTargetMachine ( ) , getOptLevel ( ) ) ) ; addPass ( createWebAssemblyArgumentMove ( ) ) ; addPass ( createWebAssemblySetP2AlignOperands ( ) ) ; addPass ( createWebAssemblyFixBrTableDefaults ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .

WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly


<s> SystemZSubtarget & SystemZSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "generic" ; if ( CPUName == "generic" ) CPUName = sys :: getHostCPUName ( ) ; ParseSubtargetFeatures ( CPUName , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .

SystemZ SystemZ SystemZ "generic" "generic"


<s> bool doInitialization ( Module & M ) override { Result . reset ( new AMDGPUAAResult ( M . getDataLayout ( ) , Triple ( M . getTargetTriple ( ) ) ) ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s>
bool
VLIWResourceModel
::
reserveResources
(
SUnit
*
SU
,
bool
IsTop
)
{
bool
startNewCycle
=
false
;
if
(
!
SU
)
{
ResourcesModel
->
clearResources
(
)
;
Packet
.
clear
(
)
;
TotalPackets
++
;
return
false
;
}
if
(
!
isResourceAvailable
(
SU
,
IsTop
)
||
Packet
.
size
(
)
>=
SchedModel
->
getIssueWidth
(
)
)
{
ResourcesModel
->
clearResources
(
)
;
Packet
.
clear
(
)
;
TotalPackets
++
;
startNewCycle
=
true
;
}
switch
(
SU
->
getInstr
(
)
->
getOpcode
(
)
)
{
default
:
ResourcesModel
->
reserveResources
(
*
SU
->
getInstr
(
)
)
;
break
;
case
TargetOpcode
::
EXTRACT_SUBREG
:
case
TargetOpcode
::
INSERT_SUBREG
:
case
TargetOpcode
::
SUBREG_TO_REG
:
case
TargetOpcode
::
REG_SEQUENCE
:
case
TargetOpcode
::
IMPLICIT_DEF
:
case
TargetOpcode
::
KILL
:
case
TargetOpcode
::
CFI_INSTRUCTION
:
case
TargetOpcode
::
EH_LABEL
:
case
TargetOpcode
::
COPY
:
case
TargetOpcode
::
INLINEASM
:
case
TargetOpcode
::
INLINEASM_BR
:
break
;
}
Packet
.
push_back
(
SU
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Packet["
<<
TotalPackets
<<
"]:\n"
)
;
for
(
unsigned
i
=
0
,
e
=
Packet
.
size
(
)
;
i
!=
e
;
++
i
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"\t["
<<
i
<<
"] SU("
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
Packet
[
i
]
->
NodeNum
<<
")\t"
)
;
LLVM_DEBUG
(
Packet
[
i
]
->
getInstr
(
)
->
dump
(
)
)
;
}
return
startNewCycle
;
}
</s>


<s> unsigned getReg ( ) const override { return Reg . RegNo ; } </s>

Returns the register associated with this edge .


<s> rtx dimode_scalar_chain :: replace_with_subreg ( rtx x , rtx reg , rtx new_reg ) { if ( x == reg ) return gen_rtx_SUBREG ( V2DImode , new_reg , 0 ) ; const char * fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; int i , j ; for ( i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'e' ) XEXP ( x , i ) = replace_with_subreg ( XEXP ( x , i ) , reg , new_reg ) ; else if ( fmt [ i ] == 'E' ) for ( j = XVECLEN ( x , i ) - 1 ; j >= 0 ; j -- ) XVECEXP ( x , i , j ) = replace_with_subreg ( XVECEXP ( x , i , j ) , reg , new_reg ) ; } return x ; } </s>

Replace REG in X with a V2DI subreg of NEW_REG .


<s> void alpha_initialize_trampoline ( rtx tramp , rtx fnaddr , rtx cxt , int fnofs , int cxtofs , int jmpofs ) { rtx temp , temp1 , addr ; enum machine_mode mode = TARGET_ABI_OPEN_VMS ? Pmode : ptr_mode ; fnaddr = convert_memory_address ( mode , fnaddr ) ; cxt = convert_memory_address ( mode , cxt ) ; addr = memory_address ( mode , plus_constant ( tramp , fnofs ) ) ; emit_move_insn ( gen_rtx_MEM ( mode , addr ) , fnaddr ) ; addr = memory_address ( mode , plus_constant ( tramp , cxtofs ) ) ; emit_move_insn ( gen_rtx_MEM ( mode , addr ) , cxt ) ; if ( 0 && jmpofs >= 0 ) { temp = force_operand ( plus_constant ( tramp , jmpofs + 4 ) , NULL_RTX ) ; temp = expand_binop ( DImode , sub_optab , fnaddr , temp , temp , 1 , OPTAB_WIDEN ) ; temp = expand_shift ( RSHIFT_EXPR , Pmode , temp , build_int_cst ( NULL_TREE , 2 ) , NULL_RTX , 1 ) ; temp = expand_and ( SImode , gen_lowpart ( SImode , temp ) , GEN_INT ( 0x3fff ) , 0 ) ; addr = memory_address ( SImode , plus_constant ( tramp , jmpofs ) ) ; temp1 = force_reg ( SImode , gen_rtx_MEM ( SImode , addr ) ) ; temp1 = expand_and ( SImode , temp1 , GEN_INT ( 0xffffc000 ) , NULL_RTX ) ; temp1 = expand_binop ( SImode , ior_optab , temp1 , temp , temp1 , 1 , OPTAB_WIDEN ) ; emit_move_insn ( gen_rtx_MEM ( SImode , addr ) , temp1 ) ; } emit_library_call ( init_one_libfunc ( "__enable_execute_stack" ) , 0 , VOIDmode , 1 , tramp , Pmode ) ; if ( jmpofs >= 0 ) emit_insn ( gen_imb ( ) ) ; } </s>

Emit RTL insns to initialize the variable parts of a trampoline at TRAMP . FNADDR is an RTX for the address of the function 's pure code . CXT is an RTX for the static chain value for the function . The three offset parameters are for the individual template 's layout . A JMPOFS < 0 indicates that the trampoline does not contain instructions at all . We assume here that a function will be called many more times than its address is taken ( e.g. , it might be passed to qsort ) , so we take the trouble to initialize the `` hint '' field in the JMP insn . Note that the hint field is PC ( new ) + 4 * bits 13:0 .


<s> bool SIInstrInfo :: isTriviallyReMaterializable ( const MachineInstr * MI , AliasAnalysis * AA ) const { switch ( MI -> getOpcode ( ) ) { default : return AMDGPUInstrInfo :: isTriviallyReMaterializable ( MI , AA ) ; case AMDGPU :: S_MOV_B32 : case AMDGPU :: S_MOV_B64 : case AMDGPU :: V_MOV_B32_e32 : return MI -> getOperand ( 1 ) . isImm ( ) ; } } </s>

Return true if the instruction is trivially rematerializable , meaning it has no side effects and requires no operands that are n't always available .


<s> SDValue AMDGPUTargetLowering :: SplitVectorLoad ( const SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; if ( VT . getVectorNumElements ( ) == 2 ) return ScalarizeVectorLoad ( Op , DAG ) ; LoadSDNode * Load = cast < LoadSDNode > ( Op ) ; SDValue BasePtr = Load -> getBasePtr ( ) ; EVT PtrVT = BasePtr . getValueType ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; SDLoc SL ( Op ) ; MachinePointerInfo SrcValue ( Load -> getMemOperand ( ) -> getValue ( ) ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Op , SL , LoVT , HiVT ) ; SDValue LoLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , LoVT , Load -> getChain ( ) , BasePtr , SrcValue , LoMemVT , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> isInvariant ( ) , Load -> getAlignment ( ) ) ; SDValue HiPtr = DAG . getNode ( ISD :: ADD , SL , PtrVT , BasePtr , DAG . getConstant ( LoMemVT . getStoreSize ( ) , PtrVT ) ) ; SDValue HiLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , HiVT , Load -> getChain ( ) , HiPtr , SrcValue . getWithOffset ( LoMemVT . getStoreSize ( ) ) , HiMemVT , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> isInvariant ( ) , Load -> getAlignment ( ) ) ; SDValue Ops [ ] = { DAG . getNode ( ISD :: CONCAT_VECTORS , SL , VT , LoLoad , HiLoad ) , DAG . getNode ( ISD :: TokenFactor , SL , MVT :: Other , LoLoad . getValue ( 1 ) , HiLoad . getValue ( 1 ) ) } ; return DAG . getMergeValues ( Ops , SL ) ; } </s>

Split a vector load into 2 loads of half the vector .


<s>
static
void
visium_print_operand
(
FILE
*
file
,
rtx
op
,
int
letter
)
{
switch
(
letter
)
{
case
'#'
:
if
(
final_sequence
)
visium_indent_opcode
=
1
;
else
fputs
(
"\n\t nop"
,
file
)
;
return
;
case
'b'
:
fprintf
(
file
,
HOST_WIDE_INT_PRINT_UNSIGNED
,
UINTVAL
(
op
)
&
0xff
)
;
return
;
case
'w'
:
fprintf
(
file
,
HOST_WIDE_INT_PRINT_UNSIGNED
,
UINTVAL
(
op
)
&
0xffff
)
;
return
;
case
'u'
:
fprintf
(
file
,
HOST_WIDE_INT_PRINT_UNSIGNED
,
(
UINTVAL
(
op
)
>>
16
)
&
0xffff
)
;
return
;
case
'r'
:
if
(
GET_CODE
(
op
)
==
REG
)
fputs
(
reg_names
[
REGNO
(
op
)
]
,
file
)
;
else
fputs
(
reg_names
[
0
]
,
file
)
;
return
;
case
'f'
:
if
(
GET_CODE
(
op
)
==
REG
)
fputs
(
reg_names
[
REGNO
(
op
)
]
,
file
)
;
else
fputs
(
reg_names
[
FP_FIRST_REGNUM
]
,
file
)
;
return
;
}
switch
(
GET_CODE
(
op
)
)
{
case
REG
:
if
(
letter
==
'd'
)
fputs
(
reg_names
[
REGNO
(
op
)
+
1
]
,
file
)
;
else
fputs
(
reg_names
[
REGNO
(
op
)
]
,
file
)
;
break
;
case
SYMBOL_REF
:
case
LABEL_REF
:
case
CONST
:
output_addr_const
(
file
,
op
)
;
break
;
case
MEM
:
visium_print_operand_address
(
file
,
GET_MODE
(
op
)
,
XEXP
(
op
,
0
)
)
;
break
;
case
CONST_INT
:
fprintf
(
file
,
HOST_WIDE_INT_PRINT_DEC
,
INTVAL
(
op
)
)
;
break
;
case
CODE_LABEL
:
asm_fprintf
(
file
,
"%LL%d"
,
CODE_LABEL_NUMBER
(
op
)
)
;
break
;
case
HIGH
:
visium_print_operand
(
file
,
XEXP
(
op
,
1
)
,
letter
)
;
break
;
default
:
fatal_insn
(
"illegal operand "
,
op
)
;
}
}
</s>

Implement TARGET_PRINT_OPERAND . Output to stdio stream FILE the assembler syntax for an instruction operand OP subject to the modifier LETTER .


<s> const TargetRegisterClass * ARMRegisterInfo :: getPointerRegClass ( ) const { return & ARM :: GPRRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> bool AArch64TargetLowering :: shouldExpandAtomicStoreInIR ( StoreInst * SI ) const { unsigned Size = SI -> getValueOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return Size == 128 ; } </s>

Returns how the given ( atomic ) store should be expanded by the IR-level AtomicExpand pass into .


<s> void MOSPassConfig :: addPreSched2 ( ) { addPass ( createMOSPostRAScavengingPass ( ) ) ; addPass ( & FinalizeISelID ) ; addPass ( & ExpandPostRAPseudosID ) ; addPass ( createMOSLateOptimizationPass ( ) ) ; addPass ( createMOSStaticStackAllocPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> InstructionCost AArch64TTIImpl :: getIntrinsicInstrCost ( const IntrinsicCostAttributes & ICA , TTI :: TargetCostKind CostKind ) { auto * RetTy = ICA . getReturnType ( ) ; switch ( ICA . getID ( ) ) { case Intrinsic :: umin : case Intrinsic :: umax : { auto LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; if ( LT . second == MVT :: v2i64 ) return LT . first * 2 ; LLVM_FALLTHROUGH ; } case Intrinsic :: smin : case Intrinsic :: smax : { static const auto ValidMinMaxTys = { MVT :: v8i8 , MVT :: v16i8 , MVT :: v4i16 , MVT :: v8i16 , MVT :: v2i32 , MVT :: v4i32 } ; auto LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; if ( any_of ( ValidMinMaxTys , [ & LT ] ( MVT M ) { return M == LT . second ; } ) ) return LT . first ; break ; } case Intrinsic :: sadd_sat : case Intrinsic :: ssub_sat : case Intrinsic :: uadd_sat : case Intrinsic :: usub_sat : { static const auto ValidSatTys = { MVT :: v8i8 , MVT :: v16i8 , MVT :: v4i16 , MVT :: v8i16 , MVT :: v2i32 , MVT :: v4i32 , MVT :: v2i64 } ; auto LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; unsigned Instrs = LT . second . getScalarSizeInBits ( ) == RetTy -> getScalarSizeInBits ( ) ? 1 : 4 ; if ( any_of ( ValidSatTys , [ & LT ] ( MVT M ) { return M == LT . second ; } ) ) return LT . first * Instrs ; break ; } case Intrinsic :: abs : { static const auto ValidAbsTys = { MVT :: v8i8 , MVT :: v16i8 , MVT :: v4i16 , MVT :: v8i16 , MVT :: v2i32 , MVT :: v4i32 , MVT :: v2i64 } ; auto LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; if ( any_of ( ValidAbsTys , [ & LT ] ( MVT M ) { return M == LT . second ; } ) ) return LT . first ; break ; } case Intrinsic :: experimental_stepvector : { InstructionCost Cost = 1 ; auto LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; if ( LT . first > 1 ) { Type * LegalVTy = EVT ( LT . second ) . getTypeForEVT ( RetTy -> getContext ( ) ) ; InstructionCost AddCost = getArithmeticInstrCost ( Instruction :: Add , LegalVTy , CostKind ) ; Cost += AddCost * ( LT . first - 1 ) ; } return Cost ; } default : break ; } return BaseT :: getIntrinsicInstrCost ( ICA , CostKind ) ; } </s>


<s>
void
SIInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
DestReg
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
const
SIMachineFunctionInfo
*
MFI
=
MF
->
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MachineFrameInfo
&
FrameInfo
=
MF
->
getFrameInfo
(
)
;
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
unsigned
Align
=
FrameInfo
.
getObjectAlignment
(
FrameIndex
)
;
unsigned
Size
=
FrameInfo
.
getObjectSize
(
FrameIndex
)
;
unsigned
SpillSize
=
TRI
->
getSpillSize
(
*
RC
)
;
MachinePointerInfo
PtrInfo
=
MachinePointerInfo
::
getFixedStack
(
*
MF
,
FrameIndex
)
;
MachineMemOperand
*
MMO
=
MF
->
getMachineMemOperand
(
PtrInfo
,
MachineMemOperand
::
MOLoad
,
Size
,
Align
)
;
if
(
RI
.
isSGPRClass
(
RC
)
)
{
const
MCInstrDesc
&
OpDesc
=
get
(
getSGPRSpillRestoreOpcode
(
SpillSize
)
)
;
if
(
TargetRegisterInfo
::
isVirtualRegister
(
DestReg
)
&&
SpillSize
==
4
)
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
MRI
.
constrainRegClass
(
DestReg
,
&
AMDGPU
::
SReg_32_XM0RegClass
)
;
}
FrameInfo
.
setStackID
(
FrameIndex
,
SIStackID
::
SGPR_SPILL
)
;
MachineInstrBuilder
Spill
=
BuildMI
(
MBB
,
MI
,
DL
,
OpDesc
,
DestReg
)
.
addFrameIndex
(
FrameIndex
)
.
addMemOperand
(
MMO
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
,
RegState
::
Implicit
)
.
addReg
(
MFI
->
getFrameOffsetReg
(
)
,
RegState
::
Implicit
)
;
if
(
ST
.
hasScalarStores
(
)
)
{
Spill
.
addReg
(
AMDGPU
::
M0
,
RegState
::
ImplicitDefine
|
RegState
::
Dead
)
;
}
return
;
}
assert
(
RI
.
hasVGPRs
(
RC
)
&&
"Only VGPR spilling expected"
)
;
unsigned
Opcode
=
getVGPRSpillRestoreOpcode
(
SpillSize
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opcode
)
,
DestReg
)
.
addFrameIndex
(
FrameIndex
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
)
.
addReg
(
MFI
->
getFrameOffsetReg
(
)
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> static inline tree def_builtin_const ( HOST_WIDE_INT mask , const char * name , enum ix86_builtin_func_type tcode , enum ix86_builtins code ) { tree decl = def_builtin ( mask , name , tcode , code ) ; if ( decl ) TREE_READONLY ( decl ) = 1 ; else ix86_builtins_isa [ ( int ) code ] . const_p = true ; return decl ; } </s>

Likewise , but also marks the function as `` const '' .


<s> const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> bool PPCTargetLowering :: isFPExtFree ( EVT VT ) const { assert ( VT . isFloatingPoint ( ) ) ; return true ; } </s>

Return true if an fpext operation is free ( for instance , because single-precision floating-point numbers are implicitly extended to double-precision ) .


<s> const SISubtarget * GCNTargetMachine :: getSubtargetImpl ( const Function & F ) const { StringRef GPU = getGPUName ( F ) ; StringRef FS = getFeatureString ( F ) ; SmallString < 128 > SubtargetKey ( GPU ) ; SubtargetKey . append ( FS ) ; auto & I = SubtargetMap [ SubtargetKey ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < SISubtarget > ( TargetTriple , GPU , FS , * this ) ; } I -> setScalarizeGlobalBehavior ( ScalarizeGlobal ) ; return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool isIntrinsic ( ) const { return ( Attributes & X86FMA3Intrinsic ) != 0 ; } </s>

Returns true iff the group of FMA opcodes holds intrinsic opcodes .


<s> void rs6000_emit_le_vsx_move ( rtx dest , rtx source , machine_mode mode ) { gcc_assert ( ! BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P ( mode ) && ! gpr_or_gpr_p ( dest , source ) && ( MEM_P ( source ) ^ MEM_P ( dest ) ) ) ; if ( MEM_P ( source ) ) { gcc_assert ( REG_P ( dest ) || GET_CODE ( dest ) == SUBREG ) ; rs6000_emit_le_vsx_load ( dest , source , mode ) ; } else { if ( ! REG_P ( source ) ) source = force_reg ( mode , source ) ; rs6000_emit_le_vsx_store ( dest , source , mode ) ; } } </s>

Emit a sequence representing a little-endian VSX load or store , moving data from SOURCE to DEST in mode MODE . This is done separately from rs6000_emit_move to ensure it is called only during expand . LE VSX loads and stores introduced later are handled with a split . The expand-time RTL generation allows us to optimize away redundant pairs of register-permutes .


<s> InstrStage :: FuncUnits HexagonInstrInfo :: getUnits ( const MachineInstr & MI ) const { const InstrItineraryData & II = * Subtarget . getInstrItineraryData ( ) ; const InstrStage & IS = * II . beginStage ( MI . getDesc ( ) . getSchedClass ( ) ) ; return IS . getUnits ( ) ; } </s>


<s> virtual unsigned getNumFixupKinds ( ) const LLVM_OVERRIDE { return SystemZ :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> static void ia64_asm_emit_except_personality ( rtx personality ) { fputs ( "\t.personality\t" , asm_out_file ) ; output_addr_const ( asm_out_file , personality ) ; fputc ( '\n' , asm_out_file ) ; } </s>


<s> static void s390_register_info ( ) { int i ; char clobbered_regs [ 32 ] ; gcc_assert ( ! epilogue_completed ) ; if ( reload_completed ) s390_regs_ever_clobbered ( clobbered_regs ) ; else for ( i = 0 ; i < 32 ; i ++ ) clobbered_regs [ i ] = df_regs_ever_live_p ( i ) ; for ( i = 0 ; i < 32 ; i ++ ) clobbered_regs [ i ] = clobbered_regs [ i ] && ! global_regs [ i ] ; cfun_frame_layout . fpr_bitmap = 0 ; cfun_frame_layout . high_fprs = 0 ; for ( i = FPR0_REGNUM ; i <= FPR15_REGNUM ; i ++ ) if ( clobbered_regs [ i ] && ! call_really_used_regs [ i ] ) { cfun_set_fpr_save ( i ) ; if ( i >= FPR8_REGNUM ) cfun_frame_layout . high_fprs ++ ; } clobbered_regs [ 12 ] |= ( ( flag_pic && df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) ) || ( flag_split_stack && cfun -> stdarg && ( crtl -> is_leaf || TARGET_TPF_PROFILING || has_hard_reg_initial_val ( Pmode , RETURN_REGNUM ) ) ) ) ; clobbered_regs [ BASE_REGNUM ] |= ( cfun -> machine -> base_reg && REGNO ( cfun -> machine -> base_reg ) == BASE_REGNUM ) ; clobbered_regs [ HARD_FRAME_POINTER_REGNUM ] |= ! ! frame_pointer_needed ; clobbered_regs [ RETURN_REGNUM ] |= ( ! crtl -> is_leaf || TARGET_TPF_PROFILING || cfun -> machine -> split_branches_pending_p || cfun_frame_layout . save_return_addr_p || crtl -> calls_eh_return ) ; clobbered_regs [ STACK_POINTER_REGNUM ] |= ( ! crtl -> is_leaf || TARGET_TPF_PROFILING || cfun_save_high_fprs_p || get_frame_size ( ) > 0 || ( reload_completed && cfun_frame_layout . frame_size > 0 ) || cfun -> calls_alloca ) ; memset ( cfun_frame_layout . gpr_save_slots , SAVE_SLOT_NONE , 16 ) ; for ( i = 6 ; i < 16 ; i ++ ) if ( clobbered_regs [ i ] ) cfun_gpr_save_slot ( i ) = SAVE_SLOT_STACK ; s390_register_info_stdarg_fpr ( ) ; s390_register_info_gprtofpr ( ) ; s390_register_info_set_ranges ( ) ; s390_register_info_stdarg_gpr ( ) ; } </s>

Fill cfun- > machine with info about register usage of current function . Return in CLOBBERED_REGS which GPRs are currently considered set .


<s> PreservedAnalyses AMDGPUUnifyMetadataPass :: run ( Module & M , ModuleAnalysisManager & AM ) { return unifyMetadataImpl ( M ) ? PreservedAnalyses :: none ( ) : PreservedAnalyses :: all ( ) ; } </s>

Run the analysis pass over a function and produce a dominator tree .


"eliminateCallFramePseudoInstr size too big: "

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s>
void
final_prescan_insn
(
rtx
insn
,
rtx
*
opvec
ATTRIBUTE_UNUSED
,
int
noperands
ATTRIBUTE_UNUSED
)
{
if
(
TARGET_DUMPISIZE
)
fprintf
(
asm_out_file
,
"\n! at %04x\n"
,
INSN_ADDRESSES
(
INSN_UID
(
insn
)
)
)
;
if
(
TARGET_RELAX
)
{
rtx
note
;
note
=
find_reg_note
(
insn
,
REG_LABEL
,
NULL_RTX
)
;
if
(
note
)
{
rtx
pattern
;
pattern
=
PATTERN
(
insn
)
;
if
(
GET_CODE
(
pattern
)
==
PARALLEL
)
pattern
=
XVECEXP
(
pattern
,
0
,
0
)
;
switch
(
GET_CODE
(
pattern
)
)
{
case
SET
:
if
(
GET_CODE
(
SET_SRC
(
pattern
)
)
!=
CALL
&&
get_attr_type
(
insn
)
!=
TYPE_SFUNC
)
{
targetm
.
asm_out
.
internal_label
(
asm_out_file
,
"L"
,
CODE_LABEL_NUMBER
(
XEXP
(
note
,
0
)
)
)
;
break
;
}
case
CALL
:
asm_fprintf
(
asm_out_file
,
"\t.uses %LL%d\n"
,
CODE_LABEL_NUMBER
(
XEXP
(
note
,
0
)
)
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
}
}
</s>

If defined , a C statement to be executed just prior to the output of assembler code for INSN , to modify the extracted operands so they will be output differently . Here the argument OPVEC is the vector containing the operands extracted from INSN , and NOPERANDS is the number of elements of the vector which contain meaningful data for this insn . The contents of this vector are what will be used to convert the insn template into assembler code , so you can change the assembler output by changing the contents of the vector . We use it to check if the current insn needs a nop in front of it because of load delays , and also to update the delay slot statistics .


<s> bool X86TargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createX86ISelDag ( * this , OptLevel ) ) ; PM . add ( createX87FPRegKillInserterPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s>
MCDisassembler
::
DecodeStatus
WebAssemblyDisassembler
::
onSymbolStart
(
StringRef
Name
,
uint64_t
&
Size
,
ArrayRef
<
uint8_t
>
Bytes
,
uint64_t
Address
,
raw_ostream
&
CStream
)
const
{
Size
=
0
;
if
(
Address
==
0
)
{
int64_t
FunctionCount
;
if
(
!
nextLEB
(
FunctionCount
,
Bytes
,
Size
,
false
)
)
return
MCDisassembler
::
Fail
;
outs
(
)
<<
"        # "
<<
FunctionCount
<<
" functions in section."
;
}
else
{
int64_t
BodySize
,
LocalEntryCount
;
if
(
!
nextLEB
(
BodySize
,
Bytes
,
Size
,
false
)
||
!
nextLEB
(
LocalEntryCount
,
Bytes
,
Size
,
false
)
)
return
MCDisassembler
::
Fail
;
if
(
LocalEntryCount
)
{
outs
(
)
<<
"        .local "
;
for
(
int64_t
I
=
0
;
I
<
LocalEntryCount
;
I
++
)
{
int64_t
Count
,
Type
;
if
(
!
nextLEB
(
Count
,
Bytes
,
Size
,
false
)
||
!
nextLEB
(
Type
,
Bytes
,
Size
,
false
)
)
return
MCDisassembler
::
Fail
;
for
(
int64_t
J
=
0
;
J
<
Count
;
J
++
)
{
if
(
I
||
J
)
outs
(
)
<<
", "
;
outs
(
)
<<
WebAssembly
::
anyTypeToString
(
Type
)
;
}
}
}
}
outs
(
)
<<
"\n"
;
return
MCDisassembler
::
Success
;
}
</s>

Used to perform separate target specific disassembly for a particular symbol .

WebAssembly
WebAssembly
0
0
"        # "
" functions in section."
"        .local "
0
0
", "
WebAssembly::anyTypeToString
"\n"


<s> enum attr_cc compute_logical_op_cc ( machine_mode mode , rtx * operands ) { enum rtx_code code = GET_CODE ( operands [ 3 ] ) ; const unsigned HOST_WIDE_INT intval = ( unsigned HOST_WIDE_INT ) ( ( GET_CODE ( operands [ 2 ] ) == CONST_INT ) && register_operand ( operands [ 1 ] , VOIDmode ) ? INTVAL ( operands [ 2 ] ) : 0x55555555 ) ; const unsigned HOST_WIDE_INT det = ( code != AND ) ? intval : ~ intval ; const unsigned HOST_WIDE_INT b0 = ( det >> 0 ) & 0xff ; const unsigned HOST_WIDE_INT b1 = ( det >> 8 ) & 0xff ; const unsigned HOST_WIDE_INT w0 = ( det >> 0 ) & 0xffff ; const unsigned HOST_WIDE_INT w1 = ( det >> 16 ) & 0xffff ; int lower_half_easy_p = 0 ; int upper_half_easy_p = 0 ; enum attr_cc cc = CC_CLOBBER ; switch ( mode ) { case HImode : if ( ( TARGET_H8300H || TARGET_H8300S ) && b0 != 0 && b1 != 0 ) { cc = CC_SET_ZNV ; } break ; case SImode : if ( TARGET_H8300H || TARGET_H8300S ) { lower_half_easy_p = ( b0 == 0 || b1 == 0 || ( code != IOR && w0 == 0xffff ) ) ; upper_half_easy_p = ( ( code != IOR && w1 == 0xffff ) || ( code == AND && w1 == 0xff00 ) ) ; } if ( ( TARGET_H8300H || TARGET_H8300S ) && w0 != 0 && w1 != 0 && ! ( lower_half_easy_p && upper_half_easy_p ) && ! ( code == IOR && w1 == 0xffff && ( w0 & 0x8000 ) != 0 && lower_half_easy_p ) ) { cc = CC_SET_ZNV ; } else { if ( ( TARGET_H8300H || TARGET_H8300S ) && code == IOR && w1 == 0xffff && ( w0 & 0x8000 ) != 0 ) { cc = CC_SET_ZNV ; } } break ; default : gcc_unreachable ( ) ; } return cc ; } </s>

Compute which flag bits are valid after a logical insn .


<s> void gen_ashift_hi ( int type , int n , rtx reg ) { if ( n < 0 ) { if ( type == ASHIFT ) type = LSHIFTRT ; else type = ASHIFT ; n = - n ; } switch ( type ) { case ASHIFTRT : case LSHIFTRT : { int offset = 0 ; if ( GET_CODE ( reg ) == SUBREG ) { offset = SUBREG_BYTE ( reg ) ; reg = SUBREG_REG ( reg ) ; } gen_ashift ( type , n , gen_rtx_SUBREG ( SImode , reg , offset ) ) ; break ; } case ASHIFT : emit_insn ( gen_ashlhi3_k ( reg , reg , GEN_INT ( n ) ) ) ; break ; } } </s>


"Unexpected register class in CSRsViaCopy!"

"Function should be nounwind in insertCopiesSplitCSR!"

Insert explicit copies in entry and exit blocks .


<s> static bool c6x_registers_update ( rtx_insn * insn ) { enum attr_cross cross ; enum attr_dest_regfile destrf ; int i , nops ; rtx x ; if ( ! reload_completed || recog_memoized ( insn ) < 0 ) return false ; reg_access_stall = false ; memcpy ( ss . tmp_reg_n_accesses , ss . reg_n_accesses , sizeof ss . tmp_reg_n_accesses ) ; memcpy ( ss . tmp_reg_n_xaccesses , ss . reg_n_xaccesses , sizeof ss . tmp_reg_n_xaccesses ) ; extract_insn ( insn ) ; cross = get_attr_cross ( insn ) ; destrf = get_attr_dest_regfile ( insn ) ; nops = recog_data . n_operands ; x = PATTERN ( insn ) ; if ( GET_CODE ( x ) == COND_EXEC ) { c6x_mark_reg_read ( XEXP ( XEXP ( x , 0 ) , 0 ) , false ) ; nops -= 2 ; } for ( i = 0 ; i < nops ; i ++ ) { rtx op = recog_data . operand [ i ] ; if ( recog_data . operand_type [ i ] == OP_OUT ) continue ; if ( REG_P ( op ) ) { bool this_cross = cross ; if ( destrf == DEST_REGFILE_A && A_REGNO_P ( REGNO ( op ) ) ) this_cross = false ; if ( destrf == DEST_REGFILE_B && B_REGNO_P ( REGNO ( op ) ) ) this_cross = false ; c6x_mark_reg_read ( op , this_cross ) ; } else if ( MEM_P ( op ) ) { op = XEXP ( op , 0 ) ; switch ( GET_CODE ( op ) ) { case POST_INC : case PRE_INC : case POST_DEC : case PRE_DEC : op = XEXP ( op , 0 ) ; case REG : c6x_mark_reg_read ( op , false ) ; break ; case POST_MODIFY : case PRE_MODIFY : op = XEXP ( op , 1 ) ; gcc_assert ( GET_CODE ( op ) == PLUS ) ; case PLUS : c6x_mark_reg_read ( XEXP ( op , 0 ) , false ) ; if ( REG_P ( XEXP ( op , 1 ) ) ) c6x_mark_reg_read ( XEXP ( op , 1 ) , false ) ; break ; case SYMBOL_REF : case LABEL_REF : case CONST : c6x_mark_regno_read ( REG_B14 , false ) ; break ; default : gcc_unreachable ( ) ; } } else if ( ! CONSTANT_P ( op ) && strlen ( recog_data . constraints [ i ] ) > 0 ) gcc_unreachable ( ) ; } return reg_access_stall ; } </s>

Update the register state information for an instruction whose body is X . Return true if the instruction has to be delayed until the next cycle .


<s> bool X86AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Intrn = MF . getFunction ( ) -> hasInternalLinkage ( ) ; OutStreamer . BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer . EmitCOFFSymbolStorageClass ( Intrn ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer . EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer . EndCOFFSymbolDef ( ) ; } EmitFunctionHeader ( ) ; EmitFunctionBody ( ) ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> void ix86_expand_divmod_libfunc ( rtx libfunc , machine_mode mode , rtx op0 , rtx op1 , rtx * quot_p , rtx * rem_p ) { rtx rem = assign_386_stack_local ( mode , SLOT_TEMP ) ; rtx quot = emit_library_call_value ( libfunc , NULL_RTX , LCT_NORMAL , mode , op0 , mode , op1 , mode , XEXP ( rem , 0 ) , Pmode ) ; * quot_p = quot ; * rem_p = rem ; } </s>


<s> unsigned SparcInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == SP :: STri || MI -> getOpcode ( ) == SP :: STXri || MI -> getOpcode ( ) == SP :: STFri || MI -> getOpcode ( ) == SP :: STDFri || MI -> getOpcode ( ) == SP :: STQFri ) { if ( MI -> getOperand ( 0 ) . isFI ( ) && MI -> getOperand ( 1 ) . isImm ( ) && MI -> getOperand ( 1 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 0 ) . getIndex ( ) ; return MI -> getOperand ( 2 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> static inline unsigned int rx_round_up ( unsigned int value , unsigned int alignment ) { alignment -= 1 ; return ( value + alignment ) & ( ~ alignment ) ; } </s>

Return VALUE rounded up to the next ALIGNMENT boundary .


<s>
void
PIC16TargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
switch
(
N
->
getOpcode
(
)
)
{
case
ISD
::
GlobalAddress
:
Results
.
push_back
(
ExpandGlobalAddress
(
N
,
DAG
)
)
;
return
;
case
ISD
::
ExternalSymbol
:
Results
.
push_back
(
ExpandExternalSymbol
(
N
,
DAG
)
)
;
return
;
case
ISD
::
STORE
:
Results
.
push_back
(
ExpandStore
(
N
,
DAG
)
)
;
return
;
case
ISD
::
LOAD
:
PopulateResults
(
ExpandLoad
(
N
,
DAG
)
,
Results
)
;
return
;
case
ISD
::
ADD
:
return
;
case
ISD
::
FrameIndex
:
Results
.
push_back
(
ExpandFrameIndex
(
N
,
DAG
)
)
;
return
;
default
:
assert
(
0
&&
"not implemented"
)
;
return
;
}
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

PIC16
PIC16
ISD::GlobalAddress
ISD::ExternalSymbol
ISD::STORE
ISD::LOAD
ISD::ADD
ISD::FrameIndex
0
"not implemented"


<s>
void
CSKYInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
Register
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
CSKYMachineFunctionInfo
*
CFI
=
MF
.
getInfo
<
CSKYMachineFunctionInfo
>
(
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
unsigned
Opcode
=
0
;
if
(
CSKY
::
GPRRegClass
.
hasSubClassEq
(
RC
)
)
{
Opcode
=
CSKY
::
LD32W
;
}
else
if
(
CSKY
::
CARRYRegClass
.
hasSubClassEq
(
RC
)
)
{
Opcode
=
CSKY
::
RESTORE_CARRY
;
CFI
->
setSpillsCR
(
)
;
}
else
{
llvm_unreachable
(
"Unknown RegisterClass"
)
;
}
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
,
MachineMemOperand
::
MOLoad
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlign
(
FI
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opcode
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> bool x86_maybe_negate_const_int ( rtx * loc , machine_mode mode ) { HOST_WIDE_INT val ; if ( ! CONST_INT_P ( * loc ) ) return false ; switch ( mode ) { case E_DImode : gcc_assert ( x86_64_immediate_operand ( * loc , mode ) ) ; mode = SImode ; break ; case E_SImode : case E_HImode : case E_QImode : break ; default : gcc_unreachable ( ) ; } if ( mode_signbit_p ( mode , * loc ) ) return false ; val = INTVAL ( * loc ) ; if ( ( val < 0 && val != - 128 ) || val == 128 ) { * loc = GEN_INT ( - val ) ; return true ; } return false ; } </s>

If profitable , negate ( without causing overflow ) integer constant of mode MODE at location LOC . Return true in this case .


<s> unsigned SparcInstrInfo :: getGlobalBaseReg ( MachineFunction * MF ) const { SparcMachineFunctionInfo * SparcFI = MF -> getInfo < SparcMachineFunctionInfo > ( ) ; unsigned GlobalBaseReg = SparcFI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg != 0 ) return GlobalBaseReg ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; GlobalBaseReg = RegInfo . createVirtualRegister ( & SP :: IntRegsRegClass ) ; DebugLoc dl = DebugLoc :: getUnknownLoc ( ) ; BuildMI ( FirstMBB , MBBI , dl , get ( SP :: GETPCX ) , GlobalBaseReg ) ; SparcFI -> setGlobalBaseReg ( GlobalBaseReg ) ; return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

Sparc Sparc Sparc Sparc Sparc Sparc 0 SP::IntRegsRegClass SP::GETPCX Sparc


<s> const TargetRegisterClass * SIInstrInfo :: getOpRegClass ( const MachineInstr & MI , unsigned OpNo ) const { const MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const MCInstrDesc & Desc = get ( MI . getOpcode ( ) ) ; if ( MI . isVariadic ( ) || OpNo >= Desc . getNumOperands ( ) || Desc . OpInfo [ OpNo ] . RegClass == - 1 ) { unsigned Reg = MI . getOperand ( OpNo ) . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) return MRI . getRegClass ( Reg ) ; return RI . getPhysRegClass ( Reg ) ; } unsigned RCID = Desc . OpInfo [ OpNo ] . RegClass ; return RI . getRegClass ( RCID ) ; } </s>

Return the correct register class for OpNo .


<s> static rtx emit_memset ( rtx destmem , rtx destptr , rtx promoted_val , HOST_WIDE_INT size_to_move ) { rtx dst = destmem , adjust ; enum insn_code code ; machine_mode move_mode ; int piece_size , i ; move_mode = GET_MODE ( promoted_val ) ; if ( move_mode == VOIDmode ) move_mode = QImode ; if ( size_to_move < GET_MODE_SIZE ( move_mode ) ) { move_mode = mode_for_size ( size_to_move * BITS_PER_UNIT , MODE_INT , 0 ) ; promoted_val = gen_lowpart ( move_mode , promoted_val ) ; } piece_size = GET_MODE_SIZE ( move_mode ) ; code = optab_handler ( mov_optab , move_mode ) ; gcc_assert ( code != CODE_FOR_nothing && promoted_val != NULL_RTX ) ; dst = adjust_automodify_address_nv ( dst , move_mode , destptr , 0 ) ; gcc_assert ( size_to_move % piece_size == 0 ) ; adjust = GEN_INT ( piece_size ) ; for ( i = 0 ; i < size_to_move ; i += piece_size ) { if ( piece_size <= GET_MODE_SIZE ( word_mode ) ) { emit_insn ( gen_strset ( destptr , dst , promoted_val ) ) ; dst = adjust_automodify_address_nv ( dst , move_mode , destptr , piece_size ) ; continue ; } emit_insn ( GEN_FCN ( code ) ( dst , promoted_val ) ) ; emit_move_insn ( destptr , gen_rtx_PLUS ( Pmode , copy_rtx ( destptr ) , adjust ) ) ; dst = adjust_automodify_address_nv ( dst , move_mode , destptr , piece_size ) ; } return dst ; } </s>

This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM with value PROMOTED_VAL . SRC is passed by pointer to be updated on return . Return value is updated DST .


<s> bool AArch64TTIImpl :: shouldConsiderAddressTypePromotion ( const Instruction & I , bool & AllowPromotionWithoutCommonHeader ) { bool Considerable = false ; AllowPromotionWithoutCommonHeader = false ; if ( ! isa < SExtInst > ( & I ) ) return false ; Type * ConsideredSExtType = Type :: getInt64Ty ( I . getParent ( ) -> getParent ( ) -> getContext ( ) ) ; if ( I . getType ( ) != ConsideredSExtType ) return false ; for ( const User * U : I . users ( ) ) { if ( const GetElementPtrInst * GEPInst = dyn_cast < GetElementPtrInst > ( U ) ) { Considerable = true ; if ( GEPInst -> getNumOperands ( ) > 2 ) { AllowPromotionWithoutCommonHeader = true ; break ; } } } return Considerable ; } </s>

See if I should be considered for address type promotion .


<s>
bool
HexagonExpandCondsets
::
split
(
MachineInstr
*
MI
)
{
if
(
TfrLimitActive
)
{
if
(
TfrCounter
>=
TfrLimit
)
return
false
;
TfrCounter
++
;
}
DEBUG
(
dbgs
(
)
<<
"\nsplitting BB#"
<<
MI
->
getParent
(
)
->
getNumber
(
)
<<
": "
<<
*
MI
)
;
MachineOperand
&
MD
=
MI
->
getOperand
(
0
)
;
MachineOperand
&
MP
=
MI
->
getOperand
(
1
)
;
assert
(
MD
.
isDef
(
)
)
;
unsigned
DR
=
MD
.
getReg
(
)
,
DSR
=
MD
.
getSubReg
(
)
;
if
(
MachineInstr
*
TfrT
=
genTfrFor
(
MI
->
getOperand
(
2
)
,
DR
,
DSR
,
MP
,
true
)
)
addInstrToLiveness
(
TfrT
)
;
if
(
MachineInstr
*
TfrF
=
genTfrFor
(
MI
->
getOperand
(
3
)
,
DR
,
DSR
,
MP
,
false
)
)
addInstrToLiveness
(
TfrF
)
;
removeInstrFromLiveness
(
MI
)
;
return
true
;
}
</s>

Split into substrings around the occurrences of a separator character .


<s> static rtx nios2_expand_ldstio_builtin ( tree exp , rtx target , const struct nios2_builtin_desc * d ) { bool has_target_p ; rtx addr , mem , val ; struct expand_operand ops [ MAX_RECOG_OPERANDS ] ; machine_mode mode = insn_data [ d -> icode ] . operand [ 0 ] . mode ; addr = expand_normal ( CALL_EXPR_ARG ( exp , 0 ) ) ; mem = gen_rtx_MEM ( mode , addr ) ; if ( insn_data [ d -> icode ] . operand [ 0 ] . allows_mem ) { val = expand_normal ( CALL_EXPR_ARG ( exp , 1 ) ) ; if ( CONST_INT_P ( val ) ) val = force_reg ( mode , gen_int_mode ( INTVAL ( val ) , mode ) ) ; val = simplify_gen_subreg ( mode , val , GET_MODE ( val ) , 0 ) ; create_output_operand ( & ops [ 0 ] , mem , mode ) ; create_input_operand ( & ops [ 1 ] , val , mode ) ; has_target_p = false ; } else { create_output_operand ( & ops [ 0 ] , target , mode ) ; create_input_operand ( & ops [ 1 ] , mem , mode ) ; has_target_p = true ; } return nios2_expand_builtin_insn ( d , 2 , ops , has_target_p ) ; } </s>

Expand ldio/stio form load-store instruction builtins .


<s> int typemap_cmp ( const void * key , const void * entry ) { return strcmp ( ( const char * ) key , ( ( const typemap * ) entry ) -> key ) ; } </s>

Comparator for bsearch on the type map .


<s> void SPUTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; } </s>

Lower the specified operand into the Ops vector .


<s>
static
void
initialize_aarch64_code_model
(
void
)
{
if
(
flag_pic
)
{
switch
(
aarch64_cmodel_var
)
{
case
AARCH64_CMODEL_TINY
:
aarch64_cmodel
=
AARCH64_CMODEL_TINY_PIC
;
break
;
case
AARCH64_CMODEL_SMALL
:
aarch64_cmodel
=
AARCH64_CMODEL_SMALL_PIC
;
break
;
case
AARCH64_CMODEL_LARGE
:
sorry
(
"code model %qs with -f%s"
,
"large"
,
flag_pic
>
1
"PIC"
:
"pic"
)
;
default
:
gcc_unreachable
(
)
;
}
}
else
aarch64_cmodel
=
aarch64_cmodel_var
;
}
</s>

A checking mechanism for the implementation of the various code models .

aarch64
"code model %qs with -f%s"
"large"
1
"PIC"
"pic"


"internal compiler error.  Incorrect shift:"

8bit arithmetic shift right ( ( signed char ) x > > i )


<s> nvptx_function_end ( STREAM ) { \ "%hr0" , "%outargs" , "%hfp" , "%punbuffer" , "%retval" , "%retval_in" , "%hr6" , "%hr7" , \ "%hr8" , "%hr9" , "%hr10" , "%hr11" , "%hr12" , "%hr13" , "%argp" , "%frame" \ } do \ { \ char * __p ; \ __p = stpcpy ( & ( LABEL ) [ 1 ] , PREFIX ) ; \ ( LABEL ) [ 0 ] = '$' ; \ sprint_ul ( __p , ( unsigned long ) ( NUM ) ) ; \ } </s>

Terminate a function by writing a closing brace to FILE .


<s> bool NVPTXDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & static_cast < const NVPTXSubtarget & > ( MF . getSubtarget ( ) ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool X86FastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Load : return X86SelectLoad ( I ) ; case Instruction :: Store : return X86SelectStore ( I ) ; case Instruction :: Ret : return X86SelectRet ( I ) ; case Instruction :: ICmp : case Instruction :: FCmp : return X86SelectCmp ( I ) ; case Instruction :: ZExt : return X86SelectZExt ( I ) ; case Instruction :: Br : return X86SelectBranch ( I ) ; case Instruction :: LShr : case Instruction :: AShr : case Instruction :: Shl : return X86SelectShift ( I ) ; case Instruction :: SDiv : case Instruction :: UDiv : case Instruction :: SRem : case Instruction :: URem : return X86SelectDivRem ( I ) ; case Instruction :: Select : return X86SelectSelect ( I ) ; case Instruction :: Trunc : return X86SelectTrunc ( I ) ; case Instruction :: FPExt : return X86SelectFPExt ( I ) ; case Instruction :: FPTrunc : return X86SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return X86SelectSIToFP ( I ) ; case Instruction :: IntToPtr : case Instruction :: PtrToInt : { EVT SrcVT = TLI . getValueType ( DL , I -> getOperand ( 0 ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) ; if ( DstVT . bitsGT ( SrcVT ) ) return X86SelectZExt ( I ) ; if ( DstVT . bitsLT ( SrcVT ) ) return X86SelectTrunc ( I ) ; unsigned Reg = getRegForValue ( I -> getOperand ( 0 ) ) ; if ( Reg == 0 ) return false ; updateValueMap ( I , Reg ) ; return true ; } } return false ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> void print_operand_address ( FILE * file , rtx x ) { if ( REG_P ( x ) ) fprintf ( file , "0(%s)" , reg_names [ REGNO ( x ) ] ) ; else if ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == CONST || GET_CODE ( x ) == LABEL_REF ) { output_addr_const ( file , x ) ; if ( small_data_operand ( x , GET_MODE ( x ) ) ) fprintf ( file , "@%s(%s)" , SMALL_DATA_RELOC , reg_names [ SMALL_DATA_REG ] ) ; else gcc_assert ( ! TARGET_TOC ) ; } else if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , 0 ) ) && REG_P ( XEXP ( x , 1 ) ) ) { if ( REGNO ( XEXP ( x , 0 ) ) == 0 ) fprintf ( file , "%s,%s" , reg_names [ REGNO ( XEXP ( x , 1 ) ) ] , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; else fprintf ( file , "%s,%s" , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] , reg_names [ REGNO ( XEXP ( x , 1 ) ) ] ) ; } else if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , 0 ) ) && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) fprintf ( file , HOST_WIDE_INT_PRINT_DEC "(%s)" , INTVAL ( XEXP ( x , 1 ) ) , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; else if ( GET_CODE ( x ) == LO_SUM && REG_P ( XEXP ( x , 0 ) ) && CONSTANT_P ( XEXP ( x , 1 ) ) ) { fprintf ( file , "lo16(" ) ; output_addr_const ( file , XEXP ( x , 1 ) ) ; fprintf ( file , ")(%s)" , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; } else if ( GET_CODE ( x ) == LO_SUM && REG_P ( XEXP ( x , 0 ) ) && CONSTANT_P ( XEXP ( x , 1 ) ) ) { output_addr_const ( file , XEXP ( x , 1 ) ) ; fprintf ( file , "@l(%s)" , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; } else if ( toc_relative_expr_p ( x , false ) ) { output_addr_const ( file , CONST_CAST_RTX ( tocrel_base ) ) ; if ( GET_CODE ( x ) == LO_SUM ) fprintf ( file , "@l(%s)" , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; else fprintf ( file , "(%s)" , reg_names [ REGNO ( XVECEXP ( tocrel_base , 0 , 1 ) ) ] ) ; } else gcc_unreachable ( ) ; } </s>

Print the operand address represented by the rtx addr


<s>
StringRef
getPassName
(
)
const
override
{
return
"DXIL Op Lowering"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> TargetFrameLowering :: DwarfFrameBase NVPTXFrameLowering :: getDwarfFrameBase ( const MachineFunction & MF ) const { return { DwarfFrameBase :: CFA , { 0 } } ; } </s>

Return the frame base information to be encoded in the DWARF subprogram debug info .


<s>
void
SystemZOperand
::
print
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
break
;
case
KindToken
:
OS
<<
"Token:"
<<
getToken
(
)
;
break
;
case
KindReg
:
OS
<<
"Reg:"
<<
SystemZInstPrinter
::
getRegisterName
(
getReg
(
)
)
;
break
;
case
KindImm
:
OS
<<
"Imm:"
;
printMCExpr
(
getImm
(
)
,
OS
)
;
break
;
case
KindImmTLS
:
OS
<<
"ImmTLS:"
;
printMCExpr
(
getImmTLS
(
)
.
Imm
,
OS
)
;
if
(
getImmTLS
(
)
.
Sym
)
{
OS
<<
", "
;
printMCExpr
(
getImmTLS
(
)
.
Sym
,
OS
)
;
}
break
;
case
KindMem
:
{
const
MemOp
&
Op
=
getMem
(
)
;
OS
<<
"Mem:"
<<
*
cast
<
MCConstantExpr
>
(
Op
.
Disp
)
;
if
(
Op
.
Base
)
{
OS
<<
"("
;
if
(
Op
.
MemKind
==
BDLMem
)
OS
<<
*
cast
<
MCConstantExpr
>
(
Op
.
Length
.
Imm
)
<<
","
;
else
if
(
Op
.
MemKind
==
BDRMem
)
OS
<<
SystemZInstPrinter
::
getRegisterName
(
Op
.
Length
.
Reg
)
<<
","
;
if
(
Op
.
Index
)
OS
<<
SystemZInstPrinter
::
getRegisterName
(
Op
.
Index
)
<<
","
;
OS
<<
SystemZInstPrinter
::
getRegisterName
(
Op
.
Base
)
;
OS
<<
")"
;
}
break
;
}
case
KindInvalid
:
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

SystemZ
SystemZ
"Token:"
"Reg:"
SystemZ
"Imm:"
"ImmTLS:"
", "
"Mem:"
"("
","
SystemZ
","
SystemZ
","
SystemZ
")"


<s> unsigned SIRegisterInfo :: reservedPrivateSegmentBufferReg ( const MachineFunction & MF ) const { unsigned BaseIdx = alignDown ( getMaxNumSGPRs ( MF ) , 4 ) - 4 ; unsigned BaseReg ( AMDGPU :: SGPR_32RegClass . getRegister ( BaseIdx ) ) ; return getMatchingSuperReg ( BaseReg , AMDGPU :: sub0 , & AMDGPU :: SReg_128RegClass ) ; } </s>

Return the end register initially reserved for the scratch buffer in case spilling is needed .


Relax the instruction in the given fragment to the next wider instruction .


<s> void ix86_avx_emit_vzeroupper ( HARD_REG_SET regs_live ) { int i ; for ( i = FIRST_SSE_REG ; i <= LAST_SSE_REG ; i ++ ) if ( TEST_HARD_REG_BIT ( regs_live , i ) && ! call_used_regs [ i ] ) return ; if ( TARGET_64BIT ) for ( i = FIRST_REX_SSE_REG ; i <= LAST_REX_SSE_REG ; i ++ ) if ( TEST_HARD_REG_BIT ( regs_live , i ) && ! call_used_regs [ i ] ) return ; emit_insn ( gen_avx_vzeroupper ( ) ) ; } </s>


<s> static bool avr_addr_space_subset_p ( addr_space_t subset ATTRIBUTE_UNUSED , addr_space_t superset ATTRIBUTE_UNUSED ) { return true ; } </s>

Implement ` TARGET_ADDR_SPACE_SUBSET_P ' .


<s> unsigned getNumFixupKinds ( ) const override { return 1 ; } </s>

Get the number of target specific fixup kinds .


<s> TargetLowering :: ConstraintWeight MipsTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; const Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'd' : case 'y' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> const TargetRegisterClass * SIRegisterInfo :: getCFGStructurizerRegClass ( MVT VT ) const { switch ( VT . SimpleTy ) { default : case MVT :: i32 : return & AMDGPU :: VGPR_32RegClass ; } } </s>

get the register class of the specified type to use in the CFGStructurizer


<s> virtual const MandarinInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> bool legitimate_constant_p ( rtx x ) { switch ( GET_CODE ( x ) ) { case CONST : x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == PLUS ) { if ( GET_CODE ( XEXP ( x , 1 ) ) != CONST_INT ) return false ; x = XEXP ( x , 0 ) ; } if ( TARGET_MACHO && darwin_local_data_pic ( x ) ) return true ; if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , 1 ) ) { case UNSPEC_GOTOFF : return TARGET_64BIT ; case UNSPEC_TPOFF : case UNSPEC_NTPOFF : x = XVECEXP ( x , 0 , 0 ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_EXEC ) ; case UNSPEC_DTPOFF : x = XVECEXP ( x , 0 , 0 ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_DYNAMIC ) ; default : return false ; } if ( GET_CODE ( x ) == LABEL_REF ) return true ; if ( GET_CODE ( x ) != SYMBOL_REF ) return false ; case SYMBOL_REF : if ( SYMBOL_REF_TLS_MODEL ( x ) ) return false ; break ; default : break ; } return true ; } </s>

Nonzero if the constant value X is a legitimate general operand . It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE .


<s> bool AArch64AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { return AsmPrinter :: runOnMachineFunction ( MF ) ; } </s>


<s> static void sparc_init_pic_reg ( void ) { edge entry_edge ; rtx_insn * seq ; if ( ! flag_pic || ( ! crtl -> uses_pic_offset_table && ! optimize ) ) return ; start_sequence ( ) ; load_got_register ( ) ; if ( ! TARGET_VXWORKS_RTP ) emit_move_insn ( pic_offset_table_rtx , got_register_rtx ) ; seq = get_insns ( ) ; end_sequence ( ) ; entry_edge = single_succ_edge ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) ; insert_insn_on_edge ( seq , entry_edge ) ; commit_one_edge_insertion ( entry_edge ) ; } </s>


<s> static int rs6000_darwin64_struct_check_p ( machine_mode mode , const_tree type ) { return rs6000_darwin64_abi && ( ( mode == BLKmode && TREE_CODE ( type ) == RECORD_TYPE && int_size_in_bytes ( type ) > 0 ) || ( type && TREE_CODE ( type ) == RECORD_TYPE && int_size_in_bytes ( type ) == 8 ) ) ? 1 : 0 ; } </s>

Check for an item that needs to be considered specially under the darwin 64 bit ABI . These are record types where the mode is BLK or the structure is 8 bytes in size .


<s> bool NVPTXReplaceImageHandles :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; InstrsToRemove . clear ( ) ; for ( MachineBasicBlock & MBB : MF ) for ( MachineInstr & MI : MBB ) Changed |= processInstr ( MI ) ; for ( MachineInstr * MI : InstrsToRemove ) { unsigned DefReg = MI -> getOperand ( 0 ) . getReg ( ) ; if ( MF . getRegInfo ( ) . use_nodbg_empty ( DefReg ) ) MI -> eraseFromParent ( ) ; } return Changed ; } </s>


<s> static void ATTRIBUTE_UNUSED nios2_init_libfuncs ( void ) { init_sync_libfuncs ( UNITS_PER_WORD ) ; } </s>


<s> const uint32_t * SparcRegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { return CSR_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static void v850_conditional_register_usage ( void ) { if ( TARGET_APP_REGS ) { fixed_regs [ 2 ] = 0 ; call_used_regs [ 2 ] = 0 ; fixed_regs [ 5 ] = 0 ; call_used_regs [ 5 ] = 1 ; } } </s>

Worker function for TARGET_CONDITIONAL_REGISTER_USAGE . If TARGET_APP_REGS is not defined then add r2 and r5 to the pool of fixed registers . See PR 14505 .


<s> static void ix86_emit_probe_stack_range ( HOST_WIDE_INT first , HOST_WIDE_INT size , const bool int_registers_saved ) { const HOST_WIDE_INT probe_interval = get_probe_interval ( ) ; if ( size <= 6 * probe_interval ) { HOST_WIDE_INT i ; for ( i = probe_interval ; i < size ; i += probe_interval ) emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + i ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + size ) ) ) ; } else { gcc_assert ( int_registers_saved ) ; HOST_WIDE_INT rounded_size , last ; struct scratch_reg sr ; get_scratch_register_on_entry ( & sr ) ; rounded_size = ROUND_DOWN ( size , probe_interval ) ; emit_move_insn ( sr . reg , GEN_INT ( - first ) ) ; last = first + rounded_size ; emit_insn ( gen_probe_stack_range ( Pmode , sr . reg , sr . reg , GEN_INT ( - last ) ) ) ; if ( size != rounded_size ) emit_stack_probe ( plus_constant ( Pmode , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , sr . reg ) , rounded_size - size ) ) ; release_scratch_register_on_entry ( & sr , size , true ) ; } emit_insn ( gen_blockage ( ) ) ; } </s>

Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE , inclusive . These are offsets from the current stack pointer .


<s>
SDValue
MipsSETargetLowering
::
PerformDAGCombine
(
SDNode
*
N
,
DAGCombinerInfo
&
DCI
)
const
{
SelectionDAG
&
DAG
=
DCI
.
DAG
;
SDValue
Val
;
switch
(
N
->
getOpcode
(
)
)
{
case
ISD
::
ADDE
:
return
performADDECombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
case
ISD
::
AND
:
Val
=
performANDCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
break
;
case
ISD
::
OR
:
Val
=
performORCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
break
;
case
ISD
::
SUBE
:
return
performSUBECombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
case
ISD
::
MUL
:
return
performMULCombine
(
N
,
DAG
,
DCI
,
this
)
;
case
ISD
::
SHL
:
return
performSHLCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
case
ISD
::
SRA
:
return
performSRACombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
case
ISD
::
SRL
:
return
performSRLCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
case
ISD
::
VSELECT
:
return
performVSELECTCombine
(
N
,
DAG
)
;
case
ISD
::
XOR
:
Val
=
performXORCombine
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SETCC
:
Val
=
performSETCCCombine
(
N
,
DAG
)
;
break
;
}
if
(
Val
.
getNode
(
)
)
{
DEBUG
(
dbgs
(
)
<<
"\nMipsSE DAG Combine:\n"
;
N
->
printrWithDepth
(
dbgs
(
)
,
&
DAG
)
;
dbgs
(
)
<<
"\n=> \n"
;
Val
.
getNode
(
)
->
printrWithDepth
(
dbgs
(
)
,
&
DAG
)
;
dbgs
(
)
<<
"\n"
)
;
return
Val
;
}
return
MipsTargetLowering
::
PerformDAGCombine
(
N
,
DCI
)
;
}
</s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips
Mips
ISD::ADDE
ISD::AND
ISD::OR
ISD::SUBE
ISD::MUL
ISD::SHL
ISD::SRA
ISD::SRL
ISD::VSELECT
ISD::XOR
ISD::SETCC
"\nMipsSE DAG Combine:\n"
"\n=> \n"
"\n"
Mips


<s>
StringRef
RISCVMCExpr
::
getVariantKindName
(
VariantKind
Kind
)
{
switch
(
Kind
)
{
case
VK_RISCV_Invalid
:
case
VK_RISCV_None
:
llvm_unreachable
(
"Invalid ELF symbol kind"
)
;
case
VK_RISCV_LO
:
return
"lo"
;
case
VK_RISCV_HI
:
return
"hi"
;
case
VK_RISCV_PCREL_LO
:
return
"pcrel_lo"
;
case
VK_RISCV_PCREL_HI
:
return
"pcrel_hi"
;
case
VK_RISCV_GOT_HI
:
return
"got_pcrel_hi"
;
case
VK_RISCV_TPREL_LO
:
return
"tprel_lo"
;
case
VK_RISCV_TPREL_HI
:
return
"tprel_hi"
;
case
VK_RISCV_TPREL_ADD
:
return
"tprel_add"
;
case
VK_RISCV_TLS_GOT_HI
:
return
"tls_ie_pcrel_hi"
;
case
VK_RISCV_TLS_GD_HI
:
return
"tls_gd_pcrel_hi"
;
case
VK_RISCV_CALL
:
return
"call"
;
case
VK_RISCV_CALL_PLT
:
return
"call_plt"
;
case
VK_RISCV_32_PCREL
:
return
"32_pcrel"
;
}
llvm_unreachable
(
"Invalid ELF symbol kind"
)
;
}
</s>

Convert the variant kind into an ELF-appropriate modifier ( e.g .

RISCV
RISCV
RISCV
RISCV
"Invalid ELF symbol kind"
RISCV
"lo"
RISCV
"hi"
RISCV
"pcrel_lo"
RISCV
"pcrel_hi"
RISCV
"got_pcrel_hi"
RISCV
"tprel_lo"
RISCV
"tprel_hi"
RISCV
"tprel_add"
RISCV
"tls_ie_pcrel_hi"
RISCV
"tls_gd_pcrel_hi"
RISCV
"call"
RISCV
"call_plt"
RISCV
"32_pcrel"
"Invalid ELF symbol kind"


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> static enum ivms_arg_type ia64_arg_type ( machine_mode mode ) { switch ( mode ) { case SFmode : return FS ; case DFmode : return FT ; default : return I64 ; } } </s>

Return ivms_arg_type based on machine_mode .


"Don't know how to handle that operation"


<s> static void rs6000_emit_msub ( rtx target , rtx m1 , rtx m2 , rtx a ) { machine_mode mode = GET_MODE ( target ) ; rtx dst ; if ( optab_handler ( fms_optab , mode ) != CODE_FOR_nothing ) dst = expand_ternary_op ( mode , fms_optab , m1 , m2 , a , target , 0 ) ; else { a = expand_unop ( mode , neg_optab , a , NULL_RTX , 0 ) ; dst = expand_ternary_op ( mode , fma_optab , m1 , m2 , a , target , 0 ) ; } gcc_assert ( dst != NULL ) ; if ( dst != target ) emit_move_insn ( target , dst ) ; } </s>

Generate a FMSUB instruction : dst = fma ( m1 , m2 , -a ) .


<s> BitVector BPFRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , BPF :: W10 ) ; markSuperRegs ( Reserved , BPF :: W11 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> MachineInstr * AlphaInstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , int FrameIndex ) const { if ( Ops . size ( ) != 1 ) return NULL ; unsigned Opc = MI -> getOpcode ( ) ; MachineInstr * NewMI = NULL ; switch ( Opc ) { default : break ; case Alpha :: BISr : case Alpha :: CPYSS : case Alpha :: CPYST : if ( MI -> getOperand ( 1 ) . getReg ( ) == MI -> getOperand ( 2 ) . getReg ( ) ) { if ( Ops [ 0 ] == 0 ) { unsigned InReg = MI -> getOperand ( 1 ) . getReg ( ) ; bool isKill = MI -> getOperand ( 1 ) . isKill ( ) ; Opc = ( Opc == Alpha :: BISr ) ? Alpha :: STQ : ( ( Opc == Alpha :: CPYSS ) ? Alpha :: STS : Alpha :: STT ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( Opc ) ) . addReg ( InReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addReg ( Alpha :: F31 ) ; } else { unsigned OutReg = MI -> getOperand ( 0 ) . getReg ( ) ; bool isDead = MI -> getOperand ( 0 ) . isDead ( ) ; Opc = ( Opc == Alpha :: BISr ) ? Alpha :: LDQ : ( ( Opc == Alpha :: CPYSS ) ? Alpha :: LDS : Alpha :: LDT ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( Opc ) ) . addReg ( OutReg , RegState :: Define | getDeadRegState ( isDead ) ) . addFrameIndex ( FrameIndex ) . addReg ( Alpha :: F31 ) ; } } break ; } return NewMI ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> static bool ia64_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { if ( size == POINTER_SIZE / BITS_PER_UNIT && ! ( TARGET_NO_PIC || TARGET_AUTO_PIC ) && GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( x ) ) { static const char * const directive [ 2 ] [ 2 ] = { { "\tdata8.ua\t@fptr(" , "\tdata4.ua\t@fptr(" } , { "\tdata8\t@fptr(" , "\tdata4\t@fptr(" } } ; fputs ( directive [ ( aligned_p != 0 ) ] [ POINTER_SIZE == 32 ] , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; fputs ( ")\n" , asm_out_file ) ; return true ; } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . Handle word-sized aligned objects and detect the cases when @ fptr is needed .


<s> void m32r_init ( void ) { init_reg_tables ( ) ; memset ( m32r_punct_chars , 0 , sizeof ( m32r_punct_chars ) ) ; m32r_punct_chars [ '#' ] = 1 ; m32r_punct_chars [ '@' ] = 1 ; if ( ! g_switch_set ) g_switch_value = SDATA_DEFAULT_SIZE ; } </s>

Called by OVERRIDE_OPTIONS to initialize various things .


<s> static void lm32_block_move_inline ( rtx dest , rtx src , HOST_WIDE_INT length , HOST_WIDE_INT alignment ) { HOST_WIDE_INT offset , delta ; unsigned HOST_WIDE_INT bits ; int i ; machine_mode mode ; rtx * regs ; switch ( alignment ) { case 1 : bits = 8 ; break ; case 2 : bits = 16 ; break ; default : bits = 32 ; break ; } mode = int_mode_for_size ( bits , 0 ) . require ( ) ; delta = bits / BITS_PER_UNIT ; regs = XALLOCAVEC ( rtx , length / delta ) ; for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) { regs [ i ] = gen_reg_rtx ( mode ) ; emit_move_insn ( regs [ i ] , adjust_address ( src , mode , offset ) ) ; } for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) emit_move_insn ( adjust_address ( dest , mode , offset ) , regs [ i ] ) ; if ( offset < length ) { src = adjust_address ( src , BLKmode , offset ) ; dest = adjust_address ( dest , BLKmode , offset ) ; move_by_pieces ( dest , src , length - offset , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) , RETURN_BEGIN ) ; } } </s>

Emit straight-line code to move LENGTH bytes from SRC to DEST . Assume that the areas do not overlap .


<s>
BitVector
ARMBaseRegisterInfo
::
getReservedRegs
(
const
MachineFunction
&
MF
)
const
{
const
ARMSubtarget
&
STI
=
MF
.
getSubtarget
<
ARMSubtarget
>
(
)
;
const
ARMFrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
BitVector
Reserved
(
getNumRegs
(
)
)
;
markSuperRegs
(
Reserved
,
ARM
::
SP
)
;
markSuperRegs
(
Reserved
,
ARM
::
PC
)
;
markSuperRegs
(
Reserved
,
ARM
::
FPSCR
)
;
markSuperRegs
(
Reserved
,
ARM
::
APSR_NZCV
)
;
if
(
TFI
->
hasFP
(
MF
)
)
markSuperRegs
(
Reserved
,
getFramePointerReg
(
STI
)
)
;
if
(
hasBasePointer
(
MF
)
)
markSuperRegs
(
Reserved
,
BasePtr
)
;
if
(
STI
.
isR9Reserved
(
)
)
markSuperRegs
(
Reserved
,
ARM
::
R9
)
;
if
(
!
STI
.
hasVFP3
(
)
||
STI
.
hasD16
(
)
)
{
static_assert
(
ARM
::
D31
==
ARM
::
D16
+
15
,
"Register list not consecutive!"
)
;
for
(
unsigned
R
=
0
;
R
<
16
;
++
R
)
markSuperRegs
(
Reserved
,
ARM
::
D16
+
R
)
;
}
const
TargetRegisterClass
&
RC
=
ARM
::
GPRPairRegClass
;
for
(
unsigned
Reg
:
RC
)
for
(
MCSubRegIterator
SI
(
Reg
,
this
)
;
SI
.
isValid
(
)
;
++
SI
)
if
(
Reserved
.
test
(
*
SI
)
)
markSuperRegs
(
Reserved
,
Reg
)
;
assert
(
checkAllSuperRegsMarked
(
Reserved
)
)
;
return
Reserved
;
}
</s>


<s> const RegisterBankInfo * ARMSubtarget :: getRegBankInfo ( ) const { return RegBankInfo . get ( ) ; } </s>

If the information for the register banks is available , return it .


<s> unsigned MCS51InstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { case MCS51 :: LDDRdPtrQ : case MCS51 :: LDDWRdYQ : { if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } default : break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> bool FPGATTIImpl :: isTypeLegal ( Type * Ty ) { return true ; } </s>


<s> bool empty ( ) const { return ! BitVector :: any ( ) ; } </s>

Determine whether this version information is empty ( e.g. , all version components are zero ) .


getTargetNodeName - This method returns the name of a target specific


"Relocation required in an instruction that we cannot encode!"

getMachineOpValue - Return binary encoding of operand .