<s>
void
MCS51AsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
adjustFixupValue
(
Fixup
,
Target
,
Value
,
&
Asm
.
getContext
(
)
)
;
if
(
Value
==
0
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
auto
NumBits
=
Info
.
TargetSize
+
Info
.
TargetOffset
;
auto
NumBytes
=
(
NumBits
/
8
)
+
(
(
NumBits
%
8
)
==
0
0
:
1
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
<
NumBytes
;
++
i
)
{
uint8_t
mask
=
(
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
)
;
Data
[
Offset
+
i
]
|=
mask
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static void emit_cfa_restores ( rtx cfa_restores ) { rtx_insn * insn = get_last_insn ( ) ; rtx * loc = & REG_NOTES ( insn ) ; while ( * loc ) loc = & XEXP ( * loc , 1 ) ; * loc = cfa_restores ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Append CFA_RESTORES to any existing REG_NOTES on the last insn .


<s> const uint32_t * X86RegisterInfo :: getNoPreservedMask ( ) const { return CSR_NoRegs_RegMask ; } </s>

Return a register mask that clobbers everything .


hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool AMDGPUCodeGenPrepare :: runOnFunction ( Function & F ) { if ( ! TM || skipFunction ( F ) ) return false ; ST = & TM -> getSubtarget < SISubtarget > ( F ) ; DA = & getAnalysis < DivergenceAnalysis > ( ) ; HasUnsafeFPMath = hasUnsafeFPMath ( F ) ; bool MadeChange = false ; for ( BasicBlock & BB : F ) { BasicBlock :: iterator Next ; for ( BasicBlock :: iterator I = BB . begin ( ) , E = BB . end ( ) ; I != E ; I = Next ) { Next = std :: next ( I ) ; MadeChange |= visit ( * I ) ; } } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> unsigned ARMAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand * AsmOp , unsigned Kind ) { ARMOperand * Op = static_cast < ARMOperand * > ( AsmOp ) ; if ( Kind == MCK__35_0 && Op -> isImm ( ) ) { const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op -> getImm ( ) ) ; if ( ! CE ) return Match_InvalidOperand ; if ( CE -> getValue ( ) == 0 ) return Match_Success ; } return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> unsigned AMDGPUAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & Op , unsigned Kind ) { AMDGPUOperand & Operand = ( AMDGPUOperand & ) Op ; switch ( Kind ) { case MCK_addr64 : return Operand . isAddr64 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_gds : return Operand . isGDS ( ) ? Match_Success : Match_InvalidOperand ; case MCK_glc : return Operand . isGLC ( ) ? Match_Success : Match_InvalidOperand ; case MCK_idxen : return Operand . isIdxen ( ) ? Match_Success : Match_InvalidOperand ; case MCK_offen : return Operand . isOffen ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SSrcB32 : return Operand . isSSrcB32 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SSrcF32 : return Operand . isSSrcF32 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SoppBrTarget : return Operand . isSoppBrTarget ( ) ? Match_Success : Match_InvalidOperand ; case MCK_VReg32OrOff : return Operand . isVReg32OrOff ( ) ? Match_Success : Match_InvalidOperand ; case MCK_InterpSlot : return Operand . isInterpSlot ( ) ? Match_Success : Match_InvalidOperand ; case MCK_Attr : return Operand . isInterpAttr ( ) ? Match_Success : Match_InvalidOperand ; case MCK_AttrChan : return Operand . isAttrChan ( ) ? Match_Success : Match_InvalidOperand ; default : return Match_InvalidOperand ; } } </s>


<s> struct machine_function * rs6000_init_machine_status ( void ) { stack_info . reload_completed = 0 ; return ggc_cleared_alloc < machine_function > ( ) ; } </s>

Functions to init , mark and free struct machine_function . These will be called , via pointer variables , from push_function_context and pop_function_context .


Output code to perform an acosh XFmode calculation .


<s> bool cris_return_address_on_stack_for_return ( void ) { return cfun -> machine -> return_type == CRIS_RETINSN_RET ? false : cris_return_address_on_stack ( ) ; } </s>

Accessor used in cris.md : return because cfun- > machine is n't available there .


<s> void AMDGPUInstructionSelector :: setupMF ( MachineFunction & MF , GISelKnownBits * KB , CodeGenCoverage & CoverageInfo , ProfileSummaryInfo * PSI , BlockFrequencyInfo * BFI , AAResults * AA ) { MRI = & MF . getRegInfo ( ) ; Subtarget = & MF . getSubtarget < GCNSubtarget > ( ) ; InstructionSelector :: setupMF ( MF , KB , CoverageInfo , PSI , BFI , AA ) ; } </s>


<s> static int num_insns_constant_gpr ( HOST_WIDE_INT value ) { if ( SIGNED_INTEGER_16BIT_P ( value ) ) return 1 ; else if ( ( value & 0xffff ) == 0 && ( value >> 31 == - 1 || value >> 31 == 0 ) ) return 1 ; else if ( TARGET_PREFIXED && SIGNED_INTEGER_34BIT_P ( value ) ) return 1 ; else if ( TARGET_POWERPC64 ) { HOST_WIDE_INT low = ( ( value & 0xffffffff ) ^ 0x80000000 ) - 0x80000000 ; HOST_WIDE_INT high = value >> 31 ; if ( high == 0 || high == - 1 ) return 2 ; high >>= 1 ; if ( low == 0 || low == high ) return num_insns_constant_gpr ( high ) + 1 ; else if ( high == 0 ) return num_insns_constant_gpr ( low ) + 1 ; else return ( num_insns_constant_gpr ( high ) + num_insns_constant_gpr ( low ) + 1 ) ; } else return 2 ; } </s>

Helper for num_insns_constant . Calculate number of instructions to load VALUE to a single gpr using combinations of addi , addis , ori , oris , sldi and rldimi instructions .


"Can't return value from vararg function in memory"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void alpha_expand_movmisalign ( machine_mode mode , rtx * operands ) { if ( MEM_P ( operands [ 1 ] ) ) { rtx tmp ; if ( register_operand ( operands [ 0 ] , mode ) ) tmp = operands [ 0 ] ; else tmp = gen_reg_rtx ( mode ) ; alpha_expand_unaligned_load ( tmp , operands [ 1 ] , 8 , 0 , 0 ) ; if ( tmp != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , tmp ) ; } else if ( MEM_P ( operands [ 0 ] ) ) { if ( ! reg_or_0_operand ( operands [ 1 ] , mode ) ) operands [ 1 ] = force_reg ( mode , operands [ 1 ] ) ; alpha_expand_unaligned_store ( operands [ 0 ] , operands [ 1 ] , 8 , 0 ) ; } else gcc_unreachable ( ) ; } </s>

Implement the movmisalign patterns . One of the operands is a memory that is not naturally aligned . Emit instructions to load it .


<s> unsigned AArch64TargetLowering :: getNumInterleavedAccesses ( VectorType * VecTy , const DataLayout & DL , bool UseScalable ) const { unsigned VecSize = UseScalable ? Subtarget -> getMinSVEVectorSizeInBits ( ) : 128 ; return std :: max < unsigned > ( 1 , ( DL . getTypeSizeInBits ( VecTy ) + 127 ) / VecSize ) ; } </s>

Returns the number of interleaved accesses that will be generated when lowering accesses of the given type .


<s>
void
BTFDebug
::
beginFunctionImpl
(
const
MachineFunction
*
MF
)
{
auto
*
SP
=
MF
->
getFunction
(
)
.
getSubprogram
(
)
;
auto
*
Unit
=
SP
->
getUnit
(
)
;
if
(
Unit
->
getEmissionKind
(
)
==
DICompileUnit
::
NoDebug
)
{
SkipInstruction
=
true
;
return
;
}
SkipInstruction
=
false
;
std
::
unordered_map
<
uint32_t
,
StringRef
>
FuncArgNames
;
for
(
const
DINode
*
DN
:
SP
->
getRetainedNodes
(
)
)
{
if
(
const
auto
*
DV
=
dyn_cast
<
DILocalVariable
>
(
DN
)
)
{
uint32_t
Arg
=
DV
->
getArg
(
)
;
if
(
Arg
)
{
visitTypeEntry
(
DV
->
getType
(
)
)
;
FuncArgNames
[
Arg
]
=
DV
->
getName
(
)
;
}
}
}
uint32_t
ProtoTypeId
;
visitSubroutineType
(
SP
->
getType
(
)
,
true
,
FuncArgNames
,
ProtoTypeId
)
;
auto
FuncTypeEntry
=
llvm
::
make_unique
<
BTFTypeFunc
>
(
SP
->
getName
(
)
,
ProtoTypeId
)
;
uint32_t
FuncTypeId
=
addType
(
std
::
move
(
FuncTypeEntry
)
)
;
MCSymbol
*
FuncLabel
=
Asm
->
getFunctionBegin
(
)
;
BTFFuncInfo
FuncInfo
;
FuncInfo
.
Label
=
FuncLabel
;
FuncInfo
.
TypeId
=
FuncTypeId
;
if
(
FuncLabel
->
isInSection
(
)
)
{
MCSection
&
Section
=
FuncLabel
->
getSection
(
)
;
const
MCSectionELF
*
SectionELF
=
dyn_cast
<
MCSectionELF
>
(
&
Section
)
;
assert
(
SectionELF
&&
"Null section for Function Label"
)
;
SecNameOff
=
addString
(
SectionELF
->
getSectionName
(
)
)
;
}
else
{
SecNameOff
=
addString
(
".text"
)
;
}
FuncInfoTable
[
SecNameOff
]
.
push_back
(
FuncInfo
)
;
}
</s>

BPF
"Null section for Function Label"
".text"


<s> static bool arc_warn_func_return ( tree decl ) { struct function * func = DECL_STRUCT_FUNCTION ( decl ) ; unsigned int fn_type = arc_compute_function_type ( func ) ; return ! ARC_NAKED_P ( fn_type ) ; } </s>


<s> void MipsSEFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; const MipsSEInstrInfo & TII = * static_cast < const MipsSEInstrInfo * > ( STI . getInstrInfo ( ) ) ; const MipsRegisterInfo & RegInfo = * static_cast < const MipsRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; unsigned SP = ABI . GetStackPtr ( ) ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned ZERO = ABI . GetNullPtr ( ) ; unsigned MOVE = ABI . GetSPMoveOp ( ) ; if ( MFI . getStackSize ( ) == 0 && ! MFI . adjustsStack ( ) ) return ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI . getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , DL , TII . get ( MOVE ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( MipsFI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = ABI . ArePtrs64bit ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI . getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = 0 ; J < 4 ; ++ J ) { TII . loadRegFromStackSlot ( MBB , I , ABI . GetEhDataReg ( J ) , MipsFI -> getEhDataRegFI ( J ) , RC , & RegInfo ) ; } } if ( MF . getFunction ( ) . hasFnAttribute ( "interrupt" ) ) emitInterruptEpilogueStub ( MF , MBB ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize , MBB , MBBI ) ; } </s>


<s>
virtual
const
char
*
getPassName
(
)
const
override
{
return
"SI Lower il Copies"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool symbolic_reference_mentioned_p ( rtx op ) { const char * fmt ; int i ; if ( GET_CODE ( op ) == SYMBOL_REF || GET_CODE ( op ) == LABEL_REF ) return true ; fmt = GET_RTX_FORMAT ( GET_CODE ( op ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( op ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( op , i ) - 1 ; j >= 0 ; j -- ) if ( symbolic_reference_mentioned_p ( XVECEXP ( op , i , j ) ) ) return true ; } else if ( fmt [ i ] == 'e' && symbolic_reference_mentioned_p ( XEXP ( op , i ) ) ) return true ; } return false ; } </s>

Return true if OP contains a symbol reference


"LEG DAG->DAG Pattern Instruction Selection"


<s> static void mips_set_architecture ( const struct mips_cpu_info * info ) { if ( info != 0 ) { mips_arch_info = info ; mips_arch = info -> cpu ; mips_isa = info -> isa ; } } </s>

Set up globals to generate code for the ISA or processor described by INFO .


<s> void SICInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { if ( ! printAliasInstr ( MI , O ) ) printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> void CSKYConstantPoolJT :: print ( raw_ostream & O ) const { O << "JTI#" << JTI ; CSKYConstantPoolValue :: print ( O ) ; } </s>

print - Print a debug representation of the operand to the given stream .


<s> static bool frv_handle_option ( size_t code , const char * arg , int value ATTRIBUTE_UNUSED ) { switch ( code ) { case OPT_mcpu_ : if ( strcmp ( arg , "simple" ) == 0 ) frv_cpu_type = FRV_CPU_SIMPLE ; else if ( strcmp ( arg , "tomcat" ) == 0 ) frv_cpu_type = FRV_CPU_TOMCAT ; else if ( strcmp ( arg , "fr550" ) == 0 ) frv_cpu_type = FRV_CPU_FR550 ; else if ( strcmp ( arg , "fr500" ) == 0 ) frv_cpu_type = FRV_CPU_FR500 ; else if ( strcmp ( arg , "fr450" ) == 0 ) frv_cpu_type = FRV_CPU_FR450 ; else if ( strcmp ( arg , "fr405" ) == 0 ) frv_cpu_type = FRV_CPU_FR405 ; else if ( strcmp ( arg , "fr400" ) == 0 ) frv_cpu_type = FRV_CPU_FR400 ; else if ( strcmp ( arg , "fr300" ) == 0 ) frv_cpu_type = FRV_CPU_FR300 ; else if ( strcmp ( arg , "frv" ) == 0 ) frv_cpu_type = FRV_CPU_GENERIC ; else return false ; return true ; default : return true ; } } </s>


<s> static bool aarch64_pragma_target_parse ( tree args , tree pop_target ) { if ( args ) { if ( ! aarch64_process_target_attr ( args ) ) return false ; aarch64_override_options_internal ( & global_options ) ; } else { pop_target = pop_target ? pop_target : target_option_default_node ; cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( pop_target ) ) ; } target_option_current_node = build_target_option_node ( & global_options , & global_options_set ) ; aarch64_reset_previous_fndecl ( ) ; cpp_options * cpp_opts = cpp_get_options ( parse_in ) ; unsigned char saved_warn_unused_macros = cpp_opts -> warn_unused_macros ; cpp_opts -> warn_unused_macros = 0 ; cpp_force_token_locations ( parse_in , BUILTINS_LOCATION ) ; aarch64_update_cpp_builtins ( parse_in ) ; cpp_stop_forcing_token_locations ( parse_in ) ; cpp_opts -> warn_unused_macros = saved_warn_unused_macros ; if ( pop_target ) aarch64_save_restore_target_globals ( pop_target ) ; if ( TARGET_SIMD ) { tree saved_current_target_pragma = current_target_pragma ; current_target_pragma = NULL ; aarch64_init_simd_builtins ( ) ; current_target_pragma = saved_current_target_pragma ; } return true ; } </s>

Hook to validate the current # pragma GCC target and set the state , and update the macros based on what was changed . If ARGS is NULL , then POP_TARGET is used to reset the options .


<s> void Cpu0FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; Cpu0FunctionInfo * Cpu0FI = MF . getInfo < Cpu0FunctionInfo > ( ) ; const Cpu0InstrInfo & TII = * static_cast < const Cpu0InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; unsigned SP = Cpu0 :: SP ; unsigned FP = Cpu0 :: FP ; unsigned ZERO = Cpu0 :: ZERO ; unsigned ADDu = Cpu0 :: ADDu ; unsigned ADDiu = Cpu0 :: ADDiu ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( ADDu ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; if ( isInt < 16 > ( StackSize ) ) BuildMI ( MBB , MBBI , dl , TII . get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( StackSize ) ; else { Cpu0FI -> setEmitNOAT ( ) ; expandLargeImm ( SP , StackSize , TII , MBB , MBBI , dl ) ; } } </s>


<s> static bool nds32_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( regno > FIRST_PSEUDO_REGISTER ) return true ; if ( ( TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE ) && NDS32_IS_FPR_REGNUM ( regno ) ) { if ( NDS32_IS_EXT_FPR_REGNUM ( regno ) ) return ( NDS32_FPR_REGNO_OK_FOR_DOUBLE ( regno ) && ( mode == DFmode ) ) ; else if ( mode == SFmode || mode == SImode ) return NDS32_FPR_REGNO_OK_FOR_SINGLE ( regno ) ; else if ( mode == DFmode ) return NDS32_FPR_REGNO_OK_FOR_DOUBLE ( regno ) ; return false ; } if ( regno <= NDS32_LAST_GPR_REGNUM ) return ( targetm . hard_regno_nregs ( regno , mode ) == 1 || ! ( ( regno ) & 1 ) ) ; return false ; } </s>


<s> unsigned TeeRISCMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO ) const { if ( MO . isReg ( ) ) return getTeeRISCRegisterNumbering ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; if ( MO . isExpr ( ) ) return 0 ; errs ( ) << MO ; llvm_unreachable ( 0 ) ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s>
static
void
nds32_emit_section_head_template
(
char
section_name
[
]
,
char
symbol_name
[
]
,
int
align_value
,
bool
object_p
)
{
const
char
*
flags_str
;
const
char
*
type_str
;
flags_str
=
(
object_p
)
"\"a\""
:
"\"ax\""
;
type_str
=
(
object_p
)
"@object"
:
"@function"
;
fprintf
(
asm_out_file
,
"\t.section\t%s, %s\n"
,
section_name
,
flags_str
)
;
fprintf
(
asm_out_file
,
"\t.align\t%d\n"
,
align_value
)
;
fprintf
(
asm_out_file
,
"\t.global\t%s\n"
,
symbol_name
)
;
fprintf
(
asm_out_file
,
"\t.type\t%s, %s\n"
,
symbol_name
,
type_str
)
;
fprintf
(
asm_out_file
,
"%s:\n"
,
symbol_name
)
;
}
</s>

A helper function to emit section head template .


<s> static rtx nios2_legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED ) { if ( CONSTANT_P ( x ) ) return nios2_legitimize_constant_address ( x ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 1 ) ) == CONST ) { rtx unspec , offset ; split_const ( XEXP ( x , 1 ) , & unspec , & offset ) ; if ( GET_CODE ( unspec ) == UNSPEC && ! nios2_large_offset_p ( XINT ( unspec , 1 ) ) && offset != const0_rtx ) { rtx reg = force_reg ( Pmode , XEXP ( x , 0 ) ) ; unspec = copy_rtx ( unspec ) ; XVECEXP ( unspec , 0 , 0 ) = plus_constant ( Pmode , XVECEXP ( unspec , 0 , 0 ) , INTVAL ( offset ) ) ; x = gen_rtx_PLUS ( Pmode , reg , gen_rtx_CONST ( Pmode , unspec ) ) ; } } return x ; } </s>


"OpenRISC DAG->DAG Pattern Instruction Selection"


<s> static void frv_start_packet ( void ) { enum frv_insn_group group ; memset ( frv_packet . regstate , 0 , sizeof ( frv_packet . regstate ) ) ; frv_packet . num_mems = 0 ; frv_packet . num_insns = 0 ; for ( group = 0 ; group < NUM_GROUPS ; group ++ ) frv_packet . groups [ group ] . num_insns = 0 ; } </s>

Initialize frv_packet for the start of a new packet .


<s> OperandMatchResultTy AMDGPUAsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { bool Result = ParseRegister ( RegNo , StartLoc , EndLoc , true ) ; bool PendingErrors = getParser ( ) . hasPendingError ( ) ; getParser ( ) . clearPendingErrors ( ) ; if ( PendingErrors ) return MatchOperand_ParseFail ; if ( Result ) return MatchOperand_NoMatch ; return MatchOperand_Success ; } </s>

tryParseRegister - parse one register if possible


<s> int c4x_check_laj_p ( rtx insn ) { insn = prev_nonnote_insn ( insn ) ; if ( insn == 0 ) return 0 ; if ( GET_CODE ( insn ) == CODE_LABEL ) return 1 ; if ( c4x_r11_set_p ( insn ) ) return 1 ; return 0 ; } </s>

The c4x sometimes has a problem when the insn before the laj insn sets the r11 register . Check for this situation .


<s> static bool frv_io_fixed_order_p ( const struct frv_io * io1 , const struct frv_io * io2 ) { if ( io1 -> type == FRV_IO_WRITE && io2 -> type == FRV_IO_WRITE ) return true ; if ( io1 -> type != FRV_IO_WRITE && io2 -> type != FRV_IO_WRITE ) return false ; return frv_same_doubleword_p ( io1 , io2 ) ; } </s>

Return true if operations IO1 and IO2 are guaranteed to complete in order .


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> optForSize ( ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = & * I ++ ; if ( OptLevel != CodeGenOpt :: None && ( ( N -> getOpcode ( ) == X86ISD :: CALL && ! Subtarget -> callRegIndirect ( ) ) || ( N -> getOpcode ( ) == X86ISD :: TC_RETURN && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; moveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; MVT SrcVT = N -> getOperand ( 0 ) . getSimpleValueType ( ) ; MVT DstVT = N -> getSimpleValueType ( 0 ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const X86TargetLowering * X86Lowering = static_cast < const X86TargetLowering * > ( TLI ) ; bool SrcIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } MVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> MachineBasicBlock * getHeader ( ) const override { return Unit -> getHeader ( ) ; } </s>

The header is the entry for each iteration .


<s> bool M68kRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ; if ( CantUseSP ( MFI ) ) return MRI -> canReserveReg ( BasePtr ) ; return true ; } </s>

True if the stack can be realigned for the target .


<s>
static
bool
class_can_hold_mode
(
reg_class_t
rclass
,
machine_mode
mode
)
{
static
char
results
[
LIM_REG_CLASSES
]
[
MAX_MACHINE_MODE
]
;
if
(
results
[
(
int
)
rclass
]
[
mode
]
==
0
)
{
int
r
;
results
[
rclass
]
[
mode
]
=
1
;
for
(
r
=
0
;
r
<
FIRST_PSEUDO_REGISTER
;
r
++
)
if
(
in_hard_reg_set_p
(
reg_class_contents
[
(
int
)
rclass
]
,
mode
,
r
)
&&
m32c_hard_regno_mode_ok
(
r
,
mode
)
)
{
results
[
rclass
]
[
mode
]
=
2
;
break
;
}
}
fprintf
(
stderr
,
"class %s can hold %s? %s\n"
,
class_names
[
(
int
)
rclass
]
,
mode_name
[
mode
]
,
(
results
[
rclass
]
[
mode
]
==
2
)
"yes"
:
"no"
)
;
return
results
[
(
int
)
rclass
]
[
mode
]
==
2
;
}
</s>

Used by m32c_register_move_cost to determine if a move is impossibly expensive .


<s> bool X86InstrInfo :: shouldScheduleLoadsNear ( SDNode * Load1 , SDNode * Load2 , int64_t Offset1 , int64_t Offset2 , unsigned NumLoads ) const { assert ( Offset2 > Offset1 ) ; if ( ( Offset2 - Offset1 ) / 8 > 64 ) return false ; unsigned Opc1 = Load1 -> getMachineOpcode ( ) ; unsigned Opc2 = Load2 -> getMachineOpcode ( ) ; if ( Opc1 != Opc2 ) return false ; switch ( Opc1 ) { default : break ; case X86 :: LD_Fp32m : case X86 :: LD_Fp64m : case X86 :: LD_Fp80m : case X86 :: MMX_MOVD64rm : case X86 :: MMX_MOVQ64rm : return false ; } EVT VT = Load1 -> getValueType ( 0 ) ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : { if ( TM . getSubtargetImpl ( ) -> is64Bit ( ) ) { if ( NumLoads >= 3 ) return false ; } else if ( NumLoads ) return false ; break ; } case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : case MVT :: i64 : case MVT :: f32 : case MVT :: f64 : if ( NumLoads ) return false ; } return true ; } </s>

shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine ( in conjunction with areLoadsFromSameBasePtr ) if two loads should be scheduled togther .


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS , bool is64bit ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS , is64bit ) , DataLayout ( Subtarget . getDataLayout ( ) ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrInfo ( Subtarget ) , FrameLowering ( Subtarget ) { } </s>


<s> static rtx aarch64_gen_compare_reg_maybe_ze ( RTX_CODE code , rtx x , rtx y , machine_mode y_mode ) { if ( y_mode == E_QImode || y_mode == E_HImode ) { if ( CONST_INT_P ( y ) ) { y = GEN_INT ( INTVAL ( y ) & GET_MODE_MASK ( y_mode ) ) ; y_mode = SImode ; } else { rtx t , cc_reg ; machine_mode cc_mode ; t = gen_rtx_ZERO_EXTEND ( SImode , y ) ; t = gen_rtx_COMPARE ( CC_SWPmode , t , x ) ; cc_mode = CC_SWPmode ; cc_reg = gen_rtx_REG ( cc_mode , CC_REGNUM ) ; emit_set_insn ( cc_reg , t ) ; return cc_reg ; } } if ( ! aarch64_plus_operand ( y , y_mode ) ) y = force_reg ( y_mode , y ) ; return aarch64_gen_compare_reg ( code , x , y ) ; } </s>

Similarly , but maybe zero-extend Y if Y_MODE < SImode .


<s> int arc_address_cost ( rtx addr , machine_mode , addr_space_t , bool speed ) { switch ( GET_CODE ( addr ) ) { case REG : return speed || satisfies_constraint_Rcq ( addr ) ? 0 : 1 ; case PRE_INC : case PRE_DEC : case POST_INC : case POST_DEC : case PRE_MODIFY : case POST_MODIFY : return ! speed ; case LABEL_REF : case SYMBOL_REF : case CONST : return COSTS_N_INSNS ( 1 ) ; case PLUS : { register rtx plus0 = XEXP ( addr , 0 ) ; register rtx plus1 = XEXP ( addr , 1 ) ; if ( GET_CODE ( plus0 ) != REG && ( GET_CODE ( plus0 ) != MULT || ! CONST_INT_P ( XEXP ( plus0 , 1 ) ) || ( INTVAL ( XEXP ( plus0 , 1 ) ) != 2 && INTVAL ( XEXP ( plus0 , 1 ) ) != 4 ) ) ) break ; switch ( GET_CODE ( plus1 ) ) { case CONST_INT : return ( ! RTX_OK_FOR_OFFSET_P ( SImode , plus1 ) ? COSTS_N_INSNS ( 1 ) : speed ? 0 : ( satisfies_constraint_Rcq ( plus0 ) && satisfies_constraint_O ( plus1 ) ) ? 0 : 1 ) ; case REG : return ( speed < 1 ? 0 : ( satisfies_constraint_Rcq ( plus0 ) && satisfies_constraint_Rcq ( plus1 ) ) ? 0 : 1 ) ; case CONST : case SYMBOL_REF : case LABEL_REF : return COSTS_N_INSNS ( 1 ) ; default : break ; } break ; } default : break ; } return 4 ; } </s>

Provide the costs of an addressing mode that contains ADDR . If ADDR is not a valid address , its cost is irrelevant .


<s> static void gen_one_bundle ( rtx_insn * * slot , int n_filled , int real_first ) { rtx seq ; rtx_insn * bundle ; rtx_insn * t ; int i ; seq = gen_rtx_SEQUENCE ( VOIDmode , gen_rtvec_v ( n_filled , slot ) ) ; bundle = make_insn_raw ( seq ) ; BLOCK_FOR_INSN ( bundle ) = BLOCK_FOR_INSN ( slot [ 0 ] ) ; INSN_LOCATION ( bundle ) = INSN_LOCATION ( slot [ 0 ] ) ; SET_PREV_INSN ( bundle ) = SET_PREV_INSN ( slot [ real_first ] ) ; t = NULL ; for ( i = 0 ; i < n_filled ; i ++ ) { rtx_insn * insn = slot [ i ] ; remove_insn ( insn ) ; SET_PREV_INSN ( insn ) = t ? t : PREV_INSN ( bundle ) ; if ( t != NULL_RTX ) SET_NEXT_INSN ( t ) = insn ; t = insn ; if ( i > 0 ) INSN_LOCATION ( slot [ i ] ) = INSN_LOCATION ( bundle ) ; } SET_NEXT_INSN ( bundle ) = NEXT_INSN ( PREV_INSN ( bundle ) ) ; SET_NEXT_INSN ( t ) = NEXT_INSN ( bundle ) ; SET_NEXT_INSN ( PREV_INSN ( bundle ) ) = bundle ; SET_PREV_INSN ( NEXT_INSN ( bundle ) ) = bundle ; } </s>

Create a SEQUENCE rtx to replace the instructions in SLOT , of which there are N_FILLED . REAL_FIRST identifies the slot if the insn that appears first in the original stream .


<s>
bool
ARMAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNum
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
return
true
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNum
)
;
assert
(
MO
.
isReg
(
)
&&
"unexpected inline asm memory operand"
)
;
O
<<
"["
<<
getRegisterName
(
MO
.
getReg
(
)
)
<<
"]"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .

ARM
ARM
0
"unexpected inline asm memory operand"
"["
"]"


<s> void RISCVDAGToDAGISel :: PostprocessISelDAG ( ) { doPeepholeLoadStoreOffset ( ) ; } </s>

PostprocessISelDAG ( ) - This hook allows the target to hack on the graph right after selection .


"target CPU does not support THUMB instructions"

"target CPU does not support unaligned accesses"

"incompatible options %<-mstack-protector-guard=global%> and "

Reset options between modes that the user has specified .


<s> void LanaiPassConfig :: addPreSched2 ( ) { addPass ( createLanaiMemAluCombinerPass ( ) ) ; addPass ( createLanaiSetflagAluCombinerPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


"Thumb1 does not have ldr to high register"

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s> bool MCS51AsmParser :: ParseDirective ( llvm :: AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal . lower ( ) == ".long" ) { parseLiteralValues ( SIZE_LONG , DirectiveID . getLoc ( ) ) ; } else if ( IDVal . lower ( ) == ".word" || IDVal . lower ( ) == ".short" ) { parseLiteralValues ( SIZE_WORD , DirectiveID . getLoc ( ) ) ; } else if ( IDVal . lower ( ) == ".byte" ) { parseLiteralValues ( 1 , DirectiveID . getLoc ( ) ) ; } return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s>
void
AVRInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
O
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
)
{
unsigned
Opcode
=
MI
->
getOpcode
(
)
;
switch
(
Opcode
)
{
case
AVR
::
LDRdPtr
:
case
AVR
::
LDRdPtrPi
:
case
AVR
::
LDRdPtrPd
:
O
<<
"\tld\t"
;
printOperand
(
MI
,
0
,
O
)
;
O
<<
", "
;
if
(
Opcode
==
AVR
::
LDRdPtrPd
)
O
<<
'-'
;
printOperand
(
MI
,
1
,
O
)
;
if
(
Opcode
==
AVR
::
LDRdPtrPi
)
O
<<
'+'
;
break
;
case
AVR
::
STPtrRr
:
O
<<
"\tst\t"
;
printOperand
(
MI
,
0
,
O
)
;
O
<<
", "
;
printOperand
(
MI
,
1
,
O
)
;
break
;
case
AVR
::
STPtrPiRr
:
case
AVR
::
STPtrPdRr
:
O
<<
"\tst\t"
;
if
(
Opcode
==
AVR
::
STPtrPdRr
)
O
<<
'-'
;
printOperand
(
MI
,
1
,
O
)
;
if
(
Opcode
==
AVR
::
STPtrPiRr
)
O
<<
'+'
;
O
<<
", "
;
printOperand
(
MI
,
2
,
O
)
;
break
;
default
:
if
(
!
printAliasInstr
(
MI
,
O
)
)
printInstruction
(
MI
,
O
)
;
printAnnotation
(
O
,
Annot
)
;
break
;
}
}
</s>

Print the specified MCInst to the specified raw_ostream .

AVR
AVR
AVR::LDRdPtr
AVR::LDRdPtrPi
AVR::LDRdPtrPd
"\tld\t"
0
", "
AVR::LDRdPtrPd
1
AVR::LDRdPtrPi
AVR::STPtrRr
"\tst\t"
0
", "
1
AVR::STPtrPiRr
AVR::STPtrPdRr
"\tst\t"
AVR::STPtrPdRr
1
AVR::STPtrPiRr
", "
2


<s>
void
NVPTXInstPrinter
::
printRegName
(
raw_ostream
&
OS
,
unsigned
RegNo
)
const
{
unsigned
RCId
=
(
RegNo
>>
28
)
;
switch
(
RCId
)
{
default
:
report_fatal_error
(
"Bad virtual register encoding"
)
;
case
0
:
OS
<<
getRegisterName
(
RegNo
)
;
return
;
case
1
:
OS
<<
"%p"
;
break
;
case
2
:
OS
<<
"%rs"
;
break
;
case
3
:
OS
<<
"%r"
;
break
;
case
4
:
OS
<<
"%rd"
;
break
;
case
5
:
OS
<<
"%f"
;
break
;
case
6
:
OS
<<
"%fd"
;
break
;
case
7
:
OS
<<
"%h"
;
break
;
}
unsigned
VReg
=
RegNo
&
0x0FFFFFFF
;
OS
<<
VReg
;
}
</s>


<s>
int
rl78_far_p
(
rtx
x
)
{
if
(
!
MEM_P
(
x
)
)
return
0
;
fprintf
(
stderr
,
"\033[35mrl78_far_p: "
)
;
debug_rtx
(
x
)
;
fprintf
(
stderr
,
" = %d\033[0m\n"
,
MEM_ADDR_SPACE
(
x
)
==
ADDR_SPACE_FAR
)
;
if
(
!
rl78_as_legitimate_address
(
GET_MODE
(
x
)
,
XEXP
(
x
,
0
)
,
false
,
ADDR_SPACE_FAR
)
)
return
0
;
return
GET_MODE_BITSIZE
(
rl78_addr_space_address_mode
(
MEM_ADDR_SPACE
(
x
)
)
)
==
32
;
}
</s>

Used in various constraints and predicates to match operands in the `` far '' address space .


<s>
StringRef
getPassName
(
)
const
override
{
return
"CHERI invalidate pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"HSAIL Always Inline Pass"
;
}
</s>


<s> MCOperand SystemZMCInstLower :: lowerOperand ( const MachineOperand & MO ) const { switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : return MCOperand :: CreateReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: CreateImm ( MO . getImm ( ) ) ; default : { MCSymbolRefExpr :: VariantKind Kind = getVariantKind ( MO . getTargetFlags ( ) ) ; return MCOperand :: CreateExpr ( getExpr ( MO , Kind ) ) ; } } } </s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s>
void
fma_forest
::
dispatch
(
)
{
this
->
m_target_parity
=
this
->
m_roots
->
front
(
)
->
get_parity
(
)
;
int
fpu_balance
=
this
->
m_globals
->
get_fpu_balance
(
)
;
if
(
fpu_balance
!=
0
)
this
->
m_target_parity
=
(
fpu_balance
<
0
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Target parity for forest #%d: %s\n"
,
this
->
m_id
,
this
->
m_target_parity
"odd"
:
"even"
)
;
}
</s>

Dispatch forest to the least utilized pipeline .


<s> static bool loongarch_scalar_mode_supported_p ( scalar_mode mode ) { if ( ALL_FIXED_POINT_MODE_P ( mode ) && GET_MODE_PRECISION ( mode ) <= 2 * BITS_PER_WORD ) return true ; return default_scalar_mode_supported_p ( mode ) ; } </s>


<s> machreg_t inet_ntoa ( machreg_t in ) { return _inet_ntoa ( in << SHIFT_BITS ) ; } </s>

< arpa/inet.h > has char * inet_ntoa ( struct in_addr ) ; on both IRIX 6.2 and 6.5 , with struct in_addr containing a 32-bit int .


<s> unsigned LanaiMCCodeEmitter :: getMachineOpValue ( const MCInst & Inst , const MCOperand & MCOp , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & SubtargetInfo ) const { if ( MCOp . isReg ( ) ) return getLanaiRegisterNumbering ( MCOp . getReg ( ) ) ; if ( MCOp . isImm ( ) ) return static_cast < unsigned > ( MCOp . getImm ( ) ) ; assert ( MCOp . isExpr ( ) ) ; const MCExpr * Expr = MCOp . getExpr ( ) ; if ( Expr -> getKind ( ) == MCExpr :: Binary ) { const MCBinaryExpr * BinaryExpr = static_cast < const MCBinaryExpr * > ( Expr ) ; Expr = BinaryExpr -> getLHS ( ) ; } assert ( isa < LanaiMCExpr > ( Expr ) || Expr -> getKind ( ) == MCExpr :: SymbolRef ) ; Fixups . push_back ( MCFixup :: create ( 0 , MCOp . getExpr ( ) , MCFixupKind ( FixupKind ( Expr ) ) ) ) ; return 0 ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> bool Z80oldTargetLowering :: IsDesirableToPromoteOp ( SDValue Op , EVT & PVT ) const { if ( isDesirableToShrinkOp ( Op . getOpcode ( ) , MVT :: i24 , Op . getValueType ( ) ) ) { return false ; } PVT = MVT :: i24 ; return true ; return false ; } </s>

Return true if the target has native support for the specified value type and it is 'desirable ' to use the type .


<s> static unsigned int mips_global_pointer ( void ) { unsigned int regno ; if ( ! TARGET_USE_GOT ) return GLOBAL_POINTER_REGNUM ; if ( mips_cfun_has_inflexible_gp_ref_p ( ) ) return GLOBAL_POINTER_REGNUM ; if ( TARGET_ABSOLUTE_JUMPS && ! mips_cfun_has_flexible_gp_ref_p ( ) ) return INVALID_REGNUM ; if ( TARGET_CALL_SAVED_GP && crtl -> is_leaf ) for ( regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( ! df_regs_ever_live_p ( regno ) && call_used_regs [ regno ] && ! fixed_regs [ regno ] && regno != PIC_FUNCTION_ADDR_REGNUM ) return regno ; return GLOBAL_POINTER_REGNUM ; } </s>

Return the register that should be used as the global pointer within this function . Return 0 if the function does n't need a global pointer .


<s> static void emit_unlikely_jump ( rtx insn ) { rtx_insn * jump = emit_jump_insn ( insn ) ; add_reg_br_prob_note ( jump , profile_probability :: very_unlikely ( ) ) ; } </s>

Mark the previous jump instruction as unlikely .


<s> static bool predicate_insn ( rtx_insn * insn , rtx cond , bool doit ) { int icode ; if ( cond == NULL_RTX ) { gcc_assert ( ! doit ) ; return false ; } if ( get_attr_predicable ( insn ) == PREDICABLE_YES && GET_CODE ( PATTERN ( insn ) ) != COND_EXEC ) { if ( doit ) { rtx newpat = gen_rtx_COND_EXEC ( VOIDmode , cond , PATTERN ( insn ) ) ; PATTERN ( insn ) = newpat ; INSN_CODE ( insn ) = - 1 ; } return true ; } if ( GET_CODE ( PATTERN ( insn ) ) == COND_EXEC && rtx_equal_p ( COND_EXEC_TEST ( PATTERN ( insn ) ) , cond ) ) return true ; icode = INSN_CODE ( insn ) ; if ( icode == CODE_FOR_real_jump || icode == CODE_FOR_jump || icode == CODE_FOR_indirect_jump ) { rtx pat = PATTERN ( insn ) ; rtx dest = ( icode == CODE_FOR_real_jump ? XVECEXP ( pat , 0 , 0 ) : icode == CODE_FOR_jump ? XEXP ( SET_SRC ( pat ) , 0 ) : SET_SRC ( pat ) ) ; if ( doit ) { rtx newpat ; if ( REG_P ( dest ) ) newpat = gen_rtx_COND_EXEC ( VOIDmode , cond , PATTERN ( insn ) ) ; else newpat = gen_br_true ( cond , XEXP ( cond , 0 ) , dest ) ; PATTERN ( insn ) = newpat ; INSN_CODE ( insn ) = - 1 ; } return true ; } if ( INSN_CODE ( insn ) == CODE_FOR_br_true ) { rtx br_cond = XEXP ( SET_SRC ( PATTERN ( insn ) ) , 0 ) ; return rtx_equal_p ( br_cond , cond ) ; } if ( INSN_CODE ( insn ) == CODE_FOR_br_false ) { rtx br_cond = XEXP ( SET_SRC ( PATTERN ( insn ) ) , 0 ) ; return conditions_opposite_p ( br_cond , cond ) ; } return false ; } </s>

Return true if we can add a predicate COND to INSN , or if INSN already has that predicate . If DOIT is true , also perform the modification .


<s> static void nvptx_generate_vector_shuffle ( location_t loc , tree dest_var , tree var , unsigned shift , gimple_seq * seq ) { unsigned fn = NVPTX_BUILTIN_SHUFFLE ; tree_code code = NOP_EXPR ; tree arg_type = unsigned_type_node ; tree var_type = TREE_TYPE ( var ) ; tree dest_type = var_type ; if ( TREE_CODE ( var_type ) == COMPLEX_TYPE ) var_type = TREE_TYPE ( var_type ) ; if ( TREE_CODE ( var_type ) == REAL_TYPE ) code = VIEW_CONVERT_EXPR ; if ( TYPE_SIZE ( var_type ) == TYPE_SIZE ( long_long_unsigned_type_node ) ) { fn = NVPTX_BUILTIN_SHUFFLELL ; arg_type = long_long_unsigned_type_node ; } tree call = nvptx_builtin_decl ( fn , true ) ; tree bits = build_int_cst ( unsigned_type_node , shift ) ; tree kind = build_int_cst ( unsigned_type_node , SHUFFLE_DOWN ) ; tree expr ; if ( var_type != dest_type ) { tree real = fold_build1 ( REALPART_EXPR , var_type , var ) ; real = fold_build1 ( code , arg_type , real ) ; real = build_call_expr_loc ( loc , call , 3 , real , bits , kind ) ; real = fold_build1 ( code , var_type , real ) ; tree imag = fold_build1 ( IMAGPART_EXPR , var_type , var ) ; imag = fold_build1 ( code , arg_type , imag ) ; imag = build_call_expr_loc ( loc , call , 3 , imag , bits , kind ) ; imag = fold_build1 ( code , var_type , imag ) ; expr = fold_build2 ( COMPLEX_EXPR , dest_type , real , imag ) ; } else { expr = fold_build1 ( code , arg_type , var ) ; expr = build_call_expr_loc ( loc , call , 3 , expr , bits , kind ) ; expr = fold_build1 ( code , dest_type , expr ) ; } gimplify_assign ( dest_var , expr , seq ) ; } </s>

Emit a SHFL.DOWN using index SHFL of VAR into DEST_VAR . This function will cast the variable if necessary .


<s> virtual bool isVirtualSection ( ) const { return false ; } </s>

Check whether this section is `` virtual '' , that is has no actual object file contents .


<s>
SDValue
PPCTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCRetInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCRetInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_PPC
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Val
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
,
InFlag
)
;
Chain
=
Val
.
getValue
(
1
)
;
InFlag
=
Val
.
getValue
(
2
)
;
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
AExt
:
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
ZExt
:
Val
=
DAG
.
getNode
(
ISD
::
AssertZext
,
dl
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
SExt
:
Val
=
DAG
.
getNode
(
ISD
::
AssertSext
,
dl
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
}
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .

PowerPC
PPC
ISD::InputArg
16
PPC
0
"Can only return in registers!"
1
2
"Unknown loc info!"
ISD::TRUNCATE
ISD::AssertZext
ISD::TRUNCATE
ISD::AssertSext
ISD::TRUNCATE


<s> const SISubtarget * SITargetLowering :: getSubtarget ( ) const { return Subtarget ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


<s> bool NVPTXAssignValidGlobalNames :: runOnModule ( Module & M ) { for ( GlobalVariable & GV : M . globals ( ) ) { if ( GV . hasLocalLinkage ( ) ) { GV . setName ( cleanUpName ( GV . getName ( ) ) ) ; } } return true ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> const TargetRegisterClass * DCPU16RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & DCPU16 :: GR16RegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> static rtx gen_rx_store_vector ( unsigned int low , unsigned int high ) { unsigned int i ; unsigned int count = ( high - low ) + 2 ; rtx vector ; vector = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; XVECEXP ( vector , 0 , 0 ) = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , gen_rtx_MINUS ( SImode , stack_pointer_rtx , GEN_INT ( ( count - 1 ) * UNITS_PER_WORD ) ) ) ; for ( i = 0 ; i < count - 1 ; i ++ ) XVECEXP ( vector , 0 , i + 1 ) = gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( SImode , gen_rtx_MINUS ( SImode , stack_pointer_rtx , GEN_INT ( ( i + 1 ) * UNITS_PER_WORD ) ) ) , gen_rtx_REG ( SImode , high - i ) ) ; return vector ; } </s>

Generate a PARALLEL that will pass the rx_store_multiple_vector predicate .


<s> void X86MCCodeEmitter :: emitPrefix ( const MCInst & MI , raw_ostream & OS , const MCSubtargetInfo & STI ) const { unsigned Opcode = MI . getOpcode ( ) ; const MCInstrDesc & Desc = MCII . get ( Opcode ) ; uint64_t TSFlags = Desc . TSFlags ; if ( X86II :: isPseudo ( TSFlags ) ) return ; unsigned CurOp = X86II :: getOperandBias ( Desc ) ; emitPrefixImpl ( CurOp , MI , STI , OS ) ; } </s>

Append the prefixes of given instruction to the code buffer .


<s>
void
ARMAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
IsPCRel
,
nullptr
,
IsLittleEndian
)
;
if
(
!
Value
)
return
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
unsigned
FullSizeBytes
;
if
(
!
IsLittleEndian
)
{
FullSizeBytes
=
getFixupKindContainerSizeBytes
(
Fixup
.
getKind
(
)
)
;
assert
(
(
Offset
+
FullSizeBytes
)
<=
DataSize
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FullSizeBytes
&&
"Invalid fixup size!"
)
;
}
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
IsLittleEndian
i
:
(
FullSizeBytes
1
i
)
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
void
AVRInstPrinter
::
printInst
(
const
MCInst
*
MI
,
uint64_t
Address
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
,
raw_ostream
&
O
)
{
unsigned
Opcode
=
MI
->
getOpcode
(
)
;
switch
(
Opcode
)
{
case
AVR
::
LDRdPtr
:
case
AVR
::
LDRdPtrPi
:
case
AVR
::
LDRdPtrPd
:
O
<<
"\tld\t"
;
printOperand
(
MI
,
0
,
O
)
;
O
<<
", "
;
if
(
Opcode
==
AVR
::
LDRdPtrPd
)
O
<<
'-'
;
printOperand
(
MI
,
1
,
O
)
;
if
(
Opcode
==
AVR
::
LDRdPtrPi
)
O
<<
'+'
;
break
;
case
AVR
::
STPtrRr
:
O
<<
"\tst\t"
;
printOperand
(
MI
,
0
,
O
)
;
O
<<
", "
;
printOperand
(
MI
,
1
,
O
)
;
break
;
case
AVR
::
STPtrPiRr
:
case
AVR
::
STPtrPdRr
:
O
<<
"\tst\t"
;
if
(
Opcode
==
AVR
::
STPtrPdRr
)
O
<<
'-'
;
printOperand
(
MI
,
1
,
O
)
;
if
(
Opcode
==
AVR
::
STPtrPiRr
)
O
<<
'+'
;
O
<<
", "
;
printOperand
(
MI
,
2
,
O
)
;
break
;
default
:
if
(
!
printAliasInstr
(
MI
,
Address
,
O
)
)
printInstruction
(
MI
,
Address
,
O
)
;
printAnnotation
(
O
,
Annot
)
;
break
;
}
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s> static tree sparc_gimplify_va_arg ( tree valist , tree type , gimple_seq * pre_p , gimple_seq * post_p ) { HOST_WIDE_INT size , rsize , align ; tree addr , incr ; bool indirect ; tree ptrtype = build_pointer_type ( type ) ; if ( pass_by_reference ( NULL , TYPE_MODE ( type ) , type , false ) ) { indirect = true ; size = rsize = UNITS_PER_WORD ; align = 0 ; } else { indirect = false ; size = int_size_in_bytes ( type ) ; rsize = ROUND_UP ( size , UNITS_PER_WORD ) ; align = 0 ; if ( TARGET_ARCH64 ) { if ( TYPE_ALIGN ( type ) >= 2 * ( unsigned ) BITS_PER_WORD ) align = 2 * UNITS_PER_WORD ; if ( AGGREGATE_TYPE_P ( type ) ) { if ( size == 0 ) size = rsize = UNITS_PER_WORD ; else size = rsize ; } } } incr = valist ; if ( align ) { incr = fold_build_pointer_plus_hwi ( incr , align - 1 ) ; incr = fold_convert ( sizetype , incr ) ; incr = fold_build2 ( BIT_AND_EXPR , sizetype , incr , size_int ( - align ) ) ; incr = fold_convert ( ptr_type_node , incr ) ; } gimplify_expr ( & incr , pre_p , post_p , is_gimple_val , fb_rvalue ) ; addr = incr ; if ( BYTES_BIG_ENDIAN && size < rsize ) addr = fold_build_pointer_plus_hwi ( incr , rsize - size ) ; if ( indirect ) { addr = fold_convert ( build_pointer_type ( ptrtype ) , addr ) ; addr = build_va_arg_indirect_ref ( addr ) ; } else if ( align == 0 && TYPE_ALIGN ( type ) > BITS_PER_WORD ) { tree tmp = create_tmp_var ( type , "va_arg_tmp" ) ; tree dest_addr = build_fold_addr_expr ( tmp ) ; tree copy = build_call_expr ( builtin_decl_implicit ( BUILT_IN_MEMCPY ) , 3 , dest_addr , addr , size_int ( rsize ) ) ; TREE_ADDRESSABLE ( tmp ) = 1 ; gimplify_and_add ( copy , pre_p ) ; addr = dest_addr ; } else addr = fold_convert ( ptrtype , addr ) ; incr = fold_build_pointer_plus_hwi ( incr , rsize ) ; gimplify_assign ( valist , incr , post_p ) ; return build_va_arg_indirect_ref ( addr ) ; } </s>


<s> static SDValue matchBinOpReduction ( SDNode * Extract , unsigned & BinOp , ArrayRef < ISD :: NodeType > CandidateBinOps ) { if ( ( Extract -> getOpcode ( ) != ISD :: EXTRACT_VECTOR_ELT ) || ! isNullConstant ( Extract -> getOperand ( 1 ) ) ) return SDValue ( ) ; SDValue Op = Extract -> getOperand ( 0 ) ; unsigned Stages = Log2_32 ( Op . getValueType ( ) . getVectorNumElements ( ) ) ; if ( llvm :: none_of ( CandidateBinOps , [ Op ] ( ISD :: NodeType BinOp ) { return Op . getOpcode ( ) == BinOp ; } ) ) return SDValue ( ) ; unsigned CandidateBinOp = Op . getOpcode ( ) ; for ( unsigned i = 0 ; i < Stages ; ++ i ) { if ( Op . getOpcode ( ) != CandidateBinOp ) return SDValue ( ) ; ShuffleVectorSDNode * Shuffle = dyn_cast < ShuffleVectorSDNode > ( Op . getOperand ( 0 ) . getNode ( ) ) ; if ( Shuffle ) { Op = Op . getOperand ( 1 ) ; } else { Shuffle = dyn_cast < ShuffleVectorSDNode > ( Op . getOperand ( 1 ) . getNode ( ) ) ; Op = Op . getOperand ( 0 ) ; } if ( ! Shuffle || Shuffle -> getOperand ( 0 ) != Op ) return SDValue ( ) ; for ( int Index = 0 , MaskEnd = 1 << i ; Index < MaskEnd ; ++ Index ) if ( Shuffle -> getMaskElt ( Index ) != MaskEnd + Index ) return SDValue ( ) ; } BinOp = CandidateBinOp ; return Op ; } </s>

Match a binop + shuffle pyramid that represents a horizontal reduction over the elements of a vector starting from the EXTRACT_VECTOR_ELT node /p Extract .


<s> void split_addsi ( rtx * operands ) { int val = INTVAL ( operands [ 2 ] ) ; if ( val > 127 && val <= 255 && arc_check_short_reg_p ( operands [ 0 ] ) ) { operands [ 3 ] = operands [ 2 ] ; operands [ 4 ] = gen_rtx_PLUS ( SImode , operands [ 0 ] , operands [ 1 ] ) ; } else { operands [ 3 ] = operands [ 1 ] ; operands [ 4 ] = gen_rtx_PLUS ( SImode , operands [ 0 ] , operands [ 2 ] ) ; } } </s>

Operands 0 .. 2 are the operands of a addsi which uses a 12 bit constant in operand 2 , but which would require a LIMM because of operand mismatch . operands 3 and 4 are new SET_SRCs for operands 0 .


<s> bool enableShrinkWrapping ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target will correctly handle shrink wrapping .


<s> static void nds32_emit_stack_v3pop ( unsigned Rb , unsigned Re , unsigned imm8u ) { unsigned regno ; int num_use_regs ; int par_index ; int offset ; rtx reg ; rtx mem ; rtx pop_rtx ; rtx adjust_sp_rtx ; rtx parallel_insn ; rtx dwarf = NULL_RTX ; num_use_regs = Re - Rb + 1 + 3 ; parallel_insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_use_regs + 1 ) ) ; par_index = 0 ; offset = 0 ; for ( regno = Rb ; regno <= Re ; regno ++ ) { reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; pop_rtx = gen_rtx_SET ( reg , mem ) ; XVECEXP ( parallel_insn , 0 , par_index ) = pop_rtx ; RTX_FRAME_RELATED_P ( pop_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; } reg = gen_rtx_REG ( SImode , FP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; pop_rtx = gen_rtx_SET ( reg , mem ) ; XVECEXP ( parallel_insn , 0 , par_index ) = pop_rtx ; RTX_FRAME_RELATED_P ( pop_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; reg = gen_rtx_REG ( SImode , GP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; pop_rtx = gen_rtx_SET ( reg , mem ) ; XVECEXP ( parallel_insn , 0 , par_index ) = pop_rtx ; RTX_FRAME_RELATED_P ( pop_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; reg = gen_rtx_REG ( SImode , LP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; pop_rtx = gen_rtx_SET ( reg , mem ) ; XVECEXP ( parallel_insn , 0 , par_index ) = pop_rtx ; RTX_FRAME_RELATED_P ( pop_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; adjust_sp_rtx = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , offset + imm8u ) ) ; XVECEXP ( parallel_insn , 0 , par_index ) = adjust_sp_rtx ; if ( frame_pointer_needed ) { rtx cfa_adjust_rtx = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , const0_rtx ) ; dwarf = alloc_reg_note ( REG_CFA_DEF_CFA , cfa_adjust_rtx , dwarf ) ; } else { dwarf = alloc_reg_note ( REG_CFA_ADJUST_CFA , copy_rtx ( adjust_sp_rtx ) , dwarf ) ; } parallel_insn = emit_insn ( parallel_insn ) ; RTX_FRAME_RELATED_P ( parallel_insn ) = 1 ; REG_NOTES ( parallel_insn ) = dwarf ; } </s>

Function to create a parallel rtx pattern which presents stack v3pop behavior . The overall concept are : `` pop registers from memory '' , `` adjust stack pointer '' .


<s> unsigned AArch64RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const AArch64FrameLowering * TFI = getFrameLowering ( MF ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case AArch64 :: GPR32RegClassID : case AArch64 :: GPR32spRegClassID : case AArch64 :: GPR32allRegClassID : case AArch64 :: GPR64spRegClassID : case AArch64 :: GPR64allRegClassID : case AArch64 :: GPR64RegClassID : case AArch64 :: GPR32commonRegClassID : case AArch64 :: GPR64commonRegClassID : return 32 - 1 - ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) - MF . getSubtarget < AArch64Subtarget > ( ) . getNumXRegisterReserved ( ) - hasBasePointer ( MF ) ; case AArch64 :: FPR8RegClassID : case AArch64 :: FPR16RegClassID : case AArch64 :: FPR32RegClassID : case AArch64 :: FPR64RegClassID : case AArch64 :: FPR128RegClassID : return 32 ; case AArch64 :: DDRegClassID : case AArch64 :: DDDRegClassID : case AArch64 :: DDDDRegClassID : case AArch64 :: QQRegClassID : case AArch64 :: QQQRegClassID : case AArch64 :: QQQQRegClassID : return 32 ; case AArch64 :: FPR128_loRegClassID : case AArch64 :: FPR64_loRegClassID : return 16 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> static int nvptx_dim_limit ( int axis ) { switch ( axis ) { case GOMP_DIM_VECTOR : return PTX_MAX_VECTOR_LENGTH ; default : break ; } return 0 ; } </s>

Return maximum dimension size , or zero for unbounded .


<s> static void emit_insr ( rtx target , rtx elem ) { machine_mode mode = GET_MODE ( target ) ; scalar_mode elem_mode = GET_MODE_INNER ( mode ) ; elem = force_reg ( elem_mode , elem ) ; insn_code icode = optab_handler ( vec_shl_insert_optab , mode ) ; gcc_assert ( icode != CODE_FOR_nothing ) ; emit_insn ( GEN_FCN ( icode ) ( target , target , elem ) ) ; } </s>

Emit RTL corresponding to : insr TARGET , ELEM .


<s> bool loongarch_split_move_insn_p ( rtx dest , rtx src ) { return loongarch_split_move_p ( dest , src ) ; } </s>

Return true if a move from SRC to DEST in INSN should be split .


<s> void PPCFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const PPCRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; PPCFunctionInfo * FI = MF . getInfo < PPCFunctionInfo > ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; SavedRegs . reset ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; const bool isPPC64 = Subtarget . isPPC64 ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( ) ; FPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int BPSI = FI -> getBasePointerSaveIndex ( ) ; if ( ! BPSI && RegInfo -> hasBasePointer ( MF ) ) { int BPOffset = getBasePointerSaveOffset ( ) ; BPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , BPOffset , true ) ; FI -> setBasePointerSaveIndex ( BPSI ) ; } if ( FI -> usesPICBase ( ) ) { int PBPSI = MFI . CreateFixedObject ( 4 , - 8 , true ) ; FI -> setPICBasePointerSaveIndex ( PBPSI ) ; } if ( needsFP ( MF ) ) SavedRegs . reset ( isPPC64 ? PPC :: X31 : PPC :: R31 ) ; if ( RegInfo -> hasBasePointer ( MF ) ) SavedRegs . reset ( RegInfo -> getBaseRegister ( MF ) ) ; if ( FI -> usesPICBase ( ) ) SavedRegs . reset ( PPC :: R30 ) ; int TCSPDelta = 0 ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < 0 ) { MFI . CreateFixedObject ( - 1 * TCSPDelta , TCSPDelta , true ) ; } if ( Subtarget . is32BitELFABI ( ) && ( SavedRegs . test ( PPC :: CR2 ) || SavedRegs . test ( PPC :: CR3 ) || SavedRegs . test ( PPC :: CR4 ) ) ) { int FrameIdx = MFI . CreateFixedObject ( ( uint64_t ) 4 , ( int64_t ) - 4 , true ) ; FI -> setCRSpillFrameIndex ( FrameIdx ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> static bool expand_vec_perm_v4hi_5 ( struct expand_vec_perm_d * d ) { unsigned char perm2 [ 4 ] ; rtx rmask [ 4 ] ; unsigned i ; rtx t0 , t1 , mask , x ; bool ok ; if ( d -> vmode != V4HImode || d -> one_operand_p ) return false ; if ( d -> testing_p ) return true ; for ( i = 0 ; i < 4 ; ++ i ) { perm2 [ i ] = d -> perm [ i ] & 3 ; rmask [ i ] = ( d -> perm [ i ] & 4 ? const0_rtx : constm1_rtx ) ; } mask = gen_rtx_CONST_VECTOR ( V4HImode , gen_rtvec_v ( 4 , rmask ) ) ; mask = force_reg ( V4HImode , mask ) ; t0 = gen_reg_rtx ( V4HImode ) ; t1 = gen_reg_rtx ( V4HImode ) ; ok = expand_vselect ( t0 , d -> op0 , perm2 , 4 ) ; gcc_assert ( ok ) ; ok = expand_vselect ( t1 , d -> op1 , perm2 , 4 ) ; gcc_assert ( ok ) ; x = gen_rtx_AND ( V4HImode , mask , t0 ) ; emit_insn ( gen_rtx_SET ( t0 , x ) ) ; x = gen_rtx_NOT ( V4HImode , mask ) ; x = gen_rtx_AND ( V4HImode , x , t1 ) ; emit_insn ( gen_rtx_SET ( t1 , x ) ) ; x = gen_rtx_IOR ( V4HImode , t0 , t1 ) ; emit_insn ( gen_rtx_SET ( d -> target , x ) ) ; return true ; } </s>

A subroutine of ia64_expand_vec_perm_const_1 . Emit a full V4HImode constant permutation via two mux2 and a merge .


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) { switch ( Op . getOpcode ( ) ) { case ISD :: AND : return LowerANDOR ( Op , DAG ) ; case ISD :: BRCOND : return LowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return LowerConstantPool ( Op , DAG ) ; case ISD :: DYNAMIC_STACKALLOC : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case ISD :: FP_TO_SINT : return LowerFP_TO_SINT ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return LowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( Op , DAG ) ; case ISD :: OR : return LowerANDOR ( Op , DAG ) ; case ISD :: SELECT : return LowerSELECT ( Op , DAG ) ; case ISD :: SETCC : return LowerSETCC ( Op , DAG ) ; case ISD :: VASTART : return LowerVASTART ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::AND ISD::BRCOND ISD::ConstantPool ISD::DYNAMIC_STACKALLOC ISD::FP_TO_SINT ISD::GlobalAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::OR ISD::SELECT ISD::SETCC ISD::VASTART


<s> static bool arc_check_short_reg_p ( rtx op ) { if ( ! REG_P ( op ) ) return false ; if ( IN_RANGE ( REGNO ( op ) ^ 4 , 4 , 11 ) ) return true ; return false ; } </s>

Return TRUE if reg is ok for short instrcutions .


<s> void Thumb1RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( ! TFI -> hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; DebugLoc dl = Old -> getDebugLoc ( ) ; unsigned Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { unsigned Align = TFI -> getStackAlignment ( ) ; Amount = ( Amount + Align - 1 ) / Align * Align ; unsigned Opc = Old -> getOpcode ( ) ; if ( Opc == ARM :: ADJCALLSTACKDOWN || Opc == ARM :: tADJCALLSTACKDOWN ) { emitSPUpdate ( MBB , I , TII , dl , * this , - Amount ) ; } else { assert ( Opc == ARM :: ADJCALLSTACKUP || Opc == ARM :: tADJCALLSTACKUP ) ; emitSPUpdate ( MBB , I , TII , dl , * this , Amount ) ; } } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool X86TargetLowering :: isCheapToSpeculateCttz ( ) const { return Subtarget . hasBMI ( ) ; } </s>

Return true if it is cheap to speculate a call to intrinsic cttz .


<s> TargetLowering :: ConstraintWeight MipsTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'd' : case 'y' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; case 'c' : case 'l' : case 'x' : if ( type -> isIntegerTy ( ) ) weight = CW_SpecificReg ; break ; case 'I' : case 'J' : case 'K' : case 'L' : case 'N' : case 'O' : case 'P' : if ( isa < ConstantInt > ( CallOperandVal ) ) weight = CW_Constant ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> int m32c_legitimate_constant_p ( rtx x ATTRIBUTE_UNUSED ) { return 1 ; } </s>

Implements LEGITIMATE_CONSTANT_P . We split large constants anyway , so we can allow anything .


"SGPR spill should have been removed in SILowerSGPRSpills"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> bool LM32TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { return VT != MVT :: f32 ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s>
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
FISCTargetLowering
::
getRegForInlineAsmConstraint
(
const
TargetRegisterInfo
*
TRI
,
StringRef
Constraint
,
MVT
VT
)
const
{
if
(
Constraint
.
size
(
)
==
1
)
{
switch
(
Constraint
[
0
]
)
{
case
'r'
:
if
(
VT
==
MVT
::
i8
||
VT
==
MVT
::
i16
||
VT
==
MVT
::
i32
||
VT
==
MVT
::
i64
)
return
std
::
make_pair
(
0U
,
&
FISC
::
GRRegsRegClass
)
;
return
std
::
make_pair
(
0u
,
static_cast
<
const
TargetRegisterClass
*
>
(
0
)
)
;
case
'c'
:
if
(
VT
==
MVT
::
i64
)
return
std
::
make_pair
(
(
unsigned
)
FISC
::
X19
,
&
FISC
::
GRRegsRegClass
)
;
assert
(
"Unexpected type."
)
;
}
}
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
R
;
R
=
parseRegForInlineAsmConstraint
(
Constraint
,
VT
)
;
if
(
R
.
second
)
return
R
;
return
TargetLowering
::
getRegForInlineAsmConstraint
(
TRI
,
Constraint
,
VT
)
;
}
</s>

Given a physical register constraint ( e.g .


<s> const uint32_t * PatmosRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { llvm_unreachable ( "Unimplemented" ) ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
SUnit
*
ConvergingVLIWScheduler
::
pickNode
(
bool
&
IsTopNode
)
{
if
(
DAG
->
top
(
)
==
DAG
->
bottom
(
)
)
{
assert
(
Top
.
Available
.
empty
(
)
&&
Top
.
Pending
.
empty
(
)
&&
Bot
.
Available
.
empty
(
)
&&
Bot
.
Pending
.
empty
(
)
&&
"ReadyQ garbage"
)
;
return
nullptr
;
}
SUnit
*
SU
;
if
(
ForceTopDown
)
{
SU
=
Top
.
pickOnlyChoice
(
)
;
if
(
!
SU
)
{
SchedCandidate
TopCand
;
CandResult
TopResult
=
pickNodeFromQueue
(
Top
,
DAG
->
getTopRPTracker
(
)
,
TopCand
)
;
assert
(
TopResult
!=
NoCand
&&
"failed to find the first candidate"
)
;
(
void
)
TopResult
;
SU
=
TopCand
.
SU
;
}
IsTopNode
=
true
;
}
else
if
(
ForceBottomUp
)
{
SU
=
Bot
.
pickOnlyChoice
(
)
;
if
(
!
SU
)
{
SchedCandidate
BotCand
;
CandResult
BotResult
=
pickNodeFromQueue
(
Bot
,
DAG
->
getBotRPTracker
(
)
,
BotCand
)
;
assert
(
BotResult
!=
NoCand
&&
"failed to find the first candidate"
)
;
(
void
)
BotResult
;
SU
=
BotCand
.
SU
;
}
IsTopNode
=
false
;
}
else
{
SU
=
pickNodeBidrectional
(
IsTopNode
)
;
}
if
(
SU
->
isTopReady
(
)
)
Top
.
removeReady
(
SU
)
;
if
(
SU
->
isBottomReady
(
)
)
Bot
.
removeReady
(
SU
)
;
DEBUG
(
dbgs
(
)
<<
"*** "
<<
(
IsTopNode
"Top"
:
"Bottom"
)
<<
" Scheduling instruction in cycle "
<<
(
IsTopNode
Top
.
CurrCycle
:
Bot
.
CurrCycle
)
<<
" ("
<<
reportPackets
(
)
<<
")\n"
;
SU
->
dump
(
DAG
)
)
;
return
SU
;
}
</s>

Pick the next node to schedule , or return NULL .

Hexagon
"ReadyQ garbage"
"failed to find the first candidate"
"failed to find the first candidate"
"*** "
"Top"
"Bottom"
" Scheduling instruction in cycle "
" ("
")\n"


<s> BitVector DCPU16RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; Reserved . set ( DCPU16 :: EX ) ; Reserved . set ( DCPU16 :: SP ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( DCPU16 :: J ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
unsigned
AArch64MCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
{
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
}
else
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
llvm_unreachable
(
"Unable to encode MCOperand!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> SDValue F2003fTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_F2003f ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> void X86LoadValueInjectionLoadHardeningPass :: getAnalysisUsage ( AnalysisUsage & AU ) const { MachineFunctionPass :: getAnalysisUsage ( AU ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < MachineDominanceFrontier > ( ) ; AU . setPreservesCFG ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
static
tree
ix86_build_builtin_va_list
(
void
)
{
if
(
TARGET_64BIT
)
{
sysv_va_list_type_node
=
ix86_build_builtin_va_list_64
(
)
;
tree
char_ptr_type
=
build_pointer_type
(
char_type_node
)
;
tree
attr
=
tree_cons
(
get_identifier
(
"ms_abi va_list"
)
,
NULL_TREE
,
TYPE_ATTRIBUTES
(
char_ptr_type
)
)
;
ms_va_list_type_node
=
build_type_attribute_variant
(
char_ptr_type
,
attr
)
;
return
(
(
ix86_abi
==
MS_ABI
)
ms_va_list_type_node
:
sysv_va_list_type_node
)
;
}
else
{
return
build_pointer_type
(
char_type_node
)
;
}
}
</s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"MVE lane interleaving"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> int rl78_force_nonfar_3 ( rtx * operands , rtx ( * gen ) ( rtx , rtx , rtx ) ) { int did = 0 ; rtx temp_reg = NULL ; if ( rtx_equal_p ( operands [ 0 ] , operands [ 1 ] ) && ! MEM_P ( operands [ 2 ] ) ) return 0 ; if ( rl78_far_p ( operands [ 1 ] ) ) { rtx temp_reg = gen_reg_rtx ( GET_MODE ( operands [ 1 ] ) ) ; emit_move_insn ( temp_reg , operands [ 1 ] ) ; operands [ 1 ] = temp_reg ; did = 1 ; } if ( rl78_far_p ( operands [ 0 ] ) ) { temp_reg = operands [ 0 ] ; operands [ 0 ] = gen_reg_rtx ( GET_MODE ( operands [ 0 ] ) ) ; did = 1 ; } if ( ! did ) return 0 ; emit_insn ( gen ( operands [ 0 ] , operands [ 1 ] , operands [ 2 ] ) ) ; if ( temp_reg ) emit_move_insn ( temp_reg , operands [ 0 ] ) ; return 1 ; } </s>

Likewise , but for three-operand expanders .


<s> bool isToken ( ) const override { return Kind == k_Token ; } </s>


<s> bool HexagonInstrInfo :: hasLoadFromStackSlot ( const MachineInstr & MI , const MachineMemOperand * & MMO , int & FrameIndex ) const { if ( MI . isBundle ( ) ) { const MachineBasicBlock * MBB = MI . getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI . getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( TargetInstrInfo :: hasLoadFromStackSlot ( * MII , MMO , FrameIndex ) ) return true ; return false ; } return TargetInstrInfo :: hasLoadFromStackSlot ( MI , MMO , FrameIndex ) ; } </s>

If the specified machine instruction has a load from a stack slot , return true along with the FrameIndices of the loaded stack slot and the machine mem operands containing the reference .


<s> int SIInstrInfo :: pseudoToMCOpcode ( int Opcode ) const { SIEncodingFamily Gen = subtargetEncodingFamily ( ST ) ; if ( ( get ( Opcode ) . TSFlags & SIInstrFlags :: renamedInGFX9 ) != 0 && ST . getGeneration ( ) == AMDGPUSubtarget :: GFX9 ) Gen = SIEncodingFamily :: GFX9 ; if ( ST . hasUnpackedD16VMem ( ) && ( get ( Opcode ) . TSFlags & SIInstrFlags :: D16Buf ) ) Gen = SIEncodingFamily :: GFX80 ; if ( get ( Opcode ) . TSFlags & SIInstrFlags :: SDWA ) { switch ( ST . getGeneration ( ) ) { default : Gen = SIEncodingFamily :: SDWA ; break ; case AMDGPUSubtarget :: GFX9 : Gen = SIEncodingFamily :: SDWA9 ; break ; case AMDGPUSubtarget :: GFX10 : Gen = SIEncodingFamily :: SDWA10 ; break ; } } int MCOp = AMDGPU :: getMCOpcode ( Opcode , Gen ) ; if ( MCOp == - 1 ) return Opcode ; if ( ST . hasGFX90AInsts ( ) ) { uint16_t NMCOp = ( uint16_t ) - 1 ; NMCOp = AMDGPU :: getMCOpcode ( Opcode , SIEncodingFamily :: GFX90A ) ; if ( NMCOp == ( uint16_t ) - 1 ) NMCOp = AMDGPU :: getMCOpcode ( Opcode , SIEncodingFamily :: GFX9 ) ; if ( NMCOp != ( uint16_t ) - 1 ) MCOp = NMCOp ; } if ( MCOp == ( uint16_t ) - 1 ) return - 1 ; if ( isAsmOnlyOpcode ( MCOp ) ) return - 1 ; return MCOp ; } </s>

Return a target-specific opcode if Opcode is a pseudo instruction .


<s> static bool bfin_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) { return arg . type && TREE_CODE ( TYPE_SIZE ( arg . type ) ) != INTEGER_CST ; } </s>

Variable sized types are passed by reference .


<s>
bool
WebAssemblyFrameLowering
::
hasFP
(
const
MachineFunction
&
MF
)
const
{
llvm_unreachable
(
"TODO: implement hasFP"
)
;
}
</s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .

WebAssembly
WebAssembly
"TODO: implement hasFP"


"Instr doesn't have FrameIndex operand!"

"Requesting 64-bit offset in 32-bit immediate!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s>
bool
ThumbDisassembler
::
getInstruction
(
MCInst
&
MI
,
uint64_t
&
Size
,
const
MemoryObject
&
Region
,
uint64_t
Address
,
raw_ostream
&
os
)
const
{
unsigned
insn
=
0
;
uint16_t
insn1
=
0
;
uint8_t
bytes
[
2
]
;
if
(
Region
.
readBytes
(
Address
,
2
,
(
uint8_t
*
)
bytes
,
)
==
1
)
return
false
;
insn
=
(
bytes
[
1
]
<<
8
)
|
bytes
[
0
]
;
unsigned
bits15_11
=
slice
(
insn
,
15
,
11
)
;
bool
IsThumb2
=
false
;
if
(
bits15_11
==
0x1D
||
bits15_11
==
0x1E
||
bits15_11
==
0x1F
)
{
IsThumb2
=
true
;
if
(
Region
.
readBytes
(
Address
+
2
,
2
,
(
uint8_t
*
)
bytes
,
)
==
1
)
return
false
;
insn1
=
(
bytes
[
1
]
<<
8
)
|
bytes
[
0
]
;
insn
=
(
insn
<<
16
|
insn1
)
;
}
unsigned
Opcode
=
decodeThumbSideEffect
(
IsThumb2
,
insn
)
;
if
(
Thumb2PreloadOpcodeNoPCI
(
Opcode
)
&&
slice
(
insn
,
19
,
16
)
==
15
)
Opcode
=
T2Morph2Preload2PCI
(
Opcode
)
;
ARMFormat
Format
=
ARMFormats
[
Opcode
]
;
Size
=
IsThumb2
4
:
2
;
DEBUG
(
{
errs
(
)
<<
"Opcode="
<<
Opcode
<<
" Name="
<<
ARMUtils
::
OpcodeName
(
Opcode
)
<<
" Format="
<<
stringForARMFormat
(
Format
)
<<
'('
<<
(
int
)
Format
<<
")\n"
;
showBitVector
(
errs
(
)
,
insn
)
;
}
)
;
ARMBasicMCBuilder
*
Builder
=
CreateMCBuilder
(
Opcode
,
Format
)
;
if
(
!
Builder
)
return
false
;
Builder
->
SetSession
(
const_cast
<
Session
*
>
(
&
SO
)
)
;
if
(
!
Builder
->
Build
(
MI
,
insn
)
)
return
false
;
delete
Builder
;
return
true
;
}
</s>

Returns the disassembly of a single instruction .


"AIX's linkage directives take a visibility setting."

"CommonLinkage of XCOFF should not come to this path"

This emits linkage information about GVSym based on GV , if this is supported by the target .


<s> unsigned X86AsmBackend :: getMaximumNopSize ( const MCSubtargetInfo & STI ) const { if ( STI . hasFeature ( X86 :: Mode16Bit ) ) return 4 ; if ( ! STI . hasFeature ( X86 :: FeatureNOPL ) && ! STI . hasFeature ( X86 :: Mode64Bit ) ) return 1 ; if ( STI . getFeatureBits ( ) [ X86 :: TuningFast7ByteNOP ] ) return 7 ; if ( STI . getFeatureBits ( ) [ X86 :: TuningFast15ByteNOP ] ) return 15 ; if ( STI . getFeatureBits ( ) [ X86 :: TuningFast11ByteNOP ] ) return 11 ; return 10 ; } </s>

Returns the maximum size of a nop in bytes on this target .


<s> void LEGInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static int loongarch_arg_partial_bytes ( cumulative_args_t cum , const function_arg_info & generic_arg ) { struct loongarch_arg_info arg ; loongarch_get_arg_info ( & arg , get_cumulative_args ( cum ) , generic_arg . mode , generic_arg . type , generic_arg . named , false ) ; return arg . stack_p ? arg . num_gprs * UNITS_PER_WORD : 0 ; } </s>


<s> bool RISCVAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & OS ) { RISCVInstPrinter :: printAddress ( MI -> getOperand ( OpNo ) . getReg ( ) , MI -> getOperand ( OpNo + 1 ) . getImm ( ) , OS ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


"instruction use requires an option to be enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> TargetTransformInfo AArch64TargetMachine :: getTargetTransformInfo ( const Function & F ) { return TargetTransformInfo ( AArch64TTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> static rtx move_to_hl ( int opno , rtx before ) { rtx src = OP ( opno ) ; machine_mode mode = GET_MODE ( src ) ; rtx reg ; if ( mode == VOIDmode ) mode = recog_data . operand_mode [ opno ] ; reg = ( mode == QImode ) ? L : HL ; if ( mode == QImode || ! is_virtual_register ( OP ( opno ) ) ) { OP ( opno ) = move_to_acc ( opno , before ) ; OP ( opno ) = move_acc_to_reg ( OP ( opno ) , L_REG , before ) ; return reg ; } return gen_and_emit_move ( reg , src , before , true ) ; } </s>

Copy OP ( opno ) to H or HL , placing any generated insns before BEFORE . Returns H/HL RTX .


<s> void NVPTXPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; addPass ( createGenericToNVVMPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static enum reg_class rs6000_secondary_reload_class ( enum reg_class rclass , machine_mode mode , rtx in ) { int regno ; if ( TARGET_ELF || ( DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT ) ) { if ( rclass != BASE_REGS && ( SYMBOL_REF_P ( in ) || GET_CODE ( in ) == HIGH || GET_CODE ( in ) == LABEL_REF || GET_CODE ( in ) == CONST ) ) return BASE_REGS ; } if ( REG_P ( in ) ) { regno = REGNO ( in ) ; if ( ! HARD_REGISTER_NUM_P ( regno ) ) { regno = true_regnum ( in ) ; if ( ! HARD_REGISTER_NUM_P ( regno ) ) regno = - 1 ; } } else if ( SUBREG_P ( in ) ) { regno = true_regnum ( in ) ; if ( ! HARD_REGISTER_NUM_P ( regno ) ) regno = - 1 ; } else regno = - 1 ; if ( TARGET_VSX && GET_MODE_SIZE ( mode ) < 16 && ! mode_supports_vmx_dform ( mode ) && ( ( ( rclass == GENERAL_REGS || rclass == BASE_REGS ) && ( regno >= 0 && ALTIVEC_REGNO_P ( regno ) ) ) || ( ( rclass == VSX_REGS || rclass == ALTIVEC_REGS ) && ( regno >= 0 && INT_REGNO_P ( regno ) ) ) ) ) return FLOAT_REGS ; if ( rclass == GENERAL_REGS || rclass == BASE_REGS || ( regno >= 0 && INT_REGNO_P ( regno ) ) ) return NO_REGS ; if ( rclass == VSX_REGS && ( regno == - 1 || VSX_REGNO_P ( regno ) ) ) return NO_REGS ; if ( ( regno == - 1 || FP_REGNO_P ( regno ) ) && ( rclass == FLOAT_REGS || rclass == GEN_OR_FLOAT_REGS ) ) return ( mode != SDmode || lra_in_progress ) ? NO_REGS : GENERAL_REGS ; if ( ( regno == - 1 || ALTIVEC_REGNO_P ( regno ) ) && rclass == ALTIVEC_REGS ) return NO_REGS ; if ( ( rclass == CR_REGS || rclass == CR0_REGS ) && regno >= 0 && CR_REGNO_P ( regno ) ) return NO_REGS ; return GENERAL_REGS ; } </s>

Return the register class of a scratch register needed to copy IN into or out of a register in RCLASS in MODE . If it can be done directly , NO_REGS is returned .


<s> bool FixAllFDIVSQRT :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < SparcSubtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget -> getInstrInfo ( ) ; DebugLoc DL = DebugLoc ( ) ; bool Modified = false ; for ( auto MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; for ( auto MBBI = MBB . begin ( ) , E = MBB . end ( ) ; MBBI != E ; ++ MBBI ) { MachineInstr & MI = * MBBI ; unsigned Opcode = MI . getOpcode ( ) ; if ( MI . isInlineAsm ( ) ) { std :: string AsmString ( MI . getOperand ( InlineAsm :: MIOp_AsmString ) . getSymbolName ( ) ) ; std :: string FSQRTDOpCode ( "fsqrtd" ) ; std :: string FDIVDOpCode ( "fdivd" ) ; std :: transform ( AsmString . begin ( ) , AsmString . end ( ) , AsmString . begin ( ) , :: tolower ) ; if ( AsmString . find ( FSQRTDOpCode ) == 0 ) { Opcode = SP :: FSQRTD ; } else if ( AsmString . find ( FDIVDOpCode ) == 0 ) { Opcode = SP :: FDIVD ; } } if ( Opcode == SP :: FSQRTD || Opcode == SP :: FDIVD ) { for ( int InsertedCount = 0 ; InsertedCount < 5 ; InsertedCount ++ ) BuildMI ( MBB , MBBI , DL , TII . get ( SP :: NOP ) ) ; MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; for ( int InsertedCount = 0 ; InsertedCount < 28 ; InsertedCount ++ ) BuildMI ( MBB , NMBBI , DL , TII . get ( SP :: NOP ) ) ; Modified = true ; } } } return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool UPTFrameLowering :: hasFP ( const MachineFunction & MF ) const { return false ; } </s>


<s> static SDValue getTargetNode ( ExternalSymbolSDNode * N , SDLoc DL , EVT Ty , SelectionDAG & DAG , unsigned Flags ) { return DAG . getTargetExternalSymbol ( N -> getSymbol ( ) , Ty , Flags ) ; } </s>

Retrieve the target node this edge connects to .


<s>
SDValue
PTXTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
if
(
isVarArg
)
llvm_unreachable
(
"PTX does not support varargs"
)
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention."
)
;
case
CallingConv
::
PTX_Kernel
:
assert
(
Outs
.
size
(
)
==
0
&&
"Kernel must return void."
)
;
return
DAG
.
getNode
(
PTXISD
::
EXIT
,
dl
,
MVT
::
Other
,
Chain
)
;
case
CallingConv
::
PTX_Device
:
assert
(
Outs
.
size
(
)
<=
1
&&
"Can at most return one value."
)
;
break
;
}
if
(
Outs
.
size
(
)
==
0
)
return
DAG
.
getNode
(
PTXISD
::
RET
,
dl
,
MVT
::
Other
,
Chain
)
;
SDValue
Flag
;
unsigned
reg
;
if
(
Outs
[
0
]
.
VT
==
MVT
::
i16
)
{
reg
=
PTX
::
RH0
;
}
else
if
(
Outs
[
0
]
.
VT
==
MVT
::
i32
)
{
reg
=
PTX
::
R0
;
}
else
if
(
Outs
[
0
]
.
VT
==
MVT
::
i64
)
{
reg
=
PTX
::
RD0
;
}
else
if
(
Outs
[
0
]
.
VT
==
MVT
::
f32
)
{
reg
=
PTX
::
F0
;
}
else
if
(
Outs
[
0
]
.
VT
==
MVT
::
f64
)
{
reg
=
PTX
::
FD0
;
}
else
{
assert
(
false
&&
"Can return only basic types"
)
;
}
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
PTXMachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
PTXMachineFunctionInfo
>
(
)
;
MFI
->
setRetReg
(
reg
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
reg
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
reg
,
OutVals
[
0
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
return
DAG
.
getNode
(
PTXISD
::
RET
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> auto HexagonVectorCombine :: getSizeOf ( const Type * Ty ) const -> int { return DL . getTypeStoreSize ( const_cast < Type * > ( Ty ) ) . getFixedValue ( ) ; } </s>

getSizeOf constant expr - computes the ( alloc ) size of a type ( in address-units , not bits ) in a target independent way ( Note : the return type is an i64 ) .


<s> enum reg_class coproc_secondary_reload_class ( machine_mode mode , rtx x , bool wb ) { if ( mode == HFmode ) { if ( ! TARGET_NEON_FP16 ) return GENERAL_REGS ; if ( s_register_operand ( x , mode ) || neon_vector_mem_operand ( x , 2 , true ) ) return NO_REGS ; return GENERAL_REGS ; } if ( TARGET_NEON && ( MEM_P ( x ) || GET_CODE ( x ) == CONST_VECTOR ) && ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT || VALID_NEON_STRUCT_MODE ( mode ) ) ) return NO_REGS ; if ( arm_coproc_mem_operand ( x , wb ) || s_register_operand ( x , mode ) ) return NO_REGS ; return GENERAL_REGS ; } </s>

Return GENERAL_REGS if a scratch register required to reload x to/from coprocessor registers . Otherwise return NO_REGS .


"Do not know how to custom type legalize this operation!"

"Unexpected result type for CTR decrement intrinsic"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s>
unsigned
ARMBaseInstrInfo
::
getNumMicroOps
(
const
InstrItineraryData
*
ItinData
,
const
MachineInstr
*
MI
)
const
{
if
(
!
ItinData
||
ItinData
->
isEmpty
(
)
)
return
1
;
const
MCInstrDesc
&
Desc
=
MI
->
getDesc
(
)
;
unsigned
Class
=
Desc
.
getSchedClass
(
)
;
unsigned
UOps
=
ItinData
->
Itineraries
[
Class
]
.
NumMicroOps
;
if
(
UOps
)
return
UOps
;
unsigned
Opc
=
MI
->
getOpcode
(
)
;
switch
(
Opc
)
{
default
:
llvm_unreachable
(
"Unexpected multi-uops instruction!"
)
;
case
ARM
::
VLDMQIA
:
case
ARM
::
VSTMQIA
:
return
2
;
case
ARM
::
VLDMDIA
:
case
ARM
::
VLDMDIA_UPD
:
case
ARM
::
VLDMDDB_UPD
:
case
ARM
::
VLDMSIA
:
case
ARM
::
VLDMSIA_UPD
:
case
ARM
::
VLDMSDB_UPD
:
case
ARM
::
VSTMDIA
:
case
ARM
::
VSTMDIA_UPD
:
case
ARM
::
VSTMDDB_UPD
:
case
ARM
::
VSTMSIA
:
case
ARM
::
VSTMSIA_UPD
:
case
ARM
::
VSTMSDB_UPD
:
{
unsigned
NumRegs
=
MI
->
getNumOperands
(
)
Desc
.
getNumOperands
(
)
;
return
(
NumRegs
/
2
)
+
(
NumRegs
%
2
)
+
1
;
}
case
ARM
::
LDMIA_RET
:
case
ARM
::
LDMIA
:
case
ARM
::
LDMDA
:
case
ARM
::
LDMDB
:
case
ARM
::
LDMIB
:
case
ARM
::
LDMIA_UPD
:
case
ARM
::
LDMDA_UPD
:
case
ARM
::
LDMDB_UPD
:
case
ARM
::
LDMIB_UPD
:
case
ARM
::
STMIA
:
case
ARM
::
STMDA
:
case
ARM
::
STMDB
:
case
ARM
::
STMIB
:
case
ARM
::
STMIA_UPD
:
case
ARM
::
STMDA_UPD
:
case
ARM
::
STMDB_UPD
:
case
ARM
::
STMIB_UPD
:
case
ARM
::
tLDMIA
:
case
ARM
::
tLDMIA_UPD
:
case
ARM
::
tSTMIA_UPD
:
case
ARM
::
tPOP_RET
:
case
ARM
::
tPOP
:
case
ARM
::
tPUSH
:
case
ARM
::
t2LDMIA_RET
:
case
ARM
::
t2LDMIA
:
case
ARM
::
t2LDMDB
:
case
ARM
::
t2LDMIA_UPD
:
case
ARM
::
t2LDMDB_UPD
:
case
ARM
::
t2STMIA
:
case
ARM
::
t2STMDB
:
case
ARM
::
t2STMIA_UPD
:
case
ARM
::
t2STMDB_UPD
:
{
unsigned
NumRegs
=
MI
->
getNumOperands
(
)
Desc
.
getNumOperands
(
)
+
1
;
if
(
Subtarget
.
isCortexA8
(
)
)
{
if
(
NumRegs
<
4
)
return
2
;
UOps
=
(
NumRegs
/
2
)
;
if
(
NumRegs
%
2
)
++
UOps
;
return
UOps
;
}
else
if
(
Subtarget
.
isCortexA9
(
)
)
{
UOps
=
(
NumRegs
/
2
)
;
if
(
(
NumRegs
%
2
)
||
!
MI
->
hasOneMemOperand
(
)
||
(
*
MI
->
memoperands_begin
(
)
)
->
getAlignment
(
)
<
8
)
++
UOps
;
return
UOps
;
}
else
{
return
NumRegs
;
}
}
}
}
</s>

Return the number of issue slots required for this MI .


"expression value must be representable in 32 bits"

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { const OR1KTargetMachine * TM = static_cast < const OR1KTargetMachine * > ( & MF . getTarget ( ) ) ; if ( TM -> getRelocationModel ( ) != Reloc :: PIC_ ) return false ; OR1KMachineFunctionInfo * OR1KFI = MF . getInfo < OR1KMachineFunctionInfo > ( ) ; unsigned GlobalBaseReg = OR1KFI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg == 0 ) return false ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; const OR1KInstrInfo * TII = TM -> getInstrInfo ( ) ; unsigned Scratch1 = RegInfo . createVirtualRegister ( & OR1K :: GPRRegClass ) ; unsigned Scratch2 = RegInfo . createVirtualRegister ( & OR1K :: GPRRegClass ) ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( OR1K :: GETPC ) ) . addImm ( 0 ) ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( OR1K :: MOVHI ) , Scratch1 ) . addExternalSymbol ( "_GLOBAL_OFFSET_TABLE_" , OR1KII :: MO_GOTPCHI ) ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( OR1K :: ORI ) , Scratch2 ) . addReg ( Scratch1 ) . addExternalSymbol ( "_GLOBAL_OFFSET_TABLE_" , OR1KII :: MO_GOTPCLO ) ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( OR1K :: ADD ) , GlobalBaseReg ) . addReg ( OR1K :: R9 ) . addReg ( Scratch2 ) ; return true ; } </s>


<s> bool ARM64PassConfig :: addInstSelector ( ) { addPass ( createARM64ISelDag ( getARM64TargetMachine ( ) , getOptLevel ( ) ) ) ; if ( TM -> getSubtarget < ARM64Subtarget > ( ) . isTargetELF ( ) && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createARM64CleanupLocalDynamicTLSPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static bool loongarch_return_in_memory ( const_tree type , const_tree fndecl ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS args ; cumulative_args_t cum = pack_cumulative_args ( & args ) ; memset ( & args , 0 , sizeof ( args ) ) ; function_arg_info arg ( const_cast < tree > ( type ) , true ) ; return loongarch_pass_by_reference ( cum , arg ) ; } </s>


<s> static reg_class_t c6x_preferred_rename_class ( reg_class_t cl ) { if ( cl == A_REGS ) return NONPREDICATE_A_REGS ; if ( cl == B_REGS ) return NONPREDICATE_B_REGS ; if ( cl == ALL_REGS || cl == GENERAL_REGS ) return NONPREDICATE_REGS ; return NO_REGS ; } </s>


<s> bool SPUTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , const Type * ) const { if ( AM . BaseGV && ! AM . HasBaseReg && AM . Scale == 0 && AM . BaseOffs == 0 ) return true ; if ( AM . BaseGV == 0 && AM . HasBaseReg && AM . Scale == 0 && isInt < 14 > ( AM . BaseOffs ) ) return true ; if ( AM . BaseGV == 0 && AM . HasBaseReg && AM . Scale == 1 && AM . BaseOffs == 0 ) return true ; return false ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> SDValue Z80oldTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , getRetCCAssignFn ( CallConv ) ) ; for ( unsigned I = 0 , E = RVLocs . size ( ) ; I != E ; ++ I ) { Chain = DAG . getCopyFromReg ( Chain , DL , RVLocs [ I ] . getLocReg ( ) , RVLocs [ I ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static bool aarch64_reads_global_state_p ( unsigned int f , machine_mode mode ) { unsigned int flags = aarch64_call_properties ( f , mode ) ; if ( flags & FLAG_READ_FPCR ) return true ; return flags & FLAG_READ_MEMORY ; } </s>

Return true if calls to the function could read some form of global state .


<s> MachineBasicBlock :: iterator X86InstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , const outliner :: TargetCostInfo & TCI ) const { if ( TCI . CallConstructionID == MachineOutlinerTailCall ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( X86 :: JMP_1 ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; } else { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( X86 :: CALL64pcrel32 ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; } return It ; } </s>

Insert a call to an outlined function into the program .


<s> bool TPCRegisterInfo :: isConstantPhysReg ( unsigned PhysReg ) const { return PhysReg == TPC :: SP0 || PhysReg == TPC :: VP0 || PhysReg == TPC :: V_LANE_ID_32 || PhysReg == TPC :: V_LANE_ID_16 || PhysReg == TPC :: V_LANE_ID_8 ; } </s>

Returns true if PhysReg is unallocatable and constant throughout the function .


<s> bool mergeStoresAfterLegalization ( ) const override { return true ; } </s>

Do not merge vector stores after legalization because that may conflict with x86-specific store splitting optimizations .


<s> const uint32_t * AArch64RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return CSR_AArch64_NoRegs_RegMask ; if ( CC == CallingConv :: AnyReg ) return CSR_AArch64_AllRegs_RegMask ; else return CSR_AArch64_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> int ARMBaseRegisterInfo :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { return ResolveFrameIndexReference ( MF , FI , FrameReg , 0 ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> int neon_vector_mem_operand ( rtx op , int type , bool strict ) { rtx ind ; if ( strict && ! ( reload_in_progress || reload_completed ) && ( reg_mentioned_p ( frame_pointer_rtx , op ) || reg_mentioned_p ( arg_pointer_rtx , op ) || reg_mentioned_p ( virtual_incoming_args_rtx , op ) || reg_mentioned_p ( virtual_outgoing_args_rtx , op ) || reg_mentioned_p ( virtual_stack_dynamic_rtx , op ) || reg_mentioned_p ( virtual_stack_vars_rtx , op ) ) ) return FALSE ; if ( ! MEM_P ( op ) ) return FALSE ; ind = XEXP ( op , 0 ) ; if ( reload_completed && ( GET_CODE ( ind ) == LABEL_REF || ( GET_CODE ( ind ) == CONST && GET_CODE ( XEXP ( ind , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( ind , 0 ) , 0 ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( ind , 0 ) , 1 ) ) ) ) ) return TRUE ; if ( REG_P ( ind ) ) return arm_address_register_rtx_p ( ind , 0 ) ; if ( ( type != 1 && GET_CODE ( ind ) == POST_INC ) || ( type == 0 && GET_CODE ( ind ) == PRE_DEC ) ) return arm_address_register_rtx_p ( XEXP ( ind , 0 ) , 0 ) ; if ( type == 2 && GET_CODE ( ind ) == POST_MODIFY && GET_CODE ( XEXP ( ind , 1 ) ) == PLUS && REG_P ( XEXP ( XEXP ( ind , 1 ) , 1 ) ) ) return true ; if ( type == 0 && GET_CODE ( ind ) == PLUS && REG_P ( XEXP ( ind , 0 ) ) && REG_MODE_OK_FOR_BASE_P ( XEXP ( ind , 0 ) , VOIDmode ) && CONST_INT_P ( XEXP ( ind , 1 ) ) && INTVAL ( XEXP ( ind , 1 ) ) > - 1024 && ( INTVAL ( XEXP ( ind , 1 ) ) < ( VALID_NEON_QREG_MODE ( GET_MODE ( op ) ) ? 1016 : 1024 ) ) && ( INTVAL ( XEXP ( ind , 1 ) ) & 3 ) == 0 ) return TRUE ; return FALSE ; } </s>

Return TRUE if OP is a memory operand which we can load or store a vector to/from . TYPE is one of the following values : 0 - Vector load/stor ( vldr ) 1 - Core registers ( ldm ) 2 - Element/structure loads ( vld1 )


<s> unsigned postOffset ( unsigned LogAlign = 0 ) const { unsigned PO = Offset + Size ; unsigned LA = std :: max ( unsigned ( PostAlign ) , LogAlign ) ; if ( ! LA ) return PO ; return PO + UnknownPadding ( LA , internalKnownBits ( ) ) ; } </s>

Compute the offset immediately following this block .


<s>
unsigned
AArch64FastISel
::
fastMaterializeConstant
(
const
Constant
*
C
)
{
EVT
CEVT
=
TLI
.
getValueType
(
DL
,
C
->
getType
(
)
,
true
)
;
if
(
!
CEVT
.
isSimple
(
)
)
return
0
;
MVT
VT
=
CEVT
.
getSimpleVT
(
)
;
if
(
const
auto
*
CPN
=
dyn_cast
<
ConstantPointerNull
>
(
C
)
)
{
(
void
)
CPN
;
assert
(
CPN
->
getType
(
)
->
getPointerAddressSpace
(
)
==
0
&&
"Unexpected address space"
)
;
assert
(
VT
==
MVT
::
i64
&&
"Expected 64-bit pointers"
)
;
return
materializeInt
(
ConstantInt
::
get
(
Type
::
getInt64Ty
(
*
Context
)
,
0
)
,
VT
)
;
}
if
(
const
auto
*
CI
=
dyn_cast
<
ConstantInt
>
(
C
)
)
return
materializeInt
(
CI
,
VT
)
;
else
if
(
const
ConstantFP
*
CFP
=
dyn_cast
<
ConstantFP
>
(
C
)
)
return
materializeFP
(
CFP
,
VT
)
;
else
if
(
const
GlobalValue
*
GV
=
dyn_cast
<
GlobalValue
>
(
C
)
)
return
materializeGV
(
GV
)
;
return
0
;
}
</s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s> static enum attr_type s390_safe_attr_type ( rtx insn ) { if ( recog_memoized ( insn ) >= 0 ) return get_attr_type ( insn ) ; else return TYPE_NONE ; } </s>


<s>
bool
HexagonPacketizer
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MF
.
getProperties
(
)
.
set
(
MachineFunctionProperties
::
Property
::
FailsVerification
)
;
auto
&
HST
=
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
;
HII
=
HST
.
getInstrInfo
(
)
;
HRI
=
HST
.
getRegisterInfo
(
)
;
auto
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
auto
*
AA
=
&
getAnalysis
<
AAResultsWrapperPass
>
(
)
.
getAAResults
(
)
;
auto
*
MBPI
=
&
getAnalysis
<
MachineBranchProbabilityInfo
>
(
)
;
if
(
EnableGenAllInsnClass
)
HII
->
genAllInsnTimingClasses
(
MF
)
;
bool
MinOnly
=
Minimal
||
DisablePacketizer
||
!
HST
.
usePackets
(
)
||
skipFunction
(
MF
.
getFunction
(
)
)
;
HexagonPacketizerList
Packetizer
(
MF
,
MLI
,
AA
,
MBPI
,
MinOnly
)
;
assert
(
Packetizer
.
getResourceTracker
(
)
&&
"Empty DFA table!"
)
;
for
(
MachineBasicBlock
&
MB
:
MF
)
{
auto
End
=
MB
.
end
(
)
;
auto
MI
=
MB
.
begin
(
)
;
while
(
MI
!=
End
)
{
auto
NextI
=
std
::
next
(
MI
)
;
if
(
MI
->
isKill
(
)
)
{
MB
.
erase
(
MI
)
;
End
=
MB
.
end
(
)
;
}
MI
=
NextI
;
}
}
if
(
HST
.
isTinyCoreWithDuplex
(
)
)
HII
->
translateInstrsForDup
(
MF
,
true
)
;
for
(
auto
&
MB
:
MF
)
{
auto
Begin
=
MB
.
begin
(
)
,
End
=
MB
.
end
(
)
;
while
(
Begin
!=
End
)
{
MachineBasicBlock
::
iterator
RB
=
Begin
;
while
(
RB
!=
End
&&
HII
->
isSchedulingBoundary
(
*
RB
,
&
MB
,
MF
)
)
++
RB
;
MachineBasicBlock
::
iterator
RE
=
RB
;
while
(
RE
!=
End
&&
!
HII
->
isSchedulingBoundary
(
*
RE
,
&
MB
,
MF
)
)
++
RE
;
if
(
RE
!=
End
)
++
RE
;
if
(
RB
!=
End
)
Packetizer
.
PacketizeMIs
(
&
MB
,
RB
,
RE
)
;
Begin
=
RE
;
}
}
if
(
HST
.
isTinyCoreWithDuplex
(
)
)
HII
->
translateInstrsForDup
(
MF
,
false
)
;
Packetizer
.
unpacketizeSoloInstrs
(
MF
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .

Hexagon
Hexagon
Hexagon
Hexagon
"Empty DFA table!"


<s> void print_operand_address ( FILE * file , rtx x ) { if ( REG_P ( x ) ) fprintf ( file , "0(%s)" , reg_names [ REGNO ( x ) ] ) ; else if ( SYMBOL_REF_P ( x ) || GET_CODE ( x ) == CONST || GET_CODE ( x ) == LABEL_REF ) { output_addr_const ( file , x ) ; if ( small_data_operand ( x , GET_MODE ( x ) ) ) fprintf ( file , "@%s(%s)" , SMALL_DATA_RELOC , reg_names [ SMALL_DATA_REG ] ) ; else gcc_assert ( ! TARGET_TOC ) ; } else if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , 0 ) ) && REG_P ( XEXP ( x , 1 ) ) ) { if ( REGNO ( XEXP ( x , 0 ) ) == 0 ) fprintf ( file , "%s,%s" , reg_names [ REGNO ( XEXP ( x , 1 ) ) ] , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; else fprintf ( file , "%s,%s" , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] , reg_names [ REGNO ( XEXP ( x , 1 ) ) ] ) ; } else if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , 0 ) ) && CONST_INT_P ( XEXP ( x , 1 ) ) ) fprintf ( file , HOST_WIDE_INT_PRINT_DEC "(%s)" , INTVAL ( XEXP ( x , 1 ) ) , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; else if ( GET_CODE ( x ) == LO_SUM && REG_P ( XEXP ( x , 0 ) ) && CONSTANT_P ( XEXP ( x , 1 ) ) ) { fprintf ( file , "lo16(" ) ; output_addr_const ( file , XEXP ( x , 1 ) ) ; fprintf ( file , ")(%s)" , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; } else if ( GET_CODE ( x ) == LO_SUM && REG_P ( XEXP ( x , 0 ) ) && CONSTANT_P ( XEXP ( x , 1 ) ) ) { output_addr_const ( file , XEXP ( x , 1 ) ) ; fprintf ( file , "@l(%s)" , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; } else if ( toc_relative_expr_p ( x , false , & tocrel_base_oac , & tocrel_offset_oac ) ) { output_addr_const ( file , CONST_CAST_RTX ( tocrel_base_oac ) ) ; if ( GET_CODE ( x ) == LO_SUM ) fprintf ( file , "@l(%s)" , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; else fprintf ( file , "(%s)" , reg_names [ REGNO ( XVECEXP ( tocrel_base_oac , 0 , 1 ) ) ] ) ; } else output_addr_const ( file , x ) ; } </s>

Print the operand address represented by the rtx addr


<s> void aarch64_expand_mov_immediate ( rtx dest , rtx imm ) { machine_mode mode = GET_MODE ( dest ) ; gcc_assert ( mode == SImode || mode == DImode ) ; if ( GET_CODE ( imm ) == SYMBOL_REF || GET_CODE ( imm ) == LABEL_REF || GET_CODE ( imm ) == CONST ) { rtx mem , base , offset ; enum aarch64_symbol_type sty ; split_const ( imm , & base , & offset ) ; sty = aarch64_classify_symbol ( base , offset ) ; switch ( sty ) { case SYMBOL_FORCE_TO_MEM : if ( offset != const0_rtx && targetm . cannot_force_const_mem ( mode , imm ) ) { gcc_assert ( can_create_pseudo_p ( ) ) ; base = aarch64_force_temporary ( mode , dest , base ) ; base = aarch64_add_offset ( mode , NULL , base , INTVAL ( offset ) ) ; aarch64_emit_move ( dest , base ) ; return ; } mem = force_const_mem ( ptr_mode , imm ) ; gcc_assert ( mem ) ; if ( ! aarch64_pcrelative_literal_loads ) { gcc_assert ( can_create_pseudo_p ( ) ) ; base = gen_reg_rtx ( ptr_mode ) ; aarch64_expand_mov_immediate ( base , XEXP ( mem , 0 ) ) ; mem = gen_rtx_MEM ( ptr_mode , base ) ; } if ( mode != ptr_mode ) mem = gen_rtx_ZERO_EXTEND ( mode , mem ) ; emit_insn ( gen_rtx_SET ( dest , mem ) ) ; return ; case SYMBOL_SMALL_TLSGD : case SYMBOL_SMALL_TLSDESC : case SYMBOL_SMALL_TLSIE : case SYMBOL_SMALL_GOT_28K : case SYMBOL_SMALL_GOT_4G : case SYMBOL_TINY_GOT : case SYMBOL_TINY_TLSIE : if ( offset != const0_rtx ) { gcc_assert ( can_create_pseudo_p ( ) ) ; base = aarch64_force_temporary ( mode , dest , base ) ; base = aarch64_add_offset ( mode , NULL , base , INTVAL ( offset ) ) ; aarch64_emit_move ( dest , base ) ; return ; } case SYMBOL_SMALL_ABSOLUTE : case SYMBOL_TINY_ABSOLUTE : case SYMBOL_TLSLE12 : case SYMBOL_TLSLE24 : case SYMBOL_TLSLE32 : case SYMBOL_TLSLE48 : aarch64_load_symref_appropriately ( dest , imm , sty ) ; return ; default : gcc_unreachable ( ) ; } } if ( ! CONST_INT_P ( imm ) ) { if ( GET_CODE ( imm ) == HIGH ) emit_insn ( gen_rtx_SET ( dest , imm ) ) ; else { rtx mem = force_const_mem ( mode , imm ) ; gcc_assert ( mem ) ; emit_insn ( gen_rtx_SET ( dest , mem ) ) ; } return ; } aarch64_internal_mov_immediate ( dest , imm , true , GET_MODE ( dest ) ) ; } </s>

Set DEST to immediate IMM . For SVE vector modes , GEN_VEC_DUPLICATE is a pattern that can be used to set DEST to a replicated scalar element .