<s> void SparcRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; int64_t Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) + Subtarget . getStackPointerBias ( ) ; SparcMachineFunctionInfo * FuncInfo = MF . getInfo < SparcMachineFunctionInfo > ( ) ; unsigned FramePtr = SP :: I6 ; if ( FuncInfo -> isLeafProc ( ) ) { FramePtr = SP :: O6 ; int stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ; Offset += ( stackSize ) ? Subtarget . getAdjustedFrameSize ( stackSize ) : 0 ; } if ( Offset >= - 4096 && Offset <= 4095 ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FramePtr , false ) ; MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ; } else { const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; unsigned OffHi = ( unsigned ) Offset >> 10U ; BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( SP :: SETHIi ) , SP :: G1 ) . addImm ( OffHi ) ; BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( SP :: ADDrr ) , SP :: G1 ) . addReg ( SP :: G1 ) . addReg ( FramePtr ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( SP :: G1 , false ) ; MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset & ( ( 1 << 10 ) - 1 ) ) ; } } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> void ARMElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { const ARMBaseTargetMachine & ARM_TM = static_cast < const ARMBaseTargetMachine & > ( TM ) ; bool isAAPCS_ABI = ARM_TM . TargetABI == ARMBaseTargetMachine :: ARMABI :: ARM_ABI_AAPCS ; TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( isAAPCS_ABI ) ; if ( isAAPCS_ABI ) { LSDASection = nullptr ; } AttributesSection = getContext ( ) . getELFSection ( ".ARM.attributes" , ELF :: SHT_ARM_ATTRIBUTES , 0 ) ; } </s>

This method must be called before any actual lowering is done .

ARM ARM ARM ARM ARM ARM ARM ARMABI::ARM_ABI_AAPCS ".ARM.attributes" ARM 0


"eliminateCallFramePseudoInstr size too big: "

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool HexagonTargetLowering :: isShuffleMaskLegal ( ArrayRef < int > Mask , EVT VT ) const { if ( Subtarget . useHVXOps ( ) ) return isStridedLoad ( Mask ) != StridedLoadKind :: NoPattern ; return true ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> SDValue X86TargetLowering :: getPICJumpTableRelocBase ( SDValue Table , SelectionDAG & DAG ) const { if ( usesGlobalOffsetTable ( ) ) return DAG . getGLOBAL_OFFSET_TABLE ( getPointerTy ( ) ) ; if ( ! Subtarget -> isPICStyleRIPRel ( ) ) return DAG . getNode ( X86ISD :: GlobalBaseReg , DebugLoc :: getUnknownLoc ( ) , getPointerTy ( ) ) ; return Table ; } </s>

Returns relocation base for the given PIC jumptable .


"missing value in %<target()%> pragma or attribute"

"invalid value (\"%s\") in %<target()%> pragma or attribute"

Parse an architecture extensions target attribute string specified in STR . For example `` +fp+nosimd '' . Show any errors if needed . Return TRUE if successful . Update aarch64_isa_flags to reflect the ISA features modified . PRAGMA_OR_ATTR is used in potential error messages .


<s> bool AArch64InstrInfo :: isPreSt ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { default : return false ; case AArch64 :: STRWpre : case AArch64 :: STRXpre : case AArch64 :: STRSpre : case AArch64 :: STRDpre : case AArch64 :: STRQpre : return true ; } } </s>

Returns whether the instruction is a pre-indexed store .


<s> void LEGPassConfig :: addPreEmitPass ( ) { } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void ix86_expand_copysign ( rtx operands [ ] ) { machine_mode mode , vmode ; rtx dest , op0 , op1 , mask , nmask ; dest = operands [ 0 ] ; op0 = operands [ 1 ] ; op1 = operands [ 2 ] ; mode = GET_MODE ( dest ) ; if ( mode == SFmode ) vmode = V4SFmode ; else if ( mode == DFmode ) vmode = V2DFmode ; else vmode = mode ; if ( GET_CODE ( op0 ) == CONST_DOUBLE ) { rtx ( * copysign_insn ) ( rtx , rtx , rtx , rtx ) ; if ( real_isneg ( CONST_DOUBLE_REAL_VALUE ( op0 ) ) ) op0 = simplify_unary_operation ( ABS , mode , op0 , mode ) ; if ( mode == SFmode || mode == DFmode ) { if ( op0 == CONST0_RTX ( mode ) ) op0 = CONST0_RTX ( vmode ) ; else { rtx v = ix86_build_const_vector ( vmode , false , op0 ) ; op0 = force_reg ( vmode , v ) ; } } else if ( op0 != CONST0_RTX ( mode ) ) op0 = force_reg ( mode , op0 ) ; mask = ix86_build_signbit_mask ( vmode , 0 , 0 ) ; if ( mode == SFmode ) copysign_insn = gen_copysignsf3_const ; else if ( mode == DFmode ) copysign_insn = gen_copysigndf3_const ; else copysign_insn = gen_copysigntf3_const ; emit_insn ( copysign_insn ( dest , op0 , op1 , mask ) ) ; } else { rtx ( * copysign_insn ) ( rtx , rtx , rtx , rtx , rtx , rtx ) ; nmask = ix86_build_signbit_mask ( vmode , 0 , 1 ) ; mask = ix86_build_signbit_mask ( vmode , 0 , 0 ) ; if ( mode == SFmode ) copysign_insn = gen_copysignsf3_var ; else if ( mode == DFmode ) copysign_insn = gen_copysigndf3_var ; else copysign_insn = gen_copysigntf3_var ; emit_insn ( copysign_insn ( dest , NULL_RTX , op0 , op1 , nmask , mask ) ) ; } } </s>

Expand a copysign operation . Special case operand 0 being a constant .


<s> unsigned BPFRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return BPF :: R10 ; } </s>


<s> unsigned MipsRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; return TFI -> hasFP ( MF ) ? Mips :: FP : Mips :: SP ; } </s>


<s> static bool s390_loadrelative_operand_p ( rtx addr , rtx * symref , HOST_WIDE_INT * addend ) { HOST_WIDE_INT tmpaddend = 0 ; if ( GET_CODE ( addr ) == CONST ) addr = XEXP ( addr , 0 ) ; if ( GET_CODE ( addr ) == PLUS ) { if ( ! CONST_INT_P ( XEXP ( addr , 1 ) ) ) return false ; tmpaddend = INTVAL ( XEXP ( addr , 1 ) ) ; addr = XEXP ( addr , 0 ) ; } if ( GET_CODE ( addr ) == SYMBOL_REF || ( GET_CODE ( addr ) == UNSPEC && ( XINT ( addr , 1 ) == UNSPEC_GOTENT || XINT ( addr , 1 ) == UNSPEC_PLT31 ) ) ) { if ( symref ) * symref = addr ; if ( addend ) * addend = tmpaddend ; return true ; } return false ; } </s>

Return TRUE if ADDR is an operand valid for a load/store relative instruction . Be aware that the alignment of the operand needs to be checked separately . Valid addresses are single references or a sum of a reference and a constant integer . Return these parts in SYMREF and ADDEND . You can pass NULL in REF and/or ADDEND if you are not interested in these values . Literal pool references are * not * considered symbol references .


<s> const char * thumb_call_via_reg ( rtx reg ) { int regno = REGNO ( reg ) ; rtx * labelp ; gcc_assert ( regno < LR_REGNUM ) ; if ( in_text_section ( ) ) { thumb_call_reg_needed = 1 ; if ( thumb_call_via_label [ regno ] == NULL ) thumb_call_via_label [ regno ] = gen_label_rtx ( ) ; labelp = thumb_call_via_label + regno ; } else { if ( cfun -> machine -> call_via [ regno ] == NULL ) cfun -> machine -> call_via [ regno ] = gen_label_rtx ( ) ; labelp = cfun -> machine -> call_via + regno ; } output_asm_insn ( "bl\t%a0" , labelp ) ; return "" ; } </s>

Output a call-via instruction for thumb state .


<s>
StringRef
getPassName
(
)
const
override
{
return
"M68k MOVEM collapser pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> std :: pair < unsigned , const TargetRegisterClass * > HexagonTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : switch ( VT . SimpleTy ) { default : return { 0u , nullptr } ; case MVT :: i1 : case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : case MVT :: f32 : return { 0u , & Hexagon :: IntRegsRegClass } ; case MVT :: i64 : case MVT :: f64 : return { 0u , & Hexagon :: DoubleRegsRegClass } ; } break ; case 'a' : if ( VT != MVT :: i32 ) return { 0u , nullptr } ; return { 0u , & Hexagon :: ModRegsRegClass } ; case 'q' : switch ( VT . getSizeInBits ( ) ) { default : return { 0u , nullptr } ; case 64 : case 128 : return { 0u , & Hexagon :: HvxQRRegClass } ; } break ; case 'v' : switch ( VT . getSizeInBits ( ) ) { default : return { 0u , nullptr } ; case 512 : return { 0u , & Hexagon :: HvxVRRegClass } ; case 1024 : if ( Subtarget . hasV60Ops ( ) && Subtarget . useHVX128BOps ( ) ) return { 0u , & Hexagon :: HvxVRRegClass } ; return { 0u , & Hexagon :: HvxWRRegClass } ; case 2048 : return { 0u , & Hexagon :: HvxWRRegClass } ; } break ; default : return { 0u , nullptr } ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> bool M68kExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { STI = & static_cast < const M68kSubtarget & > ( MF . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; MFI = MF . getInfo < M68kMachineFunctionInfo > ( ) ; FL = STI -> getFrameLowering ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : MF ) Modified |= ExpandMBB ( MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool X86TargetLowering :: isShuffleMaskLegal ( ArrayRef < int > Mask , EVT VT ) const { if ( ! VT . isSimple ( ) ) return false ; if ( VT . getSimpleVT ( ) . getScalarType ( ) == MVT :: i1 ) return false ; if ( VT . getSimpleVT ( ) . getSizeInBits ( ) == 64 ) return false ; return isTypeLegal ( VT . getSimpleVT ( ) ) ; } </s>


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , JIT , RM ) , getEffectiveX86CodeModel ( CM , JIT , TT . getArch ( ) == Triple :: x86_64 ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , IsJIT ( JIT ) { if ( TT . isPS4 ( ) || TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = TT . isOSBinFormatMachO ( ) ; } setMachineOutliner ( true ) ; initAsmInfo ( ) ; } </s>


<s> int aarch64_hard_regno_nregs ( unsigned regno , machine_mode mode ) { switch ( aarch64_regno_regclass ( regno ) ) { case FP_REGS : case FP_LO_REGS : return ( GET_MODE_SIZE ( mode ) + UNITS_PER_VREG - 1 ) / UNITS_PER_VREG ; default : return ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } gcc_unreachable ( ) ; } </s>


<s> static rtx sparc_tls_got ( void ) { if ( flag_pic ) { crtl -> uses_pic_offset_table = 1 ; return pic_offset_table_rtx ; } if ( TARGET_SUN_TLS && TARGET_ARCH32 ) { load_got_register ( ) ; return global_offset_table_rtx ; } return copy_to_reg ( sparc_got ( ) ) ; } </s>

Return the Global Offset Table to be used in TLS mode .


<s>
const
MCPhysReg
*
AArch64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_AArch64_NoRegs_SaveList
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_AArch64_AllRegs_SaveList
;
else
if
(
isSVEFunction
(
*
MF
)
)
return
CSR_AArch64_SVE_AAPCS_SaveList
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
CXX_FAST_TLS
)
return
MF
->
getInfo
<
AArch64FunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_AArch64_CXX_TLS_Darwin_PE_SaveList
:
CSR_AArch64_CXX_TLS_Darwin_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
->
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_AArch64_AAPCS_SwiftError_SaveList
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
PreserveMost
)
return
CSR_AArch64_RT_MostRegs_SaveList
;
else
return
CSR_AArch64_AAPCS_SaveList
;
}
</s>


<s> void addLiveInAttr ( Register VReg , ISD :: ArgFlagsTy Flags ) { LiveInAttrs . push_back ( std :: make_pair ( VReg , Flags ) ) ; } </s>

This function associates attributes for each live-in virtual register .


<s> RegisterAggr & RegisterAggr :: clear ( const RegisterAggr & RG ) { Units . reset ( RG . Units ) ; return * this ; } </s>


<s> bool s390_match_ccmode ( rtx_insn * insn , machine_mode req_mode ) { int i ; if ( req_mode == VOIDmode ) return false ; if ( GET_CODE ( PATTERN ( insn ) ) == SET ) return s390_match_ccmode_set ( PATTERN ( insn ) , req_mode ) ; if ( GET_CODE ( PATTERN ( insn ) ) == PARALLEL ) for ( i = 0 ; i < XVECLEN ( PATTERN ( insn ) , 0 ) ; i ++ ) { rtx set = XVECEXP ( PATTERN ( insn ) , 0 , i ) ; if ( GET_CODE ( set ) == SET ) if ( ! s390_match_ccmode_set ( set , req_mode ) ) return false ; } return true ; } </s>

Return true if every SET in INSN that sets the CC register has source and destination with matching CC modes and that CC mode is at least as constrained as REQ_MODE .


<s> virtual unsigned int execute ( function * ) { return arc_predicate_delay_insns ( ) ; } </s>


<s>
SDValue
SparcTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
FNEG
:
case
ISD
::
FABS
:
return
LowerF64Op
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
,
*
this
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
llvm_unreachable
(
"TLS not implemented for Sparc."
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_SINT
(
Op
,
DAG
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerSINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
,
*
this
)
;
case
ISD
::
VAARG
:
return
LowerVAARG
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

Sparc
Sparc
"Should not custom lower this!"
ISD::FNEG
ISD::FABS
ISD::RETURNADDR
ISD::FRAMEADDR
ISD::GlobalTLSAddress
"TLS not implemented for Sparc."
ISD::GlobalAddress
ISD::BlockAddress
ISD::ConstantPool
ISD::FP_TO_SINT
ISD::SINT_TO_FP
ISD::BR_CC
ISD::SELECT_CC
ISD::VASTART
ISD::VAARG
ISD::DYNAMIC_STACKALLOC


<s> static bool is_load_insn1 ( rtx pat ) { if ( ! pat || pat == NULL_RTX ) return false ; if ( GET_CODE ( pat ) == SET ) return is_mem_ref ( SET_SRC ( pat ) ) ; if ( GET_CODE ( pat ) == PARALLEL ) { int i ; for ( i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) if ( is_load_insn1 ( XVECEXP ( pat , 0 , i ) ) ) return true ; } return false ; } </s>

Determine if PAT is a PATTERN of a load insn .


<s>
bool
SIRegisterInfo
::
eliminateSGPRToVGPRSpillFrameIndex
(
MachineBasicBlock
::
iterator
MI
,
int
FI
,
RegScavenger
*
RS
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
case
AMDGPU
::
SI_SPILL_S1024_SAVE
:
case
AMDGPU
::
SI_SPILL_S512_SAVE
:
case
AMDGPU
::
SI_SPILL_S256_SAVE
:
case
AMDGPU
::
SI_SPILL_S160_SAVE
:
case
AMDGPU
::
SI_SPILL_S128_SAVE
:
case
AMDGPU
::
SI_SPILL_S96_SAVE
:
case
AMDGPU
::
SI_SPILL_S64_SAVE
:
case
AMDGPU
::
SI_SPILL_S32_SAVE
:
return
spillSGPR
(
MI
,
FI
,
RS
,
true
)
;
case
AMDGPU
::
SI_SPILL_S1024_RESTORE
:
case
AMDGPU
::
SI_SPILL_S512_RESTORE
:
case
AMDGPU
::
SI_SPILL_S256_RESTORE
:
case
AMDGPU
::
SI_SPILL_S160_RESTORE
:
case
AMDGPU
::
SI_SPILL_S128_RESTORE
:
case
AMDGPU
::
SI_SPILL_S96_RESTORE
:
case
AMDGPU
::
SI_SPILL_S64_RESTORE
:
case
AMDGPU
::
SI_SPILL_S32_RESTORE
:
return
restoreSGPR
(
MI
,
FI
,
RS
,
true
)
;
default
:
llvm_unreachable
(
"not an SGPR spill instruction"
)
;
}
}
</s>


<s> bool aarch64_regno_ok_for_index_p ( int regno , bool strict_p ) { if ( ! HARD_REGISTER_NUM_P ( regno ) ) { if ( ! strict_p ) return true ; if ( ! reg_renumber ) return false ; regno = reg_renumber [ regno ] ; } return GP_REGNUM_P ( regno ) ; } </s>

Return true if register REGNO is a valid index register . STRICT_P is true if REG_OK_STRICT is in effect .


<s> static bool use_32bit_hwmult ( void ) { static const char * cached_match = NULL ; static bool cached_result ; int i ; if ( msp430_hwmult_type == MSP430_HWMULT_LARGE ) return true ; if ( target_mcu == NULL || msp430_hwmult_type != MSP430_HWMULT_AUTO ) return false ; if ( target_mcu == cached_match ) return cached_result ; cached_match = target_mcu ; for ( i = ARRAY_SIZE ( msp430_mcu_data ) ; i -- ; ) if ( strcasecmp ( target_mcu , msp430_mcu_data [ i ] . name ) == 0 ) return cached_result = msp430_mcu_data [ i ] . hwmpy == 4 ; return cached_result = false ; } </s>

Returns true if the current MCU has a second generation 32-bit hardware multiplier .


<s> EVT getVectorVT ( EVT ElemVT , unsigned NumElems ) const { return EVT :: getVectorVT ( * DAG . getContext ( ) , ElemVT , NumElems ) ; } </s>

Returns the EVT that represents a vector EC.Min elements in length , where each element is of type VT .


Set the cpu type and print out other fancy things , at the top of the file .


<s> void PPCDispatchGroupSBHazardRecognizer :: EmitNoop ( ) { unsigned Directive = DAG -> TM . getSubtarget < PPCSubtarget > ( ) . getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_PWR6 || Directive == PPC :: DIR_PWR7 || CurSlots == 6 ) { CurGroup . clear ( ) ; CurSlots = CurBranches = 0 ; } else { CurGroup . push_back ( nullptr ) ; ++ CurSlots ; } } </s>

EmitNoop - This callback is invoked when a noop was added to the instruction stream .


<s> FastISel * MipsTargetLowering :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) const { const MipsTargetMachine & TM = static_cast < const MipsTargetMachine & > ( funcInfo . MF -> getTarget ( ) ) ; bool UseFastISel = TM . Options . EnableFastISel && Subtarget . hasMips32 ( ) && ! Subtarget . hasMips32r6 ( ) && ! Subtarget . inMips16Mode ( ) && ! Subtarget . inMicroMipsMode ( ) ; if ( ! TM . isPositionIndependent ( ) || ! TM . getABI ( ) . IsO32 ( ) || Subtarget . useXGOT ( ) ) UseFastISel = false ; return UseFastISel ? Mips :: createFastISel ( funcInfo , libInfo ) : nullptr ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .

Mips Mips Mips Mips Mips Mips Mips Mips Mips::createFastISel


<s> MachineBasicBlock * getMBB ( ) const { return MBB ; } </s>

Return a reference to the basic block containing this bundle .


<s> static rtx loongarch_force_address ( rtx x , machine_mode mode ) { if ( ! loongarch_legitimate_address_p ( mode , x , false ) ) x = force_reg ( Pmode , x ) ; return x ; } </s>

If X is not a valid address for mode MODE , force it into a register .


<s>
const
char
*
output_move_double
(
rtx
operands
[
]
,
rtx
insn
)
{
rtx
dest
=
operands
[
0
]
;
rtx
src
=
operands
[
1
]
;
machine_mode
mode
=
GET_MODE
(
dest
)
;
if
(
GET_CODE
(
dest
)
==
REG
)
{
int
dest_regno
=
REGNO
(
dest
)
;
if
(
GPR_P
(
dest_regno
)
)
{
if
(
GET_CODE
(
src
)
==
REG
)
{
int
src_regno
=
REGNO
(
src
)
;
if
(
GPR_P
(
src_regno
)
)
return
"#"
;
else
if
(
FPR_P
(
src_regno
)
)
{
if
(
(
(
dest_regno
GPR_FIRST
)
&
1
)
==
0
&&
(
(
src_regno
FPR_FIRST
)
&
1
)
==
0
)
return
"movfgd %1, %0"
;
return
"#"
;
}
}
else
if
(
GET_CODE
(
src
)
==
MEM
)
{
if
(
dbl_memory_one_insn_operand
(
src
,
mode
)
)
return
"ldd%I1%U1 %M1, %0"
;
return
"#"
;
}
else
if
(
GET_CODE
(
src
)
==
CONST_INT
||
GET_CODE
(
src
)
==
CONST_DOUBLE
)
return
"#"
;
}
else
if
(
FPR_P
(
dest_regno
)
)
{
if
(
GET_CODE
(
src
)
==
REG
)
{
int
src_regno
=
REGNO
(
src
)
;
if
(
GPR_P
(
src_regno
)
)
{
if
(
(
(
dest_regno
FPR_FIRST
)
&
1
)
==
0
&&
(
(
src_regno
GPR_FIRST
)
&
1
)
==
0
)
return
"movgfd %1, %0"
;
return
"#"
;
}
else
if
(
FPR_P
(
src_regno
)
)
{
if
(
TARGET_DOUBLE
&&
(
(
dest_regno
FPR_FIRST
)
&
1
)
==
0
&&
(
(
src_regno
FPR_FIRST
)
&
1
)
==
0
)
return
"fmovd %1, %0"
;
return
"#"
;
}
}
else
if
(
GET_CODE
(
src
)
==
MEM
)
{
if
(
dbl_memory_one_insn_operand
(
src
,
mode
)
)
return
"lddf%I1%U1 %M1, %0"
;
return
"#"
;
}
else
if
(
ZERO_P
(
src
)
)
return
"#"
;
}
}
else
if
(
GET_CODE
(
dest
)
==
MEM
)
{
if
(
GET_CODE
(
src
)
==
REG
)
{
int
src_regno
=
REGNO
(
src
)
;
if
(
GPR_P
(
src_regno
)
)
{
if
(
(
(
src_regno
GPR_FIRST
)
&
1
)
==
0
&&
dbl_memory_one_insn_operand
(
dest
,
mode
)
)
return
"std%I0%U0 %1, %M0"
;
return
"#"
;
}
if
(
FPR_P
(
src_regno
)
)
{
if
(
(
(
src_regno
FPR_FIRST
)
&
1
)
==
0
&&
dbl_memory_one_insn_operand
(
dest
,
mode
)
)
return
"stdf%I0%U0 %1, %M0"
;
return
"#"
;
}
}
else
if
(
ZERO_P
(
src
)
)
{
if
(
dbl_memory_one_insn_operand
(
dest
,
mode
)
)
return
"std%I0%U0 %., %M0"
;
return
"#"
;
}
}
fatal_insn
(
"bad output_move_double operand"
,
insn
)
;
return
""
;
}
</s>

Return appropriate code to load up an 8 byte integer or floating point value


<s> virtual bool requiresVirtualBaseRegisters ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers used for more efficient stack access .


<s>
void
WebAssemblyTargetAsmStreamer
::
emitTableType
(
const
MCSymbolWasm
*
Sym
)
{
assert
(
Sym
->
isTable
(
)
)
;
const
wasm
::
WasmTableType
&
Type
=
Sym
->
getTableType
(
)
;
OS
<<
"\t.tabletype\t"
<<
Sym
->
getName
(
)
<<
", "
<<
WebAssembly
::
typeToString
(
static_cast
<
wasm
::
ValType
>
(
Type
.
ElemType
)
)
;
bool
HasMaximum
=
Type
.
Limits
.
Flags
&
wasm
::
WASM_LIMITS_FLAG_HAS_MAX
;
if
(
Type
.
Limits
.
Minimum
!=
0
||
HasMaximum
)
{
OS
<<
", "
<<
Type
.
Limits
.
Minimum
;
if
(
HasMaximum
)
OS
<<
", "
<<
Type
.
Limits
.
Maximum
;
}
OS
<<
'\n'
;
}
</s>

WebAssembly
WebAssembly
wasm::WasmTableType
"\t.tabletype\t"
", "
WebAssembly::typeToString
wasm::ValType
wasm::WASM_LIMITS_FLAG_HAS_MAX
0
", "
", "


"%qE attribute only applies to functions"

"%qE attribute argument not a string constant"

Handle an `` sp_switch '' attribute ; arguments as in struct attribute_spec.handler .


"Only floating point immediates are supported at the moment."


"Cannot spill SGPR to memory without RegScavenger"

"Exec is already saved, refuse to save again"

prepare - Reset state and prepare for a new spill placement computation .


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) -> findAssociatedFragment ( ) ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


Function that may creates more instructions for large value on adjusting stack pointer . In nds32 target , 'addi ' can be used for stack pointer adjustment in prologue/epilogue stage . However , sometimes there are too many local variables so that the adjustment value is not able to be fit in the 'addi ' instruction . One solution is to move value into a register and then use 'add ' instruction . In practice , we use TA_REGNUM ( $ r15 ) to accomplish this purpose . Also , we need to return zero for sp adjustment so that proglogue/epilogue knows there is no need to create 'addi ' instruction .


<s> bool RISCVTargetLowering :: mergeStoresAfterLegalization ( EVT VT ) const { return ! Subtarget . useRVVForFixedLengthVectors ( ) || ( VT . isFixedLengthVector ( ) && VT . getVectorElementType ( ) == MVT :: i1 ) ; } </s>

Do not merge vector stores after legalization because that may conflict with x86-specific store splitting optimizations .


<s> static bool isConditionalBranch ( unsigned Opc ) { switch ( Opc ) { default : return false ; case ARM64 :: TBZ : case ARM64 :: TBNZ : case ARM64 :: CBZW : case ARM64 :: CBNZW : case ARM64 :: CBZX : case ARM64 :: CBNZX : case ARM64 :: Bcc : return true ; } } </s>

Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block .


<s> static bool spe_func_has_64bit_regs_p ( void ) { rtx_insn * insns , * insn ; if ( crtl -> calls_eh_return || cfun -> calls_setjmp || crtl -> has_nonlocal_goto ) return true ; insns = get_insns ( ) ; for ( insn = NEXT_INSN ( insns ) ; insn != NULL_RTX ; insn = NEXT_INSN ( insn ) ) { if ( INSN_P ( insn ) ) { rtx i ; i = PATTERN ( insn ) ; if ( GET_CODE ( i ) == SET ) { machine_mode mode = GET_MODE ( SET_SRC ( i ) ) ; if ( SPE_VECTOR_MODE ( mode ) ) return true ; if ( TARGET_E500_DOUBLE && ( mode == DFmode || mode == TFmode ) ) return true ; } } } return false ; } </s>

Return true if the current function uses any GPRs in 64-bit SIMD mode .


<s> unsigned TGSIInstrInfo :: isLoadFromStackSlot ( const MachineInstr * mi , int & fi ) const { if ( ( mi -> getOpcode ( ) == TGSI :: LDpis || mi -> getOpcode ( ) == TGSI :: LDpfs || mi -> getOpcode ( ) == TGSI :: LDpiv || mi -> getOpcode ( ) == TGSI :: LDpfv ) && mi -> getOperand ( 1 ) . isFI ( ) ) { fi = mi -> getOperand ( 1 ) . getIndex ( ) ; return mi -> getOperand ( 0 ) . getReg ( ) ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> DecodeStatus HexagonDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & cs ) const { DecodeStatus Result = DecodeStatus :: Success ; bool Complete = false ; Size = 0 ; * CurrentBundle = & MI ; MI . setOpcode ( Hexagon :: BUNDLE ) ; MI . addOperand ( MCOperand :: createImm ( 0 ) ) ; while ( Result == Success && ! Complete ) { if ( Bytes . size ( ) < HEXAGON_INSTR_SIZE ) return MCDisassembler :: Fail ; MCInst * Inst = new ( getContext ( ) ) MCInst ; Result = getSingleInstruction ( * Inst , MI , Bytes , Address , cs , Complete ) ; MI . addOperand ( MCOperand :: createInst ( Inst ) ) ; Size += HEXAGON_INSTR_SIZE ; Bytes = Bytes . slice ( HEXAGON_INSTR_SIZE ) ; } if ( Result == MCDisassembler :: Fail ) return Result ; if ( Size > HEXAGON_MAX_PACKET_SIZE ) return MCDisassembler :: Fail ; const auto ArchSTI = Hexagon_MC :: getArchSubtarget ( & STI ) ; const auto STI_ = ( ArchSTI != nullptr ) ? * ArchSTI : STI ; HexagonMCChecker Checker ( getContext ( ) , * MCII , STI_ , MI , * getContext ( ) . getRegisterInfo ( ) , false ) ; if ( ! Checker . check ( ) ) return MCDisassembler :: Fail ; remapInstruction ( MI ) ; return MCDisassembler :: Success ; } </s>

Returns the disassembly of a single instruction .

Hexagon Hexagon 0 Hexagon::BUNDLE 0 Hexagon Hexagon


<s>
StringRef
getPassName
(
)
const
override
{
return
"Mips Constant Islands"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool AMDGPUIntrinsicInfo :: isOverloaded ( unsigned id ) const { } </s>

Returns true if the intrinsic can be overloaded .


<s>
void
PatmosLatencyQueue
::
dump
(
)
{
dbgs
(
)
<<
"PendingQueue:"
;
for
(
unsigned
i
=
0
;
i
<
PendingQueue
.
size
(
)
;
i
++
)
{
SUnit
*
SU
=
PendingQueue
[
i
]
;
if
(
i
>
0
)
dbgs
(
)
<<
","
;
dbgs
(
)
<<
" SU("
<<
SU
->
NodeNum
<<
"): Height "
<<
SU
->
getHeight
(
)
<<
" Depth "
<<
SU
->
getDepth
(
)
<<
" Tree: "
<<
Cmp
.
DFSResult
->
getSubtreeID
(
SU
)
<<
" @"
<<
Cmp
.
DFSResult
->
getSubtreeLevel
(
Cmp
.
DFSResult
->
getSubtreeID
(
SU
)
)
;
if
(
SU
->
isScheduleLow
)
dbgs
(
)
<<
" low "
;
}
dbgs
(
)
<<
"\nAvailableQueue:"
;
for
(
unsigned
i
=
0
;
i
<
AvailableQueue
.
size
(
)
;
i
++
)
{
SUnit
*
SU
=
AvailableQueue
[
i
]
;
if
(
i
>
0
)
dbgs
(
)
<<
","
;
dbgs
(
)
<<
" SU("
<<
SU
->
NodeNum
<<
") Height "
<<
SU
->
getHeight
(
)
<<
" Depth "
<<
SU
->
getDepth
(
)
<<
" ILP: "
<<
Cmp
.
DFSResult
->
getILP
(
SU
)
;
if
(
SU
->
isScheduleLow
)
dbgs
(
)
<<
" low "
;
}
dbgs
(
)
<<
"\n"
;
}
</s>

Dump the plan to stderr ( for debugging ) .

Patmos
Patmos
"PendingQueue:"
0
0
","
" SU("
"): Height "
" Depth "
" Tree: "
" @"
" low "
"\nAvailableQueue:"
0
0
","
" SU("
") Height "
" Depth "
" ILP: "
" low "
"\n"


<s> SDNode * HexagonDAGToDAGISel :: Select ( SDNode * N ) { if ( N -> isMachineOpcode ( ) ) { N -> setNodeId ( - 1 ) ; return nullptr ; } switch ( N -> getOpcode ( ) ) { case ISD :: Constant : return SelectConstant ( N ) ; case ISD :: ConstantFP : return SelectConstantFP ( N ) ; case ISD :: FrameIndex : return SelectFrameIndex ( N ) ; case ISD :: ADD : return SelectAdd ( N ) ; case ISD :: SHL : return SelectSHL ( N ) ; case ISD :: LOAD : return SelectLoad ( N ) ; case ISD :: STORE : return SelectStore ( N ) ; case ISD :: MUL : return SelectMul ( N ) ; case ISD :: AND : case ISD :: OR : case ISD :: XOR : case ISD :: FABS : case ISD :: FNEG : return SelectBitOp ( N ) ; case ISD :: ZERO_EXTEND : return SelectZeroExtend ( N ) ; case ISD :: INTRINSIC_W_CHAIN : return SelectIntrinsicWChain ( N ) ; case ISD :: INTRINSIC_WO_CHAIN : return SelectIntrinsicWOChain ( N ) ; } return SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .

Hexagon Hexagon 1 ISD::Constant ISD::ConstantFP ISD::FrameIndex ISD::ADD ISD::SHL ISD::LOAD ISD::STORE ISD::MUL ISD::AND ISD::OR ISD::XOR ISD::FABS ISD::FNEG ISD::ZERO_EXTEND ISD::INTRINSIC_W_CHAIN ISD::INTRINSIC_WO_CHAIN


<s> static char nds32_byte_to_size ( int byte ) { switch ( byte ) { case 4 : return 'w' ; case 2 : return 'h' ; case 1 : return 'b' ; default : gcc_unreachable ( ) ; } } </s>

A helper function to return character based on byte size .


<s>
void
NVPTXInstPrinter
::
printRegName
(
raw_ostream
&
OS
,
unsigned
RegNo
)
const
{
unsigned
RCId
=
(
RegNo
>>
28
)
;
switch
(
RCId
)
{
default
:
report_fatal_error
(
"Bad virtual register encoding"
)
;
case
0
:
OS
<<
getRegisterName
(
RegNo
)
;
return
;
case
1
:
OS
<<
"%p"
;
break
;
case
2
:
OS
<<
"%rs"
;
break
;
case
3
:
OS
<<
"%r"
;
break
;
case
4
:
OS
<<
"%rd"
;
break
;
case
5
:
OS
<<
"%f"
;
break
;
case
6
:
OS
<<
"%fd"
;
break
;
case
7
:
OS
<<
"%h"
;
break
;
case
8
:
OS
<<
"%hh"
;
break
;
}
unsigned
VReg
=
RegNo
&
0x0FFFFFFF
;
OS
<<
VReg
;
}
</s>


<s> static void epiphany_setup_incoming_varargs ( cumulative_args_t cum , const function_arg_info & arg , int * pretend_size , int no_rtl ) { int first_anon_arg ; CUMULATIVE_ARGS next_cum ; machine_function_t * mf = MACHINE_FUNCTION ( cfun ) ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) ) gcc_assert ( arg . mode != BLKmode ) ; next_cum = * get_cumulative_args ( cum ) ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) ) next_cum = ( ROUND_ADVANCE_CUM ( next_cum , arg . mode , arg . type ) + ROUND_ADVANCE_ARG ( arg . mode , arg . type ) ) ; first_anon_arg = next_cum ; if ( first_anon_arg < MAX_EPIPHANY_PARM_REGS && ! no_rtl ) { int first_reg_offset = first_anon_arg ; * pretend_size = ( ( MAX_EPIPHANY_PARM_REGS - first_reg_offset ) * UNITS_PER_WORD ) ; } mf -> args_parsed = 1 ; mf -> pretend_args_odd = ( ( * pretend_size & UNITS_PER_WORD ) ? 1 : 0 ) ; } </s>

Do any needed setup for a variadic function . For the EPIPHANY , we actually emit the code in epiphany_expand_prologue . CUM has not been updated for the last named argument which has type TYPE and mode MODE , and we rely on this fact .


<s> static void arm_option_restore ( struct gcc_options * , struct cl_target_option * ptr ) { arm_configure_build_target ( & arm_active_target , ptr , & global_options_set , false ) ; } </s>


<s> static bool need_to_save ( unsigned int regno ) { if ( is_interrupt_func ( cfun -> decl ) ) { if ( regno < 8 ) return true ; if ( regno > 23 ) return false ; if ( ! crtl -> is_leaf && call_used_or_fixed_reg_p ( regno ) && regno < 22 ) return true ; return df_regs_ever_live_p ( regno ) ; } if ( regno == FRAME_POINTER_REGNUM && ( frame_pointer_needed || df_regs_ever_live_p ( regno ) ) ) return true ; if ( fixed_regs [ regno ] ) return false ; if ( crtl -> calls_eh_return ) return true ; if ( df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) ) return true ; return false ; } </s>

Returns true if the given register needs to be saved by the current function .


<s> static int ix86_enum_va_list ( int idx , const char * * pname , tree * ptree ) { if ( TARGET_64BIT ) { switch ( idx ) { default : break ; case 0 : * ptree = ms_va_list_type_node ; * pname = "__builtin_ms_va_list" ; return 1 ; case 1 : * ptree = sysv_va_list_type_node ; * pname = "__builtin_sysv_va_list" ; return 1 ; } } return 0 ; } </s>

Iterate through the target-specific builtin types for va_list . IDX denotes the iterator , * PTREE is set to the result type of the va_list builtin , and * PNAME to its internal type . Returns zero if there is no element for this index , otherwise IDX should be increased upon the next call . Note , do not iterate a base builtin 's name like __builtin_va_list . Used from c_common_nodes_and_builtins .


<s> EVT SICTargetLowering :: getSetCCResultType ( const DataLayout & , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i24 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> bool X86InstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF , bool OutlineFromLinkOnceODRs ) const { const Function & F = MF . getFunction ( ) ; if ( ! F . hasFnAttribute ( Attribute :: NoRedZone ) ) { const X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; if ( ! X86FI || X86FI -> getUsesRedZone ( ) ) return false ; } if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) ) return false ; return true ; } </s>

Return true if the function can safely be outlined from .


<s> bool X86TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , MVT VT ) const { if ( VT . getSizeInBits ( ) == 64 ) return false ; return ( VT . getVectorNumElements ( ) == 2 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isMOVLMask ( M , VT ) || isSHUFPMask ( M , VT ) || isPSHUFDMask ( M , VT ) || isPSHUFHWMask ( M , VT ) || isPSHUFLWMask ( M , VT ) || isUNPCKLMask ( M , VT ) || isUNPCKHMask ( M , VT ) || isUNPCKL_v_undef_Mask ( M , VT ) || isUNPCKH_v_undef_Mask ( M , VT ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> bool X86TargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const { return isInt < 32 > ( Imm ) ; } </s>

Return true if the specified immediate is legal icmp immediate , that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register .


<s> void rs6000_expand_extract_even ( rtx target , rtx op0 , rtx op1 ) { machine_mode vmode = GET_MODE ( target ) ; unsigned i , nelt = GET_MODE_NUNITS ( vmode ) ; vec_perm_builder perm ( nelt , nelt , 1 ) ; for ( i = 0 ; i < nelt ; i ++ ) perm . quick_push ( i * 2 ) ; rs6000_do_expand_vec_perm ( target , op0 , op1 , vmode , perm ) ; } </s>


Return the opcode of the special instruction to be used to load the constant X .


<s> int frv_issue_rate ( void ) { if ( ! TARGET_PACK ) return 1 ; switch ( frv_cpu_type ) { default : case FRV_CPU_FR300 : case FRV_CPU_SIMPLE : return 1 ; case FRV_CPU_FR400 : case FRV_CPU_FR405 : case FRV_CPU_FR450 : return 2 ; case FRV_CPU_GENERIC : case FRV_CPU_FR500 : case FRV_CPU_TOMCAT : return 4 ; case FRV_CPU_FR550 : return 8 ; } } </s>


<s> bool AMDGPUTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { EVT ScalarVT = VT . getScalarType ( ) ; return ( ScalarVT == MVT :: f32 || ScalarVT == MVT :: f64 || ( ScalarVT == MVT :: f16 && Subtarget -> has16BitInsts ( ) ) ) ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> bool doInitialization ( Loop * L , LPPassManager & LPM ) override { LoadPairs . clear ( ) ; WideLoads . clear ( ) ; return true ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s>
void
RISCVAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
MCFixupKind
Kind
=
Fixup
.
getKind
(
)
;
if
(
Kind
>=
FirstLiteralRelocationKind
)
return
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Kind
)
;
if
(
!
Value
)
return
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
Ctx
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
unsigned
NumBytes
=
alignTo
(
Info
.
TargetSize
+
Info
.
TargetOffset
,
8
)
/
8
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
void
print
(
DiagnosticPrinter
&
DP
)
const
override
{
std
::
string
Str
;
raw_string_ostream
OS
(
Str
)
;
if
(
DLoc
)
{
auto
DIL
=
DLoc
.
get
(
)
;
StringRef
Filename
=
DIL
->
getFilename
(
)
;
unsigned
Line
=
DIL
->
getLine
(
)
;
unsigned
Column
=
DIL
->
getColumn
(
)
;
OS
<<
Filename
<<
':'
<<
Line
<<
':'
<<
Column
<<
' '
;
}
OS
<<
"in function "
<<
Fn
.
getName
(
)
<<
' '
<<
*
Fn
.
getFunctionType
(
)
<<
'\n'
<<
Description
;
if
(
Value
)
Value
->
print
(
OS
)
;
OS
<<
'\n'
;
OS
.
flush
(
)
;
DP
<<
Str
;
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> bool X86TargetLowering :: isVectorLoadExtDesirable ( SDValue ExtVal ) const { EVT SrcVT = ExtVal . getOperand ( 0 ) . getValueType ( ) ; if ( SrcVT . getScalarType ( ) == MVT :: i1 ) return false ; return true ; } </s>

Return true if folding a vector load into ExtVal ( a sign , zero , or any extend node ) is profitable .


<s> bool isImm ( ) const override { return Kind == KindTy :: Immediate ; } </s>


<s> Register CSKYTargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { return CSKY :: R0 ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


" does NOT need to be EXPORTed [not a class]\n"

" does NOT need to be EXPORTed [no key function]\n"

" does NOT need to be EXPORTed [key function not defined]\n"

" does NOT need to be EXPORTed [no non-pure virtuals or ctors/dtors with dllimport]\n"

" does NOT need to be EXPORTed [no inline ctor/dtor]\n"

Decide if a class needs its vtable and rtti exporting .


<s> void gen_shifty_op ( int code , rtx * operands ) { int value = INTVAL ( operands [ 2 ] ) ; int max , i ; value = value & 31 ; if ( value == 31 ) { if ( code == LSHIFTRT ) { emit_insn ( gen_rotlsi3_1 ( operands [ 0 ] , operands [ 0 ] ) ) ; emit_insn ( gen_movt ( operands [ 0 ] , get_t_reg_rtx ( ) ) ) ; return ; } else if ( code == ASHIFT ) { if ( REG_P ( operands [ 0 ] ) && REGNO ( operands [ 0 ] ) == 0 ) { emit_insn ( gen_andsi3 ( operands [ 0 ] , operands [ 0 ] , const1_rtx ) ) ; emit_insn ( gen_rotlsi3_31 ( operands [ 0 ] , operands [ 0 ] ) ) ; return ; } } } else if ( value == 0 ) { emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , operands [ 0 ] ) ) ; return ; } max = ashl_lshr_seq [ value ] . insn_count ; for ( i = 0 ; i < max ; i ++ ) gen_ashift ( code , ashl_lshr_seq [ value ] . amount [ i ] , operands [ 0 ] ) ; } </s>

Output RTL to split a constant shift into its component SH constant shift instructions .


<s> void WebAssemblyFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { uint64_t StackSize = MF . getFrameInfo ( ) . getStackSize ( ) ; if ( ! needsSP ( MF ) || ! needsSPWriteback ( MF ) ) return ; const auto * TII = MF . getSubtarget < WebAssemblySubtarget > ( ) . getInstrInfo ( ) ; auto & MRI = MF . getRegInfo ( ) ; auto InsertPt = MBB . getFirstTerminator ( ) ; DebugLoc DL ; if ( InsertPt != MBB . end ( ) ) DL = InsertPt -> getDebugLoc ( ) ; unsigned SPReg = 0 ; if ( hasBP ( MF ) ) { auto FI = MF . getInfo < WebAssemblyFunctionInfo > ( ) ; SPReg = FI -> getBasePointerVreg ( ) ; } else if ( StackSize ) { const TargetRegisterClass * PtrRC = MRI . getTargetRegisterInfo ( ) -> getPointerRegClass ( MF ) ; unsigned OffsetReg = MRI . createVirtualRegister ( PtrRC ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( WebAssembly :: CONST_I32 ) , OffsetReg ) . addImm ( StackSize ) ; SPReg = MRI . createVirtualRegister ( PtrRC ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( WebAssembly :: ADD_I32 ) , SPReg ) . addReg ( hasFP ( MF ) ? WebAssembly :: FP32 : WebAssembly :: SP32 ) . addReg ( OffsetReg ) ; } else { SPReg = hasFP ( MF ) ? WebAssembly :: FP32 : WebAssembly :: SP32 ; } writeSPToGlobal ( SPReg , MF , MBB , InsertPt , DL ) ; } </s>


<s> unsigned TVMInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { const MCInstrDesc & Desc = MI . getDesc ( ) ; switch ( Desc . getOpcode ( ) ) { case TargetOpcode :: CFI_INSTRUCTION : case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return 0 ; case TargetOpcode :: INLINEASM : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; return TII . getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } } return 8 ; } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s>
bool
Z80InstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
,
UnCondBrIter
=
I
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
!
isUnpredicatedTerminator
(
*
I
)
)
break
;
if
(
!
I
->
isBranch
(
)
)
return
true
;
if
(
!
I
->
getOperand
(
0
)
.
isMBB
(
)
)
return
true
;
if
(
I
->
getNumOperands
(
)
==
1
)
{
UnCondBrIter
=
I
;
if
(
!
AllowModify
)
{
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
continue
;
}
while
(
std
::
next
(
I
)
!=
MBB
.
end
(
)
)
std
::
next
(
I
)
->
eraseFromParent
(
)
;
Cond
.
clear
(
)
;
FBB
=
nullptr
;
if
(
MBB
.
isLayoutSuccessor
(
I
->
getOperand
(
0
)
.
getMBB
(
)
)
)
{
TBB
=
nullptr
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
UnCondBrIter
=
I
;
continue
;
}
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
continue
;
}
assert
(
I
->
getNumExplicitOperands
(
)
==
2
&&
"Invalid conditional branch"
)
;
Z80
::
CondCode
BranchCode
=
Z80
::
CondCode
(
I
->
getOperand
(
1
)
.
getImm
(
)
)
;
if
(
Cond
.
empty
(
)
)
{
MachineBasicBlock
*
TargetBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
if
(
AllowModify
&&
UnCondBrIter
!=
MBB
.
end
(
)
&&
MBB
.
isLayoutSuccessor
(
TargetBB
)
)
{
BranchCode
=
GetOppositeBranchCondition
(
BranchCode
)
;
MachineBasicBlock
::
iterator
OldInst
=
I
;
BuildMI
(
MBB
,
UnCondBrIter
,
MBB
.
findDebugLoc
(
I
)
,
get
(
Z80
::
JQCC
)
)
.
addMBB
(
UnCondBrIter
->
getOperand
(
0
)
.
getMBB
(
)
)
.
addImm
(
BranchCode
)
;
BuildMI
(
MBB
,
UnCondBrIter
,
MBB
.
findDebugLoc
(
I
)
,
get
(
Z80
::
JQ
)
)
.
addMBB
(
TargetBB
)
;
OldInst
->
eraseFromParent
(
)
;
UnCondBrIter
->
eraseFromParent
(
)
;
UnCondBrIter
=
MBB
.
end
(
)
;
I
=
MBB
.
end
(
)
;
continue
;
}
FBB
=
TBB
;
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
BranchCode
)
)
;
continue
;
}
return
true
;
}
return
false
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


runOnMachineFunction - Emit the function body .


<s> bool SystemZShortenInst :: runOnMachineFunction ( MachineFunction & F ) { TII = static_cast < const SystemZInstrInfo * > ( F . getSubtarget ( ) . getInstrInfo ( ) ) ; bool Changed = false ; for ( auto & MBB : F ) Changed |= processBlock ( MBB ) ; return Changed ; } </s>


<s> void finishLayout ( MCAssembler const & Asm , MCAsmLayout & Layout ) const override { for ( auto I : Layout . getSectionOrder ( ) ) { auto & Fragments = I -> getFragmentList ( ) ; for ( auto & J : Fragments ) { switch ( J . getKind ( ) ) { default : break ; case MCFragment :: FT_Align : { auto Size = Asm . computeFragmentSize ( Layout , J ) ; for ( auto K = J . getIterator ( ) ; K != Fragments . begin ( ) && Size >= HEXAGON_PACKET_SIZE ; ) { -- K ; switch ( K -> getKind ( ) ) { default : break ; case MCFragment :: FT_Align : { Size = 0 ; break ; } case MCFragment :: FT_Relaxable : { auto & RF = cast < MCRelaxableFragment > ( * K ) ; auto & Inst = const_cast < MCInst & > ( RF . getInst ( ) ) ; while ( Size > 0 && HexagonMCInstrInfo :: bundleSize ( Inst ) < 4 ) { MCInst * Nop = new ( Asm . getContext ( ) ) MCInst ; Nop -> setOpcode ( Hexagon :: A2_nop ) ; Inst . addOperand ( MCOperand :: createInst ( Nop ) ) ; Size -= 4 ; if ( ! HexagonMCChecker ( * MCII , RF . getSubtargetInfo ( ) , Inst , Inst , * Asm . getContext ( ) . getRegisterInfo ( ) ) . check ( ) ) { Inst . erase ( Inst . end ( ) - 1 ) ; Size = 0 ; } } bool Error = HexagonMCShuffle ( * MCII , RF . getSubtargetInfo ( ) , Inst ) ; ( void ) Error ; ReplaceInstruction ( Asm . getEmitter ( ) , RF , Inst ) ; Layout . invalidateFragmentsFrom ( & RF ) ; Size = 0 ; break ; } } } } } } } } </s>

Give backend an opportunity to finish layout after relaxation .


<s> bool processBlock ( MachineBasicBlock & MBB ) { bool Changed = false ; for ( auto & MI : MBB ) { if ( ! hasTOCLoReloc ( MI ) ) continue ; MI . addOperand ( MachineOperand :: CreateReg ( PPC :: X2 , false , true ) ) ; Changed = true ; } return Changed ; } </s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s> int xtensa_expand_block_move ( rtx * operands ) { static const machine_mode mode_from_align [ ] = { VOIDmode , QImode , HImode , VOIDmode , SImode , } ; rtx dst_mem = operands [ 0 ] ; rtx src_mem = operands [ 1 ] ; HOST_WIDE_INT bytes , align ; int num_pieces , move_ratio ; rtx temp [ 2 ] ; machine_mode mode [ 2 ] ; int amount [ 2 ] ; bool active [ 2 ] ; int phase = 0 ; int next ; int offset_ld = 0 ; int offset_st = 0 ; rtx x ; if ( ! optimize || ( GET_CODE ( operands [ 2 ] ) != CONST_INT ) ) return 0 ; bytes = INTVAL ( operands [ 2 ] ) ; align = INTVAL ( operands [ 3 ] ) ; if ( bytes <= 0 ) return 0 ; if ( align > MOVE_MAX ) align = MOVE_MAX ; move_ratio = 4 ; if ( optimize > 2 ) move_ratio = LARGEST_MOVE_RATIO ; num_pieces = ( bytes / align ) + ( bytes % align ) ; if ( num_pieces > move_ratio ) return 0 ; x = XEXP ( dst_mem , 0 ) ; if ( ! REG_P ( x ) ) { x = force_reg ( Pmode , x ) ; dst_mem = replace_equiv_address ( dst_mem , x ) ; } x = XEXP ( src_mem , 0 ) ; if ( ! REG_P ( x ) ) { x = force_reg ( Pmode , x ) ; src_mem = replace_equiv_address ( src_mem , x ) ; } active [ 0 ] = active [ 1 ] = false ; do { next = phase ; phase ^= 1 ; if ( bytes > 0 ) { int next_amount ; next_amount = ( bytes >= 4 ? 4 : ( bytes >= 2 ? 2 : 1 ) ) ; next_amount = MIN ( next_amount , align ) ; amount [ next ] = next_amount ; mode [ next ] = mode_from_align [ next_amount ] ; temp [ next ] = gen_reg_rtx ( mode [ next ] ) ; x = adjust_address ( src_mem , mode [ next ] , offset_ld ) ; emit_insn ( gen_rtx_SET ( temp [ next ] , x ) ) ; offset_ld += next_amount ; bytes -= next_amount ; active [ next ] = true ; } if ( active [ phase ] ) { active [ phase ] = false ; x = adjust_address ( dst_mem , mode [ phase ] , offset_st ) ; emit_insn ( gen_rtx_SET ( x , temp [ phase ] ) ) ; offset_st += amount [ phase ] ; } } while ( active [ next ] ) ; return 1 ; } </s>

Try to expand a block move operation to an RTL block move instruction . If not optimizing or if the block size is not a constant or if the block is small , the expansion fails and GCC falls back to calling memcpy ( ) . operands [ 0 ] is the destination operands [ 1 ] is the source operands [ 2 ] is the length operands [ 3 ] is the alignment


"SIInstrInfo::storeRegToStackSlot - Do not know how to"

Store the specified register of the given register class to the specified stack frame index .


<s> MachineBasicBlock :: iterator RISCVFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { Register SPReg = RISCV :: X2 ; DebugLoc DL = MI -> getDebugLoc ( ) ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = MI -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { Amount = alignSPAdjust ( Amount ) ; if ( MI -> getOpcode ( ) == RISCV :: ADJCALLSTACKDOWN ) Amount = - Amount ; adjustReg ( MBB , MI , DL , SPReg , SPReg , Amount , MachineInstr :: NoFlags ) ; } } return MBB . erase ( MI ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool WebAssemblyRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { return ! MF . getFunction ( ) -> hasFnAttribute ( "no-realign-stack" ) ; } </s>

True if the stack can be realigned for the target .


<s> bool WebAssemblyAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( Count == 0 ) return true ; return false ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> static rtx alphaev5_next_group ( rtx insn , int * pin_use , int * plen ) { int len , in_use ; len = in_use = 0 ; if ( ! INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == CLOBBER || GET_CODE ( PATTERN ( insn ) ) == USE ) goto next_and_done ; while ( 1 ) { enum alphaev5_pipe pipe ; pipe = alphaev5_insn_pipe ( insn ) ; switch ( pipe ) { case EV5_STOP : if ( in_use ) goto done ; if ( recog_memoized ( insn ) < 0 ) len = - 1 ; else len = get_attr_length ( insn ) ; goto next_and_done ; case EV5_E01 : if ( in_use & EV5_E0 ) { if ( in_use & EV5_E1 ) goto done ; in_use |= EV5_E1 ; } else in_use |= EV5_E0 | EV5_E01 ; break ; case EV5_E0 : if ( in_use & EV5_E0 ) { if ( ! ( in_use & EV5_E01 ) || ( in_use & EV5_E1 ) ) goto done ; in_use |= EV5_E1 ; } in_use |= EV5_E0 ; break ; case EV5_E1 : if ( in_use & EV5_E1 ) goto done ; in_use |= EV5_E1 ; break ; case EV5_FAM : if ( in_use & EV5_FA ) { if ( in_use & EV5_FM ) goto done ; in_use |= EV5_FM ; } else in_use |= EV5_FA | EV5_FAM ; break ; case EV5_FA : if ( in_use & EV5_FA ) goto done ; in_use |= EV5_FA ; break ; case EV5_FM : if ( in_use & EV5_FM ) goto done ; in_use |= EV5_FM ; break ; case EV5_NONE : break ; default : gcc_unreachable ( ) ; } len += 4 ; if ( GET_CODE ( insn ) == JUMP_INSN ) goto next_and_done ; next : insn = next_nonnote_insn ( insn ) ; if ( ! insn || ! INSN_P ( insn ) ) goto done ; if ( GET_MODE ( insn ) == TImode ) goto done ; if ( GET_CODE ( insn ) == CLOBBER || GET_CODE ( insn ) == USE ) goto next ; } next_and_done : insn = next_nonnote_insn ( insn ) ; done : * plen = len ; * pin_use = in_use ; return insn ; } </s>

IN_USE is a mask of the slots currently filled within the insn group . The mask bits come from alphaev5_pipe above . If EV5_E01 is set , then the insn in EV5_E0 can be swapped by the hardware into EV5_E1 . LEN is , of course , the length of the group in bytes .


<s>
static
bool
v850_handle_memory_option
(
enum
small_memory_type
type
,
const
char
*
value
)
{
int
i
,
size
;
if
(
*
value
!=
'-'
&&
*
value
!=
'='
)
return
false
;
value
++
;
for
(
i
=
0
;
value
[
i
]
;
i
++
)
if
(
!
ISDIGIT
(
value
[
i
]
)
)
return
false
;
size
=
atoi
(
value
)
;
if
(
size
>
small_memory
[
type
]
.
physical_max
)
error
(
"value passed to %<-m%s%> is too large"
,
small_memory
[
type
]
.
name
)
;
else
small_memory
[
type
]
.
max
=
size
;
return
true
;
}
</s>

Set the maximum size of small memory area TYPE to the value given by VALUE . Return true if VALUE was syntactically correct . VALUE starts with the argument separator : either `` - '' or `` = '' .


<s> BitVector SparcRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const SparcSubtarget & Subtarget = MF . getSubtarget < SparcSubtarget > ( ) ; Reserved . set ( SP :: G1 ) ; if ( ReserveAppRegisters ) { Reserved . set ( SP :: G2 ) ; Reserved . set ( SP :: G3 ) ; Reserved . set ( SP :: G4 ) ; } if ( ! Subtarget . is64Bit ( ) ) Reserved . set ( SP :: G5 ) ; Reserved . set ( SP :: O6 ) ; Reserved . set ( SP :: I6 ) ; Reserved . set ( SP :: I7 ) ; Reserved . set ( SP :: G0 ) ; Reserved . set ( SP :: G6 ) ; Reserved . set ( SP :: G7 ) ; if ( ! Subtarget . isV9 ( ) ) { for ( unsigned n = 0 ; n != 16 ; ++ n ) { for ( MCRegAliasIterator AI ( SP :: D16 + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; } } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void setMustSaveLR ( bool U ) { MustSaveLR = U ; } </s>

MustSaveLR - This is set when the prolog/epilog inserter does its initial scan of the function .


<s> SDValue GBZ80TargetLowering :: LowerCallResult ( SDValue Chain , SDValue Flag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_GBZ80 ) ; for ( unsigned i = 0 , e = Ins . size ( ) ; i != e ; i ++ ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , Flag ) . getValue ( 1 ) ; Flag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> void AMDGPUCFGStructurizer :: removeSuccessor ( MachineBasicBlock * MBB ) { while ( MBB -> succ_size ( ) ) MBB -> removeSuccessor ( * MBB -> succ_begin ( ) ) ; } </s>

Remove specified successor from the successors list of this MachineBasicBlock .


<s> static bool xtensa_split_imm_two_addends ( HOST_WIDE_INT imm , HOST_WIDE_INT v [ 2 ] ) { HOST_WIDE_INT v0 , v1 ; if ( imm < - 32768 ) v0 = - 32768 , v1 = imm + 32768 ; else if ( imm > 32512 ) v0 = 32512 , v1 = imm - 32512 ; else if ( TARGET_DENSITY && xtensa_simm12b ( imm ) ) return false ; else v0 = ( imm + 128 ) & ~ 255L , v1 = imm - v0 ; if ( xtensa_simm8 ( v1 ) || xtensa_simm8x256 ( v1 ) ) { v [ 0 ] = v0 , v [ 1 ] = v1 ; return true ; } return false ; } </s>

Try to split an integer value into what are suitable for two consecutive immediate addition instructions , ADDI or ADDMI .


<s> inline tree tuple_type_field ( tree type ) { for ( tree field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) if ( TREE_CODE ( field ) == FIELD_DECL ) return field ; gcc_unreachable ( ) ; } </s>

Return the single field in tuple type TYPE .


<s> void emitValueImpl ( const MCExpr * Value , unsigned Size , SMLoc Loc ) override { const MCExpr * A , * B ; if ( ! requiresFixups ( getContext ( ) , Value , A , B ) ) return MCELFStreamer :: emitValueImpl ( Value , Size , Loc ) ; MCStreamer :: emitValueImpl ( Value , Size , Loc ) ; MCDataFragment * DF = getOrCreateDataFragment ( ) ; flushPendingLabels ( DF , DF -> getContents ( ) . size ( ) ) ; MCDwarfLineEntry :: make ( this , getCurrentSectionOnly ( ) ) ; unsigned Add , Sub ; std :: tie ( Add , Sub ) = getRelocPairForSize ( Size ) ; DF -> getFixups ( ) . push_back ( MCFixup :: create ( DF -> getContents ( ) . size ( ) , A , static_cast < MCFixupKind > ( Add ) , Loc ) ) ; DF -> getFixups ( ) . push_back ( MCFixup :: create ( DF -> getContents ( ) . size ( ) , B , static_cast < MCFixupKind > ( Sub ) , Loc ) ) ; DF -> getContents ( ) . resize ( DF -> getContents ( ) . size ( ) + Size , 0 ) ; } </s>

Overriding these functions allows us to dismiss all labels that are candidates for marking as microMIPS when .word/.long/.4byte etc directives are emitted .


<s> static bool note_csky_invalid_constants ( rtx_insn * insn , HOST_WIDE_INT address , int do_pushes ) { bool result = false ; int opno ; extract_constrain_insn ( insn ) ; if ( recog_data . n_alternatives == 0 ) return false ; preprocess_constraints ( insn ) ; const operand_alternative * op_alt = which_op_alt ( ) ; for ( opno = 0 ; opno < recog_data . n_operands ; opno ++ ) { if ( recog_data . operand_type [ opno ] != OP_IN ) continue ; if ( op_alt [ opno ] . memory_ok ) { rtx op = recog_data . operand [ opno ] ; if ( CONSTANT_P ( op ) ) { if ( do_pushes ) push_csky_minipool_fix ( insn , address , recog_data . operand_loc [ opno ] , recog_data . operand_mode [ opno ] , op ) ; result = true ; } } } return result ; } </s>

Scan INSN and note any of its operands that need fixing . If DO_PUSHES is false we do not actually push any of the fixups needed . The function returns TRUE if any fixups were needed/pushed .


<s> bool X86FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> void mips_split_call ( rtx insn , rtx call_pattern ) { emit_call_insn ( call_pattern ) ; if ( ! find_reg_note ( insn , REG_NORETURN , 0 ) ) mips_restore_gp_from_cprestore_slot ( gen_rtx_REG ( Pmode , POST_CALL_TMP_REG ) ) ; } </s>

Split call instruction INSN into a $ gp-clobbering call and ( where necessary ) an instruction to restore $ gp from its save slot . CALL_PATTERN is the pattern of the new call .


<s> void add_all_one_mask_operand ( machine_mode mode ) { add_input_operand ( CONSTM1_RTX ( mode ) , mode ) ; } </s>

Since we may normalize vop/vop_tu/vop_m/vop_tumu .. into a single patter . We add a fake all true mask for the intrinsics that do n't need a real mask .


<s> const char * mprocTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { } </s>

getTargetNodeName - This method returns the name of a target specific


<s>
StringRef
getPassName
(
)
const
override
{
return
"Mips Branch Expansion Pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> rtx avr_libcall_value ( enum machine_mode mode ) { int offs = GET_MODE_SIZE ( mode ) ; if ( offs < 2 ) offs = 2 ; return gen_rtx_REG ( mode , RET_REGISTER + 2 - offs ) ; } </s>

Ceate an RTX representing the place where a library function returns a value of mode MODE .


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot ) { if ( ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAnyX86InstComments ( MI , * CommentStream , getRegisterName ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> unsigned AMDGPURegisterBankInfo :: copyCost ( const RegisterBank & Dst , const RegisterBank & Src , unsigned Size ) const { if ( Dst . getID ( ) == AMDGPU :: SGPRRegBankID && Src . getID ( ) == AMDGPU :: VGPRRegBankID ) { return std :: numeric_limits < unsigned > :: max ( ) ; } if ( Size == 1 && Dst . getID ( ) == AMDGPU :: SCCRegBankID && ( Src . getID ( ) == AMDGPU :: SGPRRegBankID || Src . getID ( ) == AMDGPU :: VGPRRegBankID || Src . getID ( ) == AMDGPU :: VCCRegBankID ) ) return std :: numeric_limits < unsigned > :: max ( ) ; return RegisterBankInfo :: copyCost ( Dst , Src , Size ) ; } </s>

Get the cost of a copy from B to A , or put differently , get the cost of A = COPY B .

AMDGPU AMDGPU AMDGPU::SGPRRegBankID AMDGPU::VGPRRegBankID 1 AMDGPU::SCCRegBankID AMDGPU::SGPRRegBankID AMDGPU::VGPRRegBankID AMDGPU::VCCRegBankID


<s> std :: pair < const TargetRegisterClass * , uint8_t > HexagonTargetLowering :: findRepresentativeClass ( const TargetRegisterInfo * TRI , MVT VT ) const { const TargetRegisterClass * RRC = nullptr ; uint8_t Cost = 1 ; switch ( VT . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( TRI , VT ) ; case MVT :: v64i8 : case MVT :: v32i16 : case MVT :: v16i32 : case MVT :: v8i64 : RRC = & Hexagon :: HvxVRRegClass ; break ; case MVT :: v128i8 : case MVT :: v64i16 : case MVT :: v32i32 : case MVT :: v16i64 : if ( Subtarget . hasV60TOps ( ) && Subtarget . useHVXOps ( ) && Subtarget . useHVXDblOps ( ) ) RRC = & Hexagon :: HvxVRRegClass ; else RRC = & Hexagon :: HvxWRRegClass ; break ; case MVT :: v256i8 : case MVT :: v128i16 : case MVT :: v64i32 : case MVT :: v32i64 : RRC = & Hexagon :: HvxWRRegClass ; break ; } return std :: make_pair ( RRC , Cost ) ; } </s>

Return the largest legal super-reg register class of the register class for the specified type and its associated `` cost '' .


<s>
void
scalar_chain
::
add_insn
(
bitmap
candidates
,
unsigned
int
insn_uid
)
{
if
(
bitmap_bit_p
(
insns
,
insn_uid
)
)
return
;
if
(
dump_file
)
fprintf
(
dump_file
,
"  Adding insn %d to chain #%d\n"
,
insn_uid
,
chain_id
)
;
bitmap_set_bit
(
insns
,
insn_uid
)
;
rtx_insn
*
insn
=
DF_INSN_UID_GET
(
insn_uid
)
->
insn
;
rtx
def_set
=
single_set
(
insn
)
;
if
(
def_set
&&
REG_P
(
SET_DEST
(
def_set
)
)
&&
!
HARD_REGISTER_P
(
SET_DEST
(
def_set
)
)
)
bitmap_set_bit
(
defs
,
REGNO
(
SET_DEST
(
def_set
)
)
)
;
df_ref
ref
;
df_ref
def
;
for
(
ref
=
DF_INSN_UID_DEFS
(
insn_uid
)
;
ref
;
ref
=
DF_REF_NEXT_LOC
(
ref
)
)
if
(
!
HARD_REGISTER_P
(
DF_REF_REG
(
ref
)
)
)
for
(
def
=
DF_REG_DEF_CHAIN
(
DF_REF_REGNO
(
ref
)
)
;
def
;
def
=
DF_REF_NEXT_REG
(
def
)
)
analyze_register_chain
(
candidates
,
def
)
;
for
(
ref
=
DF_INSN_UID_USES
(
insn_uid
)
;
ref
;
ref
=
DF_REF_NEXT_LOC
(
ref
)
)
if
(
!
DF_REF_REG_MEM_P
(
ref
)
)
analyze_register_chain
(
candidates
,
ref
)
;
}
</s>

Add instruction into a chain . Return true if OK , false if the search was aborted .


<s> ATTRIBUTE_UNUSED static section * ia64_hpux_function_section ( tree decl ATTRIBUTE_UNUSED , enum node_frequency freq ATTRIBUTE_UNUSED , bool startup ATTRIBUTE_UNUSED , bool exit ATTRIBUTE_UNUSED ) { return NULL ; } </s>

Always default to .text section until HP-UX linker is fixed .


<s> void init ( VLIWMachineScheduler * dag , const TargetSchedModel * smodel ) { DAG = dag ; SchedModel = smodel ; CurrCycle = 0 ; IssueCount = 0 ; CriticalPathLength = DAG -> getBBSize ( ) / SchedModel -> getIssueWidth ( ) ; if ( DAG -> getBBSize ( ) < 50 ) CriticalPathLength >>= 1 ; else { unsigned MaxPath = 0 ; for ( auto & SU : DAG -> SUnits ) MaxPath = std :: max ( MaxPath , isTop ( ) ? SU . getHeight ( ) : SU . getDepth ( ) ) ; CriticalPathLength = std :: max ( CriticalPathLength , MaxPath ) + 1 ; } } </s>

Initialize the machine model for instruction scheduling .


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> SparcTargetLowering :: ConstraintType SparcTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'r' : return C_RegisterClass ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s>
bool
AVRFrameLowering
::
restoreCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
if
(
CSI
.
empty
(
)
)
{
return
false
;
}
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
AVRSubtarget
&
STI
=
MF
.
getSubtarget
<
AVRSubtarget
>
(
)
;
const
TargetInstrInfo
&
TII
=
*
STI
.
getInstrInfo
(
)
;
for
(
const
CalleeSavedInfo
&
CCSI
:
CSI
)
{
unsigned
Reg
=
CCSI
.
getReg
(
)
;
assert
(
TRI
->
getRegSizeInBits
(
*
TRI
->
getMinimalPhysRegClass
(
Reg
)
)
==
8
&&
"Invalid register size"
)
;
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
POPRd
)
,
Reg
)
;
}
return
true
;
}
</s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .

AVR
AVR
AVR
AVR
8
"Invalid register size"
AVR::POPRd


<s> static void pop ( int rn ) { rtx x ; if ( rn == FPUL_REG ) x = gen_pop_fpul ( ) ; else if ( rn == FPSCR_REG ) x = gen_pop_fpscr ( ) ; else if ( ( TARGET_SH4 || TARGET_SH2A_DOUBLE ) && TARGET_FMOVD && ! TARGET_FPU_SINGLE && FP_OR_XD_REGISTER_P ( rn ) ) { if ( FP_REGISTER_P ( rn ) && ( rn - FIRST_FP_REG ) & 1 ) return ; x = gen_pop_4 ( gen_rtx_REG ( DFmode , rn ) ) ; } else if ( TARGET_SH2E && FP_REGISTER_P ( rn ) ) x = gen_pop_e ( gen_rtx_REG ( SFmode , rn ) ) ; else x = gen_pop ( gen_rtx_REG ( SImode , rn ) ) ; x = emit_insn ( x ) ; REG_NOTES ( x ) = gen_rtx_EXPR_LIST ( REG_INC , gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) , 0 ) ; } </s>

Output RTL to pop register RN from the stack .


<s>
bool
SparcAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Operands
.
push_back
(
SparcOperand
::
CreateToken
(
Name
,
NameLoc
)
)
;
applyMnemonicAliases
(
Name
,
getAvailableFeatures
(
)
,
0
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
if
(
parseBranchModifiers
(
Operands
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
}
if
(
parseOperand
(
Operands
,
Name
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Sparc
Sparc
SparcOperand::CreateToken
0
"unexpected token"
"unexpected token"
"unexpected token"
"unexpected token"


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s>
MachineInstr
*
ARMBaseInstrInfo
::
optimizeSelect
(
MachineInstr
*
MI
,
bool
PreferFalse
)
const
{
assert
(
(
MI
->
getOpcode
(
)
==
ARM
::
MOVCCr
||
MI
->
getOpcode
(
)
==
ARM
::
t2MOVCCr
)
&&
"Unknown select instruction"
)
;
MachineRegisterInfo
&
MRI
=
MI
->
getParent
(
)
->
getParent
(
)
->
getRegInfo
(
)
;
MachineInstr
*
DefMI
=
canFoldIntoMOVCC
(
MI
->
getOperand
(
2
)
.
getReg
(
)
,
MRI
,
this
)
;
bool
Invert
=
!
DefMI
;
if
(
!
DefMI
)
DefMI
=
canFoldIntoMOVCC
(
MI
->
getOperand
(
1
)
.
getReg
(
)
,
MRI
,
this
)
;
if
(
!
DefMI
)
return
0
;
MachineOperand
FalseReg
=
MI
->
getOperand
(
Invert
2
:
1
)
;
unsigned
DestReg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
const
TargetRegisterClass
*
PreviousClass
=
MRI
.
getRegClass
(
FalseReg
.
getReg
(
)
)
;
if
(
!
MRI
.
constrainRegClass
(
DestReg
,
PreviousClass
)
)
return
0
;
MachineInstrBuilder
NewMI
=
BuildMI
(
*
MI
->
getParent
(
)
,
MI
,
MI
->
getDebugLoc
(
)
,
DefMI
->
getDesc
(
)
,
DestReg
)
;
const
MCInstrDesc
&
DefDesc
=
DefMI
->
getDesc
(
)
;
for
(
unsigned
i
=
1
,
e
=
DefDesc
.
getNumOperands
(
)
;
i
!=
e
&&
!
DefDesc
.
OpInfo
[
i
]
.
isPredicate
(
)
;
++
i
)
NewMI
.
addOperand
(
DefMI
->
getOperand
(
i
)
)
;
unsigned
CondCode
=
MI
->
getOperand
(
3
)
.
getImm
(
)
;
if
(
Invert
)
NewMI
.
addImm
(
ARMCC
::
getOppositeCondition
(
ARMCC
::
CondCodes
(
CondCode
)
)
)
;
else
NewMI
.
addImm
(
CondCode
)
;
NewMI
.
addOperand
(
MI
->
getOperand
(
4
)
)
;
if
(
NewMI
->
hasOptionalDef
(
)
)
AddDefaultCC
(
NewMI
)
;
FalseReg
.
setImplicit
(
)
;
NewMI
.
addOperand
(
FalseReg
)
;
NewMI
->
tieOperands
(
0
,
NewMI
->
getNumOperands
(
)
1
)
;
DefMI
->
eraseFromParent
(
)
;
return
NewMI
;
}
</s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { TM = static_cast < const PPCTargetMachine * > ( & MF . getTarget ( ) ) ; TII = TM -> getSubtargetImpl ( ) -> getInstrInfo ( ) ; bool Changed = false ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed = true ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> static SparcOperand * CreateReg ( unsigned RegNum , unsigned Kind , SMLoc S , SMLoc E ) { SparcOperand * Op = new SparcOperand ( k_Register ) ; Op -> Reg . RegNum = RegNum ; Op -> Reg . Kind = ( SparcOperand :: RegisterKind ) Kind ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .

Sparc Sparc Sparc Sparc SparcOperand::RegisterKind


<s> void RISCVTargetStreamer :: emitTargetAttributes ( const MCSubtargetInfo & STI ) { if ( STI . hasFeature ( RISCV :: FeatureRV32E ) ) emitAttribute ( RISCVAttrs :: STACK_ALIGN , RISCVAttrs :: ALIGN_4 ) ; else emitAttribute ( RISCVAttrs :: STACK_ALIGN , RISCVAttrs :: ALIGN_16 ) ; std :: string Arch = "rv32" ; if ( STI . hasFeature ( RISCV :: Feature64Bit ) ) Arch = "rv64" ; if ( STI . hasFeature ( RISCV :: FeatureRV32E ) ) Arch += "e1p9" ; else Arch += "i2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtM ) ) Arch += "_m2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtA ) ) Arch += "_a2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtF ) ) Arch += "_f2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtD ) ) Arch += "_d2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtC ) ) Arch += "_c2p0" ; emitTextAttribute ( RISCVAttrs :: ARCH , Arch ) ; } </s>

Emit the build attributes that only depend on the hardware that we expect .


"Code generation for MIPS-I is not implemented"

"Code generation for MIPS-V is not implemented"

"MSA requires a 64-bit FPU register file (FR=1 mode). "

"-mattr=+nooddspreg requires the O32 ABI."

"FPXX is not permitted for the N32/N64 ABI's."

"position-independent code requires '-mabicalls'"

"warning: cannot use small-data accesses for '-mabicalls'"

This constructor initializes the data members to match that of the specified triple .


"not generating patch area, nops not supported"


<s>
void
dump
(
)
{
dbgs
(
)
<<
"X86ISelAddressMode "
<<
this
<<
'\n'
;
dbgs
(
)
<<
"Base.Reg "
;
if
(
Base
.
Reg
.
getNode
(
)
!=
0
)
Base
.
Reg
.
getNode
(
)
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" Base.FrameIndex "
<<
Base
.
FrameIndex
<<
'\n'
<<
" Scale"
<<
Scale
<<
'\n'
<<
"IndexReg "
;
if
(
IndexReg
.
getNode
(
)
!=
0
)
IndexReg
.
getNode
(
)
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" Disp "
<<
Disp
<<
'\n'
<<
"GV "
;
if
(
GV
)
GV
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" CP "
;
if
(
CP
)
CP
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
'\n'
<<
"ES "
;
if
(
ES
)
dbgs
(
)
<<
ES
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" JT"
<<
JT
<<
" Align"
<<
Align
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

X86
"X86ISelAddressMode "
"Base.Reg "
0
"nul"
" Base.FrameIndex "
" Scale"
"IndexReg "
0
"nul"
" Disp "
"GV "
"nul"
" CP "
"nul"
"ES "
"nul"
" JT"
" Align"


<s> bool TeakTargetLowering :: isLegalAddImmediate ( int64_t Imm ) const { return Imm >= - 32768 && Imm <= 32767 ; } </s>

Return true if the specified immediate is legal add immediate , that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register .


<s> static void mimic_memory_attributes_and_flags ( rtx new_mem_exp , const_rtx original_mem_exp ) { RTX_FLAG ( new_mem_exp , jump ) = RTX_FLAG ( original_mem_exp , jump ) ; RTX_FLAG ( new_mem_exp , call ) = RTX_FLAG ( original_mem_exp , call ) ; RTX_FLAG ( new_mem_exp , unchanging ) = RTX_FLAG ( original_mem_exp , unchanging ) ; RTX_FLAG ( new_mem_exp , volatil ) = RTX_FLAG ( original_mem_exp , volatil ) ; RTX_FLAG ( new_mem_exp , frame_related ) = RTX_FLAG ( original_mem_exp , frame_related ) ; RTX_FLAG ( new_mem_exp , in_struct ) = RTX_FLAG ( original_mem_exp , in_struct ) ; RTX_FLAG ( new_mem_exp , return_val ) = RTX_FLAG ( original_mem_exp , return_val ) ; struct mem_attrs original_attrs = * get_mem_attrs ( original_mem_exp ) ; alias_set_type set = original_attrs . alias ; set_mem_alias_set ( new_mem_exp , set ) ; addr_space_t addrspace = original_attrs . addrspace ; set_mem_addr_space ( new_mem_exp , addrspace ) ; unsigned int align = original_attrs . align ; set_mem_align ( new_mem_exp , align ) ; tree expr = original_attrs . expr ; set_mem_expr ( new_mem_exp , expr ) ; if ( original_attrs . offset_known_p ) { HOST_WIDE_INT offset = original_attrs . offset ; set_mem_offset ( new_mem_exp , offset ) ; } else clear_mem_offset ( new_mem_exp ) ; if ( original_attrs . size_known_p ) { HOST_WIDE_INT size = original_attrs . size ; set_mem_size ( new_mem_exp , size ) ; } else clear_mem_size ( new_mem_exp ) ; } </s>

Make NEW_MEM_EXP 's attributes and flags resemble those of ORIGINAL_MEM_EXP .


"r%d has non convertible definition in insn %d\n"

"Removing insn %d from candidates list\n"

For a given bitmap of insn UIDs scans all instruction and remove insn from CANDIDATES in case it has both convertible and not convertible definitions . All insns in a bitmap are conversion candidates according to scalar_to_vector_candidate_p . Currently it implies all insns are single_set .


<s> MSP430Subtarget & MSP430Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { ExtendedInsts = false ; HWMultMode = NoHWMult ; StringRef CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "msp430" ; ParseSubtargetFeatures ( CPUName , CPUName , FS ) ; if ( HWMultModeOption != NoHWMult ) HWMultMode = HWMultModeOption ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> const TargetRegisterClass * SIRegisterInfo :: getCFGStructurizerRegClass ( MVT VT ) const { switch ( VT . SimpleTy ) { default : case MVT :: i32 : return & AMDGPU :: VGPR_32RegClass ; } } </s>

get the register class of the specified type to use in the CFGStructurizer


<s>
bool
MCS51FrameLowering
::
restoreCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
MutableArrayRef
<
CalleeSavedInfo
>
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
if
(
CSI
.
empty
(
)
)
{
return
false
;
}
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
MCS51Subtarget
&
STI
=
MF
.
getSubtarget
<
MCS51Subtarget
>
(
)
;
const
TargetInstrInfo
&
TII
=
*
STI
.
getInstrInfo
(
)
;
for
(
const
CalleeSavedInfo
&
CCSI
:
CSI
)
{
unsigned
Reg
=
CCSI
.
getReg
(
)
;
assert
(
TRI
->
getRegSizeInBits
(
*
TRI
->
getMinimalPhysRegClass
(
Reg
)
)
==
8
&&
"Invalid register size"
)
;
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
MCS51
::
POPRd
)
,
Reg
)
;
}
return
true
;
}
</s>


<s>
void
h8300_init_once
(
)
{
static
const
char
*
const
h8_push_ops
[
2
]
=
{
"push"
,
"push.l"
}
;
static
const
char
*
const
h8_pop_ops
[
2
]
=
{
"pop"
,
"pop.l"
}
;
static
const
char
*
const
h8_mov_ops
[
2
]
=
{
"mov.w"
,
"mov.l"
}
;
if
(
TARGET_H8300
)
{
cpu_type
=
(
int
)
CPU_H8300
;
h8_reg_names
=
names_big
;
}
else
{
cpu_type
=
(
int
)
CPU_H8300H
;
h8_reg_names
=
names_extended
;
}
h8_push_op
=
h8_push_ops
[
cpu_type
]
;
h8_pop_op
=
h8_pop_ops
[
cpu_type
]
;
h8_mov_op
=
h8_mov_ops
[
cpu_type
]
;
if
(
!
TARGET_H8300S
&&
TARGET_MAC
)
{
error
(
"-ms2600 is used without -ms"
)
;
target_flags
|=
1
;
}
}
</s>

Initialize various cpu specific globals at start up .


" was Pass-through, is now Dirty-out.\n"


<s> Z80oldSubtarget & Z80oldSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { ParseSubtargetFeatures ( CPU , FS ) ; HasIdxHalfRegs = HasUndocOps ; return * this ; } </s>


<s>
unsigned
ARMMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
)
const
{
if
(
MO
.
isReg
(
)
)
{
unsigned
Reg
=
MO
.
getReg
(
)
;
unsigned
RegNo
=
getARMRegisterNumbering
(
Reg
)
;
switch
(
Reg
)
{
default
:
return
RegNo
;
case
ARM
::
Q0
:
case
ARM
::
Q1
:
case
ARM
::
Q2
:
case
ARM
::
Q3
:
case
ARM
::
Q4
:
case
ARM
::
Q5
:
case
ARM
::
Q6
:
case
ARM
::
Q7
:
case
ARM
::
Q8
:
case
ARM
::
Q9
:
case
ARM
::
Q10
:
case
ARM
::
Q11
:
case
ARM
::
Q12
:
case
ARM
::
Q13
:
case
ARM
::
Q14
:
case
ARM
::
Q15
:
return
2
*
RegNo
;
}
}
else
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
else
if
(
MO
.
isFPImm
(
)
)
{
return
static_cast
<
unsigned
>
(
APFloat
(
MO
.
getFPImm
(
)
)
.
bitcastToAPInt
(
)
.
getHiBits
(
32
)
.
getLimitedValue
(
)
)
;
}
llvm_unreachable
(
"Unable to encode MCOperand!"
)
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s>
void
c4x_init_cumulative_args
(
CUMULATIVE_ARGS
*
cum
,
tree
fntype
,
rtx
libname
)
{
tree
param
,
next_param
;
cum
->
floats
=
cum
->
ints
=
0
;
cum
->
init
=
0
;
cum
->
var
=
0
;
cum
->
args
=
0
;
if
(
TARGET_DEBUG
)
{
fprintf
(
stderr
,
"\nc4x_init_cumulative_args ("
)
;
if
(
fntype
)
{
tree
ret_type
=
TREE_TYPE
(
fntype
)
;
fprintf
(
stderr
,
"fntype code = %s, ret code = %s"
,
tree_code_name
[
(
int
)
TREE_CODE
(
fntype
)
]
,
tree_code_name
[
(
int
)
TREE_CODE
(
ret_type
)
]
)
;
}
else
fprintf
(
stderr
,
"no fntype"
)
;
if
(
libname
)
fprintf
(
stderr
,
", libname = %s"
,
XSTR
(
libname
,
0
)
)
;
}
cum
->
prototype
=
(
fntype
&&
TYPE_ARG_TYPES
(
fntype
)
)
;
for
(
param
=
fntype
TYPE_ARG_TYPES
(
fntype
)
:
0
;
param
;
param
=
next_param
)
{
tree
type
;
next_param
=
TREE_CHAIN
(
param
)
;
type
=
TREE_VALUE
(
param
)
;
if
(
type
&&
type
!=
void_type_node
)
{
enum
machine_mode
mode
;
if
(
!
next_param
)
cum
->
var
=
1
;
if
(
(
mode
=
TYPE_MODE
(
type
)
)
)
{
if
(
!
targetm
.
calls
.
must_pass_in_stack
(
mode
,
type
)
)
{
if
(
mode
==
QFmode
||
mode
==
HFmode
)
cum
->
floats
++
;
else
if
(
mode
==
QImode
||
mode
==
Pmode
)
cum
->
ints
++
;
}
}
cum
->
args
++
;
}
}
if
(
TARGET_DEBUG
)
fprintf
(
stderr
,
"%s%s, args = %d)\n"
,
cum
->
prototype
", prototype"
:
""
,
cum
->
var
", variable args"
:
""
,
cum
->
args
)
;
}
</s>

Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is 0 .


<s> static int nds32_register_move_cost ( machine_mode mode , reg_class_t from , reg_class_t to ) { if ( TARGET_PIPELINE_GRAYWOLF ) { if ( GET_MODE_SIZE ( mode ) == 8 ) { if ( from == FP_REGS && to != FP_REGS ) return 3 ; if ( from != FP_REGS && to == FP_REGS ) return 2 ; } else { if ( ( from == FP_REGS && to != FP_REGS ) || ( from != FP_REGS && to == FP_REGS ) ) return 2 ; } } if ( ( from == FP_REGS && to != FP_REGS ) || ( from != FP_REGS && to == FP_REGS ) ) return 3 ; else if ( from == HIGH_REGS || to == HIGH_REGS ) return optimize_size ? 6 : 2 ; else return 2 ; } </s>

Describing Relative Costs of Operations .


<s> void MipsTargetELFStreamer :: finish ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; const MCObjectFileInfo & OFI = * MCA . getContext ( ) . getObjectFileInfo ( ) ; MCSection & TextSection = * OFI . getTextSection ( ) ; MCA . registerSection ( TextSection ) ; MCSection & DataSection = * OFI . getDataSection ( ) ; MCA . registerSection ( DataSection ) ; MCSection & BSSSection = * OFI . getBSSSection ( ) ; MCA . registerSection ( BSSSection ) ; TextSection . setAlignment ( Align ( std :: max ( 16u , TextSection . getAlignment ( ) ) ) ) ; DataSection . setAlignment ( Align ( std :: max ( 16u , DataSection . getAlignment ( ) ) ) ) ; BSSSection . setAlignment ( Align ( std :: max ( 16u , BSSSection . getAlignment ( ) ) ) ) ; if ( RoundSectionSizes ) { MCStreamer & OS = getStreamer ( ) ; for ( MCSection & S : MCA ) { MCSectionELF & Section = static_cast < MCSectionELF & > ( S ) ; unsigned Alignment = Section . getAlignment ( ) ; if ( Alignment ) { OS . SwitchSection ( & Section ) ; if ( Section . UseCodeAlign ( ) ) OS . emitCodeAlignment ( Alignment , & STI , Alignment ) ; else OS . emitValueToAlignment ( Alignment , 0 , 1 , Alignment ) ; } } } const FeatureBitset & Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI_O32 ; else if ( getABI ( ) . IsN32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI2 ; if ( Features [ Mips :: FeatureGP64Bit ] ) { if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_32BITMODE ; } else if ( Features [ Mips :: FeatureMips64r2 ] || Features [ Mips :: FeatureMips64 ] ) EFlags |= ELF :: EF_MIPS_32BITMODE ; if ( ! Features [ Mips :: FeatureNoABICalls ] ) EFlags |= ELF :: EF_MIPS_CPIC ; if ( Pic ) EFlags |= ELF :: EF_MIPS_PIC | ELF :: EF_MIPS_CPIC ; MCA . setELFHeaderEFlags ( EFlags ) ; MipsELFStreamer & MEF = static_cast < MipsELFStreamer & > ( Streamer ) ; MEF . EmitMipsOptionRecords ( ) ; emitMipsAbiFlags ( ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> static MCAsmInfo * createMCAsmInfo ( const MCRegisterInfo & , const Triple & TT ) { return new WebAssemblyMCAsmInfo ( TT ) ; } </s>

createMCAsmInfo - Create a MCAsmInfo implementation for the specified target triple .


<s> void AAPAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; AAPMCInstLower MCInstLowering ( OutContext , * this ) ; MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


"WebAssembly hasn't implemented computed gotos"

"WebAssembly hasn't implemented __builtin_return_address"

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool isProfitableToIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , unsigned ExtraPredCycles , BranchProbability Probability ) const override { return true ; } </s>


<s> SDValue R600TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; SmallVector < ISD :: InputArg , 8 > LocalIns ; if ( AMDGPU :: isShader ( CallConv ) ) { CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForCall ( CallConv , isVarArg ) ) ; } else { analyzeFormalArgumentsCompute ( CCInfo , Ins ) ; } for ( unsigned i = 0 , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const ISD :: InputArg & In = Ins [ i ] ; EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector ( ) ) { MemVT = MemVT . getVectorElementType ( ) ; } if ( AMDGPU :: isShader ( CallConv ) ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & R600 :: R600_Reg128RegClass ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , AMDGPUAS :: PARAM_I_ADDRESS ) ; ISD :: LoadExtType Ext = ISD :: NON_EXTLOAD ; if ( MemVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) { Ext = ISD :: SEXTLOAD ; } unsigned ValBase = ArgLocs [ In . getOrigArgIndex ( ) ] . getLocMemOffset ( ) ; unsigned PartOffset = VA . getLocMemOffset ( ) ; unsigned Alignment = MinAlign ( VT . getStoreSize ( ) , PartOffset ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) , PartOffset - ValBase ) ; SDValue Arg = DAG . getLoad ( ISD :: UNINDEXED , Ext , VT , DL , Chain , DAG . getConstant ( PartOffset , DL , MVT :: i32 ) , DAG . getUNDEF ( MVT :: i32 ) , PtrInfo , MemVT , Alignment , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; InVals . push_back ( Arg ) ; } return Chain ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool X86PassConfig :: addPreRegAlloc ( ) { PM . add ( createX86MaxStackAlignmentHeuristicPass ( ) ) ; return false ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> bool rs6000_emit_set_const ( rtx dest , rtx source ) { machine_mode mode = GET_MODE ( dest ) ; rtx temp , set ; rtx_insn * insn ; HOST_WIDE_INT c ; gcc_checking_assert ( CONST_INT_P ( source ) ) ; c = INTVAL ( source ) ; switch ( mode ) { case E_QImode : case E_HImode : emit_insn ( gen_rtx_SET ( dest , source ) ) ; return true ; case E_SImode : temp = ! can_create_pseudo_p ( ) ? dest : gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( temp , GEN_INT ( c & ~ ( HOST_WIDE_INT ) 0xffff ) ) ) ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_IOR ( SImode , temp , GEN_INT ( c & 0xffff ) ) ) ) ; break ; case E_DImode : if ( ! TARGET_POWERPC64 ) { rtx hi , lo ; hi = operand_subword_force ( dest , WORDS_BIG_ENDIAN == 0 , DImode ) ; lo = operand_subword_force ( dest , WORDS_BIG_ENDIAN != 0 , DImode ) ; emit_move_insn ( hi , GEN_INT ( c >> 32 ) ) ; c = sext_hwi ( c , 32 ) ; emit_move_insn ( lo , GEN_INT ( c ) ) ; } else rs6000_emit_set_long_const ( dest , c ) ; break ; default : gcc_unreachable ( ) ; } insn = get_last_insn ( ) ; set = single_set ( insn ) ; if ( ! CONSTANT_P ( SET_SRC ( set ) ) ) set_unique_reg_note ( insn , REG_EQUAL , GEN_INT ( c ) ) ; return true ; } </s>

Try to output insns to set TARGET equal to the constant C if it can be done in less than N insns . Do all computations in MODE . Returns the place where the output has been placed if it can be done and the insns have been emitted . If it would take more than N insns , zero is returned and no insns and emitted .


<s>
SDValue
VETargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
ATOMIC_FENCE
:
return
lowerATOMIC_FENCE
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
lowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
lowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
lowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
lowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
lowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
LOAD
:
return
lowerLOAD
(
Op
,
DAG
)
;
case
ISD
::
STORE
:
return
lowerSTORE
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
lowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
VAARG
:
return
lowerVAARG
(
Op
,
DAG
)
;
}
}
</s>

VE
VE
"Should not custom lower this!"
ISD::ATOMIC_FENCE
ISD::BlockAddress
ISD::ConstantPool
ISD::DYNAMIC_STACKALLOC
ISD::GlobalAddress
ISD::GlobalTLSAddress
ISD::LOAD
ISD::STORE
ISD::VASTART
ISD::VAARG


<s> bool sh_symbian_dllimport_name_p ( const char * symbol ) { return strncmp ( DLL_IMPORT_PREFIX , symbol , strlen ( DLL_IMPORT_PREFIX ) ) == 0 ; } </s>

Return nonzero if SYMBOL is marked as being dllimport 'd .


<s> bool SystemZAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { const MCRegisterInfo & MRI = * TM . getMCRegisterInfo ( ) ; const MachineOperand & MO = MI -> getOperand ( OpNo ) ; MCOperand MCOp ; if ( ExtraCode ) { if ( ExtraCode [ 0 ] == 'N' && ! ExtraCode [ 1 ] && MO . isReg ( ) && SystemZ :: GR128BitRegClass . contains ( MO . getReg ( ) ) ) MCOp = MCOperand :: createReg ( MRI . getSubReg ( MO . getReg ( ) , SystemZ :: subreg_l64 ) ) ; else return AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , OS ) ; } else { SystemZMCInstLower Lower ( MF -> getContext ( ) , * this ) ; MCOp = Lower . lowerOperand ( MO ) ; } SystemZInstPrinter :: printOperand ( MCOp , MAI , OS ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


"expected an argument to %<msp430_select_cpu%>"

This spec function is called if the user has provided an -mmcu option without an -mcpu option . It will place the correct -mcpu option for the given -mmcu onto the command line , to ensure the correct ISA multilib is selected .


<s>
unsigned
ARMBaseInstrInfo
::
getNumMicroOps
(
const
InstrItineraryData
*
ItinData
,
const
MachineInstr
*
MI
)
const
{
if
(
!
ItinData
||
ItinData
->
isEmpty
(
)
)
return
1
;
const
MCInstrDesc
&
Desc
=
MI
->
getDesc
(
)
;
unsigned
Class
=
Desc
.
getSchedClass
(
)
;
int
ItinUOps
=
ItinData
->
getNumMicroOps
(
Class
)
;
if
(
ItinUOps
>=
0
)
return
ItinUOps
;
unsigned
Opc
=
MI
->
getOpcode
(
)
;
switch
(
Opc
)
{
default
:
llvm_unreachable
(
"Unexpected multi-uops instruction!"
)
;
case
ARM
::
VLDMQIA
:
case
ARM
::
VSTMQIA
:
return
2
;
case
ARM
::
VLDMDIA
:
case
ARM
::
VLDMDIA_UPD
:
case
ARM
::
VLDMDDB_UPD
:
case
ARM
::
VLDMSIA
:
case
ARM
::
VLDMSIA_UPD
:
case
ARM
::
VLDMSDB_UPD
:
case
ARM
::
VSTMDIA
:
case
ARM
::
VSTMDIA_UPD
:
case
ARM
::
VSTMDDB_UPD
:
case
ARM
::
VSTMSIA
:
case
ARM
::
VSTMSIA_UPD
:
case
ARM
::
VSTMSDB_UPD
:
{
unsigned
NumRegs
=
MI
->
getNumOperands
(
)
Desc
.
getNumOperands
(
)
;
return
(
NumRegs
/
2
)
+
(
NumRegs
%
2
)
+
1
;
}
case
ARM
::
LDMIA_RET
:
case
ARM
::
LDMIA
:
case
ARM
::
LDMDA
:
case
ARM
::
LDMDB
:
case
ARM
::
LDMIB
:
case
ARM
::
LDMIA_UPD
:
case
ARM
::
LDMDA_UPD
:
case
ARM
::
LDMDB_UPD
:
case
ARM
::
LDMIB_UPD
:
case
ARM
::
STMIA
:
case
ARM
::
STMDA
:
case
ARM
::
STMDB
:
case
ARM
::
STMIB
:
case
ARM
::
STMIA_UPD
:
case
ARM
::
STMDA_UPD
:
case
ARM
::
STMDB_UPD
:
case
ARM
::
STMIB_UPD
:
case
ARM
::
tLDMIA
:
case
ARM
::
tLDMIA_UPD
:
case
ARM
::
tSTMIA_UPD
:
case
ARM
::
tPOP_RET
:
case
ARM
::
tPOP
:
case
ARM
::
tPUSH
:
case
ARM
::
t2LDMIA_RET
:
case
ARM
::
t2LDMIA
:
case
ARM
::
t2LDMDB
:
case
ARM
::
t2LDMIA_UPD
:
case
ARM
::
t2LDMDB_UPD
:
case
ARM
::
t2STMIA
:
case
ARM
::
t2STMDB
:
case
ARM
::
t2STMIA_UPD
:
case
ARM
::
t2STMDB_UPD
:
{
unsigned
NumRegs
=
MI
->
getNumOperands
(
)
Desc
.
getNumOperands
(
)
+
1
;
if
(
Subtarget
.
isCortexA8
(
)
)
{
if
(
NumRegs
<
4
)
return
2
;
int
A8UOps
=
(
NumRegs
/
2
)
;
if
(
NumRegs
%
2
)
++
A8UOps
;
return
A8UOps
;
}
else
if
(
Subtarget
.
isCortexA9
(
)
)
{
int
A9UOps
=
(
NumRegs
/
2
)
;
if
(
(
NumRegs
%
2
)
||
!
MI
->
hasOneMemOperand
(
)
||
(
*
MI
->
memoperands_begin
(
)
)
->
getAlignment
(
)
<
8
)
++
A9UOps
;
return
A9UOps
;
}
else
{
return
NumRegs
;
}
}
}
}
</s>

Return the number of issue slots required for this MI .


<s> bool contains ( MachineInstr & MI ) { return Insts . count ( & MI ) > 0 ; } </s>

contains - Returns true if this trace contains the given basic block .


<s> static rtx mips_legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , machine_mode mode ) { rtx base , addr ; HOST_WIDE_INT offset ; if ( mips_tls_symbol_p ( x ) ) return mips_legitimize_tls_address ( x ) ; if ( mips_split_symbol ( NULL , x , mode , & addr ) ) return mips_force_address ( addr , mode ) ; mips_split_plus ( x , & base , & offset ) ; if ( offset != 0 ) { if ( ! mips_valid_base_register_p ( base , mode , false ) ) base = copy_to_mode_reg ( Pmode , base ) ; addr = mips_add_offset ( NULL , base , offset ) ; return mips_force_address ( addr , mode ) ; } return x ; } </s>

This function is used to implement LEGITIMIZE_ADDRESS . If * XLOC can be legitimized in a way that the generic machinery might not expect , put the new address in * XLOC and return true . MODE is the mode of the memory being accessed .


<s> void RISCVFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; Align StackAlign = getStackAlign ( ) ; uint64_t MaxCallSize = alignTo ( MFI . getMaxCallFrameSize ( ) , StackAlign ) ; MFI . setMaxCallFrameSize ( MaxCallSize ) ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI . setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s> EVT MBlazeTargetLowering :: getSetCCResultType ( EVT VT ) const { return MVT :: i32 ; } </s>

Return the value type to use for ISD : :SETCC .


<s> void X86AsmParser :: EmitInstruction ( MCInst & Inst , SmallVectorImpl < MCParsedAsmOperand * > & Operands , MCStreamer & Out ) { Instrumentation -> InstrumentInstruction ( Inst , Operands , getContext ( ) , MII , Out ) ; Out . EmitInstruction ( Inst , STI ) ; } </s>


<s> static void emit_predicate_relation_info ( ) { int i ; for ( i = n_basic_blocks - 1 ; i >= 0 ; -- i ) { basic_block bb = BASIC_BLOCK ( i ) ; int r ; rtx head = bb -> head ; if ( GET_CODE ( head ) != CODE_LABEL ) continue ; if ( GET_CODE ( NEXT_INSN ( head ) ) == NOTE && NOTE_LINE_NUMBER ( NEXT_INSN ( head ) ) == NOTE_INSN_BASIC_BLOCK ) head = NEXT_INSN ( head ) ; for ( r = PR_REG ( 0 ) ; r < PR_REG ( 64 ) ; r += 2 ) if ( REGNO_REG_SET_P ( bb -> global_live_at_start , r ) ) { rtx p = gen_rtx_REG ( BImode , r ) ; rtx n = emit_insn_after ( gen_pred_rel_mutex ( p ) , head ) ; if ( head == bb -> end ) bb -> end = n ; head = n ; } } for ( i = n_basic_blocks - 1 ; i >= 0 ; -- i ) { basic_block bb = BASIC_BLOCK ( i ) ; rtx insn = bb -> head ; while ( 1 ) { if ( GET_CODE ( insn ) == CALL_INSN && GET_CODE ( PATTERN ( insn ) ) == COND_EXEC && find_reg_note ( insn , REG_NORETURN , NULL_RTX ) ) { rtx b = emit_insn_before ( gen_safe_across_calls_all ( ) , insn ) ; rtx a = emit_insn_after ( gen_safe_across_calls_normal ( ) , insn ) ; if ( bb -> head == insn ) bb -> head = b ; if ( bb -> end == insn ) bb -> end = a ; } if ( insn == bb -> end ) break ; insn = NEXT_INSN ( insn ) ; } } } </s>

Emit pseudo-ops for the assembler to describe predicate relations . At present this assumes that we only consider predicate pairs to be mutex , and that the assembler can deduce proper values from straight-line code .


<s> unsigned MSP430InstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { const MCInstrDesc & Desc = MI . getDesc ( ) ; switch ( Desc . getOpcode ( ) ) { case TargetOpcode :: CFI_INSTRUCTION : case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return 0 ; case TargetOpcode :: INLINEASM : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; return TII . getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } } return Desc . getSize ( ) ; } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> EVT AAPTargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & Context , EVT VT ) const { if ( ! VT . isVector ( ) ) { return MVT :: i16 ; } return VT . changeVectorElementTypeToInteger ( ) ; } </s>


<s> static rtx emit_multi_reg_push ( unsigned long mask , unsigned long dwarf_regs_mask ) { int num_regs = 0 ; int num_dwarf_regs = 0 ; int i , j ; rtx par ; rtx dwarf ; int dwarf_par_index ; rtx tmp , reg ; dwarf_regs_mask &= ~ ( 1 << PC_REGNUM ) ; for ( i = 0 ; i <= LAST_ARM_REGNUM ; i ++ ) { if ( mask & ( 1 << i ) ) num_regs ++ ; if ( dwarf_regs_mask & ( 1 << i ) ) num_dwarf_regs ++ ; } gcc_assert ( num_regs && num_regs <= 16 ) ; gcc_assert ( ( dwarf_regs_mask & ~ mask ) == 0 ) ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs ) ) ; dwarf = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( num_dwarf_regs + 1 ) ) ; dwarf_par_index = 1 ; for ( i = 0 ; i <= LAST_ARM_REGNUM ; i ++ ) { if ( mask & ( 1 << i ) ) { rtx dwarf_reg = reg = gen_rtx_REG ( SImode , i ) ; if ( arm_current_function_pac_enabled_p ( ) && i == IP_REGNUM ) dwarf_reg = gen_rtx_REG ( SImode , RA_AUTH_CODE ) ; XVECEXP ( par , 0 , 0 ) = gen_rtx_SET ( gen_frame_mem ( BLKmode , gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - 4 * num_regs ) ) ) , gen_rtx_UNSPEC ( BLKmode , gen_rtvec ( 1 , reg ) , UNSPEC_PUSH_MULT ) ) ; if ( dwarf_regs_mask & ( 1 << i ) ) { tmp = gen_rtx_SET ( gen_frame_mem ( SImode , stack_pointer_rtx ) , dwarf_reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , dwarf_par_index ++ ) = tmp ; } break ; } } for ( j = 1 , i ++ ; j < num_regs ; i ++ ) { if ( mask & ( 1 << i ) ) { rtx dwarf_reg = reg = gen_rtx_REG ( SImode , i ) ; if ( arm_current_function_pac_enabled_p ( ) && i == IP_REGNUM ) dwarf_reg = gen_rtx_REG ( SImode , RA_AUTH_CODE ) ; XVECEXP ( par , 0 , j ) = gen_rtx_USE ( VOIDmode , reg ) ; if ( dwarf_regs_mask & ( 1 << i ) ) { tmp = gen_rtx_SET ( gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , 4 * j ) ) , dwarf_reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , dwarf_par_index ++ ) = tmp ; } j ++ ; } } par = emit_insn ( par ) ; tmp = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - 4 * num_regs ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , 0 ) = tmp ; add_reg_note ( par , REG_FRAME_RELATED_EXPR , dwarf ) ; return par ; } </s>

Generate and emit an insn that we will recognize as a push_multi . Unfortunately , since this insn does not reflect very well the actual semantics of the operation , we need to annotate the insn for the benefit of DWARF2 frame unwind information .