<s> bool ARMCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto DL = MF . getDataLayout ( ) ; auto & TLI = * getTLI < ARMTargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb ( ) ) return false ; if ( Subtarget -> useSoftFloat ( ) || ! Subtarget -> hasVFP2 ( ) ) return false ; auto & Args = F . getArgumentList ( ) ; for ( auto & Arg : Args ) if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; SmallVector < ArgInfo , 8 > ArgInfos ; unsigned Idx = 0 ; for ( auto & Arg : Args ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + 1 , DL , F ) ; splitToValueTypes ( AInfo , ArgInfos , DL , MF . getRegInfo ( ) ) ; Idx ++ ; } FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; return handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> unsigned ARMBaseInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case ARM :: STRrs : case ARM :: t2STRs : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isReg ( ) && MI -> getOperand ( 3 ) . isImm ( ) && MI -> getOperand ( 2 ) . getReg ( ) == 0 && MI -> getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: STRi12 : case ARM :: t2STRi12 : case ARM :: tSTRspi : case ARM :: VSTRD : case ARM :: VSTRS : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VST1q64 : if ( MI -> getOperand ( 0 ) . isFI ( ) && MI -> getOperand ( 2 ) . getSubReg ( ) == 0 ) { FrameIndex = MI -> getOperand ( 0 ) . getIndex ( ) ; return MI -> getOperand ( 2 ) . getReg ( ) ; } break ; case ARM :: VSTMQIA : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> static void tilegx_expand_to_rtl_hook ( void ) { crtl -> uses_pic_offset_table = 0 ; } </s>


<s> void setFunction ( Function & F ) { Func = & F ; } </s>

Initialize data structures for specified new function .


<s> SDNode * X86DAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI -> getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> bool mayStore ( ) const { return Store ; } </s>

Return true if this instruction could possibly modify memory .


<s> static rtx nds32_expand_unopimm_builtin ( enum insn_code icode , tree exp , rtx target , bool return_p , const char * name ) { rtx pat ; rtx op0 = nds32_read_argument ( exp , 0 ) ; int op0_num = return_p ? 1 : 0 ; if ( return_p ) target = nds32_legitimize_target ( icode , target ) ; if ( ! nds32_check_constant_argument ( icode , op0_num , op0 , name ) ) return NULL_RTX ; op0 = nds32_legitimize_argument ( icode , op0_num , op0 ) ; if ( return_p ) pat = GEN_FCN ( icode ) ( target , op0 ) ; else pat = GEN_FCN ( icode ) ( op0 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return target ; } </s>

Expand builtins that take one operands and the first is immediate .


<s> static void emit_move_after_reload ( rtx to , rtx from , rtx scratch ) { rtx insn ; if ( TARGET_M6812 || H_REG_P ( to ) || H_REG_P ( from ) ) { insn = emit_move_insn ( to , from ) ; } else { emit_move_insn ( scratch , from ) ; insn = emit_move_insn ( to , scratch ) ; } if ( IS_STACK_PUSH ( to ) ) { REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_INC , XEXP ( XEXP ( to , 0 ) , 0 ) , REG_NOTES ( insn ) ) ; } else if ( IS_STACK_POP ( from ) ) { REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_INC , XEXP ( XEXP ( from , 0 ) , 0 ) , REG_NOTES ( insn ) ) ; } else if ( TARGET_M6811 && SP_REG_P ( from ) ) { REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_INC , from , REG_NOTES ( insn ) ) ; } } </s>

Emit a move after the reload pass has completed . This is used to emit the prologue and epilogue .


<s> bool SIWholeQuadMode :: runOnMachineFunction ( MachineFunction & MF ) { Instructions . clear ( ) ; Blocks . clear ( ) ; LiveMaskQueries . clear ( ) ; LowerToCopyInstrs . clear ( ) ; CallingConv = MF . getFunction ( ) . getCallingConv ( ) ; const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; LIS = & getAnalysis < LiveIntervals > ( ) ; char GlobalFlags = analyzeFunction ( MF ) ; unsigned LiveMaskReg = 0 ; if ( ! ( GlobalFlags & StateWQM ) ) { lowerLiveMaskQueries ( AMDGPU :: EXEC ) ; if ( ! ( GlobalFlags & StateWWM ) ) return ! LiveMaskQueries . empty ( ) ; } else { MachineBasicBlock & Entry = MF . front ( ) ; MachineBasicBlock :: iterator EntryMI = Entry . getFirstNonPHI ( ) ; if ( GlobalFlags & StateExact || ! LiveMaskQueries . empty ( ) ) { LiveMaskReg = MRI -> createVirtualRegister ( & AMDGPU :: SReg_64RegClass ) ; MachineInstr * MI = BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( AMDGPU :: COPY ) , LiveMaskReg ) . addReg ( AMDGPU :: EXEC ) ; LIS -> InsertMachineInstrInMaps ( * MI ) ; } lowerLiveMaskQueries ( LiveMaskReg ) ; if ( GlobalFlags == StateWQM ) { BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( AMDGPU :: S_WQM_B64 ) , AMDGPU :: EXEC ) . addReg ( AMDGPU :: EXEC ) ; lowerCopyInstrs ( ) ; return true ; } } DEBUG ( printInfo ( ) ) ; lowerCopyInstrs ( ) ; for ( auto BII : Blocks ) processBlock ( * BII . first , LiveMaskReg , BII . first == & * MF . begin ( ) ) ; LIS -> removeRegUnit ( * MCRegUnitIterator ( AMDGPU :: SCC , TRI ) ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .

AMDGPU SI SI SI 0 AMDGPU::EXEC AMDGPU::SReg_64RegClass AMDGPU::COPY AMDGPU::EXEC AMDGPU::S_WQM_B64 AMDGPU::EXEC AMDGPU::EXEC AMDGPU::SCC


<s> RegisterBankInfo :: InstructionMapping AArch64RegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { RegisterBankInfo :: InstructionMapping Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; LLT Ty = MI . getType ( ) ; unsigned BankID ; if ( Ty . isVector ( ) ) BankID = AArch64 :: FPRRegBankID ; else BankID = AArch64 :: GPRRegBankID ; Mapping = InstructionMapping { 1 , 1 , MI . getNumOperands ( ) } ; int Size = Ty . isSized ( ) ? Ty . getSizeInBits ( ) : 0 ; for ( unsigned Idx = 0 ; Idx < MI . getNumOperands ( ) ; ++ Idx ) Mapping . setOperandMapping ( Idx , Size , getRegBank ( BankID ) ) ; return Mapping ; } </s>

Get the mapping of the different operands of MI on the register bank .


<s>
virtual
const
char
*
getPassName
(
)
const
override
{
return
"SIC Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> uint64_t ARMPLT :: emit ( MemoryRegion & pRegion ) { uint64_t result = 0x0 ; iterator it = begin ( ) ; unsigned char * buffer = pRegion . begin ( ) ; memcpy ( buffer , llvm :: cast < ARMPLT0 > ( ( * it ) ) . getValue ( ) , ARMPLT0 :: EntrySize ) ; result += ARMPLT0 :: EntrySize ; ++ it ; ARMPLT1 * plt1 = 0 ; ARMPLT :: iterator ie = end ( ) ; while ( it != ie ) { plt1 = & ( llvm :: cast < ARMPLT1 > ( * it ) ) ; memcpy ( buffer + result , plt1 -> getValue ( ) , ARMPLT1 :: EntrySize ) ; result += ARMPLT1 :: EntrySize ; ++ it ; } return result ; } </s>

Output the remark via the diagnostic handler and to the optimization record file .

ARM ARM 0x0 ARM ARM ARM ARM 0 ARM ARM ARM ARM


<s> size_t parallel_elements ( rtx parallel_rtx ) { parallel_rtx = extract_pattern_from_insn ( parallel_rtx ) ; gcc_assert ( GET_CODE ( parallel_rtx ) == PARALLEL ) ; return XVECLEN ( parallel_rtx , 0 ) ; } </s>

Get the number of elements in a parallel rtx .


<s> unsigned X86TargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { if ( classifyEHPersonality ( PersonalityFn ) == EHPersonality :: CoreCLR ) return Subtarget . isTarget64BitLP64 ( ) ? X86 :: RDX : X86 :: EDX ; return Subtarget . isTarget64BitLP64 ( ) ? X86 :: RAX : X86 :: EAX ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasV8_1aOps ( false ) , HasFPARMv8 ( false ) , HasNEON ( false ) , HasCrypto ( false ) , HasCRC ( false ) , HasZeroCycleRegMove ( false ) , HasZeroCycleZeroing ( false ) , IsLittle ( LittleEndian ) , CPUString ( CPU ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS ) ) , TSInfo ( ) , TLInfo ( TM , * this ) { } </s>

This constructor initializes the data members to match that of the specified triple .


<s> virtual const TeeRISCRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static inline void desc_abi ( unsigned char abi , unsigned char context , struct unw_state_record * sr ) { sr -> unwabi = ( abi << 8 ) | context ; } </s>


<s> static void ix86_init_platform_type_builtins ( void ) { make_cpu_type_builtin ( "__builtin_cpu_init" , IX86_BUILTIN_CPU_INIT , INT_FTYPE_VOID , false ) ; make_cpu_type_builtin ( "__builtin_cpu_is" , IX86_BUILTIN_CPU_IS , INT_FTYPE_PCCHAR , true ) ; make_cpu_type_builtin ( "__builtin_cpu_supports" , IX86_BUILTIN_CPU_SUPPORTS , INT_FTYPE_PCCHAR , true ) ; } </s>

Make builtins to get CPU type and features supported . The created builtins are : __builtin_cpu_init ( ) , to detect cpu type and features , __builtin_cpu_is ( `` < CPUNAME > '' ) , to check if cpu is of type < CPUNAME > , __builtin_cpu_supports ( `` < FEATURE > '' ) , to check if cpu supports < FEATURE >


"Unexpected register class in CSRsViaCopy!"

"Function should be nounwind in insertCopiesSplitCSR!"

Insert explicit copies in entry and exit blocks .


<s> static unsigned int aarch64_classify_vector_mode ( machine_mode mode ) { if ( aarch64_advsimd_struct_mode_p ( mode ) ) return VEC_ADVSIMD | VEC_STRUCT ; if ( aarch64_sve_pred_mode_p ( mode ) ) return VEC_SVE_PRED ; switch ( mode ) { case E_VNx2QImode : case E_VNx4QImode : case E_VNx8QImode : case E_VNx2HImode : case E_VNx4HImode : case E_VNx2SImode : case E_VNx2HFmode : case E_VNx4HFmode : case E_VNx2SFmode : return TARGET_SVE ? VEC_SVE_DATA | VEC_PARTIAL : 0 ; case E_VNx16QImode : case E_VNx8HImode : case E_VNx4SImode : case E_VNx2DImode : case E_VNx8BFmode : case E_VNx8HFmode : case E_VNx4SFmode : case E_VNx2DFmode : return TARGET_SVE ? VEC_SVE_DATA : 0 ; case E_VNx32QImode : case E_VNx16HImode : case E_VNx8SImode : case E_VNx4DImode : case E_VNx16BFmode : case E_VNx16HFmode : case E_VNx8SFmode : case E_VNx4DFmode : case E_VNx48QImode : case E_VNx24HImode : case E_VNx12SImode : case E_VNx6DImode : case E_VNx24BFmode : case E_VNx24HFmode : case E_VNx12SFmode : case E_VNx6DFmode : case E_VNx64QImode : case E_VNx32HImode : case E_VNx16SImode : case E_VNx8DImode : case E_VNx32BFmode : case E_VNx32HFmode : case E_VNx16SFmode : case E_VNx8DFmode : return TARGET_SVE ? VEC_SVE_DATA | VEC_STRUCT : 0 ; case E_V8QImode : case E_V4HImode : case E_V2SImode : case E_V4HFmode : case E_V4BFmode : case E_V2SFmode : case E_V1DFmode : case E_V16QImode : case E_V8HImode : case E_V4SImode : case E_V2DImode : case E_V8HFmode : case E_V8BFmode : case E_V4SFmode : case E_V2DFmode : return TARGET_SIMD ? VEC_ADVSIMD : 0 ; default : return 0 ; } } </s>

Return a set of flags describing the vector properties of mode MODE . Ignore modes that are not supported by the current target .


<s>
void
BlackfinInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
I
!=
MBB
.
end
(
)
I
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
if
(
inClass
(
BF
::
DPRegClass
,
SrcReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
STORE32fi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
if
(
inClass
(
BF
::
D16RegClass
,
SrcReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
STORE16fi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
if
(
inClass
(
BF
::
AnyCCRegClass
,
SrcReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
STORE8fi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
llvm_unreachable
(
(
std
::
string
(
"Cannot store regclass to stack slot: "
)
+
RC
->
getName
(
)
)
.
c_str
(
)
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s>
SDValue
RISCVTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
RETURNADDR
:
return
lowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
lowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
lowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
lowerGlobalTLSAddress
(
cast
<
GlobalAddressSDNode
>
(
Op
)
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
lowerBlockAddress
(
cast
<
BlockAddressSDNode
>
(
Op
)
,
DAG
)
;
case
ISD
::
JumpTable
:
return
lowerJumpTable
(
cast
<
JumpTableSDNode
>
(
Op
)
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
lowerConstantPool
(
cast
<
ConstantPoolSDNode
>
(
Op
)
,
DAG
)
;
case
ISD
::
VASTART
:
return
lowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
VAARG
:
return
lowerVAARG
(
Op
,
DAG
)
;
case
ISD
::
ATOMIC_FENCE
:
return
lowerATOMIC_FENCE
(
Op
,
DAG
)
;
case
ISD
::
STACKSAVE
:
return
lowerSTACKSAVE
(
Op
,
DAG
)
;
case
ISD
::
STACKRESTORE
:
return
lowerSTACKRESTORE
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
lowerFRAMEADDR
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"Unexpected node to lower"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

RISCV
RISCV
ISD::RETURNADDR
ISD::SELECT_CC
ISD::GlobalAddress
ISD::GlobalTLSAddress
ISD::BlockAddress
ISD::JumpTable
ISD::ConstantPool
ISD::VASTART
ISD::VAARG
ISD::ATOMIC_FENCE
ISD::STACKSAVE
ISD::STACKRESTORE
ISD::FRAMEADDR
"Unexpected node to lower"


"Hexagon optimize redundant zero and size extends"


<s> static int get_unit_reqs ( rtx_insn * insn , int * req1 , int * side1 , int * req2 , int * side2 ) { enum attr_units units ; enum attr_cross cross ; int side , req ; if ( ! NONDEBUG_INSN_P ( insn ) || recog_memoized ( insn ) < 0 ) return 0 ; units = get_attr_units ( insn ) ; if ( units == UNITS_UNKNOWN ) return 0 ; side = get_insn_side ( insn , units ) ; cross = get_attr_cross ( insn ) ; req = ( units == UNITS_D ? UNIT_REQ_D : units == UNITS_D_ADDR ? UNIT_REQ_D : units == UNITS_DL ? UNIT_REQ_DL : units == UNITS_DS ? UNIT_REQ_DS : units == UNITS_L ? UNIT_REQ_L : units == UNITS_LS ? UNIT_REQ_LS : units == UNITS_S ? UNIT_REQ_S : units == UNITS_M ? UNIT_REQ_M : units == UNITS_DLS ? UNIT_REQ_DLS : - 1 ) ; gcc_assert ( req != - 1 ) ; * req1 = req ; * side1 = side ; if ( units == UNITS_D_ADDR ) { * req2 = UNIT_REQ_T ; * side2 = side ^ ( cross == CROSS_Y ? 1 : 0 ) ; return 2 ; } else if ( cross == CROSS_Y ) { * req2 = UNIT_REQ_X ; * side2 = side ; return 2 ; } return 1 ; } </s>

Examine INSN , and store in REQ1/SIDE1 and REQ2/SIDE2 the unit requirements . Returns zero if INSN ca n't be handled , otherwise either one or two to show how many of the two pairs are in use . REQ1 is always used , it holds what is normally thought of as the instructions reservation , e.g . UNIT_REQ_DL . REQ2 is used to either describe a cross path , or for loads/stores , the T unit .


<s>
Function
*
MBlazeIntrinsicInfo
::
getDeclaration
(
Module
*
M
,
unsigned
IntrID
,
Type
*
*
Tys
,
unsigned
numTy
)
const
{
assert
(
!
isOverloaded
(
IntrID
)
&&
"MBlaze intrinsics are not overloaded"
)
;
AttrListPtr
AList
=
getAttributes
(
(
mblazeIntrinsic
::
ID
)
IntrID
)
;
return
cast
<
Function
>
(
M
->
getOrInsertFunction
(
getName
(
IntrID
)
,
getType
(
M
->
getContext
(
)
,
IntrID
)
,
AList
)
)
;
}
</s>

Create or insert an LLVM Function declaration for an intrinsic , and return it .

MBlaze
MBlaze
"MBlaze intrinsics are not overloaded"
mblazeIntrinsic::ID


<s> bool TPCLutCacheCounter :: runOnMachineFunction ( MachineFunction & MF ) { auto ST = & MF . getSubtarget < TPCSubtarget > ( ) ; bool PrintlutWarn = ST -> getTargetLowering ( ) -> getTargetMachine ( ) . Options . LutWarn ; if ( ! PrintlutWarn ) { return false ; } for ( auto & BB : MF ) { int deep = 0 ; if ( ! isLookUpInADeepLoop ( & BB , deep ) ) continue ; for ( auto & MI : BB ) { if ( ST -> hasGoyaISA ( ) ) { if ( ! processLookupDali ( MI ) ) { return false ; } } else { if ( ! processLookupGen2Plus ( MI ) ) { return false ; } } } } return true ; } </s>


<s> void mprocAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { mprocMCInstLower MCInstLowering ( OutContext , * this ) ; MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; OutStreamer . EmitInstruction ( TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
MachineBasicBlock
::
iterator
P2FrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
LLVM_DEBUG
(
errs
(
)
<<
"=== eliminate call frame pseudo\n"
)
;
if
(
!
hasReservedCallFrame
(
MF
)
)
{
int64_t
Amount
=
I
->
getOperand
(
0
)
.
getImm
(
)
;
if
(
I
->
getOpcode
(
)
==
P2
::
ADJCALLSTACKDOWN
)
Amount
=
Amount
;
if
(
Amount
)
tm
.
getInstrInfo
(
)
->
adjustStackPtr
(
P2
::
PTRA
,
Amount
,
MBB
,
I
)
;
}
return
MBB
.
erase
(
I
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static void pru_asm_function_prologue ( FILE * file ) { if ( flag_verbose_asm || flag_debug_asm ) pru_dump_frame_layout ( file ) ; } </s>


<s> static void mcore_external_libcall ( rtx fun ) { fprintf ( asm_out_file , "\t.import\t" ) ; assemble_name ( asm_out_file , XSTR ( fun , 0 ) ) ; fprintf ( asm_out_file , "\n" ) ; } </s>

Worker function for TARGET_ASM_EXTERNAL_LIBCALL .


"Hardware instruction generated for atomic "

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s>
void
ConvergingVLIWScheduler
::
releaseBottomNode
(
SUnit
*
SU
)
{
if
(
SU
->
isScheduled
)
return
;
assert
(
SU
->
getInstr
(
)
&&
"Scheduled SUnit must have instr"
)
;
for
(
SUnit
::
succ_iterator
I
=
SU
->
Succs
.
begin
(
)
,
E
=
SU
->
Succs
.
end
(
)
;
I
!=
E
;
++
I
)
{
unsigned
SuccReadyCycle
=
I
->
getSUnit
(
)
->
BotReadyCycle
;
unsigned
MinLatency
=
I
->
getLatency
(
)
;
Bot
.
MaxMinLatency
=
std
::
max
(
MinLatency
,
Bot
.
MaxMinLatency
)
;
if
(
SU
->
BotReadyCycle
<
SuccReadyCycle
+
MinLatency
)
SU
->
BotReadyCycle
=
SuccReadyCycle
+
MinLatency
;
}
Bot
.
releaseNode
(
SU
,
SU
->
BotReadyCycle
)
;
}
</s>

Currently only scheduling top-down , so this method is empty .

Hexagon
"Scheduled SUnit must have instr"


<s> static inline bool mode_supports_vsx_dform_quad ( machine_mode mode ) { return ( ( reg_addr [ mode ] . addr_mask [ RELOAD_REG_ANY ] & RELOAD_REG_QUAD_OFFSET ) != 0 ) ; } </s>

Return true if we have D-form addressing in VSX registers . This addressing is more limited than normal d-form addressing in that the offset must be aligned on a 16-byte boundary .


<s> int m32c_modes_tieable_p ( enum machine_mode m1 , enum machine_mode m2 ) { if ( GET_MODE_SIZE ( m1 ) == GET_MODE_SIZE ( m2 ) ) return 1 ; if ( m1 == QImode || m2 == QImode ) return 0 ; return 1 ; } </s>

Implements MODES_TIEABLE_P . In general , modes are n't tieable since registers are all different sizes . However , since most modes are bigger than our registers anyway , it 's easier to implement this function that way , leaving QImode as the only unique case .


<s> unsigned CAHPInstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { if ( BytesRemoved ) * BytesRemoved = 0 ; MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return 0 ; if ( ! I -> getDesc ( ) . isUnconditionalBranch ( ) && ! I -> getDesc ( ) . isConditionalBranch ( ) ) return 0 ; I -> eraseFromParent ( ) ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return 1 ; -- I ; if ( ! I -> getDesc ( ) . isConditionalBranch ( ) ) return 1 ; I -> eraseFromParent ( ) ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; return 2 ; } </s>

Remove the branching code at the end of the specific MBB .


<s> const RISCVRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>


<s> void func_fma_steering :: dfs ( void ( * process_forest ) ( fma_forest * ) , void ( * process_root ) ( fma_forest * , fma_root_node * ) , void ( * process_node ) ( fma_forest * , fma_node * ) , bool free ) { vec < fma_node * > to_process ; std :: list < fma_forest * > :: iterator forest_iter ; to_process . create ( 0 ) ; for ( forest_iter = this -> m_fma_forests . begin ( ) ; forest_iter != this -> m_fma_forests . end ( ) ; forest_iter ++ ) { std :: list < fma_root_node * > :: iterator root_iter ; if ( process_forest ) process_forest ( * forest_iter ) ; for ( root_iter = ( * forest_iter ) -> get_roots ( ) -> begin ( ) ; root_iter != ( * forest_iter ) -> get_roots ( ) -> end ( ) ; root_iter ++ ) { if ( process_root ) process_root ( * forest_iter , * root_iter ) ; to_process . safe_push ( * root_iter ) ; } while ( ! to_process . is_empty ( ) ) { fma_node * node ; std :: list < fma_node * > :: iterator child_iter ; node = to_process . pop ( ) ; if ( process_node ) process_node ( * forest_iter , node ) ; if ( node -> get_children ( ) -> empty ( ) ) continue ; for ( child_iter = node -> get_children ( ) -> begin ( ) ; child_iter != node -> get_children ( ) -> end ( ) ; child_iter ++ ) to_process . safe_push ( * child_iter ) ; if ( free ) { if ( node -> root_p ( ) ) delete static_cast < fma_root_node * > ( node ) ; else delete node ; } } if ( free ) delete * forest_iter ; } to_process . release ( ) ; } </s>

Perform a depth-first search of the forests of fma_node in THIS- > m_fma_forests , calling PROCESS_FOREST ( ) on each fma_forest object in THIS- > m_fma_forests list , PROCESS_ROOT ( ) on each tree root and PROCESS_NODE ( ) on each node . If FREE is true , free all std : :list in the same dfs .


<s> static bool legitimate_small_data_address_p ( rtx x , machine_mode mode ) { switch ( GET_CODE ( x ) ) { case CONST : return legitimate_small_data_address_p ( XEXP ( x , 0 ) , mode ) ; case SYMBOL_REF : return SYMBOL_REF_SMALL_P ( x ) ; case PLUS : { bool p0 = ( GET_CODE ( XEXP ( x , 0 ) ) == SYMBOL_REF ) && SYMBOL_REF_SMALL_P ( XEXP ( x , 0 ) ) ; if ( ! CONST_INT_P ( XEXP ( x , 1 ) ) ) return false ; switch ( GET_MODE_SIZE ( mode ) ) { case 1 : return p0 ; case 2 : return p0 && ( ( INTVAL ( XEXP ( x , 1 ) ) & 0x1 ) == 0 ) ; case 4 : case 8 : return p0 && ( ( INTVAL ( XEXP ( x , 1 ) ) & 0x3 ) == 0 ) ; default : return false ; } } default : return false ; } } </s>

Return true if x is ok to be used as a small data address .


<s> bool HexagonInstrInfo :: isPredicable ( MachineInstr & MI ) const { return MI . getDesc ( ) . isPredicable ( ) ; } </s>

Return true if the specified instruction can be predicated .


Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> static reg_class_t xstormy16_preferred_reload_class ( rtx x , reg_class_t rclass ) { if ( rclass == GENERAL_REGS && MEM_P ( x ) ) return EIGHT_REGS ; return rclass ; } </s>

Worker function for TARGET_PREFERRED_RELOAD_CLASS and TARGET_PREFERRED_OUTPUT_RELOAD_CLASS .


<s>
void
rvexInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
O
,
StringRef
Annot
)
{
O
<<
"\tc0 "
;
printInstruction
(
MI
,
O
)
;
printAnnotation
(
O
,
Annot
)
;
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s> MVT M68kTargetLowering :: getScalarShiftAmountTy ( const DataLayout & DL , EVT Ty ) const { if ( Ty . isSimple ( ) ) { return Ty . getSimpleVT ( ) ; } return MVT :: getIntegerVT ( DL . getPointerSizeInBits ( 0 ) ) ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> bool SIFrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return true ; const SIMachineFunctionInfo * FuncInfo = MF . getInfo < SIMachineFunctionInfo > ( ) ; if ( ! FuncInfo -> SGPRForFPSaveRestoreCopy ) return false ; for ( auto & CS : CSI ) { if ( CS . getReg ( ) == FuncInfo -> getFrameOffsetReg ( ) ) { if ( FuncInfo -> SGPRForFPSaveRestoreCopy != AMDGPU :: NoRegister ) CS . setDstReg ( FuncInfo -> SGPRForFPSaveRestoreCopy ) ; break ; } } return false ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .

AMDGPU SI SI SI SI SI SI AMDGPU::NoRegister


"Instr doesn't have FrameIndex operand!"

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s> static int ix86_vec_cost ( machine_mode mode , int cost , bool parallel ) { if ( ! VECTOR_MODE_P ( mode ) ) return cost ; if ( ! parallel ) return cost * GET_MODE_NUNITS ( mode ) ; if ( GET_MODE_BITSIZE ( mode ) == 128 && TARGET_SSE_SPLIT_REGS ) return cost * 2 ; if ( GET_MODE_BITSIZE ( mode ) > 128 && TARGET_AVX128_OPTIMAL ) return cost * GET_MODE_BITSIZE ( mode ) / 128 ; return cost ; } </s>

Return cost of vector operation in MODE given that scalar version has COST . If PARALLEL is true assume that CPU has more than one unit performing the operation .


<s>
bool
MipsOs16
::
runOnModule
(
Module
&
M
)
{
bool
usingMask
=
Mips32FunctionMask
.
length
(
)
>
0
;
bool
doneUsingMask
=
false
;
DEBUG
(
dbgs
(
)
<<
"Run on Module MipsOs16 \n"
<<
Mips32FunctionMask
<<
"\n"
)
;
if
(
usingMask
)
DEBUG
(
dbgs
(
)
<<
"using mask \n"
<<
Mips32FunctionMask
<<
"\n"
)
;
unsigned
int
functionIndex
=
0
;
bool
modified
=
false
;
for
(
Module
::
iterator
F
=
M
.
begin
(
)
,
E
=
M
.
end
(
)
;
F
!=
E
;
++
F
)
{
if
(
F
->
isDeclaration
(
)
)
continue
;
DEBUG
(
dbgs
(
)
<<
"Working on "
<<
F
->
getName
(
)
<<
"\n"
)
;
if
(
usingMask
)
{
if
(
!
doneUsingMask
)
{
if
(
functionIndex
==
Mips32FunctionMask
.
length
(
)
)
functionIndex
=
0
;
switch
(
Mips32FunctionMask
[
functionIndex
]
)
{
case
'1'
:
DEBUG
(
dbgs
(
)
<<
"mask forced mips32: "
<<
F
->
getName
(
)
<<
"\n"
)
;
F
->
addFnAttr
(
"nomips16"
)
;
break
;
case
'.'
:
doneUsingMask
=
true
;
break
;
default
:
break
;
}
functionIndex
++
;
}
}
else
{
if
(
needsFP
(
*
F
)
)
{
DEBUG
(
dbgs
(
)
<<
"os16 forced mips32: "
<<
F
->
getName
(
)
<<
"\n"
)
;
F
->
addFnAttr
(
"nomips16"
)
;
}
else
{
DEBUG
(
dbgs
(
)
<<
"os16 forced mips16: "
<<
F
->
getName
(
)
<<
"\n"
)
;
F
->
addFnAttr
(
"mips16"
)
;
}
}
}
return
modified
;
}
</s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .

Mips
Mips
Mips
0
"Run on Module MipsOs16 \n"
Mips
"\n"
"using mask \n"
Mips
"\n"
0
"Working on "
"\n"
Mips
0
Mips
"mask forced mips32: "
"\n"
"nomips16"
"os16 forced mips32: "
"\n"
"nomips16"
"os16 forced mips16: "
"\n"
"mips16"


<s> void csky_init_builtins ( void ) { static tree csky_floatHF_type_node = make_node ( REAL_TYPE ) ; TYPE_PRECISION ( csky_floatHF_type_node ) = GET_MODE_PRECISION ( HFmode ) ; layout_type ( csky_floatHF_type_node ) ; ( * lang_hooks . types . register_builtin_type ) ( csky_floatHF_type_node , "__fp16" ) ; } </s>

Implement the TARGET_INIT_BUILTINS target macro .


<s>
void
HexagonMCCodeEmitter
::
encodeInstruction
(
MCInst
const
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
MCSubtargetInfo
const
&
STI
)
const
{
MCInst
&
HMB
=
const_cast
<
MCInst
&
>
(
MI
)
;
assert
(
HexagonMCInstrInfo
::
isBundle
(
HMB
)
)
;
DEBUG
(
dbgs
(
)
<<
"Encoding bundle\n"
;
)
;
*
Addend
=
0
;
*
Extended
=
false
;
*
CurrentBundle
=
&
MI
;
size_t
Instruction
=
0
;
size_t
Last
=
HexagonMCInstrInfo
::
bundleSize
(
HMB
)
1
;
for
(
auto
&
I
:
HexagonMCInstrInfo
::
bundleInstructions
(
HMB
)
)
{
MCInst
&
HMI
=
const_cast
<
MCInst
&
>
(
*
I
.
getInst
(
)
)
;
verifyInstructionPredicates
(
HMI
,
computeAvailableFeatures
(
STI
.
getFeatureBits
(
)
)
)
;
EncodeSingleInstruction
(
HMI
,
OS
,
Fixups
,
STI
,
parseBits
(
Instruction
,
Last
,
HMB
,
HMI
)
,
Instruction
)
;
*
Extended
=
HexagonMCInstrInfo
::
isImmext
(
HMI
)
;
*
Addend
+=
HEXAGON_INSTR_SIZE
;
++
Instruction
;
}
return
;
}
</s>

Encode the given Inst to bytes and append to CB .

Hexagon
Hexagon
Hexagon
"Encoding bundle\n"
0
0
Hexagon
1
Hexagon
Hexagon


"dispatch_function_versions, clone %d, %s\n"

This function generates the dispatch function for multi-versioned functions . DISPATCH_DECL is the function which will contain the dispatch logic . FNDECLS are the function choices for dispatch , and is a tree chain . EMPTY_BB is the basic block pointer in DISPATCH_DECL in which the dispatch code is generated .


<s> Register RISCVTargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) const { return RISCV :: X11 ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .


"%qs requires PowerPC64 architecture, enabling"

The Darwin version of SUBTARGET_OVERRIDE_OPTIONS .


<s>
bool
LanaiInstrInfo
::
areMemAccessesTriviallyDisjoint
(
MachineInstr
&
MIa
,
MachineInstr
&
MIb
,
AliasAnalysis
*
)
const
{
assert
(
MIa
.
mayLoadOrStore
(
)
&&
"MIa must be a load or store."
)
;
assert
(
MIb
.
mayLoadOrStore
(
)
&&
"MIb must be a load or store."
)
;
if
(
MIa
.
hasUnmodeledSideEffects
(
)
||
MIb
.
hasUnmodeledSideEffects
(
)
||
MIa
.
hasOrderedMemoryRef
(
)
||
MIb
.
hasOrderedMemoryRef
(
)
)
return
false
;
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
unsigned
BaseRegA
=
0
,
BaseRegB
=
0
;
int64_t
OffsetA
=
0
,
OffsetB
=
0
;
unsigned
int
WidthA
=
0
,
WidthB
=
0
;
if
(
getMemOpBaseRegImmOfsWidth
(
MIa
,
BaseRegA
,
OffsetA
,
WidthA
,
TRI
)
&&
getMemOpBaseRegImmOfsWidth
(
MIb
,
BaseRegB
,
OffsetB
,
WidthB
,
TRI
)
)
{
if
(
BaseRegA
==
BaseRegB
)
{
int
LowOffset
=
std
::
min
(
OffsetA
,
OffsetB
)
;
int
HighOffset
=
std
::
max
(
OffsetA
,
OffsetB
)
;
int
LowWidth
=
(
LowOffset
==
OffsetA
)
WidthA
:
WidthB
;
if
(
LowOffset
+
LowWidth
<=
HighOffset
)
return
true
;
}
}
return
false
;
}
</s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


"builtin ID '%s' not found in bif file.\n"

Parse one two-line entry in the overload file .


<s> bool s390_decompose_addrstyle_without_index ( rtx op , rtx * base , HOST_WIDE_INT * offset ) { rtx off = NULL_RTX ; if ( CONST_SCALAR_INT_P ( op ) ) { off = op ; op = NULL_RTX ; } if ( op && GET_CODE ( op ) == PLUS && CONST_SCALAR_INT_P ( XEXP ( op , 1 ) ) ) { off = XEXP ( op , 1 ) ; op = XEXP ( op , 0 ) ; } while ( op && GET_CODE ( op ) == SUBREG ) op = SUBREG_REG ( op ) ; if ( op && GET_CODE ( op ) != REG ) return false ; if ( offset ) { if ( off == NULL_RTX ) * offset = 0 ; else if ( CONST_INT_P ( off ) ) * offset = INTVAL ( off ) ; else if ( CONST_WIDE_INT_P ( off ) ) * offset = CONST_WIDE_INT_ELT ( off , 0 ) ; else gcc_unreachable ( ) ; } if ( base ) * base = op ; return true ; } </s>

Decompose a RTL expression OP for an address style operand into its components , and return the base register in BASE and the offset in OFFSET . While OP looks like an address it is never supposed to be used as such . Return true if OP is a valid address operand , false if not .


<s> bool aarch_bti_enabled ( void ) { return aarch_enable_bti != 0 ; } </s>

Return TRUE if Branch Target Identification Mechanism is enabled .


<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { AttributeSet FnAttrs = F . getAttributes ( ) ; Attribute CPUAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "target-cpu" ) ; Attribute FSAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; Attribute SFAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "use-soft-float" ) ; bool SoftFloat = ! SFAttr . hasAttribute ( Attribute :: None ) ? SFAttr . getValueAsString ( ) == "true" : Options . UseSoftFloat ; auto & I = SubtargetMap [ CPU + FS + ( SoftFloat ? "use-soft-float=true" : "use-soft-float=false" ) ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < X86Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool Thumb1RegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { DebugLoc DL ; AddDefaultPred ( BuildMI ( MBB , I , DL , TII . get ( ARM :: tMOVr ) ) . addReg ( ARM :: R12 , RegState :: Define ) . addReg ( Reg , RegState :: Kill ) ) ; bool done = false ; for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { if ( II -> isDebugValue ( ) ) continue ; for ( unsigned i = 0 , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( ARM :: R12 ) ) { UseMI = II ; done = true ; break ; } if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == ARM :: R12 ) { UseMI = II ; done = true ; break ; } } } AddDefaultPred ( BuildMI ( MBB , UseMI , DL , TII . get ( ARM :: tMOVr ) ) . addReg ( Reg , RegState :: Define ) . addReg ( ARM :: R12 , RegState :: Kill ) ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .


<s>
bool
R600ClauseMergePass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
TII
=
static_cast
<
const
R600InstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
for
(
MachineFunction
::
iterator
BB
=
MF
.
begin
(
)
,
BB_E
=
MF
.
end
(
)
;
BB
!=
BB_E
;
++
BB
)
{
MachineBasicBlock
&
MBB
=
*
BB
;
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
,
E
=
MBB
.
end
(
)
;
MachineBasicBlock
::
iterator
LatestCFAlu
=
E
;
while
(
I
!=
E
)
{
MachineInstr
*
MI
=
I
++
;
if
(
(
!
TII
->
canBeConsideredALU
(
MI
)
&&
!
isCFAlu
(
MI
)
)
||
TII
->
mustBeLastInClause
(
MI
->
getOpcode
(
)
)
)
LatestCFAlu
=
E
;
if
(
!
isCFAlu
(
MI
)
)
continue
;
cleanPotentialDisabledCFAlu
(
MI
)
;
if
(
LatestCFAlu
!=
E
&&
mergeIfPossible
(
LatestCFAlu
,
MI
)
)
{
MI
->
eraseFromParent
(
)
;
}
else
{
assert
(
MI
->
getOperand
(
8
)
.
getImm
(
)
&&
"CF ALU instruction disabled"
)
;
LatestCFAlu
=
MI
;
}
}
}
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> TargetTransformInfo ARCTargetMachine :: getTargetTransformInfo ( const Function & F ) { return TargetTransformInfo ( ARCTTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> std :: pair < SDValue , SDValue > SystemZSelectionDAGInfo :: EmitTargetCodeForMemchr ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Src , SDValue Char , SDValue Length , MachinePointerInfo SrcPtrInfo ) const { EVT PtrVT = Src . getValueType ( ) ; SDVTList VTs = DAG . getVTList ( PtrVT , MVT :: i32 , MVT :: Other ) ; Length = DAG . getZExtOrTrunc ( Length , DL , PtrVT ) ; Char = DAG . getZExtOrTrunc ( Char , DL , MVT :: i32 ) ; Char = DAG . getNode ( ISD :: AND , DL , MVT :: i32 , Char , DAG . getConstant ( 255 , DL , MVT :: i32 ) ) ; SDValue Limit = DAG . getNode ( ISD :: ADD , DL , PtrVT , Src , Length ) ; SDValue End = DAG . getNode ( SystemZISD :: SEARCH_STRING , DL , VTs , Chain , Limit , Src , Char ) ; SDValue CCReg = End . getValue ( 1 ) ; Chain = End . getValue ( 2 ) ; SDValue Ops [ ] = { End , DAG . getConstant ( 0 , DL , PtrVT ) , DAG . getConstant ( SystemZ :: CCMASK_SRST , DL , MVT :: i32 ) , DAG . getConstant ( SystemZ :: CCMASK_SRST_FOUND , DL , MVT :: i32 ) , CCReg } ; End = DAG . getNode ( SystemZISD :: SELECT_CCMASK , DL , PtrVT , Ops ) ; return std :: make_pair ( End , Chain ) ; } </s>

Emit target-specific code that performs a memchr , in cases where that is faster than a libcall .


"Hexagon relaxInstruction only works on bundles"

"No room to insert extender for relaxation"

Relax the instruction in the given fragment to the next wider instruction .


<s>
void
rs6000_aix_asm_output_dwarf_table_ref
(
char
*
frame_table_label
)
{
fprintf
(
asm_out_file
,
"\t.ref %s\n"
,
(
*
targetm
.
strip_name_encoding
)
(
frame_table_label
)
)
;
}
</s>

Issue assembly directives that create a reference to the given DWARF FRAME_TABLE_LABEL from the current function section .


"target CPU does not support THUMB instructions"

"target CPU does not support unaligned accesses"

"incompatible options %<-mstack-protector-guard=global%> and "

"This architecture does not support branch protection "

"Return address signing is not supported with %<-mtpcs-frame%>."

Reset options between modes that the user has specified .


<s> std :: pair < unsigned , const TargetRegisterClass * > NVPTXTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'b' : return std :: make_pair ( 0U , & NVPTX :: Int1RegsRegClass ) ; case 'c' : return std :: make_pair ( 0U , & NVPTX :: Int16RegsRegClass ) ; case 'h' : return std :: make_pair ( 0U , & NVPTX :: Int16RegsRegClass ) ; case 'r' : return std :: make_pair ( 0U , & NVPTX :: Int32RegsRegClass ) ; case 'l' : case 'N' : return std :: make_pair ( 0U , & NVPTX :: Int64RegsRegClass ) ; case 'f' : return std :: make_pair ( 0U , & NVPTX :: Float32RegsRegClass ) ; case 'd' : return std :: make_pair ( 0U , & NVPTX :: Float64RegsRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


"Stack realignment in presence of dynamic allocas is not supported with"

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool XtensaPassConfig :: addPreISel ( ) { return false ; } </s>


<s> int rs6000_emit_vector_cond_expr ( rtx dest , rtx op1 , rtx op2 , rtx cond , rtx cc_op0 , rtx cc_op1 ) { enum machine_mode dest_mode = GET_MODE ( dest ) ; enum rtx_code rcode = GET_CODE ( cond ) ; rtx mask ; if ( ! TARGET_ALTIVEC ) return 0 ; mask = rs6000_emit_vector_compare ( rcode , cc_op0 , cc_op1 , dest_mode ) ; rs6000_emit_vector_select ( dest , op1 , op2 , mask ) ; return 1 ; } </s>

Emit vector conditional expression . DEST is destination . OP1 and OP2 are two VEC_COND_EXPR operands . CC_OP0 and CC_OP1 are the two operands for the relation operation COND .


<s> bool ARMBaseRegisterInfo :: isAsmClobberable ( const MachineFunction & MF , MCRegister PhysReg ) const { return ! getReservedRegs ( MF ) . test ( PhysReg ) ; } </s>

Returns false if we ca n't guarantee that Physreg , specified as an IR asm clobber constraint , will be preserved across the statement .


<s> const ARMSubtarget * ARMBaseTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; Attribute SFAttr = F . getFnAttribute ( "use-soft-float" ) ; bool SoftFloat = ! SFAttr . hasAttribute ( Attribute :: None ) ? SFAttr . getValueAsString ( ) == "true" : Options . UseSoftFloat ; auto & I = SubtargetMap [ CPU + FS + ( SoftFloat ? "use-soft-float=true" : "use-soft-float=false" ) ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < ARMSubtarget > ( TargetTriple , CPU , FS , * this , isLittle ) ; } return I . get ( ) ; } </s>

ARM ARM ARM "target-cpu" "target-features" "use-soft-float" "true" "use-soft-float=true" "use-soft-float=false" ARM


<s> unsigned X86InstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr * MI , int & FrameIndex ) const { if ( isFrameLoadOpcode ( MI -> getOpcode ( ) ) ) { unsigned Reg ; if ( ( Reg = isLoadFromStackSlot ( MI , FrameIndex ) ) ) return Reg ; const MachineMemOperand * Dummy ; return hasLoadFromStackSlot ( MI , Dummy , FrameIndex ) ; } return 0 ; } </s>

isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s>
void
add
(
HOST_WIDE_INT
val
)
{
asm_fprintf
(
t_file
,
"\tadds\t%s, #"
HOST_WIDE_INT_PRINT_DEC
"\n"
,
dst_regname
,
val
)
;
}
</s>

Make function pointers for the various linear operators we can apply to compute a multiplicative value .


<s> void Z80FrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; Z80MachineFunctionInfo * Z80FI = MF . getInfo < Z80MachineFunctionInfo > ( ) ; const Z80InstrInfo & TII = * static_cast < const Z80InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; uint64_t CallFrameSize = MFI -> getMaxCallFrameSize ( ) ; uint64_t FrameSize = Z80FI -> getCalleeSavedFrameSize ( ) ; uint64_t NumBytes = StackSize + CallFrameSize - FrameSize ; while ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == Z80 :: PUSH16r ) ) MBBI ++ ; if ( NumBytes || Z80FI -> isNeedFP ( ) ) { unsigned FP = TII . getRegisterInfo ( ) . getFrameRegister ( MF ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Z80 :: LD16ri ) , FP ) . addImm ( - NumBytes ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Z80 :: ADD16rSP ) , FP ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Z80 :: LD16SPr ) ) . addReg ( FP ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> SDValue MipsTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_Mips ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


Emit special PIC prologues and epilogues .


<s> MVT MipsTargetLowering :: getSetCCResultType ( MVT VT ) const { return MVT :: i32 ; } </s>

Return the value type to use for ISD : :SETCC .


<s> unsigned DLXMachineFunctionInfo :: getGlobalBaseReg ( ) { return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static ARM64Operand * CreateReg ( unsigned RegNum , bool isVector , SMLoc S , SMLoc E , MCContext & Ctx ) { ARM64Operand * Op = new ARM64Operand ( k_Register , Ctx ) ; Op -> Reg . RegNum = RegNum ; Op -> Reg . isVector = isVector ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> outliner :: OutlinedFunction RISCVInstrInfo :: getOutliningCandidateInfo ( std :: vector < outliner :: Candidate > & RepeatedSequenceLocs ) const { auto CannotInsertCall = [ ] ( outliner :: Candidate & C ) { const TargetRegisterInfo * TRI = C . getMF ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; C . initLRU ( * TRI ) ; LiveRegUnits LRU = C . LRU ; return ! LRU . available ( RISCV :: X5 ) ; } ; RepeatedSequenceLocs . erase ( std :: remove_if ( RepeatedSequenceLocs . begin ( ) , RepeatedSequenceLocs . end ( ) , CannotInsertCall ) , RepeatedSequenceLocs . end ( ) ) ; if ( RepeatedSequenceLocs . size ( ) < 2 ) return outliner :: OutlinedFunction ( ) ; unsigned SequenceSize = 0 ; auto I = RepeatedSequenceLocs [ 0 ] . front ( ) ; auto E = std :: next ( RepeatedSequenceLocs [ 0 ] . back ( ) ) ; for ( ; I != E ; ++ I ) SequenceSize += getInstSizeInBytes ( * I ) ; unsigned CallOverhead = 8 ; for ( auto & C : RepeatedSequenceLocs ) C . setCallInfo ( MachineOutlinerDefault , CallOverhead ) ; unsigned FrameOverhead = 4 ; if ( RepeatedSequenceLocs [ 0 ] . getMF ( ) -> getSubtarget ( ) . getFeatureBits ( ) [ RISCV :: FeatureStdExtC ] ) FrameOverhead = 2 ; return outliner :: OutlinedFunction ( RepeatedSequenceLocs , SequenceSize , FrameOverhead , MachineOutlinerDefault ) ; } </s>

Returns a outliner : :OutlinedFunction struct containing target-specific information for a set of outlining candidates .


<s> bool cris_simple_epilogue ( void ) { unsigned int regno ; unsigned int reglimit = STACK_POINTER_REGNUM ; if ( ! reload_completed || frame_pointer_needed || get_frame_size ( ) != 0 || crtl -> args . pretend_args_size || crtl -> args . size || crtl -> outgoing_args_size || crtl -> calls_eh_return || ! TARGET_PROLOGUE_EPILOGUE ) return false ; for ( regno = 0 ; regno < reglimit ; regno ++ ) if ( cris_reg_saved_in_regsave_area ( regno ) ) return false ; return true ; } </s>

Return ! = 0 if the return sequence for the current function is short , like `` ret '' or `` jump [ sp+ ] '' . Prior to reloading , we ca n't tell how many registers must be saved , so return 0 then .


<s> enum aarch64_symbol_type aarch64_classify_symbol ( rtx x , HOST_WIDE_INT offset ) { if ( GET_CODE ( x ) == LABEL_REF ) { switch ( aarch64_cmodel ) { case AARCH64_CMODEL_LARGE : return SYMBOL_FORCE_TO_MEM ; case AARCH64_CMODEL_TINY_PIC : case AARCH64_CMODEL_TINY : return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL_SPIC : case AARCH64_CMODEL_SMALL_PIC : case AARCH64_CMODEL_SMALL : return SYMBOL_SMALL_ABSOLUTE ; default : gcc_unreachable ( ) ; } } if ( GET_CODE ( x ) == SYMBOL_REF ) { if ( aarch64_tls_symbol_p ( x ) ) return aarch64_classify_tls_symbol ( x ) ; switch ( aarch64_cmodel ) { case AARCH64_CMODEL_TINY : if ( ( SYMBOL_REF_WEAK ( x ) && ! aarch64_symbol_binds_local_p ( x ) ) || ! IN_RANGE ( offset , - 1048575 , 1048575 ) ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL : if ( ( SYMBOL_REF_WEAK ( x ) && ! aarch64_symbol_binds_local_p ( x ) ) || ! IN_RANGE ( offset , HOST_WIDE_INT_C ( - 4294967263 ) , HOST_WIDE_INT_C ( 4294967264 ) ) ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_SMALL_ABSOLUTE ; case AARCH64_CMODEL_TINY_PIC : if ( ! aarch64_symbol_binds_local_p ( x ) ) return SYMBOL_TINY_GOT ; return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL_SPIC : case AARCH64_CMODEL_SMALL_PIC : if ( ! aarch64_symbol_binds_local_p ( x ) ) return ( aarch64_cmodel == AARCH64_CMODEL_SMALL_SPIC ? SYMBOL_SMALL_GOT_28K : SYMBOL_SMALL_GOT_4G ) ; return SYMBOL_SMALL_ABSOLUTE ; case AARCH64_CMODEL_LARGE : if ( ! aarch64_pcrelative_literal_loads && CONSTANT_POOL_ADDRESS_P ( x ) ) return SYMBOL_SMALL_ABSOLUTE ; else return SYMBOL_FORCE_TO_MEM ; default : gcc_unreachable ( ) ; } } return SYMBOL_FORCE_TO_MEM ; } </s>

Return the method that should be used to access SYMBOL_REF or LABEL_REF X .


<s> const MCExpr * X86_64MachoTargetObjectFile :: getTTypeGlobalReference ( const GlobalValue * GV , Mangler * Mang , MachineModuleInfo * MMI , unsigned Encoding , MCStreamer & Streamer ) const { if ( Encoding & ( DW_EH_PE_indirect | DW_EH_PE_pcrel ) ) { const MCSymbol * Sym = getSymbol ( * Mang , GV ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_GOTPCREL , getContext ( ) ) ; const MCExpr * Four = MCConstantExpr :: Create ( 4 , getContext ( ) ) ; return MCBinaryExpr :: CreateAdd ( Res , Four , getContext ( ) ) ; } return TargetLoweringObjectFileMachO :: getTTypeGlobalReference ( GV , Mang , MMI , Encoding , Streamer ) ; } </s>

The mach-o version of this method defaults to returning a stub reference .


<s> static bool arm_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { machine_mode mode ; if ( size == UNITS_PER_WORD && aligned_p ) { fputs ( "\t.word\t" , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; if ( NEED_GOT_RELOC && flag_pic && making_const_table && ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF ) ) { if ( ! arm_pic_data_is_text_relative || ( GET_CODE ( x ) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P ( x ) ) ) fputs ( "(GOT)" , asm_out_file ) ; else fputs ( "(GOTOFF)" , asm_out_file ) ; } fputc ( '\n' , asm_out_file ) ; return true ; } mode = GET_MODE ( x ) ; if ( arm_vector_mode_supported_p ( mode ) ) { int i , units ; gcc_assert ( GET_CODE ( x ) == CONST_VECTOR ) ; units = CONST_VECTOR_NUNITS ( x ) ; size = GET_MODE_UNIT_SIZE ( mode ) ; if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) for ( i = 0 ; i < units ; i ++ ) { rtx elt = CONST_VECTOR_ELT ( x , i ) ; assemble_integer ( elt , size , i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT , 1 ) ; } else for ( i = 0 ; i < units ; i ++ ) { rtx elt = CONST_VECTOR_ELT ( x , i ) ; assemble_real ( * CONST_DOUBLE_REAL_VALUE ( elt ) , GET_MODE_INNER ( mode ) , i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT ) ; } return true ; } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . The ARM version needs to handle word-sized values specially .


<s>
StringRef
getPassName
(
)
const
override
{
return
"WebAssembly Lower @llvm.global_dtors"
;
}
</s>

getPassName - Return a nice clean name for a pass .

WebAssembly
"WebAssembly Lower @llvm.global_dtors"


"%<builtin_return_address%> contains only 2 bytes"

Return contents of MEM at frame pointer + stack size + 1 ( +2 if 3-byte PC ) . This is return address of function .


<s> int nios2_label_align ( rtx label ) { int n = CODE_LABEL_NUMBER ( label ) ; if ( label_align && n >= min_labelno && n <= max_labelno ) return MAX ( label_align [ n - min_labelno ] , align_labels . levels [ 0 ] . log ) ; return align_labels . levels [ 0 ] . log ; } </s>

Implement LABEL_ALIGN , using the information gathered in nios2_reorg .


<s> static int ix86_set_reg_reg_cost ( machine_mode mode ) { unsigned int units = UNITS_PER_WORD ; switch ( GET_MODE_CLASS ( mode ) ) { default : break ; case MODE_CC : units = GET_MODE_SIZE ( CCmode ) ; break ; case MODE_FLOAT : if ( ( TARGET_SSE && mode == TFmode ) || ( TARGET_80387 && mode == XFmode ) || ( ( TARGET_80387 || TARGET_SSE2 ) && mode == DFmode ) || ( ( TARGET_80387 || TARGET_SSE ) && mode == SFmode ) ) units = GET_MODE_SIZE ( mode ) ; break ; case MODE_COMPLEX_FLOAT : if ( ( TARGET_SSE && mode == TCmode ) || ( TARGET_80387 && mode == XCmode ) || ( ( TARGET_80387 || TARGET_SSE2 ) && mode == DCmode ) || ( ( TARGET_80387 || TARGET_SSE ) && mode == SCmode ) ) units = GET_MODE_SIZE ( mode ) ; break ; case MODE_VECTOR_INT : case MODE_VECTOR_FLOAT : if ( ( TARGET_AVX512F && VALID_AVX512F_REG_MODE ( mode ) ) || ( TARGET_AVX && VALID_AVX256_REG_MODE ( mode ) ) || ( TARGET_SSE2 && VALID_SSE2_REG_MODE ( mode ) ) || ( TARGET_SSE && VALID_SSE_REG_MODE ( mode ) ) || ( ( TARGET_MMX || TARGET_MMX_WITH_SSE ) && VALID_MMX_REG_MODE ( mode ) ) ) units = GET_MODE_SIZE ( mode ) ; } return COSTS_N_INSNS ( CEIL ( GET_MODE_SIZE ( mode ) , units ) ) ; } </s>

Return the cost of moving between two registers of mode MODE .


<s> bool SystemZTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( AM . BaseGV ) return false ; if ( ! isInt < 20 > ( AM . BaseOffs ) ) return false ; return AM . Scale == 0 || AM . Scale == 1 ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> bool Emitter < CodeEmitter > :: runOnMachineFunction ( MachineFunction & MF ) { II = ( ( AlphaTargetMachine & ) MF . getTarget ( ) ) . getInstrInfo ( ) ; do { MCE . startFunction ( MF ) ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) emitBasicBlock ( * I ) ; } while ( MCE . finishFunction ( MF ) ) ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> void addPreEmitPass ( ) override { addPass ( createJ2DelaySlotFillerPass ( getJ2TargetMachine ( ) ) ) ; addPass ( createJ2ConstantIslandPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> unsigned WebAssemblyFastISel :: fastMaterializeAlloca ( const AllocaInst * AI ) { DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( AI ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { unsigned ResultReg = createResultReg ( Subtarget -> hasAddr64 ( ) ? & WebAssembly :: I64RegClass : & WebAssembly :: I32RegClass ) ; unsigned Opc = Subtarget -> hasAddr64 ( ) ? WebAssembly :: COPY_I64 : WebAssembly :: COPY_I32 ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addFrameIndex ( SI -> second ) ; return ResultReg ; } return 0 ; } </s>

Emit an alloca address in a register using target-specific logic .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LiveIntervals > ( ) ; AU . addPreserved < LiveIntervals > ( ) ; AU . addPreserved < SlotIndexes > ( ) ; AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool MSP430AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { return true ; } printSrcMemOperand ( MI , OpNo , O ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> TargetIRAnalysis WebAssemblyTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( Function & F ) { return TargetTransformInfo ( WebAssemblyTTIImpl ( this , F ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


<s>
bool
X86AsmParser
::
ParseDirective
(
AsmToken
DirectiveID
)
{
StringRef
IDVal
=
DirectiveID
.
getIdentifier
(
)
;
if
(
IDVal
==
".word"
)
return
ParseDirectiveWord
(
2
,
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
.
startswith
(
".code"
)
)
return
ParseDirectiveCode
(
IDVal
,
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
.
startswith
(
".att_syntax"
)
)
{
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.att_syntax noprefix' is not "
"supported: registers must have a "
"'%' prefix in .att_syntax"
)
;
}
getParser
(
)
.
setAssemblerDialect
(
0
)
;
return
false
;
}
else
if
(
IDVal
.
startswith
(
".intel_syntax"
)
)
{
getParser
(
)
.
setAssemblerDialect
(
1
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.intel_syntax prefix' is not "
"supported: registers must not have "
"a '%' prefix in .intel_syntax"
)
;
}
return
false
;
}
return
true
;
}
</s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


"Pseudo opcode found in emitInstruction()"

Targets should implement this to emit instructions .


<s> bool ARMTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty , unsigned AS ) const { EVT VT = getValueType ( Ty , true ) ; if ( ! isLegalAddressImmediate ( AM . BaseOffs , VT , Subtarget ) ) return false ; if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( Subtarget -> isThumb1Only ( ) ) return false ; default : if ( AM . BaseOffs ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( Subtarget -> isThumb2 ( ) ) return isLegalT2ScaledAddressingMode ( AM , VT ) ; int Scale = AM . Scale ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case MVT :: i1 : case MVT :: i8 : case MVT :: i32 : if ( Scale < 0 ) Scale = - Scale ; if ( Scale == 1 ) return true ; return isPowerOf2_32 ( Scale & ~ 1 ) ; case MVT :: i16 : case MVT :: i64 : if ( ( ( unsigned ) AM . HasBaseReg + Scale ) <= 2 ) return true ; return false ; case MVT :: isVoid : if ( Scale & 1 ) return false ; return isPowerOf2_32 ( Scale ) ; } } return true ; } </s>


<s> X86Subtarget :: X86Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const X86TargetMachine & TM , unsigned StackAlignOverride ) : X86GenSubtargetInfo ( TT , CPU , FS ) , X86ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , TSInfo ( * TM . getDataLayout ( ) ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsDown , getStackAlignment ( ) , is64Bit ( ) ? - 8 : - 4 ) { if ( TM . getRelocationModel ( ) == Reloc :: Static ) { setPICStyle ( PICStyles :: None ) ; } else if ( is64Bit ( ) ) { setPICStyle ( PICStyles :: RIPRel ) ; } else if ( isTargetCOFF ( ) ) { setPICStyle ( PICStyles :: None ) ; } else if ( isTargetDarwin ( ) ) { if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( TM . getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( isTargetELF ( ) ) { setPICStyle ( PICStyles :: GOT ) ; } } </s>

This constructor initializes the data members to match that of the specified triple .


<s> void AMDGPUPassConfig :: addIRPasses ( ) { disablePass ( & StackMapLivenessID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & PatchableFunctionID ) ; addPass ( createAMDGPULowerIntrinsicsPass ( ) ) ; addPass ( createAMDGPUAlwaysInlinePass ( ) ) ; addPass ( createAlwaysInlinerLegacyPass ( ) ) ; addPass ( createBarrierNoopPass ( ) ) ; const AMDGPUTargetMachine & TM = getAMDGPUTargetMachine ( ) ; if ( TM . getTargetTriple ( ) . getArch ( ) == Triple :: amdgcn ) { addPass ( createAMDGPUCodeGenPreparePass ( static_cast < const GCNTargetMachine * > ( & TM ) ) ) ; } addPass ( createAMDGPUOpenCLImageTypeLoweringPass ( ) ) ; if ( TM . getOptLevel ( ) > CodeGenOpt :: None ) { addPass ( createInferAddressSpacesPass ( ) ) ; addPass ( createAMDGPUPromoteAlloca ( & TM ) ) ; if ( EnableSROA ) addPass ( createSROAPass ( ) ) ; addStraightLineScalarOptimizationPasses ( ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addEarlyCSEOrGVNPass ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU


<s> void thumb2_expand_return ( bool simple_return ) { int i , num_regs ; unsigned long saved_regs_mask ; arm_stack_offsets * offsets ; offsets = arm_get_frame_offsets ( ) ; saved_regs_mask = offsets -> saved_regs_mask ; for ( i = 0 , num_regs = 0 ; i <= LAST_ARM_REGNUM ; i ++ ) if ( saved_regs_mask & ( 1 << i ) ) num_regs ++ ; if ( ! simple_return && saved_regs_mask ) { if ( num_regs == 1 ) { rtx par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( 2 ) ) ; rtx reg = gen_rtx_REG ( SImode , PC_REGNUM ) ; rtx addr = gen_rtx_MEM ( SImode , gen_rtx_POST_INC ( SImode , stack_pointer_rtx ) ) ; set_mem_alias_set ( addr , get_frame_alias_set ( ) ) ; XVECEXP ( par , 0 , 0 ) = ret_rtx ; XVECEXP ( par , 0 , 1 ) = gen_rtx_SET ( reg , addr ) ; RTX_FRAME_RELATED_P ( XVECEXP ( par , 0 , 1 ) ) = 1 ; emit_jump_insn ( par ) ; } else { saved_regs_mask &= ~ ( 1 << LR_REGNUM ) ; saved_regs_mask |= ( 1 << PC_REGNUM ) ; arm_emit_multi_reg_pop ( saved_regs_mask ) ; } } else { emit_jump_insn ( simple_return_rtx ) ; } } </s>


<s> const uint32_t * F2003fRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return CSR_NoRegs_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; AU . addRequired < ScalarEvolutionWrapperPass > ( ) ; } </s>


<s> bool HexagonAsmParser :: isLabel ( AsmToken & Token ) { MCAsmLexer & Lexer = getLexer ( ) ; AsmToken const & Second = Lexer . getTok ( ) ; AsmToken Third = Lexer . peekTok ( ) ; StringRef String = Token . getString ( ) ; if ( Token . is ( AsmToken :: TokenKind :: LCurly ) || Token . is ( AsmToken :: TokenKind :: RCurly ) ) return false ; if ( ! Token . is ( AsmToken :: TokenKind :: Identifier ) ) return true ; if ( ! matchRegister ( String . lower ( ) ) ) return true ; ( void ) Second ; assert ( Second . is ( AsmToken :: Colon ) ) ; StringRef Raw ( String . data ( ) , Third . getString ( ) . data ( ) - String . data ( ) + Third . getString ( ) . size ( ) ) ; std :: string Collapsed = Raw ; Collapsed . erase ( llvm :: remove_if ( Collapsed , isspace ) , Collapsed . end ( ) ) ; StringRef Whole = Collapsed ; std :: pair < StringRef , StringRef > DotSplit = Whole . split ( '.' ) ; if ( ! matchRegister ( DotSplit . first . lower ( ) ) ) return true ; return false ; } </s>

Returns true if the MachineInstr represents a label .


<s> static rtvec rs6000_const_vec ( machine_mode mode ) { int i , subparts ; rtvec v ; switch ( mode ) { case E_V1TImode : subparts = 1 ; break ; case E_V2DFmode : case E_V2DImode : subparts = 2 ; break ; case E_V4SFmode : case E_V4SImode : subparts = 4 ; break ; case E_V8HImode : subparts = 8 ; break ; case E_V16QImode : subparts = 16 ; break ; default : gcc_unreachable ( ) ; } v = rtvec_alloc ( subparts ) ; for ( i = 0 ; i < subparts / 2 ; ++ i ) RTVEC_ELT ( v , i ) = gen_rtx_CONST_INT ( DImode , i + subparts / 2 ) ; for ( i = subparts / 2 ; i < subparts ; ++ i ) RTVEC_ELT ( v , i ) = gen_rtx_CONST_INT ( DImode , i - subparts / 2 ) ; return v ; } </s>

Generate a vector of constants to permute MODE for a little-endian storage operation by swapping the two halves of a vector .


<s>
static
void
rs6000_define_or_undefine_macro
(
bool
define_p
,
const
char
*
name
)
{
if
(
TARGET_DEBUG_BUILTIN
||
TARGET_DEBUG_TARGET
)
fprintf
(
stderr
,
"#%s %s\n"
,
(
define_p
)
"define"
:
"undef"
,
name
)
;
if
(
define_p
)
cpp_define
(
parse_in
,
name
)
;
else
cpp_undef
(
parse_in
,
name
)
;
}
</s>


<s> bool aarch64_float_const_representable_p ( rtx x ) { int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1 ; int exponent ; unsigned HOST_WIDE_INT mantissa , mask ; REAL_VALUE_TYPE r , m ; bool fail ; if ( ! CONST_DOUBLE_P ( x ) ) return false ; if ( GET_MODE ( x ) == VOIDmode || GET_MODE ( x ) == HFmode ) return false ; r = * CONST_DOUBLE_REAL_VALUE ( x ) ; if ( REAL_VALUE_ISINF ( r ) || REAL_VALUE_ISNAN ( r ) || REAL_VALUE_MINUS_ZERO ( r ) ) return false ; r = real_value_abs ( & r ) ; exponent = REAL_EXP ( & r ) ; real_ldexp ( & m , & r , point_pos - exponent ) ; wide_int w = real_to_integer ( & m , & fail , HOST_BITS_PER_WIDE_INT * 2 ) ; if ( w . elt ( 0 ) != 0 ) return false ; mantissa = w . elt ( 1 ) ; point_pos -= HOST_BITS_PER_WIDE_INT ; mask = ( ( unsigned HOST_WIDE_INT ) 1 << ( point_pos - 5 ) ) - 1 ; if ( ( mantissa & mask ) != 0 ) return false ; mantissa >>= point_pos - 5 ; if ( mantissa == 0 ) return false ; mantissa &= ~ ( 1 << 4 ) ; gcc_assert ( mantissa <= 15 ) ; exponent = 5 - exponent ; return ( exponent >= 0 && exponent <= 7 ) ; } </s>

Return true iff X can be represented by a quarter-precision floating point immediate operand X . Note , we can not represent 0.0 .


<s> std :: unique_ptr < MCObjectWriter > AVRAsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { return createAVRELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI ( OSType ) ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


"extracode instruction should be prefixed with EXTEND"

"instruction prefixed with EXTEND is not an extracode"

"memory address must be an immediate in the range "

"IO channel address must be an immediate in the "

"address must be an immediate in the range [0, 4095] or a symbol"

"bank number must be an immediate in the range [0, 35]"

"operand must be an immediate in the range [0, 32767] or a symbol"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> int riscv_address_insns ( rtx x , machine_mode mode , bool might_split_p ) { struct riscv_address_info addr ; int n = 1 ; if ( ! riscv_classify_address ( & addr , x , mode , false ) ) return 0 ; if ( mode != BLKmode && might_split_p ) n += ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; if ( addr . type == ADDRESS_LO_SUM ) n += riscv_symbol_insns ( addr . symbol_type ) - 1 ; return n ; } </s>

Return the number of instructions needed to load or store a value of mode MODE at address X . Return 0 if X is n't valid for MODE . Assume that multiword moves may need to be split into word moves if MIGHT_SPLIT_P , otherwise assume that a single load or store is enough .


<s>
static
void
dump_target_flag_bits
(
const
int
flags
)
{
if
(
flags
&
MASK_64BIT
)
fprintf
(
stderr
,
"64BIT "
)
;
if
(
flags
&
MASK_APP_REGS
)
fprintf
(
stderr
,
"APP_REGS "
)
;
if
(
flags
&
MASK_FASTER_STRUCTS
)
fprintf
(
stderr
,
"FASTER_STRUCTS "
)
;
if
(
flags
&
MASK_FLAT
)
fprintf
(
stderr
,
"FLAT "
)
;
if
(
flags
&
MASK_FMAF
)
fprintf
(
stderr
,
"FMAF "
)
;
if
(
flags
&
MASK_FPU
)
fprintf
(
stderr
,
"FPU "
)
;
if
(
flags
&
MASK_HARD_QUAD
)
fprintf
(
stderr
,
"HARD_QUAD "
)
;
if
(
flags
&
MASK_POPC
)
fprintf
(
stderr
,
"POPC "
)
;
if
(
flags
&
MASK_PTR64
)
fprintf
(
stderr
,
"PTR64 "
)
;
if
(
flags
&
MASK_STACK_BIAS
)
fprintf
(
stderr
,
"STACK_BIAS "
)
;
if
(
flags
&
MASK_UNALIGNED_DOUBLES
)
fprintf
(
stderr
,
"UNALIGNED_DOUBLES "
)
;
if
(
flags
&
MASK_V8PLUS
)
fprintf
(
stderr
,
"V8PLUS "
)
;
if
(
flags
&
MASK_VIS
)
fprintf
(
stderr
,
"VIS "
)
;
if
(
flags
&
MASK_VIS2
)
fprintf
(
stderr
,
"VIS2 "
)
;
if
(
flags
&
MASK_VIS3
)
fprintf
(
stderr
,
"VIS3 "
)
;
if
(
flags
&
MASK_VIS4
)
fprintf
(
stderr
,
"VIS4 "
)
;
if
(
flags
&
MASK_CBCOND
)
fprintf
(
stderr
,
"CBCOND "
)
;
if
(
flags
&
MASK_DEPRECATED_V8_INSNS
)
fprintf
(
stderr
,
"DEPRECATED_V8_INSNS "
)
;
if
(
flags
&
MASK_SPARCLET
)
fprintf
(
stderr
,
"SPARCLET "
)
;
if
(
flags
&
MASK_SPARCLITE
)
fprintf
(
stderr
,
"SPARCLITE "
)
;
if
(
flags
&
MASK_V8
)
fprintf
(
stderr
,
"V8 "
)
;
if
(
flags
&
MASK_V9
)
fprintf
(
stderr
,
"V9 "
)
;
}
</s>

sparc
"64BIT "
"APP_REGS "
"FASTER_STRUCTS "
"FLAT "
"FMAF "
"FPU "
"HARD_QUAD "
"POPC "
"PTR64 "
"STACK_BIAS "
"UNALIGNED_DOUBLES "
"V8PLUS "
"VIS "
"VIS2 "
"VIS3 "
"VIS4 "
"CBCOND "
"DEPRECATED_V8_INSNS "
"SPARCLET "
"SPARCLITE "
"V8 "
"V9 "


"  Skipping pass: no machine model present.\n"

runOnMachineFunction - Emit the function body .


<s>
const
char
*
output_fp_compare
(
rtx_insn
*
insn
,
rtx
*
operands
,
bool
eflags_p
,
bool
unordered_p
)
{
rtx
*
xops
=
eflags_p
&
operands
[
0
]
:
&
operands
[
1
]
;
bool
stack_top_dies
;
static
char
buf
[
40
]
;
const
char
*
p
;
gcc_assert
(
STACK_TOP_P
(
xops
[
0
]
)
)
;
stack_top_dies
=
find_regno_note
(
insn
,
REG_DEAD
,
FIRST_STACK_REG
)
;
if
(
eflags_p
)
{
p
=
unordered_p
"fucomi"
:
"fcomi"
;
strcpy
(
buf
,
p
)
;
p
=
"p\t{%y1, %0|%0, %y1}"
;
strcat
(
buf
,
p
+
!
stack_top_dies
)
;
return
buf
;
}
if
(
STACK_REG_P
(
xops
[
1
]
)
&&
stack_top_dies
&&
find_regno_note
(
insn
,
REG_DEAD
,
FIRST_STACK_REG
+
1
)
)
{
gcc_assert
(
REGNO
(
xops
[
1
]
)
==
FIRST_STACK_REG
+
1
)
;
p
=
unordered_p
"fucompp"
:
"fcompp"
;
strcpy
(
buf
,
p
)
;
}
else
if
(
const0_operand
(
xops
[
1
]
,
VOIDmode
)
)
{
gcc_assert
(
!
unordered_p
)
;
strcpy
(
buf
,
"ftst"
)
;
}
else
{
if
(
GET_MODE_CLASS
(
GET_MODE
(
xops
[
1
]
)
)
==
MODE_INT
)
{
gcc_assert
(
!
unordered_p
)
;
p
=
"ficom"
;
}
else
p
=
unordered_p
"fucom"
:
"fcom"
;
strcpy
(
buf
,
p
)
;
p
=
"p%Z2\t%y2"
;
strcat
(
buf
,
p
+
!
stack_top_dies
)
;
}
output_asm_insn
(
buf
,
operands
)
;
return
"fnstsw\t%0"
;
}
</s>

Output code for INSN to compare OPERANDS . EFLAGS_P is 1 when fcomi should be used and 2 when fnstsw should be used . UNORDERED_P is true when fucom should be used .


<s> uint64_t getReturnSaveOffset ( ) const { return ReturnSaveOffset ; } </s>

getReturnSaveOffset - Return the previous frame offset to save the return address .


<s> unsigned getScalarizationOverhead ( Type * Ty , bool Insert , bool Extract ) { return 0 ; } </s>

Estimate the overhead of scalarizing an instruction .


<s> void SITargetLowering :: AdjustInstrPostInstrSelection ( MachineInstr * MI , SDNode * Node ) const { const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( getTargetMachine ( ) . getInstrInfo ( ) ) ; if ( ! TII -> isMIMG ( MI -> getOpcode ( ) ) ) return ; unsigned VReg = MI -> getOperand ( 0 ) . getReg ( ) ; unsigned Writemask = MI -> getOperand ( 1 ) . getImm ( ) ; unsigned BitsSet = 0 ; for ( unsigned i = 0 ; i < 4 ; ++ i ) BitsSet += Writemask & ( 1 << i ) ? 1 : 0 ; const TargetRegisterClass * RC ; switch ( BitsSet ) { default : return ; case 1 : RC = & AMDGPU :: VReg_32RegClass ; break ; case 2 : RC = & AMDGPU :: VReg_64RegClass ; break ; case 3 : RC = & AMDGPU :: VReg_96RegClass ; break ; } unsigned NewOpcode = TII -> getMaskedMIMGOp ( MI -> getOpcode ( ) , BitsSet ) ; MI -> setDesc ( TII -> get ( NewOpcode ) ) ; MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; MRI . setRegClass ( VReg , RC ) ; } </s>

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


<s> static bool mips_direct_save_slot_move_p ( unsigned int regno , rtx mem , bool load_p ) { if ( TARGET_MIPS16 && ! load_p && regno == RETURN_ADDR_REGNUM ) return false ; return mips_secondary_reload_class ( REGNO_REG_CLASS ( regno ) , GET_MODE ( mem ) , mem , load_p ) == NO_REGS ; } </s>

Return true if a move between register REGNO and its save slot ( MEM ) can be done in a single move . LOAD_P is true if we are loading from the slot , false if we are storing to it .


<s> const ARM64Subtarget * getSubtargetImpl ( ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> void MipsSEInstrInfo :: adjustStackPtr ( unsigned SP , int64_t Amount , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const MipsSubtarget & STI = Subtarget ; DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned ADDu = STI . isABI_N64 ( ) ? Mips :: DADDu : Mips :: ADDu ; unsigned ADDiu = STI . isABI_N64 ( ) ? Mips :: DADDiu : Mips :: ADDiu ; if ( isInt < 16 > ( Amount ) ) BuildMI ( MBB , I , DL , get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; else { unsigned Reg = loadImmediate ( Amount , MBB , I , DL , nullptr ) ; BuildMI ( MBB , I , DL , get ( ADDu ) , SP ) . addReg ( SP ) . addReg ( Reg , RegState :: Kill ) ; } } </s>

Mips Mips Mips Mips::DADDu Mips::ADDu Mips::DADDiu Mips::ADDiu 16


<s> static bool is_va_list_char_pointer ( tree type ) { tree canonic ; if ( ! TARGET_64BIT ) return true ; canonic = ix86_canonical_va_list_type ( type ) ; return ( canonic == ms_va_list_type_node || ( ix86_abi == MS_ABI && canonic == va_list_type_node ) ) ; } </s>

Checks if TYPE is of kind va_list char * .


<s> static rtx function_arg_vector_value ( int size , enum machine_mode base_mode , int regno ) { unsigned short base_mode_size = GET_MODE_SIZE ( base_mode ) ; int nregs = size / base_mode_size , i ; rtx regs ; regs = gen_rtx_PARALLEL ( BLKmode , rtvec_alloc ( nregs ) ) ; for ( i = 0 ; i < nregs ; i ++ ) { XVECEXP ( regs , 0 , i ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( base_mode , regno ) , GEN_INT ( base_mode_size * i ) ) ; regno += base_mode_size / 4 ; } return regs ; } </s>

Used by function_arg and sparc_function_value_1 to implement the conventions for passing and returning BLKmode vectors . Return an expression valid as a return value for the FUNCTION_ARG and TARGET_FUNCTION_VALUE . SIZE is the size in bytes of the vector . REGNO is the FP hard register the vector will be passed in .


<s> unsigned HexagonInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case Hexagon :: S2_storerb_io : case Hexagon :: S2_storerh_io : case Hexagon :: S2_storeri_io : case Hexagon :: S2_storerd_io : case Hexagon :: V6_vS32b_ai : case Hexagon :: V6_vS32Ub_ai : case Hexagon :: STriw_pred : case Hexagon :: STriw_ctr : case Hexagon :: PS_vstorerq_ai : case Hexagon :: PS_vstorerw_ai : { const MachineOperand & OpFI = MI . getOperand ( 0 ) ; if ( ! OpFI . isFI ( ) ) return 0 ; const MachineOperand & OpOff = MI . getOperand ( 1 ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != 0 ) return 0 ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( 2 ) . getReg ( ) ; } case Hexagon :: S2_pstorerbt_io : case Hexagon :: S2_pstorerbf_io : case Hexagon :: S2_pstorerht_io : case Hexagon :: S2_pstorerhf_io : case Hexagon :: S2_pstorerit_io : case Hexagon :: S2_pstorerif_io : case Hexagon :: S2_pstorerdt_io : case Hexagon :: S2_pstorerdf_io : { const MachineOperand & OpFI = MI . getOperand ( 1 ) ; if ( ! OpFI . isFI ( ) ) return 0 ; const MachineOperand & OpOff = MI . getOperand ( 2 ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != 0 ) return 0 ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( 3 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> static unsigned int pa_section_type_flags ( tree decl , const char * name , int reloc ) { unsigned int flags ; flags = default_section_type_flags ( decl , name , reloc ) ; if ( strcmp ( name , ".data.rel.ro" ) == 0 || strcmp ( name , ".data.rel.ro.local" ) == 0 ) flags |= SECTION_WRITE | SECTION_RELRO ; return flags ; } </s>


<s> static bool already_warned ( tree fndecl ) { struct decl_chain * warned ; for ( warned = warned_decls ; warned != NULL ; warned = warned -> next ) if ( warned -> fndecl == fndecl ) return true ; return false ; } </s>

Returns TRUE if FNDECL is on our list of warned about decls .


<s>
void
TMS320C64XInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
const
bool
destGPR
=
TMS320C64X
::
GPRegsRegClass
.
contains
(
DestReg
)
;
const
bool
srcGPR
=
TMS320C64X
::
GPRegsRegClass
.
contains
(
SrcReg
)
;
if
(
destGPR
&&
srcGPR
)
{
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
I
,
DL
,
get
(
TMS320C64X
::
mv
)
,
DestReg
)
;
MIB
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
addDefaultPred
(
MIB
)
;
return
;
}
llvm_unreachable
(
"Can not copy physical registers!"
)
;
}
</s>


<s> static void aarch64_expand_sve_const_vector ( rtx dest , rtx src ) { machine_mode mode = GET_MODE ( src ) ; unsigned int npatterns = CONST_VECTOR_NPATTERNS ( src ) ; unsigned int nelts_per_pattern = CONST_VECTOR_NELTS_PER_PATTERN ( src ) ; gcc_assert ( npatterns > 1 ) ; if ( nelts_per_pattern == 1 ) { scalar_int_mode int_mode ; if ( BYTES_BIG_ENDIAN ) int_mode = TImode ; else { unsigned int int_bits = GET_MODE_UNIT_BITSIZE ( mode ) * npatterns ; gcc_assert ( int_bits <= 128 ) ; int_mode = int_mode_for_size ( int_bits , 0 ) . require ( ) ; } rtx int_value = simplify_gen_subreg ( int_mode , src , mode , 0 ) ; if ( int_value && aarch64_expand_sve_widened_duplicate ( dest , int_mode , int_value ) ) return ; } rtx_vector_builder builder ; auto_vec < rtx , 16 > vectors ( npatterns ) ; for ( unsigned int i = 0 ; i < npatterns ; ++ i ) { builder . new_vector ( mode , 1 , nelts_per_pattern ) ; for ( unsigned int j = 0 ; j < nelts_per_pattern ; ++ j ) builder . quick_push ( CONST_VECTOR_ELT ( src , i + j * npatterns ) ) ; vectors . quick_push ( force_reg ( mode , builder . build ( ) ) ) ; } while ( npatterns > 1 ) { npatterns /= 2 ; for ( unsigned int i = 0 ; i < npatterns ; ++ i ) { rtx tmp = ( npatterns == 1 ? dest : gen_reg_rtx ( mode ) ) ; rtvec v = gen_rtvec ( 2 , vectors [ i ] , vectors [ i + npatterns ] ) ; emit_set_insn ( tmp , gen_rtx_UNSPEC ( mode , v , UNSPEC_ZIP1 ) ) ; vectors [ i ] = tmp ; } } gcc_assert ( vectors [ 0 ] == dest ) ; } </s>

Expand a move of general CONST_VECTOR SRC into DEST , given that it is n't a simple duplicate or series .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> SDValue HexagonTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , DebugLoc dl , SelectionDAG & DAG ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_Hexagon ) ; if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( 1 ) ; } if ( Flag . getNode ( ) ) return DAG . getNode ( HexagonISD :: RET_FLAG , dl , MVT :: Other , Chain , Flag ) ; return DAG . getNode ( HexagonISD :: RET_FLAG , dl , MVT :: Other , Chain ) ; } </s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


"Constant Island pass failed to converge!"

"Branch Fix Up pass failed to converge!"


<s> bool R600TargetLowering :: isZero ( SDValue Op ) const { if ( ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Op ) ) { return Cst -> isNullValue ( ) ; } else if ( ConstantFPSDNode * CstFP = dyn_cast < ConstantFPSDNode > ( Op ) ) { return CstFP -> isZero ( ) ; } else { return false ; } } </s>

Return true if the expression is a constant zero .


"Should use MaskedValueIsZero if you don't know whether Op"

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> rtx mmix_get_hard_reg_initial_val ( machine_mode mode , int regno ) { return get_hard_reg_initial_val ( mode , regno ) ; } </s>

Wrapper for get_hard_reg_initial_val since integrate.h is n't included from insn-emit.cc .


<s> rtx ix86_memtag_extract_tag ( rtx tagged_pointer , rtx target ) { rtx tag = expand_simple_binop ( Pmode , LSHIFTRT , tagged_pointer , GEN_INT ( IX86_HWASAN_SHIFT ) , target , 0 , OPTAB_DIRECT ) ; rtx ret = gen_reg_rtx ( QImode ) ; if ( ix86_lam_type == lam_u57 ) { unsigned HOST_WIDE_INT and_imm = ( HOST_WIDE_INT_1U << IX86_HWASAN_TAG_SIZE ) - 1 ; emit_insn ( gen_andqi3 ( ret , gen_lowpart ( QImode , tag ) , gen_int_mode ( and_imm , QImode ) ) ) ; } else emit_move_insn ( ret , gen_lowpart ( QImode , tag ) ) ; return ret ; } </s>


<s> void HSAILModuleInfo :: processModule ( const Module * M , const HSAILTargetMachine * mTM ) { mSTM = mTM -> getSubtargetImpl ( ) ; if ( mProcessed ) { return ; } mProcessed = true ; } </s>

Process entire module and collect debug info anchors .


<s> static int no_previous_def ( tree function_name ) { tree branch_island ; for ( branch_island = branch_island_list ; branch_island ; branch_island = TREE_CHAIN ( branch_island ) ) if ( function_name == BRANCH_ISLAND_FUNCTION_NAME ( branch_island ) ) return 0 ; return 1 ; } </s>

NO_PREVIOUS_DEF checks in the link list whether the function name is already there or not .


<s> bool SPIRVAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static int compute_total_frame_size ( void ) { int total_size = ( get_frame_size ( ) + tilepro_saved_regs_size ( ) + crtl -> outgoing_args_size + crtl -> args . pretend_args_size ) ; if ( ! tilepro_current_function_is_leaf ( ) || cfun -> calls_alloca ) { total_size += STACK_POINTER_OFFSET ; } return round_frame_size ( total_size ) ; } </s>


<s> bool Thumb1FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; bool isVarArg = AFI -> getArgRegsSaveSize ( ) > 0 ; DebugLoc DL = MI != MBB . end ( ) ? MI -> getDebugLoc ( ) : DebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , TII . get ( ARM :: tPOP ) ) ; AddDefaultPred ( MIB ) ; bool NeedsPop = false ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( Reg == ARM :: LR ) { if ( MBB . succ_empty ( ) ) { if ( isVarArg ) continue ; if ( ! STI . hasV5TOps ( ) ) continue ; Reg = ARM :: PC ; ( * MIB ) . setDesc ( TII . get ( ARM :: tPOP_RET ) ) ; if ( MI != MBB . end ( ) ) MIB . copyImplicitOps ( & * MI ) ; MI = MBB . erase ( MI ) ; } else continue ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; NeedsPop = true ; } if ( NeedsPop ) MBB . insert ( MI , & * MIB ) ; else MF . DeleteMachineInstr ( MIB ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> const uint16_t * DLXRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * ) const { const uint16_t t = 5 ; return & t ; } </s>


<s> SDValue MipsTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; unsigned Opc = N -> getOpcode ( ) ; switch ( Opc ) { default : break ; case ISD :: SDIVREM : case ISD :: UDIVREM : return performDivRemCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SELECT : return performSELECTCombine ( N , DAG , DCI , Subtarget ) ; case MipsISD :: CMovFP_F : case MipsISD :: CMovFP_T : return performCMovFPCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: AND : return performANDCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: OR : return performORCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: ADD : return performADDCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: AssertZext : return performAssertZextCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips Mips ISD::SDIVREM ISD::UDIVREM ISD::SELECT MipsISD::CMovFP_F MipsISD::CMovFP_T ISD::AND ISD::OR ISD::ADD ISD::AssertZext


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addPreserved < LiveIntervals > ( ) ; AU . addPreserved < SlotIndexes > ( ) ; AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> void btf_ext_output ( void ) { output_btfext_header ( ) ; output_btfext_core_sections ( ) ; bpf_core_sections = NULL ; } </s>


<s> ScheduleHazardRecognizer * ARMBaseInstrInfo :: CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II , const ScheduleDAG * DAG ) const { if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2 ( ) ) return ( ScheduleHazardRecognizer * ) new ARMHazardRecognizer ( II , * this , getRegisterInfo ( ) , Subtarget , DAG ) ; return TargetInstrInfo :: CreateTargetPostRAHazardRecognizer ( II , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for by non-scheduling passes .


<s> TargetPassConfig * R600TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new R600PassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> static bool bfin_legitimate_address_p ( machine_mode mode , rtx x , bool strict ) { switch ( GET_CODE ( x ) ) { case REG : if ( bfin_valid_reg_p ( REGNO ( x ) , strict , mode , MEM ) ) return true ; break ; case PLUS : if ( REG_P ( XEXP ( x , 0 ) ) && bfin_valid_reg_p ( REGNO ( XEXP ( x , 0 ) ) , strict , mode , PLUS ) && ( ( GET_CODE ( XEXP ( x , 1 ) ) == UNSPEC && mode == SImode ) || ( GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT && bfin_valid_add ( mode , INTVAL ( XEXP ( x , 1 ) ) ) ) ) ) return true ; break ; case POST_INC : case POST_DEC : if ( LEGITIMATE_MODE_FOR_AUTOINC_P ( mode ) && REG_P ( XEXP ( x , 0 ) ) && bfin_valid_reg_p ( REGNO ( XEXP ( x , 0 ) ) , strict , mode , POST_INC ) ) return true ; break ; case PRE_DEC : if ( LEGITIMATE_MODE_FOR_AUTOINC_P ( mode ) && XEXP ( x , 0 ) == stack_pointer_rtx && REG_P ( XEXP ( x , 0 ) ) && bfin_valid_reg_p ( REGNO ( XEXP ( x , 0 ) ) , strict , mode , PRE_DEC ) ) return true ; break ; default : break ; } return false ; } </s>

Recognize an RTL expression that is a valid memory address for an instruction . The MODE argument is the machine mode for the MEM expression that wants to use this address . Blackfin addressing modes are as follows : [ preg ] [ preg + imm16 ] B [ Preg + uimm15 ] W [ Preg + uimm16m2 ] [ Preg + uimm17m4 ] [ preg++ ] [ preg -- ] [ -- sp ]


<s> unsigned Z80InstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { auto TSFlags = MI . getDesc ( ) . TSFlags ; unsigned Size = 1 ; switch ( TSFlags >> Z80II :: ImmSizeShift & Z80II :: ImmSizeMask ) { case 2 : Size += Subtarget . is24Bit ( ) ; break ; case 3 : Size += Subtarget . is16Bit ( ) ; break ; } unsigned Prefix = TSFlags >> Z80II :: PrefixShift & Z80II :: PrefixMask ; bool HasPrefix ; if ( TSFlags & Z80II :: IndexedIndexPrefix ) Size += HasPrefix = isIndex ( MI . getOperand ( Prefix ) , getRegisterInfo ( ) ) ; else switch ( Prefix ) { case Z80II :: NoPrefix : HasPrefix = false ; break ; case Z80II :: CBPrefix : case Z80II :: DDPrefix : case Z80II :: EDPrefix : case Z80II :: FDPrefix : Size += 1 ; HasPrefix = true ; break ; case Z80II :: DDCBPrefix : case Z80II :: FDCBPrefix : Size += 2 ; HasPrefix = true ; break ; case Z80II :: AnyIndexPrefix : Size += HasPrefix = hasIndex ( MI , getRegisterInfo ( ) ) ; break ; } if ( TSFlags & Z80II :: HasImm ) { unsigned ImmSize = TSFlags >> Z80II :: ImmSizeShift & Z80II :: ImmSizeMask ; if ( ! ImmSize ) ImmSize = Subtarget . is24Bit ( ) ? 3 : 2 ; Size += ImmSize ; } if ( TSFlags & Z80II :: HasOff ) Size += HasPrefix ; return Size ; } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> static void s390_update_frame_layout ( void ) { int clobbered_regs [ 16 ] ; s390_register_info ( clobbered_regs ) ; regs_ever_live [ BASE_REGNUM ] = clobbered_regs [ BASE_REGNUM ] ; regs_ever_live [ RETURN_REGNUM ] = clobbered_regs [ RETURN_REGNUM ] ; regs_ever_live [ STACK_POINTER_REGNUM ] = clobbered_regs [ STACK_POINTER_REGNUM ] ; if ( cfun -> machine -> base_reg ) regs_ever_live [ REGNO ( cfun -> machine -> base_reg ) ] = 1 ; } </s>

Update frame layout . Recompute actual register save data based on current info and update regs_ever_live for the special registers . May be called multiple times , but may never cause * more * registers to be saved than s390_init_frame_layout allocated room for .


"use of %<long%> in AltiVec types is invalid for 64-bit code"

"use of %<long%> in AltiVec types is deprecated; use %<int%>"

"use of %<long long%> in AltiVec types is invalid"

"use of %<double%> in AltiVec types is invalid"

"use of %<long double%> in AltiVec types is invalid"

"use of boolean types in AltiVec types is invalid"

"use of %<complex%> in AltiVec types is invalid"

Handle the `` altivec '' attribute . The attribute may have arguments as follows : __attribute__ ( ( altivec ( vector__ ) ) ) __attribute__ ( ( altivec ( pixel__ ) ) ) ( always followed by 'unsigned short ' ) __attribute__ ( ( altivec ( bool__ ) ) ) ( always followed by 'unsigned ' ) and may appear more than once ( e.g. , 'vector bool char ' ) in a given declaration .


<s> static bool aarch64_evpc_rev_local ( struct expand_vec_perm_d * d ) { HOST_WIDE_INT diff ; unsigned int i , size , unspec ; machine_mode pred_mode ; if ( d -> vec_flags == VEC_SVE_PRED || ! d -> one_vector_p || ! d -> perm [ 0 ] . is_constant ( & diff ) || ! diff ) return false ; if ( d -> vec_flags & VEC_SVE_DATA ) size = ( diff + 1 ) * aarch64_sve_container_bits ( d -> vmode ) ; else size = ( diff + 1 ) * GET_MODE_UNIT_BITSIZE ( d -> vmode ) ; if ( size == 64 ) { unspec = UNSPEC_REV64 ; pred_mode = VNx2BImode ; } else if ( size == 32 ) { unspec = UNSPEC_REV32 ; pred_mode = VNx4BImode ; } else if ( size == 16 ) { unspec = UNSPEC_REV16 ; pred_mode = VNx8BImode ; } else return false ; unsigned int step = diff + 1 ; for ( i = 0 ; i < step ; ++ i ) if ( ! d -> perm . series_p ( i , step , diff - i , step ) ) return false ; if ( d -> testing_p ) return true ; if ( d -> vec_flags & VEC_SVE_DATA ) { rtx pred = aarch64_ptrue_reg ( pred_mode ) ; emit_insn ( gen_aarch64_sve_revbhw ( d -> vmode , pred_mode , d -> target , pred , d -> op0 ) ) ; return true ; } rtx src = gen_rtx_UNSPEC ( d -> vmode , gen_rtvec ( 1 , d -> op0 ) , unspec ) ; emit_set_insn ( d -> target , src ) ; return true ; } </s>

Recognize patterns for the REV { 64,32,16 } insns , which reverse elements within each 64-bit , 32-bit or 16-bit granule .


<s> static bool loongarch_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { return ( mode1 == mode2 || ( ! loongarch_mode_ok_for_mov_fmt_p ( mode1 ) && ! loongarch_mode_ok_for_mov_fmt_p ( mode2 ) ) ) ; } </s>


<s> unsigned BPFMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) return MRI . getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; assert ( MO . isExpr ( ) ) ; const MCExpr * Expr = MO . getExpr ( ) ; assert ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) ; if ( MI . getOpcode ( ) == BPF :: JAL ) Fixups . push_back ( MCFixup :: Create ( 0 , Expr , FK_SecRel_4 ) ) ; else if ( MI . getOpcode ( ) == BPF :: LD_imm64 ) Fixups . push_back ( MCFixup :: Create ( 0 , Expr , FK_SecRel_8 ) ) ; else Fixups . push_back ( MCFixup :: Create ( 0 , Expr , FK_PCRel_2 ) ) ; return 0 ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> static void mips_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; struct mips_arg_info info ; mips_get_arg_info ( & info , cum , mode , type , named ) ; if ( ! info . fpr_p ) cum -> gp_reg_found = true ; if ( cum -> arg_number < 2 && info . fpr_p ) cum -> fp_code += ( mode == SFmode ? 1 : 2 ) << ( cum -> arg_number * 2 ) ; if ( mips_abi != ABI_EABI || ! info . fpr_p ) cum -> num_gprs = info . reg_offset + info . reg_words ; else if ( info . reg_words > 0 ) cum -> num_fprs += MAX_FPRS_PER_FMT ; if ( info . stack_words > 0 ) cum -> stack_words = info . stack_offset + info . stack_words ; cum -> arg_number ++ ; } </s>


<s> bool RISCVTargetLowering :: isMulAddWithConstProfitable ( SDValue AddNode , SDValue ConstNode ) const { EVT VT = AddNode . getValueType ( ) ; if ( VT . isVector ( ) ) return true ; if ( VT . getScalarSizeInBits ( ) > Subtarget . getXLen ( ) ) return true ; ConstantSDNode * C1Node = cast < ConstantSDNode > ( AddNode . getOperand ( 1 ) ) ; ConstantSDNode * C2Node = cast < ConstantSDNode > ( ConstNode ) ; const APInt & C1 = C1Node -> getAPIntValue ( ) ; const APInt & C2 = C2Node -> getAPIntValue ( ) ; if ( C1 . isSignedIntN ( 12 ) && ! ( C1 * C2 ) . isSignedIntN ( 12 ) ) return false ; return true ; } </s>

Return true if it may be profitable to transform ( mul ( add x , c1 ) , c2 ) - > ( add ( mul x , c2 ) , c1 * c2 ) .


"Only optimizing constant comparisons so far"

optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare ; remove Compare if possible .


"rs6000_secondary_reload_inner:%d, type = %s\n"

Better tracing for rs6000_secondary_reload_inner .


<s> bool X86CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto DL = MF . getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned Idx = 0 ; for ( auto & Arg : F . getArgumentList ( ) ) { ArgInfo OrigArg ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArg , Idx + 1 , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs , ArrayRef < uint64_t > Offsets ) { MIRBuilder . buildSequence ( VRegs [ Idx ] , Regs , Offsets ) ; } ) ; Idx ++ ; } MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; FormalArgHandler Handler ( MIRBuilder , MRI , CC_X86 , DL ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> void loongarch_move_integer ( rtx temp , rtx dest , unsigned HOST_WIDE_INT value ) { struct loongarch_integer_op codes [ LARCH_MAX_INTEGER_OPS ] ; machine_mode mode ; unsigned int i , num_ops ; rtx x ; mode = GET_MODE ( dest ) ; num_ops = loongarch_build_integer ( codes , value ) ; x = GEN_INT ( codes [ 0 ] . value ) ; for ( i = 1 ; i < num_ops ; i ++ ) { if ( ! can_create_pseudo_p ( ) ) { emit_insn ( gen_rtx_SET ( temp , x ) ) ; x = temp ; } else x = force_reg ( mode , x ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , GEN_INT ( codes [ i - 1 ] . curr_value ) ) ; switch ( codes [ i ] . method ) { case METHOD_NORMAL : x = gen_rtx_fmt_ee ( codes [ i ] . code , mode , x , GEN_INT ( codes [ i ] . value ) ) ; break ; case METHOD_LU32I : gcc_assert ( mode == DImode ) ; x = gen_rtx_IOR ( DImode , gen_rtx_ZERO_EXTEND ( DImode , gen_rtx_SUBREG ( SImode , x , 0 ) ) , GEN_INT ( codes [ i ] . value ) ) ; break ; case METHOD_LU52I : gcc_assert ( mode == DImode ) ; x = gen_rtx_IOR ( DImode , gen_rtx_AND ( DImode , x , GEN_INT ( 0xfffffffffffff ) ) , GEN_INT ( codes [ i ] . value ) ) ; break ; default : gcc_unreachable ( ) ; } } emit_insn ( gen_rtx_SET ( dest , x ) ) ; } </s>

Load VALUE into DEST . TEMP is as for loongarch_force_temporary .


<s> rtx m68k_function_value ( const_tree valtype , const_tree func ATTRIBUTE_UNUSED ) { machine_mode mode ; mode = TYPE_MODE ( valtype ) ; switch ( mode ) { case E_SFmode : case E_DFmode : case E_XFmode : if ( TARGET_68881 ) return gen_rtx_REG ( mode , FP0_REG ) ; break ; default : break ; } if ( func && POINTER_TYPE_P ( TREE_TYPE ( TREE_TYPE ( func ) ) ) ) return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , A0_REG ) , const0_rtx ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , D0_REG ) , const0_rtx ) ) ) ; else if ( POINTER_TYPE_P ( valtype ) ) return gen_rtx_REG ( mode , A0_REG ) ; else return gen_rtx_REG ( mode , D0_REG ) ; } </s>

Location in which function value is returned . NOTE : Due to differences in ABIs , do n't call this function directly , use FUNCTION_VALUE instead .