<s> static rtx spu_legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED ) { rtx op0 , op1 ; if ( GET_CODE ( x ) == PLUS ) { op0 = XEXP ( x , 0 ) ; op1 = XEXP ( x , 1 ) ; if ( ALIGNED_SYMBOL_REF_P ( op0 ) ) { op0 = force_reg ( Pmode , op0 ) ; mark_reg_pointer ( op0 , 128 ) ; } else if ( GET_CODE ( op0 ) != REG ) op0 = force_reg ( Pmode , op0 ) ; if ( ALIGNED_SYMBOL_REF_P ( op1 ) ) { op1 = force_reg ( Pmode , op1 ) ; mark_reg_pointer ( op1 , 128 ) ; } else if ( GET_CODE ( op1 ) != REG ) op1 = force_reg ( Pmode , op1 ) ; x = gen_rtx_PLUS ( Pmode , op0 , op1 ) ; } return x ; } </s>

When the address is reg + const_int , force the const_int into a register .


<s> static machine_mode rs6000_promote_function_mode ( const_tree type ATTRIBUTE_UNUSED , machine_mode mode , int * punsignedp ATTRIBUTE_UNUSED , const_tree , int ) { PROMOTE_MODE ( mode , * punsignedp , type ) ; return mode ; } </s>

On rs6000 , function arguments are promoted , as are function return values .


<s> static void rs6000_split_logical_inner ( rtx dest , rtx op1 , rtx op2 , enum rtx_code code , machine_mode mode , bool complement_final_p , bool complement_op1_p , bool complement_op2_p ) { rtx bool_rtx ; if ( op2 && CONST_INT_P ( op2 ) && ( mode == SImode || ( mode == DImode && TARGET_POWERPC64 ) ) && ! complement_final_p && ! complement_op1_p && ! complement_op2_p ) { HOST_WIDE_INT mask = GET_MODE_MASK ( mode ) ; HOST_WIDE_INT value = INTVAL ( op2 ) & mask ; if ( code == AND ) { if ( value == 0 ) { emit_insn ( gen_rtx_SET ( dest , const0_rtx ) ) ; return ; } else if ( value == mask ) { if ( ! rtx_equal_p ( dest , op1 ) ) emit_insn ( gen_rtx_SET ( dest , op1 ) ) ; return ; } } else if ( code == IOR || code == XOR ) { if ( value == 0 ) { if ( ! rtx_equal_p ( dest , op1 ) ) emit_insn ( gen_rtx_SET ( dest , op1 ) ) ; return ; } } } if ( code == AND && mode == SImode && ! complement_final_p && ! complement_op1_p && ! complement_op2_p ) { emit_insn ( gen_andsi3 ( dest , op1 , op2 ) ) ; return ; } if ( complement_op1_p ) op1 = gen_rtx_NOT ( mode , op1 ) ; if ( complement_op2_p ) op2 = gen_rtx_NOT ( mode , op2 ) ; if ( ! complement_op1_p && complement_op2_p ) std :: swap ( op1 , op2 ) ; bool_rtx = ( ( code == NOT ) ? gen_rtx_NOT ( mode , op1 ) : gen_rtx_fmt_ee ( code , mode , op1 , op2 ) ) ; if ( complement_final_p ) bool_rtx = gen_rtx_NOT ( mode , bool_rtx ) ; emit_insn ( gen_rtx_SET ( dest , bool_rtx ) ) ; } </s>

Helper function for rs6000_split_logical to emit a logical instruction after spliting the operation to single GPR registers . DEST is the destination register . OP1 and OP2 are the input source registers . CODE is the base operation ( AND , IOR , XOR , NOT ) . MODE is the machine mode . If COMPLEMENT_FINAL_P is true , wrap the whole operation with NOT . If COMPLEMENT_OP1_P is true , wrap operand1 with NOT . If COMPLEMENT_OP2_P is true , wrap operand2 with NOT .


<s> static bool tilepro_function_value_regno_p ( const unsigned int regno ) { return regno < TILEPRO_NUM_RETURN_REGS ; } </s>


<s> bool SITargetLowering :: requiresUniformRegister ( MachineFunction & MF , const Value * V ) const { if ( const CallInst * CI = dyn_cast < CallInst > ( V ) ) { if ( CI -> isInlineAsm ( ) ) { const SIRegisterInfo * SIRI = Subtarget -> getRegisterInfo ( ) ; TargetLowering :: AsmOperandInfoVector TargetConstraints = ParseConstraints ( MF . getDataLayout ( ) , Subtarget -> getRegisterInfo ( ) , * CI ) ; for ( auto & TC : TargetConstraints ) { if ( TC . Type == InlineAsm :: isOutput ) { ComputeConstraintToUse ( TC , SDValue ( ) ) ; const TargetRegisterClass * RC = getRegForInlineAsmConstraint ( SIRI , TC . ConstraintCode , TC . ConstraintVT ) . second ; if ( RC && SIRI -> isSGPRClass ( RC ) ) return true ; } } } } SmallPtrSet < const Value * , 16 > Visited ; return hasCFUser ( V , Visited , Subtarget -> getWavefrontSize ( ) ) ; } </s>

Allows target to decide about the register class of the specific value that is live outside the defining block .


<s> static machine_mode rs6000_abi_word_mode ( void ) { return TARGET_32BIT ? SImode : DImode ; } </s>

The mode the ABI uses for a word . This is not the same as word_mode for -m32 -mpowerpc64 . This is used to implement various target hooks .


<s> bool arc_epilogue_uses ( int regno ) { if ( regno == arc_tp_regno ) return true ; if ( reload_completed ) { if ( ARC_INTERRUPT_P ( cfun -> machine -> fn_type ) ) { if ( ! fixed_regs [ regno ] ) return true ; return ( ( regno == arc_return_address_regs [ cfun -> machine -> fn_type ] ) || ( regno == RETURN_ADDR_REGNUM ) ) ; } else return regno == RETURN_ADDR_REGNUM ; } else return regno == arc_return_address_regs [ arc_compute_function_type ( cfun ) ] ; } </s>

Implement EPILOGUE__USES . Return true if REGNO should be added to the deemed uses of the epilogue . We use the return address arc_return_address_regs [ arc_compute_function_type ( cfun ) ] . But also , we have to make sure all the register restore instructions are known to be live in interrupt functions , plus the blink register if it is clobbered by the isr .


<s>
StringRef
getPassName
(
)
const
override
{
return
"TVM Replace Physical Registers"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> rtx aarch64_simd_vect_par_cnst_half ( machine_mode mode , int nunits , bool high ) { rtvec v = rtvec_alloc ( nunits / 2 ) ; int high_base = nunits / 2 ; int low_base = 0 ; int base ; rtx t1 ; int i ; if ( BYTES_BIG_ENDIAN ) base = high ? low_base : high_base ; else base = high ? high_base : low_base ; for ( i = 0 ; i < nunits / 2 ; i ++ ) RTVEC_ELT ( v , i ) = GEN_INT ( base + i ) ; t1 = gen_rtx_PARALLEL ( mode , v ) ; return t1 ; } </s>

Construct and return a PARALLEL RTX vector with elements numbering the lanes of either the high ( HIGH == TRUE ) or low ( HIGH == FALSE ) half of the vector - from the perspective of the architecture . This does not line up with GCC 's perspective on lane numbers , so we end up with different masks depending on our target endian-ness . The diagram below may help . We must draw the distinction when building masks which select one half of the vector . An instruction selecting architectural low-lanes for a big-endian target , must be described using a mask selecting GCC high-lanes . Big-Endian Little-EndianGCC 0 1 2 3 3 2 1 0 | x | x | x | x | | x | x | x | x |Architecture 3 2 1 0 3 2 1 0Low Mask : { 2 , 3 } { 0 , 1 } High Mask : { 0 , 1 } { 2 , 3 }


<s> static tree make_dispatcher_decl ( const tree decl ) { tree func_decl ; char * func_name ; tree fn_type , func_type ; bool is_uniq = false ; if ( TREE_PUBLIC ( decl ) == 0 ) is_uniq = true ; func_name = make_name ( decl , "ifunc" , is_uniq ) ; fn_type = TREE_TYPE ( decl ) ; func_type = build_function_type ( TREE_TYPE ( fn_type ) , TYPE_ARG_TYPES ( fn_type ) ) ; func_decl = build_fn_decl ( func_name , func_type ) ; XDELETEVEC ( func_name ) ; TREE_USED ( func_decl ) = 1 ; DECL_CONTEXT ( func_decl ) = NULL_TREE ; DECL_INITIAL ( func_decl ) = error_mark_node ; DECL_ARTIFICIAL ( func_decl ) = 1 ; DECL_EXTERNAL ( func_decl ) = 1 ; TREE_PUBLIC ( func_decl ) = 1 ; return func_decl ; } </s>

Make a dispatcher declaration for the multi-versioned function DECL . Calls to DECL function will be replaced with calls to the dispatcher by the front-end . Return the decl created .


<s> bool AMDGPUPeepholeOpt :: doInitialization ( Module & M ) { return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> bool AArch64TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( AM . BaseGV ) return false ; if ( AM . HasBaseReg && AM . BaseOffs && AM . Scale ) return false ; uint64_t NumBytes = 0 ; if ( Ty -> isSized ( ) ) { uint64_t NumBits = DL . getTypeSizeInBits ( Ty ) ; NumBytes = NumBits / 8 ; if ( ! isPowerOf2_64 ( NumBits ) ) NumBytes = 0 ; } if ( ! AM . Scale ) { int64_t Offset = AM . BaseOffs ; if ( isInt < 9 > ( Offset ) ) return true ; unsigned shift = Log2_64 ( NumBytes ) ; if ( NumBytes && Offset > 0 && ( Offset / NumBytes ) <= ( 1LL << 12 ) - 1 && ( Offset >> shift ) << shift == Offset ) return true ; return false ; } return AM . Scale == 1 || ( AM . Scale > 0 && ( uint64_t ) AM . Scale == NumBytes ) ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> bool PPCQPXLoadSplat :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; bool MadeChange = false ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; for ( auto MFI = MF . begin ( ) , MFIE = MF . end ( ) ; MFI != MFIE ; ++ MFI ) { MachineBasicBlock * MBB = & * MFI ; SmallVector < MachineInstr * , 4 > Splats ; for ( auto MBBI = MBB -> rbegin ( ) ; MBBI != MBB -> rend ( ) ; ++ MBBI ) { MachineInstr * MI = & * MBBI ; if ( MI -> hasUnmodeledSideEffects ( ) || MI -> isCall ( ) ) { Splats . clear ( ) ; continue ; } for ( auto SI = Splats . begin ( ) ; SI != Splats . end ( ) ; ) { MachineInstr * SMI = * SI ; unsigned SplatReg = SMI -> getOperand ( 0 ) . getReg ( ) ; unsigned SrcReg = SMI -> getOperand ( 1 ) . getReg ( ) ; if ( MI -> modifiesRegister ( SrcReg , TRI ) ) { switch ( MI -> getOpcode ( ) ) { default : SI = Splats . erase ( SI ) ; continue ; case PPC :: LFS : case PPC :: LFD : case PPC :: LFSU : case PPC :: LFDU : case PPC :: LFSUX : case PPC :: LFDUX : case PPC :: LFSX : case PPC :: LFDX : case PPC :: LFIWAX : case PPC :: LFIWZX : if ( SplatReg != SrcReg ) { unsigned SubRegIndex = TRI -> getSubRegIndex ( SrcReg , MI -> getOperand ( 0 ) . getReg ( ) ) ; unsigned SplatSubReg = TRI -> getSubReg ( SplatReg , SubRegIndex ) ; MI -> getOperand ( 0 ) . setReg ( SplatSubReg ) ; MI -> substituteRegister ( SrcReg , SplatReg , 0 , * TRI ) ; } SI = Splats . erase ( SI ) ; ++ MBBI ; SMI -> eraseFromParent ( ) ; -- MBBI ; ++ NumSimplified ; MadeChange = true ; continue ; } } if ( MI -> modifiesRegister ( SplatReg , TRI ) || ( SrcReg != SplatReg && MI -> readsRegister ( SplatReg , TRI ) ) ) { SI = Splats . erase ( SI ) ; continue ; } ++ SI ; } if ( MI -> getOpcode ( ) != PPC :: QVESPLATI && MI -> getOpcode ( ) != PPC :: QVESPLATIs && MI -> getOpcode ( ) != PPC :: QVESPLATIb ) continue ; if ( MI -> getOperand ( 2 ) . getImm ( ) != 0 ) continue ; if ( ! MI -> getOperand ( 1 ) . isKill ( ) ) continue ; Splats . push_back ( MI ) ; } } return MadeChange ; } </s>

runOnMachineFunction - Emit the function body .


<s> SDValue WebAssemblySelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Dst , SDValue Val , SDValue Size , Align Alignment , bool IsVolatile , MachinePointerInfo DstPtrInfo ) const { auto & ST = DAG . getMachineFunction ( ) . getSubtarget < WebAssemblySubtarget > ( ) ; if ( ! ST . hasBulkMemory ( ) ) return SDValue ( ) ; SDValue MemIdx = DAG . getConstant ( 0 , DL , MVT :: i32 ) ; auto LenMVT = ST . hasAddr64 ( ) ? MVT :: i64 : MVT :: i32 ; return DAG . getNode ( WebAssemblyISD :: MEMORY_FILL , DL , MVT :: Other , Chain , MemIdx , Dst , DAG . getAnyExtOrTrunc ( Val , DL , MVT :: i32 ) , DAG . getZExtOrTrunc ( Size , DL , LenMVT ) ) ; } </s>

Emit target-specific code that performs a memset .


<s> MCSectionPIC16 * MCSectionPIC16 :: Create ( const StringRef & Name , SectionKind K , MCContext & Ctx ) { return new ( Ctx ) MCSectionPIC16 ( Name , K ) ; } </s>

Construct a unary instruction , given the opcode and an operand .


<s> static void pa_hpux_init_libfuncs ( void ) { set_optab_libfunc ( add_optab , TFmode , "_U_Qfadd" ) ; set_optab_libfunc ( sub_optab , TFmode , "_U_Qfsub" ) ; set_optab_libfunc ( smul_optab , TFmode , "_U_Qfmpy" ) ; set_optab_libfunc ( sdiv_optab , TFmode , "_U_Qfdiv" ) ; set_optab_libfunc ( smin_optab , TFmode , "_U_Qmin" ) ; set_optab_libfunc ( smax_optab , TFmode , "_U_Qfmax" ) ; set_optab_libfunc ( sqrt_optab , TFmode , "_U_Qfsqrt" ) ; set_optab_libfunc ( abs_optab , TFmode , "_U_Qfabs" ) ; set_optab_libfunc ( neg_optab , TFmode , "_U_Qfneg" ) ; set_optab_libfunc ( eq_optab , TFmode , "_U_Qfeq" ) ; set_optab_libfunc ( ne_optab , TFmode , "_U_Qfne" ) ; set_optab_libfunc ( gt_optab , TFmode , "_U_Qfgt" ) ; set_optab_libfunc ( ge_optab , TFmode , "_U_Qfge" ) ; set_optab_libfunc ( lt_optab , TFmode , "_U_Qflt" ) ; set_optab_libfunc ( le_optab , TFmode , "_U_Qfle" ) ; set_optab_libfunc ( unord_optab , TFmode , "_U_Qfunord" ) ; set_conv_libfunc ( sext_optab , TFmode , SFmode , "_U_Qfcnvff_sgl_to_quad" ) ; set_conv_libfunc ( sext_optab , TFmode , DFmode , "_U_Qfcnvff_dbl_to_quad" ) ; set_conv_libfunc ( trunc_optab , SFmode , TFmode , "_U_Qfcnvff_quad_to_sgl" ) ; set_conv_libfunc ( trunc_optab , DFmode , TFmode , "_U_Qfcnvff_quad_to_dbl" ) ; set_conv_libfunc ( sfix_optab , SImode , TFmode , TARGET_64BIT ? "__U_Qfcnvfxt_quad_to_sgl" : "_U_Qfcnvfxt_quad_to_sgl" ) ; set_conv_libfunc ( sfix_optab , DImode , TFmode , "_U_Qfcnvfxt_quad_to_dbl" ) ; set_conv_libfunc ( ufix_optab , SImode , TFmode , "_U_Qfcnvfxt_quad_to_usgl" ) ; set_conv_libfunc ( ufix_optab , DImode , TFmode , "_U_Qfcnvfxt_quad_to_udbl" ) ; set_conv_libfunc ( sfloat_optab , TFmode , SImode , "_U_Qfcnvxf_sgl_to_quad" ) ; set_conv_libfunc ( sfloat_optab , TFmode , DImode , "_U_Qfcnvxf_dbl_to_quad" ) ; } </s>

Initialize optabs to point to HPUX long double emulation routines .


<s> SDValue X86SelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { if ( DstPtrInfo . getAddrSpace ( ) >= 256 || SrcPtrInfo . getAddrSpace ( ) >= 256 ) return SDValue ( ) ; const MCPhysReg ClobberSet [ ] = { X86 :: RCX , X86 :: RSI , X86 :: RDI , X86 :: ECX , X86 :: ESI , X86 :: EDI } ; if ( isBaseRegConflictPossible ( DAG , ClobberSet ) ) return SDValue ( ) ; const X86Subtarget & Subtarget = DAG . getMachineFunction ( ) . getSubtarget < X86Subtarget > ( ) ; if ( ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ) return emitConstantSizeRepmov ( DAG , Subtarget , dl , Chain , Dst , Src , ConstantSize -> getZExtValue ( ) , Size . getValueType ( ) , Align , isVolatile , AlwaysInline , DstPtrInfo , SrcPtrInfo ) ; return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .


"Byval argument's alignment should be a multiple of"

Target-specific cleanup for formal ByVal parameters .


<s> bool AArch64TTIImpl :: getTgtMemIntrinsic ( IntrinsicInst * Inst , MemIntrinsicInfo & Info ) { switch ( Inst -> getIntrinsicID ( ) ) { default : break ; case Intrinsic :: aarch64_neon_ld2 : case Intrinsic :: aarch64_neon_ld3 : case Intrinsic :: aarch64_neon_ld4 : Info . ReadMem = true ; Info . WriteMem = false ; Info . PtrVal = Inst -> getArgOperand ( 0 ) ; break ; case Intrinsic :: aarch64_neon_st2 : case Intrinsic :: aarch64_neon_st3 : case Intrinsic :: aarch64_neon_st4 : Info . ReadMem = false ; Info . WriteMem = true ; Info . PtrVal = Inst -> getArgOperand ( Inst -> arg_size ( ) - 1 ) ; break ; } switch ( Inst -> getIntrinsicID ( ) ) { default : return false ; case Intrinsic :: aarch64_neon_ld2 : case Intrinsic :: aarch64_neon_st2 : Info . MatchingId = VECTOR_LDST_TWO_ELEMENTS ; break ; case Intrinsic :: aarch64_neon_ld3 : case Intrinsic :: aarch64_neon_st3 : Info . MatchingId = VECTOR_LDST_THREE_ELEMENTS ; break ; case Intrinsic :: aarch64_neon_ld4 : case Intrinsic :: aarch64_neon_st4 : Info . MatchingId = VECTOR_LDST_FOUR_ELEMENTS ; break ; } return true ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> bool SystemZPassConfig :: addPreEmitPass ( ) { addPass ( createSystemZLongBranchPass ( getSystemZTargetMachine ( ) ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static bool use_real_mask_p ( enum predication_type_index pred ) { return pred == PRED_TYPE_m || pred == PRED_TYPE_tum || pred == PRED_TYPE_tumu || pred == PRED_TYPE_mu ; } </s>

Return true if predication is using a real mask operand .


<s>
unsigned
getMemScale
(
)
const
{
assert
(
Kind
==
Memory
&&
"Invalid access!"
)
;
return
Mem
.
Scale
;
}
</s>

Scaling factor for ( scaled or unscaled ) load or store .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Sparc Machine Code Emitter"
;
}
</s>


<s>
void
MipsCodeEmitter
::
emitInstruction
(
const
MachineInstr
&
MI
)
{
DEBUG
(
errs
(
)
<<
"JIT: "
<<
(
void
*
)
MCE
.
getCurrentPCValue
(
)
<<
":\t"
<<
MI
)
;
MCE
.
processDebugLoc
(
MI
.
getDebugLoc
(
)
,
true
)
;
if
(
(
MI
.
getDesc
(
)
.
TSFlags
&
MipsII
::
FormMask
)
==
MipsII
::
Pseudo
)
return
;
emitWord
(
getBinaryCodeForInstr
(
MI
)
)
;
++
NumEmitted
;
MCE
.
processDebugLoc
(
MI
.
getDebugLoc
(
)
,
false
)
;
}
</s>

Targets should implement this to emit instructions .

Mips
Mips
"JIT: "
":\t"
MipsII::FormMask
MipsII::Pseudo


<s> bool AMDGPUAnnotateUniformValues :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; DA = & getAnalysis < LegacyDivergenceAnalysis > ( ) ; MDR = & getAnalysis < MemoryDependenceWrapperPass > ( ) . getMemDep ( ) ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; isEntryFunc = AMDGPU :: isEntryFunctionCC ( F . getCallingConv ( ) ) ; visit ( F ) ; noClobberClones . clear ( ) ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void SIInstrInfo :: legalizeOpWithMove ( MachineInstr * MI , unsigned OpIdx ) const { MachineBasicBlock :: iterator I = MI ; MachineOperand & MO = MI -> getOperand ( OpIdx ) ; MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; unsigned RCID = get ( MI -> getOpcode ( ) ) . OpInfo [ OpIdx ] . RegClass ; const TargetRegisterClass * RC = RI . getRegClass ( RCID ) ; unsigned Opcode = AMDGPU :: V_MOV_B32_e32 ; if ( MO . isReg ( ) ) { Opcode = AMDGPU :: COPY ; } else if ( RI . isSGPRClass ( RC ) ) { Opcode = AMDGPU :: S_MOV_B32 ; } const TargetRegisterClass * VRC = RI . getEquivalentVGPRClass ( RC ) ; unsigned Reg = MRI . createVirtualRegister ( VRC ) ; BuildMI ( * MI -> getParent ( ) , I , MI -> getParent ( ) -> findDebugLoc ( I ) , get ( Opcode ) , Reg ) . addOperand ( MO ) ; MO . ChangeToRegister ( Reg , false ) ; } </s>

Legalize the OpIndex operand of this instruction by inserting a MOV .


<s> static void mips_ls2_dfa_post_advance_cycle ( state_t state ) { if ( cpu_unit_reservation_p ( state , mips_ls2 . alu1_core_unit_code ) ) { gcc_assert ( mips_ls2 . cycle_has_multi_p ) ; mips_ls2 . alu1_turn_p = false ; } mips_ls2 . cycle_has_multi_p = false ; if ( cpu_unit_reservation_p ( state , mips_ls2 . alu2_core_unit_code ) ) mips_ls2 . alu1_turn_p = true ; if ( mips_ls2 . alu1_turn_p ) { if ( state_transition ( state , mips_ls2 . alu1_turn_enabled_insn ) >= 0 ) gcc_unreachable ( ) ; } else { if ( state_transition ( state , mips_ls2 . alu2_turn_enabled_insn ) >= 0 ) gcc_unreachable ( ) ; } if ( cpu_unit_reservation_p ( state , mips_ls2 . falu1_core_unit_code ) ) { gcc_unreachable ( ) ; mips_ls2 . falu1_turn_p = false ; } if ( cpu_unit_reservation_p ( state , mips_ls2 . falu2_core_unit_code ) ) mips_ls2 . falu1_turn_p = true ; if ( mips_ls2 . falu1_turn_p ) { if ( state_transition ( state , mips_ls2 . falu1_turn_enabled_insn ) >= 0 ) gcc_unreachable ( ) ; } else { if ( state_transition ( state , mips_ls2 . falu2_turn_enabled_insn ) >= 0 ) gcc_unreachable ( ) ; } } </s>

Initialize STATE when scheduling for Loongson 2E/2F . Support round-robin dispatch scheme by enabling only one of ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions respectively .


<s>
StringRef
getPassName
(
)
const
override
{
return
"AArch64 Redundant Copy Elimination"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static int mips_multipass_dfa_lookahead ( void ) { if ( TUNE_SB1 ) return 4 ; if ( TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A ) return 4 ; if ( TUNE_OCTEON ) return 2 ; if ( TUNE_P5600 || TUNE_I6400 ) return 4 ; return 0 ; } </s>


<s> void RISCVTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { if ( Op . getOpcode ( ) != RISCVISD :: SELECT_CC ) return ; KnownBits Known2 ; DAG . computeKnownBits ( Op -> getOperand ( 3 ) , Known , Depth + 1 ) ; DAG . computeKnownBits ( Op -> getOperand ( 4 ) , Known2 , Depth + 1 ) ; Known . Zero &= Known2 . Zero ; Known . One &= Known2 . One ; } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> static bool isNodeHidden ( const SUnit * Node , const ScheduleDAG * Graph ) { return ( Node -> NumPreds > 10 || Node -> NumSuccs > 10 ) ; } </s>

Do not print nodes that are part of a pi-block separately .


<s> rtx function_expander :: convert_to_pmode ( rtx x ) { if ( ptr_mode == SImode ) x = simplify_gen_unary ( ZERO_EXTEND , DImode , x , SImode ) ; return x ; } </s>


<s> bool MipsTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { if ( VT != MVT :: f32 && VT != MVT :: f64 ) return false ; return Imm . isZero ( ) ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> void X86DynAllocaExpander :: lower ( MachineInstr * MI , Lowering L ) { const DebugLoc & DL = MI -> getDebugLoc ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: iterator I = * MI ; int64_t Amount = getDynAllocaAmount ( MI , MRI ) ; if ( Amount == 0 ) { MI -> eraseFromParent ( ) ; return ; } bool Is64Bit = STI -> is64Bit ( ) ; bool Is64BitAlloca = MI -> getOpcode ( ) == X86 :: DYN_ALLOCA_64 ; assert ( SlotSize == 4 || SlotSize == 8 ) ; Optional < MachineFunction :: DebugInstrOperandPair > InstrNum = None ; if ( unsigned Num = MI -> peekDebugInstrNum ( ) ) { InstrNum = { Num , 2 } ; } switch ( L ) { case TouchAndSub : { assert ( Amount >= SlotSize ) ; unsigned RegA = Is64Bit ? X86 :: RAX : X86 :: EAX ; BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) ) . addReg ( RegA , RegState :: Undef ) ; Amount -= SlotSize ; if ( ! Amount ) break ; LLVM_FALLTHROUGH ; } case Sub : assert ( Amount > 0 ) ; if ( Amount == SlotSize ) { unsigned RegA = Is64Bit ? X86 :: RAX : X86 :: EAX ; BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) ) . addReg ( RegA , RegState :: Undef ) ; } else { BuildMI ( * MBB , I , DL , TII -> get ( getSubOpcode ( Is64BitAlloca , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } break ; case Probe : if ( ! NoStackArgProbe ) { unsigned RegA = Is64BitAlloca ? X86 :: RAX : X86 :: EAX ; BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: COPY ) , RegA ) . addReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ; STI -> getFrameLowering ( ) -> emitStackProbe ( * MBB -> getParent ( ) , * MBB , MI , DL , false , InstrNum ) ; } else { BuildMI ( * MBB , I , DL , TII -> get ( Is64BitAlloca ? X86 :: SUB64rr : X86 :: SUB32rr ) , StackPtr ) . addReg ( StackPtr ) . addReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ; } break ; } Register AmountReg = MI -> getOperand ( 0 ) . getReg ( ) ; MI -> eraseFromParent ( ) ; if ( MRI -> use_empty ( AmountReg ) ) if ( MachineInstr * AmountDef = MRI -> getUniqueVRegDef ( AmountReg ) ) AmountDef -> eraseFromParent ( ) ; } </s>


<s> void optimization_options ( int level ATTRIBUTE_UNUSED , int size ATTRIBUTE_UNUSED ) { flag_caller_saves = 0 ; flag_asynchronous_unwind_tables = 1 ; if ( size != 0 ) target_flags |= MASK_MVCLE ; } </s>

Change optimizations to be performed , depending on the optimization level . LEVEL is the optimization level specified ; 2 if ` -O2 ' is specified , 1 if ` -O ' is specified , and 0 if neither is specified . SIZE is nonzero if ` -Os ' is specified and zero otherwise .


<s> bool Z80FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( MFI -> getMaxCallFrameSize ( ) > 0 || ( MFI -> getNumObjects ( ) > 0 ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void Thumb2InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( RC == & ARM :: GPRRegClass || RC == & ARM :: tGPRRegClass || RC == & ARM :: tcGPRRegClass || RC == & ARM :: rGPRRegClass || RC == & ARM :: GPRnopcRegClass ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2STRi12 ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } if ( ARM :: GPRPairRegClass . hasSubClassEq ( RC ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( SrcReg , & ARM :: GPRPair_with_gsub_1_in_rGPRRegClass ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( ARM :: t2STRDi8 ) ) ; AddDReg ( MIB , SrcReg , ARM :: gsub_0 , getKillRegState ( isKill ) , TRI ) ; AddDReg ( MIB , SrcReg , ARM :: gsub_1 , 0 , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ; AddDefaultPred ( MIB ) ; return ; } ARMBaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg , isKill , FI , RC , TRI ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool ARMFastISel :: isTypeLegal ( Type * Ty , MVT & VT ) { EVT evt = TLI . getValueType ( DL , Ty , true ) ; if ( evt == MVT :: Other || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; return TLI . isTypeLegal ( VT ) ; } </s>


<s> rtx frv_split_cond_move ( rtx operands [ ] ) { rtx dest = operands [ 0 ] ; rtx test = operands [ 1 ] ; rtx cc_reg = operands [ 2 ] ; rtx src1 = operands [ 3 ] ; rtx src2 = operands [ 4 ] ; rtx cr_reg = operands [ 5 ] ; rtx ret ; enum machine_mode cr_mode = GET_MODE ( cr_reg ) ; start_sequence ( ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cr_reg , gen_rtx_fmt_ee ( GET_CODE ( test ) , GET_MODE ( cr_reg ) , cc_reg , const0_rtx ) ) ) ; if ( GET_CODE ( src1 ) == CONST_INT && GET_CODE ( src2 ) == CONST_INT ) { HOST_WIDE_INT value1 = INTVAL ( src1 ) ; HOST_WIDE_INT value2 = INTVAL ( src2 ) ; if ( value1 == 0 ) { emit_move_insn ( dest , src2 ) ; emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_NE ( cr_mode , cr_reg , const0_rtx ) , gen_rtx_SET ( VOIDmode , dest , src1 ) ) ) ; } else if ( value2 == 0 ) { emit_move_insn ( dest , src1 ) ; emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_EQ ( cr_mode , cr_reg , const0_rtx ) , gen_rtx_SET ( VOIDmode , dest , src2 ) ) ) ; } else if ( IN_RANGE_P ( value1 , - 2048 , 2047 ) && IN_RANGE_P ( value2 - value1 , - 2048 , 2047 ) ) { rtx dest_si = ( ( GET_MODE ( dest ) == SImode ) ? dest : gen_rtx_SUBREG ( SImode , dest , 0 ) ) ; emit_move_insn ( dest_si , GEN_INT ( value2 - value1 ) ) ; emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_NE ( cr_mode , cr_reg , const0_rtx ) , gen_rtx_SET ( VOIDmode , dest_si , const0_rtx ) ) ) ; emit_insn ( gen_addsi3 ( dest_si , dest_si , src1 ) ) ; } else gcc_unreachable ( ) ; } else { if ( ! rtx_equal_p ( dest , src1 ) ) emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_NE ( cr_mode , cr_reg , const0_rtx ) , gen_rtx_SET ( VOIDmode , dest , src1 ) ) ) ; if ( ! rtx_equal_p ( dest , src2 ) ) emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_EQ ( cr_mode , cr_reg , const0_rtx ) , gen_rtx_SET ( VOIDmode , dest , src2 ) ) ) ; } ret = get_insns ( ) ; end_sequence ( ) ; return ret ; } </s>

Split a conditional move into constituent parts , returning a SEQUENCE containing all of the insns .


"%qE attribute only applies to functions"

Handle an attribute requiring a FUNCTION_DECL ; arguments as in struct attribute_spec.handler .


<s> void SparcTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { KnownBits Known2 ; Known . resetAll ( ) ; switch ( Op . getOpcode ( ) ) { default : break ; case SPISD :: SELECT_ICC : case SPISD :: SELECT_XCC : case SPISD :: SELECT_FCC : Known = DAG . computeKnownBits ( Op . getOperand ( 1 ) , Depth + 1 ) ; Known2 = DAG . computeKnownBits ( Op . getOperand ( 0 ) , Depth + 1 ) ; Known . One &= Known2 . One ; Known . Zero &= Known2 . Zero ; break ; } } </s>


<s> void X86CallLowering :: splitToValueTypes ( const ArgInfo & OrigArg , SmallVectorImpl < ArgInfo > & SplitArgs , const DataLayout & DL , MachineRegisterInfo & MRI , SplitArgTy PerformArgSplit ) const { const X86TargetLowering & TLI = * getTLI < X86TargetLowering > ( ) ; LLVMContext & Context = OrigArg . Ty -> getContext ( ) ; EVT VT = TLI . getValueType ( DL , OrigArg . Ty ) ; unsigned NumParts = TLI . getNumRegisters ( Context , VT ) ; if ( NumParts == 1 ) { SplitArgs . push_back ( OrigArg ) ; return ; } SmallVector < uint64_t , 4 > BitOffsets ; SmallVector < unsigned , 8 > SplitRegs ; EVT PartVT = TLI . getRegisterType ( Context , VT ) ; Type * PartTy = PartVT . getTypeForEVT ( Context ) ; for ( unsigned i = 0 ; i < NumParts ; ++ i ) { ArgInfo Info = ArgInfo { MRI . createGenericVirtualRegister ( LLT { * PartTy , DL } ) , PartTy , OrigArg . Flags } ; SplitArgs . push_back ( Info ) ; BitOffsets . push_back ( PartVT . getSizeInBits ( ) * i ) ; SplitRegs . push_back ( Info . Reg ) ; } PerformArgSplit ( SplitRegs , BitOffsets ) ; } </s>

Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> std :: pair < unsigned , const TargetRegisterClass * > AArch64TargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : if ( VT . getSizeInBits ( ) <= 32 ) return std :: make_pair ( 0U , & AArch64 :: GPR32RegClass ) ; else if ( VT == MVT :: i64 ) return std :: make_pair ( 0U , & AArch64 :: GPR64RegClass ) ; break ; case 'w' : if ( VT == MVT :: f16 ) return std :: make_pair ( 0U , & AArch64 :: FPR16RegClass ) ; else if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , & AArch64 :: FPR32RegClass ) ; else if ( VT == MVT :: f64 ) return std :: make_pair ( 0U , & AArch64 :: FPR64RegClass ) ; else if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & AArch64 :: VPR64RegClass ) ; else if ( VT == MVT :: f128 ) return std :: make_pair ( 0U , & AArch64 :: FPR128RegClass ) ; else if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & AArch64 :: VPR128RegClass ) ; break ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> void ARMElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { const ARMBaseTargetMachine & ARM_TM = static_cast < const ARMBaseTargetMachine & > ( TM ) ; bool isAAPCS_ABI = ARM_TM . TargetABI == ARMBaseTargetMachine :: ARMABI :: ARM_ABI_AAPCS ; bool genExecuteOnly = ARM_TM . getMCSubtargetInfo ( ) -> hasFeature ( ARM :: FeatureExecuteOnly ) ; TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( isAAPCS_ABI ) ; if ( isAAPCS_ABI ) { LSDASection = nullptr ; } if ( genExecuteOnly ) { unsigned Type = ELF :: SHT_PROGBITS ; unsigned Flags = ELF :: SHF_EXECINSTR | ELF :: SHF_ALLOC | ELF :: SHF_ARM_PURECODE ; TextSection = Ctx . getELFSection ( ".text" , Type , Flags , 0 , "" , false , 0U , nullptr ) ; } } </s>

This method must be called before any actual lowering is done .

ARM ARM ARM ARM ARM ARM ARM ARMABI::ARM_ABI_AAPCS ARM ARM::FeatureExecuteOnly ARM ".text" 0 "" 0U


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addPreservedID ( MachineLoopInfoID ) ; AU . addPreservedID ( MachineDominatorsID ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
const
char
*
output_v9branch
(
rtx
op
,
rtx
dest
,
int
reg
,
int
label
,
int
reversed
,
int
annul
,
rtx_insn
*
insn
)
{
static
char
string
[
64
]
;
enum
rtx_code
code
=
GET_CODE
(
op
)
;
machine_mode
mode
=
GET_MODE
(
XEXP
(
op
,
0
)
)
;
rtx
note
;
int
far
;
char
*
p
;
far
=
get_attr_length
(
insn
)
>=
3
;
if
(
reversed
^
far
)
code
=
reverse_condition
(
code
)
;
gcc_assert
(
mode
==
DImode
)
;
switch
(
code
)
{
case
NE
:
strcpy
(
string
,
"brnz"
)
;
break
;
case
EQ
:
strcpy
(
string
,
"brz"
)
;
break
;
case
GE
:
strcpy
(
string
,
"brgez"
)
;
break
;
case
LT
:
strcpy
(
string
,
"brlz"
)
;
break
;
case
LE
:
strcpy
(
string
,
"brlez"
)
;
break
;
case
GT
:
strcpy
(
string
,
"brgz"
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
p
=
strchr
(
string
,
'\0'
)
;
if
(
annul
&&
!
far
)
{
strcpy
(
p
,
",a"
)
;
p
+=
2
;
}
if
(
insn
&&
(
note
=
find_reg_note
(
insn
,
REG_BR_PROB
,
NULL_RTX
)
)
)
{
strcpy
(
p
,
(
(
profile_probability
::
from_reg_br_prob_note
(
XINT
(
note
,
0
)
)
>=
profile_probability
::
even
(
)
)
^
far
)
",pt"
:
",pn"
)
;
p
+=
3
;
}
*
p
=
p
<
string
+
8
'\t'
:
' '
;
p
++
;
*
p
++
=
'%'
;
*
p
++
=
'0'
+
reg
;
*
p
++
=
','
;
*
p
++
=
' '
;
if
(
far
)
{
int
veryfar
=
1
,
delta
;
if
(
INSN_ADDRESSES_SET_P
(
)
)
{
delta
=
(
INSN_ADDRESSES
(
INSN_UID
(
dest
)
)
INSN_ADDRESSES
(
INSN_UID
(
insn
)
)
)
;
if
(
delta
>=
260000
&&
delta
<
260000
)
veryfar
=
0
;
}
strcpy
(
p
,
".+12\n\t nop\n\t"
)
;
if
(
annul
||
!
final_sequence
)
p
[
3
]
=
'6'
;
p
+=
12
;
if
(
veryfar
)
{
strcpy
(
p
,
"b\t"
)
;
p
+=
2
;
}
else
{
strcpy
(
p
,
"ba,pt\t%%xcc, "
)
;
p
+=
13
;
}
}
*
p
++
=
'%'
;
*
p
++
=
'l'
;
*
p
++
=
'0'
+
label
;
*
p
++
=
'%'
;
*
p
++
=
'#'
;
*
p
=
'\0'
;
return
string
;
}
</s>

Return the string to output a conditional branch to LABEL , testing register REG . LABEL is the operand number of the label ; REG is the operand number of the reg . OP is the conditional expression . The mode of REG says what kind of comparison we made . REVERSED is non-zero if we should reverse the sense of the comparison . ANNUL is non-zero if we should generate an annulling branch . NOOP is non-zero if we have to follow this branch by a noop .


Schedule - This is called back from ScheduleDAGInstrs : :Run ( ) when it 's time to do some work .


<s> bool MSP430FrameInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ; } </s>


<s> unsigned getMachineCSELookAheadLimit ( ) const override { return 20 ; } </s>

Return the value to use for the MachineCSE 's LookAheadLimit , which is a heuristic used for CSE'ing phys reg defs .


<s> void PatmosFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetInstrInfo * TII = TM . getInstrInfo ( ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; MachineInstr * MI = emitSTC ( MF , MBB , MBBI , Patmos :: SFREEi ) ; if ( MI ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; unsigned stackSize = MFI -> getStackSize ( ) ; if ( stackSize ) { if ( stackSize <= 0xFFF ) { MachineInstr * MI = AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII -> get ( Patmos :: ADDi ) , Patmos :: RSP ) ) . addReg ( Patmos :: RSP ) . addImm ( stackSize ) ; MI -> setFlag ( MachineInstr :: FrameSetup ) ; } else { MachineInstr * MI = AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII -> get ( Patmos :: ADDl ) , Patmos :: RSP ) ) . addReg ( Patmos :: RSP ) . addImm ( stackSize ) ; MI -> setFlag ( MachineInstr :: FrameSetup ) ; } } } </s>

Patmos Patmos Patmos::SFREEi 0xFFF Patmos::ADDi Patmos::RSP Patmos::RSP Patmos::ADDl Patmos::RSP Patmos::RSP


<s> static void fr30_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain_value ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx mem ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp , SImode , 4 ) ; emit_move_insn ( mem , chain_value ) ; mem = adjust_address ( m_tramp , SImode , 12 ) ; emit_move_insn ( mem , fnaddr ) ; } </s>


Implement ASM_DECLARE_FUNCTION_NAME . Output the ISA features used by the function fndecl .

aarch64
"\t.arch %s\n"
"\t"
".tune %s\n"
"function"


<s> void MipsTargetELFStreamer :: finish ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; MCContext & Context = MCA . getContext ( ) ; MCStreamer & OS = getStreamer ( ) ; Triple T ( STI . getTargetTriple ( ) ) ; uint64_t Features = STI . getFeatureBits ( ) ; if ( T . isArch64Bit ( ) && ( Features & Mips :: FeatureN64 ) ) { const MCSectionELF * Sec = Context . getELFSection ( ".MIPS.options" , ELF :: SHT_MIPS_OPTIONS , ELF :: SHF_ALLOC | ELF :: SHF_MIPS_NOSTRIP , SectionKind :: getMetadata ( ) ) ; OS . SwitchSection ( Sec ) ; OS . EmitIntValue ( 1 , 1 ) ; OS . EmitIntValue ( 40 , 1 ) ; OS . EmitIntValue ( 0 , 2 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 8 ) ; } else { const MCSectionELF * Sec = Context . getELFSection ( ".reginfo" , ELF :: SHT_MIPS_REGINFO , ELF :: SHF_ALLOC , SectionKind :: getMetadata ( ) ) ; OS . SwitchSection ( Sec ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; } emitMipsAbiFlags ( ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> void Z80AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; MCInst TmpInst ; TmpInst . setOpcode ( MI -> getOpcode ( ) ) ; for ( const MachineOperand & MO : MI -> operands ( ) ) { MCOperand MCOp ; if ( LowerZ80MachineOperandToMCOperand ( MO , MCOp , * this ) ) TmpInst . addOperand ( MCOp ) ; } EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static uint16_t flags ( uint16_t T ) { return T & FlagMask ; } </s>

Get the flags for this GlobalValue ( see struct GVFlags ) .


"You cannot take the address of a nested function if you use "

Emit RTL insns to initialize the variable parts of a trampoline . FNADDR is an RTX for the address of the function 's pure code . CXT is an RTX for the static chain value for the function .


<s> virtual uint64_t getMachineOpValue ( const MachineInstr & MI , const MachineOperand & MO ) const { return 0 ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s>
bool
R600Packetizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
const
TargetInstrInfo
*
TII
=
Fn
.
getTarget
(
)
.
getInstrInfo
(
)
;
MachineLoopInfo
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
MachineDominatorTree
&
MDT
=
getAnalysis
<
MachineDominatorTree
>
(
)
;
R600PacketizerList
Packetizer
(
Fn
,
MLI
,
MDT
)
;
assert
(
Packetizer
.
getResourceTracker
(
)
&&
"Empty DFA table!"
)
;
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
MachineBasicBlock
::
iterator
End
=
MBB
->
end
(
)
;
MachineBasicBlock
::
iterator
MI
=
MBB
->
begin
(
)
;
while
(
MI
!=
End
)
{
if
(
MI
->
isKill
(
)
||
MI
->
getOpcode
(
)
==
AMDGPU
::
IMPLICIT_DEF
||
(
MI
->
getOpcode
(
)
==
AMDGPU
::
CF_ALU
&&
!
MI
->
getOperand
(
8
)
.
getImm
(
)
)
)
{
MachineBasicBlock
::
iterator
DeleteMI
=
MI
;
++
MI
;
MBB
->
erase
(
DeleteMI
)
;
End
=
MBB
->
end
(
)
;
continue
;
}
for
(
size_t
idx
=
MI
->
getNumExplicitOperands
(
)
;
idx
<
MI
->
getNumOperands
(
)
;
idx
++
)
{
MachineOperand
&
MO
=
MI
->
getOperand
(
idx
)
;
if
(
MO
.
isImplicit
(
)
)
{
MI
->
RemoveOperand
(
idx
)
;
idx
;
}
}
++
MI
;
}
}
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
unsigned
RemainingCount
=
MBB
->
size
(
)
;
for
(
MachineBasicBlock
::
iterator
RegionEnd
=
MBB
->
end
(
)
;
RegionEnd
!=
MBB
->
begin
(
)
;
)
{
MachineBasicBlock
::
iterator
I
=
RegionEnd
;
for
(
;
I
!=
MBB
->
begin
(
)
;
I
,
RemainingCount
)
{
if
(
TII
->
isSchedulingBoundary
(
llvm
::
prior
(
I
)
,
MBB
,
Fn
)
)
break
;
}
I
=
MBB
->
begin
(
)
;
if
(
I
==
RegionEnd
)
{
RegionEnd
=
llvm
::
prior
(
RegionEnd
)
;
RemainingCount
;
continue
;
}
if
(
I
==
llvm
::
prior
(
RegionEnd
)
)
{
RegionEnd
=
llvm
::
prior
(
RegionEnd
)
;
continue
;
}
Packetizer
.
PacketizeMIs
(
MBB
,
I
,
RegionEnd
)
;
RegionEnd
=
I
;
}
}
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> SDValue HexagonTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & dl , SelectionDAG & DAG ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_Hexagon ) ; SDValue Flag ; SmallVector < SDValue , 4 > RetOps ( 1 , Chain ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( 1 ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } RetOps [ 0 ] = Chain ; if ( Flag . getNode ( ) ) RetOps . push_back ( Flag ) ; return DAG . getNode ( HexagonISD :: RET_FLAG , dl , MVT :: Other , RetOps ) ; } </s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool ARMTargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { return getTargetMachine ( ) . getOptLevel ( ) != 0 ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( 1 , true , true , false ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s>
StringRef
getPassName
(
)
const
override
{
return
"AMDGPU Annotate Uniform Values"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void MipsFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MipsInstrInfo & TII = * static_cast < const MipsInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; unsigned SP = STI . isABI_N64 ( ) ? Mips :: SP_64 : Mips :: SP ; unsigned FP = STI . isABI_N64 ( ) ? Mips :: FP_64 : Mips :: FP ; unsigned ZERO = STI . isABI_N64 ( ) ? Mips :: ZERO_64 : Mips :: ZERO ; unsigned ADDu = STI . isABI_N64 ( ) ? Mips :: DADDu : Mips :: ADDu ; unsigned ADDiu = STI . isABI_N64 ( ) ? Mips :: DADDiu : Mips :: ADDiu ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( ADDu ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; if ( isInt < 16 > ( StackSize ) ) BuildMI ( MBB , MBBI , dl , TII . get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( StackSize ) ; else { unsigned ATReg = STI . isABI_N64 ( ) ? Mips :: AT_64 : Mips :: AT ; MF . getInfo < MipsFunctionInfo > ( ) -> setEmitNOAT ( ) ; Mips :: loadImmediate ( StackSize , STI . isABI_N64 ( ) , TII , MBB , MBBI , dl , false , 0 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ADDu ) , SP ) . addReg ( SP ) . addReg ( ATReg ) ; } } </s>

Mips Mips Mips Mips Mips::SP_64 Mips::SP Mips::FP_64 Mips::FP Mips::ZERO_64 Mips::ZERO Mips::DADDu Mips::ADDu Mips::DADDiu Mips::ADDiu 0 16 Mips::AT_64 Mips::AT Mips Mips::loadImmediate 0


<s> static void mips_block_move_straight ( rtx dest , rtx src , HOST_WIDE_INT length ) { HOST_WIDE_INT offset , delta ; unsigned HOST_WIDE_INT bits ; int i ; enum machine_mode mode ; rtx * regs ; if ( MEM_ALIGN ( src ) == BITS_PER_WORD / 2 && MEM_ALIGN ( dest ) == BITS_PER_WORD / 2 ) bits = BITS_PER_WORD / 2 ; else bits = BITS_PER_WORD ; mode = mode_for_size ( bits , MODE_INT , 0 ) ; delta = bits / BITS_PER_UNIT ; regs = alloca ( sizeof ( rtx ) * length / delta ) ; for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) { regs [ i ] = gen_reg_rtx ( mode ) ; if ( MEM_ALIGN ( src ) >= bits ) emit_move_insn ( regs [ i ] , adjust_address ( src , mode , offset ) ) ; else { rtx part = adjust_address ( src , BLKmode , offset ) ; if ( ! mips_expand_unaligned_load ( regs [ i ] , part , bits , 0 ) ) gcc_unreachable ( ) ; } } for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) if ( MEM_ALIGN ( dest ) >= bits ) emit_move_insn ( adjust_address ( dest , mode , offset ) , regs [ i ] ) ; else { rtx part = adjust_address ( dest , BLKmode , offset ) ; if ( ! mips_expand_unaligned_store ( part , regs [ i ] , bits , 0 ) ) gcc_unreachable ( ) ; } if ( offset < length ) { src = adjust_address ( src , BLKmode , offset ) ; dest = adjust_address ( dest , BLKmode , offset ) ; move_by_pieces ( dest , src , length - offset , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) , 0 ) ; } } </s>

Emit straight-line code to move LENGTH bytes from SRC to DEST . Assume that the areas do not overlap .


<s> bool use_simple_return_p ( void ) { arm_stack_offsets * offsets ; if ( ! reload_completed ) arm_compute_frame_layout ( ) ; offsets = arm_get_frame_offsets ( ) ; return offsets -> outgoing_args != 0 ; } </s>

Return TRUE if we should try to use a simple_return insn , i.e . perform shrink-wrapping if possible . This is the case if we need to emit a prologue , which we can test by looking at the offsets .


NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX


<s>
SDValue
RISCVTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
RETURNADDR
:
return
lowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
lowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
lowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
lowerGlobalTLSAddress
(
cast
<
GlobalAddressSDNode
>
(
Op
)
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
lowerBlockAddress
(
cast
<
BlockAddressSDNode
>
(
Op
)
,
DAG
)
;
case
ISD
::
JumpTable
:
return
lowerJumpTable
(
cast
<
JumpTableSDNode
>
(
Op
)
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
lowerConstantPool
(
cast
<
ConstantPoolSDNode
>
(
Op
)
,
DAG
)
;
case
ISD
::
VASTART
:
return
lowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
VAARG
:
return
lowerVAARG
(
Op
,
DAG
)
;
case
ISD
::
ATOMIC_FENCE
:
return
lowerATOMIC_FENCE
(
Op
,
DAG
)
;
case
ISD
::
STACKSAVE
:
return
lowerSTACKSAVE
(
Op
,
DAG
)
;
case
ISD
::
STACKRESTORE
:
return
lowerSTACKRESTORE
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
lowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
ADD
:
return
lowerADD
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"Unexpected node to lower"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

RISCV
RISCV
ISD::RETURNADDR
ISD::SELECT_CC
ISD::GlobalAddress
ISD::GlobalTLSAddress
ISD::BlockAddress
ISD::JumpTable
ISD::ConstantPool
ISD::VASTART
ISD::VAARG
ISD::ATOMIC_FENCE
ISD::STACKSAVE
ISD::STACKRESTORE
ISD::FRAMEADDR
ISD::ADD
"Unexpected node to lower"


<s> static void mips_prepare_builtin_arg ( struct expand_operand * op , tree exp , unsigned int argno ) { tree arg ; rtx value ; arg = CALL_EXPR_ARG ( exp , argno ) ; value = expand_normal ( arg ) ; create_input_operand ( op , value , TYPE_MODE ( TREE_TYPE ( arg ) ) ) ; } </s>

Take the head of argument list * ARGLIST and convert it into a form suitable for input operand OP of instruction ICODE . Return the value and point * ARGLIST at the next element of the list .


<s> int getFormat ( ) const { return Format ; } </s>


<s> void ARCInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static rtx gen_reg_or_parallel ( enum machine_mode mode , enum machine_mode orig_mode , unsigned int regno ) { rtx tmp ; if ( orig_mode != BLKmode ) tmp = gen_rtx_REG ( orig_mode , regno ) ; else { tmp = gen_rtx_REG ( mode , regno ) ; tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , const0_rtx ) ; tmp = gen_rtx_PARALLEL ( orig_mode , gen_rtvec ( 1 , tmp ) ) ; } return tmp ; } </s>

We want to pass a value in REGNO whose `` natural '' mode is MODE . However , this may not agree with the mode that the type system has chosen for the register , which is ORIG_MODE . If ORIG_MODE is not BLKmode , then we can go ahead and use it . Otherwise we have to build a PARALLEL instead .


<s> void X86CallLowering :: splitToValueTypes ( const ArgInfo & OrigArg , SmallVectorImpl < ArgInfo > & SplitArgs , const DataLayout & DL , MachineRegisterInfo & MRI , SplitArgTy PerformArgSplit ) const { const X86TargetLowering & TLI = * getTLI < X86TargetLowering > ( ) ; LLVMContext & Context = OrigArg . Ty -> getContext ( ) ; EVT VT = TLI . getValueType ( DL , OrigArg . Ty ) ; unsigned NumParts = TLI . getNumRegisters ( Context , VT ) ; if ( NumParts == 1 ) { SplitArgs . emplace_back ( OrigArg . Reg , VT . getTypeForEVT ( Context ) , OrigArg . Flags , OrigArg . IsFixed ) ; return ; } SmallVector < unsigned , 8 > SplitRegs ; EVT PartVT = TLI . getRegisterType ( Context , VT ) ; Type * PartTy = PartVT . getTypeForEVT ( Context ) ; for ( unsigned i = 0 ; i < NumParts ; ++ i ) { ArgInfo Info = ArgInfo { MRI . createGenericVirtualRegister ( getLLTForType ( * PartTy , DL ) ) , PartTy , OrigArg . Flags } ; SplitArgs . push_back ( Info ) ; SplitRegs . push_back ( Info . Reg ) ; } PerformArgSplit ( SplitRegs ) ; } </s>

Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> void SITargetLowering :: initializeSplitCSR ( MachineBasicBlock * Entry ) const { } </s>

Perform necessary initialization to handle a subset of CSRs explicitly via copies .


<s> rtx get_unaligned_offset ( rtx addr , HOST_WIDE_INT ofs ) { if ( GET_CODE ( addr ) == PLUS ) { ofs += INTVAL ( XEXP ( addr , 1 ) ) ; addr = XEXP ( addr , 0 ) ; } return expand_simple_binop ( Pmode , PLUS , addr , GEN_INT ( ofs & 7 ) , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; } </s>

Compute a value X , such that X & 7 == ( ADDR + OFS ) & 7 . X is always returned in a register .


<s> static void mn10300_gen_multiple_store ( unsigned int mask ) { static const unsigned int store_order [ 8 ] = { FIRST_EXTENDED_REGNUM + 4 , FIRST_EXTENDED_REGNUM + 5 , FIRST_EXTENDED_REGNUM + 6 , FIRST_EXTENDED_REGNUM + 7 , FIRST_DATA_REGNUM + 2 , FIRST_DATA_REGNUM + 3 , FIRST_ADDRESS_REGNUM + 2 , FIRST_ADDRESS_REGNUM + 3 , } ; rtx x , elts [ 9 ] ; unsigned int i ; int count ; if ( mask == 0 ) return ; for ( i = count = 0 ; i < ARRAY_SIZE ( store_order ) ; ++ i ) { unsigned regno = store_order [ i ] ; if ( ( ( mask >> regno ) & 1 ) == 0 ) continue ; ++ count ; x = plus_constant ( Pmode , stack_pointer_rtx , count * - 4 ) ; x = gen_frame_mem ( SImode , x ) ; x = gen_rtx_SET ( x , gen_rtx_REG ( SImode , regno ) ) ; elts [ count ] = F ( x ) ; mask &= ~ ( 1u << regno ) ; } gcc_assert ( mask == 0 ) ; x = plus_constant ( Pmode , stack_pointer_rtx , count * - 4 ) ; x = gen_rtx_SET ( stack_pointer_rtx , x ) ; elts [ 0 ] = F ( x ) ; x = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( count + 1 , elts ) ) ; F ( emit_insn ( x ) ) ; } </s>

Generate an instruction that pushes several registers onto the stack . Register K will be saved if bit K in MASK is set . The function does nothing if MASK is zero . To be compatible with the `` movm '' instruction , the lowest-numbered register must be stored in the lowest slot . If MASK is the set { R1 , ... , RN } , where R1 ... RN are ordered least first , the generated instruction will have the form : ( parallel ( set ( reg : SI 9 ) ( plus : SI ( reg : SI 9 ) ( const_int -N * 4 ) ) ) ( set ( mem : SI ( plus : SI ( reg : SI 9 ) ( const_int -1 * 4 ) ) ) ( reg : SI RN ) ) ... ( set ( mem : SI ( plus : SI ( reg : SI 9 ) ( const_int -N * 4 ) ) ) ( reg : SI R1 ) ) )


"passing %qT to argument %d of %qE, but"

Require argument ARGNO to match argument FIRST_ARGNO , which was inferred to be a pointer to a scalar element of type TYPE .


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { bool is64 = getPointerSize ( ) == 8 ; return createPPCELFObjectWriter ( OS , is64 , isLittleEndian ( ) , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> const MCExpr * X86_64MachoTargetObjectFile :: getIndirectSymViaGOTPCRel ( const MCSymbol * Sym , const MCValue & MV , int64_t Offset , MachineModuleInfo * MMI , MCStreamer & Streamer ) const { unsigned FinalOff = Offset + MV . getConstant ( ) + 4 ; const MCExpr * Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_GOTPCREL , getContext ( ) ) ; const MCExpr * Off = MCConstantExpr :: create ( FinalOff , getContext ( ) ) ; return MCBinaryExpr :: createAdd ( Res , Off , getContext ( ) ) ; } </s>

Get the target specific PC relative GOT entry relocation .


<s> unsigned MOSInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : return 0 ; case MOS :: STAbs : if ( ! MI . getOperand ( 0 ) . isFI ( ) ) return 0 ; FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; case MOS :: STStk : FrameIndex = MI . getOperand ( 2 ) . getIndex ( ) ; return MI . getOperand ( 1 ) . getReg ( ) ; } } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s>
const
char
*
nds32_output_casesi
(
rtx
*
operands
)
{
output_asm_insn
(
"la\t$ta, %l1"
,
operands
)
;
output_asm_insn
(
"lw\t%2, [$ta + %0 << 2]"
,
operands
)
;
if
(
TARGET_16_BIT
)
return
"jr5\t%2"
;
else
return
"jr\t%2"
;
}
</s>

Function to generate normal jump table .


<s> static int ix86_division_cost ( const struct processor_costs * cost , enum machine_mode mode ) { machine_mode inner_mode = mode ; if ( VECTOR_MODE_P ( mode ) ) inner_mode = GET_MODE_INNER ( mode ) ; if ( SSE_FLOAT_MODE_SSEMATH_OR_HF_P ( mode ) ) return inner_mode == DFmode ? cost -> divsd : cost -> divss ; else if ( X87_FLOAT_MODE_P ( mode ) ) return cost -> fdiv ; else if ( FLOAT_MODE_P ( mode ) ) return ix86_vec_cost ( mode , inner_mode == DFmode ? cost -> divsd : cost -> divss ) ; else return cost -> divide [ MODE_INDEX ( mode ) ] ; } </s>


<s> unsigned getIntrinsicInstrCost ( Intrinsic :: ID ID , Type * RetTy , ArrayRef < Type * > Tys , FastMathFlags FMF , unsigned ScalarizationCostPassed = UINT_MAX ) { return 1 ; } </s>


<s> bool X86TargetLowering :: shouldFoldSelectWithIdentityConstant ( unsigned Opcode , EVT VT ) const { if ( ! Subtarget . hasAVX512 ( ) ) return false ; if ( ! Subtarget . hasVLX ( ) && ! VT . is512BitVector ( ) ) return false ; if ( ! VT . isVector ( ) ) return false ; return true ; } </s>

Return true if pulling a binary operation into a select with an identity constant is profitable .


<s> static bool sparc_cannot_force_const_mem ( machine_mode mode , rtx x ) { switch ( GET_CODE ( x ) ) { case CONST_INT : case CONST_DOUBLE : case CONST_VECTOR : return false ; case LABEL_REF : return flag_pic != 0 ; case SYMBOL_REF : if ( SYMBOL_REF_TLS_MODEL ( x ) ) return true ; else return flag_pic != 0 ; case CONST : return sparc_cannot_force_const_mem ( mode , XEXP ( x , 0 ) ) ; case PLUS : case MINUS : return sparc_cannot_force_const_mem ( mode , XEXP ( x , 0 ) ) || sparc_cannot_force_const_mem ( mode , XEXP ( x , 1 ) ) ; case UNSPEC : return true ; default : gcc_unreachable ( ) ; } } </s>

Determine if it 's legal to put X into the constant pool . This is not possible if X contains the address of a symbol that is not constant ( TLS ) or not known at final link time ( PIC ) .


<s> bool PPCInstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Cond , Register DstReg , Register TrueReg , Register FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( Cond . size ( ) != 2 ) return false ; if ( Cond [ 1 ] . getReg ( ) == PPC :: CTR || Cond [ 1 ] . getReg ( ) == PPC :: CTR8 ) return false ; if ( Register :: isPhysicalRegister ( Cond [ 1 ] . getReg ( ) ) ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( ! PPC :: GPRCRegClass . hasSubClassEq ( RC ) && ! PPC :: GPRC_NOR0RegClass . hasSubClassEq ( RC ) && ! PPC :: G8RCRegClass . hasSubClassEq ( RC ) && ! PPC :: G8RC_NOX0RegClass . hasSubClassEq ( RC ) ) return false ; CondCycles = 1 ; TrueCycles = 1 ; FalseCycles = 1 ; return true ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> bool isImm ( ) const override { return Kind == IMMEDIATE ; } </s>


<s> TargetLoweringBase :: LegalizeTypeAction AArch64TargetLowering :: getPreferredVectorAction ( MVT VT ) const { if ( VT == MVT :: v1i8 || VT == MVT :: v1i16 || VT == MVT :: v1i32 || VT == MVT :: v1f32 ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


"First entry in the cond vector must be a predicate register"

"Second entry in the cond vector must be an immediate"

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> std :: pair < int64_t , int64_t > SIInstrInfo :: splitFlatOffset ( int64_t COffsetVal , unsigned AddrSpace , uint64_t FlatVariant ) const { int64_t RemainderOffset = COffsetVal ; int64_t ImmField = 0 ; bool Signed = FlatVariant != SIInstrFlags :: FLAT ; if ( ST . hasNegativeScratchOffsetBug ( ) && FlatVariant == SIInstrFlags :: FlatScratch ) Signed = false ; const unsigned NumBits = AMDGPU :: getNumFlatOffsetBits ( ST , Signed ) ; if ( Signed ) { int64_t D = 1LL << ( NumBits - 1 ) ; RemainderOffset = ( COffsetVal / D ) * D ; ImmField = COffsetVal - RemainderOffset ; if ( ST . hasNegativeUnalignedScratchOffsetBug ( ) && FlatVariant == SIInstrFlags :: FlatScratch && ImmField < 0 && ( ImmField % 4 ) != 0 ) { RemainderOffset += ImmField % 4 ; ImmField -= ImmField % 4 ; } } else if ( COffsetVal >= 0 ) { ImmField = COffsetVal & maskTrailingOnes < uint64_t > ( NumBits ) ; RemainderOffset = COffsetVal - ImmField ; } assert ( isLegalFLATOffset ( ImmField , AddrSpace , FlatVariant ) ) ; assert ( RemainderOffset + ImmField == COffsetVal ) ; return { ImmField , RemainderOffset } ; } </s>

Split COffsetVal into { immediate offset field , remainder offset } values .


<s> int simple_memory_operand ( rtx op , machine_mode mode ATTRIBUTE_UNUSED ) { rtx addr , plus0 , plus1 ; if ( GET_CODE ( op ) != MEM ) return 0 ; if ( GET_MODE_SIZE ( GET_MODE ( op ) ) > UNITS_PER_WORD ) return 0 ; addr = XEXP ( op , 0 ) ; switch ( GET_CODE ( addr ) ) { case REG : return 1 ; case PLUS : plus0 = XEXP ( addr , 0 ) ; plus1 = XEXP ( addr , 1 ) ; if ( GET_CODE ( plus0 ) != REG ) return 0 ; if ( GET_CODE ( plus0 ) == REG && GET_CODE ( plus1 ) == CONST_INT && SMALL_INT ( plus1 ) ) { return 1 ; } else if ( GET_CODE ( plus1 ) == REG && GET_CODE ( plus0 ) == CONST_INT ) { return 1 ; } else if ( GET_CODE ( plus0 ) == REG && GET_CODE ( plus1 ) == REG ) { return 1 ; } else return 0 ; case SYMBOL_REF : return 0 ; default : break ; } return 0 ; } </s>

Return truth value if a memory operand fits in a single instruction ( ie , register + small offset ) .


<s> static void s390_reg_clobbered_rtx ( rtx setreg , rtx set_insn ATTRIBUTE_UNUSED , void * data ) { int * regs_ever_clobbered = ( int * ) data ; unsigned int i , regno ; enum machine_mode mode = GET_MODE ( setreg ) ; if ( GET_CODE ( setreg ) == SUBREG ) { rtx inner = SUBREG_REG ( setreg ) ; if ( ! GENERAL_REG_P ( inner ) ) return ; regno = subreg_regno ( setreg ) ; } else if ( GENERAL_REG_P ( setreg ) ) regno = REGNO ( setreg ) ; else return ; for ( i = regno ; i < regno + HARD_REGNO_NREGS ( regno , mode ) ; i ++ ) regs_ever_clobbered [ i ] = 1 ; } </s>

Helper function for s390_regs_ever_clobbered . Sets the fields in DATA for all clobbered hard regs in SETREG .


<s> int jump_in_call_delay ( rtx insn ) { if ( GET_CODE ( insn ) != JUMP_INSN ) return 0 ; if ( PREV_INSN ( insn ) && PREV_INSN ( PREV_INSN ( insn ) ) && GET_CODE ( next_real_insn ( PREV_INSN ( PREV_INSN ( insn ) ) ) ) == INSN ) { rtx test_insn = next_real_insn ( PREV_INSN ( PREV_INSN ( insn ) ) ) ; return ( GET_CODE ( PATTERN ( test_insn ) ) == SEQUENCE && XVECEXP ( PATTERN ( test_insn ) , 0 , 1 ) == insn ) ; } else return 0 ; } </s>

Return 1 if INSN is in the delay slot of a call instruction .


<s> static void arm_output_c_attributes ( void ) { int wchar_size = ( int ) ( TYPE_PRECISION ( wchar_type_node ) / BITS_PER_UNIT ) ; arm_emit_eabi_attribute ( "Tag_ABI_PCS_wchar_t" , 18 , wchar_size ) ; } </s>

Output C specific EABI object attributes . These can not be done in arm.c because they require information from the C frontend .


<s> bool isCheapToSpeculateCtlz ( ) const override { return true ; } </s>

Return true if it is cheap to speculate a call to intrinsic ctlz .


<s> static bool sparc_pic_register_p ( rtx x ) { if ( ! REG_P ( x ) || ! pic_offset_table_rtx ) return false ; if ( x == pic_offset_table_rtx ) return true ; if ( ! HARD_REGISTER_P ( pic_offset_table_rtx ) && ( HARD_REGISTER_P ( x ) || lra_in_progress || reload_in_progress ) && ORIGINAL_REGNO ( x ) == REGNO ( pic_offset_table_rtx ) ) return true ; return false ; } </s>

Return true if X is a representation of the PIC register .


<s> const char * SystemZTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { OPCODE ( RET_FLAG ) ; OPCODE ( CALL ) ; OPCODE ( SIBCALL ) ; OPCODE ( PCREL_WRAPPER ) ; OPCODE ( PCREL_OFFSET ) ; OPCODE ( IABS ) ; OPCODE ( ICMP ) ; OPCODE ( FCMP ) ; OPCODE ( TM ) ; OPCODE ( BR_CCMASK ) ; OPCODE ( SELECT_CCMASK ) ; OPCODE ( ADJDYNALLOC ) ; OPCODE ( EXTRACT_ACCESS ) ; OPCODE ( UMUL_LOHI64 ) ; OPCODE ( SDIVREM64 ) ; OPCODE ( UDIVREM32 ) ; OPCODE ( UDIVREM64 ) ; OPCODE ( MVC ) ; OPCODE ( MVC_LOOP ) ; OPCODE ( NC ) ; OPCODE ( NC_LOOP ) ; OPCODE ( OC ) ; OPCODE ( OC_LOOP ) ; OPCODE ( XC ) ; OPCODE ( XC_LOOP ) ; OPCODE ( CLC ) ; OPCODE ( CLC_LOOP ) ; OPCODE ( STRCMP ) ; OPCODE ( STPCPY ) ; OPCODE ( SEARCH_STRING ) ; OPCODE ( IPM ) ; OPCODE ( SERIALIZE ) ; OPCODE ( ATOMIC_SWAPW ) ; OPCODE ( ATOMIC_LOADW_ADD ) ; OPCODE ( ATOMIC_LOADW_SUB ) ; OPCODE ( ATOMIC_LOADW_AND ) ; OPCODE ( ATOMIC_LOADW_OR ) ; OPCODE ( ATOMIC_LOADW_XOR ) ; OPCODE ( ATOMIC_LOADW_NAND ) ; OPCODE ( ATOMIC_LOADW_MIN ) ; OPCODE ( ATOMIC_LOADW_MAX ) ; OPCODE ( ATOMIC_LOADW_UMIN ) ; OPCODE ( ATOMIC_LOADW_UMAX ) ; OPCODE ( ATOMIC_CMP_SWAPW ) ; OPCODE ( PREFETCH ) ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> unsigned getNumFixupKinds ( ) const override { return 1 ; } </s>

Get the number of target specific fixup kinds .


<s> bool PatmosRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return false ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < RISCVSubtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool X86FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( MI ) ; if ( MBB . isEHFuncletEntry ( ) && STI . is32Bit ( ) && STI . isOSWindows ( ) ) return true ; const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Opc = STI . is64Bit ( ) ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( const CalleeSavedInfo & I : llvm :: reverse ( CSI ) ) { unsigned Reg = I . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool isLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! isLiveIn ) MBB . addLiveIn ( Reg ) ; bool CanKill = ! isLiveIn ; if ( CanKill ) { for ( MCRegAliasIterator AReg ( Reg , TRI , false ) ; AReg . isValid ( ) ; ++ AReg ) { if ( MRI . isLiveIn ( * AReg ) ) { CanKill = false ; break ; } } } BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , getKillRegState ( CanKill ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( const CalleeSavedInfo & I : llvm :: reverse ( CSI ) ) { unsigned Reg = I . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MVT VT = MVT :: Other ; if ( X86 :: VK16RegClass . contains ( Reg ) ) VT = STI . hasBWI ( ) ? MVT :: v64i1 : MVT :: v16i1 ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg , VT ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , I . getFrameIdx ( ) , RC , TRI ) ; -- MI ; MI -> setFlag ( MachineInstr :: FrameSetup ) ; ++ MI ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> SDValue SNESTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; auto CCFunction = CCAssignFnForReturn ( CallConv ) ; CCInfo . AnalyzeCallResult ( Ins , CCFunction ) ; for ( CCValAssign const & RVLoc : RVLocs ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLoc . getLocReg ( ) , RVLoc . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


"converted opcode should be the same except for cc_out"

"expect uninitialized optional cc_out operand"

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


<s> EVT X86TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & Context , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i8 ; if ( Subtarget . hasAVX512 ( ) ) { const unsigned NumElts = VT . getVectorNumElements ( ) ; EVT LegalVT = VT ; while ( getTypeAction ( Context , LegalVT ) != TypeLegal ) LegalVT = getTypeToTransformTo ( Context , LegalVT ) ; if ( LegalVT . getSimpleVT ( ) . is512BitVector ( ) ) return EVT :: getVectorVT ( Context , MVT :: i1 , NumElts ) ; if ( LegalVT . getSimpleVT ( ) . isVector ( ) && Subtarget . hasVLX ( ) ) { MVT EltVT = LegalVT . getSimpleVT ( ) . getVectorElementType ( ) ; if ( Subtarget . hasBWI ( ) || EltVT . getSizeInBits ( ) >= 32 ) return EVT :: getVectorVT ( Context , MVT :: i1 , NumElts ) ; } } return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s>
unsigned
AArch64TargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
SelectionDAG
&
DAG
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"sp"
,
AArch64
::
SP
)
.
Case
(
"x18"
,
AArch64
::
X18
)
.
Case
(
"w18"
,
AArch64
::
W18
)
.
Default
(
0
)
;
if
(
(
Reg
==
AArch64
::
X18
||
Reg
==
AArch64
::
W18
)
&&
!
Subtarget
->
isX18Reserved
(
)
)
Reg
=
0
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
Twine
(
"Invalid register name \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;
}
</s>

Return the register ID of the name passed in .


<s>
void
LanaiDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
return
;
}
EVT
VT
=
Node
->
getValueType
(
0
)
;
switch
(
Opcode
)
{
case
ISD
::
Constant
:
if
(
VT
==
MVT
::
i32
)
{
ConstantSDNode
*
ConstNode
=
cast
<
ConstantSDNode
>
(
Node
)
;
if
(
ConstNode
->
isNullValue
(
)
)
{
SDValue
New
=
CurDAG
->
getCopyFromReg
(
CurDAG
->
getEntryNode
(
)
,
SDLoc
(
Node
)
,
Lanai
::
R0
,
MVT
::
i32
)
;
return
ReplaceNode
(
Node
,
New
.
getNode
(
)
)
;
}
if
(
ConstNode
->
isAllOnesValue
(
)
)
{
SDValue
New
=
CurDAG
->
getCopyFromReg
(
CurDAG
->
getEntryNode
(
)
,
SDLoc
(
Node
)
,
Lanai
::
R1
,
MVT
::
i32
)
;
return
ReplaceNode
(
Node
,
New
.
getNode
(
)
)
;
}
}
break
;
case
ISD
::
FrameIndex
:
selectFrameIndex
(
Node
)
;
return
;
default
:
break
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> static bool riscv_return_in_memory ( const_tree type , const_tree fndecl ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS args ; cumulative_args_t cum = pack_cumulative_args ( & args ) ; memset ( & args , 0 , sizeof args ) ; function_arg_info arg ( const_cast < tree > ( type ) , true ) ; return riscv_pass_by_reference ( cum , arg ) ; } </s>


<s> bool NyuziTargetLowering :: shouldInsertFencesForAtomic ( const Instruction * I ) const { return true ; } </s>

Helper functions for atomic operations .


<s> static int ia64_adjust_cost ( rtx_insn * insn , int dep_type1 , rtx_insn * dep_insn , int cost , dw_t dw ) { enum reg_note dep_type = ( enum reg_note ) dep_type1 ; enum attr_itanium_class dep_class ; enum attr_itanium_class insn_class ; insn_class = ia64_safe_itanium_class ( insn ) ; dep_class = ia64_safe_itanium_class ( dep_insn ) ; if ( dep_type == REG_DEP_TRUE && ( dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF ) && ( insn_class == ITANIUM_CLASS_BR || insn_class == ITANIUM_CLASS_SCALL ) ) return 0 ; if ( dw == MIN_DEP_WEAK ) return param_sched_mem_true_dep_cost ; else if ( dw > MIN_DEP_WEAK ) { if ( mflag_sched_fp_mem_deps_zero_cost && dep_class == ITANIUM_CLASS_STF ) return 0 ; else return cost ; } if ( dep_type != REG_DEP_OUTPUT ) return cost ; if ( dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF || insn_class == ITANIUM_CLASS_ST || insn_class == ITANIUM_CLASS_STF ) return 0 ; return cost ; } </s>

Adjust the cost of a scheduling dependency . Return the new cost of a dependency LINK or INSN on DEP_INSN . COST is the current cost .


<s> BitVector GBZ80RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( GBZ80 :: PC ) ; Reserved . set ( GBZ80 :: SP ) ; Reserved . set ( GBZ80 :: FLAGS ) ; Reserved . set ( getFrameRegister ( MF ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> int M68kFrameLowering :: mergeSPUpdates ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , bool MergeWithPrevious ) const { if ( ( MergeWithPrevious && MBBI == MBB . begin ( ) ) || ( ! MergeWithPrevious && MBBI == MBB . end ( ) ) ) return 0 ; MachineBasicBlock :: iterator PI = MergeWithPrevious ? std :: prev ( MBBI ) : MBBI ; MachineBasicBlock :: iterator NI = MergeWithPrevious ? nullptr : std :: next ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = 0 ; if ( ! MergeWithPrevious && NI != MBB . end ( ) && NI -> getOpcode ( ) == TargetOpcode :: CFI_INSTRUCTION ) { return Offset ; } if ( Opc == M68k :: ADD32ai && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { assert ( PI -> getOperand ( 1 ) . getReg ( ) == StackPtr ) ; Offset += PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! MergeWithPrevious ) MBBI = NI ; } else if ( Opc == M68k :: SUB32ai && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { assert ( PI -> getOperand ( 1 ) . getReg ( ) == StackPtr ) ; Offset -= PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! MergeWithPrevious ) MBBI = NI ; } return Offset ; } </s>

Check the instruction before/after the passed instruction .


<s> const SystemZRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool runOnModule ( Module & M ) override { SetVector < Function * > Functions ; AnalysisGetter AG ; for ( Function & F : M ) { if ( ! F . isIntrinsic ( ) ) Functions . insert ( & F ) ; } CallGraphUpdater CGUpdater ; BumpPtrAllocator Allocator ; AMDGPUInformationCache InfoCache ( M , AG , Allocator , nullptr , * TM ) ; DenseSet < const char * > Allowed ( { & AAAMDAttributes :: ID , & AAAMDWorkGroupSize :: ID , & AACallEdges :: ID } ) ; Attributor A ( Functions , InfoCache , CGUpdater , & Allowed ) ; for ( Function & F : M ) { if ( ! F . isIntrinsic ( ) ) { A . getOrCreateAAFor < AAAMDAttributes > ( IRPosition :: function ( F ) ) ; A . getOrCreateAAFor < AAAMDWorkGroupSize > ( IRPosition :: function ( F ) ) ; } } ChangeStatus Change = A . run ( ) ; return Change == ChangeStatus :: CHANGED ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> unsigned int nds32_dbx_register_number ( unsigned int regno ) { if ( NDS32_IS_FPR_REGNUM ( regno ) ) return regno + 4 ; return regno ; } </s>

Map internal gcc register numbers to DWARF2 register numbers .


<s>
bool
ARMDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
char
ConstraintCode
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
assert
(
ConstraintCode
==
'm'
&&
"unexpected asm memory constraint"
)
;
OutOps
.
push_back
(
Op
)
;
return
false
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .

ARM
ARM
"unexpected asm memory constraint"


<s> bool ARMBaseTargetMachine :: addPreISel ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt :: None ) PM . add ( createARMGlobalMergePass ( getTargetLowering ( ) ) ) ; return false ; } </s>


"Second offset should be larger than first offset!"

shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine ( in conjunction with areLoadsFromSameBasePtr ) if two loads should be scheduled togther .


<s> bool NyuziTargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> void clear ( ) { Refs = AvailableDomains = Dist = 0 ; Instrs . clear ( ) ; } </s>


<s> virtual const AZPRInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> StringRef AArch64NamedImmMapper :: toString ( uint32_t Value , const FeatureBitset & FeatureBits , bool & Valid ) const { for ( unsigned i = 0 ; i < NumMappings ; ++ i ) { if ( Mappings [ i ] . isValueEqual ( Value , FeatureBits ) ) { Valid = true ; return Mappings [ i ] . Name ; } } Valid = false ; return StringRef ( ) ; } </s>

Convert to a decimal representation in a string .


<s> static rtx frv_expand_prefetches ( enum insn_code icode , tree call ) { rtx pat ; rtx op0 = frv_read_argument ( call , 0 ) ; pat = GEN_FCN ( icode ) ( force_reg ( Pmode , op0 ) ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return 0 ; } </s>

Expand prefetch builtins . These take a single address as argument .


"Should be loading %r15 and something else"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s>
bool
RV16KInstrInfo
::
isBranchOffsetInRange
(
unsigned
BranchOp
,
int64_t
BrOffset
)
const
{
switch
(
BranchOp
)
{
default
:
llvm_unreachable
(
"Unexpected opcode!"
)
;
case
RV16K
::
Bcc
:
case
RV16K
::
BccI
:
return
isInt
<
8
>
(
BrOffset
2
)
;
case
RV16K
::
J
:
case
RV16K
::
JAL
:
return
isInt
<
16
>
(
BrOffset
)
;
}
}
</s>

Determine if the branch target is in range .


<s> uint64_t MipsFrameLowering :: estimateStackSize ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; int64_t Offset = 0 ; for ( int I = MFI -> getObjectIndexBegin ( ) ; I != 0 ; ++ I ) Offset = std :: max ( Offset , - MFI -> getObjectOffset ( I ) ) ; for ( const MCPhysReg * R = TRI . getCalleeSavedRegs ( & MF ) ; * R ; ++ R ) { unsigned Size = TRI . getMinimalPhysRegClass ( * R ) -> getSize ( ) ; Offset = RoundUpToAlignment ( Offset + Size , Size ) ; } unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; assert ( ! MFI -> getObjectIndexEnd ( ) || MaxAlign ) ; for ( unsigned I = 0 , E = MFI -> getObjectIndexEnd ( ) ; I != E ; ++ I ) Offset = RoundUpToAlignment ( Offset + MFI -> getObjectSize ( I ) , MaxAlign ) ; if ( MFI -> adjustsStack ( ) && hasReservedCallFrame ( MF ) ) Offset = RoundUpToAlignment ( Offset + MFI -> getMaxCallFrameSize ( ) , std :: max ( MaxAlign , getStackAlignment ( ) ) ) ; return RoundUpToAlignment ( Offset , getStackAlignment ( ) ) ; } </s>

Estimate and return the size of the stack frame .


<s> static void rs6000_setup_reg_addr_masks ( void ) { ssize_t rc , reg , m , nregs ; addr_mask_type any_addr_mask , addr_mask ; for ( m = 0 ; m < NUM_MACHINE_MODES ; ++ m ) { machine_mode m2 = ( machine_mode ) m ; bool complex_p = false ; bool small_int_p = ( m2 == QImode || m2 == HImode || m2 == SImode ) ; size_t msize ; if ( COMPLEX_MODE_P ( m2 ) ) { complex_p = true ; m2 = GET_MODE_INNER ( m2 ) ; } msize = GET_MODE_SIZE ( m2 ) ; bool indexed_only_p = ( m == SDmode && TARGET_NO_SDMODE_STACK ) ; any_addr_mask = 0 ; for ( rc = FIRST_RELOAD_REG_CLASS ; rc <= LAST_RELOAD_REG_CLASS ; rc ++ ) { addr_mask = 0 ; reg = reload_reg_map [ rc ] . reg ; if ( reg >= 0 && rs6000_hard_regno_mode_ok_p [ m ] [ reg ] ) { bool small_int_vsx_p = ( small_int_p && ( rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX ) ) ; nregs = rs6000_hard_regno_nregs [ m ] [ reg ] ; addr_mask |= RELOAD_REG_VALID ; if ( small_int_vsx_p ) addr_mask |= RELOAD_REG_INDEXED ; else if ( nregs > 1 || m == BLKmode || complex_p ) addr_mask |= RELOAD_REG_MULTIPLE ; else addr_mask |= RELOAD_REG_INDEXED ; if ( TARGET_UPDATE && ( rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR ) && msize <= 8 && ! VECTOR_MODE_P ( m2 ) && ! FLOAT128_VECTOR_P ( m2 ) && ! complex_p && ( m != E_DFmode || ! TARGET_VSX ) && ( m != E_SFmode || ! TARGET_P8_VECTOR ) && ! small_int_vsx_p ) { addr_mask |= RELOAD_REG_PRE_INCDEC ; switch ( m ) { default : addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; case E_DImode : if ( TARGET_POWERPC64 ) addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; case E_DFmode : case E_DDmode : if ( TARGET_DF_INSN ) addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; } } } if ( ( addr_mask != 0 ) && ! indexed_only_p && msize <= 8 && ( rc == RELOAD_REG_GPR || ( ( msize == 8 || m2 == SFmode ) && ( rc == RELOAD_REG_FPR || ( rc == RELOAD_REG_VMX && TARGET_P9_VECTOR ) ) ) ) ) addr_mask |= RELOAD_REG_OFFSET ; else if ( ( addr_mask != 0 ) && ! indexed_only_p && msize == 16 && TARGET_P9_VECTOR && ( ALTIVEC_OR_VSX_VECTOR_MODE ( m2 ) || ( m2 == TImode && TARGET_VSX ) ) ) { addr_mask |= RELOAD_REG_OFFSET ; if ( rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX ) addr_mask |= RELOAD_REG_QUAD_OFFSET ; } if ( rc == RELOAD_REG_VMX && msize == 16 && ( addr_mask & RELOAD_REG_VALID ) != 0 ) addr_mask |= RELOAD_REG_AND_M16 ; reg_addr [ m ] . addr_mask [ rc ] = addr_mask ; any_addr_mask |= addr_mask ; } reg_addr [ m ] . addr_mask [ RELOAD_REG_ANY ] = any_addr_mask ; } } </s>

Update the addr mask bits in reg_addr to help secondary reload and go if legitimate address support to figure out the appropriate addressing to use .


<s> void Initialize ( const MachineFunction & MF , bool isPIC ) { IsPIC = isPIC ; } </s>

This method must be called before any actual lowering is done .


<s>
void
HexagonAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
if
(
MI
->
isBundle
(
)
)
{
std
::
vector
<
MachineInstr
const
*
>
BundleMIs
;
const
MachineBasicBlock
*
MBB
=
MI
->
getParent
(
)
;
MachineBasicBlock
::
const_instr_iterator
MII
=
MI
;
++
MII
;
unsigned
int
IgnoreCount
=
0
;
while
(
MII
!=
MBB
->
end
(
)
&&
MII
->
isInsideBundle
(
)
)
{
const
MachineInstr
*
MInst
=
MII
;
if
(
MInst
->
getOpcode
(
)
==
TargetOpcode
::
DBG_VALUE
||
MInst
->
getOpcode
(
)
==
TargetOpcode
::
IMPLICIT_DEF
)
{
IgnoreCount
++
;
++
MII
;
continue
;
}
BundleMIs
.
push_back
(
MInst
)
;
++
MII
;
}
unsigned
Size
=
BundleMIs
.
size
(
)
;
assert
(
(
Size
+
IgnoreCount
)
==
MI
->
getBundleSize
(
)
&&
"Corrupt Bundle!"
)
;
for
(
unsigned
Index
=
0
;
Index
<
Size
;
Index
++
)
{
HexagonMCInst
MCI
;
HexagonLowerToMC
(
BundleMIs
[
Index
]
,
MCI
,
*
this
)
;
HexagonMCInst
::
AppendImplicitOperands
(
MCI
)
;
MCI
.
setPacketBegin
(
Index
==
0
)
;
MCI
.
setPacketEnd
(
Index
==
(
Size
1
)
)
;
EmitToStreamer
(
OutStreamer
,
MCI
)
;
}
}
else
{
HexagonMCInst
MCI
;
HexagonLowerToMC
(
MI
,
MCI
,
*
this
)
;
HexagonMCInst
::
AppendImplicitOperands
(
MCI
)
;
if
(
MI
->
getOpcode
(
)
==
Hexagon
::
ENDLOOP0
)
{
MCI
.
setPacketBegin
(
true
)
;
MCI
.
setPacketEnd
(
true
)
;
}
EmitToStreamer
(
OutStreamer
,
MCI
)
;
}
return
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool TLCS900TargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { LoadSDNode * LD = cast < LoadSDNode > ( N ) ; if ( LD -> getExtensionType ( ) != ISD :: NON_EXTLOAD ) return false ; EVT VT = LD -> getMemoryVT ( ) ; if ( VT != MVT :: i8 && VT != MVT :: i16 ) return false ; if ( Op -> getOpcode ( ) != ISD :: ADD ) return false ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ) { uint64_t RHSC = RHS -> getZExtValue ( ) ; if ( ( VT == MVT :: i16 && RHSC != 2 ) || ( VT == MVT :: i8 && RHSC != 1 ) ) return false ; Base = Op -> getOperand ( 0 ) ; Offset = DAG . getConstant ( RHSC , VT ) ; AM = ISD :: POST_INC ; return true ; } return false ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .


<s> unsigned MipsTargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT . isVector ( ) ) return std :: max ( ( VT . getSizeInBits ( ) / ( Subtarget . isABI_O32 ( ) ? 32 : 64 ) ) , 1U ) ; return MipsTargetLowering :: getNumRegisters ( Context , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s> const TargetRegisterClass * SparcRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { const SparcSubtarget & Subtarget = MF . getSubtarget < SparcSubtarget > ( ) ; return Subtarget . is64Bit ( ) ? & SP :: I64RegsRegClass : & SP :: IntRegsRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .

Sparc Sparc Sparc Sparc SP::I64RegsRegClass SP::IntRegsRegClass


<s> bool HexagonFrameLowering :: hasFP ( const MachineFunction & MF ) const { auto & MFI = * MF . getFrameInfo ( ) ; auto & HRI = * MF . getSubtarget < HexagonSubtarget > ( ) . getRegisterInfo ( ) ; bool HasFixed = MFI . getNumFixedObjects ( ) ; bool HasPrealloc = const_cast < MachineFrameInfo & > ( MFI ) . getLocalFrameObjectCount ( ) ; bool HasExtraAlign = HRI . needsStackRealignment ( MF ) ; bool HasAlloca = MFI . hasVarSizedObjects ( ) ; if ( MF . getTarget ( ) . getOptLevel ( ) == CodeGenOpt :: None ) return true ; if ( ( HasFixed || HasPrealloc ) && ( HasAlloca || HasExtraAlign ) ) return true ; if ( MFI . getStackSize ( ) > 0 ) { if ( EnableStackOVFSanitizer || UseAllocframe ) return true ; } if ( MFI . hasCalls ( ) || MF . getInfo < HexagonMachineFunctionInfo > ( ) -> hasClobberLR ( ) ) return true ; return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
static
void
arm_asm_trampoline_template
(
FILE
*
f
)
{
fprintf
(
f
,
"\t.syntax unified\n"
)
;
if
(
TARGET_ARM
)
{
fprintf
(
f
,
"\t.arm\n"
)
;
asm_fprintf
(
f
,
"\tldr\t%r, [%r, #0]\n"
,
STATIC_CHAIN_REGNUM
,
PC_REGNUM
)
;
asm_fprintf
(
f
,
"\tldr\t%r, [%r, #0]\n"
,
PC_REGNUM
,
PC_REGNUM
)
;
}
else
if
(
TARGET_THUMB2
)
{
fprintf
(
f
,
"\t.thumb\n"
)
;
asm_fprintf
(
f
,
"\tldr.w\t%r, [%r, #4]\n"
,
STATIC_CHAIN_REGNUM
,
PC_REGNUM
)
;
asm_fprintf
(
f
,
"\tldr.w\t%r, [%r, #4]\n"
,
PC_REGNUM
,
PC_REGNUM
)
;
}
else
{
ASM_OUTPUT_ALIGN
(
f
,
2
)
;
fprintf
(
f
,
"\t.code\t16\n"
)
;
fprintf
(
f
,
".Ltrampoline_start:\n"
)
;
asm_fprintf
(
f
,
"\tpush\t{r0, r1}\n"
)
;
asm_fprintf
(
f
,
"\tldr\tr0, [%r, #8]\n"
,
PC_REGNUM
)
;
asm_fprintf
(
f
,
"\tmov\t%r, r0\n"
,
STATIC_CHAIN_REGNUM
)
;
asm_fprintf
(
f
,
"\tldr\tr0, [%r, #8]\n"
,
PC_REGNUM
)
;
asm_fprintf
(
f
,
"\tstr\tr0, [%r, #4]\n"
,
SP_REGNUM
)
;
asm_fprintf
(
f
,
"\tpop\t{r0, %r}\n"
,
PC_REGNUM
)
;
}
assemble_aligned_integer
(
UNITS_PER_WORD
,
const0_rtx
)
;
assemble_aligned_integer
(
UNITS_PER_WORD
,
const0_rtx
)
;
}
</s>

Output assembler code for a block containing the constant parts of a trampoline , leaving space for the variable parts . On the ARM , ( if r8 is the static chain regnum , and remembering that referencing pc adds an offset of 8 ) the trampoline looks like : ldr r8 , [ pc , # 0 ] ldr pc , [ pc ] .word static chain value .word function 's address XXX FIXME : When the trampoline returns , r8 will be clobbered .


<s> const char * BPFTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( BPFISD :: NodeType ) Opcode ) { case BPFISD :: FIRST_NUMBER : break ; case BPFISD :: RET_FLAG : return "BPFISD::RET_FLAG" ; case BPFISD :: CALL : return "BPFISD::CALL" ; case BPFISD :: SELECT_CC : return "BPFISD::SELECT_CC" ; case BPFISD :: BR_CC : return "BPFISD::BR_CC" ; case BPFISD :: Wrapper : return "BPFISD::Wrapper" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static tree bpf_core_newdecl ( tree type ) { tree rettype = build_function_type_list ( type , type , NULL ) ; char name [ 80 ] ; int len = snprintf ( name , sizeof ( name ) , "%s" , "__builtin_pai_" ) ; static unsigned long cnt = 0 ; len = snprintf ( name + len , sizeof ( name ) - len , "%lu" , cnt ++ ) ; return add_builtin_function_ext_scope ( name , rettype , - 1 , BUILT_IN_MD , NULL , NULL_TREE ) ; } </s>

Synthesize a new builtin function declaration with signature TYPE . Used by bpf_resolve_overloaded_builtin to resolve calls to __builtin_preserve_access_index .


<s> bool SIFoldOperands :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; MRI = & MF . getRegInfo ( ) ; ST = & MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST -> getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; const SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; bool IsIEEEMode = ST -> enableIEEEBit ( MF ) || ! MFI -> hasNoSignedZerosFPMath ( ) ; for ( MachineBasicBlock * MBB : depth_first ( & MF ) ) { MachineBasicBlock :: iterator I , Next ; for ( I = MBB -> begin ( ) ; I != MBB -> end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; tryFoldInst ( TII , & MI ) ; if ( ! TII -> isFoldableCopy ( MI ) ) { if ( IsIEEEMode || ! tryFoldOMod ( MI ) ) tryFoldClamp ( MI ) ; continue ; } MachineOperand & OpToFold = MI . getOperand ( 1 ) ; bool FoldingImm = OpToFold . isImm ( ) || OpToFold . isFI ( ) ; if ( ! FoldingImm && ! OpToFold . isReg ( ) ) continue ; if ( OpToFold . isReg ( ) && ! TargetRegisterInfo :: isVirtualRegister ( OpToFold . getReg ( ) ) ) continue ; MachineOperand & Dst = MI . getOperand ( 0 ) ; if ( Dst . isReg ( ) && ! TargetRegisterInfo :: isVirtualRegister ( Dst . getReg ( ) ) ) continue ; foldInstOperand ( MI , OpToFold ) ; } } return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> MachineSDNode * SITargetLowering :: buildRSRC ( SelectionDAG & DAG , SDLoc DL , SDValue Ptr , uint32_t RsrcDword1 , uint64_t RsrcDword2And3 ) const { SDValue PtrLo = DAG . getTargetExtractSubreg ( AMDGPU :: sub0 , DL , MVT :: i32 , Ptr ) ; SDValue PtrHi = DAG . getTargetExtractSubreg ( AMDGPU :: sub1 , DL , MVT :: i32 , Ptr ) ; if ( RsrcDword1 ) { PtrHi = SDValue ( DAG . getMachineNode ( AMDGPU :: S_OR_B32 , DL , MVT :: i32 , PtrHi , DAG . getConstant ( RsrcDword1 , DL , MVT :: i32 ) ) , 0 ) ; } SDValue DataLo = buildSMovImm32 ( DAG , DL , RsrcDword2And3 & UINT64_C ( 0xFFFFFFFF ) ) ; SDValue DataHi = buildSMovImm32 ( DAG , DL , RsrcDword2And3 >> 32 ) ; const SDValue Ops [ ] = { DAG . getTargetConstant ( AMDGPU :: SReg_128RegClassID , DL , MVT :: i32 ) , PtrLo , DAG . getTargetConstant ( AMDGPU :: sub0 , DL , MVT :: i32 ) , PtrHi , DAG . getTargetConstant ( AMDGPU :: sub1 , DL , MVT :: i32 ) , DataLo , DAG . getTargetConstant ( AMDGPU :: sub2 , DL , MVT :: i32 ) , DataHi , DAG . getTargetConstant ( AMDGPU :: sub3 , DL , MVT :: i32 ) } ; return DAG . getMachineNode ( AMDGPU :: REG_SEQUENCE , DL , MVT :: v4i32 , Ops ) ; } </s>

Return a resource descriptor with the 'Add TID ' bit enabled The TID ( Thread ID ) is multiplied by the stride value ( bits [ 61:48 ] of the resource descriptor ) to create an offset , which is added to the resource pointer .


<s> rtx gen_scalar_move_mask ( machine_mode mode ) { rtx_vector_builder builder ( mode , 1 , 2 ) ; builder . quick_push ( const1_rtx ) ; builder . quick_push ( const0_rtx ) ; return builder . build ( ) ; } </s>


<s> void HexagonFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = prior ( MBB . end ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator MBBI = prior ( MBB . end ( ) ) ; MachineBasicBlock :: iterator MBBI_end = MBB . end ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; if ( STI . hasV4TOps ( ) && MBBI -> getOpcode ( ) == Hexagon :: JMPR && ! DisableDeallocRet ) { MBB . erase ( MBBI ) ; BuildMI ( MBB , MBBI_end , dl , TII . get ( Hexagon :: DEALLOC_RET_V4 ) ) . addImm ( NumBytes ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( Hexagon :: DEALLOCFRAME ) ) . addImm ( NumBytes ) ; } } } </s>

Hexagon Hexagon Hexagon::JMPR Hexagon::DEALLOC_RET_V4 Hexagon::DEALLOCFRAME


<s>
void
X86InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
assert
(
MF
.
getFrameInfo
(
)
->
getObjectSize
(
FrameIdx
)
>=
RC
->
getSize
(
)
&&
"Stack slot too small for store"
)
;
unsigned
Alignment
=
std
::
max
<
uint32_t
>
(
RC
->
getSize
(
)
,
16
)
;
bool
isAligned
=
(
Subtarget
.
getFrameLowering
(
)
->
getStackAlignment
(
)
>=
Alignment
)
||
RI
.
canRealignStack
(
MF
)
;
unsigned
Opc
=
getStoreRegOpcode
(
SrcReg
,
RC
,
isAligned
,
Subtarget
)
;
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> const char * NVPTXTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case NVPTXISD :: CALL : return "NVPTXISD::CALL" ; case NVPTXISD :: RET_FLAG : return "NVPTXISD::RET_FLAG" ; case NVPTXISD :: Wrapper : return "NVPTXISD::Wrapper" ; case NVPTXISD :: DeclareParam : return "NVPTXISD::DeclareParam" ; case NVPTXISD :: DeclareScalarParam : return "NVPTXISD::DeclareScalarParam" ; case NVPTXISD :: DeclareRet : return "NVPTXISD::DeclareRet" ; case NVPTXISD :: DeclareRetParam : return "NVPTXISD::DeclareRetParam" ; case NVPTXISD :: PrintCall : return "NVPTXISD::PrintCall" ; case NVPTXISD :: LoadParam : return "NVPTXISD::LoadParam" ; case NVPTXISD :: LoadParamV2 : return "NVPTXISD::LoadParamV2" ; case NVPTXISD :: LoadParamV4 : return "NVPTXISD::LoadParamV4" ; case NVPTXISD :: StoreParam : return "NVPTXISD::StoreParam" ; case NVPTXISD :: StoreParamV2 : return "NVPTXISD::StoreParamV2" ; case NVPTXISD :: StoreParamV4 : return "NVPTXISD::StoreParamV4" ; case NVPTXISD :: StoreParamS32 : return "NVPTXISD::StoreParamS32" ; case NVPTXISD :: StoreParamU32 : return "NVPTXISD::StoreParamU32" ; case NVPTXISD :: CallArgBegin : return "NVPTXISD::CallArgBegin" ; case NVPTXISD :: CallArg : return "NVPTXISD::CallArg" ; case NVPTXISD :: LastCallArg : return "NVPTXISD::LastCallArg" ; case NVPTXISD :: CallArgEnd : return "NVPTXISD::CallArgEnd" ; case NVPTXISD :: CallVoid : return "NVPTXISD::CallVoid" ; case NVPTXISD :: CallVal : return "NVPTXISD::CallVal" ; case NVPTXISD :: CallSymbol : return "NVPTXISD::CallSymbol" ; case NVPTXISD :: Prototype : return "NVPTXISD::Prototype" ; case NVPTXISD :: MoveParam : return "NVPTXISD::MoveParam" ; case NVPTXISD :: StoreRetval : return "NVPTXISD::StoreRetval" ; case NVPTXISD :: StoreRetvalV2 : return "NVPTXISD::StoreRetvalV2" ; case NVPTXISD :: StoreRetvalV4 : return "NVPTXISD::StoreRetvalV4" ; case NVPTXISD :: PseudoUseParam : return "NVPTXISD::PseudoUseParam" ; case NVPTXISD :: RETURN : return "NVPTXISD::RETURN" ; case NVPTXISD :: CallSeqBegin : return "NVPTXISD::CallSeqBegin" ; case NVPTXISD :: CallSeqEnd : return "NVPTXISD::CallSeqEnd" ; case NVPTXISD :: CallPrototype : return "NVPTXISD::CallPrototype" ; case NVPTXISD :: LoadV2 : return "NVPTXISD::LoadV2" ; case NVPTXISD :: LoadV4 : return "NVPTXISD::LoadV4" ; case NVPTXISD :: LDGV2 : return "NVPTXISD::LDGV2" ; case NVPTXISD :: LDGV4 : return "NVPTXISD::LDGV4" ; case NVPTXISD :: LDUV2 : return "NVPTXISD::LDUV2" ; case NVPTXISD :: LDUV4 : return "NVPTXISD::LDUV4" ; case NVPTXISD :: StoreV2 : return "NVPTXISD::StoreV2" ; case NVPTXISD :: StoreV4 : return "NVPTXISD::StoreV4" ; } } </s>


<s> static bool bfin_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { return ( to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true ) ; } </s>

Given FROM and TO register numbers , say whether this elimination is allowed . Frame pointer elimination is automatically handled . All other eliminations are valid .


<s> static unsigned getReg ( const void * D , unsigned RC , unsigned RegNo ) { const MipsDisassembler * Dis = static_cast < const MipsDisassembler * > ( D ) ; const MCRegisterInfo * RegInfo = Dis -> getContext ( ) . getRegisterInfo ( ) ; return * ( RegInfo -> getRegClass ( RC ) . begin ( ) + RegNo ) ; } </s>

Returns the register associated with this edge .


<s> int mt_legitimate_address_p ( enum machine_mode mode , rtx xinsn , int strict ) { if ( mt_legitimate_simple_address_p ( mode , xinsn , strict ) ) return 1 ; if ( ( mode ) == SImode && GET_CODE ( xinsn ) == AND && GET_CODE ( XEXP ( xinsn , 1 ) ) == CONST_INT && INTVAL ( XEXP ( xinsn , 1 ) ) == - 3 ) return mt_legitimate_simple_address_p ( mode , XEXP ( xinsn , 0 ) , strict ) ; else return 0 ; } </s>

Helper function of GO_IF_LEGITIMATE_ADDRESS . Return non-zero if XINSN is a legitimate address on MT .


<s> const DataLayout * getDataLayout ( ) const override { return getSubtargetImpl ( ) -> getDataLayout ( ) ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .