<s> int zero_and_one ( rtx operand1 , rtx operand2 ) { return CONST_INT_P ( operand1 ) && CONST_INT_P ( operand2 ) && ( ( ( INTVAL ( operand1 ) == 0 ) && ( INTVAL ( operand2 ) == 1 ) ) || ( ( INTVAL ( operand1 ) == 1 ) && ( INTVAL ( operand2 ) == 0 ) ) ) ; } </s>

Return true if the operands are the constants 0 and 1 .


<s> DecodeStatus BPFDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & VStream , raw_ostream & CStream ) const { bool IsLittleEndian = getContext ( ) . getAsmInfo ( ) -> isLittleEndian ( ) ; uint64_t Insn , Hi ; DecodeStatus Result ; Result = readInstruction64 ( Bytes , Address , Size , Insn , IsLittleEndian ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTableBPF64 , Instr , Insn , Address , this , STI ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; switch ( Instr . getOpcode ( ) ) { case BPF :: LD_imm64 : case BPF :: LD_pseudo : { if ( Bytes . size ( ) < 16 ) { Size = 0 ; return MCDisassembler :: Fail ; } Size = 16 ; if ( IsLittleEndian ) Hi = ( Bytes [ 12 ] << 0 ) | ( Bytes [ 13 ] << 8 ) | ( Bytes [ 14 ] << 16 ) | ( Bytes [ 15 ] << 24 ) ; else Hi = ( Bytes [ 12 ] << 24 ) | ( Bytes [ 13 ] << 16 ) | ( Bytes [ 14 ] << 8 ) | ( Bytes [ 15 ] << 0 ) ; auto & Op = Instr . getOperand ( 1 ) ; Op . setImm ( Make_64 ( Hi , Op . getImm ( ) ) ) ; break ; } case BPF :: LD_ABS_B : case BPF :: LD_ABS_H : case BPF :: LD_ABS_W : case BPF :: LD_IND_B : case BPF :: LD_IND_H : case BPF :: LD_IND_W : { auto Op = Instr . getOperand ( 0 ) ; Instr . clear ( ) ; Instr . addOperand ( MCOperand :: createReg ( BPF :: R6 ) ) ; Instr . addOperand ( Op ) ; break ; } } return Result ; } </s>

Returns the disassembly of a single instruction .


<s> unsigned HexagonInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case Hexagon :: S2_storeri_io : case Hexagon :: S2_storerd_io : case Hexagon :: S2_storerh_io : case Hexagon :: S2_storerb_io : if ( MI -> getOperand ( 2 ) . isFI ( ) && MI -> getOperand ( 1 ) . isImm ( ) && ( MI -> getOperand ( 1 ) . getImm ( ) == 0 ) ) { FrameIndex = MI -> getOperand ( 0 ) . getIndex ( ) ; return MI -> getOperand ( 2 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> TargetPassConfig * BPFTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new BPFPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> VETargetMachine :: VETargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( createTLOF ( ) ) , Subtarget ( TT , std :: string ( CPU ) , std :: string ( FS ) , * this ) { initAsmInfo ( ) ; } </s>

Create an Aurora VE architecture model .


<s> HOST_WIDE_INT const_vector_elt_as_int ( rtx op , unsigned int elt ) { rtx tmp ; gcc_assert ( GET_MODE ( op ) != V2DImode && GET_MODE ( op ) != V2DFmode ) ; tmp = CONST_VECTOR_ELT ( op , elt ) ; if ( GET_MODE ( op ) == V4SFmode ) tmp = gen_lowpart ( SImode , tmp ) ; return INTVAL ( tmp ) ; } </s>

Interpret element ELT of the CONST_VECTOR OP as an integer value . If the mode of OP is MODE_VECTOR_INT , this simply returns the corresponding element of the vector , but for V4SFmode , the corresponding `` float '' is interpreted as an SImode integer .


<s> bool ldstwm_operation_p ( rtx op , bool load_p ) { int start , i , end = XVECLEN ( op , 0 ) - 1 , last_regno = - 1 ; unsigned int regset = 0 ; rtx base_reg , offset ; rtx first_elt = XVECEXP ( op , 0 , 0 ) ; bool inc_p = true ; bool wb_p = base_reg_adjustment_p ( first_elt , & base_reg , & offset ) ; if ( GET_CODE ( XVECEXP ( op , 0 , end ) ) == RETURN ) end -- ; start = wb_p ? 1 : 0 ; for ( i = start ; i <= end ; i ++ ) { int regno ; rtx reg , mem , elt = XVECEXP ( op , 0 , i ) ; if ( GET_CODE ( elt ) != SET ) return false ; reg = load_p ? SET_DEST ( elt ) : SET_SRC ( elt ) ; mem = load_p ? SET_SRC ( elt ) : SET_DEST ( elt ) ; if ( ! REG_P ( reg ) || ! MEM_P ( mem ) ) return false ; regno = REGNO ( reg ) ; if ( ! nios2_ldstwm_regset_p ( regno , & regset ) ) return false ; if ( wb_p ) inc_p = INTVAL ( offset ) > 0 ; else if ( i == start ) { rtx first_base , first_offset ; if ( ! split_mem_address ( XEXP ( mem , 0 ) , & first_base , & first_offset ) ) return false ; base_reg = first_base ; inc_p = INTVAL ( first_offset ) >= 0 ; } if ( load_p && regno == ( int ) REGNO ( base_reg ) ) return false ; if ( last_regno >= 0 ) { if ( inc_p && last_regno >= regno ) return false ; if ( ! inc_p && last_regno <= regno ) return false ; } last_regno = regno ; } return true ; } </s>

Main function to implement ldwm_operation/stwm_operation predicates that check ldwm/stwm insn pattern integrity .


<s>
static
void
rs6000_output_savres_externs
(
FILE
*
file
)
{
rs6000_stack_t
*
info
=
rs6000_stack_info
(
)
;
if
(
TARGET_DEBUG_STACK
)
debug_stack_info
(
info
)
;
if
(
info
->
first_fp_reg_save
<
64
&&
!
TARGET_MACHO
&&
!
TARGET_ELF
)
{
char
*
name
;
int
regno
=
info
->
first_fp_reg_save
32
;
if
(
(
info
->
savres_strategy
&
SAVE_INLINE_FPRS
)
==
0
)
{
bool
lr
=
(
info
->
savres_strategy
&
SAVE_NOINLINE_FPRS_SAVES_LR
)
!=
0
;
int
sel
=
SAVRES_SAVE
|
SAVRES_FPR
|
(
lr
SAVRES_LR
:
0
)
;
name
=
rs6000_savres_routine_name
(
info
,
regno
,
sel
)
;
fprintf
(
file
,
"\t.extern %s\n"
,
name
)
;
}
if
(
(
info
->
savres_strategy
&
REST_INLINE_FPRS
)
==
0
)
{
bool
lr
=
(
info
->
savres_strategy
&
REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
)
==
0
;
int
sel
=
SAVRES_FPR
|
(
lr
SAVRES_LR
:
0
)
;
name
=
rs6000_savres_routine_name
(
info
,
regno
,
sel
)
;
fprintf
(
file
,
"\t.extern %s\n"
,
name
)
;
}
}
}
</s>

Output .extern statements for the save/restore routines we use .


<s> void AMDGPUAsmPrinter :: emitFunctionEntryLabel ( ) { if ( TM . getTargetTriple ( ) . getOS ( ) == Triple :: AMDHSA && isHsaAbiVersion3AndAbove ( getGlobalSTI ( ) ) ) { AsmPrinter :: emitFunctionEntryLabel ( ) ; return ; } const SIMachineFunctionInfo * MFI = MF -> getInfo < SIMachineFunctionInfo > ( ) ; const GCNSubtarget & STM = MF -> getSubtarget < GCNSubtarget > ( ) ; if ( MFI -> isEntryFunction ( ) && STM . isAmdHsaOrMesa ( MF -> getFunction ( ) ) ) { SmallString < 128 > SymbolName ; getNameWithPrefix ( SymbolName , & MF -> getFunction ( ) ) , getTargetStreamer ( ) -> EmitAMDGPUSymbolType ( SymbolName , ELF :: STT_AMDGPU_HSA_KERNEL ) ; } if ( DumpCodeInstEmitter ) { DisasmLines . push_back ( MF -> getName ( ) . str ( ) + ":" ) ; DisasmLineMaxLen = std :: max ( DisasmLineMaxLen , DisasmLines . back ( ) . size ( ) ) ; HexLines . push_back ( "" ) ; } AsmPrinter :: emitFunctionEntryLabel ( ) ; } </s>

EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function .

AMDGPU AMDGPU SI SI 128 AMDGPU AMDGPU ":" ""


<s> bool HexagonSplitConst32AndConst64 :: runOnMachineFunction ( MachineFunction & Fn ) { auto & HST = Fn . getSubtarget < HexagonSubtarget > ( ) ; auto & HTM = static_cast < const HexagonTargetMachine & > ( Fn . getTarget ( ) ) ; auto & TLOF = * HTM . getObjFileLowering ( ) ; if ( HST . useSmallData ( ) && TLOF . isSmallDataEnabled ( ) ) return false ; const TargetInstrInfo * TII = HST . getInstrInfo ( ) ; const TargetRegisterInfo * TRI = HST . getRegisterInfo ( ) ; for ( MachineBasicBlock & B : Fn ) { for ( auto I = B . begin ( ) , E = B . end ( ) ; I != E ; ) { MachineInstr & MI = * I ; ++ I ; unsigned Opc = MI . getOpcode ( ) ; if ( Opc == Hexagon :: CONST32 ) { unsigned DestReg = MI . getOperand ( 0 ) . getReg ( ) ; uint64_t ImmValue = MI . getOperand ( 1 ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( B , MI , DL , TII -> get ( Hexagon :: A2_tfrsi ) , DestReg ) . addImm ( ImmValue ) ; B . erase ( & MI ) ; } else if ( Opc == Hexagon :: CONST64 ) { unsigned DestReg = MI . getOperand ( 0 ) . getReg ( ) ; int64_t ImmValue = MI . getOperand ( 1 ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; unsigned DestLo = TRI -> getSubReg ( DestReg , Hexagon :: isub_lo ) ; unsigned DestHi = TRI -> getSubReg ( DestReg , Hexagon :: isub_hi ) ; int32_t LowWord = ( ImmValue & 0xFFFFFFFF ) ; int32_t HighWord = ( ImmValue >> 32 ) & 0xFFFFFFFF ; BuildMI ( B , MI , DL , TII -> get ( Hexagon :: A2_tfrsi ) , DestLo ) . addImm ( LowWord ) ; BuildMI ( B , MI , DL , TII -> get ( Hexagon :: A2_tfrsi ) , DestHi ) . addImm ( HighWord ) ; B . erase ( & MI ) ; } } } return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool AMDGPUPassConfig :: addPreISel ( ) { const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; addPass ( createFlattenCFGPass ( ) ) ; if ( ST . getGeneration ( ) > AMDGPUSubtarget :: NORTHERN_ISLANDS ) { addPass ( createSITypeRewriter ( ) ) ; addPass ( createStructurizeCFGPass ( ) ) ; addPass ( createSIAnnotateControlFlowPass ( ) ) ; } else { addPass ( createR600TextureIntrinsicsReplacer ( ) ) ; } return false ; } </s>


"Basic block should contain at least a RET but is empty"


<s> void spu_split_convert ( rtx ops [ ] ) { if ( REGNO ( ops [ 0 ] ) == REGNO ( ops [ 1 ] ) ) emit_note ( NOTE_INSN_DELETED ) ; else { rtx op0 = gen_rtx_REG ( TImode , REGNO ( ops [ 0 ] ) ) ; rtx op1 = gen_rtx_REG ( TImode , REGNO ( ops [ 1 ] ) ) ; emit_insn ( gen_move_insn ( op0 , op1 ) ) ; } } </s>

After reload , just change the convert into a move instruction or a dead instruction .


<s>
static
void
mn10300_asm_output_mi_thunk
(
FILE
*
file
,
tree
thunk_fndecl
ATTRIBUTE_UNUSED
,
HOST_WIDE_INT
delta
,
HOST_WIDE_INT
vcall_offset
,
tree
function
)
{
const
char
*
fnname
=
IDENTIFIER_POINTER
(
DECL_ASSEMBLER_NAME
(
thunk_fndecl
)
)
;
const
char
*
_this
;
assemble_start_function
(
thunk_fndecl
,
fnname
)
;
if
(
aggregate_value_p
(
TREE_TYPE
(
TREE_TYPE
(
function
)
)
,
function
)
)
_this
=
reg_names
[
FIRST_ARGUMENT_REGNUM
+
1
]
;
else
_this
=
reg_names
[
FIRST_ARGUMENT_REGNUM
]
;
fprintf
(
file
,
"\t%s Thunk Entry Point:\n"
,
ASM_COMMENT_START
)
;
if
(
delta
)
fprintf
(
file
,
"\tadd %d, %s\n"
,
(
int
)
delta
,
_this
)
;
if
(
vcall_offset
)
{
const
char
*
scratch
=
reg_names
[
FIRST_ADDRESS_REGNUM
+
1
]
;
fprintf
(
file
,
"\tmov %s, %s\n"
,
_this
,
scratch
)
;
fprintf
(
file
,
"\tmov (%s), %s\n"
,
scratch
,
scratch
)
;
fprintf
(
file
,
"\tadd %d, %s\n"
,
(
int
)
vcall_offset
,
scratch
)
;
fprintf
(
file
,
"\tmov (%s), %s\n"
,
scratch
,
scratch
)
;
fprintf
(
file
,
"\tadd %s, %s\n"
,
scratch
,
_this
)
;
}
fputs
(
"\tjmp "
,
file
)
;
assemble_name
(
file
,
XSTR
(
XEXP
(
DECL_RTL
(
function
)
,
0
)
,
0
)
)
;
putc
(
'\n'
,
file
)
;
assemble_end_function
(
thunk_fndecl
,
fnname
)
;
}
</s>

Output the assembler code for a C++ thunk function . THUNK_DECL is the declaration for the thunk function itself , FUNCTION is the decl for the target function . DELTA is an immediate constant offset to be added to the THIS parameter . If VCALL_OFFSET is nonzero the word at the adjusted address * ( * THIS ' + VCALL_OFFSET ) should be additionally added to THIS . Finally jump to the entry point of FUNCTION .


<s>
SDValue
XCoreTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
BR_JT
:
return
LowerBR_JT
(
Op
,
DAG
)
;
case
ISD
::
LOAD
:
return
LowerLOAD
(
Op
,
DAG
)
;
case
ISD
::
STORE
:
return
LowerSTORE
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
VAARG
:
return
LowerVAARG
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
SMUL_LOHI
:
return
LowerSMUL_LOHI
(
Op
,
DAG
)
;
case
ISD
::
UMUL_LOHI
:
return
LowerUMUL_LOHI
(
Op
,
DAG
)
;
case
ISD
::
ADD
:
case
ISD
::
SUB
:
return
ExpandADDSUB
(
Op
.
getNode
(
)
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
return
SDValue
(
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

XCore
XCore
ISD::GlobalAddress
ISD::GlobalTLSAddress
ISD::BlockAddress
ISD::ConstantPool
ISD::BR_JT
ISD::LOAD
ISD::STORE
ISD::SELECT_CC
ISD::VAARG
ISD::VASTART
ISD::SMUL_LOHI
ISD::UMUL_LOHI
ISD::ADD
ISD::SUB
ISD::FRAMEADDR
"unimplemented operand"


<s> bool aarch64_cannot_change_mode_class ( machine_mode from , machine_mode to , enum reg_class rclass ) { return ( reg_classes_intersect_p ( FP_REGS , rclass ) && GET_MODE_SIZE ( to ) == UNITS_PER_WORD && GET_MODE_SIZE ( from ) > UNITS_PER_WORD ) ; } </s>

Implement target hook CANNOT_CHANGE_MODE_CLASS .


<s> static machine_mode c6x_preferred_simd_mode ( scalar_mode mode ) { switch ( mode ) { case E_HImode : return V2HImode ; case E_QImode : return V4QImode ; default : return word_mode ; } } </s>


<s> static void filter_insns_above ( basic_block bb , int max_uid ) { rtx_insn * insn , * next ; bool prev_ti = false ; int prev_cycle = - 1 ; FOR_BB_INSNS_SAFE ( bb , insn , next ) { int this_cycle ; if ( ! NONDEBUG_INSN_P ( insn ) ) continue ; if ( insn == BB_END ( bb ) ) return ; this_cycle = insn_get_clock ( insn ) ; if ( prev_ti && this_cycle == prev_cycle ) { gcc_assert ( GET_MODE ( insn ) != TImode ) ; PUT_MODE ( insn , TImode ) ; } prev_ti = false ; if ( INSN_UID ( insn ) >= max_uid ) { if ( GET_MODE ( insn ) == TImode ) { prev_ti = true ; prev_cycle = this_cycle ; } delete_insn ( insn ) ; } } } </s>

Examine the insns in BB and remove all which have a uid greater or equal to MAX_UID .


<s> bool HexagonInstrInfo :: isIndirectCall ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { case Hexagon :: J2_callr : case Hexagon :: J2_callrf : case Hexagon :: J2_callrt : case Hexagon :: PS_call_nr : return true ; } return false ; } </s>

Return true if the callsite is an indirect call .


<s> bool AArch64PassConfig :: addPreEmitPass ( ) { addPass ( & UnpackMachineBundlesID ) ; addPass ( createAArch64BranchFixupPass ( ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> MachineInstr & ARMBaseInstrInfo :: duplicate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator InsertBefore , const MachineInstr & Orig ) const { MachineInstr & Cloned = TargetInstrInfo :: duplicate ( MBB , InsertBefore , Orig ) ; MachineBasicBlock :: instr_iterator I = Cloned . getIterator ( ) ; for ( ; ; ) { switch ( I -> getOpcode ( ) ) { case ARM :: tLDRpci_pic : case ARM :: t2LDRpci_pic : { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CPI = I -> getOperand ( 1 ) . getIndex ( ) ; unsigned PCLabelId = duplicateCPV ( MF , CPI ) ; I -> getOperand ( 1 ) . setIndex ( CPI ) ; I -> getOperand ( 2 ) . setImm ( PCLabelId ) ; break ; } } if ( ! I -> isBundledWithSucc ( ) ) break ; ++ I ; } return Cloned ; } </s>

Clones instruction or the whole instruction bundle Orig and insert into MBB before InsertBefore .


<s> unsigned PPCRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const PPCFrameLowering * TFI = getFrameLowering ( MF ) ; const unsigned DefaultSafety = 1 ; switch ( RC -> getID ( ) ) { default : return 0 ; case PPC :: G8RC_NOX0RegClassID : case PPC :: GPRC_NOR0RegClassID : case PPC :: G8RCRegClassID : case PPC :: GPRCRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 32 - FP - DefaultSafety ; } case PPC :: F8RCRegClassID : case PPC :: F4RCRegClassID : case PPC :: QFRCRegClassID : case PPC :: QSRCRegClassID : case PPC :: QBRCRegClassID : case PPC :: VRRCRegClassID : case PPC :: VFRCRegClassID : case PPC :: VSLRCRegClassID : return 32 - DefaultSafety ; case PPC :: VSRCRegClassID : case PPC :: VSFRCRegClassID : case PPC :: VSSRCRegClassID : return 64 - DefaultSafety ; case PPC :: CRRCRegClassID : return 8 - DefaultSafety ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s>
void
Cpu0InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
=
0
,
ZeroReg
=
0
;
if
(
Cpu0
::
CPURegsRegClass
.
contains
(
DestReg
)
)
{
if
(
Cpu0
::
CPURegsRegClass
.
contains
(
SrcReg
)
)
Opc
=
Cpu0
::
ADD
,
ZeroReg
=
Cpu0
::
ZERO
;
else
if
(
SrcReg
==
Cpu0
::
HI
)
Opc
=
Cpu0
::
MFHI
,
SrcReg
=
0
;
else
if
(
SrcReg
==
Cpu0
::
LO
)
Opc
=
Cpu0
::
MFLO
,
SrcReg
=
0
;
}
else
if
(
Cpu0
::
CPURegsRegClass
.
contains
(
SrcReg
)
)
{
if
(
DestReg
==
Cpu0
::
HI
)
Opc
=
Cpu0
::
MTHI
,
DestReg
=
0
;
else
if
(
DestReg
==
Cpu0
::
LO
)
Opc
=
Cpu0
::
MTLO
,
DestReg
=
0
;
}
assert
(
Opc
&&
"Cannot copy registers"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
)
;
if
(
DestReg
)
MIB
.
addReg
(
DestReg
,
RegState
::
Define
)
;
if
(
ZeroReg
)
MIB
.
addReg
(
ZeroReg
)
;
if
(
SrcReg
)
MIB
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> void ARMTargetStreamer :: emitInst ( uint32_t Inst , char Suffix ) { } </s>

Callback used to implement the .inst directive .


"optionally flag setting instruction missing optional def operand"

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


<s>
bool
NyuziInstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
TBB
=
nullptr
;
FBB
=
nullptr
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
if
(
I
==
MBB
.
begin
(
)
)
return
false
;
I
;
while
(
true
)
{
bool
CantAnalyze
=
false
;
while
(
I
->
isDebugValue
(
)
)
{
if
(
I
==
MBB
.
begin
(
)
)
return
false
;
I
;
}
if
(
!
I
->
isTerminator
(
)
)
break
;
if
(
isUncondBranchOpcode
(
I
->
getOpcode
(
)
)
)
{
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
}
else
if
(
isCondBranchOpcode
(
I
->
getOpcode
(
)
)
)
{
if
(
!
Cond
.
empty
(
)
)
return
true
;
assert
(
!
FBB
&&
"FBB should have been null."
)
;
FBB
=
TBB
;
TBB
=
I
->
getOperand
(
1
)
.
getMBB
(
)
;
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
I
->
getOpcode
(
)
)
)
;
Cond
.
push_back
(
I
->
getOperand
(
0
)
)
;
}
else
if
(
I
->
isReturn
(
)
)
{
CantAnalyze
=
true
;
}
else
{
return
true
;
}
if
(
isUncondBranchOpcode
(
I
->
getOpcode
(
)
)
)
{
Cond
.
clear
(
)
;
FBB
=
nullptr
;
if
(
AllowModify
)
{
MachineBasicBlock
::
iterator
DI
=
std
::
next
(
I
)
;
while
(
DI
!=
MBB
.
end
(
)
)
{
MachineInstr
&
InstToDelete
=
*
DI
;
++
DI
;
InstToDelete
.
eraseFromParent
(
)
;
}
}
}
if
(
CantAnalyze
)
return
true
;
if
(
I
==
MBB
.
begin
(
)
)
return
false
;
I
;
}
return
false
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> unsigned GCNHazardRecognizer :: PreEmitNoops ( MachineInstr * MI ) { int WaitStates = std :: max ( 0 , checkAnyInstHazards ( MI ) ) ; if ( SIInstrInfo :: isSMRD ( * MI ) ) return std :: max ( WaitStates , checkSMRDHazards ( MI ) ) ; if ( SIInstrInfo :: isVALU ( * MI ) ) WaitStates = std :: max ( WaitStates , checkVALUHazards ( MI ) ) ; if ( SIInstrInfo :: isVMEM ( * MI ) || SIInstrInfo :: isFLAT ( * MI ) ) WaitStates = std :: max ( WaitStates , checkVMEMHazards ( MI ) ) ; if ( SIInstrInfo :: isDPP ( * MI ) ) WaitStates = std :: max ( WaitStates , checkDPPHazards ( MI ) ) ; if ( isDivFMas ( MI -> getOpcode ( ) ) ) WaitStates = std :: max ( WaitStates , checkDivFMasHazards ( MI ) ) ; if ( isRWLane ( MI -> getOpcode ( ) ) ) WaitStates = std :: max ( WaitStates , checkRWLaneHazards ( MI ) ) ; if ( isSGetReg ( MI -> getOpcode ( ) ) ) return std :: max ( WaitStates , checkGetRegHazards ( MI ) ) ; if ( isSSetReg ( MI -> getOpcode ( ) ) ) return std :: max ( WaitStates , checkSetRegHazards ( MI ) ) ; if ( isRFE ( MI -> getOpcode ( ) ) ) return std :: max ( WaitStates , checkRFEHazards ( MI ) ) ; if ( ST . hasReadM0MovRelInterpHazard ( ) && ( TII . isVINTRP ( * MI ) || isSMovRel ( MI -> getOpcode ( ) ) ) ) return std :: max ( WaitStates , checkReadM0Hazards ( MI ) ) ; if ( ST . hasReadM0SendMsgHazard ( ) && isSendMsgTraceDataOrGDS ( * MI ) ) return std :: max ( WaitStates , checkReadM0Hazards ( MI ) ) ; return WaitStates ; } </s>

PreEmitNoops - This callback is invoked prior to emitting an instruction .


<s> static bool s390_valid_target_attribute_p ( tree fndecl , tree ARG_UNUSED ( name ) , tree args , int ARG_UNUSED ( flags ) ) { struct gcc_options func_options , func_options_set ; tree new_target , new_optimize ; bool ret = true ; if ( TREE_VALUE ( args ) && TREE_CODE ( TREE_VALUE ( args ) ) == STRING_CST && TREE_CHAIN ( args ) == NULL_TREE && strcmp ( TREE_STRING_POINTER ( TREE_VALUE ( args ) ) , "default" ) == 0 ) return true ; tree old_optimize = build_optimization_node ( & global_options , & global_options_set ) ; tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( ! func_optimize ) func_optimize = old_optimize ; memset ( & func_options , 0 , sizeof ( func_options ) ) ; init_options_struct ( & func_options , NULL ) ; lang_hooks . init_options_struct ( & func_options ) ; memset ( & func_options_set , 0 , sizeof ( func_options_set ) ) ; cl_optimization_restore ( & func_options , & func_options_set , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_restore ( & func_options , & func_options_set , TREE_TARGET_OPTION ( target_option_default_node ) ) ; new_target = s390_valid_target_attribute_tree ( args , & func_options , & global_options_set , ( args == current_target_pragma ) ) ; new_optimize = build_optimization_node ( & func_options , & func_options_set ) ; if ( new_target == error_mark_node ) ret = false ; else if ( fndecl && new_target ) { DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = new_target ; if ( old_optimize != new_optimize ) DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) = new_optimize ; } return ret ; } </s>

Hook to validate attribute ( ( target ( `` string '' ) ) ) .


<s> int X86TTIImpl :: getIntImmCost ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; unsigned ImmIdx = ~ 0U ; switch ( Opcode ) { default : return TTI :: TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: Store : ImmIdx = 0 ; break ; case Instruction :: And : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 && isUInt < 32 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; case Instruction :: Add : case Instruction :: Sub : case Instruction :: Mul : case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : case Instruction :: Or : case Instruction :: Xor : case Instruction :: ICmp : ImmIdx = 1 ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == 1 ) return TTI :: TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: IntToPtr : case Instruction :: PtrToInt : case Instruction :: BitCast : case Instruction :: PHI : case Instruction :: Call : case Instruction :: Select : case Instruction :: Ret : case Instruction :: Load : break ; } if ( Idx == ImmIdx ) { int NumConstants = ( BitSize + 63 ) / 64 ; int Cost = X86TTIImpl :: getIntImmCost ( Imm , Ty ) ; return ( Cost <= NumConstants * TTI :: TCC_Basic ) ? static_cast < int > ( TTI :: TCC_Free ) : Cost ; } return X86TTIImpl :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


"Optimize addressing mode of load/store"

getPassName - Return a nice clean name for a pass .


<s> const MCPhysReg * PPCRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const PPCSubtarget & Subtarget = MF -> getSubtarget < PPCSubtarget > ( ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: AnyReg ) { if ( Subtarget . hasVSX ( ) ) return CSR_64_AllRegs_VSX_SaveList ; if ( Subtarget . hasAltivec ( ) ) return CSR_64_AllRegs_Altivec_SaveList ; return CSR_64_AllRegs_SaveList ; } if ( Subtarget . isDarwinABI ( ) ) return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_SaveList : CSR_Darwin64_SaveList ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_SaveList : CSR_Darwin32_SaveList ) ; if ( TM . isPPC64 ( ) && MF -> getInfo < PPCFunctionInfo > ( ) -> isSplitCSR ( ) ) return CSR_SRV464_TLS_PE_SaveList ; bool SaveR2 = MF -> getRegInfo ( ) . isAllocatable ( PPC :: X2 ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: Cold ) { return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? ( SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList : CSR_SVR64_ColdCC_Altivec_SaveList ) : ( SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList : CSR_SVR64_ColdCC_SaveList ) ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR32_ColdCC_Altivec_SaveList : CSR_SVR32_ColdCC_SaveList ) ; } return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? ( SaveR2 ? CSR_SVR464_R2_Altivec_SaveList : CSR_SVR464_Altivec_SaveList ) : ( SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList ) ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR432_Altivec_SaveList : CSR_SVR432_SaveList ) ; } </s>

PowerPC PPC PPC PPC PPC PPC PPC PPC::X2 PPC PPC


<s> unsigned JVMRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return 0 ; } </s>


<s>
void
AArch64AsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
if
(
!
Value
)
return
;
unsigned
Kind
=
Fixup
.
getKind
(
)
;
if
(
Kind
>=
FirstLiteralRelocationKind
)
return
;
unsigned
NumBytes
=
getFixupKindNumBytes
(
Kind
)
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
int64_t
SignedValue
=
static_cast
<
int64_t
>
(
Value
)
;
Value
=
adjustFixupValue
(
Fixup
,
Target
,
Value
,
Ctx
,
TheTriple
,
IsResolved
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
unsigned
FulleSizeInBytes
=
getFixupKindContainereSizeInBytes
(
Fixup
.
getKind
(
)
)
;
if
(
FulleSizeInBytes
==
0
)
{
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
else
{
assert
(
(
Offset
+
FulleSizeInBytes
)
<=
Data
.
size
(
)
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FulleSizeInBytes
&&
"Invalid fixup size!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
FulleSizeInBytes
1
i
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
AArch64MCExpr
::
VariantKind
RefKind
=
static_cast
<
AArch64MCExpr
::
VariantKind
>
(
Target
.
getRefKind
(
)
)
;
if
(
AArch64MCExpr
::
getSymbolLoc
(
RefKind
)
==
AArch64MCExpr
::
VK_SABS
||
(
!
RefKind
&&
Fixup
.
getTargetKind
(
)
==
AArch64
::
fixup_aarch64_movw
)
)
{
if
(
SignedValue
<
0
)
Data
[
Offset
+
3
]
&=
~
(
1
<<
6
)
;
else
Data
[
Offset
+
3
]
|=
(
1
<<
6
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> unsigned AMDGPUIntrinsicInfo :: lookupName ( const char * Name , unsigned Len ) const { if ( ! StringRef ( Name , Len ) . startswith ( "llvm." ) ) return 0 ; AMDGPUIntrinsic :: ID IntrinsicID = ( AMDGPUIntrinsic :: ID ) Intrinsic :: not_intrinsic ; IntrinsicID = getIntrinsicForGCCBuiltin ( "AMDGPU" , Name ) ; if ( IntrinsicID != ( AMDGPUIntrinsic :: ID ) Intrinsic :: not_intrinsic ) { return IntrinsicID ; } return 0 ; } </s>


<s> bool MOSTargetLowering :: isZExtFree ( Type * SrcTy , Type * DstTy ) const { if ( ! SrcTy -> isIntegerTy ( ) || ! DstTy -> isIntegerTy ( ) ) return false ; return SrcTy -> getPrimitiveSizeInBits ( ) < DstTy -> getPrimitiveSizeInBits ( ) ; } </s>

Return true if zero-extending the specific node Val to type VT2 is free ( either because it 's implicitly zero-extended such as ARM ldrb / ldrh or because it 's folded such as X86 zero-extending loads ) .


<s> bool PatmosSinglePathInfo :: isReachable ( const MachineFunction & MF ) { return PatmosSinglePathInfo :: isReachable ( MF . getFunction ( ) ) ; } </s>

Returns true if instruction is reachable from entry .


<s> static struct machine_function * ix86_init_machine_status ( void ) { struct machine_function * f ; f = ggc_cleared_alloc < machine_function > ( ) ; f -> call_abi = ix86_abi ; return f ; } </s>

Clear stack slot assignments remembered from previous functions . This is called from INIT_EXPANDERS once before RTL is emitted for each function .


<s> void Thumb2InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( RC == & ARM :: GPRRegClass || RC == & ARM :: tGPRRegClass || RC == & ARM :: tcGPRRegClass || RC == & ARM :: rGPRRegClass || RC == & ARM :: GPRnopcRegClass ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2STRi12 ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } if ( ARM :: GPRPairRegClass . hasSubClassEq ( RC ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( SrcReg , & ARM :: GPRPair_with_gsub_1_in_rGPRRegClass ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( ARM :: t2STRDi8 ) ) ; AddDReg ( MIB , SrcReg , ARM :: gsub_0 , getKillRegState ( isKill ) , TRI ) ; AddDReg ( MIB , SrcReg , ARM :: gsub_1 , 0 , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ; AddDefaultPred ( MIB ) ; return ; } ARMBaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg , isKill , FI , RC , TRI ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool ARMBaseRegisterInfo :: hasReservedCallFrame ( MachineFunction & MF ) const { const MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; unsigned CFSize = FFI -> getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( 1 << 12 ) - 1 ) / 2 ) return false ; return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> static void paired_emit_vector_compare ( enum rtx_code rcode , rtx dest , rtx op0 , rtx op1 , rtx cc_op0 , rtx cc_op1 ) { rtx tmp = gen_reg_rtx ( V2SFmode ) ; rtx tmp1 , max , min ; gcc_assert ( TARGET_PAIRED_FLOAT ) ; gcc_assert ( GET_MODE ( op0 ) == GET_MODE ( op1 ) ) ; switch ( rcode ) { case LT : case LTU : paired_emit_vector_compare ( GE , dest , op1 , op0 , cc_op0 , cc_op1 ) ; return ; case GE : case GEU : emit_insn ( gen_subv2sf3 ( tmp , cc_op0 , cc_op1 ) ) ; emit_insn ( gen_selv2sf4 ( dest , tmp , op0 , op1 , CONST0_RTX ( SFmode ) ) ) ; return ; case LE : case LEU : paired_emit_vector_compare ( GE , dest , op0 , op1 , cc_op1 , cc_op0 ) ; return ; case GT : paired_emit_vector_compare ( LE , dest , op1 , op0 , cc_op0 , cc_op1 ) ; return ; case EQ : tmp1 = gen_reg_rtx ( V2SFmode ) ; max = gen_reg_rtx ( V2SFmode ) ; min = gen_reg_rtx ( V2SFmode ) ; gen_reg_rtx ( V2SFmode ) ; emit_insn ( gen_subv2sf3 ( tmp , cc_op0 , cc_op1 ) ) ; emit_insn ( gen_selv2sf4 ( max , tmp , cc_op0 , cc_op1 , CONST0_RTX ( SFmode ) ) ) ; emit_insn ( gen_subv2sf3 ( tmp , cc_op1 , cc_op0 ) ) ; emit_insn ( gen_selv2sf4 ( min , tmp , cc_op0 , cc_op1 , CONST0_RTX ( SFmode ) ) ) ; emit_insn ( gen_subv2sf3 ( tmp1 , min , max ) ) ; emit_insn ( gen_selv2sf4 ( dest , tmp1 , op0 , op1 , CONST0_RTX ( SFmode ) ) ) ; return ; case NE : paired_emit_vector_compare ( EQ , dest , op1 , op0 , cc_op0 , cc_op1 ) ; return ; case UNLE : paired_emit_vector_compare ( LE , dest , op1 , op0 , cc_op0 , cc_op1 ) ; return ; case UNLT : paired_emit_vector_compare ( LT , dest , op1 , op0 , cc_op0 , cc_op1 ) ; return ; case UNGE : paired_emit_vector_compare ( GE , dest , op1 , op0 , cc_op0 , cc_op1 ) ; return ; case UNGT : paired_emit_vector_compare ( GT , dest , op1 , op0 , cc_op0 , cc_op1 ) ; return ; default : gcc_unreachable ( ) ; } return ; } </s>

Emit vector compare for code RCODE . DEST is destination , OP1 and OP2 are two VEC_COND_EXPR operands , CC_OP0 and CC_OP1 are the two operands for the relation operation COND . This is a recursive function .


<s> static bool insn_terminates_group_p ( rtx_insn * insn , enum group_termination which_group ) { bool first , last ; if ( ! insn ) return false ; first = insn_must_be_first_in_group ( insn ) ; last = insn_must_be_last_in_group ( insn ) ; if ( first && last ) return true ; if ( which_group == current_group ) return last ; else if ( which_group == previous_group ) return first ; return false ; } </s>

Return whether the presence of INSN causes a dispatch group termination of group WHICH_GROUP . If WHICH_GROUP == current_group , this function will return true if INSN causes the termination of the current group ( i.e , the dispatch group to which INSN belongs ) . This means that INSN will be the last insn in the group it belongs to . If WHICH_GROUP == previous_group , this function will return true if INSN causes the termination of the previous group ( i.e , the dispatch group that precedes the group to which INSN belongs ) . This means that INSN will be the first insn in the group it belongs to ) .


<s> void ix86_emit_fp_unordered_jump ( rtx label ) { rtx reg = gen_reg_rtx ( HImode ) ; rtx temp ; emit_insn ( gen_x86_fnstsw_1 ( reg ) ) ; if ( TARGET_USE_SAHF ) { emit_insn ( gen_x86_sahf_1 ( reg ) ) ; temp = gen_rtx_REG ( CCmode , FLAGS_REG ) ; temp = gen_rtx_UNORDERED ( VOIDmode , temp , const0_rtx ) ; } else { emit_insn ( gen_testqi_ext_ccno_0 ( reg , GEN_INT ( 0x04 ) ) ) ; temp = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; temp = gen_rtx_NE ( VOIDmode , temp , const0_rtx ) ; } temp = gen_rtx_IF_THEN_ELSE ( VOIDmode , temp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; temp = gen_rtx_SET ( VOIDmode , pc_rtx , temp ) ; emit_jump_insn ( temp ) ; } </s>

Output code to perform a conditional jump to LABEL , if C2 flag in FP status register is set .


<s> static void mmix_init_libfuncs ( void ) { set_optab_libfunc ( ffs_optab , SImode , "__ffsdi2" ) ; } </s>

Unfortunately , by default __builtin_ffs is expanded to ffs for targets where INT_TYPE_SIZE < BITS_PER_WORD . That together with newlib since 2017-07-04 implementing ffs as __builtin_ffs leads to ( newlib ) ffs recursively calling itself . But , because of argument promotion , and with ffs we 're counting from the least bit , the libgcc equivalent for ffsl works equally well for int arguments , so just use that .


<s> void arc_secondary_reload_conv ( rtx reg , rtx mem , rtx scratch , bool store_p ) { rtx addr ; gcc_assert ( GET_CODE ( mem ) == MEM ) ; addr = XEXP ( mem , 0 ) ; emit_move_insn ( scratch , addr ) ; mem = replace_equiv_address_nv ( mem , scratch ) ; if ( store_p ) emit_insn ( gen_rtx_SET ( mem , reg ) ) ; else emit_insn ( gen_rtx_SET ( reg , mem ) ) ; return ; } </s>

Convert reloads using offsets that are too large to use indirect addressing .


<s> DecodeStatus LanaiDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & ) const { uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Bytes , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTableLanai32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { PostOperandDecodeAdjust ( Instr , Insn ) ; Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s> bool AMDGPULowerIntrinsics :: makeLIDRangeMetadata ( Function & F ) const { auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; const TargetMachine & TM = TPC -> getTM < TargetMachine > ( ) ; bool Changed = false ; for ( auto * U : F . users ( ) ) { auto * CI = dyn_cast < CallInst > ( U ) ; if ( ! CI ) continue ; Function * Caller = CI -> getParent ( ) -> getParent ( ) ; const AMDGPUSubtarget & ST = AMDGPUSubtarget :: get ( TM , * Caller ) ; Changed |= ST . makeLIDRangeMetadata ( CI ) ; } return Changed ; } </s>

Creates value range metadata on an workitemid . * intrinsic call or load .


<s>
unsigned
TMS320C64XInstrInfo
::
isStoreToStackSlot
(
const
MachineInstr
*
MI
,
int
&
FrameIndex
)
const
{
const
TargetInstrDesc
desc
=
MI
->
getDesc
(
)
;
if
(
desc
.
TSFlags
&
TMS320C64XII
::
is_memaccess
&&
desc
.
TSFlags
&
TMS320C64XII
::
is_store
)
{
if
(
MI
->
getOperand
(
0
)
.
getReg
(
)
==
TMS320C64X
::
B15
)
{
MachineOperand
op
=
MI
->
getOperand
(
1
)
;
if
(
op
.
isFI
(
)
)
{
FrameIndex
=
op
.
getIndex
(
)
;
return
true
;
}
else
{
llvm_unreachable
(
"Found store-to-stack sans "
"frame index operand"
)
;
}
}
}
return
false
;
}
</s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> bool mcore_gen_compare ( enum rtx_code code , rtx op0 , rtx op1 ) { rtx cc_reg = gen_rtx_REG ( CCmode , CC_REG ) ; bool invert ; if ( GET_CODE ( op1 ) == CONST_INT ) { HOST_WIDE_INT val = INTVAL ( op1 ) ; switch ( code ) { case GTU : if ( val == 0 ) code = NE ; break ; case GT : case LE : if ( CONST_OK_FOR_J ( val + 1 ) ) { op1 = GEN_INT ( val + 1 ) ; code = code == LE ? LT : GE ; } break ; default : break ; } } if ( CONSTANT_P ( op1 ) && GET_CODE ( op1 ) != CONST_INT ) op1 = force_reg ( SImode , op1 ) ; invert = false ; switch ( code ) { case EQ : code = NE ; invert = true ; case NE : if ( GET_CODE ( op1 ) == CONST_INT && ! CONST_OK_FOR_K ( INTVAL ( op1 ) ) ) op1 = force_reg ( SImode , op1 ) ; break ; case LE : code = GT ; invert = true ; case GT : if ( GET_CODE ( op1 ) == CONST_INT ) op1 = force_reg ( SImode , op1 ) ; break ; case GE : code = LT ; invert = true ; case LT : if ( GET_CODE ( op1 ) == CONST_INT && INTVAL ( op1 ) != 0 && ! CONST_OK_FOR_J ( INTVAL ( op1 ) ) ) op1 = force_reg ( SImode , op1 ) ; break ; case GTU : gcc_assert ( GET_CODE ( op1 ) != CONST_INT || INTVAL ( op1 ) != 0 ) ; code = LEU ; invert = true ; case LEU : if ( GET_CODE ( op1 ) == CONST_INT && INTVAL ( op1 ) != 0 ) op1 = force_reg ( SImode , op1 ) ; break ; case LTU : code = GEU ; invert = true ; case GEU : if ( GET_CODE ( op1 ) == CONST_INT && INTVAL ( op1 ) != 0 ) op1 = force_reg ( SImode , op1 ) ; break ; default : break ; } emit_insn ( gen_rtx_SET ( VOIDmode , cc_reg , gen_rtx_fmt_ee ( code , CCmode , op0 , op1 ) ) ) ; return invert ; } </s>

Prepare the operands for a comparison . Return whether the branch/setcc should reverse the operands .


<s> static bool arm_cannot_force_const_mem ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { rtx base , offset ; split_const ( x , & base , & offset ) ; if ( SYMBOL_REF_P ( base ) ) { if ( ( SYMBOL_REF_FLAGS ( base ) & SYMBOL_FLAG_FUNCTION ) && INTVAL ( offset ) != 0 ) return true ; if ( ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P && ! offset_within_block_p ( base , INTVAL ( offset ) ) ) return true ; } return arm_tls_referenced_p ( x ) ; } </s>


<s>
bool
AMDGPUAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Name
=
parseMnemonicSuffix
(
Name
)
;
Operands
.
push_back
(
AMDGPUOperand
::
CreateToken
(
this
,
Name
,
NameLoc
)
)
;
bool
IsMIMG
=
Name
.
startswith
(
"image_"
)
;
while
(
!
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
{
OperandMode
Mode
=
OperandMode_Default
;
if
(
IsMIMG
&&
isGFX10
(
)
&&
Operands
.
size
(
)
==
2
)
Mode
=
OperandMode_NSA
;
OperandMatchResultTy
Res
=
parseOperand
(
Operands
,
Name
,
Mode
)
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
Parser
.
Lex
(
)
;
if
(
Res
!=
MatchOperand_Success
)
{
checkUnsupportedInstruction
(
Name
,
NameLoc
)
;
if
(
!
Parser
.
hasPendingError
(
)
)
{
StringRef
Msg
=
(
Res
==
MatchOperand_ParseFail
)
"failed parsing operand."
:
"not a valid operand."
;
Error
(
getLexer
(
)
.
getLoc
(
)
,
Msg
)
;
}
while
(
!
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
{
Parser
.
Lex
(
)
;
}
return
true
;
}
}
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

AMDGPU
AMDGPU
AMDGPU
"image_"
2
"failed parsing operand."
"not a valid operand."


<s> bool GCNTTIImpl :: isAlwaysUniform ( const Value * V ) const { if ( const IntrinsicInst * Intrinsic = dyn_cast < IntrinsicInst > ( V ) ) { switch ( Intrinsic -> getIntrinsicID ( ) ) { default : return false ; case Intrinsic :: amdgcn_readfirstlane : case Intrinsic :: amdgcn_readlane : case Intrinsic :: amdgcn_icmp : case Intrinsic :: amdgcn_fcmp : return true ; } } return false ; } </s>

Whether Val will always return a uniform value regardless of its operands .


<s> int mcore_is_same_reg ( rtx x , rtx y ) { while ( GET_CODE ( x ) == SUBREG ) x = SUBREG_REG ( x ) ; while ( GET_CODE ( y ) == SUBREG ) y = SUBREG_REG ( y ) ; if ( GET_CODE ( x ) == REG && GET_CODE ( y ) == REG && REGNO ( x ) == REGNO ( y ) ) return 1 ; return 0 ; } </s>

Tell me if a pair of reg/subreg rtx 's actually refer to the same register . Note that the current version does n't worry about whether they are the same mode or note ( e.g. , a QImode in r2 matches an HImode in r2 matches an SImode in r2 . Might think in the future about whether we want to be able to say something about modes .


<s> unsigned PPCTargetLowering :: getPrefLoopAlignment ( MachineLoop * ML ) const { switch ( Subtarget . getMcpu ( ) ) { default : break ; case PPC :: MCPU_970 : case PPC :: MCPU_PWR4 : case PPC :: MCPU_PWR5 : case PPC :: MCPU_PWR5X : case PPC :: MCPU_PWR6 : case PPC :: MCPU_PWR6X : case PPC :: MCPU_PWR7 : case PPC :: MCPU_PWR8 : case PPC :: MCPU_PWR9 : { if ( ! ML ) break ; const PPCInstrInfo * TII = Subtarget . getInstrInfo ( ) ; uint64_t LoopSize = 0 ; for ( auto I = ML -> block_begin ( ) , IE = ML -> block_end ( ) ; I != IE ; ++ I ) for ( auto J = ( * I ) -> begin ( ) , JE = ( * I ) -> end ( ) ; J != JE ; ++ J ) { LoopSize += TII -> getInstSizeInBytes ( * J ) ; if ( LoopSize > 32 ) break ; } if ( LoopSize > 16 && LoopSize <= 32 ) return 5 ; break ; } } return TargetLowering :: getPrefLoopAlignment ( ML ) ; } </s>


"Can't store this register to stack slot"


<s> bool HexagonPassConfig :: addPreEmitPass ( ) { if ( ! DisableHardwareLoops ) { PM . add ( createHexagonFixupHwLoops ( ) ) ; } PM . add ( createHexagonExpandPredSpillCode ( getHexagonTargetMachine ( ) ) ) ; PM . add ( createHexagonSplitTFRCondSets ( getHexagonTargetMachine ( ) ) ) ; return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon


<s> int arc_label_align ( rtx_insn * label ) { int loop_align = LOOP_ALIGN ( LABEL ) ; if ( loop_align > align_labels_log ) { rtx_insn * prev = prev_nonnote_insn ( label ) ; if ( prev && NONJUMP_INSN_P ( prev ) && GET_CODE ( PATTERN ( prev ) ) == PARALLEL && recog_memoized ( prev ) == CODE_FOR_doloop_begin_i ) return loop_align ; } if ( align_labels_log < 1 ) { rtx_insn * next = next_nonnote_nondebug_insn ( label ) ; if ( INSN_P ( next ) && recog_memoized ( next ) >= 0 ) return 1 ; } return align_labels_log ; } </s>

Oddly enough , sometimes we get a zero overhead loop that branch shortening does n't think is a loop - observed with compile/pr24883.c -O3 -fomit-frame-pointer -funroll-loops . Make sure to include the alignment visible for branch shortening ( we actually align the loop insn before it , but that is equivalent since the loop insn is 4 byte long . )


<s> static bool aapcs_vfp_allocate ( CUMULATIVE_ARGS * pcum , machine_mode mode , const_tree type ATTRIBUTE_UNUSED ) { int rmode_size = MAX ( GET_MODE_SIZE ( pcum -> aapcs_vfp_rmode ) , GET_MODE_SIZE ( SFmode ) ) ; int shift = rmode_size / GET_MODE_SIZE ( SFmode ) ; unsigned mask = ( 1 << ( shift * pcum -> aapcs_vfp_rcount ) ) - 1 ; int regno ; for ( regno = 0 ; regno < NUM_VFP_ARG_REGS ; regno += shift ) if ( ( ( pcum -> aapcs_vfp_regs_free >> regno ) & mask ) == mask ) { pcum -> aapcs_vfp_reg_alloc = mask << regno ; if ( mode == BLKmode || ( mode == TImode && ! ( TARGET_NEON || TARGET_HAVE_MVE ) ) || ! arm_hard_regno_mode_ok ( FIRST_VFP_REGNUM + regno , mode ) ) { int i ; int rcount = pcum -> aapcs_vfp_rcount ; int rshift = shift ; machine_mode rmode = pcum -> aapcs_vfp_rmode ; rtx par ; if ( ! ( TARGET_NEON || TARGET_HAVE_MVE ) ) { if ( rmode == V2SImode ) rmode = DImode ; else if ( rmode == V4SImode ) { rmode = DImode ; rcount *= 2 ; rshift /= 2 ; } } par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( rcount ) ) ; for ( i = 0 ; i < rcount ; i ++ ) { rtx tmp = gen_rtx_REG ( rmode , FIRST_VFP_REGNUM + regno + i * rshift ) ; tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , GEN_INT ( i * GET_MODE_SIZE ( rmode ) ) ) ; XVECEXP ( par , 0 , i ) = tmp ; } pcum -> aapcs_reg = par ; } else pcum -> aapcs_reg = gen_rtx_REG ( mode , FIRST_VFP_REGNUM + regno ) ; return true ; } return false ; } </s>

Implement the allocate field in aapcs_cp_arg_layout . See the comment there for the behaviour of this function .


<s> bool PIC16Overlay :: runOnModule ( Module & M ) { CallGraph & CG = getAnalysis < CallGraph > ( ) ; CallGraphNode * ECN = CG . getExternalCallingNode ( ) ; MarkIndirectlyCalledFunctions ( M ) ; if ( ECN ) { DFSTraverse ( ECN , 0 ) ; } return false ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> MVT X86TargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT == MVT :: v32i1 && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return MVT :: v32i8 ; if ( VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i1 && Subtarget . hasAVX512 ( ) && ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) || ( VT . getVectorNumElements ( ) > 16 && ! Subtarget . hasBWI ( ) ) || ( VT . getVectorNumElements ( ) > 64 && Subtarget . hasBWI ( ) ) ) ) return MVT :: i8 ; if ( VT == MVT :: v64i1 && Subtarget . hasBWI ( ) && ! Subtarget . useAVX512Regs ( ) && CC != CallingConv :: X86_RegCall ) return MVT :: v32i1 ; if ( ( VT == MVT :: v32i16 || VT == MVT :: v64i8 ) && ! EnableOldKNLABI && Subtarget . useAVX512Regs ( ) && ! Subtarget . hasBWI ( ) ) return MVT :: v16i32 ; return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


<s> void addLOHDirective ( MCLOHType Kind , const MILOHArgs & Args ) { LOHContainerSet . push_back ( MILOHDirective ( Kind , Args ) ) ; LOHRelated . insert ( Args . begin ( ) , Args . end ( ) ) ; } </s>

Add a LOH directive of this Kind and this Args .


<s> static parallel * nvptx_find_par ( bb_insn_map_t * map , parallel * par , basic_block block ) { if ( block -> flags & BB_VISITED ) return par ; block -> flags |= BB_VISITED ; if ( rtx_insn * * endp = map -> get ( block ) ) { rtx_insn * end = * endp ; switch ( recog_memoized ( end ) ) { case CODE_FOR_return : return par ; case CODE_FOR_nvptx_forked : { unsigned mask = UINTVAL ( XVECEXP ( PATTERN ( end ) , 0 , 0 ) ) ; gcc_assert ( mask ) ; par = new parallel ( par , mask ) ; par -> forked_block = block ; par -> forked_insn = end ; if ( nvptx_needs_shared_bcast ( mask ) ) par -> fork_insn = nvptx_discover_pre ( block , CODE_FOR_nvptx_fork ) ; } break ; case CODE_FOR_nvptx_join : { unsigned mask = UINTVAL ( XVECEXP ( PATTERN ( end ) , 0 , 0 ) ) ; gcc_assert ( par -> mask == mask ) ; par -> join_block = block ; par -> join_insn = end ; if ( nvptx_needs_shared_bcast ( mask ) ) par -> joining_insn = nvptx_discover_pre ( block , CODE_FOR_nvptx_joining ) ; par = par -> parent ; } break ; default : gcc_unreachable ( ) ; } } if ( par ) par -> blocks . safe_push ( block ) ; else par = new parallel ( 0 , 0 ) ; edge e ; edge_iterator ei ; FOR_EACH_EDGE ( e , ei , block -> succs ) nvptx_find_par ( map , par , e -> dest ) ; return par ; } </s>

See also 'gcc/omp-oacc-neuter-broadcast.cc : omp_sese_find_par ' .


<s> bool isAndroid ( ) const { return IsAndroid ; } </s>


<s>
MCS51
::
Fixups
MCS51MCExpr
::
getFixupKind
(
)
const
{
MCS51
::
Fixups
Kind
=
MCS51
::
Fixups
::
LastTargetFixupKind
;
switch
(
getKind
(
)
)
{
case
VK_MCS51_LO8
:
Kind
=
isNegated
(
)
MCS51
::
fixup_lo8_ldi_neg
:
MCS51
::
fixup_lo8_ldi
;
break
;
case
VK_MCS51_HI8
:
Kind
=
isNegated
(
)
MCS51
::
fixup_hi8_ldi_neg
:
MCS51
::
fixup_hi8_ldi
;
break
;
case
VK_MCS51_HH8
:
Kind
=
isNegated
(
)
MCS51
::
fixup_hh8_ldi_neg
:
MCS51
::
fixup_hh8_ldi
;
break
;
case
VK_MCS51_HHI8
:
Kind
=
isNegated
(
)
MCS51
::
fixup_ms8_ldi_neg
:
MCS51
::
fixup_ms8_ldi
;
break
;
case
VK_MCS51_PM_LO8
:
Kind
=
isNegated
(
)
MCS51
::
fixup_lo8_ldi_pm_neg
:
MCS51
::
fixup_lo8_ldi_pm
;
break
;
case
VK_MCS51_PM_HI8
:
Kind
=
isNegated
(
)
MCS51
::
fixup_hi8_ldi_pm_neg
:
MCS51
::
fixup_hi8_ldi_pm
;
break
;
case
VK_MCS51_PM_HH8
:
Kind
=
isNegated
(
)
MCS51
::
fixup_hh8_ldi_pm_neg
:
MCS51
::
fixup_hh8_ldi_pm
;
break
;
case
VK_MCS51_PM
:
case
VK_MCS51_GS
:
Kind
=
MCS51
::
fixup_16_pm
;
break
;
case
VK_MCS51_LO8_GS
:
Kind
=
MCS51
::
fixup_lo8_ldi_gs
;
break
;
case
VK_MCS51_HI8_GS
:
Kind
=
MCS51
::
fixup_hi8_ldi_gs
;
break
;
case
VK_MCS51_None
:
llvm_unreachable
(
"Uninitialized expression"
)
;
}
return
Kind
;
}
</s>

getFixupKind - Get the fixup kind of this expression .


<s> static bool pa_function_value_regno_p ( const unsigned int regno ) { if ( regno == 28 || ( ! TARGET_SOFT_FLOAT && regno == 32 ) ) return true ; return false ; } </s>

Implement the TARGET_FUNCTION_VALUE_REGNO_P hook .


<s>
void
WebAssemblyInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
MCRegister
DestReg
,
MCRegister
SrcReg
,
bool
KillSrc
)
const
{
auto
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
const
TargetRegisterClass
*
RC
=
Register
::
isVirtualRegister
(
DestReg
)
MRI
.
getRegClass
(
DestReg
)
:
MRI
.
getTargetRegisterInfo
(
)
->
getMinimalPhysRegClass
(
DestReg
)
;
unsigned
CopyOpcode
;
if
(
RC
==
&
WebAssembly
::
I32RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_I32
;
else
if
(
RC
==
&
WebAssembly
::
I64RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_I64
;
else
if
(
RC
==
&
WebAssembly
::
F32RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_F32
;
else
if
(
RC
==
&
WebAssembly
::
F64RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_F64
;
else
if
(
RC
==
&
WebAssembly
::
V128RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_V128
;
else
if
(
RC
==
&
WebAssembly
::
FUNCREFRegClass
)
CopyOpcode
=
WebAssembly
::
COPY_FUNCREF
;
else
if
(
RC
==
&
WebAssembly
::
EXTERNREFRegClass
)
CopyOpcode
=
WebAssembly
::
COPY_EXTERNREF
;
else
if
(
RC
==
&
WebAssembly
::
EXNREFRegClass
)
CopyOpcode
=
WebAssembly
::
COPY_EXNREF
;
else
llvm_unreachable
(
"Unexpected register class"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
CopyOpcode
)
,
DestReg
)
.
addReg
(
SrcReg
,
KillSrc
RegState
::
Kill
:
0
)
;
}
</s>


<s> static machine_mode s390_promote_function_mode ( const_tree type , machine_mode mode , int * punsignedp , const_tree fntype ATTRIBUTE_UNUSED , int for_return ATTRIBUTE_UNUSED ) { if ( INTEGRAL_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) < UNITS_PER_LONG ) { if ( type != NULL_TREE && POINTER_TYPE_P ( type ) ) * punsignedp = POINTERS_EXTEND_UNSIGNED ; return Pmode ; } return mode ; } </s>

Function arguments and return values are promoted to word size .


<s> virtual const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> static void arm_asm_init_sections ( void ) { exception_section = get_unnamed_section ( 0 , output_section_asm_op , "\t.handlerdata" ) ; } </s>


<s>
void
LEGMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
if
(
Desc
.
getSize
(
)
!=
4
)
{
llvm_unreachable
(
"Unexpected instruction size!"
)
;
}
const
uint32_t
Binary
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
EmitConstant
(
Binary
,
Desc
.
getSize
(
)
,
OS
)
;
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .

LEG
LEG
4
"Unexpected instruction size!"


<s> bool AMDGPUAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == ".hsa_code_object_version" ) return ParseDirectiveHSACodeObjectVersion ( ) ; if ( IDVal == ".hsa_code_object_isa" ) return ParseDirectiveHSACodeObjectISA ( ) ; if ( IDVal == ".amd_kernel_code_t" ) return ParseDirectiveAMDKernelCodeT ( ) ; if ( IDVal == ".hsatext" || IDVal == ".text" ) return ParseSectionDirectiveHSAText ( ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool isReg ( ) const { return Kind == Register ; } </s>


<s> static SDValue LowerCallResult ( SDValue Chain , SDValue InFlag , const SmallVectorImpl < CCValAssign > & RVLocs , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { SmallVector < std :: pair < int , unsigned > , 4 > ResultMemLocs ; for ( unsigned i = 0 , e = RVLocs . size ( ) ; i != e ; ++ i ) { const CCValAssign & VA = RVLocs [ i ] ; if ( VA . isRegLoc ( ) ) { Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; ResultMemLocs . push_back ( std :: make_pair ( VA . getLocMemOffset ( ) , InVals . size ( ) ) ) ; InVals . push_back ( SDValue ( ) ) ; } } SmallVector < SDValue , 4 > MemOpChains ; for ( unsigned i = 0 , e = ResultMemLocs . size ( ) ; i != e ; ++ i ) { int offset = ResultMemLocs [ i ] . first ; unsigned index = ResultMemLocs [ i ] . second ; SDVTList VTs = DAG . getVTList ( MVT :: i32 , MVT :: Other ) ; SDValue Ops [ ] = { Chain , DAG . getConstant ( offset / 4 , dl , MVT :: i32 ) } ; SDValue load = DAG . getNode ( XCoreISD :: LDWSP , dl , VTs , Ops ) ; InVals [ index ] = load ; MemOpChains . push_back ( load . getValue ( 1 ) ) ; } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( ISD :: TokenFactor , dl , MVT :: Other , MemOpChains ) ; return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static unsigned int aarch64_function_arg_alignment ( machine_mode mode , const_tree type ) { if ( ! type ) return GET_MODE_ALIGNMENT ( mode ) ; if ( integer_zerop ( TYPE_SIZE ( type ) ) ) return 0 ; gcc_assert ( TYPE_MODE ( type ) == mode ) ; if ( ! AGGREGATE_TYPE_P ( type ) ) return TYPE_ALIGN ( TYPE_MAIN_VARIANT ( type ) ) ; if ( TREE_CODE ( type ) == ARRAY_TYPE ) return TYPE_ALIGN ( TREE_TYPE ( type ) ) ; unsigned int alignment = 0 ; for ( tree field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) if ( TREE_CODE ( field ) == FIELD_DECL ) alignment = std :: max ( alignment , DECL_ALIGN ( field ) ) ; return alignment ; } </s>

Given MODE and TYPE of a function argument , return the alignment in bits . The idea is to suppress any stronger alignment requested by the user and opt for the natural alignment ( specified in AAPCS64 \S 4.1 ) . This is a helper function for local use only .


<s>
void
AlphaInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
DestReg
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
if
(
RC
==
Alpha
::
F4RCRegisterClass
)
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Alpha
::
LDS
)
,
DestReg
)
.
addFrameIndex
(
FrameIdx
)
.
addReg
(
Alpha
::
F31
)
;
else
if
(
RC
==
Alpha
::
F8RCRegisterClass
)
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Alpha
::
LDT
)
,
DestReg
)
.
addFrameIndex
(
FrameIdx
)
.
addReg
(
Alpha
::
F31
)
;
else
if
(
RC
==
Alpha
::
GPRCRegisterClass
)
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Alpha
::
LDQ
)
,
DestReg
)
.
addFrameIndex
(
FrameIdx
)
.
addReg
(
Alpha
::
F31
)
;
else
llvm_unreachable
(
"Unhandled register class"
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> void alpha_split_compare_and_swap ( rtx retval , rtx mem , rtx oldval , rtx newval , rtx scratch ) { enum machine_mode mode = GET_MODE ( mem ) ; rtx label1 , label2 , x , cond = gen_lowpart ( DImode , scratch ) ; emit_insn ( gen_memory_barrier ( ) ) ; label1 = gen_rtx_LABEL_REF ( DImode , gen_label_rtx ( ) ) ; label2 = gen_rtx_LABEL_REF ( DImode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label1 , 0 ) ) ; emit_load_locked ( mode , retval , mem ) ; x = gen_lowpart ( DImode , retval ) ; if ( oldval == const0_rtx ) x = gen_rtx_NE ( DImode , x , const0_rtx ) ; else { x = gen_rtx_EQ ( DImode , x , oldval ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cond , x ) ) ; x = gen_rtx_EQ ( DImode , cond , const0_rtx ) ; } emit_unlikely_jump ( x , label2 ) ; emit_move_insn ( scratch , newval ) ; emit_store_conditional ( mode , cond , mem , scratch ) ; x = gen_rtx_EQ ( DImode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label1 ) ; emit_insn ( gen_memory_barrier ( ) ) ; emit_label ( XEXP ( label2 , 0 ) ) ; } </s>


<s> static rtx sh_delegitimize_address ( rtx orig_x ) { rtx x , y ; orig_x = delegitimize_mem_from_attrs ( orig_x ) ; x = orig_x ; if ( MEM_P ( x ) ) x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == CONST ) { y = XEXP ( x , 0 ) ; if ( GET_CODE ( y ) == UNSPEC ) { if ( XINT ( y , 1 ) == UNSPEC_GOT || XINT ( y , 1 ) == UNSPEC_GOTOFF || XINT ( y , 1 ) == UNSPEC_SYMOFF ) return XVECEXP ( y , 0 , 0 ) ; else if ( XINT ( y , 1 ) == UNSPEC_PCREL_SYMOFF ) { if ( GET_CODE ( XVECEXP ( y , 0 , 0 ) ) == CONST ) { rtx symplt = XEXP ( XVECEXP ( y , 0 , 0 ) , 0 ) ; if ( GET_CODE ( symplt ) == UNSPEC && ( XINT ( symplt , 1 ) == UNSPEC_PLT || XINT ( symplt , 1 ) == UNSPEC_PCREL ) ) return XVECEXP ( symplt , 0 , 0 ) ; } } else if ( TARGET_SHMEDIA && ( XINT ( y , 1 ) == UNSPEC_EXTRACT_S16 || XINT ( y , 1 ) == UNSPEC_EXTRACT_U16 ) ) { rtx offset = XVECEXP ( y , 0 , 1 ) ; x = gen_rtx_PLUS ( Pmode , XVECEXP ( y , 0 , 0 ) , offset ) ; if ( MEM_P ( orig_x ) ) x = replace_equiv_address_nv ( orig_x , x ) ; return x ; } } } return orig_x ; } </s>

In the name of slightly smaller debug output , and to cater to general assembler lossage , recognize various UNSPEC sequences and turn them back into a direct symbol reference .


<s> const MachineOperand * getNamedOperand ( const MachineInstr & MI , unsigned OpName ) const { return getNamedOperand ( const_cast < MachineInstr & > ( MI ) , OpName ) ; } </s>


<s> static bool rs6000_is_costly_dependence ( dep_t dep , int cost , int distance ) { rtx insn ; rtx next ; rtx load_mem , str_mem ; if ( rs6000_sched_costly_dep == no_dep_costly ) return false ; if ( rs6000_sched_costly_dep == all_deps_costly ) return true ; insn = DEP_PRO ( dep ) ; next = DEP_CON ( dep ) ; if ( rs6000_sched_costly_dep == store_to_load_dep_costly && is_load_insn ( next , & load_mem ) && is_store_insn ( insn , & str_mem ) ) return true ; if ( rs6000_sched_costly_dep == true_store_to_load_dep_costly && is_load_insn ( next , & load_mem ) && is_store_insn ( insn , & str_mem ) && DEP_TYPE ( dep ) == REG_DEP_TRUE && mem_locations_overlap ( str_mem , load_mem ) ) return true ; if ( rs6000_sched_costly_dep <= max_dep_latency && ( ( cost - distance ) >= ( int ) rs6000_sched_costly_dep ) ) return true ; return false ; } </s>

Returns whether the dependence between INSN and NEXT is considered costly by the given target .


<s>
void
cris_notice_update_cc
(
rtx
exp
,
rtx_insn
*
insn
)
{
enum
attr_cc
attrval
=
get_attr_cc
(
insn
)
;
if
(
TARGET_CCINIT
)
{
CC_STATUS_INIT
;
if
(
attrval
==
CC_REV
)
cc_status
.
flags
=
CC_REVERSED
;
return
;
}
switch
(
attrval
)
{
case
CC_NONE
:
if
(
GET_CODE
(
exp
)
==
SET
)
{
if
(
cc_status
.
value1
&&
modified_in_p
(
cc_status
.
value1
,
insn
)
)
cc_status
.
value1
=
0
;
if
(
cc_status
.
value2
&&
modified_in_p
(
cc_status
.
value2
,
insn
)
)
cc_status
.
value2
=
0
;
}
return
;
case
CC_CLOBBER
:
CC_STATUS_INIT
;
return
;
case
CC_REV
:
case
CC_NOOV32
:
case
CC_NORMAL
:
cris_normal_notice_update_cc
(
exp
,
insn
)
;
if
(
attrval
==
CC_NOOV32
&&
TARGET_V32
)
cc_status
.
flags
|=
CC_NO_OVERFLOW
;
return
;
default
:
internal_error
(
"unknown cc_attr value"
)
;
}
CC_STATUS_INIT
;
}
</s>

This function looks into the pattern to see how this insn affects condition codes . Used when to eliminate test insns before a condition-code user , such as a `` scc '' insn or a conditional branch . This includes checking if the entities that cc was updated by , are changed by the operation . Currently a jumble of the old peek-inside-the-insn and the newer check-cc-attribute methods .


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCInstFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
{
llvm_unreachable
(
"relaxInstruction() unimplemented"
)
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> unsigned AMDGPUAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & Op , unsigned Kind ) { AMDGPUOperand & Operand = ( AMDGPUOperand & ) Op ; switch ( Kind ) { case MCK_addr64 : return Operand . isAddr64 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_gds : return Operand . isGDS ( ) ? Match_Success : Match_InvalidOperand ; case MCK_lds : return Operand . isLDS ( ) ? Match_Success : Match_InvalidOperand ; case MCK_glc : return Operand . isGLC ( ) ? Match_Success : Match_InvalidOperand ; case MCK_d16 : return Operand . isD16 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_idxen : return Operand . isIdxen ( ) ? Match_Success : Match_InvalidOperand ; case MCK_offen : return Operand . isOffen ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SSrcB32 : return Operand . isSSrcB32 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SSrcF32 : return Operand . isSSrcF32 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SoppBrTarget : return Operand . isSoppBrTarget ( ) ? Match_Success : Match_InvalidOperand ; case MCK_VReg32OrOff : return Operand . isVReg32OrOff ( ) ? Match_Success : Match_InvalidOperand ; case MCK_InterpSlot : return Operand . isInterpSlot ( ) ? Match_Success : Match_InvalidOperand ; case MCK_Attr : return Operand . isInterpAttr ( ) ? Match_Success : Match_InvalidOperand ; case MCK_AttrChan : return Operand . isAttrChan ( ) ? Match_Success : Match_InvalidOperand ; default : return Match_InvalidOperand ; } } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> MachineBasicBlock :: iterator TL45FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { Register SPReg = TL45 :: sp ; DebugLoc DL = MI -> getDebugLoc ( ) ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = MI -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { Amount = alignSPAdjust ( Amount ) ; if ( MI -> getOpcode ( ) == TL45 :: ADJCALLSTACKDOWN ) Amount = - Amount ; adjustReg ( MBB , MI , DL , SPReg , SPReg , Amount , MachineInstr :: NoFlags ) ; } } return MBB . erase ( MI ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> EVT SITargetLowering :: getSetCCResultType ( EVT VT ) const { return MVT :: i1 ; } </s>

Return the value type to use for ISD : :SETCC .


<s>
void
TVMFrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
LLVMContext
&
C
=
MF
.
getFunction
(
)
.
getContext
(
)
;
const
auto
*
TII
=
MF
.
getSubtarget
<
TVMSubtarget
>
(
)
.
getInstrInfo
(
)
;
auto
&
MFI
=
MF
.
getFrameInfo
(
)
;
auto
&
MRI
=
MF
.
getRegInfo
(
)
;
uint64_t
StackSize
=
MFI
.
getStackSize
(
)
;
if
(
StackSize
==
0
&&
!
TraceCalls
)
return
;
if
(
MF
.
getFunction
(
)
.
hasFnAttribute
(
"tvm_raw_func"
)
&&
StackSize
)
{
report_fatal_error
(
"Raw function requires stack"
)
;
return
;
}
auto
InsertPt
=
llvm
::
find_if
(
MBB
,
[
&
]
(
auto
&
pt
)
{
return
!
TVM
::
isArgument
(
pt
)
;
}
)
;
DebugLoc
DL
;
if
(
TraceCalls
)
{
const
Function
&
Fn
=
MF
.
getFunction
(
)
;
if
(
MBB
.
getBasicBlock
(
)
==
&
Fn
.
getEntryBlock
(
)
)
BuildMI
(
MBB
,
InsertPt
,
DL
,
TII
->
get
(
TVM
::
LOGSTR
)
)
.
addGlobalAddress
(
&
Fn
)
;
}
unsigned
RegFrameBase
=
MRI
.
createVirtualRegister
(
&
TVM
::
I257RegClass
)
;
BuildMI
(
MBB
,
InsertPt
,
DL
,
TII
->
get
(
TVM
::
GETGLOB
)
,
RegFrameBase
)
.
addImm
(
5
)
;
unsigned
RegFrameBaseNew
=
MRI
.
createVirtualRegister
(
&
TVM
::
I257RegClass
)
;
if
(
StackSize
<=
128
)
{
BuildMI
(
MBB
,
InsertPt
,
DL
,
TII
->
get
(
TVM
::
ADDCONST
)
,
RegFrameBaseNew
)
.
addReg
(
RegFrameBase
)
.
addImm
(
StackSize
)
;
}
else
{
unsigned
RegStSize
=
MRI
.
createVirtualRegister
(
&
TVM
::
I257RegClass
)
;
BuildMI
(
MBB
,
InsertPt
,
DL
,
TII
->
get
(
TVM
::
CONST_I257
)
,
RegStSize
)
.
addCImm
(
cimm
(
C
,
StackSize
)
)
;
BuildMI
(
MBB
,
InsertPt
,
DL
,
TII
->
get
(
TVM
::
SUB
)
,
RegFrameBaseNew
)
.
addReg
(
RegFrameBase
)
.
addReg
(
RegStSize
)
;
}
BuildMI
(
MBB
,
InsertPt
,
DL
,
TII
->
get
(
TVM
::
SETGLOB
)
)
.
addReg
(
RegFrameBaseNew
)
.
addImm
(
5
)
;
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool AMDGPUAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { const AMDGPUSubtarget & STM = TM . getSubtarget < AMDGPUSubtarget > ( ) ; if ( STM . dumpCode ( ) ) { MF . dump ( ) ; } SetupMachineFunction ( MF ) ; if ( OutStreamer . hasRawTextSupport ( ) ) { OutStreamer . EmitRawText ( "@" + MF . getName ( ) + ":" ) ; } const MCSectionELF * ConfigSection = getObjFileLowering ( ) . getContext ( ) . getELFSection ( ".AMDGPU.config" , ELF :: SHT_PROGBITS , 0 , SectionKind :: getReadOnly ( ) ) ; OutStreamer . SwitchSection ( ConfigSection ) ; if ( STM . getGeneration ( ) > AMDGPUSubtarget :: NORTHERN_ISLANDS ) { EmitProgramInfoSI ( MF ) ; } else { EmitProgramInfoR600 ( MF ) ; } OutStreamer . SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; EmitFunctionBody ( ) ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool KudeyarFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> StringRef getPassName ( ) const override { return RISCV_CLEANUP_VSETVLI_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> PreservedAnalyses AMDGPUAlwaysInlinePass :: run ( Module & M , ModuleAnalysisManager & AM ) { alwaysInlineImpl ( M , GlobalOpt ) ; return PreservedAnalyses :: all ( ) ; } </s>

Run the analysis pass over a function and produce a dominator tree .


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override { ScheduleDAGMI * DAG = createGenericSchedPostRA ( C ) ; const GCNSubtarget & ST = C -> MF -> getSubtarget < GCNSubtarget > ( ) ; DAG -> addMutation ( ST . createFillMFMAShadowMutation ( DAG -> TII ) ) ; return DAG ; } </s>

Similar to createMachineScheduler but used when postRA machine scheduling is enabled .


<s> static bool sparc_pass_by_reference ( cumulative_args_t cum ATTRIBUTE_UNUSED , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { if ( TARGET_ARCH32 ) return ( ( type && ( AGGREGATE_TYPE_P ( type ) || VECTOR_FLOAT_TYPE_P ( type ) ) ) || mode == SCmode || GET_MODE_SIZE ( mode ) > 8 || ( type && TREE_CODE ( type ) == VECTOR_TYPE && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > 8 ) ) ; else return ( ( type && ( AGGREGATE_TYPE_P ( type ) || TREE_CODE ( type ) == VECTOR_TYPE ) && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > 16 ) || GET_MODE_SIZE ( mode ) > 16 ) ; } </s>

Handle the TARGET_PASS_BY_REFERENCE target hook . Specify whether to pass the argument by reference .


<s>
StringRef
getPassName
(
)
const
override
{
return
"CAHP Assembly Printer"
;
}
</s>


<s> bool SIInstrInfo :: usesConstantBus ( const MachineRegisterInfo & MRI , const MachineOperand & MO , const MCOperandInfo & OpInfo ) const { if ( MO . isImm ( ) ) return ! isInlineConstant ( MO , OpInfo ) ; if ( ! MO . isReg ( ) ) return true ; if ( ! MO . isUse ( ) ) return false ; if ( MO . getReg ( ) . isVirtual ( ) ) return RI . isSGPRClass ( MRI . getRegClass ( MO . getReg ( ) ) ) ; if ( MO . getReg ( ) == AMDGPU :: SGPR_NULL ) return false ; if ( MO . isImplicit ( ) ) { return MO . getReg ( ) == AMDGPU :: M0 || MO . getReg ( ) == AMDGPU :: VCC || MO . getReg ( ) == AMDGPU :: VCC_LO ; } else { return AMDGPU :: SReg_32RegClass . contains ( MO . getReg ( ) ) || AMDGPU :: SReg_64RegClass . contains ( MO . getReg ( ) ) ; } } </s>

Returns true if this operand uses the constant bus .


<s> bool ARMFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; bool isVarArg = AFI -> getArgRegsSaveSize ( ) > 0 ; unsigned NumAlignedDPRCS2Regs = AFI -> getNumAlignedDPRCS2Regs ( ) ; if ( NumAlignedDPRCS2Regs ) emitAlignedDPRCS2Restores ( MBB , MI , NumAlignedDPRCS2Regs , CSI , TRI ) ; unsigned PopOpc = AFI -> isThumbFunction ( ) ? ARM :: t2LDMIA_UPD : ARM :: LDMIA_UPD ; unsigned LdrOpc = AFI -> isThumbFunction ( ) ? ARM :: t2LDR_POST : ARM :: LDR_POST_IMM ; unsigned FltOpc = ARM :: VLDMDIA_UPD ; emitPopInst ( MBB , MI , CSI , FltOpc , 0 , isVarArg , true , & isARMArea3Register , NumAlignedDPRCS2Regs ) ; emitPopInst ( MBB , MI , CSI , PopOpc , LdrOpc , isVarArg , false , & isARMArea2Register , 0 ) ; emitPopInst ( MBB , MI , CSI , PopOpc , LdrOpc , isVarArg , false , & isARMArea1Register , 0 ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> void tilepro_expand_unaligned_load ( rtx dest_reg , rtx mem , HOST_WIDE_INT bitsize , HOST_WIDE_INT bit_offset , bool sign ) { machine_mode mode ; rtx addr_lo , addr_hi ; rtx mem_lo , mem_hi , hi ; rtx mema , wide_result ; int last_byte_offset ; HOST_WIDE_INT byte_offset = bit_offset / BITS_PER_UNIT ; mode = GET_MODE ( dest_reg ) ; hi = gen_reg_rtx ( mode ) ; if ( bitsize == 2 * BITS_PER_UNIT && ( bit_offset % BITS_PER_UNIT ) == 0 ) { rtx lo ; mem_lo = adjust_address ( mem , QImode , byte_offset ) ; mem_hi = adjust_address ( mem , QImode , byte_offset + 1 ) ; lo = gen_reg_rtx ( mode ) ; emit_insn ( gen_zero_extendqisi2 ( lo , mem_lo ) ) ; if ( sign ) { rtx tmp = gen_reg_rtx ( mode ) ; emit_insn ( gen_extendqisi2 ( gen_lowpart ( SImode , hi ) , mem_hi ) ) ; emit_insn ( gen_ashlsi3 ( gen_lowpart ( SImode , tmp ) , gen_lowpart ( SImode , hi ) , GEN_INT ( 8 ) ) ) ; emit_insn ( gen_iorsi3 ( gen_lowpart ( SImode , dest_reg ) , gen_lowpart ( SImode , lo ) , gen_lowpart ( SImode , tmp ) ) ) ; } else { emit_insn ( gen_zero_extendqisi2 ( gen_lowpart ( SImode , hi ) , mem_hi ) ) ; emit_insn ( gen_insn_intlb ( gen_lowpart ( SImode , dest_reg ) , gen_lowpart ( SImode , hi ) , gen_lowpart ( SImode , lo ) ) ) ; } return ; } mema = XEXP ( mem , 0 ) ; addr_lo = force_reg ( Pmode , plus_constant ( Pmode , mema , byte_offset ) ) ; mem_lo = change_address ( mem , mode , gen_rtx_AND ( Pmode , addr_lo , GEN_INT ( - 4 ) ) ) ; set_mem_alias_set ( mem_lo , 0 ) ; last_byte_offset = ( bit_offset + bitsize - 1 ) / BITS_PER_UNIT ; addr_hi = force_reg ( Pmode , plus_constant ( Pmode , mema , last_byte_offset ) ) ; mem_hi = change_address ( mem , mode , gen_rtx_AND ( Pmode , addr_hi , GEN_INT ( - 4 ) ) ) ; set_mem_alias_set ( mem_hi , 0 ) ; if ( bitsize == 32 ) { addr_lo = make_safe_from ( addr_lo , dest_reg ) ; wide_result = dest_reg ; } else { wide_result = gen_reg_rtx ( mode ) ; } emit_move_insn ( hi , mem_hi ) ; emit_move_insn ( wide_result , mem_lo ) ; emit_insn ( gen_insn_dword_align ( gen_lowpart ( SImode , wide_result ) , gen_lowpart ( SImode , wide_result ) , gen_lowpart ( SImode , hi ) , addr_lo ) ) ; if ( bitsize != 32 ) { rtx extracted = extract_bit_field ( gen_lowpart ( SImode , wide_result ) , bitsize , bit_offset % BITS_PER_UNIT , ! sign , gen_lowpart ( SImode , dest_reg ) , SImode , SImode , false , NULL ) ; if ( extracted != dest_reg ) emit_move_insn ( dest_reg , gen_lowpart ( SImode , extracted ) ) ; } } </s>


<s> static rtx sched_get_mem_operand ( rtx_insn * insn , bool must_read_p , bool must_write_p ) { bool opx_p ; bool opy_p ; opx_p = false ; opy_p = false ; if ( must_read_p ) { opx_p = true ; opy_p = true ; } if ( must_write_p ) { opx_p = true ; opy_p = false ; } if ( opy_p && sched_mem_operand_p ( insn , false ) ) return sched_get_operand ( insn , false ) ; if ( opx_p && sched_mem_operand_p ( insn , true ) ) return sched_get_operand ( insn , true ) ; gcc_unreachable ( ) ; return NULL ; } </s>

Return X or Y ( depending on OPX_P ) operand of INSN , if it is a MEM , or NULL overwise .


<s> static enum attr_op_type sched_get_opxy_mem_type ( rtx_insn * insn , bool opx_p ) { if ( opx_p ) { switch ( get_attr_opx_type ( insn ) ) { case OPX_TYPE_NONE : case OPX_TYPE_RN : case OPX_TYPE_FPN : case OPX_TYPE_IMM_Q : case OPX_TYPE_IMM_W : case OPX_TYPE_IMM_L : return OP_TYPE_RN ; case OPX_TYPE_MEM1 : case OPX_TYPE_MEM234 : case OPX_TYPE_MEM5 : case OPX_TYPE_MEM7 : return OP_TYPE_MEM1 ; case OPX_TYPE_MEM6 : return OP_TYPE_MEM6 ; default : gcc_unreachable ( ) ; } } else { switch ( get_attr_opy_type ( insn ) ) { case OPY_TYPE_NONE : case OPY_TYPE_RN : case OPY_TYPE_FPN : case OPY_TYPE_IMM_Q : case OPY_TYPE_IMM_W : case OPY_TYPE_IMM_L : return OP_TYPE_RN ; case OPY_TYPE_MEM1 : case OPY_TYPE_MEM234 : case OPY_TYPE_MEM5 : case OPY_TYPE_MEM7 : return OP_TYPE_MEM1 ; case OPY_TYPE_MEM6 : return OP_TYPE_MEM6 ; default : gcc_unreachable ( ) ; } } } </s>

Return operand X or Y ( depending on OPX_P ) of INSN , if it is a MEM , or NULL overwise .


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const X86Subtarget & Subtarget = MF . getSubtarget < X86Subtarget > ( ) ; bool HasSSE = Subtarget . hasSSE1 ( ) ; bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; if ( CC == CallingConv :: Mono && IsWin64 ) CC = CallingConv :: Win64 ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return CSR_64_TLS_Darwin_RegMask ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: X86_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_RegMask : CSR_Win64_RegCall_NoSSE_RegMask ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_RegMask : CSR_SysV64_RegCall_NoSSE_RegMask ) ; } } else { return ( HasSSE ? CSR_32_RegCall_RegMask : CSR_32_RegCall_NoSSE_RegMask ) ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: Win64 : return CSR_Win64_RegMask ; case CallingConv :: X86_64_SysV : return CSR_64_RegMask ; case CallingConv :: X86_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_64_AllRegs_RegMask ; return CSR_64_AllRegs_NoSSE_RegMask ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_32_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_32_AllRegs_SSE_RegMask ; return CSR_32_AllRegs_RegMask ; } default : break ; } if ( Is64Bit ) { const Function & F = MF . getFunction ( ) ; bool IsSwiftCC = Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && F . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ; if ( IsSwiftCC ) return IsWin64 ? CSR_Win64_SwiftError_RegMask : CSR_64_SwiftError_RegMask ; return IsWin64 ? CSR_Win64_RegMask : CSR_64_RegMask ; } return CSR_32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> rtx aarch64_final_eh_return_addr ( void ) { HOST_WIDE_INT fp_offset ; aarch64_layout_frame ( ) ; fp_offset = cfun -> machine -> frame . frame_size - cfun -> machine -> frame . hard_fp_offset ; if ( cfun -> machine -> frame . reg_offset [ LR_REGNUM ] < 0 ) return gen_rtx_REG ( DImode , LR_REGNUM ) ; if ( frame_pointer_needed ) { if ( fp_offset ) return gen_frame_mem ( DImode , plus_constant ( Pmode , hard_frame_pointer_rtx , UNITS_PER_WORD ) ) ; else return gen_frame_mem ( DImode , plus_constant ( Pmode , stack_pointer_rtx , UNITS_PER_WORD ) ) ; } return gen_frame_mem ( DImode , plus_constant ( Pmode , stack_pointer_rtx , fp_offset + cfun -> machine -> frame . saved_regs_size - 2 * UNITS_PER_WORD ) ) ; } </s>

Return the place to copy the exception unwinding return address to . This will probably be a stack slot , but could ( in theory be the return register ) .


<s> bool runOnMachineFunction ( MachineFunction & F ) override { AArch64FI = F . getInfo < AArch64FunctionInfo > ( ) ; return AsmPrinter :: runOnMachineFunction ( F ) ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"MSP430 Branch Selector"
;
}
</s>


<s> int avr_hard_regno_rename_ok ( unsigned int old_reg , unsigned int new_reg ) { if ( ( cfun -> machine -> is_interrupt || cfun -> machine -> is_signal ) && ! df_regs_ever_live_p ( new_reg ) ) return 0 ; if ( ( ! reload_completed || frame_pointer_needed ) && ( old_reg == REG_Y || old_reg == REG_Y + 1 || new_reg == REG_Y || new_reg == REG_Y + 1 ) ) { return 0 ; } return 1 ; } </s>

Return nonzero if register OLD_REG can be renamed to register NEW_REG .


<s> static bool s390_keep_leaf_when_profiled ( ) { return true ; } </s>

We call mcount before the function prologue . So a profiled leaf function should stay a leaf function .


<s> std :: pair < unsigned , const TargetRegisterClass * > VETargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { const TargetRegisterClass * RC = nullptr ; if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; case 'r' : RC = & VE :: I64RegClass ; break ; case 'v' : RC = & VE :: V64RegClass ; break ; } return std :: make_pair ( 0U , RC ) ; } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> static struct machine_function * arm_init_machine_status ( void ) { struct machine_function * machine ; machine = ( machine_function * ) ggc_alloc_cleared ( sizeof ( machine_function ) ) ; machine -> func_type = ARM_FT_UNKNOWN ; return machine ; } </s>

Functions to save and restore machine-specific function data .


<s> Register M68kIncomingValueHandler :: getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO , ISD :: ArgFlagsTy Flags ) { auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; const bool IsImmutable = ! Flags . isByVal ( ) ; int FI = MFI . CreateFixedObject ( Size , Offset , IsImmutable ) ; MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; llvm :: LLT FramePtr = LLT :: pointer ( 0 , MIRBuilder . getMF ( ) . getDataLayout ( ) . getPointerSizeInBits ( ) ) ; MachineInstrBuilder AddrReg = MIRBuilder . buildFrameIndex ( FramePtr , FI ) ; StackUsed = std :: max ( StackUsed , Size + Offset ) ; return AddrReg . getReg ( 0 ) ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> bool SparcInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return false ; if ( ! isUnpredicatedTerminator ( * I ) ) return false ; MachineInstr * LastInst = & * I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { if ( isUncondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } if ( isCondBranchOpcode ( LastOpc ) ) { parseCondBranch ( LastInst , TBB , Cond ) ; return false ; } return true ; } MachineInstr * SecondLastInst = & * I ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; if ( AllowModify && isUncondBranchOpcode ( LastOpc ) ) { while ( isUncondBranchOpcode ( SecondLastOpc ) ) { LastInst -> eraseFromParent ( ) ; LastInst = SecondLastInst ; LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { TBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } else { SecondLastInst = & * I ; SecondLastOpc = SecondLastInst -> getOpcode ( ) ; } } } if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( * -- I ) ) return true ; if ( isCondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { parseCondBranch ( SecondLastInst , TBB , Cond ) ; FBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } if ( isUncondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { TBB = SecondLastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } if ( isIndirectBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return true ; } return true ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> const char * pa_output_mod_insn ( int unsignedp , rtx_insn * insn ) { if ( unsignedp ) { import_milli ( remU ) ; return pa_output_millicode_call ( insn , gen_rtx_SYMBOL_REF ( SImode , "$$remU" ) ) ; } else { import_milli ( remI ) ; return pa_output_millicode_call ( insn , gen_rtx_SYMBOL_REF ( SImode , "$$remI" ) ) ; } } </s>


<s> bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , const BranchProbability & Probability ) const override { return true ; } </s>

Return true if it 's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion .


<s> static machine_mode avr_addr_space_address_mode ( addr_space_t as ) { return avr_addrspace [ as ] . pointer_size == 3 ? PSImode : HImode ; } </s>

Implement ` TARGET_ADDR_SPACE_ADDRESS_MODE ' .


<s> int RISCVFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const auto * RVFI = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; int MinCSFI = 0 ; int MaxCSFI = - 1 ; int Offset = MFI . getObjectOffset ( FI ) - getOffsetOfLocalArea ( ) + MFI . getOffsetAdjustment ( ) ; if ( CSI . size ( ) ) { MinCSFI = CSI [ 0 ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - 1 ] . getFrameIdx ( ) ; } if ( FI >= MinCSFI && FI <= MaxCSFI ) { FrameReg = RISCV :: X2 ; Offset += MF . getFrameInfo ( ) . getStackSize ( ) ; } else { FrameReg = RI -> getFrameRegister ( MF ) ; if ( hasFP ( MF ) ) Offset += RVFI -> getVarArgsSaveSize ( ) ; else Offset += MF . getFrameInfo ( ) . getStackSize ( ) ; } return Offset ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> bool RISCVRegisterInfo :: isConstantPhysReg ( MCRegister PhysReg ) const { return PhysReg == RISCV :: X0 || PhysReg == RISCV :: C0 ; } </s>

Returns true if PhysReg is unallocatable and constant throughout the function .


<s> bool X86TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned Align , MachineMemOperand :: Flags Flags , bool * Fast ) const { if ( Fast ) { switch ( VT . getSizeInBits ( ) ) { default : * Fast = true ; break ; case 128 : * Fast = ! Subtarget . isUnalignedMem16Slow ( ) ; break ; case 256 : * Fast = ! Subtarget . isUnalignedMem32Slow ( ) ; break ; } } if ( ! ! ( Flags & MachineMemOperand :: MONonTemporal ) && VT . isVector ( ) ) { if ( ! ! ( Flags & MachineMemOperand :: MOLoad ) ) return ( Align < 16 || ! Subtarget . hasSSE41 ( ) ) ; return false ; } return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> MCSymbol * OR1KMCInstLower :: GetExternalSymbolSymbol ( const MachineOperand & MO ) const { return Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; } </s>

Return the MCSymbol for the specified ExternalSymbol .


<s> static void mips_74k_agen_reorder ( rtx_insn * * ready , int nready ) { int i ; int store_pos , load_pos ; store_pos = - 1 ; load_pos = - 1 ; for ( i = nready - 1 ; i >= 0 ; i -- ) { rtx_insn * insn = ready [ i ] ; if ( USEFUL_INSN_P ( insn ) ) switch ( get_attr_type ( insn ) ) { case TYPE_STORE : if ( store_pos == - 1 ) store_pos = i ; break ; case TYPE_LOAD : if ( load_pos == - 1 ) load_pos = i ; break ; default : break ; } } if ( load_pos == - 1 || store_pos == - 1 ) return ; switch ( mips_last_74k_agen_insn ) { case TYPE_UNKNOWN : case TYPE_LOAD : mips_maybe_swap_ready ( ready , load_pos , store_pos , 4 ) ; break ; case TYPE_STORE : mips_maybe_swap_ready ( ready , store_pos , load_pos , 4 ) ; break ; default : break ; } } </s>

A TUNE_74K helper function . The 74K AGEN pipeline likes multiple loads to be grouped together , and multiple stores to be grouped together . Swap things around in the ready queue to make this happen .


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) -> findAssociatedFragment ( ) ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s>
void
PPCMIPeephole
::
initialize
(
MachineFunction
&
MFParm
)
{
MF
=
&
MFParm
;
MRI
=
&
MF
->
getRegInfo
(
)
;
TII
=
MF
->
getSubtarget
<
PPCSubtarget
>
(
)
.
getInstrInfo
(
)
;
DEBUG
(
dbgs
(
)
<<
"*** PowerPC MI peephole pass ***\n\n"
)
;
DEBUG
(
MF
->
dump
(
)
)
;
}
</s>

Initialize the strategy after building the DAG for a new region .

PowerPC
PPC
PPC
"*** PowerPC MI peephole pass ***\n\n"


<s> void SystemZPassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createSystemZShortenInstPass ( getSystemZTargetMachine ( ) ) , false ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createSystemZElimComparePass ( getSystemZTargetMachine ( ) ) , false ) ; addPass ( createSystemZLongBranchPass ( getSystemZTargetMachine ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & PostMachineSchedulerID ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s>
void
ARMAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
Value
=
adjustFixupValue
(
Asm
,
Fixup
,
Target
,
Value
,
IsResolved
,
Ctx
)
;
if
(
!
Value
)
return
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
unsigned
FullSizeBytes
;
if
(
Endian
==
support
::
big
)
{
FullSizeBytes
=
getFixupKindContainerSizeBytes
(
Fixup
.
getKind
(
)
)
;
assert
(
(
Offset
+
FullSizeBytes
)
<=
Data
.
size
(
)
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FullSizeBytes
&&
"Invalid fixup size!"
)
;
}
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
Endian
==
support
::
little
i
:
(
FullSizeBytes
1
i
)
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> unsigned LanaiInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . getOpcode ( ) == Lanai :: LDW_RI ) if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s>
unsigned
MMIXMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
llvm_unreachable
(
"Unhandled expression!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> bool Mips16FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return isInt < 15 > ( MFI -> getMaxCallFrameSize ( ) ) && ! MFI -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


"Switch should handle all register classes"


<s> void XCoreInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) && ! I -> isDebugInstr ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ; BuildMI ( MBB , I , DL , get ( XCore :: STWFI ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) . addMemOperand ( MMO ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> const ARCSubtarget * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> void LC3bMCInstLower :: Initialize ( Mangler * M , MCContext * C ) { Mang = M ; Ctx = C ; } </s>

This method must be called before any actual lowering is done .


<s> static void ia64_init_dfa_pre_cycle_insn ( void ) { if ( temp_dfa_state == NULL ) { dfa_state_size = state_size ( ) ; temp_dfa_state = xmalloc ( dfa_state_size ) ; prev_cycle_state = xmalloc ( dfa_state_size ) ; } dfa_pre_cycle_insn = make_insn_raw ( gen_pre_cycle ( ) ) ; SET_PREV_INSN ( dfa_pre_cycle_insn ) = SET_NEXT_INSN ( dfa_pre_cycle_insn ) = NULL_RTX ; recog_memoized ( dfa_pre_cycle_insn ) ; dfa_stop_insn = make_insn_raw ( gen_insn_group_barrier ( GEN_INT ( 3 ) ) ) ; SET_PREV_INSN ( dfa_stop_insn ) = SET_NEXT_INSN ( dfa_stop_insn ) = NULL_RTX ; recog_memoized ( dfa_stop_insn ) ; } </s>

The following function initiates variable ` dfa_pre_cycle_insn ' .


<s> bool runOnMachineFunction ( MachineFunction & MF ) { if ( ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ) { return false ; } const AVRSubtarget & STI = MF . getSubtarget < AVRSubtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; MachineBasicBlock & EntryMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = EntryMBB . begin ( ) ; DebugLoc DL = EntryMBB . findDebugLoc ( MBBI ) ; Register SPCopy = MF . getRegInfo ( ) . createVirtualRegister ( & AVR :: DREGSRegClass ) ; BuildMI ( EntryMBB , MBBI , DL , TII . get ( AVR :: COPY ) , SPCopy ) . addReg ( AVR :: SP ) ; for ( MachineBasicBlock & MBB : MF ) { if ( ! MBB . empty ( ) && MBB . back ( ) . isReturn ( ) ) { MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( AVR :: COPY ) , AVR :: SP ) . addReg ( SPCopy , RegState :: Kill ) ; } } return true ; } </s>

runOnMachineFunction - Emit the function body .

AVR AVR AVR AVR::DREGSRegClass AVR::COPY AVR::SP AVR::COPY AVR::SP


<s>
unsigned
AGCMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
if
(
MO
.
isExpr
(
)
&&
MO
.
getExpr
(
)
->
getKind
(
)
==
MCExpr
::
SymbolRef
)
return
0
;
llvm_unreachable
(
"Unhandled expression!"
)
;
return
0
;
}
</s>


<s> rtx s390_emit_compare ( enum rtx_code code , rtx op0 , rtx op1 ) { machine_mode mode = s390_select_ccmode ( code , op0 , op1 ) ; rtx cc ; if ( GET_MODE_CLASS ( GET_MODE ( op0 ) ) == MODE_CC ) { gcc_assert ( s390_cc_modes_compatible ( GET_MODE ( op0 ) , mode ) == GET_MODE ( op0 ) ) ; cc = op0 ; } else { cc = gen_rtx_REG ( mode , CC_REGNUM ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cc , gen_rtx_COMPARE ( mode , op0 , op1 ) ) ) ; } return gen_rtx_fmt_ee ( code , VOIDmode , cc , const0_rtx ) ; } </s>

Emit a compare instruction suitable to implement the comparison OP0 CODE OP1 . Return the correct condition RTL to be placed in the IF_THEN_ELSE of the conditional branch testing the result .


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { if ( RC == & ARM :: GPRRegClass || RC == & ARM :: tGPRRegClass || RC == & ARM :: tcGPRRegClass || RC == & ARM :: rGPRRegClass || RC == & ARM :: GPRnopcRegClass ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2LDRi12 ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } ARMBaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC , TRI ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .

ARM ARM::GPRRegClass ARM::tGPRRegClass ARM::tcGPRRegClass ARM::rGPRRegClass ARM::GPRnopcRegClass ARM::t2LDRi12 0 ARM


<s> rtx or1k_initial_frame_addr ( ) { crtl -> accesses_prior_frames = 1 ; return arg_pointer_rtx ; } </s>

Worker for INITIAL_FRAME_ADDRESS_RTX . Returns the RTX representing the address of the initial stack frame .


<s> bool isMem ( ) const { return isMEMrr ( ) || isMEMri ( ) ; } </s>


<s> static bool riscv_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { unsigned int nregs = riscv_hard_regno_nregs ( regno , mode ) ; if ( GP_REG_P ( regno ) ) { if ( riscv_v_ext_vector_mode_p ( mode ) ) return false ; if ( ! GP_REG_P ( regno + nregs - 1 ) ) return false ; } else if ( FP_REG_P ( regno ) ) { if ( riscv_v_ext_vector_mode_p ( mode ) ) return false ; if ( ! FP_REG_P ( regno + nregs - 1 ) ) return false ; if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && GET_MODE_CLASS ( mode ) != MODE_COMPLEX_FLOAT ) return false ; if ( GET_MODE_UNIT_SIZE ( mode ) > UNITS_PER_FP_REG || ( ! call_used_or_fixed_reg_p ( regno ) && GET_MODE_UNIT_SIZE ( mode ) > UNITS_PER_FP_ARG ) ) return false ; } else if ( V_REG_P ( regno ) ) { if ( ! riscv_v_ext_vector_mode_p ( mode ) ) return false ; if ( ! V_REG_P ( regno + nregs - 1 ) ) return false ; int lmul = 1 ; if ( known_gt ( GET_MODE_SIZE ( mode ) , UNITS_PER_V_REG ) ) lmul = exact_div ( GET_MODE_SIZE ( mode ) , UNITS_PER_V_REG ) . to_constant ( ) ; if ( lmul != 1 ) return ( ( regno % lmul ) == 0 ) ; } else if ( regno == VL_REGNUM || regno == VTYPE_REGNUM ) return true ; else return false ; for ( unsigned i = 1 ; i < nregs ; i ++ ) if ( call_used_or_fixed_reg_p ( regno ) != call_used_or_fixed_reg_p ( regno + i ) ) return false ; if ( ! TARGET_64BIT && TARGET_ZDINX ) { if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && GET_MODE_UNIT_SIZE ( mode ) == GET_MODE_SIZE ( DFmode ) ) return ! ( regno & 1 ) ; } return true ; } </s>


"Wrong register class for memory operand."

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .