<s> bool s390_const_int_pool_entry_p ( rtx mem , HOST_WIDE_INT * val ) { if ( ! MEM_P ( mem ) ) return false ; rtx addr = XEXP ( mem , 0 ) ; rtx sym ; if ( GET_CODE ( addr ) == UNSPEC && XINT ( addr , 1 ) == UNSPEC_LTREF ) sym = XVECEXP ( addr , 0 , 0 ) ; else sym = addr ; if ( ! SYMBOL_REF_P ( sym ) || ! CONSTANT_POOL_ADDRESS_P ( sym ) ) return false ; rtx val_rtx = get_pool_constant ( sym ) ; if ( ! CONST_INT_P ( val_rtx ) ) return false ; if ( val != nullptr ) * val = INTVAL ( val_rtx ) ; return true ; } </s>

Return true if MEM refers to an integer constant in the literal pool . If VAL is not nullptr , then also fill it with the constant 's value .


<s> void MOSPassConfig :: addOptimizedRegAlloc ( ) { insertPass ( & llvm :: TwoAddressInstructionPassID , & llvm :: RegisterCoalescerID ) ; TargetPassConfig :: addOptimizedRegAlloc ( ) ; } </s>

addOptimizedRegAlloc - Add passes related to register allocation .


<s> static int ix86_builtin_vectorization_cost ( enum vect_cost_for_stmt type_of_cost , tree vectype , int ) { unsigned elements ; switch ( type_of_cost ) { case scalar_stmt : return ix86_cost -> scalar_stmt_cost ; case scalar_load : return ix86_cost -> scalar_load_cost ; case scalar_store : return ix86_cost -> scalar_store_cost ; case vector_stmt : return ix86_cost -> vec_stmt_cost ; case vector_load : return ix86_cost -> vec_align_load_cost ; case vector_store : return ix86_cost -> vec_store_cost ; case vec_to_scalar : return ix86_cost -> vec_to_scalar_cost ; case scalar_to_vec : return ix86_cost -> scalar_to_vec_cost ; case unaligned_load : case unaligned_store : return ix86_cost -> vec_unalign_load_cost ; case cond_branch_taken : return ix86_cost -> cond_taken_branch_cost ; case cond_branch_not_taken : return ix86_cost -> cond_not_taken_branch_cost ; case vec_perm : case vec_promote_demote : return ix86_cost -> vec_stmt_cost ; case vec_construct : elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; return elements / 2 + 1 ; default : gcc_unreachable ( ) ; } } </s>


"WebAssembly can only return up to one value"

"WebAssembly doesn't support non-C calling conventions"

"WebAssembly hasn't implemented inalloca results"

"WebAssembly hasn't implemented cons regs results"

"WebAssembly hasn't implemented cons regs last results"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static tree get_prev_label ( tree function_name ) { tree branch_island ; for ( branch_island = branch_island_list ; branch_island ; branch_island = TREE_CHAIN ( branch_island ) ) if ( function_name == BRANCH_ISLAND_FUNCTION_NAME ( branch_island ) ) return BRANCH_ISLAND_LABEL_NAME ( branch_island ) ; return 0 ; } </s>

GET_PREV_LABEL gets the label name from the previous definition of the function .


<s> bool processBlock ( MachineBasicBlock & MBB ) { bool Changed = false ; const bool isPPC64 = MBB . getParent ( ) -> getSubtarget < PPCSubtarget > ( ) . isPPC64 ( ) ; const unsigned TOCReg = isPPC64 ? PPC :: X2 : PPC :: R2 ; for ( auto & MI : MBB ) { if ( ! hasTOCLoReloc ( MI ) ) continue ; MI . addOperand ( MachineOperand :: CreateReg ( TOCReg , false , true ) ) ; Changed = true ; } return Changed ; } </s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s> MVT :: SimpleValueType SPUTargetLowering :: getSetCCResultType ( EVT VT ) const { return ( ( VT == MVT :: i8 || VT == MVT :: i16 || VT == MVT :: i32 ) ? VT . getSimpleVT ( ) . SimpleTy : MVT :: i32 ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> const char * SparcTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case SPISD :: CMPICC : return "SPISD::CMPICC" ; case SPISD :: CMPFCC : return "SPISD::CMPFCC" ; case SPISD :: BRICC : return "SPISD::BRICC" ; case SPISD :: BRFCC : return "SPISD::BRFCC" ; case SPISD :: SELECT_ICC : return "SPISD::SELECT_ICC" ; case SPISD :: SELECT_FCC : return "SPISD::SELECT_FCC" ; case SPISD :: Hi : return "SPISD::Hi" ; case SPISD :: Lo : return "SPISD::Lo" ; case SPISD :: FTOI : return "SPISD::FTOI" ; case SPISD :: ITOF : return "SPISD::ITOF" ; case SPISD :: CALL : return "SPISD::CALL" ; case SPISD :: RET_FLAG : return "SPISD::RET_FLAG" ; } } </s>

getTargetNodeName - This method returns the name of a target specific

Sparc Sparc 0 SPISD::CMPICC "SPISD::CMPICC" SPISD::CMPFCC "SPISD::CMPFCC" SPISD::BRICC "SPISD::BRICC" SPISD::BRFCC "SPISD::BRFCC" SPISD::SELECT_ICC "SPISD::SELECT_ICC" SPISD::SELECT_FCC "SPISD::SELECT_FCC" SPISD::Hi "SPISD::Hi" SPISD::Lo "SPISD::Lo" SPISD::FTOI "SPISD::FTOI" SPISD::ITOF "SPISD::ITOF" SPISD::CALL "SPISD::CALL" SPISD::RET_FLAG "SPISD::RET_FLAG"


<s> bool PatmosInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { return false ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> bool loongarch_symbol_binds_local_p ( const_rtx x ) { if ( TARGET_DIRECT_EXTERN_ACCESS ) return true ; if ( SYMBOL_REF_P ( x ) ) return ( SYMBOL_REF_DECL ( x ) ? targetm . binds_local_p ( SYMBOL_REF_DECL ( x ) ) : SYMBOL_REF_LOCAL_P ( x ) ) ; else return false ; } </s>

Return true if SYMBOL_REF X binds locally .


"definition of static data member %q+D of "

Return true if DECL should be a dllimport 'd object .


"instruction requires a WASM feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> Register MipsFunctionInfo :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( & getGlobalBaseRegClass ( MF ) ) ; return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { MachineFunction & MF = MIRBuilder . getMF ( ) ; LLT p0 = LLT :: pointer ( 0 , 64 ) ; LLT s64 = LLT :: scalar ( 64 ) ; if ( IsTailCall ) { Offset += FPDiff ; int FI = MF . getFrameInfo ( ) . CreateFixedObject ( Size , Offset , true ) ; Register FIReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildFrameIndex ( FIReg , FI ) ; MPO = MachinePointerInfo :: getFixedStack ( MF , FI ) ; return FIReg ; } Register SPReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildCopy ( SPReg , Register ( AArch64 :: SP ) ) ; Register OffsetReg = MRI . createGenericVirtualRegister ( s64 ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; Register AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildGEP ( AddrReg , SPReg , OffsetReg ) ; MPO = MachinePointerInfo :: getStack ( MF , Offset ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s>
void
arc_final_prescan_insn
(
rtx_insn
*
insn
,
rtx
*
opvec
ATTRIBUTE_UNUSED
,
int
noperands
ATTRIBUTE_UNUSED
)
{
if
(
TARGET_DUMPISIZE
)
fprintf
(
asm_out_file
,
"\n; at %04x\n"
,
INSN_ADDRESSES
(
INSN_UID
(
insn
)
)
)
;
if
(
PREV_INSN
(
insn
)
&&
PREV_INSN
(
NEXT_INSN
(
insn
)
)
==
insn
&&
arc_hazard
(
prev_real_insn
(
insn
)
,
insn
)
)
{
current_output_insn
=
emit_insn_before
(
gen_nop
(
)
,
NEXT_INSN
(
PREV_INSN
(
insn
)
)
)
;
final_scan_insn
(
current_output_insn
,
asm_out_file
,
optimize
,
1
,
)
;
current_output_insn
=
insn
;
}
extract_constrain_insn_cached
(
insn
)
;
if
(
!
cfun
->
machine
->
prescan_initialized
)
{
memset
(
&
arc_ccfsm_current
,
0
,
sizeof
arc_ccfsm_current
)
;
cfun
->
machine
->
prescan_initialized
=
1
;
}
arc_ccfsm_advance
(
insn
,
&
arc_ccfsm_current
)
;
cfun
->
machine
->
size_reason
=
0
;
}
</s>

The state of the fsm controlling condition codes are : 0 : normal , do nothing special 1 : do n't output this insn 2 : do n't output this insn 3 : make insns conditional 4 : make insns conditional State transitions ( state- > state by whom , under what condition ) : 0 - > 1 final_prescan_insn , if insn is conditional branch 0 - > 2 final_prescan_insn , if the ` target ' is an unconditional branch 1 - > 3 branch patterns , after having not output the conditional branch 2 - > 4 branch patterns , after having not output the conditional branch 3 - > 0 ( * targetm.asm_out.internal_label ) , if the ` target ' label is reached ( the target label has CODE_LABEL_NUMBER equal to arc_ccfsm_target_label ) . 4 - > 0 final_prescan_insn , if ` target ' unconditional branch is reached If the jump clobbers the conditions then we use states 2 and 4 . A similar thing can be done with conditional return insns . We also handle separating branches from sets of the condition code . This is done here because knowledge of the ccfsm state is required , we may not be outputting the branch .


"code model %qs not supported in ilp32 mode"

A checking mechanism for the implementation of the various code models .


<s> static bool s390_hard_regno_scratch_ok ( unsigned int regno ) { if ( GENERAL_REGNO_P ( regno ) && ! call_really_used_regs [ regno ] && cfun_gpr_save_slot ( regno ) == SAVE_SLOT_NONE ) return false ; return true ; } </s>

Return nonzero if register REGNO can be used as a scratch register in peephole2 .


"this definition requires the MVE ISA extension"

Implement # pragma GCC arm `` arm_mve_types.h '' .


<s> void BTFTypeStruct :: completeType ( BTFDebug & BDebug ) { if ( IsCompleted ) return ; IsCompleted = true ; BTFType . NameOff = BDebug . addString ( STy -> getName ( ) ) ; const DINodeArray Elements = STy -> getElements ( ) ; for ( const auto * Element : Elements ) { struct BTF :: BTFMember BTFMember ; const auto * DDTy = cast < DIDerivedType > ( Element ) ; BTFMember . NameOff = BDebug . addString ( DDTy -> getName ( ) ) ; if ( HasBitField ) { uint8_t BitFieldSize = DDTy -> isBitField ( ) ? DDTy -> getSizeInBits ( ) : 0 ; BTFMember . Offset = BitFieldSize << 24 | DDTy -> getOffsetInBits ( ) ; } else { BTFMember . Offset = DDTy -> getOffsetInBits ( ) ; } const auto * BaseTy = DDTy -> getBaseType ( ) ; BTFMember . Type = BDebug . getTypeId ( BaseTy ) ; MemberTypeNoQual . push_back ( BDebug . getTypeId ( stripQualifiers ( BaseTy ) ) ) ; Members . push_back ( BTFMember ) ; } } </s>

Complete BTF type generation after all related DebugInfo types have been visited so their BTF type id 's are available for cross referece .


<s> static void arc_finalize_pic ( void ) { rtx pat ; rtx baseptr_rtx = gen_rtx_REG ( Pmode , PIC_OFFSET_TABLE_REGNUM ) ; if ( crtl -> uses_pic_offset_table == 0 ) return ; gcc_assert ( flag_pic != 0 ) ; pat = gen_rtx_SYMBOL_REF ( Pmode , "_DYNAMIC" ) ; pat = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , pat ) , ARC_UNSPEC_GOT ) ; pat = gen_rtx_CONST ( Pmode , pat ) ; pat = gen_rtx_SET ( VOIDmode , baseptr_rtx , pat ) ; emit_insn ( pat ) ; } </s>

If the function has any GOTOFF relocations , then the GOTBASE register has to be setup in the prologue The instruction needed at the function start for setting up the GOTBASE register is add rdest , pc , -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The rtl to be emitted for this should be : set ( reg basereg ) ( plus ( reg pc ) ( const ( unspec ( symref _DYNAMIC ) 3 ) ) ) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --


<s> unsigned X86AsmBackend :: getMaximumNopSize ( ) const { if ( STI . hasFeature ( X86 :: Mode16Bit ) ) return 4 ; if ( ! STI . hasFeature ( X86 :: FeatureNOPL ) && ! STI . hasFeature ( X86 :: Mode64Bit ) ) return 1 ; if ( STI . getFeatureBits ( ) [ X86 :: TuningFast7ByteNOP ] ) return 7 ; if ( STI . getFeatureBits ( ) [ X86 :: TuningFast15ByteNOP ] ) return 15 ; if ( STI . getFeatureBits ( ) [ X86 :: TuningFast11ByteNOP ] ) return 11 ; return 10 ; } </s>

Returns the maximum size of a nop in bytes on this target .


<s> void SICMCCodeEmitter :: EmitInstruction ( uint64_t Val , unsigned Size , raw_ostream & OS ) const { for ( unsigned i = 0 ; i < Size ; ++ i ) { unsigned Shift = IsLittleEndian ? i * 8 : ( Size - 1 - i ) * 8 ; EmitByte ( ( Val >> Shift ) & 0xff , OS ) ; } } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static int mn10300_adjust_sched_cost ( rtx_insn * insn , int dep_type , rtx_insn * dep , int cost , unsigned int ) { rtx insn_set ; rtx dep_set ; int timings ; if ( ! TARGET_AM33 ) return 1 ; insn_set = single_set ( insn ) ; if ( ! insn_set ) return cost ; dep_set = single_set ( dep ) ; if ( ! dep_set ) return cost ; if ( mn10300_tune_cpu == PROCESSOR_AM34 && set_is_load_p ( dep_set ) && set_is_store_p ( insn_set ) ) cost += 1 ; else if ( mn10300_tune_cpu == PROCESSOR_AM34 && ! set_is_store_p ( insn_set ) && ! JUMP_P ( insn ) && GET_MODE_CLASS ( GET_MODE ( SET_SRC ( dep_set ) ) ) == MODE_FLOAT && GET_MODE_CLASS ( GET_MODE ( SET_SRC ( insn_set ) ) ) == MODE_FLOAT ) cost += 1 ; if ( ! TARGET_AM33_2 ) return cost ; if ( dep_type == 0 ) return cost ; if ( GET_MODE_CLASS ( GET_MODE ( SET_SRC ( dep_set ) ) ) != MODE_FLOAT ) return cost ; if ( ! set_is_load_p ( insn_set ) && ! set_is_store_p ( insn_set ) ) return cost ; if ( GET_MODE_CLASS ( GET_MODE ( SET_SRC ( insn_set ) ) ) != MODE_INT ) return cost ; timings = get_attr_timings ( insn ) ; return timings < 100 ? ( timings % 10 ) : ( timings % 100 ) ; } </s>

Update scheduling costs for situations that can not be described using the attributes and DFA machinery . DEP is the insn being scheduled . INSN is the previous insn . COST is the current cycle cost for DEP .


"Switch should handle all register classes"


<s> const MCExpr * getSubExpr ( ) const { return Expr ; } </s>

getSubExpr - Get the child of this expression .


<s> int SystemZFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const MachineFrameInfo * MFFrame = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; FrameReg = RI -> getFrameRegister ( MF ) ; int64_t Offset = ( MFFrame -> getObjectOffset ( FI ) + MFFrame -> getOffsetAdjustment ( ) ) ; Offset -= getOffsetOfLocalArea ( ) ; Offset += getAllocatedStackSize ( MF ) ; return Offset ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> MCSection * getExplicitSectionGlobal ( const GlobalObject * GO , SectionKind Kind , const TargetMachine & TM ) const override { return DataSection ; } </s>

Targets should implement this method to assign a section to globals with an explicit section specfied .


<s> bool HexagonInstrInfo :: isTailCall ( const MachineInstr & MI ) const { if ( ! MI . isBranch ( ) ) return false ; for ( auto & Op : MI . operands ( ) ) if ( Op . isGlobal ( ) || Op . isSymbol ( ) ) return true ; return false ; } </s>

Determines whether Inst is a tail call instruction .


<s>
void
MachineConstPropagator
::
propagate
(
MachineFunction
&
MF
)
{
MachineBasicBlock
*
Entry
=
GraphTraits
<
MachineFunction
*
>
::
getEntryNode
(
&
MF
)
;
unsigned
EntryNum
=
Entry
->
getNumber
(
)
;
FlowQ
.
push
(
CFGEdge
(
EntryNum
,
EntryNum
)
)
;
while
(
!
FlowQ
.
empty
(
)
)
{
CFGEdge
Edge
=
FlowQ
.
front
(
)
;
FlowQ
.
pop
(
)
;
DEBUG
(
dbgs
(
)
<<
"Picked edge "
<<
printMBBReference
(
*
MF
.
getBlockNumbered
(
Edge
.
first
)
)
<<
"->"
<<
printMBBReference
(
*
MF
.
getBlockNumbered
(
Edge
.
second
)
)
<<
'\n'
)
;
if
(
Edge
.
first
!=
EntryNum
)
if
(
EdgeExec
.
count
(
Edge
)
)
continue
;
EdgeExec
.
insert
(
Edge
)
;
MachineBasicBlock
*
SB
=
MF
.
getBlockNumbered
(
Edge
.
second
)
;
MachineBasicBlock
::
const_iterator
It
=
SB
->
begin
(
)
,
End
=
SB
->
end
(
)
;
while
(
It
!=
End
&&
It
->
isPHI
(
)
)
{
InstrExec
.
insert
(
&
*
It
)
;
visitPHI
(
*
It
)
;
++
It
;
}
while
(
It
!=
End
&&
It
->
isDebugValue
(
)
)
++
It
;
assert
(
It
==
End
||
!
It
->
isPHI
(
)
)
;
if
(
It
!=
End
&&
InstrExec
.
count
(
&
*
It
)
)
continue
;
while
(
It
!=
End
&&
!
It
->
isBranch
(
)
)
{
if
(
!
It
->
isDebugValue
(
)
)
{
InstrExec
.
insert
(
&
*
It
)
;
visitNonBranch
(
*
It
)
;
}
++
It
;
}
if
(
It
!=
End
)
{
visitBranchesFrom
(
*
It
)
;
}
else
{
unsigned
SBN
=
SB
->
getNumber
(
)
;
for
(
const
MachineBasicBlock
*
SSB
:
SB
->
successors
(
)
)
FlowQ
.
push
(
CFGEdge
(
SBN
,
SSB
->
getNumber
(
)
)
)
;
}
}
DEBUG
(
{
dbgs
(
)
<<
"Cells after propagation:\n"
;
Cells
.
print
(
dbgs
(
)
,
MCE
.
TRI
)
;
dbgs
(
)
<<
"Dead CFG edges:\n"
;
for
(
const
MachineBasicBlock
&
B
:
MF
)
{
unsigned
BN
=
B
.
getNumber
(
)
;
for
(
const
MachineBasicBlock
*
SB
:
B
.
successors
(
)
)
{
unsigned
SN
=
SB
->
getNumber
(
)
;
if
(
!
EdgeExec
.
count
(
CFGEdge
(
BN
,
SN
)
)
)
dbgs
(
)
<<
"  "
<<
printMBBReference
(
B
)
<<
" -> "
<<
printMBBReference
(
*
SB
)
<<
'\n'
;
}
}
}
)
;
}
</s>

Propgate synthetic entry counts on a callgraph CG .

Hexagon
"Picked edge "
"->"
"Cells after propagation:\n"
"Dead CFG edges:\n"
"  "
" -> "


<s> static unsigned int ix86_minimum_incoming_stack_boundary ( bool sibcall ) { unsigned int incoming_stack_boundary ; if ( cfun -> machine -> func_type != TYPE_NORMAL ) incoming_stack_boundary = TARGET_64BIT ? 128 : MIN_STACK_BOUNDARY ; else if ( ix86_user_incoming_stack_boundary ) incoming_stack_boundary = ix86_user_incoming_stack_boundary ; else if ( ! sibcall && ix86_force_align_arg_pointer && crtl -> stack_alignment_estimated == 128 ) incoming_stack_boundary = MIN_STACK_BOUNDARY ; else incoming_stack_boundary = ix86_default_incoming_stack_boundary ; if ( incoming_stack_boundary > MIN_STACK_BOUNDARY && lookup_attribute ( "force_align_arg_pointer" , TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ) ) incoming_stack_boundary = MIN_STACK_BOUNDARY ; if ( incoming_stack_boundary < crtl -> parm_stack_boundary ) incoming_stack_boundary = crtl -> parm_stack_boundary ; if ( incoming_stack_boundary > MAIN_STACK_BOUNDARY && DECL_NAME ( current_function_decl ) && MAIN_NAME_P ( DECL_NAME ( current_function_decl ) ) && DECL_FILE_SCOPE_P ( current_function_decl ) ) incoming_stack_boundary = MAIN_STACK_BOUNDARY ; return incoming_stack_boundary ; } </s>

Return minimum incoming stack alignment .


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const PPCFrameLowering * PPCFI = static_cast < const PPCFrameLowering * > ( MF . getSubtarget ( ) . getFrameLowering ( ) ) ; Reserved . set ( PPC :: ZERO ) ; Reserved . set ( PPC :: ZERO8 ) ; Reserved . set ( PPC :: FP ) ; Reserved . set ( PPC :: FP8 ) ; Reserved . set ( PPC :: BP ) ; Reserved . set ( PPC :: BP8 ) ; Reserved . set ( PPC :: CTR ) ; Reserved . set ( PPC :: CTR8 ) ; Reserved . set ( PPC :: R1 ) ; Reserved . set ( PPC :: LR ) ; Reserved . set ( PPC :: LR8 ) ; Reserved . set ( PPC :: RM ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) Reserved . set ( PPC :: VRSAVE ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: R2 ) ; Reserved . set ( PPC :: R13 ) ; } if ( Subtarget . isPPC64 ( ) ) { Reserved . set ( PPC :: R13 ) ; Reserved . set ( PPC :: X1 ) ; Reserved . set ( PPC :: X13 ) ; if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: X31 ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( PPC :: X30 ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: X2 ) ; } } if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: R31 ) ; if ( hasBasePointer ( MF ) ) { if ( Subtarget . isSVR4ABI ( ) && ! Subtarget . isPPC64 ( ) && MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) Reserved . set ( PPC :: R29 ) ; else Reserved . set ( PPC :: R30 ) ; } if ( Subtarget . isSVR4ABI ( ) && ! Subtarget . isPPC64 ( ) && MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) Reserved . set ( PPC :: R30 ) ; if ( ! Subtarget . hasAltivec ( ) ) for ( TargetRegisterClass :: iterator I = PPC :: VRRCRegClass . begin ( ) , IE = PPC :: VRRCRegClass . end ( ) ; I != IE ; ++ I ) Reserved . set ( * I ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> BitVector VideocoreRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( VC :: SP ) ; Reserved . set ( VC :: LR ) ; Reserved . set ( VC :: SR ) ; Reserved . set ( VC :: PC ) ; return Reserved ; } </s>

Videocore Videocore VC::SP VC::LR VC::SR VC::PC


"ShadowCallStack attribute not supported on Darwin."

"ShadowCallStack attribute not supported with swifttail"

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Lanai load / store optimization pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .

Lanai
"Lanai load / store optimization pass"


<s>
void
AMDGPUAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
)
const
{
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
uint32_t
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
Data
[
Offset
+
i
]
|=
static_cast
<
uint8_t
>
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> SDValue MBlazeTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_MBlaze ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> BitVector NyuziRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( Nyuzi :: SP_REG ) ; Reserved . set ( Nyuzi :: RA_REG ) ; Reserved . set ( Nyuzi :: FP_REG ) ; Reserved . set ( Nyuzi :: GP_REG ) ; return Reserved ; } </s>


<s> void init_builtins ( ) { rvv_switcher rvv ; if ( ! TARGET_VECTOR ) return ; register_builtin_types ( ) ; if ( in_lto_p ) handle_pragma_vector ( ) ; } </s>

Initialize all compiler built-ins related to RVV that should be defined at start-up .


<s> static void arc_init_reg_tables ( void ) { int i ; for ( i = 0 ; i < NUM_MACHINE_MODES ; i ++ ) { machine_mode m = ( machine_mode ) i ; switch ( GET_MODE_CLASS ( m ) ) { case MODE_INT : case MODE_PARTIAL_INT : case MODE_COMPLEX_INT : if ( GET_MODE_SIZE ( m ) <= 4 ) arc_mode_class [ i ] = 1 << ( int ) S_MODE ; else if ( GET_MODE_SIZE ( m ) == 8 ) arc_mode_class [ i ] = 1 << ( int ) D_MODE ; else if ( GET_MODE_SIZE ( m ) == 16 ) arc_mode_class [ i ] = 1 << ( int ) T_MODE ; else if ( GET_MODE_SIZE ( m ) == 32 ) arc_mode_class [ i ] = 1 << ( int ) O_MODE ; else arc_mode_class [ i ] = 0 ; break ; case MODE_FLOAT : case MODE_COMPLEX_FLOAT : if ( GET_MODE_SIZE ( m ) <= 4 ) arc_mode_class [ i ] = 1 << ( int ) SF_MODE ; else if ( GET_MODE_SIZE ( m ) == 8 ) arc_mode_class [ i ] = 1 << ( int ) DF_MODE ; else if ( GET_MODE_SIZE ( m ) == 16 ) arc_mode_class [ i ] = 1 << ( int ) TF_MODE ; else if ( GET_MODE_SIZE ( m ) == 32 ) arc_mode_class [ i ] = 1 << ( int ) OF_MODE ; else arc_mode_class [ i ] = 0 ; break ; case MODE_VECTOR_INT : arc_mode_class [ i ] = ( 1 << ( int ) V_MODE ) ; break ; case MODE_CC : default : if ( i == ( int ) CCmode || i == ( int ) CC_ZNmode || i == ( int ) CC_Zmode || i == ( int ) CC_Cmode || i == CC_FP_GTmode || i == CC_FP_GEmode || i == CC_FP_ORDmode || i == CC_FPUmode || i == CC_FPU_UNEQmode ) arc_mode_class [ i ] = 1 << ( int ) C_MODE ; else arc_mode_class [ i ] = 0 ; break ; } } } </s>


<s> static bool alpha_store_data_bypass_p_1 ( rtx_insn * out_insn , rtx in_set ) { if ( ! MEM_P ( SET_DEST ( in_set ) ) ) return false ; rtx out_set = single_set ( out_insn ) ; if ( out_set ) return ! reg_mentioned_p ( SET_DEST ( out_set ) , SET_DEST ( in_set ) ) ; rtx out_pat = PATTERN ( out_insn ) ; if ( GET_CODE ( out_pat ) != PARALLEL ) return false ; for ( int i = 0 ; i < XVECLEN ( out_pat , 0 ) ; i ++ ) { rtx out_exp = XVECEXP ( out_pat , 0 , i ) ; if ( GET_CODE ( out_exp ) == CLOBBER || GET_CODE ( out_exp ) == USE || GET_CODE ( out_exp ) == TRAP_IF ) continue ; gcc_assert ( GET_CODE ( out_exp ) == SET ) ; if ( reg_mentioned_p ( SET_DEST ( out_exp ) , SET_DEST ( in_set ) ) ) return false ; } return true ; } </s>

Helper function for alpha_store_data_bypass_p , handle just a single SET IN_SET .


<s>
const
char
*
getPassName
(
)
const
{
return
"SI Lower control flow instructions"
;
}
</s>


"  Skipping pass: no machine model present.\n"

runOnMachineFunction - Emit the function body .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Alpha Assembly Printer"
;
}
</s>


<s> void PPCTTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP ) { if ( ST -> getCPUDirective ( ) == PPC :: DIR_A2 ) { UP . Partial = UP . Runtime = true ; UP . AllowExpensiveTripCount = true ; } BaseT :: getUnrollingPreferences ( L , SE , UP ) ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> int mmix_local_alignment ( tree type ATTRIBUTE_UNUSED , int basic_align ) { if ( basic_align < 32 ) return 32 ; return basic_align ; } </s>


<s> int riscv_const_insns ( rtx x ) { enum riscv_symbol_type symbol_type ; rtx offset ; switch ( GET_CODE ( x ) ) { case HIGH : if ( ! riscv_symbolic_constant_p ( XEXP ( x , 0 ) , & symbol_type ) || ! riscv_split_symbol_type ( symbol_type ) ) return 0 ; return 1 ; case CONST_INT : { int cost = riscv_integer_cost ( INTVAL ( x ) ) ; return cost < 4 ? cost : 0 ; } case CONST_DOUBLE : case CONST_VECTOR : return x == CONST0_RTX ( GET_MODE ( x ) ) ? 1 : 0 ; case CONST : if ( riscv_symbolic_constant_p ( x , & symbol_type ) ) return riscv_symbol_insns ( symbol_type ) ; split_const ( x , & x , & offset ) ; if ( offset != 0 ) { int n = riscv_const_insns ( x ) ; if ( n != 0 ) return n + riscv_integer_cost ( INTVAL ( offset ) ) ; } return 0 ; case SYMBOL_REF : case LABEL_REF : return riscv_symbol_insns ( riscv_classify_symbol ( x ) ) ; default : return 0 ; } } </s>

Return the number of instructions needed to load constant X . Return 0 if X is n't a valid constant .


<s> Instruction * RISCVTargetLowering :: emitLeadingFence ( IRBuilder < > & Builder , Instruction * Inst , AtomicOrdering Ord ) const { if ( isa < LoadInst > ( Inst ) && Ord == AtomicOrdering :: SequentiallyConsistent ) return Builder . CreateFence ( Ord ) ; if ( isa < StoreInst > ( Inst ) && isReleaseOrStronger ( Ord ) ) return Builder . CreateFence ( AtomicOrdering :: Release ) ; return nullptr ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"Hexagon RDF optimizations"
;
}
</s>


<s> virtual bool check ( function_checker & ) const { return true ; } </s>

Perform semantic checks on the call . Return true if the call is valid , otherwise report a suitable error .


<s>
SUnit
*
GCNMaxOccupancySchedStrategy
::
pickNodeBidirectional
(
bool
&
IsTopNode
)
{
if
(
SUnit
*
SU
=
Bot
.
pickOnlyChoice
(
)
)
{
IsTopNode
=
false
;
return
SU
;
}
if
(
SUnit
*
SU
=
Top
.
pickOnlyChoice
(
)
)
{
IsTopNode
=
true
;
return
SU
;
}
CandPolicy
BotPolicy
;
setPolicy
(
BotPolicy
,
false
,
Bot
,
&
Top
)
;
CandPolicy
TopPolicy
;
setPolicy
(
TopPolicy
,
false
,
Top
,
&
Bot
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Picking from Bot:\n"
)
;
if
(
!
BotCand
.
isValid
(
)
||
BotCand
.
SU
->
isScheduled
||
BotCand
.
Policy
!=
BotPolicy
)
{
BotCand
.
reset
(
CandPolicy
(
)
)
;
pickNodeFromQueue
(
Bot
,
BotPolicy
,
DAG
->
getBotRPTracker
(
)
,
BotCand
)
;
assert
(
BotCand
.
Reason
!=
NoCand
&&
"failed to find the first candidate"
)
;
}
else
{
LLVM_DEBUG
(
traceCandidate
(
BotCand
)
)
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Picking from Top:\n"
)
;
if
(
!
TopCand
.
isValid
(
)
||
TopCand
.
SU
->
isScheduled
||
TopCand
.
Policy
!=
TopPolicy
)
{
TopCand
.
reset
(
CandPolicy
(
)
)
;
pickNodeFromQueue
(
Top
,
TopPolicy
,
DAG
->
getTopRPTracker
(
)
,
TopCand
)
;
assert
(
TopCand
.
Reason
!=
NoCand
&&
"failed to find the first candidate"
)
;
}
else
{
LLVM_DEBUG
(
traceCandidate
(
TopCand
)
)
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Top Cand: "
;
traceCandidate
(
TopCand
)
;
dbgs
(
)
<<
"Bot Cand: "
;
traceCandidate
(
BotCand
)
;
)
;
SchedCandidate
Cand
;
if
(
TopCand
.
Reason
==
BotCand
.
Reason
)
{
Cand
=
BotCand
;
GenericSchedulerBase
::
CandReason
TopReason
=
TopCand
.
Reason
;
TopCand
.
Reason
=
NoCand
;
GenericScheduler
::
tryCandidate
(
Cand
,
TopCand
,
nullptr
)
;
if
(
TopCand
.
Reason
!=
NoCand
)
{
Cand
.
setBest
(
TopCand
)
;
}
else
{
TopCand
.
Reason
=
TopReason
;
}
}
else
{
if
(
TopCand
.
Reason
==
RegExcess
&&
TopCand
.
RPDelta
.
Excess
.
getUnitInc
(
)
<=
0
)
{
Cand
=
TopCand
;
}
else
if
(
BotCand
.
Reason
==
RegExcess
&&
BotCand
.
RPDelta
.
Excess
.
getUnitInc
(
)
<=
0
)
{
Cand
=
BotCand
;
}
else
if
(
TopCand
.
Reason
==
RegCritical
&&
TopCand
.
RPDelta
.
CriticalMax
.
getUnitInc
(
)
<=
0
)
{
Cand
=
TopCand
;
}
else
if
(
BotCand
.
Reason
==
RegCritical
&&
BotCand
.
RPDelta
.
CriticalMax
.
getUnitInc
(
)
<=
0
)
{
Cand
=
BotCand
;
}
else
{
if
(
BotCand
.
Reason
>
TopCand
.
Reason
)
{
Cand
=
TopCand
;
}
else
{
Cand
=
BotCand
;
}
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Picking: "
;
traceCandidate
(
Cand
)
;
)
;
IsTopNode
=
Cand
.
AtTop
;
return
Cand
.
SU
;
}
</s>

Pick the best candidate node from either the top or bottom queue .

AMDGPU
"Picking from Bot:\n"
"failed to find the first candidate"
"Picking from Top:\n"
"failed to find the first candidate"
"Top Cand: "
"Bot Cand: "
0
0
0
0
"Picking: "


<s> void mips_expand_vec_unpack ( rtx operands [ 2 ] , bool unsigned_p , bool high_p ) { machine_mode imode = GET_MODE ( operands [ 1 ] ) ; rtx ( * unpack ) ( rtx , rtx , rtx ) ; rtx ( * cmpgt ) ( rtx , rtx , rtx ) ; rtx tmp , dest , zero ; switch ( imode ) { case V8QImode : if ( high_p ) unpack = gen_loongson_punpckhbh ; else unpack = gen_loongson_punpcklbh ; cmpgt = gen_loongson_pcmpgtb ; break ; case V4HImode : if ( high_p ) unpack = gen_loongson_punpckhhw ; else unpack = gen_loongson_punpcklhw ; cmpgt = gen_loongson_pcmpgth ; break ; default : gcc_unreachable ( ) ; } zero = force_reg ( imode , CONST0_RTX ( imode ) ) ; if ( unsigned_p ) tmp = zero ; else { tmp = gen_reg_rtx ( imode ) ; emit_insn ( cmpgt ( tmp , zero , operands [ 1 ] ) ) ; } dest = gen_reg_rtx ( imode ) ; emit_insn ( unpack ( dest , operands [ 1 ] , tmp ) ) ; emit_move_insn ( operands [ 0 ] , gen_lowpart ( GET_MODE ( operands [ 0 ] ) , dest ) ) ; } </s>

Expand an integral vector unpack operation .


"getArithmeticInstrCost() called with vector type."

This is an approximation of reciprocal throughput of a math/logic op .


"Declaring this symbol tells the CRT that there is "

"something in BSS, so it may need to be zeroed."

"Declaring this symbol tells the CRT that there is something in .data, "

"so it may need to be copied from LMA to VMA."

"Declaring this symbol tells the CRT that there are "

"initialization routines to be run in .init_array"

"finalization routines to be run in .fini_array"

"Declaring this symbol tells the CRT that the stack "

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> int ARMTTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) { if ( ( Opcode == Instruction :: SDiv || Opcode == Instruction :: UDiv || Opcode == Instruction :: SRem || Opcode == Instruction :: URem ) && Idx == 1 ) return 0 ; if ( Opcode == Instruction :: And ) { if ( Imm == 255 || Imm == 65535 ) return 0 ; return std :: min ( getIntImmCost ( Imm , Ty ) , getIntImmCost ( ~ Imm , Ty ) ) ; } if ( Opcode == Instruction :: Add ) return std :: min ( getIntImmCost ( Imm , Ty ) , getIntImmCost ( - Imm , Ty ) ) ; if ( Opcode == Instruction :: ICmp && Imm . isNegative ( ) && Ty -> getIntegerBitWidth ( ) == 32 ) { int64_t NegImm = - Imm . getSExtValue ( ) ; if ( ST -> isThumb2 ( ) && NegImm < 1 << 12 ) return 0 ; if ( ST -> isThumb ( ) && NegImm < 1 << 8 ) return 0 ; } if ( Opcode == Instruction :: Xor && Imm . isAllOnesValue ( ) ) return 0 ; return getIntImmCost ( Imm , Ty ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> BitVector SparcRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( SP :: G1 ) ; if ( ReserveAppRegisters ) { Reserved . set ( SP :: G2 ) ; Reserved . set ( SP :: G3 ) ; Reserved . set ( SP :: G4 ) ; } if ( ! Subtarget . is64Bit ( ) ) Reserved . set ( SP :: G5 ) ; Reserved . set ( SP :: O6 ) ; Reserved . set ( SP :: I6 ) ; Reserved . set ( SP :: I7 ) ; Reserved . set ( SP :: G0 ) ; Reserved . set ( SP :: G6 ) ; Reserved . set ( SP :: G7 ) ; return Reserved ; } </s>


<s> const TargetRegisterClass * M680x0RegisterInfo :: getRegsForTailCall ( const MachineFunction & MF ) const { return & M680x0 :: XR32_TCRegClass ; } </s>

Returns a register class with registers that can be used in forming tail calls .


"%Klane index must be a constant immediate"

"%Ktotal size and element size must be a non-zero constant immediate"

Expand an AArch64 AdvSIMD builtin ( intrinsic ) .


<s>
DecodeStatus
CSKYDisassembler
::
getInstruction
(
MCInst
&
MI
,
uint64_t
&
Size
,
ArrayRef
<
uint8_t
>
Bytes
,
uint64_t
Address
,
raw_ostream
&
CS
)
const
{
uint32_t
Insn
;
DecodeStatus
Result
=
MCDisassembler
::
Fail
;
Insn
=
support
::
endian
::
read16le
(
Bytes
.
data
(
)
)
;
if
(
(
Insn
>>
14
)
==
0x3
)
{
if
(
Bytes
.
size
(
)
<
4
)
{
Size
=
0
;
return
MCDisassembler
::
Fail
;
}
Insn
=
(
Insn
<<
16
)
|
support
::
endian
::
read16le
(
&
Bytes
[
2
]
)
;
if
(
decodeFPUV3Instruction
(
MI
,
Insn
,
Address
,
this
,
STI
)
)
Result
=
MCDisassembler
::
Success
;
else
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Trying CSKY 32-bit table :\n"
)
;
Result
=
decodeInstruction
(
DecoderTable32
,
MI
,
Insn
,
Address
,
this
,
STI
)
;
}
Size
=
4
;
}
else
{
if
(
Bytes
.
size
(
)
<
2
)
{
Size
=
0
;
return
MCDisassembler
::
Fail
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Trying CSKY 16-bit table :\n"
)
;
Result
=
decodeInstruction
(
DecoderTable16
,
MI
,
Insn
,
Address
,
this
,
STI
)
;
Size
=
2
;
}
handleCROperand
(
MI
)
;
return
Result
;
}
</s>

Returns the disassembly of a single instruction .


"operand for sleep instruction must be an unsigned 6 bit compile-time constant"

Check that after all the constant folding , whether the operand to __builtin_arc_sleep is an unsigned int of 6 bits . If not , flag an error .


<s> void AMDGPUAsmParser :: peekTokens ( MutableArrayRef < AsmToken > Tokens ) { auto TokCount = getLexer ( ) . peekTokens ( Tokens ) ; for ( auto Idx = TokCount ; Idx < Tokens . size ( ) ; ++ Idx ) Tokens [ Idx ] = AsmToken ( AsmToken :: Error , "" ) ; } </s>

Look ahead an arbitrary number of tokens .


<s> bool M88kPassConfig :: addRegBankSelect ( ) { addPass ( new RegBankSelect ( ) ) ; return false ; } </s>

This method should install a register bank selector pass , which assigns register banks to virtual registers without a register class or register banks .


<s> void GCNPassConfig :: addFastRegAlloc ( ) { insertPass ( & PHIEliminationID , & SILowerControlFlowID , false ) ; insertPass ( & RegisterCoalescerID , & SIPreAllocateWWMRegsID , false ) ; TargetPassConfig :: addFastRegAlloc ( ) ; } </s>

addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast register allocation .


<s> static struct machine_function * cris_init_machine_status ( void ) { return ggc_alloc_cleared ( sizeof ( struct machine_function ) ) ; } </s>

Zero initialization is OK for all current fields .


<s>
static
void
recombine_stvx_pattern
(
rtx_insn
*
insn
,
del_info
*
to_delete
)
{
rtx
body
=
PATTERN
(
insn
)
;
gcc_assert
(
GET_CODE
(
body
)
==
SET
&&
MEM_P
(
SET_DEST
(
body
)
)
&&
(
GET_CODE
(
SET_SRC
(
body
)
)
==
VEC_SELECT
||
pattern_is_rotate64
(
body
)
)
)
;
rtx
mem
=
SET_DEST
(
body
)
;
rtx
base_reg
=
XEXP
(
mem
,
0
)
;
auto_vec
<
rtx_insn
*
>
and_insns
;
auto_vec
<
rtx
>
and_ops
;
bool
is_any_def_and
=
find_alignment_op
(
insn
,
base_reg
,
&
and_insns
,
&
and_ops
)
;
if
(
is_any_def_and
)
{
gcc_assert
(
and_insns
.
length
(
)
==
and_ops
.
length
(
)
)
;
rtx
src_reg
=
XEXP
(
SET_SRC
(
body
)
,
0
)
;
df_ref
src_use
;
struct
df_insn_info
*
insn_info
=
DF_INSN_INFO_GET
(
insn
)
;
FOR_EACH_INSN_INFO_USE
(
src_use
,
insn_info
)
{
if
(
!
rtx_equal_p
(
DF_REF_REG
(
src_use
)
,
src_reg
)
)
continue
;
struct
df_link
*
link
=
DF_REF_CHAIN
(
src_use
)
;
if
(
!
link
||
link
->
next
)
break
;
rtx_insn
*
swap_insn
=
DF_REF_INSN
(
link
->
ref
)
;
if
(
!
insn_is_swap_p
(
swap_insn
)
||
insn_is_load_p
(
swap_insn
)
||
insn_is_store_p
(
swap_insn
)
)
break
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace
=
true
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace_insn
=
swap_insn
;
rtx
new_reg
=
0
;
rtx
and_mask
=
0
;
for
(
unsigned
i
=
0
;
i
<
and_insns
.
length
(
)
;
i
++
)
{
rtx_insn
*
and_insn
=
and_insns
[
i
]
;
rtx
and_op
=
and_ops
[
i
]
;
rtx
and_base
=
XEXP
(
and_op
,
0
)
;
if
(
!
new_reg
)
{
new_reg
=
gen_reg_rtx
(
GET_MODE
(
and_base
)
)
;
and_mask
=
XEXP
(
and_op
,
1
)
;
}
rtx
copy
=
gen_rtx_SET
(
new_reg
,
and_base
)
;
rtx_insn
*
new_insn
=
emit_insn_after
(
copy
,
and_insn
)
;
set_block_for_insn
(
new_insn
,
BLOCK_FOR_INSN
(
and_insn
)
)
;
df_insn_rescan
(
new_insn
)
;
}
XEXP
(
mem
,
0
)
=
gen_rtx_AND
(
GET_MODE
(
new_reg
)
,
new_reg
,
and_mask
)
;
SET_SRC
(
body
)
=
src_reg
;
INSN_CODE
(
insn
)
=
1
;
df_insn_rescan
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"stvx opportunity found at %d\n"
,
INSN_UID
(
insn
)
)
;
}
}
}
</s>

If INSN is the store for an stvx pattern , put it in canonical form .


<s> bool RISCVDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { switch ( ConstraintID ) { case InlineAsm :: Constraint_i : case InlineAsm :: Constraint_m : OutOps . push_back ( Op ) ; return false ; case InlineAsm :: Constraint_A : OutOps . push_back ( Op ) ; return false ; default : break ; } return true ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


"Trying MicroMips16 table (16-bit instructions):\n"

"Trying MicroMips32 table (32-bit instructions):\n"

"Trying COP3_ table (32-bit opcodes):\n"

"Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"

"Trying Mips32r6_64r6 table (32-bit opcodes):\n"

"Trying Mips64 (GPR64) table (32-bit opcodes):\n"


<s>
const
char
*
m68k_output_scc
(
rtx_code
code
)
{
switch
(
code
)
{
case
EQ
:
return
"seq %0"
;
case
NE
:
return
"sne %0"
;
case
GT
:
return
"sgt %0"
;
case
GTU
:
return
"shi %0"
;
case
LT
:
return
"slt %0"
;
case
LTU
:
return
"scs %0"
;
case
GE
:
return
"sge %0"
;
case
GEU
:
return
"scc %0"
;
case
LE
:
return
"sle %0"
;
case
LEU
:
return
"sls %0"
;
case
PLUS
:
return
"spl %0"
;
case
MINUS
:
return
"smi %0"
;
default
:
gcc_unreachable
(
)
;
}
}
</s>

Return an output template for a scc instruction with CODE .


<s> bool Mips16FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , MutableArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


"unsupported return type %qT for simd\n"

"unsupported argument type %qT for simd\n"

Set CLONEI- > vecsize_mangle , CLONEI- > vecsize_int , CLONEI- > vecsize_float and if CLONEI- > simdlen is 0 , also CLONEI- > simdlen . Return 0 if SIMD clones should n't be emitted , or number of vecsize_mangle variants that should be emitted .


<s> static rtx rs6000_parallel_return ( machine_mode mode , int n_elts , machine_mode elt_mode , unsigned int regno , unsigned int reg_stride ) { rtx par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( n_elts ) ) ; int i ; for ( i = 0 ; i < n_elts ; i ++ ) { rtx r = gen_rtx_REG ( elt_mode , regno ) ; rtx off = GEN_INT ( i * GET_MODE_SIZE ( elt_mode ) ) ; XVECEXP ( par , 0 , i ) = gen_rtx_EXPR_LIST ( VOIDmode , r , off ) ; regno += reg_stride ; } return par ; } </s>

Return an rtx describing a return value of MODE as a PARALLEL in N_ELTS registers , each of mode ELT_MODE , starting at REGNO , stride REG_STRIDE .


<s> static bool msp430_use_32bit_hwmult ( void ) { static const char * cached_match = NULL ; static bool cached_result ; if ( msp430_hwmult_type == MSP430_HWMULT_LARGE ) return true ; if ( target_mcu == NULL || msp430_hwmult_type != MSP430_HWMULT_AUTO ) return false ; if ( target_mcu == cached_match ) return cached_result ; cached_match = target_mcu ; msp430_extract_mcu_data ( target_mcu ) ; if ( extracted_mcu_data . name != NULL ) return cached_result = extracted_mcu_data . hwmpy == 4 ; return cached_result = false ; } </s>

Returns true if the current MCU has a second generation 32-bit hardware multiplier .


<s> static int arc_arg_partial_bytes ( cumulative_args_t cum_v , machine_mode mode , tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int bytes = ( mode == BLKmode ? int_size_in_bytes ( type ) : ( int ) GET_MODE_SIZE ( mode ) ) ; int words = ( bytes + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; int arg_num = * cum ; int ret ; arg_num = ROUND_ADVANCE_CUM ( arg_num , mode , type ) ; ret = GPR_REST_ARG_REGS ( arg_num ) ; ret = ( ret >= words ? 0 : ret * UNITS_PER_WORD ) ; return ret ; } </s>


<s> unsigned SIRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; unsigned Occupancy = ST . getOccupancyWithLocalMemSize ( MFI -> getLDSSize ( ) , MF . getFunction ( ) ) ; switch ( RC -> getID ( ) ) { default : return AMDGPUGenRegisterInfo :: getRegPressureLimit ( RC , MF ) ; case AMDGPU :: VGPR_32RegClassID : return std :: min ( ST . getMaxNumVGPRs ( Occupancy ) , ST . getMaxNumVGPRs ( MF ) ) ; case AMDGPU :: SGPR_32RegClassID : return std :: min ( ST . getMaxNumSGPRs ( Occupancy , true ) , ST . getMaxNumSGPRs ( MF ) ) ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .

AMDGPU SI SI SI AMDGPU AMDGPU::VGPR_32RegClassID AMDGPU::SGPR_32RegClassID


<s> static bool loongarch_tls_symbol_p ( rtx x ) { return SYMBOL_REF_P ( x ) && SYMBOL_REF_TLS_MODEL ( x ) != 0 ; } </s>

Return true if X is a thread-local symbol .


<s>
static
int
write_one_arg
(
std
::
stringstream
&
s
,
tree
type
,
int
i
,
machine_mode
mode
,
bool
no_arg_types
)
{
if
(
!
PASS_IN_REG_P
(
mode
,
type
)
)
mode
=
Pmode
;
int
count
=
maybe_split_mode
(
&
mode
)
;
if
(
count
==
2
)
{
write_one_arg
(
s
,
NULL_TREE
,
i
,
mode
,
false
)
;
write_one_arg
(
s
,
NULL_TREE
,
i
+
1
,
mode
,
false
)
;
return
i
+
1
;
}
if
(
no_arg_types
&&
!
AGGREGATE_TYPE_P
(
type
)
)
{
if
(
mode
==
SFmode
)
mode
=
DFmode
;
mode
=
arg_promotion
(
mode
)
;
}
if
(
i
>
0
)
s
<<
", "
;
s
<<
".param"
<<
nvptx_ptx_type_from_mode
(
mode
,
false
)
<<
" %in_ar"
<<
(
i
+
1
)
<<
(
mode
==
QImode
||
mode
==
HImode
"[1]"
:
""
)
;
if
(
mode
==
BLKmode
)
s
<<
"["
<<
int_size_in_bytes
(
type
)
<<
"]"
;
return
i
;
}
</s>

Write the declaration of a function arg of TYPE to S. I is the index of the argument , MODE its mode . NO_ARG_TYPES is true if this is for a decl with zero TYPE_ARG_TYPES , i.e . an old-style C decl .


"Unsupported relocation: try to compile with -O2 or above, "

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


"Lowering returned the wrong number of results!"

This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types .


<s> static bool isInstr ( IndexType X ) { return X . Index >= First ; } </s>

Returns true if this SUnit refers to a machine instruction as opposed to an SDNode .


<s>
void
AGCAsmBackend
::
relaxInstruction
(
const
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
,
MCInst
&
Res
)
const
{
llvm_unreachable
(
"No relaxation implemented"
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> bool X86TargetLowering :: isLegalAddressingMode ( const AddrMode & AM , const Type * Ty ) const { CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; if ( ! X86 :: isOffsetSuitableForCodeModel ( AM . BaseOffs , M , AM . BaseGV != NULL ) ) return false ; if ( AM . BaseGV ) { unsigned GVFlags = Subtarget -> ClassifyGlobalReference ( AM . BaseGV , getTargetMachine ( ) ) ; if ( isGlobalStubReference ( GVFlags ) ) return false ; if ( AM . HasBaseReg && isGlobalRelativeToPICBase ( GVFlags ) ) return false ; if ( Subtarget -> is64Bit ( ) && ( AM . BaseOffs || AM . Scale > 1 ) ) return false ; } switch ( AM . Scale ) { case 0 : case 1 : case 2 : case 4 : case 8 : break ; case 3 : case 5 : case 9 : if ( AM . HasBaseReg ) return false ; break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> unsigned RISCVInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : { return get ( Opcode ) . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return 0 ; case RISCV :: PseudoCALL : case RISCV :: PseudoTAIL : case RISCV :: PseudoLLA : case RISCV :: PseudoLA : return 8 ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const auto & TM = static_cast < const RISCVTargetMachine & > ( MF . getTarget ( ) ) ; return getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .

RISCV RISCV 0 RISCV::PseudoCALL RISCV::PseudoTAIL RISCV::PseudoLLA RISCV::PseudoLA 8 RISCV 0


<s> bool IA64TargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createIA64DAGToDAGInstructionSelector ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static bool s390_function_arg_integer ( machine_mode mode , const_tree type ) { int size = s390_function_arg_size ( mode , type ) ; if ( size > 8 ) return false ; if ( ! type ) return GET_MODE_CLASS ( mode ) == MODE_INT || ( TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P ( mode ) ) ; if ( INTEGRAL_TYPE_P ( type ) || POINTER_TYPE_P ( type ) || TREE_CODE ( type ) == NULLPTR_TYPE || TREE_CODE ( type ) == OFFSET_TYPE || ( TARGET_SOFT_FLOAT && TREE_CODE ( type ) == REAL_TYPE ) ) return true ; if ( AGGREGATE_TYPE_P ( type ) && exact_log2 ( size ) >= 0 && ! s390_function_arg_float ( mode , type ) ) return true ; return false ; } </s>

Return true if a function argument of type TYPE and mode MODE is to be passed in an integer register , or a pair of integer registers , if available .


" (e.g. %<-mfloat-abi=softfp%> %<-mfpu=neon%>)"

Expand a Neon builtin , i.e . those registered only if TARGET_NEON holds . Most of these are `` special '' because they do n't have symbolic constants defined per-instruction or per instruction-variant . Instead , the required info is looked up in the table neon_builtin_data .


<s> static bool arm_fastmul_rtx_costs ( rtx x , int code , int outer_code , int * total ) { enum machine_mode mode = GET_MODE ( x ) ; if ( TARGET_THUMB ) { * total = thumb_rtx_costs ( x , code , outer_code ) ; return true ; } switch ( code ) { case MULT : if ( mode == DImode && ( GET_CODE ( XEXP ( x , 0 ) ) == GET_CODE ( XEXP ( x , 1 ) ) ) && ( GET_CODE ( XEXP ( x , 0 ) ) == ZERO_EXTEND || GET_CODE ( XEXP ( x , 0 ) ) == SIGN_EXTEND ) ) { * total = 8 ; return true ; } if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || mode == DImode ) { * total = 30 ; return true ; } if ( GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) { unsigned HOST_WIDE_INT i = ( INTVAL ( XEXP ( x , 1 ) ) & ( unsigned HOST_WIDE_INT ) 0xffffffff ) ; int cost , const_ok = const_ok_for_arm ( i ) ; int j , booth_unit_size ; cost = const_ok ? 4 : 8 ; booth_unit_size = 8 ; for ( j = 0 ; i && j < 32 ; j += booth_unit_size ) { i >>= booth_unit_size ; cost += 2 ; } * total = cost ; return true ; } * total = 8 + ( REG_OR_SUBREG_REG ( XEXP ( x , 0 ) ) ? 0 : 4 ) + ( REG_OR_SUBREG_REG ( XEXP ( x , 1 ) ) ? 0 : 4 ) ; return true ; default : * total = arm_rtx_costs_1 ( x , code , outer_code ) ; return true ; } } </s>

RTX cost for cores with a fast multiply unit ( M variants ) .


"parameter passing for argument of type "

Determine where to put an argument to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . On the ARM , normally the first 16 bytes are passed in registers r0-r3 ; all other arguments are passed on the stack . If ( NAMED == 0 ) ( which happens only in assign_parms , since TARGET_SETUP_INCOMING_VARARGS is defined ) , say it is passed in the stack ( function_prologue will indeed make it pass in the stack if necessary ) .


Destroys the object . Bogus destructor overriding base class destructor .


<s> bool HexagonGenPredicate :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getSubtarget < HexagonSubtarget > ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget < HexagonSubtarget > ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; PredGPRs . clear ( ) ; PUsers . clear ( ) ; G2P . clear ( ) ; bool Changed = false ; collectPredicateGPR ( MF ) ; for ( SetOfReg :: iterator I = PredGPRs . begin ( ) , E = PredGPRs . end ( ) ; I != E ; ++ I ) processPredicateGPR ( * I ) ; bool Again ; do { Again = false ; VectOfInst Processed , Copy ; typedef VectOfInst :: iterator iterator ; Copy = PUsers ; for ( iterator I = Copy . begin ( ) , E = Copy . end ( ) ; I != E ; ++ I ) { MachineInstr * MI = * I ; bool Done = convertToPredForm ( MI ) ; if ( Done ) { Processed . insert ( MI ) ; Again = true ; } } Changed |= Again ; auto Done = [ Processed ] ( MachineInstr * MI ) -> bool { return Processed . count ( MI ) ; } ; PUsers . remove_if ( Done ) ; } while ( Again ) ; Changed |= eliminatePredCopies ( MF ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool AArch64InstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Cond , unsigned TrueReg , unsigned FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; unsigned ExtraCondLat = Cond . size ( ) != 1 ; if ( AArch64 :: GPR64allRegClass . hasSubClassEq ( RC ) || AArch64 :: GPR32allRegClass . hasSubClassEq ( RC ) ) { CondCycles = 1 + ExtraCondLat ; TrueCycles = FalseCycles = 1 ; if ( canFoldIntoCSel ( MRI , TrueReg ) ) TrueCycles = 0 ; else if ( canFoldIntoCSel ( MRI , FalseReg ) ) FalseCycles = 0 ; return true ; } if ( AArch64 :: FPR64RegClass . hasSubClassEq ( RC ) || AArch64 :: FPR32RegClass . hasSubClassEq ( RC ) ) { CondCycles = 5 + ExtraCondLat ; TrueCycles = FalseCycles = 2 ; return true ; } return false ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


"MIPS16 PIC for ABIs other than o32 and o64"

"hard-float MIPS16 code for ABIs other than o32 and o64"

Set up the target-dependent global state for ISA mode COMPRESSION_MODE , which is either MASK_MIPS16 or MASK_MICROMIPS .


<s>
const
char
*
rs6000_insn_for_shift_mask
(
machine_mode
mode
,
rtx
*
operands
,
bool
dot
)
{
int
nb
,
ne
;
if
(
!
rs6000_is_valid_mask
(
operands
[
3
]
,
&
nb
,
&
ne
,
mode
)
)
gcc_unreachable
(
)
;
if
(
mode
==
DImode
&&
ne
==
0
)
{
if
(
GET_CODE
(
operands
[
4
]
)
==
LSHIFTRT
&&
INTVAL
(
operands
[
2
]
)
)
operands
[
2
]
=
GEN_INT
(
64
INTVAL
(
operands
[
2
]
)
)
;
operands
[
3
]
=
GEN_INT
(
63
nb
)
;
if
(
dot
)
return
"rld%I2cl. %0,%1,%2,%3"
;
return
"rld%I2cl %0,%1,%2,%3"
;
}
if
(
mode
==
DImode
&&
nb
==
63
)
{
operands
[
3
]
=
GEN_INT
(
63
ne
)
;
if
(
dot
)
return
"rld%I2cr. %0,%1,%2,%3"
;
return
"rld%I2cr %0,%1,%2,%3"
;
}
if
(
mode
==
DImode
&&
GET_CODE
(
operands
[
4
]
)
!=
LSHIFTRT
&&
CONST_INT_P
(
operands
[
2
]
)
&&
ne
==
INTVAL
(
operands
[
2
]
)
)
{
operands
[
3
]
=
GEN_INT
(
63
nb
)
;
if
(
dot
)
return
"rld%I2c. %0,%1,%2,%3"
;
return
"rld%I2c %0,%1,%2,%3"
;
}
if
(
nb
<
32
&&
ne
<
32
)
{
if
(
GET_CODE
(
operands
[
4
]
)
==
LSHIFTRT
&&
INTVAL
(
operands
[
2
]
)
)
operands
[
2
]
=
GEN_INT
(
32
INTVAL
(
operands
[
2
]
)
)
;
operands
[
3
]
=
GEN_INT
(
31
nb
)
;
operands
[
4
]
=
GEN_INT
(
31
ne
)
;
if
(
dot
)
return
"rlw%I2nm. %0,%1,%h2,%3,%4"
;
return
"rlw%I2nm %0,%1,%h2,%3,%4"
;
}
gcc_unreachable
(
)
;
}
</s>

Return the instruction template for a shift with mask in mode MODE , with operands OPERANDS . If DOT is true , make it a record-form instruction .


"PTX does not support weak declarations"

Implement TARGET_ASM_ASSEMBLE_UNDEFINED_DECL . Write an extern declaration only for variable DECL with NAME to FILE .


<s> virtual const BPFInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s>
unsigned
getReg
(
)
const
override
{
assert
(
Kind
==
Register
&&
"Invalid type access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s>
void
X86InstrInfo
::
insertSelect
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
Register
DstReg
,
ArrayRef
<
MachineOperand
>
Cond
,
Register
TrueReg
,
Register
FalseReg
)
const
{
MachineRegisterInfo
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
const
TargetRegisterInfo
&
TRI
=
*
MRI
.
getTargetRegisterInfo
(
)
;
const
TargetRegisterClass
&
RC
=
*
MRI
.
getRegClass
(
DstReg
)
;
assert
(
Cond
.
size
(
)
==
1
&&
"Invalid Cond array"
)
;
unsigned
Opc
=
X86
::
getCMovOpcode
(
TRI
.
getRegSizeInBits
(
RC
)
/
8
,
false
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DstReg
)
.
addReg
(
FalseReg
)
.
addReg
(
TrueReg
)
.
addImm
(
Cond
[
0
]
.
getImm
(
)
)
;
}
</s>

Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true , and FalseReg to DstReg when Cond is false .


"256-bit vector operations only available in AVX2"

Change the opcode of MI to execute in Domain .


"insertBranch must not be told to insert a fallthrough"

"Unconditional branch with multiple successors!"

"Lanai branch conditions should have one component."

Insert branch code into the end of the specified MachineBasicBlock .


<s> static void moxie_compute_frame ( void ) { int stack_alignment = STACK_BOUNDARY / BITS_PER_UNIT ; int padding_locals ; int regno ; cfun -> machine -> local_vars_size = get_frame_size ( ) ; padding_locals = cfun -> machine -> local_vars_size % stack_alignment ; if ( padding_locals ) padding_locals = stack_alignment - padding_locals ; cfun -> machine -> local_vars_size += padding_locals ; cfun -> machine -> callee_saved_reg_size = 0 ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ( ! call_used_or_fixed_reg_p ( regno ) ) ) cfun -> machine -> callee_saved_reg_size += 4 ; cfun -> machine -> size_for_adjusting_sp = crtl -> args . pretend_args_size + cfun -> machine -> local_vars_size + ( ACCUMULATE_OUTGOING_ARGS ? ( HOST_WIDE_INT ) crtl -> outgoing_args_size : 0 ) ; } </s>

Compute the size of the local area and the size to be adjusted by the * prologue and epilogue .


"Block %d(%d), parent (%d), orientation %+d\n"

DFS walk creating SESE data structures . Only cover nodes with BB_VISITED set . Append discovered blocks to LIST . We number in increments of 3 so that the above and below pseudo nodes can be implicitly numbered too .


<s> int fp_one_operand ( rtx op ) { REAL_VALUE_TYPE r ; if ( GET_MODE ( op ) != SFmode ) return 0 ; REAL_VALUE_FROM_CONST_DOUBLE ( r , op ) ; return REAL_VALUES_EQUAL ( r , dconst1 ) ; } </s>

Nonzero if OP is a floating point value with value 1.0 .


<s>
MachineBasicBlock
::
iterator
ARCFrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
LLVM_DEBUG
(
dbgs
(
)
<<
"EmitCallFramePseudo: "
<<
MF
.
getName
(
)
<<
"\n"
)
;
const
ARCInstrInfo
*
TII
=
MF
.
getSubtarget
<
ARCSubtarget
>
(
)
.
getInstrInfo
(
)
;
MachineInstr
&
Old
=
*
I
;
DebugLoc
dl
=
Old
.
getDebugLoc
(
)
;
unsigned
Amt
=
Old
.
getOperand
(
0
)
.
getImm
(
)
;
auto
*
AFI
=
MF
.
getInfo
<
ARCFunctionInfo
>
(
)
;
if
(
!
hasFP
(
MF
)
)
{
if
(
Amt
>
AFI
->
MaxCallStackReq
&&
Old
.
getOpcode
(
)
==
ARC
::
ADJCALLSTACKDOWN
)
AFI
->
MaxCallStackReq
=
Amt
;
}
else
{
if
(
Amt
!=
0
)
{
assert
(
(
Old
.
getOpcode
(
)
==
ARC
::
ADJCALLSTACKDOWN
||
Old
.
getOpcode
(
)
==
ARC
::
ADJCALLSTACKUP
)
&&
"Unknown Frame Pseudo."
)
;
bool
IsAdd
=
(
Old
.
getOpcode
(
)
==
ARC
::
ADJCALLSTACKUP
)
;
emitRegUpdate
(
MBB
,
I
,
dl
,
ARC
::
SP
,
Amt
,
IsAdd
,
TII
)
;
}
}
return
MBB
.
erase
(
I
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

ARC
ARC
"EmitCallFramePseudo: "
"\n"
ARC
ARC
0
ARC
ARC::ADJCALLSTACKDOWN
0
ARC::ADJCALLSTACKDOWN
ARC::ADJCALLSTACKUP
"Unknown Frame Pseudo."
ARC::ADJCALLSTACKUP
ARC::SP


<s> ValueType MetadataStreamer :: getValueType ( Type * Ty , StringRef TypeName ) const { switch ( Ty -> getTypeID ( ) ) { case Type :: IntegerTyID : { auto Signed = ! TypeName . startswith ( "u" ) ; switch ( Ty -> getIntegerBitWidth ( ) ) { case 8 : return Signed ? ValueType :: I8 : ValueType :: U8 ; case 16 : return Signed ? ValueType :: I16 : ValueType :: U16 ; case 32 : return Signed ? ValueType :: I32 : ValueType :: U32 ; case 64 : return Signed ? ValueType :: I64 : ValueType :: U64 ; default : return ValueType :: Struct ; } } case Type :: HalfTyID : return ValueType :: F16 ; case Type :: FloatTyID : return ValueType :: F32 ; case Type :: DoubleTyID : return ValueType :: F64 ; case Type :: PointerTyID : return getValueType ( Ty -> getPointerElementType ( ) , TypeName ) ; case Type :: VectorTyID : return getValueType ( Ty -> getVectorElementType ( ) , TypeName ) ; default : return ValueType :: Struct ; } } </s>

Return the ValueType of the referenced return value .


";;\t\tBACKEND: move insn %d to the top of list\n"

";;\t\tBACKEND: best insn %d already on top\n"

"ready list ooo attributes - sched state: %d\n"

This function is called via hook TARGET_SCHED_REORDER before issuing one insn from list READY which contains * NREADYP entries . For target z10 it reorders load instructions to avoid early load conflicts in the floating point pipeline


<s> static unsigned loongarch_pass_mode_in_fpr_p ( machine_mode mode ) { if ( GET_MODE_UNIT_SIZE ( mode ) <= UNITS_PER_FP_ARG ) { if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return 1 ; if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) return 2 ; } return 0 ; } </s>

If MODE represents an argument that can be passed or returned in floating-point registers , return the number of registers , else 0 .


<s> unsigned getOperandsScalarizationOverhead ( ArrayRef < const Value * > Args , unsigned VF ) { return 0 ; } </s>

Estimate the overhead of scalarizing an instructions unique non-constant operands .


<s> bool R600InstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumTCycles , unsigned ExtraTCycles , MachineBasicBlock & FMBB , unsigned NumFCycles , unsigned ExtraFCycles , const BranchProbability & Probability ) const { return true ; } </s>


"Wasn't expecting to be able to lower this!"

LowerOperation - Provide custom lowering hooks for some operations .


<s>
bool
ARMAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNum
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
{
if
(
ExtraCode
[
1
]
!=
0
)
return
true
;
switch
(
ExtraCode
[
0
]
)
{
case
'A'
:
default
:
return
true
;
case
'm'
:
if
(
!
MI
->
getOperand
(
OpNum
)
.
isReg
(
)
)
return
true
;
O
<<
ARMInstPrinter
::
getRegisterName
(
MI
->
getOperand
(
OpNum
)
.
getReg
(
)
)
;
return
false
;
}
}
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNum
)
;
assert
(
MO
.
isReg
(
)
&&
"unexpected inline asm memory operand"
)
;
O
<<
"["
<<
ARMInstPrinter
::
getRegisterName
(
MO
.
getReg
(
)
)
<<
"]"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> void X86FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MF . setHasWinCFI ( false ) ; const Function & F = MF . getFunction ( ) ; if ( ! STI . is64Bit ( ) || ! MF . hasEHFunclets ( ) || classifyEHPersonality ( F . getPersonalityFn ( ) ) != EHPersonality :: MSVC_CXX ) return ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; WinEHFuncInfo & EHInfo = * MF . getWinEHFuncInfo ( ) ; int64_t MinFixedObjOffset = - SlotSize ; for ( int I = MFI . getObjectIndexBegin ( ) ; I < 0 ; ++ I ) MinFixedObjOffset = std :: min ( MinFixedObjOffset , MFI . getObjectOffset ( I ) ) ; for ( WinEHTryBlockMapEntry & TBME : EHInfo . TryBlockMap ) { for ( WinEHHandlerType & H : TBME . HandlerArray ) { int FrameIndex = H . CatchObj . FrameIndex ; if ( FrameIndex != INT_MAX ) { unsigned Align = MFI . getObjectAlignment ( FrameIndex ) ; MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % Align ; MinFixedObjOffset -= MFI . getObjectSize ( FrameIndex ) ; MFI . setObjectOffset ( FrameIndex , MinFixedObjOffset ) ; } } } MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % 8 ; int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize ; int UnwindHelpFI = MFI . CreateFixedObject ( SlotSize , UnwindHelpOffset , false ) ; EHInfo . UnwindHelpFrameIdx = UnwindHelpFI ; MachineBasicBlock & MBB = MF . front ( ) ; auto MBBI = MBB . begin ( ) ; while ( MBBI != MBB . end ( ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) ) ++ MBBI ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; addFrameReference ( BuildMI ( MBB , MBBI , DL , TII . get ( X86 :: MOV64mi32 ) ) , UnwindHelpFI ) . addImm ( - 2 ) ; } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> void HexagonTargetLowering :: LowerOperationWrapper ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { if ( isHvxOperation ( N , DAG ) ) { LowerHvxOperationWrapper ( N , Results , DAG ) ; if ( ! Results . empty ( ) ) return ; } if ( N -> getOpcode ( ) != ISD :: STORE ) return TargetLowering :: LowerOperationWrapper ( N , Results , DAG ) ; } </s>

This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types .


<s> const NVPTXRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createX86MachObjectWriter ( OS , true , MachO :: CPU_TYPE_X86_64 , MachO :: CPU_SUBTYPE_X86_64_ALL ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> bool KudeyarDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { bool Ret = SelectionDAGISel :: runOnMachineFunction ( MF ) ; return Ret ; } </s>

runOnMachineFunction - Emit the function body .


<s> void neon_expand_vector_init ( rtx target , rtx vals ) { machine_mode mode = GET_MODE ( target ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; int n_elts = GET_MODE_NUNITS ( mode ) ; int n_var = 0 , one_var = - 1 ; bool all_same = true ; rtx x , mem ; int i ; for ( i = 0 ; i < n_elts ; ++ i ) { x = XVECEXP ( vals , 0 , i ) ; if ( ! CONSTANT_P ( x ) ) ++ n_var , one_var = i ; if ( i > 0 && ! rtx_equal_p ( x , XVECEXP ( vals , 0 , 0 ) ) ) all_same = false ; } if ( n_var == 0 ) { rtx constant = neon_make_constant ( vals ) ; if ( constant != NULL_RTX ) { emit_move_insn ( target , constant ) ; return ; } } if ( all_same && GET_MODE_SIZE ( inner_mode ) <= 4 ) { x = copy_to_mode_reg ( inner_mode , XVECEXP ( vals , 0 , 0 ) ) ; emit_insn ( gen_rtx_SET ( target , gen_vec_duplicate ( mode , x ) ) ) ; return ; } if ( n_var == 1 ) { rtx copy = copy_rtx ( vals ) ; rtx merge_mask = GEN_INT ( 1 << one_var ) ; XVECEXP ( copy , 0 , one_var ) = XVECEXP ( vals , 0 , ( one_var + 1 ) % n_elts ) ; neon_expand_vector_init ( target , copy ) ; x = copy_to_mode_reg ( inner_mode , XVECEXP ( vals , 0 , one_var ) ) ; emit_insn ( gen_vec_set_internal ( mode , target , x , merge_mask , target ) ) ; return ; } mem = assign_stack_temp ( mode , GET_MODE_SIZE ( mode ) ) ; for ( i = 0 ; i < n_elts ; i ++ ) emit_move_insn ( adjust_address_nv ( mem , inner_mode , i * GET_MODE_SIZE ( inner_mode ) ) , XVECEXP ( vals , 0 , i ) ) ; emit_move_insn ( target , mem ) ; } </s>


<s> const SICTargetMachine & getTargetMachine ( ) { return static_cast < const SICTargetMachine & > ( TM ) ; } </s>

Return the target machine ( if available ) .


"SPUTargetLowering::ReplaceNodeResults(): need to fix this!\n"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> void ARCompactInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned int DestReg , unsigned int SrcReg , bool KillSrc ) const { BuildMI ( MBB , I , DL , get ( ARC :: MOVrr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } </s>


<s>
bool
FixupLEAPass
::
runOnMachineFunction
(
MachineFunction
&
Func
)
{
MF
=
&
Func
;
TM
=
&
MF
->
getTarget
(
)
;
TII
=
TM
->
getInstrInfo
(
)
;
DEBUG
(
dbgs
(
)
<<
"Start X86FixupLEAs\n"
;
)
;
for
(
MachineFunction
::
iterator
I
=
Func
.
begin
(
)
,
E
=
Func
.
end
(
)
;
I
!=
E
;
++
I
)
processBasicBlock
(
Func
,
I
)
;
DEBUG
(
dbgs
(
)
<<
"End X86FixupLEAs\n"
;
)
;
return
true
;
}
</s>

X86
"Start X86FixupLEAs\n"
"End X86FixupLEAs\n"


"FPDelta isn't aligned per the Win64 ABI!"

"VLAs and dynamic stack realign, but no FP?!"

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> unsigned SPUInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case SPU :: LQDv16i8 : case SPU :: LQDv8i16 : case SPU :: LQDv4i32 : case SPU :: LQDv4f32 : case SPU :: LQDv2f64 : case SPU :: LQDr128 : case SPU :: LQDr64 : case SPU :: LQDr32 : case SPU :: LQDr16 : { const MachineOperand MOp1 = MI -> getOperand ( 1 ) ; const MachineOperand MOp2 = MI -> getOperand ( 2 ) ; if ( MOp1 . isImm ( ) && MOp2 . isFI ( ) ) { FrameIndex = MOp2 . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { const LanaiSubtarget & Subtarget = MF . getSubtarget < LanaiSubtarget > ( ) ; TII = Subtarget . getInstrInfo ( ) ; TRI = Subtarget . getRegisterInfo ( ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) Changed |= runOnMachineBasicBlock ( MBB ) ; return Changed ; } </s>


<s> static void mark_reg_gr_used_mask ( rtx reg , void * data ATTRIBUTE_UNUSED ) { unsigned int regno = REGNO ( reg ) ; if ( regno < 32 ) { unsigned int i , n = REG_NREGS ( reg ) ; for ( i = 0 ; i < n ; ++ i ) current_frame_info . gr_used_mask |= 1 << ( regno + i ) ; } } </s>

Helper function for ia64_compute_frame_size , called through diddle_return_value . Mark REG in current_frame_info.gr_used_mask .


<s> static void record_memory_reference ( rtx_insn * insn ) { enum attr_itanium_class insn_class = ia64_safe_itanium_class ( insn ) ; switch ( insn_class ) { case ITANIUM_CLASS_FLD : case ITANIUM_CLASS_LD : mem_ops_in_group [ current_cycle % 4 ] ++ ; break ; case ITANIUM_CLASS_STF : case ITANIUM_CLASS_ST : mem_ops_in_group [ ( current_cycle + 3 ) % 4 ] ++ ; break ; default : ; } } </s>

If INSN is a memory reference , memoize it in MEM_OPS_IN_GROUP global array ( taking account for 3-cycle cache reference postponing for stores : Intel Itanium 2 Reference Manual for Software Development and Optimization , 6.7.3.1 ) .


<s> unsigned MCS51InstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { if ( BytesRemoved ) * BytesRemoved = 0 ; MachineBasicBlock :: iterator I = MBB . end ( ) ; unsigned Count = 0 ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugInstr ( ) ) { continue ; } if ( I -> getOpcode ( ) != MCS51 :: RJMPk && getCondFromBranchOpc ( I -> getOpcode ( ) ) == MCS51CC :: COND_INVALID ) { break ; } if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++ Count ; } return Count ; } </s>

Remove the branching code at the end of the specific MBB .


<s> bool MipsSEFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * EntryBlock = MF -> begin ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == Mips :: RA || Reg == Mips :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> virtual const TargetFrameInfo * getFrameInfo ( ) const { return & FrameInfo ; } </s>

getFrameInfo - Return the frame info object for the current function .


<s> static char * construct_fntype_id ( prototype * protoptr ) { int len = protoptr -> nargs ? ( protoptr -> nargs + 1 ) * 9 + 6 : 17 ; char * buf = ( char * ) malloc ( len ) ; int bufi = 0 ; if ( protoptr -> rettype . ispointer ) buf [ bufi ++ ] = 'p' ; if ( protoptr -> rettype . isvoid ) buf [ bufi ++ ] = 'v' ; else { if ( protoptr -> rettype . isunsigned ) buf [ bufi ++ ] = 'u' ; if ( protoptr -> rettype . isvector ) complete_vector_type ( & protoptr -> rettype , buf , & bufi ) ; else complete_base_type ( & protoptr -> rettype , buf , & bufi ) ; } memcpy ( & buf [ bufi ] , "_ftype" , 6 ) ; bufi += 6 ; if ( ! protoptr -> nargs ) { memcpy ( & buf [ bufi ] , "_v" , 2 ) ; bufi += 2 ; } else { typelist * argptr = protoptr -> args ; for ( int i = 0 ; i < protoptr -> nargs ; i ++ , argptr = argptr -> next ) { assert ( argptr ) ; buf [ bufi ++ ] = '_' ; if ( argptr -> info . isconst && argptr -> info . base == BT_INT && ! argptr -> info . ispointer ) { buf [ bufi ++ ] = 'c' ; buf [ bufi ++ ] = 'i' ; continue ; } if ( argptr -> info . ispointer ) { if ( argptr -> info . isvoid ) { if ( argptr -> info . isconst ) { memcpy ( & buf [ bufi ] , "pcvoid" , 6 ) ; bufi += 6 ; continue ; } else { buf [ bufi ++ ] = 'p' ; buf [ bufi ++ ] = 'v' ; continue ; } } else buf [ bufi ++ ] = 'p' ; } if ( argptr -> info . isunsigned ) buf [ bufi ++ ] = 'u' ; if ( argptr -> info . isvector ) complete_vector_type ( & argptr -> info , buf , & bufi ) ; else complete_base_type ( & argptr -> info , buf , & bufi ) ; } assert ( ! argptr ) ; } buf [ bufi ] = '\0' ; rbt_insert ( & fntype_rbt , buf ) ; return buf ; } </s>

Build a function type descriptor identifier from the return type and argument types described by PROTOPTR , and store it if it does not already exist . Return the identifier .


<s> bool Z80AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNo ) ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , O ) ; case 'X' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << "$" << std :: hex << MO . getImm ( ) ; return false ; case 'x' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << "$" << std :: hex << ( MO . getImm ( ) & 0xffff ) ; return false ; case 'd' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) ; return false ; case 'm' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) - 1 ; return false ; case 'z' : { if ( MO . getType ( ) != MachineOperand :: MO_Immediate ) return true ; int64_t val = MO . getImm ( ) ; if ( val ) { O << val ; } else { O << "$0" ; } return false ; } } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> void VideocoreRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned int FIOperandNo , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNo ) . getIndex ( ) ; MI . getOperand ( FIOperandNo ) . ChangeToRegister ( VC :: SP , false ) ; int OffsetOperandNo = FIOperandNo + 1 ; int Offset = MFI -> getObjectOffset ( FrameIndex ) ; Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .

Videocore Videocore 0 "Unexpected" VC::SP 1


<s> tree builtin_decl ( unsigned int code , bool ) { if ( code >= vec_safe_length ( registered_functions ) ) return error_mark_node ; return ( * registered_functions ) [ code ] -> decl ; } </s>

Return the function decl with RVV function subcode CODE , or error_mark_node if no such function exists .


<s> static void push_regs ( HARD_REG_SET * mask , int interrupt_handler ) { int i ; int skip_fpscr = 0 ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { if ( i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD && hard_regs_intersect_p ( mask , & reg_class_contents [ DF_REGS ] ) ) { HARD_REG_SET unsaved ; push ( FPSCR_REG ) ; COMPL_HARD_REG_SET ( unsaved , * mask ) ; fpscr_set_from_mem ( NORMAL_MODE ( FP_MODE ) , unsaved ) ; skip_fpscr = 1 ; } if ( i != PR_REG && ( i != FPSCR_REG || ! skip_fpscr ) && TEST_HARD_REG_BIT ( * mask , i ) ) push ( i ) ; } if ( TEST_HARD_REG_BIT ( * mask , PR_REG ) ) push ( PR_REG ) ; } </s>

Generate code to push the regs specified in the mask . remember that the mask is of the internal shape of the regs , not the external shape - so go through the renumber vector


<s> static bool pru_valid_const_ubyte_offset ( machine_mode mode , HOST_WIDE_INT offset ) { bool valid = UBYTE_INT ( offset ) ; if ( valid && GET_MODE_SIZE ( mode ) > GET_MODE_SIZE ( SImode ) ) valid = UBYTE_INT ( offset + GET_MODE_SIZE ( mode ) - 1 ) ; return valid ; } </s>

Return true if given xbbo constant OFFSET is valid .


<s> OpRef HvxSelector :: concat ( OpRef Lo , OpRef Hi , ResultStack & Results ) { DEBUG_WITH_TYPE ( "isel" , { dbgs ( ) << __func__ << '\n' ; } ) ; const SDLoc & dl ( Results . InpNode ) ; Results . push ( TargetOpcode :: REG_SEQUENCE , getPairVT ( MVT :: i8 ) , { DAG . getTargetConstant ( Hexagon :: HvxWRRegClassID , dl , MVT :: i32 ) , Lo , DAG . getTargetConstant ( Hexagon :: vsub_lo , dl , MVT :: i32 ) , Hi , DAG . getTargetConstant ( Hexagon :: vsub_hi , dl , MVT :: i32 ) , } ) ; return OpRef :: res ( Results . top ( ) ) ; } </s>

Concatenate the bits from Lo onto the bottom of * this .


<s> bool HexagonFixupHwLoops :: runOnMachineFunction ( MachineFunction & MF ) { return fixupLoopInstrs ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s>
bool
X86DAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
SDValue
Op0
,
Op1
,
Op2
,
Op3
,
Op4
;
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
LLVM_FALLTHROUGH
;
case
InlineAsm
::
Constraint_o
:
case
InlineAsm
::
Constraint_v
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_X
:
if
(
!
selectAddr
(
nullptr
,
Op
,
Op0
,
Op1
,
Op2
,
Op3
,
Op4
)
)
return
true
;
break
;
}
OutOps
.
push_back
(
Op0
)
;
OutOps
.
push_back
(
Op1
)
;
OutOps
.
push_back
(
Op2
)
;
OutOps
.
push_back
(
Op3
)
;
OutOps
.
push_back
(
Op4
)
;
return
false
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < TargetPassConfig > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> virtual const InstrItineraryData * getInstrItineraryData ( ) const { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> poly_int64 h8300_push_rounding ( poly_int64 bytes ) { return ( ( bytes + PARM_BOUNDARY / 8 - 1 ) & ( - PARM_BOUNDARY / 8 ) ) ; } </s>

Implement PUSH_ROUNDING . On the H8/300 , @ -sp really pushes a byte if you ask it to - but that 's dangerous , so we claim that it always pushes a word , then we catch the mov.b rx , @ -sp and turn it into a mov.w rx , @ -sp on output . On the H8/300H , we simplify TARGET_QUICKCALL by setting this to 4 and doing a similar thing .


<s> static void expand_interrupt_handler_epilogue ( rtx spreg , e_funkind fkind , bool all ) { tree attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ; rtx postinc1 = gen_rtx_POST_INC ( SImode , spreg ) ; rtx postinc = gen_rtx_MEM ( SImode , postinc1 ) ; MEM_VOLATILE_P ( postinc ) = 1 ; do_unlink ( spreg , get_frame_size ( ) , all , 1 ) ; if ( lookup_attribute ( "nesting" , attrs ) ) { rtx srcreg = gen_rtx_REG ( Pmode , ret_regs [ fkind ] ) ; emit_move_insn ( srcreg , postinc ) ; } if ( ! crtl -> is_leaf ) all = true ; expand_epilogue_reg_restore ( spreg , all , true ) ; if ( fkind == EXCPT_HANDLER ) emit_insn ( gen_addsi3 ( spreg , spreg , GEN_INT ( 12 ) ) ) ; emit_jump_insn ( gen_return_internal ( gen_rtx_REG ( Pmode , ret_regs [ fkind ] ) ) ) ; } </s>

Generate an epilogue suitable for a function of kind FKIND . This is called for interrupt and exception handler epilogues . SPREG contains ( reg : SI REG_SP ) .


<s> static int sparc_arg_partial_bytes ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , bool named ) { int slotno , regno , padding ; slotno = function_arg_slotno ( cum , mode , type , named , 0 , & regno , & padding ) ; if ( slotno == - 1 ) return 0 ; if ( TARGET_ARCH32 ) { if ( ( slotno + ( mode == BLKmode ? ROUND_ADVANCE ( int_size_in_bytes ( type ) ) : ROUND_ADVANCE ( GET_MODE_SIZE ( mode ) ) ) ) > SPARC_INT_ARG_MAX ) return ( SPARC_INT_ARG_MAX - slotno ) * UNITS_PER_WORD ; } else { if ( type && AGGREGATE_TYPE_P ( type ) ) { int size = int_size_in_bytes ( type ) ; if ( size > UNITS_PER_WORD && slotno == SPARC_INT_ARG_MAX - 1 ) return UNITS_PER_WORD ; } else if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_INT || ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT && ! ( TARGET_FPU && named ) ) ) { if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && slotno == SPARC_INT_ARG_MAX - 1 ) return UNITS_PER_WORD ; } else if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) { if ( ( slotno + GET_MODE_SIZE ( mode ) / UNITS_PER_WORD ) > SPARC_FP_ARG_MAX ) return UNITS_PER_WORD ; } } return 0 ; } </s>

For an arg passed partly in registers and partly in memory , this is the number of bytes of registers used . For args passed entirely in registers or entirely in memory , zero . Any arg that starts in the first 6 regs but wo n't entirely fit in them needs partial registers on v8 . On v9 , structures with integer values in arg slots 5,6 will be passed in % o5 and SP+176 , and complex fp values that begin in the last fp reg [ where `` last fp reg '' varies with the mode ] will be split between that reg and memory .


<s> bool loongarch_can_use_return_insn ( void ) { return reload_completed && cfun -> machine -> frame . total_size == 0 ; } </s>

Return nonzero if this function is known to have a null epilogue . This allows the optimizer to omit jumps to jumps if no stack was created .


<s> bool AArch64FrameLowering :: canUseRedZone ( const MachineFunction & MF ) const { if ( ! EnableRedZone ) return false ; const AArch64Subtarget & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; const unsigned RedZoneSize = Subtarget . getTargetLowering ( ) -> getRedZoneSize ( MF . getFunction ( ) ) ; if ( ! RedZoneSize ) return false ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const AArch64FunctionInfo * AFI = MF . getInfo < AArch64FunctionInfo > ( ) ; uint64_t NumBytes = AFI -> getLocalStackSize ( ) ; return ! ( MFI . hasCalls ( ) || hasFP ( MF ) || NumBytes > RedZoneSize || getSVEStackSize ( MF ) ) ; } </s>

Can this function use the red zone for local allocations .


<s> bool HexagonTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { LSBaseSDNode * LSN = dyn_cast < LSBaseSDNode > ( N ) ; if ( ! LSN ) return false ; EVT VT = LSN -> getMemoryVT ( ) ; if ( ! VT . isSimple ( ) ) return false ; bool IsLegalType = VT == MVT :: i8 || VT == MVT :: i16 || VT == MVT :: i32 || VT == MVT :: i64 || VT == MVT :: v2i16 || VT == MVT :: v2i32 || VT == MVT :: v4i8 || VT == MVT :: v4i16 || VT == MVT :: v8i8 || Subtarget . isHVXVectorType ( VT . getSimpleVT ( ) ) ; if ( ! IsLegalType ) return false ; if ( Op -> getOpcode ( ) != ISD :: ADD ) return false ; Base = Op -> getOperand ( 0 ) ; Offset = Op -> getOperand ( 1 ) ; if ( ! isa < ConstantSDNode > ( Offset . getNode ( ) ) ) return false ; AM = ISD :: POST_INC ; int32_t V = cast < ConstantSDNode > ( Offset . getNode ( ) ) -> getSExtValue ( ) ; return Subtarget . getInstrInfo ( ) -> isValidAutoIncImm ( VT , V ) ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .


<s> bool useAA ( ) const override { return IsCheri ; } </s>

Enable use of alias analysis during code generation ( during MI scheduling , DAGCombine , etc . ) .


<s> int m32c_class_max_nregs ( int regclass , enum machine_mode mode ) { int rn , max = 0 ; for ( rn = 0 ; rn < FIRST_PSEUDO_REGISTER ; rn ++ ) if ( class_contents [ regclass ] [ 0 ] & ( 1 << rn ) ) { int n = m32c_hard_regno_nregs ( rn , mode ) ; if ( max < n ) max = n ; } return max ; } </s>

Implements CLASS_MAX_NREGS . We calculate this according to its documented meaning , to avoid potential inconsistencies with actual class definitions .


<s> bool VERegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; if ( getFrameLowering ( MF ) -> hasReservedCallFrame ( MF ) ) return true ; return false ; } </s>

True if the stack can be realigned for the target .


<s>
void
neon_lane_bounds
(
rtx
operand
,
HOST_WIDE_INT
low
,
HOST_WIDE_INT
high
)
{
bounds_check
(
operand
,
low
,
high
,
"lane out of range"
)
;
}
</s>


<s> TargetLoweringBase :: LegalizeTypeAction SITargetLowering :: getPreferredVectorAction ( MVT VT ) const { int NumElts = VT . getVectorNumElements ( ) ; if ( NumElts != 1 && VT . getScalarType ( ) . bitsLE ( MVT :: i16 ) ) return VT . isPow2VectorType ( ) ? TypeSplitVector : TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s> TargetTransformInfo X86TargetMachine :: getTargetTransformInfo ( const Function & F ) { return TargetTransformInfo ( X86TTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


"section of %q+D conflicts with previous declaration"

Handle a `` l2 '' attribute ; arguments as in struct attribute_spec.handler .


<s> bool X86AsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == ".word" ) return ParseDirectiveWord ( 2 , DirectiveID . getLoc ( ) ) ; else if ( IDVal . startswith ( ".code" ) ) return ParseDirectiveCode ( IDVal , DirectiveID . getLoc ( ) ) ; else if ( IDVal . startswith ( ".att_syntax" ) ) { getParser ( ) . setAssemblerDialect ( 0 ) ; return false ; } else if ( IDVal . startswith ( ".intel_syntax" ) ) { getParser ( ) . setAssemblerDialect ( 1 ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( Parser . getTok ( ) . getString ( ) == "noprefix" ) Parser . Lex ( ) ; } return false ; } return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s>
virtual
ScheduleHazardRecognizer
*
CreateTargetHazardRecognizer
(
)
{
const
TargetInstrInfo
*
II
=
TM
.
getInstrInfo
(
)
;
assert
(
II
&&
"No InstrInfo?"
)
;
return
new
SPUHazardRecognizer
(
*
II
)
;
}
</s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .


<s>
bool
ARM64InstrInfo
::
isGPRCopy
(
const
MachineInstr
*
MI
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
TargetOpcode
::
COPY
:
{
unsigned
DstReg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
return
(
ARM64
::
GPR32RegClass
.
contains
(
DstReg
)
||
ARM64
::
GPR64RegClass
.
contains
(
DstReg
)
)
;
}
case
ARM64
::
ORRXrs
:
if
(
MI
->
getOperand
(
1
)
.
getReg
(
)
==
ARM64
::
XZR
)
{
assert
(
MI
->
getDesc
(
)
.
getNumOperands
(
)
==
4
&&
MI
->
getOperand
(
3
)
.
getImm
(
)
==
0
&&
"invalid ORRrs operands"
)
;
return
true
;
}
case
ARM64
::
ADDXri
:
if
(
MI
->
getOperand
(
2
)
.
getImm
(
)
==
0
)
{
assert
(
MI
->
getDesc
(
)
.
getNumOperands
(
)
==
4
&&
MI
->
getOperand
(
3
)
.
getImm
(
)
==
0
&&
"invalid ADDXri operands"
)
;
return
true
;
}
}
return
false
;
}
</s>

Does this instruction rename a GPR without modifying bits ?


<s> static int branch_dest ( rtx branch ) { rtx dest = SET_SRC ( PATTERN ( branch ) ) ; if ( GET_CODE ( dest ) == IF_THEN_ELSE ) dest = XEXP ( dest , 1 ) ; return INSN_ADDRESSES ( INSN_UID ( XEXP ( dest , 0 ) ) ) ; } </s>

Return the destination address of BRANCH . We need to use this instead of get_attr_length , because the cbranch_with_nops pattern conservatively sets its length to 6 , and we still prefer to use shorter sequences .


<s>
void
AArch64AppleInstPrinter
::
printInst
(
const
MCInst
*
MI
,
uint64_t
Address
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
,
raw_ostream
&
O
)
{
unsigned
Opcode
=
MI
->
getOpcode
(
)
;
StringRef
Layout
;
bool
IsTbx
;
if
(
isTblTbxInstruction
(
MI
->
getOpcode
(
)
,
Layout
,
IsTbx
)
)
{
O
<<
"\t"
<<
(
IsTbx
"tbx"
:
"tbl"
)
<<
Layout
<<
'\t'
<<
getRegisterName
(
MI
->
getOperand
(
0
)
.
getReg
(
)
,
AArch64
::
vreg
)
<<
", "
;
unsigned
ListOpNum
=
IsTbx
2
:
1
;
printVectorList
(
MI
,
ListOpNum
,
STI
,
O
,
""
)
;
O
<<
", "
<<
getRegisterName
(
MI
->
getOperand
(
ListOpNum
+
1
)
.
getReg
(
)
,
AArch64
::
vreg
)
;
printAnnotation
(
O
,
Annot
)
;
return
;
}
if
(
const
LdStNInstrDesc
*
LdStDesc
=
getLdStNInstrDesc
(
Opcode
)
)
{
O
<<
"\t"
<<
LdStDesc
->
Mnemonic
<<
LdStDesc
->
Layout
<<
'\t'
;
int
OpNum
=
LdStDesc
->
ListOperand
;
printVectorList
(
MI
,
OpNum
++
,
STI
,
O
,
""
)
;
if
(
LdStDesc
->
HasLane
)
O
<<
'['
<<
MI
->
getOperand
(
OpNum
++
)
.
getImm
(
)
<<
']'
;
unsigned
AddrReg
=
MI
->
getOperand
(
OpNum
++
)
.
getReg
(
)
;
O
<<
", ["
<<
getRegisterName
(
AddrReg
)
<<
']'
;
if
(
LdStDesc
->
NaturalOffset
!=
0
)
{
unsigned
Reg
=
MI
->
getOperand
(
OpNum
++
)
.
getReg
(
)
;
if
(
Reg
!=
AArch64
::
XZR
)
O
<<
", "
<<
getRegisterName
(
Reg
)
;
else
{
assert
(
LdStDesc
->
NaturalOffset
&&
"no offset on post-inc instruction?"
)
;
O
<<
", #"
<<
LdStDesc
->
NaturalOffset
;
}
}
printAnnotation
(
O
,
Annot
)
;
return
;
}
AArch64InstPrinter
::
printInst
(
MI
,
Address
,
Annot
,
STI
,
O
)
;
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s> bool PatmosInstrInfo :: isPseudo ( const MachineInstr * MI ) const { if ( MI -> isBundle ( ) ) { MachineBasicBlock :: const_instr_iterator II ( MI ) ; ++ II ; const MachineBasicBlock * MBB = MI -> getParent ( ) ; while ( II != MBB -> instr_end ( ) && II -> isBundledWithPred ( ) ) { if ( ! isPseudo ( & * II ) ) return false ; II ++ ; } return true ; } if ( MI -> isDebugValue ( ) ) return true ; if ( MI -> isInlineAsm ( ) ) return false ; const MCInstrDesc & TID = MI -> getDesc ( ) ; unsigned SchedClass = TID . getSchedClass ( ) ; const InstrStage * IS = PST . getInstrItineraryData ( ) -> beginStage ( SchedClass ) ; unsigned FuncUnits = IS -> getUnits ( ) ; return ! FuncUnits ; } </s>

Return true if this is a pseudo instruction that does n't correspond to a real machine instruction .


<s>
unsigned
HexagonInstrInfo
::
createVR
(
MachineFunction
*
MF
,
MVT
VT
)
const
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
const
TargetRegisterClass
*
TRC
;
if
(
VT
==
MVT
::
i1
)
{
TRC
=
&
Hexagon
::
PredRegsRegClass
;
}
else
if
(
VT
==
MVT
::
i32
||
VT
==
MVT
::
f32
)
{
TRC
=
&
Hexagon
::
IntRegsRegClass
;
}
else
if
(
VT
==
MVT
::
i64
||
VT
==
MVT
::
f64
)
{
TRC
=
&
Hexagon
::
DoubleRegsRegClass
;
}
else
{
llvm_unreachable
(
"Cannot handle this register class"
)
;
}
Register
NewReg
=
MRI
.
createVirtualRegister
(
TRC
)
;
return
NewReg
;
}
</s>


<s> bool arc_is_jli_call_p ( rtx pat ) { tree attrs ; tree decl = SYMBOL_REF_DECL ( pat ) ; if ( ! decl || ! SYMBOL_REF_FUNCTION_P ( pat ) || ! TREE_PUBLIC ( decl ) ) return false ; attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; if ( lookup_attribute ( "jli_always" , attrs ) ) return true ; if ( lookup_attribute ( "jli_fixed" , attrs ) ) return true ; return TARGET_JLI_ALWAYS ; } </s>

Return nonzero if a jli call should be generated for a call from the current function to DECL .


<s> static bool ix86_macro_fusion_p ( ) { return TARGET_FUSE_CMP_AND_BRANCH ; } </s>

Return true if target platform supports macro-fusion .


<s> static bool epiphany_rtx_costs ( rtx x , machine_mode mode , int outer_code , int opno ATTRIBUTE_UNUSED , int * total , bool speed ATTRIBUTE_UNUSED ) { int code = GET_CODE ( x ) ; switch ( code ) { case CONST_INT : if ( ( outer_code == PLUS || outer_code == MINUS ) && SIMM11 ( INTVAL ( x ) ) ) { * total = 0 ; return true ; } if ( IMM16 ( INTVAL ( x ) ) ) { * total = outer_code == SET ? 0 : COSTS_N_INSNS ( 1 ) ; return true ; } case CONST : case LABEL_REF : case SYMBOL_REF : * total = COSTS_N_INSNS ( ( epiphany_small16 ( x ) ? 0 : 1 ) + ( outer_code == SET ? 0 : 1 ) ) ; return true ; case CONST_DOUBLE : { rtx high , low ; split_double ( x , & high , & low ) ; * total = COSTS_N_INSNS ( ! IMM16 ( INTVAL ( high ) ) + ! IMM16 ( INTVAL ( low ) ) ) ; return true ; } case ASHIFT : case ASHIFTRT : case LSHIFTRT : * total = COSTS_N_INSNS ( 1 ) ; return true ; case COMPARE : switch ( mode ) { case CC_N_NEmode : case CC_C_LTUmode : case CC_C_GTUmode : return true ; default : return false ; } case SET : { rtx src = SET_SRC ( x ) ; if ( BINARY_P ( src ) ) * total = 0 ; return false ; } default : return false ; } } </s>

Compute a ( partial ) cost for rtx X . Return true if the complete cost has been computed , and false if subexpressions should be scanned . In either case , * TOTAL contains the cost result .


<s> void MipsAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const { MCFixupKind Kind = Fixup . getKind ( ) ; MCContext & Ctx = Asm . getContext ( ) ; Value = adjustFixupValue ( Fixup , Value , Ctx ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { case FK_Data_2 : case Mips :: fixup_Mips_16 : case Mips :: fixup_MICROMIPS_PC10_S1 : FullSize = 2 ; break ; case FK_Data_8 : case Mips :: fixup_Mips_64 : FullSize = 8 ; break ; case FK_Data_4 : default : FullSize = 4 ; break ; } uint64_t CurVal = 0 ; bool microMipsLEByteOrder = needsMMLEByteOrder ( ( unsigned ) Kind ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = Endian == support :: little ? ( microMipsLEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - 1 - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = Endian == support :: little ? ( microMipsLEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static bool loongarch_classify_address ( struct loongarch_address_info * info , rtx x , machine_mode mode , bool strict_p ) { switch ( GET_CODE ( x ) ) { case REG : case SUBREG : info -> type = ADDRESS_REG ; info -> reg = x ; info -> offset = const0_rtx ; return loongarch_valid_base_register_p ( info -> reg , mode , strict_p ) ; case PLUS : if ( loongarch_valid_base_register_p ( XEXP ( x , 0 ) , mode , strict_p ) && loongarch_valid_index_p ( info , XEXP ( x , 1 ) , mode , strict_p ) ) { info -> reg = XEXP ( x , 0 ) ; return true ; } if ( loongarch_valid_base_register_p ( XEXP ( x , 1 ) , mode , strict_p ) && loongarch_valid_index_p ( info , XEXP ( x , 0 ) , mode , strict_p ) ) { info -> reg = XEXP ( x , 1 ) ; return true ; } info -> type = ADDRESS_REG ; info -> reg = XEXP ( x , 0 ) ; info -> offset = XEXP ( x , 1 ) ; return ( loongarch_valid_base_register_p ( info -> reg , mode , strict_p ) && loongarch_valid_offset_p ( info -> offset , mode ) ) ; default : return false ; } } </s>

Return true if X is a valid address for machine mode MODE . If it is , fill in INFO appropriately . STRICT_P is true if REG_OK_STRICT is in effect .


<s> static rtx mcore_function_arg ( cumulative_args_t cum , machine_mode mode , const_tree type , bool named ) { int arg_reg ; if ( ! named || mode == VOIDmode ) return 0 ; if ( targetm . calls . must_pass_in_stack ( mode , type ) ) return 0 ; arg_reg = ROUND_REG ( * get_cumulative_args ( cum ) , mode ) ; if ( arg_reg < NPARM_REGS ) return handle_structs_in_regs ( mode , type , FIRST_PARM_REG + arg_reg ) ; return 0 ; } </s>

Define where to put the arguments to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . On MCore the first args are normally in registers and the rest are pushed . Any arg that starts within the first NPARM_REGS words is at least partially passed in a register unless its data type forbids .


<s> bool GBZ80FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( MFI -> getMaxCallFrameSize ( ) > 0 || ( MFI -> getNumObjects ( ) > 0 ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> unsigned getNumFixupKinds ( ) const override { return FISC :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .