<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasV4TOps ( false ) , HasV5TOps ( false ) , HasV5TEOps ( false ) , HasV6Ops ( false ) , HasV6T2Ops ( false ) , HasV7Ops ( false ) , HasVFPv2 ( false ) , HasVFPv3 ( false ) , HasNEON ( false ) , UseNEONForSinglePrecisionFP ( false ) , SlowFPVMLx ( false ) , HasVMLxForwarding ( false ) , SlowFPBrcc ( false ) , InThumbMode ( false ) , HasThumb2 ( false ) , IsMClass ( false ) , NoARM ( false ) , PostRAScheduler ( false ) , IsR9Reserved ( ReserveR9 ) , UseMovt ( false ) , SupportsTailCall ( false ) , HasFP16 ( false ) , HasD16 ( false ) , HasHardwareDivide ( false ) , HasT2ExtractPack ( false ) , HasDataBarrier ( false ) , Pref32BitThumb ( false ) , AvoidCPSRPartialUpdate ( false ) , HasMPExtension ( false ) , FPOnlySP ( false ) , AllowsUnalignedMem ( false ) , Thumb2DSP ( false ) , stackAlignment ( 4 ) , CPUString ( CPU ) , TargetTriple ( TT ) , TargetABI ( ARM_ABI_APCS ) { if ( CPUString . empty ( ) ) CPUString = "generic" ; std :: string ArchFS = ARM_MC :: ParseARMTriple ( TT ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ArchFS + "," + FS ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; if ( ! HasV6T2Ops && hasThumb2 ( ) ) HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; computeIssueWidth ( ) ; if ( TT . find ( "eabi" ) != std :: string :: npos ) TargetABI = ARM_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = 8 ; if ( ! isTargetDarwin ( ) ) UseMovt = hasV6T2Ops ( ) ; else { IsR9Reserved = ReserveR9 | ! HasV6Ops ; UseMovt = DarwinUseMOVT && hasV6T2Ops ( ) ; const Triple & T = getTargetTriple ( ) ; SupportsTailCall = T . getOS ( ) == Triple :: IOS && ! T . isOSVersionLT ( 5 , 0 ) ; } if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; if ( ! StrictAlign && hasV6Ops ( ) && isTargetDarwin ( ) ) AllowsUnalignedMem = true ; } </s>

This constructor initializes the data members to match that of the specified triple .

ARM ARM ARM ARM ARM ARM 4 ARM "generic" ARM ARM "," "eabi" ARM 8 5 0


<s> static int sparc_arg_partial_bytes ( cumulative_args_t cum , machine_mode mode , tree type , bool named ) { int slotno , regno , padding ; slotno = function_arg_slotno ( get_cumulative_args ( cum ) , mode , type , named , false , & regno , & padding ) ; if ( slotno == - 1 ) return 0 ; if ( TARGET_ARCH32 ) { if ( ( slotno + ( mode == BLKmode ? CEIL_NWORDS ( int_size_in_bytes ( type ) ) : CEIL_NWORDS ( GET_MODE_SIZE ( mode ) ) ) ) > SPARC_INT_ARG_MAX ) return ( SPARC_INT_ARG_MAX - slotno ) * UNITS_PER_WORD ; } else { if ( type && AGGREGATE_TYPE_P ( type ) ) { int size = int_size_in_bytes ( type ) ; if ( size > UNITS_PER_WORD && ( slotno == SPARC_INT_ARG_MAX - 1 || slotno == SPARC_FP_ARG_MAX - 1 ) ) return UNITS_PER_WORD ; } else if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_INT || ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT && ! ( TARGET_FPU && named ) ) ) { if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && slotno == SPARC_INT_ARG_MAX - 1 ) return UNITS_PER_WORD ; } else if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) { if ( ( slotno + GET_MODE_SIZE ( mode ) / UNITS_PER_WORD ) > SPARC_FP_ARG_MAX ) return UNITS_PER_WORD ; } } return 0 ; } </s>

For an arg passed partly in registers and partly in memory , this is the number of bytes of registers used . For args passed entirely in registers or entirely in memory , zero . Any arg that starts in the first 6 regs but wo n't entirely fit in them needs partial registers on v8 . On v9 , structures with integer values in arg slots 5,6 will be passed in % o5 and SP+176 , and complex fp values that begin in the last fp reg [ where `` last fp reg '' varies with the mode ] will be split between that reg and memory .


<s>
const
char
*
pru_output_signed_cbranch_ubyteop2
(
rtx
*
operands
,
bool
is_near
)
{
static
char
buf
[
1024
]
;
enum
rtx_code
code
=
GET_CODE
(
operands
[
0
]
)
;
int
regop_sign_bit_pos
=
sign_bit_position
(
operands
[
1
]
)
;
const
char
*
cmp_opstr
;
const
char
*
rcmp_opstr
;
code
=
swap_condition
(
code
)
;
switch
(
code
)
{
case
LT
:
cmp_opstr
=
"qblt"
;
rcmp_opstr
=
"qbge"
;
break
;
case
LE
:
cmp_opstr
=
"qble"
;
rcmp_opstr
=
"qbgt"
;
break
;
case
GT
:
cmp_opstr
=
"qbgt"
;
rcmp_opstr
=
"qble"
;
break
;
case
GE
:
cmp_opstr
=
"qbge"
;
rcmp_opstr
=
"qblt"
;
break
;
default
:
gcc_unreachable
(
)
;
}
if
(
code
==
LT
||
code
==
LE
)
{
if
(
is_near
)
snprintf
(
buf
,
sizeof
(
buf
)
,
"qbbs\t.+8, %%1, %d\n\t"
"%s\t%%l3, %%1, %%u2"
,
regop_sign_bit_pos
,
cmp_opstr
)
;
else
snprintf
(
buf
,
sizeof
(
buf
)
,
"qbbs\t.+12, %%1, %d\n\t"
"%s\t.+8, %%1, %%u2\n\t"
"jmp\t%%%%label(%%l3)"
,
regop_sign_bit_pos
,
rcmp_opstr
)
;
}
else
if
(
code
==
GT
||
code
==
GE
)
{
if
(
is_near
)
snprintf
(
buf
,
sizeof
(
buf
)
,
"qbbs\t%%l3, %%1, %d\n\t"
"%s\t%%l3, %%1, %%u2"
,
regop_sign_bit_pos
,
cmp_opstr
)
;
else
snprintf
(
buf
,
sizeof
(
buf
)
,
"qbbs\t.+8, %%1, %d\n\t"
"%s\t.+8, %%1, %%u2\n\t"
"jmp\t%%%%label(%%l3)"
,
regop_sign_bit_pos
,
rcmp_opstr
)
;
}
else
gcc_unreachable
(
)
;
return
buf
;
}
</s>

Optimized version of pru_output_signed_cbranch for constant second operand .


<s> const TargetRegisterClass * ARMTargetLowering :: getRegClassFor ( MVT VT , bool isDivergent ) const { ( void ) isDivergent ; if ( Subtarget -> hasNEON ( ) ) { if ( VT == MVT :: v4i64 ) return & ARM :: QQPRRegClass ; if ( VT == MVT :: v8i64 ) return & ARM :: QQQQPRRegClass ; } return TargetLowering :: getRegClassFor ( VT ) ; } </s>

Return the register class that should be used for the specified value type .

ARM ARM MVT::v4i64 ARM::QQPRRegClass MVT::v8i64 ARM::QQQQPRRegClass


<s> static rtx riscv_frame_set ( rtx mem , rtx reg ) { rtx set = gen_rtx_SET ( mem , reg ) ; RTX_FRAME_RELATED_P ( set ) = 1 ; return set ; } </s>

Return a frame-related rtx that stores REG at MEM . REG must be a single register .


<s> bool ARMTargetLowering :: shouldSinkOperands ( Instruction * I , SmallVectorImpl < Use * > & Ops ) const { if ( ! I -> getType ( ) -> isVectorTy ( ) ) return false ; if ( Subtarget -> hasNEON ( ) ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Sub : case Instruction :: Add : { if ( ! areExtractExts ( I -> getOperand ( 0 ) , I -> getOperand ( 1 ) ) ) return false ; Ops . push_back ( & I -> getOperandUse ( 0 ) ) ; Ops . push_back ( & I -> getOperandUse ( 1 ) ) ; return true ; } default : return false ; } } if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; auto IsSinker = [ ] ( Instruction * I , int Operand ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Add : case Instruction :: Mul : return true ; case Instruction :: Sub : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return Operand == 1 ; default : return false ; } } ; int Op = 0 ; if ( ! isa < ShuffleVectorInst > ( I -> getOperand ( Op ) ) ) Op = 1 ; if ( ! IsSinker ( I , Op ) ) return false ; if ( ! match ( I -> getOperand ( Op ) , m_ShuffleVector ( m_InsertElement ( m_Undef ( ) , m_Value ( ) , m_ZeroInt ( ) ) , m_Undef ( ) , m_Zero ( ) ) ) ) { return false ; } Instruction * Shuffle = cast < Instruction > ( I -> getOperand ( Op ) ) ; for ( Use & U : Shuffle -> uses ( ) ) { Instruction * Insn = cast < Instruction > ( U . getUser ( ) ) ; if ( ! IsSinker ( Insn , U . getOperandNo ( ) ) ) return false ; } Ops . push_back ( & Shuffle -> getOperandUse ( 0 ) ) ; Ops . push_back ( & I -> getOperandUse ( Op ) ) ; return true ; } </s>

Return true if sinking I 's operands to the same basic block as I is profitable , e.g .


" was Pass-through, is now Dirty-out.\n"

runOnMachineFunction - Emit the function body .


<s>
void
ARCInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
dl
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
assert
(
ARC
::
GPR32RegClass
.
contains
(
SrcReg
)
&&
"Only GPR32 src copy supported."
)
;
assert
(
ARC
::
GPR32RegClass
.
contains
(
DestReg
)
&&
"Only GPR32 dest copy supported."
)
;
BuildMI
(
MBB
,
I
,
dl
,
get
(
ARC
::
MOV_rr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> static rtx neon_vdup_constant ( rtx vals , bool generate ) { machine_mode mode = GET_MODE ( vals ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx x ; if ( GET_CODE ( vals ) != CONST_VECTOR || GET_MODE_SIZE ( inner_mode ) > 4 ) return NULL_RTX ; if ( ! const_vec_duplicate_p ( vals , & x ) ) return NULL_RTX ; if ( ! generate ) return x ; x = copy_to_mode_reg ( inner_mode , x ) ; return gen_vec_duplicate ( mode , x ) ; } </s>

Return a non-NULL RTX iff VALS is a vector constant that can be loaded into a register using VDUP . If this is the case , and GENERATE is set , we also generate instructions to do this and return an RTX to assign to the register .


<s> bool MipsSEInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock & MBB = * MI -> getParent ( ) ; bool isMicroMips = Subtarget . inMicroMipsMode ( ) ; unsigned Opc ; switch ( MI -> getDesc ( ) . getOpcode ( ) ) { default : return false ; case Mips :: RetRA : expandRetRA ( MBB , MI ) ; break ; case Mips :: PseudoMFHI : Opc = isMicroMips ? Mips :: MFHI16_MM : Mips :: MFHI ; expandPseudoMFHiLo ( MBB , MI , Opc ) ; break ; case Mips :: PseudoMFLO : Opc = isMicroMips ? Mips :: MFLO16_MM : Mips :: MFLO ; expandPseudoMFHiLo ( MBB , MI , Opc ) ; break ; case Mips :: PseudoMFHI64 : expandPseudoMFHiLo ( MBB , MI , Mips :: MFHI64 ) ; break ; case Mips :: PseudoMFLO64 : expandPseudoMFHiLo ( MBB , MI , Mips :: MFLO64 ) ; break ; case Mips :: PseudoMTLOHI : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO , Mips :: MTHI , false ) ; break ; case Mips :: PseudoMTLOHI64 : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO64 , Mips :: MTHI64 , false ) ; break ; case Mips :: PseudoMTLOHI_DSP : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO_DSP , Mips :: MTHI_DSP , true ) ; break ; case Mips :: PseudoCVT_S_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_D32_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_D32_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_S_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_L , Mips :: DMTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_W , Mips :: MTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_L , Mips :: DMTC1 , true ) ; break ; case Mips :: BuildPairF64 : expandBuildPairF64 ( MBB , MI , false ) ; break ; case Mips :: BuildPairF64_64 : expandBuildPairF64 ( MBB , MI , true ) ; break ; case Mips :: ExtractElementF64 : expandExtractElementF64 ( MBB , MI , false ) ; break ; case Mips :: ExtractElementF64_64 : expandExtractElementF64 ( MBB , MI , true ) ; break ; case Mips :: MIPSeh_return32 : case Mips :: MIPSeh_return64 : expandEhReturn ( MBB , MI ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> unsigned HexagonTTIImpl :: getScalarizationOverhead ( VectorType * Ty , const APInt & DemandedElts , bool Insert , bool Extract ) { return BaseT :: getScalarizationOverhead ( Ty , DemandedElts , Insert , Extract ) ; } </s>

Estimate the overhead of scalarizing an instruction .


<s> bool X86TargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const { return Imm == ( int32_t ) Imm ; } </s>

Return true if the specified immediate is legal icmp immediate , that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register .


<s> bool aarch64_sve_float_mul_immediate_p ( rtx x ) { rtx elt ; return ( const_vec_duplicate_p ( x , & elt ) && GET_CODE ( elt ) == CONST_DOUBLE && ( real_equal ( CONST_DOUBLE_REAL_VALUE ( elt ) , & dconsthalf ) || real_equal ( CONST_DOUBLE_REAL_VALUE ( elt ) , & dconst2 ) ) ) ; } </s>

Return true if X is a valid immediate operand for an SVE FMUL instruction .


<s> DecodeStatus SNESDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & VStream , raw_ostream & CStream ) const { uint32_t Insn ; DecodeStatus Result ; { Result = readInstruction16 ( Bytes , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( getDecoderTable ( Size ) , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) return Result ; } { Result = readInstruction32 ( Bytes , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( getDecoderTable ( Size ) , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { return Result ; } return MCDisassembler :: Fail ; } } </s>

Returns the disassembly of a single instruction .


<s> static bool arm_scalar_mode_supported_p ( machine_mode mode ) { if ( mode == HFmode ) return ( arm_fp16_format != ARM_FP16_FORMAT_NONE ) ; else if ( ALL_FIXED_POINT_MODE_P ( mode ) ) return true ; else return default_scalar_mode_supported_p ( mode ) ; } </s>

Implement TARGET_SCALAR_MODE_SUPPORTED_P . This simply adds HFmode as a supported mode ; even though we do n't implement arithmetic on this type directly , it 's supported by optabs conversions , much the way the double-word arithmetic is special-cased in the default hook .


<s> static sbitmap aarch64_components_for_bb ( basic_block bb ) { bitmap in = DF_LIVE_IN ( bb ) ; bitmap gen = & DF_LIVE_BB_INFO ( bb ) -> gen ; bitmap kill = & DF_LIVE_BB_INFO ( bb ) -> kill ; bool simd_function = aarch64_simd_decl_p ( cfun -> decl ) ; sbitmap components = sbitmap_alloc ( LAST_SAVED_REGNUM + 1 ) ; bitmap_clear ( components ) ; for ( unsigned regno = 0 ; regno <= LAST_SAVED_REGNUM ; regno ++ ) if ( ( ! call_used_regs [ regno ] || ( simd_function && FP_SIMD_SAVED_REGNUM_P ( regno ) ) ) && ( bitmap_bit_p ( in , regno ) || bitmap_bit_p ( gen , regno ) || bitmap_bit_p ( kill , regno ) ) ) { unsigned regno2 , offset , offset2 ; bitmap_set_bit ( components , regno ) ; offset = cfun -> machine -> frame . reg_offset [ regno ] ; regno2 = ( ( offset & 8 ) == 0 ) ? regno + 1 : regno - 1 ; if ( regno2 <= LAST_SAVED_REGNUM ) { offset2 = cfun -> machine -> frame . reg_offset [ regno2 ] ; if ( ( offset & ~ 8 ) == ( offset2 & ~ 8 ) ) bitmap_set_bit ( components , regno2 ) ; } } return components ; } </s>


<s> bool XtensaPassConfig :: addInstSelector ( ) { return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool MipsSubtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = TargetSubtargetInfo :: ANTIDEP_NONE ; CriticalPathRCs . clear ( ) ; CriticalPathRCs . push_back ( hasMips64 ( ) ? & Mips :: CPU64RegsRegClass : & Mips :: CPURegsRegClass ) ; return OptLevel >= CodeGenOpt :: Aggressive ; } </s>

True if the subtarget should run a scheduler after register allocation .

Mips Mips Mips Mips::CPU64RegsRegClass Mips::CPURegsRegClass


<s> StackOffset M88kFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { return StackOffset :: getFixed ( resolveFrameIndexReference ( MF , FI , FrameReg ) ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> void PPCDispatchGroupSBHazardRecognizer :: EmitNoop ( ) { unsigned Directive = DAG -> TM . getSubtarget < PPCSubtarget > ( ) . getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_PWR6 || Directive == PPC :: DIR_PWR7 || CurSlots == 6 ) { CurGroup . clear ( ) ; CurSlots = CurBranches = 0 ; } else { CurGroup . push_back ( 0 ) ; ++ CurSlots ; } } </s>

EmitNoop - This callback is invoked when a noop was added to the instruction stream .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


"Can't store this register to stack slot"


<s> static int ix86_nsaved_regs ( void ) { int nregs = 0 ; int regno ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( GENERAL_REGNO_P ( regno ) && ix86_save_reg ( regno , true ) ) nregs ++ ; return nregs ; } </s>

Return number of registers to be saved on the stack .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"AZPR Delay Slot Filler"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void AArch64TargetELFStreamer :: emitDirectiveVariantPCS ( MCSymbol * Symbol ) { cast < MCSymbolELF > ( Symbol ) -> setOther ( ELF :: STO_AARCH64_VARIANT_PCS ) ; } </s>

Callback used to implement the .variant_pcs directive .


<s> bool WebAssemblyTargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { const GlobalValue * GV = GA -> getGlobal ( ) ; return isa < Function > ( GV ) ? false : TargetLowering :: isOffsetFoldingLegal ( GA ) ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> void GCNUpwardRPTracker :: reset ( const MachineInstr & MI ) { MRI = & MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; LiveRegs = getLiveRegsAfter ( MI , LIS ) ; MaxPressure = CurPressure = getRegPressure ( * MRI , LiveRegs ) ; } </s>

Reset an existing scalar value for Def and a given Instance .


"%qE attribute ignored without -mcmse option."

"%qE attribute only applies to functions"

"%qE attribute has no effect on functions "

Called upon detection of the use of the cmse_nonsecure_entry attribute , this function will check whether the attribute is allowed here and will add the attribute to the function declaration tree or otherwise issue a warning .


<s> bool MLxExpansion :: runOnMachineFunction ( MachineFunction & Fn ) { TII = static_cast < const ARMBaseInstrInfo * > ( Fn . getTarget ( ) . getInstrInfo ( ) ) ; TRI = Fn . getTarget ( ) . getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; const ARMSubtarget * STI = & Fn . getTarget ( ) . getSubtarget < ARMSubtarget > ( ) ; isLikeA9 = STI -> isLikeA9 ( ) || STI -> isSwift ( ) ; isSwift = STI -> isSwift ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= ExpandFPMLxInstructions ( MBB ) ; } return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Hexagon Packetizer"
;
}
</s>


<s> virtual void AdvanceCycle ( ) { ResourceAssignment :: AdvanceCycle ( ) ; } </s>

AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled can not issue in the current cycle , either because of latency or resource conflicts .


"instruction requires a CPU feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> static void nvptx_split_blocks ( bb_insn_map_t * map ) { insn_bb_vec_t worklist ; basic_block block ; rtx_insn * insn ; FOR_ALL_BB_FN ( block , cfun ) { bool seen_insn = false ; block -> flags &= ~ BB_VISITED ; FOR_BB_INSNS ( block , insn ) { if ( ! INSN_P ( insn ) ) continue ; switch ( recog_memoized ( insn ) ) { default : seen_insn = true ; continue ; case CODE_FOR_nvptx_forked : case CODE_FOR_nvptx_join : break ; case CODE_FOR_return : break ; } if ( seen_insn ) worklist . safe_push ( insn_bb_t ( insn , block ) ) ; else map -> get_or_insert ( block ) = insn ; seen_insn = true ; } } unsigned ix ; insn_bb_t * elt ; basic_block remap = 0 ; for ( ix = 0 ; worklist . iterate ( ix , & elt ) ; ix ++ ) { if ( remap != elt -> second ) { block = elt -> second ; remap = block ; } edge e = split_block ( block , PREV_INSN ( elt -> first ) ) ; block = e -> dest ; map -> get_or_insert ( block ) = elt -> first ; } } </s>

See also 'gcc/omp-oacc-neuter-broadcast.cc : omp_sese_split_blocks ' .


<s> static void tilegx_init_libfuncs ( void ) { set_optab_libfunc ( sdiv_optab , SImode , "__divsi3" ) ; set_optab_libfunc ( udiv_optab , SImode , "__udivsi3" ) ; set_optab_libfunc ( smod_optab , SImode , "__modsi3" ) ; set_optab_libfunc ( umod_optab , SImode , "__umodsi3" ) ; } </s>


<s> bool X86FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const X86RegisterInfo * RegInfo = static_cast < const X86RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; unsigned SlotSize = RegInfo -> getSlotSize ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned CalleeSavedFrameSize = 0 ; int SpillSlotOffset = getOffsetOfLocalArea ( ) + X86FI -> getTCReturnAddrDelta ( ) ; if ( hasFP ( MF ) ) { SpillSlotOffset -= SlotSize ; MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; unsigned FPReg = RegInfo -> getFrameRegister ( MF ) ; for ( unsigned i = 0 ; i < CSI . size ( ) ; ++ i ) { if ( TRI -> regsOverlap ( CSI [ i ] . getReg ( ) , FPReg ) ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - 1 ] . setFrameIdx ( SlotIndex ) ; } X86FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = RegInfo -> getMinimalPhysRegClass ( Reg ) ; SpillSlotOffset -= std :: abs ( SpillSlotOffset ) % RC -> getAlignment ( ) ; SpillSlotOffset -= RC -> getSize ( ) ; int SlotIndex = MFI -> CreateFixedSpillStackObject ( RC -> getSize ( ) , SpillSlotOffset ) ; CSI [ i - 1 ] . setFrameIdx ( SlotIndex ) ; MFI -> ensureMaxAlignment ( RC -> getAlignment ( ) ) ; } return true ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> static const MCAsmInfo * createMCAsmInfo ( const Target & T , StringRef TT ) { Triple TheTriple ( TT ) ; switch ( TheTriple . getOS ( ) ) { case Triple :: Darwin : return new X86MCAsmInfoDarwin ( TheTriple ) ; case Triple :: MinGW32 : case Triple :: MinGW64 : case Triple :: Cygwin : case Triple :: Win32 : return new X86MCAsmInfoCOFF ( TheTriple ) ; default : return new X86ELFMCAsmInfo ( TheTriple ) ; } } </s>

createMCAsmInfo - Create a MCAsmInfo implementation for the specified target triple .


<s> static bool rs6000_vector_mode_supported_p ( enum machine_mode mode ) { if ( TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) return true ; else if ( TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE ( mode ) ) return true ; else return false ; } </s>

Target hook for vector_mode_supported_p .


Implement TARGET_MODES_TIEABLE_P . This asymmetric test is true when MODE1 could be put in an FP register but MODE2 could not .


<s> int function_arg_boundary ( enum machine_mode mode , tree type ) { if ( DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE ( mode ) == 8 ) return 64 ; else if ( SPE_VECTOR_MODE ( mode ) || ( type && TREE_CODE ( type ) == VECTOR_TYPE && int_size_in_bytes ( type ) >= 8 && int_size_in_bytes ( type ) < 16 ) ) return 64 ; else if ( ALTIVEC_VECTOR_MODE ( mode ) || ( type && TREE_CODE ( type ) == VECTOR_TYPE && int_size_in_bytes ( type ) >= 16 ) ) return 128 ; else if ( rs6000_darwin64_abi && mode == BLKmode && type && TYPE_ALIGN ( type ) > 64 ) return 128 ; else return PARM_BOUNDARY ; } </s>

If defined , a C expression that gives the alignment boundary , in bits , of an argument with the specified mode and type . If it is not defined , PARM_BOUNDARY is used for all arguments . V.4 wants long longs to be double word aligned . Doubleword align SPE vectors . Quadword align Altivec vectors . Quadword align large synthetic vector types .


<s> bool X86RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> static rtx aarch64_simd_dup_constant ( rtx vals ) { machine_mode mode = GET_MODE ( vals ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; int n_elts = GET_MODE_NUNITS ( mode ) ; bool all_same = true ; rtx x ; int i ; if ( GET_CODE ( vals ) != CONST_VECTOR ) return NULL_RTX ; for ( i = 1 ; i < n_elts ; ++ i ) { x = CONST_VECTOR_ELT ( vals , i ) ; if ( ! rtx_equal_p ( x , CONST_VECTOR_ELT ( vals , 0 ) ) ) all_same = false ; } if ( ! all_same ) return NULL_RTX ; x = copy_to_mode_reg ( inner_mode , CONST_VECTOR_ELT ( vals , 0 ) ) ; return gen_rtx_VEC_DUPLICATE ( mode , x ) ; } </s>

If VALS is a vector constant that can be loaded into a register using DUP , generate instructions to do so and return an RTX to assign to the register . Otherwise return NULL_RTX .


"Only DWARF debug format is supported for interrupt "

Set the func_type field from the function FNDECL .


<s> const MCExpr * getSubExpr ( ) const { return Expr ; } </s>

getSubExpr - Get the child of this expression .


<s>
scalar_chain
::
scalar_chain
(
enum
machine_mode
smode_
,
enum
machine_mode
vmode_
)
{
smode
=
smode_
;
vmode
=
vmode_
;
chain_id
=
++
max_id
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Created a new instruction chain #%d\n"
,
chain_id
)
;
bitmap_obstack_initialize
(
)
;
insns
=
BITMAP_ALLOC
(
)
;
defs
=
BITMAP_ALLOC
(
)
;
defs_conv
=
BITMAP_ALLOC
(
)
;
queue
=
;
}
</s>


<s> void visium_expand_int_cstore ( rtx * operands , enum machine_mode mode ) { enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; rtx op0 = operands [ 0 ] , op1 = operands [ 2 ] , op2 = operands [ 3 ] , sltu ; bool reverse = false ; switch ( code ) { case EQ : case NE : if ( op2 != const0_rtx ) op1 = force_reg ( mode , gen_rtx_XOR ( mode , op1 , op2 ) ) ; op1 = gen_rtx_NOT ( mode , op1 ) ; op2 = constm1_rtx ; if ( code == EQ ) reverse = true ; break ; case LEU : case GEU : code = reverse_condition ( code ) ; reverse = true ; case LTU : case GTU : if ( code == GTU ) { rtx tmp = op1 ; op1 = op2 ; op2 = tmp ; } break ; default : gcc_unreachable ( ) ; } sltu = gen_rtx_LTU ( SImode , op1 , op2 ) ; if ( reverse ) { rtx tmp = copy_to_mode_reg ( SImode , gen_rtx_NEG ( SImode , sltu ) ) ; emit_insn ( gen_add3_insn ( op0 , tmp , const1_rtx ) ) ; } else emit_insn ( gen_rtx_SET ( op0 , sltu ) ) ; } </s>

Expand a cstore of OPERANDS in MODE for EQ/NE/LTU/GTU/GEU/LEU . We generate the result in the C flag and use the ADC/SUBC instructions to write it into the destination register . It would also be possible to implement support for LT/GT/LE/GE by means of the RFLAG instruction followed by some shifts , but this can pessimize the generated code .


<s> static unsigned int h8300_classify_operand ( rtx op , int size , enum h8300_operand_class * opclass ) { enum h8300_operand_class dummy ; if ( opclass == 0 ) opclass = & dummy ; if ( CONSTANT_P ( op ) ) { * opclass = H8OP_IMMEDIATE ; if ( size == 1 ) return 0 ; if ( TARGET_H8300SX && size == 4 && GET_CODE ( op ) == CONST_INT && IN_RANGE ( INTVAL ( op ) , 0 , 0xffff ) ) return 2 ; return size ; } else if ( GET_CODE ( op ) == MEM ) { op = XEXP ( op , 0 ) ; if ( CONSTANT_P ( op ) ) { * opclass = H8OP_MEM_ABSOLUTE ; return h8300_constant_length ( op ) ; } else if ( GET_CODE ( op ) == PLUS && CONSTANT_P ( XEXP ( op , 1 ) ) ) { * opclass = H8OP_MEM_COMPLEX ; return h8300_displacement_length ( op , size ) ; } else if ( GET_RTX_CLASS ( GET_CODE ( op ) ) == RTX_AUTOINC ) { * opclass = H8OP_MEM_COMPLEX ; return 0 ; } else if ( register_operand ( op , VOIDmode ) ) { * opclass = H8OP_MEM_BASE ; return 0 ; } } gcc_assert ( register_operand ( op , VOIDmode ) ) ; * opclass = H8OP_REGISTER ; return 0 ; } </s>

Store the class of operand OP in * CLASS and return the length of any extra operand fields . SIZE is the number of bytes in OP . CLASS can be null if only the length is needed .


<s> bool AMDGPUTargetLowering :: isZExtFree ( EVT Src , EVT Dest ) const { if ( Src == MVT :: i16 ) return Dest == MVT :: i32 || Dest == MVT :: i64 ; return Src == MVT :: i32 && Dest == MVT :: i64 ; } </s>

Return true if zero-extending the specific node Val to type VT2 is free ( either because it 's implicitly zero-extended such as ARM ldrb / ldrh or because it 's folded such as X86 zero-extending loads ) .


<s> int aarch64_vec_fpconst_pow_of_2 ( rtx x ) { if ( GET_CODE ( x ) != CONST_VECTOR ) return - 1 ; if ( GET_MODE_CLASS ( GET_MODE ( x ) ) != MODE_VECTOR_FLOAT ) return - 1 ; int firstval = aarch64_fpconst_pow_of_2 ( CONST_VECTOR_ELT ( x , 0 ) ) ; if ( firstval <= 0 ) return - 1 ; for ( int i = 1 ; i < CONST_VECTOR_NUNITS ( x ) ; i ++ ) if ( aarch64_fpconst_pow_of_2 ( CONST_VECTOR_ELT ( x , i ) ) != firstval ) return - 1 ; return firstval ; } </s>

If X is a vector of equal CONST_DOUBLE values and that value is Y , return the aarch64_fpconst_pow_of_2 of Y . Otherwise return -1 .


<s> static inline bool is_fast_interrupt_func ( const_tree decl ) { return has_func_attr ( decl , "fast_interrupt" ) ; } </s>

Returns true if the provided function has the `` fast_interrupt '' attribute .


<s> SDNode * PIC16DAGToDAGISel :: Select ( SDNode * N ) { SDNode * ResNode = SelectCode ( N ) ; return ResNode ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> rtx s390_return_addr_rtx ( int count , rtx frame ATTRIBUTE_UNUSED ) { int offset ; rtx addr ; if ( ! TARGET_BACKCHAIN && count > 0 ) return NULL_RTX ; if ( count == 0 ) return get_hard_reg_initial_val ( Pmode , RETURN_REGNUM ) ; if ( TARGET_PACKED_STACK ) offset = - 2 * UNITS_PER_LONG ; else offset = RETURN_REGNUM * UNITS_PER_LONG ; addr = plus_constant ( Pmode , frame , offset ) ; addr = memory_address ( Pmode , addr ) ; return gen_rtx_MEM ( Pmode , addr ) ; } </s>

Return an RTL expression representing the value of the return address for the frame COUNT steps up from the current frame . FRAME is the frame pointer of that frame .


<s> bool VERegisterInfo :: isConstantPhysReg ( MCRegister PhysReg ) const { return false ; } </s>

Returns true if PhysReg is unallocatable and constant throughout the function .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Z80old Expand Pseudo Instructions"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
unsigned
int
TMS320C64XRegisterInfo
::
getSubReg
(
unsigned
int
,
unsigned
int
)
const
{
llvm_unreachable
(
"Unimplemented function getSubReg\n"
)
;
}
</s>

Returns the physical register number of sub-register `` Index '' for physical register RegNo .


<s> void SparcFrameLowering :: emitPrologue ( MachineFunction & MF ) const { SparcMachineFunctionInfo * FuncInfo = MF . getInfo < SparcMachineFunctionInfo > ( ) ; MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const SparcInstrInfo & TII = * static_cast < const SparcInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; unsigned SAVEri = SP :: SAVEri ; unsigned SAVErr = SP :: SAVErr ; if ( FuncInfo -> isLeafProc ( ) ) { if ( NumBytes == 0 ) return ; SAVEri = SP :: ADDri ; SAVErr = SP :: ADDrr ; } NumBytes = - SubTarget . getAdjustedFrameSize ( NumBytes ) ; emitSPAdjustment ( MF , MBB , MBBI , NumBytes , SAVErr , SAVEri ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; MCSymbol * FrameLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: PROLOG_LABEL ) ) . addSym ( FrameLabel ) ; unsigned regFP = MRI -> getDwarfRegNum ( SP :: I6 , true ) ; MMI . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( FrameLabel , regFP ) ) ; MMI . addFrameInst ( MCCFIInstruction :: createWindowSave ( FrameLabel ) ) ; unsigned regInRA = MRI -> getDwarfRegNum ( SP :: I7 , true ) ; unsigned regOutRA = MRI -> getDwarfRegNum ( SP :: O7 , true ) ; MMI . addFrameInst ( MCCFIInstruction :: createRegister ( FrameLabel , regOutRA , regInRA ) ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s>
ArrayRef
<
MCPhysReg
>
MipsABIInfo
::
GetByValArgRegs
(
)
const
{
if
(
IsCheriPureCap
(
)
)
return
{
}
;
if
(
IsO32
(
)
)
return
makeArrayRef
(
O32IntRegs
)
;
if
(
IsN32
(
)
||
IsN64
(
)
)
return
makeArrayRef
(
Mips64IntRegs
)
;
llvm_unreachable
(
"Unhandled ABI"
)
;
}
</s>

The registers to use for byval arguments .


<s> static rtx function_arg_record_value ( const_tree type , machine_mode mode , int slotno , bool named , int regbase ) { HOST_WIDE_INT typesize = int_size_in_bytes ( type ) ; assign_data_t data ; int nregs ; data . slotno = slotno ; data . regbase = regbase ; data . nregs = 0 ; data . intoffset = 0 ; data . stack = false ; traverse_record_type < assign_data_t , count_registers > ( type , named , & data ) ; if ( compute_int_layout ( typesize * BITS_PER_UNIT , & data , & nregs ) ) data . nregs += nregs ; nregs = data . nregs ; if ( nregs == 0 ) { if ( typesize <= 0 ) { return gen_rtx_REG ( mode , regbase ) ; } nregs = ( typesize + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; if ( nregs + slotno > SPARC_INT_ARG_MAX ) nregs = SPARC_INT_ARG_MAX - slotno ; } gcc_assert ( nregs > 0 ) ; data . ret = gen_rtx_PARALLEL ( mode , rtvec_alloc ( data . stack + nregs ) ) ; if ( data . stack ) XVECEXP ( data . ret , 0 , 0 ) = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; data . nregs = 0 ; data . intoffset = 0 ; traverse_record_type < assign_data_t , assign_registers > ( type , named , & data ) ; assign_int_registers ( typesize * BITS_PER_UNIT , & data ) ; gcc_assert ( data . nregs == nregs ) ; return data . ret ; } </s>

Used by function_arg and sparc_function_value_1 to implement the complex conventions of the 64-bit ABI for passing and returning structures . Return an expression valid as a return value for the FUNCTION_ARG and TARGET_FUNCTION_VALUE . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . MODE is the argument 's machine mode . SLOTNO is the index number of the argument 's slot in the parameter array . NAMED is true if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . REGBASE is the regno of the base register for the parameter array .


<s>
const
RegisterBank
&
AArch64RegisterBankInfo
::
getRegBankFromRegClass
(
const
TargetRegisterClass
&
RC
)
const
{
switch
(
RC
.
getID
(
)
)
{
case
AArch64
::
FPR8RegClassID
:
case
AArch64
::
FPR16RegClassID
:
case
AArch64
::
FPR32RegClassID
:
case
AArch64
::
FPR64RegClassID
:
case
AArch64
::
FPR128RegClassID
:
case
AArch64
::
FPR128_loRegClassID
:
case
AArch64
::
DDRegClassID
:
case
AArch64
::
DDDRegClassID
:
case
AArch64
::
DDDDRegClassID
:
case
AArch64
::
QQRegClassID
:
case
AArch64
::
QQQRegClassID
:
case
AArch64
::
QQQQRegClassID
:
return
getRegBank
(
AArch64
::
FPRRegBankID
)
;
case
AArch64
::
GPR32commonRegClassID
:
case
AArch64
::
GPR32RegClassID
:
case
AArch64
::
GPR32spRegClassID
:
case
AArch64
::
GPR32sponlyRegClassID
:
case
AArch64
::
GPR32allRegClassID
:
case
AArch64
::
GPR64commonRegClassID
:
case
AArch64
::
GPR64RegClassID
:
case
AArch64
::
GPR64spRegClassID
:
case
AArch64
::
GPR64sponlyRegClassID
:
case
AArch64
::
GPR64allRegClassID
:
case
AArch64
::
tcGPR64RegClassID
:
case
AArch64
::
WSeqPairsClassRegClassID
:
case
AArch64
::
XSeqPairsClassRegClassID
:
return
getRegBank
(
AArch64
::
GPRRegBankID
)
;
case
AArch64
::
CCRRegClassID
:
return
getRegBank
(
AArch64
::
CCRegBankID
)
;
default
:
llvm_unreachable
(
"Register class not supported"
)
;
}
}
</s>


<s> RCPair ARMTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: tGPRRegClass ) ; return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'h' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: hGPRRegClass ) ; break ; case 'r' : if ( Subtarget -> isThumb1Only ( ) ) return RCPair ( 0U , & ARM :: tGPRRegClass ) ; return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'w' : if ( VT == MVT :: Other ) break ; if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPRRegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPRRegClass ) ; break ; case 'x' : if ( VT == MVT :: Other ) break ; if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPR_8RegClass ) ; break ; case 't' : if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( ARM :: CPSR ) , & ARM :: CCRRegClass ) ; return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s>
void
X86DAGToDAGISel
::
PreprocessISelDAG
(
)
{
OptForSize
=
MF
->
getFunction
(
)
.
optForSize
(
)
;
OptForMinSize
=
MF
->
getFunction
(
)
.
optForMinSize
(
)
;
assert
(
(
!
OptForMinSize
||
OptForSize
)
&&
"OptForMinSize implies OptForSize"
)
;
for
(
SelectionDAG
::
allnodes_iterator
I
=
CurDAG
->
allnodes_begin
(
)
,
E
=
CurDAG
->
allnodes_end
(
)
;
I
!=
E
;
)
{
SDNode
*
N
=
&
*
I
++
;
if
(
OptLevel
!=
CodeGenOpt
::
&&
!
Subtarget
->
useRetpoline
(
)
&&
(
(
N
->
getOpcode
(
)
==
X86ISD
::
CALL
&&
!
Subtarget
->
slowTwoMemOps
(
)
)
||
(
N
->
getOpcode
(
)
==
X86ISD
::
TC_RETURN
&&
(
Subtarget
->
is64Bit
(
)
||
!
getTargetMachine
(
)
.
isPositionIndependent
(
)
)
)
)
)
{
bool
HasCallSeq
=
N
->
getOpcode
(
)
==
X86ISD
::
CALL
;
SDValue
Chain
=
N
->
getOperand
(
0
)
;
SDValue
Load
=
N
->
getOperand
(
1
)
;
if
(
!
isCalleeLoad
(
Load
,
Chain
,
HasCallSeq
)
)
continue
;
moveBelowOrigChain
(
CurDAG
,
Load
,
SDValue
(
N
,
0
)
,
Chain
)
;
++
NumLoadMoved
;
continue
;
}
if
(
N
->
getOpcode
(
)
!=
ISD
::
FP_ROUND
&&
N
->
getOpcode
(
)
!=
ISD
::
FP_EXTEND
)
continue
;
MVT
SrcVT
=
N
->
getOperand
(
0
)
.
getSimpleValueType
(
)
;
MVT
DstVT
=
N
->
getSimpleValueType
(
0
)
;
if
(
SrcVT
.
isVector
(
)
||
DstVT
.
isVector
(
)
)
continue
;
const
X86TargetLowering
*
X86Lowering
=
static_cast
<
const
X86TargetLowering
*
>
(
TLI
)
;
bool
SrcIsSSE
=
X86Lowering
->
isScalarFPTypeInSSEReg
(
SrcVT
)
;
bool
DstIsSSE
=
X86Lowering
->
isScalarFPTypeInSSEReg
(
DstVT
)
;
if
(
SrcIsSSE
&&
DstIsSSE
)
continue
;
if
(
!
SrcIsSSE
&&
!
DstIsSSE
)
{
if
(
N
->
getOpcode
(
)
==
ISD
::
FP_EXTEND
)
continue
;
if
(
N
->
getConstantOperandVal
(
1
)
)
continue
;
}
MVT
MemVT
;
if
(
N
->
getOpcode
(
)
==
ISD
::
FP_ROUND
)
MemVT
=
DstVT
;
else
MemVT
=
SrcIsSSE
SrcVT
:
DstVT
;
SDValue
MemTmp
=
CurDAG
->
CreateStackTemporary
(
MemVT
)
;
SDLoc
dl
(
N
)
;
SDValue
Store
=
CurDAG
->
getTruncStore
(
CurDAG
->
getEntryNode
(
)
,
dl
,
N
->
getOperand
(
0
)
,
MemTmp
,
MachinePointerInfo
(
)
,
MemVT
)
;
SDValue
Result
=
CurDAG
->
getExtLoad
(
ISD
::
EXTLOAD
,
dl
,
DstVT
,
Store
,
MemTmp
,
MachinePointerInfo
(
)
,
MemVT
)
;
I
;
CurDAG
->
ReplaceAllUsesOfValueWith
(
SDValue
(
N
,
0
)
,
Result
)
;
++
I
;
CurDAG
->
DeleteNode
(
N
)
;
}
}
</s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> static int getRegClass ( RegisterKind Is , unsigned RegWidth ) { if ( Is == IS_VGPR ) { switch ( RegWidth ) { default : return - 1 ; case 1 : return AMDGPU :: VGPR_32RegClassID ; case 2 : return AMDGPU :: VReg_64RegClassID ; case 3 : return AMDGPU :: VReg_96RegClassID ; case 4 : return AMDGPU :: VReg_128RegClassID ; case 8 : return AMDGPU :: VReg_256RegClassID ; case 16 : return AMDGPU :: VReg_512RegClassID ; } } else if ( Is == IS_TTMP ) { switch ( RegWidth ) { default : return - 1 ; case 1 : return AMDGPU :: TTMP_32RegClassID ; case 2 : return AMDGPU :: TTMP_64RegClassID ; case 4 : return AMDGPU :: TTMP_128RegClassID ; case 8 : return AMDGPU :: TTMP_256RegClassID ; case 16 : return AMDGPU :: TTMP_512RegClassID ; } } else if ( Is == IS_SGPR ) { switch ( RegWidth ) { default : return - 1 ; case 1 : return AMDGPU :: SGPR_32RegClassID ; case 2 : return AMDGPU :: SGPR_64RegClassID ; case 4 : return AMDGPU :: SGPR_128RegClassID ; case 8 : return AMDGPU :: SGPR_256RegClassID ; case 16 : return AMDGPU :: SGPR_512RegClassID ; } } return - 1 ; } </s>

Given a machine instruction descriptor , returns the register class constraint for OpNum , or NULL .


<s> int sh_max_mov_insn_displacement ( machine_mode mode , bool consider_sh2a ) { const int disp_scale = consider_sh2a ? ( 4095 / 15 ) : 1 ; if ( ! consider_sh2a && TARGET_FPU_ANY && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return 0 ; else { const int mov_insn_sz = mov_insn_size ( mode , consider_sh2a ) ; const int mode_sz = GET_MODE_SIZE ( mode ) ; int r = 15 * mov_insn_sz * disp_scale ; if ( mode_sz > mov_insn_sz ) r -= mode_sz - mov_insn_sz ; return r ; } } </s>

Determine the maximum possible displacement for a move insn for the specified mode .


<s> static inline int regno_or_subregno ( rtx op ) { if ( REG_P ( op ) ) return REGNO ( op ) ; else if ( SUBREG_P ( op ) ) return subreg_regno ( op ) ; else gcc_unreachable ( ) ; } </s>

Helper function to return the register number of a RTX .


<s> Value * AArch64TargetLowering :: emitLoadLinked ( IRBuilderBase & Builder , Type * ValueTy , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsAcquire = isAcquireOrStronger ( Ord ) ; if ( ValueTy -> getPrimitiveSizeInBits ( ) == 128 ) { Intrinsic :: ID Int = IsAcquire ? Intrinsic :: aarch64_ldaxp : Intrinsic :: aarch64_ldxp ; Function * Ldxr = Intrinsic :: getDeclaration ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldxr , Addr , "lohi" ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ; Lo = Builder . CreateZExt ( Lo , ValueTy , "lo64" ) ; Hi = Builder . CreateZExt ( Hi , ValueTy , "hi64" ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValueTy , 64 ) ) , "val64" ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; Intrinsic :: ID Int = IsAcquire ? Intrinsic :: aarch64_ldaxr : Intrinsic :: aarch64_ldxr ; Function * Ldxr = Intrinsic :: getDeclaration ( M , Int , Tys ) ; const DataLayout & DL = M -> getDataLayout ( ) ; IntegerType * IntEltTy = Builder . getIntNTy ( DL . getTypeSizeInBits ( ValueTy ) ) ; Value * Trunc = Builder . CreateTrunc ( Builder . CreateCall ( Ldxr , Addr ) , IntEltTy ) ; return Builder . CreateBitCast ( Trunc , ValueTy ) ; } </s>

Perform a load-linked operation on Addr , returning a `` Value * '' with the corresponding pointee type .


<s> ScheduleHazardRecognizer :: HazardType SystemZHazardRecognizer :: getHazardType ( SUnit * SU , int Stalls ) { return ( fitsIntoCurrentGroup ( SU ) ? NoHazard : Hazard ) ; } </s>

getHazardType - Return the hazard type of emitting this node .


<s> bool AArch64ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const AArch64InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; auto UniqueRS = make_unique < RegScavenger > ( ) ; RS = UniqueRS . get ( ) ; bool Modified = false ; for ( auto & MBB : MF ) Modified |= expandMBB ( MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> const char * MipsTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case MipsISD :: JmpLink : return "MipsISD::JmpLink" ; case MipsISD :: TailCall : return "MipsISD::TailCall" ; case MipsISD :: Hi : return "MipsISD::Hi" ; case MipsISD :: Lo : return "MipsISD::Lo" ; case MipsISD :: GPRel : return "MipsISD::GPRel" ; case MipsISD :: ThreadPointer : return "MipsISD::ThreadPointer" ; case MipsISD :: Ret : return "MipsISD::Ret" ; case MipsISD :: FPBrcond : return "MipsISD::FPBrcond" ; case MipsISD :: FPCmp : return "MipsISD::FPCmp" ; case MipsISD :: CMovFP_T : return "MipsISD::CMovFP_T" ; case MipsISD :: CMovFP_F : return "MipsISD::CMovFP_F" ; case MipsISD :: FPRound : return "MipsISD::FPRound" ; case MipsISD :: MAdd : return "MipsISD::MAdd" ; case MipsISD :: MAddu : return "MipsISD::MAddu" ; case MipsISD :: MSub : return "MipsISD::MSub" ; case MipsISD :: MSubu : return "MipsISD::MSubu" ; case MipsISD :: DivRem : return "MipsISD::DivRem" ; case MipsISD :: DivRemU : return "MipsISD::DivRemU" ; case MipsISD :: BuildPairF64 : return "MipsISD::BuildPairF64" ; case MipsISD :: ExtractElementF64 : return "MipsISD::ExtractElementF64" ; case MipsISD :: Wrapper : return "MipsISD::Wrapper" ; case MipsISD :: Sync : return "MipsISD::Sync" ; case MipsISD :: Ext : return "MipsISD::Ext" ; case MipsISD :: Ins : return "MipsISD::Ins" ; case MipsISD :: LWL : return "MipsISD::LWL" ; case MipsISD :: LWR : return "MipsISD::LWR" ; case MipsISD :: SWL : return "MipsISD::SWL" ; case MipsISD :: SWR : return "MipsISD::SWR" ; case MipsISD :: LDL : return "MipsISD::LDL" ; case MipsISD :: LDR : return "MipsISD::LDR" ; case MipsISD :: SDL : return "MipsISD::SDL" ; case MipsISD :: SDR : return "MipsISD::SDR" ; case MipsISD :: EXTP : return "MipsISD::EXTP" ; case MipsISD :: EXTPDP : return "MipsISD::EXTPDP" ; case MipsISD :: EXTR_S_H : return "MipsISD::EXTR_S_H" ; case MipsISD :: EXTR_W : return "MipsISD::EXTR_W" ; case MipsISD :: EXTR_R_W : return "MipsISD::EXTR_R_W" ; case MipsISD :: EXTR_RS_W : return "MipsISD::EXTR_RS_W" ; case MipsISD :: SHILO : return "MipsISD::SHILO" ; case MipsISD :: MTHLIP : return "MipsISD::MTHLIP" ; case MipsISD :: MULT : return "MipsISD::MULT" ; case MipsISD :: MULTU : return "MipsISD::MULTU" ; case MipsISD :: MADD_DSP : return "MipsISD::MADD_DSPDSP" ; case MipsISD :: MADDU_DSP : return "MipsISD::MADDU_DSP" ; case MipsISD :: MSUB_DSP : return "MipsISD::MSUB_DSP" ; case MipsISD :: MSUBU_DSP : return "MipsISD::MSUBU_DSP" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific

Mips Mips MipsISD::JmpLink "MipsISD::JmpLink" MipsISD::TailCall "MipsISD::TailCall" MipsISD::Hi "MipsISD::Hi" MipsISD::Lo "MipsISD::Lo" MipsISD::GPRel "MipsISD::GPRel" MipsISD::ThreadPointer "MipsISD::ThreadPointer" MipsISD::Ret "MipsISD::Ret" MipsISD::FPBrcond "MipsISD::FPBrcond" MipsISD::FPCmp "MipsISD::FPCmp" MipsISD::CMovFP_T "MipsISD::CMovFP_T" MipsISD::CMovFP_F "MipsISD::CMovFP_F" MipsISD::FPRound "MipsISD::FPRound" MipsISD::MAdd "MipsISD::MAdd" MipsISD::MAddu "MipsISD::MAddu" MipsISD::MSub "MipsISD::MSub" MipsISD::MSubu "MipsISD::MSubu" MipsISD::DivRem "MipsISD::DivRem" MipsISD::DivRemU "MipsISD::DivRemU" MipsISD::BuildPairF64 "MipsISD::BuildPairF64" MipsISD::ExtractElementF64 "MipsISD::ExtractElementF64" MipsISD::Wrapper "MipsISD::Wrapper" MipsISD::Sync "MipsISD::Sync" MipsISD::Ext "MipsISD::Ext" MipsISD::Ins "MipsISD::Ins" MipsISD::LWL "MipsISD::LWL" MipsISD::LWR "MipsISD::LWR" MipsISD::SWL "MipsISD::SWL" MipsISD::SWR "MipsISD::SWR" MipsISD::LDL "MipsISD::LDL" MipsISD::LDR "MipsISD::LDR" MipsISD::SDL "MipsISD::SDL" MipsISD::SDR "MipsISD::SDR" MipsISD::EXTP "MipsISD::EXTP" MipsISD::EXTPDP "MipsISD::EXTPDP" MipsISD::EXTR_S_H "MipsISD::EXTR_S_H" MipsISD::EXTR_W "MipsISD::EXTR_W" MipsISD::EXTR_R_W "MipsISD::EXTR_R_W" MipsISD::EXTR_RS_W "MipsISD::EXTR_RS_W" MipsISD::SHILO "MipsISD::SHILO" MipsISD::MTHLIP "MipsISD::MTHLIP" MipsISD::MULT "MipsISD::MULT" MipsISD::MULTU "MipsISD::MULTU" MipsISD::MADD_DSP "MipsISD::MADD_DSPDSP" MipsISD::MADDU_DSP "MipsISD::MADDU_DSP" MipsISD::MSUB_DSP "MipsISD::MSUB_DSP" MipsISD::MSUBU_DSP "MipsISD::MSUBU_DSP"


<s> bool HexagonInstrInfo :: getMemOperandsWithOffsetWidth ( const MachineInstr & LdSt , SmallVectorImpl < const MachineOperand * > & BaseOps , int64_t & Offset , bool & OffsetIsScalable , unsigned & Width , const TargetRegisterInfo * TRI ) const { OffsetIsScalable = false ; const MachineOperand * BaseOp = getBaseAndOffset ( LdSt , Offset , Width ) ; if ( ! BaseOp || ! BaseOp -> isReg ( ) ) return false ; BaseOps . push_back ( BaseOp ) ; return true ; } </s>

Get zero or more base operands and the byte offset of an instruction that reads/writes memory .


<s> static unsigned int mips_build_lower ( struct mips_integer_op * codes , unsigned HOST_WIDE_INT value ) { unsigned HOST_WIDE_INT high ; unsigned int i ; high = value & ~ ( unsigned HOST_WIDE_INT ) 0xffff ; if ( ! LUI_OPERAND ( high ) && ( value & 0x18000 ) == 0x18000 ) { i = mips_build_integer ( codes , CONST_HIGH_PART ( value ) ) ; codes [ i ] . code = PLUS ; codes [ i ] . value = CONST_LOW_PART ( value ) ; } else { i = mips_build_integer ( codes , high ) ; codes [ i ] . code = IOR ; codes [ i ] . value = value & 0xffff ; } return i + 1 ; } </s>

As for mips_build_shift , but assume that the final action will be an IOR or PLUS operation .


<s> int SparcSubtarget :: getAdjustedFrameSize ( int frameSize ) const { if ( is64Bit ( ) ) { frameSize += 128 ; frameSize = RoundUpToAlignment ( frameSize , 16 ) ; } else { frameSize += 92 ; frameSize = RoundUpToAlignment ( frameSize , 8 ) ; } return frameSize ; } </s>

Given a actual stack size as determined by FrameInfo , this function returns adjusted framesize which includes space for RSA , return address , and frame poitner .


<s> static bool rs6000_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { if ( RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p ) { extern int in_toc_section ( void ) ; static int recurse = 0 ; if ( TARGET_RELOCATABLE && ! in_toc_section ( ) && ! in_text_section ( ) && ! in_unlikely_text_section ( ) && ! recurse && GET_CODE ( x ) != CONST_INT && GET_CODE ( x ) != CONST_DOUBLE && CONSTANT_P ( x ) ) { char buf [ 256 ] ; recurse = 1 ; ASM_GENERATE_INTERNAL_LABEL ( buf , "LCP" , fixuplabelno ) ; fixuplabelno ++ ; ASM_OUTPUT_LABEL ( asm_out_file , buf ) ; fprintf ( asm_out_file , "\t.long\t(" ) ; output_addr_const ( asm_out_file , x ) ; fprintf ( asm_out_file , ")@fixup\n" ) ; fprintf ( asm_out_file , "\t.section\t\".fixup\",\"aw\"\n" ) ; ASM_OUTPUT_ALIGN ( asm_out_file , 2 ) ; fprintf ( asm_out_file , "\t.long\t" ) ; assemble_name ( asm_out_file , buf ) ; fprintf ( asm_out_file , "\n\t.previous\n" ) ; recurse = 0 ; return true ; } else if ( GET_CODE ( x ) == SYMBOL_REF && XSTR ( x , 0 ) [ 0 ] == '.' && DEFAULT_ABI == ABI_AIX ) { const char * name = XSTR ( x , 0 ) ; while ( * name == '.' ) name ++ ; fprintf ( asm_out_file , "\t.long\t%s\n" , name ) ; return true ; } } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . The powerpc version has to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP is defined . It also needs to handle DI-mode objects on 64-bit targets .


<s> static void ix86_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; machine_mode mode = arg . mode ; HOST_WIDE_INT bytes , words ; int nregs ; if ( ! cum -> caller && cfun -> machine -> func_type != TYPE_NORMAL ) return ; bytes = arg . promoted_size_in_bytes ( ) ; words = CEIL ( bytes , UNITS_PER_WORD ) ; if ( arg . type ) mode = type_natural_mode ( arg . type , NULL , false ) ; if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) nregs = function_arg_advance_ms_64 ( cum , bytes , words ) ; else nregs = function_arg_advance_64 ( cum , mode , arg . type , words , arg . named ) ; } else nregs = function_arg_advance_32 ( cum , mode , arg . type , bytes , words ) ; if ( ! nregs ) { if ( cum -> caller ) cfun -> machine -> outgoing_args_on_stack = true ; } } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> void AArch64AsmPrinter :: emitFunctionBodyEnd ( ) { if ( ! AArch64FI -> getLOHRelated ( ) . empty ( ) ) EmitLOHs ( ) ; } </s>

Targets can override this to emit stuff after the last basic block in the function .


<s>
void
output_ascii
(
FILE
*
file
,
const
char
*
p
,
int
size
)
{
int
i
,
c
;
const
char
*
pseudo
=
"\t.ascii\t"
;
bool
delim
=
false
;
if
(
TARGET_DEC_ASM
)
{
if
(
p
[
size
1
]
==
'\0'
)
{
pseudo
=
"\t.asciz\t"
;
size
;
}
fputs
(
pseudo
,
file
)
;
for
(
i
=
0
;
i
<
size
;
i
++
)
{
c
=
*
p
++
&
0xff
;
if
(
c
<
32
||
c
==
'"'
||
c
>
126
)
{
if
(
delim
)
putc
(
'"'
,
file
)
;
fprintf
(
file
,
"<%o>"
,
c
)
;
delim
=
false
;
}
else
{
if
(
!
delim
)
putc
(
'"'
,
file
)
;
delim
=
true
;
putc
(
c
,
file
)
;
}
}
if
(
delim
)
putc
(
'"'
,
file
)
;
putc
(
'\n'
,
file
)
;
}
else
{
fprintf
(
file
,
"\t.byte "
)
;
for
(
i
=
0
;
i
<
size
;
i
++
)
{
fprintf
(
file
,
"%#o"
,
*
p
++
&
0xff
)
;
if
(
i
<
size
1
)
putc
(
','
,
file
)
;
}
putc
(
'\n'
,
file
)
;
}
}
</s>

Output an assembler pseudo-op to write an ASCII string of N characters starting at P to FILE . On the RS/6000 , we have to do this using the .byte operation and write out special characters outside the quoted string . Also , the assembler is broken ; very long strings are truncated , so we must artificially break them up early .


<s>
void
Cpu0DAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
LLVM_DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
if
(
trySelect
(
Node
)
)
return
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
ReplaceNode
(
Node
,
getGlobalBaseReg
(
)
)
;
return
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


"2003f DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> void ELFAArch64AsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { if ( ! IsLittleEndian && Fixup . getKind ( ) == FK_Data_4 ) { const MCSection * Sec = Fixup . getValue ( ) -> FindAssociatedSection ( ) ; const MCSectionELF * SecELF = static_cast < const MCSectionELF * > ( Sec ) ; if ( SecELF -> getSectionName ( ) == ".eh_frame" ) Value = ByteSwap_32 ( unsigned ( Value ) ) ; } AArch64AsmBackend :: applyFixup ( Fixup , Data , DataSize , Value , IsPCRel ) ; } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> MachineBasicBlock :: iterator X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { bool reserveCallFrame = hasReservedCallFrame ( MF ) ; unsigned Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t InternalAmt = ( isDestroy || Amount ) ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { unsigned StackAlign = getStackAlignment ( ) ; Amount = alignTo ( Amount , StackAlign ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const Function * Fn = MF . getFunction ( ) ; bool WindowsCFI = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool DwarfCFI = ! WindowsCFI && ( MMI . hasDebugInfo ( ) || Fn -> needsUnwindTableEntry ( ) ) ; bool HasDwarfEHHandlers = ! WindowsCFI && ! MF . getMMI ( ) . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < X86MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , I , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == 0 ) return I ; Amount -= InternalAmt ; if ( isDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) ) BuildCFI ( MBB , I , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ; int64_t StackAdjustment = isDestroy ? Amount : - Amount ; int64_t CfaAdjustment = - StackAdjustment ; if ( StackAdjustment ) { StackAdjustment += mergeSPUpdates ( MBB , I , true ) ; StackAdjustment += mergeSPUpdates ( MBB , I , false ) ; if ( StackAdjustment ) { if ( ! ( Fn -> optForMinSize ( ) && adjustStackWithPops ( MBB , I , DL , StackAdjustment ) ) ) BuildStackAdjustment ( MBB , I , DL , StackAdjustment , false ) ; } } if ( DwarfCFI && ! hasFP ( MF ) ) { if ( CfaAdjustment ) { BuildCFI ( MBB , I , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , CfaAdjustment ) ) ; } } return I ; } if ( isDestroy && InternalAmt ) { MachineBasicBlock :: iterator CI = I ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( CI != B && ! std :: prev ( CI ) -> isCall ( ) ) -- CI ; BuildStackAdjustment ( MBB , CI , DL , - InternalAmt , false ) ; } return I ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> aarch64_svpattern aarch64_svpattern_for_vl ( machine_mode pred_mode , int vl ) { if ( vl < 0 ) return AARCH64_SV_ALL ; if ( maybe_gt ( vl , GET_MODE_NUNITS ( pred_mode ) ) ) return AARCH64_NUM_SVPATTERNS ; if ( vl >= 1 && vl <= 8 ) return aarch64_svpattern ( AARCH64_SV_VL1 + ( vl - 1 ) ) ; if ( vl >= 16 && vl <= 256 && pow2p_hwi ( vl ) ) return aarch64_svpattern ( AARCH64_SV_VL16 + ( exact_log2 ( vl ) - 4 ) ) ; int max_vl ; if ( GET_MODE_NUNITS ( pred_mode ) . is_constant ( & max_vl ) ) { if ( vl == ( max_vl / 3 ) * 3 ) return AARCH64_SV_MUL3 ; if ( vl == ( max_vl & - 4 ) ) return AARCH64_SV_MUL4 ; if ( vl == ( 1 << floor_log2 ( max_vl ) ) ) return AARCH64_SV_POW2 ; if ( vl == max_vl ) return AARCH64_SV_ALL ; } return AARCH64_NUM_SVPATTERNS ; } </s>

See if there is an svpattern that encodes an SVE predicate of mode PRED_MODE in which the first VL bits are set and the rest are clear . Return the pattern if so , otherwise return AARCH64_NUM_SVPATTERNS . A VL of -1 indicates an all-true vector .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> void MipsRegisterInfo :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; bool isPIC = ( MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ; adjustMipsStackFrame ( MF ) ; unsigned StackSize = MFI -> getStackSize ( ) ; if ( StackSize == 0 && ! MFI -> adjustsStack ( ) ) return ; int FPOffset = MipsFI -> getFPStackOffset ( ) ; int RAOffset = MipsFI -> getRAStackOffset ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: NOREORDER ) ) ; if ( isPIC && Subtarget . isABI_O32 ( ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: CPLOAD ) ) . addReg ( getPICCallReg ( ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: NOMACRO ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDiu ) , Mips :: SP ) . addReg ( Mips :: SP ) . addImm ( - StackSize ) ; if ( MFI -> adjustsStack ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: SW ) ) . addReg ( Mips :: RA ) . addImm ( RAOffset ) . addReg ( Mips :: SP ) ; } if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: SW ) ) . addReg ( Mips :: FP ) . addImm ( FPOffset ) . addReg ( Mips :: SP ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDu ) , Mips :: FP ) . addReg ( Mips :: SP ) . addReg ( Mips :: ZERO ) ; } if ( MipsFI -> needGPSaveRestore ( ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: CPRESTORE ) ) . addImm ( MipsFI -> getGPStackOffset ( ) ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Mips Mips Mips Mips Mips Mips 0 Mips Mips Mips::NOREORDER Mips::CPLOAD Mips::NOMACRO Mips::ADDiu Mips::SP Mips::SP Mips::SW Mips::RA Mips::SP Mips::SW Mips::FP Mips::SP Mips::ADDu Mips::FP Mips::SP Mips::ZERO Mips Mips::CPRESTORE Mips


<s> static bool alpha_pass_by_reference ( cumulative_args_t ca ATTRIBUTE_UNUSED , machine_mode mode , const_tree type ATTRIBUTE_UNUSED , bool named ) { if ( mode == SFmode || mode == SCmode ) return ! named ; return mode == TFmode || mode == TCmode ; } </s>

Return true if TYPE should be passed by invisible reference .


<s> bool alpha_extra_constraint ( rtx value , int c ) { switch ( c ) { case 'Q' : return normal_memory_operand ( value , VOIDmode ) ; case 'R' : return direct_call_operand ( value , Pmode ) ; case 'S' : return ( GET_CODE ( value ) == CONST_INT && ( unsigned HOST_WIDE_INT ) INTVAL ( value ) < 64 ) ; case 'T' : return GET_CODE ( value ) == HIGH ; case 'U' : return TARGET_ABI_UNICOSMK && symbolic_operand ( value , VOIDmode ) ; case 'W' : return ( GET_CODE ( value ) == CONST_VECTOR && value == CONST0_RTX ( GET_MODE ( value ) ) ) ; default : return false ; } } </s>

Implements CONST_DOUBLE_OK_FOR_LETTER_P . Return true if VALUE matches for C .


<s> void MBlazeRegisterInfo :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MBlazeFunctionInfo * MBlazeFI = MF . getInfo < MBlazeFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = ( MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc :: getUnknownLoc ( ) ) ; adjustMBlazeStackFrame ( MF ) ; unsigned StackSize = MFI -> getStackSize ( ) ; if ( StackSize == 0 && ! MFI -> hasCalls ( ) ) return ; if ( StackSize < 28 && MFI -> hasCalls ( ) ) StackSize = 28 ; int FPOffset = MBlazeFI -> getFPStackOffset ( ) ; int RAOffset = MBlazeFI -> getRAStackOffset ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( MBlaze :: ADDI ) , MBlaze :: R1 ) . addReg ( MBlaze :: R1 ) . addImm ( - StackSize ) ; if ( MFI -> hasCalls ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( MBlaze :: SWI ) ) . addReg ( MBlaze :: R15 ) . addImm ( RAOffset ) . addReg ( MBlaze :: R1 ) ; } if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( MBlaze :: SWI ) ) . addReg ( MBlaze :: R19 ) . addImm ( FPOffset ) . addReg ( MBlaze :: R1 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( MBlaze :: ADD ) , MBlaze :: R19 ) . addReg ( MBlaze :: R1 ) . addReg ( MBlaze :: R0 ) ; } } </s>


<s> ArrayRef < const Metadata * > getNonMDStrings ( ) const { return makeArrayRef ( MDs ) . slice ( NumModuleMDs ) . slice ( NumMDStrings ) ; } </s>

Get the non-MDString metadata for this block .


<s> static bool insn_clobbers_hbr ( rtx_insn * insn ) { if ( INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == PARALLEL ) { rtx parallel = PATTERN ( insn ) ; rtx clobber ; int j ; for ( j = XVECLEN ( parallel , 0 ) - 1 ; j >= 0 ; j -- ) { clobber = XVECEXP ( parallel , 0 , j ) ; if ( GET_CODE ( clobber ) == CLOBBER && GET_CODE ( XEXP ( clobber , 0 ) ) == REG && REGNO ( XEXP ( clobber , 0 ) ) == HBR_REGNUM ) return 1 ; } } return 0 ; } </s>

The special $ hbr register is used to prevent the insn scheduler from moving hbr insns across instructions which invalidate them . It should only be used in a clobber , and this function searches for insns which clobber it .


<s> bool X86PassConfig :: addPreRegAlloc ( ) { PM -> add ( createX86MaxStackAlignmentHeuristicPass ( ) ) ; return false ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , int64_t NumBytes , bool Is64Bit , bool IsLP64 , bool UseLEA , const TargetInstrInfo & TII , const TargetRegisterInfo & TRI ) { bool isSub = NumBytes < 0 ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; unsigned Opc ; if ( UseLEA ) Opc = getLEArOpcode ( IsLP64 ) ; else Opc = isSub ? getSUBriOpcode ( IsLP64 , Offset ) : getADDriOpcode ( IsLP64 , Offset ) ; uint64_t Chunk = ( 1LL << 31 ) - 1 ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; if ( ThisVal == ( Is64Bit ? 8 : 4 ) ) { unsigned Reg = isSub ? ( unsigned ) ( Is64Bit ? X86 :: RAX : X86 :: EAX ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { Opc = isSub ? ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) : ( Is64Bit ? X86 :: POP64r : X86 :: POP32r ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ; if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; Offset -= ThisVal ; continue ; } } MachineInstr * MI = nullptr ; if ( UseLEA ) { MI = addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) , StackPtr , false , isSub ? - ThisVal : ThisVal ) ; } else { MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( ThisVal ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; } if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> void SystemZFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; if ( ! usePackedStack ( MF ) ) getOrCreateFramePointerSaveIndex ( MF ) ; uint64_t StackSize = ( MFFrame . estimateStackSize ( MF ) + SystemZMC :: CallFrameSize ) ; int64_t MaxArgOffset = 0 ; for ( int I = MFFrame . getObjectIndexBegin ( ) ; I != 0 ; ++ I ) if ( MFFrame . getObjectOffset ( I ) >= 0 ) { int64_t ArgOffset = MFFrame . getObjectOffset ( I ) + MFFrame . getObjectSize ( I ) ; MaxArgOffset = std :: max ( MaxArgOffset , ArgOffset ) ; } uint64_t MaxReach = StackSize + MaxArgOffset ; if ( ! isUInt < 12 > ( MaxReach ) ) { RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( 8 , 8 , false ) ) ; RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( 8 , 8 , false ) ) ; } } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


"Functions with 'no-prototype' attribute must take varargs: "

"Functions with 'no-prototype' attribute should not have params: "

"could not derive a function prototype from usage: "

"Prototypeless function used with conflicting signatures: "

"unexpected use of prototypeless function: "

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


"You cannot take the address of a nested function if you use "

Emit RTL insns to initialize the variable parts of a trampoline . FNADDR is an RTX for the address of the function 's pure code . CXT is an RTX for the static chain value for the function .


"Can only merge with a valid VSETVLInfo"


<s> static rtx visium_function_arg ( cumulative_args_t pcum_v , enum machine_mode mode , const_tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { int size ; CUMULATIVE_ARGS * ca = get_cumulative_args ( pcum_v ) ; size = ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; if ( mode == VOIDmode ) return GEN_INT ( 0 ) ; if ( TARGET_FPU && ( ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && GET_MODE_SIZE ( mode ) <= UNITS_PER_HWFPVALUE ) || ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT && GET_MODE_SIZE ( mode ) <= UNITS_PER_HWFPVALUE * 2 ) ) ) { if ( ca -> frcount + size <= MAX_ARGS_IN_FP_REGISTERS ) return gen_rtx_REG ( mode , FP_ARG_FIRST + ca -> frcount ) ; else return NULL_RTX ; } if ( ca -> grcount + size <= MAX_ARGS_IN_GP_REGISTERS ) return gen_rtx_REG ( mode , ca -> grcount + GP_ARG_FIRST ) ; return NULL_RTX ; } </s>

Define how arguments are passed . A range of general registers and floating registers is available for passing arguments . When the class of registers which an argument would normally use is exhausted , that argument , is passed in the overflow region of the stack . No argument is split between registers and stack . Arguments of type float or _Complex float go in FP registers if FP hardware is available . If there is no FP hardware , arguments of type float go in general registers . All other arguments are passed in general registers .


<s> MCELFStreamer & getStreamer ( ) { return static_cast < MCELFStreamer & > ( Streamer ) ; } </s>

Return the output streamer for the assembler .


"Load should return a value and a chain"

LowerOperation - Provide custom lowering hooks for some operations .


"Instr doesn't have FrameIndex operand!"

"Requesting 64-bit offset in 32-bit immediate!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


Return a string to perform a load_multiple operation . operands [ 0 ] is the vector . operands [ 1 ] is the source address . operands [ 2 ] is the first destination register .


<s> bool PPCTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , const Type * Ty ) const { if ( AM . BaseOffs <= - ( 1LL << 16 ) || AM . BaseOffs >= ( 1LL << 16 ) - 1 ) return false ; if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( AM . HasBaseReg && AM . BaseOffs ) return false ; break ; case 2 : if ( AM . HasBaseReg || AM . BaseOffs ) return false ; break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> static void replace_swapped_aligned_store ( swap_web_entry * insn_entry , rtx_insn * store_insn ) { unsigned uid = INSN_UID ( store_insn ) ; gcc_assert ( insn_entry [ uid ] . is_swap && insn_entry [ uid ] . is_store ) ; rtx body = PATTERN ( store_insn ) ; rtx dest_address = XEXP ( SET_DEST ( body ) , 0 ) ; rtx swap_reg = XEXP ( SET_SRC ( body ) , 0 ) ; gcc_assert ( REG_P ( dest_address ) || rs6000_sum_of_two_registers_p ( dest_address ) ) ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( store_insn ) ; df_ref use ; rtx_insn * swap_insn = NULL ; unsigned uid2 = 0 ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( ! rtx_equal_p ( DF_REF_REG ( use ) , swap_reg ) ) continue ; gcc_assert ( def_link && def_link -> ref && ! def_link -> next && ! DF_REF_IS_ARTIFICIAL ( def_link -> ref ) ) ; swap_insn = DF_REF_INSN ( def_link -> ref ) ; uid2 = INSN_UID ( swap_insn ) ; gcc_assert ( insn_entry [ uid2 ] . is_swap && ! insn_entry [ uid2 ] . is_load && ! insn_entry [ uid2 ] . is_store ) ; break ; } gcc_assert ( swap_insn ) ; rtx set = single_set ( store_insn ) ; gcc_assert ( set ) ; rtx dest_exp = SET_DEST ( set ) ; rtx src_exp = XEXP ( SET_SRC ( body ) , 0 ) ; enum machine_mode mode = GET_MODE ( dest_exp ) ; gcc_assert ( MEM_P ( dest_exp ) ) ; gcc_assert ( MEM_ALIGN ( dest_exp ) >= 128 ) ; rtx stvx ; stvx = rs6000_gen_stvx ( mode , dest_exp , src_exp ) ; rtx_insn * new_insn = emit_insn_before ( stvx , store_insn ) ; rtx new_body = PATTERN ( new_insn ) ; gcc_assert ( ( GET_CODE ( new_body ) == SET ) && MEM_P ( SET_DEST ( new_body ) ) ) ; set_block_for_insn ( new_insn , BLOCK_FOR_INSN ( store_insn ) ) ; df_insn_rescan ( new_insn ) ; df_insn_delete ( store_insn ) ; remove_insn ( store_insn ) ; store_insn -> set_deleted ( ) ; uid2 = INSN_UID ( swap_insn ) ; mark_swaps_for_removal ( insn_entry , uid2 ) ; replace_swap_with_copy ( insn_entry , uid2 ) ; } </s>

Given that STORE_INSN represents an aligned store-with-swap of a swapped value , replace the store with an aligned store ( without swap ) and replace the swap with a copy insn .


<s> const TargetFrameLowering :: SpillSlot * SystemZFrameLowering :: getCalleeSavedSpillSlots ( unsigned & NumEntries ) const { NumEntries = array_lengthof ( SpillOffsetTable ) ; return SpillOffsetTable ; } </s>

getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs , that contains an entry for each callee saved register that must be spilled to a particular stack location if it is spilled .


<s> bool PPCAsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { std :: string NewOpcode ; if ( getLexer ( ) . is ( AsmToken :: Plus ) ) { getLexer ( ) . Lex ( ) ; NewOpcode = Name ; NewOpcode += '+' ; Name = NewOpcode ; } if ( getLexer ( ) . is ( AsmToken :: Minus ) ) { getLexer ( ) . Lex ( ) ; NewOpcode = Name ; NewOpcode += '-' ; Name = NewOpcode ; } size_t Dot = Name . find ( '.' ) ; StringRef Mnemonic = Name . slice ( 0 , Dot ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( PPCOperand :: CreateTokenWithStringCopy ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; else Operands . push_back ( PPCOperand :: CreateToken ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; if ( Dot != StringRef :: npos ) { SMLoc DotLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Dot ) ; StringRef DotStr = Name . slice ( Dot , StringRef :: npos ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( PPCOperand :: CreateTokenWithStringCopy ( DotStr , DotLoc , isPPC64 ( ) ) ) ; else Operands . push_back ( PPCOperand :: CreateToken ( DotStr , DotLoc , isPPC64 ( ) ) ) ; } if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( ParseOperand ( Operands ) ) return true ; while ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) && getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( ParseOperand ( Operands ) ) return true ; } if ( STI . getFeatureBits ( ) [ PPC :: FeatureBookE ] && Operands . size ( ) == 4 && ( Name == "dcbt" || Name == "dcbtst" ) ) { std :: swap ( Operands [ 1 ] , Operands [ 3 ] ) ; std :: swap ( Operands [ 2 ] , Operands [ 1 ] ) ; } return false ; } </s>

ParseInstruction - Parse one assembly instruction .

PowerPC PPC 0 PPC PPC PPC PPC PPC PPC PPC PPC PPC::FeatureBookE 4 "dcbt" "dcbtst" 1 3 2 1


<s>
unsigned
getMaxNumElements
(
ElementCount
VF
)
const
{
if
(
!
VF
.
isScalable
(
)
)
return
VF
.
getFixedValue
(
)
;
Optional
<
unsigned
>
MaxNumVScale
=
getMaxVScale
(
)
;
assert
(
MaxNumVScale
&&
"Expected valid max vscale value"
)
;
return
*
MaxNumVScale
*
VF
.
getKnownMinValue
(
)
;
}
</s>

Try to return an estimate cost factor that can be used as a multiplier when scalarizing an operation for a vector with ElementCount VF .


<s> bool R600InstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , unsigned ExtraPredCycles , BranchProbability Probability ) const { return true ; } </s>


<s> bool sh_expand_strlen ( rtx * operands ) { rtx addr1 = operands [ 1 ] ; rtx current_addr = copy_addr_to_reg ( XEXP ( addr1 , 0 ) ) ; rtx start_addr = gen_reg_rtx ( Pmode ) ; rtx tmp0 = gen_reg_rtx ( SImode ) ; rtx tmp1 = gen_reg_rtx ( SImode ) ; rtx_code_label * L_return = gen_label_rtx ( ) ; rtx_code_label * L_loop_byte = gen_label_rtx ( ) ; rtx jump ; rtx_code_label * L_loop_long = gen_label_rtx ( ) ; rtx_code_label * L_end_loop_long = gen_label_rtx ( ) ; int align = INTVAL ( operands [ 3 ] ) ; emit_move_insn ( operands [ 0 ] , GEN_INT ( - 1 ) ) ; emit_move_insn ( start_addr , current_addr ) ; if ( align < 4 ) { emit_insn ( gen_tstsi_t ( current_addr , GEN_INT ( 3 ) ) ) ; jump = emit_jump_insn ( gen_branch_false ( L_loop_byte ) ) ; add_int_reg_note ( jump , REG_BR_PROB , prob_likely ) ; } emit_move_insn ( tmp0 , operands [ 2 ] ) ; addr1 = adjust_automodify_address ( addr1 , SImode , current_addr , 0 ) ; emit_label ( L_loop_long ) ; emit_move_insn ( tmp1 , addr1 ) ; emit_move_insn ( current_addr , plus_constant ( Pmode , current_addr , 4 ) ) ; emit_insn ( gen_cmpstr_t ( tmp0 , tmp1 ) ) ; jump = emit_jump_insn ( gen_branch_false ( L_loop_long ) ) ; add_int_reg_note ( jump , REG_BR_PROB , prob_likely ) ; emit_label ( L_end_loop_long ) ; emit_move_insn ( current_addr , plus_constant ( Pmode , current_addr , - 4 ) ) ; addr1 = adjust_address ( addr1 , QImode , 0 ) ; for ( int i = 0 ; i < 4 ; ++ i ) { emit_insn ( gen_extendqisi2 ( tmp1 , addr1 ) ) ; emit_move_insn ( current_addr , plus_constant ( Pmode , current_addr , 1 ) ) ; emit_insn ( gen_cmpeqsi_t ( tmp1 , const0_rtx ) ) ; jump = emit_jump_insn ( gen_branch_true ( L_return ) ) ; add_int_reg_note ( jump , REG_BR_PROB , prob_likely ) ; } emit_barrier_after ( jump ) ; emit_label ( L_loop_byte ) ; emit_insn ( gen_extendqisi2 ( tmp1 , addr1 ) ) ; emit_move_insn ( current_addr , plus_constant ( Pmode , current_addr , 1 ) ) ; emit_insn ( gen_cmpeqsi_t ( tmp1 , const0_rtx ) ) ; jump = emit_jump_insn ( gen_branch_false ( L_loop_byte ) ) ; add_int_reg_note ( jump , REG_BR_PROB , prob_likely ) ; emit_label ( L_return ) ; emit_insn ( gen_addsi3 ( start_addr , start_addr , GEN_INT ( 1 ) ) ) ; emit_insn ( gen_subsi3 ( operands [ 0 ] , current_addr , start_addr ) ) ; return true ; } </s>

Emit code to perform a strlen . OPERANDS [ 0 ] is the destination . OPERANDS [ 1 ] is the string . OPERANDS [ 2 ] is the char to search . OPERANDS [ 3 ] is the alignment .


<s> void Z80AsmPrinter :: emitInlineAsmEnd ( const MCSubtargetInfo & StartInfo , const MCSubtargetInfo * EndInfo ) const { return ; if ( TM . getTargetTriple ( ) . getArch ( ) != Triple :: ez80 ) { return ; } bool Was16 = isCode16 ( StartInfo . getTargetTriple ( ) ) ; if ( ! EndInfo || Was16 != isCode16 ( EndInfo -> getTargetTriple ( ) ) ) { OutStreamer -> EmitAssemblerFlag ( Was16 ? MCAF_Code16 : MCAF_Code24 ) ; } } </s>

Let the target do anything it needs to do after emitting inlineasm .


<s> unsigned RISCVInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : { return get ( Opcode ) . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return 0 ; case RISCV :: PseudoCALL : case RISCV :: PseudoTAIL : case RISCV :: PseudoLLA : case RISCV :: PseudoLA : case RISCV :: PseudoLA_TLS_IE : case RISCV :: PseudoLA_TLS_GD : return 8 ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const auto & TM = static_cast < const RISCVTargetMachine & > ( MF . getTarget ( ) ) ; return getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> MachineBasicBlock :: iterator Cpu0FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static void rs6000_emit_vector_select ( rtx dest , rtx op1 , rtx op2 , rtx mask ) { rtx t , temp ; enum machine_mode dest_mode = GET_MODE ( dest ) ; int vsel_insn_index = get_vsel_insn ( GET_MODE ( dest ) ) ; temp = gen_reg_rtx ( dest_mode ) ; t = gen_rtx_SET ( VOIDmode , temp , gen_rtx_UNSPEC ( dest_mode , gen_rtvec ( 3 , op2 , op1 , mask ) , vsel_insn_index ) ) ; emit_insn ( t ) ; emit_move_insn ( dest , temp ) ; return ; } </s>

Emit vector select insn where DEST is destination using operands OP1 , OP2 and MASK .


<s> const SIRegisterInfo & SIInstrInfo :: getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> const TargetRegisterClass * MandarinRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & MD :: GenericRegsRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s>
MachineBasicBlock
*
OR1KTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unexpected instr type to insert"
)
;
case
OR1K
::
Select
:
case
OR1K
::
Selectf32
:
return
emitSelect
(
MI
,
BB
)
;
case
OR1K
::
ATOMIC_LOAD_ADD_I32
:
return
emitAtomicBinary
(
MI
,
BB
,
OR1K
::
ADD
)
;
case
OR1K
::
ATOMIC_LOAD_AND_I32
:
return
emitAtomicBinary
(
MI
,
BB
,
OR1K
::
AND
)
;
case
OR1K
::
ATOMIC_LOAD_OR_I32
:
return
emitAtomicBinary
(
MI
,
BB
,
OR1K
::
OR
)
;
case
OR1K
::
ATOMIC_LOAD_XOR_I32
:
return
emitAtomicBinary
(
MI
,
BB
,
OR1K
::
XOR
)
;
case
OR1K
::
ATOMIC_LOAD_NAND_I32
:
return
emitAtomicBinary
(
MI
,
BB
,
0
,
true
)
;
case
OR1K
::
ATOMIC_LOAD_SUB_I32
:
return
emitAtomicBinary
(
MI
,
BB
,
OR1K
::
SUB
)
;
case
OR1K
::
ATOMIC_SWAP_I32
:
return
emitAtomicBinary
(
MI
,
BB
,
0
)
;
case
OR1K
::
ATOMIC_CMP_SWAP_I32
:
return
emitAtomicCmpSwap
(
MI
,
BB
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> int NVPTXTTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: TargetCostKind CostKind , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args , const Instruction * CxtI ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: ADD : case ISD :: MUL : case ISD :: XOR : case ISD :: OR : case ISD :: AND : if ( LT . second . SimpleTy == MVT :: i64 ) return 2 * LT . first ; return BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .

NVPTX NVPTX ISD::ADD ISD::MUL ISD::XOR ISD::OR ISD::AND MVT::i64 2


<s> bool X86TargetLowering :: isVectorClearMaskLegal ( const SmallVectorImpl < int > & Mask , MVT VT ) const { unsigned NumElts = VT . getVectorNumElements ( ) ; if ( NumElts == 2 ) return true ; if ( NumElts == 4 && VT . getSizeInBits ( ) == 128 ) { return ( isMOVLMask ( Mask , VT ) || isCommutedMOVLMask ( Mask , VT , true ) || isSHUFPMask ( Mask , VT ) || isCommutedSHUFPMask ( Mask , VT ) ) ; } return false ; } </s>


"RISC-V backend can't currently handle functions that need stack "

"realignment and have variable sized objects"

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> LoongArchSubtarget & LoongArchSubtarget :: initializeSubtargetDependencies ( const Triple & TT , StringRef CPU , StringRef TuneCPU , StringRef FS , StringRef ABIName ) { bool Is64Bit = TT . isArch64Bit ( ) ; if ( CPU . empty ( ) ) CPU = Is64Bit ? "generic-la64" : "generic-la32" ; if ( TuneCPU . empty ( ) ) TuneCPU = CPU ; ParseSubtargetFeatures ( CPU , TuneCPU , FS ) ; if ( Is64Bit ) { GRLenVT = MVT :: i64 ; GRLen = 64 ; } TargetABI = Is64Bit ? LoongArchABI :: ABI_LP64D : LoongArchABI :: ABI_ILP32D ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> void MBlazeRegisterInfo :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MBlazeFunctionInfo * MBlazeFI = MF . getInfo < MBlazeFunctionInfo > ( ) ; if ( MBlazeFI -> needGPSaveRestore ( ) ) MFI -> setObjectOffset ( MBlazeFI -> getGPFI ( ) , MBlazeFI -> getGPStackOffset ( ) ) ; } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .

MBlaze MBlaze MBlaze MBlaze MBlaze MBlaze MBlaze MBlaze


<s>
void
BTFDebug
::
beginFunctionImpl
(
const
MachineFunction
*
MF
)
{
auto
*
SP
=
MF
->
getFunction
(
)
.
getSubprogram
(
)
;
auto
*
Unit
=
SP
->
getUnit
(
)
;
if
(
Unit
->
getEmissionKind
(
)
==
DICompileUnit
::
NoDebug
)
{
SkipInstruction
=
true
;
return
;
}
SkipInstruction
=
false
;
if
(
MapDefNotCollected
)
{
processGlobals
(
true
)
;
MapDefNotCollected
=
false
;
}
std
::
unordered_map
<
uint32_t
,
StringRef
>
FuncArgNames
;
for
(
const
DINode
*
DN
:
SP
->
getRetainedNodes
(
)
)
{
if
(
const
auto
*
DV
=
dyn_cast
<
DILocalVariable
>
(
DN
)
)
{
uint32_t
Arg
=
DV
->
getArg
(
)
;
if
(
Arg
)
{
visitTypeEntry
(
DV
->
getType
(
)
)
;
FuncArgNames
[
Arg
]
=
DV
->
getName
(
)
;
}
}
}
uint32_t
ProtoTypeId
;
visitSubroutineType
(
SP
->
getType
(
)
,
true
,
FuncArgNames
,
ProtoTypeId
)
;
uint8_t
Scope
=
SP
->
isLocalToUnit
(
)
BTF
::
FUNC_STATIC
:
BTF
::
FUNC_GLOBAL
;
auto
FuncTypeEntry
=
std
::
make_unique
<
BTFTypeFunc
>
(
SP
->
getName
(
)
,
ProtoTypeId
,
Scope
)
;
uint32_t
FuncTypeId
=
addType
(
std
::
move
(
FuncTypeEntry
)
)
;
for
(
const
DINode
*
DN
:
SP
->
getRetainedNodes
(
)
)
{
if
(
const
auto
*
DV
=
dyn_cast
<
DILocalVariable
>
(
DN
)
)
{
uint32_t
Arg
=
DV
->
getArg
(
)
;
if
(
Arg
)
processAnnotations
(
DV
->
getAnnotations
(
)
,
FuncTypeId
,
Arg
1
)
;
}
}
processAnnotations
(
SP
->
getAnnotations
(
)
,
FuncTypeId
,
1
)
;
for
(
const
auto
&
TypeEntry
:
TypeEntries
)
TypeEntry
->
completeType
(
*
this
)
;
MCSymbol
*
FuncLabel
=
Asm
->
getFunctionBegin
(
)
;
BTFFuncInfo
FuncInfo
;
FuncInfo
.
Label
=
FuncLabel
;
FuncInfo
.
TypeId
=
FuncTypeId
;
if
(
FuncLabel
->
isInSection
(
)
)
{
MCSection
&
Section
=
FuncLabel
->
getSection
(
)
;
const
MCSectionELF
*
SectionELF
=
dyn_cast
<
MCSectionELF
>
(
&
Section
)
;
assert
(
SectionELF
&&
"Null section for Function Label"
)
;
SecNameOff
=
addString
(
SectionELF
->
getName
(
)
)
;
}
else
{
SecNameOff
=
addString
(
".text"
)
;
}
FuncInfoTable
[
SecNameOff
]
.
push_back
(
FuncInfo
)
;
}
</s>


"sh_find_extending_set_of_reg: reg %d is "

"explicitly sign/zero extended in insn %d\n"

Given a reg and the current insn , see if the value of the reg originated from a sign or zero extension and return the discovered information .


"Pseudo flag setting opcodes only exist in Selection DAG"

"Non-flag-setting Thumb1 mov is v6-only"

"Unsupported register in Thumb1 push/pop"

"Incorrect array index for MVE_VMOV_q_rr"

Perform target-specific instruction verification .


<s> static void alpha_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; bool onstack = targetm . calls . must_pass_in_stack ( mode , type ) ; int increment = onstack ? 6 : ALPHA_ARG_SIZE ( mode , type , named ) ; * cum += increment ; if ( ! onstack && cum -> num_args < 6 ) cum -> atypes [ cum -> num_args ] = alpha_arg_type ( mode ) ; cum -> num_args += increment ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> static inline int addsubcosts ( rtx x ) { if ( GET_MODE ( x ) == SImode ) { rtx op0 = XEXP ( x , 0 ) ; rtx op1 = XEXP ( x , 1 ) ; if ( GET_CODE ( x ) == PLUS ) { if ( GET_CODE ( op0 ) == AND && XEXP ( op0 , 1 ) == const1_rtx && ( GET_CODE ( op1 ) == PLUS || ( GET_CODE ( op1 ) == MULT && XEXP ( op1 , 1 ) == const2_rtx ) ) ) return 1 ; if ( GET_CODE ( op0 ) == MULT && XEXP ( op0 , 1 ) == const2_rtx && GET_CODE ( op1 ) == LSHIFTRT && CONST_INT_P ( XEXP ( op1 , 1 ) ) && INTVAL ( XEXP ( op1 , 1 ) ) == 31 ) return 1 ; } if ( treg_set_expr ( op1 , SImode ) ) return 1 ; if ( treg_set_expr ( op0 , SImode ) ) return 1 ; } const int cost_scale = ! TARGET_SHMEDIA && GET_MODE_SIZE ( GET_MODE ( x ) ) > UNITS_PER_WORD ? 2 : 1 ; if ( REG_P ( XEXP ( x , 1 ) ) || GET_CODE ( XEXP ( x , 1 ) ) == SUBREG ) return 1 * cost_scale ; if ( CONST_INT_P ( XEXP ( x , 1 ) ) && CONST_OK_FOR_ADD ( INTVAL ( XEXP ( x , 1 ) ) ) ) return 1 * cost_scale ; if ( TARGET_SHMEDIA ) switch ( GET_CODE ( XEXP ( x , 1 ) ) ) { case CONST : case LABEL_REF : case SYMBOL_REF : return TARGET_SHMEDIA64 ? 5 : 3 ; case CONST_INT : if ( CONST_OK_FOR_I16 ( INTVAL ( XEXP ( x , 1 ) ) ) ) return 2 ; else if ( CONST_OK_FOR_I16 ( INTVAL ( XEXP ( x , 1 ) ) >> 16 ) ) return 3 ; else if ( CONST_OK_FOR_I16 ( ( INTVAL ( XEXP ( x , 1 ) ) >> 16 ) >> 16 ) ) return 4 ; default : return 5 ; } return 3 * cost_scale ; } </s>

Return the cost of an addition or a subtraction .


<s> static rtx ix86_expand_sse_cmp ( rtx dest , enum rtx_code code , rtx cmp_op0 , rtx cmp_op1 , rtx op_true , rtx op_false ) { machine_mode mode = GET_MODE ( dest ) ; machine_mode cmp_ops_mode = GET_MODE ( cmp_op0 ) ; machine_mode cmp_mode ; bool maskcmp = false ; rtx x ; if ( GET_MODE_SIZE ( cmp_ops_mode ) == 64 ) { unsigned int nbits = GET_MODE_NUNITS ( cmp_ops_mode ) ; cmp_mode = int_mode_for_size ( nbits , 0 ) . require ( ) ; maskcmp = true ; } else cmp_mode = cmp_ops_mode ; cmp_op0 = force_reg ( cmp_ops_mode , cmp_op0 ) ; int ( * op1_predicate ) ( rtx , machine_mode ) = VECTOR_MODE_P ( cmp_ops_mode ) ? vector_operand : nonimmediate_operand ; if ( ! op1_predicate ( cmp_op1 , cmp_ops_mode ) ) cmp_op1 = force_reg ( cmp_ops_mode , cmp_op1 ) ; if ( optimize || ( maskcmp && cmp_mode != mode ) || ( op_true && reg_overlap_mentioned_p ( dest , op_true ) ) || ( op_false && reg_overlap_mentioned_p ( dest , op_false ) ) ) dest = gen_reg_rtx ( maskcmp ? cmp_mode : mode ) ; if ( maskcmp && ( code == GT || code == EQ ) ) { rtx ( * gen ) ( rtx , rtx , rtx ) ; switch ( cmp_ops_mode ) { case E_V64QImode : gcc_assert ( TARGET_AVX512BW ) ; gen = code == GT ? gen_avx512bw_gtv64qi3 : gen_avx512bw_eqv64qi3_1 ; break ; case E_V32HImode : gcc_assert ( TARGET_AVX512BW ) ; gen = code == GT ? gen_avx512bw_gtv32hi3 : gen_avx512bw_eqv32hi3_1 ; break ; case E_V16SImode : gen = code == GT ? gen_avx512f_gtv16si3 : gen_avx512f_eqv16si3_1 ; break ; case E_V8DImode : gen = code == GT ? gen_avx512f_gtv8di3 : gen_avx512f_eqv8di3_1 ; break ; default : gen = NULL ; } if ( gen ) { emit_insn ( gen ( dest , cmp_op0 , cmp_op1 ) ) ; return dest ; } } x = gen_rtx_fmt_ee ( code , cmp_mode , cmp_op0 , cmp_op1 ) ; if ( cmp_mode != mode && ! maskcmp ) { x = force_reg ( cmp_ops_mode , x ) ; convert_move ( dest , x , false ) ; } else emit_insn ( gen_rtx_SET ( dest , x ) ) ; return dest ; } </s>

Expand an sse vector comparison . Return the register with the result .


"Checking if value is in small-data, -G"

Return true if this global address should be placed into small data/bss section .


<s> void h8300_expand_prologue ( void ) { int regno ; int saved_regs ; int n_regs ; if ( h8300_os_task_function_p ( current_function_decl ) ) return ; if ( h8300_monitor_function_p ( current_function_decl ) ) emit_insn ( gen_monitor_prologue ( ) ) ; if ( frame_pointer_needed ) { push ( HARD_FRAME_POINTER_REGNUM , true ) ; F ( emit_move_insn ( hard_frame_pointer_rtx , stack_pointer_rtx ) , true ) ; } saved_regs = compute_saved_regs ( ) ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno += n_regs ) { n_regs = 1 ; if ( saved_regs & ( 1 << regno ) ) { if ( TARGET_H8300S ) { if ( ( ! TARGET_H8300SX || ( regno & 3 ) == 0 ) && ( ( saved_regs >> regno ) & 0x0f ) == 0x0f ) n_regs = 4 ; else if ( ( ! TARGET_H8300SX || ( regno & 3 ) == 0 ) && ( ( saved_regs >> regno ) & 0x07 ) == 0x07 ) n_regs = 3 ; else if ( ( ! TARGET_H8300SX || ( regno & 1 ) == 0 ) && ( ( saved_regs >> regno ) & 0x03 ) == 0x03 ) n_regs = 2 ; } h8300_push_pop ( regno , n_regs , false , false ) ; } } h8300_emit_stack_adjustment ( - 1 , round_frame_size ( get_frame_size ( ) ) , true ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = round_frame_size ( get_frame_size ( ) ) + ( __builtin_popcount ( saved_regs ) * UNITS_PER_WORD ) + ( frame_pointer_needed ? UNITS_PER_WORD : 0 ) ; } </s>

Generate RTL code for the function prologue .


<s>
StringRef
getPassName
(
)
const
override
{
return
"SI Fold Operands"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> static const MachineOperand & getLdStBaseOp ( const MachineInstr * MI ) { unsigned Idx = isPairedLdSt ( MI ) ? 2 : 1 ; return MI -> getOperand ( Idx ) ; } </s>

Returns the base register operator of a load/store .


<s> static void mips_get_arg_info ( struct mips_arg_info * info , const CUMULATIVE_ARGS * cum , machine_mode mode , const_tree type , bool named ) { bool doubleword_aligned_p ; unsigned int num_bytes , num_words , max_regs ; num_bytes = type ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ; num_words = ( num_bytes + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; switch ( mips_abi ) { case ABI_EABI : info -> fpr_p = ( ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || mode == V2SFmode ) && GET_MODE_SIZE ( mode ) <= UNITS_PER_FPVALUE ) ; break ; case ABI_32 : case ABI_O64 : gcc_assert ( TARGET_PAIRED_SINGLE_FLOAT || mode != V2SFmode ) ; info -> fpr_p = ( ! cum -> gp_reg_found && cum -> arg_number < 2 && ( type == 0 || SCALAR_FLOAT_TYPE_P ( type ) || VECTOR_FLOAT_TYPE_P ( type ) ) && ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || mode == V2SFmode ) && GET_MODE_SIZE ( mode ) <= UNITS_PER_FPVALUE ) ; break ; case ABI_N32 : case ABI_64 : gcc_assert ( TARGET_PAIRED_SINGLE_FLOAT || mode != V2SFmode ) ; info -> fpr_p = ( named && ( type == 0 || FLOAT_TYPE_P ( type ) ) && ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT || mode == V2SFmode ) && GET_MODE_UNIT_SIZE ( mode ) <= UNITS_PER_FPVALUE ) ; if ( info -> fpr_p && GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT && GET_MODE_UNIT_SIZE ( mode ) < UNITS_PER_FPVALUE ) { if ( cum -> num_gprs >= MAX_ARGS_IN_REGISTERS - 1 ) info -> fpr_p = false ; else num_words = 2 ; } break ; default : gcc_unreachable ( ) ; } doubleword_aligned_p = ( mips_function_arg_boundary ( mode , type ) > BITS_PER_WORD ) ; info -> reg_offset = ( mips_abi == ABI_EABI && info -> fpr_p ? cum -> num_fprs : cum -> num_gprs ) ; if ( doubleword_aligned_p ) info -> reg_offset += info -> reg_offset & 1 ; info -> stack_offset = cum -> stack_words ; if ( doubleword_aligned_p ) info -> stack_offset += info -> stack_offset & 1 ; max_regs = MAX_ARGS_IN_REGISTERS - info -> reg_offset ; info -> reg_words = MIN ( num_words , max_regs ) ; info -> stack_words = num_words - info -> reg_words ; } </s>

Fill INFO with information about a single argument . CUM is the cumulative state for earlier arguments . MODE is the mode of this argument and TYPE is its type ( if known ) . NAMED is true if this is a named ( fixed ) argument rather than a variable one .


<s> void M68kFrameLowering :: BuildCFI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , const MCCFIInstruction & CFIInst ) const { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CFIIndex = MF . addFrameInst ( CFIInst ) ; BuildMI ( MBB , MBBI , DL , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } </s>

Wraps up getting a CFI index and building a MachineInstr for it .


<s> TargetPassConfig * LoongArchTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new LoongArchPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s>
bool
AMDGPULegalizerInfo
::
legalizeCustom
(
MachineInstr
&
MI
,
MachineRegisterInfo
&
MRI
,
MachineIRBuilder
&
B
,
GISelChangeObserver
&
Observer
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
case
TargetOpcode
::
G_ADDRSPACE_CAST
:
return
legalizeAddrSpaceCast
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FRINT
:
return
legalizeFrint
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FCEIL
:
return
legalizeFceil
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_INTRINSIC_TRUNC
:
return
legalizeIntrinsicTrunc
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_SITOFP
:
return
legalizeITOFP
(
MI
,
MRI
,
B
,
true
)
;
case
TargetOpcode
::
G_UITOFP
:
return
legalizeITOFP
(
MI
,
MRI
,
B
,
false
)
;
case
TargetOpcode
::
G_FPTOSI
:
return
legalizeFPTOI
(
MI
,
MRI
,
B
,
true
)
;
case
TargetOpcode
::
G_FPTOUI
:
return
legalizeFPTOI
(
MI
,
MRI
,
B
,
false
)
;
case
TargetOpcode
::
G_FMINNUM
:
case
TargetOpcode
::
G_FMAXNUM
:
case
TargetOpcode
::
G_FMINNUM_IEEE
:
case
TargetOpcode
::
G_FMAXNUM_IEEE
:
return
legalizeMinNumMaxNum
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_EXTRACT_VECTOR_ELT
:
return
legalizeExtractVectorElt
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_INSERT_VECTOR_ELT
:
return
legalizeInsertVectorElt
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_SHUFFLE_VECTOR
:
return
legalizeShuffleVector
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FSIN
:
case
TargetOpcode
::
G_FCOS
:
return
legalizeSinCos
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_GLOBAL_VALUE
:
return
legalizeGlobalValue
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_LOAD
:
return
legalizeLoad
(
MI
,
MRI
,
B
,
Observer
)
;
case
TargetOpcode
::
G_FMAD
:
return
legalizeFMad
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FDIV
:
return
legalizeFDIV
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_UDIV
:
case
TargetOpcode
::
G_UREM
:
return
legalizeUDIV_UREM
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_SDIV
:
case
TargetOpcode
::
G_SREM
:
return
legalizeSDIV_SREM
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_ATOMIC_CMPXCHG
:
return
legalizeAtomicCmpXChg
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FLOG
:
return
legalizeFlog
(
MI
,
B
,
numbers
::
ln2f
)
;
case
TargetOpcode
::
G_FLOG10
:
return
legalizeFlog
(
MI
,
B
,
numbers
::
ln2f
/
numbers
::
ln10f
)
;
case
TargetOpcode
::
G_FEXP
:
return
legalizeFExp
(
MI
,
B
)
;
case
TargetOpcode
::
G_FPOW
:
return
legalizeFPow
(
MI
,
B
)
;
case
TargetOpcode
::
G_FFLOOR
:
return
legalizeFFloor
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_BUILD_VECTOR
:
return
legalizeBuildVector
(
MI
,
MRI
,
B
)
;
default
:
return
false
;
}
llvm_unreachable
(
"expected switch to return"
)
;
}
</s>

Called for instructions with the Custom LegalizationAction .

AMDGPU
AMDGPU
SI
SI
SI
SI
"expected switch to return"