<s> static const char * avr_asm_len ( const char * tpl , rtx * operands , int * plen , int n_words ) { if ( plen == NULL ) output_asm_insn ( tpl , operands ) ; else { if ( n_words < 0 ) * plen = - n_words ; else * plen += n_words ; } return "" ; } </s>

Helper function to print assembler resp . track instruction sequence lengths . Always return `` '' . If PLEN == NULL : Output assembler code from template TPL with operands supplied by OPERANDS . This is just forwarding to output_asm_insn . If PLEN ! = NULL : If N_WORDS > = 0 Add N_WORDS to * PLEN . If N_WORDS < 0 Set * PLEN to -N_WORDS . Do n't output anything .


<s> const SystemZRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


"should only be seeing stack pointer offset relative FrameIndex"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> bool GCNPassConfig :: addPreISel ( ) { AMDGPUPassConfig :: addPreISel ( ) ; addPass ( createAMDGPUAnnotateKernelFeaturesPass ( ) ) ; addPass ( & AMDGPUUnifyDivergentExitNodesID ) ; if ( ! LateCFGStructurize ) { addPass ( createStructurizeCFGPass ( true ) ) ; } addPass ( createSinkingPass ( ) ) ; addPass ( createSITypeRewriter ( ) ) ; addPass ( createAMDGPUAnnotateUniformValues ( ) ) ; if ( ! LateCFGStructurize ) { addPass ( createSIAnnotateControlFlowPass ( ) ) ; } return false ; } </s>

AMDGPU AMDGPU AMDGPU AMDGPU SI AMDGPU SI


<s> X86Subtarget :: X86Subtarget ( const Triple & TT , StringRef CPU , StringRef TuneCPU , StringRef FS , const X86TargetMachine & TM , MaybeAlign StackAlignOverride , unsigned PreferVectorWidthOverride , unsigned RequiredVectorWidth ) : X86GenSubtargetInfo ( TT , CPU , TuneCPU , FS ) , PICStyle ( PICStyles :: Style :: None ) , TM ( TM ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , PreferVectorWidthOverride ( PreferVectorWidthOverride ) , RequiredVectorWidth ( RequiredVectorWidth ) , InstrInfo ( initializeSubtargetDependencies ( CPU , TuneCPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( * this , getStackAlignment ( ) ) { if ( ! isPositionIndependent ( ) ) setPICStyle ( PICStyles :: Style :: None ) ; else if ( is64Bit ( ) ) setPICStyle ( PICStyles :: Style :: RIPRel ) ; else if ( isTargetCOFF ( ) ) setPICStyle ( PICStyles :: Style :: None ) ; else if ( isTargetDarwin ( ) ) setPICStyle ( PICStyles :: Style :: StubPIC ) ; else if ( isTargetELF ( ) ) setPICStyle ( PICStyles :: Style :: GOT ) ; CallLoweringInfo . reset ( new X86CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new X86LegalizerInfo ( * this , TM ) ) ; auto * RBI = new X86RegisterBankInfo ( * getRegisterInfo ( ) ) ; RegBankInfo . reset ( RBI ) ; InstSelector . reset ( createX86InstructionSelector ( TM , * this , * RBI ) ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


"Disassembly not yet supported for subtarget"

Returns the disassembly of a single instruction .


<s> void ARMHazardRecognizer :: EmitInstruction ( SUnit * SU ) { MachineInstr * MI = SU -> getInstr ( ) ; if ( ! MI -> isDebugInstr ( ) ) { LastMI = MI ; FpMLxStalls = 0 ; } ScoreboardHazardRecognizer :: EmitInstruction ( SU ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static inline bool save_reg_p ( int r ) { return ! call_used_regs [ r ] && df_regs_ever_live_p ( r ) ; } </s>

Determine whether the REG is really used .


<s> static bool isPairedLdSt ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { default : return false ; case AArch64 :: LDPSi : case AArch64 :: LDPSWi : case AArch64 :: LDPDi : case AArch64 :: LDPQi : case AArch64 :: LDPWi : case AArch64 :: LDPXi : case AArch64 :: STPSi : case AArch64 :: STPDi : case AArch64 :: STPQi : case AArch64 :: STPWi : case AArch64 :: STPXi : return true ; } } </s>

Returns whether the instruction is a paired load/store .


<s> uint64_t evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size ) const { unsigned LblOperand = Inst . getOpcode ( ) == AArch64 :: Bcc ? 1 : 0 ; if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ LblOperand ] . OperandType != MCOI :: OPERAND_PCREL ) return - 1ULL ; int64_t Imm = Inst . getOperand ( LblOperand ) . getImm ( ) ; return Addr + Imm ; } </s>

Given a branch instruction try to get the address the branch targets .


<s> SDValue HexagonTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , SDLoc dl , SelectionDAG & DAG ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_Hexagon ) ; SDValue Flag ; SmallVector < SDValue , 4 > RetOps ( 1 , Chain ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( 1 ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } RetOps [ 0 ] = Chain ; if ( Flag . getNode ( ) ) RetOps . push_back ( Flag ) ; return DAG . getNode ( HexagonISD :: RET_FLAG , dl , MVT :: Other , & RetOps [ 0 ] , RetOps . size ( ) ) ; } </s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return this -> TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s>
static
bool
aarch64_rtx_costs_wrapper
(
rtx
x
,
machine_mode
mode
,
int
outer
,
int
param
,
int
*
cost
,
bool
speed
)
{
bool
result
=
aarch64_rtx_costs
(
x
,
mode
,
outer
,
param
,
cost
,
speed
)
;
if
(
dump_file
&&
(
dump_flags
&
TDF_DETAILS
)
)
{
print_rtl_single
(
dump_file
,
x
)
;
fprintf
(
dump_file
,
"\n%s cost: %d (%s)\n"
,
speed
"Hot"
:
"Cold"
,
*
cost
,
result
"final"
:
"partial"
)
;
}
return
result
;
}
</s>

Wrapper around aarch64_rtx_costs , dumps the partial , or total cost calculated for X . This cost is stored in * COST . Returns true if the total cost of X was calculated .

aarch64
"\n%s cost: %d (%s)\n"
"Hot"
"Cold"
"final"
"partial"


"Should be handled target independently"


<s>
StringRef
getPassName
(
)
const
override
{
return
"Hexagon Expand Condsets"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static void single_move_for_cpymem ( rtx dst , rtx src , machine_mode mode , HOST_WIDE_INT offset ) { rtx scratch = gen_reg_rtx ( mode ) ; rtx srcmem , dstmem ; srcmem = adjust_address_nv ( src , mode , offset ) ; dstmem = adjust_address_nv ( dst , mode , offset ) ; emit_move_insn ( scratch , srcmem ) ; emit_move_insn ( dstmem , scratch ) ; } </s>

Adjust DST and SRC by OFFSET bytes , and generate one move in mode MODE .


<s>
const
char
*
output_add_immediate
(
rtx
*
operands
)
{
HOST_WIDE_INT
n
=
INTVAL
(
operands
[
2
]
)
;
if
(
n
!=
0
||
REGNO
(
operands
[
0
]
)
!=
REGNO
(
operands
[
1
]
)
)
{
if
(
n
<
0
)
output_multi_immediate
(
operands
,
"sub%?\t%0, %1, %2"
,
"sub%?\t%0, %0, %2"
,
2
,
n
)
;
else
output_multi_immediate
(
operands
,
"add%?\t%0, %1, %2"
,
"add%?\t%0, %0, %2"
,
2
,
n
)
;
}
return
""
;
}
</s>

Output an ADD r , s , # n where n may be too big for one instruction . If adding zero to one register , output nothing .


<s> static struct machine_function * ft32_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function > ( ) ; } </s>

Zero initialization is OK for all current fields .


<s> static void sparc_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int regno , padding ; function_arg_slotno ( cum , mode , type , named , false , & regno , & padding ) ; cum -> words += padding ; if ( TARGET_ARCH32 ) cum -> words += ( mode == BLKmode ? CEIL_NWORDS ( int_size_in_bytes ( type ) ) : CEIL_NWORDS ( GET_MODE_SIZE ( mode ) ) ) ; else { if ( type && AGGREGATE_TYPE_P ( type ) ) { int size = int_size_in_bytes ( type ) ; if ( size <= 8 ) ++ cum -> words ; else if ( size <= 16 ) cum -> words += 2 ; else ++ cum -> words ; } else cum -> words += ( mode == BLKmode ? CEIL_NWORDS ( int_size_in_bytes ( type ) ) : CEIL_NWORDS ( GET_MODE_SIZE ( mode ) ) ) ; } } </s>

Handle the TARGET_FUNCTION_ARG_ADVANCE hook . Update the data in CUM to advance over an argument of mode MODE and data type TYPE . TYPE is null for libcalls where that information may not be available .


<s> TargetLowering :: AtomicExpansionKind X86TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { Type * MemType = LI -> getType ( ) ; bool NoImplicitFloatOps = LI -> getFunction ( ) -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ; if ( MemType -> getPrimitiveSizeInBits ( ) == 64 && ! Subtarget . is64Bit ( ) && ! Subtarget . useSoftFloat ( ) && ! NoImplicitFloatOps && ( Subtarget . hasSSE2 ( ) || Subtarget . hasX87 ( ) ) ) return AtomicExpansionKind :: None ; return needsCmpXchgNb ( MemType ) ? AtomicExpansionKind :: CmpXChg : AtomicExpansionKind :: None ; } </s>

Returns how the given ( atomic ) load should be expanded by the IR-level AtomicExpand pass .


<s> static bool consume ( InternalInstruction * insn , T & ptr ) { auto r = insn -> bytes ; uint64_t offset = insn -> readerCursor - insn -> startLocation ; if ( offset + sizeof ( T ) > r . size ( ) ) return true ; T ret = 0 ; for ( unsigned i = 0 ; i < sizeof ( T ) ; ++ i ) ret |= ( uint64_t ) r [ offset + i ] << ( i * 8 ) ; ptr = ret ; insn -> readerCursor += sizeof ( T ) ; return false ; } </s>


<s> TargetPassConfig * DCPU16TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new DCPU16PassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> static bool extract_base_offset_in_addr ( rtx mem , rtx * base , rtx * offset ) { rtx addr ; gcc_assert ( MEM_P ( mem ) ) ; addr = XEXP ( mem , 0 ) ; if ( GET_CODE ( addr ) == CONST ) addr = XEXP ( addr , 0 ) ; if ( REG_P ( addr ) ) { * base = addr ; * offset = const0_rtx ; return true ; } if ( GET_CODE ( addr ) == PLUS && GET_CODE ( XEXP ( addr , 0 ) ) == REG && CONST_INT_P ( XEXP ( addr , 1 ) ) ) { * base = XEXP ( addr , 0 ) ; * offset = XEXP ( addr , 1 ) ; return true ; } * base = NULL_RTX ; * offset = NULL_RTX ; return false ; } </s>

If MEM is in the form of `` base+offset '' , extract the two parts of address and set to BASE and OFFSET , otherwise return false after clearing BASE and OFFSET .


<s> Optional < uint64_t > X86MCInstrAnalysis :: evaluateMemoryOperandAddress ( const MCInst & Inst , const MCSubtargetInfo * STI , uint64_t Addr , uint64_t Size ) const { const MCInstrDesc & MCID = Info -> get ( Inst . getOpcode ( ) ) ; int MemOpStart = X86II :: getMemoryOperandNo ( MCID . TSFlags ) ; if ( MemOpStart == - 1 ) return None ; MemOpStart += X86II :: getOperandBias ( MCID ) ; const MCOperand & SegReg = Inst . getOperand ( MemOpStart + X86 :: AddrSegmentReg ) ; const MCOperand & BaseReg = Inst . getOperand ( MemOpStart + X86 :: AddrBaseReg ) ; const MCOperand & IndexReg = Inst . getOperand ( MemOpStart + X86 :: AddrIndexReg ) ; const MCOperand & ScaleAmt = Inst . getOperand ( MemOpStart + X86 :: AddrScaleAmt ) ; const MCOperand & Disp = Inst . getOperand ( MemOpStart + X86 :: AddrDisp ) ; if ( SegReg . getReg ( ) != 0 || IndexReg . getReg ( ) != 0 || ScaleAmt . getImm ( ) != 1 || ! Disp . isImm ( ) ) return None ; if ( BaseReg . getReg ( ) == X86 :: RIP ) return Addr + Size + Disp . getImm ( ) ; return None ; } </s>

Given an instruction tries to get the address of a memory operand .


<s> bool VEInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return false ; if ( ! isUnpredicatedTerminator ( * I ) ) return false ; MachineInstr * LastInst = & * I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { if ( isUncondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } if ( isCondBranchOpcode ( LastOpc ) ) { parseCondBranch ( LastInst , TBB , Cond ) ; return false ; } return true ; } MachineInstr * SecondLastInst = & * I ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; if ( AllowModify && isUncondBranchOpcode ( LastOpc ) ) { while ( isUncondBranchOpcode ( SecondLastOpc ) ) { LastInst -> eraseFromParent ( ) ; LastInst = SecondLastInst ; LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { TBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } SecondLastInst = & * I ; SecondLastOpc = SecondLastInst -> getOpcode ( ) ; } } if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( * -- I ) ) return true ; if ( isCondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { parseCondBranch ( SecondLastInst , TBB , Cond ) ; FBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } if ( isUncondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { TBB = SecondLastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } if ( isIndirectBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return true ; } return true ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> int general_scalar_chain :: vector_const_cost ( rtx exp ) { gcc_assert ( CONST_INT_P ( exp ) ) ; if ( standard_sse_constant_p ( exp , vmode ) ) return ix86_cost -> sse_op ; return ix86_cost -> sse_load [ smode == DImode ? 1 : 0 ] ; } </s>

Return a cost of building a vector costant instead of using a scalar one .


<s> const SITargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


<s> bool X86TTIImpl :: isLegalMaskedGather ( Type * DataTy ) { if ( isa < VectorType > ( DataTy ) && ! isPowerOf2_32 ( DataTy -> getVectorNumElements ( ) ) ) return false ; Type * ScalarTy = DataTy -> getScalarType ( ) ; int DataWidth = isa < PointerType > ( ScalarTy ) ? DL . getPointerSizeInBits ( ) : ScalarTy -> getPrimitiveSizeInBits ( ) ; return DataWidth >= 32 && ST -> hasAVX512 ( ) ; } </s>

Return true if the target supports masked gather .


"Unexpected data type for Gather/Scatter"

Calculate the cost of Gather / Scatter operation .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; const PPCSubtarget & STI = MF . getSubtarget < PPCSubtarget > ( ) ; if ( ! STI . hasVSX ( ) || ! STI . needsSwapsForVSXMemOps ( ) ) return false ; bool Changed = false ; initialize ( MF ) ; if ( gatherVectorInstructions ( ) ) { formWebs ( ) ; recordUnoptimizableWebs ( ) ; markSwapsForRemoval ( ) ; Changed = removeSwaps ( ) ; } delete EC ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool ARMBaseTargetMachine :: addPreSched2 ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt :: None && ! Subtarget . isThumb1Only ( ) ) PM . add ( createARMLoadStoreOptimizationPass ( ) ) ; PM . add ( createARMExpandPseudoPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> const MOSMCExpr * MOSMCExpr :: create ( VariantKind Kind , const MCExpr * Expr , bool Negated , MCContext & Ctx ) { return new ( Ctx ) MOSMCExpr ( Kind , Expr , Negated ) ; } </s>


<s> EVT PPCTargetLowering :: getSetCCResultType ( EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s>
SDValue
SparcTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
RETURNADDR
:
return
SDValue
(
)
;
case
ISD
::
FRAMEADDR
:
return
SDValue
(
)
;
case
ISD
::
GlobalTLSAddress
:
llvm_unreachable
(
"TLS not implemented for Sparc."
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_SINT
(
Op
,
DAG
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerSINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
,
*
this
)
;
case
ISD
::
VAARG
:
return
LowerVAARG
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

Sparc
Sparc
"Should not custom lower this!"
ISD::RETURNADDR
ISD::FRAMEADDR
ISD::GlobalTLSAddress
"TLS not implemented for Sparc."
ISD::GlobalAddress
ISD::ConstantPool
ISD::FP_TO_SINT
ISD::SINT_TO_FP
ISD::BR_CC
ISD::SELECT_CC
ISD::VASTART
ISD::VAARG
ISD::DYNAMIC_STACKALLOC


<s> void HexagonDAGToDAGISel :: Select ( SDNode * N ) { if ( N -> isMachineOpcode ( ) ) return N -> setNodeId ( - 1 ) ; switch ( N -> getOpcode ( ) ) { case ISD :: Constant : return SelectConstant ( N ) ; case ISD :: ConstantFP : return SelectConstantFP ( N ) ; case ISD :: FrameIndex : return SelectFrameIndex ( N ) ; case ISD :: BITCAST : return SelectBitcast ( N ) ; case ISD :: SHL : return SelectSHL ( N ) ; case ISD :: LOAD : return SelectLoad ( N ) ; case ISD :: STORE : return SelectStore ( N ) ; case ISD :: ZERO_EXTEND : return SelectZeroExtend ( N ) ; case ISD :: INTRINSIC_W_CHAIN : return SelectIntrinsicWChain ( N ) ; case ISD :: INTRINSIC_WO_CHAIN : return SelectIntrinsicWOChain ( N ) ; } SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .

Hexagon Hexagon 1 ISD::Constant ISD::ConstantFP ISD::FrameIndex ISD::BITCAST ISD::SHL ISD::LOAD ISD::STORE ISD::ZERO_EXTEND ISD::INTRINSIC_W_CHAIN ISD::INTRINSIC_WO_CHAIN


<s> static rtx rs6000_emit_vector_compare ( enum rtx_code rcode , rtx op0 , rtx op1 , machine_mode dmode ) { rtx mask ; bool swap_operands = false ; bool try_again = false ; gcc_assert ( VECTOR_UNIT_ALTIVEC_OR_VSX_P ( dmode ) ) ; gcc_assert ( GET_MODE ( op0 ) == GET_MODE ( op1 ) ) ; mask = rs6000_emit_vector_compare_inner ( rcode , op0 , op1 ) ; if ( mask ) return mask ; switch ( rcode ) { case LT : rcode = GT ; swap_operands = true ; try_again = true ; break ; case LTU : rcode = GTU ; swap_operands = true ; try_again = true ; break ; case NE : case UNLE : case UNLT : case UNGE : case UNGT : { enum rtx_code rev_code ; enum insn_code nor_code ; rtx mask2 ; rev_code = reverse_condition_maybe_unordered ( rcode ) ; if ( rev_code == UNKNOWN ) return NULL_RTX ; nor_code = optab_handler ( one_cmpl_optab , dmode ) ; if ( nor_code == CODE_FOR_nothing ) return NULL_RTX ; mask2 = rs6000_emit_vector_compare ( rev_code , op0 , op1 , dmode ) ; if ( ! mask2 ) return NULL_RTX ; mask = gen_reg_rtx ( dmode ) ; emit_insn ( GEN_FCN ( nor_code ) ( mask , mask2 ) ) ; return mask ; } break ; case GE : case GEU : case LE : case LEU : { rtx c_rtx , eq_rtx ; enum insn_code ior_code ; enum rtx_code new_code ; switch ( rcode ) { case GE : new_code = GT ; break ; case GEU : new_code = GTU ; break ; case LE : new_code = LT ; break ; case LEU : new_code = LTU ; break ; default : gcc_unreachable ( ) ; } ior_code = optab_handler ( ior_optab , dmode ) ; if ( ior_code == CODE_FOR_nothing ) return NULL_RTX ; c_rtx = rs6000_emit_vector_compare ( new_code , op0 , op1 , dmode ) ; if ( ! c_rtx ) return NULL_RTX ; eq_rtx = rs6000_emit_vector_compare ( EQ , op0 , op1 , dmode ) ; if ( ! eq_rtx ) return NULL_RTX ; mask = gen_reg_rtx ( dmode ) ; emit_insn ( GEN_FCN ( ior_code ) ( mask , c_rtx , eq_rtx ) ) ; return mask ; } break ; default : return NULL_RTX ; } if ( try_again ) { if ( swap_operands ) std :: swap ( op0 , op1 ) ; mask = rs6000_emit_vector_compare_inner ( rcode , op0 , op1 ) ; if ( mask ) return mask ; } return NULL_RTX ; } </s>

Emit vector compare for operands OP0 and OP1 using code RCODE . DMODE is expected destination mode . This is a recursive function .


<s> void SPUHazardRecognizer :: AdvanceCycle ( ) { DOUT << "SPUHazardRecognizer::AdvanceCycle\n" ; } </s>

AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled can not issue in the current cycle , either because of latency or resource conflicts .


<s> bool lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) const { return lowerRISCVMachineOperandToMCOperand ( MO , MCOp , * this ) ; } </s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s>
bool
HCE
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
if
(
MF
.
getFunction
(
)
.
hasPersonalityFn
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
getPassName
(
)
<<
": skipping "
<<
MF
.
getName
(
)
<<
" due to exception handling\n"
)
;
return
false
;
}
LLVM_DEBUG
(
MF
.
print
(
dbgs
(
)
<<
"Before "
<<
getPassName
(
)
<<
'\n'
,
nullptr
)
)
;
HST
=
&
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
;
HII
=
HST
->
getInstrInfo
(
)
;
HRI
=
HST
->
getRegisterInfo
(
)
;
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
AssignmentMap
IMap
;
collect
(
MF
)
;
llvm
::
sort
(
Extenders
,
[
this
]
(
const
ExtDesc
&
A
,
const
ExtDesc
&
B
)
{
ExtValue
VA
(
A
)
,
VB
(
B
)
;
if
(
VA
!=
VB
)
return
VA
<
VB
;
const
MachineInstr
*
MA
=
A
.
UseMI
;
const
MachineInstr
*
MB
=
B
.
UseMI
;
if
(
MA
==
MB
)
{
return
A
.
OpNum
<
B
.
OpNum
;
}
const
MachineBasicBlock
*
BA
=
MA
->
getParent
(
)
;
const
MachineBasicBlock
*
BB
=
MB
->
getParent
(
)
;
assert
(
BA
->
getNumber
(
)
!=
1
&&
BB
->
getNumber
(
)
!=
1
)
;
if
(
BA
!=
BB
)
return
BA
->
getNumber
(
)
<
BB
->
getNumber
(
)
;
return
MDT
->
dominates
(
MA
,
MB
)
;
}
)
;
bool
Changed
=
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Collected "
<<
Extenders
.
size
(
)
<<
" extenders\n"
)
;
for
(
unsigned
I
=
0
,
E
=
Extenders
.
size
(
)
;
I
!=
E
;
)
{
unsigned
B
=
I
;
const
ExtRoot
&
T
=
Extenders
[
B
]
.
getOp
(
)
;
while
(
I
!=
E
&&
ExtRoot
(
Extenders
[
I
]
.
getOp
(
)
)
==
T
)
++
I
;
IMap
.
clear
(
)
;
assignInits
(
T
,
B
,
I
,
IMap
)
;
Changed
|=
replaceExtenders
(
IMap
)
;
}
LLVM_DEBUG
(
{
if
(
Changed
)
MF
.
print
(
dbgs
(
)
<<
"After "
<<
getPassName
(
)
<<
'\n'
,
nullptr
)
;
else
dbgs
(
)
<<
"No changes\n"
;
}
)
;
return
Changed
;
}
</s>

Hexagon
": skipping "
" due to exception handling\n"
"Before "
Hexagon
1
1
"Collected "
" extenders\n"
0
"After "
"No changes\n"


"Encoding of this operand type is not supported yet."

getMachineOpValue - Return binary encoding of operand .


<s> bool SITargetLowering :: getAddrModeArguments ( IntrinsicInst * II , SmallVectorImpl < Value * > & Ops , Type * & AccessTy ) const { switch ( II -> getIntrinsicID ( ) ) { case Intrinsic :: amdgcn_atomic_inc : case Intrinsic :: amdgcn_atomic_dec : case Intrinsic :: amdgcn_atomic_fadd : case Intrinsic :: amdgcn_atomic_fmin : case Intrinsic :: amdgcn_atomic_fmax : { Value * Ptr = II -> getArgOperand ( 0 ) ; AccessTy = II -> getType ( ) ; Ops . push_back ( Ptr ) ; return true ; } default : return false ; } } </s>

CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address .


<s> void function_arg_advance ( struct sparc_args * cum , enum machine_mode mode , tree type , int named ) { int slotno , regno , padding ; slotno = function_arg_slotno ( cum , mode , type , named , 0 , & regno , & padding ) ; if ( slotno != - 1 ) cum -> words += padding ; if ( TARGET_ARCH32 ) { cum -> words += ( mode != BLKmode ? ROUND_ADVANCE ( GET_MODE_SIZE ( mode ) ) : ROUND_ADVANCE ( int_size_in_bytes ( type ) ) ) ; } else { if ( type && AGGREGATE_TYPE_P ( type ) ) { int size = int_size_in_bytes ( type ) ; if ( size <= 8 ) ++ cum -> words ; else if ( size <= 16 ) cum -> words += 2 ; else ++ cum -> words ; } else { cum -> words += ( mode != BLKmode ? ROUND_ADVANCE ( GET_MODE_SIZE ( mode ) ) : ROUND_ADVANCE ( int_size_in_bytes ( type ) ) ) ; } } } </s>

Handle the FUNCTION_ARG_ADVANCE macro . Update the data in CUM to advance over an argument of mode MODE and data type TYPE . TYPE is null for libcalls where that information may not be available .


<s> bool X86AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { static const uint8_t Nops [ 10 ] [ 10 ] = { { 0x90 } , { 0x66 , 0x90 } , { 0x0f , 0x1f , 0x00 } , { 0x0f , 0x1f , 0x40 , 0x00 } , { 0x0f , 0x1f , 0x44 , 0x00 , 0x00 } , { 0x66 , 0x0f , 0x1f , 0x44 , 0x00 , 0x00 } , { 0x0f , 0x1f , 0x80 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x66 , 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x66 , 0x2e , 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , } ; if ( CPU == "geode" ) { for ( uint64_t i = 0 ; i < Count ; ++ i ) OW -> Write8 ( 0x90 ) ; return true ; } const uint64_t OptimalCount = ( Count < 16 ) ? Count : 15 ; const uint64_t Prefixes = OptimalCount <= 10 ? 0 : OptimalCount - 10 ; for ( uint64_t i = 0 , e = Prefixes ; i != e ; i ++ ) OW -> Write8 ( 0x66 ) ; const uint64_t Rest = OptimalCount - Prefixes ; for ( uint64_t i = 0 , e = Rest ; i != e ; i ++ ) OW -> Write8 ( Nops [ Rest - 1 ] [ i ] ) ; for ( uint64_t i = OptimalCount , e = Count ; i != e ; ++ i ) OW -> Write8 ( 0x90 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> PointerTypeMap PointerTypeAnalysis :: run ( const Module & M ) { PointerTypeMap Map ; for ( auto & G : M . globals ( ) ) { if ( G . getType ( ) -> isOpaquePointerTy ( ) ) Map [ & G ] = classifyPointerType ( & G ) ; } for ( auto & F : M ) { classifyFunctionType ( F , Map ) ; for ( const auto & B : F ) { for ( const auto & I : B ) { if ( I . getType ( ) -> isOpaquePointerTy ( ) ) Map [ & I ] = classifyPointerType ( & I ) ; } } } return Map ; } </s>

Run the analysis pass over a function and produce a dominator tree .


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> getFnAttributes ( ) . hasOptimizeForSizeAttr ( ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( N -> getOpcode ( ) == X86ISD :: CALL || N -> getOpcode ( ) == X86ISD :: TC_RETURN ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; EVT SrcVT = N -> getOperand ( 0 ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( 0 ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; bool SrcIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> static tree make_resolver_func ( const tree default_decl , const tree dispatch_decl , basic_block * empty_bb ) { tree decl_name = clone_function_name ( default_decl , "resolver" ) ; const char * resolver_name = IDENTIFIER_POINTER ( decl_name ) ; tree type = build_function_type_list ( ptr_type_node , NULL_TREE ) ; tree decl = build_fn_decl ( resolver_name , type ) ; SET_DECL_ASSEMBLER_NAME ( decl , decl_name ) ; DECL_NAME ( decl ) = decl_name ; TREE_USED ( decl ) = 1 ; DECL_ARTIFICIAL ( decl ) = 1 ; DECL_IGNORED_P ( decl ) = 0 ; TREE_PUBLIC ( decl ) = 0 ; DECL_UNINLINABLE ( decl ) = 1 ; DECL_EXTERNAL ( decl ) = 0 ; DECL_EXTERNAL ( dispatch_decl ) = 0 ; DECL_CONTEXT ( decl ) = NULL_TREE ; DECL_INITIAL ( decl ) = make_node ( BLOCK ) ; DECL_STATIC_CONSTRUCTOR ( decl ) = 0 ; tree t = build_decl ( UNKNOWN_LOCATION , RESULT_DECL , NULL_TREE , ptr_type_node ) ; DECL_CONTEXT ( t ) = decl ; DECL_ARTIFICIAL ( t ) = 1 ; DECL_IGNORED_P ( t ) = 1 ; DECL_RESULT ( decl ) = t ; gimplify_function_tree ( decl ) ; push_cfun ( DECL_STRUCT_FUNCTION ( decl ) ) ; * empty_bb = init_lowered_empty_function ( decl , false , profile_count :: uninitialized ( ) ) ; cgraph_node :: add_new_function ( decl , true ) ; symtab -> call_cgraph_insertion_hooks ( cgraph_node :: get_create ( decl ) ) ; pop_cfun ( ) ; DECL_ATTRIBUTES ( dispatch_decl ) = make_attribute ( "ifunc" , resolver_name , DECL_ATTRIBUTES ( dispatch_decl ) ) ; cgraph_node :: create_same_body_alias ( dispatch_decl , decl ) ; return decl ; } </s>

Make the resolver function decl to dispatch the versions of a multi- versioned function , DEFAULT_DECL . Create an empty basic block in the resolver and store the pointer in EMPTY_BB . Return the decl of the resolver function .


<s> unsigned PPCFrameLowering :: determineFrameLayout ( MachineFunction & MF , bool UpdateMF , bool UseEstimate ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = UseEstimate ? MFI . estimateStackSize ( MF ) : MFI . getStackSize ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned MaxAlign = MFI . getMaxAlignment ( ) ; unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - 1 ; const PPCRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; bool DisableRedZone = MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoRedZone ) ; unsigned LR = RegInfo -> getRARegister ( ) ; if ( ! DisableRedZone && ( Subtarget . isPPC64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == 0 ) && FrameSize <= 224 && ! MFI . hasVarSizedObjects ( ) && ! MFI . adjustsStack ( ) && ! MustSaveLR ( MF , LR ) && ! RegInfo -> hasBasePointer ( MF ) ) { if ( UpdateMF ) MFI . setStackSize ( 0 ) ; return 0 ; } unsigned maxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI . hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI . setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI . setStackSize ( FrameSize ) ; return FrameSize ; } </s>

Determine the frame layout but do not update the machine function .


<s> void HexagonTTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP ) { UP . Runtime = UP . Partial = true ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> MCInst ARMInstrInfo :: getNop ( ) const { MCInst NopInst ; if ( hasNOP ( ) ) { NopInst . setOpcode ( ARM :: HINT ) ; NopInst . addOperand ( MCOperand :: createImm ( 0 ) ) ; NopInst . addOperand ( MCOperand :: createImm ( ARMCC :: AL ) ) ; NopInst . addOperand ( MCOperand :: createReg ( 0 ) ) ; } else { NopInst . setOpcode ( ARM :: MOVr ) ; NopInst . addOperand ( MCOperand :: createReg ( ARM :: R0 ) ) ; NopInst . addOperand ( MCOperand :: createReg ( ARM :: R0 ) ) ; NopInst . addOperand ( MCOperand :: createImm ( ARMCC :: AL ) ) ; NopInst . addOperand ( MCOperand :: createReg ( 0 ) ) ; NopInst . addOperand ( MCOperand :: createReg ( 0 ) ) ; } return NopInst ; } </s>

Return the noop instruction to use for a noop .


<s>
SDValue
PPCTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCRetInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCRetInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_PPC
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Val
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
,
InFlag
)
;
Chain
=
Val
.
getValue
(
1
)
;
InFlag
=
Val
.
getValue
(
2
)
;
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
AExt
:
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
ZExt
:
Val
=
DAG
.
getNode
(
ISD
::
AssertZext
,
dl
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
SExt
:
Val
=
DAG
.
getNode
(
ISD
::
AssertSext
,
dl
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
}
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .

PowerPC
PPC
ISD::InputArg
16
PPC
0
"Can only return in registers!"
1
2
"Unknown loc info!"
ISD::TRUNCATE
ISD::AssertZext
ISD::TRUNCATE
ISD::AssertSext
ISD::TRUNCATE


<s> bool HexagonTargetLowering :: isTruncateFree ( EVT VT1 , EVT VT2 ) const { if ( ! VT1 . isSimple ( ) || ! VT2 . isSimple ( ) ) return false ; return VT1 . getSimpleVT ( ) == MVT :: i64 && VT2 . getSimpleVT ( ) == MVT :: i32 ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s> Register OutgoingValueHandler :: getStackAddress ( const CCValAssign & VA , MachineMemOperand * & MMO ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; const TargetFrameLowering * TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; LLT p0 = LLT :: pointer ( 0 , 32 ) ; LLT s32 = LLT :: scalar ( 32 ) ; Register SPReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildCopy ( SPReg , Register ( Mips :: SP ) ) ; Register OffsetReg = MRI . createGenericVirtualRegister ( s32 ) ; unsigned Offset = VA . getLocMemOffset ( ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; Register AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildGEP ( AddrReg , SPReg , OffsetReg ) ; MachinePointerInfo MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ; unsigned Size = alignTo ( VA . getValVT ( ) . getSizeInBits ( ) , 8 ) / 8 ; unsigned Align = MinAlign ( TFL -> getStackAlignment ( ) , Offset ) ; MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , Align ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


Implements TARGET_ASM_FILE_START . Output the assembly header .


<s> bool HexagonHardwareLoops :: isDead ( const MachineInstr * MI , SmallVector < MachineInstr * , 1 > & DeadPhis ) const { for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( MRI -> use_nodbg_empty ( Reg ) ) continue ; typedef MachineRegisterInfo :: use_nodbg_iterator use_nodbg_iterator ; use_nodbg_iterator I = MRI -> use_nodbg_begin ( Reg ) ; use_nodbg_iterator End = MRI -> use_nodbg_end ( ) ; if ( llvm :: next ( I ) != End || ! I . getOperand ( ) . getParent ( ) -> isPHI ( ) ) return false ; MachineInstr * OnePhi = I . getOperand ( ) . getParent ( ) ; for ( unsigned j = 0 , f = OnePhi -> getNumOperands ( ) ; j != f ; ++ j ) { const MachineOperand & OPO = OnePhi -> getOperand ( j ) ; if ( ! OPO . isReg ( ) || ! OPO . isDef ( ) ) continue ; unsigned OPReg = OPO . getReg ( ) ; use_nodbg_iterator nextJ ; for ( use_nodbg_iterator J = MRI -> use_nodbg_begin ( OPReg ) ; J != End ; J = nextJ ) { nextJ = llvm :: next ( J ) ; MachineOperand & Use = J . getOperand ( ) ; MachineInstr * UseMI = Use . getParent ( ) ; if ( MI != UseMI ) return false ; } } DeadPhis . push_back ( OnePhi ) ; } return true ; } </s>

isDead - Returns true if this is a dead def kill slot .


<s> rtx m68k_legitimize_sibcall_address ( rtx x ) { gcc_assert ( MEM_P ( x ) ) ; if ( sibcall_operand ( XEXP ( x , 0 ) , VOIDmode ) ) return x ; emit_move_insn ( gen_rtx_REG ( Pmode , STATIC_CHAIN_REGNUM ) , XEXP ( x , 0 ) ) ; return replace_equiv_address ( x , gen_rtx_REG ( Pmode , STATIC_CHAIN_REGNUM ) ) ; } </s>


<s> unsigned X86TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT == MVT :: v32i1 && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return 1 ; if ( ( VT == MVT :: v32i16 || VT == MVT :: v64i8 ) && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) && ! EnableOldKNLABI ) return 1 ; return TargetLowering :: getNumRegistersForCallingConv ( Context , CC , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s> bool HexagonEvaluator :: evaluate ( const MachineInstr & BI , const CellMapType & Inputs , BranchTargetList & Targets , bool & FallsThru ) const { unsigned Opc = BI . getOpcode ( ) ; bool SimpleBranch = false ; bool Negated = false ; switch ( Opc ) { case Hexagon :: J2_jumpf : case Hexagon :: J2_jumpfnew : case Hexagon :: J2_jumpfnewpt : Negated = true ; case Hexagon :: J2_jumpt : case Hexagon :: J2_jumptnew : case Hexagon :: J2_jumptnewpt : SimpleBranch = true ; break ; case Hexagon :: J2_jump : Targets . insert ( BI . getOperand ( 0 ) . getMBB ( ) ) ; FallsThru = false ; return true ; default : return false ; } if ( ! SimpleBranch ) return false ; RegisterRef PR = BI . getOperand ( 0 ) ; RegisterCell PC = getCell ( PR , Inputs ) ; const BT :: BitValue & Test = PC [ 0 ] ; if ( ! Test . is ( 0 ) && ! Test . is ( 1 ) ) return false ; if ( ! Test . is ( ! Negated ) ) { FallsThru = true ; return true ; } Targets . insert ( BI . getOperand ( 1 ) . getMBB ( ) ) ; FallsThru = false ; return true ; } </s>

evaluate - Evaluate Expr and append the resulting set to Elts .


<s> bool isLegalMaskedStore ( Type * DataTy , MaybeAlign Alignment ) { return isLegalMaskedLoad ( DataTy , Alignment ) ; } </s>

Return true if the target supports masked store .


<s> void X86PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; addPass ( createX86LowerAMXTypePass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedAccessPass ( ) ) ; addPass ( createX86PartialReductionPass ( ) ) ; } addPass ( createIndirectBrExpandPass ( ) ) ; const Triple & TT = TM -> getTargetTriple ( ) ; if ( TT . isOSWindows ( ) ) { if ( TT . getArch ( ) == Triple :: x86_64 ) { addPass ( createCFGuardDispatchPass ( ) ) ; } else { addPass ( createCFGuardCheckPass ( ) ) ; } } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> uint64_t getNullPointerValue ( unsigned AddrSpace ) const { switch ( AddrSpace ) { case AMDGPUAS :: PRIVATE_ADDRESS : case AMDGPUAS :: LOCAL_ADDRESS : case AMDGPUAS :: REGION_ADDRESS : return - 1 ; default : return 0 ; } } </s>

Get the integer value of a null pointer in the given address space .


<s> void ARCompactRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool R600InstrInfo :: fitsConstReadLimitations ( const std :: vector < MachineInstr * > & MIs ) const { std :: vector < unsigned > Consts ; SmallSet < int64_t , 4 > Literals ; for ( unsigned i = 0 , n = MIs . size ( ) ; i < n ; i ++ ) { MachineInstr * MI = MIs [ i ] ; if ( ! isALUInstr ( MI -> getOpcode ( ) ) ) continue ; ArrayRef < std :: pair < MachineOperand * , int64_t >> Srcs = getSrcs ( MI ) ; for ( unsigned j = 0 , e = Srcs . size ( ) ; j < e ; j ++ ) { std :: pair < MachineOperand * , unsigned > Src = Srcs [ j ] ; if ( Src . first -> getReg ( ) == AMDGPU :: ALU_LITERAL_X ) Literals . insert ( Src . second ) ; if ( Literals . size ( ) > 4 ) return false ; if ( Src . first -> getReg ( ) == AMDGPU :: ALU_CONST ) Consts . push_back ( Src . second ) ; if ( AMDGPU :: R600_KC0RegClass . contains ( Src . first -> getReg ( ) ) || AMDGPU :: R600_KC1RegClass . contains ( Src . first -> getReg ( ) ) ) { unsigned Index = RI . getEncodingValue ( Src . first -> getReg ( ) ) & 0xff ; unsigned Chan = RI . getHWRegChan ( Src . first -> getReg ( ) ) ; Consts . push_back ( ( Index << 2 ) | Chan ) ; } } } return fitsConstReadLimitations ( Consts ) ; } </s>

Same but using const index set instead of MI set .


<s> static void arm_initialize_isa ( sbitmap isa , const enum isa_feature * isa_bits ) { bitmap_clear ( isa ) ; while ( * isa_bits != isa_nobit ) bitmap_set_bit ( isa , * ( isa_bits ++ ) ) ; } </s>

Convert a static initializer array of feature bits to sbitmap representation .


<s>
SDValue
SPUTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_SPU
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
SPUISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
else
return
DAG
.
getNode
(
SPUISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> unsigned X86TargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const SelectionDAG & , unsigned Depth ) const { if ( Op . getOpcode ( ) == X86ISD :: SETCC_CARRY ) return Op . getValueType ( ) . getScalarType ( ) . getSizeInBits ( ) ; return 1 ; } </s>

Determine the number of bits in the operation that are sign bits .


"Expected label,@type declaration, got: "

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool SITargetLowering :: isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const { return isFlatGlobalAddrSpace ( SrcAS ) && isFlatGlobalAddrSpace ( DestAS ) ; } </s>

Returns true if a cast between SrcAS and DestAS is a noop .


<s> bool Cpu0FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = & MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || TRI -> needsStackRealignment ( MF ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> rtx mips_rewrite_small_data ( rtx op ) { op = copy_insn ( op ) ; for_each_rtx ( & op , mips_rewrite_small_data_1 , 0 ) ; return op ; } </s>

If possible , rewrite OP so that it refers to small data using explicit relocations .


<s> MachineInstrBuilder buildLoad ( const DstOp & Res , Register Addr , uint64_t Size , unsigned Alignment , MachinePointerInfo & MPO ) { auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , Size , Alignment ) ; return MIRBuilder . buildLoad ( Res , Addr , * MMO ) ; } </s>

Build and insert a G_LOAD instruction , while constructing the MachineMemOperand .


Return 1 if br.ret can do all the work required to return from a function .


<s> static bool crx_fixed_condition_code_regs ( unsigned int * p1 , unsigned int * p2 ) { * p1 = CC_REGNUM ; * p2 = INVALID_REGNUM ; return true ; } </s>

Return the fixed registers used for condition codes .


<s> tree rs6000_fold_builtin ( tree fndecl ATTRIBUTE_UNUSED , int n_args ATTRIBUTE_UNUSED , tree * args ATTRIBUTE_UNUSED , bool ignore ATTRIBUTE_UNUSED ) { return SUBTARGET_FOLD_BUILTIN ( fndecl , n_args , args , ignore ) ; return NULL_TREE ; } </s>

Target hook for early folding of built-ins , shamelessly stolen from ia64.cc .


<s>
SUnit
*
R600SchedStrategy
::
pickNode
(
bool
&
IsTopNode
)
{
SUnit
*
SU
=
nullptr
;
NextInstKind
=
IDOther
;
IsTopNode
=
false
;
bool
AllowSwitchToAlu
=
(
CurEmitted
>=
InstKindLimit
[
CurInstKind
]
)
||
(
Available
[
CurInstKind
]
.
empty
(
)
)
;
bool
AllowSwitchFromAlu
=
(
CurEmitted
>=
InstKindLimit
[
CurInstKind
]
)
&&
(
!
Available
[
IDFetch
]
.
empty
(
)
||
!
Available
[
IDOther
]
.
empty
(
)
)
;
if
(
CurInstKind
==
IDAlu
&&
!
Available
[
IDFetch
]
.
empty
(
)
)
{
float
ALUFetchRationEstimate
=
(
AluInstCount
+
AvailablesAluCount
(
)
+
Pending
[
IDAlu
]
.
size
(
)
)
/
(
FetchInstCount
+
Available
[
IDFetch
]
.
size
(
)
)
;
if
(
ALUFetchRationEstimate
==
0
)
{
AllowSwitchFromAlu
=
true
;
}
else
{
unsigned
NeededWF
=
62.5f
/
ALUFetchRationEstimate
;
DEBUG
(
dbgs
(
)
<<
NeededWF
<<
" approx. Wavefronts Required\n"
)
;
unsigned
NearRegisterRequirement
=
2
*
Available
[
IDFetch
]
.
size
(
)
;
if
(
NeededWF
>
getWFCountLimitedByGPR
(
NearRegisterRequirement
)
)
AllowSwitchFromAlu
=
true
;
}
}
if
(
!
SU
&&
(
(
AllowSwitchToAlu
&&
CurInstKind
!=
IDAlu
)
||
(
!
AllowSwitchFromAlu
&&
CurInstKind
==
IDAlu
)
)
)
{
SU
=
pickAlu
(
)
;
if
(
!
SU
&&
!
PhysicalRegCopy
.
empty
(
)
)
{
SU
=
PhysicalRegCopy
.
front
(
)
;
PhysicalRegCopy
.
erase
(
PhysicalRegCopy
.
begin
(
)
)
;
}
if
(
SU
)
{
if
(
CurEmitted
>=
InstKindLimit
[
IDAlu
]
)
CurEmitted
=
0
;
NextInstKind
=
IDAlu
;
}
}
if
(
!
SU
)
{
SU
=
pickOther
(
IDFetch
)
;
if
(
SU
)
NextInstKind
=
IDFetch
;
}
if
(
!
SU
)
{
SU
=
pickOther
(
IDOther
)
;
if
(
SU
)
NextInstKind
=
IDOther
;
}
DEBUG
(
if
(
SU
)
{
dbgs
(
)
<<
" ** Pick node **\n"
;
SU
->
dump
(
DAG
)
;
}
else
{
dbgs
(
)
<<
"NO NODE \n"
;
for
(
unsigned
i
=
0
;
i
<
DAG
->
SUnits
.
size
(
)
;
i
++
)
{
const
SUnit
&
S
=
DAG
->
SUnits
[
i
]
;
if
(
!
S
.
isScheduled
)
S
.
dump
(
DAG
)
;
}
}
</s>

Pick the next node to schedule , or return NULL .


<s> static void mips_end_ll_sc_sync_block ( void ) { if ( ! ISA_HAS_LL_SC ) output_asm_insn ( ".set\tpop" , 0 ) ; } </s>

End a block started by mips_start_ll_sc_sync_block .


"missing architecture name in 'arch' target %s"

"unknown value %qs for 'arch' target %s"

"invalid feature modifier %qs for 'arch' target %s"

Handle the ARCH_STR argument to the arch= target attribute . PRAGMA_OR_ATTR is used in potential error messages .


<s>
void
HexagonEarlyIfConversion
::
removeBlock
(
MachineBasicBlock
*
B
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Removing block "
<<
PrintMB
(
B
)
<<
"\n"
)
;
MachineDomTreeNode
*
N
=
MDT
->
getNode
(
B
)
;
MachineDomTreeNode
*
IDN
=
N
->
getIDom
(
)
;
if
(
IDN
)
{
MachineBasicBlock
*
IDB
=
IDN
->
getBlock
(
)
;
using
GTN
=
GraphTraits
<
MachineDomTreeNode
*
>
;
using
DTNodeVectType
=
SmallVector
<
MachineDomTreeNode
*
,
4
>
;
DTNodeVectType
Cn
(
GTN
::
child_begin
(
N
)
,
GTN
::
child_end
(
N
)
)
;
for
(
auto
&
I
:
Cn
)
{
MachineBasicBlock
*
SB
=
I
->
getBlock
(
)
;
MDT
->
changeImmediateDominator
(
SB
,
IDB
)
;
}
}
while
(
!
B
->
succ_empty
(
)
)
B
->
removeSuccessor
(
B
->
succ_begin
(
)
)
;
for
(
MachineBasicBlock
*
Pred
:
B
->
predecessors
(
)
)
Pred
->
removeSuccessor
(
B
,
true
)
;
Deleted
.
insert
(
B
)
;
MDT
->
eraseNode
(
B
)
;
MFN
->
erase
(
B
->
getIterator
(
)
)
;
}
</s>

This method completely removes BB from all data structures , including all of the Loop objects it is nested in and our mapping from MachineBasicBlocks to loops .

Hexagon
Hexagon
"Removing block "
"\n"
4


Simple predicate for targets where ! Resolved implies requiring relaxation .


<s>
Register
PPCTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
const
MachineFunction
&
MF
)
const
{
bool
isPPC64
=
Subtarget
.
isPPC64
(
)
;
bool
IsDarwinABI
=
Subtarget
.
isDarwinABI
(
)
;
if
(
(
isPPC64
&&
VT
!=
MVT
::
i64
&&
VT
!=
MVT
::
i32
)
||
(
!
isPPC64
&&
VT
!=
MVT
::
i32
)
)
report_fatal_error
(
"Invalid register global variable type"
)
;
bool
is64Bit
=
isPPC64
&&
VT
==
MVT
::
i64
;
Register
Reg
=
StringSwitch
<
Register
>
(
RegName
)
.
Case
(
"r1"
,
is64Bit
PPC
::
X1
:
PPC
::
R1
)
.
Case
(
"r2"
,
(
IsDarwinABI
||
isPPC64
)
Register
(
)
:
PPC
::
R2
)
.
Case
(
"r13"
,
(
!
isPPC64
&&
IsDarwinABI
)
Register
(
)
:
(
is64Bit
PPC
::
X13
:
PPC
::
R13
)
)
.
Default
(
Register
(
)
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s>
unsigned
MSP430MCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
if
(
MO
.
isImm
(
)
)
{
Offset
+=
2
;
return
MO
.
getImm
(
)
;
}
assert
(
MO
.
isExpr
(
)
&&
"Expected expr operand"
)
;
Fixups
.
push_back
(
MCFixup
::
create
(
Offset
,
MO
.
getExpr
(
)
,
static_cast
<
MCFixupKind
>
(
MSP430
::
fixup_16_byte
)
,
MI
.
getLoc
(
)
)
)
;
Offset
+=
2
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> void rs6000_sibcall_aix ( rtx value , rtx func_desc , rtx flag , rtx cookie ) { rtx call [ 2 ] ; rtx insn ; gcc_assert ( INTVAL ( cookie ) == 0 ) ; call [ 0 ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_desc ) , flag ) ; if ( value != NULL_RTX ) call [ 0 ] = gen_rtx_SET ( value , call [ 0 ] ) ; call [ 1 ] = simple_return_rtx ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( 2 , call ) ) ; insn = emit_call_insn ( insn ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , gen_rtx_REG ( Pmode , TOC_REGNUM ) ) ; } </s>

Expand code to perform a sibling call under the AIX or ELFv2 ABI .


<s>
ScheduleHazardRecognizer
*
PPCInstrInfo
::
CreateTargetPostRAHazardRecognizer
(
const
InstrItineraryData
*
II
,
const
ScheduleDAG
*
DAG
)
const
{
unsigned
Directive
=
DAG
->
TM
.
getSubtarget
<
PPCSubtarget
>
(
)
.
getDarwinDirective
(
)
;
if
(
Directive
==
PPC
::
DIR_PWR7
||
Directive
==
PPC
::
DIR_PWR8
)
return
new
PPCDispatchGroupSBHazardRecognizer
(
II
,
DAG
)
;
if
(
Directive
!=
PPC
::
DIR_440
&&
Directive
!=
PPC
::
DIR_A2
&&
Directive
!=
PPC
::
DIR_E500mc
&&
Directive
!=
PPC
::
DIR_E5500
)
{
assert
(
DAG
->
TII
&&
"No InstrInfo?"
)
;
return
new
PPCHazardRecognizer970
(
*
DAG
)
;
}
return
new
ScoreboardHazardRecognizer
(
II
,
DAG
)
;
}
</s>

Allocate and return a hazard recognizer to use for by non-scheduling passes .


<s> static void alpha_override_options_after_change ( void ) { if ( optimize > 0 ) { if ( flag_align_loops && ! str_align_loops ) str_align_loops = "16" ; if ( flag_align_jumps && ! str_align_jumps ) str_align_jumps = "16" ; } if ( flag_align_functions && ! str_align_functions ) str_align_functions = "16" ; } </s>


"insertBranch must not be told to insert a fallthrough"

"Unconditional branch with multiple successors!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( CommentStream ) HasCustomInstComment = EmitAnyX86InstComments ( MI , * CommentStream , getRegisterName ) ; unsigned Flags = MI -> getFlags ( ) ; if ( ( TSFlags & X86II :: LOCK ) || ( Flags & X86 :: IP_HAS_LOCK ) ) OS << "\tlock\t" ; if ( Flags & X86 :: IP_HAS_REPEAT_NE ) OS << "\trepne\t" ; else if ( Flags & X86 :: IP_HAS_REPEAT ) OS << "\trep\t" ; if ( MI -> getOpcode ( ) == X86 :: CALLpcrel32 && ( STI . getFeatureBits ( ) [ X86 :: Mode64Bit ] ) ) { OS << "\tcallq\t" ; printPCRelImm ( MI , 0 , OS ) ; } else if ( MI -> getOpcode ( ) == X86 :: DATA16_PREFIX && ( STI . getFeatureBits ( ) [ X86 :: Mode16Bit ] ) ) { MCInst Data32MI ( * MI ) ; Data32MI . setOpcode ( X86 :: DATA32_PREFIX ) ; printInstruction ( & Data32MI , OS ) ; } else if ( ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s>
SDValue
VETargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
assert
(
!
IsVarArg
&&
"TODO implement var args"
)
;
assert
(
Ins
.
empty
(
)
&&
"TODO implement input arguments"
)
;
return
Chain
;
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .

VE
VE
ISD::InputArg
"TODO implement var args"
"TODO implement input arguments"


<s> bool MBlazeIntrinsicInfo :: isOverloaded ( unsigned IntrID ) const { const bool OTable [ ] = { } ; if ( IntrID == 0 ) return false ; else return OTable [ IntrID - Intrinsic :: num_intrinsics ] ; } </s>

Returns true if the intrinsic can be overloaded .


<s>
bool
A15SDOptimizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
if
(
skipFunction
(
Fn
.
getFunction
(
)
)
)
return
false
;
const
ARMSubtarget
&
STI
=
Fn
.
getSubtarget
<
ARMSubtarget
>
(
)
;
if
(
!
(
STI
.
useSplatVFPToNeon
(
)
&&
STI
.
hasNEON
(
)
)
)
return
false
;
TII
=
STI
.
getInstrInfo
(
)
;
TRI
=
STI
.
getRegisterInfo
(
)
;
MRI
=
&
Fn
.
getRegInfo
(
)
;
bool
Modified
=
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Running on function "
<<
Fn
.
getName
(
)
<<
"\n"
)
;
DeadInstr
.
clear
(
)
;
Replacements
.
clear
(
)
;
for
(
MachineBasicBlock
&
MBB
:
Fn
)
{
for
(
MachineInstr
&
MI
:
MBB
)
{
Modified
|=
runOnInstruction
(
&
MI
)
;
}
}
for
(
MachineInstr
*
MI
:
DeadInstr
)
{
MI
->
eraseFromParent
(
)
;
}
return
Modified
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool AMDGPUAnnotateUniformValues :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; DA = & getAnalysis < LegacyDivergenceAnalysis > ( ) ; MSSA = & getAnalysis < MemorySSAWrapperPass > ( ) . getMSSA ( ) ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; isEntryFunc = AMDGPU :: isEntryFunctionCC ( F . getCallingConv ( ) ) ; Changed = false ; visit ( F ) ; return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool AMDGPUTargetELFStreamer :: EmitHSAMetadata ( const AMDGPU :: HSAMD :: Metadata & HSAMetadata ) { std :: string HSAMetadataString ; if ( HSAMD :: toString ( HSAMetadata , HSAMetadataString ) ) return false ; auto & Context = getContext ( ) ; auto * DescBegin = Context . createTempSymbol ( ) ; auto * DescEnd = Context . createTempSymbol ( ) ; auto * DescSZ = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( DescEnd , Context ) , MCSymbolRefExpr :: create ( DescBegin , Context ) , Context ) ; EmitNote ( ElfNote :: NoteNameV2 , DescSZ , ELF :: NT_AMD_AMDGPU_HSA_METADATA , [ & ] ( MCELFStreamer & OS ) { OS . EmitLabel ( DescBegin ) ; OS . EmitBytes ( HSAMetadataString ) ; OS . EmitLabel ( DescEnd ) ; } ) ; return true ; } </s>


<s> void AnalyzeFormalArguments ( const SmallVectorImpl < ISD :: InputArg > & Ins , CCAssignFn Fn ) { ArgIsFixed . clear ( ) ; for ( unsigned i = 0 ; i < Ins . size ( ) ; ++ i ) ArgIsFixed . push_back ( true ) ; ArgIsShortVector . clear ( ) ; for ( unsigned i = 0 ; i < Ins . size ( ) ; ++ i ) ArgIsShortVector . push_back ( IsShortVectorType ( Ins [ i ] . ArgVT ) ) ; CCState :: AnalyzeFormalArguments ( Ins , Fn ) ; } </s>

AnalyzeFormalArguments - Analyze an array of argument values , incorporating info about the formals into this state .


<s> bool rs6000_is_valid_mask ( rtx mask , int * b , int * e , machine_mode mode ) { unsigned HOST_WIDE_INT val = INTVAL ( mask ) ; unsigned HOST_WIDE_INT bit ; int nb , ne ; int n = GET_MODE_PRECISION ( mode ) ; if ( mode != DImode && mode != SImode ) return false ; if ( INTVAL ( mask ) >= 0 ) { bit = val & - val ; ne = exact_log2 ( bit ) ; nb = exact_log2 ( val + bit ) ; } else if ( val + 1 == 0 ) { nb = n ; ne = 0 ; } else if ( val & 1 ) { val = ~ val ; bit = val & - val ; nb = exact_log2 ( bit ) ; ne = exact_log2 ( val + bit ) ; } else { bit = val & - val ; ne = exact_log2 ( bit ) ; if ( val + bit == 0 ) nb = n ; else nb = 0 ; } nb -- ; if ( nb < 0 || ne < 0 || nb >= n || ne >= n ) return false ; if ( b ) * b = nb ; if ( e ) * e = ne ; return true ; } </s>

Return whether MASK ( a CONST_INT ) is a valid mask for any rlwinm , rldicl , rldicr , or rldic instruction in mode MODE . If so , if E is not zero , store there the bit offset ( counted from the right ) where the single stretch of 1 bits begins ; and similarly for B , the bit offset where it ends .


<s> const uint32_t * ARM64RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: AnyReg ) return CSR_ARM64_AllRegs_RegMask ; else return CSR_ARM64_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool MipsSETargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , MachineMemOperand :: Flags , bool * Fast ) const { MVT :: SimpleValueType SVT = VT . getSimpleVT ( ) . SimpleTy ; if ( Subtarget . systemSupportsUnalignedAccess ( ) ) { if ( Fast ) * Fast = true ; return true ; } switch ( SVT ) { case MVT :: i64 : case MVT :: i32 : if ( Fast ) * Fast = true ; return true ; default : return false ; } } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


More limited version of SimplifyDemandedBits that can be used to `` look through '' ops that do n't contribute to the DemandedBits/DemandedElts - bitwise ops etc .


<s> static rtx warp_prop_gen ( rtx reg , propagate_mask pm , unsigned ARG_UNUSED ( count ) , void * ARG_UNUSED ( data ) , bool ARG_UNUSED ( vector ) ) { if ( ! ( pm & PM_read_write ) ) return 0 ; return nvptx_gen_warp_bcast ( reg ) ; } </s>


<s>
MipsSubtarget
&
MipsSubtarget
::
initializeSubtargetDependencies
(
StringRef
CPU
,
StringRef
FS
,
const
TargetMachine
&
TM
)
{
std
::
string
CPUName
=
MIPS_MC
::
selectMipsCPU
(
TM
.
getTargetTriple
(
)
,
CPU
)
;
ParseSubtargetFeatures
(
CPUName
,
FS
)
;
InstrItins
=
getInstrItineraryForCPU
(
CPUName
)
;
if
(
InMips16Mode
&&
!
IsSoftFloat
)
InMips16HardFloat
=
true
;
if
(
StackAlignOverride
)
stackAlignment
=
StackAlignOverride
;
else
if
(
isABI_N32
(
)
||
isABI_N64
(
)
)
stackAlignment
=
16
;
else
{
assert
(
isABI_O32
(
)
&&
"Unknown ABI for stack alignment!"
)
;
stackAlignment
=
8
;
}
return
*
this
;
}
</s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .

Mips
Mips
Mips
MIPS_MC::selectMipsCPU
Mips
Mips
16
"Unknown ABI for stack alignment!"
8


<s> static bool r10k_simplified_address_p ( rtx x ) { if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , 1 ) ) ) x = XEXP ( x , 0 ) ; return x == virtual_incoming_args_rtx || CONSTANT_P ( x ) ; } </s>

Return true if it is worth r10k_simplify_address 's while replacing an address with X . We are looking for constants , and for addresses at a known offset from the incoming stack pointer .


<s> const char * MipsTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case MipsISD :: JmpLink : return "MipsISD::JmpLink" ; case MipsISD :: TailCall : return "MipsISD::TailCall" ; case MipsISD :: Hi : return "MipsISD::Hi" ; case MipsISD :: Lo : return "MipsISD::Lo" ; case MipsISD :: GPRel : return "MipsISD::GPRel" ; case MipsISD :: ThreadPointer : return "MipsISD::ThreadPointer" ; case MipsISD :: Ret : return "MipsISD::Ret" ; case MipsISD :: EH_RETURN : return "MipsISD::EH_RETURN" ; case MipsISD :: FPBrcond : return "MipsISD::FPBrcond" ; case MipsISD :: FPCmp : return "MipsISD::FPCmp" ; case MipsISD :: CMovFP_T : return "MipsISD::CMovFP_T" ; case MipsISD :: CMovFP_F : return "MipsISD::CMovFP_F" ; case MipsISD :: FPRound : return "MipsISD::FPRound" ; case MipsISD :: MAdd : return "MipsISD::MAdd" ; case MipsISD :: MAddu : return "MipsISD::MAddu" ; case MipsISD :: MSub : return "MipsISD::MSub" ; case MipsISD :: MSubu : return "MipsISD::MSubu" ; case MipsISD :: DivRem : return "MipsISD::DivRem" ; case MipsISD :: DivRemU : return "MipsISD::DivRemU" ; case MipsISD :: BuildPairF64 : return "MipsISD::BuildPairF64" ; case MipsISD :: ExtractElementF64 : return "MipsISD::ExtractElementF64" ; case MipsISD :: Wrapper : return "MipsISD::Wrapper" ; case MipsISD :: Sync : return "MipsISD::Sync" ; case MipsISD :: Ext : return "MipsISD::Ext" ; case MipsISD :: Ins : return "MipsISD::Ins" ; case MipsISD :: LWL : return "MipsISD::LWL" ; case MipsISD :: LWR : return "MipsISD::LWR" ; case MipsISD :: SWL : return "MipsISD::SWL" ; case MipsISD :: SWR : return "MipsISD::SWR" ; case MipsISD :: LDL : return "MipsISD::LDL" ; case MipsISD :: LDR : return "MipsISD::LDR" ; case MipsISD :: SDL : return "MipsISD::SDL" ; case MipsISD :: SDR : return "MipsISD::SDR" ; case MipsISD :: EXTP : return "MipsISD::EXTP" ; case MipsISD :: EXTPDP : return "MipsISD::EXTPDP" ; case MipsISD :: EXTR_S_H : return "MipsISD::EXTR_S_H" ; case MipsISD :: EXTR_W : return "MipsISD::EXTR_W" ; case MipsISD :: EXTR_R_W : return "MipsISD::EXTR_R_W" ; case MipsISD :: EXTR_RS_W : return "MipsISD::EXTR_RS_W" ; case MipsISD :: SHILO : return "MipsISD::SHILO" ; case MipsISD :: MTHLIP : return "MipsISD::MTHLIP" ; case MipsISD :: MULT : return "MipsISD::MULT" ; case MipsISD :: MULTU : return "MipsISD::MULTU" ; case MipsISD :: MADD_DSP : return "MipsISD::MADD_DSP" ; case MipsISD :: MADDU_DSP : return "MipsISD::MADDU_DSP" ; case MipsISD :: MSUB_DSP : return "MipsISD::MSUB_DSP" ; case MipsISD :: MSUBU_DSP : return "MipsISD::MSUBU_DSP" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific

Mips Mips MipsISD::JmpLink "MipsISD::JmpLink" MipsISD::TailCall "MipsISD::TailCall" MipsISD::Hi "MipsISD::Hi" MipsISD::Lo "MipsISD::Lo" MipsISD::GPRel "MipsISD::GPRel" MipsISD::ThreadPointer "MipsISD::ThreadPointer" MipsISD::Ret "MipsISD::Ret" MipsISD::EH_RETURN "MipsISD::EH_RETURN" MipsISD::FPBrcond "MipsISD::FPBrcond" MipsISD::FPCmp "MipsISD::FPCmp" MipsISD::CMovFP_T "MipsISD::CMovFP_T" MipsISD::CMovFP_F "MipsISD::CMovFP_F" MipsISD::FPRound "MipsISD::FPRound" MipsISD::MAdd "MipsISD::MAdd" MipsISD::MAddu "MipsISD::MAddu" MipsISD::MSub "MipsISD::MSub" MipsISD::MSubu "MipsISD::MSubu" MipsISD::DivRem "MipsISD::DivRem" MipsISD::DivRemU "MipsISD::DivRemU" MipsISD::BuildPairF64 "MipsISD::BuildPairF64" MipsISD::ExtractElementF64 "MipsISD::ExtractElementF64" MipsISD::Wrapper "MipsISD::Wrapper" MipsISD::Sync "MipsISD::Sync" MipsISD::Ext "MipsISD::Ext" MipsISD::Ins "MipsISD::Ins" MipsISD::LWL "MipsISD::LWL" MipsISD::LWR "MipsISD::LWR" MipsISD::SWL "MipsISD::SWL" MipsISD::SWR "MipsISD::SWR" MipsISD::LDL "MipsISD::LDL" MipsISD::LDR "MipsISD::LDR" MipsISD::SDL "MipsISD::SDL" MipsISD::SDR "MipsISD::SDR" MipsISD::EXTP "MipsISD::EXTP" MipsISD::EXTPDP "MipsISD::EXTPDP" MipsISD::EXTR_S_H "MipsISD::EXTR_S_H" MipsISD::EXTR_W "MipsISD::EXTR_W" MipsISD::EXTR_R_W "MipsISD::EXTR_R_W" MipsISD::EXTR_RS_W "MipsISD::EXTR_RS_W" MipsISD::SHILO "MipsISD::SHILO" MipsISD::MTHLIP "MipsISD::MTHLIP" MipsISD::MULT "MipsISD::MULT" MipsISD::MULTU "MipsISD::MULTU" MipsISD::MADD_DSP "MipsISD::MADD_DSP" MipsISD::MADDU_DSP "MipsISD::MADDU_DSP" MipsISD::MSUB_DSP "MipsISD::MSUB_DSP" MipsISD::MSUBU_DSP "MipsISD::MSUBU_DSP"


<s> void sh_set_return_address ( rtx ra , rtx tmp ) { HARD_REG_SET live_regs_mask ; int d = calc_live_regs ( & live_regs_mask ) ; if ( ! TEST_HARD_REG_BIT ( live_regs_mask , PR_REG ) ) { rtx rr = gen_rtx_REG ( SImode , PR_REG ) ; emit_insn ( GEN_MOV ( rr , ra ) ) ; emit_use ( rr ) ; return ; } int pr_offset = rounded_frame_size ( d ) ; emit_insn ( GEN_MOV ( tmp , GEN_INT ( pr_offset ) ) ) ; if ( frame_pointer_needed ) emit_insn ( GEN_ADD3 ( tmp , tmp , hard_frame_pointer_rtx ) ) ; else emit_insn ( GEN_ADD3 ( tmp , tmp , stack_pointer_rtx ) ) ; tmp = gen_frame_mem ( Pmode , tmp ) ; emit_insn ( GEN_MOV ( tmp , ra ) ) ; emit_use ( tmp ) ; } </s>

Emit code to change the current function 's return address to RA . TEMP is available as a scratch register , if needed .


<s> unsigned ARMBaseInstrInfo :: getInstrLatency ( const InstrItineraryData * ItinData , const MachineInstr & MI , unsigned * PredCost ) const { if ( MI . isCopyLike ( ) || MI . isInsertSubreg ( ) || MI . isRegSequence ( ) || MI . isImplicitDef ( ) ) return 1 ; if ( MI . isBundle ( ) ) { unsigned Latency = 0 ; MachineBasicBlock :: const_instr_iterator I = MI . getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI . getParent ( ) -> instr_end ( ) ; while ( ++ I != E && I -> isInsideBundle ( ) ) { if ( I -> getOpcode ( ) != ARM :: t2IT ) Latency += getInstrLatency ( ItinData , * I , PredCost ) ; } return Latency ; } const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( PredCost && ( MCID . isCall ( ) || ( MCID . hasImplicitDefOfPhysReg ( ARM :: CPSR ) && ! Subtarget . cheapPredicableCPSRDef ( ) ) ) ) { * PredCost = 1 ; } if ( ! ItinData ) return MI . mayLoad ( ) ? 3 : 1 ; unsigned Class = MCID . getSchedClass ( ) ; if ( ! ItinData -> isEmpty ( ) && ItinData -> getNumMicroOps ( Class ) < 0 ) return getNumMicroOps ( ItinData , MI ) ; unsigned Latency = ItinData -> getStageLatency ( Class ) ; unsigned DefAlign = MI . hasOneMemOperand ( ) ? ( * MI . memoperands_begin ( ) ) -> getAlignment ( ) : 0 ; int Adj = adjustDefLatency ( Subtarget , MI , MCID , DefAlign ) ; if ( Adj >= 0 || ( int ) Latency > - Adj ) { return Latency + Adj ; } return Latency ; } </s>

Compute the instruction latency of a given instruction .


<s> int standard_80387_constant_p ( rtx x ) { if ( GET_CODE ( x ) != CONST_DOUBLE || ! FLOAT_MODE_P ( GET_MODE ( x ) ) ) return - 1 ; if ( x == CONST0_RTX ( GET_MODE ( x ) ) ) return 1 ; if ( x == CONST1_RTX ( GET_MODE ( x ) ) ) return 2 ; if ( GET_MODE ( x ) == XFmode && ( optimize_size || x86_ext_80387_constants & TUNEMASK ) ) { REAL_VALUE_TYPE r ; int i ; if ( ! ext_80387_constants_init ) init_ext_80387_constants ( ) ; REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; for ( i = 0 ; i < 5 ; i ++ ) if ( real_identical ( & r , & ext_80387_constants_table [ i ] ) ) return i + 3 ; } return 0 ; } </s>

Return true if the constant is something that can be loaded with a special instruction .


<s> StringRef getPassName ( ) const override { return AARCH64_LOAD_STORE_OPT_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s>
bool
PPCInstrInfo
::
shouldReduceRegisterPressure
(
MachineBasicBlock
*
MBB
,
RegisterClassInfo
*
RegClassInfo
)
const
{
if
(
!
EnableFMARegPressureReduction
)
return
false
;
if
(
!
(
Subtarget
.
isPPC64
(
)
&&
Subtarget
.
hasP9Vector
(
)
&&
Subtarget
.
getTargetMachine
(
)
.
getCodeModel
(
)
==
CodeModel
::
Medium
)
)
return
false
;
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
MachineFunction
*
MF
=
MBB
->
getParent
(
)
;
MachineRegisterInfo
*
MRI
=
&
MF
->
getRegInfo
(
)
;
auto
GetMBBPressure
=
[
&
]
(
MachineBasicBlock
*
MBB
)
->
std
::
vector
<
unsigned
>
{
RegionPressure
Pressure
;
RegPressureTracker
RPTracker
(
Pressure
)
;
RPTracker
.
init
(
MBB
->
getParent
(
)
,
RegClassInfo
,
nullptr
,
MBB
,
MBB
->
end
(
)
,
false
,
true
)
;
for
(
MachineBasicBlock
::
iterator
MII
=
MBB
->
instr_end
(
)
,
MIE
=
MBB
->
instr_begin
(
)
;
MII
!=
MIE
;
MII
)
{
MachineInstr
&
MI
=
*
std
::
prev
(
MII
)
;
if
(
MI
.
isDebugValue
(
)
||
MI
.
isDebugLabel
(
)
)
continue
;
RegisterOperands
RegOpers
;
RegOpers
.
collect
(
MI
,
*
TRI
,
*
MRI
,
false
,
false
)
;
RPTracker
.
recedeSkipDebugValues
(
)
;
assert
(
&
*
RPTracker
.
getPos
(
)
==
&
MI
&&
"RPTracker sync error!"
)
;
RPTracker
.
recede
(
RegOpers
)
;
}
RPTracker
.
closeRegion
(
)
;
return
RPTracker
.
getPressure
(
)
.
MaxSetPressure
;
}
;
unsigned
VSSRCLimit
=
TRI
->
getRegPressureSetLimit
(
*
MBB
->
getParent
(
)
,
PPC
::
RegisterPressureSets
::
VSSRC
)
;
return
GetMBBPressure
(
MBB
)
[
PPC
::
RegisterPressureSets
::
VSSRC
]
>
(
float
)
VSSRCLimit
*
FMARPFactor
;
}
</s>

Return true if target supports reassociation of instructions in machine combiner pass to reduce register pressure for a given BB .

PowerPC
PPC
PPC
"RPTracker sync error!"
PPC::RegisterPressureSets
PPC::RegisterPressureSets


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { const DLXSubtarget & Subtarget = MF . getSubtarget < DLXSubtarget > ( ) ; TII = Subtarget . getInstrInfo ( ) ; TRI = Subtarget . getRegisterInfo ( ) ; bool Changed = false ; for ( MachineFunction :: iterator FI = MF . begin ( ) , FE = MF . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; return Changed ; } </s>


"Unexpected register class in CSRsViaCopy!"

"Function should be nounwind in insertCopiesSplitCSR!"

Insert explicit copies in entry and exit blocks .


<s>
const
uint32_t
*
AArch64RegisterInfo
::
getThisReturnPreservedMask
(
CallingConv
::
ID
CC
)
const
{
assert
(
CC
!=
CallingConv
::
GHC
&&
"should not be GHC calling convention."
)
;
return
CSR_AArch64_AAPCS_ThisReturn_RegMask
;
}
</s>

getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned ' is on an i32 first argument if the calling convention is one that can ( partially ) model this attribute with a preserved mask ( i.e .


<s>
scalar_chain
::
scalar_chain
(
)
{
chain_id
=
++
max_id
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Created a new instruction chain #%d\n"
,
chain_id
)
;
bitmap_obstack_initialize
(
)
;
insns
=
BITMAP_ALLOC
(
)
;
defs
=
BITMAP_ALLOC
(
)
;
defs_conv
=
BITMAP_ALLOC
(
)
;
queue
=
;
}
</s>


<s> OperandMatchResultTy SparcAsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { const AsmToken & Tok = Parser . getTok ( ) ; StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; RegNo = 0 ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Percent ) return MatchOperand_Success ; Parser . Lex ( ) ; unsigned regKind = SparcOperand :: rk_None ; if ( matchRegisterName ( Tok , RegNo , regKind ) ) { Parser . Lex ( ) ; return MatchOperand_Success ; } getLexer ( ) . UnLex ( Tok ) ; return MatchOperand_NoMatch ; } </s>

tryParseRegister - parse one register if possible


<s> void XCorePassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( & getXCoreTargetMachine ( ) ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> void WebAssemblyExceptionInfo :: recalculate ( MachineDominatorTree & MDT , const MachineDominanceFrontier & MDF ) { SmallVector < WebAssemblyException * , 8 > Exceptions ; for ( auto DomNode : post_order ( & MDT ) ) { MachineBasicBlock * EHPad = DomNode -> getBlock ( ) ; if ( ! EHPad -> isEHPad ( ) ) continue ; auto * WE = new WebAssemblyException ( EHPad ) ; discoverAndMapException ( WE , MDT , MDF ) ; Exceptions . push_back ( WE ) ; } for ( auto DomNode : post_order ( & MDT ) ) { MachineBasicBlock * MBB = DomNode -> getBlock ( ) ; WebAssemblyException * WE = getExceptionFor ( MBB ) ; for ( ; WE ; WE = WE -> getParentException ( ) ) WE -> addBlock ( MBB ) ; } for ( auto * WE : Exceptions ) { if ( WE -> getParentException ( ) ) WE -> getParentException ( ) -> getSubExceptions ( ) . push_back ( WE ) ; else addTopLevelException ( WE ) ; } for ( auto * WE : Exceptions ) { WE -> reverseBlock ( ) ; std :: reverse ( WE -> getSubExceptions ( ) . begin ( ) , WE -> getSubExceptions ( ) . end ( ) ) ; } } </s>

Notify DTU that the entry block was replaced .

WebAssembly WebAssembly WebAssembly 8 WebAssembly WebAssembly


<s> int m32c_trampoline_alignment ( void ) { return 2 ; } </s>


<s> EVT X86TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool NonScalarIntSafe , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( NonScalarIntSafe && ! F -> hasFnAttr ( Attribute :: NoImplicitFloat ) ) { if ( Size >= 16 && ( Subtarget -> isUnalignedMemAccessFast ( ) || ( ( DstAlign == 0 || DstAlign >= 16 ) && ( SrcAlign == 0 || SrcAlign >= 16 ) ) ) && Subtarget -> getStackAlignment ( ) >= 16 ) { if ( Subtarget -> hasSSE2 ( ) ) return MVT :: v4i32 ; if ( Subtarget -> hasSSE1 ( ) ) return MVT :: v4f32 ; } else if ( ! MemcpyStrSrc && Size >= 8 && ! Subtarget -> is64Bit ( ) && Subtarget -> getStackAlignment ( ) >= 8 && Subtarget -> hasSSE2 ( ) ) { return MVT :: f64 ; } } if ( Subtarget -> is64Bit ( ) && Size >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> RCPair ARMTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: tGPRRegClass ) ; return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'h' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: hGPRRegClass ) ; break ; case 'r' : if ( Subtarget -> isThumb1Only ( ) ) return RCPair ( 0U , & ARM :: tGPRRegClass ) ; return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'w' : if ( VT == MVT :: Other ) break ; if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPRRegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPRRegClass ) ; break ; case 'x' : if ( VT == MVT :: Other ) break ; if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPR_8RegClass ) ; break ; case 't' : if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( ARM :: CPSR ) , & ARM :: CCRRegClass ) ; return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> const MCExpr * X86ELFTargetObjectFile :: getDebugThreadLocalSymbol ( const MCSymbol * Sym ) const { return MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_DTPOFF , getContext ( ) ) ; } </s>

Describe a TLS variable address within debug info .


<s> static section * alpha_elf_select_rtx_section ( machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ) { if ( TARGET_SMALL_DATA && GET_MODE_SIZE ( mode ) <= g_switch_value ) return sdata_section ; else return default_elf_select_rtx_section ( mode , x , align ) ; } </s>

Switch to the section to which we should output X . The only thing special we do here is to honor small data .


<s> static rtx aarch64_strip_extend ( rtx x ) { rtx op = x ; if ( ( GET_CODE ( op ) == ZERO_EXTRACT || GET_CODE ( op ) == SIGN_EXTRACT ) && XEXP ( op , 2 ) == const0_rtx && GET_CODE ( XEXP ( op , 0 ) ) == MULT && aarch64_is_extend_from_extract ( GET_MODE ( op ) , XEXP ( XEXP ( op , 0 ) , 1 ) , XEXP ( op , 1 ) ) ) return XEXP ( XEXP ( op , 0 ) , 0 ) ; if ( GET_CODE ( op ) == AND && GET_CODE ( XEXP ( op , 0 ) ) == MULT && CONST_INT_P ( XEXP ( XEXP ( op , 0 ) , 1 ) ) && CONST_INT_P ( XEXP ( op , 1 ) ) && aarch64_uxt_size ( exact_log2 ( INTVAL ( XEXP ( XEXP ( op , 0 ) , 1 ) ) ) , INTVAL ( XEXP ( op , 1 ) ) ) != 0 ) return XEXP ( XEXP ( op , 0 ) , 0 ) ; if ( GET_CODE ( op ) == ASHIFT && CONST_INT_P ( XEXP ( op , 1 ) ) && ( ( unsigned HOST_WIDE_INT ) INTVAL ( XEXP ( op , 1 ) ) ) <= 4 ) op = XEXP ( op , 0 ) ; if ( GET_CODE ( op ) == ZERO_EXTEND || GET_CODE ( op ) == SIGN_EXTEND ) op = XEXP ( op , 0 ) ; if ( op != x ) return op ; return x ; } </s>

Helper function for rtx cost calculation . Strip an extend expression from X . Returns the inner operand if successful , or the original expression on failure . We deal with a number of possible canonicalization variations here .


<s> static rtx rs6000_emit_stack_reset ( rs6000_stack_t * info , rtx frame_reg_rtx , HOST_WIDE_INT frame_off , unsigned updt_regno ) { if ( frame_off == 0 && REGNO ( frame_reg_rtx ) == updt_regno ) return NULL_RTX ; rtx updt_reg_rtx = gen_rtx_REG ( Pmode , updt_regno ) ; if ( DEFAULT_ABI == ABI_V4 || ( TARGET_SPE_ABI && info -> spe_64bit_regs_used != 0 && info -> first_gp_reg_save != 32 ) ) return emit_insn ( gen_stack_restore_tie ( updt_reg_rtx , frame_reg_rtx , GEN_INT ( frame_off ) ) ) ; if ( frame_off != 0 ) return emit_insn ( gen_add3_insn ( updt_reg_rtx , frame_reg_rtx , GEN_INT ( frame_off ) ) ) ; else return emit_move_insn ( updt_reg_rtx , frame_reg_rtx ) ; return NULL_RTX ; } </s>

Emit a sequence of insns , including a stack tie if needed , for resetting the stack pointer . If UPDT_REGNO is not 1 , then do n't reset the stack pointer , but move the base of the frame into reg UPDT_REGNO for use by out-of-line register restore routines .


<s> static void recombine_lvx_stvx_patterns ( function * fun ) { int i ; basic_block bb ; rtx_insn * insn ; int num_insns = get_max_uid ( ) ; del_info * to_delete = XCNEWVEC ( del_info , num_insns ) ; FOR_ALL_BB_FN ( bb , fun ) FOR_BB_INSNS ( bb , insn ) { if ( ! NONDEBUG_INSN_P ( insn ) ) continue ; if ( insn_is_load_p ( insn ) && insn_is_swap_p ( insn ) ) recombine_lvx_pattern ( insn , to_delete ) ; else if ( insn_is_store_p ( insn ) && insn_is_swap_p ( insn ) ) recombine_stvx_pattern ( insn , to_delete ) ; } for ( i = 0 ; i < num_insns ; i ++ ) if ( to_delete [ i ] . replace ) { rtx swap_body = PATTERN ( to_delete [ i ] . replace_insn ) ; rtx src_reg = XEXP ( SET_SRC ( swap_body ) , 0 ) ; rtx copy = gen_rtx_SET ( SET_DEST ( swap_body ) , src_reg ) ; rtx_insn * new_insn = emit_insn_before ( copy , to_delete [ i ] . replace_insn ) ; set_block_for_insn ( new_insn , BLOCK_FOR_INSN ( to_delete [ i ] . replace_insn ) ) ; df_insn_rescan ( new_insn ) ; df_insn_delete ( to_delete [ i ] . replace_insn ) ; remove_insn ( to_delete [ i ] . replace_insn ) ; to_delete [ i ] . replace_insn -> set_deleted ( ) ; } free ( to_delete ) ; } </s>

Look for patterns created from builtin lvx and stvx calls , and canonicalize them to be properly recognized as such .


<s> EVT PPCTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned Align , bool isSrcConst , bool isSrcStr , SelectionDAG & DAG ) const { if ( this -> PPCSubTarget . isPPC64 ( ) ) { return MVT :: i64 ; } else { return MVT :: i32 ; } } </s>


<s> static bool is_store_insn ( rtx insn , rtx * str_mem ) { if ( ! insn || ! INSN_P ( insn ) ) return false ; return is_store_insn1 ( PATTERN ( insn ) , str_mem ) ; } </s>


<s> static unsigned int m68k_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( regno >= 16 ) return GET_MODE_NUNITS ( mode ) ; return CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ; } </s>

Implement TARGET_HARD_REGNO_NREGS . On the m68k , ordinary registers hold 32 bits worth ; for the 68881 registers , a single register is always enough for anything that can be stored in them at all .


<s> static machine_mode aarch64_simd_container_mode ( machine_mode mode , unsigned width ) { gcc_assert ( width == 64 || width == 128 ) ; if ( TARGET_SIMD ) { if ( width == 128 ) switch ( mode ) { case DFmode : return V2DFmode ; case SFmode : return V4SFmode ; case HFmode : return V8HFmode ; case SImode : return V4SImode ; case HImode : return V8HImode ; case QImode : return V16QImode ; case DImode : return V2DImode ; default : break ; } else switch ( mode ) { case SFmode : return V2SFmode ; case HFmode : return V4HFmode ; case SImode : return V2SImode ; case HImode : return V4HImode ; case QImode : return V8QImode ; default : break ; } } return word_mode ; } </s>

Return appropriate SIMD container for MODE within a vector of WIDTH bits .


<s> const char * AMDGPUPALMetadata :: getVendor ( ) const { return isLegacy ( ) ? ElfNote :: NoteNameV2 : ElfNote :: NoteNameV3 ; } </s>

Get the parsed vendor type of this triple .


<s> static bool rs6000_secondary_reload_simple_move ( enum rs6000_reg_type to_type , enum rs6000_reg_type from_type , machine_mode mode ) { int size = GET_MODE_SIZE ( mode ) ; if ( TARGET_DIRECT_MOVE && ( ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) || ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) { if ( TARGET_POWERPC64 ) { if ( size == 8 ) return true ; if ( size == 16 && TARGET_P9_VECTOR && mode != TDmode ) return true ; } if ( TARGET_P8_VECTOR ) { if ( mode == SImode ) return true ; if ( TARGET_P9_VECTOR && ( mode == HImode || mode == QImode ) ) return true ; } if ( mode == SDmode ) return true ; } else if ( TARGET_MFPGPR && TARGET_POWERPC64 && size == 8 && ( ( to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE ) || ( to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; else if ( ( size == 4 || ( TARGET_POWERPC64 && size == 8 ) ) && ( ( to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE ) || ( to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; return false ; } </s>

Helper function for rs6000_secondary_reload to return true if a move to a different register classe is really a simple move .


<s> static unsigned HOST_WIDE_INT mips_asan_shadow_offset ( void ) { return SUBTARGET_SHADOW_OFFSET ; } </s>

Implement the TARGET_ASAN_SHADOW_OFFSET hook .


<s> void AArch64PassConfig :: addPreEmitPass ( ) { if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Aggressive && EnableLoadStoreOpt ) addPass ( createAArch64LoadStoreOptimizationPass ( ) ) ; if ( EnableA53Fix835769 ) addPass ( createAArch64A53Fix835769 ( ) ) ; if ( EnableBranchTargets ) addPass ( createAArch64BranchTargetsPass ( ) ) ; if ( BranchRelaxation ) addPass ( & BranchRelaxationPassID ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) { addPass ( createCFGuardLongjmpPass ( ) ) ; addPass ( createEHContGuardCatchretPass ( ) ) ; } if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCompressJumpTables ) addPass ( createAArch64CompressJumpTablesPass ( ) ) ; addPass ( createAArch64ExpandHardenedPseudosPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool HexagonInstrInfo :: isPredicated ( unsigned Opcode ) const { const uint64_t F = get ( Opcode ) . TSFlags ; return ( ( F >> HexagonII :: PredicatedPos ) & HexagonII :: PredicatedMask ) ; } </s>

Returns true if the instruction is already predicated .

Hexagon Hexagon HexagonII::PredicatedPos HexagonII::PredicatedMask


<s> static rtx nds32_expand_scw_builtin ( enum insn_code icode , tree exp , rtx target ) { rtx pat ; rtx op0 = nds32_read_argument ( exp , 0 ) ; rtx op1 = nds32_read_argument ( exp , 1 ) ; rtx addr_helper = gen_reg_rtx ( insn_data [ icode ] . operand [ 1 ] . mode ) ; target = nds32_legitimize_target ( icode , target ) ; op0 = nds32_legitimize_argument ( icode , 1 , op0 ) ; op1 = nds32_legitimize_argument ( icode , 2 , op1 ) ; pat = GEN_FCN ( icode ) ( target , op0 , addr_helper , target ) ; if ( ! pat ) return NULL_RTX ; emit_move_insn ( addr_helper , GEN_INT ( 0 ) ) ; emit_move_insn ( target , op1 ) ; emit_insn ( pat ) ; return target ; } </s>


<s> Optional < MCDisassembler :: DecodeStatus > MOSDisassembler :: onSymbolStart ( SymbolInfoTy & Symbol , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CStream ) const { if ( Has65816 ) { if ( Symbol . Name . startswith ( "$ml" ) ) MLow = true ; else if ( Symbol . Name . startswith ( "$mh" ) ) MLow = false ; else if ( Symbol . Name . startswith ( "$xl" ) ) XLow = true ; else if ( Symbol . Name . startswith ( "$xh" ) ) XLow = false ; } return None ; } </s>

Used to perform separate target specific disassembly for a particular symbol .


<s> machine_mode mmix_promote_function_mode ( const_tree type ATTRIBUTE_UNUSED , machine_mode mode , int * punsignedp ATTRIBUTE_UNUSED , const_tree fntype ATTRIBUTE_UNUSED , int for_return ) { if ( for_return == 1 ) return mode ; if ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) < 8 ) return DImode ; else return mode ; } </s>

Worker function for TARGET_PROMOTE_FUNCTION_MODE .


<s>
bool
MipsCodeEmitter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MipsTargetMachine
&
Target
=
static_cast
<
MipsTargetMachine
&
>
(
const_cast
<
TargetMachine
&
>
(
MF
.
getTarget
(
)
)
)
;
JTI
=
Target
.
getJITInfo
(
)
;
II
=
Target
.
getInstrInfo
(
)
;
TD
=
Target
.
getDataLayout
(
)
;
Subtarget
=
&
TM
.
getSubtarget
<
MipsSubtarget
>
(
)
;
MCPEs
=
&
MF
.
getConstantPool
(
)
->
getConstants
(
)
;
MJTEs
=
nullptr
;
if
(
MF
.
getJumpTableInfo
(
)
)
MJTEs
=
&
MF
.
getJumpTableInfo
(
)
->
getJumpTables
(
)
;
JTI
->
Initialize
(
MF
,
IsPIC
,
Subtarget
->
isLittle
(
)
)
;
MCE
.
setModuleInfo
(
&
getAnalysis
<
MachineModuleInfo
>
(
)
)
;
do
{
DEBUG
(
errs
(
)
<<
"JITTing function '"
<<
MF
.
getName
(
)
<<
"'\n"
)
;
MCE
.
startFunction
(
MF
)
;
for
(
MachineFunction
::
iterator
MBB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBB
!=
E
;
++
MBB
)
{
MCE
.
StartMachineBasicBlock
(
MBB
)
;
for
(
MachineBasicBlock
::
instr_iterator
I
=
MBB
->
instr_begin
(
)
,
E
=
MBB
->
instr_end
(
)
;
I
!=
E
;
)
emitInstruction
(
*
I
++
,
*
MBB
)
;
}
}
while
(
MCE
.
finishFunction
(
MF
)
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .

Mips
Mips
Mips
Mips
Mips
"JITTing function '"
"'\n"


<s> virtual MachineInstr * foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const { return 0 ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> bool R600InstrInfo :: isVector ( const MachineInstr & MI ) const { return get ( MI . getOpcode ( ) ) . TSFlags & R600_InstFlag :: VECTOR ; } </s>

Vector instructions are instructions that must fill all instruction slots within an instruction group .


<s> static void mips_legitimize_const_move ( enum machine_mode mode , rtx dest , rtx src ) { rtx base ; HOST_WIDE_INT offset ; enum mips_symbol_type symbol_type ; if ( GET_CODE ( src ) == CONST_INT && ! TARGET_MIPS16 ) { mips_move_integer ( dest , INTVAL ( src ) ) ; return ; } if ( mips_tls_operand_p ( src ) ) { emit_move_insn ( dest , mips_legitimize_tls_address ( src ) ) ; return ; } if ( ! TARGET_MIPS16 && mips_symbolic_constant_p ( src , & symbol_type ) && mips_split_p [ symbol_type ] ) { emit_move_insn ( dest , mips_split_symbol ( dest , src ) ) ; return ; } mips_split_const ( src , & base , & offset ) ; if ( ! TARGET_MIPS16 && offset != 0 && ( ! no_new_pseudos || SMALL_OPERAND ( offset ) ) ) { base = mips_force_temporary ( dest , base ) ; emit_move_insn ( dest , mips_add_offset ( 0 , base , offset ) ) ; return ; } src = force_const_mem ( mode , src ) ; if ( ! memory_operand ( src , VOIDmode ) ) src = replace_equiv_address ( src , mips_split_symbol ( dest , XEXP ( src , 0 ) ) ) ; emit_move_insn ( dest , src ) ; } </s>

Subroutine of mips_legitimize_move . Move constant SRC into register DEST given that SRC satisfies immediate_operand but does n't satisfy move_operand .


<s>
void
cris_asm_output_case_end
(
FILE
*
stream
,
int
num
,
rtx
table
)
{
rtx
whole_jump_insn
=
prev_nonnote_nondebug_insn
(
table
)
;
gcc_assert
(
whole_jump_insn
!=
NULL_RTX
&&
LABEL_P
(
whole_jump_insn
)
)
;
whole_jump_insn
=
prev_nonnote_nondebug_insn
(
whole_jump_insn
)
;
gcc_assert
(
whole_jump_insn
!=
NULL_RTX
&&
(
JUMP_P
(
whole_jump_insn
)
||
(
TARGET_V32
&&
INSN_P
(
whole_jump_insn
)
&&
GET_CODE
(
PATTERN
(
whole_jump_insn
)
)
==
SEQUENCE
)
)
)
;
whole_jump_insn
=
PATTERN
(
whole_jump_insn
)
;
if
(
TARGET_V32
)
{
rtx
parallel_jump
=
(
GET_CODE
(
whole_jump_insn
)
==
SEQUENCE
PATTERN
(
XVECEXP
(
whole_jump_insn
,
0
,
0
)
)
:
whole_jump_insn
)
;
asm_fprintf
(
stream
,
"\t.word %LL%d-.%s\n"
,
CODE_LABEL_NUMBER
(
XEXP
(
XEXP
(
XEXP
(
XVECEXP
(
parallel_jump
,
0
,
0
)
,
1
)
,
2
)
,
0
)
)
,
(
TARGET_PDEBUG
"; default"
:
""
)
)
;
return
;
}
asm_fprintf
(
stream
,
"\t.word %LL%d-%LL%d%s\n"
,
CODE_LABEL_NUMBER
(
XEXP
(
XEXP
(
XEXP
(
XVECEXP
(
whole_jump_insn
,
0
,
0
)
,
1
)
,
2
)
,
0
)
)
,
num
,
(
TARGET_PDEBUG
"; default"
:
""
)
)
;
}
</s>


<s> void AArch64PostLegalizerCombiner :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < TargetPassConfig > ( ) ; AU . setPreservesCFG ( ) ; getSelectionDAGFallbackAnalysisUsage ( AU ) ; AU . addRequired < GISelKnownBitsAnalysis > ( ) ; AU . addPreserved < GISelKnownBitsAnalysis > ( ) ; if ( ! IsOptNone ) { AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; } MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool ARMBaseTargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt :: None ) { if ( ! Subtarget . isThumb1Only ( ) ) PM . add ( createIfConverterPass ( ) ) ; if ( Subtarget . hasNEON ( ) ) PM . add ( createNEONMoveFixPass ( ) ) ; } if ( Subtarget . isThumb2 ( ) ) { PM . add ( createThumb2ITBlockPass ( ) ) ; PM . add ( createThumb2SizeReductionPass ( ) ) ; } PM . add ( createARMConstantIslandPass ( ) ) ; return true ; } </s>


<s> static bool isConstant ( const MachineInstr & MI ) { return MI . getOpcode ( ) == TargetOpcode :: G_CONSTANT ; } </s>

Returns true if we know the value of all bits .


"Unknown form for stack limit expression"

Emit conditional trap for checking stack limit .


<s> static unsigned int spu_hard_regno_nregs ( unsigned int , machine_mode mode ) { return CEIL ( GET_MODE_BITSIZE ( mode ) , MAX_FIXED_MODE_SIZE ) ; } </s>


<s> StringRef getPassName ( ) const override { return OPTADDRMODE_DESC ; } </s>

getPassName - Return a nice clean name for a pass .


<s> BitVector MipsRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t ReservedCPURegs [ ] = { Mips :: ZERO , Mips :: AT , Mips :: K0 , Mips :: K1 , Mips :: SP , Mips :: FP , Mips :: RA } ; static const uint16_t ReservedCPU64Regs [ ] = { Mips :: ZERO_64 , Mips :: AT_64 , Mips :: K0_64 , Mips :: K1_64 , Mips :: SP_64 , Mips :: FP_64 , Mips :: RA_64 } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: iterator RegIter ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; if ( Subtarget . hasMips64 ( ) ) { for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPU64Regs ) ; ++ I ) Reserved . set ( ReservedCPU64Regs [ I ] ) ; for ( RegIter Reg = Mips :: AFGR64RegisterClass -> begin ( ) ; Reg != Mips :: AFGR64RegisterClass -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ; } else { for ( RegIter Reg = Mips :: CPU64RegsRegisterClass -> begin ( ) ; Reg != Mips :: CPU64RegsRegisterClass -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ; for ( RegIter Reg = Mips :: FGR64RegisterClass -> begin ( ) ; Reg != Mips :: FGR64RegisterClass -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ; } if ( MF . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegFixed ( ) ) { Reserved . set ( Mips :: GP ) ; Reserved . set ( Mips :: GP_64 ) ; } Reserved . set ( Mips :: HWR29 ) ; Reserved . set ( Mips :: HWR29_64 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static bool mips_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { return ( to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM ) ; } </s>

Make sure that we 're not trying to eliminate to the wrong hard frame pointer .


<s>
void
ARMTTIImpl
::
getUnrollingPreferences
(
Loop
*
L
,
ScalarEvolution
&
SE
,
TTI
::
UnrollingPreferences
&
UP
)
{
if
(
!
ST
->
isMClass
(
)
)
return
BasicTTIImplBase
::
getUnrollingPreferences
(
L
,
SE
,
UP
)
;
UP
.
OptSizeThreshold
=
0
;
UP
.
PartialOptSizeThreshold
=
0
;
if
(
L
->
getHeader
(
)
->
getParent
(
)
->
hasOptSize
(
)
)
return
;
if
(
!
ST
->
isThumb2
(
)
)
return
;
SmallVector
<
BasicBlock
*
,
4
>
ExitingBlocks
;
L
->
getExitingBlocks
(
ExitingBlocks
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Loop has:\n"
<<
"Blocks: "
<<
L
->
getNumBlocks
(
)
<<
"\n"
<<
"Exit blocks: "
<<
ExitingBlocks
.
size
(
)
<<
"\n"
)
;
if
(
ExitingBlocks
.
size
(
)
>
2
)
return
;
if
(
ST
->
hasBranchPredictor
(
)
&&
L
->
getNumBlocks
(
)
>
4
)
return
;
unsigned
Cost
=
0
;
for
(
auto
*
BB
:
L
->
getBlocks
(
)
)
{
for
(
auto
&
I
:
*
BB
)
{
if
(
isa
<
CallInst
>
(
I
)
||
isa
<
InvokeInst
>
(
I
)
)
{
ImmutableCallSite
CS
(
&
I
)
;
if
(
const
Function
*
F
=
CS
.
getCalledFunction
(
)
)
{
if
(
!
isLoweredToCall
(
F
)
)
continue
;
}
return
;
}
SmallVector
<
const
Value
*
,
4
>
Operands
(
I
.
value_op_begin
(
)
,
I
.
value_op_end
(
)
)
;
Cost
+=
getUserCost
(
&
I
,
Operands
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Cost of loop: "
<<
Cost
<<
"\n"
)
;
UP
.
Partial
=
true
;
UP
.
Runtime
=
true
;
UP
.
UnrollRemainder
=
true
;
UP
.
DefaultUnrollRuntimeCount
=
4
;
UP
.
UnrollAndJam
=
true
;
UP
.
UnrollAndJamInnerLoopThreshold
=
60
;
if
(
Cost
<
12
)
UP
.
Force
=
true
;
}
</s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> int direct_return ( void ) { if ( reload_completed ) { if ( cfun -> static_chain_decl == 0 && ( spu_saved_regs_size ( ) + get_frame_size ( ) + crtl -> outgoing_args_size + crtl -> args . pretend_args_size == 0 ) && crtl -> is_leaf ) return 1 ; } return 0 ; } </s>

Return non-zero if this function is known to have a null epilogue .


<s>
void
SystemZMCAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
MCFixupKind
Kind
=
Fixup
.
getKind
(
)
;
if
(
Kind
>=
FirstLiteralRelocationKind
)
return
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
unsigned
BitSize
=
getFixupKindInfo
(
Kind
)
.
TargetSize
;
unsigned
Size
=
(
BitSize
+
7
)
/
8
;
assert
(
Offset
+
Size
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
Value
=
extractBitsForFixup
(
Kind
,
Value
)
;
if
(
BitSize
<
64
)
Value
&=
(
(
uint64_t
)
1
<<
BitSize
)
1
;
unsigned
ShiftValue
=
(
Size
*
8
)
8
;
for
(
unsigned
I
=
0
;
I
!=
Size
;
++
I
)
{
Data
[
Offset
+
I
]
|=
uint8_t
(
Value
>>
ShiftValue
)
;
ShiftValue
-=
8
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void MipsTargetMachine :: resetSubtarget ( MachineFunction * MF ) { LLVM_DEBUG ( dbgs ( ) << "resetSubtarget\n" ) ; Subtarget = const_cast < MipsSubtarget * > ( getSubtargetImpl ( MF -> getFunction ( ) ) ) ; MF -> setSubtarget ( Subtarget ) ; } </s>

Reset the subtarget for the Mips target .


<s> bool MipsPassConfig :: addPreEmitPass ( ) { PM -> add ( createMipsDelaySlotFillerPass ( getMipsTargetMachine ( ) ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
SDValue
J2TargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
assert
(
!
isVarArg
&&
"Variable arguments not supported."
)
;
auto
&
MF
=
DAG
.
getMachineFunction
(
)
;
SmallVector
<
CCValAssign
,
4
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
MF
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_J2
)
;
SmallVector
<
SDValue
,
4
>
RetOps
{
Chain
}
;
SDValue
Glue
;
for
(
size_t
i
=
0
;
i
<
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Return in memory is not supported!"
)
;
SDValue
ValToCopy
=
OutVals
[
i
]
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
ValToCopy
,
Glue
)
;
Glue
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Glue
.
getNode
(
)
)
RetOps
.
push_back
(
Glue
)
;
return
DAG
.
getNode
(
J2ISD
::
Ret
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s>
static
raw_ostream
&
printName
(
raw_ostream
&
OS
,
StringRef
Name
)
{
return
OS
<<
Name
<<
" = "
;
}
</s>


<s> void X86InsertPrefetch :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesAll ( ) ; AU . addRequired < MachineModuleInfoWrapperPass > ( ) ; } </s>


<s>
static
void
rs6000_elf_asm_out_constructor
(
rtx
symbol
,
int
priority
)
{
const
char
*
section
=
".ctors"
;
char
buf
[
18
]
;
if
(
priority
!=
DEFAULT_INIT_PRIORITY
)
{
sprintf
(
buf
,
".ctors.%.5u"
,
MAX_INIT_PRIORITY
priority
)
;
section
=
buf
;
}
switch_to_section
(
get_section
(
section
,
SECTION_WRITE
,
)
)
;
assemble_align
(
POINTER_SIZE
)
;
if
(
DEFAULT_ABI
==
ABI_V4
&&
(
TARGET_RELOCATABLE
||
flag_pic
>
1
)
)
{
fputs
(
"\t.long ("
,
asm_out_file
)
;
output_addr_const
(
asm_out_file
,
symbol
)
;
fputs
(
")@fixup\n"
,
asm_out_file
)
;
}
else
assemble_integer
(
symbol
,
POINTER_SIZE
/
BITS_PER_UNIT
,
POINTER_SIZE
,
1
)
;
}
</s>