<s> bool xstormy16_below100_symbol ( rtx x , machine_mode mode ATTRIBUTE_UNUSED ) { if ( GET_CODE ( x ) == CONST ) x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , 1 ) ) ) x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == SYMBOL_REF ) return ( SYMBOL_REF_FLAGS ( x ) & SYMBOL_FLAG_XSTORMY16_BELOW100 ) != 0 ; if ( CONST_INT_P ( x ) ) { HOST_WIDE_INT i = INTVAL ( x ) ; if ( ( i >= 0x0000 && i <= 0x00ff ) || ( i >= 0x7f00 && i <= 0x7fff ) ) return 1 ; } return 0 ; } </s>

Predicate for symbols and addresses that reflect special 8-bit addressing .


<s> static bool arc_must_save_register ( int regno , struct function * func ) { unsigned int fn_type = arc_compute_function_type ( func ) ; bool irq_auto_save_p = ( ( irq_ctrl_saved . irq_save_last_reg >= regno ) && ARC_AUTO_IRQ_P ( fn_type ) ) ; bool firq_auto_save_p = ARC_FAST_INTERRUPT_P ( fn_type ) ; switch ( rgf_banked_register_count ) { case 4 : firq_auto_save_p &= ( regno < 4 ) ; break ; case 8 : firq_auto_save_p &= ( ( regno < 4 ) || ( ( regno > 11 ) && ( regno < 16 ) ) ) ; break ; case 16 : firq_auto_save_p &= ( ( regno < 4 ) || ( ( regno > 9 ) && ( regno < 16 ) ) || ( ( regno > 25 ) && ( regno < 29 ) ) || ( ( regno > 29 ) && ( regno < 32 ) ) ) ; break ; case 32 : firq_auto_save_p &= ( regno != 29 ) && ( regno < 32 ) ; break ; default : firq_auto_save_p = false ; break ; } if ( ( regno ) != RETURN_ADDR_REGNUM && ( regno ) != FRAME_POINTER_REGNUM && df_regs_ever_live_p ( regno ) && ( ! call_used_regs [ regno ] || ARC_INTERRUPT_P ( fn_type ) ) && ! irq_auto_save_p && ! firq_auto_save_p ) return true ; return false ; } </s>

Tell prologue and epilogue if register REGNO should be saved / restored . The return address , stack pointer and frame pointer are treated separately . Do n't consider them here . Addition for pic : The gp register needs to be saved if the current function changes it to access gotoff variables . FIXME : This will not be needed if we used some arbitrary register instead of r26 .


<s>
bool
WaitcntBrackets
::
merge
(
const
WaitcntBrackets
&
Other
)
{
bool
StrictDom
=
false
;
for
(
auto
T
:
inst_counter_types
(
)
)
{
const
bool
OldOutOfOrder
=
counterOutOfOrder
(
T
)
;
const
uint32_t
OldEvents
=
PendingEvents
&
WaitEventMaskForInst
[
T
]
;
const
uint32_t
OtherEvents
=
Other
.
PendingEvents
&
WaitEventMaskForInst
[
T
]
;
if
(
OtherEvents
&
~
OldEvents
)
StrictDom
=
true
;
if
(
Other
.
MixedPendingEvents
[
T
]
||
(
OldEvents
&&
OtherEvents
&&
OldEvents
!=
OtherEvents
)
)
MixedPendingEvents
[
T
]
=
true
;
PendingEvents
|=
OtherEvents
;
const
uint32_t
MyPending
=
ScoreUBs
[
T
]
ScoreLBs
[
T
]
;
const
uint32_t
OtherPending
=
Other
.
ScoreUBs
[
T
]
Other
.
ScoreLBs
[
T
]
;
MergeInfo
M
;
M
.
OldLB
=
ScoreLBs
[
T
]
;
M
.
OtherLB
=
Other
.
ScoreLBs
[
T
]
;
M
.
MyShift
=
OtherPending
>
MyPending
OtherPending
MyPending
:
0
;
M
.
OtherShift
=
ScoreUBs
[
T
]
Other
.
ScoreUBs
[
T
]
+
M
.
MyShift
;
const
uint32_t
NewUB
=
ScoreUBs
[
T
]
+
M
.
MyShift
;
if
(
NewUB
<
ScoreUBs
[
T
]
)
report_fatal_error
(
"waitcnt score overflow"
)
;
ScoreUBs
[
T
]
=
NewUB
;
ScoreLBs
[
T
]
=
std
::
min
(
M
.
OldLB
+
M
.
MyShift
,
M
.
OtherLB
+
M
.
OtherShift
)
;
StrictDom
|=
mergeScore
(
M
,
LastFlat
[
T
]
,
Other
.
LastFlat
[
T
]
)
;
bool
RegStrictDom
=
false
;
for
(
int
J
=
0
,
E
=
std
::
max
(
getMaxVGPR
(
)
,
Other
.
getMaxVGPR
(
)
)
+
1
;
J
!=
E
;
J
++
)
{
RegStrictDom
|=
mergeScore
(
M
,
VgprScores
[
T
]
[
J
]
,
Other
.
VgprScores
[
T
]
[
J
]
)
;
}
if
(
T
==
LGKM_CNT
)
{
for
(
int
J
=
0
,
E
=
std
::
max
(
getMaxSGPR
(
)
,
Other
.
getMaxSGPR
(
)
)
+
1
;
J
!=
E
;
J
++
)
{
RegStrictDom
|=
mergeScore
(
M
,
SgprScores
[
J
]
,
Other
.
SgprScores
[
J
]
)
;
}
}
if
(
RegStrictDom
&&
!
OldOutOfOrder
)
StrictDom
=
true
;
}
return
StrictDom
;
}
</s>


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { const ARMSubtarget & Subtarget = DAG . getMachineFunction ( ) . getSubtarget < ARMSubtarget > ( ) ; ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; if ( Subtarget . hasMVEIntegerOps ( ) && shouldGenerateInlineTPLoop ( Subtarget , DAG , ConstantSize , Alignment , false ) ) { Src = DAG . getSplatBuildVector ( MVT :: v16i8 , dl , DAG . getNode ( ISD :: TRUNCATE , dl , MVT :: i8 , Src ) ) ; return DAG . getNode ( ARMISD :: MEMSETLOOP , dl , MVT :: Other , Chain , Dst , Src , DAG . getZExtOrTrunc ( Size , dl , MVT :: i32 ) ) ; } return EmitSpecializedLibcall ( DAG , dl , Chain , Dst , Src , Size , Alignment . value ( ) , RTLIB :: MEMSET ) ; } </s>

Emit target-specific code that performs a memset .

ARM ARM ARM ARM MVT::v16i8 ISD::TRUNCATE MVT::i8 ARMISD::MEMSETLOOP MVT::Other MVT::i32


EXP is a pointer argument to a Neon load or store intrinsic . Derive and return an expression for the accessed memory . The intrinsic function operates on a block of registers that has mode REG_MODE . This block contains vectors of type TYPE_MODE . The function references the memory at EXP of type TYPE and in mode MEM_MODE ; this mode may be BLKmode if no more suitable mode is available .


<s> bool HexagonMCInstrInfo :: isDuplexPair ( MCInst const & MIa , MCInst const & MIb ) { unsigned MIaG = getDuplexCandidateGroup ( MIa ) , MIbG = getDuplexCandidateGroup ( MIb ) ; return ( isDuplexPairMatch ( MIaG , MIbG ) || isDuplexPairMatch ( MIbG , MIaG ) ) ; } </s>

Symmetrical . See if these two instructions are fit for duplex pair .


"Should only have register or immediate operands"

Legalize operands in MI by either commuting it or inserting a copy of src1 .


<s> void MSP430RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const MSP430FrameLowering * TFI = getFrameLowering ( MF ) ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned BasePtr = ( TFI -> hasFP ( MF ) ? MSP430 :: R4 : MSP430 :: SP ) ; int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) ; Offset += 2 ; if ( ! TFI -> hasFP ( MF ) ) Offset += MF . getFrameInfo ( ) . getStackSize ( ) ; else Offset += 2 ; Offset += MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ; if ( MI . getOpcode ( ) == MSP430 :: ADDframe ) { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MI . setDesc ( TII . get ( MSP430 :: MOV16rr ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; if ( Offset == 0 ) return ; Register DstReg = MI . getOperand ( 0 ) . getReg ( ) ; if ( Offset < 0 ) BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( MSP430 :: SUB16ri ) , DstReg ) . addReg ( DstReg ) . addImm ( - Offset ) ; else BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( MSP430 :: ADD16ri ) , DstReg ) . addReg ( DstReg ) . addImm ( Offset ) ; return ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool runOnMachineFunction ( MachineFunction & MF ) { for ( MachineFunction :: iterator bItr = MF . begin ( ) ; bItr != MF . end ( ) ; ++ bItr ) { bool foundTestFunc = false ; for ( MachineBasicBlock :: iterator iItr = bItr -> begin ( ) ; iItr != bItr -> end ( ) ; ++ iItr ) { if ( foundTestFunc ) { errs ( ) << * iItr << "\n" ; } if ( iItr -> isCall ( ) ) { MachineOperand MO = iItr -> getOperand ( 0 ) ; const GlobalValue * GV = MO . getGlobal ( ) ; std :: string funcName = GV -> getName ( ) ; if ( ! compareCallToFunctionNames ( funcName ) ) { foundTestFunc = false ; } else { foundTestFunc = true ; } } } } return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> rtx arm_gen_compare_reg ( rtx_code code , rtx x , rtx y , rtx scratch ) { if ( GET_MODE ( x ) == DImode || GET_MODE ( y ) == DImode ) return arm_gen_dicompare_reg ( code , x , y , scratch ) ; machine_mode mode = SELECT_CC_MODE ( code , x , y ) ; rtx cc_reg = gen_rtx_REG ( mode , CC_REGNUM ) ; if ( mode == CC_RSBmode ) { if ( ! scratch ) scratch = gen_rtx_SCRATCH ( SImode ) ; emit_insn ( gen_rsb_imm_compare_scratch ( scratch , GEN_INT ( ~ UINTVAL ( x ) ) , y ) ) ; } else emit_set_insn ( cc_reg , gen_rtx_COMPARE ( mode , x , y ) ) ; return cc_reg ; } </s>

X and Y are two things to compare using CODE . Emit the compare insn and return the rtx for register 0 in the proper mode . FP means this is a floating point compare : I do n't think that it is needed on the arm .


<s>
static
void
arm_output_fldmx
(
FILE
*
stream
,
unsigned
int
base
,
int
reg
,
int
count
)
{
int
i
;
if
(
count
==
2
&&
!
arm_arch6
)
{
if
(
reg
==
15
)
reg
;
count
++
;
}
fputc
(
'\t'
,
stream
)
;
asm_fprintf
(
stream
,
"fldmfdx\t%r!, {"
,
base
)
;
for
(
i
=
reg
;
i
<
reg
+
count
;
i
++
)
{
if
(
i
>
reg
)
fputs
(
", "
,
stream
)
;
asm_fprintf
(
stream
,
"d%d"
,
i
)
;
}
fputs
(
"}\n"
,
stream
)
;
}
</s>

Output a FLDMX instruction to STREAM . BASE if the register containing the address . REG and COUNT specify the register range . Extra registers may be added to avoid hardware bugs .


<s> static bool nvptx_return_in_memory ( const_tree type , const_tree ) { return pass_in_memory ( TYPE_MODE ( type ) , type , true ) ; } </s>


<s> static const char * arm_identify_fpu_from_isa ( sbitmap isa ) { auto_sbitmap fpubits ( isa_num_bits ) ; auto_sbitmap cand_fpubits ( isa_num_bits ) ; bitmap_and ( fpubits , isa , isa_all_fpubits_internal ) ; if ( bitmap_empty_p ( fpubits ) ) return "softvfp" ; for ( unsigned int i = 0 ; i < TARGET_FPU_auto ; i ++ ) { arm_initialize_isa ( cand_fpubits , all_fpus [ i ] . isa_bits ) ; if ( bitmap_equal_p ( fpubits , cand_fpubits ) ) return all_fpus [ i ] . name ; } gcc_unreachable ( ) ; } </s>

Match an ISA feature bitmap to a named FPU . We always use the first entry that exactly matches the feature set , so that we effectively canonicalize the FPU name for the assembler .


<s> unsigned SparcCodeEmitter :: getBranchTargetOpValue ( const MachineInstr & MI , unsigned opIdx ) const { const MachineOperand MO = MI . getOperand ( opIdx ) ; return getMachineOpValue ( MI , MO ) ; } </s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s> bool mergeStoresAfterLegalization ( ) const override { return false ; } </s>

Do not merge vector stores after legalization because that may conflict with x86-specific store splitting optimizations .


<s> void Mips16TargetLowering :: getOpndList ( SmallVectorImpl < SDValue > & Ops , std :: deque < std :: pair < unsigned , SDValue > > & RegsToPass , bool IsPICCall , bool GlobalOrExternal , bool InternalLinkage , CallLoweringInfo & CLI , SDValue Callee , SDValue Chain ) const { SelectionDAG & DAG = CLI . DAG ; const char * Mips16HelperFunction = 0 ; bool NeedMips16Helper = false ; if ( getTargetMachine ( ) . Options . UseSoftFloat && Subtarget -> inMips16HardFloat ( ) ) { bool LookupHelper = true ; if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( CLI . Callee ) ) { Mips16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , S -> getSymbol ( ) } ; if ( std :: binary_search ( HardFloatLibCalls , array_endof ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; } else if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( CLI . Callee ) ) { Mips16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , G -> getGlobal ( ) -> getName ( ) . data ( ) } ; if ( std :: binary_search ( HardFloatLibCalls , array_endof ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; } if ( LookupHelper ) Mips16HelperFunction = getMips16HelperFunction ( CLI . RetTy , CLI . Args , NeedMips16Helper ) ; } SDValue JumpTarget = Callee ; if ( IsPICCall || ! GlobalOrExternal ) { unsigned V0Reg = Mips :: V0 ; if ( NeedMips16Helper ) { RegsToPass . push_front ( std :: make_pair ( V0Reg , Callee ) ) ; JumpTarget = DAG . getExternalSymbol ( Mips16HelperFunction , getPointerTy ( ) ) ; JumpTarget = getAddrGlobal ( JumpTarget , DAG , MipsII :: MO_GOT ) ; } else RegsToPass . push_front ( std :: make_pair ( ( unsigned ) Mips :: T9 , Callee ) ) ; } Ops . push_back ( JumpTarget ) ; MipsTargetLowering :: getOpndList ( Ops , RegsToPass , IsPICCall , GlobalOrExternal , InternalLinkage , CLI , Callee , Chain ) ; } </s>

This function fills Ops , which is the list of operands that will later be used when a function call node is created .

Mips Mips Mips 0 Mips Mips Mips Mips Mips Mips Mips Mips::V0 Mips Mips MipsII::MO_GOT Mips::T9 Mips


<s> SDValue PIC16TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , DebugLoc dl , SelectionDAG & DAG ) const { unsigned NumRet = Outs . size ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function * F = MF . getFunction ( ) ; std :: string FuncName = F -> getName ( ) ; const char * tmpName = ESNames :: createESName ( PAN :: getFrameLabel ( FuncName ) ) ; SDValue ES = DAG . getTargetExternalSymbol ( tmpName , MVT :: i8 ) ; SDValue BS = DAG . getConstant ( 1 , MVT :: i8 ) ; SDValue RetVal ; for ( unsigned i = 0 ; i < NumRet ; ++ i ) { RetVal = OutVals [ i ] ; Chain = DAG . getNode ( PIC16ISD :: PIC16Store , dl , MVT :: Other , Chain , RetVal , ES , BS , DAG . getConstant ( i , MVT :: i8 ) ) ; } return DAG . getNode ( PIC16ISD :: RET , dl , MVT :: Other , Chain ) ; } </s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> unsigned PPCFastISel :: fastMaterializeAlloca ( const AllocaInst * AI ) { if ( ! FuncInfo . StaticAllocaMap . count ( AI ) ) return 0 ; MVT VT ; if ( ! isLoadTypeLegal ( AI -> getType ( ) , VT ) ) return 0 ; DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( AI ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { Register ResultReg = createResultReg ( & PPC :: G8RC_and_G8RC_NOX0RegClass ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( PPC :: ADDI8 ) , ResultReg ) . addFrameIndex ( SI -> second ) . addImm ( 0 ) ; return ResultReg ; } return 0 ; } </s>

Emit an alloca address in a register using target-specific logic .


<s> bool FISCAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNo ) ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , O ) ; case 'X' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << "0x" << StringRef ( utohexstr ( MO . getImm ( ) ) ) . lower ( ) ; return false ; case 'x' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << "0x" << StringRef ( utohexstr ( MO . getImm ( ) & 0xffff ) ) . lower ( ) ; return false ; case 'd' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) ; return false ; case 'm' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) - 1 ; return false ; case 'z' : { if ( MO . getType ( ) != MachineOperand :: MO_Immediate ) return true ; int64_t Val = MO . getImm ( ) ; if ( Val ) O << Val ; else O << "xzr" ; return false ; } } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> unsigned LanaiInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . getOpcode ( ) == Lanai :: SW_RI ) if ( MI . getOperand ( 0 ) . isFI ( ) && MI . getOperand ( 1 ) . isImm ( ) && MI . getOperand ( 1 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 0 ) . getIndex ( ) ; return MI . getOperand ( 2 ) . getReg ( ) ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


For most targets , an LLVM type must be broken down into multiple smaller types .


<s> unsigned MBlazeRegisterInfo :: getRARegister ( ) const { return MBlaze :: R15 ; } </s>

This method should return the register where the return address can be found .


<s> static int pa_reloc_rw_mask ( void ) { if ( flag_pic || ( TARGET_SOM && ! TARGET_HPUX_11 ) ) return 3 ; return TARGET_SOM ? 2 : 0 ; } </s>


<s> const MCSection * X86ELFMCAsmInfo :: getNonexecutableStackSection ( MCContext & Ctx ) const { return Ctx . getELFSection ( ".note.GNU-stack" , MCSectionELF :: SHT_PROGBITS , 0 , SectionKind :: getMetadata ( ) , false ) ; } </s>

Targets can implement this method to specify a section to switch to if the translation unit does n't have any trampolines that require an executable stack .


<s> int X86FrameLowering :: mergeSPUpdates ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , bool doMergeWithPrevious ) const { if ( ( doMergeWithPrevious && MBBI == MBB . begin ( ) ) || ( ! doMergeWithPrevious && MBBI == MBB . end ( ) ) ) return 0 ; MachineBasicBlock :: iterator PI = doMergeWithPrevious ? std :: prev ( MBBI ) : MBBI ; MachineBasicBlock :: iterator NI = doMergeWithPrevious ? nullptr : std :: next ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = 0 ; if ( ! doMergeWithPrevious && NI != MBB . end ( ) && NI -> getOpcode ( ) == TargetOpcode :: CFI_INSTRUCTION ) { return Offset ; } if ( ( Opc == X86 :: ADD64ri32 || Opc == X86 :: ADD64ri8 || Opc == X86 :: ADD32ri || Opc == X86 :: ADD32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { assert ( PI -> getOperand ( 1 ) . getReg ( ) == StackPtr ) ; Offset += PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == X86 :: LEA32r || Opc == X86 :: LEA64_32r ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr && PI -> getOperand ( 1 ) . getReg ( ) == StackPtr && PI -> getOperand ( 2 ) . getImm ( ) == 1 && PI -> getOperand ( 3 ) . getReg ( ) == X86 :: NoRegister && PI -> getOperand ( 5 ) . getReg ( ) == X86 :: NoRegister ) { Offset += PI -> getOperand ( 4 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == X86 :: SUB64ri32 || Opc == X86 :: SUB64ri8 || Opc == X86 :: SUB32ri || Opc == X86 :: SUB32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { assert ( PI -> getOperand ( 1 ) . getReg ( ) == StackPtr ) ; Offset -= PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } return Offset ; } </s>

Check the instruction before/after the passed instruction .


<s> static bool aarch64_legitimize_address_displacement ( rtx * disp , rtx * off , machine_mode mode ) { HOST_WIDE_INT offset = INTVAL ( * disp ) ; HOST_WIDE_INT base = offset & ~ ( GET_MODE_SIZE ( mode ) < 4 ? 0xfff : 0x3ffc ) ; if ( mode == TImode || mode == TFmode || ( offset & ( GET_MODE_SIZE ( mode ) - 1 ) ) != 0 ) base = ( offset + 0x100 ) & ~ 0x1ff ; * off = GEN_INT ( base ) ; * disp = GEN_INT ( offset - base ) ; return true ; } </s>

Split an out-of-range address displacement into a base and offset . Use 4KB range for 1- and 2-byte accesses and a 16KB range otherwise to increase opportunities for sharing the base address of different sizes . For unaligned accesses and TI/TF mode use the signed 9-bit range .


<s>
const
MCExpr
*
getExpr
(
)
const
{
assert
(
Kind
==
Expression
&&
"Invalid access!"
)
;
return
Expr
.
Val
;
}
</s>

Implementation of the SCEVPredicate interface .


"Can only insert epilog into returning blocks"


<s> tree function_resolver :: resolve ( ) { return shape -> resolve ( * this ) ; } </s>

If the call is erroneous , report an appropriate error and return error_mark_node . Otherwise , if the function is overloaded , return the decl of the non-overloaded function . Return NULL_TREE otherwise , indicating that the call should be processed in the normal way .


<s> static rtx nvptx_gen_wcast ( rtx reg , propagate_mask pm , unsigned rep , wcast_data_t * data ) { rtx res ; machine_mode mode = GET_MODE ( reg ) ; switch ( mode ) { case BImode : { rtx tmp = gen_reg_rtx ( SImode ) ; start_sequence ( ) ; if ( pm & PM_read ) emit_insn ( gen_sel_truesi ( tmp , reg , GEN_INT ( 1 ) , const0_rtx ) ) ; emit_insn ( nvptx_gen_wcast ( tmp , pm , rep , data ) ) ; if ( pm & PM_write ) emit_insn ( gen_rtx_SET ( reg , gen_rtx_NE ( BImode , tmp , const0_rtx ) ) ) ; res = get_insns ( ) ; end_sequence ( ) ; } break ; default : { rtx addr = data -> ptr ; if ( ! addr ) { unsigned align = GET_MODE_ALIGNMENT ( mode ) / BITS_PER_UNIT ; if ( align > worker_bcast_align ) worker_bcast_align = align ; data -> offset = ( data -> offset + align - 1 ) & ~ ( align - 1 ) ; addr = data -> base ; if ( data -> offset ) addr = gen_rtx_PLUS ( Pmode , addr , GEN_INT ( data -> offset ) ) ; } addr = gen_rtx_MEM ( mode , addr ) ; if ( pm == PM_read ) res = gen_rtx_SET ( addr , reg ) ; else if ( pm == PM_write ) res = gen_rtx_SET ( reg , addr ) ; else gcc_unreachable ( ) ; if ( data -> ptr ) { start_sequence ( ) ; emit_insn ( res ) ; emit_insn ( gen_adddi3 ( data -> ptr , data -> ptr , GEN_INT ( GET_MODE_SIZE ( GET_MODE ( reg ) ) ) ) ) ; res = get_insns ( ) ; end_sequence ( ) ; } else rep = 1 ; data -> offset += rep * GET_MODE_SIZE ( GET_MODE ( reg ) ) ; } break ; } return res ; } </s>

Generate instruction ( s ) to spill or fill register REG to/from the worker broadcast array . PM indicates what is to be done , REP how many loop iterations will be executed ( 0 for not a loop ) .


<s> static bool pdp11_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( regno <= PC_REGNUM ) return ( GET_MODE_BITSIZE ( mode ) <= 16 || ( GET_MODE_BITSIZE ( mode ) >= 32 && ! ( regno & 1 ) && ! FLOAT_MODE_P ( mode ) ) ) ; return FLOAT_MODE_P ( mode ) ; } </s>

Implement TARGET_HARD_REGNO_MODE_OK . On the pdp , the cpu registers can hold any mode other than float ( because otherwise we may end up being asked to move from CPU to FPU register , which is n't a valid operation on the PDP11 ) . For CPU registers , check alignment . FPU accepts SF and DF but actually holds a DF - simplifies life !


<s> bool VideoCore4PassConfig :: addInstSelector ( ) { addPass ( createVideoCore4ISelDag ( getVideoCore4TargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> unsigned PPCFrameLowering :: determineFrameLayout ( MachineFunction & MF , bool UpdateMF , bool UseEstimate ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = UseEstimate ? MFI . estimateStackSize ( MF ) : MFI . getStackSize ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned MaxAlign = MFI . getMaxAlignment ( ) ; unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - 1 ; const PPCRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; bool DisableRedZone = MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoRedZone ) ; bool CanUseRedZone = ! MFI . hasVarSizedObjects ( ) && ! MFI . adjustsStack ( ) && ! MustSaveLR ( MF , LR ) && ! RegInfo -> hasBasePointer ( MF ) ; bool FitsInRedZone = FrameSize <= Subtarget . getRedZoneSize ( ) ; if ( ! DisableRedZone && CanUseRedZone && FitsInRedZone ) { NumNoNeedForFrame ++ ; if ( UpdateMF ) MFI . setStackSize ( 0 ) ; return 0 ; } unsigned maxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI . hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI . setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI . setStackSize ( FrameSize ) ; return FrameSize ; } </s>

Determine the frame layout but do not update the machine function .


<s> static rtx frame_subreg_note ( rtx set , int offset ) { rtx src = simplify_gen_subreg ( SImode , SET_SRC ( set ) , DImode , offset ) ; rtx dst = simplify_gen_subreg ( SImode , SET_DEST ( set ) , DImode , offset ) ; set = gen_rtx_SET ( dst , src ) ; RTX_FRAME_RELATED_P ( set ) = 1 ; return set ; } </s>

For a DImode load / store SET , make a SImode set for a REG_FRAME_RELATED_EXPR note , using OFFSET to create a high or lowpart subreg .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
auto
PrintImmValue
=
[
&
]
(
const
MCExpr
*
Val
,
const
char
*
VName
)
{
if
(
Val
->
getKind
(
)
==
MCExpr
::
Constant
)
{
if
(
auto
Imm
=
cast
<
MCConstantExpr
>
(
Val
)
->
getValue
(
)
)
OS
<<
VName
<<
Imm
;
}
else
if
(
Val
->
getKind
(
)
==
MCExpr
::
SymbolRef
)
{
if
(
auto
*
SRE
=
dyn_cast
<
MCSymbolRefExpr
>
(
Val
)
)
{
const
MCSymbol
&
Sym
=
SRE
->
getSymbol
(
)
;
if
(
auto
SymName
=
Sym
.
getName
(
)
.
data
(
)
)
OS
<<
VName
<<
SymName
;
}
}
}
;
switch
(
Kind
)
{
case
Token
:
OS
<<
Tok
.
Data
;
break
;
case
Register
:
OS
<<
"Reg:"
<<
X86IntelInstPrinter
::
getRegisterName
(
Reg
.
RegNo
)
;
break
;
case
DXRegister
:
OS
<<
"DXReg"
;
break
;
case
Immediate
:
PrintImmValue
(
Imm
.
Val
,
"Imm:"
)
;
break
;
case
Prefix
:
OS
<<
"Prefix:"
<<
Pref
.
Prefixes
;
break
;
case
Memory
:
OS
<<
"Memory: ModeSize="
<<
Mem
.
ModeSize
;
if
(
Mem
.
Size
)
OS
<<
",Size="
<<
Mem
.
Size
;
if
(
Mem
.
BaseReg
)
OS
<<
",BaseReg="
<<
X86IntelInstPrinter
::
getRegisterName
(
Mem
.
BaseReg
)
;
if
(
Mem
.
IndexReg
)
OS
<<
",IndexReg="
<<
X86IntelInstPrinter
::
getRegisterName
(
Mem
.
IndexReg
)
;
if
(
Mem
.
Scale
)
OS
<<
",Scale="
<<
Mem
.
Scale
;
if
(
Mem
.
Disp
)
PrintImmValue
(
Mem
.
Disp
,
",Disp="
)
;
if
(
Mem
.
SegReg
)
OS
<<
",SegReg="
<<
X86IntelInstPrinter
::
getRegisterName
(
Mem
.
SegReg
)
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

X86
"Reg:"
X86
"DXReg"
"Imm:"
"Prefix:"
"Memory: ModeSize="
",Size="
",BaseReg="
X86
",IndexReg="
X86
",Scale="
",Disp="
",SegReg="
X86


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> unsigned AArch64AsmParser :: validateTargetOperandClass ( MCParsedAsmOperand * AsmOp , unsigned Kind ) { AArch64Operand * Op = static_cast < AArch64Operand * > ( AsmOp ) ; int64_t ExpectedVal ; switch ( Kind ) { default : return Match_InvalidOperand ; case MCK__35_0 : ExpectedVal = 0 ; break ; case MCK__35_1 : ExpectedVal = 1 ; break ; case MCK__35_12 : ExpectedVal = 12 ; break ; case MCK__35_16 : ExpectedVal = 16 ; break ; case MCK__35_2 : ExpectedVal = 2 ; break ; case MCK__35_24 : ExpectedVal = 24 ; break ; case MCK__35_3 : ExpectedVal = 3 ; break ; case MCK__35_32 : ExpectedVal = 32 ; break ; case MCK__35_4 : ExpectedVal = 4 ; break ; case MCK__35_48 : ExpectedVal = 48 ; break ; case MCK__35_6 : ExpectedVal = 6 ; break ; case MCK__35_64 : ExpectedVal = 64 ; break ; case MCK__35_8 : ExpectedVal = 8 ; break ; } if ( ! Op -> isImm ( ) ) return Match_InvalidOperand ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op -> getImm ( ) ) ; if ( ! CE ) return Match_InvalidOperand ; if ( CE -> getValue ( ) == ExpectedVal ) return Match_Success ; return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> static tree rs6000_builtin_vectorized_libmass ( combined_fn fn , tree type_out , tree type_in ) { char name [ 32 ] ; const char * suffix = NULL ; tree fntype , new_fndecl , bdecl = NULL_TREE ; int n_args = 1 ; const char * bname ; machine_mode el_mode , in_mode ; int n , in_n ; if ( ! flag_unsafe_math_optimizations || ! TARGET_VSX ) return NULL_TREE ; el_mode = TYPE_MODE ( TREE_TYPE ( type_out ) ) ; n = TYPE_VECTOR_SUBPARTS ( type_out ) ; in_mode = TYPE_MODE ( TREE_TYPE ( type_in ) ) ; in_n = TYPE_VECTOR_SUBPARTS ( type_in ) ; if ( el_mode != in_mode || n != in_n ) return NULL_TREE ; switch ( fn ) { CASE_CFN_ATAN2 : CASE_CFN_HYPOT : CASE_CFN_POW : n_args = 2 ; CASE_CFN_ACOS : CASE_CFN_ACOSH : CASE_CFN_ASIN : CASE_CFN_ASINH : CASE_CFN_ATAN : CASE_CFN_ATANH : CASE_CFN_CBRT : CASE_CFN_COS : CASE_CFN_COSH : CASE_CFN_ERF : CASE_CFN_ERFC : CASE_CFN_EXP2 : CASE_CFN_EXP : CASE_CFN_EXPM1 : CASE_CFN_LGAMMA : CASE_CFN_LOG10 : CASE_CFN_LOG1P : CASE_CFN_LOG2 : CASE_CFN_LOG : CASE_CFN_SIN : CASE_CFN_SINH : CASE_CFN_SQRT : CASE_CFN_TAN : CASE_CFN_TANH : if ( el_mode == DFmode && n == 2 ) { bdecl = mathfn_built_in ( double_type_node , fn ) ; suffix = "d2" ; } else if ( el_mode == SFmode && n == 4 ) { bdecl = mathfn_built_in ( float_type_node , fn ) ; suffix = "4" ; } else return NULL_TREE ; if ( ! bdecl ) return NULL_TREE ; break ; default : return NULL_TREE ; } gcc_assert ( suffix != NULL ) ; bname = IDENTIFIER_POINTER ( DECL_NAME ( bdecl ) ) ; if ( ! bname ) return NULL_TREE ; strcpy ( name , bname + sizeof ( "__builtin_" ) - 1 ) ; strcat ( name , suffix ) ; if ( n_args == 1 ) fntype = build_function_type_list ( type_out , type_in , NULL ) ; else if ( n_args == 2 ) fntype = build_function_type_list ( type_out , type_in , type_in , NULL ) ; else gcc_unreachable ( ) ; new_fndecl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , fntype ) ; TREE_PUBLIC ( new_fndecl ) = 1 ; DECL_EXTERNAL ( new_fndecl ) = 1 ; DECL_IS_NOVOPS ( new_fndecl ) = 1 ; TREE_READONLY ( new_fndecl ) = 1 ; return new_fndecl ; } </s>

Handler for the Mathematical Acceleration Subsystem ( mass ) interface to a library with vectorized intrinsics .


<s> void arc_cpu_cpp_builtins ( cpp_reader * pfile ) { builtin_assert ( "cpu=arc" ) ; builtin_assert ( "machine=arc" ) ; builtin_define ( "__arc__" ) ; def_or_undef_macro ( pfile , NAME , CONDITION ) ; builtin_define_with_int_value ( "__ARC_TLS_REGNO__" , arc_tp_regno ) ; builtin_define_with_int_value ( "__ARC_LPC_WIDTH__" , arc_lpcwidth ) ; builtin_define ( TARGET_BIG_ENDIAN ? "__BIG_ENDIAN__" : "__LITTLE_ENDIAN__" ) ; if ( TARGET_BIG_ENDIAN ) builtin_define ( "__big_endian__" ) ; } </s>

Helper for TARGET_CPU_CPP_BUILTINS hook .


<s> FastISel * Mips :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) { return new MipsFastISel ( funcInfo , libInfo ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> bool enablePostRAScheduler ( ) const override { return usePostRAScheduler ( ) ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s> void PPCAsmPrinter :: PrintSymbolOperand ( const MachineOperand & MO , raw_ostream & O ) { const GlobalValue * GV = MO . getGlobal ( ) ; getSymbol ( GV ) -> print ( O , MAI ) ; printOffset ( MO . getOffset ( ) , O ) ; } </s>


<s> bool isMem ( ) const { return false ; } </s>


<s> bool xxspltib_constant_p ( rtx op , machine_mode mode , int * num_insns_ptr , int * constant_ptr ) { size_t nunits = GET_MODE_NUNITS ( mode ) ; size_t i ; HOST_WIDE_INT value ; rtx element ; * num_insns_ptr = - 1 ; * constant_ptr = 256 ; if ( ! TARGET_P9_VECTOR ) return false ; if ( mode == VOIDmode ) mode = GET_MODE ( op ) ; else if ( mode != GET_MODE ( op ) && GET_MODE ( op ) != VOIDmode ) return false ; if ( GET_CODE ( op ) == VEC_DUPLICATE ) { if ( mode != V16QImode && mode != V8HImode && mode != V4SImode && mode != V2DImode ) return false ; element = XEXP ( op , 0 ) ; if ( ! CONST_INT_P ( element ) ) return false ; value = INTVAL ( element ) ; if ( ! IN_RANGE ( value , - 128 , 127 ) ) return false ; } else if ( GET_CODE ( op ) == CONST_VECTOR ) { if ( mode != V16QImode && mode != V8HImode && mode != V4SImode && mode != V2DImode ) return false ; element = CONST_VECTOR_ELT ( op , 0 ) ; if ( ! CONST_INT_P ( element ) ) return false ; value = INTVAL ( element ) ; if ( ! IN_RANGE ( value , - 128 , 127 ) ) return false ; for ( i = 1 ; i < nunits ; i ++ ) { element = CONST_VECTOR_ELT ( op , i ) ; if ( ! CONST_INT_P ( element ) ) return false ; if ( value != INTVAL ( element ) ) return false ; } } else if ( CONST_INT_P ( op ) ) { if ( ! SCALAR_INT_MODE_P ( mode ) ) return false ; value = INTVAL ( op ) ; if ( ! IN_RANGE ( value , - 128 , 127 ) ) return false ; if ( ! IN_RANGE ( value , - 1 , 0 ) ) { if ( ! ( reg_addr [ mode ] . addr_mask [ RELOAD_REG_VMX ] & RELOAD_REG_VALID ) ) return false ; if ( EASY_VECTOR_15 ( value ) ) return false ; } } else return false ; if ( ( mode == V4SImode || mode == V8HImode ) && ! IN_RANGE ( value , - 1 , 0 ) && EASY_VECTOR_15 ( value ) ) return false ; if ( mode == V16QImode ) * num_insns_ptr = 1 ; else if ( IN_RANGE ( value , - 1 , 0 ) ) * num_insns_ptr = 1 ; else if ( vsx_prefixed_constant ( op , mode ) ) return false ; else * num_insns_ptr = 2 ; * constant_ptr = ( int ) value ; return true ; } </s>

Return true if OP is of the given MODE and can be synthesized with ISA 3.0 instructions ( xxspltib , vupkhsb/vextsb2w/vextb2d ) . Return the number of instructions needed ( 1 or 2 ) into the address pointed via NUM_INSNS_PTR . Return the constant that is being split via CONSTANT_PTR .


<s> static bool chain_contains_only_swaps ( swap_web_entry * insn_entry , struct df_link * link , enum chain_purpose purpose ) { if ( ! link ) return false ; for ( ; link ; link = link -> next ) { if ( ! ALTIVEC_OR_VSX_VECTOR_MODE ( GET_MODE ( DF_REF_REG ( link -> ref ) ) ) ) continue ; if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) return false ; rtx reached_insn = DF_REF_INSN ( link -> ref ) ; unsigned uid = INSN_UID ( reached_insn ) ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( reached_insn ) ; if ( ! insn_entry [ uid ] . is_swap || insn_entry [ uid ] . is_load || insn_entry [ uid ] . is_store ) return false ; if ( purpose == FOR_LOADS ) { df_ref use ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { struct df_link * swap_link = DF_REF_CHAIN ( use ) ; while ( swap_link ) { if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) return false ; rtx swap_def_insn = DF_REF_INSN ( swap_link -> ref ) ; unsigned uid2 = INSN_UID ( swap_def_insn ) ; if ( ! insn_entry [ uid2 ] . is_swap || ! insn_entry [ uid2 ] . is_load ) return false ; swap_link = swap_link -> next ; } } } else if ( purpose == FOR_STORES ) { df_ref def ; FOR_EACH_INSN_INFO_DEF ( def , insn_info ) { struct df_link * swap_link = DF_REF_CHAIN ( def ) ; while ( swap_link ) { if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) return false ; rtx swap_use_insn = DF_REF_INSN ( swap_link -> ref ) ; unsigned uid2 = INSN_UID ( swap_use_insn ) ; if ( ! insn_entry [ uid2 ] . is_swap || insn_entry [ uid2 ] . is_load ) return false ; swap_link = swap_link -> next ; } } } } return true ; } </s>

Return true if the UD or DU chain headed by LINK is non-empty , and every entry on the chain references an insn that is a register swap . Furthermore , if PURPOSE is FOR_LOADS , each such register swap must have only permuting loads as reaching defs . If PURPOSE is FOR_STORES , each such register swap must have only register swaps or permuting stores as reached uses .


<s> unsigned AVRInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : { const MCInstrDesc & Desc = get ( Opcode ) ; return Desc . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return 0 ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const AVRTargetMachine & TM = static_cast < const AVRTargetMachine & > ( MF . getTarget ( ) ) ; const AVRSubtarget & STI = MF . getSubtarget < AVRSubtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; return TII . getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> void Z80FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MI = MBB . begin ( ) ; DebugLoc DL ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; int StackSize = - int ( MFI . getStackSize ( ) ) ; unsigned ScratchReg = Is24Bit ? Z80 :: UHL : Z80 :: HL ; while ( MI != MBB . end ( ) && MI -> getFlag ( MachineInstr :: FrameSetup ) ) ++ MI ; int FPOffset = - 1 ; if ( hasFP ( MF ) ) { if ( MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeList :: FunctionIndex , Attribute :: OptimizeForSize ) ) { if ( StackSize ) { BuildMI ( MBB , MI , DL , TII . get ( Is24Bit ? Z80 :: LD24ri : Z80 :: LD16ri ) , ScratchReg ) . addImm ( StackSize ) ; BuildMI ( MBB , MI , DL , TII . get ( Is24Bit ? Z80 :: CALL24i : Z80 :: CALL16i ) ) . addExternalSymbol ( "_frameset" ) . addReg ( ScratchReg , RegState :: ImplicitKill ) ; return ; } BuildMI ( MBB , MI , DL , TII . get ( Is24Bit ? Z80 :: CALL24i : Z80 :: CALL16i ) ) . addExternalSymbol ( "_frameset0" ) ; return ; } unsigned FrameReg = TRI -> getFrameRegister ( MF ) ; BuildMI ( MBB , MI , DL , TII . get ( Is24Bit ? Z80 :: PUSH24r : Z80 :: PUSH16r ) ) . addReg ( FrameReg ) ; BuildMI ( MBB , MI , DL , TII . get ( Is24Bit ? Z80 :: LD24ri : Z80 :: LD16ri ) , FrameReg ) . addImm ( 0 ) ; BuildMI ( MBB , MI , DL , TII . get ( Is24Bit ? Z80 :: ADD24SP : Z80 :: ADD16SP ) , FrameReg ) . addReg ( FrameReg ) ; FPOffset = 0 ; } BuildStackAdjustment ( MF , MBB , MI , DL , ScratchReg , StackSize , FPOffset ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> TargetLoweringBase :: LegalizeTypeAction NVPTXTargetLowering :: getPreferredVectorAction ( EVT VT ) const { if ( VT . getVectorNumElements ( ) != 1 && VT . getScalarType ( ) == MVT :: i1 ) return TypeSplitVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s> static bool mcore_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { const HOST_WIDE_INT size = int_size_in_bytes ( type ) ; return ( size == - 1 || size > 2 * UNITS_PER_WORD ) ; } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


"value of %<-mfixed-range%> must have form REG1-REG2"

Parse the -mfixed-range= option string .


<s> static void ix86_test_loading_unspec ( ) { rtl_dump_test t ( SELFTEST_LOCATION , locate_file ( "x86_64/unspec.rtl" ) ) ; ASSERT_STREQ ( "test_unspec" , IDENTIFIER_POINTER ( DECL_NAME ( cfun -> decl ) ) ) ; ASSERT_TRUE ( cfun ) ; rtx_insn * insn = get_insns ( ) ; ASSERT_EQ ( INSN , GET_CODE ( insn ) ) ; rtx set = single_set ( insn ) ; ASSERT_NE ( NULL , set ) ; rtx dst = SET_DEST ( set ) ; ASSERT_EQ ( MEM , GET_CODE ( dst ) ) ; rtx src = SET_SRC ( set ) ; ASSERT_EQ ( UNSPEC , GET_CODE ( src ) ) ; ASSERT_EQ ( BLKmode , GET_MODE ( src ) ) ; ASSERT_EQ ( UNSPEC_MEMORY_BLOCKAGE , XINT ( src , 1 ) ) ; rtx v0 = XVECEXP ( src , 0 , 0 ) ; rtx scratch_a = XEXP ( dst , 0 ) ; ASSERT_EQ ( SCRATCH , GET_CODE ( scratch_a ) ) ; rtx scratch_b = XEXP ( v0 , 0 ) ; ASSERT_EQ ( SCRATCH , GET_CODE ( scratch_b ) ) ; ASSERT_EQ ( scratch_a , scratch_b ) ; ASSERT_TRUE ( rtx_equal_p ( dst , v0 ) ) ; ASSERT_NE ( - 1 , recog_memoized ( insn ) ) ; insn = NEXT_INSN ( insn ) ; ASSERT_EQ ( INSN , GET_CODE ( insn ) ) ; set = single_set ( insn ) ; ASSERT_NE ( NULL , set ) ; src = SET_SRC ( set ) ; ASSERT_EQ ( UNSPEC_VOLATILE , GET_CODE ( src ) ) ; ASSERT_EQ ( UNSPECV_RDTSCP , XINT ( src , 1 ) ) ; } </s>

Verify that the RTL loader copes with UNSPEC and UNSPEC_VOLATILE insns . In particular , verify that it correctly loads the 2nd operand . This test is target-specific since these are machine-specific operands ( and enums ) .


"Instr doesn't have FrameIndex operand!"

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s> void ix86_expand_fp_absneg_operator ( enum rtx_code code , machine_mode mode , rtx operands [ ] ) { rtx set , dst , src ; bool use_sse = false ; bool vector_mode = VECTOR_MODE_P ( mode ) ; machine_mode vmode = mode ; rtvec par ; if ( vector_mode || mode == TFmode ) use_sse = true ; else if ( TARGET_SSE_MATH ) { use_sse = SSE_FLOAT_MODE_P ( mode ) ; if ( mode == SFmode ) vmode = V4SFmode ; else if ( mode == DFmode ) vmode = V2DFmode ; } dst = operands [ 0 ] ; src = operands [ 1 ] ; set = gen_rtx_fmt_e ( code , mode , src ) ; set = gen_rtx_SET ( dst , set ) ; if ( use_sse ) { rtx mask , use , clob ; mask = ix86_build_signbit_mask ( vmode , vector_mode , code == ABS ) ; use = gen_rtx_USE ( VOIDmode , mask ) ; if ( vector_mode || mode == TFmode ) par = gen_rtvec ( 2 , set , use ) ; else { clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; par = gen_rtvec ( 3 , set , use , clob ) ; } } else { rtx clob ; clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; par = gen_rtvec ( 2 , set , clob ) ; } emit_insn ( gen_rtx_PARALLEL ( VOIDmode , par ) ) ; } </s>

Generate code for floating point ABS or NEG .


"=== RegBanks reassign analysis on function "

"RegBank reassign stall cycles verification failed."

runOnMachineFunction - Emit the function body .


<s> rtx ix86_gen_scratch_sse_rtx ( machine_mode mode ) { return gen_reg_rtx ( mode ) ; } </s>

Implement the TARGET_GEN_MEMSET_SCRATCH_RTX hook . Return a scratch register in MODE for vector load and store .


<s>
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
WebAssemblyTargetLowering
::
getRegForInlineAsmConstraint
(
const
TargetRegisterInfo
*
TRI
,
StringRef
Constraint
,
MVT
VT
)
const
{
if
(
Constraint
.
size
(
)
==
1
)
{
switch
(
Constraint
[
0
]
)
{
case
'r'
:
assert
(
VT
!=
MVT
::
iPTR
&&
"Pointer MVT not expected here"
)
;
if
(
VT
.
isInteger
(
)
&&
!
VT
.
isVector
(
)
)
{
if
(
VT
.
getSizeInBits
(
)
<=
32
)
return
std
::
make_pair
(
0U
,
&
WebAssembly
::
I32RegClass
)
;
if
(
VT
.
getSizeInBits
(
)
<=
64
)
return
std
::
make_pair
(
0U
,
&
WebAssembly
::
I64RegClass
)
;
}
break
;
default
:
break
;
}
}
return
TargetLowering
::
getRegForInlineAsmConstraint
(
TRI
,
Constraint
,
VT
)
;
}
</s>

Given a physical register constraint ( e.g .


<s> HOST_WIDE_INT s390_initial_elimination_offset ( int from , int to ) { HOST_WIDE_INT offset ; if ( ! s390_can_eliminate ( from , to ) ) return 0 ; switch ( from ) { case FRAME_POINTER_REGNUM : offset = ( get_frame_size ( ) + STACK_POINTER_OFFSET + crtl -> outgoing_args_size ) ; break ; case ARG_POINTER_REGNUM : s390_init_frame_layout ( ) ; offset = cfun_frame_layout . frame_size + STACK_POINTER_OFFSET ; break ; case RETURN_ADDRESS_POINTER_REGNUM : s390_init_frame_layout ( ) ; if ( cfun_frame_layout . first_save_gpr_slot == - 1 ) { if ( cfun -> stdarg && ! cfun_save_arg_fprs_p ) return 0 ; gcc_unreachable ( ) ; } offset = ( cfun_frame_layout . frame_size + cfun_frame_layout . gprs_offset + ( RETURN_REGNUM - cfun_frame_layout . first_save_gpr_slot ) * UNITS_PER_LONG ) ; break ; case BASE_REGNUM : offset = 0 ; break ; default : gcc_unreachable ( ) ; } return offset ; } </s>

Return offset between register FROM and TO initially after prolog .


<s> const_iterator begin ( ) const { return m_SectToExData . begin ( ) ; } </s>


Create constant where bits outside of lowest bit set to highest bit set are set to 1 .


<s> inline hashval_t libcall_hasher :: hash ( const value_type * p1 ) { return hash_rtx ( p1 , VOIDmode , NULL , NULL , FALSE ) ; } </s>

Hash function for builtin functions with up to 3 arguments and a return type .


"Caller should have handled 0-size case"

Emit target-specific code that performs a memcmp/bcmp , in cases where that is faster than a libcall .


<s> bool SystemZXPLINKFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MutableArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; SystemZMachineFunctionInfo * ZFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; const SystemZSubtarget & Subtarget = MF . getSubtarget < SystemZSubtarget > ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; auto & Regs = Subtarget . getSpecialRegisters < SystemZXPLINK64Registers > ( ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; for ( unsigned I = 0 , E = CSI . size ( ) ; I != E ; ++ I ) { Register Reg = CSI [ I ] . getReg ( ) ; if ( SystemZ :: FP64BitRegClass . contains ( Reg ) ) TII -> loadRegFromStackSlot ( MBB , MBBI , Reg , CSI [ I ] . getFrameIdx ( ) , & SystemZ :: FP64BitRegClass , TRI ) ; if ( SystemZ :: VR128BitRegClass . contains ( Reg ) ) TII -> loadRegFromStackSlot ( MBB , MBBI , Reg , CSI [ I ] . getFrameIdx ( ) , & SystemZ :: VR128BitRegClass , TRI ) ; } SystemZ :: GPRRegs RestoreGPRs = ZFI -> getRestoreGPRRegs ( ) ; if ( RestoreGPRs . LowGPR ) { assert ( isInt < 20 > ( Regs . getStackPointerBias ( ) + RestoreGPRs . GPROffset ) ) ; if ( RestoreGPRs . LowGPR == RestoreGPRs . HighGPR ) BuildMI ( MBB , MBBI , DL , TII -> get ( SystemZ :: LG ) , RestoreGPRs . LowGPR ) . addReg ( Regs . getStackPointerRegister ( ) ) . addImm ( Regs . getStackPointerBias ( ) + RestoreGPRs . GPROffset ) . addReg ( 0 ) ; else { MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( SystemZ :: LMG ) ) ; MIB . addReg ( RestoreGPRs . LowGPR , RegState :: Define ) ; MIB . addReg ( RestoreGPRs . HighGPR , RegState :: Define ) ; MIB . addReg ( Regs . getStackPointerRegister ( ) ) ; MIB . addImm ( Regs . getStackPointerBias ( ) + RestoreGPRs . GPROffset ) ; for ( unsigned I = 0 , E = CSI . size ( ) ; I != E ; ++ I ) { Register Reg = CSI [ I ] . getReg ( ) ; if ( Reg > RestoreGPRs . LowGPR && Reg < RestoreGPRs . HighGPR ) MIB . addReg ( Reg , RegState :: ImplicitDefine ) ; } } } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


"Z80 DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> void setupMF ( MachineFunction & MF , GISelKnownBits & KB , CodeGenCoverage & CoverageInfo ) override { InstructionSelector :: setupMF ( MF , KB , CoverageInfo ) ; ProduceNonFlagSettingCondBr = ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: SpeculativeLoadHardening ) ; MFReturnAddr = Register ( ) ; } </s>


<s>
bool
PPCInstrInfo
::
isReallyTriviallyReMaterializable
(
const
MachineInstr
&
MI
,
AliasAnalysis
*
AA
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown rematerializable operation!"
)
;
break
;
case
PPC
::
LI
:
case
PPC
::
LI8
:
case
PPC
::
LIS
:
case
PPC
::
LIS8
:
case
PPC
::
QVGPCI
:
case
PPC
::
ADDIStocHA
:
case
PPC
::
ADDItocL
:
case
PPC
::
LOAD_STACK_GUARD
:
case
PPC
::
XXLXORz
:
case
PPC
::
XXLXORspz
:
case
PPC
::
XXLXORdpz
:
case
PPC
::
V_SET0B
:
case
PPC
::
V_SET0H
:
case
PPC
::
V_SET0
:
case
PPC
::
V_SETALLONESB
:
case
PPC
::
V_SETALLONESH
:
case
PPC
::
V_SETALLONES
:
case
PPC
::
CRSET
:
case
PPC
::
CRUNSET
:
return
true
;
}
return
false
;
}
</s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> const DataLayout * getDataLayout ( ) const override { return getSubtargetImpl ( ) -> getDataLayout ( ) ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s>
bool
VEAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
applyMnemonicAliases
(
Name
,
getAvailableFeatures
(
)
,
0
)
;
StringRef
Mnemonic
=
splitMnemonic
(
Name
,
NameLoc
,
&
Operands
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
parseOperand
(
Operands
,
Mnemonic
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Mnemonic
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

VE
VE
0
"unexpected token"
"unexpected token"
"unexpected token"


<s> const char * msp430_mcu_name ( void ) { if ( target_mcu ) { unsigned int i ; static char mcu_name [ 64 ] ; snprintf ( mcu_name , sizeof ( mcu_name ) - 1 , "__%s__" , target_mcu ) ; for ( i = strlen ( mcu_name ) ; i -- ; ) mcu_name [ i ] = TOUPPER ( mcu_name [ i ] ) ; return mcu_name ; } return msp430x ? "__MSP430XGENERIC__" : "__MSP430GENERIC__" ; } </s>

Generate a C preprocessor symbol based upon the MCU selected by the user . If a specific MCU has not been selected then return a generic symbol instead .


<s> static void register_svpattern ( ) { auto_vec < string_int_pair , 32 > values ; values . quick_push ( string_int_pair ( "SV_" # UPPER , VALUE ) ) ; AARCH64_FOR_SVPATTERN ( PUSH ) acle_svpattern = lang_hooks . types . simulate_enum_decl ( input_location , "svpattern" , values ) ; } </s>


<s> RegisterAggr & RegisterAggr :: intersect ( const RegisterAggr & RG ) { Units &= RG . Units ; return * this ; } </s>

Intersect this set with a temporary other set in place .


Function to tell the preprocessor about the defines for the current target .


"JIT does not support pseudo instruction GETPCX yet!"

Targets should implement this to emit instructions .


<s>
rtx
legitimize_address
(
rtx
x
,
rtx
oldx
,
enum
machine_mode
mode
)
{
x
=
oldx
;
if
(
TARGET_ALL_DEBUG
)
{
fprintf
(
stderr
,
"legitimize_address mode: %s"
,
GET_MODE_NAME
(
mode
)
)
;
debug_rtx
(
oldx
)
;
}
if
(
GET_CODE
(
oldx
)
==
PLUS
&&
REG_P
(
XEXP
(
oldx
,
0
)
)
)
{
if
(
REG_P
(
XEXP
(
oldx
,
1
)
)
)
x
=
force_reg
(
GET_MODE
(
oldx
)
,
oldx
)
;
else
if
(
GET_CODE
(
XEXP
(
oldx
,
1
)
)
==
CONST_INT
)
{
int
offs
=
INTVAL
(
XEXP
(
oldx
,
1
)
)
;
if
(
frame_pointer_rtx
!=
XEXP
(
oldx
,
0
)
)
if
(
offs
>
MAX_LD_OFFSET
(
mode
)
)
{
if
(
TARGET_ALL_DEBUG
)
fprintf
(
stderr
,
"force_reg (big offset)\n"
)
;
x
=
force_reg
(
GET_MODE
(
oldx
)
,
oldx
)
;
}
}
}
return
x
;
}
</s>

Try machine-dependent ways of modifying an illegitimate address X to be legitimate . If we find one , return the new , valid address . OLDX is the address as it was before break_out_memory_refs was called . In some cases it is useful to look at this to decide what needs to be done . MODE is the mode of the operand pointed to by X .


<s> const Thumb2RegisterInfo & getRegisterInfo ( ) const override { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void PPCFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const PPCRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; PPCFunctionInfo * FI = MF . getInfo < PPCFunctionInfo > ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; SavedRegs . reset ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; const bool isPPC64 = Subtarget . isPPC64 ( ) ; const bool IsDarwinABI = Subtarget . isDarwinABI ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( ) ; FPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int BPSI = FI -> getBasePointerSaveIndex ( ) ; if ( ! BPSI && RegInfo -> hasBasePointer ( MF ) ) { int BPOffset = getBasePointerSaveOffset ( ) ; BPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , BPOffset , true ) ; FI -> setBasePointerSaveIndex ( BPSI ) ; } if ( FI -> usesPICBase ( ) ) { int PBPSI = MFI . CreateFixedObject ( 4 , - 8 , true ) ; FI -> setPICBasePointerSaveIndex ( PBPSI ) ; } if ( needsFP ( MF ) ) SavedRegs . reset ( isPPC64 ? PPC :: X31 : PPC :: R31 ) ; if ( RegInfo -> hasBasePointer ( MF ) ) SavedRegs . reset ( RegInfo -> getBaseRegister ( MF ) ) ; if ( FI -> usesPICBase ( ) ) SavedRegs . reset ( PPC :: R30 ) ; int TCSPDelta = 0 ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < 0 ) { MFI . CreateFixedObject ( - 1 * TCSPDelta , TCSPDelta , true ) ; } if ( ! isPPC64 && ! IsDarwinABI && ( SavedRegs . test ( PPC :: CR2 ) || SavedRegs . test ( PPC :: CR3 ) || SavedRegs . test ( PPC :: CR4 ) ) ) { int FrameIdx = MFI . CreateFixedObject ( ( uint64_t ) 4 , ( int64_t ) - 4 , true ) ; FI -> setCRSpillFrameIndex ( FrameIdx ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> static void h8300_conditional_register_usage ( void ) { if ( ! TARGET_MAC ) fixed_regs [ MAC_REG ] = call_used_regs [ MAC_REG ] = 1 ; } </s>

Conditionally modify register usage based on target flags .


<s> MachineInstr * SIInstrInfo :: commuteInstruction ( MachineInstr * MI , bool NewMI ) const { MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; if ( MI -> getNumOperands ( ) < 3 || ! MI -> getOperand ( 1 ) . isReg ( ) ) return 0 ; if ( isVOP2 ( MI -> getOpcode ( ) ) && MI -> getOperand ( 1 ) . isReg ( ) && RI . isSGPRClass ( MRI . getRegClass ( MI -> getOperand ( 1 ) . getReg ( ) ) ) ) return 0 ; if ( ! MI -> getOperand ( 2 ) . isReg ( ) ) { if ( NewMI || MI -> getOperand ( 2 ) . isFPImm ( ) || ( ! isVOP2 ( MI -> getOpcode ( ) ) && ! isVOP3 ( MI -> getOpcode ( ) ) ) ) { return 0 ; } if ( isVOP3 ( MI -> getOpcode ( ) ) && ( MI -> getOperand ( AMDGPU :: getNamedOperandIdx ( MI -> getOpcode ( ) , AMDGPU :: OpName :: abs ) ) . getImm ( ) || MI -> getOperand ( AMDGPU :: getNamedOperandIdx ( MI -> getOpcode ( ) , AMDGPU :: OpName :: neg ) ) . getImm ( ) ) ) return 0 ; unsigned Reg = MI -> getOperand ( 1 ) . getReg ( ) ; unsigned SubReg = MI -> getOperand ( 1 ) . getSubReg ( ) ; MI -> getOperand ( 1 ) . ChangeToImmediate ( MI -> getOperand ( 2 ) . getImm ( ) ) ; MI -> getOperand ( 2 ) . ChangeToRegister ( Reg , false ) ; MI -> getOperand ( 2 ) . setSubReg ( SubReg ) ; } else { MI = TargetInstrInfo :: commuteInstruction ( MI , NewMI ) ; } if ( MI ) MI -> setDesc ( get ( commuteOpcode ( MI -> getOpcode ( ) ) ) ) ; return MI ; } </s>

This method commutes the operands of the given machine instruction MI .


<s> X86Subtarget & X86Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { initSubtargetFeatures ( CPU , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s>
void
WebAssemblyAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
DEBUG
(
dbgs
(
)
<<
"EmitInstruction: "
<<
*
MI
<<
'\n'
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
WebAssembly
::
ARGUMENT_I32
:
case
WebAssembly
::
ARGUMENT_I64
:
case
WebAssembly
::
ARGUMENT_F32
:
case
WebAssembly
::
ARGUMENT_F64
:
case
WebAssembly
::
ARGUMENT_v16i8
:
case
WebAssembly
::
ARGUMENT_v8i16
:
case
WebAssembly
::
ARGUMENT_v4i32
:
case
WebAssembly
::
ARGUMENT_v4f32
:
break
;
case
WebAssembly
::
FALLTHROUGH_RETURN_I32
:
case
WebAssembly
::
FALLTHROUGH_RETURN_I64
:
case
WebAssembly
::
FALLTHROUGH_RETURN_F32
:
case
WebAssembly
::
FALLTHROUGH_RETURN_F64
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v16i8
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v8i16
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v4i32
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v4f32
:
{
assert
(
MFI
->
isVRegStackified
(
MI
->
getOperand
(
0
)
.
getReg
(
)
)
)
;
if
(
isVerbose
(
)
)
{
OutStreamer
->
AddComment
(
"fallthrough-return: $pop"
+
Twine
(
MFI
->
getWARegStackId
(
MFI
->
getWAReg
(
MI
->
getOperand
(
0
)
.
getReg
(
)
)
)
)
)
;
OutStreamer
->
AddBlankLine
(
)
;
}
break
;
}
case
WebAssembly
::
FALLTHROUGH_RETURN_VOID
:
if
(
isVerbose
(
)
)
{
OutStreamer
->
AddComment
(
"fallthrough-return"
)
;
OutStreamer
->
AddBlankLine
(
)
;
}
break
;
default
:
{
WebAssemblyMCInstLower
MCInstLowering
(
OutContext
,
*
this
)
;
MCInst
TmpInst
;
MCInstLowering
.
Lower
(
MI
,
TmpInst
)
;
EmitToStreamer
(
*
OutStreamer
,
TmpInst
)
;
break
;
}
}
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createELFObjectWriter ( OS , false , OSType , ELF :: EM_MBLAZE , false , true ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


"instructions, but the target does not support ARM mode execution."

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
const
MCFixupKindInfo
&
DLXAsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
static
const
MCFixupKindInfo
Infos
[
DLX
::
NumTargetFixupKinds
]
=
{
{
"FIXUP_DLX_NONE"
,
0
,
32
,
0
}
,
{
"FIXUP_DLX_21"
,
16
,
16
,
0
}
,
{
"FIXUP_DLX_21_F"
,
16
,
16
,
0
}
,
{
"FIXUP_DLX_25"
,
7
,
25
,
0
}
,
{
"FIXUP_DLX_32"
,
0
,
32
,
0
}
,
{
"FIXUP_DLX_HI16"
,
16
,
16
,
0
}
,
{
"FIXUP_DLX_LO16"
,
16
,
16
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> static void rs6000_init_dwarf_reg_sizes_extra ( tree address ) { if ( TARGET_SPE ) { int i ; machine_mode mode = TYPE_MODE ( char_type_node ) ; rtx addr = expand_expr ( address , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; rtx mem = gen_rtx_MEM ( BLKmode , addr ) ; rtx value = gen_int_mode ( 4 , mode ) ; for ( i = FIRST_SPE_HIGH_REGNO ; i < LAST_SPE_HIGH_REGNO + 1 ; i ++ ) { int column = DWARF_REG_TO_UNWIND_COLUMN ( DWARF2_FRAME_REG_OUT ( DWARF_FRAME_REGNUM ( i ) , true ) ) ; HOST_WIDE_INT offset = column * GET_MODE_SIZE ( mode ) ; emit_move_insn ( adjust_address ( mem , mode , offset ) , value ) ; } } if ( TARGET_MACHO && ! TARGET_ALTIVEC ) { int i ; machine_mode mode = TYPE_MODE ( char_type_node ) ; rtx addr = expand_expr ( address , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; rtx mem = gen_rtx_MEM ( BLKmode , addr ) ; rtx value = gen_int_mode ( 16 , mode ) ; for ( i = FIRST_ALTIVEC_REGNO ; i < LAST_ALTIVEC_REGNO + 1 ; i ++ ) { int column = DWARF_REG_TO_UNWIND_COLUMN ( DWARF2_FRAME_REG_OUT ( DWARF_FRAME_REGNUM ( i ) , true ) ) ; HOST_WIDE_INT offset = column * GET_MODE_SIZE ( mode ) ; emit_move_insn ( adjust_address ( mem , mode , offset ) , value ) ; } } } </s>

Fill in sizes of registers used by unwinder .


<s> void rs6000_sibcall_aix ( rtx value , rtx func_desc , rtx tlsarg , rtx cookie ) { rtx call [ 2 ] ; rtx insn ; rtx r12 = NULL_RTX ; rtx func_addr = func_desc ; gcc_assert ( INTVAL ( cookie ) == 0 ) ; if ( global_tlsarg ) tlsarg = global_tlsarg ; if ( GET_CODE ( func_desc ) != SYMBOL_REF && DEFAULT_ABI == ABI_ELFv2 ) { r12 = gen_rtx_REG ( Pmode , 12 ) ; emit_move_insn ( r12 , func_desc ) ; func_addr = gen_rtx_REG ( Pmode , CTR_REGNO ) ; emit_move_insn ( func_addr , r12 ) ; } call [ 0 ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_addr ) , tlsarg ) ; if ( value != NULL_RTX ) call [ 0 ] = gen_rtx_SET ( value , call [ 0 ] ) ; call [ 1 ] = simple_return_rtx ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( 2 , call ) ) ; insn = emit_call_insn ( insn ) ; if ( ! rs6000_pcrel_p ( ) ) use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , gen_rtx_REG ( Pmode , TOC_REGNUM ) ) ; if ( r12 ) use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , r12 ) ; } </s>

Expand code to perform a sibling call under the AIX or ELFv2 ABI .


<s> EVT X86TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsZeroVal , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( IsZeroVal && ! F -> hasFnAttr ( Attribute :: NoImplicitFloat ) ) { if ( Size >= 16 && ( Subtarget -> isUnalignedMemAccessFast ( ) || ( ( DstAlign == 0 || DstAlign >= 16 ) && ( SrcAlign == 0 || SrcAlign >= 16 ) ) ) && Subtarget -> getStackAlignment ( ) >= 16 ) { if ( Subtarget -> hasAVX ( ) && Subtarget -> getStackAlignment ( ) >= 32 ) return MVT :: v8f32 ; if ( Subtarget -> hasXMMInt ( ) ) return MVT :: v4i32 ; if ( Subtarget -> hasXMM ( ) ) return MVT :: v4f32 ; } else if ( ! MemcpyStrSrc && Size >= 8 && ! Subtarget -> is64Bit ( ) && Subtarget -> getStackAlignment ( ) >= 8 && Subtarget -> hasXMMInt ( ) ) { return MVT :: f64 ; } } if ( Subtarget -> is64Bit ( ) && Size >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> static void som_output_comdat_data_section_asm_op ( const char * data ) { in_section = NULL ; output_section_asm_op ( data ) ; } </s>

A get_unnamed_section callback for switching to comdat data sections . This function is only used with SOM .


<s> TargetTransformInfo X86TargetMachine :: getTargetTransformInfo ( const Function & F ) const { return TargetTransformInfo ( X86TTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool X86FrameLowering :: canSimplifyCallFramePseudos ( const MachineFunction & MF ) const { return hasReservedCallFrame ( MF ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> hasPreallocatedCall ( ) || ( hasFP ( MF ) && ! TRI -> hasStackRealignment ( MF ) ) || TRI -> hasBasePointer ( MF ) ; } </s>

canSimplifyCallFramePseudos - If there is a reserved call frame , the call frame pseudos can be simplified .


<s> bool PPCInstrInfo :: getMachineCombinerPatterns ( MachineInstr & Root , SmallVectorImpl < MachineCombinerPattern > & Patterns ) const { if ( Subtarget . getTargetMachine ( ) . getOptLevel ( ) != CodeGenOpt :: Aggressive ) return false ; if ( getFMAPatterns ( Root , Patterns ) ) return true ; return TargetInstrInfo :: getMachineCombinerPatterns ( Root , Patterns ) ; } </s>

Return true when there is potentially a faster code sequence for an instruction chain ending in Root .


<s> inline bool libcall_hasher :: equal ( const value_type * p1 , const compare_type * p2 ) { return rtx_equal_p ( p1 , p2 ) ; } </s>


<s>
unsigned
CAHPMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
llvm_unreachable
(
"Unhandled expression!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> static bool arm_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { machine_mode mode ; if ( size == UNITS_PER_WORD && aligned_p ) { fputs ( "\t.word\t" , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; if ( NEED_GOT_RELOC && flag_pic && making_const_table && ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF ) ) { if ( ! arm_pic_data_is_text_relative || ( GET_CODE ( x ) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P ( x ) ) ) fputs ( "(GOT)" , asm_out_file ) ; else fputs ( "(GOTOFF)" , asm_out_file ) ; } fputc ( '\n' , asm_out_file ) ; return true ; } mode = GET_MODE ( x ) ; if ( arm_vector_mode_supported_p ( mode ) ) { int i , units ; gcc_assert ( GET_CODE ( x ) == CONST_VECTOR ) ; units = CONST_VECTOR_NUNITS ( x ) ; size = GET_MODE_SIZE ( GET_MODE_INNER ( mode ) ) ; if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) for ( i = 0 ; i < units ; i ++ ) { rtx elt = CONST_VECTOR_ELT ( x , i ) ; assemble_integer ( elt , size , i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT , 1 ) ; } else for ( i = 0 ; i < units ; i ++ ) { rtx elt = CONST_VECTOR_ELT ( x , i ) ; REAL_VALUE_TYPE rval ; REAL_VALUE_FROM_CONST_DOUBLE ( rval , elt ) ; assemble_real ( rval , GET_MODE_INNER ( mode ) , i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT ) ; } return true ; } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . The ARM version needs to handle word-sized values specially .


<s> StringRef getPassName ( ) const override { return AARCH64_SPECULATION_HARDENING_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> bool run ( Controls & F , Controls & R ) { if ( ! route ( Order . data ( ) , Table . data ( ) , size ( ) , 0 ) ) return false ; getControls ( F , 0 , Forward ) ; getControls ( R , Log , Reverse ) ; return true ; } </s>

Run the analysis pass over a function and produce a dominator tree .


<s> static addr_space_t avr_nonconst_pointer_addrspace ( tree typ ) { while ( ARRAY_TYPE == TREE_CODE ( typ ) ) typ = TREE_TYPE ( typ ) ; if ( POINTER_TYPE_P ( typ ) ) { addr_space_t as ; tree target = TREE_TYPE ( typ ) ; if ( FUNCTION_TYPE == TREE_CODE ( target ) ) return avr_nonconst_pointer_addrspace ( TREE_TYPE ( target ) ) ; while ( TREE_CODE ( target ) == ARRAY_TYPE ) target = TREE_TYPE ( target ) ; as = TYPE_ADDR_SPACE ( target ) ; if ( ! ADDR_SPACE_GENERIC_P ( as ) && ( ! TYPE_READONLY ( target ) || avr_addrspace [ as ] . segment >= avr_n_flash || ( ! AVR_HAVE_LPM && avr_addrspace [ as ] . pointer_size > 2 ) ) ) { return as ; } return avr_nonconst_pointer_addrspace ( target ) ; } return ADDR_SPACE_GENERIC ; } </s>

Scan type TYP for pointer references to address space ASn . Return ADDR_SPACE_GENERIC ( i.e . 0 ) if all pointers targeting the AS are also declared to be CONST . Otherwise , return the respective address space , i.e . a value ! = 0 .


<s> bool csky_legitimate_pic_operand_p ( rtx x ) { if ( tls_unspec_mentioned_p ( x ) ) return true ; if ( csky_symbol_mentioned_p ( x ) || csky_label_mentioned_p ( x ) ) return false ; return true ; } </s>


<s>
const
char
*
Cpu0AsmPrinter
::
getCurrentABIString
(
)
const
{
switch
(
Subtarget
->
getTargetABI
(
)
)
{
case
Cpu0Subtarget
::
O32
:
return
"abi32"
;
default
:
llvm_unreachable
(
"Unknown Cpu0 ABI"
)
;
;
}
}
</s>


<s> BitVector BPFRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( BPF :: R10 ) ; Reserved . set ( BPF :: R11 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool X86TargetLowering :: isSplatValueForTargetNode ( SDValue Op , const APInt & DemandedElts , APInt & UndefElts , unsigned Depth ) const { unsigned NumElts = DemandedElts . getBitWidth ( ) ; unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { case X86ISD :: VBROADCAST : case X86ISD :: VBROADCAST_LOAD : UndefElts = APInt :: getNullValue ( NumElts ) ; return true ; } return TargetLowering :: isSplatValueForTargetNode ( Op , DemandedElts , UndefElts , Depth ) ; } </s>

Return true if vector Op has the same value across all DemandedElts , indicating any elements which may be undef in the output UndefElts .


"Expected label,@type declaration, got: "

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> void MipsMCCodeEmitter :: EmitInstruction ( uint64_t Val , unsigned Size , const MCSubtargetInfo & STI , raw_ostream & OS ) const { if ( IsLittleEndian && Size == 4 && isMicroMips ( STI ) ) { EmitInstruction ( Val >> 16 , 2 , STI , OS ) ; EmitInstruction ( Val , 2 , STI , OS ) ; } else { for ( unsigned i = 0 ; i < Size ; ++ i ) { unsigned Shift = IsLittleEndian ? i * 8 : ( Size - 1 - i ) * 8 ; EmitByte ( ( Val >> Shift ) & 0xff , OS ) ; } } } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool SIInstrInfo :: isLegalFLATOffset ( int64_t Offset , unsigned AddrSpace , uint64_t FlatVariant ) const { if ( ! ST . hasFlatInstOffsets ( ) ) return false ; if ( ST . hasFlatSegmentOffsetBug ( ) && FlatVariant == SIInstrFlags :: FLAT && ( AddrSpace == AMDGPUAS :: FLAT_ADDRESS || AddrSpace == AMDGPUAS :: GLOBAL_ADDRESS ) ) return false ; bool Signed = FlatVariant != SIInstrFlags :: FLAT ; if ( ST . hasNegativeScratchOffsetBug ( ) && FlatVariant == SIInstrFlags :: FlatScratch ) Signed = false ; if ( ST . hasNegativeUnalignedScratchOffsetBug ( ) && FlatVariant == SIInstrFlags :: FlatScratch && Offset < 0 && ( Offset % 4 ) != 0 ) { return false ; } unsigned N = AMDGPU :: getNumFlatOffsetBits ( ST , Signed ) ; return Signed ? isIntN ( N , Offset ) : isUIntN ( N , Offset ) ; } </s>

Returns if Offset is legal for the subtarget as the offset to a FLAT encoded instruction .

AMDGPU SI SIInstrFlags::FLAT AMDGPU AMDGPU SIInstrFlags::FLAT SIInstrFlags::FlatScratch SIInstrFlags::FlatScratch 0 4 0 AMDGPU::getNumFlatOffsetBits


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"IA64 (Itanium) Bundling Pass"
;
}
</s>


<s> static const char * ix86_mangle_type ( const_tree type ) { type = TYPE_MAIN_VARIANT ( type ) ; if ( TREE_CODE ( type ) != VOID_TYPE && TREE_CODE ( type ) != BOOLEAN_TYPE && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE ) return NULL ; if ( type == float128_type_node || type == float64x_type_node ) return NULL ; switch ( TYPE_MODE ( type ) ) { case E_BFmode : return "DF16b" ; case E_HFmode : return "DF16_" ; case E_TFmode : return "g" ; case E_XFmode : return "e" ; default : return NULL ; } } </s>

Return the mangling of TYPE if it is an extended fundamental type .


<s>
bool
X86ATTAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
const
Function
*
F
=
MF
.
getFunction
(
)
;
this
->
MF
=
&
MF
;
unsigned
CC
=
F
->
getCallingConv
(
)
;
SetupMachineFunction
(
MF
)
;
O
<<
"\n\n"
;
if
(
CC
==
CallingConv
::
X86_StdCall
||
CC
==
CallingConv
::
X86_FastCall
)
FunctionInfoMap
[
F
]
=
*
MF
.
getInfo
<
X86MachineFunctionInfo
>
(
)
;
EmitConstantPool
(
MF
.
getConstantPool
(
)
)
;
if
(
F
->
hasDLLExportLinkage
(
)
)
DLLExportedFns
.
insert
(
Mang
->
makeNameProper
(
F
->
getName
(
)
,
""
)
)
;
emitFunctionHeader
(
MF
)
;
if
(
TAI
->
doesSupportDebugInformation
(
)
||
TAI
->
doesSupportExceptionHandling
(
)
)
DW
->
BeginFunction
(
&
MF
)
;
bool
hasAnyRealCode
=
false
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
!
I
->
pred_empty
(
)
)
{
printBasicBlockLabel
(
I
,
true
,
true
,
VerboseAsm
)
;
O
<<
'\n'
;
}
for
(
MachineBasicBlock
::
const_iterator
II
=
I
->
begin
(
)
,
IE
=
I
->
end
(
)
;
II
!=
IE
;
++
II
)
{
if
(
!
II
->
isLabel
(
)
)
hasAnyRealCode
=
true
;
printMachineInstruction
(
II
)
;
}
}
if
(
Subtarget
->
isTargetDarwin
(
)
&&
!
hasAnyRealCode
)
{
O
<<
"\tnop\n"
;
}
if
(
TAI
->
hasDotTypeDotSizeDirective
(
)
)
O
<<
"\t.size\t"
<<
CurrentFnName
<<
", .-"
<<
CurrentFnName
<<
'\n'
;
if
(
TAI
->
doesSupportDebugInformation
(
)
)
DW
->
EndFunction
(
&
MF
)
;
EmitJumpTableInfo
(
MF
.
getJumpTableInfo
(
)
,
MF
)
;
O
.
flush
(
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool ARMCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs ) const { auto & TLI = * getTLI < ARMTargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb1Only ( ) ) return false ; if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; auto DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasPassPointeeByValueCopyAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , 8 > SplitArgInfos ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArgInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArgInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArgInfo , SplitArgInfos , MF ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgInfos , ArgHandler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> unsigned PPCTargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { return Subtarget . isPPC64 ( ) ? PPC :: X3 : PPC :: R3 ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


"%<#pragma GCC aarch64%> requires a string parameter"

"unknown %<#pragma GCC aarch64%> option %qs"


<s> EVT X86TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( ( ! IsMemset || ZeroMemset ) && ! F -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { if ( Size >= 16 && ( ! Subtarget -> isUnalignedMem16Slow ( ) || ( ( DstAlign == 0 || DstAlign >= 16 ) && ( SrcAlign == 0 || SrcAlign >= 16 ) ) ) ) { if ( Size >= 32 ) { if ( Subtarget -> hasInt256 ( ) ) return MVT :: v8i32 ; if ( Subtarget -> hasFp256 ( ) ) return MVT :: v8f32 ; } if ( Subtarget -> hasSSE2 ( ) ) return MVT :: v4i32 ; if ( Subtarget -> hasSSE1 ( ) ) return MVT :: v4f32 ; } else if ( ! MemcpyStrSrc && Size >= 8 && ! Subtarget -> is64Bit ( ) && Subtarget -> hasSSE2 ( ) ) { return MVT :: f64 ; } } if ( Subtarget -> is64Bit ( ) && Size >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


"switch statement of size %lu entries too large"

Expander for the ` casesi ' pattern . INDEX is the index of the switch statement . LOWER_BOUND is a CONST_INT that is the value of INDEX corresponding to the first table entry . RANGE is the number of table entries . TABLE is an ADDR_VEC that is the jump table . DEFAULT_LABEL is the address to branch to if INDEX is outside the range LOWER_BOUND to LOWER_BOUND+RANGE-1 .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Mips OptimizePICCall"
;
}
</s>


<s> const uint32_t * SystemZXPLINK64Registers :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return CSR_SystemZ_XPLINK64_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
StringRef
getPassName
(
)
const
override
{
return
"CSKY Constant Islands"
;
}
</s>


<s> const TargetRegisterClass * AArch64RegisterInfo :: getCrossCopyRegClass ( const TargetRegisterClass * RC ) const { if ( RC == & AArch64 :: FlagClassRegClass ) return & AArch64 :: GPR64RegClass ; return RC ; } </s>

getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or from .


<s> static unsigned findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const X86RegisterInfo * TRI , bool Is64Bit ) { const MachineFunction * MF = MBB . getParent ( ) ; if ( MF -> callsEHReturn ( ) ) return 0 ; const TargetRegisterClass & AvailableRegs = * TRI -> getGPRsForTailCall ( * MF ) ; if ( MBBI == MBB . end ( ) ) return 0 ; switch ( MBBI -> getOpcode ( ) ) { default : return 0 ; case TargetOpcode :: PATCHABLE_RET : case X86 :: RET : case X86 :: RETL : case X86 :: RETQ : case X86 :: RETIL : case X86 :: RETIQ : case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: TCRETURNmi64 : case X86 :: EH_RETURN : case X86 :: EH_RETURN64 : { SmallSet < uint16_t , 8 > Uses ; for ( unsigned i = 0 , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } for ( auto CS : AvailableRegs ) if ( ! Uses . count ( CS ) && CS != X86 :: RIP && CS != X86 :: RSP && CS != X86 :: ESP ) return CS ; } } return 0 ; } </s>

findDeadCallerSavedReg - Return a caller-saved register that is n't live when it reaches the `` return '' instruction .


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BRCOND : return LowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return LowerConstantPool ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: BlockAddress : return LowerBlockAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return LowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( Op , DAG ) ; case ISD :: SELECT : return LowerSELECT ( Op , DAG ) ; case ISD :: SELECT_CC : return LowerSELECT_CC ( Op , DAG ) ; case ISD :: SETCC : return LowerSETCC ( Op , DAG ) ; case ISD :: VASTART : return LowerVASTART ( Op , DAG ) ; case ISD :: FCOPYSIGN : return LowerFCOPYSIGN ( Op , DAG ) ; case ISD :: FABS : return LowerFABS ( Op , DAG ) ; case ISD :: FRAMEADDR : return LowerFRAMEADDR ( Op , DAG ) ; case ISD :: RETURNADDR : return LowerRETURNADDR ( Op , DAG ) ; case ISD :: EH_RETURN : return LowerEH_RETURN ( Op , DAG ) ; case ISD :: MEMBARRIER : return LowerMEMBARRIER ( Op , DAG ) ; case ISD :: ATOMIC_FENCE : return LowerATOMIC_FENCE ( Op , DAG ) ; case ISD :: SHL_PARTS : return LowerShiftLeftParts ( Op , DAG ) ; case ISD :: SRA_PARTS : return LowerShiftRightParts ( Op , DAG , true ) ; case ISD :: SRL_PARTS : return LowerShiftRightParts ( Op , DAG , false ) ; case ISD :: LOAD : return LowerLOAD ( Op , DAG ) ; case ISD :: STORE : return LowerSTORE ( Op , DAG ) ; case ISD :: INTRINSIC_WO_CHAIN : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case ISD :: INTRINSIC_W_CHAIN : return LowerINTRINSIC_W_CHAIN ( Op , DAG ) ; case ISD :: ADD : return LowerADD ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::BRCOND ISD::ConstantPool ISD::GlobalAddress ISD::BlockAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::SELECT ISD::SELECT_CC ISD::SETCC ISD::VASTART ISD::FCOPYSIGN ISD::FABS ISD::FRAMEADDR ISD::RETURNADDR ISD::EH_RETURN ISD::MEMBARRIER ISD::ATOMIC_FENCE ISD::SHL_PARTS ISD::SRA_PARTS ISD::SRL_PARTS ISD::LOAD ISD::STORE ISD::INTRINSIC_WO_CHAIN ISD::INTRINSIC_W_CHAIN ISD::ADD


<s> void GCNPassConfig :: addPostRegAlloc ( ) { addPass ( & SIFixVGPRCopiesID ) ; if ( getOptLevel ( ) > CodeGenOpt :: None ) addPass ( & SIOptimizeExecMaskingID ) ; TargetPassConfig :: addPostRegAlloc ( ) ; addPass ( & SILowerSGPRSpillsID ) ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


"sorry, I don't know how to store this sort of reg in the stack\n"

Store the specified register of the given register class to the specified stack frame index .


<s> bool PPCSubtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { if ( DarwinDirective == PPC :: DIR_440 ) return false ; Mode = TargetSubtargetInfo :: ANTIDEP_CRITICAL ; CriticalPathRCs . clear ( ) ; if ( isPPC64 ( ) ) CriticalPathRCs . push_back ( & PPC :: G8RCRegClass ) ; else CriticalPathRCs . push_back ( & PPC :: GPRCRegClass ) ; return OptLevel >= CodeGenOpt :: Default ; } </s>

True if the subtarget should run a scheduler after register allocation .

PowerPC PPC PPC::DIR_440 PPC PPC::G8RCRegClass PPC::GPRCRegClass


<s> static bool r10k_safe_mem_expr_p ( tree expr , unsigned HOST_WIDE_INT offset ) { poly_int64 bitoffset , bitsize ; tree inner , var_offset ; machine_mode mode ; int unsigned_p , reverse_p , volatile_p ; inner = get_inner_reference ( expr , & bitsize , & bitoffset , & var_offset , & mode , & unsigned_p , & reverse_p , & volatile_p ) ; if ( ! DECL_P ( inner ) || ! DECL_SIZE_UNIT ( inner ) || var_offset ) return false ; offset += bitoffset / BITS_PER_UNIT ; return offset < tree_to_uhwi ( DECL_SIZE_UNIT ( inner ) ) ; } </s>

Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is an in-range access to an automatic variable , or to an object with a link-time-constant address .


"instruction use requires an option to be enabled"

"unable to convert operands to instruction"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> void ia64_expand_widen_sum ( rtx operands [ 3 ] , bool unsignedp ) { machine_mode wmode ; rtx l , h , t , sign ; sign = ia64_unpack_sign ( operands [ 1 ] , unsignedp ) ; wmode = GET_MODE ( operands [ 0 ] ) ; l = gen_reg_rtx ( wmode ) ; h = gen_reg_rtx ( wmode ) ; ia64_unpack_assemble ( l , operands [ 1 ] , sign , false ) ; ia64_unpack_assemble ( h , operands [ 1 ] , sign , true ) ; t = expand_binop ( wmode , add_optab , l , operands [ 2 ] , NULL , 0 , OPTAB_DIRECT ) ; t = expand_binop ( wmode , add_optab , h , t , operands [ 0 ] , 0 , OPTAB_DIRECT ) ; if ( t != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , t ) ; } </s>

Emit an integral vector widening sum operations .


<s> static void nios2_asm_output_mi_thunk ( FILE * file , tree thunk_fndecl ATTRIBUTE_UNUSED , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { const char * fnname = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( thunk_fndecl ) ) ; rtx this_rtx , funexp ; rtx_insn * insn ; reload_completed = 1 ; if ( flag_pic ) nios2_load_pic_register ( ) ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , FIRST_ARG_REGNO + 1 ) ; else this_rtx = gen_rtx_REG ( Pmode , FIRST_ARG_REGNO ) ; nios2_emit_add_constant ( this_rtx , delta ) ; if ( vcall_offset ) { rtx tmp ; tmp = gen_rtx_REG ( Pmode , 2 ) ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , this_rtx ) ) ; nios2_emit_add_constant ( tmp , vcall_offset ) ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , tmp ) ) ; emit_insn ( gen_add2_insn ( this_rtx , tmp ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = 1 ; } funexp = XEXP ( DECL_RTL ( function ) , 0 ) ; nios2_adjust_call_address ( & funexp , gen_rtx_REG ( Pmode , 2 ) ) ; insn = emit_call_insn ( gen_sibcall_internal ( funexp , const0_rtx ) ) ; SIBLING_CALL_P ( insn ) = 1 ; insn = get_insns ( ) ; shorten_branches ( insn ) ; assemble_start_function ( thunk_fndecl , fnname ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; assemble_end_function ( thunk_fndecl , fnname ) ; reload_completed = 0 ; } </s>


<s> static void expand_set_or_movmem_via_rep ( rtx destmem , rtx srcmem , rtx destptr , rtx srcptr , rtx value , rtx orig_value , rtx count , machine_mode mode , bool issetmem ) { rtx destexp ; rtx srcexp ; rtx countreg ; HOST_WIDE_INT rounded_count ; if ( mode == QImode && CONST_INT_P ( count ) && ! ( INTVAL ( count ) & 3 ) && ( ! issetmem || orig_value == const0_rtx ) ) mode = SImode ; if ( destptr != XEXP ( destmem , 0 ) || GET_MODE ( destmem ) != BLKmode ) destmem = adjust_automodify_address_nv ( destmem , BLKmode , destptr , 0 ) ; countreg = ix86_zero_extend_to_Pmode ( scale_counter ( count , GET_MODE_SIZE ( mode ) ) ) ; if ( mode != QImode ) { destexp = gen_rtx_ASHIFT ( Pmode , countreg , GEN_INT ( exact_log2 ( GET_MODE_SIZE ( mode ) ) ) ) ; destexp = gen_rtx_PLUS ( Pmode , destexp , destptr ) ; } else destexp = gen_rtx_PLUS ( Pmode , destptr , countreg ) ; if ( ( ! issetmem || orig_value == const0_rtx ) && CONST_INT_P ( count ) ) { rounded_count = ( INTVAL ( count ) & ~ ( ( HOST_WIDE_INT ) GET_MODE_SIZE ( mode ) - 1 ) ) ; destmem = shallow_copy_rtx ( destmem ) ; set_mem_size ( destmem , rounded_count ) ; } else if ( MEM_SIZE_KNOWN_P ( destmem ) ) clear_mem_size ( destmem ) ; if ( issetmem ) { value = force_reg ( mode , gen_lowpart ( mode , value ) ) ; emit_insn ( gen_rep_stos ( destptr , countreg , destmem , value , destexp ) ) ; } else { if ( srcptr != XEXP ( srcmem , 0 ) || GET_MODE ( srcmem ) != BLKmode ) srcmem = adjust_automodify_address_nv ( srcmem , BLKmode , srcptr , 0 ) ; if ( mode != QImode ) { srcexp = gen_rtx_ASHIFT ( Pmode , countreg , GEN_INT ( exact_log2 ( GET_MODE_SIZE ( mode ) ) ) ) ; srcexp = gen_rtx_PLUS ( Pmode , srcexp , srcptr ) ; } else srcexp = gen_rtx_PLUS ( Pmode , srcptr , countreg ) ; if ( CONST_INT_P ( count ) ) { rounded_count = ( INTVAL ( count ) & ~ ( ( HOST_WIDE_INT ) GET_MODE_SIZE ( mode ) - 1 ) ) ; srcmem = shallow_copy_rtx ( srcmem ) ; set_mem_size ( srcmem , rounded_count ) ; } else { if ( MEM_SIZE_KNOWN_P ( srcmem ) ) clear_mem_size ( srcmem ) ; } emit_insn ( gen_rep_mov ( destptr , destmem , srcptr , srcmem , countreg , destexp , srcexp ) ) ; } } </s>

Output `` rep ; mov '' or `` rep ; stos '' instruction depending on ISSETMEM argument . When ISSETMEM is true , arguments SRCMEM and SRCPTR are ignored . When ISSETMEM is false , arguments VALUE and ORIG_VALUE are ignored . For setmem case , VALUE is a promoted to a wider size ORIG_VALUE . ORIG_VALUE is the original value passed to memset to fill the memory with . Other arguments have same meaning as for previous function .


<s> static rtx s390_got_symbol ( void ) { if ( ! got_symbol ) { got_symbol = gen_rtx_SYMBOL_REF ( Pmode , "_GLOBAL_OFFSET_TABLE_" ) ; SYMBOL_REF_FLAGS ( got_symbol ) = SYMBOL_FLAG_LOCAL ; } return got_symbol ; } </s>

Return the GOT table symbol . The symbol will be created when the function is invoked for the first time .


<s> unsigned RISCVInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : return 0 ; case RISCV :: SB : case RISCV :: SH : case RISCV :: SW : case RISCV :: FSW : case RISCV :: SD : case RISCV :: FSD : case RISCV :: VSE_V_um : break ; } if ( ( MI . getOpcode ( ) == RISCV :: VSE_V_um ) && MI . getOperand ( 0 ) . isFI ( ) ) { FrameIndex = MI . getOperand ( 0 ) . getIndex ( ) ; return MI . getOperand ( 1 ) . getReg ( ) ; } else if ( MI . getOperand ( 0 ) . isFI ( ) && MI . getOperand ( 1 ) . isImm ( ) && MI . getOperand ( 1 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 0 ) . getIndex ( ) ; return MI . getOperand ( 2 ) . getReg ( ) ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> static void aarch64_restore_callee_saves ( machine_mode mode , poly_int64 start_offset , unsigned start , unsigned limit , bool skip_wb , rtx * cfi_ops ) { rtx base_rtx = stack_pointer_rtx ; unsigned regno ; unsigned regno2 ; poly_int64 offset ; for ( regno = aarch64_next_callee_save ( start , limit ) ; regno <= limit ; regno = aarch64_next_callee_save ( regno + 1 , limit ) ) { if ( cfun -> machine -> reg_is_wrapped_separately [ regno ] ) continue ; rtx reg , mem ; int offset_diff ; if ( skip_wb && ( regno == cfun -> machine -> frame . wb_candidate1 || regno == cfun -> machine -> frame . wb_candidate2 ) ) continue ; reg = gen_rtx_REG ( mode , regno ) ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno ] ; mem = gen_frame_mem ( mode , plus_constant ( Pmode , base_rtx , offset ) ) ; regno2 = aarch64_next_callee_save ( regno + 1 , limit ) ; offset_diff = cfun -> machine -> frame . reg_offset [ regno2 ] - cfun -> machine -> frame . reg_offset [ regno ] ; if ( regno2 <= limit && ! cfun -> machine -> reg_is_wrapped_separately [ regno2 ] && known_eq ( GET_MODE_SIZE ( mode ) , offset_diff ) ) { rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; rtx mem2 ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno2 ] ; mem2 = gen_frame_mem ( mode , plus_constant ( Pmode , base_rtx , offset ) ) ; emit_insn ( aarch64_gen_load_pair ( mode , reg , mem , reg2 , mem2 ) ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg2 , * cfi_ops ) ; regno = regno2 ; } else emit_move_insn ( reg , mem ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg , * cfi_ops ) ; } } </s>

Emit code to restore the callee registers of mode MODE from register number START up to and including LIMIT . Restore from the stack offset START_OFFSET , skipping any write-back candidates if SKIP_WB is true . Write the appropriate REG_CFA_RESTORE notes into CFI_OPS .


<s> unsigned MipsFastISel :: fastEmitInst_rr ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , unsigned Op1 ) { if ( MachineInstOpcode == Mips :: MUL ) { unsigned ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , II . getNumDefs ( ) ) ; Op1 = constrainOperandRegClass ( II , Op1 , II . getNumDefs ( ) + 1 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 ) . addReg ( Op1 ) . addReg ( Mips :: HI0 , RegState :: ImplicitDefine | RegState :: Dead ) . addReg ( Mips :: LO0 , RegState :: ImplicitDefine | RegState :: Dead ) ; return ResultReg ; } return FastISel :: fastEmitInst_rr ( MachineInstOpcode , RC , Op0 , Op1 ) ; } </s>

Emit a MachineInstr with two register operands and a result register in the given register class .


<s>
void
SystemZAsmPrinter
::
emitFunctionEntryLabel
(
)
{
const
SystemZSubtarget
&
Subtarget
=
MF
->
getSubtarget
<
SystemZSubtarget
>
(
)
;
if
(
Subtarget
.
getTargetTriple
(
)
.
isOSzOS
(
)
)
{
MCContext
&
OutContext
=
OutStreamer
->
getContext
(
)
;
std
::
string
N
(
MF
->
getFunction
(
)
.
hasName
(
)
Twine
(
MF
->
getFunction
(
)
.
getName
(
)
)
.
concat
(
"_"
)
.
str
(
)
:
""
)
;
CurrentFnEPMarkerSym
=
OutContext
.
createTempSymbol
(
Twine
(
"EPM_"
)
.
concat
(
N
)
.
str
(
)
,
true
)
;
CurrentFnPPA1Sym
=
OutContext
.
createTempSymbol
(
Twine
(
"PPA1_"
)
.
concat
(
N
)
.
str
(
)
,
true
)
;
const
MachineFrameInfo
&
MFFrame
=
MF
->
getFrameInfo
(
)
;
bool
IsUsingAlloca
=
MFFrame
.
hasVarSizedObjects
(
)
;
uint8_t
Flags
=
0
;
if
(
IsUsingAlloca
)
Flags
|=
0x04
;
uint32_t
DSASize
=
MFFrame
.
getStackSize
(
)
;
uint32_t
DSAAndFlags
=
DSASize
&
0xFFFFFFE0
;
DSAAndFlags
|=
Flags
;
OutStreamer
->
AddComment
(
"XPLINK Routine Layout Entry"
)
;
OutStreamer
->
emitLabel
(
CurrentFnEPMarkerSym
)
;
OutStreamer
->
AddComment
(
"Eyecatcher 0x00C300C500C500"
)
;
OutStreamer
->
emitIntValueInHex
(
0x00C300C500C500
,
7
)
;
OutStreamer
->
AddComment
(
"Mark Type C'1'"
)
;
OutStreamer
->
emitInt8
(
0xF1
)
;
OutStreamer
->
AddComment
(
"Offset to PPA1"
)
;
OutStreamer
->
emitAbsoluteSymbolDiff
(
CurrentFnPPA1Sym
,
CurrentFnEPMarkerSym
,
4
)
;
if
(
OutStreamer
->
isVerboseAsm
(
)
)
{
OutStreamer
->
AddComment
(
"DSA Size 0x"
+
Twine
::
utohexstr
(
DSASize
)
)
;
OutStreamer
->
AddComment
(
"Entry Flags"
)
;
if
(
Flags
&
0x04
)
OutStreamer
->
AddComment
(
"  Bit 2: 1 = Uses alloca"
)
;
else
OutStreamer
->
AddComment
(
"  Bit 2: 0 = Does not use alloca"
)
;
}
OutStreamer
->
emitInt32
(
DSAAndFlags
)
;
}
AsmPrinter
::
emitFunctionEntryLabel
(
)
;
}
</s>

EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function .


<s> unsigned ARCompactRegisterInfo :: getRARegister ( ) const { return ARC :: BLINK ; } </s>

This method should return the register where the return address can be found .


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override { return createTPCPostMachineScheduler ( C ) ; } </s>

Similar to createMachineScheduler but used when postRA machine scheduling is enabled .


<s> virtual bool runOnFunction ( Function & Fn ) { GlobalBaseReg = 0 ; SelectionDAGISel :: runOnFunction ( Fn ) ; InsertVRSaveCode ( Fn ) ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static bool ix86_can_inline_p ( tree caller , tree callee ) { bool ret = false ; tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET ( caller ) ; tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET ( callee ) ; if ( ! callee_tree ) ret = true ; else if ( ! caller_tree ) ret = false ; else { struct cl_target_option * caller_opts = TREE_TARGET_OPTION ( caller_tree ) ; struct cl_target_option * callee_opts = TREE_TARGET_OPTION ( callee_tree ) ; if ( ( caller_opts -> x_ix86_isa_flags & callee_opts -> x_ix86_isa_flags ) != callee_opts -> x_ix86_isa_flags ) ret = false ; else if ( caller_opts -> x_target_flags != callee_opts -> x_target_flags ) ret = false ; else if ( caller_opts -> arch != callee_opts -> arch ) ret = false ; else if ( caller_opts -> tune != callee_opts -> tune ) ret = false ; else if ( caller_opts -> x_ix86_fpmath != callee_opts -> x_ix86_fpmath ) ret = false ; else if ( caller_opts -> branch_cost != callee_opts -> branch_cost ) ret = false ; else ret = true ; } return ret ; } </s>

Hook to determine if one function can safely inline another .


<s> static inline tree def_builtin_const ( HOST_WIDE_INT mask , HOST_WIDE_INT mask2 , const char * name , enum ix86_builtin_func_type tcode , enum ix86_builtins code ) { tree decl = def_builtin ( mask , mask2 , name , tcode , code ) ; if ( decl ) TREE_READONLY ( decl ) = 1 ; else ix86_builtins_isa [ ( int ) code ] . const_p = true ; return decl ; } </s>

Likewise , but also marks the function as `` const '' .


<s>
MachineBasicBlock
::
iterator
SIFrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
int64_t
Amount
=
I
->
getOperand
(
0
)
.
getImm
(
)
;
if
(
Amount
==
0
)
return
MBB
.
erase
(
I
)
;
const
GCNSubtarget
&
ST
=
MF
.
getSubtarget
<
GCNSubtarget
>
(
)
;
const
SIInstrInfo
*
TII
=
ST
.
getInstrInfo
(
)
;
const
DebugLoc
&
DL
=
I
->
getDebugLoc
(
)
;
unsigned
Opc
=
I
->
getOpcode
(
)
;
bool
IsDestroy
=
Opc
==
TII
->
getCallFrameDestroyOpcode
(
)
;
uint64_t
CalleePopAmount
=
IsDestroy
I
->
getOperand
(
1
)
.
getImm
(
)
:
0
;
if
(
!
hasReservedCallFrame
(
MF
)
)
{
Amount
=
alignTo
(
Amount
,
getStackAlign
(
)
)
;
assert
(
isUInt
<
32
>
(
Amount
)
&&
"exceeded stack address space size"
)
;
const
SIMachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
SIMachineFunctionInfo
>
(
)
;
Register
SPReg
=
MFI
->
getStackPtrOffsetReg
(
)
;
Amount
*=
getScratchScaleFactor
(
ST
)
;
if
(
IsDestroy
)
Amount
=
Amount
;
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
AMDGPU
::
S_ADD_I32
)
,
SPReg
)
.
addReg
(
SPReg
)
.
addImm
(
Amount
)
;
}
else
if
(
CalleePopAmount
!=
0
)
{
llvm_unreachable
(
"is this used?"
)
;
}
return
MBB
.
erase
(
I
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


"WebAssembly doesn't support non-C calling conventions"

"WebAssembly doesn't support tail call yet"

"WebAssembly doesn't support patch point yet"

"WebAssembly doesn't support struct return yet"

"WebAssembly doesn't support more than 1 returned value yet"

"WebAssembly doesn't support varargs yet"

This hook must be implemented to lower calls into the specified DAG .


<s> InstructionCost HexagonTTIImpl :: getScalarizationOverhead ( VectorType * Ty , const APInt & DemandedElts , bool Insert , bool Extract ) { return BaseT :: getScalarizationOverhead ( Ty , DemandedElts , Insert , Extract ) ; } </s>

Estimate the overhead of scalarizing an instruction .


<s> int iq2000_initial_elimination_offset ( int from , int to ATTRIBUTE_UNUSED ) { int offset ; compute_frame_size ( get_frame_size ( ) ) ; if ( ( from ) == FRAME_POINTER_REGNUM ) ( offset ) = 0 ; else if ( ( from ) == ARG_POINTER_REGNUM ) ( offset ) = ( cfun -> machine -> total_size ) ; else if ( ( from ) == RETURN_ADDRESS_POINTER_REGNUM ) { if ( leaf_function_p ( ) ) ( offset ) = 0 ; else ( offset ) = cfun -> machine -> gp_sp_offset + ( ( UNITS_PER_WORD - ( POINTER_SIZE / BITS_PER_UNIT ) ) * ( BYTES_BIG_ENDIAN != 0 ) ) ; } return offset ; } </s>

Implement INITIAL_ELIMINATION_OFFSET . FROM is either the frame pointer , argument pointer , or return address pointer . TO is either the stack pointer or hard frame pointer .


<s> static rtx ia64_gen_spec_check ( rtx_insn * insn , rtx_insn * label , ds_t ds ) { rtx op1 , pat , check_pat ; gen_func_t gen_check ; int mode_no ; mode_no = get_mode_no_for_insn ( insn ) ; gcc_assert ( mode_no >= 0 ) ; if ( label ) op1 = label ; else { gcc_assert ( ! ia64_needs_block_p ( ds ) ) ; op1 = copy_rtx ( recog_data . operand [ 1 ] ) ; } gen_check = get_spec_check_gen_function ( ds , mode_no , label == NULL_RTX , true ) ; check_pat = gen_check ( copy_rtx ( recog_data . operand [ 0 ] ) , op1 ) ; pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == COND_EXEC ) check_pat = gen_rtx_COND_EXEC ( VOIDmode , copy_rtx ( COND_EXEC_TEST ( pat ) ) , check_pat ) ; return check_pat ; } </s>

Generate ( or regenerate ) a recovery check for INSN .


<s> void UnwindOpcodeAssembler :: EmitSetSP ( uint16_t Reg ) { EmitInt8 ( ARM :: EHABI :: UNWIND_OPCODE_SET_VSP | Reg ) ; } </s>

Emit unwind opcodes to copy address from source register to $ sp .


<s> int get_sequence_length ( rtx_insn * insns ) { rtx_insn * insn ; int length ; for ( insn = insns , length = 0 ; insn ; insn = NEXT_INSN ( insn ) ) length += get_attr_length ( insn ) ; return length ; } </s>


<s>
SDValue
AMDGPUTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
Op
.
getNode
(
)
->
dump
(
)
;
llvm_unreachable
(
"Custom lowering code for this"
"instruction is not implemented yet!"
)
;
break
;
case
ISD
::
SDIV
:
return
LowerSDIV
(
Op
,
DAG
)
;
case
ISD
::
SREM
:
return
LowerSREM
(
Op
,
DAG
)
;
case
ISD
::
SIGN_EXTEND_INREG
:
return
LowerSIGN_EXTEND_INREG
(
Op
,
DAG
)
;
case
ISD
::
BRCOND
:
return
LowerBRCOND
(
Op
,
DAG
)
;
case
ISD
::
CONCAT_VECTORS
:
return
LowerCONCAT_VECTORS
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_SUBVECTOR
:
return
LowerEXTRACT_SUBVECTOR
(
Op
,
DAG
)
;
case
ISD
::
FrameIndex
:
return
LowerFrameIndex
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
UDIVREM
:
return
LowerUDIVREM
(
Op
,
DAG
)
;
case
ISD
::
UINT_TO_FP
:
return
LowerUINT_TO_FP
(
Op
,
DAG
)
;
}
return
Op
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .