<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; ST = & MF . getSubtarget < GCNSubtarget > ( ) ; if ( ! ST -> hasHardClauses ( ) ) return false ; const SIInstrInfo * SII = ST -> getInstrInfo ( ) ; const TargetRegisterInfo * TRI = ST -> getRegisterInfo ( ) ; bool Changed = false ; for ( auto & MBB : MF ) { ClauseInfo CI ; for ( auto & MI : MBB ) { HardClauseType Type = getHardClauseType ( MI ) ; int64_t Dummy1 ; bool Dummy2 ; unsigned Dummy3 ; SmallVector < const MachineOperand * , 4 > BaseOps ; if ( Type <= LAST_REAL_HARDCLAUSE_TYPE ) { if ( ! SII -> getMemOperandsWithOffsetWidth ( MI , BaseOps , Dummy1 , Dummy2 , Dummy3 , TRI ) ) { Type = HARDCLAUSE_ILLEGAL ; } } if ( CI . Length == 64 || ( CI . Length && Type != HARDCLAUSE_INTERNAL && Type != HARDCLAUSE_IGNORE && ( Type != CI . Type || ! SII -> shouldClusterMemOps ( CI . BaseOps , BaseOps , 2 , 2 ) ) ) ) { Changed |= emitClause ( CI , SII ) ; CI = ClauseInfo ( ) ; } if ( CI . Length ) { if ( Type != HARDCLAUSE_IGNORE ) { if ( Type == HARDCLAUSE_INTERNAL ) { ++ CI . TrailingInternalLength ; } else { ++ CI . Length ; CI . Length += CI . TrailingInternalLength ; CI . TrailingInternalLength = 0 ; CI . Last = & MI ; CI . BaseOps = std :: move ( BaseOps ) ; } } } else if ( Type <= LAST_REAL_HARDCLAUSE_TYPE ) { CI = ClauseInfo { Type , & MI , & MI , 1 , 0 , std :: move ( BaseOps ) } ; } } if ( CI . Length ) Changed |= emitClause ( CI , SII ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> int is_function_label_plus_const ( rtx op ) { if ( GET_CODE ( op ) == CONST ) op = XEXP ( op , 0 ) ; return ( GET_CODE ( op ) == PLUS && function_label_operand ( XEXP ( op , 0 ) , Pmode ) && GET_CODE ( XEXP ( op , 1 ) ) == CONST_INT ) ; } </s>

Returns 1 if OP is a function label involved in a simple addition with a constant . Used to keep certain patterns from matching during instruction combination .


<s> bool Z80TargetLowering :: isTypeDesirableForOp ( unsigned Opc , EVT VT ) const { if ( ! isTypeLegal ( VT ) ) return false ; if ( Subtarget . is16Bit ( ) ) return true ; switch ( Opc ) { default : case ISD :: SIGN_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: ANY_EXTEND : return true ; case ISD :: LOAD : case ISD :: STORE : case ISD :: ADD : case ISD :: SUB : return VT != MVT :: i16 ; case ISD :: MUL : case ISD :: AND : case ISD :: OR : case ISD :: XOR : case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return VT != MVT :: i24 ; } } </s>

Return true if the target has native support for the specified value type and it is 'desirable ' to use the type for the given node type .


<s> void X86FrameLowering :: inlineStackProbe ( MachineFunction & MF , MachineBasicBlock & PrologMBB ) const { auto Where = llvm :: find_if ( PrologMBB , [ ] ( MachineInstr & MI ) { return MI . getOpcode ( ) == X86 :: STACKALLOC_W_PROBING ; } ) ; if ( Where != PrologMBB . end ( ) ) { DebugLoc DL = PrologMBB . findDebugLoc ( Where ) ; emitStackProbeInline ( MF , PrologMBB , Where , DL , true ) ; Where -> eraseFromParent ( ) ; } } </s>

Replace a StackProbe inline-stub with the actual probe code inline .


<s> int m32c_prepare_move ( rtx * operands , machine_mode mode ) { if ( far_addr_space_p ( operands [ 0 ] ) && CONSTANT_P ( operands [ 1 ] ) ) { operands [ 1 ] = force_reg ( GET_MODE ( operands [ 0 ] ) , operands [ 1 ] ) ; } if ( TARGET_A16 && mode == PSImode ) return m32c_split_move ( operands , mode , 1 ) ; if ( ( GET_CODE ( operands [ 0 ] ) == MEM ) && ( GET_CODE ( XEXP ( operands [ 0 ] , 0 ) ) == PRE_MODIFY ) ) { rtx pmv = XEXP ( operands [ 0 ] , 0 ) ; rtx dest_reg = XEXP ( pmv , 0 ) ; rtx dest_mod = XEXP ( pmv , 1 ) ; emit_insn ( gen_rtx_SET ( Pmode , dest_reg , dest_mod ) ) ; operands [ 0 ] = gen_rtx_MEM ( mode , dest_reg ) ; } if ( can_create_pseudo_p ( ) && MEM_P ( operands [ 0 ] ) && MEM_P ( operands [ 1 ] ) ) operands [ 1 ] = copy_to_mode_reg ( mode , operands [ 1 ] ) ; return 0 ; } </s>

Used to emit move instructions . We split some moves , and avoid mem-mem moves .


<s> bool WebAssemblyFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const auto * RegInfo = MF . getSubtarget < WebAssemblySubtarget > ( ) . getRegisterInfo ( ) ; return MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MFI -> hasStackMap ( ) || MFI -> hasPatchPoint ( ) || RegInfo -> needsStackRealignment ( MF ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static unsigned int aarch64_hard_regno_nregs ( unsigned regno , machine_mode mode ) { HOST_WIDE_INT lowest_size = constant_lower_bound ( GET_MODE_SIZE ( mode ) ) ; switch ( aarch64_regno_regclass ( regno ) ) { case FP_REGS : case FP_LO_REGS : case FP_LO8_REGS : { unsigned int vec_flags = aarch64_classify_vector_mode ( mode ) ; if ( vec_flags & VEC_SVE_DATA ) return exact_div ( GET_MODE_SIZE ( mode ) , aarch64_vl_bytes ( mode , vec_flags ) ) . to_constant ( ) ; return CEIL ( lowest_size , UNITS_PER_VREG ) ; } case PR_REGS : case PR_LO_REGS : case PR_HI_REGS : case FFR_REGS : case PR_AND_FFR_REGS : return 1 ; default : return CEIL ( lowest_size , UNITS_PER_WORD ) ; } gcc_unreachable ( ) ; } </s>


<s> const X86Subtarget * getSubtargetImpl ( ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> void AMDGPUPassConfig :: addPostRegAlloc ( ) { const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . getGeneration ( ) > AMDGPUSubtarget :: NORTHERN_ISLANDS ) { addPass ( createSIShrinkInstructionsPass ( ) , false ) ; } } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> bool Error ( SMLoc L , const Twine & Msg , SMRange Range = None ) { return getParser ( ) . Error ( L , Msg , Range ) ; } </s>

Return an error at the location L , with the message Msg .


<s> static rtx_insn * frame_emit_load ( int regno , rtx addr , rtx * cfa_restores ) { rtx reg = gen_rtx_REG ( Pmode , regno ) ; rtx mem = gen_frame_mem ( Pmode , addr ) ; if ( cfa_restores ) * cfa_restores = alloc_reg_note ( REG_CFA_RESTORE , reg , * cfa_restores ) ; return emit_insn ( gen_movsi ( reg , mem ) ) ; } </s>

Emit a load in the stack frame to load REGNO from address ADDR . Add a REG_CFA_RESTORE note to CFA_RESTORES if CFA_RESTORES is non-null . Return the emitted insn .


<s> bool s390_contiguous_bitmask_p ( unsigned HOST_WIDE_INT in , bool wrap_p , int size , int * start , int * end ) { int bs = HOST_BITS_PER_WIDE_INT ; bool b ; gcc_assert ( ! ! start == ! ! end ) ; if ( ( in & ( ( ~ HOST_WIDE_INT_0U ) >> ( bs - size ) ) ) == 0 ) return false ; b = s390_contiguous_bitmask_nowrap_p ( in , size , start , end ) ; if ( b ) return true ; if ( ! wrap_p ) return false ; b = s390_contiguous_bitmask_nowrap_p ( ~ in , size , start , end ) ; if ( b && start ) { int s = * start ; int e = * end ; gcc_assert ( s >= 1 ) ; * start = ( ( e + 1 ) & ( bs - 1 ) ) ; * end = ( ( s - 1 + bs ) & ( bs - 1 ) ) ; } return b ; } </s>

Return true if IN contains a contiguous bitfield in the lower SIZE bits and no other bits are set in IN . POS and LENGTH can be used to obtain the start position and the length of the bitfield . POS gives the position of the first bit of the bitfield counting from the lowest order bit starting with zero . In order to use this value for S/390 instructions this has to be converted to `` bits big endian '' style .


<s> VariantKind getKind ( ) const { return Kind ; } </s>


<s>
void
addExpr
(
MCInst
&
Inst
,
const
MCExpr
*
Expr
)
const
{
assert
(
Expr
&&
"Expr shouldn't be null!"
)
;
int64_t
Imm
=
0
;
RISCVMCExpr
::
VariantKind
VK
=
RISCVMCExpr
::
VK_RISCV_None
;
bool
IsConstant
=
evaluateConstantImm
(
Expr
,
Imm
,
VK
)
;
if
(
IsConstant
)
Inst
.
addOperand
(
MCOperand
::
createImm
(
Imm
)
)
;
else
Inst
.
addOperand
(
MCOperand
::
createExpr
(
Expr
)
)
;
}
</s>

RI5CY
"Expr shouldn't be null!"
0
RISCV
RISCV
RISCV


Given a MEM OP with an address that includes a splittable symbol or other large constant , emit some instructions to do the split and return a new MEM .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesAll ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


"Dangerous instruction in branch delay slot!"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void MetadataStreamerV3 :: begin ( const Module & Mod ) { emitVersion ( ) ; emitPrintf ( Mod ) ; getRootMetadata ( "amdhsa.kernels" ) . reset ( new msgpack :: ArrayNode ( ) ) ; } </s>


<s> unsigned WebAssemblyFastISel :: zeroExtend ( unsigned Reg , const Value * V , MVT :: SimpleValueType From , MVT :: SimpleValueType To ) { if ( To == MVT :: i64 ) { if ( From == MVT :: i64 ) return copyValue ( Reg ) ; Reg = zeroExtendToI32 ( Reg , V , From ) ; unsigned Result = createResultReg ( & WebAssembly :: I64RegClass ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( WebAssembly :: I64_EXTEND_U_I32 ) , Result ) . addReg ( Reg ) ; return Result ; } if ( To == MVT :: i32 ) return zeroExtendToI32 ( Reg , V , From ) ; return 0 ; } </s>

Return a new range in the specified integer type , which must be strictly larger than the current type .


<s> unsigned PPCTargetLowering :: getByValTypeAlignment ( Type * Ty ) const { const TargetMachine & TM = getTargetMachine ( ) ; if ( TM . getSubtarget < PPCSubtarget > ( ) . isDarwin ( ) ) return 4 ; if ( VectorType * VTy = dyn_cast < VectorType > ( Ty ) ) if ( VTy -> getBitWidth ( ) >= 128 ) return 16 ; if ( PPCSubTarget . isPPC64 ( ) ) return 8 ; return 4 ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


"__float128 and __ibm128 cannot be used in the same "

"__ibm128 and long double cannot be used in the same "

"__float128 and long double cannot be used in the same "

Return the diagnostic message string if the binary operation OP is not permitted on TYPE1 and TYPE2 , NULL otherwise .


<s>
void
mt_override_options
(
void
)
{
if
(
mt_cpu_string
!=
)
{
if
(
!
strcmp
(
mt_cpu_string
,
"ms1-64-001"
)
)
mt_cpu
=
PROCESSOR_MS1_64_001
;
else
if
(
!
strcmp
(
mt_cpu_string
,
"ms1-16-002"
)
)
mt_cpu
=
PROCESSOR_MS1_16_002
;
else
if
(
!
strcmp
(
mt_cpu_string
,
"ms1-16-003"
)
)
mt_cpu
=
PROCESSOR_MS1_16_003
;
else
if
(
!
strcmp
(
mt_cpu_string
,
"ms2"
)
)
mt_cpu
=
PROCESSOR_MS2
;
else
error
(
"bad value (%s) for -march= switch"
,
mt_cpu_string
)
;
}
else
mt_cpu
=
PROCESSOR_MS1_64_001
;
if
(
flag_exceptions
)
{
flag_omit_frame_pointer
=
0
;
flag_gcse
=
0
;
}
mt_flag_delayed_branch
=
flag_delayed_branch
;
flag_delayed_branch
=
0
;
init_machine_status
=
mt_init_machine_status
;
}
</s>


"Arch64 does not support GOT PC rel with extra offset"

Get the target specific PC relative GOT entry relocation .


<s> int mmix_shiftable_wyde_value ( uint64_t value ) { int i ; int has_candidate = 0 ; for ( i = 0 ; i < 4 ; i ++ ) { if ( value & 65535 ) { if ( has_candidate ) return 0 ; else has_candidate = 1 ; } value >>= 16 ; } return 1 ; } </s>

Return 1 if value is 0 .. 65535 * 2 * * ( 16 * N ) for N=0 .. 3. else return 0 .


<s> static rtx force_offsettable ( rtx addr , HOST_WIDE_INT size , bool reuse ) { rtx base = addr ; rtx offs = const0_rtx ; if ( GET_CODE ( base ) == PLUS ) { offs = XEXP ( base , 1 ) ; base = XEXP ( base , 0 ) ; } if ( ! REG_P ( base ) || ( REGNO ( base ) != STACK_POINTER_REGNUM && REGNO_PTR_FRAME_P ( REGNO ( addr ) ) ) || ! CONST_INT_P ( offs ) || ! SMALL_INT ( INTVAL ( offs ) ) || ! SMALL_INT ( INTVAL ( offs ) + size ) ) { if ( reuse ) emit_insn ( gen_add2_insn ( addr , offs ) ) ; else addr = copy_to_mode_reg ( Pmode , addr ) ; } return addr ; } </s>

Helper function of arc_expand_movmem . ADDR points to a chunk of memory . Emit code and return an potentially modified address such that offsets up to SIZE are can be added to yield a legitimate address . if REUSE is set , ADDR is a register that may be modified .


<s> const TOYInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> void s390_expand_plus_operand ( rtx target , rtx src , rtx scratch ) { rtx sum1 , sum2 ; struct s390_address ad ; gcc_assert ( GET_CODE ( src ) == PLUS ) ; gcc_assert ( GET_MODE ( src ) == Pmode ) ; sum1 = find_replacement ( & XEXP ( src , 0 ) ) ; sum2 = find_replacement ( & XEXP ( src , 1 ) ) ; src = gen_rtx_PLUS ( Pmode , sum1 , sum2 ) ; if ( ! s390_decompose_address ( src , & ad ) || ( ad . base && ! REG_OK_FOR_BASE_STRICT_P ( ad . base ) ) || ( ad . indx && ! REG_OK_FOR_INDEX_STRICT_P ( ad . indx ) ) ) { if ( true_regnum ( sum1 ) < 1 || true_regnum ( sum1 ) > 15 ) { emit_move_insn ( scratch , sum1 ) ; sum1 = scratch ; } if ( true_regnum ( sum2 ) < 1 || true_regnum ( sum2 ) > 15 ) { emit_move_insn ( scratch , sum2 ) ; sum2 = scratch ; } if ( sum1 == scratch && sum2 == scratch ) { debug_rtx ( src ) ; gcc_unreachable ( ) ; } src = gen_rtx_PLUS ( Pmode , sum1 , sum2 ) ; } s390_load_address ( target , src ) ; } </s>

Generate code to load SRC , which is PLUS that is not a legitimate operand for the LA instruction , into TARGET . SCRATCH may be used as scratch register .


<s> static bool nvptx_return_in_memory ( const_tree type , const_tree ) { machine_mode mode = TYPE_MODE ( type ) ; if ( ! RETURN_IN_REG_P ( mode ) ) return true ; return false ; } </s>


<s>
CCAssignFn
*
ARMFastISel
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
Return
,
bool
isVarArg
)
{
switch
(
CC
)
{
default
:
report_fatal_error
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
if
(
Subtarget
->
hasVFP2Base
(
)
&&
!
isVarArg
)
{
if
(
!
Subtarget
->
isAAPCS_ABI
(
)
)
return
(
Return
RetFastCC_ARM_APCS
:
FastCC_ARM_APCS
)
;
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
}
LLVM_FALLTHROUGH
;
case
CallingConv
::
C
:
case
CallingConv
::
CXX_FAST_TLS
:
if
(
Subtarget
->
isAAPCS_ABI
(
)
)
{
if
(
Subtarget
->
hasVFP2Base
(
)
&&
TM
.
Options
.
FloatABIType
==
FloatABI
::
Hard
&&
!
isVarArg
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
else
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
}
else
{
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
}
case
CallingConv
::
ARM_AAPCS_VFP
:
case
CallingConv
::
Swift
:
if
(
!
isVarArg
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
LLVM_FALLTHROUGH
;
case
CallingConv
::
ARM_AAPCS
:
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
case
CallingConv
::
ARM_APCS
:
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
case
CallingConv
::
GHC
:
if
(
Return
)
report_fatal_error
(
"Can't return in GHC call convention"
)
;
else
return
CC_ARM_APCS_GHC
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .

ARM
ARM
"Unsupported calling convention"
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
"Can't return in GHC call convention"
ARM


<s>
unsigned
MOSMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isImm
(
)
)
return
MO
.
getImm
(
)
;
assert
(
MO
.
isExpr
(
)
)
;
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
if
(
isa
<
MCSymbolRefExpr
>
(
Expr
)
)
{
Fixups
.
push_back
(
MCFixup
::
create
(
0
,
Expr
,
MCFixupKind
::
FK_Data_1
)
)
;
return
0
;
}
int64_t
Res
;
if
(
Expr
->
evaluateAsAbsolute
(
Res
)
)
{
return
Res
;
}
llvm_unreachable
(
"Unhandled expression!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> bool NVPTXAllocaHoisting :: runOnFunction ( Function & function ) { bool functionModified = false ; Function :: iterator I = function . begin ( ) ; Instruction * firstTerminatorInst = ( I ++ ) -> getTerminator ( ) ; for ( Function :: iterator E = function . end ( ) ; I != E ; ++ I ) { for ( BasicBlock :: iterator BI = I -> begin ( ) , BE = I -> end ( ) ; BI != BE ; ) { AllocaInst * allocaInst = dyn_cast < AllocaInst > ( BI ++ ) ; if ( allocaInst && isa < ConstantInt > ( allocaInst -> getArraySize ( ) ) ) { allocaInst -> moveBefore ( firstTerminatorInst ) ; functionModified = true ; } } } return functionModified ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> const TargetRegisterClass * SIInstrInfo :: getOpRegClass ( const MachineInstr & MI , unsigned OpNo ) const { const MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const MCInstrDesc & Desc = get ( MI . getOpcode ( ) ) ; if ( MI . isVariadic ( ) || OpNo >= Desc . getNumOperands ( ) || Desc . OpInfo [ OpNo ] . RegClass == - 1 ) { Register Reg = MI . getOperand ( OpNo ) . getReg ( ) ; if ( Reg . isVirtual ( ) ) return MRI . getRegClass ( Reg ) ; return RI . getPhysRegClass ( Reg ) ; } unsigned RCID = Desc . OpInfo [ OpNo ] . RegClass ; return RI . getRegClass ( RCID ) ; } </s>

Return the correct register class for OpNo .


<s> static rtx arm_find_sub_rtx_with_code ( rtx pattern , rtx_code code , bool find_any_shift ) { subrtx_var_iterator :: array_type array ; FOR_EACH_SUBRTX_VAR ( iter , array , pattern , NONCONST ) { rtx x = * iter ; if ( find_any_shift ) { if ( arm_rtx_shift_left_p ( x ) ) return x ; else for ( unsigned int i = 0 ; i < ARRAY_SIZE ( shift_rtx_codes ) ; i ++ ) if ( GET_CODE ( x ) == shift_rtx_codes [ i ] ) return x ; } if ( GET_CODE ( x ) == code ) return x ; } return NULL_RTX ; } </s>

Traverse PATTERN looking for a sub-rtx with RTX_CODE CODE . If FIND_ANY_SHIFT then we are interested in anything which can reasonably be described as a SHIFT RTX .


<s> void arm_expand_compare_and_swap ( rtx operands [ ] ) { rtx bval , rval , mem , oldval , newval , is_weak , mod_s , mod_f , x ; machine_mode mode ; rtx ( * gen ) ( rtx , rtx , rtx , rtx , rtx , rtx , rtx ) ; bval = operands [ 0 ] ; rval = operands [ 1 ] ; mem = operands [ 2 ] ; oldval = operands [ 3 ] ; newval = operands [ 4 ] ; is_weak = operands [ 5 ] ; mod_s = operands [ 6 ] ; mod_f = operands [ 7 ] ; mode = GET_MODE ( mem ) ; if ( TARGET_HAVE_LDACQ && INTVAL ( mod_f ) == MEMMODEL_ACQUIRE && INTVAL ( mod_s ) == MEMMODEL_RELEASE ) mod_s = GEN_INT ( MEMMODEL_ACQ_REL ) ; switch ( mode ) { case QImode : case HImode : rval = gen_reg_rtx ( SImode ) ; oldval = convert_modes ( SImode , mode , oldval , true ) ; case SImode : if ( ! arm_add_operand ( oldval , SImode ) ) oldval = force_reg ( SImode , oldval ) ; break ; case DImode : if ( ! cmpdi_operand ( oldval , mode ) ) oldval = force_reg ( mode , oldval ) ; break ; default : gcc_unreachable ( ) ; } switch ( mode ) { case QImode : gen = gen_atomic_compare_and_swapqi_1 ; break ; case HImode : gen = gen_atomic_compare_and_swaphi_1 ; break ; case SImode : gen = gen_atomic_compare_and_swapsi_1 ; break ; case DImode : gen = gen_atomic_compare_and_swapdi_1 ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( rval , mem , oldval , newval , is_weak , mod_s , mod_f ) ) ; if ( mode == QImode || mode == HImode ) emit_move_insn ( operands [ 1 ] , gen_lowpart ( mode , rval ) ) ; x = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_EQ ( SImode , x , const0_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , bval , x ) ) ; } </s>


<s> TargetPassConfig * JVMTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new JVMPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> static void vms_asm_out_constructor ( rtx symbol , int priority ATTRIBUTE_UNUSED ) { switch_to_section ( ctors_section ) ; assemble_align ( BITS_PER_WORD ) ; assemble_integer ( symbol , UNITS_PER_WORD , BITS_PER_WORD , 1 ) ; } </s>


<s> static int ft32_arg_partial_bytes ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int bytes_left , size ; if ( * cum >= 8 ) return 0 ; if ( ft32_pass_by_reference ( cum_v , arg ) ) size = 4 ; else if ( arg . type ) { if ( AGGREGATE_TYPE_P ( arg . type ) ) return 0 ; size = int_size_in_bytes ( arg . type ) ; } else size = GET_MODE_SIZE ( arg . mode ) ; bytes_left = ( 4 * 6 ) - ( ( * cum - 2 ) * 4 ) ; if ( size > bytes_left ) return bytes_left ; else return 0 ; } </s>

Some function arguments will only partially fit in the registers that hold arguments . Given a new arg , return the number of bytes that fit in argument passing registers .


"getJumpOffset16OpValue expects only expressions or an immediate"

getJumpOffset16OpValue - Return binary encoding of the jump target operand .


<s> bool ix86_can_use_return_insn_p ( void ) { struct ix86_frame frame ; if ( ! reload_completed || frame_pointer_needed ) return 0 ; if ( crtl -> args . pops_args && crtl -> args . size >= 32768 ) return 0 ; ix86_compute_frame_layout ( & frame ) ; return ( frame . stack_pointer_offset == UNITS_PER_WORD && ( frame . nregs + frame . nsseregs ) == 0 ) ; } </s>

Return 1 if it is appropriate to emit ` ret ' instructions in the body of a function . Do this only if the epilogue is simple , needing a couple of insns . Prior to reloading , we ca n't tell how many registers must be saved , so return 0 then . Return 0 if there is no frame marker to de-allocate .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
k_Immediate
:
OS
<<
"Imm<"
;
OS
<<
*
Imm
.
Val
;
OS
<<
">"
;
break
;
case
k_Memory
:
OS
<<
"Mem<"
;
Mem
.
Base
->
print
(
OS
)
;
OS
<<
", "
;
OS
<<
*
Mem
.
Off
;
OS
<<
">"
;
break
;
case
k_RegisterIndex
:
OS
<<
"RegIdx<"
<<
RegIdx
.
Index
<<
":"
<<
RegIdx
.
Kind
<<
">"
;
break
;
case
k_Token
:
OS
<<
Tok
.
Data
;
break
;
case
k_RegList
:
OS
<<
"RegList< "
;
for
(
auto
Reg
:
(
*
RegList
.
List
)
)
OS
<<
Reg
<<
" "
;
OS
<<
">"
;
break
;
case
k_RegPair
:
OS
<<
"RegPair<"
<<
RegIdx
.
Index
<<
","
<<
RegIdx
.
Index
+
1
<<
">"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s>
bool
R600VectorRegMerger
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
TII
=
static_cast
<
const
R600InstrInfo
*
>
(
Fn
.
getTarget
(
)
.
getInstrInfo
(
)
)
;
MRI
=
&
(
Fn
.
getRegInfo
(
)
)
;
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
MachineBasicBlock
*
MB
=
MBB
;
PreviousRegSeq
.
clear
(
)
;
PreviousRegSeqByReg
.
clear
(
)
;
PreviousRegSeqByUndefCount
.
clear
(
)
;
for
(
MachineBasicBlock
::
iterator
MII
=
MB
->
begin
(
)
,
MIIE
=
MB
->
end
(
)
;
MII
!=
MIIE
;
++
MII
)
{
MachineInstr
*
MI
=
MII
;
if
(
MI
->
getOpcode
(
)
!=
AMDGPU
::
REG_SEQUENCE
)
continue
;
RegSeqInfo
RSI
(
*
MRI
,
MI
)
;
unsigned
Reg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
if
(
!
areAllUsesSwizzeable
(
Reg
)
)
continue
;
DEBUG
(
dbgs
(
)
<<
"Trying to optimize "
;
MI
->
dump
(
)
;
)
;
RegSeqInfo
CandidateRSI
;
std
::
vector
<
std
::
pair
<
unsigned
,
unsigned
>
>
RemapChan
;
DEBUG
(
dbgs
(
)
<<
"Using common slots...\n"
;
)
;
if
(
tryMergeUsingCommonSlot
(
RSI
,
CandidateRSI
,
RemapChan
)
)
{
RemoveMI
(
CandidateRSI
.
Instr
)
;
MII
=
RebuildVector
(
&
RSI
,
&
CandidateRSI
,
RemapChan
)
;
trackRSI
(
RSI
)
;
continue
;
}
DEBUG
(
dbgs
(
)
<<
"Using free slots...\n"
;
)
;
RemapChan
.
clear
(
)
;
if
(
tryMergeUsingFreeSlot
(
RSI
,
CandidateRSI
,
RemapChan
)
)
{
RemoveMI
(
CandidateRSI
.
Instr
)
;
MII
=
RebuildVector
(
&
RSI
,
&
CandidateRSI
,
RemapChan
)
;
trackRSI
(
RSI
)
;
continue
;
}
trackRSI
(
RSI
)
;
}
}
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .

R600
SI
0
"Trying to optimize "
SI
"Using common slots...\n"
SI
SI
SI
SI
SI
SI
SI
"Using free slots...\n"
SI
SI
SI
SI
SI
SI
SI
SI
SI


<s> void RISCVFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterClass * RC = & RISCV :: GPRRegClass ; if ( ! isInt < 11 > ( MFI . estimateStackSize ( MF ) ) ) { int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RegScavFI ) ; } } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> static rtx move_to_x ( int opno , rtx before ) { rtx src = OP ( opno ) ; machine_mode mode = GET_MODE ( src ) ; rtx reg ; if ( mode == VOIDmode ) mode = recog_data . operand_mode [ opno ] ; reg = ( mode == QImode ) ? X : AX ; if ( mode == QImode || ! is_virtual_register ( OP ( opno ) ) ) { OP ( opno ) = move_to_acc ( opno , before ) ; OP ( opno ) = move_acc_to_reg ( OP ( opno ) , X_REG , before ) ; return reg ; } return gen_and_emit_move ( reg , src , before , true ) ; } </s>

Copy SRC to X , placing any generated insns before BEFORE . Returns X RTX .


<s> void ConvergingVLIWScheduler :: schedNode ( SUnit * SU , bool IsTopNode ) { if ( IsTopNode ) { SU -> TopReadyCycle = Top . CurrCycle ; Top . bumpNode ( SU ) ; } else { SU -> BotReadyCycle = Bot . CurrCycle ; Bot . bumpNode ( SU ) ; } } </s>

ScheduleDAGMI has scheduled an instruction - tell HazardRec about it .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"LC3 Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"every device must have an associate ELF architecture"

Gets the ELF architecture for the e_flags field of an ELF object file .


<s> TargetLowering :: AtomicExpansionKind RISCVTargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { if ( AI -> isFloatingPointOperation ( ) ) return AtomicExpansionKind :: CmpXChg ; unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size == 8 || Size == 16 ) return AtomicExpansionKind :: MaskedIntrinsic ; return AtomicExpansionKind :: None ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Hexagon generate mux instructions"
;
}
</s>

Hexagon
"Hexagon generate mux instructions"


<s> SDValue WebAssemblyTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : return SDValue ( ) ; case ISD :: VECTOR_SHUFFLE : return performVECTOR_SHUFFLECombine ( N , DCI ) ; case ISD :: SIGN_EXTEND : case ISD :: ZERO_EXTEND : return performVectorExtendCombine ( N , DCI ) ; case ISD :: FP_TO_SINT_SAT : case ISD :: FP_TO_UINT_SAT : case ISD :: FP_ROUND : case ISD :: CONCAT_VECTORS : return performVectorTruncZeroCombine ( N , DCI ) ; case ISD :: TRUNCATE : return performTruncateCombine ( N , DCI ) ; } } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> auto HexagonVectorCombine :: isZero ( const Value * Val ) const -> bool { if ( auto * C = dyn_cast < Constant > ( Val ) ) return C -> isZeroValue ( ) ; return false ; } </s>

Return true if the expression is a constant zero .


"Didn't find MI in its own basic block?"

getOffsetOf - Return the current offset of the specified machine instruction from the start of the function .


"Should be handled target independently"

Targets should implement this to emit instructions .


<s> static void s390_asm_file_start ( void ) { default_file_start ( ) ; s390_asm_output_machine_for_arch ( asm_out_file ) ; } </s>


<s> static void rs6000_option_override ( void ) { ( void ) rs6000_option_override_internal ( true ) ; opt_pass * pass_analyze_swaps = make_pass_analyze_swaps ( g ) ; struct register_pass_info analyze_swaps_info = { pass_analyze_swaps , "cse1" , 1 , PASS_POS_INSERT_BEFORE } ; register_pass ( & analyze_swaps_info ) ; } </s>

Implement TARGET_OPTION_OVERRIDE . On the RS/6000 this is used to define the target cpu type .


<s>
void
HexagonCommonGEP
::
materialize
(
NodeToValueMap
&
Loc
)
{
DEBUG
(
dbgs
(
)
<<
"Nodes before materialization:\n"
<<
Nodes
<<
'\n'
)
;
NodeChildrenMap
NCM
;
NodeVect
Roots
;
invert_find_roots
(
Nodes
,
NCM
,
Roots
)
;
while
(
!
Roots
.
empty
(
)
)
{
NodeVect
::
iterator
First
=
Roots
.
begin
(
)
;
GepNode
*
Root
=
*
First
,
*
Last
=
*
First
;
Roots
.
erase
(
First
)
;
NodeVect
;
bool
LastUsed
=
false
;
unsigned
LastCN
=
0
;
Value
*
LocV
=
Loc
[
Last
]
;
if
(
!
LocV
)
continue
;
BasicBlock
*
LastB
=
cast
<
BasicBlock
>
(
LocV
)
;
do
{
.
push_back
(
Last
)
;
LastUsed
=
(
Last
->
Flags
&
GepNode
::
Used
)
;
if
(
LastUsed
)
break
;
NodeChildrenMap
::
iterator
CF
=
NCM
.
find
(
Last
)
;
LastCN
=
(
CF
!=
NCM
.
end
(
)
)
CF
->
second
.
size
(
)
:
0
;
if
(
LastCN
!=
1
)
break
;
GepNode
*
Child
=
CF
->
second
.
front
(
)
;
BasicBlock
*
ChildB
=
cast_or_null
<
BasicBlock
>
(
Loc
[
Child
]
)
;
if
(
ChildB
!=
nullptr
&&
LastB
!=
ChildB
)
break
;
Last
=
Child
;
}
while
(
true
)
;
BasicBlock
::
iterator
InsertAt
=
LastB
->
getTerminator
(
)
->
getIterator
(
)
;
if
(
LastUsed
||
LastCN
>
0
)
{
ValueVect
Urs
;
getAllUsersForNode
(
Root
,
Urs
,
NCM
)
;
BasicBlock
::
iterator
FirstUse
=
first_use_of_in_block
(
Urs
,
LastB
)
;
if
(
FirstUse
!=
LastB
->
end
(
)
)
InsertAt
=
FirstUse
;
}
Value
*
NewInst
=
fabricateGEP
(
,
InsertAt
,
LastB
)
;
if
(
LastCN
>
0
)
{
NodeVect
&
Cs
=
NCM
[
Last
]
;
for
(
NodeVect
::
iterator
I
=
Cs
.
begin
(
)
,
E
=
Cs
.
end
(
)
;
I
!=
E
;
++
I
)
{
GepNode
*
CN
=
*
I
;
CN
->
Flags
&=
~
GepNode
::
Internal
;
CN
->
Flags
|=
GepNode
::
Root
;
CN
->
BaseVal
=
NewInst
;
Roots
.
push_back
(
CN
)
;
}
}
if
(
LastUsed
)
{
NodeToUsesMap
::
iterator
UF
=
Uses
.
find
(
Last
)
;
assert
(
UF
!=
Uses
.
end
(
)
&&
"No use information found"
)
;
UseSet
&
Us
=
UF
->
second
;
for
(
UseSet
::
iterator
I
=
Us
.
begin
(
)
,
E
=
Us
.
end
(
)
;
I
!=
E
;
++
I
)
{
Use
*
U
=
*
I
;
U
->
set
(
NewInst
)
;
}
}
}
}
</s>

This method can be implemented to generate a mapped Value on demand .


<s> static bool sparc_lra_p ( void ) { return TARGET_LRA ; } </s>

Return true if we use LRA instead of reload pass .


<s> unsigned AMDGPUAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & Op , unsigned Kind ) { AMDGPUOperand & Operand = ( AMDGPUOperand & ) Op ; switch ( Kind ) { case MCK_addr64 : return Operand . isAddr64 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_gds : return Operand . isGDS ( ) ? Match_Success : Match_InvalidOperand ; case MCK_glc : return Operand . isGLC ( ) ? Match_Success : Match_InvalidOperand ; case MCK_idxen : return Operand . isIdxen ( ) ? Match_Success : Match_InvalidOperand ; case MCK_offen : return Operand . isOffen ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SSrc32 : return Operand . isSSrc32 ( ) ? Match_Success : Match_InvalidOperand ; default : return Match_InvalidOperand ; } } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> static bool ia64_legitimate_constant_p ( machine_mode mode , rtx x ) { switch ( GET_CODE ( x ) ) { case CONST_INT : case LABEL_REF : return true ; case CONST_DOUBLE : if ( GET_MODE ( x ) == VOIDmode || mode == SFmode || mode == DFmode ) return true ; return satisfies_constraint_G ( x ) ; case CONST : case SYMBOL_REF : if ( tls_symbolic_operand_type ( x ) == 0 ) { HOST_WIDE_INT addend = 0 ; rtx op = x ; if ( GET_CODE ( op ) == CONST && GET_CODE ( XEXP ( op , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( op , 0 ) , 1 ) ) == CONST_INT ) { addend = INTVAL ( XEXP ( XEXP ( op , 0 ) , 1 ) ) ; op = XEXP ( XEXP ( op , 0 ) , 0 ) ; } if ( any_offset_symbol_operand ( op , mode ) || function_operand ( op , mode ) ) return true ; if ( aligned_offset_symbol_operand ( op , mode ) ) return ( addend & 0x3fff ) == 0 ; return false ; } return false ; case CONST_VECTOR : if ( mode == V2SFmode ) return satisfies_constraint_Y ( x ) ; return ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT && GET_MODE_SIZE ( mode ) <= 8 ) ; default : return false ; } } </s>

Return true if X is a constant that is valid for some immediate field in an instruction .


<s> bool HexagonRegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { return MF . getSubtarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) ; } </s>

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot .


<s> void i386_pe_seh_unwind_emit ( FILE * out_file , rtx_insn * insn ) { rtx note , pat ; bool handled_one = false ; struct seh_frame_state * seh ; if ( ! TARGET_SEH ) return ; seh = cfun -> machine -> seh ; if ( NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_SWITCH_TEXT_SECTIONS ) { rtx_insn * prev = prev_active_insn ( insn ) ; if ( prev && ( CALL_P ( prev ) || ! insn_nothrow_p ( prev ) ) ) fputs ( "\tnop\n" , out_file ) ; fputs ( "\t.seh_endproc\n" , out_file ) ; seh -> in_cold_section = true ; return ; } if ( NOTE_P ( insn ) || ! RTX_FRAME_RELATED_P ( insn ) ) return ; if ( seh -> after_prologue ) return ; for ( note = REG_NOTES ( insn ) ; note ; note = XEXP ( note , 1 ) ) { switch ( REG_NOTE_KIND ( note ) ) { case REG_FRAME_RELATED_EXPR : pat = XEXP ( note , 0 ) ; goto found ; case REG_CFA_DEF_CFA : case REG_CFA_EXPRESSION : gcc_unreachable ( ) ; break ; case REG_CFA_REGISTER : gcc_unreachable ( ) ; case REG_CFA_ADJUST_CFA : pat = XEXP ( note , 0 ) ; if ( pat == NULL ) { pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , 0 , 0 ) ; } seh_cfa_adjust_cfa ( out_file , seh , pat ) ; handled_one = true ; break ; case REG_CFA_OFFSET : pat = XEXP ( note , 0 ) ; if ( pat == NULL ) pat = single_set ( insn ) ; seh_cfa_offset ( out_file , seh , pat ) ; handled_one = true ; break ; default : break ; } } if ( handled_one ) return ; pat = PATTERN ( insn ) ; found : seh_frame_related_expr ( out_file , seh , pat ) ; } </s>

This function looks at a single insn and emits any SEH directives required for unwind of this insn .


<s> SDValue MipsTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SDNode * CallNode , const Type * RetTy ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; MipsCC MipsCCInfo ( CallConv , Subtarget -> isABI_O32 ( ) , Subtarget -> isFP64bit ( ) , CCInfo ) ; MipsCCInfo . analyzeCallResult ( Ins , Subtarget -> mipsSEUsesSoftFloat ( ) , CallNode , RetTy ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( 1 ) ; InFlag = Val . getValue ( 2 ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( ISD :: BITCAST , DL , RVLocs [ i ] . getValVT ( ) , Val ) ; InVals . push_back ( Val ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static bool mips_breakable_sequence_p ( rtx_insn * insn ) { return ( insn && GET_CODE ( PATTERN ( insn ) ) == SEQUENCE && TARGET_CB_MAYBE && get_attr_compact_form ( SEQ_BEGIN ( insn ) ) != COMPACT_FORM_NEVER ) ; } </s>

A SEQUENCE is breakable iff the branch inside it has a compact form and the target has compact branches .


<s> bool AArch64FastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Add : case Instruction :: Sub : return selectAddSub ( I ) ; case Instruction :: Mul : return selectMul ( I ) ; case Instruction :: SDiv : return selectSDiv ( I ) ; case Instruction :: SRem : if ( ! selectBinaryOp ( I , ISD :: SREM ) ) return selectRem ( I , ISD :: SREM ) ; return true ; case Instruction :: URem : if ( ! selectBinaryOp ( I , ISD :: UREM ) ) return selectRem ( I , ISD :: UREM ) ; return true ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return selectShift ( I ) ; case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : return selectLogicalOp ( I ) ; case Instruction :: Br : return selectBranch ( I ) ; case Instruction :: IndirectBr : return selectIndirectBr ( I ) ; case Instruction :: BitCast : if ( ! FastISel :: selectBitCast ( I ) ) return selectBitCast ( I ) ; return true ; case Instruction :: FPToSI : if ( ! selectCast ( I , ISD :: FP_TO_SINT ) ) return selectFPToInt ( I , true ) ; return true ; case Instruction :: FPToUI : return selectFPToInt ( I , false ) ; case Instruction :: ZExt : case Instruction :: SExt : return selectIntExt ( I ) ; case Instruction :: Trunc : if ( ! selectCast ( I , ISD :: TRUNCATE ) ) return selectTrunc ( I ) ; return true ; case Instruction :: FPExt : return selectFPExt ( I ) ; case Instruction :: FPTrunc : return selectFPTrunc ( I ) ; case Instruction :: SIToFP : if ( ! selectCast ( I , ISD :: SINT_TO_FP ) ) return selectIntToFP ( I , true ) ; return true ; case Instruction :: UIToFP : return selectIntToFP ( I , false ) ; case Instruction :: Load : return selectLoad ( I ) ; case Instruction :: Store : return selectStore ( I ) ; case Instruction :: FCmp : case Instruction :: ICmp : return selectCmp ( I ) ; case Instruction :: Select : return selectSelect ( I ) ; case Instruction :: Ret : return selectRet ( I ) ; case Instruction :: FRem : return selectFRem ( I ) ; case Instruction :: GetElementPtr : return selectGetElementPtr ( I ) ; case Instruction :: AtomicCmpXchg : return selectAtomicCmpXchg ( cast < AtomicCmpXchgInst > ( I ) ) ; } ( void ) & CC_AArch64_DarwinPCS_VarArg ; ( void ) & CC_AArch64_Win64_VarArg ; return selectOperator ( I , I -> getOpcode ( ) ) ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> bool MSP430InstrInfo :: isUnpredicatedTerminator ( const MachineInstr * MI ) const { const TargetInstrDesc & TID = MI -> getDesc ( ) ; if ( ! TID . isTerminator ( ) ) return false ; if ( TID . isBranch ( ) && ! TID . isBarrier ( ) ) return true ; if ( ! TID . isPredicable ( ) ) return true ; return ! isPredicated ( MI ) ; } </s>

Returns true if the instruction is a terminator instruction that has not been predicated .


<s> unsigned SystemZRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? SystemZ :: R11D : SystemZ :: R15D ; } </s>


<s> void flushPendingInstructions ( MCStreamer & Out ) override { if ( ! inImplicitITBlock ( ) ) { assert ( PendingConditionalInsts . size ( ) == 0 ) ; return ; } unsigned Mask = getITMaskEncoding ( ) ; MCInst ITInst ; ITInst . setOpcode ( ARM :: t2IT ) ; ITInst . addOperand ( MCOperand :: createImm ( ITState . Cond ) ) ; ITInst . addOperand ( MCOperand :: createImm ( Mask ) ) ; Out . EmitInstruction ( ITInst , getSTI ( ) ) ; assert ( PendingConditionalInsts . size ( ) <= 4 ) ; for ( MCInst Inst : PendingConditionalInsts ) { Out . EmitInstruction ( Inst , getSTI ( ) ) ; } PendingConditionalInsts . clear ( ) ; ITState . Mask = 0 ; ITState . CurPosition = ~ 0U ; } </s>

Ensure that all previously parsed instructions have been emitted to the output streamer , if the target does not emit them immediately .


<s> const MipsTargetMachine & getTargetMachine ( ) { return static_cast < const MipsTargetMachine & > ( TM ) ; } </s>

Return the target machine ( if available ) .


"getMemOperandWithOffset only supports base "

Return true if get the base operand , byte offset of an instruction and the memory width .


<s> bool HexagonMCChecker :: check ( bool FullCheck ) { bool chkP = checkPredicates ( ) ; bool chkNV = checkNewValues ( ) ; bool chkR = checkRegisters ( ) ; bool chkRRO = checkRegistersReadOnly ( ) ; checkRegisterCurDefs ( ) ; bool chkS = checkSolo ( ) ; bool chkSh = true ; if ( FullCheck ) chkSh = checkShuffle ( ) ; bool chkSl = true ; if ( FullCheck ) chkSl = checkSlots ( ) ; bool chkAXOK = checkAXOK ( ) ; bool chkCofMax1 = checkCOFMax1 ( ) ; bool chkHWLoop = checkHWLoop ( ) ; bool chkLegalVecRegPair = checkLegalVecRegPair ( ) ; bool chk = chkP && chkNV && chkR && chkRRO && chkS && chkSh && chkSl && chkAXOK && chkCofMax1 && chkHWLoop && chkLegalVecRegPair ; return chk ; } </s>

Check if the constraints are satisfiable .


<s> EVT SystemZTargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> int ARMTTIImpl :: getIntImmCost ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) { if ( ( Opcode == Instruction :: SDiv || Opcode == Instruction :: UDiv || Opcode == Instruction :: SRem || Opcode == Instruction :: URem ) && Idx == 1 ) return 0 ; if ( Opcode == Instruction :: And ) return std :: min ( getIntImmCost ( Imm , Ty ) , getIntImmCost ( ~ Imm , Ty ) ) ; if ( Opcode == Instruction :: Add ) return std :: min ( getIntImmCost ( Imm , Ty ) , getIntImmCost ( - Imm , Ty ) ) ; if ( Opcode == Instruction :: ICmp && Imm . isNegative ( ) && Ty -> getIntegerBitWidth ( ) == 32 ) { int64_t NegImm = - Imm . getSExtValue ( ) ; if ( ST -> isThumb2 ( ) && NegImm < 1 << 12 ) return 0 ; if ( ST -> isThumb ( ) && NegImm < 1 << 8 ) return 0 ; } if ( Opcode == Instruction :: Xor && Imm . isAllOnesValue ( ) ) return 0 ; return getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> static int rs6000_hard_regno_mode_ok ( int regno , machine_mode mode ) { int last_regno = regno + rs6000_hard_regno_nregs [ mode ] [ regno ] - 1 ; if ( COMPLEX_MODE_P ( mode ) ) mode = GET_MODE_INNER ( mode ) ; if ( mode == PTImode ) return ( IN_RANGE ( regno , FIRST_GPR_REGNO , LAST_GPR_REGNO ) && IN_RANGE ( last_regno , FIRST_GPR_REGNO , LAST_GPR_REGNO ) && ( ( regno & 1 ) == 0 ) ) ; if ( TARGET_VSX && VSX_REGNO_P ( regno ) && ( VECTOR_MEM_VSX_P ( mode ) || FLOAT128_VECTOR_P ( mode ) || reg_addr [ mode ] . scalar_in_vmx_p || ( TARGET_VSX_TIMODE && mode == TImode ) || ( TARGET_VADDUQM && mode == V1TImode ) ) ) { if ( FP_REGNO_P ( regno ) ) return FP_REGNO_P ( last_regno ) ; if ( ALTIVEC_REGNO_P ( regno ) ) { if ( GET_MODE_SIZE ( mode ) != 16 && ! reg_addr [ mode ] . scalar_in_vmx_p ) return 0 ; return ALTIVEC_REGNO_P ( last_regno ) ; } } if ( INT_REGNO_P ( regno ) ) return INT_REGNO_P ( last_regno ) ; if ( FP_REGNO_P ( regno ) ) { if ( FLOAT128_VECTOR_P ( mode ) ) return false ; if ( SCALAR_FLOAT_MODE_P ( mode ) && ( mode != TDmode || ( regno % 2 ) == 0 ) && FP_REGNO_P ( last_regno ) ) return 1 ; if ( GET_MODE_CLASS ( mode ) == MODE_INT ) { if ( GET_MODE_SIZE ( mode ) == UNITS_PER_FP_WORD ) return 1 ; if ( TARGET_VSX_SMALL_INTEGER ) { if ( mode == SImode ) return 1 ; if ( TARGET_P9_VECTOR && ( mode == HImode || mode == QImode ) ) return 1 ; } } if ( PAIRED_SIMD_REGNO_P ( regno ) && TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE ( mode ) ) return 1 ; return 0 ; } if ( CR_REGNO_P ( regno ) ) return GET_MODE_CLASS ( mode ) == MODE_CC ; if ( CA_REGNO_P ( regno ) ) return mode == Pmode || mode == SImode ; if ( ALTIVEC_REGNO_P ( regno ) ) return ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) || mode == V1TImode ) ; if ( SPE_SIMD_REGNO_P ( regno ) && TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) return 1 ; return GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD ; } </s>

Value is 1 if hard register REGNO can hold a value of machine-mode MODE .


runOnMachineFunction - Emit the function body .


<s> bool ok_for_simple_arith_logic_operands ( rtx * , machine_mode ) { return ! visium_flags_exposed ; } </s>

Return true if the operands are valid for a simple arithmetic or logical insn .


<s> static rtx sparc_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return sparc_function_value_1 ( NULL_TREE , mode , false ) ; } </s>


<s> rtx ix86_fixup_binary_operands ( enum rtx_code code , enum machine_mode mode , rtx operands [ ] ) { int matching_memory ; rtx src1 , src2 , dst ; dst = operands [ 0 ] ; src1 = operands [ 1 ] ; src2 = operands [ 2 ] ; if ( GET_RTX_CLASS ( code ) == RTX_COMM_ARITH && ( rtx_equal_p ( dst , src2 ) || immediate_operand ( src1 , mode ) ) ) { rtx temp = src1 ; src1 = src2 ; src2 = temp ; } matching_memory = 0 ; if ( GET_CODE ( dst ) == MEM ) { if ( rtx_equal_p ( dst , src1 ) ) matching_memory = 1 ; else if ( GET_RTX_CLASS ( code ) == RTX_COMM_ARITH && rtx_equal_p ( dst , src2 ) ) matching_memory = 2 ; else dst = gen_reg_rtx ( mode ) ; } if ( GET_CODE ( src1 ) == MEM && GET_CODE ( src2 ) == MEM ) { if ( matching_memory != 2 ) src2 = force_reg ( mode , src2 ) ; else src1 = force_reg ( mode , src1 ) ; } if ( ( CONSTANT_P ( src1 ) || ( ! matching_memory && GET_CODE ( src1 ) == MEM ) ) && GET_RTX_CLASS ( code ) != RTX_COMM_ARITH ) src1 = force_reg ( mode , src1 ) ; src1 = operands [ 1 ] = src1 ; src2 = operands [ 2 ] = src2 ; return dst ; } </s>

Fix up OPERANDS to satisfy ix86_binary_operator_ok . Return the destination to use for the operation . If different from the true destination in operands [ 0 ] , a copy operation will be required .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s>
int
m32c_extra_constraint_p
(
rtx
value
,
char
c
,
const
char
*
str
)
{
int
rv
=
m32c_extra_constraint_p2
(
value
,
c
,
str
)
;
fprintf
(
stderr
,
"\nconstraint %.*s: %d\n"
,
CONSTRAINT_LEN
(
c
,
str
)
,
str
,
rv
)
;
debug_rtx
(
value
)
;
return
rv
;
}
</s>

This is for when we 're debugging the above .


<s> static void vms_add_crtl_xlat ( const char * name , size_t nlen , const char * id_str , size_t id_len ) { tree targ ; targ = get_identifier_with_length ( name , nlen ) ; gcc_assert ( ! IDENTIFIER_TRANSPARENT_ALIAS ( targ ) ) ; IDENTIFIER_TRANSPARENT_ALIAS ( targ ) = 1 ; TREE_CHAIN ( targ ) = get_identifier_with_length ( id_str , id_len ) ; vec_safe_push ( aliases_id , targ ) ; } </s>

Add a CRTL translation . This simply use the transparent alias mechanism , which is platform independent and works with the # pragma extern_prefix ( which set the assembler name ) .


<s> void RISCVAsmPrinter :: emitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; MCInst TmpInst ; LowerRISCVMachineInstrToMCInst ( MI , TmpInst , * this ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

Targets should implement this to emit instructions .


<s> int registers_ok_for_quad_peep ( rtx reg1 , rtx reg2 ) { if ( GET_CODE ( reg1 ) != REG || GET_CODE ( reg2 ) != REG ) return 0 ; if ( ! FP_REGNO_P ( REGNO ( reg1 ) ) || ! FP_REGNO_P ( REGNO ( reg2 ) ) ) return 0 ; return ( REGNO ( reg1 ) == REGNO ( reg2 ) - 1 ) ; } </s>

Return 1 if REGNO ( reg1 ) == REGNO ( reg2 ) - 1 making them candidates for lfq and stfq insns . Note reg1 and reg2 * must * be hard registers . To be sure we will abort if we are passed pseudo registers .


"Slot for FPW register must be last in order to be found!"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> bool SIInstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( MI . isTerminator ( ) || MI . isPosition ( ) ) return true ; if ( MI . getOpcode ( ) == TargetOpcode :: INLINEASM_BR ) return true ; return MI . modifiesRegister ( AMDGPU :: EXEC , & RI ) || MI . getOpcode ( ) == AMDGPU :: S_SETREG_IMM32_B32 || MI . getOpcode ( ) == AMDGPU :: S_SETREG_B32 || changesVGPRIndexingMode ( MI ) ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> static bool ia64_return_in_memory ( const_tree valtype , const_tree fntype ATTRIBUTE_UNUSED ) { machine_mode mode ; machine_mode hfa_mode ; HOST_WIDE_INT byte_size ; mode = TYPE_MODE ( valtype ) ; byte_size = GET_MODE_SIZE ( mode ) ; if ( mode == BLKmode ) { byte_size = int_size_in_bytes ( valtype ) ; if ( byte_size < 0 ) return true ; } hfa_mode = hfa_element_mode ( valtype , 0 ) ; if ( hfa_mode != VOIDmode ) { int hfa_size = GET_MODE_SIZE ( hfa_mode ) ; if ( byte_size / hfa_size > MAX_ARGUMENT_SLOTS ) return true ; else return false ; } else if ( byte_size > UNITS_PER_WORD * MAX_INT_RETURN_SLOTS ) return true ; else return false ; } </s>

Return 1 if function return value returned in memory . Return 0 if it is in a register .


<s> SUnit * pickNode ( bool & IsTopNode ) override { return nullptr ; } </s>

Pick the next node to schedule , or return NULL .


<s> int SystemZHazardRecognizer :: groupingCost ( SUnit * SU ) const { const MCSchedClassDesc * SC = getSchedClass ( SU ) ; if ( ! SC -> isValid ( ) ) return 0 ; if ( SC -> BeginGroup ) { if ( CurrGroupSize ) return 3 - CurrGroupSize ; return - 1 ; } if ( SC -> EndGroup ) { unsigned resultingGroupSize = ( CurrGroupSize + getNumDecoderSlots ( SU ) ) ; if ( resultingGroupSize < 3 ) return ( 3 - resultingGroupSize ) ; return - 1 ; } if ( CurrGroupSize == 2 && has4RegOps ( SU -> getInstr ( ) ) ) return 1 ; return 0 ; } </s>

Return the cost of decoder grouping for SU .


<s> bool X86FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned CalleeSavedFrameSize = 0 ; int SpillSlotOffset = getOffsetOfLocalArea ( ) + X86FI -> getTCReturnAddrDelta ( ) ; int64_t TailCallReturnAddrDelta = X86FI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < 0 ) { MFI . CreateFixedObject ( - TailCallReturnAddrDelta , TailCallReturnAddrDelta - SlotSize , true ) ; } if ( this -> TRI -> hasBasePointer ( MF ) ) { if ( MF . hasEHFunclets ( ) ) { int FI = MFI . CreateSpillStackObject ( SlotSize , SlotSize ) ; X86FI -> setHasSEHFramePtrSave ( true ) ; X86FI -> setSEHFramePtrSaveIndex ( FI ) ; } } if ( hasFP ( MF ) ) { SpillSlotOffset -= SlotSize ; MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; unsigned FPReg = TRI -> getFrameRegister ( MF ) ; for ( unsigned i = 0 ; i < CSI . size ( ) ; ++ i ) { if ( TRI -> regsOverlap ( CSI [ i ] . getReg ( ) , FPReg ) ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - 1 ] . setFrameIdx ( SlotIndex ) ; } X86FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; unsigned Size = TRI -> getSpillSize ( * RC ) ; unsigned Align = TRI -> getSpillAlignment ( * RC ) ; SpillSlotOffset -= std :: abs ( SpillSlotOffset ) % Align ; SpillSlotOffset -= Size ; int SlotIndex = MFI . CreateFixedSpillStackObject ( Size , SpillSlotOffset ) ; CSI [ i - 1 ] . setFrameIdx ( SlotIndex ) ; MFI . ensureMaxAlignment ( Align ) ; } return true ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> const MCPhysReg * AGCRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_SaveList ; } </s>


<s> int cr16_const_double_ok ( rtx op ) { if ( GET_MODE ( op ) == SFmode ) { REAL_VALUE_TYPE r ; long l ; REAL_VALUE_FROM_CONST_DOUBLE ( r , op ) ; REAL_VALUE_TO_TARGET_SINGLE ( r , l ) ; return UNSIGNED_INT_FITS_N_BITS ( l , 4 ) ? 1 : 0 ; } return ( ( UNSIGNED_INT_FITS_N_BITS ( CONST_DOUBLE_LOW ( op ) , 4 ) ) && ( UNSIGNED_INT_FITS_N_BITS ( CONST_DOUBLE_HIGH ( op ) , 4 ) ) ) ? 1 : 0 ; } </s>

Check if a const_double is ok for cr16 store-immediate instructions .


<s> bool CheckReturn ( const SmallVectorImpl < ISD :: OutputArg > & ArgsFlags , CCAssignFn Fn ) { PreAnalyzeReturnForF128 ( ArgsFlags ) ; bool Return = CCState :: CheckReturn ( ArgsFlags , Fn ) ; OriginalArgWasF128 . clear ( ) ; return Return ; } </s>

CheckReturn - Analyze the return values of a function , returning true if the return can be performed without sret-demotion , and false otherwise .


<s> static std :: string getEdgeAttributes ( const MCGNode * N , GraphTraits < MCallSubGraph > :: ChildIteratorType ci , const MCallSubGraph & G ) { return ci . getSite ( ) -> isInSCC ( ) ? "style=\"bold\"" : "" ; } </s>

If you want to override the dot attributes printed for a particular edge , override this method .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override { TargetTransformInfo :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool isToken ( ) const override { return Kind == KindTy :: Token ; } </s>


<s>
void
NVPTXTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
switch
(
N
->
getOpcode
(
)
)
{
default
:
report_fatal_error
(
"Unhandled custom legalization"
)
;
case
ISD
::
LOAD
:
ReplaceLoadVector
(
N
,
DAG
,
getDataLayout
(
)
,
Results
)
;
return
;
case
ISD
::
INTRINSIC_W_CHAIN
:
ReplaceINTRINSIC_W_CHAIN
(
N
,
DAG
,
Results
)
;
return
;
}
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

NVPTX
NVPTX
"Unhandled custom legalization"
ISD::LOAD
ISD::INTRINSIC_W_CHAIN


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( ARM :: GPRRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( ARM :: t2LDRi12 ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; return ; } if ( ARM :: GPRPairRegClass . hasSubClassEq ( RC ) ) { if ( Register :: isVirtualRegister ( DestReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( DestReg , & ARM :: GPRPairnospRegClass ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( ARM :: t2LDRDi8 ) ) ; AddDReg ( MIB , DestReg , ARM :: gsub_0 , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , ARM :: gsub_1 , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; if ( Register :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; } ARMBaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC , TRI ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return createAArch64ELFObjectWriter ( OS , OSABI , IsLittleEndian ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> virtual const InstrItineraryData getInstrItineraryData ( ) const { return InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s>
void
HexagonAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
MCInst
MCB
;
MCB
.
setOpcode
(
Hexagon
::
BUNDLE
)
;
MCB
.
addOperand
(
MCOperand
::
createImm
(
0
)
)
;
const
MCInstrInfo
&
MCII
=
*
Subtarget
->
getInstrInfo
(
)
;
if
(
MI
->
isBundle
(
)
)
{
assert
(
Subtarget
->
usePackets
(
)
&&
"Support for packets is disabled"
)
;
const
MachineBasicBlock
*
MBB
=
MI
->
getParent
(
)
;
MachineBasicBlock
::
const_instr_iterator
MII
=
MI
->
getIterator
(
)
;
for
(
++
MII
;
MII
!=
MBB
->
instr_end
(
)
&&
MII
->
isInsideBundle
(
)
;
++
MII
)
if
(
!
MII
->
isDebugValue
(
)
&&
!
MII
->
isImplicitDef
(
)
)
HexagonLowerToMC
(
MCII
,
&
*
MII
,
MCB
,
*
this
)
;
}
else
HexagonLowerToMC
(
MCII
,
MI
,
MCB
,
*
this
)
;
bool
Ok
=
HexagonMCInstrInfo
::
canonicalizePacket
(
MCII
,
*
Subtarget
,
OutStreamer
->
getContext
(
)
,
MCB
,
nullptr
)
;
assert
(
Ok
)
;
(
void
)
Ok
;
if
(
HexagonMCInstrInfo
::
bundleSize
(
MCB
)
==
0
)
return
;
OutStreamer
->
EmitInstruction
(
MCB
,
getSubtargetInfo
(
)
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .

Hexagon
Hexagon
Hexagon::BUNDLE
0
"Support for packets is disabled"
Hexagon
Hexagon
Hexagon
Hexagon
0


<s> void LanaiTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { unsigned BitWidth = Known . getBitWidth ( ) ; switch ( Op . getOpcode ( ) ) { default : break ; case LanaiISD :: SETCC : Known = KnownBits ( BitWidth ) ; Known . Zero . setBits ( 1 , BitWidth ) ; break ; case LanaiISD :: SELECT_CC : KnownBits Known2 ; DAG . computeKnownBits ( Op -> getOperand ( 0 ) , Known , Depth + 1 ) ; DAG . computeKnownBits ( Op -> getOperand ( 1 ) , Known2 , Depth + 1 ) ; Known . Zero &= Known2 . Zero ; Known . One &= Known2 . One ; break ; } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


"Should use capability adjustments if and only if ABI is purecap"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> virtual bool addPassesToEmitMC ( PassManagerBase & , MCContext * & , raw_ostream & , bool = true ) { return true ; } </s>

Add passes to the specified pass manager to get machine code emitted with the MCJIT .


<s> static void mips_emit_unary ( enum rtx_code code , rtx target , rtx op0 ) { emit_insn ( gen_rtx_SET ( target , gen_rtx_fmt_e ( code , GET_MODE ( op0 ) , op0 ) ) ) ; } </s>

Emit an instruction of the form ( set TARGET ( CODE OP0 ) ) .


<s> unsigned M88kInstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { if ( BytesRemoved ) * BytesRemoved = 0 ; MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return 0 ; if ( ! I -> getDesc ( ) . isUnconditionalBranch ( ) && ! I -> getDesc ( ) . isConditionalBranch ( ) ) return 0 ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return 1 ; -- I ; if ( ! I -> getDesc ( ) . isConditionalBranch ( ) ) return 1 ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ; return 2 ; } </s>

Remove the branching code at the end of the specific MBB .


<s> bool AMDGPUCodeGenPrepare :: doInitialization ( Module & M ) { Mod = & M ; DL = & Mod -> getDataLayout ( ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s>
MachineBasicBlock
::
iterator
AArch64InstrInfo
::
insertOutlinedCall
(
Module
&
M
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
&
It
,
MachineFunction
&
MF
,
outliner
::
Candidate
&
C
)
const
{
if
(
C
.
CallConstructionID
==
MachineOutlinerTailCall
)
{
It
=
MBB
.
insert
(
It
,
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
TCRETURNdi
)
)
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
.
addImm
(
0
)
)
;
return
It
;
}
if
(
C
.
CallConstructionID
==
MachineOutlinerNoLRSave
||
C
.
CallConstructionID
==
MachineOutlinerThunk
)
{
It
=
MBB
.
insert
(
It
,
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
BL
)
)
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
)
;
return
It
;
}
MachineBasicBlock
::
iterator
CallPt
;
MachineInstr
*
Save
;
MachineInstr
*
Restore
;
if
(
C
.
CallConstructionID
==
MachineOutlinerRegSave
)
{
Register
Reg
=
findRegisterToSaveLRTo
(
C
)
;
assert
(
Reg
&&
"No callee-saved register available?"
)
;
if
(
!
MBB
.
isLiveIn
(
AArch64
::
LR
)
)
MBB
.
addLiveIn
(
AArch64
::
LR
)
;
Save
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
ORRXrs
)
,
Reg
)
.
addReg
(
AArch64
::
XZR
)
.
addReg
(
AArch64
::
LR
)
.
addImm
(
0
)
;
Restore
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
ORRXrs
)
,
AArch64
::
LR
)
.
addReg
(
AArch64
::
XZR
)
.
addReg
(
Reg
)
.
addImm
(
0
)
;
}
else
{
Save
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
STRXpre
)
)
.
addReg
(
AArch64
::
SP
,
RegState
::
Define
)
.
addReg
(
AArch64
::
LR
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
16
)
;
Restore
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
LDRXpost
)
)
.
addReg
(
AArch64
::
SP
,
RegState
::
Define
)
.
addReg
(
AArch64
::
LR
,
RegState
::
Define
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
16
)
;
}
It
=
MBB
.
insert
(
It
,
Save
)
;
It
++
;
It
=
MBB
.
insert
(
It
,
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
BL
)
)
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
)
;
CallPt
=
It
;
It
++
;
It
=
MBB
.
insert
(
It
,
Restore
)
;
return
CallPt
;
}
</s>

Insert a call to an outlined function into the program .


<s> void pass_vsetvl :: refine_vsetvls ( void ) const { basic_block cfg_bb ; FOR_EACH_BB_FN ( cfg_bb , cfun ) { auto info = m_vector_manager -> vector_block_infos [ cfg_bb -> index ] . local_dem ; insn_info * insn = info . get_insn ( ) ; if ( ! info . valid_p ( ) ) continue ; rtx_insn * rinsn = insn -> rtl ( ) ; if ( ! can_refine_vsetvl_p ( cfg_bb , info ) ) continue ; if ( vector_config_insn_p ( rinsn ) ) { m_vector_manager -> to_refine_vsetvls . add ( rinsn ) ; continue ; } rinsn = PREV_INSN ( rinsn ) ; rtx new_pat = gen_vsetvl_pat ( VSETVL_VTYPE_CHANGE_ONLY , info , NULL_RTX ) ; change_insn ( rinsn , new_pat ) ; } } </s>

Optimize athe case like this : bb 0 : vsetvl 0 a5 , zero , e8 , mf8 insn 0 ( demand SEW + LMUL ) bb 1 : vsetvl 1 a5 , zero , e16 , mf4 insn 1 ( demand SEW + LMUL ) In this case , we should be able to refine vsetvl 1 into vsetvl zero , zero according AVIN .


<s> void addSuccessor ( const PredicatedBlock * block , unsigned pred ) { Successors . insert ( std :: make_pair ( block , pred ) ) ; } </s>

Add Succ as a successor of this MachineBasicBlock .


<s> bool Thumb1FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; bool isVarArg = AFI -> getArgRegsSaveSize ( ) > 0 ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , TII . get ( ARM :: tPOP ) ) ; AddDefaultPred ( MIB ) ; bool NumRegs = false ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( Reg == ARM :: LR ) { if ( isVarArg ) continue ; if ( STI . hasV4TOps ( ) && ! STI . hasV5TOps ( ) ) continue ; Reg = ARM :: PC ; ( * MIB ) . setDesc ( TII . get ( ARM :: tPOP_RET ) ) ; MIB . copyImplicitOps ( & * MI ) ; MI = MBB . erase ( MI ) ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; NumRegs = true ; } if ( NumRegs ) MBB . insert ( MI , & * MIB ) ; else MF . DeleteMachineInstr ( MIB ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static rtx paired_expand_builtin ( tree exp , rtx target , bool * expandedp ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , 0 ) ; enum rs6000_builtins fcode = ( enum rs6000_builtins ) DECL_FUNCTION_CODE ( fndecl ) ; const struct builtin_description * d ; size_t i ; * expandedp = true ; switch ( fcode ) { case PAIRED_BUILTIN_STX : return paired_expand_stv_builtin ( CODE_FOR_paired_stx , exp ) ; case PAIRED_BUILTIN_LX : return paired_expand_lv_builtin ( CODE_FOR_paired_lx , exp , target ) ; default : break ; } d = bdesc_paired_preds ; for ( i = 0 ; i < ARRAY_SIZE ( bdesc_paired_preds ) ; i ++ , d ++ ) if ( d -> code == fcode ) return paired_expand_predicate_builtin ( d -> icode , exp , target ) ; * expandedp = false ; return NULL_RTX ; } </s>

Expand the builtin in EXP and store the result in TARGET . Store true in * EXPANDEDP if we found a builtin to expand .


<s> static rtx altivec_expand_vec_ext_builtin ( tree arglist , rtx target ) { enum machine_mode tmode , mode0 ; tree arg0 , arg1 ; int elt ; rtx op0 ; arg0 = TREE_VALUE ( arglist ) ; arg1 = TREE_VALUE ( TREE_CHAIN ( arglist ) ) ; op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , 0 ) ; elt = get_element_number ( TREE_TYPE ( arg0 ) , arg1 ) ; tmode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( arg0 ) ) ) ; mode0 = TYPE_MODE ( TREE_TYPE ( arg0 ) ) ; gcc_assert ( VECTOR_MODE_P ( mode0 ) ) ; op0 = force_reg ( mode0 , op0 ) ; if ( optimize || ! target || ! register_operand ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; rs6000_expand_vector_extract ( target , op0 , elt ) ; return target ; } </s>


<s> const char * PPCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case PPCISD :: FSEL : return "PPCISD::FSEL" ; case PPCISD :: FCFID : return "PPCISD::FCFID" ; case PPCISD :: FCTIDZ : return "PPCISD::FCTIDZ" ; case PPCISD :: FCTIWZ : return "PPCISD::FCTIWZ" ; case PPCISD :: FRE : return "PPCISD::FRE" ; case PPCISD :: FRSQRTE : return "PPCISD::FRSQRTE" ; case PPCISD :: STFIWX : return "PPCISD::STFIWX" ; case PPCISD :: VMADDFP : return "PPCISD::VMADDFP" ; case PPCISD :: VNMSUBFP : return "PPCISD::VNMSUBFP" ; case PPCISD :: VPERM : return "PPCISD::VPERM" ; case PPCISD :: Hi : return "PPCISD::Hi" ; case PPCISD :: Lo : return "PPCISD::Lo" ; case PPCISD :: TOC_ENTRY : return "PPCISD::TOC_ENTRY" ; case PPCISD :: TOC_RESTORE : return "PPCISD::TOC_RESTORE" ; case PPCISD :: LOAD : return "PPCISD::LOAD" ; case PPCISD :: LOAD_TOC : return "PPCISD::LOAD_TOC" ; case PPCISD :: DYNALLOC : return "PPCISD::DYNALLOC" ; case PPCISD :: GlobalBaseReg : return "PPCISD::GlobalBaseReg" ; case PPCISD :: SRL : return "PPCISD::SRL" ; case PPCISD :: SRA : return "PPCISD::SRA" ; case PPCISD :: SHL : return "PPCISD::SHL" ; case PPCISD :: CALL : return "PPCISD::CALL" ; case PPCISD :: CALL_NOP : return "PPCISD::CALL_NOP" ; case PPCISD :: MTCTR : return "PPCISD::MTCTR" ; case PPCISD :: BCTRL : return "PPCISD::BCTRL" ; case PPCISD :: RET_FLAG : return "PPCISD::RET_FLAG" ; case PPCISD :: EH_SJLJ_SETJMP : return "PPCISD::EH_SJLJ_SETJMP" ; case PPCISD :: EH_SJLJ_LONGJMP : return "PPCISD::EH_SJLJ_LONGJMP" ; case PPCISD :: MFOCRF : return "PPCISD::MFOCRF" ; case PPCISD :: VCMP : return "PPCISD::VCMP" ; case PPCISD :: VCMPo : return "PPCISD::VCMPo" ; case PPCISD :: LBRX : return "PPCISD::LBRX" ; case PPCISD :: STBRX : return "PPCISD::STBRX" ; case PPCISD :: LARX : return "PPCISD::LARX" ; case PPCISD :: STCX : return "PPCISD::STCX" ; case PPCISD :: COND_BRANCH : return "PPCISD::COND_BRANCH" ; case PPCISD :: BDNZ : return "PPCISD::BDNZ" ; case PPCISD :: BDZ : return "PPCISD::BDZ" ; case PPCISD :: MFFS : return "PPCISD::MFFS" ; case PPCISD :: FADDRTZ : return "PPCISD::FADDRTZ" ; case PPCISD :: TC_RETURN : return "PPCISD::TC_RETURN" ; case PPCISD :: CR6SET : return "PPCISD::CR6SET" ; case PPCISD :: CR6UNSET : return "PPCISD::CR6UNSET" ; case PPCISD :: ADDIS_TOC_HA : return "PPCISD::ADDIS_TOC_HA" ; case PPCISD :: LD_TOC_L : return "PPCISD::LD_TOC_L" ; case PPCISD :: ADDI_TOC_L : return "PPCISD::ADDI_TOC_L" ; case PPCISD :: PPC32_GOT : return "PPCISD::PPC32_GOT" ; case PPCISD :: ADDIS_GOT_TPREL_HA : return "PPCISD::ADDIS_GOT_TPREL_HA" ; case PPCISD :: LD_GOT_TPREL_L : return "PPCISD::LD_GOT_TPREL_L" ; case PPCISD :: ADD_TLS : return "PPCISD::ADD_TLS" ; case PPCISD :: ADDIS_TLSGD_HA : return "PPCISD::ADDIS_TLSGD_HA" ; case PPCISD :: ADDI_TLSGD_L : return "PPCISD::ADDI_TLSGD_L" ; case PPCISD :: GET_TLS_ADDR : return "PPCISD::GET_TLS_ADDR" ; case PPCISD :: ADDIS_TLSLD_HA : return "PPCISD::ADDIS_TLSLD_HA" ; case PPCISD :: ADDI_TLSLD_L : return "PPCISD::ADDI_TLSLD_L" ; case PPCISD :: GET_TLSLD_ADDR : return "PPCISD::GET_TLSLD_ADDR" ; case PPCISD :: ADDIS_DTPREL_HA : return "PPCISD::ADDIS_DTPREL_HA" ; case PPCISD :: ADDI_DTPREL_L : return "PPCISD::ADDI_DTPREL_L" ; case PPCISD :: VADD_SPLAT : return "PPCISD::VADD_SPLAT" ; case PPCISD :: SC : return "PPCISD::SC" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


"Running spec function '%s' with %d args\n\n"

"strange device name %qs after %qs: bad character %qc"

Implement spec function ` device-specs-file麓 . Compose -specs= < specs-file-name > % s . If everything went well then argv [ 0 ] is the inflated ( absolute ) specs directory and argv [ 1 ] is a device or core name as supplied by -mmcu= * . When building GCC the path might be relative .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> int ia64_direct_return ( void ) { if ( reload_completed && ! frame_pointer_needed ) { ia64_compute_frame_size ( get_frame_size ( ) ) ; return ( current_frame_info . total_size == 0 && current_frame_info . n_spilled == 0 && current_frame_info . r [ reg_save_b0 ] == 0 && current_frame_info . r [ reg_save_pr ] == 0 && current_frame_info . r [ reg_save_ar_pfs ] == 0 && current_frame_info . r [ reg_save_ar_unat ] == 0 && current_frame_info . r [ reg_save_ar_lc ] == 0 ) ; } return 0 ; } </s>

Return 1 if br.ret can do all the work required to return from a function .


<s> static pad_direction rs6000_function_arg_padding ( machine_mode mode , const_tree type ) { if ( ! AGGREGATE_PADDING_FIXED ) { if ( BYTES_BIG_ENDIAN ) { HOST_WIDE_INT size = 0 ; if ( mode == BLKmode ) { if ( type && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST ) size = int_size_in_bytes ( type ) ; } else size = GET_MODE_SIZE ( mode ) ; if ( size == 1 || size == 2 || size == 4 ) return PAD_DOWNWARD ; } return PAD_UPWARD ; } if ( AGGREGATES_PAD_UPWARD_ALWAYS ) { if ( type != 0 && AGGREGATE_TYPE_P ( type ) ) return PAD_UPWARD ; } return default_function_arg_padding ( mode , type ) ; } </s>

Implement TARGET_FUNCTION_ARG_PADDING . For the AIX ABI structs are always stored left shifted in their argument slot .


<s> MachineInstrBuilder SIInstrInfo :: buildIndirectRead ( MachineBasicBlock * MBB , MachineBasicBlock :: iterator I , unsigned ValueReg , unsigned Address , unsigned OffsetReg ) const { const DebugLoc & DL = MBB -> findDebugLoc ( I ) ; unsigned IndirectBaseReg = AMDGPU :: VGPR_32RegClass . getRegister ( getIndirectIndexBegin ( * MBB -> getParent ( ) ) ) ; return BuildMI ( * MBB , I , DL , get ( AMDGPU :: SI_INDIRECT_SRC ) ) . addOperand ( I -> getOperand ( 0 ) ) . addOperand ( I -> getOperand ( 1 ) ) . addReg ( IndirectBaseReg ) . addReg ( OffsetReg ) . addImm ( 0 ) ; } </s>

Build instruction ( s ) for an indirect register read .


<s> StringRef MetadataStreamerV3 :: getValueType ( Type * Ty , StringRef TypeName ) const { switch ( Ty -> getTypeID ( ) ) { case Type :: IntegerTyID : { auto Signed = ! TypeName . startswith ( "u" ) ; switch ( Ty -> getIntegerBitWidth ( ) ) { case 8 : return Signed ? "i8" : "u8" ; case 16 : return Signed ? "i16" : "u16" ; case 32 : return Signed ? "i32" : "u32" ; case 64 : return Signed ? "i64" : "u64" ; default : return "struct" ; } } case Type :: HalfTyID : return "f16" ; case Type :: FloatTyID : return "f32" ; case Type :: DoubleTyID : return "f64" ; case Type :: PointerTyID : return getValueType ( Ty -> getPointerElementType ( ) , TypeName ) ; case Type :: FixedVectorTyID : return getValueType ( cast < VectorType > ( Ty ) -> getElementType ( ) , TypeName ) ; default : return "struct" ; } } </s>

Return the ValueType of the referenced return value .


<s> TargetPassConfig * X86TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new X86PassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> void AlphaInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { DebugLoc DL ; BuildMI ( MBB , MI , DL , get ( Alpha :: BISr ) , Alpha :: R31 ) . addReg ( Alpha :: R31 ) . addReg ( Alpha :: R31 ) ; } </s>

Insert a noop into the instruction stream at the specified point .


<s> void X86LinuxNaClTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; } </s>

This method must be called before any actual lowering is done .


<s> unsigned SNESInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { case SNES :: LDDRdPtrQ : case SNES :: LDDWRdYQ : { if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } default : break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , JIT , TT . getArch ( ) == Triple :: x86_64 ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) { if ( ( TT . isOSWindows ( ) && TT . getArch ( ) == Triple :: x86_64 ) || TT . isPS4 ( ) ) this -> Options . TrapUnreachable = true ; initAsmInfo ( ) ; } </s>


<s> rtx s390_gen_rtx_const_DI ( int high , int low ) { HOST_WIDE_INT val ; val = ( HOST_WIDE_INT ) high ; val <<= 32 ; val |= ( HOST_WIDE_INT ) low ; return GEN_INT ( val ) ; return immed_double_const ( ( HOST_WIDE_INT ) low , ( HOST_WIDE_INT ) high , DImode ) ; gcc_unreachable ( ) ; } </s>

Return rtx for 64-bit constant formed from the 32-bit subwords LOW and HIGH , independent of the host word size .


<s> bool AVRInstrumentFunctions :: runOnFunction ( Function & F ) { if ( ShouldInstrument ( F ) ) { BuildEntryBlock ( F ) ; BuildExitHooks ( F ) ; } return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> const uint32_t * FISCRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { return CC_Save_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool X86TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( VT . getSizeInBits ( ) == 64 ) return false ; return ( VT . getVectorNumElements ( ) == 2 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isMOVLMask ( M , VT ) || isSHUFPMask ( M , VT , Subtarget -> hasAVX ( ) ) || isPSHUFDMask ( M , VT ) || isPSHUFHWMask ( M , VT ) || isPSHUFLWMask ( M , VT ) || isPALIGNRMask ( M , VT , Subtarget ) || isUNPCKLMask ( M , VT , Subtarget -> hasAVX2 ( ) ) || isUNPCKHMask ( M , VT , Subtarget -> hasAVX2 ( ) ) || isUNPCKL_v_undef_Mask ( M , VT , Subtarget -> hasAVX2 ( ) ) || isUNPCKH_v_undef_Mask ( M , VT , Subtarget -> hasAVX2 ( ) ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> static bool div_sqrt_insn_p ( rtx_insn * insn ) { if ( GET_CODE ( PATTERN ( insn ) ) != SET ) return false ; switch ( get_attr_type ( insn ) ) { case TYPE_FPDIVS : case TYPE_FPSQRTS : case TYPE_FPDIVD : case TYPE_FPSQRTD : return true ; default : return false ; } } </s>

True if INSN is a floating-point division or square-root .


<s>
OperandMatchResultTy
tryParseRegister
(
unsigned
&
,
SMLoc
&
,
SMLoc
&
)
override
{
llvm_unreachable
(
"tryParseRegister is not implemented."
)
;
}
</s>

tryParseRegister - parse one register if possible

WebAssembly
"tryParseRegister is not implemented."


<s>
unsigned
VEInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
!
isUncondBranchOpcode
(
I
->
getOpcode
(
)
)
&&
!
isCondBranchOpcode
(
I
->
getOpcode
(
)
)
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s> bool shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const override { return true ; } </s>

Returns true if it is beneficial to convert a load of a constant to just the constant itself .


<s> bool AArch64TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { return getTargetMachine ( ) . getOptLevel ( ) != 0 ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> static void tryAddingPcLoadReferenceComment ( uint64_t Address , int Value , const void * Decoder ) { const MCDisassembler * Dis = static_cast < const MCDisassembler * > ( Decoder ) ; Dis -> tryAddingPcLoadReferenceComment ( Value , Address ) ; } </s>

Try to add a comment on the PC-relative load .


<s> MCRegister SIRegisterInfo :: reservedPrivateSegmentBufferReg ( const MachineFunction & MF ) const { unsigned BaseIdx = alignDown ( ST . getMaxNumSGPRs ( MF ) , 4 ) - 4 ; MCRegister BaseReg ( AMDGPU :: SGPR_32RegClass . getRegister ( BaseIdx ) ) ; return getMatchingSuperReg ( BaseReg , AMDGPU :: sub0 , & AMDGPU :: SGPR_128RegClass ) ; } </s>

Return the end register initially reserved for the scratch buffer in case spilling is needed .


<s>
static
void
mmix_option_override
(
void
)
{
if
(
flag_pic
)
{
warning
(
0
,
"-f%s not supported: ignored"
,
(
flag_pic
>
1
)
"PIC"
:
"pic"
)
;
flag_pic
=
0
;
}
}
</s>


<s> unsigned int UPTInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { return TargetInstrInfo :: isLoadFromStackSlot ( MI , FrameIndex ) ; } </s>


<s> static bool ix86_legitimate_constant_p ( machine_mode mode , rtx x ) { if ( POINTER_BOUNDS_MODE_P ( GET_MODE ( x ) ) ) return false ; switch ( GET_CODE ( x ) ) { case CONST : x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == PLUS ) { if ( ! CONST_INT_P ( XEXP ( x , 1 ) ) ) return false ; x = XEXP ( x , 0 ) ; } if ( TARGET_MACHO && darwin_local_data_pic ( x ) ) return true ; if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , 1 ) ) { case UNSPEC_GOT : case UNSPEC_GOTOFF : case UNSPEC_PLTOFF : return TARGET_64BIT ; case UNSPEC_TPOFF : case UNSPEC_NTPOFF : x = XVECEXP ( x , 0 , 0 ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_EXEC ) ; case UNSPEC_DTPOFF : x = XVECEXP ( x , 0 , 0 ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_DYNAMIC ) ; default : return false ; } if ( GET_CODE ( x ) == LABEL_REF ) return true ; if ( GET_CODE ( x ) != SYMBOL_REF ) return false ; case SYMBOL_REF : if ( SYMBOL_REF_TLS_MODEL ( x ) ) return false ; if ( TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P ( x ) ) return false ; if ( MACHO_DYNAMIC_NO_PIC_P ) return machopic_symbol_defined_p ( x ) ; if ( ix86_force_load_from_GOT_p ( x ) ) return false ; break ; CASE_CONST_SCALAR_INT : switch ( mode ) { case E_TImode : if ( TARGET_64BIT ) return true ; case E_OImode : case E_XImode : if ( ! standard_sse_constant_p ( x , mode ) ) return false ; default : break ; } break ; case CONST_VECTOR : if ( ! standard_sse_constant_p ( x , mode ) ) return false ; default : break ; } return true ; } </s>

Determine if a given RTX is a valid constant . We already know this satisfies CONSTANT_P .


<s> static void nds32_emit_stack_v3push ( rtx Rb , rtx Re , rtx En4 ATTRIBUTE_UNUSED , rtx imm8u ) { int regno ; int num_use_regs ; int par_index ; int offset ; rtx reg ; rtx mem ; rtx push_rtx ; rtx adjust_sp_rtx ; rtx parallel_insn ; num_use_regs = REGNO ( Re ) - REGNO ( Rb ) + 1 + 3 ; parallel_insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_use_regs + 1 ) ) ; par_index = 0 ; offset = - ( num_use_regs * 4 ) ; for ( regno = REGNO ( Rb ) ; regno <= ( int ) REGNO ( Re ) ; regno ++ ) { reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( mem , reg ) ; XVECEXP ( parallel_insn , 0 , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; } reg = gen_rtx_REG ( SImode , FP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( mem , reg ) ; XVECEXP ( parallel_insn , 0 , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; reg = gen_rtx_REG ( SImode , GP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( mem , reg ) ; XVECEXP ( parallel_insn , 0 , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; reg = gen_rtx_REG ( SImode , LP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( mem , reg ) ; XVECEXP ( parallel_insn , 0 , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; offset = - ( num_use_regs * 4 ) ; adjust_sp_rtx = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , offset - INTVAL ( imm8u ) ) ) ; XVECEXP ( parallel_insn , 0 , par_index ) = adjust_sp_rtx ; RTX_FRAME_RELATED_P ( adjust_sp_rtx ) = 1 ; parallel_insn = emit_insn ( parallel_insn ) ; RTX_FRAME_RELATED_P ( parallel_insn ) = 1 ; } </s>

Function to create a parallel rtx pattern which presents stack v3push behavior . The overall concept are : `` push registers to memory '' , `` adjust stack pointer '' .


<s> BitVector M88kRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( M88k :: R0 ) ; Reserved . set ( M88k :: R28 ) ; Reserved . set ( M88k :: R29 ) ; Reserved . set ( M88k :: R31 ) ; if ( getFrameLowering ( MF ) -> hasFP ( MF ) ) Reserved . set ( M88k :: R30 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool AMDGPUTargetLowering :: shouldReduceLoadWidth ( SDNode * N , ISD :: LoadExtType ExtTy , EVT NewVT ) const { if ( ! TargetLoweringBase :: shouldReduceLoadWidth ( N , ExtTy , NewVT ) ) return false ; unsigned NewSize = NewVT . getStoreSizeInBits ( ) ; if ( NewSize >= 32 ) return true ; EVT OldVT = N -> getValueType ( 0 ) ; unsigned OldSize = OldVT . getStoreSizeInBits ( ) ; MemSDNode * MN = cast < MemSDNode > ( N ) ; unsigned AS = MN -> getAddressSpace ( ) ; if ( OldSize >= 32 && NewSize < 32 && MN -> getAlignment ( ) >= 4 && ( AS == AMDGPUAS :: CONSTANT_ADDRESS || AS == AMDGPUAS :: CONSTANT_ADDRESS_32BIT || ( isa < LoadSDNode > ( N ) && AS == AMDGPUAS :: GLOBAL_ADDRESS && MN -> isInvariant ( ) ) ) && AMDGPUInstrInfo :: isUniformMMO ( MN -> getMemOperand ( ) ) ) return false ; return ( OldSize < 32 ) ; } </s>

Return true if we believe it is correct and profitable to reduce the load node to a smaller type .


<s> static void rs6000_setup_reg_addr_masks ( void ) { ssize_t rc , reg , m , nregs ; addr_mask_type any_addr_mask , addr_mask ; for ( m = 0 ; m < NUM_MACHINE_MODES ; ++ m ) { machine_mode m2 = ( machine_mode ) m ; bool indexed_only_p = ( m == SDmode && TARGET_NO_SDMODE_STACK ) ; any_addr_mask = 0 ; for ( rc = FIRST_RELOAD_REG_CLASS ; rc <= LAST_RELOAD_REG_CLASS ; rc ++ ) { addr_mask = 0 ; reg = reload_reg_map [ rc ] . reg ; if ( reg >= 0 && rs6000_hard_regno_mode_ok_p [ m ] [ reg ] ) { nregs = rs6000_hard_regno_nregs [ m ] [ reg ] ; addr_mask |= RELOAD_REG_VALID ; if ( nregs > 1 || m == BLKmode ) addr_mask |= RELOAD_REG_MULTIPLE ; else addr_mask |= RELOAD_REG_INDEXED ; if ( TARGET_UPDATE && ( rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR ) && GET_MODE_SIZE ( m2 ) <= 8 && ! VECTOR_MODE_P ( m2 ) && ! COMPLEX_MODE_P ( m2 ) && ! indexed_only_p && ! ( TARGET_E500_DOUBLE && GET_MODE_SIZE ( m2 ) == 8 ) ) { addr_mask |= RELOAD_REG_PRE_INCDEC ; switch ( m ) { default : addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; case DImode : if ( TARGET_POWERPC64 ) addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; case DFmode : case DDmode : if ( TARGET_DF_INSN ) addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; } } } if ( ( addr_mask != 0 ) && ! indexed_only_p && ( rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR ) ) addr_mask |= RELOAD_REG_OFFSET ; if ( rc == RELOAD_REG_VMX && GET_MODE_SIZE ( m2 ) == 16 && ( addr_mask & RELOAD_REG_VALID ) != 0 ) addr_mask |= RELOAD_REG_AND_M16 ; reg_addr [ m ] . addr_mask [ rc ] = addr_mask ; any_addr_mask |= addr_mask ; } reg_addr [ m ] . addr_mask [ RELOAD_REG_ANY ] = any_addr_mask ; } } </s>

Update the addr mask bits in reg_addr to help secondary reload and go if legitimate address support to figure out the appropriate addressing to use .


"%<-fstack-check=specific%> not implemented for MIPS16"

Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE , inclusive . These are offsets from the current stack pointer .


<s> std :: pair < unsigned , unsigned > RISCVInstrInfo :: decomposeMachineOperandsTargetFlags ( unsigned TF ) const { const unsigned Mask = RISCVII :: MO_DIRECT_FLAG_MASK ; return std :: make_pair ( TF & Mask , TF & ~ Mask ) ; } </s>

Decompose the machine operand 's target flags into two values - the direct target flag value and any of bit flags that are applied .


<s> static void arc_setup_incoming_varargs ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type ATTRIBUTE_UNUSED , int * pretend_size , int no_rtl ) { int first_anon_arg ; gcc_assert ( mode != BLKmode ) ; first_anon_arg = * cum + ( ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ) ; if ( first_anon_arg < MAX_ARC_PARM_REGS && ! no_rtl ) { int first_reg_offset = first_anon_arg ; int size = MAX_ARC_PARM_REGS - first_reg_offset ; int align_slop = size & 1 ; rtx regblock ; regblock = gen_rtx_MEM ( BLKmode , plus_constant ( arg_pointer_rtx , FIRST_PARM_OFFSET ( 0 ) + align_slop * UNITS_PER_WORD ) ) ; set_mem_alias_set ( regblock , get_varargs_alias_set ( ) ) ; set_mem_align ( regblock , BITS_PER_WORD ) ; move_block_from_reg ( first_reg_offset , regblock , MAX_ARC_PARM_REGS - first_reg_offset ) ; * pretend_size = ( ( MAX_ARC_PARM_REGS - first_reg_offset + align_slop ) * UNITS_PER_WORD ) ; } } </s>

Do any needed setup for a variadic function . For the ARC , we must create a register parameter block , and then copy any anonymous arguments in registers to memory . CUM has not been updated for the last named argument which has type TYPE and mode MODE , and we rely on this fact .


<s> bool RISCVAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { MCSubtargetInfo & NewSTI = OutStreamer -> getContext ( ) . getSubtargetCopy ( * TM . getMCSubtargetInfo ( ) ) ; NewSTI . setFeatureBits ( MF . getSubtarget ( ) . getFeatureBits ( ) ) ; MCSTI = & NewSTI ; STI = & MF . getSubtarget < RISCVSubtarget > ( ) ; SetupMachineFunction ( MF ) ; emitFunctionBody ( ) ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool SparcPassConfig :: addPreEmitPass ( ) { addPass ( createSparcDelaySlotFillerPass ( getSparcTargetMachine ( ) ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
void
SystemZHazardRecognizer
::
EmitInstruction
(
SUnit
*
SU
)
{
const
MCSchedClassDesc
*
SC
=
getSchedClass
(
SU
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"++ HazardRecognizer emitting "
;
dumpSU
(
SU
,
dbgs
(
)
)
;
dbgs
(
)
<<
"\n"
;
)
;
LLVM_DEBUG
(
dumpCurrGroup
(
"Decode group before emission"
)
;
)
;
if
(
!
fitsIntoCurrentGroup
(
SU
)
)
nextGroup
(
)
;
LLVM_DEBUG
(
raw_string_ostream
cgd
(
CurGroupDbg
)
;
if
(
CurGroupDbg
.
length
(
)
)
cgd
<<
", "
;
dumpSU
(
SU
,
cgd
)
;
)
;
LastEmittedMI
=
SU
->
getInstr
(
)
;
if
(
SU
->
isCall
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"++ Clearing state after call.\n"
;
)
;
Reset
(
)
;
LastEmittedMI
=
SU
->
getInstr
(
)
;
return
;
}
for
(
TargetSchedModel
::
ProcResIter
PI
=
SchedModel
->
getWriteProcResBegin
(
SC
)
,
PE
=
SchedModel
->
getWriteProcResEnd
(
SC
)
;
PI
!=
PE
;
++
PI
)
{
if
(
SchedModel
->
getProcResource
(
PI
->
ProcResourceIdx
)
->
BufferSize
==
1
)
continue
;
int
&
CurrCounter
=
ProcResourceCounters
[
PI
->
ProcResourceIdx
]
;
CurrCounter
+=
PI
->
Cycles
;
if
(
(
CurrCounter
>
ProcResCostLim
)
&&
(
CriticalResourceIdx
==
UINT_MAX
||
(
PI
->
ProcResourceIdx
!=
CriticalResourceIdx
&&
CurrCounter
>
ProcResourceCounters
[
CriticalResourceIdx
]
)
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"++ New critical resource: "
<<
SchedModel
->
getProcResource
(
PI
->
ProcResourceIdx
)
->
Name
<<
"\n"
;
)
;
CriticalResourceIdx
=
PI
->
ProcResourceIdx
;
}
}
if
(
SU
->
isUnbuffered
)
{
LastFPdOpCycleIdx
=
getCurrCycleIdx
(
SU
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"++ Last FPd cycle index: "
<<
LastFPdOpCycleIdx
<<
"\n"
;
)
;
}
CurrGroupSize
+=
getNumDecoderSlots
(
SU
)
;
assert
(
CurrGroupSize
<=
3
)
;
if
(
CurrGroupSize
==
3
||
SC
->
EndGroup
)
nextGroup
(
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .

SystemZ
SystemZ
"++ HazardRecognizer emitting "
"\n"
"Decode group before emission"
", "
"++ Clearing state after call.\n"
1
"++ New critical resource: "
"\n"
"++ Last FPd cycle index: "
"\n"
3
3


<s>
void
RV16KFrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
unsigned
FPReg
=
getFPReg
(
)
;
unsigned
SPReg
=
getSPReg
(
)
;
DebugLoc
DL
;
determineFrameLayout
(
MF
)
;
uint64_t
StackSize
=
MFI
.
getStackSize
(
)
;
if
(
StackSize
==
0
&&
!
MFI
.
adjustsStack
(
)
)
return
;
adjustReg
(
MBB
,
MBBI
,
DL
,
SPReg
,
SPReg
,
StackSize
,
MachineInstr
::
FrameSetup
)
;
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
.
getCalleeSavedInfo
(
)
;
std
::
advance
(
MBBI
,
CSI
.
size
(
)
)
;
if
(
hasFP
(
MF
)
)
adjustReg
(
MBB
,
MBBI
,
DL
,
FPReg
,
SPReg
,
StackSize
,
MachineInstr
::
FrameSetup
)
;
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static cpp_hashnode * s390_macro_to_expand ( cpp_reader * pfile , const cpp_token * tok ) { cpp_hashnode * expand_this = tok -> val . node . node ; cpp_hashnode * ident ; static bool expand_bool_p = false ; int idx = 0 ; enum rid rid_code ; if ( ! TARGET_ZVECTOR ) return NULL ; ident = s390_categorize_keyword ( tok ) ; if ( ident != expand_this ) expand_this = NULL ; if ( expand_bool_p && ident == C_CPP_HASHNODE ( __bool_keyword ) ) { expand_bool_p = false ; return ident ; } if ( ident != C_CPP_HASHNODE ( __vector_keyword ) ) return expand_this ; do tok = cpp_peek_token ( pfile , idx ++ ) ; while ( tok -> type == CPP_PADDING ) ; ident = s390_categorize_keyword ( tok ) ; if ( ! ident ) return expand_this ; if ( ident == C_CPP_HASHNODE ( __bool_keyword ) ) { expand_bool_p = true ; return C_CPP_HASHNODE ( __vector_keyword ) ; } if ( ident == C_CPP_HASHNODE ( __vector_keyword ) ) return expand_this ; rid_code = ( enum rid ) ( ident -> rid_code ) ; if ( ident -> type == NT_MACRO ) { do ( void ) cpp_get_token ( pfile ) ; while ( -- idx > 0 ) ; do tok = cpp_peek_token ( pfile , idx ++ ) ; while ( tok -> type == CPP_PADDING ) ; ident = s390_categorize_keyword ( tok ) ; if ( ident == C_CPP_HASHNODE ( __bool_keyword ) ) { expand_bool_p = true ; return C_CPP_HASHNODE ( __vector_keyword ) ; } else if ( ident ) rid_code = ( enum rid ) ( ident -> rid_code ) ; } if ( rid_code == RID_UNSIGNED || rid_code == RID_LONG || rid_code == RID_SHORT || rid_code == RID_SIGNED || rid_code == RID_INT || rid_code == RID_CHAR || ( rid_code == RID_FLOAT && TARGET_VXE ) || rid_code == RID_DOUBLE ) { expand_this = C_CPP_HASHNODE ( __vector_keyword ) ; do tok = cpp_peek_token ( pfile , idx ++ ) ; while ( tok -> type == CPP_PADDING ) ; ident = s390_categorize_keyword ( tok ) ; if ( ident == C_CPP_HASHNODE ( __bool_keyword ) ) expand_bool_p = true ; else { do tok = cpp_peek_token ( pfile , idx ++ ) ; while ( tok -> type == CPP_PADDING ) ; ident = s390_categorize_keyword ( tok ) ; if ( ident == C_CPP_HASHNODE ( __bool_keyword ) ) expand_bool_p = true ; } } return expand_this ; } </s>

Called to decide whether a conditional macro should be expanded . Since we have exactly one such macro ( i.e , 'vector ' ) , we do not need to examine the 'tok ' parameter .


<s> static rtx nios2_expand_ldst_builtin ( tree exp , rtx target , const struct nios2_builtin_desc * d ) { bool has_target_p ; rtx addr , mem , val ; struct expand_operand ops [ MAX_RECOG_OPERANDS ] ; machine_mode mode = insn_data [ d -> icode ] . operand [ 0 ] . mode ; addr = expand_normal ( CALL_EXPR_ARG ( exp , 0 ) ) ; mem = gen_rtx_MEM ( mode , addr ) ; if ( insn_data [ d -> icode ] . operand [ 0 ] . allows_mem ) { val = expand_normal ( CALL_EXPR_ARG ( exp , 1 ) ) ; if ( CONST_INT_P ( val ) ) val = force_reg ( mode , gen_int_mode ( INTVAL ( val ) , mode ) ) ; val = simplify_gen_subreg ( mode , val , GET_MODE ( val ) , 0 ) ; create_output_operand ( & ops [ 0 ] , mem , mode ) ; create_input_operand ( & ops [ 1 ] , val , mode ) ; if ( insn_data [ d -> icode ] . n_operands == 3 ) { create_output_operand ( & ops [ 2 ] , target , mode ) ; has_target_p = true ; } else has_target_p = false ; } else { create_output_operand ( & ops [ 0 ] , target , mode ) ; create_input_operand ( & ops [ 1 ] , mem , mode ) ; has_target_p = true ; } return nios2_expand_builtin_insn ( d , insn_data [ d -> icode ] . n_operands , ops , has_target_p ) ; } </s>

Expand ldio/stio and ldex/ldsex/stex/stsex form load-store instruction builtins .


<s>
bool
R600Packetizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
const
TargetInstrInfo
*
TII
=
Fn
.
getTarget
(
)
.
getInstrInfo
(
)
;
MachineLoopInfo
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
MachineDominatorTree
&
MDT
=
getAnalysis
<
MachineDominatorTree
>
(
)
;
R600PacketizerList
Packetizer
(
Fn
,
MLI
,
MDT
)
;
assert
(
Packetizer
.
getResourceTracker
(
)
&&
"Empty DFA table!"
)
;
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
MachineBasicBlock
::
iterator
End
=
MBB
->
end
(
)
;
MachineBasicBlock
::
iterator
MI
=
MBB
->
begin
(
)
;
while
(
MI
!=
End
)
{
if
(
MI
->
isKill
(
)
||
(
MI
->
getOpcode
(
)
==
AMDGPU
::
CF_ALU
&&
!
MI
->
getOperand
(
8
)
.
getImm
(
)
)
)
{
MachineBasicBlock
::
iterator
DeleteMI
=
MI
;
++
MI
;
MBB
->
erase
(
DeleteMI
)
;
End
=
MBB
->
end
(
)
;
continue
;
}
++
MI
;
}
}
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
unsigned
RemainingCount
=
MBB
->
size
(
)
;
for
(
MachineBasicBlock
::
iterator
RegionEnd
=
MBB
->
end
(
)
;
RegionEnd
!=
MBB
->
begin
(
)
;
)
{
MachineBasicBlock
::
iterator
I
=
RegionEnd
;
for
(
;
I
!=
MBB
->
begin
(
)
;
I
,
RemainingCount
)
{
if
(
TII
->
isSchedulingBoundary
(
llvm
::
prior
(
I
)
,
MBB
,
Fn
)
)
break
;
}
I
=
MBB
->
begin
(
)
;
if
(
I
==
RegionEnd
)
{
RegionEnd
=
llvm
::
prior
(
RegionEnd
)
;
RemainingCount
;
continue
;
}
if
(
I
==
llvm
::
prior
(
RegionEnd
)
)
{
RegionEnd
=
llvm
::
prior
(
RegionEnd
)
;
continue
;
}
Packetizer
.
PacketizeMIs
(
MBB
,
I
,
RegionEnd
)
;
RegionEnd
=
I
;
}
}
return
true
;
}
</s>


<s>
SDNode
*
BPFDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
return
;
}
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
FrameIndex
:
{
int
FI
=
dyn_cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
EVT
VT
=
Node
->
getValueType
(
0
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
VT
)
;
unsigned
Opc
=
BPF
::
MOV_rr
;
if
(
Node
->
hasOneUse
(
)
)
return
CurDAG
->
SelectNodeTo
(
Node
,
Opc
,
VT
,
TFI
)
;
return
CurDAG
->
getMachineNode
(
Opc
,
SDLoc
(
Node
)
,
VT
,
TFI
)
;
return
CurDAG
->
getMachineNode
(
Opc
,
Node
->
getDebugLoc
(
)
,
VT
,
TFI
)
;
}
}
SDNode
*
ResNode
=
SelectCode
(
Node
)
;
DEBUG
(
errs
(
)
<<
"=> "
)
;
if
(
ResNode
==
||
ResNode
==
Node
)
DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
else
DEBUG
(
ResNode
->
dump
(
CurDAG
)
)
;
DEBUG
(
errs
(
)
<<
"\n"
)
;
return
ResNode
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

BPF
BPF
"Selecting: "
"\n"
"== "
"\n"
ISD::FrameIndex
0
BPF::MOV_rr
"=> "
"\n"


<s> static bool scalar_to_vector_candidate_p ( rtx_insn * insn ) { rtx def_set = single_set ( insn ) ; if ( ! def_set ) return false ; if ( has_non_address_hard_reg ( insn ) ) return false ; rtx src = SET_SRC ( def_set ) ; rtx dst = SET_DEST ( def_set ) ; if ( GET_CODE ( src ) == COMPARE ) return convertible_comparison_p ( insn ) ; if ( GET_MODE ( src ) != DImode || GET_MODE ( dst ) != DImode ) return false ; if ( ! REG_P ( dst ) && ! MEM_P ( dst ) ) return false ; switch ( GET_CODE ( src ) ) { case PLUS : case MINUS : case IOR : case XOR : case AND : break ; case REG : return true ; case MEM : return REG_P ( dst ) ; default : return false ; } if ( ! REG_P ( XEXP ( src , 0 ) ) && ! MEM_P ( XEXP ( src , 0 ) ) && ( GET_CODE ( src ) != AND || GET_CODE ( XEXP ( src , 0 ) ) != NOT || ! REG_P ( XEXP ( XEXP ( src , 0 ) , 0 ) ) ) ) return false ; if ( ! REG_P ( XEXP ( src , 1 ) ) && ! MEM_P ( XEXP ( src , 1 ) ) ) return false ; if ( GET_MODE ( XEXP ( src , 0 ) ) != DImode || GET_MODE ( XEXP ( src , 1 ) ) != DImode ) return false ; return true ; } </s>

Return 1 if INSN may be converted into vector instruction .