<s>
static
MCSymbol
*
GetSymbolFromOperand
(
const
MachineOperand
&
MO
,
AsmPrinter
&
AP
)
{
const
TargetMachine
&
TM
=
AP
.
TM
;
Mangler
*
Mang
=
AP
.
Mang
;
const
DataLayout
*
DL
=
TM
.
getDataLayout
(
)
;
MCContext
&
Ctx
=
AP
.
OutContext
;
bool
isDarwin
=
Triple
(
TM
.
getTargetTriple
(
)
)
.
isOSDarwin
(
)
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
)
{
if
(
isDarwin
)
Suffix
=
"$stub"
;
}
else
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
Suffix
=
"$non_lazy_ptr"
;
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
->
getPrivateGlobalPrefix
(
)
;
unsigned
PrefixLen
=
Name
.
size
(
)
;
if
(
!
MO
.
isGlobal
(
)
)
{
assert
(
MO
.
isSymbol
(
)
&&
"Isn't a symbol reference"
)
;
Mang
->
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
)
;
}
else
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
TM
.
getNameWithPrefix
(
Name
,
GV
,
*
Mang
)
;
}
unsigned
OrigLen
=
Name
.
size
(
)
PrefixLen
;
Name
+=
Suffix
;
MCSymbol
*
Sym
=
Ctx
.
GetOrCreateSymbol
(
Name
.
str
(
)
)
;
StringRef
OrigName
=
StringRef
(
Name
)
.
substr
(
PrefixLen
,
OrigLen
)
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
&&
isDarwin
)
{
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
getMachOMMI
(
AP
)
.
getFnStubEntry
(
Sym
)
;
if
(
StubSym
.
getPointer
(
)
)
return
Sym
;
if
(
MO
.
isGlobal
(
)
)
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
else
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
Ctx
.
GetOrCreateSymbol
(
OrigName
)
,
false
)
;
}
return
Sym
;
}
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
{
MachineModuleInfoMachO
&
MachO
=
getMachOMMI
(
AP
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_HIDDEN_FLAG
)
MachO
.
getHiddenGVStubEntry
(
Sym
)
:
MachO
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
return
Sym
;
}
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandLoadLinkedPass ( TM ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static void mips_avoid_hazards ( void ) { rtx insn , last_insn , lo_reg , delayed_reg ; int hilo_delay , i ; split_all_insns_noflow ( ) ; cfun -> machine -> ignore_hazard_length_p = true ; shorten_branches ( get_insns ( ) ) ; cfun -> machine -> all_noreorder_p = true ; if ( current_function_profile ) cfun -> machine -> all_noreorder_p = false ; if ( TARGET_FIX_VR4120 ) cfun -> machine -> all_noreorder_p = false ; if ( TARGET_FIX_VR4130 && ! ISA_HAS_MACCHI ) cfun -> machine -> all_noreorder_p = false ; last_insn = 0 ; hilo_delay = 2 ; delayed_reg = 0 ; lo_reg = gen_rtx_REG ( SImode , LO_REGNUM ) ; for ( insn = get_insns ( ) ; insn != 0 ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) ) { if ( GET_CODE ( PATTERN ( insn ) ) == SEQUENCE ) for ( i = 0 ; i < XVECLEN ( PATTERN ( insn ) , 0 ) ; i ++ ) mips_avoid_hazard ( last_insn , XVECEXP ( PATTERN ( insn ) , 0 , i ) , & hilo_delay , & delayed_reg , lo_reg ) ; else mips_avoid_hazard ( last_insn , insn , & hilo_delay , & delayed_reg , lo_reg ) ; last_insn = insn ; } } </s>

Go through the instruction stream and insert nops where necessary . See if the whole function can then be put into .set noreorder & .set nomacro .


<s> void final_prescan_insn ( rtx_insn * insn , rtx opvec [ ] ATTRIBUTE_UNUSED , int noperands ATTRIBUTE_UNUSED ) { if ( dslots_number_nops > 0 ) { rtx pattern = PATTERN ( insn ) ; int length = get_attr_length ( insn ) ; if ( length == 0 || ( iq2000_load_reg != 0 && reg_mentioned_p ( iq2000_load_reg , pattern ) ) || ( iq2000_load_reg2 != 0 && reg_mentioned_p ( iq2000_load_reg2 , pattern ) ) || ( iq2000_load_reg3 != 0 && reg_mentioned_p ( iq2000_load_reg3 , pattern ) ) || ( iq2000_load_reg4 != 0 && reg_mentioned_p ( iq2000_load_reg4 , pattern ) ) ) fputs ( "\tnop\n" , asm_out_file ) ; else dslots_load_filled ++ ; while ( -- dslots_number_nops > 0 ) fputs ( "\tnop\n" , asm_out_file ) ; iq2000_load_reg = 0 ; iq2000_load_reg2 = 0 ; iq2000_load_reg3 = 0 ; iq2000_load_reg4 = 0 ; } if ( ( JUMP_P ( insn ) || CALL_P ( insn ) || ( GET_CODE ( PATTERN ( insn ) ) == RETURN ) ) && NEXT_INSN ( PREV_INSN ( insn ) ) == insn ) { rtx_insn * nop_insn = emit_insn_after ( gen_nop ( ) , insn ) ; INSN_ADDRESSES_NEW ( nop_insn , - 1 ) ; } if ( TARGET_STATS && ( JUMP_P ( insn ) || CALL_P ( insn ) ) ) dslots_jump_total ++ ; } </s>

If defined , a C statement to be executed just prior to the output of assembler code for INSN , to modify the extracted operands so they will be output differently . Here the argument OPVEC is the vector containing the operands extracted from INSN , and NOPERANDS is the number of elements of the vector which contain meaningful data for this insn . The contents of this vector are what will be used to convert the insn template into assembler code , so you can change the assembler output by changing the contents of the vector . We use it to check if the current insn needs a nop in front of it because of load delays , and also to update the delay slot statistics .


<s> int AMDGPUTTIImpl :: getArithmeticReductionCost ( unsigned Opcode , Type * Ty , bool IsPairwise ) { EVT OrigTy = TLI -> getValueType ( DL , Ty ) ; if ( IsPairwise || ! ST -> hasVOP3PInsts ( ) || OrigTy . getScalarSizeInBits ( ) != 16 ) return BaseT :: getArithmeticReductionCost ( Opcode , Ty , IsPairwise ) ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; return LT . first * getFullRateInstrCost ( ) ; } </s>

Calculate the cost of vector reduction intrinsics .


<s> bool X86RegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ; if ( CantUseSP ( MFI ) ) return MRI -> canReserveReg ( BasePtr ) ; return true ; } </s>

True if the stack can be realigned for the target .


<s> void LC2200AsmBackend :: relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> bool AArch64LowerHomogeneousPE :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const AArch64InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; bool Modified = false ; for ( auto & MBB : MF ) Modified |= runOnMBB ( MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s>
bool
AMDGPUAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Name
=
parseMnemonicSuffix
(
Name
)
;
Operands
.
push_back
(
AMDGPUOperand
::
CreateToken
(
this
,
Name
,
NameLoc
)
)
;
bool
IsMIMG
=
Name
.
startswith
(
"image_"
)
;
while
(
!
trySkipToken
(
AsmToken
::
EndOfStatement
)
)
{
OperandMode
Mode
=
OperandMode_Default
;
if
(
IsMIMG
&&
isGFX10Plus
(
)
&&
Operands
.
size
(
)
==
2
)
Mode
=
OperandMode_NSA
;
CPolSeen
=
0
;
OperandMatchResultTy
Res
=
parseOperand
(
Operands
,
Name
,
Mode
)
;
if
(
Res
!=
MatchOperand_Success
)
{
checkUnsupportedInstruction
(
Name
,
NameLoc
)
;
if
(
!
Parser
.
hasPendingError
(
)
)
{
StringRef
Msg
=
(
Res
==
MatchOperand_ParseFail
)
"failed parsing operand."
:
"not a valid operand."
;
Error
(
getLoc
(
)
,
Msg
)
;
}
while
(
!
trySkipToken
(
AsmToken
::
EndOfStatement
)
)
{
lex
(
)
;
}
return
true
;
}
trySkipToken
(
AsmToken
::
Comma
)
;
}
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .


<s> static int index_term_p ( rtx prod , enum machine_mode mode , int strict ) { rtx xfoo0 , xfoo1 ; if ( GET_MODE_SIZE ( mode ) == 1 ) return BASE_REGISTER_P ( prod , strict ) ; if ( GET_CODE ( prod ) != MULT || GET_MODE_SIZE ( mode ) > 8 ) return 0 ; xfoo0 = XEXP ( prod , 0 ) ; xfoo1 = XEXP ( prod , 1 ) ; if ( GET_CODE ( xfoo0 ) == CONST_INT && INTVAL ( xfoo0 ) == ( int ) GET_MODE_SIZE ( mode ) && INDEX_REGISTER_P ( xfoo1 , strict ) ) return 1 ; if ( GET_CODE ( xfoo1 ) == CONST_INT && INTVAL ( xfoo1 ) == ( int ) GET_MODE_SIZE ( mode ) && INDEX_REGISTER_P ( xfoo0 , strict ) ) return 1 ; return 0 ; } </s>

1 if PROD is either a reg times size of mode MODE and MODE is less than or equal 8 bytes , or just a reg if MODE is one byte .


<s> void c6x_init_cumulative_args ( CUMULATIVE_ARGS * cum , const_tree fntype , rtx libname , int n_named_args ATTRIBUTE_UNUSED ) { cum -> count = 0 ; cum -> nregs = 10 ; if ( ! libname && fntype ) { if ( stdarg_p ( fntype ) ) cum -> nregs = type_num_arguments ( fntype ) - 1 ; if ( cum -> nregs > 10 ) cum -> nregs = 10 ; } } </s>

Implements the macro INIT_CUMULATIVE_ARGS defined in c6x.h .


<s> char * get_name ( function_builder & b , const function_instance & instance , bool overloaded_p ) const override { if ( overloaded_p ) if ( instance . pred == PRED_TYPE_none || instance . pred == PRED_TYPE_mu ) return nullptr ; tree type = builtin_types [ instance . type . index ] . vector ; machine_mode mode = TYPE_MODE ( type ) ; int sew = GET_MODE_BITSIZE ( GET_MODE_INNER ( mode ) ) ; b . append_name ( "__riscv_" ) ; b . append_name ( "vle" ) ; b . append_sew ( sew ) ; b . append_name ( "ff" ) ; if ( ! overloaded_p ) { b . append_name ( operand_suffixes [ instance . op_info -> op ] ) ; b . append_name ( type_suffixes [ instance . type . index ] . vector ) ; } if ( overloaded_p && instance . pred == PRED_TYPE_m ) return b . finish_name ( ) ; b . append_name ( predication_suffixes [ instance . pred ] ) ; return b . finish_name ( ) ; } </s>

Return the overloaded or full function name for INSTANCE ; OVERLOADED_P selects which . Allocate the string on m_string_obstack ; the caller must use obstack_free to free it after use .


<s> bool ARMSubtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtarget :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = TargetSubtarget :: ANTIDEP_CRITICAL ; CriticalPathRCs . clear ( ) ; CriticalPathRCs . push_back ( & ARM :: GPRRegClass ) ; return PostRAScheduler && OptLevel >= CodeGenOpt :: Default ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s> bool ARMSubtarget :: isGVInGOT ( const GlobalValue * GV ) const { return isTargetELF ( ) && TM . isPositionIndependent ( ) && ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ; } </s>

Returns the constant pool modifier needed to access the GV .


<s> static bool x86_can_output_mi_thunk ( tree thunk ATTRIBUTE_UNUSED , HOST_WIDE_INT delta ATTRIBUTE_UNUSED , HOST_WIDE_INT vcall_offset , tree function ) { if ( TARGET_64BIT ) return true ; if ( ix86_function_regparm ( TREE_TYPE ( function ) , function ) < 3 ) return true ; if ( vcall_offset ) return false ; if ( flag_pic && ! ( * targetm . binds_local_p ) ( function ) ) return false ; return true ; } </s>

Determine whether x86_output_mi_thunk can succeed .


<s> unsigned ARMRegisterInfo :: getFrameRegister ( MachineFunction & MF ) const { if ( STI . isTargetDarwin ( ) || hasFP ( MF ) ) return ( STI . useThumbBacktraces ( ) || STI . isThumb ( ) ) ? ARM :: R7 : ARM :: R11 ; else return ARM :: SP ; } </s>


<s>
bool
ARMLowOverheadLoops
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
const
ARMSubtarget
&
ST
=
static_cast
<
const
ARMSubtarget
&
>
(
mf
.
getSubtarget
(
)
)
;
if
(
!
ST
.
hasLOB
(
)
)
return
false
;
MF
=
&
mf
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM Loops on "
<<
MF
->
getName
(
)
<<
" ------------- \n"
)
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
RDA
=
&
getAnalysis
<
ReachingDefAnalysis
>
(
)
;
MF
->
getProperties
(
)
.
set
(
MachineFunctionProperties
::
Property
::
TracksLiveness
)
;
MRI
=
&
MF
->
getRegInfo
(
)
;
TII
=
static_cast
<
const
ARMBaseInstrInfo
*
>
(
ST
.
getInstrInfo
(
)
)
;
TRI
=
ST
.
getRegisterInfo
(
)
;
BBUtils
=
std
::
unique_ptr
<
ARMBasicBlockUtils
>
(
new
ARMBasicBlockUtils
(
*
MF
)
)
;
BBUtils
->
computeAllBlockSizes
(
)
;
BBUtils
->
adjustBBOffsetsAfter
(
&
MF
->
front
(
)
)
;
bool
Changed
=
false
;
for
(
auto
ML
:
*
MLI
)
{
if
(
!
ML
->
getParentLoop
(
)
)
Changed
|=
ProcessLoop
(
ML
)
;
}
Changed
|=
RevertNonLoops
(
)
;
return
Changed
;
}
</s>

ARM
ARM
ARM
ARM
"ARM Loops on "
" ------------- \n"
ARM
ARM
ARM


<s> bool CAHPFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static bool xscale_sched_adjust_cost ( rtx_insn * insn , int dep_type , rtx_insn * dep , int * cost ) { if ( dep_type == 0 && recog_memoized ( insn ) >= 0 && recog_memoized ( dep ) >= 0 ) { int shift_opnum = get_attr_shift ( insn ) ; enum attr_type attr_type = get_attr_type ( dep ) ; if ( shift_opnum != 0 && ( attr_type == TYPE_ALU_SHIFT_IMM_LSL_1TO4 || attr_type == TYPE_ALU_SHIFT_IMM_OTHER || attr_type == TYPE_ALUS_SHIFT_IMM || attr_type == TYPE_LOGIC_SHIFT_IMM || attr_type == TYPE_LOGICS_SHIFT_IMM || attr_type == TYPE_ALU_SHIFT_REG || attr_type == TYPE_ALUS_SHIFT_REG || attr_type == TYPE_LOGIC_SHIFT_REG || attr_type == TYPE_LOGICS_SHIFT_REG || attr_type == TYPE_MOV_SHIFT || attr_type == TYPE_MVN_SHIFT || attr_type == TYPE_MOV_SHIFT_REG || attr_type == TYPE_MVN_SHIFT_REG ) ) { rtx shifted_operand ; int opno ; extract_insn ( insn ) ; shifted_operand = recog_data . operand [ shift_opnum ] ; extract_insn ( dep ) ; preprocess_constraints ( dep ) ; for ( opno = 0 ; opno < recog_data . n_operands ; opno ++ ) { if ( recog_data . operand_type [ opno ] == OP_IN ) continue ; if ( reg_overlap_mentioned_p ( recog_data . operand [ opno ] , shifted_operand ) ) { * cost = 2 ; return false ; } } } } return true ; } </s>


<s> bool JVMPassConfig :: addInstSelector ( ) { ( void ) TargetPassConfig :: addInstSelector ( ) ; addPass ( createJVMISelDag ( getJVMTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s>
AVR
::
Fixups
AVRMCExpr
::
getFixupKind
(
)
const
{
AVR
::
Fixups
Kind
=
AVR
::
Fixups
::
LastTargetFixupKind
;
switch
(
getKind
(
)
)
{
case
VK_AVR_LO8
:
Kind
=
isNegated
(
)
AVR
::
fixup_lo8_ldi_neg
:
AVR
::
fixup_lo8_ldi
;
break
;
case
VK_AVR_HI8
:
Kind
=
isNegated
(
)
AVR
::
fixup_hi8_ldi_neg
:
AVR
::
fixup_hi8_ldi
;
break
;
case
VK_AVR_HH8
:
Kind
=
isNegated
(
)
AVR
::
fixup_hh8_ldi_neg
:
AVR
::
fixup_hh8_ldi
;
break
;
case
VK_AVR_HHI8
:
Kind
=
isNegated
(
)
AVR
::
fixup_ms8_ldi_neg
:
AVR
::
fixup_ms8_ldi
;
break
;
case
VK_AVR_PM_LO8
:
Kind
=
isNegated
(
)
AVR
::
fixup_lo8_ldi_pm_neg
:
AVR
::
fixup_lo8_ldi_pm
;
break
;
case
VK_AVR_PM_HI8
:
Kind
=
isNegated
(
)
AVR
::
fixup_hi8_ldi_pm_neg
:
AVR
::
fixup_hi8_ldi_pm
;
break
;
case
VK_AVR_PM_HH8
:
Kind
=
isNegated
(
)
AVR
::
fixup_hh8_ldi_pm_neg
:
AVR
::
fixup_hh8_ldi_pm
;
break
;
case
VK_AVR_GS
:
Kind
=
AVR
::
fixup_16_pm
;
break
;
case
VK_AVR_LO8_GS
:
Kind
=
AVR
::
fixup_lo8_ldi_gs
;
break
;
case
VK_AVR_HI8_GS
:
Kind
=
AVR
::
fixup_hi8_ldi_gs
;
break
;
case
VK_AVR_None
:
llvm_unreachable
(
"Uninitialized expression"
)
;
}
return
Kind
;
}
</s>

getFixupKind - Get the fixup kind of this expression .


<s> void RV16KAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; MCInst TmpInst ; LowerRV16KMachineInstrToMCInst ( MI , TmpInst , * this ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
SDValue
PatmosTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
LOAD
:
return
LowerLOAD
(
Op
,
DAG
)
;
case
ISD
::
STORE
:
return
LowerSTORE
(
Op
,
DAG
)
;
case
ISD
::
SMUL_LOHI
:
case
ISD
::
UMUL_LOHI
:
return
LowerMUL_LOHI
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operation"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

Patmos
Patmos
ISD::LOAD
ISD::STORE
ISD::SMUL_LOHI
ISD::UMUL_LOHI
ISD::VASTART
ISD::FRAMEADDR
ISD::RETURNADDR
"unimplemented operation"


Compare an SVE mode SVE_M and an Advanced SIMD mode ASIMD_M and return whether the SVE mode should be preferred over the Advanced SIMD one in aarch64_autovectorize_vector_modes .


<s> void RISCVFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s> static void rs6000_darwin64_record_arg_recurse ( CUMULATIVE_ARGS * cum , const_tree type , HOST_WIDE_INT startbitpos , rtx rvec [ ] , int * k ) { tree f ; for ( f = TYPE_FIELDS ( type ) ; f ; f = DECL_CHAIN ( f ) ) if ( TREE_CODE ( f ) == FIELD_DECL ) { HOST_WIDE_INT bitpos = startbitpos ; tree ftype = TREE_TYPE ( f ) ; machine_mode mode ; if ( ftype == error_mark_node ) continue ; mode = TYPE_MODE ( ftype ) ; if ( DECL_SIZE ( f ) != 0 && tree_fits_uhwi_p ( bit_position ( f ) ) ) bitpos += int_bit_position ( f ) ; if ( TREE_CODE ( ftype ) == RECORD_TYPE ) rs6000_darwin64_record_arg_recurse ( cum , ftype , bitpos , rvec , k ) ; else if ( cum -> named && USE_FP_FOR_ARG_P ( cum , mode ) ) { unsigned n_fpreg = ( GET_MODE_SIZE ( mode ) + 7 ) >> 3 ; switch ( mode ) { case SCmode : mode = SFmode ; break ; case DCmode : mode = DFmode ; break ; case TCmode : mode = TFmode ; break ; default : break ; } rs6000_darwin64_record_arg_flush ( cum , bitpos , rvec , k ) ; if ( cum -> fregno + n_fpreg > FP_ARG_MAX_REG + 1 ) { gcc_assert ( cum -> fregno == FP_ARG_MAX_REG && ( mode == TFmode || mode == TDmode ) ) ; mode = DECIMAL_FLOAT_MODE_P ( mode ) ? DDmode : DFmode ; cum -> use_stack = 1 ; } rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , cum -> fregno ++ ) , GEN_INT ( bitpos / BITS_PER_UNIT ) ) ; if ( FLOAT128_2REG_P ( mode ) ) cum -> fregno ++ ; } else if ( cum -> named && USE_ALTIVEC_FOR_ARG_P ( cum , mode , 1 ) ) { rs6000_darwin64_record_arg_flush ( cum , bitpos , rvec , k ) ; rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , cum -> vregno ++ ) , GEN_INT ( bitpos / BITS_PER_UNIT ) ) ; } else if ( cum -> intoffset == - 1 ) cum -> intoffset = bitpos ; } } </s>


"MIa must load from or modify a memory location"

"MIb must load from or modify a memory location"

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> unsigned HexagonTTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args ) { if ( Ty -> isVectorTy ( ) ) { std :: pair < int , MVT > LT = TLI . getTypeLegalizationCost ( DL , Ty ) ; if ( LT . second . isFloatingPoint ( ) ) return LT . first + FloatFactor * getTypeNumElements ( Ty ) ; } return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo , Args ) ; } </s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> unsigned PatmosMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups ) const { if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; unsigned RegNo = getPatmosRegisterNumbering ( Reg ) ; return RegNo ; } else { return getImmediateEncoding ( MI , MO , Fixups ) ; } } </s>

getMachineOpValue - Return binary encoding of operand .


<s> bool MSP430AsmPrinter :: doFinalization ( Module & M ) { return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> bool LinuxAsmPrinter :: doInitialization ( Module & M ) { bool Result = AsmPrinter :: doInitialization ( M ) ; DW = getAnalysisIfAvailable < DwarfWriter > ( ) ; return Result ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> void M68kPassConfig :: addPreEmitPass ( ) { addPass ( createM68kCollapseMOVEMPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
SDValue
X86TargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
bool
Is64Bit
=
Subtarget
->
is64Bit
(
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_X86
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
CopyVT
=
VA
.
getValVT
(
)
;
if
(
(
CopyVT
==
MVT
::
f32
||
CopyVT
==
MVT
::
f64
)
&&
(
(
Is64Bit
||
Ins
[
i
]
.
Flags
.
isInReg
(
)
)
&&
!
Subtarget
->
hasSSE1
(
)
)
)
{
report_fatal_error
(
"SSE register return with SSE disabled"
)
;
}
SDValue
Val
;
if
(
VA
.
getLocReg
(
)
==
X86
::
ST0
||
VA
.
getLocReg
(
)
==
X86
::
ST1
)
{
if
(
isScalarFPTypeInSSEReg
(
VA
.
getValVT
(
)
)
)
CopyVT
=
MVT
::
f80
;
SDValue
Ops
[
]
=
{
Chain
,
InFlag
}
;
Chain
=
SDValue
(
DAG
.
getMachineNode
(
X86
::
FpPOP_RETVAL
,
dl
,
CopyVT
,
MVT
::
Other
,
MVT
::
Glue
,
Ops
,
2
)
,
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
if
(
CopyVT
!=
VA
.
getValVT
(
)
)
Val
=
DAG
.
getNode
(
ISD
::
FP_ROUND
,
dl
,
VA
.
getValVT
(
)
,
Val
,
DAG
.
getIntPtrConstant
(
1
)
)
;
}
else
{
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
CopyVT
,
InFlag
)
.
getValue
(
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
}
InFlag
=
Chain
.
getValue
(
2
)
;
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static char * rs6000_offload_options ( void ) { if ( TARGET_64BIT ) return xstrdup ( "-foffload-abi=lp64" ) ; else return xstrdup ( "-foffload-abi=ilp32" ) ; } </s>

Implement the TARGET_OFFLOAD_OPTIONS hook .


<s> bool s390_vectorize_vec_perm_const ( machine_mode vmode , machine_mode op_mode , rtx target , rtx op0 , rtx op1 , const vec_perm_indices & sel ) { if ( vmode != op_mode ) return false ; struct expand_vec_perm_d d ; unsigned int i , nelt ; if ( ! s390_vector_mode_supported_p ( vmode ) || GET_MODE_SIZE ( vmode ) != 16 ) return false ; d . target = target ; d . op0 = op0 ; d . op1 = op1 ; d . vmode = vmode ; gcc_assert ( VECTOR_MODE_P ( d . vmode ) ) ; d . nelt = nelt = GET_MODE_NUNITS ( d . vmode ) ; d . testing_p = target == NULL_RTX ; d . only_op0 = false ; d . only_op1 = false ; gcc_assert ( target == NULL_RTX || REG_P ( target ) ) ; gcc_assert ( sel . length ( ) == nelt ) ; unsigned int highest = 0 , lowest = 2 * nelt - 1 ; for ( i = 0 ; i < nelt ; i ++ ) { unsigned char e = sel [ i ] ; lowest = MIN ( lowest , e ) ; highest = MAX ( highest , e ) ; gcc_assert ( e < 2 * nelt ) ; d . perm [ i ] = e ; } if ( lowest < nelt && highest < nelt ) d . only_op0 = true ; else if ( lowest >= nelt && highest >= nelt ) d . only_op1 = true ; return vectorize_vec_perm_const_1 ( d ) ; } </s>

Return true if we can emit instructions for the constant permutation vector in SEL . If OUTPUT , IN0 , IN1 are non-null the hook is supposed to emit the required INSNs .


<s> static std :: unique_ptr < MipsOperand > CreateMem ( std :: unique_ptr < MipsOperand > Base , const MCExpr * Off , SMLoc S , SMLoc E , MipsAsmParser & Parser ) { auto Op = std :: make_unique < MipsOperand > ( k_Memory , Parser ) ; Op -> Mem . Base = Base . release ( ) ; Op -> Mem . Off = Off ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>


<s> bool X86InstrInfo :: isCopyInstr ( const MachineInstr & MI , const MachineOperand * & Src , const MachineOperand * & Dest ) const { if ( MI . isMoveReg ( ) ) { Dest = & MI . getOperand ( 0 ) ; Src = & MI . getOperand ( 1 ) ; return true ; } return false ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


<s>
Nios2Subtarget
&
Nios2Subtarget
::
initializeSubtargetDependencies
(
StringRef
CPU
,
StringRef
FS
)
{
if
(
TargetTriple
.
getArch
(
)
==
Triple
::
nios2
)
{
if
(
CPU
!=
"nios2r2"
)
{
CPU
=
"nios2r1"
;
Nios2ArchVersion
=
Nios2r1
;
}
else
{
Nios2ArchVersion
=
Nios2r2
;
}
}
else
{
errs
(
)
<<
"!!!Error, TargetTriple.getArch() = "
<<
TargetTriple
.
getArch
(
)
<<
"CPU = "
<<
CPU
<<
"\n"
;
exit
(
0
)
;
}
ParseSubtargetFeatures
(
CPU
,
FS
)
;
return
*
this
;
}
</s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool ARMLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { if ( skipFunction ( Fn . getFunction ( ) ) ) return false ; MF = & Fn ; STI = & static_cast < const ARMSubtarget & > ( Fn . getSubtarget ( ) ) ; TL = STI -> getTargetLowering ( ) ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; RegClassInfoValid = false ; isThumb2 = AFI -> isThumb2Function ( ) ; isThumb1 = AFI -> isThumbFunction ( ) && ! isThumb2 ; bool Modified = false ; for ( MachineBasicBlock & MBB : Fn ) { Modified |= LoadStoreMultipleOpti ( MBB ) ; if ( STI -> hasV5TOps ( ) && ! AFI -> shouldSignReturnAddress ( ) ) Modified |= MergeReturnIntoLDM ( MBB ) ; if ( isThumb1 ) Modified |= CombineMovBx ( MBB ) ; } Allocator . DestroyAll ( ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> static int csky_sched_issue_rate ( void ) { if ( CSKY_TARGET_ARCH ( CK810 ) ) return 2 ; else return 1 ; } </s>

Implement TARGET_SCHED_ISSUE_RATE . Lookup the issue rate in the per-core tuning structs .


<s> static bool frv_registers_conflict_p_1 ( rtx pat , regstate_t cond ) { subrtx_var_iterator :: array_type array ; FOR_EACH_SUBRTX_VAR ( iter , array , pat , NONCONST ) { rtx x = * iter ; if ( GET_CODE ( x ) == REG ) { unsigned int regno ; FOR_EACH_REGNO ( regno , x ) if ( ( frv_packet . regstate [ regno ] & REGSTATE_MODIFIED ) != 0 ) if ( frv_regstate_conflict_p ( frv_packet . regstate [ regno ] , cond ) ) return true ; } else if ( GET_CODE ( x ) == MEM ) { if ( frv_packet . num_mems > ARRAY_SIZE ( frv_packet . mems ) ) return 1 ; for ( unsigned int i = 0 ; i < frv_packet . num_mems ; i ++ ) if ( frv_regstate_conflict_p ( frv_packet . mems [ i ] . cond , cond ) ) { if ( true_dependence ( frv_packet . mems [ i ] . mem , VOIDmode , x ) ) return true ; if ( output_dependence ( frv_packet . mems [ i ] . mem , x ) ) return true ; } } else if ( GET_CODE ( x ) == SET && GET_CODE ( SET_SRC ( x ) ) == CALL ) iter . substitute ( SET_SRC ( x ) ) ; } return false ; } </s>

A for_each_rtx callback . Return 1 if * X depends on an instruction in the current packet . DATA points to a regstate_t that describes the condition under which * X might be set or used .


<s> Optional < DestSourcePair > M88kInstrInfo :: isCopyInstrImpl ( const MachineInstr & MI ) const { if ( MI . isMoveReg ( ) || ( MI . getOpcode ( ) == M88k :: ORri && MI . getOperand ( 2 ) . getImm ( ) == 0 ) ) return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 1 ) } ; if ( MI . getOpcode ( ) == M88k :: ORrr ) { if ( MI . getOperand ( 2 ) . getReg ( ) == M88k :: R0 ) return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 1 ) } ; if ( MI . getOperand ( 1 ) . getReg ( ) == M88k :: R0 ) return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 2 ) } ; } return None ; } </s>


<s> bool AMDGPUAlwaysInline :: runOnModule ( Module & M ) { std :: vector < GlobalAlias * > AliasesToRemove ; std :: vector < Function * > FuncsToClone ; for ( GlobalAlias & A : M . aliases ( ) ) { if ( Function * F = dyn_cast < Function > ( A . getAliasee ( ) ) ) { A . replaceAllUsesWith ( F ) ; AliasesToRemove . push_back ( & A ) ; } } if ( GlobalOpt ) { for ( GlobalAlias * A : AliasesToRemove ) { A -> eraseFromParent ( ) ; } } auto NewAttr = StressCalls ? Attribute :: NoInline : Attribute :: AlwaysInline ; auto IncompatAttr = StressCalls ? Attribute :: AlwaysInline : Attribute :: NoInline ; for ( Function & F : M ) { if ( ! F . hasLocalLinkage ( ) && ! F . isDeclaration ( ) && ! F . use_empty ( ) && ! F . hasFnAttribute ( IncompatAttr ) ) FuncsToClone . push_back ( & F ) ; } for ( Function * F : FuncsToClone ) { ValueToValueMapTy VMap ; Function * NewFunc = CloneFunction ( F , VMap ) ; NewFunc -> setLinkage ( GlobalValue :: InternalLinkage ) ; F -> replaceAllUsesWith ( NewFunc ) ; } for ( Function & F : M ) { if ( F . hasLocalLinkage ( ) && ! F . hasFnAttribute ( IncompatAttr ) ) { F . addFnAttr ( NewAttr ) ; } } return false ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> static SDValue matchBinOpReduction ( SDNode * Extract , ISD :: NodeType BinOp ) { if ( ( Extract -> getOpcode ( ) != ISD :: EXTRACT_VECTOR_ELT ) || ! isNullConstant ( Extract -> getOperand ( 1 ) ) ) return SDValue ( ) ; unsigned Stages = Log2_32 ( Extract -> getOperand ( 0 ) . getValueType ( ) . getVectorNumElements ( ) ) ; SDValue Op = Extract -> getOperand ( 0 ) ; for ( unsigned i = 0 ; i < Stages ; ++ i ) { if ( Op . getOpcode ( ) != BinOp ) return SDValue ( ) ; ShuffleVectorSDNode * Shuffle = dyn_cast < ShuffleVectorSDNode > ( Op . getOperand ( 0 ) . getNode ( ) ) ; if ( Shuffle ) { Op = Op . getOperand ( 1 ) ; } else { Shuffle = dyn_cast < ShuffleVectorSDNode > ( Op . getOperand ( 1 ) . getNode ( ) ) ; Op = Op . getOperand ( 0 ) ; } if ( ! Shuffle || ( Shuffle -> getOperand ( 0 ) != Op ) ) return SDValue ( ) ; for ( int Index = 0 , MaskEnd = 1 << i ; Index < MaskEnd ; ++ Index ) if ( Shuffle -> getMaskElt ( Index ) != MaskEnd + Index ) return SDValue ( ) ; } return Op ; } </s>

Match a binop + shuffle pyramid that represents a horizontal reduction over the elements of a vector starting from the EXTRACT_VECTOR_ELT node /p Extract .


<s> static MBlazeOperand * CreateMem ( unsigned Base , unsigned Off , SMLoc S , SMLoc E ) { MBlazeOperand * Op = new MBlazeOperand ( Memory ) ; Op -> Mem . Base = Base ; Op -> Mem . OffReg = Off ; Op -> Mem . Off = 0 ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>


"%qE has no form that takes %qT arguments"

Report that the function has no form that takes type suffix TYPE . Return error_mark_node .


<s>
void
XCoreAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
SmallString
<
128
>
Str
;
raw_svector_ostream
O
(
Str
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
XCore
::
DBG_VALUE
:
{
if
(
isVerbose
(
)
&&
OutStreamer
.
hasRawTextSupport
(
)
)
{
SmallString
<
128
>
TmpStr
;
raw_svector_ostream
OS
(
TmpStr
)
;
PrintDebugValueComment
(
MI
,
OS
)
;
OutStreamer
.
EmitRawText
(
StringRef
(
OS
.
str
(
)
)
)
;
}
return
;
}
case
XCore
::
ADD_2rus
:
if
(
MI
->
getOperand
(
2
)
.
getImm
(
)
==
0
)
{
O
<<
"\tmov "
<<
getRegisterName
(
MI
->
getOperand
(
0
)
.
getReg
(
)
)
<<
", "
<<
getRegisterName
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
;
OutStreamer
.
EmitRawText
(
O
.
str
(
)
)
;
return
;
}
break
;
}
printInstruction
(
MI
,
O
)
;
OutStreamer
.
EmitRawText
(
O
.
str
(
)
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void X86FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MF . setHasWinCFI ( false ) ; const Function & F = MF . getFunction ( ) ; if ( ! STI . is64Bit ( ) || ! MF . hasEHFunclets ( ) || classifyEHPersonality ( F . getPersonalityFn ( ) ) != EHPersonality :: MSVC_CXX ) return ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; WinEHFuncInfo & EHInfo = * MF . getWinEHFuncInfo ( ) ; int64_t MinFixedObjOffset = - SlotSize ; for ( int I = MFI . getObjectIndexBegin ( ) ; I < 0 ; ++ I ) MinFixedObjOffset = std :: min ( MinFixedObjOffset , MFI . getObjectOffset ( I ) ) ; for ( WinEHTryBlockMapEntry & TBME : EHInfo . TryBlockMap ) { for ( WinEHHandlerType & H : TBME . HandlerArray ) { int FrameIndex = H . CatchObj . FrameIndex ; if ( FrameIndex != INT_MAX ) { unsigned Align = MFI . getObjectAlign ( FrameIndex ) . value ( ) ; MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % Align ; MinFixedObjOffset -= MFI . getObjectSize ( FrameIndex ) ; MFI . setObjectOffset ( FrameIndex , MinFixedObjOffset ) ; } } } MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % 8 ; int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize ; int UnwindHelpFI = MFI . CreateFixedObject ( SlotSize , UnwindHelpOffset , false ) ; EHInfo . UnwindHelpFrameIdx = UnwindHelpFI ; MachineBasicBlock & MBB = MF . front ( ) ; auto MBBI = MBB . begin ( ) ; while ( MBBI != MBB . end ( ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) ) ++ MBBI ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; addFrameReference ( BuildMI ( MBB , MBBI , DL , TII . get ( X86 :: MOV64mi32 ) ) , UnwindHelpFI ) . addImm ( - 2 ) ; } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> void RISCVFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( hasFP ( MF ) ) { SavedRegs . set ( RISCV :: X1 ) ; SavedRegs . set ( RISCV :: X8 ) ; } MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MF . getFunction ( ) . hasFnAttribute ( "interrupt" ) && MFI . hasCalls ( ) ) { static const MCPhysReg CSRegs [ ] = { RISCV :: X1 , RISCV :: X5 , RISCV :: X6 , RISCV :: X7 , RISCV :: X10 , RISCV :: X11 , RISCV :: X12 , RISCV :: X13 , RISCV :: X14 , RISCV :: X15 , RISCV :: X16 , RISCV :: X17 , RISCV :: X28 , RISCV :: X29 , RISCV :: X30 , RISCV :: X31 , 0 } ; for ( unsigned i = 0 ; CSRegs [ i ] ; ++ i ) SavedRegs . set ( CSRegs [ i ] ) ; if ( MF . getSubtarget < RISCVSubtarget > ( ) . hasStdExtD ( ) || MF . getSubtarget < RISCVSubtarget > ( ) . hasStdExtF ( ) ) { const MCPhysReg * Regs = MF . getRegInfo ( ) . getCalleeSavedRegs ( ) ; for ( unsigned i = 0 ; Regs [ i ] ; ++ i ) if ( RISCV :: FPR32RegClass . contains ( Regs [ i ] ) || RISCV :: FPR64RegClass . contains ( Regs [ i ] ) ) SavedRegs . set ( Regs [ i ] ) ; } } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> bool UPTInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { bool HasCondBranch = false ; TBB = nullptr ; FBB = nullptr ; for ( MachineInstr & MI : MBB ) { if ( MI . getOpcode ( ) == UPT :: JMP ) { MachineBasicBlock * TargetBB = MI . getOperand ( 0 ) . getMBB ( ) ; if ( HasCondBranch ) { FBB = TargetBB ; } else { TBB = TargetBB ; } } else if ( MI . getOpcode ( ) == UPT :: Bcc ) { MachineBasicBlock * TargetBB = MI . getOperand ( 1 ) . getMBB ( ) ; TBB = TargetBB ; Cond . push_back ( MI . getOperand ( 0 ) ) ; HasCondBranch = true ; } } return false ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> static rtx ix86_expand_sse_round ( const struct builtin_description * d , tree exp , rtx target ) { rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , 0 ) ; rtx op1 , op0 = expand_normal ( arg0 ) ; machine_mode tmode = insn_data [ d -> icode ] . operand [ 0 ] . mode ; machine_mode mode0 = insn_data [ d -> icode ] . operand [ 1 ] . mode ; if ( optimize || target == 0 || GET_MODE ( target ) != tmode || ! insn_data [ d -> icode ] . operand [ 0 ] . predicate ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! insn_data [ d -> icode ] . operand [ 0 ] . predicate ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; op1 = GEN_INT ( d -> comparison ) ; pat = GEN_FCN ( d -> icode ) ( target , op0 , op1 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>

Subroutines of ix86_expand_args_builtin to take care of round insns .


<s> TargetPassConfig * Z80TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new Z80PassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> bool X86PassConfig :: addILPOpts ( ) { if ( X86EarlyIfConv && getX86Subtarget ( ) . hasCMov ( ) ) { addPass ( & EarlyIfConverterID ) ; return true ; } return false ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .


<s> int MipsSEFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; if ( MFI -> isFixedObjectIndex ( FI ) ) FrameReg = hasFP ( MF ) ? ABI . GetFramePtr ( ) : ABI . GetStackPtr ( ) ; else FrameReg = hasBP ( MF ) ? ABI . GetBasePtr ( ) : ABI . GetStackPtr ( ) ; return MFI -> getObjectOffset ( FI ) + MFI -> getStackSize ( ) - getOffsetOfLocalArea ( ) + MFI -> getOffsetAdjustment ( ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> unsigned getMinPrefetchStride ( ) const { return MinPrefetchStride ; } </s>

Some HW prefetchers can handle accesses up to a certain constant stride .


<s> bool ix86_check_movabs ( rtx insn , int opnum ) { rtx set , mem ; set = PATTERN ( insn ) ; if ( GET_CODE ( set ) == PARALLEL ) set = XVECEXP ( set , 0 , 0 ) ; gcc_assert ( GET_CODE ( set ) == SET ) ; mem = XEXP ( set , opnum ) ; while ( SUBREG_P ( mem ) ) mem = SUBREG_REG ( mem ) ; gcc_assert ( MEM_P ( mem ) ) ; return volatile_ok || ! MEM_VOLATILE_P ( mem ) ; } </s>

Return nonzero if OPNUM 's MEM should be matched in movabs * patterns .


<s> rtx sh_load_function_descriptor ( rtx funcdesc ) { rtx r1 = gen_rtx_REG ( Pmode , R1_REG ) ; rtx pic_reg = gen_rtx_REG ( Pmode , PIC_REG ) ; rtx fnaddr = gen_rtx_MEM ( Pmode , funcdesc ) ; rtx gotaddr = gen_rtx_MEM ( Pmode , plus_constant ( Pmode , funcdesc , 4 ) ) ; emit_move_insn ( r1 , fnaddr ) ; emit_insn ( gen_blockage ( ) ) ; emit_move_insn ( pic_reg , gotaddr ) ; return r1 ; } </s>

Emit insns to load the function address from FUNCDESC ( an FDPIC function descriptor ) into r1 and the GOT address into r12 , returning an rtx for r1 .


<s> static rtx find_alignment_op ( rtx_insn * insn , rtx base_reg ) { df_ref base_use ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; rtx and_operation = 0 ; FOR_EACH_INSN_INFO_USE ( base_use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( base_use ) , base_reg ) ) continue ; struct df_link * base_def_link = DF_REF_CHAIN ( base_use ) ; if ( ! base_def_link || base_def_link -> next ) break ; if ( DF_REF_IS_ARTIFICIAL ( base_def_link -> ref ) ) break ; rtx_insn * and_insn = DF_REF_INSN ( base_def_link -> ref ) ; and_operation = alignment_mask ( and_insn ) ; if ( and_operation != 0 ) break ; } return and_operation ; } </s>

Given INSN that 's a load or store based at BASE_REG , check if all of its feeding computations align its address on a 16-byte boundary . If so , return true and add all definition insns into AND_INSNS and their corresponding fully-expanded rtxes for the masking operations into AND_OPS .


<s> inline bool registered_function_hasher :: equal ( value_type value , const compare_type & key ) { return value -> instance == key ; } </s>


<s> void SystemZAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { SystemZMCInstLower Lower ( MF -> getContext ( ) , * this ) ; MCInst LoweredMI ; switch ( MI -> getOpcode ( ) ) { case SystemZ :: Return : LoweredMI = MCInstBuilder ( SystemZ :: BR ) . addReg ( SystemZ :: R14D ) ; break ; case SystemZ :: CallBRASL : LoweredMI = MCInstBuilder ( SystemZ :: BRASL ) . addReg ( SystemZ :: R14D ) . addExpr ( Lower . getExpr ( MI -> getOperand ( 0 ) , MCSymbolRefExpr :: VK_PLT ) ) ; break ; case SystemZ :: CallBASR : LoweredMI = MCInstBuilder ( SystemZ :: BASR ) . addReg ( SystemZ :: R14D ) . addReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ; break ; case SystemZ :: CallJG : LoweredMI = MCInstBuilder ( SystemZ :: JG ) . addExpr ( Lower . getExpr ( MI -> getOperand ( 0 ) , MCSymbolRefExpr :: VK_PLT ) ) ; break ; case SystemZ :: CallBR : LoweredMI = MCInstBuilder ( SystemZ :: BR ) . addReg ( SystemZ :: R1D ) ; break ; case SystemZ :: IILF64 : LoweredMI = MCInstBuilder ( SystemZ :: IILF ) . addReg ( SystemZMC :: getRegAsGR32 ( MI -> getOperand ( 0 ) . getReg ( ) ) ) . addImm ( MI -> getOperand ( 2 ) . getImm ( ) ) ; break ; case SystemZ :: IIHF64 : LoweredMI = MCInstBuilder ( SystemZ :: IIHF ) . addReg ( SystemZMC :: getRegAsGRH32 ( MI -> getOperand ( 0 ) . getReg ( ) ) ) . addImm ( MI -> getOperand ( 2 ) . getImm ( ) ) ; break ; case SystemZ :: RISBHH : case SystemZ :: RISBHL : LoweredMI = lowerRIEfLow ( MI , SystemZ :: RISBHG ) ; break ; case SystemZ :: RISBLH : case SystemZ :: RISBLL : LoweredMI = lowerRIEfLow ( MI , SystemZ :: RISBLG ) ; break ; case SystemZ :: NAME ## 64 : LoweredMI = lowerRILow ( MI , SystemZ :: NAME ) ; break LOWER_LOW ( IILL ) ; LOWER_LOW ( IILH ) ; LOWER_LOW ( TMLL ) ; LOWER_LOW ( TMLH ) ; LOWER_LOW ( NILL ) ; LOWER_LOW ( NILH ) ; LOWER_LOW ( NILF ) ; LOWER_LOW ( OILL ) ; LOWER_LOW ( OILH ) ; LOWER_LOW ( OILF ) ; LOWER_LOW ( XILF ) ; case SystemZ :: NAME ## 64 : LoweredMI = lowerRIHigh ( MI , SystemZ :: NAME ) ; break LOWER_HIGH ( IIHL ) ; LOWER_HIGH ( IIHH ) ; LOWER_HIGH ( TMHL ) ; LOWER_HIGH ( TMHH ) ; LOWER_HIGH ( NIHL ) ; LOWER_HIGH ( NIHH ) ; LOWER_HIGH ( NIHF ) ; LOWER_HIGH ( OIHL ) ; LOWER_HIGH ( OIHH ) ; LOWER_HIGH ( OIHF ) ; LOWER_HIGH ( XIHF ) ; default : Lower . lower ( MI , LoweredMI ) ; break ; } OutStreamer . EmitInstruction ( LoweredMI ) ; } </s>


<s> bool WebAssemblyTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { switch ( Intrinsic ) { case Intrinsic :: wasm_memory_atomic_notify : Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: i32 ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . align = Align ( 4 ) ; Info . flags = MachineMemOperand :: MOVolatile | MachineMemOperand :: MOLoad ; return true ; case Intrinsic :: wasm_memory_atomic_wait32 : Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: i32 ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . align = Align ( 4 ) ; Info . flags = MachineMemOperand :: MOVolatile | MachineMemOperand :: MOLoad ; return true ; case Intrinsic :: wasm_memory_atomic_wait64 : Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: i64 ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . align = Align ( 8 ) ; Info . flags = MachineMemOperand :: MOVolatile | MachineMemOperand :: MOLoad ; return true ; default : return false ; } } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> static int avr_register_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t from , reg_class_t to ) { return ( from == STACK_REG ? 6 : to == STACK_REG ? 12 : 2 ) ; } </s>


<s> static int arc_arg_partial_bytes ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int bytes = arg . promoted_size_in_bytes ( ) ; int words = ( bytes + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; int arg_num = * cum ; int ret ; arg_num = ROUND_ADVANCE_CUM ( arg_num , arg . mode , arg . type ) ; ret = GPR_REST_ARG_REGS ( arg_num ) ; ret = ( ret >= words ? 0 : ret * UNITS_PER_WORD ) ; return ret ; } </s>


<s> void PPCPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { initializePPCVSXFMAMutatePass ( * PassRegistry :: getPassRegistry ( ) ) ; insertPass ( VSXFMAMutateEarly ? & RegisterCoalescerID : & MachineSchedulerID , & PPCVSXFMAMutateID ) ; } if ( getPPCTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) { addPass ( & LiveVariablesID , false ) ; addPass ( createPPCTLSDynamicCallPass ( ) ) ; } if ( EnableExtraTOCRegDeps ) addPass ( createPPCTOCRegDepsPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


"MMIX Internal: %s is not a shiftable int"

Print the presumed shiftable wyde argument shifted into place ( to be output with an operand ) .


<s> static bool riscv_canonicalize_int_order_test ( enum rtx_code * code , rtx * cmp1 , machine_mode mode ) { HOST_WIDE_INT plus_one ; if ( riscv_int_order_operand_ok_p ( * code , * cmp1 ) ) return true ; if ( CONST_INT_P ( * cmp1 ) ) switch ( * code ) { case LE : plus_one = trunc_int_for_mode ( UINTVAL ( * cmp1 ) + 1 , mode ) ; if ( INTVAL ( * cmp1 ) < plus_one ) { * code = LT ; * cmp1 = force_reg ( mode , GEN_INT ( plus_one ) ) ; return true ; } break ; case LEU : plus_one = trunc_int_for_mode ( UINTVAL ( * cmp1 ) + 1 , mode ) ; if ( plus_one != 0 ) { * code = LTU ; * cmp1 = force_reg ( mode , GEN_INT ( plus_one ) ) ; return true ; } break ; default : break ; } return false ; } </s>

Return true if * CMP1 ( of mode MODE ) is a valid second operand for integer ordering test * CODE , or if an equivalent combination can be formed by adjusting * CODE and * CMP1 . When returning true , update * CODE and * CMP1 with the chosen code and operand , otherwise leave them alone .


"Unrecognized Hexagon processor version"

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> static rtx csky_legitimize_address ( rtx x , rtx orig_x ATTRIBUTE_UNUSED , machine_mode mode ) { if ( csky_tls_symbol_p ( x ) ) return csky_legitimize_tls_address ( x , NULL_RTX ) ; if ( GET_CODE ( x ) == PLUS ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; if ( is_csky_address_register_rtx_p ( xop0 , 0 ) && CONST_INT_P ( xop1 ) ) { HOST_WIDE_INT offset = INTVAL ( xop1 ) ; if ( optimize_size && offset > CSKY_LD16_MAX_OFFSET ( mode ) && offset <= ( CSKY_ADDI16_MAX_IMM + CSKY_LD16_MAX_OFFSET ( mode ) ) ) { HOST_WIDE_INT new_ld_offset = offset & CSKY_LD16_OFFSET_MASK ( mode ) ; xop0 = force_operand ( plus_constant ( Pmode , xop0 , offset - new_ld_offset ) , NULL_RTX ) ; x = plus_constant ( Pmode , xop0 , new_ld_offset ) ; } else if ( offset < 0 && offset >= ( - CSKY_SUBI16_MAX_IMM ) ) x = force_operand ( x , NULL_RTX ) ; else if ( offset > CSKY_LD16_MAX_OFFSET ( mode ) || offset < 0 ) { xop1 = force_reg ( SImode , xop1 ) ; x = gen_rtx_PLUS ( SImode , xop0 , xop1 ) ; } } if ( is_csky_address_register_rtx_p ( xop1 , 0 ) && ! is_csky_address_register_rtx_p ( xop0 , 0 ) ) { xop0 = force_operand ( xop0 , NULL_RTX ) ; x = gen_rtx_PLUS ( SImode , xop0 , xop1 ) ; } } else if ( CONST_INT_P ( x ) && optimize > 0 ) { HOST_WIDE_INT mask , base , index ; rtx base_reg ; mask = CSKY_LD16_OFFSET_MASK ( mode ) ; base = INTVAL ( x ) & ~ mask ; index = INTVAL ( x ) & mask ; base_reg = force_reg ( SImode , GEN_INT ( base ) ) ; x = plus_constant ( Pmode , base_reg , index ) ; } return x ; } </s>


<s> bool PatmosLatencyQueue :: empty ( ) { return AvailableQueue . empty ( ) && PendingQueue . empty ( ) ; } </s>

Determine whether this version information is empty ( e.g. , all version components are zero ) .


<s> bool needAddressOf ( ) const override { return AddressOf ; } </s>

needAddressOf - Do we need to emit code to get the address of the variable/label ? Only valid when parsing MS-style inline assembly .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"ARM Instruction Selection"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static int m68k_sched_adjust_cost ( rtx_insn * insn , int , rtx_insn * def_insn , int cost , unsigned int ) { int delay ; if ( recog_memoized ( def_insn ) < 0 || recog_memoized ( insn ) < 0 ) return cost ; if ( sched_cfv4_bypass_data . scale == 1 ) { gcc_assert ( sched_cfv4_bypass_data . pro == def_insn && sched_cfv4_bypass_data . con == insn ) ; if ( cost < 3 ) cost = 3 ; sched_cfv4_bypass_data . pro = NULL ; sched_cfv4_bypass_data . con = NULL ; sched_cfv4_bypass_data . scale = 0 ; } else gcc_assert ( sched_cfv4_bypass_data . pro == NULL && sched_cfv4_bypass_data . con == NULL && sched_cfv4_bypass_data . scale == 0 ) ; delay = min_insn_conflict_delay ( sched_adjust_cost_state , def_insn , insn ) ; if ( delay > cost ) cost = delay ; return cost ; } </s>

Implement adjust_cost scheduler hook . Return adjusted COST of dependency LINK between DEF_INSN and INSN .


<s>
bool
HexagonPassConfig
::
addPreSched2
(
)
{
const
HexagonTargetMachine
&
TM
=
getHexagonTargetMachine
(
)
;
const
HexagonTargetObjectFile
&
TLOF
=
(
const
HexagonTargetObjectFile
&
)
getTargetLowering
(
)
->
getObjFileLowering
(
)
;
addPass
(
createHexagonCopyToCombine
(
)
)
;
if
(
getOptLevel
(
)
!=
CodeGenOpt
::
)
addPass
(
&
IfConverterID
)
;
if
(
!
TLOF
.
IsSmallDataEnabled
(
)
)
{
addPass
(
createHexagonSplitConst32AndConst64
(
TM
)
)
;
printAndVerify
(
"After hexagon split const32/64 pass"
)
;
}
return
true
;
}
</s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .

Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
"After hexagon split const32/64 pass"


<s> void SystemZTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { if ( Constraint . length ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'I' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isUInt < 8 > ( C -> getZExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ) ; return ; case 'J' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isUInt < 12 > ( C -> getZExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ) ; return ; case 'K' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isInt < 16 > ( C -> getSExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ) ; return ; case 'L' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isInt < 20 > ( C -> getSExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ) ; return ; case 'M' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( C -> getZExtValue ( ) == 0x7fffffff ) Ops . push_back ( DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ) ; return ; } } TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; } </s>

Lower the specified operand into the Ops vector .


"There are no defined alternate asm variants"

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> void AMDGPUInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << RegNo ; } </s>


<s> bool isToken ( ) const override { return Kind == k_Tok ; } </s>


<s> int ARMTTIImpl :: getIntrinsicInstrCost ( const IntrinsicCostAttributes & ICA , TTI :: TargetCostKind CostKind ) { switch ( ICA . getID ( ) ) { case Intrinsic :: get_active_lane_mask : if ( ST -> hasMVEIntegerOps ( ) ) return 0 ; break ; case Intrinsic :: sadd_sat : case Intrinsic :: ssub_sat : case Intrinsic :: uadd_sat : case Intrinsic :: usub_sat : { if ( ! ST -> hasMVEIntegerOps ( ) ) break ; Type * VT = ICA . getReturnType ( ) ; if ( ! VT -> isVectorTy ( ) && ! ICA . getVectorFactor ( ) . isScalar ( ) ) VT = VectorType :: get ( VT , ICA . getVectorFactor ( ) ) ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , VT ) ; if ( LT . second == MVT :: v4i32 || LT . second == MVT :: v8i16 || LT . second == MVT :: v16i8 ) { unsigned Instrs = LT . second . getScalarSizeInBits ( ) == ICA . getReturnType ( ) -> getScalarSizeInBits ( ) ? 1 : 4 ; return LT . first * ST -> getMVEVectorCostFactor ( ) * Instrs ; } break ; } } return BaseT :: getIntrinsicInstrCost ( ICA , CostKind ) ; } </s>


<s> static const char * mips_get_compress_on_name ( unsigned int flags ) { if ( flags == MASK_MIPS16 ) return "mips16" ; return "micromips" ; } </s>

Return the attribute name associated with MASK_MIPS16 and MASK_MICROMIPS flags FLAGS .


<s>
SDValue
AMDGPUTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
Op
.
getNode
(
)
->
dump
(
)
;
llvm_unreachable
(
"Custom lowering code for this"
"instruction is not implemented yet!"
)
;
break
;
case
ISD
::
SIGN_EXTEND_INREG
:
return
LowerSIGN_EXTEND_INREG
(
Op
,
DAG
)
;
case
ISD
::
CONCAT_VECTORS
:
return
LowerCONCAT_VECTORS
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_SUBVECTOR
:
return
LowerEXTRACT_SUBVECTOR
(
Op
,
DAG
)
;
case
ISD
::
FrameIndex
:
return
LowerFrameIndex
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
UDIVREM
:
return
LowerUDIVREM
(
Op
,
DAG
)
;
case
ISD
::
SDIVREM
:
return
LowerSDIVREM
(
Op
,
DAG
)
;
case
ISD
::
FCEIL
:
return
LowerFCEIL
(
Op
,
DAG
)
;
case
ISD
::
FTRUNC
:
return
LowerFTRUNC
(
Op
,
DAG
)
;
case
ISD
::
FRINT
:
return
LowerFRINT
(
Op
,
DAG
)
;
case
ISD
::
FNEARBYINT
:
return
LowerFNEARBYINT
(
Op
,
DAG
)
;
case
ISD
::
FFLOOR
:
return
LowerFFLOOR
(
Op
,
DAG
)
;
case
ISD
::
UINT_TO_FP
:
return
LowerUINT_TO_FP
(
Op
,
DAG
)
;
}
return
Op
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

R600
"Custom lowering code for this"
"instruction is not implemented yet!"
ISD::SIGN_EXTEND_INREG
SI
ISD::CONCAT_VECTORS
ISD::EXTRACT_SUBVECTOR
ISD::FrameIndex
ISD::INTRINSIC_WO_CHAIN
SI
ISD::UDIVREM
ISD::SDIVREM
ISD::FCEIL
ISD::FTRUNC
ISD::FRINT
ISD::FNEARBYINT
ISD::FFLOOR
ISD::UINT_TO_FP


<s>
void
MSP430InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
;
if
(
MSP430
::
GR16RegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
MSP430
::
MOV16rr
;
else
if
(
MSP430
::
GR8RegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
MSP430
::
MOV8rr
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


"AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "


ARCTargetMachine ctor - Create an ILP32 architecture model .


<s> bool ARMBaseInstrInfo :: produceSameValue ( const MachineInstr * MI0 , const MachineInstr * MI1 ) const { int Opcode = MI0 -> getOpcode ( ) ; if ( Opcode == ARM :: t2LDRpci || Opcode == ARM :: t2LDRpci_pic || Opcode == ARM :: tLDRpci || Opcode == ARM :: tLDRpci_pic ) { if ( MI1 -> getOpcode ( ) != Opcode ) return false ; if ( MI0 -> getNumOperands ( ) != MI1 -> getNumOperands ( ) ) return false ; const MachineOperand & MO0 = MI0 -> getOperand ( 1 ) ; const MachineOperand & MO1 = MI1 -> getOperand ( 1 ) ; if ( MO0 . getOffset ( ) != MO1 . getOffset ( ) ) return false ; const MachineFunction * MF = MI0 -> getParent ( ) -> getParent ( ) ; const MachineConstantPool * MCP = MF -> getConstantPool ( ) ; int CPI0 = MO0 . getIndex ( ) ; int CPI1 = MO1 . getIndex ( ) ; const MachineConstantPoolEntry & MCPE0 = MCP -> getConstants ( ) [ CPI0 ] ; const MachineConstantPoolEntry & MCPE1 = MCP -> getConstants ( ) [ CPI1 ] ; ARMConstantPoolValue * ACPV0 = static_cast < ARMConstantPoolValue * > ( MCPE0 . Val . MachineCPVal ) ; ARMConstantPoolValue * ACPV1 = static_cast < ARMConstantPoolValue * > ( MCPE1 . Val . MachineCPVal ) ; return ACPV0 -> hasSameValue ( ACPV1 ) ; } return MI0 -> isIdenticalTo ( MI1 , MachineInstr :: IgnoreVRegDefs ) ; } </s>

Return true if two machine instructions would produce identical values .


<s> int aarch64_simd_attr_length_rglist ( enum machine_mode mode ) { return ( GET_MODE_SIZE ( mode ) / UNITS_PER_VREG ) * 4 ; } </s>

Compute and return the length of aarch64_simd_reglist < mode > , where < mode > is one of VSTRUCT modes : OI , CI , EI , or XI .


<s> void or1k_expand_eh_return ( rtx eh_addr ) { rtx lraddr ; lraddr = gen_frame_mem ( Pmode , plus_constant ( Pmode , arg_pointer_rtx , - UNITS_PER_WORD ) ) ; MEM_VOLATILE_P ( lraddr ) = true ; emit_move_insn ( lraddr , eh_addr ) ; } </s>

Expand the `` eh_return '' pattern . Used for defining __builtin_eh_return , this will emit RTX to override the current function 's return address stored on the stack . The emitted RTX is inserted before the epilogue so we ca n't just update the link register . This is used when handling exceptions to jump into the exception handler catch block upon return from _Unwind_RaiseException .


<s> SDValue JVMTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { return SDValue ( N , 0 ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> static void nvptx_init_builtins ( void ) { ( nvptx_builtin_decls [ NVPTX_BUILTIN_ ## ID ] \ = add_builtin_function ( "__builtin_nvptx_" NAME , \ build_function_type_list T , \ NVPTX_BUILTIN_ ## ID , BUILT_IN_MD , NULL , NULL ) ) DEF ( SHUFFLE , "shuffle" , ( UINT , UINT , UINT , UINT , NULL_TREE ) ) ; DEF ( SHUFFLELL , "shufflell" , ( LLUINT , LLUINT , UINT , UINT , NULL_TREE ) ) ; DEF ( WORKER_ADDR , "worker_addr" , ( PTRVOID , ST , UINT , UINT , NULL_TREE ) ) ; DEF ( CMP_SWAP , "cmp_swap" , ( UINT , PTRVOID , UINT , UINT , NULL_TREE ) ) ; DEF ( CMP_SWAPLL , "cmp_swapll" , ( LLUINT , PTRVOID , LLUINT , LLUINT , NULL_TREE ) ) ; } </s>

Set up all builtin functions for this target .


<s>
static
void
mmix_asm_trampoline_template
(
FILE
*
stream
)
{
fprintf
(
stream
,
"\tGETA $255,1F\n\t"
)
;
fprintf
(
stream
,
"LDOU %s,$255,0\n\t"
,
reg_names
[
MMIX_STATIC_CHAIN_REGNUM
]
)
;
fprintf
(
stream
,
"LDOU $255,$255,8\n\t"
)
;
fprintf
(
stream
,
"GO $255,$255,0\n"
)
;
fprintf
(
stream
,
"1H\tOCTA 0\n\t"
)
;
fprintf
(
stream
,
"OCTA 0\n"
)
;
}
</s>


<s>
static
void
process_args
(
int
argc
,
char
*
*
argv
)
{
int
i
;
for
(
i
=
1
;
i
<
argc
;
i
++
)
{
if
(
startswith
(
argv
[
i
]
,
"-L"
)
)
{
search_dirs
=
XRESIZEVEC
(
const
char
*
,
search_dirs
,
search_dirs_len
+
1
)
;
search_dirs
[
search_dirs_len
++
]
=
&
argv
[
i
]
[
2
]
;
}
else
if
(
strcmp
(
argv
[
i
]
,
"-v"
)
==
0
)
verbose
++
;
else
if
(
strcmp
(
argv
[
i
]
,
"--version"
)
==
0
)
{
fprintf
(
stdout
,
"VMS Linker\n"
)
;
exit
(
EXIT_SUCCESS
)
;
}
else
if
(
strcmp
(
argv
[
i
]
,
"--help"
)
==
0
)
{
fprintf
(
stdout
,
"VMS Linker\n"
)
;
exit
(
EXIT_SUCCESS
)
;
}
else
if
(
strcmp
(
argv
[
i
]
,
"-g0"
)
==
0
)
addarg
(
"/notraceback"
)
;
else
if
(
startswith
(
argv
[
i
]
,
"-g"
)
)
{
addarg
(
"/debug"
)
;
debug
=
1
;
}
else
if
(
strcmp
(
argv
[
i
]
,
"-static"
)
==
0
)
staticp
=
1
;
else
if
(
strcmp
(
argv
[
i
]
,
"-map"
)
==
0
)
{
char
*
buff
,
*
ptr
;
buff
=
(
char
*
)
xstrdup
(
exefullfilename
)
;
ptr
=
strrchr
(
buff
,
'.'
)
;
if
(
ptr
)
*
ptr
=
0
;
strcat
(
buff
,
".map"
)
;
addarg
(
"/map="
)
;
addarg
(
buff
)
;
addarg
(
".map"
)
;
addarg
(
"/full"
)
;
free
(
buff
)
;
}
else
if
(
strcmp
(
argv
[
i
]
,
"-save-temps"
)
==
0
)
save_temps
=
1
;
else
if
(
strcmp
(
argv
[
i
]
,
"--noinhibit-exec"
)
==
0
)
inhibit_exec
=
0
;
}
}
</s>

Preprocess the number of args ARGC in ARGV . Look for special flags , etc . that must be handled for the VMS linker .


<s> int ARMBaseInstrInfo :: getInstrLatency ( const InstrItineraryData * ItinData , const MachineInstr * MI , unsigned * PredCost ) const { if ( MI -> isCopyLike ( ) || MI -> isInsertSubreg ( ) || MI -> isRegSequence ( ) || MI -> isImplicitDef ( ) ) return 1 ; if ( ! ItinData || ItinData -> isEmpty ( ) ) return 1 ; if ( MI -> isBundle ( ) ) { int Latency = 0 ; MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; while ( ++ I != E && I -> isInsideBundle ( ) ) { if ( I -> getOpcode ( ) != ARM :: t2IT ) Latency += getInstrLatency ( ItinData , I , PredCost ) ; } return Latency ; } const MCInstrDesc & MCID = MI -> getDesc ( ) ; unsigned Class = MCID . getSchedClass ( ) ; unsigned UOps = ItinData -> Itineraries [ Class ] . NumMicroOps ; if ( PredCost && MCID . hasImplicitDefOfPhysReg ( ARM :: CPSR ) ) * PredCost = 1 ; if ( UOps ) return ItinData -> getStageLatency ( Class ) ; return getNumMicroOps ( ItinData , MI ) ; } </s>

Compute the instruction latency of a given instruction .


<s>
void
AArch64RegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected"
)
;
MachineInstr
&
MI
=
*
II
;
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
AArch64InstrInfo
*
TII
=
MF
.
getSubtarget
<
AArch64Subtarget
>
(
)
.
getInstrInfo
(
)
;
const
AArch64FrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
unsigned
FrameReg
;
int
Offset
;
if
(
MI
.
isDebugValue
(
)
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
STACKMAP
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
PATCHPOINT
)
{
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
,
true
,
false
)
;
Offset
+=
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
)
;
return
;
}
if
(
MI
.
getOpcode
(
)
==
TargetOpcode
::
LOCAL_ESCAPE
)
{
MachineOperand
&
FI
=
MI
.
getOperand
(
FIOperandNum
)
;
Offset
=
TFI
->
getNonLocalFrameIndexReference
(
MF
,
FrameIndex
)
;
FI
.
ChangeToImmediate
(
Offset
)
;
return
;
}
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
,
false
,
true
)
;
if
(
rewriteAArch64FrameIndex
(
MI
,
FIOperandNum
,
FrameReg
,
Offset
,
TII
)
)
return
;
assert
(
(
!
RS
||
!
RS
->
isScavengingFrameIndex
(
FrameIndex
)
)
&&
"Emergency spill slot is out of reach"
)
;
unsigned
ScratchReg
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
&
AArch64
::
GPR64RegClass
)
;
emitFrameOffset
(
MBB
,
II
,
MI
.
getDebugLoc
(
)
,
ScratchReg
,
FrameReg
,
Offset
,
TII
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
ScratchReg
,
false
,
false
,
true
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s>
void
F2003fMCAsmStreamer
::
emitFill
(
const
MCExpr
&
NumValues
,
int64_t
Size
,
int64_t
Expr
,
SMLoc
Loc
)
{
llvm_unreachable
(
"2003lk doesn't support this directive"
)
;
}
</s>

Emit Size bytes worth of the value specified by FillValue .


<s> void NVPTXPassConfig :: addIRPasses ( ) { disablePass ( & PrologEpilogCodeInserterID ) ; disablePass ( & MachineCopyPropagationID ) ; disablePass ( & TailDuplicateID ) ; disablePass ( & StackMapLivenessID ) ; disablePass ( & LiveDebugValuesID ) ; disablePass ( & PostRAMachineSinkingID ) ; disablePass ( & PostRASchedulerID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & PatchableFunctionID ) ; disablePass ( & ShrinkWrapID ) ; addPass ( createNVVMReflectPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createNVPTXImageOptimizerPass ( ) ) ; addPass ( createNVPTXAssignValidGlobalNamesPass ( ) ) ; addPass ( createGenericToNVVMPass ( ) ) ; addPass ( createNVPTXLowerArgsPass ( & getNVPTXTargetMachine ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addAddressSpaceInferencePasses ( ) ; if ( ! DisableLoadStoreVectorizer ) addPass ( createLoadStoreVectorizerPass ( ) ) ; addStraightLineScalarOptimizationPasses ( ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addEarlyCSEOrGVNPass ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static FunctionType * getType ( LLVMContext & Context , unsigned id ) { Type * ResultTy = NULL ; std :: vector < Type * > ArgTys ; bool IsVarArg = false ; return FunctionType :: get ( ResultTy , ArgTys , IsVarArg ) ; } </s>

Overload to return most specific vector type .


<s> static void s390_chunkify_cancel ( struct constant_pool * pool_list ) { struct constant_pool * curr_pool = NULL ; rtx insn ; for ( curr_pool = pool_list ; curr_pool ; curr_pool = curr_pool -> next ) { rtx barrier = PREV_INSN ( curr_pool -> pool_insn ) ; rtx jump = barrier ? PREV_INSN ( barrier ) : NULL_RTX ; rtx label = NEXT_INSN ( curr_pool -> pool_insn ) ; if ( jump && GET_CODE ( jump ) == JUMP_INSN && barrier && GET_CODE ( barrier ) == BARRIER && label && GET_CODE ( label ) == CODE_LABEL && GET_CODE ( PATTERN ( jump ) ) == SET && SET_DEST ( PATTERN ( jump ) ) == pc_rtx && GET_CODE ( SET_SRC ( PATTERN ( jump ) ) ) == LABEL_REF && XEXP ( SET_SRC ( PATTERN ( jump ) ) , 0 ) == label ) { remove_insn ( jump ) ; remove_insn ( barrier ) ; remove_insn ( label ) ; } remove_insn ( curr_pool -> pool_insn ) ; } for ( insn = get_insns ( ) ; insn ; ) { rtx next_insn = NEXT_INSN ( insn ) ; if ( GET_CODE ( insn ) == INSN && GET_CODE ( PATTERN ( insn ) ) == SET && GET_CODE ( SET_SRC ( PATTERN ( insn ) ) ) == UNSPEC && XINT ( SET_SRC ( PATTERN ( insn ) ) , 1 ) == UNSPEC_RELOAD_BASE ) remove_insn ( insn ) ; insn = next_insn ; } while ( pool_list ) { struct constant_pool * next = pool_list -> next ; s390_free_pool ( pool_list ) ; pool_list = next ; } } </s>

POOL_LIST is a chunk list as prepared by s390_chunkify_start . We have decided we can not use this list , so revert all changes to the current function that were done by s390_chunkify_start .


<s> llvm :: FastISel * ARM :: createFastISel ( FunctionLoweringInfo & funcInfo ) { const TargetMachine & TM = funcInfo . MF -> getTarget ( ) ; const ARMSubtarget * Subtarget = & TM . getSubtarget < ARMSubtarget > ( ) ; if ( Subtarget -> isTargetIOS ( ) && ! Subtarget -> isThumb1Only ( ) && ! DisableARMFastISel ) return new ARMFastISel ( funcInfo ) ; return 0 ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .

ARM ARM::createFastISel ARM ARM ARM ARM 0


<s> bool AArch64TargetLowering :: allowsMisalignedMemoryAccesses ( LLT Ty , unsigned AddrSpace , unsigned Align , MachineMemOperand :: Flags Flags , bool * Fast ) const { if ( Subtarget -> requiresStrictAlign ( ) ) return false ; if ( Fast ) { * Fast = ! Subtarget -> isMisaligned128StoreSlow ( ) || Ty . getSizeInBytes ( ) != 16 || Align <= 2 || Ty == LLT :: vector ( 2 , 64 ) ; } return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> bool RISCVFrameLowering :: hasFP ( const MachineFunction & MF ) const { return true ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool X86TargetLowering :: decomposeMulByConstant ( EVT VT , SDValue C ) const { APInt MulC ; if ( ! ISD :: isConstantSplatVector ( C . getNode ( ) , MulC ) ) return false ; if ( isOperationLegal ( ISD :: MUL , VT ) ) return false ; return ( MulC + 1 ) . isPowerOf2 ( ) || ( MulC - 1 ) . isPowerOf2 ( ) || ( 1 - MulC ) . isPowerOf2 ( ) || ( - ( MulC + 1 ) ) . isPowerOf2 ( ) ; } </s>

Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds .


<s> void VEDAGToDAGISel :: Select ( SDNode * N ) { SDLoc dl ( N ) ; if ( N -> isMachineOpcode ( ) ) { N -> setNodeId ( - 1 ) ; return ; } switch ( N -> getOpcode ( ) ) { case VEISD :: GLOBAL_BASE_REG : ReplaceNode ( N , getGlobalBaseReg ( ) ) ; return ; } SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


"********** ARM MVE VPT Optimisations **********\n"

runOnMachineFunction - Emit the function body .


<s> bool OR1KDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintID ) { default : return true ; case InlineAsm :: Constraint_m : if ( ! SelectAddr ( Op , Op0 , Op1 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> bool AArch64FrameLowering :: canUseRedZone ( const MachineFunction & MF ) const { if ( ! EnableRedZone ) return false ; if ( MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoRedZone ) ) return false ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const AArch64FunctionInfo * AFI = MF . getInfo < AArch64FunctionInfo > ( ) ; unsigned NumBytes = AFI -> getLocalStackSize ( ) ; if ( MFI -> hasCalls ( ) || hasFP ( MF ) || NumBytes > 128 ) return false ; return true ; } </s>

Can this function use the red zone for local allocations .


<s> int csky_register_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t from , reg_class_t to ) { ( ( CLASS ) == GENERAL_REGS || ( CLASS ) == MINI_REGS || ( CLASS ) == SP_REGS \ || ( CLASS ) == LOW_REGS ) ( ( CLASS ) == HILO_REGS ) ( ( CLASS ) == V_REGS ) if ( V_REG_CLASS_P ( from ) && V_REG_CLASS_P ( to ) ) return 2 ; if ( ( V_REG_CLASS_P ( from ) && GR_REG_CLASS_P ( to ) ) || ( GR_REG_CLASS_P ( from ) && V_REG_CLASS_P ( to ) ) ) return 6 ; if ( ( HILO_REG_CLASS_P ( from ) && GR_REG_CLASS_P ( to ) ) || ( GR_REG_CLASS_P ( from ) && HILO_REG_CLASS_P ( to ) ) ) return 16 ; if ( HILO_REG_CLASS_P ( from ) && HILO_REG_CLASS_P ( to ) ) return 32 ; if ( ( HILO_REG_CLASS_P ( from ) && V_REG_CLASS_P ( to ) ) || ( V_REG_CLASS_P ( from ) && HILO_REG_CLASS_P ( to ) ) ) return 64 ; return 2 ; } </s>

Implement TARGET_REGISTER_MOVE_COST : compute extra cost of moving data between one register class and another .


<s> void Z80AsmPrinter :: emitInlineAsmEnd ( const MCSubtargetInfo & StartInfo , const MCSubtargetInfo * EndInfo ) const { if ( TM . getTargetTriple ( ) . getArch ( ) != Triple :: ez80 ) return ; bool Was16 = isCode16 ( StartInfo . getTargetTriple ( ) ) ; if ( ! EndInfo || Was16 != isCode16 ( EndInfo -> getTargetTriple ( ) ) ) OutStreamer -> EmitAssemblerFlag ( Was16 ? MCAF_Code16 : MCAF_Code24 ) ; } </s>

Let the target do anything it needs to do after emitting inlineasm .


<s> bool SystemZMCAsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const { Value = extractBitsForFixup ( Fixup . getKind ( ) , Value ) ; return ( int16_t ) Value != ( int64_t ) Value ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> GBSectionType getType ( ) const { return Type ; } </s>


<s> bool P2AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , const char * ExtraCode , raw_ostream & O ) { bool Error = AsmPrinter :: PrintAsmOperand ( MI , OpNum , ExtraCode , O ) ; const MachineOperand & MO = MI -> getOperand ( OpNum ) ; if ( Error && ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { case '#' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << "#" << MO . getImm ( ) ; return false ; } } if ( Error ) printOperand ( MI , OpNum , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s>
char
*
output_cbranch
(
rtx
op
,
const
char
*
label
,
int
reversed
,
rtx_insn
*
insn
)
{
static
char
string
[
64
]
;
enum
rtx_code
code
=
GET_CODE
(
op
)
;
rtx
cc_reg
=
XEXP
(
op
,
0
)
;
machine_mode
mode
=
GET_MODE
(
cc_reg
)
;
int
cc_regno
=
REGNO
(
cc_reg
)
CR0_REGNO
;
int
need_longbranch
=
label
!=
&&
get_attr_length
(
insn
)
==
8
;
int
really_reversed
=
reversed
^
need_longbranch
;
char
*
s
=
string
;
const
char
*
ccode
;
const
char
*
pred
;
rtx
note
;
validate_condition_mode
(
code
,
mode
)
;
if
(
really_reversed
)
{
if
(
mode
==
CCFPmode
)
code
=
reverse_condition_maybe_unordered
(
code
)
;
else
code
=
reverse_condition
(
code
)
;
}
switch
(
code
)
{
case
NE
:
case
LTGT
:
ccode
=
"ne"
;
break
;
case
EQ
:
case
UNEQ
:
ccode
=
"eq"
;
break
;
case
GE
:
case
GEU
:
ccode
=
"ge"
;
break
;
case
GT
:
case
GTU
:
case
UNGT
:
ccode
=
"gt"
;
break
;
case
LE
:
case
LEU
:
ccode
=
"le"
;
break
;
case
LT
:
case
LTU
:
case
UNLT
:
ccode
=
"lt"
;
break
;
case
UNORDERED
:
ccode
=
"un"
;
break
;
case
ORDERED
:
ccode
=
"nu"
;
break
;
case
UNGE
:
ccode
=
"nl"
;
break
;
case
UNLE
:
ccode
=
"ng"
;
break
;
default
:
gcc_unreachable
(
)
;
}
pred
=
""
;
note
=
find_reg_note
(
insn
,
REG_BR_PROB
,
NULL_RTX
)
;
if
(
note
!=
NULL_RTX
)
{
int
prob
=
profile_probability
::
from_reg_br_prob_note
(
XINT
(
note
,
0
)
)
.
to_reg_br_prob_base
(
)
REG_BR_PROB_BASE
/
2
;
if
(
rs6000_always_hint
||
(
abs
(
prob
)
>
REG_BR_PROB_BASE
/
100
*
48
&&
(
profile_status_for_fn
(
cfun
)
!=
PROFILE_GUESSED
)
&&
br_prob_note_reliable_p
(
note
)
)
)
{
if
(
abs
(
prob
)
>
REG_BR_PROB_BASE
/
20
&&
(
(
prob
>
0
)
^
need_longbranch
)
)
pred
=
"+"
;
else
pred
=
"-"
;
}
}
if
(
label
==
)
s
+=
sprintf
(
s
,
"b%slr%s "
,
ccode
,
pred
)
;
else
s
+=
sprintf
(
s
,
"b%s%s "
,
ccode
,
pred
)
;
if
(
reg_names
[
cc_regno
+
CR0_REGNO
]
[
0
]
==
'%'
)
*
s
++
=
'%'
;
s
+=
sprintf
(
s
,
"%s"
,
reg_names
[
cc_regno
+
CR0_REGNO
]
)
;
if
(
label
!=
)
{
if
(
need_longbranch
)
s
+=
sprintf
(
s
,
",$+8\n\tb %s"
,
label
)
;
else
s
+=
sprintf
(
s
,
",%s"
,
label
)
;
}
return
string
;
}
</s>

Output a conditional branch to LABEL . CODE is the comparison code . CC_MODE is the mode of the CC register . REVERSED is non-zero if we should reverse the sense of the comparison . INSN is the instruction .


<s>
static
void
rs6000_elf_output_toc_section_asm_op
(
const
void
*
data
ATTRIBUTE_UNUSED
)
{
if
(
(
DEFAULT_ABI
==
ABI_AIX
||
DEFAULT_ABI
==
ABI_ELFv2
)
&&
TARGET_MINIMAL_TOC
&&
!
TARGET_RELOCATABLE
)
{
if
(
!
toc_initialized
)
{
toc_initialized
=
1
;
fprintf
(
asm_out_file
,
"%s\n"
,
TOC_SECTION_ASM_OP
)
;
(
*
targetm
.
asm_out
.
internal_label
)
(
asm_out_file
,
"LCTOC"
,
0
)
;
fprintf
(
asm_out_file
,
"\t.tc "
)
;
ASM_OUTPUT_INTERNAL_LABEL_PREFIX
(
asm_out_file
,
"LCTOC1[TC],"
)
;
ASM_OUTPUT_INTERNAL_LABEL_PREFIX
(
asm_out_file
,
"LCTOC1"
)
;
fprintf
(
asm_out_file
,
"\n"
)
;
fprintf
(
asm_out_file
,
"%s\n"
,
MINIMAL_TOC_SECTION_ASM_OP
)
;
ASM_OUTPUT_INTERNAL_LABEL_PREFIX
(
asm_out_file
,
"LCTOC1"
)
;
fprintf
(
asm_out_file
,
" = .+32768\n"
)
;
}
else
fprintf
(
asm_out_file
,
"%s\n"
,
MINIMAL_TOC_SECTION_ASM_OP
)
;
}
else
if
(
(
DEFAULT_ABI
==
ABI_AIX
||
DEFAULT_ABI
==
ABI_ELFv2
)
&&
!
TARGET_RELOCATABLE
)
fprintf
(
asm_out_file
,
"%s\n"
,
TOC_SECTION_ASM_OP
)
;
else
{
fprintf
(
asm_out_file
,
"%s\n"
,
MINIMAL_TOC_SECTION_ASM_OP
)
;
if
(
!
toc_initialized
)
{
ASM_OUTPUT_INTERNAL_LABEL_PREFIX
(
asm_out_file
,
"LCTOC1"
)
;
fprintf
(
asm_out_file
,
" = .+32768\n"
)
;
toc_initialized
=
1
;
}
}
}
</s>

A get_unnamed_section callback , used for switching to toc_section .


<s> bool X86TargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { const IntrinsicData * IntrData = getIntrinsicWithChain ( Intrinsic ) ; if ( ! IntrData ) return false ; Info . flags = MachineMemOperand :: MONone ; Info . offset = 0 ; switch ( IntrData -> Type ) { case TRUNCATE_TO_MEM_VI8 : case TRUNCATE_TO_MEM_VI16 : case TRUNCATE_TO_MEM_VI32 : { Info . opc = ISD :: INTRINSIC_VOID ; Info . ptrVal = I . getArgOperand ( 0 ) ; MVT VT = MVT :: getVT ( I . getArgOperand ( 1 ) -> getType ( ) ) ; MVT ScalarVT = MVT :: INVALID_SIMPLE_VALUE_TYPE ; if ( IntrData -> Type == TRUNCATE_TO_MEM_VI8 ) ScalarVT = MVT :: i8 ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI16 ) ScalarVT = MVT :: i16 ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI32 ) ScalarVT = MVT :: i32 ; Info . memVT = MVT :: getVectorVT ( ScalarVT , VT . getVectorNumElements ( ) ) ; Info . align = Align :: None ( ) ; Info . flags |= MachineMemOperand :: MOStore ; break ; } case GATHER : case GATHER_AVX2 : { Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . ptrVal = nullptr ; MVT DataVT = MVT :: getVT ( I . getType ( ) ) ; MVT IndexVT = MVT :: getVT ( I . getArgOperand ( 2 ) -> getType ( ) ) ; unsigned NumElts = std :: min ( DataVT . getVectorNumElements ( ) , IndexVT . getVectorNumElements ( ) ) ; Info . memVT = MVT :: getVectorVT ( DataVT . getVectorElementType ( ) , NumElts ) ; Info . align = Align :: None ( ) ; Info . flags |= MachineMemOperand :: MOLoad ; break ; } case SCATTER : { Info . opc = ISD :: INTRINSIC_VOID ; Info . ptrVal = nullptr ; MVT DataVT = MVT :: getVT ( I . getArgOperand ( 3 ) -> getType ( ) ) ; MVT IndexVT = MVT :: getVT ( I . getArgOperand ( 2 ) -> getType ( ) ) ; unsigned NumElts = std :: min ( DataVT . getVectorNumElements ( ) , IndexVT . getVectorNumElements ( ) ) ; Info . memVT = MVT :: getVectorVT ( DataVT . getVectorElementType ( ) , NumElts ) ; Info . align = Align :: None ( ) ; Info . flags |= MachineMemOperand :: MOStore ; break ; } default : return false ; } return true ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> static void mips16_load_branch_target ( rtx dest , rtx src ) { if ( TARGET_ABICALLS && ! TARGET_ABSOLUTE_ABICALLS ) { rtx page , low ; if ( mips_cfun_has_cprestore_slot_p ( ) ) mips_emit_move ( dest , mips_cprestore_slot ( dest , true ) ) ; else mips_emit_move ( dest , pic_offset_table_rtx ) ; page = mips_unspec_address ( src , SYMBOL_GOTOFF_PAGE ) ; low = mips_unspec_address ( src , SYMBOL_GOT_PAGE_OFST ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , PMODE_INSN ( gen_unspec_got , ( dest , page ) ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , gen_rtx_LO_SUM ( Pmode , dest , low ) ) ) ; } else { src = mips_unspec_address ( src , SYMBOL_ABSOLUTE ) ; mips_emit_move ( dest , src ) ; } } </s>

Emit code to load LABEL_REF SRC into MIPS16 register DEST . This is called very late in mips_reorg , but the caller is required to run mips16_lay_out_constants on the result .


<s> MachineBasicBlock :: iterator MSP430FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const MSP430InstrInfo & TII = * static_cast < const MSP430InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; unsigned StackAlign = getStackAlignment ( ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr & Old = * I ; uint64_t Amount = TII . getFrameSize ( Old ) ; if ( Amount != 0 ) { Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = nullptr ; if ( Old . getOpcode ( ) == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( MSP430 :: SUB16ri ) , MSP430 :: SP ) . addReg ( MSP430 :: SP ) . addImm ( Amount ) ; } else { assert ( Old . getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) ; Amount -= TII . getFramePoppedByCallee ( Old ) ; if ( Amount ) New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( MSP430 :: ADD16ri ) , MSP430 :: SP ) . addReg ( MSP430 :: SP ) . addImm ( Amount ) ; } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = TII . getFramePoppedByCallee ( * I ) ) { MachineInstr & Old = * I ; MachineInstr * New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( MSP430 :: SUB16ri ) , MSP430 :: SP ) . addReg ( MSP430 :: SP ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> void SPIRVPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s>
void
RV16KInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MBBI
,
const
DebugLoc
&
DL
,
unsigned
DstReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
assert
(
RV16K
::
GPRRegClass
.
contains
(
DstReg
,
SrcReg
)
&&
"Impossible reg-to-reg copy"
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
RV16K
::
MOV
)
,
DstReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> void AMDGPUTargetELFStreamer :: finish ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; MCA . setELFHeaderEFlags ( getEFlags ( ) ) ; std :: string Blob ; const char * Vendor = getPALMetadata ( ) -> getVendor ( ) ; unsigned Type = getPALMetadata ( ) -> getType ( ) ; getPALMetadata ( ) -> toBlob ( Type , Blob ) ; if ( Blob . empty ( ) ) return ; EmitNote ( Vendor , MCConstantExpr :: create ( Blob . size ( ) , getContext ( ) ) , Type , [ & ] ( MCELFStreamer & OS ) { OS . emitBytes ( Blob ) ; } ) ; getPALMetadata ( ) -> reset ( ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> rtx visium_legitimize_reload_address ( rtx x , machine_mode mode , int opnum , int type , int ind ATTRIBUTE_UNUSED ) { rtx newrtx , tem = NULL_RTX ; if ( mode == BLKmode ) return NULL_RTX ; if ( optimize && GET_CODE ( x ) == PLUS ) tem = simplify_binary_operation ( PLUS , GET_MODE ( x ) , XEXP ( x , 0 ) , XEXP ( x , 1 ) ) ; newrtx = tem ? tem : x ; if ( GET_CODE ( newrtx ) == PLUS && GET_CODE ( XEXP ( newrtx , 1 ) ) == CONST_INT && GET_CODE ( XEXP ( newrtx , 0 ) ) == REG && BASE_REGISTER_P ( REGNO ( XEXP ( newrtx , 0 ) ) ) ) { int offset = INTVAL ( XEXP ( newrtx , 1 ) ) ; int size = GET_MODE_SIZE ( mode ) ; int mask = ( size == 1 ? 0x1f : ( size == 2 ? 0x3f : 0x7f ) ) ; int mask1 = ( size == 1 ? 0 : ( size == 2 ? 1 : 3 ) ) ; int offset_base = offset & ~ mask ; if ( size > 4 && size + offset - offset_base > 0x80 ) offset_base = offset & ~ 0x3f ; if ( offset_base && ( offset & mask1 ) == 0 ) { rtx temp = gen_rtx_PLUS ( Pmode , XEXP ( newrtx , 0 ) , GEN_INT ( offset_base ) ) ; x = gen_rtx_PLUS ( Pmode , temp , GEN_INT ( offset - offset_base ) ) ; push_reload ( XEXP ( x , 0 ) , 0 , & XEXP ( x , 0 ) , 0 , BASE_REG_CLASS , Pmode , VOIDmode , 0 , 0 , opnum , ( enum reload_type ) type ) ; return x ; } } return NULL_RTX ; } </s>

Perform a similar function to visium_legitimize_address , but this time for reload . Generating new registers is not an option here . Parts that need reloading are indicated by calling push_reload .


<s>
void
SIInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
DestReg
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
SIMachineFunctionInfo
*
MFI
=
MF
->
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MachineFrameInfo
&
FrameInfo
=
MF
->
getFrameInfo
(
)
;
const
DebugLoc
&
DL
=
MBB
.
findDebugLoc
(
MI
)
;
unsigned
Align
=
FrameInfo
.
getObjectAlignment
(
FrameIndex
)
;
unsigned
Size
=
FrameInfo
.
getObjectSize
(
FrameIndex
)
;
unsigned
SpillSize
=
TRI
->
getSpillSize
(
*
RC
)
;
MachinePointerInfo
PtrInfo
=
MachinePointerInfo
::
getFixedStack
(
*
MF
,
FrameIndex
)
;
MachineMemOperand
*
MMO
=
MF
->
getMachineMemOperand
(
PtrInfo
,
MachineMemOperand
::
MOLoad
,
Size
,
Align
)
;
if
(
RI
.
isSGPRClass
(
RC
)
)
{
MFI
->
setHasSpilledSGPRs
(
)
;
const
MCInstrDesc
&
OpDesc
=
get
(
getSGPRSpillRestoreOpcode
(
SpillSize
)
)
;
if
(
TargetRegisterInfo
::
isVirtualRegister
(
DestReg
)
&&
SpillSize
==
4
)
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
MRI
.
constrainRegClass
(
DestReg
,
&
AMDGPU
::
SReg_32_XM0RegClass
)
;
}
FrameInfo
.
setStackID
(
FrameIndex
,
TargetStackID
::
SGPRSpill
)
;
MachineInstrBuilder
Spill
=
BuildMI
(
MBB
,
MI
,
DL
,
OpDesc
,
DestReg
)
.
addFrameIndex
(
FrameIndex
)
.
addMemOperand
(
MMO
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
,
RegState
::
Implicit
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
,
RegState
::
Implicit
)
;
if
(
ST
.
hasScalarStores
(
)
)
{
Spill
.
addReg
(
AMDGPU
::
M0
,
RegState
::
ImplicitDefine
|
RegState
::
Dead
)
;
}
return
;
}
assert
(
RI
.
hasVGPRs
(
RC
)
&&
"Only VGPR spilling expected"
)
;
unsigned
Opcode
=
getVGPRSpillRestoreOpcode
(
SpillSize
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opcode
)
,
DestReg
)
.
addFrameIndex
(
FrameIndex
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


"instruction use requires an option to be enabled"

"unable to convert operands to instruction"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> bool AArch64TargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { EVT VT ; SDValue Ptr ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; } else return false ; bool IsInc ; if ( ! getIndexedAddressParts ( Ptr . getNode ( ) , Base , Offset , AM , IsInc , DAG ) ) return false ; AM = IsInc ? ISD :: PRE_INC : ISD :: PRE_DEC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .


<s>
void
HexagonEarlyIfConversion
::
removeBlock
(
MachineBasicBlock
*
B
)
{
DEBUG
(
dbgs
(
)
<<
"Removing block "
<<
PrintMB
(
B
)
<<
"\n"
)
;
MachineDomTreeNode
*
N
=
MDT
->
getNode
(
B
)
;
MachineDomTreeNode
*
IDN
=
N
->
getIDom
(
)
;
if
(
IDN
)
{
MachineBasicBlock
*
IDB
=
IDN
->
getBlock
(
)
;
typedef
GraphTraits
<
MachineDomTreeNode
*
>
GTN
;
typedef
SmallVector
<
MachineDomTreeNode
*
,
4
>
DTNodeVectType
;
DTNodeVectType
Cn
(
GTN
::
child_begin
(
N
)
,
GTN
::
child_end
(
N
)
)
;
for
(
DTNodeVectType
::
iterator
I
=
Cn
.
begin
(
)
,
E
=
Cn
.
end
(
)
;
I
!=
E
;
++
I
)
{
MachineBasicBlock
*
SB
=
(
*
I
)
->
getBlock
(
)
;
MDT
->
changeImmediateDominator
(
SB
,
IDB
)
;
}
}
while
(
B
->
succ_size
(
)
>
0
)
B
->
removeSuccessor
(
B
->
succ_begin
(
)
)
;
for
(
auto
I
=
B
->
pred_begin
(
)
,
E
=
B
->
pred_end
(
)
;
I
!=
E
;
++
I
)
(
*
I
)
->
removeSuccessor
(
B
)
;
Deleted
.
insert
(
B
)
;
MDT
->
eraseNode
(
B
)
;
MachineFunction
::
iterator
BI
=
B
;
MFN
->
erase
(
BI
)
;
}
</s>

This method completely removes BB from all data structures , including all of the Loop objects it is nested in and our mapping from MachineBasicBlocks to loops .

Hexagon
Hexagon
"Removing block "
"\n"
4
0


"  Mark r%d def in insn %d as requiring both modes in chain #%d\n"

For DImode conversion , mark register defined by DEF as requiring conversion .


<s> bool SIMachineFunctionInfo :: allocateVGPRSpillToAGPR ( MachineFunction & MF , int FI , bool isAGPRtoVGPR ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MachineFrameInfo & FrameInfo = MF . getFrameInfo ( ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; assert ( ST . hasMAIInsts ( ) && FrameInfo . isSpillSlotObjectIndex ( FI ) ) ; auto & Spill = VGPRToAGPRSpills [ FI ] ; if ( ! Spill . Lanes . empty ( ) ) return Spill . FullyAllocated ; unsigned Size = FrameInfo . getObjectSize ( FI ) ; unsigned NumLanes = Size / 4 ; Spill . Lanes . resize ( NumLanes , AMDGPU :: NoRegister ) ; const TargetRegisterClass & RC = isAGPRtoVGPR ? AMDGPU :: VGPR_32RegClass : AMDGPU :: AGPR_32RegClass ; auto Regs = RC . getRegisters ( ) ; auto & SpillRegs = isAGPRtoVGPR ? SpillAGPR : SpillVGPR ; const SIRegisterInfo * TRI = ST . getRegisterInfo ( ) ; Spill . FullyAllocated = true ; BitVector OtherUsedRegs ; OtherUsedRegs . resize ( TRI -> getNumRegs ( ) ) ; const uint32_t * CSRMask = TRI -> getCallPreservedMask ( MF , MF . getFunction ( ) . getCallingConv ( ) ) ; if ( CSRMask ) OtherUsedRegs . setBitsInMask ( CSRMask ) ; for ( MCPhysReg Reg : SpillAGPR ) OtherUsedRegs . set ( Reg ) ; for ( MCPhysReg Reg : SpillVGPR ) OtherUsedRegs . set ( Reg ) ; SmallVectorImpl < MCPhysReg > :: const_iterator NextSpillReg = Regs . begin ( ) ; for ( int I = NumLanes - 1 ; I >= 0 ; -- I ) { NextSpillReg = std :: find_if ( NextSpillReg , Regs . end ( ) , [ & MRI , & OtherUsedRegs ] ( MCPhysReg Reg ) { return MRI . isAllocatable ( Reg ) && ! MRI . isPhysRegUsed ( Reg ) && ! OtherUsedRegs [ Reg ] ; } ) ; if ( NextSpillReg == Regs . end ( ) ) { Spill . FullyAllocated = false ; break ; } OtherUsedRegs . set ( * NextSpillReg ) ; SpillRegs . push_back ( * NextSpillReg ) ; Spill . Lanes [ I ] = * NextSpillReg ++ ; } return Spill . FullyAllocated ; } </s>

Reserve AGPRs or VGPRs to support spilling for FrameIndex FI .


"getJumpTargetOpValue is not implemented yet"

getJumpTargetOpValue - Return binary encoding of the jump target operand .


<s> MCObjectWriter * WebAssemblyAsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { return createWebAssemblyELFObjectWriter ( OS , Is64Bit , 0 ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> unsigned LoongArchAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { LoongArchOperand & Op = static_cast < LoongArchOperand & > ( AsmOp ) ; if ( ! Op . isReg ( ) ) return Match_InvalidOperand ; MCRegister Reg = Op . getReg ( ) ; if ( LoongArchMCRegisterClasses [ LoongArch :: FPR32RegClassID ] . contains ( Reg ) && Kind == MCK_FPR64 ) { Op . setReg ( convertFPR32ToFPR64 ( Reg ) ) ; return Match_Success ; } return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .

LoongArch LoongArch LoongArch LoongArch LoongArch LoongArch::FPR32RegClassID


<s> static int pcrel_constant_p ( rtx x ) { if ( GET_CODE ( x ) == MINUS ) return symbol_mentioned_p ( XEXP ( x , 0 ) ) && label_mentioned_p ( XEXP ( x , 1 ) ) ; return FALSE ; } </s>

Return TRUE if this rtx is the difference of a symbol and a label , and will reduce to a PC-relative relocation in the object file . Expressions like this can be left alone when generating PIC , rather than forced through the GOT .


<s>
StringRef
getPassName
(
)
const
override
{
return
"VE Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> const MipsAnalyzeImmediate :: InstSeq & MipsAnalyzeImmediate :: Analyze ( uint64_t Imm , unsigned Size , bool LastInstrIsADDiu ) { this -> Size = Size ; if ( Size == 32 ) { ADDiu = Mips :: ADDiu ; ORi = Mips :: ORi ; SLL = Mips :: SLL ; LUi = Mips :: LUi ; } else { ADDiu = Mips :: DADDiu ; ORi = Mips :: ORi64 ; SLL = Mips :: DSLL ; LUi = Mips :: LUi64 ; } InstSeqLs SeqLs ; if ( LastInstrIsADDiu | ! Imm ) GetInstSeqLsADDiu ( Imm , Size , SeqLs ) ; else GetInstSeqLs ( Imm , Size , SeqLs ) ; GetShortestSeq ( SeqLs , Insts ) ; return Insts ; } </s>

Analyze - Get an instruction sequence to load immediate Imm .

Mips Mips Mips 32 Mips::ADDiu Mips::ORi Mips::SLL Mips::LUi Mips::DADDiu Mips::ORi64 Mips::DSLL Mips::LUi64


<s> bool MSP430RegisterInfo :: hasReservedCallFrame ( MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s>
SDValue
MBlazeTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_MBlaze
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
if
(
RVLocs
[
i
]
.
isRegLoc
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
unsigned
Ret
=
(
CallConv
==
llvm
::
CallingConv
::
MBLAZE_INTR
)
MBlazeISD
::
IRet
:
MBlazeISD
::
Ret
;
unsigned
Reg
=
(
CallConv
==
llvm
::
CallingConv
::
MBLAZE_INTR
)
MBlaze
::
R14
:
MBlaze
::
R15
;
SDValue
DReg
=
DAG
.
getRegister
(
Reg
,
MVT
::
i32
)
;
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
Ret
,
dl
,
MVT
::
Other
,
Chain
,
DReg
,
Flag
)
;
return
DAG
.
getNode
(
Ret
,
dl
,
MVT
::
Other
,
Chain
,
DReg
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool AArch64TargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { return CI -> isTailCall ( ) ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


"Callee should be an llvm::Function object."

"failed to perform tail call elimination on a call "

This hook must be implemented to lower calls into the specified DAG .


<s> static bool classof ( const SpecialTypeDescriptor * TD ) { return TD -> Kind == SpecialTypeKind :: STK_Pipe ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> void aarch64_emit_sve_pred_move ( rtx dest , rtx pred , rtx src ) { expand_operand ops [ 3 ] ; machine_mode mode = GET_MODE ( dest ) ; create_output_operand ( & ops [ 0 ] , dest , mode ) ; create_input_operand ( & ops [ 1 ] , pred , GET_MODE ( pred ) ) ; create_input_operand ( & ops [ 2 ] , src , mode ) ; temporary_volatile_ok v ( true ) ; expand_insn ( code_for_aarch64_pred_mov ( mode ) , 3 , ops ) ; } </s>

Emit an SVE predicated move from SRC to DEST . PRED is a predicate that is known to contain PTRUE .


"Using .cp. section for writeable object."

Targets should implement this method to assign a section to globals with an explicit section specfied .


<s> OperandMatchResultTy P2AsmParser :: tryParseRegister ( unsigned & reg_no , SMLoc & start , SMLoc & end ) { start = Parser . getTok ( ) . getLoc ( ) ; reg_no = parseRegister ( "" ) ; end = Parser . getTok ( ) . getLoc ( ) ; if ( reg_no == ( unsigned ) - 1 ) return MatchOperand_NoMatch ; return MatchOperand_Success ; } </s>

tryParseRegister - parse one register if possible


<s> static rtx csky_function_value ( const_tree type , const_tree func , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode mode ; int unsignedp ATTRIBUTE_UNUSED ; int size ; mode = TYPE_MODE ( type ) ; size = int_size_in_bytes ( type ) ; if ( FUNCTION_VARG_MODE_P ( mode ) ) { mode = promote_function_mode ( type , mode , & unsignedp , func , 1 ) ; return gen_rtx_REG ( mode , CSKY_FIRST_VFP_REGNUM ) ; } if ( INTEGRAL_TYPE_P ( type ) ) { mode = promote_function_mode ( type , mode , & unsignedp , func , 1 ) ; return gen_rtx_REG ( mode , CSKY_FIRST_RET_REGNUM ) ; } if ( mode == BLKmode && size > UNITS_PER_WORD && size <= UNITS_PER_WORD * 2 ) { rtx ret_regs [ 2 ] ; ret_regs [ 0 ] = gen_rtx_EXPR_LIST ( SImode , gen_rtx_REG ( SImode , CSKY_FIRST_RET_REGNUM ) , GEN_INT ( 0 * UNITS_PER_WORD ) ) ; ret_regs [ 1 ] = gen_rtx_EXPR_LIST ( SImode , gen_rtx_REG ( SImode , CSKY_FIRST_RET_REGNUM + 1 ) , GEN_INT ( 1 * UNITS_PER_WORD ) ) ; rtvec vec = gen_rtvec ( 2 , ret_regs [ 0 ] , ret_regs [ 1 ] ) ; return gen_rtx_PARALLEL ( mode , vec ) ; } return gen_rtx_REG ( mode , CSKY_FIRST_RET_REGNUM ) ; } </s>


<s> SDValue SITargetLowering :: CreateLiveInRegister ( SelectionDAG & DAG , const TargetRegisterClass * RC , unsigned Reg , EVT VT ) const { SDValue VReg = AMDGPUTargetLowering :: CreateLiveInRegister ( DAG , RC , Reg , VT ) ; return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , SDLoc ( DAG . getEntryNode ( ) ) , cast < RegisterSDNode > ( VReg ) -> getReg ( ) , VT ) ; } </s>

Helper function that adds Reg to the LiveIn list of the DAG 's MachineFunction .


<s> bool X86TTIImpl :: isLegalMaskedGather ( Type * DataTy , Align Alignment ) { if ( ! ( ST -> hasAVX512 ( ) || ( ST -> hasFastGather ( ) && ST -> hasAVX2 ( ) ) ) ) return false ; if ( auto * DataVTy = dyn_cast < FixedVectorType > ( DataTy ) ) { unsigned NumElts = DataVTy -> getNumElements ( ) ; if ( NumElts == 1 ) return false ; } Type * ScalarTy = DataTy -> getScalarType ( ) ; if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == 32 || IntWidth == 64 ; } </s>

Return true if the target supports masked gather .