<s> static bool pa_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { if ( TARGET_64BIT ) return false ; if ( TARGET_PORTABLE_RUNTIME ) return false ; return decl && targetm . binds_local_p ( decl ) ; } </s>

Only direct calls to static functions are allowed to be sibling ( tail ) call optimized . This restriction is necessary because some linker generated stubs will store return pointers into rp ' in some cases which might clobber a live value already in rp ' . In a sibcall the current function and the target function share stack space . Thus if the path to the current function and the path to the target function save a value in rp ' , they save the value into the same stack slot , which has undesirable consequences . Because of the deferred binding nature of shared libraries any function with external scope could be in a different load module and thus require rp ' to be saved when calling that function . So sibcall optimizations can only be safe for static function . Note that GCC never needs return value relocations , so we do n't have to worry about static calls with return value relocations ( which require saving rp ' ) . It is safe to perform a sibcall optimization when the target function will never return .


<s> static void arc_encode_section_info ( tree decl , rtx rtl , int first ) { default_encode_section_info ( decl , rtl , first ) ; if ( TREE_CODE ( decl ) == FUNCTION_DECL ) { rtx symbol = XEXP ( rtl , 0 ) ; int flags = SYMBOL_REF_FLAGS ( symbol ) ; tree attr = ( TREE_TYPE ( decl ) != error_mark_node ? TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) : NULL_TREE ) ; tree long_call_attr = lookup_attribute ( "long_call" , attr ) ; tree medium_call_attr = lookup_attribute ( "medium_call" , attr ) ; tree short_call_attr = lookup_attribute ( "short_call" , attr ) ; if ( long_call_attr != NULL_TREE ) flags |= SYMBOL_FLAG_LONG_CALL ; else if ( medium_call_attr != NULL_TREE ) flags |= SYMBOL_FLAG_MEDIUM_CALL ; else if ( short_call_attr != NULL_TREE ) flags |= SYMBOL_FLAG_SHORT_CALL ; SYMBOL_REF_FLAGS ( symbol ) = flags ; } else if ( TREE_CODE ( decl ) == VAR_DECL ) { rtx symbol = XEXP ( rtl , 0 ) ; tree attr = ( TREE_TYPE ( decl ) != error_mark_node ? DECL_ATTRIBUTES ( decl ) : NULL_TREE ) ; tree sec_attr = lookup_attribute ( "section" , attr ) ; if ( sec_attr ) { const char * sec_name = TREE_STRING_POINTER ( TREE_VALUE ( TREE_VALUE ( sec_attr ) ) ) ; if ( strcmp ( sec_name , ".cmem" ) == 0 || strcmp ( sec_name , ".cmem_shared" ) == 0 || strcmp ( sec_name , ".cmem_private" ) == 0 ) SYMBOL_REF_FLAGS ( symbol ) |= SYMBOL_FLAG_CMEM ; } } } </s>

Implement TARGET_ENCODE_SECTION_INFO hook .


<s> static bool msp430_use_16bit_hwmult ( void ) { static const char * cached_match = NULL ; static bool cached_result ; if ( msp430_hwmult_type == MSP430_HWMULT_SMALL ) return true ; if ( target_mcu == NULL || msp430_hwmult_type != MSP430_HWMULT_AUTO ) return false ; if ( target_mcu == cached_match ) return cached_result ; cached_match = target_mcu ; msp430_extract_mcu_data ( target_mcu ) ; if ( extracted_mcu_data . name != NULL ) return cached_result = ( extracted_mcu_data . hwmpy == 1 || extracted_mcu_data . hwmpy == 2 ) ; return cached_result = false ; } </s>

Returns true if the current MCU has a first generation 16-bit hardware multiplier .


<s>
bool
PPCAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
{
if
(
ExtraCode
[
1
]
!=
0
)
return
true
;
switch
(
ExtraCode
[
0
]
)
{
default
:
return
true
;
case
'y'
:
{
const
char
*
RegName
=
"r0"
;
if
(
!
Subtarget
.
isDarwin
(
)
)
RegName
=
stripRegisterPrefix
(
RegName
)
;
O
<<
RegName
<<
", "
;
printOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
}
case
'U'
:
case
'X'
:
{
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
return
false
;
}
}
}
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
O
<<
"0("
;
printOperand
(
MI
,
OpNo
,
O
)
;
O
<<
")"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s>
void
BTFDebug
::
beginFunctionImpl
(
const
MachineFunction
*
MF
)
{
auto
*
SP
=
MF
->
getFunction
(
)
.
getSubprogram
(
)
;
auto
*
Unit
=
SP
->
getUnit
(
)
;
if
(
Unit
->
getEmissionKind
(
)
==
DICompileUnit
::
NoDebug
)
{
SkipInstruction
=
true
;
return
;
}
SkipInstruction
=
false
;
std
::
unordered_map
<
uint32_t
,
StringRef
>
FuncArgNames
;
for
(
const
DINode
*
DN
:
SP
->
getRetainedNodes
(
)
)
{
if
(
const
auto
*
DV
=
dyn_cast
<
DILocalVariable
>
(
DN
)
)
{
visitTypeEntry
(
DV
->
getType
(
)
.
resolve
(
)
)
;
uint32_t
Arg
=
DV
->
getArg
(
)
;
if
(
Arg
)
FuncArgNames
[
Arg
]
=
DV
->
getName
(
)
;
}
}
uint32_t
ProtoTypeId
;
visitSubroutineType
(
SP
->
getType
(
)
,
true
,
FuncArgNames
,
ProtoTypeId
)
;
auto
FuncTypeEntry
=
llvm
::
make_unique
<
BTFTypeFunc
>
(
SP
->
getName
(
)
,
ProtoTypeId
)
;
uint32_t
FuncTypeId
=
addType
(
std
::
move
(
FuncTypeEntry
)
)
;
MCSymbol
*
FuncLabel
=
Asm
->
getFunctionBegin
(
)
;
BTFFuncInfo
FuncInfo
;
FuncInfo
.
Label
=
FuncLabel
;
FuncInfo
.
TypeId
=
FuncTypeId
;
if
(
FuncLabel
->
isInSection
(
)
)
{
MCSection
&
Section
=
FuncLabel
->
getSection
(
)
;
const
MCSectionELF
*
SectionELF
=
dyn_cast
<
MCSectionELF
>
(
&
Section
)
;
assert
(
SectionELF
&&
"Null section for Function Label"
)
;
SecNameOff
=
addString
(
SectionELF
->
getSectionName
(
)
)
;
}
else
{
SecNameOff
=
addString
(
".text"
)
;
}
FuncInfoTable
[
SecNameOff
]
.
push_back
(
FuncInfo
)
;
}
</s>

BPF
"Null section for Function Label"
".text"


<s> static rtx sparc_delegitimize_address ( rtx x ) { x = delegitimize_mem_from_attrs ( x ) ; if ( GET_CODE ( x ) == LO_SUM ) x = XEXP ( x , 1 ) ; if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , 1 ) ) { case UNSPEC_MOVE_PIC : case UNSPEC_TLSLE : x = XVECEXP ( x , 0 , 0 ) ; gcc_assert ( GET_CODE ( x ) == SYMBOL_REF ) ; break ; case UNSPEC_MOVE_GOTDATA : x = XVECEXP ( x , 0 , 2 ) ; gcc_assert ( GET_CODE ( x ) == SYMBOL_REF ) ; break ; default : break ; } if ( GET_CODE ( x ) == MINUS && ( XEXP ( x , 0 ) == got_register_rtx || sparc_pic_register_p ( XEXP ( x , 0 ) ) ) ) { rtx y = XEXP ( x , 1 ) ; if ( GET_CODE ( y ) == LO_SUM ) y = XEXP ( y , 1 ) ; if ( GET_CODE ( y ) == UNSPEC && XINT ( y , 1 ) == UNSPEC_MOVE_PIC_LABEL ) { x = XVECEXP ( y , 0 , 0 ) ; gcc_assert ( GET_CODE ( x ) == LABEL_REF || ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == LABEL_REF && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 1 ) ) == CONST_INT ) ) ; } } return x ; } </s>

Delegitimize an address that was legitimized by the above function .


<s> static int min_insn_size ( rtx insn ) { int l = 0 ; if ( ! INSN_P ( insn ) || ! active_insn_p ( insn ) ) return 0 ; if ( GET_CODE ( PATTERN ( insn ) ) == UNSPEC_VOLATILE && XINT ( PATTERN ( insn ) , 1 ) == UNSPECV_ALIGN ) return 0 ; if ( GET_CODE ( insn ) == JUMP_INSN && ( GET_CODE ( PATTERN ( insn ) ) == ADDR_VEC || GET_CODE ( PATTERN ( insn ) ) == ADDR_DIFF_VEC ) ) return 0 ; if ( GET_CODE ( insn ) == CALL_INSN && symbolic_reference_mentioned_p ( PATTERN ( insn ) ) && ! SIBLING_CALL_P ( insn ) ) return 5 ; if ( get_attr_length ( insn ) <= 1 ) return 1 ; if ( GET_CODE ( insn ) != JUMP_INSN ) { l = get_attr_length_address ( insn ) ; if ( l < 4 && symbolic_reference_mentioned_p ( PATTERN ( insn ) ) ) l = 4 ; } if ( l ) return 1 + l ; else return 2 ; } </s>

We do n't have exact information about the insn sizes , but we may assume quite safely that we are informed about all 1 byte insns and memory address sizes . This is enough to eliminate unnecessary padding in 99 % of cases .


<s> BitVector AArch64RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const AArch64FrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , AArch64 :: WSP ) ; markSuperRegs ( Reserved , AArch64 :: WZR ) ; if ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) markSuperRegs ( Reserved , AArch64 :: W29 ) ; for ( size_t i = 0 ; i < AArch64 :: GPR32commonRegClass . getNumRegs ( ) ; ++ i ) { if ( MF . getSubtarget < AArch64Subtarget > ( ) . isXRegisterReserved ( i ) ) markSuperRegs ( Reserved , AArch64 :: GPR32commonRegClass . getRegister ( i ) ) ; } if ( hasBasePointer ( MF ) ) markSuperRegs ( Reserved , AArch64 :: W19 ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> EVT RISCVTargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return getPointerTy ( DL ) ; if ( Subtarget . hasStdExtV ( ) ) return MVT :: getVectorVT ( MVT :: i1 , VT . getVectorElementCount ( ) ) ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s>
bool
ARMConstantIslands
::
isBBInRange
(
MachineInstr
*
MI
,
MachineBasicBlock
*
DestBB
,
unsigned
MaxDisp
)
{
unsigned
PCAdj
=
isThumb
4
:
8
;
unsigned
BrOffset
=
getOffsetOf
(
MI
)
+
PCAdj
;
unsigned
DestOffset
=
BBInfo
[
DestBB
->
getNumber
(
)
]
.
Offset
;
DEBUG
(
dbgs
(
)
<<
"Branch of destination "
<<
printMBBReference
(
*
DestBB
)
<<
" from "
<<
printMBBReference
(
*
MI
->
getParent
(
)
)
<<
" max delta="
<<
MaxDisp
<<
" from "
<<
getOffsetOf
(
MI
)
<<
" to "
<<
DestOffset
<<
" offset "
<<
int
(
DestOffset
BrOffset
)
<<
"\t"
<<
*
MI
)
;
if
(
BrOffset
<=
DestOffset
)
{
if
(
DestOffset
BrOffset
<=
MaxDisp
)
return
true
;
}
else
{
if
(
BrOffset
DestOffset
<=
MaxDisp
)
return
true
;
}
return
false
;
}
</s>

isBBInRange - Returns true if the distance between specific MI and specific BB can fit in MI 's displacement field .

ARM
ARM
4
8
"Branch of destination "
" from "
" max delta="
" from "
" to "
" offset "
"\t"


<s>
SDValue
X86TargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
bool
Is64Bit
=
Subtarget
.
is64Bit
(
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_X86
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
CopyVT
=
VA
.
getLocVT
(
)
;
if
(
(
CopyVT
==
MVT
::
f32
||
CopyVT
==
MVT
::
f64
||
CopyVT
==
MVT
::
f128
)
&&
(
(
Is64Bit
||
Ins
[
i
]
.
Flags
.
isInReg
(
)
)
&&
!
Subtarget
.
hasSSE1
(
)
)
)
{
report_fatal_error
(
"SSE register return with SSE disabled"
)
;
}
bool
RoundAfterCopy
=
false
;
if
(
(
VA
.
getLocReg
(
)
==
X86
::
FP0
||
VA
.
getLocReg
(
)
==
X86
::
FP1
)
&&
isScalarFPTypeInSSEReg
(
VA
.
getValVT
(
)
)
)
{
if
(
!
Subtarget
.
hasX87
(
)
)
report_fatal_error
(
"X87 register return with X87 disabled"
)
;
CopyVT
=
MVT
::
f80
;
RoundAfterCopy
=
(
CopyVT
!=
VA
.
getLocVT
(
)
)
;
}
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
CopyVT
,
InFlag
)
.
getValue
(
1
)
;
SDValue
Val
=
Chain
.
getValue
(
0
)
;
if
(
RoundAfterCopy
)
Val
=
DAG
.
getNode
(
ISD
::
FP_ROUND
,
dl
,
VA
.
getValVT
(
)
,
Val
,
DAG
.
getIntPtrConstant
(
1
,
dl
)
)
;
if
(
VA
.
isExtInLoc
(
)
&&
VA
.
getValVT
(
)
.
getScalarType
(
)
==
MVT
::
i1
)
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
InFlag
=
Chain
.
getValue
(
2
)
;
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s>
void
SystemZRegisterInfo
::
emitPrologue
(
MachineFunction
&
MF
)
const
{
MachineBasicBlock
&
MBB
=
MF
.
front
(
)
;
const
TargetFrameInfo
&
TFI
=
*
MF
.
getTarget
(
)
.
getFrameInfo
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
SystemZMachineFunctionInfo
*
SystemZMFI
=
MF
.
getInfo
<
SystemZMachineFunctionInfo
>
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
DL
=
(
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
::
getUnknownLoc
(
)
)
;
uint64_t
StackSize
=
MFI
->
getStackSize
(
)
;
StackSize
-=
SystemZMFI
->
getCalleeSavedFrameSize
(
)
;
uint64_t
NumBytes
=
StackSize
TFI
.
getOffsetOfLocalArea
(
)
;
while
(
MBBI
!=
MBB
.
end
(
)
&&
(
MBBI
->
getOpcode
(
)
==
SystemZ
::
MOV64mr
||
MBBI
->
getOpcode
(
)
==
SystemZ
::
MOV64mrm
)
)
++
MBBI
;
if
(
MBBI
!=
MBB
.
end
(
)
)
DL
=
MBBI
->
getDebugLoc
(
)
;
if
(
StackSize
||
MFI
->
hasCalls
(
)
)
{
assert
(
MF
.
getRegInfo
(
)
.
isPhysRegUsed
(
SystemZ
::
R15D
)
&&
"Invalid stack frame calculation!"
)
;
emitSPUpdate
(
MBB
,
MBBI
,
(
int64_t
)
NumBytes
,
TII
)
;
}
if
(
hasFP
(
MF
)
)
{
BuildMI
(
MBB
,
MBBI
,
DL
,
TII
.
get
(
SystemZ
::
MOV64rr
)
,
SystemZ
::
R11D
)
.
addReg
(
SystemZ
::
R15D
)
;
for
(
MachineFunction
::
iterator
I
=
next
(
MF
.
begin
(
)
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
I
->
addLiveIn
(
SystemZ
::
R11D
)
;
}
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> ScheduleHazardRecognizer :: HazardType GCNHazardRecognizer :: getHazardType ( SUnit * SU , int Stalls ) { MachineInstr * MI = SU -> getInstr ( ) ; if ( MI -> isBundle ( ) ) return NoHazard ; if ( SIInstrInfo :: isSMRD ( * MI ) && checkSMRDHazards ( MI ) > 0 ) return NoopHazard ; if ( ( SIInstrInfo :: isVMEM ( * MI ) || SIInstrInfo :: isFLAT ( * MI ) ) && checkVMEMHazards ( MI ) > 0 ) return NoopHazard ; if ( ST . hasNSAtoVMEMBug ( ) && checkNSAtoVMEMHazard ( MI ) > 0 ) return NoopHazard ; if ( checkFPAtomicToDenormModeHazard ( MI ) > 0 ) return NoopHazard ; if ( ST . hasNoDataDepHazard ( ) ) return NoHazard ; if ( SIInstrInfo :: isVALU ( * MI ) && checkVALUHazards ( MI ) > 0 ) return NoopHazard ; if ( SIInstrInfo :: isDPP ( * MI ) && checkDPPHazards ( MI ) > 0 ) return NoopHazard ; if ( isDivFMas ( MI -> getOpcode ( ) ) && checkDivFMasHazards ( MI ) > 0 ) return NoopHazard ; if ( isRWLane ( MI -> getOpcode ( ) ) && checkRWLaneHazards ( MI ) > 0 ) return NoopHazard ; if ( isSGetReg ( MI -> getOpcode ( ) ) && checkGetRegHazards ( MI ) > 0 ) return NoopHazard ; if ( isSSetReg ( MI -> getOpcode ( ) ) && checkSetRegHazards ( MI ) > 0 ) return NoopHazard ; if ( isRFE ( MI -> getOpcode ( ) ) && checkRFEHazards ( MI ) > 0 ) return NoopHazard ; if ( ST . hasReadM0MovRelInterpHazard ( ) && ( TII . isVINTRP ( * MI ) || isSMovRel ( MI -> getOpcode ( ) ) ) && checkReadM0Hazards ( MI ) > 0 ) return NoopHazard ; if ( ST . hasReadM0SendMsgHazard ( ) && isSendMsgTraceDataOrGDS ( TII , * MI ) && checkReadM0Hazards ( MI ) > 0 ) return NoopHazard ; if ( SIInstrInfo :: isMAI ( * MI ) && checkMAIHazards ( MI ) > 0 ) return NoopHazard ; if ( ( MI -> mayLoad ( ) || MI -> mayStore ( ) ) && checkMAILdStHazards ( MI ) > 0 ) return NoopHazard ; if ( MI -> isInlineAsm ( ) && checkInlineAsmHazards ( MI ) > 0 ) return NoopHazard ; if ( checkAnyInstHazards ( MI ) > 0 ) return NoopHazard ; return NoHazard ; } </s>

getHazardType - Return the hazard type of emitting this node .


<s> static enum mips_symbol_type mips_classify_symbol ( const_rtx x , enum mips_symbol_context context ) { if ( TARGET_RTP_PIC ) return SYMBOL_GOT_DISP ; if ( GET_CODE ( x ) == LABEL_REF ) { if ( TARGET_MIPS16_SHORT_JUMP_TABLES && ! LABEL_REF_NONLOCAL_P ( x ) ) return SYMBOL_PC_RELATIVE ; if ( TARGET_ABICALLS && ! TARGET_ABSOLUTE_ABICALLS ) return SYMBOL_GOT_PAGE_OFST ; return SYMBOL_ABSOLUTE ; } gcc_assert ( GET_CODE ( x ) == SYMBOL_REF ) ; if ( SYMBOL_REF_TLS_MODEL ( x ) ) return SYMBOL_TLS ; if ( CONSTANT_POOL_ADDRESS_P ( x ) ) { if ( TARGET_MIPS16_TEXT_LOADS ) return SYMBOL_PC_RELATIVE ; if ( TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM ) return SYMBOL_PC_RELATIVE ; if ( mips_rtx_constant_in_small_data_p ( get_pool_mode ( x ) ) ) return SYMBOL_GP_RELATIVE ; } if ( TARGET_GPOPT && SYMBOL_REF_SMALL_P ( x ) && ! SYMBOL_REF_WEAK ( x ) ) return SYMBOL_GP_RELATIVE ; if ( TARGET_ABICALLS_PIC2 && ! ( TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p ( x ) ) ) { if ( mips_global_symbol_p ( x ) ) return SYMBOL_GOT_DISP ; return SYMBOL_GOT_PAGE_OFST ; } return SYMBOL_ABSOLUTE ; } </s>

Classify symbol X , which must be a SYMBOL_REF or a LABEL_REF .


<s> static int c4x_r11_set_p ( rtx x ) { rtx set ; int i , j ; const char * fmt ; if ( x == 0 ) return 0 ; if ( INSN_P ( x ) && GET_CODE ( PATTERN ( x ) ) == SEQUENCE ) x = XVECEXP ( PATTERN ( x ) , 0 , XVECLEN ( PATTERN ( x ) , 0 ) - 1 ) ; if ( INSN_P ( x ) && ( set = single_set ( x ) ) ) x = SET_DEST ( set ) ; if ( GET_CODE ( x ) == REG && REGNO ( x ) == R11_REGNO ) return 1 ; fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'e' ) { if ( c4x_r11_set_p ( XEXP ( x , i ) ) ) return 1 ; } else if ( fmt [ i ] == 'E' ) for ( j = XVECLEN ( x , i ) - 1 ; j >= 0 ; j -- ) if ( c4x_r11_set_p ( XVECEXP ( x , i , j ) ) ) return 1 ; } return 0 ; } </s>

Check if register r11 is used as the destination of an insn .


<s> void ix86_expand_binary_operator ( enum rtx_code code , machine_mode mode , rtx operands [ ] ) { rtx src1 , src2 , dst , op , clob ; dst = ix86_fixup_binary_operands ( code , mode , operands ) ; src1 = operands [ 1 ] ; src2 = operands [ 2 ] ; op = gen_rtx_SET ( dst , gen_rtx_fmt_ee ( code , mode , src1 , src2 ) ) ; if ( reload_completed && code == PLUS && ! rtx_equal_p ( dst , src1 ) ) { emit_insn ( op ) ; } else { clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , op , clob ) ) ) ; } if ( dst != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , dst ) ; } </s>

Attempt to expand a binary operator . Make the expansion closer to the actual machine , then just general_operand , which will allow 3 separate memory references ( one output , two input ) in a single insn .


<s> static int avr_naked_function_p ( tree func ) { return avr_lookup_function_attribute1 ( func , "naked" ) ; } </s>

Return non-zero if FUNC is a naked function .


<s> bool SparcTargetMachine :: addInstSelector ( PassManagerBase & PM ) { PM . add ( createSparcISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static rtx aarch64_simd_make_constant ( rtx vals ) { machine_mode mode = GET_MODE ( vals ) ; rtx const_dup ; rtx const_vec = NULL_RTX ; int n_const = 0 ; int i ; if ( GET_CODE ( vals ) == CONST_VECTOR ) const_vec = vals ; else if ( GET_CODE ( vals ) == PARALLEL ) { int n_elts = XVECLEN ( vals , 0 ) ; for ( i = 0 ; i < n_elts ; ++ i ) { rtx x = XVECEXP ( vals , 0 , i ) ; if ( CONST_INT_P ( x ) || CONST_DOUBLE_P ( x ) ) n_const ++ ; } if ( n_const == n_elts ) const_vec = gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , 0 ) ) ; } else gcc_unreachable ( ) ; if ( const_vec != NULL_RTX && aarch64_simd_valid_immediate ( const_vec , NULL ) ) return const_vec ; else if ( ( const_dup = aarch64_simd_dup_constant ( vals ) ) != NULL_RTX ) return const_dup ; else if ( const_vec != NULL_RTX ) return const_vec ; else return NULL_RTX ; } </s>

Generate code to load VALS , which is a PARALLEL containing only constants ( for vec_init ) or CONST_VECTOR , efficiently into a register . Returns an RTX to copy into the register , or NULL_RTX for a PARALLEL that can not be converted into a CONST_VECTOR .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"ARM64 Conditional Compares"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT LHSTy ) const override { return MVT :: i8 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


"instruction requires a CPU feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> static void pop ( int rn ) { rtx x , sp_reg , reg ; if ( rn == FPUL_REG ) x = gen_pop_fpul ( ) ; else if ( rn == FPSCR_REG ) x = gen_pop_fpscr ( ) ; else if ( ( TARGET_SH4 || TARGET_SH2A_DOUBLE ) && TARGET_FMOVD && ! TARGET_FPU_SINGLE && FP_OR_XD_REGISTER_P ( rn ) ) { if ( FP_REGISTER_P ( rn ) && ( rn - FIRST_FP_REG ) & 1 ) return ; x = gen_pop_4 ( gen_rtx_REG ( DFmode , rn ) ) ; } else if ( TARGET_SH2E && FP_REGISTER_P ( rn ) ) x = gen_pop_e ( gen_rtx_REG ( SFmode , rn ) ) ; else x = gen_pop ( gen_rtx_REG ( SImode , rn ) ) ; x = emit_insn ( x ) ; sp_reg = gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) ; reg = copy_rtx ( GET_CODE ( PATTERN ( x ) ) == PARALLEL ? SET_DEST ( XVECEXP ( PATTERN ( x ) , 0 , 0 ) ) : SET_DEST ( PATTERN ( x ) ) ) ; add_reg_note ( x , REG_CFA_RESTORE , reg ) ; add_reg_note ( x , REG_CFA_ADJUST_CFA , gen_rtx_SET ( sp_reg , plus_constant ( SImode , sp_reg , GET_MODE_SIZE ( GET_MODE ( reg ) ) ) ) ) ; add_reg_note ( x , REG_INC , gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) ) ; RTX_FRAME_RELATED_P ( x ) = 1 ; } </s>

Output RTL to pop register RN from the stack .


<s> MachineInstr * AArch64InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , ArrayRef < unsigned > Ops , int FrameIndex ) const { if ( MI -> isCopy ( ) ) { unsigned DstReg = MI -> getOperand ( 0 ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; if ( SrcReg == AArch64 :: SP && TargetRegisterInfo :: isVirtualRegister ( DstReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( DstReg , & AArch64 :: GPR64RegClass ) ; return nullptr ; } if ( DstReg == AArch64 :: SP && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & AArch64 :: GPR64RegClass ) ; return nullptr ; } } return nullptr ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s>
bool
CSKYAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Operands
.
push_back
(
CSKYOperand
::
createToken
(
Name
,
NameLoc
)
)
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
return
false
;
if
(
parseOperand
(
Operands
,
Name
)
)
return
true
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
getLexer
(
)
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
)
return
true
;
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
getParser
(
)
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
getParser
(
)
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

CSKY
CSKY
CSKYOperand::createToken
"unexpected token"


<s> static void expand_setmem_epilogue_via_loop ( rtx destmem , rtx destptr , rtx value , rtx count , int max_size ) { count = expand_simple_binop ( counter_mode ( count ) , AND , count , GEN_INT ( max_size - 1 ) , count , 1 , OPTAB_DIRECT ) ; expand_set_or_cpymem_via_loop ( destmem , NULL , destptr , NULL , gen_lowpart ( QImode , value ) , count , QImode , 1 , max_size / 2 , true ) ; } </s>

Output code to set at most count & ( max_size - 1 ) bytes starting by DEST .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> bool M68kInstructionLookupBuilder :: isValid ( ) const { for ( unsigned I = 0 , E = numWords ( ) ; I < E ; ++ I ) if ( Mask [ I ] ) return true ; return false ; } </s>

Returns true if this iterator is still pointing at a valid entry .


<s> bool MLxExpansion :: runOnMachineFunction ( MachineFunction & Fn ) { TII = static_cast < const ARMBaseInstrInfo * > ( Fn . getTarget ( ) . getInstrInfo ( ) ) ; TRI = Fn . getTarget ( ) . getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; const ARMSubtarget * STI = & Fn . getTarget ( ) . getSubtarget < ARMSubtarget > ( ) ; isA9 = STI -> isCortexA9 ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= ExpandFPMLxInstructions ( MBB ) ; } return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s>
Value
*
HexagonTargetLowering
::
emitLoadLinked
(
IRBuilderBase
&
Builder
,
Type
*
ValueTy
,
Value
*
Addr
,
AtomicOrdering
Ord
)
const
{
BasicBlock
*
BB
=
Builder
.
GetInsertBlock
(
)
;
Module
*
M
=
BB
->
getParent
(
)
->
getParent
(
)
;
unsigned
SZ
=
ValueTy
->
getPrimitiveSizeInBits
(
)
;
assert
(
(
SZ
==
32
||
SZ
==
64
)
&&
"Only 32/64-bit atomic loads supported"
)
;
Intrinsic
::
ID
IntID
=
(
SZ
==
32
)
Intrinsic
::
hexagon_L2_loadw_locked
:
Intrinsic
::
hexagon_L4_loadd_locked
;
Function
*
Fn
=
Intrinsic
::
getDeclaration
(
M
,
IntID
)
;
auto
PtrTy
=
cast
<
PointerType
>
(
Addr
->
getType
(
)
)
;
PointerType
*
NewPtrTy
=
Builder
.
getIntNTy
(
SZ
)
->
getPointerTo
(
PtrTy
->
getAddressSpace
(
)
)
;
Addr
=
Builder
.
CreateBitCast
(
Addr
,
NewPtrTy
)
;
Value
*
Call
=
Builder
.
CreateCall
(
Fn
,
Addr
,
"larx"
)
;
return
Builder
.
CreateBitCast
(
Call
,
ValueTy
)
;
}
</s>

Perform a load-linked operation on Addr , returning a `` Value * '' with the corresponding pointee type .


<s> static void arm_elf_asm_constructor ( rtx symbol , int priority ) { arm_elf_asm_cdtor ( symbol , priority , true ) ; } </s>

Add a function to the list of static constructors .


<s>
const
char
*
getPassName
(
)
const
{
return
"Hexagon Packetizer"
;
}
</s>


<s> static int rs6000_issue_rate ( ) { switch ( rs6000_cpu_attr ) { case CPU_RIOS1 : case CPU_RS64A : case CPU_PPC601 : case CPU_PPC7450 : return 3 ; case CPU_PPC603 : case CPU_PPC750 : case CPU_PPC7400 : return 2 ; case CPU_RIOS2 : case CPU_PPC604 : case CPU_PPC604E : case CPU_PPC620 : case CPU_PPC630 : return 4 ; default : return 1 ; } } </s>

Return how many instructions the machine can issue per cycle .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { ForCodeSize = MF . getFunction ( ) -> optForSize ( ) ; Subtarget = & MF . getSubtarget < AArch64Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>


<s> static void loongarch_restore_reg ( rtx reg , rtx mem ) { rtx insn = loongarch_emit_move ( reg , mem ) ; rtx dwarf = NULL_RTX ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; REG_NOTES ( insn ) = dwarf ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>


<s> bool ARMTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { if ( ! Subtarget -> hasVFP3 ( ) ) return false ; if ( VT == MVT :: f16 && Subtarget -> hasFullFP16 ( ) ) return ARM_AM :: getFP16Imm ( Imm ) != - 1 ; if ( VT == MVT :: f32 ) return ARM_AM :: getFP32Imm ( Imm ) != - 1 ; if ( VT == MVT :: f64 && ! Subtarget -> isFPOnlySP ( ) ) return ARM_AM :: getFP64Imm ( Imm ) != - 1 ; return false ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> static bool ix86_optab_supported_p ( int op , machine_mode mode1 , machine_mode , optimization_type opt_type ) { switch ( op ) { case asin_optab : case acos_optab : case log1p_optab : case exp_optab : case exp10_optab : case exp2_optab : case expm1_optab : case ldexp_optab : case scalb_optab : case round_optab : case lround_optab : return opt_type == OPTIMIZE_FOR_SPEED ; case rint_optab : if ( SSE_FLOAT_MODE_P ( mode1 ) && TARGET_SSE_MATH && ! flag_trapping_math && ! TARGET_SSE4_1 && mode1 != HFmode ) return opt_type == OPTIMIZE_FOR_SPEED ; return true ; case floor_optab : case ceil_optab : case btrunc_optab : if ( ( ( SSE_FLOAT_MODE_P ( mode1 ) && TARGET_SSE_MATH && TARGET_SSE4_1 ) || mode1 == HFmode ) && ! flag_trapping_math ) return true ; return opt_type == OPTIMIZE_FOR_SPEED ; case rsqrt_optab : return opt_type == OPTIMIZE_FOR_SPEED && use_rsqrt_p ( mode1 ) ; default : return true ; } } </s>

Implement the TARGET_OPTAB_SUPPORTED_P hook .


<s>
void
AVRRegisterInfo
::
splitReg
(
Register
Reg
,
Register
&
LoReg
,
Register
&
HiReg
)
const
{
assert
(
AVR
::
DREGSRegClass
.
contains
(
Reg
)
&&
"can only split 16-bit registers"
)
;
LoReg
=
getSubReg
(
Reg
,
AVR
::
sub_lo
)
;
HiReg
=
getSubReg
(
Reg
,
AVR
::
sub_hi
)
;
}
</s>

Splits a 16-bit DREGS register into the lo/hi register pair .

AVR
AVR
AVR::DREGSRegClass
"can only split 16-bit registers"
AVR::sub_lo
AVR::sub_hi


<s> bool MipsAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { this -> MF = & MF ; SetupMachineFunction ( MF ) ; EmitConstantPool ( MF . getConstantPool ( ) ) ; EmitJumpTableInfo ( MF . getJumpTableInfo ( ) , MF ) ; O << "\n\n" ; emitFunctionStart ( MF ) ; for ( MachineFunction :: const_iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( I != MF . begin ( ) ) { printBasicBlockLabel ( I , true , true ) ; O << '\n' ; } for ( MachineBasicBlock :: const_iterator II = I -> begin ( ) , E = I -> end ( ) ; II != E ; ++ II ) { printInstruction ( II ) ; ++ EmittedInsts ; } O << '\n' ; } emitFunctionEnd ( MF ) ; return false ; } </s>


<s> int m32c_epilogue_uses ( int regno ATTRIBUTE_UNUSED ) { if ( cfun -> machine -> is_interrupt ) return 1 ; return 0 ; } </s>

Implements EPILOGUE_USES . Interrupts restore all registers .


<s> static unsigned getIntrinsicID ( const SDNode * N ) { unsigned Opcode = N -> getOpcode ( ) ; switch ( Opcode ) { default : return Intrinsic :: not_intrinsic ; case ISD :: INTRINSIC_WO_CHAIN : { unsigned IID = cast < ConstantSDNode > ( N -> getOperand ( 0 ) ) -> getZExtValue ( ) ; if ( IID < Intrinsic :: num_intrinsics ) return IID ; return Intrinsic :: not_intrinsic ; } } } </s>

Return the target intrinsic ID of a function , or 0 .


<s> gimple * fold ( gimple_folder & f ) const override { auto_vec < tree > vargs ( gimple_call_num_args ( f . call ) - 1 ) ; for ( unsigned i = 0 ; i < gimple_call_num_args ( f . call ) ; i ++ ) { if ( i == gimple_call_num_args ( f . call ) - 2 ) continue ; vargs . quick_push ( gimple_call_arg ( f . call , i ) ) ; } gimple * repl = gimple_build_call_vec ( gimple_call_fn ( f . call ) , vargs ) ; gimple_call_set_lhs ( repl , f . lhs ) ; tree new_vl = gimple_call_arg ( f . call , gimple_call_num_args ( f . call ) - 2 ) ; if ( integer_zerop ( new_vl ) ) { return repl ; } tree tmp_var = create_tmp_var ( size_type_node , "new_vl" ) ; tree decl = get_read_vl_decl ( ) ; gimple * g = gimple_build_call ( decl , 0 ) ; gimple_call_set_lhs ( g , tmp_var ) ; tree indirect = fold_build2 ( MEM_REF , size_type_node , gimple_call_arg ( f . call , gimple_call_num_args ( f . call ) - 2 ) , build_int_cst ( build_pointer_type ( size_type_node ) , 0 ) ) ; gassign * assign = gimple_build_assign ( indirect , tmp_var ) ; gsi_insert_after ( f . gsi , assign , GSI_SAME_STMT ) ; gsi_insert_after ( f . gsi , g , GSI_SAME_STMT ) ; return repl ; } </s>

Try to fold the call . Return the new statement on success and null on failure .


Hook to validate the current # pragma GCC target and set the state , and update the macros based on what was changed . If ARGS is NULL , then POP_TARGET is used to reset the options .


<s> bool X86TargetLowering :: isTruncateFree ( EVT VT1 , EVT VT2 ) const { if ( ! VT1 . isInteger ( ) || ! VT2 . isInteger ( ) ) return false ; unsigned NumBits1 = VT1 . getSizeInBits ( ) ; unsigned NumBits2 = VT2 . getSizeInBits ( ) ; if ( NumBits1 <= NumBits2 ) return false ; return true ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s>
void
HexagonInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
O
,
StringRef
Annot
)
{
const
char
packetPadding
[
]
=
"      "
;
const
char
startPacket
=
'{'
,
endPacket
=
'}'
;
if
(
MI
->
getOpcode
(
)
==
Hexagon
::
ENDLOOP0
)
{
MCInst
Nop
;
O
<<
packetPadding
<<
startPacket
<<
'\n'
;
Nop
.
setOpcode
(
Hexagon
::
NOP
)
;
printInstruction
(
&
Nop
,
O
)
;
O
<<
packetPadding
<<
endPacket
;
}
printInstruction
(
MI
,
O
)
;
printAnnotation
(
O
,
Annot
)
;
}
</s>

Print the specified MCInst to the specified raw_ostream .

Hexagon
Hexagon
"      "
Hexagon::ENDLOOP0
Hexagon::NOP


<s>
static
void
arm_asm_trampoline_template
(
FILE
*
f
)
{
if
(
TARGET_ARM
)
{
asm_fprintf
(
f
,
"\tldr\t%r, [%r, #0]\n"
,
STATIC_CHAIN_REGNUM
,
PC_REGNUM
)
;
asm_fprintf
(
f
,
"\tldr\t%r, [%r, #0]\n"
,
PC_REGNUM
,
PC_REGNUM
)
;
}
else
if
(
TARGET_THUMB2
)
{
asm_fprintf
(
f
,
"\tldr.w\t%r, [%r, #4]\n"
,
STATIC_CHAIN_REGNUM
,
PC_REGNUM
)
;
asm_fprintf
(
f
,
"\tldr.w\t%r, [%r, #4]\n"
,
PC_REGNUM
,
PC_REGNUM
)
;
}
else
{
ASM_OUTPUT_ALIGN
(
f
,
2
)
;
fprintf
(
f
,
"\t.code\t16\n"
)
;
fprintf
(
f
,
".Ltrampoline_start:\n"
)
;
asm_fprintf
(
f
,
"\tpush\t{r0, r1}\n"
)
;
asm_fprintf
(
f
,
"\tldr\tr0, [%r, #8]\n"
,
PC_REGNUM
)
;
asm_fprintf
(
f
,
"\tmov\t%r, r0\n"
,
STATIC_CHAIN_REGNUM
)
;
asm_fprintf
(
f
,
"\tldr\tr0, [%r, #8]\n"
,
PC_REGNUM
)
;
asm_fprintf
(
f
,
"\tstr\tr0, [%r, #4]\n"
,
SP_REGNUM
)
;
asm_fprintf
(
f
,
"\tpop\t{r0, %r}\n"
,
PC_REGNUM
)
;
}
assemble_aligned_integer
(
UNITS_PER_WORD
,
const0_rtx
)
;
assemble_aligned_integer
(
UNITS_PER_WORD
,
const0_rtx
)
;
}
</s>

Output assembler code for a block containing the constant parts of a trampoline , leaving space for the variable parts . On the ARM , ( if r8 is the static chain regnum , and remembering that referencing pc adds an offset of 8 ) the trampoline looks like : ldr r8 , [ pc , # 0 ] ldr pc , [ pc ] .word static chain value .word function 's address XXX FIXME : When the trampoline returns , r8 will be clobbered .


<s> int const_ok_for_dimode_op ( HOST_WIDE_INT i , enum rtx_code code ) { HOST_WIDE_INT hi_val = ( i >> 32 ) & 0xFFFFFFFF ; HOST_WIDE_INT lo_val = i & 0xFFFFFFFF ; rtx hi = GEN_INT ( hi_val ) ; rtx lo = GEN_INT ( lo_val ) ; if ( TARGET_THUMB1 ) return 0 ; switch ( code ) { case AND : case IOR : case XOR : return const_ok_for_op ( hi_val , code ) || hi_val == 0xFFFFFFFF || const_ok_for_op ( lo_val , code ) || lo_val == 0xFFFFFFFF ; case PLUS : return arm_not_operand ( hi , SImode ) && arm_add_operand ( lo , SImode ) ; default : return 0 ; } } </s>

Return true if I is a valid di mode constant for the operation CODE .


<s> unsigned PPCRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const PPCFrameLowering * TFI = getFrameLowering ( MF ) ; const unsigned DefaultSafety = 1 ; switch ( RC -> getID ( ) ) { default : return 0 ; case PPC :: G8RC_NOX0RegClassID : case PPC :: GPRC_NOR0RegClassID : case PPC :: SPERCRegClassID : case PPC :: G8RCRegClassID : case PPC :: GPRCRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 32 - FP - DefaultSafety ; } case PPC :: F8RCRegClassID : case PPC :: F4RCRegClassID : case PPC :: QFRCRegClassID : case PPC :: QSRCRegClassID : case PPC :: QBRCRegClassID : case PPC :: VRRCRegClassID : case PPC :: VFRCRegClassID : case PPC :: VSLRCRegClassID : return 32 - DefaultSafety ; case PPC :: VSRCRegClassID : case PPC :: VSFRCRegClassID : case PPC :: VSSRCRegClassID : return 64 - DefaultSafety ; case PPC :: CRRCRegClassID : return 8 - DefaultSafety ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s>
SDValue
SystemZTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
DL
,
SelectionDAG
&
DAG
)
const
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
SmallVector
<
CCValAssign
,
16
>
RetLocs
;
CCState
RetCCInfo
(
CallConv
,
IsVarArg
,
MF
,
TM
,
RetLocs
,
*
DAG
.
getContext
(
)
)
;
RetCCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_SystemZ
)
;
if
(
RetLocs
.
empty
(
)
)
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
Chain
)
;
SDValue
Glue
;
SmallVector
<
SDValue
,
4
>
RetOps
;
RetOps
.
push_back
(
Chain
)
;
for
(
unsigned
I
=
0
,
E
=
RetLocs
.
size
(
)
;
I
!=
E
;
++
I
)
{
CCValAssign
&
VA
=
RetLocs
[
I
]
;
SDValue
RetValue
=
OutVals
[
I
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
RetValue
=
convertValVTToLocVT
(
DAG
,
DL
,
VA
,
RetValue
)
;
unsigned
Reg
=
VA
.
getLocReg
(
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
Reg
,
RetValue
,
Glue
)
;
Glue
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
Reg
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Glue
.
getNode
(
)
)
RetOps
.
push_back
(
Glue
)
;
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> BitVector R600RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AMDGPU :: ZERO ) ; Reserved . set ( AMDGPU :: HALF ) ; Reserved . set ( AMDGPU :: ONE ) ; Reserved . set ( AMDGPU :: ONE_INT ) ; Reserved . set ( AMDGPU :: NEG_HALF ) ; Reserved . set ( AMDGPU :: NEG_ONE ) ; Reserved . set ( AMDGPU :: PV_X ) ; Reserved . set ( AMDGPU :: ALU_LITERAL_X ) ; Reserved . set ( AMDGPU :: ALU_CONST ) ; Reserved . set ( AMDGPU :: PREDICATE_BIT ) ; Reserved . set ( AMDGPU :: PRED_SEL_OFF ) ; Reserved . set ( AMDGPU :: PRED_SEL_ZERO ) ; Reserved . set ( AMDGPU :: PRED_SEL_ONE ) ; Reserved . set ( AMDGPU :: INDIRECT_BASE_ADDR ) ; for ( TargetRegisterClass :: iterator I = AMDGPU :: R600_AddrRegClass . begin ( ) , E = AMDGPU :: R600_AddrRegClass . end ( ) ; I != E ; ++ I ) { Reserved . set ( * I ) ; } const R600InstrInfo * RII = static_cast < const R600InstrInfo * > ( TM . getInstrInfo ( ) ) ; std :: vector < unsigned > IndirectRegs = RII -> getIndirectReservedRegs ( MF ) ; for ( std :: vector < unsigned > :: iterator I = IndirectRegs . begin ( ) , E = IndirectRegs . end ( ) ; I != E ; ++ I ) { Reserved . set ( * I ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


Emit the SVE equivalent of : ( set TMP1 ( unspec [ PRED KNOWN_PTRUE_P OP0 OP1 ] UNSPEC_COND_ < X1 > ) ) ( set TMP2 ( unspec [ PRED KNOWN_PTRUE_P OP0 OP1 ] UNSPEC_COND_ < X2 > ) ) ( set TARGET ( ior : PRED_MODE TMP1 TMP2 ) ) where < Xi > is the operation associated with comparison CODEi . KNOWN_PTRUE_P is true if PRED is known to be a PTRUE .


Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calling convention CallConv .


<s> enum reg_class mmix_preferred_output_reload_class ( rtx x ATTRIBUTE_UNUSED , enum reg_class class ) { return GET_CODE ( x ) == MOD && GET_MODE ( x ) == DImode ? REMAINDER_REG : class ; } </s>

PREFERRED_OUTPUT_RELOAD_CLASS . We need to extend the reload class of REMAINDER_REG and HIMULT_REG .


<s> rtx function_arg ( const struct sparc_args * cum , enum machine_mode mode , tree type , int named , int incoming_p ) { int regbase = ( incoming_p ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST ) ; int slotno , regno , padding ; enum mode_class mclass = GET_MODE_CLASS ( mode ) ; rtx reg ; slotno = function_arg_slotno ( cum , mode , type , named , incoming_p , & regno , & padding ) ; if ( slotno == - 1 ) return 0 ; if ( TARGET_ARCH32 ) { reg = gen_rtx_REG ( mode , regno ) ; return reg ; } if ( type && TREE_CODE ( type ) == RECORD_TYPE ) { gcc_assert ( int_size_in_bytes ( type ) <= 16 ) ; return function_arg_record_value ( type , mode , slotno , named , regbase ) ; } else if ( type && TREE_CODE ( type ) == UNION_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; return function_arg_union_value ( size , mode , slotno , regno ) ; } else if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; if ( mode == BLKmode ) return function_arg_vector_value ( size , TYPE_MODE ( TREE_TYPE ( type ) ) , SPARC_FP_ARG_FIRST + 2 * slotno ) ; else mclass = MODE_FLOAT ; } if ( ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) && SPARC_FP_REG_P ( regno ) ) { reg = gen_rtx_REG ( mode , regno ) ; if ( cum -> prototype_p || cum -> libcall_p ) { if ( ( regno - SPARC_FP_ARG_FIRST ) >= SPARC_INT_ARG_MAX * 2 ) return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) , gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ) ) ; else return reg ; } else { rtx v0 , v1 ; if ( ( regno - SPARC_FP_ARG_FIRST ) < SPARC_INT_ARG_MAX * 2 ) { int intreg ; if ( incoming_p ) return reg ; intreg = ( SPARC_OUTGOING_INT_ARG_FIRST + ( regno - SPARC_FP_ARG_FIRST ) / 2 ) ; v0 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , intreg ) , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , v0 , v1 ) ) ; } else { v0 = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , v0 , v1 ) ) ; } } } else { reg = gen_rtx_REG ( mode , regno ) ; } return reg ; } </s>

Return an RTL expression containing the register for the given mode , or 0 if the argument is to be passed on the stack . INCOMING_P is nonzero if this is an incoming argument to the current function .


<s>
SDValue
XCoreTargetLowering
::
LowerCall
(
SDValue
Chain
,
SDValue
Callee
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
bool
&
isTailCall
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
OutVals
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .

XCore
XCore
ISD::OutputArg
ISD::InputArg
"Unsupported calling convention"


<s>
void
ARMBaseInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
DebugLoc
::
getUnknownLoc
(
)
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
unsigned
Align
=
MFI
.
getObjectAlignment
(
FI
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
PseudoSourceValue
::
getFixedStack
(
FI
)
,
MachineMemOperand
::
MOLoad
,
0
,
MFI
.
getObjectSize
(
FI
)
,
Align
)
;
if
(
RC
==
ARM
::
tGPRRegisterClass
)
RC
=
ARM
::
GPRRegisterClass
;
if
(
RC
==
ARM
::
GPRRegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
LDR
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addReg
(
0
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
else
if
(
RC
==
ARM
::
DPRRegisterClass
||
RC
==
ARM
::
DPR_VFP2RegisterClass
||
RC
==
ARM
::
DPR_8RegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
VLDRD
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
else
if
(
RC
==
ARM
::
SPRRegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
VLDRS
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
else
{
assert
(
(
RC
==
ARM
::
QPRRegisterClass
||
RC
==
ARM
::
QPR_VFP2RegisterClass
||
RC
==
ARM
::
QPR_8RegisterClass
)
&&
"Unknown regclass!"
)
;
if
(
Align
>=
16
&&
(
getRegisterInfo
(
)
.
canRealignStack
(
MF
)
)
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
VLD1q64
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addImm
(
0
)
.
addImm
(
128
)
.
addMemOperand
(
MMO
)
)
;
}
else
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
VLDRQ
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> bool MipsSETargetLowering :: isEligibleForTailCallOptimization ( const CCState & CCInfo , unsigned NextStackOffset , const MipsFunctionInfo & FI ) const { if ( ! EnableMipsTailCalls ) return false ; if ( FI . isISR ( ) ) return false ; if ( CCInfo . getInRegsParamsCount ( ) > 0 || FI . hasByvalArg ( ) ) return false ; return NextStackOffset <= FI . getIncomingArgSize ( ) ; } </s>

Returns true if the call can be lowered as a tail call .


<s> static int must_parenthesize ( rtx op ) { const char * name ; switch ( GET_CODE ( op ) ) { case SYMBOL_REF : name = XSTR ( op , 0 ) ; return ( strcasecmp ( name , "a" ) == 0 || strcasecmp ( name , "b" ) == 0 || strcasecmp ( name , "d" ) == 0 || strcasecmp ( name , "x" ) == 0 || strcasecmp ( name , "y" ) == 0 || strcasecmp ( name , "ix" ) == 0 || strcasecmp ( name , "iy" ) == 0 || strcasecmp ( name , "pc" ) == 0 || strcasecmp ( name , "sp" ) == 0 || strcasecmp ( name , "ccr" ) == 0 ) ? 1 : 0 ; case PLUS : case MINUS : return must_parenthesize ( XEXP ( op , 0 ) ) || must_parenthesize ( XEXP ( op , 1 ) ) ; case MEM : case CONST : case ZERO_EXTEND : case SIGN_EXTEND : return must_parenthesize ( XEXP ( op , 0 ) ) ; case CONST_DOUBLE : case CONST_INT : case LABEL_REF : case CODE_LABEL : default : return 0 ; } } </s>

Returns true if the operand 'op ' must be printed with parenthesis around it . This must be done only if there is a symbol whose name is a processor register .


<s> void Tile64FrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Tile64InstrInfo & TII = * static_cast < const Tile64InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; const Tile64RegisterInfo & TRI = * static_cast < const Tile64RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int maxCallFrameSize = ( int ) MFI -> getMaxCallFrameSize ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; NumBytes += maxCallFrameSize ; NumBytes += abs ( getOffsetOfLocalArea ( ) ) ; NumBytes = - ( ( NumBytes + 7 ) & ~ 7 ) ; int StackOffset = ( int ) MFI -> hasCalls ( ) ? MF . getInfo < Tile64MachineFunctionInfo > ( ) -> getArgAreaOffset ( ) : 0 ; NumBytes += ( - StackOffset ) ; BuildMI ( MBB , MBBI , DL , TII . get ( T64 :: SW ) ) . addReg ( T64 :: StackPointer ) . addReg ( T64 :: LinkRegister ) ; BuildMI ( MBB , MBBI , DL , TII . get ( T64 :: MOVE ) , T64 :: FramePointer ) . addReg ( T64 :: StackPointer ) ; TRI . addOffset ( MBB , MBBI , DL , T64 :: StackPointer , T64 :: StackPointer , NumBytes ) ; unsigned TmpReg = T64 :: R10 ; if ( MFI -> hasCalls ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( T64 :: ADDI ) , TmpReg ) . addReg ( T64 :: StackPointer ) . addImm ( 4 ) ; BuildMI ( MBB , MBBI , DL , TII . get ( T64 :: SW ) ) . addReg ( TmpReg ) . addReg ( T64 :: FramePointer ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s>
bool
X86DAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
SDValue
Op0
,
Op1
,
Op2
,
Op3
,
Op4
;
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
case
InlineAsm
::
Constraint_o
:
case
InlineAsm
::
Constraint_v
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_X
:
if
(
!
selectAddr
(
nullptr
,
Op
,
Op0
,
Op1
,
Op2
,
Op3
,
Op4
)
)
return
true
;
break
;
}
OutOps
.
push_back
(
Op0
)
;
OutOps
.
push_back
(
Op1
)
;
OutOps
.
push_back
(
Op2
)
;
OutOps
.
push_back
(
Op3
)
;
OutOps
.
push_back
(
Op4
)
;
return
false
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> SDValue WebAssemblySelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool IsVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { if ( ! DAG . getMachineFunction ( ) . getSubtarget < WebAssemblySubtarget > ( ) . hasBulkMemory ( ) ) return SDValue ( ) ; SDValue MemIdx = DAG . getConstant ( 0 , DL , MVT :: i32 ) ; return DAG . getNode ( WebAssemblyISD :: MEMORY_COPY , DL , MVT :: Other , { Chain , MemIdx , MemIdx , Dst , Src , DAG . getZExtOrTrunc ( Size , DL , MVT :: i32 ) } ) ; } </s>

Emit target-specific code that performs a memcpy .


<s> BitVector AArch64RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const AArch64FrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , AArch64 :: WSP ) ; markSuperRegs ( Reserved , AArch64 :: WZR ) ; const Function & F = MF . getFunction ( ) ; if ( F . getCallingConv ( ) == CallingConv :: Mono ) markSuperRegs ( Reserved , AArch64 :: W15 ) ; if ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) markSuperRegs ( Reserved , AArch64 :: W29 ) ; if ( MF . getSubtarget < AArch64Subtarget > ( ) . isX18Reserved ( ) ) markSuperRegs ( Reserved , AArch64 :: W18 ) ; if ( hasBasePointer ( MF ) ) markSuperRegs ( Reserved , AArch64 :: W19 ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>


<s> const char * output_move_double ( rtx * operands ) { handle_move_double ( operands , output_reg_adjust , output_compadr , output_movsi ) ; return "" ; } </s>

Return appropriate code to load up an 8 byte integer or floating point value


"rs6000_cannot_change_mode_class, return %s, from = %s, "

Debug version of rs6000_cannot_change_mode_class .


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> unsigned DCPU16RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? DCPU16 :: J : DCPU16 :: SP ; } </s>


<s> MachineBasicBlock :: iterator MipsFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { unsigned SP = STI . getABI ( ) . IsN64 ( ) ? Mips :: SP_64 : Mips :: SP ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( 0 ) . getImm ( ) ; if ( I -> getOpcode ( ) == Mips :: ADJCALLSTACKDOWN ) Amount = - Amount ; STI . getInstrInfo ( ) -> adjustStackPtr ( SP , Amount , MBB , I ) ; } return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

Mips Mips Mips::SP_64 Mips::SP 0 Mips::ADJCALLSTACKDOWN


<s> static int epilogue_renumber ( register rtx * where , int test ) { register const char * fmt ; register int i ; register enum rtx_code code ; if ( * where == 0 ) return 0 ; code = GET_CODE ( * where ) ; switch ( code ) { case REG : if ( REGNO ( * where ) >= 8 && REGNO ( * where ) < 24 ) return 1 ; if ( ! test && REGNO ( * where ) >= 24 && REGNO ( * where ) < 32 ) * where = gen_rtx_REG ( GET_MODE ( * where ) , OUTGOING_REGNO ( REGNO ( * where ) ) ) ; case SCRATCH : case CC0 : case PC : case CONST_INT : case CONST_DOUBLE : return 0 ; case PLUS : if ( GET_CODE ( XEXP ( * where , 0 ) ) == REG && REGNO ( XEXP ( * where , 0 ) ) == HARD_FRAME_POINTER_REGNUM && ( GET_CODE ( XEXP ( * where , 1 ) ) != CONST_INT || INTVAL ( XEXP ( * where , 1 ) ) < SPARC_STACK_BIAS ) ) return 1 ; break ; case MEM : if ( SPARC_STACK_BIAS && GET_CODE ( XEXP ( * where , 0 ) ) == REG && REGNO ( XEXP ( * where , 0 ) ) == HARD_FRAME_POINTER_REGNUM ) return 1 ; break ; default : break ; } fmt = GET_RTX_FORMAT ( code ) ; for ( i = GET_RTX_LENGTH ( code ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { register int j ; for ( j = XVECLEN ( * where , i ) - 1 ; j >= 0 ; j -- ) if ( epilogue_renumber ( & ( XVECEXP ( * where , i , j ) ) , test ) ) return 1 ; } else if ( fmt [ i ] == 'e' && epilogue_renumber ( & ( XEXP ( * where , i ) ) , test ) ) return 1 ; } return 0 ; } </s>

Return 1 , if any of the registers of the instruction are % l [ 0-7 ] or % o [ 0-7 ] . Such instructions can not be used in the delay slot of return insn on v9 . If TEST is 0 , also rename all % i [ 0-7 ] registers to their % o [ 0-7 ] counterparts .


<s>
SDValue
OR1KTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
CTTZ
:
return
LowerCTTZ
(
Op
,
DAG
)
;
case
ISD
::
CTTZ_ZERO_UNDEF
:
return
LowerCTTZ_ZERO_UNDEF
(
Op
,
DAG
)
;
case
ISD
::
CTLZ
:
case
ISD
::
CTLZ_ZERO_UNDEF
:
return
LowerCTLZ
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> void OpenRISCRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , RegScavenger * RS ) const { assert ( 0 && "Unimplemented" ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> void Mips16FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: Move32R16 ) , Mips :: SP ) . addReg ( Mips :: S0 ) ; TII . restoreFrame ( Mips :: SP , StackSize , MBB , MBBI ) ; } </s>

Mips Mips Mips Mips Mips::Move32R16 Mips::SP Mips::S0 Mips::SP


"setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n"

Worker function for TARGET_SETUP_INCOMING_VARARGS .


"Expected integer or floating type for store"


<s> bool RISCVTargetLowering :: isEligibleForTailCallOptimization ( CCState & CCInfo , CallLoweringInfo & CLI , MachineFunction & MF , const SmallVector < CCValAssign , 16 > & ArgLocs ) const { auto & Callee = CLI . Callee ; auto CalleeCC = CLI . CallConv ; auto IsVarArg = CLI . IsVarArg ; auto & Outs = CLI . Outs ; auto & Caller = MF . getFunction ( ) ; auto CallerCC = Caller . getCallingConv ( ) ; if ( Caller . getFnAttribute ( "disable-tail-calls" ) . getValueAsString ( ) == "true" ) return false ; if ( Caller . hasFnAttribute ( "interrupt" ) ) return false ; if ( IsVarArg ) return false ; if ( CCInfo . getNextStackOffset ( ) != 0 ) return false ; for ( auto & VA : ArgLocs ) if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; auto IsCallerStructRet = Caller . hasStructRetAttr ( ) ; auto IsCalleeStructRet = Outs . empty ( ) ? false : Outs [ 0 ] . Flags . isSRet ( ) ; if ( IsCallerStructRet || IsCalleeStructRet ) return false ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; if ( GV -> hasExternalWeakLinkage ( ) ) return false ; } const RISCVRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( CalleeCC != CallerCC ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } for ( auto & Arg : Outs ) if ( Arg . Flags . isByVal ( ) ) return false ; return true ; } </s>

RISCV RISCV 16 "disable-tail-calls" "true" "interrupt" 0 0 RISCV


<s> bool ARMSubtarget :: isGVIndirectSymbol ( const GlobalValue * GV ) const { if ( ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return true ; if ( isTargetDarwin ( ) && TM . isPositionIndependent ( ) && ( GV -> isDeclarationForLinker ( ) || GV -> hasCommonLinkage ( ) ) ) return true ; return false ; } </s>

True if the GV will be accessed via an indirect symbol .


<s> bool parsePrimaryExpr ( const MCExpr * & Res , SMLoc & EndLoc ) override { return MCTargetAsmParser :: parsePrimaryExpr ( Res , EndLoc ) ; } </s>


<s> void BPFMCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; unsigned Opcode = MI . getOpcode ( ) ; support :: endian :: Writer OSE ( OS , IsLittleEndian ? support :: little : support :: big ) ; if ( Opcode == BPF :: LD_imm64 || Opcode == BPF :: LD_pseudo ) { uint64_t Value = getBinaryCodeForInstr ( MI , Fixups , STI ) ; OS << char ( Value >> 56 ) ; if ( IsLittleEndian ) OS << char ( ( Value >> 48 ) & 0xff ) ; else OS << char ( SwapBits ( ( Value >> 48 ) & 0xff ) ) ; OSE . write < uint16_t > ( 0 ) ; OSE . write < uint32_t > ( Value & 0xffffFFFF ) ; const MCOperand & MO = MI . getOperand ( 1 ) ; uint64_t Imm = MO . isImm ( ) ? MO . getImm ( ) : 0 ; OSE . write < uint8_t > ( 0 ) ; OSE . write < uint8_t > ( 0 ) ; OSE . write < uint16_t > ( 0 ) ; OSE . write < uint32_t > ( Imm >> 32 ) ; } else { uint64_t Value = getBinaryCodeForInstr ( MI , Fixups , STI ) ; OS << char ( Value >> 56 ) ; if ( IsLittleEndian ) OS << char ( ( Value >> 48 ) & 0xff ) ; else OS << char ( SwapBits ( ( Value >> 48 ) & 0xff ) ) ; OSE . write < uint16_t > ( ( Value >> 32 ) & 0xffff ) ; OSE . write < uint32_t > ( Value & 0xffffFFFF ) ; } } </s>

Encode the given Inst to bytes and append to CB .


<s> static void arm_override_options_after_change ( void ) { arm_override_options_after_change_1 ( & global_options , & global_options_set ) ; } </s>


<s> static rtx_insn * find_next_insn_start ( rtx_insn * insn ) { if ( GET_MODE ( insn ) == SImode ) { while ( GET_MODE ( insn ) != QImode ) insn = NEXT_INSN ( insn ) ; } return NEXT_INSN ( insn ) ; } </s>

This function acts like NEXT_INSN , but is aware of three-insn bundles and skips all subsequent parallel instructions if INSN is the start of such a group .


<s> bool AArch64CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { auto & Args = F . getArgumentList ( ) ; MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned i = 0 ; for ( auto & Arg : Args ) { ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + 1 , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs , ArrayRef < uint64_t > Offsets ) { MIRBuilder . buildSequence ( VRegs [ i ] , Regs , Offsets ) ; } ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI ) ; if ( ! handleAssignments ( MIRBuilder , AssignFn , SplitArgs , Handler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> void AlphaInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; if ( RC == Alpha :: F4RCRegisterClass ) BuildMI ( MBB , MI , DL , get ( Alpha :: STS ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIdx ) . addReg ( Alpha :: F31 ) ; else if ( RC == Alpha :: F8RCRegisterClass ) BuildMI ( MBB , MI , DL , get ( Alpha :: STT ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIdx ) . addReg ( Alpha :: F31 ) ; else if ( RC == Alpha :: GPRCRegisterClass ) BuildMI ( MBB , MI , DL , get ( Alpha :: STQ ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIdx ) . addReg ( Alpha :: F31 ) ; else abort ( ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> void X86FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { const Function * Fn = MF . getFunction ( ) ; if ( ! STI . is64Bit ( ) || ! MF . getMMI ( ) . hasEHFunclets ( ) || classifyEHPersonality ( Fn -> getPersonalityFn ( ) ) != EHPersonality :: MSVC_CXX ) return ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int64_t MinFixedObjOffset = - SlotSize ; for ( int I = MFI -> getObjectIndexBegin ( ) ; I < 0 ; ++ I ) MinFixedObjOffset = std :: min ( MinFixedObjOffset , MFI -> getObjectOffset ( I ) ) ; int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize ; int UnwindHelpFI = MFI -> CreateFixedObject ( SlotSize , UnwindHelpOffset , false ) ; MF . getWinEHFuncInfo ( ) -> UnwindHelpFrameIdx = UnwindHelpFI ; MachineBasicBlock & MBB = MF . front ( ) ; auto MBBI = MBB . begin ( ) ; while ( MBBI != MBB . end ( ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) ) ++ MBBI ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; addFrameReference ( BuildMI ( MBB , MBBI , DL , TII . get ( X86 :: MOV64mi32 ) ) , UnwindHelpFI ) . addImm ( - 2 ) ; } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> unsigned RISCVTTIImpl :: getRegUsageForType ( Type * Ty ) { TypeSize Size = Ty -> getPrimitiveSizeInBits ( ) ; if ( Ty -> isVectorTy ( ) ) { if ( Size . isScalable ( ) && ST -> hasVInstructions ( ) ) return divideCeil ( Size . getKnownMinValue ( ) , RISCV :: RVVBitsPerBlock ) ; if ( ST -> useRVVForFixedLengthVectors ( ) ) return divideCeil ( Size , ST -> getMinRVVVectorSizeInBits ( ) ) ; } return BaseT :: getRegUsageForType ( Ty ) ; } </s>

Returns the estimated number of registers required to represent Ty .


<s> void HexagonFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { auto & HRI = * MF . getSubtarget < HexagonSubtarget > ( ) . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; MachineBasicBlock * PrologB = & MF . front ( ) , * EpilogB = nullptr ; if ( EnableShrinkWrapping ) findShrunkPrologEpilog ( MF , PrologB , EpilogB ) ; bool PrologueStubs = false ; insertCSRSpillsInBlock ( * PrologB , CSI , HRI , PrologueStubs ) ; insertPrologueInBlock ( * PrologB , PrologueStubs ) ; updateEntryPaths ( MF , * PrologB ) ; if ( EpilogB ) { insertCSRRestoresInBlock ( * EpilogB , CSI , HRI ) ; insertEpilogueInBlock ( * EpilogB ) ; } else { for ( auto & B : MF ) if ( B . isReturnBlock ( ) ) insertCSRRestoresInBlock ( B , CSI , HRI ) ; for ( auto & B : MF ) if ( B . isReturnBlock ( ) ) insertEpilogueInBlock ( B ) ; for ( auto & B : MF ) { if ( B . empty ( ) ) continue ; MachineInstr * RetI = getReturn ( B ) ; if ( ! RetI || isRestoreCall ( RetI -> getOpcode ( ) ) ) continue ; for ( auto & R : CSI ) RetI -> addOperand ( MachineOperand :: CreateReg ( R . getReg ( ) , false , true ) ) ; } } if ( EpilogB ) { unsigned MaxBN = MF . getNumBlockIDs ( ) ; BitVector DoneT ( MaxBN + 1 ) , DoneF ( MaxBN + 1 ) , Path ( MaxBN + 1 ) ; updateExitPaths ( * EpilogB , * EpilogB , DoneT , DoneF , Path ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool VEFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> void ix86_move_vector_high_sse_to_mmx ( rtx op ) { rtx mask = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 4 , GEN_INT ( 0 ) , GEN_INT ( 2 ) , GEN_INT ( 0 ) , GEN_INT ( 0 ) ) ) ; rtx dest = lowpart_subreg ( V4SImode , op , GET_MODE ( op ) ) ; op = gen_rtx_VEC_SELECT ( V4SImode , dest , mask ) ; rtx insn = gen_rtx_SET ( dest , op ) ; emit_insn ( insn ) ; } </s>


<s> void h8300_expand_store ( rtx operands [ ] ) { rtx dest = operands [ 0 ] ; enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; rtx op0 = operands [ 2 ] ; rtx op1 = operands [ 3 ] ; rtx tmp ; tmp = gen_rtx_COMPARE ( VOIDmode , op0 , op1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cc0_rtx , tmp ) ) ; tmp = gen_rtx_fmt_ee ( code , GET_MODE ( dest ) , cc0_rtx , const0_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , tmp ) ) ; } </s>


<s> virtual unsigned int execute ( function * ) { return insert_uses ( ) ; } </s>


<s> static rtx ia64_function_value ( const_tree valtype , const_tree fn_decl_or_type , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode mode ; machine_mode hfa_mode ; int unsignedp ; const_tree func = fn_decl_or_type ; if ( fn_decl_or_type && ! DECL_P ( fn_decl_or_type ) ) func = NULL ; mode = TYPE_MODE ( valtype ) ; hfa_mode = hfa_element_mode ( valtype , 0 ) ; if ( hfa_mode != VOIDmode ) { rtx loc [ 8 ] ; int i ; int hfa_size ; int byte_size ; int offset ; hfa_size = GET_MODE_SIZE ( hfa_mode ) ; byte_size = ( ( mode == BLKmode ) ? int_size_in_bytes ( valtype ) : GET_MODE_SIZE ( mode ) ) ; offset = 0 ; for ( i = 0 ; offset < byte_size ; i ++ ) { loc [ i ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( hfa_mode , FR_ARG_FIRST + i ) , GEN_INT ( offset ) ) ; offset += hfa_size ; } return gen_rtx_PARALLEL ( mode , gen_rtvec_v ( i , loc ) ) ; } else if ( FLOAT_TYPE_P ( valtype ) && mode != TFmode && mode != TCmode ) return gen_rtx_REG ( mode , FR_ARG_FIRST ) ; else { bool need_parallel = false ; if ( BYTES_BIG_ENDIAN && ( mode == BLKmode || ( valtype && AGGREGATE_TYPE_P ( valtype ) ) ) ) need_parallel = true ; else if ( mode == XFmode || mode == XCmode || mode == RFmode ) need_parallel = true ; if ( need_parallel ) { rtx loc [ 8 ] ; int offset ; int bytesize ; int i ; offset = 0 ; bytesize = int_size_in_bytes ( valtype ) ; if ( bytesize == 0 ) return gen_rtx_REG ( mode , GR_RET_FIRST ) ; for ( i = 0 ; offset < bytesize ; i ++ ) { loc [ i ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , GR_RET_FIRST + i ) , GEN_INT ( offset ) ) ; offset += UNITS_PER_WORD ; } return gen_rtx_PARALLEL ( mode , gen_rtvec_v ( i , loc ) ) ; } mode = promote_function_mode ( valtype , mode , & unsignedp , func ? TREE_TYPE ( func ) : NULL_TREE , true ) ; return gen_rtx_REG ( mode , GR_RET_FIRST ) ; } } </s>

Return rtx for register that holds the function return value .


<s> bool MipsFastISel :: isTypeLegal ( Type * Ty , MVT & VT ) { EVT evt = TLI . getValueType ( DL , Ty , true ) ; if ( evt == MVT :: Other || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; return TLI . isTypeLegal ( VT ) ; } </s>


<s> void M680x0FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; M680x0MachineFunctionInfo * M680x0FI = MF . getInfo < M680x0MachineFunctionInfo > ( ) ; int64_t TailCallReturnAddrDelta = M680x0FI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < 0 ) { MFI . CreateFixedObject ( - TailCallReturnAddrDelta , TailCallReturnAddrDelta - SlotSize , true ) ; } if ( TRI -> hasBasePointer ( MF ) ) { SavedRegs . set ( TRI -> getBaseRegister ( ) ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> void X86InsertPrefetch :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesAll ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool aarch64_and_bitmask_imm ( unsigned HOST_WIDE_INT val_in , machine_mode mode ) { scalar_int_mode int_mode ; if ( ! is_a < scalar_int_mode > ( mode , & int_mode ) ) return false ; if ( aarch64_bitmask_imm ( val_in , int_mode ) ) return false ; if ( aarch64_move_imm ( val_in , int_mode ) ) return false ; unsigned HOST_WIDE_INT imm2 = aarch64_and_split_imm2 ( val_in ) ; return aarch64_bitmask_imm ( imm2 , int_mode ) ; } </s>

Return true if VAL_IN is a valid 'and ' bitmask immediate .


<s> const uint32_t * getRegMaskBits ( RegisterId R ) const { return RegMasks . get ( TargetRegisterInfo :: stackSlot2Index ( R ) ) ; } </s>

Returns an array of register mask pointers corresponding to getRegMaskSlots ( ) .


<s> const char * P2TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case P2ISD :: RET : return "P2RET" ; case P2ISD :: CALL : return "P2CALL" ; case P2ISD :: GAWRAPPER : return "P2GAWRAPPER" ; default : return nullptr ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s>
void
aarch64_simd_lane_bounds
(
rtx
operand
,
HOST_WIDE_INT
low
,
HOST_WIDE_INT
high
,
const_tree
exp
)
{
HOST_WIDE_INT
lane
;
gcc_assert
(
CONST_INT_P
(
operand
)
)
;
lane
=
INTVAL
(
operand
)
;
if
(
lane
<
low
||
lane
>=
high
)
{
if
(
exp
)
error
(
"%Klane %wd out of range %wd - %wd"
,
exp
,
lane
,
low
,
high
1
)
;
else
error
(
"lane %wd out of range %wd - %wd"
,
lane
,
low
,
high
1
)
;
}
}
</s>

Bounds-check lanes . Ensure OPERAND lies between LOW ( inclusive ) and HIGH ( exclusive ) .


<s> virtual MVT getShiftAmountTy ( EVT LHSTy ) const { return MVT :: i16 ; } </s>

Returns the type for the shift amount of a shift opcode .


<s> static void store_reg ( int reg , HOST_WIDE_INT disp , int base ) { rtx dest , src , basereg ; rtx_insn * insn ; src = gen_rtx_REG ( word_mode , reg ) ; basereg = gen_rtx_REG ( Pmode , base ) ; if ( VAL_14_BITS_P ( disp ) ) { dest = gen_rtx_MEM ( word_mode , plus_constant ( Pmode , basereg , disp ) ) ; insn = emit_move_insn ( dest , src ) ; } else if ( TARGET_64BIT && ! VAL_32_BITS_P ( disp ) ) { rtx delta = GEN_INT ( disp ) ; rtx tmpreg = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( tmpreg , delta ) ; insn = emit_move_insn ( tmpreg , gen_rtx_PLUS ( Pmode , tmpreg , basereg ) ) ; if ( DO_FRAME_NOTES ) { add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , tmpreg , gen_rtx_PLUS ( Pmode , basereg , delta ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } dest = gen_rtx_MEM ( word_mode , tmpreg ) ; insn = emit_move_insn ( dest , src ) ; } else { rtx delta = GEN_INT ( disp ) ; rtx high = gen_rtx_PLUS ( Pmode , basereg , gen_rtx_HIGH ( Pmode , delta ) ) ; rtx tmpreg = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( tmpreg , high ) ; dest = gen_rtx_MEM ( word_mode , gen_rtx_LO_SUM ( Pmode , tmpreg , delta ) ) ; insn = emit_move_insn ( dest , src ) ; if ( DO_FRAME_NOTES ) add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( word_mode , gen_rtx_PLUS ( word_mode , basereg , delta ) ) , src ) ) ; } if ( DO_FRAME_NOTES ) RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Emit RTL to store REG at the memory location specified by BASE+DISP . Handle case where DISP > 8k by using the add_high_const patterns . Note in DISP > 8k case , we will leave the high part of the address in % r1 . There is code in expand_hppa_ { prologue , epilogue } that knows this .


<s> static bool riscv_valid_lo_sum_p ( enum riscv_symbol_type sym_type , machine_mode mode , rtx x ) { int align , size ; if ( riscv_symbol_insns ( sym_type ) == 0 ) return false ; if ( ! riscv_split_symbol_type ( sym_type ) ) return false ; if ( mode == BLKmode ) { rtx offset ; split_const ( x , & x , & offset ) ; if ( ! SYMBOL_REF_P ( x ) ) return false ; align = ( SYMBOL_REF_DECL ( x ) ? DECL_ALIGN ( SYMBOL_REF_DECL ( x ) ) : 1 ) ; size = ( SYMBOL_REF_DECL ( x ) && DECL_SIZE ( SYMBOL_REF_DECL ( x ) ) ? tree_to_uhwi ( DECL_SIZE ( SYMBOL_REF_DECL ( x ) ) ) : 2 * BITS_PER_WORD ) ; } else { align = GET_MODE_ALIGNMENT ( mode ) ; size = GET_MODE_BITSIZE ( mode ) . to_constant ( ) ; } if ( size > BITS_PER_WORD && ( ! TARGET_STRICT_ALIGN || size > align ) ) return false ; return true ; } </s>

Return true if a LO_SUM can address a value of mode MODE when the LO_SUM symbol has type SYM_TYPE .


<s>
void
GBZ80MCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
unsigned
Size
=
Desc
.
getSize
(
)
;
assert
(
Size
>
0
&&
"Instruction size cannot be zero"
)
;
uint64_t
BinaryOpCode
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
emitInstruction
(
BinaryOpCode
,
Size
,
STI
,
OS
)
;
}
</s>

Encode the given Inst to bytes and append to CB .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> bool MipsInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock & MBB = * MI -> getParent ( ) ; switch ( MI -> getDesc ( ) . getOpcode ( ) ) { default : return false ; case Mips :: RetRA : ExpandRetRA ( MBB , MI , Mips :: RET ) ; break ; case Mips :: RetRA16 : ExpandRetRA ( MBB , MI , Mips :: RET16 ) ; break ; case Mips :: BuildPairF64 : ExpandBuildPairF64 ( MBB , MI ) ; break ; case Mips :: ExtractElementF64 : ExpandExtractElementF64 ( MBB , MI ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> bool MipsTargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createMipsDelaySlotFillerPass ( * this ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


"FMA or FMUL at insn %d but destination "

"register (%s) has different parity from expected to "

"Destination register of insn %d could not be "

"renamed. Dependent FMA insns will use this parity from "

Rename the destination register of a single FMUL or FMADD/FMSUB instruction represented by FMA_NODE to a register that respect the target parity for FOREST or with same parity of the instruction represented by its parent node if it has one .


"SystemZ DAG preprocessing replacing:\nOld:    "

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> int avr_io_address_p ( rtx x , int size ) { return ( optimize > 0 && GET_CODE ( x ) == CONST_INT && INTVAL ( x ) >= 0x20 && INTVAL ( x ) <= 0x60 - size ) ; } </s>

Returns 1 if X is a valid address for an I/O register of size SIZE ( 1 or 2 ) . Used for lds/sts - > in/out optimization . Add 0x20 to SIZE to check for the lower half of I/O space ( for cbi/sbi/sbic/sbis ) .


<s> static bool classof ( const DiagnosticInfo * DI ) { return DI -> getKind ( ) == getKindID ( ) ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> static rtx rx_function_arg ( cumulative_args_t cum , const function_arg_info & arg ) { unsigned int next_reg ; unsigned int bytes_so_far = * get_cumulative_args ( cum ) ; unsigned int size ; unsigned int rounded_size ; size = arg . promoted_size_in_bytes ( ) ; if ( size < 1 ) return NULL_RTX ; rounded_size = rx_round_up ( size , UNITS_PER_WORD ) ; if ( rounded_size + bytes_so_far > MAX_NUM_ARG_BYTES ) return NULL_RTX ; if ( ! arg . named ) return NULL_RTX ; if ( ( arg . type == NULL || AGGREGATE_TYPE_P ( arg . type ) ) && ( size % UNITS_PER_WORD ) != 0 ) return NULL_RTX ; next_reg = ( bytes_so_far / UNITS_PER_WORD ) + 1 ; return gen_rtx_REG ( arg . mode , next_reg ) ; } </s>

Return an RTL expression describing the register holding a function parameter of mode MODE and type TYPE or NULL_RTX if the parameter should be passed on the stack . CUM describes the previous parameters to the function and NAMED is false if the parameter is part of a variable parameter list , or the last named parameter before the start of a variable parameter list .


<s> bool EquivSubstPass :: runOnMachineFunction ( MachineFunction & Fn ) { const TargetInstrInfo * TII = Fn . getSubtarget ( ) . getInstrInfo ( ) ; if ( ! RNG ) RNG . reset ( Fn . getFunction ( ) -> getParent ( ) -> createRNG ( this ) ) ; bool Changed = false ; std :: vector < const EquivInsnFilter * > Candidates ; for ( MachineFunction :: iterator BB = Fn . begin ( ) , E = Fn . end ( ) ; BB != E ; ++ BB ) for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ) { ++ PreEquivSubstInstructionCount ; Candidates . clear ( ) ; for ( size_t i = 0 ; i < array_lengthof ( Filters ) ; i ++ ) if ( Filters [ i ] -> check ( * BB , * I ) ) Candidates . push_back ( Filters [ i ] ) ; if ( Candidates . empty ( ) ) { ++ I ; continue ; } unsigned int Roll = RNG -> Random ( 100 ) ; ++ EquivSubstCandidates ; if ( Roll >= multicompiler :: EquivSubstPercentage ) { ++ I ; continue ; } unsigned int Pick = RNG -> Random ( Candidates . size ( ) ) ; MachineBasicBlock :: iterator J = I ; ++ I ; Candidates [ Pick ] -> subst ( * BB , TII , J ) ; Changed = true ; ++ EquivSubstituted ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


"********* Hexagon Hardware Loops *********\n"


<s> bool X86TTIImpl :: isLegalMaskedLoad ( Type * DataTy ) { Type * ScalarTy = DataTy -> getScalarType ( ) ; int DataWidth = isa < PointerType > ( ScalarTy ) ? DL . getPointerSizeInBits ( ) : ScalarTy -> getPrimitiveSizeInBits ( ) ; return ( DataWidth >= 32 && ST -> hasAVX ( ) ) ; } </s>

Return true if the target supports masked load .


<s> BitVector SIRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; reserveRegisterTuples ( Reserved , AMDGPU :: EXEC ) ; reserveRegisterTuples ( Reserved , AMDGPU :: FLAT_SCR ) ; reserveRegisterTuples ( Reserved , AMDGPU :: M0 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_SHARED_BASE ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_SHARED_LIMIT ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_PRIVATE_BASE ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_PRIVATE_LIMIT ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TBA ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TMA ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP0_TTMP1 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP2_TTMP3 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP4_TTMP5 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP6_TTMP7 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP8_TTMP9 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP10_TTMP11 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP12_TTMP13 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP14_TTMP15 ) ; const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; unsigned MaxNumSGPRs = ST . getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = AMDGPU :: SGPR_32RegClass . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = AMDGPU :: SGPR_32RegClass . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } unsigned MaxNumVGPRs = ST . getMaxNumVGPRs ( MF ) ; unsigned TotalNumVGPRs = AMDGPU :: VGPR_32RegClass . getNumRegs ( ) ; for ( unsigned i = MaxNumVGPRs ; i < TotalNumVGPRs ; ++ i ) { unsigned Reg = AMDGPU :: VGPR_32RegClass . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } const SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , ScratchWaveOffsetReg ) ; } unsigned ScratchRSrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRSrcReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , ScratchRSrcReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , ScratchWaveOffsetReg ) ) ; } unsigned StackPtrReg = MFI -> getStackPtrOffsetReg ( ) ; if ( StackPtrReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , StackPtrReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , StackPtrReg ) ) ; } unsigned FrameReg = MFI -> getFrameOffsetReg ( ) ; if ( FrameReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , FrameReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , FrameReg ) ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static bool is_fmac_op ( enum attr_type t ) { return ( t == TYPE_FMACS ) || ( t == TYPE_FMACD ) || ( t == TYPE_NEON_FP_MLA_S ) ; } </s>

Return whether T is the attribute of a FMADD/FMSUB-like instruction .


<s> bool Cpu0SETargetLowering :: isEligibleForTailCallOptimization ( const Cpu0CC & Cpu0CCInfo , unsigned NextStackOffset , const Cpu0MachineFunctionInfo & FI ) const { if ( ! EnableCpu0TailCalls ) return false ; if ( Cpu0CCInfo . hasByValArg ( ) || FI . hasByvalArg ( ) ) return false ; return NextStackOffset <= FI . getIncomingArgSize ( ) ; } </s>

Returns true if the call can be lowered as a tail call .


"8-byte alignment required for for all register save slots"

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> static tree aarch64_promoted_type ( const_tree t ) { if ( SCALAR_FLOAT_TYPE_P ( t ) && TYPE_PRECISION ( t ) == 16 ) return float_type_node ; return NULL_TREE ; } </s>

Implement TARGET_PROMOTED_TYPE to promote __fp16 to float .


<s> unsigned ARCRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const ARCFrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? ARC :: FP : ARC :: SP ; } </s>


"Load and store instructions have exactly one mem operand"

"Default p2align value should be natural"

"Load and store instructions should have a p2align operand"


Output assembly code for a specific branch instruction , appending the branch prediction flag to the opcode if appropriate .


<s>
MachineBasicBlock
::
iterator
SIFrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
int64_t
Amount
=
I
->
getOperand
(
0
)
.
getImm
(
)
;
if
(
Amount
==
0
)
return
MBB
.
erase
(
I
)
;
const
GCNSubtarget
&
ST
=
MF
.
getSubtarget
<
GCNSubtarget
>
(
)
;
const
SIInstrInfo
*
TII
=
ST
.
getInstrInfo
(
)
;
const
DebugLoc
&
DL
=
I
->
getDebugLoc
(
)
;
unsigned
Opc
=
I
->
getOpcode
(
)
;
bool
IsDestroy
=
Opc
==
TII
->
getCallFrameDestroyOpcode
(
)
;
uint64_t
CalleePopAmount
=
IsDestroy
I
->
getOperand
(
1
)
.
getImm
(
)
:
0
;
if
(
!
hasReservedCallFrame
(
MF
)
)
{
Amount
=
alignTo
(
Amount
,
getStackAlign
(
)
)
;
assert
(
isUInt
<
32
>
(
Amount
)
&&
"exceeded stack address space size"
)
;
const
SIMachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
SIMachineFunctionInfo
>
(
)
;
Register
SPReg
=
MFI
->
getStackPtrOffsetReg
(
)
;
unsigned
Op
=
IsDestroy
AMDGPU
::
S_SUB_U32
:
AMDGPU
::
S_ADD_U32
;
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
Op
)
,
SPReg
)
.
addReg
(
SPReg
)
.
addImm
(
Amount
*
getScratchScaleFactor
(
ST
)
)
;
}
else
if
(
CalleePopAmount
!=
0
)
{
llvm_unreachable
(
"is this used?"
)
;
}
return
MBB
.
erase
(
I
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> virtual MVT getShiftAmountTy ( EVT LHSTy ) const { return MVT :: i8 ; } </s>

Returns the type for the shift amount of a shift opcode .


<s> const TargetRegisterClass * AArch64RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & AArch64 :: GPR64RegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


"There are no defined alternate asm variants"

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> void M68kAsmPrinter :: emitStartOfAsmFile ( Module & M ) { OutStreamer -> emitSyntaxDirective ( ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the start of their file .


"\tj\t%s ! jump to user handler directly\n"

"\tj\t%s ! jump to first level handler\n"

"\tmovi\t$r0, %d ! preparing software vid\n"


<s> void aarch64_expand_sve_vec_perm ( rtx target , rtx op0 , rtx op1 , rtx sel ) { machine_mode data_mode = GET_MODE ( target ) ; machine_mode sel_mode = GET_MODE ( sel ) ; int nunits = GET_MODE_NUNITS ( sel_mode ) . to_constant ( ) ; rtx sel_reg = force_reg ( sel_mode , sel ) ; if ( GET_CODE ( sel ) == CONST_VECTOR && aarch64_const_vec_all_in_range_p ( sel , 0 , nunits - 1 ) ) { emit_unspec2 ( target , UNSPEC_TBL , op0 , sel_reg ) ; return ; } if ( rtx_equal_p ( op0 , op1 ) ) { rtx max_sel = aarch64_simd_gen_const_vector_dup ( sel_mode , nunits - 1 ) ; rtx sel_mod = expand_simple_binop ( sel_mode , AND , sel_reg , max_sel , NULL , 0 , OPTAB_DIRECT ) ; emit_unspec2 ( target , UNSPEC_TBL , op0 , sel_mod ) ; return ; } rtx res0 = gen_reg_rtx ( data_mode ) ; rtx res1 = gen_reg_rtx ( data_mode ) ; rtx neg_num_elems = aarch64_simd_gen_const_vector_dup ( sel_mode , - nunits ) ; if ( GET_CODE ( sel ) != CONST_VECTOR || ! aarch64_const_vec_all_in_range_p ( sel , 0 , 2 * nunits - 1 ) ) { rtx max_sel = aarch64_simd_gen_const_vector_dup ( sel_mode , 2 * nunits - 1 ) ; sel_reg = expand_simple_binop ( sel_mode , AND , sel_reg , max_sel , NULL , 0 , OPTAB_DIRECT ) ; } emit_unspec2 ( res0 , UNSPEC_TBL , op0 , sel_reg ) ; rtx sel_sub = expand_simple_binop ( sel_mode , PLUS , sel_reg , neg_num_elems , NULL , 0 , OPTAB_DIRECT ) ; emit_unspec2 ( res1 , UNSPEC_TBL , op1 , sel_sub ) ; if ( GET_MODE_CLASS ( data_mode ) == MODE_VECTOR_INT ) emit_insn ( gen_rtx_SET ( target , gen_rtx_IOR ( data_mode , res0 , res1 ) ) ) ; else emit_unspec2 ( target , UNSPEC_IORF , res0 , res1 ) ; } </s>

Expand an SVE vec_perm with the given operands .


<s> bool Z80oldRegisterInfo :: requiresVirtualBaseRegisters ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers used for more efficient stack access .


<s> static rtx sparc_struct_value_rtx ( tree fndecl ATTRIBUTE_UNUSED , int incoming ) { if ( TARGET_ARCH64 ) return 0 ; else { rtx mem ; if ( incoming ) mem = gen_rtx_MEM ( Pmode , plus_constant ( frame_pointer_rtx , STRUCT_VALUE_OFFSET ) ) ; else mem = gen_rtx_MEM ( Pmode , plus_constant ( stack_pointer_rtx , STRUCT_VALUE_OFFSET ) ) ; set_mem_alias_set ( mem , struct_value_alias_set ) ; return mem ; } } </s>

Handle the TARGET_STRUCT_VALUE target hook . Return where to find the structure return value address .


<s> bool HexagonTargetMachine :: addPreSched2 ( PassManagerBase & PM ) { PM . add ( createIfConverterPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s>
void
relaxInstruction
(
const
MCInst
&
Inst
,
MCInst
&
Res
)
const
{
llvm_unreachable
(
"relaxInstruction() unimplemented"
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
Kind
==
Register
&&
"Invalid type access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s> bool ARMPassConfig :: addIRTranslator ( ) { addPass ( new IRTranslator ( getOptLevel ( ) ) ) ; return false ; } </s>

This method should install an IR translator pass , which converts from LLVM code to machine instructions with possibly generic opcodes .


"Encountered a global variable kind that is "

Emit the specified global variable to the .s file .


<s> static inline ChildIteratorType child_begin ( NodeRef N ) { return N -> Sites . begin ( ) ; } </s>

nodes_iterator/begin/end - Allow iteration over all nodes in the graph


<s> bool X86FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; if ( isFuncletReturnInstr ( * MI ) && STI . isOSWindows ( ) ) { if ( STI . is32Bit ( ) ) return true ; if ( MI -> getOpcode ( ) == X86 :: CATCHRET ) { const Function * Func = MBB . getParent ( ) -> getFunction ( ) ; bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( Func -> getPersonalityFn ( ) ) ) ; if ( IsSEH ) return true ; } } DebugLoc DL = MBB . findDebugLoc ( MI ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } unsigned Opc = STI . is64Bit ( ) ? X86 :: POP64r : X86 :: POP32r ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static void aarch64_push_regs ( unsigned regno1 , unsigned regno2 , HOST_WIDE_INT adjustment ) { rtx_insn * insn ; machine_mode mode = ( regno1 <= R30_REGNUM ) ? E_DImode : E_DFmode ; if ( regno2 == INVALID_REGNUM ) return aarch64_pushwb_single_reg ( mode , regno1 , adjustment ) ; rtx reg1 = gen_rtx_REG ( mode , regno1 ) ; rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; insn = emit_insn ( aarch64_gen_storewb_pair ( mode , stack_pointer_rtx , reg1 , reg2 , adjustment ) ) ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , 0 , 2 ) ) = 1 ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , 0 , 1 ) ) = 1 ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Push registers numbered REGNO1 and REGNO2 to the stack , adjusting the stack pointer by ADJUSTMENT .


<s> static rtx tilegx_tls_got ( void ) { rtx temp ; if ( flag_pic ) { crtl -> uses_pic_offset_table = 1 ; return tilegx_got_rtx ( ) ; } temp = gen_reg_rtx ( Pmode ) ; emit_move_insn ( temp , tilegx_got_symbol ( ) ) ; return temp ; } </s>

Return a reference to the got to be used by tls references .


<s> const TargetRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> i960_print_operand_addr ( FILE , ADDR ) { \ assemble_aligned_integer ( UNITS_PER_WORD , GEN_INT ( 0x8C203000 ) ) ; \ assemble_aligned_integer ( UNITS_PER_WORD , GEN_INT ( 0x00000000 ) ) ; \ assemble_aligned_integer ( UNITS_PER_WORD , GEN_INT ( 0x8CE03000 ) ) ; \ assemble_aligned_integer ( UNITS_PER_WORD , GEN_INT ( 0x00000000 ) ) ; \ assemble_aligned_integer ( UNITS_PER_WORD , GEN_INT ( 0x84212000 ) ) ; \ } </s>

Print a memory address as an operand to reference that memory location . This is exactly the same as legitimate_address_p , except that it the prints addresses instead of recognizing them .


<s> void sh_set_return_address ( rtx ra , rtx tmp ) { HARD_REG_SET live_regs_mask ; int d ; int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG ; int pr_offset ; d = calc_live_regs ( & live_regs_mask ) ; if ( ! TEST_HARD_REG_BIT ( live_regs_mask , pr_reg ) ) { rtx rr ; if ( TARGET_SHMEDIA ) { int rr_regno = sh_media_register_for_return ( ) ; if ( rr_regno < 0 ) rr_regno = pr_reg ; rr = gen_rtx_REG ( DImode , rr_regno ) ; } else rr = gen_rtx_REG ( SImode , pr_reg ) ; emit_insn ( GEN_MOV ( rr , ra ) ) ; emit_insn ( gen_rtx_USE ( VOIDmode , rr ) ) ; return ; } if ( TARGET_SH5 ) { int offset ; save_schedule schedule ; save_entry * entry ; entry = sh5_schedule_saves ( & live_regs_mask , & schedule , 0 ) ; offset = entry [ 1 ] . offset ; for ( ; entry -> mode != VOIDmode ; entry -- ) if ( entry -> reg == pr_reg ) goto found ; gcc_unreachable ( ) ; found : offset = entry -> offset - offset ; pr_offset = ( rounded_frame_size ( d ) + offset + SHMEDIA_REGS_STACK_ADJUST ( ) ) ; } else pr_offset = rounded_frame_size ( d ) ; emit_insn ( GEN_MOV ( tmp , GEN_INT ( pr_offset ) ) ) ; emit_insn ( GEN_ADD3 ( tmp , tmp , hard_frame_pointer_rtx ) ) ; tmp = gen_frame_mem ( Pmode , tmp ) ; emit_insn ( GEN_MOV ( tmp , ra ) ) ; } </s>

Emit code to change the current function 's return address to RA . TEMP is available as a scratch register , if needed .


<s>
StringRef
getPassName
(
)
const
override
{
return
"WebAssembly Explicit Locals"
;
}
</s>

getPassName - Return a nice clean name for a pass .

WebAssembly
"WebAssembly Explicit Locals"


"MCS51 dynalloca stack pointer save/restore"


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> const SpillSlot * getCalleeSavedSpillSlots ( unsigned & NumEntries ) const override { static const SpillSlot Offsets [ ] = { { Hexagon :: R17 , - 4 } , { Hexagon :: R16 , - 8 } , { Hexagon :: D8 , - 8 } , { Hexagon :: R19 , - 12 } , { Hexagon :: R18 , - 16 } , { Hexagon :: D9 , - 16 } , { Hexagon :: R21 , - 20 } , { Hexagon :: R20 , - 24 } , { Hexagon :: D10 , - 24 } , { Hexagon :: R23 , - 28 } , { Hexagon :: R22 , - 32 } , { Hexagon :: D11 , - 32 } , { Hexagon :: R25 , - 36 } , { Hexagon :: R24 , - 40 } , { Hexagon :: D12 , - 40 } , { Hexagon :: R27 , - 44 , { Hexagon :: R26 , - 48 , { Hexagon :: D13 , - 48 } } ; NumEntries = array_lengthof ( Offsets ) ; return Offsets ; } bool assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const override ; bool needsAligna ( const MachineFunction & MF ) const ; const MachineInstr * getAlignaInstr ( const MachineFunction & MF ) const ; void insertCFIInstructions ( MachineFunction & MF ) const ; private : typedef std :: vector < CalleeSavedInfo > CSIVect ; void expandAlloca ( MachineInstr * AI , const HexagonInstrInfo & TII , unsigned SP , unsigned CF ) const ; void insertPrologueInBlock ( MachineBasicBlock & MBB ) const ; void insertEpilogueInBlock ( MachineBasicBlock & MBB ) const ; bool insertCSRSpillsInBlock ( MachineBasicBlock & MBB , const CSIVect & CSI , const HexagonRegisterInfo & HRI ) const ; bool insertCSRRestoresInBlock ( MachineBasicBlock & MBB , const CSIVect & CSI , const HexagonRegisterInfo & HRI ) const ; void insertCFIInstructionsAt ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator At ) const ; void adjustForCalleeSavedRegsSpillCall ( MachineFunction & MF ) const ; bool replacePredRegPseudoSpillCode ( MachineFunction & MF ) const ; bool replaceVecPredRegPseudoSpillCode ( MachineFunction & MF ) const ; void findShrunkPrologEpilog ( MachineFunction & MF , MachineBasicBlock * & PrologB , MachineBasicBlock * & EpilogB ) const ; bool shouldInlineCSR ( llvm :: MachineFunction & MF , const CSIVect & CSI ) const ; bool useSpillFunction ( MachineFunction & MF , const CSIVect & CSI ) const ; bool useRestoreFunction ( MachineFunction & MF , const CSIVect & CSI ) const ; } </s>

getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs , that contains an entry for each callee saved register that must be spilled to a particular stack location if it is spilled .


<s> MachineInstr * AMDGPUInstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const { return 0 ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> bool LC2200PassConfig :: addPreISel ( ) { return false ; } </s>


<s> static void m32r_setup_incoming_varargs ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int * pretend_size , int no_rtl ) { int first_anon_arg ; if ( no_rtl ) return ; gcc_assert ( mode != BLKmode ) ; first_anon_arg = ( ROUND_ADVANCE_CUM ( * cum , mode , type ) + ROUND_ADVANCE_ARG ( mode , type ) ) ; if ( first_anon_arg < M32R_MAX_PARM_REGS ) { int first_reg_offset = first_anon_arg ; int size = M32R_MAX_PARM_REGS - first_reg_offset ; rtx regblock ; regblock = gen_rtx_MEM ( BLKmode , plus_constant ( arg_pointer_rtx , FIRST_PARM_OFFSET ( 0 ) ) ) ; set_mem_alias_set ( regblock , get_varargs_alias_set ( ) ) ; move_block_from_reg ( first_reg_offset , regblock , size ) ; * pretend_size = ( size * UNITS_PER_WORD ) ; } } </s>

Do any needed setup for a variadic function . For the M32R , we must create a register parameter block , and then copy any anonymous arguments in registers to memory . CUM has not been updated for the last named argument which has type TYPE and mode MODE , and we rely on this fact .


<s> void LEGAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool MipsInstructionSelector :: select ( MachineInstr & I , CodeGenCoverage & CoverageInfo ) const { if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) { return true ; } return false ; } </s>

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s> void GCNTTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP , OptimizationRemarkEmitter * ORE ) { CommonTTI . getUnrollingPreferences ( L , SE , UP , ORE ) ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> static bool symbolic_reference_mentioned_p ( rtx op ) { const char * fmt ; int i ; if ( GET_CODE ( op ) == SYMBOL_REF || GET_CODE ( op ) == LABEL_REF ) return true ; fmt = GET_RTX_FORMAT ( GET_CODE ( op ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( op ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( op , i ) - 1 ; j >= 0 ; j -- ) if ( symbolic_reference_mentioned_p ( XVECEXP ( op , i , j ) ) ) return true ; } else if ( fmt [ i ] == 'e' && symbolic_reference_mentioned_p ( XEXP ( op , i ) ) ) return true ; } return false ; } </s>

Return true if OP contains a symbol reference