<s> static char * make_name ( tree decl , const char * suffix , bool make_unique ) { char * global_var_name ; int name_len ; const char * name ; const char * unique_name = NULL ; name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; if ( make_unique ) unique_name = IDENTIFIER_POINTER ( get_file_function_name ( "\0" ) ) ; name_len = strlen ( name ) + strlen ( suffix ) + 2 ; if ( make_unique ) name_len += strlen ( unique_name ) + 1 ; global_var_name = XNEWVEC ( char , name_len ) ; if ( make_unique ) snprintf ( global_var_name , name_len , "%s.%s.%s" , name , unique_name , suffix ) ; else snprintf ( global_var_name , name_len , "%s.%s" , name , suffix ) ; return global_var_name ; } </s>

Return a new name by appending SUFFIX to the DECL name . If make_unique is true , append the full path name of the source file .


<s> void AMDGPUUnifyDivergentExitNodes :: getAnalysisUsage ( AnalysisUsage & AU ) const { if ( RequireAndPreserveDomTree ) AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addRequired < PostDominatorTreeWrapperPass > ( ) ; AU . addRequired < LegacyDivergenceAnalysis > ( ) ; if ( RequireAndPreserveDomTree ) { AU . addPreserved < DominatorTreeWrapperPass > ( ) ; } AU . addPreserved < LegacyDivergenceAnalysis > ( ) ; AU . addPreservedID ( BreakCriticalEdgesID ) ; AU . addPreservedID ( LowerSwitchID ) ; FunctionPass :: getAnalysisUsage ( AU ) ; AU . addRequired < TargetTransformInfoWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
void
dump
(
const
GCNRegBankReassign
*
P
)
const
{
MI
->
dump
(
)
;
dbgs
(
)
<<
P
->
printReg
(
Reg
)
<<
" to banks "
;
dumpFreeBanks
(
FreeBanks
)
;
dbgs
(
)
<<
" weight "
<<
Weight
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .


<s> unsigned getNumFixupKinds ( ) const override { return Patmos :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> static void fold_mergehl_helper ( gimple_stmt_iterator * gsi , gimple * stmt , int use_high ) { tree arg0 = gimple_call_arg ( stmt , 0 ) ; tree arg1 = gimple_call_arg ( stmt , 1 ) ; tree lhs = gimple_call_lhs ( stmt ) ; tree lhs_type = TREE_TYPE ( lhs ) ; tree lhs_type_type = TREE_TYPE ( lhs_type ) ; int n_elts = TYPE_VECTOR_SUBPARTS ( lhs_type ) ; int midpoint = n_elts / 2 ; int offset = 0 ; if ( use_high == 1 ) offset = midpoint ; tree_vector_builder elts ( lhs_type , VECTOR_CST_NELTS ( arg0 ) , 1 ) ; for ( int i = 0 ; i < midpoint ; i ++ ) { elts . safe_push ( build_int_cst ( lhs_type_type , offset + i ) ) ; elts . safe_push ( build_int_cst ( lhs_type_type , offset + n_elts + i ) ) ; } tree permute = elts . build ( ) ; gimple * g = gimple_build_assign ( lhs , VEC_PERM_EXPR , arg0 , arg1 , permute ) ; gimple_set_location ( g , gimple_location ( stmt ) ) ; gsi_replace ( gsi , g , true ) ; } </s>

Helper function to handle the vector merge [ hl ] built-ins . The implementation difference between h and l versions for this code are in the values used when building of the permute vector for high word versus low word merge . The variance is keyed off the use_high parameter .


<s> bool GCNPassConfig :: addLegalizeMachineIR ( ) { addPass ( new Legalizer ( ) ) ; return false ; } </s>

This method should install a legalize pass , which converts the instruction sequence into one that can be selected by the target .


<s> void AArch64AsmPrinter :: emitStartOfAsmFile ( Module & M ) { if ( ! TM . getTargetTriple ( ) . isOSBinFormatELF ( ) ) return ; unsigned Flags = 0 ; if ( const auto * BTE = mdconst :: extract_or_null < ConstantInt > ( M . getModuleFlag ( "branch-target-enforcement" ) ) ) if ( BTE -> getZExtValue ( ) ) Flags |= ELF :: GNU_PROPERTY_AARCH64_FEATURE_1_BTI ; if ( const auto * Sign = mdconst :: extract_or_null < ConstantInt > ( M . getModuleFlag ( "sign-return-address" ) ) ) if ( Sign -> getZExtValue ( ) ) Flags |= ELF :: GNU_PROPERTY_AARCH64_FEATURE_1_PAC ; if ( Flags == 0 ) return ; if ( auto * TS = static_cast < AArch64TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ) TS -> emitNoteSection ( Flags ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the start of their file .


<s> bool ARMBaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( ! MF . getTarget ( ) . Options . RealignStack ) return false ; if ( AFI -> isThumb1OnlyFunction ( ) ) return false ; if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ; if ( ! MFI -> hasVarSizedObjects ( ) ) return true ; if ( ! EnableBasePointer ) return false ; return MRI -> canReserveReg ( BasePtr ) ; } </s>

True if the stack can be realigned for the target .


"InsertBranch must not be told to insert a fallthrough"

"Patmos branch conditions should have two components (reg+imm)!"

Insert branch code into the end of the specified MachineBasicBlock .


"%qs attribute only applies to functions"

Handle an `` interrupt '' attribute ; arguments as in struct attribute_spec.handler .


<s> static enum tls_model tls_symbolic_operand_type ( rtx addr ) { enum tls_model tls_kind = TLS_MODEL_NONE ; poly_int64 offset ; addr = strip_offset_and_salt ( addr , & offset ) ; if ( SYMBOL_REF_P ( addr ) ) tls_kind = SYMBOL_REF_TLS_MODEL ( addr ) ; return tls_kind ; } </s>

Return the TLS model to use for SYMBOL .


<s> virtual bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCyles , float Probability , float Confidence ) const { return NumCyles == 1 ; } </s>

Return true if it 's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion .


<s>
bool
FixupLEAPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
const
X86Subtarget
&
ST
=
MF
.
getSubtarget
<
X86Subtarget
>
(
)
;
bool
IsSlowLEA
=
ST
.
slowLEA
(
)
;
bool
IsSlow3OpsLEA
=
ST
.
slow3OpsLEA
(
)
;
bool
LEAUsesAG
=
ST
.
LEAusesAG
(
)
;
bool
OptIncDec
=
!
ST
.
slowIncDec
(
)
||
MF
.
getFunction
(
)
.
hasOptSize
(
)
;
bool
UseLEAForSP
=
ST
.
useLeaForSP
(
)
;
TSM
.
init
(
&
ST
)
;
TII
=
ST
.
getInstrInfo
(
)
;
TRI
=
ST
.
getRegisterInfo
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Start X86FixupLEAs\n"
;
)
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
for
(
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
;
I
!=
MBB
.
end
(
)
;
++
I
)
{
if
(
!
isLEA
(
I
->
getOpcode
(
)
)
)
continue
;
if
(
optTwoAddrLEA
(
I
,
MBB
,
OptIncDec
,
UseLEAForSP
)
)
continue
;
if
(
IsSlowLEA
)
{
processInstructionForSlowLEA
(
I
,
MBB
)
;
}
else
if
(
IsSlow3OpsLEA
)
{
if
(
auto
*
NewMI
=
processInstrForSlow3OpLEA
(
*
I
,
MBB
)
)
{
MBB
.
erase
(
I
)
;
I
=
NewMI
;
}
}
}
if
(
LEAUsesAG
)
{
for
(
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
;
I
!=
MBB
.
end
(
)
;
++
I
)
processInstruction
(
I
,
MBB
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
"End X86FixupLEAs\n"
;
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


"%qE attribute only applies to functions"


<s> int AMDGPUInstrInfo :: pseudoToMCOpcode ( int Opcode ) const { SIEncodingFamily Gen = subtargetEncodingFamily ( ST ) ; if ( get ( Opcode ) . TSFlags & SIInstrFlags :: SDWA ) Gen = ST . getGeneration ( ) == AMDGPUSubtarget :: GFX9 ? SIEncodingFamily :: SDWA9 : SIEncodingFamily :: SDWA ; int MCOp = AMDGPU :: getMCOpcode ( Opcode , Gen ) ; if ( MCOp == - 1 ) return Opcode ; if ( MCOp == ( uint16_t ) - 1 ) return - 1 ; return MCOp ; } </s>

Return a target-specific opcode if Opcode is a pseudo instruction .


<s>
static
int
getMemScale
(
MachineInstr
*
MI
)
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Opcode has unknown scale!"
)
;
case
AArch64
::
LDRBBui
:
case
AArch64
::
STRBBui
:
return
1
;
case
AArch64
::
LDRHHui
:
case
AArch64
::
LDURHHi
:
case
AArch64
::
STRHHui
:
return
2
;
case
AArch64
::
LDRSui
:
case
AArch64
::
LDURSi
:
case
AArch64
::
LDRSWui
:
case
AArch64
::
LDURSWi
:
case
AArch64
::
LDRWui
:
case
AArch64
::
LDURWi
:
case
AArch64
::
STRSui
:
case
AArch64
::
STURSi
:
case
AArch64
::
STRWui
:
case
AArch64
::
STURWi
:
case
AArch64
::
LDPSi
:
case
AArch64
::
LDPSWi
:
case
AArch64
::
LDPWi
:
case
AArch64
::
STPSi
:
case
AArch64
::
STPWi
:
return
4
;
case
AArch64
::
LDRDui
:
case
AArch64
::
LDURDi
:
case
AArch64
::
LDRXui
:
case
AArch64
::
LDURXi
:
case
AArch64
::
STRDui
:
case
AArch64
::
STURDi
:
case
AArch64
::
STRXui
:
case
AArch64
::
STURXi
:
case
AArch64
::
LDPDi
:
case
AArch64
::
LDPXi
:
case
AArch64
::
STPDi
:
case
AArch64
::
STPXi
:
return
8
;
case
AArch64
::
LDRQui
:
case
AArch64
::
LDURQi
:
case
AArch64
::
STRQui
:
case
AArch64
::
STURQi
:
case
AArch64
::
LDPQi
:
case
AArch64
::
STPQi
:
return
16
;
}
}
</s>

Scaling factor for ( scaled or unscaled ) load or store .


<s> static unsigned HOST_WIDE_INT arm_asan_shadow_offset ( void ) { return HOST_WIDE_INT_1U << 29 ; } </s>

Implement the TARGET_ASAN_SHADOW_OFFSET hook .


Return the probing interval for -fstack-clash-protection .


<s>
void
output_addr_const_pdp11
(
FILE
*
file
,
rtx
x
)
{
char
buf
[
256
]
;
int
i
;
restart
:
switch
(
GET_CODE
(
x
)
)
{
case
PC
:
gcc_assert
(
flag_pic
)
;
putc
(
'.'
,
file
)
;
break
;
case
SYMBOL_REF
:
assemble_name
(
file
,
XSTR
(
x
,
0
)
)
;
break
;
case
LABEL_REF
:
ASM_GENERATE_INTERNAL_LABEL
(
buf
,
"L"
,
CODE_LABEL_NUMBER
(
XEXP
(
x
,
0
)
)
)
;
assemble_name
(
file
,
buf
)
;
break
;
case
CODE_LABEL
:
ASM_GENERATE_INTERNAL_LABEL
(
buf
,
"L"
,
CODE_LABEL_NUMBER
(
x
)
)
;
assemble_name
(
file
,
buf
)
;
break
;
case
CONST_INT
:
i
=
INTVAL
(
x
)
;
if
(
i
<
0
)
{
i
=
i
;
fprintf
(
file
,
"-"
)
;
}
fprintf
(
file
,
"%#o"
,
i
&
0xffff
)
;
break
;
case
CONST
:
output_addr_const_pdp11
(
file
,
XEXP
(
x
,
0
)
)
;
break
;
case
CONST_DOUBLE
:
if
(
GET_MODE
(
x
)
==
VOIDmode
)
{
gcc_assert
(
!
CONST_DOUBLE_HIGH
(
x
)
)
;
fprintf
(
file
,
"%#ho"
,
(
unsigned
short
)
CONST_DOUBLE_LOW
(
x
)
)
;
}
else
output_operand_lossage
(
"floating constant misused"
)
;
break
;
case
PLUS
:
if
(
GET_CODE
(
XEXP
(
x
,
0
)
)
==
CONST_INT
)
{
output_addr_const_pdp11
(
file
,
XEXP
(
x
,
1
)
)
;
if
(
INTVAL
(
XEXP
(
x
,
0
)
)
>=
0
)
fprintf
(
file
,
"+"
)
;
output_addr_const_pdp11
(
file
,
XEXP
(
x
,
0
)
)
;
}
else
{
output_addr_const_pdp11
(
file
,
XEXP
(
x
,
0
)
)
;
if
(
INTVAL
(
XEXP
(
x
,
1
)
)
>=
0
)
fprintf
(
file
,
"+"
)
;
output_addr_const_pdp11
(
file
,
XEXP
(
x
,
1
)
)
;
}
break
;
case
MINUS
:
x
=
simplify_subtraction
(
x
)
;
if
(
GET_CODE
(
x
)
!=
MINUS
)
goto
restart
;
output_addr_const_pdp11
(
file
,
XEXP
(
x
,
0
)
)
;
if
(
GET_CODE
(
XEXP
(
x
,
1
)
)
!=
CONST_INT
||
INTVAL
(
XEXP
(
x
,
1
)
)
>=
0
)
fprintf
(
file
,
"-"
)
;
output_addr_const_pdp11
(
file
,
XEXP
(
x
,
1
)
)
;
break
;
case
ZERO_EXTEND
:
case
SIGN_EXTEND
:
output_addr_const_pdp11
(
file
,
XEXP
(
x
,
0
)
)
;
break
;
default
:
output_operand_lossage
(
"invalid expression as operand"
)
;
}
}
</s>

A copy of output_addr_const modified for pdp11 expression syntax . output_addr_const also gets called for % cDIGIT and % nDIGIT , which we do n't use , and for debugging output , which we do n't support with this port either . So this copy should get called whenever needed .


<s>
unsigned
MipsTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
)
const
{
if
(
Subtarget
.
isGP64bit
(
)
)
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"$28"
,
Mips
::
GP_64
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
}
else
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"$28"
,
Mips
::
GP
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
}
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


"MIPS DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> static void rs6000_darwin64_record_arg_flush ( CUMULATIVE_ARGS * cum , HOST_WIDE_INT bitpos , rtx rvec [ ] , int * k ) { machine_mode mode ; unsigned int regno ; unsigned int startbit , endbit ; int this_regno , intregs , intoffset ; rtx reg ; if ( cum -> intoffset == - 1 ) return ; intoffset = cum -> intoffset ; cum -> intoffset = - 1 ; if ( intoffset % BITS_PER_WORD != 0 ) { mode = mode_for_size ( BITS_PER_WORD - intoffset % BITS_PER_WORD , MODE_INT , 0 ) ; if ( mode == BLKmode ) { intoffset = intoffset & - BITS_PER_WORD ; mode = word_mode ; } } else mode = word_mode ; startbit = intoffset & - BITS_PER_WORD ; endbit = ( bitpos + BITS_PER_WORD - 1 ) & - BITS_PER_WORD ; intregs = ( endbit - startbit ) / BITS_PER_WORD ; this_regno = cum -> words + intoffset / BITS_PER_WORD ; if ( intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno ) cum -> use_stack = 1 ; intregs = MIN ( intregs , GP_ARG_NUM_REG - this_regno ) ; if ( intregs <= 0 ) return ; intoffset /= BITS_PER_UNIT ; do { regno = GP_ARG_MIN_REG + this_regno ; reg = gen_rtx_REG ( mode , regno ) ; rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( intoffset ) ) ; this_regno += 1 ; intoffset = ( intoffset | ( UNITS_PER_WORD - 1 ) ) + 1 ; mode = word_mode ; intregs -= 1 ; } while ( intregs > 0 ) ; } </s>

A subroutine of rs6000_darwin64_record_arg . Assign the bits of the structure between cum- > intoffset and bitpos to integer registers .


<s> static inline bool save_global_or_fp_reg_p ( unsigned int regno , int leaf_function ATTRIBUTE_UNUSED ) { return ! call_used_regs [ regno ] && df_regs_ever_live_p ( regno ) ; } </s>

Return whether REGNO , a global or FP register , must be saved/restored .


<s> rtx mips_return_addr ( int count , rtx frame ATTRIBUTE_UNUSED ) { if ( count != 0 ) return const0_rtx ; return get_hard_reg_initial_val ( Pmode , GP_REG_FIRST + 31 ) ; } </s>

Implement RETURN_ADDR_RTX . Note , we do not support moving back to a previous frame .


<s> bool WebAssemblyFastISel :: fastLowerArguments ( ) { if ( ! FuncInfo . CanLowerReturn ) return false ; const Function * F = FuncInfo . Fn ; if ( F -> isVarArg ( ) ) return false ; unsigned i = 0 ; for ( auto const & Arg : F -> args ( ) ) { const AttributeList & Attrs = F -> getAttributes ( ) ; if ( Attrs . hasParamAttribute ( i , Attribute :: ByVal ) || Attrs . hasParamAttribute ( i , Attribute :: SwiftSelf ) || Attrs . hasParamAttribute ( i , Attribute :: SwiftError ) || Attrs . hasParamAttribute ( i , Attribute :: InAlloca ) || Attrs . hasParamAttribute ( i , Attribute :: Nest ) ) return false ; Type * ArgTy = Arg . getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) ) return false ; if ( ! Subtarget -> hasSIMD128 ( ) && ArgTy -> isVectorTy ( ) ) return false ; unsigned Opc ; const TargetRegisterClass * RC ; switch ( getSimpleType ( ArgTy ) ) { case MVT :: i1 : case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : Opc = WebAssembly :: ARGUMENT_I32 ; RC = & WebAssembly :: I32RegClass ; break ; case MVT :: i64 : Opc = WebAssembly :: ARGUMENT_I64 ; RC = & WebAssembly :: I64RegClass ; break ; case MVT :: f32 : Opc = WebAssembly :: ARGUMENT_F32 ; RC = & WebAssembly :: F32RegClass ; break ; case MVT :: f64 : Opc = WebAssembly :: ARGUMENT_F64 ; RC = & WebAssembly :: F64RegClass ; break ; case MVT :: v16i8 : Opc = WebAssembly :: ARGUMENT_v16i8 ; RC = & WebAssembly :: V128RegClass ; break ; case MVT :: v8i16 : Opc = WebAssembly :: ARGUMENT_v8i16 ; RC = & WebAssembly :: V128RegClass ; break ; case MVT :: v4i32 : Opc = WebAssembly :: ARGUMENT_v4i32 ; RC = & WebAssembly :: V128RegClass ; break ; case MVT :: v4f32 : Opc = WebAssembly :: ARGUMENT_v4f32 ; RC = & WebAssembly :: V128RegClass ; break ; default : return false ; } unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addImm ( i ) ; updateValueMap ( & Arg , ResultReg ) ; ++ i ; } MRI . addLiveIn ( WebAssembly :: ARGUMENTS ) ; auto * MFI = MF -> getInfo < WebAssemblyFunctionInfo > ( ) ; for ( auto const & Arg : F -> args ( ) ) MFI -> addParam ( getLegalType ( getSimpleType ( Arg . getType ( ) ) ) ) ; if ( ! F -> getReturnType ( ) -> isVoidTy ( ) ) MFI -> addResult ( getLegalType ( getSimpleType ( F -> getReturnType ( ) ) ) ) ; return true ; } </s>

This method is called by target-independent code to do target- specific argument lowering .


<s> static MachineInstr * findLoopInstr ( MachineBasicBlock * BB , unsigned EndLoopOp , MachineBasicBlock * TargetBB , SmallPtrSet < MachineBasicBlock * , 8 > & Visited ) { unsigned LOOPi ; unsigned LOOPr ; if ( EndLoopOp == Hexagon :: ENDLOOP0 ) { LOOPi = Hexagon :: J2_loop0i ; LOOPr = Hexagon :: J2_loop0r ; } else { LOOPi = Hexagon :: J2_loop1i ; LOOPr = Hexagon :: J2_loop1r ; } for ( MachineBasicBlock * PB : BB -> predecessors ( ) ) { if ( ! Visited . insert ( PB ) . second ) continue ; if ( PB == BB ) continue ; for ( auto I = PB -> instr_rbegin ( ) , E = PB -> instr_rend ( ) ; I != E ; ++ I ) { unsigned Opc = I -> getOpcode ( ) ; if ( Opc == LOOPi || Opc == LOOPr ) return & * I ; if ( Opc == EndLoopOp && I -> getOperand ( 0 ) . getMBB ( ) != TargetBB ) return nullptr ; } if ( MachineInstr * Loop = findLoopInstr ( PB , EndLoopOp , TargetBB , Visited ) ) return Loop ; } return nullptr ; } </s>

Find the hardware loop instruction used to set-up the specified loop .


<s> Optional < MCFixupKind > MipsAsmBackend :: getFixupKind ( StringRef Name ) const { return StringSwitch < Optional < MCFixupKind >> ( Name ) . Case ( "R_MIPS_NONE" , ( MCFixupKind ) Mips :: fixup_Mips_NONE ) . Case ( "R_MIPS_32" , FK_Data_4 ) . Case ( "R_MIPS_GOT_PAGE" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_PAGE ) . Case ( "R_MIPS_CALL_HI16" , ( MCFixupKind ) Mips :: fixup_Mips_CALL_HI16 ) . Case ( "R_MIPS_CALL_LO16" , ( MCFixupKind ) Mips :: fixup_Mips_CALL_LO16 ) . Case ( "R_MIPS_CALL16" , ( MCFixupKind ) Mips :: fixup_Mips_CALL16 ) . Case ( "R_MIPS_GOT16" , ( MCFixupKind ) Mips :: fixup_Mips_GOT ) . Case ( "R_MIPS_GOT_PAGE" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_PAGE ) . Case ( "R_MIPS_GOT_OFST" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_OFST ) . Case ( "R_MIPS_GOT_DISP" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_DISP ) . Case ( "R_MIPS_GOT_HI16" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_HI16 ) . Case ( "R_MIPS_GOT_LO16" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_LO16 ) . Case ( "R_MIPS_TLS_GOTTPREL" , ( MCFixupKind ) Mips :: fixup_Mips_GOTTPREL ) . Case ( "R_MIPS_TLS_DTPREL_HI16" , ( MCFixupKind ) Mips :: fixup_Mips_DTPREL_HI ) . Case ( "R_MIPS_TLS_DTPREL_LO16" , ( MCFixupKind ) Mips :: fixup_Mips_DTPREL_LO ) . Case ( "R_MIPS_TLS_GD" , ( MCFixupKind ) Mips :: fixup_Mips_TLSGD ) . Case ( "R_MIPS_TLS_LDM" , ( MCFixupKind ) Mips :: fixup_Mips_TLSLDM ) . Case ( "R_MIPS_TLS_TPREL_HI16" , ( MCFixupKind ) Mips :: fixup_Mips_TPREL_HI ) . Case ( "R_MIPS_TLS_TPREL_LO16" , ( MCFixupKind ) Mips :: fixup_Mips_TPREL_LO ) . Case ( "R_MICROMIPS_CALL16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_CALL16 ) . Case ( "R_MICROMIPS_GOT_DISP" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOT_DISP ) . Case ( "R_MICROMIPS_GOT_PAGE" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOT_PAGE ) . Case ( "R_MICROMIPS_GOT_OFST" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOT_OFST ) . Case ( "R_MICROMIPS_GOT16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOT16 ) . Case ( "R_MICROMIPS_TLS_GOTTPREL" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOTTPREL ) . Case ( "R_MICROMIPS_TLS_DTPREL_HI16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_DTPREL_HI16 ) . Case ( "R_MICROMIPS_TLS_DTPREL_LO16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_DTPREL_LO16 ) . Case ( "R_MICROMIPS_TLS_GD" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_GD ) . Case ( "R_MICROMIPS_TLS_LDM" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_LDM ) . Case ( "R_MICROMIPS_TLS_TPREL_HI16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_TPREL_HI16 ) . Case ( "R_MICROMIPS_TLS_TPREL_LO16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_TPREL_LO16 ) . Default ( MCAsmBackend :: getFixupKind ( Name ) ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> bool X86RegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , unsigned Reg , int & FrameIdx ) const { if ( Reg == FramePtr && hasFP ( MF ) ) { FrameIdx = MF . getFrameInfo ( ) -> getObjectIndexBegin ( ) ; return true ; } return false ; } </s>

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register .


<s> std :: string getDataLayout ( ) const { return "e-p:32:32-i:32:32-f:32:32" ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> FunctionPass * NVPTXPassConfig :: createTargetRegisterAllocator ( bool ) { return 0 ; } </s>

createTargetRegisterAllocator - Create the register allocator pass for this target at the current optimization level .


<s> static bool pdp11_legitimate_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { return GET_CODE ( x ) != CONST_DOUBLE || legitimate_const_double_p ( x ) ; } </s>


<s> std :: pair < unsigned , const TargetRegisterClass * > ARMTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return std :: make_pair ( 0U , ARM :: tGPRRegisterClass ) ; else return std :: make_pair ( 0U , ARM :: GPRRegisterClass ) ; case 'r' : return std :: make_pair ( 0U , ARM :: GPRRegisterClass ) ; case 'w' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , ARM :: SPRRegisterClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , ARM :: DPRRegisterClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , ARM :: QPRRegisterClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( 0U , ARM :: CCRRegisterClass ) ; return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


"WebAssembly should not have callee-saved registers"

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


"TPCHazardRecognizer :: EmitInstruction: "

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


"insertBranch must not be told to insert a fallthrough"

"X86 branch conditions have one component!"

"Unconditional branch with multiple successors!"

"MBB cannot be the last block in function when the false "

Insert branch code into the end of the specified MachineBasicBlock .


<s> bool HexagonPassConfig :: addPreEmitPass ( ) { if ( ! DisableHardwareLoops ) { addPass ( createHexagonFixupHwLoops ( ) ) ; } addPass ( createHexagonNewValueJump ( ) ) ; addPass ( createHexagonExpandPredSpillCode ( getHexagonTargetMachine ( ) ) ) ; addPass ( createHexagonSplitTFRCondSets ( getHexagonTargetMachine ( ) ) ) ; addPass ( createHexagonPacketizer ( ) ) ; return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon


<s> static void ix86_emit_restore_sse_regs_using_mov ( HOST_WIDE_INT cfa_offset , bool maybe_eh_return ) { unsigned int regno ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( SSE_REGNO_P ( regno ) && ix86_save_reg ( regno , maybe_eh_return ) ) { rtx reg = gen_rtx_REG ( V4SFmode , regno ) ; rtx mem ; mem = choose_baseaddr ( cfa_offset ) ; mem = gen_rtx_MEM ( V4SFmode , mem ) ; set_mem_align ( mem , 128 ) ; emit_move_insn ( reg , mem ) ; ix86_add_cfa_restore_note ( NULL_RTX , reg , cfa_offset ) ; cfa_offset -= 16 ; } } </s>

Emit code to restore saved registers using MOV insns . First register is restored from CFA - CFA_OFFSET .


<s> static tree alpha_fold_builtin_zapnot ( tree * op , unsigned HOST_WIDE_INT opint [ ] , long op_const ) { if ( op_const & 2 ) { unsigned HOST_WIDE_INT mask = 0 ; int i ; for ( i = 0 ; i < 8 ; ++ i ) if ( ( opint [ 1 ] >> i ) & 1 ) mask |= ( unsigned HOST_WIDE_INT ) 0xff << ( i * 8 ) ; if ( op_const & 1 ) return build_int_cst ( long_integer_type_node , opint [ 0 ] & mask ) ; if ( op ) return fold ( build2 ( BIT_AND_EXPR , long_integer_type_node , op [ 0 ] , build_int_cst ( long_integer_type_node , mask ) ) ) ; } else if ( ( op_const & 1 ) && opint [ 0 ] == 0 ) return build_int_cst ( long_integer_type_node , 0 ) ; return NULL ; } </s>

Fold the builtin for the ZAPNOT instruction . This is essentially a specialized form of an AND operation . Other byte manipulation instructions are defined in terms of this instruction , so this is also used as a subroutine for other builtins . OP contains the tree operands ; OPINT contains the extracted integer values . Bit N of OP_CONST it set if OPINT [ N ] is valid . OP may be null if only OPINT may be considered .


<s>
bool
TGSICFGStructurizer
::
isReturnBlock
(
MachineBasicBlock
*
MBB
)
{
MachineInstr
*
MI
=
getReturnInstr
(
MBB
)
;
bool
IsReturn
=
(
MBB
->
succ_size
(
)
==
0
)
;
if
(
MI
)
assert
(
IsReturn
)
;
else
if
(
IsReturn
)
DEBUG
(
dbgs
(
)
<<
"BB"
<<
MBB
->
getNumber
(
)
<<
" is return block without RET instr\n"
;
)
;
return
IsReturn
;
}
</s>

Convenience function that returns true if the block ends in a return instruction .

TGSI
TGSI
0
"BB"
" is return block without RET instr\n"


<s> const BitTracker :: RegisterCell & lookup ( unsigned VR ) { unsigned RInd = Register :: virtReg2Index ( VR ) ; if ( RInd >= CVect . size ( ) ) CVect . resize ( std :: max ( RInd + 16 , 32U ) , nullptr ) ; const BitTracker :: RegisterCell * CP = CVect [ RInd ] ; if ( CP == nullptr ) CP = CVect [ RInd ] = & BT . lookup ( VR ) ; return * CP ; } </s>

This method finds the value with the given Name in the the symbol table .


<s>
const
MCPhysReg
*
X86RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
const
X86Subtarget
&
Subtarget
=
MF
->
getSubtarget
<
X86Subtarget
>
(
)
;
bool
HasSSE
=
Subtarget
.
hasSSE1
(
)
;
bool
HasAVX
=
Subtarget
.
hasAVX
(
)
;
bool
HasAVX512
=
Subtarget
.
hasAVX512
(
)
;
bool
CallsEHReturn
=
MF
->
getMMI
(
)
.
callsEHReturn
(
)
;
assert
(
MF
&&
"MachineFunction required"
)
;
switch
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
)
{
case
CallingConv
::
GHC
:
case
CallingConv
::
HiPE
:
return
CSR_NoRegs_SaveList
;
case
CallingConv
::
AnyReg
:
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
return
CSR_64_AllRegs_SaveList
;
case
CallingConv
::
PreserveMost
:
return
CSR_64_RT_MostRegs_SaveList
;
case
CallingConv
::
PreserveAll
:
if
(
HasAVX
)
return
CSR_64_RT_AllRegs_AVX_SaveList
;
return
CSR_64_RT_AllRegs_SaveList
;
case
CallingConv
::
CXX_FAST_TLS
:
if
(
Is64Bit
)
return
MF
->
getInfo
<
X86MachineFunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_64_CXX_TLS_Darwin_PE_SaveList
:
CSR_64_TLS_Darwin_SaveList
;
break
;
case
CallingConv
::
Intel_OCL_BI
:
{
if
(
HasAVX512
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX512
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX_SaveList
;
if
(
HasAVX
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX_SaveList
;
if
(
!
HasAVX
&&
!
IsWin64
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_SaveList
;
break
;
}
case
CallingConv
::
HHVM
:
return
CSR_64_HHVM_SaveList
;
case
CallingConv
::
Cold
:
if
(
Is64Bit
)
return
CSR_64_MostRegs_SaveList
;
break
;
case
CallingConv
::
X86_64_Win64
:
return
CSR_Win64_SaveList
;
case
CallingConv
::
X86_64_SysV
:
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
case
CallingConv
::
X86_INTR
:
if
(
Is64Bit
)
{
if
(
HasAVX512
)
return
CSR_64_AllRegs_AVX512_SaveList
;
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
return
CSR_64_AllRegs_SaveList
;
}
else
{
if
(
HasAVX512
)
return
CSR_32_AllRegs_AVX512_SaveList
;
if
(
HasAVX
)
return
CSR_32_AllRegs_AVX_SaveList
;
if
(
HasSSE
)
return
CSR_32_AllRegs_SSE_SaveList
;
return
CSR_32_AllRegs_SaveList
;
}
default
:
break
;
}
if
(
Is64Bit
)
{
if
(
IsWin64
)
return
CSR_Win64_SaveList
;
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
if
(
Subtarget
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
->
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_64_SwiftError_SaveList
;
return
CSR_64_SaveList
;
}
if
(
CallsEHReturn
)
return
CSR_32EHRet_SaveList
;
return
CSR_32_SaveList
;
}
</s>


<s> static bool mips_vector_mode_supported_p ( machine_mode mode ) { switch ( mode ) { case V2SFmode : return TARGET_PAIRED_SINGLE_FLOAT ; case V2HImode : case V4QImode : case V2HQmode : case V2UHQmode : case V2HAmode : case V2UHAmode : case V4QQmode : case V4UQQmode : return TARGET_DSP ; case V2SImode : case V4HImode : case V8QImode : return TARGET_LOONGSON_VECTORS ; default : return MSA_SUPPORTED_MODE_P ( mode ) ; } } </s>

Target hook for vector_mode_supported_p .


<s> static bool arm_slowmul_rtx_costs ( rtx x , enum rtx_code code , enum rtx_code outer_code , int * total , bool speed ) { machine_mode mode = GET_MODE ( x ) ; if ( TARGET_THUMB ) { * total = thumb1_rtx_costs ( x , code , outer_code ) ; return true ; } switch ( code ) { case MULT : if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || mode == DImode ) { * total = COSTS_N_INSNS ( 20 ) ; return false ; } if ( CONST_INT_P ( XEXP ( x , 1 ) ) ) { unsigned HOST_WIDE_INT i = ( INTVAL ( XEXP ( x , 1 ) ) & ( unsigned HOST_WIDE_INT ) 0xffffffff ) ; int cost , const_ok = const_ok_for_arm ( i ) ; int j , booth_unit_size ; cost = const_ok ? 4 : 8 ; booth_unit_size = 2 ; for ( j = 0 ; i && j < 32 ; j += booth_unit_size ) { i >>= booth_unit_size ; cost ++ ; } * total = COSTS_N_INSNS ( cost ) ; * total += rtx_cost ( XEXP ( x , 0 ) , mode , code , 0 , speed ) ; return true ; } * total = COSTS_N_INSNS ( 20 ) ; return false ; default : return arm_rtx_costs_1 ( x , outer_code , total , speed ) ; ; } } </s>

RTX costs for cores with a slow MUL implementation . Thumb-2 is not supported on any `` slowmul '' cores , so it can be ignored .


<s> static machine_mode select_block_compare_mode ( unsigned HOST_WIDE_INT offset , unsigned HOST_WIDE_INT bytes , unsigned HOST_WIDE_INT align , bool word_mode_ok ) { unsigned HOST_WIDE_INT maxread = ROUND_UP ( bytes , align ) ; if ( word_mode_ok && bytes >= UNITS_PER_WORD ) return word_mode ; else if ( bytes == GET_MODE_SIZE ( SImode ) ) return SImode ; else if ( bytes == GET_MODE_SIZE ( HImode ) ) return HImode ; else if ( bytes == GET_MODE_SIZE ( QImode ) ) return QImode ; else if ( bytes < GET_MODE_SIZE ( SImode ) && offset >= GET_MODE_SIZE ( SImode ) - bytes ) return SImode ; else if ( word_mode_ok && bytes < UNITS_PER_WORD && offset >= UNITS_PER_WORD - bytes ) return word_mode ; else if ( word_mode_ok && maxread >= UNITS_PER_WORD ) return word_mode ; else if ( maxread >= GET_MODE_SIZE ( SImode ) ) return SImode ; else if ( bytes > GET_MODE_SIZE ( SImode ) ) return SImode ; else if ( bytes > GET_MODE_SIZE ( HImode ) ) return HImode ; return QImode ; } </s>

Select the mode to be used for reading the next chunk of bytes in the compare . OFFSET is the current read offset from the beginning of the block . BYTES is the number of bytes remaining to be read . ALIGN is the minimum alignment of the memory blocks being compared in bytes .


<s> virtual const IA64Subtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> unsigned MCS51MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; if ( MO . isDFPImm ( ) ) return static_cast < unsigned > ( bit_cast < double > ( MO . getDFPImm ( ) ) ) ; assert ( MO . isExpr ( ) ) ; return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> static unsigned int xtensa_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( FP_REG_P ( regno ) ) return CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_FPREG ) ; return CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ; } </s>


<s> unsigned HSAILRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { if ( RC == & HSAIL :: GPR32RegClass ) { return HSAILReg32PressureLimit ; } if ( RC == & HSAIL :: GPR64RegClass ) { return HSAILReg64PressureLimit ; } return 0 ; } </s>

Return the register pressure `` high water mark '' for the specific register class .


"Trying RISCV32Only_16 table (16-bit Instruction):\n"

"Trying RISCV_C table (16-bit Instruction):\n"

Returns the disassembly of a single instruction .


<s> machine_mode arm_select_dominance_cc_mode ( rtx x , rtx y , HOST_WIDE_INT cond_or ) { enum rtx_code cond1 , cond2 ; int swapped = 0 ; if ( ( arm_select_cc_mode ( cond1 = GET_CODE ( x ) , XEXP ( x , 0 ) , XEXP ( x , 1 ) ) != CCmode ) || ( arm_select_cc_mode ( cond2 = GET_CODE ( y ) , XEXP ( y , 0 ) , XEXP ( y , 1 ) ) != CCmode ) ) return CCmode ; if ( cond_or == DOM_CC_NX_OR_Y ) cond1 = reverse_condition ( cond1 ) ; if ( cond1 != cond2 && ! comparison_dominates_p ( cond1 , cond2 ) && ( swapped = 1 , ! comparison_dominates_p ( cond2 , cond1 ) ) ) return CCmode ; if ( swapped ) std :: swap ( cond1 , cond2 ) ; switch ( cond1 ) { case EQ : if ( cond_or == DOM_CC_X_AND_Y ) return CC_DEQmode ; switch ( cond2 ) { case EQ : return CC_DEQmode ; case LE : return CC_DLEmode ; case LEU : return CC_DLEUmode ; case GE : return CC_DGEmode ; case GEU : return CC_DGEUmode ; default : gcc_unreachable ( ) ; } case LT : if ( cond_or == DOM_CC_X_AND_Y ) return CC_DLTmode ; switch ( cond2 ) { case LT : return CC_DLTmode ; case LE : return CC_DLEmode ; case NE : return CC_DNEmode ; default : gcc_unreachable ( ) ; } case GT : if ( cond_or == DOM_CC_X_AND_Y ) return CC_DGTmode ; switch ( cond2 ) { case GT : return CC_DGTmode ; case GE : return CC_DGEmode ; case NE : return CC_DNEmode ; default : gcc_unreachable ( ) ; } case LTU : if ( cond_or == DOM_CC_X_AND_Y ) return CC_DLTUmode ; switch ( cond2 ) { case LTU : return CC_DLTUmode ; case LEU : return CC_DLEUmode ; case NE : return CC_DNEmode ; default : gcc_unreachable ( ) ; } case GTU : if ( cond_or == DOM_CC_X_AND_Y ) return CC_DGTUmode ; switch ( cond2 ) { case GTU : return CC_DGTUmode ; case GEU : return CC_DGEUmode ; case NE : return CC_DNEmode ; default : gcc_unreachable ( ) ; } case NE : gcc_assert ( cond1 == cond2 ) ; return CC_DNEmode ; case LE : gcc_assert ( cond1 == cond2 ) ; return CC_DLEmode ; case GE : gcc_assert ( cond1 == cond2 ) ; return CC_DGEmode ; case LEU : gcc_assert ( cond1 == cond2 ) ; return CC_DLEUmode ; case GEU : gcc_assert ( cond1 == cond2 ) ; return CC_DGEUmode ; default : gcc_unreachable ( ) ; } } </s>

Select a dominance comparison mode if possible for a test of the general form ( OP ( COND_OR ( X ) ( Y ) ) ( const_int 0 ) ) . We support three forms . COND_OR == DOM_CC_X_AND_Y = > ( X & & Y ) COND_OR == DOM_CC_NX_OR_Y = > ( ( ! X ) || Y ) COND_OR == DOM_CC_X_OR_Y = > ( X || Y ) In all cases OP will be either EQ or NE , but we do n't need to know which here . If we are unable to support a dominance comparison we return CC mode . This will then fail to match for the RTL expressions that generate this call .


<s> static unsigned HOST_WIDE_INT riscv_asan_shadow_offset ( void ) { return TARGET_64BIT ? ( HOST_WIDE_INT_1 << 29 ) : 0 ; } </s>


<s> const char * PPCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case PPCISD :: FSEL : return "PPCISD::FSEL" ; case PPCISD :: FCFID : return "PPCISD::FCFID" ; case PPCISD :: FCTIDZ : return "PPCISD::FCTIDZ" ; case PPCISD :: FCTIWZ : return "PPCISD::FCTIWZ" ; case PPCISD :: STFIWX : return "PPCISD::STFIWX" ; case PPCISD :: VMADDFP : return "PPCISD::VMADDFP" ; case PPCISD :: VNMSUBFP : return "PPCISD::VNMSUBFP" ; case PPCISD :: VPERM : return "PPCISD::VPERM" ; case PPCISD :: Hi : return "PPCISD::Hi" ; case PPCISD :: Lo : return "PPCISD::Lo" ; case PPCISD :: TOC_ENTRY : return "PPCISD::TOC_ENTRY" ; case PPCISD :: DYNALLOC : return "PPCISD::DYNALLOC" ; case PPCISD :: GlobalBaseReg : return "PPCISD::GlobalBaseReg" ; case PPCISD :: SRL : return "PPCISD::SRL" ; case PPCISD :: SRA : return "PPCISD::SRA" ; case PPCISD :: SHL : return "PPCISD::SHL" ; case PPCISD :: EXTSW_32 : return "PPCISD::EXTSW_32" ; case PPCISD :: STD_32 : return "PPCISD::STD_32" ; case PPCISD :: CALL_SVR4 : return "PPCISD::CALL_SVR4" ; case PPCISD :: CALL_Darwin : return "PPCISD::CALL_Darwin" ; case PPCISD :: NOP : return "PPCISD::NOP" ; case PPCISD :: MTCTR : return "PPCISD::MTCTR" ; case PPCISD :: BCTRL_Darwin : return "PPCISD::BCTRL_Darwin" ; case PPCISD :: BCTRL_SVR4 : return "PPCISD::BCTRL_SVR4" ; case PPCISD :: RET_FLAG : return "PPCISD::RET_FLAG" ; case PPCISD :: MFCR : return "PPCISD::MFCR" ; case PPCISD :: VCMP : return "PPCISD::VCMP" ; case PPCISD :: VCMPo : return "PPCISD::VCMPo" ; case PPCISD :: LBRX : return "PPCISD::LBRX" ; case PPCISD :: STBRX : return "PPCISD::STBRX" ; case PPCISD :: LARX : return "PPCISD::LARX" ; case PPCISD :: STCX : return "PPCISD::STCX" ; case PPCISD :: COND_BRANCH : return "PPCISD::COND_BRANCH" ; case PPCISD :: MFFS : return "PPCISD::MFFS" ; case PPCISD :: MTFSB0 : return "PPCISD::MTFSB0" ; case PPCISD :: MTFSB1 : return "PPCISD::MTFSB1" ; case PPCISD :: FADDRTZ : return "PPCISD::FADDRTZ" ; case PPCISD :: MTFSF : return "PPCISD::MTFSF" ; case PPCISD :: TC_RETURN : return "PPCISD::TC_RETURN" ; } } </s>

getTargetNodeName - This method returns the name of a target specific

PowerPC PPC 0 PPCISD::FSEL "PPCISD::FSEL" PPCISD::FCFID "PPCISD::FCFID" PPCISD::FCTIDZ "PPCISD::FCTIDZ" PPCISD::FCTIWZ "PPCISD::FCTIWZ" PPCISD::STFIWX "PPCISD::STFIWX" PPCISD::VMADDFP "PPCISD::VMADDFP" PPCISD::VNMSUBFP "PPCISD::VNMSUBFP" PPCISD::VPERM "PPCISD::VPERM" PPCISD::Hi "PPCISD::Hi" PPCISD::Lo "PPCISD::Lo" PPCISD::TOC_ENTRY "PPCISD::TOC_ENTRY" PPCISD::DYNALLOC "PPCISD::DYNALLOC" PPCISD::GlobalBaseReg "PPCISD::GlobalBaseReg" PPCISD::SRL "PPCISD::SRL" PPCISD::SRA "PPCISD::SRA" PPCISD::SHL "PPCISD::SHL" PPCISD::EXTSW_32 "PPCISD::EXTSW_32" PPCISD::STD_32 "PPCISD::STD_32" PPCISD::CALL_SVR4 "PPCISD::CALL_SVR4" PPCISD::CALL_Darwin "PPCISD::CALL_Darwin" PPCISD::NOP "PPCISD::NOP" PPCISD::MTCTR "PPCISD::MTCTR" PPCISD::BCTRL_Darwin "PPCISD::BCTRL_Darwin" PPCISD::BCTRL_SVR4 "PPCISD::BCTRL_SVR4" PPCISD::RET_FLAG "PPCISD::RET_FLAG" PPCISD::MFCR "PPCISD::MFCR" PPCISD::VCMP "PPCISD::VCMP" PPCISD::VCMPo "PPCISD::VCMPo" PPCISD::LBRX "PPCISD::LBRX" PPCISD::STBRX "PPCISD::STBRX" PPCISD::LARX "PPCISD::LARX" PPCISD::STCX "PPCISD::STCX" PPCISD::COND_BRANCH "PPCISD::COND_BRANCH" PPCISD::MFFS "PPCISD::MFFS" PPCISD::MTFSB0 "PPCISD::MTFSB0" PPCISD::MTFSB1 "PPCISD::MTFSB1" PPCISD::FADDRTZ "PPCISD::FADDRTZ" PPCISD::MTFSF "PPCISD::MTFSF" PPCISD::TC_RETURN "PPCISD::TC_RETURN"


<s>
SDValue
MSP430TargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
isVarArg
,
Ins
,
dl
,
DAG
,
InVals
)
;
case
CallingConv
::
MSP430_INTR
:
if
(
Ins
.
empty
(
)
)
return
Chain
;
report_fatal_error
(
"ISRs cannot have arguments"
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s>
MachineBasicBlock
::
iterator
AVRFrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
)
const
{
const
AVRSubtarget
&
STI
=
MF
.
getSubtarget
<
AVRSubtarget
>
(
)
;
const
AVRInstrInfo
&
TII
=
*
STI
.
getInstrInfo
(
)
;
if
(
hasReservedCallFrame
(
MF
)
)
{
fixStackStores
(
MBB
,
MI
,
TII
,
false
)
;
return
MBB
.
erase
(
MI
)
;
}
DebugLoc
DL
=
MI
->
getDebugLoc
(
)
;
unsigned
int
Opcode
=
MI
->
getOpcode
(
)
;
int
Amount
=
TII
.
getFrameSize
(
*
MI
)
;
if
(
Amount
!=
0
)
{
assert
(
getStackAlignment
(
)
==
1
&&
"Unsupported stack alignment"
)
;
if
(
Opcode
==
TII
.
getCallFrameSetupOpcode
(
)
)
{
fixStackStores
(
MBB
,
MI
,
TII
,
true
)
;
}
else
{
assert
(
Opcode
==
TII
.
getCallFrameDestroyOpcode
(
)
)
;
unsigned
addOpcode
;
if
(
isUInt
<
6
>
(
Amount
)
)
{
addOpcode
=
AVR
::
ADIWRdK
;
}
else
{
addOpcode
=
AVR
::
SUBIWRdK
;
Amount
=
Amount
;
}
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
SPREAD
)
,
AVR
::
R31R30
)
.
addReg
(
AVR
::
SP
)
;
MachineInstr
*
New
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
addOpcode
)
,
AVR
::
R31R30
)
.
addReg
(
AVR
::
R31R30
,
RegState
::
Kill
)
.
addImm
(
Amount
)
;
New
->
getOperand
(
3
)
.
setIsDead
(
)
;
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
SPWRITE
)
,
AVR
::
SP
)
.
addReg
(
AVR
::
R31R30
,
RegState
::
Kill
)
;
}
}
return
MBB
.
erase
(
MI
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool MLxExpansion :: runOnMachineFunction ( MachineFunction & Fn ) { TII = static_cast < const ARMBaseInstrInfo * > ( Fn . getTarget ( ) . getInstrInfo ( ) ) ; TRI = Fn . getTarget ( ) . getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; const ARMSubtarget * STI = & Fn . getTarget ( ) . getSubtarget < ARMSubtarget > ( ) ; isLikeA9 = STI -> isLikeA9 ( ) || STI -> isSwift ( ) ; isSwift = STI -> isSwift ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : Fn ) Modified |= ExpandFPMLxInstructions ( MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s>
void
AlphaRegisterInfo
::
emitPrologue
(
MachineFunction
&
MF
)
const
{
MachineBasicBlock
&
MBB
=
MF
.
front
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
DebugLoc
dl
=
(
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
::
getUnknownLoc
(
)
)
;
bool
FP
=
hasFP
(
MF
)
;
static
int
curgpdist
=
0
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
LDAHg
)
,
Alpha
::
R29
)
.
addGlobalAddress
(
const_cast
<
Function
*
>
(
MF
.
getFunction
(
)
)
)
.
addReg
(
Alpha
::
R27
)
.
addImm
(
++
curgpdist
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
LDAg
)
,
Alpha
::
R29
)
.
addGlobalAddress
(
const_cast
<
Function
*
>
(
MF
.
getFunction
(
)
)
)
.
addReg
(
Alpha
::
R29
)
.
addImm
(
curgpdist
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
ALTENT
)
)
.
addGlobalAddress
(
const_cast
<
Function
*
>
(
MF
.
getFunction
(
)
)
)
;
long
NumBytes
=
MFI
->
getStackSize
(
)
;
if
(
FP
)
NumBytes
+=
8
;
if
(
NumBytes
==
0
)
return
;
unsigned
Align
=
MF
.
getTarget
(
)
.
getFrameInfo
(
)
->
getStackAlignment
(
)
;
NumBytes
=
(
NumBytes
+
Align
1
)
/
Align
*
Align
;
MFI
->
setStackSize
(
NumBytes
)
;
NumBytes
=
NumBytes
;
if
(
NumBytes
>=
IMM_LOW
)
{
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
LDA
)
,
Alpha
::
R30
)
.
addImm
(
NumBytes
)
.
addReg
(
Alpha
::
R30
)
;
}
else
if
(
getUpper16
(
NumBytes
)
>=
IMM_LOW
)
{
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
LDAH
)
,
Alpha
::
R30
)
.
addImm
(
getUpper16
(
NumBytes
)
)
.
addReg
(
Alpha
::
R30
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
LDA
)
,
Alpha
::
R30
)
.
addImm
(
getLower16
(
NumBytes
)
)
.
addReg
(
Alpha
::
R30
)
;
}
else
{
cerr
<<
"Too big a stack frame at "
<<
NumBytes
<<
"\n"
;
abort
(
)
;
}
if
(
FP
)
{
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
STQ
)
)
.
addReg
(
Alpha
::
R15
)
.
addImm
(
0
)
.
addReg
(
Alpha
::
R30
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
BISr
)
,
Alpha
::
R15
)
.
addReg
(
Alpha
::
R30
)
.
addReg
(
Alpha
::
R30
)
;
}
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


"FrameIndex should have been previously eliminated!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static void cygwin_d_os_builtins ( void ) { d_add_builtin_version ( "Windows" ) ; d_add_builtin_version ( "Cygwin" ) ; d_add_builtin_version ( "Posix" ) ; d_add_builtin_version ( "CRuntime_Newlib" ) ; } </s>

Implement TARGET_D_OS_VERSIONS for Cygwin targets .


<s> bool Error ( SMLoc L , const Twine & Msg ) { return getParser ( ) . Error ( L , Msg ) ; } </s>

Return an error at the location L , with the message Msg .


<s> void HexagonFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; auto & HST = static_cast < const HexagonSubtarget & > ( MF . getSubtarget ( ) ) ; auto & HRI = * HST . getRegisterInfo ( ) ; bool HasEHReturn = MF . getInfo < HexagonMachineFunctionInfo > ( ) -> hasEHReturn ( ) ; if ( HasEHReturn ) { for ( const MCPhysReg * CSRegs = HRI . getCalleeSavedRegs ( & MF ) ; * CSRegs ; ++ CSRegs ) SavedRegs . set ( * CSRegs ) ; } const TargetRegisterClass & RC = Hexagon :: IntRegsRegClass ; bool HasReplacedPseudoInst = replacePseudoRegTransferCode ( MF ) ; if ( HasReplacedPseudoInst && needToReserveScavengingSpillSlots ( MF , HRI ) ) { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; for ( int i = 0 ; i < NumberScavengerSlots ; i ++ ) RS -> addScavengingFrameIndex ( MFI -> CreateSpillStackObject ( RC . getSize ( ) , RC . getAlignment ( ) ) ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .

Hexagon Hexagon Hexagon Hexagon Hexagon::IntRegsRegClass 0


<s> static unsigned rs6000_hash_constant ( rtx k ) { enum rtx_code code = GET_CODE ( k ) ; enum machine_mode mode = GET_MODE ( k ) ; unsigned result = ( code << 3 ) ^ mode ; const char * format ; int flen , fidx ; format = GET_RTX_FORMAT ( code ) ; flen = strlen ( format ) ; fidx = 0 ; switch ( code ) { case LABEL_REF : return result * 1231 + ( unsigned ) INSN_UID ( XEXP ( k , 0 ) ) ; case CONST_DOUBLE : if ( mode != VOIDmode ) return real_hash ( CONST_DOUBLE_REAL_VALUE ( k ) ) * result ; flen = 2 ; break ; case CODE_LABEL : fidx = 3 ; break ; default : break ; } for ( ; fidx < flen ; fidx ++ ) switch ( format [ fidx ] ) { case 's' : { unsigned i , len ; const char * str = XSTR ( k , fidx ) ; len = strlen ( str ) ; result = result * 613 + len ; for ( i = 0 ; i < len ; i ++ ) result = result * 613 + ( unsigned ) str [ i ] ; break ; } case 'u' : case 'e' : result = result * 1231 + rs6000_hash_constant ( XEXP ( k , fidx ) ) ; break ; case 'i' : case 'n' : result = result * 613 + ( unsigned ) XINT ( k , fidx ) ; break ; case 'w' : if ( sizeof ( unsigned ) >= sizeof ( HOST_WIDE_INT ) ) result = result * 613 + ( unsigned ) XWINT ( k , fidx ) ; else { size_t i ; for ( i = 0 ; i < sizeof ( HOST_WIDE_INT ) / sizeof ( unsigned ) ; i ++ ) result = result * 613 + ( unsigned ) ( XWINT ( k , fidx ) >> CHAR_BIT * i ) ; } break ; case '0' : break ; default : gcc_unreachable ( ) ; } return result ; } </s>


<s> static void free_bundle_state ( struct bundle_state * state ) { state -> next = free_bundle_state_chain ; free_bundle_state_chain = state ; } </s>

The following function frees given bundle state .


<s>
void
NVPTXInstPrinter
::
printRegName
(
raw_ostream
&
OS
,
unsigned
RegNo
)
const
{
unsigned
RCId
=
(
RegNo
>>
28
)
;
switch
(
RCId
)
{
default
:
report_fatal_error
(
"Bad virtual register encoding"
)
;
case
0
:
OS
<<
getRegisterName
(
RegNo
)
;
return
;
case
1
:
OS
<<
"%p"
;
break
;
case
2
:
OS
<<
"%rs"
;
break
;
case
3
:
OS
<<
"%r"
;
break
;
case
4
:
OS
<<
"%rd"
;
break
;
case
5
:
OS
<<
"%f"
;
break
;
case
6
:
OS
<<
"%fd"
;
break
;
}
unsigned
VReg
=
RegNo
&
0x0FFFFFFF
;
OS
<<
VReg
;
}
</s>


<s> void UnwindOpcodeAssembler :: EmitRegSave ( uint32_t RegSave ) { if ( RegSave == 0u ) return ; if ( RegSave & ( 1u << 4 ) ) { uint32_t Mask = RegSave & 0xff0u ; uint32_t Range = countTrailingOnes ( Mask >> 5 ) ; Mask &= ~ ( 0xffffffe0u << Range ) ; uint32_t UnmaskedReg = RegSave & 0xfff0u & ( ~ Mask ) ; if ( UnmaskedReg == 0u ) { EmitInt8 ( ARM :: EHABI :: UNWIND_OPCODE_POP_REG_RANGE_R4 | Range ) ; RegSave &= 0x000fu ; } else if ( UnmaskedReg == ( 1u << 14 ) ) { EmitInt8 ( ARM :: EHABI :: UNWIND_OPCODE_POP_REG_RANGE_R4_R14 | Range ) ; RegSave &= 0x000fu ; } } if ( ( RegSave & 0xfff0u ) != 0 ) EmitInt16 ( ARM :: EHABI :: UNWIND_OPCODE_POP_REG_MASK_R4 | ( RegSave >> 4 ) ) ; if ( ( RegSave & 0x000fu ) != 0 ) EmitInt16 ( ARM :: EHABI :: UNWIND_OPCODE_POP_REG_MASK | ( RegSave & 0x000fu ) ) ; } </s>

Emit unwind opcodes for .save directives .


<s> bool PPCDarwinAsmPrinter :: doFinalization ( Module & M ) { bool isPPC64 = TM . getTargetData ( ) -> getPointerSizeInBits ( ) == 64 ; TargetLoweringObjectFileMachO & TLOFMacho = static_cast < TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetFnStubList ( ) ; if ( ! Stubs . empty ( ) ) EmitFunctionStubs ( Stubs ) ; if ( MAI -> doesSupportExceptionHandling ( ) && MMI ) { const std :: vector < const Function * > & Personalities = MMI -> getPersonalities ( ) ; for ( std :: vector < const Function * > :: const_iterator I = Personalities . begin ( ) , E = Personalities . end ( ) ; I != E ; ++ I ) { if ( * I ) { MCSymbol * NLPSym = GetSymbolWithGlobalValueBase ( * I , "$non_lazy_ptr" ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMIMacho . getGVStubEntry ( NLPSym ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( * I ) , true ) ; } } } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue ( 0 , isPPC64 ? 8 : 4 , 0 ) ; else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 , 0 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 , 0 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> const SISubtarget * GCNTargetMachine :: getSubtargetImpl ( const Function & F ) const { StringRef GPU = getGPUName ( F ) ; StringRef FS = getFeatureString ( F ) ; SmallString < 128 > SubtargetKey ( GPU ) ; SubtargetKey . append ( FS ) ; auto & I = SubtargetMap [ SubtargetKey ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < SISubtarget > ( TargetTriple , GPU , FS , * this ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; SIGISelActualAccessor * GISel = new SIGISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new AMDGPUCallLowering ( * I -> getTargetLowering ( ) ) ) ; GISel -> Legalizer . reset ( new AMDGPULegalizerInfo ( ) ) ; GISel -> RegBankInfo . reset ( new AMDGPURegisterBankInfo ( * I -> getRegisterInfo ( ) ) ) ; GISel -> InstSelector . reset ( new AMDGPUInstructionSelector ( * I , * static_cast < AMDGPURegisterBankInfo * > ( GISel -> RegBankInfo . get ( ) ) ) ) ; I -> setGISelAccessor ( * GISel ) ; } I -> setScalarizeGlobalBehavior ( ScalarizeGlobal ) ; return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

AMDGPU SI 128 SI SI SI AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU


<s> void storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const override { storeRegToStack ( MBB , MBBI , SrcReg , isKill , FrameIndex , RC , TRI , 0 ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> Register PPCTargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { return Subtarget . isPPC64 ( ) ? PPC :: X3 : PPC :: R3 ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s> void Cpu0SEFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( MF . getFrameInfo ( ) . hasCalls ( ) ) setAliasRegs ( MF , SavedRegs , Cpu0 :: LR ) ; return ; } </s>


<s> int arc_output_addsi ( rtx * operands , bool cond_p , bool output_p ) { char format [ 35 ] ; int match = operands_match_p ( operands [ 0 ] , operands [ 1 ] ) ; int match2 = operands_match_p ( operands [ 0 ] , operands [ 2 ] ) ; int intval = ( REG_P ( operands [ 2 ] ) ? 1 : CONST_INT_P ( operands [ 2 ] ) ? INTVAL ( operands [ 2 ] ) : 0xbadc057 ) ; int neg_intval = - intval ; int short_0 = satisfies_constraint_Rcq ( operands [ 0 ] ) ; int short_p = ( ! cond_p && short_0 && satisfies_constraint_Rcq ( operands [ 1 ] ) ) ; int ret = 0 ; && REGNO ( OP ) != 30 ) \ || ! TARGET_V2 ) ) if ( output_p ) \ output_asm_insn ( FORMAT , operands ) ; \ return ret ; \ } </s>

Emit code for an addsi3 instruction with OPERANDS . COND_P indicates if this will use conditional execution . Return the length of the instruction . If OUTPUT_P is false , do n't actually output the instruction , just return its length .


<s>
void
Thumb1InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
bool
tDest
=
ARM
::
tGPRRegClass
.
contains
(
DestReg
)
;
bool
tSrc
=
ARM
::
tGPRRegClass
.
contains
(
SrcReg
)
;
unsigned
Opc
=
ARM
::
tMOVgpr2gpr
;
if
(
tDest
&&
tSrc
)
Opc
=
ARM
::
tMOVr
;
else
if
(
tSrc
)
Opc
=
ARM
::
tMOVtgpr2gpr
;
else
if
(
tDest
)
Opc
=
ARM
::
tMOVgpr2tgpr
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
assert
(
ARM
::
GPRRegClass
.
contains
(
DestReg
,
SrcReg
)
&&
"Thumb1 can only copy GPR registers"
)
;
}
</s>

ARM
ARM::tGPRRegClass
ARM::tGPRRegClass
ARM::tMOVgpr2gpr
ARM::tMOVr
ARM::tMOVtgpr2gpr
ARM::tMOVgpr2tgpr
ARM::GPRRegClass
"Thumb1 can only copy GPR registers"


<s> static void print_slot ( rtx_sequence * seq ) { final_scan_insn ( seq -> insn ( 1 ) , asm_out_file , optimize , 1 , NULL ) ; seq -> insn ( 1 ) -> set_deleted ( ) ; } </s>

Print an instruction which would have gone into a delay slot after another instruction , but could n't because the other instruction expanded into a sequence where putting the slot insn at the end would n't work .


<s> static void nvptx_skip_par ( unsigned mask , parallel * par ) { basic_block tail = par -> join_block ; gcc_assert ( tail -> preds -> length ( ) == 1 ) ; basic_block pre_tail = ( * tail -> preds ) [ 0 ] -> src ; gcc_assert ( pre_tail -> succs -> length ( ) == 1 ) ; nvptx_single ( mask , par -> forked_block , pre_tail ) ; } </s>

PAR is a parallel that is being skipped in its entirety according to MASK . Treat this as skipping a superblock starting at forked and ending at joining .


<s> Register LanaiRegisterInfo :: getFrameRegister ( const MachineFunction & ) const { return Lanai :: FP ; } </s>


<s> Instruction * back ( ) const { return Chain . back ( ) ; } </s>

back - Get the last character in the string .


<s> PreservedAnalyses run ( Module & M , ModuleAnalysisManager & ) { if ( lowerIntrinsics ( M ) ) return PreservedAnalyses :: none ( ) ; return PreservedAnalyses :: all ( ) ; } </s>

Run the analysis pass over a function and produce a dominator tree .


<s> bool doInitialization ( Module & M ) override { Result . reset ( new TPCAAResult ( ) ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> bool PPCInstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , const SmallVectorImpl < MachineOperand > & Cond , unsigned TrueReg , unsigned FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( ! Subtarget . hasISEL ( ) ) return false ; if ( Cond . size ( ) != 2 ) return false ; if ( Cond [ 1 ] . getReg ( ) == PPC :: CTR || Cond [ 1 ] . getReg ( ) == PPC :: CTR8 ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( ! PPC :: GPRCRegClass . hasSubClassEq ( RC ) && ! PPC :: GPRC_NOR0RegClass . hasSubClassEq ( RC ) && ! PPC :: G8RCRegClass . hasSubClassEq ( RC ) && ! PPC :: G8RC_NOX0RegClass . hasSubClassEq ( RC ) ) return false ; CondCycles = 1 ; TrueCycles = 1 ; FalseCycles = 1 ; return true ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> static void microblaze_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; cum -> arg_number ++ ; switch ( arg . mode ) { case E_VOIDmode : break ; default : gcc_assert ( GET_MODE_CLASS ( arg . mode ) == MODE_COMPLEX_INT || GET_MODE_CLASS ( arg . mode ) == MODE_COMPLEX_FLOAT ) ; cum -> gp_reg_found = 1 ; cum -> arg_words += ( ( GET_MODE_SIZE ( arg . mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ) ; break ; case E_BLKmode : cum -> gp_reg_found = 1 ; cum -> arg_words += ( ( int_size_in_bytes ( arg . type ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ) ; break ; case E_SFmode : cum -> arg_words ++ ; if ( ! cum -> gp_reg_found && cum -> arg_number <= 2 ) cum -> fp_code += 1 << ( ( cum -> arg_number - 1 ) * 2 ) ; break ; case E_DFmode : cum -> arg_words += 2 ; if ( ! cum -> gp_reg_found && cum -> arg_number <= 2 ) cum -> fp_code += 2 << ( ( cum -> arg_number - 1 ) * 2 ) ; break ; case E_DImode : cum -> gp_reg_found = 1 ; cum -> arg_words += 2 ; break ; case E_QImode : case E_HImode : case E_SImode : case E_TImode : cum -> gp_reg_found = 1 ; cum -> arg_words ++ ; break ; } } </s>

Advance the argument to the next argument position .


<s> void SNESAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { SNESMCInstLower MCInstLowering ( OutContext , * this ) ; MCInst I ; MCInstLowering . lowerInstruction ( * MI , I ) ; EmitToStreamer ( * OutStreamer , I ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


"LOAD_STACK_GUARD currently supported only for MachO."

This function is called for all pseudo instructions that remain after register allocation .


<s> Z80Subtarget & Z80Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { ParseSubtargetFeatures ( CPU , FS ) ; HasIdxHalfRegs = HasUndocOps || HasEZ80Ops ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> static void rs6000_init_dwarf_reg_sizes_extra ( tree address ) { if ( TARGET_MACHO && ! TARGET_ALTIVEC ) { int i ; machine_mode mode = TYPE_MODE ( char_type_node ) ; rtx addr = expand_expr ( address , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; rtx mem = gen_rtx_MEM ( BLKmode , addr ) ; rtx value = gen_int_mode ( 16 , mode ) ; for ( i = FIRST_ALTIVEC_REGNO ; i < LAST_ALTIVEC_REGNO + 1 ; i ++ ) { int column = DWARF_REG_TO_UNWIND_COLUMN ( DWARF2_FRAME_REG_OUT ( DWARF_FRAME_REGNUM ( i ) , true ) ) ; HOST_WIDE_INT offset = column * GET_MODE_SIZE ( mode ) ; emit_move_insn ( adjust_address ( mem , mode , offset ) , value ) ; } } } </s>

Fill in sizes of registers used by unwinder .


<s> void * getAdjustedAnalysisPointer ( const void * ID ) override { if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo * ) this ; return this ; } </s>

getAdjustedAnalysisPointer - This method is used when a pass implements an analysis interface through multiple inheritance .


<s> void sparc_expand_vcond ( machine_mode mode , rtx * operands , int ccode , int fcode ) { rtx mask , cop0 , cop1 , fcmp , cmask , bshuf , gsr ; enum rtx_code code = GET_CODE ( operands [ 3 ] ) ; mask = gen_reg_rtx ( Pmode ) ; cop0 = operands [ 4 ] ; cop1 = operands [ 5 ] ; if ( code == LT || code == GE ) { rtx t ; code = swap_condition ( code ) ; t = cop0 ; cop0 = cop1 ; cop1 = t ; } gsr = gen_rtx_REG ( DImode , SPARC_GSR_REG ) ; fcmp = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , gen_rtx_fmt_ee ( code , mode , cop0 , cop1 ) ) , fcode ) ; cmask = gen_rtx_UNSPEC ( DImode , gen_rtvec ( 2 , mask , gsr ) , ccode ) ; bshuf = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , operands [ 1 ] , operands [ 2 ] , gsr ) , UNSPEC_BSHUFFLE ) ; emit_insn ( gen_rtx_SET ( VOIDmode , mask , fcmp ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , gsr , cmask ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , bshuf ) ) ; } </s>

Emit code to conditionally move a combination of OPERANDS [ 1 ] and OPERANDS [ 2 ] into OPERANDS [ 0 ] in MODE , depending on the outcome of the comparison of OPERANDS [ 4 ] and OPERANDS [ 5 ] . OPERANDS [ 3 ] is the operator of the condition . FCODE is the machine code to be used for OPERANDS [ 3 ] and CCODE the machine code to be used for the condition mask .


<s> MachineBasicBlock :: iterator X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { bool reserveCallFrame = hasReservedCallFrame ( MF ) ; unsigned Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t InternalAmt = ( isDestroy || Amount ) ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; auto InsertPos = skipDebugInstructionsForward ( I , MBB . end ( ) ) ; if ( ! reserveCallFrame ) { unsigned StackAlign = getStackAlignment ( ) ; Amount = alignTo ( Amount , StackAlign ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const Function * Fn = MF . getFunction ( ) ; bool WindowsCFI = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool DwarfCFI = ! WindowsCFI && ( MMI . hasDebugInfo ( ) || Fn -> needsUnwindTableEntry ( ) ) ; bool HasDwarfEHHandlers = ! WindowsCFI && ! MF . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < X86MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == 0 ) return I ; Amount -= InternalAmt ; if ( isDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ; int64_t StackAdjustment = isDestroy ? Amount : - Amount ; int64_t CfaAdjustment = - StackAdjustment ; if ( StackAdjustment ) { StackAdjustment += mergeSPUpdates ( MBB , InsertPos , true ) ; StackAdjustment += mergeSPUpdates ( MBB , InsertPos , false ) ; if ( StackAdjustment ) { if ( ! ( Fn -> optForMinSize ( ) && adjustStackWithPops ( MBB , InsertPos , DL , StackAdjustment ) ) ) BuildStackAdjustment ( MBB , InsertPos , DL , StackAdjustment , false ) ; } } if ( DwarfCFI && ! hasFP ( MF ) ) { if ( CfaAdjustment ) { BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , CfaAdjustment ) ) ; } } return I ; } if ( isDestroy && InternalAmt ) { MachineBasicBlock :: iterator CI = I ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( CI != B && ! std :: prev ( CI ) -> isCall ( ) ) -- CI ; BuildStackAdjustment ( MBB , CI , DL , - InternalAmt , false ) ; } return I ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addPreservedID ( MachineLoopInfoID ) ; AU . addPreservedID ( MachineDominatorsID ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static bool nios2_tls_symbol_p ( rtx x ) { return ( targetm . have_tls && GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) != 0 ) ; } </s>

Return TRUE if X is a thread-local symbol .


<s> unsigned PPCInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case PPC :: LD : case PPC :: LWZ : case PPC :: LFS : case PPC :: LFD : case PPC :: RESTORE_CR : case PPC :: RESTORE_CRBIT : case PPC :: LVX : case PPC :: LXVD2X : case PPC :: LXVX : case PPC :: QVLFDX : case PPC :: QVLFSXs : case PPC :: QVLFDXb : case PPC :: RESTORE_VRSAVE : if ( MI . getOperand ( 1 ) . isImm ( ) && ! MI . getOperand ( 1 ) . getImm ( ) && MI . getOperand ( 2 ) . isFI ( ) ) { FrameIndex = MI . getOperand ( 2 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s>
bool
ARMAsmParser
::
ParseInstruction
(
StringRef
Name
,
SMLoc
NameLoc
,
SmallVectorImpl
<
MCParsedAsmOperand
*
>
&
Operands
)
{
size_t
Start
=
0
,
Next
=
Name
.
find
(
'.'
)
;
StringRef
Head
=
Name
.
slice
(
Start
,
Next
)
;
unsigned
CC
=
StringSwitch
<
unsigned
>
(
Head
.
substr
(
Head
.
size
(
)
2
)
)
.
Case
(
"eq"
,
ARMCC
::
EQ
)
.
Case
(
"ne"
,
ARMCC
::
NE
)
.
Case
(
"hs"
,
ARMCC
::
HS
)
.
Case
(
"lo"
,
ARMCC
::
LO
)
.
Case
(
"mi"
,
ARMCC
::
MI
)
.
Case
(
"pl"
,
ARMCC
::
PL
)
.
Case
(
"vs"
,
ARMCC
::
VS
)
.
Case
(
"vc"
,
ARMCC
::
VC
)
.
Case
(
"hi"
,
ARMCC
::
HI
)
.
Case
(
"ls"
,
ARMCC
::
LS
)
.
Case
(
"ge"
,
ARMCC
::
GE
)
.
Case
(
"lt"
,
ARMCC
::
LT
)
.
Case
(
"gt"
,
ARMCC
::
GT
)
.
Case
(
"le"
,
ARMCC
::
LE
)
.
Case
(
"al"
,
ARMCC
::
AL
)
.
Default
(
~
0U
)
;
if
(
CC
==
~
0U
||
(
CC
==
ARMCC
::
LS
&&
(
Head
==
"vmls"
||
Head
==
"vnmls"
)
)
)
{
CC
=
ARMCC
::
AL
;
}
else
{
Head
=
Head
.
slice
(
0
,
Head
.
size
(
)
2
)
;
}
Operands
.
push_back
(
ARMOperand
::
CreateToken
(
Head
,
NameLoc
)
)
;
if
(
Head
!=
"trap"
)
Operands
.
push_back
(
ARMOperand
::
CreateCondCode
(
ARMCC
::
CondCodes
(
CC
)
,
NameLoc
)
)
;
while
(
Next
!=
StringRef
::
npos
)
{
Start
=
Next
;
Next
=
Name
.
find
(
'.'
,
Start
+
1
)
;
Head
=
Name
.
slice
(
Start
,
Next
)
;
Operands
.
push_back
(
ARMOperand
::
CreateToken
(
Head
,
NameLoc
)
)
;
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
ParseOperand
(
Operands
)
)
{
Parser
.
EatToEndOfStatement
(
)
;
return
true
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
ParseOperand
(
Operands
)
)
{
Parser
.
EatToEndOfStatement
(
)
;
return
true
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
Parser
.
EatToEndOfStatement
(
)
;
return
TokError
(
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

ARM
ARM
0
2
"eq"
ARMCC::EQ
"ne"
ARMCC::NE
"hs"
ARMCC::HS
"lo"
ARMCC::LO
"mi"
ARMCC::MI
"pl"
ARMCC::PL
"vs"
ARMCC::VS
"vc"
ARMCC::VC
"hi"
ARMCC::HI
"ls"
ARMCC::LS
"ge"
ARMCC::GE
"lt"
ARMCC::LT
"gt"
ARMCC::GT
"le"
ARMCC::LE
"al"
ARMCC::AL
0U
0U
ARMCC::LS
"vmls"
"vnmls"
ARMCC::AL
0
2
ARM
"trap"
ARM
ARMCC::CondCodes
1
ARM
"unexpected token in argument list"


<s> static void ix86_output_indirect_branch ( rtx call_op , const char * xasm , bool sibcall_p ) { if ( REG_P ( call_op ) ) ix86_output_indirect_branch_via_reg ( call_op , sibcall_p ) ; else ix86_output_indirect_branch_via_push ( call_op , xasm , sibcall_p ) ; } </s>

Output indirect branch via a call and return thunk . CALL_OP is the branch target . XASM is the assembly template for CALL_OP . Branch is a tail call if SIBCALL_P is true .


<s> void X86IntelInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & OS ) { printInstFlags ( MI , OS ) ; if ( MI -> getOpcode ( ) == X86 :: DATA16_PREFIX && STI . getFeatureBits ( ) [ X86 :: Mode16Bit ] ) { OS << "\tdata32" ; } else if ( ! printAliasInstr ( MI , OS ) && ! printVecCompareInstr ( MI , OS ) ) printInstruction ( MI , Address , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAnyX86InstComments ( MI , * CommentStream , MII ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> void MipsInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { switch ( MI -> getOpcode ( ) ) { default : break ; } if ( ! printAliasInstr ( MI , O ) && ! printAlias ( * MI , O ) ) printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; switch ( MI -> getOpcode ( ) ) { default : break ; } } </s>


<s> static rtx loongarch_legitimize_tls_address ( rtx loc ) { rtx dest , tp , tmp ; enum tls_model model = SYMBOL_REF_TLS_MODEL ( loc ) ; rtx_insn * insn ; switch ( model ) { case TLS_MODEL_LOCAL_DYNAMIC : tmp = gen_rtx_REG ( Pmode , GP_RETURN ) ; dest = gen_reg_rtx ( Pmode ) ; insn = loongarch_call_tls_get_addr ( loc , SYMBOL_TLSLDM , tmp ) ; emit_libcall_block ( insn , dest , tmp , loc ) ; break ; case TLS_MODEL_GLOBAL_DYNAMIC : tmp = gen_rtx_REG ( Pmode , GP_RETURN ) ; dest = gen_reg_rtx ( Pmode ) ; insn = loongarch_call_tls_get_addr ( loc , SYMBOL_TLSGD , tmp ) ; emit_libcall_block ( insn , dest , tmp , loc ) ; break ; case TLS_MODEL_INITIAL_EXEC : tp = gen_rtx_REG ( Pmode , THREAD_POINTER_REGNUM ) ; tmp = gen_reg_rtx ( Pmode ) ; emit_insn ( loongarch_got_load_tls_ie ( tmp , loc ) ) ; dest = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_add3_insn ( dest , tmp , tp ) ) ; break ; case TLS_MODEL_LOCAL_EXEC : tp = gen_rtx_REG ( Pmode , THREAD_POINTER_REGNUM ) ; tmp = gen_reg_rtx ( Pmode ) ; emit_insn ( loongarch_got_load_tls_le ( tmp , loc ) ) ; dest = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_add3_insn ( dest , tmp , tp ) ) ; break ; default : gcc_unreachable ( ) ; } return dest ; } </s>

Generate the code to access LOC , a thread-local SYMBOL_REF , and return its address . The return value will be both a valid address and a valid SET_SRC ( either a REG or a LO_SUM ) .


<s> int fp_sethi_p ( rtx op ) { if ( GET_CODE ( op ) == CONST_DOUBLE ) { long i ; REAL_VALUE_TO_TARGET_SINGLE ( * CONST_DOUBLE_REAL_VALUE ( op ) , i ) ; return ! SPARC_SIMM13_P ( i ) && SPARC_SETHI_P ( i ) ; } return 0 ; } </s>

Nonzero if OP is a floating point constant which can be loaded into an integer register using a single sethi instruction .


<s> static opt_machine_mode ix86_get_mask_mode ( machine_mode data_mode ) { unsigned vector_size = GET_MODE_SIZE ( data_mode ) ; unsigned nunits = GET_MODE_NUNITS ( data_mode ) ; unsigned elem_size = vector_size / nunits ; if ( ( TARGET_AVX512F && vector_size == 64 ) || ( TARGET_AVX512VL && ( vector_size == 32 || vector_size == 16 ) ) ) { if ( elem_size == 4 || elem_size == 8 || ( TARGET_AVX512BW && ( elem_size == 1 || elem_size == 2 ) ) ) return smallest_int_mode_for_size ( nunits ) ; } scalar_int_mode elem_mode = smallest_int_mode_for_size ( elem_size * BITS_PER_UNIT ) ; gcc_assert ( elem_size * nunits == vector_size ) ; return mode_for_vector ( elem_mode , nunits ) ; } </s>

Implemenation of targetm.vectorize.get_mask_mode .


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override { if ( Count % 4 != 0 ) return false ; uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> write32 ( 0x01000000 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s>
unsigned
AArch64FastISel
::
fastMaterializeConstant
(
const
Constant
*
C
)
{
EVT
CEVT
=
TLI
.
getValueType
(
DL
,
C
->
getType
(
)
,
true
)
;
if
(
!
CEVT
.
isSimple
(
)
)
return
0
;
MVT
VT
=
CEVT
.
getSimpleVT
(
)
;
if
(
isa
<
ConstantPointerNull
>
(
C
)
)
{
assert
(
VT
==
MVT
::
i64
&&
"Expected 64-bit pointers"
)
;
return
materializeInt
(
ConstantInt
::
get
(
Type
::
getInt64Ty
(
*
Context
)
,
0
)
,
VT
)
;
}
if
(
const
auto
*
CI
=
dyn_cast
<
ConstantInt
>
(
C
)
)
return
materializeInt
(
CI
,
VT
)
;
else
if
(
const
ConstantFP
*
CFP
=
dyn_cast
<
ConstantFP
>
(
C
)
)
return
materializeFP
(
CFP
,
VT
)
;
else
if
(
const
GlobalValue
*
GV
=
dyn_cast
<
GlobalValue
>
(
C
)
)
return
materializeGV
(
GV
)
;
return
0
;
}
</s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


"-misched-topdown incompatible with -misched-bottomup"

Initialize the strategy after building the DAG for a new region .


<s> static BasicBlock :: iterator tryCombine ( BasicBlock :: iterator Start , BasicBlock :: iterator End ) { assert ( Start != End ) ; auto CS = CallSite ( & * Start ) ; unsigned Size = cast < ConstantInt > ( CS . getArgument ( 2 ) ) -> getZExtValue ( ) ; auto It = std :: next ( Start ) , Prev = Start ; bool Combinable = false ; for ( ; It != End ; Prev = It ++ ) { if ( auto CurrentCS = storeConstCallSite ( & * It ) ) { CanCombine Status = canCombine ( Size , CurrentCS ) ; if ( Status != CanCombine :: No && CallSite ( & * It ) . getArgument ( 1 ) == & * Prev ) { Combinable = true ; Size += cast < ConstantInt > ( CurrentCS . getArgument ( 2 ) ) -> getZExtValue ( ) ; if ( Status == CanCombine :: Last || ! It -> hasOneUse ( ) ) { ++ It ; break ; } continue ; } } break ; } if ( Combinable && std :: next ( Start ) != It ) combine ( Start , It ) ; return It ; } </s>

Try to transform MI by using all of the above combine functions .


<s> bool M68kInstrInfo :: isPCRelRegisterOperandLegal ( const MachineOperand & MO ) const { assert ( MO . isReg ( ) ) ; const auto * MI = MO . getParent ( ) ; const uint8_t * Beads = M68k :: getMCInstrBeads ( MI -> getOpcode ( ) ) ; assert ( * Beads ) ; const uint8_t EncEAk [ 3 ] = { 0b011 , 0b1 , 0b11 } ; for ( const uint8_t Pat : EncEAk ) { uint8_t Bead = * ( Beads ++ ) ; if ( ! Bead ) return false ; switch ( Bead & 0xF ) { default : return false ; case M68kBeads :: Bits1 : case M68kBeads :: Bits2 : case M68kBeads :: Bits3 : { uint8_t Val = ( Bead & 0xF0 ) >> 4 ; if ( Val != Pat ) return false ; } } } return true ; } </s>

Allow targets to tell MachineVerifier whether a specific register MachineOperand can be used as part of PC-relative addressing .


"Callee saved registers requested for unknown architecture "


<s> const uint32_t * MipsRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { const MipsSubtarget & Subtarget = MF . getSubtarget < MipsSubtarget > ( ) ; if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_RegMask ; if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_RegMask ; if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_RegMask ; if ( Subtarget . isFP64bit ( ) ) return CSR_O32_FP64_RegMask ; if ( Subtarget . isFPXX ( ) ) return CSR_O32_FPXX_RegMask ; return CSR_O32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool XCoreTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty ) const { if ( Ty -> getTypeID ( ) == Type :: VoidTyID ) return AM . Scale == 0 && isImmUs ( AM . BaseOffs ) && isImmUs4 ( AM . BaseOffs ) ; const TargetData * TD = TM . getTargetData ( ) ; unsigned Size = TD -> getTypeAllocSize ( Ty ) ; if ( AM . BaseGV ) { return Size >= 4 && ! AM . HasBaseReg && AM . Scale == 0 && AM . BaseOffs % 4 == 0 ; } switch ( Size ) { case 1 : if ( AM . Scale == 0 ) { return isImmUs ( AM . BaseOffs ) ; } return AM . Scale == 1 && AM . BaseOffs == 0 ; case 2 : case 3 : if ( AM . Scale == 0 ) { return isImmUs2 ( AM . BaseOffs ) ; } return AM . Scale == 2 && AM . BaseOffs == 0 ; default : if ( AM . Scale == 0 ) { return isImmUs4 ( AM . BaseOffs ) ; } return AM . Scale == 4 && AM . BaseOffs == 0 ; } } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> void AMDGPUPassConfig :: addCodeGenPrepare ( ) { const AMDGPUTargetMachine & TM = getAMDGPUTargetMachine ( ) ; const AMDGPUSubtarget & ST = * TM . getSubtargetImpl ( ) ; if ( TM . getOptLevel ( ) > CodeGenOpt :: None && ST . isPromoteAllocaEnabled ( ) ) { addPass ( createAMDGPUPromoteAlloca ( & TM ) ) ; addPass ( createSROAPass ( ) ) ; } TargetPassConfig :: addCodeGenPrepare ( ) ; } </s>

Add pass to prepare the LLVM IR for code generation .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU


<s> static void arm_emit_multi_reg_pop ( unsigned long saved_regs_mask ) { int num_regs = 0 ; int i , j ; rtx par ; rtx dwarf = NULL_RTX ; rtx tmp , reg ; bool return_in_pc = saved_regs_mask & ( 1 << PC_REGNUM ) ; int offset_adj ; int emit_update ; offset_adj = return_in_pc ? 1 : 0 ; for ( i = 0 ; i <= LAST_ARM_REGNUM ; i ++ ) if ( saved_regs_mask & ( 1 << i ) ) num_regs ++ ; gcc_assert ( num_regs && num_regs <= 16 ) ; emit_update = ( saved_regs_mask & ( 1 << SP_REGNUM ) ) ? 0 : 1 ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs + emit_update + offset_adj ) ) ; if ( return_in_pc ) XVECEXP ( par , 0 , 0 ) = ret_rtx ; if ( emit_update ) { tmp = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , 4 * num_regs ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , offset_adj ) = tmp ; } for ( j = 0 , i = 0 ; j < num_regs ; i ++ ) if ( saved_regs_mask & ( 1 << i ) ) { reg = gen_rtx_REG ( SImode , i ) ; if ( ( num_regs == 1 ) && emit_update && ! return_in_pc ) { tmp = gen_frame_mem ( SImode , gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ) ; tmp = emit_insn ( gen_rtx_SET ( VOIDmode , reg , tmp ) ) ; REG_NOTES ( tmp ) = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; return ; } tmp = gen_rtx_SET ( VOIDmode , reg , gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , 4 * j ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , j + emit_update + offset_adj ) = tmp ; if ( i != PC_REGNUM ) dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; j ++ ; } if ( return_in_pc ) par = emit_jump_insn ( par ) ; else par = emit_insn ( par ) ; REG_NOTES ( par ) = dwarf ; if ( ! return_in_pc ) arm_add_cfa_adjust_cfa_note ( par , UNITS_PER_WORD * num_regs , stack_pointer_rtx , stack_pointer_rtx ) ; } </s>

Generate and emit an insn pattern that we will recognize as a pop_multi . SAVED_REGS_MASK shows which registers need to be restored . Unfortunately , since this insn does not reflect very well the actual semantics of the operation , we need to annotate the insn for the benefit of DWARF2 frame unwind information .


<s> unsigned MipsTargetLowering :: getVectorTypeBreakdownForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT , EVT & IntermediateVT , unsigned & NumIntermediates , MVT & RegisterVT ) const { RegisterVT = getRegisterTypeForCallingConv ( Context , CC , VT ) ; IntermediateVT = RegisterVT ; NumIntermediates = VT . getSizeInBits ( ) < RegisterVT . getSizeInBits ( ) ? VT . getVectorNumElements ( ) : VT . getSizeInBits ( ) / RegisterVT . getSizeInBits ( ) ; return NumIntermediates ; } </s>

Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts .


<s> bool SystemZXPLINKFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MutableArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; SystemZMachineFunctionInfo * ZFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; const SystemZSubtarget & Subtarget = MF . getSubtarget < SystemZSubtarget > ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; auto & Regs = Subtarget . getSpecialRegisters < SystemZXPLINK64Registers > ( ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; for ( unsigned I = 0 , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( SystemZ :: FP64BitRegClass . contains ( Reg ) ) TII -> loadRegFromStackSlot ( MBB , MBBI , Reg , CSI [ I ] . getFrameIdx ( ) , & SystemZ :: FP64BitRegClass , TRI ) ; if ( SystemZ :: VR128BitRegClass . contains ( Reg ) ) TII -> loadRegFromStackSlot ( MBB , MBBI , Reg , CSI [ I ] . getFrameIdx ( ) , & SystemZ :: VR128BitRegClass , TRI ) ; } SystemZ :: GPRRegs RestoreGPRs = ZFI -> getRestoreGPRRegs ( ) ; if ( RestoreGPRs . LowGPR ) { assert ( isInt < 20 > ( Regs . getStackPointerBias ( ) + RestoreGPRs . GPROffset ) ) ; if ( RestoreGPRs . LowGPR == RestoreGPRs . HighGPR ) BuildMI ( MBB , MBBI , DL , TII -> get ( SystemZ :: LG ) , RestoreGPRs . LowGPR ) . addReg ( Regs . getStackPointerRegister ( ) ) . addImm ( Regs . getStackPointerBias ( ) + RestoreGPRs . GPROffset ) . addReg ( 0 ) ; else { MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( SystemZ :: LMG ) ) ; MIB . addReg ( RestoreGPRs . LowGPR , RegState :: Define ) ; MIB . addReg ( RestoreGPRs . HighGPR , RegState :: Define ) ; MIB . addReg ( Regs . getStackPointerRegister ( ) ) ; MIB . addImm ( Regs . getStackPointerBias ( ) + RestoreGPRs . GPROffset ) ; for ( unsigned I = 0 , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( Reg > RestoreGPRs . LowGPR && Reg < RestoreGPRs . HighGPR ) MIB . addReg ( Reg , RegState :: ImplicitDefine ) ; } } } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> void DLXPassConfig :: addPreEmitPass ( ) { addPass ( createDLXDelaySlotFillerPass ( getDLXTargetMachine ( ) ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static void sh_canonicalize_comparison ( int * code , rtx * op0 , rtx * op1 , bool op0_preserve_value ) { enum rtx_code tmp_code = ( enum rtx_code ) * code ; sh_canonicalize_comparison ( tmp_code , * op0 , * op1 , VOIDmode , op0_preserve_value ) ; * code = ( int ) tmp_code ; } </s>

This function implements the canonicalize_comparison target hook . This wrapper around the internally used sh_canonicalize_comparison function is needed to do the enum rtx_code < - > int conversion . Target hooks can not use enum rtx_code in its definition .


<s> tree aarch64_fold_builtin ( tree fndecl , int n_args ATTRIBUTE_UNUSED , tree * args , bool ignore ATTRIBUTE_UNUSED ) { int fcode = DECL_FUNCTION_CODE ( fndecl ) ; tree type = TREE_TYPE ( TREE_TYPE ( fndecl ) ) ; switch ( fcode ) { BUILTIN_VDQF ( UNOP , abs , 2 ) return fold_build1 ( ABS_EXPR , type , args [ 0 ] ) ; VAR1 ( UNOP , floatv2si , 2 , v2sf ) VAR1 ( UNOP , floatv4si , 2 , v4sf ) VAR1 ( UNOP , floatv2di , 2 , v2df ) return fold_build1 ( FLOAT_EXPR , type , args [ 0 ] ) ; default : break ; } return NULL_TREE ; } </s>


"Cannot store this register to stack slot!"

Load the specified register of the given register class from the specified stack frame index .


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override { ScheduleDAGMI * DAG = createGenericSchedPostRA ( C ) ; const GCNSubtarget & ST = C -> MF -> getSubtarget < GCNSubtarget > ( ) ; DAG -> addMutation ( createLoadClusterDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; DAG -> addMutation ( ST . createFillMFMAShadowMutation ( DAG -> TII ) ) ; DAG -> addMutation ( createMFMAIGroupLPDAGMutation ( ) ) ; return DAG ; } </s>

Similar to createMachineScheduler but used when postRA machine scheduling is enabled .


<s> void create_regs_rtx ( void ) { ix_reg = gen_rtx_REG ( HImode , HARD_X_REGNUM ) ; iy_reg = gen_rtx_REG ( HImode , HARD_Y_REGNUM ) ; d_reg = gen_rtx_REG ( HImode , HARD_D_REGNUM ) ; m68hc11_soft_tmp_reg = gen_rtx_REG ( HImode , SOFT_TMP_REGNUM ) ; stack_push_word = gen_rtx_MEM ( HImode , gen_rtx_PRE_DEC ( HImode , gen_rtx_REG ( HImode , HARD_SP_REGNUM ) ) ) ; stack_pop_word = gen_rtx_MEM ( HImode , gen_rtx_POST_INC ( HImode , gen_rtx_REG ( HImode , HARD_SP_REGNUM ) ) ) ; } </s>


<s> bool Mips16FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { return true ; } </s>


<s> bool ARMTargetLowering :: isCheapToSpeculateCttz ( ) const { return Subtarget -> hasV6T2Ops ( ) ; } </s>

Return true if it is cheap to speculate a call to intrinsic cttz .


<s> bool AMDGPUPromoteAlloca :: doInitialization ( Module & M ) { Mod = & M ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> EVT PPCTargetLowering :: getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const { if ( getTargetMachine ( ) . getOptLevel ( ) != CodeGenOpt :: None ) { if ( Subtarget . hasQPX ( ) && Op . size ( ) >= 32 && ( Op . isMemcpy ( ) || Op . size ( ) >= 64 ) && Op . isAligned ( Align ( 32 ) ) && ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { return MVT :: v4f64 ; } if ( Subtarget . hasAltivec ( ) && Op . size ( ) >= 16 && ( Op . isAligned ( Align ( 16 ) ) || ( ( Op . isMemset ( ) && Subtarget . hasVSX ( ) ) || Subtarget . hasP8Vector ( ) ) ) ) return MVT :: v4i32 ; } if ( Subtarget . isPPC64 ( ) ) { return MVT :: i64 ; } return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> static void ia64_setup_incoming_varargs ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int * pretend_size , int second_time ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS next_cum = * cum ; ia64_function_arg_advance ( & next_cum , mode , type , 1 ) ; if ( next_cum . words < MAX_ARGUMENT_SLOTS ) { int n = MAX_ARGUMENT_SLOTS - next_cum . words ; * pretend_size = n * UNITS_PER_WORD ; cfun -> machine -> n_varargs = n ; } } </s>

Do any needed setup for a variadic function . CUM has not been updated for the last named argument which has type TYPE and mode MODE . We generate the actual spill instructions during prologue generation .


<s> bool RISCVInstrInfo :: isAsCheapAsAMove ( const MachineInstr & MI ) const { const unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : break ; case RISCV :: FSGNJ_D : case RISCV :: FSGNJ_S : case RISCV :: FSGNJ_H : return MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 2 ) . isReg ( ) && MI . getOperand ( 1 ) . getReg ( ) == MI . getOperand ( 2 ) . getReg ( ) ; case RISCV :: ADDI : case RISCV :: ORI : case RISCV :: XORI : return ( MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 1 ) . getReg ( ) == RISCV :: X0 ) || ( MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) ; } return MI . isAsCheapAsAMove ( ) ; } </s>

Return true if the instruction is as cheap as a move instruction .


<s> virtual EVT getSetCCResultType ( LLVMContext & , EVT ) const LLVM_OVERRIDE { return MVT :: i32 ; } </s>

Return the value type to use for ISD : :SETCC .


"This resolveFrameIndex does not support Thumb1!"

"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> void visium_expand_copysign ( rtx * operands , enum machine_mode mode ) { rtx op0 = operands [ 0 ] ; rtx op1 = operands [ 1 ] ; rtx op2 = operands [ 2 ] ; rtx mask = force_reg ( SImode , GEN_INT ( 0x7fffffff ) ) ; rtx x ; gcc_assert ( mode == SFmode ) ; if ( GET_CODE ( op1 ) == CONST_DOUBLE ) { if ( real_isneg ( CONST_DOUBLE_REAL_VALUE ( op1 ) ) ) op1 = simplify_unary_operation ( ABS , mode , op1 , mode ) ; if ( op1 != CONST0_RTX ( mode ) ) { long l ; REAL_VALUE_TO_TARGET_SINGLE ( * CONST_DOUBLE_REAL_VALUE ( op1 ) , l ) ; op1 = force_reg ( SImode , gen_int_mode ( l , SImode ) ) ; } } else { op1 = copy_to_mode_reg ( SImode , gen_lowpart ( SImode , op1 ) ) ; op1 = force_reg ( SImode , gen_rtx_AND ( SImode , op1 , mask ) ) ; } mask = force_reg ( SImode , gen_rtx_NOT ( SImode , mask ) ) ; op2 = copy_to_mode_reg ( SImode , gen_lowpart ( SImode , op2 ) ) ; op2 = force_reg ( SImode , gen_rtx_AND ( SImode , op2 , mask ) ) ; if ( op1 == CONST0_RTX ( SFmode ) ) x = op2 ; else x = force_reg ( SImode , gen_rtx_IOR ( SImode , op1 , op2 ) ) ; emit_insn ( gen_rtx_SET ( op0 , gen_lowpart ( SFmode , x ) ) ) ; } </s>


<s> static bool frv_sort_insn_group_1 ( enum frv_insn_group group , unsigned int lower_slot , unsigned int upper_slot , unsigned int issued , unsigned int num_insns , state_t state ) { struct frv_packet_group * packet_group ; unsigned int i ; state_t test_state ; size_t dfa_size ; rtx_insn * insn ; if ( lower_slot == upper_slot ) return true ; packet_group = & frv_packet . groups [ group ] ; dfa_size = state_size ( ) ; test_state = alloca ( dfa_size ) ; for ( i = num_insns - 1 ; i + 1 != 0 ; i -- ) if ( ~ issued & ( 1 << i ) ) { insn = packet_group -> sorted [ i ] ; memcpy ( test_state , state , dfa_size ) ; if ( state_transition ( test_state , insn ) < 0 && cpu_unit_reservation_p ( test_state , NTH_UNIT ( group , upper_slot - 1 ) ) && frv_sort_insn_group_1 ( group , lower_slot , upper_slot - 1 , issued | ( 1 << i ) , num_insns , test_state ) ) { packet_group -> sorted [ upper_slot - 1 ] = insn ; return true ; } } return false ; } </s>

Subroutine of frv_sort_insn_group . We are trying to sort frv_packet.groups [ GROUP ] .sorted [ 0 ... NUM_INSNS-1 ] into assembly language order . We have already picked a new position for frv_packet.groups [ GROUP ] .sorted [ X ] if bit X of ISSUED is set . These instructions will occupy elements [ 0 , LOWER_SLOT ) and [ UPPER_SLOT , NUM_INSNS ) of the final ( sorted ) array . STATE is the DFA state after issuing these instructions . Try filling elements [ LOWER_SLOT , UPPER_SLOT ) with every permutation of the unused instructions . Return true if one such permutation gives a valid ordering , leaving the successful permutation in sorted [ ] . Do not modify sorted [ ] until a valid permutation is found .


"c4x_operand_subword: address not offsettable"

This is similar to operand_subword but allows autoincrement addressing .


<s> void x86_output_aligned_bss ( FILE * file , tree decl , const char * name , unsigned HOST_WIDE_INT size , unsigned align ) { if ( ( ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC ) && size > ( unsigned int ) ix86_section_threshold ) switch_to_section ( get_named_section ( decl , ".lbss" , 0 ) ) ; else switch_to_section ( bss_section ) ; ASM_OUTPUT_ALIGN ( file , floor_log2 ( align / BITS_PER_UNIT ) ) ; last_assemble_variable_decl = decl ; ASM_DECLARE_OBJECT_NAME ( file , name , decl ) ; ASM_OUTPUT_LABEL ( file , name ) ; ASM_OUTPUT_SKIP ( file , size ? size : 1 ) ; } </s>

Utility function for targets to use in implementing ASM_OUTPUT_ALIGNED_BSS .


<s> bool ARMTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( Subtarget -> isThumb1Only ( ) ) return false ; EVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == ISD :: SEXTLOAD ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; } else return false ; bool isInc ; bool isLegal = false ; if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = getARMIndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( ! isLegal ) return false ; AM = isInc ? ISD :: POST_INC : ISD :: POST_DEC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .

ARM ARM ISD::MemIndexedMode ISD::SEXTLOAD ARM ISD::POST_INC ISD::POST_DEC


<s>
virtual
void
relaxInstruction
(
const
MCInst
&
Inst
,
MCInst
&
Res
)
const
{
assert
(
!
"Not implemented"
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> static void alpha_setup_incoming_varargs ( cumulative_args_t pcum , const function_arg_info & arg , int * pretend_size , int no_rtl ) { CUMULATIVE_ARGS cum = * get_cumulative_args ( pcum ) ; targetm . calls . function_arg_advance ( pack_cumulative_args ( & cum ) , arg ) ; if ( cum . num_args < 6 ) { if ( ! no_rtl ) { emit_move_insn ( gen_rtx_REG ( DImode , 1 ) , virtual_incoming_args_rtx ) ; emit_insn ( gen_arg_home ( ) ) ; } * pretend_size = 7 * UNITS_PER_WORD ; } if ( cum >= 6 ) return ; if ( ! no_rtl ) { int count ; alias_set_type set = get_varargs_alias_set ( ) ; rtx tmp ; count = cfun -> va_list_gpr_size / UNITS_PER_WORD ; if ( count > 6 - cum ) count = 6 - cum ; gcc_assert ( ( VA_LIST_MAX_FPR_SIZE & 3 ) == 3 ) ; if ( cfun -> va_list_fpr_size & 1 ) { tmp = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , virtual_incoming_args_rtx , ( cum + 6 ) * UNITS_PER_WORD ) ) ; MEM_NOTRAP_P ( tmp ) = 1 ; set_mem_alias_set ( tmp , set ) ; move_block_from_reg ( 16 + cum , tmp , count ) ; } if ( cfun -> va_list_fpr_size & 2 ) { tmp = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , virtual_incoming_args_rtx , cum * UNITS_PER_WORD ) ) ; MEM_NOTRAP_P ( tmp ) = 1 ; set_mem_alias_set ( tmp , set ) ; move_block_from_reg ( 16 + cum + TARGET_FPREGS * 32 , tmp , count ) ; } } * pretend_size = 12 * UNITS_PER_WORD ; } </s>

Perform any needed actions needed for a function that is receiving a variable number of arguments .


<s> void visium_expand_copysign ( rtx * operands , enum machine_mode mode ) { rtx dest = operands [ 0 ] ; rtx op0 = operands [ 1 ] ; rtx op1 = operands [ 2 ] ; rtx mask = force_reg ( SImode , GEN_INT ( 0x7fffffff ) ) ; rtx x ; gcc_assert ( mode == SFmode ) ; if ( GET_CODE ( op0 ) == CONST_DOUBLE ) { if ( real_isneg ( CONST_DOUBLE_REAL_VALUE ( op0 ) ) ) op0 = simplify_unary_operation ( ABS , mode , op0 , mode ) ; if ( op0 != CONST0_RTX ( mode ) ) { long l ; REAL_VALUE_TO_TARGET_SINGLE ( * CONST_DOUBLE_REAL_VALUE ( op0 ) , l ) ; op0 = force_reg ( SImode , GEN_INT ( trunc_int_for_mode ( l , SImode ) ) ) ; } } else { op0 = copy_to_mode_reg ( SImode , gen_lowpart ( SImode , op0 ) ) ; op0 = force_reg ( SImode , gen_rtx_AND ( SImode , op0 , mask ) ) ; } mask = force_reg ( SImode , gen_rtx_NOT ( SImode , mask ) ) ; op1 = copy_to_mode_reg ( SImode , gen_lowpart ( SImode , op1 ) ) ; op1 = force_reg ( SImode , gen_rtx_AND ( SImode , op1 , mask ) ) ; if ( op0 == CONST0_RTX ( SFmode ) ) x = op1 ; else x = force_reg ( SImode , gen_rtx_IOR ( SImode , op0 , op1 ) ) ; emit_insn ( gen_rtx_SET ( dest , gen_lowpart ( SFmode , x ) ) ) ; } </s>


<s> unsigned ARMTargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) const { return Subtarget -> useSjLjEH ( ) ? ARM :: NoRegister : ARM :: R1 ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .


<s>
void
NVPTXFrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
if
(
MF
.
getFrameInfo
(
)
->
hasStackObjects
(
)
)
{
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineInstr
*
MI
=
MBB
.
begin
(
)
;
MachineRegisterInfo
&
MR
=
MF
.
getRegInfo
(
)
;
DebugLoc
dl
=
DebugLoc
(
)
;
bool
Is64Bit
=
static_cast
<
const
NVPTXTargetMachine
&
>
(
MF
.
getTarget
(
)
)
.
is64Bit
(
)
;
unsigned
CvtaLocalOpcode
=
(
Is64Bit
NVPTX
::
cvta_local_yes_64
:
NVPTX
::
cvta_local_yes
)
;
unsigned
MovDepotOpcode
=
(
Is64Bit
NVPTX
::
MOV_DEPOT_ADDR_64
:
NVPTX
::
MOV_DEPOT_ADDR
)
;
if
(
!
MR
.
use_empty
(
NVPTX
::
VRFrame
)
)
{
MI
=
BuildMI
(
MBB
,
MI
,
dl
,
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
->
get
(
CvtaLocalOpcode
)
,
NVPTX
::
VRFrame
)
.
addReg
(
NVPTX
::
VRFrameLocal
)
;
}
BuildMI
(
MBB
,
MI
,
dl
,
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
->
get
(
MovDepotOpcode
)
,
NVPTX
::
VRFrameLocal
)
.
addImm
(
MF
.
getFunctionNumber
(
)
)
;
}
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

NVPTX
NVPTX
"Shrink-wrapping not yet supported"
NVPTX
NVPTX::cvta_local_yes_64
NVPTX::cvta_local_yes
NVPTX::MOV_DEPOT_ADDR_64
NVPTX::MOV_DEPOT_ADDR
NVPTX::VRFrame
NVPTX::VRFrame
NVPTX::VRFrameLocal
NVPTX::VRFrameLocal


<s> Register getScratchRSrcReg ( ) const { return ScratchRSrcReg ; } </s>

Returns the physical register reserved for use as the resource descriptor for scratch accesses .


<s> MVT getPointerTy ( const DataLayout & DL , uint32_t AS = 0 ) const override { return MVT :: getIntegerVT ( 64 ) ; } </s>

Return the pointer type for the given address space , defaults to the pointer type from the data layout .


<s> bool tilepro_emit_setcc ( rtx operands [ ] , machine_mode cmp_mode ) { return tilepro_emit_setcc_internal ( operands [ 0 ] , GET_CODE ( operands [ 1 ] ) , operands [ 2 ] , operands [ 3 ] , cmp_mode ) ; } </s>


<s> BitVector TLCS900RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; Reserved . set ( TLCS900 :: PCB ) ; Reserved . set ( TLCS900 :: SPB ) ; Reserved . set ( TLCS900 :: SRB ) ; Reserved . set ( TLCS900 :: CGB ) ; Reserved . set ( TLCS900 :: PCW ) ; Reserved . set ( TLCS900 :: SPW ) ; Reserved . set ( TLCS900 :: SRW ) ; Reserved . set ( TLCS900 :: CGW ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( TLCS900 :: FPW ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool isMachineVerifierClean ( ) const override { return false ; } </s>

Returns true if the target is expected to pass all machine verifier checks .


<s>
void
RISCVAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
)
const
{
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
if
(
!
Value
)
return
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
Ctx
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
unsigned
NumBytes
=
(
Info
.
TargetSize
+
7
)
/
8
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
4
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .