<s> bool X86TTIImpl :: isLegalMaskedGather ( Type * DataTy , Align Alignment ) { if ( ! ( ST -> hasAVX512 ( ) || ( ST -> hasFastGather ( ) && ST -> hasAVX2 ( ) ) ) ) return false ; if ( auto * DataVTy = dyn_cast < FixedVectorType > ( DataTy ) ) { unsigned NumElts = DataVTy -> getNumElements ( ) ; if ( NumElts == 1 ) return false ; if ( ST -> hasAVX512 ( ) && ( NumElts == 2 || ( NumElts == 4 && ! ST -> hasVLX ( ) ) ) ) return false ; } Type * ScalarTy = DataTy -> getScalarType ( ) ; if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == 32 || IntWidth == 64 ; } </s>

Return true if the target supports masked gather .


<s> bool AMDGPUInliner :: runOnSCC ( CallGraphSCC & SCC ) { TTIWP = & getAnalysis < TargetTransformInfoWrapperPass > ( ) ; return LegacyInlinerBase :: runOnSCC ( SCC ) ; } </s>

runOnSCC - This method should be implemented by the subclass to perform whatever action is necessary for the specified SCC .


"parameter passing for argument of type %qT "

"when C++17 is enabled changed to match C++14 "

"with %<[[no_unique_address]]%> members "

"ELFv2 parameter passing for an argument "

"containing zero-width bit fields but that is "

"otherwise a homogeneous aggregate was "

If an argument , whose type is described by TYPE and MODE , is a homogeneous float or vector aggregate that shall be passed in FP/vector registers according to the ELFv2 ABI , return the homogeneous element mode in * ELT_MODE and the number of elements in * N_ELTS , and return TRUE . Otherwise , set * ELT_MODE to MODE and * N_ELTS to 1 , and return FALSE .


<s>
static
void
mmix_option_override
(
void
)
{
if
(
flag_pic
)
{
warning
(
0
,
"%<-f%s%> not supported: ignored"
,
(
flag_pic
>
1
)
"PIC"
:
"pic"
)
;
flag_pic
=
0
;
}
if
(
flag_verbose_asm
||
flag_debug_asm
||
flag_dump_rtl_in_asm
)
{
targetm
.
asm_out
.
byte_op
=
"\t.byte\t"
;
targetm
.
asm_out
.
aligned_op
.
hi
=
"\t.short\t"
;
targetm
.
asm_out
.
aligned_op
.
si
=
"\t.long\t"
;
targetm
.
asm_out
.
aligned_op
.
di
=
"\t.dc.a\t"
;
}
}
</s>


runOnMachineFunction - Emit the function body .


<s> virtual uint64_t getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { return 0 ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> bool ARMBaseInstrInfo :: isReallyTriviallyReMaterializable ( const MachineInstr & MI , AAResults * AA ) const { return isVCTP ( & MI ) && ! isPredicated ( MI ) ; } </s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const override { unsigned NumBytes = 4 ; Value = adjustFixupValue ( Fixup , Value ) ; if ( ! Value ) { return ; } unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { Data [ Offset + i ] |= uint8_t ( ( Value >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static bool nios2_small_section_name_p ( const char * section ) { return ( strcmp ( section , ".sbss" ) == 0 || startswith ( section , ".sbss." ) || strcmp ( section , ".sdata" ) == 0 || startswith ( section , ".sdata." ) || ( nios2_gprel_sec && regexec ( & nios2_gprel_sec_regex , section , 0 , NULL , 0 ) == 0 ) ) ; } </s>

Return true if SECTION is a small section name .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Hexagon RDF optimizations"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
virtual
void
print
(
raw_ostream
&
O
)
const
{
switch
(
Kind
)
{
case
k_Tok
:
O
<<
"Token "
<<
Tok
;
break
;
case
k_Reg
:
O
<<
"Register "
<<
Reg
;
break
;
case
k_Imm
:
O
<<
"Immediate "
<<
*
Imm
;
break
;
case
k_Mem
:
O
<<
"Memory "
;
O
<<
*
Mem
.
Offset
<<
"("
<<
Reg
<<
")"
;
break
;
case
k_IndReg
:
O
<<
"RegInd "
<<
Reg
;
break
;
case
k_PostIndReg
:
O
<<
"PostInc "
<<
Reg
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

MSP430
"Token "
"Register "
"Immediate "
"Memory "
"("
")"
"RegInd "
"PostInc "


"ShadowCallStack attribute not supported on Darwin."

"ShadowCallStack attribute not supported with swifttail"

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool AMDGPUInstrInfo :: isPredicated ( const MachineInstr * MI ) const { return false ; } </s>

Returns true if the instruction is already predicated .


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const X86Subtarget & Subtarget = MF . getSubtarget < X86Subtarget > ( ) ; bool HasSSE = Subtarget . hasSSE1 ( ) ; bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return CSR_64_TLS_Darwin_RegMask ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } CASE_OBF_MASK ( 0 ) CASE_OBF_MASK ( 1 ) CASE_OBF_MASK ( 2 ) CASE_OBF_MASK ( 3 ) CASE_OBF_MASK ( 4 ) CASE_OBF_MASK ( 5 ) CASE_OBF_MASK ( 6 ) CASE_OBF_MASK ( 7 ) CASE_OBF_MASK ( 8 ) CASE_OBF_MASK ( 9 ) case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: X86_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_RegMask : CSR_Win64_RegCall_NoSSE_RegMask ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_RegMask : CSR_SysV64_RegCall_NoSSE_RegMask ) ; } } else { return ( HasSSE ? CSR_32_RegCall_RegMask : CSR_32_RegCall_NoSSE_RegMask ) ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: Win64 : return CSR_Win64_RegMask ; case CallingConv :: X86_64_SysV : return CSR_64_RegMask ; case CallingConv :: X86_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_64_AllRegs_RegMask ; return CSR_64_AllRegs_NoSSE_RegMask ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_32_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_32_AllRegs_SSE_RegMask ; return CSR_32_AllRegs_RegMask ; } default : break ; } if ( Is64Bit ) { const Function & F = MF . getFunction ( ) ; bool IsSwiftCC = Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && F . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ; if ( IsSwiftCC ) return IsWin64 ? CSR_Win64_SwiftError_RegMask : CSR_64_SwiftError_RegMask ; return IsWin64 ? CSR_Win64_RegMask : CSR_64_RegMask ; } return CSR_32_RegMask ; } </s>


<s>
void
X86InstrInfo
::
replaceBranchWithTailCall
(
MachineBasicBlock
&
MBB
,
SmallVectorImpl
<
MachineOperand
>
&
BranchCond
,
const
MachineInstr
&
TailCall
)
const
{
assert
(
canMakeTailCallConditional
(
BranchCond
,
TailCall
)
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
!
I
->
isBranch
(
)
)
assert
(
0
&&
"Can't find the branch to replace!"
)
;
X86
::
CondCode
CC
=
getCondFromBranchOpc
(
I
->
getOpcode
(
)
)
;
assert
(
BranchCond
.
size
(
)
==
1
)
;
if
(
CC
!=
BranchCond
[
0
]
.
getImm
(
)
)
continue
;
break
;
}
unsigned
Opc
=
TailCall
.
getOpcode
(
)
==
X86
::
TCRETURNdi
X86
::
TCRETURNdicc
:
X86
::
TCRETURNdi64cc
;
auto
MIB
=
BuildMI
(
MBB
,
I
,
MBB
.
findDebugLoc
(
I
)
,
get
(
Opc
)
)
;
MIB
->
addOperand
(
TailCall
.
getOperand
(
0
)
)
;
MIB
.
addImm
(
0
)
;
MIB
->
addOperand
(
BranchCond
[
0
]
)
;
MIB
.
copyImplicitOps
(
TailCall
)
;
LivePhysRegs
LiveRegs
(
&
getRegisterInfo
(
)
)
;
LiveRegs
.
addLiveOuts
(
MBB
)
;
SmallVector
<
std
::
pair
<
unsigned
,
const
MachineOperand
*
>
,
8
>
Clobbers
;
LiveRegs
.
stepForward
(
*
MIB
,
Clobbers
)
;
for
(
const
auto
&
C
:
Clobbers
)
{
MIB
.
addReg
(
C
.
first
,
RegState
::
Implicit
)
;
MIB
.
addReg
(
C
.
first
,
RegState
::
Implicit
|
RegState
::
Define
)
;
}
I
->
eraseFromParent
(
)
;
}
</s>

Replace the conditional branch in MBB with a conditional tail call .


<s> static void mips_split_plus ( rtx x , rtx * base_ptr , HOST_WIDE_INT * offset_ptr ) { if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , 1 ) ) ) { * base_ptr = XEXP ( x , 0 ) ; * offset_ptr = INTVAL ( XEXP ( x , 1 ) ) ; } else { * base_ptr = x ; * offset_ptr = 0 ; } } </s>

If X is a PLUS of a CONST_INT , return the two terms in * BASE_PTR and * OFFSET_PTR . Return X in * BASE_PTR and 0 in * OFFSET_PTR otherwise .


<s> void PPCPassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCEarlyReturnPass ( ) , false ) ; addPass ( createPPCBranchSelectionPass ( ) , false ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> Optional < MCFixupKind > M88kMCAsmBackend :: getFixupKind ( StringRef Name ) const { unsigned Type = llvm :: StringSwitch < unsigned > ( Name ) . Default ( - 1u ) ; if ( Type != - 1u ) return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ; return None ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> static int calc_live_regs ( int * count ) { int reg ; int live_regs_mask = 0 ; * count = 0 ; for ( reg = 0 ; reg < FIRST_PSEUDO_REGISTER ; reg ++ ) { if ( regs_ever_live [ reg ] && ! call_used_regs [ reg ] ) { ( * count ) ++ ; live_regs_mask |= ( 1 << reg ) ; } } return live_regs_mask ; } </s>

Work out the registers which need to be saved , both as a mask and a count


<s> static bool visium_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { return ( rclass != MDB || GET_MODE_SIZE ( from ) == GET_MODE_SIZE ( to ) ) ; } </s>

Implement TARGET_CAN_CHANGE_MODE_CLASS . It 's not obvious from the documentation of the hook that MDB can not change mode . However difficulties arise from expressions of the form ( subreg : SI ( reg : DI R_MDB ) 0 ) There is no way to convert that reference to a single machine register and , without the following definition , reload will quietly convert it to ( reg : SI R_MDB ) .


Define the macros that we always expect to have on AArch64 .


<s> static MipsOperand * CreateReg ( unsigned Index , RegKind RegKind , const MCRegisterInfo * RegInfo , SMLoc S , SMLoc E , MipsAsmParser & Parser ) { MipsOperand * Op = new MipsOperand ( k_RegisterIndex , Parser ) ; Op -> RegIdx . Index = Index ; Op -> RegIdx . RegInfo = RegInfo ; Op -> RegIdx . Kind = RegKind ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> void load_got_register ( void ) { if ( ! global_offset_table_rtx ) global_offset_table_rtx = gen_rtx_REG ( Pmode , GLOBAL_OFFSET_TABLE_REGNUM ) ; if ( TARGET_VXWORKS_RTP ) emit_insn ( gen_vxworks_load_got ( ) ) ; else { if ( ! got_helper_rtx ) { char name [ 32 ] ; get_pc_thunk_name ( name , GLOBAL_OFFSET_TABLE_REGNUM ) ; got_helper_rtx = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( name ) ) ; } emit_insn ( gen_load_pcrel_sym ( global_offset_table_rtx , sparc_got ( ) , got_helper_rtx ) ) ; } } </s>


<s> int sparc_initial_elimination_offset ( int to ) { int offset ; if ( to == STACK_POINTER_REGNUM ) offset = sparc_compute_frame_size ( get_frame_size ( ) , crtl -> is_leaf ) ; else offset = 0 ; offset += SPARC_STACK_BIAS ; return offset ; } </s>

Implement the macro INITIAL_ELIMINATION_OFFSET , return the OFFSET .


<s> bool SIAnnotateControlFlow :: isUniform ( BranchInst * T ) { return DA -> isUniform ( T ) || T -> getMetadata ( "structurizecfg.uniform" ) != nullptr ; } </s>

Returns true if value V is uniform across VF lanes , when VF is provided , and otherwise if V is invariant across all loop iterations .


<s> unsigned NyuziInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . getOpcode ( ) == Nyuzi :: LW || MI . getOpcode ( ) == Nyuzi :: BLOCK_LOADI ) { if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


"lowerToVVP called for unexpected SDNode."


<s> bool AArch64TargetLowering :: shouldInsertFencesForAtomic ( const Instruction * I ) const { return isOpSuitableForLDPSTP ( I ) ; } </s>

Helper functions for atomic operations .


<s> static bool load_insn_p ( rtx_insn * insn ) { if ( GET_CODE ( PATTERN ( insn ) ) != SET ) return false ; switch ( get_attr_type ( insn ) ) { case TYPE_LOAD : case TYPE_SLOAD : case TYPE_FPLOAD : return true ; default : return false ; } } </s>


<s>
const
char
*
getPassName
(
)
const
override
{
return
"SystemZ Instruction Shortening"
;
}
</s>

SystemZ
"SystemZ Instruction Shortening"


<s> const char * MSP430TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( MSP430ISD :: NodeType ) Opcode ) { case MSP430ISD :: FIRST_NUMBER : break ; case MSP430ISD :: RET_FLAG : return "MSP430ISD::RET_FLAG" ; case MSP430ISD :: RETI_FLAG : return "MSP430ISD::RETI_FLAG" ; case MSP430ISD :: RRA : return "MSP430ISD::RRA" ; case MSP430ISD :: RLA : return "MSP430ISD::RLA" ; case MSP430ISD :: RRC : return "MSP430ISD::RRC" ; case MSP430ISD :: RRCL : return "MSP430ISD::RRCL" ; case MSP430ISD :: CALL : return "MSP430ISD::CALL" ; case MSP430ISD :: Wrapper : return "MSP430ISD::Wrapper" ; case MSP430ISD :: BR_CC : return "MSP430ISD::BR_CC" ; case MSP430ISD :: CMP : return "MSP430ISD::CMP" ; case MSP430ISD :: SETCC : return "MSP430ISD::SETCC" ; case MSP430ISD :: SELECT_CC : return "MSP430ISD::SELECT_CC" ; case MSP430ISD :: DADD : return "MSP430ISD::DADD" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s>
static
void
nios2_print_operand_address
(
FILE
*
file
,
machine_mode
mode
,
rtx
op
)
{
switch
(
GET_CODE
(
op
)
)
{
case
CONST
:
case
CONST_INT
:
case
LABEL_REF
:
case
CONST_DOUBLE
:
case
SYMBOL_REF
:
if
(
gprel_constant_p
(
op
)
)
{
fprintf
(
file
,
"%%gprel("
)
;
output_addr_const
(
file
,
op
)
;
fprintf
(
file
,
")(%s)"
,
reg_names
[
GP_REGNO
]
)
;
return
;
}
else
if
(
r0rel_constant_p
(
op
)
)
{
if
(
CONST_INT_P
(
op
)
)
{
output_addr_const
(
file
,
op
)
;
fprintf
(
file
,
"(r0)"
)
;
return
;
}
else
{
fprintf
(
file
,
"%%lo("
)
;
output_addr_const
(
file
,
op
)
;
fprintf
(
file
,
")(r0)"
)
;
return
;
}
}
break
;
case
PLUS
:
{
rtx
op0
=
XEXP
(
op
,
0
)
;
rtx
op1
=
XEXP
(
op
,
1
)
;
if
(
REG_P
(
op0
)
&&
CONSTANT_P
(
op1
)
)
{
output_addr_const
(
file
,
op1
)
;
fprintf
(
file
,
"(%s)"
,
reg_names
[
REGNO
(
op0
)
]
)
;
return
;
}
else
if
(
REG_P
(
op1
)
&&
CONSTANT_P
(
op0
)
)
{
output_addr_const
(
file
,
op0
)
;
fprintf
(
file
,
"(%s)"
,
reg_names
[
REGNO
(
op1
)
]
)
;
return
;
}
}
break
;
case
LO_SUM
:
{
rtx
op0
=
XEXP
(
op
,
0
)
;
rtx
op1
=
XEXP
(
op
,
1
)
;
if
(
REG_P
(
op0
)
&&
CONSTANT_P
(
op1
)
)
{
nios2_print_operand
(
file
,
op1
,
'L'
)
;
fprintf
(
file
,
"(%s)"
,
reg_names
[
REGNO
(
op0
)
]
)
;
return
;
}
}
break
;
case
REG
:
fprintf
(
file
,
"0(%s)"
,
reg_names
[
REGNO
(
op
)
]
)
;
return
;
case
MEM
:
{
rtx
base
=
XEXP
(
op
,
0
)
;
nios2_print_operand_address
(
file
,
mode
,
base
)
;
return
;
}
default
:
break
;
}
fprintf
(
stderr
,
"Missing way to print address\n"
)
;
debug_rtx
(
op
)
;
gcc_unreachable
(
)
;
}
</s>


<s> void assignValueToAddress ( Register ValVReg , Register Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { if ( VA . getLocInfo ( ) == CCValAssign :: LocInfo :: AExt ) { Size = VA . getLocVT ( ) . getSizeInBits ( ) / 8 ; ValVReg = MIRBuilder . buildAnyExt ( LLT :: scalar ( Size * 8 ) , ValVReg ) -> getOperand ( 0 ) . getReg ( ) ; } auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , 1 ) ; MIRBuilder . buildStore ( ValVReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> EVT PTXTargetLowering :: getSetCCResultType ( EVT VT ) const { return MVT :: i1 ; } </s>

Return the value type to use for ISD : :SETCC .


<s>
void
HexagonFrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
auto
&
HST
=
static_cast
<
const
HexagonSubtarget
&
>
(
MF
.
getSubtarget
(
)
)
;
auto
&
HRI
=
*
HST
.
getRegisterInfo
(
)
;
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
->
getCalleeSavedInfo
(
)
;
MachineBasicBlock
*
PrologB
=
&
MF
.
front
(
)
,
*
EpilogB
=
nullptr
;
if
(
EnableShrinkWrapping
)
findShrunkPrologEpilog
(
MF
,
PrologB
,
EpilogB
)
;
insertCSRSpillsInBlock
(
*
PrologB
,
CSI
,
HRI
)
;
insertPrologueInBlock
(
*
PrologB
)
;
if
(
EpilogB
)
{
insertCSRRestoresInBlock
(
*
EpilogB
,
CSI
,
HRI
)
;
insertEpilogueInBlock
(
*
EpilogB
)
;
}
else
{
for
(
auto
&
B
:
MF
)
if
(
!
B
.
empty
(
)
&&
B
.
back
(
)
.
isReturn
(
)
)
insertCSRRestoresInBlock
(
B
,
CSI
,
HRI
)
;
for
(
auto
&
B
:
MF
)
if
(
!
B
.
empty
(
)
&&
B
.
back
(
)
.
isReturn
(
)
)
insertEpilogueInBlock
(
B
)
;
}
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Hexagon
Hexagon
Hexagon
"Shrink-wrapping not yet supported"


<s> static tree tilepro_build_builtin_va_list ( void ) { tree f_args , f_skip , record , type_decl ; bool owp ; record = lang_hooks . types . make_type ( RECORD_TYPE ) ; type_decl = build_decl ( BUILTINS_LOCATION , TYPE_DECL , get_identifier ( "__va_list_tag" ) , record ) ; f_args = build_decl ( BUILTINS_LOCATION , FIELD_DECL , get_identifier ( "__args" ) , ptr_type_node ) ; f_skip = build_decl ( BUILTINS_LOCATION , FIELD_DECL , get_identifier ( "__skip" ) , ptr_type_node ) ; DECL_FIELD_CONTEXT ( f_args ) = record ; DECL_FIELD_CONTEXT ( f_skip ) = record ; TREE_CHAIN ( record ) = type_decl ; TYPE_NAME ( record ) = type_decl ; TYPE_FIELDS ( record ) = f_args ; TREE_CHAIN ( f_args ) = f_skip ; owp = warn_padded ; warn_padded = false ; layout_type ( record ) ; warn_padded = owp ; return record ; } </s>


<s> bool SPIRVModuleAnalysis :: runOnModule ( Module & M ) { SPIRVTargetMachine & TM = getAnalysis < TargetPassConfig > ( ) . getTM < SPIRVTargetMachine > ( ) ; ST = TM . getSubtargetImpl ( ) ; GR = ST -> getSPIRVGlobalRegistry ( ) ; TII = ST -> getInstrInfo ( ) ; MMI = & getAnalysis < MachineModuleInfoWrapperPass > ( ) . getMMI ( ) ; setBaseInfo ( M ) ; collectReqs ( M , MAI , MMI , * ST ) ; processSwitches ( M , MAI , MMI ) ; processDefInstrs ( M ) ; numberRegistersGlobally ( M ) ; processOtherInstrs ( M ) ; if ( MAI . MS [ SPIRV :: MB_EntryPoints ] . empty ( ) ) MAI . Reqs . addCapability ( Capability :: Linkage ) ; return false ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .

SPIRV SPIRV SPIRV SPIRV SPIRV SPIRV::MB_EntryPoints


<s>
SDValue
AMDGPUTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
Op
.
getNode
(
)
->
dump
(
)
;
assert
(
0
&&
"Custom lowering code for this"
"instruction is not implemented yet!"
)
;
break
;
case
ISD
::
SDIV
:
return
LowerSDIV
(
Op
,
DAG
)
;
case
ISD
::
SREM
:
return
LowerSREM
(
Op
,
DAG
)
;
case
ISD
::
SIGN_EXTEND_INREG
:
return
LowerSIGN_EXTEND_INREG
(
Op
,
DAG
)
;
case
ISD
::
BRCOND
:
return
LowerBRCOND
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
UDIVREM
:
return
LowerUDIVREM
(
Op
,
DAG
)
;
}
return
Op
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

R600
0
"Custom lowering code for this"
"instruction is not implemented yet!"
ISD::SDIV
ISD::SREM
ISD::SIGN_EXTEND_INREG
SI
ISD::BRCOND
ISD::INTRINSIC_WO_CHAIN
SI
ISD::UDIVREM


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s>
bool
ARMAsmPrinter
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
{
switch
(
MO
.
getType
(
)
)
{
default
:
assert
(
0
&&
"unknown operand type"
)
;
return
false
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
&&
MO
.
getReg
(
)
!=
ARM
::
CPSR
)
return
false
;
assert
(
!
MO
.
getSubReg
(
)
&&
"Subregs should be eliminated!"
)
;
MCOp
=
MCOperand
::
CreateReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
CreateImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
CreateExpr
(
MCSymbolRefExpr
::
Create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
OutContext
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
GetSymbolRef
(
MO
,
Mang
->
getSymbol
(
MO
.
getGlobal
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
GetSymbolRef
(
MO
,
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
MCOp
=
GetSymbolRef
(
MO
,
GetJTISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
MCOp
=
GetSymbolRef
(
MO
,
GetCPISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_BlockAddress
:
MCOp
=
GetSymbolRef
(
MO
,
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
)
;
break
;
case
MachineOperand
::
MO_FPImmediate
:
{
APFloat
Val
=
MO
.
getFPImm
(
)
->
getValueAPF
(
)
;
bool
ignored
;
Val
.
convert
(
APFloat
::
IEEEdouble
,
APFloat
::
rmTowardZero
,
&
ignored
)
;
MCOp
=
MCOperand
::
CreateFPImm
(
Val
.
convertToDouble
(
)
)
;
break
;
}
}
return
true
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .

ARM
ARM
0
"unknown operand type"
ARM::CPSR
"Subregs should be eliminated!"


<s> virtual MachineInstr * foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const { return 0 ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> static bool mcore_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( TARGET_8ALIGN && GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) return ( regno & 1 ) == 0 ; return regno < 18 ; } </s>

Implement TARGET_HARD_REGNO_MODE_OK . We may keep double values in even registers .


<s> void PPCSubtarget :: overrideSchedPolicy ( MachineSchedPolicy & Policy , MachineInstr * begin , MachineInstr * end , unsigned NumRegionInstrs ) const { if ( needsAggressiveScheduling ( DarwinDirective ) ) { Policy . OnlyTopDown = false ; Policy . OnlyBottomUp = false ; } Policy . ShouldTrackPressure = true ; } </s>

Override generic scheduling policy within a region .


<s> bool RISCVTargetLowering :: isLegalAddImmediate ( int64_t Imm ) const { return isInt < 12 > ( Imm ) ; } </s>

Return true if the specified immediate is legal add immediate , that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register .


"ignoring %<-fschedule-insns%> because of exception "

"unwind tables currently require either a frame pointer "

"or %<-maccumulate-outgoing-args%> for correctness"

Implement TARGET_OPTION_OVERRIDE macro . Validate and override various options , and do some machine dependent initialization .


<s> static bool ix86_scalar_mode_supported_p ( machine_mode mode ) { if ( DECIMAL_FLOAT_MODE_P ( mode ) ) return default_decimal_float_supported_p ( ) ; else if ( mode == TFmode ) return true ; else return default_scalar_mode_supported_p ( mode ) ; } </s>

Target hook for scalar_mode_supported_p .


<s> void setType ( nodeType value ) { type . setNodeType ( value ) ; } </s>


"Relocation required in an instruction that we cannot encode!"

getMachineOpValue - Return binary encoding of operand .


<s> void scalar_chain :: replace_with_subreg_in_insn ( rtx_insn * insn , rtx reg , rtx new_reg ) { replace_with_subreg ( single_set ( insn ) , reg , new_reg ) ; } </s>

Replace REG in INSN with a V2DI subreg of NEW_REG .


<s> const HexagonTargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


<s> BitVector GBZ80RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( GB :: SP ) ; Reserved . set ( GB :: IME ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool PPCFastISel :: isTypeLegal ( Type * Ty , MVT & VT ) { EVT Evt = TLI . getValueType ( DL , Ty , true ) ; if ( Evt == MVT :: Other || ! Evt . isSimple ( ) ) return false ; VT = Evt . getSimpleVT ( ) ; return TLI . isTypeLegal ( VT ) ; } </s>


<s> bool ARMFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( STI . isTargetIOS ( ) ) return true ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) && MFI -> hasCalls ( ) ) || RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool X86PartialReduction :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; auto & TM = TPC -> getTM < X86TargetMachine > ( ) ; ST = TM . getSubtargetImpl ( F ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; bool MadeChange = false ; for ( auto & BB : F ) { for ( auto & I : BB ) { auto * BO = dyn_cast < BinaryOperator > ( & I ) ; if ( ! BO ) continue ; if ( ! isVectorReductionOp ( * BO ) ) continue ; if ( BO -> getOpcode ( ) == Instruction :: Add ) { if ( tryMAddPattern ( BO ) ) { MadeChange = true ; continue ; } if ( trySADPattern ( BO ) ) { MadeChange = true ; continue ; } } } } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static void nios2_output_dwarf_dtprel ( FILE * file , int size , rtx x ) { gcc_assert ( size == 4 ) ; fprintf ( file , "\t.4byte\t%%tls_ldo(" ) ; output_addr_const ( file , x ) ; fprintf ( file , ")" ) ; } </s>


<s>
SUnit
*
SystemZPostRASchedStrategy
::
pickNode
(
bool
&
IsTopNode
)
{
IsTopNode
=
true
;
if
(
Available
.
empty
(
)
)
return
nullptr
;
if
(
Available
.
size
(
)
==
1
)
{
DEBUG
(
dbgs
(
)
<<
"** Only one: "
;
HazardRec
->
dumpSU
(
*
Available
.
begin
(
)
,
dbgs
(
)
)
;
dbgs
(
)
<<
"\n"
;
)
;
return
*
Available
.
begin
(
)
;
}
DEBUG
(
dbgs
(
)
<<
"** Available: "
;
Available
.
dump
(
*
HazardRec
)
;
)
;
Candidate
Best
;
for
(
auto
*
SU
:
Available
)
{
Candidate
c
(
SU
,
*
HazardRec
)
;
if
(
Best
.
SU
==
nullptr
||
c
<
Best
)
{
Best
=
c
;
DEBUG
(
dbgs
(
)
<<
"** Best so far: "
;
)
;
}
else
DEBUG
(
dbgs
(
)
<<
"** Tried      : "
;
)
;
DEBUG
(
HazardRec
->
dumpSU
(
c
.
SU
,
dbgs
(
)
)
;
c
.
dumpCosts
(
)
;
dbgs
(
)
<<
" Height:"
<<
c
.
SU
->
getHeight
(
)
;
dbgs
(
)
<<
"\n"
;
)
;
if
(
!
SU
->
isScheduleHigh
&&
Best
.
noCost
(
)
)
break
;
}
assert
(
Best
.
SU
!=
nullptr
)
;
return
Best
.
SU
;
}
</s>

Pick the next node to schedule , or return NULL .

SystemZ
SystemZ
1
"** Only one: "
"\n"
"** Available: "
"** Best so far: "
"** Tried      : "
" Height:"
"\n"


<s> rtx sh_movrt_set_dest ( const rtx_insn * i ) { if ( i == NULL ) return NULL ; const_rtx p = PATTERN ( i ) ; if ( GET_CODE ( p ) == PARALLEL ) p = XVECEXP ( p , 0 , 0 ) ; return GET_CODE ( p ) == SET && arith_reg_dest ( XEXP ( p , 0 ) , SImode ) && negt_reg_operand ( XEXP ( p , 1 ) , VOIDmode ) ? XEXP ( p , 0 ) : NULL ; } </s>

Given an insn , check whether it 's a 'movrt ' kind of insn , i.e . an insn that stores the negated T bit in a register , and return the destination register rtx , or null .


<s> unsigned AMDGPUTTIImpl :: getNumberOfRegisters ( bool Vec ) { if ( Vec ) return 0 ; if ( ST -> getGeneration ( ) >= AMDGPUSubtarget :: SOUTHERN_ISLANDS ) return 256 ; return 4 * 128 ; } </s>


<s> EVT HexagonTargetLowering :: getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const { if ( Op . size ( ) >= 8 && Op . isAligned ( Align ( 8 ) ) ) return MVT :: i64 ; if ( Op . size ( ) >= 4 && Op . isAligned ( Align ( 4 ) ) ) return MVT :: i32 ; if ( Op . size ( ) >= 2 && Op . isAligned ( Align ( 2 ) ) ) return MVT :: i16 ; return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


"********** Lower RefTypes IntPtr Convs **********\n"


<s> bool X86FastISel :: isTypeLegal ( Type * Ty , MVT & VT , bool AllowI1 ) { EVT evt = TLI . getValueType ( DL , Ty , true ) ; if ( evt == MVT :: Other || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; if ( VT == MVT :: f64 && ! Subtarget -> hasSSE2 ( ) ) return false ; if ( VT == MVT :: f32 && ! Subtarget -> hasSSE1 ( ) ) return false ; if ( VT == MVT :: f80 ) return false ; return ( AllowI1 && VT == MVT :: i1 ) || TLI . isTypeLegal ( VT ) ; } </s>


<s> static char * read_file ( const char * filename , size_t * plen ) { size_t alloc = 16384 ; size_t base = 0 ; char * buffer ; FILE * stream = fopen ( filename , "rb" ) ; if ( ! stream ) { perror ( filename ) ; exit ( 1 ) ; } if ( ! fseek ( stream , 0 , SEEK_END ) ) { long s = ftell ( stream ) ; if ( s >= 0 ) alloc = s + 100 ; fseek ( stream , 0 , SEEK_SET ) ; } buffer = malloc ( alloc ) ; for ( ; ; ) { size_t n = fread ( buffer + base , 1 , alloc - base - 1 , stream ) ; if ( ! n ) break ; base += n ; if ( base + 1 == alloc ) { alloc *= 2 ; buffer = realloc ( buffer , alloc ) ; } } buffer [ base ] = 0 ; * plen = base ; fclose ( stream ) ; return buffer ; } </s>

Read the whole input file . It will be NUL terminated ( but remember , there could be a NUL in the file itself .


<s> SDNode * Tile64DAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = TM . getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI . getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"AdvSIMD Scalar Operation Optimization"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool AlphaAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { printOperand ( MI , OpNo ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static int s390_vec_n_elem ( tree fndecl ) { tree b_arg_chain ; int n_elem = - 1 ; if ( TREE_CODE ( TREE_TYPE ( TREE_TYPE ( fndecl ) ) ) == VECTOR_TYPE ) n_elem = TYPE_VECTOR_SUBPARTS ( TREE_TYPE ( TREE_TYPE ( ( fndecl ) ) ) ) ; for ( b_arg_chain = TYPE_ARG_TYPES ( TREE_TYPE ( fndecl ) ) ; ! VOID_TYPE_P ( TREE_VALUE ( b_arg_chain ) ) ; b_arg_chain = TREE_CHAIN ( b_arg_chain ) ) { int tmp_n_elem ; if ( TREE_CODE ( TREE_VALUE ( b_arg_chain ) ) != VECTOR_TYPE ) continue ; tmp_n_elem = TYPE_VECTOR_SUBPARTS ( TREE_VALUE ( b_arg_chain ) ) ; if ( n_elem != - 1 && n_elem != tmp_n_elem ) return - 1 ; n_elem = tmp_n_elem ; } return n_elem ; } </s>

Return the number of elements in the vector arguments of FNDECL in case all it matches for all vector arguments , -1 otherwise .


<s> int ix86_frame_pointer_required ( void ) { if ( cfun -> machine -> accesses_prev_frame ) return 1 ; if ( SUBTARGET_FRAME_POINTER_REQUIRED ) return 1 ; if ( TARGET_OMIT_LEAF_FRAME_POINTER && ( ! current_function_is_leaf ) ) return 1 ; if ( current_function_profile ) return 1 ; return 0 ; } </s>

Value should be nonzero if functions must have frame pointers . Zero means the frame pointer need not be set up ( and parms may be accessed via the stack pointer ) in functions that seem suitable .


<s> bool ARMTargetLowering :: isShuffleMaskLegal ( ArrayRef < int > M , EVT VT ) const { if ( VT . getVectorNumElements ( ) == 4 && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ 4 ] ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { if ( M [ i ] < 0 ) PFIndexes [ i ] = 8 ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ 0 ] * 9 * 9 * 9 + PFIndexes [ 1 ] * 9 * 9 + PFIndexes [ 2 ] * 9 + PFIndexes [ 3 ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> 30 ) ; if ( Cost <= 4 && ( Subtarget -> hasNEON ( ) || isLegalMVEShuffleOp ( PFEntry ) ) ) return true ; } bool ReverseVEXT , isV_UNDEF ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; if ( EltSize >= 32 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || ShuffleVectorInst :: isIdentityMask ( M ) || isVREVMask ( M , VT , 64 ) || isVREVMask ( M , VT , 32 ) || isVREVMask ( M , VT , 16 ) ) return true ; else if ( Subtarget -> hasNEON ( ) && ( isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTBLMask ( M , VT ) || isNEONTwoResultShuffleMask ( M , VT , WhichResult , isV_UNDEF ) ) ) return true ; else if ( ( VT == MVT :: v8i16 || VT == MVT :: v8f16 || VT == MVT :: v16i8 ) && isReverseMask ( M , VT ) ) return true ; else if ( Subtarget -> hasMVEIntegerOps ( ) && ( isVMOVNMask ( M , VT , true , false ) || isVMOVNMask ( M , VT , false , false ) || isVMOVNMask ( M , VT , true , true ) ) ) return true ; else return false ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s>
uint32_t
AMDGPUTargetLowering
::
getImplicitParameterOffset
(
const
MachineFunction
&
MF
,
const
ImplicitParameter
Param
)
const
{
const
AMDGPUMachineFunction
*
MFI
=
MF
.
getInfo
<
AMDGPUMachineFunction
>
(
)
;
const
AMDGPUSubtarget
&
ST
=
AMDGPUSubtarget
::
get
(
getTargetMachine
(
)
,
MF
.
getFunction
(
)
)
;
unsigned
ExplicitArgOffset
=
ST
.
getExplicitKernelArgOffset
(
MF
.
getFunction
(
)
)
;
const
Align
Alignment
=
ST
.
getAlignmentForImplicitArgPtr
(
)
;
uint64_t
ArgOffset
=
alignTo
(
MFI
->
getExplicitKernArgSize
(
)
,
Alignment
)
+
ExplicitArgOffset
;
switch
(
Param
)
{
case
FIRST_IMPLICIT
:
return
ArgOffset
;
case
PRIVATE_BASE
:
return
ArgOffset
+
AMDGPU
::
ImplicitArg
::
PRIVATE_BASE_OFFSET
;
case
SHARED_BASE
:
return
ArgOffset
+
AMDGPU
::
ImplicitArg
::
SHARED_BASE_OFFSET
;
case
QUEUE_PTR
:
return
ArgOffset
+
AMDGPU
::
ImplicitArg
::
QUEUE_PTR_OFFSET
;
}
llvm_unreachable
(
"unexpected implicit parameter type"
)
;
}
</s>

Helper function that returns the byte offset of the given type of implicit parameter .

AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU::ImplicitArg
AMDGPU::ImplicitArg
AMDGPU::ImplicitArg
"unexpected implicit parameter type"


<s> bool runOnFunction ( Function & F ) override { X86LowerAMXType LAT ( F ) ; bool C = LAT . visit ( ) ; return C ; } </s>


<s> char * aarch64_output_sve_scalar_inc_dec ( rtx offset ) { poly_int64 offset_value = rtx_to_poly_int64 ( offset ) ; gcc_assert ( offset_value . coeffs [ 0 ] == offset_value . coeffs [ 1 ] ) ; if ( offset_value . coeffs [ 1 ] > 0 ) return aarch64_output_sve_cnt_immediate ( "inc" , "%x0" , AARCH64_SV_ALL , offset_value . coeffs [ 1 ] , 0 ) ; else return aarch64_output_sve_cnt_immediate ( "dec" , "%x0" , AARCH64_SV_ALL , - offset_value . coeffs [ 1 ] , 0 ) ; } </s>

Return the asm string for adding SVE INC/DEC immediate OFFSET to operand 0 .


runOnMachineFunction - Emit the function body .


<s> ScheduleHazardRecognizer :: HazardType GCNHazardRecognizer :: getHazardType ( SUnit * SU , int Stalls ) { MachineInstr * MI = SU -> getInstr ( ) ; auto HazardType = IsHazardRecognizerMode ? NoopHazard : Hazard ; if ( MI -> isBundle ( ) ) return NoHazard ; if ( SIInstrInfo :: isSMRD ( * MI ) && checkSMRDHazards ( MI ) > 0 ) return HazardType ; if ( ( SIInstrInfo :: isVMEM ( * MI ) || SIInstrInfo :: isFLAT ( * MI ) ) && checkVMEMHazards ( MI ) > 0 ) return HazardType ; if ( ST . hasNSAtoVMEMBug ( ) && checkNSAtoVMEMHazard ( MI ) > 0 ) return HazardType ; if ( checkFPAtomicToDenormModeHazard ( MI ) > 0 ) return HazardType ; if ( ST . hasNoDataDepHazard ( ) ) return NoHazard ; if ( SIInstrInfo :: isVALU ( * MI ) && checkVALUHazards ( MI ) > 0 ) return HazardType ; if ( SIInstrInfo :: isDPP ( * MI ) && checkDPPHazards ( MI ) > 0 ) return HazardType ; if ( isDivFMas ( MI -> getOpcode ( ) ) && checkDivFMasHazards ( MI ) > 0 ) return HazardType ; if ( isRWLane ( MI -> getOpcode ( ) ) && checkRWLaneHazards ( MI ) > 0 ) return HazardType ; if ( isSGetReg ( MI -> getOpcode ( ) ) && checkGetRegHazards ( MI ) > 0 ) return HazardType ; if ( isSSetReg ( MI -> getOpcode ( ) ) && checkSetRegHazards ( MI ) > 0 ) return HazardType ; if ( isRFE ( MI -> getOpcode ( ) ) && checkRFEHazards ( MI ) > 0 ) return HazardType ; if ( ST . hasReadM0MovRelInterpHazard ( ) && ( TII . isVINTRP ( * MI ) || isSMovRel ( MI -> getOpcode ( ) ) ) && checkReadM0Hazards ( MI ) > 0 ) return HazardType ; if ( ST . hasReadM0SendMsgHazard ( ) && isSendMsgTraceDataOrGDS ( TII , * MI ) && checkReadM0Hazards ( MI ) > 0 ) return HazardType ; if ( SIInstrInfo :: isMAI ( * MI ) && checkMAIHazards ( MI ) > 0 ) return HazardType ; if ( ( SIInstrInfo :: isVMEM ( * MI ) || SIInstrInfo :: isFLAT ( * MI ) || SIInstrInfo :: isDS ( * MI ) ) && checkMAILdStHazards ( MI ) > 0 ) return HazardType ; if ( MI -> isInlineAsm ( ) && checkInlineAsmHazards ( MI ) > 0 ) return HazardType ; return NoHazard ; } </s>

getHazardType - Return the hazard type of emitting this node .


Returns true if the current MCU does not have a hardware multiplier of any kind .


<s> void setSymbolSize ( const MCSymbol * Symbol , uint64_t Size ) override { } </s>

For symbols that have a size designated ( e.g .


<s> static inline int choose_baseaddr_len ( unsigned int regno , HOST_WIDE_INT offset ) { int len = 4 ; if ( offset == 0 ) { len = ( regno == BP_REG || regno == R13_REG ) ; } else if ( IN_RANGE ( offset , - 128 , 127 ) ) len = 1 ; if ( regno == SP_REG || regno == R12_REG ) len ++ ; return len ; } </s>

This is semi-inlined memory_address_length , but simplified since we know that we 're always dealing with reg+offset , and to avoid having to create and discard all that rtl .


<s>
SDValue
AMDGPUTargetLowering
::
combineFMinMaxLegacy
(
const
SDLoc
&
DL
,
EVT
VT
,
SDValue
LHS
,
SDValue
RHS
,
SDValue
True
,
SDValue
False
,
SDValue
CC
,
DAGCombinerInfo
&
DCI
)
const
{
if
(
!
(
LHS
==
True
&&
RHS
==
False
)
&&
!
(
LHS
==
False
&&
RHS
==
True
)
)
return
SDValue
(
)
;
SelectionDAG
&
DAG
=
DCI
.
DAG
;
ISD
::
CondCode
CCOpcode
=
cast
<
CondCodeSDNode
>
(
CC
)
->
get
(
)
;
switch
(
CCOpcode
)
{
case
ISD
::
SETOEQ
:
case
ISD
::
SETONE
:
case
ISD
::
SETUNE
:
case
ISD
::
SETNE
:
case
ISD
::
SETUEQ
:
case
ISD
::
SETEQ
:
case
ISD
::
SETFALSE
:
case
ISD
::
SETFALSE2
:
case
ISD
::
SETTRUE
:
case
ISD
::
SETTRUE2
:
case
ISD
::
SETUO
:
case
ISD
::
SETO
:
break
;
case
ISD
::
SETULE
:
case
ISD
::
SETULT
:
{
if
(
LHS
==
True
)
return
DAG
.
getNode
(
AMDGPUISD
::
FMIN_LEGACY
,
DL
,
VT
,
RHS
,
LHS
)
;
return
DAG
.
getNode
(
AMDGPUISD
::
FMAX_LEGACY
,
DL
,
VT
,
LHS
,
RHS
)
;
}
case
ISD
::
SETOLE
:
case
ISD
::
SETOLT
:
case
ISD
::
SETLE
:
case
ISD
::
SETLT
:
{
if
(
DCI
.
getDAGCombineLevel
(
)
<
AfterLegalizeDAG
&&
!
DCI
.
isCalledByLegalizer
(
)
)
return
SDValue
(
)
;
if
(
LHS
==
True
)
return
DAG
.
getNode
(
AMDGPUISD
::
FMIN_LEGACY
,
DL
,
VT
,
LHS
,
RHS
)
;
return
DAG
.
getNode
(
AMDGPUISD
::
FMAX_LEGACY
,
DL
,
VT
,
RHS
,
LHS
)
;
}
case
ISD
::
SETUGE
:
case
ISD
::
SETUGT
:
{
if
(
LHS
==
True
)
return
DAG
.
getNode
(
AMDGPUISD
::
FMAX_LEGACY
,
DL
,
VT
,
RHS
,
LHS
)
;
return
DAG
.
getNode
(
AMDGPUISD
::
FMIN_LEGACY
,
DL
,
VT
,
LHS
,
RHS
)
;
}
case
ISD
::
SETGT
:
case
ISD
::
SETGE
:
case
ISD
::
SETOGE
:
case
ISD
::
SETOGT
:
{
if
(
DCI
.
getDAGCombineLevel
(
)
<
AfterLegalizeDAG
&&
!
DCI
.
isCalledByLegalizer
(
)
)
return
SDValue
(
)
;
if
(
LHS
==
True
)
return
DAG
.
getNode
(
AMDGPUISD
::
FMAX_LEGACY
,
DL
,
VT
,
LHS
,
RHS
)
;
return
DAG
.
getNode
(
AMDGPUISD
::
FMIN_LEGACY
,
DL
,
VT
,
RHS
,
LHS
)
;
}
case
ISD
::
SETCC_INVALID
:
llvm_unreachable
(
"Invalid setcc condcode!"
)
;
}
return
SDValue
(
)
;
}
</s>

AMDGPU
AMDGPU
ISD::CondCode
ISD::SETOEQ
ISD::SETONE
ISD::SETUNE
ISD::SETNE
ISD::SETUEQ
ISD::SETEQ
ISD::SETFALSE
ISD::SETFALSE2
ISD::SETTRUE
ISD::SETTRUE2
ISD::SETUO
ISD::SETO
ISD::SETULE
ISD::SETULT
AMDGPUISD::FMIN_LEGACY
AMDGPUISD::FMAX_LEGACY
ISD::SETOLE
ISD::SETOLT
ISD::SETLE
ISD::SETLT
AMDGPUISD::FMIN_LEGACY
AMDGPUISD::FMAX_LEGACY
ISD::SETUGE
ISD::SETUGT
AMDGPUISD::FMAX_LEGACY
AMDGPUISD::FMIN_LEGACY
ISD::SETGT
ISD::SETGE
ISD::SETOGE
ISD::SETOGT
AMDGPUISD::FMAX_LEGACY
AMDGPUISD::FMIN_LEGACY
ISD::SETCC_INVALID
"Invalid setcc condcode!"


<s> int vms_c_get_crtl_ver ( void ) { return VMS_DEFAULT_CRTL_VER ; } </s>


<s> bool GBZ80PreRA :: runOnMachineFunction ( MachineFunction & MF ) { bool Modified = false ; this -> MF = & MF ; const GBZ80Subtarget & STI = MF . getSubtarget < GBZ80Subtarget > ( ) ; TRI = STI . getRegisterInfo ( ) ; TII = STI . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; DT = & getAnalysis < MachineDominatorTree > ( ) ; Modified |= combinePostIncMemAccs ( ) ; if ( WidenRegClasses ) Modified |= widenConstrainedRegClasses ( ) ; return Modified ; } </s>


"Encountered a global variable kind that is "

Emit the specified global variable to the .s file .


<s> static section * arm_function_section ( tree decl , enum node_frequency freq , bool startup , bool exit ) { const char * section_name ; section * sec ; if ( ! decl || TREE_CODE ( decl ) != FUNCTION_DECL ) return default_function_section ( decl , freq , startup , exit ) ; if ( ! target_pure_code ) return default_function_section ( decl , freq , startup , exit ) ; section_name = DECL_SECTION_NAME ( decl ) ; if ( ! section_name ) { section * default_sec = default_function_section ( decl , freq , startup , exit ) ; if ( default_sec ) default_sec -> common . flags |= SECTION_ARM_PURECODE ; return default_sec ; } sec = get_named_section ( decl , section_name , 0 ) ; if ( ! sec ) sec = get_named_section ( decl , NULL , 0 ) ; sec -> common . flags |= SECTION_ARM_PURECODE ; return sec ; } </s>

Implement the TARGET_ASM_FUNCTION_SECTION hook . If pure-code is passed as an option , make sure all functions are in sections that have the SHF_ARM_PURECODE attribute .


<s> static void ft32_compute_frame ( void ) { int stack_alignment = STACK_BOUNDARY / BITS_PER_UNIT ; int padding_locals ; int regno ; cfun -> machine -> local_vars_size = get_frame_size ( ) ; padding_locals = cfun -> machine -> local_vars_size % stack_alignment ; if ( padding_locals ) padding_locals = stack_alignment - padding_locals ; cfun -> machine -> local_vars_size += padding_locals ; cfun -> machine -> callee_saved_reg_size = 0 ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) ) cfun -> machine -> callee_saved_reg_size += 4 ; cfun -> machine -> size_for_adjusting_sp = 0 + cfun -> machine -> local_vars_size + ( ACCUMULATE_OUTGOING_ARGS ? ( HOST_WIDE_INT ) crtl -> outgoing_args_size : 0 ) ; } </s>

Compute the size of the local area and the size to be adjusted by the * prologue and epilogue .


<s> bool MSP430AsmPrinter :: doInitialization ( Module & M ) { Mang = new Mangler ( M , "" , TAI -> getPrivateGlobalPrefix ( ) ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> static bool s390_can_change_mode_class ( machine_mode from_mode , machine_mode to_mode , reg_class_t rclass ) { machine_mode small_mode ; machine_mode big_mode ; if ( reg_classes_intersect_p ( VEC_REGS , rclass ) && ( ( s390_is_fpr128 ( from_mode ) && s390_is_vr128 ( to_mode ) ) || ( s390_is_vr128 ( from_mode ) && s390_is_fpr128 ( to_mode ) ) ) ) return false ; if ( GET_MODE_SIZE ( from_mode ) == GET_MODE_SIZE ( to_mode ) ) return true ; if ( GET_MODE_SIZE ( from_mode ) < GET_MODE_SIZE ( to_mode ) ) { small_mode = from_mode ; big_mode = to_mode ; } else { small_mode = to_mode ; big_mode = from_mode ; } if ( reg_classes_intersect_p ( VEC_REGS , rclass ) && ( GET_MODE_SIZE ( small_mode ) < 8 || s390_class_max_nregs ( VEC_REGS , big_mode ) == 1 ) ) return false ; if ( reg_classes_intersect_p ( ACCESS_REGS , rclass ) ) return false ; return true ; } </s>


<s> void SystemZHazardRecognizer :: copyState ( SystemZHazardRecognizer * Incoming ) { CurrGroupSize = Incoming -> CurrGroupSize ; DEBUG ( CurGroupDbg = Incoming -> CurGroupDbg ; ) ; ProcResourceCounters = Incoming -> ProcResourceCounters ; CriticalResourceIdx = Incoming -> CriticalResourceIdx ; LastFPdOpCycleIdx = Incoming -> LastFPdOpCycleIdx ; GrpCount = Incoming -> GrpCount ; } </s>

Copy counters from end of single predecessor .


<s> static rtx xtensa_function_arg ( cumulative_args_t cum , const function_arg_info & arg ) { return xtensa_function_arg_1 ( cum , arg , false ) ; } </s>


<s> int PPCRegisterInfo :: getDwarfRegNum ( unsigned RegNum , bool isEH ) const { return PPCGenRegisterInfo :: getDwarfRegNumFull ( RegNum , 0 ) ; } </s>

Map a target register to an equivalent dwarf register number .


"Instr doesn't have FrameIndex operand!"

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s> unsigned HexagonInstrInfo :: getInstrLatency ( const InstrItineraryData * ItinData , const MachineInstr & MI , unsigned * PredCost ) const { return getInstrTimingClassLatency ( ItinData , & MI ) ; } </s>

Compute the instruction latency of a given instruction .


<s>
void
pa_asm_output_aligned_local
(
FILE
*
stream
,
const
char
*
name
,
unsigned
HOST_WIDE_INT
size
,
unsigned
int
align
)
{
switch_to_section
(
bss_section
)
;
fprintf
(
stream
,
"\t.align %u\n"
,
align
/
BITS_PER_UNIT
)
;
fprintf
(
stream
,
"%s"
,
LOCAL_ASM_OP
)
;
assemble_name
(
stream
,
name
)
;
fprintf
(
stream
,
"\n"
)
;
ASM_OUTPUT_LABEL
(
stream
,
name
)
;
fprintf
(
stream
,
"\t.block "
HOST_WIDE_INT_PRINT_UNSIGNED
"\n"
,
size
)
;
}
</s>

We ca n't use .comm for local common storage as the SOM linker effectively treats the symbol as universal and uses the same storage for local symbols with the same name in different object files . The .block directive reserves an uninitialized block of storage . However , it 's not common storage . Fortunately , GCC never requests common storage with the same name in any given translation unit .

pa
"\t.align %u\n"
"%s"
"\n"
"\t.block "
"\n"


<s> static bool find_mem_ref ( rtx pat , rtx * mem_ref ) { const char * fmt ; int i , j ; if ( tie_operand ( pat , VOIDmode ) ) return false ; if ( GET_CODE ( pat ) == MEM ) { * mem_ref = pat ; return true ; } fmt = GET_RTX_FORMAT ( GET_CODE ( pat ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( pat ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'e' ) { if ( find_mem_ref ( XEXP ( pat , i ) , mem_ref ) ) return true ; } else if ( fmt [ i ] == 'E' ) for ( j = XVECLEN ( pat , i ) - 1 ; j >= 0 ; j -- ) { if ( find_mem_ref ( XVECEXP ( pat , i , j ) , mem_ref ) ) return true ; } } return false ; } </s>

Determine if PAT refers to memory . If so , set MEM_REF to the MEM rtx and return true .


Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU R600 AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU


<s> static bool nds32_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( ( GET_MODE_CLASS ( mode1 ) == MODE_INT && GET_MODE_CLASS ( mode2 ) == MODE_INT ) && GET_MODE_SIZE ( mode1 ) <= UNITS_PER_WORD && GET_MODE_SIZE ( mode2 ) <= UNITS_PER_WORD ) return true ; if ( GET_MODE_SIZE ( mode1 ) == GET_MODE_SIZE ( mode2 ) ) { if ( ( TARGET_FPU_SINGLE && ! TARGET_FPU_DOUBLE ) && ( mode1 == DFmode || mode2 == DFmode ) ) return false ; else return true ; } return false ; } </s>

Implement TARGET_MODES_TIEABLE_P . We can use general registers to tie QI/HI/SI modes together .


<s>
void
SystemZHazardRecognizer
::
EmitInstruction
(
SUnit
*
SU
)
{
const
MCSchedClassDesc
*
SC
=
getSchedClass
(
SU
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"++ HazardRecognizer emitting "
;
dumpSU
(
SU
,
dbgs
(
)
)
;
dbgs
(
)
<<
"\n"
;
)
;
LLVM_DEBUG
(
dumpCurrGroup
(
"Decode group before emission"
)
;
)
;
if
(
!
fitsIntoCurrentGroup
(
SU
)
)
nextGroup
(
)
;
LLVM_DEBUG
(
raw_string_ostream
cgd
(
CurGroupDbg
)
;
if
(
CurGroupDbg
.
length
(
)
)
cgd
<<
", "
;
dumpSU
(
SU
,
cgd
)
;
)
;
LastEmittedMI
=
SU
->
getInstr
(
)
;
if
(
SU
->
isCall
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"++ Clearing state after call.\n"
;
)
;
Reset
(
)
;
LastEmittedMI
=
SU
->
getInstr
(
)
;
return
;
}
for
(
TargetSchedModel
::
ProcResIter
PI
=
SchedModel
->
getWriteProcResBegin
(
SC
)
,
PE
=
SchedModel
->
getWriteProcResEnd
(
SC
)
;
PI
!=
PE
;
++
PI
)
{
if
(
SchedModel
->
getProcResource
(
PI
->
ProcResourceIdx
)
->
BufferSize
==
1
)
continue
;
int
&
CurrCounter
=
ProcResourceCounters
[
PI
->
ProcResourceIdx
]
;
CurrCounter
+=
PI
->
Cycles
;
if
(
(
CurrCounter
>
ProcResCostLim
)
&&
(
CriticalResourceIdx
==
UINT_MAX
||
(
PI
->
ProcResourceIdx
!=
CriticalResourceIdx
&&
CurrCounter
>
ProcResourceCounters
[
CriticalResourceIdx
]
)
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"++ New critical resource: "
<<
SchedModel
->
getProcResource
(
PI
->
ProcResourceIdx
)
->
Name
<<
"\n"
;
)
;
CriticalResourceIdx
=
PI
->
ProcResourceIdx
;
}
}
if
(
SU
->
isUnbuffered
)
{
LastFPdOpCycleIdx
=
getCurrCycleIdx
(
SU
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"++ Last FPd cycle index: "
<<
LastFPdOpCycleIdx
<<
"\n"
;
)
;
}
CurrGroupSize
+=
getNumDecoderSlots
(
SU
)
;
CurrGroupHas4RegOps
|=
has4RegOps
(
SU
->
getInstr
(
)
)
;
unsigned
GroupLim
=
(
(
CurrGroupHas4RegOps
&&
getNumDecoderSlots
(
SU
)
<
3
)
2
:
3
)
;
assert
(
CurrGroupSize
<=
GroupLim
&&
"SU does not fit into decoder group!"
)
;
if
(
CurrGroupSize
==
GroupLim
||
SC
->
EndGroup
)
nextGroup
(
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .

SystemZ
SystemZ
"++ HazardRecognizer emitting "
"\n"
"Decode group before emission"
", "
"++ Clearing state after call.\n"
1
"++ New critical resource: "
"\n"
"++ Last FPd cycle index: "
"\n"
3
2
3
"SU does not fit into decoder group!"


<s> static tree rs6000_fold_builtin ( tree fndecl ATTRIBUTE_UNUSED , int n_args ATTRIBUTE_UNUSED , tree * args ATTRIBUTE_UNUSED , bool ignore ATTRIBUTE_UNUSED ) { return SUBTARGET_FOLD_BUILTIN ( fndecl , n_args , args , ignore ) ; return NULL_TREE ; } </s>

Target hook for early folding of built-ins , shamelessly stolen from ia64.cc .


"LowerFormalArguments Unhandled argument type: "

"functions with VarArgs or StructRet are not supported"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> static bool rx_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { if ( TARGET_JSR ) return false ; if ( decl == NULL ) return false ; if ( is_fast_interrupt_func ( NULL_TREE ) || is_interrupt_func ( NULL_TREE ) || is_naked_func ( NULL_TREE ) ) return false ; return true ; } </s>

Return nonzero if it is ok to make a tail-call to DECL , a function_decl or NULL if this is an indirect call , using EXP


<s> static rtx arc_legitimize_address_0 ( rtx x , rtx oldx ATTRIBUTE_UNUSED , machine_mode mode ) { rtx addr , inner ; if ( flag_pic && SYMBOLIC_CONST ( x ) ) ( x ) = arc_legitimize_pic_address ( x , 0 ) ; addr = x ; if ( GET_CODE ( addr ) == CONST ) addr = XEXP ( addr , 0 ) ; if ( GET_CODE ( addr ) == PLUS && CONST_INT_P ( XEXP ( addr , 1 ) ) && ( ( GET_CODE ( XEXP ( addr , 0 ) ) == SYMBOL_REF && ! SYMBOL_REF_FUNCTION_P ( XEXP ( addr , 0 ) ) ) || ( REG_P ( XEXP ( addr , 0 ) ) && ( INTVAL ( XEXP ( addr , 1 ) ) & 252 ) ) ) ) { HOST_WIDE_INT offs , upper ; int size = GET_MODE_SIZE ( mode ) ; offs = INTVAL ( XEXP ( addr , 1 ) ) ; upper = ( offs + 256 * size ) & ~ 511 * size ; inner = plus_constant ( Pmode , XEXP ( addr , 0 ) , upper ) ; if ( GET_CODE ( x ) == CONST ) inner = gen_rtx_CONST ( Pmode , inner ) ; addr = plus_constant ( Pmode , force_reg ( Pmode , inner ) , offs - upper ) ; x = addr ; } else if ( GET_CODE ( addr ) == SYMBOL_REF && ! SYMBOL_REF_FUNCTION_P ( addr ) ) x = force_reg ( Pmode , x ) ; if ( memory_address_p ( ( machine_mode ) mode , x ) ) return x ; return NULL_RTX ; } </s>

This is like the hook , but returns NULL when it ca n't / wo n't generate a legitimate address .


<s> static int64_t getNullPointerValue ( unsigned AddrSpace ) { return ( AddrSpace == AMDGPUAS :: LOCAL_ADDRESS || AddrSpace == AMDGPUAS :: PRIVATE_ADDRESS || AddrSpace == AMDGPUAS :: REGION_ADDRESS ) ? - 1 : 0 ; } </s>

Get the integer value of a null pointer in the given address space .


<s> void KudeyarRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( ! TFI -> hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; uint64_t Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = 0 ; if ( Old -> getOpcode ( ) == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Kudeyar :: SUB_RR ) , Kudeyar :: SP ) . addReg ( Kudeyar :: SP ) . addImm ( Amount ) ; } else { assert ( Old -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) ; uint64_t CalleeAmt = Old -> getOperand ( 1 ) . getImm ( ) ; Amount -= CalleeAmt ; if ( Amount ) New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Kudeyar :: ADD_RR ) , Kudeyar :: SP ) . addReg ( Kudeyar :: SP ) . addImm ( Amount ) ; } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { MachineInstr * Old = I ; MachineInstr * New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Kudeyar :: SUB_RR ) , Kudeyar :: SP ) . addReg ( Kudeyar :: SP ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


"Load should return a value and a chain"

LowerOperation - Provide custom lowering hooks for some operations .


<s> static void ix86_default_align ( struct gcc_options * opts ) { if ( opts -> x_align_loops == 0 ) { opts -> x_align_loops = processor_target_table [ ix86_tune ] . align_loop ; align_loops_max_skip = processor_target_table [ ix86_tune ] . align_loop_max_skip ; } if ( opts -> x_align_jumps == 0 ) { opts -> x_align_jumps = processor_target_table [ ix86_tune ] . align_jump ; align_jumps_max_skip = processor_target_table [ ix86_tune ] . align_jump_max_skip ; } if ( opts -> x_align_functions == 0 ) { opts -> x_align_functions = processor_target_table [ ix86_tune ] . align_func ; } } </s>

Default align_ * from the processor table .


<s> void Cpu0SEInstrInfo :: adjustStackPtr ( unsigned SP , int64_t Amount , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned ADDu = Cpu0 :: ADDu ; unsigned ADDiu = Cpu0 :: ADDiu ; if ( isInt < 16 > ( Amount ) ) { BuildMI ( MBB , I , DL , get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; } else { unsigned Reg = loadImmediate ( Amount , MBB , I , DL , nullptr ) ; BuildMI ( MBB , I , DL , get ( ADDu ) , SP ) . addReg ( SP ) . addReg ( Reg , RegState :: Kill ) ; } } </s>


<s> llvm :: FastISel * AArch64 :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) { return new AArch64FastISel ( funcInfo , libInfo ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> bool MandarinPassConfig :: addPreEmitPass ( ) { return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool AMDGPUCallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < unsigned > VRegs ) const { if ( Val ) return false ; MIRBuilder . buildInstr ( AMDGPU :: S_ENDPGM ) ; return true ; } </s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> void emitLocal ( ArrayRef < wasm :: ValType > ) override { } </s>


<s> static void unw_access_gr ( struct _Unwind_Context * info , int regnum , unsigned long * val , char * nat , int write ) { unsigned long * addr , * nat_addr = 0 , nat_mask = 0 , dummy_nat ; struct unw_ireg * ireg ; if ( ( unsigned ) regnum - 1 >= 127 ) abort ( ) ; if ( regnum < 1 ) { nat_addr = addr = & dummy_nat ; dummy_nat = 0 ; } else if ( regnum < 32 ) { ireg = & info -> ireg [ regnum - 2 ] ; addr = ireg -> loc ; if ( addr ) { nat_addr = addr + ireg -> nat . off ; switch ( ireg -> nat . type ) { case UNW_NAT_VAL : if ( write ) { if ( * nat ) { addr [ 0 ] = 0 ; addr [ 1 ] = 0x1fffe ; return ; } addr [ 1 ] = 0x1003e ; } else if ( addr [ 0 ] == 0 && addr [ 1 ] == 0x1ffe ) { * val = 0 ; * nat = 1 ; return ; } case UNW_NAT_NONE : dummy_nat = 0 ; nat_addr = & dummy_nat ; break ; case UNW_NAT_MEMSTK : nat_mask = 1UL << ( ( long ) addr & 0x1f8 ) / 8 ; break ; case UNW_NAT_REGSTK : nat_addr = ia64_rse_rnat_addr ( addr ) ; if ( ( unsigned long ) nat_addr >= info -> regstk_top ) nat_addr = & info -> rnat ; nat_mask = 1UL << ia64_rse_slot_num ( addr ) ; break ; } } } else { addr = ia64_rse_skip_regs ( ( unsigned long * ) info -> bsp , regnum - 32 ) ; nat_addr = ia64_rse_rnat_addr ( addr ) ; if ( ( unsigned long ) nat_addr >= info -> regstk_top ) nat_addr = & info -> rnat ; nat_mask = 1UL << ia64_rse_slot_num ( addr ) ; } if ( write ) { * addr = * val ; if ( * nat ) * nat_addr |= nat_mask ; else * nat_addr &= ~ nat_mask ; } else { * val = * addr ; * nat = ( * nat_addr & nat_mask ) != 0 ; } } </s>


<s> static bool rs6000_cannot_force_const_mem ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { if ( GET_CODE ( x ) == HIGH && GET_CODE ( XEXP ( x , 0 ) ) == UNSPEC ) return true ; if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( XEXP ( XEXP ( x , 0 ) , 0 ) ) != 0 ) return true ; return TARGET_ELF && tls_referenced_p ( x ) ; } </s>


<s> bool PIC16TargetMachine :: addInstSelector ( PassManagerBase & PM , bool Fast ) { PM . add ( createPIC16ISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


"br_on_exn does not have a reversed condition"

Insert branch code into the end of the specified MachineBasicBlock .


<s>
static
MCSymbol
*
GetSymbolFromOperand
(
const
MachineOperand
&
MO
,
AsmPrinter
&
AP
)
{
MCContext
&
Ctx
=
AP
.
OutContext
;
SmallString
<
128
>
Name
;
if
(
!
MO
.
isGlobal
(
)
)
{
assert
(
MO
.
isSymbol
(
)
&&
"Isn't a symbol reference"
)
;
Name
+=
AP
.
MAI
->
getGlobalPrefix
(
)
;
Name
+=
MO
.
getSymbolName
(
)
;
}
else
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
bool
isImplicitlyPrivate
=
false
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_DARWIN_STUB
||
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
)
isImplicitlyPrivate
=
true
;
AP
.
Mang
->
getNameWithPrefix
(
Name
,
GV
,
isImplicitlyPrivate
)
;
}
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_DARWIN_STUB
)
{
Name
+=
"$stub"
;
const
char
*
PGP
=
AP
.
MAI
->
getPrivateGlobalPrefix
(
)
;
const
char
*
Prefix
=
""
;
if
(
!
Name
.
startswith
(
PGP
)
)
{
Prefix
=
PGP
;
}
MCSymbol
*
Sym
=
Ctx
.
GetOrCreateSymbol
(
Twine
(
Prefix
)
+
Twine
(
Name
)
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
getMachOMMI
(
AP
)
.
getFnStubEntry
(
Sym
)
;
if
(
StubSym
.
getPointer
(
)
)
return
Sym
;
if
(
MO
.
isGlobal
(
)
)
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
Mang
->
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
else
{
Name
.
erase
(
Name
.
end
(
)
5
,
Name
.
end
(
)
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
Ctx
.
GetOrCreateSymbol
(
Name
.
str
(
)
)
,
false
)
;
}
return
Sym
;
}
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
{
Name
+=
"$non_lazy_ptr"
;
MCSymbol
*
Sym
=
Ctx
.
GetOrCreateSymbol
(
Name
.
str
(
)
)
;
MachineModuleInfoMachO
&
MachO
=
getMachOMMI
(
AP
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_HIDDEN_FLAG
)
MachO
.
getHiddenGVStubEntry
(
Sym
)
:
MachO
.
getGVStubEntry
(
Sym
)
;
if
(
StubSym
.
getPointer
(
)
==
0
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
Mang
->
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
return
Sym
;
}
return
Ctx
.
GetOrCreateSymbol
(
Name
.
str
(
)
)
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


"flag setting instruction only valid outside IT block"

"instruction only valid inside IT block"

"instruction variant requires ARMv6 or later"

"immediate operand must be in the range [0,4]"

"immediate operand must be in the range [0,15]"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s>
const
RegisterBank
&
AArch64RegisterBankInfo
::
getRegBankFromRegClass
(
const
TargetRegisterClass
&
RC
)
const
{
switch
(
RC
.
getID
(
)
)
{
case
AArch64
::
FPR8RegClassID
:
case
AArch64
::
FPR16RegClassID
:
case
AArch64
::
FPR32RegClassID
:
case
AArch64
::
FPR64RegClassID
:
case
AArch64
::
FPR128RegClassID
:
case
AArch64
::
FPR128_loRegClassID
:
case
AArch64
::
DDRegClassID
:
case
AArch64
::
DDDRegClassID
:
case
AArch64
::
DDDDRegClassID
:
case
AArch64
::
QQRegClassID
:
case
AArch64
::
QQQRegClassID
:
case
AArch64
::
QQQQRegClassID
:
case
AArch64
::
ZPRRegClassID
:
case
AArch64
::
ZPR2RegClassID
:
case
AArch64
::
ZPR3RegClassID
:
case
AArch64
::
ZPR4RegClassID
:
return
getRegBank
(
AArch64
::
FPRRegBankID
)
;
case
AArch64
::
GPR32commonRegClassID
:
case
AArch64
::
GPR32RegClassID
:
case
AArch64
::
GPR32spRegClassID
:
case
AArch64
::
GPR32sponlyRegClassID
:
case
AArch64
::
GPR32allRegClassID
:
case
AArch64
::
GPR64commonRegClassID
:
case
AArch64
::
GPR64RegClassID
:
case
AArch64
::
GPR64spRegClassID
:
case
AArch64
::
GPR64sponlyRegClassID
:
case
AArch64
::
GPR64allRegClassID
:
case
AArch64
::
tcGPR64RegClassID
:
case
AArch64
::
WSeqPairsClassRegClassID
:
case
AArch64
::
XSeqPairsClassRegClassID
:
return
getRegBank
(
AArch64
::
GPRRegBankID
)
;
case
AArch64
::
CCRRegClassID
:
return
getRegBank
(
AArch64
::
CCRRegBankID
)
;
default
:
llvm_unreachable
(
"Register class not supported"
)
;
}
}
</s>


<s> void MSP430InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { if ( ! printAliasInstr ( MI , O ) ) printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static int aarch64_build_constant ( int regnum , HOST_WIDE_INT val , bool generate ) { int insns = 0 ; if ( aarch64_bitmask_imm ( val , DImode ) ) { if ( generate ) emit_move_insn ( gen_rtx_REG ( Pmode , regnum ) , GEN_INT ( val ) ) ; insns = 1 ; } else { int i ; int ncount = 0 ; int zcount = 0 ; HOST_WIDE_INT valp = val >> 16 ; HOST_WIDE_INT valm ; HOST_WIDE_INT tval ; for ( i = 16 ; i < 64 ; i += 16 ) { valm = ( valp & 0xffff ) ; if ( valm != 0 ) ++ zcount ; if ( valm != 0xffff ) ++ ncount ; valp >>= 16 ; } if ( ncount < zcount ) { if ( generate ) emit_move_insn ( gen_rtx_REG ( Pmode , regnum ) , GEN_INT ( val | ~ ( HOST_WIDE_INT ) 0xffff ) ) ; tval = 0xffff ; insns ++ ; } else { if ( generate ) emit_move_insn ( gen_rtx_REG ( Pmode , regnum ) , GEN_INT ( val & 0xffff ) ) ; tval = 0 ; insns ++ ; } val >>= 16 ; for ( i = 16 ; i < 64 ; i += 16 ) { if ( ( val & 0xffff ) != tval ) { if ( generate ) emit_insn ( gen_insv_immdi ( gen_rtx_REG ( Pmode , regnum ) , GEN_INT ( i ) , GEN_INT ( val & 0xffff ) ) ) ; insns ++ ; } val >>= 16 ; } } return insns ; } </s>

Possibly output code to build up a constant in a register . For the benefit of the costs infrastructure , returns the number of instructions which would be emitted . GENERATE inhibits or enables code generation .


<s> unsigned int LC2200AsmBackend :: getNumFixupKinds ( ) const { return LC2200 :: Fixups :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


"Functions with 'no-prototype' attribute must take varargs: "

"Functions with 'no-prototype' attribute should not have params: "

"could not derive a function prototype from usage: "

"Prototypeless function used with conflicting signatures: "

"unexpected use of prototypeless function: "

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> static tree associated_type ( tree decl ) { return ( DECL_CONTEXT ( decl ) && TYPE_P ( DECL_CONTEXT ( decl ) ) ? DECL_CONTEXT ( decl ) : NULL_TREE ) ; } </s>

Return the type that we should use to determine if DECL is imported or exported .


<s>
static
void
arm_print_asm_arch_directives
(
FILE
*
stream
,
cl_target_option
*
targ_options
)
{
arm_build_target
build_target
;
if
(
last_asm_targ_options
==
targ_options
)
return
;
last_asm_targ_options
=
targ_options
;
build_target
.
isa
=
sbitmap_alloc
(
isa_num_bits
)
;
arm_configure_build_target
(
&
build_target
,
targ_options
,
false
)
;
if
(
build_target
.
core_name
&&
!
bitmap_bit_p
(
build_target
.
isa
,
isa_bit_quirk_no_asmcpu
)
)
{
const
char
*
truncated_name
=
arm_rewrite_selected_cpu
(
build_target
.
core_name
)
;
asm_fprintf
(
stream
,
"\t.cpu %s\n"
,
truncated_name
)
;
}
const
arch_option
*
arch
=
arm_parse_arch_option_name
(
all_architectures
,
"-march"
,
build_target
.
arch_name
)
;
auto_sbitmap
opt_bits
(
isa_num_bits
)
;
gcc_assert
(
arch
)
;
if
(
strcmp
(
build_target
.
arch_name
,
"armv7ve"
)
==
0
)
{
asm_fprintf
(
stream
,
"\t.arch armv7-a\n"
)
;
asm_fprintf
(
stream
,
"\t.arch_extension virt\n"
)
;
asm_fprintf
(
stream
,
"\t.arch_extension idiv\n"
)
;
asm_fprintf
(
stream
,
"\t.arch_extension sec\n"
)
;
asm_fprintf
(
stream
,
"\t.arch_extension mp\n"
)
;
}
else
asm_fprintf
(
stream
,
"\t.arch %s\n"
,
build_target
.
arch_name
)
;
const
char
*
fpu_name
=
(
TARGET_SOFT_FLOAT
"softvfp"
:
arm_identify_fpu_from_isa
(
build_target
.
isa
)
)
;
asm_fprintf
(
stream
,
"\t.fpu %s\n"
,
fpu_name
)
;
if
(
!
arch
->
common
.
extensions
)
return
;
for
(
const
struct
cpu_arch_extension
*
opt
=
arch
->
common
.
extensions
;
opt
->
name
!=
;
opt
++
)
{
if
(
!
opt
->
remove
)
{
arm_initialize_isa
(
opt_bits
,
opt
->
isa_bits
)
;
if
(
(
bitmap_bit_p
(
opt_bits
,
isa_bit_mve
)
&&
!
TARGET_HAVE_MVE
)
||
(
bitmap_bit_p
(
opt_bits
,
isa_bit_mve_float
)
&&
!
TARGET_HAVE_MVE_FLOAT
)
)
continue
;
if
(
bitmap_subset_p
(
opt_bits
,
build_target
.
isa
)
&&
!
bitmap_subset_p
(
opt_bits
,
isa_all_fpubits_internal
)
)
asm_fprintf
(
stream
,
"\t.arch_extension %s\n"
,
opt
->
name
)
;
}
}
}
</s>

Print .arch and .arch_extension directives corresponding to the current architecture configuration .

arm
"\t.cpu %s\n"
"-march"
"armv7ve"
0
"\t.arch armv7-a\n"
"\t.arch_extension virt\n"
"\t.arch_extension idiv\n"
"\t.arch_extension sec\n"
"\t.arch_extension mp\n"
"\t.arch %s\n"
"softvfp"
"\t.fpu %s\n"
"\t.arch_extension %s\n"


<s> void PPCPassConfig :: addPreRegAlloc ( ) { initializePPCVSXFMAMutatePass ( * PassRegistry :: getPassRegistry ( ) ) ; insertPass ( VSXFMAMutateEarly ? & RegisterCoalescerID : & MachineSchedulerID , & PPCVSXFMAMutateID ) ; if ( getPPCTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) addPass ( createPPCTLSDynamicCallPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


"loadRegFromStackSlot didn't insert any code!"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool AMDGPUTargetLowering :: ShouldShrinkFPConstant ( EVT VT ) const { if ( VT . getScalarType ( ) . getSimpleVT ( ) . SimpleTy == MVT :: f32 || VT . getScalarType ( ) . getSimpleVT ( ) . SimpleTy == MVT :: f64 ) { return false ; } else { return true ; } } </s>

If true , then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime .


<s> rtx mips_return_addr ( int count , rtx frame ATTRIBUTE_UNUSED ) { if ( count != 0 ) return const0_rtx ; return get_hard_reg_initial_val ( Pmode , RETURN_ADDR_REGNUM ) ; } </s>

Implement RETURN_ADDR_RTX . Note , we do not support moving back to a previous frame .


<s>
CCAssignFn
*
ARM64TargetLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
const
{
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention."
)
;
case
CallingConv
::
WebKit_JS
:
return
CC_ARM64_WebKit_JS
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
if
(
!
Subtarget
->
isTargetDarwin
(
)
)
return
CC_ARM64_AAPCS
;
return
IsVarArg
CC_ARM64_DarwinPCS_VarArg
:
CC_ARM64_DarwinPCS
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> FastISel * X86 :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) { return new X86FastISel ( funcInfo , libInfo ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> static bool get_unit_operand_masks ( rtx_insn * insn , unsigned int * pmask1 , unsigned int * pmask2 ) { enum attr_op_pattern op_pat ; if ( recog_memoized ( insn ) < 0 ) return 0 ; if ( GET_CODE ( PATTERN ( insn ) ) == COND_EXEC ) return false ; extract_insn ( insn ) ; op_pat = get_attr_op_pattern ( insn ) ; if ( op_pat == OP_PATTERN_DT ) { gcc_assert ( recog_data . n_operands == 2 ) ; * pmask1 = 1 << 0 ; * pmask2 = 1 << 1 ; return true ; } else if ( op_pat == OP_PATTERN_TD ) { gcc_assert ( recog_data . n_operands == 2 ) ; * pmask1 = 1 << 1 ; * pmask2 = 1 << 0 ; return true ; } else if ( op_pat == OP_PATTERN_SXS ) { gcc_assert ( recog_data . n_operands == 3 ) ; * pmask1 = ( 1 << 0 ) | ( 1 << 2 ) ; * pmask2 = 1 << 1 ; return true ; } else if ( op_pat == OP_PATTERN_SX ) { gcc_assert ( recog_data . n_operands == 2 ) ; * pmask1 = 1 << 0 ; * pmask2 = 1 << 1 ; return true ; } else if ( op_pat == OP_PATTERN_SSX ) { gcc_assert ( recog_data . n_operands == 3 ) ; * pmask1 = ( 1 << 0 ) | ( 1 << 1 ) ; * pmask2 = 1 << 2 ; return true ; } return false ; } </s>

Examine INSN , and store in PMASK1 and PMASK2 bitmasks that represent the operands that are involved in the ( up to ) two reservations , as found by get_unit_reqs . Return true if we did this successfully , false if we could n't identify what to do with INSN .


<s> void WebAssemblyTargetELFStreamer :: emitIndIdx ( const MCExpr * Value ) { Streamer . EmitIntValue ( WebAssembly :: DotIndIdx , sizeof ( uint64_t ) ) ; Streamer . EmitValue ( Value , sizeof ( uint64_t ) ) ; } </s>


<s> RegisterSet & insert ( const RegisterSet & Rs ) { return static_cast < RegisterSet & > ( BitVector :: operator |= ( Rs ) ) ; } </s>

insert - Append entry to the vector if it does n't already exist .


<s> static void epiphany_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; * cum = ( ROUND_ADVANCE_CUM ( * cum , arg . mode , arg . type ) + ROUND_ADVANCE_ARG ( arg . mode , arg . type ) ) ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> void addLOHDirective ( MCLOHType Kind , MILOHArgs Args ) { LOHContainerSet . push_back ( MILOHDirective ( Kind , Args ) ) ; LOHRelated . insert ( Args . begin ( ) , Args . end ( ) ) ; } </s>

Add a LOH directive of this Kind and this Args .


<s> static bool tilepro_tls_referenced_p ( rtx x ) { if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS ) x = XEXP ( XEXP ( x , 0 ) , 0 ) ; if ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) ) return true ; return false ; } </s>

Return true if X contains a thread-local symbol .


<s> PPCSubtarget & PPCSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { initializeEnvironment ( ) ; resetSubtargetFeatures ( CPU , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> void RISCVTargetStreamer :: finish ( ) { finishAttributeSection ( ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> unsigned getGlobalBaseReg ( ) const { return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static int ix86_fp_comparison_fcomi_cost ( enum rtx_code code ) { enum rtx_code bypass_code , first_code , second_code ; if ( ! TARGET_CMOVE ) return 1024 ; ix86_fp_comparison_codes ( code , & bypass_code , & first_code , & second_code ) ; return ( bypass_code != UNKNOWN || second_code != UNKNOWN ) + 2 ; } </s>

Return cost of comparison done using fcomi operation . See ix86_fp_comparison_arithmetics_cost for the metrics .


<s> bool VideocoreDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintCode ) { default : return true ; case 'm' : if ( ! SelectADDRrr ( Op , Op0 , Op1 ) ) SelectADDRri ( Op , Op0 , Op1 ) ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> int thumb_legitimate_offset_p ( enum machine_mode mode , HOST_WIDE_INT val ) { switch ( GET_MODE_SIZE ( mode ) ) { case 1 : return val >= 0 && val < 32 ; case 2 : return val >= 0 && val < 64 && ( val & 1 ) == 0 ; default : return ( val >= 0 && ( val + GET_MODE_SIZE ( mode ) ) <= 128 && ( val & 3 ) == 0 ) ; } } </s>

Return nonzero if VAL can be used as an offset in a Thumb-state address instruction of mode MODE .


<s> bool ARMRegisterInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return NoFramePointerElim || MFI -> hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static void riscv_for_each_saved_reg ( HOST_WIDE_INT sp_offset , riscv_save_restore_fn fn ) { HOST_WIDE_INT offset ; offset = cfun -> machine -> frame . gp_sp_offset - sp_offset ; for ( int regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . mask , regno - GP_REG_FIRST ) ) { riscv_save_restore_reg ( word_mode , regno , offset , fn ) ; offset -= UNITS_PER_WORD ; } offset = cfun -> machine -> frame . fp_sp_offset - sp_offset ; for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . fmask , regno - FP_REG_FIRST ) ) { machine_mode mode = TARGET_DOUBLE_FLOAT ? DFmode : SFmode ; riscv_save_restore_reg ( mode , regno , offset , fn ) ; offset -= GET_MODE_SIZE ( mode ) ; } } </s>

Call FN for each register that is saved by the current function . SP_OFFSET is the offset of the current stack pointer from the start of the frame .


<s> int X86TTIImpl :: getIntrinsicInstrCost ( Intrinsic :: ID IID , Type * RetTy , ArrayRef < Value * > Args , FastMathFlags FMF ) { return BaseT :: getIntrinsicInstrCost ( IID , RetTy , Args , FMF ) ; } </s>


<s> static rtx c6x_function_arg ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( cum -> count >= cum -> nregs ) return NULL_RTX ; if ( tree type = arg . type ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; if ( TARGET_BIG_ENDIAN && AGGREGATE_TYPE_P ( type ) ) { if ( size > 4 ) { rtx reg1 = gen_rtx_REG ( SImode , argument_registers [ cum -> count ] + 1 ) ; rtx reg2 = gen_rtx_REG ( SImode , argument_registers [ cum -> count ] ) ; rtvec vec = gen_rtvec ( 2 , gen_rtx_EXPR_LIST ( VOIDmode , reg1 , const0_rtx ) , gen_rtx_EXPR_LIST ( VOIDmode , reg2 , GEN_INT ( 4 ) ) ) ; return gen_rtx_PARALLEL ( arg . mode , vec ) ; } } } return gen_rtx_REG ( arg . mode , argument_registers [ cum -> count ] ) ; } </s>

Implements the macro FUNCTION_ARG defined in c6x.h .


<s> bool contains ( int32_t V ) const { return Min <= V && V <= Max && ( V % Align ) == 0 ; } </s>

contains - Returns true if this trace contains the given basic block .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"WebAssembly Optimize Returned"
;
}
</s>

getPassName - Return a nice clean name for a pass .

WebAssembly
"WebAssembly Optimize Returned"


<s> SMRange getLocRange ( ) const { return SMRange ( StartLoc , EndLoc ) ; } </s>

getLocRange - Get the range between the first and last token of this operand .


<s> static void arm_print_value ( FILE * f , rtx x ) { switch ( GET_CODE ( x ) ) { case CONST_INT : fprintf ( f , HOST_WIDE_INT_PRINT_HEX , INTVAL ( x ) ) ; return ; case CONST_DOUBLE : { char fpstr [ 20 ] ; real_to_decimal ( fpstr , CONST_DOUBLE_REAL_VALUE ( x ) , sizeof ( fpstr ) , 0 , 1 ) ; fputs ( fpstr , f ) ; } return ; case CONST_VECTOR : { int i ; fprintf ( f , "<" ) ; for ( i = 0 ; i < CONST_VECTOR_NUNITS ( x ) ; i ++ ) { fprintf ( f , HOST_WIDE_INT_PRINT_HEX , INTVAL ( CONST_VECTOR_ELT ( x , i ) ) ) ; if ( i < ( CONST_VECTOR_NUNITS ( x ) - 1 ) ) fputc ( ',' , f ) ; } fprintf ( f , ">" ) ; } return ; case CONST_STRING : fprintf ( f , "\"%s\"" , XSTR ( x , 0 ) ) ; return ; case SYMBOL_REF : fprintf ( f , "`%s'" , XSTR ( x , 0 ) ) ; return ; case LABEL_REF : fprintf ( f , "L%d" , INSN_UID ( XEXP ( x , 0 ) ) ) ; return ; case CONST : arm_print_value ( f , XEXP ( x , 0 ) ) ; return ; case PLUS : arm_print_value ( f , XEXP ( x , 0 ) ) ; fprintf ( f , "+" ) ; arm_print_value ( f , XEXP ( x , 1 ) ) ; return ; case PC : fprintf ( f , "pc" ) ; return ; default : fprintf ( f , "????" ) ; return ; } } </s>

Print a symbolic form of X to the debug file , F .


<s> void AMDGPUAsmPrinter :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < AMDGPUResourceUsageAnalysis > ( ) ; AU . addPreserved < AMDGPUResourceUsageAnalysis > ( ) ; AsmPrinter :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> addr_space_t nvptx_addr_space_from_address ( rtx addr ) { while ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == CONST ) addr = XEXP ( addr , 0 ) ; if ( GET_CODE ( addr ) != SYMBOL_REF ) return ADDR_SPACE_GENERIC ; tree decl = SYMBOL_REF_DECL ( addr ) ; if ( decl == NULL_TREE || TREE_CODE ( decl ) == FUNCTION_DECL ) return ADDR_SPACE_GENERIC ; bool is_const = ( CONSTANT_CLASS_P ( decl ) || TREE_CODE ( decl ) == CONST_DECL || TREE_READONLY ( decl ) ) ; if ( is_const ) return ADDR_SPACE_CONST ; return ADDR_SPACE_GLOBAL ; } </s>

Look for a SYMBOL_REF in ADDR and return the address space to be used for the insn referencing this address .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Z80old Machine Late Optimization"
;
}
</s>


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> bool M680x0FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { auto & MRI = * static_cast < const M680x0RegisterInfo * > ( TRI ) ; auto DL = MBB . findDebugLoc ( MI ) ; int FI = 0 ; unsigned Mask = 0 ; for ( size_t i = 0 ; i < CSI . size ( ) ; ++ i ) { FI = std :: max ( FI , CSI [ i ] . getFrameIdx ( ) ) ; unsigned Reg = CSI [ i ] . getReg ( ) ; unsigned Shift = MRI . getSpillRegisterOrder ( Reg ) ; Mask |= 1 << Shift ; } auto I = addFrameReference ( BuildMI ( MBB , MI , DL , TII . get ( M680x0 :: MOVM32pm ) ) , FI ) . addImm ( Mask ) . setMIFlag ( MachineInstr :: FrameSetup ) ; const MachineFunction & MF = * MBB . getParent ( ) ; const MachineRegisterInfo & RI = MF . getRegInfo ( ) ; for ( size_t i = 0 ; i < CSI . size ( ) ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool isLiveIn = RI . isLiveIn ( Reg ) ; if ( ! isLiveIn ) MBB . addLiveIn ( Reg ) ; I . addReg ( Reg , isLiveIn ? RegState :: Implicit : RegState :: ImplicitKill ) ; addMemOperand ( I , CSI [ i ] . getFrameIdx ( ) , 0 ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> void epiphany_init_expanders ( void ) { init_machine_status = epiphany_init_machine_status ; } </s>

Implements INIT_EXPANDERS . We just set up to call the above * function .


<s> bool TLCS900PassConfig :: addInstSelector ( ) { PM -> add ( createTLCS900ISelDag ( getTLCS900TargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static int m32c_leaf_function_p ( void ) { rtx_insn * saved_first , * saved_last ; struct sequence_stack * seq ; int rv ; saved_first = crtl -> emit . x_first_insn ; saved_last = crtl -> emit . x_last_insn ; for ( seq = crtl -> emit . sequence_stack ; seq && seq -> next ; seq = seq -> next ) ; if ( seq ) { crtl -> emit . x_first_insn = seq -> first ; crtl -> emit . x_last_insn = seq -> last ; } rv = leaf_function_p ( ) ; crtl -> emit . x_first_insn = saved_first ; crtl -> emit . x_last_insn = saved_last ; return rv ; } </s>

Returns TRUE if the current function is a leaf , and thus we can determine which registers an interrupt function really needs to save . The logic below is mostly about finding the insn sequence that 's the function , versus any sequence that might be open for the current insn .


<s> static bool ix86_function_ok_for_sibcall ( tree decl , tree exp ) { tree func ; rtx a , b ; if ( ! TARGET_64BIT && flag_pic && ( ! decl || TREE_PUBLIC ( decl ) ) ) return false ; if ( decl ) func = decl ; else { func = TREE_TYPE ( TREE_OPERAND ( exp , 0 ) ) ; if ( POINTER_TYPE_P ( func ) ) func = TREE_TYPE ( func ) ; } a = ix86_function_value ( TREE_TYPE ( exp ) , func , false ) ; b = ix86_function_value ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) , cfun -> decl , false ) ; if ( STACK_REG_P ( a ) || STACK_REG_P ( b ) ) { if ( ! rtx_equal_p ( a , b ) ) return false ; } else if ( VOID_TYPE_P ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) ) ) ; else if ( ! rtx_equal_p ( a , b ) ) return false ; if ( ! decl && ! TARGET_64BIT ) { tree type ; type = TREE_OPERAND ( exp , 0 ) ; type = TREE_TYPE ( type ) ; type = TREE_TYPE ( type ) ; if ( ix86_function_regparm ( type , NULL ) >= 3 ) { return false ; } } if ( decl && DECL_DLLIMPORT_P ( decl ) && ix86_function_regparm ( TREE_TYPE ( decl ) , NULL ) >= 3 ) return false ; if ( cfun -> machine -> force_align_arg_pointer ) return false ; return true ; } </s>

Decide whether we can make a sibling call to a function . DECL is the declaration of the function being targeted by the call and EXP is the CALL_EXPR representing the call .


<s> static machine_mode c6x_preferred_simd_mode ( machine_mode mode ) { switch ( mode ) { case HImode : return V2HImode ; case QImode : return V4QImode ; default : return word_mode ; } } </s>


<s> void mips16_expand_set_fcsr ( rtx newval ) { if ( ! mips16_set_fcsr_stub ) mips16_set_fcsr_stub = new mips16_set_fcsr_one_only_stub ( ) ; rtx fn = mips16_stub_call_address ( mips16_set_fcsr_stub ) ; emit_move_insn ( gen_rtx_REG ( SImode , SET_FCSR_REGNUM ) , newval ) ; emit_insn ( PMODE_INSN ( gen_mips_set_fcsr_mips16 , ( fn ) ) ) ; } </s>

Implement __builtin_mips_set_fcsr ( TARGET ) for MIPS16 , using a stub .


Create an WebAssembly architecture model .


<s> void final_prescan_insn ( rtx insn , rtx opvec [ ] ATTRIBUTE_UNUSED , int noperands ATTRIBUTE_UNUSED ) { if ( dslots_number_nops > 0 ) { rtx pattern = PATTERN ( insn ) ; int length = get_attr_length ( insn ) ; if ( length == 0 || ( iq2000_load_reg != 0 && reg_mentioned_p ( iq2000_load_reg , pattern ) ) || ( iq2000_load_reg2 != 0 && reg_mentioned_p ( iq2000_load_reg2 , pattern ) ) || ( iq2000_load_reg3 != 0 && reg_mentioned_p ( iq2000_load_reg3 , pattern ) ) || ( iq2000_load_reg4 != 0 && reg_mentioned_p ( iq2000_load_reg4 , pattern ) ) ) fputs ( "\tnop\n" , asm_out_file ) ; else dslots_load_filled ++ ; while ( -- dslots_number_nops > 0 ) fputs ( "\tnop\n" , asm_out_file ) ; iq2000_load_reg = 0 ; iq2000_load_reg2 = 0 ; iq2000_load_reg3 = 0 ; iq2000_load_reg4 = 0 ; } if ( ( GET_CODE ( insn ) == JUMP_INSN || GET_CODE ( insn ) == CALL_INSN || ( GET_CODE ( PATTERN ( insn ) ) == RETURN ) ) && NEXT_INSN ( PREV_INSN ( insn ) ) == insn ) { rtx nop_insn = emit_insn_after ( gen_nop ( ) , insn ) ; INSN_ADDRESSES_NEW ( nop_insn , - 1 ) ; } if ( TARGET_STATS && ( GET_CODE ( insn ) == JUMP_INSN || GET_CODE ( insn ) == CALL_INSN ) ) dslots_jump_total ++ ; } </s>

If defined , a C statement to be executed just prior to the output of assembler code for INSN , to modify the extracted operands so they will be output differently . Here the argument OPVEC is the vector containing the operands extracted from INSN , and NOPERANDS is the number of elements of the vector which contain meaningful data for this insn . The contents of this vector are what will be used to convert the insn template into assembler code , so you can change the assembler output by changing the contents of the vector . We use it to check if the current insn needs a nop in front of it because of load delays , and also to update the delay slot statistics .


<s> static void restore_saved_cr ( rtx reg , int using_mfcr_multiple , bool exit_func ) { int count = 0 ; int i ; if ( using_mfcr_multiple ) { for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) count ++ ; gcc_assert ( count ) ; } if ( using_mfcr_multiple && count > 1 ) { rtx_insn * insn ; rtvec p ; int ndx ; p = rtvec_alloc ( count ) ; ndx = 0 ; for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) { rtvec r = rtvec_alloc ( 2 ) ; RTVEC_ELT ( r , 0 ) = reg ; RTVEC_ELT ( r , 1 ) = GEN_INT ( 1 << ( 7 - i ) ) ; RTVEC_ELT ( p , ndx ) = gen_rtx_SET ( VOIDmode , gen_rtx_REG ( CCmode , CR0_REGNO + i ) , gen_rtx_UNSPEC ( CCmode , r , UNSPEC_MOVESI_TO_CR ) ) ; ndx ++ ; } insn = emit_insn ( gen_rtx_PARALLEL ( VOIDmode , p ) ) ; gcc_assert ( ndx == count ) ; if ( ! exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap ) { for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) add_reg_note ( insn , REG_CFA_RESTORE , gen_rtx_REG ( SImode , CR0_REGNO + i ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } else for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) { rtx insn = emit_insn ( gen_movsi_to_cr_one ( gen_rtx_REG ( CCmode , CR0_REGNO + i ) , reg ) ) ; if ( ! exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap ) { add_reg_note ( insn , REG_CFA_RESTORE , gen_rtx_REG ( SImode , CR0_REGNO + i ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } if ( ! exit_func && DEFAULT_ABI != ABI_ELFv2 && ( DEFAULT_ABI == ABI_V4 || flag_shrink_wrap ) ) { rtx_insn * insn = get_last_insn ( ) ; rtx cr = gen_rtx_REG ( SImode , CR2_REGNO ) ; add_reg_note ( insn , REG_CFA_RESTORE , cr ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } </s>


<s>
void
NVPTXAsmPrinter
::
emitImplicitDef
(
const
MachineInstr
*
MI
)
const
{
unsigned
RegNo
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
if
(
TargetRegisterInfo
::
isVirtualRegister
(
RegNo
)
)
{
OutStreamer
->
AddComment
(
Twine
(
"implicit-def: "
)
+
getVirtualRegisterName
(
RegNo
)
)
;
}
else
{
const
NVPTXSubtarget
&
STI
=
MI
->
getMF
(
)
->
getSubtarget
<
NVPTXSubtarget
>
(
)
;
OutStreamer
->
AddComment
(
Twine
(
"implicit-def: "
)
+
STI
.
getRegisterInfo
(
)
->
getName
(
RegNo
)
)
;
}
OutStreamer
->
AddBlankLine
(
)
;
}
</s>

Targets can override this to customize the output of IMPLICIT_DEF instructions in verbose mode .

NVPTX
NVPTX
0
"implicit-def: "
NVPTX
NVPTX
"implicit-def: "


<s> bool RISCVTargetLowering :: isCheapToSpeculateCtlz ( ) const { return Subtarget . hasStdExtZbb ( ) ; } </s>

Return true if it is cheap to speculate a call to intrinsic ctlz .


"Check for a non-legal type in this operation\n"

LowerOperation - Provide custom lowering hooks for some operations .


"Can only insert epilog into returning blocks"


<s> void CSKYTargetStreamer :: emitCurrentConstantPool ( ) { ConstantPool -> emitAll ( Streamer ) ; ConstantPool -> clearCache ( ) ; } </s>

Callback used to implement the .ltorg directive .


<s> enum direction pa_function_arg_padding ( machine_mode mode , const_tree type ) { if ( mode == BLKmode || ( TARGET_64BIT && type && ( AGGREGATE_TYPE_P ( type ) || TREE_CODE ( type ) == COMPLEX_TYPE || TREE_CODE ( type ) == VECTOR_TYPE ) ) ) { if ( type && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && ( int_size_in_bytes ( type ) * BITS_PER_UNIT ) % PARM_BOUNDARY == 0 ) return none ; if ( TARGET_64BIT ) return upward ; else return downward ; } if ( GET_MODE_BITSIZE ( mode ) < PARM_BOUNDARY ) return downward ; else return none ; } </s>


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsPCRel ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittleEndian ? i : ( NumBytes - 1 - i ) ; Data [ Offset + i ] |= uint8_t ( ( Value >> ( Idx * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static machine_mode mips_dwarf_frame_reg_mode ( int regno ) { machine_mode mode = default_dwarf_frame_reg_mode ( regno ) ; if ( FP_REG_P ( regno ) && mips_abi == ABI_32 && ! TARGET_FLOAT32 ) mode = SImode ; return mode ; } </s>


<s> static void mips_sim_record_set ( rtx x , rtx pat ATTRIBUTE_UNUSED , void * data ) { struct mips_sim * state ; unsigned int i ; state = data ; if ( REG_P ( x ) ) for ( i = 0 ; i < HARD_REGNO_NREGS ( REGNO ( x ) , GET_MODE ( x ) ) ; i ++ ) { state -> last_set [ REGNO ( x ) + i ] . insn = mips_sim_insn ; state -> last_set [ REGNO ( x ) + i ] . time = state -> time ; } } </s>

mips_sim_insn has just set X. Update the LAST_SET array in simulation state DATA .


<s> static bool rs6000_return_in_msb ( const_tree valtype ) { return ( DEFAULT_ABI == ABI_ELFv2 && BYTES_BIG_ENDIAN && AGGREGATE_TYPE_P ( valtype ) && FUNCTION_ARG_PADDING ( TYPE_MODE ( valtype ) , valtype ) == upward ) ; } </s>

Specify whether values returned in registers should be at the most significant end of a register . We want aggregates returned by value to match the way aggregates are passed to functions .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"SystemZ Long Branch"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool prefixed_paddi_p ( rtx_insn * insn ) { rtx set = single_set ( insn ) ; if ( ! set ) return false ; rtx dest = SET_DEST ( set ) ; rtx src = SET_SRC ( set ) ; if ( ! REG_P ( dest ) && ! SUBREG_P ( dest ) ) return false ; if ( CONST_INT_P ( src ) ) return ( satisfies_constraint_eI ( src ) && ! satisfies_constraint_I ( src ) && ! satisfies_constraint_L ( src ) ) ; if ( GET_CODE ( src ) == PLUS ) { rtx op1 = XEXP ( src , 1 ) ; return ( CONST_INT_P ( op1 ) && satisfies_constraint_eI ( op1 ) && ! satisfies_constraint_I ( op1 ) && ! satisfies_constraint_L ( op1 ) ) ; } if ( ! TARGET_PCREL || GET_MODE ( dest ) != Pmode ) return false ; if ( ! SYMBOL_REF_P ( src ) && ! LABEL_REF_P ( src ) && GET_CODE ( src ) != CONST ) return false ; enum insn_form iform = address_to_insn_form ( src , Pmode , NON_PREFIXED_DEFAULT ) ; return ( iform == INSN_FORM_PCREL_EXTERNAL || iform == INSN_FORM_PCREL_LOCAL ) ; } </s>

Whether a load immediate or add instruction is a prefixed instruction . This is called from the prefixed attribute processing .


"rs6000_builtin_md_vectorized_function (%s, %s, %s)\n"


<s> SDValue MipsTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; unsigned Opc = N -> getOpcode ( ) ; switch ( Opc ) { default : break ; case ISD :: SDIVREM : case ISD :: UDIVREM : return performDivRemCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SELECT : return performSELECTCombine ( N , DAG , DCI , Subtarget ) ; case MipsISD :: CMovFP_F : case MipsISD :: CMovFP_T : return performCMovFPCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: AND : return performANDCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: OR : return performORCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: ADD : return performADDCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips Mips ISD::SDIVREM ISD::UDIVREM ISD::SELECT MipsISD::CMovFP_F MipsISD::CMovFP_T ISD::AND ISD::OR ISD::ADD


<s>
bool
ARCFrameLowering
::
spillCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Spill callee saved registers: "
<<
MBB
.
getParent
(
)
->
getName
(
)
<<
"\n"
)
;
unsigned
Last
=
determineLastCalleeSave
(
CSI
)
;
if
(
UseSaveRestoreFunclet
&&
Last
>
ARC
::
R14
)
{
return
true
;
}
return
false
;
}
</s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .

ARC
ARC
"Spill callee saved registers: "
"\n"
ARC::R14


<s> virtual const TargetFrameInfo * getFrameInfo ( ) const { return & FrameInfo ; } </s>

getFrameInfo - Return the frame info object for the current function .


Change register usage conditional on target flags .


<s> rtx riscv_function_value ( const_tree type , const_tree func , enum machine_mode mode ) { struct riscv_arg_info info ; CUMULATIVE_ARGS args ; if ( type ) { int unsigned_p = TYPE_UNSIGNED ( type ) ; mode = TYPE_MODE ( type ) ; mode = promote_function_mode ( type , mode , & unsigned_p , func , 1 ) ; } memset ( & args , 0 , sizeof args ) ; return riscv_get_arg_info ( & info , & args , mode , type , true , true ) ; } </s>

Implement FUNCTION_VALUE and LIBCALL_VALUE . For normal calls , VALTYPE is the return type and MODE is VOIDmode . For libcalls , VALTYPE is null and MODE is the mode of the return value .


<s> static unsigned ix86_loop_unroll_adjust ( unsigned nunroll , struct loop * loop ) { basic_block * bbs ; rtx_insn * insn ; unsigned i ; unsigned mem_count = 0 ; if ( ! TARGET_ADJUST_UNROLL ) return nunroll ; subrtx_iterator :: array_type array ; bbs = get_loop_body ( loop ) ; for ( i = 0 ; i < loop -> num_nodes ; i ++ ) FOR_BB_INSNS ( bbs [ i ] , insn ) if ( NONDEBUG_INSN_P ( insn ) ) FOR_EACH_SUBRTX ( iter , array , insn , NONCONST ) if ( const_rtx x = * iter ) if ( MEM_P ( x ) ) { machine_mode mode = GET_MODE ( x ) ; unsigned int n_words = GET_MODE_SIZE ( mode ) / UNITS_PER_WORD ; if ( n_words > 4 ) mem_count += 2 ; else mem_count += 1 ; } free ( bbs ) ; if ( mem_count && mem_count <= 32 ) return 32 / mem_count ; return nunroll ; } </s>

This function adjusts the unroll factor based on the hardware capabilities . For ex , bdver3 has a loop buffer which makes unrolling of smaller loops less important . This function decides the unroll factor using number of memory references ( value 32 is used ) as a heuristic .


<s> bool pdp11_expand_shift ( rtx * operands , rtx ( * shift_sc ) ( rtx , rtx , rtx ) , rtx ( * shift_base ) ( rtx , rtx , rtx ) ) { rtx r , test ; rtx_code_label * lb ; if ( CONST_INT_P ( operands [ 2 ] ) && pdp11_small_shift ( INTVAL ( operands [ 2 ] ) ) ) emit_insn ( ( * shift_sc ) ( operands [ 0 ] , operands [ 1 ] , operands [ 2 ] ) ) ; else if ( TARGET_40_PLUS ) return false ; else { lb = gen_label_rtx ( ) ; r = gen_reg_rtx ( HImode ) ; emit_move_insn ( operands [ 0 ] , operands [ 1 ] ) ; emit_move_insn ( r , operands [ 2 ] ) ; if ( ! CONST_INT_P ( operands [ 2 ] ) ) { test = gen_rtx_LE ( HImode , r , const0_rtx ) ; emit_jump_insn ( gen_cbranchhi4 ( test , r , const0_rtx , lb ) ) ; } emit_insn ( ( * shift_base ) ( operands [ 0 ] , operands [ 1 ] , r ) ) ; if ( ! CONST_INT_P ( operands [ 2 ] ) ) { emit_label ( lb ) ; emit_use ( stack_pointer_rtx ) ; } } return true ; } </s>

Expand a shift insn . Returns true if the expansion was done , false if it needs to be handled by the caller .