<s> static unsigned arm_add_stmt_cost ( void * data , int count , enum vect_cost_for_stmt kind , struct _stmt_vec_info * stmt_info , int misalign , enum vect_cost_model_location where ) { unsigned * cost = ( unsigned * ) data ; unsigned retval = 0 ; if ( flag_vect_cost_model ) { tree vectype = stmt_info ? stmt_vectype ( stmt_info ) : NULL_TREE ; int stmt_cost = arm_builtin_vectorization_cost ( kind , vectype , misalign ) ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( stmt_info ) ) count *= 50 ; retval = ( unsigned ) ( count * stmt_cost ) ; cost [ where ] += retval ; } return retval ; } </s>


Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> MachineBasicBlock * getHeader ( ) const override { return Region -> getHeader ( ) ; } </s>

The header is the entry for each iteration .


<s> bool direct_move_p ( rtx op0 , rtx op1 ) { int regno0 , regno1 ; if ( ! REG_P ( op0 ) || ! REG_P ( op1 ) ) return false ; if ( ! TARGET_DIRECT_MOVE && ! TARGET_MFPGPR ) return false ; regno0 = REGNO ( op0 ) ; regno1 = REGNO ( op1 ) ; if ( regno0 >= FIRST_PSEUDO_REGISTER || regno1 >= FIRST_PSEUDO_REGISTER ) return false ; if ( INT_REGNO_P ( regno0 ) ) return ( TARGET_DIRECT_MOVE ) ? VSX_REGNO_P ( regno1 ) : FP_REGNO_P ( regno1 ) ; else if ( INT_REGNO_P ( regno1 ) ) { if ( TARGET_MFPGPR && FP_REGNO_P ( regno0 ) ) return true ; else if ( TARGET_DIRECT_MOVE && VSX_REGNO_P ( regno0 ) ) return true ; } return false ; } </s>

Return true if this is a move direct operation between GPR registers and floating point/VSX registers .


Return an array that contains the direct target flag values and their names .


<s> static bool mmix_pass_by_reference ( cumulative_args_t argsp_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * argsp = get_cumulative_args ( argsp_v ) ; if ( targetm . calls . must_pass_in_stack ( arg ) ) return true ; if ( MMIX_FUNCTION_ARG_SIZE ( arg . mode , arg . type ) > 8 && ! TARGET_LIBFUNC && ( ! argsp || ! argsp -> lib ) ) return true ; return false ; } </s>

Returns nonzero for everything that goes by reference , 0 for everything that goes by value .


<s>
void
SPUFrameInfo
::
determineFrameLayout
(
MachineFunction
&
MF
)
const
{
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
unsigned
FrameSize
=
MFI
->
getStackSize
(
)
;
unsigned
TargetAlign
=
MF
.
getTarget
(
)
.
getFrameInfo
(
)
->
getStackAlignment
(
)
;
unsigned
Align
=
std
::
max
(
TargetAlign
,
MFI
->
getMaxAlignment
(
)
)
;
assert
(
isPowerOf2_32
(
Align
)
&&
"Alignment is not power of 2"
)
;
unsigned
AlignMask
=
Align
1
;
unsigned
maxCallFrameSize
=
MFI
->
getMaxCallFrameSize
(
)
;
if
(
MFI
->
hasVarSizedObjects
(
)
)
maxCallFrameSize
=
(
maxCallFrameSize
+
AlignMask
)
&
~
AlignMask
;
MFI
->
setMaxCallFrameSize
(
maxCallFrameSize
)
;
FrameSize
+=
maxCallFrameSize
;
FrameSize
=
(
FrameSize
+
AlignMask
)
&
~
AlignMask
;
MFI
->
setStackSize
(
FrameSize
)
;
}
</s>

Determine the frame layout but do not update the machine function .

CellSPU
SPU
"Alignment is not power of 2"
1


<s>
bool
PPCDarwinAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
this
->
MF
=
&
MF
;
SetupMachineFunction
(
MF
)
;
O
<<
"\n\n"
;
EmitConstantPool
(
MF
.
getConstantPool
(
)
)
;
const
Function
*
F
=
MF
.
getFunction
(
)
;
OutStreamer
.
SwitchSection
(
getObjFileLowering
(
)
.
SectionForGlobal
(
F
,
Mang
,
TM
)
)
;
switch
(
F
->
getLinkage
(
)
)
{
default
:
llvm_unreachable
(
"Unknown linkage type!"
)
;
case
Function
::
PrivateLinkage
:
case
Function
::
LinkerPrivateLinkage
:
case
Function
::
InternalLinkage
:
break
;
case
Function
::
ExternalLinkage
:
O
<<
"\t.globl\t"
<<
CurrentFnName
<<
'\n'
;
break
;
case
Function
::
WeakAnyLinkage
:
case
Function
::
WeakODRLinkage
:
case
Function
::
LinkOnceAnyLinkage
:
case
Function
::
LinkOnceODRLinkage
:
O
<<
"\t.globl\t"
<<
CurrentFnName
<<
'\n'
;
O
<<
"\t.weak_definition\t"
<<
CurrentFnName
<<
'\n'
;
break
;
}
printVisibility
(
CurrentFnName
,
F
->
getVisibility
(
)
)
;
EmitAlignment
(
MF
.
getAlignment
(
)
,
F
)
;
O
<<
CurrentFnName
<<
":\n"
;
DW
->
BeginFunction
(
&
MF
)
;
MachineFunction
::
iterator
I
=
MF
.
begin
(
)
;
if
(
++
I
==
MF
.
end
(
)
&&
MF
.
front
(
)
.
empty
(
)
)
O
<<
"\tnop\n"
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
I
!=
MF
.
begin
(
)
)
{
printBasicBlockLabel
(
I
,
true
,
true
,
VerboseAsm
)
;
O
<<
'\n'
;
}
for
(
MachineBasicBlock
::
const_iterator
II
=
I
->
begin
(
)
,
IE
=
I
->
end
(
)
;
II
!=
IE
;
++
II
)
{
printMachineInstruction
(
II
)
;
}
}
EmitJumpTableInfo
(
MF
.
getJumpTableInfo
(
)
,
MF
)
;
DW
->
EndFunction
(
&
MF
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .

PowerPC
PPC
"\n\n"
"Unknown linkage type!"
"\t.globl\t"
"\t.globl\t"
"\t.weak_definition\t"
":\n"
"\tnop\n"


"parameter passing for argument of type "

Lay out a function argument using the AAPCS rules . The rule numbers referred to here are those in the AAPCS .


"getBranchTarget21OpValue expects only expressions or immediates"

getBranchTarget21OpValue - Return binary encoding of the branch target operand .


<s> static void eco32_setup_incoming_varargs ( cumulative_args_t cum_v , enum machine_mode mode , tree type , int * pretend_size , int no_rtl ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int first_anon_arg ; if ( no_rtl ) return ; gcc_assert ( mode != BLKmode ) ; if ( targetm . calls . strict_argument_naming ( cum_v ) ) * cum += eco32_num_arg_regs ( mode , type ) ; first_anon_arg = * cum + ECO32_FIRST_ARG_REGNO ; if ( first_anon_arg < ( ECO32_FIRST_ARG_REGNO + ECO32_NUM_ARG_REGS ) ) { int size = ECO32_FIRST_ARG_REGNO + ECO32_NUM_ARG_REGS - first_anon_arg ; rtx regblock ; int offset = ( first_anon_arg - ECO32_FIRST_ARG_REGNO ) * UNITS_PER_WORD ; regblock = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , arg_pointer_rtx , offset ) ) ; move_block_from_reg ( first_anon_arg , regblock , size ) ; * pretend_size = size * UNITS_PER_WORD ; } } </s>

Setup incoming varargs by copying the anonymous argument register into their respective spot on the stack


"Encoding of this operand type is not supported yet."

getMachineOpValue - Return binary encoding of operand .


<s> static enum machine_mode type_natural_mode ( tree type ) { enum machine_mode mode = TYPE_MODE ( type ) ; if ( TREE_CODE ( type ) == VECTOR_TYPE && ! VECTOR_MODE_P ( mode ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; if ( ( size == 8 || size == 16 ) && TYPE_VECTOR_SUBPARTS ( type ) > 1 ) { enum machine_mode innermode = TYPE_MODE ( TREE_TYPE ( type ) ) ; if ( TREE_CODE ( TREE_TYPE ( type ) ) == REAL_TYPE ) mode = MIN_MODE_VECTOR_FLOAT ; else mode = MIN_MODE_VECTOR_INT ; for ( ; mode != VOIDmode ; mode = GET_MODE_WIDER_MODE ( mode ) ) if ( GET_MODE_NUNITS ( mode ) == TYPE_VECTOR_SUBPARTS ( type ) && GET_MODE_INNER ( mode ) == innermode ) return mode ; gcc_unreachable ( ) ; } } return mode ; } </s>

Return the `` natural '' mode for TYPE . In most cases , this is just TYPE_MODE . But in the case of vector types , it is some vector mode . When we have only some of our vector isa extensions enabled , then there are some modes for which vector_mode_supported_p is false . For these modes , the generic vector support in gcc will choose some non-vector mode in order to implement the type . By computing the natural mode , we 'll select the proper ABI location for the operand and not depend on whatever the middle-end decides to do with these vector types .


<s> bool PPCTTIImpl :: enableAggressiveInterleaving ( bool LoopHasReductions ) { if ( ST -> getDarwinDirective ( ) == PPC :: DIR_A2 ) return true ; return LoopHasReductions ; } </s>

Do n't restrict interleaved unrolling to small loops .


<s> rtx m68k_unwrap_symbol ( rtx orig , bool unwrap_reloc32_p ) { return m68k_unwrap_symbol_1 ( orig , unwrap_reloc32_p , NULL ) ; } </s>

Unwrap symbol from UNSPEC_RELOC16 and , if unwrap_reloc32_p , UNSPEC_RELOC32 wrappers .


<s> rtx parallel_element ( rtx parallel_rtx , int nth ) { parallel_rtx = extract_pattern_from_insn ( parallel_rtx ) ; gcc_assert ( GET_CODE ( parallel_rtx ) == PARALLEL ) ; int len = parallel_elements ( parallel_rtx ) ; if ( nth >= 0 ) { if ( nth >= len ) return NULL_RTX ; return XVECEXP ( parallel_rtx , 0 , nth ) ; } else { if ( len + nth < 0 ) return NULL_RTX ; return XVECEXP ( parallel_rtx , 0 , len + nth ) ; } } </s>

Extract an rtx from a parallel rtx with index NTH . If NTH is a negative value , the function returns the last NTH rtx .


<s> const AMDGPUSubtarget & AMDGPUSubtarget :: get ( const TargetMachine & TM , const Function & F ) { if ( TM . getTargetTriple ( ) . getArch ( ) == Triple :: amdgcn ) return static_cast < const AMDGPUSubtarget & > ( TM . getSubtarget < GCNSubtarget > ( F ) ) ; else return static_cast < const AMDGPUSubtarget & > ( TM . getSubtarget < R600Subtarget > ( F ) ) ; } </s>

Get the generated Value for a given VPValue and given Part and Lane .


<s> void MSP430MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; unsigned Size = Desc . getSize ( ) ; Offset = ( ( Desc . TSFlags & MSP430TSFlags :: ExtensionWord ) ? 4 : 2 ) ; uint64_t BinaryOpCode = getBinaryCodeForInstr ( MI , Fixups , STI ) ; if ( Desc . TSFlags & MSP430TSFlags :: ExtensionWord ) BinaryOpCode = fixExtensionWord ( BinaryOpCode ) ; size_t WordCount = Size / 2 ; while ( WordCount -- ) { support :: endian :: write ( OS , ( uint16_t ) BinaryOpCode , support :: little ) ; BinaryOpCode >>= 16 ; } } </s>

Encode the given Inst to bytes and append to CB .


<s>
SDValue
HexagonTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
llvm_unreachable
(
"TLS not implemented for Hexagon."
)
;
case
ISD
::
MEMBARRIER
:
return
LowerMEMBARRIER
(
Op
,
DAG
)
;
case
ISD
::
ATOMIC_FENCE
:
return
LowerATOMIC_FENCE
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGLOBALADDRESS
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
BR_JT
:
return
LowerBR_JT
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
Op
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
INLINEASM
:
return
LowerINLINEASM
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

Hexagon
Hexagon
"Should not custom lower this!"
ISD::ConstantPool
ISD::RETURNADDR
ISD::FRAMEADDR
ISD::GlobalTLSAddress
"TLS not implemented for Hexagon."
ISD::MEMBARRIER
ISD::ATOMIC_FENCE
ISD::GlobalAddress
ISD::VASTART
ISD::BR_JT
ISD::DYNAMIC_STACKALLOC
ISD::SELECT_CC
ISD::SELECT
ISD::INTRINSIC_WO_CHAIN
ISD::INLINEASM


"failed to spill SGPR to VGPR when allocated"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> virtual MVT getScalarShiftAmountTy ( EVT LHSTy ) const { return MVT :: i8 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> bool RISCVAsmBackend :: shouldInsertFixupForCodeAlign ( MCAssembler & Asm , const MCAsmLayout & Layout , MCAlignFragment & AF ) { if ( ! STI . getFeatureBits ( ) [ RISCV :: FeatureRelax ] ) return false ; unsigned Count ; if ( ! shouldInsertExtraNopBytesForCodeAlign ( AF , Count ) || ( Count == 0 ) ) return false ; MCContext & Ctx = Asm . getContext ( ) ; const MCExpr * Dummy = MCConstantExpr :: create ( 0 , Ctx ) ; MCFixup Fixup = MCFixup :: create ( 0 , Dummy , MCFixupKind ( RISCV :: fixup_riscv_align ) , SMLoc ( ) ) ; uint64_t FixedValue = 0 ; MCValue NopBytes = MCValue :: get ( Count ) ; Asm . getWriter ( ) . recordRelocation ( Asm , Layout , & AF , Fixup , NopBytes , FixedValue ) ; return true ; } </s>

Hook which indicates if the target requires a fixup to be generated when handling an align directive in an executable section .


<s>
unsigned
OR1KMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
)
const
{
if
(
MO
.
isReg
(
)
)
return
getOR1KRegisterNumbering
(
MO
.
getReg
(
)
)
;
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
assert
(
MO
.
isExpr
(
)
)
;
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
MCExpr
::
ExprKind
Kind
=
Expr
->
getKind
(
)
;
if
(
Kind
==
MCExpr
::
Binary
)
{
Expr
=
static_cast
<
const
MCBinaryExpr
*
>
(
Expr
)
->
getLHS
(
)
;
Kind
=
Expr
->
getKind
(
)
;
}
assert
(
Kind
==
MCExpr
::
SymbolRef
)
;
OR1K
::
Fixups
FixupKind
=
OR1K
::
Fixups
(
0
)
;
switch
(
cast
<
MCSymbolRefExpr
>
(
Expr
)
->
getKind
(
)
)
{
default
:
llvm_unreachable
(
"Unknown fixup kind!"
)
;
break
;
case
MCSymbolRefExpr
::
VK_None
:
FixupKind
=
OR1K
::
fixup_OR1K_REL26
;
break
;
case
MCSymbolRefExpr
::
VK_OR1K_ABS_HI
:
FixupKind
=
OR1K
::
fixup_OR1K_HI16_INSN
;
break
;
case
MCSymbolRefExpr
::
VK_OR1K_ABS_LO
:
FixupKind
=
OR1K
::
fixup_OR1K_LO16_INSN
;
break
;
case
MCSymbolRefExpr
::
VK_OR1K_PLT
:
FixupKind
=
OR1K
::
fixup_OR1K_PLT26
;
break
;
case
MCSymbolRefExpr
::
VK_OR1K_GOTPCHI
:
FixupKind
=
OR1K
::
fixup_OR1K_GOTPC_HI16
;
break
;
case
MCSymbolRefExpr
::
VK_OR1K_GOTPCLO
:
FixupKind
=
OR1K
::
fixup_OR1K_GOTPC_LO16
;
break
;
case
MCSymbolRefExpr
::
VK_OR1K_GOTOFFHI
:
FixupKind
=
OR1K
::
fixup_OR1K_GOTOFF_HI16
;
break
;
case
MCSymbolRefExpr
::
VK_OR1K_GOTOFFLO
:
FixupKind
=
OR1K
::
fixup_OR1K_GOTOFF_LO16
;
break
;
case
MCSymbolRefExpr
::
VK_OR1K_GOT
:
FixupKind
=
OR1K
::
fixup_OR1K_GOT16
;
break
;
}
Fixups
.
push_back
(
MCFixup
::
Create
(
0
,
MO
.
getExpr
(
)
,
MCFixupKind
(
FixupKind
)
)
)
;
return
0
;
}
</s>


"***** Machine Function before Domain Reassignment *****\n"

"***** Machine Function after Domain Reassignment *****\n"


<s> void AArch64AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( OutStreamer , MI ) ) return ; MCInst TmpInst ; LowerAArch64MachineInstrToMCInst ( MI , TmpInst , * this ) ; OutStreamer . EmitInstruction ( TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( true ) ; } </s>

This method must be called before any actual lowering is done .


<s> iterator end ( ) { return ( Packet . end ( ) ) ; } </s>

Get a const_iterator to the end of the symbol table .


<s> bool ARMFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned CFSize = MFI . getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( 1 << 12 ) - 1 ) / 2 ) return false ; return ! MFI . hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> void AMDGPURegisterBankInfo :: applyMappingImpl ( const OperandsMapper & OpdMapper ) const { return applyDefaultMapping ( OpdMapper ) ; } </s>


<s>
static
bool
use_vfp_abi
(
enum
arm_pcs
pcs_variant
,
bool
is_double
)
{
if
(
pcs_variant
==
ARM_PCS_AAPCS_VFP
)
{
static
bool
seen_thumb1_vfp
=
false
;
if
(
TARGET_THUMB1
&&
!
seen_thumb1_vfp
)
{
sorry
(
"Thumb-1 %<hard-float%> VFP ABI"
)
;
seen_thumb1_vfp
=
true
;
}
return
true
;
}
if
(
pcs_variant
!=
ARM_PCS_AAPCS_LOCAL
)
return
false
;
return
(
TARGET_32BIT
&&
TARGET_HARD_FLOAT
&&
(
TARGET_VFP_DOUBLE
||
!
is_double
)
)
;
}
</s>

Return true if PCS_VARIANT should use VFP registers .


"Unsupported expression operand in assembly source"


<s> static const MachineOperand & getLdStOffsetOp ( const MachineInstr * MI ) { unsigned Idx = isPairedLdSt ( MI ) ? 3 : 2 ; return MI -> getOperand ( Idx ) ; } </s>

Returns the immediate offset operator of a load/store .


<s>
bool
X86AsmPrinter
::
PrintAsmOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
{
if
(
ExtraCode
[
1
]
!=
0
)
return
true
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNo
)
;
switch
(
ExtraCode
[
0
]
)
{
default
:
return
AsmPrinter
::
PrintAsmOperand
(
MI
,
OpNo
,
ExtraCode
,
O
)
;
case
'a'
:
switch
(
MO
.
getType
(
)
)
{
default
:
return
true
;
case
MachineOperand
::
MO_Immediate
:
O
<<
MO
.
getImm
(
)
;
return
false
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
case
MachineOperand
::
MO_JumpTableIndex
:
case
MachineOperand
::
MO_ExternalSymbol
:
llvm_unreachable
(
"unexpected operand type!"
)
;
case
MachineOperand
::
MO_GlobalAddress
:
PrintSymbolOperand
(
MO
,
O
)
;
if
(
Subtarget
->
isPICStyleRIPRel
(
)
)
O
<<
"(%rip)"
;
return
false
;
case
MachineOperand
::
MO_Register
:
O
<<
'('
;
PrintOperand
(
MI
,
OpNo
,
O
)
;
O
<<
')'
;
return
false
;
}
case
'c'
:
switch
(
MO
.
getType
(
)
)
{
default
:
PrintOperand
(
MI
,
OpNo
,
O
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
O
<<
MO
.
getImm
(
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
case
MachineOperand
::
MO_JumpTableIndex
:
case
MachineOperand
::
MO_ExternalSymbol
:
llvm_unreachable
(
"unexpected operand type!"
)
;
case
MachineOperand
::
MO_GlobalAddress
:
PrintSymbolOperand
(
MO
,
O
)
;
break
;
}
return
false
;
case
'A'
:
if
(
MO
.
isReg
(
)
)
{
O
<<
'*'
;
PrintOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
}
return
true
;
case
'b'
:
case
'h'
:
case
'w'
:
case
'k'
:
case
'q'
:
case
'V'
:
if
(
MO
.
isReg
(
)
)
return
printAsmMRegister
(
*
this
,
MO
,
ExtraCode
[
0
]
,
O
)
;
PrintOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
case
'x'
:
case
't'
:
case
'g'
:
if
(
MO
.
isReg
(
)
)
return
printAsmVRegister
(
*
this
,
MO
,
ExtraCode
[
0
]
,
O
)
;
PrintOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
case
'P'
:
PrintPCRelImm
(
MI
,
OpNo
,
O
)
;
return
false
;
case
'n'
:
if
(
MO
.
isImm
(
)
)
{
O
<<
MO
.
getImm
(
)
;
return
false
;
}
O
<<
'-'
;
}
}
PrintOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
}
</s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static rtx mips_force_unary ( machine_mode mode , enum rtx_code code , rtx op0 ) { rtx reg ; reg = gen_reg_rtx ( mode ) ; mips_emit_unary ( code , reg , op0 ) ; return reg ; } </s>

Compute ( CODE OP0 ) and store the result in a new register of mode MODE . Return that new register .


<s> EVT X86TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool NonScalarIntSafe , bool MemcpyStrSrc , SelectionDAG & DAG ) const { const Function * F = DAG . getMachineFunction ( ) . getFunction ( ) ; if ( NonScalarIntSafe && ! F -> hasFnAttr ( Attribute :: NoImplicitFloat ) ) { if ( Size >= 16 && ( Subtarget -> isUnalignedMemAccessFast ( ) || ( ( DstAlign == 0 || DstAlign >= 16 ) && ( SrcAlign == 0 || SrcAlign >= 16 ) ) ) && Subtarget -> getStackAlignment ( ) >= 16 ) { if ( Subtarget -> hasSSE2 ( ) ) return MVT :: v4i32 ; if ( Subtarget -> hasSSE1 ( ) ) return MVT :: v4f32 ; } else if ( ! MemcpyStrSrc && Size >= 8 && ! Subtarget -> is64Bit ( ) && Subtarget -> getStackAlignment ( ) >= 8 && Subtarget -> hasSSE2 ( ) ) { return MVT :: f64 ; } } if ( Subtarget -> is64Bit ( ) && Size >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> EVT MipsTargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s>
TargetTransformInfo
MipsTargetMachine
::
getTargetTransformInfo
(
const
Function
&
F
)
{
if
(
Subtarget
->
allowMixed16_32
(
)
)
{
DEBUG
(
errs
(
)
<<
"No Target Transform Info Pass Added\n"
)
;
return
TargetTransformInfo
(
F
.
getParent
(
)
->
getDataLayout
(
)
)
;
}
DEBUG
(
errs
(
)
<<
"Target Transform Info Pass Added\n"
)
;
return
TargetTransformInfo
(
BasicTTIImpl
(
this
,
F
)
)
;
}
</s>

Get a TargetTransformInfo implementation for the target .

Mips
Mips
"No Target Transform Info Pass Added\n"
"Target Transform Info Pass Added\n"


<s> bool R600InstrInfo :: fitsConstReadLimitations ( const std :: vector < MachineInstr * > & MIs ) const { std :: vector < unsigned > Consts ; SmallSet < int64_t , 4 > Literals ; for ( unsigned i = 0 , n = MIs . size ( ) ; i < n ; i ++ ) { MachineInstr * MI = MIs [ i ] ; if ( ! isALUInstr ( MI -> getOpcode ( ) ) ) continue ; ArrayRef < std :: pair < MachineOperand * , int64_t >> Srcs = getSrcs ( MI ) ; for ( const auto & Src : Srcs ) { if ( Src . first -> getReg ( ) == AMDGPU :: ALU_LITERAL_X ) Literals . insert ( Src . second ) ; if ( Literals . size ( ) > 4 ) return false ; if ( Src . first -> getReg ( ) == AMDGPU :: ALU_CONST ) Consts . push_back ( Src . second ) ; if ( AMDGPU :: R600_KC0RegClass . contains ( Src . first -> getReg ( ) ) || AMDGPU :: R600_KC1RegClass . contains ( Src . first -> getReg ( ) ) ) { unsigned Index = RI . getEncodingValue ( Src . first -> getReg ( ) ) & 0xff ; unsigned Chan = RI . getHWRegChan ( Src . first -> getReg ( ) ) ; Consts . push_back ( ( Index << 2 ) | Chan ) ; } } } return fitsConstReadLimitations ( Consts ) ; } </s>

Same but using const index set instead of MI set .


<s>
const
TargetRegisterClass
*
M68kRegisterInfo
::
getMaximalPhysRegClass
(
unsigned
reg
,
MVT
VT
)
const
{
assert
(
Register
::
isPhysicalRegister
(
reg
)
&&
"reg must be a physical register"
)
;
const
TargetRegisterClass
*
BestRC
=
nullptr
;
for
(
regclass_iterator
I
=
regclass_begin
(
)
,
E
=
regclass_end
(
)
;
I
!=
E
;
++
I
)
{
const
TargetRegisterClass
*
RC
=
*
I
;
if
(
(
VT
==
MVT
::
Other
||
isTypeLegalForClass
(
*
RC
,
VT
)
)
&&
RC
->
contains
(
reg
)
&&
(
!
BestRC
||
(
BestRC
->
hasSubClass
(
RC
)
&&
RC
->
getNumRegs
(
)
>
BestRC
->
getNumRegs
(
)
)
)
)
BestRC
=
RC
;
}
assert
(
BestRC
&&
"Couldn't find the register class"
)
;
return
BestRC
;
}
</s>

Returns the Register Class of a physical register of the given type , picking the biggest register class of the right type that contains this physreg .


"Unrecognized Hexagon processor version"

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool ARMPassConfig :: addPreISel ( ) { if ( ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE ) { bool OnlyOptimizeForSize = ( TM -> getOptLevel ( ) < CodeGenOpt :: Aggressive ) && ( EnableGlobalMerge == cl :: BOU_UNSET ) ; bool MergeExternalByDefault = ! TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ; addPass ( createGlobalMergePass ( TM , 127 , OnlyOptimizeForSize , MergeExternalByDefault ) ) ; } if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createHardwareLoopsPass ( ) ) ; return false ; } </s>


<s> void TargetLoweringObjectFileNaCl :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; StaticCtorSection = getContext ( ) . getELFSection ( ".init_array" , ELF :: SHT_INIT_ARRAY , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; StaticDtorSection = getContext ( ) . getELFSection ( ".fini_array" , ELF :: SHT_FINI_ARRAY , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; } </s>


<s> EVT AArch64TargetLowering :: getSetCCResultType ( const DataLayout & , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>


<s> static void mep_make_parallel ( rtx_insn * insn1 , rtx_insn * insn2 ) { rtx expr ; if ( RTX_FRAME_RELATED_P ( insn2 ) ) { expr = mep_frame_expr ( insn2 ) ; if ( RTX_FRAME_RELATED_P ( insn1 ) ) expr = gen_rtx_SEQUENCE ( VOIDmode , gen_rtvec ( 2 , mep_frame_expr ( insn1 ) , expr ) ) ; set_unique_reg_note ( insn1 , REG_FRAME_RELATED_EXPR , expr ) ; RTX_FRAME_RELATED_P ( insn1 ) = 1 ; } PATTERN ( insn1 ) = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , PATTERN ( insn1 ) , PATTERN ( insn2 ) ) ) ; INSN_CODE ( insn1 ) = - 1 ; } </s>

Merge instructions INSN1 and INSN2 using a PARALLEL . Store the new pattern in INSN1 ; INSN2 will be deleted by the caller .


<s> bool sh_lshrsi_clobbers_t_reg_p ( rtx shift_amount ) { gcc_assert ( CONST_INT_P ( shift_amount ) ) ; const int shift_amount_i = std :: abs ( INTVAL ( shift_amount ) ) & 31 ; if ( shift_amount_i == 31 ) return true ; return ( ashl_lshr_seq [ shift_amount_i ] . clobbers_t & LSHR_CLOBBERS_T ) != 0 ; } </s>

Return true if a logical right shift consisting of 1/2/8/16 shift instructions will clobber the T bit .


"64-bit code requested on a subtarget that doesn't support it!"

This constructor initializes the data members to match that of the specified triple .


<s> BitVector SIRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AMDGPU :: EXEC ) ; Reserved . set ( AMDGPU :: EXEC_LO ) ; Reserved . set ( AMDGPU :: EXEC_HI ) ; Reserved . set ( AMDGPU :: INDIRECT_BASE_ADDR ) ; Reserved . set ( AMDGPU :: FLAT_SCR ) ; Reserved . set ( AMDGPU :: FLAT_SCR_LO ) ; Reserved . set ( AMDGPU :: FLAT_SCR_HI ) ; Reserved . set ( AMDGPU :: VGPR255 ) ; Reserved . set ( AMDGPU :: VGPR254 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; if ( TM . getSubtarget < ARMSubtarget > ( ) . isAAPCS_ABI ( ) ) { StaticCtorSection = getELFSection ( ".init_array" , MCSectionELF :: SHT_INIT_ARRAY , MCSectionELF :: SHF_WRITE | MCSectionELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; StaticDtorSection = getELFSection ( ".fini_array" , MCSectionELF :: SHT_FINI_ARRAY , MCSectionELF :: SHF_WRITE | MCSectionELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; } } </s>

This method must be called before any actual lowering is done .


"Call frame pseudos should only be used for dynamic stack adjustment"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool pdp11_cannot_change_mode_class ( machine_mode from , machine_mode to , enum reg_class rclass ) { if ( FLOAT_MODE_P ( from ) != FLOAT_MODE_P ( to ) ) return true ; return reg_classes_intersect_p ( FPU_REGS , rclass ) ; } </s>


<s> bool Z80InstPrinter :: applyTargetSpecificCLOption ( StringRef Opt ) { return true ; } </s>

Customize the printer according to a command line option .


<s> static void bpf_asm_init_sections ( void ) { if ( TARGET_BPF_CORE ) btf_ext_init ( ) ; } </s>


<s> static bool originalTypeIsF128 ( Type * Ty , const SDNode * CallNode ) { if ( Ty -> isFP128Ty ( ) ) return true ; if ( Ty -> isStructTy ( ) && Ty -> getStructNumElements ( ) == 1 && Ty -> getStructElementType ( 0 ) -> isFP128Ty ( ) ) return true ; const ExternalSymbolSDNode * ES = dyn_cast_or_null < const ExternalSymbolSDNode > ( CallNode ) ; return ( ES && Ty -> isIntegerTy ( 128 ) && isF128SoftLibCall ( ES -> getSymbol ( ) ) ) ; } </s>

This function returns true if Ty is fp128 , { f128 } or i128 which was originally a fp128 .


<s> bool TeeRISCPassConfig :: addInstSelector ( ) { addPass ( createTeeRISCISelDag ( getTeeRISCTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void changingInstr ( MachineInstr & MI ) override { } </s>

This instruction is about to be mutated in some way .


<s> int regs_used ( rtx x , int is_dest ) { enum rtx_code code ; const char * fmt ; int i , used = 0 ; if ( ! x ) return used ; code = GET_CODE ( x ) ; switch ( code ) { case REG : if ( REGNO ( x ) < 16 ) return ( ( ( 1 << HARD_REGNO_NREGS ( 0 , GET_MODE ( x ) ) ) - 1 ) << ( REGNO ( x ) + is_dest ) ) ; return 0 ; case SUBREG : { rtx y = SUBREG_REG ( x ) ; if ( ! REG_P ( y ) ) break ; if ( REGNO ( y ) < 16 ) return ( ( ( 1 << HARD_REGNO_NREGS ( 0 , GET_MODE ( x ) ) ) - 1 ) << ( REGNO ( y ) + subreg_regno_offset ( REGNO ( y ) , GET_MODE ( y ) , SUBREG_BYTE ( x ) , GET_MODE ( x ) ) + is_dest ) ) ; return 0 ; } case SET : return regs_used ( SET_SRC ( x ) , 0 ) | regs_used ( SET_DEST ( x ) , 16 ) ; case RETURN : return 0x00ffff00 ; case CLOBBER : is_dest = 1 ; break ; case MEM : is_dest = 0 ; break ; case CALL : used |= 0x00ff00f0 ; break ; default : break ; } fmt = GET_RTX_FORMAT ( code ) ; for ( i = GET_RTX_LENGTH ( code ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( x , i ) - 1 ; j >= 0 ; j -- ) used |= regs_used ( XVECEXP ( x , i , j ) , is_dest ) ; } else if ( fmt [ i ] == 'e' ) used |= regs_used ( XEXP ( x , i ) , is_dest ) ; } return used ; } </s>

Given a X , a pattern of an insn or a part of it , return a mask of used general registers . Bits 0 .. 15 mean that the respective registers are used as inputs in the instruction . Bits 16 .. 31 mean that the registers 0 .. 15 , respectively , are used as outputs , or are clobbered . IS_DEST should be set to 16 if X is the destination of a SET , else to 0 .


Copy one MODE sized block from SRC to DST , then progress SRC and DST by MODE bytes .


"shouldAssumeDSOLocal gave inconsistent answer"

Classify a global function reference for the current subtarget .


<s> static bool sparc_can_output_mi_thunk ( tree thunk_fndecl ATTRIBUTE_UNUSED , HOST_WIDE_INT delta ATTRIBUTE_UNUSED , HOST_WIDE_INT vcall_offset , tree function ATTRIBUTE_UNUSED ) { return ( vcall_offset >= - 32768 || ! fixed_regs [ 5 ] ) ; } </s>

Return true if sparc_output_mi_thunk would be able to output the assembler code for the thunk function specified by the arguments it is passed , and false otherwise .


<s> static scalar_int_mode sparc_cstore_mode ( enum insn_code icode ATTRIBUTE_UNUSED ) { return ( TARGET_ARCH64 ? DImode : SImode ) ; } </s>


<s> static bool has_inlined_assembly ( function * fn ) { basic_block bb ; gimple_stmt_iterator gsi ; if ( fn -> cfg == NULL ) return true ; FOR_EACH_BB_FN ( bb , fn ) for ( gsi = gsi_start_bb ( bb ) ; ! gsi_end_p ( gsi ) ; gsi_next ( & gsi ) ) if ( gimple_code ( gsi_stmt ( gsi ) ) == GIMPLE_ASM ) return true ; return false ; } </s>

Return true if this function has inline assembly code or if we can not be certain that it does not . False if we know that there is no inline assembly .


<s> enum machine_mode m32c_regno_reg_class ( int regno ) { switch ( regno ) { case R0_REGNO : return R0_REGS ; case R1_REGNO : return R1_REGS ; case R2_REGNO : return R2_REGS ; case R3_REGNO : return R3_REGS ; case A0_REGNO : case A1_REGNO : return A_REGS ; case SB_REGNO : return SB_REGS ; case FB_REGNO : return FB_REGS ; case SP_REGNO : return SP_REGS ; case FLG_REGNO : return FLG_REGS ; default : if ( IS_MEM_REGNO ( regno ) ) return MEM_REGS ; return ALL_REGS ; } } </s>


<s> static HOST_WIDE_INT arm_constant_alignment ( const_tree exp , HOST_WIDE_INT align ) { unsigned int factor = ( TARGET_THUMB || ! arm_tune_xscale ? 1 : 2 ) ; if ( TREE_CODE ( exp ) == STRING_CST && ! optimize_size ) return MAX ( align , BITS_PER_WORD * factor ) ; return align ; } </s>

Implement TARGET_CONSTANT_ALIGNMENT . Make strings word-aligned so strcpy from constants will be faster .


"insertBranch must not be told to insert a fallthrough"

"NVPTX branch conditions have two components!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> static void ix86_conditional_register_usage ( void ) { int i , c_mask ; if ( cfun && cfun -> machine -> no_caller_saved_registers ) for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( ! fixed_regs [ i ] && ! ix86_function_value_regno_p ( i ) ) call_used_regs [ i ] = 0 ; if ( ! TARGET_64BIT ) { for ( i = FIRST_REX_INT_REG ; i <= LAST_REX_INT_REG ; i ++ ) CLEAR_HARD_REG_BIT ( accessible_reg_set , i ) ; for ( i = FIRST_REX_SSE_REG ; i <= LAST_REX_SSE_REG ; i ++ ) CLEAR_HARD_REG_BIT ( accessible_reg_set , i ) ; for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) CLEAR_HARD_REG_BIT ( accessible_reg_set , i ) ; } c_mask = CALL_USED_REGISTERS_MASK ( TARGET_64BIT_MS_ABI ) ; CLEAR_HARD_REG_SET ( reg_class_contents [ ( int ) CLOBBERED_REGS ] ) ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { if ( call_used_regs [ i ] > 1 ) call_used_regs [ i ] = ! ! ( call_used_regs [ i ] & c_mask ) ; if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) GENERAL_REGS ] , i ) && call_used_regs [ i ] ) SET_HARD_REG_BIT ( reg_class_contents [ ( int ) CLOBBERED_REGS ] , i ) ; } if ( ! TARGET_MMX ) accessible_reg_set &= ~ reg_class_contents [ MMX_REGS ] ; if ( ! TARGET_SSE ) accessible_reg_set &= ~ reg_class_contents [ ALL_SSE_REGS ] ; if ( ! ( TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ) ) accessible_reg_set &= ~ reg_class_contents [ FLOAT_REGS ] ; if ( ! TARGET_AVX512F ) { for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) CLEAR_HARD_REG_BIT ( accessible_reg_set , i ) ; accessible_reg_set &= ~ reg_class_contents [ ALL_MASK_REGS ] ; } } </s>

Update register usage after having seen the compiler flags .


"Using .cp. section for writeable object."

Targets should implement this method to assign a section to globals with an explicit section specfied .


<s> void AVRInstrInfo :: insertIndirectBranch ( MachineBasicBlock & MBB , MachineBasicBlock & NewDestBB , MachineBasicBlock & RestoreBB , const DebugLoc & DL , int64_t BrOffset , RegScavenger * RS ) const { BuildMI ( & MBB , DL , get ( AVR :: JMPk ) ) . addMBB ( & NewDestBB ) ; } </s>

Insert an unconditional indirect branch at the end of MBB to NewDestBB .


<s> void SNESTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { Base :: Initialize ( Ctx , TM ) ; } </s>


<s> static void frv_frame_access ( frv_frame_accessor_t * accessor , rtx reg , int stack_offset ) { machine_mode mode = GET_MODE ( reg ) ; rtx mem = frv_frame_mem ( mode , accessor -> base , stack_offset - accessor -> base_offset ) ; if ( accessor -> op == FRV_LOAD ) { if ( SPR_P ( REGNO ( reg ) ) ) { rtx temp = gen_rtx_REG ( mode , TEMP_REGNO ) ; emit_insn ( gen_rtx_SET ( temp , mem ) ) ; emit_insn ( gen_rtx_SET ( reg , temp ) ) ; } else { if ( mode == DImode && GET_CODE ( XEXP ( mem , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( mem , 0 ) , 0 ) ) == REG && GET_CODE ( XEXP ( XEXP ( mem , 0 ) , 1 ) ) == REG ) { rtx temp = gen_rtx_REG ( SImode , TEMP_REGNO ) ; emit_move_insn ( temp , gen_rtx_PLUS ( SImode , XEXP ( XEXP ( mem , 0 ) , 0 ) , XEXP ( XEXP ( mem , 0 ) , 1 ) ) ) ; mem = gen_rtx_MEM ( DImode , temp ) ; } emit_insn ( gen_rtx_SET ( reg , mem ) ) ; } emit_use ( reg ) ; } else { if ( SPR_P ( REGNO ( reg ) ) ) { rtx temp = gen_rtx_REG ( mode , TEMP_REGNO ) ; emit_insn ( gen_rtx_SET ( temp , reg ) ) ; frv_frame_insn ( gen_rtx_SET ( mem , temp ) , frv_dwarf_store ( reg , stack_offset ) ) ; } else if ( mode == DImode ) { rtx reg1 = gen_rtx_REG ( SImode , REGNO ( reg ) ) ; rtx reg2 = gen_rtx_REG ( SImode , REGNO ( reg ) + 1 ) ; rtx set1 = frv_dwarf_store ( reg1 , stack_offset ) ; rtx set2 = frv_dwarf_store ( reg2 , stack_offset + 4 ) ; if ( GET_CODE ( XEXP ( mem , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( mem , 0 ) , 0 ) ) == REG && GET_CODE ( XEXP ( XEXP ( mem , 0 ) , 1 ) ) == REG ) { rtx temp = gen_rtx_REG ( SImode , TEMP_REGNO ) ; emit_move_insn ( temp , gen_rtx_PLUS ( SImode , XEXP ( XEXP ( mem , 0 ) , 0 ) , XEXP ( XEXP ( mem , 0 ) , 1 ) ) ) ; mem = gen_rtx_MEM ( DImode , temp ) ; } frv_frame_insn ( gen_rtx_SET ( mem , reg ) , gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set1 , set2 ) ) ) ; } else frv_frame_insn ( gen_rtx_SET ( mem , reg ) , frv_dwarf_store ( reg , stack_offset ) ) ; } } </s>

Emit instructions that transfer REG to or from the memory location ( sp + STACK_OFFSET ) . The register is stored in memory if ACCESSOR- > OP is FRV_STORE and loaded if it is FRV_LOAD . Only the prologue uses this function to store registers and only the epilogue uses it to load them . The caller sets up ACCESSOR so that BASE is equal to ( sp + BASE_OFFSET ) . The generated instruction will use BASE as its base register . BASE may simply be the stack pointer , but if several accesses are being made to a region far away from the stack pointer , it may be more efficient to set up a temporary instead . Store instructions will be frame-related and will be annotated with the overall effect of the store . Load instructions will be followed by a ( use ) to prevent later optimizations from zapping them . The function takes care of the moves to and from SPRs , using TEMP_REGNO as a temporary in such cases .


<s> static bool arm_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { machine_mode mode ; if ( size == UNITS_PER_WORD && aligned_p ) { fputs ( "\t.word\t" , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; if ( NEED_GOT_RELOC && flag_pic && making_const_table && ( SYMBOL_REF_P ( x ) || LABEL_REF_P ( x ) ) ) { if ( ! arm_pic_data_is_text_relative || ( SYMBOL_REF_P ( x ) && ( ! SYMBOL_REF_LOCAL_P ( x ) || ( SYMBOL_REF_DECL ( x ) ? DECL_WEAK ( SYMBOL_REF_DECL ( x ) ) : 0 ) || ( SYMBOL_REF_FUNCTION_P ( x ) && ! arm_fdpic_local_funcdesc_p ( x ) ) ) ) ) { if ( TARGET_FDPIC && SYMBOL_REF_FUNCTION_P ( x ) ) fputs ( "(GOTFUNCDESC)" , asm_out_file ) ; else fputs ( "(GOT)" , asm_out_file ) ; } else { if ( TARGET_FDPIC && SYMBOL_REF_FUNCTION_P ( x ) ) fputs ( "(GOTOFFFUNCDESC)" , asm_out_file ) ; else { bool is_readonly ; if ( ! TARGET_FDPIC || arm_is_segment_info_known ( x , & is_readonly ) ) fputs ( "(GOTOFF)" , asm_out_file ) ; else fputs ( "(GOT)" , asm_out_file ) ; } } } if ( TARGET_FDPIC && ! making_const_table && SYMBOL_REF_P ( x ) && SYMBOL_REF_FUNCTION_P ( x ) ) fputs ( "(FUNCDESC)" , asm_out_file ) ; fputc ( '\n' , asm_out_file ) ; return true ; } mode = GET_MODE ( x ) ; if ( arm_vector_mode_supported_p ( mode ) ) { int i , units ; gcc_assert ( GET_CODE ( x ) == CONST_VECTOR ) ; units = CONST_VECTOR_NUNITS ( x ) ; size = GET_MODE_UNIT_SIZE ( mode ) ; if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) for ( i = 0 ; i < units ; i ++ ) { rtx elt = CONST_VECTOR_ELT ( x , i ) ; assemble_integer ( elt , size , i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT , 1 ) ; } else for ( i = 0 ; i < units ; i ++ ) { rtx elt = CONST_VECTOR_ELT ( x , i ) ; assemble_real ( * CONST_DOUBLE_REAL_VALUE ( elt ) , as_a < scalar_float_mode > ( GET_MODE_INNER ( mode ) ) , i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT ) ; } return true ; } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . The ARM version needs to handle word-sized values specially .


<s> static bool mips_vector_mode_supported_p ( machine_mode mode ) { switch ( mode ) { case E_V2SFmode : return TARGET_PAIRED_SINGLE_FLOAT ; case E_V2HImode : case E_V4QImode : case E_V2HQmode : case E_V2UHQmode : case E_V2HAmode : case E_V2UHAmode : case E_V4QQmode : case E_V4UQQmode : return TARGET_DSP ; case E_V2SImode : case E_V4HImode : case E_V8QImode : return TARGET_LOONGSON_VECTORS ; default : return MSA_SUPPORTED_MODE_P ( mode ) ; } } </s>

Target hook for vector_mode_supported_p .


<s>
void
MipsRegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
MachineInstr
&
MI
=
*
II
;
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
LLVM_DEBUG
(
errs
(
)
<<
"\nFunction : "
<<
MF
.
getName
(
)
<<
"\n"
;
errs
(
)
<<
"<--------->\n"
<<
MI
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
uint64_t
stackSize
=
MF
.
getFrameInfo
(
)
.
getStackSize
(
)
;
int64_t
spOffset
=
MF
.
getFrameInfo
(
)
.
getObjectOffset
(
FrameIndex
)
;
LLVM_DEBUG
(
errs
(
)
<<
"FrameIndex : "
<<
FrameIndex
<<
"\n"
<<
"spOffset   : "
<<
spOffset
<<
"\n"
<<
"stackSize  : "
<<
stackSize
<<
"\n"
<<
"alignment  : "
<<
MF
.
getFrameInfo
(
)
.
getObjectAlignment
(
FrameIndex
)
<<
"\n"
)
;
eliminateFI
(
MI
,
FIOperandNum
,
FrameIndex
,
stackSize
,
spOffset
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .

Mips
Mips
"\nFunction : "
"\n"
"<--------->\n"
"FrameIndex : "
"\n"
"spOffset   : "
"\n"
"stackSize  : "
"\n"
"alignment  : "
"\n"


<s>
bool
X86InstrInfo
::
expandPostRAPseudo
(
MachineBasicBlock
::
iterator
MI
)
const
{
bool
HasAVX
=
Subtarget
.
hasAVX
(
)
;
MachineInstrBuilder
MIB
(
*
MI
->
getParent
(
)
->
getParent
(
)
,
MI
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
X86
::
MOV32r0
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
XOR32rr
)
)
;
case
X86
::
MOV32r1
:
return
expandMOV32r1
(
MIB
,
*
this
,
false
)
;
case
X86
::
MOV32r_1
:
return
expandMOV32r1
(
MIB
,
*
this
,
true
)
;
case
X86
::
SETB_C8r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB8rr
)
)
;
case
X86
::
SETB_C16r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB16rr
)
)
;
case
X86
::
SETB_C32r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB32rr
)
)
;
case
X86
::
SETB_C64r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB64rr
)
)
;
case
X86
::
V_SET0
:
case
X86
::
FsFLD0SS
:
case
X86
::
FsFLD0SD
:
return
Expand2AddrUndef
(
MIB
,
get
(
HasAVX
X86
::
VXORPSrr
:
X86
::
XORPSrr
)
)
;
case
X86
::
AVX_SET0
:
assert
(
HasAVX
&&
"AVX not supported"
)
;
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VXORPSYrr
)
)
;
case
X86
::
AVX512_512_SET0
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VPXORDZrr
)
)
;
case
X86
::
V_SETALLONES
:
return
Expand2AddrUndef
(
MIB
,
get
(
HasAVX
X86
::
VPCMPEQDrr
:
X86
::
PCMPEQDrr
)
)
;
case
X86
::
AVX2_SETALLONES
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VPCMPEQDYrr
)
)
;
case
X86
::
TEST8ri_NOREX
:
MI
->
setDesc
(
get
(
X86
::
TEST8ri
)
)
;
return
true
;
case
X86
::
MOV32ri64
:
MI
->
setDesc
(
get
(
X86
::
MOV32ri
)
)
;
return
true
;
case
X86
::
KSET0B
:
case
X86
::
KSET0W
:
return
Expand2AddrKreg
(
MIB
,
get
(
X86
::
KXORWrr
)
,
X86
::
K0
)
;
case
X86
::
KSET0D
:
return
Expand2AddrKreg
(
MIB
,
get
(
X86
::
KXORDrr
)
,
X86
::
K0
)
;
case
X86
::
KSET0Q
:
return
Expand2AddrKreg
(
MIB
,
get
(
X86
::
KXORQrr
)
,
X86
::
K0
)
;
case
X86
::
KSET1B
:
case
X86
::
KSET1W
:
return
Expand2AddrKreg
(
MIB
,
get
(
X86
::
KXNORWrr
)
,
X86
::
K0
)
;
case
X86
::
KSET1D
:
return
Expand2AddrKreg
(
MIB
,
get
(
X86
::
KXNORDrr
)
,
X86
::
K0
)
;
case
X86
::
KSET1Q
:
return
Expand2AddrKreg
(
MIB
,
get
(
X86
::
KXNORQrr
)
,
X86
::
K0
)
;
case
TargetOpcode
::
LOAD_STACK_GUARD
:
expandLoadStackGuard
(
MIB
,
*
this
)
;
return
true
;
}
return
false
;
}
</s>

This function is called for all pseudo instructions that remain after register allocation .


<s>
static
void
rs6000_sched_finish
(
FILE
*
dump
,
int
sched_verbose
)
{
int
n_groups
;
if
(
sched_verbose
)
fprintf
(
dump
,
"=== Finishing schedule.\n"
)
;
if
(
reload_completed
&&
rs6000_sched_groups
)
{
if
(
sel_sched_p
(
)
)
return
;
if
(
rs6000_sched_insert_nops
==
sched_finish_none
)
return
;
if
(
rs6000_sched_insert_nops
==
sched_finish_pad_groups
)
n_groups
=
pad_groups
(
dump
,
sched_verbose
,
current_sched_info
->
prev_head
,
current_sched_info
->
next_tail
)
;
else
n_groups
=
redefine_groups
(
dump
,
sched_verbose
,
current_sched_info
->
prev_head
,
current_sched_info
->
next_tail
)
;
if
(
sched_verbose
>=
6
)
{
fprintf
(
dump
,
"ngroups = %d\n"
,
n_groups
)
;
print_rtl
(
dump
,
current_sched_info
->
prev_head
)
;
fprintf
(
dump
,
"Done finish_sched\n"
)
;
}
}
}
</s>

The following function is called at the end of scheduling BB . After reload , it inserts nops at insn group bundling .


<s> MipsSubtarget :: MipsSubtarget ( const std :: string & TT , const std :: string & FS , bool little ) : MipsArchVersion ( Mips1 ) , MipsABI ( O32 ) , IsLittle ( little ) , IsSingleFloat ( false ) , IsFP64bit ( false ) , IsGP64bit ( false ) , HasVFPU ( false ) , IsLinux ( true ) , HasSEInReg ( false ) , HasCondMov ( false ) , HasMulDivAdd ( false ) , HasMinMax ( false ) , HasSwap ( false ) , HasBitCount ( false ) { std :: string CPU = "mips1" ; MipsArchVersion = Mips1 ; ParseSubtargetFeatures ( FS , CPU ) ; if ( TT . find ( "linux" ) == std :: string :: npos ) IsLinux = false ; if ( TT . find ( "mipsallegrex" ) != std :: string :: npos || TT . find ( "psp" ) != std :: string :: npos ) { MipsABI = EABI ; IsSingleFloat = true ; MipsArchVersion = Mips2 ; HasVFPU = true ; HasSEInReg = true ; HasBitCount = true ; HasSwap = true ; HasCondMov = true ; } } </s>

This constructor initializes the data members to match that of the specified triple .

Mips Mips Mips Mips Mips Mips "mips1" Mips Mips "linux" "mipsallegrex" "psp" Mips Mips Mips


<s> const PPCSubtarget * PPCTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) FS += FS . empty ( ) ? "-hard-float" : ",-hard-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < PPCSubtarget > ( TargetTriple , CPU , computeFSAdditions ( FS , getOptLevel ( ) , getTargetTriple ( ) ) , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

PowerPC PPC PPC "target-cpu" "target-features" "use-soft-float" "true" "-hard-float" ",-hard-float" PPC


<s>
MipsSubtarget
&
MipsSubtarget
::
initializeSubtargetDependencies
(
StringRef
CPU
,
StringRef
FS
,
const
TargetMachine
&
TM
)
{
std
::
string
CPUName
=
MIPS_MC
::
selectMipsCPU
(
TM
.
getTargetTriple
(
)
,
CPU
)
;
ParseSubtargetFeatures
(
CPUName
,
FS
)
;
InstrItins
=
getInstrItineraryForCPU
(
CPUName
)
;
if
(
InMips16Mode
&&
!
IsSoftFloat
)
InMips16HardFloat
=
true
;
if
(
StackAlignOverride
)
stackAlignment
=
*
StackAlignOverride
;
else
if
(
isABI_N32
(
)
||
isABI_N64
(
)
)
stackAlignment
=
Align
(
16
)
;
else
{
assert
(
isABI_O32
(
)
&&
"Unknown ABI for stack alignment!"
)
;
stackAlignment
=
Align
(
8
)
;
}
return
*
this
;
}
</s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .

Mips
Mips
Mips
MIPS_MC::selectMipsCPU
Mips
Mips
16
"Unknown ABI for stack alignment!"
8


<s> int mcore_initial_elimination_offset ( int from , int to ) { int above_frame ; int below_frame ; struct mcore_frame fi ; layout_mcore_frame ( & fi ) ; above_frame = fi . local_size + fi . pad_local + fi . reg_size + fi . pad_reg ; below_frame = fi . outbound_size + fi . pad_outbound ; if ( from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM ) return above_frame ; if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) return above_frame + below_frame ; if ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) return below_frame ; gcc_unreachable ( ) ; } </s>

Define the offset between two registers , one to be eliminated , and the other its replacement , at the start of a routine .


<s> void NVPTXPassConfig :: addPostRegAlloc ( ) { addPass ( createNVPTXPrologEpilogPass ( ) , false ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createNVPTXPeephole ( ) ) ; } } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s>
Value
*
PPCTargetLowering
::
emitMaskedAtomicRMWIntrinsic
(
IRBuilderBase
&
Builder
,
AtomicRMWInst
*
AI
,
Value
*
AlignedAddr
,
Value
*
Incr
,
Value
*
Mask
,
Value
*
ShiftAmt
,
AtomicOrdering
Ord
)
const
{
assert
(
EnableQuadwordAtomics
&&
Subtarget
.
hasQuadwordAtomics
(
)
&&
"Only support quadword now"
)
;
Module
*
M
=
Builder
.
GetInsertBlock
(
)
->
getParent
(
)
->
getParent
(
)
;
Type
*
ValTy
=
Incr
->
getType
(
)
;
assert
(
ValTy
->
getPrimitiveSizeInBits
(
)
==
128
)
;
Function
*
RMW
=
Intrinsic
::
getDeclaration
(
M
,
getIntrinsicForAtomicRMWBinOp128
(
AI
->
getOperation
(
)
)
)
;
Type
*
Int64Ty
=
Type
::
getInt64Ty
(
M
->
getContext
(
)
)
;
Value
*
IncrLo
=
Builder
.
CreateTrunc
(
Incr
,
Int64Ty
,
"incr_lo"
)
;
Value
*
IncrHi
=
Builder
.
CreateTrunc
(
Builder
.
CreateLShr
(
Incr
,
64
)
,
Int64Ty
,
"incr_hi"
)
;
Value
*
Addr
=
Builder
.
CreateBitCast
(
AlignedAddr
,
Type
::
getInt8PtrTy
(
M
->
getContext
(
)
)
)
;
Value
*
LoHi
=
Builder
.
CreateCall
(
RMW
,
{
Addr
,
IncrLo
,
IncrHi
}
)
;
Value
*
Lo
=
Builder
.
CreateExtractValue
(
LoHi
,
0
,
"lo"
)
;
Value
*
Hi
=
Builder
.
CreateExtractValue
(
LoHi
,
1
,
"hi"
)
;
Lo
=
Builder
.
CreateZExt
(
Lo
,
ValTy
,
"lo64"
)
;
Hi
=
Builder
.
CreateZExt
(
Hi
,
ValTy
,
"hi64"
)
;
return
Builder
.
CreateOr
(
Lo
,
Builder
.
CreateShl
(
Hi
,
ConstantInt
::
get
(
ValTy
,
64
)
)
,
"val64"
)
;
}
</s>

Perform a masked atomicrmw using a target-specific intrinsic .


<s> SDValue AMDGPUTargetLowering :: SplitVectorLoad ( const SDValue & Op , SelectionDAG & DAG ) const { LoadSDNode * Load = dyn_cast < LoadSDNode > ( Op ) ; EVT MemEltVT = Load -> getMemoryVT ( ) . getVectorElementType ( ) ; EVT EltVT = Op . getValueType ( ) . getVectorElementType ( ) ; EVT PtrVT = Load -> getBasePtr ( ) . getValueType ( ) ; unsigned NumElts = Load -> getMemoryVT ( ) . getVectorNumElements ( ) ; SmallVector < SDValue , 8 > Loads ; SDLoc SL ( Op ) ; for ( unsigned i = 0 , e = NumElts ; i != e ; ++ i ) { SDValue Ptr = DAG . getNode ( ISD :: ADD , SL , PtrVT , Load -> getBasePtr ( ) , DAG . getConstant ( i * ( MemEltVT . getSizeInBits ( ) / 8 ) , PtrVT ) ) ; Loads . push_back ( DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , EltVT , Load -> getChain ( ) , Ptr , MachinePointerInfo ( Load -> getMemOperand ( ) -> getValue ( ) ) , MemEltVT , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> getAlignment ( ) ) ) ; } return DAG . getNode ( ISD :: BUILD_VECTOR , SL , Op . getValueType ( ) , Loads . data ( ) , Loads . size ( ) ) ; } </s>

Split a vector load into 2 loads of half the vector .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; if ( getOptLevel ( ) <= EnableGlobalISelAtO ) setGlobalISel ( true ) ; } </s>


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
AArch64
::
NumTargetFixupKinds
]
=
{
{
"fixup_aarch64_pcrel_adr_imm21"
,
0
,
32
,
PCRelFlagVal
}
,
{
"fixup_aarch64_pcrel_adrp_imm21"
,
0
,
32
,
PCRelFlagVal
}
,
{
"fixup_aarch64_add_imm12"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldst_imm12_scale1"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldst_imm12_scale2"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldst_imm12_scale4"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldst_imm12_scale8"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldst_imm12_scale16"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldr_pcrel_imm19"
,
5
,
19
,
PCRelFlagVal
}
,
{
"fixup_aarch64_movw"
,
5
,
16
,
0
}
,
{
"fixup_aarch64_pcrel_branch14"
,
5
,
14
,
PCRelFlagVal
}
,
{
"fixup_aarch64_pcrel_branch19"
,
5
,
19
,
PCRelFlagVal
}
,
{
"fixup_aarch64_pcrel_branch26"
,
0
,
26
,
PCRelFlagVal
}
,
{
"fixup_aarch64_pcrel_call26"
,
0
,
26
,
PCRelFlagVal
}
,
{
"fixup_aarch64_tlsdesc_call"
,
0
,
0
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> void from_compare ( rtx * operands , int code ) { enum machine_mode mode = GET_MODE ( sh_compare_op0 ) ; rtx insn ; if ( mode == VOIDmode ) mode = GET_MODE ( sh_compare_op1 ) ; if ( code != EQ || mode == DImode || ( TARGET_SH2E && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) ) { sh_compare_op0 = force_reg ( mode , sh_compare_op0 ) ; if ( sh_compare_op1 != const0_rtx || code == GTU || code == GEU || ( TARGET_SH2E && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) ) sh_compare_op1 = force_reg ( mode , sh_compare_op1 ) ; } if ( TARGET_SH2E && GET_MODE_CLASS ( mode ) == MODE_FLOAT && code == GE ) { from_compare ( operands , GT ) ; insn = gen_ieee_ccmpeqsf_t ( sh_compare_op0 , sh_compare_op1 ) ; } else insn = gen_rtx_SET ( VOIDmode , gen_rtx_REG ( SImode , T_REG ) , gen_rtx_fmt_ee ( code , SImode , sh_compare_op0 , sh_compare_op1 ) ) ; if ( ( TARGET_SH4 || TARGET_SH2A ) && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , insn , gen_rtx_USE ( VOIDmode , get_fpscr_rtx ( ) ) ) ) ; ( mode == SFmode ? emit_sf_insn : emit_df_insn ) ( insn ) ; } else emit_insn ( insn ) ; } </s>

Called from the md file , set up the operands of a compare instruction .


<s> void tilegx_expand_set_const64 ( rtx op0 , rtx op1 ) { if ( CONST_INT_P ( op1 ) ) { expand_set_cint64 ( op0 , op1 ) ; } else { rtx temp = create_temp_reg_if_possible ( Pmode , op0 ) ; if ( TARGET_32BIT ) { emit_insn ( gen_mov_address_32bit_step1 ( temp , op1 ) ) ; emit_insn ( gen_mov_address_32bit_step2 ( op0 , temp , op1 ) ) ; } else { rtx temp2 = create_temp_reg_if_possible ( Pmode , op0 ) ; emit_insn ( gen_mov_address_step1 ( temp , op1 ) ) ; emit_insn ( gen_mov_address_step2 ( temp2 , temp , op1 ) ) ; emit_insn ( gen_mov_address_step3 ( op0 , temp2 , op1 ) ) ; } } } </s>

Load OP1 , a 64-bit constant , into OP0 , a register . We know it ca n't be done in one insn when we get here , the move expander guarantees this .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MemoryDependenceWrapperPass > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> unsigned ARMBaseInstrInfo :: getInstrLatency ( const InstrItineraryData * ItinData , const MachineInstr & MI , unsigned * PredCost ) const { if ( MI . isCopyLike ( ) || MI . isInsertSubreg ( ) || MI . isRegSequence ( ) || MI . isImplicitDef ( ) ) return 1 ; if ( MI . isBundle ( ) ) { unsigned Latency = 0 ; MachineBasicBlock :: const_instr_iterator I = MI . getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI . getParent ( ) -> instr_end ( ) ; while ( ++ I != E && I -> isInsideBundle ( ) ) { if ( I -> getOpcode ( ) != ARM :: t2IT ) Latency += getInstrLatency ( ItinData , * I , PredCost ) ; } return Latency ; } const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( PredCost && ( MCID . isCall ( ) || MCID . hasImplicitDefOfPhysReg ( ARM :: CPSR ) ) ) { * PredCost = 1 ; } if ( ! ItinData ) return MI . mayLoad ( ) ? 3 : 1 ; unsigned Class = MCID . getSchedClass ( ) ; if ( ! ItinData -> isEmpty ( ) && ItinData -> getNumMicroOps ( Class ) < 0 ) return getNumMicroOps ( ItinData , MI ) ; unsigned Latency = ItinData -> getStageLatency ( Class ) ; unsigned DefAlign = MI . hasOneMemOperand ( ) ? ( * MI . memoperands_begin ( ) ) -> getAlignment ( ) : 0 ; int Adj = adjustDefLatency ( Subtarget , MI , MCID , DefAlign ) ; if ( Adj >= 0 || ( int ) Latency > - Adj ) { return Latency + Adj ; } return Latency ; } </s>

Compute the instruction latency of a given instruction .


<s> bool HexagonPassConfig :: addPreRegAlloc ( ) { if ( ! DisableHardwareLoops ) { PM -> add ( createHexagonHardwareLoops ( ) ) ; } return false ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> void mips_move_integer ( rtx temp , rtx dest , unsigned HOST_WIDE_INT value ) { struct mips_integer_op codes [ MIPS_MAX_INTEGER_OPS ] ; machine_mode mode ; unsigned int i , num_ops ; rtx x ; mode = GET_MODE ( dest ) ; num_ops = mips_build_integer ( codes , value ) ; x = GEN_INT ( codes [ 0 ] . value ) ; for ( i = 1 ; i < num_ops ; i ++ ) { if ( ! can_create_pseudo_p ( ) ) { emit_insn ( gen_rtx_SET ( temp , x ) ) ; x = temp ; } else x = force_reg ( mode , x ) ; x = gen_rtx_fmt_ee ( codes [ i ] . code , mode , x , GEN_INT ( codes [ i ] . value ) ) ; } emit_insn ( gen_rtx_SET ( dest , x ) ) ; } </s>


<s> static bool rs6000_global_entry_point_needed_p ( void ) { if ( DEFAULT_ABI != ABI_ELFv2 ) return false ; if ( TARGET_SINGLE_PIC_BASE ) return false ; if ( cfun -> is_thunk ) return true ; return cfun -> machine -> r2_setup_needed ; } </s>

Return whether we need to emit an ELFv2 global entry point prologue .


<s> void cris_order_for_addsi3 ( rtx * operands , int n ) { if ( ! REG_P ( operands [ n ] ) ) { rtx tem = operands [ n ] ; operands [ n ] = operands [ n + 1 ] ; operands [ n + 1 ] = tem ; } } </s>

Make sure operands are in the right order for an addsi3 insn as generated by a define_split . A MEM as the first operand is n't recognized by addsi3 after reload . OPERANDS contains the operands , with the first at OPERANDS [ N ] and the second at OPERANDS [ N+1 ] .


<s> static rtx nios2_legitimize_tls_address ( rtx loc ) { rtx tmp , mem , tp ; enum tls_model model = SYMBOL_REF_TLS_MODEL ( loc ) ; switch ( model ) { case TLS_MODEL_GLOBAL_DYNAMIC : tmp = gen_reg_rtx ( Pmode ) ; emit_move_insn ( tmp , nios2_got_address ( loc , UNSPEC_ADD_TLS_GD ) ) ; return nios2_call_tls_get_addr ( tmp ) ; case TLS_MODEL_LOCAL_DYNAMIC : tmp = gen_reg_rtx ( Pmode ) ; emit_move_insn ( tmp , nios2_got_address ( loc , UNSPEC_ADD_TLS_LDM ) ) ; return gen_rtx_PLUS ( Pmode , nios2_call_tls_get_addr ( tmp ) , nios2_unspec_offset ( loc , UNSPEC_ADD_TLS_LDO ) ) ; case TLS_MODEL_INITIAL_EXEC : tmp = gen_reg_rtx ( Pmode ) ; mem = gen_const_mem ( Pmode , nios2_got_address ( loc , UNSPEC_LOAD_TLS_IE ) ) ; emit_move_insn ( tmp , mem ) ; tp = gen_rtx_REG ( Pmode , TP_REGNO ) ; return gen_rtx_PLUS ( Pmode , tp , tmp ) ; case TLS_MODEL_LOCAL_EXEC : tp = gen_rtx_REG ( Pmode , TP_REGNO ) ; return gen_rtx_PLUS ( Pmode , tp , nios2_unspec_offset ( loc , UNSPEC_ADD_TLS_LE ) ) ; default : gcc_unreachable ( ) ; } } </s>

Generate the code to access LOC , a thread local SYMBOL_REF . The return value will be a valid address and move_operand ( either a REG or a LO_SUM ) .


<s> static void loongarch_emit_int_compare ( enum rtx_code * code , rtx * op0 , rtx * op1 ) { static const enum rtx_code mag_comparisons [ ] [ 2 ] = { { LEU , LTU } , { GTU , GEU } , { LE , LT } , { GT , GE } } ; if ( splittable_const_int_operand ( * op1 , VOIDmode ) ) { HOST_WIDE_INT rhs = INTVAL ( * op1 ) ; if ( * code == EQ || * code == NE ) { if ( IMM12_OPERAND ( - rhs ) ) { * op0 = loongarch_force_binary ( GET_MODE ( * op0 ) , PLUS , * op0 , GEN_INT ( - rhs ) ) ; * op1 = const0_rtx ; } } else { for ( size_t i = 0 ; i < ARRAY_SIZE ( mag_comparisons ) ; i ++ ) { HOST_WIDE_INT new_rhs ; bool increment = * code == mag_comparisons [ i ] [ 0 ] ; bool decrement = * code == mag_comparisons [ i ] [ 1 ] ; if ( ! increment && ! decrement ) continue ; new_rhs = rhs + ( increment ? 1 : - 1 ) ; if ( loongarch_integer_cost ( new_rhs ) < loongarch_integer_cost ( rhs ) && ( rhs < 0 ) == ( new_rhs < 0 ) ) { * op1 = GEN_INT ( new_rhs ) ; * code = mag_comparisons [ i ] [ increment ] ; } break ; } } } loongarch_extend_comparands ( * code , op0 , op1 ) ; * op0 = force_reg ( word_mode , * op0 ) ; if ( * op1 != const0_rtx ) * op1 = force_reg ( word_mode , * op1 ) ; } </s>

Convert a comparison into something that can be used in a branch . On entry , * OP0 and * OP1 are the values being compared and * CODE is the code used to compare them . Update them to describe the final comparison .


<s> static bool s390_hard_regno_scratch_ok ( unsigned int regno ) { if ( GENERAL_REGNO_P ( regno ) && ! call_really_used_regs [ regno ] && cfun_gpr_save_slot ( regno ) == 0 ) return false ; return true ; } </s>

Return nonzero if register REGNO can be used as a scratch register in peephole2 .


<s> static bool v850_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { return int_size_in_bytes ( type ) > 8 || TYPE_MODE ( type ) == BLKmode || ( ( ! TARGET_GCC_ABI ) && AGGREGATE_TYPE_P ( type ) ) ; } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


"Checking if value is in small-data, -G"

Return true if this global address should be placed into small data/bss section .


<s>
bool
RISCVInstrInfo
::
verifyInstruction
(
const
MachineInstr
&
MI
,
StringRef
&
ErrInfo
)
const
{
const
MCInstrInfo
*
MCII
=
STI
.
getInstrInfo
(
)
;
MCInstrDesc
const
&
Desc
=
MCII
->
get
(
MI
.
getOpcode
(
)
)
;
for
(
auto
&
OI
:
enumerate
(
Desc
.
operands
(
)
)
)
{
unsigned
OpType
=
OI
.
value
(
)
.
OperandType
;
if
(
OpType
>=
RISCVOp
::
OPERAND_FIRST_RISCV_IMM
&&
OpType
<=
RISCVOp
::
OPERAND_LAST_RISCV_IMM
)
{
const
MachineOperand
&
MO
=
MI
.
getOperand
(
OI
.
index
(
)
)
;
if
(
MO
.
isImm
(
)
)
{
int64_t
Imm
=
MO
.
getImm
(
)
;
bool
Ok
;
switch
(
OpType
)
{
default
:
llvm_unreachable
(
"Unexpected operand type"
)
;
case
RISCVOp
::
OPERAND_UIMM4
:
Ok
=
isUInt
<
4
>
(
Imm
)
;
break
;
case
RISCVOp
::
OPERAND_UIMM5
:
Ok
=
isUInt
<
5
>
(
Imm
)
;
break
;
case
RISCVOp
::
OPERAND_UIMM12
:
Ok
=
isUInt
<
12
>
(
Imm
)
;
break
;
case
RISCVOp
::
OPERAND_SIMM12
:
Ok
=
isInt
<
12
>
(
Imm
)
;
break
;
case
RISCVOp
::
OPERAND_UIMM20
:
Ok
=
isUInt
<
20
>
(
Imm
)
;
break
;
case
RISCVOp
::
OPERAND_UIMMLOG2XLEN
:
if
(
STI
.
getTargetTriple
(
)
.
isArch64Bit
(
)
)
Ok
=
isUInt
<
6
>
(
Imm
)
;
else
Ok
=
isUInt
<
5
>
(
Imm
)
;
break
;
}
if
(
!
Ok
)
{
ErrInfo
=
"Invalid immediate"
;
return
false
;
}
}
}
}
return
true
;
}
</s>

Perform target-specific instruction verification .


<s> static void arm_init_builtin ( unsigned int fcode , arm_builtin_datum * d , const char * prefix ) { bool print_type_signature_p = false ; char type_signature [ SIMD_MAX_BUILTIN_ARGS ] = { 0 } ; char namebuf [ 60 ] ; tree ftype = NULL ; tree fndecl = NULL ; d -> fcode = fcode ; int op_num = insn_data [ d -> code ] . n_operands - 1 ; int arg_num = d -> qualifiers [ 0 ] & qualifier_void ? op_num + 1 : op_num ; tree return_type = void_type_node , args = void_list_node ; tree eltype ; for ( ; op_num >= 0 ; arg_num -- , op_num -- ) { machine_mode op_mode = insn_data [ d -> code ] . operand [ op_num ] . mode ; enum arm_type_qualifiers qualifiers = d -> qualifiers [ arg_num ] ; if ( qualifiers & qualifier_unsigned ) { type_signature [ arg_num ] = 'u' ; print_type_signature_p = true ; } else if ( qualifiers & qualifier_poly ) { type_signature [ arg_num ] = 'p' ; print_type_signature_p = true ; } else type_signature [ arg_num ] = 's' ; if ( qualifiers & qualifier_internal ) continue ; if ( qualifiers & qualifier_map_mode ) op_mode = d -> mode ; if ( qualifiers & qualifier_predicate ) op_mode = HImode ; if ( qualifiers & qualifier_pointer && VECTOR_MODE_P ( op_mode ) ) op_mode = GET_MODE_INNER ( op_mode ) ; if ( qualifiers & qualifier_void_pointer ) eltype = qualifiers & qualifier_const ? const_ptr_type_node : ptr_type_node ; else { eltype = arm_simd_builtin_type ( op_mode , qualifiers ) ; gcc_assert ( eltype != NULL ) ; if ( qualifiers & qualifier_const ) eltype = build_qualified_type ( eltype , TYPE_QUAL_CONST ) ; if ( qualifiers & qualifier_pointer ) eltype = build_pointer_type ( eltype ) ; } if ( arg_num == 0 ) return_type = eltype ; else args = tree_cons ( NULL_TREE , eltype , args ) ; } ftype = build_function_type ( return_type , args ) ; gcc_assert ( ftype != NULL ) ; if ( print_type_signature_p && IN_RANGE ( fcode , ARM_BUILTIN_VFP_BASE , ARM_BUILTIN_ACLE_BASE - 1 ) ) snprintf ( namebuf , sizeof ( namebuf ) , "%s_%s_%s" , prefix , d -> name , type_signature ) ; else snprintf ( namebuf , sizeof ( namebuf ) , "%s_%s" , prefix , d -> name ) ; fndecl = add_builtin_function ( namebuf , ftype , fcode , BUILT_IN_MD , NULL , NULL_TREE ) ; arm_builtin_decls [ fcode ] = fndecl ; } </s>

Set up a builtin . It will use information stored in the argument struct D to derive the builtin 's type signature and name . It will append the name in D to the PREFIX passed and use these to create a builtin declaration that is then stored in 'arm_builtin_decls ' under index FCODE . This FCODE is also written back to D for future use .


<s> bool AMDGPUTTIImpl :: isSourceOfDivergence ( const Value * V ) const { if ( const Argument * A = dyn_cast < Argument > ( V ) ) return ! isArgPassedInSGPR ( A ) ; if ( const LoadInst * Load = dyn_cast < LoadInst > ( V ) ) return Load -> getPointerAddressSpace ( ) == AMDGPUAS :: PRIVATE_ADDRESS ; if ( isa < AtomicRMWInst > ( V ) || isa < AtomicCmpXchgInst > ( V ) ) return true ; if ( const IntrinsicInst * Intrinsic = dyn_cast < IntrinsicInst > ( V ) ) { const TargetMachine & TM = getTLI ( ) -> getTargetMachine ( ) ; return isIntrinsicSourceOfDivergence ( TM . getIntrinsicInfo ( ) , Intrinsic ) ; } if ( isa < CallInst > ( V ) || isa < InvokeInst > ( V ) ) return true ; return false ; } </s>

Returns whether V is a source of divergence .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < RISCVSubtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> unsigned MipsSEInstrInfo :: loadImmediate ( int64_t Imm , MachineBasicBlock & MBB , MachineBasicBlock :: iterator II , const DebugLoc & DL , unsigned * NewImm ) const { MipsAnalyzeImmediate AnalyzeImm ; const MipsSubtarget & STI = Subtarget ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; unsigned Size = STI . isABI_N64 ( ) ? 64 : 32 ; unsigned LUi = STI . isABI_N64 ( ) ? Mips :: LUi64 : Mips :: LUi ; unsigned ZEROReg = STI . isABI_N64 ( ) ? Mips :: ZERO_64 : Mips :: ZERO ; const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; bool LastInstrIsADDiu = NewImm ; const MipsAnalyzeImmediate :: InstSeq & Seq = AnalyzeImm . Analyze ( Imm , Size , LastInstrIsADDiu ) ; MipsAnalyzeImmediate :: InstSeq :: const_iterator Inst = Seq . begin ( ) ; assert ( Seq . size ( ) && ( ! LastInstrIsADDiu || ( Seq . size ( ) > 1 ) ) ) ; Register Reg = RegInfo . createVirtualRegister ( RC ) ; if ( Inst -> Opc == LUi ) BuildMI ( MBB , II , DL , get ( LUi ) , Reg ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; else BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , Reg ) . addReg ( ZEROReg ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; for ( ++ Inst ; Inst != Seq . end ( ) - LastInstrIsADDiu ; ++ Inst ) BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; if ( LastInstrIsADDiu ) * NewImm = Inst -> ImmOpnd ; return Reg ; } </s>

Emit a series of instructions to load an immediate .


<s>
const
TargetRegisterClass
*
SNESRegisterInfo
::
getLargestLegalSuperClass
(
const
TargetRegisterClass
*
RC
,
const
MachineFunction
&
MF
)
const
{
const
TargetRegisterInfo
*
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
if
(
TRI
->
isTypeLegalForClass
(
*
RC
,
MVT
::
i16
)
)
{
return
&
SNES
::
MainRegsRegClass
;
}
llvm_unreachable
(
"Invalid register size"
)
;
}
</s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .

SNES
SNES
MVT::i16
SNES::MainRegsRegClass
"Invalid register size"


<s> SDValue MCS51TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; if ( CallConv == CallingConv :: MCS51_BUILTIN ) { CCInfo . AnalyzeCallResult ( Ins , RetCC_MCS51_BUILTIN ) ; } else { analyzeReturnValues ( Ins , CCInfo ) ; } for ( CCValAssign const & RVLoc : RVLocs ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLoc . getLocReg ( ) , RVLoc . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static int frv_memory_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t rclass ATTRIBUTE_UNUSED , bool in ATTRIBUTE_UNUSED ) { return 4 ; } </s>

Worker function for TARGET_MEMORY_MOVE_COST .


<s>
void
ARMAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
unsigned
Kind
=
Fixup
.
getKind
(
)
;
if
(
Kind
>=
FirstLiteralRelocationKind
)
return
;
unsigned
NumBytes
=
getFixupKindNumBytes
(
Kind
)
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
Value
=
adjustFixupValue
(
Asm
,
Fixup
,
Target
,
Value
,
IsResolved
,
Ctx
,
STI
)
;
if
(
!
Value
)
return
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
unsigned
FullSizeBytes
;
if
(
Endian
==
support
::
big
)
{
FullSizeBytes
=
getFixupKindContainerSizeBytes
(
Kind
)
;
assert
(
(
Offset
+
FullSizeBytes
)
<=
Data
.
size
(
)
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FullSizeBytes
&&
"Invalid fixup size!"
)
;
}
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
Endian
==
support
::
little
i
:
(
FullSizeBytes
1
i
)
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> const TargetRegisterClass * M680x0RegisterInfo :: intRegClass ( unsigned size ) const { return & M680x0 :: DR32RegClass ; } </s>


<s>
StringRef
AMDGPUIntrinsicInfo
::
getName
(
unsigned
IntrID
,
ArrayRef
<
Type
*
>
Tys
)
const
{
if
(
IntrID
<
Intrinsic
::
num_intrinsics
)
return
StringRef
(
)
;
assert
(
IntrID
<
SIIntrinsic
::
num_AMDGPU_intrinsics
&&
"Invalid intrinsic ID"
)
;
return
IntrinsicNameTable
[
IntrID
Intrinsic
::
num_intrinsics
]
;
}
</s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> bool X86AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < X86Subtarget > ( ) ; SMShadowTracker . startFunction ( MF ) ; CodeEmitter . reset ( TM . getTarget ( ) . createMCCodeEmitter ( * Subtarget -> getInstrInfo ( ) , MF . getContext ( ) ) ) ; EmitFPOData = Subtarget -> isTargetWin32 ( ) && MF . getMMI ( ) . getModule ( ) -> getCodeViewFlag ( ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Local = MF . getFunction ( ) . hasLocalLinkage ( ) ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Local ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } emitFunctionBody ( ) ; emitXRayTable ( ) ; EmitFPOData = false ; return false ; } </s>


<s> static bool sh_legitimize_address_displacement ( rtx * disp , rtx * offs , machine_mode mode ) { if ( ( TARGET_FPU_DOUBLE && mode == DFmode ) || ( TARGET_SH2E && mode == SFmode ) ) return false ; struct disp_adjust adj = sh_find_mov_disp_adjust ( mode , INTVAL ( * disp ) ) ; if ( adj . offset_adjust != NULL_RTX && adj . mov_disp != NULL_RTX ) { * disp = adj . mov_disp ; * offs = adj . offset_adjust ; return true ; } return false ; } </s>

Return true if DISP can be legitimized .


<s> int HexagonMCInstrInfo :: getMaxValue ( MCInstrInfo const & MCII , MCInst const & MCI ) { uint64_t const F = HexagonMCInstrInfo :: getDesc ( MCII , MCI ) . TSFlags ; unsigned isSigned = ( F >> HexagonII :: ExtentSignedPos ) & HexagonII :: ExtentSignedMask ; unsigned bits = ( F >> HexagonII :: ExtentBitsPos ) & HexagonII :: ExtentBitsMask ; if ( isSigned ) return ~ ( - 1U << ( bits - 1 ) ) ; else return ~ ( - 1U << bits ) ; } </s>

Return the maximal unsigned value possible given these KnownBits .

Hexagon Hexagon Hexagon HexagonII::ExtentSignedPos HexagonII::ExtentSignedMask HexagonII::ExtentBitsPos HexagonII::ExtentBitsMask 1U 1 1U


<s> char * aarch64_output_sve_cnt_pat_immediate ( const char * prefix , const char * operands , rtx * cnt_pat ) { aarch64_svpattern pattern = ( aarch64_svpattern ) INTVAL ( cnt_pat [ 0 ] ) ; unsigned int nelts_per_vq = INTVAL ( cnt_pat [ 1 ] ) ; unsigned int factor = INTVAL ( cnt_pat [ 2 ] ) * nelts_per_vq ; return aarch64_output_sve_cnt_immediate ( prefix , operands , pattern , factor , nelts_per_vq ) ; } </s>

Return the asm string for an instruction with a CNT-like vector size operand ( a vector pattern followed by a multiplier in the range [ 1 , 16 ] ) . PREFIX is the mnemonic without the size suffix and OPERANDS is the first part of the operands template ( the part that comes before the vector size itself ) . CNT_PAT [ 0 .. 2 ] are the operands of the UNSPEC_SVE_CNT_PAT ; see aarch64_sve_cnt_pat for details .


<s> static inline void aarch64_adjust_sve_callee_save_base ( machine_mode mode , rtx & base_rtx , rtx & anchor_reg , poly_int64 & offset , rtx & ptrue ) { if ( maybe_ge ( offset , 8 * GET_MODE_SIZE ( mode ) ) ) { poly_int64 anchor_offset = 16 * GET_MODE_SIZE ( mode ) ; if ( ! anchor_reg ) { anchor_reg = gen_rtx_REG ( Pmode , STACK_CLASH_SVE_CFA_REGNUM ) ; emit_insn ( gen_add3_insn ( anchor_reg , base_rtx , gen_int_mode ( anchor_offset , Pmode ) ) ) ; } base_rtx = anchor_reg ; offset -= anchor_offset ; } if ( ! ptrue ) { int pred_reg = cfun -> machine -> frame . spare_pred_reg ; emit_move_insn ( gen_rtx_REG ( VNx16BImode , pred_reg ) , CONSTM1_RTX ( VNx16BImode ) ) ; ptrue = gen_rtx_REG ( VNx2BImode , pred_reg ) ; } } </s>

The caller is going to use ST1D or LD1D to save or restore an SVE register in mode MODE at BASE_RTX + OFFSET , where OFFSET is in the range [ 1 , 16 ] * GET_MODE_SIZE ( MODE ) . Prepare for this by : ( 1 ) updating BASE_RTX + OFFSET so that it is a legitimate ST1D or LD1D address ( 2 ) setting PRED to a valid predicate register for the ST1D or LD1D , if the variable is n't already nonnull ( 1 ) is needed when OFFSET is in the range [ 8 , 16 ] * GET_MODE_SIZE ( MODE ) . Handle this case using a temporary base register that is suitable for all offsets in that range . Use ANCHOR_REG as this base register if it is nonnull , otherwise create a new register and store it in ANCHOR_REG .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
X86
::
NumTargetFixupKinds
]
=
{
{
"reloc_riprel_4byte"
,
0
,
4
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_movq_load"
,
0
,
4
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_signed_4byte"
,
0
,
4
*
8
,
0
}
,
{
"reloc_global_offset_table"
,
0
,
4
*
8
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> static bool ix86_unordered_fp_compare ( enum rtx_code code ) { if ( ! TARGET_IEEE_FP ) return false ; switch ( code ) { case GT : case GE : case LT : case LE : return false ; case EQ : case NE : case LTGT : case UNORDERED : case ORDERED : case UNLT : case UNLE : case UNGT : case UNGE : case UNEQ : return true ; default : gcc_unreachable ( ) ; } } </s>

Figure out whether to use unordered fp comparisons .


<s> FastISel * PPC :: createFastISel ( FunctionLoweringInfo & FuncInfo , const TargetLibraryInfo * LibInfo ) { const PPCSubtarget & Subtarget = FuncInfo . MF -> getSubtarget < PPCSubtarget > ( ) ; if ( Subtarget . isPPC64 ( ) && Subtarget . isSVR4ABI ( ) ) return new PPCFastISel ( FuncInfo , LibInfo ) ; return nullptr ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .

PowerPC PPC::createFastISel PPC PPC PPC PPC


<s> void P2AsmPrinter :: emitFunctionBodyEnd ( ) { } </s>

Targets can override this to emit stuff after the last basic block in the function .


<s> unsigned MipsOptimizePICCall :: getReg ( ValueType Entry ) { unsigned Reg = ScopedHT . lookup ( Entry ) . second ; assert ( Reg ) ; return Reg ; } </s>

Returns the register associated with this edge .


<s>
void
SPUInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
)
const
{
unsigned
opc
;
bool
isValidFrameIdx
=
(
FrameIdx
<
SPUFrameInfo
::
maxFrameOffset
(
)
)
;
if
(
RC
==
SPU
::
GPRCRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr128
:
SPU
::
STQXr128
)
;
}
else
if
(
RC
==
SPU
::
R64CRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr64
:
SPU
::
STQXr64
)
;
}
else
if
(
RC
==
SPU
::
R64FPRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr64
:
SPU
::
STQXr64
)
;
}
else
if
(
RC
==
SPU
::
R32CRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr32
:
SPU
::
STQXr32
)
;
}
else
if
(
RC
==
SPU
::
R32FPRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr32
:
SPU
::
STQXr32
)
;
}
else
if
(
RC
==
SPU
::
R16CRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr16
:
SPU
::
STQXr16
)
;
}
else
if
(
RC
==
SPU
::
R8CRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr8
:
SPU
::
STQXr8
)
;
}
else
if
(
RC
==
SPU
::
VECREGRegisterClass
)
{
opc
=
(
isValidFrameIdx
)
SPU
::
STQDv16i8
:
SPU
::
STQXv16i8
;
}
else
{
llvm_unreachable
(
"Unknown regclass!"
)
;
}
DebugLoc
DL
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
opc
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
,
FrameIdx
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> static long ppc_linux_aux_vector ( long which ) { extern long * __libc_stack_end ; long argc ; char * * argv ; char * * envp ; struct auxv { long a_type ; long a_val ; } * auxp ; argc = __libc_stack_end [ 0 ] ; argv = ( char * * ) __libc_stack_end + 1 ; envp = argv + argc + 1 ; while ( * envp ++ ) continue ; for ( auxp = ( struct auxv * ) envp ; auxp -> a_type != 0 ; ++ auxp ) if ( auxp -> a_type == which ) return auxp -> a_val ; return 0 ; } </s>

Find an entry in the process auxiliary vector . The canonical way to test for VMX is to look at AT_HWCAP .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"AMDGPU IR optimizations"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static bool ix86_contains_aligned_value_p ( const_tree type ) { machine_mode mode = TYPE_MODE ( type ) ; if ( mode == XFmode || mode == XCmode ) return false ; if ( TYPE_ALIGN ( type ) < 128 ) return false ; if ( AGGREGATE_TYPE_P ( type ) ) { switch ( TREE_CODE ( type ) ) { case RECORD_TYPE : case UNION_TYPE : case QUAL_UNION_TYPE : { tree field ; for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) == FIELD_DECL && ix86_contains_aligned_value_p ( TREE_TYPE ( field ) ) ) return true ; } break ; } case ARRAY_TYPE : if ( ix86_contains_aligned_value_p ( TREE_TYPE ( type ) ) ) return true ; break ; default : gcc_unreachable ( ) ; } } else return TYPE_ALIGN ( type ) >= 128 ; return false ; } </s>

Return true when TYPE should be 128bit aligned for 32bit argument passing ABI .


<s> void MipsAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const { MCFixupKind Kind = Fixup . getKind ( ) ; MCContext & Ctx = Asm . getContext ( ) ; Value = adjustFixupValue ( Fixup , Value , Ctx ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { case FK_Data_2 : case Mips :: fixup_Mips_16 : case Mips :: fixup_MICROMIPS_PC10_S1 : FullSize = 2 ; break ; case FK_Data_8 : case Mips :: fixup_Mips_64 : FullSize = 8 ; break ; case FK_Data_4 : default : FullSize = 4 ; break ; } uint64_t CurVal = 0 ; bool microMipsLEByteOrder = needsMMLEByteOrder ( ( unsigned ) Kind ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = Endian == support :: little ? ( microMipsLEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - 1 - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = Endian == support :: little ? ( microMipsLEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>


"Handling of TOC entry displacement larger than 32767 "

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> bool SIAnnotateControlFlow :: runOnFunction ( Function & F ) { DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; for ( df_iterator < BasicBlock * > I = df_begin ( & F . getEntryBlock ( ) ) , E = df_end ( & F . getEntryBlock ( ) ) ; I != E ; ++ I ) { BranchInst * Term = dyn_cast < BranchInst > ( ( * I ) -> getTerminator ( ) ) ; if ( ! Term || Term -> isUnconditional ( ) ) { if ( isTopOfStack ( * I ) ) closeControlFlow ( * I ) ; continue ; } if ( I . nodeVisited ( Term -> getSuccessor ( 1 ) ) ) { if ( isTopOfStack ( * I ) ) closeControlFlow ( * I ) ; handleLoop ( Term ) ; continue ; } if ( isTopOfStack ( * I ) ) { PHINode * Phi = dyn_cast < PHINode > ( Term -> getCondition ( ) ) ; if ( Phi && Phi -> getParent ( ) == * I && isElse ( Phi ) ) { insertElse ( Term ) ; eraseIfUnused ( Phi ) ; continue ; } closeControlFlow ( * I ) ; } openIf ( Term ) ; } assert ( Stack . empty ( ) ) ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( ! skipFunction ( MF . getFunction ( ) ) ) { initialize ( MF ) ; return processAtomicInsts ( ) ; } return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool avr_hard_regno_scratch_ok ( unsigned int regno ) { if ( ( cfun -> machine -> is_interrupt || cfun -> machine -> is_signal ) && ! df_regs_ever_live_p ( regno ) ) return false ; if ( ( ! reload_completed || frame_pointer_needed ) && ( regno == REG_Y || regno == REG_Y + 1 ) ) { return false ; } return true ; } </s>

Returns true if SCRATCH are safe to be allocated as a scratch registers ( for a define_peephole2 ) in the current function .


<s>
void
mmix_output_register_setting
(
FILE
*
stream
,
int
regno
,
int64_t
value
,
int
do_begin_end
)
{
if
(
do_begin_end
)
fprintf
(
stream
,
"\t"
)
;
if
(
insn_const_int_ok_for_constraint
(
value
,
CONSTRAINT_K
)
)
fprintf
(
stream
,
"NEGU %s,0,%"
PRId64
,
reg_names
[
regno
]
,
value
)
;
else
if
(
mmix_shiftable_wyde_value
(
(
uint64_t
)
value
)
)
{
mmix_output_shiftvalue_op_from_str
(
stream
,
"SET"
,
(
uint64_t
)
value
)
;
fprintf
(
stream
,
" %s,"
,
reg_names
[
regno
]
)
;
mmix_output_shifted_value
(
stream
,
(
uint64_t
)
value
)
;
}
else
if
(
mmix_shiftable_wyde_value
(
(
uint64_t
)
value
)
)
{
mmix_output_shiftvalue_op_from_str
(
stream
,
"SET"
,
(
uint64_t
)
value
)
;
fprintf
(
stream
,
" %s,"
,
reg_names
[
regno
]
)
;
mmix_output_shifted_value
(
stream
,
(
uint64_t
)
value
)
;
fprintf
(
stream
,
"\n\tNEGU %s,0,%s"
,
reg_names
[
regno
]
,
reg_names
[
regno
]
)
;
}
else
if
(
mmix_shiftable_wyde_value
(
~
(
uint64_t
)
value
)
)
{
mmix_output_shiftvalue_op_from_str
(
stream
,
"SET"
,
~
(
uint64_t
)
value
)
;
fprintf
(
stream
,
" %s,"
,
reg_names
[
regno
]
)
;
mmix_output_shifted_value
(
stream
,
~
(
uint64_t
)
value
)
;
fprintf
(
stream
,
"\n\tNOR %s,%s,0"
,
reg_names
[
regno
]
,
reg_names
[
regno
]
)
;
}
else
{
static
const
char
*
const
higher_parts
[
]
=
{
"L"
,
"ML"
,
"MH"
,
"H"
}
;
const
char
*
op
=
"SET"
;
const
char
*
line_begin
=
""
;
int
insns
=
0
;
int
i
;
int64_t
tmpvalue
=
value
;
for
(
i
=
0
;
i
<
4
&&
tmpvalue
!=
0
;
i
++
)
{
if
(
tmpvalue
&
65535
)
insns
++
;
tmpvalue
>>=
16
;
}
if
(
TARGET_BASE_ADDRESSES
&&
insns
==
3
)
{
fprintf
(
stream
,
"LDA %s,"
,
reg_names
[
regno
]
)
;
mmix_output_octa
(
stream
,
value
,
0
)
;
}
else
{
for
(
i
=
0
;
i
<
4
&&
value
!=
0
;
i
++
)
{
if
(
value
&
65535
)
{
fprintf
(
stream
,
"%s%s%s %s,#%x"
,
line_begin
,
op
,
higher_parts
[
i
]
,
reg_names
[
regno
]
,
(
int
)
(
value
&
65535
)
)
;
op
=
"INC"
;
line_begin
=
"\n\t"
;
}
value
>>=
16
;
}
}
}
if
(
do_begin_end
)
fprintf
(
stream
,
"\n"
)
;
}
</s>

Output an optimal sequence for setting a register to a specific constant . Used in an alternative for const_ints in movdi , and when using large stack-frame offsets . Use do_begin_end to say if a line-starting TAB and newline before the first insn and after the last insn is wanted .


<s> static rtx nios2_large_got_address ( rtx offset , rtx tmp ) { if ( ! tmp ) tmp = gen_reg_rtx ( Pmode ) ; emit_move_insn ( tmp , offset ) ; return gen_rtx_PLUS ( Pmode , tmp , pic_offset_table_rtx ) ; } </s>

Generate GOT pointer based address with large offset .


<s> void function_builder :: add_unique_function ( const function_instance & instance , tree return_type , vec < tree > & argument_types , uint64_t required_extensions , bool force_direct_overloads ) { char * name = get_name ( instance , false ) ; tree fntype = build_function_type_array ( return_type , argument_types . length ( ) , argument_types . address ( ) ) ; tree attrs = get_attributes ( instance ) ; registered_function & rfn = add_function ( instance , name , fntype , attrs , required_extensions , false ) ; hashval_t hash = instance . hash ( ) ; registered_function * * rfn_slot = function_table -> find_slot_with_hash ( instance , hash , INSERT ) ; gcc_assert ( ! * rfn_slot ) ; * rfn_slot = & rfn ; if ( m_direct_overloads || force_direct_overloads ) { char * overload_name = get_name ( instance , true ) ; if ( strcmp ( name , overload_name ) != 0 ) { tree attrs = get_attributes ( instance ) ; add_function ( instance , overload_name , fntype , attrs , required_extensions , false ) ; } } obstack_free ( & m_string_obstack , name ) ; } </s>

Add a built-in function for INSTANCE , with the argument types given by ARGUMENT_TYPES and the return type given by RETURN_TYPE . NAME is the `` full '' name for C function . OVERLOAD_NAME is the `` short '' name for C++ overloaded function . OVERLOAD_NAME can be nullptr because some instance does n't have C++ overloaded function .


<s> unsigned ARMBaseRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) return FramePtr ; return ARM :: SP ; } </s>


<s> const Nios2RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool HexagonTargetLowering :: IsEligibleForTailCallOptimization ( SDValue Callee , CallingConv :: ID CalleeCC , bool isVarArg , bool isCalleeStructRet , bool isCallerStructRet , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SmallVectorImpl < ISD :: InputArg > & Ins , SelectionDAG & DAG ) const { const Function * CallerF = DAG . getMachineFunction ( ) . getFunction ( ) ; CallingConv :: ID CallerCC = CallerF -> getCallingConv ( ) ; bool CCMatch = CallerCC == CalleeCC ; if ( ! ( dyn_cast < GlobalAddressSDNode > ( Callee ) ) && ! ( dyn_cast < ExternalSymbolSDNode > ( Callee ) ) ) { return false ; } if ( ! CCMatch ) return false ; if ( isVarArg ) return false ; if ( isCalleeStructRet || isCallerStructRet ) return false ; return true ; } </s>

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization .

Hexagon Hexagon ISD::OutputArg ISD::InputArg


<s>
const
char
*
nds32_output_casesi_pc_relative
(
rtx
*
operands
)
{
machine_mode
mode
;
rtx
diff_vec
;
diff_vec
=
PATTERN
(
NEXT_INSN
(
as_a
<
rtx_insn
*
>
(
operands
[
1
]
)
)
)
;
gcc_assert
(
GET_CODE
(
diff_vec
)
==
ADDR_DIFF_VEC
)
;
output_asm_insn
(
"la\t$ta, %l1"
,
operands
)
;
mode
=
GET_MODE
(
diff_vec
)
;
switch
(
mode
)
{
case
QImode
:
output_asm_insn
(
"lb\t%2, [$ta + %0 << 0]"
,
operands
)
;
break
;
case
HImode
:
output_asm_insn
(
"lh\t%2, [$ta + %0 << 1]"
,
operands
)
;
break
;
case
SImode
:
output_asm_insn
(
"lw\t%2, [$ta + %0 << 2]"
,
operands
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
output_asm_insn
(
"add\t$ta, %2, $ta"
,
operands
)
;
if
(
TARGET_16_BIT
)
return
"jr5\t$ta"
;
else
return
"jr\t$ta"
;
}
</s>

Function to generate PC relative jump table . Refer to nds32.md for more details . The following is the sample for the case that diff value can be presented in '.short ' size . addi $ r1 , $ r1 , - ( case_lower_bound ) slti $ ta , $ r1 , ( case_number ) beqz $ ta , .L_skip_label la $ ta , .L35 ! get jump table address lh $ r1 , [ $ ta + $ r1 < < 1 ] ! load symbol diff from jump table entry addi $ ta , $ r1 , $ ta jr5 $ ta ! jump table entry L35 : .short .L25-.L35 .short .L26-.L35 .short .L27-.L35 .short .L28-.L35 .short .L29-.L35 .short .L30-.L35 .short .L31-.L35 .short .L32-.L35 .short .L33-.L35 .short .L34-.L35


<s> const XCoreInstrInfo * getInstrInfo ( ) const override { return getSubtargetImpl ( ) -> getInstrInfo ( ) ; } </s>


<s> static unsigned int compute_saved_regs ( void ) { unsigned int saved_regs = 0 ; int regno ; for ( regno = 0 ; regno <= HARD_FRAME_POINTER_REGNUM ; regno ++ ) { if ( WORD_REG_USED ( regno ) ) saved_regs |= 1 << regno ; } if ( frame_pointer_needed ) saved_regs &= ~ ( 1 << HARD_FRAME_POINTER_REGNUM ) ; return saved_regs ; } </s>

Compute which registers to push/pop . Return a bit vector of registers .


<s> const char * msp430_propagate_region_opt ( int argc , const char * * argv ) { if ( strcmp ( argv [ 0 ] , "lower" ) != 0 ) return argv [ 0 ] ; else if ( ( argc == 2 ) && ( strcmp ( argv [ 1 ] , "-muse-lower-region-prefix" ) == 0 ) ) return argv [ 0 ] ; return "none" ; } </s>

Spec function . Propagate -m { code , data } -region= to the linker , unless the lower region has been specified without -muse-lower-region-prefix also being used .


<s> size_t getSize ( ) const { return sizeof ( * this ) + alignTo ( namesz , ALIGN ) + alignTo ( descsz , ALIGN ) ; } </s>

Return the number of bytes in the encoding of this instruction , or zero if the encoding size can not be known from the opcode .


<s> bool s390_function_arg_vector ( machine_mode mode , const_tree type ) { if ( ! TARGET_VX_ABI ) return false ; if ( s390_function_arg_size ( mode , type ) > 16 ) return false ; if ( ! type ) return VECTOR_MODE_P ( mode ) ; while ( TREE_CODE ( type ) == RECORD_TYPE ) { tree field , single = NULL_TREE ; for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( single == NULL_TREE ) single = TREE_TYPE ( field ) ; else return false ; } if ( single == NULL_TREE ) return false ; else { if ( int_size_in_bytes ( single ) <= 0 || int_size_in_bytes ( single ) != int_size_in_bytes ( type ) ) return false ; type = single ; } } return VECTOR_TYPE_P ( type ) ; } </s>

Return true if a function argument of type TYPE and mode MODE is to be passed in a vector register , if available .


<s> bool AArch64InstrInfo :: analyzeCompare ( const MachineInstr * MI , unsigned & SrcReg , unsigned & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case AArch64 :: SUBSWrr : case AArch64 :: SUBSWrs : case AArch64 :: SUBSWrx : case AArch64 :: SUBSXrr : case AArch64 :: SUBSXrs : case AArch64 :: SUBSXrx : case AArch64 :: ADDSWrr : case AArch64 :: ADDSWrs : case AArch64 :: ADDSWrx : case AArch64 :: ADDSXrr : case AArch64 :: ADDSXrs : case AArch64 :: ADDSXrx : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; SrcReg2 = MI -> getOperand ( 2 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case AArch64 :: SUBSWri : case AArch64 :: ADDSWri : case AArch64 :: SUBSXri : case AArch64 :: ADDSXri : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = MI -> getOperand ( 2 ) . getImm ( ) ; return true ; case AArch64 :: ANDSWri : case AArch64 :: ANDSXri : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = AArch64_AM :: decodeLogicalImmediate ( MI -> getOperand ( 2 ) . getImm ( ) , MI -> getOpcode ( ) == AArch64 :: ANDSWri ? 32 : 64 ) ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> static const char * sparc_mangle_type ( const_tree type ) { if ( ! TARGET_64BIT && TYPE_MAIN_VARIANT ( type ) == long_double_type_node && TARGET_LONG_DOUBLE_128 ) return "g" ; return NULL ; } </s>


<s> bool isReg ( RegisterKind RegKind ) const { return Kind == KindReg && Reg . Kind == RegKind ; } </s>


<s> CCAssignFn * ARMTargetLowering :: CCAssignFnForCall ( CallingConv :: ID CC , bool isVarArg ) const { return CCAssignFnForNode ( CC , false , isVarArg ) ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> bool SIFoldOperands :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; MRI = & MF . getRegInfo ( ) ; ST = & MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST -> getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; bool IsIEEEMode = MFI -> getMode ( ) . IEEE ; bool HasNSZ = MFI -> hasNoSignedZerosFPMath ( ) ; for ( MachineBasicBlock * MBB : depth_first ( & MF ) ) { MachineBasicBlock :: iterator I , Next ; MachineOperand * CurrentKnownM0Val = nullptr ; for ( I = MBB -> begin ( ) ; I != MBB -> end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; tryFoldInst ( TII , & MI ) ; if ( ! TII -> isFoldableCopy ( MI ) ) { if ( CurrentKnownM0Val && MI . modifiesRegister ( AMDGPU :: M0 , TRI ) ) CurrentKnownM0Val = nullptr ; if ( IsIEEEMode || ( ! HasNSZ && ! MI . getFlag ( MachineInstr :: FmNsz ) ) || ! tryFoldOMod ( MI ) ) tryFoldClamp ( MI ) ; continue ; } if ( MI . getOperand ( 0 ) . getReg ( ) == AMDGPU :: M0 ) { MachineOperand & NewM0Val = MI . getOperand ( 1 ) ; if ( CurrentKnownM0Val && CurrentKnownM0Val -> isIdenticalTo ( NewM0Val ) ) { MI . eraseFromParent ( ) ; continue ; } CurrentKnownM0Val = ( NewM0Val . isReg ( ) && NewM0Val . getReg ( ) . isPhysical ( ) ) ? nullptr : & NewM0Val ; continue ; } MachineOperand & OpToFold = MI . getOperand ( 1 ) ; bool FoldingImm = OpToFold . isImm ( ) || OpToFold . isFI ( ) || OpToFold . isGlobal ( ) ; if ( ! FoldingImm && ! OpToFold . isReg ( ) ) continue ; if ( OpToFold . isReg ( ) && ! Register :: isVirtualRegister ( OpToFold . getReg ( ) ) ) continue ; MachineOperand & Dst = MI . getOperand ( 0 ) ; if ( Dst . isReg ( ) && ! Register :: isVirtualRegister ( Dst . getReg ( ) ) ) continue ; foldInstOperand ( MI , OpToFold ) ; } } return true ; } </s>


<s> void X86PassConfig :: addPreRegAlloc ( ) { addPass ( createX86FixupSetCC ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createX86OptimizeLEAs ( ) ) ; addPass ( createX86CallFrameOptimization ( ) ) ; addPass ( createX86WinAllocaExpander ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> bool PPCInstrInfo :: analyzeCompare ( const MachineInstr & MI , unsigned & SrcReg , unsigned & SrcReg2 , int & Mask , int & Value ) const { unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { default : return false ; case PPC :: CMPWI : case PPC :: CMPLWI : case PPC :: CMPDI : case PPC :: CMPLDI : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; Value = MI . getOperand ( 2 ) . getImm ( ) ; Mask = 0xFFFF ; return true ; case PPC :: CMPW : case PPC :: CMPLW : case PPC :: CMPD : case PPC :: CMPLD : case PPC :: FCMPUS : case PPC :: FCMPUD : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 2 ) . getReg ( ) ; return true ; } } </s>

PowerPC PPC PPC::CMPWI PPC::CMPLWI PPC::CMPDI PPC::CMPLDI 1 0 2 0xFFFF PPC::CMPW PPC::CMPLW PPC::CMPD PPC::CMPLD PPC::FCMPUS PPC::FCMPUD 1 2


Commutes the operands in the given instruction by changing the operands order and/or changing the instruction 's opcode and/or the immediate value operand .


<s> static unsigned int rs6000_hard_regno_nregs_hook ( unsigned int regno , machine_mode mode ) { return rs6000_hard_regno_nregs [ mode ] [ regno ] ; } </s>


<s> unsigned SparcInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == SP :: LDri || MI -> getOpcode ( ) == SP :: LDXri || MI -> getOpcode ( ) == SP :: LDFri || MI -> getOpcode ( ) == SP :: LDDFri ) { if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .