<s>
bool
X86InstrInfo
::
expandPostRAPseudo
(
MachineBasicBlock
::
iterator
MI
)
const
{
bool
HasAVX
=
Subtarget
.
hasAVX
(
)
;
MachineInstrBuilder
MIB
(
*
MI
->
getParent
(
)
->
getParent
(
)
,
MI
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
X86
::
MOV32r0
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
XOR32rr
)
)
;
case
X86
::
SETB_C8r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB8rr
)
)
;
case
X86
::
SETB_C16r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB16rr
)
)
;
case
X86
::
SETB_C32r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB32rr
)
)
;
case
X86
::
SETB_C64r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB64rr
)
)
;
case
X86
::
V_SET0
:
case
X86
::
FsFLD0SS
:
case
X86
::
FsFLD0SD
:
return
Expand2AddrUndef
(
MIB
,
get
(
HasAVX
X86
::
VXORPSrr
:
X86
::
XORPSrr
)
)
;
case
X86
::
AVX_SET0
:
assert
(
HasAVX
&&
"AVX not supported"
)
;
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VXORPSYrr
)
)
;
case
X86
::
AVX512_512_SET0
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VPXORDZrr
)
)
;
case
X86
::
V_SETALLONES
:
return
Expand2AddrUndef
(
MIB
,
get
(
HasAVX
X86
::
VPCMPEQDrr
:
X86
::
PCMPEQDrr
)
)
;
case
X86
::
AVX2_SETALLONES
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VPCMPEQDYrr
)
)
;
case
X86
::
TEST8ri_NOREX
:
MI
->
setDesc
(
get
(
X86
::
TEST8ri
)
)
;
return
true
;
case
X86
::
KSET0B
:
case
X86
::
KSET0W
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
KXORWrr
)
)
;
case
X86
::
KSET1B
:
case
X86
::
KSET1W
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
KXNORWrr
)
)
;
case
TargetOpcode
::
LOAD_STACK_GUARD
:
expandLoadStackGuard
(
MIB
,
*
this
)
;
return
true
;
}
return
false
;
}
</s>

This function is called for all pseudo instructions that remain after register allocation .


<s>
void
print_operand_address
(
FILE
*
file
,
rtx
addr
)
{
int
basereg
=
31
;
HOST_WIDE_INT
offset
=
0
;
if
(
GET_CODE
(
addr
)
==
AND
)
addr
=
XEXP
(
addr
,
0
)
;
if
(
GET_CODE
(
addr
)
==
PLUS
&&
CONST_INT_P
(
XEXP
(
addr
,
1
)
)
)
{
offset
=
INTVAL
(
XEXP
(
addr
,
1
)
)
;
addr
=
XEXP
(
addr
,
0
)
;
}
if
(
GET_CODE
(
addr
)
==
LO_SUM
)
{
const
char
*
reloc16
,
*
reloclo
;
rtx
op1
=
XEXP
(
addr
,
1
)
;
if
(
GET_CODE
(
op1
)
==
CONST
&&
GET_CODE
(
XEXP
(
op1
,
0
)
)
==
UNSPEC
)
{
op1
=
XEXP
(
op1
,
0
)
;
switch
(
XINT
(
op1
,
1
)
)
{
case
UNSPEC_DTPREL
:
reloc16
=
;
reloclo
=
(
alpha_tls_size
==
16
"dtprel"
:
"dtprello"
)
;
break
;
case
UNSPEC_TPREL
:
reloc16
=
;
reloclo
=
(
alpha_tls_size
==
16
"tprel"
:
"tprello"
)
;
break
;
default
:
output_operand_lossage
(
"unknown relocation unspec"
)
;
return
;
}
output_addr_const
(
file
,
XVECEXP
(
op1
,
0
,
0
)
)
;
}
else
{
reloc16
=
"gprel"
;
reloclo
=
"gprellow"
;
output_addr_const
(
file
,
op1
)
;
}
if
(
offset
)
fprintf
(
file
,
"+"
HOST_WIDE_INT_PRINT_DEC
,
offset
)
;
addr
=
XEXP
(
addr
,
0
)
;
switch
(
GET_CODE
(
addr
)
)
{
case
REG
:
basereg
=
REGNO
(
addr
)
;
break
;
case
SUBREG
:
basereg
=
subreg_regno
(
addr
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
fprintf
(
file
,
"($%d)\t\t!%s"
,
basereg
,
(
basereg
==
29
reloc16
:
reloclo
)
)
;
return
;
}
switch
(
GET_CODE
(
addr
)
)
{
case
REG
:
basereg
=
REGNO
(
addr
)
;
break
;
case
SUBREG
:
basereg
=
subreg_regno
(
addr
)
;
break
;
case
CONST_INT
:
offset
=
INTVAL
(
addr
)
;
break
;
case
SYMBOL_REF
:
gcc_assert
(
TARGET_ABI_OPEN_VMS
||
this_is_asm_operands
)
;
fprintf
(
file
,
"%s"
,
XSTR
(
addr
,
0
)
)
;
return
;
case
CONST
:
gcc_assert
(
TARGET_ABI_OPEN_VMS
||
this_is_asm_operands
)
;
gcc_assert
(
GET_CODE
(
XEXP
(
addr
,
0
)
)
==
PLUS
&&
GET_CODE
(
XEXP
(
XEXP
(
addr
,
0
)
,
0
)
)
==
SYMBOL_REF
)
;
fprintf
(
file
,
"%s+"
HOST_WIDE_INT_PRINT_DEC
,
XSTR
(
XEXP
(
XEXP
(
addr
,
0
)
,
0
)
,
0
)
,
INTVAL
(
XEXP
(
XEXP
(
addr
,
0
)
,
1
)
)
)
;
return
;
default
:
output_operand_lossage
(
"invalid operand address"
)
;
return
;
}
fprintf
(
file
,
HOST_WIDE_INT_PRINT_DEC
"($%d)"
,
offset
,
basereg
)
;
}
</s>

Print the operand address represented by the rtx addr


<s> static void loongarch_emit_int_order_test ( enum rtx_code code , bool * invert_ptr , rtx target , rtx cmp0 , rtx cmp1 ) { machine_mode mode ; mode = GET_MODE ( cmp0 ) ; if ( loongarch_canonicalize_int_order_test ( & code , & cmp1 , mode ) ) loongarch_emit_binary ( code , target , cmp0 , cmp1 ) ; else { enum rtx_code inv_code = reverse_condition ( code ) ; if ( ! loongarch_canonicalize_int_order_test ( & inv_code , & cmp1 , mode ) ) { cmp1 = force_reg ( mode , cmp1 ) ; loongarch_emit_int_order_test ( code , invert_ptr , target , cmp0 , cmp1 ) ; } else if ( invert_ptr == 0 ) { rtx inv_target ; inv_target = loongarch_force_binary ( GET_MODE ( target ) , inv_code , cmp0 , cmp1 ) ; loongarch_emit_binary ( XOR , target , inv_target , const1_rtx ) ; } else { * invert_ptr = ! * invert_ptr ; loongarch_emit_binary ( inv_code , target , cmp0 , cmp1 ) ; } } } </s>

Compare CMP0 and CMP1 using ordering test CODE and store the result in TARGET . CMP0 and TARGET are register_operands . If INVERT_PTR is nonnull , it 's OK to set TARGET to the inverse of the result and flip * INVERT_PTR instead .


<s> void HexagonTargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { if ( isHvxOperation ( N , DAG ) ) { ReplaceHvxNodeResults ( N , Results , DAG ) ; if ( ! Results . empty ( ) ) return ; } const SDLoc & dl ( N ) ; switch ( N -> getOpcode ( ) ) { case ISD :: SRL : case ISD :: SRA : case ISD :: SHL : return ; case ISD :: BITCAST : if ( N -> getValueType ( 0 ) == MVT :: i8 ) { SDValue P = getInstr ( Hexagon :: C2_tfrpr , dl , MVT :: i32 , N -> getOperand ( 0 ) , DAG ) ; SDValue T = DAG . getAnyExtOrTrunc ( P , dl , MVT :: i8 ) ; Results . push_back ( T ) ; } break ; } } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> bool SystemZMCAsmBackend :: mayNeedRelaxation ( const MCInst & Inst ) const { return getRelaxedOpcode ( Inst . getOpcode ( ) ) != 0 ; } </s>

Check whether the given instruction may need relaxation .


<s>
int
m32c_legitimate_address_p
(
enum
machine_mode
mode
,
rtx
x
,
int
strict
)
{
int
mode_adjust
;
if
(
CONSTANT_P
(
x
)
)
return
1
;
mode_adjust
=
GET_MODE_SIZE
(
mode
)
1
;
if
(
GET_CODE
(
x
)
==
PRE_DEC
||
GET_CODE
(
x
)
==
POST_INC
||
GET_CODE
(
x
)
==
PRE_MODIFY
)
{
return
(
GET_CODE
(
XEXP
(
x
,
0
)
)
==
REG
&&
REGNO
(
XEXP
(
x
,
0
)
)
==
SP_REGNO
)
;
}
if
(
TARGET_A24
&&
GET_CODE
(
x
)
==
MEM
&&
GET_CODE
(
XEXP
(
x
,
0
)
)
!=
PLUS
)
{
fprintf
(
stderr
,
"double indirect\n"
)
;
x
=
XEXP
(
x
,
0
)
;
}
encode_pattern
(
x
)
;
if
(
RTX_IS
(
"r"
)
)
{
switch
(
REGNO
(
patternr
[
0
]
)
)
{
case
A0_REGNO
:
case
A1_REGNO
:
case
SB_REGNO
:
case
FB_REGNO
:
case
SP_REGNO
:
return
1
;
default
:
if
(
IS_PSEUDO
(
patternr
[
0
]
,
strict
)
)
return
1
;
return
0
;
}
}
if
(
RTX_IS
(
"+ri"
)
)
{
int
rn
=
REGNO
(
patternr
[
1
]
)
;
HOST_WIDE_INT
offs
=
INTVAL
(
patternr
[
2
]
)
;
switch
(
rn
)
{
case
A0_REGNO
:
case
A1_REGNO
:
case
SB_REGNO
:
if
(
TARGET_A16
)
return
(
offs
>=
65536
&&
offs
<=
65535
mode_adjust
)
;
if
(
rn
==
SB_REGNO
)
return
(
offs
>=
0
&&
offs
<=
65535
mode_adjust
)
;
return
(
offs
>=
16777216
&&
offs
<=
16777215
)
;
case
FB_REGNO
:
if
(
TARGET_A16
)
return
(
offs
>=
128
&&
offs
<=
127
mode_adjust
)
;
return
(
offs
>=
65536
&&
offs
<=
65535
mode_adjust
)
;
case
SP_REGNO
:
return
(
offs
>=
128
&&
offs
<=
127
mode_adjust
)
;
default
:
if
(
IS_PSEUDO
(
patternr
[
1
]
,
strict
)
)
return
1
;
return
0
;
}
}
if
(
RTX_IS
(
"+rs"
)
||
RTX_IS
(
"+r+si"
)
)
{
rtx
reg
=
patternr
[
1
]
;
switch
(
REGNO
(
reg
)
)
{
case
A0_REGNO
:
case
A1_REGNO
:
return
1
;
default
:
if
(
IS_PSEUDO
(
reg
,
strict
)
)
return
1
;
return
0
;
}
}
return
0
;
}
</s>

Used by GO_IF_LEGITIMATE_ADDRESS . The r8c/m32c family supports a wide range of non-orthogonal addressing modes , including the ability to double-indirect on * some * of them . Not all insns support all modes , either , but we rely on predicates and constraints to deal with that .


<s> bool ARMAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; printAddrMode2Operand ( MI , OpNum ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


"mips16 and nomips16 specified on the same function"

Reset the subtarget for the Mips target .


"LowerFormalArguments Unhandled argument type: "

"functions with VarArgs or StructRet are not supported"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


"getJumpOffset16OpValue expects only expressions or an immediate"

getJumpOffset16OpValue - Return binary encoding of the jump target operand .


<s> static void * rs6000_init_cost ( struct loop * loop_info ) { rs6000_cost_data * data = XNEW ( struct _rs6000_cost_data ) ; data -> loop_info = loop_info ; data -> cost [ vect_prologue ] = 0 ; data -> cost [ vect_body ] = 0 ; data -> cost [ vect_epilogue ] = 0 ; rs6000_vect_nonmem = false ; return data ; } </s>


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO , ISD :: ArgFlagsTy Flags ) override { auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( Size , Offset , true ) ; MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; auto AddrReg = MIRBuilder . buildFrameIndex ( LLT :: pointer ( 0 , 16 ) , FI ) ; return AddrReg . getReg ( 0 ) ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> void PatmosPostRASchedStrategy :: scheduleTree ( unsigned SubtreeID ) { ReadyQ . scheduledTree ( SubtreeID ) ; } </s>

Scheduler callback to update SubtreeConnectLevels when a tree is initially scheduled .


<s> int sh_media_register_for_return ( void ) { int regno ; int tr0_used ; if ( ! current_function_is_leaf ) return - 1 ; if ( lookup_attribute ( "interrupt_handler" , DECL_ATTRIBUTES ( current_function_decl ) ) ) return - 1 ; if ( sh_cfun_interrupt_handler_p ( ) ) return - 1 ; tr0_used = flag_pic && regs_ever_live [ PIC_OFFSET_TABLE_REGNUM ] ; for ( regno = FIRST_TARGET_REG + tr0_used ; regno <= LAST_TARGET_REG ; regno ++ ) if ( call_really_used_regs [ regno ] && ! regs_ever_live [ regno ] ) return regno ; return - 1 ; } </s>

Choose a call-clobbered target-branch register that remains unchanged along the whole function . We set it up as the return value in the prologue .


<s> static bool h8300_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { return regno == MAC_REG ? mode == SImode : 1 ; } </s>

Worker function for HARD_REGNO_MODE_OK .


<s> bool XtensaAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned , const char * ExtraCode , raw_ostream & O ) { llvm_unreachable ( "XXX:" ) ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static unsigned findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const X86RegisterInfo * TRI , bool Is64Bit ) { const MachineFunction * MF = MBB . getParent ( ) ; const Function * F = MF -> getFunction ( ) ; if ( ! F || MF -> callsEHReturn ( ) ) return 0 ; const TargetRegisterClass & AvailableRegs = * TRI -> getGPRsForTailCall ( * MF ) ; if ( MBBI == MBB . end ( ) ) return 0 ; switch ( MBBI -> getOpcode ( ) ) { default : return 0 ; case TargetOpcode :: PATCHABLE_RET : case X86 :: RET : case X86 :: RETL : case X86 :: RETQ : case X86 :: RETIL : case X86 :: RETIQ : case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: TCRETURNmi64 : case X86 :: EH_RETURN : case X86 :: EH_RETURN64 : { SmallSet < uint16_t , 8 > Uses ; for ( unsigned i = 0 , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } for ( auto CS : AvailableRegs ) if ( ! Uses . count ( CS ) && CS != X86 :: RIP ) return CS ; } } return 0 ; } </s>

findDeadCallerSavedReg - Return a caller-saved register that is n't live when it reaches the `` return '' instruction .


<s> static void aarch64_override_options_after_change ( void ) { aarch64_override_options_after_change_1 ( & global_options ) ; } </s>


<s> bool function_arg_regno_p ( int n ) { int i ; for ( i = 0 ; arg_regs [ i ] != - 1 ; i ++ ) if ( n == arg_regs [ i ] ) return true ; return false ; } </s>

Return true when register may be used to pass function parameters .


<s> static bool pa_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { if ( TARGET_PORTABLE_RUNTIME ) return false ; if ( TARGET_ELF32 ) return ( decl != NULL_TREE ) ; if ( TARGET_64BIT ) return false ; return ( decl && ! TREE_PUBLIC ( decl ) ) ; } </s>

Only direct calls to static functions are allowed to be sibling ( tail ) call optimized . This restriction is necessary because some linker generated stubs will store return pointers into rp ' in some cases which might clobber a live value already in rp ' . In a sibcall the current function and the target function share stack space . Thus if the path to the current function and the path to the target function save a value in rp ' , they save the value into the same stack slot , which has undesirable consequences . Because of the deferred binding nature of shared libraries any function with external scope could be in a different load module and thus require rp ' to be saved when calling that function . So sibcall optimizations can only be safe for static function . Note that GCC never needs return value relocations , so we do n't have to worry about static calls with return value relocations ( which require saving rp ' ) . It is safe to perform a sibcall optimization when the target function will never return .


" was Pass-through, is now Dirty-out.\n"

runOnMachineFunction - Emit the function body .


<s> bool hasFP ( const MachineFunction & ) const override { return true ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
bool
ARMTargetLowering
::
getPostIndexedAddressParts
(
SDNode
*
N
,
SDNode
*
Op
,
SDValue
&
Base
,
SDValue
&
Offset
,
ISD
::
MemIndexedMode
&
AM
,
SelectionDAG
&
DAG
)
const
{
EVT
VT
;
SDValue
Ptr
;
bool
isSEXTLoad
=
false
,
isNonExt
;
if
(
LoadSDNode
*
LD
=
dyn_cast
<
LoadSDNode
>
(
N
)
)
{
VT
=
LD
->
getMemoryVT
(
)
;
Ptr
=
LD
->
getBasePtr
(
)
;
isSEXTLoad
=
LD
->
getExtensionType
(
)
==
ISD
::
SEXTLOAD
;
isNonExt
=
LD
->
getExtensionType
(
)
==
ISD
::
NON_EXTLOAD
;
}
else
if
(
StoreSDNode
*
ST
=
dyn_cast
<
StoreSDNode
>
(
N
)
)
{
VT
=
ST
->
getMemoryVT
(
)
;
Ptr
=
ST
->
getBasePtr
(
)
;
isNonExt
=
!
ST
->
isTruncatingStore
(
)
;
}
else
return
false
;
if
(
Subtarget
->
isThumb1Only
(
)
)
{
assert
(
Op
->
getValueType
(
0
)
==
MVT
::
i32
&&
"Non-i32 post-inc op?!"
)
;
if
(
Op
->
getOpcode
(
)
!=
ISD
::
ADD
||
!
isNonExt
)
return
false
;
auto
*
RHS
=
dyn_cast
<
ConstantSDNode
>
(
Op
->
getOperand
(
1
)
)
;
if
(
!
RHS
||
RHS
->
getZExtValue
(
)
!=
4
)
return
false
;
Offset
=
Op
->
getOperand
(
1
)
;
Base
=
Op
->
getOperand
(
0
)
;
AM
=
ISD
::
POST_INC
;
return
true
;
}
bool
isInc
;
bool
isLegal
=
false
;
if
(
Subtarget
->
isThumb2
(
)
)
isLegal
=
getT2IndexedAddressParts
(
Op
,
VT
,
isSEXTLoad
,
Base
,
Offset
,
isInc
,
DAG
)
;
else
isLegal
=
getARMIndexedAddressParts
(
Op
,
VT
,
isSEXTLoad
,
Base
,
Offset
,
isInc
,
DAG
)
;
if
(
!
isLegal
)
return
false
;
if
(
Ptr
!=
Base
)
{
if
(
Ptr
==
Offset
&&
Op
->
getOpcode
(
)
==
ISD
::
ADD
&&
!
Subtarget
->
isThumb2
(
)
)
std
::
swap
(
Base
,
Offset
)
;
if
(
Ptr
!=
Base
)
return
false
;
}
AM
=
isInc
ISD
::
POST_INC
:
ISD
::
POST_DEC
;
return
true
;
}
</s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .


<s> bool PPCLoopPreIncPrep :: runOnFunction ( Function & F ) { LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolution > ( ) ; bool MadeChange = false ; for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) { Loop * L = * I ; MadeChange |= runOnLoop ( L ) ; } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool PPCAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , O ) ; case 'L' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + 1 == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + 1 ) . isReg ( ) ) return true ; ++ OpNo ; break ; case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << "i" ; return false ; case 'x' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) ) return true ; Register Reg = MI -> getOperand ( OpNo ) . getReg ( ) ; if ( PPCInstrInfo :: isVRRegister ( Reg ) ) Reg = PPC :: VSX32 + ( Reg - PPC :: V0 ) ; else if ( PPCInstrInfo :: isVFRegister ( Reg ) ) Reg = PPC :: VSX32 + ( Reg - PPC :: VF0 ) ; const char * RegName ; RegName = PPCInstPrinter :: getRegisterName ( Reg ) ; RegName = PPCRegisterInfo :: stripRegisterPrefix ( RegName ) ; O << RegName ; return false ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>


<s> bool isValid ( ) const { return Block ; } </s>

Returns true if this iterator is still pointing at a valid entry .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addPreserved < ScalarEvolutionWrapperPass > ( ) ; getLoopAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


"VLAs and dynamic stack realign, but no FP?!"

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s>
bool
SystemZInstrInfo
::
PredicateInstruction
(
MachineInstr
*
MI
,
const
SmallVectorImpl
<
MachineOperand
>
&
Pred
)
const
{
assert
(
Pred
.
size
(
)
==
2
&&
"Invalid condition"
)
;
unsigned
CCValid
=
Pred
[
0
]
.
getImm
(
)
;
unsigned
CCMask
=
Pred
[
1
]
.
getImm
(
)
;
assert
(
CCMask
>
0
&&
CCMask
<
15
&&
"Invalid predicate"
)
;
unsigned
Opcode
=
MI
->
getOpcode
(
)
;
if
(
TM
.
getSubtargetImpl
(
)
->
hasLoadStoreOnCond
(
)
)
{
if
(
unsigned
CondOpcode
=
getConditionalMove
(
Opcode
)
)
{
MI
->
setDesc
(
get
(
CondOpcode
)
)
;
MachineInstrBuilder
(
*
MI
->
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
;
return
true
;
}
}
return
false
;
}
</s>

Convert the instruction into a predicated instruction .


<s> int mmix_initial_elimination_offset ( int fromreg , int toreg ) { int regno ; int fp_sp_offset = ( get_frame_size ( ) + crtl -> outgoing_args_size + 7 ) & ~ 7 ; if ( fromreg == MMIX_ARG_POINTER_REGNUM && toreg == MMIX_FRAME_POINTER_REGNUM ) return 0 ; for ( regno = MMIX_FIRST_GLOBAL_REGNUM ; regno <= 255 ; regno ++ ) if ( ( df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) ) || IS_MMIX_EH_RETURN_DATA_REG ( regno ) ) fp_sp_offset += 8 ; return fp_sp_offset + ( MMIX_CFUN_HAS_LANDING_PAD ? 16 : ( MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS ? 8 : 0 ) ) + ( fromreg == MMIX_ARG_POINTER_REGNUM ? 0 : 8 ) ; } </s>

The difference between the ( imaginary ) frame pointer and the stack pointer . Used to eliminate the frame pointer .


<s>
Register
VETargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
LLT
VT
,
const
MachineFunction
&
MF
)
const
{
Register
Reg
=
StringSwitch
<
Register
>
(
RegName
)
.
Case
(
"sp"
,
VE
::
SX11
)
.
Case
(
"fp"
,
VE
::
SX9
)
.
Case
(
"sl"
,
VE
::
SX8
)
.
Case
(
"lr"
,
VE
::
SX10
)
.
Case
(
"tp"
,
VE
::
SX14
)
.
Case
(
"outer"
,
VE
::
SX12
)
.
Case
(
"info"
,
VE
::
SX17
)
.
Case
(
"got"
,
VE
::
SX15
)
.
Case
(
"plt"
,
VE
::
SX16
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> unsigned TOYInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case TOY :: STORErr : if ( MI -> getOperand ( 1 ) . isFI ( ) ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


"frame pointer should not have been eliminated"


<s> static void assign_fp_registers ( const_tree field , int bitpos , assign_data_t * data ) { int nregs ; machine_mode mode ; if ( ! compute_fp_layout ( field , bitpos , data , & nregs , & mode ) ) return ; const int this_slotno = data -> slotno + bitpos / BITS_PER_WORD ; int regno = SPARC_FP_ARG_FIRST + this_slotno * 2 ; if ( GET_MODE_SIZE ( mode ) <= 4 && ( bitpos & 32 ) != 0 ) regno ++ ; int pos = bitpos / BITS_PER_UNIT ; do { rtx reg = gen_rtx_REG ( mode , regno ) ; XVECEXP ( data -> ret , 0 , data -> stack + data -> nregs ) = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( pos ) ) ; data -> nregs += 1 ; regno += GET_MODE_SIZE ( mode ) / 4 ; pos += GET_MODE_SIZE ( mode ) ; } while ( -- nregs > 0 ) ; } </s>

A subroutine of function_arg_record_value . Assign FIELD at position BITPOS to FP registers .


<s> bool isImm ( ) const override { return is ( k_Immediate ) ; } </s>


<s> int standard_sse_constant_p ( rtx x ) { if ( x == const0_rtx ) return 1 ; return ( x == CONST0_RTX ( GET_MODE ( x ) ) ) ; } </s>

Return 1 if X is all 0s and 2 if x is all 1s in supported SSE/AVX vector mode .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


"JIT relocation model must be set to static or default!"


<s> bool hasUsableDSOffset ( ) const { return getGeneration ( ) >= SEA_ISLANDS ; } </s>

True if the offset field of DS instructions works as expected .


<s> bool MipsLongBranch :: runOnMachineFunction ( MachineFunction & F ) { if ( ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) && TM . getSubtarget < MipsSubtarget > ( ) . isABI_O32 ( ) && F . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; SmallVector < MBBInfo , 16 > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; if ( ! ForceLongBranch && isInt < 16 > ( computeOffset ( I -> Br ) / 4 ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * 4 ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { MF -> getInfo < MipsFunctionInfo > ( ) -> setEmitNOAT ( ) ; uint64_t Address = 0 ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ; } for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) if ( I -> HasLongBranch ) expandToLongBranch ( * I ) ; MF -> RenumberBlocks ( ) ; return true ; } </s>


<s> static bool frv_registers_conflict_p ( rtx x ) { regstate_t flags ; flags = 0 ; if ( GET_CODE ( x ) == COND_EXEC ) { if ( frv_registers_conflict_p_1 ( XEXP ( x , 0 ) , flags ) ) return true ; flags |= frv_cond_flags ( XEXP ( x , 0 ) ) ; x = XEXP ( x , 1 ) ; } return frv_registers_conflict_p_1 ( x , flags ) ; } </s>

Return true if something in X might depend on an instruction in the current packet .


Return the DataLayout associated with the module this SCEV instance is operating on .


<s> static unsigned long rs6000_arg_size ( machine_mode mode , const_tree type ) { unsigned long size ; if ( mode != BLKmode ) size = GET_MODE_SIZE ( mode ) ; else size = int_size_in_bytes ( type ) ; if ( TARGET_32BIT ) return ( size + 3 ) >> 2 ; else return ( size + 7 ) >> 3 ; } </s>

Compute the size ( in words ) of a function argument .


<s> void AArch64PassConfig :: addPreEmitPass ( ) { if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Aggressive && EnableLoadStoreOpt ) addPass ( createAArch64LoadStoreOptimizationPass ( ) ) ; if ( EnableA53Fix835769 ) addPass ( createAArch64A53Fix835769 ( ) ) ; if ( BranchRelaxation ) addPass ( & BranchRelaxationPassID ) ; if ( EnableBranchTargets ) addPass ( createAArch64BranchTargetsPass ( ) ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardLongjmpPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCompressJumpTables ) addPass ( createAArch64CompressJumpTablesPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> unsigned ARMFastISel :: fastEmitInst_i ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , uint64_t Imm ) { Register ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; if ( II . getNumDefs ( ) >= 1 ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addImm ( Imm ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addImm ( Imm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ 0 ] ) ) ; } return ResultReg ; } </s>

Emit a MachineInstr with a single immediate operand , and a result register in the given register class .


<s> const char * SparcTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( SPISD :: NodeType ) Opcode ) { case SPISD :: FIRST_NUMBER : break ; case SPISD :: CMPICC : return "SPISD::CMPICC" ; case SPISD :: CMPFCC : return "SPISD::CMPFCC" ; case SPISD :: BRICC : return "SPISD::BRICC" ; case SPISD :: BRXCC : return "SPISD::BRXCC" ; case SPISD :: BRFCC : return "SPISD::BRFCC" ; case SPISD :: SELECT_ICC : return "SPISD::SELECT_ICC" ; case SPISD :: SELECT_XCC : return "SPISD::SELECT_XCC" ; case SPISD :: SELECT_FCC : return "SPISD::SELECT_FCC" ; case SPISD :: EH_SJLJ_SETJMP : return "SPISD::EH_SJLJ_SETJMP" ; case SPISD :: EH_SJLJ_LONGJMP : return "SPISD::EH_SJLJ_LONGJMP" ; case SPISD :: Hi : return "SPISD::Hi" ; case SPISD :: Lo : return "SPISD::Lo" ; case SPISD :: FTOI : return "SPISD::FTOI" ; case SPISD :: ITOF : return "SPISD::ITOF" ; case SPISD :: FTOX : return "SPISD::FTOX" ; case SPISD :: XTOF : return "SPISD::XTOF" ; case SPISD :: CALL : return "SPISD::CALL" ; case SPISD :: RET_FLAG : return "SPISD::RET_FLAG" ; case SPISD :: GLOBAL_BASE_REG : return "SPISD::GLOBAL_BASE_REG" ; case SPISD :: FLUSHW : return "SPISD::FLUSHW" ; case SPISD :: TLS_ADD : return "SPISD::TLS_ADD" ; case SPISD :: TLS_LD : return "SPISD::TLS_LD" ; case SPISD :: TLS_CALL : return "SPISD::TLS_CALL" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> bool strict_low_part_peephole_ok ( machine_mode mode , rtx_insn * first_insn , rtx target ) { rtx_insn * p = first_insn ; while ( ( p = PREV_INSN ( p ) ) ) { if ( NOTE_INSN_BASIC_BLOCK_P ( p ) ) return false ; if ( NOTE_P ( p ) ) continue ; if ( ! INSN_P ( p ) ) return false ; if ( reg_set_p ( target , p ) ) { rtx set = single_set ( p ) ; rtx dest ; if ( ! set ) return false ; dest = SET_DEST ( set ) ; if ( rtx_equal_p ( dest , target ) && SET_SRC ( set ) == const0_rtx ) return true ; else if ( GET_CODE ( dest ) == STRICT_LOW_PART && GET_CODE ( XEXP ( dest , 0 ) ) == REG && REGNO ( XEXP ( dest , 0 ) ) == REGNO ( target ) && ( GET_MODE_SIZE ( GET_MODE ( XEXP ( dest , 0 ) ) ) <= GET_MODE_SIZE ( mode ) ) ) ; else return false ; } } return false ; } </s>

Check for cases where a clr insns can be omitted from code using strict_low_part sets . For example , the second clrl here is not needed : clrl d0 ; movw a0 @ + , d0 ; use d0 ; clrl d0 ; movw a0 @ + ; use d0 ; ... MODE is the mode of this STRICT_LOW_PART set . FIRST_INSN is the clear insn we are checking for redundancy . TARGET is the register set by the clear insn .


<s> bool XCoreAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ! ExtraCode || ! ExtraCode [ 0 ] ) { printOperand ( MI , OpNo , O ) ; return false ; } return AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , O ) ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> BitVector ARMBaseRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( ARM :: SP ) ; Reserved . set ( ARM :: PC ) ; Reserved . set ( ARM :: FPSCR ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( FramePtr ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( BasePtr ) ; if ( STI . isR9Reserved ( ) ) Reserved . set ( ARM :: R9 ) ; if ( ! STI . hasVFP3 ( ) || STI . hasD16 ( ) ) { assert ( ARM :: D31 == ARM :: D16 + 15 ) ; for ( unsigned i = 0 ; i != 16 ; ++ i ) Reserved . set ( ARM :: D16 + i ) ; } const TargetRegisterClass * RC = & ARM :: GPRPairRegClass ; for ( TargetRegisterClass :: iterator I = RC -> begin ( ) , E = RC -> end ( ) ; I != E ; ++ I ) for ( MCSubRegIterator SI ( * I , this ) ; SI . isValid ( ) ; ++ SI ) if ( Reserved . test ( * SI ) ) Reserved . set ( * I ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void alpha_set_memflags ( rtx insn , rtx ref ) { rtx * base_ptr ; if ( GET_CODE ( ref ) != MEM ) return ; if ( ! MEM_VOLATILE_P ( ref ) && ! MEM_IN_STRUCT_P ( ref ) && ! MEM_SCALAR_P ( ref ) && ! MEM_NOTRAP_P ( ref ) && ! MEM_READONLY_P ( ref ) ) return ; if ( INSN_P ( insn ) ) base_ptr = & PATTERN ( insn ) ; else base_ptr = & insn ; for_each_rtx ( base_ptr , alpha_set_memflags_1 , ( void * ) ref ) ; } </s>

Given INSN , which is an INSN list or the PATTERN of a single insn generated to perform a memory operation , look for any MEMs in either a SET_DEST or a SET_SRC and copy the in-struct , unchanging , and volatile flags from REF into each of the MEMs found . If REF is not a MEM , do n't do anything .


<s> static void mips_maybe_swap_ready ( rtx_insn * * ready , int pos1 , int pos2 , int limit ) { if ( pos1 < pos2 && INSN_PRIORITY ( ready [ pos1 ] ) + limit >= INSN_PRIORITY ( ready [ pos2 ] ) ) { rtx_insn * temp ; temp = ready [ pos1 ] ; ready [ pos1 ] = ready [ pos2 ] ; ready [ pos2 ] = temp ; } } </s>

If the priority of the instruction at POS2 in the ready queue READY is within LIMIT units of that of the instruction at POS1 , swap the instructions if POS2 is not already less than POS1 .


<s> bool runOnModule ( Module & M ) override { FeatureBitset Features = coalesceFeatures ( M ) ; std :: string FeatureStr = getFeatureString ( Features ) ; WasmTM -> setTargetFeatureString ( FeatureStr ) ; for ( auto & F : M ) replaceFeatures ( F , FeatureStr ) ; bool StrippedAtomics = false ; bool StrippedTLS = false ; if ( ! Features [ WebAssembly :: FeatureAtomics ] ) { StrippedAtomics = stripAtomics ( M ) ; StrippedTLS = stripThreadLocals ( M ) ; } else if ( ! Features [ WebAssembly :: FeatureBulkMemory ] ) { StrippedTLS |= stripThreadLocals ( M ) ; } if ( StrippedAtomics && ! StrippedTLS ) stripThreadLocals ( M ) ; else if ( StrippedTLS && ! StrippedAtomics ) stripAtomics ( M ) ; recordFeatures ( M , Features , StrippedAtomics || StrippedTLS ) ; return true ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineModuleInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void TMS320C64XInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned dstReg , int frameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; const TargetRegisterClass * rc ; if ( ! TargetRegisterInfo :: isPhysicalRegister ( dstReg ) ) { assert ( RC ) ; if ( RC == TMS320C64X :: PredRegsRegisterClass ) rc = TMS320C64X :: ARegsRegisterClass ; else rc = RC ; } else rc = findRegisterSide ( dstReg , MBB . getParent ( ) ) ; bool xdata = ( rc == TMS320C64X :: BRegsRegisterClass ) ; addFormOp ( addDefaultPred ( BuildMI ( MBB , MI , DL , get ( TMS320C64X :: word_load_1 ) ) . addReg ( dstReg , RegState :: Define ) . addReg ( TMS320C64X :: A15 ) . addFrameIndex ( frameIndex ) ) , TMS320C64XII :: unit_d , xdata ) ; } </s>


<s> void MipsSEFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; unsigned RA = ABI . GetReturnAddress ( ) ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned BP = ABI . GetBasePtr ( ) ; if ( hasFP ( MF ) ) { setAliasRegs ( MF , SavedRegs , RA ) ; setAliasRegs ( MF , SavedRegs , FP ) ; } if ( hasBP ( MF ) ) setAliasRegs ( MF , SavedRegs , BP ) ; if ( MipsFI -> callsEhReturn ( ) ) MipsFI -> createEhDataRegsFI ( MF ) ; if ( MipsFI -> isISR ( ) ) MipsFI -> createISRRegFI ( MF ) ; if ( ExpandPseudo ( MF ) . expand ( ) ) { const TargetRegisterClass & RC = STI . isGP64bit ( ) ? Mips :: GPR64RegClass : Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlign ( RC ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } uint64_t MaxSPOffset = estimateStackSize ( MF ) ; if ( STI . isCheri ( ) ) { if ( STI . isABI_CheriPureCap ( ) ) { if ( isInt < 10 > ( MaxSPOffset ) ) return ; } else if ( isInt < 15 > ( MaxSPOffset ) ) return ; } else if ( isIntN ( STI . hasMSA ( ) ? 10 : 16 , MaxSPOffset ) && ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ) return ; const TargetRegisterClass & RC = ABI . ArePtrs64bit ( ) ? Mips :: GPR64RegClass : Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlign ( RC ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


Return nonzero if the current function is an interrupt function .


<s> unsigned MipsAsmParser :: getReg ( int RC , int RegNo ) { return * ( getContext ( ) . getRegisterInfo ( ) . getRegClass ( RC ) . begin ( ) + RegNo ) ; } </s>

Returns the register associated with this edge .


<s> bool AArch64PromoteConstant :: runOnFunction ( Function & F , PromotionCacheTy & PromotionCache ) { SmallVector < UpdateRecord , 64 > Updates ; for ( Instruction & I : instructions ( & F ) ) { for ( Use & U : I . operands ( ) ) { Constant * Cst = dyn_cast < Constant > ( U ) ; if ( ! Cst || isa < GlobalValue > ( Cst ) || ! containsOnlyConstantData ( Cst ) ) continue ; if ( ! shouldConvert ( * Cst , PromotionCache ) ) continue ; unsigned OpNo = & U - I . op_begin ( ) ; if ( ! shouldConvertUse ( Cst , & I , OpNo ) ) continue ; Updates . emplace_back ( Cst , & I , OpNo ) ; } } if ( Updates . empty ( ) ) return false ; promoteConstants ( F , Updates , PromotionCache ) ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> rtx frv_gen_GPsym2reg ( rtx dest , rtx src ) { tree gp = get_identifier ( "_gp" ) ; rtx gp_sym = gen_rtx_SYMBOL_REF ( Pmode , IDENTIFIER_POINTER ( gp ) ) ; return gen_symGOT2reg ( dest , gp_sym , src , GEN_INT ( R_FRV_GOT12 ) ) ; } </s>

Load the _gp symbol into DEST . SRC is supposed to be the FDPIC register .


<s> Register TL45RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TL45Subtarget & Subtarget = MF . getSubtarget < TL45Subtarget > ( ) ; const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? TL45 :: bp : TL45 :: sp ; } </s>


<s> static RTX_CODE compare_condition ( rtx_insn * insn ) { rtx_insn * next = next_real_insn ( insn ) ; if ( next && JUMP_P ( next ) ) { rtx pat = PATTERN ( next ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , 0 , 0 ) ; rtx src = SET_SRC ( pat ) ; if ( IF_THEN_ELSE == GET_CODE ( src ) ) return GET_CODE ( XEXP ( src , 0 ) ) ; } return UNKNOWN ; } </s>

Returns the condition of compare insn INSN , or UNKNOWN .


<s> const RegisterBankInfo * M68kSubtarget :: getRegBankInfo ( ) const { return RegBankInfo . get ( ) ; } </s>

If the information for the register banks is available , return it .


<s> unsigned PPCTTIImpl :: getNumberOfRegisters ( unsigned ClassID ) const { assert ( ClassID == GPRRC || ClassID == FPRRC || ClassID == VRRC || ClassID == VSXRC ) ; if ( ST -> hasVSX ( ) ) { assert ( ClassID == GPRRC || ClassID == VSXRC ) ; return ClassID == GPRRC ? 32 : 64 ; } assert ( ClassID == GPRRC || ClassID == FPRRC || ClassID == VRRC ) ; return 32 ; } </s>


"VTMP producer and consumer not in same block"

runOnMachineFunction - Emit the function body .


<s> SDValue XtensaTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { SDValue ret ; return ret ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> static tree aarch64_d_handle_target_float_abi ( void ) { const char * abi = "hard" ; return build_string_literal ( strlen ( abi ) + 1 , abi ) ; } </s>

Handle a call to ` __traits ( getTargetInfo , `` floatAbi '' ) ' .


<s> unsigned X86InstrInfo :: getPartialRegUpdateClearance ( const MachineInstr & MI , unsigned OpNum , const TargetRegisterInfo * TRI ) const { if ( OpNum != 0 || ! hasPartialRegUpdate ( MI . getOpcode ( ) ) ) return 0 ; const MachineOperand & MO = MI . getOperand ( 0 ) ; unsigned Reg = MO . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { if ( MO . readsReg ( ) || MI . readsVirtualRegister ( Reg ) ) return 0 ; } else { if ( MI . readsRegister ( Reg , TRI ) ) return 0 ; } return PartialRegUpdateClearance ; } </s>

Inform the BreakFalseDeps pass how many idle instructions we would like before a partial register update .


ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> static bool ft32_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { const HOST_WIDE_INT size = int_size_in_bytes ( type ) ; return ( size == - 1 || size > 2 * UNITS_PER_WORD ) ; } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


<s> void Thumb2InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == ARM :: GPRRegisterClass || RC == ARM :: tGPRRegisterClass ) { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , 0 , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2STRi12 ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } ARMBaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg , isKill , FI , RC ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> const uint32_t * SIRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { switch ( CC ) { case CallingConv :: C : case CallingConv :: Fast : case CallingConv :: Cold : case CallingConv :: AMDGPU_Gfx : return MF . getSubtarget < GCNSubtarget > ( ) . hasGFX90AInsts ( ) ? CSR_AMDGPU_HighRegs_With_AGPRs_RegMask : CSR_AMDGPU_HighRegs_RegMask ; default : return nullptr ; } } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


"Can't store this register to stack slot"


<s>
bool
FixupLEAPass
::
runOnMachineFunction
(
MachineFunction
&
Func
)
{
if
(
skipFunction
(
Func
.
getFunction
(
)
)
)
return
false
;
MF
=
&
Func
;
const
X86Subtarget
&
ST
=
Func
.
getSubtarget
<
X86Subtarget
>
(
)
;
OptIncDec
=
!
ST
.
slowIncDec
(
)
||
Func
.
getFunction
(
)
.
optForMinSize
(
)
;
OptLEA
=
ST
.
LEAusesAG
(
)
||
ST
.
slowLEA
(
)
||
ST
.
slow3OpsLEA
(
)
;
if
(
!
OptLEA
&&
!
OptIncDec
)
return
false
;
TII
=
ST
.
getInstrInfo
(
)
;
DEBUG
(
dbgs
(
)
<<
"Start X86FixupLEAs\n"
;
)
;
for
(
MachineFunction
::
iterator
I
=
Func
.
begin
(
)
,
E
=
Func
.
end
(
)
;
I
!=
E
;
++
I
)
processBasicBlock
(
Func
,
I
)
;
DEBUG
(
dbgs
(
)
<<
"End X86FixupLEAs\n"
;
)
;
return
true
;
}
</s>


<s> static bool expand_vec_perm_interleave3 ( struct expand_vec_perm_d * d ) { unsigned i , nelt ; rtx ( * gen ) ( rtx , rtx , rtx ) ; if ( d -> one_operand_p ) return false ; if ( TARGET_AVX2 && GET_MODE_SIZE ( d -> vmode ) == 32 ) ; else if ( TARGET_AVX && ( d -> vmode == V8SFmode || d -> vmode == V4DFmode ) ) ; else return false ; nelt = d -> nelt ; if ( d -> perm [ 0 ] != 0 && d -> perm [ 0 ] != nelt / 2 ) return false ; for ( i = 0 ; i < nelt ; i += 2 ) if ( d -> perm [ i ] != d -> perm [ 0 ] + i / 2 || d -> perm [ i + 1 ] != d -> perm [ 0 ] + i / 2 + nelt ) return false ; if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V32QImode : if ( d -> perm [ 0 ] ) gen = gen_vec_interleave_highv32qi ; else gen = gen_vec_interleave_lowv32qi ; break ; case V16HImode : if ( d -> perm [ 0 ] ) gen = gen_vec_interleave_highv16hi ; else gen = gen_vec_interleave_lowv16hi ; break ; case V8SImode : if ( d -> perm [ 0 ] ) gen = gen_vec_interleave_highv8si ; else gen = gen_vec_interleave_lowv8si ; break ; case V4DImode : if ( d -> perm [ 0 ] ) gen = gen_vec_interleave_highv4di ; else gen = gen_vec_interleave_lowv4di ; break ; case V8SFmode : if ( d -> perm [ 0 ] ) gen = gen_vec_interleave_highv8sf ; else gen = gen_vec_interleave_lowv8sf ; break ; case V4DFmode : if ( d -> perm [ 0 ] ) gen = gen_vec_interleave_highv4df ; else gen = gen_vec_interleave_lowv4df ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( d -> target , d -> op0 , d -> op1 ) ) ; return true ; } </s>

A subroutine of ix86_expand_vec_perm_builtin_1 . Try to simplify a two vector permutation using 2 intra-lane interleave insns and cross-lane shuffle for 32-byte vectors .


<s>
static
MCSymbol
*
GetSymbolFromOperand
(
const
MachineOperand
&
MO
,
AsmPrinter
&
AP
)
{
const
TargetMachine
&
TM
=
AP
.
TM
;
Mangler
*
Mang
=
AP
.
Mang
;
const
DataLayout
&
DL
=
AP
.
getDataLayout
(
)
;
MCContext
&
Ctx
=
AP
.
OutContext
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
Suffix
=
"$non_lazy_ptr"
;
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
.
getPrivateGlobalPrefix
(
)
;
if
(
!
MO
.
isGlobal
(
)
)
{
assert
(
MO
.
isSymbol
(
)
&&
"Isn't a symbol reference"
)
;
Mangler
::
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
,
DL
)
;
}
else
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
TM
.
getNameWithPrefix
(
Name
,
GV
,
*
Mang
)
;
}
Name
+=
Suffix
;
MCSymbol
*
Sym
=
Ctx
.
getOrCreateSymbol
(
Name
)
;
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
{
MachineModuleInfoMachO
&
MachO
=
getMachOMMI
(
AP
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
MachO
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
return
Sym
;
}
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


<s> unsigned MBlazeInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == MBlaze :: LWI ) { if ( ( MI -> getOperand ( 2 ) . isFI ( ) ) && ( MI -> getOperand ( 1 ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( 1 ) ) ) ) { FrameIndex = MI -> getOperand ( 2 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> bool X86TargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { if ( ! CI -> isTailCall ( ) ) return false ; ImmutableCallSite CS ( CI ) ; CallingConv :: ID CalleeCC = CS . getCallingConv ( ) ; if ( ! mayTailCallThisCC ( CalleeCC ) ) return false ; return true ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> bool ARMTargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const { if ( ! Subtarget -> isThumb ( ) ) return ARM_AM :: getSOImmVal ( std :: abs ( Imm ) ) != - 1 ; if ( Subtarget -> isThumb2 ( ) ) return ARM_AM :: getT2SOImmVal ( std :: abs ( Imm ) ) != - 1 ; return Imm >= 0 && Imm <= 255 ; } </s>

Return true if the specified immediate is legal icmp immediate , that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register .


<s> static void ix86_elim_entry_set_got ( rtx reg ) { basic_block bb = ENTRY_BLOCK_PTR_FOR_FN ( cfun ) -> next_bb ; rtx_insn * c_insn = BB_HEAD ( bb ) ; if ( ! NONDEBUG_INSN_P ( c_insn ) ) c_insn = next_nonnote_nondebug_insn ( c_insn ) ; if ( c_insn && NONJUMP_INSN_P ( c_insn ) ) { rtx pat = PATTERN ( c_insn ) ; if ( GET_CODE ( pat ) == PARALLEL ) { rtx vec = XVECEXP ( pat , 0 , 0 ) ; if ( GET_CODE ( vec ) == SET && XINT ( XEXP ( vec , 1 ) , 1 ) == UNSPEC_SET_GOT && REGNO ( XEXP ( vec , 0 ) ) == REGNO ( reg ) ) delete_insn ( c_insn ) ; } } } </s>

Delete SET_GOT right after entry block if it is allocated to reg .


<s> bool AArch64FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * RegInfo , std :: vector < CalleeSavedInfo > & CSI , unsigned & MinCSFrameIndex , unsigned & MaxCSFrameIndex ) const { if ( CSI . empty ( ) ) return true ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto AFI = MF . getInfo < AArch64FunctionInfo > ( ) ; for ( auto & CS : CSI ) { unsigned Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = RegInfo -> getMinimalPhysRegClass ( Reg ) ; int FrameIdx ; unsigned Size = RegInfo -> getSpillSize ( * RC ) ; Align Alignment ( RegInfo -> getSpillAlignment ( * RC ) ) ; FrameIdx = MFI . CreateStackObject ( Size , Alignment , true ) ; CS . setFrameIdx ( FrameIdx ) ; if ( ( unsigned ) FrameIdx < MinCSFrameIndex ) MinCSFrameIndex = FrameIdx ; if ( ( unsigned ) FrameIdx > MaxCSFrameIndex ) MaxCSFrameIndex = FrameIdx ; if ( hasFP ( MF ) && AFI -> hasSwiftAsyncContext ( ) && Reg == AArch64 :: FP ) { FrameIdx = MFI . CreateStackObject ( 8 , Alignment , true ) ; AFI -> setSwiftAsyncContextFrameIdx ( FrameIdx ) ; if ( ( unsigned ) FrameIdx < MinCSFrameIndex ) MinCSFrameIndex = FrameIdx ; if ( ( unsigned ) FrameIdx > MaxCSFrameIndex ) MaxCSFrameIndex = FrameIdx ; } } return true ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> static pad_direction sparc_function_arg_padding ( machine_mode mode , const_tree type ) { if ( TARGET_ARCH64 && type && AGGREGATE_TYPE_P ( type ) ) return PAD_UPWARD ; return default_function_arg_padding ( mode , type ) ; } </s>

Implement TARGET_FUNCTION_ARG_PADDING . For the 64-bit ABI structs are always stored left shifted in their argument slot .


<s> static int interrupt_function_p ( tree func ) { tree a ; if ( TREE_CODE ( func ) != FUNCTION_DECL ) return 0 ; a = lookup_attribute ( "interrupt" , DECL_ATTRIBUTES ( func ) ) ; return a != NULL_TREE ; } </s>

Return nonzero if FUNC is an interrupt function as specified by the `` interrupt '' attribute .


<s>
MachineInstr
*
LanaiInstrInfo
::
optimizeSelect
(
MachineInstr
&
MI
,
SmallPtrSetImpl
<
MachineInstr
*
>
&
SeenMIs
,
bool
PreferFalse
)
const
{
assert
(
MI
.
getOpcode
(
)
==
Lanai
::
SELECT
&&
"unknown select instruction"
)
;
MachineRegisterInfo
&
MRI
=
MI
.
getParent
(
)
->
getParent
(
)
->
getRegInfo
(
)
;
MachineInstr
*
DefMI
=
canFoldIntoSelect
(
MI
.
getOperand
(
1
)
.
getReg
(
)
,
MRI
,
this
)
;
bool
Invert
=
!
DefMI
;
if
(
!
DefMI
)
DefMI
=
canFoldIntoSelect
(
MI
.
getOperand
(
2
)
.
getReg
(
)
,
MRI
,
this
)
;
if
(
!
DefMI
)
return
nullptr
;
MachineOperand
FalseReg
=
MI
.
getOperand
(
Invert
1
:
2
)
;
unsigned
DestReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
const
TargetRegisterClass
*
PreviousClass
=
MRI
.
getRegClass
(
FalseReg
.
getReg
(
)
)
;
if
(
!
MRI
.
constrainRegClass
(
DestReg
,
PreviousClass
)
)
return
nullptr
;
MachineInstrBuilder
NewMI
=
BuildMI
(
*
MI
.
getParent
(
)
,
MI
,
MI
.
getDebugLoc
(
)
,
DefMI
->
getDesc
(
)
,
DestReg
)
;
const
MCInstrDesc
&
DefDesc
=
DefMI
->
getDesc
(
)
;
for
(
unsigned
i
=
1
,
e
=
DefDesc
.
getNumOperands
(
)
;
i
!=
e
&&
!
DefDesc
.
OpInfo
[
i
]
.
isPredicate
(
)
;
++
i
)
NewMI
.
addOperand
(
DefMI
->
getOperand
(
i
)
)
;
unsigned
CondCode
=
MI
.
getOperand
(
3
)
.
getImm
(
)
;
if
(
Invert
)
NewMI
.
addImm
(
getOppositeCondition
(
LPCC
::
CondCode
(
CondCode
)
)
)
;
else
NewMI
.
addImm
(
CondCode
)
;
NewMI
.
copyImplicitOps
(
MI
)
;
FalseReg
.
setImplicit
(
)
;
NewMI
.
addOperand
(
FalseReg
)
;
NewMI
->
tieOperands
(
0
,
NewMI
->
getNumOperands
(
)
1
)
;
SeenMIs
.
insert
(
NewMI
)
;
SeenMIs
.
erase
(
DefMI
)
;
if
(
DefMI
->
getParent
(
)
!=
MI
.
getParent
(
)
)
NewMI
->
clearKillInfo
(
)
;
DefMI
->
eraseFromParent
(
)
;
return
NewMI
;
}
</s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


<s>
const
RegisterBank
&
M88kRegisterBankInfo
::
getRegBankFromRegClass
(
const
TargetRegisterClass
&
RC
,
LLT
Ty
)
const
{
switch
(
RC
.
getID
(
)
)
{
case
M88k
::
GPRRCRegClassID
:
case
M88k
::
GPR64RCRegClassID
:
return
getRegBank
(
M88k
::
GRRegBankID
)
;
case
M88k
::
XRRCRegClassID
:
return
getRegBank
(
M88k
::
XRRegBankID
)
;
default
:
llvm_unreachable
(
"Unexpected register class"
)
;
}
}
</s>


<s> rtx rs6000_emit_eqne ( machine_mode mode , rtx op1 , rtx op2 , rtx scratch ) { if ( op2 == const0_rtx ) return op1 ; if ( GET_CODE ( scratch ) == SCRATCH ) scratch = gen_reg_rtx ( mode ) ; if ( logical_operand ( op2 , mode ) ) emit_insn ( gen_rtx_SET ( VOIDmode , scratch , gen_rtx_XOR ( mode , op1 , op2 ) ) ) ; else emit_insn ( gen_rtx_SET ( VOIDmode , scratch , gen_rtx_PLUS ( mode , op1 , negate_rtx ( mode , op2 ) ) ) ) ; return scratch ; } </s>

Emit RTL that sets a register to zero if OP1 and OP2 are equal . SCRATCH can be used as that dest register . Return the dest register .


<s> const char * output_branchy_insn ( enum rtx_code code , const char * template , rtx insn , rtx * operands ) { rtx next_insn = NEXT_INSN ( insn ) ; if ( next_insn && GET_CODE ( next_insn ) == JUMP_INSN && condjump_p ( next_insn ) ) { rtx src = SET_SRC ( PATTERN ( next_insn ) ) ; if ( GET_CODE ( src ) == IF_THEN_ELSE && GET_CODE ( XEXP ( src , 0 ) ) != code ) { operands [ 9 ] = gen_label_rtx ( ) ; emit_label_after ( operands [ 9 ] , next_insn ) ; INSN_ADDRESSES_NEW ( operands [ 9 ] , INSN_ADDRESSES ( INSN_UID ( next_insn ) ) + get_attr_length ( next_insn ) ) ; return template ; } else { int offset = ( branch_dest ( next_insn ) - INSN_ADDRESSES ( INSN_UID ( next_insn ) ) + 4 ) ; if ( offset >= - 252 && offset <= 258 ) { if ( GET_CODE ( src ) == IF_THEN_ELSE ) src = XEXP ( src , 1 ) ; operands [ 9 ] = src ; return template ; } } } operands [ 9 ] = gen_label_rtx ( ) ; emit_label_after ( operands [ 9 ] , insn ) ; INSN_ADDRESSES_NEW ( operands [ 9 ] , INSN_ADDRESSES ( INSN_UID ( insn ) ) + get_attr_length ( insn ) ) ; return template ; } </s>

Output a code sequence for INSN using TEMPL with OPERANDS ; but before , fill in operands 9 as a label to the successor insn . We try to use jump threading where possible . IF CODE matches the comparison in the IF_THEN_ELSE of a following jump , we assume the jump is taken . I.e . EQ means follow jmp and bf , NE means follow jmp and bt , if the address is in range .


"SCC used by terminator but no def in block"

Return a point at the end of the given MBB to insert SALU instructions for lane mask calculation .


<s> static tree make_resolver_func ( const tree default_decl , const tree ifunc_alias_decl , basic_block * empty_bb ) { char * resolver_name ; tree decl , type , decl_name , t ; if ( TREE_PUBLIC ( default_decl ) == 0 ) { char * ifunc_name = make_unique_name ( default_decl , "ifunc" , true ) ; symtab -> change_decl_assembler_name ( ifunc_alias_decl , get_identifier ( ifunc_name ) ) ; XDELETEVEC ( ifunc_name ) ; } resolver_name = make_unique_name ( default_decl , "resolver" , false ) ; type = build_function_type_list ( ptr_type_node , NULL_TREE ) ; decl = build_fn_decl ( resolver_name , type ) ; decl_name = get_identifier ( resolver_name ) ; SET_DECL_ASSEMBLER_NAME ( decl , decl_name ) ; DECL_NAME ( decl ) = decl_name ; TREE_USED ( decl ) = 1 ; DECL_ARTIFICIAL ( decl ) = 1 ; DECL_IGNORED_P ( decl ) = 1 ; TREE_PUBLIC ( decl ) = 0 ; DECL_UNINLINABLE ( decl ) = 1 ; DECL_EXTERNAL ( decl ) = 0 ; DECL_EXTERNAL ( ifunc_alias_decl ) = 0 ; DECL_CONTEXT ( decl ) = NULL_TREE ; DECL_INITIAL ( decl ) = make_node ( BLOCK ) ; DECL_STATIC_CONSTRUCTOR ( decl ) = 0 ; if ( DECL_COMDAT_GROUP ( default_decl ) || TREE_PUBLIC ( default_decl ) ) { DECL_COMDAT ( decl ) = 1 ; make_decl_one_only ( decl , DECL_ASSEMBLER_NAME ( decl ) ) ; } t = build_decl ( UNKNOWN_LOCATION , RESULT_DECL , NULL_TREE , ptr_type_node ) ; DECL_ARTIFICIAL ( t ) = 1 ; DECL_IGNORED_P ( t ) = 1 ; DECL_RESULT ( decl ) = t ; gimplify_function_tree ( decl ) ; push_cfun ( DECL_STRUCT_FUNCTION ( decl ) ) ; * empty_bb = init_lowered_empty_function ( decl , false , profile_count :: uninitialized ( ) ) ; cgraph_node :: add_new_function ( decl , true ) ; symtab -> call_cgraph_insertion_hooks ( cgraph_node :: get_create ( decl ) ) ; pop_cfun ( ) ; gcc_assert ( ifunc_alias_decl != NULL ) ; DECL_ATTRIBUTES ( ifunc_alias_decl ) = make_attribute ( "ifunc" , resolver_name , DECL_ATTRIBUTES ( ifunc_alias_decl ) ) ; cgraph_node :: create_same_body_alias ( ifunc_alias_decl , decl ) ; XDELETEVEC ( resolver_name ) ; return decl ; } </s>

Make the resolver function decl to dispatch the versions of a multi- versioned function , DEFAULT_DECL . Create an empty basic block in the resolver and store the pointer in EMPTY_BB . Return the decl of the resolver function .


<s> EVT M680x0TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & Context , EVT VT ) const { return MVT :: i8 ; } </s>

Return the value type to use for ISD : :SETCC .


<s> MachineBasicBlock :: iterator eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const override { return MBB . erase ( MI ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> int fp_sethi_p ( rtx op ) { if ( GET_CODE ( op ) == CONST_DOUBLE ) { REAL_VALUE_TYPE r ; long i ; REAL_VALUE_FROM_CONST_DOUBLE ( r , op ) ; REAL_VALUE_TO_TARGET_SINGLE ( r , i ) ; return ! SPARC_SIMM13_P ( i ) && SPARC_SETHI_P ( i ) ; } return 0 ; } </s>

Nonzero if OP is a floating point constant which can be loaded into an integer register using a single sethi instruction .


"CFProtection used on invalid architecture!"

This virtual method can be overridden by targets that want to emit something at the start of their file .


<s> ScheduleHazardRecognizer * PPCInstrInfo :: CreateTargetHazardRecognizer ( const TargetMachine * TM , const ScheduleDAG * DAG ) const { unsigned Directive = TM -> getSubtarget < PPCSubtarget > ( ) . getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_440 || Directive == PPC :: DIR_A2 ) { const InstrItineraryData * II = TM -> getInstrItineraryData ( ) ; return new PPCScoreboardHazardRecognizer ( II , DAG ) ; } return TargetInstrInfoImpl :: CreateTargetHazardRecognizer ( TM , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .

PowerPC PPC PPC PPC::DIR_440 PPC::DIR_A2 PPC


<s> static bool bfin_can_use_doloop_p ( const widest_int & , const widest_int & iterations_max , unsigned int , bool ) { return ( wi :: ltu_p ( iterations_max , 0xFFFFFFFF ) ) ; } </s>


<s> static void pro_epilogue_adjust_stack ( rtx dest , rtx src , rtx offset , int style ) { rtx insn ; if ( ! TARGET_64BIT ) insn = emit_insn ( gen_pro_epilogue_adjust_stack_1 ( dest , src , offset ) ) ; else if ( x86_64_immediate_operand ( offset , DImode ) ) insn = emit_insn ( gen_pro_epilogue_adjust_stack_rex64 ( dest , src , offset ) ) ; else { rtx r11 ; gcc_assert ( style ) ; r11 = gen_rtx_REG ( DImode , FIRST_REX_INT_REG + 3 ) ; insn = emit_insn ( gen_rtx_SET ( DImode , r11 , offset ) ) ; if ( style < 0 ) RTX_FRAME_RELATED_P ( insn ) = 1 ; insn = emit_insn ( gen_pro_epilogue_adjust_stack_rex64_2 ( dest , src , r11 , offset ) ) ; } if ( style < 0 ) RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Expand prologue or epilogue stack adjustment . The pattern exist to put a dependency on all ebp-based memory accesses . STYLE should be negative if instructions should be marked as frame related , zero if % r11 register is live and can not be freely used and positive otherwise .


<s> void aarch64_post_cfi_startproc ( FILE * f , tree ignored ATTRIBUTE_UNUSED ) { if ( cfun -> machine -> frame . laid_out && aarch64_return_address_signing_enabled ( ) && aarch64_ra_sign_key == AARCH64_KEY_B ) asm_fprintf ( f , "\t.cfi_b_key_frame\n" ) ; } </s>

Triggered after a .cfi_startproc directive is emitted into the assembly file . Used to output the .cfi_b_key_frame directive when signing the current function with the B key .


<s> static void mips16_fp_args ( FILE * file , int fp_code , int from_fp_p ) { const char * s ; int gparg , fparg ; unsigned int f ; gcc_assert ( TARGET_OLDABI ) ; if ( from_fp_p ) s = "mfc1" ; else s = "mtc1" ; gparg = GP_ARG_FIRST ; fparg = FP_ARG_FIRST ; for ( f = ( unsigned int ) fp_code ; f != 0 ; f >>= 2 ) { if ( ( f & 3 ) == 1 ) { if ( ( fparg & 1 ) != 0 ) ++ fparg ; fprintf ( file , "\t%s\t%s,%s\n" , s , reg_names [ gparg ] , reg_names [ fparg ] ) ; } else if ( ( f & 3 ) == 2 ) { if ( TARGET_64BIT ) fprintf ( file , "\td%s\t%s,%s\n" , s , reg_names [ gparg ] , reg_names [ fparg ] ) ; else { if ( ( fparg & 1 ) != 0 ) ++ fparg ; if ( TARGET_BIG_ENDIAN ) fprintf ( file , "\t%s\t%s,%s\n\t%s\t%s,%s\n" , s , reg_names [ gparg ] , reg_names [ fparg + 1 ] , s , reg_names [ gparg + 1 ] , reg_names [ fparg ] ) ; else fprintf ( file , "\t%s\t%s,%s\n\t%s\t%s,%s\n" , s , reg_names [ gparg ] , reg_names [ fparg ] , s , reg_names [ gparg + 1 ] , reg_names [ fparg + 1 ] ) ; ++ gparg ; ++ fparg ; } } else gcc_unreachable ( ) ; ++ gparg ; ++ fparg ; } } </s>

Write out code to move floating point arguments in or out of general registers . Output the instructions to FILE . FP_CODE is the code describing which arguments are present ( see the comment at the definition of CUMULATIVE_ARGS in mips.h ) . FROM_FP_P is nonzero if we are copying from the floating point registers .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool AArch64PreLegalizerCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: FailedISel ) ) return false ; auto * TPC = & getAnalysis < TargetPassConfig > ( ) ; AArch64PreLegalizerCombinerInfo PCInfo ; Combiner C ( PCInfo , TPC ) ; return C . combineMachineInstrs ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool sh_legitimate_combined_insn ( rtx_insn * insn ) { rtx p = PATTERN ( insn ) ; if ( GET_CODE ( p ) == SET && REG_P ( XEXP ( p , 0 ) ) && GET_MODE ( XEXP ( p , 0 ) ) == SImode && GET_CODE ( XEXP ( p , 1 ) ) == ZERO_EXTEND && MEM_P ( XEXP ( XEXP ( p , 1 ) , 0 ) ) ) return false ; return true ; } </s>

This function implements the legitimate_combined_insn target hook , which the combine pass uses to early reject combined insns , before it tries to recog the insn and determine its cost .


<s> void X86IntelInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot ) { printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAnyX86InstComments ( MI , * CommentStream , getRegisterName ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static bool get_memref_parts ( rtx mem , rtx * base , HOST_WIDE_INT * offset , HOST_WIDE_INT * size ) { rtx addr_rtx ; if ( MEM_SIZE_KNOWN_P ( mem ) ) * size = MEM_SIZE ( mem ) ; else return false ; addr_rtx = ( XEXP ( mem , 0 ) ) ; if ( GET_CODE ( addr_rtx ) == PRE_MODIFY ) addr_rtx = XEXP ( addr_rtx , 1 ) ; * offset = 0 ; while ( GET_CODE ( addr_rtx ) == PLUS && CONST_INT_P ( XEXP ( addr_rtx , 1 ) ) ) { * offset += INTVAL ( XEXP ( addr_rtx , 1 ) ) ; addr_rtx = XEXP ( addr_rtx , 0 ) ; } if ( ! REG_P ( addr_rtx ) ) return false ; * base = addr_rtx ; return true ; } </s>

Try to determine base/offset/size parts of the given MEM . Return true if successful , false if all the values could n't be determined . This function only looks for REG or REG+CONST address forms . REG+REG address form will return false .


<s> void Initialize ( const MachineFunction & MF , bool isPIC ) { const ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; ConstPoolId2AddrMap . resize ( AFI -> getNumPICLabels ( ) ) ; JumpTableId2AddrMap . resize ( AFI -> getNumJumpTables ( ) ) ; IsPIC = isPIC ; } </s>

This method must be called before any actual lowering is done .


<s> bool isToken ( ) const override { return Kind == k_Token ; } </s>


"Splitting double registers in function: "

"Register partitioning: (partition #0 is fixed)\n"


<s>
void
FISCMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
if
(
Desc
.
getSize
(
)
!=
4
)
{
llvm_unreachable
(
"Unexpected instruction size!"
)
;
}
const
uint32_t
Binary
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
EmitConstant
(
Binary
,
Desc
.
getSize
(
)
,
OS
)
;
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .

FISC
FISC
4
"Unexpected instruction size!"


<s> bool M68kFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) && ! MF . getInfo < M68kMachineFunctionInfo > ( ) -> getHasPushSequences ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> int registers_ok_for_quad_peep ( rtx reg1 , rtx reg2 ) { if ( ! REG_P ( reg1 ) || ! REG_P ( reg2 ) ) return 0 ; if ( ! FP_REGNO_P ( REGNO ( reg1 ) ) || ! FP_REGNO_P ( REGNO ( reg2 ) ) ) return 0 ; return ( REGNO ( reg1 ) == REGNO ( reg2 ) - 1 ) ; } </s>

Return 1 if REGNO ( reg1 ) == REGNO ( reg2 ) - 1 making them candidates for lfq and stfq insns . Note reg1 and reg2 * must * be hard registers . To be sure we will abort if we are passed pseudo registers .


<s> bool Thumb1FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; bool isVarArg = AFI -> getArgRegsSaveSize ( ) > 0 ; DebugLoc DL = MI != MBB . end ( ) ? MI -> getDebugLoc ( ) : DebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , TII . get ( ARM :: tPOP ) ) ; AddDefaultPred ( MIB ) ; bool NumRegs = false ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( Reg == ARM :: LR && MBB . succ_empty ( ) ) { if ( isVarArg ) continue ; if ( ! STI . hasV5TOps ( ) ) continue ; Reg = ARM :: PC ; ( * MIB ) . setDesc ( TII . get ( ARM :: tPOP_RET ) ) ; if ( MI != MBB . end ( ) ) MIB . copyImplicitOps ( & * MI ) ; MI = MBB . erase ( MI ) ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; NumRegs = true ; } if ( NumRegs ) MBB . insert ( MI , & * MIB ) ; else MF . DeleteMachineInstr ( MIB ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> const MINA32Subtarget * MINA32TargetMachine :: getSubtargetImpl ( const Function & ) const { return & SubTarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static unsigned int c6x_function_arg_round_boundary ( machine_mode mode , const_tree type ) { return c6x_function_arg_boundary ( mode , type ) ; } </s>


<s> unsigned Cpu0AsmParser :: getReg ( int RC , int RegNo ) { return * ( getContext ( ) . getRegisterInfo ( ) -> getRegClass ( RC ) . begin ( ) + RegNo ) ; } </s>

Returns the register associated with this edge .


<s> static rtx gen_pop ( rtx arg ) { if ( REG_P ( arg ) && GET_MODE ( arg ) != word_mode ) arg = gen_rtx_REG ( word_mode , REGNO ( arg ) ) ; return gen_rtx_SET ( arg , gen_rtx_MEM ( word_mode , gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ) ) ; } </s>

Generate an `` pop '' pattern for input ARG .


"Cannot handle this call frame pseudo instruction"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> rtx rs6000_find_base_term ( rtx op ) { rtx base ; base = op ; if ( GET_CODE ( base ) == CONST ) base = XEXP ( base , 0 ) ; if ( GET_CODE ( base ) == PLUS ) base = XEXP ( base , 0 ) ; if ( GET_CODE ( base ) == UNSPEC ) switch ( XINT ( base , 1 ) ) { case UNSPEC_TOCREL : case UNSPEC_MACHOPIC_OFFSET : return XVECEXP ( base , 0 , 0 ) ; } return op ; } </s>


<s>
int
AArch64LoadStoreOpt
::
getMemSize
(
MachineInstr
*
MemMI
)
{
switch
(
MemMI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Opcode has unknown size!"
)
;
case
AArch64
::
STRSui
:
case
AArch64
::
STURSi
:
return
4
;
case
AArch64
::
STRDui
:
case
AArch64
::
STURDi
:
return
8
;
case
AArch64
::
STRQui
:
case
AArch64
::
STURQi
:
return
16
;
case
AArch64
::
STRWui
:
case
AArch64
::
STURWi
:
return
4
;
case
AArch64
::
STRXui
:
case
AArch64
::
STURXi
:
return
8
;
case
AArch64
::
LDRSui
:
case
AArch64
::
LDURSi
:
return
4
;
case
AArch64
::
LDRDui
:
case
AArch64
::
LDURDi
:
return
8
;
case
AArch64
::
LDRQui
:
case
AArch64
::
LDURQi
:
return
16
;
case
AArch64
::
LDRWui
:
case
AArch64
::
LDURWi
:
return
4
;
case
AArch64
::
LDRXui
:
case
AArch64
::
LDURXi
:
return
8
;
}
}
</s>

Returns the size in bytes of the memory access .


<s> static bool xtensa_output_addr_const_extra ( FILE * fp , rtx x ) { if ( GET_CODE ( x ) == UNSPEC && XVECLEN ( x , 0 ) == 1 ) { switch ( XINT ( x , 1 ) ) { case UNSPEC_TPOFF : output_addr_const ( fp , XVECEXP ( x , 0 , 0 ) ) ; fputs ( "@TPOFF" , fp ) ; return true ; case UNSPEC_DTPOFF : output_addr_const ( fp , XVECEXP ( x , 0 , 0 ) ) ; fputs ( "@DTPOFF" , fp ) ; return true ; case UNSPEC_PLT : if ( flag_pic ) { output_addr_const ( fp , XVECEXP ( x , 0 , 0 ) ) ; fputs ( "@PLT" , fp ) ; return true ; } break ; default : break ; } } return false ; } </s>


<s>
const
char
*
getPassName
(
)
const
override
{
return
"WebAssembly Register Numbering"
;
}
</s>

getPassName - Return a nice clean name for a pass .

WebAssembly
"WebAssembly Register Numbering"


<s> static const char * arm_identify_fpu_from_isa ( sbitmap isa ) { auto_sbitmap fpubits ( isa_num_bits ) ; auto_sbitmap cand_fpubits ( isa_num_bits ) ; bitmap_and ( fpubits , isa , isa_all_fpubits ) ; if ( bitmap_empty_p ( fpubits ) ) return "softvfp" ; for ( unsigned int i = 0 ; i < TARGET_FPU_auto ; i ++ ) { arm_initialize_isa ( cand_fpubits , all_fpus [ i ] . isa_bits ) ; if ( bitmap_equal_p ( fpubits , cand_fpubits ) ) return all_fpus [ i ] . name ; } gcc_unreachable ( ) ; } </s>

Match an ISA feature bitmap to a named FPU . We always use the first entry that exactly matches the feature set , so that we effectively canonicalize the FPU name for the assembler .


<s>
SDNode
*
MipsDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
nullptr
;
}
std
::
pair
<
bool
,
SDNode
*
>
Ret
=
selectNode
(
Node
)
;
if
(
Ret
.
first
)
return
Ret
.
second
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
return
getGlobalBaseReg
(
)
;
case
ISD
::
LOAD
:
case
ISD
::
STORE
:
assert
(
cast
<
MemSDNode
>
(
Node
)
->
getMemoryVT
(
)
.
getSizeInBits
(
)
/
8
<=
cast
<
MemSDNode
>
(
Node
)
->
getAlignment
(
)
&&
"Unexpected unaligned loads/stores."
)
;
break
;
}
SDNode
*
ResNode
=
SelectCode
(
Node
)
;
DEBUG
(
errs
(
)
<<
"=> "
)
;
if
(
ResNode
==
nullptr
||
ResNode
==
Node
)
DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
else
DEBUG
(
ResNode
->
dump
(
CurDAG
)
)
;
DEBUG
(
errs
(
)
<<
"\n"
)
;
return
ResNode
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

Mips
Mips
"Selecting: "
"\n"
"== "
"\n"
1
ISD::GLOBAL_OFFSET_TABLE
ISD::LOAD
ISD::STORE
8
"Unexpected unaligned loads/stores."
"=> "
"\n"


<s> static void alpha_expand_unaligned_load_words ( rtx * out_regs , rtx smem , HOST_WIDE_INT words , HOST_WIDE_INT ofs ) { rtx const im8 = GEN_INT ( - 8 ) ; rtx ext_tmps [ MAX_MOVE_WORDS ] , data_regs [ MAX_MOVE_WORDS + 1 ] ; rtx sreg , areg , tmp , smema ; HOST_WIDE_INT i ; smema = XEXP ( smem , 0 ) ; if ( GET_CODE ( smema ) == LO_SUM ) smema = force_reg ( Pmode , smema ) ; for ( i = 0 ; i < words ; ++ i ) { data_regs [ i ] = out_regs [ i ] ; ext_tmps [ i ] = gen_reg_rtx ( DImode ) ; } data_regs [ words ] = gen_reg_rtx ( DImode ) ; if ( ofs != 0 ) smem = adjust_address ( smem , GET_MODE ( smem ) , ofs ) ; for ( i = 0 ; i < words ; ++ i ) { tmp = change_address ( smem , DImode , gen_rtx_AND ( DImode , plus_constant ( DImode , smema , 8 * i ) , im8 ) ) ; set_mem_alias_set ( tmp , 0 ) ; emit_move_insn ( data_regs [ i ] , tmp ) ; } tmp = change_address ( smem , DImode , gen_rtx_AND ( DImode , plus_constant ( DImode , smema , 8 * words - 1 ) , im8 ) ) ; set_mem_alias_set ( tmp , 0 ) ; emit_move_insn ( data_regs [ words ] , tmp ) ; sreg = copy_addr_to_reg ( smema ) ; areg = expand_binop ( DImode , and_optab , sreg , GEN_INT ( 7 ) , NULL , 1 , OPTAB_WIDEN ) ; for ( i = 0 ; i < words ; ++ i ) { emit_insn ( gen_extql ( data_regs [ i ] , data_regs [ i ] , sreg ) ) ; emit_insn ( gen_extqh ( ext_tmps [ i ] , data_regs [ i + 1 ] , sreg ) ) ; emit_insn ( gen_rtx_SET ( ext_tmps [ i ] , gen_rtx_IF_THEN_ELSE ( DImode , gen_rtx_EQ ( DImode , areg , const0_rtx ) , const0_rtx , ext_tmps [ i ] ) ) ) ; } for ( i = 0 ; i < words ; ++ i ) { out_regs [ i ] = expand_binop ( DImode , ior_optab , data_regs [ i ] , ext_tmps [ i ] , data_regs [ i ] , 1 , OPTAB_WIDEN ) ; } } </s>

Load an integral number of consecutive unaligned quadwords .


<s> static void gr5_hazard_avoidance ( void ) { unsigned int last_reg = 0 ; bool last_insn_call = false ; rtx_insn * insn ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) ) { rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == SEQUENCE ) { for ( int i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) gr5_avoid_hazard ( as_a < rtx_insn * > ( XVECEXP ( pat , 0 , i ) ) , & last_reg , & last_insn_call ) ; } else if ( GET_CODE ( insn ) == CALL_INSN ) { last_reg = 0 ; last_insn_call = false ; } else gr5_avoid_hazard ( insn , & last_reg , & last_insn_call ) ; } else if ( GET_CODE ( insn ) == BARRIER ) last_reg = 0 ; } </s>

Go through the instruction stream and insert nops where necessary to avoid pipeline hazards . There are two cases : 1 . On the original architecture , it is invalid to set the value of a ( base ) register and then use it in an address with a non-zero index in the next instruction . 2 . On the MCM , setting the value of a ( base ) register and then using it in address ( including with zero index ) in the next instruction will result in a pipeline stall of 3 cycles .


<s> PPCTargetLowering :: ConstraintType PPCTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'b' : case 'r' : case 'f' : case 'v' : case 'y' : return C_RegisterClass ; case 'Z' : return C_Memory ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> bool AMDGPUAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( AMDGPU :: IsaInfo :: hasCodeObjectV3 ( & getSTI ( ) ) ) { if ( IDVal == ".amdgcn_target" ) return ParseDirectiveAMDGCNTarget ( ) ; if ( IDVal == ".amdhsa_kernel" ) return ParseDirectiveAMDHSAKernel ( ) ; if ( IDVal == AMDGPU :: HSAMD :: V3 :: AssemblerDirectiveBegin ) return ParseDirectiveHSAMetadata ( ) ; } else { if ( IDVal == ".hsa_code_object_version" ) return ParseDirectiveHSACodeObjectVersion ( ) ; if ( IDVal == ".hsa_code_object_isa" ) return ParseDirectiveHSACodeObjectISA ( ) ; if ( IDVal == ".amd_kernel_code_t" ) return ParseDirectiveAMDKernelCodeT ( ) ; if ( IDVal == ".amdgpu_hsa_kernel" ) return ParseDirectiveAMDGPUHsaKernel ( ) ; if ( IDVal == ".amd_amdgpu_isa" ) return ParseDirectiveISAVersion ( ) ; if ( IDVal == AMDGPU :: HSAMD :: AssemblerDirectiveBegin ) return ParseDirectiveHSAMetadata ( ) ; } if ( IDVal == PALMD :: AssemblerDirectiveBegin ) return ParseDirectivePALMetadataBegin ( ) ; if ( IDVal == PALMD :: AssemblerDirective ) return ParseDirectivePALMetadata ( ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s>
void
AVRMCInstLower
::
lowerInstruction
(
const
MachineInstr
&
MI
,
MCInst
&
OutMI
)
const
{
OutMI
.
setOpcode
(
MI
.
getOpcode
(
)
)
;
for
(
MachineOperand
const
&
MO
:
MI
.
operands
(
)
)
{
MCOperand
MCOp
;
switch
(
MO
.
getType
(
)
)
{
default
:
MI
.
print
(
errs
(
)
)
;
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
)
continue
;
MCOp
=
MCOperand
::
createReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
createImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
getSymbol
(
MO
.
getGlobal
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
createExpr
(
MCSymbolRefExpr
::
create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
Ctx
)
)
;
break
;
case
MachineOperand
::
MO_RegisterMask
:
continue
;
case
MachineOperand
::
MO_BlockAddress
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetJTISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetCPISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
}
OutMI
.
addOperand
(
MCOp
)
;
}
}
</s>


<s>
CountValue
*
HexagonHardwareLoops
::
getTripCount
(
MachineLoop
*
L
)
const
{
const
MachineInstr
*
IV_Inst
=
getCanonicalInductionVariable
(
L
)
;
if
(
IV_Inst
==
0
)
return
0
;
const
MachineOperand
*
IV_Opnd
;
const
MachineOperand
*
InitialValue
;
if
(
!
L
->
contains
(
IV_Inst
->
getOperand
(
2
)
.
getMBB
(
)
)
)
{
InitialValue
=
&
IV_Inst
->
getOperand
(
1
)
;
IV_Opnd
=
&
IV_Inst
->
getOperand
(
3
)
;
}
else
{
InitialValue
=
&
IV_Inst
->
getOperand
(
3
)
;
IV_Opnd
=
&
IV_Inst
->
getOperand
(
1
)
;
}
for
(
MachineRegisterInfo
::
reg_iterator
RI
=
MRI
->
reg_begin
(
IV_Opnd
->
getReg
(
)
)
,
RE
=
MRI
->
reg_end
(
)
;
RI
!=
RE
;
++
RI
)
{
IV_Opnd
=
&
RI
.
getOperand
(
)
;
const
MachineInstr
*
MI
=
IV_Opnd
->
getParent
(
)
;
if
(
L
->
contains
(
MI
)
&&
isCompareEqualsImm
(
MI
)
)
{
const
MachineOperand
&
MO
=
MI
->
getOperand
(
2
)
;
assert
(
MO
.
isImm
(
)
&&
"IV Cmp Operand should be 0"
)
;
int64_t
ImmVal
=
MO
.
getImm
(
)
;
const
MachineInstr
*
IV_DefInstr
=
MRI
->
getVRegDef
(
IV_Opnd
->
getReg
(
)
)
;
assert
(
L
->
contains
(
IV_DefInstr
->
getParent
(
)
)
&&
"IV definition should occurs in loop"
)
;
int64_t
iv_value
=
IV_DefInstr
->
getOperand
(
2
)
.
getImm
(
)
;
if
(
ImmVal
==
0
)
{
if
(
iv_value
!=
1
&&
iv_value
!=
1
)
{
return
0
;
}
return
new
CountValue
(
InitialValue
->
getReg
(
)
,
iv_value
>
0
)
;
}
else
{
assert
(
InitialValue
->
isReg
(
)
&&
"Expecting register for init value"
)
;
const
MachineInstr
*
DefInstr
=
MRI
->
getVRegDef
(
InitialValue
->
getReg
(
)
)
;
if
(
DefInstr
&&
DefInstr
->
getOpcode
(
)
==
Hexagon
::
TFRI
)
{
int64_t
count
=
ImmVal
DefInstr
->
getOperand
(
1
)
.
getImm
(
)
;
if
(
(
count
%
iv_value
)
!=
0
)
{
return
0
;
}
return
new
CountValue
(
count
/
iv_value
)
;
}
}
}
}
return
0
;
}
</s>


<s> void MipsInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { switch ( MI -> getOpcode ( ) ) { default : break ; case Mips :: RDHWR : case Mips :: RDHWR64 : O << "\t.set\tpush\n" ; O << "\t.set\tmips32r2\n" ; } printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; switch ( MI -> getOpcode ( ) ) { default : break ; case Mips :: RDHWR : case Mips :: RDHWR64 : O << "\n\t.set\tpop" ; } } </s>

Print the specified MCInst to the specified raw_ostream .


<s> MachineInstr * X86InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const { if ( NoFusing ) return NULL ; unsigned Alignment = 0 ; if ( LoadMI -> hasOneMemOperand ( ) ) Alignment = LoadMI -> memoperands_begin ( ) -> getAlignment ( ) ; else if ( LoadMI -> getOpcode ( ) == X86 :: V_SET0 || LoadMI -> getOpcode ( ) == X86 :: V_SETALLONES ) Alignment = 16 ; if ( Ops . size ( ) == 2 && Ops [ 0 ] == 0 && Ops [ 1 ] == 1 ) { unsigned NewOpc = 0 ; switch ( MI -> getOpcode ( ) ) { default : return NULL ; case X86 :: TEST8rr : NewOpc = X86 :: CMP8ri ; break ; case X86 :: TEST16rr : NewOpc = X86 :: CMP16ri ; break ; case X86 :: TEST32rr : NewOpc = X86 :: CMP32ri ; break ; case X86 :: TEST64rr : NewOpc = X86 :: CMP64ri32 ; break ; } MI -> setDesc ( get ( NewOpc ) ) ; MI -> getOperand ( 1 ) . ChangeToImmediate ( 0 ) ; } else if ( Ops . size ( ) != 1 ) return NULL ; SmallVector < MachineOperand , X86AddrNumOperands > MOs ; if ( LoadMI -> getOpcode ( ) == X86 :: V_SET0 || LoadMI -> getOpcode ( ) == X86 :: V_SETALLONES ) { unsigned PICBase = 0 ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { if ( TM . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ) PICBase = X86 :: RIP ; else return false ; } MachineConstantPool & MCP = * MF . getConstantPool ( ) ; const VectorType * Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , 4 ) ; Constant * C = LoadMI -> getOpcode ( ) == X86 :: V_SET0 ? Constant :: getNullValue ( Ty ) : Constant :: getAllOnesValue ( Ty ) ; unsigned CPI = MCP . getConstantPoolIndex ( C , 16 ) ; MOs . push_back ( MachineOperand :: CreateReg ( PICBase , false ) ) ; MOs . push_back ( MachineOperand :: CreateImm ( 1 ) ) ; MOs . push_back ( MachineOperand :: CreateReg ( 0 , false ) ) ; MOs . push_back ( MachineOperand :: CreateCPI ( CPI , 0 ) ) ; MOs . push_back ( MachineOperand :: CreateReg ( 0 , false ) ) ; } else { unsigned NumOps = LoadMI -> getDesc ( ) . getNumOperands ( ) ; for ( unsigned i = NumOps - X86AddrNumOperands ; i != NumOps ; ++ i ) MOs . push_back ( LoadMI -> getOperand ( i ) ) ; } return foldMemoryOperandImpl ( MF , MI , Ops [ 0 ] , MOs , Alignment ) ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


"Don't know yet how to load an FSR16 from stack slot"

"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


Function that may creates more instructions for large value on adjusting stack pointer . In nds32 target , 'addi ' can be used for stack pointer adjustment in prologue/epilogue stage . However , sometimes there are too many local variables so that the adjustment value is not able to be fit in the 'addi ' instruction . One solution is to move value into a register and then use 'add ' instruction . In practice , we use TA_REGNUM ( $ r15 ) to accomplish this purpose .


<s> bool HexagonSubtarget :: useAA ( ) const { if ( OptLevel != CodeGenOpt :: None ) return true ; return false ; } </s>

Enable use of alias analysis during code generation ( during MI scheduling , DAGCombine , etc . ) .


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasV4TOps ( false ) , HasV5TOps ( false ) , HasV5TEOps ( false ) , HasV6Ops ( false ) , HasV6T2Ops ( false ) , HasV7Ops ( false ) , HasVFPv2 ( false ) , HasVFPv3 ( false ) , HasVFPv4 ( false ) , HasNEON ( false ) , UseNEONForSinglePrecisionFP ( false ) , UseMulOps ( UseFusedMulOps ) , SlowFPVMLx ( false ) , HasVMLxForwarding ( false ) , SlowFPBrcc ( false ) , InThumbMode ( false ) , HasThumb2 ( false ) , IsMClass ( false ) , NoARM ( false ) , PostRAScheduler ( false ) , IsR9Reserved ( ReserveR9 ) , UseMovt ( false ) , SupportsTailCall ( false ) , HasFP16 ( false ) , HasD16 ( false ) , HasHardwareDivide ( false ) , HasHardwareDivideInARM ( false ) , HasT2ExtractPack ( false ) , HasDataBarrier ( false ) , Pref32BitThumb ( false ) , AvoidCPSRPartialUpdate ( false ) , AvoidMOVsShifterOperand ( false ) , HasRAS ( false ) , HasMPExtension ( false ) , FPOnlySP ( false ) , AllowsUnalignedMem ( false ) , Thumb2DSP ( false ) , stackAlignment ( 4 ) , CPUString ( CPU ) , TargetTriple ( TT ) , TargetABI ( ARM_ABI_APCS ) { if ( CPUString . empty ( ) ) CPUString = "generic" ; std :: string ArchFS = ARM_MC :: ParseARMTriple ( TT , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ArchFS + "," + FS ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; if ( ! HasV6T2Ops && hasThumb2 ( ) ) HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( ( TT . find ( "eabi" ) != std :: string :: npos ) || ( isTargetIOS ( ) && isMClass ( ) ) ) TargetABI = ARM_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = 8 ; if ( ! isTargetIOS ( ) ) UseMovt = hasV6T2Ops ( ) ; else { IsR9Reserved = ReserveR9 | ! HasV6Ops ; UseMovt = DarwinUseMOVT && hasV6T2Ops ( ) ; SupportsTailCall = ! getTargetTriple ( ) . isOSVersionLT ( 5 , 0 ) ; } if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; if ( ! StrictAlign && hasV6Ops ( ) && isTargetDarwin ( ) ) AllowsUnalignedMem = true ; } </s>

This constructor initializes the data members to match that of the specified triple .

ARM ARM ARM ARM ARM ARM ARM 4 ARM "generic" ARM ARM "," "eabi" ARM 8 5 0


<s> unsigned PatmosInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . getOpcode ( ) == Patmos :: SWC || MI . getOpcode ( ) == Patmos :: SHC || MI . getOpcode ( ) == Patmos :: SBC ) { if ( MI . getOperand ( 2 ) . isFI ( ) && MI . getOperand ( 3 ) . isImm ( ) && MI . getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 2 ) . getIndex ( ) ; return MI . getOperand ( 4 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> static int mips_move_to_gpr_cost ( reg_class_t from ) { switch ( from ) { case M16_REGS : case GENERAL_REGS : return 2 ; case ACC_REGS : return 6 ; case FP_REGS : return 4 ; case COP0_REGS : case COP2_REGS : case COP3_REGS : return 5 ; default : return 0 ; } } </s>

Return the cost of moving a value from a register of class FROM to a GPR . Return 0 for classes that are unions of other classes handled by this function .


<s> static enum internal_test map_test_to_internal_test ( enum rtx_code test_code ) { enum internal_test test = ITEST_MAX ; switch ( test_code ) { default : break ; case EQ : test = ITEST_EQ ; break ; case NE : test = ITEST_NE ; break ; case GT : test = ITEST_GT ; break ; case GE : test = ITEST_GE ; break ; case LT : test = ITEST_LT ; break ; case LE : test = ITEST_LE ; break ; case GTU : test = ITEST_GTU ; break ; case GEU : test = ITEST_GEU ; break ; case LTU : test = ITEST_LTU ; break ; case LEU : test = ITEST_LEU ; break ; } return test ; } </s>

Make normal rtx_code into something we can index from an array


<s> bool X86TargetLowering :: isFMAFasterThanFMulAndFAdd ( const MachineFunction & MF , EVT VT ) const { if ( ! Subtarget . hasAnyFMA ( ) ) return false ; VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f16 : return Subtarget . hasFP16 ( ) ; case MVT :: f32 : case MVT :: f64 : return true ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> int arc_output_addsi ( rtx * operands , bool cond_p , bool output_p ) { char format [ 35 ] ; int match = operands_match_p ( operands [ 0 ] , operands [ 1 ] ) ; int match2 = operands_match_p ( operands [ 0 ] , operands [ 2 ] ) ; int intval = ( REG_P ( operands [ 2 ] ) ? 1 : CONST_INT_P ( operands [ 2 ] ) ? INTVAL ( operands [ 2 ] ) : 0xbadc057 ) ; int neg_intval = - intval ; int short_0 = satisfies_constraint_Rcq ( operands [ 0 ] ) ; int short_p = ( ! cond_p && short_0 && satisfies_constraint_Rcq ( operands [ 1 ] ) ) ; int ret = 0 ; if ( output_p ) \ output_asm_insn ( FORMAT , operands ) ; \ return ret ; \ } </s>

Emit code for an addsi3 instruction with OPERANDS . COND_P indicates if this will use conditional execution . Return the length of the instruction . If OUTPUT_P is false , do n't actually output the instruction , just return its length .


<s> static section * rs6000_xcoff_select_rtx_section ( machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED ) { if ( ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( x , mode ) ) return toc_section ; else return read_only_private_data_section ; } </s>

Select section for constant in constant pool . On RS/6000 , all constants are in the private read-only data area . However , if this is being placed in the TOC it must be output as a toc entry .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Patmos Single-Path Info"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static bool expand_vec_perm_movs ( struct expand_vec_perm_d * d ) { machine_mode vmode = d -> vmode ; unsigned i , nelt = d -> nelt ; rtx x ; if ( d -> one_operand_p ) return false ; if ( ! ( TARGET_SSE && ( vmode == V4SFmode || vmode == V4SImode ) ) && ! ( TARGET_MMX_WITH_SSE && ( vmode == V2SFmode || vmode == V2SImode ) ) && ! ( TARGET_SSE2 && ( vmode == V2DFmode || vmode == V2DImode ) ) ) return false ; if ( d -> perm [ 0 ] != nelt && d -> perm [ 0 ] != 0 ) return false ; for ( i = 1 ; i < nelt ; ++ i ) if ( d -> perm [ i ] != i + nelt - d -> perm [ 0 ] ) return false ; if ( d -> testing_p ) return true ; if ( d -> perm [ 0 ] == nelt ) x = gen_rtx_VEC_MERGE ( vmode , d -> op1 , d -> op0 , GEN_INT ( 1 ) ) ; else x = gen_rtx_VEC_MERGE ( vmode , d -> op0 , d -> op1 , GEN_INT ( 1 ) ) ; emit_insn ( gen_rtx_SET ( d -> target , x ) ) ; return true ; } </s>

A subroutine of ix86_expand_vec_perm_builtin_1 . Try to implement D using movss or movsd .


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override { const AArch64Subtarget & ST = C -> MF -> getSubtarget < AArch64Subtarget > ( ) ; ScheduleDAGMI * DAG = new ScheduleDAGMI ( C , std :: make_unique < AArch64PostRASchedStrategy > ( C ) , true ) ; if ( ST . hasFusion ( ) ) { DAG -> addMutation ( createAArch64MacroFusionDAGMutation ( ) ) ; return DAG ; } return DAG ; } </s>

Similar to createMachineScheduler but used when postRA machine scheduling is enabled .


<s> void Mips16InstrInfo :: adjustStackPtr ( unsigned SP , int64_t Amount , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; if ( isInt < 16 > ( Amount ) ) BuildMI ( MBB , I , DL , get ( Mips :: AddiuSpImmX16 ) ) . addImm ( Amount ) ; else adjustStackPtrBigUnrestricted ( SP , Amount , MBB , I ) ; } </s>


"Unmatched number of shufflevectors and indices"

Lower interleaved load ( s ) into target specific instructions/intrinsics .


<s>
void
PPCMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
verifyInstructionPredicates
(
MI
,
computeAvailableFeatures
(
STI
.
getFeatureBits
(
)
)
)
;
uint64_t
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
unsigned
Size
=
getInstSizeInBytes
(
MI
)
;
support
::
endianness
E
=
IsLittleEndian
support
::
little
:
support
::
big
;
switch
(
Size
)
{
case
0
:
break
;
case
4
:
support
::
endian
::
write
<
uint32_t
>
(
OS
,
Bits
,
E
)
;
break
;
case
8
:
support
::
endian
::
write
<
uint32_t
>
(
OS
,
Bits
>>
32
,
E
)
;
support
::
endian
::
write
<
uint32_t
>
(
OS
,
Bits
,
E
)
;
break
;
default
:
llvm_unreachable
(
"Invalid instruction size"
)
;
}
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .

PowerPC
PPC
support::endianness
support::little
support::big
0
4
support::endian
8
support::endian
32
support::endian
"Invalid instruction size"


<s> DecodeStatus Mips64Disassembler :: getInstruction ( MCInst & instr , uint64_t & Size , const MemoryObject & Region , uint64_t Address , raw_ostream & vStream , raw_ostream & cStream ) const { uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Region , Address , Size , Insn , isBigEndian ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeMips64Instruction32 ( instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } Result = decodeMipsInstruction32 ( instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s> MCDisassembler :: DecodeStatus JVMDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t , raw_ostream & OS , raw_ostream & CS ) const { return MCDisassembler :: Fail ; } </s>


".extern .shared .u%d __nvptx_stacks[32];\n"

".extern .shared .u32 __nvptx_uni[32];\n"

Write out the function declarations we 've collected .


<s> virtual const MipsRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static void nvptx_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( mode == TImode ) cum -> count += 2 ; else cum -> count ++ ; } </s>


<s> bool PPCTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , MachineMemOperand :: Flags , bool * Fast ) const { if ( DisablePPCUnaligned ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( VT . getSimpleVT ( ) . isVector ( ) ) { if ( Subtarget . hasVSX ( ) ) { if ( VT != MVT :: v2f64 && VT != MVT :: v2i64 && VT != MVT :: v4f32 && VT != MVT :: v4i32 ) return false ; } else { return false ; } } if ( VT == MVT :: ppcf128 ) return false ; if ( Fast ) * Fast = true ; return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> static rtx tilepro_function_arg ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS cum = * get_cumulative_args ( cum_v ) ; int byte_size = arg . promoted_size_in_bytes ( ) ; bool doubleword_aligned_p ; if ( cum >= TILEPRO_NUM_ARG_REGS ) return NULL_RTX ; doubleword_aligned_p = tilepro_function_arg_boundary ( arg . mode , arg . type ) > BITS_PER_WORD ; if ( doubleword_aligned_p ) cum += cum & 1 ; if ( ( cum + ( byte_size + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ) > TILEPRO_NUM_ARG_REGS ) return NULL_RTX ; return gen_rtx_REG ( arg . mode , cum ) ; } </s>


<s> unsigned X86TargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const SelectionDAG & DAG , unsigned Depth ) const { if ( Op . getOpcode ( ) == X86ISD :: SETCC_CARRY ) return Op . getScalarValueSizeInBits ( ) ; if ( Op . getOpcode ( ) == X86ISD :: VSEXT ) { EVT VT = Op . getValueType ( ) ; EVT SrcVT = Op . getOperand ( 0 ) . getValueType ( ) ; unsigned Tmp = DAG . ComputeNumSignBits ( Op . getOperand ( 0 ) , Depth + 1 ) ; Tmp += VT . getScalarSizeInBits ( ) - SrcVT . getScalarSizeInBits ( ) ; return Tmp ; } return 1 ; } </s>

Determine the number of bits in the operation that are sign bits .


<s> Register ARMTargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) const { return Subtarget -> useSjLjEH ( ) ? Register ( ) : ARM :: R1 ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .


<s> unsigned SHUXIRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return SHUXI :: SP ; } </s>


"Pointer Checker requires MPX support on this target."

Return mode to be used for bounds or VOIDmode if bounds are not supported .


<s> bool SparcInstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { assert ( Cond . size ( ) == 1 ) ; SPCC :: CondCodes CC = static_cast < SPCC :: CondCodes > ( Cond [ 0 ] . getImm ( ) ) ; Cond [ 0 ] . setImm ( GetOppositeBranchCondition ( CC ) ) ; return false ; } </s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> static void xtensa_conditional_register_usage ( void ) { unsigned i , c_mask ; c_mask = TARGET_WINDOWED_ABI ? ( 1 << 1 ) : ( 1 << 2 ) ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { if ( call_used_regs [ i ] > 1 ) call_used_regs [ i ] = ! ! ( call_used_regs [ i ] & c_mask ) ; } CLEAR_HARD_REG_BIT ( reg_class_contents [ ( int ) RL_REGS ] , HARD_FRAME_POINTER_REGNUM ) ; if ( ! TARGET_WINDOWED_ABI ) fixed_regs [ A0_REG ] = 0 ; } </s>

Update register usage after having seen the compiler flags .


<s> bool ARMSubtarget :: enablePostRAScheduler ( ) const { return ( ! isThumb ( ) || hasThumb2 ( ) ) ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s>
void
AArch64AsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
Ctx
,
TheTriple
,
IsResolved
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
unsigned
FulleSizeInBytes
=
getFixupKindContainereSizeInBytes
(
Fixup
.
getKind
(
)
)
;
if
(
FulleSizeInBytes
==
0
)
{
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
else
{
assert
(
(
Offset
+
FulleSizeInBytes
)
<=
Data
.
size
(
)
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FulleSizeInBytes
&&
"Invalid fixup size!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
FulleSizeInBytes
1
i
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool SystemZPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None && getSystemZTargetMachine ( ) . getSubtargetImpl ( ) -> hasLoadStoreOnCond ( ) ) addPass ( & IfConverterID ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .