<s> bool PPCInstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Cond , unsigned DstReg , unsigned TrueReg , unsigned FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( Cond . size ( ) != 2 ) return false ; if ( Cond [ 1 ] . getReg ( ) == PPC :: CTR || Cond [ 1 ] . getReg ( ) == PPC :: CTR8 ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( ! PPC :: GPRCRegClass . hasSubClassEq ( RC ) && ! PPC :: GPRC_NOR0RegClass . hasSubClassEq ( RC ) && ! PPC :: G8RCRegClass . hasSubClassEq ( RC ) && ! PPC :: G8RC_NOX0RegClass . hasSubClassEq ( RC ) ) return false ; CondCycles = 1 ; TrueCycles = 1 ; FalseCycles = 1 ; return true ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> bool ix86_bd_has_dispatch ( rtx_insn * insn , int action ) { if ( ( TARGET_CPU_P ( BDVER1 ) || TARGET_CPU_P ( BDVER2 ) || TARGET_CPU_P ( BDVER3 ) || TARGET_CPU_P ( BDVER4 ) ) && flag_dispatch_scheduler ) switch ( action ) { default : return false ; case IS_DISPATCH_ON : return true ; case IS_CMP : return is_cmp ( insn ) ; case DISPATCH_VIOLATION : return dispatch_violation ( ) ; case FITS_DISPATCH_WINDOW : return fits_dispatch_window ( insn ) ; } return false ; } </s>

Return TRUE if Dispatch Scheduling is supported .


<s> static bool expand_vselect_vconcat ( rtx target , rtx op0 , rtx op1 , const unsigned char * perm , unsigned nelt , bool testing_p ) { machine_mode v2mode ; rtx x ; bool ok ; if ( vselect_insn == NULL_RTX ) init_vselect_insn ( ) ; v2mode = GET_MODE_2XWIDER_MODE ( GET_MODE ( op0 ) ) ; x = XEXP ( SET_SRC ( PATTERN ( vselect_insn ) ) , 0 ) ; PUT_MODE ( x , v2mode ) ; XEXP ( x , 0 ) = op0 ; XEXP ( x , 1 ) = op1 ; ok = expand_vselect ( target , x , perm , nelt , testing_p ) ; XEXP ( x , 0 ) = const0_rtx ; XEXP ( x , 1 ) = const0_rtx ; return ok ; } </s>

Similar , but generate a vec_concat from op0 and op1 as well .


<s> void X86TargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( Subtarget . getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) || Subtarget . getTargetTriple ( ) . isWindowsItaniumEnvironment ( ) ) { M . getOrInsertGlobal ( "__security_cookie" , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; FunctionCallee SecurityCheckCookie = M . getOrInsertFunction ( "__security_check_cookie" , Type :: getVoidTy ( M . getContext ( ) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; if ( Function * F = dyn_cast < Function > ( SecurityCheckCookie . getCallee ( ) ) ) { F -> setCallingConv ( CallingConv :: X86_FastCall ) ; F -> addAttribute ( 1 , Attribute :: AttrKind :: InReg ) ; } return ; } if ( hasStackGuardSlotTLS ( Subtarget . getTargetTriple ( ) ) ) return ; TargetLowering :: insertSSPDeclarations ( M ) ; } </s>

Inserts necessary declarations for SSP ( stack protection ) purpose .


<s>
bool
MipsDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
char
ConstraintCode
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
assert
(
ConstraintCode
==
'm'
&&
"unexpected asm memory constraint"
)
;
OutOps
.
push_back
(
Op
)
;
return
false
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .

Mips
Mips
"unexpected asm memory constraint"


"getMemOperandWithOffset only supports base "

Get the base operand and byte offset of an instruction that reads/writes memory .


<s> bool AMDGPUPeepholeOpt :: doFinalization ( Module & M ) { return false ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> unsigned ARMBaseRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; const TargetFrameLowering * TFI = STI . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) return getFramePointerReg ( STI ) ; return ARM :: SP ; } </s>


<s> bool hasBranchDivergence ( ) { return false ; } </s>

Return true if branch divergence exists .


<s> void visium_split_cbranch ( enum rtx_code code , rtx op0 , rtx op1 , rtx label ) { enum machine_mode cc_mode = visium_select_cc_mode ( code , op0 , op1 ) ; rtx flags = gen_rtx_REG ( cc_mode , FLAGS_REGNUM ) ; rtx x = gen_rtx_COMPARE ( cc_mode , op0 , op1 ) ; x = gen_rtx_SET ( flags , x ) ; emit_insn ( x ) ; x = gen_rtx_fmt_ee ( code , VOIDmode , flags , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label ) , pc_rtx ) ; x = gen_rtx_SET ( pc_rtx , x ) ; emit_jump_insn ( x ) ; visium_flags_exposed = true ; } </s>

Split a compare-and-branch with CODE , operands OP0 and OP1 , and LABEL .


<s> OperandMatchResultTy MCS51AsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { StartLoc = Parser . getTok ( ) . getLoc ( ) ; RegNo = parseRegister ( true ) ; EndLoc = Parser . getTok ( ) . getLoc ( ) ; if ( RegNo == MCS51 :: NoRegister ) return MatchOperand_NoMatch ; return MatchOperand_Success ; } </s>

tryParseRegister - parse one register if possible


"Invalid number of NOP bytes requested!"

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> static bool sparc_secondary_memory_needed ( machine_mode mode , reg_class_t class1 , reg_class_t class2 ) { return ( ( FP_REG_CLASS_P ( class1 ) != FP_REG_CLASS_P ( class2 ) ) && ( ! TARGET_VIS3 || GET_MODE_SIZE ( mode ) > 8 || GET_MODE_SIZE ( mode ) < 4 ) ) ; } </s>

Implement TARGET_SECONDARY_MEMORY_NEEDED . On SPARC when not VIS3 it is not possible to directly move data between GENERAL_REGS and FP_REGS .


<s> static void vms_asm_named_section ( const char * name , unsigned int flags , tree decl ATTRIBUTE_UNUSED ) { fputc ( '\n' , asm_out_file ) ; fprintf ( asm_out_file , ".section\t%s" , name ) ; if ( flags & SECTION_DEBUG ) fprintf ( asm_out_file , ",NOWRT" ) ; fputc ( '\n' , asm_out_file ) ; } </s>

Switch to an arbitrary section NAME with attributes as specified by FLAGS . ALIGN specifies any known alignment requirements for the section ; 0 if the default should be used .


<s> unsigned MipsSEInstrInfo :: loadImmediate ( int64_t Imm , MachineBasicBlock & MBB , MachineBasicBlock :: iterator II , DebugLoc DL , unsigned * NewImm ) const { MipsAnalyzeImmediate AnalyzeImm ; const MipsSubtarget & STI = TM . getSubtarget < MipsSubtarget > ( ) ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; unsigned Size = STI . isABI_N64 ( ) ? 64 : 32 ; unsigned LUi = STI . isABI_N64 ( ) ? Mips :: LUi64 : Mips :: LUi ; unsigned ZEROReg = STI . isABI_N64 ( ) ? Mips :: ZERO_64 : Mips :: ZERO ; const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; bool LastInstrIsADDiu = NewImm ; const MipsAnalyzeImmediate :: InstSeq & Seq = AnalyzeImm . Analyze ( Imm , Size , LastInstrIsADDiu ) ; MipsAnalyzeImmediate :: InstSeq :: const_iterator Inst = Seq . begin ( ) ; assert ( Seq . size ( ) && ( ! LastInstrIsADDiu || ( Seq . size ( ) > 1 ) ) ) ; unsigned Reg = RegInfo . createVirtualRegister ( RC ) ; if ( Inst -> Opc == LUi ) BuildMI ( MBB , II , DL , get ( LUi ) , Reg ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; else BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , Reg ) . addReg ( ZEROReg ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; for ( ++ Inst ; Inst != Seq . end ( ) - LastInstrIsADDiu ; ++ Inst ) BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; if ( LastInstrIsADDiu ) * NewImm = Inst -> ImmOpnd ; return Reg ; } </s>

Emit a series of instructions to load an immediate .


<s> int AArch64TargetLowering :: getScalingFactorCost ( const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( isLegalAddressingMode ( AM , Ty , AS ) ) return AM . Scale != 0 && AM . Scale != 1 ; return - 1 ; } </s>

Return the cost of the scaling factor used in the addressing mode represented by AM for this target , for a load/store of the specified type .


<s>
bool
NVPTXAsmPrinter
::
doInitialization
(
Module
&
M
)
{
SmallString
<
128
>
Str1
;
raw_svector_ostream
OS1
(
Str1
)
;
MMI
=
getAnalysisIfAvailable
<
MachineModuleInfo
>
(
)
;
MMI
->
AnalyzeModule
(
M
)
;
const_cast
<
TargetLoweringObjectFile
&
>
(
getObjFileLowering
(
)
)
.
Initialize
(
OutContext
,
TM
)
;
Mang
=
new
Mangler
(
OutContext
,
&
TM
)
;
emitHeader
(
M
,
OS1
)
;
OutStreamer
.
EmitRawText
(
OS1
.
str
(
)
)
;
if
(
!
M
.
getModuleInlineAsm
(
)
.
empty
(
)
)
{
OutStreamer
.
AddComment
(
"Start of file scope inline assembly"
)
;
OutStreamer
.
AddBlankLine
(
)
;
OutStreamer
.
EmitRawText
(
StringRef
(
M
.
getModuleInlineAsm
(
)
)
)
;
OutStreamer
.
AddBlankLine
(
)
;
OutStreamer
.
AddComment
(
"End of file scope inline assembly"
)
;
OutStreamer
.
AddBlankLine
(
)
;
}
if
(
nvptxSubtarget
.
getDrvInterface
(
)
==
NVPTX
::
CUDA
)
recordAndEmitFilenames
(
M
)
;
GlobalsEmitted
=
false
;
return
false
;
}
</s>

Set up the AsmPrinter when we are working on a new module .

NVPTX
NVPTX
128
"Start of file scope inline assembly"
"End of file scope inline assembly"
NVPTX::CUDA


<s>
bool
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
override
{
MCInst
Inst
;
Inst
.
setLoc
(
IDLoc
)
;
FeatureBitset
MissingFeatures
;
unsigned
MatchResult
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MissingFeatures
,
MatchingInlineAsm
)
;
switch
(
MatchResult
)
{
case
Match_Success
:
{
ensureLocals
(
Out
)
;
auto
Align
=
WebAssembly
::
GetDefaultP2AlignAny
(
Inst
.
getOpcode
(
)
)
;
if
(
Align
!=
1U
)
{
auto
&
Op0
=
Inst
.
getOperand
(
0
)
;
if
(
Op0
.
getImm
(
)
==
1
)
Op0
.
setImm
(
Align
)
;
}
if
(
getSTI
(
)
.
getTargetTriple
(
)
.
isArch64Bit
(
)
)
{
auto
Opc64
=
WebAssembly
::
getWasm64Opcode
(
static_cast
<
uint16_t
>
(
Inst
.
getOpcode
(
)
)
)
;
if
(
Opc64
>=
0
)
{
Inst
.
setOpcode
(
Opc64
)
;
}
}
Out
.
emitInstruction
(
Inst
,
getSTI
(
)
)
;
if
(
CurrentState
==
EndFunction
)
{
onEndOfFunction
(
)
;
}
else
{
CurrentState
=
Instructions
;
}
return
false
;
}
case
Match_MissingFeature
:
{
assert
(
MissingFeatures
.
count
(
)
>
0
&&
"Expected missing features"
)
;
SmallString
<
128
>
Message
;
raw_svector_ostream
OS
(
Message
)
;
OS
<<
"instruction requires:"
;
for
(
unsigned
i
=
0
,
e
=
MissingFeatures
.
size
(
)
;
i
!=
e
;
++
i
)
if
(
MissingFeatures
.
test
(
i
)
)
OS
<<
' '
<<
getSubtargetFeatureName
(
i
)
;
return
Parser
.
Error
(
IDLoc
,
Message
)
;
}
case
Match_MnemonicFail
:
return
Parser
.
Error
(
IDLoc
,
"invalid instruction"
)
;
case
Match_NearMisses
:
return
Parser
.
Error
(
IDLoc
,
"ambiguous instruction"
)
;
case
Match_InvalidTiedOperand
:
case
Match_InvalidOperand
:
{
SMLoc
ErrorLoc
=
IDLoc
;
if
(
ErrorInfo
!=
~
0ULL
)
{
if
(
ErrorInfo
>=
Operands
.
size
(
)
)
return
Parser
.
Error
(
IDLoc
,
"too few operands for instruction"
)
;
ErrorLoc
=
Operands
[
ErrorInfo
]
->
getStartLoc
(
)
;
if
(
ErrorLoc
==
SMLoc
(
)
)
ErrorLoc
=
IDLoc
;
}
return
Parser
.
Error
(
ErrorLoc
,
"invalid operand for instruction"
)
;
}
}
llvm_unreachable
(
"Implement any new match types added!"
)
;
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> Builder ( BasicBlock * B ) : IRBuilder < > ( B ) { } </s>

Hold a reference to the IRBuilder used to generate output IR code .


<s> PreservedAnalyses AMDGPUUseNativeCallsPass :: run ( Function & F , FunctionAnalysisManager & AM ) { if ( UseNative . empty ( ) ) return PreservedAnalyses :: all ( ) ; AMDGPULibCalls Simplifier ; Simplifier . initNativeFuncs ( ) ; bool Changed = false ; for ( auto & BB : F ) { for ( BasicBlock :: iterator I = BB . begin ( ) , E = BB . end ( ) ; I != E ; ) { CallInst * CI = dyn_cast < CallInst > ( I ) ; ++ I ; if ( ! CI ) continue ; Function * Callee = CI -> getCalledFunction ( ) ; if ( Callee == 0 ) continue ; if ( Simplifier . useNative ( CI ) ) Changed = true ; } } return Changed ? PreservedAnalyses :: none ( ) : PreservedAnalyses :: all ( ) ; } </s>

Run the analysis pass over a function and produce a dominator tree .


<s>
unsigned
AArch64InstrInfo
::
getInstSizeInBytes
(
const
MachineInstr
&
MI
)
const
{
const
MCInstrDesc
&
MCID
=
MI
.
getDesc
(
)
;
const
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
MCAsmInfo
&
MAI
=
*
MF
.
getTarget
(
)
.
getMCAsmInfo
(
)
;
if
(
MCID
.
getSize
(
)
)
return
MCID
.
getSize
(
)
;
if
(
MI
.
getOpcode
(
)
==
AArch64
::
INLINEASM
)
return
getInlineAsmLength
(
MI
.
getOperand
(
0
)
.
getSymbolName
(
)
,
MAI
)
;
if
(
MI
.
isLabel
(
)
)
return
0
;
switch
(
MI
.
getOpcode
(
)
)
{
case
TargetOpcode
::
BUNDLE
:
return
getInstBundleLength
(
MI
)
;
case
TargetOpcode
::
IMPLICIT_DEF
:
case
TargetOpcode
::
KILL
:
case
TargetOpcode
::
PROLOG_LABEL
:
case
TargetOpcode
::
EH_LABEL
:
case
TargetOpcode
::
DBG_VALUE
:
return
0
;
case
AArch64
::
TLSDESCCALL
:
return
0
;
default
:
llvm_unreachable
(
"Unknown instruction class"
)
;
}
}
</s>


<s> bool X86PreTileConfig :: runOnMachineFunction ( MachineFunction & mf ) { MF = & mf ; MRI = & mf . getRegInfo ( ) ; ST = & mf . getSubtarget < X86Subtarget > ( ) ; TRI = ST -> getRegisterInfo ( ) ; TII = mf . getSubtarget ( ) . getInstrInfo ( ) ; DomTree = & getAnalysis < MachineDominatorTree > ( ) ; MachineInstr * MI = getTileConfigPoint ( ) ; if ( ! MI ) return false ; unsigned Size = ST -> getTileConfigSize ( ) ; Align Alignment = ST -> getTileConfigAlignment ( ) ; int SS = mf . getFrameInfo ( ) . CreateStackObject ( Size , Alignment , false ) ; Register CFG = buildConfigMI ( MI , SS , TII , MRI , ST ) ; addTileCFGUse ( mf , CFG ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> rtx gen_push ( rtx arg ) { struct machine_function * m = cfun -> machine ; if ( m -> fs . cfa_reg == stack_pointer_rtx ) m -> fs . cfa_offset += UNITS_PER_WORD ; m -> fs . sp_offset += UNITS_PER_WORD ; if ( REG_P ( arg ) && GET_MODE ( arg ) != word_mode ) arg = gen_rtx_REG ( word_mode , REGNO ( arg ) ) ; return gen_rtx_SET ( gen_rtx_MEM ( word_mode , gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ) , arg ) ; } </s>

Code to generate prologue and epilogue sequences


<s> MVT PIC16TargetLowering :: getSetCCResultType ( MVT ValType ) const { return MVT :: i8 ; } </s>

Return the value type to use for ISD : :SETCC .


<s> bool AMDGPUPostLegalizerCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: FailedISel ) ) return false ; auto * TPC = & getAnalysis < TargetPassConfig > ( ) ; const Function & F = MF . getFunction ( ) ; bool EnableOpt = MF . getTarget ( ) . getOptLevel ( ) != CodeGenOpt :: None && ! skipFunction ( F ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const AMDGPULegalizerInfo * LI = static_cast < const AMDGPULegalizerInfo * > ( ST . getLegalizerInfo ( ) ) ; GISelKnownBits * KB = & getAnalysis < GISelKnownBitsAnalysis > ( ) . get ( MF ) ; MachineDominatorTree * MDT = IsOptNone ? nullptr : & getAnalysis < MachineDominatorTree > ( ) ; AMDGPUPostLegalizerCombinerInfo PCInfo ( EnableOpt , F . hasOptSize ( ) , F . hasMinSize ( ) , LI , KB , MDT ) ; Combiner C ( PCInfo , TPC ) ; return C . combineMachineInstrs ( MF , nullptr ) ; } </s>


<s> static int eligible_for_restore_insn ( rtx trial , bool return_p ) { rtx pat = PATTERN ( trial ) ; rtx src = SET_SRC ( pat ) ; bool src_is_freg = false ; rtx src_reg ; src_reg = src ; if ( GET_CODE ( src_reg ) == SUBREG ) src_reg = SUBREG_REG ( src_reg ) ; if ( GET_CODE ( src_reg ) == REG && SPARC_FP_REG_P ( REGNO ( src_reg ) ) ) src_is_freg = true ; if ( GET_MODE_CLASS ( GET_MODE ( src ) ) != MODE_FLOAT && arith_operand ( src , GET_MODE ( src ) ) && ! src_is_freg ) { if ( TARGET_ARCH64 ) return GET_MODE_SIZE ( GET_MODE ( src ) ) <= GET_MODE_SIZE ( DImode ) ; else return GET_MODE_SIZE ( GET_MODE ( src ) ) <= GET_MODE_SIZE ( SImode ) ; } else if ( GET_MODE_CLASS ( GET_MODE ( src ) ) != MODE_FLOAT && arith_double_operand ( src , GET_MODE ( src ) ) && ! src_is_freg ) return GET_MODE_SIZE ( GET_MODE ( src ) ) <= GET_MODE_SIZE ( DImode ) ; else if ( ! TARGET_FPU && register_operand ( src , SFmode ) ) return 1 ; else if ( ! TARGET_FPU && TARGET_ARCH64 && register_operand ( src , DFmode ) ) return 1 ; else if ( return_p && TARGET_V9 && ! epilogue_renumber ( & pat , 1 ) ) return 1 ; else if ( GET_CODE ( src ) == PLUS && register_operand ( XEXP ( src , 0 ) , SImode ) && arith_operand ( XEXP ( src , 1 ) , SImode ) ) return 1 ; else if ( GET_CODE ( src ) == PLUS && register_operand ( XEXP ( src , 0 ) , DImode ) && arith_double_operand ( XEXP ( src , 1 ) , DImode ) ) return 1 ; else if ( GET_CODE ( src ) == LO_SUM && ! TARGET_CM_MEDMID && ( ( register_operand ( XEXP ( src , 0 ) , SImode ) && immediate_operand ( XEXP ( src , 1 ) , SImode ) ) || ( TARGET_ARCH64 && register_operand ( XEXP ( src , 0 ) , DImode ) && immediate_operand ( XEXP ( src , 1 ) , DImode ) ) ) ) return 1 ; else if ( GET_CODE ( src ) == ASHIFT && ( register_operand ( XEXP ( src , 0 ) , SImode ) || register_operand ( XEXP ( src , 0 ) , DImode ) ) && XEXP ( src , 1 ) == const1_rtx ) return 1 ; return 0 ; } </s>

Return nonzero if TRIAL , an insn , can be combined with a 'restore ' instruction . RETURN_P is true if the v9 variant 'return ' is to be considered in the test too . TRIAL must be a SET whose destination is a REG appropriate for the 'restore ' instruction or , if RETURN_P is true , for the 'return ' instruction .


<s> unsigned int TL45AsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & Op , unsigned Kind ) { return MCTargetAsmParser :: validateTargetOperandClass ( Op , Kind ) ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> unsigned getHash ( ) const { return Hash ; } </s>


<s>
MachineBasicBlock
::
iterator
SIFrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
int64_t
Amount
=
I
->
getOperand
(
0
)
.
getImm
(
)
;
if
(
Amount
==
0
)
return
MBB
.
erase
(
I
)
;
const
GCNSubtarget
&
ST
=
MF
.
getSubtarget
<
GCNSubtarget
>
(
)
;
const
SIInstrInfo
*
TII
=
ST
.
getInstrInfo
(
)
;
const
DebugLoc
&
DL
=
I
->
getDebugLoc
(
)
;
unsigned
Opc
=
I
->
getOpcode
(
)
;
bool
IsDestroy
=
Opc
==
TII
->
getCallFrameDestroyOpcode
(
)
;
uint64_t
CalleePopAmount
=
IsDestroy
I
->
getOperand
(
1
)
.
getImm
(
)
:
0
;
if
(
!
hasReservedCallFrame
(
MF
)
)
{
Amount
=
alignTo
(
Amount
,
getStackAlign
(
)
)
;
assert
(
isUInt
<
32
>
(
Amount
)
&&
"exceeded stack address space size"
)
;
const
SIMachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
SIMachineFunctionInfo
>
(
)
;
Register
SPReg
=
MFI
->
getStackPtrOffsetReg
(
)
;
Amount
*=
getScratchScaleFactor
(
ST
)
;
if
(
IsDestroy
)
Amount
=
Amount
;
auto
Add
=
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
AMDGPU
::
S_ADD_I32
)
,
SPReg
)
.
addReg
(
SPReg
)
.
addImm
(
Amount
)
;
Add
->
getOperand
(
3
)
.
setIsDead
(
)
;
}
else
if
(
CalleePopAmount
!=
0
)
{
llvm_unreachable
(
"is this used?"
)
;
}
return
MBB
.
erase
(
I
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s>
MachineOperand
&
AArch64InstrInfo
::
getMemOpBaseRegImmOfsOffsetOperand
(
MachineInstr
&
LdSt
)
const
{
assert
(
LdSt
.
mayLoadOrStore
(
)
&&
"Expected a memory operation."
)
;
MachineOperand
&
OfsOp
=
LdSt
.
getOperand
(
LdSt
.
getNumExplicitOperands
(
)
1
)
;
assert
(
OfsOp
.
isImm
(
)
&&
"Offset operand wasn't immediate."
)
;
return
OfsOp
;
}
</s>

Return the immediate offset of the base register in a load/store LdSt .


<s> static int classes_intersect ( int class1 , int class2 ) { return class_contents [ class1 ] [ 0 ] & class_contents [ class2 ] [ 0 ] ; } </s>

Returns TRUE If there are any registers that exist in both register classes .


<s>
const
MCExpr
*
ARMElfTargetObjectFile
::
getTTypeGlobalReference
(
const
GlobalValue
*
GV
,
Mangler
*
Mang
,
MachineModuleInfo
*
MMI
,
unsigned
Encoding
,
MCStreamer
&
Streamer
)
const
{
assert
(
Encoding
==
DW_EH_PE_absptr
&&
"Can handle absptr encoding only"
)
;
Triple
T
(
MMI
->
getModule
(
)
->
getTargetTriple
(
)
)
;
if
(
T
.
isOSNaCl
(
)
)
return
TargetLoweringObjectFileELF
::
getTTypeGlobalReference
(
GV
,
Mang
,
MMI
,
Encoding
,
Streamer
)
;
return
MCSymbolRefExpr
::
Create
(
Mang
->
getSymbol
(
GV
)
,
MCSymbolRefExpr
::
VK_ARM_TARGET2
,
getContext
(
)
)
;
}
</s>

The mach-o version of this method defaults to returning a stub reference .

ARM
ARM
"Can handle absptr encoding only"
ARM


<s> static rtx mn10300_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( mode , FIRST_DATA_REGNUM ) ; } </s>


<s> static void ix86_expand_ashl_const ( rtx operand , int count , machine_mode mode ) { rtx ( * insn ) ( rtx , rtx , rtx ) ; if ( count == 1 || ( count * ix86_cost -> add <= ix86_cost -> shift_const && ! optimize_insn_for_size_p ( ) ) ) { insn = mode == DImode ? gen_addsi3 : gen_adddi3 ; while ( count -- > 0 ) emit_insn ( insn ( operand , operand , operand ) ) ; } else { insn = mode == DImode ? gen_ashlsi3 : gen_ashldi3 ; emit_insn ( insn ( operand , operand , GEN_INT ( count ) ) ) ; } } </s>

Helper function of ix86_split_ashl used to generate an SImode/DImode left shift by a constant , either using a single shift or a sequence of add instructions .


"Did not fully process a global variable"

EmitGlobals - Emit all of the global variables to memory , storing their addresses into GlobalAddress .


<s> static rtx function_arg_vector_value ( int size , int slotno , bool named , int regno ) { const int mult = ( named ? 2 : 1 ) ; unsigned int nwords ; if ( slotno == ( named ? SPARC_FP_ARG_MAX : SPARC_INT_ARG_MAX ) - 1 ) nwords = 1 ; else nwords = CEIL_NWORDS ( size ) ; rtx regs = gen_rtx_PARALLEL ( BLKmode , rtvec_alloc ( nwords ) ) ; if ( size < UNITS_PER_WORD ) XVECEXP ( regs , 0 , 0 ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , regno ) , const0_rtx ) ; else for ( unsigned int i = 0 ; i < nwords ; i ++ ) XVECEXP ( regs , 0 , i ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( word_mode , regno + i * mult ) , GEN_INT ( i * UNITS_PER_WORD ) ) ; return regs ; } </s>

Used by function_arg and sparc_function_value_1 to implement the conventions for passing and returning BLKmode vectors . Return an expression valid as a return value for the FUNCTION_ARG and TARGET_FUNCTION_VALUE . SIZE is the size in bytes of the vector . REGNO is the FP hard register the vector will be passed in .


<s>
void
R600AsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
const
R600Subtarget
&
STI
=
MF
->
getSubtarget
<
R600Subtarget
>
(
)
;
R600MCInstLower
MCInstLowering
(
OutContext
,
STI
,
*
this
)
;
StringRef
Err
;
if
(
!
STI
.
getInstrInfo
(
)
->
verifyInstruction
(
*
MI
,
Err
)
)
{
LLVMContext
&
C
=
MI
->
getParent
(
)
->
getParent
(
)
->
getFunction
(
)
.
getContext
(
)
;
C
.
emitError
(
"Illegal instruction detected: "
+
Err
)
;
MI
->
print
(
errs
(
)
)
;
}
if
(
MI
->
isBundle
(
)
)
{
const
MachineBasicBlock
*
MBB
=
MI
->
getParent
(
)
;
MachineBasicBlock
::
const_instr_iterator
I
=
++
MI
->
getIterator
(
)
;
while
(
I
!=
MBB
->
instr_end
(
)
&&
I
->
isInsideBundle
(
)
)
{
EmitInstruction
(
&
*
I
)
;
++
I
;
}
}
else
{
MCInst
TmpInst
;
MCInstLowering
.
lower
(
MI
,
TmpInst
)
;
EmitToStreamer
(
*
OutStreamer
,
TmpInst
)
;
}
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static bool tryAddingSymbolicOperand ( uint64_t Address , int32_t Value , bool isBranch , uint64_t InstSize , MCInst & MI , const MCDisassembler * Decoder ) { return Decoder -> tryAddingSymbolicOperand ( MI , ( uint32_t ) Value , Address , isBranch , 0 , 0 , InstSize ) ; } </s>

Try to add a symbolic operand instead of Value to the MCInst .


<s>
SDValue
SPUTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_SPU
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
SPUISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
else
return
DAG
.
getNode
(
SPUISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool MipsSETargetLowering :: isEligibleForTailCallOptimization ( const CCState & CCInfo , unsigned NextStackOffset , const MipsFunctionInfo & FI ) const { if ( ! EnableMipsTailCalls ) return false ; if ( CCInfo . getInRegsParamsCount ( ) > 0 || FI . hasByvalArg ( ) ) return false ; return NextStackOffset <= FI . getIncomingArgSize ( ) ; } </s>

Returns true if the call can be lowered as a tail call .


<s>
const
char
*
AMDGPUPeepholeOpt
::
getPassName
(
)
const
{
return
"AMDGPU PeepHole Optimization Pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"This eliminateCallFramePseudoInstr does not support Thumb1!"


<s>
char
*
aarch64_output_simd_mov_immediate
(
rtx
const_vector
,
machine_mode
mode
,
unsigned
width
)
{
bool
is_valid
;
static
char
templ
[
40
]
;
const
char
*
mnemonic
;
const
char
*
shift_op
;
unsigned
int
lane_count
=
0
;
char
element_char
;
struct
simd_immediate_info
info
=
{
NULL_RTX
,
0
,
0
,
false
,
false
}
;
is_valid
=
aarch64_simd_valid_immediate
(
const_vector
,
mode
,
false
,
&
info
)
;
gcc_assert
(
is_valid
)
;
element_char
=
sizetochar
(
info
.
element_width
)
;
lane_count
=
width
/
info
.
element_width
;
mode
=
GET_MODE_INNER
(
mode
)
;
if
(
GET_MODE_CLASS
(
mode
)
==
MODE_FLOAT
)
{
gcc_assert
(
info
.
shift
==
0
&&
!
info
.
mvn
)
;
if
(
aarch64_float_const_zero_rtx_p
(
info
.
value
)
)
info
.
value
=
GEN_INT
(
0
)
;
else
{
char
float_buf
[
buf_size
]
=
{
'\0'
}
;
real_to_decimal_for_mode
(
float_buf
,
CONST_DOUBLE_REAL_VALUE
(
info
.
value
)
,
buf_size
,
buf_size
,
1
,
mode
)
;
if
(
lane_count
==
1
)
snprintf
(
templ
,
sizeof
(
templ
)
,
"fmov\t%%d0, %s"
,
float_buf
)
;
else
snprintf
(
templ
,
sizeof
(
templ
)
,
"fmov\t%%0.%d%c, %s"
,
lane_count
,
element_char
,
float_buf
)
;
return
templ
;
}
}
mnemonic
=
info
.
mvn
"mvni"
:
"movi"
;
shift_op
=
info
.
msl
"msl"
:
"lsl"
;
gcc_assert
(
CONST_INT_P
(
info
.
value
)
)
;
if
(
lane_count
==
1
)
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%d0, "
HOST_WIDE_INT_PRINT_HEX
,
mnemonic
,
UINTVAL
(
info
.
value
)
)
;
else
if
(
info
.
shift
)
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%0.%d%c, "
HOST_WIDE_INT_PRINT_HEX
", %s %d"
,
mnemonic
,
lane_count
,
element_char
,
UINTVAL
(
info
.
value
)
,
shift_op
,
info
.
shift
)
;
else
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%0.%d%c, "
HOST_WIDE_INT_PRINT_HEX
,
mnemonic
,
lane_count
,
element_char
,
UINTVAL
(
info
.
value
)
)
;
return
templ
;
}
</s>

Returns the string with the instruction for AdvSIMD MOVI , MVNI , ORR or BIC immediate with a CONST_VECTOR of MODE and WIDTH . WHICH selects whether to output MOVI/MVNI , ORR or BIC immediate .


"unexpected return calling convention register assignment"

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static void workaround_barsyncs ( void ) { bool seen_barsync = false ; for ( rtx_insn * insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( INSN_P ( insn ) && recog_memoized ( insn ) == CODE_FOR_nvptx_barsync ) { if ( seen_barsync ) { emit_insn_before ( gen_nvptx_membar_cta ( ) , insn ) ; emit_insn_before ( gen_nvptx_membar_cta ( ) , insn ) ; } seen_barsync = true ; continue ; } if ( ! seen_barsync ) continue ; if ( NOTE_P ( insn ) || DEBUG_INSN_P ( insn ) ) continue ; else if ( INSN_P ( insn ) ) switch ( recog_memoized ( insn ) ) { case CODE_FOR_nvptx_fork : case CODE_FOR_nvptx_forked : case CODE_FOR_nvptx_joining : case CODE_FOR_nvptx_join : continue ; default : break ; } seen_barsync = false ; } } </s>

Insert two membar.cta insns inbetween two subsequent bar.sync insns . This works around a hang observed at driver version 390.48 for sm_50 .


<s> const SmallVectorImpl < MachineBasicBlock * > & getOrder ( ) const { return Order ; } </s>


<s> static rtx arc_builtin_setjmp_frame_value ( void ) { return gen_raw_REG ( Pmode , HARD_FRAME_POINTER_REGNUM ) ; } </s>

Return the frame pointer value to be backed up in the setjmp buffer .


<s> static bool aarch64_rtx_arith_op_extract_p ( rtx x , machine_mode mode ) { if ( GET_CODE ( x ) == SIGN_EXTRACT || GET_CODE ( x ) == ZERO_EXTRACT ) { rtx op0 = XEXP ( x , 0 ) ; rtx op1 = XEXP ( x , 1 ) ; rtx op2 = XEXP ( x , 2 ) ; if ( GET_CODE ( op0 ) == MULT && CONST_INT_P ( op1 ) && op2 == const0_rtx && CONST_INT_P ( XEXP ( op0 , 1 ) ) && aarch64_is_extend_from_extract ( mode , XEXP ( op0 , 1 ) , op1 ) ) { return true ; } } return false ; } </s>

Return true if X is a zero or sign extract usable in an ADD or SUB ( extended register ) instruction .


<s> static void mips_emit_compare ( enum rtx_code * code , rtx * op0 , rtx * op1 , bool need_eq_ne_p ) { rtx cmp_op0 = * op0 ; rtx cmp_op1 = * op1 ; if ( GET_MODE_CLASS ( GET_MODE ( * op0 ) ) == MODE_INT ) { if ( ! need_eq_ne_p && * op1 == const0_rtx ) ; else if ( * code == EQ || * code == NE ) { if ( need_eq_ne_p ) { * op0 = mips_zero_if_equal ( cmp_op0 , cmp_op1 ) ; * op1 = const0_rtx ; } else * op1 = force_reg ( GET_MODE ( cmp_op0 ) , cmp_op1 ) ; } else { bool invert = false ; * op0 = gen_reg_rtx ( GET_MODE ( cmp_op0 ) ) ; mips_emit_int_order_test ( * code , & invert , * op0 , cmp_op0 , cmp_op1 ) ; * code = ( invert ? EQ : NE ) ; * op1 = const0_rtx ; } } else if ( ALL_FIXED_POINT_MODE_P ( GET_MODE ( cmp_op0 ) ) ) { * op0 = gen_rtx_REG ( CCDSPmode , CCDSP_CC_REGNUM ) ; mips_emit_binary ( * code , * op0 , cmp_op0 , cmp_op1 ) ; * code = NE ; * op1 = const0_rtx ; } else { enum rtx_code cmp_code ; cmp_code = * code ; if ( ISA_HAS_CCF ) { * code = NE ; * op0 = gen_reg_rtx ( CCFmode ) ; } else { * code = mips_reversed_fp_cond ( & cmp_code ) ? EQ : NE ; if ( ISA_HAS_8CC ) * op0 = mips_allocate_fcc ( CCmode ) ; else * op0 = gen_rtx_REG ( CCmode , FPSW_REGNUM ) ; } * op1 = const0_rtx ; mips_emit_binary ( cmp_code , * op0 , cmp_op0 , cmp_op1 ) ; } } </s>

Convert a comparison into something that can be used in a branch or conditional move . On entry , * OP0 and * OP1 are the values being compared and * CODE is the code used to compare them . Update * CODE , * OP0 and * OP1 so that they describe the final comparison . If NEED_EQ_NE_P , then only EQ or NE comparisons against zero are possible , otherwise any standard branch condition can be used . The standard branch conditions are : - EQ or NE between two registers . - any comparison between a register and zero .


<s> void cris_asm_output_label_ref ( FILE * file , char * buf ) { assemble_name ( file , buf ) ; } </s>

Worker function for ASM_OUTPUT_LABEL_REF .


<s> static void nios2_init_fpu_builtins ( int start_code ) { tree fndecl ; char builtin_name [ 64 ] = "__builtin_custom_" ; unsigned int i , n = strlen ( "__builtin_custom_" ) ; for ( i = 0 ; i < ARRAY_SIZE ( nios2_fpu_insn ) ; i ++ ) { snprintf ( builtin_name + n , sizeof ( builtin_name ) - n , "%s" , N2FPU_NAME ( i ) ) ; fndecl = add_builtin_function ( builtin_name , nios2_ftype ( N2FPU_FTCODE ( i ) ) , start_code + i , BUILT_IN_MD , NULL , NULL_TREE ) ; nios2_register_builtin_fndecl ( start_code + i , fndecl ) ; } } </s>


<s> bool X86FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) && ! MF . getInfo < X86MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> void HexagonTargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { const SDLoc & dl ( N ) ; switch ( N -> getOpcode ( ) ) { case ISD :: SRL : case ISD :: SRA : case ISD :: SHL : return ; case ISD :: BITCAST : if ( N -> getValueType ( 0 ) == MVT :: i8 ) { SDValue P = getInstr ( Hexagon :: C2_tfrpr , dl , MVT :: i32 , N -> getOperand ( 0 ) , DAG ) ; Results . push_back ( P ) ; } break ; } } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


"Frame offsets outside of the signed 32-bit range not supported"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool Z80FrameLowering :: hasFP ( const MachineFunction & MF ) const { return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) . hasStackObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
bool
AMDGPULegalizerInfo
::
legalizeCustom
(
LegalizerHelper
&
Helper
,
MachineInstr
&
MI
)
const
{
MachineIRBuilder
&
B
=
Helper
.
MIRBuilder
;
MachineRegisterInfo
&
MRI
=
*
B
.
getMRI
(
)
;
switch
(
MI
.
getOpcode
(
)
)
{
case
TargetOpcode
::
G_ADDRSPACE_CAST
:
return
legalizeAddrSpaceCast
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FRINT
:
return
legalizeFrint
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FCEIL
:
return
legalizeFceil
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FREM
:
return
legalizeFrem
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_INTRINSIC_TRUNC
:
return
legalizeIntrinsicTrunc
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_SITOFP
:
return
legalizeITOFP
(
MI
,
MRI
,
B
,
true
)
;
case
TargetOpcode
::
G_UITOFP
:
return
legalizeITOFP
(
MI
,
MRI
,
B
,
false
)
;
case
TargetOpcode
::
G_FPTOSI
:
return
legalizeFPTOI
(
MI
,
MRI
,
B
,
true
)
;
case
TargetOpcode
::
G_FPTOUI
:
return
legalizeFPTOI
(
MI
,
MRI
,
B
,
false
)
;
case
TargetOpcode
::
G_FMINNUM
:
case
TargetOpcode
::
G_FMAXNUM
:
case
TargetOpcode
::
G_FMINNUM_IEEE
:
case
TargetOpcode
::
G_FMAXNUM_IEEE
:
return
legalizeMinNumMaxNum
(
Helper
,
MI
)
;
case
TargetOpcode
::
G_EXTRACT_VECTOR_ELT
:
return
legalizeExtractVectorElt
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_INSERT_VECTOR_ELT
:
return
legalizeInsertVectorElt
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_SHUFFLE_VECTOR
:
return
legalizeShuffleVector
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FSIN
:
case
TargetOpcode
::
G_FCOS
:
return
legalizeSinCos
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_GLOBAL_VALUE
:
return
legalizeGlobalValue
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_LOAD
:
return
legalizeLoad
(
Helper
,
MI
)
;
case
TargetOpcode
::
G_FMAD
:
return
legalizeFMad
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FDIV
:
return
legalizeFDIV
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_UDIV
:
case
TargetOpcode
::
G_UREM
:
return
legalizeUDIV_UREM
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_SDIV
:
case
TargetOpcode
::
G_SREM
:
return
legalizeSDIV_SREM
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_ATOMIC_CMPXCHG
:
return
legalizeAtomicCmpXChg
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FLOG
:
return
legalizeFlog
(
MI
,
B
,
numbers
::
ln2f
)
;
case
TargetOpcode
::
G_FLOG10
:
return
legalizeFlog
(
MI
,
B
,
numbers
::
ln2f
/
numbers
::
ln10f
)
;
case
TargetOpcode
::
G_FEXP
:
return
legalizeFExp
(
MI
,
B
)
;
case
TargetOpcode
::
G_FPOW
:
return
legalizeFPow
(
MI
,
B
)
;
case
TargetOpcode
::
G_FFLOOR
:
return
legalizeFFloor
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_BUILD_VECTOR
:
return
legalizeBuildVector
(
MI
,
MRI
,
B
)
;
default
:
return
false
;
}
llvm_unreachable
(
"expected switch to return"
)
;
}
</s>

Called for instructions with the Custom LegalizationAction .

AMDGPU
AMDGPU
SI
SI
SI
SI
"expected switch to return"


<s> const ARMBaseInstrInfo * getInstrInfo ( ) const { return InstrInfo . get ( ) ; } </s>


<s>
static
const
char
*
output_probe_stack_range_1
(
rtx
reg1
,
rtx
reg2
)
{
static
int
labelno
=
0
;
char
loop_lab
[
32
]
;
rtx
xops
[
2
]
;
ASM_GENERATE_INTERNAL_LABEL
(
loop_lab
,
"LPSRL"
,
labelno
++
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
loop_lab
)
;
xops
[
0
]
=
reg1
;
xops
[
1
]
=
GEN_INT
(
PROBE_INTERVAL
)
;
output_asm_insn
(
"addi %0,%0,%1"
,
xops
)
;
xops
[
1
]
=
gen_rtx_REG
(
Pmode
,
0
)
;
output_asm_insn
(
"stw %1,0(%0)"
,
xops
)
;
xops
[
1
]
=
reg2
;
if
(
TARGET_64BIT
)
output_asm_insn
(
"cmpd 0,%0,%1"
,
xops
)
;
else
output_asm_insn
(
"cmpw 0,%0,%1"
,
xops
)
;
fputs
(
"\tbne 0,"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
loop_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
return
""
;
}
</s>

Probe a range of stack addresses from REG1 to REG2 inclusive . These are addresses , not offsets .


"m88k: Larger offsets not yet supported."


<s>
bool
Z80AsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Operands
.
push_back
(
Z80Operand
::
CreateToken
(
Name
,
NameLoc
)
)
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
return
false
;
if
(
ParseOperand
(
Operands
)
)
return
true
;
while
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
auto
CurrentTokenKind
=
getLexer
(
)
.
getKind
(
)
;
if
(
CurrentTokenKind
==
AsmToken
::
Comma
)
{
getLexer
(
)
.
Lex
(
)
;
continue
;
}
if
(
ParseOperand
(
Operands
)
)
return
true
;
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
return
Error
(
getLexer
(
)
.
getTok
(
)
.
getLoc
(
)
,
"unexpected token in operand list"
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .


<s> bool X86IndirectBranchTrackingPass :: runOnMachineFunction ( MachineFunction & MF ) { const X86Subtarget & SubTarget = MF . getSubtarget < X86Subtarget > ( ) ; Metadata * isCFProtectionSupported = MF . getMMI ( ) . getModule ( ) -> getModuleFlag ( "cf-protection-branch" ) ; if ( ! isCFProtectionSupported && ! IndirectBranchTracking ) return false ; bool Changed = false ; TII = SubTarget . getInstrInfo ( ) ; EndbrOpcode = SubTarget . is64Bit ( ) ? X86 :: ENDBR64 : X86 :: ENDBR32 ; if ( ( MF . getFunction ( ) . hasAddressTaken ( ) || ! MF . getFunction ( ) . hasLocalLinkage ( ) ) && ! MF . getFunction ( ) . doesNoCfCheck ( ) ) { auto MBB = MF . begin ( ) ; Changed |= addENDBR ( * MBB , MBB -> begin ( ) ) ; } for ( auto & MBB : MF ) { if ( MBB . hasAddressTaken ( ) ) Changed |= addENDBR ( MBB , MBB . begin ( ) ) ; bool EHPadIBTNeeded = MBB . isEHPad ( ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( I -> isCall ( ) && IsCallReturnTwice ( I -> getOperand ( 0 ) ) ) Changed |= addENDBR ( MBB , std :: next ( I ) ) ; if ( EHPadIBTNeeded && I -> isEHLabel ( ) ) { Changed |= addENDBR ( MBB , std :: next ( I ) ) ; EHPadIBTNeeded = false ; } } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool prepare_extend_operands ( rtx * operands , enum rtx_code code , machine_mode omode ) { if ( ! TARGET_NO_SDATA_SET && small_data_pattern ( operands [ 1 ] , Pmode ) ) { operands [ 1 ] = gen_rtx_fmt_e ( code , omode , arc_rewrite_small_data ( operands [ 1 ] ) ) ; emit_insn ( gen_rtx_SET ( omode , operands [ 0 ] , operands [ 1 ] ) ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , operands [ 1 ] ) ; emit_move_insn ( operands [ 0 ] , operands [ 0 ] ) ; return true ; } return false ; } </s>

Prepare OPERANDS for an extension using CODE to OMODE . Return true iff the move has been emitted .


<s> int arm_attr_length_move_neon ( rtx_insn * insn ) { rtx reg , mem , addr ; int load ; machine_mode mode ; extract_insn_cached ( insn ) ; if ( REG_P ( recog_data . operand [ 0 ] ) && REG_P ( recog_data . operand [ 1 ] ) ) { mode = GET_MODE ( recog_data . operand [ 0 ] ) ; switch ( mode ) { case EImode : case OImode : return 8 ; case CImode : return 12 ; case XImode : return 16 ; default : gcc_unreachable ( ) ; } } load = REG_P ( recog_data . operand [ 0 ] ) ; reg = recog_data . operand [ ! load ] ; mem = recog_data . operand [ load ] ; gcc_assert ( MEM_P ( mem ) ) ; mode = GET_MODE ( reg ) ; addr = XEXP ( mem , 0 ) ; if ( GET_CODE ( addr ) == CONST && GET_CODE ( XEXP ( addr , 0 ) ) == PLUS ) addr = XEXP ( addr , 0 ) ; if ( GET_CODE ( addr ) == LABEL_REF || GET_CODE ( addr ) == PLUS ) { int insns = HARD_REGNO_NREGS ( REGNO ( reg ) , mode ) / 2 ; return insns * 4 ; } else return 4 ; } </s>

Compute and return the length of neon_mov < mode > , where < mode > is one of VSTRUCT modes : EI , OI , CI or XI .


<s> uint32_t fpDenormModeDPValue ( ) const { if ( FP64FP16InputDenormals && FP64FP16OutputDenormals ) return FP_DENORM_FLUSH_NONE ; if ( FP64FP16InputDenormals ) return FP_DENORM_FLUSH_OUT ; if ( FP64FP16OutputDenormals ) return FP_DENORM_FLUSH_IN ; return FP_DENORM_FLUSH_IN_FLUSH_OUT ; } </s>

Get the encoding value for the FP_DENORM bits of the mode register for the FP64/FP16 denormal mode .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> unsigned LanaiRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return Lanai :: FP ; } </s>


"Don't know how to custom type legalize this operation!"

"READCYCLECOUNTER only has custom type legalization on riscv32"


<s> StringRef X86IntelInstPrinter :: getOpcodeName ( unsigned Opcode ) const { return getInstructionName ( Opcode ) ; } </s>

Return a string representation for an opcode .


<s> bool HexagonHardwareLoops :: isDead ( const MachineInstr * MI , SmallVectorImpl < MachineInstr * > & DeadPhis ) const { for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( MRI -> use_nodbg_empty ( Reg ) ) continue ; typedef MachineRegisterInfo :: use_nodbg_iterator use_nodbg_iterator ; use_nodbg_iterator I = MRI -> use_nodbg_begin ( Reg ) ; use_nodbg_iterator End = MRI -> use_nodbg_end ( ) ; if ( std :: next ( I ) != End || ! I -> getParent ( ) -> isPHI ( ) ) return false ; MachineInstr * OnePhi = I -> getParent ( ) ; for ( unsigned j = 0 , f = OnePhi -> getNumOperands ( ) ; j != f ; ++ j ) { const MachineOperand & OPO = OnePhi -> getOperand ( j ) ; if ( ! OPO . isReg ( ) || ! OPO . isDef ( ) ) continue ; unsigned OPReg = OPO . getReg ( ) ; use_nodbg_iterator nextJ ; for ( use_nodbg_iterator J = MRI -> use_nodbg_begin ( OPReg ) ; J != End ; J = nextJ ) { nextJ = std :: next ( J ) ; MachineOperand & Use = * J ; MachineInstr * UseMI = Use . getParent ( ) ; if ( MI != UseMI ) return false ; } } DeadPhis . push_back ( OnePhi ) ; } return true ; } </s>

isDead - Returns true if this is a dead def kill slot .


<s> void sh_pr_interrupt ( struct cpp_reader * pfile ATTRIBUTE_UNUSED ) { sh_add_function_attribute ( "interrupt_handler" ) ; } </s>

Handle machine specific pragmas to be semi-compatible with Hitachi compiler .


<s> bool XNCMFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; XNCMMachineFunctionInfo * MFI = MF . getInfo < XNCMMachineFunctionInfo > ( ) ; MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> MachineInstr * X86InstrInfo :: optimizeLoadInstr ( MachineInstr * MI , const MachineRegisterInfo * MRI , unsigned & FoldAsLoadDefReg , MachineInstr * & DefMI ) const { if ( FoldAsLoadDefReg == 0 ) return nullptr ; if ( MI -> mayLoad ( ) ) { FoldAsLoadDefReg = 0 ; return nullptr ; } DefMI = MRI -> getVRegDef ( FoldAsLoadDefReg ) ; assert ( DefMI ) ; bool SawStore = false ; if ( ! DefMI -> isSafeToMove ( this , nullptr , SawStore ) ) return nullptr ; unsigned IdxEnd = ( MI -> isCommutable ( ) ) ? 2 : 1 ; for ( unsigned Idx = 0 ; Idx < IdxEnd ; Idx ++ ) { unsigned SrcOperandId = 0 ; bool FoundSrcOperand = false ; for ( unsigned i = 0 , e = MI -> getDesc ( ) . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg != FoldAsLoadDefReg ) continue ; if ( MO . getSubReg ( ) || MO . isDef ( ) || FoundSrcOperand ) return nullptr ; SrcOperandId = i ; FoundSrcOperand = true ; } if ( ! FoundSrcOperand ) return nullptr ; SmallVector < unsigned , 8 > Ops ; Ops . push_back ( SrcOperandId ) ; MachineInstr * FoldMI = foldMemoryOperand ( MI , Ops , DefMI ) ; if ( FoldMI ) { FoldAsLoadDefReg = 0 ; return FoldMI ; } if ( Idx == 1 ) { commuteInstruction ( MI , false ) ; return nullptr ; } if ( MI -> isCommutable ( ) ) { MachineInstr * NewMI = commuteInstruction ( MI , false ) ; if ( ! NewMI ) return nullptr ; if ( NewMI != MI ) { NewMI -> eraseFromParent ( ) ; return nullptr ; } } } return nullptr ; } </s>

optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use .


<s> SDValue Cpu0TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_Cpu0 ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static int msp430_single_op_cost ( rtx dst , bool speed , rtx ) { enum rtx_code dst_code = GET_CODE ( dst ) ; const struct single_op_cost * cost_p ; const struct double_op_cost * double_op_cost_p ; cost_p = ( speed ? & cycle_cost_single_op : & size_cost_single_op ) ; double_op_cost_p = ( speed ? & cycle_cost_double_op : & size_cost_double_op ) ; switch ( dst_code ) { case REG : return cost_p -> reg ; case MEM : if ( msp430_is_mem_indirect ( dst ) ) return cost_p -> ind ; else return cost_p -> mem ; case CONST_INT : case CONST_FIXED : case CONST_DOUBLE : case SYMBOL_REF : case CONST : return double_op_cost_p -> imm2r + cost_p -> reg ; default : return cost_p -> mem ; } } </s>

Calculate the cost of an MSP430 single-operand instruction , for operand DST within the RTX OUTER_RTX , optimizing for speed if SPEED is true .


<s> void PIC16TargetLowering :: LowerOperationWrapper ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) { SDValue Op = SDValue ( N , 0 ) ; SDValue Res ; unsigned i ; switch ( Op . getOpcode ( ) ) { case ISD :: LOAD : Res = ExpandLoad ( Op . getNode ( ) , DAG ) ; break ; default : { Res = LowerOperation ( Op , DAG ) ; if ( Res . getNode ( ) ) Results . push_back ( Res ) ; return ; } } N = Res . getNode ( ) ; unsigned NumValues = N -> getNumValues ( ) ; for ( i = 0 ; i < NumValues ; i ++ ) { Results . push_back ( SDValue ( N , i ) ) ; } } </s>

This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types .


<s> static rtx_insn * emit_frame_save ( rtx frame_reg , machine_mode mode , unsigned int regno , int offset , HOST_WIDE_INT frame_reg_to_sp ) { rtx reg ; gcc_checking_assert ( ! ( ( TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE ( mode ) ) || ( TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) ) || ( TARGET_E500_DOUBLE && mode == DFmode ) || ( TARGET_SPE_ABI && SPE_VECTOR_MODE ( mode ) && ! SPE_CONST_OFFSET_OK ( offset ) ) ) ) ; reg = gen_rtx_REG ( mode , regno ) ; rtx_insn * insn = emit_insn ( gen_frame_store ( reg , frame_reg , offset ) ) ; return rs6000_frame_related ( insn , frame_reg , frame_reg_to_sp , NULL_RTX , NULL_RTX ) ; } </s>

Save a register into the frame , and emit RTX_FRAME_RELATED_P notes . Save REGNO into [ FRAME_REG + OFFSET ] in mode MODE .


<s> void Thumb2InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( ARM :: GPRRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( ARM :: t2STRi12 ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; return ; } if ( ARM :: GPRPairRegClass . hasSubClassEq ( RC ) ) { if ( Register :: isVirtualRegister ( SrcReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( SrcReg , & ARM :: GPRPairnospRegClass ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( ARM :: t2STRDi8 ) ) ; AddDReg ( MIB , SrcReg , ARM :: gsub_0 , getKillRegState ( isKill ) , TRI ) ; AddDReg ( MIB , SrcReg , ARM :: gsub_1 , 0 , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; return ; } ARMBaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg , isKill , FI , RC , TRI ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> static void ix86_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; HOST_WIDE_INT bytes , words ; int nregs ; if ( ! cum -> caller && cfun -> machine -> func_type != TYPE_NORMAL ) return ; if ( mode == BLKmode ) bytes = int_size_in_bytes ( type ) ; else bytes = GET_MODE_SIZE ( mode ) ; words = CEIL ( bytes , UNITS_PER_WORD ) ; if ( type ) mode = type_natural_mode ( type , NULL , false ) ; if ( ( type && POINTER_BOUNDS_TYPE_P ( type ) ) || POINTER_BOUNDS_MODE_P ( mode ) ) { if ( cum -> bnds_in_bt ) { cum -> bnds_in_bt -- ; return ; } if ( cum -> force_bnd_pass ) cum -> force_bnd_pass -- ; cum -> bnd_regno ++ ; return ; } cum -> bnds_in_bt = 0 ; if ( cum -> force_bnd_pass ) { cum -> bnd_regno += cum -> force_bnd_pass ; cum -> force_bnd_pass = 0 ; } if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) nregs = function_arg_advance_ms_64 ( cum , bytes , words ) ; else nregs = function_arg_advance_64 ( cum , mode , type , words , named ) ; } else nregs = function_arg_advance_32 ( cum , mode , type , bytes , words ) ; if ( cum -> stdarg ) cum -> force_bnd_pass = nregs ; if ( ! nregs ) cum -> bnds_in_bt = chkp_type_bounds_count ( type ) ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> unsigned PPCRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const PPCFrameLowering * TFI = getFrameLowering ( MF ) ; const unsigned DefaultSafety = 1 ; switch ( RC -> getID ( ) ) { default : return 0 ; case PPC :: G8RC_NOX0RegClassID : case PPC :: GPRC_NOR0RegClassID : case PPC :: G8RCRegClassID : case PPC :: GPRCRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 32 - FP - DefaultSafety ; } case PPC :: F8RCRegClassID : case PPC :: F4RCRegClassID : case PPC :: QFRCRegClassID : case PPC :: QSRCRegClassID : case PPC :: QBRCRegClassID : case PPC :: VRRCRegClassID : case PPC :: VFRCRegClassID : case PPC :: VSLRCRegClassID : case PPC :: VSHRCRegClassID : return 32 - DefaultSafety ; case PPC :: VSRCRegClassID : case PPC :: VSFRCRegClassID : case PPC :: VSSRCRegClassID : return 64 - DefaultSafety ; case PPC :: CRRCRegClassID : return 8 - DefaultSafety ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> bool X86PassConfig :: addPostRegAlloc ( ) { PM . add ( createX86FloatingPointStackifierPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> void analyze ( MachineBasicBlock & DefBlock , ArrayRef < MachineBasicBlock * > IncomingBlocks ) { assert ( Stack . empty ( ) ) ; ReachableMap . clear ( ) ; ReachableOrdered . clear ( ) ; Predecessors . clear ( ) ; ReachableMap . try_emplace ( & DefBlock , false ) ; ReachableOrdered . push_back ( & DefBlock ) ; for ( MachineBasicBlock * MBB : IncomingBlocks ) { if ( MBB == & DefBlock ) { ReachableMap [ & DefBlock ] = true ; continue ; } ReachableMap . try_emplace ( MBB , false ) ; ReachableOrdered . push_back ( MBB ) ; bool Divergent = false ; for ( MachineInstr & MI : MBB -> terminators ( ) ) { if ( MI . getOpcode ( ) == AMDGPU :: SI_NON_UNIFORM_BRCOND_PSEUDO || MI . getOpcode ( ) == AMDGPU :: SI_IF || MI . getOpcode ( ) == AMDGPU :: SI_ELSE || MI . getOpcode ( ) == AMDGPU :: SI_LOOP ) { Divergent = true ; break ; } } if ( Divergent && PDT . dominates ( & DefBlock , MBB ) ) append_range ( Stack , MBB -> successors ( ) ) ; } while ( ! Stack . empty ( ) ) { MachineBasicBlock * MBB = Stack . pop_back_val ( ) ; if ( ! ReachableMap . try_emplace ( MBB , false ) . second ) continue ; ReachableOrdered . push_back ( MBB ) ; append_range ( Stack , MBB -> successors ( ) ) ; } for ( MachineBasicBlock * MBB : ReachableOrdered ) { bool HaveReachablePred = false ; for ( MachineBasicBlock * Pred : MBB -> predecessors ( ) ) { if ( ReachableMap . count ( Pred ) ) { HaveReachablePred = true ; } else { Stack . push_back ( Pred ) ; } } if ( ! HaveReachablePred ) ReachableMap [ MBB ] = true ; if ( HaveReachablePred ) { for ( MachineBasicBlock * UnreachablePred : Stack ) { if ( ! llvm :: is_contained ( Predecessors , UnreachablePred ) ) Predecessors . push_back ( UnreachablePred ) ; } } Stack . clear ( ) ; } } </s>

analyze - set CurLI to the specified interval , and analyze how it may be split .


<s> unsigned X86FastISel :: fastMaterializeFloatZero ( const ConstantFP * CF ) { MVT VT ; if ( ! isTypeLegal ( CF -> getType ( ) , VT ) ) return 0 ; bool HasSSE1 = Subtarget -> hasSSE1 ( ) ; bool HasSSE2 = Subtarget -> hasSSE2 ( ) ; bool HasAVX512 = Subtarget -> hasAVX512 ( ) ; unsigned Opc = 0 ; switch ( VT . SimpleTy ) { default : return 0 ; case MVT :: f32 : Opc = HasAVX512 ? X86 :: AVX512_FsFLD0SS : HasSSE1 ? X86 :: FsFLD0SS : X86 :: LD_Fp032 ; break ; case MVT :: f64 : Opc = HasAVX512 ? X86 :: AVX512_FsFLD0SD : HasSSE2 ? X86 :: FsFLD0SD : X86 :: LD_Fp064 ; break ; case MVT :: f80 : return 0 ; } Register ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; return ResultReg ; } </s>

Emit the floating-point constant +0.0 in a register using target- specific logic .


<s> SDNode * SparcDAGToDAGISel :: Select ( SDValue Op ) { SDNode * N = Op . getNode ( ) ; DebugLoc dl = N -> getDebugLoc ( ) ; if ( N -> isMachineOpcode ( ) ) return NULL ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: SDIV : case ISD :: UDIV : { SDValue DivLHS = N -> getOperand ( 0 ) ; SDValue DivRHS = N -> getOperand ( 1 ) ; SDValue TopPart ; if ( N -> getOpcode ( ) == ISD :: SDIV ) { TopPart = SDValue ( CurDAG -> getTargetNode ( SP :: SRAri , dl , MVT :: i32 , DivLHS , CurDAG -> getTargetConstant ( 31 , MVT :: i32 ) ) , 0 ) ; } else { TopPart = CurDAG -> getRegister ( SP :: G0 , MVT :: i32 ) ; } TopPart = SDValue ( CurDAG -> getTargetNode ( SP :: WRYrr , dl , MVT :: Flag , TopPart , CurDAG -> getRegister ( SP :: G0 , MVT :: i32 ) ) , 0 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: SDIV ? SP :: SDIVrr : SP :: UDIVrr ; return CurDAG -> SelectNodeTo ( N , Opcode , MVT :: i32 , DivLHS , DivRHS , TopPart ) ; } case ISD :: MULHU : case ISD :: MULHS : { SDValue MulLHS = N -> getOperand ( 0 ) ; SDValue MulRHS = N -> getOperand ( 1 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: MULHU ? SP :: UMULrr : SP :: SMULrr ; SDNode * Mul = CurDAG -> getTargetNode ( Opcode , dl , MVT :: i32 , MVT :: Flag , MulLHS , MulRHS ) ; return CurDAG -> SelectNodeTo ( N , SP :: RDY , MVT :: i32 , SDValue ( Mul , 1 ) ) ; return NULL ; } } return SelectCode ( Op ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> const uint32_t * SIRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { switch ( CC ) { case CallingConv :: C : case CallingConv :: Fast : return CSR_AMDGPU_HighRegs_RegMask ; default : return nullptr ; } } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool CAHPMCExpr :: evaluateAsConstant ( int64_t & Res ) const { MCValue Value ; if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ) return false ; if ( ! Value . isAbsolute ( ) ) return false ; Res = evaluateAsInt64 ( Value . getConstant ( ) ) ; return true ; } </s>

Evaluates the fixup as a constant value .


<s> bool mayStore ( ) const { return ( Store ) ; } </s>

Return true if this instruction could possibly modify memory .


<s> static bool mips_use_shadow_register_set_p ( tree type ) { return lookup_attribute ( "use_shadow_register_set" , TYPE_ATTRIBUTES ( type ) ) != NULL ; } </s>

Check if the attribute to use shadow register set is set for a function .


<s> EVT R600TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> OperandMatchResultTy SparcAsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { const AsmToken & Tok = Parser . getTok ( ) ; StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; RegNo = 0 ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Percent ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; unsigned regKind = SparcOperand :: rk_None ; if ( matchRegisterName ( Tok , RegNo , regKind ) ) { Parser . Lex ( ) ; return MatchOperand_Success ; } getLexer ( ) . UnLex ( Tok ) ; return MatchOperand_NoMatch ; } </s>

tryParseRegister - parse one register if possible


<s>
bool
PPCTargetMachine
::
isLittleEndian
(
)
const
{
assert
(
Endianness
!=
Endian
::
NOT_DETECTED
&&
"Unable to determine endianness"
)
;
return
Endianness
==
Endian
::
LITTLE
;
}
</s>

Tests whether the target triple is little endian .

PowerPC
PPC
"Unable to determine endianness"


<s> static rtx rs6000_complex_function_value ( machine_mode mode ) { unsigned int regno ; rtx r1 , r2 ; machine_mode inner = GET_MODE_INNER ( mode ) ; unsigned int inner_bytes = GET_MODE_SIZE ( inner ) ; if ( FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = FP_ARG_RETURN ; else { regno = GP_ARG_RETURN ; if ( TARGET_32BIT && inner_bytes >= 4 ) return gen_rtx_REG ( mode , regno ) ; } if ( inner_bytes >= 8 ) return gen_rtx_REG ( mode , regno ) ; r1 = gen_rtx_EXPR_LIST ( inner , gen_rtx_REG ( inner , regno ) , const0_rtx ) ; r2 = gen_rtx_EXPR_LIST ( inner , gen_rtx_REG ( inner , regno + 1 ) , GEN_INT ( inner_bytes ) ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , r1 , r2 ) ) ; } </s>

Return an RTX representing where to find the function value of a function returning MODE .


<s> static void mep_reorg_noframe ( rtx_insn * insns ) { rtx_insn * start_frame_insn ; rtx_insn * end_frame_insn = 0 ; int sp_adjust , sp2 ; rtx sp ; while ( insns && ! INSN_P ( insns ) ) insns = NEXT_INSN ( insns ) ; if ( ! insns ) return ; sp_adjust = add_sp_insn_p ( insns ) ; if ( sp_adjust == 0 ) return ; start_frame_insn = insns ; sp = SET_DEST ( PATTERN ( start_frame_insn ) ) ; insns = next_real_insn ( insns ) ; while ( insns ) { rtx_insn * next = next_real_insn ( insns ) ; if ( ! next ) break ; sp2 = add_sp_insn_p ( insns ) ; if ( sp2 ) { if ( end_frame_insn ) return ; end_frame_insn = insns ; if ( sp2 != - sp_adjust ) return ; } else if ( mep_mentioned_p ( insns , sp , 0 ) ) return ; else if ( CALL_P ( insns ) ) return ; insns = next ; } if ( end_frame_insn ) { delete_insn ( start_frame_insn ) ; delete_insn ( end_frame_insn ) ; } } </s>

Check for trivial functions that set up an unneeded stack frame .


<s> bool X86RegisterInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo * MMI = MFI -> getMachineModuleInfo ( ) ; return ( NoFramePointerElim || needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || ( MMI && MMI -> callsUnwindInit ( ) ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static bool riscv_cannot_force_const_mem ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { enum riscv_symbol_type type ; rtx base , offset ; if ( GET_CODE ( x ) == HIGH ) return true ; split_const ( x , & base , & offset ) ; if ( riscv_symbolic_constant_p ( base , & type ) ) { if ( SMALL_OPERAND ( INTVAL ( offset ) ) && riscv_symbol_insns ( type ) > 0 ) return true ; if ( flag_pic ) return true ; } if ( tls_referenced_p ( x ) ) return true ; return false ; } </s>


<s> bool isLegalMaskedScatter ( Type * DataType , MaybeAlign Alignment ) { return isVectorLaneType ( * getLaneType ( DataType ) ) ; } </s>

Return true if the target supports masked scatter .


<s> static rtx ix86_load_returned_bounds ( rtx slot ) { rtx res ; gcc_assert ( REG_P ( slot ) ) ; res = gen_reg_rtx ( BNDmode ) ; emit_move_insn ( res , slot ) ; return res ; } </s>

Load and return bounds returned by function in SLOT .


<s> static rtx x86_this_parameter ( tree function ) { tree type = TREE_TYPE ( function ) ; if ( TARGET_64BIT ) { int n = aggregate_value_p ( TREE_TYPE ( type ) , type ) != 0 ; return gen_rtx_REG ( DImode , x86_64_int_parameter_registers [ n ] ) ; } if ( ix86_function_regparm ( type , function ) > 0 ) { tree parm ; parm = TYPE_ARG_TYPES ( type ) ; for ( ; parm ; parm = TREE_CHAIN ( parm ) ) if ( TREE_VALUE ( parm ) == void_type_node ) break ; if ( parm ) { int regno = 0 ; if ( lookup_attribute ( "fastcall" , TYPE_ATTRIBUTES ( type ) ) ) regno = 2 ; return gen_rtx_REG ( SImode , regno ) ; } } if ( aggregate_value_p ( TREE_TYPE ( type ) , type ) ) return gen_rtx_MEM ( SImode , plus_constant ( stack_pointer_rtx , 8 ) ) ; else return gen_rtx_MEM ( SImode , plus_constant ( stack_pointer_rtx , 4 ) ) ; } </s>

Returns an expression indicating where the this parameter is located on entry to the FUNCTION .


<s> void MipsPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; addPass ( createAtomicExpandPass ( ) ) ; if ( getMipsSubtarget ( ) . os16 ( ) ) addPass ( createMipsOs16Pass ( ) ) ; if ( getMipsSubtarget ( ) . inMips16HardFloat ( ) ) addPass ( createMips16HardFloatPass ( ) ) ; if ( getMipsSubtarget ( ) . isCheri ( ) ) { addPass ( createCheriLoopPointerDecanonicalize ( ) ) ; addPass ( createAggressiveDCEPass ( ) ) ; addPass ( createCheriRangeChecker ( ) ) ; addPass ( createCheriBoundAllocasPass ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s>
MachineBasicBlock
*
SystemZTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
const
SystemZInstrInfo
&
TII
=
*
TM
.
getInstrInfo
(
)
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
assert
(
(
MI
->
getOpcode
(
)
==
SystemZ
::
Select32
||
MI
->
getOpcode
(
)
==
SystemZ
::
SelectF32
||
MI
->
getOpcode
(
)
==
SystemZ
::
Select64
||
MI
->
getOpcode
(
)
==
SystemZ
::
SelectF64
)
&&
"Unexpected instr type to insert"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
I
=
BB
;
++
I
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
copy1MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
SystemZCC
::
CondCodes
CC
=
(
SystemZCC
::
CondCodes
)
MI
->
getOperand
(
3
)
.
getImm
(
)
;
BuildMI
(
BB
,
dl
,
TII
.
getBrCond
(
CC
)
)
.
addMBB
(
copy1MBB
)
;
F
->
insert
(
I
,
copy0MBB
)
;
F
->
insert
(
I
,
copy1MBB
)
;
copy1MBB
->
transferSuccessors
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
copy1MBB
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
copy1MBB
)
;
BB
=
copy1MBB
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
SystemZ
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
F
->
DeleteMachineInstr
(
MI
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s>
const
char
*
getPassName
(
)
const
{
return
"Hexagon Hardware Loops"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> llvm :: FastISel * ARM :: createFastISel ( FunctionLoweringInfo & funcInfo ) { const TargetMachine & TM = funcInfo . MF -> getTarget ( ) ; const ARMSubtarget * Subtarget = & TM . getSubtarget < ARMSubtarget > ( ) ; if ( Subtarget -> isTargetDarwin ( ) && ! Subtarget -> isThumb1Only ( ) && ! DisableARMFastISel ) return new ARMFastISel ( funcInfo ) ; return 0 ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .

ARM ARM::createFastISel ARM ARM ARM ARM 0


<s> const uint32_t * ARMBaseRegisterInfo :: getCallPreservedMask ( CallingConv :: ID ) const { if ( ReserveR9 ) return CSR_NaCl_RegMask ; return ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


"WDC_TODO - Write code for returning a structure as a hidden input arg pointer"

"WDC_TODO - needsCustom() in register location!"

"WDC_TODO - Write code for register location"

"WDC_TODO - needsCustom() in memory location, offset="

"WDC_TODO - Write code for memory location, offset="

"WDC_TODO - Write code for hasStructRetAttr()"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> void func_fma_steering :: dfs ( void ( * process_forest ) ( fma_forest * ) , void ( * process_root ) ( fma_forest * , fma_root_node * ) , void ( * process_node ) ( fma_forest * , fma_node * ) , bool free ) { auto_vec < fma_node * > to_process ; auto_vec < fma_node * > to_free ; std :: list < fma_forest * > :: iterator forest_iter ; for ( forest_iter = this -> m_fma_forests . begin ( ) ; forest_iter != this -> m_fma_forests . end ( ) ; ++ forest_iter ) { std :: list < fma_root_node * > :: iterator root_iter ; if ( process_forest ) process_forest ( * forest_iter ) ; for ( root_iter = ( * forest_iter ) -> get_roots ( ) -> begin ( ) ; root_iter != ( * forest_iter ) -> get_roots ( ) -> end ( ) ; ++ root_iter ) { if ( process_root ) process_root ( * forest_iter , * root_iter ) ; to_process . safe_push ( * root_iter ) ; } while ( ! to_process . is_empty ( ) ) { fma_node * node ; std :: list < fma_node * > :: iterator child_iter ; node = to_process . pop ( ) ; if ( process_node ) process_node ( * forest_iter , node ) ; for ( child_iter = node -> get_children ( ) -> begin ( ) ; child_iter != node -> get_children ( ) -> end ( ) ; ++ child_iter ) to_process . safe_push ( * child_iter ) ; if ( free ) to_free . safe_push ( node ) ; } if ( free ) { delete * forest_iter ; while ( ! to_free . is_empty ( ) ) { fma_node * node = to_free . pop ( ) ; if ( node -> root_p ( ) ) delete static_cast < fma_root_node * > ( node ) ; else delete node ; } } } } </s>

Perform a depth-first search of the forests of fma_node in THIS- > m_fma_forests , calling PROCESS_FOREST ( ) on each fma_forest object in THIS- > m_fma_forests list , PROCESS_ROOT ( ) on each tree root and PROCESS_NODE ( ) on each node . If FREE is true , free all std : :list in the same dfs .


<s> bool AMDGPUPromoteAlloca :: doInitialization ( Module & M ) { Mod = & M ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> void SystemZHazardRecognizer :: Reset ( ) { CurrGroupSize = 0 ; CurrGroupHas4RegOps = false ; clearProcResCounters ( ) ; GrpCount = 0 ; LastFPdOpCycleIdx = UINT_MAX ; LastEmittedMI = nullptr ; LLVM_DEBUG ( CurGroupDbg = "" ; ) ; } </s>


<s> static int sh_round_reg ( const CUMULATIVE_ARGS & cum , machine_mode mode ) { return ( ( ( TARGET_ALIGN_DOUBLE || ( TARGET_FPU_DOUBLE && ( mode == DFmode || mode == DCmode ) && cum . arg_count [ ( int ) SH_ARG_FLOAT ] < NPARM_REGS ( mode ) ) ) && GET_MODE_UNIT_SIZE ( mode ) > UNITS_PER_WORD ) ? ( cum . arg_count [ ( int ) get_sh_arg_class ( mode ) ] + ( cum . arg_count [ ( int ) get_sh_arg_class ( mode ) ] & 1 ) ) : cum . arg_count [ ( int ) get_sh_arg_class ( mode ) ] ) ; } </s>

Round a register number up to a proper boundary for an arg of mode MODE . The SH does n't care about double alignment , so we only round doubles to even regs when asked to explicitly .


<s> void X86DAGToDAGISel :: PostprocessISelDAG ( ) { if ( TM . getOptLevel ( ) == CodeGenOpt :: None ) return ; SelectionDAG :: allnodes_iterator Position = CurDAG -> allnodes_end ( ) ; bool MadeChange = false ; while ( Position != CurDAG -> allnodes_begin ( ) ) { SDNode * N = & * -- Position ; if ( N -> use_empty ( ) || ! N -> isMachineOpcode ( ) ) continue ; if ( tryOptimizeRem8Extend ( N ) ) { MadeChange = true ; continue ; } if ( N -> getMachineOpcode ( ) != TargetOpcode :: SUBREG_TO_REG ) continue ; unsigned SubRegIdx = N -> getConstantOperandVal ( 2 ) ; if ( SubRegIdx != X86 :: sub_xmm && SubRegIdx != X86 :: sub_ymm ) continue ; SDValue Move = N -> getOperand ( 1 ) ; if ( ! Move . isMachineOpcode ( ) ) continue ; switch ( Move . getMachineOpcode ( ) ) { default : continue ; case X86 :: VMOVAPDrr : case X86 :: VMOVUPDrr : case X86 :: VMOVAPSrr : case X86 :: VMOVUPSrr : case X86 :: VMOVDQArr : case X86 :: VMOVDQUrr : case X86 :: VMOVAPDYrr : case X86 :: VMOVUPDYrr : case X86 :: VMOVAPSYrr : case X86 :: VMOVUPSYrr : case X86 :: VMOVDQAYrr : case X86 :: VMOVDQUYrr : case X86 :: VMOVAPDZ128rr : case X86 :: VMOVUPDZ128rr : case X86 :: VMOVAPSZ128rr : case X86 :: VMOVUPSZ128rr : case X86 :: VMOVDQA32Z128rr : case X86 :: VMOVDQU32Z128rr : case X86 :: VMOVDQA64Z128rr : case X86 :: VMOVDQU64Z128rr : case X86 :: VMOVAPDZ256rr : case X86 :: VMOVUPDZ256rr : case X86 :: VMOVAPSZ256rr : case X86 :: VMOVUPSZ256rr : case X86 :: VMOVDQA32Z256rr : case X86 :: VMOVDQU32Z256rr : case X86 :: VMOVDQA64Z256rr : case X86 :: VMOVDQU64Z256rr : break ; } SDValue In = Move . getOperand ( 0 ) ; if ( ! In . isMachineOpcode ( ) || In . getMachineOpcode ( ) <= TargetOpcode :: GENERIC_OP_END ) continue ; uint64_t TSFlags = getInstrInfo ( ) -> get ( In . getMachineOpcode ( ) ) . TSFlags ; if ( ( TSFlags & X86II :: EncodingMask ) != X86II :: VEX && ( TSFlags & X86II :: EncodingMask ) != X86II :: EVEX && ( TSFlags & X86II :: EncodingMask ) != X86II :: XOP ) continue ; CurDAG -> UpdateNodeOperands ( N , N -> getOperand ( 0 ) , In , N -> getOperand ( 2 ) ) ; MadeChange = true ; } if ( MadeChange ) CurDAG -> RemoveDeadNodes ( ) ; } </s>

PostprocessISelDAG ( ) - This hook allows the target to hack on the graph right after selection .


<s> rtx arm_gen_compare_reg ( enum rtx_code code , rtx x , rtx y , rtx scratch ) { machine_mode mode ; rtx cc_reg ; int dimode_comparison = GET_MODE ( x ) == DImode || GET_MODE ( y ) == DImode ; if ( dimode_comparison && ! REG_P ( x ) ) x = force_reg ( DImode , x ) ; mode = SELECT_CC_MODE ( code , x , y ) ; cc_reg = gen_rtx_REG ( mode , CC_REGNUM ) ; if ( dimode_comparison && mode != CC_CZmode ) { rtx clobber , set ; if ( mode == CC_Zmode && y != const0_rtx ) { gcc_assert ( ! reload_completed ) ; x = expand_binop ( DImode , xor_optab , x , y , NULL_RTX , 0 , OPTAB_WIDEN ) ; y = const0_rtx ; } if ( reload_completed ) gcc_assert ( scratch != NULL && GET_MODE ( scratch ) == SImode ) ; else scratch = gen_rtx_SCRATCH ( SImode ) ; clobber = gen_rtx_CLOBBER ( VOIDmode , scratch ) ; set = gen_rtx_SET ( VOIDmode , cc_reg , gen_rtx_COMPARE ( mode , x , y ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set , clobber ) ) ) ; } else emit_set_insn ( cc_reg , gen_rtx_COMPARE ( mode , x , y ) ) ; return cc_reg ; } </s>

X and Y are two things to compare using CODE . Emit the compare insn and return the rtx for register 0 in the proper mode . FP means this is a floating point compare : I do n't think that it is needed on the arm .


"Maximum length for HLASM Label is 63 characters"

"HLASM Label has to start with an alphabetic "

Returns true if the MachineInstr represents a label .


<s> Clone ( const FnProperties & Props , Function * OrigF , Function * NewF ) : Properties ( Props ) , OrigF ( OrigF ) , NewF ( NewF ) { } </s>

Clone - Creates a clone of the specified SUnit .


runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> SDValue AMDGPUTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , SDLoc DL , SelectionDAG & DAG ) const { return DAG . getNode ( AMDGPUISD :: RET_FLAG , DL , MVT :: Other , Chain ) ; } </s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .

AMDGPU AMDGPU ISD::OutputArg AMDGPUISD::RET_FLAG MVT::Other


<s> static tree aarch64_lookup_simd_type_in_table ( machine_mode mode , enum aarch64_type_qualifiers qualifiers ) { int i ; int nelts = ARRAY_SIZE ( aarch64_simd_types ) ; int q = qualifiers & ( qualifier_poly | qualifier_unsigned ) ; for ( i = 0 ; i < nelts ; i ++ ) { if ( aarch64_simd_types [ i ] . mode == mode && aarch64_simd_types [ i ] . q == q ) return aarch64_simd_types [ i ] . itype ; if ( aarch64_simd_tuple_types [ i ] [ 0 ] != NULL_TREE ) for ( int j = 0 ; j < 3 ; j ++ ) if ( aarch64_simd_tuple_modes [ i ] [ j ] == mode && aarch64_simd_types [ i ] . q == q ) return aarch64_simd_tuple_types [ i ] [ j ] ; } return NULL_TREE ; } </s>

Helper function for aarch64_simd_builtin_type .


<s> XCoreTargetMachine :: XCoreTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo ( ) ; } </s>


<s> int thumb_legitimate_offset_p ( machine_mode mode , HOST_WIDE_INT val ) { switch ( GET_MODE_SIZE ( mode ) ) { case 1 : return val >= 0 && val < 32 ; case 2 : return val >= 0 && val < 64 && ( val & 1 ) == 0 ; default : return ( val >= 0 && ( val + GET_MODE_SIZE ( mode ) ) <= 128 && ( val & 3 ) == 0 ) ; } } </s>

Return nonzero if VAL can be used as an offset in a Thumb-state address instruction of mode MODE .


<s> bool TeakInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { bool HasCondBranch = false ; TBB = nullptr ; FBB = nullptr ; for ( MachineInstr & MI : MBB ) { if ( MI . getOpcode ( ) == Teak :: BRR_rel7 ) { MachineBasicBlock * TargetBB = MI . getOperand ( 0 ) . getMBB ( ) ; if ( HasCondBranch ) FBB = TargetBB ; else TBB = TargetBB ; } else if ( MI . getOpcode ( ) == Teak :: BRRCond_rel7 || MI . getOpcode ( ) == Teak :: BR_imm18 ) { TBB = MI . getOperand ( 0 ) . getMBB ( ) ; Cond . push_back ( MI . getOperand ( 1 ) ) ; HasCondBranch = true ; } else if ( MI . getOpcode ( ) == Teak :: RET ) return true ; } return false ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


Relax the instruction in the given fragment to the next wider instruction .


<s> static bool sparc_frame_pointer_required ( void ) { if ( cfun -> calls_alloca ) return true ; if ( cfun -> has_nonlocal_label ) return true ; if ( TARGET_FLAT ) return false ; return ! ( crtl -> is_leaf && only_leaf_regs_used ( ) ) ; } </s>


<s> static int alpha_adjust_cost ( rtx_insn * insn , int dep_type , rtx_insn * dep_insn , int cost , unsigned int ) { enum attr_type dep_insn_type ; if ( dep_type != 0 ) return cost ; if ( recog_memoized ( insn ) < 0 || recog_memoized ( dep_insn ) < 0 ) return cost ; dep_insn_type = get_attr_type ( dep_insn ) ; if ( dep_insn_type == TYPE_ILD || dep_insn_type == TYPE_FLD || dep_insn_type == TYPE_LDSYM ) cost += alpha_memory_latency - 1 ; return cost ; } </s>

Adjust the cost of a scheduling dependency . Return the new cost of a dependency LINK or INSN on DEP_INSN . COST is the current cost .


"AArch64 load / store optimization pass"

getPassName - Return a nice clean name for a pass .


<s>
static
char
*
match_integer
(
void
)
{
int
startpos
=
pos
;
if
(
linebuf
[
pos
]
==
'-'
)
safe_inc_pos
(
)
;
int
lastpos
=
pos
1
;
while
(
lastpos
<
LINELEN
1
&&
isdigit
(
linebuf
[
lastpos
+
1
]
)
)
++
lastpos
;
if
(
lastpos
>=
LINELEN
1
)
{
diag
(
lastpos
,
"line length overrun.\n"
)
;
exit
(
1
)
;
}
if
(
lastpos
<
pos
)
return
;
pos
=
lastpos
+
1
;
char
*
buf
=
(
char
*
)
malloc
(
lastpos
startpos
+
2
)
;
memcpy
(
buf
,
&
linebuf
[
startpos
]
,
lastpos
startpos
+
1
)
;
buf
[
lastpos
startpos
+
1
]
=
'\0'
;
return
buf
;
}
</s>

Match an integer and return the string representing its value , or a null string on failure .


<s> unsigned X86FrameLowering :: getWinEHFuncletFrameSize ( const MachineFunction & MF ) const { unsigned CSSize = MF . getInfo < X86MachineFunctionInfo > ( ) -> getCalleeSavedFrameSize ( ) ; unsigned UsedSize ; EHPersonality Personality = classifyEHPersonality ( MF . getFunction ( ) -> getPersonalityFn ( ) ) ; if ( Personality == EHPersonality :: CoreCLR ) { UsedSize = getPSPSlotOffsetFromSP ( MF ) + SlotSize ; } else { UsedSize = MF . getFrameInfo ( ) -> getMaxCallFrameSize ( ) ; } unsigned FrameSizeMinusRBP = RoundUpToAlignment ( CSSize + UsedSize , getStackAlignment ( ) ) ; return FrameSizeMinusRBP - CSSize ; } </s>

Funclets only need to account for space for the callee saved registers , as the locals are accounted for in the parent 's stack frame .


<s> int avr_peep2_scratch_safe ( rtx scratch ) { if ( ( interrupt_function_p ( current_function_decl ) || signal_function_p ( current_function_decl ) ) && leaf_function_p ( ) ) { int first_reg = true_regnum ( scratch ) ; int last_reg = first_reg + GET_MODE_SIZE ( GET_MODE ( scratch ) ) - 1 ; int reg ; for ( reg = first_reg ; reg <= last_reg ; reg ++ ) { if ( ! regs_ever_live [ reg ] ) return 0 ; } } return 1 ; } </s>

Returns 1 if SCRATCH are safe to be allocated as a scratch registers ( for a define_peephole2 ) in the current function .


<s> static void emit_v9_brxx_insn ( enum rtx_code code , rtx op0 , rtx label ) { emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ) ) ; } </s>

Emit a conditional jump insn for the v9 architecture using comparison code CODE and jump target LABEL . This function exists to take advantage of the v9 brxx insns .


<s> TargetPassConfig * Dcpu16TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new Dcpu16PassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> unsigned PPCFrameLowering :: determineFrameLayout ( MachineFunction & MF , bool UpdateMF , bool UseEstimate ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = UseEstimate ? MFI -> estimateStackSize ( MF ) : MFI -> getStackSize ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - 1 ; bool DisableRedZone = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoRedZone ) ; if ( ! DisableRedZone && ( Subtarget . isPPC64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == 0 ) && FrameSize <= 224 && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! ( Subtarget . isPPC64 ( ) && Subtarget . isSVR4ABI ( ) && spillsCR ( MF ) ) && ( ! ALIGN_STACK || MaxAlign <= TargetAlign ) ) { if ( UpdateMF ) MFI -> setStackSize ( 0 ) ; return 0 ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getMinCallFrameSize ( Subtarget . isPPC64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setStackSize ( FrameSize ) ; return FrameSize ; } </s>

Determine the frame layout but do not update the machine function .


<s> static rtx_insn * emit_sp_adjust ( int offset , int * next_scratch_regno , bool frame_related , rtx reg_notes ) { rtx to_add ; rtx imm_rtx = gen_int_si ( offset ) ; rtx_insn * insn ; if ( satisfies_constraint_J ( imm_rtx ) ) { to_add = imm_rtx ; } else { rtx tmp = gen_rtx_REG ( Pmode , ( * next_scratch_regno ) -- ) ; tilepro_expand_set_const32 ( tmp , imm_rtx ) ; to_add = tmp ; } insn = emit_insn ( gen_sp_adjust ( stack_pointer_rtx , stack_pointer_rtx , to_add ) ) ; REG_NOTES ( insn ) = reg_notes ; if ( frame_related ) { rtx real = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , imm_rtx ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , real ) ; } return insn ; } </s>

This emits code for 'sp += offset ' . The ABI only allows us to modify 'sp ' in a single 'addi ' or 'addli ' , so the backtracer understands it . Larger amounts can not use those instructions , so are added by placing the offset into a large register and using 'add ' . This happens after reload , so we need to expand it ourselves .


<s> const char * Z80TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( Z80ISD :: NodeType ) Opcode ) { case Z80ISD :: FIRST_NUMBER : break ; case Z80ISD :: Wrapper : return "Z80ISD::Wrapper" ; case Z80ISD :: RLC : return "Z80ISD::RLC" ; case Z80ISD :: RRC : return "Z80ISD::RRC" ; case Z80ISD :: RL : return "Z80ISD::RL" ; case Z80ISD :: RR : return "Z80ISD::RR" ; case Z80ISD :: SLA : return "Z80ISD::SLA" ; case Z80ISD :: SRA : return "Z80ISD::SRA" ; case Z80ISD :: SRL : return "Z80ISD::SRL" ; case Z80ISD :: INC : return "Z80ISD::INC" ; case Z80ISD :: DEC : return "Z80ISD::DEC" ; case Z80ISD :: ADD : return "Z80ISD::ADD" ; case Z80ISD :: ADC : return "Z80ISD::ADC" ; case Z80ISD :: SUB : return "Z80ISD::SUB" ; case Z80ISD :: SBC : return "Z80ISD::SBC" ; case Z80ISD :: AND : return "Z80ISD::AND" ; case Z80ISD :: XOR : return "Z80ISD::XOR" ; case Z80ISD :: OR : return "Z80ISD::OR" ; case Z80ISD :: CP : return "Z80ISD::CP" ; case Z80ISD :: TST : return "Z80ISD::TST" ; case Z80ISD :: MLT : return "Z80ISD::MLT" ; case Z80ISD :: SEXT : return "Z80ISD::SEXT" ; case Z80ISD :: CALL : return "Z80ISD::CALL" ; case Z80ISD :: RET_FLAG : return "Z80ISD::RET_FLAG" ; case Z80ISD :: RETN_FLAG : return "Z80ISD::RETN_FLAG" ; case Z80ISD :: RETI_FLAG : return "Z80ISD::RETI_FLAG" ; case Z80ISD :: TC_RETURN : return "Z80ISD::TC_RETURN" ; case Z80ISD :: BRCOND : return "Z80ISD::BRCOND" ; case Z80ISD :: SELECT : return "Z80ISD::SELECT" ; case Z80ISD :: POP : return "Z80ISD::POP" ; case Z80ISD :: PUSH : return "Z80ISD::PUSH" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static void ia64_set_sched_flags ( spec_info_t spec_info ) { unsigned int * flags = & ( current_sched_info -> flags ) ; if ( * flags & SCHED_RGN || * flags & SCHED_EBB || * flags & SEL_SCHED ) { int mask = 0 ; if ( ( mflag_sched_br_data_spec && ! reload_completed && optimize > 0 ) || ( mflag_sched_ar_data_spec && reload_completed ) ) { mask |= BEGIN_DATA ; if ( ! sel_sched_p ( ) && ( ( mflag_sched_br_in_data_spec && ! reload_completed ) || ( mflag_sched_ar_in_data_spec && reload_completed ) ) ) mask |= BE_IN_DATA ; } if ( mflag_sched_control_spec && ( ! sel_sched_p ( ) || reload_completed ) ) { mask |= BEGIN_CONTROL ; if ( ! sel_sched_p ( ) && mflag_sched_in_control_spec ) mask |= BE_IN_CONTROL ; } spec_info -> mask = mask ; if ( mask ) { * flags |= USE_DEPS_LIST | DO_SPECULATION ; if ( mask & BE_IN_SPEC ) * flags |= NEW_BBS ; spec_info -> flags = 0 ; if ( ( mask & CONTROL_SPEC ) && sel_sched_p ( ) && mflag_sel_sched_dont_check_control_spec ) spec_info -> flags |= SEL_SCHED_SPEC_DONT_CHECK_CONTROL ; if ( sched_verbose >= 1 ) spec_info -> dump = sched_dump ; else spec_info -> dump = 0 ; if ( mflag_sched_count_spec_in_critical_path ) spec_info -> flags |= COUNT_SPEC_IN_CRITICAL_PATH ; } } else spec_info -> mask = 0 ; } </s>

Provide information about speculation capabilities .


<s>
bool
X86TargetLowering
::
shouldExpandAtomicRMWInIR
(
AtomicRMWInst
*
AI
)
const
{
const
X86Subtarget
&
Subtarget
=
getTargetMachine
(
)
.
getSubtarget
<
X86Subtarget
>
(
)
;
unsigned
NativeWidth
=
Subtarget
.
is64Bit
(
)
64
:
32
;
const
Type
*
MemType
=
AI
->
getType
(
)
;
if
(
MemType
->
getPrimitiveSizeInBits
(
)
>
NativeWidth
)
return
needsCmpXchgNb
(
MemType
)
;
AtomicRMWInst
::
BinOp
Op
=
AI
->
getOperation
(
)
;
switch
(
Op
)
{
default
:
llvm_unreachable
(
"Unknown atomic operation"
)
;
case
AtomicRMWInst
::
Xchg
:
case
AtomicRMWInst
::
Add
:
case
AtomicRMWInst
::
Sub
:
return
false
;
case
AtomicRMWInst
::
Or
:
case
AtomicRMWInst
::
And
:
case
AtomicRMWInst
::
Xor
:
return
!
AI
->
use_empty
(
)
;
case
AtomicRMWInst
::
Nand
:
case
AtomicRMWInst
::
Max
:
case
AtomicRMWInst
::
Min
:
case
AtomicRMWInst
::
UMax
:
case
AtomicRMWInst
::
UMin
:
return
true
;
}
}
</s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> static int microblaze_version_to_int ( const char * version ) { const char * p , * v ; const char * tmpl = "vXX.YY.Z" ; int iver = 0 ; p = version ; v = tmpl ; while ( * p ) { if ( * v == 'X' ) { if ( * p == '.' ) { v ++ ; } else { if ( ! ( * p >= '0' && * p <= '9' ) ) return - 1 ; iver += ( int ) ( * p - '0' ) ; iver *= 10 ; } } else if ( * v == 'Y' ) { if ( ! ( * p >= '0' && * p <= '9' ) ) return - 1 ; iver += ( int ) ( * p - '0' ) ; iver *= 10 ; } else if ( * v == 'Z' ) { if ( ! ( * p >= 'a' && * p <= 'z' ) ) return - 1 ; iver *= 10 ; iver += ( int ) ( * p - 'a' ) ; } else { if ( * p != * v ) return - 1 ; } v ++ ; p ++ ; } if ( * p ) return - 1 ; return iver ; } </s>

Convert a version number of the form `` vX.YY.Z '' to an integer encoding for easier range comparison .


<s> MachineBasicBlock :: iterator ARMBaseInstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , const outliner :: Candidate & C ) const { MachineInstrBuilder MIB ; MachineBasicBlock :: iterator CallPt ; unsigned Opc ; bool isThumb = Subtarget . isThumb ( ) ; if ( C . CallConstructionID == MachineOutlinerTailCall ) { Opc = isThumb ? Subtarget . isTargetMachO ( ) ? ARM :: tTAILJMPd : ARM :: tTAILJMPdND : ARM :: TAILJMPd ; MIB = BuildMI ( MF , DebugLoc ( ) , get ( Opc ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ; if ( isThumb ) MIB . add ( predOps ( ARMCC :: AL ) ) ; It = MBB . insert ( It , MIB ) ; return It ; } Opc = isThumb ? ARM :: tBL : ARM :: BL ; MachineInstrBuilder CallMIB = BuildMI ( MF , DebugLoc ( ) , get ( Opc ) ) ; if ( isThumb ) CallMIB . add ( predOps ( ARMCC :: AL ) ) ; CallMIB . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ; It = MBB . insert ( It , CallMIB ) ; return It ; } </s>

Insert a call to an outlined function into the program .

ARM ARM ARM::tTAILJMPd ARM::tTAILJMPdND ARM::TAILJMPd ARMCC::AL ARM::tBL ARM::BL ARMCC::AL


<s> MCExpr const * HexagonNoExtendOperand :: getExpr ( ) const { return Expr ; } </s>

Implementation of the SCEVPredicate interface .


<s> static rtx ix86_function_arg ( cumulative_args_t cum_v , machine_mode omode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; machine_mode mode = omode ; HOST_WIDE_INT bytes , words ; rtx arg ; if ( ! cum -> caller && cfun -> machine -> func_type != TYPE_NORMAL ) { gcc_assert ( type != NULL_TREE ) ; if ( POINTER_TYPE_P ( type ) ) { gcc_assert ( TYPE_MODE ( type ) == Pmode ) ; if ( cfun -> machine -> func_type == TYPE_INTERRUPT ) arg = plus_constant ( Pmode , arg_pointer_rtx , - UNITS_PER_WORD ) ; else arg = arg_pointer_rtx ; } else { gcc_assert ( cfun -> machine -> func_type == TYPE_EXCEPTION && TREE_CODE ( type ) == INTEGER_TYPE && TYPE_MODE ( type ) == word_mode ) ; arg = gen_rtx_MEM ( word_mode , plus_constant ( Pmode , arg_pointer_rtx , - UNITS_PER_WORD ) ) ; } return arg ; } if ( ( type && POINTER_BOUNDS_TYPE_P ( type ) ) || POINTER_BOUNDS_MODE_P ( mode ) ) { if ( cum -> bnds_in_bt ) arg = NULL ; else if ( cum -> bnd_regno <= LAST_BND_REG ) arg = gen_rtx_REG ( BNDmode , cum -> bnd_regno ) ; else arg = GEN_INT ( cum -> bnd_regno - LAST_BND_REG - 1 ) ; return arg ; } if ( mode == BLKmode ) bytes = int_size_in_bytes ( type ) ; else bytes = GET_MODE_SIZE ( mode ) ; words = CEIL ( bytes , UNITS_PER_WORD ) ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) mode = type_natural_mode ( type , cum , false ) ; if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) arg = function_arg_ms_64 ( cum , mode , omode , named , bytes ) ; else arg = function_arg_64 ( cum , mode , omode , type , named ) ; } else arg = function_arg_32 ( cum , mode , omode , type , bytes , words ) ; return arg ; } </s>

Return where to put the arguments to a function . Return zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument . It is null for libcalls where that information may not be available . CUM gives information about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) .


<s> void MOSInstructionSelector :: constrainOperandRegClass ( MachineOperand & RegMO , const TargetRegisterClass & RegClass ) { MachineInstr & MI = * RegMO . getParent ( ) ; MachineRegisterInfo & MRI = MI . getMF ( ) -> getRegInfo ( ) ; RegMO . setReg ( llvm :: constrainOperandRegClass ( * MF , TRI , MRI , TII , RBI , MI , RegClass , RegMO ) ) ; } </s>

Try to constrain Op so that it is usable by argument OpNum of the provided MCInstrDesc .


<s> bool hasAddressTaken ( ) const { if ( MBB ) return MBB -> hasAddressTaken ( ) ; return false ; } </s>

Test whether this block is used as something other than the target of a terminator , exception-handling target , or jump table .


<s> void setShrinkWrapDisabled ( bool U ) { ShrinkWrapDisabled = U ; } </s>

We certainly do n't want to shrink wrap functions if we 've emitted a MovePCtoLR8 as that has to go into the entry , so the prologue definitely has to go into the entry block .


<s> const Triple & getTargetTriple ( ) const { return TargetTriple ; } </s>

Get the target triple which is a string describing the target host .


<s> bool runOnModule ( Module & M ) override { LLVM_DEBUG ( dbgs ( ) << getPassName ( ) << '\n' ) ; if ( skipModule ( M ) ) return false ; bool Changed = false ; PromotionCacheTy PromotionCache ; for ( auto & MF : M ) { Changed |= runOnFunction ( MF , PromotionCache ) ; } return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> bool PPCTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , MachineMemOperand :: Flags , bool * Fast ) const { if ( DisablePPCUnaligned ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( VT . isFloatingPoint ( ) && ! Subtarget . allowsUnalignedFPAccess ( ) ) return false ; if ( VT . getSimpleVT ( ) . isVector ( ) ) { if ( Subtarget . hasVSX ( ) ) { if ( VT != MVT :: v2f64 && VT != MVT :: v2i64 && VT != MVT :: v4f32 && VT != MVT :: v4i32 ) return false ; } else { return false ; } } if ( VT == MVT :: ppcf128 ) return false ; if ( Fast ) * Fast = true ; return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s>
const
char
*
getPassName
(
)
const
{
return
"SI Lower literal constants pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void tilegx_emit_conditional_branch ( rtx operands [ ] , machine_mode cmp_mode ) { rtx cmp_rtx = tilegx_emit_cc_test ( GET_CODE ( operands [ 0 ] ) , operands [ 1 ] , operands [ 2 ] , cmp_mode , false ) ; rtx branch_rtx = gen_rtx_SET ( pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , cmp_rtx , gen_rtx_LABEL_REF ( VOIDmode , operands [ 3 ] ) , pc_rtx ) ) ; emit_jump_insn ( branch_rtx ) ; } </s>

Generate the comparison for a conditional branch .


<s> const char * WebAssemblyTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( static_cast < WebAssemblyISD :: NodeType > ( Opcode ) ) { case WebAssemblyISD :: FIRST_NUMBER : case WebAssemblyISD :: FIRST_MEM_OPCODE : break ; case WebAssemblyISD :: NODE : \ return "WebAssemblyISD::" # NODE ; } return nullptr ; } </s>

WebAssembly WebAssembly WebAssemblyISD::NodeType WebAssemblyISD::FIRST_NUMBER WebAssemblyISD::FIRST_MEM_OPCODE WebAssemblyISD::NODE "WebAssemblyISD::"


<s> void gen_shifty_hi_op ( int code , rtx * operands ) { int value = INTVAL ( operands [ 2 ] ) ; int max , i ; void ( * gen_fun ) ( int , int , rtx ) ; value &= 31 ; if ( value == 0 ) { emit_insn ( gen_nop ( ) ) ; return ; } gen_fun = GET_MODE ( operands [ 0 ] ) == HImode ? gen_ashift_hi : gen_ashift ; if ( code == ASHIFT ) { max = ext_ashl_lshr_seq [ value ] . insn_count ; for ( i = 0 ; i < max ; i ++ ) gen_fun ( code , ext_ashl_lshr_seq [ value ] . amount [ i ] , operands [ 0 ] ) ; } else for ( i = ext_ashl_lshr_seq [ value ] . insn_count - 1 ; i >= 0 ; i -- ) gen_fun ( code , ext_ashl_lshr_seq [ value ] . amount [ i ] , operands [ 0 ] ) ; } </s>

Same as above , but optimized for values where the topmost bits do n't matter .


<s> void HexagonShuffler :: reset ( ) { Packet . clear ( ) ; BundleFlags = 0 ; } </s>

Reset an existing scalar value for Def and a given Instance .


"getBranchTargetOpValueMM expects only expressions or immediates"

getBranchTargetOpValue - Return binary encoding of the microMIPS branch target operand .


<s> static tls_model or1k_tls_symbolic_operand ( rtx op ) { rtx sym , addend ; split_const ( op , & sym , & addend ) ; if ( SYMBOL_REF_P ( sym ) ) return SYMBOL_REF_TLS_MODEL ( sym ) ; return TLS_MODEL_NONE ; } </s>

Return the TLS type for TLS symbols , 0 otherwise .


<s> rtx frv_find_base_term ( rtx x ) { struct frv_unspec unspec ; if ( frv_const_unspec_p ( x , & unspec ) && frv_small_data_reloc_p ( unspec . symbol , unspec . reloc ) ) return plus_constant ( Pmode , unspec . symbol , unspec . offset ) ; return x ; } </s>

Implement FIND_BASE_TERM . See whether ORIG_X represents # gprel12 ( foo ) or # gotoff12 ( foo ) for some small data symbol foo . If so , return foo , otherwise return ORIG_X .


<s>
bool
SIFixWWMLiveness
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"SIFixWWMLiveness: function "
<<
MF
.
getName
(
)
<<
"\n"
)
;
bool
Modified
=
false
;
LIS
=
getAnalysisIfAvailable
<
LiveIntervals
>
(
)
;
const
GCNSubtarget
&
ST
=
MF
.
getSubtarget
<
GCNSubtarget
>
(
)
;
TII
=
ST
.
getInstrInfo
(
)
;
TRI
=
&
TII
->
getRegisterInfo
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
DomTree
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
LoopInfo
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
for
(
MachineInstr
&
MI
:
MBB
)
{
if
(
MI
.
getOpcode
(
)
==
AMDGPU
::
EXIT_WWM
)
WWMs
.
push_back
(
&
MI
)
;
else
{
for
(
MachineOperand
&
DefOpnd
:
MI
.
defs
(
)
)
{
if
(
DefOpnd
.
isReg
(
)
)
{
unsigned
Reg
=
DefOpnd
.
getReg
(
)
;
if
(
TRI
->
isVGPR
(
*
MRI
,
Reg
)
)
processDef
(
DefOpnd
)
;
}
}
}
}
}
if
(
!
WWMs
.
empty
(
)
)
{
for
(
auto
ThenDef
:
ThenDefs
)
Modified
|=
processThenDef
(
ThenDef
)
;
for
(
auto
LoopExitDef
:
LoopExitDefs
)
Modified
|=
processLoopExitDef
(
LoopExitDef
.
first
,
LoopExitDef
.
second
)
;
for
(
auto
LoopPhiDef
:
LoopPhiDefs
)
Modified
|=
processLoopPhiDef
(
LoopPhiDef
.
first
,
LoopPhiDef
.
second
)
;
}
WWMs
.
clear
(
)
;
ThenDefs
.
clear
(
)
;
LoopExitDefs
.
clear
(
)
;
LoopPhiDefs
.
clear
(
)
;
return
Modified
;
}
</s>

runOnMachineFunction - Emit the function body .

AMDGPU
SI
"SIFixWWMLiveness: function "
"\n"
AMDGPU::EXIT_WWM


<s> AMDGPUSubtarget & AMDGPUSubtarget :: initializeSubtargetDependencies ( const Triple & TT , StringRef GPU , StringRef FS ) { SmallString < 256 > FullFS ( "+promote-alloca,+fp64-denormals," ) ; if ( isAmdHsaOS ( ) ) FullFS += "+flat-for-global," ; FullFS += FS ; ParseSubtargetFeatures ( GPU , FullFS ) ; if ( getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) { FP32Denormals = false ; FP64Denormals = false ; } return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .

AMDGPU AMDGPU AMDGPU 256 "+promote-alloca,+fp64-denormals," "+flat-for-global," AMDGPU