<s> bool cris_valid_pic_const ( const_rtx x , bool any_operand ) { gcc_assert ( flag_pic ) ; switch ( GET_CODE ( x ) ) { case CONST_INT : case CONST_DOUBLE : return true ; default : ; } if ( GET_CODE ( x ) != CONST ) return false ; x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 0 ) ) == UNSPEC && ( XINT ( XEXP ( x , 0 ) , 1 ) == CRIS_UNSPEC_GOTREL || XINT ( XEXP ( x , 0 ) , 1 ) == CRIS_UNSPEC_PCREL ) && CONST_INT_P ( XEXP ( x , 1 ) ) ) x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , 1 ) ) { case CRIS_UNSPEC_PLT_PCREL : case CRIS_UNSPEC_PCREL : return ! any_operand ; case CRIS_UNSPEC_PLT_GOTREL : case CRIS_UNSPEC_PLTGOTREAD : case CRIS_UNSPEC_GOTREAD : case CRIS_UNSPEC_GOTREL : return true ; default : gcc_unreachable ( ) ; } return cris_symbol_type_of ( x ) == cris_no_symbol ; } </s>

Return TRUE iff X is a CONST valid for e.g . indexing .


<s> static unsigned addLiveIn ( MachineFunction & MF , unsigned PReg , const TargetRegisterClass * RC ) { unsigned VReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MF . getRegInfo ( ) . addLiveIn ( PReg , VReg ) ; return VReg ; } </s>

addLiveIn - Add the specified register as a live-in .


<s> TargetTransformInfo VETargetMachine :: getTargetTransformInfo ( const Function & F ) { return TargetTransformInfo ( VETTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> unsigned int vectors_per_tuple ( ) const override { return m_vectors_per_tuple ; } </s>

If the function operates on tuples of vectors , return the number of vectors in the tuples , otherwise return 1 .


<s> ISD :: NodeType getExtendForAtomicOps ( ) const override { return ISD :: ANY_EXTEND ; } </s>

Returns how the platform 's atomic operations are extended ( ZERO_EXTEND , SIGN_EXTEND , or ANY_EXTEND ) .


<s> const LM32InstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> EVT RISCVTargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return getPointerTy ( DL ) ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> bool HexagonBitSimplify :: getConst ( const BitTracker :: RegisterCell & RC , uint16_t B , uint16_t W , uint64_t & U ) { assert ( B < RC . width ( ) && B + W <= RC . width ( ) ) ; int64_t T = 0 ; for ( uint16_t i = B + W ; i > B ; -- i ) { const BitTracker :: BitValue & BV = RC [ i - 1 ] ; T <<= 1 ; if ( BV . is ( 1 ) ) T |= 1 ; else if ( ! BV . is ( 0 ) ) return false ; } U = T ; return true ; } </s>


<s> bool MipsTargetLowering :: IsEligibleForTailCallOptimization ( const MipsCC & MipsCCInfo , unsigned NextStackOffset , const MipsFunctionInfo & FI ) const { if ( ! EnableMipsTailCalls ) return false ; if ( Subtarget -> inMips16Mode ( ) ) return false ; if ( MipsCCInfo . hasByValArg ( ) || FI . hasByvalArg ( ) ) return false ; return NextStackOffset <= FI . nextStackOffset ( ) ; } </s>

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization .


<s> bool X86AsmBackend :: allowEnhancedRelaxation ( ) const { return allowAutoPadding ( ) && TargetPrefixMax != 0 && X86PadForBranchAlign ; } </s>

Return true if this target allows an unrelaxable instruction to be emitted into RelaxableFragment and then we can increase its size in a tricky way for optimization .


<s> ShapeKind getKind ( ) const { return Kind ; } </s>


<s> bool aarch64_return_address_signing_enabled ( void ) { gcc_assert ( cfun -> machine -> frame . laid_out ) ; return ( aarch64_ra_sign_scope == AARCH64_FUNCTION_ALL || ( aarch64_ra_sign_scope == AARCH64_FUNCTION_NON_LEAF && cfun -> machine -> frame . reg_offset [ LR_REGNUM ] >= 0 ) ) ; } </s>

Return TRUE if return address signing should be enabled for the current function , otherwise return FALSE .


<s> bool isUnconditionalBranch ( MCInst const & Inst ) const override { return MCInstrAnalysis :: isUnconditionalBranch ( Inst ) ; } </s>

Return true if this is a branch which always transfers control flow to some other block .


<s> static tree aarch64_builtin_reciprocal ( tree fndecl ) { machine_mode mode = TYPE_MODE ( TREE_TYPE ( fndecl ) ) ; if ( ! use_rsqrt_p ( mode ) ) return NULL_TREE ; return aarch64_builtin_rsqrt ( DECL_FUNCTION_CODE ( fndecl ) ) ; } </s>

Function to decide when to use the approximate reciprocal square root builtin .


<s> bool s390_can_use_return_insn ( void ) { int i ; if ( ! reload_completed ) return false ; if ( crtl -> profile ) return false ; if ( TARGET_TPF_PROFILING ) return false ; for ( i = 0 ; i < 16 ; i ++ ) if ( cfun_gpr_save_slot ( i ) ) return false ; if ( ! TARGET_64BIT && ( cfun_fpr_save_p ( FPR4_REGNUM ) || cfun_fpr_save_p ( FPR6_REGNUM ) ) ) return false ; if ( cfun -> machine -> base_reg && ! call_really_used_regs [ REGNO ( cfun -> machine -> base_reg ) ] ) return false ; return cfun_frame_layout . frame_size == 0 ; } </s>

Return true if the epilogue is guaranteed to contain only a return instruction and if a direct return can therefore be used instead . One of the main advantages of using direct return instructions is that we can then use conditional returns .


<s> SDValue AMDGPUTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & DL , SelectionDAG & DAG ) const { return DAG . getNode ( AMDGPUISD :: RET_FLAG , DL , MVT :: Other , Chain ) ; } </s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .

AMDGPU AMDGPU ISD::OutputArg AMDGPUISD::RET_FLAG MVT::Other


<s> static void ix86_emit_binop ( enum rtx_code code , machine_mode mode , rtx dst , rtx src ) { rtx op , clob ; op = gen_rtx_SET ( VOIDmode , dst , gen_rtx_fmt_ee ( code , mode , dst , src ) ) ; clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , op , clob ) ) ) ; } </s>

Emit x86 binary operand CODE in mode MODE , where the first operand matches destination . RTX includes clobber of FLAGS_REG .


<s> bool check ( function_checker & c ) const OVERRIDE { return c . require_immediate_range ( 2 , 0 , 7 ) ; } </s>

Perform semantic checks on the call . Return true if the call is valid , otherwise report a suitable error .


<s> rtx mips_subword_at_byte ( rtx op , unsigned int byte ) { machine_mode mode ; mode = GET_MODE ( op ) ; if ( mode == VOIDmode ) mode = TImode ; gcc_assert ( ! FP_REG_RTX_P ( op ) ) ; if ( MEM_P ( op ) ) return mips_rewrite_small_data ( adjust_address ( op , word_mode , byte ) ) ; return simplify_gen_subreg ( word_mode , op , mode , byte ) ; } </s>

Return one word of 128-bit value OP , taking into account the fixed endianness of certain registers . BYTE selects from the byte address .


<s> bool X86AsmBackend :: mayNeedRelaxation ( const MCInst & Inst ) const { if ( getRelaxedOpcodeBranch ( Inst , false ) != Inst . getOpcode ( ) ) return true ; if ( getRelaxedOpcodeArith ( Inst ) == Inst . getOpcode ( ) ) return false ; unsigned RelaxableOp = Inst . getNumOperands ( ) - 1 ; if ( Inst . getOperand ( RelaxableOp ) . isExpr ( ) ) return true ; return false ; } </s>

Check whether the given instruction may need relaxation .


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> void PTXFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


<s> static bool rs6000_scalar_mode_supported_p ( scalar_mode mode ) { if ( TARGET_32BIT && mode == TImode ) return false ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) return default_decimal_float_supported_p ( ) ; else if ( TARGET_FLOAT128_TYPE && ( mode == KFmode || mode == IFmode ) ) return true ; else return default_scalar_mode_supported_p ( mode ) ; } </s>

Target hook for scalar_mode_supported_p .


<s> MCSubtargetInfo const & HexagonMCCodeEmitter :: getSubtargetInfo ( ) const { return MST ; } </s>


<s> enum arc_function_type arc_compute_function_type ( tree decl ) { tree a ; static enum arc_function_type fn_type = ARC_FUNCTION_UNKNOWN ; static tree last_fn = NULL_TREE ; if ( decl == NULL_TREE ) { fn_type = ARC_FUNCTION_UNKNOWN ; last_fn = NULL_TREE ; return fn_type ; } if ( decl == last_fn && fn_type != ARC_FUNCTION_UNKNOWN ) return fn_type ; fn_type = ARC_FUNCTION_NORMAL ; for ( a = DECL_ATTRIBUTES ( current_function_decl ) ; a ; a = TREE_CHAIN ( a ) ) { tree name = TREE_PURPOSE ( a ) , args = TREE_VALUE ( a ) ; if ( name == get_identifier ( "__interrupt__" ) && list_length ( args ) == 1 && TREE_CODE ( TREE_VALUE ( args ) ) == STRING_CST ) { tree value = TREE_VALUE ( args ) ; if ( ! strcmp ( TREE_STRING_POINTER ( value ) , "ilink1" ) ) fn_type = ARC_FUNCTION_ILINK1 ; else if ( ! strcmp ( TREE_STRING_POINTER ( value ) , "ilink2" ) ) fn_type = ARC_FUNCTION_ILINK2 ; else gcc_unreachable ( ) ; break ; } } last_fn = decl ; return fn_type ; } </s>

Type of function DECL . The result is cached . To reset the cache at the end of a function , call with DECL = NULL_TREE .


<s> static unsigned getHashValue ( const CSKYTargetStreamer :: SymbolIndex & V ) { return hash_combine ( DenseMapInfo < const MCSymbol * > :: getHashValue ( V . sym ) , DenseMapInfo < int > :: getHashValue ( V . kind ) ) ; } </s>

Using name and line to get hash value . It should already be mostly unique .


<s> void OrderedRegisterList :: remove ( unsigned VR ) { iterator L = std :: lower_bound ( Seq . begin ( ) , Seq . end ( ) , VR , Ord ) ; if ( L != Seq . end ( ) ) Seq . erase ( L ) ; } </s>

remove - Remove the specified key/value pair from the map , but do not erase it .


<s> bool isImm ( ) const override { return Kind == Immediate ; } </s>


<s> Register RISCVRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? RISCV :: X8 : RISCV :: X2 ; } </s>


<s> bool AMDGPUInstructionSelector :: select ( MachineInstr & I ) { if ( I . isPHI ( ) ) return selectPHI ( I ) ; if ( ! I . isPreISelOpcode ( ) ) { if ( I . isCopy ( ) ) return selectCOPY ( I ) ; return true ; } switch ( I . getOpcode ( ) ) { case TargetOpcode :: G_AND : case TargetOpcode :: G_OR : case TargetOpcode :: G_XOR : if ( selectG_AND_OR_XOR ( I ) ) return true ; return selectImpl ( I , * CoverageInfo ) ; case TargetOpcode :: G_ADD : case TargetOpcode :: G_SUB : if ( selectImpl ( I , * CoverageInfo ) ) return true ; return selectG_ADD_SUB ( I ) ; case TargetOpcode :: G_UADDO : case TargetOpcode :: G_USUBO : case TargetOpcode :: G_UADDE : case TargetOpcode :: G_USUBE : return selectG_UADDO_USUBO_UADDE_USUBE ( I ) ; case TargetOpcode :: G_INTTOPTR : case TargetOpcode :: G_BITCAST : case TargetOpcode :: G_PTRTOINT : return selectCOPY ( I ) ; case TargetOpcode :: G_CONSTANT : case TargetOpcode :: G_FCONSTANT : return selectG_CONSTANT ( I ) ; case TargetOpcode :: G_EXTRACT : return selectG_EXTRACT ( I ) ; case TargetOpcode :: G_MERGE_VALUES : case TargetOpcode :: G_BUILD_VECTOR : case TargetOpcode :: G_CONCAT_VECTORS : return selectG_MERGE_VALUES ( I ) ; case TargetOpcode :: G_UNMERGE_VALUES : return selectG_UNMERGE_VALUES ( I ) ; case TargetOpcode :: G_PTR_ADD : return selectG_PTR_ADD ( I ) ; case TargetOpcode :: G_IMPLICIT_DEF : return selectG_IMPLICIT_DEF ( I ) ; case TargetOpcode :: G_INSERT : return selectG_INSERT ( I ) ; case TargetOpcode :: G_INTRINSIC : return selectG_INTRINSIC ( I ) ; case TargetOpcode :: G_INTRINSIC_W_SIDE_EFFECTS : return selectG_INTRINSIC_W_SIDE_EFFECTS ( I ) ; case TargetOpcode :: G_ICMP : if ( selectG_ICMP ( I ) ) return true ; return selectImpl ( I , * CoverageInfo ) ; case TargetOpcode :: G_LOAD : case TargetOpcode :: G_ATOMIC_CMPXCHG : case TargetOpcode :: G_ATOMICRMW_XCHG : case TargetOpcode :: G_ATOMICRMW_ADD : case TargetOpcode :: G_ATOMICRMW_SUB : case TargetOpcode :: G_ATOMICRMW_AND : case TargetOpcode :: G_ATOMICRMW_OR : case TargetOpcode :: G_ATOMICRMW_XOR : case TargetOpcode :: G_ATOMICRMW_MIN : case TargetOpcode :: G_ATOMICRMW_MAX : case TargetOpcode :: G_ATOMICRMW_UMIN : case TargetOpcode :: G_ATOMICRMW_UMAX : case TargetOpcode :: G_ATOMICRMW_FADD : return selectG_LOAD_ATOMICRMW ( I ) ; case TargetOpcode :: G_SELECT : return selectG_SELECT ( I ) ; case TargetOpcode :: G_STORE : return selectG_STORE ( I ) ; case TargetOpcode :: G_TRUNC : return selectG_TRUNC ( I ) ; case TargetOpcode :: G_SEXT : case TargetOpcode :: G_ZEXT : case TargetOpcode :: G_ANYEXT : if ( selectImpl ( I , * CoverageInfo ) ) return true ; return selectG_SZA_EXT ( I ) ; case TargetOpcode :: G_BRCOND : return selectG_BRCOND ( I ) ; case TargetOpcode :: G_FRAME_INDEX : return selectG_FRAME_INDEX ( I ) ; case TargetOpcode :: G_PTR_MASK : return selectG_PTR_MASK ( I ) ; case TargetOpcode :: G_EXTRACT_VECTOR_ELT : return selectG_EXTRACT_VECTOR_ELT ( I ) ; default : return selectImpl ( I , * CoverageInfo ) ; } return false ; } </s>

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s> bool intersects ( const RegisterSet & Rs ) const { return BitVector :: anyCommon ( Rs ) ; } </s>


<s> int aarch64_asm_preferred_eh_data_format ( int code ATTRIBUTE_UNUSED , int global ) { int type ; switch ( aarch64_cmodel ) { case AARCH64_CMODEL_TINY : case AARCH64_CMODEL_TINY_PIC : case AARCH64_CMODEL_SMALL : case AARCH64_CMODEL_SMALL_PIC : case AARCH64_CMODEL_SMALL_SPIC : type = DW_EH_PE_sdata4 ; break ; default : type = DW_EH_PE_sdata8 ; break ; } return ( global ? DW_EH_PE_indirect : 0 ) | DW_EH_PE_pcrel | type ; } </s>

Select a format to encode pointers in exception handling data .


<s> bool ARMBaseInstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF , bool OutlineFromLinkOnceODRs ) const { const Function & F = MF . getFunction ( ) ; if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) ) return false ; if ( F . hasSection ( ) ) return false ; if ( MF . getInfo < ARMFunctionInfo > ( ) -> isThumb1OnlyFunction ( ) ) return false ; return true ; } </s>

Return true if the function can safely be outlined from .


<s> static void find_constant_pool_ref ( rtx x , rtx * ref ) { int i , j ; const char * fmt ; if ( GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNSPEC_LTREL_BASE ) return ; if ( GET_CODE ( x ) == UNSPEC_VOLATILE && XINT ( x , 1 ) == UNSPECV_POOL_ENTRY ) return ; gcc_assert ( GET_CODE ( x ) != SYMBOL_REF || ! CONSTANT_POOL_ADDRESS_P ( x ) ) ; if ( GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNSPEC_LTREF ) { rtx sym = XVECEXP ( x , 0 , 0 ) ; gcc_assert ( GET_CODE ( sym ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( sym ) ) ; if ( * ref == NULL_RTX ) * ref = sym ; else gcc_assert ( * ref == sym ) ; return ; } fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'e' ) { find_constant_pool_ref ( XEXP ( x , i ) , ref ) ; } else if ( fmt [ i ] == 'E' ) { for ( j = 0 ; j < XVECLEN ( x , i ) ; j ++ ) find_constant_pool_ref ( XVECEXP ( x , i , j ) , ref ) ; } } } </s>

Find an annotated literal pool symbol referenced in RTX X , and store it at REF . Will abort if X contains references to more than one such pool symbol ; multiple references to the same symbol are allowed , however . The rtx pointed to by REF must be initialized to NULL_RTX by the caller before calling this routine .


<s> bool SystemZRegisterInfo :: getRegAllocationHints ( unsigned VirtReg , ArrayRef < MCPhysReg > Order , SmallVectorImpl < MCPhysReg > & Hints , const MachineFunction & MF , const VirtRegMap * VRM , const LiveRegMatrix * Matrix ) const { const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; bool BaseImplRetVal = TargetRegisterInfo :: getRegAllocationHints ( VirtReg , Order , Hints , MF , VRM , Matrix ) ; if ( MRI -> getRegClass ( VirtReg ) == & SystemZ :: GRX32BitRegClass ) { SmallVector < unsigned , 8 > Worklist ; SmallSet < unsigned , 4 > DoneRegs ; Worklist . push_back ( VirtReg ) ; while ( Worklist . size ( ) ) { unsigned Reg = Worklist . pop_back_val ( ) ; if ( ! DoneRegs . insert ( Reg ) . second ) continue ; for ( auto & Use : MRI -> use_instructions ( Reg ) ) if ( Use . getOpcode ( ) == SystemZ :: LOCRMux ) { MachineOperand & TrueMO = Use . getOperand ( 1 ) ; MachineOperand & FalseMO = Use . getOperand ( 2 ) ; const TargetRegisterClass * RC = TRI -> getCommonSubClass ( getRC32 ( FalseMO , VRM , MRI ) , getRC32 ( TrueMO , VRM , MRI ) ) ; if ( RC && RC != & SystemZ :: GRX32BitRegClass ) { SmallSet < unsigned , 4 > CopyHints ; CopyHints . insert ( Hints . begin ( ) , Hints . end ( ) ) ; Hints . clear ( ) ; for ( MCPhysReg Reg : Order ) if ( CopyHints . count ( Reg ) && RC -> contains ( Reg ) && ! MRI -> isReserved ( Reg ) ) Hints . push_back ( Reg ) ; for ( MCPhysReg Reg : Order ) if ( ! CopyHints . count ( Reg ) && RC -> contains ( Reg ) && ! MRI -> isReserved ( Reg ) ) Hints . push_back ( Reg ) ; return true ; } unsigned OtherReg = ( TrueMO . getReg ( ) == Reg ? FalseMO . getReg ( ) : TrueMO . getReg ( ) ) ; if ( MRI -> getRegClass ( OtherReg ) == & SystemZ :: GRX32BitRegClass ) Worklist . push_back ( OtherReg ) ; } } } return BaseImplRetVal ; } </s>

Get a list of 'hint ' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg .


<s>
const
MCPhysReg
*
X86RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
const
X86Subtarget
&
Subtarget
=
MF
->
getSubtarget
<
X86Subtarget
>
(
)
;
bool
HasAVX
=
Subtarget
.
hasAVX
(
)
;
bool
HasAVX512
=
Subtarget
.
hasAVX512
(
)
;
bool
CallsEHReturn
=
MF
->
getMMI
(
)
.
callsEHReturn
(
)
;
assert
(
MF
&&
"MachineFunction required"
)
;
switch
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
)
{
case
CallingConv
::
GHC
:
case
CallingConv
::
HiPE
:
return
CSR_NoRegs_SaveList
;
case
CallingConv
::
AnyReg
:
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
return
CSR_64_AllRegs_SaveList
;
case
CallingConv
::
PreserveMost
:
return
CSR_64_RT_MostRegs_SaveList
;
case
CallingConv
::
PreserveAll
:
if
(
HasAVX
)
return
CSR_64_RT_AllRegs_AVX_SaveList
;
return
CSR_64_RT_AllRegs_SaveList
;
case
CallingConv
::
Intel_OCL_BI
:
{
if
(
HasAVX512
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX512
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX_SaveList
;
if
(
HasAVX
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX_SaveList
;
if
(
!
HasAVX
&&
!
IsWin64
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_SaveList
;
break
;
}
case
CallingConv
::
HHVM
:
return
CSR_64_HHVM_SaveList
;
case
CallingConv
::
Cold
:
if
(
Is64Bit
)
return
CSR_64_MostRegs_SaveList
;
break
;
case
CallingConv
::
X86_64_Win64
:
return
CSR_Win64_SaveList
;
case
CallingConv
::
X86_64_SysV
:
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
default
:
break
;
}
if
(
Is64Bit
)
{
if
(
IsWin64
)
return
CSR_Win64_SaveList
;
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
}
if
(
CallsEHReturn
)
return
CSR_32EHRet_SaveList
;
return
CSR_32_SaveList
;
}
</s>


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> static tree arm_extract_valist_ptr ( tree valist ) { if ( TREE_TYPE ( valist ) == error_mark_node ) return error_mark_node ; if ( TARGET_AAPCS_BASED ) { tree ap_field = TYPE_FIELDS ( TREE_TYPE ( valist ) ) ; valist = build3 ( COMPONENT_REF , TREE_TYPE ( ap_field ) , valist , ap_field , NULL_TREE ) ; } return valist ; } </s>

Return an expression of type `` void * '' pointing to the next available argument in a variable-argument list . VALIST is the user-level va_list object , of type __builtin_va_list .


<s> static bool s390_function_ok_for_sibcall ( tree decl , tree exp ) { if ( TARGET_TPF_PROFILING ) return false ; if ( ! TARGET_64BIT && flag_pic && decl && ! targetm . binds_local_p ( decl ) ) return false ; if ( TARGET_INDIRECT_BRANCH_NOBP_CALL && ! TARGET_CPU_Z10 && ! decl ) return false ; return ! s390_call_saved_register_used ( exp ) ; } </s>

Return true if the given call expression can be turned into a sibling call . DECL holds the declaration of the function to be called whereas EXP is the call expression itself .


<s> bool MOSInstrInfo :: isReallyTriviallyReMaterializable ( const MachineInstr & MI , AAResults * AA ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case MOS :: LDImm16 : return true ; } } </s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s>
SDValue
MandarinTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
DL
,
SelectionDAG
&
DAG
)
const
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
DAG
.
getTarget
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_Mandarin
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
MDISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
&
RetOps
[
0
]
,
RetOps
.
size
(
)
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> unsigned PPCFastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( DL , C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return PPCMaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return PPCMaterializeGV ( GV , VT ) ; else if ( isa < ConstantInt > ( C ) ) return PPCMaterializeInt ( C , VT , VT != MVT :: i1 ) ; return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s> static const char * s390_mangle_type ( const_tree type ) { if ( TYPE_MAIN_VARIANT ( type ) == long_double_type_node && TARGET_LONG_DOUBLE_128 ) return "g" ; return NULL ; } </s>


<s> const MCSection * getSectionForConstant ( SectionKind Kind ) const override { return ReadOnlySection ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> bool CSKYAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { MCP = MF . getConstantPool ( ) ; Subtarget = & MF . getSubtarget < CSKYSubtarget > ( ) ; return AsmPrinter :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> const MCPhysReg * Cpu0RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_O32_SaveList ; } </s>


<s> bool SIInstrInfo :: mayReadEXEC ( const MachineRegisterInfo & MRI , const MachineInstr & MI ) const { if ( MI . isMetaInstruction ( ) ) return false ; if ( MI . isCopyLike ( ) ) { if ( ! RI . isSGPRReg ( MRI , MI . getOperand ( 0 ) . getReg ( ) ) ) return true ; return MI . readsRegister ( AMDGPU :: EXEC , & RI ) ; } if ( ! isTargetSpecificOpcode ( MI . getOpcode ( ) ) ) return true ; return ! isSALU ( MI ) || MI . readsRegister ( AMDGPU :: EXEC , & RI ) ; } </s>

Returns true if the instruction could potentially depend on the value of exec .


<s> bool SIInsertWaits :: runOnMachineFunction ( MachineFunction & MF ) { bool Changes = false ; MRI = & MF . getRegInfo ( ) ; WaitedOn = ZeroCounts ; LastIssued = ZeroCounts ; memset ( & UsedRegs , 0 , sizeof ( UsedRegs ) ) ; memset ( & DefinedRegs , 0 , sizeof ( DefinedRegs ) ) ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { Changes |= insertWait ( MBB , I , handleOperands ( * I ) ) ; pushInstruction ( * I ) ; } Changes |= insertWait ( MBB , MBB . getFirstTerminator ( ) , LastIssued ) ; } return Changes ; } </s>


<s> void riscv_atomic_assign_expand_fenv ( tree * hold , tree * clear , tree * update ) { if ( ! TARGET_HARD_FLOAT ) return ; tree frflags = GET_BUILTIN_DECL ( CODE_FOR_riscv_frflags ) ; tree fsflags = GET_BUILTIN_DECL ( CODE_FOR_riscv_fsflags ) ; tree old_flags = create_tmp_var_raw ( RISCV_ATYPE_USI ) ; * hold = build4 ( TARGET_EXPR , RISCV_ATYPE_USI , old_flags , build_call_expr ( frflags , 0 ) , NULL_TREE , NULL_TREE ) ; * clear = build_call_expr ( fsflags , 1 , old_flags ) ; * update = NULL_TREE ; } </s>


<s> bool Cpu0FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void MipsAsmPrinter :: emitFrameDirective ( MachineFunction & MF ) { const TargetRegisterInfo & RI = * TM . getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ; O << "\t.frame\t" << '$' << LowercaseString ( RI . get ( stackReg ) . AsmName ) << ',' << stackSize << ',' << '$' << LowercaseString ( RI . get ( returnReg ) . AsmName ) << '\n' ; } </s>


Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calling convention CallConv .


<s> void MipsSEFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; const MipsSEInstrInfo & TII = * static_cast < const MipsSEInstrInfo * > ( STI . getInstrInfo ( ) ) ; const MipsRegisterInfo & RegInfo = * static_cast < const MipsRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; unsigned SP = ABI . GetStackPtr ( ) ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned ZERO = ABI . GetNullPtr ( ) ; unsigned ADDu = ABI . GetPtrAdduOp ( ) ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( ADDu ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( MipsFI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = ABI . ArePtrs64bit ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = 0 ; J < 4 ; ++ J ) { TII . loadRegFromStackSlot ( MBB , I , ABI . GetEhDataReg ( J ) , MipsFI -> getEhDataRegFI ( J ) , RC , & RegInfo ) ; } } uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize , MBB , MBBI ) ; } </s>

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips 0 Mips Mips::GPR64RegClass Mips::GPR32RegClass 0 0 4 Mips


<s> static bool isEqual ( const MemOpKey & LHS , const MemOpKey & RHS ) { if ( RHS . Disp == PtrInfo :: getEmptyKey ( ) ) return LHS . Disp == PtrInfo :: getEmptyKey ( ) ; if ( RHS . Disp == PtrInfo :: getTombstoneKey ( ) ) return LHS . Disp == PtrInfo :: getTombstoneKey ( ) ; return LHS == RHS ; } </s>

isEqual - Compares two trees for structural equality and returns true if they are equal .


<s> static void ix86_sched_init_global ( FILE * , int , int ) { switch ( ix86_tune ) { case PROCESSOR_CORE2 : case PROCESSOR_NEHALEM : case PROCESSOR_SANDYBRIDGE : case PROCESSOR_HASWELL : case PROCESSOR_TREMONT : case PROCESSOR_ALDERLAKE : case PROCESSOR_GENERIC : if ( reload_completed ) { ix86_core2i7_init_hooks ( ) ; break ; } default : targetm . sched . dfa_post_advance_cycle = NULL ; targetm . sched . first_cycle_multipass_init = NULL ; targetm . sched . first_cycle_multipass_begin = NULL ; targetm . sched . first_cycle_multipass_issue = NULL ; targetm . sched . first_cycle_multipass_backtrack = NULL ; targetm . sched . first_cycle_multipass_end = NULL ; targetm . sched . first_cycle_multipass_fini = NULL ; break ; } } </s>


<s> static bool isIndirectCall ( const SDValue & Callee , SelectionDAG & DAG , const PPCSubtarget & Subtarget , bool isPatchPoint ) { if ( isPatchPoint ) return false ; if ( isFunctionGlobalAddress ( Callee ) || dyn_cast < ExternalSymbolSDNode > ( Callee ) ) return false ; if ( ! Subtarget . usesFunctionDescriptors ( ) && ! Subtarget . isELFv2ABI ( ) && isBLACompatibleAddress ( Callee , DAG ) ) return false ; return true ; } </s>

Return true if the callsite is an indirect call .


"unexpected return calling convention register assignment"

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Patmos Single-Path Prepare"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static bool s390_cannot_copy_insn_p ( rtx_insn * insn ) { rtx label = s390_execute_label ( insn ) ; return label && label != const0_rtx ; } </s>

Indicate that INSN can not be duplicated . This is the case for execute insns that carry a unique label .


"Warning: Illegal instruction detected: "

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


"Pseudo opcode found in EmitInstruction()"


"Hexagon DAG->DAG Pattern Instruction Selection"


<s> static inline unsigned ptr_regno_for_savres ( int sel ) { if ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) return ( sel & SAVRES_REG ) == SAVRES_FPR || ( sel & SAVRES_LR ) ? 1 : 12 ; return DEFAULT_ABI == ABI_DARWIN && ( sel & SAVRES_REG ) == SAVRES_FPR ? 1 : 11 ; } </s>

Return the register number used as a pointer by out-of-line save/restore functions .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
Kind
==
k_Reg
&&
"Invalid access!"
)
;
return
Reg
;
}
</s>

Returns the register associated with this edge .


<s> bool ARMTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( Subtarget -> isThumb1Only ( ) ) return false ; const bool restrict_addressing_modes_for_nacl = Subtarget -> isTargetNaCl ( ) && isa < MemSDNode > ( N ) ; if ( restrict_addressing_modes_for_nacl ) { return false ; } EVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == ISD :: SEXTLOAD ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; } else return false ; bool isInc ; bool isLegal = false ; if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = getARMIndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( ! isLegal ) return false ; AM = isInc ? ISD :: PRE_INC : ISD :: PRE_DEC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .

ARM ARM ISD::MemIndexedMode ISD::SEXTLOAD ARM ISD::PRE_INC ISD::PRE_DEC


<s> static void iq2000_setup_incoming_varargs ( cumulative_args_t cum_v , machine_mode mode ATTRIBUTE_UNUSED , tree type ATTRIBUTE_UNUSED , int * pretend_size , int no_rtl ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; unsigned int iq2000_off = ! cum -> last_arg_fp ; unsigned int iq2000_fp_off = cum -> last_arg_fp ; if ( ( cum -> arg_words < MAX_ARGS_IN_REGISTERS - iq2000_off ) ) { int iq2000_save_gp_regs = MAX_ARGS_IN_REGISTERS - cum -> arg_words - iq2000_off ; int iq2000_save_fp_regs = ( MAX_ARGS_IN_REGISTERS - cum -> fp_arg_words - iq2000_fp_off ) ; if ( iq2000_save_gp_regs < 0 ) iq2000_save_gp_regs = 0 ; if ( iq2000_save_fp_regs < 0 ) iq2000_save_fp_regs = 0 ; * pretend_size = ( ( iq2000_save_gp_regs * UNITS_PER_WORD ) + ( iq2000_save_fp_regs * UNITS_PER_FPREG ) ) ; if ( ! ( no_rtl ) ) { if ( cum -> arg_words < MAX_ARGS_IN_REGISTERS - iq2000_off ) { rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , - ( iq2000_save_gp_regs * UNITS_PER_WORD ) ) ; mem = gen_rtx_MEM ( BLKmode , ptr ) ; move_block_from_reg ( cum -> arg_words + GP_ARG_FIRST + iq2000_off , mem , iq2000_save_gp_regs ) ; } } } } </s>

Worker function for TARGET_SETUP_INCOMING_VARARGS .


<s> bool rvexInstrInfo :: isSchedulingBoundary ( const MachineInstr * MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( MI -> isDebugValue ( ) ) return false ; if ( MI -> getDesc ( ) . isTerminator ( ) || MI -> isLabel ( ) || MI -> isInlineAsm ( ) ) { return true ; } return false ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> bool xtensa_b4constu ( HOST_WIDE_INT v ) { switch ( v ) { case 32768 : case 65536 : case 2 : case 3 : case 4 : case 5 : case 6 : case 7 : case 8 : case 10 : case 12 : case 16 : case 32 : case 64 : case 128 : case 256 : return true ; } return false ; } </s>

Functions to test Xtensa immediate operand validity .


<s> static bool riscv_in_small_data_p ( const_tree x ) { if ( TREE_CODE ( x ) == STRING_CST || TREE_CODE ( x ) == FUNCTION_DECL ) return false ; if ( TREE_CODE ( x ) == VAR_DECL && DECL_SECTION_NAME ( x ) ) { const char * sec = DECL_SECTION_NAME ( x ) ; return strcmp ( sec , ".sdata" ) == 0 || strcmp ( sec , ".sbss" ) == 0 ; } return riscv_size_ok_for_small_data_p ( int_size_in_bytes ( TREE_TYPE ( x ) ) ) ; } </s>

Return true if EXP should be placed in the small data section .


<s> const AArch64MCExpr * AArch64MCExpr :: Create ( const MCExpr * Expr , VariantKind Kind , MCContext & Ctx ) { return new ( Ctx ) AArch64MCExpr ( Expr , Kind ) ; } </s>

Construct a unary instruction , given the opcode and an operand .


<s> bool X86DAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 , Op2 , Op3 , Op4 ; switch ( ConstraintCode ) { case 'o' : case 'v' : default : return true ; case 'm' : if ( ! SelectAddr ( Op , Op , Op0 , Op1 , Op2 , Op3 , Op4 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; OutOps . push_back ( Op2 ) ; OutOps . push_back ( Op3 ) ; OutOps . push_back ( Op4 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> bool SIInstrInfo :: isSafeToMoveRegClassDefs ( const TargetRegisterClass * RC ) const { return RC != & AMDGPU :: EXECRegRegClass ; } </s>

isSafeToMoveRegClassDefs - Return true if it 's safe to move a machine instruction that defines the specified register class .


<s> bool XtensaRegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return false ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> bool RISCVELFTargetObjectFile :: isConstantInSmallSection ( const DataLayout & DL , const Constant * CN ) const { return isInSmallSection ( DL . getTypeAllocSize ( CN -> getType ( ) ) ) ; } </s>

Return true if this constant should be placed into small data section .


Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> bool HexagonEarlyIfConversion :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; auto & ST = MF . getSubtarget < HexagonSubtarget > ( ) ; HII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; MFN = & MF ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MBPI = EnableHexagonBP ? & getAnalysis < MachineBranchProbabilityInfo > ( ) : nullptr ; Deleted . clear ( ) ; bool Changed = false ; for ( MachineLoop * L : * MLI ) Changed |= visitLoop ( L ) ; Changed |= visitLoop ( nullptr ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Kudeyar Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> BitVector KudeyarRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; Reserved . set ( Kudeyar :: SP ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( Kudeyar :: FP ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool AMDGPUCallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , unsigned VReg ) const { MIRBuilder . buildInstr ( AMDGPU :: S_ENDPGM ) ; return true ; } </s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


"switch %<-mcpu=%s%> conflicts with %<-march=%s%> switch"

"assembler does not support %<-mabi=ilp32%>"

"return address signing is only supported for %<-mabi=lp64%>"


<s> unsigned X86InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( isFrameLoadOpcode ( MI -> getOpcode ( ) ) ) if ( MI -> getOperand ( 0 ) . getSubReg ( ) == 0 && isFrameOperand ( MI , 1 , FrameIndex ) ) return MI -> getOperand ( 0 ) . getReg ( ) ; return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> int rs6000_emit_vector_cond_expr ( rtx dest , rtx op_true , rtx op_false , rtx cond , rtx cc_op0 , rtx cc_op1 ) { machine_mode dest_mode = GET_MODE ( dest ) ; machine_mode mask_mode = GET_MODE ( cc_op0 ) ; enum rtx_code rcode = GET_CODE ( cond ) ; machine_mode cc_mode = CCmode ; rtx mask ; rtx cond2 ; rtx tmp ; bool invert_move = false ; if ( VECTOR_UNIT_NONE_P ( dest_mode ) ) return 0 ; gcc_assert ( GET_MODE_SIZE ( dest_mode ) == GET_MODE_SIZE ( mask_mode ) && GET_MODE_NUNITS ( dest_mode ) == GET_MODE_NUNITS ( mask_mode ) ) ; switch ( rcode ) { case NE : case UNLE : case UNLT : case UNGE : case UNGT : invert_move = true ; rcode = reverse_condition_maybe_unordered ( rcode ) ; if ( rcode == UNKNOWN ) return 0 ; break ; case GTU : case GEU : case LTU : case LEU : cc_mode = CCUNSmode ; break ; default : break ; } mask = rs6000_emit_vector_compare ( rcode , cc_op0 , cc_op1 , mask_mode ) ; if ( ! mask ) return 0 ; if ( invert_move ) { tmp = op_true ; op_true = op_false ; op_false = tmp ; } cond2 = gen_rtx_fmt_ee ( NE , cc_mode , gen_lowpart ( dest_mode , mask ) , CONST0_RTX ( dest_mode ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , gen_rtx_IF_THEN_ELSE ( dest_mode , cond2 , op_true , op_false ) ) ) ; return 1 ; } </s>

Emit vector conditional expression . DEST is destination . OP1 and OP2 are two VEC_COND_EXPR operands . CC_OP0 and CC_OP1 are the two operands for the relation operation COND .


<s> bool fixupNeedsRelaxationAdvanced ( const MCFixup & Fixup , bool Resolved , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { MCInst const & MCB = DF -> getInst ( ) ; assert ( HexagonMCInstrInfo :: isBundle ( MCB ) ) ; * RelaxTarget = nullptr ; MCInst & MCI = const_cast < MCInst & > ( HexagonMCInstrInfo :: instruction ( MCB , Fixup . getOffset ( ) / HEXAGON_INSTR_SIZE ) ) ; bool Relaxable = isInstRelaxable ( MCI ) ; if ( Relaxable == false ) return false ; if ( ! Resolved ) { switch ( ( unsigned ) Fixup . getKind ( ) ) { case fixup_Hexagon_B22_PCREL : default : return false ; break ; case fixup_Hexagon_B13_PCREL : case fixup_Hexagon_B15_PCREL : case fixup_Hexagon_B9_PCREL : case fixup_Hexagon_B7_PCREL : { if ( HexagonMCInstrInfo :: bundleSize ( MCB ) < HEXAGON_PACKET_SIZE ) { ++ relaxedCnt ; * RelaxTarget = & MCI ; setExtender ( Layout . getAssembler ( ) . getContext ( ) ) ; return true ; } else { return false ; } break ; } } } MCFixupKind Kind = Fixup . getKind ( ) ; int64_t sValue = Value ; int64_t maxValue ; switch ( ( unsigned ) Kind ) { case fixup_Hexagon_B7_PCREL : maxValue = 1 << 8 ; break ; case fixup_Hexagon_B9_PCREL : maxValue = 1 << 10 ; break ; case fixup_Hexagon_B15_PCREL : maxValue = 1 << 16 ; break ; case fixup_Hexagon_B22_PCREL : maxValue = 1 << 23 ; break ; default : maxValue = INT64_MAX ; break ; } bool isFarAway = - maxValue > sValue || sValue > maxValue - 1 ; if ( isFarAway ) { if ( HexagonMCInstrInfo :: bundleSize ( MCB ) < HEXAGON_PACKET_SIZE ) { ++ relaxedCnt ; * RelaxTarget = & MCI ; setExtender ( Layout . getAssembler ( ) . getContext ( ) ) ; return true ; } } return false ; } </s>

Target specific predicate for whether a given fixup requires the associated instruction to be relaxed .


<s> void GCNPassConfig :: addMachineSSAOptimization ( ) { TargetPassConfig :: addMachineSSAOptimization ( ) ; addPass ( & SIFoldOperandsID ) ; addPass ( & DeadMachineInstructionElimID ) ; addPass ( & SILoadStoreOptimizerID ) ; if ( EnableSDWAPeephole ) { addPass ( & SIPeepholeSDWAID ) ; addPass ( & MachineLICMID ) ; addPass ( & MachineCSEID ) ; addPass ( & SIFoldOperandsID ) ; addPass ( & DeadMachineInstructionElimID ) ; } addPass ( createSIShrinkInstructionsPass ( ) ) ; } </s>

Methods with trivial inline returns are convenient points in the common codegen pass pipeline where targets may insert passes .


"ARM hazards don't support scoreboard lookahead"

getHazardType - Return the hazard type of emitting this node .


"Can only insert epilog into returning blocks"


<s> bool MSP430PassConfig :: addPreEmitPass ( ) { PM -> add ( createMSP430BranchSelectionPass ( ) ) ; return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool SIMemoryLegalizer :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; SIMemOpAccess MOA ( MF ) ; CC = SICacheControl :: create ( MF . getSubtarget < GCNSubtarget > ( ) ) ; for ( auto & MBB : MF ) { for ( auto MI = MBB . begin ( ) ; MI != MBB . end ( ) ; ++ MI ) { if ( ! ( MI -> getDesc ( ) . TSFlags & SIInstrFlags :: maybeAtomic ) ) continue ; if ( const auto & MOI = MOA . getLoadInfo ( MI ) ) Changed |= expandLoad ( MOI . getValue ( ) , MI ) ; else if ( const auto & MOI = MOA . getStoreInfo ( MI ) ) Changed |= expandStore ( MOI . getValue ( ) , MI ) ; else if ( const auto & MOI = MOA . getAtomicFenceInfo ( MI ) ) Changed |= expandAtomicFence ( MOI . getValue ( ) , MI ) ; else if ( const auto & MOI = MOA . getAtomicCmpxchgOrRmwInfo ( MI ) ) Changed |= expandAtomicCmpxchgOrRmw ( MOI . getValue ( ) , MI ) ; } } Changed |= removeAtomicPseudoMIs ( ) ; return Changed ; } </s>

AMDGPU SI SI SI SIInstrFlags::maybeAtomic


<s> NVPTXSubtarget & NVPTXSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { TargetName = std :: string ( CPU . empty ( ) ? "sm_20" : CPU ) ; ParseSubtargetFeatures ( TargetName , FS ) ; if ( PTXVersion == 0 ) { PTXVersion = 32 ; } return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s>
bool
ARCFrameLowering
::
spillCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
DEBUG
(
dbgs
(
)
<<
"Spill callee saved registers: "
<<
MBB
.
getParent
(
)
->
getFunction
(
)
->
getName
(
)
<<
"\n"
)
;
unsigned
Last
=
determineLastCalleeSave
(
CSI
)
;
if
(
UseSaveRestoreFunclet
&&
Last
>
ARC
::
R14
)
{
return
true
;
}
return
false
;
}
</s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .

ARC
ARC
"Spill callee saved registers: "
"\n"
ARC::R14


<s>
enum
calling_abi
ix86_function_type_abi
(
const_tree
fntype
)
{
enum
calling_abi
abi
=
ix86_abi
;
if
(
fntype
==
NULL_TREE
||
TYPE_ATTRIBUTES
(
fntype
)
==
NULL_TREE
)
return
abi
;
if
(
abi
==
SYSV_ABI
&&
lookup_attribute
(
"ms_abi"
,
TYPE_ATTRIBUTES
(
fntype
)
)
)
{
static
int
warned
;
if
(
TARGET_X32
&&
!
warned
)
{
error
(
"X32 does not support ms_abi attribute"
)
;
warned
=
1
;
}
abi
=
MS_ABI
;
}
else
if
(
abi
==
MS_ABI
&&
lookup_attribute
(
"sysv_abi"
,
TYPE_ATTRIBUTES
(
fntype
)
)
)
abi
=
SYSV_ABI
;
return
abi
;
}
</s>

Returns value SYSV_ABI , MS_ABI dependent on fntype , specifying the call abi used .


<s> DecodeStatus TL45Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & OS , raw_ostream & CS ) const { uint32_t Insn ; DecodeStatus Result ; if ( Bytes . size ( ) < 4 ) { Size = 0 ; return MCDisassembler :: Fail ; } Insn = support :: endian :: read32be ( Bytes . data ( ) ) ; Result = decodeInstruction ( DecoderTable32 , MI , Insn , Address , this , STI ) ; Size = 4 ; return Result ; } </s>

Returns the disassembly of a single instruction .


<s> static unsigned int arc_autovectorize_vector_sizes ( void ) { return TARGET_PLUS_QMACW ? ( 8 | 4 ) : 0 ; } </s>


<s>
bool
SIInstrInfo
::
isInlineConstant
(
const
MachineOperand
&
MO
,
uint8_t
OperandType
)
const
{
if
(
!
MO
.
isImm
(
)
||
OperandType
<
AMDGPU
::
OPERAND_SRC_FIRST
||
OperandType
>
AMDGPU
::
OPERAND_SRC_LAST
)
return
false
;
int64_t
Imm
=
MO
.
getImm
(
)
;
switch
(
OperandType
)
{
case
AMDGPU
::
OPERAND_REG_IMM_INT32
:
case
AMDGPU
::
OPERAND_REG_IMM_FP32
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_INT32
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_FP32
:
{
int32_t
Trunc
=
static_cast
<
int32_t
>
(
Imm
)
;
return
Trunc
==
Imm
&&
AMDGPU
::
isInlinableLiteral32
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
case
AMDGPU
::
OPERAND_REG_IMM_INT64
:
case
AMDGPU
::
OPERAND_REG_IMM_FP64
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_INT64
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_FP64
:
return
AMDGPU
::
isInlinableLiteral64
(
MO
.
getImm
(
)
,
ST
.
hasInv2PiInlineImm
(
)
)
;
case
AMDGPU
::
OPERAND_REG_IMM_INT16
:
case
AMDGPU
::
OPERAND_REG_IMM_FP16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_INT16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_FP16
:
{
if
(
isInt
<
16
>
(
Imm
)
||
isUInt
<
16
>
(
Imm
)
)
{
int16_t
Trunc
=
static_cast
<
int16_t
>
(
Imm
)
;
return
ST
.
has16BitInsts
(
)
&&
AMDGPU
::
isInlinableLiteral16
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
return
false
;
}
case
AMDGPU
::
OPERAND_REG_INLINE_C_V2INT16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_V2FP16
:
{
if
(
isUInt
<
16
>
(
Imm
)
)
{
int16_t
Trunc
=
static_cast
<
int16_t
>
(
Imm
)
;
return
ST
.
has16BitInsts
(
)
&&
AMDGPU
::
isInlinableLiteral16
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
if
(
!
(
Imm
&
0xffff
)
)
{
return
ST
.
has16BitInsts
(
)
&&
AMDGPU
::
isInlinableLiteral16
(
Imm
>>
16
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
uint32_t
Trunc
=
static_cast
<
uint32_t
>
(
Imm
)
;
return
AMDGPU
::
isInlinableLiteralV216
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
default
:
llvm_unreachable
(
"invalid bitwidth"
)
;
}
}
</s>

returns true if the operand OpIdx in MI is a valid inline immediate .


Create the va_list data type . We keep 3 pointers , and two offsets . Two pointers are to the overflow area , which starts at the CFA . One of these is constant , for addressing into the GPR save area below it . The other is advanced up the stack through the overflow region . The third pointer is to the GPR save area . Since the FPR save area is just below it , we can address FPR slots off this pointer . We also keep two one-byte offsets , which are to be subtracted from the constant pointers to yield addresses in the GPR and FPR save areas . These are downcounted as float or non-float arguments are used , and when they get to zero , the argument must be obtained from the overflow region . If TARGET_SOFT_FLOAT or TARGET_SINGLE_FLOAT , then no FPR save area exists , and a single pointer is enough . It 's started at the GPR save area , and is advanced , period . Note that the GPR save area is not constant size , due to optimization in the prologue . Hence , we ca n't use a design with two pointers and two offsets , although we could have designed this with two pointers and three offsets .


<s> static rtx rs6000_internal_arg_pointer ( void ) { if ( flag_split_stack && ( lookup_attribute ( "no_split_stack" , DECL_ATTRIBUTES ( cfun -> decl ) ) == NULL ) ) { if ( cfun -> machine -> split_stack_arg_pointer == NULL_RTX ) { rtx pat ; cfun -> machine -> split_stack_arg_pointer = gen_reg_rtx ( Pmode ) ; REG_POINTER ( cfun -> machine -> split_stack_arg_pointer ) = 1 ; pat = gen_rtx_SET ( cfun -> machine -> split_stack_arg_pointer , gen_rtx_REG ( Pmode , 12 ) ) ; push_topmost_sequence ( ) ; emit_insn_after ( pat , get_insns ( ) ) ; pop_topmost_sequence ( ) ; } return plus_constant ( Pmode , cfun -> machine -> split_stack_arg_pointer , FIRST_PARM_OFFSET ( current_function_decl ) ) ; } return virtual_incoming_args_rtx ; } </s>

Return the internal arg pointer used for function incoming arguments . When -fsplit-stack , the arg pointer is r12 so we need to copy it to a pseudo in order for it to be preserved over calls and suchlike . We 'd really like to use a pseudo here for the internal arg pointer but data-flow analysis is not prepared to accept pseudos as live at the beginning of a function .


<s> void BTFDebug :: emitCommonHeader ( ) { OS . AddComment ( "0x" + Twine :: utohexstr ( BTF :: MAGIC ) ) ; OS . emitIntValue ( BTF :: MAGIC , 2 ) ; OS . emitInt8 ( BTF :: VERSION ) ; OS . emitInt8 ( 0 ) ; } </s>

Emit the common part of the header for this unit .


<s> bool AArch64PassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnablePromoteConstant ) addPass ( createAArch64PromoteConstantPass ( ) ) ; if ( ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE ) { bool OnlyOptimizeForSize = ( TM -> getOptLevel ( ) < CodeGenOpt :: Aggressive ) && ( EnableGlobalMerge == cl :: BOU_UNSET ) ; addPass ( createGlobalMergePass ( TM , 4095 , OnlyOptimizeForSize ) ) ; } return false ; } </s>


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
auto
RegName
=
[
]
(
unsigned
Reg
)
{
if
(
Reg
)
return
RISCVInstPrinter
::
getRegisterName
(
Reg
)
;
else
return
"noreg"
;
}
;
switch
(
Kind
)
{
case
KindTy
::
Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
KindTy
::
Register
:
OS
<<
"<register "
<<
RegName
(
getReg
(
)
)
<<
">"
;
break
;
case
KindTy
::
Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
case
KindTy
::
SystemRegister
:
OS
<<
"<sysreg: "
<<
getSysReg
(
)
<<
'>'
;
break
;
case
KindTy
::
VType
:
OS
<<
"<vtype: "
;
RISCVVType
::
printVType
(
getVType
(
)
,
OS
)
;
OS
<<
'>'
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

RISCV
RISCV
"noreg"
"<register "
">"
"'"
"'"
"<sysreg: "
"<vtype: "
RISCV


<s> bool XtensaAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> unsigned M68kOperand :: getReg ( ) const { assert ( isReg ( ) ) ; return MemOp . OuterReg ; } </s>

Returns the register associated with this edge .


<s> int PPCInstrInfo :: getOperandLatency ( const InstrItineraryData * ItinData , const MachineInstr & DefMI , unsigned DefIdx , const MachineInstr & UseMI , unsigned UseIdx ) const { int Latency = PPCGenInstrInfo :: getOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ; if ( ! DefMI . getParent ( ) ) return Latency ; const MachineOperand & DefMO = DefMI . getOperand ( DefIdx ) ; Register Reg = DefMO . getReg ( ) ; bool IsRegCR ; if ( Register :: isVirtualRegister ( Reg ) ) { const MachineRegisterInfo * MRI = & DefMI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; IsRegCR = MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & PPC :: CRRCRegClass ) || MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & PPC :: CRBITRCRegClass ) ; } else { IsRegCR = PPC :: CRRCRegClass . contains ( Reg ) || PPC :: CRBITRCRegClass . contains ( Reg ) ; } if ( UseMI . isBranch ( ) && IsRegCR ) { if ( Latency < 0 ) Latency = getInstrLatency ( ItinData , DefMI ) ; unsigned Directive = Subtarget . getCPUDirective ( ) ; switch ( Directive ) { default : break ; case PPC :: DIR_7400 : case PPC :: DIR_750 : case PPC :: DIR_970 : case PPC :: DIR_E5500 : case PPC :: DIR_PWR4 : case PPC :: DIR_PWR5 : case PPC :: DIR_PWR5X : case PPC :: DIR_PWR6 : case PPC :: DIR_PWR6X : case PPC :: DIR_PWR7 : case PPC :: DIR_PWR8 : Latency += 2 ; break ; } } return Latency ; } </s>

Compute and return the use operand latency of a given pair of def and use .


<s> TargetPassConfig * HSAILTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new HSAILPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> bool X86TargetLowering :: isSafeMemOpType ( MVT VT ) const { if ( VT == MVT :: f32 ) return Subtarget . hasSSE1 ( ) ; if ( VT == MVT :: f64 ) return Subtarget . hasSSE2 ( ) ; return true ; } </s>

Returns true if it 's safe to use load / store of the specified type to expand memcpy / memset inline .


<s> void function_builder :: append_base_name ( const char * name ) { append_name ( "__riscv_" ) ; append_name ( name ) ; } </s>


<s>
static
rtx
m32c_legitimize_address
(
rtx
x
,
rtx
oldx
ATTRIBUTE_UNUSED
,
machine_mode
mode
)
{
fprintf
(
stderr
,
"m32c_legitimize_address for mode %s\n"
,
mode_name
[
mode
]
)
;
debug_rtx
(
x
)
;
fprintf
(
stderr
,
"\n"
)
;
if
(
GET_CODE
(
x
)
==
PLUS
&&
GET_CODE
(
XEXP
(
x
,
0
)
)
==
REG
&&
REGNO
(
XEXP
(
x
,
0
)
)
==
FB_REGNO
&&
GET_CODE
(
XEXP
(
x
,
1
)
)
==
CONST_INT
&&
(
INTVAL
(
XEXP
(
x
,
1
)
)
<
128
||
INTVAL
(
XEXP
(
x
,
1
)
)
>
(
128
GET_MODE_SIZE
(
mode
)
)
)
)
{
rtx
temp
=
gen_reg_rtx
(
Pmode
)
;
x
=
copy_rtx
(
x
)
;
emit_insn
(
gen_rtx_SET
(
temp
,
XEXP
(
x
,
0
)
)
)
;
XEXP
(
x
,
0
)
=
temp
;
}
return
x
;
}
</s>

Implements LEGITIMIZE_ADDRESS . The only address we really have to worry about is frame base offsets , as $ fb has a limited displacement range . We deal with this by attempting to reload $ fb itself into an address register ; that seems to result in the best code .


<s> inline static const char * getTagName ( TAGS tag ) { switch ( tag ) { default : return "" ; case PREFIX_SYMBOL : return "@" ; case AUTOS_LABEL : return ".auto." ; case FRAME_LABEL : return ".frame." ; case TEMPS_LABEL : return ".temp." ; case ARGS_LABEL : return ".args." ; case RET_LABEL : return ".ret." ; case LIBCALL : return ".lib." ; case FRAME_SECTION : return ".frame_section." ; case AUTOS_SECTION : return ".autos_section." ; case CODE_SECTION : return ".code_section." ; } } </s>

Return the tag of this operand bundle as a string .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> rtx expand_builtin ( unsigned int code , tree exp , rtx target ) { registered_function & rfn = * ( * registered_functions ) [ code ] ; return function_expander ( rfn . instance , rfn . decl , exp , target ) . expand ( ) ; } </s>

Expand a call to the RVV function with subcode CODE . EXP is the call expression and TARGET is the preferred location for the result . Return the value of the lhs .


<s> void rs6000_expand_atomic_exchange ( rtx operands [ ] ) { rtx retval , mem , val , cond ; machine_mode mode ; enum memmodel model ; rtx label , x , mask , shift ; retval = operands [ 0 ] ; mem = operands [ 1 ] ; val = operands [ 2 ] ; model = ( enum memmodel ) INTVAL ( operands [ 3 ] ) ; mode = GET_MODE ( mem ) ; mask = shift = NULL_RTX ; if ( ! TARGET_SYNC_HI_QI && ( mode == QImode || mode == HImode ) ) { mem = rs6000_adjust_atomic_subword ( mem , & shift , & mask ) ; val = convert_modes ( SImode , mode , val , 1 ) ; val = expand_simple_binop ( SImode , ASHIFT , val , shift , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; retval = gen_reg_rtx ( SImode ) ; mode = SImode ; } mem = rs6000_pre_atomic_barrier ( mem , model ) ; label = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label , 0 ) ) ; emit_load_locked ( mode , retval , mem ) ; x = val ; if ( mask ) x = rs6000_mask_atomic_subword ( retval , val , mask ) ; cond = gen_reg_rtx ( CCmode ) ; emit_store_conditional ( mode , cond , mem , x ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label ) ; rs6000_post_atomic_barrier ( model ) ; if ( shift ) rs6000_finish_atomic_subword ( operands [ 0 ] , retval , shift ) ; } </s>


<s> static bool arc_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { return ( ( to == HARD_FRAME_POINTER_REGNUM ) || ( to == STACK_POINTER_REGNUM ) ) ; } </s>

Given FROM and TO register numbers , say whether this elimination is allowed . Frame pointer elimination is automatically handled . All eliminations are permissible . If we need a frame pointer , we must eliminate ARG_POINTER_REGNUM into FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM .


<s> static rtx riscv_unspec_address_offset ( rtx base , rtx offset , enum riscv_symbol_type symbol_type ) { base = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , base ) , UNSPEC_ADDRESS_FIRST + symbol_type ) ; if ( offset != const0_rtx ) base = gen_rtx_PLUS ( Pmode , base , offset ) ; return gen_rtx_CONST ( Pmode , base ) ; } </s>

Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE , then add CONST_INT OFFSET to the result .


<s>
void
AMDGPUAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsPCRel
,
MCContext
&
Ctx
)
const
{
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
uint32_t
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
Data
[
Offset
+
i
]
|=
static_cast
<
uint8_t
>
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


"no expression found in stanza header.\n"

Parse one stanza of the input BIF file . linebuf already contains the first line to parse .


<s> void assignValueToReg ( Register ValVReg , Register PhysReg , CCValAssign & VA ) override { MIB . addUse ( PhysReg , RegState :: Implicit ) ; Register ExtReg = extendRegisterMin32 ( * this , ValVReg , VA ) ; MIRBuilder . buildCopy ( PhysReg , ExtReg ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> MachinePointerInfo Cpu0MachineFunctionInfo :: callPtrInfo ( const GlobalValue * GV ) { return MachinePointerInfo ( MF . getPSVManager ( ) . getGlobalValueCallEntry ( GV ) ) ; } </s>

Create a MachinePointerInfo that has a GlobalValuePseudoSourceValue object representing a GOT entry for a global function .


<s> bool AMDGPUInstrInfo :: isCoalescableExtInstr ( const MachineInstr & MI , unsigned & SrcReg , unsigned & DstReg , unsigned & SubIdx ) const { return false ; } </s>

isCoalescableExtInstr - Return true if the instruction is a `` coalescable '' extension instruction .


<s> SDValue AArch64SelectionDAGInfo :: EmitTargetCodeForMemmove ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { const AArch64Subtarget & STI = DAG . getMachineFunction ( ) . getSubtarget < AArch64Subtarget > ( ) ; if ( STI . hasMOPS ( ) ) { return EmitMOPS ( AArch64ISD :: MOPS_MEMMOVE , DAG , dl , Chain , Dst , Src , Size , Alignment , isVolatile , DstPtrInfo , SrcPtrInfo ) ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memmove .


<s> void sparc_expand_vcond ( machine_mode mode , rtx * operands , int ccode , int fcode ) { rtx mask , cop0 , cop1 , fcmp , cmask , bshuf , gsr ; enum rtx_code code = GET_CODE ( operands [ 3 ] ) ; mask = gen_reg_rtx ( Pmode ) ; cop0 = operands [ 4 ] ; cop1 = operands [ 5 ] ; if ( code == LT || code == GE ) { rtx t ; code = swap_condition ( code ) ; t = cop0 ; cop0 = cop1 ; cop1 = t ; } gsr = gen_rtx_REG ( DImode , SPARC_GSR_REG ) ; fcmp = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , gen_rtx_fmt_ee ( code , mode , cop0 , cop1 ) ) , fcode ) ; cmask = gen_rtx_UNSPEC ( DImode , gen_rtvec ( 2 , mask , gsr ) , ccode ) ; bshuf = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , operands [ 1 ] , operands [ 2 ] , gsr ) , UNSPEC_BSHUFFLE ) ; emit_insn ( gen_rtx_SET ( mask , fcmp ) ) ; emit_insn ( gen_rtx_SET ( gsr , cmask ) ) ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , bshuf ) ) ; } </s>

Emit code to conditionally move a combination of OPERANDS [ 1 ] and OPERANDS [ 2 ] into OPERANDS [ 0 ] in MODE , depending on the outcome of the comparison of OPERANDS [ 4 ] and OPERANDS [ 5 ] . OPERANDS [ 3 ] is the operator of the condition . FCODE is the machine code to be used for OPERANDS [ 3 ] and CCODE the machine code to be used for the condition mask .


<s> inline void function_expander :: add_input_operand ( machine_mode mode , rtx op ) { create_input_operand ( & m_ops [ opno ++ ] , op , mode ) ; } </s>

Create op and add it into M_OPS and increase OPNO .


<s> virtual const ARMRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool csky_minipool_load_p ( rtx_insn * insn ) { rtx op1 , addr ; extract_insn_cached ( insn ) ; op1 = recog_data . operand [ 1 ] ; if ( CONSTANT_P ( op1 ) ) return true ; if ( GET_CODE ( op1 ) == ZERO_EXTEND || GET_CODE ( op1 ) == SIGN_EXTEND ) op1 = XEXP ( op1 , 0 ) ; if ( GET_CODE ( op1 ) != MEM ) return false ; addr = XEXP ( op1 , 0 ) ; if ( GET_CODE ( addr ) == PLUS && CONST_INT_P ( XEXP ( addr , 1 ) ) ) addr = XEXP ( addr , 0 ) ; return GET_CODE ( addr ) == LABEL_REF ; } </s>

Return true if INSN is a minipool load or instruction that will be converted to one . It is assumed that INSN has type attribute `` load '' .


<s>
unsigned
ARMCodeEmitter
::
getMachineOpValue
(
const
MachineInstr
&
MI
,
const
MachineOperand
&
MO
)
const
{
if
(
MO
.
isReg
(
)
)
return
II
->
getRegisterInfo
(
)
.
getEncodingValue
(
MO
.
getReg
(
)
)
;
else
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
else
if
(
MO
.
isFPImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getFPImm
(
)
->
getValueAPF
(
)
.
bitcastToAPInt
(
)
.
getHiBits
(
32
)
.
getLimitedValue
(
)
)
;
else
if
(
MO
.
isGlobal
(
)
)
emitGlobalAddress
(
MO
.
getGlobal
(
)
,
ARM
::
reloc_arm_branch
,
true
,
false
)
;
else
if
(
MO
.
isSymbol
(
)
)
emitExternalSymbolAddress
(
MO
.
getSymbolName
(
)
,
ARM
::
reloc_arm_branch
)
;
else
if
(
MO
.
isCPI
(
)
)
{
const
MCInstrDesc
&
MCID
=
MI
.
getDesc
(
)
;
unsigned
Reloc
=
(
(
MCID
.
TSFlags
&
ARMII
::
FormMask
)
==
ARMII
::
VFPLdStFrm
)
ARM
::
reloc_arm_vfp_cp_entry
:
ARM
::
reloc_arm_cp_entry
;
emitConstPoolAddress
(
MO
.
getIndex
(
)
,
Reloc
)
;
}
else
if
(
MO
.
isJTI
(
)
)
emitJumpTableAddress
(
MO
.
getIndex
(
)
,
ARM
::
reloc_arm_relative
)
;
else
if
(
MO
.
isMBB
(
)
)
emitMachineBasicBlock
(
MO
.
getMBB
(
)
,
ARM
::
reloc_arm_branch
)
;
else
llvm_unreachable
(
"Unable to encode MachineOperand!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> bool AArch64TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> const MCPhysReg * VERegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_SaveList ; } </s>


<s> bool RISCVAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == ".option" ) return parseDirectiveOption ( ) ; else if ( IDVal == ".attribute" ) return parseDirectiveAttribute ( ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool NEONPreAllocPass :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getTarget ( ) . getInstrInfo ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= PreAllocNEONRegisters ( MBB ) ; } return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> static HOST_WIDE_INT aarch64_constant_alignment ( const_tree exp , HOST_WIDE_INT align ) { if ( TREE_CODE ( exp ) == STRING_CST && ! optimize_size ) return MAX ( align , BITS_PER_WORD ) ; return align ; } </s>

Implement TARGET_CONSTANT_ALIGNMENT . Make strings word-aligned so that strcpy from constants will be faster .


"********** AArch64 Conditional Compares **********\n"


<s> bool X86TTIImpl :: isLegalMaskedLoad ( Type * DataTy ) { Type * ScalarTy = DataTy -> getScalarType ( ) ; int DataWidth = isa < PointerType > ( ScalarTy ) ? DL . getPointerSizeInBits ( ) : ScalarTy -> getPrimitiveSizeInBits ( ) ; return ( ( DataWidth == 32 || DataWidth == 64 ) && ST -> hasAVX ( ) ) || ( ( DataWidth == 8 || DataWidth == 16 ) && ST -> hasBWI ( ) ) ; } </s>

Return true if the target supports masked load .


<s>
bool
AMDGPUAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Operands
.
push_back
(
AMDGPUOperand
::
CreateToken
(
Name
,
NameLoc
)
)
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
return
false
;
AMDGPUAsmParser
::
OperandMatchResultTy
Res
=
parseOperand
(
Operands
,
Name
)
;
switch
(
Res
)
{
case
MatchOperand_Success
:
return
false
;
case
MatchOperand_ParseFail
:
return
Error
(
NameLoc
,
"Failed parsing operand"
)
;
case
MatchOperand_NoMatch
:
return
Error
(
NameLoc
,
"Not a valid operand"
)
;
}
return
true
;
}
</s>

ParseInstruction - Parse one assembly instruction .

R600
"Failed parsing operand"
"Not a valid operand"


<s>
unsigned
ARMMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
{
unsigned
Reg
=
MO
.
getReg
(
)
;
unsigned
RegNo
=
CTX
.
getRegisterInfo
(
)
->
getEncodingValue
(
Reg
)
;
if
(
STI
.
getFeatureBits
(
)
[
ARM
::
HasMVEIntegerOps
]
)
return
RegNo
;
switch
(
Reg
)
{
default
:
return
RegNo
;
case
ARM
::
Q0
:
case
ARM
::
Q1
:
case
ARM
::
Q2
:
case
ARM
::
Q3
:
case
ARM
::
Q4
:
case
ARM
::
Q5
:
case
ARM
::
Q6
:
case
ARM
::
Q7
:
case
ARM
::
Q8
:
case
ARM
::
Q9
:
case
ARM
::
Q10
:
case
ARM
::
Q11
:
case
ARM
::
Q12
:
case
ARM
::
Q13
:
case
ARM
::
Q14
:
case
ARM
::
Q15
:
return
2
*
RegNo
;
}
}
else
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
else
if
(
MO
.
isDFPImm
(
)
)
{
return
static_cast
<
unsigned
>
(
APFloat
(
bit_cast
<
double
>
(
MO
.
getDFPImm
(
)
)
)
.
bitcastToAPInt
(
)
.
getHiBits
(
32
)
.
getLimitedValue
(
)
)
;
}
llvm_unreachable
(
"Unable to encode MCOperand!"
)
;
}
</s>


<s> static bool tryAddingSymbolicOperand ( int64_t Value , bool IsBranch , uint64_t Address , uint64_t Offset , uint64_t Width , MCInst & MI , const void * Decoder ) { const MCDisassembler * Dis = static_cast < const MCDisassembler * > ( Decoder ) ; return Dis -> tryAddingSymbolicOperand ( MI , Value , Address , IsBranch , Offset , Width ) ; } </s>

Try to add a symbolic operand instead of Value to the MCInst .


<s> bool RISCVTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( AM . BaseGV ) return false ; if ( ! isInt < 12 > ( AM . BaseOffs ) ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( ! AM . HasBaseReg ) break ; return false ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> bool GBZ80PassConfig :: addInstSelector ( ) { addPass ( createGBZ80ISelDAG ( getGBZ80TargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> int X86FrameLowering :: mergeSPUpdates ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , bool doMergeWithPrevious ) const { if ( ( doMergeWithPrevious && MBBI == MBB . begin ( ) ) || ( ! doMergeWithPrevious && MBBI == MBB . end ( ) ) ) return 0 ; MachineBasicBlock :: iterator PI = doMergeWithPrevious ? std :: prev ( MBBI ) : MBBI ; PI = skipDebugInstructionsBackward ( PI , MBB . begin ( ) ) ; if ( doMergeWithPrevious && PI != MBB . begin ( ) && PI -> isCFIInstruction ( ) ) PI = std :: prev ( PI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = 0 ; if ( ( Opc == X86 :: ADD64ri32 || Opc == X86 :: ADD64ri8 || Opc == X86 :: ADD32ri || Opc == X86 :: ADD32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { assert ( PI -> getOperand ( 1 ) . getReg ( ) == StackPtr ) ; Offset = PI -> getOperand ( 2 ) . getImm ( ) ; } else if ( ( Opc == X86 :: LEA32r || Opc == X86 :: LEA64_32r ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr && PI -> getOperand ( 1 ) . getReg ( ) == StackPtr && PI -> getOperand ( 2 ) . getImm ( ) == 1 && PI -> getOperand ( 3 ) . getReg ( ) == X86 :: NoRegister && PI -> getOperand ( 5 ) . getReg ( ) == X86 :: NoRegister ) { Offset = PI -> getOperand ( 4 ) . getImm ( ) ; } else if ( ( Opc == X86 :: SUB64ri32 || Opc == X86 :: SUB64ri8 || Opc == X86 :: SUB32ri || Opc == X86 :: SUB32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { assert ( PI -> getOperand ( 1 ) . getReg ( ) == StackPtr ) ; Offset = - PI -> getOperand ( 2 ) . getImm ( ) ; } else return 0 ; PI = MBB . erase ( PI ) ; if ( PI != MBB . end ( ) && PI -> isCFIInstruction ( ) ) PI = MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = skipDebugInstructionsForward ( PI , MBB . end ( ) ) ; return Offset ; } </s>

Check the instruction before/after the passed instruction .


<s> bool PPCInstrInfo :: analyzeLoop ( MachineLoop & L , MachineInstr * & IndVarInst , MachineInstr * & CmpInst ) const { MachineBasicBlock * LoopEnd = L . getBottomBlock ( ) ; MachineBasicBlock :: iterator I = LoopEnd -> getFirstTerminator ( ) ; if ( I != LoopEnd -> end ( ) && isBDNZ ( I -> getOpcode ( ) ) ) { IndVarInst = nullptr ; CmpInst = & * I ; return false ; } return true ; } </s>

Analyze the loop code , return true if it can not be understood .


<s> bool ARM64TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { if ( Imm . isPosZero ( ) && ( VT == MVT :: f64 || VT == MVT :: f32 ) ) return true ; if ( VT == MVT :: f64 ) return ARM64_AM :: getFP64Imm ( Imm ) != - 1 ; else if ( VT == MVT :: f32 ) return ARM64_AM :: getFP32Imm ( Imm ) != - 1 ; return false ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> void EmitInstruction ( uint64_t Val , unsigned Size , raw_ostream & OS ) const { for ( unsigned i = 0 ; i < Size ; ++ i ) { unsigned Shift = i * 8 ; EmitByte ( ( Val >> Shift ) & 0xff , OS ) ; } } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static int mem_is_padded_component_ref ( rtx x ) { tree t = MEM_EXPR ( x ) ; tree r ; if ( ! t || TREE_CODE ( t ) != COMPONENT_REF ) return 0 ; t = TREE_OPERAND ( t , 1 ) ; if ( ! t || TREE_CODE ( t ) != FIELD_DECL || DECL_ALIGN ( t ) < 128 || AGGREGATE_TYPE_P ( TREE_TYPE ( t ) ) ) return 0 ; r = DECL_FIELD_CONTEXT ( t ) ; if ( ! r || TREE_CODE ( r ) != RECORD_TYPE ) return 0 ; if ( GET_MODE ( x ) != TYPE_MODE ( TREE_TYPE ( t ) ) ) return 0 ; if ( TREE_CHAIN ( t ) == 0 ) return 1 ; t = TREE_CHAIN ( t ) ; if ( TREE_CODE ( t ) == FIELD_DECL && DECL_ALIGN ( t ) >= 128 ) return 1 ; return 0 ; } </s>

Return TRUE if X is MEM which is a struct member reference and the member can safely be loaded and stored with a single instruction because it is padded .


<s> void order_regs_for_local_alloc ( void ) { static int last_order_nonleaf = 1 ; if ( df_regs_ever_live_p ( 15 ) != last_order_nonleaf ) { last_order_nonleaf = ! last_order_nonleaf ; memcpy ( ( char * ) reg_alloc_order , ( const char * ) reg_alloc_orders [ last_order_nonleaf ] , FIRST_PSEUDO_REGISTER * sizeof ( int ) ) ; } } </s>

Choose the order in which to allocate hard registers for pseudo-registers local to a basic block . Store the desired register order in the array ` reg_alloc_order ' . Element 0 should be the register to allocate first ; element 1 , the next register ; and so on .


<s> static int ix86_mode_after ( int entity , int mode , rtx_insn * insn ) { switch ( entity ) { case X86_DIRFLAG : return mode ; case AVX_U128 : return ix86_avx_u128_mode_after ( mode , insn ) ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : case I387_MASK_PM : return mode ; default : gcc_unreachable ( ) ; } } </s>

Return the mode that an insn results in .


<s> VariantKind getKind ( ) const { return Kind ; } </s>


<s> unsigned getMaxInlineSizeThreshold ( ) const { return 64 ; } </s>

Returns the maximum memset / memcpy size that still makes it profitable to inline the call .


<s> bool OR1KInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . end ( ) ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! isUnpredicatedTerminator ( * I ) ) break ; if ( ! I -> isBranch ( ) ) return true ; if ( I -> getOpcode ( ) == OR1K :: JR ) return true ; if ( I -> getOpcode ( ) == OR1K :: J ) { if ( ! AllowModify ) { TBB = I -> getOperand ( 0 ) . getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = 0 ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( 0 ) . getMBB ( ) ) ) { TBB = 0 ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( 0 ) . getMBB ( ) ; continue ; } return true ; } return false ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool FPGATTIImpl :: isLegalMaskedLoad ( Type * DataType ) { return true ; } </s>


<s> bool AArch64TargetLowering :: shouldNormalizeToSelectSequence ( LLVMContext & , EVT ) const { return false ; } </s>

Returns true if we should normalize select ( N0 & N1 , X , Y ) = > select ( N0 , select ( N1 , X , Y ) , Y ) and select ( N0|N1 , X , Y ) = > select ( N0 , select ( N1 , X , Y , Y ) ) if it is likely that it saves us from materializing N0 and N1 in an integer register .


<s> bool invalid_e500_subreg ( rtx op , enum machine_mode mode ) { if ( GET_CODE ( op ) == SUBREG && mode == SImode && REG_P ( SUBREG_REG ( op ) ) && GET_MODE ( SUBREG_REG ( op ) ) == DFmode ) return true ; if ( GET_CODE ( op ) == SUBREG && mode == DFmode && REG_P ( SUBREG_REG ( op ) ) && GET_MODE ( SUBREG_REG ( op ) ) == DImode ) return true ; return false ; } </s>

Return TRUE if OP is an invalid SUBREG operation on the e500 .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Hexagon Vector Combine"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
static
void
mips16_build_function_stub
(
void
)
{
const
char
*
fnname
,
*
alias_name
,
*
separator
;
char
*
secname
,
*
stubname
;
tree
stubdecl
;
unsigned
int
f
;
rtx
symbol
,
alias
;
symbol
=
XEXP
(
DECL_RTL
(
current_function_decl
)
,
0
)
;
alias
=
mips16_local_alias
(
symbol
)
;
fnname
=
targetm
.
strip_name_encoding
(
XSTR
(
symbol
,
0
)
)
;
alias_name
=
targetm
.
strip_name_encoding
(
XSTR
(
alias
,
0
)
)
;
secname
=
ACONCAT
(
(
".mips16.fn."
,
fnname
,
)
)
;
stubname
=
ACONCAT
(
(
"__fn_stub_"
,
fnname
,
)
)
;
stubdecl
=
build_decl
(
BUILTINS_LOCATION
,
FUNCTION_DECL
,
get_identifier
(
stubname
)
,
build_function_type_list
(
void_type_node
,
NULL_TREE
)
)
;
set_decl_section_name
(
stubdecl
,
secname
)
;
DECL_RESULT
(
stubdecl
)
=
build_decl
(
BUILTINS_LOCATION
,
RESULT_DECL
,
NULL_TREE
,
void_type_node
)
;
fprintf
(
asm_out_file
,
"\t# Stub function for %s ("
,
current_function_name
(
)
)
;
separator
=
""
;
for
(
f
=
(
unsigned
int
)
crtl
->
args
.
info
.
fp_code
;
f
!=
0
;
f
>>=
2
)
{
fprintf
(
asm_out_file
,
"%s%s"
,
separator
,
(
f
&
3
)
==
1
"float"
:
"double"
)
;
separator
=
", "
;
}
fprintf
(
asm_out_file
,
")\n"
)
;
assemble_start_function
(
stubdecl
,
stubname
)
;
mips_start_function_definition
(
stubname
,
false
)
;
if
(
TARGET_ABICALLS_PIC2
)
{
if
(
TARGET_ABSOLUTE_ABICALLS
)
fprintf
(
asm_out_file
,
"\t.option\tpic0\n"
)
;
else
{
output_asm_insn
(
"%(.cpload\t%^%)"
,
)
;
output_asm_insn
(
".reloc\t0,R_MIPS_NONE,%0"
,
&
symbol
)
;
symbol
=
alias
;
}
}
output_asm_insn
(
"la\t%^,%0"
,
&
symbol
)
;
mips_output_args_xfer
(
crtl
->
args
.
info
.
fp_code
,
'f'
)
;
output_asm_insn
(
"jr\t%^"
,
)
;
if
(
TARGET_ABICALLS_PIC2
&&
TARGET_ABSOLUTE_ABICALLS
)
fprintf
(
asm_out_file
,
"\t.option\tpic2\n"
)
;
mips_end_function_definition
(
stubname
)
;
ASM_OUTPUT_DEF
(
asm_out_file
,
alias_name
,
fnname
)
;
switch_to_section
(
function_section
(
current_function_decl
)
)
;
}
</s>

Write a MIPS16 stub for the current function . This stub is used for functions which take arguments in the floating-point registers . It is normal-mode code that moves the floating-point arguments into the general registers and then jumps to the MIPS16 code .


<s> bool X86CallFrameOptimization :: runOnMachineFunction ( MachineFunction & MF ) { STI = & MF . getSubtarget < X86Subtarget > ( ) ; TII = STI -> getInstrInfo ( ) ; TFL = STI -> getFrameLowering ( ) ; MRI = & MF . getRegInfo ( ) ; if ( ! isLegal ( MF ) ) return false ; unsigned FrameSetupOpcode = TII -> getCallFrameSetupOpcode ( ) ; bool Changed = false ; ContextVector CallSeqVector ; for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ++ I ) if ( I -> getOpcode ( ) == FrameSetupOpcode ) { CallContext Context ; collectCallInfo ( MF , * BB , I , Context ) ; CallSeqVector . push_back ( Context ) ; } if ( ! isProfitable ( MF , CallSeqVector ) ) return false ; for ( auto CC : CallSeqVector ) if ( CC . UsePush ) Changed |= adjustCallSequence ( MF , CC ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool hasFusion ( ) const { return hasArithmeticBccFusion ( ) || hasArithmeticCbzFusion ( ) || hasFuseAES ( ) || hasFuseLiterals ( ) ; } </s>

Return true if the CPU supports any kind of instruction fusion .


<s> int legitimate_const_double_p ( rtx address ) { REAL_VALUE_TYPE r ; long sval [ 2 ] ; REAL_VALUE_FROM_CONST_DOUBLE ( r , address ) ; REAL_VALUE_TO_TARGET_DOUBLE ( r , sval ) ; if ( ( sval [ 0 ] & 0xffff ) == 0 && sval [ 1 ] == 0 ) return 1 ; return 0 ; } </s>

This function checks whether a real value can be encoded as a literal , i.e. , addressing mode 27 . In that mode , real values are one word values , so the remaining 48 bits have to be zero .


<s> const char * mcore_output_cmov ( rtx operands [ ] , int cmp_t , const char * test ) { HOST_WIDE_INT load_value ; HOST_WIDE_INT adjust_value ; rtx out_operands [ 4 ] ; out_operands [ 0 ] = operands [ 0 ] ; if ( const_ok_for_mcore ( INTVAL ( operands [ 1 ] ) ) ) { out_operands [ 1 ] = operands [ 1 ] ; out_operands [ 2 ] = operands [ 2 ] ; } else if ( const_ok_for_mcore ( INTVAL ( operands [ 2 ] ) ) ) { out_operands [ 1 ] = operands [ 2 ] ; out_operands [ 2 ] = operands [ 1 ] ; cmp_t = ( cmp_t == 0 ) ; } load_value = INTVAL ( out_operands [ 1 ] ) ; adjust_value = INTVAL ( out_operands [ 2 ] ) ; if ( test ) output_asm_insn ( test , operands ) ; if ( load_value >= 0 && load_value <= 127 ) output_asm_insn ( "movi\t%0,%1" , out_operands ) ; else if ( CONST_OK_FOR_M ( load_value ) ) output_asm_insn ( "bgeni\t%0,%P1" , out_operands ) ; else if ( CONST_OK_FOR_N ( load_value ) ) output_asm_insn ( "bmaski\t%0,%N1" , out_operands ) ; if ( load_value > adjust_value ) { if ( cmp_t ) output_asm_insn ( "decf\t%0" , out_operands ) ; else output_asm_insn ( "dect\t%0" , out_operands ) ; } else { if ( cmp_t ) output_asm_insn ( "incf\t%0" , out_operands ) ; else output_asm_insn ( "inct\t%0" , out_operands ) ; } return "" ; } </s>

Output a conditional move of two constants that are +/- 1 within each other . See the `` movtK '' patterns in mcore.md . I 'm not sure this is really worth the effort .


<s> static int xtensa_register_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t from , reg_class_t to ) { if ( from == to && from != BR_REGS && to != BR_REGS ) return 2 ; else if ( reg_class_subset_p ( from , AR_REGS ) && reg_class_subset_p ( to , AR_REGS ) ) return 2 ; else if ( reg_class_subset_p ( from , AR_REGS ) && to == ACC_REG ) return 3 ; else if ( from == ACC_REG && reg_class_subset_p ( to , AR_REGS ) ) return 3 ; else return 10 ; } </s>

Worker function for TARGET_REGISTER_MOVE_COST .


<s> int avr_jump_mode ( rtx x , rtx insn ) { int dest_addr = INSN_ADDRESSES ( INSN_UID ( GET_MODE ( x ) == LABEL_REF ? XEXP ( x , 0 ) : x ) ) ; int cur_addr = INSN_ADDRESSES ( INSN_UID ( insn ) ) ; int jump_distance = cur_addr - dest_addr ; if ( - 63 <= jump_distance && jump_distance <= 62 ) return 1 ; else if ( - 2046 <= jump_distance && jump_distance <= 2045 ) return 2 ; else if ( AVR_MEGA ) return 3 ; return 2 ; } </s>

Choose mode for jump insn : 1 - relative jump in range -63 < = x < = 62 ; 2 - relative jump in range -2046 < = x < = 2045 ; 3 - absolute jump ( only for ATmega [ 16 ] 03 ) .


"EBP/ESI restoration only required on win32"

"restoring EBP/ESI on non-32-bit target"

"end of registration object above normal EBP position!"

"32-bit frames with WinEH must use FramePtr or BasePtr"

Sets up EBP and optionally ESI based on the incoming EBP value .


<s> int rl78_initial_elimination_offset ( int from , int to ) { int rv = 0 ; rl78_compute_frame_info ( ) ; switch ( to ) { case STACK_POINTER_REGNUM : rv += cfun -> machine -> framesize_outgoing ; rv += cfun -> machine -> framesize_locals ; case FRAME_POINTER_REGNUM : rv += cfun -> machine -> framesize_regs ; rv += 4 ; break ; default : gcc_unreachable ( ) ; } switch ( from ) { case FRAME_POINTER_REGNUM : rv -= 4 ; rv -= cfun -> machine -> framesize_regs ; case ARG_POINTER_REGNUM : break ; default : gcc_unreachable ( ) ; } return rv ; } </s>

Implements INITIAL_ELIMINATION_OFFSET . The frame layout is described in the machine_Function struct definition , above .


<s> static unsigned int rs6000_xcoff_section_type_flags ( tree decl , const char * name , int reloc ) { unsigned int align ; unsigned int flags = default_section_type_flags ( decl , name , reloc ) ; if ( decl && DECL_P ( decl ) && VAR_P ( decl ) && bss_initializer_p ( decl ) ) flags |= SECTION_BSS ; if ( ! decl || ! DECL_P ( decl ) ) align = MIN_UNITS_PER_WORD ; else if ( ( flags & SECTION_CODE ) != 0 ) align = MAX ( ( DECL_ALIGN ( decl ) / BITS_PER_UNIT ) , 32 ) ; else align = MAX ( ( DECL_ALIGN ( decl ) / BITS_PER_UNIT ) , int_size_in_bytes ( TREE_TYPE ( decl ) ) > MIN_UNITS_PER_WORD ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD ) ; return flags | ( exact_log2 ( align ) & SECTION_ENTSIZE ) ; } </s>

Section attributes . AIX is always PIC .


<s> bool ARMTargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { if ( ! Subtarget -> supportsTailCall ( ) ) return false ; if ( ! CI -> isTailCall ( ) ) return false ; return true ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> void split_di ( rtx operands [ ] , int num , rtx lo_half [ ] , rtx hi_half [ ] ) { while ( num -- ) { rtx op = operands [ num ] ; if ( GET_CODE ( op ) == MEM ) { lo_half [ num ] = adjust_address ( op , SImode , 4 ) ; hi_half [ num ] = adjust_address ( op , SImode , 0 ) ; } else { lo_half [ num ] = simplify_gen_subreg ( SImode , op , GET_MODE ( op ) == VOIDmode ? DImode : GET_MODE ( op ) , 4 ) ; hi_half [ num ] = simplify_gen_subreg ( SImode , op , GET_MODE ( op ) == VOIDmode ? DImode : GET_MODE ( op ) , 0 ) ; } } } </s>

Split one or more DImode RTL references into pairs of SImode references . The RTL can be REG , offsettable MEM , integer constant , or CONST_DOUBLE . `` operands '' is a pointer to an array of DImode RTL to split and `` num '' is its length . lo_half and hi_half are output arrays that parallel `` operands '' .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return 0 ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static rtx mips_add_offset ( rtx temp , rtx reg , HOST_WIDE_INT offset ) { if ( ! SMALL_OPERAND ( offset ) ) { rtx high ; if ( TARGET_MIPS16 ) { high = GEN_INT ( offset ) ; offset = 0 ; } else { high = gen_int_mode ( CONST_HIGH_PART ( offset ) , Pmode ) ; offset = CONST_LOW_PART ( offset ) ; } high = mips_force_temporary ( temp , high ) ; reg = mips_force_temporary ( temp , gen_rtx_PLUS ( Pmode , high , reg ) ) ; } return plus_constant ( Pmode , reg , offset ) ; } </s>

Return a legitimate address for REG + OFFSET . TEMP is as for mips_force_temporary ; it is only needed when OFFSET is not a SMALL_OPERAND .


<s> static inline bool mode_supports_pre_modify_p ( machine_mode mode ) { return ( ( reg_addr [ mode ] . addr_mask [ RELOAD_REG_ANY ] & RELOAD_REG_PRE_MODIFY ) != 0 ) ; } </s>

Helper function to say whether a mode supports PRE_MODIFY .


<s> static bool arm_xscale_rtx_costs ( rtx x , int code , int outer_code , int * total ) { enum machine_mode mode = GET_MODE ( x ) ; if ( TARGET_THUMB ) { * total = thumb_rtx_costs ( x , code , outer_code ) ; return true ; } switch ( code ) { case MULT : if ( mode == DImode && ( GET_CODE ( XEXP ( x , 0 ) ) == GET_CODE ( XEXP ( x , 1 ) ) ) && ( GET_CODE ( XEXP ( x , 0 ) ) == ZERO_EXTEND || GET_CODE ( XEXP ( x , 0 ) ) == SIGN_EXTEND ) ) { * total = 8 ; return true ; } if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || mode == DImode ) { * total = 30 ; return true ; } if ( GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) { unsigned HOST_WIDE_INT i = ( INTVAL ( XEXP ( x , 1 ) ) & ( unsigned HOST_WIDE_INT ) 0xffffffff ) ; int cost , const_ok = const_ok_for_arm ( i ) ; unsigned HOST_WIDE_INT masked_const ; cost = 2 ; if ( ! const_ok ) cost += 1 ; masked_const = i & 0xffff8000 ; if ( masked_const != 0 && masked_const != 0xffff8000 ) { masked_const = i & 0xf8000000 ; if ( masked_const == 0 || masked_const == 0xf8000000 ) cost += 1 ; else cost += 2 ; } * total = cost ; return true ; } * total = 8 + ( REG_OR_SUBREG_REG ( XEXP ( x , 0 ) ) ? 0 : 4 ) + ( REG_OR_SUBREG_REG ( XEXP ( x , 1 ) ) ? 0 : 4 ) ; return true ; case COMPARE : if ( GET_CODE ( XEXP ( x , 0 ) ) == MULT ) * total = 4 + rtx_cost ( XEXP ( x , 0 ) , code ) ; else * total = arm_rtx_costs_1 ( x , code , outer_code ) ; return true ; default : * total = arm_rtx_costs_1 ( x , code , outer_code ) ; return true ; } } </s>

RTX cost for XScale CPUs . Thumb-2 is not supported on any xscale cores , so it can be ignored .


<s> static rtx avr_find_unused_d_reg ( rtx_insn * insn , rtx exclude ) { bool isr_p = ( avr_interrupt_function_p ( current_function_decl ) || avr_signal_function_p ( current_function_decl ) ) ; for ( int regno = 16 ; regno < 32 ; regno ++ ) { rtx reg = all_regs_rtx [ regno ] ; if ( ( exclude && reg_overlap_mentioned_p ( exclude , reg ) ) || fixed_regs [ regno ] ) { continue ; } if ( ! df_regs_ever_live_p ( regno ) && ( TREE_THIS_VOLATILE ( current_function_decl ) || cfun -> machine -> is_OS_task || cfun -> machine -> is_OS_main || ( ! isr_p && call_used_or_fixed_reg_p ( regno ) ) ) ) { return reg ; } if ( df_regs_ever_live_p ( regno ) && reg_unused_after ( insn , reg ) ) { return reg ; } } return NULL_RTX ; } </s>

Fixme : This is a hack because secondary reloads do n't works as expected . Find an unused d-register to be used as scratch in INSN . EXCLUDE is either NULL_RTX or some register . In the case where EXCLUDE is a register , skip all possible return values that overlap EXCLUDE . The policy for the returned register is similar to that of ` reg_unused_after ' , i.e . the returned register may overlap the SET_DEST of INSN . Return a QImode d-register or NULL_RTX if nothing found .


<s> rtx tilegx_simd_int ( rtx num , machine_mode mode ) { HOST_WIDE_INT n = 0 ; gcc_assert ( CONST_INT_P ( num ) ) ; n = INTVAL ( num ) ; switch ( mode ) { case QImode : n = 0x0101010101010101LL * ( n & 0x000000FF ) ; break ; case HImode : n = 0x0001000100010001LL * ( n & 0x0000FFFF ) ; break ; case SImode : n = 0x0000000100000001LL * ( n & 0xFFFFFFFF ) ; break ; case DImode : break ; default : gcc_unreachable ( ) ; } return GEN_INT ( n ) ; } </s>

Return the simd variant of the constant NUM of mode MODE , by replicating it to fill an interger of mode DImode . NUM is first truncated to fit in MODE .


<s> void m32c_init_cumulative_args ( CUMULATIVE_ARGS * ca , tree fntype , rtx libname ATTRIBUTE_UNUSED , tree fndecl , int n_named_args ATTRIBUTE_UNUSED ) { if ( fntype && aggregate_value_p ( TREE_TYPE ( fntype ) , fndecl ) ) ca -> force_mem = 1 ; else ca -> force_mem = 0 ; ca -> parm_num = 1 ; } </s>


"Only Linux target is expected to contain LOAD_STACK_GUARD"

This function is called for all pseudo instructions that remain after register allocation .


"Unmatched number of shufflevectors and indices"

Lower interleaved load ( s ) into target specific instructions/intrinsics .


<s> bool BPFTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( ! AM . HasBaseReg ) break ; return false ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> void WDC65816TargetLowering :: LowerOperationWrapper ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { SDValue Res = LowerOperation ( SDValue ( N , 0 ) , DAG ) ; for ( unsigned I = 0 , E = Res -> getNumValues ( ) ; I != E ; ++ I ) Results . push_back ( Res . getValue ( I ) ) ; } </s>

This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types .


<s> TargetPassConfig * FISCTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new FISCPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


"WebAssembly hasn't implemented computed gotos"

"WebAssembly hasn't implemented __builtin_return_address"

LowerOperation - Provide custom lowering hooks for some operations .


"Can only put epilog before 'retl' instruction!"


<s> bool isConstantSplat ( SDValue Op , APInt & SplatVal , bool AllowPartialUndefs ) { APInt UndefElts ; SmallVector < APInt , 16 > EltBits ; if ( getTargetConstantBitsFromNode ( Op , Op . getScalarValueSizeInBits ( ) , UndefElts , EltBits , true , AllowPartialUndefs ) ) { int SplatIndex = - 1 ; for ( int i = 0 , e = EltBits . size ( ) ; i != e ; ++ i ) { if ( UndefElts [ i ] ) continue ; if ( 0 <= SplatIndex && EltBits [ i ] != EltBits [ SplatIndex ] ) { SplatIndex = - 1 ; break ; } SplatIndex = i ; } if ( 0 <= SplatIndex ) { SplatVal = EltBits [ SplatIndex ] ; return true ; } } return false ; } </s>

Check if this is a constant splat , and if so , find the smallest element size that splats the vector .


<s> void XCoreInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> DecodeStatus HexagonDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & os , raw_ostream & cs ) const { DecodeStatus Result = DecodeStatus :: Success ; bool Complete = false ; Size = 0 ; * CurrentBundle = & MI ; MI = HexagonMCInstrInfo :: createBundle ( ) ; while ( Result == Success && ! Complete ) { if ( Bytes . size ( ) < HEXAGON_INSTR_SIZE ) return MCDisassembler :: Fail ; MCInst * Inst = new ( getContext ( ) ) MCInst ; Result = getSingleInstruction ( * Inst , MI , Bytes , Address , os , cs , Complete ) ; MI . addOperand ( MCOperand :: createInst ( Inst ) ) ; Size += HEXAGON_INSTR_SIZE ; Bytes = Bytes . slice ( HEXAGON_INSTR_SIZE ) ; } if ( Result == MCDisassembler :: Fail ) return Result ; if ( Size > HEXAGON_MAX_PACKET_SIZE ) return MCDisassembler :: Fail ; HexagonMCChecker Checker ( * MCII , STI , MI , MI , * getContext ( ) . getRegisterInfo ( ) ) ; if ( ! Checker . check ( ) ) return MCDisassembler :: Fail ; return MCDisassembler :: Success ; } </s>

Returns the disassembly of a single instruction .


<s> unsigned ARMFastISel :: fastEmitInst_ri ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , bool Op0IsKill , uint64_t Imm ) { unsigned ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , 1 ) ; if ( II . getNumDefs ( ) >= 1 ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addImm ( Imm ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addImm ( Imm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ 0 ] ) ) ; } return ResultReg ; } </s>

Emit a MachineInstr with a register operand , an immediate , and a result register in the given register class .


<s> MipsCCState :: SpecialCallingConvType MipsCCState :: getSpecialCallingConvForCallee ( const SDNode * Callee , const MipsSubtarget & Subtarget ) { MipsCCState :: SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv ; if ( Subtarget . inMips16HardFloat ( ) ) { if ( const GlobalAddressSDNode * G = dyn_cast < const GlobalAddressSDNode > ( Callee ) ) { llvm :: StringRef Sym = G -> getGlobal ( ) -> getName ( ) ; Function * F = G -> getGlobal ( ) -> getParent ( ) -> getFunction ( Sym ) ; if ( F && F -> hasFnAttribute ( "__Mips16RetHelper" ) ) { SpecialCallingConv = Mips16RetHelperConv ; } } } return SpecialCallingConv ; } </s>

Determine the SpecialCallingConvType for the given callee .

Mips Mips Mips Mips Mips Mips "__Mips16RetHelper" Mips


"Hexagon DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> static rtx ix86_expand_vec_ext_builtin ( tree arglist , rtx target ) { enum machine_mode tmode , mode0 ; tree arg0 , arg1 ; int elt ; rtx op0 ; arg0 = TREE_VALUE ( arglist ) ; arg1 = TREE_VALUE ( TREE_CHAIN ( arglist ) ) ; op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , 0 ) ; elt = get_element_number ( TREE_TYPE ( arg0 ) , arg1 ) ; tmode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( arg0 ) ) ) ; mode0 = TYPE_MODE ( TREE_TYPE ( arg0 ) ) ; gcc_assert ( VECTOR_MODE_P ( mode0 ) ) ; op0 = force_reg ( mode0 , op0 ) ; if ( optimize || ! target || ! register_operand ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; ix86_expand_vector_extract ( true , target , op0 , elt ) ; return target ; } </s>

A subroutine of ix86_expand_builtin . These builtins are a wrapper around ix86_expand_vector_extract . They would be redundant ( for non-MMX ) if we had a language-level syntax for referencing vector elements .


<s> static void hwloop_fail ( hwloop_info loop ) { rtx test ; rtx insn = loop -> loop_end ; if ( TARGET_DBNZ && ( loop -> length && ( loop -> length <= ARC_MAX_LOOP_LENGTH ) ) && REG_P ( loop -> iter_reg ) ) { test = gen_dbnz ( loop -> iter_reg , loop -> start_label ) ; insn = emit_jump_insn_before ( test , loop -> loop_end ) ; } else if ( REG_P ( loop -> iter_reg ) && ( REGNO ( loop -> iter_reg ) == LP_COUNT ) ) { emit_insn_before ( gen_loop_fail ( ) , loop -> loop_end ) ; test = gen_rtx_NE ( VOIDmode , gen_rtx_REG ( CC_ZNmode , CC_REG ) , const0_rtx ) ; test = gen_rtx_IF_THEN_ELSE ( VOIDmode , test , gen_rtx_LABEL_REF ( Pmode , loop -> start_label ) , pc_rtx ) ; insn = emit_jump_insn_before ( gen_rtx_SET ( pc_rtx , test ) , loop -> loop_end ) ; } else { emit_insn_before ( gen_addsi3 ( loop -> iter_reg , loop -> iter_reg , constm1_rtx ) , loop -> loop_end ) ; test = gen_rtx_NE ( VOIDmode , loop -> iter_reg , const0_rtx ) ; insn = emit_jump_insn_before ( gen_cbranchsi4 ( test , loop -> iter_reg , const0_rtx , loop -> start_label ) , loop -> loop_end ) ; } JUMP_LABEL ( insn ) = loop -> start_label ; LABEL_NUSES ( loop -> start_label ) ++ ; delete_insn ( loop -> loop_end ) ; } </s>

A callback for the hw-doloop pass . Called when a loop we have discovered turns out not to be optimizable ; we have to split the doloop_end pattern into a subtract and a test .


<s> unsigned getNumFixupKinds ( ) const override { return MINA32 :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> unsigned stackAlignment ( ) const { return 8 ; } </s>

The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function .