<s> static cpp_hashnode * s390_macro_to_expand ( cpp_reader * pfile , const cpp_token * tok ) { cpp_hashnode * expand_this = tok -> val . node . node ; cpp_hashnode * ident ; static bool expand_bool_p = false ; int idx = 0 ; enum rid rid_code ; if ( ! TARGET_ZVECTOR ) return NULL ; ident = s390_categorize_keyword ( tok ) ; if ( ident != expand_this ) expand_this = NULL ; if ( expand_bool_p && ident == C_CPP_HASHNODE ( __bool_keyword ) ) { expand_bool_p = false ; return ident ; } if ( ident != C_CPP_HASHNODE ( __vector_keyword ) ) return expand_this ; do tok = cpp_peek_token ( pfile , idx ++ ) ; while ( tok -> type == CPP_PADDING ) ; ident = s390_categorize_keyword ( tok ) ; if ( ! ident ) return expand_this ; if ( ident == C_CPP_HASHNODE ( __bool_keyword ) ) { expand_bool_p = true ; return C_CPP_HASHNODE ( __vector_keyword ) ; } if ( ident == C_CPP_HASHNODE ( __vector_keyword ) ) return expand_this ; rid_code = ( enum rid ) ( ident -> rid_code ) ; if ( cpp_macro_p ( ident ) ) { do ( void ) cpp_get_token ( pfile ) ; while ( -- idx > 0 ) ; do tok = cpp_peek_token ( pfile , idx ++ ) ; while ( tok -> type == CPP_PADDING ) ; ident = s390_categorize_keyword ( tok ) ; if ( ident == C_CPP_HASHNODE ( __bool_keyword ) ) { expand_bool_p = true ; return C_CPP_HASHNODE ( __vector_keyword ) ; } else if ( ident ) rid_code = ( enum rid ) ( ident -> rid_code ) ; } if ( rid_code == RID_UNSIGNED || rid_code == RID_LONG || rid_code == RID_SHORT || rid_code == RID_SIGNED || rid_code == RID_INT || rid_code == RID_CHAR || ( rid_code == RID_FLOAT && TARGET_VXE ) || rid_code == RID_DOUBLE ) { expand_this = C_CPP_HASHNODE ( __vector_keyword ) ; do tok = cpp_peek_token ( pfile , idx ++ ) ; while ( tok -> type == CPP_PADDING ) ; ident = s390_categorize_keyword ( tok ) ; if ( ident == C_CPP_HASHNODE ( __bool_keyword ) ) expand_bool_p = true ; else { do tok = cpp_peek_token ( pfile , idx ++ ) ; while ( tok -> type == CPP_PADDING ) ; ident = s390_categorize_keyword ( tok ) ; if ( ident == C_CPP_HASHNODE ( __bool_keyword ) ) expand_bool_p = true ; } } return expand_this ; } </s>

Called to decide whether a conditional macro should be expanded . Since we have exactly one such macro ( i.e , 'vector ' ) , we do not need to examine the 'tok ' parameter .


<s>
bool
AArch64FrameLowering
::
restoreCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
;
SmallVector
<
RegPairInfo
,
8
>
RegPairs
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
computeCalleeSaveRegisterPairs
(
MF
,
CSI
,
TRI
,
RegPairs
)
;
for
(
auto
RPII
=
RegPairs
.
begin
(
)
,
RPIE
=
RegPairs
.
end
(
)
;
RPII
!=
RPIE
;
++
RPII
)
{
RegPairInfo
RPI
=
*
RPII
;
unsigned
Reg1
=
RPI
.
Reg1
;
unsigned
Reg2
=
RPI
.
Reg2
;
unsigned
LdrOpc
;
if
(
RPI
.
IsGPR
)
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPXi
:
AArch64
::
LDRXui
;
else
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPDi
:
AArch64
::
LDRDui
;
DEBUG
(
dbgs
(
)
<<
"CSR restore: ("
<<
TRI
->
getName
(
Reg1
)
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
TRI
->
getName
(
Reg2
)
;
dbgs
(
)
<<
") -> fi#("
<<
RPI
.
FrameIdx
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
RPI
.
FrameIdx
+
1
;
dbgs
(
)
<<
")\n"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
LdrOpc
)
)
;
if
(
RPI
.
isPaired
(
)
)
{
MIB
.
addReg
(
Reg2
,
getDefRegState
(
true
)
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
+
1
)
,
MachineMemOperand
::
MOLoad
,
8
,
8
)
)
;
}
MIB
.
addReg
(
Reg1
,
getDefRegState
(
true
)
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
RPI
.
Offset
)
.
setMIFlag
(
MachineInstr
::
FrameDestroy
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
)
,
MachineMemOperand
::
MOLoad
,
8
,
8
)
)
;
}
return
true
;
}
</s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> void alpha_split_tfmode_frobsign ( rtx operands [ 3 ] , rtx ( * operation ) ( rtx , rtx , rtx ) ) { rtx high_bit = operands [ 2 ] ; rtx scratch ; int move ; alpha_split_tmode_pair ( operands , TFmode , false ) ; move = 1 ; if ( rtx_equal_p ( operands [ 0 ] , operands [ 2 ] ) ) move = 0 ; else if ( rtx_equal_p ( operands [ 1 ] , operands [ 2 ] ) ) { if ( rtx_equal_p ( operands [ 0 ] , high_bit ) ) move = 2 ; else move = - 1 ; } if ( move < 0 ) emit_move_insn ( operands [ 0 ] , operands [ 2 ] ) ; scratch = operands [ move < 2 ? 1 : 3 ] ; emit_insn ( ( * operation ) ( scratch , high_bit , operands [ 3 ] ) ) ; if ( move > 0 ) { emit_move_insn ( operands [ 0 ] , operands [ 2 ] ) ; if ( move > 1 ) emit_move_insn ( operands [ 1 ] , scratch ) ; } } </s>

Implement negtf2 or abstf2 . Op0 is destination , op1 is source , op2 is a register containing the sign bit , operation is the logical operation to be performed .


<s> bool HexagonInstrInfo :: isSchedulingBoundary ( const MachineInstr * MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( MI -> isDebugValue ( ) ) return false ; if ( MI -> isCall ( ) ) { for ( auto I : MBB -> successors ( ) ) if ( I -> isEHPad ( ) ) return true ; } if ( MI -> getOpcode ( ) == Hexagon :: CALLv3nr ) return true ; if ( MI -> getDesc ( ) . isTerminator ( ) || MI -> isPosition ( ) ) return true ; if ( MI -> isInlineAsm ( ) && ! ScheduleInlineAsm ) return true ; return false ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s>
unsigned
LanaiInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
Instruction
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
Instruction
!=
MBB
.
begin
(
)
)
{
Instruction
;
if
(
Instruction
->
isDebugValue
(
)
)
continue
;
if
(
Instruction
->
getOpcode
(
)
!=
Lanai
::
BT
&&
Instruction
->
getOpcode
(
)
!=
Lanai
::
BRCC
)
{
break
;
}
Instruction
->
eraseFromParent
(
)
;
Instruction
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .

Lanai
Lanai
"code size not handled"
0
Lanai::BT
Lanai::BRCC


<s> rtx mt_function_arg ( const CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int named , int incoming_p ) { int slotno , regno ; rtx reg ; slotno = mt_function_arg_slotno ( cum , mode , type , named , incoming_p , & regno ) ; if ( slotno == - 1 ) reg = NULL_RTX ; else reg = gen_rtx_REG ( mode , regno ) ; return reg ; } </s>


<s>
bool
AMDGPUCallLowering
::
lowerReturn
(
MachineIRBuilder
&
MIRBuilder
,
const
Value
*
Val
,
ArrayRef
<
Register
>
VRegs
)
const
{
MachineFunction
&
MF
=
MIRBuilder
.
getMF
(
)
;
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
SIMachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MFI
->
setIfReturnsVoid
(
!
Val
)
;
assert
(
!
Val
==
VRegs
.
empty
(
)
&&
"Return value without a vreg"
)
;
CallingConv
::
ID
CC
=
MIRBuilder
.
getMF
(
)
.
getFunction
(
)
.
getCallingConv
(
)
;
const
bool
IsShader
=
AMDGPU
::
isShader
(
CC
)
;
const
bool
IsWaveEnd
=
(
IsShader
&&
MFI
->
returnsVoid
(
)
)
||
AMDGPU
::
isKernel
(
CC
)
;
if
(
IsWaveEnd
)
{
MIRBuilder
.
buildInstr
(
AMDGPU
::
S_ENDPGM
)
.
addImm
(
0
)
;
return
true
;
}
auto
const
&
ST
=
MIRBuilder
.
getMF
(
)
.
getSubtarget
<
GCNSubtarget
>
(
)
;
unsigned
ReturnOpc
=
IsShader
AMDGPU
::
SI_RETURN_TO_EPILOG
:
AMDGPU
::
S_SETPC_B64_return
;
auto
Ret
=
MIRBuilder
.
buildInstrNoInsert
(
ReturnOpc
)
;
Register
ReturnAddrVReg
;
if
(
ReturnOpc
==
AMDGPU
::
S_SETPC_B64_return
)
{
ReturnAddrVReg
=
MRI
.
createVirtualRegister
(
&
AMDGPU
::
CCR_SGPR_64RegClass
)
;
Ret
.
addUse
(
ReturnAddrVReg
)
;
}
if
(
!
lowerReturnVal
(
MIRBuilder
,
Val
,
VRegs
,
Ret
)
)
return
false
;
if
(
ReturnOpc
==
AMDGPU
::
S_SETPC_B64_return
)
{
const
SIRegisterInfo
*
TRI
=
ST
.
getRegisterInfo
(
)
;
Register
LiveInReturn
=
MF
.
addLiveIn
(
TRI
->
getReturnAddressReg
(
MF
)
,
&
AMDGPU
::
SGPR_64RegClass
)
;
MIRBuilder
.
buildCopy
(
ReturnAddrVReg
,
LiveInReturn
)
;
}
MIRBuilder
.
insertInstr
(
Ret
)
;
return
true
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> int empty_delay_slot ( rtx_insn * insn ) { rtx seq ; if ( PREV_INSN ( insn ) == NULL ) return 1 ; seq = NEXT_INSN ( PREV_INSN ( insn ) ) ; if ( GET_CODE ( PATTERN ( seq ) ) == SEQUENCE ) return 0 ; return 1 ; } </s>

Return non-zero if a branch or call instruction will be emitting a nop into its delay slot .


<s>
void
dump
(
)
{
dbgs
(
)
<<
"M680x0ISelAddressMode "
<<
this
;
dbgs
(
)
<<
"\nDisp: "
<<
Disp
;
dbgs
(
)
<<
", BaseReg: "
;
if
(
BaseReg
.
getNode
(
)
)
BaseReg
.
getNode
(
)
->
dump
(
)
;
else
dbgs
(
)
<<
"null"
;
dbgs
(
)
<<
", BaseFI: "
<<
BaseFrameIndex
;
dbgs
(
)
<<
", IndexReg: "
;
if
(
IndexReg
.
getNode
(
)
)
{
IndexReg
.
getNode
(
)
->
dump
(
)
;
}
else
{
dbgs
(
)
<<
"null"
;
dbgs
(
)
<<
", Scale: "
<<
Scale
;
}
dbgs
(
)
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

M680x0
"M680x0ISelAddressMode "
"\nDisp: "
", BaseReg: "
"null"
", BaseFI: "
", IndexReg: "
"null"
", Scale: "


<s> bool MCS51TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { int64_t Offs = AM . BaseOffs ; if ( AM . BaseGV && ! AM . HasBaseReg && AM . Scale == 0 && Offs == 0 ) { return true ; } if ( isa < PointerType > ( Ty ) && AS == MCS51 :: ProgramMemory ) { return false ; } if ( Offs < 0 ) Offs = - Offs ; if ( AM . BaseGV == 0 && AM . HasBaseReg && AM . Scale == 0 && isUInt < 6 > ( Offs ) ) { return true ; } return false ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> static hashval_t hash ( const char * s ) { return htab_hash_string ( s ) ; } </s>

Hash function for builtin functions with up to 3 arguments and a return type .


<s> const BitTracker :: RegisterCell & lookup ( unsigned VR ) { unsigned RInd = TargetRegisterInfo :: virtReg2Index ( VR ) ; if ( RInd >= CVect . size ( ) ) CVect . resize ( std :: max ( RInd + 16 , 32U ) , nullptr ) ; const BitTracker :: RegisterCell * CP = CVect [ RInd ] ; if ( CP == nullptr ) CP = CVect [ RInd ] = & BT . lookup ( VR ) ; return * CP ; } </s>

This method finds the value with the given Name in the the symbol table .


<s> int memory_address_length ( rtx addr , bool lea ) { struct ix86_address parts ; rtx base , index , disp ; int len ; int ok ; if ( GET_CODE ( addr ) == PRE_DEC || GET_CODE ( addr ) == POST_INC || GET_CODE ( addr ) == PRE_MODIFY || GET_CODE ( addr ) == POST_MODIFY ) return 0 ; ok = ix86_decompose_address ( addr , & parts ) ; gcc_assert ( ok ) ; len = ( parts . seg == SEG_DEFAULT ) ? 0 : 1 ; if ( TARGET_64BIT && ! lea && ( SImode_address_operand ( addr , VOIDmode ) || ( parts . base && GET_MODE ( parts . base ) == SImode ) || ( parts . index && GET_MODE ( parts . index ) == SImode ) ) ) len ++ ; base = parts . base ; index = parts . index ; disp = parts . disp ; if ( base && GET_CODE ( base ) == SUBREG ) base = SUBREG_REG ( base ) ; if ( index && GET_CODE ( index ) == SUBREG ) index = SUBREG_REG ( index ) ; gcc_assert ( base == NULL_RTX || REG_P ( base ) ) ; gcc_assert ( index == NULL_RTX || REG_P ( index ) ) ; if ( base && ! index && ! disp ) { if ( base == arg_pointer_rtx || base == frame_pointer_rtx || REGNO ( base ) == SP_REG || REGNO ( base ) == BP_REG || REGNO ( base ) == R12_REG || REGNO ( base ) == R13_REG ) len ++ ; } else if ( disp && ! base && ! index ) { len += 4 ; if ( rip_relative_addr_p ( & parts ) ) len ++ ; } else { if ( disp ) { if ( base && satisfies_constraint_K ( disp ) ) len += 1 ; else len += 4 ; } else if ( base && ( REGNO ( base ) == BP_REG || REGNO ( base ) == R13_REG ) ) len ++ ; if ( index || base == arg_pointer_rtx || base == frame_pointer_rtx || ( base && ( REGNO ( base ) == SP_REG || REGNO ( base ) == R12_REG ) ) ) len ++ ; } return len ; } </s>

Calculate the length of the memory address in the instruction encoding . Does not include the one-byte modrm , opcode , or prefix .


<s>
MCOperand
PTXAsmPrinter
::
lowerOperand
(
const
MachineOperand
&
MO
)
{
MCOperand
MCOp
;
const
PTXMachineFunctionInfo
*
MFI
=
MF
->
getInfo
<
PTXMachineFunctionInfo
>
(
)
;
unsigned
EncodedReg
;
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"Unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
getReg
(
)
>
0
)
{
EncodedReg
=
MFI
->
getEncodedRegister
(
MO
.
getReg
(
)
)
;
}
else
{
EncodedReg
=
0
;
}
MCOp
=
MCOperand
::
CreateReg
(
EncodedReg
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
CreateImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
CreateExpr
(
MCSymbolRefExpr
::
Create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
OutContext
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
GetSymbolRef
(
MO
,
Mang
->
getSymbol
(
MO
.
getGlobal
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
GetSymbolRef
(
MO
,
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
)
;
break
;
case
MachineOperand
::
MO_FPImmediate
:
APFloat
Val
=
MO
.
getFPImm
(
)
->
getValueAPF
(
)
;
bool
ignored
;
Val
.
convert
(
APFloat
::
IEEEdouble
,
APFloat
::
rmTowardZero
,
&
ignored
)
;
MCOp
=
MCOperand
::
CreateFPImm
(
Val
.
convertToDouble
(
)
)
;
break
;
}
return
MCOp
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .

PTX
PTX
PTX
PTX
"Unknown operand type"
0
0


<s> static void init_window ( int window_num ) { int i ; dispatch_windows * new_list ; if ( window_num == 0 ) new_list = dispatch_window_list ; else new_list = dispatch_window_list1 ; new_list -> num_insn = 0 ; new_list -> num_uops = 0 ; new_list -> window_size = 0 ; new_list -> next = NULL ; new_list -> prev = NULL ; new_list -> window_num = window_num ; new_list -> num_imm = 0 ; new_list -> num_imm_32 = 0 ; new_list -> num_imm_64 = 0 ; new_list -> imm_size = 0 ; new_list -> num_loads = 0 ; new_list -> num_stores = 0 ; new_list -> violation = false ; for ( i = 0 ; i < MAX_INSN ; i ++ ) { new_list -> window [ i ] . insn = NULL ; new_list -> window [ i ] . group = disp_no_group ; new_list -> window [ i ] . path = no_path ; new_list -> window [ i ] . byte_len = 0 ; new_list -> window [ i ] . imm_bytes = 0 ; } return ; } </s>

This function initializes a dispatch window and the list container holding a pointer to the window .


"Wasn't expecting to be able to lower this!"

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool RISCVMCExpr :: evaluateAsConstant ( int64_t & Res ) const { MCValue Value ; if ( Kind == VK_RISCV_PCREL_HI || Kind == VK_RISCV_PCREL_LO || Kind == VK_RISCV_GOT_HI || Kind == VK_RISCV_TPREL_HI || Kind == VK_RISCV_TPREL_LO || Kind == VK_RISCV_TPREL_ADD || Kind == VK_RISCV_TLS_GOT_HI || Kind == VK_RISCV_TLS_GD_HI || Kind == VK_RISCV_CALL || Kind == VK_RISCV_CALL_PLT ) return false ; if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ) return false ; if ( ! Value . isAbsolute ( ) ) return false ; Res = evaluateAsInt64 ( Value . getConstant ( ) ) ; return true ; } </s>

Evaluates the fixup as a constant value .

RI5CY RISCV RISCV RISCV RISCV RISCV RISCV RISCV RISCV RISCV RISCV RISCV


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { const Function & F = MF . getFunction ( ) ; if ( skipFunction ( F ) ) return false ; HexagonConstEvaluator HCE ( MF ) ; return MachineConstPropagator ( HCE ) . run ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s>
MachineBasicBlock
*
TeakTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown SELECT_CC!"
)
;
case
Teak
::
SELECT_CC_Int_ICC
:
case
Teak
::
SELECT_CC_Int_ICC_i16
:
return
ExpandSelectCC
(
MI
,
BB
,
Teak
::
BRRCond_rel7
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> const MipsInstrInfo * MipsInstrInfo :: create ( MipsSubtarget & STI ) { if ( STI . inMips16Mode ( ) ) return createMips16InstrInfo ( STI ) ; return createMipsSEInstrInfo ( STI ) ; } </s>


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesAll ( ) ; AU . addRequired < PMLMachineFunctionImport > ( ) ; AU . addRequired < MachineBranchProbabilityInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> std :: pair < unsigned , const TargetRegisterClass * > SITargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { const TargetRegisterClass * RC = nullptr ; if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; case 's' : case 'r' : switch ( VT . getSizeInBits ( ) ) { default : return std :: make_pair ( 0U , nullptr ) ; case 32 : case 16 : RC = & AMDGPU :: SReg_32_XM0RegClass ; break ; case 64 : RC = & AMDGPU :: SGPR_64RegClass ; break ; case 96 : RC = & AMDGPU :: SReg_96RegClass ; break ; case 128 : RC = & AMDGPU :: SReg_128RegClass ; break ; case 160 : RC = & AMDGPU :: SReg_160RegClass ; break ; case 256 : RC = & AMDGPU :: SReg_256RegClass ; break ; case 512 : RC = & AMDGPU :: SReg_512RegClass ; break ; } break ; case 'v' : switch ( VT . getSizeInBits ( ) ) { default : return std :: make_pair ( 0U , nullptr ) ; case 32 : case 16 : RC = & AMDGPU :: VGPR_32RegClass ; break ; case 64 : RC = & AMDGPU :: VReg_64RegClass ; break ; case 96 : RC = & AMDGPU :: VReg_96RegClass ; break ; case 128 : RC = & AMDGPU :: VReg_128RegClass ; break ; case 160 : RC = & AMDGPU :: VReg_160RegClass ; break ; case 256 : RC = & AMDGPU :: VReg_256RegClass ; break ; case 512 : RC = & AMDGPU :: VReg_512RegClass ; break ; } break ; } if ( RC && ( isTypeLegal ( VT ) || VT . SimpleTy == MVT :: i128 || VT . SimpleTy == MVT :: i16 || VT . SimpleTy == MVT :: f16 ) ) return std :: make_pair ( 0U , RC ) ; } if ( Constraint . size ( ) > 1 ) { if ( Constraint [ 1 ] == 'v' ) { RC = & AMDGPU :: VGPR_32RegClass ; } else if ( Constraint [ 1 ] == 's' ) { RC = & AMDGPU :: SGPR_32RegClass ; } if ( RC ) { uint32_t Idx ; bool Failed = Constraint . substr ( 2 ) . getAsInteger ( 10 , Idx ) ; if ( ! Failed && Idx < RC -> getNumRegs ( ) ) return std :: make_pair ( RC -> getRegister ( Idx ) , RC ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> BitVector SPIRVRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
StringRef
getPassName
(
)
const
override
{
return
"AMDGPU Annotate Kernel Features"
;
}
</s>

getPassName - Return a nice clean name for a pass .

AMDGPU
"AMDGPU Annotate Kernel Features"


<s> void SystemZPassConfig :: addIRPasses ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createSystemZTDCPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> bool MipsSEInstrInfo :: isCopyInstrImpl ( const MachineInstr & MI , const MachineOperand * & Src , const MachineOperand * & Dest ) const { bool isDSPControlWrite = false ; if ( isReadOrWriteToDSPReg ( MI , isDSPControlWrite ) ) { if ( ! MI . getOperand ( 1 ) . isImm ( ) || MI . getOperand ( 1 ) . getImm ( ) != ( 1 << 4 ) ) return false ; else if ( isDSPControlWrite ) { Src = & MI . getOperand ( 0 ) ; Dest = & MI . getOperand ( 2 ) ; } else { Dest = & MI . getOperand ( 0 ) ; Src = & MI . getOperand ( 2 ) ; } return true ; } else if ( MI . isMoveReg ( ) || isORCopyInst ( MI ) ) { Dest = & MI . getOperand ( 0 ) ; Src = & MI . getOperand ( 1 ) ; return true ; } return false ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


<s> void WebAssemblyTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; } </s>

This method must be called before any actual lowering is done .


<s> int mep_register_move_cost ( machine_mode mode , enum reg_class from , enum reg_class to ) { if ( mep_have_copro_copro_moves_p && reg_class_subset_p ( from , CR_REGS ) && reg_class_subset_p ( to , CR_REGS ) ) { if ( TARGET_32BIT_CR_REGS && GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) return 4 ; return 2 ; } if ( reg_class_subset_p ( from , CR_REGS ) && reg_class_subset_p ( to , CR_REGS ) ) { if ( TARGET_32BIT_CR_REGS && GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) return 8 ; return 4 ; } if ( reg_class_subset_p ( from , CR_REGS ) || reg_class_subset_p ( to , CR_REGS ) ) { if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) return 4 ; return 2 ; } if ( mep_secondary_memory_needed ( from , to , mode ) ) return 1000 ; if ( MEP_NONGENERAL_CLASS ( from ) && MEP_NONGENERAL_CLASS ( to ) ) return 1000 ; if ( GET_MODE_SIZE ( mode ) > 4 ) return 4 ; return 2 ; } </s>

Implement REGISTER_MOVE_COST . Return 2 for direct single-register moves , 4 for direct double-register moves , and 1000 for anything that requires a temporary register or temporary stack slot .


"getBranchTarget21OpValue expects only expressions or immediates"

getBranchTarget21OpValue - Return binary encoding of the branch target operand .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LiveIntervals > ( ) ; AU . addPreserved < LiveIntervals > ( ) ; AU . addPreserved < SlotIndexes > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const override { ScheduleDAGMILive * DAG = createGenericSchedLive ( C ) ; DAG -> addMutation ( createLoadClusterDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; DAG -> addMutation ( createStoreClusterDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; DAG -> addMutation ( createAArch64MacroFusionDAGMutation ( ) ) ; return DAG ; } </s>

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level .


<s> static void lm32_option_override ( void ) { if ( ! TARGET_BARREL_SHIFT_ENABLED && ! TARGET_SIGN_EXTEND_ENABLED ) target_flags |= MASK_SIGN_EXTEND_ENABLED ; } </s>


"The ABI for passing parameters with %d-byte"

Gives the alignment boundary , in bits , of an argument with the specified mode and type .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"ARM MLA / MLS expansion pass"
;
}
</s>


The darwin64 ABI calls for us to recurse down through structs , looking for elements passed in registers . Unfortunately , we have to track int register count here also because of misalignments in powerpc alignment mode .


<s> void PIC16TargetLowering :: LowerOperationWrapper ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) { SDValue Op = SDValue ( N , 0 ) ; SDValue Res ; unsigned i ; switch ( Op . getOpcode ( ) ) { case ISD :: FORMAL_ARGUMENTS : Res = LowerFORMAL_ARGUMENTS ( Op , DAG ) ; break ; case ISD :: LOAD : Res = ExpandLoad ( Op . getNode ( ) , DAG ) ; break ; case ISD :: CALL : Res = LowerCALL ( Op , DAG ) ; break ; default : { Res = LowerOperation ( Op , DAG ) ; if ( Res . getNode ( ) ) Results . push_back ( Res ) ; return ; } } N = Res . getNode ( ) ; unsigned NumValues = N -> getNumValues ( ) ; for ( i = 0 ; i < NumValues ; i ++ ) { Results . push_back ( SDValue ( N , i ) ) ; } } </s>

This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> bool X86AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNo ) ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'a' : if ( MO . isImm ( ) ) { O << MO . getImm ( ) ; return false ; } if ( MO . isGlobal ( ) || MO . isCPI ( ) || MO . isJTI ( ) || MO . isSymbol ( ) ) { printSymbolOperand ( MO , O ) ; if ( Subtarget -> isPICStyleRIPRel ( ) ) O << "(%rip)" ; return false ; } if ( MO . isReg ( ) ) { O << '(' ; printOperand ( MI , OpNo , O ) ; O << ')' ; return false ; } return true ; case 'c' : if ( MO . isImm ( ) ) O << MO . getImm ( ) ; else if ( MO . isGlobal ( ) || MO . isCPI ( ) || MO . isJTI ( ) || MO . isSymbol ( ) ) printSymbolOperand ( MO , O ) ; else printOperand ( MI , OpNo , O ) ; return false ; case 'A' : if ( MO . isReg ( ) ) { O << '*' ; printOperand ( MI , OpNo , O ) ; return false ; } return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : if ( MO . isReg ( ) ) return printAsmMRegister ( MO , ExtraCode [ 0 ] , O ) ; printOperand ( MI , OpNo , O ) ; return false ; case 'P' : print_pcrel_imm ( MI , OpNo , O ) ; return false ; case 'n' : if ( MO . isImm ( ) ) { O << - MO . getImm ( ) ; return false ; } O << '-' ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


"loadRegFromStackSlot didn't insert any code!"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> unsigned X86InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case X86 :: MOV8mr : case X86 :: MOV16mr : case X86 :: MOV32mr : case X86 :: MOV64mr : case X86 :: ST_FpP64m : case X86 :: MOVSSmr : case X86 :: MOVSDmr : case X86 :: MOVAPSmr : case X86 :: MOVAPDmr : case X86 :: MOVDQAmr : case X86 :: MMX_MOVD64mr : case X86 :: MMX_MOVQ64mr : case X86 :: MMX_MOVNTQmr : if ( MI -> getOperand ( 0 ) . isFI ( ) && MI -> getOperand ( 1 ) . isImm ( ) && MI -> getOperand ( 2 ) . isReg ( ) && MI -> getOperand ( 3 ) . isImm ( ) && MI -> getOperand ( 1 ) . getImm ( ) == 1 && MI -> getOperand ( 2 ) . getReg ( ) == 0 && MI -> getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 0 ) . getIndex ( ) ; return MI -> getOperand ( X86AddrNumOperands ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> bool X86AvoidSFBPass :: alias ( const MachineMemOperand & Op1 , const MachineMemOperand & Op2 ) const { if ( ! Op1 . getValue ( ) || ! Op2 . getValue ( ) ) return true ; int64_t MinOffset = std :: min ( Op1 . getOffset ( ) , Op2 . getOffset ( ) ) ; int64_t Overlapa = Op1 . getSize ( ) + Op1 . getOffset ( ) - MinOffset ; int64_t Overlapb = Op2 . getSize ( ) + Op2 . getOffset ( ) - MinOffset ; return ! AA -> isNoAlias ( MemoryLocation ( Op1 . getValue ( ) , Overlapa , Op1 . getAAInfo ( ) ) , MemoryLocation ( Op2 . getValue ( ) , Overlapb , Op2 . getAAInfo ( ) ) ) ; } </s>

alias - If one of the pointers is to a global that we are tracking , and the other is some random pointer , we know there can not be an alias , because the address of the global is n't taken .


<s> static bool use_toc_relative_ref ( rtx sym , machine_mode mode ) { return ( ( constant_pool_expr_p ( sym ) && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( get_pool_constant ( sym ) , get_pool_mode ( sym ) ) ) || ( TARGET_CMODEL == CMODEL_MEDIUM && SYMBOL_REF_LOCAL_P ( sym ) && GET_MODE_SIZE ( mode ) <= POWERPC64_TOC_POINTER_ALIGNMENT ) ) ; } </s>

Return true iff the given SYMBOL_REF refers to a constant pool entry that we have put in the TOC , or for cmodel=medium , if the SYMBOL_REF can be addressed relative to the toc pointer .


<s>
void
dump
(
const
TargetRegisterInfo
*
TRI
,
int
depth
=
0
)
override
{
dumpDepth
(
depth
)
;
dbgs
(
)
<<
"Region: "
<<
(
void
*
)
Region
;
dbgs
(
)
<<
" In: "
<<
printReg
(
getBBSelectRegIn
(
)
,
TRI
)
;
dbgs
(
)
<<
", Out: "
<<
printReg
(
getBBSelectRegOut
(
)
,
TRI
)
<<
"\n"
;
dumpDepth
(
depth
)
;
if
(
getSucc
(
)
)
dbgs
(
)
<<
"Succ: "
<<
getSucc
(
)
->
getNumber
(
)
<<
"\n"
;
else
dbgs
(
)
<<
"Succ: none \n"
;
for
(
auto
MRTI
:
Children
)
{
MRTI
->
dump
(
TRI
,
depth
+
1
)
;
}
}
</s>

Dump the plan to stderr ( for debugging ) .

AMDGPU
0
"Region: "
" In: "
", Out: "
"\n"
"Succ: "
"\n"
"Succ: none \n"
1


"Instructions with multiple result values not implemented"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
void
SystemZHazardRecognizer
::
EmitInstruction
(
SUnit
*
SU
)
{
const
MCSchedClassDesc
*
SC
=
getSchedClass
(
SU
)
;
DEBUG
(
dbgs
(
)
<<
"++ HazardRecognizer emitting "
;
dumpSU
(
SU
,
dbgs
(
)
)
;
dbgs
(
)
<<
"\n"
;
)
;
DEBUG
(
dumpCurrGroup
(
"Decode group before emission"
)
;
)
;
if
(
!
fitsIntoCurrentGroup
(
SU
)
)
nextGroup
(
)
;
DEBUG
(
raw_string_ostream
cgd
(
CurGroupDbg
)
;
if
(
CurGroupDbg
.
length
(
)
)
cgd
<<
", "
;
dumpSU
(
SU
,
cgd
)
;
)
;
LastEmittedMI
=
SU
->
getInstr
(
)
;
if
(
SU
->
isCall
)
{
DEBUG
(
dbgs
(
)
<<
"++ Clearing state after call.\n"
;
)
;
Reset
(
)
;
LastEmittedMI
=
SU
->
getInstr
(
)
;
return
;
}
for
(
TargetSchedModel
::
ProcResIter
PI
=
SchedModel
->
getWriteProcResBegin
(
SC
)
,
PE
=
SchedModel
->
getWriteProcResEnd
(
SC
)
;
PI
!=
PE
;
++
PI
)
{
if
(
SchedModel
->
getProcResource
(
PI
->
ProcResourceIdx
)
->
BufferSize
==
1
)
continue
;
int
&
CurrCounter
=
ProcResourceCounters
[
PI
->
ProcResourceIdx
]
;
CurrCounter
+=
PI
->
Cycles
;
if
(
(
CurrCounter
>
ProcResCostLim
)
&&
(
CriticalResourceIdx
==
UINT_MAX
||
(
PI
->
ProcResourceIdx
!=
CriticalResourceIdx
&&
CurrCounter
>
ProcResourceCounters
[
CriticalResourceIdx
]
)
)
)
{
DEBUG
(
dbgs
(
)
<<
"++ New critical resource: "
<<
SchedModel
->
getProcResource
(
PI
->
ProcResourceIdx
)
->
Name
<<
"\n"
;
)
;
CriticalResourceIdx
=
PI
->
ProcResourceIdx
;
}
}
if
(
SU
->
isUnbuffered
)
{
LastFPdOpCycleIdx
=
getCurrCycleIdx
(
SU
)
;
DEBUG
(
dbgs
(
)
<<
"++ Last FPd cycle index: "
<<
LastFPdOpCycleIdx
<<
"\n"
;
)
;
}
CurrGroupSize
+=
getNumDecoderSlots
(
SU
)
;
assert
(
CurrGroupSize
<=
3
)
;
if
(
CurrGroupSize
==
3
||
SC
->
EndGroup
)
nextGroup
(
)
;
}
</s>

SystemZ
SystemZ
"++ HazardRecognizer emitting "
"\n"
"Decode group before emission"
", "
"++ Clearing state after call.\n"
1
"++ New critical resource: "
"\n"
"++ Last FPd cycle index: "
"\n"
3
3


<s> void FixupLEAPass :: processInstruction ( MachineBasicBlock :: iterator & I , MachineFunction :: iterator MFI ) { MachineInstr & MI = * I ; const MCInstrDesc & Desc = MI . getDesc ( ) ; int AddrOffset = X86II :: getMemoryOperandNo ( Desc . TSFlags ) ; if ( AddrOffset >= 0 ) { AddrOffset += X86II :: getOperandBias ( Desc ) ; MachineOperand & p = MI . getOperand ( AddrOffset + X86 :: AddrBaseReg ) ; if ( p . isReg ( ) && p . getReg ( ) != X86 :: ESP ) { seekLEAFixup ( p , I , MFI ) ; } MachineOperand & q = MI . getOperand ( AddrOffset + X86 :: AddrIndexReg ) ; if ( q . isReg ( ) && q . getReg ( ) != X86 :: ESP ) { seekLEAFixup ( q , I , MFI ) ; } } } </s>

Process a single instruction and collect debug info anchors .


<s> int neon_immediate_valid_for_shift ( rtx op , machine_mode mode , rtx * modconst , int * elementwidth , bool isleftshift ) { unsigned int innersize = GET_MODE_SIZE ( GET_MODE_INNER ( mode ) ) ; unsigned int n_elts = CONST_VECTOR_NUNITS ( op ) , i ; unsigned HOST_WIDE_INT last_elt = 0 ; unsigned HOST_WIDE_INT maxshift ; for ( i = 0 ; i < n_elts ; i ++ ) { rtx el = CONST_VECTOR_ELT ( op , i ) ; unsigned HOST_WIDE_INT elpart ; if ( CONST_INT_P ( el ) ) elpart = INTVAL ( el ) ; else if ( CONST_DOUBLE_P ( el ) ) return 0 ; else gcc_unreachable ( ) ; if ( i != 0 && elpart != last_elt ) return 0 ; last_elt = elpart ; } maxshift = innersize * 8 ; if ( isleftshift ) { if ( last_elt >= maxshift ) return 0 ; } else { if ( last_elt == 0 || last_elt > maxshift ) return 0 ; } if ( elementwidth ) * elementwidth = innersize * 8 ; if ( modconst ) * modconst = CONST_VECTOR_ELT ( op , 0 ) ; return 1 ; } </s>

Return TRUE if rtx OP is legal for use in a VSHR or VSHL instruction . If the immediate is valid , write a constant suitable for using as an operand to VSHR/VSHL to * MODCONST and the corresponding element width to * ELEMENTWIDTH . ISLEFTSHIFT is for determine left or right shift , because they have different limitations .


<s> void X86CmovConverterPass :: getAnalysisUsage ( AnalysisUsage & AU ) const { MachineFunctionPass :: getAnalysisUsage ( AU ) ; AU . addRequired < MachineLoopInfo > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
Kind
==
Register
&&
"Invalid type access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s> static void output_addr_reloc ( FILE * stream , rtx x , HOST_WIDE_INT add , const char * reloc ) { if ( * reloc ) { fputs ( reloc , stream ) ; fputc ( '(' , stream ) ; } output_addr_const ( stream , x ) ; if ( add ) { if ( add > 0 ) fputc ( '+' , stream ) ; fprintf ( stream , HOST_WIDE_INT_PRINT_DEC , add ) ; } if ( * reloc ) fputc ( ')' , stream ) ; } </s>


<s> void PPCIncomingValueHandler :: assignValueToReg ( Register ValVReg , Register PhysReg , CCValAssign & VA ) { markPhysRegUsed ( PhysReg ) ; IncomingValueHandler :: assignValueToReg ( ValVReg , PhysReg , VA ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> bool PIC16AsmPrinter :: doFinalization ( Module & M ) { printLibcallDecls ( ) ; DbgInfo . EmitVarDebugInfo ( M ) ; O << "\n\t" << ".EOF" ; O << "\n\t" << "END\n" ; bool Result = AsmPrinter :: doFinalization ( M ) ; return Result ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s>
BitVector
ARMBaseRegisterInfo
::
getReservedRegs
(
const
MachineFunction
&
MF
)
const
{
const
ARMSubtarget
&
STI
=
MF
.
getSubtarget
<
ARMSubtarget
>
(
)
;
const
ARMFrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
BitVector
Reserved
(
getNumRegs
(
)
)
;
markSuperRegs
(
Reserved
,
ARM
::
SP
)
;
markSuperRegs
(
Reserved
,
ARM
::
PC
)
;
markSuperRegs
(
Reserved
,
ARM
::
FPSCR
)
;
markSuperRegs
(
Reserved
,
ARM
::
APSR_NZCV
)
;
if
(
TFI
->
hasFP
(
MF
)
)
markSuperRegs
(
Reserved
,
getFramePointerReg
(
STI
)
)
;
if
(
hasBasePointer
(
MF
)
)
markSuperRegs
(
Reserved
,
BasePtr
)
;
if
(
STI
.
isR9Reserved
(
)
)
markSuperRegs
(
Reserved
,
ARM
::
R9
)
;
if
(
!
STI
.
hasD32
(
)
)
{
static_assert
(
ARM
::
D31
==
ARM
::
D16
+
15
,
"Register list not consecutive!"
)
;
for
(
unsigned
R
=
0
;
R
<
16
;
++
R
)
markSuperRegs
(
Reserved
,
ARM
::
D16
+
R
)
;
}
const
TargetRegisterClass
&
RC
=
ARM
::
GPRPairRegClass
;
for
(
unsigned
Reg
:
RC
)
for
(
MCSubRegIterator
SI
(
Reg
,
this
)
;
SI
.
isValid
(
)
;
++
SI
)
if
(
Reserved
.
test
(
*
SI
)
)
markSuperRegs
(
Reserved
,
Reg
)
;
assert
(
checkAllSuperRegsMarked
(
Reserved
)
)
;
return
Reserved
;
}
</s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
bool
runOnMachineFunction
(
MachineFunction
&
MF
)
override
{
PatmosSinglePathInfo
&
PSPI
=
getAnalysis
<
PatmosSinglePathInfo
>
(
)
;
bool
changed
=
false
;
if
(
PSPI
.
isConverting
(
MF
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"[Single-Path] Preparing "
<<
MF
.
getFunction
(
)
.
getName
(
)
<<
"\n"
)
;
doPrepareFunction
(
MF
)
;
changed
|=
true
;
}
return
changed
;
}
</s>

runOnMachineFunction - Emit the function body .

Patmos
Patmos
Patmos
"[Single-Path] Preparing "
"\n"


<s> void SystemZInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , Register SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned LoadOpcode , StoreOpcode ; getLoadStoreOpcodes ( RC , LoadOpcode , StoreOpcode ) ; addFrameReference ( BuildMI ( MBB , MBBI , DL , get ( StoreOpcode ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ; } </s>


<s> static bool tryAddingSymbolicOperand ( int64_t Value , bool isBranch , uint64_t Address , uint64_t Offset , uint64_t Width , MCInst & MI , const void * Decoder ) { const MCDisassembler * Dis = static_cast < const MCDisassembler * > ( Decoder ) ; return Dis -> tryAddingSymbolicOperand ( MI , Value , Address , isBranch , Offset , Width ) ; } </s>

Try to add a symbolic operand instead of Value to the MCInst .


"********** Cheap Definition Rematerializing **********\n"


<s>
const
CallLowering
*
AMDGPUSubtarget
::
getCallLowering
(
)
const
{
assert
(
GISel
&&
"Access to GlobalISel APIs not set"
)
;
return
GISel
->
getCallLowering
(
)
;
}
</s>

AMDGPU
AMDGPU
"Access to GlobalISel APIs not set"


<s> bool atIssueLimit ( ) const override { return true ; } </s>

atIssueLimit - Return true if no more instructions may be issued in this cycle .


<s> SDValue AArch64SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; ConstantSDNode * SizeValue = dyn_cast < ConstantSDNode > ( Size ) ; const AArch64Subtarget & STI = DAG . getMachineFunction ( ) . getSubtarget < AArch64Subtarget > ( ) ; const char * bzeroEntry = ( V && V -> isNullValue ( ) ) ? STI . getBZeroEntry ( ) : nullptr ; if ( bzeroEntry && ( ! SizeValue || SizeValue -> getZExtValue ( ) > 256 ) ) { const AArch64TargetLowering & TLI = * STI . getTargetLowering ( ) ; EVT IntPtr = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; Type * IntPtrTy = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroEntry , IntPtr ) , std :: move ( Args ) , 0 ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memset .


<s> unsigned AMDGPUAsmParser :: checkTargetMatchPredicate ( MCInst & Inst ) { uint64_t TSFlags = MII . get ( Inst . getOpcode ( ) ) . TSFlags ; if ( ( getForcedEncodingSize ( ) == 32 && ( TSFlags & SIInstrFlags :: VOP3 ) ) || ( getForcedEncodingSize ( ) == 64 && ! ( TSFlags & SIInstrFlags :: VOP3 ) ) || ( isForcedDPP ( ) && ! ( TSFlags & SIInstrFlags :: DPP ) ) || ( isForcedSDWA ( ) && ! ( TSFlags & SIInstrFlags :: SDWA ) ) ) return Match_InvalidOperand ; if ( ( TSFlags & SIInstrFlags :: VOP3 ) && ( TSFlags & SIInstrFlags :: VOPAsmPrefer32Bit ) && getForcedEncodingSize ( ) != 64 ) return Match_PreferE32 ; if ( Inst . getOpcode ( ) == AMDGPU :: V_MAC_F32_sdwa_vi || Inst . getOpcode ( ) == AMDGPU :: V_MAC_F16_sdwa_vi ) { auto OpNum = AMDGPU :: getNamedOperandIdx ( Inst . getOpcode ( ) , AMDGPU :: OpName :: dst_sel ) ; const auto & Op = Inst . getOperand ( OpNum ) ; if ( ! Op . isImm ( ) || Op . getImm ( ) != AMDGPU :: SDWA :: SdwaSel :: DWORD ) { return Match_InvalidOperand ; } } if ( ( TSFlags & SIInstrFlags :: FLAT ) && ! hasFlatOffsets ( ) ) { auto OpNum = AMDGPU :: getNamedOperandIdx ( Inst . getOpcode ( ) , AMDGPU :: OpName :: offset ) ; const auto & Op = Inst . getOperand ( OpNum ) ; if ( Op . getImm ( ) != 0 ) return Match_InvalidOperand ; } return Match_Success ; } </s>

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


<s> void tilegx_emit_conditional_branch ( rtx operands [ ] , machine_mode cmp_mode ) { rtx cmp_rtx = tilegx_emit_cc_test ( GET_CODE ( operands [ 0 ] ) , operands [ 1 ] , operands [ 2 ] , cmp_mode , false ) ; rtx branch_rtx = gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , cmp_rtx , gen_rtx_LABEL_REF ( VOIDmode , operands [ 3 ] ) , pc_rtx ) ) ; emit_jump_insn ( branch_rtx ) ; } </s>

Generate the comparison for a conditional branch .


<s> void SICInstrInfo :: adjustStackPtr ( unsigned SP , int64_t Amount , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned ADDR = SIC :: ADD ; unsigned SUBR = SIC :: SUB ; unsigned LDi = SIC :: LDi ; unsigned LDi4 = SIC :: LDi4 ; unsigned LDiL = SIC :: LDiL ; unsigned T = SIC :: T ; if ( isUInt < 20 > ( Amount ) ) { if ( isUInt < 12 > ( Amount ) ) { BuildMI ( MBB , I , DL , get ( LDi ) , T ) . addImm ( Amount ) ; } else { BuildMI ( MBB , I , DL , get ( LDi4 ) , T ) . addImm ( Amount ) ; } BuildMI ( MBB , I , DL , get ( ADDR ) , SP ) . addReg ( SP ) . addReg ( T ) ; } else if ( isUInt < 20 > ( - Amount ) ) { if ( isUInt < 12 > ( - Amount ) ) { BuildMI ( MBB , I , DL , get ( LDi ) , T ) . addImm ( - Amount ) ; } else { BuildMI ( MBB , I , DL , get ( LDi4 ) , T ) . addImm ( - Amount ) ; } BuildMI ( MBB , I , DL , get ( SUBR ) , SP ) . addReg ( SP ) . addReg ( T ) ; } else { BuildMI ( MBB , I , DL , get ( LDiL ) , T ) . addImm ( Amount ) ; BuildMI ( MBB , I , DL , get ( ADDR ) , SP ) . addReg ( SP ) . addReg ( T ) ; } } </s>


<s>
bool
SparcAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Operands
.
push_back
(
SparcOperand
::
CreateToken
(
Name
,
NameLoc
)
)
;
applyMnemonicAliases
(
Name
,
getAvailableFeatures
(
)
,
0
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
if
(
parseBranchModifiers
(
Operands
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
}
if
(
parseOperand
(
Operands
,
Name
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
||
getLexer
(
)
.
is
(
AsmToken
::
Plus
)
)
{
if
(
getLexer
(
)
.
is
(
AsmToken
::
Plus
)
)
{
Operands
.
push_back
(
SparcOperand
::
CreateToken
(
"+"
,
Parser
.
getTok
(
)
.
getLoc
(
)
)
)
;
}
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Sparc
Sparc
SparcOperand::CreateToken
0
"unexpected token"
"unexpected token"
SparcOperand::CreateToken
"+"
"unexpected token"
"unexpected token"


<s> bool X86AsmBackend :: allowAutoPadding ( ) const { return ( AlignBoundary != Align ( 1 ) && AlignBranchType != X86 :: AlignBranchNone ) ; } </s>

Return true if this target might automatically pad instructions and thus need to emit padding enable/disable directives around sensative code .


"builtin vec_step can only be used on vector types."

Expand builtins which can directly be mapped to tree expressions . LOC - location information FCODE - function code of the builtin ARGLIST - value supposed to be passed as arguments RETURN-TYPE - expected return type of the builtin


" (e.g. %<-mfloat-abi=softfp%> %<-mfpu=neon%>)"

"%Klane index must be a constant immediate"

Expand a Neon builtin , i.e . those registered only if TARGET_NEON holds . Most of these are `` special '' because they do n't have symbolic constants defined per-instruction or per instruction-variant . Instead , the required info is looked up in the table neon_builtin_data .


<s> static unsigned int arm_elf_section_type_flags ( tree decl , const char * name , int reloc ) { unsigned int flags = default_section_type_flags ( decl , name , reloc ) ; if ( decl && TREE_CODE ( decl ) == FUNCTION_DECL && target_pure_code ) flags |= SECTION_ARM_PURECODE ; return flags ; } </s>

Implements the TARGET_SECTION_FLAGS hook . If DECL is a function declaration and pure-code is passed as an option then add the SFH_ARM_PURECODE attribute to the section flags . NAME is the section 's name and RELOC indicates whether the declarations initializer may contain runtime relocations .


<s> static bool mips_return_in_msb ( const_tree valtype ) { if ( ! TARGET_NEWABI || ! TARGET_BIG_ENDIAN || ! AGGREGATE_TYPE_P ( valtype ) ) return false ; tree fields [ 2 ] ; bool has_cxx_zero_width_bf = false ; bool has_cxx17_empty_base = false ; return ( mips_fpr_return_fields ( valtype , fields , & has_cxx_zero_width_bf , & has_cxx17_empty_base ) == 0 || has_cxx_zero_width_bf ) ; } </s>

Implement TARGET_RETURN_IN_MSB . For n32 & n64 , we should return a value in the most significant part of $ 2/ $ 3 if : - the target is big-endian ; - the value has a structure or union type ( we generalize this to cover aggregates from other languages too ) ; and - the structure is not returned in floating-point registers .


<s> static void mips_avoid_hazard ( rtx_insn * after , rtx_insn * insn , int * hilo_delay , rtx * delayed_reg , rtx lo_reg , bool * fs_delay ) { rtx pattern , set ; int nops , ninsns ; pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) == ASM_INPUT || asm_noperands ( pattern ) >= 0 ) cfun -> machine -> all_noreorder_p = false ; ninsns = get_attr_length ( insn ) / 4 ; if ( ninsns == 0 ) return ; if ( * hilo_delay < 2 && reg_set_p ( lo_reg , pattern ) ) nops = 2 - * hilo_delay ; else if ( * delayed_reg != 0 && reg_referenced_p ( * delayed_reg , pattern ) ) nops = 1 ; else if ( * fs_delay && get_attr_can_delay ( insn ) == CAN_DELAY_NO && GET_CODE ( PATTERN ( after ) ) != SEQUENCE && GET_CODE ( pattern ) != ASM_INPUT && asm_noperands ( pattern ) < 0 ) nops = 1 ; else nops = 0 ; * hilo_delay += nops ; while ( nops -- > 0 ) emit_insn_after ( gen_hazard_nop ( ) , after ) ; * hilo_delay += ninsns ; * delayed_reg = 0 ; * fs_delay = false ; if ( INSN_CODE ( insn ) >= 0 ) switch ( get_attr_hazard ( insn ) ) { case HAZARD_NONE : break ; case HAZARD_FORBIDDEN_SLOT : if ( TARGET_CB_MAYBE ) * fs_delay = true ; break ; case HAZARD_HILO : * hilo_delay = 0 ; break ; case HAZARD_DELAY : set = single_set ( insn ) ; gcc_assert ( set ) ; * delayed_reg = SET_DEST ( set ) ; break ; } } </s>

Subroutine of mips_reorg . If there is a hazard between INSN and a previous instruction , avoid it by inserting nops after instruction AFTER . * DELAYED_REG and * HILO_DELAY describe the hazards that apply at this point . If * DELAYED_REG is non-null , INSN must wait a cycle before using the value of that register . * HILO_DELAY counts the number of instructions since the last hilo hazard ( that is , the number of instructions since the last mflo or mfhi ) . After inserting nops for INSN , update * DELAYED_REG and * HILO_DELAY for the next instruction . LO_REG is an rtx for the LO register , used in dependence checking .


<s> static int get_max_pos ( state_t state ) { if ( cpu_unit_reservation_p ( state , pos_6 ) ) return 6 ; else if ( cpu_unit_reservation_p ( state , pos_5 ) ) return 5 ; else if ( cpu_unit_reservation_p ( state , pos_4 ) ) return 4 ; else if ( cpu_unit_reservation_p ( state , pos_3 ) ) return 3 ; else if ( cpu_unit_reservation_p ( state , pos_2 ) ) return 2 ; else if ( cpu_unit_reservation_p ( state , pos_1 ) ) return 1 ; else return 0 ; } </s>

The following function returns position in the two window bundle for given STATE .


<s> TargetPassConfig * X86TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new X86PassConfig ( this , PM , Subtarget . is64Bit ( ) ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> bool HexagonInstrInfo :: isPredicated ( unsigned Opcode ) const { const uint64_t F = get ( Opcode ) . TSFlags ; return ( F >> HexagonII :: PredicatedPos ) & HexagonII :: PredicatedMask ; } </s>

Returns true if the instruction is already predicated .

Hexagon Hexagon HexagonII::PredicatedPos HexagonII::PredicatedMask


<s> const TargetRegisterClass * getPointerRegClass ( const MachineFunction & MF , unsigned Kind = 0 ) const override { return & Patmos :: RRegsRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesAll ( ) ; AU . addRequired < PatmosCallGraphBuilder > ( ) ; AU . addRequired < PatmosStackCacheAnalysisInfo > ( ) ; ModulePass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static tree def_builtin ( const char * name , enum bpf_builtins code , tree type ) { tree t = add_builtin_function ( name , type , code , BUILT_IN_MD , NULL , NULL_TREE ) ; bpf_builtins [ code ] = t ; return t ; } </s>

Add a SPARC builtin function with NAME , ICODE , CODE and TYPE . Return the function decl or NULL_TREE if the builtin was not added .


<s> static bool ix86_expand_vector_init_one_var ( bool mmx_ok , machine_mode mode , rtx target , rtx vals , int one_var ) { rtx var = XVECEXP ( vals , 0 , one_var ) ; machine_mode wmode ; rtx const_vec , x ; const_vec = copy_rtx ( vals ) ; XVECEXP ( const_vec , 0 , one_var ) = CONST0_RTX ( GET_MODE_INNER ( mode ) ) ; const_vec = gen_rtx_CONST_VECTOR ( mode , XVEC ( const_vec , 0 ) ) ; switch ( mode ) { case E_V2DFmode : case E_V2DImode : case E_V2SFmode : case E_V2SImode : return false ; case E_V4DImode : if ( ! TARGET_64BIT ) return false ; case E_V8HFmode : case E_V16HFmode : case E_V4DFmode : case E_V8SFmode : case E_V8SImode : case E_V16HImode : case E_V32QImode : case E_V4SFmode : case E_V4SImode : case E_V8HImode : case E_V4HImode : break ; case E_V16QImode : if ( TARGET_SSE4_1 ) break ; wmode = V8HImode ; goto widen ; case E_V8QImode : if ( TARGET_MMX_WITH_SSE && TARGET_SSE4_1 ) break ; wmode = V4HImode ; goto widen ; case E_V4QImode : if ( TARGET_SSE4_1 ) break ; wmode = V2HImode ; widen : x = XVECEXP ( vals , 0 , one_var ^ 1 ) ; if ( one_var & 1 ) { var = convert_modes ( HImode , QImode , var , true ) ; var = expand_simple_binop ( HImode , ASHIFT , var , GEN_INT ( 8 ) , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; x = GEN_INT ( INTVAL ( x ) & 0xff ) ; } else { var = convert_modes ( HImode , QImode , var , true ) ; x = gen_int_mode ( UINTVAL ( x ) << 8 , HImode ) ; } if ( x != const0_rtx ) var = expand_simple_binop ( HImode , IOR , var , x , var , 1 , OPTAB_LIB_WIDEN ) ; x = gen_reg_rtx ( wmode ) ; emit_move_insn ( x , gen_lowpart ( wmode , const_vec ) ) ; ix86_expand_vector_set ( mmx_ok , x , var , one_var >> 1 ) ; emit_move_insn ( target , gen_lowpart ( mode , x ) ) ; return true ; default : return false ; } emit_move_insn ( target , const_vec ) ; ix86_expand_vector_set ( mmx_ok , target , var , one_var ) ; return true ; } </s>

A subroutine of ix86_expand_vector_init . Store into TARGET a vector consisting of the values in VALS . It is known that all elements except ONE_VAR are constants . Return true if successful .


<s> void sparc_expand_vector_init ( rtx target , rtx vals ) { const machine_mode mode = GET_MODE ( target ) ; const machine_mode inner_mode = GET_MODE_INNER ( mode ) ; const int n_elts = GET_MODE_NUNITS ( mode ) ; int i , n_var = 0 ; bool all_same ; rtx mem ; all_same = true ; for ( i = 0 ; i < n_elts ; i ++ ) { rtx x = XVECEXP ( vals , 0 , i ) ; if ( ! CONSTANT_P ( x ) ) n_var ++ ; if ( i > 0 && ! rtx_equal_p ( x , XVECEXP ( vals , 0 , 0 ) ) ) all_same = false ; } if ( n_var == 0 ) { emit_move_insn ( target , gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , 0 ) ) ) ; return ; } if ( GET_MODE_SIZE ( inner_mode ) == GET_MODE_SIZE ( mode ) ) { if ( GET_MODE_SIZE ( inner_mode ) == 4 ) { emit_move_insn ( gen_lowpart ( SImode , target ) , gen_lowpart ( SImode , XVECEXP ( vals , 0 , 0 ) ) ) ; return ; } else if ( GET_MODE_SIZE ( inner_mode ) == 8 ) { emit_move_insn ( gen_lowpart ( DImode , target ) , gen_lowpart ( DImode , XVECEXP ( vals , 0 , 0 ) ) ) ; return ; } } else if ( GET_MODE_SIZE ( inner_mode ) == GET_MODE_SIZE ( word_mode ) && GET_MODE_SIZE ( mode ) == 2 * GET_MODE_SIZE ( word_mode ) ) { emit_move_insn ( gen_highpart ( word_mode , target ) , gen_lowpart ( word_mode , XVECEXP ( vals , 0 , 0 ) ) ) ; emit_move_insn ( gen_lowpart ( word_mode , target ) , gen_lowpart ( word_mode , XVECEXP ( vals , 0 , 1 ) ) ) ; return ; } if ( all_same && GET_MODE_SIZE ( mode ) == 8 ) { if ( TARGET_VIS2 ) { vector_init_bshuffle ( target , XVECEXP ( vals , 0 , 0 ) , mode , inner_mode ) ; return ; } if ( mode == V8QImode ) { vector_init_fpmerge ( target , XVECEXP ( vals , 0 , 0 ) ) ; return ; } if ( mode == V4HImode ) { vector_init_faligndata ( target , XVECEXP ( vals , 0 , 0 ) ) ; return ; } } mem = assign_stack_temp ( mode , GET_MODE_SIZE ( mode ) ) ; for ( i = 0 ; i < n_elts ; i ++ ) emit_move_insn ( adjust_address_nv ( mem , inner_mode , i * GET_MODE_SIZE ( inner_mode ) ) , XVECEXP ( vals , 0 , i ) ) ; emit_move_insn ( target , mem ) ; } </s>

Emit code to initialize TARGET to values for individual fields VALS .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { ForCodeSize = MF . getFunction ( ) . hasFnAttribute ( Attribute :: OptimizeForSize ) || MF . getFunction ( ) . hasFnAttribute ( Attribute :: MinSize ) ; Subtarget = & MF . getSubtarget < WebAssemblySubtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool ia64_expand_load_address ( rtx dest , rtx src ) { gcc_assert ( GET_CODE ( dest ) == REG ) ; if ( GET_MODE ( dest ) != Pmode ) dest = gen_rtx_REG_offset ( dest , Pmode , REGNO ( dest ) , byte_lowpart_offset ( Pmode , GET_MODE ( dest ) ) ) ; if ( TARGET_NO_PIC ) return false ; if ( small_addr_symbolic_operand ( src , VOIDmode ) ) return false ; if ( TARGET_AUTO_PIC ) emit_insn ( gen_load_gprel64 ( dest , src ) ) ; else if ( GET_CODE ( src ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( src ) ) emit_insn ( gen_load_fptr ( dest , src ) ) ; else if ( sdata_symbolic_operand ( src , VOIDmode ) ) emit_insn ( gen_load_gprel ( dest , src ) ) ; else { HOST_WIDE_INT addend = 0 ; rtx tmp ; if ( GET_CODE ( src ) == CONST ) { HOST_WIDE_INT hi , lo ; hi = INTVAL ( XEXP ( XEXP ( src , 0 ) , 1 ) ) ; lo = ( ( hi & 0x3fff ) ^ 0x2000 ) - 0x2000 ; hi = hi - lo ; if ( lo != 0 ) { addend = lo ; src = plus_constant ( Pmode , XEXP ( XEXP ( src , 0 ) , 0 ) , hi ) ; } } tmp = gen_rtx_HIGH ( Pmode , src ) ; tmp = gen_rtx_PLUS ( Pmode , tmp , pic_offset_table_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , tmp ) ) ; tmp = gen_rtx_LO_SUM ( Pmode , gen_const_mem ( Pmode , dest ) , src ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , tmp ) ) ; if ( addend ) { tmp = gen_rtx_PLUS ( Pmode , dest , GEN_INT ( addend ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , tmp ) ) ; } } return true ; } </s>


<s>
void
XtensaDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
llvm
::
dbgs
(
)
<<
"Attempting to do a select\n"
;
Node
->
dump
(
CurDAG
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;
return
;
}
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
switch
(
Opcode
)
{
default
:
break
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

Xtensa
Xtensa
"Attempting to do a select\n"
"== "


<s> void M680x0PassConfig :: addPreEmitPass ( ) { addPass ( createM680x0CollapseMOVEMPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> unsigned MipsTargetLowering :: getVectorTypeBreakdownForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT , EVT & IntermediateVT , unsigned & NumIntermediates , MVT & RegisterVT ) const { RegisterVT = getRegisterTypeForCallingConv ( Context , CC , VT ) ; IntermediateVT = RegisterVT ; NumIntermediates = VT . getFixedSizeInBits ( ) < RegisterVT . getFixedSizeInBits ( ) ? VT . getVectorNumElements ( ) : VT . getSizeInBits ( ) / RegisterVT . getSizeInBits ( ) ; return NumIntermediates ; } </s>

Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts .


<s> void BPFPassConfig :: addPreEmitPass ( ) { addPass ( createBPFMIPreEmitCheckingPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) if ( ! DisableMIPeephole ) addPass ( createBPFMIPreEmitPeepholePass ( ) ) ; } </s>


"%s expects a compile time integer constant"

"%s expects a compile time long integer constant"

"rounding to %d bits has no effect for "

"fixed-point value with %d fractional bits"

Expand an expression EXP that calls a built-in function , with result going to TARGET if that 's convenient ( and in mode MODE if that 's convenient ) . SUBTARGET may be used as the target for computing one of EXP 's operands . IGNORE is nonzero if the value is to be ignored .


<s> static machine_mode s390_cc_modes_compatible ( machine_mode m1 , machine_mode m2 ) { if ( m1 == m2 ) return m1 ; switch ( m1 ) { case CCZmode : if ( m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode ) return m2 ; return VOIDmode ; case CCSmode : case CCUmode : case CCTmode : case CCSRmode : case CCURmode : case CCZ1mode : if ( m2 == CCZmode ) return m1 ; return VOIDmode ; default : return VOIDmode ; } return VOIDmode ; } </s>

If two condition code modes are compatible , return a condition code mode which is compatible with both . Otherwise , return VOIDmode .


<s> static void nvptx_goacc_reduction_fini ( gcall * call , offload_attrs * oa ) { gimple_stmt_iterator gsi = gsi_for_stmt ( call ) ; tree lhs = gimple_call_lhs ( call ) ; tree ref_to_res = gimple_call_arg ( call , 1 ) ; tree var = gimple_call_arg ( call , 2 ) ; int level = TREE_INT_CST_LOW ( gimple_call_arg ( call , 3 ) ) ; enum tree_code op = ( enum tree_code ) TREE_INT_CST_LOW ( gimple_call_arg ( call , 4 ) ) ; gimple_seq seq = NULL ; tree r = NULL_TREE ; ; push_gimplify_context ( true ) ; if ( level == GOMP_DIM_VECTOR && oa -> vector_length == PTX_WARP_SIZE ) { for ( int shfl = PTX_WARP_SIZE / 2 ; shfl > 0 ; shfl = shfl >> 1 ) { tree other_var = make_ssa_name ( TREE_TYPE ( var ) ) ; nvptx_generate_vector_shuffle ( gimple_location ( call ) , other_var , var , shfl , & seq ) ; r = make_ssa_name ( TREE_TYPE ( var ) ) ; gimplify_assign ( r , fold_build2 ( op , TREE_TYPE ( var ) , var , other_var ) , & seq ) ; var = r ; } } else { tree accum = NULL_TREE ; if ( level == GOMP_DIM_WORKER || level == GOMP_DIM_VECTOR ) { tree offset = gimple_call_arg ( call , 5 ) ; tree call = nvptx_get_shared_red_addr ( TREE_TYPE ( var ) , offset , level == GOMP_DIM_VECTOR ) ; tree ptr = make_ssa_name ( TREE_TYPE ( call ) ) ; gimplify_assign ( ptr , call , & seq ) ; accum = ptr ; } else if ( integer_zerop ( ref_to_res ) ) r = var ; else accum = ref_to_res ; if ( accum ) { gsi_insert_seq_before ( & gsi , seq , GSI_SAME_STMT ) ; seq = NULL ; r = nvptx_reduction_update ( gimple_location ( call ) , & gsi , accum , var , op , level ) ; } } if ( lhs ) gimplify_assign ( lhs , r , & seq ) ; pop_gimplify_context ( NULL ) ; gsi_replace_with_seq ( & gsi , seq , true ) ; } </s>

NVPTX implementation of GOACC_REDUCTION_FINI .


<s> static enum mips_shadow_set mips_use_shadow_register_set ( tree type ) { tree attr = lookup_attribute ( "use_shadow_register_set" , TYPE_ATTRIBUTES ( type ) ) ; tree args ; if ( attr == NULL ) return SHADOW_SET_NO ; args = TREE_VALUE ( attr ) ; if ( args == NULL ) return SHADOW_SET_YES ; return SHADOW_SET_INTSTACK ; } </s>

Return the mips_shadow_set if the `` use_shadow_register_set '' attribute is set for a function .


<s>
bool
GCNDPPCombine
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
auto
&
ST
=
MF
.
getSubtarget
<
GCNSubtarget
>
(
)
;
if
(
!
ST
.
hasDPP
(
)
||
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
MRI
=
&
MF
.
getRegInfo
(
)
;
TII
=
ST
.
getInstrInfo
(
)
;
assert
(
MRI
->
isSSA
(
)
&&
"Must be run on SSA"
)
;
bool
Changed
=
false
;
for
(
auto
&
MBB
:
MF
)
{
for
(
auto
I
=
MBB
.
rbegin
(
)
,
E
=
MBB
.
rend
(
)
;
I
!=
E
;
)
{
auto
&
MI
=
*
I
++
;
if
(
MI
.
getOpcode
(
)
==
AMDGPU
::
V_MOV_B32_dpp
&&
combineDPPMov
(
MI
)
)
{
Changed
=
true
;
++
NumDPPMovsCombined
;
}
}
}
return
Changed
;
}
</s>

AMDGPU
"Must be run on SSA"
AMDGPU::V_MOV_B32_dpp


<s> static void cr16_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int l = GET_MODE_BITSIZE ( arg . mode ) / BITS_PER_WORD ; if ( ! cum -> last_parm_in_reg ) return ; if ( targetm . calls . must_pass_in_stack ( arg ) || ( cum -> ints < 0 ) ) return ; if ( ( arg . mode == SImode ) || ( arg . mode == HImode ) || ( arg . mode == QImode ) || ( arg . mode == DImode ) ) { if ( l <= 1 ) cum -> ints += 1 ; else cum -> ints += l ; } else if ( ( arg . mode == SFmode ) || ( arg . mode == DFmode ) ) cum -> ints += l ; else if ( arg . mode == BLKmode ) { if ( ( l = enough_regs_for_param ( cum , arg . type , arg . mode ) ) != 0 ) cum -> ints += l ; } return ; } </s>

Implements the macro FUNCTION_ARG_ADVANCE defined in cr16.h .


<s> void GCNPassConfig :: addOptimizedRegAlloc ( ) { insertPass ( & MachineSchedulerID , & SIWholeQuadModeID ) ; insertPass ( & MachineSchedulerID , & SIPreAllocateWWMRegsID ) ; if ( OptExecMaskPreRA ) insertPass ( & MachineSchedulerID , & SIOptimizeExecMaskingPreRAID ) ; if ( isPassEnabled ( EnablePreRAOptimizations ) ) insertPass ( & RenameIndependentSubregsID , & GCNPreRAOptimizationsID ) ; if ( TM -> getOptLevel ( ) > CodeGenOpt :: Less ) insertPass ( & MachineSchedulerID , & SIFormMemoryClausesID ) ; if ( OptVGPRLiveRange ) insertPass ( & LiveVariablesID , & SIOptimizeVGPRLiveRangeID , false ) ; insertPass ( & PHIEliminationID , & SILowerControlFlowID , false ) ; if ( EnableDCEInRA ) insertPass ( & DetectDeadLanesID , & DeadMachineInstructionElimID ) ; TargetPassConfig :: addOptimizedRegAlloc ( ) ; } </s>

addOptimizedRegAlloc - Add passes related to register allocation .


<s> void addEdge ( SCANode * src , SCANode * dst , const MachineBasicBlock * MBB , unsigned index ) { E . push_back ( new SCAEdge ( src -> yId , dst -> yId , MBB -> getName ( ) , index , MBB -> getNumber ( ) ) ) ; } </s>

Add a DAG edge to the given SU with the given predecessor dependence data .


<s> static void paired_emit_vector_compare ( enum rtx_code rcode , rtx dest , rtx op0 , rtx op1 , rtx cc_op0 , rtx cc_op1 ) { rtx tmp = gen_reg_rtx ( V2SFmode ) ; rtx tmp1 , max , min ; gcc_assert ( TARGET_PAIRED_FLOAT ) ; gcc_assert ( GET_MODE ( op0 ) == GET_MODE ( op1 ) ) ; switch ( rcode ) { case LT : case LTU : paired_emit_vector_compare ( GE , dest , op1 , op0 , cc_op0 , cc_op1 ) ; return ; case GE : case GEU : emit_insn ( gen_subv2sf3 ( tmp , cc_op0 , cc_op1 ) ) ; emit_insn ( gen_selv2sf4 ( dest , tmp , op0 , op1 , CONST0_RTX ( SFmode ) ) ) ; return ; case LE : case LEU : paired_emit_vector_compare ( GE , dest , op0 , op1 , cc_op1 , cc_op0 ) ; return ; case GT : paired_emit_vector_compare ( LE , dest , op1 , op0 , cc_op0 , cc_op1 ) ; return ; case EQ : tmp1 = gen_reg_rtx ( V2SFmode ) ; max = gen_reg_rtx ( V2SFmode ) ; min = gen_reg_rtx ( V2SFmode ) ; gen_reg_rtx ( V2SFmode ) ; emit_insn ( gen_subv2sf3 ( tmp , cc_op0 , cc_op1 ) ) ; emit_insn ( gen_selv2sf4 ( max , tmp , cc_op0 , cc_op1 , CONST0_RTX ( SFmode ) ) ) ; emit_insn ( gen_subv2sf3 ( tmp , cc_op1 , cc_op0 ) ) ; emit_insn ( gen_selv2sf4 ( min , tmp , cc_op0 , cc_op1 , CONST0_RTX ( SFmode ) ) ) ; emit_insn ( gen_subv2sf3 ( tmp1 , min , max ) ) ; emit_insn ( gen_selv2sf4 ( dest , tmp1 , op0 , op1 , CONST0_RTX ( SFmode ) ) ) ; return ; case NE : paired_emit_vector_compare ( EQ , dest , op1 , op0 , cc_op0 , cc_op1 ) ; return ; case UNLE : paired_emit_vector_compare ( LE , dest , op1 , op0 , cc_op0 , cc_op1 ) ; return ; case UNLT : paired_emit_vector_compare ( LT , dest , op1 , op0 , cc_op0 , cc_op1 ) ; return ; case UNGE : paired_emit_vector_compare ( GE , dest , op1 , op0 , cc_op0 , cc_op1 ) ; return ; case UNGT : paired_emit_vector_compare ( GT , dest , op1 , op0 , cc_op0 , cc_op1 ) ; return ; default : gcc_unreachable ( ) ; } return ; } </s>

Emit vector compare for code RCODE . DEST is destination , OP1 and OP2 are two VEC_COND_EXPR operands , CC_OP0 and CC_OP1 are the two operands for the relation operation COND . This is a recursive function .


<s> unsigned XCoreRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; return TFI -> hasFP ( MF ) ? XCore :: R10 : XCore :: SP ; } </s>


<s> static rtx gen_rx_rtsd_vector ( unsigned int adjust , unsigned int low , unsigned int high ) { unsigned int i ; unsigned int bias = 3 ; unsigned int count = ( high - low ) + bias ; rtx vector ; vector = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; XVECEXP ( vector , 0 , 0 ) = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , adjust ) ) ; for ( i = 0 ; i < count - 2 ; i ++ ) XVECEXP ( vector , 0 , i + 1 ) = gen_rtx_SET ( VOIDmode , gen_rtx_REG ( SImode , low + i ) , gen_rtx_MEM ( SImode , i == 0 ? stack_pointer_rtx : plus_constant ( Pmode , stack_pointer_rtx , i * UNITS_PER_WORD ) ) ) ; XVECEXP ( vector , 0 , count - 1 ) = ret_rtx ; return vector ; } </s>

Generate a PARALLEL which will satisfy the rx_rtsd_vector predicate .


<s> bool PPCAIXAsmPrinter :: doFinalization ( Module & M ) { if ( ! MAI -> usesDwarfFileAndLocDirectives ( ) && MMI -> hasDebugInfo ( ) ) OutStreamer -> doFinalizationAtSectionEnd ( OutStreamer -> getContext ( ) . getObjectFileInfo ( ) -> getTextSection ( ) ) ; for ( MCSymbol * Sym : ExtSymSDNodeSymbols ) OutStreamer -> emitSymbolAttribute ( Sym , MCSA_Extern ) ; return PPCAsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> Optional < MCFixupKind > MipsAsmBackend :: getFixupKind ( StringRef Name ) const { return StringSwitch < Optional < MCFixupKind >> ( Name ) . Case ( "R_MIPS_NONE" , ( MCFixupKind ) Mips :: fixup_Mips_NONE ) . Case ( "R_MIPS_32" , FK_Data_4 ) . Default ( MCAsmBackend :: getFixupKind ( Name ) ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> static rtx frv_legitimize_argument ( enum insn_code icode , int opnum , rtx arg ) { enum machine_mode mode = insn_data [ icode ] . operand [ opnum ] . mode ; if ( ( * insn_data [ icode ] . operand [ opnum ] . predicate ) ( arg , mode ) ) return arg ; else return copy_to_mode_reg ( mode , arg ) ; } </s>

Given that ARG is being passed as operand OPNUM to instruction ICODE , check whether ARG satisfies the operand 's constraints . If it does n't , copy ARG to a temporary register and return that . Otherwise return ARG itself .


<s> unsigned X86AsmBackend :: getMaximumNopSize ( const MCSubtargetInfo & STI ) const { if ( STI . hasFeature ( X86 :: Is16Bit ) ) return 4 ; if ( ! STI . hasFeature ( X86 :: FeatureNOPL ) && ! STI . hasFeature ( X86 :: Is64Bit ) ) return 1 ; if ( STI . getFeatureBits ( ) [ X86 :: TuningFast7ByteNOP ] ) return 7 ; if ( STI . getFeatureBits ( ) [ X86 :: TuningFast15ByteNOP ] ) return 15 ; if ( STI . getFeatureBits ( ) [ X86 :: TuningFast11ByteNOP ] ) return 11 ; return 10 ; } </s>

Returns the maximum size of a nop in bytes on this target .


<s> bool isMem ( ) const override { return false ; } </s>


<s> int get_ta ( rtx ta ) { if ( INTVAL ( ta ) == TAIL_ANY ) return INVALID_ATTRIBUTE ; return INTVAL ( ta ) ; } </s>

Get ta according to operand [ tail_op_idx ] .


<s>
void
final_prescan_insn
(
rtx_insn
*
insn
,
rtx
*
operand
ATTRIBUTE_UNUSED
,
int
num_operands
ATTRIBUTE_UNUSED
)
{
static
int
last_insn_address
=
0
;
const
int
uid
=
INSN_UID
(
insn
)
;
if
(
TARGET_ADDRESSES
)
{
fprintf
(
asm_out_file
,
"; 0x%x %d\n"
,
INSN_ADDRESSES
(
uid
)
,
INSN_ADDRESSES
(
uid
)
last_insn_address
)
;
last_insn_address
=
INSN_ADDRESSES
(
uid
)
;
}
}
</s>

If defined , a C statement to be executed just prior to the output of assembler code for INSN , to modify the extracted operands so they will be output differently . Here the argument OPVEC is the vector containing the operands extracted from INSN , and NOPERANDS is the number of elements of the vector which contain meaningful data for this insn . The contents of this vector are what will be used to convert the insn template into assembler code , so you can change the assembler output by changing the contents of the vector . We use it to check if the current insn needs a nop in front of it because of load delays , and also to update the delay slot statistics .


<s> static const char * rs6000_xcoff_strip_name_encoding ( const char * name ) { size_t len ; if ( * name == '*' ) name ++ ; len = strlen ( name ) ; if ( name [ len - 1 ] == ']' ) return ggc_alloc_string ( name , len - 4 ) ; else return name ; } </s>

Remove any trailing [ DS ] or the like from the symbol name .


<s> StringRef getPassName ( ) const override { return PassDescription ; } </s>

getPassName - Return a nice clean name for a pass .


<s> static bool avr_legitimate_combined_insn ( rtx_insn * insn ) { subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , NONCONST ) { const_rtx op = * iter ; if ( SUBREG_P ( op ) && MEM_P ( SUBREG_REG ( op ) ) && ( GET_MODE_SIZE ( GET_MODE ( op ) ) > GET_MODE_SIZE ( GET_MODE ( SUBREG_REG ( op ) ) ) ) ) { return false ; } } return true ; } </s>

PR78883 : Filter out paradoxical SUBREGs of MEM which are not handled properly by following passes . As INSN_SCHEDULING is off and hence general_operand accepts such expressions , ditch them now .


<s> static bool aarch64_base_register_rtx_p ( rtx x , bool strict_p ) { if ( ! strict_p && SUBREG_P ( x ) && contains_reg_of_mode [ GENERAL_REGS ] [ GET_MODE ( SUBREG_REG ( x ) ) ] ) x = SUBREG_REG ( x ) ; return ( REG_P ( x ) && aarch64_regno_ok_for_base_p ( REGNO ( x ) , strict_p ) ) ; } </s>

Return true if X is a valid base register for mode MODE . STRICT_P is true if REG_OK_STRICT is in effect .


<s> unsigned LanaiInstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . getOpcode ( ) == Lanai :: LDW_RI ) { unsigned Reg ; if ( ( Reg = isLoadFromStackSlot ( MI , FrameIndex ) ) ) return Reg ; SmallVector < const MachineMemOperand * , 1 > Accesses ; if ( hasLoadFromStackSlot ( MI , Accesses ) ) { FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) -> getFrameIndex ( ) ; return 1 ; } } return 0 ; } </s>

isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s> rtx legitimize_pe_coff_symbol ( rtx addr , bool inreg ) { if ( ! TARGET_PECOFF ) return NULL_RTX ; if ( TARGET_DLLIMPORT_DECL_ATTRIBUTES ) { if ( GET_CODE ( addr ) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P ( addr ) ) return legitimize_dllimport_symbol ( addr , inreg ) ; if ( GET_CODE ( addr ) == CONST && GET_CODE ( XEXP ( addr , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) ) { rtx t = legitimize_dllimport_symbol ( XEXP ( XEXP ( addr , 0 ) , 0 ) , inreg ) ; return gen_rtx_PLUS ( Pmode , t , XEXP ( XEXP ( addr , 0 ) , 1 ) ) ; } } if ( ix86_cmodel != CM_LARGE_PIC && ix86_cmodel != CM_MEDIUM_PIC ) return NULL_RTX ; if ( GET_CODE ( addr ) == SYMBOL_REF && ! is_imported_p ( addr ) && SYMBOL_REF_EXTERNAL_P ( addr ) && SYMBOL_REF_DECL ( addr ) ) return legitimize_pe_coff_extern_decl ( addr , inreg ) ; if ( GET_CODE ( addr ) == CONST && GET_CODE ( XEXP ( addr , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) == SYMBOL_REF && ! is_imported_p ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) && SYMBOL_REF_EXTERNAL_P ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) && SYMBOL_REF_DECL ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) ) { rtx t = legitimize_pe_coff_extern_decl ( XEXP ( XEXP ( addr , 0 ) , 0 ) , inreg ) ; return gen_rtx_PLUS ( Pmode , t , XEXP ( XEXP ( addr , 0 ) , 1 ) ) ; } return NULL_RTX ; } </s>

Expand SYMBOL into its corresponding dllimport or refptr symbol . WANT_REG is true if we require the result be a register .


<s> void Thumb2InstrInfo :: ReplaceTailWithBranchTo ( MachineBasicBlock :: iterator Tail , MachineBasicBlock * NewDest ) const { MachineBasicBlock * MBB = Tail -> getParent ( ) ; ARMFunctionInfo * AFI = MBB -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; if ( ! AFI -> hasITBlocks ( ) || Tail -> isBranch ( ) ) { TargetInstrInfo :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; return ; } unsigned PredReg = 0 ; ARMCC :: CondCodes CC = getInstrPredicate ( * Tail , PredReg ) ; MachineBasicBlock :: iterator MBBI = Tail ; if ( CC != ARMCC :: AL ) -- MBBI ; TargetInstrInfo :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; if ( CC != ARMCC :: AL ) { MachineBasicBlock :: iterator E = MBB -> begin ( ) ; unsigned Count = 4 ; while ( Count && MBBI != E ) { if ( MBBI -> isDebugInstr ( ) ) { -- MBBI ; continue ; } if ( MBBI -> getOpcode ( ) == ARM :: t2IT ) { unsigned Mask = MBBI -> getOperand ( 1 ) . getImm ( ) ; if ( Count == 4 ) MBBI -> eraseFromParent ( ) ; else { unsigned MaskOn = 1 << Count ; unsigned MaskOff = ~ ( MaskOn - 1 ) ; MBBI -> getOperand ( 1 ) . setImm ( ( Mask & MaskOff ) | MaskOn ) ; } return ; } -- MBBI ; -- Count ; } } } </s>

Delete the instruction OldInst and everything after it , replacing it with an unconditional branch to NewDest .


<s> DecodeStatus PPCDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & OS , raw_ostream & CS ) const { Size = 4 ; if ( Bytes . size ( ) < 4 ) { Size = 0 ; return MCDisassembler :: Fail ; } uint32_t Inst = ( Bytes [ 0 ] << 24 ) | ( Bytes [ 1 ] << 16 ) | ( Bytes [ 2 ] << 8 ) | ( Bytes [ 3 ] << 0 ) ; if ( STI . getFeatureBits ( ) [ PPC :: FeatureQPX ] ) { DecodeStatus result = decodeInstruction ( DecoderTableQPX32 , MI , Inst , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) return result ; MI . clear ( ) ; } return decodeInstruction ( DecoderTable32 , MI , Inst , Address , this , STI ) ; } </s>

Returns the disassembly of a single instruction .


<s> bool m68k_tls_reference_p ( rtx x , bool legitimate_p ) { if ( ! TARGET_HAVE_TLS ) return false ; if ( ! legitimate_p ) { subrtx_var_iterator :: array_type array ; FOR_EACH_SUBRTX_VAR ( iter , array , x , ALL ) { rtx x = * iter ; if ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) != 0 ) return true ; if ( m68k_tls_reference_p ( x , true ) ) iter . skip_subrtxes ( ) ; } return false ; } else { enum m68k_reloc reloc = RELOC_GOT ; return ( m68k_unwrap_symbol_1 ( x , true , & reloc ) != x && TLS_RELOC_P ( reloc ) ) ; } } </s>

If ! LEGITIMATE_P , return true if X is a TLS symbol reference , though illegitimate one . If LEGITIMATE_P , return true if X is a legitimate TLS symbol reference .


<s> Value * ARMTargetLowering :: getSDagStackGuard ( const Module & M ) const { if ( Subtarget -> getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) ) return M . getGlobalVariable ( "__security_cookie" ) ; return TargetLowering :: getSDagStackGuard ( M ) ; } </s>

Return the variable that 's previously inserted by insertSSPDeclarations , if any , otherwise return nullptr .


<s> bool arm_validize_comparison ( rtx * comparison , rtx * op1 , rtx * op2 ) { enum rtx_code code = GET_CODE ( * comparison ) ; int code_int ; machine_mode mode = ( GET_MODE ( * op1 ) == VOIDmode ) ? GET_MODE ( * op2 ) : GET_MODE ( * op1 ) ; gcc_assert ( GET_MODE ( * op1 ) != VOIDmode || GET_MODE ( * op2 ) != VOIDmode ) ; if ( code == UNEQ || code == LTGT ) return false ; code_int = ( int ) code ; arm_canonicalize_comparison ( & code_int , op1 , op2 , 0 ) ; PUT_CODE ( * comparison , ( enum rtx_code ) code_int ) ; switch ( mode ) { case SImode : if ( ! arm_add_operand ( * op1 , mode ) ) * op1 = force_reg ( mode , * op1 ) ; if ( ! arm_add_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; return true ; case DImode : if ( ! cmpdi_operand ( * op1 , mode ) ) * op1 = force_reg ( mode , * op1 ) ; if ( ! cmpdi_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; return true ; case HFmode : if ( ! TARGET_VFP_FP16INST ) break ; mode = SFmode ; * op1 = convert_to_mode ( mode , * op1 , 1 ) ; * op2 = convert_to_mode ( mode , * op2 , 1 ) ; case SFmode : case DFmode : if ( ! vfp_compare_operand ( * op1 , mode ) ) * op1 = force_reg ( mode , * op1 ) ; if ( ! vfp_compare_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; return true ; default : break ; } return false ; } </s>

Returns true if a valid comparison operation and makes the operands in a form that is valid .


<s> void bfin_expand_epilogue ( int need_return , int eh_return , bool sibcall_p ) { rtx spreg = gen_rtx_REG ( Pmode , REG_SP ) ; e_funkind fkind = funkind ( TREE_TYPE ( current_function_decl ) ) ; int e = sibcall_p ? - 1 : 1 ; tree attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ; bool all = lookup_attribute ( "saveall" , attrs ) != NULL_TREE ; if ( fkind != SUBROUTINE ) { expand_interrupt_handler_epilogue ( spreg , fkind , all ) ; return ; } do_unlink ( spreg , get_frame_size ( ) , all , e ) ; expand_epilogue_reg_restore ( spreg , all , false ) ; if ( ! need_return ) return ; if ( eh_return ) emit_insn ( gen_addsi3 ( spreg , spreg , gen_rtx_REG ( Pmode , REG_P2 ) ) ) ; emit_jump_insn ( gen_return_internal ( gen_rtx_REG ( Pmode , REG_RETS ) ) ) ; } </s>

Generate RTL for the epilogue of the current function . NEED_RETURN is zero if this is for a sibcall . EH_RETURN is nonzero if we 're expanding an eh_return pattern .


<s> StringRef getPassName ( ) const override { return "AMDGPUPreLegalizerCombiner" ; } </s>


<s> bool PPCFrameInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( MF . getFunction ( ) -> hasFnAttr ( Attribute :: Naked ) ) return false ; return DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || ( GuaranteedTailCallOpt && MF . getInfo < PPCFunctionInfo > ( ) -> hasFastCall ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> MCSection * SystemZMCAsmInfo :: getNonexecutableStackSection ( MCContext & Ctx ) const { return MCSectionELF :: Create ( ".note.GNU-stack" , MCSectionELF :: SHT_PROGBITS , 0 , SectionKind :: getMetadata ( ) , false , Ctx ) ; } </s>

Targets can implement this method to specify a section to switch to if the translation unit does n't have any trampolines that require an executable stack .


<s> bool AArch64InstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MBBI ) const { MachineInstr & MI = * MBBI ; MachineBasicBlock & MBB = * MI . getParent ( ) ; unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { case AArch64 :: TLSDESC_BLRx : { MachineInstr * NewMI = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , get ( AArch64 :: TLSDESCCALL ) ) . addOperand ( MI . getOperand ( 1 ) ) ; MI . setDesc ( get ( AArch64 :: BLRx ) ) ; llvm :: finalizeBundle ( MBB , NewMI , * ++ MBBI ) ; return true ; } default : return false ; } return false ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> static const char * output_387_ffreep ( rtx * operands ATTRIBUTE_UNUSED , int opno ) { if ( TARGET_USE_FFREEP ) return opno ? "ffreep\t%y1" : "ffreep\t%y0" ; { static char retval [ 32 ] ; int regno = REGNO ( operands [ opno ] ) ; gcc_assert ( STACK_REGNO_P ( regno ) ) ; regno -= FIRST_STACK_REG ; snprintf ( retval , sizeof ( retval ) , ASM_SHORT "0xc%ddf" , regno ) ; return retval ; } return opno ? "fstp\t%y1" : "fstp\t%y0" ; } </s>

Output code for x87 ffreep insn . The OPNO argument , which may only have the values zero or one , indicates the ffreep insn 's operand from the OPERANDS array .


<s> void ix86_expand_sse2_abs ( rtx target , rtx input ) { machine_mode mode = GET_MODE ( target ) ; rtx tmp0 , tmp1 , x ; switch ( mode ) { case E_V2DImode : case E_V4DImode : if ( TARGET_SSE4_2 ) { tmp0 = gen_reg_rtx ( mode ) ; tmp1 = gen_reg_rtx ( mode ) ; emit_move_insn ( tmp1 , CONST0_RTX ( mode ) ) ; if ( mode == E_V2DImode ) emit_insn ( gen_sse4_2_gtv2di3 ( tmp0 , tmp1 , input ) ) ; else emit_insn ( gen_avx2_gtv4di3 ( tmp0 , tmp1 , input ) ) ; } else { tmp0 = expand_simple_binop ( mode , LSHIFTRT , input , GEN_INT ( GET_MODE_UNIT_BITSIZE ( mode ) - 1 ) , NULL , 0 , OPTAB_DIRECT ) ; tmp0 = expand_simple_unop ( mode , NEG , tmp0 , NULL , false ) ; } tmp1 = expand_simple_binop ( mode , XOR , tmp0 , input , NULL , 0 , OPTAB_DIRECT ) ; x = expand_simple_binop ( mode , MINUS , tmp1 , tmp0 , target , 0 , OPTAB_DIRECT ) ; break ; case E_V4SImode : tmp0 = expand_simple_binop ( mode , ASHIFTRT , input , GEN_INT ( GET_MODE_UNIT_BITSIZE ( mode ) - 1 ) , NULL , 0 , OPTAB_DIRECT ) ; tmp1 = expand_simple_binop ( mode , XOR , tmp0 , input , NULL , 0 , OPTAB_DIRECT ) ; x = expand_simple_binop ( mode , MINUS , tmp1 , tmp0 , target , 0 , OPTAB_DIRECT ) ; break ; case E_V8HImode : tmp0 = expand_unop ( mode , neg_optab , input , NULL_RTX , 0 ) ; x = expand_simple_binop ( mode , SMAX , tmp0 , input , target , 0 , OPTAB_DIRECT ) ; break ; case E_V16QImode : tmp0 = expand_unop ( mode , neg_optab , input , NULL_RTX , 0 ) ; x = expand_simple_binop ( V16QImode , UMIN , tmp0 , input , target , 0 , OPTAB_DIRECT ) ; break ; default : gcc_unreachable ( ) ; } if ( x != target ) emit_move_insn ( target , x ) ; } </s>

Calculate integer abs ( ) using only SSE2 instructions .


<s> const char * HexagonTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( HexagonISD :: NodeType ) Opcode ) { case HexagonISD :: ALLOCA : return "HexagonISD::ALLOCA" ; case HexagonISD :: ARGEXTEND : return "HexagonISD::ARGEXTEND" ; case HexagonISD :: AT_GOT : return "HexagonISD::AT_GOT" ; case HexagonISD :: AT_PCREL : return "HexagonISD::AT_PCREL" ; case HexagonISD :: BARRIER : return "HexagonISD::BARRIER" ; case HexagonISD :: BR_JT : return "HexagonISD::BR_JT" ; case HexagonISD :: CALLR : return "HexagonISD::CALLR" ; case HexagonISD :: CALLv3nr : return "HexagonISD::CALLv3nr" ; case HexagonISD :: CALLv3 : return "HexagonISD::CALLv3" ; case HexagonISD :: COMBINE : return "HexagonISD::COMBINE" ; case HexagonISD :: CONST32_GP : return "HexagonISD::CONST32_GP" ; case HexagonISD :: CONST32 : return "HexagonISD::CONST32" ; case HexagonISD :: CP : return "HexagonISD::CP" ; case HexagonISD :: DCFETCH : return "HexagonISD::DCFETCH" ; case HexagonISD :: EH_RETURN : return "HexagonISD::EH_RETURN" ; case HexagonISD :: EXTRACTU : return "HexagonISD::EXTRACTU" ; case HexagonISD :: EXTRACTURP : return "HexagonISD::EXTRACTURP" ; case HexagonISD :: FCONST32 : return "HexagonISD::FCONST32" ; case HexagonISD :: INSERT : return "HexagonISD::INSERT" ; case HexagonISD :: INSERTRP : return "HexagonISD::INSERTRP" ; case HexagonISD :: JT : return "HexagonISD::JT" ; case HexagonISD :: PACKHL : return "HexagonISD::PACKHL" ; case HexagonISD :: PIC_ADD : return "HexagonISD::PIC_ADD" ; case HexagonISD :: POPCOUNT : return "HexagonISD::POPCOUNT" ; case HexagonISD :: RET_FLAG : return "HexagonISD::RET_FLAG" ; case HexagonISD :: SHUFFEB : return "HexagonISD::SHUFFEB" ; case HexagonISD :: SHUFFEH : return "HexagonISD::SHUFFEH" ; case HexagonISD :: SHUFFOB : return "HexagonISD::SHUFFOB" ; case HexagonISD :: SHUFFOH : return "HexagonISD::SHUFFOH" ; case HexagonISD :: TC_RETURN : return "HexagonISD::TC_RETURN" ; case HexagonISD :: VCMPBEQ : return "HexagonISD::VCMPBEQ" ; case HexagonISD :: VCMPBGT : return "HexagonISD::VCMPBGT" ; case HexagonISD :: VCMPBGTU : return "HexagonISD::VCMPBGTU" ; case HexagonISD :: VCMPHEQ : return "HexagonISD::VCMPHEQ" ; case HexagonISD :: VCMPHGT : return "HexagonISD::VCMPHGT" ; case HexagonISD :: VCMPHGTU : return "HexagonISD::VCMPHGTU" ; case HexagonISD :: VCMPWEQ : return "HexagonISD::VCMPWEQ" ; case HexagonISD :: VCMPWGT : return "HexagonISD::VCMPWGT" ; case HexagonISD :: VCMPWGTU : return "HexagonISD::VCMPWGTU" ; case HexagonISD :: VSHLH : return "HexagonISD::VSHLH" ; case HexagonISD :: VSHLW : return "HexagonISD::VSHLW" ; case HexagonISD :: VSPLATB : return "HexagonISD::VSPLTB" ; case HexagonISD :: VSPLATH : return "HexagonISD::VSPLATH" ; case HexagonISD :: VSRAH : return "HexagonISD::VSRAH" ; case HexagonISD :: VSRAW : return "HexagonISD::VSRAW" ; case HexagonISD :: VSRLH : return "HexagonISD::VSRLH" ; case HexagonISD :: VSRLW : return "HexagonISD::VSRLW" ; case HexagonISD :: VSXTBH : return "HexagonISD::VSXTBH" ; case HexagonISD :: VSXTBW : return "HexagonISD::VSXTBW" ; case HexagonISD :: OP_END : break ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

Hexagon Hexagon HexagonISD::NodeType HexagonISD::ALLOCA "HexagonISD::ALLOCA" HexagonISD::ARGEXTEND "HexagonISD::ARGEXTEND" HexagonISD::AT_GOT "HexagonISD::AT_GOT" HexagonISD::AT_PCREL "HexagonISD::AT_PCREL" HexagonISD::BARRIER "HexagonISD::BARRIER" HexagonISD::BR_JT "HexagonISD::BR_JT" HexagonISD::CALLR "HexagonISD::CALLR" HexagonISD::CALLv3nr "HexagonISD::CALLv3nr" HexagonISD::CALLv3 "HexagonISD::CALLv3" HexagonISD::COMBINE "HexagonISD::COMBINE" HexagonISD::CONST32_GP "HexagonISD::CONST32_GP" HexagonISD::CONST32 "HexagonISD::CONST32" HexagonISD::CP "HexagonISD::CP" HexagonISD::DCFETCH "HexagonISD::DCFETCH" HexagonISD::EH_RETURN "HexagonISD::EH_RETURN" HexagonISD::EXTRACTU "HexagonISD::EXTRACTU" HexagonISD::EXTRACTURP "HexagonISD::EXTRACTURP" HexagonISD::FCONST32 "HexagonISD::FCONST32" HexagonISD::INSERT "HexagonISD::INSERT" HexagonISD::INSERTRP "HexagonISD::INSERTRP" HexagonISD::JT "HexagonISD::JT" HexagonISD::PACKHL "HexagonISD::PACKHL" HexagonISD::PIC_ADD "HexagonISD::PIC_ADD" HexagonISD::POPCOUNT "HexagonISD::POPCOUNT" HexagonISD::RET_FLAG "HexagonISD::RET_FLAG" HexagonISD::SHUFFEB "HexagonISD::SHUFFEB" HexagonISD::SHUFFEH "HexagonISD::SHUFFEH" HexagonISD::SHUFFOB "HexagonISD::SHUFFOB" HexagonISD::SHUFFOH "HexagonISD::SHUFFOH" HexagonISD::TC_RETURN "HexagonISD::TC_RETURN" HexagonISD::VCMPBEQ "HexagonISD::VCMPBEQ" HexagonISD::VCMPBGT "HexagonISD::VCMPBGT" HexagonISD::VCMPBGTU "HexagonISD::VCMPBGTU" HexagonISD::VCMPHEQ "HexagonISD::VCMPHEQ" HexagonISD::VCMPHGT "HexagonISD::VCMPHGT" HexagonISD::VCMPHGTU "HexagonISD::VCMPHGTU" HexagonISD::VCMPWEQ "HexagonISD::VCMPWEQ" HexagonISD::VCMPWGT "HexagonISD::VCMPWGT" HexagonISD::VCMPWGTU "HexagonISD::VCMPWGTU" HexagonISD::VSHLH "HexagonISD::VSHLH" HexagonISD::VSHLW "HexagonISD::VSHLW" HexagonISD::VSPLATB "HexagonISD::VSPLTB" HexagonISD::VSPLATH "HexagonISD::VSPLATH" HexagonISD::VSRAH "HexagonISD::VSRAH" HexagonISD::VSRAW "HexagonISD::VSRAW" HexagonISD::VSRLH "HexagonISD::VSRLH" HexagonISD::VSRLW "HexagonISD::VSRLW" HexagonISD::VSXTBH "HexagonISD::VSXTBH" HexagonISD::VSXTBW "HexagonISD::VSXTBW" HexagonISD::OP_END


<s>
const
RegisterBankInfo
*
ARMSubtarget
::
getRegBankInfo
(
)
const
{
assert
(
GISel
&&
"Access to GlobalISel APIs not set"
)
;
return
GISel
->
getRegBankInfo
(
)
;
}
</s>

If the information for the register banks is available , return it .

ARM
ARM
"Access to GlobalISel APIs not set"


<s> static int arm_sched_reorder ( FILE * file , int verbose , rtx_insn * * ready , int * n_readyp , int clock ) { switch ( arm_tune ) { case TARGET_CPU_cortexa7 : cortexa7_sched_reorder ( file , verbose , ready , n_readyp , clock ) ; break ; default : break ; } return arm_issue_rate ( ) ; } </s>


<s> static int ix86_mode_exit ( int entity ) { switch ( entity ) { case X86_DIRFLAG : return X86_DIRFLAG_ANY ; case AVX_U128 : return ix86_avx_u128_mode_exit ( ) ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : case I387_MASK_PM : return I387_CW_ANY ; default : gcc_unreachable ( ) ; } } </s>

Return a mode that ENTITY is assumed to be switched to at function exit .


<s> int direct_return ( ) { return ( ! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK && reload_completed && alpha_sa_size ( ) == 0 && get_frame_size ( ) == 0 && current_function_outgoing_args_size == 0 && current_function_pretend_args_size == 0 ) ; } </s>

Return non-zero if this function is known to have a null epilogue .


<s>
Register
SITargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
const
MachineFunction
&
MF
)
const
{
Register
Reg
=
StringSwitch
<
Register
>
(
RegName
)
.
Case
(
"m0"
,
AMDGPU
::
M0
)
.
Case
(
"exec"
,
AMDGPU
::
EXEC
)
.
Case
(
"exec_lo"
,
AMDGPU
::
EXEC_LO
)
.
Case
(
"exec_hi"
,
AMDGPU
::
EXEC_HI
)
.
Case
(
"flat_scratch"
,
AMDGPU
::
FLAT_SCR
)
.
Case
(
"flat_scratch_lo"
,
AMDGPU
::
FLAT_SCR_LO
)
.
Case
(
"flat_scratch_hi"
,
AMDGPU
::
FLAT_SCR_HI
)
.
Default
(
Register
(
)
)
;
if
(
Reg
==
AMDGPU
::
NoRegister
)
{
report_fatal_error
(
Twine
(
"invalid register name \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;
}
if
(
!
Subtarget
->
hasFlatScrRegister
(
)
&&
Subtarget
->
getRegisterInfo
(
)
->
regsOverlap
(
Reg
,
AMDGPU
::
FLAT_SCR
)
)
{
report_fatal_error
(
Twine
(
"invalid register \""
+
StringRef
(
RegName
)
+
"\" for subtarget."
)
)
;
}
switch
(
Reg
)
{
case
AMDGPU
::
M0
:
case
AMDGPU
::
EXEC_LO
:
case
AMDGPU
::
EXEC_HI
:
case
AMDGPU
::
FLAT_SCR_LO
:
case
AMDGPU
::
FLAT_SCR_HI
:
if
(
VT
.
getSizeInBits
(
)
==
32
)
return
Reg
;
break
;
case
AMDGPU
::
EXEC
:
case
AMDGPU
::
FLAT_SCR
:
if
(
VT
.
getSizeInBits
(
)
==
64
)
return
Reg
;
break
;
default
:
llvm_unreachable
(
"missing register type checking"
)
;
}
report_fatal_error
(
Twine
(
"invalid type for register \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;
}
</s>

Return the register ID of the name passed in .


<s> static rtx sparc_function_value_1 ( const_tree type , machine_mode mode , bool outgoing ) { const int regbase = outgoing ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST ; enum mode_class mclass = GET_MODE_CLASS ( mode ) ; int regno ; if ( type && VECTOR_INTEGER_TYPE_P ( type ) && mode != BLKmode ) mclass = MODE_FLOAT ; if ( TARGET_ARCH64 && type ) { if ( TREE_CODE ( type ) == RECORD_TYPE ) { const int size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 32 ) ; return function_arg_record_value ( type , mode , 0 , true , regbase ) ; } else if ( TREE_CODE ( type ) == UNION_TYPE ) { const int size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 32 ) ; return function_arg_union_value ( size , mode , 0 , regbase ) ; } else if ( VECTOR_TYPE_P ( type ) && mode == BLKmode ) { const int size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 32 ) ; return function_arg_vector_value ( size , 0 , true , SPARC_FP_ARG_FIRST ) ; } else if ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) ; else if ( AGGREGATE_TYPE_P ( type ) ) { const int size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 32 ) ; mode = int_mode_for_size ( size * BITS_PER_UNIT , 0 ) . else_blk ( ) ; if ( mode == BLKmode ) return function_arg_union_value ( size , mode , 0 , regbase ) ; else mclass = MODE_INT ; } else if ( mclass == MODE_INT && GET_MODE_SIZE ( mode ) < UNITS_PER_WORD ) mode = word_mode ; } else if ( TARGET_ARCH32 && ! ( type && AGGREGATE_TYPE_P ( type ) ) && mclass == MODE_INT && GET_MODE_SIZE ( mode ) < UNITS_PER_WORD ) mode = word_mode ; if ( ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) && TARGET_FPU ) regno = SPARC_FP_ARG_FIRST ; else regno = regbase ; return gen_rtx_REG ( mode , regno ) ; } </s>

Handle TARGET_FUNCTION_VALUE , and TARGET_LIBCALL_VALUE target hook . For v9 , function return values are subject to the same rules as arguments , except that up to 32 bytes may be returned in registers .


<s> TargetPassConfig * MipsTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new MipsPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s>
bool
R600Packetizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
const
R600Subtarget
&
ST
=
Fn
.
getSubtarget
<
R600Subtarget
>
(
)
;
const
R600InstrInfo
*
TII
=
ST
.
getInstrInfo
(
)
;
MachineLoopInfo
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
R600PacketizerList
Packetizer
(
Fn
,
ST
,
MLI
)
;
assert
(
Packetizer
.
getResourceTracker
(
)
&&
"Empty DFA table!"
)
;
assert
(
Packetizer
.
getResourceTracker
(
)
->
getInstrItins
(
)
)
;
if
(
Packetizer
.
getResourceTracker
(
)
->
getInstrItins
(
)
->
isEmpty
(
)
)
return
false
;
for
(
MachineBasicBlock
&
MBB
:
Fn
)
{
for
(
MachineInstr
&
MI
:
llvm
::
make_early_inc_range
(
MBB
)
)
{
if
(
MI
.
isKill
(
)
||
MI
.
getOpcode
(
)
==
R600
::
IMPLICIT_DEF
||
(
MI
.
getOpcode
(
)
==
R600
::
CF_ALU
&&
!
MI
.
getOperand
(
8
)
.
getImm
(
)
)
)
MBB
.
erase
(
MI
)
;
}
}
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
unsigned
RemainingCount
=
MBB
->
size
(
)
;
for
(
MachineBasicBlock
::
iterator
RegionEnd
=
MBB
->
end
(
)
;
RegionEnd
!=
MBB
->
begin
(
)
;
)
{
MachineBasicBlock
::
iterator
I
=
RegionEnd
;
for
(
;
I
!=
MBB
->
begin
(
)
;
I
,
RemainingCount
)
{
if
(
TII
->
isSchedulingBoundary
(
*
std
::
prev
(
I
)
,
&
*
MBB
,
Fn
)
)
break
;
}
I
=
MBB
->
begin
(
)
;
if
(
I
==
RegionEnd
)
{
RegionEnd
=
std
::
prev
(
RegionEnd
)
;
RemainingCount
;
continue
;
}
if
(
I
==
std
::
prev
(
RegionEnd
)
)
{
RegionEnd
=
std
::
prev
(
RegionEnd
)
;
continue
;
}
Packetizer
.
PacketizeMIs
(
&
*
MBB
,
&
*
I
,
RegionEnd
)
;
RegionEnd
=
I
;
}
}
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static bool s390_fixed_condition_code_regs ( unsigned int * p1 , unsigned int * p2 ) { * p1 = CC_REGNUM ; * p2 = INVALID_REGNUM ; return true ; } </s>

Return the fixed registers used for condition codes .


<s> StringRef getPassName ( ) const override { return THUMB2_SIZE_REDUCE_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 cmov Conversion"
;
}
</s>


<s>
const
char
*
output_move_quad
(
rtx
*
operands
)
{
if
(
REG_P
(
operands
[
0
]
)
)
{
if
(
MEM_P
(
operands
[
1
]
)
)
{
switch
(
GET_CODE
(
XEXP
(
operands
[
1
]
,
0
)
)
)
{
case
REG
:
output_asm_insn
(
"ldmia%?\t%m1, %M0"
,
operands
)
;
break
;
case
LABEL_REF
:
case
CONST
:
output_asm_insn
(
"adr%?\t%0, %1"
,
operands
)
;
output_asm_insn
(
"ldmia%?\t%0, %M0"
,
operands
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
else
{
rtx
ops
[
2
]
;
int
dest
,
src
,
i
;
gcc_assert
(
REG_P
(
operands
[
1
]
)
)
;
dest
=
REGNO
(
operands
[
0
]
)
;
src
=
REGNO
(
operands
[
1
]
)
;
if
(
dest
<
src
)
for
(
i
=
0
;
i
<
4
;
i
++
)
{
ops
[
0
]
=
gen_rtx_REG
(
SImode
,
dest
+
i
)
;
ops
[
1
]
=
gen_rtx_REG
(
SImode
,
src
+
i
)
;
output_asm_insn
(
"mov%?\t%0, %1"
,
ops
)
;
}
else
for
(
i
=
3
;
i
>=
0
;
i
)
{
ops
[
0
]
=
gen_rtx_REG
(
SImode
,
dest
+
i
)
;
ops
[
1
]
=
gen_rtx_REG
(
SImode
,
src
+
i
)
;
output_asm_insn
(
"mov%?\t%0, %1"
,
ops
)
;
}
}
}
else
{
gcc_assert
(
MEM_P
(
operands
[
0
]
)
)
;
gcc_assert
(
REG_P
(
operands
[
1
]
)
)
;
gcc_assert
(
!
reg_overlap_mentioned_p
(
operands
[
1
]
,
operands
[
0
]
)
)
;
switch
(
GET_CODE
(
XEXP
(
operands
[
0
]
,
0
)
)
)
{
case
REG
:
output_asm_insn
(
"stm%?\t%m0, %M1"
,
operands
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
return
""
;
}
</s>

Output assembler code to perform a quadword move insn with operands OPERANDS .


<s> TargetPassConfig * DigitalTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new DigitalPassConfig ( this , PM ) ; } </s>


<s> static bool check_liw_constraints ( struct liw_data * pliw1 , struct liw_data * pliw2 ) { if ( pliw2 -> slot == pliw1 -> slot && pliw1 -> slot != LIW_EITHER ) return false ; if ( pliw1 -> op == LIW_OP_CMP ) { gcc_assert ( pliw1 -> op != pliw2 -> op ) ; return true ; } if ( pliw2 -> op == LIW_OP_CMP ) { if ( REGNO ( pliw2 -> dest ) == REGNO ( pliw1 -> dest ) ) return false ; if ( REG_P ( pliw2 -> src ) ) return REGNO ( pliw2 -> src ) != REGNO ( pliw1 -> dest ) ; return true ; } if ( REGNO ( pliw2 -> dest ) == REGNO ( pliw1 -> dest ) ) return false ; if ( REG_P ( pliw2 -> src ) && REGNO ( pliw2 -> src ) == REGNO ( pliw1 -> dest ) ) { if ( pliw1 -> op == LIW_OP_MOV && REG_P ( pliw1 -> src ) ) { if ( ! REG_P ( pliw1 -> src ) && ( pliw2 -> op == LIW_OP_AND || pliw2 -> op == LIW_OP_OR || pliw2 -> op == LIW_OP_XOR ) ) return false ; pliw2 -> src = pliw1 -> src ; return true ; } return false ; } return true ; } </s>

Make sure that it is OK to execute LIW1 and LIW2 in parallel . GCC generated the instructions with the assumption that LIW1 would be executed before LIW2 so we must check for overlaps between their sources and destinations .


<s> const MCExpr * X86_64MachoTargetObjectFile :: getTTypeGlobalReference ( const GlobalValue * GV , unsigned Encoding , Mangler & Mang , const TargetMachine & TM , MachineModuleInfo * MMI , MCStreamer & Streamer ) const { if ( ( Encoding & DW_EH_PE_indirect ) && ( Encoding & DW_EH_PE_pcrel ) ) { const MCSymbol * Sym = TM . getSymbol ( GV , Mang ) ; const MCExpr * Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_GOTPCREL , getContext ( ) ) ; const MCExpr * Four = MCConstantExpr :: create ( 4 , getContext ( ) ) ; return MCBinaryExpr :: createAdd ( Res , Four , getContext ( ) ) ; } return TargetLoweringObjectFileMachO :: getTTypeGlobalReference ( GV , Encoding , Mang , TM , MMI , Streamer ) ; } </s>

The mach-o version of this method defaults to returning a stub reference .


<s> void AMDGPURegBankCombiner :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < TargetPassConfig > ( ) ; AU . setPreservesCFG ( ) ; getSelectionDAGFallbackAnalysisUsage ( AU ) ; AU . addRequired < GISelKnownBitsAnalysis > ( ) ; AU . addPreserved < GISelKnownBitsAnalysis > ( ) ; if ( ! IsOptNone ) { AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; } MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> const MCPhysReg * F2003fRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_NoRegs_SaveList ; } </s>