<s> static bool expand_vec_perm_even_odd ( struct expand_vec_perm_d * d ) { unsigned i , odd , nelt = d -> nelt ; odd = d -> perm [ 0 ] ; if ( odd != 0 && odd != 1 ) return false ; for ( i = 1 ; i < nelt ; ++ i ) if ( d -> perm [ i ] != 2 * i + odd ) return false ; if ( d -> vmode == E_V32HImode && d -> testing_p && ! TARGET_AVX512BW ) return false ; return expand_vec_perm_even_odd_1 ( d , odd ) ; } </s>

A subroutine of ix86_expand_vec_perm_builtin_1 . Pattern match extract-even and extract-odd permutations .


<s>
void
ARMAsmBackend
::
relaxInstruction
(
const
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
,
MCInst
&
Res
)
const
{
unsigned
RelaxedOp
=
getRelaxedOpcode
(
Inst
.
getOpcode
(
)
,
STI
)
;
if
(
RelaxedOp
==
Inst
.
getOpcode
(
)
)
{
SmallString
<
256
>
Tmp
;
raw_svector_ostream
OS
(
Tmp
)
;
Inst
.
dump_pretty
(
OS
)
;
OS
<<
"\n"
;
report_fatal_error
(
"unexpected instruction to relax: "
+
OS
.
str
(
)
)
;
}
if
(
(
Inst
.
getOpcode
(
)
==
ARM
::
tCBZ
||
Inst
.
getOpcode
(
)
==
ARM
::
tCBNZ
)
&&
RelaxedOp
==
ARM
::
tHINT
)
{
Res
.
setOpcode
(
RelaxedOp
)
;
Res
.
addOperand
(
MCOperand
::
createImm
(
0
)
)
;
Res
.
addOperand
(
MCOperand
::
createImm
(
14
)
)
;
Res
.
addOperand
(
MCOperand
::
createReg
(
0
)
)
;
return
;
}
Res
=
Inst
;
Res
.
setOpcode
(
RelaxedOp
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> rtx arm_gen_compare_reg ( enum rtx_code code , rtx x , rtx y ) { enum machine_mode mode = SELECT_CC_MODE ( code , x , y ) ; rtx cc_reg = gen_rtx_REG ( mode , CC_REGNUM ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cc_reg , gen_rtx_COMPARE ( mode , x , y ) ) ) ; return cc_reg ; } </s>

X and Y are two things to compare using CODE . Emit the compare insn and return the rtx for register 0 in the proper mode . FP means this is a floating point compare : I do n't think that it is needed on the arm .


<s> InstructionCost getIntImmCostInst ( unsigned Opc , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind , Instruction * Inst = nullptr ) { return getIntImmCost ( Imm , Ty , CostKind ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> static tree xtensa_build_builtin_va_list ( void ) { tree f_stk , f_reg , f_ndx , record , type_decl ; record = ( * lang_hooks . types . make_type ) ( RECORD_TYPE ) ; type_decl = build_decl ( TYPE_DECL , get_identifier ( "__va_list_tag" ) , record ) ; f_stk = build_decl ( FIELD_DECL , get_identifier ( "__va_stk" ) , ptr_type_node ) ; f_reg = build_decl ( FIELD_DECL , get_identifier ( "__va_reg" ) , ptr_type_node ) ; f_ndx = build_decl ( FIELD_DECL , get_identifier ( "__va_ndx" ) , integer_type_node ) ; DECL_FIELD_CONTEXT ( f_stk ) = record ; DECL_FIELD_CONTEXT ( f_reg ) = record ; DECL_FIELD_CONTEXT ( f_ndx ) = record ; TREE_CHAIN ( record ) = type_decl ; TYPE_NAME ( record ) = type_decl ; TYPE_FIELDS ( record ) = f_stk ; TREE_CHAIN ( f_stk ) = f_reg ; TREE_CHAIN ( f_reg ) = f_ndx ; layout_type ( record ) ; return record ; } </s>

Create the va_list data type . This structure is set up by __builtin_saveregs . The __va_reg field points to a stack-allocated region holding the contents of the incoming argument registers . The __va_ndx field is an index initialized to the position of the first unnamed ( variable ) argument . This same index is also used to address the arguments passed in memory . Thus , the __va_stk field is initialized to point to the position of the first argument in memory offset to account for the arguments passed in registers and to account for the size of the argument registers not being 16-byte aligned . E.G. , there are 6 argument registers of 4 bytes each , but we want the __va_ndx for the first stack argument to have the maximal alignment of 16 bytes , so we offset the __va_stk address by 32 bytes so that __va_stk [ 32 ] references the first argument on the stack .


<s> static void frv_split_iacc_move ( rtx dest , rtx src ) { enum machine_mode inner ; int i ; inner = GET_MODE ( dest ) ; for ( i = 0 ; i < GET_MODE_SIZE ( inner ) ; i += GET_MODE_SIZE ( SImode ) ) emit_move_insn ( simplify_gen_subreg ( SImode , dest , inner , i ) , simplify_gen_subreg ( SImode , src , inner , i ) ) ; } </s>

Emit a move from SRC to DEST in SImode chunks . This can be used to move DImode values into and out of IACC0 .


<s> static tree aarch64_simd_builtin_type ( machine_mode mode , bool unsigned_p , bool poly_p ) { if ( poly_p ) return aarch64_lookup_simd_builtin_type ( mode , qualifier_poly ) ; else if ( unsigned_p ) return aarch64_lookup_simd_builtin_type ( mode , qualifier_unsigned ) ; else return aarch64_lookup_simd_builtin_type ( mode , qualifier_none ) ; } </s>

Return a type for an operand with specified mode and qualifiers .


<s>
StringRef
getPassName
(
)
const
override
{
return
"WebAssembly Nullify DBG_VALUE_LISTs"
;
}
</s>

getPassName - Return a nice clean name for a pass .

WebAssembly
"WebAssembly Nullify DBG_VALUE_LISTs"


<s> void LC2200InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << StringRef ( getRegisterName ( RegNo ) ) . lower ( ) ; } </s>


<s> void SPUHazardRecognizer :: EmitNoop ( ) { AdvanceCycle ( ) ; } </s>

EmitNoop - This callback is invoked when a noop was added to the instruction stream .


<s> void CustomListScheduler :: StartBlock ( MachineBasicBlock * BB ) { TheBase :: StartBlock ( BB ) ; HazardRec -> Reset ( ) ; if ( AntiDepBreak != NULL ) AntiDepBreak -> StartBlock ( BB ) ; } </s>

Initialize anti-dep breaking for a new basic block .


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> static bool arm_function_ok_for_sibcall ( tree decl , tree exp ) { unsigned long func_type ; if ( cfun -> machine -> sibcall_blocked ) return false ; if ( TARGET_THUMB1 ) return false ; if ( TARGET_VXWORKS_RTP && flag_pic && ! targetm . binds_local_p ( decl ) ) return false ; if ( TARGET_INTERWORK && decl && TREE_PUBLIC ( decl ) && ! TREE_ASM_WRITTEN ( decl ) ) return false ; func_type = arm_current_func_type ( ) ; if ( IS_INTERRUPT ( func_type ) ) return false ; if ( ! VOID_TYPE_P ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) ) ) { rtx a , b ; a = arm_function_value ( TREE_TYPE ( exp ) , decl , false ) ; b = arm_function_value ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) , cfun -> decl , false ) ; if ( ! rtx_equal_p ( a , b ) ) return false ; } if ( IS_STACKALIGN ( func_type ) ) return false ; if ( TARGET_AAPCS_BASED && arm_abi == ARM_ABI_AAPCS && decl && DECL_WEAK ( decl ) ) return false ; return true ; } </s>

Return non-zero if it is ok to make a tail-call to DECL .


"too large function value type, needs %d registers,\ have only %d registers for this"


<s>
const
char
*
output_probe_stack_range
(
rtx
reg1
,
rtx
reg2
)
{
static
int
labelno
=
0
;
char
loop_lab
[
32
]
,
end_lab
[
32
]
;
rtx
xops
[
3
]
;
ASM_GENERATE_INTERNAL_LABEL
(
loop_lab
,
"LPSRL"
,
labelno
)
;
ASM_GENERATE_INTERNAL_LABEL
(
end_lab
,
"LPSRE"
,
labelno
++
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
loop_lab
)
;
xops
[
0
]
=
reg1
;
xops
[
1
]
=
reg2
;
xops
[
2
]
=
gen_rtx_REG
(
BImode
,
PR_REG
(
6
)
)
;
output_asm_insn
(
"cmp.eq %2, %I2 = %0, %1"
,
xops
)
;
fprintf
(
asm_out_file
,
"\t(%s) br.cond.dpnt "
,
reg_names
[
REGNO
(
xops
[
2
]
)
]
)
;
assemble_name_raw
(
asm_out_file
,
end_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
xops
[
1
]
=
GEN_INT
(
PROBE_INTERVAL
)
;
output_asm_insn
(
"addl %0 = %1, %0"
,
xops
)
;
fputs
(
"\t;;\n"
,
asm_out_file
)
;
output_asm_insn
(
"probe.w.fault %0, 0"
,
xops
)
;
fprintf
(
asm_out_file
,
"\tbr "
)
;
assemble_name_raw
(
asm_out_file
,
loop_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
end_lab
)
;
return
""
;
}
</s>

Wrapper around the output_probe_stack_range routines .


<s> DecodeStatus AAPDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & os , raw_ostream & cs ) const { uint32_t Insn ; DecodeStatus Result ; if ( Bytes . size ( ) < 2 ) { Size = 0 ; return MCDisassembler :: Fail ; } Insn = ( Bytes [ 1 ] << 8 ) | ( Bytes [ 0 ] << 0 ) ; Result = decodeInstruction ( DecoderTable16 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 2 ; return Result ; } if ( Bytes . size ( ) < 4 ) { Size = 0 ; return MCDisassembler :: Fail ; } Insn = ( Bytes [ 3 ] << 24 ) | ( Bytes [ 2 ] << 16 ) | ( Bytes [ 1 ] << 8 ) | ( Bytes [ 0 ] << 0 ) ; Result = decodeInstruction ( DecoderTable32 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } Size = 2 ; return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s>
bool
AArch64FrameLowering
::
spillCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
std
::
vector
<
CalleeSavedInfo
>
&
CSIWithSVE
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
;
std
::
vector
<
CalleeSavedInfo
>
CSI
;
for
(
unsigned
i
=
0
;
i
<
CSIWithSVE
.
size
(
)
;
++
i
)
{
if
(
MFI
->
getStackRegionToHandleCSR
(
CSIWithSVE
[
i
]
.
getReg
(
)
)
!=
nullptr
)
continue
;
CSI
.
push_back
(
CSIWithSVE
[
i
]
)
;
}
SmallVector
<
RegPairInfo
,
8
>
RegPairs
;
computeCalleeSaveRegisterPairs
(
MF
,
CSI
,
TRI
,
RegPairs
)
;
for
(
auto
RPII
=
RegPairs
.
rbegin
(
)
,
RPIE
=
RegPairs
.
rend
(
)
;
RPII
!=
RPIE
;
++
RPII
)
{
RegPairInfo
RPI
=
*
RPII
;
unsigned
Reg1
=
RPI
.
Reg1
;
unsigned
Reg2
=
RPI
.
Reg2
;
unsigned
StrOpc
;
if
(
RPI
.
IsGPR
)
StrOpc
=
RPI
.
isPaired
(
)
AArch64
::
STPXi
:
AArch64
::
STRXui
;
else
StrOpc
=
RPI
.
isPaired
(
)
AArch64
::
STPDi
:
AArch64
::
STRDui
;
DEBUG
(
dbgs
(
)
<<
"CSR spill: ("
<<
TRI
->
getName
(
Reg1
)
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
TRI
->
getName
(
Reg2
)
;
dbgs
(
)
<<
") -> fi#("
<<
RPI
.
FrameIdx
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
RPI
.
FrameIdx
+
1
;
dbgs
(
)
<<
")\n"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
StrOpc
)
)
;
MBB
.
addLiveIn
(
Reg1
)
;
if
(
RPI
.
isPaired
(
)
)
{
MBB
.
addLiveIn
(
Reg2
)
;
MIB
.
addReg
(
Reg2
,
getPrologueDeath
(
MF
,
Reg2
)
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
+
1
)
,
MachineMemOperand
::
MOStore
,
8
,
8
)
)
;
}
MIB
.
addReg
(
Reg1
,
getPrologueDeath
(
MF
,
Reg1
)
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
RPI
.
Offset
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
)
,
MachineMemOperand
::
MOStore
,
8
,
8
)
)
;
}
return
true
;
}
</s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s>
void
mmix_asm_output_aligned_local
(
FILE
*
stream
,
const
char
*
name
,
int
size
,
int
align
)
{
switch_to_section
(
data_section
)
;
ASM_OUTPUT_ALIGN
(
stream
,
exact_log2
(
align
/
BITS_PER_UNIT
)
)
;
assemble_name
(
stream
,
name
)
;
fprintf
(
stream
,
"\tLOC @+%d\n"
,
size
)
;
}
</s>


"; WARNING: The following code is valid only with MASM v8.x"

"; This version of MASM is usually shipped with Microsoft "

"; or (possible) further versions. Unfortunately, there is no "

"; dllexported symbols in the earlier versions of MASM in fully "

"_drectve\t segment info alias('.drectve')\n"

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> bool PPCSubtarget :: useAA ( ) const { return true ; } </s>

Enable use of alias analysis during code generation ( during MI scheduling , DAGCombine , etc . ) .


<s> bool AMDGPUUseNativeCalls :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) || UseNative . empty ( ) ) return false ; bool Changed = false ; for ( auto & BB : F ) { for ( BasicBlock :: iterator I = BB . begin ( ) , E = BB . end ( ) ; I != E ; ) { CallInst * CI = dyn_cast < CallInst > ( I ) ; ++ I ; if ( ! CI ) continue ; Function * Callee = CI -> getCalledFunction ( ) ; if ( Callee == nullptr ) continue ; if ( Simplifier . useNative ( CI ) ) Changed = true ; } } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


"WebAssembly hasn't implemented computed gotos"

LowerOperation - Provide custom lowering hooks for some operations .


<s>
const
char
*
HexagonRegisterInfo
::
getRegPressureSetName
(
unsigned
Idx
)
const
{
static
const
char
*
const
RegPressureSetName
[
]
=
{
"IntRegsRegSet"
,
"CRRegsRegSet"
,
"PredRegsRegSet"
,
"DoubleRegsRegSet"
}
;
assert
(
(
Idx
<
4
)
&&
"Index out of bounds"
)
;
return
RegPressureSetName
[
Idx
]
;
}
</s>

Get the name of this register unit pressure set .

Hexagon
Hexagon
"IntRegsRegSet"
"CRRegsRegSet"
"PredRegsRegSet"
"DoubleRegsRegSet"
4
"Index out of bounds"


<s> static unsigned loongarch_pass_aggregate_num_fpr ( const_tree type , loongarch_aggregate_field fields [ 2 ] ) { int n = loongarch_flatten_aggregate_argument ( type , fields ) ; for ( int i = 0 ; i < n ; i ++ ) if ( ! SCALAR_FLOAT_TYPE_P ( fields [ i ] . type ) ) return 0 ; return n > 0 ? n : 0 ; } </s>

See whether TYPE is a record whose fields should be returned in one or two floating-point registers . If so , populate FIELDS accordingly .


<s> int mmix_use_simple_return ( void ) { int regno ; int stack_space_to_allocate = ( crtl -> outgoing_args_size + crtl -> args . pretend_args_size + get_frame_size ( ) + 7 ) & ~ 7 ; if ( ! TARGET_USE_RETURN_INSN || ! reload_completed ) return 0 ; for ( regno = 255 ; regno >= MMIX_FIRST_GLOBAL_REGNUM ; regno -- ) if ( ( ( ( regno != MMIX_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) && df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) ) || IS_MMIX_EH_RETURN_DATA_REG ( regno ) ) return 0 ; if ( frame_pointer_needed ) stack_space_to_allocate += 8 ; if ( MMIX_CFUN_HAS_LANDING_PAD ) stack_space_to_allocate += 16 ; else if ( MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS ) stack_space_to_allocate += 8 ; return stack_space_to_allocate == 0 ; } </s>

Nonzero when the function epilogue is simple enough that a single `` POP % d,0 '' should be used even within the function .


<s> bool writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const override { if ( Count % 4 != 0 ) return false ; uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) support :: endian :: write < uint32_t > ( OS , 0x01000000 , Endian ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s>
int
AArch64InstrInfo
::
getMemScale
(
unsigned
Opc
)
{
switch
(
Opc
)
{
default
:
llvm_unreachable
(
"Opcode has unknown scale!"
)
;
case
AArch64
::
LDRBBui
:
case
AArch64
::
LDURBBi
:
case
AArch64
::
LDRSBWui
:
case
AArch64
::
LDURSBWi
:
case
AArch64
::
STRBBui
:
case
AArch64
::
STURBBi
:
return
1
;
case
AArch64
::
LDRHHui
:
case
AArch64
::
LDURHHi
:
case
AArch64
::
LDRSHWui
:
case
AArch64
::
LDURSHWi
:
case
AArch64
::
STRHHui
:
case
AArch64
::
STURHHi
:
return
2
;
case
AArch64
::
LDRSui
:
case
AArch64
::
LDURSi
:
case
AArch64
::
LDRSpre
:
case
AArch64
::
LDRSWui
:
case
AArch64
::
LDURSWi
:
case
AArch64
::
LDRWpre
:
case
AArch64
::
LDRWui
:
case
AArch64
::
LDURWi
:
case
AArch64
::
STRSui
:
case
AArch64
::
STURSi
:
case
AArch64
::
STRSpre
:
case
AArch64
::
STRWui
:
case
AArch64
::
STURWi
:
case
AArch64
::
STRWpre
:
case
AArch64
::
LDPSi
:
case
AArch64
::
LDPSWi
:
case
AArch64
::
LDPWi
:
case
AArch64
::
STPSi
:
case
AArch64
::
STPWi
:
return
4
;
case
AArch64
::
LDRDui
:
case
AArch64
::
LDURDi
:
case
AArch64
::
LDRDpre
:
case
AArch64
::
LDRXui
:
case
AArch64
::
LDURXi
:
case
AArch64
::
LDRXpre
:
case
AArch64
::
STRDui
:
case
AArch64
::
STURDi
:
case
AArch64
::
STRDpre
:
case
AArch64
::
STRXui
:
case
AArch64
::
STURXi
:
case
AArch64
::
STRXpre
:
case
AArch64
::
LDPDi
:
case
AArch64
::
LDPXi
:
case
AArch64
::
STPDi
:
case
AArch64
::
STPXi
:
return
8
;
case
AArch64
::
LDRQui
:
case
AArch64
::
LDURQi
:
case
AArch64
::
STRQui
:
case
AArch64
::
STURQi
:
case
AArch64
::
STRQpre
:
case
AArch64
::
LDPQi
:
case
AArch64
::
LDRQpre
:
case
AArch64
::
STPQi
:
case
AArch64
::
STGOffset
:
case
AArch64
::
STZGOffset
:
case
AArch64
::
ST2GOffset
:
case
AArch64
::
STZ2GOffset
:
case
AArch64
::
STGPi
:
return
16
;
}
}
</s>

Scaling factor for ( scaled or unscaled ) load or store .


<s>
bool
RISCVMakeCompressibleOpt
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
if
(
skipFunction
(
Fn
.
getFunction
(
)
)
||
!
Fn
.
getFunction
(
)
.
hasMinSize
(
)
)
return
false
;
const
RISCVSubtarget
&
STI
=
Fn
.
getSubtarget
<
RISCVSubtarget
>
(
)
;
const
RISCVInstrInfo
&
TII
=
*
STI
.
getInstrInfo
(
)
;
if
(
!
STI
.
hasStdExtC
(
)
)
return
false
;
for
(
MachineBasicBlock
&
MBB
:
Fn
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"MBB: "
<<
MBB
.
getName
(
)
<<
"\n"
)
;
for
(
MachineInstr
&
MI
:
MBB
)
{
RegImmPair
RegImm
=
getRegImmPairPreventingCompression
(
MI
)
;
if
(
!
RegImm
.
Reg
&&
RegImm
.
Imm
==
0
)
continue
;
SmallVector
<
MachineInstr
*
,
8
>
MIs
;
Register
NewReg
=
analyzeCompressibleUses
(
MI
,
RegImm
,
MIs
)
;
if
(
!
NewReg
)
continue
;
if
(
RISCV
::
GPRRegClass
.
contains
(
RegImm
.
Reg
)
)
{
assert
(
isInt
<
12
>
(
RegImm
.
Imm
)
)
;
BuildMI
(
MBB
,
MI
,
MI
.
getDebugLoc
(
)
,
TII
.
get
(
RISCV
::
ADDI
)
,
NewReg
)
.
addReg
(
RegImm
.
Reg
)
.
addImm
(
RegImm
.
Imm
)
;
}
else
{
assert
(
RegImm
.
Imm
==
0
)
;
unsigned
Opcode
=
RISCV
::
FPR32RegClass
.
contains
(
RegImm
.
Reg
)
RISCV
::
FSGNJ_S
:
RISCV
::
FSGNJ_D
;
BuildMI
(
MBB
,
MI
,
MI
.
getDebugLoc
(
)
,
TII
.
get
(
Opcode
)
,
NewReg
)
.
addReg
(
RegImm
.
Reg
)
.
addReg
(
RegImm
.
Reg
)
;
}
for
(
MachineInstr
*
UpdateMI
:
MIs
)
updateOperands
(
*
UpdateMI
,
RegImm
,
NewReg
)
;
}
}
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"R600 Control Flow Finalizer Pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .

AMDGPU
"R600 Control Flow Finalizer Pass"


<s> bool ARMBaseInstrInfo :: hasHighOperandLatency ( const TargetSchedModel & SchedModel , const MachineRegisterInfo * MRI , const MachineInstr & DefMI , unsigned DefIdx , const MachineInstr & UseMI , unsigned UseIdx ) const { unsigned DDomain = DefMI . getDesc ( ) . TSFlags & ARMII :: DomainMask ; unsigned UDomain = UseMI . getDesc ( ) . TSFlags & ARMII :: DomainMask ; if ( Subtarget . nonpipelinedVFP ( ) && ( DDomain == ARMII :: DomainVFP || UDomain == ARMII :: DomainVFP ) ) return true ; unsigned Latency = SchedModel . computeOperandLatency ( & DefMI , DefIdx , & UseMI , UseIdx ) ; if ( Latency <= 3 ) return false ; return DDomain == ARMII :: DomainVFP || DDomain == ARMII :: DomainNEON || UDomain == ARMII :: DomainVFP || UDomain == ARMII :: DomainNEON ; } </s>

Compute operand latency between a def of 'Reg ' and a use in the current loop .

ARM ARM ARMII::DomainMask ARMII::DomainMask ARMII::DomainVFP ARMII::DomainVFP 3 ARMII::DomainVFP ARMII::DomainNEON ARMII::DomainVFP ARMII::DomainNEON


<s> int ARMFrameInfo :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { return ResolveFrameIndexReference ( MF , FI , FrameReg , 0 ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> static unsigned HOST_WIDE_INT xtensa_asan_shadow_offset ( void ) { return HOST_WIDE_INT_UC ( 0x10000000 ) ; } </s>


<s> static rtx get_free_reg ( HARD_REG_SET regs_live ) { if ( ! TEST_HARD_REG_BIT ( regs_live , 1 ) ) return gen_rtx_REG ( Pmode , 1 ) ; gcc_assert ( ! TEST_HARD_REG_BIT ( regs_live , 7 ) ) ; return gen_rtx_REG ( Pmode , 7 ) ; } </s>

REGS_LIVE is the liveness information for the point for which we need this allocation . In some bare-bones exit blocks , r1 is live at the start . We can even have all of r0 .. r3 being live : __complex__ long long f ( double d ) { if ( d == 0 ) return 2 ; else return 3 ; } INSN before which new insns are placed with will clobber the register we return . If a basic block consists only of setting the return value register to a pseudo and using that register , the return value is not live before or after this block , yet we we 'll insert our insns right in the middle .


<s> TargetPassConfig * WDC65816TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new WDC65816PassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s>
Optional
<
RegImmPair
>
AArch64InstrInfo
::
isAddImmediate
(
const
MachineInstr
&
MI
,
Register
Reg
)
const
{
int
Sign
=
1
;
int64_t
Offset
=
0
;
const
MachineOperand
&
Op0
=
MI
.
getOperand
(
0
)
;
if
(
!
Op0
.
isReg
(
)
||
Reg
!=
Op0
.
getReg
(
)
)
return
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
return
;
case
AArch64
::
SUBWri
:
case
AArch64
::
SUBXri
:
case
AArch64
::
SUBSWri
:
case
AArch64
::
SUBSXri
:
Sign
*=
1
;
LLVM_FALLTHROUGH
;
case
AArch64
::
ADDSWri
:
case
AArch64
::
ADDSXri
:
case
AArch64
::
ADDWri
:
case
AArch64
::
ADDXri
:
{
if
(
!
MI
.
getOperand
(
0
)
.
isReg
(
)
||
!
MI
.
getOperand
(
1
)
.
isReg
(
)
||
!
MI
.
getOperand
(
2
)
.
isImm
(
)
)
return
;
Offset
=
MI
.
getOperand
(
2
)
.
getImm
(
)
*
Sign
;
int
Shift
=
MI
.
getOperand
(
3
)
.
getImm
(
)
;
assert
(
(
Shift
==
0
||
Shift
==
12
)
&&
"Shift can be either 0 or 12"
)
;
Offset
=
Offset
<<
Shift
;
}
}
return
RegImmPair
{
MI
.
getOperand
(
1
)
.
getReg
(
)
,
Offset
}
;
}
</s>

If the specific machine instruction is an instruction that adds an immediate value and a register , and stores the result in the given register Reg , return a pair of the source register and the offset which has been added .


<s> bool isValid ( ) const { return isValue ( ) || ! ( OpN & Invalid ) ; } </s>

Returns true if this iterator is still pointing at a valid entry .


<s> AArch64Subtarget & AArch64Subtarget :: initializeSubtargetDependencies ( StringRef FS , StringRef CPUString , StringRef TuneCPUString ) { if ( CPUString . empty ( ) ) CPUString = "generic" ; if ( TuneCPUString . empty ( ) ) TuneCPUString = CPUString ; ParseSubtargetFeatures ( CPUString , TuneCPUString , FS ) ; initializeProperties ( ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> rtx nvptx_gen_shuffle ( rtx dst , rtx src , rtx idx , nvptx_shuffle_kind kind ) { rtx res ; switch ( GET_MODE ( dst ) ) { case SImode : res = gen_nvptx_shufflesi ( dst , src , idx , GEN_INT ( kind ) ) ; break ; case SFmode : res = gen_nvptx_shufflesf ( dst , src , idx , GEN_INT ( kind ) ) ; break ; case DImode : case DFmode : { rtx tmp0 = gen_reg_rtx ( SImode ) ; rtx tmp1 = gen_reg_rtx ( SImode ) ; start_sequence ( ) ; emit_insn ( nvptx_gen_unpack ( tmp0 , tmp1 , src ) ) ; emit_insn ( nvptx_gen_shuffle ( tmp0 , tmp0 , idx , kind ) ) ; emit_insn ( nvptx_gen_shuffle ( tmp1 , tmp1 , idx , kind ) ) ; emit_insn ( nvptx_gen_pack ( dst , tmp0 , tmp1 ) ) ; res = get_insns ( ) ; end_sequence ( ) ; } break ; case BImode : { rtx tmp = gen_reg_rtx ( SImode ) ; start_sequence ( ) ; emit_insn ( gen_sel_truesi ( tmp , src , GEN_INT ( 1 ) , const0_rtx ) ) ; emit_insn ( nvptx_gen_shuffle ( tmp , tmp , idx , kind ) ) ; emit_insn ( gen_rtx_SET ( dst , gen_rtx_NE ( BImode , tmp , const0_rtx ) ) ) ; res = get_insns ( ) ; end_sequence ( ) ; } break ; case QImode : case HImode : { rtx tmp = gen_reg_rtx ( SImode ) ; start_sequence ( ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_fmt_e ( ZERO_EXTEND , SImode , src ) ) ) ; emit_insn ( nvptx_gen_shuffle ( tmp , tmp , idx , kind ) ) ; emit_insn ( gen_rtx_SET ( dst , gen_rtx_fmt_e ( TRUNCATE , GET_MODE ( dst ) , tmp ) ) ) ; res = get_insns ( ) ; end_sequence ( ) ; } break ; default : gcc_unreachable ( ) ; } return res ; } </s>

Generate an instruction or sequence to broadcast register REG across the vectors of a single warp .


<s> static rtx bfin_load_pic_reg ( rtx dest ) { struct cgraph_local_info * i = NULL ; rtx addr ; i = cgraph_node :: local_info ( current_function_decl ) ; if ( i && i -> local ) return pic_offset_table_rtx ; if ( global_options_set . x_bfin_library_id ) addr = plus_constant ( Pmode , pic_offset_table_rtx , - 4 - bfin_library_id * 4 ) ; else addr = gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , const0_rtx ) , UNSPEC_LIBRARY_OFFSET ) ) ; emit_insn ( gen_movsi ( dest , gen_rtx_MEM ( Pmode , addr ) ) ) ; return dest ; } </s>

Used while emitting the prologue to generate code to load the correct value into the PIC register , which is passed in DEST .


<s> static rtx ix86_builtin_setjmp_frame_value ( void ) { return stack_realign_fp ? hard_frame_pointer_rtx : virtual_stack_vars_rtx ; } </s>

In a dynamically-aligned function , we ca n't know the offset from stack pointer to frame pointer , so we must ensure that setjmp eliminates fp against the hard fp ( % ebp ) rather than trying to index from % esp up to the top of the frame across a gap that is of unknown ( at compile-time ) size .


"builtin %s only accepts a string argument"

"cpu %s is an invalid argument to builtin %s"

"hwcap %s is an invalid argument to builtin %s"

Expand the CPU builtin in FCODE and store the result in TARGET .


<s> unsigned AMDGPUTTIImpl :: getNumberOfRegisters ( bool Vec ) { if ( Vec ) return 0 ; if ( ST -> getGeneration ( ) >= AMDGPUSubtarget :: SOUTHERN_ISLANDS ) return 256 ; return 4 * 128 ; } </s>


<s> static void unicosmk_output_module_name ( FILE * file ) { const char * name = lbasename ( main_input_filename ) ; unsigned len = strlen ( name ) ; char * clean_name = alloca ( len + 2 ) ; char * ptr = clean_name ; if ( ! ISALPHA ( * name ) ) * ptr ++ = '$' ; memcpy ( ptr , name , len + 1 ) ; clean_symbol_name ( clean_name ) ; fputs ( clean_name , file ) ; } </s>

Output the module name for .ident and .end directives . We have to strip directories and add make sure that the module name starts with a letter or ' $ ' .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this , isLittle , Options ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = Subtarget . isTargetHardFloat ( ) ? FloatABI :: Hard : FloatABI :: Soft ; } </s>


<s> bool isReg ( ) const override { return Kind == REGISTER ; } </s>


<s> Optional < bool > isSyncScopeInclusion ( SyncScope :: ID A , SyncScope :: ID B ) const { const auto & AIO = getSyncScopeInclusionOrdering ( A ) ; const auto & BIO = getSyncScopeInclusionOrdering ( B ) ; if ( ! AIO || ! BIO ) return None ; bool IsAOneAddressSpace = isOneAddressSpace ( A ) ; bool IsBOneAddressSpace = isOneAddressSpace ( B ) ; return AIO . getValue ( ) >= BIO . getValue ( ) && ( IsAOneAddressSpace == IsBOneAddressSpace || ! IsAOneAddressSpace ) ; } </s>

In AMDGPU target synchronization scopes are inclusive , meaning a larger synchronization scope is inclusive of a smaller synchronization scope .


<s> bool PPCFastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { MVT VT ; if ( ! isLoadTypeLegal ( LI -> getType ( ) , VT ) ) return false ; bool IsZExt = false ; switch ( MI -> getOpcode ( ) ) { default : return false ; case PPC :: RLDICL : case PPC :: RLDICL_32_64 : { IsZExt = true ; unsigned MB = MI -> getOperand ( 3 ) . getImm ( ) ; if ( ( VT == MVT :: i8 && MB <= 56 ) || ( VT == MVT :: i16 && MB <= 48 ) || ( VT == MVT :: i32 && MB <= 32 ) ) break ; return false ; } case PPC :: RLWINM : case PPC :: RLWINM8 : { IsZExt = true ; unsigned MB = MI -> getOperand ( 3 ) . getImm ( ) ; if ( ( VT == MVT :: i8 && MB <= 24 ) || ( VT == MVT :: i16 && MB <= 16 ) ) break ; return false ; } case PPC :: EXTSB : case PPC :: EXTSB8 : case PPC :: EXTSB8_32_64 : return false ; case PPC :: EXTSH : case PPC :: EXTSH8 : case PPC :: EXTSH8_32_64 : { if ( VT != MVT :: i16 && VT != MVT :: i8 ) return false ; break ; } case PPC :: EXTSW : case PPC :: EXTSW_32 : case PPC :: EXTSW_32_64 : { if ( VT != MVT :: i32 && VT != MVT :: i16 && VT != MVT :: i8 ) return false ; break ; } } Address Addr ; if ( ! PPCComputeAddress ( LI -> getOperand ( 0 ) , Addr ) ) return false ; unsigned ResultReg = MI -> getOperand ( 0 ) . getReg ( ) ; if ( ! PPCEmitLoad ( VT , ResultReg , Addr , nullptr , IsZExt ) ) return false ; MI -> eraseFromParent ( ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> bool isValid ( ) { return isFIBase ( ) || ( isRegBase ( ) && getReg ( ) != 0 ) ; } </s>


<s> const AMDGPUCallLowering * getCallLowering ( ) const override { return CallLoweringInfo . get ( ) ; } </s>


Return an array that contains the bitmask target flag values and their names .


<s> static void sparc_fpu_init_builtins ( void ) { tree ftype = build_function_type_list ( void_type_node , build_pointer_type ( unsigned_type_node ) , 0 ) ; def_builtin ( "__builtin_load_fsr" , CODE_FOR_ldfsr , SPARC_BUILTIN_LDFSR , ftype ) ; def_builtin ( "__builtin_store_fsr" , CODE_FOR_stfsr , SPARC_BUILTIN_STFSR , ftype ) ; } </s>

Create builtin functions for FPU instructions .


"ByVal args of size 0 should have been ignored by front-end."

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> static bool arm_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( GET_MODE_CLASS ( mode1 ) == GET_MODE_CLASS ( mode2 ) ) return true ; if ( TARGET_NEON && ( VALID_NEON_DREG_MODE ( mode1 ) || VALID_NEON_QREG_MODE ( mode1 ) || VALID_NEON_STRUCT_MODE ( mode1 ) ) && ( VALID_NEON_DREG_MODE ( mode2 ) || VALID_NEON_QREG_MODE ( mode2 ) || VALID_NEON_STRUCT_MODE ( mode2 ) ) ) return true ; return false ; } </s>


<s> void aarch64_expand_epilogue ( bool for_sibcall ) { aarch64_layout_frame ( ) ; poly_int64 initial_adjust = cfun -> machine -> frame . initial_adjust ; HOST_WIDE_INT callee_adjust = cfun -> machine -> frame . callee_adjust ; poly_int64 final_adjust = cfun -> machine -> frame . final_adjust ; poly_int64 callee_offset = cfun -> machine -> frame . callee_offset ; unsigned reg1 = cfun -> machine -> frame . wb_candidate1 ; unsigned reg2 = cfun -> machine -> frame . wb_candidate2 ; rtx cfi_ops = NULL ; rtx_insn * insn ; bool can_inherit_p = ( initial_adjust . is_constant ( ) && final_adjust . is_constant ( ) && ! flag_stack_clash_protection ) ; bool need_barrier_p = maybe_ne ( get_frame_size ( ) + cfun -> machine -> frame . saved_varargs_size , 0 ) ; if ( maybe_gt ( final_adjust , crtl -> outgoing_args_size ) || cfun -> calls_alloca || crtl -> calls_eh_return ) { emit_insn ( gen_stack_tie ( stack_pointer_rtx , stack_pointer_rtx ) ) ; need_barrier_p = false ; } rtx ip0_rtx = gen_rtx_REG ( Pmode , IP0_REGNUM ) ; rtx ip1_rtx = gen_rtx_REG ( Pmode , IP1_REGNUM ) ; if ( frame_pointer_needed && ( maybe_ne ( final_adjust , 0 ) || cfun -> calls_alloca ) ) aarch64_add_offset ( Pmode , stack_pointer_rtx , hard_frame_pointer_rtx , - callee_offset , ip1_rtx , ip0_rtx , callee_adjust == 0 ) ; else aarch64_add_sp ( ip1_rtx , ip0_rtx , final_adjust , ! can_inherit_p || df_regs_ever_live_p ( IP1_REGNUM ) ) ; aarch64_restore_callee_saves ( DImode , callee_offset , R0_REGNUM , R30_REGNUM , callee_adjust != 0 , & cfi_ops ) ; aarch64_restore_callee_saves ( DFmode , callee_offset , V0_REGNUM , V31_REGNUM , callee_adjust != 0 , & cfi_ops ) ; if ( need_barrier_p ) emit_insn ( gen_stack_tie ( stack_pointer_rtx , stack_pointer_rtx ) ) ; if ( callee_adjust != 0 ) aarch64_pop_regs ( reg1 , reg2 , callee_adjust , & cfi_ops ) ; if ( callee_adjust != 0 || maybe_gt ( initial_adjust , 65536 ) ) { insn = get_last_insn ( ) ; rtx new_cfa = plus_constant ( Pmode , stack_pointer_rtx , initial_adjust ) ; REG_NOTES ( insn ) = alloc_reg_note ( REG_CFA_DEF_CFA , new_cfa , cfi_ops ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; cfi_ops = NULL ; } aarch64_add_sp ( ip0_rtx , ip1_rtx , initial_adjust , ! can_inherit_p || df_regs_ever_live_p ( IP0_REGNUM ) ) ; if ( cfi_ops ) { insn = get_last_insn ( ) ; cfi_ops = alloc_reg_note ( REG_CFA_DEF_CFA , stack_pointer_rtx , cfi_ops ) ; REG_NOTES ( insn ) = cfi_ops ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } if ( aarch64_return_address_signing_enabled ( ) && ( for_sibcall || ! TARGET_ARMV8_3 || crtl -> calls_eh_return ) ) { insn = emit_insn ( gen_autisp ( ) ) ; add_reg_note ( insn , REG_CFA_TOGGLE_RA_MANGLE , const0_rtx ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } if ( crtl -> calls_eh_return ) { emit_insn ( gen_add2_insn ( stack_pointer_rtx , EH_RETURN_STACKADJ_RTX ) ) ; } emit_use ( gen_rtx_REG ( DImode , LR_REGNUM ) ) ; if ( ! for_sibcall ) emit_jump_insn ( ret_rtx ) ; } </s>

Generate the epilogue instructions for returning from a function .


<s> int SystemZHazardRecognizer :: resourcesCost ( SUnit * SU ) { int Cost = 0 ; const MCSchedClassDesc * SC = getSchedClass ( SU ) ; if ( ! SC -> isValid ( ) ) return 0 ; if ( SU -> isUnbuffered ) Cost = ( isFPdOpPreferred_distance ( SU ) ? INT_MIN : INT_MAX ) ; else if ( CriticalResourceIdx != UINT_MAX ) { for ( TargetSchedModel :: ProcResIter PI = SchedModel -> getWriteProcResBegin ( SC ) , PE = SchedModel -> getWriteProcResEnd ( SC ) ; PI != PE ; ++ PI ) if ( PI -> ProcResourceIdx == CriticalResourceIdx ) Cost = PI -> Cycles ; } return Cost ; } </s>

Return the cost of SU in regards to processor resources usage .


<s>
SUnit
*
ConvergingVLIWScheduler
::
pickNode
(
bool
&
IsTopNode
)
{
if
(
DAG
->
top
(
)
==
DAG
->
bottom
(
)
)
{
assert
(
Top
.
Available
.
empty
(
)
&&
Top
.
Pending
.
empty
(
)
&&
Bot
.
Available
.
empty
(
)
&&
Bot
.
Pending
.
empty
(
)
&&
"ReadyQ garbage"
)
;
return
;
}
SUnit
*
SU
;
if
(
llvm
::
ForceTopDown
)
{
SU
=
Top
.
pickOnlyChoice
(
)
;
if
(
!
SU
)
{
SchedCandidate
TopCand
;
CandResult
TopResult
=
pickNodeFromQueue
(
Top
.
Available
,
DAG
->
getTopRPTracker
(
)
,
TopCand
)
;
assert
(
TopResult
!=
NoCand
&&
"failed to find the first candidate"
)
;
(
void
)
TopResult
;
SU
=
TopCand
.
SU
;
}
IsTopNode
=
true
;
}
else
if
(
llvm
::
ForceBottomUp
)
{
SU
=
Bot
.
pickOnlyChoice
(
)
;
if
(
!
SU
)
{
SchedCandidate
BotCand
;
CandResult
BotResult
=
pickNodeFromQueue
(
Bot
.
Available
,
DAG
->
getBotRPTracker
(
)
,
BotCand
)
;
assert
(
BotResult
!=
NoCand
&&
"failed to find the first candidate"
)
;
(
void
)
BotResult
;
SU
=
BotCand
.
SU
;
}
IsTopNode
=
false
;
}
else
{
SU
=
pickNodeBidrectional
(
IsTopNode
)
;
}
if
(
SU
->
isTopReady
(
)
)
Top
.
removeReady
(
SU
)
;
if
(
SU
->
isBottomReady
(
)
)
Bot
.
removeReady
(
SU
)
;
DEBUG
(
dbgs
(
)
<<
"*** "
<<
(
IsTopNode
"Top"
:
"Bottom"
)
<<
" Scheduling Instruction in cycle "
<<
(
IsTopNode
Top
.
CurrCycle
:
Bot
.
CurrCycle
)
<<
'\n'
;
SU
->
dump
(
DAG
)
)
;
return
SU
;
}
</s>

Pick the next node to schedule , or return NULL .

Hexagon
"ReadyQ garbage"
"failed to find the first candidate"
"failed to find the first candidate"
"*** "
"Top"
"Bottom"
" Scheduling Instruction in cycle "


<s>
MachineBasicBlock
::
iterator
AArch64InstrInfo
::
insertOutlinedCall
(
Module
&
M
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
&
It
,
MachineFunction
&
MF
,
const
outliner
::
Candidate
&
C
)
const
{
if
(
C
.
CallConstructionID
==
MachineOutlinerTailCall
)
{
It
=
MBB
.
insert
(
It
,
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
TCRETURNdi
)
)
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
.
addImm
(
0
)
)
;
return
It
;
}
if
(
C
.
CallConstructionID
==
MachineOutlinerNoLRSave
||
C
.
CallConstructionID
==
MachineOutlinerThunk
)
{
It
=
MBB
.
insert
(
It
,
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
BL
)
)
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
)
;
return
It
;
}
MachineBasicBlock
::
iterator
CallPt
;
MachineInstr
*
Save
;
MachineInstr
*
Restore
;
if
(
C
.
CallConstructionID
==
MachineOutlinerRegSave
)
{
unsigned
Reg
=
findRegisterToSaveLRTo
(
C
)
;
assert
(
Reg
!=
0
&&
"No callee-saved register available?"
)
;
Save
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
ORRXrs
)
,
Reg
)
.
addReg
(
AArch64
::
XZR
)
.
addReg
(
AArch64
::
LR
)
.
addImm
(
0
)
;
Restore
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
ORRXrs
)
,
AArch64
::
LR
)
.
addReg
(
AArch64
::
XZR
)
.
addReg
(
Reg
)
.
addImm
(
0
)
;
}
else
{
Save
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
STRXpre
)
)
.
addReg
(
AArch64
::
SP
,
RegState
::
Define
)
.
addReg
(
AArch64
::
LR
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
16
)
;
Restore
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
LDRXpost
)
)
.
addReg
(
AArch64
::
SP
,
RegState
::
Define
)
.
addReg
(
AArch64
::
LR
,
RegState
::
Define
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
16
)
;
}
It
=
MBB
.
insert
(
It
,
Save
)
;
It
++
;
It
=
MBB
.
insert
(
It
,
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
BL
)
)
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
)
;
CallPt
=
It
;
It
++
;
It
=
MBB
.
insert
(
It
,
Restore
)
;
return
CallPt
;
}
</s>

Insert a call to an outlined function into the program .


<s> bool ARMFastISel :: isTypeLegal ( Type * Ty , MVT & VT ) { EVT evt = TLI . getValueType ( Ty , true ) ; if ( evt == MVT :: Other || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; return TLI . isTypeLegal ( VT ) ; } </s>


<s> rtx function_arg ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int named ATTRIBUTE_UNUSED ) { rtx result = 0 ; int size , align ; int nregs = 2 ; if ( mode == BLKmode ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; align = size ; cum -> nbytes = ( cum -> nbytes + 3 ) & ~ 3 ; if ( cum -> nbytes > nregs * UNITS_PER_WORD ) return 0 ; if ( type == NULL_TREE && cum -> nbytes + size > nregs * UNITS_PER_WORD ) return 0 ; switch ( cum -> nbytes / UNITS_PER_WORD ) { case 0 : result = gen_rtx_REG ( mode , 0 ) ; break ; case 1 : result = gen_rtx_REG ( mode , 1 ) ; break ; default : result = 0 ; } return result ; } </s>

Return an RTL expression containing the register for the given mode , or 0 if the argument is to be passed on the stack . INCOMING_P is nonzero if this is an incoming argument to the current function .


<s> void arc_cpu_cpp_builtins ( cpp_reader * pfile ) { builtin_assert ( "cpu=arc" ) ; builtin_assert ( "machine=arc" ) ; builtin_define ( "__arc__" ) ; def_or_undef_macro ( pfile , NAME , CONDITION ) ; builtin_define_with_int_value ( "__ARC_TLS_REGNO__" , arc_tp_regno ) ; builtin_define ( TARGET_BIG_ENDIAN ? "__BIG_ENDIAN__" : "__LITTLE_ENDIAN__" ) ; if ( TARGET_BIG_ENDIAN ) builtin_define ( "__big_endian__" ) ; } </s>

Helper for TARGET_CPU_CPP_BUILTINS hook .


<s> bool M68kFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || TRI -> hasStackRealignment ( MF ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
static
void
preprocess_args
(
int
argc
,
char
*
*
argv
)
{
int
i
;
for
(
i
=
1
;
i
<
argc
;
i
++
)
if
(
strcmp
(
argv
[
i
]
,
"-shared"
)
==
0
)
{
share
=
1
;
break
;
}
for
(
i
=
1
;
i
<
argc
;
i
++
)
if
(
strcmp
(
argv
[
i
]
,
"-o"
)
==
0
)
{
int
len
;
i
++
;
exefilename
=
lbasename
(
argv
[
i
]
)
;
exefullfilename
=
xstrdup
(
to_host_file_spec
(
argv
[
i
]
)
)
;
if
(
share
)
addarg
(
" /share="
)
;
else
addarg
(
" /exe="
)
;
addarg
(
exefullfilename
)
;
if
(
share
)
{
char
*
ptr
;
ptr
=
strchr
(
argv
[
i
]
,
']'
)
;
if
(
ptr
==
)
ptr
=
strchr
(
argv
[
i
]
,
':'
)
;
if
(
ptr
==
)
ptr
=
strchr
(
argv
[
i
]
,
'/'
)
;
if
(
ptr
==
)
sharebasename
=
xstrdup
(
argv
[
i
]
)
;
else
sharebasename
=
xstrdup
(
ptr
+
1
)
;
len
=
strlen
(
sharebasename
)
;
if
(
strncasecmp
(
&
sharebasename
[
len
4
]
,
".exe"
,
4
)
==
0
)
sharebasename
[
len
4
]
=
0
;
for
(
ptr
=
sharebasename
;
*
ptr
;
ptr
++
)
*
ptr
=
TOUPPER
(
*
ptr
)
;
}
}
if
(
exefullfilename
==
&&
!
share
)
{
exefilename
=
"a_out.exe"
;
exefullfilename
=
"a_out.exe"
;
addarg
(
xstrdup
(
" /exe=a_out.exe"
)
)
;
}
}
</s>

Preprocess the number of args P_ARGC in ARGV . Look for special flags , etc . that must be handled first .


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( ARM :: GPRRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( ARM :: t2LDRi12 ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; return ; } if ( ARM :: GPRPairRegClass . hasSubClassEq ( RC ) ) { if ( TargetRegisterInfo :: isVirtualRegister ( DestReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( DestReg , & ARM :: GPRPair_with_gsub_1_in_rGPRRegClass ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( ARM :: t2LDRDi8 ) ) ; AddDReg ( MIB , DestReg , ARM :: gsub_0 , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , ARM :: gsub_1 , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; } ARMBaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC , TRI ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> HOST_WIDE_INT pa_function_arg_size ( machine_mode mode , const_tree type ) { HOST_WIDE_INT size ; size = mode != BLKmode ? GET_MODE_SIZE ( mode ) : int_size_in_bytes ( type ) ; return CEIL ( size , UNITS_PER_WORD ) ; } </s>

Figure out the size in words of the function argument .


<s> static rtx_insn * vax_md_asm_adjust ( vec < rtx > & outputs ATTRIBUTE_UNUSED , vec < rtx > & inputs ATTRIBUTE_UNUSED , vec < machine_mode > & input_modes ATTRIBUTE_UNUSED , vec < const char * > & constraints ATTRIBUTE_UNUSED , vec < rtx > & clobbers , HARD_REG_SET & clobbered_regs , location_t ) { clobbers . safe_push ( gen_rtx_REG ( CCmode , VAX_PSL_REGNUM ) ) ; SET_HARD_REG_BIT ( clobbered_regs , VAX_PSL_REGNUM ) ; return NULL ; } </s>

Mark PSL as clobbered for compatibility with the CC0 representation .


"For each split Type there should be exactly one VReg."

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> static bool ix86_check_avx256_register ( const_rtx exp ) { if ( GET_CODE ( exp ) == SUBREG ) exp = SUBREG_REG ( exp ) ; return ( REG_P ( exp ) && VALID_AVX256_REG_OR_OI_MODE ( GET_MODE ( exp ) ) ) ; } </s>

Check if a 256bit AVX register is referenced inside of EXP .


<s> rtx standard_80387_constant_rtx ( int idx ) { int i ; if ( ! ext_80387_constants_init ) init_ext_80387_constants ( ) ; switch ( idx ) { case 3 : case 4 : case 5 : case 6 : case 7 : i = idx - 3 ; break ; default : gcc_unreachable ( ) ; } return CONST_DOUBLE_FROM_REAL_VALUE ( ext_80387_constants_table [ i ] , XFmode ) ; } </s>

Return the CONST_DOUBLE representing the 80387 constant that is loaded by the specified special instruction . The argument IDX matches the return value from standard_80387_constant_p .


<s> static int thumb_far_jump_used_p ( void ) { rtx_insn * insn ; bool far_jump = false ; unsigned int func_size = 0 ; if ( cfun -> machine -> far_jump_used ) return 1 ; if ( ! ( ARM_DOUBLEWORD_ALIGN || reload_completed ) ) { if ( df_regs_ever_live_p ( ARG_POINTER_REGNUM ) ) cfun -> machine -> arg_pointer_live = 1 ; else if ( ! cfun -> machine -> arg_pointer_live ) return 0 ; } if ( reload_in_progress || reload_completed ) return 0 ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( JUMP_P ( insn ) && get_attr_far_jump ( insn ) == FAR_JUMP_YES ) { far_jump = true ; } func_size += get_attr_length ( insn ) ; } if ( far_jump ) { if ( ( func_size * 3 ) >= 2048 ) { cfun -> machine -> far_jump_used = 1 ; return 1 ; } } return 0 ; } </s>

Returns non-zero if the current function contains , or might contain a far jump .


<s>
unsigned
ARMMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
)
const
{
if
(
MO
.
isReg
(
)
)
{
unsigned
Reg
=
MO
.
getReg
(
)
;
unsigned
RegNo
=
CTX
.
getRegisterInfo
(
)
->
getEncodingValue
(
Reg
)
;
switch
(
Reg
)
{
default
:
return
RegNo
;
case
ARM
::
Q0
:
case
ARM
::
Q1
:
case
ARM
::
Q2
:
case
ARM
::
Q3
:
case
ARM
::
Q4
:
case
ARM
::
Q5
:
case
ARM
::
Q6
:
case
ARM
::
Q7
:
case
ARM
::
Q8
:
case
ARM
::
Q9
:
case
ARM
::
Q10
:
case
ARM
::
Q11
:
case
ARM
::
Q12
:
case
ARM
::
Q13
:
case
ARM
::
Q14
:
case
ARM
::
Q15
:
return
2
*
RegNo
;
}
}
else
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
else
if
(
MO
.
isFPImm
(
)
)
{
return
static_cast
<
unsigned
>
(
APFloat
(
MO
.
getFPImm
(
)
)
.
bitcastToAPInt
(
)
.
getHiBits
(
32
)
.
getLimitedValue
(
)
)
;
}
llvm_unreachable
(
"Unable to encode MCOperand!"
)
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> static void s390_emit_stack_probe ( rtx addr ) { rtx mem = gen_rtx_MEM ( word_mode , addr ) ; MEM_VOLATILE_P ( mem ) = 1 ; emit_insn ( gen_probe_stack ( mem ) ) ; } </s>

Emit a compare instruction with a volatile memory access as stack probe . It does not waste store tags and does not clobber any registers apart from the condition code .


<s> X86GenInstrInfo :: MachineOutlinerInstrType X86InstrInfo :: getOutliningType ( MachineInstr & MI ) const { if ( MI . isDebugValue ( ) || MI . isIndirectDebugValue ( ) ) return MachineOutlinerInstrType :: Invisible ; if ( isTailCall ( MI ) ) return MachineOutlinerInstrType :: Legal ; if ( MI . isTerminator ( ) || MI . isReturn ( ) ) { if ( MI . getParent ( ) -> succ_empty ( ) ) return MachineOutlinerInstrType :: Legal ; return MachineOutlinerInstrType :: Illegal ; } if ( MI . modifiesRegister ( X86 :: RSP , & RI ) || MI . readsRegister ( X86 :: RSP , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( X86 :: RSP ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( X86 :: RSP ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . readsRegister ( X86 :: RIP , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( X86 :: RIP ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( X86 :: RIP ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . isPosition ( ) ) return MachineOutlinerInstrType :: Illegal ; for ( const MachineOperand & MOP : MI . operands ( ) ) if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return MachineOutlinerInstrType :: Illegal ; return MachineOutlinerInstrType :: Legal ; } </s>

Returns how or if MIT should be outlined .


<s> bool SystemZTargetLowering :: isFMAFasterThanFMulAndFAdd ( EVT VT ) const { VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f32 : case MVT :: f64 : return true ; case MVT :: f128 : return false ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> static bool tryAddingSymbolicOperand ( int64_t Value , bool isBranch , uint64_t Address , uint64_t Offset , uint64_t Width , MCInst & MI , const MCDisassembler * Decoder ) { return Decoder -> tryAddingSymbolicOperand ( MI , Value , Address , isBranch , Offset , Width , 0 ) ; } </s>

Try to add a symbolic operand instead of Value to the MCInst .


<s> int nds32_can_use_bset_p ( int ival ) { int one_bit_count ; one_bit_count = popcount_hwi ( ( unsigned HOST_WIDE_INT ) ( ival ) ) ; return ( TARGET_EXT_PERF && ( one_bit_count == 1 ) ) ; } </s>

Function to check if 'bset ' instruction can be used with IVAL .


<s> static int aarch64_compute_pressure_classes ( reg_class * classes ) { int i = 0 ; classes [ i ++ ] = GENERAL_REGS ; classes [ i ++ ] = FP_REGS ; classes [ i ++ ] = PR_LO_REGS ; classes [ i ++ ] = PR_HI_REGS ; return i ; } </s>


<s> bool isUnspillableTerminatorImpl ( const MachineInstr * MI ) const override { return MI -> getOpcode ( ) == ARM :: t2LoopEndDec || MI -> getOpcode ( ) == ARM :: t2DoLoopStartTP || MI -> getOpcode ( ) == ARM :: t2WhileLoopStartLR || MI -> getOpcode ( ) == ARM :: t2WhileLoopStartTP ; } </s>

Return true if the given terminator MI is not expected to spill .


<s> std :: pair < unsigned , unsigned > MipsInstrInfo :: decomposeMachineOperandsTargetFlags ( unsigned TF ) const { return std :: make_pair ( TF , 0u ) ; } </s>

Decompose the machine operand 's target flags into two values - the direct target flag value and any of bit flags that are applied .


"\nnew fndecl target specific options:\n"

"\nold fndecl target specific options:\n"

Establish appropriate back-end context for processing the function FNDECL . The argument might be NULL to indicate processing at top level , outside of any function scope .


<s> void rs6000_emit_sCOND ( machine_mode mode , rtx operands [ ] ) { rtx condition_rtx ; machine_mode op_mode ; enum rtx_code cond_code ; rtx result = operands [ 0 ] ; condition_rtx = rs6000_generate_compare ( operands [ 1 ] , mode ) ; cond_code = GET_CODE ( condition_rtx ) ; if ( FLOAT_MODE_P ( mode ) && ! TARGET_FPRS && TARGET_HARD_FLOAT ) { rtx t ; PUT_MODE ( condition_rtx , SImode ) ; t = XEXP ( condition_rtx , 0 ) ; gcc_assert ( cond_code == NE || cond_code == EQ ) ; if ( cond_code == NE ) emit_insn ( gen_e500_flip_gt_bit ( t , t ) ) ; emit_insn ( gen_move_from_CR_gt_bit ( result , t ) ) ; return ; } if ( cond_code == NE || cond_code == GE || cond_code == LE || cond_code == GEU || cond_code == LEU || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE ) { rtx not_result = gen_reg_rtx ( CCEQmode ) ; rtx not_op , rev_cond_rtx ; machine_mode cc_mode ; cc_mode = GET_MODE ( XEXP ( condition_rtx , 0 ) ) ; rev_cond_rtx = gen_rtx_fmt_ee ( rs6000_reverse_condition ( cc_mode , cond_code ) , SImode , XEXP ( condition_rtx , 0 ) , const0_rtx ) ; not_op = gen_rtx_COMPARE ( CCEQmode , rev_cond_rtx , const0_rtx ) ; emit_insn ( gen_rtx_SET ( not_result , not_op ) ) ; condition_rtx = gen_rtx_EQ ( VOIDmode , not_result , const0_rtx ) ; } op_mode = GET_MODE ( XEXP ( operands [ 1 ] , 0 ) ) ; if ( op_mode == VOIDmode ) op_mode = GET_MODE ( XEXP ( operands [ 1 ] , 1 ) ) ; if ( TARGET_POWERPC64 && ( op_mode == DImode || FLOAT_MODE_P ( mode ) ) ) { PUT_MODE ( condition_rtx , DImode ) ; convert_move ( result , condition_rtx , 0 ) ; } else { PUT_MODE ( condition_rtx , SImode ) ; emit_insn ( gen_rtx_SET ( result , condition_rtx ) ) ; } } </s>


<s> enum reg_class arm_regno_class ( int regno ) { if ( regno == PC_REGNUM ) return NO_REGS ; if ( IS_VPR_REGNUM ( regno ) ) return VPR_REG ; if ( TARGET_THUMB1 ) { if ( regno == STACK_POINTER_REGNUM ) return STACK_REG ; if ( regno == CC_REGNUM ) return CC_REG ; if ( regno < 8 ) return LO_REGS ; return HI_REGS ; } if ( TARGET_THUMB2 && regno < 8 ) return LO_REGS ; if ( regno <= LAST_ARM_REGNUM || regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return TARGET_THUMB2 ? HI_REGS : GENERAL_REGS ; if ( regno == CC_REGNUM || regno == VFPCC_REGNUM ) return TARGET_THUMB2 ? CC_REG : NO_REGS ; if ( IS_VFP_REGNUM ( regno ) ) { if ( regno <= D7_VFP_REGNUM ) return VFP_D0_D7_REGS ; else if ( regno <= LAST_LO_VFP_REGNUM ) return VFP_LO_REGS ; else return VFP_HI_REGS ; } if ( IS_IWMMXT_REGNUM ( regno ) ) return IWMMXT_REGS ; if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return IWMMXT_GR_REGS ; return NO_REGS ; } </s>

For efficiency and historical reasons LO_REGS , HI_REGS and CC_REGS are not used in arm mode .


<s> void MipsELFStreamer :: createPendingLabelRelocs ( ) { MipsTargetELFStreamer * ELFTargetStreamer = static_cast < MipsTargetELFStreamer * > ( getTargetStreamer ( ) ) ; if ( ELFTargetStreamer -> isMicroMipsEnabled ( ) ) { for ( auto Label : Labels ) { MCSymbolData & Data = getOrCreateSymbolData ( Label ) ; MCELF :: setOther ( Data , ELF :: STO_MIPS_MICROMIPS >> 2 ) ; } } Labels . clear ( ) ; } </s>

Mark labels as microMIPS , if necessary for the subtarget .


<s> const AArch64Subtarget * AArch64TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < AArch64Subtarget > ( TargetTriple , CPU , FS , * this , Subtarget . isLittleEndian ( ) ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; AArch64GISelActualAccessor * GISel = new AArch64GISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new AArch64CallLowering ( * I -> getTargetLowering ( ) ) ) ; GISel -> Legalizer . reset ( new AArch64MachineLegalizer ( ) ) ; auto * RBI = new AArch64RegisterBankInfo ( * I -> getRegisterInfo ( ) ) ; GISel -> InstSelector . reset ( new AArch64InstructionSelector ( * I , * RBI ) ) ; GISel -> RegBankInfo . reset ( RBI ) ; I -> setGISelAccessor ( * GISel ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
void
addExpr
(
MCInst
&
Inst
,
const
MCExpr
*
Expr
)
const
{
assert
(
Expr
&&
"Expr shouldn't be null!"
)
;
if
(
auto
*
CE
=
dyn_cast
<
MCConstantExpr
>
(
Expr
)
)
Inst
.
addOperand
(
MCOperand
::
createImm
(
CE
->
getValue
(
)
)
)
;
else
Inst
.
addOperand
(
MCOperand
::
createExpr
(
Expr
)
)
;
}
</s>


<s>
unsigned
AMDGPUSubtarget
::
getOccupancyWithLocalMemSize
(
uint32_t
Bytes
,
const
Function
&
F
)
const
{
const
unsigned
MaxWorkGroupSize
=
getFlatWorkGroupSizes
(
F
)
.
second
;
const
unsigned
MaxWorkGroupsPerCu
=
getMaxWorkGroupsPerCU
(
MaxWorkGroupSize
)
;
if
(
!
MaxWorkGroupsPerCu
)
return
0
;
const
unsigned
WaveSize
=
getWavefrontSize
(
)
;
unsigned
NumGroups
=
getLocalMemorySize
(
)
/
(
Bytes
Bytes
:
1u
)
;
if
(
NumGroups
==
0
)
return
1
;
NumGroups
=
std
::
min
(
MaxWorkGroupsPerCu
,
NumGroups
)
;
const
unsigned
MaxGroupNumWaves
=
(
MaxWorkGroupSize
+
WaveSize
1
)
/
WaveSize
;
unsigned
MaxWaves
=
NumGroups
*
MaxGroupNumWaves
;
MaxWaves
=
std
::
min
(
MaxWaves
,
getMaxWavesPerEU
(
)
)
;
assert
(
MaxWaves
>
0
&&
MaxWaves
<=
getMaxWavesPerEU
(
)
&&
"computed invalid occupancy"
)
;
return
MaxWaves
;
}
</s>

Inverse of getMaxLocalMemWithWaveCount .


<s>
unsigned
HexagonInstrInfo
::
createVR
(
MachineFunction
*
MF
,
MVT
VT
)
const
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
const
TargetRegisterClass
*
TRC
;
if
(
VT
==
MVT
::
i1
)
{
TRC
=
&
Hexagon
::
PredRegsRegClass
;
}
else
if
(
VT
==
MVT
::
i32
||
VT
==
MVT
::
f32
)
{
TRC
=
&
Hexagon
::
IntRegsRegClass
;
}
else
if
(
VT
==
MVT
::
i64
||
VT
==
MVT
::
f64
)
{
TRC
=
&
Hexagon
::
DoubleRegsRegClass
;
}
else
{
llvm_unreachable
(
"Cannot handle this register class"
)
;
}
unsigned
NewReg
=
MRI
.
createVirtualRegister
(
TRC
)
;
return
NewReg
;
}
</s>


<s> bool MandarinAsmPrinter :: isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { if ( MBB -> isLandingPad ( ) || MBB -> pred_empty ( ) ) return false ; MachineBasicBlock :: const_pred_iterator PI = MBB -> pred_begin ( ) , PI2 = PI ; ++ PI2 ; if ( PI2 != MBB -> pred_end ( ) ) return false ; const MachineBasicBlock * Pred = * PI ; if ( ! Pred -> isLayoutSuccessor ( MBB ) ) return false ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> isTerminator ( ) ) ; return I == Pred -> end ( ) || ! I -> isBarrier ( ) ; } </s>

isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


<s> bool isMem ( ) const override { return Kind == k_Mem ; } </s>


<s> int calc_live_regs ( int * count ) { int reg ; int live_regs_mask = 0 ; * count = 0 ; for ( reg = 0 ; reg < FIRST_PSEUDO_REGISTER ; reg ++ ) { if ( df_regs_ever_live_p ( reg ) && ! call_used_regs [ reg ] ) { ( * count ) ++ ; live_regs_mask |= ( 1 << reg ) ; if ( reg == FRAME_POINTER_REGNUM && frame_pointer_needed && TARGET_BIG ) { ( * count ) ++ ; reg ++ ; live_regs_mask |= ( 1 << reg ) ; } } } return live_regs_mask ; } </s>

Work out the registers which need to be saved , both as a mask and a count


<s> EVT getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const override { return Op . size ( ) >= 8 ? MVT :: i64 : MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> EVT VETargetLowering :: getSetCCResultType ( const DataLayout & , LLVMContext & , EVT VT ) const { return MVT :: i32 ; } </s>

Return the value type to use for ISD : :SETCC .


"Small-data allocation is disabled, but symbols "

"may have explicit section assignments...\n"

"Checking if value is in small-data, -G"

"no, small-data allocation is disabled\n"

Return true if this global address should be placed into small data/bss section .


<s> static unsigned long arm_compute_save_reg_mask ( ) { unsigned int save_reg_mask = 0 ; unsigned long func_type = arm_current_func_type ( ) ; if ( IS_NAKED ( func_type ) ) return 0 ; if ( frame_pointer_needed ) save_reg_mask |= ( 1 << ARM_HARD_FRAME_POINTER_REGNUM ) | ( 1 << IP_REGNUM ) | ( 1 << LR_REGNUM ) | ( 1 << PC_REGNUM ) ; if ( IS_VOLATILE ( func_type ) ) return save_reg_mask ; save_reg_mask |= arm_compute_save_reg0_reg12_mask ( ) ; if ( regs_ever_live [ LR_REGNUM ] || ( save_reg_mask && optimize_size && ARM_FUNC_TYPE ( func_type ) == ARM_FT_NORMAL ) ) save_reg_mask |= 1 << LR_REGNUM ; if ( cfun -> machine -> lr_save_eliminated ) save_reg_mask &= ~ ( 1 << LR_REGNUM ) ; return save_reg_mask ; } </s>

Compute a bit mask of which registers need to be saved on the stack for the current function . This is used by arm_get_frame_offsets , which may add extra registers .


<s> static void c6x_print_operand_address ( FILE * file , machine_mode mode , rtx addr ) { c6x_print_address_operand ( file , addr , mode ) ; } </s>

Output assembly language output for the address ADDR to FILE .


<s> const SparcRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool AMDGPUAnnotateUniformValues :: doInitialization ( Module & M ) { return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> void GCNPassConfig :: addPreEmitPass ( ) { addPass ( & PostRAHazardRecognizerID ) ; addPass ( createSIInsertWaitsPass ( ) , false ) ; addPass ( createSIShrinkInstructionsPass ( ) ) ; addPass ( createSILowerControlFlowPass ( ) , false ) ; addPass ( createSIDebuggerInsertNopsPass ( ) , false ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
static
void
rs6000_output_function_prologue
(
FILE
*
file
)
{
if
(
!
cfun
->
is_thunk
)
rs6000_output_savres_externs
(
file
)
;
if
(
rs6000_global_entry_point_needed_p
(
)
)
{
const
char
*
name
=
XSTR
(
XEXP
(
DECL_RTL
(
current_function_decl
)
,
0
)
,
0
)
;
(
*
targetm
.
asm_out
.
internal_label
)
(
file
,
"LCF"
,
rs6000_pic_labelno
)
;
if
(
TARGET_CMODEL
!=
CMODEL_LARGE
)
{
char
buf
[
256
]
;
ASM_GENERATE_INTERNAL_LABEL
(
buf
,
"LCF"
,
rs6000_pic_labelno
)
;
fprintf
(
file
,
"0:\taddis 2,12,.TOC.-"
)
;
assemble_name
(
file
,
buf
)
;
fprintf
(
file
,
"@ha\n"
)
;
fprintf
(
file
,
"\taddi 2,2,.TOC.-"
)
;
assemble_name
(
file
,
buf
)
;
fprintf
(
file
,
"@l\n"
)
;
}
else
{
char
buf
[
256
]
;
fprintf
(
file
,
"\t.reloc .,R_PPC64_ENTRY\n"
)
;
fprintf
(
file
,
"\tld 2,"
)
;
ASM_GENERATE_INTERNAL_LABEL
(
buf
,
"LCL"
,
rs6000_pic_labelno
)
;
assemble_name
(
file
,
buf
)
;
fprintf
(
file
,
"-"
)
;
ASM_GENERATE_INTERNAL_LABEL
(
buf
,
"LCF"
,
rs6000_pic_labelno
)
;
assemble_name
(
file
,
buf
)
;
fprintf
(
file
,
"(12)\n"
)
;
fprintf
(
file
,
"\tadd 2,2,12\n"
)
;
}
fputs
(
"\t.localentry\t"
,
file
)
;
assemble_name
(
file
,
name
)
;
fputs
(
",.-"
,
file
)
;
assemble_name
(
file
,
name
)
;
fputs
(
"\n"
,
file
)
;
}
if
(
TARGET_PROFILE_KERNEL
&&
crtl
->
profile
)
{
gcc_assert
(
DEFAULT_ABI
==
ABI_AIX
||
DEFAULT_ABI
==
ABI_ELFv2
)
;
gcc_assert
(
!
TARGET_32BIT
)
;
asm_fprintf
(
file
,
"\tmflr %s\n"
,
reg_names
[
0
]
)
;
if
(
DEFAULT_ABI
!=
ABI_ELFv2
&&
cfun
->
static_chain_decl
!=
)
{
asm_fprintf
(
file
,
"\tstd %s,24(%s)\n"
,
reg_names
[
STATIC_CHAIN_REGNUM
]
,
reg_names
[
1
]
)
;
fprintf
(
file
,
"\tbl %s\n"
,
RS6000_MCOUNT
)
;
asm_fprintf
(
file
,
"\tld %s,24(%s)\n"
,
reg_names
[
STATIC_CHAIN_REGNUM
]
,
reg_names
[
1
]
)
;
}
else
fprintf
(
file
,
"\tbl %s\n"
,
RS6000_MCOUNT
)
;
}
rs6000_pic_labelno
++
;
}
</s>


<s> void BTFDebug :: beginInstruction ( const MachineInstr * MI ) { DebugHandlerBase :: beginInstruction ( MI ) ; if ( SkipInstruction || MI -> isMetaInstruction ( ) || MI -> getFlag ( MachineInstr :: FrameSetup ) ) return ; if ( MI -> isInlineAsm ( ) ) { unsigned NumDefs = 0 ; for ( ; MI -> getOperand ( NumDefs ) . isReg ( ) && MI -> getOperand ( NumDefs ) . isDef ( ) ; ++ NumDefs ) ; const char * AsmStr = MI -> getOperand ( NumDefs ) . getSymbolName ( ) ; if ( AsmStr [ 0 ] == 0 ) return ; } if ( MI -> getOpcode ( ) == BPF :: LD_imm64 ) { processReloc ( MI -> getOperand ( 1 ) ) ; } else if ( MI -> getOpcode ( ) == BPF :: CORE_MEM || MI -> getOpcode ( ) == BPF :: CORE_ALU32_MEM || MI -> getOpcode ( ) == BPF :: CORE_SHIFT ) { processReloc ( MI -> getOperand ( 3 ) ) ; } else if ( MI -> getOpcode ( ) == BPF :: JAL ) { const MachineOperand & MO = MI -> getOperand ( 0 ) ; if ( MO . isGlobal ( ) ) { processFuncPrototypes ( dyn_cast < Function > ( MO . getGlobal ( ) ) ) ; } } const DebugLoc & DL = MI -> getDebugLoc ( ) ; if ( ! DL || PrevInstLoc == DL ) { if ( LineInfoGenerated == false ) { auto * S = MI -> getMF ( ) -> getFunction ( ) . getSubprogram ( ) ; MCSymbol * FuncLabel = Asm -> getFunctionBegin ( ) ; constructLineInfo ( S , FuncLabel , S -> getLine ( ) , 0 ) ; LineInfoGenerated = true ; } return ; } MCSymbol * LineSym = OS . getContext ( ) . createTempSymbol ( ) ; OS . EmitLabel ( LineSym ) ; auto SP = DL . get ( ) -> getScope ( ) -> getSubprogram ( ) ; constructLineInfo ( SP , LineSym , DL . getLine ( ) , DL . getCol ( ) ) ; LineInfoGenerated = true ; PrevInstLoc = DL ; } </s>


<s> void thumb_expand_movmemqi ( rtx * operands ) { rtx out = copy_to_mode_reg ( SImode , XEXP ( operands [ 0 ] , 0 ) ) ; rtx in = copy_to_mode_reg ( SImode , XEXP ( operands [ 1 ] , 0 ) ) ; HOST_WIDE_INT len = INTVAL ( operands [ 2 ] ) ; HOST_WIDE_INT offset = 0 ; while ( len >= 12 ) { emit_insn ( gen_movmem12b ( out , in , out , in ) ) ; len -= 12 ; } if ( len >= 8 ) { emit_insn ( gen_movmem8b ( out , in , out , in ) ) ; len -= 8 ; } if ( len >= 4 ) { rtx reg = gen_reg_rtx ( SImode ) ; emit_insn ( gen_movsi ( reg , gen_rtx_MEM ( SImode , in ) ) ) ; emit_insn ( gen_movsi ( gen_rtx_MEM ( SImode , out ) , reg ) ) ; len -= 4 ; offset += 4 ; } if ( len >= 2 ) { rtx reg = gen_reg_rtx ( HImode ) ; emit_insn ( gen_movhi ( reg , gen_rtx_MEM ( HImode , plus_constant ( Pmode , in , offset ) ) ) ) ; emit_insn ( gen_movhi ( gen_rtx_MEM ( HImode , plus_constant ( Pmode , out , offset ) ) , reg ) ) ; len -= 2 ; offset += 2 ; } if ( len ) { rtx reg = gen_reg_rtx ( QImode ) ; emit_insn ( gen_movqi ( reg , gen_rtx_MEM ( QImode , plus_constant ( Pmode , in , offset ) ) ) ) ; emit_insn ( gen_movqi ( gen_rtx_MEM ( QImode , plus_constant ( Pmode , out , offset ) ) , reg ) ) ; } } </s>


<s> MVT SITargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( CC != CallingConv :: AMDGPU_KERNEL && VT . isVector ( ) && VT . getVectorNumElements ( ) == 3 ) { EVT ScalarVT = VT . getScalarType ( ) ; if ( ScalarVT . getSizeInBits ( ) == 32 ) return ScalarVT . getSimpleVT ( ) ; } return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


<s> const char * csky_output_casesi ( rtx * operands ) { rtx diff_vec = PATTERN ( NEXT_INSN ( as_a < rtx_insn * > ( operands [ 0 ] ) ) ) ; gcc_assert ( GET_CODE ( diff_vec ) == ADDR_DIFF_VEC ) ; switch ( GET_MODE ( diff_vec ) ) { case E_QImode : return ( ADDR_DIFF_VEC_FLAGS ( diff_vec ) . offset_unsigned ? "jbsr\t___gnu_csky_case_uqi" : "jbsr\t___gnu_csky_case_sqi" ) ; case E_HImode : return ( ADDR_DIFF_VEC_FLAGS ( diff_vec ) . offset_unsigned ? "jbsr\t___gnu_csky_case_uhi" : "jbsr\t___gnu_csky_case_shi" ) ; case E_SImode : return "jbsr\t___gnu_csky_case_si" ; default : gcc_unreachable ( ) ; } } </s>

Emit assembly code for CASESI . This is only used on CK801 and CK802 when optimizing for size , and uses helper functions in libgcc instead of doing the control transfer inline .


<s> BitVector TOYRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( TOY :: SP ) ; Reserved . set ( TOY :: LR ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


"TargetInstrInfo::findCommutedOpIndices() can't handle bundles"

Returns true iff the routine could find two commutable operands in the given machine instruction .


<s> const MachineDomTreeNode * MBBInfo :: getNode ( ) const { return Node ; } </s>


"The number of element should not be zero."

Target-specific splitting of values into parts that fit a register storing a legal type .


"Caller should have checked for a comparison"

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> BitVector AlphaRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( Alpha :: R15 ) ; Reserved . set ( Alpha :: R30 ) ; Reserved . set ( Alpha :: R31 ) ; return Reserved ; } </s>


<s> bool NVPTXAsmPrinter :: doFinalization ( Module & M ) { bool HasDebugInfo = MMI && MMI -> hasDebugInfo ( ) ; if ( ! GlobalsEmitted ) { emitGlobals ( M ) ; GlobalsEmitted = true ; } Module :: GlobalListType & global_list = M . getGlobalList ( ) ; int i , n = global_list . size ( ) ; GlobalVariable * * gv_array = new GlobalVariable * [ n ] ; i = 0 ; for ( Module :: global_iterator I = global_list . begin ( ) , E = global_list . end ( ) ; I != E ; ++ I ) gv_array [ i ++ ] = & * I ; while ( ! global_list . empty ( ) ) global_list . remove ( global_list . begin ( ) ) ; bool ret = AsmPrinter :: doFinalization ( M ) ; for ( i = 0 ; i < n ; i ++ ) global_list . insert ( global_list . end ( ) , gv_array [ i ] ) ; clearAnnotationCache ( & M ) ; delete [ ] gv_array ; if ( HasDebugInfo ) { static_cast < NVPTXTargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) -> closeLastSection ( ) ; OutStreamer -> emitRawText ( "\t.section\t.debug_loc\t{\t}" ) ; } static_cast < NVPTXTargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) -> outputDwarfFileDirectives ( ) ; return ret ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


"RegScavenger required for long branching"

"new block should be inserted for expanding unconditional branch"

Insert an unconditional indirect branch at the end of MBB to NewDestBB .


<s> static bool arm_array_mode_supported_p ( machine_mode mode , unsigned HOST_WIDE_INT nelems ) { if ( TARGET_NEON && ( VALID_NEON_DREG_MODE ( mode ) || VALID_NEON_QREG_MODE ( mode ) ) && ( nelems >= 2 && nelems <= 4 ) ) return true ; return false ; } </s>

Implements target hook array_mode_supported_p .


<s>
static
void
avr_asm_function_end_prologue
(
FILE
*
file
)
{
if
(
cfun
->
machine
->
is_naked
)
{
fputs
(
"/* prologue: naked */\n"
,
file
)
;
}
else
{
if
(
cfun
->
machine
->
is_interrupt
)
{
fputs
(
"/* prologue: Interrupt */\n"
,
file
)
;
}
else
if
(
cfun
->
machine
->
is_signal
)
{
fputs
(
"/* prologue: Signal */\n"
,
file
)
;
}
else
fputs
(
"/* prologue: function */\n"
,
file
)
;
}
if
(
ACCUMULATE_OUTGOING_ARGS
)
fprintf
(
file
,
"/* outgoing args size = %d */\n"
,
avr_outgoing_args_size
(
)
)
;
fprintf
(
file
,
"/* frame size = "
HOST_WIDE_INT_PRINT_DEC
" */\n"
,
get_frame_size
(
)
)
;
fprintf
(
file
,
"/* stack size = %d */\n"
,
cfun
->
machine
->
stack_usage
)
;
fprintf
(
file
,
".L__stack_usage = %d\n"
,
cfun
->
machine
->
stack_usage
)
;
}
</s>

Output summary at end of function prologue .

avr
"/* prologue: naked */\n"
"/* prologue: Interrupt */\n"
"/* prologue: Signal */\n"
"/* prologue: function */\n"
"/* outgoing args size = %d */\n"
"/* frame size = "
" */\n"
"/* stack size = %d */\n"
".L__stack_usage = %d\n"


<s> const PPCInstrInfo * getInstrInfo ( ) const override { return getSubtargetImpl ( ) -> getInstrInfo ( ) ; } </s>


"selected fp16 options are incompatible"

Reconfigure global status flags from the active_target.isa .


<s> EVT AArch64TargetLowering :: getSetCCResultType ( const DataLayout & , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i32 ; if ( VT . isScalableVector ( ) ) return MVT :: getVectorVT ( MVT :: i1 , VT . getVectorElementCount ( ) ) ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> llvm :: FastISel * ARM :: createFastISel ( FunctionLoweringInfo & funcInfo ) { if ( EnableARMFastISel ) return new ARMFastISel ( funcInfo ) ; return 0 ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> void LanaiInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annotation , const MCSubtargetInfo & , raw_ostream & OS ) { if ( ! printAlias ( MI , OS ) && ! printAliasInstr ( MI , Address , OS ) ) printInstruction ( MI , Address , OS ) ; printAnnotation ( OS , Annotation ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> unsigned X86TargetLowering :: combineRepeatedFPDivisors ( ) const { return 2 ; } </s>

Indicate whether this target prefers to combine FDIVs with the same divisor .


<s>
SDValue
GBZ80TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom lower this!"
)
;
case
ISD
::
SHL
:
case
ISD
::
SRA
:
case
ISD
::
SRL
:
case
ISD
::
ROTL
:
case
ISD
::
ROTR
:
return
LowerShifts
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
FrameIndex
:
return
LowerFrameIndex
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
SDIVREM
:
case
ISD
::
UDIVREM
:
return
LowerDivRem
(
Op
,
DAG
)
;
case
ISD
::
LOAD
:
return
LowerLOAD
(
Op
,
DAG
)
;
}
return
SDValue
(
)
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

GBZ80
GB
"Don't know how to custom lower this!"
ISD::SHL
ISD::SRA
ISD::SRL
ISD::ROTL
ISD::ROTR
ISD::GlobalAddress
ISD::BlockAddress
ISD::FrameIndex
ISD::BR_CC
ISD::SELECT_CC
ISD::SETCC
ISD::VASTART
ISD::SDIVREM
ISD::UDIVREM
ISD::LOAD


<s> static void alpha_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; bool onstack = targetm . calls . must_pass_in_stack ( mode , type ) ; int increment = onstack ? 6 : ALPHA_ARG_SIZE ( mode , type ) ; * cum += increment ; if ( ! onstack && cum -> num_args < 6 ) cum -> atypes [ cum -> num_args ] = alpha_arg_type ( mode ) ; cum -> num_args += increment ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> const RegisterBankInfo :: InstructionMapping & MipsRegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const RegisterBankInfo :: InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; switch ( Opc ) { case G_ADD : case G_LOAD : case G_STORE : case G_GEP : case G_AND : case G_OR : case G_XOR : case G_SHL : case G_ASHR : case G_LSHR : case G_SDIV : case G_UDIV : case G_SREM : case G_UREM : OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; break ; case G_CONSTANT : case G_FRAME_INDEX : case G_GLOBAL_VALUE : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr } ) ; break ; case G_ICMP : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] } ) ; break ; default : return getInvalidInstructionMapping ( ) ; } return getInstructionMapping ( DefaultMappingID , 1 , OperandsMapping , NumOperands ) ; } </s>

Get the mapping of the different operands of MI on the register bank .

Mips Mips Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx 1


<s> bool SIPeepholeSDWA :: runOnMachineFunction ( MachineFunction & MF ) { const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; if ( ! ST . hasSDWA ( ) || skipFunction ( MF . getFunction ( ) ) ) return false ; MRI = & MF . getRegInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; TII = ST . getInstrInfo ( ) ; bool Ret = false ; for ( MachineBasicBlock & MBB : MF ) { bool Changed = false ; do { matchSDWAOperands ( MBB ) ; for ( const auto & OperandPair : SDWAOperands ) { const auto & Operand = OperandPair . second ; MachineInstr * PotentialMI = Operand -> potentialToConvert ( TII ) ; if ( PotentialMI && isConvertibleToSDWA ( * PotentialMI , ST ) ) { PotentialMatches [ PotentialMI ] . push_back ( Operand . get ( ) ) ; } } for ( auto & PotentialPair : PotentialMatches ) { MachineInstr & PotentialMI = * PotentialPair . first ; convertToSDWA ( PotentialMI , PotentialPair . second ) ; } PotentialMatches . clear ( ) ; SDWAOperands . clear ( ) ; Changed = ! ConvertedInstructions . empty ( ) ; if ( Changed ) Ret = true ; while ( ! ConvertedInstructions . empty ( ) ) legalizeScalarOperands ( * ConvertedInstructions . pop_back_val ( ) , ST ) ; } while ( Changed ) ; } return Ret ; } </s>

runOnMachineFunction - Emit the function body .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
ARM
::
NumTargetFixupKinds
]
=
{
{
"fixup_arm_ldst_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_ldst_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_pcrel_10_unscaled"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_pcrel_10"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_pcrel_10"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_thumb_adr_pcrel_10"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_adr_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_adr_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_condbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_uncondbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_condbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_uncondbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_br"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_bl"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_blx"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_bl"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_blx"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cb"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cp"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_bcc"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> void hppa_encode_label ( rtx sym ) { const char * str = XSTR ( sym , 0 ) ; int len = strlen ( str ) + 1 ; char * newstr , * p ; p = newstr = alloca ( len + 1 ) ; * p ++ = '@' ; strcpy ( p , str ) ; XSTR ( sym , 0 ) = ggc_alloc_string ( newstr , len ) ; } </s>

In HPUX 8.0 's shared library scheme , special relocations are needed for function labels if they might be passed to a function in a shared library ( because shared libraries do n't live in code space ) , and special magic is needed to construct their address .


<s> void X86InstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , unsigned SubIdx , const MachineInstr * Orig ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( SubIdx && TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) { DestReg = RI . getSubReg ( DestReg , SubIdx ) ; SubIdx = 0 ; } bool Clone = true ; unsigned Opc = Orig -> getOpcode ( ) ; switch ( Opc ) { default : break ; case X86 :: MOV8r0 : case X86 :: MOV16r0 : case X86 :: MOV32r0 : { if ( ! isSafeToClobberEFLAGS ( MBB , I ) ) { switch ( Opc ) { default : break ; case X86 :: MOV8r0 : Opc = X86 :: MOV8ri ; break ; case X86 :: MOV16r0 : Opc = X86 :: MOV16ri ; break ; case X86 :: MOV32r0 : Opc = X86 :: MOV32ri ; break ; } Clone = false ; } break ; } } if ( Clone ) { MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( Orig ) ; MI -> getOperand ( 0 ) . setReg ( DestReg ) ; MBB . insert ( I , MI ) ; } else { BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addImm ( 0 ) ; } MachineInstr * NewMI = prior ( I ) ; NewMI -> getOperand ( 0 ) . setSubReg ( SubIdx ) ; } </s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s> bool NVPTXAtomicLower :: runOnFunction ( Function & F ) { SmallVector < AtomicRMWInst * > LocalMemoryAtomics ; for ( Instruction & I : instructions ( F ) ) if ( AtomicRMWInst * RMWI = dyn_cast < AtomicRMWInst > ( & I ) ) if ( RMWI -> getPointerAddressSpace ( ) == ADDRESS_SPACE_LOCAL ) LocalMemoryAtomics . push_back ( RMWI ) ; bool Changed = false ; for ( AtomicRMWInst * RMWI : LocalMemoryAtomics ) Changed |= lowerAtomicRMWInst ( RMWI ) ; return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static int s390_address_cost ( rtx addr , machine_mode mode ATTRIBUTE_UNUSED , addr_space_t as ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { struct s390_address ad ; if ( ! s390_decompose_address ( addr , & ad ) ) return 1000 ; return ad . indx ? COSTS_N_INSNS ( 1 ) + 1 : COSTS_N_INSNS ( 1 ) ; } </s>

Return the cost of an address rtx ADDR .


<s> void CAHPFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterClass * RC = & CAHP :: GPRRegClass ; if ( ! isInt < 9 > ( MFI . estimateStackSize ( MF ) ) ) { int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlignment ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RegScavFI ) ; } } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> rtx rs6000_darwin64_record_arg ( CUMULATIVE_ARGS * orig_cum , const_tree type , bool named , bool retval ) { rtx rvec [ FIRST_PSEUDO_REGISTER ] ; int k = 1 , kbase = 1 ; HOST_WIDE_INT typesize = int_size_in_bytes ( type ) ; CUMULATIVE_ARGS copy_cum = * orig_cum ; CUMULATIVE_ARGS * cum = & copy_cum ; if ( ! retval && TYPE_ALIGN ( type ) >= 2 * BITS_PER_WORD && ( cum -> words % 2 ) != 0 ) cum -> words ++ ; cum -> intoffset = 0 ; cum -> use_stack = 0 ; cum -> named = named ; rs6000_darwin64_record_arg_recurse ( cum , type , 0 , rvec , & k ) ; rs6000_darwin64_record_arg_flush ( cum , typesize * BITS_PER_UNIT , rvec , & k ) ; if ( cum -> use_stack ) { if ( retval ) return NULL_RTX ; kbase = 0 ; rvec [ 0 ] = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; } if ( k > 1 || cum -> use_stack ) return gen_rtx_PARALLEL ( BLKmode , gen_rtvec_v ( k - kbase , & rvec [ kbase ] ) ) ; else return NULL_RTX ; } </s>

For the darwin64 ABI , we want to construct a PARALLEL consisting of the register ( s ) to be used for each field and subfield of a struct being passed by value , along with the offset of where the register 's value may be found in the block . FP fields go in FP register , vector fields go in vector registers , and everything else goes in int registers , packed as in memory . This code is also used for function return values . RETVAL indicates whether this is the case . Much of this is taken from the SPARC V9 port , which has a similar calling convention .


<s> void Thumb2InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { if ( RC == ARM :: GPRRegisterClass || RC == ARM :: tGPRRegisterClass || RC == ARM :: tcGPRRegisterClass || RC == ARM :: rGPRRegisterClass || RC == ARM :: GPRnopcRegisterClass ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2STRi12 ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } ARMBaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg , isKill , FI , RC , TRI ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .

ARM ARM::GPRRegisterClass ARM::tGPRRegisterClass ARM::tcGPRRegisterClass ARM::rGPRRegisterClass ARM::GPRnopcRegisterClass ARM::t2STRi12 0 ARM


<s>
SDValue
ARMTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom lower this!"
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
Subtarget
->
isTargetDarwin
(
)
LowerGlobalAddressDarwin
(
Op
,
DAG
)
:
LowerGlobalAddressELF
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
BR_JT
:
return
LowerBR_JT
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
,
VarArgsFrameIndex
)
;
case
ISD
::
MEMBARRIER
:
return
LowerMEMBARRIER
(
Op
,
DAG
,
Subtarget
)
;
case
ISD
::
FP16_TO_FP32
:
case
ISD
::
SINT_TO_FP
:
case
ISD
::
UINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
FP32_TO_FP16
:
case
ISD
::
FP_TO_SINT
:
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
)
;
case
ISD
::
FCOPYSIGN
:
return
LowerFCOPYSIGN
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
break
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
return
LowerGLOBAL_OFFSET_TABLE
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
,
Subtarget
)
;
case
ISD
::
BIT_CONVERT
:
return
ExpandBIT_CONVERT
(
Op
.
getNode
(
)
,
DAG
)
;
case
ISD
::
SHL
:
case
ISD
::
SRL
:
case
ISD
::
SRA
:
return
LowerShift
(
Op
.
getNode
(
)
,
DAG
,
Subtarget
)
;
case
ISD
::
SHL_PARTS
:
return
LowerShiftLeftParts
(
Op
,
DAG
)
;
case
ISD
::
SRL_PARTS
:
case
ISD
::
SRA_PARTS
:
return
LowerShiftRightParts
(
Op
,
DAG
)
;
case
ISD
::
CTTZ
:
return
LowerCTTZ
(
Op
.
getNode
(
)
,
DAG
,
Subtarget
)
;
case
ISD
::
VSETCC
:
return
LowerVSETCC
(
Op
,
DAG
)
;
case
ISD
::
BUILD_VECTOR
:
return
LowerBUILD_VECTOR
(
Op
,
DAG
)
;
case
ISD
::
VECTOR_SHUFFLE
:
return
LowerVECTOR_SHUFFLE
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_VECTOR_ELT
:
return
LowerEXTRACT_VECTOR_ELT
(
Op
,
DAG
)
;
case
ISD
::
CONCAT_VECTORS
:
return
LowerCONCAT_VECTORS
(
Op
,
DAG
)
;
}
return
SDValue
(
)
;
}
</s>


<s> static void s390_emit_stack_tie ( void ) { rtx mem = gen_frame_mem ( BLKmode , gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ) ; emit_insn ( gen_stack_tie ( mem ) ) ; } </s>

This ties together stack memory ( MEM with an alias set of frame_alias_set ) and the change to the stack pointer .


<s> bool X86InstrInfo :: isCoalescableExtInstr ( const MachineInstr & MI , Register & SrcReg , Register & DstReg , unsigned & SubIdx ) const { switch ( MI . getOpcode ( ) ) { default : break ; case X86 :: MOVSX16rr8 : case X86 :: MOVZX16rr8 : case X86 :: MOVSX32rr8 : case X86 :: MOVZX32rr8 : case X86 :: MOVSX64rr8 : if ( ! Subtarget . is64Bit ( ) ) return false ; LLVM_FALLTHROUGH ; case X86 :: MOVSX32rr16 : case X86 :: MOVZX32rr16 : case X86 :: MOVSX64rr16 : case X86 :: MOVSX64rr32 : { if ( MI . getOperand ( 0 ) . getSubReg ( ) || MI . getOperand ( 1 ) . getSubReg ( ) ) return false ; SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; DstReg = MI . getOperand ( 0 ) . getReg ( ) ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( "Unreachable!" ) ; case X86 :: MOVSX16rr8 : case X86 :: MOVZX16rr8 : case X86 :: MOVSX32rr8 : case X86 :: MOVZX32rr8 : case X86 :: MOVSX64rr8 : SubIdx = X86 :: sub_8bit ; break ; case X86 :: MOVSX32rr16 : case X86 :: MOVZX32rr16 : case X86 :: MOVSX64rr16 : SubIdx = X86 :: sub_16bit ; break ; case X86 :: MOVSX64rr32 : SubIdx = X86 :: sub_32bit ; break ; } return true ; } } return false ; } </s>

isCoalescableExtInstr - Return true if the instruction is a `` coalescable '' extension instruction .


<s> bool PPCTargetLowering :: isLegalAddImmediate ( int64_t Imm ) const { return isInt < 16 > ( Imm ) || isUInt < 16 > ( Imm ) ; } </s>

Return true if the specified immediate is legal add immediate , that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register .


<s> void rs6000_call_darwin_1 ( rtx value , rtx func_desc , rtx tlsarg , rtx cookie , bool sibcall ) { rtx func = func_desc ; rtx func_addr ; rtx call [ 3 ] ; rtx insn ; int cookie_val = INTVAL ( cookie ) ; bool make_island = false ; if ( ( cookie_val & CALL_LONG ) != 0 && GET_CODE ( func_desc ) == SYMBOL_REF ) { if ( darwin_emit_branch_islands && TARGET_32BIT ) make_island = true ; else { func = rs6000_longcall_ref ( func_desc , NULL_RTX ) ; cookie_val &= ~ CALL_LONG ; } } if ( GET_CODE ( func ) != SYMBOL_REF ) { func = force_reg ( Pmode , func ) ; func_addr = gen_rtx_REG ( Pmode , CTR_REGNO ) ; emit_move_insn ( func_addr , func ) ; } else func_addr = func ; call [ 0 ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_addr ) , tlsarg ) ; if ( value != NULL_RTX ) call [ 0 ] = gen_rtx_SET ( value , call [ 0 ] ) ; call [ 1 ] = gen_rtx_USE ( VOIDmode , GEN_INT ( cookie_val ) ) ; if ( sibcall ) call [ 2 ] = simple_return_rtx ; else call [ 2 ] = gen_hard_reg_clobber ( Pmode , LR_REGNO ) ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( 3 , call ) ) ; insn = emit_call_insn ( insn ) ; if ( make_island ) { tree funname = get_identifier ( XSTR ( func_desc , 0 ) ) ; if ( no_previous_def ( funname ) ) { rtx label_rtx = gen_label_rtx ( ) ; char * label_buf , temp_buf [ 256 ] ; ASM_GENERATE_INTERNAL_LABEL ( temp_buf , "L" , CODE_LABEL_NUMBER ( label_rtx ) ) ; label_buf = temp_buf [ 0 ] == '*' ? temp_buf + 1 : temp_buf ; tree labelname = get_identifier ( label_buf ) ; add_compiler_branch_island ( labelname , funname , insn_line ( ( const rtx_insn * ) insn ) ) ; } } } </s>

Expand code to perform a call under the Darwin ABI . Modulo handling of mlongcall , this is much the same as sysv . if/when the longcall optimisation is removed , we could drop this code and use the sysv case ( taking care to avoid the tls stuff ) . We can use this for sibcalls too , if needed .


<s> bool X86InstrInfo :: classifyLEAReg ( MachineInstr & MI , const MachineOperand & Src , unsigned Opc , bool AllowSP , unsigned & NewSrc , bool & isKill , bool & isUndef , MachineOperand & ImplicitOp , LiveVariables * LV ) const { MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const TargetRegisterClass * RC ; if ( AllowSP ) { RC = Opc != X86 :: LEA32r ? & X86 :: GR64RegClass : & X86 :: GR32RegClass ; } else { RC = Opc != X86 :: LEA32r ? & X86 :: GR64_NOSPRegClass : & X86 :: GR32_NOSPRegClass ; } unsigned SrcReg = Src . getReg ( ) ; if ( Opc != X86 :: LEA64_32r ) { NewSrc = SrcReg ; isKill = Src . isKill ( ) ; isUndef = Src . isUndef ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( NewSrc ) && ! MF . getRegInfo ( ) . constrainRegClass ( NewSrc , RC ) ) return false ; return true ; } if ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) ) { ImplicitOp = Src ; ImplicitOp . setImplicit ( ) ; NewSrc = getX86SubSuperRegister ( Src . getReg ( ) , 64 ) ; isKill = Src . isKill ( ) ; isUndef = Src . isUndef ( ) ; } else { NewSrc = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MachineInstr * Copy = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( NewSrc , RegState :: Define | RegState :: Undef , X86 :: sub_32bit ) . add ( Src ) ; isKill = true ; isUndef = false ; if ( LV ) LV -> replaceKillInstruction ( SrcReg , MI , * Copy ) ; } return true ; } </s>

Given an operand within a MachineInstr , insert preceding code to put it into the right format for a particular kind of LEA instruction .


<s>
unsigned
ARMCodeEmitter
::
getMachineOpValue
(
const
MachineInstr
&
MI
,
const
MachineOperand
&
MO
)
const
{
if
(
MO
.
isReg
(
)
)
return
II
->
getRegisterInfo
(
)
.
getEncodingValue
(
MO
.
getReg
(
)
)
;
else
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
else
if
(
MO
.
isGlobal
(
)
)
emitGlobalAddress
(
MO
.
getGlobal
(
)
,
ARM
::
reloc_arm_branch
,
true
,
false
)
;
else
if
(
MO
.
isSymbol
(
)
)
emitExternalSymbolAddress
(
MO
.
getSymbolName
(
)
,
ARM
::
reloc_arm_branch
)
;
else
if
(
MO
.
isCPI
(
)
)
{
const
MCInstrDesc
&
MCID
=
MI
.
getDesc
(
)
;
unsigned
Reloc
=
(
(
MCID
.
TSFlags
&
ARMII
::
FormMask
)
==
ARMII
::
VFPLdStFrm
)
ARM
::
reloc_arm_vfp_cp_entry
:
ARM
::
reloc_arm_cp_entry
;
emitConstPoolAddress
(
MO
.
getIndex
(
)
,
Reloc
)
;
}
else
if
(
MO
.
isJTI
(
)
)
emitJumpTableAddress
(
MO
.
getIndex
(
)
,
ARM
::
reloc_arm_relative
)
;
else
if
(
MO
.
isMBB
(
)
)
emitMachineBasicBlock
(
MO
.
getMBB
(
)
,
ARM
::
reloc_arm_branch
)
;
else
llvm_unreachable
(
"Unable to encode MachineOperand!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> static unsigned findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const M680x0RegisterInfo * TRI ) { const MachineFunction * MF = MBB . getParent ( ) ; if ( MF -> callsEHReturn ( ) ) return 0 ; const TargetRegisterClass & AvailableRegs = * TRI -> getRegsForTailCall ( * MF ) ; if ( MBBI == MBB . end ( ) ) return 0 ; switch ( MBBI -> getOpcode ( ) ) { default : return 0 ; case TargetOpcode :: PATCHABLE_RET : case M680x0 :: RET : { SmallSet < uint16_t , 8 > Uses ; for ( unsigned i = 0 , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } for ( auto CS : AvailableRegs ) if ( ! Uses . count ( CS ) ) return CS ; } } return 0 ; } </s>

findDeadCallerSavedReg - Return a caller-saved register that is n't live when it reaches the `` return '' instruction .


"Epilogue can only be inserted in returning blocks"


<s> static void def_or_undef_macro ( struct cpp_reader * pfile , const char * name , bool def_p ) { if ( def_p ) cpp_define ( pfile , name ) ; else cpp_undef ( pfile , name ) ; } </s>

Define or undefine macros based on the current target . If the user does # pragma GCC target , we need to adjust the macros dynamically .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"X86 DAG->DAG Instruction Selection"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static rtx hwloop_pattern_reg ( rtx_insn * insn ) { rtx reg ; if ( ! JUMP_P ( insn ) || recog_memoized ( insn ) != CODE_FOR_loop_end ) return NULL_RTX ; reg = SET_DEST ( XVECEXP ( PATTERN ( insn ) , 0 , 1 ) ) ; if ( ! REG_P ( reg ) ) return NULL_RTX ; return reg ; } </s>

A callback for the hw-doloop pass . This function examines INSN ; if it is a doloop_end pattern we recognize , return the reg rtx for the loop counter . Otherwise , return NULL_RTX .


Return an array that contains the direct target flag values and their names .


<s> bool RISCVTargetLowering :: decomposeMulByConstant ( LLVMContext & Context , EVT VT , SDValue C ) const { if ( VT . isScalarInteger ( ) ) { if ( Subtarget . hasStdExtM ( ) && VT . getSizeInBits ( ) > Subtarget . getXLen ( ) ) return false ; if ( auto * ConstNode = dyn_cast < ConstantSDNode > ( C . getNode ( ) ) ) { const APInt & Imm = ConstNode -> getAPIntValue ( ) ; if ( ( Imm + 1 ) . isPowerOf2 ( ) || ( Imm - 1 ) . isPowerOf2 ( ) || ( 1 - Imm ) . isPowerOf2 ( ) || ( - 1 - Imm ) . isPowerOf2 ( ) ) return true ; if ( Subtarget . hasStdExtM ( ) && VT . getSizeInBits ( ) >= Subtarget . getXLen ( ) ) return false ; if ( ! Imm . isSignedIntN ( 12 ) && Imm . countTrailingZeros ( ) < 12 ) { APInt ImmS = Imm . ashr ( Imm . countTrailingZeros ( ) ) ; if ( ( ImmS + 1 ) . isPowerOf2 ( ) || ( ImmS - 1 ) . isPowerOf2 ( ) || ( 1 - ImmS ) . isPowerOf2 ( ) ) return true ; } } } return false ; } </s>

Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds .


<s> void MipsTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ; const MipsSubtarget & Subtarget = TM . getSubtarget < MipsSubtarget > ( ) ; if ( Subtarget . isABI_N64 ( ) || Subtarget . isABI_N32 ( ) ) ReginfoSection = getContext ( ) . getELFSection ( ".MIPS.options" , ELF :: SHT_MIPS_OPTIONS , ELF :: SHF_ALLOC | ELF :: SHF_MIPS_NOSTRIP , SectionKind :: getMetadata ( ) ) ; else ReginfoSection = getContext ( ) . getELFSection ( ".reginfo" , ELF :: SHT_MIPS_REGINFO , ELF :: SHF_ALLOC , SectionKind :: getMetadata ( ) ) ; if ( Subtarget . isTargetNaCl ( ) ) { StaticCtorSection = getContext ( ) . getELFSection ( ".init_array" , ELF :: SHT_INIT_ARRAY , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; StaticDtorSection = getContext ( ) . getELFSection ( ".fini_array" , ELF :: SHT_FINI_ARRAY , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; } } </s>

This method must be called before any actual lowering is done .


<s> static void ix86_emit_restore_regs_using_pop ( void ) { unsigned int regno ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( GENERAL_REGNO_P ( regno ) && ix86_save_reg ( regno , false , true ) ) ix86_emit_restore_reg_using_pop ( gen_rtx_REG ( word_mode , regno ) ) ; } </s>

Emit code to restore saved registers using POP insns .


<s> bool VEInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { case VE :: EXTEND_STACK : { return expandExtendStackPseudo ( MI ) ; } case VE :: EXTEND_STACK_GUARD : { MI . eraseFromParent ( ) ; return true ; } } return false ; } </s>

This function is called for all pseudo instructions that remain after register allocation .