<s> bool PPCAsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { std :: string NewOpcode ; if ( getLexer ( ) . is ( AsmToken :: Plus ) ) { getLexer ( ) . Lex ( ) ; NewOpcode = Name ; NewOpcode += '+' ; Name = NewOpcode ; } if ( getLexer ( ) . is ( AsmToken :: Minus ) ) { getLexer ( ) . Lex ( ) ; NewOpcode = Name ; NewOpcode += '-' ; Name = NewOpcode ; } size_t Dot = Name . find ( '.' ) ; StringRef Mnemonic = Name . slice ( 0 , Dot ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( PPCOperand :: CreateTokenWithStringCopy ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; else Operands . push_back ( PPCOperand :: CreateToken ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; if ( Dot != StringRef :: npos ) { SMLoc DotLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Dot ) ; StringRef DotStr = Name . slice ( Dot , StringRef :: npos ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( PPCOperand :: CreateTokenWithStringCopy ( DotStr , DotLoc , isPPC64 ( ) ) ) ; else Operands . push_back ( PPCOperand :: CreateToken ( DotStr , DotLoc , isPPC64 ( ) ) ) ; } if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( ParseOperand ( Operands ) ) return true ; while ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) && getLexer ( ) . is ( AsmToken :: Comma ) ) { Lex ( ) ; if ( ParseOperand ( Operands ) ) return true ; } if ( getSTI ( ) . getFeatureBits ( ) [ PPC :: FeatureBookE ] && Operands . size ( ) == 4 && ( Name == "dcbt" || Name == "dcbtst" ) ) { std :: swap ( Operands [ 1 ] , Operands [ 3 ] ) ; std :: swap ( Operands [ 2 ] , Operands [ 1 ] ) ; } return false ; } </s>

ParseInstruction - Parse one assembly instruction .

PowerPC PPC 0 PPC PPC PPC PPC PPC PPC PPC PPC PPC::FeatureBookE 4 "dcbt" "dcbtst" 1 3 2 1


<s>
void
AArch64AsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
Value
=
adjustFixupValue
(
Fixup
,
Target
,
Value
,
Ctx
,
TheTriple
,
IsResolved
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
unsigned
FulleSizeInBytes
=
getFixupKindContainereSizeInBytes
(
Fixup
.
getKind
(
)
)
;
if
(
FulleSizeInBytes
==
0
)
{
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
else
{
assert
(
(
Offset
+
FulleSizeInBytes
)
<=
Data
.
size
(
)
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FulleSizeInBytes
&&
"Invalid fixup size!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
FulleSizeInBytes
1
i
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static void replace_constant_pool_ref ( rtx * x , rtx ref , rtx offset ) { int i , j ; const char * fmt ; gcc_assert ( * x != ref ) ; if ( GET_CODE ( * x ) == UNSPEC && XINT ( * x , 1 ) == UNSPEC_LTREF && XVECEXP ( * x , 0 , 0 ) == ref ) { * x = gen_rtx_PLUS ( Pmode , XVECEXP ( * x , 0 , 1 ) , offset ) ; return ; } if ( GET_CODE ( * x ) == PLUS && GET_CODE ( XEXP ( * x , 1 ) ) == CONST_INT && GET_CODE ( XEXP ( * x , 0 ) ) == UNSPEC && XINT ( XEXP ( * x , 0 ) , 1 ) == UNSPEC_LTREF && XVECEXP ( XEXP ( * x , 0 ) , 0 , 0 ) == ref ) { rtx addr = gen_rtx_PLUS ( Pmode , XVECEXP ( XEXP ( * x , 0 ) , 0 , 1 ) , offset ) ; * x = plus_constant ( Pmode , addr , INTVAL ( XEXP ( * x , 1 ) ) ) ; return ; } fmt = GET_RTX_FORMAT ( GET_CODE ( * x ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( * x ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'e' ) { replace_constant_pool_ref ( & XEXP ( * x , i ) , ref , offset ) ; } else if ( fmt [ i ] == 'E' ) { for ( j = 0 ; j < XVECLEN ( * x , i ) ; j ++ ) replace_constant_pool_ref ( & XVECEXP ( * x , i , j ) , ref , offset ) ; } } } </s>

Replace every reference to the annotated literal pool symbol REF in X by its base plus OFFSET .


<s> void SIAssignInterpRegsPass :: addLiveIn ( MachineFunction * MF , MachineRegisterInfo & MRI , unsigned physReg , unsigned virtReg ) { const TargetInstrInfo * TII = TM . getInstrInfo ( ) ; if ( ! MRI . isLiveIn ( physReg ) ) { MRI . addLiveIn ( physReg , virtReg ) ; MF -> front ( ) . addLiveIn ( physReg ) ; BuildMI ( MF -> front ( ) , MF -> front ( ) . begin ( ) , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , virtReg ) . addReg ( physReg ) ; } else { MRI . replaceRegWith ( virtReg , MRI . getLiveInVirtReg ( physReg ) ) ; } } </s>

addLiveIn - Add the specified register as a live-in .


<s> void init_cumulative_args ( struct sparc_args * cum , tree fntype , rtx libname ATTRIBUTE_UNUSED , tree fndecl ATTRIBUTE_UNUSED ) { cum -> words = 0 ; cum -> prototype_p = fntype && prototype_p ( fntype ) ; cum -> libcall_p = fntype == 0 ; } </s>

Handle the INIT_CUMULATIVE_ARGS macro . Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is 0 .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , LittleEndian ) , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; } </s>


<s>
void
F2003fMCAsmStreamer
::
emitValueToOffset
(
const
MCExpr
*
Offset
,
unsigned
char
Value
,
SMLoc
Loc
)
{
llvm_unreachable
(
"2003lk doesn't support this directive"
)
;
}
</s>

Emit some number of copies of Value until the byte offset Offset is reached .


<s> static const MCAsmInfo * createMCAsmInfo ( const Target & T , StringRef TT ) { Triple TheTriple ( TT ) ; bool isPPC64 = TheTriple . getArch ( ) == Triple :: ppc64 ; if ( TheTriple . getOS ( ) == Triple :: Darwin ) return new PPCMCAsmInfoDarwin ( isPPC64 ) ; return new PPCLinuxMCAsmInfo ( isPPC64 ) ; } </s>

createMCAsmInfo - Create a MCAsmInfo implementation for the specified target triple .


<s>
void
BlackfinRegisterInfo
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
const
TargetFrameLowering
*
TFI
=
MF
.
getTarget
(
)
.
getFrameLowering
(
)
;
if
(
!
TFI
->
hasReservedCallFrame
(
MF
)
)
{
int64_t
Amount
=
I
->
getOperand
(
0
)
.
getImm
(
)
;
if
(
Amount
!=
0
)
{
assert
(
Amount
%
4
==
0
&&
"Unaligned call frame size"
)
;
if
(
I
->
getOpcode
(
)
==
BF
::
ADJCALLSTACKDOWN
)
{
adjustRegister
(
MBB
,
I
,
I
->
getDebugLoc
(
)
,
BF
::
SP
,
BF
::
P1
,
Amount
)
;
}
else
{
assert
(
I
->
getOpcode
(
)
==
BF
::
ADJCALLSTACKUP
&&
"Unknown call frame pseudo instruction"
)
;
adjustRegister
(
MBB
,
I
,
I
->
getDebugLoc
(
)
,
BF
::
SP
,
BF
::
P1
,
Amount
)
;
}
}
}
MBB
.
erase
(
I
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool M68kOperand :: isReg ( ) const { return Kind == Kind :: MemOp && MemOp . Op == M68kMemOp :: Kind :: Reg ; } </s>


<s> static void riscv_emit_int_order_test ( enum rtx_code code , bool * invert_ptr , rtx target , rtx cmp0 , rtx cmp1 ) { machine_mode mode ; mode = GET_MODE ( cmp0 ) ; if ( riscv_canonicalize_int_order_test ( & code , & cmp1 , mode ) ) riscv_emit_binary ( code , target , cmp0 , cmp1 ) ; else { enum rtx_code inv_code = reverse_condition ( code ) ; if ( ! riscv_canonicalize_int_order_test ( & inv_code , & cmp1 , mode ) ) { cmp1 = force_reg ( mode , cmp1 ) ; riscv_emit_int_order_test ( code , invert_ptr , target , cmp0 , cmp1 ) ; } else if ( invert_ptr == 0 ) { rtx inv_target = riscv_force_binary ( word_mode , inv_code , cmp0 , cmp1 ) ; riscv_emit_binary ( EQ , target , inv_target , const0_rtx ) ; } else { * invert_ptr = ! * invert_ptr ; riscv_emit_binary ( inv_code , target , cmp0 , cmp1 ) ; } } } </s>

Compare CMP0 and CMP1 using ordering test CODE and store the result in TARGET . CMP0 and TARGET are register_operands . If INVERT_PTR is nonnull , it 's OK to set TARGET to the inverse of the result and flip * INVERT_PTR instead .


<s> void XCoreAsmPrinter :: emitFileDirective ( const std :: string & name ) { O << "\t.file\t\"" ; PrintEscapedString ( name , O ) ; O << "\"\n" ; } </s>

Emit `` .file assembler diretive with additioal info .


<s>
static
int
avr_address_cost
(
rtx
x
,
machine_mode
mode
ATTRIBUTE_UNUSED
,
addr_space_t
as
ATTRIBUTE_UNUSED
,
bool
speed
ATTRIBUTE_UNUSED
)
{
int
cost
=
4
;
if
(
GET_CODE
(
x
)
==
PLUS
&&
CONST_INT_P
(
XEXP
(
x
,
1
)
)
&&
(
REG_P
(
XEXP
(
x
,
0
)
)
||
SUBREG_P
(
XEXP
(
x
,
0
)
)
)
)
{
if
(
INTVAL
(
XEXP
(
x
,
1
)
)
>
MAX_LD_OFFSET
(
mode
)
)
cost
=
18
;
}
else
if
(
CONSTANT_ADDRESS_P
(
x
)
)
{
if
(
optimize
>
0
&&
io_address_operand
(
x
,
QImode
)
)
cost
=
2
;
if
(
AVR_TINY
&&
avr_address_tiny_absdata_p
(
x
,
QImode
)
)
cost
=
2
;
}
if
(
avr_log
.
address_cost
)
avr_edump
(
"\n%?: %d = %r\n"
,
cost
,
x
)
;
return
cost
;
}
</s>

Calculate the cost of a memory address .


<s> static rtx force_mode ( machine_mode mode , rtx orig ) { if ( mode == GET_MODE ( orig ) ) return orig ; if ( REGNO ( orig ) >= FIRST_PSEUDO_REGISTER ) abort ( ) ; return gen_rtx_REG ( mode , REGNO ( orig ) ) ; } </s>

Ensure mode of ORIG , a REG rtx , is MODE . Returns either ORIG or a new rtx with the correct mode .


"Frame indices can only appear as the first "

"operand of a DBG_VALUE machine instruction"

runOnMachineFunction - Emit the function body .


<s> static unsigned int m32c_hard_regno_nregs_1 ( unsigned int regno , machine_mode mode ) { if ( regno == FLG_REGNO && mode == CCmode ) return 1 ; if ( regno >= FIRST_PSEUDO_REGISTER ) return ( ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ) ; if ( regno >= MEM0_REGNO && regno <= MEM7_REGNO ) return ( GET_MODE_SIZE ( mode ) + 1 ) / 2 ; if ( GET_MODE_SIZE ( mode ) <= 1 ) return nregs_table [ regno ] . qi_regs ; if ( GET_MODE_SIZE ( mode ) <= 2 ) return nregs_table [ regno ] . hi_regs ; if ( regno == A0_REGNO && mode == SImode && TARGET_A16 ) return 2 ; if ( ( GET_MODE_SIZE ( mode ) <= 3 || mode == PSImode ) && TARGET_A24 ) return nregs_table [ regno ] . pi_regs ; if ( GET_MODE_SIZE ( mode ) <= 4 ) return nregs_table [ regno ] . si_regs ; if ( GET_MODE_SIZE ( mode ) <= 8 ) return nregs_table [ regno ] . di_regs ; return 0 ; } </s>

Implements HARD_REGNO_NREGS . This is complicated by the fact that different registers are different sizes from each other , * and * may be different sizes in different chip families .


<s> bool AMDGPUPreLegalizerCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: FailedISel ) ) return false ; auto * TPC = & getAnalysis < TargetPassConfig > ( ) ; const Function & F = MF . getFunction ( ) ; bool EnableOpt = MF . getTarget ( ) . getOptLevel ( ) != CodeGenOpt :: None && ! skipFunction ( F ) ; GISelKnownBits * KB = & getAnalysis < GISelKnownBitsAnalysis > ( ) . get ( MF ) ; MachineDominatorTree * MDT = IsOptNone ? nullptr : & getAnalysis < MachineDominatorTree > ( ) ; AMDGPUPreLegalizerCombinerInfo PCInfo ( EnableOpt , F . hasOptSize ( ) , F . hasMinSize ( ) , KB , MDT ) ; GISelCSEAnalysisWrapper & Wrapper = getAnalysis < GISelCSEAnalysisWrapperPass > ( ) . getCSEWrapper ( ) ; auto * CSEInfo = & Wrapper . get ( TPC -> getCSEConfig ( ) ) ; Combiner C ( PCInfo , TPC ) ; return C . combineMachineInstrs ( MF , CSEInfo ) ; } </s>


<s> bool nds32_n13_last_load_to_e2_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx last_def_reg = extract_nth_access_reg ( producer , - 1 ) ; return n13_consumed_by_e2_dep_p ( consumer , last_def_reg ) ; } </s>

Check dependencies from LMW ( N , N ) to E2 .


<s> bool SILowerControlFlow :: runOnMachineFunction ( MachineFunction & MF ) { const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; LIS = getAnalysisIfAvailable < LiveIntervals > ( ) ; MRI = & MF . getRegInfo ( ) ; MachineFunction :: iterator NextBB ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; BI = NextBB ) { NextBB = std :: next ( BI ) ; MachineBasicBlock & MBB = * BI ; MachineBasicBlock :: iterator I , Next , Last ; for ( I = MBB . begin ( ) , Last = MBB . end ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; switch ( MI . getOpcode ( ) ) { case AMDGPU :: SI_IF : emitIf ( MI ) ; break ; case AMDGPU :: SI_ELSE : emitElse ( MI ) ; break ; case AMDGPU :: SI_IF_BREAK : emitIfBreak ( MI ) ; break ; case AMDGPU :: SI_LOOP : emitLoop ( MI ) ; break ; case AMDGPU :: SI_END_CF : emitEndCf ( MI ) ; break ; case AMDGPU :: S_AND_B64 : case AMDGPU :: S_OR_B64 : combineMasks ( MI ) ; Last = I ; continue ; default : Last = I ; continue ; } Next = ( Last == MBB . end ( ) ) ? MBB . begin ( ) : Last ; } } return true ; } </s>


<s> static bool aarch_macro_fusion_pair_p ( rtx_insn * prev , rtx_insn * curr ) { rtx prev_set = single_set ( prev ) ; rtx curr_set = single_set ( curr ) ; if ( ! prev_set || ! curr_set ) return false ; if ( any_condjump_p ( curr ) ) return false ; if ( ! arm_macro_fusion_p ( ) ) return false ; if ( current_tune -> fusible_ops & tune_params :: FUSE_MOVW_MOVT && arm_sets_movw_movt_fusible_p ( prev_set , curr_set ) ) return true ; return false ; } </s>

Implement TARGET_SCHED_MACRO_FUSION_PAIR_P . Return true if PREV and CURR should be kept together during scheduling .


<s>
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
WebAssemblyTargetLowering
::
getRegForInlineAsmConstraint
(
const
TargetRegisterInfo
*
TRI
,
StringRef
Constraint
,
MVT
VT
)
const
{
if
(
Constraint
.
size
(
)
==
1
)
{
switch
(
Constraint
[
0
]
)
{
case
'r'
:
assert
(
VT
!=
MVT
::
iPTR
&&
"Pointer MVT not expected here"
)
;
if
(
Subtarget
->
hasSIMD128
(
)
&&
VT
.
isVector
(
)
)
{
if
(
VT
.
getSizeInBits
(
)
==
128
)
return
std
::
make_pair
(
0U
,
&
WebAssembly
::
V128RegClass
)
;
}
if
(
VT
.
isInteger
(
)
&&
!
VT
.
isVector
(
)
)
{
if
(
VT
.
getSizeInBits
(
)
<=
32
)
return
std
::
make_pair
(
0U
,
&
WebAssembly
::
I32RegClass
)
;
if
(
VT
.
getSizeInBits
(
)
<=
64
)
return
std
::
make_pair
(
0U
,
&
WebAssembly
::
I64RegClass
)
;
}
if
(
VT
.
isFloatingPoint
(
)
&&
!
VT
.
isVector
(
)
)
{
switch
(
VT
.
getSizeInBits
(
)
)
{
case
32
:
return
std
::
make_pair
(
0U
,
&
WebAssembly
::
F32RegClass
)
;
case
64
:
return
std
::
make_pair
(
0U
,
&
WebAssembly
::
F64RegClass
)
;
default
:
break
;
}
}
break
;
default
:
break
;
}
}
return
TargetLowering
::
getRegForInlineAsmConstraint
(
TRI
,
Constraint
,
VT
)
;
}
</s>

Given a physical register constraint ( e.g .


"RESTORE_QUADWORD does not define its destination"

lowerQuadwordRestore - Generate code to restore paired general register .


"%<stack_offset%> must be a multiple of 4"


<s>
StringRef
getPassName
(
)
const
override
{
return
"Cheri Addressing Mode Folder"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static void d30v_add_gc_roots ( ) { ggc_add_rtx_root ( & d30v_compare_op0 , 1 ) ; ggc_add_rtx_root ( & d30v_compare_op1 , 1 ) ; } </s>

Called to register all of our global variables with the garbage collector .


<s> static void arm_encode_section_info ( tree decl , rtx rtl , int first ) { if ( optimize > 0 && TREE_CONSTANT ( decl ) ) SYMBOL_REF_FLAG ( XEXP ( rtl , 0 ) ) = 1 ; if ( first && DECL_P ( decl ) ) { if ( TREE_CODE ( decl ) == FUNCTION_DECL && DECL_WEAK ( decl ) ) arm_encode_call_attribute ( decl , LONG_CALL_FLAG_CHAR ) ; else if ( ! TREE_PUBLIC ( decl ) ) arm_encode_call_attribute ( decl , SHORT_CALL_FLAG_CHAR ) ; } default_encode_section_info ( decl , rtl , first ) ; } </s>

Symbols in the text segment can be accessed without indirecting via the constant pool ; it may take an extra binary operation , but this is still faster than indirecting via memory . Do n't do this when not optimizing , since we wo n't be calculating al of the offsets necessary to do this simplification .


<s> bool GBZ80FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc dl ; if ( MI != MBB . end ( ) ) dl = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; GBZ80MachineFunctionInfo * MFI = MF . getInfo < GBZ80MachineFunctionInfo > ( ) ; MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; i -- ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , dl , TII . get ( GBZ80 :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s>
void
print_operand_address
(
FILE
*
file
,
rtx
addr
)
{
struct
microblaze_address_info
info
;
enum
microblaze_address_type
type
;
if
(
!
microblaze_classify_address
(
&
info
,
addr
,
GET_MODE
(
addr
)
,
1
)
)
fatal_insn
(
"insn contains an invalid address !"
,
addr
)
;
type
=
info
.
type
;
switch
(
info
.
type
)
{
case
ADDRESS_REG
:
fprintf
(
file
,
"%s,"
,
reg_names
[
REGNO
(
info
.
regA
)
]
)
;
output_addr_const
(
file
,
info
.
offset
)
;
break
;
case
ADDRESS_REG_INDEX
:
if
(
REGNO
(
info
.
regA
)
==
0
)
fprintf
(
file
,
"%s,%s"
,
reg_names
[
REGNO
(
info
.
regB
)
]
,
reg_names
[
REGNO
(
info
.
regA
)
]
)
;
else
if
(
REGNO
(
info
.
regB
)
!=
0
)
fprintf
(
file
,
"%s,%s"
,
reg_names
[
REGNO
(
info
.
regB
)
]
,
reg_names
[
REGNO
(
info
.
regA
)
]
)
;
break
;
case
ADDRESS_CONST_INT
:
fprintf
(
file
,
"%s,"
,
reg_names
[
REGNO
(
info
.
regA
)
]
)
;
output_addr_const
(
file
,
info
.
offset
)
;
break
;
case
ADDRESS_SYMBOLIC
:
case
ADDRESS_GOTOFF
:
case
ADDRESS_PLT
:
case
ADDRESS_TLS
:
if
(
info
.
regA
)
fprintf
(
file
,
"%s,"
,
reg_names
[
REGNO
(
info
.
regA
)
]
)
;
output_addr_const
(
file
,
info
.
symbol
)
;
if
(
type
==
ADDRESS_GOTOFF
)
{
fputs
(
"@GOT"
,
file
)
;
}
else
if
(
type
==
ADDRESS_PLT
)
{
fputs
(
"@PLT"
,
file
)
;
}
else
if
(
type
==
ADDRESS_TLS
)
{
switch
(
info
.
tls_type
)
{
case
TLS_GD
:
fputs
(
"@TLSGD"
,
file
)
;
break
;
case
TLS_LDM
:
fputs
(
"@TLSLDM"
,
file
)
;
break
;
case
TLS_DTPREL
:
fputs
(
"@TLSDTPREL"
,
file
)
;
break
;
default
:
abort
(
)
;
break
;
}
}
break
;
case
ADDRESS_INVALID
:
fatal_insn
(
"invalid address"
,
addr
)
;
break
;
}
}
</s>

Print the operand address represented by the rtx addr


"%<builtin_return_address%> contains only 2 bytes"

Return contents of MEM at frame pointer + stack size + 1 ( +2 if 3-byte PC ) . This is return address of function .


<s> bool AMDGPUAnnotateKernelFeatures :: runOnModule ( Module & M ) { Triple TT ( M . getTargetTriple ( ) ) ; static const StringRef IntrinsicToAttr [ ] [ 2 ] = { { "llvm.amdgcn.workitem.id.y" , "amdgpu-work-item-id-y" } , { "llvm.amdgcn.workitem.id.z" , "amdgpu-work-item-id-z" } , { "llvm.amdgcn.workgroup.id.y" , "amdgpu-work-group-id-y" } , { "llvm.amdgcn.workgroup.id.z" , "amdgpu-work-group-id-z" } , { "llvm.r600.read.tgid.y" , "amdgpu-work-group-id-y" } , { "llvm.r600.read.tgid.z" , "amdgpu-work-group-id-z" } , { "llvm.r600.read.tidig.y" , "amdgpu-work-item-id-y" } , { "llvm.r600.read.tidig.z" , "amdgpu-work-item-id-z" } } ; static const StringRef HSAIntrinsicToAttr [ ] [ 2 ] = { { "llvm.amdgcn.dispatch.ptr" , "amdgpu-dispatch-ptr" } , { "llvm.amdgcn.queue.ptr" , "amdgpu-queue-ptr" } , { "llvm.amdgcn.dispatch.id" , "amdgpu-dispatch-id" } , { "llvm.trap" , "amdgpu-queue-ptr" } , { "llvm.debugtrap" , "amdgpu-queue-ptr" } } ; bool Changed = addAttrsForIntrinsics ( M , IntrinsicToAttr ) ; if ( TT . getOS ( ) == Triple :: AMDHSA || TT . getOS ( ) == Triple :: Mesa3D ) { Changed |= addAttrsForIntrinsics ( M , HSAIntrinsicToAttr ) ; for ( Function & F : M ) { if ( F . hasFnAttribute ( "amdgpu-queue-ptr" ) ) continue ; bool HasApertureRegs = TM && TM -> getSubtarget < AMDGPUSubtarget > ( F ) . hasApertureRegs ( ) ; if ( ! HasApertureRegs && hasAddrSpaceCast ( F ) ) F . addFnAttr ( "amdgpu-queue-ptr" ) ; } } return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> DecodeStatus AArch64Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CS ) const { CommentStream = & CS ; Size = 0 ; if ( Bytes . size ( ) < 4 ) return Fail ; Size = 4 ; uint32_t Insn = ( Bytes [ 3 ] << 24 ) | ( Bytes [ 2 ] << 16 ) | ( Bytes [ 1 ] << 8 ) | ( Bytes [ 0 ] << 0 ) ; const uint8_t * Tables [ ] = { DecoderTable32 , DecoderTableFallback32 } ; for ( auto Table : Tables ) { DecodeStatus Result = decodeInstruction ( Table , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s>
const
char
*
mcore_output_move
(
rtx
insn
ATTRIBUTE_UNUSED
,
rtx
operands
[
]
,
enum
machine_mode
mode
ATTRIBUTE_UNUSED
)
{
rtx
dst
=
operands
[
0
]
;
rtx
src
=
operands
[
1
]
;
if
(
GET_CODE
(
dst
)
==
REG
)
{
if
(
GET_CODE
(
src
)
==
REG
)
{
if
(
REGNO
(
src
)
==
CC_REG
)
return
"mvc\t%0"
;
else
return
"mov\t%0,%1"
;
}
else
if
(
GET_CODE
(
src
)
==
MEM
)
{
if
(
GET_CODE
(
XEXP
(
src
,
0
)
)
==
LABEL_REF
)
return
"lrw\t%0,[%1]"
;
else
switch
(
GET_MODE
(
src
)
)
{
case
SImode
:
return
"ldw\t%0,%1"
;
case
HImode
:
return
"ld.h\t%0,%1"
;
case
QImode
:
return
"ld.b\t%0,%1"
;
default
:
gcc_unreachable
(
)
;
}
}
else
if
(
GET_CODE
(
src
)
==
CONST_INT
)
{
int
x
,
y
;
if
(
CONST_OK_FOR_I
(
INTVAL
(
src
)
)
)
return
"movi\t%0,%1"
;
else
if
(
CONST_OK_FOR_M
(
INTVAL
(
src
)
)
)
return
"bgeni\t%0,%P1\t// %1 %x1"
;
else
if
(
CONST_OK_FOR_N
(
INTVAL
(
src
)
)
)
return
"bmaski\t%0,%N1\t// %1 %x1"
;
else
if
(
try_constant_tricks
(
INTVAL
(
src
)
,
&
x
,
&
y
)
)
return
output_inline_const
(
SImode
,
operands
)
;
else
return
"lrw\t%0,%x1\t// %1"
;
}
else
return
"lrw\t%0, %1"
;
}
else
if
(
GET_CODE
(
dst
)
==
MEM
)
switch
(
GET_MODE
(
dst
)
)
{
case
SImode
:
return
"stw\t%1,%0"
;
case
HImode
:
return
"st.h\t%1,%0"
;
case
QImode
:
return
"st.b\t%1,%0"
;
default
:
gcc_unreachable
(
)
;
}
gcc_unreachable
(
)
;
}
</s>


<s> bool SIInstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { return TargetInstrInfo :: isSchedulingBoundary ( MI , MBB , MF ) || MI . modifiesRegister ( AMDGPU :: EXEC , & RI ) || MI . getOpcode ( ) == AMDGPU :: S_SETREG_IMM32_B32 || MI . getOpcode ( ) == AMDGPU :: S_SETREG_B32 || changesVGPRIndexingMode ( MI ) ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> void ValueEnumerator :: purgeFunction ( ) { for ( unsigned i = NumModuleValues , e = Values . size ( ) ; i != e ; ++ i ) ValueMap . erase ( Values [ i ] . first ) ; for ( unsigned i = NumModuleMDs , e = MDs . size ( ) ; i != e ; ++ i ) MetadataMap . erase ( MDs [ i ] ) ; for ( const BasicBlock * BB : BasicBlocks ) ValueMap . erase ( BB ) ; Values . resize ( NumModuleValues ) ; MDs . resize ( NumModuleMDs ) ; BasicBlocks . clear ( ) ; NumMDStrings = 0 ; } </s>

After calling incorporateFunction , use this method to remove the most recently incorporated function from the SlotTracker .


Check whether X is a VEC_SERIES-like constant that starts at 0 and has a step in the range of INDEX . Return the index expression if so , otherwise return null .


<s>
bool
runOnFunction
(
Function
&
F
)
override
{
if
(
!
EnableScalarToIRF
)
return
false
;
if
(
skipFunction
(
F
)
)
return
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"**** ScalarToIRF Pass\n"
)
;
bool
Changed
=
false
;
for
(
BasicBlock
&
BB
:
F
)
{
Changed
|=
runOnBasicBlock
(
BB
)
;
}
return
Changed
;
}
</s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static bool aarch64_sched_can_speculate_insn ( rtx_insn * insn ) { switch ( get_attr_type ( insn ) ) { case TYPE_SDIV : case TYPE_UDIV : case TYPE_FDIVS : case TYPE_FDIVD : case TYPE_FSQRTS : case TYPE_FSQRTD : case TYPE_NEON_FP_SQRT_S : case TYPE_NEON_FP_SQRT_D : case TYPE_NEON_FP_SQRT_S_Q : case TYPE_NEON_FP_SQRT_D_Q : case TYPE_NEON_FP_DIV_S : case TYPE_NEON_FP_DIV_D : case TYPE_NEON_FP_DIV_S_Q : case TYPE_NEON_FP_DIV_D_Q : return false ; default : return true ; } } </s>

Implement TARGET_SCHED_CAN_SPECULATE_INSN . Return true if INSN can be scheduled for speculative execution . Reject the long-running division and square-root instructions .


<s> MCSymbol * BPFMCInstLower :: GetExternalSymbolSymbol ( const MachineOperand & MO ) const { return Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; } </s>

Return the MCSymbol for the specified ExternalSymbol .


<s> const MCExpr * getSubExpr ( ) const { return Expr ; } </s>

getSubExpr - Get the child of this expression .


<s> TargetLowering :: AtomicExpansionKind ARMTargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return ( Size <= ( Subtarget -> isMClass ( ) ? 32U : 64U ) ) ? AtomicExpansionKind :: LLSC : AtomicExpansionKind :: None ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> static void ea_load_store ( rtx mem , bool is_store , rtx ea_addr , rtx data_addr ) { if ( is_store ) { rtx ndirty = GEN_INT ( GET_MODE_SIZE ( GET_MODE ( mem ) ) ) ; if ( ! cache_fetch_dirty ) cache_fetch_dirty = init_one_libfunc ( "__cache_fetch_dirty" ) ; emit_library_call_value ( cache_fetch_dirty , data_addr , LCT_NORMAL , Pmode , 2 , ea_addr , EAmode , ndirty , SImode ) ; } else { if ( ! cache_fetch ) cache_fetch = init_one_libfunc ( "__cache_fetch" ) ; emit_library_call_value ( cache_fetch , data_addr , LCT_NORMAL , Pmode , 1 , ea_addr , EAmode ) ; } } </s>

MEM is known to be an __ea qualified memory access . Emit a call to fetch the ppu memory to local store , and return its address in local store .


<s> DecodeStatus AVRDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & VStream , raw_ostream & CStream ) const { uint32_t Insn ; DecodeStatus Result ; { Result = readInstruction16 ( Bytes , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( getDecoderTable ( Size ) , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) return Result ; } { Result = readInstruction32 ( Bytes , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( getDecoderTable ( Size ) , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { return Result ; } return MCDisassembler :: Fail ; } } </s>


<s> void X86PassConfig :: addPreRegAlloc ( ) { addPass ( createX86CallFrameOptimization ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> void lm32_expand_conditional_branch ( rtx operands [ ] ) { enum rtx_code code = GET_CODE ( operands [ 0 ] ) ; rtx op0 = operands [ 1 ] ; rtx op1 = operands [ 2 ] ; rtx destination = operands [ 3 ] ; gen_int_relational ( code , NULL_RTX , op0 , op1 , destination ) ; } </s>

Compare OPERANDS [ 1 ] with OPERANDS [ 2 ] using comparison code CODE and jump to OPERANDS [ 3 ] if the condition holds .


<s> bool NyuziTargetLowering :: isIntDivCheap ( EVT , AttributeList ) const { return false ; } </s>

Return true if integer divide is usually cheaper than a sequence of several shifts , adds , and multiplies for this target .


<s> void MipsAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( Fixup , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { case FK_Data_2 : case Mips :: fixup_Mips_16 : case Mips :: fixup_MICROMIPS_PC10_S1 : FullSize = 2 ; break ; case FK_Data_8 : case Mips :: fixup_Mips_64 : FullSize = 8 ; break ; case FK_Data_4 : default : FullSize = 4 ; break ; } uint64_t CurVal = 0 ; bool microMipsLEByteOrder = needsMMLEByteOrder ( ( unsigned ) Kind ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? ( microMipsLEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - 1 - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? ( microMipsLEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static rtx mem_ref ( rtx x ) { if ( GET_CODE ( x ) == SIGN_EXTEND || GET_CODE ( x ) == ZERO_EXTEND ) x = XEXP ( x , 0 ) ; if ( MEM_P ( x ) ) return x ; return NULL_RTX ; } </s>

Return the memory reference contained in X if any , zero otherwise .


<s> static tree alpha_fold_builtin_cmpbge ( unsigned HOST_WIDE_INT opint [ ] , long op_const ) { if ( op_const == 3 ) { int i , val ; for ( i = 0 , val = 0 ; i < 8 ; ++ i ) { unsigned HOST_WIDE_INT c0 = ( opint [ 0 ] >> ( i * 8 ) ) & 0xff ; unsigned HOST_WIDE_INT c1 = ( opint [ 1 ] >> ( i * 8 ) ) & 0xff ; if ( c0 >= c1 ) val |= 1 << i ; } return build_int_cst ( alpha_dimode_u , val ) ; } else if ( op_const == 2 && opint [ 1 ] == 0 ) return build_int_cst ( alpha_dimode_u , 0xff ) ; return NULL ; } </s>

Fold the builtin for the CMPBGE instruction . This is a vector comparison with an 8 bit output vector . OPINT contains the integer operands ; bit N of OP_CONST is set if OPINT [ N ] is valid .


<s> unsigned AMDGPUAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & Op , unsigned Kind ) { AMDGPUOperand & Operand = ( AMDGPUOperand & ) Op ; switch ( Kind ) { case MCK_addr64 : return Operand . isAddr64 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_gds : return Operand . isGDS ( ) ? Match_Success : Match_InvalidOperand ; case MCK_glc : return Operand . isGLC ( ) ? Match_Success : Match_InvalidOperand ; case MCK_idxen : return Operand . isIdxen ( ) ? Match_Success : Match_InvalidOperand ; case MCK_offen : return Operand . isOffen ( ) ? Match_Success : Match_InvalidOperand ; default : return Match_InvalidOperand ; } } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> bool Thumb1RegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { const TargetInstrInfo & TII = * MBB . getParent ( ) -> getTarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; AddDefaultPred ( BuildMI ( MBB , I , DL , TII . get ( ARM :: tMOVr ) ) . addReg ( ARM :: R12 , RegState :: Define ) . addReg ( Reg , RegState :: Kill ) ) ; bool done = false ; for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { if ( II -> isDebugValue ( ) ) continue ; for ( unsigned i = 0 , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( ARM :: R12 ) ) { UseMI = II ; done = true ; break ; } if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == ARM :: R12 ) { UseMI = II ; done = true ; break ; } } } AddDefaultPred ( BuildMI ( MBB , UseMI , DL , TII . get ( ARM :: tMOVr ) ) . addReg ( Reg , RegState :: Define ) . addReg ( ARM :: R12 , RegState :: Kill ) ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .


<s> bool AMDGPUTargetLowering :: shouldReduceLoadWidth ( SDNode * N , ISD :: LoadExtType , EVT NewVT ) const { unsigned NewSize = NewVT . getStoreSizeInBits ( ) ; if ( NewSize == 32 ) return true ; EVT OldVT = N -> getValueType ( 0 ) ; unsigned OldSize = OldVT . getStoreSizeInBits ( ) ; return ( OldSize < 32 ) ; } </s>

Return true if we believe it is correct and profitable to reduce the load node to a smaller type .


<s>
bool
PPCAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
{
if
(
ExtraCode
[
1
]
!=
0
)
return
true
;
switch
(
ExtraCode
[
0
]
)
{
default
:
return
true
;
case
'L'
:
O
<<
getDataLayout
(
)
.
getPointerSize
(
)
<<
"("
;
printOperand
(
MI
,
OpNo
,
O
)
;
O
<<
")"
;
return
false
;
case
'y'
:
O
<<
"0, "
;
printOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
case
'I'
:
if
(
MI
->
getOperand
(
OpNo
)
.
isImm
(
)
)
O
<<
"i"
;
return
false
;
case
'U'
:
case
'X'
:
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
return
false
;
}
}
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
O
<<
"0("
;
printOperand
(
MI
,
OpNo
,
O
)
;
O
<<
")"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> std :: pair < SDValue , SDValue > SystemZSelectionDAGInfo :: EmitTargetCodeForMemchr ( SelectionDAG & DAG , SDLoc DL , SDValue Chain , SDValue Src , SDValue Char , SDValue Length , MachinePointerInfo SrcPtrInfo ) const { EVT PtrVT = Src . getValueType ( ) ; SDVTList VTs = DAG . getVTList ( PtrVT , MVT :: Other , MVT :: Glue ) ; Length = DAG . getZExtOrTrunc ( Length , DL , PtrVT ) ; Char = DAG . getZExtOrTrunc ( Char , DL , MVT :: i32 ) ; Char = DAG . getNode ( ISD :: AND , DL , MVT :: i32 , Char , DAG . getConstant ( 255 , MVT :: i32 ) ) ; SDValue Limit = DAG . getNode ( ISD :: ADD , DL , PtrVT , Src , Length ) ; SDValue End = DAG . getNode ( SystemZISD :: SEARCH_STRING , DL , VTs , Chain , Limit , Src , Char ) ; Chain = End . getValue ( 1 ) ; SDValue Glue = End . getValue ( 2 ) ; SmallVector < SDValue , 5 > Ops ; Ops . push_back ( End ) ; Ops . push_back ( DAG . getConstant ( 0 , PtrVT ) ) ; Ops . push_back ( DAG . getConstant ( SystemZ :: CCMASK_SRST , MVT :: i32 ) ) ; Ops . push_back ( DAG . getConstant ( SystemZ :: CCMASK_SRST_FOUND , MVT :: i32 ) ) ; Ops . push_back ( Glue ) ; VTs = DAG . getVTList ( PtrVT , MVT :: Glue ) ; End = DAG . getNode ( SystemZISD :: SELECT_CCMASK , DL , VTs , & Ops [ 0 ] , Ops . size ( ) ) ; return std :: make_pair ( End , Chain ) ; } </s>

Emit target-specific code that performs a memchr , in cases where that is faster than a libcall .


<s> bool hasFusion ( ) const { return hasArithmeticBccFusion ( ) || hasArithmeticCbzFusion ( ) || hasFuseAES ( ) || hasFuseCCSelect ( ) || hasFuseLiterals ( ) ; } </s>

Return true if the CPU supports any kind of instruction fusion .


<s> bool SIAnnotateControlFlow :: doInitialization ( Module & M ) { LLVMContext & Context = M . getContext ( ) ; Void = Type :: getVoidTy ( Context ) ; Boolean = Type :: getInt1Ty ( Context ) ; Int64 = Type :: getInt64Ty ( Context ) ; ReturnStruct = StructType :: get ( Boolean , Int64 ) ; BoolTrue = ConstantInt :: getTrue ( Context ) ; BoolFalse = ConstantInt :: getFalse ( Context ) ; BoolUndef = UndefValue :: get ( Boolean ) ; Int64Zero = ConstantInt :: get ( Int64 , 0 ) ; If = Intrinsic :: getDeclaration ( & M , Intrinsic :: amdgcn_if ) ; Else = Intrinsic :: getDeclaration ( & M , Intrinsic :: amdgcn_else ) ; Break = Intrinsic :: getDeclaration ( & M , Intrinsic :: amdgcn_break ) ; IfBreak = Intrinsic :: getDeclaration ( & M , Intrinsic :: amdgcn_if_break ) ; ElseBreak = Intrinsic :: getDeclaration ( & M , Intrinsic :: amdgcn_else_break ) ; Loop = Intrinsic :: getDeclaration ( & M , Intrinsic :: amdgcn_loop ) ; EndCf = Intrinsic :: getDeclaration ( & M , Intrinsic :: amdgcn_end_cf ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> static rtx visium_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return visium_function_value_1 ( mode ) ; } </s>

Return an RTX representing the place where the library function result will be returned .


<s>
void
ARMTTIImpl
::
getUnrollingPreferences
(
Loop
*
L
,
ScalarEvolution
&
SE
,
TTI
::
UnrollingPreferences
&
UP
)
{
if
(
!
ST
->
isMClass
(
)
)
return
BasicTTIImplBase
::
getUnrollingPreferences
(
L
,
SE
,
UP
)
;
UP
.
OptSizeThreshold
=
0
;
UP
.
PartialOptSizeThreshold
=
0
;
if
(
L
->
getHeader
(
)
->
getParent
(
)
->
hasOptSize
(
)
)
return
;
if
(
!
ST
->
isThumb2
(
)
)
return
;
SmallVector
<
BasicBlock
*
,
4
>
ExitingBlocks
;
L
->
getExitingBlocks
(
ExitingBlocks
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Loop has:\n"
<<
"Blocks: "
<<
L
->
getNumBlocks
(
)
<<
"\n"
<<
"Exit blocks: "
<<
ExitingBlocks
.
size
(
)
<<
"\n"
)
;
if
(
ExitingBlocks
.
size
(
)
>
2
)
return
;
if
(
ST
->
hasBranchPredictor
(
)
&&
L
->
getNumBlocks
(
)
>
4
)
return
;
unsigned
Cost
=
0
;
for
(
auto
*
BB
:
L
->
getBlocks
(
)
)
{
for
(
auto
&
I
:
*
BB
)
{
if
(
isa
<
CallInst
>
(
I
)
||
isa
<
InvokeInst
>
(
I
)
)
{
ImmutableCallSite
CS
(
&
I
)
;
if
(
const
Function
*
F
=
CS
.
getCalledFunction
(
)
)
{
if
(
!
isLoweredToCall
(
F
)
)
continue
;
}
return
;
}
SmallVector
<
const
Value
*
,
4
>
Operands
(
I
.
value_op_begin
(
)
,
I
.
value_op_end
(
)
)
;
Cost
+=
getUserCost
(
&
I
,
Operands
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Cost of loop: "
<<
Cost
<<
"\n"
)
;
UP
.
Partial
=
true
;
UP
.
Runtime
=
true
;
UP
.
UpperBound
=
true
;
UP
.
UnrollRemainder
=
true
;
UP
.
DefaultUnrollRuntimeCount
=
4
;
UP
.
UnrollAndJam
=
true
;
UP
.
UnrollAndJamInnerLoopThreshold
=
60
;
if
(
Cost
<
12
)
UP
.
Force
=
true
;
}
</s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> const LegalizerInfo * M68kSubtarget :: getLegalizerInfo ( ) const { return Legalizer . get ( ) ; } </s>

Expose LegalizerInfo so the clients can re-use .


<s>
void
ARCRegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected"
)
;
MachineInstr
&
MI
=
*
II
;
MachineOperand
&
FrameOp
=
MI
.
getOperand
(
FIOperandNum
)
;
int
FrameIndex
=
FrameOp
.
getIndex
(
)
;
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
const
ARCInstrInfo
&
TII
=
*
MF
.
getSubtarget
<
ARCSubtarget
>
(
)
.
getInstrInfo
(
)
;
const
ARCFrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
int
Offset
=
MF
.
getFrameInfo
(
)
.
getObjectOffset
(
FrameIndex
)
;
int
ObjSize
=
MF
.
getFrameInfo
(
)
.
getObjectSize
(
FrameIndex
)
;
int
StackSize
=
MF
.
getFrameInfo
(
)
.
getStackSize
(
)
;
int
LocalFrameSize
=
MF
.
getFrameInfo
(
)
.
getLocalFrameSize
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"\nFunction         : "
<<
MF
.
getName
(
)
<<
"\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"<--------->\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
MI
<<
"\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"FrameIndex         : "
<<
FrameIndex
<<
"\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ObjSize            : "
<<
ObjSize
<<
"\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"FrameOffset        : "
<<
Offset
<<
"\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"StackSize          : "
<<
StackSize
<<
"\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"LocalFrameSize     : "
<<
LocalFrameSize
<<
"\n"
)
;
(
void
)
LocalFrameSize
;
if
(
MI
.
isDebugValue
(
)
)
{
Register
FrameReg
=
getFrameRegister
(
MF
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
)
;
return
;
}
Offset
+=
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Offset             : "
<<
Offset
<<
"\n"
<<
"<--------->\n"
)
;
Register
Reg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
assert
(
ARC
::
GPR32RegClass
.
contains
(
Reg
)
&&
"Unexpected register operand"
)
;
if
(
!
TFI
->
hasFP
(
MF
)
)
{
Offset
=
StackSize
+
Offset
;
if
(
FrameIndex
>=
0
)
assert
(
(
Offset
>=
0
&&
Offset
<
StackSize
)
&&
"SP Offset not in bounds."
)
;
}
else
{
if
(
FrameIndex
>=
0
)
{
assert
(
(
Offset
<
0
&&
Offset
<=
StackSize
)
&&
"FP Offset not in bounds."
)
;
}
}
replaceFrameIndex
(
II
,
TII
,
Reg
,
getFrameRegister
(
MF
)
,
Offset
,
StackSize
,
ObjSize
,
RS
,
SPAdj
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .

ARC
ARC
0
"Unexpected"
ARC
ARC
ARC
"\nFunction         : "
"\n"
"<--------->\n"
"\n"
"FrameIndex         : "
"\n"
"ObjSize            : "
"\n"
"FrameOffset        : "
"\n"
"StackSize          : "
"\n"
"LocalFrameSize     : "
"\n"
1
1
"Offset             : "
"\n"
"<--------->\n"
0
ARC::GPR32RegClass
"Unexpected register operand"
0
0
"SP Offset not in bounds."
0
0
"FP Offset not in bounds."


<s> bool isThumb ( ) const { return InThumbMode ; } </s>

Tests whether the target is Thumb ( little and big endian ) .


<s>
bool
ARMDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
LLVM_FALLTHROUGH
;
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_o
:
case
InlineAsm
::
Constraint_Q
:
case
InlineAsm
::
Constraint_Um
:
case
InlineAsm
::
Constraint_Un
:
case
InlineAsm
::
Constraint_Uq
:
case
InlineAsm
::
Constraint_Us
:
case
InlineAsm
::
Constraint_Ut
:
case
InlineAsm
::
Constraint_Uv
:
case
InlineAsm
::
Constraint_Uy
:
OutOps
.
push_back
(
Op
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .

ARM
ARM
"Unexpected asm memory constraint"


<s>
static
void
recombine_lvx_pattern
(
rtx_insn
*
insn
,
del_info
*
to_delete
)
{
rtx
body
=
PATTERN
(
insn
)
;
gcc_assert
(
GET_CODE
(
body
)
==
SET
&&
GET_CODE
(
SET_SRC
(
body
)
)
==
VEC_SELECT
&&
MEM_P
(
XEXP
(
SET_SRC
(
body
)
,
0
)
)
)
;
rtx
mem
=
XEXP
(
SET_SRC
(
body
)
,
0
)
;
rtx
base_reg
=
XEXP
(
mem
,
0
)
;
auto_vec
<
rtx_insn
*
>
and_insns
;
auto_vec
<
rtx
>
and_ops
;
bool
is_any_def_and
=
find_alignment_op
(
insn
,
base_reg
,
&
and_insns
,
&
and_ops
)
;
if
(
is_any_def_and
)
{
gcc_assert
(
and_insns
.
length
(
)
==
and_ops
.
length
(
)
)
;
df_ref
def
;
struct
df_insn_info
*
insn_info
=
DF_INSN_INFO_GET
(
insn
)
;
FOR_EACH_INSN_INFO_DEF
(
def
,
insn_info
)
{
struct
df_link
*
link
=
DF_REF_CHAIN
(
def
)
;
if
(
!
link
||
link
->
next
)
break
;
rtx_insn
*
swap_insn
=
DF_REF_INSN
(
link
->
ref
)
;
if
(
!
insn_is_swap_p
(
swap_insn
)
||
insn_is_load_p
(
swap_insn
)
||
insn_is_store_p
(
swap_insn
)
)
break
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace
=
true
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace_insn
=
swap_insn
;
rtx
new_reg
=
0
;
rtx
and_mask
=
0
;
for
(
unsigned
i
=
0
;
i
<
and_insns
.
length
(
)
;
i
++
)
{
rtx_insn
*
and_insn
=
and_insns
[
i
]
;
rtx
and_op
=
and_ops
[
i
]
;
rtx
and_base
=
XEXP
(
and_op
,
0
)
;
if
(
!
new_reg
)
{
new_reg
=
gen_reg_rtx
(
GET_MODE
(
and_base
)
)
;
and_mask
=
XEXP
(
and_op
,
1
)
;
}
rtx
copy
=
gen_rtx_SET
(
new_reg
,
and_base
)
;
rtx_insn
*
new_insn
=
emit_insn_after
(
copy
,
and_insn
)
;
set_block_for_insn
(
new_insn
,
BLOCK_FOR_INSN
(
and_insn
)
)
;
df_insn_rescan
(
new_insn
)
;
}
XEXP
(
mem
,
0
)
=
gen_rtx_AND
(
GET_MODE
(
new_reg
)
,
new_reg
,
and_mask
)
;
SET_SRC
(
body
)
=
mem
;
INSN_CODE
(
insn
)
=
1
;
df_insn_rescan
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"lvx opportunity found at %d\n"
,
INSN_UID
(
insn
)
)
;
}
}
}
</s>

If INSN is the load for an lvx pattern , put it in canonical form .


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> Optional < MCFixupKind > getFixupKind ( StringRef Name ) const override { return StringSwitch < Optional < MCFixupKind >> ( Name ) . Case ( "dir32" , FK_Data_4 ) . Case ( "secrel32" , FK_SecRel_4 ) . Case ( "secidx" , FK_SecRel_2 ) . Default ( MCAsmBackend :: getFixupKind ( Name ) ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s>
static
void
nvptx_assemble_decl_end
(
void
)
{
if
(
init_frag
.
offset
)
nvptx_assemble_value
(
0
,
init_frag
.
size
init_frag
.
offset
)
;
fprintf
(
asm_out_file
,
init_frag
.
started
" };\n"
:
";\n"
)
;
}
</s>

Called when the initializer for a decl has been completely output through combinations of the three functions above .


<s> static rtx gen_push ( rtx arg ) { return gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( Pmode , gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ) , arg ) ; } </s>

Code to generate prologue and epilogue sequences


<s> rtx ix86_expand_adjust_ufix_to_sfix_si ( rtx val , rtx * xorp ) { REAL_VALUE_TYPE TWO31r ; rtx two31r , tmp [ 4 ] ; machine_mode mode = GET_MODE ( val ) ; machine_mode scalarmode = GET_MODE_INNER ( mode ) ; machine_mode intmode = GET_MODE_SIZE ( mode ) == 32 ? V8SImode : V4SImode ; rtx ( * cmp ) ( rtx , rtx , rtx , rtx ) ; int i ; for ( i = 0 ; i < 3 ; i ++ ) tmp [ i ] = gen_reg_rtx ( mode ) ; real_ldexp ( & TWO31r , & dconst1 , 31 ) ; two31r = const_double_from_real_value ( TWO31r , scalarmode ) ; two31r = ix86_build_const_vector ( mode , 1 , two31r ) ; two31r = force_reg ( mode , two31r ) ; switch ( mode ) { case V8SFmode : cmp = gen_avx_maskcmpv8sf3 ; break ; case V4SFmode : cmp = gen_sse_maskcmpv4sf3 ; break ; case V4DFmode : cmp = gen_avx_maskcmpv4df3 ; break ; case V2DFmode : cmp = gen_sse2_maskcmpv2df3 ; break ; default : gcc_unreachable ( ) ; } tmp [ 3 ] = gen_rtx_LE ( mode , two31r , val ) ; emit_insn ( cmp ( tmp [ 0 ] , two31r , val , tmp [ 3 ] ) ) ; tmp [ 1 ] = expand_simple_binop ( mode , AND , tmp [ 0 ] , two31r , tmp [ 1 ] , 0 , OPTAB_DIRECT ) ; if ( intmode == V4SImode || TARGET_AVX2 ) * xorp = expand_simple_binop ( intmode , ASHIFT , gen_lowpart ( intmode , tmp [ 0 ] ) , GEN_INT ( 31 ) , NULL_RTX , 0 , OPTAB_DIRECT ) ; else { rtx two31 = GEN_INT ( ( unsigned HOST_WIDE_INT ) 1 << 31 ) ; two31 = ix86_build_const_vector ( intmode , 1 , two31 ) ; * xorp = expand_simple_binop ( intmode , AND , gen_lowpart ( intmode , tmp [ 0 ] ) , two31 , NULL_RTX , 0 , OPTAB_DIRECT ) ; } return expand_simple_binop ( mode , MINUS , val , tmp [ 1 ] , tmp [ 2 ] , 0 , OPTAB_DIRECT ) ; } </s>

Adjust a V * SFmode/V * DFmode value VAL so that * sfix_trunc * resp . fix_trunc * pattern can be used on it instead of fixuns_trunc * . This is done by doing just signed conversion if < 0x1p31 , and otherwise by subtracting 0x1p31 first and xoring in 0x80000000 from * XORP afterwards .


<s> const Function * PatmosSPMark :: getCallTarget ( const MachineInstr * MI ) const { const MachineOperand & MO = MI -> getOperand ( 2 ) ; const Function * Target = NULL ; if ( MO . isGlobal ( ) ) { Target = dyn_cast < Function > ( MO . getGlobal ( ) ) ; } else if ( MO . isSymbol ( ) ) { const char * TargetName = MO . getSymbolName ( ) ; const Module * M = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) . getParent ( ) ; Target = M -> getFunction ( TargetName ) ; } return Target ; } </s>

Return the target of the underlying call .


<s>
bool
ARMBaseInstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
TBB
=
nullptr
;
FBB
=
nullptr
;
MachineBasicBlock
::
instr_iterator
I
=
MBB
.
instr_end
(
)
;
if
(
I
==
MBB
.
instr_begin
(
)
)
return
false
;
I
;
while
(
isPredicated
(
*
I
)
||
I
->
isTerminator
(
)
||
I
->
isDebugValue
(
)
)
{
bool
CantAnalyze
=
false
;
while
(
I
->
isDebugInstr
(
)
||
!
I
->
isTerminator
(
)
)
{
if
(
I
==
MBB
.
instr_begin
(
)
)
return
false
;
I
;
}
if
(
isIndirectBranchOpcode
(
I
->
getOpcode
(
)
)
||
isJumpTableBranchOpcode
(
I
->
getOpcode
(
)
)
)
{
CantAnalyze
=
true
;
}
else
if
(
isUncondBranchOpcode
(
I
->
getOpcode
(
)
)
)
{
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
}
else
if
(
isCondBranchOpcode
(
I
->
getOpcode
(
)
)
)
{
if
(
!
Cond
.
empty
(
)
)
return
true
;
assert
(
!
FBB
&&
"FBB should have been null."
)
;
FBB
=
TBB
;
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
Cond
.
push_back
(
I
->
getOperand
(
1
)
)
;
Cond
.
push_back
(
I
->
getOperand
(
2
)
)
;
}
else
if
(
I
->
isReturn
(
)
)
{
CantAnalyze
=
true
;
}
else
{
return
true
;
}
if
(
!
isPredicated
(
*
I
)
&&
(
isUncondBranchOpcode
(
I
->
getOpcode
(
)
)
||
isIndirectBranchOpcode
(
I
->
getOpcode
(
)
)
||
isJumpTableBranchOpcode
(
I
->
getOpcode
(
)
)
||
I
->
isReturn
(
)
)
)
{
Cond
.
clear
(
)
;
FBB
=
nullptr
;
if
(
AllowModify
)
{
MachineBasicBlock
::
iterator
DI
=
std
::
next
(
I
)
;
while
(
DI
!=
MBB
.
instr_end
(
)
)
{
MachineInstr
&
InstToDelete
=
*
DI
;
++
DI
;
InstToDelete
.
eraseFromParent
(
)
;
}
}
}
if
(
CantAnalyze
)
{
if
(
AllowModify
&&
!
isPredicated
(
MBB
.
back
(
)
)
&&
isUncondBranchOpcode
(
MBB
.
back
(
)
.
getOpcode
(
)
)
&&
TBB
&&
MBB
.
isLayoutSuccessor
(
TBB
)
)
removeBranch
(
MBB
)
;
return
true
;
}
if
(
I
==
MBB
.
instr_begin
(
)
)
return
false
;
I
;
}
return
false
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> SDNode * PIC16DAGToDAGISel :: Select ( SDValue N ) { SDNode * ResNode = SelectCode ( N ) ; return ResNode ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s>
void
assignValueToReg
(
Register
ValVReg
,
Register
PhysReg
,
CCValAssign
VA
)
override
{
assert
(
VA
.
isRegLoc
(
)
&&
"Value shouldn't be assigned to reg"
)
;
assert
(
VA
.
getLocReg
(
)
==
PhysReg
&&
"Assigning to the wrong reg?"
)
;
uint64_t
ValSize
=
VA
.
getValVT
(
)
.
getFixedSizeInBits
(
)
;
uint64_t
LocSize
=
VA
.
getLocVT
(
)
.
getFixedSizeInBits
(
)
;
assert
(
ValSize
<=
64
&&
"Unsupported value size"
)
;
assert
(
LocSize
<=
64
&&
"Unsupported location size"
)
;
markPhysRegUsed
(
PhysReg
)
;
if
(
ValSize
==
LocSize
)
{
MIRBuilder
.
buildCopy
(
ValVReg
,
PhysReg
)
;
}
else
{
assert
(
ValSize
<
LocSize
&&
"Extensions not supported"
)
;
auto
PhysRegToVReg
=
MIRBuilder
.
buildCopy
(
LLT
::
scalar
(
LocSize
)
,
PhysReg
)
;
MIRBuilder
.
buildTrunc
(
ValVReg
,
PhysRegToVReg
)
;
}
}
</s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .

ARM
"Value shouldn't be assigned to reg"
"Assigning to the wrong reg?"
64
"Unsupported value size"
64
"Unsupported location size"
"Extensions not supported"


<s> static unsigned int compute_vrsave_mask ( void ) { unsigned int i , mask = 0 ; if ( DEFAULT_ABI == ABI_DARWIN && crtl -> calls_eh_return && ! TARGET_ALTIVEC ) mask |= 0xFFF ; for ( i = FIRST_ALTIVEC_REGNO ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( df_regs_ever_live_p ( i ) ) mask |= ALTIVEC_REG_BIT ( i ) ; if ( mask == 0 ) return mask ; for ( i = ALTIVEC_ARG_MIN_REG ; i < ( unsigned ) crtl -> args . info . vregno ; i ++ ) mask &= ~ ALTIVEC_REG_BIT ( i ) ; { bool yes = false ; diddle_return_value ( is_altivec_return_reg , & yes ) ; if ( yes ) mask &= ~ ALTIVEC_REG_BIT ( ALTIVEC_ARG_RETURN ) ; } return mask ; } </s>

Return a 32-bit mask of the AltiVec registers we need to set in VRSAVE . Bit n of the return value is 1 if Vn is live . The MSB in the 32-bit word is 0 .


<s>
StringRef
getPassName
(
)
const
override
{
return
"AArch64 Post Select Optimizer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"Wasn't expecting to be able to lower this!"

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool nds32_naked_function_p ( tree func ) { tree t_naked ; tree t_no_prologue ; if ( TREE_CODE ( func ) != FUNCTION_DECL ) abort ( ) ; t_naked = lookup_attribute ( "naked" , DECL_ATTRIBUTES ( func ) ) ; t_no_prologue = lookup_attribute ( "no_prologue" , DECL_ATTRIBUTES ( func ) ) ; return ( ( t_naked != NULL_TREE ) || ( t_no_prologue != NULL_TREE ) ) ; } </s>

Return true if FUNC is a naked function .


"_reflect function should not have a body"

"_reflect's return type should be integer"

"Wrong number of operands to __nvvm_reflect function"

"Format of __nvvm__reflect function not recognized"

"Format of __nvvm_reflect function not recognized"

"Format of _reflect function not recognized"

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static bool mips_hard_regno_mode_ok_uncached ( unsigned int regno , machine_mode mode ) { unsigned int size ; enum mode_class mclass ; if ( mode == CCV2mode ) return ( ISA_HAS_8CC && ST_REG_P ( regno ) && ( regno - ST_REG_FIRST ) % 2 == 0 ) ; if ( mode == CCV4mode ) return ( ISA_HAS_8CC && ST_REG_P ( regno ) && ( regno - ST_REG_FIRST ) % 4 == 0 ) ; if ( mode == CCmode ) return ISA_HAS_8CC ? ST_REG_P ( regno ) : regno == FPSW_REGNUM ; size = GET_MODE_SIZE ( mode ) ; mclass = GET_MODE_CLASS ( mode ) ; if ( GP_REG_P ( regno ) && mode != CCFmode && ! MSA_SUPPORTED_MODE_P ( mode ) ) return ( ( regno - GP_REG_FIRST ) & 1 ) == 0 || size <= UNITS_PER_WORD ; if ( FP_REG_P ( regno ) && MSA_SUPPORTED_MODE_P ( mode ) ) return true ; if ( FP_REG_P ( regno ) && ( ( ( regno - FP_REG_FIRST ) % MAX_FPRS_PER_FMT ) == 0 || ( MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG ) ) ) { if ( TARGET_O32_FP64A_ABI && size <= 4 && ( regno & 1 ) != 0 ) return false ; if ( mode == CCFmode ) return ! ( TARGET_FLOATXX && ( regno & 1 ) != 0 ) ; if ( TARGET_LOONGSON_VECTORS && ( mode == V2SImode || mode == V4HImode || mode == V8QImode || mode == DImode ) ) return true ; if ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT || mclass == MODE_VECTOR_FLOAT ) return size <= UNITS_PER_FPVALUE ; if ( mclass == MODE_INT ) return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG ; } if ( ACC_REG_P ( regno ) && ! VECTOR_MODE_P ( mode ) && ( INTEGRAL_MODE_P ( mode ) || ALL_FIXED_POINT_MODE_P ( mode ) ) ) { if ( MD_REG_P ( regno ) ) { if ( size <= UNITS_PER_WORD * 2 ) return regno == ( size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST ) ; } else { if ( size <= UNITS_PER_WORD ) return true ; if ( size <= UNITS_PER_WORD * 2 && ( ( regno - DSP_ACC_REG_FIRST ) & 1 ) == 0 ) return true ; } } if ( ALL_COP_REG_P ( regno ) ) return mclass == MODE_INT && size <= UNITS_PER_WORD ; if ( regno == GOT_VERSION_REGNUM ) return mode == SImode ; return false ; } </s>

Return true if register REGNO can store a value of mode MODE . The result of this function is cached in mips_hard_regno_mode_ok .


<s> static void store_reg ( int reg , HOST_WIDE_INT disp , int base ) { rtx insn , dest , src , basereg ; src = gen_rtx_REG ( word_mode , reg ) ; basereg = gen_rtx_REG ( Pmode , base ) ; if ( VAL_14_BITS_P ( disp ) ) { dest = gen_rtx_MEM ( word_mode , plus_constant ( basereg , disp ) ) ; insn = emit_move_insn ( dest , src ) ; } else if ( TARGET_64BIT && ! VAL_32_BITS_P ( disp ) ) { rtx delta = GEN_INT ( disp ) ; rtx tmpreg = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( tmpreg , delta ) ; insn = emit_move_insn ( tmpreg , gen_rtx_PLUS ( Pmode , tmpreg , basereg ) ) ; if ( DO_FRAME_NOTES ) { REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , tmpreg , gen_rtx_PLUS ( Pmode , basereg , delta ) ) , REG_NOTES ( insn ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } dest = gen_rtx_MEM ( word_mode , tmpreg ) ; insn = emit_move_insn ( dest , src ) ; } else { rtx delta = GEN_INT ( disp ) ; rtx high = gen_rtx_PLUS ( Pmode , basereg , gen_rtx_HIGH ( Pmode , delta ) ) ; rtx tmpreg = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( tmpreg , high ) ; dest = gen_rtx_MEM ( word_mode , gen_rtx_LO_SUM ( Pmode , tmpreg , delta ) ) ; insn = emit_move_insn ( dest , src ) ; if ( DO_FRAME_NOTES ) { REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( word_mode , gen_rtx_PLUS ( word_mode , basereg , delta ) ) , src ) , REG_NOTES ( insn ) ) ; } } if ( DO_FRAME_NOTES ) RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Emit RTL to store REG at the memory location specified by BASE+DISP . Handle case where DISP > 8k by using the add_high_const patterns . Note in DISP > 8k case , we will leave the high part of the address in % r1 . There is code in expand_hppa_ { prologue , epilogue } that knows this .


<s> static bool ft32_pass_by_reference ( cumulative_args_t cum ATTRIBUTE_UNUSED , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { unsigned HOST_WIDE_INT size ; if ( type ) { if ( AGGREGATE_TYPE_P ( type ) ) return true ; size = int_size_in_bytes ( type ) ; } else size = GET_MODE_SIZE ( mode ) ; return size > 4 * 6 ; } </s>

Return non-zero if the function argument described by TYPE is to be passed by reference .


<s> static int cris_address_cost ( rtx x , machine_mode mode ATTRIBUTE_UNUSED , addr_space_t as ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { if ( cris_base_or_autoincr_p ( x , false ) ) return 0 ; if ( MEM_P ( x ) ) return ( 2 + 4 ) / 2 ; if ( CONSTANT_P ( x ) ) return ( 2 + 4 ) / 2 ; if ( GET_CODE ( x ) == PLUS ) { rtx tem1 = XEXP ( x , 0 ) ; rtx tem2 = XEXP ( x , 1 ) ; if ( ! REG_P ( tem1 ) && GET_CODE ( tem1 ) != MULT ) tem1 = tem2 , tem2 = XEXP ( x , 0 ) ; gcc_assert ( REG_P ( tem1 ) || GET_CODE ( tem1 ) == MULT ) ; if ( ( GET_CODE ( tem1 ) == MULT && cris_biap_index_p ( tem1 , false ) ) || REG_P ( tem2 ) ) return 2 / 2 ; if ( CONST_INT_P ( tem2 ) && INTVAL ( tem2 ) < 128 && INTVAL ( tem2 ) >= - 128 ) return 2 / 2 ; if ( satisfies_constraint_L ( tem2 ) ) return ( 2 + 2 ) / 2 ; if ( CONSTANT_P ( tem2 ) ) return ( 2 + 2 + 2 ) / 2 ; return ( 2 + 2 + 2 ) / 2 ; } return 10 ; } </s>


<s> bool X86TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( ! VT . isSimple ( ) ) return false ; MVT SVT = VT . getSimpleVT ( ) ; if ( VT . getSizeInBits ( ) == 64 ) return false ; return ( SVT . getVectorNumElements ( ) == 2 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isMOVLMask ( M , SVT ) || isSHUFPMask ( M , SVT ) || isPSHUFDMask ( M , SVT ) || isPSHUFHWMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isPSHUFLWMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isPALIGNRMask ( M , SVT , Subtarget ) || isUNPCKLMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isUNPCKHMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isUNPCKL_v_undef_Mask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isUNPCKH_v_undef_Mask ( M , SVT , Subtarget -> hasInt256 ( ) ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> void riscv_d_register_target_info ( void ) { const struct d_target_info_spec handlers [ ] = { { "floatAbi" , riscv_d_handle_target_float_abi } , { NULL , NULL } , } ; d_add_target_info_handlers ( handlers ) ; } </s>


<s> static rtx aarch64_expand_sve_const_vector_sel ( rtx target , rtx src ) { gcc_assert ( CONST_VECTOR_NELTS_PER_PATTERN ( src ) == 2 ) ; machine_mode mode = GET_MODE ( src ) ; machine_mode pred_mode = aarch64_sve_pred_mode ( mode ) ; unsigned int npatterns = CONST_VECTOR_NPATTERNS ( src ) ; if ( aarch64_svpattern_for_vl ( pred_mode , npatterns ) == AARCH64_NUM_SVPATTERNS ) return NULL_RTX ; rtx_vector_builder pred_builder ( pred_mode , npatterns , 2 ) ; rtx_vector_builder true_builder ( mode , npatterns , 1 ) ; rtx_vector_builder false_builder ( mode , npatterns , 1 ) ; for ( unsigned int i = 0 ; i < npatterns ; ++ i ) { true_builder . quick_push ( CONST_VECTOR_ENCODED_ELT ( src , i ) ) ; pred_builder . quick_push ( CONST1_RTX ( BImode ) ) ; } for ( unsigned int i = 0 ; i < npatterns ; ++ i ) { false_builder . quick_push ( CONST_VECTOR_ENCODED_ELT ( src , i + npatterns ) ) ; pred_builder . quick_push ( CONST0_RTX ( BImode ) ) ; } expand_operand ops [ 4 ] ; create_output_operand ( & ops [ 0 ] , target , mode ) ; create_input_operand ( & ops [ 1 ] , true_builder . build ( ) , mode ) ; create_input_operand ( & ops [ 2 ] , false_builder . build ( ) , mode ) ; create_input_operand ( & ops [ 3 ] , pred_builder . build ( ) , pred_mode ) ; expand_insn ( code_for_vcond_mask ( mode , mode ) , 4 , ops ) ; return target ; } </s>

SRC is an SVE CONST_VECTOR that contains N `` foreground '' values followed by N `` background '' values . Try to move it into TARGET using : PTRUE PRED. < T > , VL < N > MOV TRUE. < T > , # < foreground > MOV FALSE. < T > , # < background > SEL TARGET. < T > , PRED. < T > , TRUE. < T > , FALSE. < T > The PTRUE is always a single instruction but the MOVs might need a longer sequence . If the background value is zero ( as it often is ) , the sequence can sometimes collapse to a PTRUE followed by a zero-predicated move . Return the target on success , otherwise return null .


<s> bool hasNullExportTarget ( ) const { return ! GFX11Insts ; } </s>

Return true if the target 's EXP instruction supports the NULL export target .


" was Pass-through, is now Dirty-out.\n"

runOnMachineFunction - Emit the function body .


<s> static void make_cpu_type_builtin ( const char * name , int code , enum ix86_builtin_func_type ftype , bool is_const ) { tree decl ; tree type ; type = ix86_get_builtin_func_type ( ftype ) ; decl = add_builtin_function ( name , type , code , BUILT_IN_MD , NULL , NULL_TREE ) ; gcc_assert ( decl != NULL_TREE ) ; ix86_builtins [ ( int ) code ] = decl ; TREE_READONLY ( decl ) = is_const ; } </s>

Make builtins to detect cpu type and features supported . NAME is the builtin name , CODE is the builtin code , and FTYPE is the function type of the builtin .


initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


"loadRegFromStackSlot didn't insert any code!"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static bool mep_get_move_insn ( int intrinsic , const struct cgen_insn * * cgen_insn ) { size_t i ; if ( intrinsic == mep_cmov ) { for ( i = 0 ; i < ARRAY_SIZE ( mep_cmov_insns ) ; i ++ ) if ( mep_get_intrinsic_insn ( mep_cmov_insns [ i ] , cgen_insn ) ) return true ; return false ; } return mep_get_intrinsic_insn ( intrinsic , cgen_insn ) ; } </s>

Like mep_get_intrinsic_insn , but with extra handling for moves . If INTRINSIC is mep_cmov , but there is no pure CR < - CR move insn , try using a work-alike instead . In this case , the returned insn may have three operands rather than two .


<s> bool F2003fPassConfig :: addInstSelector ( ) { addPass ( createF2003fISelDag ( getF2003fTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


"\nrs6000_secondary_reload_gpr, type = %s\n"

Convert reloads involving 64-bit gprs and misaligned offset addressing , or multiple 32-bit gprs and offsets that are too large , to use indirect addressing .


<s> const RegisterBankInfo :: ValueMapping * AMDGPURegisterBankInfo :: getValueMappingForPtr ( const MachineRegisterInfo & MRI , Register PtrReg ) const { LLT PtrTy = MRI . getType ( PtrReg ) ; unsigned Size = PtrTy . getSizeInBits ( ) ; if ( Subtarget . useFlatForGlobal ( ) || ! SITargetLowering :: isFlatGlobalAddrSpace ( PtrTy . getAddressSpace ( ) ) ) return AMDGPU :: getValueMapping ( AMDGPU :: VGPRRegBankID , Size ) ; const RegisterBank * PtrBank = getRegBank ( PtrReg , MRI , * TRI ) ; return AMDGPU :: getValueMapping ( PtrBank -> getID ( ) , Size ) ; } </s>

Return the mapping for a pointer argument .

AMDGPU AMDGPU SI AMDGPU::getValueMapping AMDGPU::VGPRRegBankID AMDGPU::getValueMapping


"SIInstrInfo::storeRegToStackSlot - Do not know how to"

Store the specified register of the given register class to the specified stack frame index .


<s> static rtx mn10300_function_value ( const_tree valtype , const_tree fn_decl_or_type ATTRIBUTE_UNUSED , bool outgoing ) { rtx rv ; machine_mode mode = TYPE_MODE ( valtype ) ; if ( ! POINTER_TYPE_P ( valtype ) ) return gen_rtx_REG ( mode , FIRST_DATA_REGNUM ) ; else if ( ! TARGET_PTR_A0D0 || ! outgoing || cfun -> returns_struct ) return gen_rtx_REG ( mode , FIRST_ADDRESS_REGNUM ) ; rv = gen_rtx_PARALLEL ( mode , rtvec_alloc ( 2 ) ) ; XVECEXP ( rv , 0 , 0 ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , FIRST_ADDRESS_REGNUM ) , GEN_INT ( 0 ) ) ; XVECEXP ( rv , 0 , 1 ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , FIRST_DATA_REGNUM ) , GEN_INT ( 0 ) ) ; return rv ; } </s>

Return the location of the function 's value . This will be either $ d0 for integer functions , $ a0 for pointers , or a PARALLEL of both $ d0 and $ a0 if the -mreturn-pointer-on-do flag is set . Note that we only return the PARALLEL for outgoing values ; we do not want callers relying on this extra copy .


<s> const Z80Subtarget * Z80TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < 512 > Key ; Key . reserve ( CPU . size ( ) + FS . size ( ) ) ; Key += CPU ; Key += FS ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < Z80Subtarget > ( TargetTriple , CPU , FS , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> void ARCInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & O ) { printInstruction ( MI , Address , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool TLCS900AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static void s390_init_frame_layout ( void ) { HOST_WIDE_INT frame_size ; int base_used ; int clobbered_regs [ 16 ] ; if ( ! TARGET_CPU_ZARCH ) cfun -> machine -> split_branches_pending_p = true ; do { frame_size = cfun_frame_layout . frame_size ; base_used = cfun -> machine -> split_branches_pending_p || current_function_uses_const_pool || ( ! DISP_IN_RANGE ( - frame_size ) && ! CONST_OK_FOR_K ( - frame_size ) ) ; if ( ! base_used ) cfun -> machine -> base_reg = NULL_RTX ; else if ( current_function_is_leaf && ! regs_ever_live [ 5 ] ) cfun -> machine -> base_reg = gen_rtx_REG ( Pmode , 5 ) ; else cfun -> machine -> base_reg = gen_rtx_REG ( Pmode , BASE_REGNUM ) ; s390_register_info ( clobbered_regs ) ; s390_frame_info ( ) ; } while ( frame_size != cfun_frame_layout . frame_size ) ; } </s>

Generate frame layout . Fills in register and frame data for the current function in cfun- > machine . This routine can be called multiple times ; it will re-do the complete frame layout every time .


<s>
StringRef
getPassName
(
)
const
override
{
return
"AArch64 Indirect Thunks"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { AttributeSet FnAttrs = MF . getFunction ( ) -> getAttributes ( ) ; ForCodeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) || FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>


<s> void PPCSubtarget :: overrideSchedPolicy ( MachineSchedPolicy & Policy , unsigned NumRegionInstrs ) const { Policy . OnlyBottomUp = false ; Policy . ShouldTrackPressure = true ; } </s>

Override generic scheduling policy within a region .


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , int64_t NumBytes , bool Is64Bit , bool IsLP64 , bool UseLEA , const TargetInstrInfo & TII , const TargetRegisterInfo & TRI ) { bool isSub = NumBytes < 0 ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; unsigned Opc ; if ( UseLEA ) Opc = getLEArOpcode ( IsLP64 ) ; else Opc = isSub ? getSUBriOpcode ( IsLP64 , Offset ) : getADDriOpcode ( IsLP64 , Offset ) ; uint64_t Chunk = ( 1LL << 31 ) - 1 ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; if ( ThisVal == ( Is64Bit ? 8 : 4 ) ) { unsigned Reg = isSub ? ( unsigned ) ( Is64Bit ? X86 :: RAX : X86 :: EAX ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { Opc = isSub ? ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) : ( Is64Bit ? X86 :: POP64r : X86 :: POP32r ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ; if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; Offset -= ThisVal ; continue ; } } MachineInstr * MI = NULL ; if ( UseLEA ) { MI = addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) , StackPtr , false , isSub ? - ThisVal : ThisVal ) ; } else { MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( ThisVal ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; } if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


"Altivec is not implemented on AIX yet."

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void MipsRegisterInfo :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = prior ( MBB . end ( ) ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; int FPOffset = MipsFI -> getFPStackOffset ( ) ; int RAOffset = MipsFI -> getRAStackOffset ( ) ; if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDu ) , Mips :: SP ) . addReg ( Mips :: FP ) . addReg ( Mips :: ZERO ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: LW ) ) . addReg ( Mips :: FP ) . addImm ( FPOffset ) . addReg ( Mips :: SP ) ; } if ( MFI -> hasCalls ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: LW ) ) . addReg ( Mips :: RA ) . addImm ( RAOffset ) . addReg ( Mips :: SP ) ; } if ( NumBytes ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDiu ) , Mips :: SP ) . addReg ( Mips :: SP ) . addImm ( NumBytes ) ; } } </s>

Mips Mips Mips Mips Mips Mips Mips Mips::ADDu Mips::SP Mips::FP Mips::ZERO Mips::LW Mips::FP Mips::SP Mips::LW Mips::RA Mips::SP Mips::ADDiu Mips::SP Mips::SP


<s> static void arm_elf_asm_destructor ( rtx symbol , int priority ) { arm_elf_asm_cdtor ( symbol , priority , false ) ; } </s>

Add a function to the list of static destructors .


<s> bool SparcTargetLowering :: useLoadStackGuardNode ( ) const { if ( ! Subtarget -> isTargetLinux ( ) ) return TargetLowering :: useLoadStackGuardNode ( ) ; return true ; } </s>

If this function returns true , SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic : :stackprotector .


<s> static void arc_encode_section_info ( tree decl , rtx rtl , int first ) { default_encode_section_info ( decl , rtl , first ) ; if ( TREE_CODE ( decl ) == FUNCTION_DECL ) { rtx symbol = XEXP ( rtl , 0 ) ; int flags = SYMBOL_REF_FLAGS ( symbol ) ; tree attr = ( TREE_TYPE ( decl ) != error_mark_node ? TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) : NULL_TREE ) ; tree long_call_attr = lookup_attribute ( "long_call" , attr ) ; tree medium_call_attr = lookup_attribute ( "medium_call" , attr ) ; tree short_call_attr = lookup_attribute ( "short_call" , attr ) ; if ( long_call_attr != NULL_TREE ) flags |= SYMBOL_FLAG_LONG_CALL ; else if ( medium_call_attr != NULL_TREE ) flags |= SYMBOL_FLAG_MEDIUM_CALL ; else if ( short_call_attr != NULL_TREE ) flags |= SYMBOL_FLAG_SHORT_CALL ; SYMBOL_REF_FLAGS ( symbol ) = flags ; } } </s>

Implement TARGET_ENCODE_SECTION_INFO hook .


<s> TargetPassConfig * PPCTargetMachine :: createPassConfig ( PassManagerBase & PM ) { TargetPassConfig * PassConfig = new PPCPassConfig ( this , PM ) ; PassConfig -> setEnableTailMerge ( false ) ; return PassConfig ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> bool AArch64TargetLowering :: isExtractSubvectorCheap ( EVT ResVT , EVT SrcVT , unsigned Index ) const { if ( ! isOperationLegalOrCustom ( ISD :: EXTRACT_SUBVECTOR , ResVT ) ) return false ; return ( Index == 0 || Index == ResVT . getVectorNumElements ( ) ) ; } </s>

Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index .


<s> bool isValid ( ) const { return State != Uninitialized ; } </s>

Returns true if this iterator is still pointing at a valid entry .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void RISCVFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterClass * RC = & RISCV :: GPRRegClass ; if ( ! isInt < 11 > ( MFI . estimateStackSize ( MF ) ) ) { int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RegScavFI ) ; } } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> static bool pa_cannot_force_const_mem ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { return tls_referenced_p ( x ) ; } </s>


<s>
void
RISCVInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MBBI
,
const
DebugLoc
&
DL
,
unsigned
DstReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
RISCV
::
GPRRegClass
.
contains
(
DstReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
RISCV
::
ADDI
)
,
DstReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
0
)
;
return
;
}
if
(
RISCV
::
FPR32RegClass
.
contains
(
DstReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
RISCV
::
FSGNJ_S
)
,
DstReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
return
;
}
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
</s>


<s> MCSymbol * WebAssemblyMCInstLower :: GetExternalSymbolSymbol ( const MachineOperand & MO ) const { const char * Name = MO . getSymbolName ( ) ; auto * WasmSym = cast < MCSymbolWasm > ( Printer . GetExternalSymbolSymbol ( Name ) ) ; const WebAssemblySubtarget & Subtarget = Printer . getSubtarget ( ) ; if ( strcmp ( Name , "__stack_pointer" ) == 0 || strcmp ( Name , "__memory_base" ) == 0 || strcmp ( Name , "__table_base" ) == 0 ) { bool Mutable = strcmp ( Name , "__stack_pointer" ) == 0 ; WasmSym -> setType ( wasm :: WASM_SYMBOL_TYPE_GLOBAL ) ; WasmSym -> setGlobalType ( wasm :: WasmGlobalType { uint8_t ( Subtarget . hasAddr64 ( ) ? wasm :: WASM_TYPE_I64 : wasm :: WASM_TYPE_I32 ) , Mutable } ) ; return WasmSym ; } SmallVector < wasm :: ValType , 4 > Returns ; SmallVector < wasm :: ValType , 4 > Params ; if ( strcmp ( Name , "__cpp_exception" ) == 0 ) { WasmSym -> setType ( wasm :: WASM_SYMBOL_TYPE_EVENT ) ; WasmSym -> setEventType ( { wasm :: WASM_EVENT_ATTRIBUTE_EXCEPTION , 0 } ) ; WasmSym -> setWeak ( true ) ; WasmSym -> setExternal ( true ) ; Params . push_back ( Subtarget . hasAddr64 ( ) ? wasm :: ValType :: I64 : wasm :: ValType :: I32 ) ; } else { WasmSym -> setType ( wasm :: WASM_SYMBOL_TYPE_FUNCTION ) ; getLibcallSignature ( Subtarget , Name , Returns , Params ) ; } auto Signature = make_unique < wasm :: WasmSignature > ( std :: move ( Returns ) , std :: move ( Params ) ) ; WasmSym -> setSignature ( Signature . get ( ) ) ; Printer . addSignature ( std :: move ( Signature ) ) ; return WasmSym ; } </s>

Return the MCSymbol for the specified ExternalSymbol .


<s>
void
h8300_init_once
(
void
)
{
static
const
char
*
const
h8_push_ops
[
2
]
=
{
"push"
,
"push.l"
}
;
static
const
char
*
const
h8_pop_ops
[
2
]
=
{
"pop"
,
"pop.l"
}
;
static
const
char
*
const
h8_mov_ops
[
2
]
=
{
"mov.w"
,
"mov.l"
}
;
if
(
TARGET_H8300
)
{
cpu_type
=
(
int
)
CPU_H8300
;
h8_reg_names
=
names_big
;
}
else
{
cpu_type
=
(
int
)
CPU_H8300H
;
h8_reg_names
=
names_extended
;
}
h8_push_op
=
h8_push_ops
[
cpu_type
]
;
h8_pop_op
=
h8_pop_ops
[
cpu_type
]
;
h8_mov_op
=
h8_mov_ops
[
cpu_type
]
;
if
(
!
TARGET_H8300S
&&
TARGET_MAC
)
{
error
(
"-ms2600 is used without -ms"
)
;
target_flags
|=
MASK_H8300S_1
;
}
if
(
TARGET_H8300
&&
TARGET_NORMAL_MODE
)
{
error
(
"-mn is used without -mh or -ms"
)
;
target_flags
^=
MASK_NORMAL_MODE
;
}
if
(
optimize_size
)
{
shift_alg_hi
[
H8_300
]
[
SHIFT_ASHIFT
]
[
5
]
=
SHIFT_LOOP
;
shift_alg_hi
[
H8_300
]
[
SHIFT_ASHIFT
]
[
6
]
=
SHIFT_LOOP
;
shift_alg_hi
[
H8_300
]
[
SHIFT_ASHIFT
]
[
13
]
=
SHIFT_LOOP
;
shift_alg_hi
[
H8_300
]
[
SHIFT_ASHIFT
]
[
14
]
=
SHIFT_LOOP
;
shift_alg_hi
[
H8_300
]
[
SHIFT_LSHIFTRT
]
[
13
]
=
SHIFT_LOOP
;
shift_alg_hi
[
H8_300
]
[
SHIFT_LSHIFTRT
]
[
14
]
=
SHIFT_LOOP
;
shift_alg_hi
[
H8_300
]
[
SHIFT_ASHIFTRT
]
[
13
]
=
SHIFT_LOOP
;
shift_alg_hi
[
H8_300
]
[
SHIFT_ASHIFTRT
]
[
14
]
=
SHIFT_LOOP
;
shift_alg_hi
[
H8_300H
]
[
SHIFT_ASHIFT
]
[
5
]
=
SHIFT_LOOP
;
shift_alg_hi
[
H8_300H
]
[
SHIFT_ASHIFT
]
[
6
]
=
SHIFT_LOOP
;
shift_alg_hi
[
H8_300H
]
[
SHIFT_LSHIFTRT
]
[
5
]
=
SHIFT_LOOP
;
shift_alg_hi
[
H8_300H
]
[
SHIFT_LSHIFTRT
]
[
6
]
=
SHIFT_LOOP
;
shift_alg_hi
[
H8_300H
]
[
SHIFT_ASHIFTRT
]
[
5
]
=
SHIFT_LOOP
;
shift_alg_hi
[
H8_300H
]
[
SHIFT_ASHIFTRT
]
[
6
]
=
SHIFT_LOOP
;
shift_alg_hi
[
H8_300H
]
[
SHIFT_ASHIFTRT
]
[
13
]
=
SHIFT_LOOP
;
shift_alg_hi
[
H8_300H
]
[
SHIFT_ASHIFTRT
]
[
14
]
=
SHIFT_LOOP
;
shift_alg_hi
[
H8_S
]
[
SHIFT_ASHIFTRT
]
[
14
]
=
SHIFT_LOOP
;
}
if
(
!
TARGET_H8300SX
)
{
h8300_move_ratio
=
3
;
}
else
if
(
flag_omit_frame_pointer
)
{
h8300_move_ratio
=
4
;
}
else
if
(
optimize_size
)
{
h8300_move_ratio
=
4
;
}
else
{
h8300_move_ratio
=
6
;
}
}
</s>

Initialize various cpu specific globals at start up .


<s> void mn10300_print_operand_address ( FILE * file , rtx addr ) { switch ( GET_CODE ( addr ) ) { case POST_INC : mn10300_print_operand ( file , XEXP ( addr , 0 ) , 0 ) ; fputc ( '+' , file ) ; break ; case POST_MODIFY : mn10300_print_operand ( file , XEXP ( addr , 0 ) , 0 ) ; fputc ( '+' , file ) ; fputc ( ',' , file ) ; mn10300_print_operand ( file , XEXP ( addr , 1 ) , 0 ) ; break ; case REG : mn10300_print_operand ( file , addr , 0 ) ; break ; case PLUS : { rtx base = XEXP ( addr , 0 ) ; rtx index = XEXP ( addr , 1 ) ; if ( REG_P ( index ) && ! REG_OK_FOR_INDEX_P ( index ) ) { rtx x = base ; base = index ; index = x ; gcc_assert ( REG_P ( index ) && REG_OK_FOR_INDEX_P ( index ) ) ; } gcc_assert ( REG_OK_FOR_BASE_P ( base ) ) ; mn10300_print_operand ( file , index , 0 ) ; fputc ( ',' , file ) ; mn10300_print_operand ( file , base , 0 ) ; break ; } case SYMBOL_REF : output_addr_const ( file , addr ) ; break ; default : output_addr_const ( file , addr ) ; break ; } } </s>

Output assembly language output for the address ADDR to FILE .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addRequired < PostDominatorTreeWrapperPass > ( ) ; AU . addPreserved < PostDominatorTreeWrapperPass > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s>
bool
SIFixVGPRCopies
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
const
SISubtarget
&
ST
=
MF
.
getSubtarget
<
SISubtarget
>
(
)
;
const
SIRegisterInfo
*
TRI
=
ST
.
getRegisterInfo
(
)
;
const
SIInstrInfo
*
TII
=
ST
.
getInstrInfo
(
)
;
bool
Changed
=
false
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
for
(
MachineInstr
&
MI
:
MBB
)
{
switch
(
MI
.
getOpcode
(
)
)
{
case
AMDGPU
::
COPY
:
if
(
TII
->
isVGPRCopy
(
MI
)
&&
!
MI
.
readsRegister
(
AMDGPU
::
EXEC
,
TRI
)
)
{
MI
.
addOperand
(
MF
,
MachineOperand
::
CreateReg
(
AMDGPU
::
EXEC
,
false
,
true
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Add exec use to "
<<
MI
)
;
Changed
=
true
;
}
break
;
default
:
break
;
}
}
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

AMDGPU
SI
SI
SI
SI
SI
AMDGPU::COPY
AMDGPU::EXEC
AMDGPU::EXEC
"Add exec use to "


<s>
enum
calling_abi
ix86_function_type_abi
(
const_tree
fntype
)
{
if
(
fntype
!=
NULL_TREE
&&
TYPE_ATTRIBUTES
(
fntype
)
!=
NULL_TREE
)
{
enum
calling_abi
abi
=
ix86_abi
;
if
(
abi
==
SYSV_ABI
)
{
if
(
lookup_attribute
(
"ms_abi"
,
TYPE_ATTRIBUTES
(
fntype
)
)
)
{
if
(
TARGET_X32
)
{
static
bool
warned
=
false
;
if
(
!
warned
)
{
error
(
"X32 does not support ms_abi attribute"
)
;
warned
=
true
;
}
}
abi
=
MS_ABI
;
}
}
else
if
(
lookup_attribute
(
"sysv_abi"
,
TYPE_ATTRIBUTES
(
fntype
)
)
)
abi
=
SYSV_ABI
;
return
abi
;
}
return
ix86_abi
;
}
</s>

Returns value SYSV_ABI , MS_ABI dependent on fntype , specifying the call abi used .


<s> virtual bool addPreISel ( ) { if ( PatmosSinglePathInfo :: isEnabled ( ) ) { addPass ( createUnifyFunctionExitNodesPass ( ) ) ; addPass ( createLowerSwitchPass ( ) ) ; addPass ( createPatmosSPClonePass ( ) ) ; return true ; } return false ; } </s>


<s>
void
HexagonDCE
::
removeOperand
(
NodeAddr
<
InstrNode
*
>
IA
,
unsigned
OpNum
)
{
MachineInstr
*
MI
=
NodeAddr
<
StmtNode
*
>
(
IA
)
.
Addr
->
getCode
(
)
;
auto
getOpNum
=
[
MI
]
(
MachineOperand
&
Op
)
->
unsigned
{
for
(
unsigned
i
=
0
,
n
=
MI
->
getNumOperands
(
)
;
i
!=
n
;
++
i
)
if
(
&
MI
->
getOperand
(
i
)
==
&
Op
)
return
i
;
llvm_unreachable
(
"Invalid operand"
)
;
}
;
DenseMap
<
NodeId
,
unsigned
>
OpMap
;
NodeList
Refs
=
IA
.
Addr
->
members
(
getDFG
(
)
)
;
for
(
NodeAddr
<
RefNode
*
>
RA
:
Refs
)
OpMap
.
insert
(
std
::
make_pair
(
RA
.
Id
,
getOpNum
(
RA
.
Addr
->
getOp
(
)
)
)
)
;
MI
->
RemoveOperand
(
OpNum
)
;
for
(
NodeAddr
<
RefNode
*
>
RA
:
Refs
)
{
unsigned
N
=
OpMap
[
RA
.
Id
]
;
if
(
N
<
OpNum
)
RA
.
Addr
->
setRegRef
(
&
MI
->
getOperand
(
N
)
)
;
else
if
(
N
>
OpNum
)
RA
.
Addr
->
setRegRef
(
&
MI
->
getOperand
(
N
1
)
)
;
}
}
</s>

Erase an operand from an instruction , leaving it with one fewer operand than it started with .


<s> EVT TeakTargetLowering :: getSetCCResultType ( const DataLayout & , LLVMContext & , EVT VT ) const { return MVT :: i40 ; } </s>

Return the value type to use for ISD : :SETCC .


<s>
bool
AArch64TargetLowering
::
isFPImmLegal
(
const
APFloat
&
Imm
,
EVT
VT
)
const
{
if
(
Imm
.
isPosZero
(
)
&&
(
VT
==
MVT
::
f64
||
VT
==
MVT
::
f32
||
(
VT
==
MVT
::
f16
&&
Subtarget
->
hasFullFP16
(
)
)
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Legal "
<<
VT
.
getEVTString
(
)
<<
" imm value: 0\n"
)
;
return
true
;
}
bool
IsLegal
=
false
;
SmallString
<
128
>
ImmStrVal
;
Imm
.
toString
(
ImmStrVal
)
;
if
(
VT
==
MVT
::
f64
)
IsLegal
=
AArch64_AM
::
getFP64Imm
(
Imm
)
!=
1
;
else
if
(
VT
==
MVT
::
f32
)
IsLegal
=
AArch64_AM
::
getFP32Imm
(
Imm
)
!=
1
;
else
if
(
VT
==
MVT
::
f16
&&
Subtarget
->
hasFullFP16
(
)
)
IsLegal
=
AArch64_AM
::
getFP16Imm
(
Imm
)
!=
1
;
if
(
IsLegal
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Legal "
<<
VT
.
getEVTString
(
)
<<
" imm value: "
<<
ImmStrVal
<<
"\n"
)
;
return
true
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Illegal "
<<
VT
.
getEVTString
(
)
<<
" imm value: "
<<
ImmStrVal
<<
"\n"
)
;
return
false
;
}
</s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> bool ARMBaseRegisterInfo :: getRegAllocationHints ( Register VirtReg , ArrayRef < MCPhysReg > Order , SmallVectorImpl < MCPhysReg > & Hints , const MachineFunction & MF , const VirtRegMap * VRM , const LiveRegMatrix * Matrix ) const { const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; std :: pair < Register , Register > Hint = MRI . getRegAllocationHint ( VirtReg ) ; unsigned Odd ; switch ( Hint . first ) { case ARMRI :: RegPairEven : Odd = 0 ; break ; case ARMRI :: RegPairOdd : Odd = 1 ; break ; default : TargetRegisterInfo :: getRegAllocationHints ( VirtReg , Order , Hints , MF , VRM ) ; return false ; } Register Paired = Hint . second ; if ( ! Paired ) return false ; Register PairedPhys ; if ( Paired . isPhysical ( ) ) { PairedPhys = Paired ; } else if ( VRM && VRM -> hasPhys ( Paired ) ) { PairedPhys = getPairedGPR ( VRM -> getPhys ( Paired ) , Odd , this ) ; } if ( PairedPhys && is_contained ( Order , PairedPhys ) ) Hints . push_back ( PairedPhys ) ; for ( MCPhysReg Reg : Order ) { if ( Reg == PairedPhys || ( getEncodingValue ( Reg ) & 1 ) != Odd ) continue ; MCPhysReg Paired = getPairedGPR ( Reg , ! Odd , this ) ; if ( ! Paired || MRI . isReserved ( Paired ) ) continue ; Hints . push_back ( Reg ) ; } return false ; } </s>

Get a list of 'hint ' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg .


<s> void PPCPassConfig :: addPreRegAlloc ( ) { initializePPCVSXFMAMutatePass ( * PassRegistry :: getPassRegistry ( ) ) ; insertPass ( VSXFMAMutateEarly ? & RegisterCoalescerID : & MachineSchedulerID , & PPCVSXFMAMutateID ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> void function_expander :: add_integer_operand ( HOST_WIDE_INT x ) { m_ops . safe_grow ( m_ops . length ( ) + 1 ) ; create_integer_operand ( & m_ops . last ( ) , x ) ; } </s>


<s> unsigned AlphaRegisterInfo :: getFrameRegister ( MachineFunction & MF ) const { return hasFP ( MF ) ? Alpha :: R15 : Alpha :: R30 ; } </s>


<s> int pru_get_ctable_base_offset ( unsigned HOST_WIDE_INT caddr ) { int i ; i = pru_get_ctable_base_index ( caddr ) ; gcc_assert ( i >= 0 ) ; return caddr - pru_ctable [ i ] . base ; } </s>

Return the offset from some CTABLE base for this address .


<s> static rtx_insn * rs6000_frame_related ( rtx_insn * insn , rtx reg , HOST_WIDE_INT val , rtx reg2 , rtx repl2 ) { rtx repl ; if ( REGNO ( reg ) == STACK_POINTER_REGNUM ) { gcc_checking_assert ( val == 0 ) ; repl = NULL_RTX ; } else repl = gen_rtx_PLUS ( Pmode , gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) , GEN_INT ( val ) ) ; rtx pat = PATTERN ( insn ) ; if ( ! repl && ! reg2 ) { if ( GET_CODE ( pat ) == PARALLEL ) for ( int i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) if ( GET_CODE ( XVECEXP ( pat , 0 , i ) ) == SET ) { rtx set = XVECEXP ( pat , 0 , i ) ; if ( ! REG_P ( SET_SRC ( set ) ) || ! fixed_reg_p ( REGNO ( SET_SRC ( set ) ) ) ) RTX_FRAME_RELATED_P ( set ) = 1 ; } RTX_FRAME_RELATED_P ( insn ) = 1 ; return insn ; } set_used_flags ( pat ) ; if ( GET_CODE ( pat ) == SET ) { if ( repl ) pat = simplify_replace_rtx ( pat , reg , repl ) ; if ( reg2 ) pat = simplify_replace_rtx ( pat , reg2 , repl2 ) ; } else if ( GET_CODE ( pat ) == PARALLEL ) { pat = shallow_copy_rtx ( pat ) ; XVEC ( pat , 0 ) = shallow_copy_rtvec ( XVEC ( pat , 0 ) ) ; for ( int i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) if ( GET_CODE ( XVECEXP ( pat , 0 , i ) ) == SET ) { rtx set = XVECEXP ( pat , 0 , i ) ; if ( repl ) set = simplify_replace_rtx ( set , reg , repl ) ; if ( reg2 ) set = simplify_replace_rtx ( set , reg2 , repl2 ) ; XVECEXP ( pat , 0 , i ) = set ; if ( ! REG_P ( SET_SRC ( set ) ) || ! fixed_reg_p ( REGNO ( SET_SRC ( set ) ) ) ) RTX_FRAME_RELATED_P ( set ) = 1 ; } } else gcc_unreachable ( ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , copy_rtx_if_shared ( pat ) ) ; return insn ; } </s>

Add to 'insn ' a note which is PATTERN ( INSN ) but with REG replaced with ( plus : P ( reg 1 ) VAL ) , and with REG2 replaced with RREG if REG2 is not NULL . It would be nice if dwarf2out_frame_debug_expr could deduce these equivalences by itself so it was n't necessary to hold its hand so much . Do n't be tempted to always supply d2_f_d_e with the actual cfa register , ie . r31 when we are using a hard frame pointer . That fails when saving regs off r1 , and sched moves the r31 setup past the reg saves .


<s> BitVector TPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , TPC :: LFSR ) ; markSuperRegs ( Reserved , TPC :: LFSR_NO_CHANGE ) ; markSuperRegs ( Reserved , TPC :: V_LANE_ID_32 ) ; markSuperRegs ( Reserved , TPC :: V_LANE_ID_16 ) ; markSuperRegs ( Reserved , TPC :: V_LANE_ID_8 ) ; Reserved . set ( TPC :: SP0 ) ; Reserved . set ( TPC :: VP0 ) ; if ( MF . getSubtarget < TPCSubtarget > ( ) . hasGoyaISA ( ) ) { Reserved . set ( TPC :: S31 ) ; } Reserved . set ( TPC :: S32 ) ; Reserved . set ( TPC :: S33 ) ; Reserved . set ( TPC :: S34 ) ; Reserved . set ( TPC :: S35 ) ; markSuperRegs ( Reserved , TPC :: S_LFSR ) ; markSuperRegs ( Reserved , TPC :: S_LFSR_NO_CHANGE ) ; Reserved . set ( TPC :: I0 ) ; Reserved . set ( TPC :: I1 ) ; const Module * MM = MF . getMMI ( ) . getModule ( ) ; Metadata * PrintfModule = MM -> getModuleFlag ( "tpc-printf" ) ; if ( PrintfModule ) { Reserved . set ( TPC :: I2 ) ; MachineInstrBuilder MIB ; const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; auto MBB = MF . getBlockNumbered ( 0 ) ; auto firstInst = MF . getBlockNumbered ( 0 ) -> instr_begin ( ) ; auto FI = & * firstInst ; MIB = BuildMI ( * MBB , firstInst , FI -> getDebugLoc ( ) , TII -> get ( TPC :: SET_INDX_spu_ip ) , TPC :: I2 ) . addReg ( TPC :: I2 , RegState :: Undef ) . addImm ( 0 ) . addImm ( 31 ) . addImm ( 0 ) . addReg ( TPC :: SP0 ) . addImm ( 0 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void ix86_emit_i387_tanh ( rtx op0 , rtx op1 ) { rtx e1 = gen_reg_rtx ( XFmode ) ; rtx e2 = gen_reg_rtx ( XFmode ) ; rtx scratch = gen_reg_rtx ( HImode ) ; rtx flags = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; rtx cst2 , tmp ; rtx_code_label * jump_label = gen_label_rtx ( ) ; rtx_insn * insn ; emit_insn ( gen_fxamxf2_i387 ( scratch , op1 ) ) ; emit_insn ( gen_addxf3 ( e2 , op1 , op1 ) ) ; emit_insn ( gen_absxf2 ( e2 , e2 ) ) ; emit_insn ( gen_negxf2 ( e2 , e2 ) ) ; emit_insn ( gen_expm1xf2 ( e1 , e2 ) ) ; cst2 = force_reg ( XFmode , CONST2_RTX ( XFmode ) ) ; emit_insn ( gen_addxf3 ( e2 , e1 , cst2 ) ) ; emit_insn ( gen_divxf3 ( e2 , e1 , e2 ) ) ; emit_insn ( gen_testqi_ext_1_ccno ( scratch , GEN_INT ( 0x02 ) ) ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_NE ( VOIDmode , flags , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , jump_label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; predict_jump ( REG_BR_PROB_BASE * 50 / 100 ) ; JUMP_LABEL ( insn ) = jump_label ; emit_insn ( gen_negxf2 ( e2 , e2 ) ) ; emit_label ( jump_label ) ; LABEL_NUSES ( jump_label ) = 1 ; emit_move_insn ( op0 , e2 ) ; } </s>

Output code to perform an tanh XFmode calculation .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> bool BPFAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { if ( ( Count % 8 ) != 0 ) return false ; for ( uint64_t i = 0 ; i < Count ; i += 8 ) support :: endian :: write < uint64_t > ( OS , 0x15000000 , Endian ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> bool AArch64PromoteConstant :: runOnFunction ( Function & F ) { bool LocalChange = false ; SmallSet < Constant * , 8 > AlreadyChecked ; for ( auto & MBB : F ) { for ( auto & MI : MBB ) { for ( unsigned OpIdx = 0 , EndOpIdx = MI . getNumOperands ( ) ; OpIdx != EndOpIdx ; ++ OpIdx ) { Constant * Cst = dyn_cast < Constant > ( MI . getOperand ( OpIdx ) ) ; if ( Cst && ! isa < GlobalValue > ( Cst ) && ! isa < ConstantExpr > ( Cst ) && AlreadyChecked . insert ( Cst ) . second ) LocalChange |= promoteConstant ( Cst ) ; } } } return LocalChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


"\tj\t%s ! jump to first level handler\n"

"\tmovi\t$r0, %d ! preparing software vid\n"


<s> void mn10300_print_reg_list ( FILE * file , int mask ) { int need_comma ; int i ; need_comma = 0 ; fputc ( '[' , file ) ; for ( i = 0 ; i < FIRST_EXTENDED_REGNUM ; i ++ ) if ( ( mask & ( 1 << i ) ) != 0 ) { if ( need_comma ) fputc ( ',' , file ) ; fputs ( reg_names [ i ] , file ) ; need_comma = 1 ; } if ( ( mask & 0x3c000 ) != 0 ) { gcc_assert ( ( mask & 0x3c000 ) == 0x3c000 ) ; if ( need_comma ) fputc ( ',' , file ) ; fputs ( "exreg1" , file ) ; need_comma = 1 ; } fputc ( ']' , file ) ; } </s>

Print a set of registers in the format required by `` movm '' and `` ret '' . Register K is saved if bit K of MASK is set . The data and address registers can be stored individually , but the extended registers can not . We assume that the mask alread takes that into account . For instance , bits 14 to 17 must have the same value .


<s> bool GCNTTIImpl :: isInlineAsmSourceOfDivergence ( const CallInst * CI , ArrayRef < unsigned > Indices ) const { if ( Indices . size ( ) > 1 ) return true ; const DataLayout & DL = CI -> getModule ( ) -> getDataLayout ( ) ; const SIRegisterInfo * TRI = ST -> getRegisterInfo ( ) ; TargetLowering :: AsmOperandInfoVector TargetConstraints = TLI -> ParseConstraints ( DL , ST -> getRegisterInfo ( ) , * CI ) ; const int TargetOutputIdx = Indices . empty ( ) ? - 1 : Indices [ 0 ] ; int OutputIdx = 0 ; for ( auto & TC : TargetConstraints ) { if ( TC . Type != InlineAsm :: isOutput ) continue ; if ( TargetOutputIdx != - 1 && TargetOutputIdx != OutputIdx ++ ) continue ; TLI -> ComputeConstraintToUse ( TC , SDValue ( ) ) ; Register AssignedReg ; const TargetRegisterClass * RC ; std :: tie ( AssignedReg , RC ) = TLI -> getRegForInlineAsmConstraint ( TRI , TC . ConstraintCode , TC . ConstraintVT ) ; if ( AssignedReg ) { RC = TRI -> getPhysRegClass ( AssignedReg ) ; } if ( ! RC || ! TRI -> isSGPRClass ( RC ) ) return true ; } return false ; } </s>

Analyze if the results of inline asm are divergent .


"MachineModuleInfo should always be available"


<s> unsigned PatmosInstrInfo :: getIssueWidth ( const MachineInstr * MI ) const { if ( MI -> isInlineAsm ( ) ) return PST . getSchedModel ( ) . IssueWidth ; return PST . getIssueWidth ( MI -> getDesc ( ) . SchedClass ) ; } </s>

Maximum number of micro-ops that may be scheduled per cycle .


<s> bool sh_lra_p ( void ) { return sh_lra_flag ; } </s>

Return true if we use LRA instead of reload pass .


"Call frame pseudos should only be used for dynamic stack adjustment"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static struct machine_function * iq2000_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function > ( ) ; } </s>

Allocate a chunk of memory for per-function machine-dependent data .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addRequired < AAResultsWrapperPass > ( ) ; AU . addRequired < TargetPassConfig > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static unsigned int bpf_hard_regno_nregs ( unsigned int regno ATTRIBUTE_UNUSED , enum machine_mode mode ) { return CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ; } </s>

Return the number of consecutive hard registers , starting at register number REGNO , required to hold a value of mode MODE .


"Cannot handle this call frame pseudo instruction"


<s> bool MipsTargetLowering :: shouldSignExtendTypeInLibCall ( EVT Type , bool IsSigned ) const { if ( Subtarget . hasMips3 ( ) && Subtarget . abiUsesSoftFloat ( ) ) { if ( Type == MVT :: i32 ) return true ; } return IsSigned ; } </s>

Returns true if arguments should be sign-extended in lib calls .


<s> unsigned MBlazeInstrInfo :: getGlobalBaseReg ( MachineFunction * MF ) const { MBlazeFunctionInfo * MBlazeFI = MF -> getInfo < MBlazeFunctionInfo > ( ) ; unsigned GlobalBaseReg = MBlazeFI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg != 0 ) return GlobalBaseReg ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; const TargetInstrInfo * TII = MF -> getTarget ( ) . getInstrInfo ( ) ; GlobalBaseReg = RegInfo . createVirtualRegister ( MBlaze :: GPRRegisterClass ) ; BuildMI ( FirstMBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , GlobalBaseReg ) . addReg ( MBlaze :: R20 ) ; RegInfo . addLiveIn ( MBlaze :: R20 ) ; MBlazeFI -> setGlobalBaseReg ( GlobalBaseReg ) ; return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

MBlaze MBlaze MBlaze MBlaze MBlaze MBlaze 0 MBlaze::GPRRegisterClass MBlaze::R20 MBlaze::R20 MBlaze