<s> bool MipsAsmParser :: processInstruction ( MCInst & Inst , SMLoc IDLoc , SmallVectorImpl < MCInst > & Instructions ) { const MCInstrDesc & MCID = getInstDesc ( Inst . getOpcode ( ) ) ; Inst . setLoc ( IDLoc ) ; if ( MCID . hasDelaySlot ( ) && Options . isReorder ( ) ) { Instructions . push_back ( Inst ) ; MCInst NopInst ; NopInst . setOpcode ( Mips :: SLL ) ; NopInst . addOperand ( MCOperand :: CreateReg ( Mips :: ZERO ) ) ; NopInst . addOperand ( MCOperand :: CreateReg ( Mips :: ZERO ) ) ; NopInst . addOperand ( MCOperand :: CreateImm ( 0 ) ) ; Instructions . push_back ( NopInst ) ; return false ; } if ( MCID . mayLoad ( ) || MCID . mayStore ( ) ) { for ( unsigned i = 0 ; i < MCID . getNumOperands ( ) ; i ++ ) { const MCOperandInfo & OpInfo = MCID . OpInfo [ i ] ; if ( ( OpInfo . OperandType == MCOI :: OPERAND_MEMORY ) || ( OpInfo . OperandType == MCOI :: OPERAND_UNKNOWN ) ) { MCOperand & Op = Inst . getOperand ( i ) ; if ( Op . isImm ( ) ) { int MemOffset = Op . getImm ( ) ; if ( MemOffset < - 32768 || MemOffset > 32767 ) { expandMemInst ( Inst , IDLoc , Instructions , MCID . mayLoad ( ) , true ) ; return false ; } } else if ( Op . isExpr ( ) ) { const MCExpr * Expr = Op . getExpr ( ) ; if ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) { const MCSymbolRefExpr * SR = static_cast < const MCSymbolRefExpr * > ( Expr ) ; if ( SR -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { expandMemInst ( Inst , IDLoc , Instructions , MCID . mayLoad ( ) , false ) ; return false ; } } else if ( ! isEvaluated ( Expr ) ) { expandMemInst ( Inst , IDLoc , Instructions , MCID . mayLoad ( ) , false ) ; return false ; } } } } } if ( needsExpansion ( Inst ) ) expandInstruction ( Inst , IDLoc , Instructions ) ; else Instructions . push_back ( Inst ) ; return false ; } </s>

Process a single instruction and collect debug info anchors .


<s> void fr30_expand_epilogue ( void ) { int regno ; gcc_assert ( current_frame_info . initialised ) ; if ( current_frame_info . frame_size > 0 ) { if ( current_frame_info . save_fp && frame_pointer_needed ) { emit_insn ( gen_leave_func ( ) ) ; current_frame_info . save_fp = 0 ; } else if ( current_frame_info . frame_size <= 508 ) emit_insn ( gen_add_to_stack ( GEN_INT ( current_frame_info . frame_size ) ) ) ; else { rtx tmp = gen_rtx_REG ( Pmode , PROLOGUE_TMP_REGNUM ) ; emit_insn ( gen_movsi ( tmp , GEN_INT ( current_frame_info . frame_size ) ) ) ; emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , tmp ) ) ; } } if ( current_frame_info . save_fp ) emit_insn ( gen_movsi_pop ( frame_pointer_rtx ) ) ; if ( current_frame_info . save_rp ) emit_insn ( gen_movsi_pop ( gen_rtx_REG ( Pmode , RETURN_POINTER_REGNUM ) ) ) ; for ( regno = 0 ; regno < STACK_POINTER_REGNUM ; regno ++ ) if ( current_frame_info . gmask & ( 1 << regno ) ) emit_insn ( gen_movsi_pop ( gen_rtx_REG ( Pmode , regno ) ) ) ; if ( current_frame_info . pretend_size ) emit_insn ( gen_add_to_stack ( GEN_INT ( current_frame_info . pretend_size ) ) ) ; current_frame_info = zero_frame_info ; emit_jump_insn ( gen_return_from_func ( ) ) ; } </s>

Called after register allocation to add any instructions needed for the epilogue . Using an epilogue insn is favored compared to putting all of the instructions in output_function_epilogue ( ) , since it allows the scheduler to intermix instructions with the restores of the caller saved registers . In some cases , it might be necessary to emit a barrier instruction as the first insn to prevent such scheduling .


<s> static parallel * nvptx_discover_pars ( bb_insn_map_t * map ) { basic_block block ; block = EXIT_BLOCK_PTR_FOR_FN ( cfun ) ; block -> flags |= BB_VISITED ; block = ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ; block -> flags &= ~ BB_VISITED ; parallel * par = nvptx_find_par ( map , 0 , block ) ; if ( dump_file ) { fprintf ( dump_file , "\nLoops\n" ) ; nvptx_dump_pars ( par , 0 ) ; fprintf ( dump_file , "\n" ) ; } return par ; } </s>

See also 'gcc/omp-oacc-neuter-broadcast.cc : omp_sese_discover_pars ' .


<s> static bool dep_between_memop_and_curr ( rtx memop ) { rtx load_reg ; int opno ; gcc_assert ( GET_CODE ( memop ) == SET ) ; if ( ! REG_P ( SET_DEST ( memop ) ) ) return false ; load_reg = SET_DEST ( memop ) ; for ( opno = 1 ; opno < recog_data . n_operands ; opno ++ ) { rtx operand = recog_data . operand [ opno ] ; if ( REG_P ( operand ) && reg_overlap_mentioned_p ( load_reg , operand ) ) return true ; } return false ; } </s>

Check if there is a register dependency between a load and the insn for which we hold recog_data .


<s> int hard_regno_mode_ok ( int regno , enum machine_mode mode ) { enum reg_class class = REGNO_REG_CLASS ( regno ) ; if ( mode == CCmode ) return 0 ; if ( mode == V2HImode ) return D_REGNO_P ( regno ) ; if ( class == CCREGS ) return mode == BImode ; if ( mode == PDImode ) return regno == REG_A0 || regno == REG_A1 ; if ( mode == SImode && TEST_HARD_REG_BIT ( reg_class_contents [ PROLOGUE_REGS ] , regno ) ) return 1 ; return TEST_HARD_REG_BIT ( reg_class_contents [ MOST_REGS ] , regno ) ; } </s>

Value is 1 if hard register REGNO can hold a value of machine-mode MODE .


"No MachineFunctionInfo for this function!"

runOnMachineFunction - Emit the function body .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Remove sign extends"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
void
ARMConstantIslands
::
verify
(
)
{
assert
(
std
::
is_sorted
(
MF
->
begin
(
)
,
MF
->
end
(
)
,
[
this
]
(
const
MachineBasicBlock
&
LHS
,
const
MachineBasicBlock
&
RHS
)
{
return
BBInfo
[
LHS
.
getNumber
(
)
]
.
postOffset
(
)
<
BBInfo
[
RHS
.
getNumber
(
)
]
.
postOffset
(
)
;
}
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Verifying "
<<
CPUsers
.
size
(
)
<<
" CP users.\n"
)
;
for
(
unsigned
i
=
0
,
e
=
CPUsers
.
size
(
)
;
i
!=
e
;
++
i
)
{
CPUser
&
U
=
CPUsers
[
i
]
;
unsigned
UserOffset
=
getUserOffset
(
U
)
;
if
(
isCPEntryInRange
(
U
.
MI
,
UserOffset
,
U
.
CPEMI
,
U
.
getMaxDisp
(
)
+
2
,
U
.
NegOk
,
true
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"OK\n"
)
;
continue
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Out of range.\n"
)
;
dumpBBs
(
)
;
LLVM_DEBUG
(
MF
->
dump
(
)
)
;
llvm_unreachable
(
"Constant pool entry out of range!"
)
;
}
}
</s>

ARM
ARM
"Verifying "
" CP users.\n"
0
2
"OK\n"
"Out of range.\n"
"Constant pool entry out of range!"


<s> static bool reg_used_in_mem_p ( int regno , rtx x ) { enum rtx_code code = GET_CODE ( x ) ; int i , j ; const char * fmt ; if ( code == MEM ) { if ( refers_to_regno_p ( regno , regno + 1 , XEXP ( x , 0 ) , 0 ) ) return true ; } else if ( code == SET && GET_CODE ( SET_DEST ( x ) ) == PC ) { if ( refers_to_regno_p ( regno , regno + 1 , SET_SRC ( x ) , 0 ) ) return true ; } fmt = GET_RTX_FORMAT ( code ) ; for ( i = GET_RTX_LENGTH ( code ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'e' && reg_used_in_mem_p ( regno , XEXP ( x , i ) ) ) return true ; else if ( fmt [ i ] == 'E' ) for ( j = 0 ; j < XVECLEN ( x , i ) ; j ++ ) if ( reg_used_in_mem_p ( regno , XVECEXP ( x , i , j ) ) ) return true ; } return false ; } </s>

Returns true if register REGNO is used for forming a memory address in expression X .


"  Found lowered global address with one use: "


<s> bool ARCExpandPseudos :: runOnMachineFunction ( MachineFunction & MF ) { const ARCSubtarget * STI = & MF . getSubtarget < ARCSubtarget > ( ) ; TII = STI -> getInstrInfo ( ) ; bool ExpandedStore = false ; for ( auto & MBB : MF ) { MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; while ( MBBI != E ) { MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; switch ( MBBI -> getOpcode ( ) ) { case ARC :: ST_FAR : case ARC :: STH_FAR : case ARC :: STB_FAR : ExpandStore ( MF , MBBI ) ; ExpandedStore = true ; break ; default : break ; } MBBI = NMBBI ; } } return ExpandedStore ; } </s>


<s> SDNode * NVPTXDAGToDAGISel :: Select ( SDNode * N ) { if ( N -> isMachineOpcode ( ) ) { N -> setNodeId ( - 1 ) ; return NULL ; } SDNode * ResNode = NULL ; switch ( N -> getOpcode ( ) ) { case ISD :: LOAD : ResNode = SelectLoad ( N ) ; break ; case ISD :: STORE : ResNode = SelectStore ( N ) ; break ; case NVPTXISD :: LoadV2 : case NVPTXISD :: LoadV4 : ResNode = SelectLoadVector ( N ) ; break ; case NVPTXISD :: LDGV2 : case NVPTXISD :: LDGV4 : case NVPTXISD :: LDUV2 : case NVPTXISD :: LDUV4 : ResNode = SelectLDGLDUVector ( N ) ; break ; case NVPTXISD :: StoreV2 : case NVPTXISD :: StoreV4 : ResNode = SelectStoreVector ( N ) ; break ; case NVPTXISD :: LoadParam : case NVPTXISD :: LoadParamV2 : case NVPTXISD :: LoadParamV4 : ResNode = SelectLoadParam ( N ) ; break ; case NVPTXISD :: StoreRetval : case NVPTXISD :: StoreRetvalV2 : case NVPTXISD :: StoreRetvalV4 : ResNode = SelectStoreRetval ( N ) ; break ; case NVPTXISD :: StoreParam : case NVPTXISD :: StoreParamV2 : case NVPTXISD :: StoreParamV4 : case NVPTXISD :: StoreParamS32 : case NVPTXISD :: StoreParamU32 : ResNode = SelectStoreParam ( N ) ; break ; default : break ; } if ( ResNode ) return ResNode ; return SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> static bool arc_can_follow_jump ( const rtx_insn * follower , const rtx_insn * followee ) { union { const rtx_insn * c ; rtx_insn * r ; } u ; u . c = follower ; if ( CROSSING_JUMP_P ( followee ) ) switch ( get_attr_type ( u . r ) ) { case TYPE_BRCC : case TYPE_BRCC_NO_DELAY_SLOT : return false ; default : return true ; } return true ; } </s>

Without this , gcc.dg/tree-prof/bb-reorg.c fails to assemble when compiling with -O2 -freorder-blocks-and-partition -fprofile-use -D_PROFILE_USE ; delay branch scheduling then follows a crossing jump to redirect two breqs .


<s> static bool predicate_insn ( rtx_insn * insn , rtx cond , bool doit ) { int icode ; if ( cond == NULL_RTX ) { gcc_assert ( ! doit ) ; return false ; } if ( get_attr_predicable ( insn ) == PREDICABLE_YES && GET_CODE ( PATTERN ( insn ) ) != COND_EXEC ) { if ( doit ) { cond = copy_rtx ( cond ) ; rtx newpat = gen_rtx_COND_EXEC ( VOIDmode , cond , PATTERN ( insn ) ) ; PATTERN ( insn ) = newpat ; INSN_CODE ( insn ) = - 1 ; } return true ; } if ( GET_CODE ( PATTERN ( insn ) ) == COND_EXEC && rtx_equal_p ( COND_EXEC_TEST ( PATTERN ( insn ) ) , cond ) ) return true ; icode = INSN_CODE ( insn ) ; if ( icode == CODE_FOR_real_jump || icode == CODE_FOR_jump || icode == CODE_FOR_indirect_jump ) { rtx pat = PATTERN ( insn ) ; rtx dest = ( icode == CODE_FOR_real_jump ? XVECEXP ( pat , 0 , 0 ) : icode == CODE_FOR_jump ? XEXP ( SET_SRC ( pat ) , 0 ) : SET_SRC ( pat ) ) ; if ( doit ) { rtx newpat ; if ( REG_P ( dest ) ) newpat = gen_rtx_COND_EXEC ( VOIDmode , cond , PATTERN ( insn ) ) ; else newpat = gen_br_true ( cond , XEXP ( cond , 0 ) , dest ) ; PATTERN ( insn ) = newpat ; INSN_CODE ( insn ) = - 1 ; } return true ; } if ( INSN_CODE ( insn ) == CODE_FOR_br_true ) { rtx br_cond = XEXP ( SET_SRC ( PATTERN ( insn ) ) , 0 ) ; return rtx_equal_p ( br_cond , cond ) ; } if ( INSN_CODE ( insn ) == CODE_FOR_br_false ) { rtx br_cond = XEXP ( SET_SRC ( PATTERN ( insn ) ) , 0 ) ; return conditions_opposite_p ( br_cond , cond ) ; } return false ; } </s>

Return true if we can add a predicate COND to INSN , or if INSN already has that predicate . If DOIT is true , also perform the modification .


<s>
void
VEInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
MCRegister
DestReg
,
MCRegister
SrcReg
,
bool
KillSrc
)
const
{
if
(
IsAliasOfSX
(
SrcReg
)
&&
IsAliasOfSX
(
DestReg
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
VE
::
ORri
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
0
)
;
}
else
{
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
dbgs
(
)
<<
"Impossible reg-to-reg copy from "
<<
printReg
(
SrcReg
,
TRI
)
<<
" to "
<<
printReg
(
DestReg
,
TRI
)
<<
"\n"
;
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
}
</s>

VE
VE
VE::ORri
0
"Impossible reg-to-reg copy from "
" to "
"\n"
"Impossible reg-to-reg copy"


"#if defined(_ARCH_PPC64) && defined (_ARCH_PWR9)\n"

Write everything to the include file ( rs6000-vecdefines.h ) . Return 1 if successful , 0 otherwise .


<s> int xstormy16_extra_constraint_p ( rtx x , int c ) { switch ( c ) { case 'Q' : return ( GET_CODE ( x ) == MEM && GET_CODE ( XEXP ( x , 0 ) ) == POST_INC && XEXP ( XEXP ( x , 0 ) , 0 ) == stack_pointer_rtx ) ; case 'R' : return ( GET_CODE ( x ) == MEM && GET_CODE ( XEXP ( x , 0 ) ) == PRE_DEC && XEXP ( XEXP ( x , 0 ) , 0 ) == stack_pointer_rtx ) ; case 'S' : return ( GET_CODE ( x ) == MEM && GET_CODE ( XEXP ( x , 0 ) ) == CONST_INT && xstormy16_legitimate_address_p ( VOIDmode , XEXP ( x , 0 ) , 0 ) ) ; case 'T' : return 0 ; case 'U' : return ( GET_CODE ( x ) == CONST_INT && ( INTVAL ( x ) < 2 || INTVAL ( x ) > 15 ) ) ; case 'Z' : return ( GET_CODE ( x ) == CONST_INT && ( INTVAL ( x ) == 0 ) ) ; case 'W' : return xstormy16_below100_operand ( x , GET_MODE ( x ) ) ; default : return 0 ; } } </s>

A C expression that defines the optional machine-dependent constraint letters ( ` Q ' , ` R ' , ` S ' , ` T ' , ` U ' ) that can be used to segregate specific types of operands , usually memory references , for the target machine . Normally this macro will not be defined . If it is required for a particular target machine , it should return 1 if VALUE corresponds to the operand type represented by the constraint letter C. If C is not defined as an extra constraint , the value returned should be 0 regardless of VALUE .


<s> unsigned ARMRegisterInfo :: getRARegister ( ) const { return ARM :: LR ; } </s>

This method should return the register where the return address can be found .


<s> bool isImm ( ) const { return Kind == Immediate ; } </s>


<s> static void reorder_var_tracking_notes ( void ) { basic_block bb ; FOR_EACH_BB_FN ( bb , cfun ) { rtx_insn * insn , * next ; rtx_insn * queue = NULL ; bool in_bundle = false ; for ( insn = BB_HEAD ( bb ) ; insn != BB_END ( bb ) ; insn = next ) { next = NEXT_INSN ( insn ) ; if ( INSN_P ( insn ) ) { if ( GET_MODE ( insn ) == QImode ) { while ( queue ) { rtx_insn * next_queue = PREV_INSN ( queue ) ; SET_PREV_INSN ( NEXT_INSN ( insn ) ) = queue ; SET_NEXT_INSN ( queue ) = NEXT_INSN ( insn ) ; SET_NEXT_INSN ( insn ) = queue ; SET_PREV_INSN ( queue ) = insn ; queue = next_queue ; } in_bundle = false ; } else if ( GET_MODE ( insn ) == SImode ) in_bundle = true ; } else if ( NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_VAR_LOCATION ) { if ( in_bundle ) { rtx_insn * prev = PREV_INSN ( insn ) ; SET_PREV_INSN ( next ) = prev ; SET_NEXT_INSN ( prev ) = next ; SET_PREV_INSN ( insn ) = queue ; queue = insn ; } } } } } </s>

Ensure that no var tracking notes are emitted in the middle of a three-instruction bundle .


<s> bool X86IndirectBranchTrackingPass :: runOnMachineFunction ( MachineFunction & MF ) { const X86Subtarget & SubTarget = MF . getSubtarget < X86Subtarget > ( ) ; if ( ! SubTarget . hasIBT ( ) ) return false ; Metadata * isCFProtectionSupported = MF . getMMI ( ) . getModule ( ) -> getModuleFlag ( "cf-protection-branch" ) ; if ( ! isCFProtectionSupported && ! IndirectBranchTracking ) return false ; bool Changed = false ; TII = SubTarget . getInstrInfo ( ) ; EndbrOpcode = SubTarget . is64Bit ( ) ? X86 :: ENDBR64 : X86 :: ENDBR32 ; if ( ( MF . getFunction ( ) . hasAddressTaken ( ) || ! MF . getFunction ( ) . hasLocalLinkage ( ) ) && ! MF . getFunction ( ) . doesNoCfCheck ( ) ) { auto MBB = MF . begin ( ) ; Changed |= addENDBR ( * MBB ) ; } for ( auto & MBB : MF ) if ( MBB . hasAddressTaken ( ) ) Changed |= addENDBR ( MBB ) ; return Changed ; } </s>


<s> void SITypeRewriter :: visitCallInst ( CallInst & I ) { IRBuilder < > Builder ( & I ) ; SmallVector < Value * , 8 > Args ; SmallVector < Type * , 8 > Types ; bool NeedToReplace = false ; Function * F = I . getCalledFunction ( ) ; std :: string Name = F -> getName ( ) ; for ( unsigned i = 0 , e = I . getNumArgOperands ( ) ; i != e ; ++ i ) { Value * Arg = I . getArgOperand ( i ) ; if ( Arg -> getType ( ) == v16i8 ) { Args . push_back ( Builder . CreateBitCast ( Arg , v4i32 ) ) ; Types . push_back ( v4i32 ) ; NeedToReplace = true ; Name = Name + ".v4i32" ; } else if ( Arg -> getType ( ) -> isVectorTy ( ) && Arg -> getType ( ) -> getVectorNumElements ( ) == 1 && Arg -> getType ( ) -> getVectorElementType ( ) == Type :: getInt32Ty ( I . getContext ( ) ) ) { Type * ElementTy = Arg -> getType ( ) -> getVectorElementType ( ) ; std :: string TypeName = "i32" ; InsertElementInst * Def = cast < InsertElementInst > ( Arg ) ; Args . push_back ( Def -> getOperand ( 1 ) ) ; Types . push_back ( ElementTy ) ; std :: string VecTypeName = "v1" + TypeName ; Name = Name . replace ( Name . find ( VecTypeName ) , VecTypeName . length ( ) , TypeName ) ; NeedToReplace = true ; } else { Args . push_back ( Arg ) ; Types . push_back ( Arg -> getType ( ) ) ; } } if ( ! NeedToReplace ) { return ; } Function * NewF = Mod -> getFunction ( Name ) ; if ( ! NewF ) { NewF = Function :: Create ( FunctionType :: get ( F -> getReturnType ( ) , Types , false ) , GlobalValue :: ExternalLinkage , Name , Mod ) ; NewF -> setAttributes ( F -> getAttributes ( ) ) ; } I . replaceAllUsesWith ( Builder . CreateCall ( NewF , Args ) ) ; I . eraseFromParent ( ) ; } </s>


<s>
const
MCFixupKindInfo
&
OR1KAsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
OR1K
::
NumTargetFixupKinds
]
=
{
{
"fixup_OR1K_NONE"
,
0
,
32
,
0
}
,
{
"fixup_OR1K_32"
,
0
,
32
,
0
}
,
{
"fixup_OR1K_16"
,
16
,
16
,
0
}
,
{
"fixup_OR1K_8"
,
24
,
8
,
0
}
,
{
"fixup_OR1K_LO16_INSN"
,
16
,
16
,
0
}
,
{
"fixup_OR1K_HI16_INSN"
,
16
,
16
,
0
}
,
{
"fixup_OR1K_REL26"
,
6
,
26
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_OR1K_PCREL32"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_OR1K_PCREL16"
,
16
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_OR1K_PCREL8"
,
24
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_OR1K_GOTPC_HI16"
,
16
,
16
,
0
}
,
{
"fixup_OR1K_GOTPC_LO16"
,
16
,
16
,
0
}
,
{
"fixup_OR1K_GOT16"
,
16
,
16
,
0
}
,
{
"fixup_OR1K_PLT26"
,
6
,
26
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_OR1K_GOTOFF_HI16"
,
16
,
16
,
0
}
,
{
"fixup_OR1K_GOTOFF_LO16"
,
16
,
16
,
0
}
,
{
"fixup_OR1K_COPY"
,
0
,
32
,
0
}
,
{
"fixup_OR1K_GLOB_DAT"
,
0
,
32
,
0
}
,
{
"fixup_OR1K_JMP_SLOT"
,
0
,
32
,
0
}
,
{
"fixup_OR1K_RELATIVE"
,
0
,
32
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> bool ARMBaseInstrInfo :: areLoadsFromSameBasePtr ( SDNode * Load1 , SDNode * Load2 , int64_t & Offset1 , int64_t & Offset2 ) const { if ( Subtarget . isThumb1Only ( ) ) return false ; if ( ! Load1 -> isMachineOpcode ( ) || ! Load2 -> isMachineOpcode ( ) ) return false ; switch ( Load1 -> getMachineOpcode ( ) ) { default : return false ; case ARM :: LDRi12 : case ARM :: LDRBi12 : case ARM :: LDRD : case ARM :: LDRH : case ARM :: LDRSB : case ARM :: LDRSH : case ARM :: VLDRD : case ARM :: VLDRS : case ARM :: t2LDRi8 : case ARM :: t2LDRBi8 : case ARM :: t2LDRDi8 : case ARM :: t2LDRSHi8 : case ARM :: t2LDRi12 : case ARM :: t2LDRBi12 : case ARM :: t2LDRSHi12 : break ; } switch ( Load2 -> getMachineOpcode ( ) ) { default : return false ; case ARM :: LDRi12 : case ARM :: LDRBi12 : case ARM :: LDRD : case ARM :: LDRH : case ARM :: LDRSB : case ARM :: LDRSH : case ARM :: VLDRD : case ARM :: VLDRS : case ARM :: t2LDRi8 : case ARM :: t2LDRBi8 : case ARM :: t2LDRSHi8 : case ARM :: t2LDRi12 : case ARM :: t2LDRBi12 : case ARM :: t2LDRSHi12 : break ; } if ( Load1 -> getOperand ( 0 ) != Load2 -> getOperand ( 0 ) || Load1 -> getOperand ( 4 ) != Load2 -> getOperand ( 4 ) ) return false ; if ( Load1 -> getOperand ( 3 ) != Load2 -> getOperand ( 3 ) ) return false ; if ( isa < ConstantSDNode > ( Load1 -> getOperand ( 1 ) ) && isa < ConstantSDNode > ( Load2 -> getOperand ( 1 ) ) ) { Offset1 = cast < ConstantSDNode > ( Load1 -> getOperand ( 1 ) ) -> getSExtValue ( ) ; Offset2 = cast < ConstantSDNode > ( Load2 -> getOperand ( 1 ) ) -> getSExtValue ( ) ; return true ; } return false ; } </s>

areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address .


<s> void s390_expand_split_stack_prologue ( void ) { rtx r1 , guard , cc = NULL ; rtx_insn * insn ; int psso = TARGET_64BIT ? 0x38 : 0x20 ; HOST_WIDE_INT frame_size = cfun_frame_layout . frame_size ; HOST_WIDE_INT args_size = crtl -> args . size >= 0 ? ( ( crtl -> args . size + 7 ) & ~ 7 ) : 0 ; rtx_code_label * call_done = NULL ; rtx_code_label * parm_base = NULL ; rtx tmp ; gcc_assert ( flag_split_stack && reload_completed ) ; r1 = gen_rtx_REG ( Pmode , 1 ) ; if ( ! frame_size ) { if ( cfun -> machine -> split_stack_varargs_pointer != NULL_RTX ) { emit_move_insn ( r1 , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( STACK_POINTER_OFFSET ) ) ) ; } return ; } if ( morestack_ref == NULL_RTX ) { morestack_ref = gen_rtx_SYMBOL_REF ( Pmode , "__morestack" ) ; SYMBOL_REF_FLAGS ( morestack_ref ) |= ( SYMBOL_FLAG_LOCAL | SYMBOL_FLAG_FUNCTION ) ; } if ( CONST_OK_FOR_K ( frame_size ) || CONST_OK_FOR_Op ( frame_size ) ) { emit_move_insn ( r1 , gen_rtx_REG ( Pmode , TP_REGNUM ) ) ; guard = gen_rtx_MEM ( Pmode , plus_constant ( Pmode , r1 , psso ) ) ; if ( frame_size > SPLIT_STACK_AVAILABLE ) { emit_move_insn ( r1 , guard ) ; if ( TARGET_64BIT ) emit_insn ( gen_adddi3 ( r1 , r1 , GEN_INT ( frame_size ) ) ) ; else emit_insn ( gen_addsi3 ( r1 , r1 , GEN_INT ( frame_size ) ) ) ; guard = r1 ; } cc = s390_emit_compare ( LT , stack_pointer_rtx , guard ) ; } call_done = gen_label_rtx ( ) ; parm_base = gen_label_rtx ( ) ; tmp = gen_split_stack_data ( parm_base , call_done , GEN_INT ( frame_size ) , GEN_INT ( args_size ) ) ; insn = emit_insn ( tmp ) ; add_reg_note ( insn , REG_LABEL_OPERAND , call_done ) ; LABEL_NUSES ( call_done ) ++ ; add_reg_note ( insn , REG_LABEL_OPERAND , parm_base ) ; LABEL_NUSES ( parm_base ) ++ ; insn = emit_move_insn ( r1 , gen_rtx_LABEL_REF ( VOIDmode , parm_base ) ) ; add_reg_note ( insn , REG_LABEL_OPERAND , parm_base ) ; LABEL_NUSES ( parm_base ) ++ ; if ( cc != NULL ) { tmp = gen_split_stack_cond_call ( morestack_ref , cc , call_done ) ; insn = emit_jump_insn ( tmp ) ; JUMP_LABEL ( insn ) = call_done ; LABEL_NUSES ( call_done ) ++ ; add_reg_br_prob_note ( insn , profile_probability :: very_unlikely ( ) ) ; if ( cfun -> machine -> split_stack_varargs_pointer != NULL_RTX ) { emit_move_insn ( r1 , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( STACK_POINTER_OFFSET ) ) ) ; } } else { tmp = gen_split_stack_call ( morestack_ref , call_done ) ; insn = emit_jump_insn ( tmp ) ; JUMP_LABEL ( insn ) = call_done ; LABEL_NUSES ( call_done ) ++ ; emit_barrier ( ) ; } emit_label ( call_done ) ; } </s>

Emit -fsplit-stack prologue , which goes before the regular function prologue .


<s> unsigned HexagonMCInstrInfo :: getType ( MCInstrInfo const & MCII , MCInst const & MCI ) { const uint64_t F = MCII . get ( MCI . getOpcode ( ) ) . TSFlags ; return ( ( F >> HexagonII :: TypePos ) & HexagonII :: TypeMask ) ; } </s>

Overload to return most specific vector type .

Hexagon Hexagon HexagonII::TypePos HexagonII::TypeMask


<s>
bool
ARMAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
this
->
MF
=
&
MF
;
AFI
=
MF
.
getInfo
<
ARMFunctionInfo
>
(
)
;
MCP
=
MF
.
getConstantPool
(
)
;
SetupMachineFunction
(
MF
)
;
O
<<
"\n"
;
O
<<
'\n'
;
const
Function
*
F
=
MF
.
getFunction
(
)
;
OutStreamer
.
SwitchSection
(
getObjFileLowering
(
)
.
SectionForGlobal
(
F
,
Mang
,
TM
)
)
;
switch
(
F
->
getLinkage
(
)
)
{
default
:
llvm_unreachable
(
"Unknown linkage type!"
)
;
case
Function
::
PrivateLinkage
:
case
Function
::
LinkerPrivateLinkage
:
case
Function
::
InternalLinkage
:
break
;
case
Function
::
ExternalLinkage
:
O
<<
"\t.globl\t"
<<
CurrentFnName
<<
"\n"
;
break
;
case
Function
::
WeakAnyLinkage
:
case
Function
::
WeakODRLinkage
:
case
Function
::
LinkOnceAnyLinkage
:
case
Function
::
LinkOnceODRLinkage
:
if
(
Subtarget
->
isTargetDarwin
(
)
)
{
O
<<
"\t.globl\t"
<<
CurrentFnName
<<
"\n"
;
O
<<
"\t.weak_definition\t"
<<
CurrentFnName
<<
"\n"
;
}
else
{
O
<<
TAI
->
getWeakRefDirective
(
)
<<
CurrentFnName
<<
"\n"
;
}
break
;
}
printVisibility
(
CurrentFnName
,
F
->
getVisibility
(
)
)
;
if
(
AFI
->
isThumbFunction
(
)
)
{
EmitAlignment
(
MF
.
getAlignment
(
)
,
F
,
AFI
->
getAlign
(
)
)
;
O
<<
"\t.code\t16\n"
;
O
<<
"\t.thumb_func"
;
if
(
Subtarget
->
isTargetDarwin
(
)
)
O
<<
"\t"
<<
CurrentFnName
;
O
<<
"\n"
;
InCPMode
=
false
;
}
else
{
EmitAlignment
(
MF
.
getAlignment
(
)
,
F
)
;
}
O
<<
CurrentFnName
<<
":\n"
;
DW
->
BeginFunction
(
&
MF
)
;
if
(
Subtarget
->
isTargetDarwin
(
)
)
{
MachineFunction
::
iterator
I
=
MF
.
begin
(
)
;
if
(
++
I
==
MF
.
end
(
)
&&
MF
.
front
(
)
.
empty
(
)
)
O
<<
"\tnop\n"
;
}
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
I
!=
MF
.
begin
(
)
)
{
printBasicBlockLabel
(
I
,
true
,
true
,
VerboseAsm
)
;
O
<<
'\n'
;
}
for
(
MachineBasicBlock
::
const_iterator
II
=
I
->
begin
(
)
,
E
=
I
->
end
(
)
;
II
!=
E
;
++
II
)
{
printMachineInstruction
(
II
)
;
}
}
if
(
TAI
->
hasDotTypeDotSizeDirective
(
)
)
O
<<
"\t.size "
<<
CurrentFnName
<<
", .-"
<<
CurrentFnName
<<
"\n"
;
DW
->
EndFunction
(
&
MF
)
;
return
false
;
}
</s>

ARM
ARM
ARM
"\n"
"Unknown linkage type!"
"\t.globl\t"
"\n"
"\t.globl\t"
"\n"
"\t.weak_definition\t"
"\n"
"\n"
"\t.code\t16\n"
"\t.thumb_func"
"\t"
"\n"
":\n"
"\tnop\n"
"\t.size "
", .-"
"\n"


<s>
static
bool
ix86_function_ok_for_sibcall
(
tree
decl
,
tree
exp
)
{
tree
type
,
decl_or_type
;
rtx
a
,
b
;
bool
bind_global
=
decl
&&
!
targetm
.
binds_local_p
(
decl
)
;
if
(
ix86_function_naked
(
current_function_decl
)
)
return
false
;
if
(
cfun
->
machine
->
no_caller_saved_registers
)
return
false
;
if
(
!
TARGET_MACHO
&&
!
TARGET_64BIT
&&
flag_pic
&&
flag_plt
&&
bind_global
)
return
false
;
if
(
ix86_minimum_incoming_stack_boundary
(
true
)
<
PREFERRED_STACK_BOUNDARY
)
return
false
;
if
(
decl
)
{
decl_or_type
=
decl
;
type
=
TREE_TYPE
(
decl
)
;
}
else
{
type
=
CALL_EXPR_FN
(
exp
)
;
type
=
TREE_TYPE
(
type
)
;
type
=
TREE_TYPE
(
type
)
;
decl_or_type
=
type
;
}
if
(
(
OUTGOING_REG_PARM_STACK_SPACE
(
type
)
!=
OUTGOING_REG_PARM_STACK_SPACE
(
TREE_TYPE
(
current_function_decl
)
)
)
||
(
REG_PARM_STACK_SPACE
(
decl_or_type
)
!=
REG_PARM_STACK_SPACE
(
current_function_decl
)
)
)
{
maybe_complain_about_tail_call
(
exp
,
"inconsistent size of stack space"
" allocated for arguments which are"
" passed in registers"
)
;
return
false
;
}
a
=
ix86_function_value
(
TREE_TYPE
(
exp
)
,
decl_or_type
,
false
)
;
b
=
ix86_function_value
(
TREE_TYPE
(
DECL_RESULT
(
cfun
->
decl
)
)
,
cfun
->
decl
,
false
)
;
if
(
STACK_REG_P
(
a
)
||
STACK_REG_P
(
b
)
)
{
if
(
!
rtx_equal_p
(
a
,
b
)
)
return
false
;
}
else
if
(
VOID_TYPE_P
(
TREE_TYPE
(
DECL_RESULT
(
cfun
->
decl
)
)
)
)
;
else
if
(
!
rtx_equal_p
(
a
,
b
)
)
return
false
;
if
(
TARGET_64BIT
)
{
if
(
cfun
->
machine
->
call_abi
==
MS_ABI
&&
ix86_function_type_abi
(
type
)
==
SYSV_ABI
)
return
false
;
}
else
{
if
(
!
decl
||
(
bind_global
&&
flag_pic
&&
!
flag_plt
)
||
(
TARGET_DLLIMPORT_DECL_ATTRIBUTES
&&
DECL_DLLIMPORT_P
(
decl
)
)
||
flag_force_indirect_call
)
{
if
(
ix86_function_regparm
(
type
,
decl
)
>=
3
&&
!
cfun
->
machine
->
arg_reg_available
)
return
false
;
}
}
return
true
;
}
</s>

Decide whether we can make a sibling call to a function . DECL is the declaration of the function being targeted by the call and EXP is the CALL_EXPR representing the call .


<s> void rs6000_gen_section_name ( char * * buf , const char * filename , const char * section_desc ) { const char * q , * after_last_slash , * last_period = 0 ; char * p ; int len ; after_last_slash = filename ; for ( q = filename ; * q ; q ++ ) { if ( * q == '/' ) after_last_slash = q + 1 ; else if ( * q == '.' ) last_period = q ; } len = strlen ( after_last_slash ) + strlen ( section_desc ) + 2 ; * buf = ( char * ) xmalloc ( len ) ; p = * buf ; * p ++ = '_' ; for ( q = after_last_slash ; * q ; q ++ ) { if ( q == last_period ) { strcpy ( p , section_desc ) ; p += strlen ( section_desc ) ; break ; } else if ( ISALNUM ( * q ) ) * p ++ = * q ; } if ( last_period == 0 ) strcpy ( p , section_desc ) ; else * p = '\0' ; } </s>

Generate a unique section name for FILENAME for a section type represented by SECTION_DESC . Output goes into BUF . SECTION_DESC can be any string , as long as it is different for each possible section type . We name the section in the same manner as xlc . The name begins with an underscore followed by the filename ( after stripping any leading directory names ) with the last period replaced by the string SECTION_DESC . If FILENAME does not contain a period , SECTION_DESC is appended to the end of the name .


<s> static inline rtx s390_expand_mask_and_shift ( rtx val , enum machine_mode mode , rtx count ) { val = expand_simple_binop ( SImode , AND , val , GEN_INT ( GET_MODE_MASK ( mode ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ; return expand_simple_binop ( SImode , ASHIFT , val , count , NULL_RTX , 1 , OPTAB_DIRECT ) ; } </s>

A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a register that holds VAL of mode MODE shifted by COUNT bits .


<s> TargetTransformInfo VETargetMachine :: getTargetTransformInfo ( const Function & F ) const { return TargetTransformInfo ( VETTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> void RISCVPassConfig :: addPreEmitPass ( ) { addPass ( & BranchRelaxationPassID ) ; addPass ( createRISCVMakeCompressibleOptPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static bool isConstant ( const MachineOperand & MO , int64_t & C ) { const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const MachineInstr * Def = MRI . getVRegDef ( MO . getReg ( ) ) ; if ( ! Def ) return false ; if ( Def -> getOpcode ( ) == AMDGPU :: G_CONSTANT ) { C = Def -> getOperand ( 1 ) . getCImm ( ) -> getSExtValue ( ) ; return true ; } if ( Def -> getOpcode ( ) == AMDGPU :: COPY ) return isConstant ( Def -> getOperand ( 1 ) , C ) ; return false ; } </s>

Returns true if we know the value of all bits .


getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned ' is on an i32 first argument if the calling convention is one that can ( partially ) model this attribute with a preserved mask ( i.e .


<s> static bool m32c_function_needs_enter ( void ) { rtx insn ; struct sequence_stack * seq ; rtx sp = gen_rtx_REG ( Pmode , SP_REGNO ) ; rtx fb = gen_rtx_REG ( Pmode , FB_REGNO ) ; insn = get_insns ( ) ; for ( seq = cfun -> emit -> sequence_stack ; seq ; insn = seq -> first , seq = seq -> next ) ; while ( insn ) { if ( reg_mentioned_p ( sp , insn ) ) return true ; if ( reg_mentioned_p ( fb , insn ) ) return true ; insn = NEXT_INSN ( insn ) ; } return false ; } </s>

Returns TRUE if the current function needs to use the ENTER/EXIT opcodes . If the function does n't need the frame base or stack pointer , it can use the simpler RTS opcode .


<s> void riscv_set_return_address ( rtx address , rtx scratch ) { rtx slot_address ; gcc_assert ( BITSET_P ( cfun -> machine -> frame . mask , RETURN_ADDR_REGNUM ) ) ; slot_address = riscv_add_offset ( scratch , stack_pointer_rtx , cfun -> machine -> frame . gp_sp_offset . to_constant ( ) ) ; riscv_emit_move ( gen_frame_mem ( GET_MODE ( address ) , slot_address ) , address ) ; } </s>

Emit code to change the current function 's return address to ADDRESS . SCRATCH is available as a scratch register , if needed . ADDRESS and SCRATCH are both word-mode GPRs .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; X86MachineFunctionInfo * MFI = MF . getInfo < X86MachineFunctionInfo > ( ) ; if ( MFI -> getNumLocalDynamicTLSAccesses ( ) < 2 ) { return false ; } MachineDominatorTree * DT = & getAnalysis < MachineDominatorTree > ( ) ; return VisitNode ( DT -> getRootNode ( ) , 0 ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> static rtx rs6000_finish_function_arg ( machine_mode mode , rtx * rvec , int k ) { gcc_assert ( k >= 1 ) ; if ( k == 1 ) { if ( XEXP ( rvec [ 0 ] , 0 ) == NULL_RTX ) return NULL_RTX ; if ( GET_MODE ( XEXP ( rvec [ 0 ] , 0 ) ) == mode ) return XEXP ( rvec [ 0 ] , 0 ) ; } return gen_rtx_PARALLEL ( mode , gen_rtvec_v ( k , rvec ) ) ; } </s>

RVEC is a vector of K components of an argument of mode MODE . Construct the final function_arg return value from it .


<s> StringRef getPassName ( ) const override { return RISCV_COMPRESS_INSTRS_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> static void alpha_emit_xfloating_libcall ( rtx func , rtx target , rtx operands [ ] , int noperands , rtx equiv ) { rtx usage = NULL_RTX , tmp , reg ; int regno = 16 , i ; start_sequence ( ) ; for ( i = 0 ; i < noperands ; ++ i ) { switch ( GET_MODE ( operands [ i ] ) ) { case TFmode : reg = gen_rtx_REG ( TFmode , regno ) ; regno += 2 ; break ; case DFmode : reg = gen_rtx_REG ( DFmode , regno + 32 ) ; regno += 1 ; break ; case VOIDmode : gcc_assert ( CONST_INT_P ( operands [ i ] ) ) ; case DImode : reg = gen_rtx_REG ( DImode , regno ) ; regno += 1 ; break ; default : gcc_unreachable ( ) ; } emit_move_insn ( reg , operands [ i ] ) ; use_reg ( & usage , reg ) ; } switch ( GET_MODE ( target ) ) { case TFmode : reg = gen_rtx_REG ( TFmode , 16 ) ; break ; case DFmode : reg = gen_rtx_REG ( DFmode , 32 ) ; break ; case DImode : reg = gen_rtx_REG ( DImode , 0 ) ; break ; default : gcc_unreachable ( ) ; } tmp = gen_rtx_MEM ( QImode , func ) ; tmp = emit_call_insn ( GEN_CALL_VALUE ( reg , tmp , const0_rtx , const0_rtx , const0_rtx ) ) ; CALL_INSN_FUNCTION_USAGE ( tmp ) = usage ; RTL_CONST_CALL_P ( tmp ) = 1 ; tmp = get_insns ( ) ; end_sequence ( ) ; emit_libcall_block ( tmp , target , reg , equiv ) ; } </s>

Emit an X_floating library function call . Note that these functions do not follow normal calling conventions : TFmode arguments are passed in two integer registers ( as opposed to indirect ) ; TFmode return values appear in R16+R17 . FUNC is the function name to call . TARGET is where the output belongs . OPERANDS are the inputs . NOPERANDS is the count of inputs . EQUIV is the expression equivalent for the function .


<s> SparcSubtarget & SparcSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { UseSoftMulDiv = false ; IsV9 = false ; IsLeon = false ; V8DeprecatedInsts = false ; IsVIS = false ; HasHardQuad = false ; UsePopc = false ; UseSoftFloat = false ; HasLeonCasa = false ; HasUmacSmac = false ; PerformSDIVReplace = false ; InsertNOPLoad = false ; FixFSMULD = false ; ReplaceFMULS = false ; FixAllFDIVSQRT = false ; DetectRoundChange = false ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? "v9" : "v8" ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( ! IsV9 ) UsePopc = false ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> static void microblaze_elf_asm_constructor ( rtx symbol , int priority ) { microblaze_elf_asm_cdtor ( symbol , priority , true ) ; } </s>

Add a function to the list of static constructors .


<s> void MOSMCELFStreamer :: emitValueImpl ( const MCExpr * Value , unsigned Size , SMLoc Loc ) { if ( const auto * MME = dyn_cast < MOSMCExpr > ( Value ) ) { if ( MME -> getKind ( ) == MOSMCExpr :: VK_MOS_ADDR_ASCIZ ) { emitMosAddrAsciz ( MME -> getSubExpr ( ) , Size , Loc ) ; return ; } } MCELFStreamer :: emitValueImpl ( Value , Size , Loc ) ; } </s>

Overriding these functions allows us to dismiss all labels that are candidates for marking as microMIPS when .word/.long/.4byte etc directives are emitted .


<s>
bool
runOnMachineFunction
(
MachineFunction
&
MF
)
override
{
LLVM_DEBUG
(
dbgs
(
)
<<
"********** ISelDAGToDAG **********\n"
"********** Function: "
<<
MF
.
getName
(
)
<<
'\n'
)
;
ForCodeSize
=
MF
.
getFunction
(
)
.
hasFnAttribute
(
Attribute
::
OptimizeForSize
)
||
MF
.
getFunction
(
)
.
hasFnAttribute
(
Attribute
::
MinSize
)
;
Subtarget
=
&
MF
.
getSubtarget
<
WebAssemblySubtarget
>
(
)
;
return
SelectionDAGISel
::
runOnMachineFunction
(
MF
)
;
}
</s>

WebAssembly
"********** ISelDAGToDAG **********\n"
"********** Function: "
WebAssembly


<s>
Value
*
PPCTargetLowering
::
emitMaskedAtomicCmpXchgIntrinsic
(
IRBuilderBase
&
Builder
,
AtomicCmpXchgInst
*
CI
,
Value
*
AlignedAddr
,
Value
*
CmpVal
,
Value
*
NewVal
,
Value
*
Mask
,
AtomicOrdering
Ord
)
const
{
assert
(
shouldInlineQuadwordAtomics
(
)
&&
"Only support quadword now"
)
;
Module
*
M
=
Builder
.
GetInsertBlock
(
)
->
getParent
(
)
->
getParent
(
)
;
Type
*
ValTy
=
CmpVal
->
getType
(
)
;
assert
(
ValTy
->
getPrimitiveSizeInBits
(
)
==
128
)
;
Function
*
IntCmpXchg
=
Intrinsic
::
getDeclaration
(
M
,
Intrinsic
::
ppc_cmpxchg_i128
)
;
Type
*
Int64Ty
=
Type
::
getInt64Ty
(
M
->
getContext
(
)
)
;
Value
*
CmpLo
=
Builder
.
CreateTrunc
(
CmpVal
,
Int64Ty
,
"cmp_lo"
)
;
Value
*
CmpHi
=
Builder
.
CreateTrunc
(
Builder
.
CreateLShr
(
CmpVal
,
64
)
,
Int64Ty
,
"cmp_hi"
)
;
Value
*
NewLo
=
Builder
.
CreateTrunc
(
NewVal
,
Int64Ty
,
"new_lo"
)
;
Value
*
NewHi
=
Builder
.
CreateTrunc
(
Builder
.
CreateLShr
(
NewVal
,
64
)
,
Int64Ty
,
"new_hi"
)
;
Value
*
Addr
=
Builder
.
CreateBitCast
(
AlignedAddr
,
Type
::
getInt8PtrTy
(
M
->
getContext
(
)
)
)
;
emitLeadingFence
(
Builder
,
CI
,
Ord
)
;
Value
*
LoHi
=
Builder
.
CreateCall
(
IntCmpXchg
,
{
Addr
,
CmpLo
,
CmpHi
,
NewLo
,
NewHi
}
)
;
emitTrailingFence
(
Builder
,
CI
,
Ord
)
;
Value
*
Lo
=
Builder
.
CreateExtractValue
(
LoHi
,
0
,
"lo"
)
;
Value
*
Hi
=
Builder
.
CreateExtractValue
(
LoHi
,
1
,
"hi"
)
;
Lo
=
Builder
.
CreateZExt
(
Lo
,
ValTy
,
"lo64"
)
;
Hi
=
Builder
.
CreateZExt
(
Hi
,
ValTy
,
"hi64"
)
;
return
Builder
.
CreateOr
(
Lo
,
Builder
.
CreateShl
(
Hi
,
ConstantInt
::
get
(
ValTy
,
64
)
)
,
"val64"
)
;
}
</s>

Perform a masked cmpxchg using a target-specific intrinsic .


<s> static bool arm_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) { return arg . type && TREE_CODE ( TYPE_SIZE ( arg . type ) ) != INTEGER_CST ; } </s>

Variable sized types are passed by reference . This is a GCC extension to the ARM ABI .


<s> unsigned X86InstrInfo :: getOpcodeAfterMemoryUnfold ( unsigned Opc , bool UnfoldLoad , bool UnfoldStore , unsigned * LoadRegIndex ) const { DenseMap < unsigned * , std :: pair < unsigned , unsigned > > :: const_iterator I = MemOp2RegOpTable . find ( ( unsigned * ) Opc ) ; if ( I == MemOp2RegOpTable . end ( ) ) return 0 ; bool FoldedLoad = I -> second . second & ( 1 << 4 ) ; bool FoldedStore = I -> second . second & ( 1 << 5 ) ; if ( UnfoldLoad && ! FoldedLoad ) return 0 ; if ( UnfoldStore && ! FoldedStore ) return 0 ; if ( LoadRegIndex ) * LoadRegIndex = I -> second . second & 0xf ; return I -> second . first ; } </s>

getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode .


<s>
virtual
StringRef
getPassName
(
)
const
override
{
return
"Cpu0 Assmebly Printer"
;
}
</s>


<s> static bool aapcs_vfp_allocate ( CUMULATIVE_ARGS * pcum , machine_mode mode , const_tree type ATTRIBUTE_UNUSED ) { int shift = GET_MODE_SIZE ( pcum -> aapcs_vfp_rmode ) / GET_MODE_SIZE ( SFmode ) ; unsigned mask = ( 1 << ( shift * pcum -> aapcs_vfp_rcount ) ) - 1 ; int regno ; for ( regno = 0 ; regno < NUM_VFP_ARG_REGS ; regno += shift ) if ( ( ( pcum -> aapcs_vfp_regs_free >> regno ) & mask ) == mask ) { pcum -> aapcs_vfp_reg_alloc = mask << regno ; if ( mode == BLKmode || ( mode == TImode && ! TARGET_NEON ) || ! arm_hard_regno_mode_ok ( FIRST_VFP_REGNUM + regno , mode ) ) { int i ; int rcount = pcum -> aapcs_vfp_rcount ; int rshift = shift ; machine_mode rmode = pcum -> aapcs_vfp_rmode ; rtx par ; if ( ! TARGET_NEON ) { if ( rmode == V2SImode ) rmode = DImode ; else if ( rmode == V4SImode ) { rmode = DImode ; rcount *= 2 ; rshift /= 2 ; } } par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( rcount ) ) ; for ( i = 0 ; i < rcount ; i ++ ) { rtx tmp = gen_rtx_REG ( rmode , FIRST_VFP_REGNUM + regno + i * rshift ) ; tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , GEN_INT ( i * GET_MODE_SIZE ( rmode ) ) ) ; XVECEXP ( par , 0 , i ) = tmp ; } pcum -> aapcs_reg = par ; } else pcum -> aapcs_reg = gen_rtx_REG ( mode , FIRST_VFP_REGNUM + regno ) ; return true ; } return false ; } </s>

Implement the allocate field in aapcs_cp_arg_layout . See the comment there for the behaviour of this function .


"Can only insert epilog into returning blocks"


<s> void AArch64PassConfig :: addPreEmitPass ( ) { if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Aggressive && EnableLoadStoreOpt ) addPass ( createAArch64LoadStoreOptimizationPass ( ) ) ; if ( EnableA53Fix835769 ) addPass ( createAArch64A53Fix835769 ( ) ) ; if ( EnableBranchTargets ) addPass ( createAArch64BranchTargetsPass ( ) ) ; if ( BranchRelaxation ) addPass ( & BranchRelaxationPassID ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardLongjmpPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCompressJumpTables ) addPass ( createAArch64CompressJumpTablesPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; addPass ( createUnpackMachineBundles ( nullptr ) ) ; } </s>


<s> static bool tilegx_return_in_memory ( const_tree type , const_tree fndecl ATTRIBUTE_UNUSED ) { return ! IN_RANGE ( int_size_in_bytes ( type ) , 0 , TILEGX_NUM_RETURN_REGS * UNITS_PER_WORD ) ; } </s>


<s> void rl78_expand_eh_epilogue ( rtx x ATTRIBUTE_UNUSED ) { emit_jump_insn ( gen_rl78_return ( ) ) ; } </s>


<s> static rtx rs6000_complex_function_value ( enum machine_mode mode ) { unsigned int regno ; rtx r1 , r2 ; enum machine_mode inner = GET_MODE_INNER ( mode ) ; unsigned int inner_bytes = GET_MODE_SIZE ( inner ) ; if ( FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = FP_ARG_RETURN ; else { regno = GP_ARG_RETURN ; if ( TARGET_32BIT && inner_bytes >= 4 ) return gen_rtx_REG ( mode , regno ) ; } if ( inner_bytes >= 8 ) return gen_rtx_REG ( mode , regno ) ; r1 = gen_rtx_EXPR_LIST ( inner , gen_rtx_REG ( inner , regno ) , const0_rtx ) ; r2 = gen_rtx_EXPR_LIST ( inner , gen_rtx_REG ( inner , regno + 1 ) , GEN_INT ( inner_bytes ) ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , r1 , r2 ) ) ; } </s>

Return an RTX representing where to find the function value of a function returning MODE .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
X86
::
NumTargetFixupKinds
]
=
{
{
"reloc_riprel_4byte"
,
0
,
4
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_movq_load"
,
0
,
4
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_signed_4byte"
,
0
,
4
*
8
,
0
}
,
{
"reloc_global_offset_table"
,
0
,
4
*
8
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


Return the cache associatvity for the given level of cache .


<s> void arm_emit_speculation_barrier_function ( ) { emit_library_call ( speculation_barrier_libfunc , LCT_NORMAL , VOIDmode ) ; } </s>

Emit a speculation barrier on target architectures that do not have DSB/ISB directly . Such systems probably do n't need a barrier themselves , but if the code is ever run on a later architecture , it might become a problem .


<s> static bool ix86_expand_vec_one_operand_perm_avx512 ( struct expand_vec_perm_d * d ) { machine_mode mode = GET_MODE ( d -> op0 ) ; machine_mode maskmode = mode ; rtx ( * gen ) ( rtx , rtx , rtx ) = NULL ; rtx target , op0 , mask ; rtx vec [ 64 ] ; if ( ! rtx_equal_p ( d -> op0 , d -> op1 ) ) return false ; if ( ! TARGET_AVX512F ) return false ; switch ( mode ) { case V16SImode : gen = gen_avx512f_permvarv16si ; break ; case V16SFmode : gen = gen_avx512f_permvarv16sf ; maskmode = V16SImode ; break ; case V8DImode : gen = gen_avx512f_permvarv8di ; break ; case V8DFmode : gen = gen_avx512f_permvarv8df ; maskmode = V8DImode ; break ; default : return false ; } target = d -> target ; op0 = d -> op0 ; for ( int i = 0 ; i < d -> nelt ; ++ i ) vec [ i ] = GEN_INT ( d -> perm [ i ] ) ; mask = gen_rtx_CONST_VECTOR ( maskmode , gen_rtvec_v ( d -> nelt , vec ) ) ; emit_insn ( gen ( target , op0 , force_reg ( maskmode , mask ) ) ) ; return true ; } </s>

Try to expand one-operand permutation with constant mask .


<s> static bool compute_int_layout ( HOST_WIDE_INT bitpos , assign_data_t * data , int * pnregs ) { if ( data -> intoffset < 0 ) return false ; const int intoffset = data -> intoffset ; data -> intoffset = - 1 ; const int this_slotno = data -> slotno + intoffset / BITS_PER_WORD ; const unsigned int startbit = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; const unsigned int endbit = ROUND_UP ( bitpos , BITS_PER_WORD ) ; int nregs = ( endbit - startbit ) / BITS_PER_WORD ; if ( nregs > 0 && nregs > SPARC_INT_ARG_MAX - this_slotno ) { nregs = SPARC_INT_ARG_MAX - this_slotno ; data -> stack = 1 ; } if ( nregs <= 0 ) return false ; * pnregs = nregs ; return true ; } </s>

A subroutine of function_arg_record_value . Compute the number of integer registers to be assigned between PARMS- > intoffset and BITPOS . Return true if at least one integer register is assigned or false otherwise .


<s>
SDValue
TOYTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unimplemented operand"
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

TOY
TOY
"Unimplemented operand"
ISD::GlobalAddress


<s> bool PPCTargetLowering :: SelectAddressRegReg ( SDValue N , SDValue & Base , SDValue & Index , SelectionDAG & DAG ) const { short imm = 0 ; if ( N . getOpcode ( ) == ISD :: ADD ) { if ( isIntS16Immediate ( N . getOperand ( 1 ) , imm ) ) return false ; if ( N . getOperand ( 1 ) . getOpcode ( ) == PPCISD :: Lo ) return false ; Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } else if ( N . getOpcode ( ) == ISD :: OR ) { if ( isIntS16Immediate ( N . getOperand ( 1 ) , imm ) ) return false ; KnownBits LHSKnown , RHSKnown ; DAG . computeKnownBits ( N . getOperand ( 0 ) , LHSKnown ) ; if ( LHSKnown . Zero . getBoolValue ( ) ) { DAG . computeKnownBits ( N . getOperand ( 1 ) , RHSKnown ) ; if ( ~ ( LHSKnown . Zero | RHSKnown . Zero ) == 0 ) { Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } } } return false ; } </s>

SelectAddressRegReg - Given the specified addressed , check to see if it can be more efficiently represented as [ r+imm ] .


<s>
SDValue
RISCVTargetLowering
::
PerformDAGCombine
(
SDNode
*
N
,
DAGCombinerInfo
&
DCI
)
const
{
SelectionDAG
&
DAG
=
DCI
.
DAG
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
break
;
case
ISD
::
SHL
:
case
ISD
::
SRL
:
case
ISD
::
SRA
:
{
assert
(
Subtarget
.
getXLen
(
)
==
64
&&
"Combine should be 64-bit only"
)
;
if
(
!
DCI
.
isBeforeLegalize
(
)
)
break
;
SDValue
RHS
=
N
->
getOperand
(
1
)
;
if
(
N
->
getValueType
(
0
)
!=
MVT
::
i32
||
RHS
->
getOpcode
(
)
==
ISD
::
Constant
||
(
RHS
->
getOpcode
(
)
==
ISD
::
AssertZext
&&
cast
<
VTSDNode
>
(
RHS
->
getOperand
(
1
)
)
->
getVT
(
)
.
getSizeInBits
(
)
<=
5
)
)
break
;
SDValue
LHS
=
N
->
getOperand
(
0
)
;
SDLoc
DL
(
N
)
;
SDValue
NewRHS
=
DAG
.
getNode
(
ISD
::
AssertZext
,
DL
,
RHS
.
getValueType
(
)
,
RHS
,
DAG
.
getValueType
(
EVT
::
getIntegerVT
(
*
DAG
.
getContext
(
)
,
5
)
)
)
;
return
DCI
.
CombineTo
(
N
,
DAG
.
getNode
(
N
->
getOpcode
(
)
,
DL
,
LHS
.
getValueType
(
)
,
LHS
,
NewRHS
)
)
;
}
case
ISD
::
ANY_EXTEND
:
{
SDValue
Src
=
N
->
getOperand
(
0
)
;
if
(
N
->
getValueType
(
0
)
!=
MVT
::
i64
||
Src
.
getValueType
(
)
!=
MVT
::
i32
)
break
;
if
(
!
isVariableShift
(
Src
)
&&
!
(
Subtarget
.
hasStdExtM
(
)
&&
isVariableSDivUDivURem
(
Src
)
)
)
break
;
SDLoc
DL
(
N
)
;
return
DCI
.
CombineTo
(
N
,
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
DL
,
MVT
::
i64
,
Src
)
,
false
)
;
}
case
RISCVISD
::
SplitF64
:
{
SDValue
Op0
=
N
->
getOperand
(
0
)
;
if
(
Op0
->
getOpcode
(
)
!=
RISCVISD
::
BuildPairF64
)
break
;
return
DCI
.
CombineTo
(
N
,
Op0
.
getOperand
(
0
)
,
Op0
.
getOperand
(
1
)
)
;
}
}
return
SDValue
(
)
;
}
</s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s>
bool
ARMAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
;
bool
PendConditionalInstruction
=
false
;
SmallVector
<
NearMissInfo
,
4
>
NearMisses
;
MatchResult
=
MatchInstruction
(
Operands
,
Inst
,
NearMisses
,
MatchingInlineAsm
,
PendConditionalInstruction
,
Out
)
;
switch
(
MatchResult
)
{
case
Match_Success
:
if
(
validateInstruction
(
Inst
,
Operands
)
)
{
forwardITPosition
(
)
;
return
true
;
}
{
bool
wasInITBlock
=
inITBlock
(
)
;
while
(
processInstruction
(
Inst
,
Operands
,
Out
)
)
;
if
(
wasInITBlock
&&
hasV8Ops
(
)
&&
isThumb
(
)
&&
!
isV8EligibleForIT
(
&
Inst
)
)
{
Warning
(
IDLoc
,
"deprecated instruction in IT block"
)
;
}
}
forwardITPosition
(
)
;
if
(
Inst
.
getOpcode
(
)
==
ARM
::
ITasm
)
return
false
;
Inst
.
setLoc
(
IDLoc
)
;
if
(
PendConditionalInstruction
)
{
PendingConditionalInsts
.
push_back
(
Inst
)
;
if
(
isITBlockFull
(
)
||
isITBlockTerminator
(
Inst
)
)
flushPendingInstructions
(
Out
)
;
}
else
{
Out
.
EmitInstruction
(
Inst
,
getSTI
(
)
)
;
}
return
false
;
case
Match_NearMisses
:
ReportNearMisses
(
NearMisses
,
IDLoc
,
Operands
)
;
return
true
;
case
Match_MnemonicFail
:
{
uint64_t
FBS
=
ComputeAvailableFeatures
(
getSTI
(
)
.
getFeatureBits
(
)
)
;
std
::
string
Suggestion
=
ARMMnemonicSpellCheck
(
(
(
ARMOperand
&
)
*
Operands
[
0
]
)
.
getToken
(
)
,
FBS
)
;
return
Error
(
IDLoc
,
"invalid instruction"
+
Suggestion
,
(
(
ARMOperand
&
)
*
Operands
[
0
]
)
.
getLocRange
(
)
)
;
}
}
llvm_unreachable
(
"Implement any new match types added!"
)
;
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .

ARM
ARM
4
"deprecated instruction in IT block"
ARM::ITasm
ARM
ARM
0
"invalid instruction"
ARM
0
"Implement any new match types added!"


<s> const char * mips_msa_output_shift_immediate ( const char * shift , rtx * operands ) { rtx amount = operands [ 2 ] ; machine_mode mode = amount -> mode ; unsigned val = UINTVAL ( CONST_VECTOR_ELT ( amount , 0 ) ) ; val &= GET_MODE_UNIT_BITSIZE ( mode ) - 1 ; if ( ! val ) return "" ; rtx c = gen_int_mode ( val , GET_MODE_INNER ( mode ) ) ; operands [ 2 ] = gen_const_vec_duplicate ( mode , c ) ; return shift ; } </s>

Return the assembly code for MSA immediate shift instructions , which has the operands given by OPERANDS . Truncate the shift amount to make GAS happy .


<s> bool AArch64SIMDInstrOpt :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; const TargetSubtargetInfo & ST = MF . getSubtarget ( ) ; const AArch64InstrInfo * AAII = static_cast < const AArch64InstrInfo * > ( ST . getInstrInfo ( ) ) ; if ( ! AAII ) return false ; SchedModel . init ( & ST ) ; if ( ! SchedModel . hasInstrSchedModel ( ) ) return false ; bool Changed = false ; for ( auto OptimizationKind : { VectorElem , Interleave } ) { if ( ! shouldExitEarly ( & MF , OptimizationKind ) ) { SmallVector < MachineInstr * , 8 > RemoveMIs ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineBasicBlock :: iterator MII = MBB . begin ( ) , MIE = MBB . end ( ) ; MII != MIE ; ) { MachineInstr & MI = * MII ; bool InstRewrite ; if ( OptimizationKind == VectorElem ) InstRewrite = optimizeVectElement ( MI ) ; else InstRewrite = optimizeLdStInterleave ( MI ) ; if ( InstRewrite ) { RemoveMIs . push_back ( & MI ) ; Changed = true ; } ++ MII ; } } for ( MachineInstr * MI : RemoveMIs ) MI -> eraseFromParent ( ) ; } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool ARMFastISel :: fastLowerArguments ( ) { if ( ! FuncInfo . CanLowerReturn ) return false ; const Function * F = FuncInfo . Fn ; if ( F -> isVarArg ( ) ) return false ; CallingConv :: ID CC = F -> getCallingConv ( ) ; switch ( CC ) { default : return false ; case CallingConv :: Fast : case CallingConv :: C : case CallingConv :: ARM_AAPCS_VFP : case CallingConv :: ARM_AAPCS : case CallingConv :: ARM_APCS : break ; } unsigned Idx = 1 ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( Idx > 4 ) return false ; if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) ) return false ; Type * ArgTy = I -> getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( DL , ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : break ; default : return false ; } } static const MCPhysReg GPRArgRegs [ ] = { ARM :: R0 , ARM :: R1 , ARM :: R2 , ARM :: R3 } ; const TargetRegisterClass * RC = & ARM :: rGPRRegClass ; Idx = 0 ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { unsigned SrcReg = GPRArgRegs [ Idx ] ; unsigned DstReg = FuncInfo . MF -> addLiveIn ( SrcReg , RC ) ; unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( DstReg , getKillRegState ( true ) ) ; updateValueMap ( & * I , ResultReg ) ; } return true ; } </s>

This method is called by target-independent code to do target- specific argument lowering .


<s> bool alpha_const_ok_for_letter_p ( HOST_WIDE_INT value , int c ) { switch ( c ) { case 'I' : return ( unsigned HOST_WIDE_INT ) value < 0x100 ; case 'J' : return value == 0 ; case 'K' : return ( unsigned HOST_WIDE_INT ) ( value + 0x8000 ) < 0x10000 ; case 'L' : return ( ( value & 0xffff ) == 0 && ( ( value ) >> 31 == - 1 || value >> 31 == 0 ) ) ; case 'M' : return zap_mask ( value ) ; case 'N' : return ( unsigned HOST_WIDE_INT ) ( ~ value ) < 0x100 ; case 'O' : return ( unsigned HOST_WIDE_INT ) ( - value ) < 0x100 ; case 'P' : return value == 1 || value == 2 || value == 3 ; default : return false ; } } </s>

Implements CONST_OK_FOR_LETTER_P . Return true if the value matches the range defined for C in [ I-P ] .


<s> static bool or1k_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { if ( rclass == FLAG_REGS ) return from == to ; return true ; } </s>

Worker for TARGET_CAN_CHANGE_MODE_CLASS . Returns true if its ok to change a register in class RCLASS from mode FROM to mode TO . In general OpenRISC registers , other than special flags , handle all supported classes .


<s> unsigned AArch64InstrInfo :: getLoadStoreImmIdx ( unsigned Opc ) { switch ( Opc ) { default : return 2 ; case AArch64 :: LDPXi : case AArch64 :: LDPDi : case AArch64 :: STPXi : case AArch64 :: STPDi : case AArch64 :: LDNPXi : case AArch64 :: LDNPDi : case AArch64 :: STNPXi : case AArch64 :: STNPDi : case AArch64 :: LDPQi : case AArch64 :: STPQi : case AArch64 :: LDNPQi : case AArch64 :: STNPQi : case AArch64 :: LDPWi : case AArch64 :: LDPSi : case AArch64 :: STPWi : case AArch64 :: STPSi : case AArch64 :: LDNPWi : case AArch64 :: LDNPSi : case AArch64 :: STNPWi : case AArch64 :: STNPSi : case AArch64 :: LDG : case AArch64 :: STGPi : return 3 ; case AArch64 :: ADDG : case AArch64 :: STGOffset : return 2 ; } } </s>

Returns the index for the immediate for a given instruction .


"IA64 (Itanium) DAG->DAG Instruction Selector"

getPassName - Return a nice clean name for a pass .


<s> static void aarch64_emit_unlikely_jump ( rtx insn ) { int very_unlikely = REG_BR_PROB_BASE / 100 - 1 ; insn = emit_jump_insn ( insn ) ; add_int_reg_note ( insn , REG_BR_PROB , very_unlikely ) ; } </s>

Mark the previous jump instruction as unlikely .


<s> static void rs6000_override_options_after_change ( void ) { if ( ( global_options_set . x_flag_unroll_loops && flag_unroll_loops ) || ( global_options_set . x_flag_unroll_all_loops && flag_unroll_all_loops ) ) { if ( ! global_options_set . x_unroll_only_small_loops ) unroll_only_small_loops = 0 ; if ( ! global_options_set . x_flag_rename_registers ) flag_rename_registers = 1 ; if ( ! global_options_set . x_flag_cunroll_grow_size ) flag_cunroll_grow_size = 1 ; } else if ( ! global_options_set . x_flag_cunroll_grow_size ) flag_cunroll_grow_size = flag_peel_loops || optimize >= 3 ; } </s>

This target function is similar to the hook TARGET_OPTION_OVERRIDE but is called when the optimize level is changed via an attribute or pragma or when it is reset at the end of the code affected by the attribute or pragma . It is not called at the beginning of compilation when TARGET_OPTION_OVERRIDE is called so if you want to perform these actions then , you should have TARGET_OPTION_OVERRIDE call TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE .


<s> void build ( function_builder & b , const function_group_info & group ) const override { b . add_overloaded_functions ( group , MODE_none ) ; build_all ( b , "v0,vu0" , group , MODE_none ) ; } </s>

Build new chain starting from insn INSN_UID recursively adding all dependent uses and definitions . Return true if OK , false if the chain discovery was aborted .


<s> bool hasFP ( const MachineFunction & MF ) const { return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static bool mips_lwxs_address_p ( rtx addr ) { if ( ISA_HAS_LWXS && GET_CODE ( addr ) == PLUS && REG_P ( XEXP ( addr , 1 ) ) ) { rtx offset = XEXP ( addr , 0 ) ; if ( GET_CODE ( offset ) == MULT && REG_P ( XEXP ( offset , 0 ) ) && CONST_INT_P ( XEXP ( offset , 1 ) ) && INTVAL ( XEXP ( offset , 1 ) ) == 4 ) return true ; } return false ; } </s>

Return true if ADDR matches the pattern for the LWXS load scaled indexed address instruction . Note that such addresses are not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense , because their use is so restricted .


<s> static void bfin_gen_bundles ( void ) { basic_block bb ; FOR_EACH_BB_FN ( bb , cfun ) { rtx_insn * insn , * next ; rtx_insn * slot [ 3 ] ; int n_filled = 0 ; slot [ 0 ] = slot [ 1 ] = slot [ 2 ] = NULL ; for ( insn = BB_HEAD ( bb ) ; ; insn = next ) { int at_end ; rtx delete_this = NULL_RTX ; if ( NONDEBUG_INSN_P ( insn ) ) { enum attr_type type = get_attr_type ( insn ) ; if ( type == TYPE_STALL ) { gcc_assert ( n_filled == 0 ) ; delete_this = insn ; } else { if ( type == TYPE_DSP32 || type == TYPE_DSP32SHIFTIMM ) slot [ 0 ] = insn ; else if ( slot [ 1 ] == NULL_RTX ) slot [ 1 ] = insn ; else slot [ 2 ] = insn ; n_filled ++ ; } } next = NEXT_INSN ( insn ) ; while ( next && insn != BB_END ( bb ) && ! ( INSN_P ( next ) && GET_CODE ( PATTERN ( next ) ) != USE && GET_CODE ( PATTERN ( next ) ) != CLOBBER ) ) { insn = next ; next = NEXT_INSN ( insn ) ; } at_end = insn == BB_END ( bb ) ; if ( delete_this == NULL_RTX && ( at_end || GET_MODE ( next ) == TImode ) ) { if ( ( n_filled < 2 || ! gen_one_bundle ( slot ) ) && slot [ 0 ] != NULL_RTX ) { rtx pat = PATTERN ( slot [ 0 ] ) ; if ( GET_CODE ( pat ) == SET && GET_CODE ( SET_SRC ( pat ) ) == UNSPEC && XINT ( SET_SRC ( pat ) , 1 ) == UNSPEC_32BIT ) { SET_SRC ( pat ) = XVECEXP ( SET_SRC ( pat ) , 0 , 0 ) ; INSN_CODE ( slot [ 0 ] ) = - 1 ; df_insn_rescan ( slot [ 0 ] ) ; } } n_filled = 0 ; slot [ 0 ] = slot [ 1 ] = slot [ 2 ] = NULL ; } if ( delete_this != NULL_RTX ) delete_insn ( delete_this ) ; if ( at_end ) break ; } } } </s>

Go through all insns , and use the information generated during scheduling to generate SEQUENCEs to represent bundles of instructions issued simultaneously .


Return an array that contains the direct target flag values and their names .

RISCV RISCV RISCV "riscv-call" "riscv-plt" "riscv-lo" "riscv-hi" "riscv-pcrel-lo" "riscv-pcrel-hi" "riscv-got-hi" "riscv-tprel-lo" "riscv-tprel-hi" "riscv-tprel-add" "riscv-tls-got-hi" "riscv-tls-gd-hi"


"rs6000_can_inline_p:, caller %s, callee %s, %s inline\n"

Hook to determine if one function can safely inline another .


"\nrs6000_rtx_costs, return = %s, mode = %s, outer_code = %s, "

"opno = %d, total = %d, speed = %s, x:\n"

Debug form of r6000_rtx_costs that is selected if -mdebug=cost .


"instruction use requires an option to be enabled"

"immediate must be a multiple of 2 bytes in the range"

"operand must be formed of letters selected in-order from 'iorw'"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> static hsa_status_t get_memory_region ( hsa_region_t region , hsa_region_t * retval , hsa_region_global_flag_t kind ) { hsa_region_segment_t segment ; hsa_fns . hsa_region_get_info_fn ( region , HSA_REGION_INFO_SEGMENT , & segment ) ; if ( HSA_REGION_SEGMENT_GLOBAL != segment ) return HSA_STATUS_SUCCESS ; hsa_region_global_flag_t flags ; hsa_fns . hsa_region_get_info_fn ( region , HSA_REGION_INFO_GLOBAL_FLAGS , & flags ) ; if ( flags & kind ) { * retval = region ; return HSA_STATUS_INFO_BREAK ; } return HSA_STATUS_SUCCESS ; } </s>

Callback of hsa_iterate_regions . Called once for each available memory region , and returns `` break '' when a suitable one has been found .


<s> bool PIC16AsmPrinter :: doFinalization ( Module & M ) { printLibcallDecls ( ) ; EmitRemainingAutos ( ) ; DbgInfo . EndModule ( M ) ; O << "\n\t" << "END\n" ; return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


"argument of %qE attribute is not a string constant"

"argument of %qE attribute is not \"ilink1\" or \"ilink2\""

"argument of %qE attribute is not \"ilink\" or \"firq\""

Handle an `` interrupt '' attribute ; arguments as in struct attribute_spec.handler .


<s> bool enableShrinkWrapping ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target will correctly handle shrink wrapping .


"invalid operand (violates constant bus restrictions)"

"internal error: instruction without _e64 suffix "


<s> int hppa_fpstore_bypass_p ( rtx out_insn , rtx in_insn ) { enum machine_mode store_mode ; enum machine_mode other_mode ; rtx set ; if ( recog_memoized ( in_insn ) < 0 || get_attr_type ( in_insn ) != TYPE_FPSTORE || recog_memoized ( out_insn ) < 0 ) return 0 ; store_mode = GET_MODE ( SET_SRC ( PATTERN ( in_insn ) ) ) ; set = single_set ( out_insn ) ; if ( ! set ) return 0 ; other_mode = GET_MODE ( SET_SRC ( set ) ) ; return ( GET_MODE_SIZE ( store_mode ) == GET_MODE_SIZE ( other_mode ) ) ; } </s>

Return nonzero if there is a bypass for the output of OUT_INSN and the fp store IN_INSN .


<s> bool MBlazeAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( ( Count % 4 ) != 0 ) return false ; for ( uint64_t i = 0 ; i < Count ; i += 4 ) OW -> Write32 ( 0x00000000 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> unsigned PPCFrameLowering :: determineFrameLayout ( const MachineFunction & MF , bool UseEstimate , unsigned * NewMaxCallFrameSize ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = UseEstimate ? MFI . estimateStackSize ( MF ) : MFI . getStackSize ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned MaxAlign = MFI . getMaxAlignment ( ) ; unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - 1 ; const PPCRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; bool DisableRedZone = MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoRedZone ) ; bool CanUseRedZone = ! MFI . hasVarSizedObjects ( ) && ! MFI . adjustsStack ( ) && ! MustSaveLR ( MF , LR ) && ! RegInfo -> hasBasePointer ( MF ) ; bool FitsInRedZone = FrameSize <= Subtarget . getRedZoneSize ( ) ; if ( ! DisableRedZone && CanUseRedZone && FitsInRedZone ) { return 0 ; } unsigned maxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI . hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( NewMaxCallFrameSize ) * NewMaxCallFrameSize = maxCallFrameSize ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; return FrameSize ; } </s>

Determine the frame layout but do not update the machine function .


<s> virtual void emitSparcRegisterScratch ( unsigned reg ) { } </s>

Emit `` .register < reg > , # scratch '' .


<s> static void mips_restore_reg ( rtx reg , rtx mem ) { if ( TARGET_MIPS16 && REGNO ( reg ) == RETURN_ADDR_REGNUM ) reg = gen_rtx_REG ( GET_MODE ( reg ) , GP_REG_FIRST + 7 ) ; else if ( GET_MODE ( reg ) == DFmode && ( ! TARGET_FLOAT64 || mips_abi == ABI_32 ) ) { mips_add_cfa_restore ( mips_subword ( reg , true ) ) ; mips_add_cfa_restore ( mips_subword ( reg , false ) ) ; } else mips_add_cfa_restore ( reg ) ; mips_emit_save_slot_move ( reg , mem , MIPS_EPILOGUE_TEMP ( GET_MODE ( reg ) ) ) ; if ( REGNO ( reg ) == REGNO ( mips_epilogue . cfa_reg ) ) mips_epilogue_set_cfa ( stack_pointer_rtx , mips_epilogue . cfa_restore_sp_offset ) ; } </s>

Emit instructions to restore register REG from slot MEM .


<s>
X86TTI
::
PopcntSupportKind
X86TTI
::
getPopcntSupport
(
unsigned
TyWidth
)
const
{
assert
(
isPowerOf2_32
(
TyWidth
)
&&
"Ty width must be power of 2"
)
;
return
ST
->
hasPOPCNT
(
)
PSK_FastHardware
:
PSK_Software
;
}
</s>

Return hardware support for population count .


<s> void OR1KFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const OR1KRegisterInfo * TRI = static_cast < const OR1KRegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; bool IsPIC = MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; int Offset = - 4 ; if ( MFI -> adjustsStack ( ) || IsPIC ) { MFI -> CreateFixedObject ( 4 , Offset , true ) ; SavedRegs . set ( OR1K :: R9 ) ; Offset -= 4 ; } if ( hasFP ( MF ) ) { MFI -> CreateFixedObject ( 4 , Offset , true ) ; Offset -= 4 ; } if ( TRI -> hasBasePointer ( MF ) ) { MFI -> CreateFixedObject ( 4 , Offset , true ) ; SavedRegs . set ( TRI -> getBaseRegister ( ) ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


"Constant Island pass failed to converge!"

"Branch Fix Up pass failed to converge!"

runOnMachineFunction - Emit the function body .


<s> static bool rs6000_const_not_ok_for_debug_p ( rtx x ) { if ( GET_CODE ( x ) == UNSPEC ) return true ; if ( GET_CODE ( x ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) ) { rtx c = get_pool_constant ( x ) ; machine_mode cmode = get_pool_mode ( x ) ; if ( ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( c , cmode ) ) return true ; } return false ; } </s>

Return true if X should n't be emitted into the debug info . The linker does n't like .toc section references from .debug_ * sections , so reject .toc section symbols .


<s> bool X86TargetMachine :: addInstSelector ( PassManagerBase & PM ) { PM . add ( createX86ISelDag ( * this , getOptLevel ( ) ) ) ; if ( ! Subtarget . is64Bit ( ) ) PM . add ( createGlobalBaseRegPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool LanaiRegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s>
unsigned
XtensaInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
llvm_unreachable
(
"Unimplemented operand"
)
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s> bool MipsSETargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , bool * Fast ) const { MVT :: SimpleValueType SVT = VT . getSimpleVT ( ) . SimpleTy ; if ( Subtarget . systemSupportsUnalignedAccess ( ) ) { if ( Fast ) * Fast = true ; return true ; } switch ( SVT ) { case MVT :: i64 : case MVT :: i32 : if ( Fast ) * Fast = true ; return true ; default : return false ; } } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> MVT RISCVTargetLowering :: getVPExplicitVectorLengthTy ( ) const { return Subtarget . getXLenVT ( ) ; } </s>

Returns the type to be used for the EVL/AVL operand of VP nodes : ISD : :VP_ADD , ISD : :VP_SUB , etc .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const { return false ; } </s>

Check whether the given instruction may need relaxation .


<s>
unsigned
AArch64MCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
)
const
{
if
(
MO
.
isReg
(
)
)
{
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
}
else
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
llvm_unreachable
(
"Unable to encode MCOperand!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> const TargetRegisterClass * SIRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { if ( MF . getSubtarget < GCNSubtarget > ( ) . hasMAIInsts ( ) && ( isVGPRClass ( RC ) || isAGPRClass ( RC ) ) ) { if ( RC == & AMDGPU :: VGPR_32RegClass || RC == & AMDGPU :: AGPR_32RegClass ) return & AMDGPU :: AV_32RegClass ; if ( RC == & AMDGPU :: VReg_64RegClass || RC == & AMDGPU :: AReg_64RegClass ) return & AMDGPU :: AV_64RegClass ; if ( RC == & AMDGPU :: VReg_64_Align2RegClass || RC == & AMDGPU :: AReg_64_Align2RegClass ) return & AMDGPU :: AV_64_Align2RegClass ; if ( RC == & AMDGPU :: VReg_96RegClass || RC == & AMDGPU :: AReg_96RegClass ) return & AMDGPU :: AV_96RegClass ; if ( RC == & AMDGPU :: VReg_96_Align2RegClass || RC == & AMDGPU :: AReg_96_Align2RegClass ) return & AMDGPU :: AV_96_Align2RegClass ; if ( RC == & AMDGPU :: VReg_128RegClass || RC == & AMDGPU :: AReg_128RegClass ) return & AMDGPU :: AV_128RegClass ; if ( RC == & AMDGPU :: VReg_128_Align2RegClass || RC == & AMDGPU :: AReg_128_Align2RegClass ) return & AMDGPU :: AV_128_Align2RegClass ; if ( RC == & AMDGPU :: VReg_160RegClass || RC == & AMDGPU :: AReg_160RegClass ) return & AMDGPU :: AV_160RegClass ; if ( RC == & AMDGPU :: VReg_160_Align2RegClass || RC == & AMDGPU :: AReg_160_Align2RegClass ) return & AMDGPU :: AV_160_Align2RegClass ; if ( RC == & AMDGPU :: VReg_192RegClass || RC == & AMDGPU :: AReg_192RegClass ) return & AMDGPU :: AV_192RegClass ; if ( RC == & AMDGPU :: VReg_192_Align2RegClass || RC == & AMDGPU :: AReg_192_Align2RegClass ) return & AMDGPU :: AV_192_Align2RegClass ; if ( RC == & AMDGPU :: VReg_256RegClass || RC == & AMDGPU :: AReg_256RegClass ) return & AMDGPU :: AV_256RegClass ; if ( RC == & AMDGPU :: VReg_256_Align2RegClass || RC == & AMDGPU :: AReg_256_Align2RegClass ) return & AMDGPU :: AV_256_Align2RegClass ; if ( RC == & AMDGPU :: VReg_512RegClass || RC == & AMDGPU :: AReg_512RegClass ) return & AMDGPU :: AV_512RegClass ; if ( RC == & AMDGPU :: VReg_512_Align2RegClass || RC == & AMDGPU :: AReg_512_Align2RegClass ) return & AMDGPU :: AV_512_Align2RegClass ; if ( RC == & AMDGPU :: VReg_1024RegClass || RC == & AMDGPU :: AReg_1024RegClass ) return & AMDGPU :: AV_1024RegClass ; if ( RC == & AMDGPU :: VReg_1024_Align2RegClass || RC == & AMDGPU :: AReg_1024_Align2RegClass ) return & AMDGPU :: AV_1024_Align2RegClass ; } return TargetRegisterInfo :: getLargestLegalSuperClass ( RC , MF ) ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .


<s> bool PPCFrameLowering :: canUseAsEpilogue ( const MachineBasicBlock & MBB ) const { MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ; return findScratchRegister ( TmpMBB , true , nullptr ) ; } </s>

Check whether or not the given MBB can be used as a epilogue for the target .


"All regions recorded, starting actual scheduling.\n"

"Retrying function scheduling with lowest recorded occupancy "

After the schedule has been formed , call this function to combine the instructions from the different stages/cycles .


<s> bool Mips16RegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { DebugLoc DL ; const TargetInstrInfo & TII = * MBB . getParent ( ) -> getTarget ( ) . getInstrInfo ( ) ; TII . copyPhysReg ( MBB , I , DL , Mips :: T0 , Reg , true ) ; TII . copyPhysReg ( MBB , UseMI , DL , Reg , Mips :: T0 , true ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .


<s> bool SNESFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return hasFP ( MF ) && ! MFI . hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> static int rs6000_hard_regno_mode_ok ( int regno , machine_mode mode ) { int last_regno = regno + rs6000_hard_regno_nregs [ mode ] [ regno ] - 1 ; if ( mode == PTImode ) return ( IN_RANGE ( regno , FIRST_GPR_REGNO , LAST_GPR_REGNO ) && IN_RANGE ( last_regno , FIRST_GPR_REGNO , LAST_GPR_REGNO ) && ( ( regno & 1 ) == 0 ) ) ; if ( TARGET_VSX && VSX_REGNO_P ( regno ) && ( VECTOR_MEM_VSX_P ( mode ) || reg_addr [ mode ] . scalar_in_vmx_p || ( TARGET_VSX_TIMODE && mode == TImode ) || ( TARGET_VADDUQM && mode == V1TImode ) ) ) { if ( FP_REGNO_P ( regno ) ) return FP_REGNO_P ( last_regno ) ; if ( ALTIVEC_REGNO_P ( regno ) ) { if ( GET_MODE_SIZE ( mode ) != 16 && ! reg_addr [ mode ] . scalar_in_vmx_p ) return 0 ; return ALTIVEC_REGNO_P ( last_regno ) ; } } if ( INT_REGNO_P ( regno ) ) return INT_REGNO_P ( last_regno ) ; if ( FP_REGNO_P ( regno ) ) { if ( SCALAR_FLOAT_MODE_P ( mode ) && ( mode != TDmode || ( regno % 2 ) == 0 ) && FP_REGNO_P ( last_regno ) ) return 1 ; if ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) == UNITS_PER_FP_WORD ) return 1 ; if ( PAIRED_SIMD_REGNO_P ( regno ) && TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE ( mode ) ) return 1 ; return 0 ; } if ( CR_REGNO_P ( regno ) ) return GET_MODE_CLASS ( mode ) == MODE_CC ; if ( CA_REGNO_P ( regno ) ) return mode == Pmode || mode == SImode ; if ( ALTIVEC_REGNO_P ( regno ) ) return ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) || mode == V1TImode ) ; if ( SPE_SIMD_REGNO_P ( regno ) && TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) return 1 ; return GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD ; } </s>

Value is 1 if hard register REGNO can hold a value of machine-mode MODE .


<s> bool PPCAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'c' : printOperand ( MI , OpNo ) ; return false ; case 'L' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + 1 == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + 1 ) . isReg ( ) ) return true ; ++ OpNo ; break ; case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << "i" ; return false ; } } printOperand ( MI , OpNo ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> bool X86Subtarget :: enableEarlyIfConversion ( ) const { return canUseCMOV ( ) && X86EarlyIfConv ; } </s>

Enable the use of the early if conversion pass .


<s>
bool
R600AsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MF
.
ensureLogAlignment
(
8
)
;
SetupMachineFunction
(
MF
)
;
MCContext
&
Context
=
getObjFileLowering
(
)
.
getContext
(
)
;
MCSectionELF
*
ConfigSection
=
Context
.
getELFSection
(
".AMDGPU.config"
,
ELF
::
SHT_PROGBITS
,
0
)
;
OutStreamer
->
SwitchSection
(
ConfigSection
)
;
EmitProgramInfoR600
(
MF
)
;
EmitFunctionBody
(
)
;
if
(
isVerbose
(
)
)
{
MCSectionELF
*
CommentSection
=
Context
.
getELFSection
(
".AMDGPU.csdata"
,
ELF
::
SHT_PROGBITS
,
0
)
;
OutStreamer
->
SwitchSection
(
CommentSection
)
;
R600MachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
R600MachineFunctionInfo
>
(
)
;
OutStreamer
->
emitRawComment
(
Twine
(
"SQ_PGM_RESOURCES:STACK_SIZE = "
+
Twine
(
MFI
->
CFStackSize
)
)
)
;
}
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < TargetData > ( ) ; AU . addPreserved < MachineFunctionAnalysis > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
unsigned
HexagonInstrInfo
::
getSize
(
const
MachineInstr
&
MI
)
const
{
if
(
MI
.
isDebugValue
(
)
||
MI
.
isPosition
(
)
)
return
0
;
unsigned
Size
=
MI
.
getDesc
(
)
.
getSize
(
)
;
if
(
!
Size
)
Size
=
HEXAGON_INSTR_SIZE
;
if
(
isConstExtended
(
MI
)
||
isExtended
(
MI
)
)
Size
+=
HEXAGON_INSTR_SIZE
;
if
(
BranchRelaxAsmLarge
&&
MI
.
getOpcode
(
)
==
Hexagon
::
INLINEASM
)
{
const
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
const
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
const
MCAsmInfo
*
MAI
=
MF
->
getTarget
(
)
.
getMCAsmInfo
(
)
;
unsigned
NumDefs
=
0
;
for
(
;
MI
.
getOperand
(
NumDefs
)
.
isReg
(
)
&&
MI
.
getOperand
(
NumDefs
)
.
isDef
(
)
;
++
NumDefs
)
assert
(
NumDefs
!=
MI
.
getNumOperands
(
)
2
&&
"No asm string?"
)
;
assert
(
MI
.
getOperand
(
NumDefs
)
.
isSymbol
(
)
&&
"No asm string?"
)
;
const
char
*
AsmStr
=
MI
.
getOperand
(
NumDefs
)
.
getSymbolName
(
)
;
Size
=
getInlineAsmLength
(
AsmStr
,
*
MAI
)
;
}
return
Size
;
}
</s>

Return the number of bytes in the encoding of this instruction , or zero if the encoding size can not be known from the opcode .


<s> const MCExpr * AArch64TargetStreamer :: addConstantPoolEntry ( const MCExpr * Expr , unsigned Size , SMLoc Loc ) { return ConstantPools -> addEntry ( Streamer , Expr , Size , Loc ) ; } </s>

Add a new entry to the constant pool for the current section and return an MCExpr that can be used to refer to the constant pool location .


<s>
void
MipsInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
O
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
)
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
Mips
::
RDHWR
:
case
Mips
::
RDHWR64
:
O
<<
"\t.set\tpush\n"
;
O
<<
"\t.set\tmips32r2\n"
;
break
;
case
Mips
::
Save16
:
O
<<
"\tsave\t"
;
printSaveRestore
(
MI
,
O
)
;
O
<<
" # 16 bit inst\n"
;
return
;
case
Mips
::
SaveX16
:
O
<<
"\tsave\t"
;
printSaveRestore
(
MI
,
O
)
;
O
<<
"\n"
;
return
;
case
Mips
::
Restore16
:
O
<<
"\trestore\t"
;
printSaveRestore
(
MI
,
O
)
;
O
<<
" # 16 bit inst\n"
;
return
;
case
Mips
::
RestoreX16
:
O
<<
"\trestore\t"
;
printSaveRestore
(
MI
,
O
)
;
O
<<
"\n"
;
return
;
}
if
(
!
printAliasInstr
(
MI
,
O
)
&&
!
printAlias
(
*
MI
,
O
)
)
printInstruction
(
MI
,
O
)
;
printAnnotation
(
O
,
Annot
)
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
Mips
::
RDHWR
:
case
Mips
::
RDHWR64
:
O
<<
"\n\t.set\tpop"
;
}
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s>
unsigned
getReg
(
)
const
{
assert
(
isRegBase
(
)
&&
"Invalid base register access!"
)
;
return
Base
.
Reg
;
}
</s>

Returns the register associated with this edge .


<s> bool SystemZMCAsmInfoGOFF :: isAcceptableChar ( char C ) const { return MCAsmInfo :: isAcceptableChar ( C ) || C == '#' ; } </s>

Return true if C is an acceptable character inside a symbol name .


<s> bool M88kMCAsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { return Fixup . getKind ( ) == M88k :: FK_88K_DISP16 || Fixup . getKind ( ) == M88k :: FK_88K_DISP26 ; } </s>

Hook to check if a relocation is needed for some target specific reason .


"argument %d of %qE must be an integer constant"

Report that LOCATION has a call to FNDECL in which argument ARGNO was not an integer constant expression . ARGNO counts from zero .


<s> const TargetRegisterInfo * getRegisterInfo ( ) const { return & Subtarget . getInstrInfo ( ) -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool DLXAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] ) return true ; switch ( ExtraCode [ 0 ] ) { case 'H' : { if ( OpNo == 0 ) return true ; const MachineOperand & FlagsOP = MI -> getOperand ( OpNo - 1 ) ; if ( ! FlagsOP . isImm ( ) ) return true ; unsigned Flags = FlagsOP . getImm ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; if ( NumVals != 2 ) return true ; unsigned RegOp = OpNo + 1 ; if ( RegOp >= MI -> getNumOperands ( ) ) return true ; const MachineOperand & MO = MI -> getOperand ( RegOp ) ; if ( ! MO . isReg ( ) ) return true ; unsigned Reg = MO . getReg ( ) ; O << DLXInstPrinter :: getRegisterName ( Reg ) ; return false ; } default : return true ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>


<s> void mt_expand_epilogue ( enum epilogue_type eh_mode ) { rtx size_rtx , insn ; unsigned frame_size ; mt_compute_frame_size ( get_frame_size ( ) ) ; if ( TARGET_DEBUG_STACK ) mt_debug_stack ( & current_frame_info ) ; frame_size = current_frame_info . total_size ; if ( CONST_OK_FOR_LETTER_P ( frame_size , 'O' ) ) size_rtx = GEN_INT ( frame_size ) ; else { gcc_assert ( ! interrupt_handler ) ; size_rtx = gen_rtx_REG ( SImode , GPR_R9 ) ; insn = emit_move_insn ( size_rtx , GEN_INT ( frame_size & 0xffff0000 ) ) ; insn = emit_insn ( gen_iorsi3 ( size_rtx , size_rtx , GEN_INT ( frame_size & 0x0000ffff ) ) ) ; emit_insn ( gen_addsi3 ( size_rtx , size_rtx , stack_pointer_rtx ) ) ; } if ( frame_pointer_needed ) insn = emit_move_insn ( stack_pointer_rtx , frame_pointer_rtx ) ; mt_emit_save_fp ( FROM_MEM_TO_PROCESSOR , current_frame_info ) ; mt_emit_save_regs ( FROM_MEM_TO_PROCESSOR , current_frame_info ) ; if ( frame_size ) { if ( CONST_OK_FOR_LETTER_P ( frame_size , 'O' ) ) insn = emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , size_rtx ) ) ; else insn = emit_move_insn ( stack_pointer_rtx , gen_rtx_REG ( SImode , GPR_R9 ) ) ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , stack_pointer_rtx , gen_rtx_PLUS ( SImode , stack_pointer_rtx , GEN_INT ( frame_size ) ) ) , REG_NOTES ( insn ) ) ; } if ( cfun -> machine && cfun -> machine -> eh_stack_adjust != NULL_RTX ) emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , cfun -> machine -> eh_stack_adjust ) ) ; if ( eh_mode == EH_EPILOGUE ) { emit_jump_insn ( gen_eh_return_internal ( ) ) ; emit_barrier ( ) ; } else if ( interrupt_handler ) emit_jump_insn ( gen_return_interrupt_internal ( ) ) ; else emit_jump_insn ( gen_return_internal ( ) ) ; interrupt_handler = 0 ; current_frame_info = zero_frame_info ; if ( cfun -> machine ) cfun -> machine -> eh_stack_adjust = NULL_RTX ; } </s>

Generate epilogue . EH_MODE is NORMAL_EPILOGUE when generating a function epilogue , or EH_EPILOGUE when generating an EH epilogue .


<s> static void arc_pre_atomic_barrier ( enum memmodel model ) { if ( need_atomic_barrier_p ( model , true ) ) emit_insn ( gen_memory_barrier ( ) ) ; } </s>

Emit a ( pre ) memory barrier around an atomic sequence according to MODEL .


<s> unsigned ARMTTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned Bits = Ty -> getPrimitiveSizeInBits ( ) ; if ( Bits == 0 || Bits > 32 ) return 4 ; int32_t SImmVal = Imm . getSExtValue ( ) ; uint32_t ZImmVal = Imm . getZExtValue ( ) ; if ( ! ST -> isThumb ( ) ) { if ( ( SImmVal >= 0 && SImmVal < 65536 ) || ( ARM_AM :: getSOImmVal ( ZImmVal ) != - 1 ) || ( ARM_AM :: getSOImmVal ( ~ ZImmVal ) != - 1 ) ) return 1 ; return ST -> hasV6T2Ops ( ) ? 2 : 3 ; } if ( ST -> isThumb2 ( ) ) { if ( ( SImmVal >= 0 && SImmVal < 65536 ) || ( ARM_AM :: getT2SOImmVal ( ZImmVal ) != - 1 ) || ( ARM_AM :: getT2SOImmVal ( ~ ZImmVal ) != - 1 ) ) return 1 ; return ST -> hasV6T2Ops ( ) ? 2 : 3 ; } if ( SImmVal >= 0 && SImmVal < 256 ) return 1 ; if ( ( ~ ZImmVal < 256 ) || ARM_AM :: isThumbImmShiftedVal ( ZImmVal ) ) return 2 ; return 3 ; } </s>

Calculate the cost of materializing a 64-bit value .


"There are no defined alternate asm variants"

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> const uint32_t * Z80RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID id ) const { return CC_Save_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void MMIXInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>


<s> static int mips_fp_div_cost ( machine_mode mode ) { return mode == DFmode ? mips_cost -> fp_div_df : mips_cost -> fp_div_sf ; } </s>

Return the cost of floating-point divisions of mode MODE .


<s>
static
void
csky_output_mi_thunk
(
FILE
*
file
,
tree
thunk
ATTRIBUTE_UNUSED
,
HOST_WIDE_INT
delta
,
HOST_WIDE_INT
vcall_offset
,
tree
function
)
{
const
char
*
thiz
=
"a0"
;
const
char
*
reg0
=
"t0"
;
const
char
*
reg1
=
"t1"
;
int
maxoff
=
4096
;
final_start_function
(
emit_barrier
(
)
,
file
,
1
)
;
rtx
fnaddr
=
XEXP
(
DECL_RTL
(
function
)
,
0
)
;
if
(
CSKY_TARGET_ARCH
(
CK801
)
)
{
reg0
=
"l0"
;
reg1
=
"l1"
;
maxoff
=
256
;
if
(
vcall_offset
>
maxoff
||
vcall_offset
<
maxoff
)
fprintf
(
file
,
"\tpush\tl0, l1\n"
)
;
else
if
(
delta
>
maxoff
||
delta
<
maxoff
)
fprintf
(
file
,
"\tpush\tl0\n"
)
;
}
if
(
aggregate_value_p
(
TREE_TYPE
(
TREE_TYPE
(
function
)
)
,
function
)
)
thiz
=
"a1"
;
if
(
delta
!=
0
)
{
if
(
delta
>
maxoff
||
delta
<
maxoff
)
{
fprintf
(
file
,
"\tlrw\t%s, %ld\n"
,
reg0
,
(
long
)
delta
)
;
fprintf
(
file
,
"\taddu\t%s, %s, %s\n"
,
thiz
,
thiz
,
reg0
)
;
}
else
fprintf
(
file
,
"\t%s\t%s, %s, %ld\n"
,
(
delta
>
0
"addi"
:
"subi"
)
,
thiz
,
thiz
,
(
long
)
(
delta
>
0
delta
:
delta
)
)
;
}
if
(
vcall_offset
!=
0
)
{
fprintf
(
file
,
"\tld.w\t%s, (%s, 0)\n"
,
reg0
,
thiz
)
;
if
(
vcall_offset
>
maxoff
||
vcall_offset
<
maxoff
)
{
fprintf
(
file
,
"\tlrw\t%s, %ld\n"
,
reg1
,
(
long
)
vcall_offset
)
;
fprintf
(
file
,
"\taddu\t%s, %s, %s\n"
,
reg0
,
reg0
,
reg1
)
;
}
else
fprintf
(
file
,
"\t%s\t%s, %s, %ld\n"
,
(
vcall_offset
>
0
"addi"
:
"subi"
)
,
reg0
,
reg0
,
(
long
)
(
vcall_offset
>
0
vcall_offset
:
vcall_offset
)
)
;
fprintf
(
file
,
"\tld.w\t%s, (%s, 0)\n"
,
reg0
,
reg0
)
;
fprintf
(
file
,
"\taddu\t%s, %s, %s\n"
,
thiz
,
thiz
,
reg0
)
;
}
if
(
CSKY_TARGET_ARCH
(
CK801
)
)
{
if
(
vcall_offset
>
maxoff
||
vcall_offset
<
maxoff
)
{
fprintf
(
file
,
"\tld.w\tl0, (sp, 0)\n"
)
;
fprintf
(
file
,
"\tld.w\tl1, (sp, 4)\n"
)
;
fprintf
(
file
,
"\taddi\t sp, sp, 8\n"
)
;
}
else
if
(
delta
>
maxoff
||
delta
<
maxoff
)
{
fprintf
(
file
,
"\tld.w\tl0, (sp, 0)\n"
)
;
fprintf
(
file
,
"\taddi\tsp, sp, 4\n"
)
;
}
}
fprintf
(
file
,
"\tjbr\t"
)
;
output_addr_const
(
file
,
fnaddr
)
;
fprintf
(
file
,
"\n"
)
;
final_end_function
(
)
;
}
</s>

Implement TARGET_ASM_OUTPUT_MI_THUNK . Output code to add DELTA to the first argument , and then jump to FUNCTION . Used for C++ multiple inheritance .


<s> static bool rs6000_return_in_msb ( const_tree valtype ) { return ( DEFAULT_ABI == ABI_ELFv2 && BYTES_BIG_ENDIAN && AGGREGATE_TYPE_P ( valtype ) && ( rs6000_function_arg_padding ( TYPE_MODE ( valtype ) , valtype ) == PAD_UPWARD ) ) ; } </s>

Specify whether values returned in registers should be at the most significant end of a register . We want aggregates returned by value to match the way aggregates are passed to functions .


"%qs attribute only applies to functions"

"%qs appears to be a misspelled interrupt handler"

"%qs appears to be a misspelled signal handler"

Handle an attribute requiring a FUNCTION_DECL ; arguments as in struct attribute_spec.handler .


<s> std :: unique_ptr < SICacheControl > SICacheControl :: create ( const GCNSubtarget & ST ) { GCNSubtarget :: Generation Generation = ST . getGeneration ( ) ; if ( Generation <= AMDGPUSubtarget :: SOUTHERN_ISLANDS ) return std :: make_unique < SIGfx6CacheControl > ( ST ) ; if ( Generation < AMDGPUSubtarget :: GFX10 ) return std :: make_unique < SIGfx7CacheControl > ( ST ) ; return std :: make_unique < SIGfx10CacheControl > ( ST ) ; } </s>


<s>
bool
ARMBaseInstrInfo
::
analyzeSelect
(
const
MachineInstr
&
MI
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
unsigned
&
TrueOp
,
unsigned
&
FalseOp
,
bool
&
Optimizable
)
const
{
assert
(
(
MI
.
getOpcode
(
)
==
ARM
::
MOVCCr
||
MI
.
getOpcode
(
)
==
ARM
::
t2MOVCCr
)
&&
"Unknown select instruction"
)
;
TrueOp
=
1
;
FalseOp
=
2
;
Cond
.
push_back
(
MI
.
getOperand
(
3
)
)
;
Cond
.
push_back
(
MI
.
getOperand
(
4
)
)
;
Optimizable
=
true
;
return
false
;
}
</s>

Analyze the given select instruction , returning true if it can not be understood .


<s> bool ARMBaseInstrInfo :: isAddImmediate ( const MachineInstr & MI , const MachineOperand * & Destination , const MachineOperand * & Source , int64_t & Offset ) const { int Sign = 1 ; unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == ARM :: SUBri ) Sign = - 1 ; else if ( Opcode != ARM :: ADDri ) return false ; if ( ! MI . getOperand ( 0 ) . isReg ( ) || ! MI . getOperand ( 1 ) . isReg ( ) || ! MI . getOperand ( 2 ) . isImm ( ) ) return false ; Destination = & MI . getOperand ( 0 ) ; Source = & MI . getOperand ( 1 ) ; Offset = MI . getOperand ( 2 ) . getImm ( ) * Sign ; return true ; } </s>

If the specific machine instruction is an instruction that adds an immediate value and a register , and stores the result in the given register Reg , return a pair of the source register and the offset which has been added .


<s> bool SparcPassConfig :: addInstSelector ( ) { PM -> add ( createSparcISelDag ( getSparcTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void AArch64PassConfig :: addPreLegalizeMachineIR ( ) { if ( getOptLevel ( ) == CodeGenOpt :: None ) addPass ( createAArch64O0PreLegalizerCombiner ( ) ) ; else addPass ( createAArch64PreLegalizerCombiner ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before legalization .


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> static void bfin_gen_bundles ( void ) { basic_block bb ; FOR_EACH_BB_FN ( bb , cfun ) { rtx_insn * insn , * next ; rtx_insn * slot [ 3 ] ; int n_filled = 0 ; slot [ 0 ] = slot [ 1 ] = slot [ 2 ] = NULL ; for ( insn = BB_HEAD ( bb ) ; ; insn = next ) { int at_end ; rtx_insn * delete_this = NULL ; if ( NONDEBUG_INSN_P ( insn ) ) { enum attr_type type = get_attr_type ( insn ) ; if ( type == TYPE_STALL ) { gcc_assert ( n_filled == 0 ) ; delete_this = insn ; } else { if ( type == TYPE_DSP32 || type == TYPE_DSP32SHIFTIMM ) slot [ 0 ] = insn ; else if ( slot [ 1 ] == NULL_RTX ) slot [ 1 ] = insn ; else slot [ 2 ] = insn ; n_filled ++ ; } } next = NEXT_INSN ( insn ) ; while ( next && insn != BB_END ( bb ) && ! ( INSN_P ( next ) && GET_CODE ( PATTERN ( next ) ) != USE && GET_CODE ( PATTERN ( next ) ) != CLOBBER ) ) { insn = next ; next = NEXT_INSN ( insn ) ; } at_end = insn == BB_END ( bb ) ; if ( delete_this == NULL_RTX && ( at_end || GET_MODE ( next ) == TImode ) ) { if ( ( n_filled < 2 || ! gen_one_bundle ( slot ) ) && slot [ 0 ] != NULL_RTX ) { rtx pat = PATTERN ( slot [ 0 ] ) ; if ( GET_CODE ( pat ) == SET && GET_CODE ( SET_SRC ( pat ) ) == UNSPEC && XINT ( SET_SRC ( pat ) , 1 ) == UNSPEC_32BIT ) { SET_SRC ( pat ) = XVECEXP ( SET_SRC ( pat ) , 0 , 0 ) ; INSN_CODE ( slot [ 0 ] ) = - 1 ; df_insn_rescan ( slot [ 0 ] ) ; } } n_filled = 0 ; slot [ 0 ] = slot [ 1 ] = slot [ 2 ] = NULL ; } if ( delete_this != NULL_RTX ) delete_insn ( delete_this ) ; if ( at_end ) break ; } } } </s>

Go through all insns , and use the information generated during scheduling to generate SEQUENCEs to represent bundles of instructions issued simultaneously .


<s> TargetPassConfig * Nios2TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new Nios2PassConfig ( * this , & PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> virtual const TargetRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
AArch64
::
NumTargetFixupKinds
]
=
{
{
"fixup_aarch64_pcrel_adr_imm21"
,
0
,
32
,
PCRelFlagVal
}
,
{
"fixup_aarch64_pcrel_adrp_imm21"
,
0
,
32
,
PCRelFlagVal
}
,
{
"fixup_aarch64_add_imm12"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldst_imm12_scale1"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldst_imm12_scale2"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldst_imm12_scale4"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldst_imm12_scale8"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldst_imm12_scale16"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldr_pcrel_imm19"
,
5
,
19
,
PCRelFlagVal
}
,
{
"fixup_aarch64_movw"
,
5
,
16
,
0
}
,
{
"fixup_aarch64_pcrel_branch14"
,
5
,
14
,
PCRelFlagVal
}
,
{
"fixup_aarch64_pcrel_branch19"
,
5
,
19
,
PCRelFlagVal
}
,
{
"fixup_aarch64_pcrel_branch26"
,
0
,
26
,
PCRelFlagVal
}
,
{
"fixup_aarch64_pcrel_call26"
,
0
,
26
,
PCRelFlagVal
}
,
{
"fixup_aarch64_tlsdesc_call"
,
0
,
0
,
0
}
}
;
if
(
Kind
>=
FirstLiteralRelocationKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
FK_NONE
)
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> std :: pair < SDValue , SDValue > SystemZSelectionDAGInfo :: EmitTargetCodeForMemchr ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Src , SDValue Char , SDValue Length , MachinePointerInfo SrcPtrInfo ) const { EVT PtrVT = Src . getValueType ( ) ; SDVTList VTs = DAG . getVTList ( PtrVT , MVT :: i32 , MVT :: Other ) ; Length = DAG . getZExtOrTrunc ( Length , DL , PtrVT ) ; Char = DAG . getZExtOrTrunc ( Char , DL , MVT :: i32 ) ; Char = DAG . getNode ( ISD :: AND , DL , MVT :: i32 , Char , DAG . getConstant ( 255 , DL , MVT :: i32 ) ) ; SDValue Limit = DAG . getNode ( ISD :: ADD , DL , PtrVT , Src , Length ) ; SDValue End = DAG . getNode ( SystemZISD :: SEARCH_STRING , DL , VTs , Chain , Limit , Src , Char ) ; SDValue CCReg = End . getValue ( 1 ) ; Chain = End . getValue ( 2 ) ; SDValue Ops [ ] = { End , DAG . getConstant ( 0 , DL , PtrVT ) , DAG . getTargetConstant ( SystemZ :: CCMASK_SRST , DL , MVT :: i32 ) , DAG . getTargetConstant ( SystemZ :: CCMASK_SRST_FOUND , DL , MVT :: i32 ) , CCReg } ; End = DAG . getNode ( SystemZISD :: SELECT_CCMASK , DL , PtrVT , Ops ) ; return std :: make_pair ( End , Chain ) ; } </s>

Emit target-specific code that performs a memchr , in cases where that is faster than a libcall .


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
READ_REGISTER
:
ExpandREAD_REGISTER
(
N
,
Results
,
DAG
)
;
break
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SREM
:
case
ISD
::
UREM
:
Res
=
LowerREM
(
N
,
DAG
)
;
break
;
case
ISD
::
SDIVREM
:
case
ISD
::
UDIVREM
:
Res
=
LowerDivRem
(
SDValue
(
N
,
0
)
,
DAG
)
;
assert
(
Res
.
getNumOperands
(
)
==
2
&&
"DivRem needs two values"
)
;
Results
.
push_back
(
Res
.
getValue
(
0
)
)
;
Results
.
push_back
(
Res
.
getValue
(
1
)
)
;
return
;
case
ISD
::
READCYCLECOUNTER
:
ReplaceREADCYCLECOUNTER
(
N
,
Results
,
DAG
,
Subtarget
)
;
return
;
case
ISD
::
UDIV
:
case
ISD
::
SDIV
:
assert
(
Subtarget
->
isTargetWindows
(
)
&&
"can only expand DIV on Windows"
)
;
return
ExpandDIV_Windows
(
SDValue
(
N
,
0
)
,
DAG
,
N
->
getOpcode
(
)
==
ISD
::
SDIV
,
Results
)
;
case
ISD
::
ATOMIC_CMP_SWAP
:
ReplaceCMP_SWAP_64Results
(
N
,
Results
,
DAG
)
;
return
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
ReplaceLongIntrinsic
(
N
,
Results
,
DAG
)
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

ARM
ARM
"Don't know how to custom expand this!"
ISD::READ_REGISTER
ISD::BITCAST
ISD::SRL
ISD::SRA
ISD::SREM
ISD::UREM
ISD::SDIVREM
ISD::UDIVREM
0
2
"DivRem needs two values"
0
1
ISD::READCYCLECOUNTER
ISD::UDIV
ISD::SDIV
"can only expand DIV on Windows"
0
ISD::SDIV
ISD::ATOMIC_CMP_SWAP
ISD::INTRINSIC_WO_CHAIN


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & getSubtargetImpl ( ) -> getInstrItineraryData ( ) ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> bool Error ( SMLoc L , const Twine & Msg , ArrayRef < SMRange > Ranges = None , bool MatchingInlineAsm = false ) { MCAsmParser & Parser = getParser ( ) ; if ( MatchingInlineAsm ) return true ; return Parser . Error ( L , Msg , Ranges ) ; } </s>

Return an error at the location L , with the message Msg .


<s>
static
std
::
pair
<
SDValue
,
SDValue
>
splitVector
(
SDValue
Op
,
SelectionDAG
&
DAG
,
const
SDLoc
&
dl
)
{
EVT
VT
=
Op
.
getValueType
(
)
;
unsigned
NumElems
=
VT
.
getVectorNumElements
(
)
;
unsigned
SizeInBits
=
VT
.
getSizeInBits
(
)
;
assert
(
(
NumElems
%
2
)
==
0
&&
(
SizeInBits
%
2
)
==
0
&&
"Can't split odd sized vector"
)
;
SDValue
Lo
=
extractSubVector
(
Op
,
0
,
DAG
,
dl
,
SizeInBits
/
2
)
;
SDValue
Hi
=
extractSubVector
(
Op
,
NumElems
/
2
,
DAG
,
dl
,
SizeInBits
/
2
)
;
return
std
::
make_pair
(
Lo
,
Hi
)
;
}
</s>

Split a vector value into two parts of types LoVT and HiVT .