<s> SDValue R600TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; SmallVector < ISD :: InputArg , 8 > LocalIns ; if ( AMDGPU :: isShader ( CallConv ) ) { CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForCall ( CallConv , isVarArg ) ) ; } else { analyzeFormalArgumentsCompute ( CCInfo , Ins ) ; } for ( unsigned i = 0 , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const ISD :: InputArg & In = Ins [ i ] ; EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector ( ) ) { MemVT = MemVT . getVectorElementType ( ) ; } if ( AMDGPU :: isShader ( CallConv ) ) { Register Reg = MF . addLiveIn ( VA . getLocReg ( ) , & R600 :: R600_Reg128RegClass ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } ISD :: LoadExtType Ext = ISD :: NON_EXTLOAD ; if ( MemVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) { Ext = ISD :: SEXTLOAD ; } unsigned PartOffset = VA . getLocMemOffset ( ) ; unsigned Alignment = MinAlign ( VT . getStoreSize ( ) , PartOffset ) ; MachinePointerInfo PtrInfo ( AMDGPUAS :: PARAM_I_ADDRESS ) ; SDValue Arg = DAG . getLoad ( ISD :: UNINDEXED , Ext , VT , DL , Chain , DAG . getConstant ( PartOffset , DL , MVT :: i32 ) , DAG . getUNDEF ( MVT :: i32 ) , PtrInfo , MemVT , Alignment , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; InVals . push_back ( Arg ) ; } return Chain ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> int MipsAsmParser :: tryParseRegister ( bool is64BitReg ) { const AsmToken & Tok = Parser . getTok ( ) ; int RegNum = - 1 ; if ( Tok . is ( AsmToken :: Identifier ) ) { std :: string lowerCase = Tok . getString ( ) . lower ( ) ; RegNum = matchRegisterName ( lowerCase , is64BitReg ) ; } else if ( Tok . is ( AsmToken :: Integer ) ) RegNum = matchRegisterByNumber ( static_cast < unsigned > ( Tok . getIntVal ( ) ) , is64BitReg ? Mips :: GPR64RegClassID : Mips :: GPR32RegClassID ) ; return RegNum ; } </s>

tryParseRegister - parse one register if possible


<s>
const
char
*
getPassName
(
)
const
override
{
return
"PowerPC QPX Load Splat Simplification"
;
}
</s>

getPassName - Return a nice clean name for a pass .

PowerPC
"PowerPC QPX Load Splat Simplification"


Emit target-specific code that performs a memcpy .


<s> static int cris_reg_saved_in_regsave_area ( unsigned int regno , bool got_really_used ) { return ( ( ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) || ( regno == PIC_OFFSET_TABLE_REGNUM && ( got_really_used || ( flag_pic && df_regs_ever_live_p ( regno + 1 ) && ! call_used_regs [ regno + 1 ] ) ) ) ) && ( regno != FRAME_POINTER_REGNUM || ! frame_pointer_needed ) && regno != CRIS_SRP_REGNUM ) || ( crtl -> calls_eh_return && ( regno == EH_RETURN_DATA_REGNO ( 0 ) || regno == EH_RETURN_DATA_REGNO ( 1 ) || regno == EH_RETURN_DATA_REGNO ( 2 ) || regno == EH_RETURN_DATA_REGNO ( 3 ) ) ) ; } </s>

Return nonzero if REGNO is an ordinary register that * needs * to be saved together with other registers , possibly by a MOVEM instruction , or is saved for target-independent reasons . There may be target-dependent reasons to save the register anyway ; this is just a wrapper for a complicated conditional .


<s> bool JVMAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { return false ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


"Missing call preserved mask for calling convention"

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


<s> static int microblaze_adjust_cost ( rtx_insn * , int dep_type , rtx_insn * , int cost , unsigned int ) { if ( dep_type == REG_DEP_OUTPUT || dep_type == 0 ) return cost ; return 0 ; } </s>


<s> inline void function_expander :: add_fixed_operand ( rtx x ) { create_fixed_operand ( & m_ops [ opno ++ ] , x ) ; } </s>

Add an operand that must be X . The only way of legitimizing an invalid X is to reload the address of a MEM .


<s> static bool csky_fixed_condition_code_regs ( unsigned int * p1 , unsigned int * p2 ) { * p1 = CSKY_CC_REGNUM ; * p2 = INVALID_REGNUM ; return true ; } </s>


<s> static void frv_align_label ( void ) { unsigned int alignment , target , nop ; rtx x , last , barrier , label ; last = frv_packet . insns [ frv_packet . num_insns - 1 ] ; label = barrier = 0 ; alignment = 4 ; for ( x = NEXT_INSN ( last ) ; x != 0 && ! INSN_P ( x ) ; x = NEXT_INSN ( x ) ) { if ( LABEL_P ( x ) ) { unsigned int subalign = 1 << label_to_alignment ( x ) ; alignment = MAX ( alignment , subalign ) ; label = x ; } if ( BARRIER_P ( x ) ) barrier = x ; } if ( TARGET_ALIGN_LABELS && label != 0 && barrier == 0 && frv_packet . num_insns < frv_packet . issue_rate ) alignment = MAX ( alignment , 8 ) ; frv_packet_address += frv_packet . num_insns * 4 ; target = ( frv_packet_address + alignment - 1 ) & - alignment ; if ( barrier == 0 ) { for ( nop = 0 ; nop < frv_num_nops ; nop ++ ) while ( frv_packet_address < target && frv_pack_insn_p ( frv_nops [ nop ] ) ) { frv_insert_nop_in_packet ( frv_nops [ nop ] ) ; frv_packet_address += 4 ; } last = frv_packet . insns [ frv_packet . num_insns - 1 ] ; nop = 0 ; while ( frv_packet_address < target ) { last = emit_insn_after ( PATTERN ( frv_nops [ nop ] ) , last ) ; frv_packet_address += 4 ; if ( frv_num_nops > 1 ) nop ^= 1 ; } } frv_packet_address = target ; } </s>

If the current packet falls through to a label , try to pad the packet with nops in order to fit the label 's alignment requirements .


<s> int HexagonInstrInfo :: getOperandLatency ( const InstrItineraryData * ItinData , const MachineInstr & DefMI , unsigned DefIdx , const MachineInstr & UseMI , unsigned UseIdx ) const { const HexagonRegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; const MachineOperand & DefMO = DefMI . getOperand ( DefIdx ) ; if ( DefMO . isReg ( ) && Register :: isPhysicalRegister ( DefMO . getReg ( ) ) ) { if ( DefMO . isImplicit ( ) ) { for ( MCSuperRegIterator SR ( DefMO . getReg ( ) , & HRI ) ; SR . isValid ( ) ; ++ SR ) { int Idx = DefMI . findRegisterDefOperandIdx ( * SR , false , false , & HRI ) ; if ( Idx != - 1 ) { DefIdx = Idx ; break ; } } } const MachineOperand & UseMO = UseMI . getOperand ( UseIdx ) ; if ( UseMO . isImplicit ( ) ) { for ( MCSuperRegIterator SR ( UseMO . getReg ( ) , & HRI ) ; SR . isValid ( ) ; ++ SR ) { int Idx = UseMI . findRegisterUseOperandIdx ( * SR , false , & HRI ) ; if ( Idx != - 1 ) { UseIdx = Idx ; break ; } } } } int Latency = TargetInstrInfo :: getOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ; if ( ! Latency ) Latency = 1 ; return Latency ; } </s>

Compute and return the use operand latency of a given pair of def and use .


<s> static rtx expand_msb ( function_expander & e , unsigned int merge_argno = DEFAULT_MERGE_ARGNO ) { if ( e . pred == PRED_x ) { insn_code icode ; if ( e . type_suffix ( 0 ) . integer_p ) icode = code_for_aarch64_pred_fnma ( e . vector_mode ( 0 ) ) ; else icode = code_for_aarch64_pred ( UNSPEC_COND_FMLS , e . vector_mode ( 0 ) ) ; return e . use_pred_x_insn ( icode ) ; } insn_code icode = e . direct_optab_handler ( cond_fnma_optab ) ; return e . use_cond_insn ( icode , merge_argno ) ; } </s>

Expand a call to svmsb , or svmls after reordering its operands . Make _m forms merge with argument MERGE_ARGNO .


<s> static void rs6000_emit_stack_tie ( rtx fp , bool hard_frame_needed ) { rtvec p ; int i ; rtx regs [ 3 ] ; i = 0 ; regs [ i ++ ] = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; if ( hard_frame_needed ) regs [ i ++ ] = gen_rtx_REG ( Pmode , HARD_FRAME_POINTER_REGNUM ) ; if ( ! ( REGNO ( fp ) == STACK_POINTER_REGNUM || ( hard_frame_needed && REGNO ( fp ) == HARD_FRAME_POINTER_REGNUM ) ) ) regs [ i ++ ] = fp ; p = rtvec_alloc ( i ) ; while ( -- i >= 0 ) { rtx mem = gen_frame_mem ( BLKmode , regs [ i ] ) ; RTVEC_ELT ( p , i ) = gen_rtx_SET ( mem , const0_rtx ) ; } emit_insn ( gen_stack_tie ( gen_rtx_PARALLEL ( VOIDmode , p ) ) ) ; } </s>

This ties together stack memory ( MEM with an alias set of rs6000_sr_alias_set ) and the change to the stack pointer .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s> static void mmix_file_end ( void ) { switch_to_section ( data_section ) ; } </s>


<s>
bool
LC2200AsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Operands
.
push_back
(
LC2200Operand
::
CreateToken
(
Name
,
NameLoc
)
)
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
return
false
;
if
(
ParseOperand
(
Operands
)
)
return
true
;
while
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
getLexer
(
)
.
Lex
(
)
;
continue
;
}
if
(
ParseOperand
(
Operands
)
)
return
true
;
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
return
Error
(
getLexer
(
)
.
getTok
(
)
.
getLoc
(
)
,
"unexpected token in operand list"
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .


"  Skipping pass: no machine model present.\n"

runOnMachineFunction - Emit the function body .


"Larger stack frame not yet implemented"

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s>
DEBUG_FUNCTION
void
debug_ready_dispatch
(
void
)
{
int
i
;
int
no_ready
=
number_in_ready
(
)
;
fprintf
(
stdout
,
"Number of ready: %d\n"
,
no_ready
)
;
for
(
i
=
0
;
i
<
no_ready
;
i
++
)
debug_insn_dispatch_info_file
(
stdout
,
get_ready_element
(
i
)
)
;
}
</s>

Print to STDERR the status of the ready list with respect to dispatch windows .


"BPF CO-RE requires BTF debugging information, use %<-gbtf%>"

Override options and do some other initialization .


<s> bool TL45InstrInfo :: isAsCheapAsAMove ( const MachineInstr & MI ) const { const unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : break ; } return MI . isAsCheapAsAMove ( ) ; } </s>

Return true if the instruction is as cheap as a move instruction .


<s> void ix86_fp_comparison_codes ( enum rtx_code code , enum rtx_code * bypass_code , enum rtx_code * first_code , enum rtx_code * second_code ) { * first_code = code ; * bypass_code = UNKNOWN ; * second_code = UNKNOWN ; switch ( code ) { case GT : case GE : case ORDERED : case UNORDERED : case UNEQ : case UNLT : case UNLE : case LTGT : break ; case LT : * first_code = UNLT ; * bypass_code = UNORDERED ; break ; case LE : * first_code = UNLE ; * bypass_code = UNORDERED ; break ; case EQ : * first_code = UNEQ ; * bypass_code = UNORDERED ; break ; case NE : * first_code = LTGT ; * second_code = UNORDERED ; break ; case UNGE : * first_code = GE ; * second_code = UNORDERED ; break ; case UNGT : * first_code = GT ; * second_code = UNORDERED ; break ; default : gcc_unreachable ( ) ; } if ( ! TARGET_IEEE_FP ) { * second_code = UNKNOWN ; * bypass_code = UNKNOWN ; } } </s>

Split comparison code CODE into comparisons we can do using branch instructions . BYPASS_CODE is comparison code for branch that will branch around FIRST_CODE and SECOND_CODE . If some of branches is not required , set value to UNKNOWN . We never require more than two branches .


<s> static void s390_add_execute ( struct constant_pool * pool , rtx insn ) { struct constant * c ; for ( c = pool -> execute ; c != NULL ; c = c -> next ) if ( INSN_UID ( insn ) == INSN_UID ( c -> value ) ) break ; if ( c == NULL ) { c = ( struct constant * ) xmalloc ( sizeof * c ) ; c -> value = insn ; c -> label = gen_label_rtx ( ) ; c -> next = pool -> execute ; pool -> execute = c ; pool -> size += 6 ; } } </s>

Add execute target for INSN to the constant pool POOL .


"=== RegBanks reassign analysis on function "

"RegBank reassign stall cycles verification failed."


<s> bool getAlign ( const CallInst & I , unsigned index , unsigned & align ) { if ( MDNode * alignNode = I . getMetadata ( "callalign" ) ) { for ( int i = 0 , n = alignNode -> getNumOperands ( ) ; i < n ; i ++ ) { if ( const ConstantInt * CI = mdconst :: dyn_extract < ConstantInt > ( alignNode -> getOperand ( i ) ) ) { unsigned v = CI -> getZExtValue ( ) ; if ( ( v >> 16 ) == index ) { align = v & 0xFFFF ; return true ; } if ( ( v >> 16 ) > index ) { return false ; } } } } return false ; } </s>

Return the minimum known alignment in bytes of the actual memory reference .


<s> void FISCInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( FISC :: STR ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool isReg ( ) const override { return Kind == Register ; } </s>


<s> static void pa_hpux_file_end ( void ) { unsigned int i ; extern_symbol * p ; if ( ! NO_DEFERRED_PROFILE_COUNTERS ) output_deferred_profile_counters ( ) ; output_deferred_plabels ( ) ; for ( i = 0 ; vec_safe_iterate ( extern_symbols , i , & p ) ; i ++ ) { tree decl = p -> decl ; if ( ! TREE_ASM_WRITTEN ( decl ) && SYMBOL_REF_REFERENCED_P ( XEXP ( DECL_RTL ( decl ) , 0 ) ) ) ASM_OUTPUT_EXTERNAL_REAL ( asm_out_file , decl , p -> name ) ; } vec_free ( extern_symbols ) ; } </s>

Output text required at the end of an assembler file . This includes deferred plabels and .import directives for all external symbols that were actually referenced .


<s> bool RISCVTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; for ( unsigned i = 0 , e = Outs . size ( ) ; i != e ; ++ i ) { MVT VT = Outs [ i ] . VT ; ISD :: ArgFlagsTy ArgFlags = Outs [ i ] . Flags ; if ( CC_RISCV ( MF . getDataLayout ( ) , i , VT , VT , CCValAssign :: Full , ArgFlags , CCInfo , true , true ) ) return false ; } return true ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .

RISCV RISCV ISD::OutputArg 16 0 ISD::ArgFlagsTy RISCV


<s> static int vfp3_const_double_index ( rtx x ) { REAL_VALUE_TYPE r , m ; int sign , exponent ; unsigned HOST_WIDE_INT mantissa , mant_hi ; unsigned HOST_WIDE_INT mask ; int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1 ; bool fail ; if ( ! TARGET_VFP3 || ! CONST_DOUBLE_P ( x ) ) return - 1 ; r = * CONST_DOUBLE_REAL_VALUE ( x ) ; if ( REAL_VALUE_ISINF ( r ) || REAL_VALUE_ISNAN ( r ) || REAL_VALUE_MINUS_ZERO ( r ) ) return - 1 ; sign = REAL_VALUE_NEGATIVE ( r ) ? 1 : 0 ; r = real_value_abs ( & r ) ; exponent = REAL_EXP ( & r ) ; real_ldexp ( & m , & r , point_pos - exponent ) ; wide_int w = real_to_integer ( & m , & fail , HOST_BITS_PER_WIDE_INT * 2 ) ; mantissa = w . elt ( 0 ) ; mant_hi = w . elt ( 1 ) ; if ( mantissa != 0 ) return - 1 ; point_pos -= HOST_BITS_PER_WIDE_INT ; mantissa = mant_hi ; mask = ( HOST_WIDE_INT_1U << ( point_pos - 5 ) ) - 1 ; if ( ( mantissa & mask ) != 0 ) return - 1 ; mantissa >>= point_pos - 5 ; if ( mantissa == 0 ) return - 1 ; gcc_assert ( mantissa >= 16 && mantissa <= 31 ) ; exponent = 5 - exponent ; if ( exponent < 0 || exponent > 7 ) return - 1 ; return ( sign << 7 ) | ( ( exponent ^ 3 ) << 4 ) | ( mantissa - 16 ) ; } </s>

Return an integer index for a VFPv3 immediate operand X suitable for the fconst [ sd ] instruction , or -1 if X is n't suitable .


<s> bool LC2200AsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool SIWholeQuadMode :: runOnMachineFunction ( MachineFunction & MF ) { Instructions . clear ( ) ; Blocks . clear ( ) ; LiveMaskQueries . clear ( ) ; LowerToCopyInstrs . clear ( ) ; CallingConv = MF . getFunction ( ) . getCallingConv ( ) ; const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; LIS = & getAnalysis < LiveIntervals > ( ) ; char GlobalFlags = analyzeFunction ( MF ) ; unsigned LiveMaskReg = 0 ; if ( ! ( GlobalFlags & StateWQM ) ) { lowerLiveMaskQueries ( AMDGPU :: EXEC ) ; if ( ! ( GlobalFlags & StateWWM ) ) return ! LiveMaskQueries . empty ( ) ; } else { MachineBasicBlock & Entry = MF . front ( ) ; MachineBasicBlock :: iterator EntryMI = Entry . getFirstNonPHI ( ) ; if ( GlobalFlags & StateExact || ! LiveMaskQueries . empty ( ) ) { LiveMaskReg = MRI -> createVirtualRegister ( & AMDGPU :: SReg_64RegClass ) ; MachineInstr * MI = BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( AMDGPU :: COPY ) , LiveMaskReg ) . addReg ( AMDGPU :: EXEC ) ; LIS -> InsertMachineInstrInMaps ( * MI ) ; } lowerLiveMaskQueries ( LiveMaskReg ) ; if ( GlobalFlags == StateWQM ) { BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( AMDGPU :: S_WQM_B64 ) , AMDGPU :: EXEC ) . addReg ( AMDGPU :: EXEC ) ; lowerCopyInstrs ( ) ; return true ; } } LLVM_DEBUG ( printInfo ( ) ) ; lowerCopyInstrs ( ) ; for ( auto BII : Blocks ) processBlock ( * BII . first , LiveMaskReg , BII . first == & * MF . begin ( ) ) ; LIS -> removeRegUnit ( * MCRegUnitIterator ( AMDGPU :: SCC , TRI ) ) ; return true ; } </s>

AMDGPU SI SI SI 0 AMDGPU::EXEC AMDGPU::SReg_64RegClass AMDGPU::COPY AMDGPU::EXEC AMDGPU::S_WQM_B64 AMDGPU::EXEC AMDGPU::EXEC AMDGPU::SCC


<s> const NVPTXInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> int s390_class_max_nregs ( enum reg_class rclass , machine_mode mode ) { int reg_size ; bool reg_pair_required_p = false ; switch ( rclass ) { case FP_REGS : case VEC_REGS : reg_size = TARGET_VX ? 16 : 8 ; if ( TARGET_VX && SCALAR_FLOAT_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) >= 16 && ! ( TARGET_VXE && mode == TFmode ) ) reg_pair_required_p = true ; if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) reg_pair_required_p = true ; break ; case ACCESS_REGS : reg_size = 4 ; break ; default : reg_size = UNITS_PER_WORD ; break ; } if ( reg_pair_required_p ) return 2 * ( ( GET_MODE_SIZE ( mode ) / 2 + reg_size - 1 ) / reg_size ) ; return ( GET_MODE_SIZE ( mode ) + reg_size - 1 ) / reg_size ; } </s>

Maximum number of registers to represent a value of mode MODE in a register of class RCLASS .


<s>
static
void
rs6000_output_function_prologue
(
FILE
*
file
,
HOST_WIDE_INT
size
ATTRIBUTE_UNUSED
)
{
if
(
!
cfun
->
is_thunk
)
rs6000_output_savres_externs
(
file
)
;
if
(
rs6000_global_entry_point_needed_p
(
)
)
{
const
char
*
name
=
XSTR
(
XEXP
(
DECL_RTL
(
current_function_decl
)
,
0
)
,
0
)
;
(
*
targetm
.
asm_out
.
internal_label
)
(
file
,
"LCF"
,
rs6000_pic_labelno
)
;
if
(
TARGET_CMODEL
!=
CMODEL_LARGE
)
{
char
buf
[
256
]
;
ASM_GENERATE_INTERNAL_LABEL
(
buf
,
"LCF"
,
rs6000_pic_labelno
)
;
fprintf
(
file
,
"0:\taddis 2,12,.TOC.-"
)
;
assemble_name
(
file
,
buf
)
;
fprintf
(
file
,
"@ha\n"
)
;
fprintf
(
file
,
"\taddi 2,2,.TOC.-"
)
;
assemble_name
(
file
,
buf
)
;
fprintf
(
file
,
"@l\n"
)
;
}
else
{
char
buf
[
256
]
;
fprintf
(
file
,
"\t.reloc .,R_PPC64_ENTRY\n"
)
;
fprintf
(
file
,
"\tld 2,"
)
;
ASM_GENERATE_INTERNAL_LABEL
(
buf
,
"LCL"
,
rs6000_pic_labelno
)
;
assemble_name
(
file
,
buf
)
;
fprintf
(
file
,
"-"
)
;
ASM_GENERATE_INTERNAL_LABEL
(
buf
,
"LCF"
,
rs6000_pic_labelno
)
;
assemble_name
(
file
,
buf
)
;
fprintf
(
file
,
"(12)\n"
)
;
fprintf
(
file
,
"\tadd 2,2,12\n"
)
;
}
fputs
(
"\t.localentry\t"
,
file
)
;
assemble_name
(
file
,
name
)
;
fputs
(
",.-"
,
file
)
;
assemble_name
(
file
,
name
)
;
fputs
(
"\n"
,
file
)
;
}
if
(
TARGET_PROFILE_KERNEL
&&
crtl
->
profile
)
{
gcc_assert
(
DEFAULT_ABI
==
ABI_AIX
||
DEFAULT_ABI
==
ABI_ELFv2
)
;
gcc_assert
(
!
TARGET_32BIT
)
;
asm_fprintf
(
file
,
"\tmflr %s\n"
,
reg_names
[
0
]
)
;
if
(
DEFAULT_ABI
!=
ABI_ELFv2
&&
cfun
->
static_chain_decl
!=
)
{
asm_fprintf
(
file
,
"\tstd %s,24(%s)\n"
,
reg_names
[
STATIC_CHAIN_REGNUM
]
,
reg_names
[
1
]
)
;
fprintf
(
file
,
"\tbl %s\n"
,
RS6000_MCOUNT
)
;
asm_fprintf
(
file
,
"\tld %s,24(%s)\n"
,
reg_names
[
STATIC_CHAIN_REGNUM
]
,
reg_names
[
1
]
)
;
}
else
fprintf
(
file
,
"\tbl %s\n"
,
RS6000_MCOUNT
)
;
}
rs6000_pic_labelno
++
;
}
</s>


"WebAssembly Lower Emscripten Exceptions"

getPassName - Return a nice clean name for a pass .


<s> unsigned Z80RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { return 3 ; const Z80FrameLowering * TFI = getFrameLowering ( MF ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case Z80 :: R16RegClassID : case Z80 :: R24RegClassID : return 2 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> bool RV16KDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { switch ( ConstraintID ) { case InlineAsm :: Constraint_i : llvm_unreachable ( "" ) ; case InlineAsm :: Constraint_m : OutOps . push_back ( Op ) ; return false ; default : break ; } return true ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> SDValue X86TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: EXTRACT_VECTOR_ELT : return PerformEXTRACT_VECTOR_ELTCombine ( N , DAG , * this ) ; case ISD :: SELECT : return PerformSELECTCombine ( N , DAG , Subtarget ) ; case X86ISD :: CMOV : return PerformCMOVCombine ( N , DAG , DCI ) ; case ISD :: MUL : return PerformMulCombine ( N , DAG , DCI ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DAG , Subtarget ) ; case ISD :: OR : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: STORE : return PerformSTORECombine ( N , DAG , Subtarget ) ; case X86ISD :: FXOR : case X86ISD :: FOR : return PerformFORCombine ( N , DAG ) ; case X86ISD :: FAND : return PerformFANDCombine ( N , DAG ) ; case X86ISD :: BT : return PerformBTCombine ( N , DAG , DCI ) ; case X86ISD :: VZEXT_MOVL : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case ISD :: ZERO_EXTEND : return PerformZExtCombine ( N , DAG ) ; case X86ISD :: SHUFPS : case X86ISD :: SHUFPD : case X86ISD :: PUNPCKHBW : case X86ISD :: PUNPCKHWD : case X86ISD :: PUNPCKHDQ : case X86ISD :: PUNPCKHQDQ : case X86ISD :: UNPCKHPS : case X86ISD :: UNPCKHPD : case X86ISD :: PUNPCKLBW : case X86ISD :: PUNPCKLWD : case X86ISD :: PUNPCKLDQ : case X86ISD :: PUNPCKLQDQ : case X86ISD :: UNPCKLPS : case X86ISD :: UNPCKLPD : case X86ISD :: MOVHLPS : case X86ISD :: MOVLHPS : case X86ISD :: PSHUFD : case X86ISD :: PSHUFHW : case X86ISD :: PSHUFLW : case X86ISD :: MOVSS : case X86ISD :: MOVSD : case ISD :: VECTOR_SHUFFLE : return PerformShuffleCombine ( N , DAG , * this ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly


<s> bool isVarArg ( ) const { return IsVarArg ; } </s>

isVarArg - Return true if this function takes a variable number of arguments .


<s> Register getExceptionSelectorRegister ( const Constant * PersonalityFn ) const override { return Hexagon :: R1 ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .


<s>
bool
X86LoadValueInjectionRetHardeningPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"***** "
<<
getPassName
(
)
<<
" : "
<<
MF
.
getName
(
)
<<
" *****\n"
)
;
const
X86Subtarget
*
Subtarget
=
&
MF
.
getSubtarget
<
X86Subtarget
>
(
)
;
if
(
!
Subtarget
->
useLVIControlFlowIntegrity
(
)
||
!
Subtarget
->
is64Bit
(
)
)
return
false
;
const
Function
&
F
=
MF
.
getFunction
(
)
;
if
(
!
F
.
hasOptNone
(
)
&&
skipFunction
(
F
)
)
return
false
;
++
NumFunctionsConsidered
;
const
X86RegisterInfo
*
TRI
=
Subtarget
->
getRegisterInfo
(
)
;
const
X86InstrInfo
*
TII
=
Subtarget
->
getInstrInfo
(
)
;
bool
Modified
=
false
;
for
(
auto
&
MBB
:
MF
)
{
for
(
auto
MBBI
=
MBB
.
begin
(
)
;
MBBI
!=
MBB
.
end
(
)
;
++
MBBI
)
{
if
(
MBBI
->
getOpcode
(
)
!=
X86
::
RET64
)
continue
;
unsigned
ClobberReg
=
TRI
->
findDeadCallerSavedReg
(
MBB
,
MBBI
)
;
if
(
ClobberReg
!=
X86
::
NoRegister
)
{
BuildMI
(
MBB
,
MBBI
,
DebugLoc
(
)
,
TII
->
get
(
X86
::
POP64r
)
)
.
addReg
(
ClobberReg
,
RegState
::
Define
)
.
setMIFlag
(
MachineInstr
::
FrameDestroy
)
;
BuildMI
(
MBB
,
MBBI
,
DebugLoc
(
)
,
TII
->
get
(
X86
::
LFENCE
)
)
;
BuildMI
(
MBB
,
MBBI
,
DebugLoc
(
)
,
TII
->
get
(
X86
::
JMP64r
)
)
.
addReg
(
ClobberReg
)
;
MBB
.
erase
(
MBBI
)
;
}
else
{
MachineInstr
*
Fence
=
BuildMI
(
MBB
,
MBBI
,
DebugLoc
(
)
,
TII
->
get
(
X86
::
LFENCE
)
)
;
addRegOffset
(
BuildMI
(
MBB
,
Fence
,
DebugLoc
(
)
,
TII
->
get
(
X86
::
SHL64mi
)
)
,
X86
::
RSP
,
false
,
0
)
.
addImm
(
0
)
->
addRegisterDead
(
X86
::
EFLAGS
,
TRI
)
;
}
++
NumFences
;
Modified
=
true
;
break
;
}
}
if
(
Modified
)
++
NumFunctionsMitigated
;
return
Modified
;
}
</s>

runOnMachineFunction - Emit the function body .


"Did not fully process a global variable"

EmitGlobals - Emit all of the global variables to memory , storing their addresses into GlobalAddress .


<s> MCSection * getExplicitSectionGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler & Mang , const TargetMachine & TM ) const override { return DataSection ; } </s>

Targets should implement this method to assign a section to globals with an explicit section specfied .


<s> Value * AArch64TargetLowering :: getSafeStackPointerLocation ( IRBuilderBase & IRB ) const { if ( Subtarget -> isTargetAndroid ( ) ) return UseTlsOffset ( IRB , 0x48 ) ; if ( Subtarget -> isTargetFuchsia ( ) ) return UseTlsOffset ( IRB , - 0x8 ) ; return TargetLowering :: getSafeStackPointerLocation ( IRB ) ; } </s>

Return true if the target stores SafeStack pointer at a fixed offset in some non-standard address space , and populates the address space and offset as appropriate .


<s> DecodeStatus SystemZDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & OS , raw_ostream & CS ) const { Size = 0 ; if ( Bytes . size ( ) < 2 ) return MCDisassembler :: Fail ; const uint8_t * Table ; if ( Bytes [ 0 ] < 0x40 ) { Size = 2 ; Table = DecoderTable16 ; } else if ( Bytes [ 0 ] < 0xc0 ) { Size = 4 ; Table = DecoderTable32 ; } else { Size = 6 ; Table = DecoderTable48 ; } if ( Bytes . size ( ) < Size ) return MCDisassembler :: Fail ; uint64_t Inst = 0 ; for ( uint64_t I = 0 ; I < Size ; ++ I ) Inst = ( Inst << 8 ) | Bytes [ I ] ; return decodeInstruction ( Table , MI , Inst , Address , this , STI ) ; } </s>

Returns the disassembly of a single instruction .


<s> const MBlazeInstrInfo * getInstrInfo ( ) { return getTargetMachine ( ) . getInstrInfo ( ) ; } </s>


<s>
SUnit
*
R600SchedStrategy
::
pickNode
(
bool
&
IsTopNode
)
{
SUnit
*
SU
=
nullptr
;
NextInstKind
=
IDOther
;
IsTopNode
=
false
;
bool
AllowSwitchToAlu
=
(
CurEmitted
>=
InstKindLimit
[
CurInstKind
]
)
||
(
Available
[
CurInstKind
]
.
empty
(
)
)
;
bool
AllowSwitchFromAlu
=
(
CurEmitted
>=
InstKindLimit
[
CurInstKind
]
)
&&
(
!
Available
[
IDFetch
]
.
empty
(
)
||
!
Available
[
IDOther
]
.
empty
(
)
)
;
if
(
CurInstKind
==
IDAlu
&&
!
Available
[
IDFetch
]
.
empty
(
)
)
{
float
ALUFetchRationEstimate
=
(
AluInstCount
+
AvailablesAluCount
(
)
+
Pending
[
IDAlu
]
.
size
(
)
)
/
(
FetchInstCount
+
Available
[
IDFetch
]
.
size
(
)
)
;
if
(
ALUFetchRationEstimate
==
0
)
{
AllowSwitchFromAlu
=
true
;
}
else
{
unsigned
NeededWF
=
62.5f
/
ALUFetchRationEstimate
;
LLVM_DEBUG
(
dbgs
(
)
<<
NeededWF
<<
" approx. Wavefronts Required\n"
)
;
unsigned
NearRegisterRequirement
=
2
*
Available
[
IDFetch
]
.
size
(
)
;
if
(
NeededWF
>
getWFCountLimitedByGPR
(
NearRegisterRequirement
)
)
AllowSwitchFromAlu
=
true
;
}
}
if
(
!
SU
&&
(
(
AllowSwitchToAlu
&&
CurInstKind
!=
IDAlu
)
||
(
!
AllowSwitchFromAlu
&&
CurInstKind
==
IDAlu
)
)
)
{
SU
=
pickAlu
(
)
;
if
(
!
SU
&&
!
PhysicalRegCopy
.
empty
(
)
)
{
SU
=
PhysicalRegCopy
.
front
(
)
;
PhysicalRegCopy
.
erase
(
PhysicalRegCopy
.
begin
(
)
)
;
}
if
(
SU
)
{
if
(
CurEmitted
>=
InstKindLimit
[
IDAlu
]
)
CurEmitted
=
0
;
NextInstKind
=
IDAlu
;
}
}
if
(
!
SU
)
{
SU
=
pickOther
(
IDFetch
)
;
if
(
SU
)
NextInstKind
=
IDFetch
;
}
if
(
!
SU
)
{
SU
=
pickOther
(
IDOther
)
;
if
(
SU
)
NextInstKind
=
IDOther
;
}
LLVM_DEBUG
(
if
(
SU
)
{
dbgs
(
)
<<
" ** Pick node **\n"
;
DAG
->
dumpNode
(
*
SU
)
;
}
else
{
dbgs
(
)
<<
"NO NODE \n"
;
for
(
unsigned
i
=
0
;
i
<
DAG
->
SUnits
.
size
(
)
;
i
++
)
{
const
SUnit
&
S
=
DAG
->
SUnits
[
i
]
;
if
(
!
S
.
isScheduled
)
DAG
->
dumpNode
(
S
)
;
}
}
</s>

Pick the next node to schedule , or return NULL .


<s> bool LinuxAsmPrinter :: doFinalization ( Module & M ) { for ( Module :: const_global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ; I != E ; ++ I ) printModuleLevelGV ( I ) ; DW -> EndModule ( ) ; return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> void s390_function_arg_advance ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int named ATTRIBUTE_UNUSED ) { if ( s390_function_arg_float ( mode , type ) ) { cum -> fprs += 1 ; } else if ( s390_function_arg_integer ( mode , type ) ) { int size = s390_function_arg_size ( mode , type ) ; cum -> gprs += ( ( size + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ) ; } else gcc_unreachable ( ) ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available. ) . The boolean NAMED specifies whether the argument is a named argument ( as opposed to an unnamed argument matching an ellipsis ) .


<s> static machine_mode rs6000_preferred_doloop_mode ( machine_mode ) { return word_mode ; } </s>


<s> enum reg_class s390_preferred_reload_class ( rtx op , enum reg_class class ) { switch ( GET_CODE ( op ) ) { case CONST_DOUBLE : case CONST_INT : if ( legitimate_reload_constant_p ( op ) ) return class ; else return NO_REGS ; case PLUS : case LABEL_REF : case SYMBOL_REF : case CONST : if ( reg_class_subset_p ( ADDR_REGS , class ) ) return ADDR_REGS ; else return NO_REGS ; default : break ; } return class ; } </s>

Given an rtx OP being reloaded into a reg required to be in class CLASS , return the class of reg to actually use .


<s> int64_t getOffset ( ) { return Offset ; } </s>

Get the offest of a string in the string table .


"emitting conditional microcode insn %s\t[%s] #%d"

Define FINAL_PRESCAN_INSN if some processing needs to be done before outputting the assembler code . On the PowerPC , we remember if the current insn is a prefixed insn where we need to emit a ' p ' before the insn . In addition , if the insn is part of a PC-relative reference to an external label optimization , this is recorded also .


<s> virtual const MCSection * getSectionForConstant ( SectionKind Kind ) const { return ReadOnlySection ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> bool pass_vsetvl :: hard_empty_block_p ( const bb_info * bb , const vector_insn_info & info ) const { if ( ! info . dirty_p ( ) || ! info . has_avl_reg ( ) ) return false ; basic_block cfg_bb = bb -> cfg_bb ( ) ; sbitmap avin = m_vector_manager -> vector_avin [ cfg_bb -> index ] ; set_info * set = info . get_avl_source ( ) ; rtx avl = gen_rtx_REG ( Pmode , set -> regno ( ) ) ; hash_set < set_info * > sets = get_all_sets ( set , true , false , false ) ; hash_set < basic_block > pred_cfg_bbs = get_all_predecessors ( cfg_bb ) ; if ( find_reg_killed_by ( bb , avl ) ) { gcc_assert ( info . dirty_with_killed_avl_p ( ) ) ; if ( info . get_avl_source ( ) && get_same_bb_set ( sets , bb -> cfg_bb ( ) ) == info . get_avl_source ( ) ) return false ; } if ( bitmap_empty_p ( avin ) ) { bool hard_empty_p = true ; for ( const basic_block pred_cfg_bb : pred_cfg_bbs ) { if ( pred_cfg_bb == ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) continue ; sbitmap avout = m_vector_manager -> vector_avout [ pred_cfg_bb -> index ] ; if ( ! bitmap_empty_p ( avout ) ) { hard_empty_p = false ; break ; } } if ( hard_empty_p ) return true ; } edge e ; edge_iterator ei ; bool has_avl_killed_insn_p = false ; FOR_EACH_EDGE ( e , ei , cfg_bb -> succs ) { const auto block_info = m_vector_manager -> vector_block_infos [ e -> dest -> index ] ; if ( block_info . local_dem . dirty_with_killed_avl_p ( ) ) { has_avl_killed_insn_p = true ; break ; } } if ( ! has_avl_killed_insn_p ) return false ; bool any_set_in_bbs_p = false ; for ( const basic_block pred_cfg_bb : pred_cfg_bbs ) { insn_info * def_insn = extract_single_source ( set ) ; if ( def_insn ) { insn_info * last_killed_insn = find_reg_killed_by ( crtl -> ssa -> bb ( pred_cfg_bb ) , avl ) ; if ( ! last_killed_insn || pred_cfg_bb == def_insn -> bb ( ) -> cfg_bb ( ) ) continue ; if ( source_equal_p ( last_killed_insn , def_insn ) ) { any_set_in_bbs_p = true ; break ; } } else { if ( any_set_in_bb_p ( sets , crtl -> ssa -> bb ( pred_cfg_bb ) ) ) { any_set_in_bbs_p = true ; break ; } } } if ( ! any_set_in_bbs_p ) return true ; return false ; } </s>

We almost enable all cases in get_backward_fusion_type , this function disable the backward fusion by changing dirty blocks into hard empty blocks in forward dataflow . We can have more accurate optimization by this method .


<s>
bool
CookieSetter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
TII
=
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
if
(
!
MF
.
getFunction
(
)
->
hasFnAttribute
(
Attribute
::
CookieCheck
)
)
{
DEBUG
(
dbgs
(
)
<<
"Setting cookies for "
<<
MF
.
getName
(
)
<<
"\n"
)
;
LowerSetCookieInstrs
(
MF
)
;
}
return
true
;
}
</s>


<s> bool GCNHazardRecognizer :: ShouldPreferAnother ( SUnit * SU ) { if ( ! SU -> isInstr ( ) ) return false ; MachineInstr * MAI = nullptr ; auto IsMFMAFn = [ & MAI ] ( MachineInstr * MI ) { MAI = nullptr ; if ( SIInstrInfo :: isMAI ( * MI ) && MI -> getOpcode ( ) != AMDGPU :: V_ACCVGPR_WRITE_B32_e64 && MI -> getOpcode ( ) != AMDGPU :: V_ACCVGPR_READ_B32_e64 ) MAI = MI ; return MAI != nullptr ; } ; MachineInstr * MI = SU -> getInstr ( ) ; if ( IsMFMAFn ( MI ) ) { int W = getWaitStatesSince ( IsMFMAFn , 16 ) ; if ( MAI ) return W < ( int ) TSchedModel . computeInstrLatency ( MAI ) ; } return false ; } </s>

ShouldPreferAnother - This callback may be invoked if getHazardType returns NoHazard .


<s> void ARMPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createARMLoadStoreOptimizationPass ( true ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None && getARMSubtarget ( ) . isCortexA9 ( ) ) addPass ( createMLxExpansionPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None && getARMSubtarget ( ) . isCortexA15 ( ) && getARMSubtarget ( ) . hasNEON ( ) && ! DisableA15SDOptimization ) { addPass ( createA15SDOptimizerPass ( ) ) ; } } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static void bpf_asm_named_section ( const char * name , unsigned int flags ATTRIBUTE_UNUSED , tree decl ATTRIBUTE_UNUSED ) { fprintf ( asm_out_file , "\t.section\t%s\n" , name ) ; } </s>

Output assembly directives to switch to section NAME . The section should have attributes as specified by FLAGS , which is a bit mask of the 'SECTION_ * ' flags defined in 'output.h ' . If DECL is non-NULL , it is the 'VAR_DECL ' or 'FUNCTION_DECL ' with which this section is associated .


<s> void GCNPassConfig :: addOptimizedRegAlloc ( FunctionPass * RegAllocPass ) { insertPass ( & MachineSchedulerID , & SIFixControlFlowLiveIntervalsID ) ; insertPass ( & PHIEliminationID , & SILowerControlFlowID , false ) ; TargetPassConfig :: addOptimizedRegAlloc ( RegAllocPass ) ; } </s>

addOptimizedRegAlloc - Add passes related to register allocation .


<s> void loongarch_expand_conditional_move ( rtx * operands ) { enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; rtx op0 = XEXP ( operands [ 1 ] , 0 ) ; rtx op1 = XEXP ( operands [ 1 ] , 1 ) ; if ( FLOAT_MODE_P ( GET_MODE ( op1 ) ) ) loongarch_emit_float_compare ( & code , & op0 , & op1 ) ; else { loongarch_extend_comparands ( code , & op0 , & op1 ) ; op0 = force_reg ( word_mode , op0 ) ; if ( code == EQ || code == NE ) { op0 = loongarch_zero_if_equal ( op0 , op1 ) ; op1 = const0_rtx ; } else { bool invert = false ; rtx target = gen_reg_rtx ( GET_MODE ( op0 ) ) ; loongarch_emit_int_order_test ( code , & invert , target , op0 , op1 ) ; code = invert ? EQ : NE ; op0 = target ; op1 = const0_rtx ; } } rtx cond = gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 , op1 ) ; if ( INTEGRAL_MODE_P ( GET_MODE ( operands [ 2 ] ) ) && register_operand ( operands [ 2 ] , VOIDmode ) && register_operand ( operands [ 3 ] , VOIDmode ) ) { machine_mode mode = GET_MODE ( operands [ 0 ] ) ; rtx temp = gen_reg_rtx ( mode ) ; rtx temp2 = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_IF_THEN_ELSE ( mode , cond , operands [ 2 ] , const0_rtx ) ) ) ; cond = gen_rtx_fmt_ee ( ( code == EQ ) ? NE : EQ , GET_MODE ( op0 ) , op0 , op1 ) ; emit_insn ( gen_rtx_SET ( temp2 , gen_rtx_IF_THEN_ELSE ( mode , cond , operands [ 3 ] , const0_rtx ) ) ) ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , gen_rtx_IOR ( mode , temp , temp2 ) ) ) ; } else emit_insn ( gen_rtx_SET ( operands [ 0 ] , gen_rtx_IF_THEN_ELSE ( GET_MODE ( operands [ 0 ] ) , cond , operands [ 2 ] , operands [ 3 ] ) ) ) ; } </s>

Perform the comparison in OPERANDS [ 1 ] . Move OPERANDS [ 2 ] into OPERANDS [ 0 ] if the condition holds , otherwise move OPERANDS [ 3 ] into OPERANDS [ 0 ] .


<s>
SDValue
AVRTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
if
(
CallConv
==
CallingConv
::
AVR_BUILTIN
)
{
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_AVR_BUILTIN
)
;
}
else
{
analyzeReturnValues
(
Outs
,
CCInfo
)
;
}
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
if
(
MF
.
getFunction
(
)
.
getAttributes
(
)
.
hasAttribute
(
AttributeList
::
FunctionIndex
,
Attribute
::
Naked
)
)
{
return
Chain
;
}
const
AVRMachineFunctionInfo
*
AFI
=
MF
.
getInfo
<
AVRMachineFunctionInfo
>
(
)
;
unsigned
RetOpc
=
AFI
->
isInterruptOrSignalHandler
(
)
AVRISD
::
RETI_FLAG
:
AVRISD
::
RET_FLAG
;
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
{
RetOps
.
push_back
(
Flag
)
;
}
return
DAG
.
getNode
(
RetOpc
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static bool can_use_callp ( rtx_insn * insn ) { int icode = recog_memoized ( insn ) ; if ( ! TARGET_INSNS_64PLUS || icode < 0 || GET_CODE ( PATTERN ( insn ) ) == COND_EXEC ) return false ; return ( ( icode == CODE_FOR_real_call || icode == CODE_FOR_call_internal || icode == CODE_FOR_call_value_internal ) && get_attr_dest_regfile ( insn ) == DEST_REGFILE_ANY ) ; } </s>

Determine whether INSN 's pattern can be converted to use callp .


<s> bool X86AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < X86Subtarget > ( ) ; SMShadowTracker . startFunction ( MF ) ; CodeEmitter . reset ( TM . getTarget ( ) . createMCCodeEmitter ( * Subtarget -> getInstrInfo ( ) , MF . getContext ( ) ) ) ; EmitFPOData = Subtarget -> isTargetWin32 ( ) && MF . getMMI ( ) . getModule ( ) -> getCodeViewFlag ( ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Local = MF . getFunction ( ) . hasLocalLinkage ( ) ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> emitCOFFSymbolStorageClass ( Local ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer -> emitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } emitFunctionBody ( ) ; emitXRayTable ( ) ; EmitFPOData = false ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> SDValue PPCTargetLowering :: getNegatedExpression ( SDValue Op , SelectionDAG & DAG , bool LegalOps , bool OptForSize , NegatibleCost & Cost , unsigned Depth ) const { if ( Depth > SelectionDAG :: MaxRecursionDepth ) return SDValue ( ) ; unsigned Opc = Op . getOpcode ( ) ; EVT VT = Op . getValueType ( ) ; SDNodeFlags Flags = Op . getNode ( ) -> getFlags ( ) ; switch ( Opc ) { case PPCISD :: FNMSUB : if ( ! Op . hasOneUse ( ) || ! isTypeLegal ( VT ) ) break ; const TargetOptions & Options = getTargetMachine ( ) . Options ; SDValue N0 = Op . getOperand ( 0 ) ; SDValue N1 = Op . getOperand ( 1 ) ; SDValue N2 = Op . getOperand ( 2 ) ; SDLoc Loc ( Op ) ; NegatibleCost N2Cost = NegatibleCost :: Expensive ; SDValue NegN2 = getNegatedExpression ( N2 , DAG , LegalOps , OptForSize , N2Cost , Depth + 1 ) ; if ( ! NegN2 ) return SDValue ( ) ; if ( Flags . hasNoSignedZeros ( ) || Options . NoSignedZerosFPMath ) { NegatibleCost N0Cost = NegatibleCost :: Expensive ; SDValue NegN0 = getNegatedExpression ( N0 , DAG , LegalOps , OptForSize , N0Cost , Depth + 1 ) ; NegatibleCost N1Cost = NegatibleCost :: Expensive ; SDValue NegN1 = getNegatedExpression ( N1 , DAG , LegalOps , OptForSize , N1Cost , Depth + 1 ) ; if ( NegN0 && N0Cost <= N1Cost ) { Cost = std :: min ( N0Cost , N2Cost ) ; return DAG . getNode ( Opc , Loc , VT , NegN0 , N1 , NegN2 , Flags ) ; } else if ( NegN1 ) { Cost = std :: min ( N1Cost , N2Cost ) ; return DAG . getNode ( Opc , Loc , VT , N0 , NegN1 , NegN2 , Flags ) ; } } if ( isOperationLegal ( ISD :: FMA , VT ) ) { Cost = N2Cost ; return DAG . getNode ( ISD :: FMA , Loc , VT , N0 , N1 , NegN2 , Flags ) ; } break ; } return TargetLowering :: getNegatedExpression ( Op , DAG , LegalOps , OptForSize , Cost , Depth ) ; } </s>

Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate that if it is cheaper or neutral to do the negation .


<s> bool runOnMachineFunction ( MachineFunction & MF ) { if ( ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ) { return false ; } const GBZ80Subtarget & STI = MF . getSubtarget < GBZ80Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; MachineBasicBlock & EntryMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = EntryMBB . begin ( ) ; DebugLoc DL = EntryMBB . findDebugLoc ( MBBI ) ; unsigned SPCopy = MF . getRegInfo ( ) . createVirtualRegister ( & GB :: DREGSRegClass ) ; BuildMI ( EntryMBB , MBBI , DL , TII . get ( GB :: COPY ) , SPCopy ) . addReg ( GB :: SP ) ; for ( MachineBasicBlock & MBB : MF ) { if ( ! MBB . empty ( ) && MBB . back ( ) . isReturn ( ) ) { MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( GB :: COPY ) , GB :: SP ) . addReg ( SPCopy , RegState :: Kill ) ; } } return true ; } </s>

GBZ80 GB GB GB::DREGSRegClass GB::COPY GB::SP GB::COPY GB::SP


<s> std :: vector < MachineBasicBlock * > & getBlocksVector ( ) { return Blocks ; } </s>

Return a direct , mutable handle to the blocks vector so that we can mutate it efficiently with techniques like std : :remove .


<s> bool X86FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const X86RegisterInfo * RegInfo = static_cast < const X86RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; unsigned SlotSize = RegInfo -> getSlotSize ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned CalleeSavedFrameSize = 0 ; int SpillSlotOffset = getOffsetOfLocalArea ( ) + X86FI -> getTCReturnAddrDelta ( ) ; if ( hasFP ( MF ) ) { SpillSlotOffset -= SlotSize ; MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; unsigned FPReg = RegInfo -> getFrameRegister ( MF ) ; for ( unsigned i = 0 ; i < CSI . size ( ) ; ++ i ) { if ( CSI [ i ] . getReg ( ) == FPReg ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - 1 ] . setFrameIdx ( SlotIndex ) ; } X86FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = RegInfo -> getMinimalPhysRegClass ( Reg ) ; SpillSlotOffset -= abs ( SpillSlotOffset ) % RC -> getAlignment ( ) ; SpillSlotOffset -= RC -> getSize ( ) ; int SlotIndex = MFI -> CreateFixedSpillStackObject ( RC -> getSize ( ) , SpillSlotOffset ) ; CSI [ i - 1 ] . setFrameIdx ( SlotIndex ) ; MFI -> ensureMaxAlignment ( RC -> getAlignment ( ) ) ; } return true ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s>
SDValue
NVPTXTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
)
const
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
Type
*
RetTy
=
MF
.
getFunction
(
)
->
getReturnType
(
)
;
bool
isABI
=
(
STI
.
getSmVersion
(
)
>=
20
)
;
assert
(
isABI
&&
"Non-ABI compilation is not supported"
)
;
if
(
!
isABI
)
return
Chain
;
const
DataLayout
DL
=
DAG
.
getDataLayout
(
)
;
SmallVector
<
EVT
,
16
>
VTs
;
SmallVector
<
uint64_t
,
16
>
Offsets
;
ComputePTXValueVTs
(
*
this
,
DL
,
RetTy
,
VTs
,
&
Offsets
)
;
assert
(
VTs
.
size
(
)
==
OutVals
.
size
(
)
&&
"Bad return value decomposition"
)
;
auto
VectorInfo
=
VectorizePTXValueVTs
(
VTs
,
Offsets
,
RetTy
->
isSized
(
)
DL
.
getABITypeAlignment
(
RetTy
)
:
1
)
;
bool
ExtendIntegerRetVal
=
RetTy
->
isIntegerTy
(
)
&&
DL
.
getTypeAllocSizeInBits
(
RetTy
)
<
32
;
SmallVector
<
SDValue
,
6
>
StoreOperands
;
for
(
unsigned
i
=
0
,
e
=
VTs
.
size
(
)
;
i
!=
e
;
++
i
)
{
if
(
VectorInfo
[
i
]
&
PVF_FIRST
)
{
assert
(
StoreOperands
.
empty
(
)
&&
"Orphaned operand list."
)
;
StoreOperands
.
push_back
(
Chain
)
;
StoreOperands
.
push_back
(
DAG
.
getConstant
(
Offsets
[
i
]
,
dl
,
MVT
::
i32
)
)
;
}
SDValue
RetVal
=
OutVals
[
i
]
;
if
(
ExtendIntegerRetVal
)
{
RetVal
=
DAG
.
getNode
(
Outs
[
i
]
.
Flags
.
isSExt
(
)
ISD
::
SIGN_EXTEND
:
ISD
::
ZERO_EXTEND
,
dl
,
MVT
::
i32
,
RetVal
)
;
}
else
if
(
RetVal
.
getValueSizeInBits
(
)
<
16
)
{
RetVal
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
dl
,
MVT
::
i16
,
RetVal
)
;
}
StoreOperands
.
push_back
(
RetVal
)
;
if
(
VectorInfo
[
i
]
&
PVF_LAST
)
{
NVPTXISD
::
NodeType
Op
;
unsigned
NumElts
=
StoreOperands
.
size
(
)
2
;
switch
(
NumElts
)
{
case
1
:
Op
=
NVPTXISD
::
StoreRetval
;
break
;
case
2
:
Op
=
NVPTXISD
::
StoreRetvalV2
;
break
;
case
4
:
Op
=
NVPTXISD
::
StoreRetvalV4
;
break
;
default
:
llvm_unreachable
(
"Invalid vector info."
)
;
}
EVT
TheStoreType
=
ExtendIntegerRetVal
MVT
::
i32
:
VTs
[
i
]
;
Chain
=
DAG
.
getMemIntrinsicNode
(
Op
,
dl
,
DAG
.
getVTList
(
MVT
::
Other
)
,
StoreOperands
,
TheStoreType
,
MachinePointerInfo
(
)
,
1
)
;
StoreOperands
.
clear
(
)
;
}
}
return
DAG
.
getNode
(
NVPTXISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>


<s>
void
BPFAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
if
(
Fixup
.
getKind
(
)
==
FK_SecRel_8
)
{
assert
(
Value
<=
UINT32_MAX
)
;
support
::
endian
::
write
<
uint32_t
>
(
&
Data
[
Fixup
.
getOffset
(
)
+
4
]
,
static_cast
<
uint32_t
>
(
Value
)
,
Endian
)
;
}
else
if
(
Fixup
.
getKind
(
)
==
FK_Data_4
)
{
support
::
endian
::
write
<
uint32_t
>
(
&
Data
[
Fixup
.
getOffset
(
)
]
,
Value
,
Endian
)
;
}
else
if
(
Fixup
.
getKind
(
)
==
FK_Data_8
)
{
support
::
endian
::
write
<
uint64_t
>
(
&
Data
[
Fixup
.
getOffset
(
)
]
,
Value
,
Endian
)
;
}
else
if
(
Fixup
.
getKind
(
)
==
FK_PCRel_4
)
{
Value
=
(
uint32_t
)
(
(
Value
8
)
/
8
)
;
if
(
Endian
==
support
::
little
)
{
Data
[
Fixup
.
getOffset
(
)
+
1
]
=
0x10
;
support
::
endian
::
write32le
(
&
Data
[
Fixup
.
getOffset
(
)
+
4
]
,
Value
)
;
}
else
{
Data
[
Fixup
.
getOffset
(
)
+
1
]
=
0x1
;
support
::
endian
::
write32be
(
&
Data
[
Fixup
.
getOffset
(
)
+
4
]
,
Value
)
;
}
}
else
{
assert
(
Fixup
.
getKind
(
)
==
FK_PCRel_2
)
;
int64_t
ByteOff
=
(
int64_t
)
Value
8
;
if
(
ByteOff
>
INT16_MAX
*
8
||
ByteOff
<
INT16_MIN
*
8
)
report_fatal_error
(
"Branch target out of insn range"
)
;
Value
=
(
uint16_t
)
(
(
Value
8
)
/
8
)
;
support
::
endian
::
write
<
uint16_t
>
(
&
Data
[
Fixup
.
getOffset
(
)
+
2
]
,
Value
,
Endian
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> virtual MVT getScalarShiftAmountTy ( EVT LHSTy ) const { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


"empty class %qT parameter passing ABI "


"Unable to get the legal offset for nil instruction."

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


"the default AIX Altivec ABI is not yet "


<s> void ARM64BranchRelaxation :: verify ( ) { unsigned PrevNum = MF -> begin ( ) -> getNumber ( ) ; for ( MachineBasicBlock & MBB : * MF ) { unsigned Align = MBB . getAlignment ( ) ; unsigned Num = MBB . getNumber ( ) ; assert ( BlockInfo [ Num ] . Offset % ( 1u << Align ) == 0 ) ; assert ( ! Num || BlockInfo [ PrevNum ] . postOffset ( ) <= BlockInfo [ Num ] . Offset ) ; PrevNum = Num ; } } </s>


<s> void altivec_expand_stvx_be ( rtx op0 , rtx op1 , machine_mode mode , unsigned unspec ) { rtx tmp = gen_reg_rtx ( mode ) ; rtx store = gen_rtx_SET ( VOIDmode , op0 , tmp ) ; rtx stvx = gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , const0_rtx ) , unspec ) ; rtx par = gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , store , stvx ) ) ; rtx sel = swap_selector_for_mode ( mode ) ; rtx vperm ; gcc_assert ( REG_P ( op1 ) ) ; vperm = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , op1 , op1 , sel ) , UNSPEC_VPERM ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , vperm ) ) ; emit_insn ( par ) ; } </s>

Generate code for a `` stvx '' or `` stvxl '' built-in for a little endian target with -maltivec=be specified . Issue the store preceded by an element-reversing permute .


"Hexagon remove redundant zero and size extends"

getPassName - Return a nice clean name for a pass .


<s> bool PPCInstrInfo :: isAssociativeAndCommutative ( const MachineInstr & Inst ) const { switch ( Inst . getOpcode ( ) ) { case PPC :: FADD : case PPC :: FADDS : case PPC :: FMUL : case PPC :: FMULS : case PPC :: VADDFP : case PPC :: XSADDDP : case PPC :: XVADDDP : case PPC :: XVADDSP : case PPC :: XSADDSP : case PPC :: XSMULDP : case PPC :: XVMULDP : case PPC :: XVMULSP : case PPC :: XSMULSP : case PPC :: QVFADD : case PPC :: QVFADDS : case PPC :: QVFADDSs : case PPC :: QVFMUL : case PPC :: QVFMULS : case PPC :: QVFMULSs : return Inst . getFlag ( MachineInstr :: MIFlag :: FmReassoc ) && Inst . getFlag ( MachineInstr :: MIFlag :: FmNsz ) ; default : return false ; } } </s>

Return true when \P Inst is both associative and commutative .

PowerPC PPC PPC::FADD PPC::FADDS PPC::FMUL PPC::FMULS PPC::VADDFP PPC::XSADDDP PPC::XVADDDP PPC::XVADDSP PPC::XSADDSP PPC::XSMULDP PPC::XVMULDP PPC::XVMULSP PPC::XSMULSP PPC::QVFADD PPC::QVFADDS PPC::QVFADDSs PPC::QVFMUL PPC::QVFMULS PPC::QVFMULSs


<s> const uint16_t * TLCS900RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const TargetFrameLowering * TFI = MF -> getTarget ( ) . getFrameLowering ( ) ; const Function * F = MF -> getFunction ( ) ; static const uint16_t CalleeSavedRegs [ ] = { TLCS900 :: FPW , TLCS900 :: R5W , TLCS900 :: R6W , TLCS900 :: R7W , TLCS900 :: R8W , TLCS900 :: R9W , TLCS900 :: R10W , TLCS900 :: R11W , 0 } ; static const uint16_t CalleeSavedRegsFP [ ] = { TLCS900 :: R5W , TLCS900 :: R6W , TLCS900 :: R7W , TLCS900 :: R8W , TLCS900 :: R9W , TLCS900 :: R10W , TLCS900 :: R11W , 0 } ; static const uint16_t CalleeSavedRegsIntr [ ] = { TLCS900 :: FPW , TLCS900 :: R5W , TLCS900 :: R6W , TLCS900 :: R7W , TLCS900 :: R8W , TLCS900 :: R9W , TLCS900 :: R10W , TLCS900 :: R11W , TLCS900 :: R12W , TLCS900 :: R13W , TLCS900 :: R14W , TLCS900 :: R15W , 0 } ; static const uint16_t CalleeSavedRegsIntrFP [ ] = { TLCS900 :: R5W , TLCS900 :: R6W , TLCS900 :: R7W , TLCS900 :: R8W , TLCS900 :: R9W , TLCS900 :: R10W , TLCS900 :: R11W , TLCS900 :: R12W , TLCS900 :: R13W , TLCS900 :: R14W , TLCS900 :: R15W , 0 } ; if ( TFI -> hasFP ( * MF ) ) return ( F -> getCallingConv ( ) == CallingConv :: TLCS900_INTR ? CalleeSavedRegsIntrFP : CalleeSavedRegsFP ) ; else return ( F -> getCallingConv ( ) == CallingConv :: TLCS900_INTR ? CalleeSavedRegsIntr : CalleeSavedRegs ) ; } </s>


<s> static unsigned selectBinaryOp ( unsigned GenericOpc , unsigned RegBankID , unsigned OpSize ) { switch ( RegBankID ) { case AArch64 :: GPRRegBankID : if ( OpSize == 32 ) { switch ( GenericOpc ) { case TargetOpcode :: G_SHL : return AArch64 :: LSLVWr ; case TargetOpcode :: G_LSHR : return AArch64 :: LSRVWr ; case TargetOpcode :: G_ASHR : return AArch64 :: ASRVWr ; default : return GenericOpc ; } } else if ( OpSize == 64 ) { switch ( GenericOpc ) { case TargetOpcode :: G_PTR_ADD : return AArch64 :: ADDXrr ; case TargetOpcode :: G_SHL : return AArch64 :: LSLVXr ; case TargetOpcode :: G_LSHR : return AArch64 :: LSRVXr ; case TargetOpcode :: G_ASHR : return AArch64 :: ASRVXr ; default : return GenericOpc ; } } break ; case AArch64 :: FPRRegBankID : switch ( OpSize ) { case 32 : switch ( GenericOpc ) { case TargetOpcode :: G_FADD : return AArch64 :: FADDSrr ; case TargetOpcode :: G_FSUB : return AArch64 :: FSUBSrr ; case TargetOpcode :: G_FMUL : return AArch64 :: FMULSrr ; case TargetOpcode :: G_FDIV : return AArch64 :: FDIVSrr ; default : return GenericOpc ; } case 64 : switch ( GenericOpc ) { case TargetOpcode :: G_FADD : return AArch64 :: FADDDrr ; case TargetOpcode :: G_FSUB : return AArch64 :: FSUBDrr ; case TargetOpcode :: G_FMUL : return AArch64 :: FMULDrr ; case TargetOpcode :: G_FDIV : return AArch64 :: FDIVDrr ; case TargetOpcode :: G_OR : return AArch64 :: ORRv8i8 ; default : return GenericOpc ; } } break ; } return GenericOpc ; } </s>

Select and emit code for a binary operator instruction , which has an opcode which directly corresponds to the given ISD opcode .


<s> static rtx frv_alloc_temp_reg ( frv_tmp_reg_t * info , enum reg_class rclass , machine_mode mode , int mark_as_used , int no_abort ) { int regno = info -> next_reg [ ( int ) rclass ] ; int orig_regno = regno ; HARD_REG_SET * reg_in_class = & reg_class_contents [ ( int ) rclass ] ; int i , nr ; for ( ; ; ) { if ( TEST_HARD_REG_BIT ( * reg_in_class , regno ) && TEST_HARD_REG_BIT ( info -> regs , regno ) ) break ; if ( ++ regno >= FIRST_PSEUDO_REGISTER ) regno = 0 ; if ( regno == orig_regno ) { gcc_assert ( no_abort ) ; return NULL_RTX ; } } nr = hard_regno_nregs ( regno , mode ) ; info -> next_reg [ ( int ) rclass ] = regno + nr ; if ( mark_as_used ) for ( i = 0 ; i < nr ; i ++ ) CLEAR_HARD_REG_BIT ( info -> regs , regno + i ) ; return gen_rtx_REG ( mode , regno ) ; } </s>

Return the next available temporary register in a given class .


<s> bool sparc_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { enum mode_class mclass1 , mclass2 ; unsigned short size1 , size2 ; if ( mode1 == mode2 ) return true ; mclass1 = GET_MODE_CLASS ( mode1 ) ; mclass2 = GET_MODE_CLASS ( mode2 ) ; if ( mclass1 != mclass2 ) return false ; if ( ! TARGET_V9 ) return true ; if ( mclass1 != MODE_FLOAT && mclass1 != MODE_VECTOR_INT ) return true ; size1 = GET_MODE_SIZE ( mode1 ) ; size2 = GET_MODE_SIZE ( mode2 ) ; if ( ( size1 > 4 && size2 == 4 ) || ( size2 > 4 && size1 == 4 ) ) return false ; return true ; } </s>

Return TRUE if it is a good idea to tie two pseudo registers when one has mode MODE1 and one has mode MODE2 . If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2 , for any hard reg , then this must be FALSE for correct output . For V9 we have to deal with the fact that only the lower 32 floating point registers are 32-bit addressable .


<s>
void
WebAssemblyAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
DEBUG
(
dbgs
(
)
<<
"EmitInstruction: "
<<
*
MI
<<
'\n'
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
WebAssembly
::
ARGUMENT_I32
:
case
WebAssembly
::
ARGUMENT_I64
:
case
WebAssembly
::
ARGUMENT_F32
:
case
WebAssembly
::
ARGUMENT_F64
:
break
;
case
WebAssembly
::
FALLTHROUGH_RETURN_I32
:
case
WebAssembly
::
FALLTHROUGH_RETURN_I64
:
case
WebAssembly
::
FALLTHROUGH_RETURN_F32
:
case
WebAssembly
::
FALLTHROUGH_RETURN_F64
:
{
assert
(
MFI
->
isVRegStackified
(
MI
->
getOperand
(
0
)
.
getReg
(
)
)
)
;
if
(
isVerbose
(
)
)
{
OutStreamer
->
AddComment
(
"fallthrough-return: $pop"
+
utostr
(
MFI
->
getWARegStackId
(
MFI
->
getWAReg
(
MI
->
getOperand
(
0
)
.
getReg
(
)
)
)
)
)
;
OutStreamer
->
AddBlankLine
(
)
;
}
break
;
}
case
WebAssembly
::
FALLTHROUGH_RETURN_VOID
:
if
(
isVerbose
(
)
)
{
OutStreamer
->
AddComment
(
"fallthrough-return"
)
;
OutStreamer
->
AddBlankLine
(
)
;
}
break
;
default
:
{
WebAssemblyMCInstLower
MCInstLowering
(
OutContext
,
*
this
)
;
MCInst
TmpInst
;
MCInstLowering
.
Lower
(
MI
,
TmpInst
)
;
EmitToStreamer
(
*
OutStreamer
,
TmpInst
)
;
break
;
}
}
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void AlphaInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; BuildMI ( MBB , MI , DL , get ( Alpha :: BISr ) , Alpha :: R31 ) . addReg ( Alpha :: R31 ) . addReg ( Alpha :: R31 ) ; } </s>

Insert a noop into the instruction stream at the specified point .


<s>
MipsSubtarget
::
MipsSubtarget
(
const
std
::
string
&
TT
,
const
std
::
string
&
CPU
,
const
std
::
string
&
FS
,
bool
little
)
:
MipsGenSubtargetInfo
(
TT
,
CPU
,
FS
)
,
MipsArchVersion
(
Mips32
)
,
MipsABI
(
UnknownABI
)
,
IsLittle
(
little
)
,
IsSingleFloat
(
false
)
,
IsFP64bit
(
false
)
,
IsGP64bit
(
false
)
,
HasVFPU
(
false
)
,
IsLinux
(
true
)
,
HasSEInReg
(
false
)
,
HasCondMov
(
false
)
,
HasMulDivAdd
(
false
)
,
HasMinMax
(
false
)
,
HasSwap
(
false
)
,
HasBitCount
(
false
)
{
std
::
string
CPUName
=
CPU
;
if
(
CPUName
.
empty
(
)
)
CPUName
=
"mips32r1"
;
ParseSubtargetFeatures
(
CPUName
,
FS
)
;
InstrItins
=
getInstrItineraryForCPU
(
CPUName
)
;
if
(
MipsABI
==
UnknownABI
)
MipsABI
=
hasMips64
(
)
N64
:
O32
;
assert
(
(
(
!
hasMips64
(
)
&&
(
isABI_O32
(
)
||
isABI_EABI
(
)
)
)
||
(
hasMips64
(
)
&&
(
isABI_N32
(
)
||
isABI_N64
(
)
)
)
)
&&
"Invalid  Arch & ABI pair."
)
;
if
(
TT
.
find
(
"linux"
)
==
std
::
string
::
npos
)
IsLinux
=
false
;
}
</s>

This constructor initializes the data members to match that of the specified triple .

Mips
Mips
Mips
Mips
Mips
Mips
Mips
"mips32r1"
Mips
Mips
Mips
Mips
Mips
"Invalid  Arch & ABI pair."
"linux"


<s>
const
char
*
getPassName
(
)
const
override
{
return
"HSAIL Assembly Printer"
;
}
</s>


<s> const char * SystemZTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { OPCODE ( RET_FLAG ) ; OPCODE ( CALL ) ; OPCODE ( PCREL_WRAPPER ) ; OPCODE ( CMP ) ; OPCODE ( UCMP ) ; OPCODE ( BR_CCMASK ) ; OPCODE ( SELECT_CCMASK ) ; OPCODE ( ADJDYNALLOC ) ; OPCODE ( EXTRACT_ACCESS ) ; OPCODE ( UMUL_LOHI64 ) ; OPCODE ( SDIVREM64 ) ; OPCODE ( UDIVREM32 ) ; OPCODE ( UDIVREM64 ) ; OPCODE ( MVC ) ; OPCODE ( ATOMIC_SWAPW ) ; OPCODE ( ATOMIC_LOADW_ADD ) ; OPCODE ( ATOMIC_LOADW_SUB ) ; OPCODE ( ATOMIC_LOADW_AND ) ; OPCODE ( ATOMIC_LOADW_OR ) ; OPCODE ( ATOMIC_LOADW_XOR ) ; OPCODE ( ATOMIC_LOADW_NAND ) ; OPCODE ( ATOMIC_LOADW_MIN ) ; OPCODE ( ATOMIC_LOADW_MAX ) ; OPCODE ( ATOMIC_LOADW_UMIN ) ; OPCODE ( ATOMIC_LOADW_UMAX ) ; OPCODE ( ATOMIC_CMP_SWAPW ) ; } return NULL ; } </s>

getTargetNodeName - This method returns the name of a target specific


"only register based stack limit is supported"

Emit conditional trap for checking stack limit .


<s> void GBZ80PassConfig :: addPostRegAlloc ( ) { addPass ( createGBZ80PostRAPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> void XCoreFrameInfo :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const { } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> void M68kAsmPrinter :: emitFunctionBodyEnd ( ) { } </s>

Targets can override this to emit stuff after the last basic block in the function .


<s> bool canMergeStoresTo ( unsigned AddressSpace , EVT MemVT , const MachineFunction & MF ) const override { return ( MemVT . getSizeInBits ( ) <= 32 ) ; } </s>

Returns if it 's reasonable to merge stores to MemVT size .


<s> static void riscv_function_arg_advance ( cumulative_args_t cum_v , enum machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; struct riscv_arg_info info ; riscv_get_arg_info ( & info , cum , mode , type , named , false ) ; cum -> num_fprs = info . fpr_offset + info . num_fprs ; cum -> num_gprs = info . gpr_offset + info . num_gprs ; } </s>


<s> bool X86PassConfig :: addPreEmitPass ( ) { bool ShouldPrint = false ; if ( getOptLevel ( ) != CodeGenOpt :: None && getX86Subtarget ( ) . hasSSE2 ( ) ) { addPass ( createExecutionDependencyFixPass ( & X86 :: VR128RegClass ) ) ; ShouldPrint = true ; } if ( getX86Subtarget ( ) . hasAVX ( ) && UseVZeroUpper ) { addPass ( createX86IssueVZeroUpperPass ( ) ) ; ShouldPrint = true ; } return ShouldPrint ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> int GCNTTIImpl :: getIntrinsicInstrCost ( Intrinsic :: ID ID , Type * RetTy , ArrayRef < T * > Args , FastMathFlags FMF , unsigned VF , const Instruction * I ) { if ( ! intrinsicHasPackedVectorBenefit ( ID ) ) return BaseT :: getIntrinsicInstrCost ( ID , RetTy , Args , FMF , VF , I ) ; EVT OrigTy = TLI -> getValueType ( DL , RetTy ) ; if ( ! OrigTy . isSimple ( ) ) { return BaseT :: getIntrinsicInstrCost ( ID , RetTy , Args , FMF , VF , I ) ; } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; unsigned NElts = LT . second . isVector ( ) ? LT . second . getVectorNumElements ( ) : 1 ; MVT :: SimpleValueType SLT = LT . second . getScalarType ( ) . SimpleTy ; if ( SLT == MVT :: f64 ) return LT . first * NElts * get64BitInstrCost ( ) ; if ( ST -> has16BitInsts ( ) && SLT == MVT :: f16 ) NElts = ( NElts + 1 ) / 2 ; unsigned InstRate = getQuarterRateInstrCost ( ) ; if ( ID == Intrinsic :: fma ) { InstRate = ST -> hasFastFMAF32 ( ) ? getHalfRateInstrCost ( ) : getQuarterRateInstrCost ( ) ; } return LT . first * NElts * InstRate ; } </s>


<s> bool NVPTXPrologEpilogPass :: runOnMachineFunction ( MachineFunction & MF ) { const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const TargetFrameLowering & TFI = * STI . getFrameLowering ( ) ; const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; bool Modified = false ; calculateFrameObjectOffsets ( MF ) ; for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) { for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ++ I ) { MachineInstr * MI = I ; for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( ! MI -> getOperand ( i ) . isFI ( ) ) continue ; TRI . eliminateFrameIndex ( MI , 0 , i , nullptr ) ; Modified = true ; } } } TFI . emitPrologue ( MF , MF . front ( ) ) ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( I -> isReturnBlock ( ) ) TFI . emitEpilogue ( MF , * I ) ; } return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> int AMDGPUFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; FrameReg = RI -> getFrameRegister ( MF ) ; unsigned OffsetBytes = 2 * ( getStackWidth ( MF ) * 4 ) ; int UpperBound = FI == - 1 ? MFI -> getNumObjects ( ) : FI ; for ( int i = MFI -> getObjectIndexBegin ( ) ; i < UpperBound ; ++ i ) { OffsetBytes = alignTo ( OffsetBytes , MFI -> getObjectAlignment ( i ) ) ; OffsetBytes += MFI -> getObjectSize ( i ) ; OffsetBytes = alignTo ( OffsetBytes , 4 ) ; } if ( FI != - 1 ) OffsetBytes = alignTo ( OffsetBytes , MFI -> getObjectAlignment ( FI ) ) ; return OffsetBytes / ( getStackWidth ( MF ) * 4 ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s>
static
MCSymbol
*
GetSymbolFromOperand
(
const
MachineOperand
&
MO
,
AsmPrinter
&
AP
)
{
const
TargetMachine
&
TM
=
AP
.
TM
;
Mangler
*
Mang
=
AP
.
Mang
;
const
DataLayout
&
DL
=
AP
.
getDataLayout
(
)
;
MCContext
&
Ctx
=
AP
.
OutContext
;
bool
isDarwin
=
TM
.
getTargetTriple
(
)
.
isOSDarwin
(
)
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
)
{
if
(
isDarwin
)
Suffix
=
"$stub"
;
}
else
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
Suffix
=
"$non_lazy_ptr"
;
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
.
getPrivateGlobalPrefix
(
)
;
unsigned
PrefixLen
=
Name
.
size
(
)
;
if
(
!
MO
.
isGlobal
(
)
)
{
assert
(
MO
.
isSymbol
(
)
&&
"Isn't a symbol reference"
)
;
Mangler
::
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
,
DL
)
;
}
else
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
TM
.
getNameWithPrefix
(
Name
,
GV
,
*
Mang
)
;
}
unsigned
OrigLen
=
Name
.
size
(
)
PrefixLen
;
Name
+=
Suffix
;
MCSymbol
*
Sym
=
Ctx
.
getOrCreateSymbol
(
Name
)
;
StringRef
OrigName
=
StringRef
(
Name
)
.
substr
(
PrefixLen
,
OrigLen
)
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
&&
isDarwin
)
{
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
getMachOMMI
(
AP
)
.
getFnStubEntry
(
Sym
)
;
if
(
StubSym
.
getPointer
(
)
)
return
Sym
;
if
(
MO
.
isGlobal
(
)
)
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
else
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
Ctx
.
getOrCreateSymbol
(
OrigName
)
,
false
)
;
}
return
Sym
;
}
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
{
MachineModuleInfoMachO
&
MachO
=
getMachOMMI
(
AP
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
MachO
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
return
Sym
;
}
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


This routine handles output of long unconditional branches that exceed the maximum range of a simple branch instruction . Since we do n't have a register available for the branch , we save register % r1 in the frame marker , load the branch destination DEST into % r1 , execute the branch , and restore % r1 in the delay slot of the branch . Since long branches may have an insn in the delay slot and the delay slot is used to restore % r1 , we in general need to extract this insn and execute it before the branch . However , to facilitate use of this function by conditional branches , we also provide an option to not extract the delay insn so that it will be emitted after the long branch . So , if there is an insn in the delay slot , it is extracted if XDELAY is nonzero . The lengths of the various long-branch sequences are 20 , 16 and 24 bytes for the portable runtime , non-PIC and PIC cases , respectively .


<s> StringRef getPassName ( ) const override { return "AArch64PreLegalizerCombiner" ; } </s>

getPassName - Return a nice clean name for a pass .


<s> const char * thumb1_output_casesi ( rtx * operands ) { rtx diff_vec = PATTERN ( NEXT_INSN ( as_a < rtx_insn * > ( operands [ 0 ] ) ) ) ; gcc_assert ( GET_CODE ( diff_vec ) == ADDR_DIFF_VEC ) ; switch ( GET_MODE ( diff_vec ) ) { case QImode : return ( ADDR_DIFF_VEC_FLAGS ( diff_vec ) . offset_unsigned ? "bl\t%___gnu_thumb1_case_uqi" : "bl\t%___gnu_thumb1_case_sqi" ) ; case HImode : return ( ADDR_DIFF_VEC_FLAGS ( diff_vec ) . offset_unsigned ? "bl\t%___gnu_thumb1_case_uhi" : "bl\t%___gnu_thumb1_case_shi" ) ; case SImode : return "bl\t%___gnu_thumb1_case_si" ; default : gcc_unreachable ( ) ; } } </s>

Output a Thumb-1 casesi dispatch sequence .


<s> void GCNTTIImpl :: getPeelingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: PeelingPreferences & PP ) { CommonTTI . getPeelingPreferences ( L , SE , PP ) ; } </s>

Get target-customized preferences for the generic loop peeling transformation .


<s> int label_mentioned_p ( rtx x ) { const char * fmt ; int i ; if ( LABEL_REF_P ( x ) ) return 1 ; if ( GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNSPEC_TLS ) return 0 ; fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( x , i ) - 1 ; j >= 0 ; j -- ) if ( label_mentioned_p ( XVECEXP ( x , i , j ) ) ) return 1 ; } else if ( fmt [ i ] == 'e' && label_mentioned_p ( XEXP ( x , i ) ) ) return 1 ; } return 0 ; } </s>

Return TRUE if X references a LABEL_REF .


<s> static void add_pop_cfi_notes ( rtx_insn * insn , unsigned int high , unsigned int low ) { rtx t = plus_constant ( Pmode , stack_pointer_rtx , ( high - low + 1 ) * UNITS_PER_WORD ) ; t = gen_rtx_SET ( stack_pointer_rtx , t ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , t ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; for ( unsigned int i = low ; i <= high ; i ++ ) add_reg_note ( insn , REG_CFA_RESTORE , gen_rtx_REG ( word_mode , i ) ) ; } </s>


<s> uint32_t BTFDebug :: addType ( std :: unique_ptr < BTFTypeBase > TypeEntry , const DIType * Ty ) { TypeEntry -> setId ( TypeEntries . size ( ) + 1 ) ; uint32_t Id = TypeEntry -> getId ( ) ; DIToIdMap [ Ty ] = Id ; TypeEntries . push_back ( std :: move ( TypeEntry ) ) ; return Id ; } </s>

Add a new type attribute to the specified entity .


<s> bool AVRFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return hasFP ( MF ) && ! MFI . hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s>
const
char
*
getPassName
(
)
const
{
return
"Hexagon Split TFRCondSets"
;
}
</s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"PPC Lower MASS Entries"
;
}
</s>


<s> const SDValue & getMask ( ) const { return getOperand ( 3 ) ; } </s>


<s> bool AMDGPUCodeGenPrepare :: doInitialization ( Module & M ) { return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> static void split_quadword_operands ( rtx insn , enum rtx_code code , rtx * operands , rtx * low , int n ) { int i ; for ( i = 0 ; i < n ; i ++ ) low [ i ] = 0 ; for ( i = 0 ; i < n ; i ++ ) { if ( MEM_P ( operands [ i ] ) && ( GET_CODE ( XEXP ( operands [ i ] , 0 ) ) == PRE_DEC || GET_CODE ( XEXP ( operands [ i ] , 0 ) ) == POST_INC ) ) { rtx addr = XEXP ( operands [ i ] , 0 ) ; operands [ i ] = low [ i ] = gen_rtx_MEM ( SImode , addr ) ; } else if ( optimize_size && MEM_P ( operands [ i ] ) && REG_P ( XEXP ( operands [ i ] , 0 ) ) && ( code != MINUS || operands [ 1 ] != const0_rtx ) && find_regno_note ( insn , REG_DEAD , REGNO ( XEXP ( operands [ i ] , 0 ) ) ) ) { low [ i ] = gen_rtx_MEM ( SImode , gen_rtx_POST_INC ( Pmode , XEXP ( operands [ i ] , 0 ) ) ) ; operands [ i ] = gen_rtx_MEM ( SImode , XEXP ( operands [ i ] , 0 ) ) ; } else { low [ i ] = operand_subword ( operands [ i ] , 0 , 0 , DImode ) ; operands [ i ] = operand_subword ( operands [ i ] , 1 , 0 , DImode ) ; } } } </s>

This is like nonimmediate_operand with a restriction on the type of MEM .


<s> bool R600InstrInfo :: isPredicable ( MachineInstr & MI ) const { if ( MI . getOpcode ( ) == AMDGPU :: KILLGT ) { return false ; } else if ( MI . getOpcode ( ) == AMDGPU :: CF_ALU ) { if ( MI . getParent ( ) -> begin ( ) != MachineBasicBlock :: iterator ( MI ) ) return false ; return MI . getOperand ( 3 ) . getImm ( ) == 0 && MI . getOperand ( 4 ) . getImm ( ) == 0 ; } else if ( isVector ( MI ) ) { return false ; } else { return AMDGPUInstrInfo :: isPredicable ( MI ) ; } } </s>

Return true if the specified instruction can be predicated .


"Unknown fence ordering in emitLeadingFence"


<s>
bool
WaitInsert
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
!
MF
.
getFunction
(
)
.
hasFnAttribute
(
Attribute
::
StrictFP
)
)
return
false
;
const
X86Subtarget
&
ST
=
MF
.
getSubtarget
<
X86Subtarget
>
(
)
;
const
X86InstrInfo
*
TII
=
ST
.
getInstrInfo
(
)
;
bool
Changed
=
false
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
for
(
MachineBasicBlock
::
iterator
MI
=
MBB
.
begin
(
)
;
MI
!=
MBB
.
end
(
)
;
++
MI
)
{
if
(
!
X86
::
isX87Instruction
(
*
MI
)
)
continue
;
if
(
!
(
MI
->
mayRaiseFPException
(
)
||
MI
->
mayLoadOrStore
(
)
)
||
isX87ControlInstruction
(
*
MI
)
)
continue
;
MachineBasicBlock
::
iterator
AfterMI
=
std
::
next
(
MI
)
;
if
(
AfterMI
!=
MBB
.
end
(
)
&&
X86
::
isX87Instruction
(
*
AfterMI
)
&&
!
isX87NonWaitingControlInstruction
(
*
AfterMI
)
)
continue
;
BuildMI
(
MBB
,
AfterMI
,
MI
->
getDebugLoc
(
)
,
TII
->
get
(
X86
::
WAIT
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"\nInsert wait after:\t"
<<
*
MI
)
;
++
MI
;
Changed
=
true
;
}
}
return
Changed
;
}
</s>


<s> bool HexagonTargetLowering :: IsEligibleForTailCallOptimization ( SDValue Callee , CallingConv :: ID CalleeCC , bool isVarArg , bool isCalleeStructRet , bool isCallerStructRet , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SmallVectorImpl < ISD :: InputArg > & Ins , SelectionDAG & DAG ) const { const Function * CallerF = DAG . getMachineFunction ( ) . getFunction ( ) ; CallingConv :: ID CallerCC = CallerF -> getCallingConv ( ) ; bool CCMatch = CallerCC == CalleeCC ; if ( ! isa < GlobalAddressSDNode > ( Callee ) && ! isa < ExternalSymbolSDNode > ( Callee ) ) { return false ; } if ( ! CCMatch ) { bool R = ( CallerCC == CallingConv :: C || CallerCC == CallingConv :: Fast ) ; bool E = ( CalleeCC == CallingConv :: C || CalleeCC == CallingConv :: Fast ) ; if ( ! R || ! E ) return false ; } if ( isVarArg ) return false ; if ( isCalleeStructRet || isCallerStructRet ) return false ; return true ; } </s>

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization .

Hexagon Hexagon ISD::OutputArg ISD::InputArg


"%qs requires PowerPC64 architecture, enabling"

The Darwin version of SUBTARGET_OVERRIDE_OPTIONS .


<s> static bool s390_legitimate_constant_p ( machine_mode mode , rtx op ) { if ( TARGET_VX && VECTOR_MODE_P ( mode ) && GET_CODE ( op ) == CONST_VECTOR ) { if ( GET_MODE_SIZE ( mode ) != 16 ) return 0 ; if ( ! satisfies_constraint_j00 ( op ) && ! satisfies_constraint_jm1 ( op ) && ! satisfies_constraint_jKK ( op ) && ! satisfies_constraint_jxx ( op ) && ! satisfies_constraint_jyy ( op ) ) return 0 ; } if ( ! SYMBOLIC_CONST ( op ) ) return 1 ; if ( TARGET_CPU_ZARCH && larl_operand ( op , mode ) ) return 1 ; if ( TLS_SYMBOLIC_CONST ( op ) ) return 0 ; if ( flag_pic ) return 1 ; return 0 ; } </s>

Returns true if the constant value OP is a legitimate general operand . It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE .


<s> static std :: string toString ( const APFloat & FP ) { if ( FP . isNaN ( ) && ! FP . bitwiseIsEqual ( APFloat :: getQNaN ( FP . getSemantics ( ) ) ) && ! FP . bitwiseIsEqual ( APFloat :: getQNaN ( FP . getSemantics ( ) , true ) ) ) { APInt AI = FP . bitcastToAPInt ( ) ; return std :: string ( AI . isNegative ( ) ? "-" : "" ) + "nan:0x" + utohexstr ( AI . getZExtValue ( ) & ( AI . getBitWidth ( ) == 32 ? INT64_C ( 0x007fffff ) : INT64_C ( 0x000fffffffffffff ) ) , true ) ; } static const size_t BufBytes = 128 ; char Buf [ BufBytes ] ; auto Written = FP . convertToHexString ( Buf , 0 , false , APFloat :: rmNearestTiesToEven ) ; ( void ) Written ; assert ( Written != 0 ) ; assert ( Written < BufBytes ) ; return Buf ; } </s>

Convert to a decimal representation in a string .


<s> static bool m68k_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( DATA_REGNO_P ( regno ) ) { if ( regno + GET_MODE_SIZE ( mode ) / 4 <= 8 ) return true ; } else if ( ADDRESS_REGNO_P ( regno ) ) { if ( regno + GET_MODE_SIZE ( mode ) / 4 <= 16 ) return true ; } else if ( FP_REGNO_P ( regno ) ) { if ( ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) && GET_MODE_UNIT_SIZE ( mode ) <= TARGET_FP_REG_SIZE ) return true ; } return false ; } </s>

Implement TARGET_HARD_REGNO_MODE_OK . On the 68000 , we let the cpu registers can hold any mode , but restrict the 68881 registers to floating-point modes .


<s>
unsigned
ARMMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
)
const
{
if
(
MO
.
isReg
(
)
)
{
unsigned
Reg
=
MO
.
getReg
(
)
;
unsigned
RegNo
=
CTX
.
getRegisterInfo
(
)
.
getEncodingValue
(
Reg
)
;
switch
(
Reg
)
{
default
:
return
RegNo
;
case
ARM
::
Q0
:
case
ARM
::
Q1
:
case
ARM
::
Q2
:
case
ARM
::
Q3
:
case
ARM
::
Q4
:
case
ARM
::
Q5
:
case
ARM
::
Q6
:
case
ARM
::
Q7
:
case
ARM
::
Q8
:
case
ARM
::
Q9
:
case
ARM
::
Q10
:
case
ARM
::
Q11
:
case
ARM
::
Q12
:
case
ARM
::
Q13
:
case
ARM
::
Q14
:
case
ARM
::
Q15
:
return
2
*
RegNo
;
}
}
else
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
else
if
(
MO
.
isFPImm
(
)
)
{
return
static_cast
<
unsigned
>
(
APFloat
(
MO
.
getFPImm
(
)
)
.
bitcastToAPInt
(
)
.
getHiBits
(
32
)
.
getLimitedValue
(
)
)
;
}
llvm_unreachable
(
"Unable to encode MCOperand!"
)
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s>
const
uint32_t
*
RISCVRegisterInfo
::
getCallPreservedMask
(
const
MachineFunction
&
MF
,
CallingConv
::
ID
CC
)
const
{
auto
&
Subtarget
=
MF
.
getSubtarget
<
RISCVSubtarget
>
(
)
;
if
(
CC
==
CallingConv
::
GHC
)
return
CSR_NoRegs_RegMask
;
switch
(
Subtarget
.
getTargetABI
(
)
)
{
default
:
llvm_unreachable
(
"Unrecognized ABI"
)
;
case
RISCVABI
::
ABI_ILP32
:
case
RISCVABI
::
ABI_LP64
:
return
CSR_ILP32_LP64_RegMask
;
case
RISCVABI
::
ABI_IL32PC64
:
case
RISCVABI
::
ABI_L64PC128
:
return
CSR_IL32PC64_L64PC128_RegMask
;
case
RISCVABI
::
ABI_ILP32F
:
case
RISCVABI
::
ABI_LP64F
:
return
CSR_ILP32F_LP64F_RegMask
;
case
RISCVABI
::
ABI_IL32PC64F
:
case
RISCVABI
::
ABI_L64PC128F
:
return
CSR_IL32PC64F_L64PC128F_RegMask
;
case
RISCVABI
::
ABI_ILP32D
:
case
RISCVABI
::
ABI_LP64D
:
return
CSR_ILP32D_LP64D_RegMask
;
case
RISCVABI
::
ABI_IL32PC64D
:
case
RISCVABI
::
ABI_L64PC128D
:
return
CSR_IL32PC64D_L64PC128D_RegMask
;
}
}
</s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> Register R600RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return R600 :: NoRegister ; } </s>


Return the assembly code for INSN , which branches to OPERANDS [ 0 ] if some ordering condition is true . The condition is given by OPERANDS [ 1 ] if ! INVERTED_P , otherwise it is the inverse of OPERANDS [ 1 ] . OPERANDS [ 2 ] is the comparison 's first operand ; OPERANDS [ 3 ] is the second operand and may be zero or a register .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"SI annotate control flow"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool WinEHStatePass :: runOnFunction ( Function & F ) { if ( ! F . hasPersonalityFn ( ) ) return false ; PersonalityFn = dyn_cast < Function > ( F . getPersonalityFn ( ) -> stripPointerCasts ( ) ) ; if ( ! PersonalityFn ) return false ; Personality = classifyEHPersonality ( PersonalityFn ) ; if ( ! isFuncletEHPersonality ( Personality ) ) return false ; bool HasPads = false ; for ( BasicBlock & BB : F ) { if ( BB . isEHPad ( ) ) { HasPads = true ; break ; } } if ( ! HasPads ) return false ; Type * Int8PtrType = Type :: getInt8PtrTy ( TheModule -> getContext ( ) ) ; SetJmp3 = TheModule -> getOrInsertFunction ( "_setjmp3" , FunctionType :: get ( Type :: getInt32Ty ( TheModule -> getContext ( ) ) , { Int8PtrType , Type :: getInt32Ty ( TheModule -> getContext ( ) ) } , true ) ) ; F . addFnAttr ( "no-frame-pointer-elim" , "true" ) ; emitExceptionRegistrationRecord ( & F ) ; WinEHFuncInfo FuncInfo ; addStateStores ( F , FuncInfo ) ; PersonalityFn = nullptr ; Personality = EHPersonality :: Unknown ; UseStackGuard = false ; RegNode = nullptr ; EHGuardNode = nullptr ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static bool pa_scalar_mode_supported_p ( scalar_mode mode ) { int precision = GET_MODE_PRECISION ( mode ) ; if ( TARGET_64BIT && mode == TImode ) return true ; switch ( GET_MODE_CLASS ( mode ) ) { case MODE_PARTIAL_INT : case MODE_INT : if ( precision == CHAR_TYPE_SIZE ) return true ; if ( precision == SHORT_TYPE_SIZE ) return true ; if ( precision == INT_TYPE_SIZE ) return true ; if ( precision == LONG_TYPE_SIZE ) return true ; if ( precision == LONG_LONG_TYPE_SIZE ) return true ; return false ; case MODE_FLOAT : if ( precision == FLOAT_TYPE_SIZE ) return true ; if ( precision == DOUBLE_TYPE_SIZE ) return true ; if ( precision == LONG_DOUBLE_TYPE_SIZE ) return true ; return false ; case MODE_DECIMAL_FLOAT : return false ; default : gcc_unreachable ( ) ; } } </s>

True if MODE is valid for the target . By `` valid '' , we mean able to be manipulated in non-trivial ways . In particular , this means all the arithmetic is supported .


<s> void AMDGPUDAGToDAGISel :: PostprocessISelDAG ( ) { if ( Subtarget . getGeneration ( ) < AMDGPUSubtarget :: SOUTHERN_ISLANDS ) { return ; } const AMDGPUTargetLowering & Lowering = ( * ( const AMDGPUTargetLowering * ) TLI ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ++ I ) { SDNode * Node = I ; switch ( Node -> getOpcode ( ) ) { case ISD :: CopyToReg : { unsigned Reg = cast < RegisterSDNode > ( Node -> getOperand ( 1 ) ) -> getReg ( ) ; SDValue Val = Node -> getOperand ( 2 ) ; const TargetRegisterClass * RC = RegInfo -> getRegClass ( Reg ) ; if ( RC != & AMDGPU :: SReg_64RegClass ) { continue ; } if ( ! Val . getNode ( ) -> isMachineOpcode ( ) || Val . getNode ( ) -> getMachineOpcode ( ) == AMDGPU :: IMPLICIT_DEF ) { continue ; } const MCInstrDesc Desc = TM . getInstrInfo ( ) -> get ( Val . getNode ( ) -> getMachineOpcode ( ) ) ; const TargetRegisterInfo * TRI = TM . getRegisterInfo ( ) ; RegInfo -> setRegClass ( Reg , TRI -> getRegClass ( Desc . OpInfo [ 0 ] . RegClass ) ) ; continue ; } } MachineSDNode * MachineNode = dyn_cast < MachineSDNode > ( I ) ; if ( ! MachineNode ) continue ; SDNode * ResNode = Lowering . PostISelFolding ( MachineNode , * CurDAG ) ; if ( ResNode != Node ) { ReplaceUses ( Node , ResNode ) ; } } } </s>

PostprocessISelDAG ( ) - This hook allows the target to hack on the graph right after selection .


<s>
void
SPUInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
)
const
{
unsigned
opc
;
bool
isValidFrameIdx
=
(
FrameIdx
<
SPUFrameInfo
::
maxFrameOffset
(
)
)
;
if
(
RC
==
SPU
::
GPRCRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr128
:
SPU
::
STQXr128
)
;
}
else
if
(
RC
==
SPU
::
R64CRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr64
:
SPU
::
STQXr64
)
;
}
else
if
(
RC
==
SPU
::
R64FPRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr64
:
SPU
::
STQXr64
)
;
}
else
if
(
RC
==
SPU
::
R32CRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr32
:
SPU
::
STQXr32
)
;
}
else
if
(
RC
==
SPU
::
R32FPRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr32
:
SPU
::
STQXr32
)
;
}
else
if
(
RC
==
SPU
::
R16CRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr16
:
SPU
::
STQXr16
)
;
}
else
if
(
RC
==
SPU
::
R8CRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr8
:
SPU
::
STQXr8
)
;
}
else
if
(
RC
==
SPU
::
VECREGRegisterClass
)
{
opc
=
(
isValidFrameIdx
)
SPU
::
STQDv16i8
:
SPU
::
STQXv16i8
;
}
else
{
assert
(
0
&&
"Unknown regclass!"
)
;
abort
(
)
;
}
DebugLoc
DL
=
DebugLoc
::
getUnknownLoc
(
)
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
opc
)
)
.
addReg
(
SrcReg
,
false
,
false
,
isKill
)
,
FrameIdx
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s>
void
addExpr
(
MCInst
&
Inst
,
const
MCExpr
*
Expr
)
const
{
assert
(
Expr
&&
"Expr shouldn't be null!"
)
;
if
(
auto
*
CE
=
dyn_cast
<
MCConstantExpr
>
(
Expr
)
)
Inst
.
addOperand
(
MCOperand
::
createImm
(
CE
->
getValue
(
)
)
)
;
else
Inst
.
addOperand
(
MCOperand
::
createExpr
(
Expr
)
)
;
}
</s>


<s> int64_t getRegNo ( ) const { return RegNo ; } </s>

getSubExpr - Get the child of this expression .


<s> bool MLxExpansion :: runOnMachineFunction ( MachineFunction & Fn ) { TII = static_cast < const ARMBaseInstrInfo * > ( Fn . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; const ARMSubtarget * STI = & Fn . getSubtarget < ARMSubtarget > ( ) ; if ( ! STI -> isCortexA9 ( ) ) return false ; isLikeA9 = STI -> isLikeA9 ( ) || STI -> isSwift ( ) ; isSwift = STI -> isSwift ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : Fn ) Modified |= ExpandFPMLxInstructions ( MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> void AArch64PassConfig :: addPreGlobalInstructionSelect ( ) { addPass ( new Localizer ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before the ( global ) instruction selection .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s>
void
frv_expand_builtin_va_start
(
tree
valist
,
rtx
nextarg
)
{
tree
t
;
int
num
=
cfun
->
args_info
FIRST_ARG_REGNUM
FRV_NUM_ARG_REGS
;
nextarg
=
gen_rtx_PLUS
(
Pmode
,
virtual_incoming_args_rtx
,
GEN_INT
(
UNITS_PER_WORD
*
num
)
)
;
if
(
TARGET_DEBUG_ARG
)
{
fprintf
(
stderr
,
"va_start: args_info = %d, num = %d\n"
,
cfun
->
args_info
,
num
)
;
debug_rtx
(
nextarg
)
;
}
t
=
build
(
MODIFY_EXPR
,
TREE_TYPE
(
valist
)
,
valist
,
make_tree
(
ptr_type_node
,
nextarg
)
)
;
TREE_SIDE_EFFECTS
(
t
)
=
1
;
expand_expr
(
t
,
const0_rtx
,
VOIDmode
,
EXPAND_NORMAL
)
;
}
</s>

Expand __builtin_va_start to do the va_start macro .

frv
"va_start: args_info = %d, num = %d\n"
1


<s> static void csky_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain_value ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx mem , a_tramp ; int pool = TRAMPOLINE_SIZE - 8 ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp , SImode , pool ) ; emit_move_insn ( mem , chain_value ) ; mem = adjust_address ( m_tramp , SImode , pool + 4 ) ; emit_move_insn ( mem , fnaddr ) ; a_tramp = XEXP ( m_tramp , 0 ) ; maybe_emit_call_builtin___clear_cache ( a_tramp , plus_constant ( Pmode , a_tramp , TRAMPOLINE_SIZE ) ) ; } </s>

Worker function for TARGET_TRAMPOLINE_INIT .


<s> BitVector HexagonRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( Hexagon :: R29 ) ; Reserved . set ( Hexagon :: R30 ) ; Reserved . set ( Hexagon :: R31 ) ; Reserved . set ( Hexagon :: VTMP ) ; Reserved . set ( Hexagon :: SA0 ) ; Reserved . set ( Hexagon :: LC0 ) ; Reserved . set ( Hexagon :: SA1 ) ; Reserved . set ( Hexagon :: LC1 ) ; Reserved . set ( Hexagon :: P3_0 ) ; Reserved . set ( Hexagon :: USR ) ; Reserved . set ( Hexagon :: PC ) ; Reserved . set ( Hexagon :: UGP ) ; Reserved . set ( Hexagon :: GP ) ; Reserved . set ( Hexagon :: CS0 ) ; Reserved . set ( Hexagon :: CS1 ) ; Reserved . set ( Hexagon :: UPCYCLELO ) ; Reserved . set ( Hexagon :: UPCYCLEHI ) ; Reserved . set ( Hexagon :: FRAMELIMIT ) ; Reserved . set ( Hexagon :: FRAMEKEY ) ; Reserved . set ( Hexagon :: PKTCOUNTLO ) ; Reserved . set ( Hexagon :: PKTCOUNTHI ) ; Reserved . set ( Hexagon :: UTIMERLO ) ; Reserved . set ( Hexagon :: UTIMERHI ) ; Reserved . set ( Hexagon :: C8 ) ; Reserved . set ( Hexagon :: USR_OVF ) ; for ( int x = Reserved . find_first ( ) ; x >= 0 ; x = Reserved . find_next ( x ) ) markSuperRegs ( Reserved , x ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


"asked to expand an instruction that is not a shift"

expand - Expand a record into a set of elements if possible .


<s> bool WebAssembly :: mayThrow ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { case WebAssembly :: THROW : case WebAssembly :: THROW_S : case WebAssembly :: RETHROW : case WebAssembly :: RETHROW_S : return true ; } if ( isCallIndirect ( MI . getOpcode ( ) ) ) return true ; if ( ! MI . isCall ( ) ) return false ; const MachineOperand & MO = getCalleeOp ( MI ) ; assert ( MO . isGlobal ( ) || MO . isSymbol ( ) ) ; if ( MO . isSymbol ( ) ) { const char * Name = MO . getSymbolName ( ) ; if ( strcmp ( Name , "memcpy" ) == 0 || strcmp ( Name , "memmove" ) == 0 || strcmp ( Name , "memset" ) == 0 ) return false ; return true ; } const auto * F = dyn_cast < Function > ( MO . getGlobal ( ) ) ; if ( ! F ) return true ; if ( F -> doesNotThrow ( ) ) return false ; if ( F -> getName ( ) == CxaBeginCatchFn || F -> getName ( ) == PersonalityWrapperFn || F -> getName ( ) == StdTerminateFn ) return false ; return true ; } </s>

Return true if this instruction may throw an exception .


<s> static unsigned ix86_loop_unroll_adjust ( unsigned nunroll , struct loop * loop ) { basic_block * bbs ; rtx_insn * insn ; unsigned i ; unsigned mem_count = 0 ; if ( ! TARGET_ADJUST_UNROLL ) return nunroll ; subrtx_iterator :: array_type array ; bbs = get_loop_body ( loop ) ; for ( i = 0 ; i < loop -> num_nodes ; i ++ ) FOR_BB_INSNS ( bbs [ i ] , insn ) if ( NONDEBUG_INSN_P ( insn ) ) FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , NONCONST ) if ( const_rtx x = * iter ) if ( MEM_P ( x ) ) { machine_mode mode = GET_MODE ( x ) ; unsigned int n_words = GET_MODE_SIZE ( mode ) / UNITS_PER_WORD ; if ( n_words > 4 ) mem_count += 2 ; else mem_count += 1 ; } free ( bbs ) ; if ( mem_count && mem_count <= 32 ) return 32 / mem_count ; return nunroll ; } </s>

This function adjusts the unroll factor based on the hardware capabilities . For ex , bdver3 has a loop buffer which makes unrolling of smaller loops less important . This function decides the unroll factor using number of memory references ( value 32 is used ) as a heuristic .


<s> static reg_class_t mmix_preferred_reload_class ( rtx x , reg_class_t rclass ) { return GET_CODE ( x ) == MOD && GET_MODE ( x ) == DImode ? REMAINDER_REG : rclass ; } </s>

PREFERRED_RELOAD_CLASS . We need to extend the reload class of REMAINDER_REG and HIMULT_REG .


<s> static const char * nvptx_name_replacement ( const char * name ) { if ( strcmp ( name , "call" ) == 0 ) return "__nvptx_call" ; if ( strcmp ( name , "malloc" ) == 0 ) return "__nvptx_malloc" ; if ( strcmp ( name , "free" ) == 0 ) return "__nvptx_free" ; if ( strcmp ( name , "realloc" ) == 0 ) return "__nvptx_realloc" ; return name ; } </s>

Check NAME for special function names and redirect them by returning a replacement . This applies to malloc , free and realloc , for which we want to use libgcc wrappers , and call , which triggers a bug in ptxas .


<s> static rtx nvptx_gen_warp_bcast ( rtx reg ) { return nvptx_gen_shuffle ( reg , reg , const0_rtx , SHUFFLE_IDX ) ; } </s>

Generate an instruction or sequence to broadcast register REG across the vectors of a single warp .


<s> bool X86InstrInfo :: isUnpredicatedTerminator ( const MachineInstr * MI ) const { const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( ! MCID . isTerminator ( ) ) return false ; if ( MCID . isBranch ( ) && ! MCID . isBarrier ( ) ) return true ; if ( ! MCID . isPredicable ( ) ) return true ; return ! isPredicated ( MI ) ; } </s>

Returns true if the instruction is a terminator instruction that has not been predicated .


<s> static void aarch64_emit_sve_ptrue_op_cc ( rtx target , rtx ptrue , rtx op ) { rtx unspec = gen_rtx_UNSPEC ( GET_MODE ( target ) , gen_rtvec ( 2 , ptrue , op ) , UNSPEC_MERGE_PTRUE ) ; rtx_insn * insn = emit_insn ( gen_set_clobber_cc ( target , unspec ) ) ; set_unique_reg_note ( insn , REG_EQUAL , copy_rtx ( op ) ) ; } </s>

Likewise , but also clobber the condition codes .


<s> rtx ix86_rewrite_tls_address ( rtx pattern ) { pattern = copy_insn ( pattern ) ; ix86_rewrite_tls_address_1 ( & pattern ) ; return pattern ; } </s>

Rewrite instruction pattern involvning TLS address so that it refers to a default TLS address space .


<s> static unsigned int sparc_function_arg_boundary ( machine_mode mode , const_tree type ) { return ( ( TARGET_ARCH64 && ( GET_MODE_ALIGNMENT ( mode ) == 128 || ( type && TYPE_ALIGN ( type ) == 128 ) ) ) ? 128 : PARM_BOUNDARY ) ; } </s>

For sparc64 , objects requiring 16 byte alignment are passed that way .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 Indirect Branch Tracking"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
bool
SIFixVGPRCopies
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
const
GCNSubtarget
&
ST
=
MF
.
getSubtarget
<
GCNSubtarget
>
(
)
;
const
SIRegisterInfo
*
TRI
=
ST
.
getRegisterInfo
(
)
;
const
SIInstrInfo
*
TII
=
ST
.
getInstrInfo
(
)
;
bool
Changed
=
false
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
for
(
MachineInstr
&
MI
:
MBB
)
{
switch
(
MI
.
getOpcode
(
)
)
{
case
AMDGPU
::
COPY
:
if
(
TII
->
isVGPRCopy
(
MI
)
&&
!
MI
.
readsRegister
(
AMDGPU
::
EXEC
,
TRI
)
)
{
MI
.
addOperand
(
MF
,
MachineOperand
::
CreateReg
(
AMDGPU
::
EXEC
,
false
,
true
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Add exec use to "
<<
MI
)
;
Changed
=
true
;
}
break
;
default
:
break
;
}
}
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

AMDGPU
SI
SI
SI
AMDGPU::COPY
AMDGPU::EXEC
AMDGPU::EXEC
"Add exec use to "


<s>
bool
MSP430InstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugInstr
(
)
)
continue
;
if
(
!
isUnpredicatedTerminator
(
*
I
)
)
break
;
if
(
!
I
->
isBranch
(
)
)
return
true
;
if
(
I
->
getOpcode
(
)
==
MSP430
::
Br
||
I
->
getOpcode
(
)
==
MSP430
::
Bm
)
return
true
;
if
(
I
->
getOpcode
(
)
==
MSP430
::
JMP
||
I
->
getOpcode
(
)
==
MSP430
::
Bi
)
{
if
(
!
AllowModify
)
{
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
continue
;
}
while
(
std
::
next
(
I
)
!=
MBB
.
end
(
)
)
std
::
next
(
I
)
->
eraseFromParent
(
)
;
Cond
.
clear
(
)
;
FBB
=
nullptr
;
if
(
MBB
.
isLayoutSuccessor
(
I
->
getOperand
(
0
)
.
getMBB
(
)
)
)
{
TBB
=
nullptr
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
continue
;
}
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
continue
;
}
assert
(
I
->
getOpcode
(
)
==
MSP430
::
JCC
&&
"Invalid conditional branch"
)
;
MSP430CC
::
CondCodes
BranchCode
=
static_cast
<
MSP430CC
::
CondCodes
>
(
I
->
getOperand
(
1
)
.
getImm
(
)
)
;
if
(
BranchCode
==
MSP430CC
::
COND_INVALID
)
return
true
;
if
(
Cond
.
empty
(
)
)
{
FBB
=
TBB
;
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
BranchCode
)
)
;
continue
;
}
assert
(
Cond
.
size
(
)
==
1
)
;
assert
(
TBB
)
;
if
(
TBB
!=
I
->
getOperand
(
0
)
.
getMBB
(
)
)
return
true
;
MSP430CC
::
CondCodes
OldBranchCode
=
(
MSP430CC
::
CondCodes
)
Cond
[
0
]
.
getImm
(
)
;
if
(
OldBranchCode
==
BranchCode
)
continue
;
return
true
;
}
return
false
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .