<s> static void aarch64_push_regs ( unsigned regno1 , unsigned regno2 , HOST_WIDE_INT adjustment ) { rtx_insn * insn ; machine_mode mode = aarch64_reg_save_mode ( regno1 ) ; if ( regno2 == INVALID_REGNUM ) return aarch64_pushwb_single_reg ( mode , regno1 , adjustment ) ; rtx reg1 = gen_rtx_REG ( mode , regno1 ) ; rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; insn = emit_insn ( aarch64_gen_storewb_pair ( mode , stack_pointer_rtx , reg1 , reg2 , adjustment ) ) ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , 0 , 2 ) ) = 1 ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , 0 , 1 ) ) = 1 ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Push registers numbered REGNO1 and REGNO2 to the stack , adjusting the stack pointer by ADJUSTMENT .


<s> bool PatmosInstrInfo :: isPseudo ( const MachineInstr * MI ) const { if ( MI -> isBundle ( ) ) { MachineBasicBlock :: const_instr_iterator II = MI ; ++ II ; const MachineBasicBlock * MBB = MI -> getParent ( ) ; while ( II != MBB -> instr_end ( ) && II -> isBundledWithPred ( ) ) { if ( ! isPseudo ( II ) ) return false ; II ++ ; } return true ; } if ( MI -> isDebugValue ( ) ) return true ; if ( MI -> isInlineAsm ( ) ) return false ; const MCInstrDesc & TID = MI -> getDesc ( ) ; unsigned SchedClass = TID . getSchedClass ( ) ; const InstrStage * IS = PST . getInstrItineraryData ( ) . beginStage ( SchedClass ) ; unsigned FuncUnits = IS -> getUnits ( ) ; return ! FuncUnits ; } </s>

Return true if this is a pseudo instruction that does n't correspond to a real machine instruction .


<s> virtual MVT getShiftAmountTy ( EVT LHSTy ) const { return MVT :: i32 ; } </s>

Returns the type for the shift amount of a shift opcode .


<s> SDValue AAPTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { case ISD :: ADD : return PerformADDCombine ( N , DCI ) ; default : break ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> static void visium_conditional_register_usage ( void ) { if ( ! TARGET_SV_MODE ) { if ( visium_cpu_and_features == PROCESSOR_GR5 ) { fixed_regs [ 24 ] = 1 ; fixed_regs [ 25 ] = 1 ; fixed_regs [ 26 ] = 1 ; fixed_regs [ 27 ] = 1 ; fixed_regs [ 28 ] = 1 ; call_used_regs [ 24 ] = 0 ; call_used_regs [ 25 ] = 0 ; call_used_regs [ 26 ] = 0 ; call_used_regs [ 27 ] = 0 ; call_used_regs [ 28 ] = 0 ; } fixed_regs [ 31 ] = 1 ; call_used_regs [ 31 ] = 0 ; if ( visium_cpu_and_features == PROCESSOR_GR5 ) long_branch_regnum = 20 ; else long_branch_regnum = 28 ; } if ( ! TARGET_FPU ) { for ( int i = FP_FIRST_REGNUM ; i <= FP_LAST_REGNUM ; i ++ ) { fixed_regs [ i ] = 1 ; call_used_regs [ i ] = 0 ; } } } </s>

Conditionally modify the settings of the register file .


<s> static bool s390_function_arg_float ( machine_mode mode , const_tree type ) { if ( s390_function_arg_size ( mode , type ) > 8 ) return false ; if ( TARGET_SOFT_FLOAT ) return false ; if ( ! type ) return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode ; while ( TREE_CODE ( type ) == RECORD_TYPE ) { tree field , single = NULL_TREE ; for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( single == NULL_TREE ) single = TREE_TYPE ( field ) ; else return false ; } if ( single == NULL_TREE ) return false ; else type = single ; } return TREE_CODE ( type ) == REAL_TYPE ; } </s>

Return true if a function argument of type TYPE and mode MODE is to be passed in a floating-point register , if available .


<s>
void
addExpr
(
MCInst
&
Inst
,
const
MCExpr
*
Expr
)
const
{
assert
(
Expr
&&
"Expr shouldn't be null!"
)
;
int64_t
Imm
=
0
;
bool
IsConstant
=
false
;
if
(
auto
*
RE
=
dyn_cast
<
CAHPMCExpr
>
(
Expr
)
)
{
IsConstant
=
RE
->
evaluateAsConstant
(
Imm
)
;
}
else
if
(
auto
*
CE
=
dyn_cast
<
MCConstantExpr
>
(
Expr
)
)
{
IsConstant
=
true
;
Imm
=
CE
->
getValue
(
)
;
}
if
(
IsConstant
)
Inst
.
addOperand
(
MCOperand
::
createImm
(
Imm
)
)
;
else
Inst
.
addOperand
(
MCOperand
::
createExpr
(
Expr
)
)
;
}
</s>


<s> static tree c6x_builtin_decl ( unsigned code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= C6X_BUILTIN_MAX ) return error_mark_node ; return c6x_builtin_decls [ code ] ; } </s>


<s>
void
ARMBaseInstrInfo
::
setExecutionDomain
(
MachineInstr
*
MI
,
unsigned
Domain
)
const
{
assert
(
MI
->
getOpcode
(
)
==
ARM
::
VMOVD
&&
"Can only swizzle VMOVD"
)
;
if
(
Domain
!=
ExeNEON
)
return
;
assert
(
!
isPredicated
(
MI
)
&&
"Cannot predicate a VORRd"
)
;
MI
->
RemoveOperand
(
3
)
;
MI
->
RemoveOperand
(
2
)
;
MI
->
setDesc
(
get
(
ARM
::
VORRd
)
)
;
AddDefaultPred
(
MachineInstrBuilder
(
MI
)
.
addOperand
(
MI
->
getOperand
(
1
)
)
)
;
}
</s>

Change the opcode of MI to execute in Domain .

ARM
ARM
ARM::VMOVD
"Can only swizzle VMOVD"
"Cannot predicate a VORRd"
3
2
ARM::VORRd
1


<s>
const
char
*
output_movedouble
(
rtx
insn
ATTRIBUTE_UNUSED
,
rtx
operands
[
]
,
machine_mode
mode
)
{
rtx
dst
=
operands
[
0
]
;
rtx
src
=
operands
[
1
]
;
if
(
MEM_P
(
dst
)
&&
GET_CODE
(
XEXP
(
dst
,
0
)
)
==
PRE_DEC
)
return
"mov.l	%T1,%0"
"\n"
"	mov.l	%1,%0"
;
if
(
register_operand
(
dst
,
mode
)
&&
register_operand
(
src
,
mode
)
)
{
if
(
REGNO
(
src
)
==
MACH_REG
)
return
"sts	mach,%S0"
"\n"
"	sts	macl,%R0"
;
if
(
REGNO
(
src
)
+
1
==
REGNO
(
dst
)
)
return
"mov	%T1,%T0"
"\n"
"	mov	%1,%0"
;
else
return
"mov	%1,%0"
"\n"
"	mov	%T1,%T0"
;
}
else
if
(
CONST_INT_P
(
src
)
)
{
if
(
INTVAL
(
src
)
<
0
)
output_asm_insn
(
"mov	#-1,%S0"
,
operands
)
;
else
output_asm_insn
(
"mov	#0,%S0"
,
operands
)
;
return
"mov	%1,%R0"
;
}
else
if
(
MEM_P
(
src
)
)
{
int
ptrreg
=
1
;
int
dreg
=
REGNO
(
dst
)
;
rtx
inside
=
XEXP
(
src
,
0
)
;
switch
(
GET_CODE
(
inside
)
)
{
case
REG
:
ptrreg
=
REGNO
(
inside
)
;
break
;
case
SUBREG
:
ptrreg
=
subreg_regno
(
inside
)
;
break
;
case
PLUS
:
ptrreg
=
REGNO
(
XEXP
(
inside
,
0
)
)
;
gcc_assert
(
!
REG_P
(
XEXP
(
inside
,
1
)
)
)
;
break
;
case
LABEL_REF
:
return
"mov.l	%1,%0"
"\n"
"	mov.l	%1+4,%T0"
;
case
POST_INC
:
return
"mov.l	%1,%0"
"\n"
"	mov.l	%1,%T0"
;
default
:
gcc_unreachable
(
)
;
}
if
(
dreg
==
ptrreg
)
return
"mov.l	%T1,%T0"
"\n"
"	mov.l	%1,%0"
;
}
return
"mov.l	%1,%0"
"\n"
"	mov.l	%T1,%T0"
;
}
</s>

Return a sequence of instructions to perform DI or DF move . Since the SH can not move a DI or DF in one instruction , we have to take care when we see overlapping source and dest registers .


<s> unsigned int rs6000_special_round_type_align ( tree type , int computed , int specified ) { tree field = TYPE_FIELDS ( type ) ; while ( field != NULL && TREE_CODE ( field ) != FIELD_DECL ) field = TREE_CHAIN ( field ) ; if ( field == NULL || field == type || DECL_MODE ( field ) != DFmode ) return MAX ( computed , specified ) ; return MAX ( MAX ( computed , specified ) , 64 ) ; } </s>

Darwin , AIX increases natural record alignment to doubleword if the first field is an FP double while the FP fields remain word aligned .


<s> static bool tilepro_emit_setcc_internal ( rtx res , enum rtx_code code , rtx op0 , rtx op1 , machine_mode cmp_mode ) { rtx tmp ; bool swap = false ; if ( cmp_mode == DImode ) { return tilepro_emit_setcc_internal_di ( res , code , op0 , op1 ) ; } switch ( code ) { case EQ : case NE : case LE : case LT : case LEU : case LTU : break ; case GE : case GT : case GEU : case GTU : swap = true ; break ; default : gcc_unreachable ( ) ; } if ( swap ) { code = swap_condition ( code ) ; tmp = op0 , op0 = op1 , op1 = tmp ; } if ( ! reg_or_0_operand ( op0 , SImode ) ) op0 = force_reg ( SImode , op0 ) ; if ( ! CONST_INT_P ( op1 ) && ! register_operand ( op1 , SImode ) ) op1 = force_reg ( SImode , op1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , res , gen_rtx_fmt_ee ( code , SImode , op0 , op1 ) ) ) ; return true ; } </s>

Certain simplifications can be done to make invalid setcc operations valid . Return the final comparison , or NULL if we ca n't work .


<s>
void
SystemZRegisterInfo
::
emitPrologue
(
MachineFunction
&
MF
)
const
{
MachineBasicBlock
&
MBB
=
MF
.
front
(
)
;
const
TargetFrameInfo
&
TFI
=
*
MF
.
getTarget
(
)
.
getFrameInfo
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
SystemZMachineFunctionInfo
*
SystemZMFI
=
MF
.
getInfo
<
SystemZMachineFunctionInfo
>
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
DL
=
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
uint64_t
StackSize
=
MFI
->
getStackSize
(
)
;
StackSize
-=
SystemZMFI
->
getCalleeSavedFrameSize
(
)
;
uint64_t
NumBytes
=
StackSize
TFI
.
getOffsetOfLocalArea
(
)
;
while
(
MBBI
!=
MBB
.
end
(
)
&&
(
MBBI
->
getOpcode
(
)
==
SystemZ
::
MOV64mr
||
MBBI
->
getOpcode
(
)
==
SystemZ
::
MOV64mrm
)
)
++
MBBI
;
if
(
MBBI
!=
MBB
.
end
(
)
)
DL
=
MBBI
->
getDebugLoc
(
)
;
if
(
StackSize
||
MFI
->
hasCalls
(
)
)
{
assert
(
MF
.
getRegInfo
(
)
.
isPhysRegUsed
(
SystemZ
::
R15D
)
&&
"Invalid stack frame calculation!"
)
;
emitSPUpdate
(
MBB
,
MBBI
,
(
int64_t
)
NumBytes
,
TII
)
;
}
if
(
hasFP
(
MF
)
)
{
BuildMI
(
MBB
,
MBBI
,
DL
,
TII
.
get
(
SystemZ
::
MOV64rr
)
,
SystemZ
::
R11D
)
.
addReg
(
SystemZ
::
R15D
)
;
for
(
MachineFunction
::
iterator
I
=
llvm
::
next
(
MF
.
begin
(
)
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
I
->
addLiveIn
(
SystemZ
::
R11D
)
;
}
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


"Do not know how to custom type legalize this operation!"

"Unexpected result type for CTR decrement intrinsic"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> bool R600InstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return false ; if ( isBranch ( I -> getOpcode ( ) ) ) return true ; if ( ! isJump ( static_cast < MachineInstr * > ( I ) -> getOpcode ( ) ) ) { return false ; } while ( I != MBB . begin ( ) && std :: prev ( I ) -> getOpcode ( ) == AMDGPU :: JUMP ) { MachineBasicBlock :: iterator PriorI = std :: prev ( I ) ; if ( AllowModify ) I -> removeFromParent ( ) ; I = PriorI ; } MachineInstr & LastInst = * I ; unsigned LastOpc = LastInst . getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isJump ( static_cast < MachineInstr * > ( -- I ) -> getOpcode ( ) ) ) { if ( LastOpc == AMDGPU :: JUMP ) { TBB = LastInst . getOperand ( 0 ) . getMBB ( ) ; return false ; } else if ( LastOpc == AMDGPU :: JUMP_COND ) { auto predSet = I ; while ( ! isPredicateSetter ( predSet -> getOpcode ( ) ) ) { predSet = -- I ; } TBB = LastInst . getOperand ( 0 ) . getMBB ( ) ; Cond . push_back ( predSet -> getOperand ( 1 ) ) ; Cond . push_back ( predSet -> getOperand ( 2 ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( AMDGPU :: PRED_SEL_ONE , false ) ) ; return false ; } return true ; } MachineInstr & SecondLastInst = * I ; unsigned SecondLastOpc = SecondLastInst . getOpcode ( ) ; if ( SecondLastOpc == AMDGPU :: JUMP_COND && LastOpc == AMDGPU :: JUMP ) { auto predSet = -- I ; while ( ! isPredicateSetter ( predSet -> getOpcode ( ) ) ) { predSet = -- I ; } TBB = SecondLastInst . getOperand ( 0 ) . getMBB ( ) ; FBB = LastInst . getOperand ( 0 ) . getMBB ( ) ; Cond . push_back ( predSet -> getOperand ( 1 ) ) ; Cond . push_back ( predSet -> getOperand ( 2 ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( AMDGPU :: PRED_SEL_ONE , false ) ) ; return false ; } return true ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s>
static
void
alpha_output_function_end_prologue
(
FILE
*
file
)
{
if
(
TARGET_ABI_OPEN_VMS
)
fputs
(
"\t.prologue\n"
,
file
)
;
else
if
(
!
flag_inhibit_size_directive
)
fprintf
(
file
,
"\t.prologue %d\n"
,
alpha_function_needs_gp
||
cfun
->
is_thunk
)
;
}
</s>

Emit the .prologue note at the scheduled end of the prologue .

alpha
"\t.prologue\n"
"\t.prologue %d\n"


<s> static void mips_va_start ( tree valist , rtx nextarg ) { if ( EABI_FLOAT_VARARGS_P ) { const CUMULATIVE_ARGS * cum ; tree f_ovfl , f_gtop , f_ftop , f_goff , f_foff ; tree ovfl , gtop , ftop , goff , foff ; tree t ; int gpr_save_area_size ; int fpr_save_area_size ; int fpr_offset ; cum = & crtl -> args . info ; gpr_save_area_size = ( MAX_ARGS_IN_REGISTERS - cum -> num_gprs ) * UNITS_PER_WORD ; fpr_save_area_size = ( MAX_ARGS_IN_REGISTERS - cum -> num_fprs ) * UNITS_PER_FPREG ; f_ovfl = TYPE_FIELDS ( va_list_type_node ) ; f_gtop = DECL_CHAIN ( f_ovfl ) ; f_ftop = DECL_CHAIN ( f_gtop ) ; f_goff = DECL_CHAIN ( f_ftop ) ; f_foff = DECL_CHAIN ( f_goff ) ; ovfl = build3 ( COMPONENT_REF , TREE_TYPE ( f_ovfl ) , valist , f_ovfl , NULL_TREE ) ; gtop = build3 ( COMPONENT_REF , TREE_TYPE ( f_gtop ) , valist , f_gtop , NULL_TREE ) ; ftop = build3 ( COMPONENT_REF , TREE_TYPE ( f_ftop ) , valist , f_ftop , NULL_TREE ) ; goff = build3 ( COMPONENT_REF , TREE_TYPE ( f_goff ) , valist , f_goff , NULL_TREE ) ; foff = build3 ( COMPONENT_REF , TREE_TYPE ( f_foff ) , valist , f_foff , NULL_TREE ) ; t = make_tree ( TREE_TYPE ( ovfl ) , virtual_incoming_args_rtx ) ; if ( cum -> stack_words > 0 ) t = fold_build_pointer_plus_hwi ( t , cum -> stack_words * UNITS_PER_WORD ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( ovfl ) , ovfl , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( gtop ) , virtual_incoming_args_rtx ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( gtop ) , gtop , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( ftop ) , virtual_incoming_args_rtx ) ; fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1 ; fpr_offset &= - UNITS_PER_FPVALUE ; if ( fpr_offset ) t = fold_build_pointer_plus_hwi ( t , - fpr_offset ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( ftop ) , ftop , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( goff ) , goff , build_int_cst ( TREE_TYPE ( goff ) , gpr_save_area_size ) ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( foff ) , foff , build_int_cst ( TREE_TYPE ( foff ) , fpr_save_area_size ) ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; } else { nextarg = plus_constant ( Pmode , nextarg , - cfun -> machine -> varargs_size ) ; std_expand_builtin_va_start ( valist , nextarg ) ; } } </s>


<s>
unsigned
getReg
(
)
const
override
{
assert
(
isReg
(
)
&&
"Invalid type access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s>
void
X86InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
Register
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
assert
(
MFI
.
getObjectSize
(
FrameIdx
)
>=
TRI
->
getSpillSize
(
*
RC
)
&&
"Stack slot too small for store"
)
;
if
(
RC
->
getID
(
)
==
X86
::
TILERegClassID
)
{
unsigned
Opc
=
X86
::
TILESTORED
;
MachineRegisterInfo
&
RegInfo
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
Register
VirtReg
=
RegInfo
.
createVirtualRegister
(
&
X86
::
GR64_NOSPRegClass
)
;
BuildMI
(
MBB
,
MI
,
DebugLoc
(
)
,
get
(
X86
::
MOV64ri
)
,
VirtReg
)
.
addImm
(
64
)
;
MachineInstr
*
NewMI
=
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DebugLoc
(
)
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
MachineOperand
&
MO
=
NewMI
->
getOperand
(
2
)
;
MO
.
setReg
(
VirtReg
)
;
MO
.
setIsKill
(
true
)
;
}
else
{
unsigned
Alignment
=
std
::
max
<
uint32_t
>
(
TRI
->
getSpillSize
(
*
RC
)
,
16
)
;
bool
isAligned
=
(
Subtarget
.
getFrameLowering
(
)
->
getStackAlign
(
)
>=
Alignment
)
||
(
RI
.
canRealignStack
(
MF
)
&&
!
MFI
.
isFixedObjectIndex
(
FrameIdx
)
)
;
unsigned
Opc
=
getStoreRegOpcode
(
SrcReg
,
RC
,
isAligned
,
Subtarget
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DebugLoc
(
)
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> tree function_builder :: get_attributes ( const function_instance & instance ) { tree attrs = NULL_TREE ; if ( ! instance . modifies_global_state_p ( ) ) { if ( instance . reads_global_state_p ( ) ) attrs = add_attribute ( "pure" , attrs ) ; else attrs = add_attribute ( "const" , attrs ) ; } if ( ! flag_non_call_exceptions || ! instance . could_trap_p ( ) ) attrs = add_attribute ( "nothrow" , attrs ) ; return add_attribute ( "leaf" , attrs ) ; } </s>

Return the appropriate function attributes for INSTANCE .


<s> ScheduleHazardRecognizer :: HazardType ARMHazardRecognizer :: getHazardType ( SUnit * SU ) { MachineInstr * MI = SU -> getInstr ( ) ; if ( ! MI -> isDebugValue ( ) ) { if ( ITBlockSize && MI != ITBlockMIs [ ITBlockSize - 1 ] ) return Hazard ; const TargetInstrDesc & TID = MI -> getDesc ( ) ; if ( LastMI && ( TID . TSFlags & ARMII :: DomainMask ) != ARMII :: DomainGeneral ) { MachineInstr * DefMI = LastMI ; const TargetInstrDesc & LastTID = LastMI -> getDesc ( ) ; if ( ! LastTID . isBarrier ( ) && ( LastTID . TSFlags & ARMII :: DomainMask ) == ARMII :: DomainGeneral ) { MachineBasicBlock :: iterator I = LastMI ; if ( I != LastMI -> getParent ( ) -> begin ( ) ) { I = llvm :: prior ( I ) ; DefMI = & * I ; } } if ( TII . isFpMLxInstruction ( DefMI -> getOpcode ( ) ) && ( TII . canCauseFpMLxStall ( MI -> getOpcode ( ) ) || hasRAWHazard ( DefMI , MI , TRI ) ) ) { if ( Stalls == 0 ) Stalls = 4 ; return Hazard ; } } } return ScoreboardHazardRecognizer :: getHazardType ( SU ) ; } </s>

getHazardType - Return the hazard type of emitting this node .

ARM ARM 1 ARMII::DomainMask ARMII::DomainGeneral ARMII::DomainMask ARMII::DomainGeneral 0 4


<s> static rtx arm_dwarf_register_span ( rtx rtl ) { machine_mode mode ; unsigned regno ; rtx parts [ 16 ] ; int nregs ; int i ; regno = REGNO ( rtl ) ; if ( ! IS_VFP_REGNUM ( regno ) ) return NULL_RTX ; mode = GET_MODE ( rtl ) ; if ( GET_MODE_SIZE ( mode ) < 8 ) return NULL_RTX ; if ( VFP_REGNO_OK_FOR_SINGLE ( regno ) ) { nregs = GET_MODE_SIZE ( mode ) / 4 ; for ( i = 0 ; i < nregs ; i += 2 ) if ( TARGET_BIG_END ) { parts [ i ] = gen_rtx_REG ( SImode , regno + i + 1 ) ; parts [ i + 1 ] = gen_rtx_REG ( SImode , regno + i ) ; } else { parts [ i ] = gen_rtx_REG ( SImode , regno + i ) ; parts [ i + 1 ] = gen_rtx_REG ( SImode , regno + i + 1 ) ; } } else { nregs = GET_MODE_SIZE ( mode ) / 8 ; for ( i = 0 ; i < nregs ; i ++ ) parts [ i ] = gen_rtx_REG ( DImode , regno + i ) ; } return gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( nregs , parts ) ) ; } </s>

Dwarf models VFPv3 registers as 32 64-bit registers . GCC models tham as 64 32-bit registers , so we need to describe this to the DWARF generation code . Other registers can use the default .


<s> static tree nios2_builtin_decl ( unsigned code , bool initialize_p ATTRIBUTE_UNUSED ) { gcc_assert ( nios2_custom_builtin_end == ARRAY_SIZE ( nios2_builtin_decls ) ) ; if ( code >= nios2_custom_builtin_end ) return error_mark_node ; if ( code >= nios2_fpu_builtin_base && code < nios2_custom_builtin_base && ! N2FPU_ENABLED_P ( code - nios2_fpu_builtin_base ) ) return error_mark_node ; return nios2_builtin_decls [ code ] ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesAll ( ) ; AU . addRequired < MachineModuleInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> SDValue CJGTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; AnalyzeReturnValues ( CCInfo , RVLocs , Ins ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> bool MipsConstantIslands :: runOnMachineFunction ( MachineFunction & F ) { return true ; } </s>

runOnMachineFunction - Emit the function body .


<s>
SDValue
BPFTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
dl
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_BPF64
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
if
(
RVLocs
[
i
]
.
isRegLoc
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
if
(
DAG
.
getMachineFunction
(
)
.
getFunction
(
)
->
hasStructRetAttr
(
)
)
{
errs
(
)
<<
"Function: "
<<
DAG
.
getMachineFunction
(
)
.
getName
(
)
<<
" "
;
DAG
.
getMachineFunction
(
)
.
getFunction
(
)
->
getFunctionType
(
)
->
dump
(
)
;
errs
(
)
<<
"\n"
;
report_fatal_error
(
"BPF doesn't support struct return"
)
;
}
unsigned
Opc
=
BPFISD
::
RET_FLAG
;
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
Opc
,
dl
,
MVT
::
Other
,
&
RetOps
[
0
]
,
RetOps
.
size
(
)
)
;
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
Opc
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
return
DAG
.
getNode
(
Opc
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> unsigned PPCInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case PPC :: LD : case PPC :: LWZ : case PPC :: LFS : case PPC :: LFD : case PPC :: RESTORE_CR : case PPC :: RESTORE_CRBIT : case PPC :: LVX : case PPC :: LXVD2X : case PPC :: LXVX : case PPC :: QVLFDX : case PPC :: QVLFSXs : case PPC :: QVLFDXb : case PPC :: RESTORE_VRSAVE : case PPC :: SPILLTOVSR_LD : if ( MI . getOperand ( 1 ) . isImm ( ) && ! MI . getOperand ( 1 ) . getImm ( ) && MI . getOperand ( 2 ) . isFI ( ) ) { FrameIndex = MI . getOperand ( 2 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> void NVPTXTargetStreamer :: closeLastSection ( ) { if ( HasSections ) getStreamer ( ) . emitRawText ( "\t}" ) ; } </s>


<s> int arc_hazard ( rtx_insn * pred , rtx_insn * succ ) { if ( ! pred || ! INSN_P ( pred ) || ! succ || ! INSN_P ( succ ) ) return 0 ; if ( TARGET_ARC600 ) return arc600_corereg_hazard ( pred , succ ) ; return 0 ; } </s>

For ARC600 : A write to a core reg greater or equal to 32 must not be immediately followed by a use . Anticipate the length requirement to insert a nop between PRED and SUCC to prevent a hazard .


<s>
const
char
*
host_detect_local_cpu
(
int
argc
,
const
char
*
*
argv
)
{
const
char
*
cpu
=
;
char
buf
[
128
]
;
FILE
*
f
;
bool
arch
;
if
(
argc
<
1
)
return
;
arch
=
strcmp
(
argv
[
0
]
,
"arch"
)
==
0
;
if
(
!
arch
&&
strcmp
(
argv
[
0
]
,
"tune"
)
)
return
;
f
=
fopen
(
"/proc/cpuinfo"
,
"r"
)
;
if
(
f
==
)
return
;
while
(
fgets
(
buf
,
sizeof
(
buf
)
,
f
)
!=
)
if
(
startswith
(
buf
,
"cpu model"
)
)
{
if
(
strstr
(
buf
,
"Godson2 V0.2"
)
!=
||
strstr
(
buf
,
"Loongson-2 V0.2"
)
!=
||
strstr
(
buf
,
"Loongson-2E"
)
!=
)
cpu
=
"loongson2e"
;
else
if
(
strstr
(
buf
,
"Godson2 V0.3"
)
!=
||
strstr
(
buf
,
"Loongson-2 V0.3"
)
!=
||
strstr
(
buf
,
"Loongson-2F"
)
!=
)
cpu
=
"loongson2f"
;
else
if
(
strstr
(
buf
,
"Godson3 V0.5"
)
!=
||
strstr
(
buf
,
"Loongson-3 V0.5"
)
!=
||
strstr
(
buf
,
"Loongson-3A"
)
!=
)
cpu
=
"loongson3a"
;
else
if
(
strstr
(
buf
,
"SiByte SB1"
)
!=
)
cpu
=
"sb1"
;
else
if
(
strstr
(
buf
,
"R5000"
)
!=
)
cpu
=
"r5000"
;
else
if
(
strstr
(
buf
,
"Octeon II"
)
!=
)
cpu
=
"octeon2"
;
else
if
(
strstr
(
buf
,
"Octeon"
)
!=
)
cpu
=
"octeon"
;
break
;
}
fclose
(
f
)
;
if
(
cpu
==
)
return
;
return
concat
(
"-m"
,
argv
[
0
]
,
"="
,
cpu
,
)
;
}
</s>

This will be called by the spec parser in gcc.cc when it sees a % : local_cpu_detect ( args ) construct . Currently it will be called with either `` cpu '' or `` tune '' as argument depending on if -mcpu=native or -mtune=native is to be substituted . It returns a string containing new command line parameters to be put at the place of the above two options , depending on what CPU this is executed . E.g . `` -mcpu=ultrasparc3 '' on an UltraSPARC III for -mcpu=native . If the routine ca n't detect a known processor , the -mcpu or -mtune option is discarded . ARGC and ARGV are set depending on the actual arguments given in the spec .


"Not all fixup kinds added to Infos array"


<s>
void
SIRegisterInfo
::
resolveFrameIndex
(
MachineInstr
&
MI
,
Register
BaseReg
,
int64_t
Offset
)
const
{
const
SIInstrInfo
*
TII
=
ST
.
getInstrInfo
(
)
;
bool
IsFlat
=
TII
->
isFLATScratch
(
MI
)
;
bool
SeenFI
=
false
;
for
(
const
MachineOperand
&
MO
:
MI
.
operands
(
)
)
{
if
(
MO
.
isFI
(
)
)
{
if
(
SeenFI
)
llvm_unreachable
(
"should not see multiple frame indices"
)
;
SeenFI
=
true
;
}
}
MachineOperand
*
FIOp
=
TII
->
getNamedOperand
(
MI
,
IsFlat
AMDGPU
::
OpName
::
saddr
:
AMDGPU
::
OpName
::
vaddr
)
;
MachineOperand
*
OffsetOp
=
TII
->
getNamedOperand
(
MI
,
AMDGPU
::
OpName
::
offset
)
;
int64_t
NewOffset
=
OffsetOp
->
getImm
(
)
+
Offset
;
MachineBasicBlock
*
MBB
=
MI
.
getParent
(
)
;
MachineFunction
*
MF
=
MBB
->
getParent
(
)
;
assert
(
FIOp
&&
FIOp
->
isFI
(
)
&&
"frame index must be address operand"
)
;
assert
(
TII
->
isMUBUF
(
MI
)
||
TII
->
isFLATScratch
(
MI
)
)
;
if
(
IsFlat
)
{
assert
(
TII
->
isLegalFLATOffset
(
NewOffset
,
AMDGPUAS
::
PRIVATE_ADDRESS
,
true
)
&&
"offset should be legal"
)
;
FIOp
->
ChangeToRegister
(
BaseReg
,
false
)
;
OffsetOp
->
setImm
(
NewOffset
)
;
return
;
}
MachineOperand
*
SOffset
=
TII
->
getNamedOperand
(
MI
,
AMDGPU
::
OpName
::
soffset
)
;
assert
(
(
SOffset
->
isReg
(
)
&&
SOffset
->
getReg
(
)
==
MF
->
getInfo
<
SIMachineFunctionInfo
>
(
)
->
getStackPtrOffsetReg
(
)
)
||
(
SOffset
->
isImm
(
)
&&
SOffset
->
getImm
(
)
==
0
)
)
;
assert
(
SIInstrInfo
::
isLegalMUBUFImmOffset
(
NewOffset
)
&&
"offset should be legal"
)
;
FIOp
->
ChangeToRegister
(
BaseReg
,
false
)
;
OffsetOp
->
setImm
(
NewOffset
)
;
}
</s>

AMDGPU
SI
SI
"should not see multiple frame indices"
AMDGPU::OpName
AMDGPU::OpName
AMDGPU::OpName
"frame index must be address operand"
AMDGPU
"offset should be legal"
AMDGPU::OpName
SI
0
SI
"offset should be legal"


<s> bool GCNPassConfig :: addRegBankSelect ( ) { addPass ( new RegBankSelect ( ) ) ; return false ; } </s>

This method should install a register bank selector pass , which assigns register banks to virtual registers without a register class or register banks .


<s> void PPCRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && I -> getOpcode ( ) == PPC :: ADJCALLSTACKUP ) { if ( int CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { bool is64Bit = Subtarget . isPPC64 ( ) ; CalleeAmt *= - 1 ; unsigned StackReg = is64Bit ? PPC :: X1 : PPC :: R1 ; unsigned TmpReg = is64Bit ? PPC :: X0 : PPC :: R0 ; unsigned ADDIInstr = is64Bit ? PPC :: ADDI8 : PPC :: ADDI ; unsigned ADDInstr = is64Bit ? PPC :: ADD8 : PPC :: ADD4 ; unsigned LISInstr = is64Bit ? PPC :: LIS8 : PPC :: LIS ; unsigned ORIInstr = is64Bit ? PPC :: ORI8 : PPC :: ORI ; MachineInstr * MI = I ; DebugLoc dl = MI -> getDebugLoc ( ) ; if ( isInt < 16 > ( CalleeAmt ) ) { BuildMI ( MBB , I , dl , TII . get ( ADDIInstr ) , StackReg ) . addReg ( StackReg , RegState :: Kill ) . addImm ( CalleeAmt ) ; } else { MachineBasicBlock :: iterator MBBI = I ; BuildMI ( MBB , MBBI , dl , TII . get ( LISInstr ) , TmpReg ) . addImm ( CalleeAmt >> 16 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ORIInstr ) , TmpReg ) . addReg ( TmpReg , RegState :: Kill ) . addImm ( CalleeAmt & 0xFFFF ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ADDInstr ) , StackReg ) . addReg ( StackReg , RegState :: Kill ) . addReg ( TmpReg ) ; } } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool RISCVFrameLowering :: enableShrinkWrapping ( const MachineFunction & MF ) const { if ( MF . getFunction ( ) . hasOptNone ( ) ) return false ; return true ; } </s>

Returns true if the target will correctly handle shrink wrapping .


"getBranchTargetOpValueMM expects only expressions or immediates"

getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch target operand .


Implement target hook libgcc_floating_mode_supported_p .


<s> void PPCOperand :: print ( raw_ostream & OS ) const { switch ( Kind ) { case Token : OS << "'" << getToken ( ) << "'" ; break ; case Immediate : OS << getImm ( ) ; break ; case Expression : getExpr ( ) -> print ( OS ) ; break ; } } </s>

print - Print a debug representation of the operand to the given stream .


<s> bool ARMPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None && ! getARMSubtarget ( ) . isThumb1Only ( ) ) PM . add ( createARMLoadStoreOptimizationPass ( true ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None && getARMSubtarget ( ) . isCortexA9 ( ) ) PM . add ( createMLxExpansionPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> virtual const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> static void rs6000_emit_epilogue_components ( sbitmap components ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; rtx ptr_reg = gen_rtx_REG ( Pmode , frame_pointer_needed ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ) ; machine_mode reg_mode = Pmode ; int reg_size = TARGET_32BIT ? 4 : 8 ; machine_mode fp_reg_mode = ( TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT ) ? DFmode : SFmode ; int fp_reg_size = 8 ; int offset = info -> fp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_fp_reg_save ; i < 64 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( fp_reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } offset += fp_reg_size ; } offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_gp_reg_save ; i < 32 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } offset += reg_size ; } if ( bitmap_bit_p ( components , 0 ) ) { int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; rtx reg = gen_rtx_REG ( reg_mode , 0 ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; rtx lr = gen_rtx_REG ( Pmode , LR_REGNO ) ; insn = emit_move_insn ( lr , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_RESTORE , lr ) ; } } </s>


<s> static void aarch64_emit_bic ( machine_mode mode , rtx dst , rtx s1 , rtx s2 , int shift ) { rtx shift_rtx = GEN_INT ( shift ) ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; switch ( mode ) { case SImode : gen = gen_and_one_cmpl_lshrsi3 ; break ; case DImode : gen = gen_and_one_cmpl_lshrdi3 ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( dst , s2 , shift_rtx , s1 ) ) ; } </s>


<s> static void arc_ccfsm_post_advance ( rtx_insn * insn , struct arc_ccfsm * state ) { enum attr_type type ; if ( LABEL_P ( insn ) ) arc_ccfsm_at_label ( "L" , CODE_LABEL_NUMBER ( insn ) , state ) ; else if ( JUMP_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) != ADDR_VEC && GET_CODE ( PATTERN ( insn ) ) != ADDR_DIFF_VEC && ( ( type = get_attr_type ( insn ) ) == TYPE_BRANCH || ( type == TYPE_UNCOND_BRANCH && ARC_CCFSM_BRANCH_DELETED_P ( state ) ) ) ) { if ( ARC_CCFSM_BRANCH_DELETED_P ( state ) ) ARC_CCFSM_RECORD_BRANCH_DELETED ( state ) ; else { rtx src = SET_SRC ( PATTERN ( insn ) ) ; arc_ccfsm_record_condition ( XEXP ( src , 0 ) , XEXP ( src , 1 ) == pc_rtx , insn , state ) ; } } else if ( arc_ccfsm_current . state == 5 ) arc_ccfsm_current . state = 0 ; } </s>

Update * STATE as we would when we emit INSN .


<s> std :: pair < unsigned , const TargetRegisterClass * > SystemZTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'd' : case 'r' : if ( VT == MVT :: i64 ) return std :: make_pair ( 0U , & SystemZ :: GR64BitRegClass ) ; else if ( VT == MVT :: i128 ) return std :: make_pair ( 0U , & SystemZ :: GR128BitRegClass ) ; return std :: make_pair ( 0U , & SystemZ :: GR32BitRegClass ) ; case 'a' : if ( VT == MVT :: i64 ) return std :: make_pair ( 0U , & SystemZ :: ADDR64BitRegClass ) ; else if ( VT == MVT :: i128 ) return std :: make_pair ( 0U , & SystemZ :: ADDR128BitRegClass ) ; return std :: make_pair ( 0U , & SystemZ :: ADDR32BitRegClass ) ; case 'f' : if ( VT == MVT :: f64 ) return std :: make_pair ( 0U , & SystemZ :: FP64BitRegClass ) ; else if ( VT == MVT :: f128 ) return std :: make_pair ( 0U , & SystemZ :: FP128BitRegClass ) ; return std :: make_pair ( 0U , & SystemZ :: FP32BitRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


"ARM pre- register allocation load / store optimization pass"

getPassName - Return a nice clean name for a pass .


<s> static void dispatch_forest ( fma_forest * forest ) { forest -> dispatch ( ) ; } </s>

Wrapper around fma_forest : :dispatch for use as parameter of function pointer type in func_fma_steering : :dfs .


<s> const MCPhysReg * CJGRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CC_Save_SaveList ; } </s>


<s> void WebAssemblyTargetWasmStreamer :: emitLocal ( ArrayRef < MVT > Types ) { SmallVector < std :: pair < MVT , uint32_t > , 4 > Grouped ; for ( MVT Type : Types ) { if ( Grouped . empty ( ) || Grouped . back ( ) . first != Type ) Grouped . push_back ( std :: make_pair ( Type , 1 ) ) ; else ++ Grouped . back ( ) . second ; } Streamer . EmitULEB128IntValue ( Grouped . size ( ) ) ; for ( auto Pair : Grouped ) { Streamer . EmitULEB128IntValue ( Pair . second ) ; emitValueType ( WebAssembly :: toValType ( Pair . first ) ) ; } } </s>


<s> static bool nds32_needs_double_word_align ( machine_mode mode , const_tree type ) { unsigned int align ; align = NDS32_MODE_TYPE_ALIGN ( mode , type ) ; return ( align > PARM_BOUNDARY ) ; } </s>

Return true if MODE/TYPE need double word alignment .


<s> void PPCAIXAsmPrinter :: SetupMachineFunction ( MachineFunction & MF ) { CurrentFnDescSym = getSymbol ( & MF . getFunction ( ) ) ; MCSectionXCOFF * FnDescSec = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForFunctionDescriptor ( CurrentFnDescSym ) ) ; FnDescSec -> setAlignment ( Align ( Subtarget -> isPPC64 ( ) ? 8 : 4 ) ) ; cast < MCSymbolXCOFF > ( CurrentFnDescSym ) -> setContainingCsect ( FnDescSec ) ; return AsmPrinter :: SetupMachineFunction ( MF ) ; } </s>

This should be called when a new MachineFunction is being processed from runOnMachineFunction .


<s> static void mt_machine_reorg ( void ) { if ( mt_flag_delayed_branch ) dbr_schedule ( get_insns ( ) , dump_file ) ; if ( TARGET_MS2 ) { split_all_insns_noflow ( ) ; mt_reorg_hazard ( ) ; } } </s>

Fixup the looping instructions , do delayed branch scheduling , fixup scheduling hazards .


<s> void XCoreTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; DataSection = Ctx . getELFSection ( ".dp.data" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_WRITE | ELF :: XCORE_SHF_DP_SECTION , SectionKind :: getDataRel ( ) ) ; BSSSection = Ctx . getELFSection ( ".dp.bss" , ELF :: SHT_NOBITS , ELF :: SHF_ALLOC | ELF :: SHF_WRITE | ELF :: XCORE_SHF_DP_SECTION , SectionKind :: getBSS ( ) ) ; MergeableConst4Section = Ctx . getELFSection ( ".cp.rodata.cst4" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_MERGE | ELF :: XCORE_SHF_CP_SECTION , SectionKind :: getMergeableConst4 ( ) ) ; MergeableConst8Section = Ctx . getELFSection ( ".cp.rodata.cst8" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_MERGE | ELF :: XCORE_SHF_CP_SECTION , SectionKind :: getMergeableConst8 ( ) ) ; MergeableConst16Section = Ctx . getELFSection ( ".cp.rodata.cst16" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_MERGE | ELF :: XCORE_SHF_CP_SECTION , SectionKind :: getMergeableConst16 ( ) ) ; TLSDataSection = DataSection ; TLSBSSSection = BSSSection ; ReadOnlySection = Ctx . getELFSection ( ".cp.rodata" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: XCORE_SHF_CP_SECTION , SectionKind :: getReadOnlyWithRel ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s> const MCPhysReg * CAHPRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_SaveList ; } </s>


<s> void OutgoingValueHandler :: assignValueToAddress ( unsigned ValVReg , unsigned Addr , uint64_t Size , MachinePointerInfo & MPO ) { MachineMemOperand * MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , 0 ) ; MIRBuilder . buildStore ( ValVReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> static tree build_const_pointer ( tree t ) { return build_pointer_type ( build_qualified_type ( t , TYPE_QUAL_CONST ) ) ; } </s>

Return a representation of `` const T * '' .


<s> MachineBasicBlock :: iterator X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { bool reserveCallFrame = hasReservedCallFrame ( MF ) ; unsigned Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = TII . getFrameSize ( * I ) ; uint64_t InternalAmt = ( isDestroy || Amount ) ? TII . getFrameAdjustment ( * I ) : 0 ; I = MBB . erase ( I ) ; auto InsertPos = skipDebugInstructionsForward ( I , MBB . end ( ) ) ; if ( ! reserveCallFrame ) { unsigned StackAlign = getStackAlignment ( ) ; Amount = alignTo ( Amount , StackAlign ) ; const Function & F = MF . getFunction ( ) ; bool WindowsCFI = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool DwarfCFI = ! WindowsCFI && MF . needsFrameMoves ( ) ; bool HasDwarfEHHandlers = ! WindowsCFI && ! MF . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < X86MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == 0 ) return I ; Amount -= InternalAmt ; if ( isDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ; int64_t StackAdjustment = isDestroy ? Amount : - Amount ; if ( StackAdjustment ) { StackAdjustment += mergeSPUpdates ( MBB , InsertPos , true ) ; StackAdjustment += mergeSPUpdates ( MBB , InsertPos , false ) ; if ( StackAdjustment ) { if ( ! ( F . hasMinSize ( ) && adjustStackWithPops ( MBB , InsertPos , DL , StackAdjustment ) ) ) BuildStackAdjustment ( MBB , InsertPos , DL , StackAdjustment , false ) ; } } if ( DwarfCFI && ! hasFP ( MF ) ) { int64_t CfaAdjustment = - StackAdjustment ; if ( CfaAdjustment ) { BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , CfaAdjustment ) ) ; } } return I ; } if ( isDestroy && InternalAmt && ! blockEndIsUnreachable ( MBB , I ) ) { MachineBasicBlock :: iterator CI = I ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( CI != B && ! std :: prev ( CI ) -> isCall ( ) ) -- CI ; BuildStackAdjustment ( MBB , CI , DL , - InternalAmt , false ) ; } return I ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool isLegalMaskedLoad ( Type * DataType , Align Alignment ) { return isLegalMaskedLoadStore ( DataType , Alignment ) ; } </s>

Return true if the target supports masked load .


<s> bool AMDGPUPassConfig :: addInstSelector ( ) { addPass ( createAMDGPUISelDag ( getAMDGPUTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool MipsAsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { const unsigned FixupKind = Fixup . getKind ( ) ; switch ( FixupKind ) { default : return false ; case Mips :: fixup_Mips_CALL_HI16 : case Mips :: fixup_Mips_CALL_LO16 : case Mips :: fixup_Mips_CALL16 : case Mips :: fixup_Mips_GOT : case Mips :: fixup_Mips_GOT_PAGE : case Mips :: fixup_Mips_GOT_OFST : case Mips :: fixup_Mips_GOT_DISP : case Mips :: fixup_Mips_GOT_HI16 : case Mips :: fixup_Mips_GOT_LO16 : case Mips :: fixup_Mips_GOTTPREL : case Mips :: fixup_Mips_DTPREL_HI : case Mips :: fixup_Mips_DTPREL_LO : case Mips :: fixup_Mips_TLSGD : case Mips :: fixup_Mips_TLSLDM : case Mips :: fixup_Mips_TPREL_HI : case Mips :: fixup_Mips_TPREL_LO : case Mips :: fixup_Mips_JALR : case Mips :: fixup_MICROMIPS_CALL16 : case Mips :: fixup_MICROMIPS_GOT_DISP : case Mips :: fixup_MICROMIPS_GOT_PAGE : case Mips :: fixup_MICROMIPS_GOT_OFST : case Mips :: fixup_MICROMIPS_GOT16 : case Mips :: fixup_MICROMIPS_GOTTPREL : case Mips :: fixup_MICROMIPS_TLS_DTPREL_HI16 : case Mips :: fixup_MICROMIPS_TLS_DTPREL_LO16 : case Mips :: fixup_MICROMIPS_TLS_GD : case Mips :: fixup_MICROMIPS_TLS_LDM : case Mips :: fixup_MICROMIPS_TLS_TPREL_HI16 : case Mips :: fixup_MICROMIPS_TLS_TPREL_LO16 : case Mips :: fixup_MICROMIPS_JALR : return true ; } } </s>

Hook to check if a relocation is needed for some target specific reason .


<s>
StringRef
getPassName
(
)
const
override
{
return
"AMDGPU Promote Alloca to vector"
;
}
</s>

AMDGPU
"AMDGPU Promote Alloca to vector"


<s> static bool mips_hard_regno_mode_ok_p ( unsigned int regno , machine_mode mode ) { unsigned int size ; enum mode_class mclass ; if ( mode == CCV2mode ) return ( ISA_HAS_8CC && ST_REG_P ( regno ) && ( regno - ST_REG_FIRST ) % 2 == 0 ) ; if ( mode == CCV4mode ) return ( ISA_HAS_8CC && ST_REG_P ( regno ) && ( regno - ST_REG_FIRST ) % 4 == 0 ) ; if ( mode == CCmode ) return ISA_HAS_8CC ? ST_REG_P ( regno ) : regno == FPSW_REGNUM ; size = GET_MODE_SIZE ( mode ) ; mclass = GET_MODE_CLASS ( mode ) ; if ( GP_REG_P ( regno ) && mode != CCFmode ) return ( ( regno - GP_REG_FIRST ) & 1 ) == 0 || size <= UNITS_PER_WORD ; if ( FP_REG_P ( regno ) && ( ( ( regno - FP_REG_FIRST ) % MAX_FPRS_PER_FMT ) == 0 || ( MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG ) ) ) { if ( TARGET_O32_FP64A_ABI && size <= 4 && ( regno & 1 ) != 0 ) return false ; if ( mode == CCFmode ) return ! ( TARGET_FLOATXX && ( regno & 1 ) != 0 ) ; if ( TARGET_LOONGSON_VECTORS && ( mode == V2SImode || mode == V4HImode || mode == V8QImode || mode == DImode ) ) return true ; if ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT || mclass == MODE_VECTOR_FLOAT ) return size <= UNITS_PER_FPVALUE ; if ( mclass == MODE_INT ) return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG ; } if ( ACC_REG_P ( regno ) && ! VECTOR_MODE_P ( mode ) && ( INTEGRAL_MODE_P ( mode ) || ALL_FIXED_POINT_MODE_P ( mode ) ) ) { if ( MD_REG_P ( regno ) ) { if ( size <= UNITS_PER_WORD * 2 ) return regno == ( size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST ) ; } else { if ( size <= UNITS_PER_WORD ) return true ; if ( size <= UNITS_PER_WORD * 2 && ( ( regno - DSP_ACC_REG_FIRST ) & 1 ) == 0 ) return true ; } } if ( ALL_COP_REG_P ( regno ) ) return mclass == MODE_INT && size <= UNITS_PER_WORD ; if ( regno == GOT_VERSION_REGNUM ) return mode == SImode ; return false ; } </s>

Return true if register REGNO can store a value of mode MODE . The result of this function is cached in mips_hard_regno_mode_ok .


<s>
bool
PPCAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
{
if
(
ExtraCode
[
1
]
!=
0
)
return
true
;
switch
(
ExtraCode
[
0
]
)
{
default
:
return
true
;
case
'L'
:
O
<<
getDataLayout
(
)
.
getPointerSize
(
)
<<
"("
;
printOperand
(
MI
,
OpNo
,
O
)
;
O
<<
")"
;
return
false
;
case
'y'
:
{
const
char
*
RegName
=
"r0"
;
if
(
!
Subtarget
->
isDarwin
(
)
)
RegName
=
PPCRegisterInfo
::
stripRegisterPrefix
(
RegName
)
;
O
<<
RegName
<<
", "
;
printOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
}
case
'U'
:
case
'X'
:
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
return
false
;
}
}
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
O
<<
"0("
;
printOperand
(
MI
,
OpNo
,
O
)
;
O
<<
")"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> TargetLowering :: ConstraintType SystemZTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'a' : case 'd' : case 'f' : case 'h' : case 'r' : return C_RegisterClass ; case 'Q' : case 'R' : case 'S' : case 'T' : case 'm' : return C_Memory ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : return C_Other ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> const MCPhysReg * XCoreRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const MCPhysReg CalleeSavedRegs [ ] = { XCore :: R4 , XCore :: R5 , XCore :: R6 , XCore :: R7 , XCore :: R8 , XCore :: R9 , XCore :: R10 , 0 } ; static const MCPhysReg CalleeSavedRegsFP [ ] = { XCore :: R4 , XCore :: R5 , XCore :: R6 , XCore :: R7 , XCore :: R8 , XCore :: R9 , 0 } ; const TargetFrameLowering * TFI = MF -> getSubtarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( * MF ) ) return CalleeSavedRegsFP ; return CalleeSavedRegs ; } </s>


<s> static bool zero_all_mm_registers ( HARD_REG_SET need_zeroed_hardregs , unsigned int ret_mmx_regno ) { bool need_zero_all_mm = false ; for ( unsigned int regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( STACK_REGNO_P ( regno ) && TEST_HARD_REG_BIT ( need_zeroed_hardregs , regno ) ) { need_zero_all_mm = true ; break ; } if ( ! need_zero_all_mm ) return false ; machine_mode mode = V2SImode ; for ( unsigned int regno = FIRST_MMX_REG ; regno <= LAST_MMX_REG ; regno ++ ) if ( regno != ret_mmx_regno ) { rtx reg = gen_rtx_REG ( mode , regno ) ; emit_insn ( gen_rtx_SET ( reg , CONST0_RTX ( mode ) ) ) ; } return true ; } </s>

When the routine exit in MMX mode , if any ST register needs to be zeroed , we should clear all MMX registers except the RET_MMX_REGNO that holds the return value .


"passing %wd to argument %d of %qE, which expects"

Report that LOCATION has a call to FNDECL in which argument ARGNO has the value ACTUAL , whereas the function requires a value in the range [ MIN , MAX ] . ARGNO counts from zero .


<s> bool WebAssemblyTargetLowering :: CanLowerReturn ( CallingConv :: ID , MachineFunction & , bool , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & ) const { return Subtarget -> hasMultivalue ( ) || Outs . size ( ) <= 1 ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .

WebAssembly WebAssembly ISD::OutputArg 1


"256-bit vector operations only available in AVX2"

"Can only select PackedSingle or PackedDouble"

"256-bit insert/extract only available in AVX2"

Change the opcode of MI to execute in Domain .


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
READ_REGISTER
:
ExpandREAD_REGISTER
(
N
,
Results
,
DAG
)
;
break
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
case
ISD
::
SHL
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SREM
:
case
ISD
::
UREM
:
Res
=
LowerREM
(
N
,
DAG
)
;
break
;
case
ISD
::
SDIVREM
:
case
ISD
::
UDIVREM
:
Res
=
LowerDivRem
(
SDValue
(
N
,
0
)
,
DAG
)
;
assert
(
Res
.
getNumOperands
(
)
==
2
&&
"DivRem needs two values"
)
;
Results
.
push_back
(
Res
.
getValue
(
0
)
)
;
Results
.
push_back
(
Res
.
getValue
(
1
)
)
;
return
;
case
ISD
::
SADDSAT
:
case
ISD
::
SSUBSAT
:
case
ISD
::
UADDSAT
:
case
ISD
::
USUBSAT
:
Res
=
LowerADDSUBSAT
(
SDValue
(
N
,
0
)
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
READCYCLECOUNTER
:
ReplaceREADCYCLECOUNTER
(
N
,
Results
,
DAG
,
Subtarget
)
;
return
;
case
ISD
::
UDIV
:
case
ISD
::
SDIV
:
assert
(
Subtarget
->
isTargetWindows
(
)
&&
"can only expand DIV on Windows"
)
;
return
ExpandDIV_Windows
(
SDValue
(
N
,
0
)
,
DAG
,
N
->
getOpcode
(
)
==
ISD
::
SDIV
,
Results
)
;
case
ISD
::
ATOMIC_CMP_SWAP
:
ReplaceCMP_SWAP_64Results
(
N
,
Results
,
DAG
)
;
return
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
ReplaceLongIntrinsic
(
N
,
Results
,
DAG
)
;
case
ISD
::
ABS
:
lowerABS
(
N
,
Results
,
DAG
)
;
return
;
case
ISD
::
LOAD
:
LowerLOAD
(
N
,
Results
,
DAG
)
;
break
;
case
ISD
::
TRUNCATE
:
Res
=
LowerTruncate
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SIGN_EXTEND
:
case
ISD
::
ZERO_EXTEND
:
Res
=
LowerVectorExtend
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
FP_TO_SINT_SAT
:
case
ISD
::
FP_TO_UINT_SAT
:
Res
=
LowerFP_TO_INT_SAT
(
SDValue
(
N
,
0
)
,
DAG
,
Subtarget
)
;
break
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> static rtx nvptx_cta_sync ( rtx lock , int threads ) { return gen_nvptx_barsync ( lock , GEN_INT ( threads ) ) ; } </s>

Emit a CTA-level synchronization barrier . LOCK is the barrier number , which is an integer or a register . THREADS is the number of threads controlled by the barrier .


<s> static void aarch64_setup_incoming_varargs ( cumulative_args_t cum_v , machine_mode mode , tree type , int * pretend_size ATTRIBUTE_UNUSED , int no_rtl ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; CUMULATIVE_ARGS local_cum ; int gr_saved = cfun -> va_list_gpr_size ; int vr_saved = cfun -> va_list_fpr_size ; local_cum = * cum ; aarch64_function_arg_advance ( pack_cumulative_args ( & local_cum ) , mode , type , true ) ; if ( cfun -> va_list_gpr_size ) gr_saved = MIN ( NUM_ARG_REGS - local_cum . aapcs_ncrn , cfun -> va_list_gpr_size / UNITS_PER_WORD ) ; if ( cfun -> va_list_fpr_size ) vr_saved = MIN ( NUM_FP_ARG_REGS - local_cum . aapcs_nvrn , cfun -> va_list_fpr_size / UNITS_PER_VREG ) ; if ( ! TARGET_FLOAT ) { gcc_assert ( local_cum . aapcs_nvrn == 0 ) ; vr_saved = 0 ; } if ( ! no_rtl ) { if ( gr_saved > 0 ) { rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , - gr_saved * UNITS_PER_WORD ) ; mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . aapcs_ncrn + R0_REGNUM , mem , gr_saved ) ; } if ( vr_saved > 0 ) { machine_mode mode = TImode ; int off , i , vr_start ; off = - ROUND_UP ( gr_saved * UNITS_PER_WORD , STACK_BOUNDARY / BITS_PER_UNIT ) ; off -= vr_saved * UNITS_PER_VREG ; vr_start = V0_REGNUM + local_cum . aapcs_nvrn ; for ( i = 0 ; i < vr_saved ; ++ i ) { rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , off ) ; mem = gen_frame_mem ( mode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; aarch64_emit_move ( mem , gen_rtx_REG ( mode , vr_start + i ) ) ; off += UNITS_PER_VREG ; } } } cfun -> machine -> frame . saved_varargs_size = ( ROUND_UP ( gr_saved * UNITS_PER_WORD , STACK_BOUNDARY / BITS_PER_UNIT ) + vr_saved * UNITS_PER_VREG ) ; } </s>


<s> Register ( const MachineOperand & Op ) : Reg ( Op . getReg ( ) ) , Sub ( Op . getSubReg ( ) ) { } </s>


<s> bool AMDGPUPassConfig :: addPreISel ( ) { const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . getGeneration ( ) > AMDGPUSubtarget :: NORTHERN_ISLANDS ) { addPass ( createStructurizeCFGPass ( ) ) ; addPass ( createSIAnnotateControlFlowPass ( ) ) ; } else { addPass ( createR600TextureIntrinsicsReplacer ( ) ) ; } return false ; } </s>


<s> const char * output_fix_trunc ( rtx insn , rtx * operands , int fisttp ) { int stack_top_dies = find_regno_note ( insn , REG_DEAD , FIRST_STACK_REG ) != 0 ; int dimode_p = GET_MODE ( operands [ 0 ] ) == DImode ; int round_mode = get_attr_i387_cw ( insn ) ; if ( ( dimode_p || fisttp ) && ! stack_top_dies ) output_asm_insn ( "fld\t%y1" , operands ) ; gcc_assert ( STACK_TOP_P ( operands [ 1 ] ) ) ; gcc_assert ( GET_CODE ( operands [ 0 ] ) == MEM ) ; if ( fisttp ) output_asm_insn ( "fisttp%z0\t%0" , operands ) ; else { if ( round_mode != I387_CW_ANY ) output_asm_insn ( "fldcw\t%3" , operands ) ; if ( stack_top_dies || dimode_p ) output_asm_insn ( "fistp%z0\t%0" , operands ) ; else output_asm_insn ( "fist%z0\t%0" , operands ) ; if ( round_mode != I387_CW_ANY ) output_asm_insn ( "fldcw\t%2" , operands ) ; } return "" ; } </s>

Output code for INSN to convert a float to a signed int . OPERANDS are the insn operands . The output may be [ HSD ] Imode and the input operand may be [ SDX ] Fmode .


<s> bool doInitialization ( Module & M ) override { SMShadowTracker . reset ( 0 ) ; SM . reset ( ) ; return AsmPrinter :: doInitialization ( M ) ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> const LC3InstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> const MachineFunction & getMachineFunction ( ) const { return MF ; } </s>

getMachineFunction - Return the last machine function computed .


<s> bool GCNDPPCombine :: runOnMachineFunction ( MachineFunction & MF ) { ST = & MF . getSubtarget < GCNSubtarget > ( ) ; if ( ! ST -> hasDPP ( ) || skipFunction ( MF . getFunction ( ) ) ) return false ; MRI = & MF . getRegInfo ( ) ; TII = ST -> getInstrInfo ( ) ; bool Changed = false ; for ( auto & MBB : MF ) { for ( MachineInstr & MI : llvm :: make_early_inc_range ( llvm :: reverse ( MBB ) ) ) { if ( MI . getOpcode ( ) == AMDGPU :: V_MOV_B32_dpp && combineDPPMov ( MI ) ) { Changed = true ; ++ NumDPPMovsCombined ; } else if ( MI . getOpcode ( ) == AMDGPU :: V_MOV_B64_DPP_PSEUDO || MI . getOpcode ( ) == AMDGPU :: V_MOV_B64_dpp ) { if ( ST -> has64BitDPP ( ) && combineDPPMov ( MI ) ) { Changed = true ; ++ NumDPPMovsCombined ; } else { auto Split = TII -> expandMovDPP64 ( MI ) ; for ( auto M : { Split . first , Split . second } ) { if ( M && combineDPPMov ( * M ) ) ++ NumDPPMovsCombined ; } Changed = true ; } } } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> static void aarch64_output_mi_thunk ( FILE * file , tree thunk ATTRIBUTE_UNUSED , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { int this_regno = R0_REGNUM ; rtx this_rtx , temp0 , temp1 , addr , funexp ; rtx_insn * insn ; if ( aarch64_bti_enabled ( ) ) emit_insn ( gen_bti_c ( ) ) ; reload_completed = 1 ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; this_rtx = gen_rtx_REG ( Pmode , this_regno ) ; temp0 = gen_rtx_REG ( Pmode , EP0_REGNUM ) ; temp1 = gen_rtx_REG ( Pmode , EP1_REGNUM ) ; if ( vcall_offset == 0 ) aarch64_add_offset ( Pmode , this_rtx , this_rtx , delta , temp1 , temp0 , false ) ; else { gcc_assert ( ( vcall_offset & ( POINTER_BYTES - 1 ) ) == 0 ) ; addr = this_rtx ; if ( delta != 0 ) { if ( delta >= - 256 && delta < 256 ) addr = gen_rtx_PRE_MODIFY ( Pmode , this_rtx , plus_constant ( Pmode , this_rtx , delta ) ) ; else aarch64_add_offset ( Pmode , this_rtx , this_rtx , delta , temp1 , temp0 , false ) ; } if ( Pmode == ptr_mode ) aarch64_emit_move ( temp0 , gen_rtx_MEM ( ptr_mode , addr ) ) ; else aarch64_emit_move ( temp0 , gen_rtx_ZERO_EXTEND ( Pmode , gen_rtx_MEM ( ptr_mode , addr ) ) ) ; if ( vcall_offset >= - 256 && vcall_offset < 4096 * POINTER_BYTES ) addr = plus_constant ( Pmode , temp0 , vcall_offset ) ; else { aarch64_internal_mov_immediate ( temp1 , GEN_INT ( vcall_offset ) , true , Pmode ) ; addr = gen_rtx_PLUS ( Pmode , temp0 , temp1 ) ; } if ( Pmode == ptr_mode ) aarch64_emit_move ( temp1 , gen_rtx_MEM ( ptr_mode , addr ) ) ; else aarch64_emit_move ( temp1 , gen_rtx_SIGN_EXTEND ( Pmode , gen_rtx_MEM ( ptr_mode , addr ) ) ) ; emit_insn ( gen_add2_insn ( this_rtx , temp1 ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = 1 ; } funexp = XEXP ( DECL_RTL ( function ) , 0 ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx , NULL_RTX ) ) ; SIBLING_CALL_P ( insn ) = 1 ; insn = get_insns ( ) ; shorten_branches ( insn ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; reload_completed = 0 ; } </s>

Output code to add DELTA to the first argument , and then jump to FUNCTION . Used for C++ multiple inheritance .


<s> unsigned ARMTargetLowering :: getNumInterleavedAccesses ( VectorType * VecTy , const DataLayout & DL ) const { return ( DL . getTypeSizeInBits ( VecTy ) + 127 ) / 128 ; } </s>

Returns the number of interleaved accesses that will be generated when lowering accesses of the given type .


<s> const M680x0RegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> X86MCTargetExpr * X86MCTargetExpr :: Create ( const MCSymbol * Sym , VariantKind K , MCContext & Ctx ) { return new ( Ctx ) X86MCTargetExpr ( Sym , K ) ; } </s>

Construct a unary instruction , given the opcode and an operand .


<s> bool sh_attr_renesas_p ( const_tree td ) { if ( TARGET_HITACHI ) return true ; if ( td == NULL_TREE ) return false ; if ( DECL_P ( td ) ) td = TREE_TYPE ( td ) ; if ( td == error_mark_node ) return false ; return ( lookup_attribute ( "renesas" , TYPE_ATTRIBUTES ( td ) ) != NULL_TREE ) ; } </s>

True if __attribute__ ( ( renesas ) ) or -mrenesas .


<s> SDNode * MipsDAGToDAGISel :: getGlobalBaseReg ( bool IsForTls ) { Register GlobalBaseReg = MF -> getInfo < MipsFunctionInfo > ( ) -> getGlobalBaseReg ( * MF , IsForTls ) ; return CurDAG -> getRegister ( GlobalBaseReg , getTargetLowering ( ) -> getPointerTy ( CurDAG -> getDataLayout ( ) , 0 ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static void require_pic_register ( void ) { if ( ! crtl -> uses_pic_offset_table ) { gcc_assert ( can_create_pseudo_p ( ) ) ; if ( arm_pic_register != INVALID_REGNUM && ! ( TARGET_THUMB1 && arm_pic_register > LAST_LO_REGNUM ) ) { if ( ! cfun -> machine -> pic_reg ) cfun -> machine -> pic_reg = gen_rtx_REG ( Pmode , arm_pic_register ) ; if ( current_ir_type ( ) != IR_GIMPLE || currently_expanding_to_rtl ) crtl -> uses_pic_offset_table = 1 ; } else { rtx_insn * seq , * insn ; if ( ! cfun -> machine -> pic_reg ) cfun -> machine -> pic_reg = gen_reg_rtx ( Pmode ) ; if ( current_ir_type ( ) != IR_GIMPLE || currently_expanding_to_rtl ) { crtl -> uses_pic_offset_table = 1 ; start_sequence ( ) ; if ( TARGET_THUMB1 && arm_pic_register != INVALID_REGNUM && arm_pic_register > LAST_LO_REGNUM ) emit_move_insn ( cfun -> machine -> pic_reg , gen_rtx_REG ( Pmode , arm_pic_register ) ) ; else arm_load_pic_register ( 0UL ) ; seq = get_insns ( ) ; end_sequence ( ) ; for ( insn = seq ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) ) INSN_LOCATION ( insn ) = prologue_location ; insert_insn_on_edge ( seq , single_succ_edge ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) ) ; } } } } </s>

Record that the current function needs a PIC register . Initialize cfun- > machine- > pic_reg if we have not already done so .


<s> void function_expander :: add_integer_operand ( HOST_WIDE_INT x ) { m_ops . safe_grow ( m_ops . length ( ) + 1 , true ) ; create_integer_operand ( & m_ops . last ( ) , x ) ; } </s>


<s> static void aarch64_emit_sve_fp_cond ( rtx target , rtx_code code , rtx pred , bool known_ptrue_p , rtx op0 , rtx op1 ) { rtx flag = gen_int_mode ( known_ptrue_p , SImode ) ; rtx unspec = gen_rtx_UNSPEC ( GET_MODE ( pred ) , gen_rtvec ( 4 , pred , flag , op0 , op1 ) , aarch64_unspec_cond_code ( code ) ) ; emit_set_insn ( target , unspec ) ; } </s>

Emit : ( set TARGET ( unspec [ PRED KNOWN_PTRUE_P OP0 OP1 ] UNSPEC_COND_ < X > ) ) where < X > is the operation associated with comparison CODE . KNOWN_PTRUE_P is true if PRED is known to be a PTRUE .


<s> bool MipsTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { if ( VT != MVT :: f32 && VT != MVT :: f64 ) return false ; if ( Imm . isNegZero ( ) ) return false ; return Imm . isZero ( ) ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> static void mips_end_function_definition ( const char * name ) { if ( ! flag_inhibit_size_directive ) { fputs ( "\t.end\t" , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; fputs ( "\n" , asm_out_file ) ; } } </s>

End a function definition started by mips_start_function_definition .


<s> MCDisassembler :: DecodeStatus XCoreDisassembler :: getInstruction ( MCInst & instr , uint64_t & Size , const MemoryObject & Region , uint64_t Address , raw_ostream & vStream , raw_ostream & cStream ) const { uint16_t insn16 ; if ( ! readInstruction16 ( Region , Address , Size , insn16 ) ) { return Fail ; } DecodeStatus Result = decodeInstruction ( DecoderTable16 , instr , insn16 , Address , this , STI ) ; if ( Result != Fail ) { Size = 2 ; return Result ; } uint32_t insn32 ; if ( ! readInstruction32 ( Region , Address , Size , insn32 ) ) { return Fail ; } Result = decodeInstruction ( DecoderTable32 , instr , insn32 , Address , this , STI ) ; if ( Result != Fail ) { Size = 4 ; return Result ; } return Fail ; } </s>

Returns the disassembly of a single instruction .


"parameter passing for argument of type %qT when C++17 "

"is enabled changed to match C++14 %{in GCC 10.1%}"

"parameter passing for argument of type %qT with "

"%<[[no_unique_address]]%> members changed "

"zero-width bit fields members changed in GCC 12"

Return true if a variable of TYPE should be passed as single value with type CODE . If STRICT_SIZE_CHECK_P is true the sizes of the record type and the field type must match . The ABI says that record types with a single member are treated just like that member would be . This function is a helper to detect such cases . The function also produces the proper diagnostics for cases where the outcome might be different depending on the GCC version .


<s> iterator_range < function_sym_iterator > HSACodeObject :: functions ( ) const { return make_range ( functions_begin ( ) , functions_end ( ) ) ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { TargetTransformInfo :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool aarch64_use_return_insn_p ( void ) { if ( ! reload_completed ) return false ; if ( crtl -> profile ) return false ; aarch64_layout_frame ( ) ; return cfun -> machine -> frame . frame_size == 0 ; } </s>

Return TRUE if we can use a simple_return insn . This function checks whether the callee saved stack is empty , which means no restore actions are need . The pro_and_epilogue will use this to check whether shrink-wrapping opt is feasible .


"AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "


<s> bool aarch64_sve_ld1rq_operand_p ( rtx op ) { return aarch64_sve_ld1rq_ld1ro_operand_p ( op , TImode , GET_MODE_INNER ( GET_MODE ( op ) ) ) ; } </s>

Return true if OP is a valid MEM operand for an SVE LD1RQ instruction .


<s> bool AMDGPUAnnotateKernelFeatures :: runOnModule ( Module & M ) { Triple TT ( M . getTargetTriple ( ) ) ; static const StringRef IntrinsicToAttr [ ] [ 2 ] = { { "llvm.amdgcn.workitem.id.y" , "amdgpu-work-item-id-y" } , { "llvm.amdgcn.workitem.id.z" , "amdgpu-work-item-id-z" } , { "llvm.amdgcn.workgroup.id.y" , "amdgpu-work-group-id-y" } , { "llvm.amdgcn.workgroup.id.z" , "amdgpu-work-group-id-z" } , { "llvm.r600.read.tgid.y" , "amdgpu-work-group-id-y" } , { "llvm.r600.read.tgid.z" , "amdgpu-work-group-id-z" } , { "llvm.r600.read.tidig.y" , "amdgpu-work-item-id-y" } , { "llvm.r600.read.tidig.z" , "amdgpu-work-item-id-z" } } ; static const StringRef HSAIntrinsicToAttr [ ] [ 2 ] = { { "llvm.amdgcn.dispatch.ptr" , "amdgpu-dispatch-ptr" } , { "llvm.amdgcn.queue.ptr" , "amdgpu-queue-ptr" } , { "llvm.amdgcn.dispatch.id" , "amdgpu-dispatch-id" } , { "llvm.trap" , "amdgpu-queue-ptr" } } ; bool Changed = addAttrsForIntrinsics ( M , IntrinsicToAttr ) ; if ( TT . getOS ( ) == Triple :: AMDHSA || TT . getOS ( ) == Triple :: Mesa3D ) { Changed |= addAttrsForIntrinsics ( M , HSAIntrinsicToAttr ) ; for ( Function & F : M ) { if ( F . hasFnAttribute ( "amdgpu-queue-ptr" ) ) continue ; if ( hasAddrSpaceCast ( F ) ) F . addFnAttr ( "amdgpu-queue-ptr" ) ; } } return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


Initialize the transactional memory extension ( TME ) builtins .


<s> static void rs6000_set_default_type_attributes ( tree type ) { if ( rs6000_default_long_calls && ( TREE_CODE ( type ) == FUNCTION_TYPE || TREE_CODE ( type ) == METHOD_TYPE ) ) TYPE_ATTRIBUTES ( type ) = tree_cons ( get_identifier ( "longcall" ) , NULL_TREE , TYPE_ATTRIBUTES ( type ) ) ; darwin_set_default_type_attributes ( type ) ; } </s>

Set longcall attributes on all functions declared when rs6000_default_long_calls is true .


<s> const char * BlackfinTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case BFISD :: CALL : return "BFISD::CALL" ; case BFISD :: RET_FLAG : return "BFISD::RET_FLAG" ; case BFISD :: Wrapper : return "BFISD::Wrapper" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static int group_barrier_needed ( rtx_insn * insn ) { rtx pat ; int need_barrier = 0 ; struct reg_flags flags ; memset ( & flags , 0 , sizeof ( flags ) ) ; switch ( GET_CODE ( insn ) ) { case NOTE : case DEBUG_INSN : break ; case BARRIER : break ; case CODE_LABEL : memset ( rws_insn , 0 , sizeof ( rws_insn ) ) ; return 1 ; case CALL_INSN : flags . is_branch = 1 ; flags . is_sibcall = SIBLING_CALL_P ( insn ) ; memset ( rws_insn , 0 , sizeof ( rws_insn ) ) ; if ( ( pat = prev_active_insn ( insn ) ) && CALL_P ( pat ) ) { need_barrier = 1 ; break ; } need_barrier = rtx_needs_barrier ( PATTERN ( insn ) , flags , 0 ) ; break ; case JUMP_INSN : if ( ! ia64_spec_check_p ( insn ) ) flags . is_branch = 1 ; if ( ( pat = prev_active_insn ( insn ) ) && CALL_P ( pat ) ) { need_barrier = 1 ; break ; } case INSN : if ( GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) break ; pat = PATTERN ( insn ) ; switch ( recog_memoized ( insn ) ) { case CODE_FOR_epilogue_deallocate_stack : case CODE_FOR_prologue_allocate_stack : pat = XVECEXP ( pat , 0 , 0 ) ; break ; case CODE_FOR_doloop_end_internal : pat = XVECEXP ( pat , 0 , 1 ) ; break ; case CODE_FOR_pred_rel_mutex : case CODE_FOR_prologue_use : return 0 ; default : break ; } memset ( rws_insn , 0 , sizeof ( rws_insn ) ) ; need_barrier = rtx_needs_barrier ( pat , flags , 0 ) ; if ( ! need_barrier ) need_barrier = rws_access_regno ( REG_VOLATILE , flags , 0 ) ; break ; default : gcc_unreachable ( ) ; } if ( first_instruction && important_for_bundling_p ( insn ) ) { need_barrier = 0 ; first_instruction = 0 ; } return need_barrier ; } </s>

Given the current state , determine whether a group barrier ( a stop bit ) is necessary before INSN . Return nonzero if so . This modifies the state to include the effects of INSN as a side-effect .


<s> const char * get_bundle_name ( int b ) { return bundle_name [ b ] ; } </s>


<s> static bool arm_evpc_neon_vtrn ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> nelt ; rtx out0 , out1 , in0 , in1 , x ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; if ( d -> perm [ 0 ] == 0 ) odd = 0 ; else if ( d -> perm [ 0 ] == 1 ) odd = 1 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt ; i += 2 ) { if ( d -> perm [ i ] != i + odd ) return false ; if ( d -> perm [ i + 1 ] != ( ( i + nelt + odd ) & mask ) ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vtrnv16qi_internal ; break ; case V8QImode : gen = gen_neon_vtrnv8qi_internal ; break ; case V8HImode : gen = gen_neon_vtrnv8hi_internal ; break ; case V4HImode : gen = gen_neon_vtrnv4hi_internal ; break ; case V4SImode : gen = gen_neon_vtrnv4si_internal ; break ; case V2SImode : gen = gen_neon_vtrnv2si_internal ; break ; case V2SFmode : gen = gen_neon_vtrnv2sf_internal ; break ; case V4SFmode : gen = gen_neon_vtrnv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN ) { x = in0 , in0 = in1 , in1 = x ; odd = ! odd ; } out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( odd ) x = out0 , out0 = out1 , out1 = x ; emit_insn ( gen ( out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s> const HexagonSubtarget * HexagonTargetMachine :: getSubtargetImpl ( const Function & F ) const { AttributeList FnAttrs = F . getAttributes ( ) ; Attribute CPUAttr = FnAttrs . getAttribute ( AttributeList :: FunctionIndex , "target-cpu" ) ; Attribute FSAttr = FnAttrs . getAttribute ( AttributeList :: FunctionIndex , "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; if ( FnAttrs . hasFnAttribute ( "unsafe-fp-math" ) && F . getFnAttribute ( "unsafe-fp-math" ) . getValueAsString ( ) == "true" ) FS = FS . empty ( ) ? "+unsafe-fp" : "+unsafe-fp," + FS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < HexagonSubtarget > ( TargetTriple , CPU , FS , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

Hexagon Hexagon Hexagon "target-cpu" "target-features" "unsafe-fp-math" "unsafe-fp-math" "true" "+unsafe-fp" "+unsafe-fp," Hexagon


"=== RegBanks reassign analysis on function "

"RegBank reassign stall cycles verification failed."

runOnMachineFunction - Emit the function body .


<s> ScheduleHazardRecognizer * ARMBaseInstrInfo :: CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II , const ScheduleDAG * DAG ) const { if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2Base ( ) ) return ( ScheduleHazardRecognizer * ) new ARMHazardRecognizer ( II , DAG ) ; return TargetInstrInfo :: CreateTargetPostRAHazardRecognizer ( II , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for by non-scheduling passes .


"Can't store this register to stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> static const struct processor * aarch64_get_arch ( enum aarch64_arch arch ) { if ( arch != aarch64_no_arch ) return & all_architectures [ arch ] ; const struct processor * cpu = & all_cores [ TARGET_CPU_DEFAULT & 0x3f ] ; return & all_architectures [ cpu -> arch ] ; } </s>

Return the architecture corresponding to the enum ARCH . If it does n't specify a valid architecture , return the default .


<s> MCOperand LM32MCInstLower :: lowerOperand ( const MachineOperand & MO ) const { switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : return MCOperand :: CreateReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: CreateImm ( MO . getImm ( ) ) ; default : return MCOperand :: CreateExpr ( getExpr ( MO ) ) ; } } </s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> bool hasCompressedExport ( ) const { return ! GFX11Insts ; } </s>

Return true if the target 's EXP instruction has the COMPR flag , which affects the meaning of the EN ( enable ) bits .


<s>
rtx
function_expander
::
generate_insn
(
insn_code
icode
)
{
gcc_assert
(
opno
==
insn_data
[
icode
]
.
n_generator_args
)
;
if
(
!
maybe_expand_insn
(
icode
,
opno
,
m_ops
)
)
{
error
(
"invalid argument to built-in function"
)
;
return
NULL_RTX
;
}
return
function_returns_void_p
(
)
const0_rtx
:
m_ops
[
0
]
.
value
;
}
</s>

Generate instruction ICODE , given that its operands have already been added to M_OPS . Return the value of the first operand .

riscv
"invalid argument to built-in function"
0


<s> const RegisterBank & AMDGPURegisterBankInfo :: getRegBankFromRegClass ( const TargetRegisterClass & RC ) const { if ( & RC == & AMDGPU :: SReg_1RegClass ) return AMDGPU :: VCCRegBank ; if ( TRI -> isSGPRClass ( & RC ) ) return AMDGPU :: SGPRRegBank ; if ( TRI -> isAGPRClass ( & RC ) ) return AMDGPU :: AGPRRegBank ; return AMDGPU :: VGPRRegBank ; } </s>

AMDGPU AMDGPU AMDGPU::SReg_1RegClass AMDGPU::VCCRegBank AMDGPU::SGPRRegBank AMDGPU::AGPRRegBank AMDGPU::VGPRRegBank


<s> void JVMAsmBackend :: relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const { return ; } </s>

Relax the instruction in the given fragment to the next wider instruction .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> static bool aarch64_option_valid_attribute_p ( tree fndecl , tree , tree args , int ) { struct cl_target_option cur_target ; bool ret ; tree old_optimize ; tree new_target , new_optimize ; tree existing_target = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( ! existing_target && args == current_target_pragma ) { DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = target_option_current_node ; return true ; } tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; old_optimize = build_optimization_node ( & global_options , & global_options_set ) ; func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( func_optimize && func_optimize != old_optimize ) cl_optimization_restore ( & global_options , & global_options_set , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_save ( & cur_target , & global_options , & global_options_set ) ; if ( existing_target ) { struct cl_target_option * existing_options = TREE_TARGET_OPTION ( existing_target ) ; if ( existing_options ) cl_target_option_restore ( & global_options , & global_options_set , existing_options ) ; } else cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( target_option_current_node ) ) ; ret = aarch64_process_target_attr ( args ) ; if ( ret ) { aarch64_override_options_internal ( & global_options ) ; if ( TARGET_SIMD ) { tree saved_current_target_pragma = current_target_pragma ; current_target_pragma = NULL ; aarch64_init_simd_builtins ( ) ; current_target_pragma = saved_current_target_pragma ; } new_target = build_target_option_node ( & global_options , & global_options_set ) ; } else new_target = NULL ; new_optimize = build_optimization_node ( & global_options , & global_options_set ) ; if ( fndecl && ret ) { DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = new_target ; if ( old_optimize != new_optimize ) DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) = new_optimize ; } cl_target_option_restore ( & global_options , & global_options_set , & cur_target ) ; if ( old_optimize != new_optimize ) cl_optimization_restore ( & global_options , & global_options_set , TREE_OPTIMIZATION ( old_optimize ) ) ; return ret ; } </s>

Implement TARGET_OPTION_VALID_ATTRIBUTE_P . This is used to process attribute ( ( target ( `` ... '' ) ) ) .


<s>
void
i386_pe_asm_output_aligned_decl_common
(
FILE
*
stream
,
tree
decl
,
const
char
*
name
,
HOST_WIDE_INT
size
,
HOST_WIDE_INT
align
)
{
HOST_WIDE_INT
rounded
;
rounded
=
size
size
:
1
;
rounded
+=
(
BIGGEST_ALIGNMENT
/
BITS_PER_UNIT
)
1
;
rounded
=
(
rounded
/
(
BIGGEST_ALIGNMENT
/
BITS_PER_UNIT
)
*
(
BIGGEST_ALIGNMENT
/
BITS_PER_UNIT
)
)
;
i386_pe_maybe_record_exported_symbol
(
decl
,
name
,
1
)
;
fprintf
(
stream
,
"\t.comm\t"
)
;
assemble_name
(
stream
,
name
)
;
if
(
use_pe_aligned_common
)
fprintf
(
stream
,
", "
HOST_WIDE_INT_PRINT_DEC
", %d\n"
,
size
size
:
(
HOST_WIDE_INT
)
1
,
exact_log2
(
align
)
exact_log2
(
CHAR_BIT
)
)
;
else
fprintf
(
stream
,
", "
HOST_WIDE_INT_PRINT_DEC
"\t"
ASM_COMMENT_START
" "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
rounded
,
size
)
;
}
</s>

Beware , DECL may be NULL if compile_file ( ) is emitting the LTO marker .


<s> bool WebAssemblyFastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Call : if ( selectCall ( I ) ) return true ; break ; case Instruction :: Select : return selectSelect ( I ) ; case Instruction :: Trunc : return selectTrunc ( I ) ; case Instruction :: ZExt : return selectZExt ( I ) ; case Instruction :: SExt : return selectSExt ( I ) ; case Instruction :: ICmp : return selectICmp ( I ) ; case Instruction :: FCmp : return selectFCmp ( I ) ; case Instruction :: BitCast : return selectBitCast ( I ) ; case Instruction :: Load : return selectLoad ( I ) ; case Instruction :: Store : return selectStore ( I ) ; case Instruction :: Br : return selectBr ( I ) ; case Instruction :: Ret : return selectRet ( I ) ; case Instruction :: Unreachable : return selectUnreachable ( I ) ; default : break ; } return selectOperator ( I , I -> getOpcode ( ) ) ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> unsigned OR1KTargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) const { return OR1K :: R4 ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .


<s> bool useAA ( ) const override { return UseAA ; } </s>

Enable use of alias analysis during code generation ( during MI scheduling , DAGCombine , etc . ) .


<s> static void emit_load_locked ( machine_mode mode , rtx reg , rtx mem ) { rtx ( * fn ) ( rtx , rtx ) = NULL ; switch ( mode ) { case E_QImode : fn = gen_load_lockedqi ; break ; case E_HImode : fn = gen_load_lockedhi ; break ; case E_SImode : if ( GET_MODE ( mem ) == QImode ) fn = gen_load_lockedqi_si ; else if ( GET_MODE ( mem ) == HImode ) fn = gen_load_lockedhi_si ; else fn = gen_load_lockedsi ; break ; case E_DImode : fn = gen_load_lockeddi ; break ; case E_TImode : fn = gen_load_lockedti ; break ; default : gcc_unreachable ( ) ; } emit_insn ( fn ( reg , mem ) ) ; } </s>

A subroutine of the atomic operation splitters . Emit a load-locked instruction in MODE . For QI/HImode , possibly use a pattern than includes the zero_extend operation .


<s> void nvptx_cpu_cpp_builtins ( void ) { cpp_assert ( parse_in , "machine=nvptx" ) ; cpp_assert ( parse_in , "cpu=nvptx" ) ; cpp_define ( parse_in , "__nvptx__" ) ; if ( TARGET_SOFT_STACK ) cpp_define ( parse_in , "__nvptx_softstack__" ) ; if ( TARGET_UNIFORM_SIMT ) cpp_define ( parse_in , "__nvptx_unisimt__" ) ; const char * ptx_sm = NULL ; { \ if ( TARGET_SM ## XX ) \ ptx_sm = "__PTX_SM__=" # XX "0" ; \ } cpp_define ( parse_in , ptx_sm ) ; { unsigned major = ptx_version_to_number ( ( ptx_version ) ptx_version_option , true ) ; unsigned minor = ptx_version_to_number ( ( ptx_version ) ptx_version_option , false ) ; cpp_define_formatted ( parse_in , "__PTX_ISA_VERSION_MAJOR__=%u" , major ) ; cpp_define_formatted ( parse_in , "__PTX_ISA_VERSION_MINOR__=%u" , minor ) ; } } </s>

Function to tell the preprocessor about the defines for the target .


<s> void SystemZMCInstLower :: lower ( const MachineInstr * MI , MCInst & OutMI ) const { OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( const MachineOperand & MO : MI -> operands ( ) ) if ( ! MO . isReg ( ) || ! MO . isImplicit ( ) ) OutMI . addOperand ( lowerOperand ( MO ) ) ; } </s>


<s> static bool mem_locations_overlap ( rtx mem1 , rtx mem2 ) { rtx reg1 , reg2 ; HOST_WIDE_INT off1 , size1 , off2 , size2 ; if ( get_memref_parts ( mem1 , & reg1 , & off1 , & size1 ) && get_memref_parts ( mem2 , & reg2 , & off2 , & size2 ) ) return ( ( REGNO ( reg1 ) == REGNO ( reg2 ) ) && ( ( ( off1 <= off2 ) && ( off1 + size1 > off2 ) ) || ( ( off2 <= off1 ) && ( off2 + size2 > off1 ) ) ) ) ; return false ; } </s>

This function returns true if it can be determined that the two MEM locations overlap by at least 1 byte based on base reg/offset/size .


<s> bool Cpu0AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Cpu0FI = MF . getInfo < Cpu0MachineFunctionInfo > ( ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> int ARMAsmParser :: tryParseRegister ( ) { const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return - 1 ; std :: string lowerCase = Tok . getString ( ) . lower ( ) ; unsigned RegNum = MatchRegisterName ( lowerCase ) ; if ( ! RegNum ) { RegNum = StringSwitch < unsigned > ( lowerCase ) . Case ( "r13" , ARM :: SP ) . Case ( "r14" , ARM :: LR ) . Case ( "r15" , ARM :: PC ) . Case ( "ip" , ARM :: R12 ) . Default ( 0 ) ; } if ( ! RegNum ) return - 1 ; Parser . Lex ( ) ; return RegNum ; } </s>

tryParseRegister - parse one register if possible


<s> unsigned ARMBaseInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case ARM :: LDRrs : case ARM :: t2LDRs : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isReg ( ) && MI . getOperand ( 3 ) . isImm ( ) && MI . getOperand ( 2 ) . getReg ( ) == 0 && MI . getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: LDRi12 : case ARM :: t2LDRi12 : case ARM :: tLDRspi : case ARM :: VLDRD : case ARM :: VLDRS : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VLD1q64 : case ARM :: VLD1d8TPseudo : case ARM :: VLD1d16TPseudo : case ARM :: VLD1d32TPseudo : case ARM :: VLD1d64TPseudo : case ARM :: VLD1d8QPseudo : case ARM :: VLD1d16QPseudo : case ARM :: VLD1d32QPseudo : case ARM :: VLD1d64QPseudo : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VLDMQIA : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> static void mips_setup_incoming_varargs ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int * pretend_size ATTRIBUTE_UNUSED , int no_rtl ) { CUMULATIVE_ARGS local_cum ; int gp_saved , fp_saved ; local_cum = * cum ; FUNCTION_ARG_ADVANCE ( local_cum , mode , type , 1 ) ; gp_saved = MAX_ARGS_IN_REGISTERS - local_cum . num_gprs ; fp_saved = ( EABI_FLOAT_VARARGS_P ? MAX_ARGS_IN_REGISTERS - local_cum . num_fprs : 0 ) ; if ( ! no_rtl ) { if ( gp_saved > 0 ) { rtx ptr , mem ; ptr = plus_constant ( virtual_incoming_args_rtx , REG_PARM_STACK_SPACE ( cfun -> decl ) - gp_saved * UNITS_PER_WORD ) ; mem = gen_rtx_MEM ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . num_gprs + GP_ARG_FIRST , mem , gp_saved ) ; } if ( fp_saved > 0 ) { enum machine_mode mode ; int off , i ; off = - gp_saved * UNITS_PER_WORD ; off &= ~ ( UNITS_PER_FPVALUE - 1 ) ; off -= fp_saved * UNITS_PER_FPREG ; mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode ; for ( i = local_cum . num_fprs ; i < MAX_ARGS_IN_REGISTERS ; i += FP_INC ) { rtx ptr , mem ; ptr = plus_constant ( virtual_incoming_args_rtx , off ) ; mem = gen_rtx_MEM ( mode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; emit_move_insn ( mem , gen_rtx_REG ( mode , FP_ARG_FIRST + i ) ) ; off += UNITS_PER_HWFPVALUE ; } } } if ( REG_PARM_STACK_SPACE ( cfun -> decl ) == 0 ) cfun -> machine -> varargs_size = ( gp_saved * UNITS_PER_WORD + fp_saved * UNITS_PER_FPREG ) ; } </s>


<s> bool Mips16TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , MachineMemOperand :: Flags , bool * Fast ) const { return false ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> static ARMOperand * CreateReg ( unsigned RegNum , SMLoc S , SMLoc E ) { ARMOperand * Op = new ARMOperand ( k_Register ) ; Op -> Reg . RegNum = RegNum ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


"MSA requires a 64-bit FPU register file (FR=1 mode). "

This constructor initializes the data members to match that of the specified triple .


<s>
static
rtx
arm_expand_mve_builtin
(
int
fcode
,
tree
exp
,
rtx
target
)
{
if
(
fcode
>=
ARM_BUILTIN_MVE_BASE
&&
!
TARGET_HAVE_MVE
)
{
fatal_error
(
input_location
,
"You must enable MVE instructions"
" to use these intrinsics"
)
;
return
const0_rtx
;
}
arm_builtin_datum
*
d
=
&
mve_builtin_data
[
fcode
ARM_BUILTIN_MVE_PATTERN_START
]
;
return
arm_expand_builtin_1
(
fcode
,
exp
,
target
,
d
)
;
}
</s>

Expand an MVE builtin , i.e . those registered only if their respective target constraints are met . This check happens within arm_expand_builtin .

arm
"You must enable MVE instructions"
" to use these intrinsics"


<s> bool Z80FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc dl ; if ( MI != MBB . end ( ) ) dl = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; Z80MachineFunctionInfo * MFI = MF . getInfo < Z80MachineFunctionInfo > ( ) ; MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; i -- ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , dl , TII . get ( Z80 :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesAll ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void HexagonDAGToDAGISel :: Select ( SDNode * N ) { if ( N -> isMachineOpcode ( ) ) return N -> setNodeId ( - 1 ) ; switch ( N -> getOpcode ( ) ) { case ISD :: Constant : return SelectConstant ( N ) ; case ISD :: ConstantFP : return SelectConstantFP ( N ) ; case ISD :: FrameIndex : return SelectFrameIndex ( N ) ; case ISD :: BITCAST : return SelectBitcast ( N ) ; case ISD :: SHL : return SelectSHL ( N ) ; case ISD :: LOAD : return SelectLoad ( N ) ; case ISD :: STORE : return SelectStore ( N ) ; case ISD :: INTRINSIC_W_CHAIN : return SelectIntrinsicWChain ( N ) ; case ISD :: INTRINSIC_WO_CHAIN : return SelectIntrinsicWOChain ( N ) ; case HexagonISD :: VALIGN : return SelectVAlign ( N ) ; case HexagonISD :: VALIGNADDR : return SelectVAlignAddr ( N ) ; case HexagonISD :: TYPECAST : return SelectTypecast ( N ) ; case HexagonISD :: P2D : return SelectP2D ( N ) ; case HexagonISD :: D2P : return SelectD2P ( N ) ; case HexagonISD :: Q2V : return SelectQ2V ( N ) ; case HexagonISD :: V2Q : return SelectV2Q ( N ) ; } if ( HST -> useHVXOps ( ) ) { switch ( N -> getOpcode ( ) ) { case ISD :: VECTOR_SHUFFLE : return SelectHvxShuffle ( N ) ; case HexagonISD :: VROR : return SelectHvxRor ( N ) ; } } SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> static void arm32_output_mi_thunk ( FILE * file , tree , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { const bool long_call_p = arm_is_long_call_p ( function ) ; int this_regno = ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ? R1_REGNUM : R0_REGNUM ) ; rtx temp = gen_rtx_REG ( Pmode , IP_REGNUM ) ; rtx this_rtx = gen_rtx_REG ( Pmode , this_regno ) ; reload_completed = 1 ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; if ( delta != 0 ) arm_split_constant ( PLUS , Pmode , NULL_RTX , delta , this_rtx , this_rtx , false ) ; if ( vcall_offset != 0 ) { emit_move_insn ( temp , gen_rtx_MEM ( Pmode , this_rtx ) ) ; arm_split_constant ( PLUS , Pmode , NULL_RTX , vcall_offset , temp , temp , false ) ; emit_move_insn ( temp , gen_rtx_MEM ( Pmode , temp ) ) ; emit_insn ( gen_add3_insn ( this_rtx , this_rtx , temp ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = 1 ; } rtx funexp = XEXP ( DECL_RTL ( function ) , 0 ) ; if ( long_call_p ) { emit_move_insn ( temp , funexp ) ; funexp = temp ; } funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; rtx_insn * insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx , NULL_RTX ) ) ; SIBLING_CALL_P ( insn ) = 1 ; emit_barrier ( ) ; if ( long_call_p ) { split_all_insns_noflow ( ) ; arm_reorg ( ) ; } insn = get_insns ( ) ; shorten_branches ( insn ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; reload_completed = 0 ; } </s>


<s> void SystemZAsmPrinter :: emitEndOfAsmFile ( Module & M ) { emitEXRLTargetInstructions ( ) ; emitStackMaps ( SM ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> static void nvptx_record_fndecl ( tree decl ) { tree * slot = declared_fndecls_htab -> find_slot ( decl , INSERT ) ; if ( * slot == NULL ) { * slot = decl ; const char * name = get_fnname_from_decl ( decl ) ; write_fn_proto ( func_decls , false , name , decl ) ; } } </s>

DECL is an external FUNCTION_DECL , make sure its in the fndecl hash table and and write a ptx prototype . These are emitted at end of compilation .


<s>
bool
HexagonPacketizer
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
DisablePacketizer
||
skipFunction
(
*
MF
.
getFunction
(
)
)
)
return
false
;
HII
=
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getInstrInfo
(
)
;
HRI
=
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getRegisterInfo
(
)
;
auto
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
auto
*
AA
=
&
getAnalysis
<
AAResultsWrapperPass
>
(
)
.
getAAResults
(
)
;
auto
*
MBPI
=
&
getAnalysis
<
MachineBranchProbabilityInfo
>
(
)
;
if
(
EnableGenAllInsnClass
)
HII
->
genAllInsnTimingClasses
(
MF
)
;
HexagonPacketizerList
Packetizer
(
MF
,
MLI
,
AA
,
MBPI
)
;
assert
(
Packetizer
.
getResourceTracker
(
)
&&
"Empty DFA table!"
)
;
for
(
auto
&
MB
:
MF
)
{
auto
End
=
MB
.
end
(
)
;
auto
MI
=
MB
.
begin
(
)
;
while
(
MI
!=
End
)
{
auto
NextI
=
std
::
next
(
MI
)
;
if
(
MI
->
isKill
(
)
)
{
MB
.
erase
(
MI
)
;
End
=
MB
.
end
(
)
;
}
MI
=
NextI
;
}
}
for
(
auto
&
MB
:
MF
)
{
auto
Begin
=
MB
.
begin
(
)
,
End
=
MB
.
end
(
)
;
while
(
Begin
!=
End
)
{
MachineBasicBlock
::
iterator
RB
=
Begin
;
while
(
RB
!=
End
&&
HII
->
isSchedulingBoundary
(
*
RB
,
&
MB
,
MF
)
)
++
RB
;
MachineBasicBlock
::
iterator
RE
=
RB
;
while
(
RE
!=
End
&&
!
HII
->
isSchedulingBoundary
(
*
RE
,
&
MB
,
MF
)
)
++
RE
;
if
(
RE
!=
End
)
++
RE
;
if
(
RB
!=
End
)
Packetizer
.
PacketizeMIs
(
&
MB
,
RB
,
RE
)
;
Begin
=
RE
;
}
}
Packetizer
.
unpacketizeSoloInstrs
(
MF
)
;
return
true
;
}
</s>

Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
"Empty DFA table!"


<s> const uint16_t * OR1KRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const TargetFrameLowering * TFI = getFrameLowering ( * MF ) ; return TFI -> hasFP ( * MF ) ? CSR_FP_SaveList : CSR_SaveList ; } </s>


<s> static rtx_insn * arm_pic_static_addr ( rtx orig , rtx reg ) { rtx l1 , labelno , offset_rtx ; rtx_insn * insn ; gcc_assert ( flag_pic ) ; bool is_readonly = false ; bool info_known = false ; if ( TARGET_FDPIC && SYMBOL_REF_P ( orig ) && ! SYMBOL_REF_FUNCTION_P ( orig ) ) info_known = arm_is_segment_info_known ( orig , & is_readonly ) ; if ( TARGET_FDPIC && SYMBOL_REF_P ( orig ) && ! SYMBOL_REF_FUNCTION_P ( orig ) && ! info_known ) { rtx pic_reg = gen_rtx_REG ( Pmode , FDPIC_REGNUM ) ; insn = calculate_pic_address_constant ( reg , pic_reg , orig ) ; } else if ( TARGET_FDPIC && SYMBOL_REF_P ( orig ) && ( SYMBOL_REF_FUNCTION_P ( orig ) || ! is_readonly ) ) { rtx pic_reg = gen_rtx_REG ( Pmode , FDPIC_REGNUM ) ; rtx l1 = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , orig ) , UNSPEC_PIC_SYM ) ; emit_insn ( gen_movsi ( reg , l1 ) ) ; insn = emit_insn ( gen_addsi3 ( reg , reg , pic_reg ) ) ; } else { labelno = GEN_INT ( pic_labelno ++ ) ; l1 = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , labelno ) , UNSPEC_PIC_LABEL ) ; l1 = gen_rtx_CONST ( VOIDmode , l1 ) ; offset_rtx = plus_constant ( Pmode , l1 , TARGET_ARM ? 8 : 4 ) ; offset_rtx = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 2 , orig , offset_rtx ) , UNSPEC_SYMBOL_OFFSET ) ; offset_rtx = gen_rtx_CONST ( Pmode , offset_rtx ) ; insn = emit_insn ( gen_pic_load_addr_unified ( reg , offset_rtx , labelno ) ) ; } return insn ; } </s>

Generate code to load the address of a static var when flag_pic is set .


<s> MCObjectWriter * MipsAsmBackend :: createObjectWriter ( raw_ostream & OS ) const { return createMipsELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI ( OSType ) , IsLittle , Is64Bit ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> enum aarch64_symbol_type aarch64_classify_symbol ( rtx x , rtx offset ) { if ( GET_CODE ( x ) == LABEL_REF ) { switch ( aarch64_cmodel ) { case AARCH64_CMODEL_LARGE : return SYMBOL_FORCE_TO_MEM ; case AARCH64_CMODEL_TINY_PIC : case AARCH64_CMODEL_TINY : return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL_SPIC : case AARCH64_CMODEL_SMALL_PIC : case AARCH64_CMODEL_SMALL : return SYMBOL_SMALL_ABSOLUTE ; default : gcc_unreachable ( ) ; } } if ( GET_CODE ( x ) == SYMBOL_REF ) { if ( aarch64_cmodel == AARCH64_CMODEL_LARGE ) { if ( nopcrelative_literal_loads && CONSTANT_POOL_ADDRESS_P ( x ) ) return SYMBOL_SMALL_ABSOLUTE ; else return SYMBOL_FORCE_TO_MEM ; } if ( aarch64_tls_symbol_p ( x ) ) return aarch64_classify_tls_symbol ( x ) ; switch ( aarch64_cmodel ) { case AARCH64_CMODEL_TINY : if ( SYMBOL_REF_WEAK ( x ) || INTVAL ( offset ) < - 1048575 || INTVAL ( offset ) > 1048575 ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL : if ( SYMBOL_REF_WEAK ( x ) || ! IN_RANGE ( INTVAL ( offset ) , HOST_WIDE_INT_C ( - 4294967263 ) , HOST_WIDE_INT_C ( 4294967264 ) ) ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_SMALL_ABSOLUTE ; case AARCH64_CMODEL_TINY_PIC : if ( ! aarch64_symbol_binds_local_p ( x ) ) return SYMBOL_TINY_GOT ; return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL_SPIC : case AARCH64_CMODEL_SMALL_PIC : if ( ! aarch64_symbol_binds_local_p ( x ) ) return ( aarch64_cmodel == AARCH64_CMODEL_SMALL_SPIC ? SYMBOL_SMALL_GOT_28K : SYMBOL_SMALL_GOT_4G ) ; return SYMBOL_SMALL_ABSOLUTE ; default : gcc_unreachable ( ) ; } } return SYMBOL_FORCE_TO_MEM ; } </s>

Return the method that should be used to access SYMBOL_REF or LABEL_REF X .


<s> unsigned MipsSEInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( ( Opc == Mips :: SW ) || ( Opc == Mips :: SD ) || ( Opc == Mips :: SWC1 ) || ( Opc == Mips :: SDC1 ) || ( Opc == Mips :: SDC164 ) ) { if ( ( MI -> getOperand ( 1 ) . isFI ( ) ) && ( MI -> getOperand ( 2 ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( 2 ) ) ) ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> unsigned getOffsetOf ( MachineBasicBlock * MBB ) const { return BBInfo [ MBB -> getNumber ( ) ] . Offset ; } </s>

getOffsetOf - Return the current offset of the specified machine instruction from the start of the function .