<s> static cpp_hashnode * s390_categorize_keyword ( const cpp_token * tok ) { if ( tok -> type == CPP_NAME ) { cpp_hashnode * ident = tok -> val . node . node ; if ( ident == C_CPP_HASHNODE ( vector_keyword ) ) return C_CPP_HASHNODE ( __vector_keyword ) ; if ( ident == C_CPP_HASHNODE ( bool_keyword ) ) return C_CPP_HASHNODE ( __bool_keyword ) ; if ( ident == C_CPP_HASHNODE ( _Bool_keyword ) ) return C_CPP_HASHNODE ( __bool_keyword ) ; return ident ; } return 0 ; } </s>

Unify the different variants to the same nodes in order to keep the code working with it simple .


<s> static bool mips_rewrite_small_data_p ( rtx x ) { enum mips_symbol_type symbol_type ; return ( TARGET_EXPLICIT_RELOCS && mips_symbolic_constant_p ( x , & symbol_type ) && symbol_type == SYMBOL_SMALL_DATA ) ; } </s>

Return true if X is a small data address that can be rewritten as a LO_SUM .


<s> ChangeStatus manifest ( Attributor & A ) override { SmallVector < Attribute , 8 > AttrList ; LLVMContext & Ctx = getAssociatedFunction ( ) -> getContext ( ) ; for ( StringRef AttrName : Attributes ) AttrList . push_back ( Attribute :: get ( Ctx , AttrName ) ) ; return IRAttributeManifest :: manifestAttrs ( A , getIRPosition ( ) , AttrList , true ) ; } </s>

See AbstractAttribute : :manifest ( ... ) .


<s> bool NVPTXPrologEpilogPass :: runOnMachineFunction ( MachineFunction & MF ) { const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const TargetFrameLowering & TFI = * STI . getFrameLowering ( ) ; const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; bool Modified = false ; calculateFrameObjectOffsets ( MF ) ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) { for ( unsigned i = 0 , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { if ( ! MI . getOperand ( i ) . isFI ( ) ) continue ; TRI . eliminateFrameIndex ( MI , 0 , i , nullptr ) ; Modified = true ; } } } TFI . emitPrologue ( MF , MF . front ( ) ) ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( I -> isReturnBlock ( ) ) TFI . emitEpilogue ( MF , * I ) ; } return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> const char * pdp11_assemble_shift ( rtx * operands , machine_mode m , int code ) { int i , n ; rtx inops [ 2 ] ; rtx exops [ 2 ] [ 2 ] ; rtx lb [ 1 ] ; pdp11_action action [ 2 ] ; const bool small = CONST_INT_P ( operands [ 2 ] ) && pdp11_small_shift ( INTVAL ( operands [ 2 ] ) ) ; gcc_assert ( small || ! TARGET_40_PLUS ) ; if ( m == E_SImode ) { inops [ 0 ] = operands [ 0 ] ; pdp11_expand_operands ( inops , exops , 1 , 2 , action , either ) ; } if ( ! small ) { lb [ 0 ] = gen_label_rtx ( ) ; output_asm_label ( lb [ 0 ] ) ; fputs ( ":\n" , asm_out_file ) ; n = 1 ; } else n = INTVAL ( operands [ 2 ] ) ; if ( code == LSHIFTRT ) { output_asm_insn ( "clc" , NULL ) ; switch ( m ) { case E_QImode : output_asm_insn ( "rorb\t%0" , operands ) ; break ; case E_HImode : output_asm_insn ( "ror\t%0" , operands ) ; break ; case E_SImode : output_asm_insn ( "ror\t%0" , exops [ 0 ] ) ; output_asm_insn ( "ror\t%0" , exops [ 1 ] ) ; break ; default : gcc_unreachable ( ) ; } n -- ; } for ( i = 0 ; i < n ; i ++ ) { switch ( code ) { case LSHIFTRT : case ASHIFTRT : switch ( m ) { case E_QImode : output_asm_insn ( "asrb\t%0" , operands ) ; break ; case E_HImode : output_asm_insn ( "asr\t%0" , operands ) ; break ; case E_SImode : output_asm_insn ( "asr\t%0" , exops [ 0 ] ) ; output_asm_insn ( "ror\t%0" , exops [ 1 ] ) ; break ; default : gcc_unreachable ( ) ; } break ; case ASHIFT : switch ( m ) { case E_QImode : output_asm_insn ( "aslb\t%0" , operands ) ; break ; case E_HImode : output_asm_insn ( "asl\t%0" , operands ) ; break ; case E_SImode : output_asm_insn ( "asl\t%0" , exops [ 1 ] ) ; output_asm_insn ( "rol\t%0" , exops [ 0 ] ) ; break ; default : gcc_unreachable ( ) ; } break ; } } if ( ! small ) { output_asm_insn ( "dec\t%2" , operands ) ; output_asm_insn ( "bne\t%l0" , lb ) ; } return "" ; } </s>

Emit the instructions needed to produce a shift by a small constant amount ( unrolled ) , or a shift made from a loop for the base machine case .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
Register
:
OS
<<
"<register x"
;
OS
<<
getReg
(
)
<<
">"
;
break
;
case
Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


"don't know how to get the name for this callee"


<s> ARMConstantPoolSymbol * ARMConstantPoolSymbol :: Create ( LLVMContext & C , StringRef s , unsigned ID , unsigned char PCAdj ) { return new ARMConstantPoolSymbol ( C , s , ID , PCAdj , ARMCP :: no_modifier , false ) ; } </s>

Construct a unary instruction , given the opcode and an operand .


<s> static void note_np_check_stores ( rtx x , const_rtx pat ATTRIBUTE_UNUSED , void * data ATTRIBUTE_UNUSED ) { if ( REG_P ( x ) && ( REGNO ( x ) == REG_CC || ( int ) REGNO ( x ) == np_check_regno ) ) np_check_regno = - 1 ; } </s>

Subroutine of workaround_speculation , called through note_stores .


<s> static void th_mempair_restore_regs ( rtx operands [ 4 ] ) { rtx set1 = gen_rtx_SET ( operands [ 0 ] , operands [ 1 ] ) ; rtx set2 = gen_rtx_SET ( operands [ 2 ] , operands [ 3 ] ) ; rtx insn = emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set1 , set2 ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_RESTORE , operands [ 0 ] ) ; add_reg_note ( insn , REG_CFA_RESTORE , operands [ 2 ] ) ; } </s>

Similar like riscv_restore_reg , but restores two registers from memory and marks the instruction frame-related .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < DominatorTreeWrapperPass > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
void
TPCSchedStrategy
::
releaseTopNode
(
SUnit
*
SU
)
{
MachineInstr
*
MI
=
SU
->
getInstr
(
)
;
(
void
)
MI
;
if
(
SU
->
isScheduled
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"*** release Top - already scheduled: "
<<
*
MI
)
;
return
;
}
SU
->
TopReadyCycle
=
0
;
for
(
const
SDep
&
PI
:
SU
->
Preds
)
{
unsigned
PredReadyCycle
=
PI
.
getSUnit
(
)
->
TopReadyCycle
;
unsigned
MinLatency
=
PI
.
getLatency
(
)
;
Top
.
MaxMinLatency
=
std
::
max
(
MinLatency
,
Top
.
MaxMinLatency
)
;
if
(
SU
->
TopReadyCycle
<
PredReadyCycle
+
MinLatency
)
SU
->
TopReadyCycle
=
PredReadyCycle
+
MinLatency
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"*** released Top (ready = "
<<
SU
->
TopReadyCycle
<<
"): "
<<
*
MI
)
;
if
(
MI
->
getOpcode
(
)
==
TPC
::
MOVnodce
)
{
SU
->
isScheduleHigh
=
true
;
}
Top
.
releaseNode
(
SU
,
SU
->
TopReadyCycle
,
isPostRA
)
;
}
</s>

SU has had all predecessor dependencies resolved .

TPC
TPC
"*** release Top - already scheduled: "
0
"*** released Top (ready = "
"): "
TPC::MOVnodce


<s> enum reg_class m68k_preferred_reload_class ( rtx x , enum reg_class rclass ) { enum reg_class secondary_class ; secondary_class = m68k_secondary_reload_class ( rclass , GET_MODE ( x ) , x ) ; if ( secondary_class != NO_REGS && reg_class_subset_p ( secondary_class , rclass ) ) return secondary_class ; if ( GET_CODE ( x ) == CONST_INT && reg_class_subset_p ( DATA_REGS , rclass ) && IN_RANGE ( INTVAL ( x ) , - 0x80 , 0x7f ) ) return DATA_REGS ; if ( GET_CODE ( x ) == CONST_DOUBLE && GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) { if ( TARGET_HARD_FLOAT && reg_class_subset_p ( FP_REGS , rclass ) ) return FP_REGS ; return NO_REGS ; } return rclass ; } </s>


<s>
SDValue
VETargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
getReturnCC
(
CallConv
)
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
assert
(
!
VA
.
needsCustom
(
)
&&
"Unexpected custom lowering"
)
;
SDValue
OutVal
=
OutVals
[
i
]
;
switch
(
VA
.
getLocInfo
(
)
)
{
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
SExt
:
OutVal
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
DL
,
VA
.
getLocVT
(
)
,
OutVal
)
;
break
;
case
CCValAssign
::
ZExt
:
OutVal
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
DL
,
VA
.
getLocVT
(
)
,
OutVal
)
;
break
;
case
CCValAssign
::
AExt
:
OutVal
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
DL
,
VA
.
getLocVT
(
)
,
OutVal
)
;
break
;
case
CCValAssign
::
BCvt
:
{
assert
(
VA
.
getLocVT
(
)
==
MVT
::
i64
)
;
assert
(
VA
.
getValVT
(
)
==
MVT
::
f32
)
;
SDValue
Undef
=
SDValue
(
DAG
.
getMachineNode
(
TargetOpcode
::
IMPLICIT_DEF
,
DL
,
MVT
::
i64
)
,
0
)
;
SDValue
Sub_f32
=
DAG
.
getTargetConstant
(
VE
::
sub_f32
,
DL
,
MVT
::
i32
)
;
OutVal
=
SDValue
(
DAG
.
getMachineNode
(
TargetOpcode
::
INSERT_SUBREG
,
DL
,
MVT
::
i64
,
Undef
,
OutVal
,
Sub_f32
)
,
0
)
;
break
;
}
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
}
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
OutVal
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
VEISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void pa_output_addr_diff_vec ( rtx lab , rtx body ) { rtx base = XEXP ( XEXP ( body , 0 ) , 0 ) ; int idx , vlen = XVECLEN ( body , 1 ) ; targetm . asm_out . internal_label ( asm_out_file , "L" , CODE_LABEL_NUMBER ( lab ) ) ; if ( TARGET_GAS ) fputs ( "\t.begin_brtab\n" , asm_out_file ) ; for ( idx = 0 ; idx < vlen ; idx ++ ) { ASM_OUTPUT_ADDR_DIFF_ELT ( asm_out_file , body , CODE_LABEL_NUMBER ( XEXP ( XVECEXP ( body , 1 , idx ) , 0 ) ) , CODE_LABEL_NUMBER ( base ) ) ; } if ( TARGET_GAS ) fputs ( "\t.end_brtab\n" , asm_out_file ) ; } </s>


<s> void MipsSEFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; unsigned RA = ABI . IsN64 ( ) ? Mips :: RA_64 : Mips :: RA ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned BP = ABI . IsN64 ( ) ? Mips :: S7_64 : Mips :: S7 ; if ( hasFP ( MF ) ) { setAliasRegs ( MF , SavedRegs , RA ) ; setAliasRegs ( MF , SavedRegs , FP ) ; } if ( hasBP ( MF ) ) setAliasRegs ( MF , SavedRegs , BP ) ; if ( MipsFI -> callsEhReturn ( ) ) MipsFI -> createEhDataRegsFI ( ) ; if ( MipsFI -> isISR ( ) ) MipsFI -> createISRRegFI ( ) ; if ( ExpandPseudo ( MF ) . expand ( ) ) { const TargetRegisterClass & RC = STI . isGP64bit ( ) ? Mips :: GPR64RegClass : Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlignment ( RC ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } uint64_t MaxSPOffset = estimateStackSize ( MF ) ; if ( isIntN ( STI . hasMSA ( ) ? 10 : 16 , MaxSPOffset ) && ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ) return ; const TargetRegisterClass & RC = ABI . ArePtrs64bit ( ) ? Mips :: GPR64RegClass : Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlignment ( RC ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> int AArch64AsmParser :: tryParseRegister ( ) { MCAsmParser & Parser = getParser ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return - 1 ; std :: string lowerCase = Tok . getString ( ) . lower ( ) ; if ( isSVEDataVectorRegister ( lowerCase ) ) return - 1 ; unsigned RegNum = matchRegisterNameAlias ( lowerCase , RegKind :: Scalar ) ; if ( RegNum == 0 ) RegNum = StringSwitch < unsigned > ( lowerCase ) . Case ( "fp" , AArch64 :: FP ) . Case ( "lr" , AArch64 :: LR ) . Case ( "x31" , AArch64 :: XZR ) . Case ( "w31" , AArch64 :: WZR ) . Default ( 0 ) ; if ( RegNum == 0 ) return - 1 ; Parser . Lex ( ) ; return RegNum ; } </s>

tryParseRegister - parse one register if possible


<s> static rtx mmix_function_arg ( cumulative_args_t argsp , machine_mode mode , const_tree type , bool named ) { return mmix_function_arg_1 ( argsp , mode , type , named , false ) ; } </s>

Return an rtx for a function argument to go in a register , and 0 for one that must go on stack .


<s> void addDomain ( unsigned domain ) { AvailableDomains |= 1u << domain ; } </s>


<s> bool MipsLongBranch :: runOnMachineFunction ( MachineFunction & F ) { const MipsSubtarget & STI = static_cast < const MipsSubtarget & > ( F . getSubtarget ( ) ) ; const MipsInstrInfo * TII = static_cast < const MipsInstrInfo * > ( STI . getInstrInfo ( ) ) ; const TargetMachine & TM = F . getTarget ( ) ; IsPIC = TM . isPositionIndependent ( ) ; ABI = static_cast < const MipsTargetMachine & > ( TM ) . getABI ( ) ; LongBranchSeqSize = ! IsPIC ? 2 : ( ABI . IsN64 ( ) ? 10 : ( ! STI . isTargetNaCl ( ) ? 9 : 10 ) ) ; if ( STI . inMips16Mode ( ) || ! STI . enableLongBranchPass ( ) ) return false ; if ( IsPIC && static_cast < const MipsTargetMachine & > ( TM ) . getABI ( ) . IsO32 ( ) && F . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; int ShVal = STI . inMicroMipsMode ( ) ? 2 : 4 ; int64_t Offset = computeOffset ( I -> Br ) / ShVal ; if ( STI . isTargetNaCl ( ) ) { Offset *= 2 ; } if ( ! ForceLongBranch && isInt < 16 > ( Offset ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * 4 ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( IsPIC ) { uint64_t Address = 0 ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ; } for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) if ( I -> HasLongBranch ) expandToLongBranch ( * I ) ; MF -> RenumberBlocks ( ) ; return true ; } </s>


<s> TargetPassConfig * AArch64TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new AArch64PassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> void GCNPassConfig :: addPreLegalizeMachineIR ( ) { bool IsOptNone = getOptLevel ( ) == CodeGenOpt :: None ; addPass ( createAMDGPUPreLegalizeCombiner ( IsOptNone ) ) ; addPass ( new Localizer ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before legalization .


<s> MachineInstrBuilder buildLoad ( const DstOp & Res , const CCValAssign & VA ) { MachineMemOperand * MMO ; Register Addr = getStackAddress ( VA , MMO ) ; return MIRBuilder . buildLoad ( Res , Addr , * MMO ) ; } </s>

Build and insert a G_LOAD instruction , while constructing the MachineMemOperand .


<s>
bool
NVPTXAsmPrinter
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
{
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
MCOp
=
MCOperand
::
CreateReg
(
encodeVirtualRegister
(
MO
.
getReg
(
)
)
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
CreateImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
CreateExpr
(
MCSymbolRefExpr
::
Create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
OutContext
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
GetSymbolRef
(
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
GetSymbolRef
(
getSymbol
(
MO
.
getGlobal
(
)
)
)
;
break
;
case
MachineOperand
::
MO_FPImmediate
:
{
const
ConstantFP
*
Cnt
=
MO
.
getFPImm
(
)
;
APFloat
Val
=
Cnt
->
getValueAPF
(
)
;
switch
(
Cnt
->
getType
(
)
->
getTypeID
(
)
)
{
default
:
report_fatal_error
(
"Unsupported FP type"
)
;
break
;
case
Type
::
FloatTyID
:
MCOp
=
MCOperand
::
CreateExpr
(
NVPTXFloatMCExpr
::
CreateConstantFPSingle
(
Val
,
OutContext
)
)
;
break
;
case
Type
::
DoubleTyID
:
MCOp
=
MCOperand
::
CreateExpr
(
NVPTXFloatMCExpr
::
CreateConstantFPDouble
(
Val
,
OutContext
)
)
;
break
;
}
break
;
}
}
return
true
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .

NVPTX
NVPTX
"unknown operand type"
"Unsupported FP type"
NVPTX
NVPTX


<s> bool aarch64_harden_sls_blr_p ( void ) { return aarch64_sls_hardening & SLS_BLR ; } </s>

Return whether we should mitigatate Straight Line Speculation for the BLR instruction .


<s> size_t count ( const StackVreg & Elem ) const { return llvm :: count ( Data , Elem ) ; } </s>

Return 1 if the specified key is in the map , 0 otherwise .


<s>
void
X86DAGToDAGISel
::
PreprocessISelDAG
(
)
{
OptForSize
=
MF
->
getFunction
(
)
->
optForSize
(
)
;
OptForMinSize
=
MF
->
getFunction
(
)
->
optForMinSize
(
)
;
assert
(
(
!
OptForMinSize
||
OptForSize
)
&&
"OptForMinSize implies OptForSize"
)
;
for
(
SelectionDAG
::
allnodes_iterator
I
=
CurDAG
->
allnodes_begin
(
)
,
E
=
CurDAG
->
allnodes_end
(
)
;
I
!=
E
;
)
{
SDNode
*
N
=
&
*
I
++
;
if
(
OptLevel
!=
CodeGenOpt
::
&&
(
(
N
->
getOpcode
(
)
==
X86ISD
::
CALL
&&
!
Subtarget
->
slowTwoMemOps
(
)
)
||
(
N
->
getOpcode
(
)
==
X86ISD
::
TC_RETURN
&&
(
Subtarget
->
is64Bit
(
)
||
!
getTargetMachine
(
)
.
isPositionIndependent
(
)
)
)
)
)
{
bool
HasCallSeq
=
N
->
getOpcode
(
)
==
X86ISD
::
CALL
;
SDValue
Chain
=
N
->
getOperand
(
0
)
;
SDValue
Load
=
N
->
getOperand
(
1
)
;
if
(
!
isCalleeLoad
(
Load
,
Chain
,
HasCallSeq
)
)
continue
;
moveBelowOrigChain
(
CurDAG
,
Load
,
SDValue
(
N
,
0
)
,
Chain
)
;
++
NumLoadMoved
;
continue
;
}
if
(
N
->
getOpcode
(
)
!=
ISD
::
FP_ROUND
&&
N
->
getOpcode
(
)
!=
ISD
::
FP_EXTEND
)
continue
;
MVT
SrcVT
=
N
->
getOperand
(
0
)
.
getSimpleValueType
(
)
;
MVT
DstVT
=
N
->
getSimpleValueType
(
0
)
;
if
(
SrcVT
.
isVector
(
)
||
DstVT
.
isVector
(
)
)
continue
;
const
X86TargetLowering
*
X86Lowering
=
static_cast
<
const
X86TargetLowering
*
>
(
TLI
)
;
bool
SrcIsSSE
=
X86Lowering
->
isScalarFPTypeInSSEReg
(
SrcVT
)
;
bool
DstIsSSE
=
X86Lowering
->
isScalarFPTypeInSSEReg
(
DstVT
)
;
if
(
SrcIsSSE
&&
DstIsSSE
)
continue
;
if
(
!
SrcIsSSE
&&
!
DstIsSSE
)
{
if
(
N
->
getOpcode
(
)
==
ISD
::
FP_EXTEND
)
continue
;
if
(
N
->
getConstantOperandVal
(
1
)
)
continue
;
}
MVT
MemVT
;
if
(
N
->
getOpcode
(
)
==
ISD
::
FP_ROUND
)
MemVT
=
DstVT
;
else
MemVT
=
SrcIsSSE
SrcVT
:
DstVT
;
SDValue
MemTmp
=
CurDAG
->
CreateStackTemporary
(
MemVT
)
;
SDLoc
dl
(
N
)
;
SDValue
Store
=
CurDAG
->
getTruncStore
(
CurDAG
->
getEntryNode
(
)
,
dl
,
N
->
getOperand
(
0
)
,
MemTmp
,
MachinePointerInfo
(
)
,
MemVT
)
;
SDValue
Result
=
CurDAG
->
getExtLoad
(
ISD
::
EXTLOAD
,
dl
,
DstVT
,
Store
,
MemTmp
,
MachinePointerInfo
(
)
,
MemVT
)
;
I
;
CurDAG
->
ReplaceAllUsesOfValueWith
(
SDValue
(
N
,
0
)
,
Result
)
;
++
I
;
CurDAG
->
DeleteNode
(
N
)
;
}
}
</s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> bool AMDGPUAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( ! AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , O ) ) return false ; if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { case 'r' : break ; default : return true ; } } const MachineOperand & MO = MI -> getOperand ( OpNo ) ; if ( MO . isReg ( ) ) { AMDGPUInstPrinter :: printRegOperand ( MO . getReg ( ) , O , * MF -> getSubtarget ( ) . getRegisterInfo ( ) ) ; return false ; } else if ( MO . isImm ( ) ) { int64_t Val = MO . getImm ( ) ; if ( AMDGPU :: isInlinableIntLiteral ( Val ) ) { O << Val ; } else if ( isUInt < 16 > ( Val ) ) { O << format ( "0x%" PRIx16 , static_cast < uint16_t > ( Val ) ) ; } else if ( isUInt < 32 > ( Val ) ) { O << format ( "0x%" PRIx32 , static_cast < uint32_t > ( Val ) ) ; } else { O << format ( "0x%" PRIx64 , static_cast < uint64_t > ( Val ) ) ; } return false ; } return true ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> const RegisterBankInfo * X86Subtarget :: getRegBankInfo ( ) const { return RegBankInfo . get ( ) ; } </s>

If the information for the register banks is available , return it .


<s>
static
bool
isReg
(
const
MCInst
&
MI
,
unsigned
OpNo
)
{
assert
(
MI
.
getOperand
(
OpNo
)
.
isReg
(
)
&&
"Register operand expected."
)
;
return
MI
.
getOperand
(
OpNo
)
.
getReg
(
)
==
R
;
}
</s>


Implement TARGET_MODES_TIEABLE_P . Tie QI/HI/SI modes together .


<s> static void mips_setup_incoming_varargs ( cumulative_args_t cum , const function_arg_info & arg , int * pretend_size ATTRIBUTE_UNUSED , int no_rtl ) { CUMULATIVE_ARGS local_cum ; int gp_saved , fp_saved ; local_cum = * get_cumulative_args ( cum ) ; mips_function_arg_advance ( pack_cumulative_args ( & local_cum ) , arg ) ; gp_saved = MAX_ARGS_IN_REGISTERS - local_cum . num_gprs ; fp_saved = ( EABI_FLOAT_VARARGS_P ? MAX_ARGS_IN_REGISTERS - local_cum . num_fprs : 0 ) ; if ( ! no_rtl ) { if ( gp_saved > 0 ) { rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , REG_PARM_STACK_SPACE ( cfun -> decl ) - gp_saved * UNITS_PER_WORD ) ; mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . num_gprs + GP_ARG_FIRST , mem , gp_saved ) ; } if ( fp_saved > 0 ) { machine_mode mode ; int off , i ; off = ROUND_DOWN ( - gp_saved * UNITS_PER_WORD , UNITS_PER_FPVALUE ) ; off -= fp_saved * UNITS_PER_FPREG ; mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode ; for ( i = local_cum . num_fprs ; i < MAX_ARGS_IN_REGISTERS ; i += MAX_FPRS_PER_FMT ) { rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , off ) ; mem = gen_frame_mem ( mode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; mips_emit_move ( mem , gen_rtx_REG ( mode , FP_ARG_FIRST + i ) ) ; off += UNITS_PER_HWFPVALUE ; } } } if ( REG_PARM_STACK_SPACE ( cfun -> decl ) == 0 ) cfun -> machine -> varargs_size = ( gp_saved * UNITS_PER_WORD + fp_saved * UNITS_PER_FPREG ) ; } </s>


"Slot for FPW register must be last in order to be found!"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> bool LEGInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { switch ( MI -> getOpcode ( ) ) { default : return false ; case LEG :: MOVi32 : { DebugLoc DL = MI -> getDebugLoc ( ) ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; const unsigned DstReg = MI -> getOperand ( 0 ) . getReg ( ) ; const bool DstIsDead = MI -> getOperand ( 0 ) . isDead ( ) ; const MachineOperand & MO = MI -> getOperand ( 1 ) ; auto LO16 = BuildMI ( MBB , MI , DL , get ( LEG :: MOVLOi16 ) , DstReg ) ; auto HI16 = BuildMI ( MBB , MI , DL , get ( LEG :: MOVHIi16 ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; if ( MO . isImm ( ) ) { const unsigned Imm = MO . getImm ( ) ; const unsigned Lo16 = Imm & 0xffff ; const unsigned Hi16 = ( Imm >> 16 ) & 0xffff ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; } else { const GlobalValue * GV = MO . getGlobal ( ) ; const unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | LEGII :: MO_LO16 ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | LEGII :: MO_HI16 ) ; } MBB . erase ( MI ) ; return true ; } } } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> void XCoreTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; BSSSection = Ctx . getELFSection ( ".dp.bss" , ELF :: SHT_NOBITS , ELF :: SHF_ALLOC | ELF :: SHF_WRITE | ELF :: XCORE_SHF_DP_SECTION ) ; BSSSectionLarge = Ctx . getELFSection ( ".dp.bss.large" , ELF :: SHT_NOBITS , ELF :: SHF_ALLOC | ELF :: SHF_WRITE | ELF :: XCORE_SHF_DP_SECTION ) ; DataSection = Ctx . getELFSection ( ".dp.data" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_WRITE | ELF :: XCORE_SHF_DP_SECTION ) ; DataSectionLarge = Ctx . getELFSection ( ".dp.data.large" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_WRITE | ELF :: XCORE_SHF_DP_SECTION ) ; DataRelROSection = Ctx . getELFSection ( ".dp.rodata" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_WRITE | ELF :: XCORE_SHF_DP_SECTION ) ; DataRelROSectionLarge = Ctx . getELFSection ( ".dp.rodata.large" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_WRITE | ELF :: XCORE_SHF_DP_SECTION ) ; ReadOnlySection = Ctx . getELFSection ( ".cp.rodata" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: XCORE_SHF_CP_SECTION ) ; ReadOnlySectionLarge = Ctx . getELFSection ( ".cp.rodata.large" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: XCORE_SHF_CP_SECTION ) ; MergeableConst4Section = Ctx . getELFSection ( ".cp.rodata.cst4" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_MERGE | ELF :: XCORE_SHF_CP_SECTION , 4 , "" ) ; MergeableConst8Section = Ctx . getELFSection ( ".cp.rodata.cst8" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_MERGE | ELF :: XCORE_SHF_CP_SECTION , 8 , "" ) ; MergeableConst16Section = Ctx . getELFSection ( ".cp.rodata.cst16" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_MERGE | ELF :: XCORE_SHF_CP_SECTION , 16 , "" ) ; CStringSection = Ctx . getELFSection ( ".cp.rodata.string" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_MERGE | ELF :: SHF_STRINGS | ELF :: XCORE_SHF_CP_SECTION ) ; } </s>

This method must be called before any actual lowering is done .


<s> rtx ix86_build_const_vector ( machine_mode mode , bool vect , rtx value ) { int i , n_elt ; rtvec v ; machine_mode scalar_mode ; switch ( mode ) { case E_V64QImode : case E_V32QImode : case E_V16QImode : case E_V32HImode : case E_V16HImode : case E_V8HImode : case E_V16SImode : case E_V8SImode : case E_V4SImode : case E_V8DImode : case E_V4DImode : case E_V2DImode : gcc_assert ( vect ) ; case E_V16SFmode : case E_V8SFmode : case E_V4SFmode : case E_V2SFmode : case E_V8DFmode : case E_V4DFmode : case E_V2DFmode : n_elt = GET_MODE_NUNITS ( mode ) ; v = rtvec_alloc ( n_elt ) ; scalar_mode = GET_MODE_INNER ( mode ) ; RTVEC_ELT ( v , 0 ) = value ; for ( i = 1 ; i < n_elt ; ++ i ) RTVEC_ELT ( v , i ) = vect ? value : CONST0_RTX ( scalar_mode ) ; return gen_rtx_CONST_VECTOR ( mode , v ) ; default : gcc_unreachable ( ) ; } } </s>

A subroutine of ix86_build_signbit_mask . If VECT is true , then replicate the value for all elements of the vector register .


<s> static bool mem_ok_for_ldrd_strd ( rtx mem , rtx * base , rtx * offset , HOST_WIDE_INT * align ) { rtx addr ; gcc_assert ( base != NULL && offset != NULL ) ; if ( side_effects_p ( mem ) ) return false ; if ( GET_CODE ( mem ) == SUBREG ) return false ; gcc_assert ( MEM_P ( mem ) ) ; * offset = const0_rtx ; * align = MEM_ALIGN ( mem ) ; addr = XEXP ( mem , 0 ) ; if ( ! arm_legitimate_address_p ( DImode , addr , reload_in_progress || reload_completed ) ) return false ; if ( REG_P ( addr ) ) { * base = addr ; return true ; } else if ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == MINUS ) { * base = XEXP ( addr , 0 ) ; * offset = XEXP ( addr , 1 ) ; return ( REG_P ( * base ) && CONST_INT_P ( * offset ) ) ; } return false ; } </s>

Helper for gen_operands_ldrd_strd . Returns true iff the memory operand MEM 's address contains an immediate offset from the base register and has no side effects , in which case it sets BASE and OFFSET accordingly .


<s> static int avr_interrupt_function_p ( tree func ) { return avr_lookup_function_attribute1 ( func , "interrupt" ) ; } </s>

Return nonzero if FUNC is an interrupt function as specified by the `` interrupt '' attribute .


<s> static enum flt_eval_method ix86_excess_precision ( enum excess_precision_type type ) { switch ( type ) { case EXCESS_PRECISION_TYPE_FAST : return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ; case EXCESS_PRECISION_TYPE_STANDARD : case EXCESS_PRECISION_TYPE_IMPLICIT : if ( ! TARGET_80387 ) return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ; else if ( ! TARGET_MIX_SSE_I387 ) { if ( ! ( TARGET_SSE && TARGET_SSE_MATH ) ) return FLT_EVAL_METHOD_PROMOTE_TO_LONG_DOUBLE ; else if ( TARGET_SSE2 ) return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ; } return ( type == EXCESS_PRECISION_TYPE_STANDARD ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT : FLT_EVAL_METHOD_UNPREDICTABLE ) ; default : gcc_unreachable ( ) ; } return FLT_EVAL_METHOD_UNPREDICTABLE ; } </s>

Set the value of FLT_EVAL_METHOD in float.h . When using only the FPU , assume that the fpcw is set to extended precision ; when using only SSE , rounding is correct ; when using both SSE and the FPU , the rounding precision is indeterminate , since either may be chosen apparently at random .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"ARM Assembly / Object Emitter"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool AArch64InstrInfo :: isStridedAccess ( const MachineInstr & MI ) { return llvm :: any_of ( MI . memoperands ( ) , [ ] ( MachineMemOperand * MMO ) { return MMO -> getFlags ( ) & MOStridedAccess ; } ) ; } </s>

Return true if the given load or store is a strided memory access .


<s> static void process_args ( int * p_argc , char * argv [ ] ) { int i ; for ( i = 1 ; i < * p_argc ; i ++ ) { if ( strlen ( argv [ i ] ) < 2 ) continue ; if ( strncmp ( argv [ i ] , "-I" , 2 ) == 0 ) { char * ptr ; int new_len , search_dirs_len ; ptr = to_host_dir_spec ( & argv [ i ] [ 2 ] ) ; new_len = strlen ( ptr ) ; search_dirs_len = strlen ( search_dirs ) ; search_dirs = xrealloc ( search_dirs , search_dirs_len + new_len + 2 ) ; if ( search_dirs_len > 0 ) strcat ( search_dirs , PATH_SEPARATOR_STR ) ; strcat ( search_dirs , ptr ) ; } else if ( strncmp ( argv [ i ] , "-D" , 2 ) == 0 ) { char * ptr ; int new_len , defines_len ; ptr = & argv [ i ] [ 2 ] ; new_len = strlen ( ptr ) ; defines_len = strlen ( defines ) ; defines = xrealloc ( defines , defines_len + new_len + 4 ) ; if ( defines_len > 0 ) strcat ( defines , "," ) ; strcat ( defines , "\"" ) ; strcat ( defines , ptr ) ; strcat ( defines , "\"" ) ; } else if ( strcmp ( argv [ i ] , "-v" ) == 0 ) verbose = 1 ; else if ( strcmp ( argv [ i ] , "-g0" ) == 0 ) addarg ( "/nodebug" ) ; else if ( strcmp ( argv [ i ] , "-O0" ) == 0 ) addarg ( "/noopt" ) ; else if ( strncmp ( argv [ i ] , "-g" , 2 ) == 0 ) addarg ( "/debug" ) ; else if ( strcmp ( argv [ i ] , "-E" ) == 0 ) addarg ( "/preprocess" ) ; else if ( strcmp ( argv [ i ] , "-save-temps" ) == 0 ) save_temps = 1 ; } } </s>

Preprocess the number of args ARGC in ARGV . Look for special flags , etc . that must be handled for the VMS linker .


<s> static void mips_autovectorize_vector_sizes ( vector_sizes * sizes ) { if ( ISA_HAS_MSA ) sizes -> safe_push ( 16 ) ; } </s>


<s> bool tilegx_can_use_return_insn_p ( void ) { return ( reload_completed && cfun -> static_chain_decl == 0 && compute_total_frame_size ( ) == 0 && tilegx_current_function_is_leaf ( ) && ! crtl -> profile && ! df_regs_ever_live_p ( TILEGX_LINK_REGNUM ) ) ; } </s>

Return nonzero if this function is known to have a null epilogue . This allows the optimizer to omit jumps to jumps if no stack was created .


<s> static int riscv_immediate_operand_p ( int code , HOST_WIDE_INT x ) { switch ( code ) { case ASHIFT : case ASHIFTRT : case LSHIFTRT : return true ; case AND : case IOR : case XOR : case PLUS : case LT : case LTU : return SMALL_OPERAND ( x ) ; case LE : return SMALL_OPERAND ( x + 1 ) ; case LEU : return SMALL_OPERAND ( x + 1 ) && x + 1 != 0 ; case GE : case GEU : return x == 1 ; default : return x == 0 ; } } </s>

Return true if there is an instruction that implements CODE and accepts X as an immediate operand .


<s> DecodeStatus SystemZDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , const MemoryObject & Region , uint64_t Address , raw_ostream & os , raw_ostream & cs ) const { uint8_t Bytes [ 6 ] ; Size = 0 ; if ( Region . readBytes ( Address , 2 , Bytes ) == - 1 ) return MCDisassembler :: Fail ; const uint8_t * Table ; if ( Bytes [ 0 ] < 0x40 ) { Size = 2 ; Table = DecoderTable16 ; } else if ( Bytes [ 0 ] < 0xc0 ) { Size = 4 ; Table = DecoderTable32 ; } else { Size = 6 ; Table = DecoderTable48 ; } if ( Size > 2 && Region . readBytes ( Address + 2 , Size - 2 , Bytes + 2 ) == - 1 ) return MCDisassembler :: Fail ; uint64_t Inst = 0 ; for ( uint64_t I = 0 ; I < Size ; ++ I ) Inst = ( Inst << 8 ) | Bytes [ I ] ; return decodeInstruction ( Table , MI , Inst , Address , this , STI ) ; } </s>

Returns the disassembly of a single instruction .


"Alloca should always return a pointer."

Emit an alloca address in a register using target-specific logic .


<s> machine_mode rs6000_secondary_memory_needed_mode ( machine_mode mode ) { if ( lra_in_progress && mode == SDmode ) return DDmode ; return mode ; } </s>

Return the mode to be used for memory when a secondary memory location is needed . For SDmode values we need to use DDmode , in all other cases we can use the same mode .


<s> static void riscv_output_mi_thunk ( FILE * file , tree thunk_fndecl ATTRIBUTE_UNUSED , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { const char * fnname = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( thunk_fndecl ) ) ; rtx this_rtx , temp1 , temp2 , fnaddr ; rtx_insn * insn ; reload_completed = 1 ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; fnaddr = gen_rtx_MEM ( FUNCTION_MODE , XEXP ( DECL_RTL ( function ) , 0 ) ) ; temp1 = gen_rtx_REG ( Pmode , RISCV_PROLOGUE_TEMP_REGNUM ) ; temp2 = gen_rtx_REG ( Pmode , STATIC_CHAIN_REGNUM ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , GP_ARG_FIRST + 1 ) ; else this_rtx = gen_rtx_REG ( Pmode , GP_ARG_FIRST ) ; if ( delta != 0 ) { rtx offset = GEN_INT ( delta ) ; if ( ! SMALL_OPERAND ( delta ) ) { riscv_emit_move ( temp1 , offset ) ; offset = temp1 ; } emit_insn ( gen_add3_insn ( this_rtx , this_rtx , offset ) ) ; } if ( vcall_offset != 0 ) { rtx addr ; riscv_emit_move ( temp1 , gen_rtx_MEM ( Pmode , this_rtx ) ) ; addr = riscv_add_offset ( temp2 , temp1 , vcall_offset ) ; riscv_emit_move ( temp1 , gen_rtx_MEM ( Pmode , addr ) ) ; emit_insn ( gen_add3_insn ( this_rtx , this_rtx , temp1 ) ) ; } insn = emit_call_insn ( gen_sibcall ( fnaddr , const0_rtx , NULL , const0_rtx ) ) ; SIBLING_CALL_P ( insn ) = 1 ; insn = get_insns ( ) ; split_all_insns_noflow ( ) ; shorten_branches ( insn ) ; assemble_start_function ( thunk_fndecl , fnname ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; assemble_end_function ( thunk_fndecl , fnname ) ; reload_completed = 0 ; } </s>

Implement TARGET_ASM_OUTPUT_MI_THUNK . Generate rtl rather than asm text in order to avoid duplicating too much logic from elsewhere .


<s> void WebAssemblyExceptionInfo :: print ( raw_ostream & OS , const Module * ) const { for ( auto * WE : TopLevelExceptions ) WE -> print ( OS ) ; } </s>

print - Print a debug representation of the operand to the given stream .


<s> const TargetRegisterClass * ThumbRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { if ( ! MF . getSubtarget < ARMSubtarget > ( ) . isThumb1Only ( ) ) return ARMBaseRegisterInfo :: getPointerRegClass ( MF , Kind ) ; return & ARM :: tGPRRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> bool AArch64InstrInfo :: isCopyInstrImpl ( const MachineInstr & MI , const MachineOperand * & Source , const MachineOperand * & Destination ) const { if ( MI . getOpcode ( ) == AArch64 :: ORRWrs && MI . getOperand ( 1 ) . getReg ( ) == AArch64 :: WZR && MI . getOperand ( 3 ) . getImm ( ) == 0x0 ) { Destination = & MI . getOperand ( 0 ) ; Source = & MI . getOperand ( 2 ) ; return true ; } if ( MI . getOpcode ( ) == AArch64 :: ORRXrs && MI . getOperand ( 1 ) . getReg ( ) == AArch64 :: XZR && MI . getOperand ( 3 ) . getImm ( ) == 0x0 ) { Destination = & MI . getOperand ( 0 ) ; Source = & MI . getOperand ( 2 ) ; return true ; } return false ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


<s> void h8300_swap_out_of_er6 ( rtx addr ) { rtx insn ; if ( REGNO ( addr ) != SP_REG ) emit_move_insn ( addr , hard_frame_pointer_rtx ) ; insn = pop ( HARD_FRAME_POINTER_REGNUM ) ; if ( frame_pointer_needed ) add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , hard_frame_pointer_rtx , 2 * UNITS_PER_WORD ) ) ; else add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - 4 ) ) ) ; } </s>

Move the current value of er6 into ADDR and pop its old value from the stack .


"cannot call %<__builtin_custom_%s%> without specifying "

Helper function for expanding FPU builtins .


<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < 512 > Key ; Key . reserve ( CPU . size ( ) + FS . size ( ) ) ; Key += CPU ; Key += FS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) Key += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; FS = Key . substr ( CPU . size ( ) ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < X86Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
static
bool
write_as_kernel
(
tree
attrs
)
{
return
(
lookup_attribute
(
"kernel"
,
attrs
)
!=
NULL_TREE
||
lookup_attribute
(
"omp target entrypoint"
,
attrs
)
!=
NULL_TREE
)
;
}
</s>

Look for attributes in ATTRS that would indicate we must write a function as a .entry kernel rather than a .func . Return true if one is found .


<s> Optional < ParamLoadedValue > AArch64InstrInfo :: describeLoadedValue ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { case AArch64 :: MOVZWi : case AArch64 :: MOVZXi : if ( ! MI . getOperand ( 1 ) . isImm ( ) ) return None ; int64_t Immediate = MI . getOperand ( 1 ) . getImm ( ) ; int Shift = MI . getOperand ( 2 ) . getImm ( ) ; return ParamLoadedValue ( MachineOperand :: CreateImm ( Immediate << Shift ) , nullptr ) ; } return TargetInstrInfo :: describeLoadedValue ( MI ) ; } </s>

Produce the expression describing the MI loading a value into the physical register Reg .


Return an array that contains the bitmask target flag values and their names .


<s>
void
aarch64_parse_one_override_token
(
const
char
*
token
,
size_t
length
,
struct
tune_params
*
tune
)
{
const
struct
aarch64_tuning_override_function
*
fn
=
aarch64_tuning_override_functions
;
const
char
*
option_part
=
strchr
(
token
,
'='
)
;
if
(
!
option_part
)
{
error
(
"tuning string missing in option (%s)"
,
token
)
;
return
;
}
length
=
option_part
token
;
option_part
++
;
for
(
;
fn
->
name
!=
;
fn
++
)
{
if
(
!
strncmp
(
fn
->
name
,
token
,
length
)
)
{
fn
->
parse_override
(
option_part
,
tune
)
;
return
;
}
}
error
(
"unknown tuning option (%s)"
,
token
)
;
return
;
}
</s>

Parse TOKEN , which has length LENGTH to see if it is a tuning option we understand . If it is , extract the option string and handoff to the appropriate function .

aarch64
"tuning string missing in option (%s)"
"unknown tuning option (%s)"


<s> void ARMPassConfig :: addIRPasses ( ) { if ( getARMSubtarget ( ) . isTargetNaCl ( ) ) addPass ( createInsertDivideCheckPass ( ) ) ; if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( TM ) ) ; const ARMSubtarget * Subtarget = & getARMSubtarget ( ) ; if ( Subtarget -> hasAnyDataBarrier ( ) && ! Subtarget -> isThumb1Only ( ) ) if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> unsigned HexagonGenInsert :: distance ( const MachineBasicBlock * FromB , const MachineBasicBlock * ToB , const UnsignedMap & RPO , PairMapType & M ) const { assert ( FromB != ToB ) ; unsigned FromN = FromB -> getNumber ( ) , ToN = ToB -> getNumber ( ) ; PairMapType :: iterator F = M . find ( std :: make_pair ( FromN , ToN ) ) ; if ( F != M . end ( ) ) return F -> second ; unsigned ToRPO = RPO . lookup ( ToN ) ; unsigned MaxD = 0 ; for ( const MachineBasicBlock * PB : ToB -> predecessors ( ) ) { if ( PB == FromB || RPO . lookup ( PB -> getNumber ( ) ) >= ToRPO ) continue ; unsigned D = PB -> size ( ) + distance ( FromB , PB , RPO , M ) ; if ( D > MaxD ) MaxD = D ; } M . insert ( std :: make_pair ( std :: make_pair ( FromN , ToN ) , MaxD ) ) ; return MaxD ; } </s>

Return the distance from this index to the given one .


<s> void MipsFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const { const MipsRegisterInfo * RegInfo = static_cast < const MipsRegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; RegInfo -> processFunctionBeforeFrameFinalized ( MF ) ; } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> MCDisassembler :: DecodeStatus XCoreDisassembler :: getInstruction ( MCInst & instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & cStream ) const { uint16_t insn16 ; if ( ! readInstruction16 ( Bytes , Address , Size , insn16 ) ) { return Fail ; } DecodeStatus Result = decodeInstruction ( DecoderTable16 , instr , insn16 , Address , this , STI ) ; if ( Result != Fail ) { Size = 2 ; return Result ; } uint32_t insn32 ; if ( ! readInstruction32 ( Bytes , Address , Size , insn32 ) ) { return Fail ; } Result = decodeInstruction ( DecoderTable32 , instr , insn32 , Address , this , STI ) ; if ( Result != Fail ) { Size = 4 ; return Result ; } return Fail ; } </s>

Returns the disassembly of a single instruction .


<s> static bool s390_cannot_copy_insn_p ( rtx insn ) { rtx label = s390_execute_label ( insn ) ; return label && label != const0_rtx ; } </s>

Indicate that INSN can not be duplicated . This is the case for execute insns that carry a unique label .


<s> SDValue SystemZTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; unsigned Opcode = N -> getOpcode ( ) ; if ( Opcode == ISD :: SIGN_EXTEND ) { SDValue N0 = N -> getOperand ( 0 ) ; EVT VT = N -> getValueType ( 0 ) ; if ( N0 . hasOneUse ( ) && N0 . getOpcode ( ) == ISD :: SRA ) { auto * SraAmt = dyn_cast < ConstantSDNode > ( N0 . getOperand ( 1 ) ) ; SDValue Inner = N0 . getOperand ( 0 ) ; if ( SraAmt && Inner . hasOneUse ( ) && Inner . getOpcode ( ) == ISD :: SHL ) { if ( auto * ShlAmt = dyn_cast < ConstantSDNode > ( Inner . getOperand ( 1 ) ) ) { unsigned Extra = ( VT . getSizeInBits ( ) - N0 . getValueType ( ) . getSizeInBits ( ) ) ; unsigned NewShlAmt = ShlAmt -> getZExtValue ( ) + Extra ; unsigned NewSraAmt = SraAmt -> getZExtValue ( ) + Extra ; EVT ShiftVT = N0 . getOperand ( 1 ) . getValueType ( ) ; SDValue Ext = DAG . getNode ( ISD :: ANY_EXTEND , SDLoc ( Inner ) , VT , Inner . getOperand ( 0 ) ) ; SDValue Shl = DAG . getNode ( ISD :: SHL , SDLoc ( Inner ) , VT , Ext , DAG . getConstant ( NewShlAmt , ShiftVT ) ) ; return DAG . getNode ( ISD :: SRA , SDLoc ( N0 ) , VT , Shl , DAG . getConstant ( NewSraAmt , ShiftVT ) ) ; } } } } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> static void sh_trampoline_init ( rtx tramp_mem , tree fndecl , rtx cxt ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx tramp = force_reg ( Pmode , XEXP ( tramp_mem , 0 ) ) ; if ( TARGET_FDPIC ) { rtx a = force_reg ( Pmode , plus_constant ( Pmode , XEXP ( tramp_mem , 0 ) , 8 ) ) ; sh_emit_storesi ( tramp_mem , 0 , a ) ; sh_emit_storesi ( tramp_mem , 4 , sh_get_fdpic_reg_initial_val ( ) ) ; sh_emit_storehi ( tramp_mem , 8 , 0xd302 , 0xd203 ) ; sh_emit_storehi ( tramp_mem , 12 , 0x6122 , 0x5c21 ) ; sh_emit_storehi ( tramp_mem , 16 , 0x412b , 0x0009 ) ; sh_emit_storesi ( tramp_mem , 20 , cxt ) ; sh_emit_storesi ( tramp_mem , 24 , fnaddr ) ; } else { sh_emit_storehi ( tramp_mem , 0 , 0xd202 , 0xd301 ) ; sh_emit_storehi ( tramp_mem , 4 , 0x422b , 0x0009 ) ; sh_emit_storesi ( tramp_mem , 8 , cxt ) ; sh_emit_storesi ( tramp_mem , 12 , fnaddr ) ; } if ( TARGET_HARD_SH4 ) { if ( ! TARGET_INLINE_IC_INVALIDATE || ( ! ( TARGET_SH4A || TARGET_SH4_300 ) && TARGET_USERMODE ) ) emit_library_call ( function_symbol ( NULL , "__ic_invalidate" , FUNCTION_ORDINARY ) . sym , LCT_NORMAL , VOIDmode , 1 , tramp , SImode ) ; else emit_insn ( gen_ic_invalidate_line ( tramp ) ) ; } } </s>

Emit RTL insns to initialize the variable parts of a trampoline . FNADDR is an RTX for the address of the function 's pure code . CXT is an RTX for the static chain value for the function .


<s> virtual const DCPU16Subtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>


<s> static unsigned int h8300_short_immediate_length ( rtx op ) { enum h8300_operand_class opclass ; unsigned int size , operand_length ; size = GET_MODE_SIZE ( GET_MODE ( op ) ) ; operand_length = h8300_classify_operand ( op , size , & opclass ) ; switch ( opclass ) { case H8OP_REGISTER : return 2 ; case H8OP_MEM_BASE : case H8OP_MEM_ABSOLUTE : case H8OP_MEM_COMPLEX : return 4 + operand_length ; default : gcc_unreachable ( ) ; } } </s>

Likewise short immediate instructions such as add.w # xx:3 , OP .


<s> static bool cris_function_value_regno_p ( const unsigned int regno ) { return ( regno == CRIS_FIRST_ARG_REG ) ; } </s>

Let 's assume all functions return in r [ CRIS_FIRST_ARG_REG ] for the time being .


<s>
StringRef
getPassName
(
)
const
override
{
return
"WebAssembly Lower br_unless"
;
}
</s>

getPassName - Return a nice clean name for a pass .

WebAssembly
"WebAssembly Lower br_unless"


<s>
bool
FixupBWInstPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
!
FixupBWInsts
||
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
this
->
MF
=
&
MF
;
TII
=
MF
.
getSubtarget
<
X86Subtarget
>
(
)
.
getInstrInfo
(
)
;
OptForSize
=
MF
.
getFunction
(
)
.
optForSize
(
)
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
LiveRegs
.
init
(
TII
->
getRegisterInfo
(
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Start X86FixupBWInsts\n"
;
)
;
for
(
auto
&
MBB
:
MF
)
processBasicBlock
(
MF
,
MBB
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"End X86FixupBWInsts\n"
;
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> static unsigned int avr_case_values_threshold ( void ) { return 7 ; } </s>

Supply the default for -- param case-values-threshold=0


<s>
const
MCExpr
*
ARMElfTargetObjectFile
::
getTTypeGlobalReference
(
const
GlobalValue
*
GV
,
unsigned
Encoding
,
Mangler
&
Mang
,
const
TargetMachine
&
TM
,
MachineModuleInfo
*
MMI
,
MCStreamer
&
Streamer
)
const
{
if
(
TM
.
getMCAsmInfo
(
)
->
getExceptionHandlingType
(
)
!=
ExceptionHandling
::
ARM
)
return
TargetLoweringObjectFileELF
::
getTTypeGlobalReference
(
GV
,
Encoding
,
Mang
,
TM
,
MMI
,
Streamer
)
;
assert
(
Encoding
==
DW_EH_PE_absptr
&&
"Can handle absptr encoding only"
)
;
Triple
T
(
MMI
->
getModule
(
)
->
getTargetTriple
(
)
)
;
if
(
T
.
isOSNaCl
(
)
)
return
TargetLoweringObjectFileELF
::
getTTypeGlobalReference
(
GV
,
Encoding
,
Mang
,
TM
,
MMI
,
Streamer
)
;
return
MCSymbolRefExpr
::
Create
(
TM
.
getSymbol
(
GV
,
Mang
)
,
MCSymbolRefExpr
::
VK_ARM_TARGET2
,
getContext
(
)
)
;
}
</s>

The mach-o version of this method defaults to returning a stub reference .

ARM
ARM
ARM
"Can handle absptr encoding only"
ARM


<s>
bool
WebAssemblyStoreResults
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
DEBUG
(
{
dbgs
(
)
<<
"********** Store Results **********\n"
<<
"********** Function: "
<<
MF
.
getName
(
)
<<
'\n'
;
}
)
;
const
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
MachineDominatorTree
&
MDT
=
getAnalysis
<
MachineDominatorTree
>
(
)
;
bool
Changed
=
false
;
assert
(
MRI
.
isSSA
(
)
&&
"StoreResults depends on SSA form"
)
;
for
(
auto
&
MBB
:
MF
)
{
DEBUG
(
dbgs
(
)
<<
"Basic Block: "
<<
MBB
.
getName
(
)
<<
'\n'
)
;
for
(
auto
&
MI
:
MBB
)
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
WebAssembly
::
STORE8_I32
:
case
WebAssembly
::
STORE16_I32
:
case
WebAssembly
::
STORE8_I64
:
case
WebAssembly
::
STORE16_I64
:
case
WebAssembly
::
STORE32_I64
:
case
WebAssembly
::
STORE_F32
:
case
WebAssembly
::
STORE_F64
:
case
WebAssembly
::
STORE_I32
:
case
WebAssembly
::
STORE_I64
:
unsigned
ToReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
unsigned
FromReg
=
MI
.
getOperand
(
3
)
.
getReg
(
)
;
for
(
auto
I
=
MRI
.
use_begin
(
FromReg
)
,
E
=
MRI
.
use_end
(
)
;
I
!=
E
;
)
{
MachineOperand
&
O
=
*
I
++
;
MachineInstr
*
Where
=
O
.
getParent
(
)
;
if
(
Where
->
getOpcode
(
)
==
TargetOpcode
::
PHI
)
{
MachineBasicBlock
*
Pred
=
Where
->
getOperand
(
&
O
&
Where
->
getOperand
(
0
)
+
1
)
.
getMBB
(
)
;
if
(
!
MDT
.
dominates
(
&
MBB
,
Pred
)
)
continue
;
}
else
{
if
(
&
MI
==
Where
||
!
MDT
.
dominates
(
&
MI
,
Where
)
)
continue
;
}
Changed
=
true
;
DEBUG
(
dbgs
(
)
<<
"Setting operand "
<<
O
<<
" in "
<<
*
Where
<<
" from "
<<
MI
<<
"\n"
)
;
O
.
setReg
(
ToReg
)
;
assert
(
!
MI
.
getOperand
(
0
)
.
isDead
(
)
&&
"Dead flag set on store result"
)
;
}
}
}
return
Changed
;
}
</s>


<s> Value * ARMTargetLowering :: emitStoreConditional ( IRBuilder < > & Builder , Value * Val , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = isAtLeastRelease ( Ord ) ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == 64 ) { Intrinsic :: ID Int = IsRelease ? Intrinsic :: arm_stlexd : Intrinsic :: arm_strexd ; Function * Strex = Intrinsic :: getDeclaration ( M , Int ) ; Type * Int32Ty = Type :: getInt32Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int32Ty , "lo" ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , 32 ) , Int32Ty , "hi" ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall3 ( Strex , Lo , Hi , Addr ) ; } Intrinsic :: ID Int = IsRelease ? Intrinsic :: arm_stlex : Intrinsic :: arm_strex ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Strex = Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateCall2 ( Strex , Builder . CreateZExtOrBitCast ( Val , Strex -> getFunctionType ( ) -> getParamType ( 0 ) ) , Addr ) ; } </s>

Perform a store-conditional operation to Addr .


<s>
const
MCExpr
*
SystemZMCInstLower
::
getExpr
(
const
MachineOperand
&
MO
,
MCSymbolRefExpr
::
VariantKind
Kind
)
const
{
const
MCSymbol
*
Symbol
;
bool
HasOffset
=
true
;
switch
(
MO
.
getType
(
)
)
{
case
MachineOperand
::
MO_MachineBasicBlock
:
Symbol
=
MO
.
getMBB
(
)
->
getSymbol
(
)
;
HasOffset
=
false
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
Symbol
=
AsmPrinter
.
getSymbol
(
MO
.
getGlobal
(
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
Symbol
=
AsmPrinter
.
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
Symbol
=
AsmPrinter
.
GetJTISymbol
(
MO
.
getIndex
(
)
)
;
HasOffset
=
false
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
Symbol
=
AsmPrinter
.
GetCPISymbol
(
MO
.
getIndex
(
)
)
;
break
;
case
MachineOperand
::
MO_BlockAddress
:
Symbol
=
AsmPrinter
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
;
break
;
default
:
llvm_unreachable
(
"unknown operand type"
)
;
}
const
MCExpr
*
Expr
=
MCSymbolRefExpr
::
Create
(
Symbol
,
Kind
,
Ctx
)
;
if
(
HasOffset
)
if
(
int64_t
Offset
=
MO
.
getOffset
(
)
)
{
const
MCExpr
*
OffsetExpr
=
MCConstantExpr
::
Create
(
Offset
,
Ctx
)
;
Expr
=
MCBinaryExpr
::
CreateAdd
(
Expr
,
OffsetExpr
,
Ctx
)
;
}
return
Expr
;
}
</s>

Implementation of the SCEVPredicate interface .


<s> yaml :: MachineFunctionInfo * GCNTargetMachine :: convertFuncInfoToYAML ( const MachineFunction & MF ) const { const SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; return new yaml :: SIMachineFunctionInfo ( * MFI , * MF . getSubtarget ( ) . getRegisterInfo ( ) , MF ) ; } </s>

Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo .


<s> bool isReg ( ) const override { return Kind == KindTy :: Register ; } </s>


<s> void NVPTXTTIImpl :: getPeelingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: PeelingPreferences & PP ) { BaseT :: getPeelingPreferences ( L , SE , PP ) ; } </s>

Get target-customized preferences for the generic loop peeling transformation .


<s> bool GCNPassConfig :: addPreISel ( ) { AMDGPUPassConfig :: addPreISel ( ) ; if ( EnableAtomicOptimizations ) { addPass ( createAMDGPUAtomicOptimizerPass ( ) ) ; } addPass ( & AMDGPUUnifyDivergentExitNodesID ) ; if ( ! LateCFGStructurize ) { addPass ( createStructurizeCFGPass ( true ) ) ; } addPass ( createSinkingPass ( ) ) ; addPass ( createAMDGPUAnnotateUniformValues ( ) ) ; if ( ! LateCFGStructurize ) { addPass ( createSIAnnotateControlFlowPass ( ) ) ; } addPass ( createLCSSAPass ( ) ) ; return false ; } </s>


<s> void eliminateFrameIndex ( MachineBasicBlock :: iterator MI , int SPAdj , unsigned FIOperandNum , RegScavenger * RS = nullptr ) const override { } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> void sparc_flat_expand_epilogue ( bool for_eh ) { HOST_WIDE_INT size = sparc_frame_size ; if ( sparc_n_global_fp_regs > 0 ) emit_save_or_restore_global_fp_regs ( sparc_frame_base_reg , sparc_frame_base_offset - sparc_apparent_frame_size , SORR_RESTORE ) ; if ( frame_pointer_needed && ! for_eh ) emit_move_insn ( gen_rtx_REG ( Pmode , 1 ) , hard_frame_pointer_rtx ) ; if ( return_addr_reg_needed_p ( sparc_leaf_function_p ) ) emit_move_insn ( gen_rtx_REG ( Pmode , INCOMING_RETURN_ADDR_REGNUM ) , gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ) ; if ( sparc_save_local_in_regs_p ) emit_save_or_restore_local_in_regs ( sparc_frame_base_reg , sparc_frame_base_offset , SORR_RESTORE ) ; if ( size == 0 || for_eh ) ; else if ( frame_pointer_needed ) { emit_insn ( gen_frame_blockage ( ) ) ; emit_move_insn ( stack_pointer_rtx , gen_rtx_REG ( Pmode , 1 ) ) ; } else { emit_insn ( gen_frame_blockage ( ) ) ; if ( size <= 4096 ) emit_insn ( gen_stack_pointer_inc ( GEN_INT ( size ) ) ) ; else if ( size <= 8192 ) { emit_insn ( gen_stack_pointer_inc ( GEN_INT ( 4096 ) ) ) ; emit_insn ( gen_stack_pointer_inc ( GEN_INT ( size - 4096 ) ) ) ; } else { rtx reg = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( reg , GEN_INT ( size ) ) ; emit_insn ( gen_stack_pointer_inc ( reg ) ) ; } } } </s>

Expand the function epilogue , either normal or part of a sibcall . We emit all the instructions except the return or the call .


<s> static bool mflip_mips16_use_mips16_p ( tree decl ) { const char * name ; bool base_is_mips16 = ( mips_base_compression_flags & MASK_MIPS16 ) != 0 ; if ( ! DECL_NAME ( decl ) ) return ! base_is_mips16 ; if ( ! mflip_mips16_htab ) mflip_mips16_htab = hash_map < nofree_string_hash , bool > :: create_ggc ( 37 ) ; name = IDENTIFIER_POINTER ( DECL_NAME ( decl ) ) ; bool existed ; bool * slot = & mflip_mips16_htab -> get_or_insert ( name , & existed ) ; if ( ! existed ) { mips16_flipper = ! mips16_flipper ; * slot = mips16_flipper ? ! base_is_mips16 : base_is_mips16 ; } return * slot ; } </s>

DECL is a function that needs a default `` mips16 '' or `` nomips16 '' attribute for -mflip-mips16 . Return true if it should use `` mips16 '' and false if it should use `` nomips16 '' .


<s> SDValue PPCTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { if ( PPCSubTarget . isSVR4ABI ( ) ) { if ( PPCSubTarget . isPPC64 ( ) ) return LowerFormalArguments_64SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; else return LowerFormalArguments_32SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } else { return LowerFormalArguments_Darwin ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> int cr16_function_arg_regno_p ( int n ) { return ( ( n <= MAX_REG_FOR_PASSING_ARGS ) && ( n >= MIN_REG_FOR_PASSING_ARGS ) ) ; } </s>

Implements the macro FUNCTION_ARG_REGNO_P defined in cr16.h . Return nonzero if N is a register used for passing parameters .


<s> bool rs6000_emit_set_const ( rtx dest , rtx source ) { machine_mode mode = GET_MODE ( dest ) ; rtx temp , set ; rtx_insn * insn ; HOST_WIDE_INT c ; gcc_checking_assert ( CONST_INT_P ( source ) ) ; c = INTVAL ( source ) ; switch ( mode ) { case QImode : case HImode : emit_insn ( gen_rtx_SET ( VOIDmode , dest , source ) ) ; return true ; case SImode : temp = ! can_create_pseudo_p ( ) ? dest : gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , copy_rtx ( temp ) , GEN_INT ( c & ~ ( HOST_WIDE_INT ) 0xffff ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , gen_rtx_IOR ( SImode , copy_rtx ( temp ) , GEN_INT ( c & 0xffff ) ) ) ) ; break ; case DImode : if ( ! TARGET_POWERPC64 ) { rtx hi , lo ; hi = operand_subword_force ( copy_rtx ( dest ) , WORDS_BIG_ENDIAN == 0 , DImode ) ; lo = operand_subword_force ( dest , WORDS_BIG_ENDIAN != 0 , DImode ) ; emit_move_insn ( hi , GEN_INT ( c >> 32 ) ) ; c = ( ( c & 0xffffffff ) ^ 0x80000000 ) - 0x80000000 ; emit_move_insn ( lo , GEN_INT ( c ) ) ; } else rs6000_emit_set_long_const ( dest , c ) ; break ; default : gcc_unreachable ( ) ; } insn = get_last_insn ( ) ; set = single_set ( insn ) ; if ( ! CONSTANT_P ( SET_SRC ( set ) ) ) set_unique_reg_note ( insn , REG_EQUAL , GEN_INT ( c ) ) ; return true ; } </s>

Try to output insns to set TARGET equal to the constant C if it can be done in less than N insns . Do all computations in MODE . Returns the place where the output has been placed if it can be done and the insns have been emitted . If it would take more than N insns , zero is returned and no insns and emitted .


<s> static poly_uint16 aarch64_convert_sve_vector_bits ( aarch64_sve_vector_bits_enum value ) { if ( value == SVE_SCALABLE || value == SVE_128 ) return poly_uint16 ( 2 , 2 ) ; else return ( int ) value / 64 ; } </s>

Return the VG value associated with -msve-vector-bits= value VALUE .


<s> static bool mips_hard_regno_mode_ok_p ( unsigned int regno , machine_mode mode ) { unsigned int size ; enum mode_class mclass ; if ( mode == CCV2mode ) return ( ISA_HAS_8CC && ST_REG_P ( regno ) && ( regno - ST_REG_FIRST ) % 2 == 0 ) ; if ( mode == CCV4mode ) return ( ISA_HAS_8CC && ST_REG_P ( regno ) && ( regno - ST_REG_FIRST ) % 4 == 0 ) ; if ( mode == CCmode ) return ISA_HAS_8CC ? ST_REG_P ( regno ) : regno == FPSW_REGNUM ; size = GET_MODE_SIZE ( mode ) ; mclass = GET_MODE_CLASS ( mode ) ; if ( GP_REG_P ( regno ) && mode != CCFmode && ! MSA_SUPPORTED_MODE_P ( mode ) ) return ( ( regno - GP_REG_FIRST ) & 1 ) == 0 || size <= UNITS_PER_WORD ; if ( FP_REG_P ( regno ) && MSA_SUPPORTED_MODE_P ( mode ) ) return true ; if ( FP_REG_P ( regno ) && ( ( ( regno - FP_REG_FIRST ) % MAX_FPRS_PER_FMT ) == 0 || ( MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG ) ) ) { if ( TARGET_O32_FP64A_ABI && size <= 4 && ( regno & 1 ) != 0 ) return false ; if ( mode == CCFmode ) return ! ( TARGET_FLOATXX && ( regno & 1 ) != 0 ) ; if ( TARGET_LOONGSON_VECTORS && ( mode == V2SImode || mode == V4HImode || mode == V8QImode || mode == DImode ) ) return true ; if ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT || mclass == MODE_VECTOR_FLOAT ) return size <= UNITS_PER_FPVALUE ; if ( mclass == MODE_INT ) return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG ; } if ( ACC_REG_P ( regno ) && ! VECTOR_MODE_P ( mode ) && ( INTEGRAL_MODE_P ( mode ) || ALL_FIXED_POINT_MODE_P ( mode ) ) ) { if ( MD_REG_P ( regno ) ) { if ( size <= UNITS_PER_WORD * 2 ) return regno == ( size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST ) ; } else { if ( size <= UNITS_PER_WORD ) return true ; if ( size <= UNITS_PER_WORD * 2 && ( ( regno - DSP_ACC_REG_FIRST ) & 1 ) == 0 ) return true ; } } if ( ALL_COP_REG_P ( regno ) ) return mclass == MODE_INT && size <= UNITS_PER_WORD ; if ( regno == GOT_VERSION_REGNUM ) return mode == SImode ; return false ; } </s>

Return true if register REGNO can store a value of mode MODE . The result of this function is cached in mips_hard_regno_mode_ok .


<s>
bool
HexagonPacketizer
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
auto
&
HST
=
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
;
HII
=
HST
.
getInstrInfo
(
)
;
HRI
=
HST
.
getRegisterInfo
(
)
;
auto
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
auto
*
AA
=
&
getAnalysis
<
AAResultsWrapperPass
>
(
)
.
getAAResults
(
)
;
auto
*
MBPI
=
&
getAnalysis
<
MachineBranchProbabilityInfo
>
(
)
;
if
(
EnableGenAllInsnClass
)
HII
->
genAllInsnTimingClasses
(
MF
)
;
bool
MinOnly
=
Minimal
||
DisablePacketizer
||
!
HST
.
usePackets
(
)
||
skipFunction
(
MF
.
getFunction
(
)
)
;
HexagonPacketizerList
Packetizer
(
MF
,
MLI
,
AA
,
MBPI
,
MinOnly
)
;
assert
(
Packetizer
.
getResourceTracker
(
)
&&
"Empty DFA table!"
)
;
for
(
MachineBasicBlock
&
MB
:
MF
)
{
auto
End
=
MB
.
end
(
)
;
auto
MI
=
MB
.
begin
(
)
;
while
(
MI
!=
End
)
{
auto
NextI
=
std
::
next
(
MI
)
;
if
(
MI
->
isKill
(
)
)
{
MB
.
erase
(
MI
)
;
End
=
MB
.
end
(
)
;
}
MI
=
NextI
;
}
}
for
(
auto
&
MB
:
MF
)
{
auto
Begin
=
MB
.
begin
(
)
,
End
=
MB
.
end
(
)
;
while
(
Begin
!=
End
)
{
MachineBasicBlock
::
iterator
RB
=
Begin
;
while
(
RB
!=
End
&&
HII
->
isSchedulingBoundary
(
*
RB
,
&
MB
,
MF
)
)
++
RB
;
MachineBasicBlock
::
iterator
RE
=
RB
;
while
(
RE
!=
End
&&
!
HII
->
isSchedulingBoundary
(
*
RE
,
&
MB
,
MF
)
)
++
RE
;
if
(
RE
!=
End
)
++
RE
;
if
(
RB
!=
End
)
Packetizer
.
PacketizeMIs
(
&
MB
,
RB
,
RE
)
;
Begin
=
RE
;
}
}
Packetizer
.
unpacketizeSoloInstrs
(
MF
)
;
return
true
;
}
</s>

Hexagon
Hexagon
Hexagon
Hexagon
"Empty DFA table!"


<s>
const
char
*
getPassName
(
)
const
{
return
"SI Assign intrpolation registers"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
static
void
spu_option_override
(
void
)
{
init_machine_status
=
spu_init_machine_status
;
if
(
!
flag_unroll_loops
&&
!
flag_peel_loops
)
maybe_set_param_value
(
PARAM_MAX_COMPLETELY_PEEL_TIMES
,
4
,
global_options
.
x_param_values
,
global_options_set
.
x_param_values
)
;
flag_omit_frame_pointer
=
1
;
if
(
align_functions
<
8
)
align_functions
=
8
;
spu_hint_dist
=
8
*
4
spu_max_nops
*
4
;
if
(
spu_hint_dist
<
0
)
spu_hint_dist
=
0
;
if
(
spu_fixed_range_string
)
fix_range
(
spu_fixed_range_string
)
;
if
(
spu_arch_string
)
{
if
(
strcmp
(
&
spu_arch_string
[
0
]
,
"cell"
)
==
0
)
spu_arch
=
PROCESSOR_CELL
;
else
if
(
strcmp
(
&
spu_arch_string
[
0
]
,
"celledp"
)
==
0
)
spu_arch
=
PROCESSOR_CELLEDP
;
else
error
(
"bad value (%s) for -march= switch"
,
spu_arch_string
)
;
}
if
(
spu_tune_string
)
{
if
(
strcmp
(
&
spu_tune_string
[
0
]
,
"cell"
)
==
0
)
spu_tune
=
PROCESSOR_CELL
;
else
if
(
strcmp
(
&
spu_tune_string
[
0
]
,
"celledp"
)
==
0
)
spu_tune
=
PROCESSOR_CELLEDP
;
else
error
(
"bad value (%s) for -mtune= switch"
,
spu_tune_string
)
;
}
if
(
spu_arch
==
PROCESSOR_CELLEDP
)
{
if
(
!
(
target_flags_explicit
&
MASK_SAFE_HINTS
)
)
target_flags
&=
~
MASK_SAFE_HINTS
;
}
REAL_MODE_FORMAT
(
SFmode
)
=
&
spu_single_format
;
}
</s>


"non-standard ABI extension with no compatibility guarantee"

Return a nonzero value to say to return the function value in memory , just as large structures are always returned . TYPE will be the data type of the value , and FNTYPE will be the type of the function doing the returning , or @ code { NULL } for libcalls . The AIX ABI for the RS/6000 specifies that all structures are returned in memory . The Darwin ABI does the same . The SVR4 ABI specifies that structures < = 8 bytes are returned in r3/r4 , but a draft put them in memory , and GCC used to implement the draft instead of the final standard . Therefore , aix_struct_return controls this instead of DEFAULT_ABI ; V.4 targets needing backward compatibility can change DRAFT_V4_STRUCT_RET to override the default , and -m switches get the final word . See rs6000_override_options for more details . The PPC32 SVR4 ABI uses IEEE double extended for long double , if 128-bit long double support is enabled . These values are returned in memory . int_size_in_bytes returns -1 for variable size objects , which go in memory always . The cast to unsigned makes -1 > 8 .


<s> static void initialize_aarch64_tls_size ( struct gcc_options * opts ) { if ( aarch64_tls_size == 0 ) aarch64_tls_size = 24 ; switch ( opts -> x_aarch64_cmodel_var ) { case AARCH64_CMODEL_TINY : if ( aarch64_tls_size > 24 ) aarch64_tls_size = 24 ; break ; case AARCH64_CMODEL_SMALL : if ( aarch64_tls_size > 32 ) aarch64_tls_size = 32 ; break ; case AARCH64_CMODEL_LARGE : if ( aarch64_tls_size > 48 ) aarch64_tls_size = 48 ; break ; default : gcc_unreachable ( ) ; } return ; } </s>

A checking mechanism for the implementation of the tls size .


<s> static bool riscv_interrupt_type_p ( tree type ) { return lookup_attribute ( "interrupt" , TYPE_ATTRIBUTES ( type ) ) != NULL ; } </s>

Return true if function TYPE is an interrupt function .


"%Kargument %d must be a constant immediate"

Expand a FCMLA lane expression EXP with code FCODE and result going to TARGET if that is convenient .


<s> void RISCVConstantPoolValue :: print ( raw_ostream & O ) const { O << GV ; } </s>

print - Print a debug representation of the operand to the given stream .


<s> static rtx frv_dwarf_store ( rtx reg , int offset ) { rtx set = gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( GET_MODE ( reg ) , plus_constant ( stack_pointer_rtx , offset ) ) , reg ) ; RTX_FRAME_RELATED_P ( set ) = 1 ; return set ; } </s>

Generate a frame-related expression : ( set REG ( mem ( plus ( sp ) ( const_int OFFSET ) ) ) ) . Such expressions are used in FRAME_RELATED_EXPR notes for more complex instructions . Marking the expressions as frame-related is superfluous if the note contains just a single set . But if the note contains a PARALLEL or SEQUENCE that has several sets , each set must be individually marked as frame-related .


<s> unsigned AArch64InstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return 0 ; if ( ! isUncondBranchOpcode ( I -> getOpcode ( ) ) && ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return 0 ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) { if ( BytesRemoved ) * BytesRemoved = 4 ; return 1 ; } -- I ; if ( ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) { if ( BytesRemoved ) * BytesRemoved = 4 ; return 1 ; } I -> eraseFromParent ( ) ; if ( BytesRemoved ) * BytesRemoved = 8 ; return 2 ; } </s>

Remove the branching code at the end of the specific MBB .


<s> unsigned int pass_s390_early_mach :: execute ( function * fun ) { rtx_insn * insn ; s390_optimize_nonescaping_tx ( ) ; s390_register_info ( ) ; if ( fun -> machine -> base_reg ) emit_insn_at_entry ( gen_main_pool ( fun -> machine -> base_reg ) ) ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) ) { annotate_constant_pool_refs ( & PATTERN ( insn ) ) ; df_insn_rescan ( insn ) ; } return 0 ; } </s>


<s> BitVector TeeRISCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t ReservedCPURegs [ ] = { TeeRISC :: R0 , TeeRISC :: R1 , TeeRISC :: R14 , TeeRISC :: R15 , TeeRISC :: R16 , TeeRISC :: R17 , TeeRISC :: R18 , TeeRISC :: R19 , TeeRISC :: R20 , TeeRISC :: R21 , TeeRISC :: R22 , TeeRISC :: R23 , TeeRISC :: R24 , TeeRISC :: R25 , TeeRISC :: R26 , TeeRISC :: R27 , TeeRISC :: R28 , TeeRISC :: R29 , TeeRISC :: R30 , TeeRISC :: R31 } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: iterator RegIter ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: CreateImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ; } </s>


<s>
void
ARMELFStreamer
::
EmitRegSave
(
const
SmallVectorImpl
<
unsigned
>
&
RegList
,
bool
IsVector
)
{
unsigned
Count
=
0
;
uint32_t
Mask
=
0
;
const
MCRegisterInfo
*
MRI
=
getContext
(
)
.
getRegisterInfo
(
)
;
for
(
size_t
i
=
0
;
i
<
RegList
.
size
(
)
;
++
i
)
{
unsigned
Reg
=
MRI
->
getEncodingValue
(
RegList
[
i
]
)
;
assert
(
Reg
<
(
IsVector
32U
:
16U
)
&&
"Register out of range"
)
;
unsigned
Bit
=
(
1u
<<
Reg
)
;
if
(
(
Mask
&
Bit
)
==
0
)
{
Mask
|=
Bit
;
++
Count
;
}
}
SPOffset
-=
Count
*
(
IsVector
8
:
4
)
;
FlushPendingOffset
(
)
;
if
(
IsVector
)
UnwindOpAsm
.
EmitVFPRegSave
(
Mask
)
;
else
UnwindOpAsm
.
EmitRegSave
(
Mask
)
;
}
</s>

Emit unwind opcodes for .save directives .


<s>
static
void
rx_print_operand_address
(
FILE
*
file
,
machine_mode
,
rtx
addr
)
{
switch
(
GET_CODE
(
addr
)
)
{
case
REG
:
fprintf
(
file
,
"["
)
;
rx_print_operand
(
file
,
addr
,
0
)
;
fprintf
(
file
,
"]"
)
;
break
;
case
PRE_DEC
:
fprintf
(
file
,
"[-"
)
;
rx_print_operand
(
file
,
XEXP
(
addr
,
0
)
,
0
)
;
fprintf
(
file
,
"]"
)
;
break
;
case
POST_INC
:
fprintf
(
file
,
"["
)
;
rx_print_operand
(
file
,
XEXP
(
addr
,
0
)
,
0
)
;
fprintf
(
file
,
"+]"
)
;
break
;
case
PLUS
:
{
rtx
arg1
=
XEXP
(
addr
,
0
)
;
rtx
arg2
=
XEXP
(
addr
,
1
)
;
rtx
base
,
index
;
if
(
REG_P
(
arg1
)
&&
RTX_OK_FOR_BASE
(
arg1
,
true
)
)
base
=
arg1
,
index
=
arg2
;
else
if
(
REG_P
(
arg2
)
&&
RTX_OK_FOR_BASE
(
arg2
,
true
)
)
base
=
arg2
,
index
=
arg1
;
else
{
rx_print_operand
(
file
,
arg1
,
0
)
;
fprintf
(
file
,
" + "
)
;
rx_print_operand
(
file
,
arg2
,
0
)
;
break
;
}
if
(
REG_P
(
index
)
||
GET_CODE
(
index
)
==
MULT
)
{
fprintf
(
file
,
"["
)
;
rx_print_operand
(
file
,
index
,
'A'
)
;
fprintf
(
file
,
","
)
;
}
else
{
rx_print_operand
(
file
,
index
,
'A'
)
;
fprintf
(
file
,
"["
)
;
}
rx_print_operand
(
file
,
base
,
0
)
;
fprintf
(
file
,
"]"
)
;
break
;
}
case
CONST
:
if
(
GET_CODE
(
XEXP
(
addr
,
0
)
)
==
UNSPEC
)
{
addr
=
XEXP
(
addr
,
0
)
;
gcc_assert
(
XINT
(
addr
,
1
)
==
UNSPEC_CONST
)
;
addr
=
XVECEXP
(
addr
,
0
,
0
)
;
gcc_assert
(
CONST_INT_P
(
addr
)
)
;
fprintf
(
file
,
"#"
)
;
output_addr_const
(
file
,
addr
)
;
break
;
}
fprintf
(
file
,
"#"
)
;
output_addr_const
(
file
,
XEXP
(
addr
,
0
)
)
;
break
;
case
UNSPEC
:
addr
=
XVECEXP
(
addr
,
0
,
0
)
;
case
LABEL_REF
:
case
SYMBOL_REF
:
fprintf
(
file
,
"#"
)
;
default
:
output_addr_const
(
file
,
addr
)
;
break
;
}
}
</s>

A C compound statement to output to stdio stream FILE the assembler syntax for an instruction operand that is a memory reference whose address is ADDR .


<s> void xstormy16_expand_move ( machine_mode mode , rtx dest , rtx src ) { if ( MEM_P ( dest ) && ( GET_CODE ( XEXP ( dest , 0 ) ) == PRE_MODIFY ) ) { rtx pmv = XEXP ( dest , 0 ) ; rtx dest_reg = XEXP ( pmv , 0 ) ; rtx dest_mod = XEXP ( pmv , 1 ) ; rtx set = gen_rtx_SET ( dest_reg , dest_mod ) ; rtx clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( BImode , CARRY_REGNUM ) ) ; dest = gen_rtx_MEM ( mode , dest_reg ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set , clobber ) ) ) ; } else if ( MEM_P ( src ) && ( GET_CODE ( XEXP ( src , 0 ) ) == PRE_MODIFY ) ) { rtx pmv = XEXP ( src , 0 ) ; rtx src_reg = XEXP ( pmv , 0 ) ; rtx src_mod = XEXP ( pmv , 1 ) ; rtx set = gen_rtx_SET ( src_reg , src_mod ) ; rtx clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( BImode , CARRY_REGNUM ) ) ; src = gen_rtx_MEM ( mode , src_reg ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set , clobber ) ) ) ; } if ( ! reload_in_progress && ! reload_completed && MEM_P ( dest ) && ( ! CONST_INT_P ( XEXP ( dest , 0 ) ) || ! xstormy16_legitimate_address_p ( mode , XEXP ( dest , 0 ) , 0 ) ) && ! xstormy16_below100_operand ( dest , mode ) && ! REG_P ( src ) && GET_CODE ( src ) != SUBREG ) src = copy_to_mode_reg ( mode , src ) ; if ( reload_completed && mode != HImode && mode != QImode ) { xstormy16_split_move ( mode , dest , src ) ; return ; } emit_insn ( gen_rtx_SET ( dest , src ) ) ; } </s>

Expander for the 'move ' patterns . Emit insns to copy a value of mode MODE from SRC to DEST .


<s> static rtx save_fpr ( rtx base , int offset , int regnum ) { rtx addr ; addr = gen_rtx_MEM ( DFmode , plus_constant ( base , offset ) ) ; if ( regnum >= 16 && regnum <= ( 16 + FP_ARG_NUM_REG ) ) set_mem_alias_set ( addr , get_varargs_alias_set ( ) ) ; else set_mem_alias_set ( addr , get_frame_alias_set ( ) ) ; return emit_move_insn ( addr , gen_rtx_REG ( DFmode , regnum ) ) ; } </s>

Emit insn to save fpr REGNUM at offset OFFSET relative to register BASE . Return generated insn .


<s> bool MipsExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { STI = & MF . getSubtarget < MipsSubtarget > ( ) ; TII = STI -> getInstrInfo ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : MF ) Modified |= expandMBB ( MBB ) ; if ( Modified ) MF . RenumberBlocks ( ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


Return the DataLayout associated with the module this SCEV instance is operating on .


<s> static std :: string getGraphName ( const ScheduleDAG * G ) { return G -> MF . getName ( ) ; } </s>

Generate a title for the graph in DOT format .


<s>
bool
AArch64InstrInfo
::
isLdStPairSuppressed
(
const
MachineInstr
*
MI
)
const
{
assert
(
MOSuppressPair
<
(
1
<<
MachineMemOperand
::
MOTargetNumBits
)
&&
"Too many target MO flags"
)
;
for
(
auto
*
MM
:
MI
->
memoperands
(
)
)
{
if
(
MM
->
getFlags
(
)
&
(
MOSuppressPair
<<
MachineMemOperand
::
MOTargetStartBit
)
)
{
return
true
;
}
}
return
false
;
}
</s>

Return true if pairing the given load or store is hinted to be unprofitable .


<s> bool X86FrameInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; bool isWin64 = STI . isTargetWin64 ( ) ; unsigned SlotSize = STI . is64Bit ( ) ? 8 : 4 ; unsigned FPReg = TRI -> getFrameRegister ( MF ) ; unsigned CalleeFrameSize = 0 ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned Opc = STI . is64Bit ( ) ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; if ( Reg == FPReg ) continue ; if ( ! X86 :: VR128RegClass . contains ( Reg ) && ! isWin64 ) { CalleeFrameSize += SlotSize ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - 1 ] . getFrameIdx ( ) , RC , TRI ) ; } } X86FI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ; return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static void riscv_print_operand_address ( FILE * file , machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { struct riscv_address_info addr ; if ( riscv_classify_address ( & addr , x , word_mode , true ) ) switch ( addr . type ) { case ADDRESS_REG : riscv_print_operand ( file , addr . offset , 0 ) ; fprintf ( file , "(%s)" , reg_names [ REGNO ( addr . reg ) ] ) ; return ; case ADDRESS_LO_SUM : riscv_print_operand_reloc ( file , addr . offset , false ) ; fprintf ( file , "(%s)" , reg_names [ REGNO ( addr . reg ) ] ) ; return ; case ADDRESS_CONST_INT : output_addr_const ( file , x ) ; fprintf ( file , "(%s)" , reg_names [ GP_REG_FIRST ] ) ; return ; case ADDRESS_SYMBOLIC : output_addr_const ( file , riscv_strip_unspec_address ( x ) ) ; return ; } gcc_unreachable ( ) ; } </s>


<s> bool ELFAArch64AsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> void ix86_expand_floorceildf_32 ( rtx operand0 , rtx operand1 , bool do_floor ) { machine_mode mode = GET_MODE ( operand0 ) ; rtx xa , TWO52 , tmp , one , res , mask ; rtx_code_label * label ; TWO52 = ix86_gen_TWO52 ( mode ) ; res = copy_to_reg ( operand1 ) ; xa = ix86_expand_sse_fabs ( res , & mask ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; xa = expand_simple_binop ( mode , PLUS , xa , TWO52 , NULL_RTX , 0 , OPTAB_DIRECT ) ; xa = expand_simple_binop ( mode , MINUS , xa , TWO52 , xa , 0 , OPTAB_DIRECT ) ; ix86_sse_copysign_to_positive ( xa , xa , res , mask ) ; one = force_reg ( mode , const_double_from_real_value ( dconst1 , mode ) ) ; tmp = ix86_expand_sse_compare_mask ( UNGT , xa , res , ! do_floor ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_AND ( mode , one , tmp ) ) ) ; tmp = expand_simple_binop ( mode , do_floor ? MINUS : PLUS , xa , tmp , NULL_RTX , 0 , OPTAB_DIRECT ) ; if ( HONOR_SIGNED_ZEROS ( mode ) ) { if ( do_floor && flag_rounding_math ) tmp = ix86_expand_sse_fabs ( tmp , NULL ) ; ix86_sse_copysign_to_positive ( tmp , tmp , res , mask ) ; } emit_move_insn ( res , tmp ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; emit_move_insn ( operand0 , res ) ; } </s>

Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing into OPERAND0 .


<s> bool isShuffleMaskLegal ( ArrayRef < int > Mask , EVT VT ) const override { return false ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> static bool offsettable_ok_by_alignment ( rtx op , HOST_WIDE_INT offset , machine_mode mode ) { tree decl ; unsigned HOST_WIDE_INT dsize , dalign , lsb , mask ; if ( GET_CODE ( op ) != SYMBOL_REF ) return false ; if ( mode_supports_vsx_dform_quad ( mode ) ) return false ; dsize = GET_MODE_SIZE ( mode ) ; decl = SYMBOL_REF_DECL ( op ) ; if ( ! decl ) { if ( dsize == 0 ) return false ; dalign = BITS_PER_UNIT ; if ( SYMBOL_REF_HAS_BLOCK_INFO_P ( op ) && SYMBOL_REF_ANCHOR_P ( op ) && SYMBOL_REF_BLOCK ( op ) != NULL ) { struct object_block * block = SYMBOL_REF_BLOCK ( op ) ; dalign = block -> alignment ; offset += SYMBOL_REF_BLOCK_OFFSET ( op ) ; } else if ( CONSTANT_POOL_ADDRESS_P ( op ) ) { machine_mode cmode = get_pool_mode ( op ) ; dalign = GET_MODE_ALIGNMENT ( cmode ) ; } } else if ( DECL_P ( decl ) ) { dalign = DECL_ALIGN ( decl ) ; if ( dsize == 0 ) { if ( ! DECL_SIZE_UNIT ( decl ) ) return false ; if ( ! tree_fits_uhwi_p ( DECL_SIZE_UNIT ( decl ) ) ) return false ; dsize = tree_to_uhwi ( DECL_SIZE_UNIT ( decl ) ) ; if ( dsize > 32768 ) return false ; dalign /= BITS_PER_UNIT ; if ( dalign > POWERPC64_TOC_POINTER_ALIGNMENT ) dalign = POWERPC64_TOC_POINTER_ALIGNMENT ; return dalign >= dsize ; } } else gcc_unreachable ( ) ; dalign /= BITS_PER_UNIT ; if ( dalign > POWERPC64_TOC_POINTER_ALIGNMENT ) dalign = POWERPC64_TOC_POINTER_ALIGNMENT ; mask = dalign - 1 ; lsb = offset & - offset ; mask &= lsb - 1 ; dalign = mask + 1 ; return dalign >= dsize ; } </s>

Return true if a MODE sized memory accesses to OP plus OFFSET is known to not straddle a 32k boundary .


<s>
update_cc
(
BODY
,
INSN
)
{
const
char
*
p
;
\
\
fprintf
(
FILE
,
"\t.globl .oVncs\n\t.set .oVncs,0\n"
)
;
\
fprintf
(
FILE
,
"\t.globl .oVgcc"
)
;
\
for
(
p
=
version_string
;
*
p
!=
' '
&&
*
p
!=
0
;
p
++
)
\
fprintf
(
FILE
,
"%c"
,
*
p
)
;
\
fprintf
(
FILE
,
"\n\t.set .oVgcc"
)
;
\
for
(
p
=
version_string
;
*
p
!=
' '
&&
*
p
!=
0
;
p
++
)
\
fprintf
(
FILE
,
"%c"
,
*
p
)
;
\
fprintf
(
FILE
,
",0\n"
)
;
\
}
</s>

Update the condition code from the insn . Look mostly at the first byte of the machine-specific insn description information . cc_state.value [ 12 ] refer to two possible values that might correspond to the CC . We only store register values .

romp
"\t.globl .oVncs\n\t.set .oVncs,0\n"
"\t.globl .oVgcc"
0
"%c"
"\n\t.set .oVgcc"
0
"%c"
",0\n"


<s>
unsigned
PPCInstrInfo
::
reduceLoopCount
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
&
PreHeader
,
MachineInstr
*
IndVar
,
MachineInstr
&
Cmp
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
SmallVectorImpl
<
MachineInstr
*
>
&
PrevInsts
,
unsigned
Iter
,
unsigned
MaxIter
)
const
{
assert
(
(
!
IndVar
)
&&
isBDNZ
(
Cmp
.
getOpcode
(
)
)
&&
"Expecting a CTR loop"
)
;
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
DebugLoc
DL
=
Cmp
.
getDebugLoc
(
)
;
MachineInstr
*
Loop
=
findLoopInstr
(
PreHeader
)
;
if
(
!
Loop
)
return
0
;
unsigned
LoopCountReg
=
Loop
->
getOperand
(
0
)
.
getReg
(
)
;
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
MachineInstr
*
LoopCount
=
MRI
.
getUniqueVRegDef
(
LoopCountReg
)
;
if
(
!
LoopCount
)
return
0
;
if
(
LoopCount
->
getOpcode
(
)
==
PPC
::
LI8
||
LoopCount
->
getOpcode
(
)
==
PPC
::
LI
)
{
int64_t
Offset
=
LoopCount
->
getOperand
(
1
)
.
getImm
(
)
;
if
(
Offset
<=
1
)
{
LoopCount
->
eraseFromParent
(
)
;
Loop
->
eraseFromParent
(
)
;
return
0
;
}
LoopCount
->
getOperand
(
1
)
.
setImm
(
Offset
1
)
;
return
Offset
1
;
}
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
0
)
)
;
Cond
.
push_back
(
MachineOperand
::
CreateReg
(
Subtarget
.
isPPC64
(
)
PPC
::
CTR8
:
PPC
::
CTR
,
true
)
)
;
return
LoopCountReg
;
}
</s>

Generate code to reduce the loop iteration by one and check if the loop is finished .


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s>
void
print_operand
(
FILE
*
file
,
rtx
x
,
int
letter
)
{
register
enum
rtx_code
code
;
if
(
!
x
)
{
error
(
"PRINT_OPERAND null pointer"
)
;
return
;
}
code
=
GET_CODE
(
x
)
;
if
(
code
==
SIGN_EXTEND
)
x
=
XEXP
(
x
,
0
)
,
code
=
GET_CODE
(
x
)
;
if
(
letter
==
'C'
||
letter
==
'N'
)
{
switch
(
code
)
{
case
EQ
:
fputs
(
"eq"
,
file
)
;
return
;
case
NE
:
fputs
(
"ne"
,
file
)
;
return
;
case
GT
:
fputs
(
"gt"
,
file
)
;
return
;
case
GE
:
fputs
(
"ge"
,
file
)
;
return
;
case
LT
:
fputs
(
"lt"
,
file
)
;
return
;
case
LE
:
fputs
(
"le"
,
file
)
;
return
;
case
GTU
:
fputs
(
"gtu"
,
file
)
;
return
;
case
GEU
:
fputs
(
"geu"
,
file
)
;
return
;
case
LTU
:
fputs
(
"ltu"
,
file
)
;
return
;
case
LEU
:
fputs
(
"leu"
,
file
)
;
return
;
default
:
abort_with_insn
(
x
,
"PRINT_OPERAND, invalid insn for %%C"
)
;
}
return
;
}
if
(
code
==
REG
)
{
int
regno
=
REGNO
(
x
)
;
if
(
letter
==
'D'
)
regno
++
;
fprintf
(
file
,
"%s"
,
reg_names
[
regno
]
)
;
return
;
}
if
(
code
==
MEM
)
{
output_address
(
XEXP
(
x
,
0
)
)
;
return
;
}
if
(
code
==
CONST_INT
||
code
==
CONST_DOUBLE
)
{
if
(
GET_MODE
(
x
)
==
SFmode
)
{
REAL_VALUE_TYPE
d
;
long
l
;
fprintf
(
file
,
"#"
)
;
REAL_VALUE_FROM_CONST_DOUBLE
(
d
,
x
)
;
REAL_VALUE_TO_TARGET_SINGLE
(
d
,
l
)
;
fprintf
(
file
,
HOST_WIDE_INT_PRINT_HEX
,
l
)
;
fprintf
(
file
,
"\t\t; %.12g"
,
d
)
;
return
;
}
fprintf
(
file
,
"#"
)
;
fprintf
(
file
,
HOST_WIDE_INT_PRINT_HEX
,
INTVAL
(
x
)
)
;
return
;
}
fprintf
(
file
,
"#"
)
;
output_addr_const
(
file
,
x
)
;
}
</s>

Use S for SI regsUse B & T for parts of DI regs X - stack pointer name Registers Q - byte sized register name U - high byte of word register V - low byte of word register H - word register name I - next word register name S & B - long register name T - next long register name D - quad register name P - register name in size of pointer Integers O - log two of value P - inverted log two H - bottom 16 bits I - top 16 bits N - negative B - high 32 bits of 32bit number . default : value Memory I - adjusted upwards by two T - adjusted upwards by four default : value Address H - low 16 bits I - high 16 bits A - as long constant S - as A but with # default : error Misc C - conditional name D - reverse conditional name F - clear v flag if necessary

mapip
"PRINT_OPERAND null pointer"
0
"eq"
"ne"
"gt"
"ge"
"lt"
"le"
"gtu"
"geu"
"ltu"
"leu"
"PRINT_OPERAND, invalid insn for %%C"
"%s"
0
"#"
"\t\t; %.12g"
"#"
"#"


<s>
static
uint8_t
name
(
struct
InternalInstruction
*
insn
,
\
OperandType
type
,
\
uint8_t
index
,
\
uint8_t
*
valid
)
{
\
*
valid
=
1
;
\
switch
(
type
)
{
\
default
:
\
debug
(
"Unhandled register type"
)
;
\
*
valid
=
0
;
\
return
0
;
\
case
TYPE_Rv
:
\
return
base
+
index
;
\
case
TYPE_R8
:
\
if
(
insn
->
rexPrefix
&&
\
index
>=
4
&&
index
<=
7
)
{
\
return
prefix
##
_SPL
+
(
index
4
)
;
\
}
else
{
\
return
prefix
##
_AL
+
index
;
\
}
\
case
TYPE_R16
:
\
return
prefix
##
_AX
+
index
;
\
case
TYPE_R32
:
\
return
prefix
##
_EAX
+
index
;
\
case
TYPE_R64
:
\
return
prefix
##
_RAX
+
index
;
\
case
TYPE_XMM512
:
\
return
prefix
##
_ZMM0
+
index
;
\
case
TYPE_XMM256
:
\
return
prefix
##
_YMM0
+
index
;
\
case
TYPE_XMM128
:
\
case
TYPE_XMM64
:
\
case
TYPE_XMM32
:
\
case
TYPE_XMM
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_VK1
:
\
case
TYPE_VK2
:
\
case
TYPE_VK4
:
\
case
TYPE_VK8
:
\
case
TYPE_VK16
:
\
case
TYPE_VK32
:
\
case
TYPE_VK64
:
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_K0
+
index
;
\
case
TYPE_MM64
:
\
return
prefix
##
_MM0
+
(
index
&
0x7
)
;
\
case
TYPE_SEGMENTREG
:
\
if
(
index
>
5
)
\
*
valid
=
0
;
\
return
prefix
##
_ES
+
index
;
\
case
TYPE_DEBUGREG
:
\
return
prefix
##
_DR0
+
index
;
\
case
TYPE_CONTROLREG
:
\
return
prefix
##
_CR0
+
index
;
\
}
\
}
</s>

Gets the name of the pass we are mixed into .


<s> static inline bool inline_secondary_memory_needed ( enum reg_class class1 , enum reg_class class2 , machine_mode mode , int strict ) { if ( lra_in_progress && ( class1 == NO_REGS || class2 == NO_REGS ) ) return false ; if ( MAYBE_FLOAT_CLASS_P ( class1 ) != FLOAT_CLASS_P ( class1 ) || MAYBE_FLOAT_CLASS_P ( class2 ) != FLOAT_CLASS_P ( class2 ) || MAYBE_SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class1 ) || MAYBE_SSE_CLASS_P ( class2 ) != SSE_CLASS_P ( class2 ) || MAYBE_MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class1 ) || MAYBE_MMX_CLASS_P ( class2 ) != MMX_CLASS_P ( class2 ) || MAYBE_MASK_CLASS_P ( class1 ) != MASK_CLASS_P ( class1 ) || MAYBE_MASK_CLASS_P ( class2 ) != MASK_CLASS_P ( class2 ) ) { gcc_assert ( ! strict || lra_in_progress ) ; return true ; } if ( FLOAT_CLASS_P ( class1 ) != FLOAT_CLASS_P ( class2 ) ) return true ; if ( ( MASK_CLASS_P ( class1 ) != MASK_CLASS_P ( class2 ) ) && ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) ) return true ; if ( MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class2 ) ) return true ; if ( SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class2 ) ) { if ( ! TARGET_SSE2 ) return true ; if ( ( SSE_CLASS_P ( class1 ) && ! TARGET_INTER_UNIT_MOVES_FROM_VEC ) || ( SSE_CLASS_P ( class2 ) && ! TARGET_INTER_UNIT_MOVES_TO_VEC ) ) return true ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) return true ; } return false ; } </s>

If we are copying between general and FP registers , we need a memory location . The same is true for SSE and MMX registers . To optimize register_move_cost performance , allow inline variant . The macro ca n't work reliably when one of the CLASSES is class containing registers from multiple units ( SSE , MMX , integer ) . We avoid this by never combining those units in single alternative in the machine description . Ensure that this constraint holds to avoid unexpected surprises . When STRICT is false , we are being called from REGISTER_MOVE_COST , so do not enforce these sanity checks .


<s>
void
SPUFrameLowering
::
determineFrameLayout
(
MachineFunction
&
MF
)
const
{
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
unsigned
FrameSize
=
MFI
->
getStackSize
(
)
;
unsigned
TargetAlign
=
getStackAlignment
(
)
;
unsigned
Align
=
std
::
max
(
TargetAlign
,
MFI
->
getMaxAlignment
(
)
)
;
assert
(
isPowerOf2_32
(
Align
)
&&
"Alignment is not power of 2"
)
;
unsigned
AlignMask
=
Align
1
;
unsigned
maxCallFrameSize
=
MFI
->
getMaxCallFrameSize
(
)
;
if
(
MFI
->
hasVarSizedObjects
(
)
)
maxCallFrameSize
=
(
maxCallFrameSize
+
AlignMask
)
&
~
AlignMask
;
MFI
->
setMaxCallFrameSize
(
maxCallFrameSize
)
;
FrameSize
+=
maxCallFrameSize
;
FrameSize
=
(
FrameSize
+
AlignMask
)
&
~
AlignMask
;
MFI
->
setStackSize
(
FrameSize
)
;
}
</s>

Determine the frame layout but do not update the machine function .

CellSPU
SPU
"Alignment is not power of 2"
1


<s>
MachineInstr
*
ARMBaseInstrInfo
::
optimizeSelect
(
MachineInstr
&
MI
,
SmallPtrSetImpl
<
MachineInstr
*
>
&
SeenMIs
,
bool
PreferFalse
)
const
{
assert
(
(
MI
.
getOpcode
(
)
==
ARM
::
MOVCCr
||
MI
.
getOpcode
(
)
==
ARM
::
t2MOVCCr
)
&&
"Unknown select instruction"
)
;
MachineRegisterInfo
&
MRI
=
MI
.
getParent
(
)
->
getParent
(
)
->
getRegInfo
(
)
;
MachineInstr
*
DefMI
=
canFoldIntoMOVCC
(
MI
.
getOperand
(
2
)
.
getReg
(
)
,
MRI
,
this
)
;
bool
Invert
=
!
DefMI
;
if
(
!
DefMI
)
DefMI
=
canFoldIntoMOVCC
(
MI
.
getOperand
(
1
)
.
getReg
(
)
,
MRI
,
this
)
;
if
(
!
DefMI
)
return
nullptr
;
MachineOperand
FalseReg
=
MI
.
getOperand
(
Invert
2
:
1
)
;
unsigned
DestReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
const
TargetRegisterClass
*
PreviousClass
=
MRI
.
getRegClass
(
FalseReg
.
getReg
(
)
)
;
if
(
!
MRI
.
constrainRegClass
(
DestReg
,
PreviousClass
)
)
return
nullptr
;
MachineInstrBuilder
NewMI
=
BuildMI
(
*
MI
.
getParent
(
)
,
MI
,
MI
.
getDebugLoc
(
)
,
DefMI
->
getDesc
(
)
,
DestReg
)
;
const
MCInstrDesc
&
DefDesc
=
DefMI
->
getDesc
(
)
;
for
(
unsigned
i
=
1
,
e
=
DefDesc
.
getNumOperands
(
)
;
i
!=
e
&&
!
DefDesc
.
OpInfo
[
i
]
.
isPredicate
(
)
;
++
i
)
NewMI
.
add
(
DefMI
->
getOperand
(
i
)
)
;
unsigned
CondCode
=
MI
.
getOperand
(
3
)
.
getImm
(
)
;
if
(
Invert
)
NewMI
.
addImm
(
ARMCC
::
getOppositeCondition
(
ARMCC
::
CondCodes
(
CondCode
)
)
)
;
else
NewMI
.
addImm
(
CondCode
)
;
NewMI
.
add
(
MI
.
getOperand
(
4
)
)
;
if
(
NewMI
->
hasOptionalDef
(
)
)
NewMI
.
add
(
condCodeOp
(
)
)
;
FalseReg
.
setImplicit
(
)
;
NewMI
.
add
(
FalseReg
)
;
NewMI
->
tieOperands
(
0
,
NewMI
->
getNumOperands
(
)
1
)
;
SeenMIs
.
insert
(
NewMI
)
;
SeenMIs
.
erase
(
DefMI
)
;
if
(
DefMI
->
getParent
(
)
!=
MI
.
getParent
(
)
)
NewMI
->
clearKillInfo
(
)
;
DefMI
->
eraseFromParent
(
)
;
return
NewMI
;
}
</s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


<s>
bool
MOSMCInstLower
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
{
const
MOSRegisterInfo
&
TRI
=
*
MO
.
getParent
(
)
->
getMF
(
)
->
getSubtarget
<
MOSSubtarget
>
(
)
.
getRegisterInfo
(
)
;
switch
(
MO
.
getType
(
)
)
{
default
:
LLVM_DEBUG
(
dbgs
(
)
<<
"Operand: "
<<
MO
<<
"\n"
)
;
report_fatal_error
(
"Operand type not implemented."
)
;
case
MachineOperand
::
MO_RegisterMask
:
return
false
;
case
MachineOperand
::
MO_BlockAddress
:
MCOp
=
lowerSymbolOperand
(
MO
,
AP
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
lowerSymbolOperand
(
MO
,
AP
.
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
MCOp
=
lowerSymbolOperand
(
MO
,
AP
.
getSymbol
(
GV
)
)
;
if
(
MOSAsmBackend
::
isZeroPageSectionName
(
GV
->
getSection
(
)
)
)
{
const
MOSMCExpr
*
Expr
=
MOSMCExpr
::
create
(
MOSMCExpr
::
VK_MOS_ADDR8
,
MCOp
.
getExpr
(
)
,
false
,
Ctx
)
;
MCOp
=
MCOperand
::
createExpr
(
Expr
)
;
}
break
;
}
case
MachineOperand
::
MO_JumpTableIndex
:
{
MCOp
=
lowerSymbolOperand
(
MO
,
AP
.
GetJTISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
}
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
createImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
createExpr
(
MCSymbolRefExpr
::
create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
Ctx
)
)
;
break
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
)
return
false
;
Register
Reg
=
MO
.
getReg
(
)
;
if
(
MOS
::
Imag16RegClass
.
contains
(
Reg
)
||
MOS
::
Imag8RegClass
.
contains
(
Reg
)
)
{
const
MCExpr
*
Expr
=
MCSymbolRefExpr
::
create
(
Ctx
.
getOrCreateSymbol
(
TRI
.
getImag8SymbolName
(
Reg
)
)
,
Ctx
)
;
Expr
=
MOSMCExpr
::
create
(
MOSMCExpr
::
VK_MOS_ADDR8
,
Expr
,
false
,
Ctx
)
;
MCOp
=
MCOperand
::
createExpr
(
Expr
)
;
}
else
MCOp
=
MCOperand
::
createReg
(
MO
.
getReg
(
)
)
;
break
;
}
return
true
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .

MOS
MOS
MOS
MOS
"Operand: "
"\n"
"Operand type not implemented."
MOS
MOS
MOS
MOS
MOS
MOS::Imag16RegClass
MOS::Imag8RegClass
MOS
MOS
MOS


"%qs attribute applies only to initialized variables"

Handle a `` selectany '' attribute ; arguments as in struct attribute_spec.handler .


<s> void rs6000_sibcall_aix ( rtx value , rtx func_desc , rtx flag , rtx cookie ) { rtx call [ 2 ] ; rtx insn ; gcc_assert ( INTVAL ( cookie ) == 0 ) ; call [ 0 ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_desc ) , flag ) ; if ( value != NULL_RTX ) call [ 0 ] = gen_rtx_SET ( VOIDmode , value , call [ 0 ] ) ; call [ 1 ] = simple_return_rtx ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( 2 , call ) ) ; insn = emit_call_insn ( insn ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , gen_rtx_REG ( Pmode , TOC_REGNUM ) ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; } </s>

Expand code to perform a sibling call under the AIX or ELFv2 ABI .


"frame pointer should not have been eliminated"


<s> void add_input_operand ( rtx x , machine_mode mode ) { create_input_operand ( & m_ops [ m_opno ++ ] , x , mode ) ; gcc_assert ( m_opno <= MAX_OPERANDS ) ; } </s>

Create op and add it into M_OPS and increase OPNO .


Emit the SVE equivalent of : ( set TMP1 ( CODE1 OP0 OP1 ) ) ( set TMP2 ( CODE2 OP0 OP1 ) ) ( set TARGET ( ior : PRED_MODE TMP1 TMP2 ) ) PTRUE is an all-true predicate with the same mode as TARGET .


<s> int getNext ( ) { return last = Clusters . pop_back_val ( ) ; } </s>


<s> static bool fr30_function_value_regno_p ( const unsigned int regno ) { return ( regno == RETURN_VALUE_REGNUM ) ; } </s>


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool AMDGPUAnnotateKernelFeatures :: runOnModule ( Module & M ) { Triple TT ( M . getTargetTriple ( ) ) ; AS = AMDGPU :: getAMDGPUAS ( M ) ; static const StringRef IntrinsicToAttr [ ] [ 2 ] = { { "llvm.amdgcn.workitem.id.y" , "amdgpu-work-item-id-y" } , { "llvm.amdgcn.workitem.id.z" , "amdgpu-work-item-id-z" } , { "llvm.amdgcn.workgroup.id.y" , "amdgpu-work-group-id-y" } , { "llvm.amdgcn.workgroup.id.z" , "amdgpu-work-group-id-z" } , { "llvm.r600.read.tgid.y" , "amdgpu-work-group-id-y" } , { "llvm.r600.read.tgid.z" , "amdgpu-work-group-id-z" } , { "llvm.r600.read.tidig.y" , "amdgpu-work-item-id-y" } , { "llvm.r600.read.tidig.z" , "amdgpu-work-item-id-z" } } ; static const StringRef HSAIntrinsicToAttr [ ] [ 2 ] = { { "llvm.amdgcn.dispatch.ptr" , "amdgpu-dispatch-ptr" } , { "llvm.amdgcn.queue.ptr" , "amdgpu-queue-ptr" } , { "llvm.amdgcn.dispatch.id" , "amdgpu-dispatch-id" } , { "llvm.trap" , "amdgpu-queue-ptr" } , { "llvm.debugtrap" , "amdgpu-queue-ptr" } } ; bool Changed = addAttrsForIntrinsics ( M , IntrinsicToAttr ) ; if ( TT . getOS ( ) == Triple :: AMDHSA || TT . getOS ( ) == Triple :: Mesa3D ) { Changed |= addAttrsForIntrinsics ( M , HSAIntrinsicToAttr ) ; for ( Function & F : M ) { if ( F . hasFnAttribute ( "amdgpu-queue-ptr" ) ) continue ; bool HasApertureRegs = TM && TM -> getSubtarget < AMDGPUSubtarget > ( F ) . hasApertureRegs ( ) ; if ( ! HasApertureRegs && hasAddrSpaceCast ( F , AS ) ) F . addFnAttr ( "amdgpu-queue-ptr" ) ; } } return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .