<s> static inline tree def_builtin2 ( HOST_WIDE_INT mask , const char * name , enum ix86_builtin_func_type tcode , enum ix86_builtins code ) { tree decl = NULL_TREE ; ix86_builtins_isa [ ( int ) code ] . isa2 = mask ; if ( mask == 0 || ( mask & ix86_isa_flags2 ) != 0 || ( lang_hooks . builtin_function == lang_hooks . builtin_function_ext_scope ) ) { tree type = ix86_get_builtin_func_type ( tcode ) ; decl = add_builtin_function ( name , type , code , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ ( int ) code ] = decl ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = false ; } else { deferred_isa_values2 |= mask ; ix86_builtins [ ( int ) code ] = NULL_TREE ; ix86_builtins_isa [ ( int ) code ] . tcode = tcode ; ix86_builtins_isa [ ( int ) code ] . name = name ; ix86_builtins_isa [ ( int ) code ] . leaf_p = false ; ix86_builtins_isa [ ( int ) code ] . nothrow_p = false ; ix86_builtins_isa [ ( int ) code ] . const_p = false ; ix86_builtins_isa [ ( int ) code ] . pure_p = false ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = true ; } return decl ; } </s>

Like def_builtin , but for additional isa2 flags .


<s> rtx rs6000_libcall_value ( enum machine_mode mode ) { unsigned int regno ; if ( TARGET_32BIT && TARGET_POWERPC64 && mode == DImode ) { return gen_rtx_PARALLEL ( DImode , gen_rtvec ( 2 , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , GP_ARG_RETURN ) , const0_rtx ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , GP_ARG_RETURN + 1 ) , GEN_INT ( 4 ) ) ) ) ; } if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = FP_ARG_RETURN ; else if ( ALTIVEC_VECTOR_MODE ( mode ) && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI ) regno = ALTIVEC_ARG_RETURN ; else if ( COMPLEX_MODE_P ( mode ) && targetm . calls . split_complex_arg ) return rs6000_complex_function_value ( mode ) ; else if ( TARGET_E500_DOUBLE && TARGET_HARD_FLOAT && ( mode == DFmode || mode == DCmode ) ) return spe_build_register_parallel ( mode , GP_ARG_RETURN ) ; else regno = GP_ARG_RETURN ; return gen_rtx_REG ( mode , regno ) ; } </s>

Define how to find the value returned by a library function assuming the value has mode MODE .


<s> int arm_coproc_mem_operand ( rtx op , bool wb ) { rtx ind ; if ( ! ( reload_in_progress || reload_completed ) && ( reg_mentioned_p ( frame_pointer_rtx , op ) || reg_mentioned_p ( arg_pointer_rtx , op ) || reg_mentioned_p ( virtual_incoming_args_rtx , op ) || reg_mentioned_p ( virtual_outgoing_args_rtx , op ) || reg_mentioned_p ( virtual_stack_dynamic_rtx , op ) || reg_mentioned_p ( virtual_stack_vars_rtx , op ) ) ) return FALSE ; if ( GET_CODE ( op ) != MEM ) return FALSE ; ind = XEXP ( op , 0 ) ; if ( reload_completed && ( GET_CODE ( ind ) == LABEL_REF || ( GET_CODE ( ind ) == CONST && GET_CODE ( XEXP ( ind , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( ind , 0 ) , 0 ) ) == LABEL_REF && GET_CODE ( XEXP ( XEXP ( ind , 0 ) , 1 ) ) == CONST_INT ) ) ) return TRUE ; if ( GET_CODE ( ind ) == REG ) return arm_address_register_rtx_p ( ind , 0 ) ; if ( wb && ( GET_CODE ( ind ) == PRE_INC || GET_CODE ( ind ) == POST_INC || GET_CODE ( ind ) == PRE_DEC || GET_CODE ( ind ) == POST_DEC ) ) return arm_address_register_rtx_p ( XEXP ( ind , 0 ) , 0 ) ; if ( wb && ( GET_CODE ( ind ) == POST_MODIFY || GET_CODE ( ind ) == PRE_MODIFY ) && arm_address_register_rtx_p ( XEXP ( ind , 0 ) , 0 ) && GET_CODE ( XEXP ( ind , 1 ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( ind , 1 ) , 0 ) , XEXP ( ind , 0 ) ) ) ind = XEXP ( ind , 1 ) ; if ( GET_CODE ( ind ) == PLUS && GET_CODE ( XEXP ( ind , 0 ) ) == REG && REG_MODE_OK_FOR_BASE_P ( XEXP ( ind , 0 ) , VOIDmode ) && GET_CODE ( XEXP ( ind , 1 ) ) == CONST_INT && INTVAL ( XEXP ( ind , 1 ) ) > - 1024 && INTVAL ( XEXP ( ind , 1 ) ) < 1024 && ( INTVAL ( XEXP ( ind , 1 ) ) & 3 ) == 0 ) return TRUE ; return FALSE ; } </s>

Return TRUE if OP is a valid coprocessor memory address pattern . WB if true if writeback address modes are allowed .


<s> bool riscv_epilogue_uses ( unsigned int regno ) { if ( regno == RETURN_ADDR_REGNUM ) return true ; if ( epilogue_completed && cfun -> machine -> interrupt_handler_p ) { if ( df_regs_ever_live_p ( regno ) || ( ! crtl -> is_leaf && call_used_regs [ regno ] ) ) return true ; } return false ; } </s>


"More vector elements requested than available!"

Split a vector value into two parts of types LoVT and HiVT .


<s> std :: pair < unsigned , const TargetRegisterClass * > DCPU16TargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'r' : return std :: make_pair ( 0U , & DCPU16 :: GR16RegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> virtual bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , const BranchProbability & Probability ) const { return true ; } </s>

Return true if it 's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion .


<s> void ARMBaseInstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , unsigned SubIdx , const MachineInstr * Orig , const TargetRegisterInfo & TRI ) const { unsigned Opcode = Orig -> getOpcode ( ) ; switch ( Opcode ) { default : { MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( Orig ) ; MI -> substituteRegister ( Orig -> getOperand ( 0 ) . getReg ( ) , DestReg , SubIdx , TRI ) ; MBB . insert ( I , MI ) ; break ; } case ARM :: tLDRpci_pic : case ARM :: t2LDRpci_pic : { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CPI = Orig -> getOperand ( 1 ) . getIndex ( ) ; unsigned PCLabelId = duplicateCPV ( MF , CPI ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , Orig -> getDebugLoc ( ) , get ( Opcode ) , DestReg ) . addConstantPoolIndex ( CPI ) . addImm ( PCLabelId ) ; MIB -> setMemRefs ( Orig -> memoperands_begin ( ) , Orig -> memoperands_end ( ) ) ; break ; } } } </s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s>
static
void
som_output_text_section_asm_op
(
const
char
*
data
ATTRIBUTE_UNUSED
)
{
gcc_assert
(
TARGET_SOM
)
;
if
(
TARGET_GAS
)
{
if
(
cfun
&&
cfun
->
machine
&&
!
cfun
->
machine
->
in_nsubspa
)
{
cfun
->
machine
->
in_nsubspa
=
1
;
if
(
cfun
->
decl
&&
DECL_ONE_ONLY
(
cfun
->
decl
)
&&
!
DECL_WEAK
(
cfun
->
decl
)
)
{
output_section_asm_op
(
"\t.SPACE $TEXT$\n"
"\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8,"
"ACCESS=44,SORT=24,COMDAT"
)
;
return
;
}
}
else
{
gcc_assert
(
!
cfun
||
!
cfun
->
machine
||
cfun
->
machine
->
in_nsubspa
==
2
)
;
in_section
=
;
}
output_section_asm_op
(
"\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$"
)
;
return
;
}
output_section_asm_op
(
"\t.SPACE $TEXT$\n\t.SUBSPA $CODE$"
)
;
}
</s>

A get_unnamed_section callback for switching to the text section . This function is only used with SOM . Because we do n't support named subspaces , we can only create a new subspace or switch back to the default text subspace .


<s>
void
dump
(
)
{
errs
(
)
<<
"MSP430ISelAddressMode "
<<
this
<<
'\n'
;
if
(
BaseType
==
RegBase
&&
Base
.
Reg
.
getNode
(
)
!=
nullptr
)
{
errs
(
)
<<
"Base.Reg "
;
Base
.
Reg
.
getNode
(
)
->
dump
(
)
;
}
else
if
(
BaseType
==
FrameIndexBase
)
{
errs
(
)
<<
" Base.FrameIndex "
<<
Base
.
FrameIndex
<<
'\n'
;
}
errs
(
)
<<
" Disp "
<<
Disp
<<
'\n'
;
if
(
GV
)
{
errs
(
)
<<
"GV "
;
GV
->
dump
(
)
;
}
else
if
(
CP
)
{
errs
(
)
<<
" CP "
;
CP
->
dump
(
)
;
errs
(
)
<<
" Align"
<<
Align
<<
'\n'
;
}
else
if
(
ES
)
{
errs
(
)
<<
"ES "
;
errs
(
)
<<
ES
<<
'\n'
;
}
else
if
(
JT
!=
1
)
errs
(
)
<<
" JT"
<<
JT
<<
" Align"
<<
Align
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

MSP430
"MSP430ISelAddressMode "
"Base.Reg "
" Base.FrameIndex "
" Disp "
"GV "
" CP "
" Align"
"ES "
1
" JT"
" Align"


<s> virtual MachineInstr * foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const { return 0 ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> bool get_ta ( ) const { return m_ta ; } </s>

Get ta according to operand [ tail_op_idx ] .


<s>
SDValue
BlackfinTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
SmallVector
<
CCValAssign
,
16
>
ArgLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
ArgLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AllocateStack
(
12
,
4
)
;
CCInfo
.
AnalyzeFormalArguments
(
Ins
,
CC_Blackfin
)
;
for
(
unsigned
i
=
0
,
e
=
ArgLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
ArgLocs
[
i
]
;
if
(
VA
.
isRegLoc
(
)
)
{
EVT
RegVT
=
VA
.
getLocVT
(
)
;
TargetRegisterClass
*
RC
=
VA
.
getLocReg
(
)
==
BF
::
P0
BF
::
PRegisterClass
:
BF
::
DRegisterClass
;
assert
(
RC
->
contains
(
VA
.
getLocReg
(
)
)
&&
"Unexpected regclass in CCState"
)
;
assert
(
RC
->
hasType
(
RegVT
)
&&
"Unexpected regclass in CCState"
)
;
unsigned
Reg
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
RC
)
;
MF
.
getRegInfo
(
)
.
addLiveIn
(
VA
.
getLocReg
(
)
,
Reg
)
;
SDValue
ArgValue
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
Reg
,
RegVT
)
;
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
SExt
)
ArgValue
=
DAG
.
getNode
(
ISD
::
AssertSext
,
dl
,
RegVT
,
ArgValue
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
else
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExt
)
ArgValue
=
DAG
.
getNode
(
ISD
::
AssertZext
,
dl
,
RegVT
,
ArgValue
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
if
(
VA
.
getLocInfo
(
)
!=
CCValAssign
::
Full
)
ArgValue
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
ArgValue
)
;
InVals
.
push_back
(
ArgValue
)
;
}
else
{
assert
(
VA
.
isMemLoc
(
)
&&
"CCValAssign must be RegLoc or MemLoc"
)
;
unsigned
ObjSize
=
VA
.
getLocVT
(
)
.
getStoreSize
(
)
;
int
FI
=
MFI
->
CreateFixedObject
(
ObjSize
,
VA
.
getLocMemOffset
(
)
,
true
)
;
SDValue
FIN
=
DAG
.
getFrameIndex
(
FI
,
MVT
::
i32
)
;
InVals
.
push_back
(
DAG
.
getLoad
(
VA
.
getValVT
(
)
,
dl
,
Chain
,
FIN
,
,
0
,
false
,
false
,
0
)
)
;
}
}
return
Chain
;
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> unsigned PPCFrameLowering :: getFramePointerSaveOffset ( ) const { return FramePointerSaveOffset ; } </s>

getFramePointerSaveOffset - Return the previous frame offset to save the frame pointer .


<s> static bool s390_call_saved_register_used ( tree argument_list ) { CUMULATIVE_ARGS cum ; tree parameter ; enum machine_mode mode ; tree type ; rtx parm_rtx ; int reg ; INIT_CUMULATIVE_ARGS ( cum , NULL , NULL , 0 , 0 ) ; while ( argument_list ) { parameter = TREE_VALUE ( argument_list ) ; argument_list = TREE_CHAIN ( argument_list ) ; gcc_assert ( parameter ) ; if ( TREE_CODE ( parameter ) == ERROR_MARK ) return true ; type = TREE_TYPE ( parameter ) ; gcc_assert ( type ) ; mode = TYPE_MODE ( type ) ; gcc_assert ( mode ) ; if ( pass_by_reference ( & cum , mode , type , true ) ) { mode = Pmode ; type = build_pointer_type ( type ) ; } parm_rtx = s390_function_arg ( & cum , mode , type , 0 ) ; s390_function_arg_advance ( & cum , mode , type , 0 ) ; if ( parm_rtx && REG_P ( parm_rtx ) ) { for ( reg = 0 ; reg < HARD_REGNO_NREGS ( REGNO ( parm_rtx ) , GET_MODE ( parm_rtx ) ) ; reg ++ ) if ( ! call_used_regs [ reg + REGNO ( parm_rtx ) ] ) return true ; } } return false ; } </s>

Checks whether the given ARGUMENT_LIST would use a caller saved register . This is used to decide whether sibling call optimization could be performed on the respective function call .


<s> static bool aarch64_legitimate_constant_p ( machine_mode mode , rtx x ) { if ( CONST_INT_P ( x ) || ( CONST_DOUBLE_P ( x ) && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) ) return true ; if ( ! GET_MODE_SIZE ( mode ) . is_constant ( ) ) return aarch64_simd_valid_immediate ( x , NULL ) ; if ( GET_CODE ( x ) == CONST_VECTOR ) return ! targetm . cannot_force_const_mem ( mode , x ) ; unsigned int vec_flags = aarch64_classify_vector_mode ( mode ) ; if ( vec_flags == ( VEC_ADVSIMD | VEC_STRUCT ) ) return false ; if ( GET_CODE ( x ) == HIGH ) x = XEXP ( x , 0 ) ; poly_int64 offset ; if ( poly_int_rtx_p ( x , & offset ) ) return aarch64_offset_temporaries ( false , offset ) <= 1 ; x = strip_offset_and_salt ( x , & offset ) ; if ( ! offset . is_constant ( ) && aarch64_offset_temporaries ( true , offset ) > 0 ) return false ; if ( maybe_ne ( offset , 0 ) && SYMBOL_REF_P ( x ) && SYMBOL_REF_ANCHOR_P ( x ) ) return false ; if ( SYMBOL_REF_P ( x ) && ! SYMBOL_REF_TLS_MODEL ( x ) ) return true ; if ( LABEL_REF_P ( x ) ) return true ; return false ; } </s>

Implement TARGET_LEGITIMATE_CONSTANT_P hook . Return true for constants that should be rematerialized rather than spilled .


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , DebugLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { if ( ! Subtarget -> isAAPCS_ABI ( ) || Subtarget -> isTargetDarwin ( ) ) return SDValue ( ) ; const ARMTargetLowering & TLI = * static_cast < const ARMTargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Type * IntPtrTy = TLI . getTargetData ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( MVT :: i32 ) ) Src = DAG . getNode ( ISD :: TRUNCATE , dl , MVT :: i32 , Src ) ; else Src = DAG . getNode ( ISD :: ZERO_EXTEND , dl , MVT :: i32 , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , 0 , TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , false , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ; return CallResult . second ; } </s>

Emit target-specific code that performs a memset .


<s> static struct machine_function * rs6000_init_machine_status ( void ) { stack_info . reload_completed = 0 ; return ggc_cleared_alloc < machine_function > ( ) ; } </s>

Functions to init , mark and free struct machine_function . These will be called , via pointer variables , from push_function_context and pop_function_context .


<s> bool MipsLongBranch :: runOnMachineFunction ( MachineFunction & F ) { const MipsInstrInfo * TII = static_cast < const MipsInstrInfo * > ( TM . getInstrInfo ( ) ) ; if ( TM . getSubtarget < MipsSubtarget > ( ) . inMips16Mode ( ) ) return false ; if ( ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) && TM . getSubtarget < MipsSubtarget > ( ) . isABI_O32 ( ) && F . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; SmallVector < MBBInfo , 16 > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; if ( ! ForceLongBranch && isInt < 16 > ( computeOffset ( I -> Br ) / 4 ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * 4 ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { uint64_t Address = 0 ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ; } for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) if ( I -> HasLongBranch ) expandToLongBranch ( * I ) ; MF -> RenumberBlocks ( ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> int arm_coproc_mem_operand_wb ( rtx op , int wb_level ) { gcc_assert ( wb_level == 0 || wb_level == 1 || wb_level == 2 ) ; rtx ind ; if ( ! ( reload_in_progress || reload_completed || lra_in_progress ) && ( reg_mentioned_p ( frame_pointer_rtx , op ) || reg_mentioned_p ( arg_pointer_rtx , op ) || reg_mentioned_p ( virtual_incoming_args_rtx , op ) || reg_mentioned_p ( virtual_outgoing_args_rtx , op ) || reg_mentioned_p ( virtual_stack_dynamic_rtx , op ) || reg_mentioned_p ( virtual_stack_vars_rtx , op ) ) ) return FALSE ; if ( ! MEM_P ( op ) ) return FALSE ; ind = XEXP ( op , 0 ) ; if ( reload_completed && ( LABEL_REF_P ( ind ) || ( GET_CODE ( ind ) == CONST && GET_CODE ( XEXP ( ind , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( ind , 0 ) , 0 ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( ind , 0 ) , 1 ) ) ) ) ) return TRUE ; if ( REG_P ( ind ) ) return arm_address_register_rtx_p ( ind , 0 ) ; if ( wb_level > 0 && ( GET_CODE ( ind ) == POST_INC || GET_CODE ( ind ) == PRE_DEC || ( wb_level > 1 && ( GET_CODE ( ind ) == PRE_INC || GET_CODE ( ind ) == POST_DEC ) ) ) ) return arm_address_register_rtx_p ( XEXP ( ind , 0 ) , 0 ) ; if ( wb_level > 1 && ( GET_CODE ( ind ) == POST_MODIFY || GET_CODE ( ind ) == PRE_MODIFY ) && arm_address_register_rtx_p ( XEXP ( ind , 0 ) , 0 ) && GET_CODE ( XEXP ( ind , 1 ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( ind , 1 ) , 0 ) , XEXP ( ind , 0 ) ) ) ind = XEXP ( ind , 1 ) ; int factor = MIN ( GET_MODE_SIZE ( GET_MODE ( op ) ) , 4 ) ; if ( GET_CODE ( ind ) == PLUS && REG_P ( XEXP ( ind , 0 ) ) && REG_MODE_OK_FOR_BASE_P ( XEXP ( ind , 0 ) , VOIDmode ) && CONST_INT_P ( XEXP ( ind , 1 ) ) && IN_RANGE ( INTVAL ( XEXP ( ind , 1 ) ) , - 255 * factor , 255 * factor ) && ( INTVAL ( XEXP ( ind , 1 ) ) & ( factor - 1 ) ) == 0 ) return TRUE ; return FALSE ; } </s>

Return TRUE if OP is a valid coprocessor memory address pattern . WB level is 2 if full writeback address modes are allowed , 1 if limited writeback address modes ( POST_INC and PRE_DEC ) are allowed and 0 if no writeback at all is supported .


<s> Register SIRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , int FrameIdx , int64_t Offset ) const { MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const SIInstrInfo * TII = ST . getInstrInfo ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; unsigned MovOpc = ST . enableFlatScratch ( ) ? AMDGPU :: S_MOV_B32 : AMDGPU :: V_MOV_B32_e32 ; Register BaseReg = MRI . createVirtualRegister ( ST . enableFlatScratch ( ) ? & AMDGPU :: SReg_32_XEXEC_HIRegClass : & AMDGPU :: VGPR_32RegClass ) ; if ( Offset == 0 ) { BuildMI ( * MBB , Ins , DL , TII -> get ( MovOpc ) , BaseReg ) . addFrameIndex ( FrameIdx ) ; return BaseReg ; } Register OffsetReg = MRI . createVirtualRegister ( & AMDGPU :: SReg_32_XM0RegClass ) ; Register FIReg = MRI . createVirtualRegister ( ST . enableFlatScratch ( ) ? & AMDGPU :: SReg_32_XM0RegClass : & AMDGPU :: VGPR_32RegClass ) ; BuildMI ( * MBB , Ins , DL , TII -> get ( AMDGPU :: S_MOV_B32 ) , OffsetReg ) . addImm ( Offset ) ; BuildMI ( * MBB , Ins , DL , TII -> get ( MovOpc ) , FIReg ) . addFrameIndex ( FrameIdx ) ; if ( ST . enableFlatScratch ( ) ) { BuildMI ( * MBB , Ins , DL , TII -> get ( AMDGPU :: S_ADD_I32 ) , BaseReg ) . addReg ( OffsetReg , RegState :: Kill ) . addReg ( FIReg ) ; return BaseReg ; } TII -> getAddNoCarry ( * MBB , Ins , DL , BaseReg ) . addReg ( OffsetReg , RegState :: Kill ) . addReg ( FIReg ) . addImm ( 0 ) ; return BaseReg ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( CommentStream ) HasCustomInstComment = EmitAnyX86InstComments ( MI , * CommentStream , getRegisterName ) ; if ( TSFlags & X86II :: LOCK ) OS << "\tlock\n" ; if ( MI -> getOpcode ( ) == X86 :: CALLpcrel32 && ( STI . getFeatureBits ( ) & X86 :: Mode64Bit ) != 0 ) { OS << "\tcallq\t" ; printPCRelImm ( MI , 0 , OS ) ; } else if ( ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


"Expected a flag and a condition expression"

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> DecodeStatus MipsDisassembler :: getInstruction ( MCInst & instr , uint64_t & Size , const MemoryObject & Region , uint64_t Address , raw_ostream & vStream , raw_ostream & cStream ) const { uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Region , Address , Size , Insn , isBigEndian , IsMicroMips ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( IsMicroMips ) { Result = decodeInstruction ( DecoderTableMicroMips32 , instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } if ( isMips32r6 ( ) ) { Result = decodeInstruction ( DecoderTableMips32r6_64r632 , instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } } Result = decodeInstruction ( DecoderTableMips32 , instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .

Mips Mips Mips Mips Mips 4 Mips Mips 4 Mips 4


<s> static bool fits_dispatch_window ( rtx_insn * insn ) { dispatch_windows * window_list = dispatch_window_list ; dispatch_windows * window_list_next = dispatch_window_list -> next ; unsigned int num_restrict ; enum dispatch_group group = get_insn_group ( insn ) ; enum insn_path path = get_insn_path ( insn ) ; int sum ; if ( group == disp_jcc || group == disp_cmp ) return false ; if ( group == disp_no_group || group == disp_branch ) return true ; if ( window_list_next ) window_list = window_list_next ; if ( window_list -> window_num == 1 ) { sum = window_list -> prev -> window_size + window_list -> window_size ; if ( sum == 32 || ( ix86_min_insn_size ( insn ) + sum ) >= 48 ) return true ; } num_restrict = count_num_restricted ( insn , window_list ) ; if ( num_restrict > num_allowable_groups [ group ] ) return false ; if ( window_list -> window_num == 0 ) { if ( path == path_double && ( window_list -> num_uops + 2 ) > MAX_INSN ) return false ; else if ( path != path_single ) return false ; } return true ; } </s>

This function returns true if insn satisfies dispatch rules on the last window scheduled .


<s> bool ARMFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getTarget ( ) . getRegisterInfo ( ) ; if ( STI . isTargetIOS ( ) ) return true ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) && MFI -> hasCalls ( ) ) || RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
const
char
*
output_mov_long_double_arm_from_arm
(
rtx
*
operands
)
{
int
dest_start
=
REGNO
(
operands
[
0
]
)
;
int
src_start
=
REGNO
(
operands
[
1
]
)
;
rtx
ops
[
2
]
;
int
i
;
if
(
dest_start
<
src_start
)
{
for
(
i
=
0
;
i
<
3
;
i
++
)
{
ops
[
0
]
=
gen_rtx_REG
(
SImode
,
dest_start
+
i
)
;
ops
[
1
]
=
gen_rtx_REG
(
SImode
,
src_start
+
i
)
;
output_asm_insn
(
"mov%?\t%0, %1"
,
ops
)
;
}
}
else
{
for
(
i
=
2
;
i
>=
0
;
i
)
{
ops
[
0
]
=
gen_rtx_REG
(
SImode
,
dest_start
+
i
)
;
ops
[
1
]
=
gen_rtx_REG
(
SImode
,
src_start
+
i
)
;
output_asm_insn
(
"mov%?\t%0, %1"
,
ops
)
;
}
}
return
""
;
}
</s>

Output a move from arm registers to arm registers of a long double OPERANDS [ 0 ] is the destination . OPERANDS [ 1 ] is the source .


<s>
const
char
*
output_jump_label_table
(
)
{
int
i
;
if
(
pool_size
)
{
fprintf
(
asm_out_file
,
"\t.align 2\n"
)
;
for
(
i
=
0
;
i
<
pool_size
;
i
++
)
{
pool_node
*
p
=
&
pool_vector
[
i
]
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
"L"
,
CODE_LABEL_NUMBER
(
p
->
label
)
)
;
output_asm_insn
(
".long	%O0"
,
&
p
->
value
)
;
}
pool_size
=
0
;
}
return
""
;
}
</s>

Dump out any constants accumulated in the final pass . These will only be labels .


<s> bool alpha_legitimate_constant_p ( rtx x ) { enum machine_mode mode = GET_MODE ( x ) ; HOST_WIDE_INT i0 , i1 ; switch ( GET_CODE ( x ) ) { case CONST : case LABEL_REF : case SYMBOL_REF : case HIGH : return true ; case CONST_DOUBLE : if ( x == CONST0_RTX ( mode ) ) return true ; if ( FLOAT_MODE_P ( mode ) ) return false ; goto do_integer ; case CONST_VECTOR : if ( x == CONST0_RTX ( mode ) ) return true ; if ( GET_MODE_CLASS ( mode ) != MODE_VECTOR_INT ) return false ; if ( GET_MODE_SIZE ( mode ) != 8 ) return false ; goto do_integer ; case CONST_INT : do_integer : if ( TARGET_BUILD_CONSTANTS ) return true ; alpha_extract_integer ( x , & i0 , & i1 ) ; if ( HOST_BITS_PER_WIDE_INT >= 64 || i1 == ( - i0 < 0 ) ) return alpha_emit_set_const_1 ( x , mode , i0 , 3 , true ) != NULL ; return false ; default : return false ; } } </s>

Implement LEGITIMATE_CONSTANT_P . This is all constants for which we are willing to load the value into a register via a move pattern . Normally this is all symbolic constants , integral constants that take three or fewer instructions , and floating-point zero .


<s> rtx mmix_get_hard_reg_initial_val ( enum machine_mode mode , int regno ) { return get_hard_reg_initial_val ( mode , regno ) ; } </s>

Wrapper for get_hard_reg_initial_val since integrate.h is n't included from insn-emit.cc .


<s> static void block_move_sequence ( rtx dst_mem , rtx src_mem , int size , int align ) { rtx temp [ 2 ] ; machine_mode mode [ 2 ] ; int amount [ 2 ] ; bool active [ 2 ] ; int phase = 0 ; int next ; int offset_ld = 0 ; int offset_st = 0 ; rtx x ; x = XEXP ( dst_mem , 0 ) ; if ( ! REG_P ( x ) ) { x = force_reg ( Pmode , x ) ; dst_mem = replace_equiv_address ( dst_mem , x ) ; } x = XEXP ( src_mem , 0 ) ; if ( ! REG_P ( x ) ) { x = force_reg ( Pmode , x ) ; src_mem = replace_equiv_address ( src_mem , x ) ; } active [ 0 ] = active [ 1 ] = false ; do { next = phase ; phase ^= 1 ; if ( size > 0 ) { int next_amount ; next_amount = ( size >= 4 ? 4 : ( size >= 2 ? 2 : 1 ) ) ; next_amount = MIN ( next_amount , align ) ; amount [ next ] = next_amount ; mode [ next ] = mode_from_align [ next_amount ] ; temp [ next ] = gen_reg_rtx ( mode [ next ] ) ; x = adjust_address ( src_mem , mode [ next ] , offset_ld ) ; emit_insn ( gen_rtx_SET ( temp [ next ] , x ) ) ; offset_ld += next_amount ; size -= next_amount ; active [ next ] = true ; } if ( active [ phase ] ) { active [ phase ] = false ; x = adjust_address ( dst_mem , mode [ phase ] , offset_st ) ; emit_insn ( gen_rtx_SET ( x , temp [ phase ] ) ) ; offset_st += amount [ phase ] ; } } while ( active [ next ] ) ; } </s>

Emit code to perform a block move with an offset sequence of ld/st instructions ( ... , ld 0 , st 1 , ld 1 , st 0 , ... ) . SIZE and ALIGN are known constants . DEST and SRC are registers . OFFSET is the known starting point for the output pattern .


<s> static rtx ix86_erase_embedded_rounding ( rtx pat ) { if ( GET_CODE ( pat ) == INSN ) pat = PATTERN ( pat ) ; gcc_assert ( GET_CODE ( pat ) == PARALLEL ) ; if ( XVECLEN ( pat , 0 ) == 2 ) { rtx p0 = XVECEXP ( pat , 0 , 0 ) ; rtx p1 = XVECEXP ( pat , 0 , 1 ) ; gcc_assert ( GET_CODE ( p0 ) == SET && GET_CODE ( p1 ) == UNSPEC && XINT ( p1 , 1 ) == UNSPEC_EMBEDDED_ROUNDING ) ; return p0 ; } else { rtx * res = XALLOCAVEC ( rtx , XVECLEN ( pat , 0 ) ) ; int i = 0 ; int j = 0 ; for ( ; i < XVECLEN ( pat , 0 ) ; ++ i ) { rtx elem = XVECEXP ( pat , 0 , i ) ; if ( GET_CODE ( elem ) != UNSPEC || XINT ( elem , 1 ) != UNSPEC_EMBEDDED_ROUNDING ) res [ j ++ ] = elem ; } gcc_assert ( j >= XVECLEN ( pat , 0 ) - 1 ) ; return gen_rtx_PARALLEL ( GET_MODE ( pat ) , gen_rtvec_v ( j , res ) ) ; } } </s>

Transform pattern of following layout : ( parallel [ set ( A B ) ( unspec [ C ] UNSPEC_EMBEDDED_ROUNDING ) ] ) ] ) into : ( set ( A B ) ) Or : ( parallel [ A B ... ( unspec [ C ] UNSPEC_EMBEDDED_ROUNDING ) ... ] ) into : ( parallel [ A B ... ] )


<s> void MipsSEInstrInfo :: adjustStackPtr ( unsigned SP , int64_t Amount , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { MipsABIInfo ABI = Subtarget . getABI ( ) ; DebugLoc DL ; unsigned ADDiu = ABI . GetPtrAddiuOp ( ) ; if ( Amount == 0 ) return ; if ( isInt < 16 > ( Amount ) ) { BuildMI ( MBB , I , DL , get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; } else { unsigned Opc = ABI . GetPtrAdduOp ( ) ; if ( Amount < 0 ) { Opc = ABI . GetPtrSubuOp ( ) ; Amount = - Amount ; } unsigned Reg = loadImmediate ( Amount , MBB , I , DL , nullptr ) ; BuildMI ( MBB , I , DL , get ( Opc ) , SP ) . addReg ( SP ) . addReg ( Reg , RegState :: Kill ) ; } } </s>


<s> static int get_symbol_alignment ( rtx x ) { tree decl = NULL_TREE ; int align = 0 ; switch ( GET_CODE ( x ) ) { case SYMBOL_REF : decl = SYMBOL_REF_DECL ( x ) ; break ; case CONST : return get_symbol_alignment ( XEXP ( x , 0 ) ) ; case PLUS : gcc_assert ( CONST_INT_P ( XEXP ( x , 1 ) ) ) ; return get_symbol_alignment ( XEXP ( x , 0 ) ) ; default : return 0 ; } if ( decl ) align = DECL_ALIGN ( decl ) ; align = align / BITS_PER_UNIT ; return align ; } </s>

Given a symbol RTX ( const ( symb < + const_int > ) , returns its alignment .


<s> void riscv_expand_prologue ( void ) { struct riscv_frame_info * frame = & cfun -> machine -> frame ; HOST_WIDE_INT size = frame -> total_size ; unsigned mask = frame -> mask ; rtx insn ; if ( cfun -> machine -> naked_p ) { if ( flag_stack_usage_info ) current_function_static_stack_size = 0 ; return ; } if ( flag_stack_usage_info ) current_function_static_stack_size = size ; if ( riscv_use_save_libcall ( frame ) ) { rtx dwarf = NULL_RTX ; dwarf = riscv_adjust_libcall_cfi_prologue ( ) ; frame -> mask = 0 ; size -= frame -> save_libcall_adjustment ; insn = emit_insn ( gen_gpr_save ( GEN_INT ( mask ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = dwarf ; } if ( ( frame -> mask | frame -> fmask ) != 0 ) { HOST_WIDE_INT step1 = MIN ( size , riscv_first_stack_step ( frame ) ) ; insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = 1 ; size -= step1 ; riscv_for_each_saved_reg ( size , riscv_save_reg ) ; } frame -> mask = mask ; if ( frame_pointer_needed ) { insn = gen_add3_insn ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( frame -> hard_frame_pointer_offset - size ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = 1 ; riscv_emit_stack_tie ( ) ; } if ( size > 0 ) { if ( SMALL_OPERAND ( - size ) ) { insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - size ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = 1 ; } else { riscv_emit_move ( RISCV_PROLOGUE_TEMP ( Pmode ) , GEN_INT ( - size ) ) ; emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , RISCV_PROLOGUE_TEMP ( Pmode ) ) ) ; insn = plus_constant ( Pmode , stack_pointer_rtx , - size ) ; insn = gen_rtx_SET ( stack_pointer_rtx , insn ) ; riscv_set_frame_expr ( insn ) ; } } } </s>


"Did not fully process a global variable"

EmitGlobals - Emit all of the global variables to memory , storing their addresses into GlobalAddress .


<s> void FISCRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { MachineInstr & MI = * II ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ; unsigned FI = FIOp . getIndex ( ) ; unsigned ImmOpIdx = 0 ; switch ( MI . getOpcode ( ) ) { default : return ; case FISC :: ADDri : case FISC :: LDR : case FISC :: LDRB : case FISC :: LDRH : case FISC :: LDRSW : case FISC :: LDRXR : case FISC :: LDRR : case FISC :: LDRBR : case FISC :: LDRHR : case FISC :: LDRSWR : case FISC :: LDRXRR : case FISC :: STR : case FISC :: STRB : case FISC :: STRH : case FISC :: STRW : case FISC :: STRXR : case FISC :: STRR : case FISC :: STRBR : case FISC :: STRHR : case FISC :: STRWR : case FISC :: STRXRR : ImmOpIdx = FIOperandNum + 1 ; break ; } MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ; int Offset = MFI -> getObjectOffset ( FI ) + MFI -> getStackSize ( ) + ImmOp . getImm ( ) ; FIOp . ChangeToRegister ( FISC :: SP , false ) ; ImmOp . setImm ( Offset ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .

FISC FISC 0 FISC::ADDri FISC::LDR FISC::LDRB FISC::LDRH FISC::LDRSW FISC::LDRXR FISC::LDRR FISC::LDRBR FISC::LDRHR FISC::LDRSWR FISC::LDRXRR FISC::STR FISC::STRB FISC::STRH FISC::STRW FISC::STRXR FISC::STRR FISC::STRBR FISC::STRHR FISC::STRWR FISC::STRXRR 1 FISC::SP


<s> StringRef getPassName ( ) const override { return MCS51_EXPAND_PSEUDO_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s>
static
void
recombine_lvx_pattern
(
rtx_insn
*
insn
,
del_info
*
to_delete
)
{
rtx
body
=
PATTERN
(
insn
)
;
gcc_assert
(
GET_CODE
(
body
)
==
SET
&&
GET_CODE
(
SET_SRC
(
body
)
)
==
VEC_SELECT
&&
GET_CODE
(
XEXP
(
SET_SRC
(
body
)
,
0
)
)
==
MEM
)
;
rtx
mem
=
XEXP
(
SET_SRC
(
body
)
,
0
)
;
rtx
base_reg
=
XEXP
(
mem
,
0
)
;
rtx
and_operation
=
find_alignment_op
(
insn
,
base_reg
)
;
if
(
and_operation
!=
0
)
{
df_ref
def
;
struct
df_insn_info
*
insn_info
=
DF_INSN_INFO_GET
(
insn
)
;
FOR_EACH_INSN_INFO_DEF
(
def
,
insn_info
)
{
struct
df_link
*
link
=
DF_REF_CHAIN
(
def
)
;
if
(
!
link
||
link
->
next
)
break
;
rtx_insn
*
swap_insn
=
DF_REF_INSN
(
link
->
ref
)
;
if
(
!
insn_is_swap_p
(
swap_insn
)
||
insn_is_load_p
(
swap_insn
)
||
insn_is_store_p
(
swap_insn
)
)
break
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace
=
true
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace_insn
=
swap_insn
;
XEXP
(
mem
,
0
)
=
and_operation
;
SET_SRC
(
body
)
=
mem
;
INSN_CODE
(
insn
)
=
1
;
df_insn_rescan
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"lvx opportunity found at %d\n"
,
INSN_UID
(
insn
)
)
;
}
}
}
</s>

If INSN is the load for an lvx pattern , put it in canonical form .


<s> static const char * fp_const_from_val ( REAL_VALUE_TYPE * r ) { if ( ! fp_consts_inited ) init_fp_table ( ) ; gcc_assert ( real_equal ( r , & value_fp0 ) ) ; return "0" ; } </s>

As for fp_immediate_constant , but value is passed directly , not in rtx .


"Do not know how to custom type legalize this operation!"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> MCSection * AMDGPUTargetObjectFile :: getExplicitSectionGlobal ( const GlobalObject * GO , SectionKind SK , const TargetMachine & TM ) const { StringRef SectionName = GO -> getSection ( ) ; if ( SectionName . startswith ( ".AMDGPU.metadata." ) ) SK = SectionKind :: getMetadata ( ) ; return TargetLoweringObjectFileELF :: getExplicitSectionGlobal ( GO , SK , TM ) ; } </s>

Targets should implement this method to assign a section to globals with an explicit section specfied .


<s> int AArch64AsmParser :: tryParseRegister ( ) { MCAsmParser & Parser = getParser ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return - 1 ; std :: string lowerCase = Tok . getString ( ) . lower ( ) ; unsigned RegNum = matchRegisterNameAlias ( lowerCase , false ) ; if ( RegNum == 0 ) RegNum = StringSwitch < unsigned > ( lowerCase ) . Case ( "fp" , AArch64 :: FP ) . Case ( "lr" , AArch64 :: LR ) . Case ( "x31" , AArch64 :: XZR ) . Case ( "w31" , AArch64 :: WZR ) . Default ( 0 ) ; if ( RegNum == 0 ) return - 1 ; Parser . Lex ( ) ; return RegNum ; } </s>

tryParseRegister - parse one register if possible


<s> long rs6000_const_f32_to_i32 ( rtx operand ) { long value ; const struct real_value * rv = CONST_DOUBLE_REAL_VALUE ( operand ) ; gcc_assert ( GET_MODE ( operand ) == SFmode ) ; REAL_VALUE_TO_TARGET_SINGLE ( * rv , value ) ; return value ; } </s>

Convert a SFmode constant to the integer bit pattern .


"SI Lower control flow pseudo instructions"


<s> static bool aarch64_legitimate_constant_p ( machine_mode mode , rtx x ) { if ( TARGET_SIMD && aarch64_vect_struct_mode_p ( mode ) ) return false ; if ( ( GET_CODE ( x ) == CONST_VECTOR && aarch64_simd_valid_immediate ( x , mode , false , NULL ) ) || CONST_INT_P ( x ) || aarch64_valid_floating_const ( mode , x ) ) return ! targetm . cannot_force_const_mem ( mode , x ) ; if ( GET_CODE ( x ) == HIGH && aarch64_valid_symref ( XEXP ( x , 0 ) , GET_MODE ( XEXP ( x , 0 ) ) ) ) return true ; return aarch64_constant_address_p ( x ) ; } </s>

Implement TARGET_LEGITIMATE_CONSTANT_P hook . Return true for constants that should be rematerialized rather than spilled .


Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calling convention CallConv .


"unimplemented opcode in encodeInstruction()"

Encode the given Inst to bytes and append to CB .


<s> const MCPhysReg * SystemZTargetLowering :: getScratchRegisters ( CallingConv :: ID ) const { static const MCPhysReg ScratchRegs [ ] = { SystemZ :: R0D , SystemZ :: R1D , SystemZ :: R14D , 0 } ; return ScratchRegs ; } </s>

Returns a 0 terminated array of registers that can be safely used as scratch registers .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
Register
:
OS
<<
"<register "
<<
getReg
(
)
<<
" mods: "
<<
Reg
.
Modifiers
<<
'>'
;
break
;
case
Immediate
:
OS
<<
getImm
(
)
;
break
;
case
Token
:
OS
<<
'\''
<<
getToken
(
)
<<
'\''
;
break
;
case
Expression
:
OS
<<
"<expr "
<<
*
Expr
<<
'>'
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> const Z80Subtarget & getSubtarget ( ) const { return * Subtarget ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


<s> static bool arm_align_anon_bitfield ( void ) { return TARGET_AAPCS_BASED ; } </s>

AAPCS requires that anonymous bitfields affect structure alignment .


<s> unsigned getNumberOfRegisters ( unsigned ClassID ) const { bool Vector = ( ClassID == 1 ) ; if ( Vector ) { return 0 ; } return 12 ; } </s>


<s>
TargetTransformInfo
MipsTargetMachine
::
getTargetTransformInfo
(
const
Function
&
F
)
const
{
if
(
Subtarget
->
allowMixed16_32
(
)
)
{
LLVM_DEBUG
(
errs
(
)
<<
"No Target Transform Info Pass Added\n"
)
;
return
TargetTransformInfo
(
F
.
getParent
(
)
->
getDataLayout
(
)
)
;
}
LLVM_DEBUG
(
errs
(
)
<<
"Target Transform Info Pass Added\n"
)
;
return
TargetTransformInfo
(
MipsTTIImpl
(
this
,
F
)
)
;
}
</s>

Get a TargetTransformInfo implementation for the target .

Mips
Mips
"No Target Transform Info Pass Added\n"
"Target Transform Info Pass Added\n"
Mips


<s>
void
X86DAGToDAGISel
::
PreprocessISelDAG
(
)
{
OptForSize
=
MF
->
getFunction
(
)
->
optForSize
(
)
;
OptForMinSize
=
MF
->
getFunction
(
)
->
optForMinSize
(
)
;
assert
(
(
!
OptForMinSize
||
OptForSize
)
&&
"OptForMinSize implies OptForSize"
)
;
for
(
SelectionDAG
::
allnodes_iterator
I
=
CurDAG
->
allnodes_begin
(
)
,
E
=
CurDAG
->
allnodes_end
(
)
;
I
!=
E
;
)
{
SDNode
*
N
=
&
*
I
++
;
if
(
OptLevel
!=
CodeGenOpt
::
&&
(
(
N
->
getOpcode
(
)
==
X86ISD
::
CALL
&&
!
Subtarget
->
callRegIndirect
(
)
)
||
(
N
->
getOpcode
(
)
==
X86ISD
::
TC_RETURN
&&
(
Subtarget
->
is64Bit
(
)
||
!
getTargetMachine
(
)
.
isPositionIndependent
(
)
)
)
)
)
{
bool
HasCallSeq
=
N
->
getOpcode
(
)
==
X86ISD
::
CALL
;
SDValue
Chain
=
N
->
getOperand
(
0
)
;
SDValue
Load
=
N
->
getOperand
(
1
)
;
if
(
!
isCalleeLoad
(
Load
,
Chain
,
HasCallSeq
)
)
continue
;
moveBelowOrigChain
(
CurDAG
,
Load
,
SDValue
(
N
,
0
)
,
Chain
)
;
++
NumLoadMoved
;
continue
;
}
if
(
N
->
getOpcode
(
)
!=
ISD
::
FP_ROUND
&&
N
->
getOpcode
(
)
!=
ISD
::
FP_EXTEND
)
continue
;
MVT
SrcVT
=
N
->
getOperand
(
0
)
.
getSimpleValueType
(
)
;
MVT
DstVT
=
N
->
getSimpleValueType
(
0
)
;
if
(
SrcVT
.
isVector
(
)
||
DstVT
.
isVector
(
)
)
continue
;
const
X86TargetLowering
*
X86Lowering
=
static_cast
<
const
X86TargetLowering
*
>
(
TLI
)
;
bool
SrcIsSSE
=
X86Lowering
->
isScalarFPTypeInSSEReg
(
SrcVT
)
;
bool
DstIsSSE
=
X86Lowering
->
isScalarFPTypeInSSEReg
(
DstVT
)
;
if
(
SrcIsSSE
&&
DstIsSSE
)
continue
;
if
(
!
SrcIsSSE
&&
!
DstIsSSE
)
{
if
(
N
->
getOpcode
(
)
==
ISD
::
FP_EXTEND
)
continue
;
if
(
N
->
getConstantOperandVal
(
1
)
)
continue
;
}
MVT
MemVT
;
if
(
N
->
getOpcode
(
)
==
ISD
::
FP_ROUND
)
MemVT
=
DstVT
;
else
MemVT
=
SrcIsSSE
SrcVT
:
DstVT
;
SDValue
MemTmp
=
CurDAG
->
CreateStackTemporary
(
MemVT
)
;
SDLoc
dl
(
N
)
;
SDValue
Store
=
CurDAG
->
getTruncStore
(
CurDAG
->
getEntryNode
(
)
,
dl
,
N
->
getOperand
(
0
)
,
MemTmp
,
MachinePointerInfo
(
)
,
MemVT
)
;
SDValue
Result
=
CurDAG
->
getExtLoad
(
ISD
::
EXTLOAD
,
dl
,
DstVT
,
Store
,
MemTmp
,
MachinePointerInfo
(
)
,
MemVT
)
;
I
;
CurDAG
->
ReplaceAllUsesOfValueWith
(
SDValue
(
N
,
0
)
,
Result
)
;
++
I
;
CurDAG
->
DeleteNode
(
N
)
;
}
}
</s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
isReg
(
)
&&
"Invalid type access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s> opt_machine_mode aarch64_vq_mode ( scalar_mode mode ) { switch ( mode ) { case E_DFmode : return V2DFmode ; case E_SFmode : return V4SFmode ; case E_HFmode : return V8HFmode ; case E_BFmode : return V8BFmode ; case E_SImode : return V4SImode ; case E_HImode : return V8HImode ; case E_QImode : return V16QImode ; case E_DImode : return V2DImode ; default : return opt_machine_mode ( ) ; } } </s>

Return the 128-bit Advanced SIMD vector mode for element mode MODE , if it exists .


<s> void rs6000_emit_swdivdf ( rtx res , rtx n , rtx d ) { rtx x0 , e0 , e1 , e2 , y1 , y2 , y3 , u0 , v0 , one ; x0 = gen_reg_rtx ( DFmode ) ; e0 = gen_reg_rtx ( DFmode ) ; e1 = gen_reg_rtx ( DFmode ) ; e2 = gen_reg_rtx ( DFmode ) ; y1 = gen_reg_rtx ( DFmode ) ; y2 = gen_reg_rtx ( DFmode ) ; y3 = gen_reg_rtx ( DFmode ) ; u0 = gen_reg_rtx ( DFmode ) ; v0 = gen_reg_rtx ( DFmode ) ; one = force_reg ( DFmode , CONST_DOUBLE_FROM_REAL_VALUE ( dconst1 , DFmode ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x0 , gen_rtx_UNSPEC ( DFmode , gen_rtvec ( 1 , d ) , UNSPEC_FRES ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , e0 , gen_rtx_MINUS ( DFmode , one , gen_rtx_MULT ( SFmode , d , x0 ) ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , y1 , gen_rtx_PLUS ( DFmode , gen_rtx_MULT ( DFmode , e0 , x0 ) , x0 ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , e1 , gen_rtx_MULT ( DFmode , e0 , e0 ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , y2 , gen_rtx_PLUS ( DFmode , gen_rtx_MULT ( DFmode , e1 , y1 ) , y1 ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , e2 , gen_rtx_MULT ( DFmode , e1 , e1 ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , y3 , gen_rtx_PLUS ( DFmode , gen_rtx_MULT ( DFmode , e2 , y2 ) , y2 ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , u0 , gen_rtx_MULT ( DFmode , n , y3 ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , v0 , gen_rtx_MINUS ( DFmode , n , gen_rtx_MULT ( DFmode , d , u0 ) ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , res , gen_rtx_PLUS ( DFmode , gen_rtx_MULT ( DFmode , v0 , y3 ) , u0 ) ) ) ; } </s>

Newton-Raphson approximation of double-precision floating point divide n/d . Assumes no trapping math and finite arguments .


<s> bool Warning ( SMLoc L , const Twine & Msg , SMRange Range = None ) { return getParser ( ) . Warning ( L , Msg , Range ) ; } </s>

Emit a warning at the location L , with the message Msg .


Return true if INSN is a multiply-add or multiply-subtract instruction and PREV assigns to the accumulator operand .


<s> rtx thumb_legitimize_address ( rtx x , rtx orig_x , machine_mode mode ) { if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , 1 ) ) && ( INTVAL ( XEXP ( x , 1 ) ) >= 32 * GET_MODE_SIZE ( mode ) || INTVAL ( XEXP ( x , 1 ) ) < 0 ) ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; HOST_WIDE_INT offset = INTVAL ( xop1 ) ; if ( optimize_size && offset >= 0 && offset < 256 + 31 * GET_MODE_SIZE ( mode ) ) { HOST_WIDE_INT delta ; if ( offset >= 256 ) delta = offset - ( 256 - GET_MODE_SIZE ( mode ) ) ; else if ( offset < 32 * GET_MODE_SIZE ( mode ) + 8 ) delta = 31 * GET_MODE_SIZE ( mode ) ; else delta = offset & ( ~ 31 * GET_MODE_SIZE ( mode ) ) ; xop0 = force_operand ( plus_constant ( Pmode , xop0 , offset - delta ) , NULL_RTX ) ; x = plus_constant ( Pmode , xop0 , delta ) ; } else if ( offset < 0 && offset > - 256 ) x = force_operand ( x , NULL_RTX ) ; else { xop1 = force_reg ( SImode , xop1 ) ; x = gen_rtx_PLUS ( SImode , xop0 , xop1 ) ; } } else if ( GET_CODE ( x ) == PLUS && s_register_operand ( XEXP ( x , 1 ) , SImode ) && ! s_register_operand ( XEXP ( x , 0 ) , SImode ) ) { rtx xop0 = force_operand ( XEXP ( x , 0 ) , NULL_RTX ) ; x = gen_rtx_PLUS ( SImode , xop0 , XEXP ( x , 1 ) ) ; } if ( flag_pic ) { rtx new_x = legitimize_pic_address ( orig_x , mode , NULL_RTX ) ; if ( new_x != orig_x ) x = new_x ; } return x ; } </s>

Try machine-dependent ways of modifying an illegitimate Thumb address to be legitimate . If we find one , return the new , valid address .


<s> static save_entry * sh5_schedule_saves ( HARD_REG_SET * live_regs_mask , save_schedule * schedule , int offset_base ) { int align , i ; save_entry * entry = schedule -> entries ; int tmpx = 0 ; int offset ; if ( ! current_function_interrupt ) for ( i = FIRST_GENERAL_REG ; tmpx < MAX_TEMPS && i <= LAST_GENERAL_REG ; i ++ ) if ( call_really_used_regs [ i ] && ! fixed_regs [ i ] && i != PR_MEDIA_REG && ! FUNCTION_ARG_REGNO_P ( i ) && i != FIRST_RET_REG && ! ( cfun -> static_chain_decl != NULL && i == STATIC_CHAIN_REGNUM ) && ! ( current_function_calls_eh_return && ( i == EH_RETURN_STACKADJ_REGNO || ( ( unsigned ) i >= EH_RETURN_DATA_REGNO ( 0 ) && ( unsigned ) i <= EH_RETURN_DATA_REGNO ( 3 ) ) ) ) ) schedule -> temps [ tmpx ++ ] = i ; entry -> reg = - 1 ; entry -> mode = VOIDmode ; entry -> offset = offset_base ; entry ++ ; offset = offset_base ; for ( align = 1 ; align >= 0 ; align -- ) { for ( i = FIRST_PSEUDO_REGISTER - 1 ; i >= 0 ; i -- ) if ( TEST_HARD_REG_BIT ( * live_regs_mask , i ) ) { enum machine_mode mode = REGISTER_NATURAL_MODE ( i ) ; int reg = i ; if ( current_function_interrupt ) { if ( TARGET_REGISTER_P ( i ) ) continue ; if ( GENERAL_REGISTER_P ( i ) ) mode = DImode ; } if ( mode == SFmode && ( i % 2 ) == 1 && ! TARGET_FPU_SINGLE && FP_REGISTER_P ( i ) && ( TEST_HARD_REG_BIT ( * live_regs_mask , ( i ^ 1 ) ) ) ) { mode = DFmode ; i -- ; reg -- ; } if ( ( GET_MODE_SIZE ( mode ) % ( STACK_BOUNDARY / BITS_PER_UNIT ) == 0 ) != align ) continue ; if ( current_function_interrupt && GENERAL_REGISTER_P ( i ) && tmpx < MAX_TEMPS ) schedule -> temps [ tmpx ++ ] = i ; offset -= GET_MODE_SIZE ( mode ) ; entry -> reg = i ; entry -> mode = mode ; entry -> offset = offset ; entry ++ ; } if ( align && current_function_interrupt ) for ( i = LAST_TARGET_REG ; i >= FIRST_TARGET_REG ; i -- ) if ( TEST_HARD_REG_BIT ( * live_regs_mask , i ) ) { offset -= GET_MODE_SIZE ( DImode ) ; entry -> reg = i ; entry -> mode = DImode ; entry -> offset = offset ; entry ++ ; } } entry -> reg = - 1 ; entry -> mode = VOIDmode ; entry -> offset = offset ; schedule -> temps [ tmpx ] = - 1 ; return entry - 1 ; } </s>

Fill in SCHEDULE according to LIVE_REGS_MASK . If RESTORE is nonzero , use reverse order . Returns the last entry written to ( not counting the delimiter ) . OFFSET_BASE is a number to be added to all offset entries .


<s>
const
LegalizerInfo
*
AArch64Subtarget
::
getLegalizerInfo
(
)
const
{
assert
(
GISel
&&
"Access to GlobalISel APIs not set"
)
;
return
GISel
->
getLegalizerInfo
(
)
;
}
</s>

Expose LegalizerInfo so the clients can re-use .


<s> int mmix_starting_frame_offset ( ) { return ( - 8 + ( MMIX_CFUN_HAS_LANDING_PAD ? - 16 : ( MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS ? - 8 : 0 ) ) ) ; } </s>


"  Mark r%d def in insn %d as requiring both modes in chain #%d\n"

For DImode conversion , mark register defined by DEF as requiring conversion .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> static bool mips_cannot_force_const_mem ( machine_mode mode , rtx x ) { enum mips_symbol_type type ; rtx base , offset ; if ( GET_CODE ( x ) == HIGH ) return true ; if ( ( CONST_INT_P ( x ) || GET_CODE ( x ) == CONST_VECTOR ) && mips_legitimate_constant_p ( mode , x ) ) return true ; split_const ( x , & base , & offset ) ; if ( mips_symbolic_constant_p ( base , SYMBOL_CONTEXT_LEA , & type ) ) { if ( mips_use_pcrel_pool_p [ ( int ) type ] ) return false ; if ( SMALL_INT ( offset ) && mips_symbol_insns ( type , MAX_MACHINE_MODE ) > 0 ) return true ; if ( TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p ( type ) ) return true ; } if ( tls_referenced_p ( x ) ) return true ; return false ; } </s>

Return true if X can not be forced into a constant pool .


<s> bool AMDGPUCodeGenPrepare :: doInitialization ( Module & M ) { Mod = & M ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


runOnMachineFunction - Emit the function body .


<s> void NVPTXTTIImpl :: getUnrollingPreferences ( Loop * L , TTI :: UnrollingPreferences & UP ) { BaseT :: getUnrollingPreferences ( L , UP ) ; UP . Partial = UP . Runtime = true ; UP . PartialThreshold = UP . Threshold / 4 ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> SDValue AMDGPUTargetLowering :: SplitVectorLoad ( const SDValue Op , SelectionDAG & DAG ) const { LoadSDNode * Load = cast < LoadSDNode > ( Op ) ; EVT VT = Op . getValueType ( ) ; if ( VT . getVectorNumElements ( ) == 2 ) return scalarizeVectorLoad ( Load , DAG ) ; SDValue BasePtr = Load -> getBasePtr ( ) ; EVT PtrVT = BasePtr . getValueType ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; SDLoc SL ( Op ) ; const MachinePointerInfo & SrcValue = Load -> getMemOperand ( ) -> getPointerInfo ( ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Op , SL , LoVT , HiVT ) ; unsigned Size = LoMemVT . getStoreSize ( ) ; unsigned BaseAlign = Load -> getAlignment ( ) ; unsigned HiAlign = MinAlign ( BaseAlign , Size ) ; SDValue LoLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , LoVT , Load -> getChain ( ) , BasePtr , SrcValue , LoMemVT , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> isInvariant ( ) , BaseAlign ) ; SDValue HiPtr = DAG . getNode ( ISD :: ADD , SL , PtrVT , BasePtr , DAG . getConstant ( Size , SL , PtrVT ) ) ; SDValue HiLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , HiVT , Load -> getChain ( ) , HiPtr , SrcValue . getWithOffset ( LoMemVT . getStoreSize ( ) ) , HiMemVT , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> isInvariant ( ) , HiAlign ) ; SDValue Ops [ ] = { DAG . getNode ( ISD :: CONCAT_VECTORS , SL , VT , LoLoad , HiLoad ) , DAG . getNode ( ISD :: TokenFactor , SL , MVT :: Other , LoLoad . getValue ( 1 ) , HiLoad . getValue ( 1 ) ) } ; return DAG . getMergeValues ( Ops , SL ) ; } </s>

Split a vector load into 2 loads of half the vector .


<s> void MSP430RegisterInfo :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MSP430MachineFunctionInfo * MSP430FI = MF . getInfo < MSP430MachineFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; uint64_t NumBytes = 0 ; if ( hasFP ( MF ) ) { uint64_t FrameSize = StackSize - 2 ; NumBytes = FrameSize - MSP430FI -> getCalleeSavedFrameSize ( ) ; MFI -> setOffsetAdjustment ( - NumBytes ) ; BuildMI ( MBB , MBBI , DL , TII . get ( MSP430 :: PUSH16r ) ) . addReg ( MSP430 :: FPW , RegState :: Kill ) ; BuildMI ( MBB , MBBI , DL , TII . get ( MSP430 :: MOV16rr ) , MSP430 :: FPW ) . addReg ( MSP430 :: SPW ) ; for ( MachineFunction :: iterator I = llvm :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( MSP430 :: FPW ) ; } else NumBytes = StackSize - MSP430FI -> getCalleeSavedFrameSize ( ) ; while ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == MSP430 :: PUSH16r ) ) ++ MBBI ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes ) { if ( NumBytes ) { MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( MSP430 :: SUB16ri ) , MSP430 :: SPW ) . addReg ( MSP430 :: SPW ) . addImm ( NumBytes ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; } } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> SDValue SystemZSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool IsVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { if ( IsVolatile ) return SDValue ( ) ; if ( auto * CSize = dyn_cast < ConstantSDNode > ( Size ) ) return emitMemMem ( DAG , DL , SystemZISD :: MVC , SystemZISD :: MVC_LOOP , Chain , Dst , Src , CSize -> getZExtValue ( ) ) ; return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .

SystemZ SystemZ SystemZISD::MVC SystemZISD::MVC_LOOP


<s> virtual void * getAdjustedAnalysisPointer ( const void * ID ) { if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo * ) this ; return this ; } </s>

getAdjustedAnalysisPointer - This method is used when a pass implements an analysis interface through multiple inheritance .


<s> bool ARMBaseInstrInfo :: shouldOutlineFromFunctionByDefault ( MachineFunction & MF ) const { return Subtarget . isMClass ( ) && MF . getFunction ( ) . hasMinSize ( ) ; } </s>

Return true if the function should be outlined from by default .


<s>
bool
ARMTargetLowering
::
lowerInterleavedStore
(
StoreInst
*
SI
,
ShuffleVectorInst
*
SVI
,
unsigned
Factor
)
const
{
assert
(
Factor
>=
2
&&
Factor
<=
getMaxSupportedInterleaveFactor
(
)
&&
"Invalid interleave factor"
)
;
VectorType
*
VecTy
=
SVI
->
getType
(
)
;
assert
(
VecTy
->
getVectorNumElements
(
)
%
Factor
==
0
&&
"Invalid interleaved store"
)
;
unsigned
NumSubElts
=
VecTy
->
getVectorNumElements
(
)
/
Factor
;
Type
*
EltTy
=
VecTy
->
getVectorElementType
(
)
;
VectorType
*
SubVecTy
=
VectorType
::
get
(
EltTy
,
NumSubElts
)
;
const
DataLayout
&
DL
=
SI
->
getModule
(
)
->
getDataLayout
(
)
;
unsigned
SubVecSize
=
DL
.
getTypeAllocSizeInBits
(
SubVecTy
)
;
bool
EltIs64Bits
=
DL
.
getTypeAllocSizeInBits
(
EltTy
)
==
64
;
if
(
(
SubVecSize
!=
64
&&
SubVecSize
!=
128
)
||
EltIs64Bits
)
return
false
;
Value
*
Op0
=
SVI
->
getOperand
(
0
)
;
Value
*
Op1
=
SVI
->
getOperand
(
1
)
;
IRBuilder
<
>
Builder
(
SI
)
;
if
(
EltTy
->
isPointerTy
(
)
)
{
Type
*
IntTy
=
DL
.
getIntPtrType
(
EltTy
)
;
Type
*
IntVecTy
=
VectorType
::
get
(
IntTy
,
Op0
->
getType
(
)
->
getVectorNumElements
(
)
)
;
Op0
=
Builder
.
CreatePtrToInt
(
Op0
,
IntVecTy
)
;
Op1
=
Builder
.
CreatePtrToInt
(
Op1
,
IntVecTy
)
;
SubVecTy
=
VectorType
::
get
(
IntTy
,
NumSubElts
)
;
}
static
Intrinsic
::
ID
StoreInts
[
3
]
=
{
Intrinsic
::
arm_neon_vst2
,
Intrinsic
::
arm_neon_vst3
,
Intrinsic
::
arm_neon_vst4
}
;
Function
*
VstNFunc
=
Intrinsic
::
getDeclaration
(
SI
->
getModule
(
)
,
StoreInts
[
Factor
2
]
,
SubVecTy
)
;
SmallVector
<
Value
*
,
6
>
Ops
;
Type
*
Int8Ptr
=
Builder
.
getInt8PtrTy
(
SI
->
getPointerAddressSpace
(
)
)
;
Ops
.
push_back
(
Builder
.
CreateBitCast
(
SI
->
getPointerOperand
(
)
,
Int8Ptr
)
)
;
for
(
unsigned
i
=
0
;
i
<
Factor
;
i
++
)
Ops
.
push_back
(
Builder
.
CreateShuffleVector
(
Op0
,
Op1
,
getSequentialMask
(
Builder
,
NumSubElts
*
i
,
NumSubElts
)
)
)
;
Ops
.
push_back
(
Builder
.
getInt32
(
SI
->
getAlignment
(
)
)
)
;
Builder
.
CreateCall
(
VstNFunc
,
Ops
)
;
return
true
;
}
</s>

Lower interleaved store ( s ) into target specific instructions/intrinsics .


<s>
bool
ARMBaseInstrInfo
::
analyzeSelect
(
const
MachineInstr
*
MI
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
unsigned
&
TrueOp
,
unsigned
&
FalseOp
,
bool
&
Optimizable
)
const
{
assert
(
(
MI
->
getOpcode
(
)
==
ARM
::
MOVCCr
||
MI
->
getOpcode
(
)
==
ARM
::
t2MOVCCr
)
&&
"Unknown select instruction"
)
;
TrueOp
=
1
;
FalseOp
=
2
;
Cond
.
push_back
(
MI
->
getOperand
(
3
)
)
;
Cond
.
push_back
(
MI
->
getOperand
(
4
)
)
;
Optimizable
=
true
;
return
false
;
}
</s>

Analyze the given select instruction , returning true if it can not be understood .


<s> virtual const AlphaRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
MCSection
*
XCoreTargetObjectFile
::
getSectionForConstant
(
const
DataLayout
&
DL
,
SectionKind
Kind
,
const
Constant
*
C
,
unsigned
&
Align
,
const
GlobalObject
*
GO
)
const
{
if
(
Kind
.
isMergeableConst4
(
)
)
return
MergeableConst4Section
;
if
(
Kind
.
isMergeableConst8
(
)
)
return
MergeableConst8Section
;
if
(
Kind
.
isMergeableConst16
(
)
)
return
MergeableConst16Section
;
assert
(
(
Kind
.
isReadOnly
(
)
||
Kind
.
isReadOnlyWithRel
(
)
)
&&
"Unknown section kind"
)
;
return
ReadOnlySection
;
}
</s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> static bool arm_evpc_neon_vrev ( struct expand_vec_perm_d * d ) { unsigned int i , j , diff , nelt = d -> nelt ; rtx ( * gen ) ( rtx , rtx ) ; if ( ! d -> one_vector_p ) return false ; diff = d -> perm [ 0 ] ; switch ( diff ) { case 7 : switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vrev64v16qi ; break ; case V8QImode : gen = gen_neon_vrev64v8qi ; break ; default : return false ; } break ; case 3 : switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vrev32v16qi ; break ; case V8QImode : gen = gen_neon_vrev32v8qi ; break ; case V8HImode : gen = gen_neon_vrev64v8hi ; break ; case V4HImode : gen = gen_neon_vrev64v4hi ; break ; default : return false ; } break ; case 1 : switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vrev16v16qi ; break ; case V8QImode : gen = gen_neon_vrev16v8qi ; break ; case V8HImode : gen = gen_neon_vrev32v8hi ; break ; case V4HImode : gen = gen_neon_vrev32v4hi ; break ; case V4SImode : gen = gen_neon_vrev64v4si ; break ; case V2SImode : gen = gen_neon_vrev64v2si ; break ; case V4SFmode : gen = gen_neon_vrev64v4sf ; break ; case V2SFmode : gen = gen_neon_vrev64v2sf ; break ; default : return false ; } break ; default : return false ; } for ( i = 0 ; i < nelt ; i += diff + 1 ) for ( j = 0 ; j <= diff ; j += 1 ) { gcc_assert ( i + j < nelt ) ; if ( d -> perm [ i + j ] != i + diff - j ) return false ; } if ( d -> testing_p ) return true ; emit_insn ( gen ( d -> target , d -> op0 ) ) ; return true ; } </s>


<s> int crx_const_double_ok ( rtx op ) { if ( GET_MODE ( op ) == DFmode ) { REAL_VALUE_TYPE r ; long l [ 2 ] ; REAL_VALUE_FROM_CONST_DOUBLE ( r , op ) ; REAL_VALUE_TO_TARGET_DOUBLE ( r , l ) ; return ( UNSIGNED_INT_FITS_N_BITS ( l [ 0 ] , 4 ) && UNSIGNED_INT_FITS_N_BITS ( l [ 1 ] , 4 ) ) ? 1 : 0 ; } if ( GET_MODE ( op ) == SFmode ) { REAL_VALUE_TYPE r ; long l ; REAL_VALUE_FROM_CONST_DOUBLE ( r , op ) ; REAL_VALUE_TO_TARGET_SINGLE ( r , l ) ; return UNSIGNED_INT_FITS_N_BITS ( l , 4 ) ? 1 : 0 ; } return ( UNSIGNED_INT_FITS_N_BITS ( CONST_DOUBLE_LOW ( op ) , 4 ) && UNSIGNED_INT_FITS_N_BITS ( CONST_DOUBLE_HIGH ( op ) , 4 ) ) ? 1 : 0 ; } </s>

Check if a const_double is ok for crx store-immediate instructions


<s> rtx frv_split_minmax ( rtx operands [ ] ) { rtx dest = operands [ 0 ] ; rtx minmax = operands [ 1 ] ; rtx src1 = operands [ 2 ] ; rtx src2 = operands [ 3 ] ; rtx cc_reg = operands [ 4 ] ; rtx cr_reg = operands [ 5 ] ; rtx ret ; enum rtx_code test_code ; enum machine_mode cr_mode = GET_MODE ( cr_reg ) ; start_sequence ( ) ; switch ( GET_CODE ( minmax ) ) { default : gcc_unreachable ( ) ; case SMIN : test_code = LT ; break ; case SMAX : test_code = GT ; break ; case UMIN : test_code = LTU ; break ; case UMAX : test_code = GTU ; break ; } emit_insn ( gen_rtx_SET ( VOIDmode , cc_reg , gen_rtx_COMPARE ( GET_MODE ( cc_reg ) , src1 , src2 ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cr_reg , gen_rtx_fmt_ee ( test_code , GET_MODE ( cr_reg ) , cc_reg , const0_rtx ) ) ) ; if ( GET_CODE ( src2 ) == CONST_INT && INTVAL ( src2 ) != 0 ) { gcc_assert ( ! rtx_equal_p ( dest , src1 ) ) ; emit_move_insn ( dest , src2 ) ; emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_NE ( cr_mode , cr_reg , const0_rtx ) , gen_rtx_SET ( VOIDmode , dest , src1 ) ) ) ; } else { if ( ! rtx_equal_p ( dest , src1 ) ) emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_NE ( cr_mode , cr_reg , const0_rtx ) , gen_rtx_SET ( VOIDmode , dest , src1 ) ) ) ; if ( ! rtx_equal_p ( dest , src2 ) ) emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_EQ ( cr_mode , cr_reg , const0_rtx ) , gen_rtx_SET ( VOIDmode , dest , src2 ) ) ) ; } ret = get_insns ( ) ; end_sequence ( ) ; return ret ; } </s>

Split a min/max operation returning a SEQUENCE containing all of the insns .


<s>
static
rtx
bpf_expand_builtin
(
tree
exp
,
rtx
target
ATTRIBUTE_UNUSED
,
rtx
subtarget
ATTRIBUTE_UNUSED
,
machine_mode
mode
ATTRIBUTE_UNUSED
,
int
ignore
ATTRIBUTE_UNUSED
)
{
tree
fndecl
=
TREE_OPERAND
(
CALL_EXPR_FN
(
exp
)
,
0
)
;
int
code
=
DECL_MD_FUNCTION_CODE
(
fndecl
)
;
if
(
code
==
BPF_BUILTIN_LOAD_BYTE
||
code
==
BPF_BUILTIN_LOAD_HALF
||
code
==
BPF_BUILTIN_LOAD_WORD
)
{
enum
insn_code
abs_icode
=
(
code
==
BPF_BUILTIN_LOAD_BYTE
CODE_FOR_ldabsb
:
code
==
BPF_BUILTIN_LOAD_HALF
CODE_FOR_ldabsh
:
CODE_FOR_ldabsw
)
;
enum
insn_code
ind_icode
=
(
code
==
BPF_BUILTIN_LOAD_BYTE
CODE_FOR_ldindb
:
code
==
BPF_BUILTIN_LOAD_HALF
CODE_FOR_ldindh
:
CODE_FOR_ldindw
)
;
tree
offset_arg
=
CALL_EXPR_ARG
(
exp
,
0
)
;
struct
expand_operand
ops
[
2
]
;
create_input_operand
(
&
ops
[
0
]
,
expand_normal
(
offset_arg
)
,
TYPE_MODE
(
TREE_TYPE
(
offset_arg
)
)
)
;
create_input_operand
(
&
ops
[
1
]
,
const0_rtx
,
SImode
)
;
if
(
!
maybe_expand_insn
(
abs_icode
,
2
,
ops
)
&&
!
maybe_expand_insn
(
ind_icode
,
2
,
ops
)
)
{
error
(
"invalid argument to built-in function"
)
;
return
gen_rtx_REG
(
ops
[
0
]
.
mode
,
BPF_R0
)
;
}
return
gen_rtx_REG
(
ops
[
0
]
.
mode
,
BPF_R0
)
;
}
else
if
(
code
==
BPF_BUILTIN_PRESERVE_ACCESS_INDEX
)
{
tree
arg
=
CALL_EXPR_ARG
(
exp
,
0
)
;
if
(
arg
==
NULL_TREE
)
return
NULL_RTX
;
if
(
TREE_CODE
(
arg
)
==
SSA_NAME
)
{
gimple
*
def_stmt
=
SSA_NAME_DEF_STMT
(
arg
)
;
if
(
is_gimple_assign
(
def_stmt
)
)
arg
=
gimple_assign_rhs1
(
def_stmt
)
;
else
return
expand_normal
(
arg
)
;
}
if
(
!
is_attr_preserve_access
(
arg
)
)
maybe_make_core_relo
(
arg
,
BPF_RELO_FIELD_BYTE_OFFSET
)
;
return
expand_normal
(
arg
)
;
}
else
if
(
code
==
BPF_BUILTIN_PRESERVE_FIELD_INFO
)
{
tree
src
=
CALL_EXPR_ARG
(
exp
,
0
)
;
tree
kind_tree
=
CALL_EXPR_ARG
(
exp
,
1
)
;
unsigned
HOST_WIDE_INT
kind_val
=
0
;
if
(
tree_fits_uhwi_p
(
kind_tree
)
)
kind_val
=
tree_to_uhwi
(
kind_tree
)
;
else
{
error
(
"invalid argument to built-in function"
)
;
return
expand_normal
(
error_mark_node
)
;
}
enum
btf_core_reloc_kind
kind
=
(
enum
btf_core_reloc_kind
)
kind_val
;
if
(
TREE_CODE
(
src
)
==
SSA_NAME
)
{
gimple
*
def_stmt
=
SSA_NAME_DEF_STMT
(
src
)
;
if
(
is_gimple_assign
(
def_stmt
)
)
src
=
gimple_assign_rhs1
(
def_stmt
)
;
}
if
(
TREE_CODE
(
src
)
==
ADDR_EXPR
)
src
=
TREE_OPERAND
(
src
,
0
)
;
tree
result
=
bpf_core_field_info
(
src
,
kind
)
;
if
(
result
!=
error_mark_node
)
maybe_make_core_relo
(
src
,
kind
)
;
return
expand_normal
(
result
)
;
}
gcc_unreachable
(
)
;
}
</s>

Expand a call to a BPF-specific built-in function that was set up with bpf_init_builtins .


<s> const IntegerRangeState & getState ( ) const override { return * this ; } </s>


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , computeDefaultCPU ( TT , CPU ) , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveAArch64CodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } if ( getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) { this -> Options . TrapUnreachable = true ; } if ( this -> Options . TLSSize == 0 ) this -> Options . TLSSize = 24 ; if ( ( getCodeModel ( ) == CodeModel :: Small || getCodeModel ( ) == CodeModel :: Kernel ) && this -> Options . TLSSize > 32 ) this -> Options . TLSSize = 32 ; else if ( getCodeModel ( ) == CodeModel :: Tiny && this -> Options . TLSSize > 24 ) this -> Options . TLSSize = 24 ; if ( getOptLevel ( ) <= EnableGlobalISelAtO && TT . getArch ( ) != Triple :: aarch64_32 && TT . getArchName ( ) != "arm64e" && TT . getEnvironment ( ) != Triple :: GNUILP32 && ! ( getCodeModel ( ) == CodeModel :: Large && TT . isOSBinFormatMachO ( ) ) ) { setGlobalISel ( true ) ; setGlobalISelAbort ( GlobalISelAbortMode :: Disable ) ; } setMachineOutliner ( true ) ; setSupportsDefaultOutlining ( true ) ; setSupportsDebugEntryValues ( true ) ; } </s>


<s> void ix86_expand_floorceil ( rtx operand0 , rtx operand1 , bool do_floor ) { machine_mode mode = GET_MODE ( operand0 ) ; rtx xa , xi , TWO52 , tmp , one , res , mask ; rtx_code_label * label ; TWO52 = ix86_gen_TWO52 ( mode ) ; res = copy_to_reg ( operand1 ) ; xa = ix86_expand_sse_fabs ( res , & mask ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; xi = gen_reg_rtx ( int_mode_for_mode ( mode ) . require ( ) ) ; expand_fix ( xi , res , 0 ) ; expand_float ( xa , xi , 0 ) ; one = force_reg ( mode , const_double_from_real_value ( dconst1 , mode ) ) ; tmp = ix86_expand_sse_compare_mask ( UNGT , xa , res , ! do_floor ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_AND ( mode , one , tmp ) ) ) ; tmp = expand_simple_binop ( mode , do_floor ? MINUS : PLUS , xa , tmp , NULL_RTX , 0 , OPTAB_DIRECT ) ; if ( HONOR_SIGNED_ZEROS ( mode ) ) { if ( do_floor && flag_rounding_math ) tmp = ix86_expand_sse_fabs ( tmp , NULL ) ; ix86_sse_copysign_to_positive ( tmp , tmp , res , mask ) ; } emit_move_insn ( res , tmp ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; emit_move_insn ( operand0 , res ) ; } </s>

Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing into OPERAND0 .


<s> void NyuziFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( hasFP ( MF ) ) SavedRegs . set ( Nyuzi :: FP_REG ) ; if ( isInt < 14 > ( getWorstCaseStackSize ( MF ) ) ) return ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const TargetRegisterClass & RC = Nyuzi :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlignment ( RC ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s>
int
AArch64TTIImpl
::
getArithmeticReductionCost
(
unsigned
Opcode
,
Type
*
ValTy
,
bool
IsPairwiseForm
)
{
if
(
IsPairwiseForm
)
return
BaseT
::
getArithmeticReductionCost
(
Opcode
,
ValTy
,
IsPairwiseForm
)
;
std
::
pair
<
int
,
MVT
>
LT
=
TLI
->
getTypeLegalizationCost
(
DL
,
ValTy
)
;
MVT
MTy
=
LT
.
second
;
int
ISD
=
TLI
->
InstructionOpcodeToISD
(
Opcode
)
;
assert
(
ISD
&&
"Invalid opcode"
)
;
static
const
CostTblEntry
CostTblNoPairwise
[
]
{
{
ISD
::
ADD
,
MVT
::
v8i8
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v16i8
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v4i16
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v8i16
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v4i32
,
1
}
,
}
;
if
(
const
auto
*
Entry
=
CostTableLookup
(
CostTblNoPairwise
,
ISD
,
MTy
)
)
return
LT
.
first
*
Entry
->
Cost
;
return
BaseT
::
getArithmeticReductionCost
(
Opcode
,
ValTy
,
IsPairwiseForm
)
;
}
</s>

Calculate the cost of vector reduction intrinsics .


<s>
bool
X86CallLowering
::
lowerReturn
(
MachineIRBuilder
&
MIRBuilder
,
const
Value
*
Val
,
unsigned
VReg
)
const
{
assert
(
(
(
Val
&&
VReg
)
||
(
!
Val
&&
!
VReg
)
)
&&
"Return value without a vreg"
)
;
auto
MIB
=
MIRBuilder
.
buildInstrNoInsert
(
X86
::
RET
)
.
addImm
(
0
)
;
if
(
VReg
)
{
MachineFunction
&
MF
=
MIRBuilder
.
getMF
(
)
;
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
auto
&
DL
=
MF
.
getDataLayout
(
)
;
const
Function
&
F
=
*
MF
.
getFunction
(
)
;
ArgInfo
OrigArg
{
VReg
,
Val
->
getType
(
)
}
;
setArgFlags
(
OrigArg
,
AttributeList
::
ReturnIndex
,
DL
,
F
)
;
SmallVector
<
ArgInfo
,
8
>
SplitArgs
;
if
(
!
splitToValueTypes
(
OrigArg
,
SplitArgs
,
DL
,
MRI
,
[
&
]
(
ArrayRef
<
unsigned
>
Regs
)
{
MIRBuilder
.
buildUnmerge
(
Regs
,
VReg
)
;
}
)
)
return
false
;
FuncReturnHandler
Handler
(
MIRBuilder
,
MRI
,
MIB
,
RetCC_X86
)
;
if
(
!
handleAssignments
(
MIRBuilder
,
SplitArgs
,
Handler
)
)
return
false
;
}
MIRBuilder
.
insertInstr
(
MIB
)
;
return
true
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> static tree aarch64_promoted_type ( const_tree t ) { if ( SCALAR_FLOAT_TYPE_P ( t ) && TYPE_MAIN_VARIANT ( t ) == aarch64_fp16_type_node ) return float_type_node ; return NULL_TREE ; } </s>

Implement TARGET_PROMOTED_TYPE to promote __fp16 to float .


<s> bool MipsTargetMachine :: addPreRegAlloc ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( ! Subtarget . hasMips64 ( ) ) PM . add ( createMipsEmitGPRestorePass ( * this ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s>
static
char
*
rs6000_savres_routine_name
(
int
regno
,
int
sel
)
{
const
char
*
prefix
=
""
;
const
char
*
suffix
=
""
;
if
(
DEFAULT_ABI
==
ABI_V4
)
{
if
(
TARGET_64BIT
)
goto
aix_names
;
if
(
(
sel
&
SAVRES_REG
)
==
SAVRES_GPR
)
prefix
=
(
sel
&
SAVRES_SAVE
)
"_savegpr_"
:
"_restgpr_"
;
else
if
(
(
sel
&
SAVRES_REG
)
==
SAVRES_FPR
)
prefix
=
(
sel
&
SAVRES_SAVE
)
"_savefpr_"
:
"_restfpr_"
;
else
if
(
(
sel
&
SAVRES_REG
)
==
SAVRES_VR
)
prefix
=
(
sel
&
SAVRES_SAVE
)
"_savevr_"
:
"_restvr_"
;
else
abort
(
)
;
if
(
(
sel
&
SAVRES_LR
)
)
suffix
=
"_x"
;
}
else
if
(
DEFAULT_ABI
==
ABI_AIX
||
DEFAULT_ABI
==
ABI_ELFv2
)
{
gcc_assert
(
!
TARGET_AIX
||
(
sel
&
SAVRES_REG
)
!=
SAVRES_GPR
)
;
aix_names
:
if
(
(
sel
&
SAVRES_REG
)
==
SAVRES_GPR
)
prefix
=
(
(
sel
&
SAVRES_SAVE
)
(
(
sel
&
SAVRES_LR
)
"_savegpr0_"
:
"_savegpr1_"
)
:
(
(
sel
&
SAVRES_LR
)
"_restgpr0_"
:
"_restgpr1_"
)
)
;
else
if
(
(
sel
&
SAVRES_REG
)
==
SAVRES_FPR
)
{
if
(
(
sel
&
SAVRES_LR
)
)
prefix
=
(
(
sel
&
SAVRES_SAVE
)
"_savefpr_"
:
"_restfpr_"
)
;
else
{
prefix
=
(
sel
&
SAVRES_SAVE
)
SAVE_FP_PREFIX
:
RESTORE_FP_PREFIX
;
suffix
=
(
sel
&
SAVRES_SAVE
)
SAVE_FP_SUFFIX
:
RESTORE_FP_SUFFIX
;
}
}
else
if
(
(
sel
&
SAVRES_REG
)
==
SAVRES_VR
)
prefix
=
(
sel
&
SAVRES_SAVE
)
"_savevr_"
:
"_restvr_"
;
else
abort
(
)
;
}
if
(
DEFAULT_ABI
==
ABI_DARWIN
)
{
prefix
=
(
sel
&
SAVRES_SAVE
)
"save"
:
"rest"
;
if
(
(
sel
&
SAVRES_REG
)
==
SAVRES_GPR
)
sprintf
(
savres_routine_name
,
"*%sGPR%s%s%.0d ; %s r%d-r31"
,
prefix
,
(
(
sel
&
SAVRES_LR
)
"x"
:
""
)
,
(
regno
==
13
""
:
"+"
)
,
(
regno
13
)
*
4
,
prefix
,
regno
)
;
else
if
(
(
sel
&
SAVRES_REG
)
==
SAVRES_FPR
)
sprintf
(
savres_routine_name
,
"*%sFP%s%.0d ; %s f%d-f31"
,
prefix
,
(
regno
==
14
""
:
"+"
)
,
(
regno
14
)
*
4
,
prefix
,
regno
)
;
else
if
(
(
sel
&
SAVRES_REG
)
==
SAVRES_VR
)
sprintf
(
savres_routine_name
,
"*%sVEC%s%.0d ; %s v%d-v31"
,
prefix
,
(
regno
==
20
""
:
"+"
)
,
(
regno
20
)
*
8
,
prefix
,
regno
)
;
else
abort
(
)
;
}
else
sprintf
(
savres_routine_name
,
"%s%d%s"
,
prefix
,
regno
,
suffix
)
;
return
savres_routine_name
;
}
</s>

Return the name for an out-of-line register save/restore routine . We are saving/restoring GPRs if GPR is true .


<s> static void s390_swap_cmp ( rtx cond , rtx * op0 , rtx * op1 , rtx_insn * insn ) { rtx tmp = * op0 ; if ( cond == NULL_RTX ) { rtx_insn * jump = find_cond_jump ( NEXT_INSN ( insn ) ) ; rtx set = jump ? single_set ( jump ) : NULL_RTX ; if ( set == NULL_RTX ) return ; cond = XEXP ( SET_SRC ( set ) , 0 ) ; } * op0 = * op1 ; * op1 = tmp ; PUT_CODE ( cond , swap_condition ( GET_CODE ( cond ) ) ) ; } </s>

Swap the condition in COND and the operands in OP0 and OP1 so that the semantics does not change . If NULL_RTX is passed as COND the function tries to find the conditional jump starting with INSN .


<s> SDValue PPCTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { if ( PPCSubTarget . isSVR4ABI ( ) && ! PPCSubTarget . isPPC64 ( ) ) { return LowerFormalArguments_SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } else { return LowerFormalArguments_Darwin ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> bool ARM64AsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const { return int64_t ( Value ) != int64_t ( int8_t ( Value ) ) ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s>
char
*
crx_prepare_push_pop_string
(
int
push_or_pop
)
{
static
char
mask_str
[
50
]
;
int
i
=
0
;
int
ra_in_bitmask
=
0
;
char
*
return_str
;
char
*
temp_str
;
return_str
=
(
char
*
)
xmalloc
(
120
)
;
temp_str
=
(
char
*
)
xmalloc
(
120
)
;
memset
(
return_str
,
0
,
3
)
;
while
(
i
<=
last_reg_to_save
)
{
mask_str
[
0
]
=
0
;
if
(
i
<=
SP_REGNUM
)
{
int
j
=
0
;
while
(
j
<
MAX_COUNT
&&
i
<=
SP_REGNUM
)
{
if
(
save_regs
[
i
]
)
{
if
(
i
==
RETURN_ADDRESS_REGNUM
)
ra_in_bitmask
=
1
;
if
(
j
>
0
)
strcat
(
mask_str
,
", "
)
;
strcat
(
mask_str
,
reg_names
[
i
]
)
;
++
j
;
}
++
i
;
}
}
else
{
while
(
i
<=
last_reg_to_save
)
{
if
(
save_regs
[
i
]
)
{
strcat
(
mask_str
,
"lo, hi"
)
;
i
=
last_reg_to_save
+
1
;
break
;
}
++
i
;
}
}
if
(
strlen
(
mask_str
)
==
0
)
continue
;
if
(
push_or_pop
==
1
)
{
if
(
crx_interrupt_function_p
(
)
)
mpushpop_str
(
temp_str
,
"popx"
,
mask_str
)
;
else
{
if
(
ra_in_bitmask
)
{
mpushpop_str
(
temp_str
,
"popret"
,
mask_str
)
;
ra_in_bitmask
=
0
;
}
else
mpushpop_str
(
temp_str
,
"pop"
,
mask_str
)
;
}
strcat
(
return_str
,
temp_str
)
;
}
else
{
if
(
crx_interrupt_function_p
(
)
)
mpushpop_str
(
temp_str
,
"pushx"
,
mask_str
)
;
else
mpushpop_str
(
temp_str
,
"push"
,
mask_str
)
;
strcat
(
temp_str
,
return_str
)
;
strcpy
(
strcat
(
return_str
,
"\t"
)
,
temp_str
)
;
}
}
if
(
push_or_pop
==
1
)
{
if
(
crx_interrupt_function_p
(
)
)
strcat
(
return_str
,
"\n\tretx\n"
)
;
else
if
(
!
FUNC_IS_NORETURN_P
(
current_function_decl
)
&&
!
save_regs
[
RETURN_ADDRESS_REGNUM
]
)
strcat
(
return_str
,
"\n\tjump\tra\n"
)
;
}
return_str
+=
2
;
return
return_str
;
}
</s>

Called from crx.md . The return value depends on the parameter push_or_pop : * When push_or_pop is zero - > string for push instructions of prologue . * When push_or_pop is nonzero - > string for pop/popret/retx in epilogue . * Relies on the assumptions : * 1 . RA is the last register to be saved . * 2 . The maximal value of the counter is MAX_COUNT .


<s> bool X86TargetLowering :: hasInlineStackProbe ( MachineFunction & MF ) const { if ( Subtarget . isOSWindows ( ) || MF . getFunction ( ) . hasFnAttribute ( "no-stack-arg-probe" ) ) return false ; if ( MF . getFunction ( ) . hasFnAttribute ( "probe-stack" ) ) return MF . getFunction ( ) . getFnAttribute ( "probe-stack" ) . getValueAsString ( ) == "inline-asm" ; return false ; } </s>

Returns true if stack probing through inline assembly is requested .

X86 X86 "no-stack-arg-probe" "probe-stack" "probe-stack" "inline-asm"


<s> static void insert_wic ( void ) { rtx_insn * insn ; int i ; basic_block bb , prev = 0 ; rtx branch_target = 0 ; shorten_branches ( get_insns ( ) ) ; for ( i = 0 ; i < n_basic_blocks_for_fn ( cfun ) - 1 ; i ++ ) { edge e ; edge_iterator ei ; bool simple_loop = false ; bb = BASIC_BLOCK_FOR_FN ( cfun , i ) ; if ( bb == NULL ) continue ; if ( ( prev != 0 ) && ( prev != bb ) ) continue ; else prev = 0 ; FOR_EACH_EDGE ( e , ei , bb -> preds ) if ( e -> src == bb ) { simple_loop = true ; prev = e -> dest ; break ; } for ( insn = BB_END ( bb ) ; insn ; insn = PREV_INSN ( insn ) ) { if ( INSN_P ( insn ) && ! simple_loop && CALL_P ( insn ) ) { if ( ( branch_target = get_branch_target ( insn ) ) ) insert_wic_for_ilb_runout ( next_active_insn ( next_active_insn ( insn ) ) ) ; } if ( insn == BB_HEAD ( bb ) ) break ; } } } </s>

Insert instruction prefetch instruction at the fall through path of the function call .


<s> static bool global_reg_mentioned_p_1 ( const_rtx x ) { int regno ; switch ( GET_CODE ( x ) ) { case SUBREG : if ( REG_P ( SUBREG_REG ( x ) ) ) { if ( REGNO ( SUBREG_REG ( x ) ) < FIRST_PSEUDO_REGISTER && global_regs [ subreg_regno ( x ) ] ) return true ; return false ; } break ; case REG : regno = REGNO ( x ) ; if ( regno < FIRST_PSEUDO_REGISTER && global_regs [ regno ] ) return true ; return false ; case CALL : return true ; default : break ; } return false ; } </s>

A subroutine of global_reg_mentioned_p , returns 1 if * LOC mentions a global register .


<s> bool ARMSubtarget :: enablePostRAScheduler ( ) const { if ( getSchedModel ( ) . isOutOfOrder ( ) && isSwift ( ) ) return false ; return ( ! isThumb ( ) || hasThumb2 ( ) ) ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s> TargetPassConfig * OpenRISCTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new OpenRISCPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> MachineBasicBlock & getBlock ( ) const { return Block ; } </s>

getBlock - Return the current basic block .


<s> void aarch64_init_builtin_rsqrt ( void ) { tree fndecl = NULL ; tree ftype = NULL ; tree V2SF_type_node = build_vector_type ( float_type_node , 2 ) ; tree V2DF_type_node = build_vector_type ( double_type_node , 2 ) ; tree V4SF_type_node = build_vector_type ( float_type_node , 4 ) ; struct builtin_decls_data { tree type_node ; const char * builtin_name ; int function_code ; } ; builtin_decls_data bdda [ ] = { { double_type_node , "__builtin_aarch64_rsqrt_df" , AARCH64_BUILTIN_RSQRT_DF } , { float_type_node , "__builtin_aarch64_rsqrt_sf" , AARCH64_BUILTIN_RSQRT_SF } , { V2DF_type_node , "__builtin_aarch64_rsqrt_v2df" , AARCH64_BUILTIN_RSQRT_V2DF } , { V2SF_type_node , "__builtin_aarch64_rsqrt_v2sf" , AARCH64_BUILTIN_RSQRT_V2SF } , { V4SF_type_node , "__builtin_aarch64_rsqrt_v4sf" , AARCH64_BUILTIN_RSQRT_V4SF } } ; builtin_decls_data * bdd = bdda ; builtin_decls_data * bdd_end = bdd + ( sizeof ( bdda ) / sizeof ( builtin_decls_data ) ) ; for ( ; bdd < bdd_end ; bdd ++ ) { ftype = build_function_type_list ( bdd -> type_node , bdd -> type_node , NULL_TREE ) ; tree attrs = aarch64_get_attributes ( FLAG_FP , TYPE_MODE ( bdd -> type_node ) ) ; fndecl = aarch64_general_add_builtin ( bdd -> builtin_name , ftype , bdd -> function_code , attrs ) ; aarch64_builtin_decls [ bdd -> function_code ] = fndecl ; } } </s>

Add builtins for reciprocal square root .


<s> bool X86TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { for ( const APFloat & FPImm : LegalFPImmediates ) if ( Imm . bitwiseIsEqual ( FPImm ) ) return true ; return false ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> bool ARMInstrInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( ! AFI -> isThumbFunction ( ) || CSI . empty ( ) ) return false ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > 0 ; MachineInstr * PopMI = MF . CreateMachineInstr ( get ( ARM :: tPOP ) , MI -> getDebugLoc ( ) ) ; MBB . insert ( MI , PopMI ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( Reg == ARM :: LR ) { if ( isVarArg ) continue ; Reg = ARM :: PC ; PopMI -> setDesc ( get ( ARM :: tPOP_RET ) ) ; MBB . erase ( MI ) ; } PopMI -> addOperand ( MachineOperand :: CreateReg ( Reg , true ) ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool MipsFastISel :: fastLowerCall ( CallLoweringInfo & CLI ) { CallingConv :: ID CC = CLI . CallConv ; bool IsTailCall = CLI . IsTailCall ; bool IsVarArg = CLI . IsVarArg ; const Value * Callee = CLI . Callee ; if ( IsTailCall ) return false ; if ( IsVarArg ) return false ; MVT RetVT ; if ( CLI . RetTy -> isVoidTy ( ) ) RetVT = MVT :: isVoid ; else if ( ! isTypeLegal ( CLI . RetTy , RetVT ) ) return false ; for ( auto Flag : CLI . OutFlags ) if ( Flag . isInReg ( ) || Flag . isSRet ( ) || Flag . isNest ( ) || Flag . isByVal ( ) ) return false ; SmallVector < MVT , 16 > OutVTs ; OutVTs . reserve ( CLI . OutVals . size ( ) ) ; for ( auto * Val : CLI . OutVals ) { MVT VT ; if ( ! isTypeLegal ( Val -> getType ( ) , VT ) && ! ( VT == MVT :: i1 || VT == MVT :: i8 || VT == MVT :: i16 ) ) return false ; if ( VT . isVector ( ) || VT . getSizeInBits ( ) > 64 ) return false ; OutVTs . push_back ( VT ) ; } Address Addr ; if ( ! computeCallAddress ( Callee , Addr ) ) return false ; unsigned NumBytes ; if ( ! processCallArgs ( CLI , OutVTs , NumBytes ) ) return false ; unsigned DestAddress = materializeGV ( Addr . getGlobalValue ( ) , MVT :: i32 ) ; emitInst ( TargetOpcode :: COPY , Mips :: T9 ) . addReg ( DestAddress ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Mips :: JALR ) , Mips :: RA ) . addReg ( Mips :: T9 ) ; for ( auto Reg : CLI . OutRegs ) MIB . addReg ( Reg , RegState :: Implicit ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( * FuncInfo . MF , CC ) ) ; CLI . Call = MIB ; return finishCall ( CLI , RetVT , NumBytes ) ; } </s>

This method is called by target-independent code to do target- specific call lowering .


<s> bool isToken ( ) const { return Kind == K_Token ; } </s>


<s>
void
MSP430FrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
MSP430MachineFunctionInfo
*
MSP430FI
=
MF
.
getInfo
<
MSP430MachineFunctionInfo
>
(
)
;
const
MSP430InstrInfo
&
TII
=
*
static_cast
<
const
MSP430InstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
DL
=
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
uint64_t
StackSize
=
MFI
.
getStackSize
(
)
;
uint64_t
NumBytes
=
0
;
if
(
hasFP
(
MF
)
)
{
uint64_t
FrameSize
=
StackSize
2
;
NumBytes
=
FrameSize
MSP430FI
->
getCalleeSavedFrameSize
(
)
;
MFI
.
setOffsetAdjustment
(
NumBytes
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
TII
.
get
(
MSP430
::
PUSH16r
)
)
.
addReg
(
MSP430
::
FP
,
RegState
::
Kill
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
TII
.
get
(
MSP430
::
MOV16rr
)
,
MSP430
::
FP
)
.
addReg
(
MSP430
::
SP
)
;
for
(
MachineFunction
::
iterator
I
=
std
::
next
(
MF
.
begin
(
)
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
I
->
addLiveIn
(
MSP430
::
FP
)
;
}
else
NumBytes
=
StackSize
MSP430FI
->
getCalleeSavedFrameSize
(
)
;
while
(
MBBI
!=
MBB
.
end
(
)
&&
(
MBBI
->
getOpcode
(
)
==
MSP430
::
PUSH16r
)
)
++
MBBI
;
if
(
MBBI
!=
MBB
.
end
(
)
)
DL
=
MBBI
->
getDebugLoc
(
)
;
if
(
NumBytes
)
{
if
(
NumBytes
)
{
MachineInstr
*
MI
=
BuildMI
(
MBB
,
MBBI
,
DL
,
TII
.
get
(
MSP430
::
SUB16ri
)
,
MSP430
::
SP
)
.
addReg
(
MSP430
::
SP
)
.
addImm
(
NumBytes
)
;
MI
->
getOperand
(
3
)
.
setIsDead
(
)
;
}
}
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static Align getPrefTypeAlign ( EVT VT , SelectionDAG & DAG ) { return DAG . getDataLayout ( ) . getPrefTypeAlign ( VT . getTypeForEVT ( * DAG . getContext ( ) ) ) ; } </s>

Returns the preferred stack/global alignment for the specified type .


<s>
MachineInstrBuilder
R600InstrInfo
::
buildIndirectWrite
(
MachineBasicBlock
*
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
ValueReg
,
unsigned
Address
,
unsigned
OffsetReg
,
unsigned
AddrChan
)
const
{
unsigned
AddrReg
;
switch
(
AddrChan
)
{
default
:
llvm_unreachable
(
"Invalid Channel"
)
;
case
0
:
AddrReg
=
AMDGPU
::
R600_AddrRegClass
.
getRegister
(
Address
)
;
break
;
case
1
:
AddrReg
=
AMDGPU
::
R600_Addr_YRegClass
.
getRegister
(
Address
)
;
break
;
case
2
:
AddrReg
=
AMDGPU
::
R600_Addr_ZRegClass
.
getRegister
(
Address
)
;
break
;
case
3
:
AddrReg
=
AMDGPU
::
R600_Addr_WRegClass
.
getRegister
(
Address
)
;
break
;
}
MachineInstr
*
MOVA
=
buildDefaultInstruction
(
*
MBB
,
I
,
AMDGPU
::
MOVA_INT_eg
,
AMDGPU
::
AR_X
,
OffsetReg
)
;
setImmOperand
(
*
MOVA
,
AMDGPU
::
OpName
::
write
,
0
)
;
MachineInstrBuilder
Mov
=
buildDefaultInstruction
(
*
MBB
,
I
,
AMDGPU
::
MOV
,
AddrReg
,
ValueReg
)
.
addReg
(
AMDGPU
::
AR_X
,
RegState
::
Implicit
|
RegState
::
Kill
)
;
setImmOperand
(
*
Mov
,
AMDGPU
::
OpName
::
dst_rel
,
1
)
;
return
Mov
;
}
</s>

Build instruction ( s ) for an indirect register write .


<s> static void ix86_add_reg_usage_to_vzeroupper ( rtx_insn * insn , bitmap live_regs ) { rtx pattern = PATTERN ( insn ) ; unsigned int nregs = TARGET_64BIT ? 16 : 8 ; unsigned int npats = nregs ; for ( unsigned int i = 0 ; i < nregs ; ++ i ) { unsigned int regno = GET_SSE_REGNO ( i ) ; if ( ! bitmap_bit_p ( live_regs , regno ) ) npats -- ; } if ( npats == 0 ) return ; rtvec vec = rtvec_alloc ( npats + 1 ) ; RTVEC_ELT ( vec , 0 ) = XVECEXP ( pattern , 0 , 0 ) ; for ( unsigned int i = 0 , j = 0 ; i < nregs ; ++ i ) { unsigned int regno = GET_SSE_REGNO ( i ) ; if ( ! bitmap_bit_p ( live_regs , regno ) ) continue ; rtx reg = gen_rtx_REG ( V2DImode , regno ) ; ++ j ; RTVEC_ELT ( vec , j ) = gen_rtx_SET ( reg , reg ) ; } XVEC ( pattern , 0 ) = vec ; INSN_CODE ( insn ) = - 1 ; df_insn_rescan ( insn ) ; } </s>

Modify the vzeroupper pattern in INSN so that it describes the effect that the instruction has on the SSE registers . LIVE_REGS are the set of registers that are live across the instruction . For a live register R we use : ( set ( reg : V2DF R ) ( reg : V2DF R ) ) which preserves the low 128 bits but clobbers the upper bits .


"\nrs6000_rtx_costs, return = %s, code = %s, outer_code = %s, "

"opno = %d, total = %d, speed = %s, x:\n"

Debug form of r6000_rtx_costs that is selected if -mdebug=cost .


<s> static int ix86_initialize_bounds ( tree var , tree lb , tree ub , tree * stmts ) { tree bnd_ptr = build_pointer_type ( pointer_sized_int_node ) ; tree lhs , modify , var_p ; ub = build1 ( BIT_NOT_EXPR , pointer_sized_int_node , ub ) ; var_p = fold_convert ( bnd_ptr , build_fold_addr_expr ( var ) ) ; lhs = build1 ( INDIRECT_REF , pointer_sized_int_node , var_p ) ; modify = build2 ( MODIFY_EXPR , TREE_TYPE ( lhs ) , lhs , lb ) ; append_to_statement_list ( modify , stmts ) ; lhs = build1 ( INDIRECT_REF , pointer_sized_int_node , build2 ( POINTER_PLUS_EXPR , bnd_ptr , var_p , TYPE_SIZE_UNIT ( pointer_sized_int_node ) ) ) ; modify = build2 ( MODIFY_EXPR , TREE_TYPE ( lhs ) , lhs , ub ) ; append_to_statement_list ( modify , stmts ) ; return 2 ; } </s>

Generate a list of statements STMTS to initialize pointer bounds variable VAR with bounds LB and UB . Return the number of generated statements .


<s> void RISCVFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( hasFP ( MF ) ) { if ( RISCVABI :: isCheriPureCapABI ( STI . getTargetABI ( ) ) ) { SavedRegs . set ( RISCV :: C1 ) ; SavedRegs . set ( RISCV :: C8 ) ; } else { SavedRegs . set ( RISCV :: X1 ) ; SavedRegs . set ( RISCV :: X8 ) ; } } if ( hasBP ( MF ) ) SavedRegs . set ( RISCVABI :: getBPReg ( STI . getTargetABI ( ) ) ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MF . getFunction ( ) . hasFnAttribute ( "interrupt" ) && MFI . hasCalls ( ) ) { static const MCPhysReg CSGPRs [ ] = { RISCV :: X1 , RISCV :: X5 , RISCV :: X6 , RISCV :: X7 , RISCV :: X10 , RISCV :: X11 , RISCV :: X12 , RISCV :: X13 , RISCV :: X14 , RISCV :: X15 , RISCV :: X16 , RISCV :: X17 , RISCV :: X28 , RISCV :: X29 , RISCV :: X30 , RISCV :: X31 , 0 } ; static const MCPhysReg CSGPCRs [ ] = { RISCV :: C1 , RISCV :: C5 , RISCV :: C6 , RISCV :: C7 , RISCV :: C10 , RISCV :: C11 , RISCV :: C12 , RISCV :: C13 , RISCV :: C14 , RISCV :: C15 , RISCV :: C16 , RISCV :: C17 , RISCV :: C28 , RISCV :: C29 , RISCV :: C30 , RISCV :: C31 , 0 } ; ArrayRef < MCPhysReg > CSRegs ; if ( RISCVABI :: isCheriPureCapABI ( STI . getTargetABI ( ) ) ) CSRegs = CSGPCRs ; else CSRegs = CSGPRs ; for ( unsigned i = 0 ; CSRegs [ i ] ; ++ i ) SavedRegs . set ( CSRegs [ i ] ) ; if ( MF . getSubtarget < RISCVSubtarget > ( ) . hasStdExtF ( ) ) { const MCPhysReg * Regs = MF . getRegInfo ( ) . getCalleeSavedRegs ( ) ; for ( unsigned i = 0 ; Regs [ i ] ; ++ i ) if ( RISCV :: FPR16RegClass . contains ( Regs [ i ] ) || RISCV :: FPR32RegClass . contains ( Regs [ i ] ) || RISCV :: FPR64RegClass . contains ( Regs [ i ] ) ) SavedRegs . set ( Regs [ i ] ) ; } } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s>
StringRef
getPassName
(
)
const
override
{
return
"AArch64 Condition Optimizer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void HexagonMCELFStreamer :: emitInstruction ( const MCInst & MCB , const MCSubtargetInfo & STI ) { assert ( MCB . getOpcode ( ) == Hexagon :: BUNDLE ) ; assert ( HexagonMCInstrInfo :: bundleSize ( MCB ) <= HEXAGON_PACKET_SIZE ) ; assert ( HexagonMCInstrInfo :: bundleSize ( MCB ) > 0 ) ; for ( auto const & I : HexagonMCInstrInfo :: bundleInstructions ( MCB ) ) { MCInst * MCI = const_cast < MCInst * > ( I . getInst ( ) ) ; EmitSymbol ( * MCI ) ; } MCObjectStreamer :: emitInstruction ( MCB , STI ) ; } </s>

Targets should implement this to emit instructions .

Hexagon Hexagon Hexagon::BUNDLE Hexagon Hexagon 0 Hexagon


<s> void X86PassConfig :: addPreEmitPass2 ( ) { addPass ( createX86RetpolineThunksPass ( ) ) ; const Triple & TT = TM -> getTargetTriple ( ) ; const MCAsmInfo * MAI = TM -> getMCAsmInfo ( ) ; if ( ! TT . isOSDarwin ( ) && ( ! TT . isOSWindows ( ) || MAI -> getExceptionHandlingType ( ) == ExceptionHandling :: DwarfCFI ) ) addPass ( createCFIInstrInserter ( ) ) ; } </s>

Targets may add passes immediately before machine code is emitted in this callback .


<s> void bfin_expand_prologue ( void ) { HOST_WIDE_INT frame_size = get_frame_size ( ) ; rtx spreg = gen_rtx_REG ( Pmode , REG_SP ) ; e_funkind fkind = funkind ( TREE_TYPE ( current_function_decl ) ) ; rtx pic_reg_loaded = NULL_RTX ; tree attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ; bool all = lookup_attribute ( "saveall" , attrs ) != NULL_TREE ; if ( flag_stack_usage_info ) current_function_static_stack_size = frame_size ; if ( fkind != SUBROUTINE ) { expand_interrupt_handler_prologue ( spreg , fkind , all ) ; return ; } if ( crtl -> limit_stack || ( TARGET_STACK_CHECK_L1 && ! DECL_NO_LIMIT_STACK ( current_function_decl ) ) ) { HOST_WIDE_INT offset = bfin_initial_elimination_offset ( ARG_POINTER_REGNUM , STACK_POINTER_REGNUM ) ; rtx lim = crtl -> limit_stack ? stack_limit_rtx : NULL_RTX ; rtx tmp = gen_rtx_REG ( Pmode , REG_R3 ) ; rtx p2reg = gen_rtx_REG ( Pmode , REG_P2 ) ; emit_move_insn ( tmp , p2reg ) ; if ( ! lim ) { emit_move_insn ( p2reg , gen_int_mode ( 0xFFB00000 , SImode ) ) ; emit_move_insn ( p2reg , gen_rtx_MEM ( Pmode , p2reg ) ) ; lim = p2reg ; } if ( GET_CODE ( lim ) == SYMBOL_REF ) { if ( TARGET_ID_SHARED_LIBRARY ) { rtx p1reg = gen_rtx_REG ( Pmode , REG_P1 ) ; rtx val ; pic_reg_loaded = bfin_load_pic_reg ( p2reg ) ; val = legitimize_pic_address ( stack_limit_rtx , p1reg , pic_reg_loaded ) ; emit_move_insn ( p1reg , val ) ; frame_related_constant_load ( p2reg , offset , FALSE ) ; emit_insn ( gen_addsi3 ( p2reg , p2reg , p1reg ) ) ; lim = p2reg ; } else { rtx limit = plus_constant ( Pmode , lim , offset ) ; emit_move_insn ( p2reg , limit ) ; lim = p2reg ; } } else { if ( lim != p2reg ) emit_move_insn ( p2reg , lim ) ; add_to_reg ( p2reg , offset , 0 , 0 ) ; lim = p2reg ; } emit_insn ( gen_compare_lt ( bfin_cc_rtx , spreg , lim ) ) ; emit_insn ( gen_trapifcc ( ) ) ; emit_move_insn ( p2reg , tmp ) ; } expand_prologue_reg_save ( spreg , all , false ) ; do_link ( spreg , frame_size , all ) ; if ( TARGET_ID_SHARED_LIBRARY && ! TARGET_SEP_DATA && ( crtl -> uses_pic_offset_table || ! crtl -> is_leaf ) ) bfin_load_pic_reg ( pic_offset_table_rtx ) ; } </s>

Generate RTL for the prologue of the current function .


<s> virtual const X86RegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool nvptx_hard_regno_mode_ok ( int regno , machine_mode mode ) { if ( regno != NVPTX_RETURN_REGNUM || cfun == NULL || cfun -> machine -> ret_reg_mode == VOIDmode ) return true ; return mode == cfun -> machine -> ret_reg_mode ; } </s>

Implement HARD_REGNO_MODE_OK . We barely use hard regs , but we want to ensure that the return register 's mode is n't changed .


<s> static rtx ft32_function_value ( const_tree valtype , const_tree fntype_or_decl ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( TYPE_MODE ( valtype ) , FT32_R0 ) ; } </s>

Define how to find the value returned by a function . VALTYPE is the data type of the value ( as a tree ) . If the precise function being called is known , FUNC is its FUNCTION_DECL ; otherwise , FUNC is 0 . We always return values in register $ r0 for ft32 .


"XCore DAG->DAG Pattern Instruction Selection"


<s> void RISCVPassConfig :: addPreEmitPass2 ( ) { addPass ( createRISCVExpandPseudoPass ( ) ) ; addPass ( createRISCVExpandAtomicPseudoPass ( ) ) ; } </s>


<s> static bool tryAddingSymbolicOperand ( int64_t Value , bool IsBranch , uint64_t Address , uint64_t Offset , uint64_t Width , MCInst & MI , const void * Decoder ) { const MCDisassembler * Dis = static_cast < const MCDisassembler * > ( Decoder ) ; return Dis -> tryAddingSymbolicOperand ( MI , Value , Address , IsBranch , Offset , Width ) ; } </s>

Try to add a symbolic operand instead of Value to the MCInst .


<s> bool ix86_pre_reload_split ( void ) { return ( can_create_pseudo_p ( ) && ! ( cfun -> curr_properties & PROP_rtl_split_insns ) ) ; } </s>

Predicate for pre-reload splitters with associated instructions , which can match any time before the split1 pass ( usually combine ) , then are unconditionally split in that pass and should not be matched again afterwards .


<s>
StringRef
getPassName
(
)
const
override
{
return
"AMDGPU IR optimizations"
;
}
</s>


<s> static rtx mt_check_delay_slot ( rtx branch , rtx insn ) { rtx slot ; rtx tmp ; rtx p ; rtx jmp ; gcc_assert ( GET_CODE ( PATTERN ( branch ) ) == SEQUENCE ) ; if ( INSN_DELETED_P ( branch ) ) return NULL_RTX ; slot = XVECEXP ( PATTERN ( branch ) , 0 , 1 ) ; tmp = PATTERN ( insn ) ; note_stores ( PATTERN ( slot ) , insn_dependent_p_1 , & tmp ) ; if ( tmp ) return NULL_RTX ; jmp = XVECEXP ( PATTERN ( branch ) , 0 , 0 ) ; tmp = PATTERN ( jmp ) ; note_stores ( PATTERN ( slot ) , insn_dependent_p_1 , & tmp ) ; if ( ! tmp ) return branch ; p = PREV_INSN ( branch ) ; NEXT_INSN ( p ) = slot ; PREV_INSN ( slot ) = p ; NEXT_INSN ( slot ) = jmp ; PREV_INSN ( jmp ) = slot ; NEXT_INSN ( jmp ) = branch ; PREV_INSN ( branch ) = jmp ; XVECEXP ( PATTERN ( branch ) , 0 , 0 ) = NULL_RTX ; XVECEXP ( PATTERN ( branch ) , 0 , 1 ) = NULL_RTX ; delete_insn ( branch ) ; return jmp ; } </s>

If BRANCH has a filled delay slot , check if INSN is dependent upon it . If so , undo the delay slot fill . Returns the next insn , if we patch out the branch . Returns the branch insn , if we can not patch out the branch ( due to anti-dependency in the delay slot ) . In that case , the caller must insert nops at the branch target .


<s>
SDValue
XCoreTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
CALL
:
return
LowerCALL
(
Op
,
DAG
)
;
case
ISD
::
FORMAL_ARGUMENTS
:
return
LowerFORMAL_ARGUMENTS
(
Op
,
DAG
)
;
case
ISD
::
RET
:
return
LowerRET
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
VAARG
:
return
LowerVAARG
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
ADD
:
case
ISD
::
SUB
:
return
ExpandADDSUB
(
Op
.
getNode
(
)
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
default
:
assert
(
0
&&
"unimplemented operand"
)
;
return
SDValue
(
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

XCore
XCore
ISD::CALL
ISD::FORMAL_ARGUMENTS
ISD::RET
ISD::GlobalAddress
ISD::GlobalTLSAddress
ISD::ConstantPool
ISD::JumpTable
ISD::SELECT_CC
ISD::VAARG
ISD::VASTART
ISD::ADD
ISD::SUB
ISD::FRAMEADDR
0
"unimplemented operand"