<s>
bool
X86CmovConverterPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
if
(
!
EnableCmovConverter
)
return
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"********** "
<<
getPassName
(
)
<<
" : "
<<
MF
.
getName
(
)
<<
"**********\n"
)
;
bool
Changed
=
false
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
const
TargetSubtargetInfo
&
STI
=
MF
.
getSubtarget
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
TII
=
STI
.
getInstrInfo
(
)
;
TRI
=
STI
.
getRegisterInfo
(
)
;
TSchedModel
.
init
(
&
STI
)
;
if
(
ForceMemOperand
)
{
CmovGroups
AllCmovGroups
;
SmallVector
<
MachineBasicBlock
*
,
4
>
Blocks
;
for
(
auto
&
MBB
:
MF
)
Blocks
.
push_back
(
&
MBB
)
;
if
(
collectCmovCandidates
(
Blocks
,
AllCmovGroups
,
true
)
)
{
for
(
auto
&
Group
:
AllCmovGroups
)
{
if
(
!
llvm
::
any_of
(
Group
,
[
&
]
(
MachineInstr
*
I
)
{
return
I
->
mayLoad
(
)
;
}
)
)
continue
;
Changed
=
true
;
convertCmovInstsToBranches
(
Group
)
;
}
}
}
SmallVector
<
MachineLoop
*
,
4
>
Loops
(
MLI
->
begin
(
)
,
MLI
->
end
(
)
)
;
for
(
int
i
=
0
;
i
<
(
int
)
Loops
.
size
(
)
;
++
i
)
for
(
MachineLoop
*
Child
:
Loops
[
i
]
->
getSubLoops
(
)
)
Loops
.
push_back
(
Child
)
;
for
(
MachineLoop
*
CurrLoop
:
Loops
)
{
if
(
!
CurrLoop
->
getSubLoops
(
)
.
empty
(
)
)
continue
;
CmovGroups
CmovInstGroups
;
if
(
!
collectCmovCandidates
(
CurrLoop
->
getBlocks
(
)
,
CmovInstGroups
)
)
continue
;
if
(
!
checkForProfitableCmovCandidates
(
CurrLoop
->
getBlocks
(
)
,
CmovInstGroups
)
)
continue
;
Changed
=
true
;
for
(
auto
&
Group
:
CmovInstGroups
)
convertCmovInstsToBranches
(
Group
)
;
}
return
Changed
;
}
</s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"AMDGPU IR late optimizations"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void PPCFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - 1 ; bool DisableRedZone = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoRedZone ) ; if ( ! DisableRedZone && ( Subtarget . isPPC64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == 0 ) && FrameSize <= 224 && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! ( Subtarget . isPPC64 ( ) && Subtarget . isSVR4ABI ( ) && spillsCR ( MF ) ) && ( ! ALIGN_STACK || MaxAlign <= TargetAlign ) ) { MFI -> setStackSize ( 0 ) ; return ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getMinCallFrameSize ( Subtarget . isPPC64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; MFI -> setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s> int zap_mask ( HOST_WIDE_INT value ) { int i ; for ( i = 0 ; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR ; i ++ , value >>= 8 ) if ( ( value & 0xff ) != 0 && ( value & 0xff ) != 0xff ) return 0 ; return 1 ; } </s>

Returns 1 if VALUE is a mask that contains full bytes of zero or ones .


<s> static std :: string getGraphName ( const ScheduleDAG * G ) { return G -> MF . getName ( ) . str ( ) ; } </s>

Generate a title for the graph in DOT format .


<s> virtual const TargetFrameInfo * getFrameInfo ( ) const { return & FrameInfo ; } </s>

getFrameInfo - Return the frame info object for the current function .


<s> void reset ( ) { Inst2Replace = nullptr ; BackedgeInst = nullptr ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s>
void
ARMTTIImpl
::
getUnrollingPreferences
(
Loop
*
L
,
ScalarEvolution
&
SE
,
TTI
::
UnrollingPreferences
&
UP
)
{
if
(
!
ST
->
isMClass
(
)
)
return
BasicTTIImplBase
::
getUnrollingPreferences
(
L
,
SE
,
UP
)
;
UP
.
OptSizeThreshold
=
0
;
UP
.
PartialOptSizeThreshold
=
0
;
if
(
L
->
getHeader
(
)
->
getParent
(
)
->
optForSize
(
)
)
return
;
if
(
!
ST
->
isThumb2
(
)
)
return
;
SmallVector
<
BasicBlock
*
,
4
>
ExitingBlocks
;
L
->
getExitingBlocks
(
ExitingBlocks
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Loop has:\n"
<<
"Blocks: "
<<
L
->
getNumBlocks
(
)
<<
"\n"
<<
"Exit blocks: "
<<
ExitingBlocks
.
size
(
)
<<
"\n"
)
;
if
(
ExitingBlocks
.
size
(
)
>
2
)
return
;
if
(
ST
->
hasBranchPredictor
(
)
&&
L
->
getNumBlocks
(
)
>
4
)
return
;
unsigned
Cost
=
0
;
for
(
auto
*
BB
:
L
->
getBlocks
(
)
)
{
for
(
auto
&
I
:
*
BB
)
{
if
(
isa
<
CallInst
>
(
I
)
||
isa
<
InvokeInst
>
(
I
)
)
{
ImmutableCallSite
CS
(
&
I
)
;
if
(
const
Function
*
F
=
CS
.
getCalledFunction
(
)
)
{
if
(
!
isLoweredToCall
(
F
)
)
continue
;
}
return
;
}
SmallVector
<
const
Value
*
,
4
>
Operands
(
I
.
value_op_begin
(
)
,
I
.
value_op_end
(
)
)
;
Cost
+=
getUserCost
(
&
I
,
Operands
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Cost of loop: "
<<
Cost
<<
"\n"
)
;
UP
.
Partial
=
true
;
UP
.
Runtime
=
true
;
UP
.
UnrollRemainder
=
true
;
UP
.
DefaultUnrollRuntimeCount
=
4
;
UP
.
UnrollAndJam
=
true
;
UP
.
UnrollAndJamInnerLoopThreshold
=
60
;
if
(
Cost
<
12
)
UP
.
Force
=
true
;
}
</s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> bool mips_legitimize_move ( machine_mode mode , rtx dest , rtx src ) { if ( ! register_operand ( dest , mode ) && ! register_operand ( src , mode ) && ( TARGET_MIPS16 || ! const_0_operand ( src , mode ) || MSA_SUPPORTED_MODE_P ( mode ) ) ) { mips_emit_move ( dest , force_reg ( mode , src ) ) ; return true ; } if ( CONSTANT_P ( src ) && ! move_operand ( src , mode ) ) { mips_legitimize_const_move ( mode , dest , src ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , copy_rtx ( src ) ) ; return true ; } return false ; } </s>

If ( set DEST SRC ) is not a valid instruction , emit an equivalent sequence that is valid .


<s> bool AMDGPUPassConfig :: addPreSched2 ( ) { const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) addPass ( createR600EmitClauseMarkers ( ) ) ; if ( ST . isIfCvtEnabled ( ) ) addPass ( & IfConverterID ) ; if ( ST . getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) addPass ( createR600ClauseMergePass ( * TM ) ) ; return false ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s>
bool
MOSCallLowering
::
lowerCall
(
MachineIRBuilder
&
MIRBuilder
,
CallLoweringInfo
&
Info
)
const
{
if
(
Info
.
IsMustTailCall
)
report_fatal_error
(
"Musttail calls not supported."
)
;
MachineFunction
&
MF
=
MIRBuilder
.
getMF
(
)
;
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
const
DataLayout
&
DL
=
MF
.
getDataLayout
(
)
;
const
TargetRegisterInfo
&
TRI
=
*
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
bool
IsIndirect
=
Info
.
Callee
.
isReg
(
)
;
if
(
IsIndirect
)
{
MIRBuilder
.
buildCopy
(
MOS
::
RS9
,
Info
.
Callee
)
;
Info
.
Callee
.
ChangeToES
(
"__call_indir"
)
;
}
auto
CallSeqStart
=
MIRBuilder
.
buildInstr
(
MOS
::
ADJCALLSTACKDOWN
)
;
auto
Call
=
MIRBuilder
.
buildInstrNoInsert
(
MOS
::
JSR
)
.
add
(
Info
.
Callee
)
.
addRegMask
(
TRI
.
getCallPreservedMask
(
MF
,
Info
.
CallConv
)
)
;
if
(
IsIndirect
)
Call
.
addUse
(
MOS
::
RS9
,
RegState
::
Implicit
)
;
SmallVector
<
ArgInfo
,
8
>
OutArgs
;
for
(
auto
&
OrigArg
:
Info
.
OrigArgs
)
{
splitToValueTypes
(
OrigArg
,
OutArgs
,
DL
)
;
}
SmallVector
<
ArgInfo
,
8
>
InArgs
;
if
(
!
Info
.
OrigRet
.
Ty
->
isVoidTy
(
)
)
splitToValueTypes
(
Info
.
OrigRet
,
InArgs
,
DL
)
;
MOSOutgoingArgsHandler
ArgsHandler
(
MIRBuilder
,
Call
,
MRI
)
;
MOSValueAssigner
ArgsAssigner
(
false
,
MRI
,
MF
)
;
if
(
!
determineAndHandleAssignments
(
ArgsHandler
,
ArgsAssigner
,
OutArgs
,
MIRBuilder
,
Info
.
CallConv
,
Info
.
IsVarArg
)
)
return
false
;
MIRBuilder
.
insertInstr
(
Call
)
;
uint64_t
StackSize
=
ArgsAssigner
.
StackOffset
;
if
(
!
Info
.
OrigRet
.
Ty
->
isVoidTy
(
)
)
{
MOSIncomingReturnHandler
RetHandler
(
MIRBuilder
,
MRI
,
Call
)
;
MOSValueAssigner
RetAssigner
(
true
,
MRI
,
MF
)
;
if
(
!
determineAndHandleAssignments
(
RetHandler
,
RetAssigner
,
InArgs
,
MIRBuilder
,
Info
.
CallConv
,
Info
.
IsVarArg
)
)
return
false
;
StackSize
=
std
::
max
(
StackSize
,
RetAssigner
.
StackOffset
)
;
}
CallSeqStart
.
addImm
(
StackSize
)
.
addImm
(
0
)
;
MIRBuilder
.
buildInstr
(
MOS
::
ADJCALLSTACKUP
)
.
addImm
(
StackSize
)
.
addImm
(
0
)
;
return
true
;
}
</s>

This hook must be implemented to lower the given call instruction , including argument and return value marshalling .


"LowerFormalArguments Unhandled argument type: "

"functions with VarArgs or StructRet are not supported"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> const TargetRegisterClass * Z80RegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & ) const { const TargetRegisterClass * Super = RC ; TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case Z80 :: R8RegClassID : case Z80 :: R16RegClassID : case Z80 :: R24RegClassID : return Super ; } Super = * I ++ ; } while ( Super ) ; return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .


<s> SMLoc getEndLoc ( ) const { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> static bool riscv_legitimate_address_p ( machine_mode mode , rtx x , bool strict_p ) { struct riscv_address_info addr ; return riscv_classify_address ( & addr , x , mode , strict_p ) ; } </s>


<s> const char * XCoreTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case XCoreISD :: BL : return "XCoreISD::BL" ; case XCoreISD :: PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper" ; case XCoreISD :: DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper" ; case XCoreISD :: CPRelativeWrapper : return "XCoreISD::CPRelativeWrapper" ; case XCoreISD :: STWSP : return "XCoreISD::STWSP" ; case XCoreISD :: RETSP : return "XCoreISD::RETSP" ; case XCoreISD :: LADD : return "XCoreISD::LADD" ; case XCoreISD :: LSUB : return "XCoreISD::LSUB" ; case XCoreISD :: LMUL : return "XCoreISD::LMUL" ; case XCoreISD :: MACCU : return "XCoreISD::MACCU" ; case XCoreISD :: MACCS : return "XCoreISD::MACCS" ; case XCoreISD :: BR_JT : return "XCoreISD::BR_JT" ; case XCoreISD :: BR_JT32 : return "XCoreISD::BR_JT32" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific

XCore XCore XCoreISD::BL "XCoreISD::BL" XCoreISD::PCRelativeWrapper "XCoreISD::PCRelativeWrapper" XCoreISD::DPRelativeWrapper "XCoreISD::DPRelativeWrapper" XCoreISD::CPRelativeWrapper "XCoreISD::CPRelativeWrapper" XCoreISD::STWSP "XCoreISD::STWSP" XCoreISD::RETSP "XCoreISD::RETSP" XCoreISD::LADD "XCoreISD::LADD" XCoreISD::LSUB "XCoreISD::LSUB" XCoreISD::LMUL "XCoreISD::LMUL" XCoreISD::MACCU "XCoreISD::MACCU" XCoreISD::MACCS "XCoreISD::MACCS" XCoreISD::BR_JT "XCoreISD::BR_JT" XCoreISD::BR_JT32 "XCoreISD::BR_JT32"


<s> void SparcFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr & MI = * I ; int Size = MI . getOperand ( 0 ) . getImm ( ) ; if ( MI . getOpcode ( ) == SP :: ADJCALLSTACKDOWN ) Size = - Size ; if ( Size ) emitSPAdjustment ( MF , MBB , I , Size , SP :: ADDrr , SP :: ADDri ) ; } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

Sparc Sparc 0 SP::ADJCALLSTACKDOWN SP SP::ADDrr SP::ADDri


<s> void SystemZInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned LoadOpcode , StoreOpcode ; getLoadStoreOpcodes ( RC , LoadOpcode , StoreOpcode ) ; addFrameReference ( BuildMI ( MBB , MBBI , DL , get ( LoadOpcode ) , DestReg ) , FrameIdx ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s>
void
AAPFrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
MachineFrameInfo
&
MFrameInfo
=
MF
.
getFrameInfo
(
)
;
AAPMachineFunctionInfo
*
MFuncInfo
=
MF
.
getInfo
<
AAPMachineFunctionInfo
>
(
)
;
const
AAPInstrInfo
&
TII
=
*
static_cast
<
const
AAPInstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
auto
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
DL
=
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
const
uint64_t
StackSize
=
MFrameInfo
.
getStackSize
(
)
;
assert
(
!
hasFP
(
MF
)
&&
"Frame pointer unsupported!"
)
;
uint64_t
NumBytes
=
StackSize
MFuncInfo
->
getCalleeSavedFrameSize
(
)
;
const
unsigned
SP
=
AAPRegisterInfo
::
getStackPtrRegister
(
)
;
if
(
NumBytes
)
{
const
uint64_t
Addend
=
NumBytes
%
1023
;
const
uint64_t
NumChunks
=
NumBytes
/
1023
;
for
(
uint64_t
i
=
0
;
i
<
NumChunks
;
++
i
)
{
BuildMI
(
MBB
,
MBBI
,
DL
,
TII
.
get
(
AAP
::
SUBI_i10
)
,
SP
)
.
addReg
(
SP
)
.
addImm
(
1023
)
;
}
if
(
Addend
)
{
BuildMI
(
MBB
,
MBBI
,
DL
,
TII
.
get
(
AAP
::
SUBI_i10
)
,
SP
)
.
addReg
(
SP
)
.
addImm
(
Addend
)
;
}
}
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s>
bool
ARMLowOverheadLoops
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
const
ARMSubtarget
&
ST
=
static_cast
<
const
ARMSubtarget
&
>
(
mf
.
getSubtarget
(
)
)
;
if
(
!
ST
.
hasLOB
(
)
)
return
false
;
MF
=
&
mf
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM Loops on "
<<
MF
->
getName
(
)
<<
" ------------- \n"
)
;
auto
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
MF
->
getProperties
(
)
.
set
(
MachineFunctionProperties
::
Property
::
TracksLiveness
)
;
MRI
=
&
MF
->
getRegInfo
(
)
;
TII
=
static_cast
<
const
ARMBaseInstrInfo
*
>
(
ST
.
getInstrInfo
(
)
)
;
BBUtils
=
std
::
unique_ptr
<
ARMBasicBlockUtils
>
(
new
ARMBasicBlockUtils
(
*
MF
)
)
;
BBUtils
->
computeAllBlockSizes
(
)
;
BBUtils
->
adjustBBOffsetsAfter
(
&
MF
->
front
(
)
)
;
bool
Changed
=
false
;
for
(
auto
ML
:
MLI
)
{
if
(
!
ML
->
getParentLoop
(
)
)
Changed
|=
ProcessLoop
(
ML
)
;
}
Changed
|=
RevertNonLoops
(
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

ARM
ARM
ARM
ARM
"ARM Loops on "
" ------------- \n"
ARM
ARM
ARM


<s> TargetLowering :: ConstraintWeight BlackfinTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'a' : case 'd' : case 'z' : case 'D' : case 'W' : case 'e' : case 'b' : case 'v' : case 'f' : case 'c' : case 't' : case 'u' : case 'k' : case 'x' : case 'y' : case 'w' : return CW_Register ; case 'A' : case 'B' : case 'C' : case 'Z' : case 'Y' : return CW_SpecificReg ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> void JVMFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


<s> bool AArch64InstPrinter :: applyTargetSpecificCLOption ( StringRef Opt ) { if ( Opt == "no-aliases" ) { PrintAliases = false ; return true ; } return false ; } </s>

Customize the printer according to a command line option .


Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> int rs6000_store_data_bypass_p ( rtx_insn * out_insn , rtx_insn * in_insn ) { rtx out_set , in_set ; rtx out_pat , in_pat ; rtx out_exp , in_exp ; int i , j ; in_set = single_set ( in_insn ) ; if ( in_set ) { if ( MEM_P ( SET_DEST ( in_set ) ) ) { out_set = single_set ( out_insn ) ; if ( ! out_set ) { out_pat = PATTERN ( out_insn ) ; if ( GET_CODE ( out_pat ) == PARALLEL ) { for ( i = 0 ; i < XVECLEN ( out_pat , 0 ) ; i ++ ) { out_exp = XVECEXP ( out_pat , 0 , i ) ; if ( ( GET_CODE ( out_exp ) == CLOBBER ) || ( GET_CODE ( out_exp ) == USE ) ) continue ; else if ( GET_CODE ( out_exp ) != SET ) return false ; } } } } } else { in_pat = PATTERN ( in_insn ) ; if ( GET_CODE ( in_pat ) != PARALLEL ) return false ; for ( i = 0 ; i < XVECLEN ( in_pat , 0 ) ; i ++ ) { in_exp = XVECEXP ( in_pat , 0 , i ) ; if ( ( GET_CODE ( in_exp ) == CLOBBER ) || ( GET_CODE ( in_exp ) == USE ) ) continue ; else if ( GET_CODE ( in_exp ) != SET ) return false ; if ( MEM_P ( SET_DEST ( in_exp ) ) ) { out_set = single_set ( out_insn ) ; if ( ! out_set ) { out_pat = PATTERN ( out_insn ) ; if ( GET_CODE ( out_pat ) != PARALLEL ) return false ; for ( j = 0 ; j < XVECLEN ( out_pat , 0 ) ; j ++ ) { out_exp = XVECEXP ( out_pat , 0 , j ) ; if ( ( GET_CODE ( out_exp ) == CLOBBER ) || ( GET_CODE ( out_exp ) == USE ) ) continue ; else if ( GET_CODE ( out_exp ) != SET ) return false ; } } } } } return store_data_bypass_p ( out_insn , in_insn ) ; } </s>

Given that there exists at least one variable that is set ( produced ) by OUT_INSN and read ( consumed ) by IN_INSN , return true iff IN_INSN represents one or more memory store operations and none of the variables set by OUT_INSN is used by IN_INSN as the address of a store operation . If either IN_INSN or OUT_INSN does not represent a `` single '' RTL SET expression ( as loosely defined by the implementation of the single_set function ) or a PARALLEL with only SETs , CLOBBERs , and USEs inside , this function returns false . This rs6000-specific version of store_data_bypass_p checks for certain conditions that result in assertion failures ( and internal compiler errors ) in the generic store_data_bypass_p function and returns false rather than calling store_data_bypass_p if one of the problematic conditions is detected .


"Should be saving %r15 and something else"

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static void emit_store_conditional ( machine_mode mode , rtx mem , rtx val ) { gcc_assert ( mode == SImode ) ; emit_insn ( gen_store_conditional_si ( mem , val ) ) ; } </s>

A subroutine of the atomic operation splitters . Emit a store-conditional instruction in MODE .


<s> static bool branch_to_delay_slot_p ( rtx_insn * insn ) { rtx_insn * jump_insn ; if ( dbr_sequence_length ( ) ) return FALSE ; jump_insn = next_active_insn ( JUMP_LABEL ( insn ) ) ; while ( insn ) { insn = next_active_insn ( insn ) ; if ( jump_insn == insn ) return TRUE ; if ( ! insn || GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT || extract_asm_operands ( PATTERN ( insn ) ) != NULL_RTX || get_attr_length ( insn ) > 0 ) break ; } return FALSE ; } </s>

Return TRUE if INSN , a jump insn , has an unfilled delay slot and it branches into the delay slot . Otherwise , return FALSE .


<s> static int ix86_fp_comparison_arithmetics_cost ( enum rtx_code code ) { if ( ! TARGET_IEEE_FP ) return 4 ; switch ( code ) { case UNLE : case UNLT : case LTGT : case GT : case GE : case UNORDERED : case ORDERED : case UNEQ : return 4 ; break ; case LT : case NE : case EQ : case UNGE : return 5 ; break ; case LE : case UNGT : return 6 ; break ; default : gcc_unreachable ( ) ; } } </s>

Return cost of comparison done fcom + arithmetics operations on AX . All following functions do use number of instructions as a cost metrics . In future this should be tweaked to compute bytes for optimize_size and take into account performance of various instructions on various CPUs .


<s> bool s390_check_symref_alignment ( rtx addr , HOST_WIDE_INT alignment ) { HOST_WIDE_INT addend ; rtx symref ; if ( alignment < 2 || alignment > 8 ) return false ; if ( ! s390_loadrelative_operand_p ( addr , & symref , & addend ) ) return false ; if ( addend & ( alignment - 1 ) ) return false ; if ( GET_CODE ( symref ) == SYMBOL_REF ) { switch ( alignment ) { case 8 : return ! SYMBOL_FLAG_NOTALIGN8_P ( symref ) ; case 4 : return ! SYMBOL_FLAG_NOTALIGN4_P ( symref ) ; case 2 : return ! SYMBOL_FLAG_NOTALIGN2_P ( symref ) ; default : return false ; } } if ( GET_CODE ( symref ) == UNSPEC && alignment <= UNITS_PER_LONG ) return true ; return false ; } </s>

Return true if ADDR is SYMBOL_REF + addend with addend being a multiple of ALIGNMENT and the SYMBOL_REF being naturally aligned .


<s> bool MipsLongBranch :: runOnMachineFunction ( MachineFunction & F ) { const MipsSubtarget & STI = static_cast < const MipsSubtarget & > ( F . getSubtarget ( ) ) ; const MipsInstrInfo * TII = static_cast < const MipsInstrInfo * > ( STI . getInstrInfo ( ) ) ; LongBranchSeqSize = ! IsPIC ? 2 : ( ABI . IsN64 ( ) ? 10 : ( ! STI . isTargetNaCl ( ) ? 9 : 10 ) ) ; if ( STI . inMips16Mode ( ) || ! STI . enableLongBranchPass ( ) ) return false ; if ( ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) && static_cast < const MipsTargetMachine & > ( TM ) . getABI ( ) . IsO32 ( ) && F . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; int ShVal = STI . inMicroMipsMode ( ) ? 2 : 4 ; int64_t Offset = computeOffset ( I -> Br ) / ShVal ; if ( STI . isTargetNaCl ( ) ) { Offset *= 2 ; } if ( ! ForceLongBranch && isInt < 16 > ( Offset ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * 4 ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { uint64_t Address = 0 ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ; } for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) if ( I -> HasLongBranch ) expandToLongBranch ( * I ) ; MF -> RenumberBlocks ( ) ; return true ; } </s>


<s>
SDValue
M680x0TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
MUL
:
return
LowerMUL
(
Op
,
DAG
)
;
case
ISD
::
SADDO
:
case
ISD
::
UADDO
:
case
ISD
::
SSUBO
:
case
ISD
::
USUBO
:
case
ISD
::
SMULO
:
case
ISD
::
UMULO
:
return
LowerXALUO
(
Op
,
DAG
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
case
ISD
::
SETCCCARRY
:
return
LowerSETCCCARRY
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
LowerSELECT
(
Op
,
DAG
)
;
case
ISD
::
BRCOND
:
return
LowerBRCOND
(
Op
,
DAG
)
;
case
ISD
::
ADDC
:
case
ISD
::
ADDE
:
case
ISD
::
SUBC
:
case
ISD
::
SUBE
:
return
LowerADDC_ADDE_SUBC_SUBE
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
ExternalSymbol
:
return
LowerExternalSymbol
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

M680x0
M680x0
"Should not custom lower this!"
ISD::MUL
ISD::SADDO
ISD::UADDO
ISD::SSUBO
ISD::USUBO
ISD::SMULO
ISD::UMULO
ISD::SETCC
ISD::SETCCCARRY
ISD::SELECT
ISD::BRCOND
ISD::ADDC
ISD::ADDE
ISD::SUBC
ISD::SUBE
ISD::ConstantPool
ISD::GlobalAddress
ISD::ExternalSymbol
ISD::BlockAddress
ISD::JumpTable
ISD::VASTART
ISD::DYNAMIC_STACKALLOC


<s>
bool
SystemZAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
;
MatchResult
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MatchingInlineAsm
)
;
switch
(
MatchResult
)
{
case
Match_Success
:
Inst
.
setLoc
(
IDLoc
)
;
Out
.
EmitInstruction
(
Inst
,
getSTI
(
)
)
;
return
false
;
case
Match_MissingFeature
:
{
assert
(
ErrorInfo
&&
"Unknown missing feature!"
)
;
std
::
string
Msg
=
"instruction requires:"
;
uint64_t
Mask
=
1
;
for
(
unsigned
I
=
0
;
I
<
sizeof
(
ErrorInfo
)
*
8
1
;
++
I
)
{
if
(
ErrorInfo
&
Mask
)
{
Msg
+=
" "
;
Msg
+=
getSubtargetFeatureName
(
ErrorInfo
&
Mask
)
;
}
Mask
<<=
1
;
}
return
Error
(
IDLoc
,
Msg
)
;
}
case
Match_InvalidOperand
:
{
SMLoc
ErrorLoc
=
IDLoc
;
if
(
ErrorInfo
!=
~
0ULL
)
{
if
(
ErrorInfo
>=
Operands
.
size
(
)
)
return
Error
(
IDLoc
,
"too few operands for instruction"
)
;
ErrorLoc
=
(
(
SystemZOperand
&
)
*
Operands
[
ErrorInfo
]
)
.
getStartLoc
(
)
;
if
(
ErrorLoc
==
SMLoc
(
)
)
ErrorLoc
=
IDLoc
;
}
return
Error
(
ErrorLoc
,
"invalid operand for instruction"
)
;
}
case
Match_MnemonicFail
:
{
uint64_t
FBS
=
ComputeAvailableFeatures
(
getSTI
(
)
.
getFeatureBits
(
)
)
;
std
::
string
Suggestion
=
SystemZMnemonicSpellCheck
(
(
(
SystemZOperand
&
)
*
Operands
[
0
]
)
.
getToken
(
)
,
FBS
)
;
return
Error
(
IDLoc
,
"invalid instruction"
+
Suggestion
,
(
(
SystemZOperand
&
)
*
Operands
[
0
]
)
.
getLocRange
(
)
)
;
}
}
llvm_unreachable
(
"Unexpected match type"
)
;
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> static struct gcc_regs * get_regs ( struct _Unwind_Context * context ) { const unsigned char * pc = context -> ra ; if ( * ( unsigned int * ) ( pc + 4 ) != 0x44000002 ) return NULL ; if ( * ( unsigned int * ) ( pc + 0 ) == 0x38007777 || * ( unsigned int * ) ( pc + 0 ) == 0x38000077 ) { struct sigframe { char gap [ SIGNAL_FRAMESIZE ] ; unsigned long pad [ 7 ] ; struct gcc_regs * regs ; } * frame = ( struct sigframe * ) context -> cfa ; return frame -> regs ; } else if ( * ( unsigned int * ) ( pc + 0 ) == 0x38006666 || * ( unsigned int * ) ( pc + 0 ) == 0x380000AC ) { struct rt_sigframe { char gap [ SIGNAL_FRAMESIZE + 16 ] ; char siginfo [ 128 ] ; struct gcc_ucontext uc ; } * frame = ( struct rt_sigframe * ) context -> cfa ; return frame -> uc . regs ; } return NULL ; } </s>

If PC is at a sigreturn trampoline , return a pointer to the regs . Otherwise return NULL .


"argument %d of %qE must be an integer constant"

Report that LOCATION has a call to FNDECL in which argument ARGNO was not an integer constant expression . ARGNO counts from zero .


<s> static SDValue WidenVector ( SDValue V64Reg , SelectionDAG & DAG ) { EVT VT = V64Reg . getValueType ( ) ; unsigned NarrowSize = VT . getVectorNumElements ( ) ; MVT EltTy = VT . getVectorElementType ( ) . getSimpleVT ( ) ; MVT WideTy = MVT :: getVectorVT ( EltTy , 2 * NarrowSize ) ; SDLoc DL ( V64Reg ) ; return DAG . getNode ( ISD :: INSERT_SUBVECTOR , DL , WideTy , DAG . getUNDEF ( WideTy ) , V64Reg , DAG . getConstant ( 0 , DL , MVT :: i32 ) ) ; } </s>

Widen the vector up to the next power of two using INSERT_SUBVECTOR .


<s> unsigned getInstSizeInBytes ( const MachineInstr & MI ) const override { return 4U ; } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> unsigned int ix86_minimum_alignment ( tree exp , machine_mode mode , unsigned int align ) { tree type , decl ; if ( exp && DECL_P ( exp ) ) { type = TREE_TYPE ( exp ) ; decl = exp ; } else { type = exp ; decl = NULL ; } if ( TARGET_64BIT || align != 64 || ix86_preferred_stack_boundary >= 64 ) return align ; if ( ( mode == DImode || ( type && TYPE_MODE ( type ) == DImode ) ) && ( ! type || ( ! TYPE_USER_ALIGN ( type ) && ! TYPE_ATOMIC ( strip_array_types ( type ) ) ) ) && ( ! decl || ! DECL_USER_ALIGN ( decl ) ) ) { gcc_checking_assert ( ! TARGET_STV ) ; return 32 ; } return align ; } </s>

Compute the minimum required alignment for dynamic stack realignment purposes for a local variable , parameter or a stack slot . EXP is the data type or decl itself , MODE is its mode and ALIGN is the alignment that the object would ordinarily have .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AsmPrinter :: getAnalysisUsage ( AU ) ; AU . setPreservesAll ( ) ; AU . addRequired < MachineModuleInfo > ( ) ; AU . addRequired < DwarfWriter > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void SystemZPassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createSystemZShortenInstPass ( getSystemZTargetMachine ( ) ) , false ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createSystemZElimComparePass ( getSystemZTargetMachine ( ) ) , false ) ; addPass ( createSystemZLongBranchPass ( getSystemZTargetMachine ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( MISchedPostRA ) addPass ( & PostMachineSchedulerID ) ; else addPass ( & PostRASchedulerID ) ; } } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ


<s> unsigned int UPTInstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { if ( MBB . empty ( ) ) return 0 ; unsigned NumRemoved = 0 ; auto I = MBB . end ( ) ; do { -- I ; unsigned Opc = I -> getOpcode ( ) ; if ( ( Opc == UPT :: JMP ) || ( Opc == UPT :: Bcc ) ) { auto ToDelete = I ; ++ I ; MBB . erase ( ToDelete ) ; NumRemoved ++ ; } } while ( I != MBB . begin ( ) ) ; return NumRemoved ; } </s>

Remove the branching code at the end of the specific MBB .


"expression value must be representable in 32 bits"

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> const char * mcore_output_andn ( rtx insn ATTRIBUTE_UNUSED , rtx operands [ ] ) { int x , y ; rtx out_operands [ 3 ] ; const char * load_op ; char buf [ 256 ] ; int trick_no ; trick_no = try_constant_tricks ( INTVAL ( operands [ 1 ] ) , & x , & y ) ; gcc_assert ( trick_no == 2 ) ; out_operands [ 0 ] = operands [ 0 ] ; out_operands [ 1 ] = GEN_INT ( x ) ; out_operands [ 2 ] = operands [ 2 ] ; if ( x >= 0 && x <= 127 ) load_op = "movi\t%0,%1" ; else if ( ( x & ( x - 1 ) ) == 0 ) load_op = "bgeni\t%0,%P1" ; else if ( ( x & ( x + 1 ) ) == 0 ) load_op = "bmaski\t%0,%N1" ; else load_op = "BADMOVI\t%0,%1" ; sprintf ( buf , "%s\n\tandn\t%%2,%%0" , load_op ) ; output_asm_insn ( buf , out_operands ) ; return "" ; } </s>

Outputs the peephole for moving a constant that gets not'ed followed by an and ( i.e . combine the not and the and into andn ) . BRC


<s> int AArch64TTIImpl :: getIntImmCost ( Intrinsic :: ID IID , unsigned Idx , const APInt & Imm , Type * Ty ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; if ( IID >= Intrinsic :: aarch64_addg && IID <= Intrinsic :: aarch64_udiv ) return AArch64TTIImpl :: getIntImmCost ( Imm , Ty ) ; switch ( IID ) { default : return TTI :: TCC_Free ; case Intrinsic :: sadd_with_overflow : case Intrinsic :: uadd_with_overflow : case Intrinsic :: ssub_with_overflow : case Intrinsic :: usub_with_overflow : case Intrinsic :: smul_with_overflow : case Intrinsic :: umul_with_overflow : if ( Idx == 1 ) { int NumConstants = ( BitSize + 63 ) / 64 ; int Cost = AArch64TTIImpl :: getIntImmCost ( Imm , Ty ) ; return ( Cost <= NumConstants * TTI :: TCC_Basic ) ? static_cast < int > ( TTI :: TCC_Free ) : Cost ; } break ; case Intrinsic :: experimental_stackmap : if ( ( Idx < 2 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; case Intrinsic :: experimental_patchpoint_void : case Intrinsic :: experimental_patchpoint_i64 : if ( ( Idx < 4 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; } return AArch64TTIImpl :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> void Thumb1RegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , unsigned PredReg ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: tLDRcp ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( Pred ) . addReg ( PredReg ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s> void ARMInstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , unsigned SubIdx , const MachineInstr * Orig , const TargetRegisterInfo * TRI ) const { DebugLoc dl = Orig -> getDebugLoc ( ) ; unsigned Opcode = Orig -> getOpcode ( ) ; switch ( Opcode ) { default : break ; case ARM :: MOVi2pieces : { RI . emitLoadConstPool ( MBB , I , dl , DestReg , SubIdx , Orig -> getOperand ( 1 ) . getImm ( ) , ( ARMCC :: CondCodes ) Orig -> getOperand ( 2 ) . getImm ( ) , Orig -> getOperand ( 3 ) . getReg ( ) ) ; MachineInstr * NewMI = prior ( I ) ; NewMI -> getOperand ( 0 ) . setSubReg ( SubIdx ) ; return ; } } return ARMBaseInstrInfo :: reMaterialize ( MBB , I , DestReg , SubIdx , Orig , TRI ) ; } </s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s> static bool arm_evpc_neon_vtrn ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> perm . length ( ) ; rtx out0 , out1 , in0 , in1 ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; if ( d -> perm [ 0 ] == 0 ) odd = 0 ; else if ( d -> perm [ 0 ] == 1 ) odd = 1 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt ; i += 2 ) { if ( d -> perm [ i ] != i + odd ) return false ; if ( d -> perm [ i + 1 ] != ( ( i + nelt + odd ) & mask ) ) return false ; } if ( d -> testing_p ) return true ; in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN ) { std :: swap ( in0 , in1 ) ; odd = ! odd ; } out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( odd ) std :: swap ( out0 , out1 ) ; emit_insn ( gen_neon_vtrn_internal ( d -> vmode , out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s> static std :: unique_ptr < MSP430Operand > CreateMem ( unsigned RegNum , const MCExpr * Val , SMLoc S , SMLoc E ) { return std :: make_unique < MSP430Operand > ( RegNum , Val , S , E ) ; } </s>


<s> void init_cumulative_args ( struct sparc_args * cum , tree fntype , rtx , tree ) { cum -> words = 0 ; cum -> prototype_p = fntype && prototype_p ( fntype ) ; cum -> libcall_p = ! fntype ; } </s>

Handle the INIT_CUMULATIVE_ARGS macro . Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is 0 .


<s>
void
F2003fMCAsmStreamer
::
addExplicitComment
(
const
Twine
&
T
)
{
StringRef
c
=
T
.
getSingleStringRef
(
)
;
if
(
c
.
startswith
(
StringRef
(
MAI
->
getCommentString
(
)
)
)
)
{
ExplicitCommentToEmit
.
append
(
c
.
str
(
)
)
;
}
else
{
assert
(
false
&&
"Unexpected Assembly Comment"
)
;
}
if
(
c
.
back
(
)
==
'\n'
)
emitExplicitComments
(
)
;
}
</s>


<s> int PPCTTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) { if ( DisablePPCConstHoist ) return BaseT :: getIntImmCostInst ( Opcode , Idx , Imm , Ty ) ; assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return ~ 0U ; unsigned ImmIdx = ~ 0U ; bool ShiftedFree = false , RunFree = false , UnsignedFree = false , ZeroFree = false ; switch ( Opcode ) { default : return TTI :: TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: And : RunFree = true ; LLVM_FALLTHROUGH ; case Instruction :: Add : case Instruction :: Or : case Instruction :: Xor : ShiftedFree = true ; LLVM_FALLTHROUGH ; case Instruction :: Sub : case Instruction :: Mul : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : ImmIdx = 1 ; break ; case Instruction :: ICmp : UnsignedFree = true ; ImmIdx = 1 ; LLVM_FALLTHROUGH ; case Instruction :: Select : ZeroFree = true ; break ; case Instruction :: PHI : case Instruction :: Call : case Instruction :: Ret : case Instruction :: Load : case Instruction :: Store : break ; } if ( ZeroFree && Imm == 0 ) return TTI :: TCC_Free ; if ( Idx == ImmIdx && Imm . getBitWidth ( ) <= 64 ) { if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; if ( RunFree ) { if ( Imm . getBitWidth ( ) <= 32 && ( isShiftedMask_32 ( Imm . getZExtValue ( ) ) || isShiftedMask_32 ( ~ Imm . getZExtValue ( ) ) ) ) return TTI :: TCC_Free ; if ( ST -> isPPC64 ( ) && ( isShiftedMask_64 ( Imm . getZExtValue ( ) ) || isShiftedMask_64 ( ~ Imm . getZExtValue ( ) ) ) ) return TTI :: TCC_Free ; } if ( UnsignedFree && isUInt < 16 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( ShiftedFree && ( Imm . getZExtValue ( ) & 0xFFFF ) == 0 ) return TTI :: TCC_Free ; } return PPCTTIImpl :: getIntImmCost ( Imm , Ty ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s>
void
i386_pe_file_end
(
void
)
{
struct
extern_list
*
p
;
ix86_file_end
(
)
;
for
(
p
=
extern_head
;
p
!=
;
p
=
p
->
next
)
{
tree
decl
;
decl
=
p
->
decl
;
if
(
!
TREE_ASM_WRITTEN
(
decl
)
&&
TREE_SYMBOL_REFERENCED
(
DECL_ASSEMBLER_NAME
(
decl
)
)
)
{
TREE_ASM_WRITTEN
(
decl
)
=
1
;
i386_pe_declare_function_type
(
asm_out_file
,
p
->
name
,
TREE_PUBLIC
(
decl
)
)
;
}
}
if
(
export_head
)
{
struct
export_list
*
q
;
drectve_section
(
)
;
for
(
q
=
export_head
;
q
!=
;
q
=
q
->
next
)
{
fprintf
(
asm_out_file
,
"\t.ascii \" -export:%s%s\"\n"
,
i386_pe_strip_name_encoding
(
q
->
name
)
,
(
q
->
is_data
)
",data"
:
""
)
;
}
}
}
</s>

This is called at the end of assembly . For each external function which has not been defined , we output a declaration now . We also output the .drectve section .


<s> static bool visium_rtx_costs ( rtx x , int code , int outer_code ATTRIBUTE_UNUSED , int opno ATTRIBUTE_UNUSED , int * total , bool speed ATTRIBUTE_UNUSED ) { enum machine_mode mode = GET_MODE ( x ) ; switch ( code ) { case CONST_INT : * total = COSTS_N_INSNS ( ! satisfies_constraint_J ( x ) ) ; return true ; case CONST : case LABEL_REF : case SYMBOL_REF : * total = COSTS_N_INSNS ( 2 ) ; return true ; case CONST_DOUBLE : { rtx high , low ; split_double ( x , & high , & low ) ; * total = COSTS_N_INSNS ( ! satisfies_constraint_J ( high ) + ! satisfies_constraint_J ( low ) ) ; return true ; } case MULT : * total = COSTS_N_INSNS ( 3 ) ; return false ; case DIV : case UDIV : case MOD : case UMOD : if ( mode == DImode ) * total = COSTS_N_INSNS ( 64 ) ; else * total = COSTS_N_INSNS ( 32 ) ; return false ; case PLUS : case MINUS : case NEG : if ( mode == DImode ) * total = COSTS_N_INSNS ( 2 ) ; else * total = COSTS_N_INSNS ( 1 ) ; return false ; case ASHIFT : case ASHIFTRT : case LSHIFTRT : if ( mode == DImode ) * total = COSTS_N_INSNS ( 3 ) ; else * total = COSTS_N_INSNS ( 1 ) ; return false ; case COMPARE : if ( GET_CODE ( XEXP ( x , 0 ) ) == ZERO_EXTRACT && XEXP ( x , 1 ) == const0_rtx && XEXP ( XEXP ( x , 0 ) , 1 ) == const1_rtx && satisfies_constraint_K ( XEXP ( XEXP ( x , 0 ) , 2 ) ) ) * total = COSTS_N_INSNS ( 1 ) ; return false ; default : return false ; } } </s>

Return the relative costs of expression X .


<s> unsigned X86InstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { return removeBranchImpl ( MBB , BytesRemoved , false ) ; } </s>


<s> bool ARMFrameLowering :: canSimplifyCallFramePseudos ( const MachineFunction & MF ) const { return hasReservedCallFrame ( MF ) || MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ; } </s>

canSimplifyCallFramePseudos - If there is a reserved call frame , the call frame pseudos can be simplified .


<s> bool X86FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; const X86Subtarget & STI = MF . getTarget ( ) . getSubtarget < X86Subtarget > ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } unsigned Opc = STI . is64Bit ( ) ? X86 :: POP64r : X86 :: POP32r ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static enum machine_mode ix86_cc_modes_compatible ( enum machine_mode m1 , enum machine_mode m2 ) { if ( m1 == m2 ) return m1 ; if ( GET_MODE_CLASS ( m1 ) != MODE_CC || GET_MODE_CLASS ( m2 ) != MODE_CC ) return VOIDmode ; if ( ( m1 == CCGCmode && m2 == CCGOCmode ) || ( m1 == CCGOCmode && m2 == CCGCmode ) ) return CCGCmode ; switch ( m1 ) { default : gcc_unreachable ( ) ; case CCmode : case CCGCmode : case CCGOCmode : case CCNOmode : case CCZmode : switch ( m2 ) { default : return VOIDmode ; case CCmode : case CCGCmode : case CCGOCmode : case CCNOmode : case CCZmode : return CCmode ; } case CCFPmode : case CCFPUmode : return VOIDmode ; } } </s>

If two condition code modes are compatible , return a condition code mode which is compatible with both . Otherwise , return VOIDmode .


<s>
bool
HexagonRDFOpt
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
if
(
RDFLimit
.
getPosition
(
)
)
{
if
(
RDFCount
>=
RDFLimit
)
return
false
;
RDFCount
++
;
}
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
const
auto
&
MDF
=
getAnalysis
<
MachineDominanceFrontier
>
(
)
;
const
auto
&
HII
=
*
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getInstrInfo
(
)
;
const
auto
&
HRI
=
*
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getRegisterInfo
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
bool
Changed
;
if
(
RDFDump
)
MF
.
print
(
dbgs
(
)
<<
"Before "
<<
getPassName
(
)
<<
"\n"
,
nullptr
)
;
TargetOperandInfo
TOI
(
HII
)
;
DataFlowGraph
G
(
MF
,
HII
,
HRI
,
*
MDT
,
MDF
,
TOI
)
;
G
.
build
(
BuildOptions
::
KeepDeadPhis
)
;
if
(
RDFDump
)
dbgs
(
)
<<
"Starting copy propagation on: "
<<
MF
.
getName
(
)
<<
'\n'
<<
PrintNode
<
FuncNode
*
>
(
G
.
getFunc
(
)
,
G
)
<<
'\n'
;
HexagonCP
CP
(
G
)
;
CP
.
trace
(
RDFDump
)
;
Changed
=
CP
.
run
(
)
;
if
(
RDFDump
)
dbgs
(
)
<<
"Starting dead code elimination on: "
<<
MF
.
getName
(
)
<<
'\n'
<<
PrintNode
<
FuncNode
*
>
(
G
.
getFunc
(
)
,
G
)
<<
'\n'
;
HexagonDCE
DCE
(
G
,
*
MRI
)
;
DCE
.
trace
(
RDFDump
)
;
Changed
|=
DCE
.
run
(
)
;
if
(
Changed
)
{
if
(
RDFDump
)
dbgs
(
)
<<
"Starting liveness recomputation on: "
<<
MF
.
getName
(
)
<<
'\n'
;
Liveness
LV
(
*
MRI
,
G
)
;
LV
.
trace
(
RDFDump
)
;
LV
.
computeLiveIns
(
)
;
LV
.
resetLiveIns
(
)
;
LV
.
resetKills
(
)
;
}
if
(
RDFDump
)
MF
.
print
(
dbgs
(
)
<<
"After "
<<
getPassName
(
)
<<
"\n"
,
nullptr
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .

Hexagon
Hexagon
Hexagon
Hexagon
"Before "
"\n"
"Starting copy propagation on: "
Hexagon
"Starting dead code elimination on: "
Hexagon
"Starting liveness recomputation on: "
"After "
"\n"


<s> unsigned getMaxCallFrameSize ( ) const { return MaxCallFrameSize ; } </s>

Return the maximum size of a call frame that must be allocated for an outgoing function call .


<s>
void
mmix_output_register_setting
(
FILE
*
stream
,
int
regno
,
HOST_WIDEST_INT
value
,
int
do_begin_end
)
{
if
(
do_begin_end
)
fprintf
(
stream
,
"\t"
)
;
if
(
mmix_shiftable_wyde_value
(
(
unsigned
HOST_WIDEST_INT
)
value
)
)
{
mmix_output_shiftvalue_op_from_str
(
stream
,
"SET"
,
(
unsigned
HOST_WIDEST_INT
)
value
)
;
fprintf
(
stream
,
" %s,"
,
reg_names
[
regno
]
)
;
mmix_output_shifted_value
(
stream
,
(
unsigned
HOST_WIDEST_INT
)
value
)
;
}
else
if
(
mmix_shiftable_wyde_value
(
(
unsigned
HOST_WIDEST_INT
)
value
)
)
{
mmix_output_shiftvalue_op_from_str
(
stream
,
"SET"
,
(
unsigned
HOST_WIDEST_INT
)
value
)
;
fprintf
(
stream
,
" %s,"
,
reg_names
[
regno
]
)
;
mmix_output_shifted_value
(
stream
,
(
unsigned
HOST_WIDEST_INT
)
value
)
;
fprintf
(
stream
,
"\n\tNEGU %s,0,%s"
,
reg_names
[
regno
]
,
reg_names
[
regno
]
)
;
}
else
if
(
mmix_shiftable_wyde_value
(
~
(
unsigned
HOST_WIDEST_INT
)
value
)
)
{
mmix_output_shiftvalue_op_from_str
(
stream
,
"SET"
,
~
(
unsigned
HOST_WIDEST_INT
)
value
)
;
fprintf
(
stream
,
" %s,"
,
reg_names
[
regno
]
)
;
mmix_output_shifted_value
(
stream
,
~
(
unsigned
HOST_WIDEST_INT
)
value
)
;
fprintf
(
stream
,
"\n\tNOR %s,%s,0"
,
reg_names
[
regno
]
,
reg_names
[
regno
]
)
;
}
else
{
static
const
char
*
const
higher_parts
[
]
=
{
"L"
,
"ML"
,
"MH"
,
"H"
}
;
const
char
*
op
=
"SET"
;
const
char
*
line_begin
=
""
;
int
insns
=
0
;
int
i
;
HOST_WIDEST_INT
tmpvalue
=
value
;
for
(
i
=
0
;
i
<
4
&&
tmpvalue
!=
0
;
i
++
)
{
if
(
tmpvalue
&
65535
)
insns
++
;
tmpvalue
>>=
16
;
}
if
(
TARGET_BASE_ADDRESSES
&&
insns
==
3
)
{
fprintf
(
stream
,
"LDA %s,"
,
reg_names
[
regno
]
)
;
mmix_output_octa
(
stream
,
value
,
0
)
;
}
else
{
for
(
i
=
0
;
i
<
4
&&
value
!=
0
;
i
++
)
{
if
(
value
&
65535
)
{
fprintf
(
stream
,
"%s%s%s %s,#%x"
,
line_begin
,
op
,
higher_parts
[
i
]
,
reg_names
[
regno
]
,
(
int
)
(
value
&
65535
)
)
;
op
=
"INC"
;
line_begin
=
"\n\t"
;
}
value
>>=
16
;
}
}
}
if
(
do_begin_end
)
fprintf
(
stream
,
"\n"
)
;
}
</s>

Output an optimal sequence for setting a register to a specific constant . Used in an alternative for const_ints in movdi , and when using large stack-frame offsets . Use do_begin_end to say if a line-starting TAB and newline before the first insn and after the last insn is wanted .


<s> void SparcPassConfig :: addPreEmitPass ( ) { addPass ( createSparcDelaySlotFillerPass ( getSparcTargetMachine ( ) ) ) ; if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> insertNOPLoad ( ) ) { addPass ( new InsertNOPLoad ( getSparcTargetMachine ( ) ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> fixFSMULD ( ) ) { addPass ( new FixFSMULD ( getSparcTargetMachine ( ) ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> replaceFMULS ( ) ) { addPass ( new ReplaceFMULS ( getSparcTargetMachine ( ) ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> fixAllFDIVSQRT ( ) ) { addPass ( new FixAllFDIVSQRT ( getSparcTargetMachine ( ) ) ) ; } } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc


<s> tree function_resolver :: resolve_to ( mode_suffix_index mode , type_suffix_index type0 , type_suffix_index type1 ) { tree res = lookup_form ( mode , type0 , type1 ) ; if ( ! res ) { if ( type1 == NUM_TYPE_SUFFIXES ) return report_no_such_form ( type0 ) ; if ( type0 == type_suffix_ids [ 0 ] ) return report_no_such_form ( type1 ) ; gcc_unreachable ( ) ; } return res ; } </s>

Resolve the function to one with the mode suffix given by MODE and the type suffixes given by TYPE0 and TYPE1 . Return its function decl on success , otherwise report an error and return error_mark_node .


<s>
void
NVPTXAsmPrinter
::
emitHeader
(
Module
&
M
,
raw_ostream
&
O
,
const
NVPTXSubtarget
&
STI
)
{
O
<<
"//\n"
;
O
<<
"// Generated by LLVM NVPTX Back-End\n"
;
O
<<
"//\n"
;
O
<<
"\n"
;
unsigned
PTXVersion
=
STI
.
getPTXVersion
(
)
;
O
<<
".version "
<<
(
PTXVersion
/
10
)
<<
"."
<<
(
PTXVersion
%
10
)
<<
"\n"
;
O
<<
".target "
;
O
<<
STI
.
getTargetName
(
)
;
const
NVPTXTargetMachine
&
NTM
=
static_cast
<
const
NVPTXTargetMachine
&
>
(
TM
)
;
if
(
NTM
.
getDrvInterface
(
)
==
NVPTX
::
NVCL
)
O
<<
", texmode_independent"
;
else
{
if
(
!
STI
.
hasDouble
(
)
)
O
<<
", map_f64_to_f32"
;
}
if
(
MAI
->
doesSupportDebugInformation
(
)
)
O
<<
", debug"
;
O
<<
"\n"
;
O
<<
".address_size "
;
if
(
NTM
.
is64Bit
(
)
)
O
<<
"64"
;
else
O
<<
"32"
;
O
<<
"\n"
;
O
<<
"\n"
;
}
</s>

Emit the header for this unit , not including the initial length field .

NVPTX
NVPTX
NVPTX
"//\n"
"// Generated by LLVM NVPTX Back-End\n"
"//\n"
"\n"
".version "
10
"."
10
"\n"
".target "
NVPTX
NVPTX
NVPTX::NVCL
", texmode_independent"
", map_f64_to_f32"
", debug"
"\n"
".address_size "
"64"
"32"
"\n"
"\n"


<s> static unsigned long arm_compute_func_type ( void ) { unsigned long type = ARM_FT_UNKNOWN ; tree a ; tree attr ; gcc_assert ( TREE_CODE ( current_function_decl ) == FUNCTION_DECL ) ; if ( optimize > 0 && ( TREE_NOTHROW ( current_function_decl ) || ! ( flag_unwind_tables || ( flag_exceptions && arm_except_unwind_info ( & global_options ) != UI_SJLJ ) ) ) && TREE_THIS_VOLATILE ( current_function_decl ) ) type |= ARM_FT_VOLATILE ; if ( cfun -> static_chain_decl != NULL ) type |= ARM_FT_NESTED ; attr = DECL_ATTRIBUTES ( current_function_decl ) ; a = lookup_attribute ( "naked" , attr ) ; if ( a != NULL_TREE ) type |= ARM_FT_NAKED ; a = lookup_attribute ( "isr" , attr ) ; if ( a == NULL_TREE ) a = lookup_attribute ( "interrupt" , attr ) ; if ( a == NULL_TREE ) type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL ; else type |= arm_isr_value ( TREE_VALUE ( a ) ) ; return type ; } </s>

Computes the type of the current function .


<s>
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
PatmosTargetLowering
::
getRegForInlineAsmConstraint
(
const
std
::
string
&
Constraint
,
MVT
VT
)
const
{
if
(
Constraint
.
size
(
)
==
1
)
{
switch
(
Constraint
[
0
]
)
{
case
'R'
:
case
'r'
:
return
std
::
make_pair
(
0U
,
&
Patmos
::
RRegsRegClass
)
;
case
'S'
:
if
(
VT
==
MVT
::
i32
)
{
return
std
::
make_pair
(
0U
,
&
Patmos
::
SRegsRegClass
)
;
}
assert
(
"Unexpected register type"
)
;
return
std
::
make_pair
(
0U
,
static_cast
<
const
TargetRegisterClass
*
>
(
0
)
)
;
case
'P'
:
if
(
VT
==
MVT
::
i1
)
{
return
std
::
make_pair
(
0U
,
&
Patmos
::
PRegsRegClass
)
;
}
assert
(
"Unexpected register type"
)
;
return
std
::
make_pair
(
0U
,
static_cast
<
const
TargetRegisterClass
*
>
(
0
)
)
;
}
}
if
(
Constraint
.
size
(
)
>
2
&&
Constraint
[
0
]
==
'{'
&&
Constraint
[
1
]
==
'$'
)
{
std
::
string
Stripped
=
"{"
+
Constraint
.
substr
(
2
)
;
return
TargetLowering
::
getRegForInlineAsmConstraint
(
Stripped
,
VT
)
;
}
return
TargetLowering
::
getRegForInlineAsmConstraint
(
Constraint
,
VT
)
;
}
</s>

Given a physical register constraint ( e.g .


<s> bool X86AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNo ) ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , O ) ; case 'a' : if ( MO . isImm ( ) ) { O << MO . getImm ( ) ; return false ; } if ( MO . isGlobal ( ) || MO . isCPI ( ) || MO . isJTI ( ) || MO . isSymbol ( ) ) { printSymbolOperand ( MO , O ) ; if ( Subtarget -> isPICStyleRIPRel ( ) ) O << "(%rip)" ; return false ; } if ( MO . isReg ( ) ) { O << '(' ; printOperand ( MI , OpNo , O ) ; O << ')' ; return false ; } return true ; case 'c' : if ( MO . isImm ( ) ) O << MO . getImm ( ) ; else if ( MO . isGlobal ( ) || MO . isCPI ( ) || MO . isJTI ( ) || MO . isSymbol ( ) ) printSymbolOperand ( MO , O ) ; else printOperand ( MI , OpNo , O ) ; return false ; case 'A' : if ( MO . isReg ( ) ) { O << '*' ; printOperand ( MI , OpNo , O ) ; return false ; } return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : if ( MO . isReg ( ) ) return printAsmMRegister ( MO , ExtraCode [ 0 ] , O ) ; printOperand ( MI , OpNo , O ) ; return false ; case 'P' : print_pcrel_imm ( MI , OpNo , O ) ; return false ; case 'n' : if ( MO . isImm ( ) ) { O << - MO . getImm ( ) ; return false ; } O << '-' ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


"GBZ80 dynalloca stack pointer save/restore"

getPassName - Return a nice clean name for a pass .


"\nnew fndecl target specific options:\n"

"\nold fndecl target specific options:\n"

Establish appropriate back-end context for processing the function FNDECL . The argument might be NULL to indicate processing at top level , outside of any function scope .


<s> SDValue AMDGPUTargetLowering :: SplitVectorStore ( SDValue Op , SelectionDAG & DAG ) const { StoreSDNode * Store = cast < StoreSDNode > ( Op ) ; SDValue Val = Store -> getValue ( ) ; EVT VT = Val . getValueType ( ) ; if ( VT . getVectorNumElements ( ) == 2 ) return ScalarizeVectorStore ( Op , DAG ) ; EVT MemVT = Store -> getMemoryVT ( ) ; SDValue Chain = Store -> getChain ( ) ; SDValue BasePtr = Store -> getBasePtr ( ) ; SDLoc SL ( Op ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Val , SL , LoVT , HiVT ) ; EVT PtrVT = BasePtr . getValueType ( ) ; SDValue HiPtr = DAG . getNode ( ISD :: ADD , SL , PtrVT , BasePtr , DAG . getConstant ( LoMemVT . getStoreSize ( ) , PtrVT ) ) ; MachinePointerInfo SrcValue ( Store -> getMemOperand ( ) -> getValue ( ) ) ; SDValue LoStore = DAG . getTruncStore ( Chain , SL , Lo , BasePtr , SrcValue , LoMemVT , Store -> isNonTemporal ( ) , Store -> isVolatile ( ) , Store -> getAlignment ( ) ) ; SDValue HiStore = DAG . getTruncStore ( Chain , SL , Hi , HiPtr , SrcValue . getWithOffset ( LoMemVT . getStoreSize ( ) ) , HiMemVT , Store -> isNonTemporal ( ) , Store -> isVolatile ( ) , Store -> getAlignment ( ) ) ; return DAG . getNode ( ISD :: TokenFactor , SL , MVT :: Other , LoStore , HiStore ) ; } </s>

Split a vector store into 2 stores of half the vector .


<s> void avr_expand_prologue ( void ) { HARD_REG_SET set ; HOST_WIDE_INT size ; size = get_frame_size ( ) + avr_outgoing_args_size ( ) ; cfun -> machine -> stack_usage = 0 ; if ( cfun -> machine -> is_naked ) { return ; } avr_regs_to_save ( & set ) ; if ( cfun -> machine -> is_interrupt || cfun -> machine -> is_signal ) { if ( cfun -> machine -> is_interrupt ) emit_insn ( gen_enable_interrupt ( ) ) ; emit_push_byte ( AVR_ZERO_REGNO , true ) ; emit_push_byte ( AVR_TMP_REGNO , true ) ; emit_push_sfr ( sreg_rtx , false , false ) ; emit_move_insn ( zero_reg_rtx , const0_rtx ) ; emit_use ( zero_reg_rtx ) ; if ( AVR_HAVE_RAMPD ) emit_push_sfr ( rampd_rtx , false , true ) ; if ( AVR_HAVE_RAMPX && TEST_HARD_REG_BIT ( set , REG_X ) && TEST_HARD_REG_BIT ( set , REG_X + 1 ) ) { emit_push_sfr ( rampx_rtx , false , true ) ; } if ( AVR_HAVE_RAMPY && ( frame_pointer_needed || ( TEST_HARD_REG_BIT ( set , REG_Y ) && TEST_HARD_REG_BIT ( set , REG_Y + 1 ) ) ) ) { emit_push_sfr ( rampy_rtx , false , true ) ; } if ( AVR_HAVE_RAMPZ && TEST_HARD_REG_BIT ( set , REG_Z ) && TEST_HARD_REG_BIT ( set , REG_Z + 1 ) ) { emit_push_sfr ( rampz_rtx , false , AVR_HAVE_RAMPD ) ; } } avr_prologue_setup_frame ( size , set ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = cfun -> machine -> stack_usage + INCOMING_FRAME_SP_OFFSET ; } </s>


<s> static bool verify_neutering_jumps ( basic_block from , rtx_insn * vector_jump , rtx_insn * worker_jump , rtx_insn * vector_label , rtx_insn * worker_label ) { basic_block bb = from ; rtx_insn * insn = BB_HEAD ( bb ) ; bool seen_worker_jump = false ; bool seen_vector_jump = false ; bool seen_worker_label = false ; bool seen_vector_label = false ; bool worker_neutered = false ; bool vector_neutered = false ; while ( true ) { if ( insn == worker_jump ) { seen_worker_jump = true ; worker_neutered = true ; gcc_assert ( ! vector_neutered ) ; } else if ( insn == vector_jump ) { seen_vector_jump = true ; vector_neutered = true ; } else if ( insn == worker_label ) { seen_worker_label = true ; gcc_assert ( worker_neutered ) ; worker_neutered = false ; } else if ( insn == vector_label ) { seen_vector_label = true ; gcc_assert ( vector_neutered ) ; vector_neutered = false ; } else if ( INSN_P ( insn ) ) switch ( recog_memoized ( insn ) ) { case CODE_FOR_nvptx_barsync : gcc_assert ( ! vector_neutered && ! worker_neutered ) ; break ; default : break ; } if ( insn != BB_END ( bb ) ) insn = NEXT_INSN ( insn ) ; else if ( JUMP_P ( insn ) && single_succ_p ( bb ) && ! seen_vector_jump && ! seen_worker_jump ) { bb = single_succ ( bb ) ; insn = BB_HEAD ( bb ) ; } else break ; } gcc_assert ( ! ( vector_jump && ! seen_vector_jump ) ) ; gcc_assert ( ! ( worker_jump && ! seen_worker_jump ) ) ; if ( seen_vector_label || seen_worker_label ) { gcc_assert ( ! ( vector_label && ! seen_vector_label ) ) ; gcc_assert ( ! ( worker_label && ! seen_worker_label ) ) ; return true ; } return false ; } </s>

Verify position of VECTOR_ { JUMP , LABEL } and WORKER_ { JUMP , LABEL } in FROM .


<s> static bool m68k_output_addr_const_extra ( FILE * file , rtx x ) { if ( GET_CODE ( x ) == UNSPEC ) { switch ( XINT ( x , 1 ) ) { case UNSPEC_RELOC16 : case UNSPEC_RELOC32 : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fputs ( m68k_get_reloc_decoration ( ( enum m68k_reloc ) INTVAL ( XVECEXP ( x , 0 , 1 ) ) ) , file ) ; return true ; default : break ; } } return false ; } </s>


<s>
void
SystemZPostRASchedStrategy
::
enterMBB
(
MachineBasicBlock
*
NextMBB
)
{
assert
(
(
SchedStates
.
find
(
NextMBB
)
==
SchedStates
.
end
(
)
)
&&
"Entering MBB twice?"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"** Entering "
<<
printMBBReference
(
*
NextMBB
)
)
;
MBB
=
NextMBB
;
HazardRec
=
SchedStates
[
MBB
]
=
new
SystemZHazardRecognizer
(
TII
,
&
SchedModel
)
;
LLVM_DEBUG
(
const
MachineLoop
*
Loop
=
MLI
->
getLoopFor
(
MBB
)
;
if
(
Loop
&&
Loop
->
getHeader
(
)
==
MBB
)
dbgs
(
)
<<
" (Loop header)"
;
dbgs
(
)
<<
":\n"
;
)
;
MachineBasicBlock
*
SinglePredMBB
=
getSingleSchedPred
(
MBB
,
MLI
->
getLoopFor
(
MBB
)
)
;
if
(
SinglePredMBB
==
nullptr
||
SchedStates
.
find
(
SinglePredMBB
)
==
SchedStates
.
end
(
)
)
return
;
LLVM_DEBUG
(
dbgs
(
)
<<
"** Continued scheduling from "
<<
printMBBReference
(
*
SinglePredMBB
)
<<
"\n"
;
)
;
HazardRec
->
copyState
(
SchedStates
[
SinglePredMBB
]
)
;
LLVM_DEBUG
(
HazardRec
->
dumpState
(
)
;
)
;
for
(
MachineBasicBlock
::
iterator
I
=
SinglePredMBB
->
getFirstTerminator
(
)
;
I
!=
SinglePredMBB
->
end
(
)
;
I
++
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"** Emitting incoming branch: "
;
I
->
dump
(
)
;
)
;
bool
TakenBranch
=
(
I
->
isBranch
(
)
&&
(
TII
->
getBranchInfo
(
*
I
)
.
isIndirect
(
)
||
TII
->
getBranchInfo
(
*
I
)
.
getMBBTarget
(
)
==
MBB
)
)
;
HazardRec
->
emitInstruction
(
&
*
I
,
TakenBranch
)
;
if
(
TakenBranch
)
break
;
}
}
</s>

Tell the strategy that MBB is about to be processed .

SystemZ
SystemZ
"Entering MBB twice?"
"** Entering "
SystemZ
" (Loop header)"
":\n"
"** Continued scheduling from "
"\n"
"** Emitting incoming branch: "


<s> static void replace_mov_pcrel_step3 ( rtx_insn * insn ) { rtx pattern = PATTERN ( insn ) ; rtx unspec ; rtx opnds [ 4 ] ; rtx_insn * new_insns ; rtx got_rtx = tilegx_got_rtx ( ) ; rtx text_label_rtx = tilegx_text_label_rtx ( ) ; gcc_assert ( GET_CODE ( pattern ) == SET ) ; opnds [ 0 ] = SET_DEST ( pattern ) ; unspec = SET_SRC ( pattern ) ; gcc_assert ( GET_CODE ( unspec ) == UNSPEC ) ; gcc_assert ( XINT ( unspec , 1 ) == UNSPEC_MOV_PCREL_STEP3 ) ; opnds [ 1 ] = got_rtx ; if ( XVECEXP ( unspec , 0 , 0 ) == text_label_rtx ) opnds [ 2 ] = XVECEXP ( unspec , 0 , 1 ) ; else { gcc_assert ( XVECEXP ( unspec , 0 , 1 ) == text_label_rtx ) ; opnds [ 2 ] = XVECEXP ( unspec , 0 , 0 ) ; } opnds [ 3 ] = XVECEXP ( unspec , 0 , 2 ) ; if ( GET_CODE ( opnds [ 3 ] ) != SYMBOL_REF ) return ; start_sequence ( ) ; if ( flag_pic == 1 ) { emit_move_insn ( opnds [ 0 ] , gen_const_mem ( Pmode , opnds [ 2 ] ) ) ; } else { emit_move_insn ( opnds [ 0 ] , gen_rtx_PLUS ( Pmode , opnds [ 1 ] , opnds [ 2 ] ) ) ; emit_move_insn ( opnds [ 0 ] , gen_const_mem ( Pmode , opnds [ 0 ] ) ) ; } new_insns = get_insns ( ) ; end_sequence ( ) ; replace_insns ( insn , new_insns ) ; } </s>

Do the third replacement step in tilegx_fixup_pcrel_references .


<s> static int vax_address_cost ( rtx x , machine_mode mode ATTRIBUTE_UNUSED , addr_space_t as ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { return COSTS_N_INSNS ( 1 + ( REG_P ( x ) ? 0 : vax_address_cost_1 ( x ) ) ) ; } </s>

Return the cost in cycles of a memory address , relative to register indirect . Each of the following adds the indicated number of cycles : 1 - symbolic address 1 - pre-decrement 1 - indexing and/or offset ( register ) 2 - indirect


<s> const AArch64Subtarget * getSubtarget ( ) const { return & getTargetMachine ( ) . getSubtarget < AArch64Subtarget > ( ) ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


<s> static void ix86_simd_clone_adjust ( struct cgraph_node * node ) { const char * str = NULL ; gcc_assert ( node -> decl == cfun -> decl ) ; switch ( node -> simdclone -> vecsize_mangle ) { case 'b' : if ( ! TARGET_SSE2 ) str = "sse2" ; break ; case 'c' : if ( ! TARGET_AVX ) str = "avx" ; break ; case 'd' : if ( ! TARGET_AVX2 ) str = "avx2" ; break ; default : gcc_unreachable ( ) ; } if ( str == NULL ) return ; push_cfun ( NULL ) ; tree args = build_tree_list ( NULL_TREE , build_string ( strlen ( str ) , str ) ) ; bool ok = ix86_valid_target_attribute_p ( node -> decl , NULL , args , 0 ) ; gcc_assert ( ok ) ; pop_cfun ( ) ; ix86_reset_previous_fndecl ( ) ; ix86_set_current_function ( node -> decl ) ; } </s>

Add target attribute to SIMD clone NODE if needed .


<s>
void
Z80Operand
::
addExpr
(
MCInst
&
Inst
,
const
MCExpr
*
expr
)
const
{
if
(
expr
==
nullptr
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"addExpr() called with a null expr\n"
"adding an imm(0); \n"
)
;
Inst
.
addOperand
(
MCOperand
::
createImm
(
0
)
)
;
}
else
if
(
const
auto
*
CE
=
dyn_cast
<
MCConstantExpr
>
(
expr
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Collapsing const expr to imm\n"
)
;
Inst
.
addOperand
(
MCOperand
::
createImm
(
CE
->
getValue
(
)
)
)
;
}
else
{
Inst
.
addOperand
(
MCOperand
::
createExpr
(
expr
)
)
;
}
}
</s>


<s> BitVector BlackfinRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { using namespace BF ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AZ ) ; Reserved . set ( AN ) ; Reserved . set ( AQ ) ; Reserved . set ( AC0 ) ; Reserved . set ( AC1 ) ; Reserved . set ( AV0 ) ; Reserved . set ( AV0S ) ; Reserved . set ( AV1 ) ; Reserved . set ( AV1S ) ; Reserved . set ( V ) ; Reserved . set ( VS ) ; Reserved . set ( CYCLES ) . set ( CYCLES2 ) ; Reserved . set ( L0 ) ; Reserved . set ( L1 ) ; Reserved . set ( L2 ) ; Reserved . set ( L3 ) ; Reserved . set ( SP ) ; Reserved . set ( RETS ) ; if ( hasFP ( MF ) ) Reserved . set ( FP ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
SDValue
TLCS900TargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
isVarArg
,
Ins
,
dl
,
DAG
,
InVals
)
;
case
CallingConv
::
TLCS900_INTR
:
if
(
Ins
.
empty
(
)
)
return
Chain
;
report_fatal_error
(
"ISRs cannot have arguments"
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> void HexagonFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { auto & HST = MF . getSubtarget < HexagonSubtarget > ( ) ; auto & HRI = * HST . getRegisterInfo ( ) ; SavedRegs . resize ( HRI . getNumRegs ( ) ) ; if ( MF . getInfo < HexagonMachineFunctionInfo > ( ) -> hasEHReturn ( ) ) for ( const MCPhysReg * R = HRI . getCalleeSavedRegs ( & MF ) ; * R ; ++ R ) SavedRegs . set ( * R ) ; SmallVector < unsigned , 8 > NewRegs ; expandSpillMacros ( MF , NewRegs ) ; if ( OptimizeSpillSlots && ! isOptNone ( MF ) ) optimizeSpillSlots ( MF , NewRegs ) ; if ( ! NewRegs . empty ( ) || mayOverflowFrameOffset ( MF ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; SetVector < const TargetRegisterClass * > SpillRCs ; SpillRCs . insert ( & Hexagon :: IntRegsRegClass ) ; for ( unsigned VR : NewRegs ) SpillRCs . insert ( MRI . getRegClass ( VR ) ) ; for ( auto * RC : SpillRCs ) { if ( ! needToReserveScavengingSpillSlots ( MF , HRI , RC ) ) continue ; unsigned Num = RC == & Hexagon :: IntRegsRegClass ? NumberScavengerSlots : 1 ; unsigned S = HRI . getSpillSize ( * RC ) , A = HRI . getSpillAlignment ( * RC ) ; for ( unsigned i = 0 ; i < Num ; i ++ ) { int NewFI = MFI . CreateSpillStackObject ( S , A ) ; RS -> addScavengingFrameIndex ( NewFI ) ; } } } TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .

Hexagon Hexagon Hexagon Hexagon 8 Hexagon::IntRegsRegClass Hexagon::IntRegsRegClass 1 0


<s> static void aarch64_expand_fpsr_fpcr_setter ( int unspec , machine_mode mode , tree exp ) { tree arg = CALL_EXPR_ARG ( exp , 0 ) ; rtx op = force_reg ( mode , expand_normal ( arg ) ) ; emit_insn ( gen_aarch64_set ( unspec , mode , op ) ) ; } </s>

Expand an expression EXP as fpsr or fpcr setter ( depending on UNSPEC ) using MODE .


<s> static tree ix86_builtin_reciprocal ( unsigned int fn , bool md_fn , bool ) { if ( ! ( TARGET_SSE_MATH && ! optimize_insn_for_size_p ( ) && flag_finite_math_only && ! flag_trapping_math && flag_unsafe_math_optimizations ) ) return NULL_TREE ; if ( md_fn ) switch ( fn ) { case IX86_BUILTIN_SQRTPS_NR : return ix86_get_builtin ( IX86_BUILTIN_RSQRTPS_NR ) ; case IX86_BUILTIN_SQRTPS_NR256 : return ix86_get_builtin ( IX86_BUILTIN_RSQRTPS_NR256 ) ; default : return NULL_TREE ; } else switch ( fn ) { case BUILT_IN_SQRTF : return ix86_get_builtin ( IX86_BUILTIN_RSQRTF ) ; default : return NULL_TREE ; } } </s>

Returns a code for a target-specific builtin that implements reciprocal of the function , or NULL_TREE if not available .


<s> bool HexagonGenPredicate :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; TII = MF . getSubtarget < HexagonSubtarget > ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget < HexagonSubtarget > ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; PredGPRs . clear ( ) ; PUsers . clear ( ) ; G2P . clear ( ) ; bool Changed = false ; collectPredicateGPR ( MF ) ; for ( const RegisterSubReg & R : PredGPRs ) processPredicateGPR ( R ) ; bool Again ; do { Again = false ; VectOfInst Processed , Copy ; Copy = PUsers ; for ( MachineInstr * MI : Copy ) { bool Done = convertToPredForm ( MI ) ; if ( Done ) { Processed . insert ( MI ) ; Again = true ; } } Changed |= Again ; auto Done = [ Processed ] ( MachineInstr * MI ) -> bool { return Processed . count ( MI ) ; } ; PUsers . remove_if ( Done ) ; } while ( Again ) ; Changed |= eliminatePredCopies ( MF ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> const TargetRegisterClass * RISCVRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & ) const { if ( RC == & RISCV :: VMV0RegClass ) return & RISCV :: VRRegClass ; return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .

RISCV RISCV RISCV::VMV0RegClass RISCV::VRRegClass


<s> bool isToken ( ) const { return Kind == Token ; } </s>


<s> static dispatch_windows * allocate_window ( void ) { dispatch_windows * new_list = XNEW ( struct dispatch_windows_s ) ; new_list -> window = XNEWVEC ( struct sched_insn_info_s , MAX_INSN + 1 ) ; return new_list ; } </s>

This function allocates and initializes a dispatch window and the list container holding a pointer to the window .


"There are no defined alternate asm variants"

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> static unsigned int aarch64_case_values_threshold ( void ) { if ( optimize > 2 && selected_cpu -> tune -> max_case_values != 0 ) return selected_cpu -> tune -> max_case_values ; else return default_case_values_threshold ( ) ; } </s>


Return an array that contains the direct target flag values and their names .


<s> void PPCInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { const char * RegName = getRegisterName ( RegNo ) ; OS << RegName ; } </s>


<s> Register ( ) { X86TargetMachine :: registerAsmPrinter ( createX86CodePrinterPass ) ; } </s>


<s>
const
char
*
mcore_output_move
(
rtx
insn
ATTRIBUTE_UNUSED
,
rtx
operands
[
]
,
machine_mode
mode
ATTRIBUTE_UNUSED
)
{
rtx
dst
=
operands
[
0
]
;
rtx
src
=
operands
[
1
]
;
if
(
GET_CODE
(
dst
)
==
REG
)
{
if
(
GET_CODE
(
src
)
==
REG
)
{
if
(
REGNO
(
src
)
==
CC_REG
)
return
"mvc\t%0"
;
else
return
"mov\t%0,%1"
;
}
else
if
(
GET_CODE
(
src
)
==
MEM
)
{
if
(
GET_CODE
(
XEXP
(
src
,
0
)
)
==
LABEL_REF
)
return
"lrw\t%0,[%1]"
;
else
switch
(
GET_MODE
(
src
)
)
{
case
SImode
:
return
"ldw\t%0,%1"
;
case
HImode
:
return
"ld.h\t%0,%1"
;
case
QImode
:
return
"ld.b\t%0,%1"
;
default
:
gcc_unreachable
(
)
;
}
}
else
if
(
GET_CODE
(
src
)
==
CONST_INT
)
{
HOST_WIDE_INT
x
,
y
;
if
(
CONST_OK_FOR_I
(
INTVAL
(
src
)
)
)
return
"movi\t%0,%1"
;
else
if
(
CONST_OK_FOR_M
(
INTVAL
(
src
)
)
)
return
"bgeni\t%0,%P1\t// %1 %x1"
;
else
if
(
CONST_OK_FOR_N
(
INTVAL
(
src
)
)
)
return
"bmaski\t%0,%N1\t// %1 %x1"
;
else
if
(
try_constant_tricks
(
INTVAL
(
src
)
,
&
x
,
&
y
)
)
return
output_inline_const
(
SImode
,
operands
)
;
else
return
"lrw\t%0,%x1\t// %1"
;
}
else
return
"lrw\t%0, %1"
;
}
else
if
(
GET_CODE
(
dst
)
==
MEM
)
switch
(
GET_MODE
(
dst
)
)
{
case
SImode
:
return
"stw\t%1,%0"
;
case
HImode
:
return
"st.h\t%1,%0"
;
case
QImode
:
return
"st.b\t%1,%0"
;
default
:
gcc_unreachable
(
)
;
}
gcc_unreachable
(
)
;
}
</s>


<s> void VEInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & OS ) { if ( ! printAliasInstr ( MI , Address , STI , OS ) ) printInstruction ( MI , Address , STI , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static bool frv_assemble_integer ( rtx value , unsigned int size , int aligned_p ) { if ( ( flag_pic || TARGET_FDPIC ) && size == UNITS_PER_WORD ) { if ( GET_CODE ( value ) == CONST || GET_CODE ( value ) == SYMBOL_REF || GET_CODE ( value ) == LABEL_REF ) { if ( TARGET_FDPIC && GET_CODE ( value ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( value ) ) { fputs ( "\t.picptr\tfuncdesc(" , asm_out_file ) ; output_addr_const ( asm_out_file , value ) ; fputs ( ")\n" , asm_out_file ) ; return true ; } else if ( TARGET_FDPIC && GET_CODE ( value ) == CONST && frv_function_symbol_referenced_p ( value ) ) return false ; if ( aligned_p && ! TARGET_FDPIC ) { static int label_num = 0 ; char buf [ 256 ] ; const char * p ; ASM_GENERATE_INTERNAL_LABEL ( buf , "LCP" , label_num ++ ) ; p = ( * targetm . strip_name_encoding ) ( buf ) ; fprintf ( asm_out_file , "%s:\n" , p ) ; fprintf ( asm_out_file , "%s\n" , FIXUP_SECTION_ASM_OP ) ; fprintf ( asm_out_file , "\t.picptr\t%s\n" , p ) ; fprintf ( asm_out_file , "\t.previous\n" ) ; } assemble_integer_with_op ( "\t.picptr\t" , value ) ; return true ; } if ( ! aligned_p ) { assemble_integer_with_op ( "\t.4byte\t" , value ) ; return true ; } } return default_assemble_integer ( value , size , aligned_p ) ; } </s>

Implementation of TARGET_ASM_INTEGER . In the FRV case we need to use `` .picptr '' to generate safe relocations for PIC code . We also need a fixup entry for aligned ( non-debugging ) code .


<s>
const
char
*
output_mov_long_double_arm_from_fpa
(
rtx
*
operands
)
{
int
arm_reg0
=
REGNO
(
operands
[
0
]
)
;
rtx
ops
[
3
]
;
gcc_assert
(
arm_reg0
!=
IP_REGNUM
)
;
ops
[
0
]
=
gen_rtx_REG
(
SImode
,
arm_reg0
)
;
ops
[
1
]
=
gen_rtx_REG
(
SImode
,
1
+
arm_reg0
)
;
ops
[
2
]
=
gen_rtx_REG
(
SImode
,
2
+
arm_reg0
)
;
output_asm_insn
(
"stf%?e\t%1, [%|sp, #-12]!"
,
operands
)
;
output_asm_insn
(
"ldm%?fd\t%|sp!, {%0, %1, %2}"
,
ops
)
;
return
""
;
}
</s>

Output a move from an fpa register to arm registers . OPERANDS [ 0 ] is the first registers of an arm register pair . OPERANDS [ 1 ] is an fpa register .


<s> LLVM_READONLY const MachineOperand * getNamedOperand ( const MachineInstr & MI , unsigned OpName ) const { return getNamedOperand ( const_cast < MachineInstr & > ( MI ) , OpName ) ; } </s>


"Custom lowering not defined for operation"

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool ARMFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getTarget ( ) . getRegisterInfo ( ) ; if ( STI . isTargetDarwin ( ) ) return true ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( ( DisableFramePointerElim ( MF ) && MFI -> hasCalls ( ) ) || RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool X86TTIImpl :: isLegalMaskedGather ( Type * DataTy ) { if ( ! ( ST -> hasAVX512 ( ) || ( ST -> hasFastGather ( ) && ST -> hasAVX2 ( ) ) ) ) return false ; if ( isa < VectorType > ( DataTy ) ) { unsigned NumElts = DataTy -> getVectorNumElements ( ) ; if ( NumElts == 1 || ! isPowerOf2_32 ( NumElts ) ) return false ; } Type * ScalarTy = DataTy -> getScalarType ( ) ; if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == 32 || IntWidth == 64 ; } </s>

Return true if the target supports masked gather .


<s> static rtx ix86_expand_int_compare ( enum rtx_code code , rtx op0 , rtx op1 ) { enum machine_mode cmpmode ; rtx tmp , flags ; cmpmode = SELECT_CC_MODE ( code , op0 , op1 ) ; flags = gen_rtx_REG ( cmpmode , FLAGS_REG ) ; tmp = gen_rtx_COMPARE ( cmpmode , op0 , op1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , flags , tmp ) ) ; return gen_rtx_fmt_ee ( code , VOIDmode , flags , const0_rtx ) ; } </s>

Generate insn patterns to do an integer compare of OPERANDS .


<s> opt_machine_mode get_vector_mode ( scalar_mode inner_mode , poly_uint64 nunits ) { enum mode_class mclass ; if ( inner_mode == E_BImode ) mclass = MODE_VECTOR_BOOL ; else if ( FLOAT_MODE_P ( inner_mode ) ) mclass = MODE_VECTOR_FLOAT ; else mclass = MODE_VECTOR_INT ; machine_mode mode ; FOR_EACH_MODE_IN_CLASS ( mode , mclass ) if ( inner_mode == GET_MODE_INNER ( mode ) && known_eq ( nunits , GET_MODE_NUNITS ( mode ) ) && riscv_v_ext_vector_mode_p ( mode ) ) return mode ; return opt_machine_mode ( ) ; } </s>

Return the RVV vector mode that has NUNITS elements of mode INNER_MODE . This function is not only used by builtins , but also will be used by auto-vectorization in the future .


<s> unsigned ARMBaseRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; const TargetFrameLowering * TFI = STI . getFrameLowering ( ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case ARM :: tGPRRegClassID : return TFI -> hasFP ( MF ) ? 4 : 5 ; case ARM :: GPRRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 10 - FP - ( STI . isR9Reserved ( ) ? 1 : 0 ) ; } case ARM :: SPRRegClassID : case ARM :: DPRRegClassID : return 32 - 10 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> static opt_machine_mode aarch64_array_mode ( machine_mode mode , unsigned HOST_WIDE_INT nelems ) { if ( aarch64_classify_vector_mode ( mode ) == VEC_SVE_DATA && IN_RANGE ( nelems , 2 , 4 ) ) return mode_for_vector ( GET_MODE_INNER ( mode ) , GET_MODE_NUNITS ( mode ) * nelems ) ; return opt_machine_mode ( ) ; } </s>

Implement target hook TARGET_ARRAY_MODE .


<s> virtual const Tile64RegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> inline void printRegName ( raw_ostream & O , unsigned RegNo ) const override { printFormattedRegName ( & MAI , RegNo , O ) ; } </s>


<s> static tree ix86_vectorize_builtin_scatter ( const_tree vectype , const_tree index_type , int scale ) { bool si ; enum ix86_builtins code ; if ( ! TARGET_AVX512F ) return NULL_TREE ; if ( ( TREE_CODE ( index_type ) != INTEGER_TYPE && ! POINTER_TYPE_P ( index_type ) ) || ( TYPE_MODE ( index_type ) != SImode && TYPE_MODE ( index_type ) != DImode ) ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) > POINTER_SIZE ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) < POINTER_SIZE && TYPE_UNSIGNED ( index_type ) ) return NULL_TREE ; if ( scale <= 0 || scale > 8 || ( scale & ( scale - 1 ) ) != 0 ) return NULL_TREE ; si = TYPE_MODE ( index_type ) == SImode ; switch ( TYPE_MODE ( vectype ) ) { case V8DFmode : code = si ? IX86_BUILTIN_SCATTERALTSIV8DF : IX86_BUILTIN_SCATTERDIV8DF ; break ; case V8DImode : code = si ? IX86_BUILTIN_SCATTERALTSIV8DI : IX86_BUILTIN_SCATTERDIV8DI ; break ; case V16SFmode : code = si ? IX86_BUILTIN_SCATTERSIV16SF : IX86_BUILTIN_SCATTERALTDIV16SF ; break ; case V16SImode : code = si ? IX86_BUILTIN_SCATTERSIV16SI : IX86_BUILTIN_SCATTERALTDIV16SI ; break ; default : return NULL_TREE ; } return ix86_builtins [ code ] ; } </s>

Returns a decl of a function that implements scatter store with register type VECTYPE and index type INDEX_TYPE and SCALE . Return NULL_TREE if it is not available .


<s> static NodeType * getEntryNode ( SPScope * S ) { return S ; } </s>

Return the token chain corresponding to the entry of the function .


<s> bool isToken ( ) const override { return Kind == Token ; } </s>


<s> AArch64Subtarget :: AArch64Subtarget ( StringRef TT , StringRef CPU , StringRef FS ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , HasFPARMv8 ( false ) , HasNEON ( false ) , HasCrypto ( false ) , TargetTriple ( TT ) , CPUString ( CPU ) { initializeSubtargetFeatures ( CPU , FS ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> void MipsRegisterInfo :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = prior ( MBB . end ( ) ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; int FPOffset = MipsFI -> getFPStackOffset ( ) ; int RAOffset = MipsFI -> getRAStackOffset ( ) ; if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDu ) , Mips :: SP ) . addReg ( Mips :: FP ) . addReg ( Mips :: ZERO ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: LW ) , Mips :: FP ) . addImm ( FPOffset ) . addReg ( Mips :: SP ) ; } if ( MFI -> adjustsStack ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: LW ) , Mips :: RA ) . addImm ( RAOffset ) . addReg ( Mips :: SP ) ; } if ( NumBytes ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDiu ) , Mips :: SP ) . addReg ( Mips :: SP ) . addImm ( NumBytes ) ; } } </s>

Mips Mips Mips Mips Mips Mips Mips Mips::ADDu Mips::SP Mips::FP Mips::ZERO Mips::LW Mips::FP Mips::SP Mips::LW Mips::RA Mips::SP Mips::ADDiu Mips::SP Mips::SP


<s> static void aarch64_emit_mult ( rtx dst , rtx ptrue , rtx src1 , rtx src2 ) { if ( ptrue ) emit_insn ( gen_aarch64_pred ( UNSPEC_COND_FMUL , GET_MODE ( dst ) , dst , ptrue , src1 , src2 , gen_int_mode ( SVE_RELAXED_GP , SImode ) ) ) ; else emit_set_insn ( dst , gen_rtx_MULT ( GET_MODE ( dst ) , src1 , src2 ) ) ; } </s>

Emit code to perform the floating-point operation : DST = SRC1 * SRC2 where all three operands are already known to be registers . If the operation is an SVE one , PTRUE is a suitable all-true predicate .


<s>
bool
AArch64TargetLowering
::
lowerInterleavedStore
(
StoreInst
*
SI
,
ShuffleVectorInst
*
SVI
,
unsigned
Factor
)
const
{
assert
(
Factor
>=
2
&&
Factor
<=
getMaxSupportedInterleaveFactor
(
)
&&
"Invalid interleave factor"
)
;
VectorType
*
VecTy
=
SVI
->
getType
(
)
;
assert
(
VecTy
->
getVectorNumElements
(
)
%
Factor
==
0
&&
"Invalid interleaved store"
)
;
unsigned
NumSubElts
=
VecTy
->
getVectorNumElements
(
)
/
Factor
;
Type
*
EltTy
=
VecTy
->
getVectorElementType
(
)
;
VectorType
*
SubVecTy
=
VectorType
::
get
(
EltTy
,
NumSubElts
)
;
const
DataLayout
&
DL
=
SI
->
getModule
(
)
->
getDataLayout
(
)
;
unsigned
SubVecSize
=
DL
.
getTypeAllocSizeInBits
(
SubVecTy
)
;
if
(
SubVecSize
!=
64
&&
SubVecSize
!=
128
)
return
false
;
Value
*
Op0
=
SVI
->
getOperand
(
0
)
;
Value
*
Op1
=
SVI
->
getOperand
(
1
)
;
IRBuilder
<
>
Builder
(
SI
)
;
if
(
EltTy
->
isPointerTy
(
)
)
{
Type
*
IntTy
=
DL
.
getIntPtrType
(
EltTy
)
;
unsigned
NumOpElts
=
dyn_cast
<
VectorType
>
(
Op0
->
getType
(
)
)
->
getVectorNumElements
(
)
;
Type
*
IntVecTy
=
VectorType
::
get
(
IntTy
,
NumOpElts
)
;
Op0
=
Builder
.
CreatePtrToInt
(
Op0
,
IntVecTy
)
;
Op1
=
Builder
.
CreatePtrToInt
(
Op1
,
IntVecTy
)
;
SubVecTy
=
VectorType
::
get
(
IntTy
,
NumSubElts
)
;
}
Type
*
PtrTy
=
SubVecTy
->
getPointerTo
(
SI
->
getPointerAddressSpace
(
)
)
;
Type
*
Tys
[
2
]
=
{
SubVecTy
,
PtrTy
}
;
static
const
Intrinsic
::
ID
StoreInts
[
3
]
=
{
Intrinsic
::
aarch64_neon_st2
,
Intrinsic
::
aarch64_neon_st3
,
Intrinsic
::
aarch64_neon_st4
}
;
Function
*
StNFunc
=
Intrinsic
::
getDeclaration
(
SI
->
getModule
(
)
,
StoreInts
[
Factor
2
]
,
Tys
)
;
SmallVector
<
Value
*
,
5
>
Ops
;
for
(
unsigned
i
=
0
;
i
<
Factor
;
i
++
)
Ops
.
push_back
(
Builder
.
CreateShuffleVector
(
Op0
,
Op1
,
getSequentialMask
(
Builder
,
NumSubElts
*
i
,
NumSubElts
)
)
)
;
Ops
.
push_back
(
Builder
.
CreateBitCast
(
SI
->
getPointerOperand
(
)
,
PtrTy
)
)
;
Builder
.
CreateCall
(
StNFunc
,
Ops
)
;
return
true
;
}
</s>

Lower interleaved store ( s ) into target specific instructions/intrinsics .


<s> static void emit_load_locked ( enum machine_mode mode , rtx reg , rtx mem ) { rtx ( * fn ) ( rtx , rtx ) = NULL ; if ( mode == SImode ) fn = gen_load_locked_si ; else if ( mode == DImode ) fn = gen_load_locked_di ; emit_insn ( fn ( reg , mem ) ) ; } </s>

A subroutine of the atomic operation splitters . Emit a load-locked instruction in MODE . For QI/HImode , possibly use a pattern than includes the zero_extend operation .


<s> bool ARMBaseRegisterInfo :: getRegAllocationHints ( unsigned VirtReg , ArrayRef < MCPhysReg > Order , SmallVectorImpl < MCPhysReg > & Hints , const MachineFunction & MF , const VirtRegMap * VRM , const LiveRegMatrix * Matrix ) const { const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; std :: pair < unsigned , unsigned > Hint = MRI . getRegAllocationHint ( VirtReg ) ; unsigned Odd ; switch ( Hint . first ) { case ARMRI :: RegPairEven : Odd = 0 ; break ; case ARMRI :: RegPairOdd : Odd = 1 ; break ; default : TargetRegisterInfo :: getRegAllocationHints ( VirtReg , Order , Hints , MF , VRM ) ; return false ; } unsigned Paired = Hint . second ; if ( Paired == 0 ) return false ; unsigned PairedPhys = 0 ; if ( Register :: isPhysicalRegister ( Paired ) ) { PairedPhys = Paired ; } else if ( VRM && VRM -> hasPhys ( Paired ) ) { PairedPhys = getPairedGPR ( VRM -> getPhys ( Paired ) , Odd , this ) ; } if ( PairedPhys && is_contained ( Order , PairedPhys ) ) Hints . push_back ( PairedPhys ) ; for ( unsigned Reg : Order ) { if ( Reg == PairedPhys || ( getEncodingValue ( Reg ) & 1 ) != Odd ) continue ; unsigned Paired = getPairedGPR ( Reg , ! Odd , this ) ; if ( ! Paired || MRI . isReserved ( Paired ) ) continue ; Hints . push_back ( Reg ) ; } return false ; } </s>

Get a list of 'hint ' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg .


<s> std :: pair < unsigned , unsigned > DLXInstrInfo :: decomposeMachineOperandsTargetFlags ( unsigned TF ) const { return std :: make_pair ( TF , 0u ) ; } </s>

Decompose the machine operand 's target flags into two values - the direct target flag value and any of bit flags that are applied .


<s> static void rx_get_stack_layout ( unsigned int * lowest , unsigned int * highest , unsigned int * register_mask , unsigned int * frame_size , unsigned int * stack_size ) { unsigned int reg ; unsigned int low ; unsigned int high ; unsigned int fixed_reg = 0 ; unsigned int save_mask ; unsigned int pushed_mask ; unsigned int unneeded_pushes ; if ( is_naked_func ( NULL_TREE ) ) { * lowest = 0 ; * highest = 0 ; * register_mask = 0 ; * frame_size = 0 ; * stack_size = 0 ; return ; } for ( save_mask = high = low = 0 , reg = 1 ; reg < CC_REGNUM ; reg ++ ) { if ( ( df_regs_ever_live_p ( reg ) || ( call_used_or_fixed_reg_p ( reg ) && is_interrupt_func ( NULL_TREE ) && ! crtl -> is_leaf ) ) && ( ! call_used_or_fixed_reg_p ( reg ) || is_interrupt_func ( NULL_TREE ) || ( is_fast_interrupt_func ( NULL_TREE ) && ! IN_RANGE ( reg , 10 , 13 ) ) ) ) { if ( low == 0 ) low = reg ; high = reg ; save_mask |= 1 << reg ; } if ( low != 0 && fixed_reg == 0 && fixed_regs [ reg ] ) fixed_reg = reg ; } if ( MUST_SAVE_ACC_REGISTER && bit_count ( save_mask ) < 2 ) { save_mask |= ( 1 << 13 ) | ( 1 << 14 ) ; if ( low == 0 ) low = 13 ; if ( high == 0 || low == high ) high = low + 1 ; } pushed_mask = ( HOST_WIDE_INT_M1U << low ) & ~ ( HOST_WIDE_INT_M1U << ( high + 1 ) ) ; unneeded_pushes = ( pushed_mask & ( ~ save_mask ) ) & pushed_mask ; if ( ( fixed_reg && fixed_reg <= high ) || ( optimize_function_for_speed_p ( cfun ) && bit_count ( save_mask ) < bit_count ( unneeded_pushes ) ) ) { * lowest = 0 ; * highest = 0 ; * register_mask = save_mask ; } else { * lowest = low ; * highest = high ; * register_mask = 0 ; } * frame_size = rx_round_up ( get_frame_size ( ) , STACK_BOUNDARY / BITS_PER_UNIT ) ; if ( crtl -> args . size > 0 ) * frame_size += rx_round_up ( crtl -> args . size , STACK_BOUNDARY / BITS_PER_UNIT ) ; * stack_size = rx_round_up ( crtl -> outgoing_args_size , STACK_BOUNDARY / BITS_PER_UNIT ) ; } </s>

Returns either the lowest numbered and highest numbered registers that occupy the call-saved area of the stack frame , if the registers are stored as a contiguous block , or else a bitmask of the individual registers if they are stored piecemeal . Also computes the size of the frame and the size of the outgoing arguments block ( in bytes ) .


<s> const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> const MCPhysReg * NVPTXRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * ) const { static const MCPhysReg CalleeSavedRegs [ ] = { 0 } ; return CalleeSavedRegs ; } </s>


<s>
bool
ARM64AdvSIMDScalar
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
bool
Changed
=
false
;
DEBUG
(
dbgs
(
)
<<
"***** ARM64AdvSIMDScalar *****\n"
)
;
const
TargetMachine
&
TM
=
mf
.
getTarget
(
)
;
MRI
=
&
mf
.
getRegInfo
(
)
;
TII
=
static_cast
<
const
ARM64InstrInfo
*
>
(
TM
.
getInstrInfo
(
)
)
;
for
(
MachineFunction
::
iterator
I
=
mf
.
begin
(
)
,
E
=
mf
.
end
(
)
;
I
!=
E
;
++
I
)
if
(
processMachineBasicBlock
(
I
)
)
Changed
=
true
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool HexagonFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const HexagonMachineFunctionInfo * FuncInfo = MF . getInfo < HexagonMachineFunctionInfo > ( ) ; return MFI -> hasCalls ( ) || MFI -> getStackSize ( ) > 0 || FuncInfo -> hasClobberLR ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool WebAssemblyPassConfig :: addInstSelector ( ) { ( void ) TargetPassConfig :: addInstSelector ( ) ; addPass ( createWebAssemblyISelDag ( getWebAssemblyTargetMachine ( ) , getOptLevel ( ) ) ) ; addPass ( createWebAssemblyArgumentMove ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .

WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly


<s> int X86InstrInfo :: getSPAdjust ( const MachineInstr * MI ) const { const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const TargetFrameLowering * TFI = MF -> getSubtarget ( ) . getFrameLowering ( ) ; if ( MI -> getOpcode ( ) == getCallFrameSetupOpcode ( ) || MI -> getOpcode ( ) == getCallFrameDestroyOpcode ( ) ) { unsigned StackAlign = TFI -> getStackAlignment ( ) ; int SPAdj = ( MI -> getOperand ( 0 ) . getImm ( ) + StackAlign - 1 ) / StackAlign * StackAlign ; SPAdj -= MI -> getOperand ( 1 ) . getImm ( ) ; if ( MI -> getOpcode ( ) == getCallFrameSetupOpcode ( ) ) return SPAdj ; else return - SPAdj ; } if ( MI -> isCall ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; auto I = ++ MachineBasicBlock :: const_iterator ( MI ) ; for ( auto E = MBB -> end ( ) ; I != E ; ++ I ) { if ( I -> getOpcode ( ) == getCallFrameDestroyOpcode ( ) || I -> isCall ( ) ) break ; } if ( I -> getOpcode ( ) != getCallFrameDestroyOpcode ( ) ) return 0 ; return - ( I -> getOperand ( 1 ) . getImm ( ) ) ; } switch ( MI -> getOpcode ( ) ) { default : return 0 ; case X86 :: PUSH32i8 : case X86 :: PUSH32r : case X86 :: PUSH32rmm : case X86 :: PUSH32rmr : case X86 :: PUSHi32 : return 4 ; } } </s>

getSPAdjust - This returns the stack pointer adjustment made by this instruction .


<s> bool isToken ( ) const override { return Kind == KindTy :: Token ; } </s>


<s> const uint16_t * AVRRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const AVRMachineFunctionInfo * AFI = MF -> getInfo < AVRMachineFunctionInfo > ( ) ; return AFI -> isInterruptOrSignalHandler ( ) ? CSR_Interrupts_SaveList : CSR_Normal_SaveList ; } </s>


<s> void alpha_split_tmode_pair ( rtx operands [ 4 ] , machine_mode mode , bool fixup_overlap ) { switch ( GET_CODE ( operands [ 1 ] ) ) { case REG : operands [ 3 ] = gen_rtx_REG ( DImode , REGNO ( operands [ 1 ] ) + 1 ) ; operands [ 2 ] = gen_rtx_REG ( DImode , REGNO ( operands [ 1 ] ) ) ; break ; case MEM : operands [ 3 ] = adjust_address ( operands [ 1 ] , DImode , 8 ) ; operands [ 2 ] = adjust_address ( operands [ 1 ] , DImode , 0 ) ; break ; CASE_CONST_SCALAR_INT : case CONST_DOUBLE : gcc_assert ( operands [ 1 ] == CONST0_RTX ( mode ) ) ; operands [ 2 ] = operands [ 3 ] = const0_rtx ; break ; default : gcc_unreachable ( ) ; } switch ( GET_CODE ( operands [ 0 ] ) ) { case REG : operands [ 1 ] = gen_rtx_REG ( DImode , REGNO ( operands [ 0 ] ) + 1 ) ; operands [ 0 ] = gen_rtx_REG ( DImode , REGNO ( operands [ 0 ] ) ) ; break ; case MEM : operands [ 1 ] = adjust_address ( operands [ 0 ] , DImode , 8 ) ; operands [ 0 ] = adjust_address ( operands [ 0 ] , DImode , 0 ) ; break ; default : gcc_unreachable ( ) ; } if ( fixup_overlap && reg_overlap_mentioned_p ( operands [ 0 ] , operands [ 3 ] ) ) { std :: swap ( operands [ 0 ] , operands [ 1 ] ) ; std :: swap ( operands [ 2 ] , operands [ 3 ] ) ; } } </s>

Split a TImode or TFmode move from OP [ 1 ] to OP [ 0 ] into a pair of DImode moves from OP [ 2,3 ] to OP [ 0,1 ] . If FIXUP_OVERLAP is true , guarantee that the sequence set ( OP [ 0 ] OP [ 2 ] ) set ( OP [ 1 ] OP [ 3 ] ) is valid . Naturally , output operand ordering is little-endian . This is used by * movtf_internal and * movti_internal .


<s>
const
char
*
emit_fusion_p9_load
(
rtx
reg
,
rtx
mem
,
rtx
tmp_reg
)
{
machine_mode
mode
=
GET_MODE
(
reg
)
;
rtx
hi
;
rtx
lo
;
rtx
addr
;
const
char
*
load_string
;
int
r
;
if
(
GET_CODE
(
mem
)
==
FLOAT_EXTEND
||
GET_CODE
(
mem
)
==
ZERO_EXTEND
)
{
mem
=
XEXP
(
mem
,
0
)
;
mode
=
GET_MODE
(
mem
)
;
}
if
(
GET_CODE
(
reg
)
==
SUBREG
)
{
gcc_assert
(
SUBREG_BYTE
(
reg
)
==
0
)
;
reg
=
SUBREG_REG
(
reg
)
;
}
if
(
!
REG_P
(
reg
)
)
fatal_insn
(
"emit_fusion_p9_load, bad reg #1"
,
reg
)
;
r
=
REGNO
(
reg
)
;
if
(
FP_REGNO_P
(
r
)
)
{
if
(
mode
==
SFmode
)
load_string
=
"lfs"
;
else
if
(
mode
==
DFmode
||
mode
==
DImode
)
load_string
=
"lfd"
;
else
gcc_unreachable
(
)
;
}
else
if
(
ALTIVEC_REGNO_P
(
r
)
&&
TARGET_P9_VECTOR
)
{
if
(
mode
==
SFmode
)
load_string
=
"lxssp"
;
else
if
(
mode
==
DFmode
||
mode
==
DImode
)
load_string
=
"lxsd"
;
else
gcc_unreachable
(
)
;
}
else
if
(
INT_REGNO_P
(
r
)
)
{
switch
(
mode
)
{
case
E_QImode
:
load_string
=
"lbz"
;
break
;
case
E_HImode
:
load_string
=
"lhz"
;
break
;
case
E_SImode
:
case
E_SFmode
:
load_string
=
"lwz"
;
break
;
case
E_DImode
:
case
E_DFmode
:
if
(
!
TARGET_POWERPC64
)
gcc_unreachable
(
)
;
load_string
=
"ld"
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
else
fatal_insn
(
"emit_fusion_p9_load, bad reg #2"
,
reg
)
;
if
(
!
MEM_P
(
mem
)
)
fatal_insn
(
"emit_fusion_p9_load not MEM"
,
mem
)
;
addr
=
XEXP
(
mem
,
0
)
;
fusion_split_address
(
addr
,
&
hi
,
&
lo
)
;
emit_fusion_addis
(
tmp_reg
,
hi
)
;
emit_fusion_load_store
(
reg
,
tmp_reg
,
lo
,
load_string
)
;
return
""
;
}
</s>

Return a string to fuse an addis instruction with a load using extended fusion . The address that is used is the logical address that was formed during peephole2 : ( lo_sum ( high ) ( low-part ) ) The code is complicated , so we call output_asm_insn directly , and just return `` '' .

rs6000
0
0
"emit_fusion_p9_load, bad reg #1"
"lfs"
"lfd"
"lxssp"
"lxsd"
"lbz"
"lhz"
"lwz"
"ld"
"emit_fusion_p9_load, bad reg #2"
"emit_fusion_p9_load not MEM"
0
""


<s>
void
PatmosInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
MCRegister
DestReg
,
MCRegister
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
;
if
(
Patmos
::
RRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
Opc
=
Patmos
::
MOV
;
}
else
if
(
Patmos
::
RRegsRegClass
.
contains
(
DestReg
)
&&
Patmos
::
PRegsRegClass
.
contains
(
SrcReg
)
)
{
Opc
=
Patmos
::
MOVpr
;
}
else
if
(
Patmos
::
PRegsRegClass
.
contains
(
DestReg
)
&&
Patmos
::
RRegsRegClass
.
contains
(
SrcReg
)
)
{
Opc
=
Patmos
::
MOVrp
;
}
else
if
(
Patmos
::
PRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
Opc
=
Patmos
::
PMOV
;
}
else
if
(
Patmos
::
SRegsRegClass
.
contains
(
DestReg
)
)
{
assert
(
Patmos
::
RRegsRegClass
.
contains
(
SrcReg
)
)
;
Opc
=
Patmos
::
MTS
;
}
else
if
(
Patmos
::
SRegsRegClass
.
contains
(
SrcReg
)
)
{
assert
(
Patmos
::
RRegsRegClass
.
contains
(
DestReg
)
)
;
Opc
=
Patmos
::
MFS
;
}
else
{
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
auto
&
instr
=
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DestReg
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>

Patmos
Patmos
Patmos::RRegsRegClass
Patmos::MOV
Patmos::RRegsRegClass
Patmos::PRegsRegClass
Patmos::MOVpr
Patmos::PRegsRegClass
Patmos::RRegsRegClass
Patmos::MOVrp
Patmos::PRegsRegClass
Patmos::PMOV
Patmos::SRegsRegClass
Patmos::RRegsRegClass
Patmos::MTS
Patmos::SRegsRegClass
Patmos::RRegsRegClass
Patmos::MFS
"Impossible reg-to-reg copy"


<s> static void mips_sim_wait_units ( struct mips_sim * state , rtx_insn * insn ) { state_t tmp_state ; tmp_state = alloca ( state_size ( ) ) ; while ( state -> insns_left == 0 || ( memcpy ( tmp_state , state -> dfa_state , state_size ( ) ) , state_transition ( tmp_state , insn ) >= 0 ) ) mips_sim_next_cycle ( state ) ; } </s>

Advance simulation state STATE until the units required by instruction INSN are available .


<s> static bool rs6000_real_tls_symbol_ref_p ( rtx x ) { return ( SYMBOL_REF_P ( x ) && SYMBOL_REF_TLS_MODEL ( x ) >= TLS_MODEL_REAL ) ; } </s>

Return true if X is a symbol that refers to real ( rather than emulated ) TLS .


<s> static bool c6x_function_in_section_p ( tree decl , section * section ) { if ( ! TREE_STATIC ( decl ) ) return false ; if ( ! targetm . binds_local_p ( decl ) ) return false ; if ( ! DECL_SECTION_NAME ( decl ) ) { if ( flag_function_sections || DECL_COMDAT_GROUP ( decl ) ) return false ; } return function_section ( decl ) == section ; } </s>

Return true if DECL is known to be linked into section SECTION .


<s> bool addPreISel ( ) override { return false ; } </s>


<s> int direct_return ( ) { if ( reload_completed ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; if ( info -> first_gp_reg_save == 32 && info -> first_fp_reg_save == 64 && info -> first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1 && ! info -> lr_save_p && ! info -> cr_save_p && info -> vrsave_mask == 0 && ! info -> push_p ) return 1 ; } return 0 ; } </s>

Return non-zero if this function is known to have a null epilogue .


"%qE attribute only applies to functions"

Handle an attribute requiring a FUNCTION_DECL ; arguments as in struct attribute_spec.handler .


<s> void BPFTargetMachine :: registerPassBuilderCallbacks ( PassBuilder & PB , bool DebugPassManager ) { PB . registerPipelineStartEPCallback ( [ = ] ( ModulePassManager & MPM ) { FunctionPassManager FPM ( DebugPassManager ) ; FPM . addPass ( BPFAbstractMemberAccessPass ( this ) ) ; FPM . addPass ( BPFPreserveDITypePass ( ) ) ; MPM . addPass ( createModuleToFunctionPassAdaptor ( std :: move ( FPM ) ) ) ; } ) ; PB . registerPeepholeEPCallback ( [ = ] ( FunctionPassManager & FPM , PassBuilder :: OptimizationLevel Level ) { FPM . addPass ( SimplifyCFGPass ( SimplifyCFGOptions ( ) . hoistCommonInsts ( true ) ) ) ; } ) ; } </s>

Invoke the PassBuilder callback registration .