<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"TMS320C64X Branch Delay Reducer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"-target-abi option != target-abi module flag"

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool MipsSEFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * EntryBlock = & MF -> front ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == Mips :: RA || Reg == Mips :: RA_64 ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; bool IsLOHI = ( Reg == Mips :: LO0 || Reg == Mips :: LO0_64 || Reg == Mips :: HI0 || Reg == Mips :: HI0_64 ) ; const Function * Func = MBB . getParent ( ) -> getFunction ( ) ; if ( IsLOHI && Func -> hasFnAttribute ( "interrupt" ) ) { DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Op = 0 ; if ( ! STI . getABI ( ) . ArePtrs64bit ( ) ) { Op = ( Reg == Mips :: HI0 ) ? Mips :: MFHI : Mips :: MFLO ; Reg = Mips :: K0 ; } else { Op = ( Reg == Mips :: HI0 ) ? Mips :: MFHI64 : Mips :: MFLO64 ; Reg = Mips :: K0_64 ; } BuildMI ( MBB , MI , DL , TII . get ( Op ) , Mips :: K0 ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> X86Subtarget :: X86Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const X86TargetMachine & TM , unsigned StackAlignOverride ) : X86GenSubtargetInfo ( TT , CPU , FS ) , X86ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , TSInfo ( ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( * this , getStackAlignment ( ) ) { if ( TM . getRelocationModel ( ) == Reloc :: Static ) { setPICStyle ( PICStyles :: None ) ; } else if ( is64Bit ( ) ) { setPICStyle ( PICStyles :: RIPRel ) ; } else if ( isTargetCOFF ( ) ) { setPICStyle ( PICStyles :: None ) ; } else if ( isTargetDarwin ( ) ) { if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( TM . getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( isTargetELF ( ) ) { setPICStyle ( PICStyles :: GOT ) ; } } </s>

This constructor initializes the data members to match that of the specified triple .


<s>
static
void
nios2_print_operand_address
(
FILE
*
file
,
machine_mode
mode
,
rtx
op
)
{
switch
(
GET_CODE
(
op
)
)
{
case
CONST
:
case
CONST_INT
:
case
LABEL_REF
:
case
CONST_DOUBLE
:
case
SYMBOL_REF
:
if
(
gprel_constant_p
(
op
)
)
{
fprintf
(
file
,
"%%gprel("
)
;
output_addr_const
(
file
,
op
)
;
fprintf
(
file
,
")(%s)"
,
reg_names
[
GP_REGNO
]
)
;
return
;
}
break
;
case
PLUS
:
{
rtx
op0
=
XEXP
(
op
,
0
)
;
rtx
op1
=
XEXP
(
op
,
1
)
;
if
(
REG_P
(
op0
)
&&
CONSTANT_P
(
op1
)
)
{
output_addr_const
(
file
,
op1
)
;
fprintf
(
file
,
"(%s)"
,
reg_names
[
REGNO
(
op0
)
]
)
;
return
;
}
else
if
(
REG_P
(
op1
)
&&
CONSTANT_P
(
op0
)
)
{
output_addr_const
(
file
,
op0
)
;
fprintf
(
file
,
"(%s)"
,
reg_names
[
REGNO
(
op1
)
]
)
;
return
;
}
}
break
;
case
REG
:
fprintf
(
file
,
"0(%s)"
,
reg_names
[
REGNO
(
op
)
]
)
;
return
;
case
MEM
:
{
rtx
base
=
XEXP
(
op
,
0
)
;
nios2_print_operand_address
(
file
,
mode
,
base
)
;
return
;
}
default
:
break
;
}
fprintf
(
stderr
,
"Missing way to print address\n"
)
;
debug_rtx
(
op
)
;
gcc_unreachable
(
)
;
}
</s>


<s>
const
char
*
avr_out_ashlpsi3
(
rtx_insn
*
insn
,
rtx
*
op
,
int
*
plen
)
{
if
(
plen
)
*
plen
=
0
;
if
(
CONST_INT_P
(
op
[
2
]
)
)
{
switch
(
INTVAL
(
op
[
2
]
)
)
{
default
:
if
(
INTVAL
(
op
[
2
]
)
<
24
)
break
;
return
avr_asm_len
(
"clr %A0"
CR_TAB
"clr %B0"
CR_TAB
"clr %C0"
,
op
,
plen
,
3
)
;
case
8
:
{
int
reg0
=
REGNO
(
op
[
0
]
)
;
int
reg1
=
REGNO
(
op
[
1
]
)
;
if
(
reg0
>=
reg1
)
return
avr_asm_len
(
"mov %C0,%B1"
CR_TAB
"mov %B0,%A1"
CR_TAB
"clr %A0"
,
op
,
plen
,
3
)
;
else
return
avr_asm_len
(
"clr %A0"
CR_TAB
"mov %B0,%A1"
CR_TAB
"mov %C0,%B1"
,
op
,
plen
,
3
)
;
}
case
16
:
{
int
reg0
=
REGNO
(
op
[
0
]
)
;
int
reg1
=
REGNO
(
op
[
1
]
)
;
if
(
reg0
+
2
!=
reg1
)
avr_asm_len
(
"mov %C0,%A0"
,
op
,
plen
,
1
)
;
return
avr_asm_len
(
"clr %B0"
CR_TAB
"clr %A0"
,
op
,
plen
,
2
)
;
}
case
23
:
return
avr_asm_len
(
"clr %C0"
CR_TAB
"lsr %A0"
CR_TAB
"ror %C0"
CR_TAB
"clr %B0"
CR_TAB
"clr %A0"
,
op
,
plen
,
5
)
;
}
}
out_shift_with_cnt
(
"lsl %A0"
CR_TAB
"rol %B0"
CR_TAB
"rol %C0"
,
insn
,
op
,
plen
,
3
)
;
return
""
;
}
</s>


<s> MVT getScalarShiftAmountTy ( EVT LHSTy ) const override { return MVT :: i8 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


Select appropriate section for constants depending on where we place literal pools .


"Expected label,@type declaration, got: "

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return this -> TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> bool AMDGPUSymbolizer :: tryAddingSymbolicOperand ( MCInst & Inst , raw_ostream & , int64_t Value , uint64_t , bool IsBranch , uint64_t , uint64_t ) { if ( ! IsBranch ) { return false ; } auto * Symbols = static_cast < SectionSymbolsTy * > ( DisInfo ) ; if ( ! Symbols ) return false ; auto Result = std :: find_if ( Symbols -> begin ( ) , Symbols -> end ( ) , [ Value ] ( const SymbolInfoTy & Val ) { return Val . Addr == static_cast < uint64_t > ( Value ) && Val . Type == ELF :: STT_NOTYPE ; } ) ; if ( Result != Symbols -> end ( ) ) { auto * Sym = Ctx . getOrCreateSymbol ( Result -> Name ) ; const auto * Add = MCSymbolRefExpr :: create ( Sym , Ctx ) ; Inst . addOperand ( MCOperand :: createExpr ( Add ) ) ; return true ; } return false ; } </s>

Try to add a symbolic operand instead of Value to the MCInst .


<s> void iq2000_expand_epilogue ( void ) { HOST_WIDE_INT tsize = cfun -> machine -> total_size ; rtx tsize_rtx = GEN_INT ( tsize ) ; rtx tmp_rtx = ( rtx ) 0 ; if ( iq2000_can_use_return_insn ( ) ) { emit_jump_insn ( gen_return ( ) ) ; return ; } if ( tsize > 32767 ) { tmp_rtx = gen_rtx_REG ( Pmode , IQ2000_TEMP1_REGNUM ) ; emit_move_insn ( tmp_rtx , tsize_rtx ) ; tsize_rtx = tmp_rtx ; } if ( tsize > 0 ) { if ( frame_pointer_needed ) { emit_insn ( gen_blockage ( ) ) ; emit_insn ( gen_movsi ( stack_pointer_rtx , hard_frame_pointer_rtx ) ) ; } save_restore_insns ( 0 ) ; if ( crtl -> calls_eh_return ) { rtx eh_ofs = EH_RETURN_STACKADJ_RTX ; emit_insn ( gen_addsi3 ( eh_ofs , eh_ofs , tsize_rtx ) ) ; tsize_rtx = eh_ofs ; } emit_insn ( gen_blockage ( ) ) ; if ( tsize != 0 || crtl -> calls_eh_return ) { emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , tsize_rtx ) ) ; } } if ( crtl -> calls_eh_return ) { emit_move_insn ( gen_rtx_REG ( Pmode , HARD_FRAME_POINTER_REGNUM ) , stack_pointer_rtx ) ; emit_use ( gen_rtx_REG ( Pmode , HARD_FRAME_POINTER_REGNUM ) ) ; emit_jump_insn ( gen_eh_return_internal ( ) ) ; } else emit_jump_insn ( gen_return_internal ( gen_rtx_REG ( Pmode , GP_REG_FIRST + 31 ) ) ) ; } </s>

Expand the epilogue into a bunch of separate insns .


<s> const char * RISCVTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( RISCVISD :: NodeType ) Opcode ) { case RISCVISD :: FIRST_NUMBER : break ; case RISCVISD :: RET_FLAG : return "RISCVISD::RET_FLAG" ; case RISCVISD :: URET_FLAG : return "RISCVISD::URET_FLAG" ; case RISCVISD :: SRET_FLAG : return "RISCVISD::SRET_FLAG" ; case RISCVISD :: MRET_FLAG : return "RISCVISD::MRET_FLAG" ; case RISCVISD :: CALL : return "RISCVISD::CALL" ; case RISCVISD :: SELECT_CC : return "RISCVISD::SELECT_CC" ; case RISCVISD :: BuildPairF64 : return "RISCVISD::BuildPairF64" ; case RISCVISD :: SplitF64 : return "RISCVISD::SplitF64" ; case RISCVISD :: TAIL : return "RISCVISD::TAIL" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> void ScheduleDAGPostRA :: addMutation ( ScheduleDAGPostRAMutation * M ) { Mutations . push_back ( M ) ; } </s>

Add a postprocessing step to the DAG builder .


<s> static void bpf_init_builtins ( void ) { tree ullt = long_long_unsigned_type_node ; def_builtin ( "__builtin_bpf_load_byte" , BPF_BUILTIN_LOAD_BYTE , build_function_type_list ( ullt , ullt , 0 ) ) ; def_builtin ( "__builtin_bpf_load_half" , BPF_BUILTIN_LOAD_HALF , build_function_type_list ( ullt , ullt , 0 ) ) ; def_builtin ( "__builtin_bpf_load_word" , BPF_BUILTIN_LOAD_WORD , build_function_type_list ( ullt , ullt , 0 ) ) ; def_builtin ( "__builtin_preserve_access_index" , BPF_BUILTIN_PRESERVE_ACCESS_INDEX , build_function_type_list ( ptr_type_node , ptr_type_node , 0 ) ) ; def_builtin ( "__builtin_preserve_field_info" , BPF_BUILTIN_PRESERVE_FIELD_INFO , build_function_type_list ( unsigned_type_node , ptr_type_node , unsigned_type_node , 0 ) ) ; } </s>

Define machine-specific built-in functions .


<s> bool X86TargetLowering :: isTruncateFree ( EVT VT1 , EVT VT2 ) const { if ( ! VT1 . isScalarInteger ( ) || ! VT2 . isScalarInteger ( ) ) return false ; unsigned NumBits1 = VT1 . getSizeInBits ( ) ; unsigned NumBits2 = VT2 . getSizeInBits ( ) ; return NumBits1 > NumBits2 ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s>
const
char
*
frv_asm_output_opcode
(
FILE
*
f
,
const
char
*
ptr
)
{
int
c
;
if
(
frv_insn_packing_flag
<=
0
)
return
ptr
;
for
(
;
*
ptr
&&
*
ptr
!=
' '
&&
*
ptr
!=
'\t'
;
)
{
c
=
*
ptr
++
;
if
(
c
==
'%'
&&
(
(
*
ptr
>=
'a'
&&
*
ptr
<=
'z'
)
||
(
*
ptr
>=
'A'
&&
*
ptr
<=
'Z'
)
)
)
{
int
letter
=
*
ptr
++
;
c
=
atoi
(
ptr
)
;
frv_print_operand
(
f
,
frv_insn_operands
[
c
]
,
letter
)
;
while
(
(
c
=
*
ptr
)
>=
'0'
&&
c
<=
'9'
)
ptr
++
;
}
else
fputc
(
c
,
f
)
;
}
fprintf
(
f
,
".p"
)
;
return
ptr
;
}
</s>

The following function is used to add assembler insn code suffix .p if it is necessary .


<s>
void
NVPTXTargetStreamer
::
changeSection
(
const
MCSection
*
CurSection
,
MCSection
*
Section
,
const
MCExpr
*
SubSection
,
raw_ostream
&
OS
)
{
assert
(
!
SubSection
&&
"SubSection is not null!"
)
;
const
MCObjectFileInfo
*
FI
=
getStreamer
(
)
.
getContext
(
)
.
getObjectFileInfo
(
)
;
if
(
isDwarfSection
(
FI
,
CurSection
)
)
OS
<<
"\t}\n"
;
if
(
isDwarfSection
(
FI
,
Section
)
)
{
outputDwarfFileDirectives
(
)
;
OS
<<
"\t.section"
;
Section
->
PrintSwitchToSection
(
*
getStreamer
(
)
.
getContext
(
)
.
getAsmInfo
(
)
,
FI
->
getTargetTriple
(
)
,
OS
,
SubSection
)
;
OS
<<
"\t{\n"
;
HasSections
=
true
;
}
}
</s>

Update streamer for a new active section .

NVPTX
NVPTX
"SubSection is not null!"
"\t}\n"
"\t.section"
"\t{\n"


<s>
SDValue
MSP430TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
FORMAL_ARGUMENTS
:
return
LowerFORMAL_ARGUMENTS
(
Op
,
DAG
)
;
case
ISD
::
SHL
:
case
ISD
::
SRL
:
case
ISD
::
SRA
:
return
LowerShifts
(
Op
,
DAG
)
;
case
ISD
::
RET
:
return
LowerRET
(
Op
,
DAG
)
;
case
ISD
::
CALL
:
return
LowerCALL
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
ExternalSymbol
:
return
LowerExternalSymbol
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SIGN_EXTEND
:
return
LowerSIGN_EXTEND
(
Op
,
DAG
)
;
default
:
assert
(
0
&&
"unimplemented operand"
)
;
return
SDValue
(
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s>
SDValue
HexagonTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
if
(
Subtarget
.
useHVXOps
(
)
)
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_Hexagon_HVX
)
;
else
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_Hexagon
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
SDValue
Val
=
OutVals
[
i
]
;
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
BCvt
:
Val
=
DAG
.
getBitcast
(
VA
.
getLocVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
SExt
:
Val
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
ZExt
:
Val
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
AExt
:
Val
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Val
)
;
break
;
}
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
Val
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
HexagonISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


"Unexpected operand for inline assembly"

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static int aarch64_sched_issue_rate ( void ) { return aarch64_tune_params . issue_rate ; } </s>

Return the number of instructions that can be issued per cycle .


<s>
SDValue
AMDGPUTargetLowering
::
LowerCall
(
CallLoweringInfo
&
CLI
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
return
lowerUnhandledCall
(
CLI
,
InVals
,
"unsupported call to function "
)
;
}
</s>

This hook must be implemented to lower calls into the specified DAG .

AMDGPU
AMDGPU
"unsupported call to function "


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; initialize ( MF ) ; return eliminateTruncSeq ( ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool Thumb1FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; unsigned CFSize = FFI -> getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( 1 << 8 ) - 1 ) * 4 / 2 ) return false ; return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> bool DLXAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { if ( ( Count % 4 ) != 0 ) return false ; for ( uint64_t i = 0 ; i < Count ; i += 4 ) OS . write ( "\x15\0\0\0" , 4 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> char * aarch64_output_sve_cnt_immediate ( const char * prefix , const char * operands , rtx x ) { poly_int64 value = rtx_to_poly_int64 ( x ) ; gcc_assert ( aarch64_sve_cnt_immediate_p ( value ) ) ; return aarch64_output_sve_cnt_immediate ( prefix , operands , AARCH64_SV_ALL , value . coeffs [ 1 ] , 0 ) ; } </s>

Return the asm string for an instruction with a CNT-like vector size operand ( a vector pattern followed by a multiplier in the range [ 1 , 16 ] ) . PREFIX is the mnemonic without the size suffix and OPERANDS is the first part of the operands template ( the part that comes before the vector size itself ) . X is the value of the vector size operand , as a polynomial integer rtx .


<s> FusionKind getKind ( ) const { return Kd ; } </s>


<s> bool FISCPassConfig :: addInstSelector ( ) { addPass ( createFISCISelDag ( getFISCTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> void TPCInstrCompress :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


"parameter passing for argument of type "

Determine where to put an argument to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . On the ARM , normally the first 16 bytes are passed in registers r0-r3 ; all other arguments are passed on the stack . If ( NAMED == 0 ) ( which happens only in assign_parms , since TARGET_SETUP_INCOMING_VARARGS is defined ) , say it is passed in the stack ( function_prologue will indeed make it pass in the stack if necessary ) .


<s> static unsigned int aarch64_function_arg_alignment ( machine_mode mode , const_tree type ) { unsigned int alignment ; if ( type ) { if ( ! integer_zerop ( TYPE_SIZE ( type ) ) ) { if ( TYPE_MODE ( type ) == mode ) alignment = TYPE_ALIGN ( type ) ; else alignment = GET_MODE_ALIGNMENT ( mode ) ; } else alignment = 0 ; } else alignment = GET_MODE_ALIGNMENT ( mode ) ; return alignment ; } </s>

Given MODE and TYPE of a function argument , return the alignment in bits . The idea is to suppress any stronger alignment requested by the user and opt for the natural alignment ( specified in AAPCS64 \S 4.1 ) . This is a helper function for local use only .


<s> const Z80oldRegisterInfo * getRegisterInfo ( ) const override { return & getInstrInfo ( ) -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> unsigned AlphaInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { case Alpha :: STL : case Alpha :: STQ : case Alpha :: STB : case Alpha :: STW : case Alpha :: STS : case Alpha :: STT : if ( MI -> getOperand ( 1 ) . isFI ( ) ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .

Alpha Alpha Alpha::STL Alpha::STQ Alpha::STB Alpha::STW Alpha::STS Alpha::STT 1 1 0 0


Return an array that contains the bitmask target flag values and their names .

PowerPC PPC PPC "ppc-plt" "ppc-pic" "ppc-pcrel" "ppc-got" "ppc-opt-pcrel"


<s> bool isReg ( ) const override { return Kind == k_Register ; } </s>


<s>
bool
ARCInstrInfo
::
reverseBranchCondition
(
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
assert
(
(
Cond
.
size
(
)
==
3
)
&&
"Invalid ARC branch condition!"
)
;
Cond
[
2
]
.
setImm
(
GetOppositeBranchCondition
(
(
ARCCC
::
CondCode
)
Cond
[
2
]
.
getImm
(
)
)
)
;
return
false
;
}
</s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> static bool arm_evpc_neon_vtbl ( struct expand_vec_perm_d * d ) { rtx rperm [ MAX_VECT_LEN ] , sel ; machine_mode vmode = d -> vmode ; unsigned int i , nelt = d -> nelt ; if ( BYTES_BIG_ENDIAN ) return false ; if ( d -> testing_p ) return true ; if ( vmode != V8QImode && vmode != V16QImode ) return false ; for ( i = 0 ; i < nelt ; ++ i ) rperm [ i ] = GEN_INT ( d -> perm [ i ] ) ; sel = gen_rtx_CONST_VECTOR ( vmode , gen_rtvec_v ( nelt , rperm ) ) ; sel = force_reg ( vmode , sel ) ; arm_expand_vec_perm_1 ( d -> target , d -> op0 , d -> op1 , sel ) ; return true ; } </s>

The NEON VTBL instruction is a fully variable permuation that 's even stronger than what we expose via VEC_PERM_EXPR . What it does n't do is mask the index operand as VEC_PERM_EXPR requires . Therefore we can do slightly better by expanding this as a constant where we do n't have to apply a mask .


<s> bool Z80oldTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( AM . Scale ) { return false ; } if ( AM . BaseGV && AM . HasBaseReg ) { return false ; } if ( AM . BaseGV ) { return AM . BaseOffs == 0 ; } if ( AM . HasBaseReg ) { return isInt < 8 > ( AM . BaseOffs ) ; } return false ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> static unsigned getSubRegIndex ( const TargetRegisterClass * RC ) { unsigned SubIdx = X86 :: NoSubRegister ; if ( RC == & X86 :: GR32RegClass ) { SubIdx = X86 :: sub_32bit ; } else if ( RC == & X86 :: GR16RegClass ) { SubIdx = X86 :: sub_16bit ; } else if ( RC == & X86 :: GR8RegClass ) { SubIdx = X86 :: sub_8bit ; } return SubIdx ; } </s>

Check if the given identifier is a name of a subregister index .


<s> bool BPFFrameLowering :: hasFP ( const MachineFunction & MF ) const { return true ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
bool
Nios2AsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNum
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
return
true
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNum
)
;
assert
(
MO
.
isReg
(
)
&&
"unexpected inline asm memory operand"
)
;
O
<<
"($"
<<
Nios2InstPrinter
::
getRegisterName
(
MO
.
getReg
(
)
)
<<
")"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> static int ix86_mode_after ( int entity , int mode , rtx_insn * insn ) { switch ( entity ) { case X86_DIRFLAG : return mode ; case AVX_U128 : return ix86_avx_u128_mode_after ( mode , insn ) ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : return mode ; default : gcc_unreachable ( ) ; } } </s>

Return the mode that an insn results in .


<s> bool arm_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_NEON && ( mode == V2SFmode || mode == V4SImode || mode == V8HImode || mode == V4HFmode || mode == V16QImode || mode == V4SFmode || mode == V2DImode ) ) return true ; if ( ( TARGET_NEON || TARGET_IWMMXT ) && ( ( mode == V2SImode ) || ( mode == V4HImode ) || ( mode == V8QImode ) ) ) return true ; if ( TARGET_INT_SIMD && ( mode == V4UQQmode || mode == V4QQmode || mode == V2UHQmode || mode == V2HQmode || mode == V2UHAmode || mode == V2HAmode ) ) return true ; return false ; } </s>

Implements target hook vector_mode_supported_p .


<s> void addPreEmitPass ( ) override { if ( ! getPatmosSubtarget ( ) . usePatmosPostRAScheduler ( getOptLevel ( ) ) ) { addPass ( createPatmosDelaySlotFillerPass ( getPatmosTargetMachine ( ) , getOptLevel ( ) == CodeGenOpt :: None ) ) ; } if ( getPatmosSubtarget ( ) . hasMethodCache ( ) ) { addPass ( createPatmosFunctionSplitterPass ( getPatmosTargetMachine ( ) ) ) ; } addPass ( createPatmosDelaySlotKillerPass ( getPatmosTargetMachine ( ) ) ) ; addPass ( createPatmosEnsureAlignmentPass ( getPatmosTargetMachine ( ) ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

Patmos Patmos Patmos Patmos Patmos Patmos Patmos Patmos Patmos Patmos Patmos Patmos


<s> bool RISCVTargetLowering :: isDesirableToCommuteWithShift ( const SDNode * N , CombineLevel Level ) const { SDValue N0 = N -> getOperand ( 0 ) ; EVT Ty = N0 . getValueType ( ) ; if ( Ty . isScalarInteger ( ) && ( N0 . getOpcode ( ) == ISD :: ADD || N0 . getOpcode ( ) == ISD :: OR ) ) { auto * C1 = dyn_cast < ConstantSDNode > ( N0 -> getOperand ( 1 ) ) ; auto * C2 = dyn_cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) ; if ( C1 && C2 ) { const APInt & C1Int = C1 -> getAPIntValue ( ) ; APInt ShiftedC1Int = C1Int << C2 -> getAPIntValue ( ) ; if ( ShiftedC1Int . getMinSignedBits ( ) <= 64 && isLegalAddImmediate ( ShiftedC1Int . getSExtValue ( ) ) ) return true ; if ( C1Int . getMinSignedBits ( ) <= 64 && isLegalAddImmediate ( C1Int . getSExtValue ( ) ) ) return false ; int C1Cost = RISCVMatInt :: getIntMatCost ( C1Int , Ty . getSizeInBits ( ) , Subtarget . is64Bit ( ) ) ; int ShiftedC1Cost = RISCVMatInt :: getIntMatCost ( ShiftedC1Int , Ty . getSizeInBits ( ) , Subtarget . is64Bit ( ) ) ; if ( C1Cost < ShiftedC1Cost ) return false ; } } return true ; } </s>

Return true if it is profitable to move this shift by a constant amount through its operand , adjusting any immediate operands as necessary to preserve semantics .


<s> bool PPCRegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , unsigned Reg , int & FrameIdx ) const { if ( PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ) { FrameIdx = MF . getInfo < PPCFunctionInfo > ( ) -> getCRSpillFrameIndex ( ) ; return true ; } return false ; } </s>

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register .


<s> bool GCNPassConfig :: addInstSelector ( ) { AMDGPUPassConfig :: addInstSelector ( ) ; addPass ( & SIFixSGPRCopiesID ) ; addPass ( createSILowerI1CopiesPass ( ) ) ; addPass ( createSIFixupVectorISelPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


"64-bit code requested on a subtarget that doesn't "

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> PPCTargetLowering :: ConstraintType PPCTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'b' : case 'r' : case 'f' : case 'v' : case 'y' : return C_RegisterClass ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> size_t MipsLA25Stub :: size ( ) const { return m_Size ; } </s>

The number of name/type pairs is returned .


<s>
SUnit
*
GCNMaxOccupancySchedStrategy
::
pickNodeBidirectional
(
bool
&
IsTopNode
)
{
if
(
SUnit
*
SU
=
Bot
.
pickOnlyChoice
(
)
)
{
IsTopNode
=
false
;
return
SU
;
}
if
(
SUnit
*
SU
=
Top
.
pickOnlyChoice
(
)
)
{
IsTopNode
=
true
;
return
SU
;
}
CandPolicy
BotPolicy
;
setPolicy
(
BotPolicy
,
false
,
Bot
,
&
Top
)
;
CandPolicy
TopPolicy
;
setPolicy
(
TopPolicy
,
false
,
Top
,
&
Bot
)
;
DEBUG
(
dbgs
(
)
<<
"Picking from Bot:\n"
)
;
if
(
!
BotCand
.
isValid
(
)
||
BotCand
.
SU
->
isScheduled
||
BotCand
.
Policy
!=
BotPolicy
)
{
BotCand
.
reset
(
CandPolicy
(
)
)
;
pickNodeFromQueue
(
Bot
,
BotPolicy
,
DAG
->
getBotRPTracker
(
)
,
BotCand
)
;
assert
(
BotCand
.
Reason
!=
NoCand
&&
"failed to find the first candidate"
)
;
}
else
{
DEBUG
(
traceCandidate
(
BotCand
)
)
;
}
DEBUG
(
dbgs
(
)
<<
"Picking from Top:\n"
)
;
if
(
!
TopCand
.
isValid
(
)
||
TopCand
.
SU
->
isScheduled
||
TopCand
.
Policy
!=
TopPolicy
)
{
TopCand
.
reset
(
CandPolicy
(
)
)
;
pickNodeFromQueue
(
Top
,
TopPolicy
,
DAG
->
getTopRPTracker
(
)
,
TopCand
)
;
assert
(
TopCand
.
Reason
!=
NoCand
&&
"failed to find the first candidate"
)
;
}
else
{
DEBUG
(
traceCandidate
(
TopCand
)
)
;
}
DEBUG
(
dbgs
(
)
<<
"Top Cand: "
;
traceCandidate
(
TopCand
)
;
dbgs
(
)
<<
"Bot Cand: "
;
traceCandidate
(
BotCand
)
;
)
;
SchedCandidate
Cand
;
if
(
TopCand
.
Reason
==
BotCand
.
Reason
)
{
Cand
=
BotCand
;
GenericSchedulerBase
::
CandReason
TopReason
=
TopCand
.
Reason
;
TopCand
.
Reason
=
NoCand
;
GenericScheduler
::
tryCandidate
(
Cand
,
TopCand
,
nullptr
)
;
if
(
TopCand
.
Reason
!=
NoCand
)
{
Cand
.
setBest
(
TopCand
)
;
}
else
{
TopCand
.
Reason
=
TopReason
;
}
}
else
{
if
(
TopCand
.
Reason
==
RegExcess
&&
TopCand
.
RPDelta
.
Excess
.
getUnitInc
(
)
<=
0
)
{
Cand
=
TopCand
;
}
else
if
(
BotCand
.
Reason
==
RegExcess
&&
BotCand
.
RPDelta
.
Excess
.
getUnitInc
(
)
<=
0
)
{
Cand
=
BotCand
;
}
else
if
(
TopCand
.
Reason
==
RegCritical
&&
TopCand
.
RPDelta
.
CriticalMax
.
getUnitInc
(
)
<=
0
)
{
Cand
=
TopCand
;
}
else
if
(
BotCand
.
Reason
==
RegCritical
&&
BotCand
.
RPDelta
.
CriticalMax
.
getUnitInc
(
)
<=
0
)
{
Cand
=
BotCand
;
}
else
{
if
(
BotCand
.
Reason
>
TopCand
.
Reason
)
{
Cand
=
TopCand
;
}
else
{
Cand
=
BotCand
;
}
}
}
DEBUG
(
dbgs
(
)
<<
"Picking: "
;
traceCandidate
(
Cand
)
;
)
;
IsTopNode
=
Cand
.
AtTop
;
return
Cand
.
SU
;
}
</s>

Pick the best candidate node from either the top or bottom queue .

AMDGPU
"Picking from Bot:\n"
"failed to find the first candidate"
"Picking from Top:\n"
"failed to find the first candidate"
"Top Cand: "
"Bot Cand: "
0
0
0
0
"Picking: "


<s>
Register
SparcTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
LLT
VT
,
const
MachineFunction
&
MF
)
const
{
Register
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"i0"
,
SP
::
I0
)
.
Case
(
"i1"
,
SP
::
I1
)
.
Case
(
"i2"
,
SP
::
I2
)
.
Case
(
"i3"
,
SP
::
I3
)
.
Case
(
"i4"
,
SP
::
I4
)
.
Case
(
"i5"
,
SP
::
I5
)
.
Case
(
"i6"
,
SP
::
I6
)
.
Case
(
"i7"
,
SP
::
I7
)
.
Case
(
"o0"
,
SP
::
O0
)
.
Case
(
"o1"
,
SP
::
O1
)
.
Case
(
"o2"
,
SP
::
O2
)
.
Case
(
"o3"
,
SP
::
O3
)
.
Case
(
"o4"
,
SP
::
O4
)
.
Case
(
"o5"
,
SP
::
O5
)
.
Case
(
"o6"
,
SP
::
O6
)
.
Case
(
"o7"
,
SP
::
O7
)
.
Case
(
"l0"
,
SP
::
L0
)
.
Case
(
"l1"
,
SP
::
L1
)
.
Case
(
"l2"
,
SP
::
L2
)
.
Case
(
"l3"
,
SP
::
L3
)
.
Case
(
"l4"
,
SP
::
L4
)
.
Case
(
"l5"
,
SP
::
L5
)
.
Case
(
"l6"
,
SP
::
L6
)
.
Case
(
"l7"
,
SP
::
L7
)
.
Case
(
"g0"
,
SP
::
G0
)
.
Case
(
"g1"
,
SP
::
G1
)
.
Case
(
"g2"
,
SP
::
G2
)
.
Case
(
"g3"
,
SP
::
G3
)
.
Case
(
"g4"
,
SP
::
G4
)
.
Case
(
"g5"
,
SP
::
G5
)
.
Case
(
"g6"
,
SP
::
G6
)
.
Case
(
"g7"
,
SP
::
G7
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> bool BlackfinAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'r' : break ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


"AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "


<s>
bool
AMDGPUMCInstLower
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
const
{
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
createImm
(
MO
.
getImm
(
)
)
;
return
true
;
case
MachineOperand
::
MO_Register
:
MCOp
=
MCOperand
::
createReg
(
AMDGPU
::
getMCReg
(
MO
.
getReg
(
)
,
ST
)
)
;
return
true
;
case
MachineOperand
::
MO_MachineBasicBlock
:
{
if
(
MO
.
getTargetFlags
(
)
!=
0
)
{
MCOp
=
MCOperand
::
createExpr
(
getLongBranchBlockExpr
(
*
MO
.
getParent
(
)
->
getParent
(
)
,
MO
)
)
;
}
else
{
MCOp
=
MCOperand
::
createExpr
(
MCSymbolRefExpr
::
create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
Ctx
)
)
;
}
return
true
;
}
case
MachineOperand
::
MO_GlobalAddress
:
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
SmallString
<
128
>
SymbolName
;
AP
.
getNameWithPrefix
(
SymbolName
,
GV
)
;
MCSymbol
*
Sym
=
Ctx
.
getOrCreateSymbol
(
SymbolName
)
;
const
MCExpr
*
Expr
=
MCSymbolRefExpr
::
create
(
Sym
,
getVariantKind
(
MO
.
getTargetFlags
(
)
)
,
Ctx
)
;
int64_t
Offset
=
MO
.
getOffset
(
)
;
if
(
Offset
!=
0
)
{
Expr
=
MCBinaryExpr
::
createAdd
(
Expr
,
MCConstantExpr
::
create
(
Offset
,
Ctx
)
,
Ctx
)
;
}
MCOp
=
MCOperand
::
createExpr
(
Expr
)
;
return
true
;
}
case
MachineOperand
::
MO_ExternalSymbol
:
{
MCSymbol
*
Sym
=
Ctx
.
getOrCreateSymbol
(
StringRef
(
MO
.
getSymbolName
(
)
)
)
;
Sym
->
setExternal
(
true
)
;
const
MCSymbolRefExpr
*
Expr
=
MCSymbolRefExpr
::
create
(
Sym
,
Ctx
)
;
MCOp
=
MCOperand
::
createExpr
(
Expr
)
;
return
true
;
}
case
MachineOperand
::
MO_RegisterMask
:
return
false
;
}
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> bool X86InstrInfo :: isHighLatencyDef ( int opc ) const { switch ( opc ) { default : return false ; case X86 :: DIVSDrm : case X86 :: DIVSDrm_Int : case X86 :: DIVSDrr : case X86 :: DIVSDrr_Int : case X86 :: DIVSSrm : case X86 :: DIVSSrm_Int : case X86 :: DIVSSrr : case X86 :: DIVSSrr_Int : case X86 :: SQRTPDm : case X86 :: SQRTPDm_Int : case X86 :: SQRTPDr : case X86 :: SQRTPDr_Int : case X86 :: SQRTPSm : case X86 :: SQRTPSm_Int : case X86 :: SQRTPSr : case X86 :: SQRTPSr_Int : case X86 :: SQRTSDm : case X86 :: SQRTSDm_Int : case X86 :: SQRTSDr : case X86 :: SQRTSDr_Int : case X86 :: SQRTSSm : case X86 :: SQRTSSm_Int : case X86 :: SQRTSSr : case X86 :: SQRTSSr_Int : return true ; } } </s>

Return true if this opcode has high latency to its result .


<s> bool ARMExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { const TargetMachine & TM = MF . getTarget ( ) ; TII = static_cast < const ARMBaseInstrInfo * > ( TM . getInstrInfo ( ) ) ; TRI = TM . getRegisterInfo ( ) ; STI = & TM . getSubtarget < ARMSubtarget > ( ) ; AFI = MF . getInfo < ARMFunctionInfo > ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= ExpandMBB ( * MFI ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> static reg_class_t microblaze_secondary_reload ( bool in_p ATTRIBUTE_UNUSED , rtx x ATTRIBUTE_UNUSED , reg_class_t rclass , machine_mode mode ATTRIBUTE_UNUSED , secondary_reload_info * sri ATTRIBUTE_UNUSED ) { if ( rclass == ST_REGS ) return GR_REGS ; return NO_REGS ; } </s>


<s>
const
char
*
emit_fusion_p9_load
(
rtx
reg
,
rtx
mem
,
rtx
tmp_reg
)
{
machine_mode
mode
=
GET_MODE
(
reg
)
;
rtx
hi
;
rtx
lo
;
rtx
addr
;
const
char
*
load_string
;
int
r
;
if
(
GET_CODE
(
mem
)
==
FLOAT_EXTEND
||
GET_CODE
(
mem
)
==
ZERO_EXTEND
)
{
mem
=
XEXP
(
mem
,
0
)
;
mode
=
GET_MODE
(
mem
)
;
}
if
(
GET_CODE
(
reg
)
==
SUBREG
)
{
gcc_assert
(
SUBREG_BYTE
(
reg
)
==
0
)
;
reg
=
SUBREG_REG
(
reg
)
;
}
if
(
!
REG_P
(
reg
)
)
fatal_insn
(
"emit_fusion_p9_load, bad reg #1"
,
reg
)
;
r
=
REGNO
(
reg
)
;
if
(
FP_REGNO_P
(
r
)
)
{
if
(
mode
==
SFmode
)
load_string
=
"lfs"
;
else
if
(
mode
==
DFmode
||
mode
==
DImode
)
load_string
=
"lfd"
;
else
gcc_unreachable
(
)
;
}
else
if
(
ALTIVEC_REGNO_P
(
r
)
&&
TARGET_P9_DFORM_SCALAR
)
{
if
(
mode
==
SFmode
)
load_string
=
"lxssp"
;
else
if
(
mode
==
DFmode
||
mode
==
DImode
)
load_string
=
"lxsd"
;
else
gcc_unreachable
(
)
;
}
else
if
(
INT_REGNO_P
(
r
)
)
{
switch
(
mode
)
{
case
E_QImode
:
load_string
=
"lbz"
;
break
;
case
E_HImode
:
load_string
=
"lhz"
;
break
;
case
E_SImode
:
case
E_SFmode
:
load_string
=
"lwz"
;
break
;
case
E_DImode
:
case
E_DFmode
:
if
(
!
TARGET_POWERPC64
)
gcc_unreachable
(
)
;
load_string
=
"ld"
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
else
fatal_insn
(
"emit_fusion_p9_load, bad reg #2"
,
reg
)
;
if
(
!
MEM_P
(
mem
)
)
fatal_insn
(
"emit_fusion_p9_load not MEM"
,
mem
)
;
addr
=
XEXP
(
mem
,
0
)
;
fusion_split_address
(
addr
,
&
hi
,
&
lo
)
;
emit_fusion_addis
(
tmp_reg
,
hi
,
"power9 load fusion"
,
GET_MODE_NAME
(
mode
)
)
;
emit_fusion_load_store
(
reg
,
tmp_reg
,
lo
,
load_string
)
;
return
""
;
}
</s>

Return a string to fuse an addis instruction with a load using extended fusion . The address that is used is the logical address that was formed during peephole2 : ( lo_sum ( high ) ( low-part ) ) The code is complicated , so we call output_asm_insn directly , and just return `` '' .

powerpcspe
0
0
"emit_fusion_p9_load, bad reg #1"
"lfs"
"lfd"
"lxssp"
"lxsd"
"lbz"
"lhz"
"lwz"
"ld"
"emit_fusion_p9_load, bad reg #2"
"emit_fusion_p9_load not MEM"
0
"power9 load fusion"
""


<s> bool PPCLoopInstrFormPrep :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; auto * DTWP = getAnalysisIfAvailable < DominatorTreeWrapperPass > ( ) ; DT = DTWP ? & DTWP -> getDomTree ( ) : nullptr ; PreserveLCSSA = mustPreserveAnalysisID ( LCSSAID ) ; ST = TM ? TM -> getSubtargetImpl ( F ) : nullptr ; SuccPrepCount = 0 ; bool MadeChange = false ; for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L = df_begin ( * I ) , LE = df_end ( * I ) ; L != LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ; return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static bool tilepro_legitimate_address_p ( machine_mode ARG_UNUSED ( mode ) , rtx x , bool strict ) { if ( GET_CODE ( x ) == SUBREG ) x = SUBREG_REG ( x ) ; switch ( GET_CODE ( x ) ) { case POST_INC : case POST_DEC : if ( GET_MODE_SIZE ( GET_MODE ( x ) ) > UNITS_PER_WORD ) return false ; x = XEXP ( x , 0 ) ; break ; case POST_MODIFY : if ( GET_MODE_SIZE ( GET_MODE ( x ) ) > UNITS_PER_WORD ) return false ; if ( GET_CODE ( XEXP ( x , 1 ) ) != PLUS ) return false ; if ( ! rtx_equal_p ( XEXP ( x , 0 ) , XEXP ( XEXP ( x , 1 ) , 0 ) ) ) return false ; if ( ! satisfies_constraint_I ( XEXP ( XEXP ( x , 1 ) , 1 ) ) ) return false ; x = XEXP ( x , 0 ) ; break ; case REG : break ; default : return false ; } if ( ! REG_P ( x ) ) return false ; if ( strict ) return REGNO_OK_FOR_BASE_P ( REGNO ( x ) ) ; else return true ; } </s>

Return true if the rtx X can be used as an address operand .


<s> bool supportsEfficientVectorElementLoadStore ( ) { return ST -> getProcFamily ( ) == AArch64Subtarget :: ThunderX2T99 ; } </s>

If target has efficient vector element load/store instructions , it can return true here so that insertion/extraction costs are not added to the scalarization cost of a load/store .


<s> static bool arm_function_ok_for_sibcall ( tree decl , tree exp ) { unsigned long func_type ; if ( cfun -> machine -> sibcall_blocked ) return false ; if ( TARGET_FDPIC ) { if ( decl == NULL ) return false ; } if ( TARGET_THUMB1 ) return false ; if ( TARGET_VXWORKS_RTP && flag_pic && decl && ! targetm . binds_local_p ( decl ) ) return false ; if ( TARGET_APCS_FRAME && TARGET_ARM && TARGET_HARD_FLOAT && decl && arm_is_long_call_p ( decl ) ) return false ; if ( TARGET_INTERWORK && decl && TREE_PUBLIC ( decl ) && ! TREE_ASM_WRITTEN ( decl ) ) return false ; func_type = arm_current_func_type ( ) ; if ( IS_INTERRUPT ( func_type ) ) return false ; if ( IS_CMSE_ENTRY ( arm_current_func_type ( ) ) ) return false ; if ( TREE_CODE ( exp ) == CALL_EXPR ) { tree fntype = TREE_TYPE ( TREE_TYPE ( CALL_EXPR_FN ( exp ) ) ) ; if ( lookup_attribute ( "cmse_nonsecure_call" , TYPE_ATTRIBUTES ( fntype ) ) ) return false ; } if ( ! VOID_TYPE_P ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) ) ) { rtx a , b ; tree decl_or_type = decl ; if ( ! decl ) decl_or_type = TREE_TYPE ( TREE_TYPE ( CALL_EXPR_FN ( exp ) ) ) ; a = arm_function_value ( TREE_TYPE ( exp ) , decl_or_type , false ) ; b = arm_function_value ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) , cfun -> decl , false ) ; if ( ! rtx_equal_p ( a , b ) ) return false ; } if ( IS_STACKALIGN ( func_type ) ) return false ; if ( TARGET_AAPCS_BASED && arm_abi == ARM_ABI_AAPCS && decl && DECL_WEAK ( decl ) ) return false ; if ( ! decl && CALL_EXPR_BY_DESCRIPTOR ( exp ) && ! flag_trampolines ) { tree fntype = TREE_TYPE ( TREE_TYPE ( CALL_EXPR_FN ( exp ) ) ) ; CUMULATIVE_ARGS cum ; cumulative_args_t cum_v ; arm_init_cumulative_args ( & cum , fntype , NULL_RTX , NULL_TREE ) ; cum_v = pack_cumulative_args ( & cum ) ; for ( tree t = TYPE_ARG_TYPES ( fntype ) ; t ; t = TREE_CHAIN ( t ) ) { tree type = TREE_VALUE ( t ) ; if ( ! VOID_TYPE_P ( type ) ) { function_arg_info arg ( type , true ) ; arm_function_arg_advance ( cum_v , arg ) ; } } function_arg_info arg ( integer_type_node , true ) ; if ( ! arm_function_arg ( cum_v , arg ) ) return false ; } return true ; } </s>

Return non-zero if it is ok to make a tail-call to DECL .


<s> bool isMachineVerifierClean ( ) const override { return false ; } </s>

Returns true if the target is expected to pass all machine verifier checks .


<s> int msp430_hard_regno_nregs ( int regno ATTRIBUTE_UNUSED , machine_mode mode ) { if ( mode == PSImode && msp430x ) return 1 ; return ( ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ) ; } </s>

Implements HARD_REGNO_NREGS . MSP430X registers can hold a single PSImode value , but not an SImode value .


<s> bool GCNTTIImpl :: isAlwaysUniform ( const Value * V ) const { if ( const IntrinsicInst * Intrinsic = dyn_cast < IntrinsicInst > ( V ) ) { switch ( Intrinsic -> getIntrinsicID ( ) ) { default : return false ; case Intrinsic :: amdgcn_readfirstlane : case Intrinsic :: amdgcn_readlane : case Intrinsic :: amdgcn_icmp : case Intrinsic :: amdgcn_fcmp : case Intrinsic :: amdgcn_ballot : case Intrinsic :: amdgcn_if_break : return true ; } } if ( const CallInst * CI = dyn_cast < CallInst > ( V ) ) { if ( CI -> isInlineAsm ( ) ) return ! isInlineAsmSourceOfDivergence ( CI ) ; return false ; } const ExtractValueInst * ExtValue = dyn_cast < ExtractValueInst > ( V ) ; if ( ! ExtValue ) return false ; const CallInst * CI = dyn_cast < CallInst > ( ExtValue -> getOperand ( 0 ) ) ; if ( ! CI ) return false ; if ( const IntrinsicInst * Intrinsic = dyn_cast < IntrinsicInst > ( CI ) ) { switch ( Intrinsic -> getIntrinsicID ( ) ) { default : return false ; case Intrinsic :: amdgcn_if : case Intrinsic :: amdgcn_else : { ArrayRef < unsigned > Indices = ExtValue -> getIndices ( ) ; return Indices . size ( ) == 1 && Indices [ 0 ] == 1 ; } } } if ( CI -> isInlineAsm ( ) ) return ! isInlineAsmSourceOfDivergence ( CI , ExtValue -> getIndices ( ) ) ; return false ; } </s>

Whether Val will always return a uniform value regardless of its operands .


<s> Value * AArch64TargetLowering :: getSafeStackPointerLocation ( IRBuilder < > & IRB ) const { if ( ! Subtarget -> isTargetAndroid ( ) ) return TargetLowering :: getSafeStackPointerLocation ( IRB ) ; const unsigned TlsOffset = 0x48 ; Module * M = IRB . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Function * ThreadPointerFunc = Intrinsic :: getDeclaration ( M , Intrinsic :: aarch64_thread_pointer ) ; return IRB . CreatePointerCast ( IRB . CreateConstGEP1_32 ( IRB . CreateCall ( ThreadPointerFunc ) , TlsOffset ) , Type :: getInt8PtrTy ( IRB . getContext ( ) ) -> getPointerTo ( 0 ) ) ; } </s>

Return true if the target stores SafeStack pointer at a fixed offset in some non-standard address space , and populates the address space and offset as appropriate .


<s> std :: pair < unsigned , const TargetRegisterClass * > PPCTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'b' : if ( VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RC_NOX0RegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRC_NOR0RegClass ) ; case 'r' : if ( VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RCRegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRCRegClass ) ; case 'f' : if ( VT == MVT :: f32 || VT == MVT :: i32 ) return std :: make_pair ( 0U , & PPC :: F4RCRegClass ) ; if ( VT == MVT :: f64 || VT == MVT :: i64 ) return std :: make_pair ( 0U , & PPC :: F8RCRegClass ) ; break ; case 'v' : return std :: make_pair ( 0U , & PPC :: VRRCRegClass ) ; case 'y' : return std :: make_pair ( 0U , & PPC :: CRRCRegClass ) ; } } std :: pair < unsigned , const TargetRegisterClass * > R = TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; if ( R . first && VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) && PPC :: GPRCRegClass . contains ( R . first ) ) { const TargetRegisterInfo * TRI = getTargetMachine ( ) . getRegisterInfo ( ) ; return std :: make_pair ( TRI -> getMatchingSuperReg ( R . first , PPC :: sub_32 , & PPC :: GPRCRegClass ) , & PPC :: G8RCRegClass ) ; } return R ; } </s>

Given a physical register constraint ( e.g .


<s> bool R600InstrInfo :: FindSwizzleForVectorSlot ( const std :: vector < std :: vector < std :: pair < int , unsigned >> > & IGSrcs , std :: vector < R600InstrInfo :: BankSwizzle > & SwzCandidate , const std :: vector < std :: pair < int , unsigned >> & TransSrcs , R600InstrInfo :: BankSwizzle TransSwz ) const { unsigned ValidUpTo = 0 ; do { ValidUpTo = isLegalUpTo ( IGSrcs , SwzCandidate , TransSrcs , TransSwz ) ; if ( ValidUpTo == IGSrcs . size ( ) ) return true ; } while ( NextPossibleSolution ( SwzCandidate , ValidUpTo ) ) ; return false ; } </s>

Enumerate all possible Swizzle sequence to find one that can meet all read port requirements .


<s> bool isToken ( ) const override { return Kind == Token ; } </s>


<s> bool isReg ( ) const override { return false ; } </s>


<s> void s390_expand_tbegin ( rtx dest , rtx tdb , rtx retry , bool clobber_fprs_p ) { rtx retry_plus_two = gen_reg_rtx ( SImode ) ; rtx retry_reg = gen_reg_rtx ( SImode ) ; rtx_code_label * retry_label = NULL ; if ( retry != NULL_RTX ) { emit_move_insn ( retry_reg , retry ) ; emit_insn ( gen_addsi3 ( retry_plus_two , retry_reg , const2_rtx ) ) ; emit_insn ( gen_addsi3 ( retry_reg , retry_reg , const1_rtx ) ) ; retry_label = gen_label_rtx ( ) ; emit_label ( retry_label ) ; } if ( clobber_fprs_p ) emit_insn ( gen_tbegin_1 ( gen_rtx_CONST_INT ( VOIDmode , TBEGIN_MASK ) , tdb ) ) ; else emit_insn ( gen_tbegin_nofloat_1 ( gen_rtx_CONST_INT ( VOIDmode , TBEGIN_MASK ) , tdb ) ) ; emit_move_insn ( dest , gen_rtx_UNSPEC ( SImode , gen_rtvec ( 1 , gen_rtx_REG ( CCRAWmode , CC_REGNUM ) ) , UNSPEC_CC_TO_INT ) ) ; if ( retry != NULL_RTX ) { const int CC0 = 1 << 3 ; const int CC1 = 1 << 2 ; const int CC3 = 1 << 0 ; rtx jump ; rtx count = gen_reg_rtx ( SImode ) ; rtx_code_label * leave_label = gen_label_rtx ( ) ; jump = s390_emit_jump ( leave_label , gen_rtx_EQ ( VOIDmode , gen_rtx_REG ( CCRAWmode , CC_REGNUM ) , gen_rtx_CONST_INT ( VOIDmode , CC0 | CC1 | CC3 ) ) ) ; LABEL_NUSES ( leave_label ) = 1 ; emit_move_insn ( count , retry_plus_two ) ; emit_insn ( gen_subsi3 ( count , count , retry_reg ) ) ; emit_insn ( gen_tx_assist ( count ) ) ; jump = emit_jump_insn ( gen_doloop_si64 ( retry_label , retry_reg , retry_reg ) ) ; JUMP_LABEL ( jump ) = retry_label ; LABEL_NUSES ( retry_label ) = 1 ; emit_label ( leave_label ) ; } } </s>

Emit rtl for the tbegin or tbegin_retry ( RETRY ! = NULL_RTX ) expanders . DEST - Register location where CC will be stored . TDB - Pointer to a 256 byte area where to store the transaction . diagnostic block . NULL if TDB is not needed . RETRY - Retry count value . If non-NULL a retry loop for CC2 is emitted CLOBBER_FPRS_P - If true clobbers for all FPRs are emitted as part of the tbegin instruction pattern .


<s> static hsa_status_t get_kernarg_region ( hsa_region_t region , void * data __attribute__ ( ( unused ) ) ) { hsa_region_segment_t segment ; hsa_fns . hsa_region_get_info_fn ( region , HSA_REGION_INFO_SEGMENT , & segment ) ; if ( HSA_REGION_SEGMENT_GLOBAL != segment ) return HSA_STATUS_SUCCESS ; hsa_region_global_flag_t flags ; hsa_fns . hsa_region_get_info_fn ( region , HSA_REGION_INFO_GLOBAL_FLAGS , & flags ) ; if ( flags & HSA_REGION_GLOBAL_FLAG_KERNARG ) { kernargs_region = region ; return HSA_STATUS_INFO_BREAK ; } return HSA_STATUS_SUCCESS ; } </s>

Callback of hsa_iterate_regions . Called once for each available memory region , and returns `` break '' when a suitable one has been found .


<s> bool SIInstrInfo :: isOperandLegal ( const MachineInstr & MI , unsigned OpIdx , const MachineOperand * MO ) const { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const MCInstrDesc & InstDesc = MI . getDesc ( ) ; const MCOperandInfo & OpInfo = InstDesc . OpInfo [ OpIdx ] ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const TargetRegisterClass * DefinedRC = OpInfo . RegClass != - 1 ? RI . getRegClass ( OpInfo . RegClass ) : nullptr ; if ( ! MO ) MO = & MI . getOperand ( OpIdx ) ; int ConstantBusLimit = ST . getConstantBusLimit ( MI . getOpcode ( ) ) ; int VOP3LiteralLimit = ST . hasVOP3Literal ( ) ? 1 : 0 ; if ( isVALU ( MI ) && usesConstantBus ( MRI , * MO , OpInfo ) ) { if ( isVOP3 ( MI ) && isLiteralConstantLike ( * MO , OpInfo ) && ! VOP3LiteralLimit -- ) return false ; SmallDenseSet < RegSubRegPair > SGPRsUsed ; if ( MO -> isReg ( ) ) SGPRsUsed . insert ( RegSubRegPair ( MO -> getReg ( ) , MO -> getSubReg ( ) ) ) ; for ( unsigned i = 0 , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { if ( i == OpIdx ) continue ; const MachineOperand & Op = MI . getOperand ( i ) ; if ( Op . isReg ( ) ) { RegSubRegPair SGPR ( Op . getReg ( ) , Op . getSubReg ( ) ) ; if ( ! SGPRsUsed . count ( SGPR ) && usesConstantBus ( MRI , Op , InstDesc . OpInfo [ i ] ) ) { if ( -- ConstantBusLimit <= 0 ) return false ; SGPRsUsed . insert ( SGPR ) ; } } else if ( InstDesc . OpInfo [ i ] . OperandType == AMDGPU :: OPERAND_KIMM32 ) { if ( -- ConstantBusLimit <= 0 ) return false ; } else if ( isVOP3 ( MI ) && AMDGPU :: isSISrcOperand ( InstDesc , i ) && isLiteralConstantLike ( Op , InstDesc . OpInfo [ i ] ) ) { if ( ! VOP3LiteralLimit -- ) return false ; if ( -- ConstantBusLimit <= 0 ) return false ; } } } if ( MO -> isReg ( ) ) { assert ( DefinedRC ) ; return isLegalRegOperand ( MRI , OpInfo , * MO ) ; } assert ( MO -> isImm ( ) || MO -> isTargetIndex ( ) || MO -> isFI ( ) || MO -> isGlobal ( ) ) ; if ( ! DefinedRC ) { return true ; } return isImmOperandLegal ( MI , OpIdx , * MO ) ; } </s>

Check if MO is a legal operand if it was the OpIdx Operand for MI .


<s> bool ARMPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None && ! getARMSubtarget ( ) . isThumb1Only ( ) ) addPass ( createARMLoadStoreOptimizationPass ( true ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None && getARMSubtarget ( ) . isCortexA9 ( ) ) addPass ( createMLxExpansionPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None && getARMSubtarget ( ) . isCortexA15 ( ) && getARMSubtarget ( ) . hasNEON ( ) && ! DisableA15SDOptimization ) { addPass ( createA15SDOptimizerPass ( ) ) ; } return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> bool HexagonAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal . lower ( ) == ".falign" ) return ParseDirectiveFalign ( 256 , DirectiveID . getLoc ( ) ) ; if ( ( IDVal . lower ( ) == ".lcomm" ) || ( IDVal . lower ( ) == ".lcommon" ) ) return ParseDirectiveComm ( true , DirectiveID . getLoc ( ) ) ; if ( ( IDVal . lower ( ) == ".comm" ) || ( IDVal . lower ( ) == ".common" ) ) return ParseDirectiveComm ( false , DirectiveID . getLoc ( ) ) ; if ( IDVal . lower ( ) == ".subsection" ) return ParseDirectiveSubsection ( DirectiveID . getLoc ( ) ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> SDValue MSP430TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_MSP430 ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static bool flexible_array_member_type_p ( const_tree type ) { if ( TREE_CODE ( type ) != RECORD_TYPE ) return false ; const_tree last_field = NULL_TREE ; for ( const_tree f = TYPE_FIELDS ( type ) ; f ; f = TREE_CHAIN ( f ) ) last_field = f ; if ( ! last_field ) return false ; const_tree last_field_type = TREE_TYPE ( last_field ) ; if ( TREE_CODE ( last_field_type ) != ARRAY_TYPE ) return false ; return ( ! TYPE_DOMAIN ( last_field_type ) || ! TYPE_MAX_VALUE ( TYPE_DOMAIN ( last_field_type ) ) ) ; } </s>

Return true if TYPE is a record type where the last field is an array without given dimension .


"  Preloading operand for insn %d into r%d\n"

Convert operand OP in INSN . We should handle memory operands and uninitialized registers . All other register uses are converted during registers conversion .


<s> void HexagonShuffler :: append ( MCInst const & ID , MCInst const * Extender , unsigned S ) { HexagonInstr PI ( & TUL , MCII , & ID , Extender , S ) ; Packet . push_back ( PI ) ; } </s>


<s> bool AVRRelaxMem :: runOnMachineFunction ( MachineFunction & MF ) { bool Modified = false ; const AVRSubtarget & STI = MF . getSubtarget < AVRSubtarget > ( ) ; TII = STI . getInstrInfo ( ) ; for ( Block & MBB : MF ) { bool BlockModified = runOnBasicBlock ( MBB ) ; Modified |= BlockModified ; } return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> void AArch64PassConfig :: addPreLegalizeMachineIR ( ) { bool IsOptNone = getOptLevel ( ) == CodeGenOpt :: None ; addPass ( createAArch64PreLegalizerCombiner ( IsOptNone ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before legalization .


<s> std :: pair < unsigned , const TargetRegisterClass * > RISCVTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , & RISCV :: GPRRegClass ) ; case 'f' : if ( Subtarget . hasStdExtF ( ) && VT == MVT :: f32 ) return std :: make_pair ( 0U , & RISCV :: FPR32RegClass ) ; if ( Subtarget . hasStdExtD ( ) && VT == MVT :: f64 ) return std :: make_pair ( 0U , & RISCV :: FPR64RegClass ) ; break ; default : break ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>


"Wrong register class for memory operand."

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


"ARCOMPACT DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s>
bool
PPCInstrInfo
::
isReallyTriviallyReMaterializable
(
const
MachineInstr
&
MI
,
AliasAnalysis
*
AA
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown rematerializable operation!"
)
;
break
;
case
PPC
::
LI
:
case
PPC
::
LI8
:
case
PPC
::
LIS
:
case
PPC
::
LIS8
:
case
PPC
::
QVGPCI
:
case
PPC
::
ADDIStocHA
:
case
PPC
::
ADDIStocHA8
:
case
PPC
::
ADDItocL
:
case
PPC
::
LOAD_STACK_GUARD
:
case
PPC
::
XXLXORz
:
case
PPC
::
XXLXORspz
:
case
PPC
::
XXLXORdpz
:
case
PPC
::
XXLEQVOnes
:
case
PPC
::
V_SET0B
:
case
PPC
::
V_SET0H
:
case
PPC
::
V_SET0
:
case
PPC
::
V_SETALLONESB
:
case
PPC
::
V_SETALLONESH
:
case
PPC
::
V_SETALLONES
:
case
PPC
::
CRSET
:
case
PPC
::
CRUNSET
:
return
true
;
}
return
false
;
}
</s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> static rtx m68k_struct_value_rtx ( tree fntype ATTRIBUTE_UNUSED , int incoming ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( Pmode , M68K_STRUCT_VALUE_REGNUM ) ; } </s>

Worker function for TARGET_STRUCT_VALUE_RTX .


<s> bool AArch64TargetLowering :: shouldExtendGSIndex ( EVT VT , EVT & EltTy ) const { if ( VT . getVectorElementType ( ) == MVT :: i8 || VT . getVectorElementType ( ) == MVT :: i16 ) { EltTy = MVT :: i32 ; return true ; } return false ; } </s>

Returns true if the index type for a masked gather/scatter requires extending .


<s> ScheduleDAGInstrs * MOSPassConfig :: createMachineScheduler ( MachineSchedContext * C ) const { return new ScheduleDAGMILive ( C , std :: make_unique < MOSSchedStrategy > ( C ) ) ; } </s>

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level .


"Instr doesn't have FrameIndex operand!"

"16-byte alignment violated in eliminateFrameIndex"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> virtual EVT getSetCCResultType ( EVT VT ) const { return MVT :: i1 ; } </s>

Return the value type to use for ISD : :SETCC .


<s> Register getExceptionPointerRegister ( const Constant * PersonalityFn ) const override { return Hexagon :: R0 ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s> static bool pru_repeat_loop_p ( struct pru_doloop * loop ) { struct pru_doloop_end * end ; rtx_insn * fallthrough ; if ( loop -> begin == 0 || loop -> end == 0 || loop -> begin -> next != 0 ) return false ; if ( prev_real_insn ( as_a < rtx_insn * > ( loop -> end -> label ) ) != loop -> begin -> insn ) return false ; if ( get_attr_length ( loop -> end -> insn ) != 4 ) return false ; fallthrough = loop -> end -> fallthrough ; for ( end = loop -> end -> next ; end != 0 ; end = end -> next ) if ( end -> label != loop -> end -> label || ! simplejump_p ( end -> fallthrough ) || fallthrough != next_real_insn ( JUMP_LABEL_AS_INSN ( end -> fallthrough ) ) ) return false ; return true ; } </s>

Return true if LOOP can be converted into LOOP form ( that is , if it matches cases ( 1 ) or ( 2 ) above ) .


<s>
static
void
write_fn_proto_1
(
std
::
stringstream
&
s
,
bool
is_defn
,
const
char
*
name
,
const_tree
decl
)
{
if
(
lookup_attribute
(
"alias"
,
DECL_ATTRIBUTES
(
decl
)
)
==
)
write_fn_marker
(
s
,
is_defn
,
TREE_PUBLIC
(
decl
)
,
name
)
;
if
(
DECL_EXTERNAL
(
decl
)
)
s
<<
".extern "
;
else
if
(
TREE_PUBLIC
(
decl
)
)
s
<<
(
DECL_WEAK
(
decl
)
".weak "
:
".visible "
)
;
s
<<
(
write_as_kernel
(
DECL_ATTRIBUTES
(
decl
)
)
".entry "
:
".func "
)
;
tree
fntype
=
TREE_TYPE
(
decl
)
;
tree
result_type
=
TREE_TYPE
(
fntype
)
;
int
not_atomic_weak_arg
=
1
;
if
(
DECL_BUILT_IN_CLASS
(
decl
)
==
BUILT_IN_NORMAL
)
switch
(
DECL_FUNCTION_CODE
(
decl
)
)
{
case
BUILT_IN_ATOMIC_COMPARE_EXCHANGE_1
:
case
BUILT_IN_ATOMIC_COMPARE_EXCHANGE_2
:
case
BUILT_IN_ATOMIC_COMPARE_EXCHANGE_4
:
case
BUILT_IN_ATOMIC_COMPARE_EXCHANGE_8
:
case
BUILT_IN_ATOMIC_COMPARE_EXCHANGE_16
:
not_atomic_weak_arg
=
3
;
break
;
default
:
break
;
}
bool
return_in_mem
=
write_return_type
(
s
,
true
,
result_type
)
;
s
<<
name
;
int
argno
=
0
;
if
(
return_in_mem
)
argno
=
write_arg_type
(
s
,
1
,
argno
,
ptr_type_node
,
true
)
;
tree
args
=
TYPE_ARG_TYPES
(
fntype
)
;
bool
prototyped
=
true
;
if
(
!
args
)
{
args
=
DECL_ARGUMENTS
(
decl
)
;
prototyped
=
false
;
}
for
(
;
args
;
args
=
TREE_CHAIN
(
args
)
,
not_atomic_weak_arg
)
{
tree
type
=
prototyped
TREE_VALUE
(
args
)
:
TREE_TYPE
(
args
)
;
if
(
not_atomic_weak_arg
)
argno
=
write_arg_type
(
s
,
1
,
argno
,
type
,
prototyped
)
;
else
gcc_assert
(
TREE_CODE
(
type
)
==
BOOLEAN_TYPE
)
;
}
if
(
stdarg_p
(
fntype
)
)
argno
=
write_arg_type
(
s
,
1
,
argno
,
ptr_type_node
,
true
)
;
if
(
DECL_STATIC_CHAIN
(
decl
)
)
argno
=
write_arg_type
(
s
,
1
,
argno
,
ptr_type_node
,
true
)
;
if
(
argno
<
2
&&
strcmp
(
name
,
"main"
)
==
0
)
{
if
(
argno
==
0
)
argno
=
write_arg_type
(
s
,
1
,
argno
,
integer_type_node
,
true
)
;
if
(
argno
==
1
)
argno
=
write_arg_type
(
s
,
1
,
argno
,
ptr_type_node
,
true
)
;
}
if
(
argno
)
s
<<
")"
;
s
<<
(
is_defn
"\n"
:
";\n"
)
;
}
</s>


<s> const char * HexagonTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case HexagonISD :: CONST32 : return "HexagonISD::CONST32" ; case HexagonISD :: CONST32_GP : return "HexagonISD::CONST32_GP" ; case HexagonISD :: CONST32_Int_Real : return "HexagonISD::CONST32_Int_Real" ; case HexagonISD :: ADJDYNALLOC : return "HexagonISD::ADJDYNALLOC" ; case HexagonISD :: CMPICC : return "HexagonISD::CMPICC" ; case HexagonISD :: CMPFCC : return "HexagonISD::CMPFCC" ; case HexagonISD :: BRICC : return "HexagonISD::BRICC" ; case HexagonISD :: BRFCC : return "HexagonISD::BRFCC" ; case HexagonISD :: SELECT_ICC : return "HexagonISD::SELECT_ICC" ; case HexagonISD :: SELECT_FCC : return "HexagonISD::SELECT_FCC" ; case HexagonISD :: Hi : return "HexagonISD::Hi" ; case HexagonISD :: Lo : return "HexagonISD::Lo" ; case HexagonISD :: FTOI : return "HexagonISD::FTOI" ; case HexagonISD :: ITOF : return "HexagonISD::ITOF" ; case HexagonISD :: CALL : return "HexagonISD::CALL" ; case HexagonISD :: RET_FLAG : return "HexagonISD::RET_FLAG" ; case HexagonISD :: BR_JT : return "HexagonISD::BR_JT" ; case HexagonISD :: TC_RETURN : return "HexagonISD::TC_RETURN" ; case HexagonISD :: EH_RETURN : return "HexagonISD::EH_RETURN" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s>
SDValue
PPCTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_PPC
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Arg
=
OutVals
[
i
]
;
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
AExt
:
Arg
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Arg
)
;
break
;
case
CCValAssign
::
ZExt
:
Arg
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Arg
)
;
break
;
case
CCValAssign
::
SExt
:
Arg
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Arg
)
;
break
;
}
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
Arg
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
PPCISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
else
return
DAG
.
getNode
(
PPCISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> uint32_t insert ( T Val ) { auto F = llvm :: find ( Map , Val ) ; if ( F != Map . end ( ) ) return F - Map . begin ( ) + 1 ; Map . push_back ( Val ) ; return Map . size ( ) ; } </s>

insert - Append entry to the vector if it does n't already exist .


<s>
virtual
StringRef
getPassName
(
)
const
{
return
StringRef
(
"CJG Assembly Printer"
)
;
}
</s>


<s> static int cris_initial_frame_pointer_offset ( ) { int regno ; int offs = 0 ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ( ( ( regs_ever_live [ regno ] && ! call_used_regs [ regno ] ) || ( regno == ( int ) PIC_OFFSET_TABLE_REGNUM && ( current_function_uses_pic_offset_table || ( flag_pic && regs_ever_live [ regno + 1 ] && ! call_used_regs [ regno + 1 ] ) ) ) ) && ( regno != FRAME_POINTER_REGNUM || ! frame_pointer_needed ) && regno != CRIS_SRP_REGNUM ) || ( current_function_calls_eh_return && ( regno == EH_RETURN_DATA_REGNO ( 0 ) || regno == EH_RETURN_DATA_REGNO ( 1 ) || regno == EH_RETURN_DATA_REGNO ( 2 ) || regno == EH_RETURN_DATA_REGNO ( 3 ) ) ) ) offs += 4 ; offs += get_frame_size ( ) ; offs += current_function_outgoing_args_size ; if ( TARGET_STACK_ALIGN ) offs = TARGET_ALIGN_BY_32 ? ( offs + 3 ) & ~ 3 : ( offs + 1 ) & ~ 1 ; return offs ; } </s>

This used to be the INITIAL_FRAME_POINTER_OFFSET worker ; now only handles FP - > SP elimination offset .


<s> virtual const InstrItineraryData * getInstrItineraryData ( ) const { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> bool X86TargetLowering :: isIntDivCheap ( EVT VT , AttributeList Attr ) const { bool OptSize = Attr . hasFnAttr ( Attribute :: MinSize ) ; return OptSize && ! VT . isVector ( ) ; } </s>

Return true if integer divide is usually cheaper than a sequence of several shifts , adds , and multiplies for this target .


<s> static bool is_costly_group ( rtx * group_insns , rtx next_insn ) { int i ; int issue_rate = rs6000_issue_rate ( ) ; for ( i = 0 ; i < issue_rate ; i ++ ) { sd_iterator_def sd_it ; dep_t dep ; rtx insn = group_insns [ i ] ; if ( ! insn ) continue ; FOR_EACH_DEP ( insn , SD_LIST_RES_FORW , sd_it , dep ) { rtx next = DEP_CON ( dep ) ; if ( next == next_insn && rs6000_is_costly_dependence ( dep , dep_cost ( dep ) , 0 ) ) return true ; } } return false ; } </s>

Return true if it is recommended to keep NEXT_INSN `` far '' ( in a separate dispatch group ) from the insns in GROUP_INSNS . Return false otherwise .


<s> void X86PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> BitVector P2RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( P2 :: PTRA ) ; Reserved . set ( P2 :: PTRB ) ; Reserved . set ( P2 :: OUTA ) ; Reserved . set ( P2 :: OUTB ) ; Reserved . set ( P2 :: DIRA ) ; Reserved . set ( P2 :: DIRB ) ; Reserved . set ( P2 :: QX ) ; Reserved . set ( P2 :: QY ) ; Reserved . set ( P2 :: R15 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
bool
AArch64InstrInfo
::
getMemOperandWithOffsetWidth
(
const
MachineInstr
&
LdSt
,
const
MachineOperand
*
&
BaseOp
,
int64_t
&
Offset
,
bool
&
OffsetIsScalable
,
unsigned
&
Width
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
LdSt
.
mayLoadOrStore
(
)
&&
"Expected a memory operation."
)
;
if
(
LdSt
.
getNumExplicitOperands
(
)
==
3
)
{
if
(
(
!
LdSt
.
getOperand
(
1
)
.
isReg
(
)
&&
!
LdSt
.
getOperand
(
1
)
.
isFI
(
)
)
||
!
LdSt
.
getOperand
(
2
)
.
isImm
(
)
)
return
false
;
}
else
if
(
LdSt
.
getNumExplicitOperands
(
)
==
4
)
{
if
(
!
LdSt
.
getOperand
(
1
)
.
isReg
(
)
||
(
!
LdSt
.
getOperand
(
2
)
.
isReg
(
)
&&
!
LdSt
.
getOperand
(
2
)
.
isFI
(
)
)
||
!
LdSt
.
getOperand
(
3
)
.
isImm
(
)
)
return
false
;
}
else
return
false
;
TypeSize
Scale
(
0U
,
false
)
;
int64_t
Dummy1
,
Dummy2
;
if
(
!
getMemOpInfo
(
LdSt
.
getOpcode
(
)
,
Scale
,
Width
,
Dummy1
,
Dummy2
)
)
return
false
;
if
(
LdSt
.
getNumExplicitOperands
(
)
==
3
)
{
BaseOp
=
&
LdSt
.
getOperand
(
1
)
;
Offset
=
LdSt
.
getOperand
(
2
)
.
getImm
(
)
*
Scale
.
getKnownMinSize
(
)
;
}
else
{
assert
(
LdSt
.
getNumExplicitOperands
(
)
==
4
&&
"invalid number of operands"
)
;
BaseOp
=
&
LdSt
.
getOperand
(
2
)
;
Offset
=
LdSt
.
getOperand
(
3
)
.
getImm
(
)
*
Scale
.
getKnownMinSize
(
)
;
}
OffsetIsScalable
=
Scale
.
isScalable
(
)
;
if
(
!
BaseOp
->
isReg
(
)
&&
!
BaseOp
->
isFI
(
)
)
return
false
;
return
true
;
}
</s>

Return true if get the base operand , byte offset of an instruction and the memory width .


<s> static bool ix86_vectorize_vec_perm_const_ok ( machine_mode vmode , const unsigned char * sel ) { struct expand_vec_perm_d d ; unsigned int i , nelt , which ; bool ret ; d . vmode = vmode ; d . nelt = nelt = GET_MODE_NUNITS ( d . vmode ) ; d . testing_p = true ; switch ( d . vmode ) { case V16SFmode : case V16SImode : case V8DImode : case V8DFmode : if ( TARGET_AVX512F ) return true ; break ; case V32HImode : if ( TARGET_AVX512BW ) return true ; break ; case V64QImode : if ( TARGET_AVX512BW ) return true ; break ; case V8SImode : case V8SFmode : case V4DFmode : case V4DImode : if ( TARGET_AVX512VL ) return true ; break ; case V16HImode : if ( TARGET_AVX2 ) return true ; break ; case V32QImode : if ( TARGET_AVX2 ) return true ; break ; case V4SImode : case V4SFmode : case V8HImode : case V16QImode : if ( TARGET_XOP ) return true ; if ( TARGET_SSSE3 ) return true ; break ; case V2DImode : case V2DFmode : return true ; default : return false ; } memcpy ( d . perm , sel , nelt ) ; for ( i = which = 0 ; i < nelt ; ++ i ) { unsigned char e = d . perm [ i ] ; gcc_assert ( e < 2 * nelt ) ; which |= ( e < nelt ? 1 : 2 ) ; } if ( which == 2 ) for ( i = 0 ; i < nelt ; ++ i ) d . perm [ i ] -= nelt ; d . one_operand_p = ( which != 3 ) ; if ( d . one_operand_p && ( d . vmode == V4SFmode || d . vmode == V4SImode ) ) return true ; d . target = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 1 ) ; d . op1 = d . op0 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 2 ) ; if ( ! d . one_operand_p ) d . op1 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 3 ) ; start_sequence ( ) ; ret = ix86_expand_vec_perm_const_1 ( & d ) ; end_sequence ( ) ; return ret ; } </s>


<s> bool isSubregFoldable ( ) const override { return true ; } </s>

Check whether the target can fold a load that feeds a subreg operand ( or a subreg operand that feeds a store ) .


<s> static rtx frv_alloc_temp_reg ( frv_tmp_reg_t * info , enum reg_class class , enum machine_mode mode , int mark_as_used , int no_abort ) { int regno = info -> next_reg [ ( int ) class ] ; int orig_regno = regno ; HARD_REG_SET * reg_in_class = & reg_class_contents [ ( int ) class ] ; int i , nr ; for ( ; ; ) { if ( TEST_HARD_REG_BIT ( * reg_in_class , regno ) && TEST_HARD_REG_BIT ( info -> regs , regno ) ) break ; if ( ++ regno >= FIRST_PSEUDO_REGISTER ) regno = 0 ; if ( regno == orig_regno ) { gcc_assert ( no_abort ) ; return NULL_RTX ; } } nr = HARD_REGNO_NREGS ( regno , mode ) ; info -> next_reg [ ( int ) class ] = regno + nr ; if ( mark_as_used ) for ( i = 0 ; i < nr ; i ++ ) CLEAR_HARD_REG_BIT ( info -> regs , regno + i ) ; return gen_rtx_REG ( mode , regno ) ; } </s>

Return the next available temporary register in a given class .


<s> static const uint16_t * lookup ( unsigned opcode , unsigned domain ) { for ( unsigned i = 0 , e = array_lengthof ( ReplaceableInstrs ) ; i != e ; ++ i ) if ( ReplaceableInstrs [ i ] [ domain - 1 ] == opcode ) return ReplaceableInstrs [ i ] ; return nullptr ; } </s>

This method finds the value with the given Name in the the symbol table .


<s> static void build_sv_index64 ( function_builder & b , const char * signature , const function_group_info & group ) { build_32_64 ( b , signature , group , MODE_none , MODE_s64index ) ; build_32_64 ( b , signature , group , MODE_none , MODE_u64index ) ; } </s>

Like build_sv_index , but only handle 64-bit types .


<s>
void
microblaze_asm_output_ident
(
const
char
*
string
)
{
const
char
*
section_asm_op
;
int
size
;
char
*
buf
;
if
(
symtab
->
state
!=
PARSING
)
return
;
size
=
strlen
(
string
)
+
1
;
if
(
size
<=
microblaze_section_threshold
)
section_asm_op
=
SDATA2_SECTION_ASM_OP
;
else
section_asm_op
=
READONLY_DATA_SECTION_ASM_OP
;
buf
=
ACONCAT
(
(
"\t.pushsection"
,
section_asm_op
,
"\n\t.ascii \""
,
string
,
"\\0\"\n"
,
"\t.popsection\n"
,
)
)
;
symtab
->
finalize_toplevel_asm
(
build_string
(
strlen
(
buf
)
,
buf
)
)
;
}
</s>

Queue an .ident string in the queue of top-level asm statements . If the string size is below the threshold , put it into .sdata2 . If the front-end is done , we must be being called from toplev.cc . In that case , do nothing .


"selector must be an integer constant in the range [0, %wi]"

Return the integer constant in ARG . Constrain it to be in the range of the subparts of VEC_TYPE ; issue an error if not .


<s> const M680x0Subtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> unsigned RISCVTargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { switch ( Op . getOpcode ( ) ) { default : break ; case RISCVISD :: SLLW : case RISCVISD :: SRAW : case RISCVISD :: SRLW : case RISCVISD :: DIVW : case RISCVISD :: DIVUW : case RISCVISD :: REMUW : case RISCVISD :: ROLW : case RISCVISD :: RORW : case RISCVISD :: GREVIW : case RISCVISD :: GORCIW : case RISCVISD :: FSLW : case RISCVISD :: FSRW : return 33 ; case RISCVISD :: VMV_X_S : return Subtarget . getXLen ( ) - Op . getOperand ( 0 ) . getScalarValueSizeInBits ( ) + 1 ; } return 1 ; } </s>

Determine the number of bits in the operation that are sign bits .

RISCV RISCV RISCVISD::SLLW RISCVISD::SRAW RISCVISD::SRLW RISCVISD::DIVW RISCVISD::DIVUW RISCVISD::REMUW RISCVISD::ROLW RISCVISD::RORW RISCVISD::GREVIW RISCVISD::GORCIW RISCVISD::FSLW RISCVISD::FSRW 33 RISCVISD::VMV_X_S 0 1 1


<s> void EmitInstruction ( const MachineInstr * MI ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; printInstruction ( MI , OS ) ; OutStreamer . EmitRawText ( OS . str ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool HexagonInstrInfo :: areMemAccessesTriviallyDisjoint ( const MachineInstr & MIa , const MachineInstr & MIb , AliasAnalysis * AA ) const { if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) || MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; if ( MIa . mayLoad ( ) && ! isMemOp ( MIa ) && MIb . mayLoad ( ) && ! isMemOp ( MIb ) ) return true ; unsigned BasePosA , OffsetPosA ; if ( ! getBaseAndOffsetPosition ( MIa , BasePosA , OffsetPosA ) ) return false ; const MachineOperand & BaseA = MIa . getOperand ( BasePosA ) ; unsigned BaseRegA = BaseA . getReg ( ) ; unsigned BaseSubA = BaseA . getSubReg ( ) ; unsigned BasePosB , OffsetPosB ; if ( ! getBaseAndOffsetPosition ( MIb , BasePosB , OffsetPosB ) ) return false ; const MachineOperand & BaseB = MIb . getOperand ( BasePosB ) ; unsigned BaseRegB = BaseB . getReg ( ) ; unsigned BaseSubB = BaseB . getSubReg ( ) ; if ( BaseRegA != BaseRegB || BaseSubA != BaseSubB ) return false ; unsigned SizeA = getMemAccessSize ( MIa ) ; unsigned SizeB = getMemAccessSize ( MIb ) ; const MachineOperand & OffA = MIa . getOperand ( OffsetPosA ) ; const MachineOperand & OffB = MIb . getOperand ( OffsetPosB ) ; if ( ! MIa . getOperand ( OffsetPosA ) . isImm ( ) || ! MIb . getOperand ( OffsetPosB ) . isImm ( ) ) return false ; int OffsetA = isPostIncrement ( MIa ) ? 0 : OffA . getImm ( ) ; int OffsetB = isPostIncrement ( MIb ) ? 0 : OffB . getImm ( ) ; if ( OffsetA > OffsetB ) { uint64_t OffDiff = ( uint64_t ) ( ( int64_t ) OffsetA - ( int64_t ) OffsetB ) ; return SizeB <= OffDiff ; } if ( OffsetA < OffsetB ) { uint64_t OffDiff = ( uint64_t ) ( ( int64_t ) OffsetB - ( int64_t ) OffsetA ) ; return SizeA <= OffDiff ; } return false ; } </s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s>
bool
RISCVInstrInfo
::
verifyInstruction
(
const
MachineInstr
&
MI
,
StringRef
&
ErrInfo
)
const
{
const
MCInstrInfo
*
MCII
=
STI
.
getInstrInfo
(
)
;
MCInstrDesc
const
&
Desc
=
MCII
->
get
(
MI
.
getOpcode
(
)
)
;
for
(
auto
&
OI
:
enumerate
(
Desc
.
operands
(
)
)
)
{
unsigned
OpType
=
OI
.
value
(
)
.
OperandType
;
if
(
OpType
>=
RISCVOp
::
OPERAND_FIRST_RISCV_IMM
&&
OpType
<=
RISCVOp
::
OPERAND_LAST_RISCV_IMM
)
{
const
MachineOperand
&
MO
=
MI
.
getOperand
(
OI
.
index
(
)
)
;
if
(
MO
.
isImm
(
)
)
{
int64_t
Imm
=
MO
.
getImm
(
)
;
bool
Ok
;
switch
(
OpType
)
{
default
:
llvm_unreachable
(
"Unexpected operand type"
)
;
case
RISCVOp
::
OPERAND_UIMM1
:
Ok
=
isUInt
<
1
>
(
Imm
)
;
break
;
case
RISCVOp
::
OPERAND_UIMM4
:
Ok
=
isUInt
<
4
>
(
Imm
)
;
break
;
case
RISCVOp
::
OPERAND_UIMM5
:
Ok
=
isUInt
<
5
>
(
Imm
)
;
break
;
case
RISCVOp
::
OPERAND_UIMM12
:
Ok
=
isUInt
<
12
>
(
Imm
)
;
break
;
case
RISCVOp
::
OPERAND_SIMM12
:
Ok
=
isInt
<
12
>
(
Imm
)
;
break
;
case
RISCVOp
::
OPERAND_SIMM13_LSB0
:
Ok
=
isShiftedInt
<
12
,
1
>
(
Imm
)
;
break
;
case
RISCVOp
::
OPERAND_UIMM20
:
Ok
=
isUInt
<
20
>
(
Imm
)
;
break
;
case
RISCVOp
::
OPERAND_SIMM21_LSB0
:
Ok
=
isShiftedInt
<
20
,
1
>
(
Imm
)
;
break
;
case
RISCVOp
::
OPERAND_UIMMLOG2XLEN
:
if
(
STI
.
getTargetTriple
(
)
.
isArch64Bit
(
)
)
Ok
=
isUInt
<
6
>
(
Imm
)
;
else
Ok
=
isUInt
<
5
>
(
Imm
)
;
break
;
}
if
(
!
Ok
)
{
ErrInfo
=
"Invalid immediate"
;
return
false
;
}
}
}
}
return
true
;
}
</s>

Perform target-specific instruction verification .


<s>
static
void
thumb_pushpop
(
FILE
*
f
,
unsigned
long
mask
,
int
push
,
int
*
cfa_offset
,
unsigned
long
real_regs
)
{
int
regno
;
int
lo_mask
=
mask
&
0xFF
;
int
pushed_words
=
0
;
gcc_assert
(
mask
)
;
if
(
lo_mask
==
0
&&
!
push
&&
(
mask
&
(
1
<<
PC_REGNUM
)
)
)
{
thumb_exit
(
f
,
1
)
;
return
;
}
if
(
ARM_EABI_UNWIND_TABLES
&&
push
)
{
fprintf
(
f
,
"\t.save\t{"
)
;
for
(
regno
=
0
;
regno
<
15
;
regno
++
)
{
if
(
real_regs
&
(
1
<<
regno
)
)
{
if
(
real_regs
&
(
(
1
<<
regno
)
1
)
)
fprintf
(
f
,
", "
)
;
asm_fprintf
(
f
,
"%r"
,
regno
)
;
}
}
fprintf
(
f
,
"}\n"
)
;
}
fprintf
(
f
,
"\t%s\t{"
,
push
"push"
:
"pop"
)
;
for
(
regno
=
0
;
regno
<=
LAST_LO_REGNUM
;
regno
++
,
lo_mask
>>=
1
)
{
if
(
lo_mask
&
1
)
{
asm_fprintf
(
f
,
"%r"
,
regno
)
;
if
(
(
lo_mask
&
~
1
)
!=
0
)
fprintf
(
f
,
", "
)
;
pushed_words
++
;
}
}
if
(
push
&&
(
mask
&
(
1
<<
LR_REGNUM
)
)
)
{
if
(
mask
&
0xFF
)
fprintf
(
f
,
", "
)
;
asm_fprintf
(
f
,
"%r"
,
LR_REGNUM
)
;
pushed_words
++
;
}
else
if
(
!
push
&&
(
mask
&
(
1
<<
PC_REGNUM
)
)
)
{
if
(
TARGET_INTERWORK
||
TARGET_BACKTRACE
||
current_function_calls_eh_return
)
{
fprintf
(
f
,
"}\n"
)
;
thumb_exit
(
f
,
1
)
;
return
;
}
else
{
if
(
mask
&
0xFF
)
fprintf
(
f
,
", "
)
;
asm_fprintf
(
f
,
"%r"
,
PC_REGNUM
)
;
}
}
fprintf
(
f
,
"}\n"
)
;
if
(
push
&&
pushed_words
&&
dwarf2out_do_frame
(
)
)
{
char
*
l
=
dwarf2out_cfi_label
(
)
;
int
pushed_mask
=
real_regs
;
*
cfa_offset
+=
pushed_words
*
4
;
dwarf2out_def_cfa
(
l
,
SP_REGNUM
,
*
cfa_offset
)
;
pushed_words
=
0
;
pushed_mask
=
real_regs
;
for
(
regno
=
0
;
regno
<=
14
;
regno
++
,
pushed_mask
>>=
1
)
{
if
(
pushed_mask
&
1
)
dwarf2out_reg_save
(
l
,
regno
,
4
*
pushed_words
++
*
cfa_offset
)
;
}
}
}
</s>

Emit code to push or pop registers to or from the stack . F is the assembly file . MASK is the registers to push or pop . PUSH is nonzero if we should push , and zero if we should pop . For debugging output , if pushing , adjust CFA_OFFSET by the amount of space added to the stack . REAL_REGS should have the same number of bits set as MASK , and will be used instead ( in the same order ) to describe which registers were saved - this is used to mark the save slots when we push high registers after moving them to low registers .


<s> bool XCoreRegisterInfo :: needsFrameMoves ( const MachineFunction & MF ) { return MF . getMMI ( ) . hasDebugInfo ( ) || MF . getFunction ( ) -> needsUnwindTableEntry ( ) ; } </s>


<s> static bool aarch64_pass_by_reference_1 ( CUMULATIVE_ARGS * pcum , const function_arg_info & arg ) { HOST_WIDE_INT size ; machine_mode dummymode ; int nregs ; if ( arg . mode == BLKmode && arg . type ) size = int_size_in_bytes ( arg . type ) ; else size = GET_MODE_SIZE ( arg . mode ) . to_constant ( ) ; if ( arg . aggregate_type_p ( ) ) size = int_size_in_bytes ( arg . type ) ; if ( size < 0 ) return true ; if ( aarch64_vfp_is_call_or_return_candidate ( arg . mode , arg . type , & dummymode , & nregs , NULL , ! pcum || pcum -> silent_p ) ) return false ; return size > 2 * UNITS_PER_WORD ; } </s>

Subroutine of aarch64_pass_by_reference for arguments that are not passed in SVE registers .


<s>
bool
processBlock
(
MachineBasicBlock
&
MBB
)
{
bool
Changed
=
false
;
MachineRegisterInfo
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
for
(
MachineInstr
&
MI
:
MBB
)
{
if
(
!
MI
.
isFullCopy
(
)
)
continue
;
MachineOperand
&
DstMO
=
MI
.
getOperand
(
0
)
;
MachineOperand
&
SrcMO
=
MI
.
getOperand
(
1
)
;
if
(
IsVSReg
(
DstMO
.
getReg
(
)
,
MRI
)
&&
!
IsVSReg
(
SrcMO
.
getReg
(
)
,
MRI
)
)
{
Changed
=
true
;
const
TargetRegisterClass
*
SrcRC
=
&
PPC
::
VSLRCRegClass
;
assert
(
(
IsF8Reg
(
SrcMO
.
getReg
(
)
,
MRI
)
||
IsVSSReg
(
SrcMO
.
getReg
(
)
,
MRI
)
||
IsVSFReg
(
SrcMO
.
getReg
(
)
,
MRI
)
)
&&
"Unknown source for a VSX copy"
)
;
unsigned
NewVReg
=
MRI
.
createVirtualRegister
(
SrcRC
)
;
BuildMI
(
MBB
,
MI
,
MI
.
getDebugLoc
(
)
,
TII
->
get
(
TargetOpcode
::
SUBREG_TO_REG
)
,
NewVReg
)
.
addImm
(
1
)
.
add
(
SrcMO
)
.
addImm
(
PPC
::
sub_64
)
;
SrcMO
.
setReg
(
NewVReg
)
;
}
else
if
(
!
IsVSReg
(
DstMO
.
getReg
(
)
,
MRI
)
&&
IsVSReg
(
SrcMO
.
getReg
(
)
,
MRI
)
)
{
Changed
=
true
;
const
TargetRegisterClass
*
DstRC
=
&
PPC
::
VSLRCRegClass
;
assert
(
(
IsF8Reg
(
DstMO
.
getReg
(
)
,
MRI
)
||
IsVSFReg
(
DstMO
.
getReg
(
)
,
MRI
)
||
IsVSSReg
(
DstMO
.
getReg
(
)
,
MRI
)
)
&&
"Unknown destination for a VSX copy"
)
;
unsigned
NewVReg
=
MRI
.
createVirtualRegister
(
DstRC
)
;
BuildMI
(
MBB
,
MI
,
MI
.
getDebugLoc
(
)
,
TII
->
get
(
TargetOpcode
::
COPY
)
,
NewVReg
)
.
add
(
SrcMO
)
;
SrcMO
.
setReg
(
NewVReg
)
;
SrcMO
.
setSubReg
(
PPC
::
sub_64
)
;
}
}
return
Changed
;
}
</s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s> static rtx rs6000_longcall_ref ( rtx call_ref , rtx arg ) { const char * call_name = XSTR ( call_ref , 0 ) ; if ( * call_name == '.' ) { while ( * call_name == '.' ) call_name ++ ; tree node = get_identifier ( call_name ) ; call_ref = gen_rtx_SYMBOL_REF ( VOIDmode , IDENTIFIER_POINTER ( node ) ) ; } if ( TARGET_PLTSEQ ) { rtx base = const0_rtx ; int regno = 12 ; if ( rs6000_pcrel_p ( ) ) { rtx reg = gen_rtx_REG ( Pmode , regno ) ; rtx u = gen_rtx_UNSPEC_VOLATILE ( Pmode , gen_rtvec ( 3 , base , call_ref , arg ) , UNSPECV_PLT_PCREL ) ; emit_insn ( gen_rtx_SET ( reg , u ) ) ; return reg ; } if ( DEFAULT_ABI == ABI_ELFv2 ) base = gen_rtx_REG ( Pmode , TOC_REGISTER ) ; else { if ( flag_pic ) base = gen_rtx_REG ( Pmode , RS6000_PIC_OFFSET_TABLE_REGNUM ) ; regno = 11 ; } rtx reg = gen_rtx_REG ( Pmode , regno ) ; rtx hi = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 3 , base , call_ref , arg ) , UNSPEC_PLT16_HA ) ; rtx lo = gen_rtx_UNSPEC_VOLATILE ( Pmode , gen_rtvec ( 3 , reg , call_ref , arg ) , UNSPECV_PLT16_LO ) ; emit_insn ( gen_rtx_SET ( reg , hi ) ) ; emit_insn ( gen_rtx_SET ( reg , lo ) ) ; return reg ; } return force_reg ( Pmode , call_ref ) ; } </s>

Return a reference suitable for calling a function with the longcall attribute .


"frame pointer should not have been eliminated"


<s> int s390_const_ok_for_constraint_p ( HOST_WIDE_INT value , int c , const char * str ) { enum machine_mode mode , part_mode ; int def ; int part , part_goal ; gcc_assert ( c == str [ 0 ] ) ; switch ( str [ 0 ] ) { case 'I' : return ( unsigned int ) value < 256 ; case 'J' : return ( unsigned int ) value < 4096 ; case 'K' : return value >= - 32768 && value < 32768 ; case 'L' : return ( TARGET_LONG_DISPLACEMENT ? ( value >= - 524288 && value <= 524287 ) : ( value >= 0 && value <= 4095 ) ) ; case 'M' : return value == 2147483647 ; case 'N' : if ( str [ 1 ] == 'x' ) part_goal = - 1 ; else part_goal = str [ 1 ] - '0' ; switch ( str [ 2 ] ) { case 'Q' : part_mode = QImode ; break ; case 'H' : part_mode = HImode ; break ; case 'S' : part_mode = SImode ; break ; default : return 0 ; } switch ( str [ 3 ] ) { case 'H' : mode = HImode ; break ; case 'S' : mode = SImode ; break ; case 'D' : mode = DImode ; break ; default : return 0 ; } switch ( str [ 4 ] ) { case '0' : def = 0 ; break ; case 'F' : def = - 1 ; break ; default : return 0 ; } if ( GET_MODE_SIZE ( mode ) <= GET_MODE_SIZE ( part_mode ) ) return 0 ; part = s390_single_part ( GEN_INT ( value ) , mode , part_mode , def ) ; if ( part < 0 ) return 0 ; if ( part_goal != - 1 && part_goal != part ) return 0 ; break ; case 'O' : if ( ! TARGET_EXTIMM ) return 0 ; switch ( str [ 1 ] ) { case 's' : return trunc_int_for_mode ( value , SImode ) == value ; case 'p' : return value == 0 || s390_single_part ( GEN_INT ( value ) , DImode , SImode , 0 ) == 1 ; case 'n' : return value == - 1 || s390_single_part ( GEN_INT ( value ) , DImode , SImode , - 1 ) == 1 ; default : gcc_unreachable ( ) ; } break ; case 'P' : return legitimate_reload_constant_p ( GEN_INT ( value ) ) ; default : return 0 ; } return 1 ; } </s>

Return true if VALUE matches the constraint STR .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , RM , CM , OL ) , TargetABI ( computeTargetABI ( TT , CPU , Options ) ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , Subtarget ( TT , CPU , FS , * this , isLittle ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = Subtarget . isTargetHardFloat ( ) ? FloatABI :: Hard : FloatABI :: Soft ; } </s>


"argument of %qE attribute is not a string constant"

"argument of %qE attribute is not \"ilink1\" or \"ilink2\""

"argument of %qE attribute is not \"ilink\""

Handle an `` interrupt '' attribute ; arguments as in struct attribute_spec.handler .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < TargetPassConfig > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static NewSense Def ( unsigned PR , bool True , bool Float ) { NewSense NS = { PR , Float , false , True } ; return NS ; } </s>

Pointer to the VPDef that defines this VPValue .


Return true if at least one possible value of type TYPE includes at least one object of Pure Scalable Type , in the sense of the AAPCS64 . This is a relatively expensive test for some types , so it should generally be made as late as possible .


<s> static void ix86_setup_incoming_varargs ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int * pretend_size ATTRIBUTE_UNUSED , int no_rtl ) { CUMULATIVE_ARGS next_cum ; rtx save_area = NULL_RTX , mem ; rtx label ; rtx label_ref ; rtx tmp_reg ; rtx nsse_reg ; int set ; tree fntype ; int stdarg_p ; int i ; if ( ! TARGET_64BIT ) return ; if ( ! cfun -> va_list_gpr_size && ! cfun -> va_list_fpr_size ) return ; ix86_save_varrargs_registers = 1 ; cfun -> stack_alignment_needed = 128 ; fntype = TREE_TYPE ( current_function_decl ) ; stdarg_p = ( TYPE_ARG_TYPES ( fntype ) != 0 && ( TREE_VALUE ( tree_last ( TYPE_ARG_TYPES ( fntype ) ) ) != void_type_node ) ) ; next_cum = * cum ; if ( stdarg_p ) function_arg_advance ( & next_cum , mode , type , 1 ) ; if ( ! no_rtl ) save_area = frame_pointer_rtx ; set = get_varargs_alias_set ( ) ; for ( i = next_cum . regno ; i < ix86_regparm && i < next_cum . regno + cfun -> va_list_gpr_size / UNITS_PER_WORD ; i ++ ) { mem = gen_rtx_MEM ( Pmode , plus_constant ( save_area , i * UNITS_PER_WORD ) ) ; MEM_NOTRAP_P ( mem ) = 1 ; set_mem_alias_set ( mem , set ) ; emit_move_insn ( mem , gen_rtx_REG ( Pmode , x86_64_int_parameter_registers [ i ] ) ) ; } if ( next_cum . sse_nregs && cfun -> va_list_fpr_size ) { label = gen_label_rtx ( ) ; label_ref = gen_rtx_LABEL_REF ( Pmode , label ) ; tmp_reg = gen_reg_rtx ( Pmode ) ; nsse_reg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_zero_extendqidi2 ( nsse_reg , gen_rtx_REG ( QImode , 0 ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp_reg , gen_rtx_MULT ( Pmode , nsse_reg , GEN_INT ( 4 ) ) ) ) ; if ( next_cum . sse_regno ) emit_move_insn ( nsse_reg , gen_rtx_CONST ( DImode , gen_rtx_PLUS ( DImode , label_ref , GEN_INT ( next_cum . sse_regno * 4 ) ) ) ) ; else emit_move_insn ( nsse_reg , label_ref ) ; emit_insn ( gen_subdi3 ( nsse_reg , nsse_reg , tmp_reg ) ) ; tmp_reg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp_reg , plus_constant ( save_area , 8 * REGPARM_MAX + 127 ) ) ) ; mem = gen_rtx_MEM ( BLKmode , plus_constant ( tmp_reg , - 127 ) ) ; MEM_NOTRAP_P ( mem ) = 1 ; set_mem_alias_set ( mem , set ) ; set_mem_align ( mem , BITS_PER_WORD ) ; emit_insn ( gen_sse_prologue_save ( mem , nsse_reg , GEN_INT ( next_cum . sse_regno ) , label ) ) ; } } </s>

Worker function for TARGET_SETUP_INCOMING_VARARGS .


<s> void LanaiTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; } </s>

This method must be called before any actual lowering is done .


<s> MCSection * X86WindowsTargetObjectFile :: getSectionForConstant ( SectionKind Kind , const Constant * C ) const { if ( Kind . isReadOnly ( ) ) { if ( C ) { Type * Ty = C -> getType ( ) ; SmallString < 32 > COMDATSymName ; if ( Ty -> isFloatTy ( ) || Ty -> isDoubleTy ( ) ) { COMDATSymName = "__real@" ; COMDATSymName += scalarConstantToHexString ( C ) ; } else if ( const auto * VTy = dyn_cast < VectorType > ( Ty ) ) { uint64_t NumBits = VTy -> getBitWidth ( ) ; if ( NumBits == 128 || NumBits == 256 ) { COMDATSymName = NumBits == 128 ? "__xmm@" : "__ymm@" ; for ( int I = VTy -> getNumElements ( ) - 1 , E = - 1 ; I != E ; -- I ) COMDATSymName += scalarConstantToHexString ( C -> getAggregateElement ( I ) ) ; } } if ( ! COMDATSymName . empty ( ) ) { unsigned Characteristics = COFF :: IMAGE_SCN_CNT_INITIALIZED_DATA | COFF :: IMAGE_SCN_MEM_READ | COFF :: IMAGE_SCN_LNK_COMDAT ; return getContext ( ) . getCOFFSection ( ".rdata" , Characteristics , Kind , COMDATSymName , COFF :: IMAGE_COMDAT_SELECT_ANY ) ; } } } return TargetLoweringObjectFile :: getSectionForConstant ( Kind , C ) ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s>
bool
CJGInstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
!
isUnpredicatedTerminator
(
*
I
)
)
break
;
if
(
!
I
->
isBranch
(
)
)
return
true
;
if
(
I
->
getOpcode
(
)
==
CJG
::
JMP
)
{
if
(
!
AllowModify
)
{
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
continue
;
}
while
(
std
::
next
(
I
)
!=
MBB
.
end
(
)
)
std
::
next
(
I
)
->
eraseFromParent
(
)
;
Cond
.
clear
(
)
;
FBB
=
nullptr
;
if
(
MBB
.
isLayoutSuccessor
(
I
->
getOperand
(
0
)
.
getMBB
(
)
)
)
{
TBB
=
nullptr
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
continue
;
}
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
continue
;
}
assert
(
I
->
getOpcode
(
)
==
CJG
::
JCC
&&
"Invalid conditional branch"
)
;
CJGCC
::
CondCodes
BranchCode
=
static_cast
<
CJGCC
::
CondCodes
>
(
I
->
getOperand
(
1
)
.
getImm
(
)
)
;
if
(
BranchCode
==
CJGCC
::
COND_INVALID
)
return
true
;
if
(
Cond
.
empty
(
)
)
{
FBB
=
TBB
;
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
BranchCode
)
)
;
continue
;
}
assert
(
Cond
.
size
(
)
==
1
)
;
assert
(
TBB
)
;
if
(
TBB
!=
I
->
getOperand
(
0
)
.
getMBB
(
)
)
return
true
;
CJGCC
::
CondCodes
OldBranchCode
=
(
CJGCC
::
CondCodes
)
Cond
[
0
]
.
getImm
(
)
;
if
(
OldBranchCode
==
BranchCode
)
continue
;
return
true
;
}
return
false
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> static inline int addsubcosts ( rtx x ) { if ( GET_CODE ( XEXP ( x , 1 ) ) == REG || GET_CODE ( XEXP ( x , 1 ) ) == SUBREG ) return 1 ; if ( GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT && CONST_OK_FOR_ADD ( INTVAL ( XEXP ( x , 1 ) ) ) ) return 1 ; if ( TARGET_SHMEDIA ) switch ( GET_CODE ( XEXP ( x , 1 ) ) ) { case CONST : case LABEL_REF : case SYMBOL_REF : return TARGET_SHMEDIA64 ? 5 : 3 ; case CONST_INT : if ( CONST_OK_FOR_I16 ( INTVAL ( XEXP ( x , 1 ) ) ) ) return 2 ; else if ( CONST_OK_FOR_I16 ( INTVAL ( XEXP ( x , 1 ) ) >> 16 ) ) return 3 ; else if ( CONST_OK_FOR_I16 ( ( INTVAL ( XEXP ( x , 1 ) ) >> 16 ) >> 16 ) ) return 4 ; default : return 5 ; } return 3 ; } </s>

Return the cost of an addition or a subtraction .


<s> bool NVPTXTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( AM . BaseGV ) { return ! AM . BaseOffs && ! AM . HasBaseReg && ! AM . Scale ; } switch ( AM . Scale ) { case 0 : break ; case 1 : if ( AM . HasBaseReg ) return false ; break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s>
unsigned
int
remove
(
void
)
{
unsigned
int
cnt
=
Removables
.
size
(
)
;
for
(
std
::
set
<
MachineInstr
*
>
::
iterator
I
=
Removables
.
begin
(
)
,
E
=
Removables
.
end
(
)
;
I
!=
E
;
++
I
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"  "
<<
*
*
I
)
;
(
*
I
)
->
eraseFromParent
(
)
;
}
Removables
.
clear
(
)
;
return
cnt
;
}
</s>

remove - Remove the specified key/value pair from the map , but do not erase it .


<s> static bool aarch64_function_value_regno_p ( const unsigned int regno ) { if ( regno == R0_REGNUM || regno == R1_REGNUM ) return true ; if ( regno >= V0_REGNUM && regno < V0_REGNUM + HA_MAX_NUM_FLDS ) return TARGET_FLOAT ; return false ; } </s>

Implements TARGET_FUNCTION_VALUE_REGNO_P . Return true if REGNO is the number of a hard register in which the values of called function may come back .


<s> bool isTarget64BitLP64 ( ) const { return In64BitMode && ( ! TargetTriple . isX32 ( ) && ! TargetTriple . isOSNaCl ( ) ) ; } </s>

Is this x86_64 with the LP64 programming model ( standard AMD64 , no x32 ) ?


<s> bool empty ( ) const { return ! Bits . any ( ) ; } </s>

Determine whether this version information is empty ( e.g. , all version components are zero ) .


<s> rtx unicosmk_add_call_info_word ( rtx x ATTRIBUTE_UNUSED ) { return NULL_RTX ; } </s>

Add a call information word ( CIW ) to the list of the current function 's CIWs and return its index . X is a CONST_INT or CONST_DOUBLE representing the CIW .


<s> static rtx rl78_lo16 ( rtx addr ) { rtx r ; if ( GET_CODE ( addr ) == SYMBOL_REF || GET_CODE ( addr ) == CONST ) { r = gen_rtx_ZERO_EXTRACT ( HImode , addr , GEN_INT ( 16 ) , GEN_INT ( 0 ) ) ; r = gen_rtx_CONST ( HImode , r ) ; } else r = rl78_subreg ( HImode , addr , SImode , 0 ) ; r = gen_es_addr ( r ) ; cfun -> machine -> uses_es = true ; return r ; } </s>

Return a suitable RTX for the low half of a __far address .


<s> bool arm_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_NEON && ( mode == V2SFmode || mode == V4SImode || mode == V8HImode || mode == V4HFmode || mode == V16QImode || mode == V4SFmode || mode == V2DImode || mode == V8HFmode || mode == V4BFmode || mode == V8BFmode ) ) return true ; if ( ( TARGET_NEON || TARGET_IWMMXT ) && ( ( mode == V2SImode ) || ( mode == V4HImode ) || ( mode == V8QImode ) ) ) return true ; if ( TARGET_INT_SIMD && ( mode == V4UQQmode || mode == V4QQmode || mode == V2UHQmode || mode == V2HQmode || mode == V2UHAmode || mode == V2HAmode ) ) return true ; if ( TARGET_HAVE_MVE && ( mode == V2DImode || mode == V4SImode || mode == V8HImode || mode == V16QImode || mode == V16BImode || mode == V8BImode || mode == V4BImode ) ) return true ; if ( TARGET_HAVE_MVE_FLOAT && ( mode == V2DFmode || mode == V4SFmode || mode == V8HFmode ) ) return true ; return false ; } </s>

Implements target hook vector_mode_supported_p .


<s> static const char * sparc_mangle_type ( const_tree type ) { if ( TARGET_ARCH32 && TYPE_MAIN_VARIANT ( type ) == long_double_type_node && TARGET_LONG_DOUBLE_128 ) return "g" ; return NULL ; } </s>


<s>
bool
AArch64BranchRelaxation
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
MF
=
&
mf
;
if
(
!
BranchRelaxation
)
return
false
;
DEBUG
(
dbgs
(
)
<<
"***** AArch64BranchRelaxation *****\n"
)
;
TII
=
(
const
AArch64InstrInfo
*
)
MF
->
getTarget
(
)
.
getInstrInfo
(
)
;
MF
->
RenumberBlocks
(
)
;
scanFunction
(
)
;
DEBUG
(
dbgs
(
)
<<
"  Basic blocks before relaxation\n"
)
;
DEBUG
(
dumpBBs
(
)
)
;
bool
MadeChange
=
false
;
while
(
relaxBranchInstructions
(
)
)
MadeChange
=
true
;
verify
(
)
;
DEBUG
(
dbgs
(
)
<<
"  Basic blocks after relaxation\n"
)
;
DEBUG
(
dbgs
(
)
<<
'\n'
;
dumpBBs
(
)
)
;
BlockInfo
.
clear
(
)
;
return
MadeChange
;
}
</s>

runOnMachineFunction - Emit the function body .