<s> bool SITargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , Align Alignment , MachineMemOperand :: Flags Flags , bool * IsFast ) const { bool Allow = allowsMisalignedMemoryAccessesImpl ( VT . getSizeInBits ( ) , AddrSpace , Alignment , Flags , IsFast ) ; if ( Allow && IsFast && Subtarget -> hasUnalignedDSAccessEnabled ( ) && ( AddrSpace == AMDGPUAS :: LOCAL_ADDRESS || AddrSpace == AMDGPUAS :: REGION_ADDRESS ) ) { * IsFast = true ; } return Allow ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> static bool arm_legitimate_constant_p_1 ( machine_mode , rtx x ) { if ( GET_CODE ( x ) == CONST_VECTOR && ! neon_make_constant ( x , false ) ) return false ; return flag_pic || ! label_mentioned_p ( x ) ; } </s>

Implement TARGET_LEGITIMATE_CONSTANT_P . On the ARM , allow any integer ( invalid ones are removed later by insn patterns ) , nice doubles and symbol_refs which refer to the function 's constant pool XXX . When generating pic allow anything .


<s>
static
void
rl78_start_function
(
FILE
*
file
,
HOST_WIDE_INT
hwi_local
ATTRIBUTE_UNUSED
)
{
int
i
;
if
(
cfun
->
machine
->
framesize
==
0
)
return
;
fprintf
(
file
,
"\t; start of function\n"
)
;
if
(
cfun
->
machine
->
framesize_regs
)
{
fprintf
(
file
,
"\t; push %d:"
,
cfun
->
machine
->
framesize_regs
)
;
for
(
i
=
0
;
i
<
16
;
i
++
)
if
(
cfun
->
machine
->
need_to_push
[
i
]
)
fprintf
(
file
,
" %s"
,
word_regnames
[
i
*
2
]
)
;
fprintf
(
file
,
"\n"
)
;
}
if
(
frame_pointer_needed
)
fprintf
(
file
,
"\t; $fp points here (r22)\n"
)
;
if
(
cfun
->
machine
->
framesize_locals
)
fprintf
(
file
,
"\t; locals: %d byte%s\n"
,
cfun
->
machine
->
framesize_locals
,
cfun
->
machine
->
framesize_locals
==
1
""
:
"s"
)
;
if
(
cfun
->
machine
->
framesize_outgoing
)
fprintf
(
file
,
"\t; outgoing: %d byte%s\n"
,
cfun
->
machine
->
framesize_outgoing
,
cfun
->
machine
->
framesize_outgoing
==
1
""
:
"s"
)
;
if
(
cfun
->
machine
->
uses_es
)
fprintf
(
file
,
"\t; uses ES register\n"
)
;
}
</s>

We do n't use this to actually emit the function prologue . We use this to insert a comment in the asm file describing the function .


<s> unsigned int reg_or_subreg_regno ( rtx op ) { unsigned int regno ; if ( GET_CODE ( op ) == REG ) regno = REGNO ( op ) ; else if ( GET_CODE ( op ) == SUBREG && GET_CODE ( SUBREG_REG ( op ) ) == REG ) { if ( REGNO ( SUBREG_REG ( op ) ) < FIRST_PSEUDO_REGISTER ) regno = subreg_regno ( op ) ; else regno = REGNO ( SUBREG_REG ( op ) ) ; } else regno = INVALID_REGNUM ; return regno ; } </s>

Return the register number if OP is a REG or a SUBREG of a REG , and INVALID_REGNUM in all the other cases .


<s> const char * MipsTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case MipsISD :: JmpLink : return "MipsISD::JmpLink" ; case MipsISD :: Hi : return "MipsISD::Hi" ; case MipsISD :: Lo : return "MipsISD::Lo" ; case MipsISD :: GPRel : return "MipsISD::GPRel" ; case MipsISD :: Ret : return "MipsISD::Ret" ; case MipsISD :: SelectCC : return "MipsISD::SelectCC" ; case MipsISD :: FPSelectCC : return "MipsISD::FPSelectCC" ; case MipsISD :: FPBrcond : return "MipsISD::FPBrcond" ; case MipsISD :: FPCmp : return "MipsISD::FPCmp" ; case MipsISD :: FPRound : return "MipsISD::FPRound" ; case MipsISD :: MAdd : return "MipsISD::MAdd" ; case MipsISD :: MAddu : return "MipsISD::MAddu" ; case MipsISD :: MSub : return "MipsISD::MSub" ; case MipsISD :: MSubu : return "MipsISD::MSubu" ; case MipsISD :: DivRem : return "MipsISD::DivRem" ; case MipsISD :: DivRemU : return "MipsISD::DivRemU" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific

Mips Mips MipsISD::JmpLink "MipsISD::JmpLink" MipsISD::Hi "MipsISD::Hi" MipsISD::Lo "MipsISD::Lo" MipsISD::GPRel "MipsISD::GPRel" MipsISD::Ret "MipsISD::Ret" MipsISD::SelectCC "MipsISD::SelectCC" MipsISD::FPSelectCC "MipsISD::FPSelectCC" MipsISD::FPBrcond "MipsISD::FPBrcond" MipsISD::FPCmp "MipsISD::FPCmp" MipsISD::FPRound "MipsISD::FPRound" MipsISD::MAdd "MipsISD::MAdd" MipsISD::MAddu "MipsISD::MAddu" MipsISD::MSub "MipsISD::MSub" MipsISD::MSubu "MipsISD::MSubu" MipsISD::DivRem "MipsISD::DivRem" MipsISD::DivRemU "MipsISD::DivRemU"


<s> static bool find_mem_ref ( rtx pat , rtx * mem_ref ) { const char * fmt ; int i , j ; if ( tie_operand ( pat , VOIDmode ) ) return false ; if ( MEM_P ( pat ) ) { * mem_ref = pat ; return true ; } fmt = GET_RTX_FORMAT ( GET_CODE ( pat ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( pat ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'e' ) { if ( find_mem_ref ( XEXP ( pat , i ) , mem_ref ) ) return true ; } else if ( fmt [ i ] == 'E' ) for ( j = XVECLEN ( pat , i ) - 1 ; j >= 0 ; j -- ) { if ( find_mem_ref ( XVECEXP ( pat , i , j ) , mem_ref ) ) return true ; } } return false ; } </s>

Determine if PAT refers to memory . If so , set MEM_REF to the MEM rtx and return true .


<s> const JVMRegisterInfo * getRegisterInfo ( ) const override { return & getInstrInfo ( ) -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < AMDGPUArgumentUsageInfo > ( ) ; SelectionDAGISel :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void SITargetLowering :: finalizeLowering ( MachineFunction & MF ) const { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; SIMachineFunctionInfo * Info = MF . getInfo < SIMachineFunctionInfo > ( ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const SIRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; if ( Info -> isEntryFunction ( ) ) { reservePrivateMemoryRegs ( getTargetMachine ( ) , MF , * TRI , * Info ) ; } assert ( ! TRI -> isSubRegister ( Info -> getScratchRSrcReg ( ) , Info -> getStackPtrOffsetReg ( ) ) ) ; if ( Info -> getStackPtrOffsetReg ( ) != AMDGPU :: SP_REG ) MRI . replaceRegWith ( AMDGPU :: SP_REG , Info -> getStackPtrOffsetReg ( ) ) ; if ( Info -> getScratchRSrcReg ( ) != AMDGPU :: PRIVATE_RSRC_REG ) MRI . replaceRegWith ( AMDGPU :: PRIVATE_RSRC_REG , Info -> getScratchRSrcReg ( ) ) ; if ( Info -> getFrameOffsetReg ( ) != AMDGPU :: FP_REG ) MRI . replaceRegWith ( AMDGPU :: FP_REG , Info -> getFrameOffsetReg ( ) ) ; Info -> limitOccupancy ( MF ) ; if ( ST . isWave32 ( ) && ! MF . empty ( ) ) { const SIInstrInfo * TII = ST . getInstrInfo ( ) ; for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { TII -> fixImplicitOperands ( MI ) ; } } } TargetLoweringBase :: finalizeLowering ( MF ) ; if ( VGPRReserveforSGPRSpill && ! Info -> VGPRReservedForSGPRSpill && ! Info -> isEntryFunction ( ) && MF . getFrameInfo ( ) . hasStackObjects ( ) ) Info -> reserveVGPRforSGPRSpills ( MF ) ; } </s>

Execute target specific actions to finalize target lowering .


<s> const MCExpr * getSubExpr ( ) const { return Expr ; } </s>

getSubExpr - Get the child of this expression .


<s> const char * MipsTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case MipsISD :: JmpLink : return "MipsISD::JmpLink" ; case MipsISD :: Hi : return "MipsISD::Hi" ; case MipsISD :: Lo : return "MipsISD::Lo" ; case MipsISD :: GPRel : return "MipsISD::GPRel" ; case MipsISD :: Ret : return "MipsISD::Ret" ; case MipsISD :: SelectCC : return "MipsISD::SelectCC" ; case MipsISD :: FPSelectCC : return "MipsISD::FPSelectCC" ; case MipsISD :: FPBrcond : return "MipsISD::FPBrcond" ; case MipsISD :: FPCmp : return "MipsISD::FPCmp" ; case MipsISD :: FPRound : return "MipsISD::FPRound" ; default : return NULL ; } } </s>

Mips Mips MipsISD::JmpLink "MipsISD::JmpLink" MipsISD::Hi "MipsISD::Hi" MipsISD::Lo "MipsISD::Lo" MipsISD::GPRel "MipsISD::GPRel" MipsISD::Ret "MipsISD::Ret" MipsISD::SelectCC "MipsISD::SelectCC" MipsISD::FPSelectCC "MipsISD::FPSelectCC" MipsISD::FPBrcond "MipsISD::FPBrcond" MipsISD::FPCmp "MipsISD::FPCmp" MipsISD::FPRound "MipsISD::FPRound"


<s> void SystemZInstPrinter :: printRegName ( raw_ostream & O , unsigned RegNo ) const { O << '%' << getRegisterName ( RegNo ) ; } </s>


<s> bool GBZ80PostRA :: runOnMachineFunction ( MachineFunction & MF ) { bool Modified = false ; this -> MF = & MF ; const GBZ80Subtarget & STI = MF . getSubtarget < GBZ80Subtarget > ( ) ; TRI = STI . getRegisterInfo ( ) ; TII = STI . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; Modified |= expandPostRAPseudos ( ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s>
static
int
ia64_dfa_new_cycle
(
FILE
*
dump
,
int
verbose
,
rtx_insn
*
insn
,
int
last_clock
,
int
clock
,
int
*
sort_p
)
{
gcc_assert
(
insn
&&
INSN_P
(
insn
)
)
;
if
(
DEBUG_INSN_P
(
insn
)
)
return
0
;
gcc_assert
(
!
(
reload_completed
&&
safe_group_barrier_needed
(
insn
)
)
||
last_scheduled_insn
)
;
if
(
(
reload_completed
&&
(
safe_group_barrier_needed
(
insn
)
||
(
mflag_sched_stop_bits_after_every_cycle
&&
last_clock
!=
clock
&&
last_scheduled_insn
&&
scheduled_good_insn
(
last_scheduled_insn
)
)
)
)
||
(
last_scheduled_insn
&&
(
CALL_P
(
last_scheduled_insn
)
||
unknown_for_bundling_p
(
last_scheduled_insn
)
)
)
)
{
init_insn_group_barriers
(
)
;
if
(
verbose
&&
dump
)
fprintf
(
dump
,
"//    Stop should be before %d%s\n"
,
INSN_UID
(
insn
)
,
last_clock
==
clock
" + cycle advance"
:
""
)
;
stop_before_p
=
1
;
current_cycle
=
clock
;
mem_ops_in_group
[
current_cycle
%
4
]
=
0
;
if
(
last_clock
==
clock
)
{
state_transition
(
curr_state
,
dfa_stop_insn
)
;
if
(
TARGET_EARLY_STOP_BITS
)
*
sort_p
=
(
last_scheduled_insn
==
NULL_RTX
||
!
CALL_P
(
last_scheduled_insn
)
)
;
else
*
sort_p
=
0
;
return
1
;
}
if
(
last_scheduled_insn
)
{
if
(
unknown_for_bundling_p
(
last_scheduled_insn
)
)
state_reset
(
curr_state
)
;
else
{
memcpy
(
curr_state
,
prev_cycle_state
,
dfa_state_size
)
;
state_transition
(
curr_state
,
dfa_stop_insn
)
;
state_transition
(
curr_state
,
dfa_pre_cycle_insn
)
;
state_transition
(
curr_state
,
)
;
}
}
}
return
0
;
}
</s>

We are about to being issuing INSN . Return nonzero if we can not issue it on given cycle CLOCK and return zero if we should not sort the ready queue on the next clock start .


<s> std :: pair < unsigned , const TargetRegisterClass * > SystemZTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'd' : case 'r' : if ( VT == MVT :: i64 ) return std :: make_pair ( 0U , & SystemZ :: GR64BitRegClass ) ; else if ( VT == MVT :: i128 ) return std :: make_pair ( 0U , & SystemZ :: GR128BitRegClass ) ; return std :: make_pair ( 0U , & SystemZ :: GR32BitRegClass ) ; case 'a' : if ( VT == MVT :: i64 ) return std :: make_pair ( 0U , & SystemZ :: ADDR64BitRegClass ) ; else if ( VT == MVT :: i128 ) return std :: make_pair ( 0U , & SystemZ :: ADDR128BitRegClass ) ; return std :: make_pair ( 0U , & SystemZ :: ADDR32BitRegClass ) ; case 'h' : return std :: make_pair ( 0U , & SystemZ :: GRH32BitRegClass ) ; case 'f' : if ( VT == MVT :: f64 ) return std :: make_pair ( 0U , & SystemZ :: FP64BitRegClass ) ; else if ( VT == MVT :: f128 ) return std :: make_pair ( 0U , & SystemZ :: FP128BitRegClass ) ; return std :: make_pair ( 0U , & SystemZ :: FP32BitRegClass ) ; } } if ( Constraint [ 0 ] == '{' ) { if ( Constraint [ 1 ] == 'r' ) { if ( VT == MVT :: i32 ) return parseRegisterNumber ( Constraint , & SystemZ :: GR32BitRegClass , SystemZMC :: GR32Regs ) ; if ( VT == MVT :: i128 ) return parseRegisterNumber ( Constraint , & SystemZ :: GR128BitRegClass , SystemZMC :: GR128Regs ) ; return parseRegisterNumber ( Constraint , & SystemZ :: GR64BitRegClass , SystemZMC :: GR64Regs ) ; } if ( Constraint [ 1 ] == 'f' ) { if ( VT == MVT :: f32 ) return parseRegisterNumber ( Constraint , & SystemZ :: FP32BitRegClass , SystemZMC :: FP32Regs ) ; if ( VT == MVT :: f128 ) return parseRegisterNumber ( Constraint , & SystemZ :: FP128BitRegClass , SystemZMC :: FP128Regs ) ; return parseRegisterNumber ( Constraint , & SystemZ :: FP64BitRegClass , SystemZMC :: FP64Regs ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


"The MBB is not the destination of an indirect jump"


<s> static rtx s390_two_part_insv ( struct alignment_context * ac , rtx * seq1 , rtx * seq2 , machine_mode mode , rtx val , rtx ins ) { rtx tmp ; if ( ac -> aligned ) { start_sequence ( ) ; tmp = copy_to_mode_reg ( SImode , val ) ; if ( s390_expand_insv ( tmp , GEN_INT ( GET_MODE_BITSIZE ( mode ) ) , const0_rtx , ins ) ) { * seq1 = NULL ; * seq2 = get_insns ( ) ; end_sequence ( ) ; return tmp ; } end_sequence ( ) ; } start_sequence ( ) ; tmp = s390_expand_mask_and_shift ( ins , mode , ac -> shift ) ; * seq1 = get_insns ( ) ; end_sequence ( ) ; start_sequence ( ) ; tmp = expand_simple_binop ( SImode , IOR , tmp , val , NULL_RTX , 1 , OPTAB_DIRECT ) ; * seq2 = get_insns ( ) ; end_sequence ( ) ; return tmp ; } </s>

A subroutine of s390_expand_cs_hqi . Insert INS into VAL . If possible , use a single insv insn into SEQ2 . Otherwise , put prep insns in SEQ1 and perform the merge in SEQ2 .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> unsigned PPCRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; if ( ! Subtarget . isPPC64 ( ) ) return TFI -> hasFP ( MF ) ? PPC :: R31 : PPC :: R1 ; else return TFI -> hasFP ( MF ) ? PPC :: X31 : PPC :: X1 ; } </s>


<s> bool isToken ( ) const override { return Kind == KindTy :: Token ; } </s>


<s> static rtx shifter_op_p ( rtx op , rtx * shift_reg ) { enum rtx_code code = GET_CODE ( op ) ; if ( code == MULT && CONST_INT_P ( XEXP ( op , 1 ) ) && exact_log2 ( INTVAL ( XEXP ( op , 1 ) ) ) > 0 ) return XEXP ( op , 0 ) ; else if ( code == ROTATE && CONST_INT_P ( XEXP ( op , 1 ) ) ) return XEXP ( op , 0 ) ; else if ( code == ROTATERT || code == ASHIFT || code == LSHIFTRT || code == ASHIFTRT ) { if ( ! CONST_INT_P ( XEXP ( op , 1 ) ) ) * shift_reg = XEXP ( op , 1 ) ; return XEXP ( op , 0 ) ; } return NULL ; } </s>

Helper function for arm_rtx_costs . If the operand is a valid shift operand , then return the operand that is being shifted . If the shift is not by a constant , then set SHIFT_REG to point to the operand . Return NULL if OP is not a shifter operand .


<s> unsigned getNumFixupKinds ( ) const { return Mips :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> const MCPhysReg * MOSRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const MOSFrameLowering & TFI = * getFrameLowering ( * MF ) ; return TFI . isISR ( * MF ) ? MOS_Interrupt_CSR_SaveList : MOS_CSR_SaveList ; } </s>


<s> virtual const IA64InstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s>
unsigned
HexagonInstrInfo
::
createVR
(
MachineFunction
*
MF
,
MVT
VT
)
const
{
MachineRegisterInfo
&
RegInfo
=
MF
->
getRegInfo
(
)
;
const
TargetRegisterClass
*
TRC
;
if
(
VT
==
MVT
::
i1
)
{
TRC
=
&
Hexagon
::
PredRegsRegClass
;
}
else
if
(
VT
==
MVT
::
i32
||
VT
==
MVT
::
f32
)
{
TRC
=
&
Hexagon
::
IntRegsRegClass
;
}
else
if
(
VT
==
MVT
::
i64
||
VT
==
MVT
::
f64
)
{
TRC
=
&
Hexagon
::
DoubleRegsRegClass
;
}
else
{
llvm_unreachable
(
"Cannot handle this register class"
)
;
}
unsigned
NewReg
=
RegInfo
.
createVirtualRegister
(
TRC
)
;
return
NewReg
;
}
</s>


<s> void PPCPostRASchedStrategy :: tryCandidate ( SchedCandidate & Cand , SchedCandidate & TryCand ) { if ( ! Cand . isValid ( ) ) { TryCand . Reason = NodeOrder ; return ; } if ( tryLess ( Top . getLatencyStallCycles ( TryCand . SU ) , Top . getLatencyStallCycles ( Cand . SU ) , TryCand , Cand , Stall ) ) return ; if ( tryGreater ( TryCand . SU == DAG -> getNextClusterSucc ( ) , Cand . SU == DAG -> getNextClusterSucc ( ) , TryCand , Cand , Cluster ) ) return ; if ( tryLess ( TryCand . ResDelta . CritResources , Cand . ResDelta . CritResources , TryCand , Cand , ResourceReduce ) ) return ; if ( tryGreater ( TryCand . ResDelta . DemandedResources , Cand . ResDelta . DemandedResources , TryCand , Cand , ResourceDemand ) ) return ; if ( Cand . Policy . ReduceLatency && tryLatency ( TryCand , Cand , Top ) ) { return ; } if ( TryCand . SU -> NodeNum < Cand . SU -> NodeNum ) TryCand . Reason = NodeOrder ; if ( TryCand . Reason != NodeOrder && TryCand . Reason != NoCand ) return ; if ( biasAddiCandidate ( Cand , TryCand ) ) return ; } </s>

Apply a set of heuristics to a new candidate .


<s> bool HexagonTTIImpl :: isLegalMaskedLoad ( Type * DataType , Align ) { return HexagonMaskedVMem && ST . isTypeForHVX ( DataType ) ; } </s>

Return true if the target supports masked load .


<s> static machine_mode rs6000_preferred_simd_mode ( scalar_mode mode ) { if ( TARGET_VSX ) switch ( mode ) { case E_DFmode : return V2DFmode ; default : ; } if ( TARGET_ALTIVEC || TARGET_VSX ) switch ( mode ) { case E_SFmode : return V4SFmode ; case E_TImode : return V1TImode ; case E_DImode : return V2DImode ; case E_SImode : return V4SImode ; case E_HImode : return V8HImode ; case E_QImode : return V16QImode ; default : ; } if ( TARGET_PAIRED_FLOAT && mode == SFmode ) return V2SFmode ; return word_mode ; } </s>


"warning: some functions compiled with BTI and some compiled "

"warning: not setting BTI in feature flags\n"

This virtual method can be overridden by targets that want to emit something at the start of their file .


<s> bool use_simple_return_p ( void ) { arm_stack_offsets * offsets ; offsets = arm_get_frame_offsets ( ) ; return offsets -> outgoing_args != 0 ; } </s>

Return TRUE if we should try to use a simple_return insn , i.e . perform shrink-wrapping if possible . This is the case if we need to emit a prologue , which we can test by looking at the offsets .


<s> void ScheduleDAGPostRA :: placeDebugValues ( ) { if ( FirstDbgValue ) { BB -> splice ( RegionBegin , BB , FirstDbgValue ) ; RegionBegin = FirstDbgValue ; } for ( std :: vector < std :: pair < MachineInstr * , MachineInstr * > > :: iterator DI = DbgValues . end ( ) , DE = DbgValues . begin ( ) ; DI != DE ; -- DI ) { std :: pair < MachineInstr * , MachineInstr * > P = * std :: prev ( DI ) ; MachineInstr * DbgValue = P . first ; MachineBasicBlock :: instr_iterator OrigPrevMI ( P . second ) ; while ( OrigPrevMI -> isBundledWithSucc ( ) ) { OrigPrevMI ++ ; } moveInstruction ( DbgValue -> getIterator ( ) , ++ OrigPrevMI ) ; } DbgValues . clear ( ) ; FirstDbgValue = NULL ; } </s>

Reinsert debug_values recorded in ScheduleDAGInstrs : :DbgValues .


<s> enum reg_class mep_preferred_reload_class ( rtx x , enum reg_class rclass ) { switch ( GET_CODE ( x ) ) { case CONST_INT : if ( INTVAL ( x ) >= 0x10000 && INTVAL ( x ) < 0x01000000 && ( INTVAL ( x ) & 0xffff ) != 0 && reg_class_subset_p ( TPREL_REGS , rclass ) ) rclass = TPREL_REGS ; break ; case CONST : case SYMBOL_REF : case LABEL_REF : if ( mep_section_tag ( x ) != 'f' && reg_class_subset_p ( TPREL_REGS , rclass ) ) rclass = TPREL_REGS ; break ; default : break ; } return rclass ; } </s>

Implement PREFERRED_RELOAD_CLASS . See whether X is a constant that can be moved directly into registers 0 to 7 , but not into the rest . If so , and if the required class includes registers 0 to 7 , restrict it to those registers .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Remove sign extends"
;
}
</s>

getPassName - Return a nice clean name for a pass .


This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly


<s> void WebAssemblyAsmPrinter :: emitGlobalVariable ( const GlobalVariable * GV ) { if ( ! WebAssembly :: isWasmVarAddressSpace ( GV -> getAddressSpace ( ) ) ) { AsmPrinter :: emitGlobalVariable ( GV ) ; return ; } assert ( ! GV -> isThreadLocal ( ) ) ; MCSymbolWasm * Sym = cast < MCSymbolWasm > ( getSymbol ( GV ) ) ; if ( ! Sym -> getType ( ) ) { SmallVector < MVT , 1 > VTs ; Type * GlobalVT = GV -> getValueType ( ) ; if ( Subtarget ) { const WebAssemblyTargetLowering & TLI = * Subtarget -> getTargetLowering ( ) ; computeLegalValueVTs ( TLI , GV -> getParent ( ) -> getContext ( ) , GV -> getParent ( ) -> getDataLayout ( ) , GlobalVT , VTs ) ; } WebAssembly :: wasmSymbolSetType ( Sym , GlobalVT , VTs ) ; } emitVisibility ( Sym , GV -> getVisibility ( ) , ! GV -> isDeclaration ( ) ) ; emitSymbolType ( Sym ) ; if ( GV -> hasInitializer ( ) ) { assert ( getSymbolPreferLocal ( * GV ) == Sym ) ; emitLinkage ( GV , Sym ) ; OutStreamer -> emitLabel ( Sym ) ; OutStreamer -> AddBlankLine ( ) ; } } </s>

Emit the specified global variable to the .s file .

WebAssembly WebAssembly WebAssembly::isWasmVarAddressSpace 1 WebAssembly WebAssembly::wasmSymbolSetType


<s>
void
mmix_asm_output_def
(
FILE
*
stream
,
const
char
*
name
,
const
char
*
value
)
{
assemble_name
(
stream
,
name
)
;
fprintf
(
stream
,
"\tIS "
)
;
assemble_name
(
stream
,
value
)
;
fputc
(
'\n'
,
stream
)
;
}
</s>


<s>
bool
AArch64PostLegalizerLowering
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
MF
.
getProperties
(
)
.
hasProperty
(
MachineFunctionProperties
::
Property
::
FailedISel
)
)
return
false
;
assert
(
MF
.
getProperties
(
)
.
hasProperty
(
MachineFunctionProperties
::
Property
::
Legalized
)
&&
"Expected a legalized function?"
)
;
auto
*
TPC
=
&
getAnalysis
<
TargetPassConfig
>
(
)
;
const
Function
&
F
=
MF
.
getFunction
(
)
;
AArch64PostLegalizerLoweringInfo
PCInfo
(
F
.
hasOptSize
(
)
,
F
.
hasMinSize
(
)
)
;
Combiner
C
(
PCInfo
,
TPC
)
;
return
C
.
combineMachineInstrs
(
MF
,
nullptr
)
;
}
</s>


<s>
static
bool
avr_assemble_integer
(
rtx
x
,
unsigned
int
size
,
int
aligned_p
)
{
if
(
size
==
POINTER_SIZE
/
BITS_PER_UNIT
&&
aligned_p
&&
text_segment_operand
(
x
,
VOIDmode
)
)
{
fputs
(
"\t.word\tgs("
,
asm_out_file
)
;
output_addr_const
(
asm_out_file
,
x
)
;
fputs
(
")\n"
,
asm_out_file
)
;
return
true
;
}
else
if
(
GET_MODE
(
x
)
==
PSImode
)
{
fputs
(
"\t.byte\tlo8("
,
asm_out_file
)
;
output_addr_const
(
asm_out_file
,
x
)
;
fputs
(
")"
ASM_COMMENT_START
"need binutils PR13503\n"
,
asm_out_file
)
;
fputs
(
"\t.byte\thi8("
,
asm_out_file
)
;
output_addr_const
(
asm_out_file
,
x
)
;
fputs
(
")"
ASM_COMMENT_START
"need binutils PR13503\n"
,
asm_out_file
)
;
fputs
(
"\t.byte\thh8("
,
asm_out_file
)
;
output_addr_const
(
asm_out_file
,
x
)
;
fputs
(
")"
ASM_COMMENT_START
"need binutils PR13503\n"
,
asm_out_file
)
;
return
true
;
}
else
if
(
CONST_FIXED_P
(
x
)
)
{
unsigned
n
;
for
(
n
=
0
;
n
<
size
;
n
++
)
{
rtx
xn
=
simplify_gen_subreg
(
QImode
,
x
,
GET_MODE
(
x
)
,
n
)
;
default_assemble_integer
(
xn
,
1
,
aligned_p
)
;
}
return
true
;
}
return
default_assemble_integer
(
x
,
size
,
aligned_p
)
;
}
</s>

Target hook for assembling integer objects . The AVR version needs special handling for references to certain labels .


<s> Register M88kRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { if ( getFrameLowering ( MF ) -> hasFP ( MF ) ) return M88k :: R30 ; return M88k :: R31 ; } </s>


<s> void addPostRegAlloc ( ) override { if ( getMipsSubtarget ( ) . isCheri ( ) ) addPass ( createCheriInvalidatePass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> const OR1KInstrInfo * getInstrInfo ( ) { return getTargetMachine ( ) . getInstrInfo ( ) ; } </s>


<s> bool AArch64TargetLowering :: shouldLocalize ( const MachineInstr & MI , const TargetTransformInfo * TTI ) const { switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_GLOBAL_VALUE : { const GlobalValue & GV = * MI . getOperand ( 1 ) . getGlobal ( ) ; if ( GV . isThreadLocal ( ) && Subtarget -> isTargetMachO ( ) ) return false ; break ; } case AArch64 :: ADRP : case AArch64 :: G_ADD_LOW : return true ; default : break ; } return TargetLoweringBase :: shouldLocalize ( MI , TTI ) ; } </s>

Check whether or not MI needs to be moved close to its uses .


<s> ScheduleHazardRecognizer :: HazardType GCNHazardRecognizer :: getHazardType ( SUnit * SU , int Stalls ) { MachineInstr * MI = SU -> getInstr ( ) ; if ( SIInstrInfo :: isSMRD ( * MI ) && checkSMRDHazards ( MI ) > 0 ) return NoopHazard ; if ( ( SIInstrInfo :: isVMEM ( * MI ) || SIInstrInfo :: isFLAT ( * MI ) ) && checkVMEMHazards ( MI ) > 0 ) return NoopHazard ; if ( SIInstrInfo :: isVALU ( * MI ) && checkVALUHazards ( MI ) > 0 ) return NoopHazard ; if ( SIInstrInfo :: isDPP ( * MI ) && checkDPPHazards ( MI ) > 0 ) return NoopHazard ; if ( isDivFMas ( MI -> getOpcode ( ) ) && checkDivFMasHazards ( MI ) > 0 ) return NoopHazard ; if ( isRWLane ( MI -> getOpcode ( ) ) && checkRWLaneHazards ( MI ) > 0 ) return NoopHazard ; if ( isSGetReg ( MI -> getOpcode ( ) ) && checkGetRegHazards ( MI ) > 0 ) return NoopHazard ; if ( isSSetReg ( MI -> getOpcode ( ) ) && checkSetRegHazards ( MI ) > 0 ) return NoopHazard ; if ( isRFE ( MI -> getOpcode ( ) ) && checkRFEHazards ( MI ) > 0 ) return NoopHazard ; if ( ST . hasReadM0MovRelInterpHazard ( ) && ( TII . isVINTRP ( * MI ) || isSMovRel ( MI -> getOpcode ( ) ) ) && checkReadM0Hazards ( MI ) > 0 ) return NoopHazard ; if ( ST . hasReadM0SendMsgHazard ( ) && isSendMsgTraceDataOrGDS ( * MI ) && checkReadM0Hazards ( MI ) > 0 ) return NoopHazard ; if ( MI -> isInlineAsm ( ) && checkInlineAsmHazards ( MI ) > 0 ) return NoopHazard ; if ( checkAnyInstHazards ( MI ) > 0 ) return NoopHazard ; return NoHazard ; } </s>

getHazardType - Return the hazard type of emitting this node .


<s>
bool
X86InstrInfo
::
classifyLEAReg
(
MachineInstr
&
MI
,
const
MachineOperand
&
Src
,
unsigned
Opc
,
bool
AllowSP
,
Register
&
NewSrc
,
bool
&
isKill
,
MachineOperand
&
ImplicitOp
,
LiveVariables
*
LV
,
LiveIntervals
*
LIS
)
const
{
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
const
TargetRegisterClass
*
RC
;
if
(
AllowSP
)
{
RC
=
Opc
!=
X86
::
LEA32r
&
X86
::
GR64RegClass
:
&
X86
::
GR32RegClass
;
}
else
{
RC
=
Opc
!=
X86
::
LEA32r
&
X86
::
GR64_NOSPRegClass
:
&
X86
::
GR32_NOSPRegClass
;
}
Register
SrcReg
=
Src
.
getReg
(
)
;
isKill
=
MI
.
killsRegister
(
SrcReg
)
;
if
(
Opc
!=
X86
::
LEA64_32r
)
{
NewSrc
=
SrcReg
;
assert
(
!
Src
.
isUndef
(
)
&&
"Undef op doesn't need optimization"
)
;
if
(
NewSrc
.
isVirtual
(
)
&&
!
MF
.
getRegInfo
(
)
.
constrainRegClass
(
NewSrc
,
RC
)
)
return
false
;
return
true
;
}
if
(
SrcReg
.
isPhysical
(
)
)
{
ImplicitOp
=
Src
;
ImplicitOp
.
setImplicit
(
)
;
NewSrc
=
getX86SubSuperRegister
(
SrcReg
,
64
)
;
assert
(
!
Src
.
isUndef
(
)
&&
"Undef op doesn't need optimization"
)
;
}
else
{
NewSrc
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
RC
)
;
MachineInstr
*
Copy
=
BuildMI
(
*
MI
.
getParent
(
)
,
MI
,
MI
.
getDebugLoc
(
)
,
get
(
TargetOpcode
::
COPY
)
)
.
addReg
(
NewSrc
,
RegState
::
Define
|
RegState
::
Undef
,
X86
::
sub_32bit
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
isKill
=
true
;
if
(
LV
)
LV
->
replaceKillInstruction
(
SrcReg
,
MI
,
*
Copy
)
;
if
(
LIS
)
{
SlotIndex
CopyIdx
=
LIS
->
InsertMachineInstrInMaps
(
*
Copy
)
;
SlotIndex
Idx
=
LIS
->
getInstructionIndex
(
MI
)
;
LiveInterval
&
LI
=
LIS
->
getInterval
(
SrcReg
)
;
LiveRange
::
Segment
*
S
=
LI
.
getSegmentContaining
(
Idx
)
;
if
(
S
->
end
.
getBaseIndex
(
)
==
Idx
)
S
->
end
=
CopyIdx
.
getRegSlot
(
)
;
}
}
return
true
;
}
</s>

Given an operand within a MachineInstr , insert preceding code to put it into the right format for a particular kind of LEA instruction .


<s> static inline int abi_default_cpu_arch ( struct loongarch_abi abi ) { switch ( abi . base ) { case ABI_BASE_LP64D : case ABI_BASE_LP64F : case ABI_BASE_LP64S : if ( abi . ext == ABI_EXT_BASE ) return CPU_LOONGARCH64 ; } gcc_unreachable ( ) ; } </s>

The behavior of this function should be consistent with config.gcc .


<s> bool R600TargetLowering :: canMergeStoresTo ( unsigned AS , EVT MemVT , const SelectionDAG & DAG ) const { if ( ( AS == AMDGPUAS :: LOCAL_ADDRESS || AS == AMDGPUAS :: PRIVATE_ADDRESS ) ) { return ( MemVT . getSizeInBits ( ) <= 32 ) ; } return true ; } </s>

Returns if it 's reasonable to merge stores to MemVT size .


<s> bool SystemZInstrInfo :: areMemAccessesTriviallyDisjoint ( MachineInstr & MIa , MachineInstr & MIb , AliasAnalysis * AA ) const { if ( ! MIa . hasOneMemOperand ( ) || ! MIb . hasOneMemOperand ( ) ) return false ; MachineMemOperand * MMOa = * MIa . memoperands_begin ( ) ; MachineMemOperand * MMOb = * MIb . memoperands_begin ( ) ; const Value * VALa = MMOa -> getValue ( ) ; const Value * VALb = MMOb -> getValue ( ) ; bool SameVal = ( VALa && VALb && ( VALa == VALb ) ) ; if ( ! SameVal ) { const PseudoSourceValue * PSVa = MMOa -> getPseudoValue ( ) ; const PseudoSourceValue * PSVb = MMOb -> getPseudoValue ( ) ; if ( PSVa && PSVb && ( PSVa == PSVb ) ) SameVal = true ; } if ( SameVal ) { int OffsetA = MMOa -> getOffset ( ) , OffsetB = MMOb -> getOffset ( ) ; int WidthA = MMOa -> getSize ( ) , WidthB = MMOb -> getSize ( ) ; int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB ; int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA ; int LowWidth = ( LowOffset == OffsetA ) ? WidthA : WidthB ; if ( LowOffset + LowWidth <= HighOffset ) return true ; } return false ; } </s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> static int arm_sched_variable_issue ( FILE * , int , rtx_insn * insn , int more ) { if ( DEBUG_INSN_P ( insn ) ) return more ; rtx_code code = GET_CODE ( PATTERN ( insn ) ) ; if ( code == USE || code == CLOBBER ) return more ; if ( get_attr_type ( insn ) == TYPE_NO_INSN ) return more ; return more - 1 ; } </s>


<s> static bool ix86_valid_mask_cmp_mode ( machine_mode mode ) { if ( TARGET_XOP && ! TARGET_AVX512F ) return false ; if ( TARGET_AVX512FP16 && mode == HFmode ) return true ; if ( ! ( TARGET_AVX512F && VECTOR_MODE_P ( mode ) ) ) return false ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; int vector_size = GET_MODE_SIZE ( mode ) ; if ( ( inner_mode == QImode || inner_mode == HImode ) && ! TARGET_AVX512BW ) return false ; return vector_size == 64 || TARGET_AVX512VL ; } </s>

Return true if MODE is valid for vector compare to mask register , Same result for conditionl vector move with mask register .


<s> const AMDGPULibFunc :: Param * AMDGPULibFunc :: getLeads ( ) const { return cast < const AMDGPUMangledLibFunc > ( Impl . get ( ) ) -> Leads ; } </s>

Get leading parameters for mangled lib functions .


<s> int addr24_operand ( rtx op , machine_mode mode ATTRIBUTE_UNUSED ) { rtx sym ; if ( flag_pic ) return 0 ; if ( GET_CODE ( op ) == LABEL_REF ) return TARGET_ADDR24 ; if ( GET_CODE ( op ) == SYMBOL_REF ) sym = op ; else if ( GET_CODE ( op ) == CONST && GET_CODE ( XEXP ( op , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( op , 0 ) , 0 ) ) == SYMBOL_REF && satisfies_constraint_M ( XEXP ( XEXP ( op , 0 ) , 1 ) ) ) sym = XEXP ( XEXP ( op , 0 ) , 0 ) ; else return 0 ; if ( SYMBOL_REF_MODEL ( sym ) == M32R_MODEL_SMALL ) return 1 ; if ( TARGET_ADDR24 && ( CONSTANT_POOL_ADDRESS_P ( sym ) || LIT_NAME_P ( XSTR ( sym , 0 ) ) ) ) return 1 ; return 0 ; } </s>

Return 1 if OP is a symbol that can use 24 bit addressing .


<s>
bool
M680x0InstrInfo
::
ExpandMOVEM
(
MachineInstrBuilder
&
MIB
,
const
MCInstrDesc
&
Desc
,
bool
isRM
)
const
{
int
Reg
=
0
,
Offset
=
0
,
Base
=
0
;
auto
XR32
=
RI
.
getRegClass
(
M680x0
::
XR32RegClassID
)
;
auto
DL
=
MIB
->
getDebugLoc
(
)
;
auto
MI
=
MIB
.
getInstr
(
)
;
auto
&
MBB
=
*
MIB
->
getParent
(
)
;
if
(
isRM
)
{
Reg
=
MIB
->
getOperand
(
0
)
.
getReg
(
)
;
Offset
=
MIB
->
getOperand
(
1
)
.
getImm
(
)
;
Base
=
MIB
->
getOperand
(
2
)
.
getReg
(
)
;
}
else
{
Offset
=
MIB
->
getOperand
(
0
)
.
getImm
(
)
;
Base
=
MIB
->
getOperand
(
1
)
.
getReg
(
)
;
Reg
=
MIB
->
getOperand
(
2
)
.
getReg
(
)
;
}
if
(
!
XR32
->
contains
(
Reg
)
)
{
Reg
=
RI
.
getMatchingMegaReg
(
Reg
,
XR32
)
;
assert
(
Reg
&&
"Has not meaningful MEGA register"
)
;
}
unsigned
Mask
=
1
<<
RI
.
getSpillRegisterOrder
(
Reg
)
;
if
(
isRM
)
{
BuildMI
(
MBB
,
MI
,
DL
,
Desc
)
.
addImm
(
Mask
)
.
addImm
(
Offset
)
.
addReg
(
Base
)
.
addReg
(
Reg
,
RegState
::
ImplicitDefine
)
.
copyImplicitOps
(
*
MIB
)
;
}
else
{
BuildMI
(
MBB
,
MI
,
DL
,
Desc
)
.
addImm
(
Offset
)
.
addReg
(
Base
)
.
addImm
(
Mask
)
.
addReg
(
Reg
,
RegState
::
Implicit
)
.
copyImplicitOps
(
*
MIB
)
;
}
MIB
->
eraseFromParent
(
)
;
return
true
;
}
</s>

Expand all MOVEM pseudos into real MOVEMs .


<s> bool aarch64_sve_float_arith_immediate_p ( rtx x , bool negate_p ) { rtx elt ; REAL_VALUE_TYPE r ; if ( ! const_vec_duplicate_p ( x , & elt ) || ! CONST_DOUBLE_P ( elt ) ) return false ; r = * CONST_DOUBLE_REAL_VALUE ( elt ) ; if ( negate_p ) r = real_value_negate ( & r ) ; if ( real_equal ( & r , & dconst1 ) ) return true ; if ( real_equal ( & r , & dconsthalf ) ) return true ; return false ; } </s>

Return true if X is a valid immediate operand for an SVE FADD or FSUB instruction . Negate X first if NEGATE_P is true .


<s> static bool abi_v4_pass_in_fpr ( machine_mode mode ) { if ( ! TARGET_FPRS || ! TARGET_HARD_FLOAT ) return false ; if ( TARGET_SINGLE_FLOAT && mode == SFmode ) return true ; if ( TARGET_DOUBLE_FLOAT && mode == DFmode ) return true ; if ( is_complex_IBM_long_double ( mode ) ) return false ; if ( FLOAT128_2REG_P ( mode ) ) return true ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) return true ; return false ; } </s>

Whether ABI_V4 passes MODE args to a function in floating point registers .


<s> const Cpu0MCExpr * Cpu0MCExpr :: create ( const MCSymbol * Symbol , Cpu0MCExpr :: Cpu0ExprKind Kind , MCContext & Ctx ) { const MCSymbolRefExpr * MCSym = MCSymbolRefExpr :: create ( Symbol , MCSymbolRefExpr :: VK_None , Ctx ) ; return new ( Ctx ) Cpu0MCExpr ( Kind , MCSym ) ; } </s>


<s> static void aarch64_init_rng_builtins ( void ) { tree unsigned_ptr_type = build_pointer_type ( unsigned_intDI_type_node ) ; tree ftype = build_function_type_list ( integer_type_node , unsigned_ptr_type , NULL ) ; aarch64_builtin_decls [ AARCH64_BUILTIN_RNG_RNDR ] = aarch64_general_add_builtin ( "__builtin_aarch64_rndr" , ftype , AARCH64_BUILTIN_RNG_RNDR ) ; aarch64_builtin_decls [ AARCH64_BUILTIN_RNG_RNDRRS ] = aarch64_general_add_builtin ( "__builtin_aarch64_rndrrs" , ftype , AARCH64_BUILTIN_RNG_RNDRRS ) ; } </s>

Add builtins for Random Number instructions .


<s> bool SystemZPassConfig :: addPreSched2 ( ) { if ( getSystemZTargetMachine ( ) . getSubtargetImpl ( ) -> hasLoadStoreOnCond ( ) ) addPass ( & IfConverterID ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> TargetLowering :: ConstraintWeight PPCTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; if ( StringRef ( constraint ) == "wc" && type -> isIntegerTy ( 1 ) ) return CW_Register ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'b' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; case 'd' : if ( type -> isDoubleTy ( ) ) weight = CW_Register ; break ; case 'v' : if ( type -> isVectorTy ( ) ) weight = CW_Register ; break ; case 'y' : weight = CW_Register ; break ; case 'Z' : weight = CW_Memory ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> void build ( function_builder & b , const function_group_info & group ) const override { auto_vec < tree > argument_types ; function_instance function_instance ( group . base_name , * group . base , * group . shape , group . ops_infos . types [ 0 ] , group . preds [ 0 ] , & group . ops_infos ) ; b . add_unique_function ( function_instance , ( * group . shape ) , long_unsigned_type_node , argument_types ) ; } </s>

Build new chain starting from insn INSN_UID recursively adding all dependent uses and definitions . Return true if OK , false if the chain discovery was aborted .


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , int64_t NumBytes , bool Is64Bit , const TargetInstrInfo & TII ) { bool isSub = NumBytes < 0 ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; unsigned Opc = isSub ? ( ( Offset < 128 ) ? ( Is64Bit ? X86 :: SUB64ri8 : X86 :: SUB32ri8 ) : ( Is64Bit ? X86 :: SUB64ri32 : X86 :: SUB32ri ) ) : ( ( Offset < 128 ) ? ( Is64Bit ? X86 :: ADD64ri8 : X86 :: ADD32ri8 ) : ( Is64Bit ? X86 :: ADD64ri32 : X86 :: ADD32ri ) ) ; uint64_t Chunk = ( 1LL << 31 ) - 1 ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( ThisVal ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> bool AMDGPUInstrInfo :: hasLoadFromStackSlot ( const MachineInstr * MI , const MachineMemOperand * & MMO , int & FrameIndex ) const { return false ; } </s>

If the specified machine instruction has a load from a stack slot , return true along with the FrameIndices of the loaded stack slot and the machine mem operands containing the reference .


<s> static bool loongarch_valid_lo_sum_p ( enum loongarch_symbol_type symbol_type , machine_mode mode , rtx x ) { int align , size ; if ( loongarch_symbol_insns ( symbol_type , mode ) == 0 ) return false ; if ( ! loongarch_split_symbol_type ( symbol_type ) ) return false ; if ( mode == BLKmode ) { rtx offset ; split_const ( x , & x , & offset ) ; if ( ! SYMBOL_REF_P ( x ) ) return false ; align = ( SYMBOL_REF_DECL ( x ) ? DECL_ALIGN ( SYMBOL_REF_DECL ( x ) ) : 1 ) ; size = ( SYMBOL_REF_DECL ( x ) && DECL_SIZE ( SYMBOL_REF_DECL ( x ) ) ? tree_to_uhwi ( DECL_SIZE ( SYMBOL_REF_DECL ( x ) ) ) : 2 * BITS_PER_WORD ) ; } else { align = GET_MODE_ALIGNMENT ( mode ) ; size = GET_MODE_BITSIZE ( mode ) ; } if ( size > BITS_PER_WORD && ( ! TARGET_STRICT_ALIGN || size > align ) ) return false ; return true ; } </s>

Return true if a LO_SUM can address a value of mode MODE when the LO_SUM symbol has type SYMBOL_TYPE .


<s> bool AMDGPUAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { const AMDGPUSubtarget & STM = TM . getSubtarget < AMDGPUSubtarget > ( ) ; if ( STM . dumpCode ( ) ) { MF . dump ( ) ; } SetupMachineFunction ( MF ) ; OutStreamer . SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; if ( STM . device ( ) -> getGeneration ( ) > AMDGPUDeviceInfo :: HD6XXX ) { EmitProgramInfo ( MF ) ; } EmitFunctionBody ( ) ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool matches_type_p ( const_tree model_type , const_tree candidate ) { if ( VECTOR_TYPE_P ( model_type ) ) { if ( ! VECTOR_TYPE_P ( candidate ) || maybe_ne ( TYPE_VECTOR_SUBPARTS ( model_type ) , TYPE_VECTOR_SUBPARTS ( candidate ) ) || TYPE_MODE ( model_type ) != TYPE_MODE ( candidate ) ) return false ; model_type = TREE_TYPE ( model_type ) ; candidate = TREE_TYPE ( candidate ) ; } return ( candidate != error_mark_node && TYPE_MAIN_VARIANT ( model_type ) == TYPE_MAIN_VARIANT ( candidate ) ) ; } </s>

Return true if CANDIDATE is equivalent to MODEL_TYPE for overloading purposes .


<s> static bool isF128SoftLibCall ( const char * CallSym ) { const char * const LibCalls [ ] = { "__addtf3" , "__divtf3" , "__eqtf2" , "__extenddftf2" , "__extendsftf2" , "__fixtfdi" , "__fixtfsi" , "__fixtfti" , "__fixunstfdi" , "__fixunstfsi" , "__fixunstfti" , "__floatditf" , "__floatsitf" , "__floattitf" , "__floatunditf" , "__floatunsitf" , "__floatuntitf" , "__getf2" , "__gttf2" , "__letf2" , "__lttf2" , "__multf3" , "__netf2" , "__powitf2" , "__subtf3" , "__trunctfdf2" , "__trunctfsf2" , "__unordtf2" , "ceill" , "copysignl" , "cosl" , "exp2l" , "expl" , "floorl" , "fmal" , "fmaxl" , "fmodl" , "log10l" , "log2l" , "logl" , "nearbyintl" , "powl" , "rintl" , "roundl" , "sinl" , "sqrtl" , "truncl" } ; auto Comp = [ ] ( const char * S1 , const char * S2 ) { return strcmp ( S1 , S2 ) < 0 ; } ; assert ( llvm :: is_sorted ( LibCalls , Comp ) ) ; return std :: binary_search ( std :: begin ( LibCalls ) , std :: end ( LibCalls ) , CallSym , Comp ) ; } </s>

This function returns true if CallSym is a long double emulation routine .


<s> bool SIRegisterInfo :: isFrameOffsetLegal ( const MachineInstr * MI , Register BaseReg , int64_t Offset ) const { if ( ! SIInstrInfo :: isMUBUF ( * MI ) ) return false ; int64_t NewOffset = Offset + getMUBUFInstrOffset ( MI ) ; return SIInstrInfo :: isLegalMUBUFImmOffset ( NewOffset ) ; } </s>

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s> Value * RISCVTargetLowering :: emitMaskedAtomicRMWIntrinsic ( IRBuilder < > & Builder , AtomicRMWInst * AI , Value * AlignedAddr , Value * Incr , Value * Mask , Value * ShiftAmt , AtomicOrdering Ord ) const { unsigned XLen = Subtarget . getXLen ( ) ; Value * Ordering = Builder . getIntN ( XLen , static_cast < uint64_t > ( AI -> getOrdering ( ) ) ) ; Type * Tys [ ] = { AlignedAddr -> getType ( ) } ; Function * LrwOpScwLoop = Intrinsic :: getDeclaration ( AI -> getModule ( ) , getIntrinsicForMaskedAtomicRMWBinOp ( XLen , AI -> getOperation ( ) ) , Tys ) ; if ( XLen == 64 ) { Incr = Builder . CreateSExt ( Incr , Builder . getInt64Ty ( ) ) ; Mask = Builder . CreateSExt ( Mask , Builder . getInt64Ty ( ) ) ; ShiftAmt = Builder . CreateSExt ( ShiftAmt , Builder . getInt64Ty ( ) ) ; } Value * Result ; if ( AI -> getOperation ( ) == AtomicRMWInst :: Min || AI -> getOperation ( ) == AtomicRMWInst :: Max ) { const DataLayout & DL = AI -> getModule ( ) -> getDataLayout ( ) ; unsigned ValWidth = DL . getTypeStoreSizeInBits ( AI -> getValOperand ( ) -> getType ( ) ) ; Value * SextShamt = Builder . CreateSub ( Builder . getIntN ( XLen , XLen - ValWidth ) , ShiftAmt ) ; Result = Builder . CreateCall ( LrwOpScwLoop , { AlignedAddr , Incr , Mask , SextShamt , Ordering } ) ; } else { Result = Builder . CreateCall ( LrwOpScwLoop , { AlignedAddr , Incr , Mask , Ordering } ) ; } if ( XLen == 64 ) Result = Builder . CreateTrunc ( Result , Builder . getInt32Ty ( ) ) ; return Result ; } </s>

Perform a masked atomicrmw using a target-specific intrinsic .


<s> int ix86_data_alignment ( tree type , int align , bool opt ) { int max_align_compat = MIN ( 256 , MAX_OFILE_ALIGNMENT ) ; int max_align = MIN ( ( unsigned ) ix86_tune_cost -> prefetch_block * 8 , MAX_OFILE_ALIGNMENT ) ; if ( max_align < BITS_PER_WORD ) max_align = BITS_PER_WORD ; switch ( ix86_align_data_type ) { case ix86_align_data_type_abi : opt = false ; break ; case ix86_align_data_type_compat : max_align = BITS_PER_WORD ; break ; case ix86_align_data_type_cacheline : break ; } if ( opt && AGGREGATE_TYPE_P ( type ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST ) { if ( wi :: geu_p ( TYPE_SIZE ( type ) , max_align_compat ) && align < max_align_compat ) align = max_align_compat ; if ( wi :: geu_p ( TYPE_SIZE ( type ) , max_align ) && align < max_align ) align = max_align ; } if ( TARGET_64BIT ) { if ( ( opt ? AGGREGATE_TYPE_P ( type ) : TREE_CODE ( type ) == ARRAY_TYPE ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && wi :: geu_p ( TYPE_SIZE ( type ) , 128 ) && align < 128 ) return 128 ; } if ( ! opt ) return align ; if ( TREE_CODE ( type ) == ARRAY_TYPE ) { if ( TYPE_MODE ( TREE_TYPE ( type ) ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( type ) ) ) && align < 128 ) return 128 ; } else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) { if ( TYPE_MODE ( type ) == DCmode && align < 64 ) return 64 ; if ( ( TYPE_MODE ( type ) == XCmode || TYPE_MODE ( type ) == TCmode ) && align < 128 ) return 128 ; } else if ( ( TREE_CODE ( type ) == RECORD_TYPE || TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == QUAL_UNION_TYPE ) && TYPE_FIELDS ( type ) ) { if ( DECL_MODE ( TYPE_FIELDS ( type ) ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( DECL_MODE ( TYPE_FIELDS ( type ) ) ) && align < 128 ) return 128 ; } else if ( TREE_CODE ( type ) == REAL_TYPE || TREE_CODE ( type ) == VECTOR_TYPE || TREE_CODE ( type ) == INTEGER_TYPE ) { if ( TYPE_MODE ( type ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( TYPE_MODE ( type ) ) && align < 128 ) return 128 ; } return align ; } </s>

Compute the alignment for a static variable . TYPE is the data type , and ALIGN is the alignment that the object would ordinarily have . The value of this function is used instead of that alignment to align the object .


<s> bool isReg ( ) const override { return Kind == OpKind_Reg ; } </s>


<s> int total_frame_size ( ) { unsigned int size = get_frame_size ( ) ; unsigned int outgoing_args_size = current_function_outgoing_args_size ; int i ; if ( optimize && ! current_function_needs_context && ! frame_pointer_needed ) { int inline_count , outline_count ; inline_count = 0 ; if ( regs_ever_live [ 5 ] ) inline_count += 2 ; if ( regs_ever_live [ 6 ] ) inline_count += 2 ; if ( regs_ever_live [ 2 ] ) inline_count += 3 ; if ( regs_ever_live [ 3 ] ) inline_count += 3 ; if ( size || outgoing_args_size || regs_ever_live [ 5 ] || regs_ever_live [ 6 ] || regs_ever_live [ 2 ] || regs_ever_live [ 3 ] ) inline_count += 2 ; inline_count = inline_count * 2 + 1 ; outline_count = 3 ; outline_count += ( outgoing_args_size == 0 ? 0 : 2 ) ; if ( get_frame_size ( ) != 0 ) outline_count += 2 ; outline_count = outline_count * 2 + 1 ; if ( get_frame_size ( ) == 0 && outgoing_args_size == 0 ) outline_count -= 1 ; if ( inline_count > outline_count ) return size + outgoing_args_size + 16 ; } for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { if ( ( regs_ever_live [ i ] && ! call_used_regs [ i ] && ! fixed_regs [ i ] ) || ( i == FRAME_POINTER_REGNUM && frame_pointer_needed ) ) size += 4 ; } return ( size + outgoing_args_size ) ; } </s>

Return the total size ( in bytes ) of the current function 's frame . This is the size of the register save area + the size of locals , spills , etc .


<s>
const
char
*
emit_fusion_gpr_load
(
rtx
target
,
rtx
mem
)
{
rtx
addis_value
;
rtx
addr
;
rtx
load_offset
;
const
char
*
load_str
=
;
machine_mode
mode
;
if
(
GET_CODE
(
mem
)
==
ZERO_EXTEND
)
mem
=
XEXP
(
mem
,
0
)
;
gcc_assert
(
REG_P
(
target
)
&&
MEM_P
(
mem
)
)
;
addr
=
XEXP
(
mem
,
0
)
;
fusion_split_address
(
addr
,
&
addis_value
,
&
load_offset
)
;
mode
=
GET_MODE
(
mem
)
;
switch
(
mode
)
{
case
E_QImode
:
load_str
=
"lbz"
;
break
;
case
E_HImode
:
load_str
=
"lhz"
;
break
;
case
E_SImode
:
case
E_SFmode
:
load_str
=
"lwz"
;
break
;
case
E_DImode
:
case
E_DFmode
:
gcc_assert
(
TARGET_POWERPC64
)
;
load_str
=
"ld"
;
break
;
default
:
fatal_insn
(
"Bad GPR fusion"
,
gen_rtx_SET
(
target
,
mem
)
)
;
}
emit_fusion_addis
(
target
,
addis_value
)
;
emit_fusion_load
(
target
,
target
,
load_offset
,
load_str
)
;
return
""
;
}
</s>

Return a string to fuse an addis instruction with a gpr load to the same register that we loaded up the addis instruction . The address that is used is the logical address that was formed during peephole2 : ( lo_sum ( high ) ( low-part ) ) The code is complicated , so we call output_asm_insn directly , and just return `` '' .

rs6000
0
0
"lbz"
"lhz"
"lwz"
"ld"
"Bad GPR fusion"
""


<s>
bool
processBlock
(
MachineBasicBlock
&
MBB
)
{
bool
Changed
=
false
;
bool
Is64Bit
=
TM
->
getSubtargetImpl
(
)
->
isPPC64
(
)
;
for
(
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
,
IE
=
MBB
.
end
(
)
;
I
!=
IE
;
++
I
)
{
MachineInstr
*
MI
=
I
;
if
(
MI
->
getOpcode
(
)
!=
PPC
::
GETtlsADDR
&&
MI
->
getOpcode
(
)
!=
PPC
::
GETtlsldADDR
&&
MI
->
getOpcode
(
)
!=
PPC
::
GETtlsADDR32
&&
MI
->
getOpcode
(
)
!=
PPC
::
GETtlsldADDR32
)
continue
;
DEBUG
(
dbgs
(
)
<<
"TLS Dynamic Call Fixup:\n    "
<<
*
MI
;
)
;
unsigned
OutReg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
unsigned
InReg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
DebugLoc
DL
=
MI
->
getDebugLoc
(
)
;
unsigned
GPR3
=
Is64Bit
PPC
::
X3
:
PPC
::
R3
;
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
TargetOpcode
::
COPY
)
,
GPR3
)
.
addReg
(
InReg
)
;
MI
->
getOperand
(
0
)
.
setReg
(
GPR3
)
;
MI
->
getOperand
(
1
)
.
setReg
(
GPR3
)
;
BuildMI
(
MBB
,
++
I
,
DL
,
TII
->
get
(
TargetOpcode
::
COPY
)
,
OutReg
)
.
addReg
(
GPR3
)
;
Changed
=
true
;
}
return
Changed
;
}
</s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s>
bool
AArch64InstrInfo
::
shouldClusterMemOps
(
MachineInstr
&
FirstLdSt
,
MachineInstr
&
SecondLdSt
,
unsigned
NumLoads
)
const
{
if
(
NumLoads
>
1
)
return
false
;
unsigned
FirstOpc
=
FirstLdSt
.
getOpcode
(
)
;
unsigned
SecondOpc
=
SecondLdSt
.
getOpcode
(
)
;
if
(
!
canPairLdStOpc
(
FirstOpc
,
SecondOpc
)
)
return
false
;
if
(
!
isCandidateToMergeOrPair
(
FirstLdSt
)
||
!
isCandidateToMergeOrPair
(
SecondLdSt
)
)
return
false
;
int64_t
Offset1
=
FirstLdSt
.
getOperand
(
2
)
.
getImm
(
)
;
if
(
isUnscaledLdSt
(
FirstOpc
)
&&
!
scaleOffset
(
FirstOpc
,
Offset1
)
)
return
false
;
int64_t
Offset2
=
SecondLdSt
.
getOperand
(
2
)
.
getImm
(
)
;
if
(
isUnscaledLdSt
(
SecondOpc
)
&&
!
scaleOffset
(
SecondOpc
,
Offset2
)
)
return
false
;
if
(
Offset1
>
63
||
Offset1
<
64
)
return
false
;
assert
(
Offset1
<=
Offset2
&&
"Caller should have ordered offsets."
)
;
return
Offset1
+
1
==
Offset2
;
}
</s>

Returns true if the two given memory operations should be scheduled adjacent .


<s> static rtx arm_trampoline_adjust_address ( rtx addr ) { if ( TARGET_THUMB ) addr = expand_simple_binop ( Pmode , IOR , addr , const1_rtx , NULL , 0 , OPTAB_LIB_WIDEN ) ; return addr ; } </s>

Thumb trampolines should be entered in thumb mode , so set the bottom bit of the address .


Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU R600 AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU


<s> void RISCVPassConfig :: addMachineSSAOptimization ( ) { TargetPassConfig :: addMachineSSAOptimization ( ) ; addPass ( createRISCVOptimizeVSETVLUsesPass ( ) ) ; } </s>

Methods with trivial inline returns are convenient points in the common codegen pass pipeline where targets may insert passes .


<s> static rtx tilepro_got_symbol ( void ) { if ( g_got_symbol == NULL ) g_got_symbol = gen_rtx_SYMBOL_REF ( Pmode , "_GLOBAL_OFFSET_TABLE_" ) ; return g_got_symbol ; } </s>

Return the SYMBOL_REF for _GLOBAL_OFFSET_TABLE_ .


<s>
virtual
const
char
*
getPassName
(
)
const
override
{
return
"ARM64 Store Pair Suppression"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> ConvergingVLIWScheduler :: CandResult ConvergingVLIWScheduler :: pickNodeFromQueue ( ReadyQueue & Q , const RegPressureTracker & RPTracker , SchedCandidate & Candidate ) { DEBUG ( Q . dump ( ) ) ; RegPressureTracker & TempTracker = const_cast < RegPressureTracker & > ( RPTracker ) ; CandResult FoundCandidate = NoCand ; for ( ReadyQueue :: iterator I = Q . begin ( ) , E = Q . end ( ) ; I != E ; ++ I ) { RegPressureDelta RPDelta ; TempTracker . getMaxPressureDelta ( ( * I ) -> getInstr ( ) , RPDelta , DAG -> getRegionCriticalPSets ( ) , DAG -> getRegPressure ( ) . MaxSetPressure ) ; int CurrentCost = SchedulingCost ( Q , * I , Candidate , RPDelta , false ) ; if ( ! Candidate . SU ) { Candidate . SU = * I ; Candidate . RPDelta = RPDelta ; Candidate . SCost = CurrentCost ; FoundCandidate = NodeOrder ; continue ; } if ( CurrentCost > Candidate . SCost ) { DEBUG ( traceCandidate ( "CCAND" , Q , * I ) ) ; Candidate . SU = * I ; Candidate . RPDelta = RPDelta ; Candidate . SCost = CurrentCost ; FoundCandidate = BestCost ; continue ; } if ( FoundCandidate == NoCand ) continue ; } return FoundCandidate ; } </s>

Pick the best candidate from the queue .


<s>
void
ScheduleDAGPostRA
::
releasePred
(
SUnit
*
SU
,
SDep
*
PredEdge
)
{
SUnit
*
PredSU
=
PredEdge
->
getSUnit
(
)
;
if
(
PredEdge
->
isWeak
(
)
)
{
PredSU
->
WeakSuccsLeft
;
return
;
}
if
(
PredSU
->
NumSuccsLeft
==
0
)
{
dbgs
(
)
<<
"*** Scheduling failed! ***\n"
;
PredSU
->
dumpAttributes
(
)
;
dbgs
(
)
<<
" has been released too many times!\n"
;
llvm_unreachable
(
0
)
;
}
PredSU
->
NumSuccsLeft
;
if
(
PredSU
->
NumSuccsLeft
==
0
&&
PredSU
!=
&
EntrySU
)
SchedImpl
->
releaseBottomNode
(
PredSU
)
;
}
</s>

ReleasePred - Decrement the NumSuccsLeft count of a predecessor .


<s> static bool pa_scalar_mode_supported_p ( machine_mode mode ) { int precision = GET_MODE_PRECISION ( mode ) ; switch ( GET_MODE_CLASS ( mode ) ) { case MODE_PARTIAL_INT : case MODE_INT : if ( precision == CHAR_TYPE_SIZE ) return true ; if ( precision == SHORT_TYPE_SIZE ) return true ; if ( precision == INT_TYPE_SIZE ) return true ; if ( precision == LONG_TYPE_SIZE ) return true ; if ( precision == LONG_LONG_TYPE_SIZE ) return true ; return false ; case MODE_FLOAT : if ( precision == FLOAT_TYPE_SIZE ) return true ; if ( precision == DOUBLE_TYPE_SIZE ) return true ; if ( precision == LONG_DOUBLE_TYPE_SIZE ) return true ; return false ; case MODE_DECIMAL_FLOAT : return false ; default : gcc_unreachable ( ) ; } } </s>

True if MODE is valid for the target . By `` valid '' , we mean able to be manipulated in non-trivial ways . In particular , this means all the arithmetic is supported .


<s> bool AMDGPUPromoteAlloca :: doInitialization ( Module & M ) { if ( ! TM ) return false ; Mod = & M ; DL = & Mod -> getDataLayout ( ) ; const Triple & TT = TM -> getTargetTriple ( ) ; IsAMDGCN = TT . getArch ( ) == Triple :: amdgcn ; IsAMDHSA = TT . getOS ( ) == Triple :: AMDHSA ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> bool Thumb1InstrInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( ARM :: tPUSH ) ) ; AddDefaultPred ( MIB ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; bool isKill = true ; if ( Reg == ARM :: LR ) { MachineFunction & MF = * MBB . getParent ( ) ; if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) && MF . getRegInfo ( ) . isLiveIn ( Reg ) ) isKill = false ; } if ( isKill ) MBB . addLiveIn ( Reg ) ; MIB . addReg ( Reg , getKillRegState ( isKill ) ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> bool X86TargetLowering :: isVectorClearMaskLegal ( const SmallVectorImpl < int > & Mask , EVT VT ) const { if ( ! VT . isSimple ( ) ) return false ; MVT SVT = VT . getSimpleVT ( ) ; unsigned NumElts = SVT . getVectorNumElements ( ) ; if ( NumElts == 2 ) return true ; if ( NumElts == 4 && SVT . is128BitVector ( ) ) { return ( isMOVLMask ( Mask , SVT ) || isCommutedMOVLMask ( Mask , SVT , true ) || isSHUFPMask ( Mask , SVT ) || isSHUFPMask ( Mask , SVT , true ) ) ; } return false ; } </s>


<s>
Nios2Subtarget
&
Nios2Subtarget
::
initializeSubtargetDependencies
(
StringRef
CPU
,
StringRef
FS
,
const
TargetMachine
&
TM
)
{
if
(
TargetTriple
.
getArch
(
)
==
Triple
::
nios2
)
{
if
(
CPU
!=
"nios2r2"
)
{
CPU
=
"nios2r1"
;
Nios2ArchVersion
=
Nios2r1
;
}
else
{
Nios2ArchVersion
=
Nios2r2
;
}
}
else
{
errs
(
)
<<
"!!!Error, TargetTriple.getArch() = "
<<
TargetTriple
.
getArch
(
)
<<
"CPU = "
<<
CPU
<<
"\n"
;
exit
(
0
)
;
}
ParseSubtargetFeatures
(
CPU
,
FS
)
;
return
*
this
;
}
</s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s>
SDValue
SparcTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
RETURNADDR
:
return
SDValue
(
)
;
case
ISD
::
FRAMEADDR
:
return
SDValue
(
)
;
case
ISD
::
GlobalTLSAddress
:
llvm_unreachable
(
"TLS not implemented for Sparc."
)
;
case
ISD
::
GlobalAddress
:
return
LowerGLOBALADDRESS
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerCONSTANTPOOL
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_SINT
(
Op
,
DAG
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerSINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
,
*
this
)
;
case
ISD
::
VAARG
:
return
LowerVAARG
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

Sparc
Sparc
"Should not custom lower this!"
ISD::RETURNADDR
ISD::FRAMEADDR
ISD::GlobalTLSAddress
"TLS not implemented for Sparc."
ISD::GlobalAddress
ISD::ConstantPool
ISD::FP_TO_SINT
ISD::SINT_TO_FP
ISD::BR_CC
ISD::SELECT_CC
ISD::VASTART
ISD::VAARG
ISD::DYNAMIC_STACKALLOC


<s> bool useAA ( ) const override { return isCortexA53 ( ) || isCortexA57 ( ) ; } </s>

Enable use of alias analysis during code generation ( during MI scheduling , DAGCombine , etc . ) .


<s> bool isToken ( ) const override { return Kind == Token ; } </s>


<s> static int rs6000_reassociation_width ( unsigned int opc ATTRIBUTE_UNUSED , enum machine_mode mode ) { switch ( rs6000_cpu ) { case PROCESSOR_POWER8 : case PROCESSOR_POWER9 : if ( DECIMAL_FLOAT_MODE_P ( mode ) ) return 1 ; if ( VECTOR_MODE_P ( mode ) ) return 4 ; if ( INTEGRAL_MODE_P ( mode ) ) return opc == MULT_EXPR ? 4 : 6 ; if ( FLOAT_MODE_P ( mode ) ) return 4 ; break ; default : break ; } return 1 ; } </s>

Determine the reassociation width to be used in reassociate_bb . This takes into account how many parallel operations we can actually do of a given type , and also the latency . P8 : int add/sub 6/cycle mul 2/cycle vect add/sub/mul 2/cycle fp add/sub/mul 2/cycle dfp 1/cycle


<s>
static
int
getMemScale
(
const
MachineInstr
&
MI
)
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Opcode has unknown scale!"
)
;
case
AArch64
::
LDRBBui
:
case
AArch64
::
LDURBBi
:
case
AArch64
::
LDRSBWui
:
case
AArch64
::
LDURSBWi
:
case
AArch64
::
STRBBui
:
case
AArch64
::
STURBBi
:
return
1
;
case
AArch64
::
LDRHHui
:
case
AArch64
::
LDURHHi
:
case
AArch64
::
LDRSHWui
:
case
AArch64
::
LDURSHWi
:
case
AArch64
::
STRHHui
:
case
AArch64
::
STURHHi
:
return
2
;
case
AArch64
::
LDRSui
:
case
AArch64
::
LDURSi
:
case
AArch64
::
LDRSWui
:
case
AArch64
::
LDURSWi
:
case
AArch64
::
LDRWui
:
case
AArch64
::
LDURWi
:
case
AArch64
::
STRSui
:
case
AArch64
::
STURSi
:
case
AArch64
::
STRWui
:
case
AArch64
::
STURWi
:
case
AArch64
::
LDPSi
:
case
AArch64
::
LDPSWi
:
case
AArch64
::
LDPWi
:
case
AArch64
::
STPSi
:
case
AArch64
::
STPWi
:
return
4
;
case
AArch64
::
LDRDui
:
case
AArch64
::
LDURDi
:
case
AArch64
::
LDRXui
:
case
AArch64
::
LDURXi
:
case
AArch64
::
STRDui
:
case
AArch64
::
STURDi
:
case
AArch64
::
STRXui
:
case
AArch64
::
STURXi
:
case
AArch64
::
LDPDi
:
case
AArch64
::
LDPXi
:
case
AArch64
::
STPDi
:
case
AArch64
::
STPXi
:
return
8
;
case
AArch64
::
LDRQui
:
case
AArch64
::
LDURQi
:
case
AArch64
::
STRQui
:
case
AArch64
::
STURQi
:
case
AArch64
::
LDPQi
:
case
AArch64
::
STPQi
:
case
AArch64
::
STGOffset
:
case
AArch64
::
STZGOffset
:
case
AArch64
::
ST2GOffset
:
case
AArch64
::
STZ2GOffset
:
case
AArch64
::
STGPi
:
return
16
;
}
}
</s>

Scaling factor for ( scaled or unscaled ) load or store .


<s> bool SparcAsmPrinter :: doFinalization ( Module & M ) { for ( Module :: const_global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ; I != E ; ++ I ) printModuleLevelGV ( I ) ; O << '\n' ; return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


Return an array that contains the bitmask target flag values and their names .


<s> void R600TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { switch ( N -> getOpcode ( ) ) { default : AMDGPUTargetLowering :: ReplaceNodeResults ( N , Results , DAG ) ; return ; case ISD :: FP_TO_UINT : if ( N -> getValueType ( 0 ) == MVT :: i1 ) { Results . push_back ( LowerFPTOUINT ( N -> getOperand ( 0 ) , DAG ) ) ; return ; } case ISD :: FP_TO_SINT : { SDValue Result ; if ( expandFP_TO_SINT ( N , Result , DAG ) ) Results . push_back ( Result ) ; return ; } case ISD :: SDIVREM : { SDValue Op = SDValue ( N , 1 ) ; SDValue RES = LowerSDIVREM ( Op , DAG ) ; Results . push_back ( RES ) ; Results . push_back ( RES . getValue ( 1 ) ) ; break ; } case ISD :: UDIVREM : { SDValue Op = SDValue ( N , 0 ) ; LowerUDIVREM64 ( Op , DAG , Results ) ; break ; } } } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> Optional < DestSourcePair > AArch64InstrInfo :: isCopyInstrImpl ( const MachineInstr & MI ) const { if ( MI . getOpcode ( ) == AArch64 :: ORRWrs && MI . getOperand ( 1 ) . getReg ( ) == AArch64 :: WZR && MI . getOperand ( 3 ) . getImm ( ) == 0x0 ) { return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 2 ) } ; } if ( MI . getOpcode ( ) == AArch64 :: ORRXrs && MI . getOperand ( 1 ) . getReg ( ) == AArch64 :: XZR && MI . getOperand ( 3 ) . getImm ( ) == 0x0 ) { return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 2 ) } ; } return None ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


<s> bool TOYPassConfig :: addPreRegAlloc ( ) { addPass ( createTOYPreRegAlloc ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s>
static
MCSymbol
*
GetSymbolFromOperand
(
const
MachineOperand
&
mo
,
AsmPrinter
&
ap
)
{
SmallString
<
128
>
name
;
const
TargetMachine
&
TM
=
ap
.
TM
;
Mangler
&
Mang
=
TM
.
getObjFileLowering
(
)
->
getMangler
(
)
;
if
(
mo
.
isGlobal
(
)
)
{
const
GlobalValue
*
gv
=
mo
.
getGlobal
(
)
;
TM
.
getNameWithPrefix
(
name
,
gv
,
Mang
)
;
}
else
{
assert
(
mo
.
isSymbol
(
)
&&
"Isn't a symbol reference"
)
;
Mangler
::
getNameWithPrefix
(
name
,
mo
.
getSymbolName
(
)
,
ap
.
getDataLayout
(
)
)
;
}
return
ap
.
OutContext
.
getOrCreateSymbol
(
name
)
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


"JIT relocation model must be set to static or default!"

runOnMachineFunction - Emit the function body .


<s> static rtx alpha_function_arg ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int basereg ; int num_args ; if ( type && AGGREGATE_TYPE_P ( type ) ) basereg = 16 ; else { gcc_assert ( ! COMPLEX_MODE_P ( mode ) ) ; if ( TARGET_FPREGS && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) basereg = 32 + 16 ; else basereg = 16 ; } { if ( mode == VOIDmode ) return alpha_arg_info_reg_val ( * cum ) ; num_args = cum -> num_args ; if ( num_args >= 6 || targetm . calls . must_pass_in_stack ( mode , type ) ) return NULL_RTX ; } { if ( * cum >= 6 ) return NULL_RTX ; num_args = * cum ; if ( type == void_type_node ) basereg = 16 ; else if ( targetm . calls . must_pass_in_stack ( mode , type ) ) return NULL_RTX ; } return gen_rtx_REG ( mode , num_args + basereg ) ; } </s>

Determine where to put an argument to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . On Alpha the first 6 words of args are normally in registers and the rest are pushed .


<s>
const
MCFixupKindInfo
&
Nios2AsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
Nios2
::
NumTargetFixupKinds
]
=
{
{
"fixup_Nios2_32"
,
0
,
32
,
0
}
,
{
"fixup_Nios2_HI16"
,
0
,
16
,
0
}
,
{
"fixup_Nios2_LO16"
,
0
,
16
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> void avr_init_expanders ( void ) { for ( int regno = 0 ; regno < 32 ; regno ++ ) all_regs_rtx [ regno ] = gen_rtx_REG ( QImode , regno ) ; lpm_reg_rtx = all_regs_rtx [ LPM_REGNO ] ; tmp_reg_rtx = all_regs_rtx [ AVR_TMP_REGNO ] ; zero_reg_rtx = all_regs_rtx [ AVR_ZERO_REGNO ] ; cc_reg_rtx = gen_rtx_REG ( CCmode , REG_CC ) ; lpm_addr_reg_rtx = gen_rtx_REG ( HImode , REG_Z ) ; sreg_rtx = gen_rtx_MEM ( QImode , GEN_INT ( avr_addr . sreg ) ) ; rampd_rtx = gen_rtx_MEM ( QImode , GEN_INT ( avr_addr . rampd ) ) ; rampx_rtx = gen_rtx_MEM ( QImode , GEN_INT ( avr_addr . rampx ) ) ; rampy_rtx = gen_rtx_MEM ( QImode , GEN_INT ( avr_addr . rampy ) ) ; rampz_rtx = gen_rtx_MEM ( QImode , GEN_INT ( avr_addr . rampz ) ) ; xstring_empty = gen_rtx_CONST_STRING ( VOIDmode , "" ) ; xstring_e = gen_rtx_CONST_STRING ( VOIDmode , "e" ) ; if ( AVR_TINY ) avr_have_dimode = false ; } </s>


<s> bool mips_epilogue_uses ( unsigned int regno ) { if ( regno == RETURN_ADDR_REGNUM ) return true ; if ( TARGET_USE_GOT && ( regno ) == GOT_VERSION_REGNUM ) return true ; if ( cfun -> machine -> interrupt_handler_p && mips_interrupt_extra_call_saved_reg_p ( regno ) ) return true ; return false ; } </s>


"Instr doesn't have FrameIndex operand!"

"Unconditionally using R28 for evil purposes Offset: "

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> ScheduleHazardRecognizer * SIInstrInfo :: CreateTargetPostRAHazardRecognizer ( const MachineFunction & MF ) const { return new GCNHazardRecognizer ( MF ) ; } </s>

Allocate and return a hazard recognizer to use for by non-scheduling passes .


<s> bool X86TargetLowering :: isExtractSubvectorCheap ( EVT ResVT , unsigned Index ) const { if ( ! isOperationLegalOrCustom ( ISD :: EXTRACT_SUBVECTOR , ResVT ) ) return false ; return ( Index == 0 || Index == ResVT . getVectorNumElements ( ) ) ; } </s>

Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index .


<s> void tilepro_expand_movmisalign ( machine_mode mode , rtx * operands ) { if ( MEM_P ( operands [ 1 ] ) ) { rtx tmp ; if ( register_operand ( operands [ 0 ] , mode ) ) tmp = operands [ 0 ] ; else tmp = gen_reg_rtx ( mode ) ; tilepro_expand_unaligned_load ( tmp , operands [ 1 ] , GET_MODE_BITSIZE ( mode ) , 0 , true ) ; if ( tmp != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , tmp ) ; } else if ( MEM_P ( operands [ 0 ] ) ) { if ( ! reg_or_0_operand ( operands [ 1 ] , mode ) ) operands [ 1 ] = force_reg ( mode , operands [ 1 ] ) ; tilepro_expand_unaligned_store ( operands [ 0 ] , operands [ 1 ] , GET_MODE_BITSIZE ( mode ) , 0 ) ; } else gcc_unreachable ( ) ; } </s>

Implement the movmisalign patterns . One of the operands is a memory that is not naturally aligned . Emit instructions to load it .


<s> bool isImm ( ) const override { return Kind == Immediate ; } </s>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ) { return false ; } const MCS51Subtarget & STI = MF . getSubtarget < MCS51Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; MachineBasicBlock & EntryMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = EntryMBB . begin ( ) ; DebugLoc DL = EntryMBB . findDebugLoc ( MBBI ) ; Register SPCopy = MF . getRegInfo ( ) . createVirtualRegister ( & MCS51 :: DREGSRegClass ) ; BuildMI ( EntryMBB , MBBI , DL , TII . get ( MCS51 :: COPY ) , SPCopy ) . addReg ( MCS51 :: SP ) ; for ( MachineBasicBlock & MBB : MF ) { if ( ! MBB . empty ( ) && MBB . back ( ) . isReturn ( ) ) { MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( MCS51 :: COPY ) , MCS51 :: SP ) . addReg ( SPCopy , RegState :: Kill ) ; } } return true ; } </s>


<s> bool AArch64InstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Cond , unsigned TrueReg , unsigned FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; unsigned ExtraCondLat = Cond . size ( ) != 1 ; if ( AArch64 :: GPR64allRegClass . hasSubClassEq ( RC ) || AArch64 :: GPR32allRegClass . hasSubClassEq ( RC ) ) { CondCycles = 1 + ExtraCondLat ; TrueCycles = FalseCycles = 1 ; if ( canFoldIntoCSel ( MRI , TrueReg ) ) TrueCycles = 0 ; else if ( canFoldIntoCSel ( MRI , FalseReg ) ) FalseCycles = 0 ; return true ; } if ( AArch64 :: FPR64RegClass . hasSubClassEq ( RC ) || AArch64 :: FPR32RegClass . hasSubClassEq ( RC ) ) { CondCycles = 5 + ExtraCondLat ; TrueCycles = FalseCycles = 2 ; return true ; } return false ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s>
void
rs6000_va_start
(
tree
valist
,
rtx
nextarg
)
{
HOST_WIDE_INT
words
,
n_gpr
,
n_fpr
;
tree
f_gpr
,
f_fpr
,
f_res
,
f_ovf
,
f_sav
;
tree
gpr
,
fpr
,
ovf
,
sav
,
t
;
if
(
DEFAULT_ABI
!=
ABI_V4
)
{
std_expand_builtin_va_start
(
valist
,
nextarg
)
;
return
;
}
f_gpr
=
TYPE_FIELDS
(
TREE_TYPE
(
va_list_type_node
)
)
;
f_fpr
=
TREE_CHAIN
(
f_gpr
)
;
f_res
=
TREE_CHAIN
(
f_fpr
)
;
f_ovf
=
TREE_CHAIN
(
f_res
)
;
f_sav
=
TREE_CHAIN
(
f_ovf
)
;
valist
=
build_va_arg_indirect_ref
(
valist
)
;
gpr
=
build
(
COMPONENT_REF
,
TREE_TYPE
(
f_gpr
)
,
valist
,
f_gpr
,
NULL_TREE
)
;
fpr
=
build
(
COMPONENT_REF
,
TREE_TYPE
(
f_fpr
)
,
valist
,
f_fpr
,
NULL_TREE
)
;
ovf
=
build
(
COMPONENT_REF
,
TREE_TYPE
(
f_ovf
)
,
valist
,
f_ovf
,
NULL_TREE
)
;
sav
=
build
(
COMPONENT_REF
,
TREE_TYPE
(
f_sav
)
,
valist
,
f_sav
,
NULL_TREE
)
;
words
=
current_function_args_info
.
words
;
n_gpr
=
MIN
(
current_function_args_info
.
sysv_gregno
GP_ARG_MIN_REG
,
GP_ARG_NUM_REG
)
;
n_fpr
=
MIN
(
current_function_args_info
.
fregno
FP_ARG_MIN_REG
,
FP_ARG_NUM_REG
)
;
if
(
TARGET_DEBUG_ARG
)
fprintf
(
stderr
,
"va_start: words = "
HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
HOST_WIDE_INT_PRINT_DEC
", n_fpr = "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
words
,
n_gpr
,
n_fpr
)
;
if
(
cfun
->
va_list_gpr_size
)
{
t
=
build
(
MODIFY_EXPR
,
TREE_TYPE
(
gpr
)
,
gpr
,
build_int_cst
(
NULL_TREE
,
n_gpr
)
)
;
TREE_SIDE_EFFECTS
(
t
)
=
1
;
expand_expr
(
t
,
const0_rtx
,
VOIDmode
,
EXPAND_NORMAL
)
;
}
if
(
cfun
->
va_list_fpr_size
)
{
t
=
build
(
MODIFY_EXPR
,
TREE_TYPE
(
fpr
)
,
fpr
,
build_int_cst
(
NULL_TREE
,
n_fpr
)
)
;
TREE_SIDE_EFFECTS
(
t
)
=
1
;
expand_expr
(
t
,
const0_rtx
,
VOIDmode
,
EXPAND_NORMAL
)
;
}
t
=
make_tree
(
TREE_TYPE
(
ovf
)
,
virtual_incoming_args_rtx
)
;
if
(
words
!=
0
)
t
=
build
(
PLUS_EXPR
,
TREE_TYPE
(
ovf
)
,
t
,
build_int_cst
(
NULL_TREE
,
words
*
UNITS_PER_WORD
)
)
;
t
=
build
(
MODIFY_EXPR
,
TREE_TYPE
(
ovf
)
,
ovf
,
t
)
;
TREE_SIDE_EFFECTS
(
t
)
=
1
;
expand_expr
(
t
,
const0_rtx
,
VOIDmode
,
EXPAND_NORMAL
)
;
if
(
!
cfun
->
va_list_gpr_size
&&
!
cfun
->
va_list_fpr_size
&&
n_gpr
<
GP_ARG_NUM_REG
&&
n_fpr
<
FP_ARG_V4_MAX_REG
)
return
;
t
=
make_tree
(
TREE_TYPE
(
sav
)
,
virtual_stack_vars_rtx
)
;
if
(
cfun
->
machine
->
varargs_save_offset
)
t
=
build
(
PLUS_EXPR
,
TREE_TYPE
(
sav
)
,
t
,
build_int_cst
(
NULL_TREE
,
cfun
->
machine
->
varargs_save_offset
)
)
;
t
=
build
(
MODIFY_EXPR
,
TREE_TYPE
(
sav
)
,
sav
,
t
)
;
TREE_SIDE_EFFECTS
(
t
)
=
1
;
expand_expr
(
t
,
const0_rtx
,
VOIDmode
,
EXPAND_NORMAL
)
;
}
</s>


<s> iterator begin ( ) { return ( Packet . begin ( ) ) ; } </s>


<s> static void aarch64_emit_binop ( rtx dest , optab binoptab , rtx op0 , rtx op1 ) { rtx tmp = expand_binop ( GET_MODE ( dest ) , binoptab , op0 , op1 , dest , 0 , OPTAB_DIRECT ) ; if ( dest != tmp ) emit_move_insn ( dest , tmp ) ; } </s>

Apply BINOPTAB to OP0 and OP1 and store the result in DEST .


<s> SDValue RISCVTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case RISCVISD :: SplitF64 : { SDValue Op0 = N -> getOperand ( 0 ) ; if ( Op0 -> getOpcode ( ) != RISCVISD :: BuildPairF64 ) break ; return DCI . CombineTo ( N , Op0 . getOperand ( 0 ) , Op0 . getOperand ( 1 ) ) ; } } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { TII = static_cast < const R600InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; for ( MachineFunction :: iterator BB = MF . begin ( ) , BB_E = MF . end ( ) ; BB != BB_E ; ++ BB ) { MachineBasicBlock & MBB = * BB ; MachineBasicBlock :: iterator I = MBB . begin ( ) ; if ( I -> getOpcode ( ) == AMDGPU :: CF_ALU ) continue ; for ( MachineBasicBlock :: iterator E = MBB . end ( ) ; I != E ; ) { if ( isALU ( I ) ) I = MakeALUClause ( MBB , I ) ; else ++ I ; } } return false ; } </s>


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == & ARM :: GPRRegClass || RC == & ARM :: tGPRRegClass || RC == & ARM :: tcGPRRegClass || RC == & ARM :: rGPRRegClass || RC == & ARM :: GPRnopcRegClass ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2LDRi12 ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } if ( ARM :: GPRPairRegClass . hasSubClassEq ( RC ) ) { if ( TargetRegisterInfo :: isVirtualRegister ( DestReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( DestReg , & ARM :: GPRPair_with_gsub_1_in_rGPRRegClass ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( ARM :: t2LDRDi8 ) ) ; AddDReg ( MIB , DestReg , ARM :: gsub_0 , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , ARM :: gsub_1 , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ; AddDefaultPred ( MIB ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; } ARMBaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC , TRI ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> static rtx nvptx_function_incoming_arg ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( arg . end_marker_p ( ) || ! arg . named ) return NULL_RTX ; return gen_rtx_UNSPEC ( arg . mode , gen_rtvec ( 1 , GEN_INT ( cum -> count ) ) , UNSPEC_ARG_REG ) ; } </s>


<s> void assignValueToAddress ( const CallLowering :: ArgInfo & Arg , Register Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { Register ValVReg = VA . getLocInfo ( ) != CCValAssign :: LocInfo :: FPExt ? extendRegister ( Arg . Regs [ 0 ] , VA ) : Arg . Regs [ 0 ] ; const LLT RegTy = MRI . getType ( ValVReg ) ; if ( RegTy . getSizeInBytes ( ) > Size ) Size = RegTy . getSizeInBytes ( ) ; assignValueToAddress ( ValVReg , Addr , Size , MPO , VA ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s>
SDValue
ARMTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom lower this!"
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
Subtarget
->
isTargetDarwin
(
)
LowerGlobalAddressDarwin
(
Op
,
DAG
)
:
LowerGlobalAddressELF
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
BR_JT
:
return
LowerBR_JT
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
,
VarArgsFrameIndex
)
;
case
ISD
::
MEMBARRIER
:
return
LowerMEMBARRIER
(
Op
,
DAG
,
Subtarget
)
;
case
ISD
::
SINT_TO_FP
:
case
ISD
::
UINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
)
;
case
ISD
::
FCOPYSIGN
:
return
LowerFCOPYSIGN
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
break
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
return
LowerGLOBAL_OFFSET_TABLE
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
,
Subtarget
)
;
case
ISD
::
BIT_CONVERT
:
return
ExpandBIT_CONVERT
(
Op
.
getNode
(
)
,
DAG
)
;
case
ISD
::
SHL
:
case
ISD
::
SRL
:
case
ISD
::
SRA
:
return
LowerShift
(
Op
.
getNode
(
)
,
DAG
,
Subtarget
)
;
case
ISD
::
SHL_PARTS
:
return
LowerShiftLeftParts
(
Op
,
DAG
)
;
case
ISD
::
SRL_PARTS
:
case
ISD
::
SRA_PARTS
:
return
LowerShiftRightParts
(
Op
,
DAG
)
;
case
ISD
::
CTTZ
:
return
LowerCTTZ
(
Op
.
getNode
(
)
,
DAG
,
Subtarget
)
;
case
ISD
::
VSETCC
:
return
LowerVSETCC
(
Op
,
DAG
)
;
case
ISD
::
BUILD_VECTOR
:
return
LowerBUILD_VECTOR
(
Op
,
DAG
)
;
case
ISD
::
VECTOR_SHUFFLE
:
return
LowerVECTOR_SHUFFLE
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_VECTOR_ELT
:
return
LowerEXTRACT_VECTOR_ELT
(
Op
,
DAG
)
;
case
ISD
::
CONCAT_VECTORS
:
return
LowerCONCAT_VECTORS
(
Op
,
DAG
)
;
}
return
SDValue
(
)
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> const TargetRegisterClass * X86RegisterInfo :: getMatchingSuperRegClass ( const TargetRegisterClass * A , const TargetRegisterClass * B , unsigned SubIdx ) const { if ( ! Is64Bit && SubIdx == X86 :: sub_8bit ) { A = X86GenRegisterInfo :: getSubClassWithSubReg ( A , X86 :: sub_8bit_hi ) ; if ( ! A ) return 0 ; } return X86GenRegisterInfo :: getMatchingSuperRegClass ( A , B , SubIdx ) ; } </s>

getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register in it has a sub-register of the specified sub-register index which is in the specified register class B .


<s> TargetLowering :: ConstraintWeight AArch64TargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'x' : case 'w' : if ( type -> isFloatingPointTy ( ) || type -> isVectorTy ( ) ) weight = CW_Register ; break ; case 'z' : weight = CW_Constant ; break ; case 'U' : if ( constraint [ 1 ] == 'p' && ( constraint [ 2 ] == 'l' || constraint [ 2 ] == 'a' ) ) weight = CW_Register ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s>
bool
runOnMachineFunction
(
MachineFunction
&
F
)
{
bool
Changed
=
false
;
DEBUG
(
dbgs
(
)
<<
"\n[DelaySlotFiller] "
<<
F
.
getFunction
(
)
->
getName
(
)
<<
"\n"
)
;
for
(
MachineFunction
::
iterator
FI
=
F
.
begin
(
)
,
FE
=
F
.
end
(
)
;
FI
!=
FE
;
++
FI
)
Changed
|=
fillDelaySlots
(
*
FI
)
;
for
(
MachineFunction
::
iterator
FI
=
F
.
begin
(
)
,
FE
=
F
.
end
(
)
;
FI
!=
FE
;
++
FI
)
Changed
|=
insertNOPs
(
*
FI
)
;
return
Changed
;
}
</s>


<s> const SystemZInstrInfo * getInstrInfo ( ) const override { return getSubtargetImpl ( ) -> getInstrInfo ( ) ; } </s>


<s> uint64_t SystemZInstrInfo :: getInstSizeInBytes ( const MachineInstr * MI ) const { if ( MI -> getOpcode ( ) == TargetOpcode :: INLINEASM ) { const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const char * AsmStr = MI -> getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } return MI -> getDesc ( ) . getSize ( ) ; } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> Register MipsRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const MipsSubtarget & Subtarget = MF . getSubtarget < MipsSubtarget > ( ) ; const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; bool IsN64 = static_cast < const MipsTargetMachine & > ( MF . getTarget ( ) ) . getABI ( ) . IsN64 ( ) ; if ( Subtarget . inMips16Mode ( ) ) return TFI -> hasFP ( MF ) ? Mips :: S0 : Mips :: SP ; else return TFI -> hasFP ( MF ) ? ( IsN64 ? Mips :: FP_64 : Mips :: FP ) : ( IsN64 ? Mips :: SP_64 : Mips :: SP ) ; } </s>

Mips Mips Mips Mips Mips Mips Mips::S0 Mips::SP Mips::FP_64 Mips::FP Mips::SP_64 Mips::SP


<s> bool PPCRegisterInfo :: isCallerPreservedPhysReg ( unsigned PhysReg , const MachineFunction & MF ) const { assert ( TargetRegisterInfo :: isPhysicalRegister ( PhysReg ) ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! TM . isPPC64 ( ) ) return false ; if ( ! Subtarget . isSVR4ABI ( ) ) return false ; if ( PhysReg == PPC :: X2 ) return ( getReservedRegs ( MF ) . test ( PPC :: X2 ) ) ; if ( StackPtrConst && ( PhysReg == PPC :: X1 ) && ! MFI . hasVarSizedObjects ( ) && ! MFI . hasOpaqueSPAdjustment ( ) ) return true ; return false ; } </s>

Physical registers that may be modified within a function but are guaranteed to be restored before any uses .


<s> bool lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) const { return LowerRISCVMachineOperandToMCOperand ( MO , MCOp , * this ) ; } </s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> const MCRegisterInfo * getRegInfo ( ) const { return RegInfo ; } </s>

getRegInfo - Return information about the registers currently in use .


<s> enum reg_class mcore_reload_class ( rtx x , enum reg_class rclass ) { if ( reg_class_subset_p ( LRW_REGS , rclass ) && ! mcore_r15_operand_p ( x ) ) return LRW_REGS ; return rclass ; } </s>

Return the reg_class to use when reloading the rtx X into the class CLASS . If X is too complex to move directly into r15 , prefer to use LRW_REGS instead .


<s> bool dominates ( const Waitcnt & Other ) const { return VmCnt <= Other . VmCnt && ExpCnt <= Other . ExpCnt && LgkmCnt <= Other . LgkmCnt && VsCnt <= Other . VsCnt ; } </s>

Returns true if B1 occurs before B2 in the trace , or if it is the same block as B2 .


<s> void mips_expand_vector_init ( rtx target , rtx vals ) { machine_mode vmode = GET_MODE ( target ) ; machine_mode imode = GET_MODE_INNER ( vmode ) ; unsigned i , nelt = GET_MODE_NUNITS ( vmode ) ; unsigned nvar = 0 , one_var = - 1u ; bool all_same = true ; rtx x ; for ( i = 0 ; i < nelt ; ++ i ) { x = XVECEXP ( vals , 0 , i ) ; if ( ! mips_constant_elt_p ( x ) ) nvar ++ , one_var = i ; if ( i > 0 && ! rtx_equal_p ( x , XVECEXP ( vals , 0 , 0 ) ) ) all_same = false ; } if ( nvar == 0 ) { emit_move_insn ( target , gen_rtx_CONST_VECTOR ( vmode , XVEC ( vals , 0 ) ) ) ; return ; } if ( nelt == 2 ) { rtx op0 = force_reg ( imode , XVECEXP ( vals , 0 , 0 ) ) ; rtx op1 = force_reg ( imode , XVECEXP ( vals , 0 , 1 ) ) ; x = gen_rtx_VEC_CONCAT ( vmode , op0 , op1 ) ; emit_insn ( gen_rtx_SET ( target , x ) ) ; return ; } gcc_assert ( TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS ) ; if ( all_same ) { mips_expand_vi_broadcast ( vmode , target , XVECEXP ( vals , 0 , 0 ) ) ; return ; } if ( nvar == 1 && vmode == V4HImode ) { mips_expand_vi_loongson_one_pinsrh ( target , vals , one_var ) ; return ; } mips_expand_vi_general ( vmode , imode , nelt , nvar , target , vals ) ; } </s>


<s> const TargetRegisterClass * TPCRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & TPC :: SRFRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


"Peephole: call to builtin function with "

runOnMachineFunction - Emit the function body .


<s> bool AMDGPUSubtarget :: makeLIDRangeMetadata ( Instruction * I ) const { Function * Kernel = I -> getParent ( ) -> getParent ( ) ; unsigned MinSize = 0 ; unsigned MaxSize = getFlatWorkGroupSizes ( * Kernel ) . second ; bool IdQuery = false ; if ( auto * CI = dyn_cast < CallInst > ( I ) ) { const Function * F = CI -> getCalledFunction ( ) ; if ( F ) { unsigned Dim = UINT_MAX ; switch ( F -> getIntrinsicID ( ) ) { case Intrinsic :: amdgcn_workitem_id_x : case Intrinsic :: r600_read_tidig_x : IdQuery = true ; LLVM_FALLTHROUGH ; case Intrinsic :: r600_read_local_size_x : Dim = 0 ; break ; case Intrinsic :: amdgcn_workitem_id_y : case Intrinsic :: r600_read_tidig_y : IdQuery = true ; LLVM_FALLTHROUGH ; case Intrinsic :: r600_read_local_size_y : Dim = 1 ; break ; case Intrinsic :: amdgcn_workitem_id_z : case Intrinsic :: r600_read_tidig_z : IdQuery = true ; LLVM_FALLTHROUGH ; case Intrinsic :: r600_read_local_size_z : Dim = 2 ; break ; default : break ; } if ( Dim <= 3 ) { if ( auto Node = Kernel -> getMetadata ( "reqd_work_group_size" ) ) if ( Node -> getNumOperands ( ) == 3 ) MinSize = MaxSize = mdconst :: extract < ConstantInt > ( Node -> getOperand ( Dim ) ) -> getZExtValue ( ) ; } } } if ( ! MaxSize ) return false ; if ( IdQuery ) MinSize = 0 ; else ++ MaxSize ; MDBuilder MDB ( I -> getContext ( ) ) ; MDNode * MaxWorkGroupSizeRange = MDB . createRange ( APInt ( 32 , MinSize ) , APInt ( 32 , MaxSize ) ) ; I -> setMetadata ( LLVMContext :: MD_range , MaxWorkGroupSizeRange ) ; return true ; } </s>

Creates value range metadata on an workitemid . * intrinsic call or load .


<s> void GCNMaxOccupancySchedStrategy :: pickNodeFromQueue ( SchedBoundary & Zone , const CandPolicy & ZonePolicy , const RegPressureTracker & RPTracker , SchedCandidate & Cand ) { const SIRegisterInfo * SRI = static_cast < const SIRegisterInfo * > ( TRI ) ; ArrayRef < unsigned > Pressure = RPTracker . getRegSetPressureAtPos ( ) ; unsigned SGPRPressure = Pressure [ AMDGPU :: RegisterPressureSets :: SReg_32 ] ; unsigned VGPRPressure = Pressure [ AMDGPU :: RegisterPressureSets :: VGPR_32 ] ; ReadyQueue & Q = Zone . Available ; for ( SUnit * SU : Q ) { SchedCandidate TryCand ( ZonePolicy ) ; initCandidate ( TryCand , SU , Zone . isTop ( ) , RPTracker , SRI , SGPRPressure , VGPRPressure ) ; SchedBoundary * ZoneArg = Cand . AtTop == TryCand . AtTop ? & Zone : nullptr ; GenericScheduler :: tryCandidate ( Cand , TryCand , ZoneArg ) ; if ( TryCand . Reason != NoCand ) { if ( TryCand . ResDelta == SchedResourceDelta ( ) ) TryCand . initResourceDelta ( Zone . DAG , SchedModel ) ; Cand . setBest ( TryCand ) ; LLVM_DEBUG ( traceCandidate ( Cand ) ) ; } } } </s>

Pick the best candidate from the queue .

AMDGPU SI SI AMDGPU::RegisterPressureSets AMDGPU::RegisterPressureSets


<s> bool X86FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; unsigned SlotSize = STI . is64Bit ( ) ? 8 : 4 ; unsigned FPReg = TRI -> getFrameRegister ( MF ) ; unsigned CalleeFrameSize = 0 ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned Opc = STI . is64Bit ( ) ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; if ( Reg == FPReg ) continue ; CalleeFrameSize += SlotSize ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } X86FI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - 1 ] . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> bool RISCVCoreVHwlpBlocks :: runOnMachineFunction ( MachineFunction & MF ) { if ( ! MF . getSubtarget < RISCVSubtarget > ( ) . hasExtXCoreVHwlp ( ) ) { return false ; } MachineLoopInfo & MLI = getAnalysis < MachineLoopInfo > ( ) ; bool Changed = false ; for ( auto & ML : MLI ) { Changed |= ProcessLoop ( ML , MF ) ; } return Changed ; } </s>


<s> void aarch64_expand_prologue ( void ) { aarch64_layout_frame ( ) ; poly_int64 frame_size = cfun -> machine -> frame . frame_size ; poly_int64 initial_adjust = cfun -> machine -> frame . initial_adjust ; HOST_WIDE_INT callee_adjust = cfun -> machine -> frame . callee_adjust ; poly_int64 final_adjust = cfun -> machine -> frame . final_adjust ; poly_int64 callee_offset = cfun -> machine -> frame . callee_offset ; unsigned reg1 = cfun -> machine -> frame . wb_candidate1 ; unsigned reg2 = cfun -> machine -> frame . wb_candidate2 ; bool emit_frame_chain = cfun -> machine -> frame . emit_frame_chain ; rtx_insn * insn ; if ( aarch64_return_address_signing_enabled ( ) ) { insn = emit_insn ( gen_pacisp ( ) ) ; add_reg_note ( insn , REG_CFA_TOGGLE_RA_MANGLE , const0_rtx ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } if ( flag_stack_usage_info ) current_function_static_stack_size = constant_lower_bound ( frame_size ) ; if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK ) { if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { if ( maybe_gt ( frame_size , PROBE_INTERVAL ) && maybe_gt ( frame_size , get_stack_check_protect ( ) ) ) aarch64_emit_probe_stack_range ( get_stack_check_protect ( ) , ( frame_size - get_stack_check_protect ( ) ) ) ; } else if ( maybe_gt ( frame_size , 0 ) ) aarch64_emit_probe_stack_range ( get_stack_check_protect ( ) , frame_size ) ; } rtx ip0_rtx = gen_rtx_REG ( Pmode , IP0_REGNUM ) ; rtx ip1_rtx = gen_rtx_REG ( Pmode , IP1_REGNUM ) ; aarch64_sub_sp ( ip0_rtx , ip1_rtx , initial_adjust , true ) ; if ( callee_adjust != 0 ) aarch64_push_regs ( reg1 , reg2 , callee_adjust ) ; if ( emit_frame_chain ) { poly_int64 reg_offset = callee_adjust ; if ( callee_adjust == 0 ) { reg1 = R29_REGNUM ; reg2 = R30_REGNUM ; reg_offset = callee_offset ; aarch64_save_callee_saves ( DImode , reg_offset , reg1 , reg2 , false ) ; } aarch64_add_offset ( Pmode , hard_frame_pointer_rtx , stack_pointer_rtx , callee_offset , ip1_rtx , ip0_rtx , frame_pointer_needed ) ; if ( frame_pointer_needed && ! frame_size . is_constant ( ) ) { rtx_insn * insn = get_last_insn ( ) ; gcc_assert ( RTX_FRAME_RELATED_P ( insn ) ) ; if ( ! find_reg_note ( insn , REG_CFA_ADJUST_CFA , NULL_RTX ) ) { rtx src = plus_constant ( Pmode , stack_pointer_rtx , callee_offset ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( hard_frame_pointer_rtx , src ) ) ; } reg_offset -= callee_offset ; aarch64_add_cfa_expression ( insn , reg2 , hard_frame_pointer_rtx , reg_offset + UNITS_PER_WORD ) ; aarch64_add_cfa_expression ( insn , reg1 , hard_frame_pointer_rtx , reg_offset ) ; } emit_insn ( gen_stack_tie ( stack_pointer_rtx , hard_frame_pointer_rtx ) ) ; } aarch64_save_callee_saves ( DImode , callee_offset , R0_REGNUM , R30_REGNUM , callee_adjust != 0 || emit_frame_chain ) ; aarch64_save_callee_saves ( DFmode , callee_offset , V0_REGNUM , V31_REGNUM , callee_adjust != 0 || emit_frame_chain ) ; aarch64_sub_sp ( ip1_rtx , ip0_rtx , final_adjust , ! frame_pointer_needed ) ; } </s>

Generate the prologue instructions for entry into a function . Establish the stack frame by decreasing the stack pointer with a properly calculated size and , if necessary , create a frame record filled with the values of LR and previous frame pointer . The current FP is also set up if it is in use .


<s> bool isTargetEHABICompatible ( ) const { return ( TargetTriple . getEnvironment ( ) == Triple :: EABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: EABIHF || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: Android ) && ! isTargetDarwin ( ) && ! isTargetWindows ( ) ; } </s>

Tests whether the target supports the EHABI exception handling standard .


<s> void CSKYFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> unsigned getBranchTargetOpValue ( const MachineInstr & MI , unsigned Op ) const { return 0 ; } </s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s> static std :: unique_ptr < ARMOperand > CreateMem ( unsigned BaseRegNum , const MCExpr * OffsetImm , unsigned OffsetRegNum , ARM_AM :: ShiftOpc ShiftType , unsigned ShiftImm , unsigned Alignment , bool isNegative , SMLoc S , SMLoc E , SMLoc AlignmentLoc = SMLoc ( ) ) { auto Op = std :: make_unique < ARMOperand > ( k_Memory ) ; Op -> Memory . BaseRegNum = BaseRegNum ; Op -> Memory . OffsetImm = OffsetImm ; Op -> Memory . OffsetRegNum = OffsetRegNum ; Op -> Memory . ShiftType = ShiftType ; Op -> Memory . ShiftImm = ShiftImm ; Op -> Memory . Alignment = Alignment ; Op -> Memory . isNegative = isNegative ; Op -> StartLoc = S ; Op -> EndLoc = E ; Op -> AlignmentLoc = AlignmentLoc ; return Op ; } </s>


<s> bool AMDGPUTargetLowering :: isFNegFree ( EVT VT ) const { return isFAbsFree ( VT ) ; } </s>

Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation .


"SIC DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> bool SILowerControlFlowPass :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const SIInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; TRI = static_cast < const SIRegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; bool HaveKill = false ; bool NeedM0 = false ; bool NeedWQM = false ; unsigned Depth = 0 ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ; MachineBasicBlock :: iterator I , Next ; for ( I = MBB . begin ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; if ( TII -> isDS ( MI . getOpcode ( ) ) ) { NeedM0 = true ; NeedWQM = true ; } switch ( MI . getOpcode ( ) ) { default : break ; case AMDGPU :: SI_IF : ++ Depth ; If ( MI ) ; break ; case AMDGPU :: SI_ELSE : Else ( MI ) ; break ; case AMDGPU :: SI_BREAK : Break ( MI ) ; break ; case AMDGPU :: SI_IF_BREAK : IfBreak ( MI ) ; break ; case AMDGPU :: SI_ELSE_BREAK : ElseBreak ( MI ) ; break ; case AMDGPU :: SI_LOOP : ++ Depth ; Loop ( MI ) ; break ; case AMDGPU :: SI_END_CF : if ( -- Depth == 0 && HaveKill ) { SkipIfDead ( MI ) ; HaveKill = false ; } EndCf ( MI ) ; break ; case AMDGPU :: SI_KILL : if ( Depth == 0 ) SkipIfDead ( MI ) ; else HaveKill = true ; Kill ( MI ) ; break ; case AMDGPU :: S_BRANCH : Branch ( MI ) ; break ; case AMDGPU :: SI_INDIRECT_SRC : IndirectSrc ( MI ) ; break ; case AMDGPU :: SI_INDIRECT_DST_V1 : case AMDGPU :: SI_INDIRECT_DST_V2 : case AMDGPU :: SI_INDIRECT_DST_V4 : case AMDGPU :: SI_INDIRECT_DST_V8 : case AMDGPU :: SI_INDIRECT_DST_V16 : IndirectDst ( MI ) ; break ; case AMDGPU :: V_INTERP_P1_F32 : case AMDGPU :: V_INTERP_P2_F32 : case AMDGPU :: V_INTERP_MOV_F32 : NeedWQM = true ; break ; } } } if ( NeedM0 ) { MachineBasicBlock & MBB = MF . front ( ) ; InitM0ForLDS ( MBB . getFirstNonPHI ( ) ) ; } if ( NeedWQM && MFI -> getShaderType ( ) == ShaderType :: PIXEL ) { MachineBasicBlock & MBB = MF . front ( ) ; BuildMI ( MBB , MBB . getFirstNonPHI ( ) , DebugLoc ( ) , TII -> get ( AMDGPU :: S_WQM_B64 ) , AMDGPU :: EXEC ) . addReg ( AMDGPU :: EXEC ) ; } return true ; } </s>

R600 SI SI SI SI SI 0 SI SI SI SI SI SI SI 0 SI 0 SI SI SI SI SI SI


<s> static bool microblaze_gen_pic_addr_dif_vec ( void ) { return ( flag_pic && ! TARGET_PIC_DATA_TEXT_REL ) ; } </s>

We need to disable address diff vectors incase of pic data text relative mode .


<s> void TOYFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const TOYInstrInfo & TII = * static_cast < const TOYInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; int StackSize = ( int ) MFI -> getStackSize ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TOY :: SUBri ) , TOY :: SP ) . addReg ( TOY :: SP ) . addImm ( StackSize ) ; } </s>

TOY TOY TOY TOY TOY::SUBri TOY::SP TOY::SP


<s> bool WebAssemblyTargetLowering :: shouldScalarizeBinop ( SDValue VecOp ) const { unsigned Opc = VecOp . getOpcode ( ) ; if ( Opc >= ISD :: BUILTIN_OP_END ) return false ; EVT VecVT = VecOp . getValueType ( ) ; if ( ! isOperationLegalOrCustomOrPromote ( Opc , VecVT ) ) return true ; EVT ScalarVT = VecVT . getScalarType ( ) ; return isOperationLegalOrCustomOrPromote ( Opc , ScalarVT ) ; } </s>

Scalar ops always have equal or better analysis/performance/power than the vector equivalent , so this always makes sense if the scalar op is supported .