<s> void XCoreFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; XCoreFunctionInfo * XFI = MF . getInfo < XCoreFunctionInfo > ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool LRUsed = MRI . isPhysRegModified ( XCore :: LR ) ; if ( ! LRUsed && ! MF . getFunction ( ) -> isVarArg ( ) && MF . getFrameInfo ( ) . estimateStackSize ( MF ) ) LRUsed = true ; if ( MF . getMMI ( ) . callsUnwindInit ( ) || MF . getMMI ( ) . callsEHReturn ( ) ) { XFI -> createEHSpillSlot ( MF ) ; LRUsed = true ; } if ( LRUsed ) { SavedRegs . reset ( XCore :: LR ) ; XFI -> createLRSpillSlot ( MF ) ; } if ( hasFP ( MF ) ) XFI -> createFPSpillSlot ( MF ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .

XCore XCore XCore XCore XCore::LR XCore::LR


<s> static void pru_set_current_function ( tree fndecl ) { tree old_tree = ( pru_previous_fndecl ? DECL_FUNCTION_SPECIFIC_TARGET ( pru_previous_fndecl ) : NULL_TREE ) ; tree new_tree = ( fndecl ? DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) : NULL_TREE ) ; if ( fndecl && fndecl != pru_previous_fndecl ) { pru_previous_fndecl = fndecl ; if ( old_tree == new_tree ) ; else if ( new_tree ) { cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( new_tree ) ) ; target_reinit ( ) ; } else if ( old_tree ) { struct cl_target_option * def = TREE_TARGET_OPTION ( target_option_current_node ) ; cl_target_option_restore ( & global_options , & global_options_set , def ) ; target_reinit ( ) ; } } } </s>

Establish appropriate back-end context for processing the function FNDECL . The argument might be NULL to indicate processing at top level , outside of any function scope .


"********** AArch64 Conditional Compares **********\n"

runOnMachineFunction - Emit the function body .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addRequired < ScalarEvolutionWrapperPass > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const X86RegisterInfo & RegInfo = * static_cast < const X86RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; unsigned StackPtr = RegInfo . getStackRegister ( ) ; bool reserveCallFrame = hasReservedCallFrame ( MF ) ; int Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; const X86Subtarget & STI = MF . getTarget ( ) . getSubtarget < X86Subtarget > ( ) ; bool IsLP64 = STI . isTarget64BitLP64 ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t CalleeAmt = isDestroy ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { if ( Amount == 0 ) return ; unsigned StackAlign = MF . getTarget ( ) . getSubtargetImpl ( ) -> getFrameLowering ( ) -> getStackAlignment ( ) ; Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = nullptr ; if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { if ( ! IsLP64 && convertArgMovsToPushes ( MF , MBB , I , Amount ) ) return ; New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( IsLP64 , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; Amount -= CalleeAmt ; if ( Amount ) { unsigned Opc = getADDriOpcode ( IsLP64 , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } return ; } if ( Opcode == TII . getCallFrameDestroyOpcode ( ) && CalleeAmt ) { unsigned Opc = getSUBriOpcode ( IsLP64 , CalleeAmt ) ; MachineInstr * New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! std :: prev ( I ) -> isCall ( ) ) -- I ; MBB . insert ( I , New ) ; } } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> unsigned int visium_data_alignment ( tree type , unsigned int align ) { if ( AGGREGATE_TYPE_P ( type ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && align < 32 ) { if ( TREE_INT_CST_LOW ( TYPE_SIZE ( type ) ) >= 32 ) return 32 ; if ( TREE_INT_CST_LOW ( TYPE_SIZE ( type ) ) >= 16 && align < 16 ) return 16 ; } return align ; } </s>

Compute the alignment for a variable . The alignment of an aggregate is set to be at least that of a scalar less than or equal to it in size .


<s> MachineInstr * SystemZInstrInfo :: convertToThreeAddress ( MachineInstr & MI , LiveVariables * LV , LiveIntervals * LIS ) const { MachineBasicBlock * MBB = MI . getParent ( ) ; if ( LogicOp And = interpretAndImmediate ( MI . getOpcode ( ) ) ) { uint64_t Imm = MI . getOperand ( 2 ) . getImm ( ) << And . ImmLSB ; Imm |= allOnes ( And . RegSize ) & ~ ( allOnes ( And . ImmSize ) << And . ImmLSB ) ; unsigned Start , End ; if ( isRxSBGMask ( Imm , And . RegSize , Start , End ) ) { unsigned NewOpcode ; if ( And . RegSize == 64 ) { NewOpcode = SystemZ :: RISBG ; if ( STI . hasMiscellaneousExtensions ( ) ) NewOpcode = SystemZ :: RISBGN ; } else { NewOpcode = SystemZ :: RISBMux ; Start &= 31 ; End &= 31 ; } MachineOperand & Dest = MI . getOperand ( 0 ) ; MachineOperand & Src = MI . getOperand ( 1 ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( NewOpcode ) ) . add ( Dest ) . addReg ( 0 ) . addReg ( Src . getReg ( ) , getKillRegState ( Src . isKill ( ) ) , Src . getSubReg ( ) ) . addImm ( Start ) . addImm ( End + 128 ) . addImm ( 0 ) ; if ( LV ) { unsigned NumOps = MI . getNumOperands ( ) ; for ( unsigned I = 1 ; I < NumOps ; ++ I ) { MachineOperand & Op = MI . getOperand ( I ) ; if ( Op . isReg ( ) && Op . isKill ( ) ) LV -> replaceKillInstruction ( Op . getReg ( ) , MI , * MIB ) ; } } if ( LIS ) LIS -> ReplaceMachineInstrInMaps ( MI , * MIB ) ; transferDeadCC ( & MI , MIB ) ; return MIB ; } } return nullptr ; } </s>

convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag .


<s>
SDValue
MSP430TargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
if
(
CallConv
==
CallingConv
::
MSP430_INTR
&&
!
Outs
.
empty
(
)
)
report_fatal_error
(
"ISRs cannot return any value"
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
AnalyzeReturnValues
(
CCInfo
,
RVLocs
,
Outs
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
unsigned
Opc
=
(
CallConv
==
CallingConv
::
MSP430_INTR
MSP430ISD
::
RETI_FLAG
:
MSP430ISD
::
RET_FLAG
)
;
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
Opc
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static void c6x_hwloops ( void ) { if ( optimize ) reorg_loops ( true , & c6x_doloop_hooks ) ; } </s>

Run the hw-doloop pass to modulo-schedule hardware loops , or split the doloop_end patterns where such optimizations are impossible .


<s> opt_machine_mode aarch64_ptrue_all_mode ( rtx x ) { gcc_assert ( GET_MODE ( x ) == VNx16BImode ) ; if ( GET_CODE ( x ) != CONST_VECTOR || ! CONST_VECTOR_DUPLICATE_P ( x ) || ! CONST_INT_P ( CONST_VECTOR_ENCODED_ELT ( x , 0 ) ) || INTVAL ( CONST_VECTOR_ENCODED_ELT ( x , 0 ) ) == 0 ) return opt_machine_mode ( ) ; unsigned int nelts = const_vector_encoded_nelts ( x ) ; for ( unsigned int i = 1 ; i < nelts ; ++ i ) if ( CONST_VECTOR_ENCODED_ELT ( x , i ) != const0_rtx ) return opt_machine_mode ( ) ; return aarch64_sve_pred_mode ( nelts ) ; } </s>

If VNx16BImode rtx X is a canonical PTRUE for a predicate mode , return that predicate mode , otherwise return opt_machine_mode ( ) .


<s> void rs6000_cost_data :: update_target_cost_per_stmt ( vect_cost_for_stmt kind , stmt_vec_info stmt_info , vect_cost_model_location where , unsigned int orig_count ) { if ( kind == vec_to_scalar || kind == vec_perm || kind == vec_promote_demote || kind == vec_construct || kind == scalar_to_vec || ( where == vect_body && kind == vector_stmt ) ) m_vect_nonmem = true ; if ( ! m_costing_for_scalar && is_a < loop_vec_info > ( m_vinfo ) && where == vect_body ) { m_nstmts += orig_count ; if ( kind == scalar_load || kind == vector_load || kind == unaligned_load || kind == vector_gather_load ) { m_nloads += orig_count ; if ( stmt_info && STMT_VINFO_GATHER_SCATTER_P ( stmt_info ) ) m_gather_load = true ; } else if ( kind == scalar_store || kind == vector_store || kind == unaligned_store || kind == vector_scatter_store ) m_nstores += orig_count ; else if ( ( kind == scalar_stmt || kind == vector_stmt || kind == vec_to_scalar ) && stmt_info && vect_is_reduction ( stmt_info ) ) { tree lhs = gimple_get_lhs ( stmt_info -> stmt ) ; bool is_float = FLOAT_TYPE_P ( TREE_TYPE ( lhs ) ) ; unsigned int basic_cost = is_float ? 2 : 1 ; m_reduc_factor = MAX ( basic_cost * orig_count , m_reduc_factor ) ; } if ( kind == vec_construct && stmt_info && STMT_VINFO_TYPE ( stmt_info ) == load_vec_info_type && ( STMT_VINFO_MEMORY_ACCESS_TYPE ( stmt_info ) == VMAT_ELEMENTWISE || STMT_VINFO_MEMORY_ACCESS_TYPE ( stmt_info ) == VMAT_STRIDED_SLP ) ) { tree vectype = STMT_VINFO_VECTYPE ( stmt_info ) ; unsigned int nunits = vect_nunits_for_cost ( vectype ) ; if ( nunits == 1 ) return ; unsigned int adjusted_cost = ( nunits == 2 ) ? 2 : 1 ; unsigned int extra_cost = nunits * adjusted_cost ; m_extra_ctor_cost += extra_cost ; } } } </s>

Helper function for add_stmt_cost . Check each statement cost entry , gather information and update the target_cost fields accordingly .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"ARM64 branch relaxation pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool microblaze_tls_referenced_p ( rtx x ) { if ( ! TARGET_HAVE_TLS ) return false ; subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , x , ALL ) { const_rtx x = * iter ; if ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) != 0 ) return true ; if ( GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNSPEC_TLS ) iter . skip_subrtxes ( ) ; } return false ; } </s>

Return TRUE if X contains any TLS symbol references .


<s> static bool mips_classify_address ( struct mips_address_info * info , rtx x , machine_mode mode , bool strict_p ) { switch ( GET_CODE ( x ) ) { case REG : case SUBREG : info -> type = ADDRESS_REG ; info -> reg = x ; info -> offset = const0_rtx ; return mips_valid_base_register_p ( info -> reg , mode , strict_p ) ; case PLUS : info -> type = ADDRESS_REG ; info -> reg = XEXP ( x , 0 ) ; info -> offset = XEXP ( x , 1 ) ; return ( mips_valid_base_register_p ( info -> reg , mode , strict_p ) && mips_valid_offset_p ( info -> offset , mode ) ) ; case LO_SUM : info -> type = ADDRESS_LO_SUM ; info -> reg = XEXP ( x , 0 ) ; info -> offset = XEXP ( x , 1 ) ; info -> symbol_type = mips_classify_symbolic_expression ( info -> offset , SYMBOL_CONTEXT_MEM ) ; return ( mips_valid_base_register_p ( info -> reg , mode , strict_p ) && mips_valid_lo_sum_p ( info -> symbol_type , mode ) ) ; case CONST_INT : info -> type = ADDRESS_CONST_INT ; return ! TARGET_MIPS16 && SMALL_INT ( x ) ; case CONST : case LABEL_REF : case SYMBOL_REF : info -> type = ADDRESS_SYMBOLIC ; return ( mips_symbolic_constant_p ( x , SYMBOL_CONTEXT_MEM , & info -> symbol_type ) && mips_symbol_insns ( info -> symbol_type , mode ) > 0 && ! mips_split_p [ info -> symbol_type ] ) ; default : return false ; } } </s>

Return true if X is a valid address for machine mode MODE . If it is , fill in INFO appropriately . STRICT is true if we should only accept hard base registers .


<s> bool isImm ( ) const { return Kind == k_Imm ; } </s>


<s> void ix86_expand_reduc ( rtx ( * fn ) ( rtx , rtx , rtx ) , rtx dest , rtx in ) { rtx half , dst , vec = in ; machine_mode mode = GET_MODE ( in ) ; int i ; if ( TARGET_SSE4_1 && mode == V8HImode && fn == gen_uminv8hi3 ) { emit_insn ( gen_sse4_1_phminposuw ( dest , in ) ) ; return ; } for ( i = GET_MODE_BITSIZE ( mode ) ; i > GET_MODE_BITSIZE ( GET_MODE_INNER ( mode ) ) ; i >>= 1 ) { half = gen_reg_rtx ( mode ) ; emit_reduc_half ( half , vec , i ) ; if ( i == GET_MODE_BITSIZE ( GET_MODE_INNER ( mode ) ) * 2 ) dst = dest ; else dst = gen_reg_rtx ( mode ) ; emit_insn ( fn ( dst , half , vec ) ) ; vec = dst ; } } </s>

Expand a vector reduction . FN is the binary pattern to reduce ; DEST is the destination ; IN is the input vector .


<s>
void
ARMConstantIslands
::
verify
(
)
{
for
(
MachineFunction
::
iterator
MBBI
=
MF
->
begin
(
)
,
E
=
MF
->
end
(
)
;
MBBI
!=
E
;
++
MBBI
)
{
MachineBasicBlock
*
MBB
=
&
*
MBBI
;
unsigned
MBBId
=
MBB
->
getNumber
(
)
;
assert
(
!
MBBId
||
BBInfo
[
MBBId
1
]
.
postOffset
(
)
<=
BBInfo
[
MBBId
]
.
Offset
)
;
}
DEBUG
(
dbgs
(
)
<<
"Verifying "
<<
CPUsers
.
size
(
)
<<
" CP users.\n"
)
;
for
(
unsigned
i
=
0
,
e
=
CPUsers
.
size
(
)
;
i
!=
e
;
++
i
)
{
CPUser
&
U
=
CPUsers
[
i
]
;
unsigned
UserOffset
=
getUserOffset
(
U
)
;
if
(
isCPEntryInRange
(
U
.
MI
,
UserOffset
,
U
.
CPEMI
,
U
.
getMaxDisp
(
)
+
2
,
U
.
NegOk
,
true
)
)
{
DEBUG
(
dbgs
(
)
<<
"OK\n"
)
;
continue
;
}
DEBUG
(
dbgs
(
)
<<
"Out of range.\n"
)
;
dumpBBs
(
)
;
DEBUG
(
MF
->
dump
(
)
)
;
llvm_unreachable
(
"Constant pool entry out of range!"
)
;
}
}
</s>

ARM
ARM
1
"Verifying "
" CP users.\n"
0
2
"OK\n"
"Out of range.\n"
"Constant pool entry out of range!"


<s> void s390_expand_cs_hqi ( machine_mode mode , rtx btarget , rtx vtarget , rtx mem , rtx cmp , rtx new_rtx , bool is_weak ) { struct alignment_context ac ; rtx cmpv , newv , val , cc , seq0 , seq1 , seq2 , seq3 ; rtx res = gen_reg_rtx ( SImode ) ; rtx_code_label * csloop = NULL , * csend = NULL ; gcc_assert ( MEM_P ( mem ) ) ; init_alignment_context ( & ac , mem , mode ) ; val = expand_simple_binop ( SImode , AND , ac . memsi , ac . modemaski , NULL_RTX , 1 , OPTAB_DIRECT ) ; cmpv = s390_two_part_insv ( & ac , & seq0 , & seq2 , mode , val , cmp ) ; newv = s390_two_part_insv ( & ac , & seq1 , & seq3 , mode , val , new_rtx ) ; if ( seq0 ) emit_insn ( seq0 ) ; if ( seq1 ) emit_insn ( seq1 ) ; if ( ! is_weak ) { emit_move_insn ( btarget , const1_rtx ) ; csloop = gen_label_rtx ( ) ; csend = gen_label_rtx ( ) ; emit_label ( csloop ) ; } emit_insn ( seq2 ) ; emit_insn ( seq3 ) ; cc = s390_emit_compare_and_swap ( EQ , res , ac . memsi , cmpv , newv ) ; if ( is_weak ) emit_insn ( gen_cstorecc4 ( btarget , cc , XEXP ( cc , 0 ) , XEXP ( cc , 1 ) ) ) ; else { rtx tmp ; s390_emit_jump ( csend , cc ) ; tmp = copy_to_reg ( val ) ; force_expand_binop ( SImode , and_optab , res , ac . modemaski , val , 1 , OPTAB_DIRECT ) ; cc = s390_emit_compare ( NE , val , tmp ) ; s390_emit_jump ( csloop , cc ) ; emit_move_insn ( btarget , const0_rtx ) ; emit_label ( csend ) ; } convert_move ( vtarget , expand_simple_binop ( SImode , LSHIFTRT , res , ac . shift , NULL_RTX , 1 , OPTAB_DIRECT ) , 1 ) ; } </s>

Expand an atomic compare and swap operation for HImode and QImode . MEM is the memory location , CMP the old value to compare MEM with and NEW the value to set if CMP == MEM . CMP is never in memory for compare_and_swap_cc because expand_bool_compare_and_swap puts it into a register for later compare .


"%qs attribute only applies to functions"

Handle an attribute requiring a FUNCTION_TYPE , FIELD_DECL or TYPE_DECL ; arguments as in struct attribute_spec.handler .


More limited version of SimplifyDemandedBits that can be used to `` look through '' ops that do n't contribute to the DemandedBits/DemandedElts - bitwise ops etc .


<s>
bool
ARMCodeGenPrepare
::
runOnFunction
(
Function
&
F
)
{
if
(
skipFunction
(
F
)
||
DisableCGP
)
return
false
;
auto
*
TPC
=
&
getAnalysis
<
TargetPassConfig
>
(
)
;
if
(
!
TPC
)
return
false
;
const
TargetMachine
&
TM
=
TPC
->
getTM
<
TargetMachine
>
(
)
;
ST
=
&
TM
.
getSubtarget
<
ARMSubtarget
>
(
F
)
;
bool
MadeChange
=
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM CGP: Running on "
<<
F
.
getName
(
)
<<
"\n"
)
;
for
(
BasicBlock
&
BB
:
F
)
{
auto
&
Insts
=
BB
.
getInstList
(
)
;
for
(
auto
&
I
:
Insts
)
{
if
(
AllVisited
.
count
(
&
I
)
)
continue
;
if
(
isa
<
ICmpInst
>
(
I
)
)
{
auto
&
CI
=
cast
<
ICmpInst
>
(
I
)
;
if
(
CI
.
isSigned
(
)
||
!
isa
<
IntegerType
>
(
CI
.
getOperand
(
0
)
->
getType
(
)
)
)
continue
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM CGP: Searching from: "
<<
CI
<<
"\n"
)
;
for
(
auto
&
Op
:
CI
.
operands
(
)
)
{
if
(
auto
*
I
=
dyn_cast
<
Instruction
>
(
Op
)
)
MadeChange
|=
TryToPromote
(
I
)
;
}
}
}
Promoter
->
Cleanup
(
)
;
LLVM_DEBUG
(
if
(
verifyFunction
(
F
,
&
dbgs
(
)
)
)
{
dbgs
(
)
;
report_fatal_error
(
"Broken function after type promotion"
)
;
}
)
;
}
if
(
MadeChange
)
LLVM_DEBUG
(
dbgs
(
)
<<
"After ARMCodeGenPrepare: "
<<
F
<<
"\n"
)
;
return
MadeChange
;
}
</s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .

ARM
ARM
ARM
"ARM CGP: Running on "
"\n"
0
"ARM CGP: Searching from: "
"\n"
"Broken function after type promotion"
"After ARMCodeGenPrepare: "
"\n"


<s> static const char * ix86_get_multilib_abi_name ( void ) { if ( ! ( TARGET_64BIT_P ( ix86_isa_flags ) ) ) return "i386" ; else if ( TARGET_X32_P ( ix86_isa_flags ) ) return "x32" ; else return "x86_64" ; } </s>

This hook returns name of multilib ABI .


<s> void nvptx_expand_call ( rtx retval , rtx address ) { rtx callee = XEXP ( address , 0 ) ; rtx varargs = NULL_RTX ; unsigned parallel = 0 ; if ( ! call_insn_operand ( callee , Pmode ) ) { callee = force_reg ( Pmode , callee ) ; address = change_address ( address , QImode , callee ) ; } if ( GET_CODE ( callee ) == SYMBOL_REF ) { tree decl = SYMBOL_REF_DECL ( callee ) ; if ( decl != NULL_TREE ) { if ( DECL_STATIC_CHAIN ( decl ) ) cfun -> machine -> has_chain = true ; tree attr = get_oacc_fn_attrib ( decl ) ; if ( attr ) { tree dims = TREE_VALUE ( attr ) ; parallel = GOMP_DIM_MASK ( GOMP_DIM_MAX ) - 1 ; for ( int ix = 0 ; ix != GOMP_DIM_MAX ; ix ++ ) { if ( TREE_PURPOSE ( dims ) && ! integer_zerop ( TREE_PURPOSE ( dims ) ) ) break ; parallel ^= GOMP_DIM_MASK ( ix ) ; dims = TREE_CHAIN ( dims ) ; } } } } unsigned nargs = cfun -> machine -> num_args ; if ( cfun -> machine -> is_varadic ) { varargs = gen_reg_rtx ( Pmode ) ; emit_move_insn ( varargs , stack_pointer_rtx ) ; } rtvec vec = rtvec_alloc ( nargs + 1 ) ; rtx pat = gen_rtx_PARALLEL ( VOIDmode , vec ) ; int vec_pos = 0 ; rtx call = gen_rtx_CALL ( VOIDmode , address , const0_rtx ) ; rtx tmp_retval = retval ; if ( retval ) { if ( ! nvptx_register_operand ( retval , GET_MODE ( retval ) ) ) tmp_retval = gen_reg_rtx ( GET_MODE ( retval ) ) ; call = gen_rtx_SET ( tmp_retval , call ) ; } XVECEXP ( pat , 0 , vec_pos ++ ) = call ; for ( rtx arg = cfun -> machine -> call_args ; arg ; arg = XEXP ( arg , 1 ) ) XVECEXP ( pat , 0 , vec_pos ++ ) = gen_rtx_USE ( VOIDmode , XEXP ( arg , 0 ) ) ; if ( varargs ) XVECEXP ( pat , 0 , vec_pos ++ ) = gen_rtx_USE ( VOIDmode , varargs ) ; gcc_assert ( vec_pos = XVECLEN ( pat , 0 ) ) ; nvptx_emit_forking ( parallel , true ) ; emit_call_insn ( pat ) ; nvptx_emit_joining ( parallel , true ) ; if ( tmp_retval != retval ) emit_move_insn ( retval , tmp_retval ) ; } </s>


<s> unsigned AMDGPUInstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr * MI , int & FrameIndex ) const { return 0 ; } </s>

isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s> rtx loongarch_strip_unspec_address ( rtx op ) { rtx base , offset ; split_const ( op , & base , & offset ) ; if ( UNSPEC_ADDRESS_P ( base ) ) op = plus_constant ( Pmode , UNSPEC_ADDRESS ( base ) , INTVAL ( offset ) ) ; return op ; } </s>

If OP is an UNSPEC address , return the address to which it refers , otherwise return OP itself .


<s>
StringRef
getPassName
(
)
const
override
{
return
"RISCV sext.w Removal"
;
}
</s>


<s> bool AMDGPUAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == ".hsa_code_object_version" ) return ParseDirectiveHSACodeObjectVersion ( ) ; if ( IDVal == ".hsa_code_object_isa" ) return ParseDirectiveHSACodeObjectISA ( ) ; if ( IDVal == ".amd_kernel_code_t" ) return ParseDirectiveAMDKernelCodeT ( ) ; if ( IDVal == ".amdgpu_hsa_kernel" ) return ParseDirectiveAMDGPUHsaKernel ( ) ; if ( IDVal == ".amd_amdgpu_isa" ) return ParseDirectiveISAVersion ( ) ; if ( IDVal == AMDGPU :: HSAMD :: AssemblerDirectiveBegin ) return ParseDirectiveHSAMetadata ( ) ; if ( IDVal == PALMD :: AssemblerDirective ) return ParseDirectivePALMetadata ( ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> TargetLowering :: AtomicExpansionKind AArch64TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { unsigned Size = LI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size != 128 || isOpSuitableForLDPSTP ( LI ) ) return AtomicExpansionKind :: None ; return AtomicExpansionKind :: LLSC ; } </s>

Returns how the given ( atomic ) load should be expanded by the IR-level AtomicExpand pass .


<s>
const
char
*
output_mov_double_fpa_from_arm
(
rtx
*
operands
)
{
int
arm_reg0
=
REGNO
(
operands
[
1
]
)
;
rtx
ops
[
2
]
;
gcc_assert
(
arm_reg0
!=
IP_REGNUM
)
;
ops
[
0
]
=
gen_rtx_REG
(
SImode
,
arm_reg0
)
;
ops
[
1
]
=
gen_rtx_REG
(
SImode
,
1
+
arm_reg0
)
;
output_asm_insn
(
"stm%?fd\t%|sp!, {%0, %1}"
,
ops
)
;
output_asm_insn
(
"ldf%?d\t%0, [%|sp], #8"
,
operands
)
;
return
""
;
}
</s>

Output a move from arm registers to an fpa registers . OPERANDS [ 0 ] is an fpa register . OPERANDS [ 1 ] is the first registers of an arm register pair .


"initial_elimination_offset from=%d to=%d, ofs=%d\n"

Implements INITIAL_ELIMINATION_OFFSET . See the comment above that diagrams our call frame .


<s> const char * GBZ80TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { case GBISD :: name : \ return # name switch ( Opcode ) { default : return nullptr ; NODE ( RET_FLAG ) ; NODE ( RETI_FLAG ) ; NODE ( CALL ) ; NODE ( WRAPPER ) ; NODE ( FI ) ; NODE ( LSL ) ; NODE ( LSR ) ; NODE ( ROL ) ; NODE ( ROR ) ; NODE ( ASR ) ; NODE ( LSLLOOP ) ; NODE ( LSRLOOP ) ; NODE ( ASRLOOP ) ; NODE ( BRCOND ) ; NODE ( CMP ) ; NODE ( CMPC ) ; NODE ( TST ) ; NODE ( SELECT_CC ) ; NODE ( SELECT_BR ) ; NODE ( BR16 ) ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static bool i386_pe_dllexport_p ( tree decl ) { if ( TREE_CODE ( decl ) != VAR_DECL && TREE_CODE ( decl ) != FUNCTION_DECL ) return false ; if ( lookup_attribute ( "dllexport" , DECL_ATTRIBUTES ( decl ) ) ) return true ; if ( associated_type ( decl ) && lookup_attribute ( "dllexport" , TYPE_ATTRIBUTES ( associated_type ( decl ) ) ) ) return i386_pe_type_dllexport_p ( decl ) ; return false ; } </s>

Return true if DECL is a dllexport 'd object .


<s> unsigned OutgoingValueHandler :: getStackAddress ( const CCValAssign & VA , MachineMemOperand * & MMO ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; const TargetFrameLowering * TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; LLT p0 = LLT :: pointer ( 0 , 32 ) ; LLT s32 = LLT :: scalar ( 32 ) ; unsigned SPReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildCopy ( SPReg , Mips :: SP ) ; unsigned OffsetReg = MRI . createGenericVirtualRegister ( s32 ) ; unsigned Offset = VA . getLocMemOffset ( ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildGEP ( AddrReg , SPReg , OffsetReg ) ; MachinePointerInfo MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ; unsigned Size = alignTo ( VA . getValVT ( ) . getSizeInBits ( ) , 8 ) / 8 ; unsigned Align = MinAlign ( TFL -> getStackAlignment ( ) , Offset ) ; MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , Align ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> rtx alpha_expand_zap_mask ( HOST_WIDE_INT value ) { rtx result ; int i ; HOST_WIDE_INT mask = 0 ; for ( i = 7 ; i >= 0 ; -- i ) { mask <<= 8 ; if ( ! ( ( value >> i ) & 1 ) ) mask |= 0xff ; } result = gen_int_mode ( mask , DImode ) ; return result ; } </s>

Returns a mask so that zap ( x , value ) == x & mask .


<s> bool Error ( SMLoc L , const Twine & Msg ) { return Parser . Error ( L , Msg ) ; } </s>

Return an error at the location L , with the message Msg .


<s> static bool has_vector_insn ( function * fn ) { basic_block cfg_bb ; rtx_insn * rinsn ; FOR_ALL_BB_FN ( cfg_bb , fn ) FOR_BB_INSNS ( cfg_bb , rinsn ) if ( NONDEBUG_INSN_P ( rinsn ) && has_vtype_op ( rinsn ) ) return true ; return false ; } </s>

Return true if FN has a vector instruction that use VL/VTYPE .


<s> static rtx riscv_pass_fpr_single ( machine_mode type_mode , unsigned regno , machine_mode value_mode , HOST_WIDE_INT offset ) { rtx x = gen_rtx_REG ( value_mode , regno ) ; if ( type_mode != value_mode ) { x = gen_rtx_EXPR_LIST ( VOIDmode , x , GEN_INT ( offset ) ) ; x = gen_rtx_PARALLEL ( type_mode , gen_rtvec ( 1 , x ) ) ; } return x ; } </s>

Return the representation of an argument passed or returned in an FPR when the value has mode VALUE_MODE and the type has TYPE_MODE . The two modes may be different for structures like : struct __attribute__ ( ( packed ) ) foo { float f ; } where the SFmode value `` f '' is passed in REGNO but the struct itself has mode BLKmode .


<s> bool ARM64PromoteConstant :: runOnFunction ( Function & F ) { bool LocalChange = false ; SmallSet < Constant * , 8 > AlreadyChecked ; for ( auto & MBB : F ) { for ( auto & MI : MBB ) { for ( unsigned OpIdx = 0 , EndOpIdx = MI . getNumOperands ( ) ; OpIdx != EndOpIdx ; ++ OpIdx ) { Constant * Cst = dyn_cast < Constant > ( MI . getOperand ( OpIdx ) ) ; if ( Cst && ! isa < GlobalValue > ( Cst ) && ! isa < ConstantExpr > ( Cst ) && AlreadyChecked . insert ( Cst ) ) LocalChange |= promoteConstant ( Cst ) ; } } } return LocalChange ; } </s>


"getMemOperandWithOffset only supports base "

Return true if get the base operand , byte offset of an instruction and the memory width .


<s> static bool mips_legitimate_address_p ( machine_mode mode , rtx x , bool strict_p ) { struct mips_address_info addr ; return mips_classify_address ( & addr , x , mode , strict_p ) ; } </s>

This function is used to implement GO_IF_LEGITIMATE_ADDRESS . It returns a nonzero value if X is a legitimate address for a memory operand of the indicated MODE . STRICT is nonzero if this function is called during reload .


<s> X86Subtarget :: X86Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const X86TargetMachine & TM , unsigned StackAlignOverride ) : X86GenSubtargetInfo ( TT , CPU , FS ) , X86ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TM ( TM ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( * this , getStackAlignment ( ) ) { if ( ! isPositionIndependent ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( is64Bit ( ) ) setPICStyle ( PICStyles :: RIPRel ) ; else if ( isTargetCOFF ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( isTargetDarwin ( ) ) setPICStyle ( PICStyles :: StubPIC ) ; else if ( isTargetELF ( ) ) setPICStyle ( PICStyles :: GOT ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> static bool thumb_force_lr_save ( void ) { return ! cfun -> machine -> lr_save_eliminated && ( ! leaf_function_p ( ) || thumb_far_jump_used_p ( ) || regs_ever_live [ LR_REGNUM ] ) ; } </s>

Return true if the current function needs to save/restore LR .


"Can only put epilog before 'retl' instruction!"


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return createARMELFObjectWriter ( OS , OSABI , isLittle ( ) ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


"Error: found feature bits in the ALL_FPU_INTERAL"

" group that are not defined by any FPU.\n"

Scan the static data tables generated by parsecpu.awk looking for potential issues with the data . Here we check for consistency between the fpu bits , in particular we check that ISA_ALL_FPU_INTERNAL does not contain a feature bit that is not defined by any FPU flag .


<s> bool PPCInstrInfo :: getMachineCombinerPatterns ( MachineInstr & Root , SmallVectorImpl < MachineCombinerPattern > & Patterns ) const { if ( Subtarget . getTargetMachine ( ) . getOptLevel ( ) != CodeGenOpt :: Aggressive ) return false ; if ( ! Root . getParent ( ) -> getParent ( ) -> getTarget ( ) . Options . UnsafeFPMath ) return false ; return TargetInstrInfo :: getMachineCombinerPatterns ( Root , Patterns ) ; } </s>

Return true when there is potentially a faster code sequence for an instruction chain ending in Root .


<s> bool m68k_regno_mode_ok ( int regno , machine_mode mode ) { if ( DATA_REGNO_P ( regno ) ) { if ( regno + GET_MODE_SIZE ( mode ) / 4 <= 8 ) return true ; } else if ( ADDRESS_REGNO_P ( regno ) ) { if ( regno + GET_MODE_SIZE ( mode ) / 4 <= 16 ) return true ; } else if ( FP_REGNO_P ( regno ) ) { if ( ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) && GET_MODE_UNIT_SIZE ( mode ) <= TARGET_FP_REG_SIZE ) return true ; } return false ; } </s>

Value is true if hard register REGNO can hold a value of machine-mode MODE . On the 68000 , we let the cpu registers can hold any mode , but restrict the 68881 registers to floating-point modes .


<s>
bool
SIPreAllocateWWMRegs
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"SIPreAllocateWWMRegs: function "
<<
MF
.
getName
(
)
<<
"\n"
)
;
const
GCNSubtarget
&
ST
=
MF
.
getSubtarget
<
GCNSubtarget
>
(
)
;
TII
=
ST
.
getInstrInfo
(
)
;
TRI
=
&
TII
->
getRegisterInfo
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
LIS
=
&
getAnalysis
<
LiveIntervals
>
(
)
;
Matrix
=
&
getAnalysis
<
LiveRegMatrix
>
(
)
;
VRM
=
&
getAnalysis
<
VirtRegMap
>
(
)
;
RegClassInfo
.
runOnMachineFunction
(
MF
)
;
bool
RegsAssigned
=
false
;
ReversePostOrderTraversal
<
MachineFunction
*
>
RPOT
(
&
MF
)
;
for
(
MachineBasicBlock
*
MBB
:
RPOT
)
{
bool
InWWM
=
false
;
for
(
MachineInstr
&
MI
:
*
MBB
)
{
if
(
MI
.
getOpcode
(
)
==
AMDGPU
::
V_SET_INACTIVE_B32
||
MI
.
getOpcode
(
)
==
AMDGPU
::
V_SET_INACTIVE_B64
)
RegsAssigned
|=
processDef
(
MI
.
getOperand
(
0
)
)
;
if
(
MI
.
getOpcode
(
)
==
AMDGPU
::
ENTER_STRICT_WWM
||
MI
.
getOpcode
(
)
==
AMDGPU
::
ENTER_STRICT_WQM
)
{
LLVM_DEBUG
(
printWWMInfo
(
MI
)
)
;
InWWM
=
true
;
continue
;
}
if
(
MI
.
getOpcode
(
)
==
AMDGPU
::
EXIT_STRICT_WWM
||
MI
.
getOpcode
(
)
==
AMDGPU
::
EXIT_STRICT_WQM
)
{
LLVM_DEBUG
(
printWWMInfo
(
MI
)
)
;
InWWM
=
false
;
}
if
(
!
InWWM
)
continue
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Processing "
<<
MI
)
;
for
(
MachineOperand
&
DefOpnd
:
MI
.
defs
(
)
)
{
RegsAssigned
|=
processDef
(
DefOpnd
)
;
}
}
}
if
(
!
RegsAssigned
)
return
false
;
rewriteRegs
(
MF
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> SchedBoundary ( unsigned ID , const Twine & Name ) : DAG ( 0 ) , Available ( ID , Name + ".A" ) , Pending ( ID << ConvergingVLIWScheduler :: LogMaxQID , Name + ".P" ) , CheckPending ( false ) , HazardRec ( 0 ) , ResourceModel ( 0 ) , CurrCycle ( 0 ) , IssueCount ( 0 ) , MinReadyCycle ( UINT_MAX ) , MaxMinLatency ( 0 ) { } </s>

Pending queues extend the ready queues with the same ID and the PendingFlag set .


<s>
SDValue
LC3TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unimplemented operand"
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool SPUTargetMachine :: addPreEmitPass ( PassManagerBase & PM ) { typedef llvm :: FunctionPass * ( * BuilderFunc ) ( const char * ) ; BuilderFunc schedulerCreator = ( BuilderFunc ) ( intptr_t ) sys :: DynamicLibrary :: SearchForAddressOfSymbol ( "createTCESchedulerPass" ) ; if ( schedulerCreator != NULL ) PM . add ( schedulerCreator ( "cellspu" ) ) ; PM . add ( createSPUNopFillerPass ( * this ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

CellSPU SPU "createTCESchedulerPass" "cellspu" SPU


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BRCOND : return LowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return LowerConstantPool ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: BlockAddress : return LowerBlockAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return LowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( Op , DAG ) ; case ISD :: SELECT : return LowerSELECT ( Op , DAG ) ; case ISD :: SELECT_CC : return LowerSELECT_CC ( Op , DAG ) ; case ISD :: SETCC : return LowerSETCC ( Op , DAG ) ; case ISD :: VASTART : return LowerVASTART ( Op , DAG ) ; case ISD :: FCOPYSIGN : return LowerFCOPYSIGN ( Op , DAG ) ; case ISD :: FABS : return LowerFABS ( Op , DAG ) ; case ISD :: FRAMEADDR : return LowerFRAMEADDR ( Op , DAG ) ; case ISD :: RETURNADDR : return LowerRETURNADDR ( Op , DAG ) ; case ISD :: MEMBARRIER : return LowerMEMBARRIER ( Op , DAG ) ; case ISD :: ATOMIC_FENCE : return LowerATOMIC_FENCE ( Op , DAG ) ; case ISD :: SHL_PARTS : return LowerShiftLeftParts ( Op , DAG ) ; case ISD :: SRA_PARTS : return LowerShiftRightParts ( Op , DAG , true ) ; case ISD :: SRL_PARTS : return LowerShiftRightParts ( Op , DAG , false ) ; case ISD :: LOAD : return LowerLOAD ( Op , DAG ) ; case ISD :: STORE : return LowerSTORE ( Op , DAG ) ; case ISD :: INTRINSIC_WO_CHAIN : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case ISD :: INTRINSIC_W_CHAIN : return LowerINTRINSIC_W_CHAIN ( Op , DAG ) ; case ISD :: ADD : return LowerADD ( Op , DAG ) ; } return SDValue ( ) ; } </s>

Mips Mips ISD::BRCOND ISD::ConstantPool ISD::GlobalAddress ISD::BlockAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::SELECT ISD::SELECT_CC ISD::SETCC ISD::VASTART ISD::FCOPYSIGN ISD::FABS ISD::FRAMEADDR ISD::RETURNADDR ISD::MEMBARRIER ISD::ATOMIC_FENCE ISD::SHL_PARTS ISD::SRA_PARTS ISD::SRL_PARTS ISD::LOAD ISD::STORE ISD::INTRINSIC_WO_CHAIN ISD::INTRINSIC_W_CHAIN ISD::ADD


<s> bool const_vec_all_same_in_range_p ( rtx x , HOST_WIDE_INT minval , HOST_WIDE_INT maxval ) { rtx elt ; return ( const_vec_duplicate_p ( x , & elt ) && CONST_INT_P ( elt ) && IN_RANGE ( INTVAL ( elt ) , minval , maxval ) ) ; } </s>

Return true if X is a const_vector with all duplicate elements , which is in the range between MINVAL and MAXVAL .


<s> void rs6000_set_handled_components ( sbitmap components ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; for ( int i = info -> first_gp_reg_save ; i < 32 ; i ++ ) if ( bitmap_bit_p ( components , i ) ) cfun -> machine -> gpr_is_wrapped_separately [ i ] = true ; for ( int i = info -> first_fp_reg_save ; i < 64 ; i ++ ) if ( bitmap_bit_p ( components , i ) ) cfun -> machine -> fpr_is_wrapped_separately [ i - 32 ] = true ; if ( bitmap_bit_p ( components , 0 ) ) cfun -> machine -> lr_is_wrapped_separately = true ; if ( bitmap_bit_p ( components , 2 ) ) cfun -> machine -> toc_is_wrapped_separately = true ; } </s>


<s> const char * VETargetLowering :: getTargetNodeName ( unsigned Opcode ) const { case VEISD :: NAME : \ return "VEISD::" # NAME ; switch ( ( VEISD :: NodeType ) Opcode ) { case VEISD :: FIRST_NUMBER : break ; TARGET_NODE_CASE ( Lo ) TARGET_NODE_CASE ( Hi ) TARGET_NODE_CASE ( GETFUNPLT ) TARGET_NODE_CASE ( GETSTACKTOP ) TARGET_NODE_CASE ( GETTLSADDR ) TARGET_NODE_CASE ( CALL ) TARGET_NODE_CASE ( RET_FLAG ) TARGET_NODE_CASE ( GLOBAL_BASE_REG ) } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

VE VE VEISD::NAME "VEISD::" VEISD::NodeType VEISD::FIRST_NUMBER


<s> bool PPCFastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Load : return SelectLoad ( I ) ; case Instruction :: Store : return SelectStore ( I ) ; case Instruction :: Br : return SelectBranch ( I ) ; case Instruction :: IndirectBr : return SelectIndirectBr ( I ) ; case Instruction :: FPExt : return SelectFPExt ( I ) ; case Instruction :: FPTrunc : return SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return SelectIToFP ( I , true ) ; case Instruction :: UIToFP : return SelectIToFP ( I , false ) ; case Instruction :: FPToSI : return SelectFPToI ( I , true ) ; case Instruction :: FPToUI : return SelectFPToI ( I , false ) ; case Instruction :: Add : return SelectBinaryIntOp ( I , ISD :: ADD ) ; case Instruction :: Or : return SelectBinaryIntOp ( I , ISD :: OR ) ; case Instruction :: Sub : return SelectBinaryIntOp ( I , ISD :: SUB ) ; case Instruction :: Ret : return SelectRet ( I ) ; case Instruction :: Trunc : return SelectTrunc ( I ) ; case Instruction :: ZExt : case Instruction :: SExt : return SelectIntExt ( I ) ; default : break ; } return false ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> bool XCoreAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( ! ExtraCode || ! ExtraCode [ 0 ] ) { printOperand ( MI , OpNo , O ) ; return false ; } return AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , O ) ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static bool is_lfs_stfs_insn ( rtx_insn * insn ) { rtx pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) != PARALLEL ) return false ; if ( XVECLEN ( pattern , 0 ) != 2 ) return false ; rtx set = XVECEXP ( pattern , 0 , 0 ) ; if ( GET_CODE ( set ) != SET ) return false ; rtx clobber = XVECEXP ( pattern , 0 , 1 ) ; if ( GET_CODE ( clobber ) != CLOBBER ) return false ; rtx dest = SET_DEST ( set ) ; rtx src = SET_SRC ( set ) ; rtx scratch = SET_DEST ( clobber ) ; if ( GET_CODE ( src ) != UNSPEC ) return false ; if ( XINT ( src , 1 ) == UNSPEC_SI_FROM_SF && GET_CODE ( dest ) == MEM && GET_MODE ( dest ) == SImode && GET_CODE ( scratch ) == SCRATCH && GET_MODE ( scratch ) == V4SFmode ) return true ; if ( XINT ( src , 1 ) == UNSPEC_SF_FROM_SI && GET_CODE ( dest ) == REG && GET_MODE ( dest ) == SFmode && GET_CODE ( scratch ) == SCRATCH && GET_MODE ( scratch ) == DImode ) return true ; return false ; } </s>

Helper function to see if we 're potentially looking at lfs/stfs . - PARALLEL containing a SET and a CLOBBER - stfs : - SET is from UNSPEC_SI_FROM_SF to MEM : SI - CLOBBER is a V4SF - lfs : - SET is from UNSPEC_SF_FROM_SI to REG : SF - CLOBBER is a DI


<s> BitVector TOYRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( TOY :: ZERO ) ; Reserved . set ( TOY :: SP ) ; Reserved . set ( TOY :: LR ) ; Reserved . set ( TOY :: TMP ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .

TOY TOY TOY::ZERO TOY::SP TOY::LR TOY::TMP


<s> const MipsFrameLowering * MipsFrameLowering :: create ( const MipsSubtarget & ST ) { return llvm :: createMipsSEFrameLowering ( ST ) ; } </s>


<s> bool Thumb1RegisterInfo :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; unsigned CFSize = FFI -> getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( 1 << 8 ) - 1 ) * 4 / 2 ) return false ; return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> bool R600InstrInfo :: isPredicable ( const MachineInstr & MI ) const { if ( MI . getOpcode ( ) == R600 :: KILLGT ) { return false ; } else if ( MI . getOpcode ( ) == R600 :: CF_ALU ) { if ( MI . getParent ( ) -> begin ( ) != MachineBasicBlock :: const_iterator ( MI ) ) return false ; return MI . getOperand ( 3 ) . getImm ( ) == 0 && MI . getOperand ( 4 ) . getImm ( ) == 0 ; } else if ( isVector ( MI ) ) { return false ; } else { return TargetInstrInfo :: isPredicable ( MI ) ; } } </s>

Return true if the specified instruction can be predicated .


<s> static HOST_WIDE_INT cris_static_rtx_alignment ( machine_mode mode ) { return MAX ( cris_preferred_mininum_alignment ( ) , GET_MODE_ALIGNMENT ( mode ) ) ; } </s>


<s> virtual bool isFMAFasterThanFMulAndFAdd ( EVT ) const { return true ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> rtx alpha_gp_save_rtx ( ) { rtx r = get_hard_reg_initial_val ( DImode , 29 ) ; if ( GET_CODE ( r ) != MEM ) r = gen_mem_addressof ( r , NULL_TREE ) ; return r ; } </s>

Return or create a pseudo containing the gp value for the current function . Needed only if TARGET_LD_BUGGY_LDGP .


<s> MVT getPointerMemTy ( const DataLayout & DL , uint32_t AS = 0 ) const override { if ( AS == WasmAddressSpace :: EXTERNREF ) return MVT :: externref ; if ( AS == WasmAddressSpace :: FUNCREF ) return MVT :: funcref ; return TargetLowering :: getPointerMemTy ( DL , AS ) ; } </s>

Return the in-memory pointer type for the given address space , defaults to the pointer type from the data layout .

WebAssembly 0 WasmAddressSpace::EXTERNREF MVT::externref WasmAddressSpace::FUNCREF MVT::funcref


<s> ScheduleHazardRecognizer * HexagonInstrInfo :: CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II , const ScheduleDAG * DAG ) const { return TargetInstrInfo :: CreateTargetPostRAHazardRecognizer ( II , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for by non-scheduling passes .


<s>
void
cris_expand_pic_call_address
(
rtx
*
opp
,
rtx
*
markerp
)
{
rtx
op
=
*
opp
;
gcc_assert
(
flag_pic
&&
MEM_P
(
op
)
)
;
op
=
XEXP
(
op
,
0
)
;
if
(
CONSTANT_P
(
op
)
&&
!
CONST_INT_P
(
op
)
)
{
enum
cris_symbol_type
t
=
cris_symbol_type_of
(
op
)
;
CRIS_ASSERT
(
can_create_pseudo_p
(
)
)
;
if
(
t
==
cris_rel_symbol
)
{
if
(
TARGET_V32
)
{
rtx
sym
=
GET_CODE
(
op
)
!=
CONST
op
:
get_related_value
(
op
)
;
HOST_WIDE_INT
offs
=
get_integer_term
(
op
)
;
gcc_assert
(
offs
==
0
)
;
op
=
gen_rtx_CONST
(
Pmode
,
gen_rtx_UNSPEC
(
Pmode
,
gen_rtvec
(
1
,
sym
)
,
CRIS_UNSPEC_PCREL
)
)
;
}
else
op
=
force_reg
(
Pmode
,
op
)
;
*
markerp
=
const0_rtx
;
}
else
if
(
t
==
cris_got_symbol
)
{
if
(
TARGET_AVOID_GOTPLT
)
{
rtx
tem
,
rm
,
ro
;
crtl
->
uses_pic_offset_table
=
1
;
tem
=
gen_rtx_UNSPEC
(
Pmode
,
gen_rtvec
(
1
,
op
)
,
TARGET_V32
CRIS_UNSPEC_PLT_PCREL
:
CRIS_UNSPEC_PLT_GOTREL
)
;
tem
=
gen_rtx_CONST
(
Pmode
,
tem
)
;
if
(
TARGET_V32
)
op
=
tem
;
else
{
rm
=
gen_reg_rtx
(
Pmode
)
;
emit_move_insn
(
rm
,
tem
)
;
ro
=
gen_reg_rtx
(
Pmode
)
;
if
(
expand_binop
(
Pmode
,
add_optab
,
rm
,
pic_offset_table_rtx
,
ro
,
0
,
OPTAB_LIB_WIDEN
)
!=
ro
)
internal_error
(
"expand_binop failed in movsi got"
)
;
op
=
ro
;
}
}
else
{
rtx
tem
,
mem
,
rm
,
ro
;
gcc_assert
(
can_create_pseudo_p
(
)
)
;
crtl
->
uses_pic_offset_table
=
1
;
tem
=
gen_rtx_UNSPEC
(
Pmode
,
gen_rtvec
(
1
,
op
)
,
CRIS_UNSPEC_PLTGOTREAD
)
;
rm
=
gen_reg_rtx
(
Pmode
)
;
emit_move_insn
(
rm
,
gen_rtx_CONST
(
Pmode
,
tem
)
)
;
ro
=
gen_reg_rtx
(
Pmode
)
;
if
(
expand_binop
(
Pmode
,
add_optab
,
rm
,
pic_offset_table_rtx
,
ro
,
0
,
OPTAB_LIB_WIDEN
)
!=
ro
)
internal_error
(
"expand_binop failed in movsi got"
)
;
mem
=
gen_rtx_MEM
(
Pmode
,
ro
)
;
set_mem_alias_set
(
mem
,
new_alias_set
(
)
)
;
MEM_NOTRAP_P
(
mem
)
=
1
;
op
=
mem
;
}
*
markerp
=
pic_offset_table_rtx
;
}
else
fatal_insn
(
"unidentifiable call op"
,
op
)
;
*
opp
=
replace_equiv_address_nv
(
*
opp
,
op
)
;
}
else
*
markerp
=
pic_offset_table_rtx
;
}
</s>

Worker function for expanding the address for PIC function calls .


<s> static rtx frame_emit_store ( int regno , int regno_note , rtx addr , rtx cfa , int cfa_offset ) { rtx reg = gen_rtx_REG ( DImode , regno ) ; rtx mem = gen_frame_mem ( DImode , addr ) ; rtx mov = gen_movdi ( mem , reg ) ; rtx reg_note = gen_rtx_REG ( DImode , regno_note ) ; rtx cfa_relative_addr = gen_rtx_PLUS ( Pmode , cfa , GEN_INT ( cfa_offset ) ) ; rtx cfa_relative_mem = gen_frame_mem ( DImode , cfa_relative_addr ) ; rtx real = gen_rtx_SET ( cfa_relative_mem , reg_note ) ; add_reg_note ( mov , REG_CFA_OFFSET , real ) ; return emit_insn ( mov ) ; } </s>

Emit a store in the stack frame to save REGNO at address ADDR , and emit the corresponding REG_CFA_OFFSET note described by CFA and CFA_OFFSET . Return the emitted insn .


<s> BitVector MipsRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t ReservedCPURegs [ ] = { Mips :: ZERO , Mips :: K0 , Mips :: K1 , Mips :: SP } ; static const uint16_t ReservedCPU64Regs [ ] = { Mips :: ZERO_64 , Mips :: K0_64 , Mips :: K1_64 , Mips :: SP_64 } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: const_iterator RegIter ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; if ( Subtarget . isTargetNaCl ( ) ) { static const uint16_t PnaclReservedCPURegs [ ] = { Mips :: T6 , Mips :: T7 , Mips :: T8 } ; for ( unsigned I = 0 ; I < array_lengthof ( PnaclReservedCPURegs ) ; ++ I ) Reserved . set ( PnaclReservedCPURegs [ I ] ) ; } for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPU64Regs ) ; ++ I ) Reserved . set ( ReservedCPU64Regs [ I ] ) ; if ( Subtarget . hasMips64 ( ) ) { for ( RegIter Reg = Mips :: AFGR64RegClass . begin ( ) , EReg = Mips :: AFGR64RegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } else { for ( RegIter Reg = Mips :: FGR64RegClass . begin ( ) , EReg = Mips :: FGR64RegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) ) { if ( Subtarget . inMips16Mode ( ) ) Reserved . set ( Mips :: S0 ) ; else { Reserved . set ( Mips :: FP ) ; Reserved . set ( Mips :: FP_64 ) ; } } Reserved . set ( Mips :: HWR29 ) ; Reserved . set ( Mips :: HWR29_64 ) ; Reserved . set ( Mips :: DSPCtrl ) ; if ( Subtarget . inMips16Mode ( ) ) { Reserved . set ( Mips :: RA ) ; Reserved . set ( Mips :: RA_64 ) ; } if ( Subtarget . useSmallSection ( ) ) { Reserved . set ( Mips :: GP ) ; Reserved . set ( Mips :: GP_64 ) ; } return Reserved ; } </s>


<s> const RegisterBankInfo :: InstructionMapping & MipsRegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const RegisterBankInfo :: InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; switch ( Opc ) { case G_ADD : case G_LOAD : case G_STORE : case G_GEP : OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; break ; case G_CONSTANT : case G_FRAME_INDEX : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr } ) ; break ; default : return getInvalidInstructionMapping ( ) ; } return getInstructionMapping ( DefaultMappingID , 1 , OperandsMapping , NumOperands ) ; } </s>

Get the mapping of the different operands of MI on the register bank .

Mips Mips Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx 1


<s> unsigned Cpu0RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? ( Cpu0 :: FP ) : ( Cpu0 :: SP ) ; } </s>


<s> void ia64_expand_compare ( rtx * expr , rtx * op0 , rtx * op1 ) { enum rtx_code code = GET_CODE ( * expr ) ; rtx cmp ; if ( GET_MODE ( * op0 ) == BImode ) { gcc_assert ( ( code == NE || code == EQ ) && * op1 == const0_rtx ) ; cmp = * op0 ; } else if ( TARGET_HPUX && GET_MODE ( * op0 ) == TFmode ) { enum qfcmp_magic { QCMP_INV = 1 , QCMP_UNORD = 2 , QCMP_EQ = 4 , QCMP_LT = 8 , QCMP_GT = 16 } ; int magic ; enum rtx_code ncode ; rtx ret ; gcc_assert ( cmptf_libfunc && GET_MODE ( * op1 ) == TFmode ) ; switch ( code ) { case EQ : magic = QCMP_EQ ; ncode = NE ; break ; case NE : magic = QCMP_EQ ; ncode = EQ ; break ; case UNORDERED : magic = QCMP_UNORD ; ncode = NE ; break ; case ORDERED : magic = QCMP_UNORD ; ncode = EQ ; break ; case LT : magic = QCMP_LT | QCMP_INV ; ncode = NE ; break ; case LE : magic = QCMP_LT | QCMP_EQ | QCMP_INV ; ncode = NE ; break ; case GT : magic = QCMP_GT | QCMP_INV ; ncode = NE ; break ; case GE : magic = QCMP_GT | QCMP_EQ | QCMP_INV ; ncode = NE ; break ; case UNLT : magic = QCMP_LT | QCMP_UNORD ; ncode = NE ; break ; case UNLE : magic = QCMP_LT | QCMP_EQ | QCMP_UNORD ; ncode = NE ; break ; case UNGT : magic = QCMP_GT | QCMP_UNORD ; ncode = NE ; break ; case UNGE : magic = QCMP_GT | QCMP_EQ | QCMP_UNORD ; ncode = NE ; break ; case UNEQ : case LTGT : default : gcc_unreachable ( ) ; } start_sequence ( ) ; ret = emit_library_call_value ( cmptf_libfunc , 0 , LCT_CONST , DImode , * op0 , TFmode , * op1 , TFmode , GEN_INT ( magic ) , DImode ) ; cmp = gen_reg_rtx ( BImode ) ; emit_insn ( gen_rtx_SET ( cmp , gen_rtx_fmt_ee ( ncode , BImode , ret , const0_rtx ) ) ) ; rtx_insn * insns = get_insns ( ) ; end_sequence ( ) ; emit_libcall_block ( insns , cmp , cmp , gen_rtx_fmt_ee ( code , BImode , * op0 , * op1 ) ) ; code = NE ; } else { cmp = gen_reg_rtx ( BImode ) ; emit_insn ( gen_rtx_SET ( cmp , gen_rtx_fmt_ee ( code , BImode , * op0 , * op1 ) ) ) ; code = NE ; } * expr = gen_rtx_fmt_ee ( code , VOIDmode , cmp , const0_rtx ) ; * op0 = cmp ; * op1 = const0_rtx ; } </s>

Emit comparison instruction if necessary , returning the expression that holds the compare result in the proper mode .


<s> int SIFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const SIRegisterInfo * RI = MF . getSubtarget < SISubtarget > ( ) . getRegisterInfo ( ) ; FrameReg = RI -> getFrameRegister ( MF ) ; return MF . getFrameInfo ( ) . getObjectOffset ( FI ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> static tree nvptx_get_worker_red_addr ( tree type , tree offset ) { machine_mode mode = TYPE_MODE ( type ) ; tree fndecl = nvptx_builtin_decl ( NVPTX_BUILTIN_WORKER_ADDR , true ) ; tree size = build_int_cst ( unsigned_type_node , GET_MODE_SIZE ( mode ) ) ; tree align = build_int_cst ( unsigned_type_node , GET_MODE_ALIGNMENT ( mode ) / BITS_PER_UNIT ) ; tree call = build_call_expr ( fndecl , 3 , offset , size , align ) ; return fold_convert ( build_pointer_type ( type ) , call ) ; } </s>

Generate a PTX builtin function call that returns the address in the worker reduction buffer at OFFSET . TYPE is the type of the data at that location .


<s> static rtx mcore_function_arg ( cumulative_args_t cum , const function_arg_info & arg ) { int arg_reg ; if ( ! arg . named || arg . end_marker_p ( ) ) return 0 ; if ( targetm . calls . must_pass_in_stack ( arg ) ) return 0 ; arg_reg = ROUND_REG ( * get_cumulative_args ( cum ) , arg . mode ) ; if ( arg_reg < NPARM_REGS ) return handle_structs_in_regs ( arg . mode , arg . type , FIRST_PARM_REG + arg_reg ) ; return 0 ; } </s>

Define where to put the arguments to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . On MCore the first args are normally in registers and the rest are pushed . Any arg that starts within the first NPARM_REGS words is at least partially passed in a register unless its data type forbids .


<s> bool Mips16DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & static_cast < const MipsSubtarget & > ( MF . getSubtarget ( ) ) ; if ( ! Subtarget -> inMips16Mode ( ) ) return false ; return MipsDAGToDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> static enum reg_class rs6000_secondary_reload_class ( enum reg_class rclass , machine_mode mode , rtx in ) { int regno ; if ( TARGET_ELF || ( DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT ) ) { if ( rclass != BASE_REGS && ( GET_CODE ( in ) == SYMBOL_REF || GET_CODE ( in ) == HIGH || GET_CODE ( in ) == LABEL_REF || GET_CODE ( in ) == CONST ) ) return BASE_REGS ; } if ( GET_CODE ( in ) == REG ) { regno = REGNO ( in ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) { regno = true_regnum ( in ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) regno = - 1 ; } } else if ( GET_CODE ( in ) == SUBREG ) { regno = true_regnum ( in ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) regno = - 1 ; } else regno = - 1 ; if ( TARGET_VSX && GET_MODE_SIZE ( mode ) < 16 && ! mode_supports_vmx_dform ( mode ) && ( ( ( rclass == GENERAL_REGS || rclass == BASE_REGS ) && ( regno >= 0 && ALTIVEC_REGNO_P ( regno ) ) ) || ( ( rclass == VSX_REGS || rclass == ALTIVEC_REGS ) && ( regno >= 0 && INT_REGNO_P ( regno ) ) ) ) ) return FLOAT_REGS ; if ( rclass == GENERAL_REGS || rclass == BASE_REGS || ( regno >= 0 && INT_REGNO_P ( regno ) ) ) return NO_REGS ; if ( rclass == VSX_REGS && ( regno == - 1 || VSX_REGNO_P ( regno ) ) ) return NO_REGS ; if ( ( regno == - 1 || FP_REGNO_P ( regno ) ) && ( rclass == FLOAT_REGS || rclass == NON_SPECIAL_REGS ) ) return ( mode != SDmode || lra_in_progress ) ? NO_REGS : GENERAL_REGS ; if ( ( regno == - 1 || ALTIVEC_REGNO_P ( regno ) ) && rclass == ALTIVEC_REGS ) return NO_REGS ; if ( ( rclass == CR_REGS || rclass == CR0_REGS ) && regno >= 0 && CR_REGNO_P ( regno ) ) return NO_REGS ; return GENERAL_REGS ; } </s>

Return the register class of a scratch register needed to copy IN into or out of a register in RCLASS in MODE . If it can be done directly , NO_REGS is returned .


<s> int h8300_regs_ok_for_stm ( int n , rtx operands [ ] ) { switch ( n ) { case 2 : return ( ( REGNO ( operands [ 0 ] ) == 0 && REGNO ( operands [ 1 ] ) == 1 ) || ( REGNO ( operands [ 0 ] ) == 2 && REGNO ( operands [ 1 ] ) == 3 ) || ( REGNO ( operands [ 0 ] ) == 4 && REGNO ( operands [ 1 ] ) == 5 ) ) ; case 3 : return ( ( REGNO ( operands [ 0 ] ) == 0 && REGNO ( operands [ 1 ] ) == 1 && REGNO ( operands [ 2 ] ) == 2 ) || ( REGNO ( operands [ 0 ] ) == 4 && REGNO ( operands [ 1 ] ) == 5 && REGNO ( operands [ 2 ] ) == 6 ) ) ; case 4 : return ( REGNO ( operands [ 0 ] ) == 0 && REGNO ( operands [ 1 ] ) == 1 && REGNO ( operands [ 2 ] ) == 2 && REGNO ( operands [ 3 ] ) == 3 ) ; default : gcc_unreachable ( ) ; } } </s>

Return nonzero if OPERANDS are valid for stm ( or ldm ) that pushes ( or pops ) N registers . OPERANDS are assumed to be an array of registers .


<s> void arm_split_compare_and_swap ( rtx operands [ ] ) { rtx rval , mem , oldval , newval , scratch ; machine_mode mode ; enum memmodel mod_s , mod_f ; bool is_weak ; rtx_code_label * label1 , * label2 ; rtx x , cond ; rval = operands [ 0 ] ; mem = operands [ 1 ] ; oldval = operands [ 2 ] ; newval = operands [ 3 ] ; is_weak = ( operands [ 4 ] != const0_rtx ) ; mod_s = ( enum memmodel ) INTVAL ( operands [ 5 ] ) ; mod_f = ( enum memmodel ) INTVAL ( operands [ 6 ] ) ; scratch = operands [ 7 ] ; mode = GET_MODE ( mem ) ; bool use_acquire = TARGET_HAVE_LDACQ && ! ( mod_s == MEMMODEL_RELAXED || mod_s == MEMMODEL_CONSUME || mod_s == MEMMODEL_RELEASE ) ; bool use_release = TARGET_HAVE_LDACQ && ! ( mod_s == MEMMODEL_RELAXED || mod_s == MEMMODEL_CONSUME || mod_s == MEMMODEL_ACQUIRE ) ; if ( ! ( use_acquire || use_release ) ) arm_pre_atomic_barrier ( mod_s ) ; label1 = NULL ; if ( ! is_weak ) { label1 = gen_label_rtx ( ) ; emit_label ( label1 ) ; } label2 = gen_label_rtx ( ) ; arm_emit_load_exclusive ( mode , rval , mem , use_acquire ) ; cond = arm_gen_compare_reg ( NE , rval , oldval , scratch ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; emit_unlikely_jump ( gen_rtx_SET ( VOIDmode , pc_rtx , x ) ) ; arm_emit_store_exclusive ( mode , scratch , mem , newval , use_release ) ; cond = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_COMPARE ( CCmode , scratch , const0_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cond , x ) ) ; if ( ! is_weak ) { x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label1 ) , pc_rtx ) ; emit_unlikely_jump ( gen_rtx_SET ( VOIDmode , pc_rtx , x ) ) ; } if ( mod_f != MEMMODEL_RELAXED ) emit_label ( label2 ) ; if ( ! ( use_acquire || use_release ) ) arm_post_atomic_barrier ( mod_s ) ; if ( mod_f == MEMMODEL_RELAXED ) emit_label ( label2 ) ; } </s>

Split a compare and swap pattern . It is IMPLEMENTATION DEFINED whether another memory store between the load-exclusive and store-exclusive can reset the monitor from Exclusive to Open state . This means we must wait until after reload to split the pattern , lest we get a register spill in the middle of the atomic sequence .


<s> unsigned ValueEnumerator :: getGlobalBasicBlockID ( const BasicBlock * BB ) const { unsigned & Idx = GlobalBasicBlockIDs [ BB ] ; if ( Idx != 0 ) return Idx - 1 ; IncorporateFunctionInfoGlobalBBIDs ( BB -> getParent ( ) , GlobalBasicBlockIDs ) ; return getGlobalBasicBlockID ( BB ) ; } </s>

getGlobalBasicBlockID - This returns the function-specific ID for the specified basic block .


<s> const TargetRegisterClass * SICRegisterInfo :: intRegClass ( unsigned Size ) const { return & SIC :: CPURegsRegClass ; } </s>


<s> AMDGPUSubtarget & AMDGPUSubtarget :: initializeSubtargetDependencies ( StringRef GPU , StringRef FS ) { SmallString < 256 > FullFS ( "+promote-alloca,+fp64-denormals," ) ; FullFS += FS ; ParseSubtargetFeatures ( GPU , FullFS ) ; if ( getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) { FP32Denormals = false ; FP64Denormals = false ; } return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s>
void
J2AsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
)
const
{
auto
Offset
=
Fixup
.
getOffset
(
)
;
switch
(
(
unsigned
)
Fixup
.
getKind
(
)
)
{
case
J2
::
fixup_J2_PC2_12
:
applyDisplacement
<
12
,
2
>
(
Value
,
Data
.
slice
(
Offset
)
)
;
break
;
case
J2
::
fixup_J2_PC2_8
:
applyDisplacement
<
8
,
2
>
(
Value
,
Data
.
slice
(
Offset
)
)
;
break
;
case
J2
::
fixup_J2_PC4_8
:
{
applyDisplacement
<
8
,
4
>
(
Value
,
Data
.
slice
(
Offset
)
)
;
break
;
}
case
FK_Data_4
:
*
reinterpret_cast
<
uint32_t
*
>
(
Data
.
slice
(
Offset
)
.
data
(
)
)
=
Value
/
4
;
break
;
default
:
llvm_unreachable
(
"Unkown fixup!"
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static unsigned estimateStackSize ( MachineFunction & MF ) { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; const TargetRegisterInfo * RegInfo = MF . getTarget ( ) . getRegisterInfo ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; int Offset = 0 ; for ( int i = MFI -> getObjectIndexBegin ( ) ; i != 0 ; ++ i ) { int FixedOff = - MFI -> getObjectOffset ( i ) ; if ( FixedOff > Offset ) Offset = FixedOff ; } for ( unsigned i = 0 , e = MFI -> getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( MFI -> isDeadObjectIndex ( i ) ) continue ; Offset += MFI -> getObjectSize ( i ) ; unsigned Align = MFI -> getObjectAlignment ( i ) ; Offset = ( Offset + Align - 1 ) / Align * Align ; MaxAlign = std :: max ( Align , MaxAlign ) ; } if ( MFI -> adjustsStack ( ) && TFI -> hasReservedCallFrame ( MF ) ) Offset += MFI -> getMaxCallFrameSize ( ) ; unsigned StackAlign ; if ( MFI -> adjustsStack ( ) || MFI -> hasVarSizedObjects ( ) || ( RegInfo -> needsStackRealignment ( MF ) && MFI -> getObjectIndexEnd ( ) != 0 ) ) StackAlign = TFI -> getStackAlignment ( ) ; else StackAlign = TFI -> getTransientStackAlignment ( ) ; StackAlign = std :: max ( StackAlign , MaxAlign ) ; unsigned AlignMask = StackAlign - 1 ; Offset = ( Offset + AlignMask ) & ~ uint64_t ( AlignMask ) ; return ( unsigned ) Offset ; } </s>

Estimate and return the size of the stack frame .


<s>
unsigned
SystemZRegisterInfo
::
getFrameRegister
(
MachineFunction
&
MF
)
const
{
assert
(
0
&&
"What is the frame register"
)
;
return
0
;
}
</s>


<s> bool isReg ( ) const override { return Kind == k_Register ; } </s>


Implemenation of targetm.vectorize.get_mask_mode .


<s> int arc_adjust_insn_length ( rtx_insn * insn , int len , bool ) { if ( ! INSN_P ( insn ) ) return len ; if ( GET_CODE ( PATTERN ( insn ) ) == SEQUENCE ) return len ; if ( recog_memoized ( insn ) == CODE_FOR_doloop_end_i ) { rtx_insn * prev = prev_nonnote_insn ( insn ) ; return ( ( LABEL_P ( prev ) || ( TARGET_ARC600 && ( JUMP_P ( prev ) || CALL_P ( prev ) || ( NONJUMP_INSN_P ( prev ) && GET_CODE ( PATTERN ( prev ) ) == SEQUENCE ) ) ) ) ? len + 4 : len ) ; } if ( TARGET_PAD_RETURN && JUMP_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) != ADDR_VEC && GET_CODE ( PATTERN ( insn ) ) != ADDR_DIFF_VEC && get_attr_type ( insn ) == TYPE_RETURN ) { rtx_insn * prev = prev_active_insn ( insn ) ; if ( ! prev || ! ( prev = prev_active_insn ( prev ) ) || ( ( NONJUMP_INSN_P ( prev ) && GET_CODE ( PATTERN ( prev ) ) == SEQUENCE ) ? CALL_ATTR ( as_a < rtx_sequence * > ( PATTERN ( prev ) ) -> insn ( 0 ) , NON_SIBCALL ) : CALL_ATTR ( prev , NON_SIBCALL ) ) ) return len + 4 ; } if ( TARGET_ARC600 ) { rtx_insn * succ = next_real_insn ( insn ) ; if ( succ && INSN_P ( succ ) ) len += arc600_corereg_hazard ( insn , succ ) ; } extract_constrain_insn_cached ( insn ) ; return len ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LiveVariables > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < LiveVariables > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool alias ( RegisterRef RA , RegisterRef RB ) const { if ( ! isRegMaskId ( RA . Reg ) ) return ! isRegMaskId ( RB . Reg ) ? aliasRR ( RA , RB ) : aliasRM ( RA , RB ) ; return ! isRegMaskId ( RB . Reg ) ? aliasRM ( RB , RA ) : aliasMM ( RA , RB ) ; } </s>

alias - If one of the pointers is to a global that we are tracking , and the other is some random pointer , we know there can not be an alias , because the address of the global is n't taken .


<s> const MCPhysReg * TPCRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_AllRegs_SaveList ; } </s>


<s> static enum epiphany_function_type epiphany_compute_function_type ( tree decl ) { tree a ; static enum epiphany_function_type fn_type = EPIPHANY_FUNCTION_UNKNOWN ; static tree last_fn = NULL_TREE ; if ( decl == NULL_TREE ) { fn_type = EPIPHANY_FUNCTION_UNKNOWN ; last_fn = NULL_TREE ; return fn_type ; } if ( decl == last_fn && fn_type != EPIPHANY_FUNCTION_UNKNOWN ) return fn_type ; fn_type = EPIPHANY_FUNCTION_NORMAL ; for ( a = DECL_ATTRIBUTES ( decl ) ; a ; a = TREE_CHAIN ( a ) ) { tree name = TREE_PURPOSE ( a ) ; if ( name == get_identifier ( "interrupt" ) ) fn_type = EPIPHANY_FUNCTION_INTERRUPT ; } last_fn = decl ; return fn_type ; } </s>

Type of function DECL . The result is cached . To reset the cache at the end of a function , call with DECL = NULL_TREE .


<s>
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
MipsTargetLowering
::
getRegForInlineAsmConstraint
(
const
std
::
string
&
Constraint
,
MVT
VT
)
const
{
if
(
Constraint
.
size
(
)
==
1
)
{
switch
(
Constraint
[
0
]
)
{
case
'd'
:
case
'y'
:
case
'r'
:
if
(
VT
==
MVT
::
i32
||
VT
==
MVT
::
i16
||
VT
==
MVT
::
i8
)
{
if
(
Subtarget
->
inMips16Mode
(
)
)
return
std
::
make_pair
(
0U
,
&
Mips
::
CPU16RegsRegClass
)
;
return
std
::
make_pair
(
0U
,
&
Mips
::
CPURegsRegClass
)
;
}
if
(
VT
==
MVT
::
i64
&&
!
HasMips64
)
return
std
::
make_pair
(
0U
,
&
Mips
::
CPURegsRegClass
)
;
if
(
VT
==
MVT
::
i64
&&
HasMips64
)
return
std
::
make_pair
(
0U
,
&
Mips
::
CPU64RegsRegClass
)
;
return
std
::
make_pair
(
0u
,
static_cast
<
const
TargetRegisterClass
*
>
(
0
)
)
;
case
'f'
:
if
(
VT
==
MVT
::
f32
)
return
std
::
make_pair
(
0U
,
&
Mips
::
FGR32RegClass
)
;
if
(
(
VT
==
MVT
::
f64
)
&&
(
!
Subtarget
->
isSingleFloat
(
)
)
)
{
if
(
Subtarget
->
isFP64bit
(
)
)
return
std
::
make_pair
(
0U
,
&
Mips
::
FGR64RegClass
)
;
return
std
::
make_pair
(
0U
,
&
Mips
::
AFGR64RegClass
)
;
}
break
;
case
'c'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
(
unsigned
)
Mips
::
T9
,
&
Mips
::
CPURegsRegClass
)
;
assert
(
VT
==
MVT
::
i64
&&
"Unexpected type."
)
;
return
std
::
make_pair
(
(
unsigned
)
Mips
::
T9_64
,
&
Mips
::
CPU64RegsRegClass
)
;
case
'l'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
(
unsigned
)
Mips
::
LO
,
&
Mips
::
LORegsRegClass
)
;
return
std
::
make_pair
(
(
unsigned
)
Mips
::
LO64
,
&
Mips
::
LORegs64RegClass
)
;
case
'x'
:
return
std
::
make_pair
(
0u
,
static_cast
<
const
TargetRegisterClass
*
>
(
0
)
)
;
}
}
return
TargetLowering
::
getRegForInlineAsmConstraint
(
Constraint
,
VT
)
;
}
</s>

Given a physical register constraint ( e.g .


<s> static void arc_reorg_loops ( void ) { reorg_loops ( true , & arc_doloop_hooks ) ; } </s>

Run from machine_dependent_reorg , this pass looks for doloop_end insns and tries to rewrite the RTL of these loops so that proper Blackfin hardware loops are generated .


<s> static reg_class_t bfin_secondary_reload ( bool in_p , rtx x , reg_class_t rclass_i , machine_mode mode , secondary_reload_info * sri ) { enum reg_class default_class = GET_MODE_SIZE ( mode ) >= 4 ? DPREGS : DREGS ; enum reg_class x_class = NO_REGS ; enum rtx_code code = GET_CODE ( x ) ; enum reg_class rclass = ( enum reg_class ) rclass_i ; if ( code == SUBREG ) x = SUBREG_REG ( x ) , code = GET_CODE ( x ) ; if ( REG_P ( x ) ) { int regno = REGNO ( x ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) regno = reg_renumber [ regno ] ; if ( regno == - 1 ) code = MEM ; else x_class = REGNO_REG_CLASS ( regno ) ; } if ( fp_plus_const_operand ( x , mode ) ) { rtx op2 = XEXP ( x , 1 ) ; int large_constant_p = ! satisfies_constraint_Ks7 ( op2 ) ; if ( rclass == PREGS || rclass == PREGS_CLOBBERED ) return NO_REGS ; if ( ( rclass == DREGS || rclass == DPREGS ) && ! large_constant_p ) return NO_REGS ; sri -> icode = CODE_FOR_reload_insi ; return NO_REGS ; } if ( x_class == AREGS || x_class == EVEN_AREGS || x_class == ODD_AREGS ) return ( rclass == DREGS || rclass == AREGS || rclass == EVEN_AREGS || rclass == ODD_AREGS ? NO_REGS : DREGS ) ; if ( rclass == AREGS || rclass == EVEN_AREGS || rclass == ODD_AREGS ) { if ( code == MEM ) { sri -> icode = in_p ? CODE_FOR_reload_inpdi : CODE_FOR_reload_outpdi ; return NO_REGS ; } if ( x != const0_rtx && x_class != DREGS ) { return DREGS ; } else return NO_REGS ; } if ( rclass == CCREGS && x_class != DREGS ) return DREGS ; if ( x_class == CCREGS && rclass != DREGS ) return DREGS ; if ( code == MEM ) if ( ! reg_class_subset_p ( rclass , default_class ) ) return default_class ; return NO_REGS ; } </s>

Inform reload about cases where moving X with a mode MODE to a register in RCLASS requires an extra scratch register . Return the class needed for the scratch register .


<s>
static
void
mips_print_float_branch_condition
(
FILE
*
file
,
enum
rtx_code
code
,
int
letter
)
{
switch
(
code
)
{
case
EQ
:
if
(
ISA_HAS_CCF
)
fputs
(
"c1eqz"
,
file
)
;
else
fputs
(
"c1f"
,
file
)
;
break
;
case
NE
:
if
(
ISA_HAS_CCF
)
fputs
(
"c1nez"
,
file
)
;
else
fputs
(
"c1t"
,
file
)
;
break
;
default
:
output_operand_lossage
(
"'%%%c' is not a valid operand prefix"
,
letter
)
;
break
;
}
}
</s>


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , DebugLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { if ( ! Subtarget -> isAAPCS_ABI ( ) || Subtarget -> isTargetDarwin ( ) ) return SDValue ( ) ; const ARMTargetLowering & TLI = * static_cast < const ARMTargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; unsigned AS = DstPtrInfo . getAddrSpace ( ) ; Type * IntPtrTy = TLI . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) , AS ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( MVT :: i32 ) ) Src = DAG . getNode ( ISD :: TRUNCATE , dl , MVT :: i32 , Src ) ; else Src = DAG . getNode ( ISD :: ZERO_EXTEND , dl , MVT :: i32 , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , 0 , TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , false , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } </s>

Emit target-specific code that performs a memset .


<s>
SDValue
TPCTargetLowering
::
PerformDAGCombine
(
SDNode
*
N
,
DAGCombinerInfo
&
DCI
)
const
{
SelectionDAG
&
DAG
=
DCI
.
DAG
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
LLVM_DEBUG
(
dbgs
(
)
<<
"Custom combining: skipping\n"
)
;
break
;
case
ISD
::
BITCAST
:
return
performBitCastCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
case
ISD
::
VECTOR_SHUFFLE
:
return
performShuffleCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
}
return
SDValue
(
)
;
}
</s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

TPC
TPC
"Custom combining: skipping\n"
ISD::BITCAST
ISD::VECTOR_SHUFFLE


<s> void AnalyzeCallResult ( const SmallVectorImpl < ISD :: InputArg > & Ins , CCAssignFn Fn , const Type * RetTy , const char * Func ) { PreAnalyzeCallResultForF128 ( Ins , RetTy , Func ) ; PreAnalyzeCallResultForVectorFloat ( Ins , RetTy ) ; CCState :: AnalyzeCallResult ( Ins , Fn ) ; OriginalArgWasFloat . clear ( ) ; OriginalArgWasF128 . clear ( ) ; OriginalArgWasFloatVector . clear ( ) ; } </s>

AnalyzeCallResult - Same as above except it 's specialized for calls which produce a single value .


runOnMachineFunction - Emit the function body .


<s> bool AMDGPULowerKernelAttributes :: doInitialization ( Module & M ) { Mod = & M ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> int arm_apply_result_size ( void ) { int size = 16 ; if ( TARGET_32BIT ) { if ( TARGET_HARD_FLOAT_ABI ) size += 32 ; if ( TARGET_IWMMXT_ABI ) size += 8 ; } return size ; } </s>

Determine the amount of memory needed to store the possible return registers of an untyped call .


<s> const M88kSubtarget * M88kTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < M88kSubtarget > ( TargetTriple , CPU , FS , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
unsigned
getReg
(
)
const
{
assert
(
Kind
==
K_Register
&&
"Invalid type access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s> static rtx frv_frame_mem ( enum machine_mode mode , rtx base , int offset ) { return gen_rtx_MEM ( mode , gen_rtx_PLUS ( Pmode , base , frv_frame_offset_rtx ( offset ) ) ) ; } </s>

Generate ( mem : MODE ( plus : Pmode BASE ( frv_frame_offset OFFSET ) ) ) ) . The prologue and epilogue uses such expressions to access the stack .


"Running spec function '%s' with %d args\n\n"

"strange device name %qs after %qs: bad character %qc"

Implement spec function ` device-specs-file麓 . Compose -specs= < specs-file-name > % s . If everything went well then argv [ 0 ] is the inflated ( absolute ) specs directory and argv [ 1 ] is a device or core name as supplied by -mmcu= * . When building GCC the path might be relative .


<s> ARM64TargetLowering :: ConstraintType ARM64TargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'z' : return C_Other ; case 'x' : case 'w' : return C_RegisterClass ; case 'Q' : return C_Memory ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s>
bool
AMDGPUCallLowering
::
lowerReturn
(
MachineIRBuilder
&
B
,
const
Value
*
Val
,
ArrayRef
<
Register
>
VRegs
)
const
{
MachineFunction
&
MF
=
B
.
getMF
(
)
;
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
SIMachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MFI
->
setIfReturnsVoid
(
!
Val
)
;
assert
(
!
Val
==
VRegs
.
empty
(
)
&&
"Return value without a vreg"
)
;
CallingConv
::
ID
CC
=
B
.
getMF
(
)
.
getFunction
(
)
.
getCallingConv
(
)
;
const
bool
IsShader
=
AMDGPU
::
isShader
(
CC
)
;
const
bool
IsWaveEnd
=
(
IsShader
&&
MFI
->
returnsVoid
(
)
)
||
AMDGPU
::
isKernel
(
CC
)
;
if
(
IsWaveEnd
)
{
B
.
buildInstr
(
AMDGPU
::
S_ENDPGM
)
.
addImm
(
0
)
;
return
true
;
}
auto
const
&
ST
=
MF
.
getSubtarget
<
GCNSubtarget
>
(
)
;
unsigned
ReturnOpc
=
IsShader
AMDGPU
::
SI_RETURN_TO_EPILOG
:
AMDGPU
::
S_SETPC_B64_return
;
auto
Ret
=
B
.
buildInstrNoInsert
(
ReturnOpc
)
;
Register
ReturnAddrVReg
;
if
(
ReturnOpc
==
AMDGPU
::
S_SETPC_B64_return
)
{
ReturnAddrVReg
=
MRI
.
createVirtualRegister
(
&
AMDGPU
::
CCR_SGPR_64RegClass
)
;
Ret
.
addUse
(
ReturnAddrVReg
)
;
}
if
(
!
lowerReturnVal
(
B
,
Val
,
VRegs
,
Ret
)
)
return
false
;
if
(
ReturnOpc
==
AMDGPU
::
S_SETPC_B64_return
)
{
const
SIRegisterInfo
*
TRI
=
ST
.
getRegisterInfo
(
)
;
Register
LiveInReturn
=
MF
.
addLiveIn
(
TRI
->
getReturnAddressReg
(
MF
)
,
&
AMDGPU
::
SGPR_64RegClass
)
;
B
.
buildCopy
(
ReturnAddrVReg
,
LiveInReturn
)
;
}
B
.
insertInstr
(
Ret
)
;
return
true
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> yaml :: MachineFunctionInfo * RISCVTargetMachine :: createDefaultFuncInfoYAML ( ) const { return new yaml :: RISCVMachineFunctionInfo ( ) ; } </s>

Allocate and return a default initialized instance of the YAML representation for the MachineFunctionInfo .


<s> static rtx avr_builtin_setjmp_frame_value ( void ) { rtx xval = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_subhi3 ( xval , virtual_stack_vars_rtx , gen_int_mode ( STARTING_FRAME_OFFSET , Pmode ) ) ) ; return xval ; } </s>

Actual start of frame is virtual_stack_vars_rtx this is offset from frame pointer by +TARGET_STARTING_FRAME_OFFSET . Using saved frame = virtual_stack_vars_rtx - TARGET_STARTING_FRAME_OFFSET avoids creating add/sub of offset in nonlocal goto and setjmp .


<s> static inline bool cris_index_p ( const_rtx x , bool strict ) { return ( REG_P ( x ) && reg_ok_for_index_p ( x , strict ) ) ; } </s>


<s> bool SIInstrInfo :: findCommutedOpIndices ( MCInstrDesc Desc , unsigned & SrcOpIdx0 , unsigned & SrcOpIdx1 ) const { if ( ! Desc . isCommutable ( ) ) return false ; unsigned Opc = Desc . getOpcode ( ) ; int Src0Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src0 ) ; if ( Src0Idx == - 1 ) return false ; int Src1Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src1 ) ; if ( Src1Idx == - 1 ) return false ; return fixCommutedOpIndices ( SrcOpIdx0 , SrcOpIdx1 , Src0Idx , Src1Idx ) ; } </s>

Returns true iff the routine could find two commutable operands in the given machine instruction .

AMDGPU SI AMDGPU::getNamedOperandIdx AMDGPU::OpName 1 AMDGPU::getNamedOperandIdx AMDGPU::OpName 1


<s>
char
*
rx_gen_move_template
(
rtx
*
operands
,
bool
is_movu
)
{
static
char
out_template
[
64
]
;
const
char
*
extension
=
TARGET_AS100_SYNTAX
".L"
:
""
;
const
char
*
src_template
;
const
char
*
dst_template
;
rtx
dest
=
operands
[
0
]
;
rtx
src
=
operands
[
1
]
;
switch
(
CONST_INT_P
(
src
)
GET_MODE
(
dest
)
:
GET_MODE
(
src
)
)
{
case
E_QImode
:
if
(
!
REG_P
(
dest
)
||
!
CONST_INT_P
(
src
)
)
extension
=
".B"
;
break
;
case
E_HImode
:
if
(
!
REG_P
(
dest
)
||
!
CONST_INT_P
(
src
)
)
extension
=
".W"
;
break
;
case
E_DFmode
:
case
E_DImode
:
case
E_SFmode
:
case
E_SImode
:
extension
=
".L"
;
break
;
case
E_VOIDmode
:
break
;
default
:
debug_rtx
(
src
)
;
gcc_unreachable
(
)
;
}
if
(
MEM_P
(
src
)
&&
rx_pid_data_operand
(
XEXP
(
src
,
0
)
)
==
PID_UNENCODED
)
{
gcc_assert
(
GET_MODE
(
src
)
!=
DImode
)
;
gcc_assert
(
GET_MODE
(
src
)
!=
DFmode
)
;
src_template
=
"(%A1 - __pid_base)[%P1]"
;
}
else
if
(
MEM_P
(
src
)
&&
rx_small_data_operand
(
XEXP
(
src
,
0
)
)
)
{
gcc_assert
(
GET_MODE
(
src
)
!=
DImode
)
;
gcc_assert
(
GET_MODE
(
src
)
!=
DFmode
)
;
src_template
=
"%%gp(%A1)[%G1]"
;
}
else
src_template
=
"%1"
;
if
(
MEM_P
(
dest
)
&&
rx_small_data_operand
(
XEXP
(
dest
,
0
)
)
)
{
gcc_assert
(
GET_MODE
(
dest
)
!=
DImode
)
;
gcc_assert
(
GET_MODE
(
dest
)
!=
DFmode
)
;
dst_template
=
"%%gp(%A0)[%G0]"
;
}
else
dst_template
=
"%0"
;
if
(
GET_MODE
(
dest
)
==
DImode
||
GET_MODE
(
dest
)
==
DFmode
)
{
gcc_assert
(
!
is_movu
)
;
if
(
REG_P
(
src
)
&&
REG_P
(
dest
)
&&
(
REGNO
(
dest
)
==
REGNO
(
src
)
+
1
)
)
sprintf
(
out_template
,
"mov.L\t%%H1, %%H0 ! mov.L\t%%1, %%0"
)
;
else
sprintf
(
out_template
,
"mov.L\t%%1, %%0 ! mov.L\t%%H1, %%H0"
)
;
}
else
sprintf
(
out_template
,
"%s%s\t%s, %s"
,
is_movu
"movu"
:
"mov"
,
extension
,
src_template
,
dst_template
)
;
return
out_template
;
}
</s>

Returns an assembler template for a move instruction .


<s> void GCNPassConfig :: addFastRegAlloc ( ) { insertPass ( & PHIEliminationID , & SILowerControlFlowID ) ; insertPass ( & TwoAddressInstructionPassID , & SIWholeQuadModeID ) ; insertPass ( & TwoAddressInstructionPassID , & SIPreAllocateWWMRegsID ) ; TargetPassConfig :: addFastRegAlloc ( ) ; } </s>

addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast register allocation .


<s> unsigned PPCFastISel :: fastEmit_i ( MVT Ty , MVT VT , unsigned Opc , uint64_t Imm ) { if ( Opc != ISD :: Constant ) return 0 ; if ( VT == MVT :: i1 && Subtarget -> useCRBits ( ) ) { unsigned ImmReg = createResultReg ( & PPC :: CRBITRCRegClass ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Imm == 0 ? PPC :: CRUNSET : PPC :: CRSET ) , ImmReg ) ; return ImmReg ; } if ( VT != MVT :: i64 && VT != MVT :: i32 && VT != MVT :: i16 && VT != MVT :: i8 && VT != MVT :: i1 ) return 0 ; const TargetRegisterClass * RC = ( ( VT == MVT :: i64 ) ? & PPC :: G8RCRegClass : & PPC :: GPRCRegClass ) ; if ( VT == MVT :: i64 ) return PPCMaterialize64BitInt ( Imm , RC ) ; else return PPCMaterialize32BitInt ( Imm , RC ) ; } </s>

This method is called by target-independent code to request that an instruction with the given type , opcode , and immediate operand be emitted .


<s> bool targetHandlesStackFrameRounding ( ) const override { return true ; } </s>

targetHandlesStackFrameRounding - Returns true if the target is responsible for rounding up the stack frame ( probably at emitPrologue time ) .


<s> int riscv_load_store_insns ( rtx mem , rtx_insn * insn ) { machine_mode mode ; bool might_split_p ; rtx set ; gcc_assert ( MEM_P ( mem ) ) ; mode = GET_MODE ( mem ) ; might_split_p = true ; if ( GET_MODE_BITSIZE ( mode ) . to_constant ( ) <= 32 ) might_split_p = false ; else if ( GET_MODE_BITSIZE ( mode ) . to_constant ( ) == 64 ) { set = single_set ( insn ) ; if ( set && ! riscv_split_64bit_move_p ( SET_DEST ( set ) , SET_SRC ( set ) ) ) might_split_p = false ; } return riscv_address_insns ( XEXP ( mem , 0 ) , mode , might_split_p ) ; } </s>

Return the number of instructions needed to implement INSN , given that it loads from or stores to MEM .


<s> unsigned getMaxCallFrameSize ( ) const { return MaxCallFrameSize ; } </s>

Return the maximum size of a call frame that must be allocated for an outgoing function call .


<s>
unsigned
ARCInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"Code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
getLastNonDebugInstr
(
)
;
if
(
I
==
MBB
.
end
(
)
)
return
0
;
if
(
!
isUncondBranchOpcode
(
I
->
getOpcode
(
)
)
&&
!
isCondBranchOpcode
(
I
->
getOpcode
(
)
)
)
return
0
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
if
(
I
==
MBB
.
begin
(
)
)
return
1
;
I
;
if
(
!
isCondBranchOpcode
(
I
->
getOpcode
(
)
)
)
return
1
;
I
->
eraseFromParent
(
)
;
return
2
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s> static int tilepro_sched_adjust_cost ( rtx_insn * insn , int dep_type , rtx_insn * dep_insn , int cost , unsigned int ) { if ( CALL_P ( insn ) && dep_type == REG_DEP_TRUE ) { rtx target = get_jump_target ( insn ) ; if ( ! REG_P ( target ) || ! set_of ( target , dep_insn ) ) return 0 ; } return cost ; } </s>


<s>
void
BPFMIPreEmitPeephole
::
initialize
(
MachineFunction
&
MFParm
)
{
MF
=
&
MFParm
;
TRI
=
MF
->
getSubtarget
<
BPFSubtarget
>
(
)
.
getRegisterInfo
(
)
;
DEBUG
(
dbgs
(
)
<<
"*** BPF PreEmit peephole pass ***\n\n"
)
;
}
</s>

Initialize the strategy after building the DAG for a new region .

BPF
BPF
BPF
"*** BPF PreEmit peephole pass ***\n\n"


<s> bool SILowerControlFlow :: runOnMachineFunction ( MachineFunction & MF ) { const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; LIS = getAnalysisIfAvailable < LiveIntervals > ( ) ; MRI = & MF . getRegInfo ( ) ; BoolRC = TRI -> getBoolRC ( ) ; InsertKillCleanups = MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: AMDGPU_PS ; if ( ST . isWave32 ( ) ) { AndOpc = AMDGPU :: S_AND_B32 ; OrOpc = AMDGPU :: S_OR_B32 ; XorOpc = AMDGPU :: S_XOR_B32 ; MovTermOpc = AMDGPU :: S_MOV_B32_term ; Andn2TermOpc = AMDGPU :: S_ANDN2_B32_term ; XorTermrOpc = AMDGPU :: S_XOR_B32_term ; OrTermrOpc = AMDGPU :: S_OR_B32_term ; OrSaveExecOpc = AMDGPU :: S_OR_SAVEEXEC_B32 ; Exec = AMDGPU :: EXEC_LO ; } else { AndOpc = AMDGPU :: S_AND_B64 ; OrOpc = AMDGPU :: S_OR_B64 ; XorOpc = AMDGPU :: S_XOR_B64 ; MovTermOpc = AMDGPU :: S_MOV_B64_term ; Andn2TermOpc = AMDGPU :: S_ANDN2_B64_term ; XorTermrOpc = AMDGPU :: S_XOR_B64_term ; OrTermrOpc = AMDGPU :: S_OR_B64_term ; OrSaveExecOpc = AMDGPU :: S_OR_SAVEEXEC_B64 ; Exec = AMDGPU :: EXEC ; } SmallVector < MachineInstr * , 32 > Worklist ; MachineFunction :: iterator NextBB ; for ( MachineFunction :: iterator BI = MF . begin ( ) ; BI != MF . end ( ) ; BI = NextBB ) { NextBB = std :: next ( BI ) ; MachineBasicBlock * MBB = & * BI ; MachineBasicBlock :: iterator I , E , Next ; E = MBB -> end ( ) ; for ( I = MBB -> begin ( ) ; I != E ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; MachineBasicBlock * SplitMBB = MBB ; switch ( MI . getOpcode ( ) ) { case AMDGPU :: SI_IF : SplitMBB = process ( MI ) ; break ; case AMDGPU :: SI_ELSE : case AMDGPU :: SI_IF_BREAK : case AMDGPU :: SI_LOOP : case AMDGPU :: SI_END_CF : if ( InsertKillCleanups ) Worklist . push_back ( & MI ) ; else SplitMBB = process ( MI ) ; break ; default : break ; } if ( SplitMBB != MBB ) { MBB = Next -> getParent ( ) ; E = MBB -> end ( ) ; } } } for ( MachineInstr * MI : Worklist ) process ( * MI ) ; optimizeEndCf ( ) ; LoweredEndCf . clear ( ) ; LoweredIf . clear ( ) ; NeedsKillCleanup . clear ( ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s>
bool
F2003fInstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
!
isUnpredicatedTerminator
(
*
I
)
)
break
;
if
(
!
I
->
isBranch
(
)
)
return
true
;
if
(
I
->
isIndirectBranch
(
)
)
return
true
;
if
(
I
->
getOpcode
(
)
==
F2003f
::
KRZx
)
{
if
(
!
AllowModify
)
{
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
continue
;
}
while
(
std
::
next
(
I
)
!=
MBB
.
end
(
)
)
std
::
next
(
I
)
->
eraseFromParent
(
)
;
Cond
.
clear
(
)
;
FBB
=
nullptr
;
if
(
MBB
.
isLayoutSuccessor
(
I
->
getOperand
(
0
)
.
getMBB
(
)
)
)
{
TBB
=
nullptr
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
continue
;
}
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
continue
;
}
assert
(
getMalkrzFromFiMalkrz
(
I
->
getOpcode
(
)
)
==
F2003f
::
MALKRZx
&&
"Invalid conditional branch"
)
;
if
(
Cond
.
empty
(
)
)
{
FBB
=
TBB
;
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
I
->
getOpcode
(
)
)
)
;
for
(
unsigned
i
=
1
;
i
<
I
->
getNumOperands
(
)
;
i
++
)
{
Cond
.
push_back
(
I
->
getOperand
(
i
)
)
;
}
continue
;
}
return
true
;
}
return
false
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"AMDGPU Annotate Uniform Values"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void AVRPassConfig :: addPreEmitPass ( ) { addPass ( & BranchRelaxationPassID ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static MachineInstr * findLoopInstr ( MachineBasicBlock * BB , int EndLoopOp , SmallPtrSet < MachineBasicBlock * , 8 > & Visited ) { int LOOPi ; int LOOPr ; if ( EndLoopOp == Hexagon :: ENDLOOP0 ) { LOOPi = Hexagon :: J2_loop0i ; LOOPr = Hexagon :: J2_loop0r ; } else { LOOPi = Hexagon :: J2_loop1i ; LOOPr = Hexagon :: J2_loop1r ; } for ( MachineBasicBlock :: pred_iterator PB = BB -> pred_begin ( ) , PE = BB -> pred_end ( ) ; PB != PE ; ++ PB ) { if ( ! Visited . insert ( * PB ) . second ) continue ; if ( * PB == BB ) continue ; for ( MachineBasicBlock :: reverse_instr_iterator I = ( * PB ) -> instr_rbegin ( ) , E = ( * PB ) -> instr_rend ( ) ; I != E ; ++ I ) { int Opc = I -> getOpcode ( ) ; if ( Opc == LOOPi || Opc == LOOPr ) return & * I ; if ( Opc == EndLoopOp ) return 0 ; } MachineInstr * loop = findLoopInstr ( * PB , EndLoopOp , Visited ) ; if ( loop ) return loop ; } return 0 ; } </s>

Find the hardware loop instruction used to set-up the specified loop .


<s> void Initialize ( MCContext & ctx , const TargetMachine & TM ) override { TargetLoweringObjectFile :: Initialize ( ctx , TM ) ; TextSection = new TGSISection ( MCSection :: SV_ELF , SectionKind :: getText ( ) ) ; DataSection = new TGSISection ( MCSection :: SV_ELF , SectionKind :: getData ( ) ) ; BSSSection = new TGSISection ( MCSection :: SV_ELF , SectionKind :: getBSS ( ) ) ; ReadOnlySection = new TGSISection ( MCSection :: SV_ELF , SectionKind :: getReadOnly ( ) ) ; StaticCtorSection = new TGSISection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; StaticDtorSection = new TGSISection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; LSDASection = new TGSISection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; EHFrameSection = new TGSISection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfAbbrevSection = new TGSISection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfInfoSection = new TGSISection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfLineSection = new TGSISection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfFrameSection = new TGSISection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfPubTypesSection = new TGSISection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfDebugInlineSection = new TGSISection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfStrSection = new TGSISection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfLocSection = new TGSISection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfARangesSection = new TGSISection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfRangesSection = new TGSISection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; } </s>

This method must be called before any actual lowering is done .

TGSI TGSI TGSI TGSI TGSI TGSI TGSI TGSI TGSI TGSI TGSI TGSI TGSI TGSI TGSI TGSI TGSI TGSI TGSI


"Should only have an r11 thunk on 64-bit targets"


<s> std :: pair < unsigned , const TargetRegisterClass * > NVPTXTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'c' : return std :: make_pair ( 0U , & NVPTX :: Int8RegsRegClass ) ; case 'h' : return std :: make_pair ( 0U , & NVPTX :: Int16RegsRegClass ) ; case 'r' : return std :: make_pair ( 0U , & NVPTX :: Int32RegsRegClass ) ; case 'l' : case 'N' : return std :: make_pair ( 0U , & NVPTX :: Int64RegsRegClass ) ; case 'f' : return std :: make_pair ( 0U , & NVPTX :: Float32RegsRegClass ) ; case 'd' : return std :: make_pair ( 0U , & NVPTX :: Float64RegsRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> inline bool isShiftedMask ( uint64_t I , uint64_t & Width , uint64_t & Offset ) { if ( ! isShiftedMask_64 ( I ) ) return false ; Width = countPopulation ( I ) ; Offset = countTrailingZeros ( I ) ; return true ; } </s>

Return true if this APInt value contains a non-empty sequence of ones with the remainder zero .


<s> bool nds32_long_call_p ( rtx symbol ) { return TARGET_CMODEL_LARGE ; } </s>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { AArch64MachineFunctionInfo * MFI = MF . getInfo < AArch64MachineFunctionInfo > ( ) ; if ( MFI -> getNumLocalDynamicTLSAccesses ( ) < 2 ) { return false ; } MachineDominatorTree * DT = & getAnalysis < MachineDominatorTree > ( ) ; return VisitNode ( DT -> getRootNode ( ) , 0 ) ; } </s>


"Unexpected operand in reassociable instruction"

Return true when \P Inst has reassociable operands in the same \P MBB .


<s> bool SIInstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { assert ( Cond . size ( ) == 2 ) ; Cond [ 0 ] . setImm ( - Cond [ 0 ] . getImm ( ) ) ; return false ; } </s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> void CSKYFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


<s>
const
char
*
nds32_output_stack_pop
(
rtx
par_rtx
ATTRIBUTE_UNUSED
)
{
char
pattern
[
100
]
;
rtx
operands
[
3
]
;
int
rb_callee_saved
=
cfun
->
machine
->
callee_saved_first_gpr_regno
;
int
re_callee_saved
=
cfun
->
machine
->
callee_saved_last_gpr_regno
;
if
(
TARGET_V3PUSH
&&
!
nds32_isr_function_p
(
current_function_decl
)
&&
(
cfun
->
machine
->
va_args_size
==
0
)
)
{
int
sp_adjust
;
operands
[
0
]
=
gen_rtx_REG
(
SImode
,
re_callee_saved
)
;
sp_adjust
=
cfun
->
machine
->
local_size
+
cfun
->
machine
->
out_args_size
+
cfun
->
machine
->
callee_saved_area_gpr_padding_bytes
;
if
(
satisfies_constraint_Iu08
(
GEN_INT
(
sp_adjust
)
)
&&
NDS32_DOUBLE_WORD_ALIGN_P
(
sp_adjust
)
&&
!
cfun
->
calls_alloca
)
operands
[
1
]
=
GEN_INT
(
sp_adjust
)
;
else
operands
[
1
]
=
GEN_INT
(
0
)
;
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"pop25\t%%0, %%1"
)
;
}
else
{
int
pop_en4_only_p
=
0
;
operands
[
0
]
=
gen_rtx_REG
(
SImode
,
rb_callee_saved
)
;
operands
[
1
]
=
gen_rtx_REG
(
SImode
,
re_callee_saved
)
;
if
(
!
cfun
->
machine
->
fp_size
&&
!
cfun
->
machine
->
gp_size
&&
!
cfun
->
machine
->
lp_size
&&
REGNO
(
operands
[
0
]
)
==
SP_REGNUM
&&
REGNO
(
operands
[
1
]
)
==
SP_REGNUM
)
{
return
""
;
}
else
{
if
(
REGNO
(
operands
[
0
]
)
==
SP_REGNUM
&&
REGNO
(
operands
[
1
]
)
==
SP_REGNUM
)
pop_en4_only_p
=
1
;
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"pop.s\t%s{%s%s%s }"
,
pop_en4_only_p
""
:
"%0, %1, "
,
cfun
->
machine
->
fp_size
" $fp"
:
""
,
cfun
->
machine
->
gp_size
" $gp"
:
""
,
cfun
->
machine
->
lp_size
" $lp"
:
""
)
;
}
}
output_asm_insn
(
pattern
,
operands
)
;
return
""
;
}
</s>

Function to output stack pop operation . We need to deal with normal stack pop multiple or stack v3pop .


<s> static HOST_WIDE_INT ix86_GOT_alias_set ( void ) { static HOST_WIDE_INT set = - 1 ; if ( set == - 1 ) set = new_alias_set ( ) ; return set ; } </s>

Return an unique alias set for the GOT .


<s> PreservedAnalyses NVVMReflectPass :: run ( Function & F , FunctionAnalysisManager & AM ) { return runNVVMReflect ( F , SmVersion ) ? PreservedAnalyses :: none ( ) : PreservedAnalyses :: all ( ) ; } </s>

Run the analysis pass over a function and produce a dominator tree .


<s> static MCAsmInfo * createMCAsmInfo ( const MCRegisterInfo & , const Triple & TT ) { return new JVMMCAsmInfo ( TT ) ; } </s>

createMCAsmInfo - Create a MCAsmInfo implementation for the specified target triple .


<s>
static
void
rs6000_darwin_file_start
(
void
)
{
static
const
struct
{
const
char
*
arg
;
const
char
*
name
;
HOST_WIDE_INT
if_set
;
}
mapping
[
]
=
{
{
"ppc64"
,
"ppc64"
,
MASK_64BIT
}
,
{
"970"
,
"ppc970"
,
OPTION_MASK_PPC_GPOPT
|
OPTION_MASK_MFCRF
\
|
MASK_POWERPC64
}
,
{
"power4"
,
"ppc970"
,
0
}
,
{
"G5"
,
"ppc970"
,
0
}
,
{
"7450"
,
"ppc7450"
,
0
}
,
{
"7400"
,
"ppc7400"
,
OPTION_MASK_ALTIVEC
}
,
{
"G4"
,
"ppc7400"
,
0
}
,
{
"750"
,
"ppc750"
,
0
}
,
{
"740"
,
"ppc750"
,
0
}
,
{
"G3"
,
"ppc750"
,
0
}
,
{
"604e"
,
"ppc604e"
,
0
}
,
{
"604"
,
"ppc604"
,
0
}
,
{
"603e"
,
"ppc603"
,
0
}
,
{
"603"
,
"ppc603"
,
0
}
,
{
"601"
,
"ppc601"
,
0
}
,
{
,
"ppc"
,
0
}
}
;
const
char
*
cpu_id
=
""
;
size_t
i
;
rs6000_file_start
(
)
;
darwin_file_start
(
)
;
if
(
rs6000_default_cpu
!=
0
&&
rs6000_default_cpu
[
0
]
!=
'\0'
)
cpu_id
=
rs6000_default_cpu
;
if
(
OPTION_SET_P
(
rs6000_cpu_index
)
)
cpu_id
=
processor_target_table
[
rs6000_cpu_index
]
.
name
;
i
=
0
;
while
(
mapping
[
i
]
.
arg
!=
&&
strcmp
(
mapping
[
i
]
.
arg
,
cpu_id
)
!=
0
&&
(
mapping
[
i
]
.
if_set
&
rs6000_isa_flags
)
==
0
)
i
++
;
fprintf
(
asm_out_file
,
"\t.machine %s\n"
,
mapping
[
i
]
.
name
)
;
}
</s>

Output a .machine directive for the Darwin assembler , and call the generic start_file routine .


<s> static double calc_defect ( double x , int constant , int factor ) { double y0 = ( constant - ( int ) floor ( ( x * factor * 64. ) ) ) / 16384. ; double y1 = 2 * y0 - y0 * y0 * ( x + BIAS / ( 1. * ( 1LL << 30 ) ) ) ; double y2d0 , y2d ; int y2d1 ; double d , d2 ; y1 = floor ( y1 * ( 1024 * 1024 * 1024 ) ) / ( 1024 * 1024 * 1024 ) ; d = y1 - 1 / x ; if ( d > max_defect ) { max_defect = d ; max_defect_x = x ; } if ( d < min_defect ) { min_defect = d ; min_defect_x = x ; } y2d0 = floor ( y1 * x * ( 1LL << 60 - 16 ) ) ; y2d1 = ( int ) ( long long ) y2d0 ; y2d = - floor ( ( y1 - y0 / ( 1 << 30 - 14 ) ) * y2d1 ) / ( 1LL << 44 ) ; d2 = y1 + y2d - 1 / x ; if ( d2 > max_defect2 ) { max_defect2 = d2 ; max_defect2_x = x ; } if ( d2 < min_defect2 ) { min_defect2 = d2 ; min_defect2_x = x ; } note_defect3 ( ( 1 << CUTOFF_BITS ) - 1 , d2 , y2d , x ) ; note_defect3 ( 1 << CUTOFF_BITS , d2 , y2d , x ) ; note_defect3 ( ( 1U << 31 ) - ( 1 << CUTOFF_BITS ) , d2 , y2d , x ) ; note_defect3 ( ( 1U << 31 ) - 1 , d2 , y2d , x ) ; note_defect3 ( - 1 , d2 , y2d , x ) ; note_defect3 ( - ( 1 << CUTOFF_BITS ) , d2 , y2d , x ) ; note_defect3 ( ( 1U << 31 ) - ( 1 << CUTOFF_BITS ) + 1 , d2 , y2d , x ) ; note_defect3 ( - ( 1U << 31 ) , d2 , y2d , x ) ; return d ; } </s>


<s> bool ARMTargetLowering :: isFNegFree ( EVT VT ) const { if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : break ; case MVT :: f16 : return Subtarget -> hasFullFP16 ( ) ; } return false ; } </s>

Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation .