<s> static void tilepro_fixup_pcrel_references ( void ) { rtx_insn * insn , * next_insn ; bool same_section_as_entry = true ; for ( insn = get_insns ( ) ; insn ; insn = next_insn ) { next_insn = NEXT_INSN ( insn ) ; if ( NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_SWITCH_TEXT_SECTIONS ) { same_section_as_entry = ! same_section_as_entry ; continue ; } if ( same_section_as_entry ) continue ; if ( ! ( INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER ) ) continue ; if ( match_addli_pcrel ( insn ) ) replace_addli_pcrel ( insn ) ; else if ( match_auli_pcrel ( insn ) ) replace_auli_pcrel ( insn ) ; } } </s>

We generate PC relative SYMBOL_REFs as an optimization , to avoid going through the GOT when the symbol is local to the compilation unit . But such a symbol requires that the common text_label that we generate at the beginning of the function be in the same section as the reference to the SYMBOL_REF . This may not be true if we generate hot/cold sections . This function looks for such cases and replaces such references with the longer sequence going through the GOT . We expect one of the following two instruction sequences : addli tmp1 , txt_label_reg , lo16 ( sym - txt_label ) auli tmp2 , tmp1 , ha16 ( sym - txt_label ) auli tmp1 , txt_label_reg , ha16 ( sym - txt_label ) addli tmp2 , tmp1 , lo16 ( sym - txt_label ) If we 're compiling -fpic , we replace the first instruction with nothing , and the second instruction with : addli tmp2 , got_rtx , got ( sym ) lw tmp2 , tmp2 If we 're compiling -fPIC , we replace the first instruction with : auli tmp1 , got_rtx , got_ha16 ( sym ) and the second instruction with : addli tmp2 , tmp1 , got_lo16 ( sym ) lw tmp2 , tmp2 Note that we 're careful to disturb the instruction sequence as little as possible , since it 's very late in the compilation process .


<s>
StringRef
getPassName
(
)
const
override
{
return
"AMDGPU Kernel Attributes"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool NVPTXLowerArgs :: runOnFunction ( Function & F ) { return isKernelFunction ( F ) ? runOnKernelFunction ( F ) : runOnDeviceFunction ( F ) ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static bool rs6000_slow_unaligned_access ( machine_mode mode , unsigned int align ) { return ( STRICT_ALIGNMENT || ( ! TARGET_EFFICIENT_UNALIGNED_VSX && ( ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( mode ) && align < 32 ) || ( ( VECTOR_MODE_P ( mode ) || FLOAT128_VECTOR_P ( mode ) ) && ( int ) align < VECTOR_ALIGN ( mode ) ) ) ) ) ; } </s>

Implement TARGET_SLOW_UNALIGNED_ACCESS . Altivec vector memory instructions simply ignore the low bits ; VSX memory instructions are aligned to 4 or 8 bytes .


<s> DecodeStatus TeeRISCDisassembler :: getInstruction ( MCInst & instr , uint64_t & Size , const MemoryObject & Region , uint64_t Address , raw_ostream & vStream , raw_ostream & cStream ) const { uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Region , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTableTeeRISC32 , instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s> void SystemZFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; bool BackChain = MF . getFunction ( ) . hasFnAttribute ( "backchain" ) ; if ( ! usePackedStack ( MF ) || BackChain ) getOrCreateFramePointerSaveIndex ( MF ) ; uint64_t StackSize = ( MFFrame . estimateStackSize ( MF ) + SystemZMC :: CallFrameSize ) ; int64_t MaxArgOffset = 0 ; for ( int I = MFFrame . getObjectIndexBegin ( ) ; I != 0 ; ++ I ) if ( MFFrame . getObjectOffset ( I ) >= 0 ) { int64_t ArgOffset = MFFrame . getObjectOffset ( I ) + MFFrame . getObjectSize ( I ) ; MaxArgOffset = std :: max ( MaxArgOffset , ArgOffset ) ; } uint64_t MaxReach = StackSize + MaxArgOffset ; if ( ! isUInt < 12 > ( MaxReach ) ) { RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( 8 , Align ( 8 ) , false ) ) ; RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( 8 , Align ( 8 ) , false ) ) ; } } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < PatmosSinglePathInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool AMDGPUPropagateAttributesLate :: runOnModule ( Module & M ) { if ( ! TM ) { auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; TM = & TPC -> getTM < TargetMachine > ( ) ; } return AMDGPUPropagateAttributes ( TM , true ) . process ( M ) ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> static rtx nios2_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( mode , FIRST_RETVAL_REGNO ) ; } </s>


A get_unnamed_decl callback , used for read-only sections . PTR points to the section string variable .


<s>
bool
ARMAsmBackend
::
shouldForceRelocation
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
)
{
const
MCSymbolRefExpr
*
A
=
Target
.
getSymA
(
)
;
const
MCSymbol
*
Sym
=
A
&
A
->
getSymbol
(
)
:
nullptr
;
const
unsigned
FixupKind
=
Fixup
.
getKind
(
)
;
if
(
FixupKind
==
FK_NONE
)
return
true
;
if
(
FixupKind
==
ARM
::
fixup_arm_thumb_bl
)
{
assert
(
Sym
&&
"How did we resolve this?"
)
;
if
(
Sym
->
isExternal
(
)
)
return
true
;
}
if
(
Sym
&&
Sym
->
isELF
(
)
)
{
unsigned
Type
=
cast
<
MCSymbolELF
>
(
Sym
)
->
getType
(
)
;
if
(
(
Type
==
ELF
::
STT_FUNC
||
Type
==
ELF
::
STT_GNU_IFUNC
)
)
{
if
(
Asm
.
isThumbFunc
(
Sym
)
&&
(
FixupKind
==
ARM
::
fixup_arm_uncondbranch
)
)
return
true
;
if
(
!
Asm
.
isThumbFunc
(
Sym
)
&&
(
FixupKind
==
ARM
::
fixup_arm_thumb_br
||
FixupKind
==
ARM
::
fixup_arm_thumb_bl
||
FixupKind
==
ARM
::
fixup_t2_condbranch
||
FixupKind
==
ARM
::
fixup_t2_uncondbranch
)
)
return
true
;
}
}
if
(
A
&&
(
FixupKind
==
ARM
::
fixup_arm_thumb_blx
||
FixupKind
==
ARM
::
fixup_arm_blx
||
FixupKind
==
ARM
::
fixup_arm_uncondbl
||
FixupKind
==
ARM
::
fixup_arm_condbl
)
)
return
true
;
return
false
;
}
</s>

Hook to check if a relocation is needed for some target specific reason .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> static int pa_arg_partial_bytes ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; unsigned int max_arg_words = 8 ; unsigned int offset = 0 ; int arg_size ; if ( ! TARGET_64BIT ) return 0 ; arg_size = pa_function_arg_size ( arg . mode , arg . type ) ; if ( arg_size > 1 && ( cum -> words & 1 ) ) offset = 1 ; if ( cum -> words + offset + arg_size <= max_arg_words ) return 0 ; else if ( cum -> words + offset >= max_arg_words ) return 0 ; else return ( max_arg_words - cum -> words - offset ) * UNITS_PER_WORD ; } </s>

If this arg would be passed totally in registers or totally on the stack , then this routine should return zero .


<s>
bool
BPFAsmPrinter
::
doInitialization
(
Module
&
M
)
{
AsmPrinter
::
doInitialization
(
M
)
;
if
(
MAI
->
doesSupportDebugInformation
(
)
&&
!
empty
(
M
.
debug_compile_units
(
)
)
)
{
Handlers
.
emplace_back
(
llvm
::
make_unique
<
BTFDebug
>
(
this
)
,
"emit"
,
"Debug Info Emission"
,
"BTF"
,
"BTF Emission"
)
;
}
return
false
;
}
</s>

Set up the AsmPrinter when we are working on a new module .

BPF
BPF
"emit"
"Debug Info Emission"
"BTF"
"BTF Emission"


<s> bool CJGPassConfig :: addInstSelector ( ) { addPass ( createCJGISelDag ( getCJGTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s>
void
bb_sese
::
append
(
bb_sese
*
child
)
{
if
(
int
len
=
child
->
brackets
.
length
(
)
)
{
int
ix
;
if
(
dump_file
)
{
for
(
ix
=
0
;
ix
<
len
;
ix
++
)
{
const
pseudo_node_t
&
pseudo
=
child
->
brackets
[
ix
]
.
back
;
fprintf
(
dump_file
,
"Appending (%d)'s backedge %d:%+d\n"
,
child
->
node
,
pseudo
.
first
pseudo
.
first
->
index
:
0
,
pseudo
.
second
)
;
}
}
if
(
!
brackets
.
length
(
)
)
std
::
swap
(
brackets
,
child
->
brackets
)
;
else
{
brackets
.
reserve
(
len
)
;
for
(
ix
=
0
;
ix
<
len
;
ix
++
)
brackets
.
quick_push
(
child
->
brackets
[
ix
]
)
;
}
}
}
</s>

Destructively append CHILD 's brackets .


"attribute %<target%> argument not a string"

"invalid fpu for target attribute or pragma %qs"

"auto fpu selection not currently permitted here"

"invalid architecture for target attribute or pragma %qs"

"unknown target attribute or pragma %qs"

Inner function to process the attribute ( ( target ( ... ) ) ) , take an argument and set the current options from the argument . If we have a list , recursively go over the list .


<s> static void rs6000_set_default_type_attributes ( tree type ) { if ( rs6000_default_long_calls && ( TREE_CODE ( type ) == FUNCTION_TYPE || TREE_CODE ( type ) == METHOD_TYPE ) ) TYPE_ATTRIBUTES ( type ) = tree_cons ( get_identifier ( "longcall" ) , NULL_TREE , TYPE_ATTRIBUTES ( type ) ) ; } </s>

Set longcall attributes on all functions declared when rs6000_default_long_calls is true .


<s> static void rs6000_function_specific_save ( struct cl_target_option * ptr , struct gcc_options * opts , struct gcc_options * ) { ptr -> x_rs6000_isa_flags = opts -> x_rs6000_isa_flags ; ptr -> x_rs6000_isa_flags_explicit = opts -> x_rs6000_isa_flags_explicit ; } </s>


<s>
bool
WinEHStatePass
::
runOnFunction
(
Function
&
F
)
{
StringRef
WinEHParentName
=
F
.
getFnAttribute
(
"wineh-parent"
)
.
getValueAsString
(
)
;
if
(
WinEHParentName
!=
F
.
getName
(
)
&&
!
WinEHParentName
.
empty
(
)
)
return
false
;
if
(
!
F
.
hasPersonalityFn
(
)
)
return
false
;
PersonalityFn
=
dyn_cast
<
Function
>
(
F
.
getPersonalityFn
(
)
->
stripPointerCasts
(
)
)
;
if
(
!
PersonalityFn
)
return
false
;
Personality
=
classifyEHPersonality
(
PersonalityFn
)
;
if
(
!
isFuncletEHPersonality
(
Personality
)
)
return
false
;
if
(
WinEHParentName
.
empty
(
)
)
{
bool
HasPads
=
false
;
for
(
BasicBlock
&
BB
:
F
)
{
if
(
BB
.
isEHPad
(
)
)
{
HasPads
=
true
;
break
;
}
}
if
(
!
HasPads
)
return
false
;
}
F
.
addFnAttr
(
"no-frame-pointer-elim"
,
"true"
)
;
emitExceptionRegistrationRecord
(
&
F
)
;
auto
*
MMI
=
getAnalysisIfAvailable
<
MachineModuleInfo
>
(
)
;
std
::
unique_ptr
<
WinEHFuncInfo
>
FuncInfoPtr
;
if
(
!
MMI
)
FuncInfoPtr
.
reset
(
new
WinEHFuncInfo
(
)
)
;
WinEHFuncInfo
&
FuncInfo
=
*
(
MMI
&
MMI
->
getWinEHFuncInfo
(
&
F
)
:
FuncInfoPtr
.
get
(
)
)
;
FuncInfo
.
EHRegNode
=
RegNode
;
switch
(
Personality
)
{
default
:
llvm_unreachable
(
"unexpected personality function"
)
;
case
EHPersonality
::
MSVC_CXX
:
addCXXStateStores
(
F
,
FuncInfo
)
;
break
;
case
EHPersonality
::
MSVC_X86SEH
:
addSEHStateStores
(
F
,
FuncInfo
)
;
break
;
}
PersonalityFn
=
nullptr
;
Personality
=
EHPersonality
::
Unknown
;
return
true
;
}
</s>

X86
"wineh-parent"
"no-frame-pointer-elim"
"true"
"unexpected personality function"
X86


<s> static void aarch64_emit_probe_stack_range ( HOST_WIDE_INT first , HOST_WIDE_INT size ) { rtx reg1 = gen_rtx_REG ( Pmode , PROBE_STACK_FIRST_REG ) ; gcc_assert ( ( first % ARITH_FACTOR ) == 0 ) ; if ( size <= PROBE_INTERVAL ) { const HOST_WIDE_INT base = ROUND_UP ( size , ARITH_FACTOR ) ; emit_set_insn ( reg1 , plus_constant ( Pmode , stack_pointer_rtx , - ( first + base ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , reg1 , base - size ) ) ; } else if ( size <= 4 * PROBE_INTERVAL ) { HOST_WIDE_INT i , rem ; emit_set_insn ( reg1 , plus_constant ( Pmode , stack_pointer_rtx , - ( first + PROBE_INTERVAL ) ) ) ; emit_stack_probe ( reg1 ) ; for ( i = 2 * PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) { emit_set_insn ( reg1 , plus_constant ( Pmode , reg1 , - PROBE_INTERVAL ) ) ; emit_stack_probe ( reg1 ) ; } rem = size - ( i - PROBE_INTERVAL ) ; if ( rem > 256 ) { const HOST_WIDE_INT base = ROUND_UP ( rem , ARITH_FACTOR ) ; emit_set_insn ( reg1 , plus_constant ( Pmode , reg1 , - base ) ) ; emit_stack_probe ( plus_constant ( Pmode , reg1 , base - rem ) ) ; } else emit_stack_probe ( plus_constant ( Pmode , reg1 , - rem ) ) ; } else { rtx reg2 = gen_rtx_REG ( Pmode , PROBE_STACK_SECOND_REG ) ; HOST_WIDE_INT rounded_size = size & - PROBE_INTERVAL ; emit_set_insn ( reg1 , plus_constant ( Pmode , stack_pointer_rtx , - first ) ) ; emit_set_insn ( reg2 , plus_constant ( Pmode , stack_pointer_rtx , - ( first + rounded_size ) ) ) ; emit_insn ( gen_probe_stack_range ( reg1 , reg1 , reg2 ) ) ; if ( size != rounded_size ) { HOST_WIDE_INT rem = size - rounded_size ; if ( rem > 256 ) { const HOST_WIDE_INT base = ROUND_UP ( rem , ARITH_FACTOR ) ; emit_set_insn ( reg2 , plus_constant ( Pmode , reg2 , - base ) ) ; emit_stack_probe ( plus_constant ( Pmode , reg2 , base - rem ) ) ; } else emit_stack_probe ( plus_constant ( Pmode , reg2 , - rem ) ) ; } } emit_insn ( gen_blockage ( ) ) ; } </s>

Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE , inclusive . These are offsets from the current stack pointer .


<s> static inline bool m32r_legitimate_lo_sum_addres_p ( machine_mode mode , const_rtx x , bool strict ) { if ( GET_CODE ( x ) == LO_SUM && ( mode != BLKmode && GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD ) && m32r_rtx_ok_for_base_p ( XEXP ( x , 0 ) , strict ) && CONSTANT_P ( XEXP ( x , 1 ) ) ) return true ; return false ; } </s>

For LO_SUM addresses , do not allow them if the MODE is > 1 word , since more than one instruction will be required .


<s>
bool
ARM64FrameLowering
::
hasFP
(
const
MachineFunction
&
MF
)
const
{
const
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
const
TargetRegisterInfo
*
RegInfo
=
MF
.
getTarget
(
)
.
getRegisterInfo
(
)
;
assert
(
!
RegInfo
->
needsStackRealignment
(
MF
)
&&
"No stack realignment on ARM64!"
)
;
return
(
MFI
->
hasCalls
(
)
||
MFI
->
hasVarSizedObjects
(
)
||
MFI
->
isFrameAddressTaken
(
)
)
;
}
</s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> enum aarch64_symbol_type aarch64_classify_symbolic_expression ( rtx x , enum aarch64_symbol_context context ) { rtx offset ; split_const ( x , & x , & offset ) ; return aarch64_classify_symbol ( x , offset , context ) ; } </s>

Classify the base of symbolic expression X , given that X appears in context CONTEXT .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Hexagon bit simplification"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static unsigned HOST_WIDE_INT arm_asan_shadow_offset ( void ) { return ( unsigned HOST_WIDE_INT ) 1 << 29 ; } </s>

Implement the TARGET_ASAN_SHADOW_OFFSET hook .


<s> static rtx arc_get_tp ( void ) { if ( arc_tp_regno != - 1 ) return gen_rtx_REG ( Pmode , arc_tp_regno ) ; rtx reg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_tls_load_tp_soft ( ) ) ; emit_move_insn ( reg , gen_rtx_REG ( Pmode , R0_REG ) ) ; return reg ; } </s>


<s> static int get_some_local_dynamic_name_1 ( rtx * px , void * data ATTRIBUTE_UNUSED ) { rtx x = * px ; if ( x && GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_DYNAMIC ) { cfun -> machine -> some_ld_name = XSTR ( x , 0 ) ; return 1 ; } return 0 ; } </s>


"MSP430 DAG->DAG Pattern Instruction Selection"


<s>
const
char
*
output_move_double
(
rtx
*
operands
)
{
enum
machine_mode
mode
=
GET_MODE
(
operands
[
0
]
)
;
rtx
dst
=
operands
[
0
]
;
rtx
src
=
operands
[
1
]
;
if
(
register_operand
(
dst
,
mode
)
&&
register_operand
(
src
,
mode
)
)
{
if
(
REGNO
(
src
)
+
1
==
REGNO
(
dst
)
)
return
"mov %R1,%R0\n\tmov %1,%0"
;
else
return
"mov %1,%0\n\tmov %R1,%R0"
;
}
if
(
GET_CODE
(
dst
)
==
MEM
&&
(
(
GET_CODE
(
src
)
==
CONST_INT
&&
INTVAL
(
src
)
==
0
)
||
(
GET_CODE
(
src
)
==
CONST_DOUBLE
&&
CONST_DOUBLE_OK_FOR_G
(
src
)
)
)
)
return
"st.w %.,%0\n\tst.w %.,%R0"
;
if
(
GET_CODE
(
src
)
==
CONST_INT
||
GET_CODE
(
src
)
==
CONST_DOUBLE
)
{
HOST_WIDE_INT
high_low
[
2
]
;
int
i
;
rtx
xop
[
10
]
;
if
(
GET_CODE
(
src
)
==
CONST_DOUBLE
)
const_double_split
(
src
,
&
high_low
[
1
]
,
&
high_low
[
0
]
)
;
else
{
high_low
[
0
]
=
INTVAL
(
src
)
;
high_low
[
1
]
=
(
INTVAL
(
src
)
>=
0
)
0
:
1
;
}
for
(
i
=
0
;
i
<
2
;
i
++
)
{
xop
[
0
]
=
gen_rtx_REG
(
SImode
,
REGNO
(
dst
)
+
i
)
;
xop
[
1
]
=
GEN_INT
(
high_low
[
i
]
)
;
output_asm_insn
(
output_move_single
(
xop
)
,
xop
)
;
}
return
""
;
}
if
(
GET_CODE
(
src
)
==
MEM
)
{
int
ptrreg
=
1
;
int
dreg
=
REGNO
(
dst
)
;
rtx
inside
=
XEXP
(
src
,
0
)
;
if
(
GET_CODE
(
inside
)
==
REG
)
ptrreg
=
REGNO
(
inside
)
;
else
if
(
GET_CODE
(
inside
)
==
SUBREG
)
ptrreg
=
subreg_regno
(
inside
)
;
else
if
(
GET_CODE
(
inside
)
==
PLUS
)
ptrreg
=
REGNO
(
XEXP
(
inside
,
0
)
)
;
else
if
(
GET_CODE
(
inside
)
==
LO_SUM
)
ptrreg
=
REGNO
(
XEXP
(
inside
,
0
)
)
;
if
(
dreg
==
ptrreg
)
return
"ld.w %R1,%R0\n\tld.w %1,%0"
;
}
if
(
GET_CODE
(
src
)
==
MEM
)
return
"ld.w %1,%0\n\tld.w %R1,%R0"
;
if
(
GET_CODE
(
dst
)
==
MEM
)
return
"st.w %1,%0\n\tst.w %R1,%R0"
;
return
"mov %1,%0\n\tmov %R1,%R0"
;
}
</s>

Return appropriate code to load up an 8 byte integer or floating point value


<s> rtx ix86_memtag_set_tag ( rtx untagged , rtx tag , rtx target ) { if ( ix86_lam_type == lam_u57 ) { unsigned HOST_WIDE_INT and_imm = ( HOST_WIDE_INT_1U << IX86_HWASAN_TAG_SIZE ) - 1 ; emit_insn ( gen_andqi3 ( tag , tag , GEN_INT ( and_imm ) ) ) ; } tag = expand_simple_binop ( Pmode , ASHIFT , tag , GEN_INT ( IX86_HWASAN_SHIFT ) , NULL_RTX , 1 , OPTAB_WIDEN ) ; rtx ret = expand_simple_binop ( Pmode , IOR , untagged , tag , target , 1 , OPTAB_DIRECT ) ; return ret ; } </s>


<s> const SparcSubtarget * getSubtargetImpl ( ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
bool
isNoTOCCallInstr
(
unsigned
Opcode
)
const
{
if
(
!
get
(
Opcode
)
.
isCall
(
)
)
return
false
;
switch
(
Opcode
)
{
default
:
llvm_unreachable
(
"Unknown call opcode"
)
;
return
false
;
case
PPC
::
BL8_NOTOC
:
case
PPC
::
BL8_NOTOC_TLS
:
case
PPC
::
BL8_NOTOC_RM
:
return
true
;
case
PPC
::
BL8
:
case
PPC
::
BL
:
case
PPC
::
BL8_TLS
:
case
PPC
::
BL_TLS
:
case
PPC
::
BLA8
:
case
PPC
::
BLA
:
case
PPC
::
BCCL
:
case
PPC
::
BCCLA
:
case
PPC
::
BCL
:
case
PPC
::
BCLn
:
case
PPC
::
BL8_NOP
:
case
PPC
::
BL_NOP
:
case
PPC
::
BL8_NOP_TLS
:
case
PPC
::
BLA8_NOP
:
case
PPC
::
BCTRL8
:
case
PPC
::
BCTRL
:
case
PPC
::
BCCCTRL8
:
case
PPC
::
BCCCTRL
:
case
PPC
::
BCCTRL8
:
case
PPC
::
BCCTRL
:
case
PPC
::
BCCTRL8n
:
case
PPC
::
BCCTRLn
:
case
PPC
::
BL8_RM
:
case
PPC
::
BLA8_RM
:
case
PPC
::
BL8_NOP_RM
:
case
PPC
::
BLA8_NOP_RM
:
case
PPC
::
BCTRL8_RM
:
case
PPC
::
BCTRL8_LDinto_toc
:
case
PPC
::
BCTRL8_LDinto_toc_RM
:
case
PPC
::
BL8_TLS_
:
case
PPC
::
TCRETURNdi8
:
case
PPC
::
TCRETURNai8
:
case
PPC
::
TCRETURNri8
:
case
PPC
::
TAILBCTR8
:
case
PPC
::
TAILB8
:
case
PPC
::
TAILBA8
:
case
PPC
::
BCLalways
:
case
PPC
::
BLRL
:
case
PPC
::
BCCLRL
:
case
PPC
::
BCLRL
:
case
PPC
::
BCLRLn
:
case
PPC
::
BDZL
:
case
PPC
::
BDNZL
:
case
PPC
::
BDZLA
:
case
PPC
::
BDNZLA
:
case
PPC
::
BDZLp
:
case
PPC
::
BDNZLp
:
case
PPC
::
BDZLAp
:
case
PPC
::
BDNZLAp
:
case
PPC
::
BDZLm
:
case
PPC
::
BDNZLm
:
case
PPC
::
BDZLAm
:
case
PPC
::
BDNZLAm
:
case
PPC
::
BDZLRL
:
case
PPC
::
BDNZLRL
:
case
PPC
::
BDZLRLp
:
case
PPC
::
BDNZLRLp
:
case
PPC
::
BDZLRLm
:
case
PPC
::
BDNZLRLm
:
case
PPC
::
BL_RM
:
case
PPC
::
BLA_RM
:
case
PPC
::
BL_NOP_RM
:
case
PPC
::
BCTRL_RM
:
case
PPC
::
TCRETURNdi
:
case
PPC
::
TCRETURNai
:
case
PPC
::
TCRETURNri
:
case
PPC
::
BCTRL_LWZinto_toc
:
case
PPC
::
BCTRL_LWZinto_toc_RM
:
case
PPC
::
TAILBCTR
:
case
PPC
::
TAILB
:
case
PPC
::
TAILBA
:
return
false
;
}
}
</s>

Check if Opcode corresponds to a call instruction that should be marked with the NOTOC relocation .


<s> void print ( raw_ostream * O ) const { if ( O ) print ( * O ) ; } </s>

print - Print a debug representation of the operand to the given stream .


<s> static rtx mips_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return mips_function_value_1 ( NULL_TREE , NULL_TREE , mode ) ; } </s>


<s> virtual const XCoreSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>


<s>
AArch64TargetLowering
::
ConstraintType
AArch64TargetLowering
::
getConstraintType
(
const
std
::
string
&
Constraint
)
const
{
if
(
Constraint
.
size
(
)
==
1
)
{
switch
(
Constraint
[
0
]
)
{
default
:
break
;
case
'w'
:
return
C_RegisterClass
;
case
'I'
:
case
'J'
:
case
'K'
:
case
'L'
:
case
'M'
:
case
'N'
:
case
'Y'
:
case
'Z'
:
return
C_Other
;
case
'Q'
:
return
C_Memory
;
case
'S'
:
return
C_Other
;
}
}
assert
(
Constraint
!=
"Ump"
&&
Constraint
!=
"Utf"
&&
Constraint
!=
"Usa"
&&
Constraint
!=
"Ush"
&&
"Unimplemented constraints"
)
;
return
TargetLowering
::
getConstraintType
(
Constraint
)
;
}
</s>

Given a constraint letter , return the type of constraint for this target .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineTraceMetrics > ( ) ; AU . addPreserved < MachineTraceMetrics > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static void swap_const_vector_halves ( rtx * op_ptr ) { int i ; rtx op = * op_ptr ; enum rtx_code code = GET_CODE ( op ) ; if ( GET_CODE ( op ) == CONST_VECTOR ) { int units = GET_MODE_NUNITS ( GET_MODE ( op ) ) ; rtx_vector_builder builder ( GET_MODE ( op ) , units , 1 ) ; for ( i = 0 ; i < units / 2 ; ++ i ) builder . quick_push ( CONST_VECTOR_ELT ( op , i + units / 2 ) ) ; for ( i = 0 ; i < units / 2 ; ++ i ) builder . quick_push ( CONST_VECTOR_ELT ( op , i ) ) ; * op_ptr = builder . build ( ) ; } else { int j ; const char * fmt = GET_RTX_FORMAT ( code ) ; for ( i = 0 ; i < GET_RTX_LENGTH ( code ) ; ++ i ) if ( fmt [ i ] == 'e' || fmt [ i ] == 'u' ) swap_const_vector_halves ( & XEXP ( op , i ) ) ; else if ( fmt [ i ] == 'E' ) for ( j = 0 ; j < XVECLEN ( op , i ) ; ++ j ) swap_const_vector_halves ( & XVECEXP ( op , i , j ) ) ; } } </s>

OP is either a CONST_VECTOR or an expression containing one . Swap the first half of the vector with the second in the first case . Recurse to find it in the second .


<s> bool empty ( ) const { return getSGPRNum ( ) == 0 && getVGPRNum ( false ) == 0 ; } </s>

Determine whether this version information is empty ( e.g. , all version components are zero ) .


<s> uint64_t AArch64InstrInfo :: getElementSizeForOpcode ( unsigned Opc ) const { return get ( Opc ) . TSFlags & AArch64 :: ElementSizeMask ; } </s>

Returns the vector element size ( B , H , S or D ) of an SVE opcode .


<s> unsigned MOSInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { return 3 ; } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> SDValue X86TargetLowering :: getSqrtEstimate ( SDValue Op , SelectionDAG & DAG , int Enabled , int & RefinementSteps , bool & UseOneConstNR , bool Reciprocal ) const { EVT VT = Op . getValueType ( ) ; if ( ( VT == MVT :: f32 && Subtarget . hasSSE1 ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasSSE1 ( ) && Reciprocal ) || ( VT == MVT :: v4f32 && Subtarget . hasSSE2 ( ) && ! Reciprocal ) || ( VT == MVT :: v8f32 && Subtarget . hasAVX ( ) ) || ( VT == MVT :: v16f32 && Subtarget . useAVX512Regs ( ) ) ) { if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = 1 ; UseOneConstNR = false ; unsigned Opcode = VT == MVT :: v16f32 ? X86ISD :: RSQRT14 : X86ISD :: FRSQRT ; return DAG . getNode ( Opcode , SDLoc ( Op ) , VT , Op ) ; } return SDValue ( ) ; } </s>

Hooks for building estimates in place of slower divisions and square roots .


<s> static unsigned findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const TargetRegisterInfo & TRI , bool Is64Bit ) { const MachineFunction * MF = MBB . getParent ( ) ; const Function * F = MF -> getFunction ( ) ; if ( ! F || MF -> getMMI ( ) . callsEHReturn ( ) ) return 0 ; static const unsigned CallerSavedRegs32Bit [ ] = { X86 :: EAX , X86 :: EDX , X86 :: ECX , 0 } ; static const unsigned CallerSavedRegs64Bit [ ] = { X86 :: RAX , X86 :: RDX , X86 :: RCX , X86 :: RSI , X86 :: RDI , X86 :: R8 , X86 :: R9 , X86 :: R10 , X86 :: R11 , 0 } ; unsigned Opc = MBBI -> getOpcode ( ) ; switch ( Opc ) { default : return 0 ; case X86 :: RET : case X86 :: RETI : case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: TCRETURNmi64 : case X86 :: EH_RETURN : case X86 :: EH_RETURN64 : { SmallSet < unsigned , 8 > Uses ; for ( unsigned i = 0 , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( const unsigned * AsI = TRI . getOverlaps ( Reg ) ; * AsI ; ++ AsI ) Uses . insert ( * AsI ) ; } const unsigned * CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit ; for ( ; * CS ; ++ CS ) if ( ! Uses . count ( * CS ) ) return * CS ; } } return 0 ; } </s>

findDeadCallerSavedReg - Return a caller-saved register that is n't live when it reaches the `` return '' instruction .


<s> const DirectXTargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


<s> static bool ix86_find_max_used_stack_alignment ( unsigned int & stack_alignment , bool check_stack_slot ) { HARD_REG_SET set_up_by_prologue , prologue_used ; basic_block bb ; CLEAR_HARD_REG_SET ( prologue_used ) ; CLEAR_HARD_REG_SET ( set_up_by_prologue ) ; add_to_hard_reg_set ( & set_up_by_prologue , Pmode , STACK_POINTER_REGNUM ) ; add_to_hard_reg_set ( & set_up_by_prologue , Pmode , ARG_POINTER_REGNUM ) ; add_to_hard_reg_set ( & set_up_by_prologue , Pmode , HARD_FRAME_POINTER_REGNUM ) ; if ( stack_alignment > crtl -> preferred_stack_boundary ) stack_alignment = crtl -> preferred_stack_boundary ; bool require_stack_frame = false ; FOR_EACH_BB_FN ( bb , cfun ) { rtx_insn * insn ; FOR_BB_INSNS ( bb , insn ) if ( NONDEBUG_INSN_P ( insn ) && requires_stack_frame_p ( insn , prologue_used , set_up_by_prologue ) ) { require_stack_frame = true ; if ( check_stack_slot ) { subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , ALL ) if ( MEM_P ( * iter ) && ( reg_mentioned_p ( stack_pointer_rtx , * iter ) || reg_mentioned_p ( frame_pointer_rtx , * iter ) ) ) { unsigned int alignment = MEM_ALIGN ( * iter ) ; if ( alignment > stack_alignment ) stack_alignment = alignment ; } } } } return require_stack_frame ; } </s>

Return true if stack frame is required . Update STACK_ALIGNMENT to the largest alignment , in bits , of stack slot used if stack frame is required and CHECK_STACK_SLOT is true .


<s> bool TeakFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TeakSubtarget & STI = MF . getSubtarget < TeakSubtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; BuildMI ( MBB , MI , DL , TII . get ( Teak :: POP_regnob16 ) , Reg ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> void riscv_split_doubleword_move ( rtx dest , rtx src ) { rtx low_dest ; low_dest = riscv_subword ( dest , false ) ; if ( REG_P ( low_dest ) && reg_overlap_mentioned_p ( low_dest , src ) ) { riscv_emit_move ( riscv_subword ( dest , true ) , riscv_subword ( src , true ) ) ; riscv_emit_move ( low_dest , riscv_subword ( src , false ) ) ; } else { riscv_emit_move ( low_dest , riscv_subword ( src , false ) ) ; riscv_emit_move ( riscv_subword ( dest , true ) , riscv_subword ( src , true ) ) ; } } </s>

Split a doubleword move from SRC to DEST . On 32-bit targets , this function handles 64-bit moves for which riscv_split_64bit_move_p holds . For 64-bit targets , this function handles 128-bit moves .


<s> static void v850_print_operand_address ( FILE * file , rtx addr ) { switch ( GET_CODE ( addr ) ) { case REG : fprintf ( file , "0[" ) ; v850_print_operand ( file , addr , 0 ) ; fprintf ( file , "]" ) ; break ; case LO_SUM : if ( GET_CODE ( XEXP ( addr , 0 ) ) == REG ) { fprintf ( file , "lo(" ) ; v850_print_operand ( file , XEXP ( addr , 1 ) , 0 ) ; fprintf ( file , ")[" ) ; v850_print_operand ( file , XEXP ( addr , 0 ) , 0 ) ; fprintf ( file , "]" ) ; } break ; case PLUS : if ( GET_CODE ( XEXP ( addr , 0 ) ) == REG || GET_CODE ( XEXP ( addr , 0 ) ) == SUBREG ) { v850_print_operand ( file , XEXP ( addr , 1 ) , 0 ) ; fprintf ( file , "[" ) ; v850_print_operand ( file , XEXP ( addr , 0 ) , 0 ) ; fprintf ( file , "]" ) ; } else { v850_print_operand ( file , XEXP ( addr , 0 ) , 0 ) ; fprintf ( file , "+" ) ; v850_print_operand ( file , XEXP ( addr , 1 ) , 0 ) ; } break ; case SYMBOL_REF : { const char * off_name = NULL ; const char * reg_name = NULL ; if ( SYMBOL_REF_ZDA_P ( addr ) ) { off_name = "zdaoff" ; reg_name = "r0" ; } else if ( SYMBOL_REF_SDA_P ( addr ) ) { off_name = "sdaoff" ; reg_name = "gp" ; } else if ( SYMBOL_REF_TDA_P ( addr ) ) { off_name = "tdaoff" ; reg_name = "ep" ; } if ( off_name ) fprintf ( file , "%s(" , off_name ) ; output_addr_const ( file , addr ) ; if ( reg_name ) fprintf ( file , ")[%s]" , reg_name ) ; } break ; case CONST : if ( special_symbolref_operand ( addr , VOIDmode ) ) { rtx x = XEXP ( XEXP ( addr , 0 ) , 0 ) ; const char * off_name ; const char * reg_name ; if ( SYMBOL_REF_ZDA_P ( x ) ) { off_name = "zdaoff" ; reg_name = "r0" ; } else if ( SYMBOL_REF_SDA_P ( x ) ) { off_name = "sdaoff" ; reg_name = "gp" ; } else if ( SYMBOL_REF_TDA_P ( x ) ) { off_name = "tdaoff" ; reg_name = "ep" ; } else gcc_unreachable ( ) ; fprintf ( file , "%s(" , off_name ) ; output_addr_const ( file , addr ) ; fprintf ( file , ")[%s]" , reg_name ) ; } else output_addr_const ( file , addr ) ; break ; default : output_addr_const ( file , addr ) ; break ; } } </s>

Output assembly language output for the address ADDR to FILE .


<s> void R600MCCodeEmitter :: Emit ( uint64_t Value , raw_ostream & OS ) const { support :: endian :: write ( OS , Value , support :: little ) ; } </s>

AMDGPU R600 support::endian support::little


<s> bool ARMAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AFI = MF . getInfo < ARMFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; Subtarget = & MF . getSubtarget < ARMSubtarget > ( ) ; SetupMachineFunction ( MF ) ; const Function & F = MF . getFunction ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; for ( auto * GV : AFI -> getGlobalsPromotedToConstantPool ( ) ) PromotedGlobals . insert ( GV ) ; unsigned OptimizationGoal ; if ( F . hasOptNone ( ) ) OptimizationGoal = 6 ; else if ( F . hasMinSize ( ) ) OptimizationGoal = 4 ; else if ( F . hasOptSize ( ) ) OptimizationGoal = 3 ; else if ( TM . getOptLevel ( ) == CodeGenOpt :: Aggressive ) OptimizationGoal = 2 ; else if ( TM . getOptLevel ( ) > CodeGenOpt :: None ) OptimizationGoal = 1 ; else OptimizationGoal = 5 ; if ( OptimizationGoals == - 1 ) OptimizationGoals = OptimizationGoal ; else if ( OptimizationGoals != ( int ) OptimizationGoal ) OptimizationGoals = 0 ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = F . hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer -> EmitCOFFSymbolType ( Type ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; emitXRayTable ( ) ; if ( ! ThumbIndirectPads . empty ( ) ) { OutStreamer -> EmitAssemblerFlag ( MCAF_Code16 ) ; EmitAlignment ( Align ( 2 ) ) ; for ( std :: pair < unsigned , MCSymbol * > & TIP : ThumbIndirectPads ) { OutStreamer -> EmitLabel ( TIP . second ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( ARM :: tBX ) . addReg ( TIP . first ) . addImm ( ARMCC :: AL ) . addReg ( 0 ) ) ; } ThumbIndirectPads . clear ( ) ; } return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> void TOYInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { } </s>


"%qs attribute only applies to functions"


<s> void s390_output_pool_entry ( rtx exp , machine_mode mode , unsigned int align ) { switch ( GET_MODE_CLASS ( mode ) ) { case MODE_FLOAT : case MODE_DECIMAL_FLOAT : gcc_assert ( GET_CODE ( exp ) == CONST_DOUBLE ) ; assemble_real ( * CONST_DOUBLE_REAL_VALUE ( exp ) , mode , align ) ; break ; case MODE_INT : assemble_integer ( exp , GET_MODE_SIZE ( mode ) , align , 1 ) ; mark_symbol_refs_as_used ( exp ) ; break ; case MODE_VECTOR_INT : case MODE_VECTOR_FLOAT : { int i ; machine_mode inner_mode ; gcc_assert ( GET_CODE ( exp ) == CONST_VECTOR ) ; inner_mode = GET_MODE_INNER ( GET_MODE ( exp ) ) ; for ( i = 0 ; i < XVECLEN ( exp , 0 ) ; i ++ ) s390_output_pool_entry ( XVECEXP ( exp , 0 , i ) , inner_mode , i == 0 ? align : GET_MODE_BITSIZE ( inner_mode ) ) ; } break ; default : gcc_unreachable ( ) ; } } </s>

Output the constant pool entry EXP in mode MODE with alignment ALIGN .


"-misched-topdown incompatible with -misched-bottomup"

Initialize the strategy after building the DAG for a new region .


<s> void gas_output_limited_string ( FILE * file , const char * str ) { const unsigned char * _limited_str = ( unsigned char * ) str ; unsigned ch ; fprintf ( file , "%s\"" , STRING_ASM_OP ) ; for ( ; ( ch = * _limited_str ) ; _limited_str ++ ) { int escape ; switch ( escape = ESCAPES [ ch ] ) { case 0 : putc ( ch , file ) ; break ; case 1 : fprintf ( file , "\\%03o" , ch ) ; break ; default : putc ( '\\' , file ) ; putc ( escape , file ) ; break ; } } fprintf ( file , "\"\n" ) ; } </s>

The routine used to output NUL terminated strings . We use a special version of this for most svr4 targets because doing so makes the generated assembly code more compact ( and thus faster to assemble ) as well as more readable , especially for targets like the i386 ( where the only alternative is to output character sequences as comma separated lists of numbers ) .


<s> virtual void Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileMachO :: Initialize ( Ctx , TM ) ; LSDASection = getMachOSection ( "__TEXT" , "__gcc_except_tab" , 0 , SectionKind :: getReadOnlyWithRel ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s> void rs6000_scale_v2df ( rtx tgt , rtx src , int scale ) { HOST_WIDE_INT hwi_scale ( scale ) ; REAL_VALUE_TYPE r_pow ; rtvec v = rtvec_alloc ( 2 ) ; rtx elt ; rtx scale_vec = gen_reg_rtx ( V2DFmode ) ; ( void ) real_powi ( & r_pow , DFmode , & dconst2 , hwi_scale ) ; elt = const_double_from_real_value ( r_pow , DFmode ) ; RTVEC_ELT ( v , 0 ) = elt ; RTVEC_ELT ( v , 1 ) = elt ; rs6000_expand_vector_init ( scale_vec , gen_rtx_PARALLEL ( V2DFmode , v ) ) ; emit_insn ( gen_mulv2df3 ( tgt , src , scale_vec ) ) ; } </s>

Scale a V2DF vector SRC by two to the SCALE and place in TGT .


<s> static void insert_wic_for_ilb_runout ( rtx_insn * first ) { rtx_insn * insn ; rtx_insn * before_4 = 0 ; rtx_insn * before_16 = 0 ; int addr_offset = 0 ; int length ; int wic_addr0 = 128 * 4 ; int first_addr = INSN_ADDRESSES ( INSN_UID ( first ) ) ; for ( insn = first ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) ) { addr_offset = INSN_ADDRESSES ( INSN_UID ( insn ) ) - first_addr ; length = get_attr_length ( insn ) ; if ( before_4 == 0 && addr_offset + length >= 4 * 4 ) before_4 = insn ; if ( JUMP_P ( insn ) ) return ; if ( before_16 == 0 && addr_offset + length >= 14 * 4 ) before_16 = insn ; if ( CALL_P ( insn ) || tablejump_p ( insn , 0 , 0 ) ) return ; if ( addr_offset + length >= 32 * 4 ) { gcc_assert ( before_4 && before_16 ) ; if ( wic_addr0 > 4 * 4 ) { insn = emit_insn_before ( gen_iprefetch ( gen_int_mode ( addr_offset , SImode ) ) , before_4 ) ; recog_memoized ( insn ) ; INSN_LOCATION ( insn ) = INSN_LOCATION ( before_4 ) ; INSN_ADDRESSES_NEW ( insn , INSN_ADDRESSES ( INSN_UID ( before_4 ) ) ) ; return ; } } } } </s>

Heuristics to identify where to insert at the fall through path of the caller function . If there is a call after the caller branch delay slot then we dont generate the instruction prefetch instruction . Scan up to 32 instructions after the call and checks for the JUMP and call instruction . If there is a call or JUMP instruction in the range of 32 instruction `` wic '' instruction wont be generated . Otherwise insert the `` wic '' instruction in the fall through of the call instruction four instruction after the call . before_4 is used for the position to insert `` wic '' instructions . before_16 is used to check for call and JUMP instruction for first 15 insns .


<s> bool XCorePassConfig :: addInstSelector ( ) { PM -> add ( createXCoreISelDag ( getXCoreTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static bool nvptx_modes_tieable_p ( machine_mode , machine_mode ) { return false ; } </s>


"-mtune= expects mn10300, am33, am33-2, or am34"


<s> static bool csky_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { return ! ( TARGET_HARD_FLOAT && mode1 != mode2 && ( mode1 == DFmode || mode2 == DFmode ) ) ; } </s>

Implement TARGET_MODES_TIEABLE_P . We ca n't tie DFmode with other modes when V_REGs might be in use because those registers mess with the stored bits .


<s> static void msp430_evaluate_arg ( cumulative_args_t cap , machine_mode mode , const_tree type ATTRIBUTE_UNUSED , bool named ) { CUMULATIVE_ARGS * ca = get_cumulative_args ( cap ) ; int nregs = GET_MODE_SIZE ( mode ) ; int i ; ca -> reg_count = 0 ; ca -> mem_count = 0 ; if ( ! named ) return ; if ( mode == PSImode ) nregs = 1 ; else nregs = ( nregs + 1 ) / 2 ; if ( ca -> special_p ) { ca -> start_reg = 8 ; ca -> reg_count = 4 ; return ; } switch ( nregs ) { case 1 : for ( i = 0 ; i < 4 ; i ++ ) if ( ! ca -> reg_used [ i ] ) { ca -> reg_count = 1 ; ca -> start_reg = CA_FIRST_REG + i ; return ; } break ; case 2 : for ( i = 0 ; i < 3 ; i ++ ) if ( ! ca -> reg_used [ i ] && ! ca -> reg_used [ i + 1 ] ) { ca -> reg_count = 2 ; ca -> start_reg = CA_FIRST_REG + i ; return ; } if ( ! ca -> reg_used [ 3 ] && ca -> can_split ) { ca -> reg_count = 1 ; ca -> mem_count = 2 ; ca -> start_reg = CA_FIRST_REG + 3 ; return ; } break ; case 3 : case 4 : ca -> can_split = 0 ; if ( ! ca -> reg_used [ 0 ] && ! ca -> reg_used [ 1 ] && ! ca -> reg_used [ 2 ] && ! ca -> reg_used [ 3 ] ) { ca -> reg_count = 4 ; ca -> start_reg = CA_FIRST_REG ; return ; } break ; } } </s>

Helper function for argument passing ; this function is the common code that determines where an argument will be passed .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> static bool nios2_legitimate_address_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx operand , bool strict_p ) { switch ( GET_CODE ( operand ) ) { case SYMBOL_REF : if ( SYMBOL_REF_TLS_MODEL ( operand ) ) return false ; case CONST : if ( gprel_constant_p ( operand ) ) return true ; case LABEL_REF : case CONST_INT : case CONST_DOUBLE : return false ; case REG : return nios2_regno_ok_for_base_p ( REGNO ( operand ) , strict_p ) ; case PLUS : { rtx op0 = XEXP ( operand , 0 ) ; rtx op1 = XEXP ( operand , 1 ) ; return ( nios2_valid_addr_expr_p ( op0 , op1 , strict_p ) || nios2_valid_addr_expr_p ( op1 , op0 , strict_p ) ) ; } default : break ; } return false ; } </s>


<s> bool RISCVAsmBackend :: shouldInsertExtraNopBytesForCodeAlign ( const MCAlignFragment & AF , unsigned & Size ) { const MCSubtargetInfo * STI = AF . getSubtargetInfo ( ) ; if ( ! STI -> getFeatureBits ( ) [ RISCV :: FeatureRelax ] ) return false ; bool HasStdExtC = STI -> getFeatureBits ( ) [ RISCV :: FeatureStdExtC ] ; unsigned MinNopLen = HasStdExtC ? 2 : 4 ; if ( AF . getAlignment ( ) <= MinNopLen ) { return false ; } else { Size = AF . getAlignment ( ) - MinNopLen ; return true ; } } </s>

Hook to check if extra nop bytes must be inserted for alignment directive .

RISCV RISCV RISCV::FeatureRelax RISCV::FeatureStdExtC 2 4


"Instr doesn't have FrameIndex operand!"

"Unconditionally using R28 for evil purposes Offset: "

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s>
bool
ARMCodeGenPrepare
::
runOnFunction
(
Function
&
F
)
{
if
(
skipFunction
(
F
)
||
DisableCGP
)
return
false
;
auto
*
TPC
=
&
getAnalysis
<
TargetPassConfig
>
(
)
;
if
(
!
TPC
)
return
false
;
const
TargetMachine
&
TM
=
TPC
->
getTM
<
TargetMachine
>
(
)
;
ST
=
&
TM
.
getSubtarget
<
ARMSubtarget
>
(
F
)
;
bool
MadeChange
=
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM CGP: Running on "
<<
F
.
getName
(
)
<<
"\n"
)
;
for
(
BasicBlock
&
BB
:
F
)
{
auto
&
Insts
=
BB
.
getInstList
(
)
;
for
(
auto
&
I
:
Insts
)
{
if
(
AllVisited
.
count
(
&
I
)
)
continue
;
if
(
isa
<
ICmpInst
>
(
I
)
)
{
auto
&
CI
=
cast
<
ICmpInst
>
(
I
)
;
if
(
CI
.
isSigned
(
)
||
!
isa
<
IntegerType
>
(
CI
.
getOperand
(
0
)
->
getType
(
)
)
)
continue
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM CGP: Searching from: "
<<
CI
<<
"\n"
)
;
for
(
auto
&
Op
:
CI
.
operands
(
)
)
{
if
(
auto
*
I
=
dyn_cast
<
Instruction
>
(
Op
)
)
MadeChange
|=
TryToPromote
(
I
)
;
}
}
}
LLVM_DEBUG
(
if
(
verifyFunction
(
F
,
&
dbgs
(
)
)
)
{
dbgs
(
)
<<
F
;
report_fatal_error
(
"Broken function after type promotion"
)
;
}
)
;
}
if
(
MadeChange
)
LLVM_DEBUG
(
dbgs
(
)
<<
"After ARMCodeGenPrepare: "
<<
F
<<
"\n"
)
;
return
MadeChange
;
}
</s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .

ARM
ARM
ARM
"ARM CGP: Running on "
"\n"
0
"ARM CGP: Searching from: "
"\n"
"Broken function after type promotion"
"After ARMCodeGenPrepare: "
"\n"


Prepare for a new round of multipass lookahead scheduling .


<s> unsigned getPointerSize ( ) const { return 4 ; } </s>

Layout pointer size in bytes , rounded up to a whole number of bytes .


<s> X86Subtarget :: X86Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , unsigned StackAlignOverride ) : X86GenSubtargetInfo ( TT , CPU , FS ) , X86ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) { initializeEnvironment ( ) ; resetSubtargetFeatures ( CPU , FS ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> bool NVPTXAsmPrinter :: doFinalization ( Module & M ) { bool HasDebugInfo = MMI && MMI -> hasDebugInfo ( ) ; if ( ! GlobalsEmitted ) { emitGlobals ( M ) ; GlobalsEmitted = true ; } bool ret = AsmPrinter :: doFinalization ( M ) ; clearAnnotationCache ( & M ) ; if ( auto * TS = static_cast < NVPTXTargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ) { if ( HasDebugInfo ) { TS -> closeLastSection ( ) ; OutStreamer -> emitRawText ( "\t.section\t.debug_loc\t{\t}" ) ; } TS -> outputDwarfFileDirectives ( ) ; } return ret ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .

NVPTX NVPTX NVPTX "\t.section\t.debug_loc\t{\t}"


<s> unsigned HexagonInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { case Hexagon :: STriw : case Hexagon :: STrid : case Hexagon :: STrih : case Hexagon :: STrib : if ( MI -> getOperand ( 2 ) . isFI ( ) && MI -> getOperand ( 1 ) . isImm ( ) && ( MI -> getOperand ( 1 ) . getImm ( ) == 0 ) ) { FrameIndex = MI -> getOperand ( 2 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; default : break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> bool AArch64AsmBackend :: mayNeedRelaxation ( const MCInst & Inst ) const { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> unsigned SIInstrInfo :: getInstrLatency ( const InstrItineraryData * ItinData , const MachineInstr & MI , unsigned * PredCost ) const { if ( MI . isBundle ( ) ) { MachineBasicBlock :: const_instr_iterator I ( MI . getIterator ( ) ) ; MachineBasicBlock :: const_instr_iterator E ( MI . getParent ( ) -> instr_end ( ) ) ; unsigned Lat = 0 , Count = 0 ; for ( ++ I ; I != E && I -> isBundledWithPred ( ) ; ++ I ) { ++ Count ; Lat = std :: max ( Lat , SchedModel . computeInstrLatency ( & * I ) ) ; } return Lat + Count - 1 ; } return SchedModel . computeInstrLatency ( & MI ) ; } </s>

Compute the instruction latency of a given instruction .


<s>
uint32_t
ARM64MCCodeEmitter
::
getBranchTargetOpValue
(
const
MCInst
&
MI
,
unsigned
OpIdx
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCOperand
&
MO
=
MI
.
getOperand
(
OpIdx
)
;
if
(
MO
.
isImm
(
)
)
return
MO
.
getImm
(
)
;
assert
(
MO
.
isExpr
(
)
&&
"Unexpected ADR target type!"
)
;
MCFixupKind
Kind
=
MI
.
getOpcode
(
)
==
ARM64
::
BL
MCFixupKind
(
ARM64
::
fixup_arm64_pcrel_call26
)
:
MCFixupKind
(
ARM64
::
fixup_arm64_pcrel_branch26
)
;
Fixups
.
push_back
(
MCFixup
::
Create
(
0
,
MO
.
getExpr
(
)
,
Kind
,
MI
.
getLoc
(
)
)
)
;
++
MCNumFixups
;
return
0
;
}
</s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .


This is just a placeholder to make linking work without having to add this to the generic Darwin EXTRA_SECTIONS . If -mcall-aix is ever needed for Darwin ( not too likely ! ) this would have to get a real definition .


<s> static void alpha_elf_select_rtx_section ( enum machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ) { if ( TARGET_SMALL_DATA && GET_MODE_SIZE ( mode ) <= g_switch_value ) sdata_section ( ) ; else default_elf_select_rtx_section ( mode , x , align ) ; } </s>

Switch to the section to which we should output X . The only thing special we do here is to honor small data .


<s> bool AVRAsmParser :: ParseDirective ( llvm :: AsmToken DirectiveID ) { return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s>
MachineBasicBlock
*
XCoreTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
const
TargetInstrInfo
&
TII
=
*
Subtarget
.
getInstrInfo
(
)
;
DebugLoc
dl
=
MI
.
getDebugLoc
(
)
;
assert
(
(
MI
.
getOpcode
(
)
==
XCore
::
SELECT_CC
)
&&
"Unexpected instr type to insert"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
It
=
++
BB
->
getIterator
(
)
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
sinkMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
F
->
insert
(
It
,
copy0MBB
)
;
F
->
insert
(
It
,
sinkMBB
)
;
sinkMBB
->
splice
(
sinkMBB
->
begin
(
)
,
BB
,
std
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
BB
->
end
(
)
)
;
sinkMBB
->
transferSuccessorsAndUpdatePHIs
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
sinkMBB
)
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
XCore
::
BRFT_lru6
)
)
.
addReg
(
MI
.
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
sinkMBB
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
sinkMBB
;
BuildMI
(
*
BB
,
BB
->
begin
(
)
,
dl
,
TII
.
get
(
XCore
::
PHI
)
,
MI
.
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
.
getOperand
(
3
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
.
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
MI
.
eraseFromParent
(
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> void PPCInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { DebugLoc DL ; BuildMI ( MBB , MI , DL , get ( PPC :: NOP ) ) ; } </s>

Insert a noop into the instruction stream at the specified point .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
ARM64
::
NumTargetFixupKinds
]
=
{
{
"fixup_arm64_pcrel_adr_imm21"
,
0
,
32
,
PCRelFlagVal
}
,
{
"fixup_arm64_pcrel_adrp_imm21"
,
0
,
32
,
PCRelFlagVal
}
,
{
"fixup_arm64_add_imm12"
,
10
,
12
,
0
}
,
{
"fixup_arm64_ldst_imm12_scale1"
,
10
,
12
,
0
}
,
{
"fixup_arm64_ldst_imm12_scale2"
,
10
,
12
,
0
}
,
{
"fixup_arm64_ldst_imm12_scale4"
,
10
,
12
,
0
}
,
{
"fixup_arm64_ldst_imm12_scale8"
,
10
,
12
,
0
}
,
{
"fixup_arm64_ldst_imm12_scale16"
,
10
,
12
,
0
}
,
{
"fixup_arm64_ldr_pcrel_imm19"
,
5
,
19
,
PCRelFlagVal
}
,
{
"fixup_arm64_movw"
,
5
,
16
,
0
}
,
{
"fixup_arm64_pcrel_branch14"
,
5
,
14
,
PCRelFlagVal
}
,
{
"fixup_arm64_pcrel_branch19"
,
5
,
19
,
PCRelFlagVal
}
,
{
"fixup_arm64_pcrel_branch26"
,
0
,
26
,
PCRelFlagVal
}
,
{
"fixup_arm64_pcrel_call26"
,
0
,
26
,
PCRelFlagVal
}
,
{
"fixup_arm64_tlsdesc_call"
,
0
,
0
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> bool SystemZRegisterInfo :: getRegAllocationHints ( unsigned VirtReg , ArrayRef < MCPhysReg > Order , SmallVectorImpl < MCPhysReg > & Hints , const MachineFunction & MF , const VirtRegMap * VRM , const LiveRegMatrix * Matrix ) const { const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( MRI -> getRegClass ( VirtReg ) == & SystemZ :: GRX32BitRegClass ) { SmallVector < unsigned , 8 > Worklist ; SmallSet < unsigned , 4 > DoneRegs ; Worklist . push_back ( VirtReg ) ; while ( Worklist . size ( ) ) { unsigned Reg = Worklist . pop_back_val ( ) ; if ( ! DoneRegs . insert ( Reg ) . second ) continue ; for ( auto & Use : MRI -> use_instructions ( Reg ) ) if ( Use . getOpcode ( ) == SystemZ :: LOCRMux ) { MachineOperand & TrueMO = Use . getOperand ( 1 ) ; MachineOperand & FalseMO = Use . getOperand ( 2 ) ; const TargetRegisterClass * RC = TRI -> getCommonSubClass ( getRC32 ( FalseMO , VRM , MRI ) , getRC32 ( TrueMO , VRM , MRI ) ) ; if ( RC && RC != & SystemZ :: GRX32BitRegClass ) { for ( MCPhysReg Reg : Order ) if ( RC -> contains ( Reg ) && ! MRI -> isReserved ( Reg ) ) Hints . push_back ( Reg ) ; return true ; } unsigned OtherReg = ( TrueMO . getReg ( ) == Reg ? FalseMO . getReg ( ) : TrueMO . getReg ( ) ) ; if ( MRI -> getRegClass ( OtherReg ) == & SystemZ :: GRX32BitRegClass ) Worklist . push_back ( OtherReg ) ; } } } return TargetRegisterInfo :: getRegAllocationHints ( VirtReg , Order , Hints , MF , VRM , Matrix ) ; } </s>

Get a list of 'hint ' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg .


Compute a bit mask of which core registers need to be saved on the stack for the current function .


<s> int m32c_const_ok_for_constraint_p ( HOST_WIDE_INT value , char c ATTRIBUTE_UNUSED , const char * str ) { if ( memcmp ( str , "Is3" , 3 ) == 0 ) { return ( - 8 <= value && value <= 7 ) ; } if ( memcmp ( str , "IS1" , 3 ) == 0 ) { return ( - 128 <= value && value <= 127 ) ; } if ( memcmp ( str , "IS2" , 3 ) == 0 ) { return ( - 32768 <= value && value <= 32767 ) ; } if ( memcmp ( str , "IU2" , 3 ) == 0 ) { return ( 0 <= value && value <= 65535 ) ; } if ( memcmp ( str , "IU3" , 3 ) == 0 ) { return ( 0 <= value && value <= 0x00ffffff ) ; } if ( memcmp ( str , "In4" , 3 ) == 0 ) { return ( - 8 <= value && value && value <= 8 ) ; } if ( memcmp ( str , "In5" , 3 ) == 0 ) { return ( - 16 <= value && value && value <= 16 ) ; } if ( memcmp ( str , "IM2" , 3 ) == 0 ) { return ( - 65536 <= value && value && value <= - 1 ) ; } if ( memcmp ( str , "Ilb" , 3 ) == 0 ) { int b = exact_log2 ( value ) ; return ( b >= 1 && b <= 8 ) ; } if ( memcmp ( str , "Ilw" , 3 ) == 0 ) { int b = exact_log2 ( value ) ; return ( b >= 1 && b <= 16 ) ; } return 0 ; } </s>

Implements CONST_OK_FOR_CONSTRAINT_P . Currently , all constant constraints start with ' I ' , with the next two characters indicating the type and size of the range allowed .


<s> bool X86FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; if ( isFuncletReturnInstr ( MI ) && STI . isOSWindows ( ) ) { if ( STI . is32Bit ( ) ) return true ; if ( MI -> getOpcode ( ) == X86 :: CATCHRET ) { const Function * Func = MBB . getParent ( ) -> getFunction ( ) ; bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( Func -> getPersonalityFn ( ) ) ) ; if ( IsSEH ) return true ; } } DebugLoc DL = MBB . findDebugLoc ( MI ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } unsigned Opc = STI . is64Bit ( ) ? X86 :: POP64r : X86 :: POP32r ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool ARMCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto DL = MF . getDataLayout ( ) ; auto & TLI = * getTLI < ARMTargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb ( ) ) return false ; for ( auto & Arg : F . args ( ) ) if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; SmallVector < ArgInfo , 8 > ArgInfos ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + 1 , DL , F ) ; splitToValueTypes ( AInfo , ArgInfos , DL , MF . getRegInfo ( ) ) ; Idx ++ ; } FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; return handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


"unimplemented opcode in encodeInstruction()"

Encode the given Inst to bytes and append to CB .


"Lowering returned the wrong number of results!"

This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types .


<s> bool isReg ( ) const override { return Kind == Register ; } </s>


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const ARMBaseTargetMachine & TM , bool IsLittle ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , ARMProcClass ( None ) , stackAlignment ( 4 ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , TSInfo ( * TM . getDataLayout ( ) ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( ARMBaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( ARMBaseInstrInfo * ) new ARMInstrInfo ( * this ) : ( ARMBaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) { } </s>

This constructor initializes the data members to match that of the specified triple .

ARM ARM ARM ARM ARM ARM ARM 4 ARM ARM ARM ARM


<s> bool M680x0FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || TRI -> needsStackRealignment ( MF ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
unsigned
WebAssemblyInstrInfo
::
insertBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
TBB
,
MachineBasicBlock
*
FBB
,
ArrayRef
<
MachineOperand
>
Cond
,
const
DebugLoc
&
DL
,
int
*
BytesAdded
)
const
{
assert
(
!
BytesAdded
&&
"code size not handled"
)
;
if
(
Cond
.
empty
(
)
)
{
if
(
!
TBB
)
return
0
;
BuildMI
(
&
MBB
,
DL
,
get
(
WebAssembly
::
BR
)
)
.
addMBB
(
TBB
)
;
return
1
;
}
assert
(
Cond
.
size
(
)
==
2
&&
"Expected a flag and a successor block"
)
;
if
(
Cond
[
0
]
.
getImm
(
)
)
{
BuildMI
(
&
MBB
,
DL
,
get
(
WebAssembly
::
BR_IF
)
)
.
addMBB
(
TBB
)
.
add
(
Cond
[
1
]
)
;
}
else
{
BuildMI
(
&
MBB
,
DL
,
get
(
WebAssembly
::
BR_UNLESS
)
)
.
addMBB
(
TBB
)
.
add
(
Cond
[
1
]
)
;
}
if
(
!
FBB
)
return
1
;
BuildMI
(
&
MBB
,
DL
,
get
(
WebAssembly
::
BR
)
)
.
addMBB
(
FBB
)
;
return
2
;
}
</s>

Insert branch code into the end of the specified MachineBasicBlock .


<s> MachineInstr * X86InstrInfo :: optimizeLoadInstr ( MachineInstr & MI , const MachineRegisterInfo * MRI , unsigned & FoldAsLoadDefReg , MachineInstr * & DefMI ) const { DefMI = MRI -> getVRegDef ( FoldAsLoadDefReg ) ; assert ( DefMI ) ; bool SawStore = false ; if ( ! DefMI -> isSafeToMove ( nullptr , SawStore ) ) return nullptr ; SmallVector < unsigned , 1 > SrcOperandIds ; for ( unsigned i = 0 , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg != FoldAsLoadDefReg ) continue ; if ( MO . getSubReg ( ) || MO . isDef ( ) ) return nullptr ; SrcOperandIds . push_back ( i ) ; } if ( SrcOperandIds . empty ( ) ) return nullptr ; if ( MachineInstr * FoldMI = foldMemoryOperand ( MI , SrcOperandIds , * DefMI ) ) { FoldAsLoadDefReg = 0 ; return FoldMI ; } return nullptr ; } </s>

optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use .


<s> static bool s390_call_saved_register_used ( tree call_expr ) { CUMULATIVE_ARGS cum_v ; cumulative_args_t cum ; tree parameter ; machine_mode mode ; tree type ; rtx parm_rtx ; int reg , i ; INIT_CUMULATIVE_ARGS ( cum_v , NULL , NULL , 0 , 0 ) ; cum = pack_cumulative_args ( & cum_v ) ; for ( i = 0 ; i < call_expr_nargs ( call_expr ) ; i ++ ) { parameter = CALL_EXPR_ARG ( call_expr , i ) ; gcc_assert ( parameter ) ; if ( TREE_CODE ( parameter ) == ERROR_MARK ) return true ; type = TREE_TYPE ( parameter ) ; gcc_assert ( type ) ; mode = TYPE_MODE ( type ) ; gcc_assert ( mode ) ; if ( pass_by_reference ( & cum_v , mode , type , true ) ) { mode = Pmode ; type = build_pointer_type ( type ) ; } parm_rtx = s390_function_arg ( cum , mode , type , true ) ; s390_function_arg_advance ( cum , mode , type , true ) ; if ( ! parm_rtx ) continue ; if ( REG_P ( parm_rtx ) ) { for ( reg = 0 ; reg < REG_NREGS ( parm_rtx ) ; reg ++ ) if ( ! call_used_regs [ reg + REGNO ( parm_rtx ) ] ) return true ; } if ( GET_CODE ( parm_rtx ) == PARALLEL ) { int i ; for ( i = 0 ; i < XVECLEN ( parm_rtx , 0 ) ; i ++ ) { rtx r = XEXP ( XVECEXP ( parm_rtx , 0 , i ) , 0 ) ; gcc_assert ( REG_P ( r ) ) ; for ( reg = 0 ; reg < REG_NREGS ( r ) ; reg ++ ) if ( ! call_used_regs [ reg + REGNO ( r ) ] ) return true ; } } } return false ; } </s>

Checks whether the given ARGUMENT_LIST would use a caller saved register . This is used to decide whether sibling call optimization could be performed on the respective function call .


<s>
static
void
rl78_note_reg_set
(
char
*
dead
,
rtx
d
,
rtx
insn
)
{
int
r
,
i
;
if
(
GET_CODE
(
d
)
==
MEM
)
rl78_note_reg_uses
(
dead
,
XEXP
(
d
,
0
)
,
insn
)
;
if
(
GET_CODE
(
d
)
!=
REG
)
return
;
r
=
REGNO
(
d
)
;
if
(
dead
[
r
]
)
add_reg_note
(
insn
,
REG_UNUSED
,
gen_rtx_REG
(
GET_MODE
(
d
)
,
r
)
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"note set reg %d size %d\n"
,
r
,
GET_MODE_SIZE
(
GET_MODE
(
d
)
)
)
;
for
(
i
=
0
;
i
<
GET_MODE_SIZE
(
GET_MODE
(
d
)
)
;
i
++
)
dead
[
r
+
i
]
=
1
;
}
</s>

Like the previous function , but scan for SETs instead .


<s> bool isToken ( ) const override { return Kind == Token ; } </s>


<s> bool LC3bAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { LC3bFI = MF . getInfo < LC3bFunctionInfo > ( ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool Mips16InstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { MachineBasicBlock & MBB = * MI . getParent ( ) ; switch ( MI . getDesc ( ) . getOpcode ( ) ) { default : return false ; case Mips :: RetRA16 : ExpandRetRA16 ( MBB , MI , Mips :: JrcRa16 ) ; break ; } MBB . erase ( MI . getIterator ( ) ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { const auto & Subtarget = MF . getSubtarget < WebAssemblySubtarget > ( ) ; hasAddr64 = Subtarget . hasAddr64 ( ) ; TII = Subtarget . getInstrInfo ( ) ; return AsmPrinter :: runOnMachineFunction ( MF ) ; } </s>


"Instr doesn't have FrameIndex operand!"

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s> bool SITargetLowering :: isTypeDesirableForOp ( unsigned Op , EVT VT ) const { if ( VT == MVT :: i1 && Op == ISD :: SETCC ) return false ; return TargetLowering :: isTypeDesirableForOp ( Op , VT ) ; } </s>

Return true if the target has native support for the specified value type and it is 'desirable ' to use the type for the given node type .


<s> const uint32_t * ARMBaseRegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return CSR_NoRegs_RegMask ; return ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> SDValue HexagonTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SmallVectorImpl < SDValue > & OutVals , SDValue Callee ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_Hexagon ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { SDValue RetVal ; if ( RVLocs [ i ] . getValVT ( ) == MVT :: i1 ) { auto & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue FR0 = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , MVT :: i32 , InFlag ) ; unsigned PredR = MRI . createVirtualRegister ( & Hexagon :: PredRegsRegClass ) ; SDValue TPR = DAG . getCopyToReg ( FR0 . getValue ( 1 ) , dl , PredR , FR0 . getValue ( 0 ) , FR0 . getValue ( 2 ) ) ; RetVal = DAG . getCopyFromReg ( TPR . getValue ( 0 ) , dl , PredR , MVT :: i1 , TPR . getValue ( 1 ) ) ; } else { RetVal = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) ; } InVals . push_back ( RetVal . getValue ( 0 ) ) ; Chain = RetVal . getValue ( 1 ) ; InFlag = RetVal . getValue ( 2 ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s>
void
GBZ80InstPrinter
::
printPCRelImm
(
const
MCInst
*
MI
,
unsigned
OpNo
,
raw_ostream
&
O
)
{
const
MCOperand
&
Op
=
MI
->
getOperand
(
OpNo
)
;
if
(
Op
.
isImm
(
)
)
{
int64_t
Imm
=
Op
.
getImm
(
)
;
if
(
Imm
>=
0
)
O
<<
'+'
;
O
<<
Imm
;
}
else
{
assert
(
Op
.
isExpr
(
)
&&
"Unknown pcrel immediate operand"
)
;
O
<<
*
Op
.
getExpr
(
)
;
}
}
</s>


<s> int RISCVFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const auto * RVFI = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; const auto & CSI = getNonLibcallCSI ( MFI . getCalleeSavedInfo ( ) ) ; int MinCSFI = 0 ; int MaxCSFI = - 1 ; int Offset = MFI . getObjectOffset ( FI ) - getOffsetOfLocalArea ( ) + MFI . getOffsetAdjustment ( ) ; uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( CSI . size ( ) ) { MinCSFI = CSI [ 0 ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - 1 ] . getFrameIdx ( ) ; } if ( FI >= MinCSFI && FI <= MaxCSFI ) { FrameReg = RISCV :: X2 ; if ( FirstSPAdjustAmount ) Offset += FirstSPAdjustAmount ; else Offset += MFI . getStackSize ( ) ; } else if ( RI -> needsStackRealignment ( MF ) && ! MFI . isFixedObjectIndex ( FI ) ) { if ( hasBP ( MF ) ) FrameReg = RISCVABI :: getBPReg ( ) ; else FrameReg = RISCV :: X2 ; Offset += MFI . getStackSize ( ) ; if ( FI < 0 ) Offset += RVFI -> getLibCallStackSize ( ) ; } else { FrameReg = RI -> getFrameRegister ( MF ) ; if ( hasFP ( MF ) ) { Offset += RVFI -> getVarArgsSaveSize ( ) ; if ( FI >= 0 ) Offset -= RVFI -> getLibCallStackSize ( ) ; } else { Offset += MFI . getStackSize ( ) ; if ( FI < 0 ) Offset += RVFI -> getLibCallStackSize ( ) ; } } return Offset ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> static bool classof ( const MCExpr * E ) { return E -> getKind ( ) == MCExpr :: Target ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> Optional < MCFixupKind > X86AsmBackend :: getFixupKind ( StringRef Name ) const { if ( STI . getTargetTriple ( ) . isOSBinFormatELF ( ) ) { unsigned Type ; if ( STI . getTargetTriple ( ) . getArch ( ) == Triple :: x86_64 ) { Type = llvm :: StringSwitch < unsigned > ( Name ) . Default ( - 1u ) ; } else { Type = llvm :: StringSwitch < unsigned > ( Name ) . Default ( - 1u ) ; } if ( Type == - 1u ) return None ; return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ; } return MCAsmBackend :: getFixupKind ( Name ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


"r%d has non convertible def in insn %d\n"

"r%d has non convertible use in insn %d\n"

For a register REGNO , scan instructions for its defs and uses . Put REGNO in REGS if a def or use is n't in CANDIDATES .


<s> bool nios2_emit_move_sequence ( rtx * operands , machine_mode mode ) { rtx to = operands [ 0 ] ; rtx from = operands [ 1 ] ; if ( ! register_operand ( to , mode ) && ! reg_or_0_operand ( from , mode ) ) { gcc_assert ( can_create_pseudo_p ( ) ) ; from = copy_to_mode_reg ( mode , from ) ; } if ( CONSTANT_P ( from ) ) { if ( CONST_INT_P ( from ) ) { if ( ! SMALL_INT ( INTVAL ( from ) ) && ! SMALL_INT_UNSIGNED ( INTVAL ( from ) ) && ! UPPER16_INT ( INTVAL ( from ) ) ) { HOST_WIDE_INT high = ( INTVAL ( from ) + 0x8000 ) & ~ 0xffff ; HOST_WIDE_INT low = INTVAL ( from ) & 0xffff ; emit_move_insn ( to , gen_int_mode ( high , SImode ) ) ; emit_insn ( gen_add2_insn ( to , gen_int_mode ( low , HImode ) ) ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , copy_rtx ( from ) ) ; return true ; } } else if ( ! gprel_constant_p ( from ) ) { if ( ! nios2_large_unspec_reloc_p ( from ) ) from = nios2_legitimize_constant_address ( from ) ; if ( CONSTANT_P ( from ) ) { emit_insn ( gen_rtx_SET ( to , gen_rtx_HIGH ( Pmode , from ) ) ) ; emit_insn ( gen_rtx_SET ( to , gen_rtx_LO_SUM ( Pmode , to , from ) ) ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , copy_rtx ( operands [ 1 ] ) ) ; return true ; } } } operands [ 0 ] = to ; operands [ 1 ] = from ; return false ; } </s>


"Can't store this register to stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> static void ix86_check_avx256_stores ( rtx dest , const_rtx , void * data ) { if ( ix86_check_avx256_register ( dest ) ) { bool * used = ( bool * ) data ; * used = true ; } } </s>

Check if a 256bit AVX register is referenced in stores .


<s> void s390_expand_split_stack_prologue ( void ) { rtx r1 , guard , cc = NULL ; rtx_insn * insn ; int psso = TARGET_64BIT ? 0x38 : 0x20 ; HOST_WIDE_INT frame_size = cfun_frame_layout . frame_size ; HOST_WIDE_INT args_size = crtl -> args . size >= 0 ? ( ( crtl -> args . size + 7 ) & ~ 7 ) : 0 ; rtx_code_label * call_done = NULL ; rtx_code_label * parm_base = NULL ; rtx tmp ; gcc_assert ( flag_split_stack && reload_completed ) ; r1 = gen_rtx_REG ( Pmode , 1 ) ; if ( ! frame_size ) { if ( cfun -> machine -> split_stack_varargs_pointer != NULL_RTX ) { emit_move_insn ( r1 , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( STACK_POINTER_OFFSET ) ) ) ; } return ; } if ( morestack_ref == NULL_RTX ) { morestack_ref = gen_rtx_SYMBOL_REF ( Pmode , "__morestack" ) ; SYMBOL_REF_FLAGS ( morestack_ref ) |= ( SYMBOL_FLAG_LOCAL | SYMBOL_FLAG_FUNCTION ) ; } if ( CONST_OK_FOR_K ( frame_size ) || CONST_OK_FOR_Op ( frame_size ) ) { emit_insn ( gen_get_thread_pointer ( Pmode , r1 ) ) ; guard = gen_rtx_MEM ( Pmode , plus_constant ( Pmode , r1 , psso ) ) ; if ( frame_size > SPLIT_STACK_AVAILABLE ) { emit_move_insn ( r1 , guard ) ; if ( TARGET_64BIT ) emit_insn ( gen_adddi3 ( r1 , r1 , GEN_INT ( frame_size ) ) ) ; else emit_insn ( gen_addsi3 ( r1 , r1 , GEN_INT ( frame_size ) ) ) ; guard = r1 ; } cc = s390_emit_compare ( LT , stack_pointer_rtx , guard ) ; } call_done = gen_label_rtx ( ) ; parm_base = gen_label_rtx ( ) ; LABEL_NUSES ( parm_base ) ++ ; LABEL_NUSES ( call_done ) ++ ; insn = emit_move_insn ( r1 , gen_rtx_LABEL_REF ( VOIDmode , parm_base ) ) ; add_reg_note ( insn , REG_LABEL_OPERAND , parm_base ) ; LABEL_NUSES ( parm_base ) ++ ; if ( cc != NULL ) tmp = gen_split_stack_cond_call ( Pmode , morestack_ref , parm_base , call_done , GEN_INT ( frame_size ) , GEN_INT ( args_size ) , cc ) ; else tmp = gen_split_stack_call ( Pmode , morestack_ref , parm_base , call_done , GEN_INT ( frame_size ) , GEN_INT ( args_size ) ) ; insn = emit_jump_insn ( tmp ) ; JUMP_LABEL ( insn ) = call_done ; add_reg_note ( insn , REG_LABEL_OPERAND , parm_base ) ; add_reg_note ( insn , REG_LABEL_OPERAND , call_done ) ; if ( cc != NULL ) { add_reg_br_prob_note ( insn , profile_probability :: very_unlikely ( ) ) ; if ( cfun -> machine -> split_stack_varargs_pointer != NULL_RTX ) { emit_move_insn ( r1 , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( STACK_POINTER_OFFSET ) ) ) ; } } else { emit_barrier ( ) ; } emit_label ( call_done ) ; } </s>

Emit -fsplit-stack prologue , which goes before the regular function prologue .


<s> static bool m32c_function_needs_enter ( void ) { rtx_insn * insn ; rtx sp = gen_rtx_REG ( Pmode , SP_REGNO ) ; rtx fb = gen_rtx_REG ( Pmode , FB_REGNO ) ; for ( insn = get_topmost_sequence ( ) -> first ; insn ; insn = NEXT_INSN ( insn ) ) if ( NONDEBUG_INSN_P ( insn ) ) { if ( reg_mentioned_p ( sp , insn ) ) return true ; if ( reg_mentioned_p ( fb , insn ) ) return true ; } return false ; } </s>

Returns TRUE if the current function needs to use the ENTER/EXIT opcodes . If the function does n't need the frame base or stack pointer , it can use the simpler RTS opcode .


<s> void CFGStructurizer < PassT > :: removeSuccessor ( BlockT * srcBlk ) { while ( srcBlk -> succ_size ( ) ) { srcBlk -> removeSuccessor ( * srcBlk -> succ_begin ( ) ) ; } } </s>

Remove specified successor from the successors list of this MachineBasicBlock .


<s> Function * X86TargetLowering :: getSSPStackGuardCheck ( const Module & M ) const { if ( Subtarget . getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) || Subtarget . getTargetTriple ( ) . isWindowsItaniumEnvironment ( ) ) { return M . getFunction ( "__security_check_cookie" ) ; } return TargetLowering :: getSSPStackGuardCheck ( M ) ; } </s>

If the target has a standard stack protection check function that performs validation and error handling , returns the function .


<s> static HOST_WIDE_INT mips_constant_alignment ( const_tree exp , HOST_WIDE_INT align ) { if ( TREE_CODE ( exp ) == STRING_CST || TREE_CODE ( exp ) == CONSTRUCTOR ) return MAX ( align , BITS_PER_WORD ) ; return align ; } </s>


<s> const MipsSubtarget * getSubtargetImpl ( ) const { if ( Subtarget ) return Subtarget ; return & DefaultSubtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
MCFragment
*
AArch64MCExpr
::
findAssociatedFragment
(
)
const
{
llvm_unreachable
(
"FIXME: what goes here?"
)
;
}
</s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s> unsigned X86InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( isFrameLoadOpcode ( MI -> getOpcode ( ) ) ) if ( isFrameOperand ( MI , 1 , FrameIndex ) ) return MI -> getOperand ( 0 ) . getReg ( ) ; return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


"Only floating point immediates are supported at the moment."


<s>
static
void
riscv_file_start
(
void
)
{
default_file_start
(
)
;
fprintf
(
asm_out_file
,
"\t.option %spic\n"
,
(
flag_pic
""
:
"no"
)
)
;
if
(
!
riscv_mrelax
)
fprintf
(
asm_out_file
,
"\t.option norelax\n"
)
;
if
(
riscv_mcsr_check
)
fprintf
(
asm_out_file
,
"\t.option csr-check\n"
)
;
if
(
riscv_emit_attribute_p
)
riscv_emit_attribute
(
)
;
}
</s>

riscv
"\t.option %spic\n"
""
"no"
"\t.option norelax\n"
"\t.option csr-check\n"


<s> virtual bool isProfitableToIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , unsigned ExtraPredCycles , const BranchProbability & Probability ) const { return true ; } </s>


<s> static HOST_WIDE_INT aarch64_estimated_poly_value ( poly_int64 val ) { enum aarch64_sve_vector_bits_enum width_source = aarch64_tune_params . sve_width ; if ( width_source == SVE_SCALABLE ) return default_estimated_poly_value ( val ) ; HOST_WIDE_INT over_128 = width_source - 128 ; return val . coeffs [ 0 ] + val . coeffs [ 1 ] * over_128 / 128 ; } </s>

Implement TARGET_ESTIMATED_POLY_VALUE . Look into the tuning structure for an estimate . KIND specifies the type of requested estimate : min , max or likely . For cores with a known SVE width all three estimates are the same . For generic SVE tuning we want to distinguish the maximum estimate from the minimum and likely ones . The likely estimate is the same as the minimum in that case to give a conservative behavior of auto-vectorizing with SVE when it is a win even for 128-bit SVE . When SVE width information is available VAL.coeffs [ 1 ] is multiplied by the number of VQ chunks over the initial Advanced SIMD 128 bits .


<s>
bool
AArch64TargetLowering
::
lowerInterleavedStore
(
StoreInst
*
SI
,
ShuffleVectorInst
*
SVI
,
unsigned
Factor
)
const
{
assert
(
Factor
>=
2
&&
Factor
<=
getMaxSupportedInterleaveFactor
(
)
&&
"Invalid interleave factor"
)
;
VectorType
*
VecTy
=
SVI
->
getType
(
)
;
assert
(
VecTy
->
getVectorNumElements
(
)
%
Factor
==
0
&&
"Invalid interleaved store"
)
;
unsigned
LaneLen
=
VecTy
->
getVectorNumElements
(
)
/
Factor
;
Type
*
EltTy
=
VecTy
->
getVectorElementType
(
)
;
VectorType
*
SubVecTy
=
VectorType
::
get
(
EltTy
,
LaneLen
)
;
const
DataLayout
&
DL
=
SI
->
getModule
(
)
->
getDataLayout
(
)
;
unsigned
SubVecSize
=
DL
.
getTypeSizeInBits
(
SubVecTy
)
;
if
(
!
Subtarget
->
hasNEON
(
)
||
(
SubVecSize
!=
64
&&
SubVecSize
!=
128
)
)
return
false
;
Value
*
Op0
=
SVI
->
getOperand
(
0
)
;
Value
*
Op1
=
SVI
->
getOperand
(
1
)
;
IRBuilder
<
>
Builder
(
SI
)
;
if
(
EltTy
->
isPointerTy
(
)
)
{
Type
*
IntTy
=
DL
.
getIntPtrType
(
EltTy
)
;
unsigned
NumOpElts
=
dyn_cast
<
VectorType
>
(
Op0
->
getType
(
)
)
->
getVectorNumElements
(
)
;
Type
*
IntVecTy
=
VectorType
::
get
(
IntTy
,
NumOpElts
)
;
Op0
=
Builder
.
CreatePtrToInt
(
Op0
,
IntVecTy
)
;
Op1
=
Builder
.
CreatePtrToInt
(
Op1
,
IntVecTy
)
;
SubVecTy
=
VectorType
::
get
(
IntTy
,
LaneLen
)
;
}
Type
*
PtrTy
=
SubVecTy
->
getPointerTo
(
SI
->
getPointerAddressSpace
(
)
)
;
Type
*
Tys
[
2
]
=
{
SubVecTy
,
PtrTy
}
;
static
const
Intrinsic
::
ID
StoreInts
[
3
]
=
{
Intrinsic
::
aarch64_neon_st2
,
Intrinsic
::
aarch64_neon_st3
,
Intrinsic
::
aarch64_neon_st4
}
;
Function
*
StNFunc
=
Intrinsic
::
getDeclaration
(
SI
->
getModule
(
)
,
StoreInts
[
Factor
2
]
,
Tys
)
;
SmallVector
<
Value
*
,
5
>
Ops
;
auto
Mask
=
SVI
->
getShuffleMask
(
)
;
for
(
unsigned
i
=
0
;
i
<
Factor
;
i
++
)
{
if
(
Mask
[
i
]
>=
0
)
{
Ops
.
push_back
(
Builder
.
CreateShuffleVector
(
Op0
,
Op1
,
getSequentialMask
(
Builder
,
Mask
[
i
]
,
LaneLen
)
)
)
;
}
else
{
unsigned
StartMask
=
0
;
for
(
unsigned
j
=
1
;
j
<
LaneLen
;
j
++
)
{
if
(
Mask
[
j
*
Factor
+
i
]
>=
0
)
{
StartMask
=
Mask
[
j
*
Factor
+
i
]
j
;
break
;
}
}
Ops
.
push_back
(
Builder
.
CreateShuffleVector
(
Op0
,
Op1
,
getSequentialMask
(
Builder
,
StartMask
,
LaneLen
)
)
)
;
}
}
Ops
.
push_back
(
Builder
.
CreateBitCast
(
SI
->
getPointerOperand
(
)
,
PtrTy
)
)
;
Builder
.
CreateCall
(
StNFunc
,
Ops
)
;
return
true
;
}
</s>

Lower interleaved store ( s ) into target specific instructions/intrinsics .


<s> bool AArch64TargetLowering :: isLegalAddImmediate ( int64_t Immed ) const { return ( ( Immed >> 12 ) == 0 || ( ( Immed & 0xfff ) == 0 && Immed >> 24 == 0 ) ) ; } </s>

Return true if the specified immediate is legal add immediate , that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register .


<s>
const
uint32_t
*
RISCVRegisterInfo
::
getCallPreservedMask
(
const
MachineFunction
&
MF
,
CallingConv
::
ID
)
const
{
auto
&
Subtarget
=
MF
.
getSubtarget
<
RISCVSubtarget
>
(
)
;
switch
(
Subtarget
.
getTargetABI
(
)
)
{
default
:
llvm_unreachable
(
"Unrecognized ABI"
)
;
case
RISCVABI
::
ABI_ILP32
:
case
RISCVABI
::
ABI_LP64
:
return
CSR_ILP32_LP64_RegMask
;
case
RISCVABI
::
ABI_ILP32F
:
case
RISCVABI
::
ABI_LP64F
:
return
CSR_ILP32F_LP64F_RegMask
;
case
RISCVABI
::
ABI_ILP32D
:
case
RISCVABI
::
ABI_LP64D
:
return
CSR_ILP32D_LP64D_RegMask
;
}
}
</s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool GCNPassConfig :: addPreISel ( ) { AMDGPUPassConfig :: addPreISel ( ) ; addPass ( createSinkingPass ( ) ) ; addPass ( createSITypeRewriter ( ) ) ; addPass ( createSIAnnotateControlFlowPass ( ) ) ; return false ; } </s>


<s> bool X86TargetLowering :: shouldExpandAtomicStoreInIR ( StoreInst * SI ) const { Type * MemType = SI -> getValueOperand ( ) -> getType ( ) ; bool NoImplicitFloatOps = SI -> getFunction ( ) -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ; if ( MemType -> getPrimitiveSizeInBits ( ) == 64 && ! Subtarget . is64Bit ( ) && ! Subtarget . useSoftFloat ( ) && ! NoImplicitFloatOps && Subtarget . hasSSE2 ( ) ) return false ; return needsCmpXchgNb ( MemType ) ; } </s>

Returns how the given ( atomic ) store should be expanded by the IR-level AtomicExpand pass into .


<s> static bool callee_saved_regno_p ( int regno ) { if ( ! call_used_or_fixed_reg_p ( regno ) && df_regs_ever_live_p ( regno ) ) return true ; switch ( regno ) { case HARD_FRAME_POINTER_REGNUM : return frame_pointer_needed ; case LR_REGNUM : return ( frame_pointer_needed || ! crtl -> is_leaf || crtl -> uses_pic_offset_table || df_regs_ever_live_p ( regno ) ) ; case HW_TO_GCC_REGNO ( 25 ) : case HW_TO_GCC_REGNO ( 27 ) : case HW_TO_GCC_REGNO ( 29 ) : case HW_TO_GCC_REGNO ( 31 ) : return crtl -> calls_eh_return ; default : return false ; } } </s>

Returns true if REGNO must be saved for the current function .


<s> const AArch64Subtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>


<s>
unsigned
getReg
(
)
const
{
assert
(
Kind
==
Register
&&
"Invalid type access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s>
void
R600RegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
MI
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
llvm_unreachable
(
"Subroutines not supported yet"
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .

AMDGPU
R600
"Subroutines not supported yet"


<s> void MipsAsmPrinter :: emitFrameDirective ( ) { const TargetRegisterInfo & RI = * TM . getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) -> getStackSize ( ) ; if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( "\t.frame\t$" + StringRef ( MipsInstPrinter :: getRegisterName ( stackReg ) ) . lower ( ) + "," + Twine ( stackSize ) + ",$" + StringRef ( MipsInstPrinter :: getRegisterName ( returnReg ) ) . lower ( ) ) ; } </s>

Mips Mips "\t.frame\t$" Mips "," ",$" Mips


<s>
const
char
*
ix86_output_ssemov
(
rtx_insn
*
insn
,
rtx
*
operands
)
{
machine_mode
mode
=
GET_MODE
(
operands
[
0
]
)
;
if
(
get_attr_type
(
insn
)
!=
TYPE_SSEMOV
||
mode
!=
GET_MODE
(
operands
[
1
]
)
)
gcc_unreachable
(
)
;
enum
attr_mode
insn_mode
=
get_attr_mode
(
insn
)
;
switch
(
insn_mode
)
{
case
MODE_XI
:
case
MODE_V8DF
:
case
MODE_V16SF
:
return
ix86_get_ssemov
(
operands
,
64
,
insn_mode
,
mode
)
;
case
MODE_OI
:
case
MODE_V4DF
:
case
MODE_V8SF
:
return
ix86_get_ssemov
(
operands
,
32
,
insn_mode
,
mode
)
;
case
MODE_TI
:
case
MODE_V2DF
:
case
MODE_V4SF
:
return
ix86_get_ssemov
(
operands
,
16
,
insn_mode
,
mode
)
;
case
MODE_DI
:
if
(
GENERAL_REG_P
(
operands
[
0
]
)
)
{
if
(
HAVE_AS_IX86_INTERUNIT_MOVQ
)
return
"%vmovq\t{%1, %q0|%q0, %1}"
;
else
return
"%vmovd\t{%1, %q0|%q0, %1}"
;
}
else
if
(
GENERAL_REG_P
(
operands
[
1
]
)
)
{
if
(
HAVE_AS_IX86_INTERUNIT_MOVQ
)
return
"%vmovq\t{%q1, %0|%0, %q1}"
;
else
return
"%vmovd\t{%q1, %0|%0, %q1}"
;
}
else
return
"%vmovq\t{%1, %0|%0, %1}"
;
case
MODE_SI
:
if
(
GENERAL_REG_P
(
operands
[
0
]
)
)
return
"%vmovd\t{%1, %k0|%k0, %1}"
;
else
if
(
GENERAL_REG_P
(
operands
[
1
]
)
)
return
"%vmovd\t{%k1, %0|%0, %k1}"
;
else
return
"%vmovd\t{%1, %0|%0, %1}"
;
case
MODE_HI
:
if
(
GENERAL_REG_P
(
operands
[
0
]
)
)
return
"vmovw\t{%1, %k0|%k0, %1}"
;
else
if
(
GENERAL_REG_P
(
operands
[
1
]
)
)
return
"vmovw\t{%k1, %0|%0, %k1}"
;
else
return
"vmovw\t{%1, %0|%0, %1}"
;
case
MODE_DF
:
if
(
TARGET_AVX
&&
REG_P
(
operands
[
0
]
)
&&
REG_P
(
operands
[
1
]
)
)
return
"vmovsd\t{%d1, %0|%0, %d1}"
;
else
return
"%vmovsd\t{%1, %0|%0, %1}"
;
case
MODE_SF
:
if
(
TARGET_AVX
&&
REG_P
(
operands
[
0
]
)
&&
REG_P
(
operands
[
1
]
)
)
return
"vmovss\t{%d1, %0|%0, %d1}"
;
else
return
"%vmovss\t{%1, %0|%0, %1}"
;
case
MODE_HF
:
case
MODE_BF
:
if
(
REG_P
(
operands
[
0
]
)
&&
REG_P
(
operands
[
1
]
)
)
return
"vmovsh\t{%d1, %0|%0, %d1}"
;
else
return
"vmovsh\t{%1, %0|%0, %1}"
;
case
MODE_V1DF
:
gcc_assert
(
!
TARGET_AVX
)
;
return
"movlpd\t{%1, %0|%0, %1}"
;
case
MODE_V2SF
:
if
(
TARGET_AVX
&&
REG_P
(
operands
[
0
]
)
)
return
"vmovlps\t{%1, %d0|%d0, %1}"
;
else
return
"%vmovlps\t{%1, %0|%0, %1}"
;
default
:
gcc_unreachable
(
)
;
}
}
</s>

Return the template of the TYPE_SSEMOV instruction to move operands [ 1 ] into operands [ 0 ] .


<s> const uint32_t * SNESRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return CSR_Normal_RegMask ; } </s>


<s> void ix86_split_fp_absneg_operator ( enum rtx_code code , machine_mode mode , rtx operands [ ] ) { enum rtx_code absneg_op ; rtx dst , set ; gcc_assert ( operands_match_p ( operands [ 0 ] , operands [ 1 ] ) ) ; switch ( mode ) { case E_SFmode : dst = gen_lowpart ( SImode , operands [ 0 ] ) ; if ( code == ABS ) { set = gen_int_mode ( 0x7fffffff , SImode ) ; absneg_op = AND ; } else { set = gen_int_mode ( 0x80000000 , SImode ) ; absneg_op = XOR ; } set = gen_rtx_fmt_ee ( absneg_op , SImode , dst , set ) ; break ; case E_DFmode : if ( TARGET_64BIT ) { dst = gen_lowpart ( DImode , operands [ 0 ] ) ; dst = gen_rtx_ZERO_EXTRACT ( DImode , dst , const1_rtx , GEN_INT ( 63 ) ) ; if ( code == ABS ) set = const0_rtx ; else set = gen_rtx_NOT ( DImode , dst ) ; } else { dst = gen_highpart ( SImode , operands [ 0 ] ) ; if ( code == ABS ) { set = gen_int_mode ( 0x7fffffff , SImode ) ; absneg_op = AND ; } else { set = gen_int_mode ( 0x80000000 , SImode ) ; absneg_op = XOR ; } set = gen_rtx_fmt_ee ( absneg_op , SImode , dst , set ) ; } break ; case E_XFmode : dst = gen_rtx_REG ( SImode , REGNO ( operands [ 0 ] ) + ( TARGET_64BIT ? 1 : 2 ) ) ; if ( code == ABS ) { set = GEN_INT ( 0x7fff ) ; absneg_op = AND ; } else { set = GEN_INT ( 0x8000 ) ; absneg_op = XOR ; } set = gen_rtx_fmt_ee ( absneg_op , SImode , dst , set ) ; break ; default : gcc_unreachable ( ) ; } set = gen_rtx_SET ( dst , set ) ; rtx clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; rtvec par = gen_rtvec ( 2 , set , clob ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , par ) ) ; } </s>

Deconstruct a floating point ABS or NEG operation with integer registers into integer operations .


<s> bool LM32TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> const char * VETargetLowering :: getTargetNodeName ( unsigned Opcode ) const { case VEISD :: NAME : \ return "VEISD::" # NAME ; switch ( ( VEISD :: NodeType ) Opcode ) { case VEISD :: FIRST_NUMBER : break ; TARGET_NODE_CASE ( Lo ) TARGET_NODE_CASE ( Hi ) TARGET_NODE_CASE ( GETFUNPLT ) TARGET_NODE_CASE ( GETTLSADDR ) TARGET_NODE_CASE ( CALL ) TARGET_NODE_CASE ( RET_FLAG ) TARGET_NODE_CASE ( GLOBAL_BASE_REG ) } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

VE VE VEISD::NAME "VEISD::" VEISD::NodeType VEISD::FIRST_NUMBER


<s> void TMS320C64XInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { int delay = 1 ; DebugLoc dl ; addDefaultPred ( BuildMI ( MBB , MI , dl , get ( TMS320C64X :: noop ) ) . addImm ( delay ) ) ; } </s>

Insert a noop into the instruction stream at the specified point .


<s>
void
HexagonCommonGEP
::
materialize
(
NodeToValueMap
&
Loc
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Nodes before materialization:\n"
<<
Nodes
<<
'\n'
)
;
NodeChildrenMap
NCM
;
NodeVect
Roots
;
invert_find_roots
(
Nodes
,
NCM
,
Roots
)
;
while
(
!
Roots
.
empty
(
)
)
{
NodeVect
::
iterator
First
=
Roots
.
begin
(
)
;
GepNode
*
Root
=
*
First
,
*
Last
=
*
First
;
Roots
.
erase
(
First
)
;
NodeVect
;
bool
LastUsed
=
false
;
unsigned
LastCN
=
0
;
Value
*
LocV
=
Loc
[
Last
]
;
if
(
!
LocV
)
continue
;
BasicBlock
*
LastB
=
cast
<
BasicBlock
>
(
LocV
)
;
do
{
.
push_back
(
Last
)
;
LastUsed
=
(
Last
->
Flags
&
GepNode
::
Used
)
;
if
(
LastUsed
)
break
;
NodeChildrenMap
::
iterator
CF
=
NCM
.
find
(
Last
)
;
LastCN
=
(
CF
!=
NCM
.
end
(
)
)
CF
->
second
.
size
(
)
:
0
;
if
(
LastCN
!=
1
)
break
;
GepNode
*
Child
=
CF
->
second
.
front
(
)
;
BasicBlock
*
ChildB
=
cast_or_null
<
BasicBlock
>
(
Loc
[
Child
]
)
;
if
(
ChildB
!=
nullptr
&&
LastB
!=
ChildB
)
break
;
Last
=
Child
;
}
while
(
true
)
;
BasicBlock
::
iterator
InsertAt
=
LastB
->
getTerminator
(
)
->
getIterator
(
)
;
if
(
LastUsed
||
LastCN
>
0
)
{
ValueVect
Urs
;
getAllUsersForNode
(
Root
,
Urs
,
NCM
)
;
BasicBlock
::
iterator
FirstUse
=
first_use_of_in_block
(
Urs
,
LastB
)
;
if
(
FirstUse
!=
LastB
->
end
(
)
)
InsertAt
=
FirstUse
;
}
Value
*
NewInst
=
fabricateGEP
(
,
InsertAt
,
LastB
)
;
if
(
LastCN
>
0
)
{
NodeVect
&
Cs
=
NCM
[
Last
]
;
for
(
GepNode
*
CN
:
Cs
)
{
CN
->
Flags
&=
~
GepNode
::
Internal
;
CN
->
Flags
|=
GepNode
::
Root
;
CN
->
BaseVal
=
NewInst
;
Roots
.
push_back
(
CN
)
;
}
}
if
(
LastUsed
)
{
NodeToUsesMap
::
iterator
UF
=
Uses
.
find
(
Last
)
;
assert
(
UF
!=
Uses
.
end
(
)
&&
"No use information found"
)
;
UseSet
&
Us
=
UF
->
second
;
for
(
Use
*
U
:
Us
)
U
->
set
(
NewInst
)
;
}
}
}
</s>

This method can be implemented to generate a mapped Value on demand .


<s> static void pop ( int rn ) { rtx x , sp_reg , reg ; if ( rn == FPUL_REG ) x = gen_pop_fpul ( ) ; else if ( rn == FPSCR_REG ) x = gen_pop_fpscr ( ) ; else if ( TARGET_FPU_DOUBLE && TARGET_FMOVD && ! TARGET_FPU_SINGLE && FP_OR_XD_REGISTER_P ( rn ) ) { if ( FP_REGISTER_P ( rn ) && ( rn - FIRST_FP_REG ) & 1 ) return ; x = gen_pop_4 ( gen_rtx_REG ( DFmode , rn ) ) ; } else if ( TARGET_SH2E && FP_REGISTER_P ( rn ) ) x = gen_pop_e ( gen_rtx_REG ( SFmode , rn ) ) ; else x = gen_pop ( gen_rtx_REG ( SImode , rn ) ) ; x = emit_insn ( x ) ; sp_reg = gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) ; reg = copy_rtx ( GET_CODE ( PATTERN ( x ) ) == PARALLEL ? SET_DEST ( XVECEXP ( PATTERN ( x ) , 0 , 0 ) ) : SET_DEST ( PATTERN ( x ) ) ) ; add_reg_note ( x , REG_CFA_RESTORE , reg ) ; add_reg_note ( x , REG_CFA_ADJUST_CFA , gen_rtx_SET ( sp_reg , plus_constant ( SImode , sp_reg , GET_MODE_SIZE ( GET_MODE ( reg ) ) ) ) ) ; add_reg_note ( x , REG_INC , gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) ) ; RTX_FRAME_RELATED_P ( x ) = 1 ; } </s>

Output RTL to pop register RN from the stack .


<s> bool PPCDarwinAsmPrinter :: doFinalization ( Module & M ) { bool isPPC64 = getDataLayout ( ) . getPointerSizeInBits ( ) == 64 ; const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; if ( MAI -> doesSupportExceptionHandling ( ) && MMI ) { for ( const Function * Personality : MMI -> getPersonalities ( ) ) { if ( Personality ) { MCSymbol * NLPSym = getSymbolWithGlobalValueBase ( Personality , "$non_lazy_ptr" ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMIMacho . getGVStubEntry ( NLPSym ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( Personality ) , true ) ; } } } MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer -> EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer -> EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer -> EmitIntValue ( 0 , isPPC64 ? 8 : 4 ) ; else OutStreamer -> EmitValue ( MCSymbolRefExpr :: create ( MCSym . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 ) ; } Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> static void pa_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int arg_size = pa_function_arg_size ( arg . mode , arg . type ) ; cum -> nargs_prototype -- ; cum -> words += ( arg_size + ( ( cum -> words & 01 ) && arg . type != NULL_TREE && arg_size > 1 ) ) ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> static bool arm_evpc_neon_vtrn ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> nelt ; rtx out0 , out1 , in0 , in1 ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; if ( d -> perm [ 0 ] == 0 ) odd = 0 ; else if ( d -> perm [ 0 ] == 1 ) odd = 1 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt ; i += 2 ) { if ( d -> perm [ i ] != i + odd ) return false ; if ( d -> perm [ i + 1 ] != ( ( i + nelt + odd ) & mask ) ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vtrnv16qi_internal ; break ; case V8QImode : gen = gen_neon_vtrnv8qi_internal ; break ; case V8HImode : gen = gen_neon_vtrnv8hi_internal ; break ; case V4HImode : gen = gen_neon_vtrnv4hi_internal ; break ; case V4SImode : gen = gen_neon_vtrnv4si_internal ; break ; case V2SImode : gen = gen_neon_vtrnv2si_internal ; break ; case V2SFmode : gen = gen_neon_vtrnv2sf_internal ; break ; case V4SFmode : gen = gen_neon_vtrnv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN ) { std :: swap ( in0 , in1 ) ; odd = ! odd ; } out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( odd ) std :: swap ( out0 , out1 ) ; emit_insn ( gen ( out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s> void SIInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , Register SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { storeRegToStackSlotImpl ( MBB , MI , SrcReg , isKill , FrameIndex , RC , TRI , false ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool sh_is_nott_insn ( const rtx_insn * i ) { return i != NULL && GET_CODE ( PATTERN ( i ) ) == SET && t_reg_operand ( XEXP ( PATTERN ( i ) , 0 ) , VOIDmode ) && negt_reg_operand ( XEXP ( PATTERN ( i ) , 1 ) , VOIDmode ) ; } </s>

Given an insn , determine whether it 's a 'nott ' insn , i.e . an insn that negates the T bit and stores the result in the T bit .


<s> void Nios2InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { unsigned opc = Subtarget . hasNios2r2 ( ) ? Nios2 :: ADD_R2 : Nios2 :: ADD_R1 ; BuildMI ( MBB , I , DL , get ( opc ) ) . addReg ( DestReg , RegState :: Define ) . addReg ( Nios2 :: ZERO ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } </s>


<s> void X86AvoidSFBPass :: buildCopy ( MachineInstr * LoadInst , unsigned NLoadOpcode , int64_t LoadDisp , MachineInstr * StoreInst , unsigned NStoreOpcode , int64_t StoreDisp , unsigned Size , int64_t LMMOffset , int64_t SMMOffset ) { MachineOperand & LoadBase = getBaseOperand ( LoadInst ) ; MachineOperand & StoreBase = getBaseOperand ( StoreInst ) ; MachineBasicBlock * MBB = LoadInst -> getParent ( ) ; MachineMemOperand * LMMO = * LoadInst -> memoperands_begin ( ) ; MachineMemOperand * SMMO = * StoreInst -> memoperands_begin ( ) ; unsigned Reg1 = MRI -> createVirtualRegister ( TII -> getRegClass ( TII -> get ( NLoadOpcode ) , 0 , TRI , * ( MBB -> getParent ( ) ) ) ) ; BuildMI ( * MBB , LoadInst , LoadInst -> getDebugLoc ( ) , TII -> get ( NLoadOpcode ) , Reg1 ) . add ( LoadBase ) . addImm ( 1 ) . addReg ( X86 :: NoRegister ) . addImm ( LoadDisp ) . addReg ( X86 :: NoRegister ) . addMemOperand ( MBB -> getParent ( ) -> getMachineMemOperand ( LMMO , LMMOffset , Size ) ) ; DEBUG ( LoadInst -> getPrevNode ( ) -> dump ( ) ) ; MachineInstr * StInst = StoreInst ; if ( StoreInst -> getPrevNode ( ) == LoadInst ) StInst = LoadInst ; BuildMI ( * MBB , StInst , StInst -> getDebugLoc ( ) , TII -> get ( NStoreOpcode ) ) . add ( StoreBase ) . addImm ( 1 ) . addReg ( X86 :: NoRegister ) . addImm ( StoreDisp ) . addReg ( X86 :: NoRegister ) . addReg ( Reg1 ) . addMemOperand ( MBB -> getParent ( ) -> getMachineMemOperand ( SMMO , SMMOffset , Size ) ) ; DEBUG ( StInst -> getPrevNode ( ) -> dump ( ) ) ; } </s>


<s> void mmix_setup_frame_addresses ( ) { } </s>


<s> void addPreEmitPass ( ) override { addPass ( createTGSICFGStructurizerPass ( ) , false ) ; addPass ( createTGSIPreEmitImmPass ( getTGSITargetMachine ( ) . MCP ) , false ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static bool avr_decl_absdata_p ( tree decl , tree attributes ) { return ( TREE_CODE ( decl ) == VAR_DECL && NULL_TREE != lookup_attribute ( "absdata" , attributes ) ) ; } </s>

Return true if DECL has attribute ` absdata ' set . This function should only be used for AVR_TINY .


<s> int mt_reg_ok_for_base_p ( rtx x , int strict ) { if ( strict ) return ( ( ( unsigned ) REGNO ( x ) ) < FIRST_PSEUDO_REGISTER ) ; return 1 ; } </s>


Try to add a comment on the PC-relative load .