<s> static void epiphany_setup_incoming_varargs ( cumulative_args_t cum , machine_mode mode , tree type , int * pretend_size , int no_rtl ) { int first_anon_arg ; CUMULATIVE_ARGS next_cum ; machine_function_t * mf = MACHINE_FUNCTION ( cfun ) ; gcc_assert ( mode != BLKmode ) ; next_cum = * get_cumulative_args ( cum ) ; next_cum = ROUND_ADVANCE_CUM ( next_cum , mode , type ) + ROUND_ADVANCE_ARG ( mode , type ) ; first_anon_arg = next_cum ; if ( first_anon_arg < MAX_EPIPHANY_PARM_REGS && ! no_rtl ) { int first_reg_offset = first_anon_arg ; * pretend_size = ( ( MAX_EPIPHANY_PARM_REGS - first_reg_offset ) * UNITS_PER_WORD ) ; } mf -> args_parsed = 1 ; mf -> pretend_args_odd = ( ( * pretend_size & UNITS_PER_WORD ) ? 1 : 0 ) ; } </s>

Do any needed setup for a variadic function . For the EPIPHANY , we actually emit the code in epiphany_expand_prologue . CUM has not been updated for the last named argument which has type TYPE and mode MODE , and we rely on this fact .


<s> AArch64TargetLowering :: ConstraintType AArch64TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'z' : return C_Other ; case 'x' : case 'w' : return C_RegisterClass ; case 'Q' : return C_Memory ; case 'S' : return C_Other ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s>
MachineInstr
*
PPCInstrInfo
::
commuteInstruction
(
MachineInstr
*
MI
,
bool
NewMI
)
const
{
MachineFunction
&
MF
=
*
MI
->
getParent
(
)
->
getParent
(
)
;
if
(
MI
->
getOpcode
(
)
!=
PPC
::
RLWIMI
)
return
TargetInstrInfoImpl
::
commuteInstruction
(
MI
,
NewMI
)
;
if
(
MI
->
getOperand
(
3
)
.
getImm
(
)
!=
0
)
return
0
;
unsigned
Reg0
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
unsigned
Reg1
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
unsigned
Reg2
=
MI
->
getOperand
(
2
)
.
getReg
(
)
;
bool
Reg1IsKill
=
MI
->
getOperand
(
1
)
.
isKill
(
)
;
bool
Reg2IsKill
=
MI
->
getOperand
(
2
)
.
isKill
(
)
;
bool
ChangeReg0
=
false
;
if
(
Reg0
==
Reg1
)
{
assert
(
MI
->
getDesc
(
)
.
getOperandConstraint
(
0
,
MCOI
::
TIED_TO
)
&&
"Expecting a two-address instruction!"
)
;
Reg2IsKill
=
false
;
ChangeReg0
=
true
;
}
unsigned
MB
=
MI
->
getOperand
(
4
)
.
getImm
(
)
;
unsigned
ME
=
MI
->
getOperand
(
5
)
.
getImm
(
)
;
if
(
NewMI
)
{
unsigned
Reg0
=
ChangeReg0
Reg2
:
MI
->
getOperand
(
0
)
.
getReg
(
)
;
bool
Reg0IsDead
=
MI
->
getOperand
(
0
)
.
isDead
(
)
;
return
BuildMI
(
MF
,
MI
->
getDebugLoc
(
)
,
MI
->
getDesc
(
)
)
.
addReg
(
Reg0
,
RegState
::
Define
|
getDeadRegState
(
Reg0IsDead
)
)
.
addReg
(
Reg2
,
getKillRegState
(
Reg2IsKill
)
)
.
addReg
(
Reg1
,
getKillRegState
(
Reg1IsKill
)
)
.
addImm
(
(
ME
+
1
)
&
31
)
.
addImm
(
(
MB
1
)
&
31
)
;
}
if
(
ChangeReg0
)
MI
->
getOperand
(
0
)
.
setReg
(
Reg2
)
;
MI
->
getOperand
(
2
)
.
setReg
(
Reg1
)
;
MI
->
getOperand
(
1
)
.
setReg
(
Reg2
)
;
MI
->
getOperand
(
2
)
.
setIsKill
(
Reg1IsKill
)
;
MI
->
getOperand
(
1
)
.
setIsKill
(
Reg2IsKill
)
;
MI
->
getOperand
(
4
)
.
setImm
(
(
ME
+
1
)
&
31
)
;
MI
->
getOperand
(
5
)
.
setImm
(
(
MB
1
)
&
31
)
;
return
MI
;
}
</s>

This method commutes the operands of the given machine instruction MI .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"R600 Texture Intrinsics Replacer"
;
}
</s>

getPassName - Return a nice clean name for a pass .

AMDGPU
"R600 Texture Intrinsics Replacer"


<s>
unsigned
AArch64TargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"sp"
,
AArch64
::
SP
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
Twine
(
"Invalid register name \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;
}
</s>

Return the register ID of the name passed in .


"invalid id value for interrupt attribute"

FIXME : FOR BACKWARD COMPATIBILITY , we need to support following patterns : __attribute__ ( ( interrupt ( `` XXX ; YYY ; id=ZZZ '' ) ) ) __attribute__ ( ( exception ( `` XXX ; YYY ; id=ZZZ '' ) ) ) __attribute__ ( ( reset ( `` vectors=XXX ; nmi_func=YYY ; warm_func=ZZZ '' ) ) ) We provide several functions to parse the strings .


<s> M680x0Subtarget & M680x0Subtarget :: initializeSubtargetDependencies ( StringRef CPU , Triple TT , StringRef FS , const M680x0TargetMachine & TM ) { std :: string CPUName = selectM680x0CPU ( TT , CPU ) ; IsM68000 = true ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; stackAlignment = 8 ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool M68kPassConfig :: addIRTranslator ( ) { addPass ( new IRTranslator ( ) ) ; return false ; } </s>

This method should install an IR translator pass , which converts from LLVM code to machine instructions with possibly generic opcodes .


<s> void WebAssemblyPassConfig :: addISelPrepare ( ) { addPass ( new CoalesceFeaturesAndStripAtomics ( & getWebAssemblyTargetMachine ( ) ) ) ; addPass ( createAtomicExpandPass ( ) ) ; TargetPassConfig :: addISelPrepare ( ) ; } </s>

Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection .


<s> static bool nios2_symbol_ref_in_small_data_p ( rtx sym ) { tree decl ; gcc_assert ( GET_CODE ( sym ) == SYMBOL_REF ) ; decl = SYMBOL_REF_DECL ( sym ) ; if ( SYMBOL_REF_TLS_MODEL ( sym ) != 0 ) return false ; if ( TARGET_ARCH_R2 && ( TARGET_BYPASS_CACHE || TARGET_BYPASS_CACHE_VOLATILE ) ) return false ; switch ( nios2_gpopt_option ) { case gpopt_none : return false ; case gpopt_local : if ( decl && DECL_SECTION_NAME ( decl ) ) return nios2_small_section_name_p ( DECL_SECTION_NAME ( decl ) ) ; return ( SYMBOL_REF_SMALL_P ( sym ) && ! SYMBOL_REF_EXTERNAL_P ( sym ) && ! ( decl && DECL_WEAK ( decl ) ) && ! ( decl && DECL_COMMON ( decl ) && ( DECL_INITIAL ( decl ) == NULL || ( ! in_lto_p && DECL_INITIAL ( decl ) == error_mark_node ) ) ) ) ; case gpopt_global : return SYMBOL_REF_SMALL_P ( sym ) ; case gpopt_data : return ! SYMBOL_REF_FUNCTION_P ( sym ) ; case gpopt_all : return true ; default : return false ; } } </s>

Return true if symbol is in small data section .


<s> static rtx strip_offset_and_salt ( rtx addr , poly_int64 * offset ) { return strip_salt ( strip_offset ( addr , offset ) ) ; } </s>

Like strip_offset , but also strip any UNSPEC_SALT_ADDR from the expression .


<s> const char * arithmetic_instr ( rtx op , int shift_first_arg ) { switch ( GET_CODE ( op ) ) { case PLUS : return "add" ; case MINUS : return shift_first_arg ? "rsb" : "sub" ; case IOR : return "orr" ; case XOR : return "eor" ; case AND : return "and" ; case ASHIFT : case ASHIFTRT : case LSHIFTRT : case ROTATERT : return arm_shift_nmem ( GET_CODE ( op ) ) ; default : gcc_unreachable ( ) ; } } </s>

Return the appropriate ARM instruction for the operation code . The returned result should not be overwritten . OP is the rtx of the operation . SHIFT_FIRST_ARG is TRUE if the first argument of the operator was shifted .


<s> void X86PassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & LiveRangeShrinkID ) ; addPass ( createX86FixupSetCC ( ) ) ; addPass ( createX86OptimizeLEAs ( ) ) ; addPass ( createX86CallFrameOptimization ( ) ) ; addPass ( createX86AvoidStoreForwardingBlocks ( ) ) ; } addPass ( createX86FlagsCopyLoweringPass ( ) ) ; addPass ( createX86WinAllocaExpander ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> SDNode * GBZ80DAGToDAGISel :: Select ( SDNode * Node ) { DebugLoc dl = Node -> getDebugLoc ( ) ; switch ( Node -> getOpcode ( ) ) { default : break ; } SDNode * ResNode = SelectCode ( Node ) ; return ResNode ; } </s>

Main hook for targets to transform nodes into machine nodes .


Return how many instructions should scheduler lookahead to choose the best one .


<s> bool AMDGPUDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { DominatorTree & DT = getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; LoopInfo * LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; for ( auto & L : LI -> getLoopsInPreorder ( ) ) { assert ( L -> isLCSSAForm ( DT ) ) ; } Subtarget = & MF . getSubtarget < GCNSubtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool nds32_reg_base_load_store_p ( rtx_insn * insn ) { rtx mem_src = NULL_RTX ; switch ( get_attr_type ( insn ) ) { case TYPE_LOAD : mem_src = SET_SRC ( PATTERN ( insn ) ) ; break ; case TYPE_STORE : mem_src = SET_DEST ( PATTERN ( insn ) ) ; break ; default : break ; } if ( mem_src != NULL_RTX ) { if ( ( GET_CODE ( mem_src ) == ZERO_EXTEND ) || ( GET_CODE ( mem_src ) == SIGN_EXTEND ) ) mem_src = XEXP ( mem_src , 0 ) ; if ( GET_CODE ( XEXP ( mem_src , 0 ) ) == REG ) return true ; } return false ; } </s>

Return true if is load/store with REG addressing mode and memory mode is SImode .


Targets may add passes immediately before machine code is emitted in this callback .


<s> static enum aarch64_parse_opt_result aarch64_parse_arch ( const char * to_parse , const struct processor * * res , unsigned long * isa_flags , std :: string * invalid_extension ) { const char * ext ; const struct processor * arch ; size_t len ; ext = strchr ( to_parse , '+' ) ; if ( ext != NULL ) len = ext - to_parse ; else len = strlen ( to_parse ) ; if ( len == 0 ) return AARCH64_PARSE_MISSING_ARG ; for ( arch = all_architectures ; arch -> name != NULL ; arch ++ ) { if ( strlen ( arch -> name ) == len && strncmp ( arch -> name , to_parse , len ) == 0 ) { unsigned long isa_temp = arch -> flags ; if ( ext != NULL ) { enum aarch64_parse_opt_result ext_res = aarch64_parse_extension ( ext , & isa_temp , invalid_extension ) ; if ( ext_res != AARCH64_PARSE_OK ) return ext_res ; } * res = arch ; * isa_flags = isa_temp ; return AARCH64_PARSE_OK ; } } return AARCH64_PARSE_INVALID_ARG ; } </s>

Parse the TO_PARSE string and put the architecture struct that it selects into RES and the architectural features into ISA_FLAGS . Return an aarch64_parse_opt_result describing the parse result . If there is an error parsing , RES and ISA_FLAGS are left unchanged .


<s> bool nds32_n9_last_load_to_ex_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx last_def_reg = extract_nth_access_reg ( producer , - 1 ) ; if ( nds32_register_ports_config == REG_PORT_2R1W ) { if ( post_update_insn_p ( producer ) ) return false ; size_t i ; size_t n_elems = parallel_elements ( producer ) ; rtx base_reg = extract_base_reg ( producer ) ; for ( i = 0 ; i < n_elems ; ++ i ) { rtx load_rtx = extract_nth_access_rtx ( producer , i ) ; rtx list_element = SET_DEST ( load_rtx ) ; if ( rtx_equal_p ( base_reg , list_element ) && i != n_elems - 1 ) { last_def_reg = base_reg ; break ; } } return n9_2r1w_consumed_by_ex_dep_p ( consumer , last_def_reg ) ; } else return n9_3r2w_consumed_by_ex_dep_p ( consumer , last_def_reg ) ; } </s>

Check dependencies from LMW ( N , N ) to EX .


<s> const char * SystemZTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { OPCODE ( RET_FLAG ) ; OPCODE ( CALL ) ; OPCODE ( SIBCALL ) ; OPCODE ( PCREL_WRAPPER ) ; OPCODE ( PCREL_OFFSET ) ; OPCODE ( IABS ) ; OPCODE ( ICMP ) ; OPCODE ( FCMP ) ; OPCODE ( TM ) ; OPCODE ( BR_CCMASK ) ; OPCODE ( SELECT_CCMASK ) ; OPCODE ( ADJDYNALLOC ) ; OPCODE ( EXTRACT_ACCESS ) ; OPCODE ( UMUL_LOHI64 ) ; OPCODE ( SDIVREM64 ) ; OPCODE ( UDIVREM32 ) ; OPCODE ( UDIVREM64 ) ; OPCODE ( MVC ) ; OPCODE ( MVC_LOOP ) ; OPCODE ( NC ) ; OPCODE ( NC_LOOP ) ; OPCODE ( OC ) ; OPCODE ( OC_LOOP ) ; OPCODE ( XC ) ; OPCODE ( XC_LOOP ) ; OPCODE ( CLC ) ; OPCODE ( CLC_LOOP ) ; OPCODE ( STRCMP ) ; OPCODE ( STPCPY ) ; OPCODE ( SEARCH_STRING ) ; OPCODE ( IPM ) ; OPCODE ( SERIALIZE ) ; OPCODE ( ATOMIC_SWAPW ) ; OPCODE ( ATOMIC_LOADW_ADD ) ; OPCODE ( ATOMIC_LOADW_SUB ) ; OPCODE ( ATOMIC_LOADW_AND ) ; OPCODE ( ATOMIC_LOADW_OR ) ; OPCODE ( ATOMIC_LOADW_XOR ) ; OPCODE ( ATOMIC_LOADW_NAND ) ; OPCODE ( ATOMIC_LOADW_MIN ) ; OPCODE ( ATOMIC_LOADW_MAX ) ; OPCODE ( ATOMIC_LOADW_UMIN ) ; OPCODE ( ATOMIC_LOADW_UMAX ) ; OPCODE ( ATOMIC_CMP_SWAPW ) ; OPCODE ( PREFETCH ) ; } return NULL ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static unsigned int insn_is_swappable_p ( swap_web_entry * insn_entry , rtx insn , unsigned int * special ) { if ( GET_CODE ( insn ) == CALL_INSN ) return 0 ; rtx body = PATTERN ( insn ) ; int i = INSN_UID ( insn ) ; if ( insn_entry [ i ] . is_load ) { if ( GET_CODE ( body ) == SET ) { * special = SH_NOSWAP_LD ; return 1 ; } else return 0 ; } if ( insn_entry [ i ] . is_store ) { if ( GET_CODE ( body ) == SET && GET_CODE ( SET_SRC ( body ) ) != UNSPEC ) { * special = SH_NOSWAP_ST ; return 1 ; } else return 0 ; } return rtx_is_swappable_p ( body , special ) ; } </s>

Return 1 iff INSN is an operand that will not be affected by having vector doublewords swapped in memory ( in which case * SPECIAL is unchanged ) , or that can be modified to be correct if vector doublewords are swapped in memory ( in which case * SPECIAL is changed to a value indicating how ) .


<s> static struct machine_function * arm_init_machine_status ( void ) { struct machine_function * machine ; machine = ggc_cleared_alloc < machine_function > ( ) ; machine -> func_type = ARM_FT_UNKNOWN ; return machine ; } </s>

Functions to save and restore machine-specific function data .


<s> static bool indirectable_constant_address_p ( rtx x , bool indirect ATTRIBUTE_UNUSED ) { return CONSTANT_ADDRESS_P ( x ) ; } </s>

Re-definition of CONSTANT_ADDRESS_P , which is true only when there are no SYMBOL_REFs for external symbols present .


<s> static bool aarch64_evpc_sel ( struct expand_vec_perm_d * d ) { machine_mode vmode = d -> vmode ; int unit_size = GET_MODE_UNIT_SIZE ( vmode ) ; if ( d -> vec_flags != VEC_SVE_DATA || unit_size > 8 ) return false ; int n_patterns = d -> perm . encoding ( ) . npatterns ( ) ; poly_int64 vec_len = d -> perm . length ( ) ; for ( int i = 0 ; i < n_patterns ; ++ i ) if ( ! known_eq ( d -> perm [ i ] , i ) && ! known_eq ( d -> perm [ i ] , vec_len + i ) ) return false ; for ( int i = n_patterns ; i < n_patterns * 2 ; i ++ ) if ( ! d -> perm . series_p ( i , n_patterns , i , n_patterns ) && ! d -> perm . series_p ( i , n_patterns , vec_len + i , n_patterns ) ) return false ; if ( d -> testing_p ) return true ; machine_mode pred_mode = aarch64_sve_pred_mode ( vmode ) ; rtx_vector_builder builder ( pred_mode , n_patterns , 2 ) ; for ( int i = 0 ; i < n_patterns * 2 ; i ++ ) { rtx elem = known_eq ( d -> perm [ i ] , i ) ? CONST1_RTX ( BImode ) : CONST0_RTX ( BImode ) ; builder . quick_push ( elem ) ; } rtx const_vec = builder . build ( ) ; rtx pred = force_reg ( pred_mode , const_vec ) ; emit_insn ( gen_vcond_mask ( vmode , vmode , d -> target , d -> op0 , d -> op1 , pred ) ) ; return true ; } </s>

Try to implement D using SVE SEL instruction .


<s> void mips_expand_atomic_qihi ( union mips_gen_fn_ptrs generator , rtx result , rtx mem , rtx oldval , rtx newval ) { rtx orig_addr , memsi_addr , memsi , shift , shiftsi , unshifted_mask ; rtx unshifted_mask_reg , mask , inverted_mask , si_op ; rtx res = NULL ; machine_mode mode ; mode = GET_MODE ( mem ) ; orig_addr = force_reg ( Pmode , XEXP ( mem , 0 ) ) ; memsi_addr = mips_force_binary ( Pmode , AND , orig_addr , force_reg ( Pmode , GEN_INT ( - 4 ) ) ) ; memsi = gen_rtx_MEM ( SImode , memsi_addr ) ; set_mem_alias_set ( memsi , ALIAS_SET_MEMORY_BARRIER ) ; MEM_VOLATILE_P ( memsi ) = MEM_VOLATILE_P ( mem ) ; shift = mips_force_binary ( Pmode , AND , orig_addr , GEN_INT ( 3 ) ) ; if ( TARGET_BIG_ENDIAN ) mips_emit_binary ( XOR , shift , shift , GEN_INT ( mode == QImode ? 3 : 2 ) ) ; mips_emit_binary ( ASHIFT , shift , shift , GEN_INT ( 3 ) ) ; shiftsi = force_reg ( SImode , gen_lowpart ( SImode , shift ) ) ; unshifted_mask = GEN_INT ( GET_MODE_MASK ( mode ) ) ; unshifted_mask_reg = force_reg ( SImode , unshifted_mask ) ; mask = mips_force_binary ( SImode , ASHIFT , unshifted_mask_reg , shiftsi ) ; inverted_mask = gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , inverted_mask , gen_rtx_NOT ( SImode , mask ) ) ) ; if ( oldval != const0_rtx ) { oldval = convert_modes ( SImode , mode , oldval , true ) ; oldval = force_reg ( SImode , oldval ) ; oldval = mips_force_binary ( SImode , ASHIFT , oldval , shiftsi ) ; } if ( newval && newval != const0_rtx ) { newval = convert_modes ( SImode , mode , newval , true ) ; newval = force_reg ( SImode , newval ) ; newval = mips_force_binary ( SImode , ASHIFT , newval , shiftsi ) ; } if ( result ) res = gen_reg_rtx ( SImode ) ; if ( newval ) si_op = generator . fn_6 ( res , memsi , mask , inverted_mask , oldval , newval ) ; else if ( result ) si_op = generator . fn_5 ( res , memsi , mask , inverted_mask , oldval ) ; else si_op = generator . fn_4 ( memsi , mask , inverted_mask , oldval ) ; emit_insn ( si_op ) ; if ( result ) { mips_emit_binary ( AND , res , res , mask ) ; mips_emit_binary ( LSHIFTRT , res , res , shiftsi ) ; mips_emit_move ( result , gen_lowpart ( GET_MODE ( result ) , res ) ) ; } } </s>

Expand a QI or HI mode atomic memory operation . GENERATOR contains a pointer to the gen_ * function that generates the SI mode underlying atomic operation using masks that we calculate . RESULT is the return register for the operation . Its value is NULL if unused . MEM is the location of the atomic access . OLDVAL is the first operand for the operation . NEWVAL is the optional second operand for the operation . Its value is NULL if unused .


<s> const RegisterBankInfo :: InstructionMapping & MipsRegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const RegisterBankInfo :: InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; switch ( Opc ) { case G_ADD : case G_LOAD : case G_STORE : case G_GEP : case G_AND : case G_OR : case G_XOR : case G_SHL : case G_ASHR : case G_LSHR : OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; break ; case G_CONSTANT : case G_FRAME_INDEX : case G_GLOBAL_VALUE : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr } ) ; break ; default : return getInvalidInstructionMapping ( ) ; } return getInstructionMapping ( DefaultMappingID , 1 , OperandsMapping , NumOperands ) ; } </s>

Get the mapping of the different operands of MI on the register bank .

Mips Mips Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx 1


<s> bool NVPTXDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintCode ) { default : return true ; case 'm' : if ( SelectDirectAddr ( Op , Op0 ) ) { OutOps . push_back ( Op0 ) ; OutOps . push_back ( CurDAG -> getTargetConstant ( 0 , MVT :: i32 ) ) ; return false ; } if ( SelectADDRri ( Op . getNode ( ) , Op , Op0 , Op1 ) ) { OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } break ; } return true ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s>
bool
LanaiInstrInfo
::
areMemAccessesTriviallyDisjoint
(
const
MachineInstr
&
MIa
,
const
MachineInstr
&
MIb
,
AliasAnalysis
*
)
const
{
assert
(
MIa
.
mayLoadOrStore
(
)
&&
"MIa must be a load or store."
)
;
assert
(
MIb
.
mayLoadOrStore
(
)
&&
"MIb must be a load or store."
)
;
if
(
MIa
.
hasUnmodeledSideEffects
(
)
||
MIb
.
hasUnmodeledSideEffects
(
)
||
MIa
.
hasOrderedMemoryRef
(
)
||
MIb
.
hasOrderedMemoryRef
(
)
)
return
false
;
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
const
MachineOperand
*
BaseOpA
=
nullptr
,
*
BaseOpB
=
nullptr
;
int64_t
OffsetA
=
0
,
OffsetB
=
0
;
unsigned
int
WidthA
=
0
,
WidthB
=
0
;
if
(
getMemOperandWithOffsetWidth
(
MIa
,
BaseOpA
,
OffsetA
,
WidthA
,
TRI
)
&&
getMemOperandWithOffsetWidth
(
MIb
,
BaseOpB
,
OffsetB
,
WidthB
,
TRI
)
)
{
if
(
BaseOpA
->
isIdenticalTo
(
*
BaseOpB
)
)
{
int
LowOffset
=
std
::
min
(
OffsetA
,
OffsetB
)
;
int
HighOffset
=
std
::
max
(
OffsetA
,
OffsetB
)
;
int
LowWidth
=
(
LowOffset
==
OffsetA
)
WidthA
:
WidthB
;
if
(
LowOffset
+
LowWidth
<=
HighOffset
)
return
true
;
}
}
return
false
;
}
</s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> SDValue AArch64TargetLowering :: getGOT ( NodeTy * N , SelectionDAG & DAG ) const { DEBUG ( dbgs ( ) << "AArch64TargetLowering::getGOT\n" ) ; SDLoc DL ( N ) ; EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue GotAddr = getTargetNode ( N , Ty , DAG , AArch64II :: MO_GOT ) ; return DAG . getNode ( AArch64ISD :: LOADgot , DL , Ty , GotAddr ) ; } </s>

Return a pseudo source value referencing the global offset table ( or something the like ) .


<s> bool HexagonTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; if ( MF . getSubtarget < HexagonSubtarget > ( ) . useHVXOps ( ) ) return CCInfo . CheckReturn ( Outs , RetCC_Hexagon_HVX ) ; return CCInfo . CheckReturn ( Outs , RetCC_Hexagon ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .

Hexagon Hexagon ISD::OutputArg 16 Hexagon Hexagon Hexagon


<s> bool arm_rtx_shift_left_p ( rtx x ) { enum rtx_code code = GET_CODE ( x ) ; if ( code == MULT && CONST_INT_P ( XEXP ( x , 1 ) ) && exact_log2 ( INTVAL ( XEXP ( x , 1 ) ) ) > 0 ) return true ; if ( code == ASHIFT ) return true ; return false ; } </s>

Return TRUE if X is either an arithmetic shift left , or is a multiplication by a power of two .


<s> SDValue AMDGPUTargetLowering :: getNegatedExpression ( SDValue Op , SelectionDAG & DAG , bool LegalOperations , bool ForCodeSize , NegatibleCost & Cost , unsigned Depth ) const { switch ( Op . getOpcode ( ) ) { case ISD :: FMA : case ISD :: FMAD : { if ( ! allUsesHaveSourceMods ( Op . getNode ( ) ) ) return SDValue ( ) ; break ; } default : break ; } return TargetLowering :: getNegatedExpression ( Op , DAG , LegalOperations , ForCodeSize , Cost , Depth ) ; } </s>

Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate that if it is cheaper or neutral to do the negation .


<s> void visium_expand_epilogue ( void ) { const int save_area_size = current_frame_info . save_area_size ; const int reg_size1 = current_frame_info . reg_size1 ; const int max_reg1 = current_frame_info . max_reg1 ; const int reg_size2 = current_frame_info . reg_size2 ; const int var_size = current_frame_info . var_size ; const int restore_fp = current_frame_info . save_fp ; const int restore_lr = current_frame_info . save_lr ; const int lr_slot = current_frame_info . lr_slot ; const int local_frame_offset = ( restore_fp + restore_lr + lr_slot ) * UNITS_PER_WORD ; const int combine = current_frame_info . combine ; int reg_size ; int last_reg ; int fsize ; if ( ! crtl -> sp_is_unchanging ) emit_insn ( gen_stack_restore ( ) ) ; if ( restore_fp ) { rtx src ; if ( TARGET_MCM && ! crtl -> sp_is_unchanging ) src = gen_frame_mem ( SImode , hard_frame_pointer_rtx ) ; else src = gen_frame_mem ( SImode , stack_pointer_rtx ) ; rtx insn = emit_frame_insn ( gen_movsi ( hard_frame_pointer_rtx , src ) ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( VOIDmode , stack_pointer_rtx , hard_frame_pointer_rtx ) ) ; visium_add_cfa_restore_note ( hard_frame_pointer_rtx ) ; } if ( restore_lr ) { rtx mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , restore_fp * UNITS_PER_WORD ) ) ; rtx reg = gen_rtx_REG ( SImode , LINK_REGNUM ) ; emit_insn ( gen_movsi ( reg , mem ) ) ; visium_add_cfa_restore_note ( reg ) ; } if ( reg_size2 ) { reg_size = reg_size2 ; last_reg = max_reg1 + 1 ; fsize = local_frame_offset + var_size + reg_size2 ; } else { reg_size = reg_size1 ; last_reg = 0 ; fsize = local_frame_offset + var_size + reg_size1 + save_area_size ; } if ( reg_size && combine ) visium_restore_regs ( fsize , local_frame_offset + var_size , FIRST_PSEUDO_REGISTER - 1 , last_reg ) ; else if ( fsize ) { const int pop_size = reg_size ? local_frame_offset + var_size : fsize ; rtx insn ; if ( pop_size > 65535 ) { rtx tmp = gen_rtx_REG ( SImode , PROLOGUE_TMP_REGNUM ) ; emit_move_insn ( tmp , GEN_INT ( pop_size ) ) ; insn = emit_frame_insn ( gen_stack_pop ( tmp ) ) ; } else insn = emit_frame_insn ( gen_stack_pop ( GEN_INT ( pop_size ) ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( pop_size ) ) ) ) ; visium_add_queued_cfa_restore_notes ( insn ) ; } if ( reg_size && ! combine ) visium_restore_regs ( fsize - local_frame_offset - var_size , 0 , FIRST_PSEUDO_REGISTER - 1 , last_reg ) ; if ( reg_size2 ) visium_restore_regs ( reg_size1 + save_area_size , 0 , max_reg1 , 0 ) ; if ( crtl -> calls_eh_return ) emit_insn ( gen_stack_pop ( EH_RETURN_STACKADJ_RTX ) ) ; } </s>

This function generates the code for function exit .


<s> uint64_t MipsFrameLowering :: estimateStackSize ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; int64_t Offset = 0 ; for ( int I = MFI . getObjectIndexBegin ( ) ; I != 0 ; ++ I ) Offset = std :: max ( Offset , - MFI . getObjectOffset ( I ) ) ; for ( const MCPhysReg * R = TRI . getCalleeSavedRegs ( & MF ) ; * R ; ++ R ) { unsigned Size = TRI . getMinimalPhysRegClass ( * R ) -> getSize ( ) ; Offset = alignTo ( Offset + Size , Size ) ; } unsigned MaxAlign = MFI . getMaxAlignment ( ) ; assert ( ! MFI . getObjectIndexEnd ( ) || MaxAlign ) ; for ( unsigned I = 0 , E = MFI . getObjectIndexEnd ( ) ; I != E ; ++ I ) Offset = alignTo ( Offset + MFI . getObjectSize ( I ) , MaxAlign ) ; if ( MFI . adjustsStack ( ) && hasReservedCallFrame ( MF ) ) Offset = alignTo ( Offset + MFI . getMaxCallFrameSize ( ) , std :: max ( MaxAlign , getStackAlignment ( ) ) ) ; return alignTo ( Offset , getStackAlignment ( ) ) ; } </s>

Estimate and return the size of the stack frame .


<s> TargetLoweringBase :: LegalizeTypeAction getPreferredVectorAction ( EVT VT ) const override { if ( VT . getVectorElementType ( ) . getSizeInBits ( ) % 8 == 0 ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s> bool PIC16AsmPrinter :: doFinalization ( Module & M ) { EmitAllAutos ( M ) ; printLibcallDecls ( ) ; DbgInfo . EndModule ( M ) ; OutStreamer . EmitRawText ( StringRef ( "\tEND" ) ) ; return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> bool aarch64_sve_dup_immediate_p ( rtx x ) { x = aarch64_bit_representation ( unwrap_const_vec_duplicate ( x ) ) ; if ( ! CONST_INT_P ( x ) ) return false ; HOST_WIDE_INT val = INTVAL ( x ) ; if ( val & 0xff ) return IN_RANGE ( val , - 0x80 , 0x7f ) ; return IN_RANGE ( val , - 0x8000 , 0x7f00 ) ; } </s>

Return true if X is a valid immediate for the SVE DUP and CPY instructions .


<s> static bool rs6000_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { return rs6000_hard_regno_mode_ok_p [ mode ] [ regno ] ; } </s>

Value is 1 if hard register REGNO can hold a value of machine-mode MODE .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> bool AMDGPUTargetLowering :: isFAbsFree ( EVT VT ) const { assert ( VT . isFloatingPoint ( ) ) ; return VT == MVT :: f32 || VT == MVT :: f64 ; } </s>

Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation .


"Frame offsets outside of the signed 32-bit range not supported"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static bool mips_matching_cpu_name_p ( const char * canonical , const char * given ) { if ( mips_strict_matching_cpu_name_p ( canonical , given ) ) return true ; if ( TOLOWER ( * given ) == 'r' ) given ++ ; if ( ! ISDIGIT ( * given ) ) return false ; if ( TOLOWER ( canonical [ 0 ] ) == 'v' && TOLOWER ( canonical [ 1 ] ) == 'r' ) canonical += 2 ; else if ( TOLOWER ( canonical [ 0 ] ) == 'r' && TOLOWER ( canonical [ 1 ] ) == 'm' ) canonical += 2 ; else if ( TOLOWER ( canonical [ 0 ] ) == 'r' ) canonical += 1 ; return mips_strict_matching_cpu_name_p ( canonical , given ) ; } </s>

Return true if GIVEN matches CANONICAL , where GIVEN is a user-supplied CPU name . We 've traditionally allowed a lot of variation here . Note : this function is shared between GCC and GAS .


<s> const TargetRegisterClass * PPCRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC ) const { if ( Subtarget . hasVSX ( ) ) { if ( RC == & PPC :: F8RCRegClass ) return & PPC :: VSFRCRegClass ; else if ( RC == & PPC :: VRRCRegClass ) return & PPC :: VSRCRegClass ; } return TargetRegisterInfo :: getLargestLegalSuperClass ( RC ) ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .

PowerPC PPC PPC::F8RCRegClass PPC::VSFRCRegClass PPC::VRRCRegClass PPC::VSRCRegClass


<s> bool mips_pad_arg_upward ( enum machine_mode mode , tree type ) { if ( ! BYTES_BIG_ENDIAN ) return true ; if ( type != 0 ? INTEGRAL_TYPE_P ( type ) || POINTER_TYPE_P ( type ) : GET_MODE_CLASS ( mode ) == MODE_INT ) return false ; if ( mips_abi == ABI_O64 ) if ( type != 0 ? FLOAT_TYPE_P ( type ) : GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return false ; if ( mips_abi != ABI_EABI ) return true ; if ( mode != BLKmode ) return ( GET_MODE_BITSIZE ( mode ) >= PARM_BOUNDARY ) ; else return ( int_size_in_bytes ( type ) >= ( PARM_BOUNDARY / BITS_PER_UNIT ) ) ; } </s>

Return true if FUNCTION_ARG_PADDING ( MODE , TYPE ) should return upward rather than downward . In other words , return true if the first byte of the stack slot has useful data , false if the last byte does .


<s> virtual const TargetRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> Optional < ParamLoadedValue > ARMBaseInstrInfo :: describeLoadedValue ( const MachineInstr & MI , Register Reg ) const { if ( auto DstSrcPair = isCopyInstrImpl ( MI ) ) { Register DstReg = DstSrcPair -> Destination -> getReg ( ) ; if ( DstReg != Reg ) return None ; } return TargetInstrInfo :: describeLoadedValue ( MI , Reg ) ; } </s>

Produce the expression describing the MI loading a value into the physical register Reg .


<s> bool isToken ( ) const override { return Kind == k_Token ; } </s>


<s> static bool cortex_a9_sched_adjust_cost ( rtx_insn * insn , rtx link , rtx_insn * dep , int * cost ) { switch ( REG_NOTE_KIND ( link ) ) { case REG_DEP_ANTI : * cost = 0 ; return false ; case REG_DEP_TRUE : case REG_DEP_OUTPUT : if ( recog_memoized ( insn ) >= 0 && recog_memoized ( dep ) >= 0 ) { if ( GET_CODE ( PATTERN ( insn ) ) == SET ) { if ( GET_MODE_CLASS ( GET_MODE ( SET_DEST ( PATTERN ( insn ) ) ) ) == MODE_FLOAT || GET_MODE_CLASS ( GET_MODE ( SET_SRC ( PATTERN ( insn ) ) ) ) == MODE_FLOAT ) { enum attr_type attr_type_insn = get_attr_type ( insn ) ; enum attr_type attr_type_dep = get_attr_type ( dep ) ; if ( REG_P ( SET_DEST ( PATTERN ( insn ) ) ) && reg_set_p ( SET_DEST ( PATTERN ( insn ) ) , dep ) ) { if ( ( attr_type_insn == TYPE_FMACS || attr_type_insn == TYPE_FMACD ) && ( attr_type_dep == TYPE_FMACS || attr_type_dep == TYPE_FMACD ) ) { if ( REG_NOTE_KIND ( link ) == REG_DEP_OUTPUT ) * cost = insn_default_latency ( dep ) - 3 ; else * cost = insn_default_latency ( dep ) ; return false ; } else { if ( REG_NOTE_KIND ( link ) == REG_DEP_OUTPUT ) * cost = insn_default_latency ( dep ) + 1 ; else * cost = insn_default_latency ( dep ) ; } return false ; } } } } break ; default : gcc_unreachable ( ) ; } return true ; } </s>


<s> int X86FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const X86RegisterInfo * RegInfo = MF . getSubtarget < X86Subtarget > ( ) . getRegisterInfo ( ) ; if ( RegInfo -> hasBasePointer ( MF ) ) FrameReg = RegInfo -> getBaseRegister ( ) ; else if ( RegInfo -> needsStackRealignment ( MF ) ) FrameReg = RegInfo -> getStackRegister ( ) ; else FrameReg = RegInfo -> getFrameRegister ( MF ) ; return getFrameIndexOffset ( MF , FI ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> void TLCS900AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { TLCS900MCInstLower MCInstLowering ( OutContext , * Mang , * this ) ; MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; OutStreamer . EmitInstruction ( TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> MCELFStreamer & getStreamer ( ) { return static_cast < MCELFStreamer & > ( Streamer ) ; } </s>

Return the output streamer for the assembler .


<s> void XCoreInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , get ( XCore :: STWFI ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> int rs6000_adjust_insn_length ( rtx_insn * insn , int length ) { if ( TARGET_PREFIXED && NONJUMP_INSN_P ( insn ) ) { rtx pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) != USE && GET_CODE ( pattern ) != CLOBBER && get_attr_prefixed ( insn ) == PREFIXED_YES ) { int num_prefixed = get_attr_max_prefixed_insns ( insn ) ; length += 4 * ( num_prefixed + 1 ) ; } } return length ; } </s>

Adjust the length of an INSN . LENGTH is the currently-computed length and should be adjusted to reflect any required changes . This macro is used when there is some systematic length adjustment required that would be difficult to express in the length attribute . In the PowerPC , we use this to adjust the length of an instruction if one or more prefixed instructions are generated , using the attribute num_prefixed_insns . A prefixed instruction is 8 bytes instead of 4 , but the hardware requires that a prefied instruciton does not cross a 64-byte boundary . This means the compiler has to assume the length of the first prefixed instruction is 12 bytes instead of 8 bytes . Since the length is already set for the non-prefixed instruction , we just need to udpate for the difference .


<s> const XtensaInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> unsigned getNumberOfRegisters ( bool Vector ) { if ( Vector ) { return 0 ; } return 12 ; } </s>


<s> BitVector PatmosRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; Reserved . set ( Patmos :: R0 ) ; Reserved . set ( Patmos :: P0 ) ; Reserved . set ( Patmos :: S0 ) ; Reserved . set ( Patmos :: S1 ) ; Reserved . set ( Patmos :: SL ) ; Reserved . set ( Patmos :: SH ) ; Reserved . set ( Patmos :: S4 ) ; Reserved . set ( Patmos :: SS ) ; Reserved . set ( Patmos :: ST ) ; Reserved . set ( Patmos :: SRB ) ; Reserved . set ( Patmos :: SRO ) ; Reserved . set ( Patmos :: SXB ) ; Reserved . set ( Patmos :: SXO ) ; Reserved . set ( Patmos :: S11 ) ; Reserved . set ( Patmos :: S12 ) ; Reserved . set ( Patmos :: S13 ) ; Reserved . set ( Patmos :: S14 ) ; Reserved . set ( Patmos :: S15 ) ; Reserved . set ( Patmos :: RSP ) ; Reserved . set ( Patmos :: RFP ) ; Reserved . set ( Patmos :: RTR ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( Patmos :: RFP ) ; if ( PatmosSinglePathInfo :: isEnabled ( MF ) ) { Reserved . set ( Patmos :: R26 ) ; Reserved . set ( Patmos :: P6 ) ; Reserved . set ( Patmos :: P7 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void NVPTXPassConfig :: addFastRegAlloc ( ) { addPass ( & PHIEliminationID ) ; addPass ( & TwoAddressInstructionPassID ) ; } </s>

addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast register allocation .


<s> void CSKYAsmPrinter :: emitFunctionBodyEnd ( ) { if ( ! InConstantPool ) return ; InConstantPool = false ; } </s>

Targets can override this to emit stuff after the last basic block in the function .


<s>
unsigned
WebAssemblyInstrInfo
::
insertBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
TBB
,
MachineBasicBlock
*
FBB
,
ArrayRef
<
MachineOperand
>
Cond
,
const
DebugLoc
&
DL
,
int
*
BytesAdded
)
const
{
assert
(
!
BytesAdded
&&
"code size not handled"
)
;
if
(
Cond
.
empty
(
)
)
{
if
(
!
TBB
)
return
0
;
BuildMI
(
&
MBB
,
DL
,
get
(
WebAssembly
::
BR
)
)
.
addMBB
(
TBB
)
;
return
1
;
}
assert
(
Cond
.
size
(
)
==
2
&&
"Expected a flag and a successor block"
)
;
if
(
Cond
[
0
]
.
getImm
(
)
)
{
BuildMI
(
&
MBB
,
DL
,
get
(
WebAssembly
::
BR_IF
)
)
.
addMBB
(
TBB
)
.
addOperand
(
Cond
[
1
]
)
;
}
else
{
BuildMI
(
&
MBB
,
DL
,
get
(
WebAssembly
::
BR_UNLESS
)
)
.
addMBB
(
TBB
)
.
addOperand
(
Cond
[
1
]
)
;
}
if
(
!
FBB
)
return
1
;
BuildMI
(
&
MBB
,
DL
,
get
(
WebAssembly
::
BR
)
)
.
addMBB
(
FBB
)
;
return
2
;
}
</s>

Insert branch code into the end of the specified MachineBasicBlock .


<s> void unicosmk_output_align ( FILE * file , int align ) { if ( inside_function ) fprintf ( file , "\tgcc@code@align\t%d\n" , align ) ; else fprintf ( file , "\t.align\t%d\n" , align ) ; } </s>

Output an alignment directive . We have to use the macro 'gcc @ code @ align ' in code sections because .align fill unused space with zeroes .


<s> MVT getScalarShiftAmountTy ( EVT LHSTy ) const override { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> void ARMConstantPoolValue :: print ( raw_ostream & O ) const { if ( GV ) O << GV -> getName ( ) ; else O << S ; if ( Modifier ) O << "(" << Modifier << ")" ; if ( PCAdjust != 0 ) { O << "-(LPC" << LabelId << "+" << ( unsigned ) PCAdjust ; if ( AddCurrentAddress ) O << "-." ; O << ")" ; } } </s>

print - Print a debug representation of the operand to the given stream .


<s> bool ARMTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned Alignment , MachineMemOperand :: Flags , bool * Fast ) const { if ( ! VT . isSimple ( ) ) return false ; bool AllowsUnaligned = Subtarget -> allowsUnalignedMem ( ) ; auto Ty = VT . getSimpleVT ( ) . SimpleTy ; if ( Ty == MVT :: i8 || Ty == MVT :: i16 || Ty == MVT :: i32 ) { if ( AllowsUnaligned ) { if ( Fast ) * Fast = Subtarget -> hasV7Ops ( ) ; return true ; } } if ( Ty == MVT :: f64 || Ty == MVT :: v2f64 ) { if ( Subtarget -> hasNEON ( ) && ( AllowsUnaligned || Subtarget -> isLittle ( ) ) ) { if ( Fast ) * Fast = true ; return true ; } } if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; if ( ( Ty == MVT :: v16i1 || Ty == MVT :: v8i1 || Ty == MVT :: v4i1 ) ) { if ( Fast ) * Fast = true ; return true ; } if ( Ty != MVT :: v16i8 && Ty != MVT :: v8i16 && Ty != MVT :: v8f16 && Ty != MVT :: v4i32 && Ty != MVT :: v4f32 && Ty != MVT :: v2i64 && Ty != MVT :: v2f64 && Ty != MVT :: v4i8 && Ty != MVT :: v8i8 && Ty != MVT :: v4i16 ) return false ; if ( Subtarget -> isLittle ( ) ) { if ( Fast ) * Fast = true ; return true ; } else { if ( Ty == MVT :: v16i8 || ( ( Ty == MVT :: v8i16 || Ty == MVT :: v8f16 ) && Alignment >= 2 ) || ( ( Ty == MVT :: v4i32 || Ty == MVT :: v4f32 ) && Alignment >= 4 ) ) { if ( Fast ) * Fast = true ; return true ; } } return false ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> bool RISCVAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { MCSubtargetInfo & NewSTI = OutStreamer -> getContext ( ) . getSubtargetCopy ( * TM . getMCSubtargetInfo ( ) ) ; NewSTI . setFeatureBits ( MF . getSubtarget ( ) . getFeatureBits ( ) ) ; STI = & NewSTI ; SetupMachineFunction ( MF ) ; emitFunctionBody ( ) ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> int sh_loop_align ( rtx_insn * label ) { rtx_insn * next = label ; if ( ! optimize || optimize_size ) return 0 ; do next = next_nonnote_insn ( next ) ; while ( next && LABEL_P ( next ) ) ; if ( ! next || ! INSN_P ( next ) || recog_memoized ( next ) == CODE_FOR_consttable_2 ) return 0 ; return align_loops_log ; } </s>

If we are inside a phony loop , almost any kind of label can turn up as the first one in the loop . Aligning a braf label causes incorrect switch destination addresses ; we can detect braf labels because they are followed by a BARRIER . Applying loop alignment to small constant or switch tables is a waste of space , so we suppress this too .


<s>
bool
AArch64LegalizerInfo
::
legalizeCustom
(
LegalizerHelper
&
Helper
,
MachineInstr
&
MI
)
const
{
MachineIRBuilder
&
MIRBuilder
=
Helper
.
MIRBuilder
;
MachineRegisterInfo
&
MRI
=
*
MIRBuilder
.
getMRI
(
)
;
GISelChangeObserver
&
Observer
=
Helper
.
Observer
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
return
false
;
case
TargetOpcode
::
G_VAARG
:
return
legalizeVaArg
(
MI
,
MRI
,
MIRBuilder
)
;
case
TargetOpcode
::
G_LOAD
:
case
TargetOpcode
::
G_STORE
:
return
legalizeLoadStore
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
case
TargetOpcode
::
G_SHL
:
case
TargetOpcode
::
G_ASHR
:
case
TargetOpcode
::
G_LSHR
:
return
legalizeShlAshrLshr
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
case
TargetOpcode
::
G_GLOBAL_VALUE
:
return
legalizeSmallCMGlobalValue
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
}
llvm_unreachable
(
"expected switch to return"
)
;
}
</s>

Called for instructions with the Custom LegalizationAction .


<s> static bool ix86_expand_vector_init_one_var ( bool mmx_ok , enum machine_mode mode , rtx target , rtx vals , int one_var ) { rtx var = XVECEXP ( vals , 0 , one_var ) ; enum machine_mode wmode ; rtx const_vec , x ; const_vec = copy_rtx ( vals ) ; XVECEXP ( const_vec , 0 , one_var ) = CONST0_RTX ( GET_MODE_INNER ( mode ) ) ; const_vec = gen_rtx_CONST_VECTOR ( mode , XVEC ( const_vec , 0 ) ) ; switch ( mode ) { case V2DFmode : case V2DImode : case V2SFmode : case V2SImode : return false ; case V4SFmode : case V4SImode : case V8HImode : case V4HImode : break ; case V16QImode : wmode = V8HImode ; goto widen ; case V8QImode : wmode = V4HImode ; goto widen ; widen : x = XVECEXP ( vals , 0 , one_var ^ 1 ) ; if ( one_var & 1 ) { var = convert_modes ( HImode , QImode , var , true ) ; var = expand_simple_binop ( HImode , ASHIFT , var , GEN_INT ( 8 ) , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; x = GEN_INT ( INTVAL ( x ) & 0xff ) ; } else { var = convert_modes ( HImode , QImode , var , true ) ; x = gen_int_mode ( INTVAL ( x ) << 8 , HImode ) ; } if ( x != const0_rtx ) var = expand_simple_binop ( HImode , IOR , var , x , var , 1 , OPTAB_LIB_WIDEN ) ; x = gen_reg_rtx ( wmode ) ; emit_move_insn ( x , gen_lowpart ( wmode , const_vec ) ) ; ix86_expand_vector_set ( mmx_ok , x , var , one_var >> 1 ) ; emit_move_insn ( target , gen_lowpart ( mode , x ) ) ; return true ; default : return false ; } emit_move_insn ( target , const_vec ) ; ix86_expand_vector_set ( mmx_ok , target , var , one_var ) ; return true ; } </s>

A subroutine of ix86_expand_vector_init . Store into TARGET a vector consisting of the values in VALS . It is known that all elements except ONE_VAR are constants . Return true if successful .


<s> void X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { bool reserveCallFrame = hasReservedCallFrame ( MF ) ; unsigned Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t InternalAmt = ( isDestroy || Amount ) ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { unsigned StackAlign = getStackAlignment ( ) ; Amount = RoundUpToAlignment ( Amount , StackAlign ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const Function * Fn = MF . getFunction ( ) ; bool WindowsCFI = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool DwarfCFI = ! WindowsCFI && ( MMI . hasDebugInfo ( ) || Fn -> needsUnwindTableEntry ( ) ) ; bool HasDwarfEHHandlers = ! WindowsCFI && ! MF . getMMI ( ) . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < X86MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , I , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == 0 ) return ; Amount -= InternalAmt ; if ( isDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) ) BuildCFI ( MBB , I , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ; if ( Amount ) { int Offset = isDestroy ? Amount : - Amount ; if ( ! ( Fn -> optForMinSize ( ) && adjustStackWithPops ( MBB , I , DL , Offset ) ) ) BuildStackAdjustment ( MBB , I , DL , Offset , false ) ; } if ( DwarfCFI && ! hasFP ( MF ) ) { int CFAOffset = Amount ; if ( CFAOffset ) { CFAOffset = isDestroy ? - CFAOffset : CFAOffset ; BuildCFI ( MBB , I , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , CFAOffset ) ) ; } } return ; } if ( isDestroy && InternalAmt ) { MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! std :: prev ( I ) -> isCall ( ) ) -- I ; BuildStackAdjustment ( MBB , I , DL , - InternalAmt , false ) ; } } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s>
uint32_t
AMDGPUTargetLowering
::
getImplicitParameterOffset
(
const
AMDGPUMachineFunction
*
MFI
,
const
ImplicitParameter
Param
)
const
{
uint64_t
ArgOffset
=
MFI
->
ABIArgOffset
;
switch
(
Param
)
{
case
GRID_DIM
:
return
ArgOffset
;
case
GRID_OFFSET
:
return
ArgOffset
+
4
;
}
llvm_unreachable
(
"unexpected implicit parameter type"
)
;
}
</s>

Helper function that returns the byte offset of the given type of implicit parameter .

AMDGPU
AMDGPU
AMDGPU
4
"unexpected implicit parameter type"


<s> static bool cdxreg ( rtx op ) { return REG_P ( op ) && ( ! reload_completed || CDX_REG_P ( REGNO ( op ) ) ) ; } </s>

Returns true if OP is a REG and assigned a CDX reg .


<s>
void
rvexAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
SmallString
<
128
>
Str
;
raw_svector_ostream
OS
(
Str
)
;
DEBUG
(
errs
(
)
<<
"MI:"
<<
MI
<<
"\n"
)
;
if
(
MI
->
isBundle
(
)
)
{
DEBUG
(
errs
(
)
<<
"MI bundle:"
<<
MI
<<
"\n"
)
;
std
::
vector
<
const
MachineInstr
*
>
BundleMIs
;
unsigned
int
IgnoreCount
=
0
;
MachineBasicBlock
::
const_instr_iterator
MII
=
MI
;
MachineBasicBlock
::
const_instr_iterator
MBBe
=
MI
->
getParent
(
)
->
instr_end
(
)
;
++
MII
;
while
(
MII
!=
MBBe
&&
MII
->
isInsideBundle
(
)
)
{
const
MachineInstr
*
MInst
=
MII
;
if
(
MInst
->
getOpcode
(
)
==
TargetOpcode
::
DBG_VALUE
||
MInst
->
getOpcode
(
)
==
TargetOpcode
::
IMPLICIT_DEF
)
{
IgnoreCount
++
;
}
else
{
BundleMIs
.
push_back
(
MInst
)
;
}
++
MII
;
}
unsigned
Size
=
BundleMIs
.
size
(
)
;
assert
(
(
Size
+
IgnoreCount
)
==
MI
->
getBundleSize
(
)
&&
"Corrupt Bundle!"
)
;
for
(
unsigned
Index
=
0
;
Index
<
Size
;
++
Index
)
{
const
MachineInstr
*
BMI
=
BundleMIs
[
Index
]
;
MCInst
TmpInst0
;
MCInstLowering
.
Lower
(
BMI
,
TmpInst0
)
;
OutStreamer
.
EmitInstruction
(
TmpInst0
)
;
DEBUG
(
errs
(
)
<<
"inst:"
<<
TmpInst0
<<
"\n"
)
;
}
OutStreamer
.
EmitRawText
(
StringRef
(
";;\n\n"
)
)
;
}
else
{
MCInst
TmpInst0
;
MCInstLowering
.
Lower
(
MI
,
TmpInst0
)
;
OutStreamer
.
EmitInstruction
(
TmpInst0
)
;
OutStreamer
.
EmitRawText
(
StringRef
(
";;\n\n"
)
)
;
}
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .

rvex
rvex
128
"MI:"
"\n"
"MI bundle:"
"\n"
0
"Corrupt Bundle!"
0
"inst:"
"\n"
";;\n\n"
";;\n\n"


<s> static void riscv_block_move_loop ( rtx dest , rtx src , unsigned HOST_WIDE_INT length , unsigned HOST_WIDE_INT bytes_per_iter ) { rtx label , src_reg , dest_reg , final_src , test ; unsigned HOST_WIDE_INT leftover ; leftover = length % bytes_per_iter ; length -= leftover ; riscv_adjust_block_mem ( src , bytes_per_iter , & src_reg , & src ) ; riscv_adjust_block_mem ( dest , bytes_per_iter , & dest_reg , & dest ) ; final_src = expand_simple_binop ( Pmode , PLUS , src_reg , GEN_INT ( length ) , 0 , 0 , OPTAB_WIDEN ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; riscv_block_move_straight ( dest , src , bytes_per_iter ) ; riscv_emit_move ( src_reg , plus_constant ( Pmode , src_reg , bytes_per_iter ) ) ; riscv_emit_move ( dest_reg , plus_constant ( Pmode , dest_reg , bytes_per_iter ) ) ; test = gen_rtx_NE ( VOIDmode , src_reg , final_src ) ; if ( Pmode == DImode ) emit_jump_insn ( gen_cbranchdi4 ( test , src_reg , final_src , label ) ) ; else emit_jump_insn ( gen_cbranchsi4 ( test , src_reg , final_src , label ) ) ; if ( leftover ) riscv_block_move_straight ( dest , src , leftover ) ; else emit_insn ( gen_nop ( ) ) ; } </s>

Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER bytes at a time . LENGTH must be at least BYTES_PER_ITER . Assume that the memory regions do not overlap .


<s>
unsigned
ARMMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
{
unsigned
Reg
=
MO
.
getReg
(
)
;
unsigned
RegNo
=
CTX
.
getRegisterInfo
(
)
->
getEncodingValue
(
Reg
)
;
if
(
STI
.
getFeatureBits
(
)
[
ARM
::
HasMVEIntegerOps
]
)
return
RegNo
;
switch
(
Reg
)
{
default
:
return
RegNo
;
case
ARM
::
Q0
:
case
ARM
::
Q1
:
case
ARM
::
Q2
:
case
ARM
::
Q3
:
case
ARM
::
Q4
:
case
ARM
::
Q5
:
case
ARM
::
Q6
:
case
ARM
::
Q7
:
case
ARM
::
Q8
:
case
ARM
::
Q9
:
case
ARM
::
Q10
:
case
ARM
::
Q11
:
case
ARM
::
Q12
:
case
ARM
::
Q13
:
case
ARM
::
Q14
:
case
ARM
::
Q15
:
return
2
*
RegNo
;
}
}
else
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
else
if
(
MO
.
isFPImm
(
)
)
{
return
static_cast
<
unsigned
>
(
APFloat
(
MO
.
getFPImm
(
)
)
.
bitcastToAPInt
(
)
.
getHiBits
(
32
)
.
getLimitedValue
(
)
)
;
}
llvm_unreachable
(
"Unable to encode MCOperand!"
)
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> static bool arm_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( GET_MODE_CLASS ( mode ) == MODE_CC ) return ( regno == CC_REGNUM || ( TARGET_VFP_BASE && regno == VFPCC_REGNUM ) ) ; if ( regno == CC_REGNUM && GET_MODE_CLASS ( mode ) != MODE_CC ) return false ; if ( IS_VPR_REGNUM ( regno ) ) return VALID_MVE_PRED_MODE ( mode ) ; if ( TARGET_THUMB1 ) return ( ARM_NUM_REGS ( mode ) < 2 ) || ( regno < LAST_LO_REGNUM ) ; if ( TARGET_VFP_BASE && IS_VFP_REGNUM ( regno ) ) { if ( mode == DFmode || mode == DImode ) return VFP_REGNO_OK_FOR_DOUBLE ( regno ) ; if ( mode == HFmode || mode == BFmode || mode == HImode || mode == SFmode || mode == SImode ) return VFP_REGNO_OK_FOR_SINGLE ( regno ) ; if ( TARGET_NEON ) return ( VALID_NEON_DREG_MODE ( mode ) && VFP_REGNO_OK_FOR_DOUBLE ( regno ) ) || ( VALID_NEON_QREG_MODE ( mode ) && NEON_REGNO_OK_FOR_QUAD ( regno ) ) || ( mode == TImode && NEON_REGNO_OK_FOR_NREGS ( regno , 2 ) ) || ( mode == EImode && NEON_REGNO_OK_FOR_NREGS ( regno , 3 ) ) || ( mode == OImode && NEON_REGNO_OK_FOR_NREGS ( regno , 4 ) ) || ( mode == CImode && NEON_REGNO_OK_FOR_NREGS ( regno , 6 ) ) || ( mode == XImode && NEON_REGNO_OK_FOR_NREGS ( regno , 8 ) ) ; if ( TARGET_HAVE_MVE ) return ( ( VALID_MVE_MODE ( mode ) && NEON_REGNO_OK_FOR_QUAD ( regno ) ) || ( mode == OImode && NEON_REGNO_OK_FOR_NREGS ( regno , 4 ) ) || ( mode == XImode && NEON_REGNO_OK_FOR_NREGS ( regno , 8 ) ) ) ; return false ; } if ( TARGET_REALLY_IWMMXT ) { if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return mode == SImode ; if ( IS_IWMMXT_REGNUM ( regno ) ) return VALID_IWMMXT_REG_MODE ( mode ) ; } if ( regno <= LAST_ARM_REGNUM ) { if ( ARM_NUM_REGS ( mode ) > 4 ) return false ; if ( TARGET_THUMB2 && ! ( TARGET_HAVE_MVE || TARGET_CDE ) ) return true ; return ! ( ( TARGET_LDRD || TARGET_CDE ) && GET_MODE_SIZE ( mode ) > 4 && ( regno & 1 ) != 0 ) ; } if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return GET_MODE_CLASS ( mode ) == MODE_INT ; return false ; } </s>

Returns true if REGNO is a valid register for holding a quantity of type MODE .


<s> const MCPhysReg * MipsRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const MipsSubtarget & Subtarget = MF -> getSubtarget < MipsSubtarget > ( ) ; if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_SaveList ; if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_SaveList ; if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_SaveList ; if ( Subtarget . isFP64bit ( ) ) return CSR_O32_FP64_SaveList ; if ( Subtarget . isFPXX ( ) ) return CSR_O32_FPXX_SaveList ; return CSR_O32_SaveList ; } </s>


<s> int mips_adjust_insn_length ( rtx_insn * insn , int length ) { if ( length == MAX_PIC_BRANCH_LENGTH && JUMP_P ( insn ) && INSN_CODE ( insn ) >= 0 && get_attr_type ( insn ) == TYPE_BRANCH ) { length = simplejump_p ( insn ) ? 0 : 8 ; length += BASE_INSN_LENGTH * mips_load_label_num_insns ( ) ; length += TARGET_COMPRESSION ? 2 : 4 ; } if ( CALL_P ( insn ) || ( TARGET_MIPS16 ? simplejump_p ( insn ) : JUMP_P ( insn ) ) ) length += TARGET_MIPS16 ? 2 : 4 ; if ( ! cfun -> machine -> ignore_hazard_length_p && INSN_P ( insn ) && INSN_CODE ( insn ) >= 0 ) switch ( get_attr_hazard ( insn ) ) { case HAZARD_NONE : break ; case HAZARD_DELAY : length += NOP_INSN_LENGTH ; break ; case HAZARD_HILO : length += NOP_INSN_LENGTH * 2 ; break ; } return length ; } </s>

Return the length of INSN . LENGTH is the initial length computed by attributes in the machine-description file .


<s> bool SystemZInstrInfo :: areMemAccessesTriviallyDisjoint ( const MachineInstr & MIa , const MachineInstr & MIb , AliasAnalysis * AA ) const { if ( ! MIa . hasOneMemOperand ( ) || ! MIb . hasOneMemOperand ( ) ) return false ; MachineMemOperand * MMOa = * MIa . memoperands_begin ( ) ; MachineMemOperand * MMOb = * MIb . memoperands_begin ( ) ; const Value * VALa = MMOa -> getValue ( ) ; const Value * VALb = MMOb -> getValue ( ) ; bool SameVal = ( VALa && VALb && ( VALa == VALb ) ) ; if ( ! SameVal ) { const PseudoSourceValue * PSVa = MMOa -> getPseudoValue ( ) ; const PseudoSourceValue * PSVb = MMOb -> getPseudoValue ( ) ; if ( PSVa && PSVb && ( PSVa == PSVb ) ) SameVal = true ; } if ( SameVal ) { int OffsetA = MMOa -> getOffset ( ) , OffsetB = MMOb -> getOffset ( ) ; int WidthA = MMOa -> getSize ( ) , WidthB = MMOb -> getSize ( ) ; int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB ; int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA ; int LowWidth = ( LowOffset == OffsetA ) ? WidthA : WidthB ; if ( LowOffset + LowWidth <= HighOffset ) return true ; } return false ; } </s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


getTargetNodeName - This method returns the name of a target specific


<s> inline iterator_range < block_iterator > blocks ( ) const { return make_range ( block_begin ( ) , block_end ( ) ) ; } </s>

Returns a range view of the basic blocks in the region .


<s>
SDValue
VETargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
ATOMIC_FENCE
:
return
lowerATOMIC_FENCE
(
Op
,
DAG
)
;
case
ISD
::
ATOMIC_SWAP
:
return
lowerATOMIC_SWAP
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
lowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
lowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
lowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
lowerFRAMEADDR
(
Op
,
DAG
,
*
this
,
Subtarget
)
;
case
ISD
::
GlobalAddress
:
return
lowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
lowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
lowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
LOAD
:
return
lowerLOAD
(
Op
,
DAG
)
;
case
ISD
::
BUILD_VECTOR
:
return
lowerBUILD_VECTOR
(
Op
,
DAG
)
;
case
ISD
::
STORE
:
return
lowerSTORE
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
lowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
VAARG
:
return
lowerVAARG
(
Op
,
DAG
)
;
return
lowerToVVP
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

VE
VE
"Should not custom lower this!"
ISD::ATOMIC_FENCE
ISD::ATOMIC_SWAP
ISD::BlockAddress
ISD::ConstantPool
ISD::DYNAMIC_STACKALLOC
ISD::FRAMEADDR
ISD::GlobalAddress
ISD::GlobalTLSAddress
ISD::JumpTable
ISD::LOAD
ISD::BUILD_VECTOR
VE
ISD::STORE
ISD::VASTART
ISD::VAARG


<s> static unsigned selectBinaryOp ( unsigned GenericOpc , unsigned RegBankID , unsigned OpSize ) { switch ( RegBankID ) { case AArch64 :: GPRRegBankID : switch ( OpSize ) { case 32 : switch ( GenericOpc ) { case TargetOpcode :: G_OR : return AArch64 :: ORRWrr ; case TargetOpcode :: G_XOR : return AArch64 :: EORWrr ; case TargetOpcode :: G_AND : return AArch64 :: ANDWrr ; case TargetOpcode :: G_ADD : return AArch64 :: ADDWrr ; case TargetOpcode :: G_SUB : return AArch64 :: SUBWrr ; case TargetOpcode :: G_SHL : return AArch64 :: LSLVWr ; case TargetOpcode :: G_LSHR : return AArch64 :: LSRVWr ; case TargetOpcode :: G_ASHR : return AArch64 :: ASRVWr ; case TargetOpcode :: G_SDIV : return AArch64 :: SDIVWr ; case TargetOpcode :: G_UDIV : return AArch64 :: UDIVWr ; default : return GenericOpc ; } case 64 : switch ( GenericOpc ) { case TargetOpcode :: G_OR : return AArch64 :: ORRXrr ; case TargetOpcode :: G_XOR : return AArch64 :: EORXrr ; case TargetOpcode :: G_AND : return AArch64 :: ANDXrr ; case TargetOpcode :: G_ADD : return AArch64 :: ADDXrr ; case TargetOpcode :: G_SUB : return AArch64 :: SUBXrr ; case TargetOpcode :: G_SHL : return AArch64 :: LSLVXr ; case TargetOpcode :: G_LSHR : return AArch64 :: LSRVXr ; case TargetOpcode :: G_ASHR : return AArch64 :: ASRVXr ; case TargetOpcode :: G_SDIV : return AArch64 :: SDIVXr ; case TargetOpcode :: G_UDIV : return AArch64 :: UDIVXr ; default : return GenericOpc ; } } case AArch64 :: FPRRegBankID : switch ( OpSize ) { case 32 : switch ( GenericOpc ) { case TargetOpcode :: G_FADD : return AArch64 :: FADDSrr ; case TargetOpcode :: G_FSUB : return AArch64 :: FSUBSrr ; case TargetOpcode :: G_FMUL : return AArch64 :: FMULSrr ; case TargetOpcode :: G_FDIV : return AArch64 :: FDIVSrr ; default : return GenericOpc ; } case 64 : switch ( GenericOpc ) { case TargetOpcode :: G_FADD : return AArch64 :: FADDDrr ; case TargetOpcode :: G_FSUB : return AArch64 :: FSUBDrr ; case TargetOpcode :: G_FMUL : return AArch64 :: FMULDrr ; case TargetOpcode :: G_FDIV : return AArch64 :: FDIVDrr ; default : return GenericOpc ; } } } ; return GenericOpc ; } </s>

Select and emit code for a binary operator instruction , which has an opcode which directly corresponds to the given ISD opcode .


<s> unsigned LanaiInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == Lanai :: LDW_RI ) if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> int xtensa_expand_block_move ( rtx * operands ) { static const enum machine_mode mode_from_align [ ] = { VOIDmode , QImode , HImode , VOIDmode , SImode , } ; rtx dst_mem = operands [ 0 ] ; rtx src_mem = operands [ 1 ] ; HOST_WIDE_INT bytes , align ; int num_pieces , move_ratio ; rtx temp [ 2 ] ; enum machine_mode mode [ 2 ] ; int amount [ 2 ] ; bool active [ 2 ] ; int phase = 0 ; int next ; int offset_ld = 0 ; int offset_st = 0 ; rtx x ; if ( ! optimize || ( GET_CODE ( operands [ 2 ] ) != CONST_INT ) ) return 0 ; bytes = INTVAL ( operands [ 2 ] ) ; align = INTVAL ( operands [ 3 ] ) ; if ( bytes <= 0 ) return 0 ; if ( align > MOVE_MAX ) align = MOVE_MAX ; move_ratio = 4 ; if ( optimize > 2 ) move_ratio = LARGEST_MOVE_RATIO ; num_pieces = ( bytes / align ) + ( bytes % align ) ; if ( num_pieces > move_ratio ) return 0 ; x = XEXP ( dst_mem , 0 ) ; if ( ! REG_P ( x ) ) { x = force_reg ( Pmode , x ) ; dst_mem = replace_equiv_address ( dst_mem , x ) ; } x = XEXP ( src_mem , 0 ) ; if ( ! REG_P ( x ) ) { x = force_reg ( Pmode , x ) ; src_mem = replace_equiv_address ( src_mem , x ) ; } active [ 0 ] = active [ 1 ] = false ; do { next = phase ; phase ^= 1 ; if ( bytes > 0 ) { int next_amount ; next_amount = ( bytes >= 4 ? 4 : ( bytes >= 2 ? 2 : 1 ) ) ; next_amount = MIN ( next_amount , align ) ; amount [ next ] = next_amount ; mode [ next ] = mode_from_align [ next_amount ] ; temp [ next ] = gen_reg_rtx ( mode [ next ] ) ; x = adjust_address ( src_mem , mode [ next ] , offset_ld ) ; emit_insn ( gen_rtx_SET ( VOIDmode , temp [ next ] , x ) ) ; offset_ld += next_amount ; bytes -= next_amount ; active [ next ] = true ; } if ( active [ phase ] ) { active [ phase ] = false ; x = adjust_address ( dst_mem , mode [ phase ] , offset_st ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x , temp [ phase ] ) ) ; offset_st += amount [ phase ] ; } } while ( active [ next ] ) ; return 1 ; } </s>

Try to expand a block move operation to an RTL block move instruction . If not optimizing or if the block size is not a constant or if the block is small , the expansion fails and GCC falls back to calling memcpy ( ) . operands [ 0 ] is the destination operands [ 1 ] is the source operands [ 2 ] is the length operands [ 3 ] is the alignment


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < DivergenceAnalysis > ( ) ; AU . addRequired < MemoryDependenceWrapperPass > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . setPreservesAll ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void mips_expand_before_return ( void ) { if ( TARGET_CALL_CLOBBERED_GP ) emit_clobber ( pic_offset_table_rtx ) ; } </s>

Emit any instructions needed before a return .


<s> void RISCVPassConfig :: addPreRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createRISCVMergeBaseOffsetOptPass ( ) ) ; addPass ( createRISCVInsertVSETVLIPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> void ARMELFStreamer :: finishImpl ( ) { MCTargetStreamer & TS = * getTargetStreamer ( ) ; ARMTargetStreamer & ATS = static_cast < ARMTargetStreamer & > ( TS ) ; ATS . finishAttributeSection ( ) ; MCELFStreamer :: finishImpl ( ) ; } </s>


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Thumb IT blocks insertion pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const override { ScheduleDAGMILive * DAG = createGenericSchedLive ( C ) ; DAG -> addMutation ( createX86MacroFusionDAGMutation ( ) ) ; return DAG ; } </s>

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level .


<s> static bool s390_call_saved_register_used ( tree call_expr ) { CUMULATIVE_ARGS cum_v ; cumulative_args_t cum ; tree parameter ; rtx parm_rtx ; int reg , i ; INIT_CUMULATIVE_ARGS ( cum_v , NULL , NULL , 0 , 0 ) ; cum = pack_cumulative_args ( & cum_v ) ; for ( i = 0 ; i < call_expr_nargs ( call_expr ) ; i ++ ) { parameter = CALL_EXPR_ARG ( call_expr , i ) ; gcc_assert ( parameter ) ; if ( TREE_CODE ( parameter ) == ERROR_MARK ) return true ; function_arg_info arg ( TREE_TYPE ( parameter ) , true ) ; apply_pass_by_reference_rules ( & cum_v , arg ) ; parm_rtx = s390_function_arg ( cum , arg ) ; s390_function_arg_advance ( cum , arg ) ; if ( ! parm_rtx ) continue ; if ( REG_P ( parm_rtx ) ) { for ( reg = 0 ; reg < REG_NREGS ( parm_rtx ) ; reg ++ ) if ( ! call_used_or_fixed_reg_p ( reg + REGNO ( parm_rtx ) ) ) return true ; } if ( GET_CODE ( parm_rtx ) == PARALLEL ) { int i ; for ( i = 0 ; i < XVECLEN ( parm_rtx , 0 ) ; i ++ ) { rtx r = XEXP ( XVECEXP ( parm_rtx , 0 , i ) , 0 ) ; gcc_assert ( REG_P ( r ) ) ; for ( reg = 0 ; reg < REG_NREGS ( r ) ; reg ++ ) if ( ! call_used_or_fixed_reg_p ( reg + REGNO ( r ) ) ) return true ; } } } return false ; } </s>

Checks whether the given ARGUMENT_LIST would use a caller saved register . This is used to decide whether sibling call optimization could be performed on the respective function call .


"LOAD_STACK_GUARD currently supported only for MachO."

This function is called for all pseudo instructions that remain after register allocation .


<s> static void nvptx_end_call_args ( void ) { cfun -> machine -> start_call = NULL_RTX ; free_EXPR_LIST_list ( & cfun -> machine -> call_args ) ; } </s>

Implement the corresponding END_CALL_ARGS hook . Clear and free the information we recorded .


<s> bool X86PassConfig :: addPreEmitPass ( ) { bool ShouldPrint = false ; if ( getOptLevel ( ) != CodeGenOpt :: None && getX86Subtarget ( ) . hasSSE2 ( ) ) { addPass ( createExecutionDependencyFixPass ( & X86 :: VR128RegClass ) ) ; ShouldPrint = true ; } if ( UseVZeroUpper ) { addPass ( createX86IssueVZeroUpperPass ( ) ) ; ShouldPrint = true ; } if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86PadShortFunctions ( ) ) ; addPass ( createX86FixupLEAs ( ) ) ; ShouldPrint = true ; } addPass ( createX86ProtectReturnSupport ( ) ) ; addPass ( createX86ProtectSpillSupport ( ) ) ; addPass ( createX86EnqueueExits ( ) ) ; return ShouldPrint ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


"********** Replace Physical Registers **********\n"

"LiveIntervals shouldn't be active yet!"

runOnMachineFunction - Emit the function body .


<s> virtual const HexagonSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static bool isReassociationCandidate ( const MachineInstr & Inst , bool & Commuted ) { if ( isAssociativeAndCommutative ( Inst ) && hasReassociableOperands ( Inst , Inst . getParent ( ) ) && hasReassociableSibling ( Inst , Commuted ) ) return true ; return false ; } </s>

Return true if the input \P Inst is part of a chain of dependent ops that are suitable for reassociation , otherwise return false .


<s> static unsigned long thumb_compute_save_reg_mask ( void ) { unsigned long mask ; unsigned reg ; mask = 0 ; for ( reg = 0 ; reg < 12 ; reg ++ ) if ( regs_ever_live [ reg ] && ! call_used_regs [ reg ] ) mask |= 1 << reg ; if ( flag_pic && ! TARGET_SINGLE_PIC_BASE && current_function_uses_pic_offset_table ) mask |= 1 << PIC_OFFSET_TABLE_REGNUM ; if ( ! frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0 ) mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM ; if ( mask & 0xff || thumb_force_lr_save ( ) ) mask |= ( 1 << LR_REGNUM ) ; if ( ( mask & 0xff ) == 0 && ( ( mask & 0x0f00 ) || TARGET_BACKTRACE ) ) { reg = thumb_find_work_register ( 1 << LAST_LO_REGNUM ) ; if ( ! call_used_regs [ reg ] ) mask |= 1 << reg ; } return mask ; } </s>

Compute a bit mask of which registers need to be saved on the stack for the current function .


"dynamic alloca in the static alloca map?"

Emit an alloca address in a register using target-specific logic .


<s> bool BTFDebug :: InstLower ( const MachineInstr * MI , MCInst & OutMI ) { if ( MI -> getOpcode ( ) == BPF :: LD_imm64 ) { const MachineOperand & MO = MI -> getOperand ( 1 ) ; if ( MO . isGlobal ( ) ) { const GlobalValue * GVal = MO . getGlobal ( ) ; auto * GVar = dyn_cast < GlobalVariable > ( GVal ) ; if ( GVar && GVar -> hasAttribute ( BPFCoreSharedInfo :: AmaAttr ) ) { uint32_t Imm = PatchImms [ GVar -> getName ( ) . str ( ) ] ; OutMI . setOpcode ( BPF :: MOV_ri ) ; OutMI . addOperand ( MCOperand :: createReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ) ; OutMI . addOperand ( MCOperand :: createImm ( Imm ) ) ; return true ; } } } else if ( MI -> getOpcode ( ) == BPF :: CORE_MEM || MI -> getOpcode ( ) == BPF :: CORE_ALU32_MEM || MI -> getOpcode ( ) == BPF :: CORE_SHIFT ) { const MachineOperand & MO = MI -> getOperand ( 3 ) ; if ( MO . isGlobal ( ) ) { const GlobalValue * GVal = MO . getGlobal ( ) ; auto * GVar = dyn_cast < GlobalVariable > ( GVal ) ; if ( GVar && GVar -> hasAttribute ( BPFCoreSharedInfo :: AmaAttr ) ) { uint32_t Imm = PatchImms [ GVar -> getName ( ) . str ( ) ] ; OutMI . setOpcode ( MI -> getOperand ( 1 ) . getImm ( ) ) ; if ( MI -> getOperand ( 0 ) . isImm ( ) ) OutMI . addOperand ( MCOperand :: createImm ( MI -> getOperand ( 0 ) . getImm ( ) ) ) ; else OutMI . addOperand ( MCOperand :: createReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ) ; OutMI . addOperand ( MCOperand :: createReg ( MI -> getOperand ( 2 ) . getReg ( ) ) ) ; OutMI . addOperand ( MCOperand :: createImm ( Imm ) ) ; return true ; } } } return false ; } </s>


<s> unsigned VEAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & GOp , unsigned Kind ) { VEOperand & Op = ( VEOperand & ) GOp ; switch ( Kind ) { default : break ; case MCK_F32 : if ( Op . isReg ( ) && VEOperand :: MorphToF32Reg ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; case MCK_I32 : if ( Op . isReg ( ) && VEOperand :: MorphToI32Reg ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; case MCK_F128 : if ( Op . isReg ( ) && VEOperand :: MorphToF128Reg ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; case MCK_VM512 : if ( Op . isReg ( ) && VEOperand :: MorphToVM512Reg ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; case MCK_MISC : if ( Op . isImm ( ) && VEOperand :: MorphToMISCReg ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; } return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s>
SDValue
PPCTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_PPC
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
PPCISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
else
return
DAG
.
getNode
(
PPCISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void function_builder :: add_unique_function ( const function_instance & instance , const function_shape * shape , tree return_type , vec < tree > & argument_types ) { if ( ! check_required_extensions ( instance ) ) return ; char * name = shape -> get_name ( * this , instance , false ) ; tree fntype = build_function_type_array ( return_type , argument_types . length ( ) , argument_types . address ( ) ) ; tree attrs = get_attributes ( instance ) ; registered_function & rfn = add_function ( instance , name , fntype , attrs , false ) ; hashval_t hash = instance . hash ( ) ; registered_function * * rfn_slot = function_table -> find_slot_with_hash ( instance , hash , INSERT ) ; gcc_assert ( ! * rfn_slot ) ; * rfn_slot = & rfn ; char * overload_name = shape -> get_name ( * this , instance , true ) ; if ( overload_name ) { tree attrs = get_attributes ( instance ) ; bool placeholder_p = ! m_direct_overloads ; add_function ( instance , overload_name , fntype , attrs , placeholder_p ) ; } obstack_free ( & m_string_obstack , name ) ; } </s>

Add a built-in function for INSTANCE , with the argument types given by ARGUMENT_TYPES and the return type given by RETURN_TYPE . NAME is the `` full '' name for C function . OVERLOAD_NAME is the `` short '' name for C++ overloaded function . OVERLOAD_NAME can be nullptr because some instance does n't have C++ overloaded function .


<s> void ARMElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { const ARMBaseTargetMachine & ARM_TM = static_cast < const ARMBaseTargetMachine & > ( TM ) ; bool isAAPCS_ABI = ARM_TM . TargetABI == ARMBaseTargetMachine :: ARMABI :: ARM_ABI_AAPCS ; genExecuteOnly = ARM_TM . getSubtargetImpl ( ) -> genExecuteOnly ( ) ; TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( isAAPCS_ABI ) ; if ( isAAPCS_ABI ) { LSDASection = nullptr ; } AttributesSection = getContext ( ) . getELFSection ( ".ARM.attributes" , ELF :: SHT_ARM_ATTRIBUTES , 0 ) ; if ( genExecuteOnly ) { unsigned Type = ELF :: SHT_PROGBITS ; unsigned Flags = ELF :: SHF_EXECINSTR | ELF :: SHF_ALLOC | ELF :: SHF_ARM_PURECODE ; TextSection = Ctx . getELFSection ( ".text" , Type , Flags , 0 , "" , 0U ) ; } } </s>

This method must be called before any actual lowering is done .


<s> static bool decl_has_samegp ( const_tree decl ) { if ( ! ( * targetm . binds_local_p ) ( decl ) ) return false ; if ( TARGET_EXPLICIT_RELOCS && TARGET_SMALL_DATA ) return true ; return ! TREE_PUBLIC ( decl ) || ! DECL_EXTERNAL ( decl ) ; } </s>

Return true if the function DECL will share the same GP as any function in the current unit of translation .


<s>
StringRef
getPassName
(
)
const
override
{
return
"RISCV gather/scatter lowering"
;
}
</s>


"unknown parameter to option %<-mtune-ctrl%>: %s"

parse -mtune-ctrl= option . When DUMP is true , print the features that are explicitly set .


<s> void ARMBaseRegisterInfo :: getRegAllocationHints ( unsigned VirtReg , ArrayRef < MCPhysReg > Order , SmallVectorImpl < MCPhysReg > & Hints , const MachineFunction & MF , const VirtRegMap * VRM , const LiveRegMatrix * Matrix ) const { const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; std :: pair < unsigned , unsigned > Hint = MRI . getRegAllocationHint ( VirtReg ) ; unsigned Odd ; switch ( Hint . first ) { case ARMRI :: RegPairEven : Odd = 0 ; break ; case ARMRI :: RegPairOdd : Odd = 1 ; break ; default : TargetRegisterInfo :: getRegAllocationHints ( VirtReg , Order , Hints , MF , VRM ) ; return ; } unsigned Paired = Hint . second ; if ( Paired == 0 ) return ; unsigned PairedPhys = 0 ; if ( TargetRegisterInfo :: isPhysicalRegister ( Paired ) ) { PairedPhys = Paired ; } else if ( VRM && VRM -> hasPhys ( Paired ) ) { PairedPhys = getPairedGPR ( VRM -> getPhys ( Paired ) , Odd , this ) ; } if ( PairedPhys && is_contained ( Order , PairedPhys ) ) Hints . push_back ( PairedPhys ) ; for ( unsigned Reg : Order ) { if ( Reg == PairedPhys || ( getEncodingValue ( Reg ) & 1 ) != Odd ) continue ; unsigned Paired = getPairedGPR ( Reg , ! Odd , this ) ; if ( ! Paired || MRI . isReserved ( Paired ) ) continue ; Hints . push_back ( Reg ) ; } } </s>

Get a list of 'hint ' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg .


<s> static void sh_file_start ( void ) { default_file_start ( ) ; if ( TARGET_ELF ) fprintf ( asm_out_file , "%s\n" , TEXT_SECTION_ASM_OP ) ; else switch_to_section ( data_section ) ; if ( TARGET_LITTLE_ENDIAN ) fputs ( "\t.little\n" , asm_out_file ) ; } </s>

Output the start of the assembler file .


<s> void TVMInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { switch ( MI -> getOpcode ( ) ) { case TVM :: TO_TUPLE_COPY_S : case TVM :: TO_SLICE_COPY_S : case TVM :: TO_BUILDER_COPY_S : case TVM :: TO_CELL_COPY_S : case TVM :: FROM_TUPLE_COPY_S : case TVM :: FROM_SLICE_COPY_S : case TVM :: FROM_BUILDER_COPY_S : case TVM :: FROM_CELL_COPY_S : case TVM :: REG_TO_REG_COPY_S : case TVM :: PUSH_GLOBAL_ADDRESS_S : case TVM :: FALLTHROUGH_RETURN : return ; default : break ; } { std :: string Str ; raw_string_ostream OStr ( Str ) ; if ( ! printAliasInstr ( MI , OStr ) ) printInstruction ( MI , OStr ) ; OStr . flush ( ) ; assert ( Str . front ( ) == '\t' ) ; Str . erase ( 0 , 1 ) ; O << Str ; } printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> int mips_idiv_insns ( void ) { int count ; count = 1 ; if ( TARGET_CHECK_ZERO_DIV ) { if ( GENERATE_DIVIDE_TRAPS ) count ++ ; else count += 2 ; } if ( TARGET_FIX_R4000 || TARGET_FIX_R4400 ) count ++ ; return count ; } </s>

Return the number of instructions needed for an integer division .


<s> static bool frv_for_each_packet ( void ( * handle_packet ) ( void ) ) { rtx_insn * insn , * next_insn ; frv_packet . issue_rate = frv_issue_rate ( ) ; if ( ! optimize || ! flag_schedule_insns_after_reload || ! TARGET_VLIW_BRANCH || frv_packet . issue_rate == 1 ) return false ; dfa_start ( ) ; frv_packet . dfa_state = alloca ( state_size ( ) ) ; frv_start_packet_block ( ) ; for ( insn = get_insns ( ) ; insn != 0 ; insn = next_insn ) { enum rtx_code code ; bool eh_insn_p ; code = GET_CODE ( insn ) ; next_insn = NEXT_INSN ( insn ) ; if ( code == CODE_LABEL ) { frv_finish_packet ( handle_packet ) ; frv_start_packet_block ( ) ; } if ( INSN_P ( insn ) ) switch ( GET_CODE ( PATTERN ( insn ) ) ) { case USE : case CLOBBER : break ; default : if ( CALL_P ( insn ) && frv_cpu_type == FRV_CPU_TOMCAT ) frv_finish_packet ( handle_packet ) ; eh_insn_p = ( find_reg_note ( insn , REG_EH_REGION , NULL ) != NULL ) ; if ( eh_insn_p && ! frv_issues_to_branch_unit_p ( insn ) ) frv_finish_packet ( handle_packet ) ; if ( ! frv_pack_insn_p ( insn ) ) { frv_finish_packet ( handle_packet ) ; while ( ! frv_pack_insn_p ( insn ) ) state_transition ( frv_packet . dfa_state , 0 ) ; } frv_add_insn_to_packet ( insn ) ; if ( code == CALL_INSN || code == JUMP_INSN || eh_insn_p ) frv_finish_packet ( handle_packet ) ; break ; } } frv_finish_packet ( handle_packet ) ; dfa_finish ( ) ; return true ; } </s>

If packing is enabled , divide the instructions into packets and return true . Call HANDLE_PACKET for each complete packet .


<s> SDValue AArch64TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: AND : return PerformANDCombine ( N , DCI ) ; case ISD :: OR : return PerformORCombine ( N , DCI , Subtarget ) ; case ISD :: SRA : return PerformSRACombine ( N , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> bool AArch64SIMDInstrOpt :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; const TargetSubtargetInfo & ST = MF . getSubtarget ( ) ; const AArch64InstrInfo * AAII = static_cast < const AArch64InstrInfo * > ( ST . getInstrInfo ( ) ) ; if ( ! AAII ) return false ; SchedModel . init ( ST . getSchedModel ( ) , & ST , AAII ) ; if ( ! SchedModel . hasInstrSchedModel ( ) ) return false ; bool Changed = false ; for ( auto OptimizationKind : { VectorElem , Interleave } ) { if ( ! shouldExitEarly ( & MF , OptimizationKind ) ) { SmallVector < MachineInstr * , 8 > RemoveMIs ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineBasicBlock :: iterator MII = MBB . begin ( ) , MIE = MBB . end ( ) ; MII != MIE ; ) { MachineInstr & MI = * MII ; bool InstRewrite ; if ( OptimizationKind == VectorElem ) InstRewrite = optimizeVectElement ( MI ) ; else InstRewrite = optimizeLdStInterleave ( MI ) ; if ( InstRewrite ) { RemoveMIs . push_back ( & MI ) ; Changed = true ; } ++ MII ; } } for ( MachineInstr * MI : RemoveMIs ) MI -> eraseFromParent ( ) ; } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool BTFDebug :: InstLower ( const MachineInstr * MI , MCInst & OutMI ) { if ( MI -> getOpcode ( ) == BPF :: LD_imm64 ) { const MachineOperand & MO = MI -> getOperand ( 1 ) ; if ( MO . isGlobal ( ) ) { const GlobalValue * GVal = MO . getGlobal ( ) ; auto * GVar = dyn_cast < GlobalVariable > ( GVal ) ; if ( GVar && GVar -> hasAttribute ( BPFCoreSharedInfo :: AmaAttr ) ) { MDNode * MDN = GVar -> getMetadata ( LLVMContext :: MD_preserve_access_index ) ; DIType * Ty = dyn_cast < DIType > ( MDN ) ; std :: string TypeName = Ty -> getName ( ) ; int64_t Imm = AccessOffsets [ GVar -> getName ( ) . str ( ) ] ; OutMI . setOpcode ( BPF :: MOV_ri ) ; OutMI . addOperand ( MCOperand :: createReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ) ; OutMI . addOperand ( MCOperand :: createImm ( Imm ) ) ; return true ; } else if ( GVar && ! GVar -> hasInitializer ( ) && GVar -> hasExternalLinkage ( ) && GVar -> getSection ( ) == BPFCoreSharedInfo :: PatchableExtSecName ) { const IntegerType * IntTy = dyn_cast < IntegerType > ( GVar -> getValueType ( ) ) ; assert ( IntTy ) ; if ( IntTy -> getBitWidth ( ) == 64 ) OutMI . setOpcode ( BPF :: LD_imm64 ) ; else OutMI . setOpcode ( BPF :: MOV_ri ) ; OutMI . addOperand ( MCOperand :: createReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ) ; OutMI . addOperand ( MCOperand :: createImm ( 0 ) ) ; return true ; } } } return false ; } </s>


<s> static void c6x_clear_sched_context ( void * _sc ) { c6x_sched_context_t sc = ( c6x_sched_context_t ) _sc ; gcc_assert ( _sc != NULL ) ; free ( sc -> prev_cycle_state_ctx ) ; } </s>


<s> Relocator :: Result unsupported ( Relocation & pReloc , AArch64Relocator & pParent ) { return Relocator :: Unsupported ; } </s>


<s> Sched :: Preference ARMTargetLowering :: getSchedulingPreference ( SDNode * N ) const { unsigned NumVals = N -> getNumValues ( ) ; if ( ! NumVals ) return Sched :: RegPressure ; for ( unsigned i = 0 ; i != NumVals ; ++ i ) { EVT VT = N -> getValueType ( i ) ; if ( VT == MVT :: Glue || VT == MVT :: Other ) continue ; if ( VT . isFloatingPoint ( ) || VT . isVector ( ) ) return Sched :: Latency ; } if ( ! N -> isMachineOpcode ( ) ) return Sched :: RegPressure ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII -> get ( N -> getMachineOpcode ( ) ) ; if ( MCID . getNumDefs ( ) == 0 ) return Sched :: RegPressure ; if ( ! Itins -> isEmpty ( ) && Itins -> getOperandCycle ( MCID . getSchedClass ( ) , 0 ) > 2 ) return Sched :: Latency ; return Sched :: RegPressure ; } </s>


<s> bool PPCPassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( ) ) ; return false ; } </s>

This method should install a ( global ) instruction selector pass , which converts possibly generic instructions to fully target-specific instructions , thereby constraining all generic virtual registers to register classes .


<s> bool AArch64PassConfig :: addILPOpts ( ) { if ( EnableCCMP ) addPass ( createAArch64ConditionalCompares ( ) ) ; addPass ( & EarlyIfConverterID ) ; if ( EnableStPairSuppress ) addPass ( createAArch64StorePairSuppressPass ( ) ) ; return true ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .


<s> bool R600InstrInfo :: isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCyles , const BranchProbability & Probability ) const { return true ; } </s>

Return true if it 's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion .


<s> void dimode_scalar_chain :: replace_with_subreg_in_insn ( rtx_insn * insn , rtx reg , rtx new_reg ) { replace_with_subreg ( single_set ( insn ) , reg , new_reg ) ; } </s>

Replace REG in INSN with a V2DI subreg of NEW_REG .


<s> bool PPCFrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return true ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! EnablePEVectorSpills || MFI . hasCalls ( ) || ! Subtarget . hasP9Vector ( ) ) return false ; BitVector BVAllocatable = TRI -> getAllocatableSet ( MF ) ; BitVector BVCalleeSaved ( TRI -> getNumRegs ( ) ) ; const PPCRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( & MF ) ; for ( unsigned i = 0 ; CSRegs [ i ] ; ++ i ) BVCalleeSaved . set ( CSRegs [ i ] ) ; for ( unsigned Reg : BVAllocatable . set_bits ( ) ) { if ( BVCalleeSaved [ Reg ] || ( ! PPC :: F8RCRegClass . contains ( Reg ) && ! PPC :: VFRCRegClass . contains ( Reg ) ) || ( MF . getRegInfo ( ) . isPhysRegUsed ( Reg ) ) ) BVAllocatable . reset ( Reg ) ; } bool AllSpilledToReg = true ; for ( auto & CS : CSI ) { if ( BVAllocatable . none ( ) ) return false ; unsigned Reg = CS . getReg ( ) ; if ( ! PPC :: G8RCRegClass . contains ( Reg ) && ! PPC :: GPRCRegClass . contains ( Reg ) ) { AllSpilledToReg = false ; continue ; } unsigned VolatileVFReg = BVAllocatable . find_first ( ) ; if ( VolatileVFReg < BVAllocatable . size ( ) ) { CS . setDstReg ( VolatileVFReg ) ; BVAllocatable . reset ( VolatileVFReg ) ; } else { AllSpilledToReg = false ; } } return AllSpilledToReg ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s>
void
i386_pe_assemble_visibility
(
tree
decl
,
int
)
{
if
(
!
decl
||
!
lookup_attribute
(
"visibility"
,
DECL_ATTRIBUTES
(
decl
)
)
)
return
;
if
(
!
DECL_ARTIFICIAL
(
decl
)
)
warning
(
OPT_Wattributes
,
"visibility attribute not supported "
"in this configuration; ignored"
)
;
}
</s>

Emit an assembler directive to set symbol for DECL visibility to the visibility type VIS , which must not be VISIBILITY_DEFAULT . As for PE there is no hidden support in gas , we just warn for user-specified visibility attributes .

i386
"visibility"
"visibility attribute not supported "
"in this configuration; ignored"


<s> static void union_uses ( swap_web_entry * insn_entry , rtx insn , df_ref def ) { struct df_link * link = DF_REF_CHAIN ( def ) ; if ( ! link ) insn_entry [ INSN_UID ( insn ) ] . is_live_out = 1 ; while ( link ) { if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) insn_entry [ INSN_UID ( insn ) ] . is_live_out = 1 ; if ( DF_REF_INSN_INFO ( link -> ref ) ) { rtx use_insn = DF_REF_INSN ( link -> ref ) ; ( void ) unionfind_union ( insn_entry + INSN_UID ( insn ) , insn_entry + INSN_UID ( use_insn ) ) ; } link = link -> next ; } } </s>

Union INSN with all insns containing uses reached from DEF . Detect whether DEF is live-out from the current function .


<s> int mips_const_insns ( rtx x ) { struct mips_integer_op codes [ MIPS_MAX_INTEGER_OPS ] ; enum mips_symbol_type symbol_type ; rtx offset ; switch ( GET_CODE ( x ) ) { case HIGH : if ( ! mips_symbolic_constant_p ( XEXP ( x , 0 ) , SYMBOL_CONTEXT_LEA , & symbol_type ) || ! mips_split_p [ symbol_type ] ) return 0 ; return TARGET_MIPS16 ? 4 : 1 ; case CONST_INT : if ( TARGET_MIPS16 ) return ( IN_RANGE ( INTVAL ( x ) , 0 , 255 ) ? 1 : SMALL_OPERAND_UNSIGNED ( INTVAL ( x ) ) ? 2 : IN_RANGE ( - INTVAL ( x ) , 0 , 255 ) ? 2 : SMALL_OPERAND_UNSIGNED ( - INTVAL ( x ) ) ? 3 : 0 ) ; return mips_build_integer ( codes , INTVAL ( x ) ) ; case CONST_DOUBLE : case CONST_VECTOR : return ! TARGET_MIPS16 && x == CONST0_RTX ( GET_MODE ( x ) ) ? 1 : 0 ; case CONST : if ( CONST_GP_P ( x ) ) return 1 ; if ( mips_symbolic_constant_p ( x , SYMBOL_CONTEXT_LEA , & symbol_type ) ) return mips_symbol_insns ( symbol_type , MAX_MACHINE_MODE ) ; split_const ( x , & x , & offset ) ; if ( offset != 0 ) { int n = mips_const_insns ( x ) ; if ( n != 0 ) { if ( SMALL_INT ( offset ) ) return n + 1 ; else if ( ! targetm . cannot_force_const_mem ( GET_MODE ( x ) , x ) ) return n + 1 + mips_build_integer ( codes , INTVAL ( offset ) ) ; } } return 0 ; case SYMBOL_REF : case LABEL_REF : return mips_symbol_insns ( mips_classify_symbol ( x , SYMBOL_CONTEXT_LEA ) , MAX_MACHINE_MODE ) ; default : return 0 ; } } </s>


<s> bool MipsCallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , unsigned VReg ) const { MachineInstrBuilder Ret = MIRBuilder . buildInstrNoInsert ( Mips :: RetRA ) ; if ( Val != nullptr ) { return false ; } MIRBuilder . insertInstr ( Ret ) ; return true ; } </s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s>
void
SNESInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
O
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
)
{
unsigned
Opcode
=
MI
->
getOpcode
(
)
;
switch
(
Opcode
)
{
case
SNES
::
LDRdPtr
:
case
SNES
::
LDRdPtrPi
:
case
SNES
::
LDRdPtrPd
:
O
<<
"\tld\t"
;
printOperand
(
MI
,
0
,
O
)
;
O
<<
", "
;
if
(
Opcode
==
SNES
::
LDRdPtrPd
)
O
<<
'-'
;
printOperand
(
MI
,
1
,
O
)
;
if
(
Opcode
==
SNES
::
LDRdPtrPi
)
O
<<
'+'
;
break
;
case
SNES
::
STPtrRr
:
O
<<
"\tst\t"
;
printOperand
(
MI
,
0
,
O
)
;
O
<<
", "
;
printOperand
(
MI
,
1
,
O
)
;
break
;
case
SNES
::
STPtrPiRr
:
case
SNES
::
STPtrPdRr
:
O
<<
"\tst\t"
;
if
(
Opcode
==
SNES
::
STPtrPdRr
)
O
<<
'-'
;
printOperand
(
MI
,
1
,
O
)
;
if
(
Opcode
==
SNES
::
STPtrPiRr
)
O
<<
'+'
;
O
<<
", "
;
printOperand
(
MI
,
2
,
O
)
;
break
;
default
:
if
(
!
printAliasInstr
(
MI
,
O
)
)
printInstruction
(
MI
,
O
)
;
printAnnotation
(
O
,
Annot
)
;
break
;
}
}
</s>

SNES
SNES
SNES::LDRdPtr
SNES::LDRdPtrPi
SNES::LDRdPtrPd
"\tld\t"
0
", "
SNES::LDRdPtrPd
1
SNES::LDRdPtrPi
SNES::STPtrRr
"\tst\t"
0
", "
1
SNES::STPtrPiRr
SNES::STPtrPdRr
"\tst\t"
SNES::STPtrPdRr
1
SNES::STPtrPiRr
", "
2


<s>
void
Mips16InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineMemOperand
*
MMO
=
GetMemOperand
(
MBB
,
FI
,
MachineMemOperand
::
MOStore
)
;
unsigned
Opc
=
0
;
if
(
Mips
::
CPU16RegsRegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
Mips
::
SwRxSpImmX16
;
assert
(
Opc
&&
"Register class not handled!"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> static void pdp11_option_override ( void ) { if ( TARGET_DEC_ASM ) { targetm . asm_out . open_paren = "<" ; targetm . asm_out . close_paren = ">" ; } } </s>

This overrides some target hooks that are initializer elements so they ca n't be variables in the # define .


<s>
SDValue
RISCVTargetLowering
::
getAddr
(
NodeTy
*
N
,
SelectionDAG
&
DAG
,
bool
IsLocal
)
const
{
SDLoc
DL
(
N
)
;
EVT
Ty
=
getPointerTy
(
DAG
.
getDataLayout
(
)
)
;
if
(
isPositionIndependent
(
)
)
{
SDValue
Addr
=
getTargetNode
(
N
,
DL
,
Ty
,
DAG
,
0
)
;
if
(
IsLocal
)
return
SDValue
(
DAG
.
getMachineNode
(
RISCV
::
PseudoLLA
,
DL
,
Ty
,
Addr
)
,
0
)
;
return
SDValue
(
DAG
.
getMachineNode
(
RISCV
::
PseudoLA
,
DL
,
Ty
,
Addr
)
,
0
)
;
}
switch
(
getTargetMachine
(
)
.
getCodeModel
(
)
)
{
default
:
report_fatal_error
(
"Unsupported code model for lowering"
)
;
case
CodeModel
::
Small
:
{
SDValue
AddrHi
=
getTargetNode
(
N
,
DL
,
Ty
,
DAG
,
RISCVII
::
MO_HI
)
;
SDValue
AddrLo
=
getTargetNode
(
N
,
DL
,
Ty
,
DAG
,
RISCVII
::
MO_LO
)
;
SDValue
MNHi
=
SDValue
(
DAG
.
getMachineNode
(
RISCV
::
LUI
,
DL
,
Ty
,
AddrHi
)
,
0
)
;
return
SDValue
(
DAG
.
getMachineNode
(
RISCV
::
ADDI
,
DL
,
Ty
,
MNHi
,
AddrLo
)
,
0
)
;
}
case
CodeModel
::
Medium
:
{
SDValue
Addr
=
getTargetNode
(
N
,
DL
,
Ty
,
DAG
,
0
)
;
return
SDValue
(
DAG
.
getMachineNode
(
RISCV
::
PseudoLLA
,
DL
,
Ty
,
Addr
)
,
0
)
;
}
}
}
</s>

Return the address accessed by this recipe .


<s> const MCPhysReg * MSP430RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const MSP430FrameLowering * TFI = getFrameLowering ( * MF ) ; const Function * F = MF -> getFunction ( ) ; static const MCPhysReg CalleeSavedRegs [ ] = { MSP430 :: FP , MSP430 :: R5 , MSP430 :: R6 , MSP430 :: R7 , MSP430 :: R8 , MSP430 :: R9 , MSP430 :: R10 , 0 } ; static const MCPhysReg CalleeSavedRegsFP [ ] = { MSP430 :: R5 , MSP430 :: R6 , MSP430 :: R7 , MSP430 :: R8 , MSP430 :: R9 , MSP430 :: R10 , 0 } ; static const MCPhysReg CalleeSavedRegsIntr [ ] = { MSP430 :: FP , MSP430 :: R5 , MSP430 :: R6 , MSP430 :: R7 , MSP430 :: R8 , MSP430 :: R9 , MSP430 :: R10 , MSP430 :: R11 , MSP430 :: R12 , MSP430 :: R13 , MSP430 :: R14 , MSP430 :: R15 , 0 } ; static const MCPhysReg CalleeSavedRegsIntrFP [ ] = { MSP430 :: R5 , MSP430 :: R6 , MSP430 :: R7 , MSP430 :: R8 , MSP430 :: R9 , MSP430 :: R10 , MSP430 :: R11 , MSP430 :: R12 , MSP430 :: R13 , MSP430 :: R14 , MSP430 :: R15 , 0 } ; if ( TFI -> hasFP ( * MF ) ) return ( F -> getCallingConv ( ) == CallingConv :: MSP430_INTR ? CalleeSavedRegsIntrFP : CalleeSavedRegsFP ) ; else return ( F -> getCallingConv ( ) == CallingConv :: MSP430_INTR ? CalleeSavedRegsIntr : CalleeSavedRegs ) ; } </s>


"Tile64 DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


"haven't found the end of the statement\n"

ParseInstruction - Parse one assembly instruction .


"Should only have an r11 thunk on 64-bit targets"


<s> bool constant_address_p ( rtx x ) { return CONSTANT_P ( x ) && ix86_legitimate_address_p ( Pmode , x , 1 ) ; } </s>

Determine if a given RTX is a valid constant address .


"Pseudo flag-setting opcodes must be marked with 'hasPostISelHook'"

"converted opcode should be the same except for cc_out"

"expect uninitialized optional cc_out operand"

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


"frame index out of bounds: frame too large"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s>
void
rs6000_xcoff_declare_function_name
(
FILE
*
file
,
const
char
*
name
,
tree
decl
)
{
char
*
buffer
=
(
char
*
)
alloca
(
strlen
(
name
)
+
1
)
;
char
*
p
;
int
dollar_inside
=
0
;
struct
declare_alias_data
data
=
{
file
,
false
}
;
strcpy
(
buffer
,
name
)
;
p
=
strchr
(
buffer
,
'$'
)
;
while
(
p
)
{
*
p
=
'_'
;
dollar_inside
++
;
p
=
strchr
(
p
+
1
,
'$'
)
;
}
if
(
TREE_PUBLIC
(
decl
)
)
{
if
(
!
RS6000_WEAK
||
!
DECL_WEAK
(
decl
)
)
{
if
(
dollar_inside
)
{
fprintf
(
file
,
"\t.rename .%s,\".%s\"\n"
,
buffer
,
name
)
;
fprintf
(
file
,
"\t.rename %s,\"%s\"\n"
,
buffer
,
name
)
;
}
fputs
(
"\t.globl ."
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
fputs
(
rs6000_xcoff_visibility
(
decl
)
,
file
)
;
putc
(
'\n'
,
file
)
;
}
}
else
{
if
(
dollar_inside
)
{
fprintf
(
file
,
"\t.rename .%s,\".%s\"\n"
,
buffer
,
name
)
;
fprintf
(
file
,
"\t.rename %s,\"%s\"\n"
,
buffer
,
name
)
;
}
fputs
(
"\t.lglobl ."
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
putc
(
'\n'
,
file
)
;
}
fputs
(
"\t.csect "
,
file
)
;
assemble_name
(
file
,
buffer
)
;
fputs
(
TARGET_32BIT
"\n"
:
",3\n"
,
file
)
;
ASM_OUTPUT_LABEL
(
file
,
buffer
)
;
symtab_node
::
get
(
decl
)
->
call_for_symbol_and_aliases
(
rs6000_declare_alias
,
&
data
,
true
)
;
fputs
(
TARGET_32BIT
"\t.long ."
:
"\t.llong ."
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
fputs
(
", TOC[tc0], 0\n"
,
file
)
;
in_section
=
;
switch_to_section
(
function_section
(
decl
)
)
;
putc
(
'.'
,
file
)
;
ASM_OUTPUT_LABEL
(
file
,
buffer
)
;
data
.
function_descriptor
=
true
;
symtab_node
::
get
(
decl
)
->
call_for_symbol_and_aliases
(
rs6000_declare_alias
,
&
data
,
true
)
;
if
(
!
DECL_IGNORED_P
(
decl
)
)
{
if
(
write_symbols
==
DBX_DEBUG
||
write_symbols
==
XCOFF_DEBUG
)
xcoffout_declare_function
(
file
,
decl
,
buffer
)
;
else
if
(
dwarf_debuginfo_p
(
)
)
{
name
=
(
*
targetm
.
strip_name_encoding
)
(
name
)
;
fprintf
(
file
,
"\t.function .%s,.%s,2,0\n"
,
name
,
name
)
;
}
}
return
;
}
</s>

This macro produces the initial definition of a function name . On the RS/6000 , we need to place an extra ' . ' in the function name and output the function descriptor . Dollar signs are converted to underscores . The csect for the function will have already been created when text_section was selected . We do have to go back to that csect , however . The third and fourth parameters to the .function pseudo-op ( 16 and 044 ) are placeholders which no longer have any use . Because AIX assembler 's .set command has unexpected semantics , we output all aliases as alternative labels in front of the definition .