<s> static int pad_groups ( FILE * dump , int sched_verbose , rtx prev_head_insn , rtx tail ) { rtx insn , next_insn ; rtx nop ; int issue_rate ; int can_issue_more ; int group_end ; int group_count = 0 ; issue_rate = rs6000_issue_rate ( ) ; can_issue_more = issue_rate ; insn = get_next_active_insn ( prev_head_insn , tail ) ; next_insn = get_next_active_insn ( insn , tail ) ; while ( insn != NULL_RTX ) { can_issue_more = rs6000_variable_issue ( dump , sched_verbose , insn , can_issue_more ) ; group_end = ( next_insn == NULL_RTX || GET_MODE ( next_insn ) == TImode ) ; if ( next_insn == NULL_RTX ) break ; if ( group_end ) { if ( can_issue_more && ( rs6000_sched_insert_nops == sched_finish_pad_groups ) && ! insn_terminates_group_p ( insn , current_group ) && ! insn_terminates_group_p ( next_insn , previous_group ) ) { if ( ! is_branch_slot_insn ( next_insn ) ) can_issue_more -- ; while ( can_issue_more ) { nop = gen_nop ( ) ; emit_insn_before ( nop , next_insn ) ; can_issue_more -- ; } } can_issue_more = issue_rate ; group_count ++ ; } insn = next_insn ; next_insn = get_next_active_insn ( insn , tail ) ; } return group_count ; } </s>

Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the dispatch group boundaries that the scheduler had marked . Pad with nops any dispatch groups which have vacant issue slots , in order to force the scheduler 's grouping on the processor dispatcher . The function returns the number of dispatch groups found .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool isToken ( ) const override { return Kind == Token ; } </s>


<s> bool invalidate ( Function & , const PreservedAnalyses & ) { return false ; } </s>

Handle invalidation events from the new pass manager .


Set up the AsmPrinter when we are working on a new module .


<s> X86Subtarget :: X86Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , X86TargetMachine & TM , unsigned StackAlignOverride ) : X86GenSubtargetInfo ( TT , CPU , FS ) , X86ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TargetTriple ( TT ) , DL ( computeDataLayout ( TargetTriple ) ) , StackAlignOverride ( StackAlignOverride ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , TSInfo ( DL ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM ) , FrameLowering ( TargetFrameLowering :: StackGrowsDown , getStackAlignment ( ) , is64Bit ( ) ? - 8 : - 4 ) { if ( TM . getRelocationModel ( ) == Reloc :: Static ) { setPICStyle ( PICStyles :: None ) ; } else if ( is64Bit ( ) ) { setPICStyle ( PICStyles :: RIPRel ) ; } else if ( isTargetCOFF ( ) ) { setPICStyle ( PICStyles :: None ) ; } else if ( isTargetDarwin ( ) ) { if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( TM . getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( isTargetELF ( ) ) { setPICStyle ( PICStyles :: GOT ) ; } } </s>

This constructor initializes the data members to match that of the specified triple .


<s> bool nds32_symbol_load_store_p ( rtx_insn * insn ) { rtx mem_src = NULL_RTX ; switch ( get_attr_type ( insn ) ) { case TYPE_LOAD : mem_src = SET_SRC ( PATTERN ( insn ) ) ; break ; case TYPE_STORE : mem_src = SET_DEST ( PATTERN ( insn ) ) ; break ; default : break ; } if ( mem_src != NULL_RTX ) { if ( ( GET_CODE ( mem_src ) == ZERO_EXTEND ) || ( GET_CODE ( mem_src ) == SIGN_EXTEND ) ) mem_src = XEXP ( mem_src , 0 ) ; if ( ( GET_CODE ( XEXP ( mem_src , 0 ) ) == SYMBOL_REF ) || ( GET_CODE ( XEXP ( mem_src , 0 ) ) == LO_SUM ) ) return true ; } return false ; } </s>

Return true if is load/store with SYMBOL_REF addressing mode and memory mode is SImode .


<s> StringRef getPassName ( ) const override { return AARCH64_ADVSIMD_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> bool Mips16FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; for ( const CalleeSavedInfo & I : CSI ) { Register Reg = I . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == Mips :: RA ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) MBB . addLiveIn ( Reg ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { LoopPass :: getAnalysisUsage ( AU ) ; AU . addRequired < AssumptionCacheTracker > ( ) ; AU . addRequired < ScalarEvolutionWrapperPass > ( ) ; AU . addRequired < AAResultsWrapperPass > ( ) ; AU . addRequired < TargetLibraryInfoWrapperPass > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addRequired < TargetPassConfig > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; AU . setPreservesCFG ( ) ; } </s>


<s> static bool aarch64_macro_fusion_p ( void ) { return aarch64_tune_params -> fuseable_ops != AARCH64_FUSE_NOTHING ; } </s>

Implement TARGET_SCHED_MACRO_FUSION_P . Return true if target supports instruction fusion of some sort .


<s> void rs6000_emit_eh_reg_restore ( rtx source , rtx scratch ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; rtx operands [ 2 ] ; operands [ 0 ] = source ; operands [ 1 ] = scratch ; if ( info -> lr_save_p ) { rtx frame_rtx = stack_pointer_rtx ; HOST_WIDE_INT sp_offset = 0 ; rtx tmp ; if ( frame_pointer_needed || current_function_calls_alloca || info -> total_size > 32767 ) { tmp = gen_rtx_MEM ( Pmode , frame_rtx ) ; MEM_NOTRAP_P ( tmp ) = 1 ; set_mem_alias_set ( tmp , rs6000_sr_alias_set ) ; emit_move_insn ( operands [ 1 ] , tmp ) ; frame_rtx = operands [ 1 ] ; } else if ( info -> push_p ) sp_offset = info -> total_size ; tmp = plus_constant ( frame_rtx , info -> lr_save_offset + sp_offset ) ; tmp = gen_rtx_MEM ( Pmode , tmp ) ; MEM_NOTRAP_P ( tmp ) = 1 ; set_mem_alias_set ( tmp , rs6000_sr_alias_set ) ; emit_move_insn ( tmp , operands [ 0 ] ) ; } else emit_move_insn ( gen_rtx_REG ( Pmode , LINK_REGISTER_REGNUM ) , operands [ 0 ] ) ; } </s>

Emit instructions to restore the link register after determining where its value has been stored .


<s> int num_insns_constant ( rtx op , machine_mode mode ) { HOST_WIDE_INT val ; switch ( GET_CODE ( op ) ) { case CONST_INT : val = INTVAL ( op ) ; break ; case CONST_WIDE_INT : { int insns = 0 ; for ( int i = 0 ; i < CONST_WIDE_INT_NUNITS ( op ) ; i ++ ) insns += num_insns_constant_multi ( CONST_WIDE_INT_ELT ( op , i ) , DImode ) ; return insns ; } case CONST_DOUBLE : { const struct real_value * rv = CONST_DOUBLE_REAL_VALUE ( op ) ; if ( mode == SFmode || mode == SDmode ) { long l ; if ( mode == SDmode ) REAL_VALUE_TO_TARGET_DECIMAL32 ( * rv , l ) ; else REAL_VALUE_TO_TARGET_SINGLE ( * rv , l ) ; val = l ; mode = SImode ; } else if ( mode == DFmode || mode == DDmode ) { long l [ 2 ] ; if ( mode == DDmode ) REAL_VALUE_TO_TARGET_DECIMAL64 ( * rv , l ) ; else REAL_VALUE_TO_TARGET_DOUBLE ( * rv , l ) ; val = ( unsigned HOST_WIDE_INT ) l [ WORDS_BIG_ENDIAN ? 0 : 1 ] << 32 ; val |= l [ WORDS_BIG_ENDIAN ? 1 : 0 ] & 0xffffffffUL ; mode = DImode ; } else if ( mode == TFmode || mode == TDmode || mode == KFmode || mode == IFmode ) { long l [ 4 ] ; int insns ; if ( mode == TDmode ) REAL_VALUE_TO_TARGET_DECIMAL128 ( * rv , l ) ; else REAL_VALUE_TO_TARGET_LONG_DOUBLE ( * rv , l ) ; val = ( unsigned HOST_WIDE_INT ) l [ WORDS_BIG_ENDIAN ? 0 : 3 ] << 32 ; val |= l [ WORDS_BIG_ENDIAN ? 1 : 2 ] & 0xffffffffUL ; insns = num_insns_constant_multi ( val , DImode ) ; val = ( unsigned HOST_WIDE_INT ) l [ WORDS_BIG_ENDIAN ? 2 : 1 ] << 32 ; val |= l [ WORDS_BIG_ENDIAN ? 3 : 0 ] & 0xffffffffUL ; insns += num_insns_constant_multi ( val , DImode ) ; return insns ; } else gcc_unreachable ( ) ; } break ; default : gcc_unreachable ( ) ; } return num_insns_constant_multi ( val , mode ) ; } </s>

Return the number of instructions it takes to form a constant in as many gprs are needed for MODE .


<s> int single_const_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { if ( big_const_operand ( op , mode ) || GET_CODE ( op ) == CONST || GET_CODE ( op ) == LABEL_REF || GET_CODE ( op ) == SYMBOL_REF ) return 0 ; return 1 ; } </s>

Return truth value of whether OP is a constant that require only one load to put in a register .


<s> void setDesc ( const MCInstrDesc & mcid ) { MCID = & mcid ; } </s>

Replace the instruction descriptor ( thus opcode ) of the current instruction with a new one .


<s>
MachineOperand
&
AArch64InstrInfo
::
getMemOpBaseRegImmOfsOffsetOperand
(
MachineInstr
&
LdSt
)
const
{
assert
(
LdSt
.
mayLoadOrStore
(
)
&&
"Expected a memory operation."
)
;
MachineOperand
&
OfsOp
=
LdSt
.
getOperand
(
LdSt
.
getNumExplicitOperands
(
)
1
)
;
assert
(
OfsOp
.
isImm
(
)
&&
"Offset operand wasn't immediate."
)
;
return
OfsOp
;
}
</s>

Return the immediate offset of the base register in a load/store LdSt .


<s> bool AArch64PassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnablePromoteConstant ) addPass ( createAArch64PromoteConstantPass ( ) ) ; if ( ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE ) { bool OnlyOptimizeForSize = ( TM -> getOptLevel ( ) < CodeGenOpt :: Aggressive ) && ( EnableGlobalMerge == cl :: BOU_UNSET ) ; addPass ( createGlobalMergePass ( TM , 4095 , OnlyOptimizeForSize ) ) ; } if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createAArch64AddressTypePromotionPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableSVEPostVec ) { addPass ( createSVEAddressingModesPass ( ) ) ; addPass ( createDeadCodeEliminationPass ( ) ) ; } return false ; } </s>


<s> bool MCS51ShiftExpand :: runOnFunction ( Function & F ) { SmallVector < BinaryOperator * , 1 > ShiftInsts ; auto & Ctx = F . getContext ( ) ; for ( Instruction & I : instructions ( F ) ) { if ( ! I . isShift ( ) ) continue ; if ( I . getType ( ) != Type :: getInt32Ty ( Ctx ) ) continue ; if ( isa < ConstantInt > ( I . getOperand ( 1 ) ) ) continue ; ShiftInsts . push_back ( cast < BinaryOperator > ( & I ) ) ; } for ( auto * I : ShiftInsts ) { expand ( I ) ; } return ShiftInsts . size ( ) > 0 ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool AArch64InstrInfo :: isPreLd ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { default : return false ; case AArch64 :: LDRWpre : case AArch64 :: LDRXpre : case AArch64 :: LDRSpre : case AArch64 :: LDRDpre : case AArch64 :: LDRQpre : return true ; } } </s>

Returns whether the instruction is a pre-indexed load .


<s> bool RISCVPassConfig :: addInstSelector ( ) { addPass ( createRISCVISelDag ( getRISCVTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void mn10300_split_cbranch ( machine_mode cmp_mode , rtx cmp_op , rtx label_ref ) { rtx flags , x ; flags = gen_rtx_REG ( cmp_mode , CC_REG ) ; x = gen_rtx_COMPARE ( cmp_mode , XEXP ( cmp_op , 0 ) , XEXP ( cmp_op , 1 ) ) ; x = gen_rtx_SET ( flags , x ) ; emit_insn ( x ) ; x = gen_rtx_fmt_ee ( GET_CODE ( cmp_op ) , VOIDmode , flags , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , label_ref , pc_rtx ) ; x = gen_rtx_SET ( pc_rtx , x ) ; emit_jump_insn ( x ) ; } </s>

A helper function for splitting cbranch patterns after reload .


<s> static void aarch64_emit_load_exclusive ( machine_mode mode , rtx rval , rtx mem , rtx model_rtx ) { if ( mode == TImode ) emit_insn ( gen_aarch64_load_exclusive_pair ( gen_lowpart ( DImode , rval ) , gen_highpart ( DImode , rval ) , mem , model_rtx ) ) ; else emit_insn ( gen_aarch64_load_exclusive ( mode , rval , mem , model_rtx ) ) ; } </s>


<s> void SITargetLowering :: AdjustInstrPostInstrSelection ( MachineInstr & MI , SDNode * Node ) const { const SIInstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; if ( TII -> isVOP3 ( MI . getOpcode ( ) ) ) { TII -> legalizeOperandsVOP3 ( MRI , MI ) ; return ; } if ( TII -> isMIMG ( MI ) ) { unsigned VReg = MI . getOperand ( 0 ) . getReg ( ) ; unsigned DmaskIdx = MI . getNumOperands ( ) == 12 ? 3 : 4 ; unsigned Writemask = MI . getOperand ( DmaskIdx ) . getImm ( ) ; unsigned BitsSet = 0 ; for ( unsigned i = 0 ; i < 4 ; ++ i ) BitsSet += Writemask & ( 1 << i ) ? 1 : 0 ; const TargetRegisterClass * RC ; switch ( BitsSet ) { default : return ; case 1 : RC = & AMDGPU :: VGPR_32RegClass ; break ; case 2 : RC = & AMDGPU :: VReg_64RegClass ; break ; case 3 : RC = & AMDGPU :: VReg_96RegClass ; break ; } unsigned NewOpcode = TII -> getMaskedMIMGOp ( MI . getOpcode ( ) , BitsSet ) ; MI . setDesc ( TII -> get ( NewOpcode ) ) ; MRI . setRegClass ( VReg , RC ) ; return ; } int NoRetAtomicOp = AMDGPU :: getAtomicNoRetOp ( MI . getOpcode ( ) ) ; if ( NoRetAtomicOp != - 1 ) { if ( ! Node -> hasAnyUseOfValue ( 0 ) ) { MI . setDesc ( TII -> get ( NoRetAtomicOp ) ) ; MI . RemoveOperand ( 0 ) ; return ; } if ( ( Node -> hasNUsesOfValue ( 1 , 0 ) && Node -> use_begin ( ) -> isMachineOpcode ( ) && Node -> use_begin ( ) -> getMachineOpcode ( ) == AMDGPU :: EXTRACT_SUBREG && ! Node -> use_begin ( ) -> hasAnyUseOfValue ( 0 ) ) ) { unsigned Def = MI . getOperand ( 0 ) . getReg ( ) ; MI . setDesc ( TII -> get ( NoRetAtomicOp ) ) ; MI . RemoveOperand ( 0 ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , TII -> get ( AMDGPU :: IMPLICIT_DEF ) , Def ) ; } return ; } } </s>

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


<s> SDValue HSAILTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { case ISD :: INTRINSIC_WO_CHAIN : return PerformIntrinsic_Wo_ChainCombine ( N , DCI ) ; default : break ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> unsigned int TL45AsmBackend :: getNumFixupKinds ( ) const { return TL45 :: Fixups :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> bool targetHandlesStackFrameRounding ( ) const override { return true ; } </s>

targetHandlesStackFrameRounding - Returns true if the target is responsible for rounding up the stack frame ( probably at emitPrologue time ) .


<s> static bool ft32_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { return 1 ; return ( to == FRAME_POINTER_REGNUM ) || ! ft32_frame_pointer_required ( ) ; } </s>

Return true if register FROM can be eliminated via register TO .


<s> bool GCNPassConfig :: addPreISel ( ) { AMDGPUPassConfig :: addPreISel ( ) ; addPass ( & AMDGPUAnnotateKernelFeaturesID ) ; addPass ( createStructurizeCFGPass ( true ) ) ; addPass ( createSinkingPass ( ) ) ; addPass ( createSITypeRewriter ( ) ) ; addPass ( createAMDGPUAnnotateUniformValues ( ) ) ; addPass ( createSIAnnotateControlFlowPass ( ) ) ; return false ; } </s>


"Unmatched number of shufflevectors and indices"

Lower interleaved load ( s ) into target specific instructions/intrinsics .


<s>
virtual
StringRef
getPassName
(
)
const
override
{
return
"P2 Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
const
RegisterBank
&
AArch64RegisterBankInfo
::
getRegBankFromRegClass
(
const
TargetRegisterClass
&
RC
,
LLT
)
const
{
switch
(
RC
.
getID
(
)
)
{
case
AArch64
::
FPR8RegClassID
:
case
AArch64
::
FPR16RegClassID
:
case
AArch64
::
FPR32RegClassID
:
case
AArch64
::
FPR64RegClassID
:
case
AArch64
::
FPR64_loRegClassID
:
case
AArch64
::
FPR128RegClassID
:
case
AArch64
::
FPR128_loRegClassID
:
case
AArch64
::
DDRegClassID
:
case
AArch64
::
DDDRegClassID
:
case
AArch64
::
DDDDRegClassID
:
case
AArch64
::
QQRegClassID
:
case
AArch64
::
QQQRegClassID
:
case
AArch64
::
QQQQRegClassID
:
return
getRegBank
(
AArch64
::
FPRRegBankID
)
;
case
AArch64
::
GPR32commonRegClassID
:
case
AArch64
::
GPR32RegClassID
:
case
AArch64
::
GPR32spRegClassID
:
case
AArch64
::
GPR32sponlyRegClassID
:
case
AArch64
::
GPR32argRegClassID
:
case
AArch64
::
GPR32allRegClassID
:
case
AArch64
::
GPR64commonRegClassID
:
case
AArch64
::
GPR64RegClassID
:
case
AArch64
::
GPR64spRegClassID
:
case
AArch64
::
GPR64sponlyRegClassID
:
case
AArch64
::
GPR64argRegClassID
:
case
AArch64
::
GPR64allRegClassID
:
case
AArch64
::
GPR64noipRegClassID
:
case
AArch64
::
GPR64common_and_GPR64noipRegClassID
:
case
AArch64
::
GPR64noip_and_tcGPR64RegClassID
:
case
AArch64
::
tcGPR64RegClassID
:
case
AArch64
::
WSeqPairsClassRegClassID
:
case
AArch64
::
XSeqPairsClassRegClassID
:
return
getRegBank
(
AArch64
::
GPRRegBankID
)
;
case
AArch64
::
CCRRegClassID
:
return
getRegBank
(
AArch64
::
CCRegBankID
)
;
default
:
llvm_unreachable
(
"Register class not supported"
)
;
}
}
</s>


<s> static unsigned s390_loop_unroll_adjust ( unsigned nunroll , struct loop * loop ) { basic_block * bbs ; rtx_insn * insn ; unsigned i ; unsigned mem_count = 0 ; if ( s390_tune < PROCESSOR_2097_Z10 ) return nunroll ; bbs = get_loop_body ( loop ) ; subrtx_iterator :: array_type array ; for ( i = 0 ; i < loop -> num_nodes ; i ++ ) FOR_BB_INSNS ( bbs [ i ] , insn ) if ( INSN_P ( insn ) && INSN_CODE ( insn ) != - 1 ) FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , NONCONST ) if ( MEM_P ( * iter ) ) mem_count += 1 ; free ( bbs ) ; if ( mem_count == 0 ) return nunroll ; switch ( loop_depth ( loop ) ) { case 1 : return MIN ( nunroll , 28 / mem_count ) ; case 2 : return MIN ( nunroll , 22 / mem_count ) ; default : return MIN ( nunroll , 16 / mem_count ) ; } } </s>

This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates a new number struct loop * loop should be unrolled if tuned for cpus with a built-in stride prefetcher . The loop is analyzed for memory accesses by calling check_dpu for each rtx of the loop . Depending on the loop_depth and the amount of memory accesses a new number < =nunroll is returned to improve the behaviour of the hardware prefetch unit .


<s> bool AMDGPUInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock * MBB = MI -> getParent ( ) ; int OffsetOpIdx = AMDGPU :: getNamedOperandIdx ( MI -> getOpcode ( ) , AMDGPU :: OpName :: addr ) ; int RegOpIdx = OffsetOpIdx + 1 ; int ChanOpIdx = AMDGPU :: getNamedOperandIdx ( MI -> getOpcode ( ) , AMDGPU :: OpName :: chan ) ; if ( isRegisterLoad ( * MI ) ) { int DstOpIdx = AMDGPU :: getNamedOperandIdx ( MI -> getOpcode ( ) , AMDGPU :: OpName :: dst ) ; unsigned RegIndex = MI -> getOperand ( RegOpIdx ) . getImm ( ) ; unsigned Channel = MI -> getOperand ( ChanOpIdx ) . getImm ( ) ; unsigned Address = calculateIndirectAddress ( RegIndex , Channel ) ; unsigned OffsetReg = MI -> getOperand ( OffsetOpIdx ) . getReg ( ) ; if ( OffsetReg == AMDGPU :: INDIRECT_BASE_ADDR ) { buildMovInstr ( MBB , MI , MI -> getOperand ( DstOpIdx ) . getReg ( ) , getIndirectAddrRegClass ( ) -> getRegister ( Address ) ) ; } else { buildIndirectRead ( MBB , MI , MI -> getOperand ( DstOpIdx ) . getReg ( ) , Address , OffsetReg ) ; } } else if ( isRegisterStore ( * MI ) ) { int ValOpIdx = AMDGPU :: getNamedOperandIdx ( MI -> getOpcode ( ) , AMDGPU :: OpName :: val ) ; unsigned RegIndex = MI -> getOperand ( RegOpIdx ) . getImm ( ) ; unsigned Channel = MI -> getOperand ( ChanOpIdx ) . getImm ( ) ; unsigned Address = calculateIndirectAddress ( RegIndex , Channel ) ; unsigned OffsetReg = MI -> getOperand ( OffsetOpIdx ) . getReg ( ) ; if ( OffsetReg == AMDGPU :: INDIRECT_BASE_ADDR ) { buildMovInstr ( MBB , MI , getIndirectAddrRegClass ( ) -> getRegister ( Address ) , MI -> getOperand ( ValOpIdx ) . getReg ( ) ) ; } else { buildIndirectWrite ( MBB , MI , MI -> getOperand ( ValOpIdx ) . getReg ( ) , calculateIndirectAddress ( RegIndex , Channel ) , OffsetReg ) ; } } else { return false ; } MBB -> erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .

AMDGPU AMDGPU AMDGPU::getNamedOperandIdx AMDGPU::OpName 1 AMDGPU::getNamedOperandIdx AMDGPU::OpName AMDGPU::getNamedOperandIdx AMDGPU::OpName AMDGPU::INDIRECT_BASE_ADDR AMDGPU::getNamedOperandIdx AMDGPU::OpName AMDGPU::INDIRECT_BASE_ADDR


<s> void AMDGPUSubtarget :: overrideSchedPolicy ( MachineSchedPolicy & Policy , MachineInstr * begin , MachineInstr * end , unsigned NumRegionInstrs ) const { if ( getGeneration ( ) >= SOUTHERN_ISLANDS ) { Policy . ShouldTrackPressure = true ; Policy . OnlyTopDown = false ; Policy . OnlyBottomUp = false ; } } </s>

Override generic scheduling policy within a region .


<s> unsigned size ( ) const { return IDs . size ( ) ; } </s>

The number of name/type pairs is returned .


<s> bool X86InstrInfo :: isDataInvariant ( MachineInstr & MI ) { if ( MI . mayLoad ( ) || MI . mayStore ( ) ) return false ; if ( MI . isCopyLike ( ) || MI . isInsertSubreg ( ) ) return true ; unsigned Opcode = MI . getOpcode ( ) ; using namespace X86 ; if ( isIMUL ( Opcode ) ) return true ; if ( isBSF ( Opcode ) || isBSR ( Opcode ) || isLZCNT ( Opcode ) || isPOPCNT ( Opcode ) || isTZCNT ( Opcode ) ) return true ; if ( isBLCFILL ( Opcode ) || isBLCI ( Opcode ) || isBLCIC ( Opcode ) || isBLCMSK ( Opcode ) || isBLCS ( Opcode ) || isBLSFILL ( Opcode ) || isBLSI ( Opcode ) || isBLSIC ( Opcode ) || isBLSMSK ( Opcode ) || isBLSR ( Opcode ) || isTZMSK ( Opcode ) ) return true ; if ( isBEXTR ( Opcode ) || isBZHI ( Opcode ) ) return true ; if ( isROL ( Opcode ) || isROR ( Opcode ) || isSAR ( Opcode ) || isSHL ( Opcode ) || isSHR ( Opcode ) || isSHLD ( Opcode ) || isSHRD ( Opcode ) ) return true ; if ( isADC ( Opcode ) || isADD ( Opcode ) || isAND ( Opcode ) || isOR ( Opcode ) || isSBB ( Opcode ) || isSUB ( Opcode ) || isXOR ( Opcode ) ) return true ; if ( isADCX ( Opcode ) || isADOX ( Opcode ) || isANDN ( Opcode ) ) return true ; if ( isDEC ( Opcode ) || isINC ( Opcode ) || isNEG ( Opcode ) ) return true ; if ( isNOT ( Opcode ) ) return true ; if ( isMOVSX ( Opcode ) || isMOVZX ( Opcode ) || isMOVSXD ( Opcode ) || isMOV ( Opcode ) ) return true ; if ( isRORX ( Opcode ) || isSARX ( Opcode ) || isSHLX ( Opcode ) || isSHRX ( Opcode ) ) return true ; if ( isLEA ( Opcode ) ) return true ; return false ; } </s>

Returns true if the instruction has no behavior ( specified or otherwise ) that is based on the value of any of its register operands .


<s> bool PPCInstrInfo :: isPredicable ( MachineInstr & MI ) const { unsigned OpC = MI . getOpcode ( ) ; switch ( OpC ) { default : return false ; case PPC :: B : case PPC :: BLR : case PPC :: BLR8 : case PPC :: BCTR : case PPC :: BCTR8 : case PPC :: BCTRL : case PPC :: BCTRL8 : return true ; } } </s>

Return true if the specified instruction can be predicated .

PowerPC PPC PPC::B PPC::BLR PPC::BLR8 PPC::BCTR PPC::BCTR8 PPC::BCTRL PPC::BCTRL8


<s> virtual const MSP430InstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


"Warning: Illegal instruction detected: "

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static int mergeSPUpdates ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , bool doMergeWithPrevious ) { if ( ( doMergeWithPrevious && MBBI == MBB . begin ( ) ) || ( ! doMergeWithPrevious && MBBI == MBB . end ( ) ) ) return 0 ; MachineBasicBlock :: iterator PI = doMergeWithPrevious ? prior ( MBBI ) : MBBI ; MachineBasicBlock :: iterator NI = doMergeWithPrevious ? 0 : next ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = 0 ; if ( ( Opc == X86 :: ADD64ri32 || Opc == X86 :: ADD64ri8 || Opc == X86 :: ADD32ri || Opc == X86 :: ADD32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { Offset += PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == X86 :: SUB64ri32 || Opc == X86 :: SUB64ri8 || Opc == X86 :: SUB32ri || Opc == X86 :: SUB32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { Offset -= PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } return Offset ; } </s>

Check the instruction before/after the passed instruction .


"End of MachineConstPropagator (Changed="

Run the analysis pass over a function and produce a dominator tree .


<s> static tree ia64_gimplify_va_arg ( tree valist , tree type , gimple_seq * pre_p , gimple_seq * post_p ) { if ( pass_va_arg_by_reference ( type ) ) { tree ptrtype = build_pointer_type ( type ) ; tree addr = std_gimplify_va_arg_expr ( valist , ptrtype , pre_p , post_p ) ; return build_va_arg_indirect_ref ( addr ) ; } if ( ( TREE_CODE ( type ) == REAL_TYPE || TREE_CODE ( type ) == INTEGER_TYPE ) ? int_size_in_bytes ( type ) > 8 : TYPE_ALIGN ( type ) > 8 * BITS_PER_UNIT ) { tree t = fold_build_pointer_plus_hwi ( valist , 2 * UNITS_PER_WORD - 1 ) ; t = build2 ( BIT_AND_EXPR , TREE_TYPE ( t ) , t , build_int_cst ( TREE_TYPE ( t ) , - 2 * UNITS_PER_WORD ) ) ; gimplify_assign ( unshare_expr ( valist ) , t , pre_p ) ; } return std_gimplify_va_arg_expr ( valist , type , pre_p , post_p ) ; } </s>


<s> static bool rs6000_optab_supported_p ( int op , machine_mode mode1 , machine_mode , optimization_type opt_type ) { switch ( op ) { case rsqrt_optab : return ( opt_type == OPTIMIZE_FOR_SPEED && RS6000_RECIP_AUTO_RSQRTE_P ( mode1 ) ) ; default : return true ; } } </s>

Implement the TARGET_OPTAB_SUPPORTED_P hook .


<s> void rs6000_emit_swdiv ( rtx dst , rtx n , rtx d , bool note_p ) { machine_mode mode = GET_MODE ( dst ) ; rtx one , x0 , e0 , x1 , xprev , eprev , xnext , enext , u , v ; int i ; int passes = ( TARGET_RECIP_PRECISION ) ? 1 : 3 ; if ( mode == DFmode || mode == V2DFmode ) passes ++ ; enum insn_code code = optab_handler ( smul_optab , mode ) ; insn_gen_fn gen_mul = GEN_FCN ( code ) ; gcc_assert ( code != CODE_FOR_nothing ) ; one = rs6000_load_constant_and_splat ( mode , dconst1 ) ; x0 = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , d ) , UNSPEC_FRES ) ) ) ; if ( passes > 1 ) { e0 = gen_reg_rtx ( mode ) ; rs6000_emit_nmsub ( e0 , d , x0 , one ) ; x1 = gen_reg_rtx ( mode ) ; rs6000_emit_madd ( x1 , e0 , x0 , x0 ) ; for ( i = 0 , xprev = x1 , eprev = e0 ; i < passes - 2 ; ++ i , xprev = xnext , eprev = enext ) { enext = gen_reg_rtx ( mode ) ; emit_insn ( gen_mul ( enext , eprev , eprev ) ) ; xnext = gen_reg_rtx ( mode ) ; rs6000_emit_madd ( xnext , enext , xprev , xprev ) ; } } else xprev = x0 ; u = gen_reg_rtx ( mode ) ; emit_insn ( gen_mul ( u , n , xprev ) ) ; v = gen_reg_rtx ( mode ) ; rs6000_emit_nmsub ( v , d , u , n ) ; rs6000_emit_madd ( dst , v , xprev , u ) ; if ( note_p ) add_reg_note ( get_last_insn ( ) , REG_EQUAL , gen_rtx_DIV ( mode , n , d ) ) ; } </s>

Newton-Raphson approximation of floating point divide DST = N/D . If NOTE_P , add a reg_note saying that this was a division . Support both scalar and vector divide . Assumes no trapping math and finite arguments .


<s>
const
RegisterBankInfo
*
getRegBankInfo
(
)
const
override
{
assert
(
GISel
&&
"Access to GlobalISel APIs not set"
)
;
return
GISel
->
getRegBankInfo
(
)
;
}
</s>

If the information for the register banks is available , return it .

AMDGPU
"Access to GlobalISel APIs not set"


<s> MachineInstr * SystemZInstrInfo :: convertToThreeAddress ( MachineFunction :: iterator & MFI , MachineInstr & MI , LiveVariables * LV ) const { MachineBasicBlock * MBB = MI . getParent ( ) ; if ( LogicOp And = interpretAndImmediate ( MI . getOpcode ( ) ) ) { uint64_t Imm = MI . getOperand ( 2 ) . getImm ( ) << And . ImmLSB ; Imm |= allOnes ( And . RegSize ) & ~ ( allOnes ( And . ImmSize ) << And . ImmLSB ) ; unsigned Start , End ; if ( isRxSBGMask ( Imm , And . RegSize , Start , End ) ) { unsigned NewOpcode ; if ( And . RegSize == 64 ) { NewOpcode = SystemZ :: RISBG ; if ( STI . hasMiscellaneousExtensions ( ) ) NewOpcode = SystemZ :: RISBGN ; } else { NewOpcode = SystemZ :: RISBMux ; Start &= 31 ; End &= 31 ; } MachineOperand & Dest = MI . getOperand ( 0 ) ; MachineOperand & Src = MI . getOperand ( 1 ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( NewOpcode ) ) . add ( Dest ) . addReg ( 0 ) . addReg ( Src . getReg ( ) , getKillRegState ( Src . isKill ( ) ) , Src . getSubReg ( ) ) . addImm ( Start ) . addImm ( End + 128 ) . addImm ( 0 ) ; if ( LV ) { unsigned NumOps = MI . getNumOperands ( ) ; for ( unsigned I = 1 ; I < NumOps ; ++ I ) { MachineOperand & Op = MI . getOperand ( I ) ; if ( Op . isReg ( ) && Op . isKill ( ) ) LV -> replaceKillInstruction ( Op . getReg ( ) , MI , * MIB ) ; } } transferDeadCC ( & MI , MIB ) ; return MIB ; } } return nullptr ; } </s>

convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag .


<s> bool z8k_regno_ok_for_base_p ( int regno , bool strict_p ) { if ( regno < FIRST_PSEUDO_REGISTER && regno != 0 ) { if ( ! strict_p ) return true ; if ( ! reg_renumber ) return false ; regno = reg_renumber [ regno ] ; } return regno < FIRST_PSEUDO_REGISTER && regno > 0 ; } </s>

It 's ok for a base reg if it 's in a hard reg which is not 0 or it will be renumbered on the way out and its not -1 or 0


"instruction requires a WASM feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> SDValue PPCTargetLowering :: getPICJumpTableRelocBase ( SDValue Table , SelectionDAG & DAG ) const { if ( ! Subtarget . isPPC64 ( ) || Subtarget . isAIXABI ( ) ) return TargetLowering :: getPICJumpTableRelocBase ( Table , DAG ) ; switch ( getTargetMachine ( ) . getCodeModel ( ) ) { case CodeModel :: Small : case CodeModel :: Medium : return TargetLowering :: getPICJumpTableRelocBase ( Table , DAG ) ; default : return DAG . getNode ( PPCISD :: GlobalBaseReg , SDLoc ( ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; } } </s>

Returns relocation base for the given PIC jumptable .


<s> rtx alpha_gp_save_rtx ( void ) { rtx seq , m = cfun -> machine -> gp_save_rtx ; if ( m == NULL ) { start_sequence ( ) ; m = assign_stack_local ( DImode , UNITS_PER_WORD , BITS_PER_WORD ) ; m = validize_mem ( m ) ; emit_move_insn ( m , pic_offset_table_rtx ) ; seq = get_insns ( ) ; end_sequence ( ) ; emit_insn_after ( seq , entry_of_function ( ) ) ; cfun -> machine -> gp_save_rtx = m ; } return m ; } </s>

Return or create a pseudo containing the gp value for the current function . Needed only if TARGET_LD_BUGGY_LDGP .


<s> bool addrSinkUsingGEPs ( ) const override { return useAA ( ) || isTargetILP32 ( ) ; } </s>

Sink addresses into blocks using GEP instructions rather than pointer casts and arithmetic .


<s> bool AZPRPassConfig :: addPreEmitPass ( ) { addPass ( createAZPRDelaySlotFillerPass ( getAZPRTargetMachine ( ) ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static void aarch64_emit_sve_predicated_cond ( rtx target , rtx_code code , rtx pred , rtx op0 , rtx op1 ) { rtx unspec = gen_rtx_UNSPEC ( GET_MODE ( pred ) , gen_rtvec ( 3 , pred , op0 , op1 ) , aarch64_unspec_cond_code ( code ) ) ; emit_set_insn ( target , unspec ) ; } </s>

Emit : ( set TARGET ( unspec [ PRED OP0 OP1 ] UNSPEC_COND_ < X > ) ) where < X > is the operation associated with comparison CODE . This form of instruction is used when ( and ( CODE OP0 OP1 ) PRED ) would have different semantics , such as when PRED might not be all-true and when comparing inactive lanes could have side effects .


<s> MCObjectWriter * SICAsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { return createSICELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI ( OSType ) , IsLittle ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s>
static
const
char
*
pru_output_ltle_signed_cbranch
(
rtx
*
operands
,
bool
is_near
)
{
static
char
buf
[
1024
]
;
enum
rtx_code
code
=
GET_CODE
(
operands
[
0
]
)
;
rtx
op1
;
rtx
op2
;
const
char
*
cmp_opstr
;
int
bufi
=
0
;
op1
=
operands
[
1
]
;
op2
=
operands
[
2
]
;
gcc_assert
(
GET_CODE
(
op1
)
==
REG
&&
GET_CODE
(
op2
)
==
REG
)
;
if
(
code
==
LT
)
cmp_opstr
=
"qblt"
;
else
if
(
code
==
LE
)
cmp_opstr
=
"qble"
;
else
gcc_unreachable
(
)
;
if
(
is_near
)
bufi
=
snprintf
(
buf
,
sizeof
(
buf
)
,
"qbbc\t.+12, %%1, %d\n\t"
"qbbc\t%%l3, %%2, %d\n\t"
"%s\t%%l3, %%2, %%1\n\t"
"qbbs\t.+8, %%2, %d\n\t"
"%s\t%%l3, %%2, %%1"
,
sign_bit_position
(
op1
)
,
sign_bit_position
(
op2
)
,
cmp_opstr
,
sign_bit_position
(
op2
)
,
cmp_opstr
)
;
else
bufi
=
snprintf
(
buf
,
sizeof
(
buf
)
,
"qbbc\t.+12, %%1, %d\n\t"
"qbbc\t.+20, %%2, %d\n\t"
"%s\t.+16, %%2, %%1\n\t"
"qbbs\t.+16, %%2, %d\n\t"
"%s\t.+8, %%2, %%1\n\t"
"jmp\t.+8\n\t"
"jmp\t%%%%label(%%l3)"
,
sign_bit_position
(
op1
)
,
sign_bit_position
(
op2
)
,
cmp_opstr
,
sign_bit_position
(
op2
)
,
cmp_opstr
)
;
gcc_assert
(
bufi
>
0
)
;
gcc_assert
(
(
unsigned
int
)
bufi
<
sizeof
(
buf
)
)
;
return
buf
;
}
</s>

Output asm code for a signed-compare LT/LE conditional branch .


<s> bool X86PassConfig :: addPreEmitPass ( ) { bool ShouldPrint = false ; if ( getOptLevel ( ) != CodeGenOpt :: None && getX86Subtarget ( ) . hasSSE2 ( ) ) { addPass ( createExecutionDependencyFixPass ( & X86 :: VR128RegClass ) ) ; ShouldPrint = true ; } if ( getX86Subtarget ( ) . hasAVX ( ) && UseVZeroUpper ) { addPass ( createX86IssueVZeroUpperPass ( ) ) ; ShouldPrint = true ; } if ( getOptLevel ( ) != CodeGenOpt :: None && getX86Subtarget ( ) . padShortFunctions ( ) ) { addPass ( createX86PadShortFunctions ( ) ) ; ShouldPrint = true ; } if ( getX86Subtarget ( ) . isTargetNaCl ( ) ) { addPass ( createX86NaClRewritePass ( ) ) ; ShouldPrint = true ; } return ShouldPrint ; } </s>


<s> Value * AArch64TargetLowering :: emitLoadLinked ( IRBuilder < > & Builder , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Type * ValTy = cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ; bool IsAcquire = Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent ; if ( ValTy -> getPrimitiveSizeInBits ( ) == 128 ) { Intrinsic :: ID Int = IsAcquire ? Intrinsic :: aarch64_ldaxp : Intrinsic :: aarch64_ldxp ; Function * Ldxr = llvm :: Intrinsic :: getDeclaration ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldxr , Addr , "lohi" ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ; Lo = Builder . CreateZExt ( Lo , ValTy , "lo64" ) ; Hi = Builder . CreateZExt ( Hi , ValTy , "hi64" ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , 64 ) ) , "val64" ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; Intrinsic :: ID Int = IsAcquire ? Intrinsic :: aarch64_ldaxr : Intrinsic :: aarch64_ldxr ; Function * Ldxr = llvm :: Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateTruncOrBitCast ( Builder . CreateCall ( Ldxr , Addr ) , cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ) ; } </s>

Perform a load-linked operation on Addr , returning a `` Value * '' with the corresponding pointee type .


<s> MVT X86TargetLowering :: hasFastEqualityCompare ( unsigned NumBits ) const { MVT VT = MVT :: getIntegerVT ( NumBits ) ; if ( isTypeLegal ( VT ) ) return VT ; if ( NumBits == 128 && isTypeLegal ( MVT :: v16i8 ) ) return MVT :: v16i8 ; if ( NumBits == 256 && isTypeLegal ( MVT :: v32i8 ) ) return MVT :: v32i8 ; return MVT :: INVALID_SIMPLE_VALUE_TYPE ; } </s>

Vector-sized comparisons are fast using PCMPEQ + PMOVMSK or PTEST .


"/* This table has been generated by divtab-sh4.cc.  */"

"\ /* Lookup table translating positive divisor to index into table of\n\ normalized inverse.  N.B. the '0' entry is also the last entry of the\n\ previous table, and causes an unaligned access for division by zero.  */\n\ LOCAL(div_table_ix):"

"\ /* 1/64 .. 1/127, normalized.  There is an implicit leading 1 in bit 32.  */\n\ .balign 4\n\ LOCAL(zero_l):"

Main program to convert flat files into built-in initialization code .


"Too many operands in instructions group"

Same but using const index set instead of MI set .


<s> static rtx ft32_function_arg ( cumulative_args_t cum_v , machine_mode mode , const_tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( * cum < 8 ) return gen_rtx_REG ( mode , * cum ) ; else return NULL_RTX ; } </s>

Return the next register to be used to hold a function argument or NULL_RTX if there 's no more space .


<s> MachineInstr * SIInstrInfo :: createPHISourceCopy ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator InsPt , const DebugLoc & DL , Register Src , Register SrcSubReg , Register Dst ) const { if ( InsPt != MBB . end ( ) && ( InsPt -> getOpcode ( ) == AMDGPU :: SI_IF || InsPt -> getOpcode ( ) == AMDGPU :: SI_ELSE || InsPt -> getOpcode ( ) == AMDGPU :: SI_IF_BREAK ) && InsPt -> definesRegister ( Src ) ) { InsPt ++ ; return BuildMI ( MBB , InsPt , InsPt -> getDebugLoc ( ) , get ( ST . isWave32 ( ) ? AMDGPU :: S_MOV_B32_term : AMDGPU :: S_MOV_B64_term ) , Dst ) . addReg ( Src , 0 , SrcSubReg ) . addReg ( AMDGPU :: EXEC , RegState :: Implicit ) ; } return TargetInstrInfo :: createPHISourceCopy ( MBB , InsPt , DL , Src , SrcSubReg , Dst ) ; } </s>

During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destination register in a target specific manner .


<s>
StringRef
getPassName
(
)
const
override
{
return
"TVM Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
void
mmix_trampoline_template
(
FILE
*
stream
)
{
fprintf
(
stream
,
"\tGETA $255,1F\n\t"
)
;
fprintf
(
stream
,
"LDOU %s,$255,0\n\t"
,
reg_names
[
MMIX_STATIC_CHAIN_REGNUM
]
)
;
fprintf
(
stream
,
"LDOU $255,$255,8\n\t"
)
;
fprintf
(
stream
,
"GO $255,$255,0\n"
)
;
fprintf
(
stream
,
"1H\tOCTA 0\n\t"
)
;
fprintf
(
stream
,
"OCTA 0\n"
)
;
}
</s>


<s> const SparcSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static int cr16_register_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t from ATTRIBUTE_UNUSED , reg_class_t to ) { return ( to != GENERAL_REGS ? 8 : 2 ) ; } </s>

Implement ` TARGET_REGISTER_MOVE_COST ' .


<s> const uint32_t * rvexRegisterInfo :: getCallPreservedMask ( CallingConv :: ID ) const { return CSR_O32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void getFunctionConstantRange ( unsigned & Start , unsigned & End ) const { Start = FirstFuncConstantID ; End = FirstInstID ; } </s>

getFunctionConstantRange - Return the range of values that corresponds to function-local constants .


<s> static int min_insn_size ( rtx_insn * insn ) { int l = 0 , len ; if ( ! INSN_P ( insn ) || ! active_insn_p ( insn ) ) return 0 ; if ( GET_CODE ( PATTERN ( insn ) ) == UNSPEC_VOLATILE && XINT ( PATTERN ( insn ) , 1 ) == UNSPECV_ALIGN ) return 0 ; if ( CALL_P ( insn ) && symbolic_reference_mentioned_p ( PATTERN ( insn ) ) && ! SIBLING_CALL_P ( insn ) ) return 5 ; len = get_attr_length ( insn ) ; if ( len <= 1 ) return 1 ; if ( ! JUMP_P ( insn ) ) { enum attr_type type = get_attr_type ( insn ) ; switch ( type ) { case TYPE_MULTI : if ( GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT || asm_noperands ( PATTERN ( insn ) ) >= 0 ) return 0 ; break ; case TYPE_OTHER : case TYPE_FCMP : break ; default : return len ; } l = get_attr_length_address ( insn ) ; if ( l < 4 && symbolic_reference_mentioned_p ( PATTERN ( insn ) ) ) l = 4 ; } if ( l ) return 1 + l ; else return 2 ; } </s>

We do n't have exact information about the insn sizes , but we may assume quite safely that we are informed about all 1 byte insns and memory address sizes . This is enough to eliminate unnecessary padding in 99 % of cases .


<s> bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , BranchProbability Probability ) const override { return NumCycles == 1 ; } </s>

Return true if it 's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion .


<s> bool empty ( ) const { return ! notEmpty ( ) ; } </s>

Determine whether this version information is empty ( e.g. , all version components are zero ) .


<s> SDValue SystemZSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , SDLoc DL , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool IsVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { if ( IsVolatile ) return SDValue ( ) ; if ( ConstantSDNode * CSize = dyn_cast < ConstantSDNode > ( Size ) ) return emitMemMem ( DAG , DL , SystemZISD :: MVC , SystemZISD :: MVC_LOOP , Chain , Dst , Src , CSize -> getZExtValue ( ) ) ; return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .

SystemZ SystemZ SystemZISD::MVC SystemZISD::MVC_LOOP


<s> MachineInstrBuilder SIInstrInfo :: getAddNoCarry ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , unsigned DestReg ) const { if ( ST . hasAddNoCarry ( ) ) return BuildMI ( MBB , I , DL , get ( AMDGPU :: V_ADD_U32_e64 ) , DestReg ) ; MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; unsigned UnusedCarry = MRI . createVirtualRegister ( & AMDGPU :: SReg_64RegClass ) ; MRI . setRegAllocationHint ( UnusedCarry , 0 , AMDGPU :: VCC ) ; return BuildMI ( MBB , I , DL , get ( AMDGPU :: V_ADD_I32_e64 ) , DestReg ) . addReg ( UnusedCarry , RegState :: Define | RegState :: Dead ) ; } </s>

Return a partially built integer add instruction without carry .


<s> static bool visium_pass_by_reference ( cumulative_args_t ca ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , const_tree type , bool named ATTRIBUTE_UNUSED ) { return type && ( AGGREGATE_TYPE_P ( type ) || TREE_CODE ( type ) == VECTOR_TYPE ) ; } </s>

Return true if an argument must be passed by indirect reference .


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { unsigned NumOps = Inst . getNumOperands ( ) ; if ( NumOps == 0 ) return false ; switch ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ NumOps - 1 ] . OperandType ) { case MCOI :: OPERAND_UNKNOWN : case MCOI :: OPERAND_IMMEDIATE : Target = Addr + Inst . getOperand ( NumOps - 1 ) . getImm ( ) ; return true ; default : return false ; } } </s>

Given a branch instruction try to get the address the branch targets .


<s> int class_max_nregs ( enum reg_class class ATTRIBUTE_UNUSED , enum machine_mode mode ) { return ( ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ) ; } </s>

A C expression for the maximum number of consecutive registers of class CLASS needed to hold a value of mode MODE .


<s> static void register_vector_type ( vector_type_index type ) { tree vectype = abi_vector_types [ type ] ; if ( ! vectype ) return ; tree id = get_identifier ( vector_types [ type ] . name ) ; tree decl = build_decl ( input_location , TYPE_DECL , id , vectype ) ; decl = lang_hooks . decls . pushdecl ( decl ) ; if ( decl && TREE_CODE ( decl ) == TYPE_DECL && TREE_TYPE ( decl ) != error_mark_node && TYPE_MAIN_VARIANT ( TREE_TYPE ( decl ) ) == vectype ) vectype = TREE_TYPE ( decl ) ; builtin_types [ type ] . vector = vectype ; builtin_types [ type ] . vector_ptr = build_pointer_type ( vectype ) ; } </s>

Register vector type TYPE under its risv_vector.h name .


"Not expecting bundled instructions here"

Replace a StackProbe inline-stub with the actual probe code inline .


<s> const uint32_t * ARMBaseRegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { if ( STI . isTargetNaCl ( ) ) return CSR_NaCl_RegMask ; if ( CC == CallingConv :: GHC ) return CSR_NoRegs_RegMask ; return ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask ; } </s>


<s> rtx c6x_subword ( rtx op , bool high_p ) { unsigned int byte ; machine_mode mode ; mode = GET_MODE ( op ) ; if ( mode == VOIDmode ) mode = DImode ; if ( TARGET_BIG_ENDIAN ? ! high_p : high_p ) byte = UNITS_PER_WORD ; else byte = 0 ; if ( MEM_P ( op ) ) { rtx addr = XEXP ( op , 0 ) ; if ( GET_CODE ( addr ) == PLUS || REG_P ( addr ) ) return adjust_address ( op , word_mode , byte ) ; gcc_unreachable ( ) ; } return simplify_gen_subreg ( word_mode , op , mode , byte ) ; } </s>

Return one word of double-word value OP . HIGH_P is true to select the high part , false to select the low part . When encountering auto-increment addressing , we make the assumption that the low part is going to be accessed first .


"%<-mindirect-branch=%s%> and %<-mcmodel=large%> are not "

"%<-fcheck-pointer-bounds%> are not compatible"

"%<-mfunction-return=%s%> and %<-mcmodel=large%> are not "

Set the indirect_branch_type field from the function FNDECL .


<s> bool HexagonMCChecker :: check ( bool FullCheck ) { bool chkP = checkPredicates ( ) ; bool chkNV = checkNewValues ( ) ; bool chkR = checkRegisters ( ) ; bool chkRRO = checkRegistersReadOnly ( ) ; checkRegisterCurDefs ( ) ; bool chkS = checkSolo ( ) ; bool chkSh = true ; if ( FullCheck ) chkSh = checkShuffle ( ) ; bool chkSl = true ; if ( FullCheck ) chkSl = checkSlots ( ) ; bool chkAXOK = checkAXOK ( ) ; bool chkCofMax1 = checkCOFMax1 ( ) ; bool chkHWLoop = checkHWLoop ( ) ; bool chkValidTmpDst = FullCheck ? checkValidTmpDst ( ) : true ; bool chkLegalVecRegPair = checkLegalVecRegPair ( ) ; bool ChkHVXAccum = checkHVXAccum ( ) ; bool chk = chkP && chkNV && chkR && chkRRO && chkS && chkSh && chkSl && chkAXOK && chkCofMax1 && chkHWLoop && chkValidTmpDst && chkLegalVecRegPair && ChkHVXAccum ; return chk ; } </s>

Check if the constraints are satisfiable .


<s> unsigned MipsRegisterInfo :: getPICCallReg ( ) { return Mips :: T9 ; } </s>


<s>
void
M680x0AsmBackend
::
relaxInstruction
(
const
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
,
MCInst
&
Res
)
const
{
unsigned
RelaxedOp
=
getRelaxedOpcode
(
Inst
)
;
if
(
RelaxedOp
==
Inst
.
getOpcode
(
)
)
{
SmallString
<
256
>
Tmp
;
raw_svector_ostream
OS
(
Tmp
)
;
Inst
.
dump_pretty
(
OS
)
;
OS
<<
"\n"
;
report_fatal_error
(
"unexpected instruction to relax: "
+
OS
.
str
(
)
)
;
}
Res
=
Inst
;
Res
.
setOpcode
(
RelaxedOp
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


"Code generation for MIPS-I is not implemented"

"Code generation for MIPS-V is not implemented"

"MSA requires a 64-bit FPU register file (FR=1 mode). "

"-mattr=+nooddspreg requires the O32 ABI."

"FPXX is not permitted for the N32/N64 ABI's."

"position-independent code requires '-mabicalls'"

"warning: cannot use small-data accesses for '-mabicalls'"

This constructor initializes the data members to match that of the specified triple .


<s> void sh_init_cumulative_args ( CUMULATIVE_ARGS * pcum , tree fntype , rtx libname ATTRIBUTE_UNUSED , tree fndecl , signed int n_named_args , machine_mode mode ) { pcum -> arg_count [ ( int ) SH_ARG_FLOAT ] = 0 ; pcum -> free_single_fp_reg = 0 ; pcum -> stack_regs = 0 ; pcum -> byref_regs = 0 ; pcum -> byref = 0 ; pcum -> outgoing = ( n_named_args == - 1 ) ? 0 : 1 ; pcum -> renesas_abi = sh_attr_renesas_p ( fntype ) ? 1 : 0 ; if ( fntype ) { pcum -> force_mem = ( ( TARGET_HITACHI || pcum -> renesas_abi ) && aggregate_value_p ( TREE_TYPE ( fntype ) , fndecl ) ) ; pcum -> prototype_p = prototype_p ( fntype ) ; pcum -> arg_count [ ( int ) SH_ARG_INT ] = TARGET_SH5 && aggregate_value_p ( TREE_TYPE ( fntype ) , fndecl ) ; pcum -> call_cookie = CALL_COOKIE_RET_TRAMP ( TARGET_SHCOMPACT && pcum -> arg_count [ ( int ) SH_ARG_INT ] == 0 && ( TYPE_MODE ( TREE_TYPE ( fntype ) ) == BLKmode ? int_size_in_bytes ( TREE_TYPE ( fntype ) ) : GET_MODE_SIZE ( TYPE_MODE ( TREE_TYPE ( fntype ) ) ) ) > 4 && ( BASE_RETURN_VALUE_REG ( TYPE_MODE ( TREE_TYPE ( fntype ) ) ) == FIRST_RET_REG ) ) ; } else { pcum -> arg_count [ ( int ) SH_ARG_INT ] = 0 ; pcum -> prototype_p = FALSE ; if ( mode != VOIDmode ) { pcum -> call_cookie = CALL_COOKIE_RET_TRAMP ( TARGET_SHCOMPACT && GET_MODE_SIZE ( mode ) > 4 && BASE_RETURN_VALUE_REG ( mode ) == FIRST_RET_REG ) ; pcum -> force_mem = ( TARGET_DEFAULT & MASK_HITACHI ) && ( mode == BLKmode || ( GET_MODE_SIZE ( mode ) > 4 && ! ( mode == DFmode && TARGET_FPU_DOUBLE ) ) ) ; } else { pcum -> call_cookie = 0 ; pcum -> force_mem = FALSE ; } } } </s>

Initialize the CUMULATIVE_ARGS structure .


<s>
static
hsa_status_t
get_gpu_agent
(
hsa_agent_t
agent
,
void
*
data
__attribute__
(
(
unused
)
)
)
{
hsa_device_type_t
device_type
;
XHSA
(
hsa_fns
.
hsa_agent_get_info_fn
(
agent
,
HSA_AGENT_INFO_DEVICE
,
&
device_type
)
,
"Get agent type"
)
;
if
(
HSA_DEVICE_TYPE_GPU
==
device_type
)
{
device
=
agent
;
return
HSA_STATUS_INFO_BREAK
;
}
return
HSA_STATUS_SUCCESS
;
}
</s>

Callback of hsa_iterate_agents . Called once for each available device , and returns `` break '' when a suitable one has been found .


<s>
SDValue
BPFTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
DL
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
MF
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
if
(
Ins
.
size
(
)
>=
2
)
{
fail
(
DL
,
DAG
,
"only small returns supported"
)
;
for
(
unsigned
i
=
0
,
e
=
Ins
.
size
(
)
;
i
!=
e
;
++
i
)
InVals
.
push_back
(
DAG
.
getConstant
(
0
,
DL
,
Ins
[
i
]
.
VT
)
)
;
return
DAG
.
getCopyFromReg
(
Chain
,
DL
,
1
,
Ins
[
0
]
.
VT
,
InFlag
)
.
getValue
(
1
)
;
}
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_BPF64
)
;
for
(
auto
&
Val
:
RVLocs
)
{
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
DL
,
Val
.
getLocReg
(
)
,
Val
.
getValVT
(
)
,
InFlag
)
.
getValue
(
1
)
;
InFlag
=
Chain
.
getValue
(
2
)
;
InVals
.
push_back
(
Chain
.
getValue
(
0
)
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> void AArch64PassConfig :: addPreEmitPass ( ) { if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Aggressive && EnableLoadStoreOpt ) addPass ( createAArch64LoadStoreOptimizationPass ( ) ) ; if ( EnableA53Fix835769 ) addPass ( createAArch64A53Fix835769 ( ) ) ; if ( EnableBranchTargets ) addPass ( createAArch64BranchTargetsPass ( ) ) ; if ( BranchRelaxation ) addPass ( & BranchRelaxationPassID ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardLongjmpPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCompressJumpTables ) addPass ( createAArch64CompressJumpTablesPass ( ) ) ; addPass ( createAArch64ExpandHardenedPseudosPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


"Can only insert epilog into returning blocks"

"Expected to see callee-save register restore code"


<s> const TargetRegisterClass * ARM64RegisterInfo :: getCrossCopyRegClass ( const TargetRegisterClass * RC ) const { if ( RC == & ARM64 :: CCRRegClass ) return nullptr ; return RC ; } </s>

getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or from .


<s> const CallLowering * getCallLowering ( ) const override { return CallLoweringInfo . get ( ) ; } </s>


<s> unsigned char X86Subtarget :: classifyGlobalReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large && ! isPositionIndependent ( ) ) return X86II :: MO_NO_FLAG ; if ( GV ) { if ( Optional < ConstantRange > CR = GV -> getAbsoluteSymbolRange ( ) ) { if ( CR -> getUnsignedMax ( ) . ult ( 128 ) ) return X86II :: MO_ABS8 ; else return X86II :: MO_NO_FLAG ; } } if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return classifyLocalReference ( GV ) ; if ( isTargetCOFF ( ) ) { if ( ! GV ) return X86II :: MO_NO_FLAG ; if ( GV -> hasDLLImportStorageClass ( ) ) return X86II :: MO_DLLIMPORT ; return X86II :: MO_COFFSTUB ; } if ( isOSWindows ( ) ) return X86II :: MO_NO_FLAG ; if ( is64Bit ( ) ) { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return isTargetELF ( ) ? X86II :: MO_GOT : X86II :: MO_NO_FLAG ; return X86II :: MO_GOTPCREL ; } if ( isTargetDarwin ( ) ) { if ( ! isPositionIndependent ( ) ) return X86II :: MO_DARWIN_NONLAZY ; return X86II :: MO_DARWIN_NONLAZY_PIC_BASE ; } if ( TM . getRelocationModel ( ) == Reloc :: Static ) return X86II :: MO_NO_FLAG ; return X86II :: MO_GOT ; } </s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s> bool nios2_large_constant_p ( rtx x ) { return ( nios2_symbolic_constant_p ( x ) || nios2_large_unspec_reloc_p ( x ) || ( CONST_INT_P ( x ) && ! SMALL_INT ( INTVAL ( x ) ) ) ) ; } </s>

Return true if X is something that needs to be split into a high/lo_sum pair .


<s> static void xputenv ( const char * string ) { if ( verbose ) fprintf ( stderr , "%s\n" , string ) ; putenv ( CONST_CAST ( char * , string ) ) ; } </s>

Add or change the value of an environment variable , outputting the change to standard error if in verbose mode .


<s> static bool s390_legitimate_address_p ( machine_mode mode , rtx addr , bool strict ) { struct s390_address ad ; if ( TARGET_Z10 && larl_operand ( addr , VOIDmode ) && ( mode == VOIDmode || s390_check_symref_alignment ( addr , GET_MODE_SIZE ( mode ) ) ) ) return true ; if ( ! s390_decompose_address ( addr , & ad ) ) return false ; if ( TARGET_VX && VECTOR_MODE_P ( mode ) && ad . disp != NULL_RTX && CONST_INT_P ( ad . disp ) && ! SHORT_DISP_IN_RANGE ( INTVAL ( ad . disp ) ) ) return false ; if ( strict ) { if ( ad . base && ! REGNO_OK_FOR_BASE_P ( REGNO ( ad . base ) ) ) return false ; if ( ad . indx && ! REGNO_OK_FOR_INDEX_P ( REGNO ( ad . indx ) ) ) return false ; } else { if ( ad . base && ! ( REGNO ( ad . base ) >= FIRST_PSEUDO_REGISTER || REGNO_REG_CLASS ( REGNO ( ad . base ) ) == ADDR_REGS ) ) return false ; if ( ad . indx && ! ( REGNO ( ad . indx ) >= FIRST_PSEUDO_REGISTER || REGNO_REG_CLASS ( REGNO ( ad . indx ) ) == ADDR_REGS ) ) return false ; } return true ; } </s>

Return true if ADDR is a valid memory address . STRICT specifies whether strict register checking applies .


<s> static void mips16_load_branch_target ( rtx dest , rtx src ) { if ( TARGET_ABICALLS && ! TARGET_ABSOLUTE_ABICALLS ) { rtx page , low ; if ( mips_cfun_has_cprestore_slot_p ( ) ) mips_emit_move ( dest , mips_cprestore_slot ( dest , true ) ) ; else mips_emit_move ( dest , pic_offset_table_rtx ) ; page = mips_unspec_address ( src , SYMBOL_GOTOFF_PAGE ) ; low = mips_unspec_address ( src , SYMBOL_GOT_PAGE_OFST ) ; emit_insn ( gen_rtx_SET ( dest , PMODE_INSN ( gen_unspec_got , ( dest , page ) ) ) ) ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_LO_SUM ( Pmode , dest , low ) ) ) ; } else { src = mips_unspec_address ( src , SYMBOL_ABSOLUTE ) ; mips_emit_move ( dest , src ) ; } } </s>

Emit code to load LABEL_REF SRC into MIPS16 register DEST . This is called very late in mips_reorg , but the caller is required to run mips16_lay_out_constants on the result .


<s> static void adjust_subreg_index ( rtx op ) { enum rtx_code code = GET_CODE ( op ) ; if ( code == SUBREG && ( GET_MODE_SIZE ( GET_MODE ( op ) ) < GET_MODE_SIZE ( GET_MODE ( XEXP ( op , 0 ) ) ) ) ) { unsigned int index = SUBREG_BYTE ( op ) ; if ( index < 8 ) index += 8 ; else index -= 8 ; SUBREG_BYTE ( op ) = index ; } const char * fmt = GET_RTX_FORMAT ( code ) ; int i , j ; for ( i = 0 ; i < GET_RTX_LENGTH ( code ) ; ++ i ) if ( fmt [ i ] == 'e' || fmt [ i ] == 'u' ) adjust_subreg_index ( XEXP ( op , i ) ) ; else if ( fmt [ i ] == 'E' ) for ( j = 0 ; j < XVECLEN ( op , i ) ; ++ j ) adjust_subreg_index ( XVECEXP ( op , i , j ) ) ; } </s>

Find all subregs of a vector expression that perform a narrowing , and adjust the subreg index to account for doubleword swapping .


<s> static void rs6000_expand_vector_set_var_p9 ( rtx target , rtx val , rtx idx ) { machine_mode mode = GET_MODE ( target ) ; gcc_assert ( VECTOR_MEM_VSX_P ( mode ) && ! CONST_INT_P ( idx ) ) ; machine_mode inner_mode = GET_MODE ( val ) ; int width = GET_MODE_SIZE ( inner_mode ) ; gcc_assert ( width >= 1 && width <= 8 ) ; int shift = exact_log2 ( width ) ; machine_mode idx_mode = GET_MODE ( idx ) ; machine_mode shift_mode ; rtx ( * gen_ashl ) ( rtx , rtx , rtx ) ; rtx ( * gen_lvsl ) ( rtx , rtx ) ; rtx ( * gen_lvsr ) ( rtx , rtx ) ; if ( TARGET_POWERPC64 ) { shift_mode = DImode ; gen_ashl = gen_ashldi3 ; gen_lvsl = gen_altivec_lvsl_reg_di ; gen_lvsr = gen_altivec_lvsr_reg_di ; } else { shift_mode = SImode ; gen_ashl = gen_ashlsi3 ; gen_lvsl = gen_altivec_lvsl_reg_si ; gen_lvsr = gen_altivec_lvsr_reg_si ; } rtx tmp = gen_reg_rtx ( shift_mode ) ; idx = convert_modes ( shift_mode , idx_mode , idx , 1 ) ; emit_insn ( gen_ashl ( tmp , idx , GEN_INT ( shift ) ) ) ; rtx pcvr = gen_reg_rtx ( V16QImode ) ; emit_insn ( gen_lvsr ( pcvr , tmp ) ) ; rtx pcvl = gen_reg_rtx ( V16QImode ) ; emit_insn ( gen_lvsl ( pcvl , tmp ) ) ; rtx sub_target = simplify_gen_subreg ( V16QImode , target , mode , 0 ) ; rtx permr = gen_altivec_vperm_v8hiv16qi ( sub_target , sub_target , sub_target , pcvr ) ; emit_insn ( permr ) ; rs6000_expand_vector_set ( target , val , const0_rtx ) ; rtx perml = gen_altivec_vperm_v8hiv16qi ( sub_target , sub_target , sub_target , pcvl ) ; emit_insn ( perml ) ; } </s>

Insert VAL into IDX of TARGET , VAL size is same of the vector element , IDX is variable and also counts by vector element size for p9 and above .


<s> CCAssignFn * AMDGPUTargetLowering :: CCAssignFnForReturn ( CallingConv :: ID CC , bool IsVarArg ) { return AMDGPUCallLowering :: CCAssignFnForReturn ( CC , IsVarArg ) ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> Value * GCNTTIImpl :: rewriteIntrinsicWithAddressSpace ( IntrinsicInst * II , Value * OldV , Value * NewV ) const { auto IntrID = II -> getIntrinsicID ( ) ; switch ( IntrID ) { case Intrinsic :: amdgcn_atomic_inc : case Intrinsic :: amdgcn_atomic_dec : case Intrinsic :: amdgcn_ds_fadd : case Intrinsic :: amdgcn_ds_fmin : case Intrinsic :: amdgcn_ds_fmax : { const ConstantInt * IsVolatile = cast < ConstantInt > ( II -> getArgOperand ( 4 ) ) ; if ( ! IsVolatile -> isZero ( ) ) return nullptr ; Module * M = II -> getParent ( ) -> getParent ( ) -> getParent ( ) ; Type * DestTy = II -> getType ( ) ; Type * SrcTy = NewV -> getType ( ) ; Function * NewDecl = Intrinsic :: getDeclaration ( M , II -> getIntrinsicID ( ) , { DestTy , SrcTy } ) ; II -> setArgOperand ( 0 , NewV ) ; II -> setCalledFunction ( NewDecl ) ; return II ; } case Intrinsic :: amdgcn_is_shared : case Intrinsic :: amdgcn_is_private : { unsigned TrueAS = IntrID == Intrinsic :: amdgcn_is_shared ? AMDGPUAS :: LOCAL_ADDRESS : AMDGPUAS :: PRIVATE_ADDRESS ; unsigned NewAS = NewV -> getType ( ) -> getPointerAddressSpace ( ) ; LLVMContext & Ctx = NewV -> getType ( ) -> getContext ( ) ; ConstantInt * NewVal = ( TrueAS == NewAS ) ? ConstantInt :: getTrue ( Ctx ) : ConstantInt :: getFalse ( Ctx ) ; return NewVal ; } case Intrinsic :: ptrmask : { unsigned OldAS = OldV -> getType ( ) -> getPointerAddressSpace ( ) ; unsigned NewAS = NewV -> getType ( ) -> getPointerAddressSpace ( ) ; Value * MaskOp = II -> getArgOperand ( 1 ) ; Type * MaskTy = MaskOp -> getType ( ) ; bool DoTruncate = false ; const GCNTargetMachine & TM = static_cast < const GCNTargetMachine & > ( getTLI ( ) -> getTargetMachine ( ) ) ; if ( ! TM . isNoopAddrSpaceCast ( OldAS , NewAS ) ) { if ( DL . getPointerSizeInBits ( OldAS ) != 64 || DL . getPointerSizeInBits ( NewAS ) != 32 ) return nullptr ; KnownBits Known = computeKnownBits ( MaskOp , DL , 0 , nullptr , II ) ; if ( Known . countMinLeadingOnes ( ) < 32 ) return nullptr ; DoTruncate = true ; } IRBuilder < > B ( II ) ; if ( DoTruncate ) { MaskTy = B . getInt32Ty ( ) ; MaskOp = B . CreateTrunc ( MaskOp , MaskTy ) ; } return B . CreateIntrinsic ( Intrinsic :: ptrmask , { NewV -> getType ( ) , MaskTy } , { NewV , MaskOp } ) ; } default : return nullptr ; } } </s>

Rewrite intrinsic call II such that OldV will be replaced with NewV , which has a different address space .


"  group = %s, path = %d, byte_len = %d\n"

"  num_imm = %d, num_imm_32 = %d, num_imm_64 = %d, imm_size = %d\n"

Print INSN dispatch information to FILE .


<s>
void
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
override
{
Value
=
adjustFixupValue
(
Fixup
.
getKind
(
)
,
Value
)
;
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
Endian
==
support
::
little
i
:
(
NumBytes
1
)
i
;
Data
[
Offset
+
Idx
]
|=
static_cast
<
uint8_t
>
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static rtx_insn * pdp11_md_asm_adjust ( vec < rtx > & , vec < rtx > & , vec < machine_mode > & , vec < const char * > & , vec < rtx > & clobbers , HARD_REG_SET & clobbered_regs , location_t ) { clobbers . safe_push ( gen_rtx_REG ( CCmode , CC_REGNUM ) ) ; SET_HARD_REG_BIT ( clobbered_regs , CC_REGNUM ) ; if ( TARGET_FPU ) { clobbers . safe_push ( gen_rtx_REG ( CCmode , FCC_REGNUM ) ) ; SET_HARD_REG_BIT ( clobbered_regs , FCC_REGNUM ) ; } return NULL ; } </s>

Prepend to CLOBBERS hard registers that are automatically clobbered for an asm We do this for CC_REGNUM and FCC_REGNUM ( on FPU target ) to maintain source compatibility with the original cc0-based compiler .


<s> void SIScheduleBlockScheduler :: addLiveRegs ( std :: set < unsigned > & Regs ) { for ( unsigned Reg : Regs ) { if ( ! Register :: isVirtualRegister ( Reg ) ) continue ; ( void ) LiveRegs . insert ( Reg ) ; } } </s>

Force liveness of virtual registers or physical register units .


<s>
SUnit
*
GCNMaxOccupancySchedStrategy
::
pickNode
(
bool
&
IsTopNode
)
{
if
(
DAG
->
top
(
)
==
DAG
->
bottom
(
)
)
{
assert
(
Top
.
Available
.
empty
(
)
&&
Top
.
Pending
.
empty
(
)
&&
Bot
.
Available
.
empty
(
)
&&
Bot
.
Pending
.
empty
(
)
&&
"ReadyQ garbage"
)
;
return
nullptr
;
}
SUnit
*
SU
;
do
{
if
(
RegionPolicy
.
OnlyTopDown
)
{
SU
=
Top
.
pickOnlyChoice
(
)
;
if
(
!
SU
)
{
CandPolicy
NoPolicy
;
TopCand
.
reset
(
NoPolicy
)
;
pickNodeFromQueue
(
Top
,
NoPolicy
,
DAG
->
getTopRPTracker
(
)
,
TopCand
)
;
assert
(
TopCand
.
Reason
!=
NoCand
&&
"failed to find a candidate"
)
;
SU
=
TopCand
.
SU
;
}
IsTopNode
=
true
;
}
else
if
(
RegionPolicy
.
OnlyBottomUp
)
{
SU
=
Bot
.
pickOnlyChoice
(
)
;
if
(
!
SU
)
{
CandPolicy
NoPolicy
;
BotCand
.
reset
(
NoPolicy
)
;
pickNodeFromQueue
(
Bot
,
NoPolicy
,
DAG
->
getBotRPTracker
(
)
,
BotCand
)
;
assert
(
BotCand
.
Reason
!=
NoCand
&&
"failed to find a candidate"
)
;
SU
=
BotCand
.
SU
;
}
IsTopNode
=
false
;
}
else
{
SU
=
pickNodeBidirectional
(
IsTopNode
)
;
}
}
while
(
SU
->
isScheduled
)
;
if
(
SU
->
isTopReady
(
)
)
Top
.
removeReady
(
SU
)
;
if
(
SU
->
isBottomReady
(
)
)
Bot
.
removeReady
(
SU
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Scheduling SU("
<<
SU
->
NodeNum
<<
") "
<<
*
SU
->
getInstr
(
)
)
;
return
SU
;
}
</s>

Pick the next node to schedule , or return NULL .

AMDGPU
"ReadyQ garbage"
"failed to find a candidate"
"failed to find a candidate"
"Scheduling SU("
") "


<s> RISCVConstantPoolValue * RISCVConstantPoolValue :: Create ( const GlobalValue * GV , RISCVCP :: RISCVCPModifier Modifier ) { return new RISCVConstantPoolValue ( GV , Modifier ) ; } </s>

Construct a unary instruction , given the opcode and an operand .

RISCV RISCV RISCV RISCVCP::RISCVCPModifier RISCV


<s>
bool
WinEHStatePass
::
runOnFunction
(
Function
&
F
)
{
StringRef
WinEHParentName
=
F
.
getFnAttribute
(
"wineh-parent"
)
.
getValueAsString
(
)
;
if
(
WinEHParentName
!=
F
.
getName
(
)
&&
!
WinEHParentName
.
empty
(
)
)
return
false
;
if
(
!
F
.
hasPersonalityFn
(
)
)
return
false
;
PersonalityFn
=
dyn_cast
<
Function
>
(
F
.
getPersonalityFn
(
)
->
stripPointerCasts
(
)
)
;
if
(
!
PersonalityFn
)
return
false
;
Personality
=
classifyEHPersonality
(
PersonalityFn
)
;
if
(
!
isMSVCEHPersonality
(
Personality
)
)
return
false
;
F
.
addFnAttr
(
"no-frame-pointer-elim"
,
"true"
)
;
emitExceptionRegistrationRecord
(
&
F
)
;
auto
*
MMI
=
getAnalysisIfAvailable
<
MachineModuleInfo
>
(
)
;
std
::
unique_ptr
<
WinEHFuncInfo
>
FuncInfoPtr
;
if
(
!
MMI
)
FuncInfoPtr
.
reset
(
new
WinEHFuncInfo
(
)
)
;
WinEHFuncInfo
&
FuncInfo
=
*
(
MMI
&
MMI
->
getWinEHFuncInfo
(
&
F
)
:
FuncInfoPtr
.
get
(
)
)
;
switch
(
Personality
)
{
default
:
llvm_unreachable
(
"unexpected personality function"
)
;
case
EHPersonality
::
MSVC_CXX
:
addCXXStateStores
(
F
,
FuncInfo
)
;
break
;
case
EHPersonality
::
MSVC_X86SEH
:
addSEHStateStores
(
F
,
FuncInfo
)
;
break
;
}
PersonalityFn
=
nullptr
;
Personality
=
EHPersonality
::
Unknown
;
return
true
;
}
</s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .

X86
"wineh-parent"
"no-frame-pointer-elim"
"true"
"unexpected personality function"
X86


Probe a range of stack addresses from REG1 to REG3 inclusive . These are addresses , not offsets . REG2 contains the backchain that must be stored into * sp at each allocation . This is subtly different than the Ada probing above in that it tries hard to prevent attacks that jump the stack guard . Thus , it is never allowed to allocate more than PROBE_INTERVAL bytes of stack space without a suitable probe .


<s> bool shouldBuildRelLookupTables ( ) const { return false ; } </s>

Return true if lookup tables should be turned into relative lookup tables .


<s> static enum machine_mode hfa_element_mode ( tree type , bool nested ) { enum machine_mode element_mode = VOIDmode ; enum machine_mode mode ; enum tree_code code = TREE_CODE ( type ) ; int know_element_mode = 0 ; tree t ; if ( ! nested && ( ! TYPE_SIZE ( type ) || integer_zerop ( TYPE_SIZE ( type ) ) ) ) return VOIDmode ; switch ( code ) { case VOID_TYPE : case INTEGER_TYPE : case ENUMERAL_TYPE : case BOOLEAN_TYPE : case CHAR_TYPE : case POINTER_TYPE : case OFFSET_TYPE : case REFERENCE_TYPE : case METHOD_TYPE : case LANG_TYPE : case FUNCTION_TYPE : return VOIDmode ; case COMPLEX_TYPE : if ( GET_MODE_CLASS ( TYPE_MODE ( type ) ) == MODE_COMPLEX_FLOAT && TYPE_MODE ( type ) != TCmode ) return GET_MODE_INNER ( TYPE_MODE ( type ) ) ; else return VOIDmode ; case REAL_TYPE : if ( nested && TYPE_MODE ( type ) != TFmode ) return TYPE_MODE ( type ) ; else return VOIDmode ; case ARRAY_TYPE : return hfa_element_mode ( TREE_TYPE ( type ) , 1 ) ; case RECORD_TYPE : case UNION_TYPE : case QUAL_UNION_TYPE : for ( t = TYPE_FIELDS ( type ) ; t ; t = TREE_CHAIN ( t ) ) { if ( TREE_CODE ( t ) != FIELD_DECL ) continue ; mode = hfa_element_mode ( TREE_TYPE ( t ) , 1 ) ; if ( know_element_mode ) { if ( mode != element_mode ) return VOIDmode ; } else if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT ) return VOIDmode ; else { know_element_mode = 1 ; element_mode = mode ; } } return element_mode ; default : return VOIDmode ; } return VOIDmode ; } </s>

Check whether TYPE is a homogeneous floating point aggregate . If it is , return the mode of the floating point type that appears in all leafs . If it is not , return VOIDmode . An aggregate is a homogeneous floating point aggregate is if all fields/elements in it have the same floating point type ( e.g , SFmode ) . 128-bit quad-precision floats are excluded .


"passing %wd to argument %d of %qE, which expects"

Report that LOCATION has a call to FNDECL in which argument ARGNO has the value ACTUAL , whereas the function requires a valid value of enum type ENUMTYPE . ARGNO counts from zero .


Add value VAL sized SIZE to the data we 're emitting , and keep writing out chunks as they fill up .


<s> bool isReg ( ) const override { return Kind == k_Register ; } </s>


<s> static bool ix86_vector_mode_supported_p ( machine_mode mode ) { if ( ! TARGET_64BIT && GET_MODE_INNER ( mode ) == TImode ) return false ; if ( TARGET_SSE && VALID_SSE_REG_MODE ( mode ) ) return true ; if ( TARGET_SSE2 && VALID_SSE2_REG_MODE ( mode ) ) return true ; if ( TARGET_AVX && VALID_AVX256_REG_MODE ( mode ) ) return true ; if ( TARGET_AVX512F && VALID_AVX512F_REG_MODE ( mode ) ) return true ; if ( ( TARGET_MMX || TARGET_MMX_WITH_SSE ) && VALID_MMX_REG_MODE ( mode ) ) return true ; if ( ( TARGET_3DNOW || TARGET_MMX_WITH_SSE ) && VALID_MMX_REG_MODE_3DNOW ( mode ) ) return true ; if ( mode == V2QImode ) return true ; return false ; } </s>

Implements target hook vector_mode_supported_p .


<s>
bool
ARMCallLowering
::
lowerReturn
(
MachineIRBuilder
&
MIRBuilder
,
const
Value
*
Val
,
unsigned
VReg
)
const
{
assert
(
!
Val
==
!
VReg
&&
"Return value without a vreg"
)
;
auto
const
&
ST
=
MIRBuilder
.
getMF
(
)
.
getSubtarget
<
ARMSubtarget
>
(
)
;
unsigned
Opcode
=
ST
.
getReturnOpcode
(
)
;
auto
Ret
=
MIRBuilder
.
buildInstrNoInsert
(
Opcode
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
if
(
!
lowerReturnVal
(
MIRBuilder
,
Val
,
VReg
,
Ret
)
)
return
false
;
MIRBuilder
.
insertInstr
(
Ret
)
;
return
true
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .

ARM
ARM
"Return value without a vreg"
ARM
ARMCC::AL


<s> enum non_prefixed_form reg_to_non_prefixed ( rtx reg , machine_mode mode ) { if ( ! REG_P ( reg ) && ! SUBREG_P ( reg ) ) return NON_PREFIXED_DEFAULT ; unsigned int r = reg_or_subregno ( reg ) ; if ( ! HARD_REGISTER_NUM_P ( r ) ) return NON_PREFIXED_DEFAULT ; unsigned size = GET_MODE_SIZE ( mode ) ; if ( FP_REGNO_P ( r ) ) { if ( mode == SFmode || size == 8 || FLOAT128_2REG_P ( mode ) ) return NON_PREFIXED_D ; else if ( size < 8 ) return NON_PREFIXED_X ; else if ( TARGET_VSX && size >= 16 && ( VECTOR_MODE_P ( mode ) || VECTOR_ALIGNMENT_P ( mode ) || mode == TImode || mode == CTImode ) ) return ( TARGET_P9_VECTOR ) ? NON_PREFIXED_DQ : NON_PREFIXED_X ; else return NON_PREFIXED_DEFAULT ; } else if ( ALTIVEC_REGNO_P ( r ) ) { if ( ! TARGET_P9_VECTOR ) return NON_PREFIXED_X ; if ( mode == SFmode || size == 8 || FLOAT128_2REG_P ( mode ) ) return NON_PREFIXED_DS ; else if ( size < 8 ) return NON_PREFIXED_X ; else if ( TARGET_VSX && size >= 16 && ( VECTOR_MODE_P ( mode ) || VECTOR_ALIGNMENT_P ( mode ) || mode == TImode || mode == CTImode ) ) return NON_PREFIXED_DQ ; else return NON_PREFIXED_DEFAULT ; } else if ( TARGET_POWERPC64 && size >= 8 ) return NON_PREFIXED_DS ; return NON_PREFIXED_D ; } </s>

Helper function to take a REG and a MODE and turn it into the non-prefixed instruction format ( D/DS/DQ ) used for offset memory .


<s> static bool rs6000_output_addr_const_extra ( FILE * file , rtx x ) { if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , 1 ) ) { case UNSPEC_TOCREL : gcc_checking_assert ( GET_CODE ( XVECEXP ( x , 0 , 0 ) ) == SYMBOL_REF && REG_P ( XVECEXP ( x , 0 , 1 ) ) && REGNO ( XVECEXP ( x , 0 , 1 ) ) == TOC_REGISTER ) ; output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; if ( x == tocrel_base && tocrel_offset != const0_rtx ) { if ( INTVAL ( tocrel_offset ) >= 0 ) fprintf ( file , "+" ) ; output_addr_const ( file , CONST_CAST_RTX ( tocrel_offset ) ) ; } if ( ! TARGET_AIX || ( TARGET_ELF && TARGET_MINIMAL_TOC ) ) { putc ( '-' , file ) ; assemble_name ( file , toc_label_name ) ; } else if ( TARGET_ELF ) fputs ( "@toc" , file ) ; return true ; case UNSPEC_MACHOPIC_OFFSET : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; putc ( '-' , file ) ; machopic_output_function_base_name ( file ) ; return true ; } return false ; } </s>


<s> bool MipsTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , getTargetMachine ( ) , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_Mips ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> int ix86_issue_rate ( void ) { switch ( ix86_tune ) { case PROCESSOR_PENTIUM : case PROCESSOR_LAKEMONT : case PROCESSOR_BONNELL : case PROCESSOR_SILVERMONT : case PROCESSOR_KNL : case PROCESSOR_KNM : case PROCESSOR_INTEL : case PROCESSOR_K6 : case PROCESSOR_BTVER2 : case PROCESSOR_PENTIUM4 : case PROCESSOR_NOCONA : return 2 ; case PROCESSOR_PENTIUMPRO : case PROCESSOR_ATHLON : case PROCESSOR_K8 : case PROCESSOR_AMDFAM10 : case PROCESSOR_BTVER1 : return 3 ; case PROCESSOR_BDVER1 : case PROCESSOR_BDVER2 : case PROCESSOR_BDVER3 : case PROCESSOR_BDVER4 : case PROCESSOR_ZNVER1 : case PROCESSOR_ZNVER2 : case PROCESSOR_ZNVER3 : case PROCESSOR_CORE2 : case PROCESSOR_NEHALEM : case PROCESSOR_SANDYBRIDGE : case PROCESSOR_HASWELL : case PROCESSOR_TREMONT : case PROCESSOR_ALDERLAKE : case PROCESSOR_GENERIC : return 4 ; default : return 1 ; } } </s>

Return the maximum number of instructions a cpu can issue .


<s> void F2003fInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << getRegisterName ( RegNo ) ; } </s>


"insertBranch must not be told to insert a fallthrough"

"ARC branch conditions have two components!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> TargetLowering :: ConstraintType MSP430TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return C_RegisterClass ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> const PPCInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"TPC Software Loop Pipelining"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static void replace_auli_pcrel ( rtx_insn * insn ) { rtx pattern = PATTERN ( insn ) ; rtx set_src ; rtx high ; rtx unspec ; rtx opnds [ 4 ] ; bool first_insn_p ; gcc_assert ( GET_CODE ( pattern ) == SET ) ; opnds [ 0 ] = SET_DEST ( pattern ) ; set_src = SET_SRC ( pattern ) ; gcc_assert ( GET_CODE ( set_src ) == PLUS ) ; opnds [ 1 ] = XEXP ( set_src , 0 ) ; high = XEXP ( set_src , 1 ) ; gcc_assert ( GET_CODE ( high ) == HIGH ) ; gcc_assert ( GET_CODE ( XEXP ( high , 0 ) ) == CONST ) ; unspec = XEXP ( XEXP ( high , 0 ) , 0 ) ; gcc_assert ( GET_CODE ( unspec ) == UNSPEC ) ; gcc_assert ( XINT ( unspec , 1 ) == UNSPEC_PCREL_SYM ) ; opnds [ 2 ] = XVECEXP ( unspec , 0 , 0 ) ; opnds [ 3 ] = XVECEXP ( unspec , 0 , 1 ) ; if ( GET_CODE ( opnds [ 2 ] ) != SYMBOL_REF ) return ; first_insn_p = ( opnds [ 1 ] == tilepro_text_label_rtx ( ) ) ; replace_pc_relative_symbol_ref ( insn , opnds , first_insn_p ) ; } </s>

Helper function for tilepro_fixup_pcrel_references .


<s> static int arm_compute_static_chain_stack_bytes ( void ) { if ( TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM && IS_NESTED ( arm_current_func_type ( ) ) && arm_r3_live_at_start_p ( ) && crtl -> args . pretend_args_size == 0 ) return 4 ; return 0 ; } </s>

Compute the number of bytes used to store the static chain register on the stack , above the stack frame . We need to know this accurately to get the alignment of the rest of the stack frame correct .


<s> static void nios2_asm_output_mi_thunk ( FILE * file , tree thunk_fndecl ATTRIBUTE_UNUSED , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { rtx this_rtx , funexp ; rtx_insn * insn ; reload_completed = 1 ; if ( flag_pic ) nios2_load_pic_register ( ) ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , FIRST_ARG_REGNO + 1 ) ; else this_rtx = gen_rtx_REG ( Pmode , FIRST_ARG_REGNO ) ; nios2_emit_add_constant ( this_rtx , delta ) ; if ( vcall_offset ) { rtx tmp ; tmp = gen_rtx_REG ( Pmode , 2 ) ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , this_rtx ) ) ; nios2_emit_add_constant ( tmp , vcall_offset ) ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , tmp ) ) ; emit_insn ( gen_add2_insn ( this_rtx , tmp ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = 1 ; } funexp = XEXP ( DECL_RTL ( function ) , 0 ) ; nios2_adjust_call_address ( & funexp , gen_rtx_REG ( Pmode , 2 ) ) ; insn = emit_call_insn ( gen_sibcall_internal ( funexp , const0_rtx ) ) ; SIBLING_CALL_P ( insn ) = 1 ; insn = get_insns ( ) ; shorten_branches ( insn ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; reload_completed = 0 ; } </s>


<s> bool NVPTXTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , unsigned Intrinsic ) const { switch ( Intrinsic ) { default : return false ; case Intrinsic :: nvvm_atomic_load_add_f32 : Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: f32 ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . vol = 0 ; Info . readMem = true ; Info . writeMem = true ; Info . align = 0 ; return true ; case Intrinsic :: nvvm_atomic_load_inc_32 : case Intrinsic :: nvvm_atomic_load_dec_32 : Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: i32 ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . vol = 0 ; Info . readMem = true ; Info . writeMem = true ; Info . align = 0 ; return true ; case Intrinsic :: nvvm_ldu_global_i : case Intrinsic :: nvvm_ldu_global_f : case Intrinsic :: nvvm_ldu_global_p : Info . opc = ISD :: INTRINSIC_W_CHAIN ; if ( Intrinsic == Intrinsic :: nvvm_ldu_global_i ) Info . memVT = getValueType ( I . getType ( ) ) ; else if ( Intrinsic == Intrinsic :: nvvm_ldu_global_p ) Info . memVT = getValueType ( I . getType ( ) ) ; else Info . memVT = MVT :: f32 ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . vol = 0 ; Info . readMem = true ; Info . writeMem = false ; Info . align = 0 ; return true ; } return false ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> void AGCMCELFStreamer :: EmitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , bool ) { switch ( Inst . getOpcode ( ) ) { default : break ; case AGC :: DirectiveBLOCK : { int64_t ImmOp = Inst . getOperand ( 0 ) . getImm ( ) ; StringRef SectionName = ImmOp == 0 ? "BLOCK0" : ( "BANK" + itostr ( ImmOp ) ) ; MCSection * Section = ( ( MCSection * ) getContext ( ) . getELFSection ( SectionName , ELF :: SHT_PROGBITS , ELF :: SHF_EXECINSTR | ELF :: SHF_ALLOC ) ) ; SwitchSection ( Section , nullptr ) ; return ; } case AGC :: DirectiveBANK : { StringRef SectionName = "BANK" + itostr ( Inst . getOperand ( 0 ) . getImm ( ) ) ; MCSection * Section = ( ( MCSection * ) getContext ( ) . getELFSection ( SectionName , ELF :: SHT_PROGBITS , ELF :: SHF_EXECINSTR | ELF :: SHF_ALLOC ) ) ; SwitchSection ( Section , nullptr ) ; return ; } case AGC :: DirectiveBNKSUM : { return ; } case AGC :: DirectiveSETLOC : { StringRef SectionName = "ADDR" + itostr ( Inst . getOperand ( 0 ) . getImm ( ) ) ; MCSection * Section = ( ( MCSection * ) getContext ( ) . getELFSection ( SectionName , ELF :: SHT_PROGBITS , ELF :: SHF_EXECINSTR | ELF :: SHF_ALLOC ) ) ; SwitchSection ( Section , nullptr ) ; return ; } } MCELFStreamer :: EmitInstruction ( Inst , STI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool h8300_operands_match_p ( rtx * operands ) { if ( register_operand ( operands [ 0 ] , VOIDmode ) && register_operand ( operands [ 1 ] , VOIDmode ) ) return true ; if ( h8sx_mergeable_memrefs_p ( operands [ 0 ] , operands [ 1 ] ) ) return true ; return false ; } </s>

Return true if OPERANDS [ 1 ] can be mapped to the same assembly operand as OPERANDS [ 0 ] .


<s>
SDValue
XtensaTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Custom lowering: "
)
;
LLVM_DEBUG
(
Op
.
dump
(
)
)
;
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
return
SDValue
(
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

Xtensa
Xtensa
"Custom lowering: "
ISD::BR_CC
"unimplemented operand"


<s> static rtx find_addr_reg ( rtx addr ) { while ( GET_CODE ( addr ) == PLUS ) { if ( GET_CODE ( XEXP ( addr , 0 ) ) == REG ) addr = XEXP ( addr , 0 ) ; else if ( GET_CODE ( XEXP ( addr , 1 ) ) == REG ) addr = XEXP ( addr , 1 ) ; else if ( CONSTANT_P ( XEXP ( addr , 0 ) ) ) addr = XEXP ( addr , 1 ) ; else if ( CONSTANT_P ( XEXP ( addr , 1 ) ) ) addr = XEXP ( addr , 0 ) ; else gcc_unreachable ( ) ; } gcc_assert ( GET_CODE ( addr ) == REG ) ; return addr ; } </s>

Return a REG that occurs in ADDR with coefficient 1 . ADDR can be effectively incremented by incrementing REG . r0 is special and we must not select it as an address register by this routine since our caller will try to increment the returned register via an `` la '' instruction .


<s> static bool rs6000_discover_homogeneous_aggregate ( machine_mode mode , const_tree type , machine_mode * elt_mode , int * n_elts ) { if ( TARGET_HARD_FLOAT && DEFAULT_ABI == ABI_ELFv2 && type && AGGREGATE_TYPE_P ( type ) ) { machine_mode field_mode = VOIDmode ; int field_count = rs6000_aggregate_candidate ( type , & field_mode ) ; if ( field_count > 0 ) { int reg_size = ALTIVEC_OR_VSX_VECTOR_MODE ( field_mode ) ? 16 : 8 ; int field_size = ROUND_UP ( GET_MODE_SIZE ( field_mode ) , reg_size ) ; if ( field_count * field_size <= AGGR_ARG_NUM_REG * reg_size ) { if ( elt_mode ) * elt_mode = field_mode ; if ( n_elts ) * n_elts = field_count ; return true ; } } } if ( elt_mode ) * elt_mode = mode ; if ( n_elts ) * n_elts = 1 ; return false ; } </s>

If an argument , whose type is described by TYPE and MODE , is a homogeneous float or vector aggregate that shall be passed in FP/vector registers according to the ELFv2 ABI , return the homogeneous element mode in * ELT_MODE and the number of elements in * N_ELTS , and return TRUE . Otherwise , set * ELT_MODE to MODE and * N_ELTS to 1 , and return FALSE .


<s> int direct_return ( void ) { if ( ! reload_completed ) return FALSE ; if ( M32R_INTERRUPT_P ( m32r_compute_function_type ( current_function_decl ) ) ) return FALSE ; if ( ! current_frame_info . initialized ) m32r_compute_frame_size ( get_frame_size ( ) ) ; return current_frame_info . total_size == 0 ; } </s>

Return non-zero if this function is known to have a null epilogue .


<s> rtx mep_mulr_source ( rtx_insn * insn , rtx dest , rtx src1 , rtx src2 ) { if ( rtx_equal_p ( dest , src1 ) ) return src2 ; else if ( rtx_equal_p ( dest , src2 ) ) return src1 ; else { if ( insn == 0 ) emit_insn ( gen_movsi ( copy_rtx ( dest ) , src1 ) ) ; else emit_insn_before ( gen_movsi ( copy_rtx ( dest ) , src1 ) , insn ) ; return src2 ; } } </s>

Given three integer registers DEST , SRC1 and SRC2 , return an rtx X such that `` mulr DEST , X '' will calculate DEST = SRC1 * SRC2 . If a move is needed , emit it before INSN if INSN is nonnull , otherwise emit it at the end of the insn stream .


<s> bool X86PassConfig :: addPreEmitPass ( ) { bool ShouldPrint = false ; if ( getOptLevel ( ) != CodeGenOpt :: None && getX86Subtarget ( ) . hasSSE2 ( ) ) { addPass ( createExecutionDependencyFixPass ( & X86 :: VR128RegClass ) ) ; ShouldPrint = true ; } if ( UseVZeroUpper ) { addPass ( createX86IssueVZeroUpperPass ( ) ) ; ShouldPrint = true ; } if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86PadShortFunctions ( ) ) ; addPass ( createX86FixupLEAs ( ) ) ; ShouldPrint = true ; } return ShouldPrint ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static void frv_io_check_address ( rtx x , const_rtx pat ATTRIBUTE_UNUSED , void * data ) { rtx * other = ( rtx * ) data ; if ( REG_P ( x ) && * other != 0 && reg_overlap_mentioned_p ( x , * other ) ) * other = 0 ; } </s>

A note_stores callback for which DATA points to an rtx . Nullify * DATA if X is a register and * DATA depends on X .


<s> bool HexagonFrameLowering :: hasFP ( const MachineFunction & MF ) const { if ( MF . getFunction ( ) . hasFnAttribute ( Attribute :: Naked ) ) return false ; auto & MFI = MF . getFrameInfo ( ) ; auto & HRI = * MF . getSubtarget < HexagonSubtarget > ( ) . getRegisterInfo ( ) ; bool HasExtraAlign = HRI . needsStackRealignment ( MF ) ; bool HasAlloca = MFI . hasVarSizedObjects ( ) ; if ( MF . getTarget ( ) . getOptLevel ( ) == CodeGenOpt :: None ) return true ; if ( HasAlloca || HasExtraAlign ) return true ; if ( MFI . getStackSize ( ) > 0 ) { const TargetMachine & TM = MF . getTarget ( ) ; if ( TM . Options . DisableFramePointerElim ( MF ) || ! EliminateFramePointer ) return true ; if ( EnableStackOVFSanitizer ) return true ; } const auto & HMFI = * MF . getInfo < HexagonMachineFunctionInfo > ( ) ; if ( MFI . hasCalls ( ) || HMFI . hasClobberLR ( ) ) return true ; return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static rtx m68k_function_arg ( cumulative_args_t , const function_arg_info & ) { return NULL_RTX ; } </s>

On the m68k all args are always pushed .


<s> void J2RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; int FrameIdx = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; auto isCalleeSaved = isCalleeSavedIndex ( FrameIdx , MF . getFrameInfo ( ) ) ; unsigned BaseReg = isCalleeSaved ? J2 :: R15 : getFrameRegister ( MF ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BaseReg , false ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool aarch64_return_address_signing_enabled ( void ) { gcc_assert ( cfun -> machine -> frame . laid_out ) ; return ( aarch64_ra_sign_scope == AARCH64_FUNCTION_ALL || ( aarch64_ra_sign_scope == AARCH64_FUNCTION_NON_LEAF && known_ge ( cfun -> machine -> frame . reg_offset [ LR_REGNUM ] , 0 ) ) ) ; } </s>

Return TRUE if return address signing should be enabled for the current function , otherwise return FALSE .


<s> bool ARMLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { const TargetMachine & TM = Fn . getTarget ( ) ; TL = TM . getTargetLowering ( ) ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; TII = TM . getInstrInfo ( ) ; TRI = TM . getRegisterInfo ( ) ; STI = & TM . getSubtarget < ARMSubtarget > ( ) ; RS = new RegScavenger ( ) ; isThumb2 = AFI -> isThumb2Function ( ) ; isThumb1 = AFI -> isThumbFunction ( ) && ! isThumb2 ; if ( isThumb1 ) { delete RS ; return false ; } bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= LoadStoreMultipleOpti ( MBB ) ; if ( TM . getSubtarget < ARMSubtarget > ( ) . hasV5TOps ( ) ) Modified |= MergeReturnIntoLDM ( MBB ) ; } delete RS ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const PPCFrameLowering * TFI = getFrameLowering ( MF ) ; markSuperRegs ( Reserved , PPC :: ZERO ) ; markSuperRegs ( Reserved , PPC :: FP ) ; markSuperRegs ( Reserved , PPC :: BP ) ; markSuperRegs ( Reserved , PPC :: CTR ) ; markSuperRegs ( Reserved , PPC :: CTR8 ) ; markSuperRegs ( Reserved , PPC :: R1 ) ; markSuperRegs ( Reserved , PPC :: LR ) ; markSuperRegs ( Reserved , PPC :: LR8 ) ; markSuperRegs ( Reserved , PPC :: RM ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) markSuperRegs ( Reserved , PPC :: VRSAVE ) ; if ( Subtarget . isSVR4ABI ( ) ) { const PPCFunctionInfo * FuncInfo = MF . getInfo < PPCFunctionInfo > ( ) ; if ( ! TM . isPPC64 ( ) || FuncInfo -> usesTOCBasePtr ( ) || MF . hasInlineAsm ( ) ) markSuperRegs ( Reserved , PPC :: R2 ) ; markSuperRegs ( Reserved , PPC :: R13 ) ; } if ( Subtarget . isAIXABI ( ) ) markSuperRegs ( Reserved , PPC :: R2 ) ; if ( TM . isPPC64 ( ) ) markSuperRegs ( Reserved , PPC :: R13 ) ; if ( TFI -> needsFP ( MF ) ) markSuperRegs ( Reserved , PPC :: R31 ) ; bool IsPositionIndependent = TM . isPositionIndependent ( ) ; if ( hasBasePointer ( MF ) ) { if ( Subtarget . isSVR4ABI ( ) && ! TM . isPPC64 ( ) && IsPositionIndependent ) markSuperRegs ( Reserved , PPC :: R29 ) ; else markSuperRegs ( Reserved , PPC :: R30 ) ; } if ( Subtarget . isSVR4ABI ( ) && ! TM . isPPC64 ( ) && IsPositionIndependent ) markSuperRegs ( Reserved , PPC :: R30 ) ; if ( ! Subtarget . hasAltivec ( ) ) for ( TargetRegisterClass :: iterator I = PPC :: VRRCRegClass . begin ( ) , IE = PPC :: VRRCRegClass . end ( ) ; I != IE ; ++ I ) markSuperRegs ( Reserved , * I ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
void
AArch64TargetLowering
::
LowerAsmOperandForConstraint
(
SDValue
Op
,
std
::
string
&
Constraint
,
std
::
vector
<
SDValue
>
&
Ops
,
SelectionDAG
&
DAG
)
const
{
SDValue
Result
(
0
,
0
)
;
if
(
Constraint
.
size
(
)
!=
1
)
return
;
switch
(
Constraint
[
0
]
)
{
default
:
break
;
case
'I'
:
case
'J'
:
case
'K'
:
case
'L'
:
case
'M'
:
case
'N'
:
case
'Z'
:
{
ConstantSDNode
*
C
=
dyn_cast
<
ConstantSDNode
>
(
Op
)
;
if
(
!
C
)
return
;
uint64_t
CVal
=
C
->
getZExtValue
(
)
;
uint32_t
Bits
;
switch
(
Constraint
[
0
]
)
{
default
:
llvm_unreachable
(
"Unimplemented C_Other constraint"
)
;
case
'I'
:
if
(
CVal
<=
0xfff
)
break
;
return
;
case
'K'
:
if
(
A64Imms
::
isLogicalImm
(
32
,
CVal
,
Bits
)
)
break
;
return
;
case
'L'
:
if
(
A64Imms
::
isLogicalImm
(
64
,
CVal
,
Bits
)
)
break
;
return
;
case
'Z'
:
if
(
CVal
==
0
)
break
;
return
;
}
Result
=
DAG
.
getTargetConstant
(
CVal
,
Op
.
getValueType
(
)
)
;
break
;
}
case
'S'
:
{
if
(
const
GlobalAddressSDNode
*
GA
=
dyn_cast
<
GlobalAddressSDNode
>
(
Op
)
)
{
Result
=
DAG
.
getTargetGlobalAddress
(
GA
->
getGlobal
(
)
,
SDLoc
(
Op
)
,
GA
->
getValueType
(
0
)
)
;
}
else
if
(
const
BlockAddressSDNode
*
BA
=
dyn_cast
<
BlockAddressSDNode
>
(
Op
)
)
{
Result
=
DAG
.
getTargetBlockAddress
(
BA
->
getBlockAddress
(
)
,
BA
->
getValueType
(
0
)
)
;
}
else
if
(
const
ExternalSymbolSDNode
*
ES
=
dyn_cast
<
ExternalSymbolSDNode
>
(
Op
)
)
{
Result
=
DAG
.
getTargetExternalSymbol
(
ES
->
getSymbol
(
)
,
ES
->
getValueType
(
0
)
)
;
}
else
return
;
break
;
}
case
'Y'
:
if
(
const
ConstantFPSDNode
*
CFP
=
dyn_cast
<
ConstantFPSDNode
>
(
Op
)
)
{
if
(
CFP
->
isExactlyValue
(
0.0
)
)
{
Result
=
DAG
.
getTargetConstantFP
(
0.0
,
CFP
->
getValueType
(
0
)
)
;
break
;
}
}
return
;
}
if
(
Result
.
getNode
(
)
)
{
Ops
.
push_back
(
Result
)
;
return
;
}
TargetLowering
::
LowerAsmOperandForConstraint
(
Op
,
Constraint
,
Ops
,
DAG
)
;
}
</s>

Lower the specified operand into the Ops vector .


<s> int mips_register_move_cost ( enum machine_mode mode ATTRIBUTE_UNUSED , enum reg_class to , enum reg_class from ) { if ( from == M16_REGS && GR_REG_CLASS_P ( to ) ) return 2 ; else if ( from == M16_NA_REGS && GR_REG_CLASS_P ( to ) ) return 2 ; else if ( GR_REG_CLASS_P ( from ) ) { if ( to == M16_REGS ) return 2 ; else if ( to == M16_NA_REGS ) return 2 ; else if ( GR_REG_CLASS_P ( to ) ) { if ( TARGET_MIPS16 ) return 4 ; else return 2 ; } else if ( to == FP_REGS ) return 4 ; else if ( reg_class_subset_p ( to , ACC_REGS ) ) { if ( TARGET_MIPS16 ) return 12 ; else return 6 ; } else if ( COP_REG_CLASS_P ( to ) ) { return 5 ; } } else if ( from == FP_REGS ) { if ( GR_REG_CLASS_P ( to ) ) return 4 ; else if ( to == FP_REGS ) return 2 ; else if ( to == ST_REGS ) return 8 ; } else if ( reg_class_subset_p ( from , ACC_REGS ) ) { if ( GR_REG_CLASS_P ( to ) ) { if ( TARGET_MIPS16 ) return 12 ; else return 6 ; } } else if ( from == ST_REGS && GR_REG_CLASS_P ( to ) ) return 4 ; else if ( COP_REG_CLASS_P ( from ) ) { return 5 ; } return 12 ; } </s>

Implement TARGET_REGISTER_MOVE_COST . Return 0 for classes that are the maximum of the move costs for subclasses ; regclass will work out the maximum for us .


<s> bool AArch64TargetLowering :: isProfitableToHoist ( Instruction * I ) const { if ( I -> getOpcode ( ) != Instruction :: FMul ) return true ; if ( ! I -> hasOneUse ( ) ) return true ; Instruction * User = I -> user_back ( ) ; if ( User && ! ( User -> getOpcode ( ) == Instruction :: FSub || User -> getOpcode ( ) == Instruction :: FAdd ) ) return true ; const TargetOptions & Options = getTargetMachine ( ) . Options ; const Function * F = I -> getFunction ( ) ; const DataLayout & DL = F -> getParent ( ) -> getDataLayout ( ) ; Type * Ty = User -> getOperand ( 0 ) -> getType ( ) ; return ! ( isFMAFasterThanFMulAndFAdd ( * F , Ty ) && isOperationLegalOrCustom ( ISD :: FMA , getValueType ( DL , Ty ) ) && ( Options . AllowFPOpFusion == FPOpFusion :: Fast || Options . UnsafeFPMath ) ) ; } </s>

Return true if it is profitable to hoist instruction in the then/else to before if .


<s>
SDValue
HexagonTargetLowering
::
getZero
(
const
SDLoc
&
dl
,
MVT
Ty
,
SelectionDAG
&
DAG
)
const
{
if
(
Ty
.
isVector
(
)
)
{
unsigned
W
=
Ty
.
getSizeInBits
(
)
;
if
(
W
<=
64
)
return
DAG
.
getBitcast
(
Ty
,
DAG
.
getConstant
(
0
,
dl
,
MVT
::
getIntegerVT
(
W
)
)
)
;
return
DAG
.
getNode
(
ISD
::
SPLAT_VECTOR
,
dl
,
Ty
,
getZero
(
dl
,
MVT
::
i32
,
DAG
)
)
;
}
if
(
Ty
.
isInteger
(
)
)
return
DAG
.
getConstant
(
0
,
dl
,
Ty
)
;
if
(
Ty
.
isFloatingPoint
(
)
)
return
DAG
.
getConstantFP
(
0.0
,
dl
,
Ty
)
;
llvm_unreachable
(
"Invalid type for zero"
)
;
}
</s>

Return a SCEV for the constant 0 of a specific type .


<s> void Thumb2InstrInfo :: ReplaceTailWithBranchTo ( MachineBasicBlock :: iterator Tail , MachineBasicBlock * NewDest ) const { MachineBasicBlock * MBB = Tail -> getParent ( ) ; ARMFunctionInfo * AFI = MBB -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; if ( ! AFI -> hasITBlocks ( ) ) { TargetInstrInfoImpl :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; return ; } unsigned PredReg = 0 ; ARMCC :: CondCodes CC = llvm :: getInstrPredicate ( Tail , PredReg ) ; MachineBasicBlock :: iterator MBBI = Tail ; if ( CC != ARMCC :: AL ) -- MBBI ; TargetInstrInfoImpl :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; if ( CC != ARMCC :: AL ) { MachineBasicBlock :: iterator E = MBB -> begin ( ) ; unsigned Count = 4 ; while ( Count && MBBI != E ) { if ( MBBI -> isDebugValue ( ) ) { -- MBBI ; continue ; } if ( MBBI -> getOpcode ( ) == ARM :: t2IT ) { unsigned Mask = MBBI -> getOperand ( 1 ) . getImm ( ) ; if ( Count == 4 ) MBBI -> eraseFromParent ( ) ; else { unsigned MaskOn = 1 << Count ; unsigned MaskOff = ~ ( MaskOn - 1 ) ; MBBI -> getOperand ( 1 ) . setImm ( ( Mask & MaskOff ) | MaskOn ) ; } return ; } -- MBBI ; -- Count ; } } } </s>

Delete the instruction OldInst and everything after it , replacing it with an unconditional branch to NewDest .


<s> bool arm_pad_arg_upward ( enum machine_mode mode , tree type ) { if ( ! TARGET_AAPCS_BASED ) return DEFAULT_FUNCTION_ARG_PADDING ( mode , type ) == upward ; if ( type && BYTES_BIG_ENDIAN && INTEGRAL_TYPE_P ( type ) ) return false ; return true ; } </s>

For use by FUNCTION_ARG_PADDING ( MODE , TYPE ) . Return true if an argument passed on the stack should be padded upwards , i.e . if the least-significant byte has useful data . For legacy APCS ABIs we use the default . For AAPCS based ABIs small aggregate types are placed in the lowest memory address .


<s> bool MSP430TargetLowering :: isZExtFree ( SDValue Val , EVT VT2 ) const { return isZExtFree ( Val . getValueType ( ) , VT2 ) ; } </s>

Return true if zero-extending the specific node Val to type VT2 is free ( either because it 's implicitly zero-extended such as ARM ldrb / ldrh or because it 's folded such as X86 zero-extending loads ) .


" was Pass-through, is now Dirty-out.\n"


"Couldn't get MachineMemOperand for store to stack."

"Only support 4-byte loads from stack now."

"Only support GPR32 stores to stack now."

Load the specified register of the given register class from the specified stack frame index .


<s> void PatmosPostRASchedStrategy :: finalize ( ScheduleDAGPostRA * dag ) { DAG = NULL ; } </s>

Analyze the strings and build the final table .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ; AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void SITargetLowering :: computeKnownBitsForFrameIndex ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { TargetLowering :: computeKnownBitsForFrameIndex ( Op , Known , DemandedElts , DAG , Depth ) ; if ( getSubtarget ( ) -> enableHugePrivateBuffer ( ) ) return ; Known . Zero . setHighBits ( AssumeFrameIndexHighZeroBits ) ; } </s>

Determine which of the bits of FrameIndex FIOp are known to be 0 .