<s> SDValue XCoreTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_XCore ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> void m68hc11_output_swap ( rtx insn ATTRIBUTE_UNUSED , rtx operands [ ] ) { if ( X_REG_P ( operands [ 1 ] ) || X_REG_P ( operands [ 0 ] ) ) { if ( cc_prev_status . value1 != 0 && ( D_REG_P ( cc_prev_status . value1 ) || X_REG_P ( cc_prev_status . value1 ) ) ) { cc_status = cc_prev_status ; if ( D_REG_P ( cc_status . value1 ) ) cc_status . value1 = gen_rtx_REG ( GET_MODE ( cc_status . value1 ) , HARD_X_REGNUM ) ; else cc_status . value1 = gen_rtx_REG ( GET_MODE ( cc_status . value1 ) , HARD_D_REGNUM ) ; } else CC_STATUS_INIT ; output_asm_insn ( "xgdx" , operands ) ; } else { if ( cc_prev_status . value1 != 0 && ( D_REG_P ( cc_prev_status . value1 ) || Y_REG_P ( cc_prev_status . value1 ) ) ) { cc_status = cc_prev_status ; if ( D_REG_P ( cc_status . value1 ) ) cc_status . value1 = gen_rtx_REG ( GET_MODE ( cc_status . value1 ) , HARD_Y_REGNUM ) ; else cc_status . value1 = gen_rtx_REG ( GET_MODE ( cc_status . value1 ) , HARD_D_REGNUM ) ; } else CC_STATUS_INIT ; output_asm_insn ( "xgdy" , operands ) ; } } </s>


<s> static void rs6000_xcoff_select_rtx_section ( enum machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED ) { if ( ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( x , mode ) ) toc_section ( ) ; else read_only_private_data_section ( ) ; } </s>

Select section for constant in constant pool . On RS/6000 , all constants are in the private read-only data area . However , if this is being placed in the TOC it must be output as a toc entry .


<s>
char
*
neon_output_shift_immediate
(
const
char
*
mnem
,
char
sign
,
rtx
*
op2
,
machine_mode
mode
,
int
quad
,
bool
isleftshift
)
{
int
width
,
is_valid
;
static
char
templ
[
40
]
;
is_valid
=
neon_immediate_valid_for_shift
(
*
op2
,
mode
,
op2
,
&
width
,
isleftshift
)
;
gcc_assert
(
is_valid
!=
0
)
;
if
(
quad
)
sprintf
(
templ
,
"%s.%c%d\t%%q0, %%q1, %%2"
,
mnem
,
sign
,
width
)
;
else
sprintf
(
templ
,
"%s.%c%d\t%%P0, %%P1, %%2"
,
mnem
,
sign
,
width
)
;
return
templ
;
}
</s>

Return a string suitable for output of Neon immediate shift operation ( VSHR or VSHL ) MNEM .


<s> static void choose_basereg ( HOST_WIDE_INT cfa_offset , rtx & base_reg , HOST_WIDE_INT & base_offset , unsigned int align_reqested , unsigned int * align ) { const struct machine_function * m = cfun -> machine ; unsigned int hfp_align ; unsigned int drap_align ; unsigned int sp_align ; bool hfp_ok = fp_valid_at ( cfa_offset ) ; bool drap_ok = m -> fs . drap_valid ; bool sp_ok = sp_valid_at ( cfa_offset ) ; hfp_align = drap_align = sp_align = INCOMING_STACK_BOUNDARY ; if ( align_reqested ) { if ( m -> fs . realigned ) hfp_align = drap_align = sp_align = crtl -> stack_alignment_needed ; else if ( m -> fs . sp_realigned ) sp_align = crtl -> stack_alignment_needed ; hfp_ok = hfp_ok && hfp_align >= align_reqested ; drap_ok = drap_ok && drap_align >= align_reqested ; sp_ok = sp_ok && sp_align >= align_reqested ; } if ( m -> use_fast_prologue_epilogue ) { if ( hfp_ok ) { base_reg = hard_frame_pointer_rtx ; base_offset = m -> fs . fp_offset - cfa_offset ; } else if ( drap_ok ) { base_reg = crtl -> drap_reg ; base_offset = 0 - cfa_offset ; } else if ( sp_ok ) { base_reg = stack_pointer_rtx ; base_offset = m -> fs . sp_offset - cfa_offset ; } } else { HOST_WIDE_INT toffset ; int len = 16 , tlen ; if ( sp_ok ) { base_reg = stack_pointer_rtx ; base_offset = m -> fs . sp_offset - cfa_offset ; len = choose_baseaddr_len ( STACK_POINTER_REGNUM , base_offset ) ; } if ( drap_ok ) { toffset = 0 - cfa_offset ; tlen = choose_baseaddr_len ( REGNO ( crtl -> drap_reg ) , toffset ) ; if ( tlen <= len ) { base_reg = crtl -> drap_reg ; base_offset = toffset ; len = tlen ; } } if ( hfp_ok ) { toffset = m -> fs . fp_offset - cfa_offset ; tlen = choose_baseaddr_len ( HARD_FRAME_POINTER_REGNUM , toffset ) ; if ( tlen <= len ) { base_reg = hard_frame_pointer_rtx ; base_offset = toffset ; } } } if ( align ) { if ( base_reg == stack_pointer_rtx ) * align = sp_align ; else if ( base_reg == crtl -> drap_reg ) * align = drap_align ; else if ( base_reg == hard_frame_pointer_rtx ) * align = hfp_align ; } } </s>

Choose a base register based upon alignment requested , speed and/or size .


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCRelaxableFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
{
llvm_unreachable
(
"fixupNeedsRelaxation() unimplemeted"
)
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> static HOST_WIDE_INT arg_area_size ( void ) { if ( current_function_outgoing_args_size ) { if ( current_function_outgoing_args_size >= FIXED_STACK_AREA ) return current_function_outgoing_args_size ; else return FIXED_STACK_AREA ; } return 0 ; } </s>

Return the number of bytes we must reserve for outgoing arguments in the current function 's stack frame .


<s> void v850_output_aligned_bss ( FILE * file , tree decl , const char * name , unsigned HOST_WIDE_INT size , int align ) { switch ( v850_get_data_area ( decl ) ) { case DATA_AREA_ZDA : switch_to_section ( zbss_section ) ; break ; case DATA_AREA_SDA : switch_to_section ( sbss_section ) ; break ; case DATA_AREA_TDA : switch_to_section ( tdata_section ) ; default : switch_to_section ( bss_section ) ; break ; } ASM_OUTPUT_ALIGN ( file , floor_log2 ( align / BITS_PER_UNIT ) ) ; last_assemble_variable_decl = decl ; ASM_DECLARE_OBJECT_NAME ( file , name , decl ) ; ASM_OUTPUT_LABEL ( file , name ) ; ASM_OUTPUT_SKIP ( file , size ? size : 1 ) ; } </s>

A version of asm_output_aligned_bss ( ) that copes with the special data areas of the v850 .


<s>
const
char
*
host_detect_local_cpu
(
int
argc
,
const
char
*
*
argv
)
{
const
char
*
cpu
=
;
char
*
ret
=
;
char
buf
[
128
]
;
FILE
*
f
;
bool
arch
;
if
(
argc
<
1
)
return
;
arch
=
strcmp
(
argv
[
0
]
,
"arch"
)
==
0
;
if
(
!
arch
&&
strcmp
(
argv
[
0
]
,
"tune"
)
)
return
;
f
=
fopen
(
"/proc/cpuinfo"
,
"r"
)
;
if
(
f
==
)
goto
fallback_cpu
;
while
(
fgets
(
buf
,
sizeof
(
buf
)
,
f
)
!=
)
if
(
startswith
(
buf
,
"cpu model"
)
)
{
if
(
strstr
(
buf
,
"Godson2 V0.2"
)
!=
||
strstr
(
buf
,
"Loongson-2 V0.2"
)
!=
||
strstr
(
buf
,
"Loongson-2E"
)
!=
)
cpu
=
"loongson2e"
;
else
if
(
strstr
(
buf
,
"Godson2 V0.3"
)
!=
||
strstr
(
buf
,
"Loongson-2 V0.3"
)
!=
||
strstr
(
buf
,
"Loongson-2F"
)
!=
)
cpu
=
"loongson2f"
;
else
if
(
strstr
(
buf
,
"Godson3 V0.5"
)
!=
||
strstr
(
buf
,
"Loongson-3 V0.5"
)
!=
||
strstr
(
buf
,
"Loongson-3A"
)
!=
)
cpu
=
"loongson3a"
;
else
if
(
strstr
(
buf
,
"SiByte SB1"
)
!=
)
cpu
=
"sb1"
;
else
if
(
strstr
(
buf
,
"R5000"
)
!=
)
cpu
=
"r5000"
;
else
if
(
strstr
(
buf
,
"Octeon II"
)
!=
)
cpu
=
"octeon2"
;
else
if
(
strstr
(
buf
,
"Octeon"
)
!=
)
cpu
=
"octeon"
;
break
;
}
fclose
(
f
)
;
fallback_cpu
:
ret
=
reconcat
(
ret
,
" -mnan=2008 "
,
)
;
if
(
cpu
==
)
cpu
=
(
const
char
*
)
getauxval
(
AT_BASE_PLATFORM
)
;
if
(
cpu
==
)
cpu
=
_MIPS_ARCH
;
if
(
cpu
)
ret
=
reconcat
(
ret
,
ret
,
"-m"
,
argv
[
0
]
,
"="
,
cpu
,
)
;
return
ret
;
}
</s>

This will be called by the spec parser in gcc.cc when it sees a % : local_cpu_detect ( args ) construct . Currently it will be called with either `` cpu '' or `` tune '' as argument depending on if -mcpu=native or -mtune=native is to be substituted . It returns a string containing new command line parameters to be put at the place of the above two options , depending on what CPU this is executed . E.g . `` -mcpu=ultrasparc3 '' on an UltraSPARC III for -mcpu=native . If the routine ca n't detect a known processor , the -mcpu or -mtune option is discarded . ARGC and ARGV are set depending on the actual arguments given in the spec .


<s>
const
char
*
mn10300_output_add
(
rtx
operands
[
3
]
,
bool
need_flags
)
{
rtx
dest
,
src1
,
src2
;
unsigned
int
dest_regnum
,
src1_regnum
,
src2_regnum
;
enum
reg_class
src1_class
,
src2_class
,
dest_class
;
dest
=
operands
[
0
]
;
src1
=
operands
[
1
]
;
src2
=
operands
[
2
]
;
dest_regnum
=
true_regnum
(
dest
)
;
src1_regnum
=
true_regnum
(
src1
)
;
dest_class
=
REGNO_REG_CLASS
(
dest_regnum
)
;
src1_class
=
REGNO_REG_CLASS
(
src1_regnum
)
;
if
(
CONST_INT_P
(
src2
)
)
{
gcc_assert
(
dest_regnum
==
src1_regnum
)
;
if
(
src2
==
const1_rtx
&&
!
need_flags
)
return
"inc %0"
;
if
(
INTVAL
(
src2
)
==
4
&&
!
need_flags
&&
dest_class
!=
DATA_REGS
)
return
"inc4 %0"
;
gcc_assert
(
!
need_flags
||
dest_class
!=
SP_REGS
)
;
return
"add %2,%0"
;
}
else
if
(
CONSTANT_P
(
src2
)
)
return
"add %2,%0"
;
src2_regnum
=
true_regnum
(
src2
)
;
src2_class
=
REGNO_REG_CLASS
(
src2_regnum
)
;
if
(
dest_regnum
==
src1_regnum
)
return
"add %2,%0"
;
if
(
dest_regnum
==
src2_regnum
)
return
"add %1,%0"
;
if
(
TARGET_AM33
&&
optimize_insn_for_speed_p
(
)
)
return
"add %2,%1,%0"
;
if
(
src1_class
!=
EXTENDED_REGS
&&
src2_class
!=
EXTENDED_REGS
&&
dest_class
!=
EXTENDED_REGS
)
{
if
(
src1_class
==
dest_class
)
return
"mov %1,%0\n\tadd %2,%0"
;
else
return
"mov %2,%0\n\tadd %1,%0"
;
}
if
(
dest_class
==
EXTENDED_REGS
||
src1_class
==
src2_class
)
return
"add %2,%1,%0"
;
if
(
src1_class
==
EXTENDED_REGS
)
return
"mov %1,%0\n\tadd %2,%0"
;
else
return
"mov %2,%0\n\tadd %1,%0"
;
}
</s>


"passing %qT to argument %d of %qE, which"

Require argument ARGNO to have vector type TYPE , in cases where this requirement holds for all uses of the function . Return true if the argument has the right form , otherwise report an appropriate error .


<s> virtual const SystemZRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> int cris_legitimate_pic_operand ( rtx x ) { return cris_valid_pic_const ( x , true ) ; } </s>


"Wasn't expecting to be able to lower this!"

LowerOperation - Provide custom lowering hooks for some operations .


<s> static rtx stv_expand_builtin ( insn_code icode , rtx * op , machine_mode tmode , machine_mode smode ) { op [ 2 ] = copy_to_mode_reg ( Pmode , op [ 2 ] ) ; if ( icode == CODE_FOR_altivec_stvx_v2df || icode == CODE_FOR_altivec_stvx_v2di || icode == CODE_FOR_altivec_stvx_v4sf || icode == CODE_FOR_altivec_stvx_v4si || icode == CODE_FOR_altivec_stvx_v8hi || icode == CODE_FOR_altivec_stvx_v16qi ) { rtx rawaddr ; if ( op [ 1 ] == const0_rtx ) rawaddr = op [ 2 ] ; else { op [ 1 ] = copy_to_mode_reg ( Pmode , op [ 1 ] ) ; rawaddr = gen_rtx_PLUS ( Pmode , op [ 2 ] , op [ 1 ] ) ; } rtx addr = gen_rtx_AND ( Pmode , rawaddr , gen_rtx_CONST_INT ( Pmode , - 16 ) ) ; addr = gen_rtx_MEM ( tmode , addr ) ; op [ 0 ] = copy_to_mode_reg ( tmode , op [ 0 ] ) ; emit_insn ( gen_rtx_SET ( addr , op [ 0 ] ) ) ; } else if ( icode == CODE_FOR_vsx_stxvrbx || icode == CODE_FOR_vsx_stxvrhx || icode == CODE_FOR_vsx_stxvrwx || icode == CODE_FOR_vsx_stxvrdx ) { rtx truncrtx = gen_rtx_TRUNCATE ( tmode , op [ 0 ] ) ; op [ 0 ] = copy_to_mode_reg ( E_TImode , truncrtx ) ; rtx addr ; if ( op [ 1 ] == const0_rtx ) addr = gen_rtx_MEM ( tmode , op [ 2 ] ) ; else { op [ 1 ] = copy_to_mode_reg ( Pmode , op [ 1 ] ) ; addr = gen_rtx_MEM ( tmode , gen_rtx_PLUS ( Pmode , op [ 2 ] , op [ 1 ] ) ) ; } rtx pat = GEN_FCN ( icode ) ( addr , op [ 0 ] ) ; if ( pat ) emit_insn ( pat ) ; } else { if ( ! insn_data [ icode ] . operand [ 1 ] . predicate ( op [ 0 ] , smode ) ) op [ 0 ] = copy_to_mode_reg ( smode , op [ 0 ] ) ; rtx addr ; if ( op [ 1 ] == const0_rtx ) addr = gen_rtx_MEM ( tmode , op [ 2 ] ) ; else { op [ 1 ] = copy_to_mode_reg ( Pmode , op [ 1 ] ) ; addr = gen_rtx_MEM ( tmode , gen_rtx_PLUS ( Pmode , op [ 2 ] , op [ 1 ] ) ) ; } rtx pat = GEN_FCN ( icode ) ( addr , op [ 0 ] ) ; if ( pat ) emit_insn ( pat ) ; } return NULL_RTX ; } </s>

Expand an AltiVec vector store builtin , and return the expanded rtx .


<s> static section * loongarch_select_rtx_section ( machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ) { if ( loongarch_rtx_constant_in_small_data_p ( mode ) ) return get_named_section ( NULL , ".sdata" , 0 ) ; return default_elf_select_rtx_section ( mode , x , align ) ; } </s>


<s> bool SPIRVPreLegalizer :: runOnMachineFunction ( MachineFunction & MF ) { const SPIRVSubtarget & ST = MF . getSubtarget < SPIRVSubtarget > ( ) ; SPIRVGlobalRegistry * GR = ST . getSPIRVGlobalRegistry ( ) ; GR -> setCurrentFunc ( MF ) ; MachineIRBuilder MIB ( MF ) ; addConstantsToTrack ( MF , GR ) ; foldConstantsIntoIntrinsics ( MF ) ; insertBitcasts ( MF , GR , MIB ) ; generateAssignInstrs ( MF , GR , MIB ) ; processInstrsWithTypeFolding ( MF , GR , MIB ) ; processSwitches ( MF , GR , MIB ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> SDValue PPCTargetLowering :: getRecipEstimate ( SDValue Operand , DAGCombinerInfo & DCI , unsigned & RefinementSteps ) const { EVT VT = Operand . getValueType ( ) ; if ( ( VT == MVT :: f32 && Subtarget . hasFRES ( ) ) || ( VT == MVT :: f64 && Subtarget . hasFRE ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasAltivec ( ) ) || ( VT == MVT :: v2f64 && Subtarget . hasVSX ( ) ) ) { RefinementSteps = Subtarget . hasRecipPrec ( ) ? 1 : 3 ; if ( VT . getScalarType ( ) == MVT :: f64 ) ++ RefinementSteps ; return DCI . DAG . getNode ( PPCISD :: FRE , SDLoc ( Operand ) , VT , Operand ) ; } return SDValue ( ) ; } </s>

Return a reciprocal estimate value for the input operand .


"instruction requires a CPU feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> static bool alpha_in_small_data_p ( tree exp ) { if ( TREE_CODE ( exp ) == STRING_CST ) return false ; if ( TREE_CODE ( exp ) == FUNCTION_DECL ) return false ; if ( TREE_CODE ( exp ) == VAR_DECL && DECL_SECTION_NAME ( exp ) ) { const char * section = TREE_STRING_POINTER ( DECL_SECTION_NAME ( exp ) ) ; if ( strcmp ( section , ".sdata" ) == 0 || strcmp ( section , ".sbss" ) == 0 ) return true ; } else { HOST_WIDE_INT size = int_size_in_bytes ( TREE_TYPE ( exp ) ) ; if ( size > 0 && ( unsigned HOST_WIDE_INT ) size <= g_switch_value ) return true ; } return false ; } </s>

Return true if EXP should be placed in the small data section .


<s>
unsigned
MipsSEInstrInfo
::
getOppositeBranchOpc
(
unsigned
Opc
)
const
{
switch
(
Opc
)
{
default
:
llvm_unreachable
(
"Illegal opcode!"
)
;
case
Mips
::
BEQ
:
return
Mips
::
BNE
;
case
Mips
::
BEQ_MM
:
return
Mips
::
BNE_MM
;
case
Mips
::
BNE
:
return
Mips
::
BEQ
;
case
Mips
::
BNE_MM
:
return
Mips
::
BEQ_MM
;
case
Mips
::
BGTZ
:
return
Mips
::
BLEZ
;
case
Mips
::
BGEZ
:
return
Mips
::
BLTZ
;
case
Mips
::
BLTZ
:
return
Mips
::
BGEZ
;
case
Mips
::
BLEZ
:
return
Mips
::
BGTZ
;
case
Mips
::
BEQ64
:
return
Mips
::
BNE64
;
case
Mips
::
BNE64
:
return
Mips
::
BEQ64
;
case
Mips
::
BGTZ64
:
return
Mips
::
BLEZ64
;
case
Mips
::
BGEZ64
:
return
Mips
::
BLTZ64
;
case
Mips
::
BLTZ64
:
return
Mips
::
BGEZ64
;
case
Mips
::
BLEZ64
:
return
Mips
::
BGTZ64
;
case
Mips
::
BC1T
:
return
Mips
::
BC1F
;
case
Mips
::
BC1F
:
return
Mips
::
BC1T
;
case
Mips
::
BEQZC_MM
:
return
Mips
::
BNEZC_MM
;
case
Mips
::
BNEZC_MM
:
return
Mips
::
BEQZC_MM
;
case
Mips
::
BEQZC
:
return
Mips
::
BNEZC
;
case
Mips
::
BNEZC
:
return
Mips
::
BEQZC
;
case
Mips
::
BEQC
:
return
Mips
::
BNEC
;
case
Mips
::
BNEC
:
return
Mips
::
BEQC
;
case
Mips
::
BGTZC
:
return
Mips
::
BLEZC
;
case
Mips
::
BGEZC
:
return
Mips
::
BLTZC
;
case
Mips
::
BLTZC
:
return
Mips
::
BGEZC
;
case
Mips
::
BLEZC
:
return
Mips
::
BGTZC
;
case
Mips
::
BEQZC64
:
return
Mips
::
BNEZC64
;
case
Mips
::
BNEZC64
:
return
Mips
::
BEQZC64
;
case
Mips
::
BEQC64
:
return
Mips
::
BNEC64
;
case
Mips
::
BNEC64
:
return
Mips
::
BEQC64
;
case
Mips
::
BGEC64
:
return
Mips
::
BLTC64
;
case
Mips
::
BGEUC64
:
return
Mips
::
BLTUC64
;
case
Mips
::
BLTC64
:
return
Mips
::
BGEC64
;
case
Mips
::
BLTUC64
:
return
Mips
::
BGEUC64
;
case
Mips
::
BGTZC64
:
return
Mips
::
BLEZC64
;
case
Mips
::
BGEZC64
:
return
Mips
::
BLTZC64
;
case
Mips
::
BLTZC64
:
return
Mips
::
BGEZC64
;
case
Mips
::
BLEZC64
:
return
Mips
::
BGTZC64
;
case
Mips
::
BBIT0
:
return
Mips
::
BBIT1
;
case
Mips
::
BBIT1
:
return
Mips
::
BBIT0
;
case
Mips
::
BBIT032
:
return
Mips
::
BBIT132
;
case
Mips
::
BBIT132
:
return
Mips
::
BBIT032
;
}
}
</s>

getOppositeBranchOpc - Return the inverse of the specified opcode , e.g .


<s> void TriCorePassConfig :: addPreEmitPass ( ) { } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


Return nonzero if the CONSUMER instruction is some sort of arithmetic or logic + shift operation , and the register we are writing in PRODUCER is not used in a register shift by register operation .


<s> const PPCSubtarget * PPCTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) FS += FS . empty ( ) ? "-hard-float" : ",-hard-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < PPCSubtarget > ( TargetTriple , CPU , computeFSAdditions ( FS , getOptLevel ( ) , getTargetTriple ( ) ) , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

PowerPC PPC PPC "target-cpu" "target-features" "use-soft-float" "true" "-hard-float" ",-hard-float" PPC


<s> bool FineIBTHashesSection :: runOnModule ( Module & M ) { if ( ! M . getModuleFlag ( "cf-protection-fine" ) ) return false ; const TargetMachine * TM = & getAnalysis < TargetPassConfig > ( ) . getTM < TargetMachine > ( ) ; if ( ! TM ) return false ; for ( auto & F : M ) { if ( F . getName ( ) . startswith ( "__ibt_fine_plt" ) ) continue ; if ( ! F . doesNoCfCheck ( ) && ! F . doesCoarseCfCheck ( ) && ! F . hasLocalLinkage ( ) ) { if ( F . isIntrinsic ( ) && ! IsExternalIntrinsic ( & F ) ) continue ; CreatePLTTemplate ( M , & F ) ; } } return true ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> int vms_c_get_vms_ver ( void ) { return VMS_DEFAULT_VMS_VER ; } </s>


<s> static int riscv_register_priority ( int regno ) { if ( riscv_compressed_reg_p ( regno ) ) return 1 ; return 0 ; } </s>

Return a register priority for hard reg REGNO .


<s> int msp430_initial_elimination_offset ( int from , int to ) { int rv = 0 ; msp430_compute_frame_info ( ) ; switch ( to ) { case STACK_POINTER_REGNUM : rv += cfun -> machine -> framesize_outgoing ; rv += cfun -> machine -> framesize_locals ; case FRAME_POINTER_REGNUM : rv += cfun -> machine -> framesize_regs ; rv += ( TARGET_LARGE ? 4 : 2 ) ; break ; default : gcc_unreachable ( ) ; } switch ( from ) { case FRAME_POINTER_REGNUM : rv -= ( TARGET_LARGE ? 4 : 2 ) ; rv -= cfun -> machine -> framesize_regs ; case ARG_POINTER_REGNUM : break ; default : gcc_unreachable ( ) ; } return rv ; } </s>


<s> static SDValue getVectorShuffle ( SelectionDAG & DAG , EVT VT , const SDLoc & dl , SDValue V1 , SDValue V2 , ArrayRef < int > Mask ) { if ( ( ISD :: isBuildVectorOfConstantSDNodes ( V1 . getNode ( ) ) || V1 . isUndef ( ) ) && ( ISD :: isBuildVectorOfConstantSDNodes ( V2 . getNode ( ) ) || V2 . isUndef ( ) ) ) { SmallVector < SDValue > Ops ( Mask . size ( ) , DAG . getUNDEF ( VT . getScalarType ( ) ) ) ; for ( int I = 0 , NumElts = Mask . size ( ) ; I != NumElts ; ++ I ) { int M = Mask [ I ] ; if ( M < 0 ) continue ; SDValue V = ( M < NumElts ) ? V1 : V2 ; if ( V . isUndef ( ) ) continue ; Ops [ I ] = V . getOperand ( M % NumElts ) ; } return DAG . getBuildVector ( VT , dl , Ops ) ; } return DAG . getVectorShuffle ( VT , dl , V1 , V2 , Mask ) ; } </s>


<s> static bool mn10300_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( REGNO_REG_CLASS ( regno ) == FP_REGS || REGNO_REG_CLASS ( regno ) == FP_ACC_REGS ) return GET_MODE_CLASS ( mode ) == MODE_FLOAT && ( ( regno & 1 ) == 0 ) ; if ( ! TARGET_AM33 && REGNO_REG_CLASS ( regno ) == EXTENDED_REGS ) return false ; if ( ( ( regno ) & 1 ) == 0 || GET_MODE_SIZE ( mode ) == 4 ) return true ; if ( REGNO_REG_CLASS ( regno ) == DATA_REGS || ( TARGET_AM33 && REGNO_REG_CLASS ( regno ) == ADDRESS_REGS ) || REGNO_REG_CLASS ( regno ) == EXTENDED_REGS ) return GET_MODE_SIZE ( mode ) <= 4 ; return false ; } </s>


"Flag output operand is of invalid type"


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> MCInst Thumb1InstrInfo :: getNop ( ) const { return MCInstBuilder ( ARM :: tMOVr ) . addReg ( ARM :: R8 ) . addReg ( ARM :: R8 ) . addImm ( ARMCC :: AL ) . addReg ( 0 ) ; } </s>

Return the noop instruction to use for a noop .


<s> machine_mode frv_select_cc_mode ( enum rtx_code code , rtx x , rtx y ) { if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) return CC_FPmode ; switch ( code ) { case EQ : case NE : case LT : case GE : return y == const0_rtx ? CC_NZmode : CCmode ; case GTU : case GEU : case LTU : case LEU : return y == const0_rtx ? CC_NZmode : CC_UNSmode ; default : return CCmode ; } } </s>

Implement SELECT_CC_MODE . Choose CC_FP for floating-point comparisons , CC_NZ for comparisons against zero in which a single Z or N flag test is enough , CC_UNS for other unsigned comparisons , and CC for other signed comparisons .


<s> uint64_t MipsFrameLowering :: estimateStackSize ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; int64_t Size = 0 ; for ( int I = MFI . getObjectIndexBegin ( ) ; I != 0 ; ++ I ) if ( MFI . getObjectOffset ( I ) > 0 ) Size += MFI . getObjectSize ( I ) ; for ( const MCPhysReg * R = TRI . getCalleeSavedRegs ( & MF ) ; * R ; ++ R ) { unsigned RegSize = TRI . getSpillSize ( * TRI . getMinimalPhysRegClass ( * R ) ) ; Size = alignTo ( Size + RegSize , RegSize ) ; } return Size + MFI . estimateStackSize ( MF ) ; } </s>

Estimate and return the size of the stack frame .


<s> const uint32_t * PPCRegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { if ( Subtarget . isDarwinABI ( ) ) return Subtarget . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_RegMask : CSR_Darwin64_RegMask ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_RegMask : CSR_Darwin32_RegMask ) ; return Subtarget . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_SVR464_Altivec_RegMask : CSR_SVR464_RegMask ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR432_Altivec_RegMask : CSR_SVR432_RegMask ) ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
AAP
::
NumTargetFixupKinds
]
=
{
{
"fixup_AAP_NONE"
,
0
,
16
,
0
}
,
{
"fixup_AAP_BR16"
,
0
,
9
,
0
}
,
{
"fixup_AAP_BR32"
,
0
,
9
,
0
}
,
{
"fixup_AAP_BRCC16"
,
6
,
3
,
0
}
,
{
"fixup_AAP_BRCC32"
,
6
,
3
,
0
}
,
{
"fixup_AAP_BAL16"
,
0
,
3
,
0
}
,
{
"fixup_AAP_BAL32"
,
0
,
3
,
0
}
,
{
"fixup_AAP_ABS6"
,
0
,
3
,
0
}
,
{
"fixup_AAP_ABS9"
,
0
,
3
,
0
}
,
{
"fixup_AAP_ABS10"
,
0
,
3
,
0
}
,
{
"fixup_AAP_ABS12"
,
0
,
6
,
0
}
,
{
"fixup_AAP_ABS16"
,
0
,
6
,
0
}
,
{
"fixup_AAP_SHIFT6"
,
0
,
3
,
0
}
,
{
"fixup_AAP_OFF10"
,
0
,
3
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> bool X86AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { static const uint8_t Nops [ 10 ] [ 10 ] = { { 0x90 } , { 0x66 , 0x90 } , { 0x0f , 0x1f , 0x00 } , { 0x0f , 0x1f , 0x40 , 0x00 } , { 0x0f , 0x1f , 0x44 , 0x00 , 0x00 } , { 0x66 , 0x0f , 0x1f , 0x44 , 0x00 , 0x00 } , { 0x0f , 0x1f , 0x80 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x66 , 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x66 , 0x2e , 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , } ; if ( CPU == "generic" || CPU == "i386" || CPU == "i486" || CPU == "i586" || CPU == "pentium" || CPU == "pentium-mmx" || CPU == "geode" ) { for ( uint64_t i = 0 ; i < Count ; ++ i ) OW -> Write8 ( 0x90 ) ; return true ; } const uint64_t OptimalCount = ( Count < 16 ) ? Count : 15 ; const uint64_t Prefixes = OptimalCount <= 10 ? 0 : OptimalCount - 10 ; for ( uint64_t i = 0 , e = Prefixes ; i != e ; i ++ ) OW -> Write8 ( 0x66 ) ; const uint64_t Rest = OptimalCount - Prefixes ; for ( uint64_t i = 0 , e = Rest ; i != e ; i ++ ) OW -> Write8 ( Nops [ Rest - 1 ] [ i ] ) ; for ( uint64_t i = OptimalCount , e = Count ; i != e ; ++ i ) OW -> Write8 ( 0x90 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> EVT MipsTargetLowering :: getTypeForExtReturn ( LLVMContext & Context , EVT VT , ISD :: NodeType ) const { bool Cond = ! Subtarget . isABI_O32 ( ) && VT . getSizeInBits ( ) == 32 ; EVT MinVT = getRegisterType ( Context , Cond ? MVT :: i64 : MVT :: i32 ) ; return VT . bitsLT ( MinVT ) ? MinVT : VT ; } </s>

Return the type that should be used to zero or sign extend a zeroext/signext integer return value .


<s> static void ix86_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; HOST_WIDE_INT bytes , words ; int nregs ; if ( mode == BLKmode ) bytes = int_size_in_bytes ( type ) ; else bytes = GET_MODE_SIZE ( mode ) ; words = CEIL ( bytes , UNITS_PER_WORD ) ; if ( type ) mode = type_natural_mode ( type , NULL , false ) ; if ( ( type && POINTER_BOUNDS_TYPE_P ( type ) ) || POINTER_BOUNDS_MODE_P ( mode ) ) { if ( cum -> bnds_in_bt ) { cum -> bnds_in_bt -- ; return ; } if ( cum -> force_bnd_pass ) cum -> force_bnd_pass -- ; cum -> bnd_regno ++ ; return ; } cum -> bnds_in_bt = 0 ; if ( cum -> force_bnd_pass ) { cum -> bnd_regno += cum -> force_bnd_pass ; cum -> force_bnd_pass = 0 ; } if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) nregs = function_arg_advance_ms_64 ( cum , bytes , words ) ; else nregs = function_arg_advance_64 ( cum , mode , type , words , named ) ; } else nregs = function_arg_advance_32 ( cum , mode , type , bytes , words ) ; if ( cum -> stdarg ) cum -> force_bnd_pass = nregs ; if ( ! nregs ) cum -> bnds_in_bt = chkp_type_bounds_count ( type ) ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> bool valid ( ) const { return Ref . size ( ) >= sizeof ( Item ) && Ref . size ( ) >= getItemPadSize ( ) ; } </s>

valid - Return true if iterator is at an overlap .


<s> static unsigned int find_drap_reg ( void ) { tree decl = cfun -> decl ; if ( TARGET_64BIT ) { if ( DECL_STATIC_CHAIN ( decl ) || cfun -> machine -> no_caller_saved_registers || crtl -> tail_call_emit ) return R13_REG ; return R10_REG ; } else { if ( DECL_STATIC_CHAIN ( decl ) || cfun -> machine -> no_caller_saved_registers || crtl -> tail_call_emit || crtl -> calls_eh_return ) return DI_REG ; if ( ix86_function_regparm ( TREE_TYPE ( decl ) , decl ) <= 2 ) { unsigned int ccvt = ix86_get_callcvt ( TREE_TYPE ( decl ) ) ; if ( ( ccvt & ( IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL ) ) == 0 ) return CX_REG ; } return DI_REG ; } } </s>

Find an available register to be used as dynamic realign argument pointer regsiter . Such a register will be written in prologue and used in begin of body , so it must not be 1. parameter passing register . 2 . GOT pointer . We reuse static-chain register if it is available . Otherwise , we use DI for i386 and R13 for x86-64 . We chose R13 since it has shorter encoding . Return : the regno of chosen register .


<s> bool LC3RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> static bool mep_legitimate_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { if ( GET_CODE ( x ) == SYMBOL_REF && ( reload_in_progress || reload_completed ) ) { char e = mep_section_tag ( x ) ; return ( e != 't' && e != 'b' ) ; } return 1 ; } </s>


<s>
MipsSubtarget
::
MipsSubtarget
(
const
std
::
string
&
TT
,
const
std
::
string
&
CPU
,
const
std
::
string
&
FS
,
bool
little
,
Reloc
::
Model
RM
)
:
MipsGenSubtargetInfo
(
TT
,
CPU
,
FS
)
,
MipsArchVersion
(
Mips32
)
,
MipsABI
(
UnknownABI
)
,
IsLittle
(
little
)
,
IsSingleFloat
(
false
)
,
IsFP64bit
(
false
)
,
IsGP64bit
(
false
)
,
HasVFPU
(
false
)
,
IsLinux
(
true
)
,
HasSEInReg
(
false
)
,
HasCondMov
(
false
)
,
HasMulDivAdd
(
false
)
,
HasMinMax
(
false
)
,
HasSwap
(
false
)
,
HasBitCount
(
false
)
,
InMips16Mode
(
false
)
,
HasDSP
(
false
)
,
HasDSPR2
(
false
)
,
IsAndroid
(
false
)
{
std
::
string
CPUName
=
CPU
;
if
(
CPUName
.
empty
(
)
)
CPUName
=
"mips32"
;
ParseSubtargetFeatures
(
CPUName
,
FS
)
;
InstrItins
=
getInstrItineraryForCPU
(
CPUName
)
;
if
(
MipsABI
==
UnknownABI
)
MipsABI
=
hasMips64
(
)
N64
:
O32
;
assert
(
(
(
!
hasMips64
(
)
&&
(
isABI_O32
(
)
||
isABI_EABI
(
)
)
)
||
(
hasMips64
(
)
&&
(
isABI_N32
(
)
||
isABI_N64
(
)
)
)
)
&&
"Invalid  Arch & ABI pair."
)
;
if
(
TT
.
find
(
"linux"
)
==
std
::
string
::
npos
)
IsLinux
=
false
;
UseSmallSection
=
!
IsLinux
&&
(
RM
==
Reloc
::
Static
)
;
}
</s>

This constructor initializes the data members to match that of the specified triple .

Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
"mips32"
Mips
Mips
Mips
Mips
Mips
"Invalid  Arch & ABI pair."
"linux"


<s> bool TGSICFGStructurizer :: prepare ( ) { bool Changed = false ; DEBUG ( dbgs ( ) << "TGSICFGStructurizer::prepare\n" ; ) ; orderBlocks ( FuncRep ) ; SmallVector < MachineBasicBlock * , DEFAULT_VEC_SLOTS > RetBlks ; for ( MachineLoopInfo :: iterator It = MLI -> begin ( ) , E = MLI -> end ( ) ; It != E ; ++ It ) { MachineLoop * LoopRep = ( * It ) ; MBBVector ExitingMBBs ; LoopRep -> getExitingBlocks ( ExitingMBBs ) ; if ( ExitingMBBs . size ( ) == 0 ) { MachineBasicBlock * DummyExitBlk = normalizeInfiniteLoopExit ( LoopRep ) ; if ( DummyExitBlk ) RetBlks . push_back ( DummyExitBlk ) ; } } for ( SmallVectorImpl < MachineBasicBlock * > :: const_iterator It = OrderedBlks . begin ( ) , E = OrderedBlks . end ( ) ; It != E ; ++ It ) { MachineBasicBlock * MBB = * It ; removeUnconditionalBranch ( MBB ) ; removeRedundantConditionalBranch ( MBB ) ; if ( isReturnBlock ( MBB ) ) { RetBlks . push_back ( MBB ) ; } assert ( MBB -> succ_size ( ) <= 2 ) ; } if ( RetBlks . size ( ) >= 2 ) { addDummyExitBlock ( RetBlks ) ; Changed = true ; } return Changed ; } </s>

prepare - Reset state and prepare for a new spill placement computation .


<s>
void
MetadataStreamerV3
::
verify
(
StringRef
HSAMetadataString
)
const
{
errs
(
)
<<
"AMDGPU HSA Metadata Parser Test: "
;
std
::
shared_ptr
<
msgpack
::
Node
>
FromHSAMetadataString
=
std
::
make_shared
<
msgpack
::
MapNode
>
(
)
;
yaml
::
Input
YIn
(
HSAMetadataString
)
;
YIn
>>
FromHSAMetadataString
;
if
(
YIn
.
error
(
)
)
{
errs
(
)
<<
"FAIL\n"
;
return
;
}
std
::
string
ToHSAMetadataString
;
raw_string_ostream
StrOS
(
ToHSAMetadataString
)
;
yaml
::
Output
YOut
(
StrOS
)
;
YOut
<<
FromHSAMetadataString
;
errs
(
)
<<
(
HSAMetadataString
==
StrOS
.
str
(
)
"PASS"
:
"FAIL"
)
<<
'\n'
;
if
(
HSAMetadataString
!=
ToHSAMetadataString
)
{
errs
(
)
<<
"Original input: "
<<
HSAMetadataString
<<
'\n'
<<
"Produced output: "
<<
StrOS
.
str
(
)
<<
'\n'
;
}
}
</s>

AMDGPU
"AMDGPU HSA Metadata Parser Test: "
"FAIL\n"
"PASS"
"FAIL"
"Original input: "
"Produced output: "


<s> Function * AMDGPUIntrinsicInfo :: getDeclaration ( Module * M , unsigned IntrID , ArrayRef < Type * > Tys ) const { FunctionType * FTy = getType ( M -> getContext ( ) , IntrID , Tys ) ; Function * F = cast < Function > ( M -> getOrInsertFunction ( getName ( IntrID , Tys ) , FTy ) ) ; AttributeList AS = getAttributes ( M -> getContext ( ) , static_cast < SIIntrinsic :: ID > ( IntrID ) ) ; F -> setAttributes ( AS ) ; return F ; } </s>

Create or insert an LLVM Function declaration for an intrinsic , and return it .


<s> static int sh_address_cost ( rtx x , machine_mode mode , addr_space_t as ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { if ( REG_P ( x ) && REGNO ( x ) == GBR_REG ) return 2 ; if ( REG_P ( x ) || GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == PRE_DEC ) return 1 ; if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , 0 ) ) && CONST_INT_P ( XEXP ( x , 1 ) ) ) { if ( REGNO ( XEXP ( x , 0 ) ) == GBR_REG && gbr_displacement ( XEXP ( x , 1 ) , mode ) ) return 2 ; const HOST_WIDE_INT offset = INTVAL ( XEXP ( x , 1 ) ) ; if ( offset == 0 ) return 1 ; if ( offset > 0 && offset <= sh_max_mov_insn_displacement ( mode , false ) ) return ( mode == HImode || mode == QImode ) ? 2 : 1 ; if ( TARGET_SH2A && offset > 0 && offset <= sh_max_mov_insn_displacement ( mode , true ) ) return 2 ; return 3 ; } if ( GET_CODE ( x ) == PLUS && ! CONSTANT_P ( XEXP ( x , 1 ) ) && ! TARGET_SHMEDIA ) return 3 ; return 10 ; } </s>

Compute the cost of an address . For the SH , all valid addresses are the same cost . Use a slightly higher cost for reg + reg addressing , since it increases pressure on r0 .


<s> unsigned AArch64TTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo ) { std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Ty ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( ISD == ISD :: SDIV && Opd2Info == TargetTransformInfo :: OK_UniformConstantValue && Opd2PropInfo == TargetTransformInfo :: OP_PowerOf2 ) { unsigned Cost = getArithmeticInstrCost ( Instruction :: Add , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Sub , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Select , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: AShr , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return Cost ; } switch ( ISD ) { default : return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: ADD : case ISD :: MUL : case ISD :: XOR : case ISD :: OR : case ISD :: AND : return 1 * LT . first ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .

AArch64 AArch64 ISD::SDIV ISD::ADD ISD::MUL ISD::XOR ISD::OR ISD::AND 1


<s> int bpf_core_get_sou_member_index ( ctf_container_ref ctfc , const tree node ) { if ( TREE_CODE ( node ) == FIELD_DECL ) { const tree container = DECL_CONTEXT ( node ) ; dw_die_ref die = lookup_type_die ( container ) ; if ( die == NULL ) return - 1 ; ctf_dtdef_ref dtd = ctf_dtd_lookup ( ctfc , die ) ; if ( dtd == NULL ) return - 1 ; unsigned int kind = CTF_V2_INFO_KIND ( dtd -> dtd_data . ctti_info ) ; if ( kind != CTF_K_STRUCT && kind != CTF_K_UNION ) return - 1 ; tree field = TYPE_FIELDS ( container ) ; int i = 0 ; ctf_dmdef_t * dmd ; for ( dmd = dtd -> dtd_u . dtu_members ; dmd != NULL ; dmd = ( ctf_dmdef_t * ) ctf_dmd_list_next ( dmd ) ) { bool field_has_btf = get_btf_id ( dmd -> dmd_type ) <= BTF_MAX_TYPE ; if ( field == node ) return field_has_btf ? i : - 1 ; if ( field_has_btf ) i ++ ; field = DECL_CHAIN ( field ) ; } } return - 1 ; } </s>

Return the 0-based index of the field NODE in its containing struct or union type .


<s>
bool
R600Packetizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
const
TargetInstrInfo
*
TII
=
Fn
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
MachineLoopInfo
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
R600PacketizerList
Packetizer
(
Fn
,
MLI
)
;
assert
(
Packetizer
.
getResourceTracker
(
)
&&
"Empty DFA table!"
)
;
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
MachineBasicBlock
::
iterator
End
=
MBB
->
end
(
)
;
MachineBasicBlock
::
iterator
MI
=
MBB
->
begin
(
)
;
while
(
MI
!=
End
)
{
if
(
MI
->
isKill
(
)
||
MI
->
getOpcode
(
)
==
AMDGPU
::
IMPLICIT_DEF
||
(
MI
->
getOpcode
(
)
==
AMDGPU
::
CF_ALU
&&
!
MI
->
getOperand
(
8
)
.
getImm
(
)
)
)
{
MachineBasicBlock
::
iterator
DeleteMI
=
MI
;
++
MI
;
MBB
->
erase
(
DeleteMI
)
;
End
=
MBB
->
end
(
)
;
continue
;
}
++
MI
;
}
}
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
unsigned
RemainingCount
=
MBB
->
size
(
)
;
for
(
MachineBasicBlock
::
iterator
RegionEnd
=
MBB
->
end
(
)
;
RegionEnd
!=
MBB
->
begin
(
)
;
)
{
MachineBasicBlock
::
iterator
I
=
RegionEnd
;
for
(
;
I
!=
MBB
->
begin
(
)
;
I
,
RemainingCount
)
{
if
(
TII
->
isSchedulingBoundary
(
std
::
prev
(
I
)
,
MBB
,
Fn
)
)
break
;
}
I
=
MBB
->
begin
(
)
;
if
(
I
==
RegionEnd
)
{
RegionEnd
=
std
::
prev
(
RegionEnd
)
;
RemainingCount
;
continue
;
}
if
(
I
==
std
::
prev
(
RegionEnd
)
)
{
RegionEnd
=
std
::
prev
(
RegionEnd
)
;
continue
;
}
Packetizer
.
PacketizeMIs
(
MBB
,
I
,
RegionEnd
)
;
RegionEnd
=
I
;
}
}
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool HexagonInstrInfo :: areMemAccessesTriviallyDisjoint ( MachineInstr * MIa , MachineInstr * MIb , AliasAnalysis * AA ) const { int OffsetA = 0 , OffsetB = 0 ; unsigned SizeA = 0 , SizeB = 0 ; if ( MIa -> hasUnmodeledSideEffects ( ) || MIb -> hasUnmodeledSideEffects ( ) || MIa -> hasOrderedMemoryRef ( ) || MIa -> hasOrderedMemoryRef ( ) ) return false ; if ( MIa -> mayLoad ( ) && ! isMemOp ( MIa ) && MIb -> mayLoad ( ) && ! isMemOp ( MIb ) ) return true ; unsigned BaseRegA = getBaseAndOffset ( MIa , OffsetA , SizeA ) ; if ( ! BaseRegA || ! SizeA ) return false ; unsigned BaseRegB = getBaseAndOffset ( MIb , OffsetB , SizeB ) ; if ( ! BaseRegB || ! SizeB ) return false ; if ( BaseRegA != BaseRegB ) return false ; if ( OffsetA > OffsetB ) { uint64_t offDiff = ( uint64_t ) ( ( int64_t ) OffsetA - ( int64_t ) OffsetB ) ; return ( SizeB <= offDiff ) ; } else if ( OffsetA < OffsetB ) { uint64_t offDiff = ( uint64_t ) ( ( int64_t ) OffsetB - ( int64_t ) OffsetA ) ; return ( SizeA <= offDiff ) ; } return false ; } </s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> bool toc_relative_expr_p ( const_rtx op , bool strict ) { if ( ! TARGET_TOC ) return false ; if ( TARGET_CMODEL != CMODEL_SMALL ) { if ( strict && ! ( GET_CODE ( op ) == LO_SUM && REG_P ( XEXP ( op , 0 ) ) && INT_REG_OK_FOR_BASE_P ( XEXP ( op , 0 ) , strict ) ) ) return false ; if ( GET_CODE ( op ) == LO_SUM ) op = XEXP ( op , 1 ) ; } tocrel_base = op ; tocrel_offset = const0_rtx ; if ( GET_CODE ( op ) == PLUS && add_cint_operand ( XEXP ( op , 1 ) , GET_MODE ( op ) ) ) { tocrel_base = XEXP ( op , 0 ) ; tocrel_offset = XEXP ( op , 1 ) ; } return ( GET_CODE ( tocrel_base ) == UNSPEC && XINT ( tocrel_base , 1 ) == UNSPEC_TOCREL ) ; } </s>

Return true if OP is a toc pointer relative address ( the output of create_TOC_reference ) . If STRICT , do not match high part or non-split -mcmodel=large/medium toc pointer relative addresses .


<s> void HexagonTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s> void OR1KInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool isMem ( ) const override { return false ; } </s>


"JIT relocation model must be set to static or default!"


<s> static bool is_microcoded_insn ( rtx_insn * insn ) { if ( ! insn || ! NONDEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; if ( rs6000_cpu_attr == CPU_CELL ) return get_attr_cell_micro ( insn ) == CELL_MICRO_ALWAYS ; if ( rs6000_sched_groups && ( rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5 ) ) { enum attr_type type = get_attr_type ( insn ) ; if ( ( type == TYPE_LOAD && get_attr_update ( insn ) == UPDATE_YES && get_attr_sign_extend ( insn ) == SIGN_EXTEND_YES ) || ( ( type == TYPE_LOAD || type == TYPE_STORE ) && get_attr_update ( insn ) == UPDATE_YES && get_attr_indexed ( insn ) == INDEXED_YES ) || type == TYPE_MFCR ) return true ; } return false ; } </s>

The function returns a true if INSN is microcoded . Return false otherwise .


<s> void R600PassConfig :: addPreEmitPass ( ) { addPass ( createAMDGPUCFGStructurizerPass ( ) ) ; addPass ( createR600ExpandSpecialInstrsPass ( ) ) ; addPass ( & FinalizeMachineBundlesID ) ; addPass ( createR600Packetizer ( ) ) ; addPass ( createR600ControlFlowFinalizer ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
static
void
nvptx_write_function_decl
(
std
::
stringstream
&
s
,
const
char
*
name
,
const_tree
decl
)
{
tree
fntype
=
TREE_TYPE
(
decl
)
;
tree
result_type
=
TREE_TYPE
(
fntype
)
;
tree
args
=
TYPE_ARG_TYPES
(
fntype
)
;
tree
attrs
=
DECL_ATTRIBUTES
(
decl
)
;
bool
kernel
=
write_as_kernel
(
attrs
)
;
bool
is_main
=
strcmp
(
name
,
"main"
)
==
0
;
bool
args_from_decl
=
false
;
if
(
args
==
0
)
{
args
=
DECL_ARGUMENTS
(
decl
)
;
args_from_decl
=
true
;
}
if
(
DECL_EXTERNAL
(
decl
)
)
s
<<
".extern "
;
else
if
(
TREE_PUBLIC
(
decl
)
)
s
<<
".visible "
;
if
(
kernel
)
s
<<
".entry "
;
else
s
<<
".func "
;
bool
return_in_mem
=
false
;
if
(
TYPE_MODE
(
result_type
)
!=
VOIDmode
)
{
machine_mode
mode
=
TYPE_MODE
(
result_type
)
;
if
(
!
RETURN_IN_REG_P
(
mode
)
)
return_in_mem
=
true
;
else
{
mode
=
arg_promotion
(
mode
)
;
s
<<
"(.param"
<<
nvptx_ptx_type_from_mode
(
mode
,
false
)
<<
" %out_retval)"
;
}
}
if
(
name
[
0
]
==
'*'
)
s
<<
(
name
+
1
)
;
else
s
<<
name
;
if
(
(
args
!=
NULL_TREE
&&
!
(
TREE_CODE
(
args
)
==
TREE_LIST
&&
TREE_VALUE
(
args
)
==
void_type_node
)
)
||
is_main
||
return_in_mem
||
DECL_STATIC_CHAIN
(
decl
)
)
{
s
<<
"("
;
int
i
=
0
;
bool
any_args
=
false
;
if
(
return_in_mem
)
{
s
<<
".param.u"
<<
GET_MODE_BITSIZE
(
Pmode
)
<<
" %in_ar1"
;
i
++
;
}
while
(
args
!=
NULL_TREE
)
{
tree
type
=
args_from_decl
TREE_TYPE
(
args
)
:
TREE_VALUE
(
args
)
;
machine_mode
mode
=
TYPE_MODE
(
type
)
;
if
(
mode
!=
VOIDmode
)
{
i
=
write_one_arg
(
s
,
type
,
i
,
mode
,
TYPE_ARG_TYPES
(
fntype
)
==
0
)
;
any_args
=
true
;
i
++
;
}
args
=
TREE_CHAIN
(
args
)
;
}
if
(
stdarg_p
(
fntype
)
)
{
gcc_assert
(
i
>
0
)
;
s
<<
", .param.u"
<<
GET_MODE_BITSIZE
(
Pmode
)
<<
" %in_argp"
;
}
if
(
DECL_STATIC_CHAIN
(
decl
)
)
{
if
(
i
>
0
)
s
<<
", "
;
s
<<
".reg.u"
<<
GET_MODE_BITSIZE
(
Pmode
)
<<
reg_names
[
STATIC_CHAIN_REGNUM
]
;
}
if
(
!
any_args
&&
is_main
)
s
<<
".param.u32 %argc, .param.u"
<<
GET_MODE_BITSIZE
(
Pmode
)
<<
" %argv"
;
s
<<
")"
;
}
}
</s>

Write a function decl for DECL to S , where NAME is the name to be used .


<s> static const char * detect_caches_amd ( unsigned max_ext_level ) { unsigned eax , ebx , ecx , edx ; struct cache_desc level1 , level2 = { 0 , 0 , 0 } ; if ( max_ext_level < 0x80000005 ) return "" ; __cpuid ( 0x80000005 , eax , ebx , ecx , edx ) ; level1 . sizekb = ( ecx >> 24 ) & 0xff ; level1 . assoc = ( ecx >> 16 ) & 0xff ; level1 . line = ecx & 0xff ; if ( max_ext_level >= 0x80000006 ) detect_l2_cache ( & level2 ) ; return describe_cache ( level1 , level2 ) ; } </s>

Returns the description of caches for an AMD processor .


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


"Legal fp imm: materialize 0 using the zero register\n"

Returns true if the target can instruction select the specified FP immediate natively .


<s> bool isTargetEHABICompatible ( ) const { return ( TargetTriple . getEnvironment ( ) == Triple :: EABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: MuslEABI || TargetTriple . getEnvironment ( ) == Triple :: EABIHF || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF || isTargetAndroid ( ) ) && ! isTargetDarwin ( ) && ! isTargetWindows ( ) ; } </s>

Tests whether the target supports the EHABI exception handling standard .


<s> bool HexagonInstrInfo :: isIndirectCall ( const MachineInstr * MI ) const { switch ( MI -> getOpcode ( ) ) { case Hexagon :: J2_callr : case Hexagon :: J2_callrf : case Hexagon :: J2_callrt : return true ; } return false ; } </s>

Return true if the callsite is an indirect call .


<s> static void push_minipool_barrier ( rtx insn , HOST_WIDE_INT address ) { Mfix * fix = ( Mfix * ) obstack_alloc ( & minipool_obstack , sizeof ( * fix ) ) ; fix -> insn = insn ; fix -> address = address ; fix -> next = NULL ; if ( minipool_fix_head != NULL ) minipool_fix_tail -> next = fix ; else minipool_fix_head = fix ; minipool_fix_tail = fix ; } </s>

Record that there is a natural barrier in the insn stream at ADDRESS .


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
READ_REGISTER
:
ExpandREAD_REGISTER
(
N
,
Results
,
DAG
)
;
break
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
case
ISD
::
SHL
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SREM
:
case
ISD
::
UREM
:
Res
=
LowerREM
(
N
,
DAG
)
;
break
;
case
ISD
::
SDIVREM
:
case
ISD
::
UDIVREM
:
Res
=
LowerDivRem
(
SDValue
(
N
,
0
)
,
DAG
)
;
assert
(
Res
.
getNumOperands
(
)
==
2
&&
"DivRem needs two values"
)
;
Results
.
push_back
(
Res
.
getValue
(
0
)
)
;
Results
.
push_back
(
Res
.
getValue
(
1
)
)
;
return
;
case
ISD
::
READCYCLECOUNTER
:
ReplaceREADCYCLECOUNTER
(
N
,
Results
,
DAG
,
Subtarget
)
;
return
;
case
ISD
::
UDIV
:
case
ISD
::
SDIV
:
assert
(
Subtarget
->
isTargetWindows
(
)
&&
"can only expand DIV on Windows"
)
;
return
ExpandDIV_Windows
(
SDValue
(
N
,
0
)
,
DAG
,
N
->
getOpcode
(
)
==
ISD
::
SDIV
,
Results
)
;
case
ISD
::
ATOMIC_CMP_SWAP
:
ReplaceCMP_SWAP_64Results
(
N
,
Results
,
DAG
)
;
return
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
ReplaceLongIntrinsic
(
N
,
Results
,
DAG
)
;
case
ISD
::
ABS
:
lowerABS
(
N
,
Results
,
DAG
)
;
return
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

ARM
ARM
"Don't know how to custom expand this!"
ISD::READ_REGISTER
ISD::BITCAST
ISD::SRL
ISD::SRA
ISD::SHL
ISD::SREM
ISD::UREM
ISD::SDIVREM
ISD::UDIVREM
0
2
"DivRem needs two values"
0
1
ISD::READCYCLECOUNTER
ISD::UDIV
ISD::SDIV
"can only expand DIV on Windows"
0
ISD::SDIV
ISD::ATOMIC_CMP_SWAP
ISD::INTRINSIC_WO_CHAIN
ISD::ABS


<s> int s390_const_double_ok_for_constraint_p ( rtx value , int c , const char * str ) { gcc_assert ( c == str [ 0 ] ) ; switch ( str [ 0 ] ) { case 'G' : return ( GET_MODE_CLASS ( GET_MODE ( value ) ) == MODE_FLOAT && value == CONST0_RTX ( GET_MODE ( value ) ) ) ; default : return 0 ; } } </s>

Return true if VALUE matches the constraint STR .


<s> void AnalyzeCallOperands ( const SmallVectorImpl < ISD :: OutputArg > & Outs , CCAssignFn Fn , std :: vector < TargetLowering :: ArgListEntry > & FuncArgs , const SDNode * CallNode ) { PreAnalyzeCallOperands ( Outs , FuncArgs , CallNode ) ; CCState :: AnalyzeCallOperands ( Outs , Fn ) ; OriginalArgWasF128 . clear ( ) ; OriginalArgWasFloat . clear ( ) ; CallOperandIsFixed . clear ( ) ; } </s>

AnalyzeCallOperands - Same as above except it takes vectors of types and argument flags .


<s> virtual bool isBranchWithImm ( unsigned Opc ) const { return false ; } </s>

isBranchWithImm - Return true if the branch contains an immediate operand (


<s> MCInstrDesc const & HexagonMCInstrInfo :: getDesc ( MCInstrInfo const & MCII , MCInst const & MCI ) { return MCII . get ( MCI . getOpcode ( ) ) ; } </s>

Returns the target instruction descriptor of this MachineInstr .


<s> static bool scalar_move_insn_p ( rtx_insn * rinsn ) { return get_attr_type ( rinsn ) == TYPE_VIMOVXV || get_attr_type ( rinsn ) == TYPE_VFMOVFV ; } </s>

Return true if the instruction is scalar move instruction .


<s> void Mips16FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( STI . getInstrInfo ( ) ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( ! StackSize ) return ; if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: Move32R16 ) , Mips :: SP ) . addReg ( Mips :: S0 ) ; TII . restoreFrame ( Mips :: SP , StackSize , MBB , MBBI ) ; } </s>

Mips Mips Mips Mips Mips::Move32R16 Mips::SP Mips::S0 Mips::SP


<s> unsigned AAPInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { default : return MI . getDesc ( ) . getSize ( ) ; case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return 0 ; case TargetOpcode :: INLINEASM : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const auto & TM = static_cast < const AAPTargetMachine & > ( MF . getTarget ( ) ) ; return getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> static bool isStore ( int Opcode ) { return Opcode == ARC :: ST_rs9 || Opcode == ARC :: STH_rs9 || Opcode == ARC :: STB_rs9 ; } </s>

Returns true if this recipe is a store .


<s> void GCNPassConfig :: addPreEmitPass ( ) { addPass ( & PostRAHazardRecognizerID ) ; addPass ( createSIMemoryLegalizerPass ( ) ) ; addPass ( createSIInsertWaitcntsPass ( ) ) ; addPass ( createSIShrinkInstructionsPass ( ) ) ; addPass ( & SIInsertSkipsPassID ) ; addPass ( createSIDebuggerInsertNopsPass ( ) ) ; addPass ( & BranchRelaxationPassID ) ; } </s>


<s> bool shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) override { switch ( ( Sparc :: Fixups ) Fixup . getKind ( ) ) { default : return false ; case Sparc :: fixup_sparc_wplt30 : if ( Target . getSymA ( ) -> getSymbol ( ) . isTemporary ( ) ) return false ; case Sparc :: fixup_sparc_tls_gd_hi22 : case Sparc :: fixup_sparc_tls_gd_lo10 : case Sparc :: fixup_sparc_tls_gd_add : case Sparc :: fixup_sparc_tls_gd_call : case Sparc :: fixup_sparc_tls_ldm_hi22 : case Sparc :: fixup_sparc_tls_ldm_lo10 : case Sparc :: fixup_sparc_tls_ldm_add : case Sparc :: fixup_sparc_tls_ldm_call : case Sparc :: fixup_sparc_tls_ldo_hix22 : case Sparc :: fixup_sparc_tls_ldo_lox10 : case Sparc :: fixup_sparc_tls_ldo_add : case Sparc :: fixup_sparc_tls_ie_hi22 : case Sparc :: fixup_sparc_tls_ie_lo10 : case Sparc :: fixup_sparc_tls_ie_ld : case Sparc :: fixup_sparc_tls_ie_ldx : case Sparc :: fixup_sparc_tls_ie_add : case Sparc :: fixup_sparc_tls_le_hix22 : case Sparc :: fixup_sparc_tls_le_lox10 : return true ; } } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> bool MipsAbiFlags :: merge ( const Input & pInput , MipsAbiFlags & oldFlags , const MipsAbiFlags & newFlags ) { if ( oldFlags . m_IsaLevel == 0 ) { oldFlags = newFlags ; return true ; } if ( newFlags . m_IsaLevel > oldFlags . m_IsaLevel ) oldFlags . m_IsaLevel = newFlags . m_IsaLevel ; oldFlags . m_IsaRev = std :: max ( oldFlags . m_IsaRev , newFlags . m_IsaRev ) ; oldFlags . m_GprSize = std :: max ( oldFlags . m_GprSize , newFlags . m_GprSize ) ; oldFlags . m_Cpr1Size = std :: max ( oldFlags . m_Cpr1Size , newFlags . m_Cpr1Size ) ; oldFlags . m_Cpr2Size = std :: max ( oldFlags . m_Cpr2Size , newFlags . m_Cpr2Size ) ; oldFlags . m_Ases |= newFlags . m_Ases ; oldFlags . m_Flags1 |= newFlags . m_Flags1 ; if ( oldFlags . m_FpAbi == newFlags . m_FpAbi ) return true ; if ( isFpGreater ( newFlags . m_FpAbi , oldFlags . m_FpAbi ) ) { oldFlags . m_FpAbi = newFlags . m_FpAbi ; return true ; } if ( isFpGreater ( oldFlags . m_FpAbi , newFlags . m_FpAbi ) ) return true ; llvm :: StringRef oldAbiName = getFpAbiName ( oldFlags . m_FpAbi ) ; llvm :: StringRef newAbiName = getFpAbiName ( newFlags . m_FpAbi ) ; warning ( diag :: warn_Mips_fp_abi_incompatible ) << oldAbiName << newAbiName << pInput . name ( ) ; return false ; } </s>


<s>
void
PPCHazardRecognizer970
::
EmitInstruction
(
SUnit
*
SU
)
{
const
SDNode
*
Node
=
SU
->
getNode
(
)
->
getFlaggedMachineNode
(
)
;
bool
isFirst
,
isSingle
,
isCracked
,
isLoad
,
isStore
;
PPCII
::
PPC970_Unit
InstrType
=
GetInstrType
(
Node
->
getOpcode
(
)
,
isFirst
,
isSingle
,
isCracked
,
isLoad
,
isStore
)
;
if
(
InstrType
==
PPCII
::
PPC970_Pseudo
)
return
;
unsigned
Opcode
=
Node
->
getMachineOpcode
(
)
;
if
(
Opcode
==
PPC
::
MTCTR
)
HasCTRSet
=
true
;
if
(
isStore
)
{
unsigned
ThisStoreSize
;
switch
(
Opcode
)
{
default
:
llvm_unreachable
(
"Unknown store instruction!"
)
;
case
PPC
::
STB
:
case
PPC
::
STB8
:
case
PPC
::
STBU
:
case
PPC
::
STBU8
:
case
PPC
::
STBX
:
case
PPC
::
STBX8
:
case
PPC
::
STVEBX
:
ThisStoreSize
=
1
;
break
;
case
PPC
::
STH
:
case
PPC
::
STH8
:
case
PPC
::
STHU
:
case
PPC
::
STHU8
:
case
PPC
::
STHX
:
case
PPC
::
STHX8
:
case
PPC
::
STVEHX
:
case
PPC
::
STHBRX
:
ThisStoreSize
=
2
;
break
;
case
PPC
::
STFS
:
case
PPC
::
STFSU
:
case
PPC
::
STFSX
:
case
PPC
::
STWX
:
case
PPC
::
STWX8
:
case
PPC
::
STWUX
:
case
PPC
::
STW
:
case
PPC
::
STW8
:
case
PPC
::
STWU
:
case
PPC
::
STWU8
:
case
PPC
::
STVEWX
:
case
PPC
::
STFIWX
:
case
PPC
::
STWBRX
:
ThisStoreSize
=
4
;
break
;
case
PPC
::
STD_32
:
case
PPC
::
STDX_32
:
case
PPC
::
STD
:
case
PPC
::
STDU
:
case
PPC
::
STFD
:
case
PPC
::
STFDX
:
case
PPC
::
STDX
:
case
PPC
::
STDUX
:
ThisStoreSize
=
8
;
break
;
case
PPC
::
STVX
:
case
PPC
::
STVXL
:
ThisStoreSize
=
16
;
break
;
}
StoreSize
[
NumStores
]
=
ThisStoreSize
;
StorePtr1
[
NumStores
]
=
Node
->
getOperand
(
1
)
;
StorePtr2
[
NumStores
]
=
Node
->
getOperand
(
2
)
;
++
NumStores
;
}
if
(
InstrType
==
PPCII
::
PPC970_BRU
||
isSingle
)
NumIssued
=
4
;
++
NumIssued
;
if
(
isCracked
)
++
NumIssued
;
if
(
NumIssued
==
5
)
EndDispatchGroup
(
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> formatted_raw_ostream & getOStream ( ) { return OS ; } </s>

getOStream - Get the raw output stream into the graph file .


<s> static rtx s390_find_execute ( struct constant_pool * pool , rtx insn ) { struct constant * c ; for ( c = pool -> execute ; c != NULL ; c = c -> next ) if ( INSN_UID ( insn ) == INSN_UID ( c -> value ) ) break ; gcc_assert ( c ) ; return s390_pool_offset ( pool , gen_rtx_LABEL_REF ( Pmode , c -> label ) ) ; } </s>

Find execute target for INSN in the constant pool POOL . Return an RTX describing the distance from the start of the pool to the location of the execute target .


<s> static tree arm_mve_type_for_scalar_type ( tree eltype ) { for ( unsigned int i = 0 ; i < __TYPE_FINAL ; ++ i ) if ( arm_simd_types [ i ] . eltype == eltype && GET_MODE_SIZE ( arm_simd_types [ i ] . mode ) == 16 ) return arm_simd_types [ i ] . itype ; gcc_unreachable ( ) ; } </s>

Return the MVE abi type with element of type TYPE .


<s> inline hashval_t mips_lo_sum_offset_hasher :: hash ( const value_type * entry ) { return mips_hash_base ( entry -> base ) ; } </s>

Hash function for builtin functions with up to 3 arguments and a return type .


<s> void changeSection ( MCSection * Section , const MCExpr * Subsection ) override { } </s>

Update streamer for a new active section .


<s> bool MMIXFrameLowering :: hasFP ( const MachineFunction & MF ) const { return true ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
void
HSAILInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
unsigned
int
Opc
=
0
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
DebugLoc
DL
;
unsigned
BT
;
switch
(
RC
->
getID
(
)
)
{
default
:
llvm_unreachable
(
"unrecognized TargetRegisterClass"
)
;
break
;
case
HSAIL
::
GPR32RegClassID
:
Opc
=
HSAIL
::
ST_U32
;
BT
=
BRIG_TYPE_U32
;
break
;
case
HSAIL
::
GPR64RegClassID
:
Opc
=
HSAIL
::
ST_U64
;
BT
=
BRIG_TYPE_U64
;
break
;
case
HSAIL
::
CRRegClassID
:
{
HSAILMachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
HSAILMachineFunctionInfo
>
(
)
;
MFI
->
setHasSpilledCRs
(
)
;
Opc
=
HSAIL
::
SPILL_B1
;
BT
=
BRIG_TYPE_B1
;
break
;
}
}
if
(
MI
!=
MBB
.
end
(
)
)
{
DL
=
MI
->
getDebugLoc
(
)
;
}
switch
(
RC
->
getID
(
)
)
{
default
:
llvm_unreachable
(
"unrecognized TargetRegisterClass"
)
;
break
;
case
HSAIL
::
CRRegClassID
:
case
HSAIL
::
GPR32RegClassID
:
case
HSAIL
::
GPR64RegClassID
:
{
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FrameIndex
)
,
MachineMemOperand
::
MOStore
,
MFI
.
getObjectSize
(
FrameIndex
)
,
MFI
.
getObjectAlignment
(
FrameIndex
)
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIndex
)
.
addReg
(
HSAIL
::
NoRegister
)
.
addImm
(
0
)
.
addImm
(
BT
)
.
addImm
(
HSAILAS
::
SPILL_ADDRESS
)
.
addImm
(
MMO
->
getAlignment
(
)
)
.
addMemOperand
(
MMO
)
;
break
;
}
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel , MCContext & Ctx ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { unsigned Idx = IsLittleEndian ? i : 3 - i ; Data [ Offset + Idx ] |= uint8_t ( ( Value >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static tree nios2_ftype ( enum nios2_ftcode ftcode ) { static tree types [ ( int ) N2_FTYPE_MAX ] ; tree N2_TYPE_SF = float_type_node ; tree N2_TYPE_DF = double_type_node ; tree N2_TYPE_SI = integer_type_node ; tree N2_TYPE_UI = unsigned_type_node ; tree N2_TYPE_VOID = void_type_node ; static const_tree N2_TYPE_CVPTR , N2_TYPE_VPTR ; if ( ! N2_TYPE_CVPTR ) { N2_TYPE_CVPTR = build_pointer_type ( build_qualified_type ( void_type_node , ( TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE ) ) ) ; N2_TYPE_VPTR = build_pointer_type ( build_qualified_type ( void_type_node , TYPE_QUAL_VOLATILE ) ) ; } if ( types [ ( int ) ftcode ] == NULL_TREE ) switch ( ftcode ) { case N2_FTYPE_OP ## N ARGS : \ types [ ( int ) ftcode ] \ = build_function_type_list ( N2_FTYPE_ARGS ## N ARGS , NULL_TREE ) ; \ break ; N2_FTYPES default : gcc_unreachable ( ) ; } return types [ ( int ) ftcode ] ; } </s>

Return the tree function type , based on the ftcode .


<s>
void
SIFrameLowering
::
determineCalleeSaves
(
MachineFunction
&
MF
,
BitVector
&
SavedVGPRs
,
RegScavenger
*
RS
)
const
{
TargetFrameLowering
::
determineCalleeSaves
(
MF
,
SavedVGPRs
,
RS
)
;
SIMachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
SIMachineFunctionInfo
>
(
)
;
if
(
MFI
->
isEntryFunction
(
)
)
return
;
MachineFrameInfo
&
FrameInfo
=
MF
.
getFrameInfo
(
)
;
const
GCNSubtarget
&
ST
=
MF
.
getSubtarget
<
GCNSubtarget
>
(
)
;
const
SIRegisterInfo
*
TRI
=
ST
.
getRegisterInfo
(
)
;
SavedVGPRs
.
clearBitsNotInMask
(
TRI
->
getAllVectorRegMask
(
)
)
;
if
(
!
ST
.
hasGFX90AInsts
(
)
)
SavedVGPRs
.
clearBitsInMask
(
TRI
->
getAllAGPRRegMask
(
)
)
;
const
bool
WillHaveFP
=
FrameInfo
.
hasCalls
(
)
&&
(
SavedVGPRs
.
any
(
)
||
!
allStackObjectsAreDead
(
FrameInfo
)
)
;
for
(
auto
SSpill
:
MFI
->
getSGPRSpillVGPRs
(
)
)
SavedVGPRs
.
reset
(
SSpill
.
VGPR
)
;
LivePhysRegs
LiveRegs
;
LiveRegs
.
init
(
*
TRI
)
;
if
(
WillHaveFP
||
hasFP
(
MF
)
)
{
assert
(
!
MFI
->
SGPRForFPSaveRestoreCopy
&&
!
MFI
->
FramePointerSaveIndex
&&
"Re-reserving spill slot for FP"
)
;
getVGPRSpillLaneOrTempRegister
(
MF
,
LiveRegs
,
MFI
->
SGPRForFPSaveRestoreCopy
,
MFI
->
FramePointerSaveIndex
,
true
)
;
}
if
(
TRI
->
hasBasePointer
(
MF
)
)
{
if
(
MFI
->
SGPRForFPSaveRestoreCopy
)
LiveRegs
.
addReg
(
MFI
->
SGPRForFPSaveRestoreCopy
)
;
assert
(
!
MFI
->
SGPRForBPSaveRestoreCopy
&&
!
MFI
->
BasePointerSaveIndex
&&
"Re-reserving spill slot for BP"
)
;
getVGPRSpillLaneOrTempRegister
(
MF
,
LiveRegs
,
MFI
->
SGPRForBPSaveRestoreCopy
,
MFI
->
BasePointerSaveIndex
,
false
)
;
}
}
</s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .

AMDGPU
SI
SI
SI
SI
"Re-reserving spill slot for FP"
"Re-reserving spill slot for BP"


<s>
bool
MSP430BSel
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
MF
=
&
mf
;
TII
=
static_cast
<
const
MSP430InstrInfo
*
>
(
MF
->
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
if
(
!
BranchSelectEnabled
)
return
false
;
DEBUG
(
dbgs
(
)
<<
"\n********** "
<<
getPassName
(
)
<<
" **********\n"
)
;
OffsetVector
BlockOffsets
;
unsigned
FunctionSize
=
measureFunction
(
BlockOffsets
)
;
if
(
isInRage
(
FunctionSize
)
)
{
return
false
;
}
bool
MadeChange
=
false
;
while
(
expandBranches
(
BlockOffsets
)
)
MadeChange
=
true
;
return
MadeChange
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> void GCNPassConfig :: addMachineSSAOptimization ( ) { TargetPassConfig :: addMachineSSAOptimization ( ) ; addPass ( & SIFoldOperandsID ) ; addPass ( & DeadMachineInstructionElimID ) ; } </s>

Methods with trivial inline returns are convenient points in the common codegen pass pipeline where targets may insert passes .


<s> int num_insns_constant ( rtx op , machine_mode mode ) { HOST_WIDE_INT low , high ; switch ( GET_CODE ( op ) ) { case CONST_INT : if ( ( INTVAL ( op ) >> 31 ) != 0 && ( INTVAL ( op ) >> 31 ) != - 1 && mask64_operand ( op , mode ) ) return 2 ; else return num_insns_constant_wide ( INTVAL ( op ) ) ; case CONST_WIDE_INT : { int i ; int ins = CONST_WIDE_INT_NUNITS ( op ) - 1 ; for ( i = 0 ; i < CONST_WIDE_INT_NUNITS ( op ) ; i ++ ) ins += num_insns_constant_wide ( CONST_WIDE_INT_ELT ( op , i ) ) ; return ins ; } case CONST_DOUBLE : if ( mode == SFmode || mode == SDmode ) { long l ; REAL_VALUE_TYPE rv ; REAL_VALUE_FROM_CONST_DOUBLE ( rv , op ) ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) REAL_VALUE_TO_TARGET_DECIMAL32 ( rv , l ) ; else REAL_VALUE_TO_TARGET_SINGLE ( rv , l ) ; return num_insns_constant_wide ( ( HOST_WIDE_INT ) l ) ; } long l [ 2 ] ; REAL_VALUE_TYPE rv ; REAL_VALUE_FROM_CONST_DOUBLE ( rv , op ) ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) REAL_VALUE_TO_TARGET_DECIMAL64 ( rv , l ) ; else REAL_VALUE_TO_TARGET_DOUBLE ( rv , l ) ; high = l [ WORDS_BIG_ENDIAN == 0 ] ; low = l [ WORDS_BIG_ENDIAN != 0 ] ; if ( TARGET_32BIT ) return ( num_insns_constant_wide ( low ) + num_insns_constant_wide ( high ) ) ; else { if ( ( high == 0 && low >= 0 ) || ( high == - 1 && low < 0 ) ) return num_insns_constant_wide ( low ) ; else if ( mask64_operand ( op , mode ) ) return 2 ; else if ( low == 0 ) return num_insns_constant_wide ( high ) + 1 ; else return ( num_insns_constant_wide ( high ) + num_insns_constant_wide ( low ) + 1 ) ; } default : gcc_unreachable ( ) ; } } </s>

Return the number of instructions it takes to form a constant in as many gprs are needed for MODE .


ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> const char * HexagonTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( HexagonISD :: NodeType ) Opcode ) { case HexagonISD :: ADDC : return "HexagonISD::ADDC" ; case HexagonISD :: SUBC : return "HexagonISD::SUBC" ; case HexagonISD :: ALLOCA : return "HexagonISD::ALLOCA" ; case HexagonISD :: AT_GOT : return "HexagonISD::AT_GOT" ; case HexagonISD :: AT_PCREL : return "HexagonISD::AT_PCREL" ; case HexagonISD :: BARRIER : return "HexagonISD::BARRIER" ; case HexagonISD :: CALL : return "HexagonISD::CALL" ; case HexagonISD :: CALLnr : return "HexagonISD::CALLnr" ; case HexagonISD :: CALLR : return "HexagonISD::CALLR" ; case HexagonISD :: COMBINE : return "HexagonISD::COMBINE" ; case HexagonISD :: CONST32_GP : return "HexagonISD::CONST32_GP" ; case HexagonISD :: CONST32 : return "HexagonISD::CONST32" ; case HexagonISD :: CP : return "HexagonISD::CP" ; case HexagonISD :: DCFETCH : return "HexagonISD::DCFETCH" ; case HexagonISD :: EH_RETURN : return "HexagonISD::EH_RETURN" ; case HexagonISD :: TSTBIT : return "HexagonISD::TSTBIT" ; case HexagonISD :: EXTRACTU : return "HexagonISD::EXTRACTU" ; case HexagonISD :: INSERT : return "HexagonISD::INSERT" ; case HexagonISD :: JT : return "HexagonISD::JT" ; case HexagonISD :: RET_FLAG : return "HexagonISD::RET_FLAG" ; case HexagonISD :: TC_RETURN : return "HexagonISD::TC_RETURN" ; case HexagonISD :: VASL : return "HexagonISD::VASL" ; case HexagonISD :: VASR : return "HexagonISD::VASR" ; case HexagonISD :: VLSR : return "HexagonISD::VLSR" ; case HexagonISD :: VEXTRACTW : return "HexagonISD::VEXTRACTW" ; case HexagonISD :: VINSERTW0 : return "HexagonISD::VINSERTW0" ; case HexagonISD :: VROR : return "HexagonISD::VROR" ; case HexagonISD :: READCYCLE : return "HexagonISD::READCYCLE" ; case HexagonISD :: PTRUE : return "HexagonISD::PTRUE" ; case HexagonISD :: PFALSE : return "HexagonISD::PFALSE" ; case HexagonISD :: D2P : return "HexagonISD::D2P" ; case HexagonISD :: P2D : return "HexagonISD::P2D" ; case HexagonISD :: V2Q : return "HexagonISD::V2Q" ; case HexagonISD :: Q2V : return "HexagonISD::Q2V" ; case HexagonISD :: QCAT : return "HexagonISD::QCAT" ; case HexagonISD :: QTRUE : return "HexagonISD::QTRUE" ; case HexagonISD :: QFALSE : return "HexagonISD::QFALSE" ; case HexagonISD :: TYPECAST : return "HexagonISD::TYPECAST" ; case HexagonISD :: VALIGN : return "HexagonISD::VALIGN" ; case HexagonISD :: VALIGNADDR : return "HexagonISD::VALIGNADDR" ; case HexagonISD :: VPACKL : return "HexagonISD::VPACKL" ; case HexagonISD :: VUNPACK : return "HexagonISD::VUNPACK" ; case HexagonISD :: VUNPACKU : return "HexagonISD::VUNPACKU" ; case HexagonISD :: ISEL : return "HexagonISD::ISEL" ; case HexagonISD :: OP_END : break ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

Hexagon Hexagon HexagonISD::NodeType HexagonISD::ADDC "HexagonISD::ADDC" HexagonISD::SUBC "HexagonISD::SUBC" HexagonISD::ALLOCA "HexagonISD::ALLOCA" HexagonISD::AT_GOT "HexagonISD::AT_GOT" HexagonISD::AT_PCREL "HexagonISD::AT_PCREL" HexagonISD::BARRIER "HexagonISD::BARRIER" HexagonISD::CALL "HexagonISD::CALL" HexagonISD::CALLnr "HexagonISD::CALLnr" HexagonISD::CALLR "HexagonISD::CALLR" HexagonISD::COMBINE "HexagonISD::COMBINE" HexagonISD::CONST32_GP "HexagonISD::CONST32_GP" HexagonISD::CONST32 "HexagonISD::CONST32" HexagonISD::CP "HexagonISD::CP" HexagonISD::DCFETCH "HexagonISD::DCFETCH" HexagonISD::EH_RETURN "HexagonISD::EH_RETURN" HexagonISD::TSTBIT "HexagonISD::TSTBIT" HexagonISD::EXTRACTU "HexagonISD::EXTRACTU" HexagonISD::INSERT "HexagonISD::INSERT" HexagonISD::JT "HexagonISD::JT" HexagonISD::RET_FLAG "HexagonISD::RET_FLAG" HexagonISD::TC_RETURN "HexagonISD::TC_RETURN" HexagonISD::VASL "HexagonISD::VASL" HexagonISD::VASR "HexagonISD::VASR" HexagonISD::VLSR "HexagonISD::VLSR" HexagonISD::VEXTRACTW "HexagonISD::VEXTRACTW" HexagonISD::VINSERTW0 "HexagonISD::VINSERTW0" HexagonISD::VROR "HexagonISD::VROR" HexagonISD::READCYCLE "HexagonISD::READCYCLE" HexagonISD::PTRUE "HexagonISD::PTRUE" HexagonISD::PFALSE "HexagonISD::PFALSE" HexagonISD::D2P "HexagonISD::D2P" HexagonISD::P2D "HexagonISD::P2D" HexagonISD::V2Q "HexagonISD::V2Q" HexagonISD::Q2V "HexagonISD::Q2V" HexagonISD::QCAT "HexagonISD::QCAT" HexagonISD::QTRUE "HexagonISD::QTRUE" HexagonISD::QFALSE "HexagonISD::QFALSE" HexagonISD::TYPECAST "HexagonISD::TYPECAST" HexagonISD::VALIGN "HexagonISD::VALIGN" HexagonISD::VALIGNADDR "HexagonISD::VALIGNADDR" HexagonISD::VPACKL "HexagonISD::VPACKL" HexagonISD::VUNPACK "HexagonISD::VUNPACK" HexagonISD::VUNPACKU "HexagonISD::VUNPACKU" HexagonISD::ISEL "HexagonISD::ISEL" HexagonISD::OP_END


<s> unsigned BPFMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) return MRI . getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; assert ( MO . isExpr ( ) ) ; const MCExpr * Expr = MO . getExpr ( ) ; assert ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) ; if ( MI . getOpcode ( ) == BPF :: JAL ) Fixups . push_back ( MCFixup :: create ( 0 , Expr , FK_SecRel_4 ) ) ; else if ( MI . getOpcode ( ) == BPF :: LD_imm64 ) Fixups . push_back ( MCFixup :: create ( 0 , Expr , FK_SecRel_8 ) ) ; else Fixups . push_back ( MCFixup :: create ( 0 , Expr , FK_PCRel_2 ) ) ; return 0 ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s>
CCAssignFn
*
ARMFastISel
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
Return
,
bool
isVarArg
)
{
switch
(
CC
)
{
default
:
report_fatal_error
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
if
(
Subtarget
->
hasVFP2
(
)
&&
!
isVarArg
)
{
if
(
!
Subtarget
->
isAAPCS_ABI
(
)
)
return
(
Return
RetFastCC_ARM_APCS
:
FastCC_ARM_APCS
)
;
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
}
LLVM_FALLTHROUGH
;
case
CallingConv
::
C
:
case
CallingConv
::
CXX_FAST_TLS
:
if
(
Subtarget
->
isAAPCS_ABI
(
)
)
{
if
(
Subtarget
->
hasVFP2
(
)
&&
TM
.
Options
.
FloatABIType
==
FloatABI
::
Hard
&&
!
isVarArg
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
else
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
}
else
{
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
}
case
CallingConv
::
ARM_AAPCS_VFP
:
case
CallingConv
::
Swift
:
if
(
!
isVarArg
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
LLVM_FALLTHROUGH
;
case
CallingConv
::
ARM_AAPCS
:
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
case
CallingConv
::
ARM_APCS
:
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
case
CallingConv
::
GHC
:
if
(
Return
)
report_fatal_error
(
"Can't return in GHC call convention"
)
;
else
return
CC_ARM_APCS_GHC
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .

ARM
ARM
"Unsupported calling convention"
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
"Can't return in GHC call convention"
ARM


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCRelaxableFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
{
assert
(
0
&&
"RelaxInstruction() is not implemented"
)
;
return
false
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .

TeeRISC
0
"RelaxInstruction() is not implemented"


<s> static rtx_insn * aarch64_speculation_clobber_sp ( ) { rtx sp = gen_rtx_REG ( DImode , SP_REGNUM ) ; rtx tracker = gen_rtx_REG ( DImode , SPECULATION_TRACKER_REGNUM ) ; rtx scratch = gen_rtx_REG ( DImode , SPECULATION_SCRATCH_REGNUM ) ; start_sequence ( ) ; emit_insn ( gen_rtx_SET ( scratch , sp ) ) ; emit_insn ( gen_anddi3 ( scratch , scratch , tracker ) ) ; emit_insn ( gen_rtx_SET ( sp , scratch ) ) ; rtx_insn * seq = get_insns ( ) ; end_sequence ( ) ; return seq ; } </s>

Generate a code sequence to clobber SP if speculating incorreclty .


<s> static bool ix86_function_ok_for_sibcall ( tree decl , tree exp ) { tree type , decl_or_type ; rtx a , b ; bool bind_global = decl && ! targetm . binds_local_p ( decl ) ; if ( cfun -> machine -> no_caller_saved_registers ) return false ; if ( ! TARGET_MACHO && ! TARGET_64BIT && flag_pic && flag_plt && bind_global ) return false ; if ( ix86_minimum_incoming_stack_boundary ( true ) < PREFERRED_STACK_BOUNDARY ) return false ; if ( decl ) { decl_or_type = decl ; type = TREE_TYPE ( decl ) ; } else { type = CALL_EXPR_FN ( exp ) ; type = TREE_TYPE ( type ) ; type = TREE_TYPE ( type ) ; decl_or_type = type ; } a = ix86_function_value ( TREE_TYPE ( exp ) , decl_or_type , false ) ; b = ix86_function_value ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) , cfun -> decl , false ) ; if ( STACK_REG_P ( a ) || STACK_REG_P ( b ) ) { if ( ! rtx_equal_p ( a , b ) ) return false ; } else if ( VOID_TYPE_P ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) ) ) ; else if ( ! rtx_equal_p ( a , b ) ) return false ; if ( TARGET_64BIT ) { if ( cfun -> machine -> call_abi == MS_ABI && ix86_function_type_abi ( type ) == SYSV_ABI ) return false ; } else { if ( ! decl || ( bind_global && flag_pic && ! flag_plt ) || ( TARGET_DLLIMPORT_DECL_ATTRIBUTES && DECL_DLLIMPORT_P ( decl ) ) ) { if ( ix86_function_regparm ( type , NULL ) >= 3 && ! cfun -> machine -> arg_reg_available ) return false ; } } return true ; } </s>

Decide whether we can make a sibling call to a function . DECL is the declaration of the function being targeted by the call and EXP is the CALL_EXPR representing the call .


<s> bool shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const override { return true ; } </s>

Returns true if it is beneficial to convert a load of a constant to just the constant itself .


<s> bool SIRegisterInfo :: needsFrameBaseReg ( MachineInstr * MI , int64_t Offset ) const { if ( ! SIInstrInfo :: isMUBUF ( * MI ) && ! SIInstrInfo :: isFLATScratch ( * MI ) ) return false ; int64_t FullOffset = Offset + getScratchInstrOffset ( MI ) ; if ( SIInstrInfo :: isMUBUF ( * MI ) ) return ! SIInstrInfo :: isLegalMUBUFImmOffset ( FullOffset ) ; const SIInstrInfo * TII = ST . getInstrInfo ( ) ; return ! TII -> isLegalFLATOffset ( FullOffset , AMDGPUAS :: PRIVATE_ADDRESS , SIInstrFlags :: FlatScratch ) ; } </s>

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .

AMDGPU SI SI SI SI SI SI AMDGPU SIInstrFlags::FlatScratch


<s>
rtx
iq2000_legitimize_address
(
rtx
xinsn
,
rtx
old_x
ATTRIBUTE_UNUSED
,
machine_mode
mode
)
{
if
(
TARGET_DEBUG_B_MODE
)
{
GO_PRINTF
(
"\n========== LEGITIMIZE_ADDRESS\n"
)
;
GO_DEBUG_RTX
(
xinsn
)
;
}
if
(
iq2000_check_split
(
xinsn
,
mode
)
)
{
return
gen_rtx_LO_SUM
(
Pmode
,
copy_to_mode_reg
(
Pmode
,
gen_rtx_HIGH
(
Pmode
,
xinsn
)
)
,
xinsn
)
;
}
if
(
GET_CODE
(
xinsn
)
==
PLUS
)
{
rtx
xplus0
=
XEXP
(
xinsn
,
0
)
;
rtx
xplus1
=
XEXP
(
xinsn
,
1
)
;
enum
rtx_code
code0
=
GET_CODE
(
xplus0
)
;
enum
rtx_code
code1
=
GET_CODE
(
xplus1
)
;
if
(
code0
!=
REG
&&
code1
==
REG
)
{
xplus0
=
XEXP
(
xinsn
,
1
)
;
xplus1
=
XEXP
(
xinsn
,
0
)
;
code0
=
GET_CODE
(
xplus0
)
;
code1
=
GET_CODE
(
xplus1
)
;
}
if
(
code0
==
REG
&&
REG_MODE_OK_FOR_BASE_P
(
xplus0
,
mode
)
&&
code1
==
CONST_INT
&&
!
SMALL_INT
(
xplus1
)
)
{
rtx
int_reg
=
gen_reg_rtx
(
Pmode
)
;
rtx
ptr_reg
=
gen_reg_rtx
(
Pmode
)
;
emit_move_insn
(
int_reg
,
GEN_INT
(
INTVAL
(
xplus1
)
&
~
0x7fff
)
)
;
emit_insn
(
gen_rtx_SET
(
VOIDmode
,
ptr_reg
,
gen_rtx_PLUS
(
Pmode
,
xplus0
,
int_reg
)
)
)
;
return
plus_constant
(
Pmode
,
ptr_reg
,
INTVAL
(
xplus1
)
&
0x7fff
)
;
}
}
if
(
TARGET_DEBUG_B_MODE
)
GO_PRINTF
(
"LEGITIMIZE_ADDRESS could not fix.\n"
)
;
return
xinsn
;
}
</s>

For the IQ2000 , transform : memory ( X + < large int > ) into : Y = < large int > & ~0x7fff ; Z = X + Y memory ( Z + ( < large int > & 0x7fff ) ) ;


<s> tree aarch64_builtin_rsqrt ( unsigned int fn ) { if ( fn == AARCH64_SIMD_BUILTIN_UNOP_sqrtv2df ) return aarch64_builtin_decls [ AARCH64_BUILTIN_RSQRT_V2DF ] ; if ( fn == AARCH64_SIMD_BUILTIN_UNOP_sqrtv2sf ) return aarch64_builtin_decls [ AARCH64_BUILTIN_RSQRT_V2SF ] ; if ( fn == AARCH64_SIMD_BUILTIN_UNOP_sqrtv4sf ) return aarch64_builtin_decls [ AARCH64_BUILTIN_RSQRT_V4SF ] ; return NULL_TREE ; } </s>

Return builtin for reciprocal square root .


<s> bool SystemZAsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true ; } </s>


<s> bool HSAILRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> const InstrItineraryData & getInstrItineraryData ( ) const { return InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> static rtx legitimize_pe_coff_extern_decl ( rtx symbol , bool want_reg ) { tree imp_decl ; rtx x ; gcc_assert ( SYMBOL_REF_DECL ( symbol ) ) ; imp_decl = get_dllimport_decl ( SYMBOL_REF_DECL ( symbol ) , false ) ; x = DECL_RTL ( imp_decl ) ; if ( want_reg ) x = force_reg ( Pmode , x ) ; return x ; } </s>

Expand SYMBOL into its corresponding far-addresse symbol . WANT_REG is true if we require the result be a register .


<s> const char * mips_output_conditional_branch ( rtx_insn * insn , rtx * operands , const char * branch_if_true , const char * branch_if_false ) { unsigned int length ; rtx taken ; gcc_assert ( LABEL_P ( operands [ 0 ] ) ) ; length = get_attr_length ( insn ) ; if ( length <= 8 ) { mips_branch_likely = ( final_sequence && INSN_ANNULLED_BRANCH_P ( insn ) ) ; return branch_if_true ; } mips_branch_likely = false ; rtx_code_label * not_taken = gen_label_rtx ( ) ; taken = operands [ 0 ] ; operands [ 0 ] = not_taken ; output_asm_insn ( branch_if_false , operands ) ; if ( final_sequence ) { if ( ! INSN_ANNULLED_BRANCH_P ( insn ) ) { final_scan_insn ( final_sequence -> insn ( 1 ) , asm_out_file , optimize , 1 , NULL ) ; final_sequence -> insn ( 1 ) -> set_deleted ( ) ; } else output_asm_insn ( "nop" , 0 ) ; fprintf ( asm_out_file , "\n" ) ; } if ( TARGET_ABSOLUTE_JUMPS ) output_asm_insn ( MIPS_ABSOLUTE_JUMP ( "j\t%0%/" ) , & taken ) ; else { mips_output_load_label ( taken ) ; output_asm_insn ( "jr\t%@%]%/" , 0 ) ; } if ( final_sequence ) { if ( INSN_ANNULLED_BRANCH_P ( insn ) ) { final_scan_insn ( final_sequence -> insn ( 1 ) , asm_out_file , optimize , 1 , NULL ) ; final_sequence -> insn ( 1 ) -> set_deleted ( ) ; } else output_asm_insn ( "nop" , 0 ) ; fprintf ( asm_out_file , "\n" ) ; } targetm . asm_out . internal_label ( asm_out_file , "L" , CODE_LABEL_NUMBER ( not_taken ) ) ; return "" ; } </s>

Output assembly instructions to peform a conditional branch . INSN is the branch instruction . OPERANDS [ 0 ] is the condition . OPERANDS [ 1 ] is the target of the branch . OPERANDS [ 2 ] is the target of the first operand to the condition . If TWO_OPERANDS_P is nonzero the comparison takes two operands ; OPERANDS [ 3 ] will be the second operand . If INVERTED_P is nonzero we are to branch if the condition does not hold . If FLOAT_P is nonzero this is a floating-point comparison . LENGTH is the length ( in bytes ) of the sequence we are to generate . That tells us whether to generate a simple conditional branch , or a reversed conditional branch around a ` jr ' instruction .


<s> static rtx expand_set_or_movmem_prologue ( rtx destmem , rtx srcmem , rtx destptr , rtx srcptr , rtx value , rtx vec_value , rtx count , int align , int desired_alignment , bool issetmem ) { int i ; for ( i = 1 ; i < desired_alignment ; i <<= 1 ) { if ( align <= i ) { rtx_code_label * label = ix86_expand_aligntest ( destptr , i , false ) ; if ( issetmem ) { if ( vec_value && i > GET_MODE_SIZE ( GET_MODE ( value ) ) ) destmem = emit_memset ( destmem , destptr , vec_value , i ) ; else destmem = emit_memset ( destmem , destptr , value , i ) ; } else destmem = emit_memmov ( destmem , & srcmem , destptr , srcptr , i ) ; ix86_adjust_counter ( count , i ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; set_mem_align ( destmem , i * 2 * BITS_PER_UNIT ) ; } } return destmem ; } </s>

Depending on ISSETMEM , copy enough from SRCMEM to DESTMEM or set enough to DESTMEM to align it to DESIRED_ALIGNMENT . Original alignment is ALIGN . Depending on ISSETMEM , either arguments SRCMEM/SRCPTR or VALUE/VEC_VALUE are ignored . Return value is updated DESTMEM .


<s> BitVector ARCompactRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( ARC :: GP ) ; Reserved . set ( ARC :: SP ) ; Reserved . set ( ARC :: FP ) ; Reserved . set ( ARC :: BLINK ) ; Reserved . set ( ARC :: ILINK1 ) ; Reserved . set ( ARC :: ILINK2 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .

ARCompact ARC ARC::GP ARC::SP ARC::FP ARC::BLINK ARC::ILINK1 ARC::ILINK2


<s>
void
Thumb1InstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
(
PseudoSourceValue
::
getFixedStack
(
FI
)
)
,
MachineMemOperand
::
MOLoad
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tLDRspi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .

ARM
ARM::tGPRRegisterClass
ARM
"Unknown regclass!"
ARM::tGPRRegisterClass
ARM
ARM::tLDRspi
0


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const ARMBaseTargetMachine & TM , bool IsLittle ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , ARMProcClass ( None ) , stackAlignment ( 4 ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , DL ( computeDataLayout ( initializeSubtargetDependencies ( CPU , FS ) ) ) , TSInfo ( DL ) , InstrInfo ( isThumb1Only ( ) ? ( ARMBaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( ARMBaseInstrInfo * ) new ARMInstrInfo ( * this ) : ( ARMBaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM ) , FrameLowering ( ! isThumb1Only ( ) ? new ARMFrameLowering ( * this ) : ( ARMFrameLowering * ) new Thumb1FrameLowering ( * this ) ) { } </s>

This constructor initializes the data members to match that of the specified triple .

ARM ARM ARM ARM ARM ARM ARM 4 ARM ARM ARM ARM ARM ARM


<s>
void
RISCVDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
MVT
XLenVT
=
Subtarget
->
getXLenVT
(
)
;
SDLoc
DL
(
Node
)
;
EVT
VT
=
Node
->
getValueType
(
0
)
;
switch
(
Opcode
)
{
case
ISD
::
Constant
:
{
auto
ConstNode
=
cast
<
ConstantSDNode
>
(
Node
)
;
if
(
VT
==
XLenVT
&&
ConstNode
->
isNullValue
(
)
)
{
SDValue
New
=
CurDAG
->
getCopyFromReg
(
CurDAG
->
getEntryNode
(
)
,
SDLoc
(
Node
)
,
RISCV
::
X0
,
XLenVT
)
;
ReplaceNode
(
Node
,
New
.
getNode
(
)
)
;
return
;
}
int64_t
Imm
=
ConstNode
->
getSExtValue
(
)
;
if
(
XLenVT
==
MVT
::
i64
)
{
ReplaceNode
(
Node
,
selectImm
(
CurDAG
,
SDLoc
(
Node
)
,
Imm
,
XLenVT
)
)
;
return
;
}
break
;
}
case
ISD
::
FrameIndex
:
{
SDValue
Imm
=
CurDAG
->
getTargetConstant
(
0
,
DL
,
XLenVT
)
;
int
FI
=
cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
VT
)
;
ReplaceNode
(
Node
,
CurDAG
->
getMachineNode
(
RISCV
::
ADDI
,
DL
,
VT
,
TFI
,
Imm
)
)
;
return
;
}
case
ISD
::
SRL
:
{
if
(
!
Subtarget
->
is64Bit
(
)
)
break
;
SDValue
Op0
=
Node
->
getOperand
(
0
)
;
SDValue
Op1
=
Node
->
getOperand
(
1
)
;
uint64_t
Mask
;
if
(
Op1
.
getOpcode
(
)
==
ISD
::
Constant
&&
isConstantMask
(
Op0
.
getNode
(
)
,
Mask
)
)
{
uint64_t
ShAmt
=
cast
<
ConstantSDNode
>
(
Op1
.
getNode
(
)
)
->
getZExtValue
(
)
;
if
(
(
Mask
|
maskTrailingOnes
<
uint64_t
>
(
ShAmt
)
)
==
0xffffffff
)
{
SDValue
ShAmtVal
=
CurDAG
->
getTargetConstant
(
ShAmt
,
SDLoc
(
Node
)
,
XLenVT
)
;
CurDAG
->
SelectNodeTo
(
Node
,
RISCV
::
SRLIW
,
XLenVT
,
Op0
.
getOperand
(
0
)
,
ShAmtVal
)
;
return
;
}
}
break
;
}
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> static bool has_dispatch ( rtx_insn * insn , int action ) { if ( ( TARGET_BDVER1 || TARGET_BDVER2 || TARGET_BDVER3 || TARGET_BDVER4 || TARGET_ZNVER1 ) && flag_dispatch_scheduler ) switch ( action ) { default : return false ; case IS_DISPATCH_ON : return true ; break ; case IS_CMP : return is_cmp ( insn ) ; case DISPATCH_VIOLATION : return dispatch_violation ( ) ; case FITS_DISPATCH_WINDOW : return fits_dispatch_window ( insn ) ; } return false ; } </s>

Return TRUE if Dispatch Scheduling is supported .


<s> int X86FrameLowering :: mergeSPUpdates ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , bool doMergeWithPrevious ) { if ( ( doMergeWithPrevious && MBBI == MBB . begin ( ) ) || ( ! doMergeWithPrevious && MBBI == MBB . end ( ) ) ) return 0 ; MachineBasicBlock :: iterator PI = doMergeWithPrevious ? std :: prev ( MBBI ) : MBBI ; MachineBasicBlock :: iterator NI = doMergeWithPrevious ? nullptr : std :: next ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = 0 ; if ( ( Opc == X86 :: ADD64ri32 || Opc == X86 :: ADD64ri8 || Opc == X86 :: ADD32ri || Opc == X86 :: ADD32ri8 || Opc == X86 :: LEA32r || Opc == X86 :: LEA64_32r ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { Offset += PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == X86 :: SUB64ri32 || Opc == X86 :: SUB64ri8 || Opc == X86 :: SUB32ri || Opc == X86 :: SUB32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { Offset -= PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } return Offset ; } </s>

Check the instruction before/after the passed instruction .


isArgumentReg - Returns true if Reg can be used as an argument to a function .


<s> const X86InstrInfo * getInstrInfo ( ) const { return getTargetMachine ( ) -> getInstrInfo ( ) ; } </s>


<s> unsigned AMDGPUAsmBackend :: getMinimumNopSize ( ) const { return 4 ; } </s>

Returns the minimum size of a nop in bytes on this target .


"Pseudo flag-setting opcodes must be marked with 'hasPostISelHook'"

"converted opcode should be the same except for cc_out"

"expect uninitialized optional cc_out operand"

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


<s> MachineBasicBlock :: iterator X86InstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , bool IsTailCall ) const { if ( IsTailCall ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( X86 :: JMP_1 ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; } else { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( X86 :: CALL64pcrel32 ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; } return It ; } </s>

Insert a call to an outlined function into the program .


<s> bool X86AsmParser :: processInstruction ( MCInst & Inst , const SmallVectorImpl < MCParsedAsmOperand * > & Ops ) { switch ( Inst . getOpcode ( ) ) { default : return false ; case X86 :: AND16i16 : return convert16i16to16ri8 ( Inst , X86 :: AND16ri8 ) ; case X86 :: AND32i32 : return convert32i32to32ri8 ( Inst , X86 :: AND32ri8 ) ; case X86 :: AND64i32 : return convert64i32to64ri8 ( Inst , X86 :: AND64ri8 ) ; case X86 :: XOR16i16 : return convert16i16to16ri8 ( Inst , X86 :: XOR16ri8 ) ; case X86 :: XOR32i32 : return convert32i32to32ri8 ( Inst , X86 :: XOR32ri8 ) ; case X86 :: XOR64i32 : return convert64i32to64ri8 ( Inst , X86 :: XOR64ri8 ) ; case X86 :: OR16i16 : return convert16i16to16ri8 ( Inst , X86 :: OR16ri8 ) ; case X86 :: OR32i32 : return convert32i32to32ri8 ( Inst , X86 :: OR32ri8 ) ; case X86 :: OR64i32 : return convert64i32to64ri8 ( Inst , X86 :: OR64ri8 ) ; case X86 :: CMP16i16 : return convert16i16to16ri8 ( Inst , X86 :: CMP16ri8 , true ) ; case X86 :: CMP32i32 : return convert32i32to32ri8 ( Inst , X86 :: CMP32ri8 , true ) ; case X86 :: CMP64i32 : return convert64i32to64ri8 ( Inst , X86 :: CMP64ri8 , true ) ; case X86 :: ADD16i16 : return convert16i16to16ri8 ( Inst , X86 :: ADD16ri8 ) ; case X86 :: ADD32i32 : return convert32i32to32ri8 ( Inst , X86 :: ADD32ri8 ) ; case X86 :: ADD64i32 : return convert64i32to64ri8 ( Inst , X86 :: ADD64ri8 ) ; case X86 :: SUB16i16 : return convert16i16to16ri8 ( Inst , X86 :: SUB16ri8 ) ; case X86 :: SUB32i32 : return convert32i32to32ri8 ( Inst , X86 :: SUB32ri8 ) ; case X86 :: SUB64i32 : return convert64i32to64ri8 ( Inst , X86 :: SUB64ri8 ) ; case X86 :: ADC16i16 : return convert16i16to16ri8 ( Inst , X86 :: ADC16ri8 ) ; case X86 :: ADC32i32 : return convert32i32to32ri8 ( Inst , X86 :: ADC32ri8 ) ; case X86 :: ADC64i32 : return convert64i32to64ri8 ( Inst , X86 :: ADC64ri8 ) ; case X86 :: SBB16i16 : return convert16i16to16ri8 ( Inst , X86 :: SBB16ri8 ) ; case X86 :: SBB32i32 : return convert32i32to32ri8 ( Inst , X86 :: SBB32ri8 ) ; case X86 :: SBB64i32 : return convert64i32to64ri8 ( Inst , X86 :: SBB64ri8 ) ; } } </s>

Process a single instruction and collect debug info anchors .


<s>
void
AArch64Operand
::
print
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
k_FPImm
:
OS
<<
"<fpimm "
<<
getFPImm
(
)
.
bitcastToAPInt
(
)
.
getZExtValue
(
)
;
if
(
!
getFPImmIsExact
(
)
)
OS
<<
" (inexact)"
;
OS
<<
">"
;
break
;
case
k_Barrier
:
{
StringRef
Name
=
getBarrierName
(
)
;
if
(
!
Name
.
empty
(
)
)
OS
<<
"<barrier "
<<
Name
<<
">"
;
else
OS
<<
"<barrier invalid #"
<<
getBarrier
(
)
<<
">"
;
break
;
}
case
k_Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
k_ShiftedImm
:
{
unsigned
Shift
=
getShiftedImmShift
(
)
;
OS
<<
"<shiftedimm "
;
OS
<<
*
getShiftedImmVal
(
)
;
OS
<<
", lsl #"
<<
AArch64_AM
::
getShiftValue
(
Shift
)
<<
">"
;
break
;
}
case
k_CondCode
:
OS
<<
"<condcode "
<<
getCondCode
(
)
<<
">"
;
break
;
case
k_VectorList
:
{
OS
<<
"<vectorlist "
;
unsigned
Reg
=
getVectorListStart
(
)
;
for
(
unsigned
i
=
0
,
e
=
getVectorListCount
(
)
;
i
!=
e
;
++
i
)
OS
<<
Reg
+
i
<<
" "
;
OS
<<
">"
;
break
;
}
case
k_VectorIndex
:
OS
<<
"<vectorindex "
<<
getVectorIndex
(
)
<<
">"
;
break
;
case
k_SysReg
:
OS
<<
"<sysreg: "
<<
getSysReg
(
)
<<
'>'
;
break
;
case
k_Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
case
k_SysCR
:
OS
<<
"c"
<<
getSysCR
(
)
;
break
;
case
k_Prefetch
:
{
StringRef
Name
=
getPrefetchName
(
)
;
if
(
!
Name
.
empty
(
)
)
OS
<<
"<prfop "
<<
Name
<<
">"
;
else
OS
<<
"<prfop invalid #"
<<
getPrefetch
(
)
<<
">"
;
break
;
}
case
k_PSBHint
:
OS
<<
getPSBHintName
(
)
;
break
;
case
k_Register
:
OS
<<
"<register "
<<
getReg
(
)
<<
">"
;
if
(
!
getShiftExtendAmount
(
)
&&
!
hasShiftExtendAmount
(
)
)
break
;
LLVM_FALLTHROUGH
;
case
k_BTIHint
:
OS
<<
getBTIHintName
(
)
;
break
;
case
k_ShiftExtend
:
OS
<<
"<"
<<
AArch64_AM
::
getShiftExtendName
(
getShiftExtendType
(
)
)
<<
" #"
<<
getShiftExtendAmount
(
)
;
if
(
!
hasShiftExtendAmount
(
)
)
OS
<<
"<imp>"
;
OS
<<
'>'
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

AArch64
AArch64
"<fpimm "
" (inexact)"
">"
"<barrier "
">"
"<barrier invalid #"
">"
"<shiftedimm "
", lsl #"
AArch64_AM::getShiftValue
">"
"<condcode "
">"
"<vectorlist "
0
" "
">"
"<vectorindex "
">"
"<sysreg: "
"'"
"'"
"c"
"<prfop "
">"
"<prfop invalid #"
">"
"<register "
">"
"<"
AArch64_AM::getShiftExtendName
" #"
"<imp>"


<s> TargetTransformInfo AArch64TargetMachine :: getTargetTransformInfo ( const Function & F ) const { return TargetTransformInfo ( AArch64TTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> bool X86InstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == X86 :: ENDBR64 || Opcode == X86 :: ENDBR32 ) return true ; return TargetInstrInfo :: isSchedulingBoundary ( MI , MBB , MF ) ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> int pdp10_starting_frame_offset ( ) { return 0 ; } </s>

Called by the STARTING_FRAME_OFFSET macro .


<s> bool arm_valid_symbolic_address_p ( rtx addr ) { rtx xop0 , xop1 = NULL_RTX ; rtx tmp = addr ; if ( GET_CODE ( tmp ) == SYMBOL_REF || GET_CODE ( tmp ) == LABEL_REF ) return true ; if ( GET_CODE ( addr ) == CONST ) tmp = XEXP ( addr , 0 ) ; if ( GET_CODE ( tmp ) == PLUS ) { xop0 = XEXP ( tmp , 0 ) ; xop1 = XEXP ( tmp , 1 ) ; if ( GET_CODE ( xop0 ) == SYMBOL_REF && CONST_INT_P ( xop1 ) ) return IN_RANGE ( INTVAL ( xop1 ) , - 0x8000 , 0x7fff ) ; } return false ; } </s>

Returns true if the pattern is a valid symbolic address , which is either a symbol_ref or ( symbol_ref + addend ) . According to the ARM ELF ABI , the initial addend of REL-type relocations processing MOVW and MOVT instructions is formed by interpreting the 16-bit literal field of the instruction as a 16-bit signed value in the range -32768 < = A < 32768 . In Thumb-1 mode , we use upper/lower relocations which have an 8-bit unsigned range of 0 < = A < 256 as described in the AAELF32 relocation handling documentation : REL-type relocations are encoded as unsigned in this case .


<s> const MCExpr * VEAsmParser :: parseIdentifier ( StringRef Identifier ) { StringRef Modifier ; size_t at = Identifier . rfind ( '@' ) ; if ( at != 0 || at != StringRef :: npos ) { std :: pair < StringRef , StringRef > Pair = Identifier . rsplit ( "@" ) ; if ( ! Pair . first . empty ( ) && ! Pair . second . empty ( ) ) { Identifier = Pair . first ; Modifier = Pair . second ; } } MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; VEMCExpr :: VariantKind VK = VEMCExpr :: parseVariantKind ( Modifier ) ; if ( VK == VEMCExpr :: VK_VE_None ) { VEMCExpr :: VariantKind Kind = VEMCExpr :: VK_VE_REFLONG ; return VEMCExpr :: create ( Kind , Res , getContext ( ) ) ; } return VEMCExpr :: create ( VK , Res , getContext ( ) ) ; } </s>

Parse an identifier or string ( as a quoted identifier ) and set Res to the identifier contents .


<s> void ix86_rewrite_tls_address_1 ( rtx * loc ) { subrtx_ptr_iterator :: array_type array ; FOR_EACH_SUBRTX_PTR ( iter , array , loc , ALL ) { rtx * loc = * iter ; if ( MEM_P ( * loc ) ) { rtx addr = XEXP ( * loc , 0 ) ; rtx * x = & addr ; while ( GET_CODE ( * x ) == PLUS ) { int i ; for ( i = 0 ; i < 2 ; i ++ ) { rtx u = XEXP ( * x , i ) ; if ( GET_CODE ( u ) == ZERO_EXTEND ) u = XEXP ( u , 0 ) ; if ( GET_CODE ( u ) == UNSPEC && XINT ( u , 1 ) == UNSPEC_TP ) { addr_space_t as = DEFAULT_TLS_SEG_REG ; * x = XEXP ( * x , 1 - i ) ; * loc = replace_equiv_address_nv ( * loc , addr , true ) ; set_mem_addr_space ( * loc , as ) ; return ; } } x = & XEXP ( * x , 0 ) ; } iter . skip_subrtxes ( ) ; } } } </s>

Rewrite * LOC so that it refers to a default TLS address space .


<s> enum arc_function_type arc_compute_function_type ( struct function * fun ) { tree decl = fun -> decl ; tree a ; enum arc_function_type fn_type = fun -> machine -> fn_type ; if ( fn_type != ARC_FUNCTION_UNKNOWN ) return fn_type ; fn_type = ARC_FUNCTION_NORMAL ; for ( a = DECL_ATTRIBUTES ( decl ) ; a ; a = TREE_CHAIN ( a ) ) { tree name = TREE_PURPOSE ( a ) , args = TREE_VALUE ( a ) ; if ( name == get_identifier ( "interrupt" ) && list_length ( args ) == 1 && TREE_CODE ( TREE_VALUE ( args ) ) == STRING_CST ) { tree value = TREE_VALUE ( args ) ; if ( ! strcmp ( TREE_STRING_POINTER ( value ) , "ilink1" ) ) fn_type = ARC_FUNCTION_ILINK1 ; else if ( ! strcmp ( TREE_STRING_POINTER ( value ) , "ilink2" ) ) fn_type = ARC_FUNCTION_ILINK2 ; else gcc_unreachable ( ) ; break ; } } return fun -> machine -> fn_type = fn_type ; } </s>

Type of function DECL . The result is cached . To reset the cache at the end of a function , call with DECL = NULL_TREE .


<s> void TriCoreCallingConvHook :: init ( ) { curPos = 0 ; curArg = 0 ; } </s>

Initialize the machine model for instruction scheduling .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { initialize ( MF ) ; unskipableSimplifyCode ( ) ; if ( skipFunction ( MF . getFunction ( ) ) ) return false ; return simplifyCode ( ) ; } </s>

runOnMachineFunction - Emit the function body .