<s> unsigned SparcInstrInfo :: getGlobalBaseReg ( MachineFunction * MF ) const { SparcMachineFunctionInfo * SparcFI = MF -> getInfo < SparcMachineFunctionInfo > ( ) ; unsigned GlobalBaseReg = SparcFI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg != 0 ) return GlobalBaseReg ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; GlobalBaseReg = RegInfo . createVirtualRegister ( & SP :: IntRegsRegClass ) ; DebugLoc dl ; BuildMI ( FirstMBB , MBBI , dl , get ( SP :: GETPCX ) , GlobalBaseReg ) ; SparcFI -> setGlobalBaseReg ( GlobalBaseReg ) ; return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

Sparc Sparc Sparc Sparc Sparc Sparc 0 SP::IntRegsRegClass SP::GETPCX Sparc


<s>
void
A57ChainingConstraint
::
apply
(
PBQPRAGraph
&
G
)
{
const
MachineFunction
&
MF
=
G
.
getMetadata
(
)
.
MF
;
LiveIntervals
&
LIs
=
G
.
getMetadata
(
)
.
LIS
;
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
DEBUG
(
MF
.
dump
(
)
)
;
for
(
const
auto
&
MBB
:
MF
)
{
Chains
.
clear
(
)
;
for
(
const
auto
&
MI
:
MBB
)
{
for
(
auto
r
:
Chains
)
{
SmallVector
<
unsigned
,
8
>
toDel
;
if
(
regJustKilledBefore
(
LIs
,
r
,
MI
)
)
{
DEBUG
(
dbgs
(
)
<<
"Killing chain "
<<
PrintReg
(
r
,
TRI
)
<<
" at "
;
MI
.
print
(
dbgs
(
)
)
;
)
;
toDel
.
push_back
(
r
)
;
}
while
(
!
toDel
.
empty
(
)
)
{
Chains
.
remove
(
toDel
.
back
(
)
)
;
toDel
.
pop_back
(
)
;
}
}
switch
(
MI
.
getOpcode
(
)
)
{
case
AArch64
::
FMSUBSrrr
:
case
AArch64
::
FMADDSrrr
:
case
AArch64
::
FNMSUBSrrr
:
case
AArch64
::
FNMADDSrrr
:
case
AArch64
::
FMSUBDrrr
:
case
AArch64
::
FMADDDrrr
:
case
AArch64
::
FNMSUBDrrr
:
case
AArch64
::
FNMADDDrrr
:
{
unsigned
Rd
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
unsigned
Ra
=
MI
.
getOperand
(
3
)
.
getReg
(
)
;
if
(
addIntraChainConstraint
(
G
,
Rd
,
Ra
)
)
addInterChainConstraint
(
G
,
Rd
,
Ra
)
;
break
;
}
case
AArch64
::
FMLAv2f32
:
case
AArch64
::
FMLSv2f32
:
{
unsigned
Rd
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
addInterChainConstraint
(
G
,
Rd
,
Rd
)
;
break
;
}
default
:
break
;
}
}
}
}
</s>

Apply the profile inference algorithm for a given function .


<s> void msp430_output_labelref ( FILE * file , const char * name ) { int i ; for ( i = 0 ; helper_function_name_mappings [ i ] . gcc_name ; i ++ ) if ( strcmp ( helper_function_name_mappings [ i ] . gcc_name , name ) == 0 ) { name = helper_function_name_mappings [ i ] . ti_name ; break ; } if ( user_label_prefix [ 0 ] != 0 ) fputs ( user_label_prefix , file ) ; fputs ( name , file ) ; } </s>

This function does the same as the default , but it will replace GCC function names with the MSPABI-specified ones .


<s> void RegDefsUses :: init ( const MachineInstr & MI ) { update ( MI , 0 , MI . getDesc ( ) . getNumOperands ( ) ) ; if ( MI . isCall ( ) ) Defs . set ( Mips :: RA ) ; if ( MI . isBranch ( ) ) { update ( MI , MI . getDesc ( ) . getNumOperands ( ) , MI . getNumOperands ( ) ) ; Defs . reset ( Mips :: AT ) ; } } </s>

Initialize the machine model for instruction scheduling .


<s> bool loongarch_do_optimize_block_move_p ( void ) { if ( target_flags_explicit & MASK_MEMCPY ) return ! TARGET_MEMCPY ; return ! optimize_size ; } </s>

Return true if loongarch_expand_block_move is the preferred implementation of the 'cpymemsi ' template .


<s> bool X86AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < X86Subtarget > ( ) ; SMShadowTracker . startFunction ( MF ) ; CodeEmitter . reset ( TM . getTarget ( ) . createMCCodeEmitter ( * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegisterInfo ( ) , MF . getContext ( ) ) ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Intrn = MF . getFunction ( ) -> hasInternalLinkage ( ) ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Intrn ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> int ix86_local_alignment ( tree type , int align ) { if ( TARGET_64BIT ) { if ( AGGREGATE_TYPE_P ( type ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && ( TREE_INT_CST_LOW ( TYPE_SIZE ( type ) ) >= 16 || TREE_INT_CST_HIGH ( TYPE_SIZE ( type ) ) ) && align < 128 ) return 128 ; } if ( TREE_CODE ( type ) == ARRAY_TYPE ) { if ( TYPE_MODE ( TREE_TYPE ( type ) ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( type ) ) ) && align < 128 ) return 128 ; } else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) { if ( TYPE_MODE ( type ) == DCmode && align < 64 ) return 64 ; if ( TYPE_MODE ( type ) == XCmode && align < 128 ) return 128 ; } else if ( ( TREE_CODE ( type ) == RECORD_TYPE || TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == QUAL_UNION_TYPE ) && TYPE_FIELDS ( type ) ) { if ( DECL_MODE ( TYPE_FIELDS ( type ) ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( DECL_MODE ( TYPE_FIELDS ( type ) ) ) && align < 128 ) return 128 ; } else if ( TREE_CODE ( type ) == REAL_TYPE || TREE_CODE ( type ) == VECTOR_TYPE || TREE_CODE ( type ) == INTEGER_TYPE ) { if ( TYPE_MODE ( type ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( TYPE_MODE ( type ) ) && align < 128 ) return 128 ; } return align ; } </s>

Compute the alignment for a local variable . TYPE is the data type , and ALIGN is the alignment that the object would ordinarily have . The value of this macro is used instead of that alignment to align the object .


<s> static int distance_agu_use ( unsigned int regno0 , rtx_insn * insn ) { basic_block bb = BLOCK_FOR_INSN ( insn ) ; int distance = 0 ; bool found = false ; bool redefined = false ; if ( insn != BB_END ( bb ) ) distance = distance_agu_use_in_bb ( regno0 , insn , distance , NEXT_INSN ( insn ) , & found , & redefined ) ; if ( ! found && ! redefined && distance < LEA_SEARCH_THRESHOLD ) { edge e ; edge_iterator ei ; bool simple_loop = false ; FOR_EACH_EDGE ( e , ei , bb -> succs ) if ( e -> dest == bb ) { simple_loop = true ; break ; } if ( simple_loop ) distance = distance_agu_use_in_bb ( regno0 , insn , distance , BB_HEAD ( bb ) , & found , & redefined ) ; else { int shortest_dist = - 1 ; bool found_in_bb = false ; bool redefined_in_bb = false ; FOR_EACH_EDGE ( e , ei , bb -> succs ) { int bb_dist = distance_agu_use_in_bb ( regno0 , insn , distance , BB_HEAD ( e -> dest ) , & found_in_bb , & redefined_in_bb ) ; if ( found_in_bb ) { if ( shortest_dist < 0 ) shortest_dist = bb_dist ; else if ( bb_dist > 0 ) shortest_dist = MIN ( bb_dist , shortest_dist ) ; found = true ; } } distance = shortest_dist ; } } if ( ! found || redefined ) return - 1 ; return distance >> 1 ; } </s>

Return the distance between INSN and the next insn that uses register number REGNO0 in memory address . Return -1 if no such a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set .


<s> bool SIRegisterInfo :: shouldCoalesce ( MachineInstr * MI , const TargetRegisterClass * SrcRC , unsigned SubReg , const TargetRegisterClass * DstRC , unsigned DstSubReg , const TargetRegisterClass * NewRC ) const { unsigned SrcSize = getRegSizeInBits ( * SrcRC ) ; unsigned DstSize = getRegSizeInBits ( * DstRC ) ; unsigned NewSize = getRegSizeInBits ( * NewRC ) ; if ( SrcSize <= 32 || DstSize <= 32 ) return true ; return NewSize <= DstSize || NewSize <= SrcSize ; } </s>


<s> void s390_expand_movmem ( rtx dst , rtx src , rtx len ) { if ( GET_CODE ( len ) == CONST_INT && INTVAL ( len ) >= 0 && INTVAL ( len ) <= 256 ) { if ( INTVAL ( len ) > 0 ) emit_insn ( gen_movmem_short ( dst , src , GEN_INT ( INTVAL ( len ) - 1 ) ) ) ; } else if ( TARGET_MVCLE ) { emit_insn ( gen_movmem_long ( dst , src , convert_to_mode ( Pmode , len , 1 ) ) ) ; } else { rtx dst_addr , src_addr , count , blocks , temp ; rtx loop_start_label = gen_label_rtx ( ) ; rtx loop_end_label = gen_label_rtx ( ) ; rtx end_label = gen_label_rtx ( ) ; enum machine_mode mode ; mode = GET_MODE ( len ) ; if ( mode == VOIDmode ) mode = Pmode ; dst_addr = gen_reg_rtx ( Pmode ) ; src_addr = gen_reg_rtx ( Pmode ) ; count = gen_reg_rtx ( mode ) ; blocks = gen_reg_rtx ( mode ) ; convert_move ( count , len , 1 ) ; emit_cmp_and_jump_insns ( count , const0_rtx , EQ , NULL_RTX , mode , 1 , end_label ) ; emit_move_insn ( dst_addr , force_operand ( XEXP ( dst , 0 ) , NULL_RTX ) ) ; emit_move_insn ( src_addr , force_operand ( XEXP ( src , 0 ) , NULL_RTX ) ) ; dst = change_address ( dst , VOIDmode , dst_addr ) ; src = change_address ( src , VOIDmode , src_addr ) ; temp = expand_binop ( mode , add_optab , count , constm1_rtx , count , 1 , 0 ) ; if ( temp != count ) emit_move_insn ( count , temp ) ; temp = expand_binop ( mode , ashr_optab , count , GEN_INT ( 8 ) , blocks , 1 , 0 ) ; if ( temp != blocks ) emit_move_insn ( blocks , temp ) ; emit_cmp_and_jump_insns ( blocks , const0_rtx , EQ , NULL_RTX , mode , 1 , loop_end_label ) ; emit_label ( loop_start_label ) ; emit_insn ( gen_movmem_short ( dst , src , GEN_INT ( 255 ) ) ) ; s390_load_address ( dst_addr , gen_rtx_PLUS ( Pmode , dst_addr , GEN_INT ( 256 ) ) ) ; s390_load_address ( src_addr , gen_rtx_PLUS ( Pmode , src_addr , GEN_INT ( 256 ) ) ) ; temp = expand_binop ( mode , add_optab , blocks , constm1_rtx , blocks , 1 , 0 ) ; if ( temp != blocks ) emit_move_insn ( blocks , temp ) ; emit_cmp_and_jump_insns ( blocks , const0_rtx , EQ , NULL_RTX , mode , 1 , loop_end_label ) ; emit_jump ( loop_start_label ) ; emit_label ( loop_end_label ) ; emit_insn ( gen_movmem_short ( dst , src , convert_to_mode ( Pmode , count , 1 ) ) ) ; emit_label ( end_label ) ; } } </s>

Emit code to move LEN bytes from DST to SRC .


<s> unsigned WebAssemblyFastISel :: signExtend ( unsigned Reg , const Value * V , MVT :: SimpleValueType From , MVT :: SimpleValueType To ) { if ( To == MVT :: i64 ) { if ( From == MVT :: i64 ) return copyValue ( Reg ) ; Reg = signExtendToI32 ( Reg , V , From ) ; unsigned Result = createResultReg ( & WebAssembly :: I64RegClass ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( WebAssembly :: I64_EXTEND_S_I32 ) , Result ) . addReg ( Reg ) ; return Result ; } if ( To == MVT :: i32 ) return signExtendToI32 ( Reg , V , From ) ; return 0 ; } </s>

Return a new range in the specified integer type , which must be strictly larger than the current type .


<s> unsigned int s390_case_values_threshold ( void ) { if ( TARGET_INDIRECT_BRANCH_NOBP_JUMP ) return 20 ; return default_case_values_threshold ( ) ; } </s>

Implement the TARGET_CASE_VALUES_THRESHOLD target hook .


"Relocation emission for MachO/PPC64 unimplemented."


<s> unsigned AArch64FrameLowering :: getWinEHParentFrameOffset ( const MachineFunction & MF ) const { return 0 ; } </s>

The parent frame offset ( aka dispFrame ) is only used on X86_64 to retrieve the parent 's frame pointer .


"The number of element should not be zero."

Target-specific combining of register parts into its original value .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> static bool ia64_function_value_regno_p ( const unsigned int regno ) { return ( ( regno >= GR_RET_FIRST && regno <= GR_RET_LAST ) || ( regno >= FR_RET_FIRST && regno <= FR_RET_LAST ) ) ; } </s>

Worker function for FUNCTION_VALUE_REGNO_P .


<s> const char * SparcTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( SPISD :: NodeType ) Opcode ) { case SPISD :: FIRST_NUMBER : break ; case SPISD :: CMPICC : return "SPISD::CMPICC" ; case SPISD :: CMPFCC : return "SPISD::CMPFCC" ; case SPISD :: BRICC : return "SPISD::BRICC" ; case SPISD :: BRXCC : return "SPISD::BRXCC" ; case SPISD :: BRFCC : return "SPISD::BRFCC" ; case SPISD :: SELECT_ICC : return "SPISD::SELECT_ICC" ; case SPISD :: SELECT_XCC : return "SPISD::SELECT_XCC" ; case SPISD :: SELECT_FCC : return "SPISD::SELECT_FCC" ; case SPISD :: Hi : return "SPISD::Hi" ; case SPISD :: Lo : return "SPISD::Lo" ; case SPISD :: FTOI : return "SPISD::FTOI" ; case SPISD :: ITOF : return "SPISD::ITOF" ; case SPISD :: FTOX : return "SPISD::FTOX" ; case SPISD :: XTOF : return "SPISD::XTOF" ; case SPISD :: CALL : return "SPISD::CALL" ; case SPISD :: RET_FLAG : return "SPISD::RET_FLAG" ; case SPISD :: GLOBAL_BASE_REG : return "SPISD::GLOBAL_BASE_REG" ; case SPISD :: FLUSHW : return "SPISD::FLUSHW" ; case SPISD :: TLS_ADD : return "SPISD::TLS_ADD" ; case SPISD :: TLS_LD : return "SPISD::TLS_LD" ; case SPISD :: TLS_CALL : return "SPISD::TLS_CALL" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> int first_reg_to_save ( void ) { int first_reg ; for ( first_reg = 13 ; first_reg <= 31 ; first_reg ++ ) if ( save_reg_p ( first_reg ) ) break ; if ( first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM && ( ( DEFAULT_ABI == ABI_V4 && flag_pic != 0 ) || ( DEFAULT_ABI == ABI_DARWIN && flag_pic ) || ( TARGET_TOC && TARGET_MINIMAL_TOC ) ) && rs6000_reg_live_or_pic_offset_p ( RS6000_PIC_OFFSET_TABLE_REGNUM ) ) first_reg = RS6000_PIC_OFFSET_TABLE_REGNUM ; if ( flag_pic && crtl -> uses_pic_offset_table && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM ) return RS6000_PIC_OFFSET_TABLE_REGNUM ; return first_reg ; } </s>

Return the first register that is required to be saved . 16 if none .


<s> TargetPassConfig * VideoCore4TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new VideoCore4PassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> void ix86_expand_vector_move_misalign ( machine_mode mode , rtx operands [ ] ) { rtx op0 , op1 , m ; op0 = operands [ 0 ] ; op1 = operands [ 1 ] ; if ( GET_MODE_SIZE ( mode ) == 64 || optimize_insn_for_size_p ( ) ) { emit_insn ( gen_rtx_SET ( op0 , op1 ) ) ; return ; } if ( TARGET_AVX ) { if ( GET_MODE_SIZE ( mode ) == 32 ) ix86_avx256_split_vector_move_misalign ( op0 , op1 ) ; else emit_insn ( gen_rtx_SET ( op0 , op1 ) ) ; return ; } if ( TARGET_SSE_UNALIGNED_LOAD_OPTIMAL || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL ) { emit_insn ( gen_rtx_SET ( op0 , op1 ) ) ; return ; } if ( TARGET_SSE2 && GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) { emit_insn ( gen_rtx_SET ( op0 , op1 ) ) ; return ; } if ( MEM_P ( op1 ) ) { if ( TARGET_SSE2 && mode == V2DFmode ) { rtx zero ; if ( TARGET_SSE_SPLIT_REGS ) { emit_clobber ( op0 ) ; zero = op0 ; } else { zero = CONST0_RTX ( V2DFmode ) ; } m = adjust_address ( op1 , DFmode , 0 ) ; emit_insn ( gen_sse2_loadlpd ( op0 , zero , m ) ) ; m = adjust_address ( op1 , DFmode , 8 ) ; emit_insn ( gen_sse2_loadhpd ( op0 , op0 , m ) ) ; } else { rtx t ; if ( mode != V4SFmode ) t = gen_reg_rtx ( V4SFmode ) ; else t = op0 ; if ( TARGET_SSE_PARTIAL_REG_DEPENDENCY ) emit_move_insn ( t , CONST0_RTX ( V4SFmode ) ) ; else emit_clobber ( t ) ; m = adjust_address ( op1 , V2SFmode , 0 ) ; emit_insn ( gen_sse_loadlps ( t , t , m ) ) ; m = adjust_address ( op1 , V2SFmode , 8 ) ; emit_insn ( gen_sse_loadhps ( t , t , m ) ) ; if ( mode != V4SFmode ) emit_move_insn ( op0 , gen_lowpart ( mode , t ) ) ; } } else if ( MEM_P ( op0 ) ) { if ( TARGET_SSE2 && mode == V2DFmode ) { m = adjust_address ( op0 , DFmode , 0 ) ; emit_insn ( gen_sse2_storelpd ( m , op1 ) ) ; m = adjust_address ( op0 , DFmode , 8 ) ; emit_insn ( gen_sse2_storehpd ( m , op1 ) ) ; } else { if ( mode != V4SFmode ) op1 = gen_lowpart ( V4SFmode , op1 ) ; m = adjust_address ( op0 , V2SFmode , 0 ) ; emit_insn ( gen_sse_storelps ( m , op1 ) ) ; m = adjust_address ( op0 , V2SFmode , 8 ) ; emit_insn ( gen_sse_storehps ( m , copy_rtx ( op1 ) ) ) ; } } else gcc_unreachable ( ) ; } </s>

Implement the movmisalign patterns for SSE . Non-SSE modes go straight to ix86_expand_vector_move .


<s>
ScheduleHazardRecognizer
*
PPCInstrInfo
::
CreateTargetPostRAHazardRecognizer
(
const
InstrItineraryData
*
II
,
const
ScheduleDAG
*
DAG
)
const
{
unsigned
Directive
=
DAG
->
MF
.
getSubtarget
<
PPCSubtarget
>
(
)
.
getMcpu
(
)
;
if
(
Directive
==
PPC
::
MCPU_PWR7
||
Directive
==
PPC
::
MCPU_PWR8
)
return
new
PPCDispatchGroupSBHazardRecognizer
(
II
,
DAG
)
;
if
(
Directive
!=
PPC
::
MCPU_440
&&
Directive
!=
PPC
::
MCPU_A2
&&
Directive
!=
PPC
::
MCPU_E500mc
&&
Directive
!=
PPC
::
MCPU_E5500
)
{
assert
(
DAG
->
TII
&&
"No InstrInfo?"
)
;
return
new
PPCHazardRecognizer970
(
*
DAG
)
;
}
return
new
ScoreboardHazardRecognizer
(
II
,
DAG
)
;
}
</s>

Allocate and return a hazard recognizer to use for by non-scheduling passes .


<s> bool enableMachineScheduler ( ) const override { return true ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


<s> void MipsSEFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; unsigned RA = ABI . IsN64 ( ) ? Mips :: RA_64 : Mips :: RA ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned BP = ABI . IsN64 ( ) ? Mips :: S7_64 : Mips :: S7 ; if ( hasFP ( MF ) ) { setAliasRegs ( MF , SavedRegs , RA ) ; setAliasRegs ( MF , SavedRegs , FP ) ; } if ( hasBP ( MF ) ) setAliasRegs ( MF , SavedRegs , BP ) ; if ( MipsFI -> callsEhReturn ( ) ) MipsFI -> createEhDataRegsFI ( MF ) ; if ( MipsFI -> isISR ( ) ) MipsFI -> createISRRegFI ( MF ) ; if ( ExpandPseudo ( MF ) . expand ( ) ) { const TargetRegisterClass & RC = STI . isGP64bit ( ) ? Mips :: GPR64RegClass : Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlign ( RC ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } uint64_t MaxSPOffset = estimateStackSize ( MF ) ; if ( isIntN ( STI . hasMSA ( ) ? 10 : 16 , MaxSPOffset ) && ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ) return ; const TargetRegisterClass & RC = ABI . ArePtrs64bit ( ) ? Mips :: GPR64RegClass : Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlign ( RC ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> bool RedundantInstrElimination :: processBlock ( MachineBasicBlock & B , const RegisterSet & ) { if ( ! BT . reached ( & B ) ) return false ; bool Changed = false ; for ( auto I = B . begin ( ) , E = B . end ( ) , NextI = I ; I != E ; ++ I ) { NextI = std :: next ( I ) ; MachineInstr * MI = & * I ; if ( MI -> getOpcode ( ) == TargetOpcode :: COPY ) continue ; if ( MI -> isPHI ( ) || MI -> hasUnmodeledSideEffects ( ) || MI -> isInlineAsm ( ) ) continue ; unsigned NumD = MI -> getDesc ( ) . getNumDefs ( ) ; if ( NumD != 1 ) continue ; BitTracker :: RegisterRef RD = MI -> getOperand ( 0 ) ; if ( ! BT . has ( RD . Reg ) ) continue ; const BitTracker :: RegisterCell & DC = BT . lookup ( RD . Reg ) ; auto At = MachineBasicBlock :: iterator ( MI ) ; for ( auto & Op : MI -> uses ( ) ) { if ( ! Op . isReg ( ) ) continue ; BitTracker :: RegisterRef RS = Op ; if ( ! BT . has ( RS . Reg ) ) continue ; if ( ! HBS :: isTransparentCopy ( RD , RS , MRI ) ) continue ; unsigned BN , BW ; if ( ! HBS :: getSubregMask ( RS , BN , BW , MRI ) ) continue ; const BitTracker :: RegisterCell & SC = BT . lookup ( RS . Reg ) ; if ( ! usedBitsEqual ( RD , RS ) && ! HBS :: isEqual ( DC , 0 , SC , BN , BW ) ) continue ; const DebugLoc & DL = MI -> getDebugLoc ( ) ; const TargetRegisterClass * FRC = HBS :: getFinalVRegClass ( RD , MRI ) ; unsigned NewR = MRI . createVirtualRegister ( FRC ) ; MachineInstr * CopyI = BuildMI ( B , At , DL , HII . get ( TargetOpcode :: COPY ) , NewR ) . addReg ( RS . Reg , 0 , RS . Sub ) ; HBS :: replaceSubWithSub ( RD . Reg , RD . Sub , NewR , 0 , MRI ) ; BT . visit ( * CopyI ) ; Changed = true ; break ; } } return Changed ; } </s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s> static bool is_end_basic_block ( enum dispatch_group group ) { return group == disp_branch ; } </s>

This function returns true if a branch is detected . End of a basic block does not have to be a branch , but here we assume only branches end a window .


<s>
StringRef
getPassName
(
)
const
override
{
return
"SystemZ Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> int VESubtarget :: getAdjustedFrameSize ( int frameSize ) const { frameSize += 176 ; frameSize = alignTo ( frameSize , 16 ) ; return frameSize ; } </s>

Given a actual stack size as determined by FrameInfo , this function returns adjusted framesize which includes space for RSA , return address , and frame poitner .


<s> static int stackSlotSize ( ) { return 16 ; } </s>


<s> static const char * cond_name_x ( int code ) { if ( cc_prev_status . flags & CC_NO_OVERFLOW ) { switch ( code ) { case LT : return "mi" ; case GE : return "pl" ; } } switch ( code ) { case EQ : return "eq" ; case NE : return "ne" ; case LT : return "lt" ; case LE : return "le" ; case GT : return "gt" ; case GE : return "ge" ; case LTU : return "ult" ; case LEU : return "ule" ; case GTU : return "ugt" ; case GEU : return "uge" ; default : abort ( ) ; } } </s>

z8k "mi" "pl" "eq" "ne" "lt" "le" "gt" "ge" "ult" "ule" "ugt" "uge"


<s> static tree spu_builtin_mask_for_load ( void ) { return spu_builtin_decls [ SPU_MASK_FOR_LOAD ] ; } </s>


<s> bool PPCInstrInfo :: FoldImmediate ( MachineInstr & UseMI , MachineInstr & DefMI , Register Reg , MachineRegisterInfo * MRI ) const { bool Changed = onlyFoldImmediate ( UseMI , DefMI , Reg ) ; if ( MRI -> use_nodbg_empty ( Reg ) ) DefMI . eraseFromParent ( ) ; return Changed ; } </s>

Reg is known to be defined by a move immediate instruction , try to fold the immediate into the use instruction .


<s> bool MSP430AsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal . lower ( ) == ".long" ) { ParseLiteralValues ( 4 , DirectiveID . getLoc ( ) ) ; } else if ( IDVal . lower ( ) == ".word" || IDVal . lower ( ) == ".short" ) { ParseLiteralValues ( 2 , DirectiveID . getLoc ( ) ) ; } else if ( IDVal . lower ( ) == ".byte" ) { ParseLiteralValues ( 1 , DirectiveID . getLoc ( ) ) ; } else if ( IDVal . lower ( ) == ".refsym" ) { return ParseDirectiveRefSym ( DirectiveID ) ; } return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> MCSection * AMDGPUTargetObjectFile :: getExplicitSectionGlobal ( const GlobalObject * GO , SectionKind SK , const TargetMachine & TM ) const { StringRef SectionName = GO -> getSection ( ) ; if ( SectionName . startswith ( ".AMDGPU.comment." ) ) SK = SectionKind :: getMetadata ( ) ; return TargetLoweringObjectFileELF :: getExplicitSectionGlobal ( GO , SK , TM ) ; } </s>

Targets should implement this method to assign a section to globals with an explicit section specfied .


<s> inline bool function_call_info :: function_returns_void_p ( ) { return TREE_TYPE ( TREE_TYPE ( fndecl ) ) == void_type_node ; } </s>

Return true if the function has no return value .


"The function works only with LEA instructions"


<s> iterator end ( ) { return Blocks . rend ( ) ; } </s>

Get a const_iterator to the end of the symbol table .


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCRelaxableFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
{
llvm_unreachable
(
"relaxInstruction() unimplemented"
)
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s>
bool
ARMPassConfig
::
addPreSched2
(
)
{
if
(
getOptLevel
(
)
!=
CodeGenOpt
::
)
{
if
(
!
getARMSubtarget
(
)
.
isThumb1Only
(
)
)
{
addPass
(
createARMLoadStoreOptimizationPass
(
)
)
;
printAndVerify
(
"After ARM load / store optimizer"
)
;
}
if
(
getARMSubtarget
(
)
.
hasNEON
(
)
)
addPass
(
createExecutionDependencyFixPass
(
&
ARM
::
DPRRegClass
)
)
;
}
addPass
(
createARMExpandPseudoPass
(
)
)
;
if
(
getOptLevel
(
)
!=
CodeGenOpt
::
)
{
if
(
!
getARMSubtarget
(
)
.
isThumb1Only
(
)
)
{
if
(
getARMSubtarget
(
)
.
restrictIT
(
)
&&
!
getARMSubtarget
(
)
.
prefers32BitThumb
(
)
)
addPass
(
createThumb2SizeReductionPass
(
)
)
;
addPass
(
&
IfConverterID
)
;
}
}
if
(
getARMSubtarget
(
)
.
isThumb2
(
)
)
addPass
(
createThumb2ITBlockPass
(
)
)
;
return
true
;
}
</s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .

ARM
ARM
ARM
ARM
"After ARM load / store optimizer"
ARM
ARM::DPRRegClass
ARM
ARM
ARM
ARM
ARM


<s> static int64_t getConstant ( const MachineInstr * MI ) { return MI -> getOperand ( 1 ) . getCImm ( ) -> getSExtValue ( ) ; } </s>

Return the large constant at the given index .


<s> bool KudeyarPassConfig :: addPreEmitPass ( ) { return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , CM , OL ) , TargetABI ( computeTargetABI ( TT , CPU , Options ) ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) { if ( TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF || TargetTriple . getEnvironment ( ) == Triple :: EABIHF || TargetTriple . isOSWindows ( ) || TargetABI == ARMBaseTargetMachine :: ARM_ABI_AAPCS16 ) this -> Options . FloatABIType = FloatABI :: Hard ; else this -> Options . FloatABIType = FloatABI :: Soft ; } if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( ( TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABI || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF ) && ! ( TargetTriple . isOSWindows ( ) || TargetTriple . isOSDarwin ( ) ) ) this -> Options . EABIVersion = EABI :: GNU ; else this -> Options . EABIVersion = EABI :: EABI5 ; } initAsmInfo ( ) ; } </s>


<s> void XCoreInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) && ! I -> isDebugInstr ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlign ( FrameIndex ) ) ; BuildMI ( MBB , I , DL , get ( XCore :: STWFI ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) . addMemOperand ( MMO ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> void MipsAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( MI -> isDebugValue ( ) ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; PrintDebugValueComment ( MI , OS ) ; return ; } if ( emitPseudoExpansionLowering ( OutStreamer , MI ) ) return ; MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { MCInst TmpInst0 ; MCInstLowering . Lower ( I ++ , TmpInst0 ) ; OutStreamer . EmitInstruction ( TmpInst0 ) ; } while ( ( I != E ) && I -> isInsideBundle ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void SparcPassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> bool swiftAsyncContextIsDynamicallySet ( ) const { const Triple & TT = getTargetTriple ( ) ; unsigned Major , Minor , Micro ; TT . getOSVersion ( Major , Minor , Micro ) ; switch ( TT . getOS ( ) ) { default : return false ; case Triple :: IOS : case Triple :: TvOS : return Major < 15 ; case Triple :: WatchOS : return Major < 8 ; case Triple :: MacOSX : case Triple :: Darwin : return Major < 12 ; } } </s>

Return whether FrameLowering should always set the `` extended frame present '' bit in FP , or set it based on a symbol in the runtime .


<s> bool ARMPassConfig :: addPreEmitPass ( ) { if ( getARMSubtarget ( ) . isThumb2 ( ) ) { if ( ! getARMSubtarget ( ) . prefers32BitThumb ( ) ) addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( & UnpackMachineBundlesID ) ; } addPass ( createARMConstantIslandPass ( ) ) ; return true ; } </s>


<s> MCOperand SystemZMCInstLower :: lowerOperand ( const MachineOperand & MO ) const { switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : return MCOperand :: createReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: createImm ( MO . getImm ( ) ) ; default : { MCSymbolRefExpr :: VariantKind Kind = getVariantKind ( MO . getTargetFlags ( ) ) ; return MCOperand :: createExpr ( getExpr ( MO , Kind ) ) ; } } } </s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> static rtx pa_function_value ( const_tree valtype , const_tree func ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode valmode ; if ( AGGREGATE_TYPE_P ( valtype ) || TREE_CODE ( valtype ) == COMPLEX_TYPE || TREE_CODE ( valtype ) == VECTOR_TYPE ) { HOST_WIDE_INT valsize = int_size_in_bytes ( valtype ) ; if ( ( valsize & ( UNITS_PER_WORD - 1 ) ) == 0 ) return gen_rtx_REG ( TYPE_MODE ( valtype ) , 28 ) ; if ( TARGET_64BIT ) { rtx loc [ 2 ] ; int i , offset = 0 ; int ub = valsize <= UNITS_PER_WORD ? 1 : 2 ; for ( i = 0 ; i < ub ; i ++ ) { loc [ i ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , 28 + i ) , GEN_INT ( offset ) ) ; offset += 8 ; } return gen_rtx_PARALLEL ( BLKmode , gen_rtvec_v ( ub , loc ) ) ; } else if ( valsize > UNITS_PER_WORD ) { rtx loc = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , 28 ) , const0_rtx ) ; return gen_rtx_PARALLEL ( BLKmode , gen_rtvec ( 1 , loc ) ) ; } } if ( ( INTEGRAL_TYPE_P ( valtype ) && GET_MODE_BITSIZE ( TYPE_MODE ( valtype ) ) < BITS_PER_WORD ) || POINTER_TYPE_P ( valtype ) ) valmode = word_mode ; else valmode = TYPE_MODE ( valtype ) ; if ( TREE_CODE ( valtype ) == REAL_TYPE && ! AGGREGATE_TYPE_P ( valtype ) && TYPE_MODE ( valtype ) != TFmode && ! TARGET_SOFT_FLOAT ) return gen_rtx_REG ( valmode , 32 ) ; return gen_rtx_REG ( valmode , 28 ) ; } </s>

On the HP-PA the value is found in register ( s ) 28 ( -29 ) , unless the mode is SF or DF . Then the value is returned in fr4 ( 32 ) . This must perform the same promotions as PROMOTE_MODE , else promoting return values in TARGET_PROMOTE_FUNCTION_MODE will not work correctly . Small structures must be returned in a PARALLEL on PA64 in order to match the HP Compiler ABI .


"Comet2 DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> rtx_insn * sh_check_add_incdec_notes ( rtx_insn * i ) { struct for_each_inc_dec_clb { static int func ( rtx mem ATTRIBUTE_UNUSED , rtx op ATTRIBUTE_UNUSED , rtx dest , rtx src ATTRIBUTE_UNUSED , rtx srcoff ATTRIBUTE_UNUSED , void * arg ) { gcc_assert ( REG_P ( dest ) ) ; rtx_insn * i = ( rtx_insn * ) arg ; if ( find_regno_note ( i , REG_INC , REGNO ( dest ) ) == NULL ) add_reg_note ( i , REG_INC , dest ) ; return 0 ; } } ; for_each_inc_dec ( PATTERN ( i ) , for_each_inc_dec_clb :: func , i ) ; return i ; } </s>

Given an insn check if it contains any post/pre inc/dec mem operands and add the REG_INC notes accordingly . FIXME : This function is very similar to lra.cc ( add_auto_inc_notes ) . FIXME : This function is currently used by peephole2 patterns because the peephole2 pass does not preserve REG_INC notes . If the notes are dropped the following passes will do wrong things .


<s>
void
s390_indirect_branch_via_thunk
(
unsigned
int
regno
,
unsigned
int
return_addr_regno
,
rtx
comparison_operator
,
enum
s390_indirect_branch_type
type
)
{
enum
s390_indirect_branch_option
option
;
if
(
type
==
s390_indirect_branch_type_return
)
{
if
(
s390_return_addr_from_memory
(
)
)
option
=
s390_opt_function_return_mem
;
else
option
=
s390_opt_function_return_reg
;
}
else
if
(
type
==
s390_indirect_branch_type_jump
)
option
=
s390_opt_indirect_branch_jump
;
else
if
(
type
==
s390_indirect_branch_type_call
)
option
=
s390_opt_indirect_branch_call
;
else
gcc_unreachable
(
)
;
if
(
TARGET_INDIRECT_BRANCH_TABLE
)
{
char
label
[
32
]
;
ASM_GENERATE_INTERNAL_LABEL
(
label
,
indirect_branch_table_label
[
option
]
,
indirect_branch_table_label_no
[
option
]
++
)
;
ASM_OUTPUT_LABEL
(
asm_out_file
,
label
)
;
}
if
(
return_addr_regno
!=
INVALID_REGNUM
)
{
gcc_assert
(
comparison_operator
==
NULL_RTX
)
;
fprintf
(
asm_out_file
,
" \tbrasl\t%%r%d,"
,
return_addr_regno
)
;
}
else
{
fputs
(
" \tjg"
,
asm_out_file
)
;
if
(
comparison_operator
!=
NULL_RTX
)
print_operand
(
asm_out_file
,
comparison_operator
,
'C'
)
;
fputs
(
"\t"
,
asm_out_file
)
;
}
if
(
TARGET_CPU_Z10
)
fprintf
(
asm_out_file
,
TARGET_INDIRECT_BRANCH_THUNK_NAME_EXRL
"\n"
,
regno
)
;
else
fprintf
(
asm_out_file
,
TARGET_INDIRECT_BRANCH_THUNK_NAME_EX
"\n"
,
INDIRECT_BRANCH_THUNK_REGNUM
,
regno
)
;
if
(
(
option
==
s390_opt_indirect_branch_jump
&&
cfun
->
machine
->
indirect_branch_jump
==
indirect_branch_thunk
)
||
(
option
==
s390_opt_indirect_branch_call
&&
cfun
->
machine
->
indirect_branch_call
==
indirect_branch_thunk
)
||
(
option
==
s390_opt_function_return_reg
&&
cfun
->
machine
->
function_return_reg
==
indirect_branch_thunk
)
||
(
option
==
s390_opt_function_return_mem
&&
cfun
->
machine
->
function_return_mem
==
indirect_branch_thunk
)
)
{
if
(
TARGET_CPU_Z10
)
indirect_branch_z10thunk_mask
|=
(
1
<<
regno
)
;
else
indirect_branch_prez10thunk_mask
|=
(
1
<<
regno
)
;
}
}
</s>

Output either an indirect jump or a an indirect call ( RETURN_ADDR_REGNO ! = INVALID_REGNUM ) with target register REGNO using a branch trampoline disabling branch target prediction .


"Missing call preserved mask for calling convention"

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


<s>
void
print_operand
(
FILE
*
file
,
rtx
op
,
int
letter
)
{
switch
(
letter
)
{
case
'#'
:
if
(
final_sequence
)
visium_indent_opcode
=
1
;
else
fputs
(
"\n\t nop"
,
file
)
;
return
;
case
'b'
:
fprintf
(
file
,
HOST_WIDE_INT_PRINT_UNSIGNED
,
UINTVAL
(
op
)
&
0xff
)
;
return
;
case
'w'
:
fprintf
(
file
,
HOST_WIDE_INT_PRINT_UNSIGNED
,
UINTVAL
(
op
)
&
0xffff
)
;
return
;
case
'u'
:
fprintf
(
file
,
HOST_WIDE_INT_PRINT_UNSIGNED
,
(
UINTVAL
(
op
)
>>
16
)
&
0xffff
)
;
return
;
case
'r'
:
if
(
GET_CODE
(
op
)
==
REG
)
fputs
(
reg_names
[
REGNO
(
op
)
]
,
file
)
;
else
fputs
(
reg_names
[
0
]
,
file
)
;
return
;
case
'f'
:
if
(
GET_CODE
(
op
)
==
REG
)
fputs
(
reg_names
[
REGNO
(
op
)
]
,
file
)
;
else
fputs
(
reg_names
[
FP_FIRST_REGNUM
]
,
file
)
;
return
;
}
switch
(
GET_CODE
(
op
)
)
{
case
REG
:
if
(
letter
==
'd'
)
fputs
(
reg_names
[
REGNO
(
op
)
+
1
]
,
file
)
;
else
fputs
(
reg_names
[
REGNO
(
op
)
]
,
file
)
;
break
;
case
SYMBOL_REF
:
case
LABEL_REF
:
case
CONST
:
output_addr_const
(
file
,
op
)
;
break
;
case
MEM
:
visium_output_address
(
file
,
GET_MODE
(
op
)
,
XEXP
(
op
,
0
)
)
;
break
;
case
CONST_INT
:
fprintf
(
file
,
HOST_WIDE_INT_PRINT_DEC
,
INTVAL
(
op
)
)
;
break
;
case
CODE_LABEL
:
asm_fprintf
(
file
,
"%LL%d"
,
CODE_LABEL_NUMBER
(
op
)
)
;
break
;
case
HIGH
:
print_operand
(
file
,
XEXP
(
op
,
1
)
,
letter
)
;
break
;
default
:
fatal_insn
(
"illegal operand "
,
op
)
;
}
}
</s>

Use S for SI regsUse B & T for parts of DI regs X - stack pointer name Registers Q - byte sized register name U - high byte of word register V - low byte of word register H - word register name I - next word register name S & B - long register name T - next long register name D - quad register name P - register name in size of pointer Integers O - log two of value P - inverted log two H - bottom 16 bits I - top 16 bits N - negative B - high 32 bits of 32bit number . default : value Memory I - adjusted upwards by two T - adjusted upwards by four default : value Address H - low 16 bits I - high 16 bits A - as long constant S - as A but with # default : error Misc C - conditional name D - reverse conditional name F - clear v flag if necessary


<s> const rvexInstrInfo * getInstrInfo ( ) { return getTargetMachine ( ) . getInstrInfo ( ) ; } </s>


<s> static bool vsetvl_insn_p ( rtx_insn * rinsn ) { if ( ! vector_config_insn_p ( rinsn ) ) return false ; return ( INSN_CODE ( rinsn ) == CODE_FOR_vsetvldi || INSN_CODE ( rinsn ) == CODE_FOR_vsetvlsi ) ; } </s>

Return true if it is vsetvldi or vsetvlsi .


<s> const TargetRegisterClass * PPCRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { if ( Kind == 1 ) { if ( Subtarget . isPPC64 ( ) ) return & PPC :: G8RC_NOX0RegClass ; return & PPC :: GPRC_NOR0RegClass ; } if ( Subtarget . isPPC64 ( ) ) return & PPC :: G8RCRegClass ; return & PPC :: GPRCRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( 1 , true , true , false , true ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedLoadCombinePass ( ) ) ; addPass ( createInterleavedAccessPass ( ) ) ; } if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } addPass ( createAArch64StackTaggingPass ( ) ) ; if ( PACStack :: doAArch64IRPass ( ) ) addPass ( PACStack :: createPACStackOptCallPass ( ) ) ; } </s>


<s> bool RISCVFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> void RISCVFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; Align StackAlign = getStackAlign ( ) ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI . setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s> bool AMDGPUPassConfig :: addPreEmitPass ( ) { const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) { addPass ( createAMDGPUCFGStructurizerPass ( * TM ) ) ; addPass ( createR600ExpandSpecialInstrsPass ( * TM ) ) ; addPass ( & FinalizeMachineBundlesID ) ; addPass ( createR600Packetizer ( * TM ) ) ; addPass ( createR600ControlFlowFinalizer ( * TM ) ) ; } else { addPass ( createSILowerControlFlowPass ( * TM ) ) ; } return false ; } </s>


<s> bool AMDGPUAnnotateUniformValues :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; DA = & getAnalysis < LegacyDivergenceAnalysis > ( ) ; MSSA = & getAnalysis < MemorySSAWrapperPass > ( ) . getMSSA ( ) ; isEntryFunc = AMDGPU :: isEntryFunctionCC ( F . getCallingConv ( ) ) ; visit ( F ) ; noClobberClones . clear ( ) ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static bool note_invalid_constants ( rtx insn , HOST_WIDE_INT address , int do_pushes ) { bool result = false ; int opno ; extract_insn ( insn ) ; if ( ! constrain_operands ( 1 ) ) fatal_insn_not_found ( insn ) ; if ( recog_data . n_alternatives == 0 ) return false ; preprocess_constraints ( ) ; for ( opno = 0 ; opno < recog_data . n_operands ; opno ++ ) { if ( recog_data . operand_type [ opno ] != OP_IN ) continue ; if ( recog_op_alt [ opno ] [ which_alternative ] . memory_ok ) { rtx op = recog_data . operand [ opno ] ; if ( CONSTANT_P ( op ) ) { if ( do_pushes ) push_minipool_fix ( insn , address , recog_data . operand_loc [ opno ] , recog_data . operand_mode [ opno ] , op ) ; result = true ; } else if ( GET_CODE ( op ) == MEM && GET_CODE ( XEXP ( op , 0 ) ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( XEXP ( op , 0 ) ) ) { if ( do_pushes ) { rtx cop = avoid_constant_pool_reference ( op ) ; if ( op == cop ) cop = get_pool_constant ( XEXP ( op , 0 ) ) ; push_minipool_fix ( insn , address , recog_data . operand_loc [ opno ] , recog_data . operand_mode [ opno ] , cop ) ; } result = true ; } } } return result ; } </s>

Scan INSN and note any of its operands that need fixing . If DO_PUSHES is false we do not actually push any of the fixups needed . The function returns TRUE if any fixups were needed/pushed . This is used by arm_memory_load_p ( ) which needs to know about loads of constants that will be converted into minipool loads .


<s> void nvptx_output_skip ( FILE * , unsigned HOST_WIDE_INT size ) { if ( init_frag . offset ) { unsigned part = init_frag . size - init_frag . offset ; if ( part > size ) part = ( unsigned ) size ; size -= part ; nvptx_assemble_value ( 0 , part ) ; } if ( size < init_frag . remaining * init_frag . size ) { while ( size >= init_frag . size ) { size -= init_frag . size ; output_init_frag ( NULL_RTX ) ; } if ( size ) nvptx_assemble_value ( 0 , size ) ; } } </s>

Output SIZE zero bytes . We ignore the FILE argument since the functions we 're calling to perform the output just use asm_out_file .


<s> bool NVPTXInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . end ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) return false ; MachineInstr & LastInst = * I ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { if ( LastInst . getOpcode ( ) == NVPTX :: GOTO ) { TBB = LastInst . getOperand ( 0 ) . getMBB ( ) ; return false ; } else if ( LastInst . getOpcode ( ) == NVPTX :: CBranch ) { TBB = LastInst . getOperand ( 1 ) . getMBB ( ) ; Cond . push_back ( LastInst . getOperand ( 0 ) ) ; return false ; } return true ; } MachineInstr & SecondLastInst = * I ; if ( I != MBB . begin ( ) && isUnpredicatedTerminator ( * -- I ) ) return true ; if ( SecondLastInst . getOpcode ( ) == NVPTX :: CBranch && LastInst . getOpcode ( ) == NVPTX :: GOTO ) { TBB = SecondLastInst . getOperand ( 1 ) . getMBB ( ) ; Cond . push_back ( SecondLastInst . getOperand ( 0 ) ) ; FBB = LastInst . getOperand ( 0 ) . getMBB ( ) ; return false ; } if ( SecondLastInst . getOpcode ( ) == NVPTX :: GOTO && LastInst . getOpcode ( ) == NVPTX :: GOTO ) { TBB = SecondLastInst . getOperand ( 0 ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } return true ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


" is return block without RETURN instr\n"

Convenience function that returns true if the block ends in a return instruction .


<s> unsigned ARMBaseInstrInfo :: predictBranchSizeForIfCvt ( MachineInstr & MI ) const { if ( MI . getOpcode ( ) == ARM :: t2Bcc && findCMPToFoldIntoCBZ ( & MI , & getRegisterInfo ( ) ) ) return 0 ; unsigned Size = getInstSizeInBytes ( MI ) ; if ( Subtarget . isThumb2 ( ) ) Size /= 2 ; return Size ; } </s>

Return an estimate for the code size reduction ( in bytes ) which will be caused by removing the given branch instruction during if-conversion .


<s> MCELFStreamer & M88kTargetELFStreamer :: getStreamer ( ) { return static_cast < MCELFStreamer & > ( Streamer ) ; } </s>

Return the output streamer for the assembler .


<s> static bool ft32_fixed_condition_code_regs ( unsigned int * p1 , unsigned int * p2 ) { * p1 = CC_REG ; * p2 = INVALID_REGNUM ; return true ; } </s>

Return the fixed registers used for condition codes .


<s>
static
tree
ix86_handle_fentry_name
(
tree
*
node
,
tree
name
,
tree
args
,
int
,
bool
*
no_add_attrs
)
{
if
(
TREE_CODE
(
*
node
)
==
FUNCTION_DECL
&&
TREE_CODE
(
TREE_VALUE
(
args
)
)
==
STRING_CST
)
;
else
{
warning
(
OPT_Wattributes
,
"%qE attribute ignored"
,
name
)
;
*
no_add_attrs
=
true
;
}
return
NULL_TREE
;
}
</s>

Handle fentry_name / fentry_section attribute .


"Cannot store this register to stack slot!"

Load the specified register of the given register class from the specified stack frame index .


<s> void MipsTargetMachine :: resetSubtarget ( MachineFunction * MF ) { DEBUG ( dbgs ( ) << "resetSubtarget\n" ) ; Subtarget = const_cast < MipsSubtarget * > ( getSubtargetImpl ( * MF -> getFunction ( ) ) ) ; MF -> setSubtarget ( Subtarget ) ; } </s>

Reset the subtarget for the Mips target .


<s> enum rtx_code pru_noteq_condition ( enum rtx_code code ) { switch ( code ) { case GT : return GT ; case GTU : return GTU ; case GE : return GT ; case GEU : return GTU ; case LT : return LT ; case LTU : return LTU ; case LE : return LT ; case LEU : return LTU ; default : gcc_unreachable ( ) ; } } </s>

Given a comparison CODE , return a similar comparison but without the `` equals '' condition . In other words , it strips GE/GEU/LE/LEU and instead returns GT/GTU/LT/LTU .


<s> const unsigned * MBlazeRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const unsigned CalleeSavedRegs [ ] = { MBlaze :: R20 , MBlaze :: R21 , MBlaze :: R22 , MBlaze :: R23 , MBlaze :: R24 , MBlaze :: R25 , MBlaze :: R26 , MBlaze :: R27 , MBlaze :: R28 , MBlaze :: R29 , MBlaze :: R30 , MBlaze :: R31 , 0 } ; return CalleeSavedRegs ; } </s>


<s> unsigned int nds32_local_alignment ( tree local ATTRIBUTE_UNUSED , unsigned int basic_align ) { bool at_least_align_to_word = false ; switch ( TREE_CODE ( local ) ) { case ARRAY_TYPE : case RECORD_TYPE : case UNION_TYPE : at_least_align_to_word = true ; break ; default : at_least_align_to_word = false ; break ; } if ( at_least_align_to_word && ( basic_align < BITS_PER_WORD ) ) return BITS_PER_WORD ; else return basic_align ; } </s>


<s> OffsetRange & intersect ( OffsetRange A ) { if ( Align < A . Align ) std :: swap ( * this , A ) ; if ( Offset >= A . Offset && ( Offset - A . Offset ) % A . Align == 0 ) { Min = adjustUp ( std :: max ( Min , A . Min ) , Align , Offset ) ; Max = adjustDown ( std :: min ( Max , A . Max ) , Align , Offset ) ; } else { Min = 0 ; Max = - 1 ; } if ( Min > Max ) std :: tie ( Min , Max , Align ) = std :: make_tuple ( 0 , - 1 , 1 ) ; return * this ; } </s>

Intersect this set with a temporary other set in place .


<s>
DFAPacketizer
*
rvexInstrInfo
::
CreateTargetScheduleState
(
const
TargetMachine
*
TM
,
const
ScheduleDAG
*
DAG
)
const
{
DEBUG
(
errs
(
)
<<
"Voor DFA!\n"
)
;
const
InstrItineraryData
*
II
=
TM
->
getInstrItineraryData
(
)
;
DEBUG
(
errs
(
)
<<
"Na DFA!\n"
)
;
DFAPacketizer
*
temp
=
TM
->
getSubtarget
<
rvexGenSubtargetInfo
>
(
)
.
createDFAPacketizer
(
II
)
;
DEBUG
(
errs
(
)
<<
"Na na DFA!\n"
)
;
return
temp
;
}
</s>

Create machine specific model for scheduling .

rvex
rvex
"Voor DFA!\n"
"Na DFA!\n"
rvex
"Na na DFA!\n"


<s> const MCPhysReg * SystemZRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const SystemZSubtarget * Subtarget = & MF -> getSubtarget < SystemZSubtarget > ( ) ; SystemZCallingConventionRegisters * Regs = Subtarget -> getSpecialRegisters ( ) ; return Regs -> getCalleeSavedRegs ( MF ) ; } </s>


<s> bool swiftAsyncContextIsDynamicallySet ( ) const { const Triple & TT = getTargetTriple ( ) ; unsigned Major , Minor , Micro ; TT . getOSVersion ( Major , Minor , Micro ) ; switch ( TT . getOS ( ) ) { default : return false ; case Triple :: IOS : case Triple :: TvOS : return Major < 15 ; case Triple :: WatchOS : return Major < 8 ; case Triple :: MacOSX : case Triple :: Darwin : return Major < 12 ; } } </s>

Return whether FrameLowering should always set the `` extended frame present '' bit in FP , or set it based on a symbol in the runtime .


<s> static int flags_needed_for_conditional ( rtx cond ) { switch ( GET_CODE ( cond ) ) { case LE : case GT : return FLAGS_OSZ ; case LEU : case GTU : return FLAGS_ZC ; case LT : case GE : return FLAGS_OS ; case LTU : case GEU : return FLAGS_C ; case EQ : case NE : return FLAGS_Z ; default : return FLAGS_N ; } } </s>

Indicate which flags must be properly set for a given conditional .


<s> bool shouldOmitSectionDirective ( StringRef SectionName ) const override { return true ; } </s>

Return true if the .section directive should be omitted when emitting SectionName .


<s> bool DCPU16FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) BuildMI ( MBB , MI , DL , TII . get ( DCPU16 :: POP16r ) , CSI [ i ] . getReg ( ) ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static void mips_multi_copy_insn ( unsigned int i ) { struct mips_multi_member * member ; member = mips_multi_add ( ) ; memcpy ( member , & mips_multi_members [ i ] , sizeof ( * member ) ) ; gcc_assert ( ! member -> is_label_p ) ; } </s>

Add a copy of an existing instruction to the current multi-insn sequence . I is the index of the instruction that should be copied .


<s> EVT ARMTargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return getPointerTy ( DL ) ; if ( ( Subtarget -> hasMVEIntegerOps ( ) && ( VT == MVT :: v4i32 || VT == MVT :: v8i16 || VT == MVT :: v16i8 ) ) || ( Subtarget -> hasMVEFloatOps ( ) && ( VT == MVT :: v4f32 || VT == MVT :: v8f16 ) ) ) return MVT :: getVectorVT ( MVT :: i1 , VT . getVectorElementCount ( ) ) ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


"cannot return value in vector register because"

" altivec instructions are disabled, use -maltivec"

Handle the INIT_CUMULATIVE_ARGS macro . Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is 0 .


<s>
CCAssignFn
*
AArch64TargetLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
const
{
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention."
)
;
case
CallingConv
::
WebKit_JS
:
return
CC_AArch64_WebKit_JS
;
case
CallingConv
::
GHC
:
return
CC_AArch64_GHC
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
case
CallingConv
::
PreserveMost
:
case
CallingConv
::
CXX_FAST_TLS
:
if
(
!
Subtarget
->
isTargetDarwin
(
)
)
return
CC_AArch64_AAPCS
;
return
IsVarArg
CC_AArch64_DarwinPCS_VarArg
:
CC_AArch64_DarwinPCS
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> bool allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace = 0 , unsigned Align = 1 , bool * Fast = nullptr ) const override { if ( RequireStrictAlign ) return false ; if ( Fast ) * Fast = true ; return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


"Instruction should be in a basic block!"

"Generic instr has unexpected implicit operands\n"

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s> bool isReg ( ) const override { return Kind == Register && Reg . Modifiers == - 1 ; } </s>


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Mips Native Client Rewrite Pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
StringRef
getPassName
(
)
const
override
{
return
"ARM Instruction Selection"
;
}
</s>


<s> int s390_O_constraint_str ( const char c , HOST_WIDE_INT value ) { if ( ! TARGET_EXTIMM ) return 0 ; switch ( c ) { case 's' : return trunc_int_for_mode ( value , SImode ) == value ; case 'p' : return value == 0 || s390_single_part ( GEN_INT ( value ) , DImode , SImode , 0 ) == 1 ; case 'n' : return s390_single_part ( GEN_INT ( value - 1 ) , DImode , SImode , - 1 ) == 1 ; default : gcc_unreachable ( ) ; } } </s>

Evaluates constraint strings starting with letter O . Input parameter C is the second letter following the `` O '' in the constraint string . Returns 1 if VALUE meets the respective constraint and 0 otherwise .


<s> const TOYRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> static void mep_reload_pointer ( int regno , const char * symbol ) { rtx reg , sym ; if ( ! df_regs_ever_live_p ( regno ) && crtl -> is_leaf ) return ; reg = gen_rtx_REG ( SImode , regno ) ; sym = gen_rtx_SYMBOL_REF ( SImode , symbol ) ; emit_insn ( gen_movsi_topsym_s ( reg , sym ) ) ; emit_insn ( gen_movsi_botsym_s ( reg , reg , sym ) ) ; } </s>

Used for interrupt functions , which ca n't assume that $ tp and $ gp contain the correct pointers .


<s>
static
void
nvptx_assemble_decl_begin
(
FILE
*
file
,
const
char
*
name
,
const
char
*
section
,
const_tree
type
,
HOST_WIDE_INT
size
,
unsigned
align
)
{
while
(
TREE_CODE
(
type
)
==
ARRAY_TYPE
)
type
=
TREE_TYPE
(
type
)
;
if
(
TREE_CODE
(
type
)
==
VECTOR_TYPE
||
TREE_CODE
(
type
)
==
COMPLEX_TYPE
)
type
=
TREE_TYPE
(
type
)
;
unsigned
elt_size
=
int_size_in_bytes
(
type
)
;
machine_mode
elt_mode
=
TYPE_MODE
(
type
)
==
BLKmode
Pmode
:
DImode
;
elt_size
|=
GET_MODE_SIZE
(
elt_mode
)
;
elt_size
&=
elt_size
;
init_frag
.
size
=
elt_size
;
init_frag
.
mask
=
(
(
unsigned
HOST_WIDE_INT
)
2
<<
(
elt_size
*
BITS_PER_UNIT
1
)
)
1
;
init_frag
.
val
=
0
;
init_frag
.
offset
=
0
;
init_frag
.
started
=
false
;
init_frag
.
remaining
=
(
size
+
elt_size
1
)
/
elt_size
;
fprintf
(
file
,
"%s .align %d .u%d "
,
section
,
align
/
BITS_PER_UNIT
,
elt_size
*
BITS_PER_UNIT
)
;
assemble_name
(
file
,
name
)
;
if
(
size
)
fprintf
(
file
,
"["
HOST_WIDE_INT_PRINT_DEC
"]"
,
init_frag
.
remaining
)
;
}
</s>

Emit a PTX variable decl and prepare for emission of its initializer . NAME is the symbol name and SETION the PTX data area . The type is TYPE , object size SIZE and alignment is ALIGN . The caller has already emitted any indentation and linkage specifier . It is responsible for any initializer , terminating ; and newline . SIZE is in bytes , ALIGN is in bits -- confusingly this is the opposite way round that PTX wants them !


<s> MachineInstr * X86InstrInfo :: optimizeLoadInstr ( MachineInstr & MI , const MachineRegisterInfo * MRI , unsigned & FoldAsLoadDefReg , MachineInstr * & DefMI ) const { if ( FoldAsLoadDefReg == 0 ) return nullptr ; if ( MI . mayLoad ( ) ) { FoldAsLoadDefReg = 0 ; return nullptr ; } DefMI = MRI -> getVRegDef ( FoldAsLoadDefReg ) ; assert ( DefMI ) ; bool SawStore = false ; if ( ! DefMI -> isSafeToMove ( nullptr , SawStore ) ) return nullptr ; unsigned SrcOperandId = 0 ; bool FoundSrcOperand = false ; for ( unsigned i = 0 , e = MI . getDesc ( ) . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg != FoldAsLoadDefReg ) continue ; if ( MO . getSubReg ( ) || MO . isDef ( ) || FoundSrcOperand ) return nullptr ; SrcOperandId = i ; FoundSrcOperand = true ; } if ( ! FoundSrcOperand ) return nullptr ; if ( MachineInstr * FoldMI = foldMemoryOperand ( MI , SrcOperandId , * DefMI ) ) { FoldAsLoadDefReg = 0 ; return FoldMI ; } return nullptr ; } </s>

optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use .


<s> static void ix86_emit_cmove ( rtx dst , rtx src , enum rtx_code code , rtx op1 , rtx op2 ) { rtx t ; if ( TARGET_CMOVE ) { t = ix86_expand_compare ( code , op1 , op2 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dst , gen_rtx_IF_THEN_ELSE ( GET_MODE ( dst ) , t , src , dst ) ) ) ; } else { rtx nomove = gen_label_rtx ( ) ; emit_cmp_and_jump_insns ( op1 , op2 , reverse_condition ( code ) , const0_rtx , GET_MODE ( op1 ) , 1 , nomove ) ; emit_move_insn ( dst , src ) ; emit_label ( nomove ) ; } } </s>

Emit conditional move of SRC to DST with condition OP1 CODE OP2 .


<s> unsigned MipsInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { default : return MI . getDesc ( ) . getSize ( ) ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } case Mips :: CONSTPOOL_ENTRY : return MI . getOperand ( 2 ) . getImm ( ) ; } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> bool AArch64AsmParser :: ParseDirective ( AsmToken DirectiveID ) { const MCObjectFileInfo :: Environment Format = getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ; bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; StringRef IDVal = DirectiveID . getIdentifier ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == ".arch" ) parseDirectiveArch ( Loc ) ; else if ( IDVal == ".cpu" ) parseDirectiveCPU ( Loc ) ; else if ( IDVal == ".tlsdesccall" ) parseDirectiveTLSDescCall ( Loc ) ; else if ( IDVal == ".ltorg" || IDVal == ".pool" ) parseDirectiveLtorg ( Loc ) ; else if ( IDVal == ".unreq" ) parseDirectiveUnreq ( Loc ) ; else if ( IDVal == ".inst" ) parseDirectiveInst ( Loc ) ; else if ( IDVal == ".cfi_negate_ra_state" ) parseDirectiveCFINegateRAState ( ) ; else if ( IsMachO ) { if ( IDVal == MCLOHDirectiveName ( ) ) parseDirectiveLOH ( IDVal , Loc ) ; else return true ; } else return true ; return false ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool isMem ( ) const override { return isMEMrri ( ) || isMEMrii ( ) || isMEMzri ( ) || isMEMzii ( ) || isMEMri ( ) || isMEMzi ( ) ; } </s>


<s> EVT MipsTargetLowering :: getSetCCResultType ( EVT VT ) const { return MVT :: i32 ; } </s>


<s> SMRange getLocRange ( ) const { return SMRange ( StartLoc , EndLoc ) ; } </s>

getLocRange - Get the range between the first and last token of this operand .


<s> virtual EVT getSetCCResultType ( EVT VT ) const { return MVT :: i32 ; } </s>


<s> unsigned MSP430RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? MSP430 :: FP : MSP430 :: SP ; } </s>


<s> TargetLoweringBase :: LegalizeTypeAction getPreferredVectorAction ( EVT VT ) const override { if ( VT . getScalarSizeInBits ( ) % 8 == 0 ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s> bool system_reg_operand ( rtx op , machine_mode mode ATTRIBUTE_UNUSED ) { switch ( REGNO ( op ) ) { case PR_REG : case MACL_REG : case MACH_REG : return true ; } return false ; } </s>

Returns 1 if OP is MACL , MACH or PR . The input must be a REG rtx . Used only in general_movsrc_operand .


<s>
void
MipsInstPrinter
::
printInst
(
const
MCInst
*
MI
,
uint64_t
Address
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
,
raw_ostream
&
O
)
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
Mips
::
RDHWR
:
case
Mips
::
RDHWR64
:
O
<<
"\t.set\tpush\n"
;
O
<<
"\t.set\tmips32r2\n"
;
break
;
case
Mips
::
Save16
:
O
<<
"\tsave\t"
;
printSaveRestore
(
MI
,
O
)
;
O
<<
" # 16 bit inst\n"
;
return
;
case
Mips
::
SaveX16
:
O
<<
"\tsave\t"
;
printSaveRestore
(
MI
,
O
)
;
O
<<
"\n"
;
return
;
case
Mips
::
Restore16
:
O
<<
"\trestore\t"
;
printSaveRestore
(
MI
,
O
)
;
O
<<
" # 16 bit inst\n"
;
return
;
case
Mips
::
RestoreX16
:
O
<<
"\trestore\t"
;
printSaveRestore
(
MI
,
O
)
;
O
<<
"\n"
;
return
;
}
if
(
!
printAliasInstr
(
MI
,
Address
,
O
)
&&
!
printAlias
(
*
MI
,
O
)
)
printInstruction
(
MI
,
Address
,
O
)
;
printAnnotation
(
O
,
Annot
)
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
Mips
::
RDHWR
:
case
Mips
::
RDHWR64
:
O
<<
"\n\t.set\tpop"
;
}
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s> bool PatmosInstPrinter :: isBundled ( const MCInst * MI ) const { return MI -> getOperand ( MI -> getNumOperands ( ) - 1 ) . getImm ( ) > 0 ; } </s>

Return true if this instruction part of a bundle .


<s> static void hwloop_fail ( hwloop_info loop ) { rtx test ; rtx_insn * insn = loop -> loop_end ; emit_insn_before ( gen_addsi3 ( loop -> iter_reg , loop -> iter_reg , constm1_rtx ) , loop -> loop_end ) ; test = gen_rtx_NE ( VOIDmode , loop -> iter_reg , const0_rtx ) ; insn = emit_jump_insn_before ( gen_cbranchsi4 ( test , loop -> iter_reg , const0_rtx , loop -> start_label ) , loop -> loop_end ) ; JUMP_LABEL ( insn ) = loop -> start_label ; LABEL_NUSES ( loop -> start_label ) ++ ; delete_insn ( loop -> loop_end ) ; } </s>

A callback for the hw-doloop pass . Called when a loop we have discovered turns out not to be optimizable ; we have to split the doloop_end pattern into a subtract and a test .


<s>
bool
AArch64InstrInfo
::
areMemAccessesTriviallyDisjoint
(
MachineInstr
&
MIa
,
MachineInstr
&
MIb
,
AliasAnalysis
*
AA
)
const
{
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
MachineOperand
*
BaseOpA
=
nullptr
,
*
BaseOpB
=
nullptr
;
int64_t
OffsetA
=
0
,
OffsetB
=
0
;
unsigned
WidthA
=
0
,
WidthB
=
0
;
assert
(
MIa
.
mayLoadOrStore
(
)
&&
"MIa must be a load or store."
)
;
assert
(
MIb
.
mayLoadOrStore
(
)
&&
"MIb must be a load or store."
)
;
if
(
MIa
.
hasUnmodeledSideEffects
(
)
||
MIb
.
hasUnmodeledSideEffects
(
)
||
MIa
.
hasOrderedMemoryRef
(
)
||
MIb
.
hasOrderedMemoryRef
(
)
)
return
false
;
if
(
getMemOperandWithOffsetWidth
(
MIa
,
BaseOpA
,
OffsetA
,
WidthA
,
TRI
)
&&
getMemOperandWithOffsetWidth
(
MIb
,
BaseOpB
,
OffsetB
,
WidthB
,
TRI
)
)
{
if
(
BaseOpA
->
isIdenticalTo
(
*
BaseOpB
)
)
{
int
LowOffset
=
OffsetA
<
OffsetB
OffsetA
:
OffsetB
;
int
HighOffset
=
OffsetA
<
OffsetB
OffsetB
:
OffsetA
;
int
LowWidth
=
(
LowOffset
==
OffsetA
)
WidthA
:
WidthB
;
if
(
LowOffset
+
LowWidth
<=
HighOffset
)
return
true
;
}
}
return
false
;
}
</s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> PreservedAnalyses BPFAdjustOptPass :: run ( Module & M , ModuleAnalysisManager & AM ) { return BPFAdjustOptImpl ( & M ) . run ( ) ? PreservedAnalyses :: none ( ) : PreservedAnalyses :: all ( ) ; } </s>

Run the analysis pass over a function and produce a dominator tree .


<s> const char * output_h8sx_shift ( rtx * operands , int suffix , int optype ) { static char buffer [ 16 ] ; const char * stem ; switch ( GET_CODE ( operands [ 3 ] ) ) { case ASHIFT : stem = "shll" ; break ; case ASHIFTRT : stem = "shar" ; break ; case LSHIFTRT : stem = "shlr" ; break ; case ROTATE : stem = "rotl" ; if ( INTVAL ( operands [ 2 ] ) > 2 ) { operands [ 2 ] = GEN_INT ( GET_MODE_BITSIZE ( GET_MODE ( operands [ 0 ] ) ) - INTVAL ( operands [ 2 ] ) ) ; stem = "rotr" ; } break ; default : gcc_unreachable ( ) ; } if ( operands [ 2 ] == const1_rtx ) sprintf ( buffer , "%s.%c\t%%%c0" , stem , suffix , optype ) ; else sprintf ( buffer , "%s.%c\t%%X2,%%%c0" , stem , suffix , optype ) ; return buffer ; } </s>

Return the asm template for a single h8sx shift instruction . OPERANDS [ 0 ] and OPERANDS [ 1 ] are the destination , OPERANDS [ 2 ] is the source and OPERANDS [ 3 ] is the shift . SUFFIX is the size suffix ( ' b ' , ' w ' or ' l ' ) and OPTYPE is the print_operand prefix for the destination operand .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"ARM Instruction Selection"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static rtx mips16e_save_restore_reg ( bool restore_p , bool reg_parm_p , HOST_WIDE_INT offset , unsigned int regno ) { rtx reg , mem ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; reg = gen_rtx_REG ( SImode , regno ) ; if ( restore_p ) { mips_add_cfa_restore ( reg ) ; return gen_rtx_SET ( VOIDmode , reg , mem ) ; } if ( reg_parm_p ) return gen_rtx_SET ( VOIDmode , mem , reg ) ; return mips_frame_set ( mem , reg ) ; } </s>

Return a move between register REGNO and memory location SP + OFFSET . REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE . Make the move a load if RESTORE_P , otherwise make it a store .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


"********** Prepare For LiveIntervals **********\n"

"LiveIntervals shouldn't be active yet!"

runOnMachineFunction - Emit the function body .


<s> void X86AsmPrinter :: emitFunctionBodyStart ( ) { if ( EmitFPOData ) { if ( auto * XTS = static_cast < X86TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ) XTS -> emitFPOProc ( CurrentFnSym , MF -> getInfo < X86MachineFunctionInfo > ( ) -> getArgumentStackSize ( ) ) ; } } </s>

Targets can override this to emit stuff before the first basic block in the function .


<s> void print ( raw_ostream & OS , const TargetMachine * TM = 0 ) const { if ( isReg ( ) ) { OS << PrintReg ( getReg ( ) ) ; } if ( isImm ( ) ) { OS << getImm ( ) ; } } </s>

print - Print a debug representation of the operand to the given stream .


<s> static bool ix86_optab_supported_p ( int op , machine_mode mode1 , machine_mode , optimization_type opt_type ) { switch ( op ) { case asin_optab : case acos_optab : case log1p_optab : case exp_optab : case exp10_optab : case exp2_optab : case expm1_optab : case ldexp_optab : case scalb_optab : case round_optab : return opt_type == OPTIMIZE_FOR_SPEED ; case rint_optab : if ( SSE_FLOAT_MODE_P ( mode1 ) && TARGET_SSE_MATH && ! flag_trapping_math && ! TARGET_SSE4_1 && mode1 != HFmode ) return opt_type == OPTIMIZE_FOR_SPEED ; return true ; case floor_optab : case ceil_optab : case btrunc_optab : if ( ( ( SSE_FLOAT_MODE_P ( mode1 ) && TARGET_SSE_MATH && TARGET_SSE4_1 ) || mode1 == HFmode ) && ! flag_trapping_math ) return true ; return opt_type == OPTIMIZE_FOR_SPEED ; case rsqrt_optab : return opt_type == OPTIMIZE_FOR_SPEED && use_rsqrt_p ( mode1 ) ; default : return true ; } } </s>

Implement the TARGET_OPTAB_SUPPORTED_P hook .


<s> poly_int64 riscv_v_adjust_bytesize ( machine_mode mode , int scale ) { if ( riscv_v_ext_vector_mode_p ( mode ) ) { poly_uint16 mode_size = GET_MODE_SIZE ( mode ) ; if ( maybe_eq ( mode_size , ( uint16_t ) - 1 ) ) mode_size = riscv_vector_chunks * scale ; if ( known_gt ( mode_size , BYTES_PER_RISCV_VECTOR ) ) mode_size = BYTES_PER_RISCV_VECTOR ; return mode_size ; } return scale ; } </s>

Call from ADJUST_BYTESIZE in riscv-modes.def . Return the correct BYTE size for corresponding machine_mode .


<s> bool isMem ( ) const override { return false ; } </s>


<s> void SparcFrameLowering :: emitPrologue ( MachineFunction & MF ) const { SparcMachineFunctionInfo * FuncInfo = MF . getInfo < SparcMachineFunctionInfo > ( ) ; MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const SparcInstrInfo & TII = * static_cast < const SparcInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; unsigned SAVEri = SP :: SAVEri ; unsigned SAVErr = SP :: SAVErr ; if ( FuncInfo -> isLeafProc ( ) ) { if ( NumBytes == 0 ) return ; SAVEri = SP :: ADDri ; SAVErr = SP :: ADDrr ; } NumBytes = - SubTarget . getAdjustedFrameSize ( NumBytes ) ; if ( NumBytes >= - 4096 ) { BuildMI ( MBB , MBBI , dl , TII . get ( SAVEri ) , SP :: O6 ) . addReg ( SP :: O6 ) . addImm ( NumBytes ) ; } else { unsigned OffHi = ( unsigned ) NumBytes >> 10U ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: SETHIi ) , SP :: G1 ) . addImm ( OffHi ) ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: ORri ) , SP :: G1 ) . addReg ( SP :: G1 ) . addImm ( NumBytes & ( ( 1 << 10 ) - 1 ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( SAVErr ) , SP :: O6 ) . addReg ( SP :: O6 ) . addReg ( SP :: G1 ) ; } MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; MCSymbol * FrameLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: PROLOG_LABEL ) ) . addSym ( FrameLabel ) ; unsigned regFP = MRI -> getDwarfRegNum ( SP :: I6 , true ) ; MMI . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( FrameLabel , regFP ) ) ; MMI . addFrameInst ( MCCFIInstruction :: createWindowSave ( FrameLabel ) ) ; unsigned regInRA = MRI -> getDwarfRegNum ( SP :: I7 , true ) ; unsigned regOutRA = MRI -> getDwarfRegNum ( SP :: O7 , true ) ; MMI . addFrameInst ( MCCFIInstruction :: createRegister ( FrameLabel , regOutRA , regInRA ) ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
READ_REGISTER
:
ExpandREAD_REGISTER
(
N
,
Results
,
DAG
)
;
break
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
case
ISD
::
SHL
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SREM
:
case
ISD
::
UREM
:
Res
=
LowerREM
(
N
,
DAG
)
;
break
;
case
ISD
::
SDIVREM
:
case
ISD
::
UDIVREM
:
Res
=
LowerDivRem
(
SDValue
(
N
,
0
)
,
DAG
)
;
assert
(
Res
.
getNumOperands
(
)
==
2
&&
"DivRem needs two values"
)
;
Results
.
push_back
(
Res
.
getValue
(
0
)
)
;
Results
.
push_back
(
Res
.
getValue
(
1
)
)
;
return
;
case
ISD
::
SADDSAT
:
case
ISD
::
SSUBSAT
:
Res
=
LowerSADDSUBSAT
(
SDValue
(
N
,
0
)
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
READCYCLECOUNTER
:
ReplaceREADCYCLECOUNTER
(
N
,
Results
,
DAG
,
Subtarget
)
;
return
;
case
ISD
::
UDIV
:
case
ISD
::
SDIV
:
assert
(
Subtarget
->
isTargetWindows
(
)
&&
"can only expand DIV on Windows"
)
;
return
ExpandDIV_Windows
(
SDValue
(
N
,
0
)
,
DAG
,
N
->
getOpcode
(
)
==
ISD
::
SDIV
,
Results
)
;
case
ISD
::
ATOMIC_CMP_SWAP
:
ReplaceCMP_SWAP_64Results
(
N
,
Results
,
DAG
)
;
return
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
ReplaceLongIntrinsic
(
N
,
Results
,
DAG
)
;
case
ISD
::
ABS
:
lowerABS
(
N
,
Results
,
DAG
)
;
return
;
case
ISD
::
LOAD
:
LowerLOAD
(
N
,
Results
,
DAG
)
;
break
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

ARM
ARM
"Don't know how to custom expand this!"
ISD::READ_REGISTER
ISD::BITCAST
ISD::SRL
ISD::SRA
ISD::SHL
ISD::SREM
ISD::UREM
ISD::SDIVREM
ISD::UDIVREM
0
2
"DivRem needs two values"
0
1
ISD::SADDSAT
ISD::SSUBSAT
0
ISD::READCYCLECOUNTER
ISD::UDIV
ISD::SDIV
"can only expand DIV on Windows"
0
ISD::SDIV
ISD::ATOMIC_CMP_SWAP
ISD::INTRINSIC_WO_CHAIN
ISD::ABS
ISD::LOAD


<s> BitVector WebAssemblyRegisterInfo :: getReservedRegs ( const MachineFunction & ) const { BitVector Reserved ( getNumRegs ( ) ) ; for ( auto Reg : { WebAssembly :: SP32 , WebAssembly :: SP64 , WebAssembly :: FP32 , WebAssembly :: FP64 } ) Reserved . set ( Reg ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool ARMInstrInfo :: SubsumesPredicate ( const SmallVectorImpl < MachineOperand > & Pred1 , const SmallVectorImpl < MachineOperand > & Pred2 ) const { if ( Pred1 . size ( ) > 2 || Pred2 . size ( ) > 2 ) return false ; ARMCC :: CondCodes CC1 = ( ARMCC :: CondCodes ) Pred1 [ 0 ] . getImm ( ) ; ARMCC :: CondCodes CC2 = ( ARMCC :: CondCodes ) Pred2 [ 0 ] . getImm ( ) ; if ( CC1 == CC2 ) return true ; switch ( CC1 ) { default : return false ; case ARMCC :: AL : return true ; case ARMCC :: HS : return CC2 == ARMCC :: HI ; case ARMCC :: LS : return CC2 == ARMCC :: LO || CC2 == ARMCC :: EQ ; case ARMCC :: GE : return CC2 == ARMCC :: GT ; case ARMCC :: LE : return CC2 == ARMCC :: LT ; } } </s>

Returns true if the first specified predicate subsumes the second , e.g .

ARM ARM 2 2 ARMCC::CondCodes ARMCC::CondCodes 0 ARMCC::CondCodes ARMCC::CondCodes 0 ARMCC::AL ARMCC::HS ARMCC::HI ARMCC::LS ARMCC::LO ARMCC::EQ ARMCC::GE ARMCC::GT ARMCC::LE ARMCC::LT


<s> void PPCELFStreamer :: emitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) { PPCMCCodeEmitter * Emitter = static_cast < PPCMCCodeEmitter * > ( getAssembler ( ) . getEmitterPtr ( ) ) ; Optional < bool > IsPartOfGOTToPCRelPair = isPartOfGOTToPCRelPair ( Inst , STI ) ; if ( IsPartOfGOTToPCRelPair . hasValue ( ) && ! IsPartOfGOTToPCRelPair . getValue ( ) ) emitGOTToPCRelReloc ( Inst ) ; if ( ! Emitter -> isPrefixedInstruction ( Inst ) ) { MCELFStreamer :: emitInstruction ( Inst , STI ) ; return ; } emitPrefixedInstruction ( Inst , STI ) ; if ( IsPartOfGOTToPCRelPair . hasValue ( ) && IsPartOfGOTToPCRelPair . getValue ( ) ) emitGOTToPCRelLabel ( Inst ) ; } </s>

Targets should implement this to emit instructions .


"Basic block should contain at least a RET but is empty"


<s> static bool rs6000_reg_live_or_pic_offset_p ( int reg ) { if ( reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ! TARGET_SINGLE_PIC_BASE ) { if ( TARGET_TOC && TARGET_MINIMAL_TOC && ( crtl -> calls_eh_return || df_regs_ever_live_p ( reg ) || ! constant_pool_empty_p ( ) ) ) return true ; if ( ( DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN ) && flag_pic ) return true ; } return ( ( crtl -> calls_eh_return || df_regs_ever_live_p ( reg ) ) && ! call_used_regs [ reg ] ) ; } </s>

Determine whether the gp REG is really used .


<s> SDNode * M68kDAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; auto & DL = MF -> getDataLayout ( ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI -> getPointerTy ( DL ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


"\t.frame\t%s,%ld,%s\t\t# vars= %ld, regs= %d, args= %d\n"

Set up the stack and frame ( if desired ) for the function .


<s> unsigned RISCVTargetLowering :: getJumpTableEncoding ( ) const { if ( Subtarget . is64Bit ( ) && ! isPositionIndependent ( ) && getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Small ) { return MachineJumpTableInfo :: EK_Custom32 ; } return TargetLowering :: getJumpTableEncoding ( ) ; } </s>

Return the entry encoding for a jump table in the current function .


<s> OperandMatchResultTy CSKYAsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { const AsmToken & Tok = getParser ( ) . getTok ( ) ; StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( matchRegisterNameHelper ( getSTI ( ) , ( MCRegister & ) RegNo , Name ) ) return MatchOperand_NoMatch ; getParser ( ) . Lex ( ) ; return MatchOperand_Success ; } </s>

tryParseRegister - parse one register if possible


<s> static void free_array_of_ptrs ( void * * ptr , unsigned n ) { unsigned i ; if ( ! ptr ) return ; for ( i = 0 ; i < n ; i ++ ) { if ( ! ptr [ i ] ) break ; free ( ptr [ i ] ) ; } free ( ptr ) ; return ; } </s>

Auxiliary function that frees elements of PTR and PTR itself . N is number of elements to be freed . If PTR is NULL , nothing is freed . If an element is NULL , subsequent elements are not freed .


<s> static void * mingw32_gt_pch_get_address ( size_t size , int ) { void * res ; res = VirtualAlloc ( NULL , size , MEM_RESERVE | MEM_TOP_DOWN , PAGE_NOACCESS ) ; if ( ! res ) w32_error ( __FUNCTION__ , __FILE__ , __LINE__ , "VirtualAlloc" ) ; else VirtualFree ( res , 0 , MEM_RELEASE ) ; return res ; } </s>

Identify an address that 's likely to be free in a subsequent invocation of the compiler . The area should be able to hold SIZE bytes . FD is an open file descriptor if the host would like to probe with mmap .


<s> TargetTransformInfo R600TargetMachine :: getTargetTransformInfo ( const Function & F ) const { return TargetTransformInfo ( R600TTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> bool Thumb2SizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { if ( PredicateFtor && ! PredicateFtor ( MF . getFunction ( ) ) ) return false ; STI = & static_cast < const ARMSubtarget & > ( MF . getSubtarget ( ) ) ; if ( STI -> isThumb1Only ( ) || STI -> prefers32BitThumb ( ) ) return false ; TII = static_cast < const Thumb2InstrInfo * > ( STI -> getInstrInfo ( ) ) ; OptimizeSize = MF . getFunction ( ) . hasOptSize ( ) ; MinimizeSize = STI -> hasMinSize ( ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; ReversePostOrderTraversal < MachineFunction * > RPOT ( & MF ) ; bool Modified = false ; for ( ReversePostOrderTraversal < MachineFunction * > :: rpo_iterator I = RPOT . begin ( ) , E = RPOT . end ( ) ; I != E ; ++ I ) Modified |= ReduceMBB ( * * I ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


"MMIX Internal: This is not a recognized address"


<s> static rtx iq2000_function_value ( const_tree valtype , const_tree fn_decl_or_type , bool outgoing ATTRIBUTE_UNUSED ) { int reg = GP_RETURN ; machine_mode mode = TYPE_MODE ( valtype ) ; int unsignedp = TYPE_UNSIGNED ( valtype ) ; const_tree func = fn_decl_or_type ; if ( fn_decl_or_type && ! DECL_P ( fn_decl_or_type ) ) fn_decl_or_type = NULL ; mode = promote_function_mode ( valtype , mode , & unsignedp , func , 1 ) ; return gen_rtx_REG ( mode , reg ) ; } </s>

Return register to use for a function return value with VALTYPE for function FUNC .


<s> bool enablePostRAScheduler ( ) const override { return UsePostRAScheduler ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s> bool Cpu0SEFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * EntryBlock = & MF -> front ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == Cpu0 :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> TargetLoweringBase :: LegalizeTypeAction HexagonTargetLowering :: getPreferredVectorAction ( EVT VT ) const { if ( VT . getVectorNumElements ( ) == 1 ) return TargetLoweringBase :: TypeScalarizeVector ; MVT ElemTy = VT . getSimpleVT ( ) . getVectorElementType ( ) ; if ( ElemTy == MVT :: i1 ) return TargetLoweringBase :: TypeWidenVector ; if ( Subtarget . useHVXOps ( ) ) { ArrayRef < MVT > Tys = Subtarget . getHVXElementTypes ( ) ; if ( llvm :: find ( Tys , ElemTy ) != Tys . end ( ) ) { unsigned HwWidth = 8 * Subtarget . getVectorLength ( ) ; unsigned VecWidth = VT . getSizeInBits ( ) ; if ( VecWidth >= HwWidth / 2 && VecWidth < HwWidth ) return TargetLoweringBase :: TypeWidenVector ; } } return TargetLoweringBase :: TypeSplitVector ; } </s>

Customize the preferred legalization strategy for certain types .


<s> WasmEHFuncInfo * getWasmEHFuncInfo ( ) const { return WasmEHInfo ; } </s>

getWasmEHFuncInfo - Return information about how the current function uses Wasm exception handling .


<s> int compute_frame_size ( int size , long * p_reg_saved ) { return ( size + compute_register_save_size ( p_reg_saved ) + crtl -> outgoing_args_size ) ; } </s>

Typical stack layout should looks like this after the function 's prologue : | | -- ^ | | \ | | | arguments saved | Increasing | | on the stack | addresses PARENT arg pointer - > | | / -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - | | - space for argument split between regs & stack -- CHILD | | \ < -- ( return address here ) | | other call | | saved registers | | / -- frame pointer - > | | \ ___ | | local | | | variables |f | | / |r -- |a | | \ |m | | outgoing |e | | arguments | | Decreasing ( hard ) frame pointer | | / | | addresses and stack pointer - > | | / _|_ | -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- V


<s> static void riscv_restore_reg ( rtx reg , rtx mem ) { rtx insn = riscv_emit_move ( reg , mem ) ; rtx dwarf = NULL_RTX ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; if ( epilogue_cfa_sp_offset && REGNO ( reg ) == HARD_FRAME_POINTER_REGNUM ) { rtx cfa_adjust_rtx = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( epilogue_cfa_sp_offset ) ) ; dwarf = alloc_reg_note ( REG_CFA_DEF_CFA , cfa_adjust_rtx , dwarf ) ; } REG_NOTES ( insn ) = dwarf ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>


<s> static tree char_to_type ( char c ) { static tree volatile_ptr_type_node = NULL ; static tree volatile_const_ptr_type_node = NULL ; if ( volatile_ptr_type_node == NULL ) { volatile_ptr_type_node = build_pointer_type ( build_qualified_type ( void_type_node , TYPE_QUAL_VOLATILE ) ) ; volatile_const_ptr_type_node = build_pointer_type ( build_qualified_type ( void_type_node , TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE ) ) ; } switch ( c ) { case 'v' : return void_type_node ; case 'l' : return long_unsigned_type_node ; case 'p' : return volatile_ptr_type_node ; case 'k' : return volatile_const_ptr_type_node ; default : gcc_unreachable ( ) ; } } </s>

Convert a character in a builtin type string to a tree type .


<s> const char * getPassName ( ) const override { return AARCH64_TYPE_PROMO_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> static bool umips_build_save_restore ( mips_save_restore_fn fn , unsigned * mask , HOST_WIDE_INT * offset ) { int nregs ; unsigned int i , j ; rtx pattern , set , reg , mem ; HOST_WIDE_INT this_offset ; rtx this_base ; for ( i = 0 ; i < ARRAY_SIZE ( umips_swm_mask ) ; i ++ ) if ( ( * mask & 0xffff0000 ) == umips_swm_mask [ i ] ) break ; if ( i == ARRAY_SIZE ( umips_swm_mask ) ) return false ; nregs = ( umips_swm_encoding [ i ] & 0xf ) + ( umips_swm_encoding [ i ] >> 4 ) ; this_offset = * offset - UNITS_PER_WORD * ( nregs - 1 ) ; if ( ! UMIPS_12BIT_OFFSET_P ( this_offset ) ) return false ; pattern = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nregs ) ) ; this_base = stack_pointer_rtx ; for ( j = 0 ; j < ( umips_swm_encoding [ i ] & 0xf ) ; j ++ ) { HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , this_base , offset ) ) ; unsigned int regno = ( j != 8 ) ? 16 + j : 30 ; * mask &= ~ ( 1 << regno ) ; reg = gen_rtx_REG ( SImode , regno ) ; if ( fn == mips_save_reg ) set = mips_frame_set ( mem , reg ) ; else { set = gen_rtx_SET ( VOIDmode , reg , mem ) ; mips_add_cfa_restore ( reg ) ; } XVECEXP ( pattern , 0 , j ) = set ; } if ( umips_swm_encoding [ i ] >> 4 ) { HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD ; * mask &= ~ ( 1 << 31 ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , this_base , offset ) ) ; reg = gen_rtx_REG ( SImode , 31 ) ; if ( fn == mips_save_reg ) set = mips_frame_set ( mem , reg ) ; else { set = gen_rtx_SET ( VOIDmode , reg , mem ) ; mips_add_cfa_restore ( reg ) ; } XVECEXP ( pattern , 0 , j ) = set ; } pattern = emit_insn ( pattern ) ; if ( fn == mips_save_reg ) RTX_FRAME_RELATED_P ( pattern ) = 1 ; * offset -= UNITS_PER_WORD * nregs ; return true ; } </s>

Try to use a microMIPS LWM or SWM instruction to save or restore as many GPRs in * MASK as possible . * OFFSET is the offset from the stack pointer of the topmost save slot . Remove from * MASK all registers that were handled using LWM and SWM . Update * OFFSET so that it points to the first unused save slot .


<s> ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const override { return createR600MachineScheduler ( C ) ; } </s>

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level .


<s> unsigned getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info = TTI :: OK_AnyValue , TTI :: OperandValueKind Opd2Info = TTI :: OK_AnyValue , TTI :: OperandValueProperties Opd1PropInfo = TTI :: OP_None , TTI :: OperandValueProperties Opd2PropInfo = TTI :: OP_None , ArrayRef < const Value * > Args = ArrayRef < const Value * > ( ) ) { int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: MUL : case ISD :: SDIV : case ISD :: UDIV : case ISD :: UREM : return 64 * BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .

Lanai ISD::MUL ISD::SDIV ISD::UDIV ISD::UREM 64


"storeRegToStackSlot should not be called for PTX"

Store the specified register of the given register class to the specified stack frame index .


Return an array that contains the direct target flag values and their names .

Mips Mips Mips "mips-got" "mips-got-call" "mips-gprel" "mips-abs-hi" "mips-abs-lo" "mips-tlsgd" "mips-tlsldm" "mips-dtprel-hi" "mips-dtprel-lo" "mips-gottprel" "mips-tprel-hi" "mips-tprel-lo" "mips-gpoff-hi" "mips-gpoff-lo" "mips-got-disp" "mips-got-page" "mips-got-ofst" "mips-higher" "mips-highest" "mips-got-hi16" "mips-got-lo16" "mips-call-hi16" "mips-call-lo16" "mips-jalr"


"Unknown fence ordering in emitLeadingFence"


<s> void AVRPassConfig :: addPreEmitPass ( ) { addPass ( new TestMFP ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> const ARM64RegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static bool is_prefetch ( rtx insn ) { return NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == PREFETCH ; } </s>

Return true if insn is a prefetch instruction .


"instruction use requires an option to be enabled"

"immediate must be an integer in the range [-127, 127]"

"immediate must be an integer in the range [-65535, 65535]"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> unsigned constant_generates_xxspltiw ( vec_const_128bit_type * vsx_const ) { if ( ! TARGET_SPLAT_WORD_CONSTANT || ! TARGET_PREFIXED || ! TARGET_VSX ) return 0 ; if ( ! vsx_const -> all_words_same ) return 0 ; if ( vsx_const -> all_bytes_same ) return 0 ; if ( vsx_const -> all_half_words_same ) { short sign_h_word = vsx_const -> half_words [ 0 ] ; if ( EASY_VECTOR_15 ( sign_h_word ) ) return 0 ; } int sign_word = vsx_const -> words [ 0 ] ; if ( EASY_VECTOR_15 ( sign_word ) ) return 0 ; return vsx_const -> words [ 0 ] ; } </s>

Determine if a vector constant can be loaded with XXSPLTIW . Return zero if the XXSPLTIW instruction can not be used . Otherwise return the immediate value to be used with the XXSPLTIW instruction .


<s> void emitFileDirective ( StringRef Filename ) override { } </s>

Emit `` .file assembler diretive with additioal info .


<s> TOYSubtarget & TOYSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS , bool Is64Bit = false ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = Is64Bit ? "generic-rv64" : "generic-rv32" ; ParseSubtargetFeatures ( CPUName , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> static bool vectorize_vec_perm_const_1 ( const struct expand_vec_perm_d & d ) { if ( expand_perm_with_merge ( d ) ) return true ; if ( expand_perm_with_vpdi ( d ) ) return true ; return false ; } </s>

Try to find the best sequence for the vector permute operation described by D. Return true if the operation could be expanded .


<s> static void bpf_file_end ( void ) { if ( TARGET_BPF_CORE ) btf_ext_output ( ) ; } </s>


"********** AArch64 Conditional Compares **********\n"

runOnMachineFunction - Emit the function body .


<s>
void
print
(
DiagnosticPrinter
&
DP
)
const
override
{
DP
<<
"unsupported "
<<
getDescription
(
)
<<
" in "
<<
Fn
.
getName
(
)
;
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> void emit_symbolic_move ( rtx * operands ) { rtx temp = ! can_create_pseudo_p ( ) ? operands [ 0 ] : gen_reg_rtx ( Pmode ) ; if ( GET_CODE ( operands [ 0 ] ) == MEM ) operands [ 1 ] = force_reg ( Pmode , operands [ 1 ] ) ; else if ( TLS_SYMBOLIC_CONST ( operands [ 1 ] ) ) operands [ 1 ] = legitimize_tls_address ( operands [ 1 ] , temp ) ; else if ( flag_pic ) operands [ 1 ] = legitimize_pic_address ( operands [ 1 ] , temp ) ; } </s>

Emit insns to move operands [ 1 ] into operands [ 0 ] .


<s>
bool
AVRFrameLowering
::
restoreCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
MutableArrayRef
<
CalleeSavedInfo
>
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
if
(
CSI
.
empty
(
)
)
{
return
false
;
}
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
AVRSubtarget
&
STI
=
MF
.
getSubtarget
<
AVRSubtarget
>
(
)
;
const
TargetInstrInfo
&
TII
=
*
STI
.
getInstrInfo
(
)
;
for
(
const
CalleeSavedInfo
&
CCSI
:
CSI
)
{
Register
Reg
=
CCSI
.
getReg
(
)
;
assert
(
TRI
->
getRegSizeInBits
(
*
TRI
->
getMinimalPhysRegClass
(
Reg
)
)
==
8
&&
"Invalid register size"
)
;
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
POPRd
)
,
Reg
)
;
}
return
true
;
}
</s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .

AVR
AVR
AVR
AVR
8
"Invalid register size"
AVR::POPRd


<s> static rtx nios2_legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED ) { if ( CONSTANT_P ( x ) ) return nios2_legitimize_constant_address ( x ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 0 ) ) == REG && GET_CODE ( XEXP ( x , 1 ) ) == CONST ) { rtx unspec , offset , reg = XEXP ( x , 0 ) ; split_const ( XEXP ( x , 1 ) , & unspec , & offset ) ; if ( GET_CODE ( unspec ) == UNSPEC && ! nios2_large_offset_p ( XINT ( unspec , 1 ) ) && offset != const0_rtx ) { unspec = copy_rtx ( unspec ) ; XVECEXP ( unspec , 0 , 0 ) = plus_constant ( Pmode , XVECEXP ( unspec , 0 , 0 ) , INTVAL ( offset ) ) ; x = gen_rtx_PLUS ( Pmode , reg , gen_rtx_CONST ( Pmode , unspec ) ) ; } } return x ; } </s>


<s> MVT RISCVTargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT == MVT :: f16 && Subtarget . hasStdExtF ( ) && ! Subtarget . hasStdExtZfhmin ( ) ) return MVT :: f32 ; return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


<s> bool RISCVTargetLowering :: isEligibleForTailCallOptimization ( CCState & CCInfo , CallLoweringInfo & CLI , MachineFunction & MF , const SmallVector < CCValAssign , 16 > & ArgLocs ) const { auto & Callee = CLI . Callee ; auto CalleeCC = CLI . CallConv ; auto & Outs = CLI . Outs ; auto & Caller = MF . getFunction ( ) ; auto CallerCC = Caller . getCallingConv ( ) ; if ( Caller . getFnAttribute ( "disable-tail-calls" ) . getValueAsString ( ) == "true" ) return false ; if ( Caller . hasFnAttribute ( "interrupt" ) ) return false ; if ( CCInfo . getNextStackOffset ( ) != 0 ) return false ; for ( auto & VA : ArgLocs ) if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; auto IsCallerStructRet = Caller . hasStructRetAttr ( ) ; auto IsCalleeStructRet = Outs . empty ( ) ? false : Outs [ 0 ] . Flags . isSRet ( ) ; if ( IsCallerStructRet || IsCalleeStructRet ) return false ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; if ( GV -> hasExternalWeakLinkage ( ) ) return false ; } const RISCVRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( CalleeCC != CallerCC ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } for ( auto & Arg : Outs ) if ( Arg . Flags . isByVal ( ) ) return false ; return true ; } </s>

Returns true if the call can be lowered as a tail call .

RISCV RISCV 16 "disable-tail-calls" "true" "interrupt" 0 0 RISCV


<s>
void
print
(
)
{
if
(
numSymbols
==
0
)
{
for
(
unsigned
i
=
0
;
i
<
size
;
i
++
)
{
if
(
i
)
O
<<
", "
;
O
<<
(
unsigned
int
)
buffer
[
i
]
;
}
}
else
{
unsigned
int
pos
=
0
;
unsigned
int
nSym
=
0
;
unsigned
int
nextSymbolPos
=
symbolPosInBuffer
[
nSym
]
;
unsigned
int
nBytes
=
4
;
if
(
AP
.
nvptxSubtarget
.
is64Bit
(
)
)
nBytes
=
8
;
for
(
pos
=
0
;
pos
<
size
;
pos
+=
nBytes
)
{
if
(
pos
)
O
<<
", "
;
if
(
pos
==
nextSymbolPos
)
{
const
Value
*
v
=
Symbols
[
nSym
]
;
if
(
const
GlobalValue
*
GVar
=
dyn_cast
<
GlobalValue
>
(
v
)
)
{
MCSymbol
*
Name
=
AP
.
getSymbol
(
GVar
)
;
PointerType
*
PTy
=
dyn_cast
<
PointerType
>
(
GVar
->
getType
(
)
)
;
bool
IsNonGenericPointer
=
false
;
if
(
PTy
&&
PTy
->
getAddressSpace
(
)
!=
0
)
{
IsNonGenericPointer
=
true
;
}
if
(
EmitGeneric
&&
!
isa
<
Function
>
(
v
)
&&
!
IsNonGenericPointer
)
{
O
<<
"generic("
;
O
<<
*
Name
;
O
<<
")"
;
}
else
{
O
<<
*
Name
;
}
}
else
if
(
const
ConstantExpr
*
Cexpr
=
dyn_cast
<
ConstantExpr
>
(
v
)
)
{
O
<<
*
AP
.
lowerConstant
(
Cexpr
)
;
}
else
llvm_unreachable
(
"symbol type unknown"
)
;
nSym
++
;
if
(
nSym
>=
numSymbols
)
nextSymbolPos
=
size
+
1
;
else
nextSymbolPos
=
symbolPosInBuffer
[
nSym
]
;
}
else
if
(
nBytes
==
4
)
O
<<
*
(
unsigned
int
*
)
(
&
buffer
[
pos
]
)
;
else
O
<<
*
(
unsigned
long
long
*
)
(
&
buffer
[
pos
]
)
;
}
}
}
</s>


<s> void SparcFrameLowering :: emitPrologue ( MachineFunction & MF ) const { SparcMachineFunctionInfo * FuncInfo = MF . getInfo < SparcMachineFunctionInfo > ( ) ; MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const SparcInstrInfo & TII = * static_cast < const SparcInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; unsigned SAVEri = SP :: SAVEri ; unsigned SAVErr = SP :: SAVErr ; if ( FuncInfo -> isLeafProc ( ) ) { if ( NumBytes == 0 ) return ; SAVEri = SP :: ADDri ; SAVErr = SP :: ADDrr ; } NumBytes = - MF . getTarget ( ) . getSubtarget < SparcSubtarget > ( ) . getAdjustedFrameSize ( NumBytes ) ; emitSPAdjustment ( MF , MBB , MBBI , NumBytes , SAVErr , SAVEri ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; unsigned regFP = MRI -> getDwarfRegNum ( SP :: I6 , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , regFP ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createWindowSave ( nullptr ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; unsigned regInRA = MRI -> getDwarfRegNum ( SP :: I7 , true ) ; unsigned regOutRA = MRI -> getDwarfRegNum ( SP :: O7 , true ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createRegister ( nullptr , regOutRA , regInRA ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Sparc Sparc Sparc Sparc Sparc Sparc SP::SAVEri SP::SAVErr 0 SP::ADDri SP::ADDrr Sparc SP SP::I6 SP::I7 SP::O7