<s> void X86FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; int64_t TailCallReturnAddrDelta = X86FI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < 0 ) { MFI -> CreateFixedObject ( - TailCallReturnAddrDelta , TailCallReturnAddrDelta - SlotSize , true ) ; } if ( TRI -> hasBasePointer ( MF ) ) { SavedRegs . set ( TRI -> getBaseRegister ( ) ) ; if ( MF . getMMI ( ) . hasEHFunclets ( ) ) { int FI = MFI -> CreateSpillStackObject ( SlotSize , SlotSize ) ; X86FI -> setHasSEHFramePtrSave ( true ) ; X86FI -> setSEHFramePtrSaveIndex ( FI ) ; } } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> bool R600InstrInfo :: isPredicable ( MachineInstr * MI ) const { if ( MI -> getOpcode ( ) == AMDGPU :: KILLGT ) { return false ; } else if ( isVector ( * MI ) ) { return false ; } else { return AMDGPUInstrInfo :: isPredicable ( MI ) ; } } </s>

Return true if the specified instruction can be predicated .


<s> std :: pair < unsigned , const TargetRegisterClass * > XCoreTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'r' : return std :: make_pair ( 0U , & XCore :: GRRegsRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> bool XNCMTargetLowering :: isZExtFree ( EVT VT1 , EVT VT2 ) const { return 0 && VT1 == MVT :: i8 && VT2 == MVT :: i16 ; } </s>

Return true if zero-extending the specific node Val to type VT2 is free ( either because it 's implicitly zero-extended such as ARM ldrb / ldrh or because it 's folded such as X86 zero-extending loads ) .


<s> SDValue Cpu0TargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BRCOND : return lowerBRCOND ( Op , DAG ) ; case ISD :: GlobalAddress : return lowerGlobalAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return lowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: BlockAddress : return lowerBlockAddress ( Op , DAG ) ; case ISD :: JumpTable : return lowerJumpTable ( Op , DAG ) ; case ISD :: SELECT : return lowerSELECT ( Op , DAG ) ; case ISD :: VASTART : return lowerVASTART ( Op , DAG ) ; case ISD :: FRAMEADDR : return lowerFRAMEADDR ( Op , DAG ) ; case ISD :: RETURNADDR : return lowerRETURNADDR ( Op , DAG ) ; case ISD :: EH_RETURN : return lowerEH_RETURN ( Op , DAG ) ; case ISD :: ADD : return lowerADD ( Op , DAG ) ; case ISD :: ATOMIC_FENCE : return lowerATOMIC_FENCE ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Cpu0 Cpu0 ISD::BRCOND ISD::GlobalAddress ISD::GlobalTLSAddress ISD::BlockAddress ISD::JumpTable ISD::SELECT ISD::VASTART ISD::FRAMEADDR ISD::RETURNADDR ISD::EH_RETURN ISD::ADD ISD::ATOMIC_FENCE


<s> bool NVPTXDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < NVPTXSubtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> int BSideAssigner :: select ( int side , const res_set_t & set ) { assert ( set . size ( ) ) ; if ( set . size ( ) == 1 ) return - 1 ; for ( res_set_t :: const_iterator I = set . begin ( ) , E = set . end ( ) ; I != E ; ++ I ) if ( ( * I & 0x1 ) == side ) return * I ; return - 1 ; } </s>

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s> const TargetRegisterClass * PPCRegisterInfo :: getPointerRegClass ( ) const { if ( Subtarget . isPPC64 ( ) ) return & PPC :: G8RCRegClass ; else return & PPC :: GPRCRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .

PowerPC PPC PPC PPC::G8RCRegClass PPC::GPRCRegClass


<s> static void fold_mergehl_helper ( gimple_stmt_iterator * gsi , gimple * stmt , int use_high ) { tree arg0 = gimple_call_arg ( stmt , 0 ) ; tree arg1 = gimple_call_arg ( stmt , 1 ) ; tree lhs = gimple_call_lhs ( stmt ) ; tree lhs_type = TREE_TYPE ( lhs ) ; int n_elts = TYPE_VECTOR_SUBPARTS ( lhs_type ) ; int midpoint = n_elts / 2 ; int offset = 0 ; if ( use_high == 1 ) offset = midpoint ; tree permute_type ; permute_type = map_to_integral_tree_type ( lhs_type ) ; tree_vector_builder elts ( permute_type , VECTOR_CST_NELTS ( arg0 ) , 1 ) ; for ( int i = 0 ; i < midpoint ; i ++ ) { elts . safe_push ( build_int_cst ( TREE_TYPE ( permute_type ) , offset + i ) ) ; elts . safe_push ( build_int_cst ( TREE_TYPE ( permute_type ) , offset + n_elts + i ) ) ; } tree permute = elts . build ( ) ; gimple * g = gimple_build_assign ( lhs , VEC_PERM_EXPR , arg0 , arg1 , permute ) ; gimple_set_location ( g , gimple_location ( stmt ) ) ; gsi_replace ( gsi , g , true ) ; } </s>

Helper function to handle the vector merge [ hl ] built-ins . The implementation difference between h and l versions for this code are in the values used when building of the permute vector for high word versus low word merge . The variance is keyed off the use_high parameter .


<s> MCObjectWriter * BPFAsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { return createBPFELFObjectWriter ( OS , 0 ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static void split_plus ( rtx x , rtx * base_ptr , HOST_WIDE_INT * offset_ptr ) { if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , 1 ) ) ) { * base_ptr = XEXP ( x , 0 ) ; * offset_ptr = INTVAL ( XEXP ( x , 1 ) ) ; } else { * base_ptr = x ; * offset_ptr = 0 ; } } </s>

If X is a PLUS of a CONST_INT , return the two terms in * BASE_PTR and * OFFSET_PTR . Return X in * BASE_PTR and 0 in * OFFSET_PTR otherwise .


"This eliminateCallFramePseudoInstr does not support Thumb1!"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> int addr32_operand ( rtx op , machine_mode mode ) { rtx sym ; if ( GET_CODE ( op ) == LABEL_REF ) return TARGET_ADDR32 ; if ( GET_CODE ( op ) == SYMBOL_REF ) sym = op ; else if ( GET_CODE ( op ) == CONST && GET_CODE ( XEXP ( op , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( op , 0 ) , 0 ) ) == SYMBOL_REF && CONST_INT_P ( XEXP ( XEXP ( op , 0 ) , 1 ) ) && ! flag_pic ) sym = XEXP ( XEXP ( op , 0 ) , 0 ) ; else return 0 ; return ( ! addr24_operand ( sym , mode ) && ! small_data_operand ( sym , mode ) ) ; } </s>

Return 1 if OP is a symbol that needs 32 bit addressing .


<s> unsigned PPCTTIImpl :: getIntrinsicInstrCost ( const IntrinsicCostAttributes & ICA , TTI :: TargetCostKind CostKind ) { return BaseT :: getIntrinsicInstrCost ( ICA , CostKind ) ; } </s>


<s>
void
AMDGPUDAGToDAGISel
::
PreprocessISelDAG
(
)
{
if
(
!
Subtarget
->
d16PreservesUnusedBits
(
)
)
return
;
SelectionDAG
::
allnodes_iterator
Position
=
CurDAG
->
allnodes_end
(
)
;
bool
MadeChange
=
false
;
while
(
Position
!=
CurDAG
->
allnodes_begin
(
)
)
{
SDNode
*
N
=
&
*
Position
;
if
(
N
->
use_empty
(
)
)
continue
;
switch
(
N
->
getOpcode
(
)
)
{
case
ISD
::
BUILD_VECTOR
:
MadeChange
|=
matchLoadD16FromBuildVector
(
N
)
;
break
;
default
:
break
;
}
}
if
(
MadeChange
)
{
CurDAG
->
RemoveDeadNodes
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"After PreProcess:\n"
;
CurDAG
->
dump
(
)
;
)
;
}
}
</s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .

AMDGPU
AMDGPU
ISD::BUILD_VECTOR
"After PreProcess:\n"


<s> bool MipsAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < MipsSubtarget > ( ) ; MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; if ( Subtarget -> inMips16Mode ( ) ) for ( std :: map < const char * , const llvm :: Mips16HardFloatInfo :: FuncSignature * > :: const_iterator it = MipsFI -> StubsNeeded . begin ( ) ; it != MipsFI -> StubsNeeded . end ( ) ; ++ it ) { const char * Symbol = it -> first ; const llvm :: Mips16HardFloatInfo :: FuncSignature * Signature = it -> second ; if ( StubsNeeded . find ( Symbol ) == StubsNeeded . end ( ) ) StubsNeeded [ Symbol ] = Signature ; } MCP = MF . getConstantPool ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) NaClAlignIndirectJumpTargets ( MF ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; EmitXRayTable ( ) ; return true ; } </s>

Mips Mips Mips Mips Mips Mips Mips16HardFloatInfo::FuncSignature Mips Mips Mips16HardFloatInfo::FuncSignature


<s> static reg_class_t ix86_preferred_reload_class ( rtx x , reg_class_t regclass ) { machine_mode mode = GET_MODE ( x ) ; if ( regclass == NO_REGS ) return NO_REGS ; if ( x == CONST0_RTX ( mode ) ) return regclass ; if ( CONSTANT_P ( x ) && ( MAYBE_MMX_CLASS_P ( regclass ) || MAYBE_SSE_CLASS_P ( regclass ) || MAYBE_MASK_CLASS_P ( regclass ) ) ) return NO_REGS ; if ( TARGET_SSE_MATH && ! TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P ( mode ) ) return SSE_CLASS_P ( regclass ) ? regclass : NO_REGS ; if ( GET_CODE ( x ) == CONST_DOUBLE && GET_MODE ( x ) != VOIDmode ) { if ( reg_class_subset_p ( regclass , GENERAL_REGS ) ) return regclass ; if ( TARGET_80387 && standard_80387_constant_p ( x ) > 0 ) { if ( regclass == FLOAT_SSE_REGS ) return FLOAT_REGS ; if ( regclass == FP_TOP_SSE_REGS ) return FP_TOP_REG ; if ( regclass == FP_SECOND_SSE_REGS ) return FP_SECOND_REG ; if ( regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS ) return regclass ; } return NO_REGS ; } if ( GET_CODE ( x ) == PLUS ) return reg_class_subset_p ( regclass , GENERAL_REGS ) ? regclass : NO_REGS ; if ( GET_MODE ( x ) == QImode && ! CONSTANT_P ( x ) ) { if ( reg_class_subset_p ( regclass , Q_REGS ) ) return regclass ; if ( reg_class_subset_p ( Q_REGS , regclass ) ) return Q_REGS ; return NO_REGS ; } return regclass ; } </s>

Put float CONST_DOUBLE in the constant pool instead of fp regs . QImode must go into class Q_REGS . Narrow ALL_REGS to GENERAL_REGS . This supports allowing movsf and movdf to do mem-to-mem moves through integer regs .


<s> static rtx bpf_function_value ( const_tree ret_type , const_tree fntype_or_decl , bool outgoing ATTRIBUTE_UNUSED ) { enum machine_mode mode ; int unsignedp ; mode = TYPE_MODE ( ret_type ) ; if ( INTEGRAL_TYPE_P ( ret_type ) ) mode = promote_function_mode ( ret_type , mode , & unsignedp , fntype_or_decl , 1 ) ; return gen_rtx_REG ( mode , BPF_R0 ) ; } </s>

Return an RTX representing the place where a function returns or receives a value of data type RET_TYPE , a tree node representing a data type .


<s> bool Cpu0TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( ! AM . HasBaseReg ) break ; return false ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> bool HSAILAsmPrinter :: doFinalization ( Module & M ) { EmitEndOfAsmFile ( M ) ; return false ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s>
bool
AMDGPUPerfHint
::
runOnFunction
(
Function
&
F
)
{
const
Module
&
M
=
*
F
.
getParent
(
)
;
DL
=
&
M
.
getDataLayout
(
)
;
if
(
F
.
hasFnAttribute
(
"amdgpu-wave-limiter"
)
&&
F
.
hasFnAttribute
(
"amdgpu-memory-bound"
)
)
return
false
;
const
AMDGPUPerfHintAnalysis
::
FuncInfo
*
Info
=
visit
(
F
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
F
.
getName
(
)
<<
" MemInst cost: "
<<
Info
->
MemInstCost
<<
'\n'
<<
" IAMInst cost: "
<<
Info
->
IAMInstCost
<<
'\n'
<<
" LSMInst cost: "
<<
Info
->
LSMInstCost
<<
'\n'
<<
" TotalInst cost: "
<<
Info
->
InstCost
<<
'\n'
)
;
bool
Changed
=
false
;
if
(
isMemBound
(
*
Info
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
F
.
getName
(
)
<<
" is memory bound\n"
)
;
NumMemBound
++
;
F
.
addFnAttr
(
"amdgpu-memory-bound"
,
"true"
)
;
Changed
=
true
;
}
if
(
AMDGPU
::
isEntryFunctionCC
(
F
.
getCallingConv
(
)
)
&&
needLimitWave
(
*
Info
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
F
.
getName
(
)
<<
" needs limit wave\n"
)
;
NumLimitWave
++
;
F
.
addFnAttr
(
"amdgpu-wave-limiter"
,
"true"
)
;
Changed
=
true
;
}
return
Changed
;
}
</s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .

AMDGPU
AMDGPU
"amdgpu-wave-limiter"
"amdgpu-memory-bound"
AMDGPU
" MemInst cost: "
" IAMInst cost: "
" LSMInst cost: "
" TotalInst cost: "
" is memory bound\n"
"amdgpu-memory-bound"
"true"
AMDGPU::isEntryFunctionCC
" needs limit wave\n"
"amdgpu-wave-limiter"
"true"


<s> char * msp430_dirname ( char * path ) { int last_elem = strlen ( path ) - 1 ; int i = last_elem - ( IS_DIR_SEPARATOR ( path [ last_elem ] ) ? 1 : 0 ) ; for ( ; i >= 0 ; i -- ) { if ( IS_DIR_SEPARATOR ( path [ i ] ) ) { path [ i ] = '\0' ; return path ; } } return path ; } </s>

This function returns the enclosing directory of PATH . It is inconsequential whether PATH ends in a dirsep or not . It modifies the string pointed to by PATH .


"internal error in %s, at %s:%d: %s: %s\n"

Print out the GetLastError ( ) translation .


"\nrs6000_legitimate_address_p: return = %s, mode = %s, "

Debug version of rs6000_legitimate_address_p .


<s> void HexagonInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { if ( Hexagon :: IntRegsRegClass . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: TFR ) , DestReg ) . addReg ( SrcReg ) ; return ; } if ( Hexagon :: DoubleRegsRegClass . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: TFR_64 ) , DestReg ) . addReg ( SrcReg ) ; return ; } if ( Hexagon :: PredRegsRegClass . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: OR_pp ) , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg ) ; return ; } if ( Hexagon :: DoubleRegsRegClass . contains ( DestReg , SrcReg ) ) { if ( SrcReg == RI . getSubReg ( DestReg , Hexagon :: subreg_loreg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: TFRI ) , ( RI . getSubReg ( DestReg , Hexagon :: subreg_hireg ) ) ) . addImm ( 0 ) ; } else { BuildMI ( MBB , I , DL , get ( Hexagon :: TFR ) , ( RI . getSubReg ( DestReg , Hexagon :: subreg_loreg ) ) ) . addReg ( SrcReg ) ; BuildMI ( MBB , I , DL , get ( Hexagon :: TFRI ) , ( RI . getSubReg ( DestReg , Hexagon :: subreg_hireg ) ) ) . addImm ( 0 ) ; } return ; } if ( Hexagon :: CRRegsRegClass . contains ( DestReg , SrcReg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: TFCR ) , DestReg ) . addReg ( SrcReg ) ; return ; } llvm_unreachable ( "Unimplemented" ) ; } </s>


<s> void split_double_mode ( machine_mode mode , rtx operands [ ] , int num , rtx lo_half [ ] , rtx hi_half [ ] ) { machine_mode half_mode ; unsigned int byte ; switch ( mode ) { case E_TImode : half_mode = DImode ; break ; case E_DImode : half_mode = SImode ; break ; default : gcc_unreachable ( ) ; } byte = GET_MODE_SIZE ( half_mode ) ; while ( num -- ) { rtx op = operands [ num ] ; if ( MEM_P ( op ) ) { lo_half [ num ] = adjust_address ( op , half_mode , 0 ) ; hi_half [ num ] = adjust_address ( op , half_mode , byte ) ; } else { lo_half [ num ] = simplify_gen_subreg ( half_mode , op , GET_MODE ( op ) == VOIDmode ? mode : GET_MODE ( op ) , 0 ) ; hi_half [ num ] = simplify_gen_subreg ( half_mode , op , GET_MODE ( op ) == VOIDmode ? mode : GET_MODE ( op ) , byte ) ; } } } </s>

Split one or more double-mode RTL references into pairs of half-mode references . The RTL can be REG , offsettable MEM , integer constant , or CONST_DOUBLE . `` operands '' is a pointer to an array of double-mode RTLs to split and `` num '' is its length . lo_half and hi_half are output arrays that parallel `` operands '' .


<s> static bool mmix_legitimate_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { RTX_CODE code = GET_CODE ( x ) ; if ( code == CONST_INT || code == CONST_DOUBLE ) return 1 ; return CONSTANT_ADDRESS_P ( x ) ; } </s>


<s> unsigned int execute ( function * ) { return nds32_relax_opt ( ) ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < AAResultsWrapperPass > ( ) ; AU . addRequired < MachineBranchProbabilityInfo > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"NaCl Rewrites"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> int64_t getFrameAdjustment ( const MachineInstr & I ) const { assert ( isFrameInstr ( I ) ) ; return I . getOperand ( 1 ) . getImm ( ) ; } </s>

Returns the stack pointer adjustment that happens inside the frame setup .. destroy sequence ( e.g .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == 0 ) Inst . addOperand ( MCOperand :: CreateImm ( 0 ) ) ; else if ( auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ; } </s>


<s>
void
maybe_unlink
(
const
char
*
file
)
{
if
(
!
save_temps
)
{
if
(
unlink_if_ordinary
(
file
)
&&
errno
!=
ENOENT
)
fatal_error
(
input_location
,
"deleting file %s: %m"
,
file
)
;
}
else
if
(
verbose
)
fprintf
(
stderr
,
"[Leaving %s]\n"
,
file
)
;
}
</s>

Unlink a temporary file unless requested otherwise .

nvptx
"deleting file %s: %m"
"[Leaving %s]\n"


<s> int effective_address_32bit_p ( rtx op , enum machine_mode mode ) { HOST_WIDE_INT offset ; mode = GET_MODE ( op ) ; op = XEXP ( op , 0 ) ; if ( GET_CODE ( op ) != PLUS ) { gcc_assert ( REG_P ( op ) || GET_CODE ( op ) == POST_INC || GET_CODE ( op ) == PRE_DEC || GET_CODE ( op ) == POST_DEC ) ; return 0 ; } offset = INTVAL ( XEXP ( op , 1 ) ) ; if ( GET_MODE_SIZE ( mode ) == 1 ) return 1 ; if ( GET_MODE_SIZE ( mode ) == 4 ) { if ( XEXP ( op , 0 ) == frame_pointer_rtx ) return offset < - 128 || offset > 60 ; return offset < 0 || offset > 60 ; } return offset < 0 || offset > 30 ; } </s>

This predicate is used to compute the length of a load/store insn . OP is a MEM rtx , we return nonzero if its addressing mode requires a 32 bit instruction .


<s> static void rs6000_set_handled_components ( sbitmap components ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; for ( int i = info -> first_gp_reg_save ; i < 32 ; i ++ ) if ( bitmap_bit_p ( components , i ) ) cfun -> machine -> gpr_is_wrapped_separately [ i ] = true ; for ( int i = info -> first_fp_reg_save ; i < 64 ; i ++ ) if ( bitmap_bit_p ( components , i ) ) cfun -> machine -> fpr_is_wrapped_separately [ i - 32 ] = true ; if ( bitmap_bit_p ( components , 0 ) ) cfun -> machine -> lr_is_wrapped_separately = true ; if ( bitmap_bit_p ( components , 2 ) ) cfun -> machine -> toc_is_wrapped_separately = true ; } </s>


<s>
bool
LVLGen
::
runOnMachineFunction
(
MachineFunction
&
F
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"********** Begin LVLGen **********\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"********** Function: "
<<
F
.
getName
(
)
<<
'\n'
)
;
LLVM_DEBUG
(
F
.
dump
(
)
)
;
bool
Changed
=
false
;
const
VESubtarget
&
Subtarget
=
F
.
getSubtarget
<
VESubtarget
>
(
)
;
TII
=
Subtarget
.
getInstrInfo
(
)
;
TRI
=
Subtarget
.
getRegisterInfo
(
)
;
for
(
MachineFunction
::
iterator
FI
=
F
.
begin
(
)
,
FE
=
F
.
end
(
)
;
FI
!=
FE
;
++
FI
)
Changed
|=
runOnMachineBasicBlock
(
*
FI
)
;
if
(
Changed
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"\n"
)
;
LLVM_DEBUG
(
F
.
dump
(
)
)
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"********** End LVLGen **********\n"
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool isFMAFasterThanFMulAndFAdd ( const MachineFunction & MF , EVT ) const override { return true ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> static void compute_save_world_info ( rs6000_stack_t * info ) { info -> world_save_p = 1 ; info -> world_save_p = ( WORLD_SAVE_P ( info ) && DEFAULT_ABI == ABI_DARWIN && ! cfun -> has_nonlocal_label && info -> first_fp_reg_save == FIRST_SAVED_FP_REGNO && info -> first_gp_reg_save == FIRST_SAVED_GP_REGNO && info -> first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO && info -> cr_save_p ) ; if ( WORLD_SAVE_P ( info ) ) { rtx_insn * insn ; for ( insn = get_last_insn_anywhere ( ) ; insn ; insn = PREV_INSN ( insn ) ) if ( CALL_P ( insn ) && SIBLING_CALL_P ( insn ) ) { info -> world_save_p = 0 ; break ; } } if ( WORLD_SAVE_P ( info ) ) { info -> vrsave_size = 4 ; info -> lr_save_p = 1 ; if ( info -> vrsave_mask == 0 ) info -> vrsave_mask = compute_vrsave_mask ( ) ; gcc_assert ( info -> first_fp_reg_save >= FIRST_SAVED_FP_REGNO && ( info -> first_altivec_reg_save >= FIRST_SAVED_ALTIVEC_REGNO ) ) ; } return ; } </s>

For a very restricted set of circumstances , we can cut down the size of prologues/epilogues by calling our own save/restore-the-world routines .


"Encoding of this operand type is not supported yet."

getMachineOpValue - Return binary encoding of operand .


<s> const MCExpr * X86TargetLowering :: getPICJumpTableRelocBaseExpr ( const MachineFunction * MF , unsigned JTI , MCContext & Ctx ) const { if ( Subtarget -> isPICStyleRIPRel ( ) ) return TargetLowering :: getPICJumpTableRelocBaseExpr ( MF , JTI , Ctx ) ; return MCSymbolRefExpr :: Create ( MF -> getPICBaseSymbol ( ) , Ctx ) ; } </s>

This returns the relocation base for the given PIC jumptable , the same as getPICJumpTableRelocBase , but as an MCExpr .


<s>
bool
HexagonExpandCondsets
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
*
MF
.
getFunction
(
)
)
)
return
false
;
HII
=
static_cast
<
const
HexagonInstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
LIS
=
&
getAnalysis
<
LiveIntervals
>
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
LocalImpDefs
.
clear
(
)
;
DEBUG
(
LIS
->
print
(
dbgs
(
)
<<
"Before expand-condsets\n"
,
MF
.
getFunction
(
)
->
getParent
(
)
)
)
;
bool
Changed
=
false
;
std
::
set
<
unsigned
>
SplitUpd
,
PredUpd
;
Changed
|=
coalesceSegments
(
MF
)
;
for
(
auto
&
B
:
MF
)
Changed
|=
splitInBlock
(
B
,
SplitUpd
)
;
updateLiveness
(
SplitUpd
,
true
,
true
,
false
)
;
for
(
auto
&
B
:
MF
)
Changed
|=
predicateInBlock
(
B
,
PredUpd
)
;
updateLiveness
(
PredUpd
,
true
,
true
,
true
)
;
std
::
set
<
unsigned
>
Diff
;
std
::
set_difference
(
SplitUpd
.
begin
(
)
,
SplitUpd
.
end
(
)
,
PredUpd
.
begin
(
)
,
PredUpd
.
end
(
)
,
std
::
inserter
(
Diff
,
Diff
.
begin
(
)
)
)
;
updateLiveness
(
Diff
,
false
,
false
,
true
)
;
for
(
auto
*
ImpD
:
LocalImpDefs
)
removeInstr
(
ImpD
)
;
DEBUG
(
{
if
(
Changed
)
LIS
->
print
(
dbgs
(
)
<<
"After expand-condsets\n"
,
MF
.
getFunction
(
)
->
getParent
(
)
)
;
}
)
;
return
Changed
;
}
</s>

Hexagon
Hexagon
Hexagon
"Before expand-condsets\n"
"After expand-condsets\n"


<s> machine_mode ix86_split_reduction ( machine_mode mode ) { switch ( mode ) { case E_V8DImode : case E_V4DImode : return V2DImode ; case E_V16SImode : case E_V8SImode : return V4SImode ; case E_V32HImode : case E_V16HImode : return V8HImode ; case E_V64QImode : case E_V32QImode : return V16QImode ; case E_V16SFmode : case E_V8SFmode : return V4SFmode ; case E_V8DFmode : case E_V4DFmode : return V2DFmode ; default : return mode ; } } </s>

All CPUs prefer to avoid cross-lane operations so perform reductions upper against lower halves up to SSE reg size .


<s> MachineBasicBlock :: iterator DLXFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"TOY Assembly Printer"
;
}
</s>


<s> SDNode * PPCDAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * PPCSubTarget -> getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; const Module * M = MF -> getFunction ( ) . getParent ( ) ; DebugLoc dl ; if ( PPCLowering -> getPointerTy ( CurDAG -> getDataLayout ( ) ) == MVT :: i32 ) { if ( PPCSubTarget -> isTargetELF ( ) ) { GlobalBaseReg = PPC :: R30 ; if ( ! PPCSubTarget -> isSecurePlt ( ) && M -> getPICLevel ( ) == PICLevel :: SmallPIC ) { BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MoveGOTtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; MF -> getInfo < PPCFunctionInfo > ( ) -> setUsesPICBase ( true ) ; } else { BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; unsigned TempReg = RegInfo -> createVirtualRegister ( & PPC :: GPRCRegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: UpdateGBR ) , GlobalBaseReg ) . addReg ( TempReg , RegState :: Define ) . addReg ( GlobalBaseReg ) ; MF -> getInfo < PPCFunctionInfo > ( ) -> setUsesPICBase ( true ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: GPRC_and_GPRC_NOR0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; } } else { MF -> getInfo < PPCFunctionInfo > ( ) -> setShrinkWrapDisabled ( true ) ; GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: G8RC_and_G8RC_NOX0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR8 ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR8 ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , PPCLowering -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

PowerPC PPC PPC PPC MVT::i32 PPC PPC::R30 PPC PPC::MoveGOTtoLR PPC::MFLR PPC PPC::MovePCtoLR PPC::MFLR PPC::GPRCRegClass PPC::UpdateGBR PPC PPC::GPRC_and_GPRC_NOR0RegClass PPC::MovePCtoLR PPC::MFLR PPC PPC::G8RC_and_G8RC_NOX0RegClass PPC::MovePCtoLR8 PPC::MFLR8 PPC


<s> bool ARMBaseInstrInfo :: shouldScheduleLoadsNear ( SDNode * Load1 , SDNode * Load2 , int64_t Offset1 , int64_t Offset2 , unsigned NumLoads ) const { if ( Subtarget . isThumb1Only ( ) ) return false ; assert ( Offset2 > Offset1 ) ; if ( ( Offset2 - Offset1 ) / 8 > 64 ) return false ; if ( ( Load1 -> getMachineOpcode ( ) != Load2 -> getMachineOpcode ( ) ) && ! ( ( Load1 -> getMachineOpcode ( ) == ARM :: t2LDRBi8 && Load2 -> getMachineOpcode ( ) == ARM :: t2LDRBi12 ) || ( Load1 -> getMachineOpcode ( ) == ARM :: t2LDRBi12 && Load2 -> getMachineOpcode ( ) == ARM :: t2LDRBi8 ) ) ) return false ; if ( NumLoads >= 3 ) return false ; return true ; } </s>

shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine ( in conjunction with areLoadsFromSameBasePtr ) if two loads should be scheduled togther .


<s> unsigned getNumFixupKinds ( ) const override { return Hexagon :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> void ARMAsmPrinter :: emitInlineAsmEnd ( const MCSubtargetInfo & StartInfo , const MCSubtargetInfo * EndInfo ) const { const bool WasThumb = isThumb ( StartInfo ) ; if ( EndInfo == NULL || WasThumb != isThumb ( * EndInfo ) ) { OutStreamer . EmitAssemblerFlag ( WasThumb ? MCAF_Code16 : MCAF_Code32 ) ; } } </s>

Let the target do anything it needs to do after emitting inlineasm .


<s> int m32r_first_insn_address ( ) { if ( ! current_frame_info . initialized ) m32r_compute_frame_size ( get_frame_size ( ) ) ; return 0 ; } </s>

When the ` length ' insn attribute is used , this macro specifies the value to be assigned to the address of the first insn in a function . If not specified , 0 is used .


<s> bool HexagonHardwareLoops :: isDead ( const MachineInstr * MI , SmallVectorImpl < MachineInstr * > & DeadPhis ) const { for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( MRI -> use_nodbg_empty ( Reg ) ) continue ; using use_nodbg_iterator = MachineRegisterInfo :: use_nodbg_iterator ; use_nodbg_iterator I = MRI -> use_nodbg_begin ( Reg ) ; use_nodbg_iterator End = MRI -> use_nodbg_end ( ) ; if ( std :: next ( I ) != End || ! I -> getParent ( ) -> isPHI ( ) ) return false ; MachineInstr * OnePhi = I -> getParent ( ) ; for ( unsigned j = 0 , f = OnePhi -> getNumOperands ( ) ; j != f ; ++ j ) { const MachineOperand & OPO = OnePhi -> getOperand ( j ) ; if ( ! OPO . isReg ( ) || ! OPO . isDef ( ) ) continue ; unsigned OPReg = OPO . getReg ( ) ; use_nodbg_iterator nextJ ; for ( use_nodbg_iterator J = MRI -> use_nodbg_begin ( OPReg ) ; J != End ; J = nextJ ) { nextJ = std :: next ( J ) ; MachineOperand & Use = * J ; MachineInstr * UseMI = Use . getParent ( ) ; if ( MI != UseMI ) return false ; } } DeadPhis . push_back ( OnePhi ) ; } return true ; } </s>

isDead - Returns true if this is a dead def kill slot .


<s> SDValue Cpu0TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , DebugLoc dl , SelectionDAG & DAG ) const { return DAG . getNode ( Cpu0ISD :: Ret , dl , MVT :: Other , Chain , DAG . getRegister ( Cpu0 :: LR , MVT :: i32 ) ) ; } </s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool X86AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { static const uint8_t Nops [ 10 ] [ 10 ] = { { 0x90 } , { 0x66 , 0x90 } , { 0x0f , 0x1f , 0x00 } , { 0x0f , 0x1f , 0x40 , 0x00 } , { 0x0f , 0x1f , 0x44 , 0x00 , 0x00 } , { 0x66 , 0x0f , 0x1f , 0x44 , 0x00 , 0x00 } , { 0x0f , 0x1f , 0x80 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x66 , 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x66 , 0x2e , 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , } ; if ( ! HasNopl ) { for ( uint64_t i = 0 ; i < Count ; ++ i ) OW -> Write8 ( 0x90 ) ; return true ; } do { const uint8_t ThisNopLength = ( uint8_t ) std :: min ( Count , ( uint64_t ) 15 ) ; const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10 ; for ( uint8_t i = 0 ; i < Prefixes ; i ++ ) OW -> Write8 ( 0x66 ) ; const uint8_t Rest = ThisNopLength - Prefixes ; for ( uint8_t i = 0 ; i < Rest ; i ++ ) OW -> Write8 ( Nops [ Rest - 1 ] [ i ] ) ; Count -= ThisNopLength ; } while ( Count != 0 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s>
bool
HexagonExpandCondsets
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
HII
=
static_cast
<
const
HexagonInstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
LIS
=
&
getAnalysis
<
LiveIntervals
>
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
DEBUG
(
LIS
->
print
(
dbgs
(
)
<<
"Before expand-condsets\n"
,
MF
.
getFunction
(
)
.
getParent
(
)
)
)
;
bool
Changed
=
false
;
std
::
set
<
unsigned
>
CoalUpd
,
PredUpd
;
SmallVector
<
MachineInstr
*
,
16
>
Condsets
;
for
(
auto
&
B
:
MF
)
for
(
auto
&
I
:
B
)
if
(
isCondset
(
I
)
)
Condsets
.
push_back
(
&
I
)
;
Changed
|=
coalesceSegments
(
Condsets
,
CoalUpd
)
;
std
::
set
<
unsigned
>
KillUpd
;
for
(
MachineInstr
*
MI
:
Condsets
)
for
(
MachineOperand
&
Op
:
MI
->
operands
(
)
)
if
(
Op
.
isReg
(
)
&&
Op
.
isUse
(
)
)
if
(
!
CoalUpd
.
count
(
Op
.
getReg
(
)
)
)
KillUpd
.
insert
(
Op
.
getReg
(
)
)
;
updateLiveness
(
KillUpd
,
false
,
true
,
false
)
;
DEBUG
(
LIS
->
print
(
dbgs
(
)
<<
"After coalescing\n"
,
MF
.
getFunction
(
)
.
getParent
(
)
)
)
;
for
(
MachineInstr
*
MI
:
Condsets
)
Changed
|=
split
(
*
MI
,
PredUpd
)
;
Condsets
.
clear
(
)
;
DEBUG
(
LIS
->
print
(
dbgs
(
)
<<
"After splitting\n"
,
MF
.
getFunction
(
)
.
getParent
(
)
)
)
;
for
(
auto
&
B
:
MF
)
Changed
|=
predicateInBlock
(
B
,
PredUpd
)
;
DEBUG
(
LIS
->
print
(
dbgs
(
)
<<
"After predicating\n"
,
MF
.
getFunction
(
)
.
getParent
(
)
)
)
;
PredUpd
.
insert
(
CoalUpd
.
begin
(
)
,
CoalUpd
.
end
(
)
)
;
updateLiveness
(
PredUpd
,
true
,
true
,
true
)
;
DEBUG
(
{
if
(
Changed
)
LIS
->
print
(
dbgs
(
)
<<
"After expand-condsets\n"
,
MF
.
getFunction
(
)
.
getParent
(
)
)
;
}
)
;
return
Changed
;
}
</s>

Hexagon
Hexagon
Hexagon
"Before expand-condsets\n"
16
"After coalescing\n"
"After splitting\n"
"After predicating\n"
"After expand-condsets\n"


<s> unsigned X86TargetLowering :: getAddressSpace ( ) const { if ( Subtarget . is64Bit ( ) ) return ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Kernel ) ? 256 : 257 ; return 256 ; } </s>

Return the address space of the Pointer type .


<s> void X86PassConfig :: addIRPasses ( ) { addPass ( createX86AtomicExpandPass ( & getX86TargetMachine ( ) ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> int mmix_use_simple_return ( void ) { int regno ; int stack_space_to_allocate = ( crtl -> outgoing_args_size + crtl -> args . pretend_args_size + get_frame_size ( ) + 7 ) & ~ 7 ; if ( ! TARGET_USE_RETURN_INSN || ! reload_completed ) return 0 ; for ( regno = 255 ; regno >= MMIX_FIRST_GLOBAL_REGNUM ; regno -- ) if ( ( ( ( regno != MMIX_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) && df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) ) ) || IS_MMIX_EH_RETURN_DATA_REG ( regno ) ) return 0 ; if ( frame_pointer_needed ) stack_space_to_allocate += 8 ; if ( MMIX_CFUN_HAS_LANDING_PAD ) stack_space_to_allocate += 16 ; else if ( MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS ) stack_space_to_allocate += 8 ; return stack_space_to_allocate == 0 ; } </s>

Nonzero when the function epilogue is simple enough that a single `` POP % d,0 '' should be used even within the function .


<s> bool SIInstrInfo :: shouldClusterMemOps ( ArrayRef < const MachineOperand * > BaseOps1 , ArrayRef < const MachineOperand * > BaseOps2 , unsigned NumLoads ) const { assert ( BaseOps1 . size ( ) == 1 && BaseOps2 . size ( ) == 1 ) ; const MachineOperand & BaseOp1 = * BaseOps1 . front ( ) ; const MachineOperand & BaseOp2 = * BaseOps2 . front ( ) ; const MachineInstr & FirstLdSt = * BaseOp1 . getParent ( ) ; const MachineInstr & SecondLdSt = * BaseOp2 . getParent ( ) ; if ( ! memOpsHaveSameBasePtr ( FirstLdSt , BaseOp1 , SecondLdSt , BaseOp2 ) ) return false ; const MachineOperand * FirstDst = nullptr ; const MachineOperand * SecondDst = nullptr ; if ( ( isMUBUF ( FirstLdSt ) && isMUBUF ( SecondLdSt ) ) || ( isMTBUF ( FirstLdSt ) && isMTBUF ( SecondLdSt ) ) || ( isFLAT ( FirstLdSt ) && isFLAT ( SecondLdSt ) ) ) { const unsigned MaxGlobalLoadCluster = 6 ; if ( NumLoads > MaxGlobalLoadCluster ) return false ; FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: vdata ) ; if ( ! FirstDst ) FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: vdst ) ; SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: vdata ) ; if ( ! SecondDst ) SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: vdst ) ; } else if ( isSMRD ( FirstLdSt ) && isSMRD ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: sdst ) ; SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: sdst ) ; } else if ( isDS ( FirstLdSt ) && isDS ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: vdst ) ; SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: vdst ) ; } if ( ! FirstDst || ! SecondDst ) return false ; unsigned LoadClusterThreshold = 16 ; const MachineRegisterInfo & MRI = FirstLdSt . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const Register Reg = FirstDst -> getReg ( ) ; const TargetRegisterClass * DstRC = Register :: isVirtualRegister ( Reg ) ? MRI . getRegClass ( Reg ) : RI . getPhysRegClass ( Reg ) ; return ( NumLoads * ( RI . getRegSizeInBits ( * DstRC ) / 8 ) ) <= LoadClusterThreshold ; } </s>

Returns true if the two given memory operations should be scheduled adjacent .

AMDGPU SI 1 1 6 AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName 16 8


<s> static void sparc_solaris_elf_asm_named_section ( const char * name , unsigned int flags , tree decl ATTRIBUTE_UNUSED ) { if ( HAVE_COMDAT_GROUP && flags & SECTION_LINKONCE ) { solaris_elf_asm_comdat_section ( name , flags , decl ) ; return ; } fprintf ( asm_out_file , "\t.section\t\"%s\"" , name ) ; if ( ! ( flags & SECTION_DEBUG ) ) fputs ( ",#alloc" , asm_out_file ) ; if ( flags & SECTION_WRITE ) fputs ( ",#write" , asm_out_file ) ; if ( flags & SECTION_TLS ) fputs ( ",#tls" , asm_out_file ) ; if ( flags & SECTION_CODE ) fputs ( ",#execinstr" , asm_out_file ) ; if ( flags & SECTION_NOTYPE ) ; else if ( flags & SECTION_BSS ) fputs ( ",#nobits" , asm_out_file ) ; else fputs ( ",#progbits" , asm_out_file ) ; fputc ( '\n' , asm_out_file ) ; } </s>

Solaris implementation of TARGET_ASM_NAMED_SECTION .

sparc "\t.section\t\"%s\"" ",#alloc" ",#write" ",#tls" ",#execinstr" ",#nobits" ",#progbits"


<s> SMLoc getStartLoc ( ) const override { return Start ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> SMLoc getLoc ( ) const { return getParser ( ) . getTok ( ) . getLoc ( ) ; } </s>

Get the source location of the point where the field was defined .


<s> SDValue LM32TargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: ConstantPool : return LowerConstantPool ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return LowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( Op , DAG ) ; case ISD :: SELECT_CC : return LowerSELECT_CC ( Op , DAG ) ; case ISD :: VASTART : return LowerVASTART ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> unsigned WebAssemblyFastISel :: fastMaterializeConstant ( const Constant * C ) { if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) { unsigned ResultReg = createResultReg ( Subtarget -> hasAddr64 ( ) ? & WebAssembly :: I64RegClass : & WebAssembly :: I32RegClass ) ; unsigned Opc = Subtarget -> hasAddr64 ( ) ? WebAssembly :: CONST_I64 : WebAssembly :: CONST_I32 ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addGlobalAddress ( GV ) ; return ResultReg ; } return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s>
void
BPFInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
MCRegister
DestReg
,
MCRegister
SrcReg
,
bool
KillSrc
)
const
{
if
(
BPF
::
GPRRegClass
.
contains
(
DestReg
,
SrcReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
BPF
::
MOV_rr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
if
(
BPF
::
GPR32RegClass
.
contains
(
DestReg
,
SrcReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
BPF
::
MOV_rr_32
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
</s>


<s> void xtensa_va_start ( tree valist , rtx nextarg ATTRIBUTE_UNUSED ) { tree f_stk , stk ; tree f_reg , reg ; tree f_ndx , ndx ; tree t , u ; int arg_words ; arg_words = current_function_args_info . arg_words ; f_stk = TYPE_FIELDS ( va_list_type_node ) ; f_reg = TREE_CHAIN ( f_stk ) ; f_ndx = TREE_CHAIN ( f_reg ) ; stk = build ( COMPONENT_REF , TREE_TYPE ( f_stk ) , valist , f_stk , NULL_TREE ) ; reg = build ( COMPONENT_REF , TREE_TYPE ( f_reg ) , valist , f_reg , NULL_TREE ) ; ndx = build ( COMPONENT_REF , TREE_TYPE ( f_ndx ) , valist , f_ndx , NULL_TREE ) ; u = make_tree ( ptr_type_node , expand_builtin_saveregs ( ) ) ; t = build ( MODIFY_EXPR , ptr_type_node , reg , u ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; u = make_tree ( ptr_type_node , virtual_incoming_args_rtx ) ; u = fold ( build ( PLUS_EXPR , ptr_type_node , u , build_int_cst ( NULL_TREE , - 32 ) ) ) ; t = build ( MODIFY_EXPR , ptr_type_node , stk , u ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; if ( arg_words >= MAX_ARGS_IN_REGISTERS ) arg_words += 2 ; u = build_int_cst ( NULL_TREE , arg_words * UNITS_PER_WORD ) ; t = build ( MODIFY_EXPR , integer_type_node , ndx , u ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; } </s>

Implement ` va_start ' for varargs and stdarg . We look at the current function to fill in an initial va_list .


<s> unsigned Tile64RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return T64 :: FramePointer ; } </s>


"-misched-topdown incompatible with -misched-bottomup"

Initialize the strategy after building the DAG for a new region .


<s> bool load_single_p ( rtx_insn * insn ) { if ( get_attr_type ( insn ) != TYPE_LOAD ) return false ; if ( INSN_CODE ( insn ) == CODE_FOR_move_di || INSN_CODE ( insn ) == CODE_FOR_move_df ) return false ; return true ; } </s>

Functions to determine whether INSN is single-word , double-word or partial-word load/store insn .


<s> virtual bool doFinalization ( Module & M ) { return false ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> bool n9_2r1w_consumed_by_ex_dep_p ( rtx_insn * consumer , rtx def_reg ) { rtx use_rtx ; switch ( get_attr_type ( consumer ) ) { case TYPE_ALU : if ( movd44_even_dep_p ( consumer , def_reg ) ) return true ; use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_PBSAD : case TYPE_MUL : use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_ALU_SHIFT : use_rtx = extract_shift_reg ( consumer ) ; break ; case TYPE_PBSADA : return pbsada_insn_ra_rb_dep_reg_p ( consumer , def_reg ) ; case TYPE_MAC : use_rtx = PATTERN ( consumer ) ; break ; case TYPE_DIV : if ( divmod_p ( consumer ) ) use_rtx = SET_SRC ( parallel_element ( consumer , 0 ) ) ; else use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_MMU : if ( GET_CODE ( PATTERN ( consumer ) ) == SET ) use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; else return true ; break ; case TYPE_LOAD : if ( post_update_insn_p ( consumer ) ) use_rtx = extract_base_reg ( consumer ) ; else use_rtx = extract_mem_rtx ( consumer ) ; break ; case TYPE_STORE : if ( post_update_insn_p ( consumer ) ) use_rtx = extract_base_reg ( consumer ) ; else use_rtx = extract_mem_rtx ( consumer ) ; if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; if ( ! post_update_insn_p ( consumer ) && ! immed_offset_p ( extract_mem_rtx ( consumer ) ) ) return false ; use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_LOAD_MULTIPLE : use_rtx = extract_base_reg ( consumer ) ; break ; case TYPE_STORE_MULTIPLE : use_rtx = extract_base_reg ( consumer ) ; if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; use_rtx = extract_nth_access_rtx ( consumer , 0 ) ; break ; case TYPE_BRANCH : use_rtx = PATTERN ( consumer ) ; break ; default : gcc_unreachable ( ) ; } if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; return false ; } </s>

Check the dependency between the producer defining DEF_REG and CONSUMER requiring input operand at EX .


"\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "

"type = %d, ind_levels = %d, win = %d, original addr:\n"

Debug version of rs6000_legitimize_reload_address .


<s> static enum flt_eval_method arm_excess_precision ( enum excess_precision_type type ) { switch ( type ) { case EXCESS_PRECISION_TYPE_FAST : case EXCESS_PRECISION_TYPE_STANDARD : return ( TARGET_VFP_FP16INST ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16 : FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ) ; case EXCESS_PRECISION_TYPE_IMPLICIT : case EXCESS_PRECISION_TYPE_FLOAT16 : return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16 ; default : gcc_unreachable ( ) ; } return FLT_EVAL_METHOD_UNPREDICTABLE ; } </s>

Set the value of FLT_EVAL_METHOD . ISO/IEC TS 18661-3 defines two values that we 'd like to make use of : 0 : evaluate all operations and constants , whose semantic type has at most the range and precision of type float , to the range and precision of float ; evaluate all other operations and constants to the range and precision of the semantic type ; N , where _FloatN is a supported interchange floating type evaluate all operations and constants , whose semantic type has at most the range and precision of _FloatN type , to the range and precision of the _FloatN type ; evaluate all other operations and constants to the range and precision of the semantic type ; If we have the ARMv8.2-A extensions then we support _Float16 in native precision , so we should set this to 16 . Otherwise , we support the type , but want to evaluate expressions in float precision , so set this to 0 .


<s> static void ix86_emit_save_regs_using_mov ( HOST_WIDE_INT cfa_offset ) { unsigned int regno ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( GENERAL_REGNO_P ( regno ) && ix86_save_reg ( regno , true , true ) ) { ix86_emit_save_reg_using_mov ( word_mode , regno , cfa_offset ) ; cfa_offset -= UNITS_PER_WORD ; } } </s>

Emit code to save registers using MOV insns . First register is restored from POINTER + OFFSET .


<s> static void loongarch_prepare_builtin_arg ( struct expand_operand * op , tree exp , unsigned int argno ) { tree arg ; rtx value ; arg = CALL_EXPR_ARG ( exp , argno ) ; value = expand_normal ( arg ) ; create_input_operand ( op , value , TYPE_MODE ( TREE_TYPE ( arg ) ) ) ; } </s>

Take argument ARGNO from EXP 's argument list and convert it into an expand operand . Store the operand in * OP .


<s> std :: vector < std :: string > swap ( SwapType swap ) { std :: string desc ; switch ( swap . GetName ( ) ) { case SwapTypeValue :: a0b0 : desc = "a0<->b0" ; break ; case SwapTypeValue :: a0b1 : desc = "a0<->b1" ; break ; case SwapTypeValue :: a1b0 : desc = "a1<->b0" ; break ; case SwapTypeValue :: a1b1 : desc = "a1<->b1" ; break ; case SwapTypeValue :: a0b0a1b1 : desc = "a<->b" ; break ; case SwapTypeValue :: a0b1a1b0 : desc = "a-x-b" ; break ; case SwapTypeValue :: a0b0a1 : desc = "a0->b0->a1" ; break ; case SwapTypeValue :: a0b1a1 : desc = "a0->b1->a1" ; break ; case SwapTypeValue :: a1b0a0 : desc = "a1->b0->a0" ; break ; case SwapTypeValue :: a1b1a0 : desc = "a1->b1->a0" ; break ; case SwapTypeValue :: b0a0b1 : desc = "b0->a0->b1" ; break ; case SwapTypeValue :: b0a1b1 : desc = "b0->a1->b1" ; break ; case SwapTypeValue :: b1a0b0 : desc = "b1->a0->b0" ; break ; case SwapTypeValue :: b1a1b0 : desc = "b1->a1->b0" ; break ; default : desc = "[ERROR]" ; } return D ( "swap" , desc ) ; } </s>

Provide a fast substitute to std : :swap < Use > that also works with less standard-compliant compilers .


<s>
MachineBasicBlock
*
RISCVTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
MBB
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
case
RISCV
::
SELECT_CC
:
case
RISCV
::
SELECT_CC64
:
case
RISCV
::
FSELECT_CC_F
:
case
RISCV
::
FSELECT_CC_D
:
return
emitSelectCC
(
MI
,
MBB
)
;
case
RISCV
::
CALL
:
case
RISCV
::
CALLREG
:
case
RISCV
::
CALL64
:
case
RISCV
::
CALLREG64
:
return
emitCALL
(
MI
,
MBB
)
;
case
RISCV
::
PEXTRACT_PSEUDO
:
case
RISCV
::
PEXTRACT_PSEUDO_REV
:
return
emitPEXTRACT
(
MI
,
MBB
,
false
)
;
case
RISCV
::
PEXTRACTU_PSEUDO
:
case
RISCV
::
PEXTRACTU_PSEUDO_REV
:
return
emitPEXTRACT
(
MI
,
MBB
,
true
)
;
case
RISCV
::
PINSERT_PSEUDO
:
return
emitPINSERT
(
MI
,
MBB
)
;
case
RISCV
::
PBCLR_PSEUDO
:
return
emitPBCLRSET
(
MI
,
MBB
,
false
)
;
case
RISCV
::
PBSET_PSEUDO
:
return
emitPBCLRSET
(
MI
,
MBB
,
true
)
;
case
RISCV
::
PADDRN_PSEUDO
:
case
RISCV
::
PADDURN_PSEUDO
:
case
RISCV
::
PSUBRN_PSEUDO
:
case
RISCV
::
PSUBURN_PSEUDO
:
return
emitPRN
(
MI
,
MBB
)
;
default
:
llvm_unreachable
(
"Unexpected instr type to insert"
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> void HexagonDAGToDAGISel :: Select ( SDNode * N ) { if ( N -> isMachineOpcode ( ) ) return N -> setNodeId ( - 1 ) ; switch ( N -> getOpcode ( ) ) { case ISD :: Constant : return SelectConstant ( N ) ; case ISD :: ConstantFP : return SelectConstantFP ( N ) ; case ISD :: FrameIndex : return SelectFrameIndex ( N ) ; case ISD :: SHL : return SelectSHL ( N ) ; case ISD :: LOAD : return SelectLoad ( N ) ; case ISD :: STORE : return SelectStore ( N ) ; case ISD :: INTRINSIC_W_CHAIN : return SelectIntrinsicWChain ( N ) ; case ISD :: INTRINSIC_WO_CHAIN : return SelectIntrinsicWOChain ( N ) ; case HexagonISD :: ADDC : case HexagonISD :: SUBC : return SelectAddSubCarry ( N ) ; case HexagonISD :: VALIGN : return SelectVAlign ( N ) ; case HexagonISD :: VALIGNADDR : return SelectVAlignAddr ( N ) ; case HexagonISD :: TYPECAST : return SelectTypecast ( N ) ; case HexagonISD :: P2D : return SelectP2D ( N ) ; case HexagonISD :: D2P : return SelectD2P ( N ) ; case HexagonISD :: Q2V : return SelectQ2V ( N ) ; case HexagonISD :: V2Q : return SelectV2Q ( N ) ; } if ( HST -> useHVXOps ( ) ) { switch ( N -> getOpcode ( ) ) { case ISD :: VECTOR_SHUFFLE : return SelectHvxShuffle ( N ) ; case HexagonISD :: VROR : return SelectHvxRor ( N ) ; } } SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> int ARMBaseInstrInfo :: getOperandLatency ( const InstrItineraryData * ItinData , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * UseMI , unsigned UseIdx ) const { if ( ! ItinData || ItinData -> isEmpty ( ) ) return - 1 ; const MachineOperand & DefMO = DefMI -> getOperand ( DefIdx ) ; unsigned Reg = DefMO . getReg ( ) ; const MCInstrDesc * DefMCID = & DefMI -> getDesc ( ) ; const MCInstrDesc * UseMCID = & UseMI -> getDesc ( ) ; unsigned DefAdj = 0 ; if ( DefMI -> isBundle ( ) ) { DefMI = getBundledDefMI ( & getRegisterInfo ( ) , DefMI , Reg , DefIdx , DefAdj ) ; DefMCID = & DefMI -> getDesc ( ) ; } if ( DefMI -> isCopyLike ( ) || DefMI -> isInsertSubreg ( ) || DefMI -> isRegSequence ( ) || DefMI -> isImplicitDef ( ) ) { return 1 ; } unsigned UseAdj = 0 ; if ( UseMI -> isBundle ( ) ) { unsigned NewUseIdx ; const MachineInstr * NewUseMI = getBundledUseMI ( & getRegisterInfo ( ) , UseMI , Reg , NewUseIdx , UseAdj ) ; if ( ! NewUseMI ) return - 1 ; UseMI = NewUseMI ; UseIdx = NewUseIdx ; UseMCID = & UseMI -> getDesc ( ) ; } if ( Reg == ARM :: CPSR ) { if ( DefMI -> getOpcode ( ) == ARM :: FMSTAT ) { return Subtarget . isCortexA9 ( ) ? 1 : 20 ; } if ( UseMI -> isBranch ( ) ) return 0 ; unsigned Latency = getInstrLatency ( ItinData , DefMI ) ; if ( Latency > 0 && Subtarget . isThumb2 ( ) ) { const MachineFunction * MF = DefMI -> getParent ( ) -> getParent ( ) ; if ( MF -> getFunction ( ) -> hasFnAttr ( Attribute :: OptimizeForSize ) ) -- Latency ; } return Latency ; } if ( DefMO . isImplicit ( ) || UseMI -> getOperand ( UseIdx ) . isImplicit ( ) ) return - 1 ; unsigned DefAlign = DefMI -> hasOneMemOperand ( ) ? ( * DefMI -> memoperands_begin ( ) ) -> getAlignment ( ) : 0 ; unsigned UseAlign = UseMI -> hasOneMemOperand ( ) ? ( * UseMI -> memoperands_begin ( ) ) -> getAlignment ( ) : 0 ; int Latency = getOperandLatency ( ItinData , * DefMCID , DefIdx , DefAlign , * UseMCID , UseIdx , UseAlign ) ; if ( Latency < 0 ) return Latency ; int Adj = DefAdj + UseAdj ; Adj += adjustDefLatency ( Subtarget , DefMI , DefMCID , DefAlign ) ; if ( Adj >= 0 || ( int ) Latency > - Adj ) { return Latency + Adj ; } return Latency ; } </s>

Compute and return the use operand latency of a given pair of def and use .


<s> bool PPCFastISel :: fastLowerArguments ( ) { return false ; } </s>

This method is called by target-independent code to do target- specific argument lowering .


<s> void Mips16TargetLowering :: getOpndList ( SmallVectorImpl < SDValue > & Ops , std :: deque < std :: pair < unsigned , SDValue > > & RegsToPass , bool IsPICCall , bool GlobalOrExternal , bool InternalLinkage , CallLoweringInfo & CLI , SDValue Callee , SDValue Chain ) const { SelectionDAG & DAG = CLI . DAG ; const char * Mips16HelperFunction = 0 ; bool NeedMips16Helper = false ; if ( getTargetMachine ( ) . Options . UseSoftFloat && Subtarget -> inMips16HardFloat ( ) ) { bool LookupHelper = true ; if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( CLI . Callee ) ) { Mips16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , S -> getSymbol ( ) } ; if ( std :: binary_search ( HardFloatLibCalls , array_endof ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; else { Mips16IntrinsicHelperType IntrinsicFind = { S -> getSymbol ( ) , "" } ; if ( std :: binary_search ( Mips16IntrinsicHelper , array_endof ( Mips16IntrinsicHelper ) , IntrinsicFind ) ) { const Mips16IntrinsicHelperType * h = ( std :: find ( Mips16IntrinsicHelper , array_endof ( Mips16IntrinsicHelper ) , IntrinsicFind ) ) ; Mips16HelperFunction = h -> Helper ; NeedMips16Helper = true ; LookupHelper = false ; } } } else if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( CLI . Callee ) ) { Mips16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , G -> getGlobal ( ) -> getName ( ) . data ( ) } ; if ( std :: binary_search ( HardFloatLibCalls , array_endof ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; } if ( LookupHelper ) Mips16HelperFunction = getMips16HelperFunction ( CLI . RetTy , CLI . Args , NeedMips16Helper ) ; } SDValue JumpTarget = Callee ; if ( IsPICCall || ! GlobalOrExternal ) { unsigned V0Reg = Mips :: V0 ; if ( NeedMips16Helper ) { RegsToPass . push_front ( std :: make_pair ( V0Reg , Callee ) ) ; JumpTarget = DAG . getExternalSymbol ( Mips16HelperFunction , getPointerTy ( ) ) ; JumpTarget = getAddrGlobal ( JumpTarget , DAG , MipsII :: MO_GOT ) ; } else RegsToPass . push_front ( std :: make_pair ( ( unsigned ) Mips :: T9 , Callee ) ) ; } Ops . push_back ( JumpTarget ) ; MipsTargetLowering :: getOpndList ( Ops , RegsToPass , IsPICCall , GlobalOrExternal , InternalLinkage , CLI , Callee , Chain ) ; } </s>

This function fills Ops , which is the list of operands that will later be used when a function call node is created .

Mips Mips Mips 0 Mips Mips Mips Mips "" Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips::V0 Mips Mips MipsII::MO_GOT Mips::T9 Mips


<s> bool HexagonTTIImpl :: shouldBuildLookupTables ( ) const { return EmitLookupTables ; } </s>

Return true if switches should be turned into lookup tables for the target .


<s> bool ARMAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == ".word" ) return parseDirectiveWord ( 4 , DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".thumb" ) return parseDirectiveThumb ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".arm" ) return parseDirectiveARM ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".thumb_func" ) return parseDirectiveThumbFunc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".code" ) return parseDirectiveCode ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".syntax" ) return parseDirectiveSyntax ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".unreq" ) return parseDirectiveUnreq ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".arch" ) return parseDirectiveArch ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".eabi_attribute" ) return parseDirectiveEabiAttr ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".cpu" ) return parseDirectiveCPU ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".fpu" ) return parseDirectiveFPU ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".fnstart" ) return parseDirectiveFnStart ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".fnend" ) return parseDirectiveFnEnd ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".cantunwind" ) return parseDirectiveCantUnwind ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".personality" ) return parseDirectivePersonality ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".handlerdata" ) return parseDirectiveHandlerData ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".setfp" ) return parseDirectiveSetFP ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".pad" ) return parseDirectivePad ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".save" ) return parseDirectiveRegSave ( DirectiveID . getLoc ( ) , false ) ; else if ( IDVal == ".vsave" ) return parseDirectiveRegSave ( DirectiveID . getLoc ( ) , true ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> static int parse_devices_csv ( const char * mcu_name ) { if ( msp430_devices_csv_loc != NULL ) return parse_devices_csv_1 ( msp430_devices_csv_loc , mcu_name ) ; else if ( derived_devices_csv_loc != NULL ) return parse_devices_csv_1 ( derived_devices_csv_loc , mcu_name ) ; if ( msp430_check_env_var_for_devices ( & derived_devices_csv_loc ) ) return 2 ; return parse_devices_csv_1 ( derived_devices_csv_loc , mcu_name ) ; } </s>

Wrapper for the parse_devices_csv_1 work function . A return code of 0 indicates that the MCU data has been successfully extracted into extracted_mcu_data . A return code of 1 indicates that the specified MCU was n't found in devices.csv . A return code of 2 indicates that devices.csv was n't found at all .


";; Sequence not recognized, giving up.\n\n"

Return true if we see an insn stream generated by casesi expander together with an extension to SImode of the switch value . If this is the case , fill in the insns from casesi to INSNS [ 1 .. 5 ] and the SImode extension to INSNS [ 0 ] . Moreover , extract the operands of pattern casesi_ < mode > _sequence forged from the sequence to recog_data .


<s> DecodeStatus Mips64Disassembler :: getInstruction ( MCInst & instr , uint64_t & Size , const MemoryObject & Region , uint64_t Address , raw_ostream & vStream , raw_ostream & cStream ) const { uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Region , Address , Size , Insn , isBigEndian , false ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTableMips6432 , instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } Result = decodeInstruction ( DecoderTableMips32 , instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s> void arm_expand_vcond ( rtx * operands , machine_mode cmp_result_mode ) { rtx mask = gen_reg_rtx ( cmp_result_mode ) ; bool inverted = arm_expand_vector_compare ( mask , GET_CODE ( operands [ 3 ] ) , operands [ 4 ] , operands [ 5 ] , true ) ; if ( inverted ) std :: swap ( operands [ 1 ] , operands [ 2 ] ) ; emit_insn ( gen_neon_vbsl ( GET_MODE ( operands [ 0 ] ) , operands [ 0 ] , mask , operands [ 1 ] , operands [ 2 ] ) ) ; } </s>

Expand a vcond or vcondu pattern with operands OPERANDS . CMP_RESULT_MODE is the mode of the comparison result .


<s> void assignValueToAddress ( const CallLowering :: ArgInfo & Arg , Register Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { unsigned MaxSize = Size * 8 ; if ( ! Arg . IsFixed ) MaxSize = 0 ; Register ValVReg = VA . getLocInfo ( ) != CCValAssign :: LocInfo :: FPExt ? extendRegister ( Arg . Regs [ 0 ] , VA , MaxSize ) : Arg . Regs [ 0 ] ; const LLT RegTy = MRI . getType ( ValVReg ) ; if ( RegTy . getSizeInBytes ( ) > Size ) Size = RegTy . getSizeInBytes ( ) ; assignValueToAddress ( ValVReg , Addr , Size , MPO , VA ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> bool X86TargetLowering :: isTypeDesirableForOp ( unsigned Opc , EVT VT ) const { if ( ! isTypeLegal ( VT ) ) return false ; if ( Opc == ISD :: SHL && VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i8 ) return false ; if ( Opc == ISD :: MUL && VT == MVT :: i8 ) return false ; if ( VT == MVT :: i16 ) { switch ( Opc ) { default : break ; case ISD :: LOAD : case ISD :: SIGN_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: ANY_EXTEND : case ISD :: SHL : case ISD :: SRL : case ISD :: SUB : case ISD :: ADD : case ISD :: MUL : case ISD :: AND : case ISD :: OR : case ISD :: XOR : return false ; } } return true ; } </s>

Return true if the target has native support for the specified value type and it is 'desirable ' to use the type for the given node type .


<s> bool PPCAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == ".word" ) return ParseDirectiveWord ( 2 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".llong" ) return ParseDirectiveWord ( 8 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".tc" ) return ParseDirectiveTC ( isPPC64 ( ) ? 8 : 4 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".machine" ) return ParseDirectiveMachine ( DirectiveID . getLoc ( ) ) ; return true ; } </s>


<s> void LM32MCInstLower :: lower ( const MachineInstr * MI , MCInst & OutMI ) const { OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( unsigned I = 0 , E = MI -> getNumOperands ( ) ; I != E ; ++ I ) { const MachineOperand & MO = MI -> getOperand ( I ) ; if ( ! MO . isReg ( ) || ! MO . isImplicit ( ) ) OutMI . addOperand ( lowerOperand ( MO ) ) ; } } </s>


<s> bool ARMTargetLowering :: isFMAFasterThanFMulAndFAdd ( const MachineFunction & MF , EVT VT ) const { if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: v4f32 : case MVT :: v8f16 : return Subtarget -> hasMVEFloatOps ( ) ; case MVT :: f16 : return Subtarget -> useFPVFMx16 ( ) ; case MVT :: f32 : return Subtarget -> useFPVFMx ( ) ; case MVT :: f64 : return Subtarget -> useFPVFMx64 ( ) ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s>
bool
P2AsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNum
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
)
{
return
true
;
}
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNum
)
;
assert
(
MO
.
isReg
(
)
&&
"unexpected inline asm memory operand"
)
;
O
<<
P2InstPrinter
::
getRegisterName
(
MO
.
getReg
(
)
)
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s>
unsigned
getReg
(
)
const
override
{
llvm_unreachable
(
"Invalid type access!"
)
;
}
</s>

Returns the register associated with this edge .


<s>
bool
BPFAsmPrinter
::
doInitialization
(
Module
&
M
)
{
AsmPrinter
::
doInitialization
(
M
)
;
if
(
MAI
->
doesSupportDebugInformation
(
)
&&
!
M
.
debug_compile_units
(
)
.
empty
(
)
)
{
Handlers
.
emplace_back
(
llvm
::
make_unique
<
BTFDebug
>
(
this
)
,
"emit"
,
"Debug Info Emission"
,
"BTF"
,
"BTF Emission"
)
;
}
return
false
;
}
</s>

Set up the AsmPrinter when we are working on a new module .

BPF
BPF
"emit"
"Debug Info Emission"
"BTF"
"BTF Emission"


<s> X86DCModule & getParent ( ) { return static_cast < X86DCModule & > ( DCFunction :: getParent ( ) ) ; } </s>

getParent - Return the last analyzed interval .


<s> bool ARMFrameLowering :: canSimplifyCallFramePseudos ( const MachineFunction & MF ) const { return hasReservedCallFrame ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

canSimplifyCallFramePseudos - If there is a reserved call frame , the call frame pseudos can be simplified .


<s> void ARMFrameLowering :: getCalleeSaves ( const MachineFunction & MF , BitVector & SavedRegs ) const { TargetFrameLowering :: getCalleeSaves ( MF , SavedRegs ) ; const ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( AFI -> getPreservesR0 ( ) ) SavedRegs . set ( ARM :: R0 ) ; } </s>

Returns the callee-saved registers as computed by determineCalleeSaves in the BitVector SavedRegs .


<s> const unsigned * X86RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { bool callsEHReturn = false ; if ( MF ) { const MachineFrameInfo * MFI = MF -> getFrameInfo ( ) ; const MachineModuleInfo * MMI = MFI -> getMachineModuleInfo ( ) ; callsEHReturn = ( MMI ? MMI -> callsEHReturn ( ) : false ) ; } static const unsigned CalleeSavedRegs32Bit [ ] = { X86 :: ESI , X86 :: EDI , X86 :: EBX , X86 :: EBP , 0 } ; static const unsigned CalleeSavedRegs32EHRet [ ] = { X86 :: EAX , X86 :: EDX , X86 :: ESI , X86 :: EDI , X86 :: EBX , X86 :: EBP , 0 } ; static const unsigned CalleeSavedRegs64Bit [ ] = { X86 :: RBX , X86 :: R12 , X86 :: R13 , X86 :: R14 , X86 :: R15 , X86 :: RBP , 0 } ; static const unsigned CalleeSavedRegs64EHRet [ ] = { X86 :: RAX , X86 :: RDX , X86 :: RBX , X86 :: R12 , X86 :: R13 , X86 :: R14 , X86 :: R15 , X86 :: RBP , 0 } ; static const unsigned CalleeSavedRegsWin64 [ ] = { X86 :: RBX , X86 :: RBP , X86 :: RDI , X86 :: RSI , X86 :: R12 , X86 :: R13 , X86 :: R14 , X86 :: R15 , X86 :: XMM6 , X86 :: XMM7 , X86 :: XMM8 , X86 :: XMM9 , X86 :: XMM10 , X86 :: XMM11 , X86 :: XMM12 , X86 :: XMM13 , X86 :: XMM14 , X86 :: XMM15 , 0 } ; if ( Is64Bit ) { if ( IsWin64 ) return CalleeSavedRegsWin64 ; else return ( callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit ) ; } else { return ( callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit ) ; } } </s>


<s> void LanaiAsmPrinter :: emitInstruction ( const MachineInstr * MI ) { MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { if ( I -> isCall ( ) ) { emitCallInstruction ( & * I ) ; continue ; } customEmitInstruction ( & * I ) ; } while ( ( ++ I != E ) && I -> isInsideBundle ( ) ) ; } </s>

Targets should implement this to emit instructions .


<s>
unsigned
X86TTI
::
getScalarizationOverhead
(
Type
*
Ty
,
bool
Insert
,
bool
Extract
)
const
{
assert
(
Ty
->
isVectorTy
(
)
&&
"Can only scalarize vectors"
)
;
unsigned
Cost
=
0
;
for
(
int
i
=
0
,
e
=
Ty
->
getVectorNumElements
(
)
;
i
<
e
;
++
i
)
{
if
(
Insert
)
Cost
+=
TopTTI
->
getVectorInstrCost
(
Instruction
::
InsertElement
,
Ty
,
i
)
;
if
(
Extract
)
Cost
+=
TopTTI
->
getVectorInstrCost
(
Instruction
::
ExtractElement
,
Ty
,
i
)
;
}
return
Cost
;
}
</s>

Estimate the overhead of scalarizing an instruction .


<s> static bool rs6000_cannot_force_const_mem ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { if ( GET_CODE ( x ) == HIGH && GET_CODE ( XEXP ( x , 0 ) ) == UNSPEC ) return true ; if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && SYMBOL_REF_P ( XEXP ( XEXP ( x , 0 ) , 0 ) ) && SYMBOL_REF_TLS_MODEL ( XEXP ( XEXP ( x , 0 ) , 0 ) ) != 0 ) return true ; return TARGET_ELF && tls_referenced_p ( x ) ; } </s>


<s> void sparc_emit_call_insn ( rtx pat , rtx addr ) { rtx_insn * insn ; insn = emit_call_insn ( pat ) ; if ( TARGET_VXWORKS_RTP && flag_pic && GET_CODE ( addr ) == SYMBOL_REF && ( SYMBOL_REF_DECL ( addr ) ? ! targetm . binds_local_p ( SYMBOL_REF_DECL ( addr ) ) : ! SYMBOL_REF_LOCAL_P ( addr ) ) ) { use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , pic_offset_table_rtx ) ; crtl -> uses_pic_offset_table = 1 ; } } </s>

Emit a call instruction with the pattern given by PAT . ADDR is the address of the call target .


<s> bool RISCVAsmParser :: processInstruction ( MCInst & Inst , SMLoc IDLoc , MCStreamer & Out ) { Inst . setLoc ( IDLoc ) ; switch ( Inst . getOpcode ( ) ) { default : break ; case RISCV :: PseudoLI : { unsigned Reg = Inst . getOperand ( 0 ) . getReg ( ) ; const MCOperand & Op1 = Inst . getOperand ( 1 ) ; if ( Op1 . isExpr ( ) ) { emitToStreamer ( Out , MCInstBuilder ( RISCV :: ADDI ) . addReg ( Reg ) . addReg ( RISCV :: X0 ) . addExpr ( Op1 . getExpr ( ) ) ) ; return false ; } int64_t Imm = Inst . getOperand ( 1 ) . getImm ( ) ; if ( ! isRV64 ( ) ) Imm = SignExtend64 < 32 > ( Imm ) ; emitLoadImm ( Reg , Imm , Out ) ; return false ; } case RISCV :: PseudoLLA : emitLoadLocalAddress ( Inst , IDLoc , Out ) ; return false ; case RISCV :: PseudoLA : emitLoadAddress ( Inst , IDLoc , Out ) ; return false ; } emitToStreamer ( Out , Inst ) ; return false ; } </s>

Process a single instruction and collect debug info anchors .


<s> bool TeakAsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> unsigned char AArch64Subtarget :: ClassifyGlobalReference ( const GlobalValue * GV , const TargetMachine & TM ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) ) return AArch64II :: MO_GOT ; unsigned Flags = GV -> hasDLLImportStorageClass ( ) ? AArch64II :: MO_DLLIMPORT : AArch64II :: MO_NO_FLAG ; if ( ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return AArch64II :: MO_GOT | Flags ; if ( ( useSmallAddressing ( ) || TM . getCodeModel ( ) == CodeModel :: Tiny ) && GV -> hasExternalWeakLinkage ( ) ) return AArch64II :: MO_GOT | Flags ; return Flags ; } </s>

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be referenced for the current subtarget .


<s> static bool harmless_null_pointer_p ( rtx mem , int np_reg ) { mem = XEXP ( mem , 0 ) ; if ( GET_CODE ( mem ) == POST_INC || GET_CODE ( mem ) == POST_DEC ) mem = XEXP ( mem , 0 ) ; if ( REG_P ( mem ) && ( int ) REGNO ( mem ) == np_reg ) return true ; if ( GET_CODE ( mem ) == PLUS && REG_P ( XEXP ( mem , 0 ) ) && ( int ) REGNO ( XEXP ( mem , 0 ) ) == np_reg ) { mem = XEXP ( mem , 1 ) ; if ( GET_CODE ( mem ) == CONST_INT && INTVAL ( mem ) > 0 ) return true ; } return false ; } </s>

Return true iff the address found in MEM is based on the register NP_REG and optionally has a positive offset .


"getIntImmCost can only estimate cost of materialising integers"

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> static void detect_caches_cpuid2 ( bool xeon_mp , struct cache_desc * level1 , struct cache_desc * level2 ) { unsigned regs [ 4 ] ; int nreps , i ; __cpuid ( 2 , regs [ 0 ] , regs [ 1 ] , regs [ 2 ] , regs [ 3 ] ) ; nreps = regs [ 0 ] & 0x0f ; regs [ 0 ] &= ~ 0x0f ; while ( -- nreps >= 0 ) { for ( i = 0 ; i < 4 ; i ++ ) if ( regs [ i ] && ! ( ( regs [ i ] >> 31 ) & 1 ) ) decode_caches_intel ( regs [ i ] , xeon_mp , level1 , level2 ) ; if ( nreps ) __cpuid ( 2 , regs [ 0 ] , regs [ 1 ] , regs [ 2 ] , regs [ 3 ] ) ; } } </s>

Detect cache parameters using CPUID function 2 .


<s> void MipsSEFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned BP = ABI . IsN64 ( ) ? Mips :: S7_64 : Mips :: S7 ; if ( hasFP ( MF ) ) setAliasRegs ( MF , SavedRegs , FP ) ; if ( hasBP ( MF ) ) setAliasRegs ( MF , SavedRegs , BP ) ; if ( MipsFI -> callsEhReturn ( ) ) MipsFI -> createEhDataRegsFI ( ) ; if ( MipsFI -> isISR ( ) ) MipsFI -> createISRRegFI ( ) ; if ( ExpandPseudo ( MF ) . expand ( ) ) { const TargetRegisterClass * RC = STI . hasMips64 ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } uint64_t MaxSPOffset = MF . getInfo < MipsFunctionInfo > ( ) -> getIncomingArgSize ( ) + estimateStackSize ( MF ) ; if ( isInt < 16 > ( MaxSPOffset ) ) return ; const TargetRegisterClass * RC = ABI . ArePtrs64bit ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> static bool c6x_vector_mode_supported_p ( machine_mode mode ) { switch ( mode ) { case E_V2HImode : case E_V4QImode : case E_V2SImode : case E_V4HImode : case E_V8QImode : return true ; default : return false ; } } </s>

Implements target hook vector_mode_supported_p .


<s> static void arm_set_current_function ( tree fndecl ) { if ( ! fndecl || fndecl == arm_previous_fndecl ) return ; tree old_tree = ( arm_previous_fndecl ? DECL_FUNCTION_SPECIFIC_TARGET ( arm_previous_fndecl ) : NULL_TREE ) ; tree new_tree = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( ! new_tree && old_tree ) new_tree = target_option_default_node ; if ( old_tree == new_tree ) return ; arm_previous_fndecl = fndecl ; cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( new_tree ) ) ; save_restore_target_globals ( new_tree ) ; arm_override_options_after_change_1 ( & global_options , & global_options_set ) ; } </s>

Establish appropriate back-end context for processing the function FNDECL . The argument might be NULL to indicate processing at top level , outside of any function scope .


<s> unsigned HexagonGenInsert :: distance ( const MachineBasicBlock * FromB , const MachineBasicBlock * ToB , const UnsignedMap & RPO , PairMapType & M ) const { assert ( FromB != ToB ) ; unsigned FromN = FromB -> getNumber ( ) , ToN = ToB -> getNumber ( ) ; PairMapType :: iterator F = M . find ( std :: make_pair ( FromN , ToN ) ) ; if ( F != M . end ( ) ) return F -> second ; unsigned ToRPO = RPO . lookup ( ToN ) ; unsigned MaxD = 0 ; using pred_iterator = MachineBasicBlock :: const_pred_iterator ; for ( pred_iterator I = ToB -> pred_begin ( ) , E = ToB -> pred_end ( ) ; I != E ; ++ I ) { const MachineBasicBlock * PB = * I ; if ( PB == FromB || RPO . lookup ( PB -> getNumber ( ) ) >= ToRPO ) continue ; unsigned D = PB -> size ( ) + distance ( FromB , PB , RPO , M ) ; if ( D > MaxD ) MaxD = D ; } M . insert ( std :: make_pair ( std :: make_pair ( FromN , ToN ) , MaxD ) ) ; return MaxD ; } </s>

Return the distance from this index to the given one .


<s> registered_function & function_builder :: add_function ( const function_instance & instance , const char * name , tree fntype , tree attrs , bool placeholder_p ) { unsigned int code = vec_safe_length ( registered_functions ) ; code = ( code << RISCV_BUILTIN_SHIFT ) + RISCV_BUILTIN_VECTOR ; tree decl = placeholder_p ? integer_zero_node : simulate_builtin_function_decl ( input_location , name , fntype , code , NULL , attrs ) ; registered_function & rfn = * ggc_alloc < registered_function > ( ) ; rfn . instance = instance ; rfn . decl = decl ; vec_safe_push ( registered_functions , & rfn ) ; return rfn ; } </s>

Add a function called NAME with type FNTYPE and attributes ATTRS . INSTANCE describes what the function does .


<s> bool MipsDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { bool Ret = SelectionDAGISel :: runOnMachineFunction ( MF ) ; processFunctionAfterISel ( MF ) ; return Ret ; } </s>

runOnMachineFunction - Emit the function body .


<s>
void
AArch64TargetLowering
::
computeKnownBitsForTargetNode
(
const
SDValue
Op
,
KnownBits
&
Known
,
const
APInt
&
DemandedElts
,
const
SelectionDAG
&
DAG
,
unsigned
Depth
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
break
;
case
AArch64ISD
::
CSEL
:
{
KnownBits
Known2
;
Known
=
DAG
.
computeKnownBits
(
Op
->
getOperand
(
0
)
,
Depth
+
1
)
;
Known2
=
DAG
.
computeKnownBits
(
Op
->
getOperand
(
1
)
,
Depth
+
1
)
;
Known
.
Zero
&=
Known2
.
Zero
;
Known
.
One
&=
Known2
.
One
;
break
;
}
case
ISD
::
INTRINSIC_W_CHAIN
:
{
ConstantSDNode
*
CN
=
cast
<
ConstantSDNode
>
(
Op
->
getOperand
(
1
)
)
;
Intrinsic
::
ID
IntID
=
static_cast
<
Intrinsic
::
ID
>
(
CN
->
getZExtValue
(
)
)
;
switch
(
IntID
)
{
default
:
return
;
case
Intrinsic
::
aarch64_ldaxr
:
case
Intrinsic
::
aarch64_ldxr
:
{
unsigned
BitWidth
=
Known
.
getBitWidth
(
)
;
EVT
VT
=
cast
<
MemIntrinsicSDNode
>
(
Op
)
->
getMemoryVT
(
)
;
unsigned
MemBits
=
VT
.
getScalarSizeInBits
(
)
;
Known
.
Zero
|=
APInt
::
getHighBitsSet
(
BitWidth
,
BitWidth
MemBits
)
;
return
;
}
}
break
;
}
case
ISD
::
INTRINSIC_WO_CHAIN
:
case
ISD
::
INTRINSIC_VOID
:
{
unsigned
IntNo
=
cast
<
ConstantSDNode
>
(
Op
.
getOperand
(
0
)
)
->
getZExtValue
(
)
;
switch
(
IntNo
)
{
default
:
break
;
case
Intrinsic
::
aarch64_neon_umaxv
:
case
Intrinsic
::
aarch64_neon_uminv
:
{
MVT
VT
=
Op
.
getOperand
(
1
)
.
getValueType
(
)
.
getSimpleVT
(
)
;
unsigned
BitWidth
=
Known
.
getBitWidth
(
)
;
if
(
VT
==
MVT
::
v8i8
||
VT
==
MVT
::
v16i8
)
{
assert
(
BitWidth
>=
8
&&
"Unexpected width!"
)
;
APInt
Mask
=
APInt
::
getHighBitsSet
(
BitWidth
,
BitWidth
8
)
;
Known
.
Zero
|=
Mask
;
}
else
if
(
VT
==
MVT
::
v4i16
||
VT
==
MVT
::
v8i16
)
{
assert
(
BitWidth
>=
16
&&
"Unexpected width!"
)
;
APInt
Mask
=
APInt
::
getHighBitsSet
(
BitWidth
,
BitWidth
16
)
;
Known
.
Zero
|=
Mask
;
}
break
;
}
break
;
}
}
}
}
</s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> void push ( int rn , enum machine_mode mode ) { emit_insn ( gen_push ( gen_rtx_REG ( mode , rn ) , mode ) ) ; } </s>

Output RTL to push register RN onto the stack .


<s> static void tilegx_va_start ( tree valist , rtx nextarg ATTRIBUTE_UNUSED ) { tree f_args , f_skip ; tree args , skip , t ; f_args = TYPE_FIELDS ( TREE_TYPE ( valist ) ) ; f_skip = TREE_CHAIN ( f_args ) ; args = build3 ( COMPONENT_REF , TREE_TYPE ( f_args ) , valist , f_args , NULL_TREE ) ; skip = build3 ( COMPONENT_REF , TREE_TYPE ( f_skip ) , valist , f_skip , NULL_TREE ) ; t = make_tree ( TREE_TYPE ( args ) , virtual_incoming_args_rtx ) ; t = fold_build_pointer_plus_hwi ( t , UNITS_PER_WORD * ( crtl -> args . info - TILEGX_NUM_ARG_REGS ) ) ; if ( crtl -> args . pretend_args_size > 0 ) t = fold_build_pointer_plus_hwi ( t , - STACK_POINTER_OFFSET ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( args ) , args , t ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( skip ) , virtual_incoming_args_rtx ) ; t = fold_build_pointer_plus_hwi ( t , - STACK_POINTER_OFFSET ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( skip ) , skip , t ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; } </s>


<s> void mips_expand_synci_loop ( rtx begin , rtx end ) { rtx inc , cmp_result , mask , length ; rtx_code_label * label , * end_label ; end_label = gen_label_rtx ( ) ; cmp_result = gen_rtx_EQ ( VOIDmode , begin , end ) ; emit_jump_insn ( gen_condjump ( cmp_result , end_label ) ) ; inc = gen_reg_rtx ( Pmode ) ; emit_insn ( PMODE_INSN ( gen_rdhwr_synci_step , ( inc ) ) ) ; cmp_result = gen_rtx_EQ ( VOIDmode , inc , const0_rtx ) ; emit_jump_insn ( gen_condjump ( cmp_result , end_label ) ) ; mask = mips_force_unary ( Pmode , NEG , inc ) ; begin = mips_force_binary ( Pmode , AND , begin , mask ) ; length = mips_force_binary ( Pmode , MINUS , end , begin ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; emit_insn ( gen_synci ( begin ) ) ; mips_emit_binary ( MINUS , length , length , inc ) ; mips_emit_binary ( PLUS , begin , begin , inc ) ; cmp_result = gen_rtx_GT ( VOIDmode , length , const0_rtx ) ; emit_jump_insn ( gen_condjump ( cmp_result , label ) ) ; emit_label ( end_label ) ; } </s>

Expand a loop of synci insns for the address range [ BEGIN , END ) .


<s> static bool mips_expand_vselect_vconcat ( rtx target , rtx op0 , rtx op1 , const unsigned char * perm , unsigned nelt ) { machine_mode v2mode ; rtx x ; v2mode = GET_MODE_2XWIDER_MODE ( GET_MODE ( op0 ) ) ; x = gen_rtx_VEC_CONCAT ( v2mode , op0 , op1 ) ; return mips_expand_vselect ( target , x , perm , nelt ) ; } </s>

Similar , but generate a vec_concat from op0 and op1 as well .


<s> static int gen_v9_scc ( rtx dest , enum rtx_code compare_code , rtx x , rtx y ) { if ( ! TARGET_ARCH64 && ( GET_MODE ( x ) == DImode || GET_MODE ( dest ) == DImode ) ) return 0 ; if ( TARGET_ARCH64 && GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_INT && y == const0_rtx && v9_regcmp_p ( compare_code ) ) { rtx op0 = x ; rtx temp ; if ( compare_code == NE && GET_MODE ( dest ) == DImode && rtx_equal_p ( op0 , dest ) ) { emit_insn ( gen_rtx_SET ( dest , gen_rtx_IF_THEN_ELSE ( DImode , gen_rtx_fmt_ee ( compare_code , DImode , op0 , const0_rtx ) , const1_rtx , dest ) ) ) ; return 1 ; } if ( reg_overlap_mentioned_p ( dest , op0 ) ) { op0 = gen_reg_rtx ( GET_MODE ( x ) ) ; emit_move_insn ( op0 , x ) ; } emit_insn ( gen_rtx_SET ( dest , const0_rtx ) ) ; if ( GET_MODE ( op0 ) != DImode ) { temp = gen_reg_rtx ( DImode ) ; convert_move ( temp , op0 , 0 ) ; } else temp = op0 ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_IF_THEN_ELSE ( GET_MODE ( dest ) , gen_rtx_fmt_ee ( compare_code , DImode , temp , const0_rtx ) , const1_rtx , dest ) ) ) ; return 1 ; } else { x = gen_compare_reg_1 ( compare_code , x , y ) ; y = const0_rtx ; gcc_assert ( GET_MODE ( x ) != CC_NOOVmode && GET_MODE ( x ) != CCX_NOOVmode ) ; emit_insn ( gen_rtx_SET ( dest , const0_rtx ) ) ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_IF_THEN_ELSE ( GET_MODE ( dest ) , gen_rtx_fmt_ee ( compare_code , GET_MODE ( x ) , x , y ) , const1_rtx , dest ) ) ) ; return 1 ; } } </s>

This function is used for v9 only . CODE is the code for an Scc 's comparison . OPERANDS [ 0 ] is the target of the Scc insn . OPERANDS [ 1 ] is the value we compare against const0_rtx ( which has n't been generated yet ) . This function is needed to turn ( set ( reg : SI 110 ) ( gt ( reg : CCX 100 % icc ) ( const_int 0 ) ) ) into ( set ( reg : SI 110 ) ( gt : DI ( reg : CCX 100 % icc ) ( const_int 0 ) ) ) IE : The instruction recognizer needs to see the mode of the comparison to find the right instruction . We could use `` gt : DI '' right in the define_expand , but leaving it out allows us to handle DI , SI , etc . We refer to the global sparc compare operands sparc_compare_op0 and sparc_compare_op1 .


<s> void rs6000_sibcall_aix ( rtx value , rtx func_desc , rtx flag , rtx cookie ) { rtx call [ 2 ] ; rtx insn ; gcc_assert ( INTVAL ( cookie ) == 0 ) ; call [ 0 ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_desc ) , flag ) ; if ( value != NULL_RTX ) call [ 0 ] = gen_rtx_SET ( value , call [ 0 ] ) ; call [ 1 ] = simple_return_rtx ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( 2 , call ) ) ; insn = emit_call_insn ( insn ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , gen_rtx_REG ( Pmode , TOC_REGNUM ) ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; } </s>

Expand code to perform a sibling call under the AIX or ELFv2 ABI .


This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> static enum riscv_symbol_type riscv_classify_symbol ( const_rtx x ) { if ( riscv_tls_symbol_p ( x ) ) return SYMBOL_TLS ; if ( GET_CODE ( x ) == SYMBOL_REF && flag_pic && ! riscv_symbol_binds_local_p ( x ) ) return SYMBOL_GOT_DISP ; return riscv_cmodel == CM_MEDLOW ? SYMBOL_ABSOLUTE : SYMBOL_PCREL ; } </s>

Return the method that should be used to access SYMBOL_REF or LABEL_REF X .


<s> tree i386_pe_mangle_assembler_name ( const char * name ) { const char * skipped = name + ( * name == '*' ? 1 : 0 ) ; const char * stripped = targetm . strip_name_encoding ( skipped ) ; if ( * name != '*' && * user_label_prefix && * stripped != FASTCALL_PREFIX ) stripped = ACONCAT ( ( user_label_prefix , stripped , NULL ) ) ; return get_identifier ( stripped ) ; } </s>

This hook behaves the same as varasm.cc/assemble_name ( ) , but generates the name into memory rather than outputting it to a file stream .


<s> static bool nvptx_needs_shared_bcast ( unsigned mask ) { bool worker = mask & GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ; bool large_vector = ( mask & GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) ) && nvptx_mach_vector_length ( ) != PTX_WARP_SIZE ; return worker || large_vector ; } </s>

Return true if MASK contains parallelism that requires shared memory to broadcast .


<s> const TargetRegisterClass * ARMBaseRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { const TargetRegisterClass * Super = RC ; TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case ARM :: GPRRegClassID : case ARM :: SPRRegClassID : case ARM :: DPRRegClassID : case ARM :: GPRPairRegClassID : return Super ; case ARM :: QPRRegClassID : case ARM :: QQPRRegClassID : case ARM :: QQQQPRRegClassID : if ( MF . getSubtarget < ARMSubtarget > ( ) . hasNEON ( ) ) return Super ; break ; case ARM :: MQPRRegClassID : case ARM :: MQQPRRegClassID : case ARM :: MQQQQPRRegClassID : if ( MF . getSubtarget < ARMSubtarget > ( ) . hasMVEIntegerOps ( ) ) return Super ; break ; } Super = * I ++ ; } while ( Super ) ; return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .

ARM ARM ARM::GPRRegClassID ARM::SPRRegClassID ARM::DPRRegClassID ARM::GPRPairRegClassID ARM::QPRRegClassID ARM::QQPRRegClassID ARM::QQQQPRRegClassID ARM ARM::MQPRRegClassID ARM::MQQPRRegClassID ARM::MQQQQPRRegClassID ARM


<s> bool X86FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; const TargetRegisterInfo * RI = TM . getRegisterInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RI -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


"\n%s -G value = %d, Arch = %s, ISA = %d\n"


<s> MCAssembler * getAssembler ( ) const { MCAssembler * Assembler = nullptr ; if ( ! Parser . getStreamer ( ) . hasRawTextSupport ( ) ) { MCELFStreamer * MES = static_cast < MCELFStreamer * > ( & Parser . getStreamer ( ) ) ; Assembler = & MES -> getAssembler ( ) ; } return Assembler ; } </s>

Get the assembler object this is a layout for .


<s> static int arm_barrier_cost ( rtx insn ) { int base_cost = 50 ; rtx next = next_nonnote_insn ( insn ) ; if ( next != NULL && LABEL_P ( next ) ) base_cost -= 20 ; switch ( GET_CODE ( insn ) ) { case CODE_LABEL : return 50 ; case INSN : case CALL_INSN : return base_cost ; case JUMP_INSN : return base_cost - 10 ; default : return base_cost + 10 ; } } </s>

Return the cost of forcibly inserting a barrier after INSN .


<s> SDValue MipsTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , unsigned CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_Mips ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> void setAlignment ( unsigned Align ) { Alignment = Align ; } </s>

setAlignment - Set the alignment of the function .


<s>
SDValue
DLXTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> static void cris_file_start ( void ) { targetm . file_start_app_off = ! ( TARGET_PDEBUG || flag_print_asm_name ) ; targetm . file_start_file_directive = TARGET_ELF ; default_file_start ( ) ; } </s>

Boilerplate emitted at start of file . NO_APP * only at file start * means faster assembly . It also means comments are not allowed . In some cases comments will be output for debugging purposes . Make sure they are allowed then . We want a .file directive only if TARGET_ELF .


<s> static void aarch64_emit_load_exclusive ( machine_mode mode , rtx rval , rtx mem , rtx model_rtx ) { rtx ( * gen ) ( rtx , rtx , rtx ) ; switch ( mode ) { case QImode : gen = gen_aarch64_load_exclusiveqi ; break ; case HImode : gen = gen_aarch64_load_exclusivehi ; break ; case SImode : gen = gen_aarch64_load_exclusivesi ; break ; case DImode : gen = gen_aarch64_load_exclusivedi ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( rval , mem , model_rtx ) ) ; } </s>


<s> bool LM32FrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ; } </s>


<s> static unsigned int ix86_minimum_incoming_stack_boundary ( bool sibcall ) { unsigned int incoming_stack_boundary ; if ( cfun -> machine -> func_type != TYPE_NORMAL ) incoming_stack_boundary = TARGET_64BIT ? 128 : MIN_STACK_BOUNDARY ; else if ( ix86_user_incoming_stack_boundary ) incoming_stack_boundary = ix86_user_incoming_stack_boundary ; else if ( ! sibcall && ix86_force_align_arg_pointer && crtl -> stack_alignment_estimated == 128 ) incoming_stack_boundary = MIN_STACK_BOUNDARY ; else incoming_stack_boundary = ix86_default_incoming_stack_boundary ; if ( incoming_stack_boundary > MIN_STACK_BOUNDARY && lookup_attribute ( ix86_force_align_arg_pointer_string , TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ) ) incoming_stack_boundary = MIN_STACK_BOUNDARY ; if ( incoming_stack_boundary < crtl -> parm_stack_boundary ) incoming_stack_boundary = crtl -> parm_stack_boundary ; if ( incoming_stack_boundary > MAIN_STACK_BOUNDARY && DECL_NAME ( current_function_decl ) && MAIN_NAME_P ( DECL_NAME ( current_function_decl ) ) && DECL_FILE_SCOPE_P ( current_function_decl ) ) incoming_stack_boundary = MAIN_STACK_BOUNDARY ; return incoming_stack_boundary ; } </s>

Return minimum incoming stack alignment .


<s> Register SparcRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return SP :: I6 ; } </s>


<s> bool BTFDebug :: InstLower ( const MachineInstr * MI , MCInst & OutMI ) { if ( MI -> getOpcode ( ) == BPF :: LD_imm64 ) { const MachineOperand & MO = MI -> getOperand ( 1 ) ; if ( MO . isGlobal ( ) ) { const GlobalValue * GVal = MO . getGlobal ( ) ; auto * GVar = dyn_cast < GlobalVariable > ( GVal ) ; if ( GVar && GVar -> hasAttribute ( BPFCoreSharedInfo :: AmaAttr ) ) { uint32_t Imm = PatchImms [ GVar -> getName ( ) . str ( ) ] ; OutMI . setOpcode ( BPF :: MOV_ri ) ; OutMI . addOperand ( MCOperand :: createReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ) ; OutMI . addOperand ( MCOperand :: createImm ( Imm ) ) ; return true ; } } } return false ; } </s>


<s> void CSKYInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCInst * NewMI = MI ; if ( NoAliases || ! printAliasInstr ( NewMI , Address , STI , O ) ) printInstruction ( NewMI , Address , STI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool MipsAsmPrinter :: isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { const MachineBasicBlock * Pred = * MBB -> pred_begin ( ) ; if ( const BasicBlock * bb = Pred -> getBasicBlock ( ) ) if ( isa < SwitchInst > ( bb -> getTerminator ( ) ) ) return false ; if ( MBB -> isLandingPad ( ) || MBB -> pred_empty ( ) ) return false ; MachineBasicBlock :: const_pred_iterator PI = MBB -> pred_begin ( ) , PI2 = PI ; ++ PI2 ; if ( PI2 != MBB -> pred_end ( ) ) return false ; if ( ! Pred -> isLayoutSuccessor ( MBB ) ) return false ; if ( Pred -> empty ( ) ) return true ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> isTerminator ( ) ) ; return ! I -> isBarrier ( ) ; } </s>

isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


<s> bool isReg ( ) const override { return Kind == OpKind :: Reg ; } </s>


<s> static int getRegClass ( RegisterKind Is , unsigned RegWidth ) { if ( Is == IS_VGPR ) { switch ( RegWidth ) { default : return - 1 ; case 1 : return AMDGPU :: VGPR_32RegClassID ; case 2 : return AMDGPU :: VReg_64RegClassID ; case 3 : return AMDGPU :: VReg_96RegClassID ; case 4 : return AMDGPU :: VReg_128RegClassID ; case 5 : return AMDGPU :: VReg_160RegClassID ; case 6 : return AMDGPU :: VReg_192RegClassID ; case 8 : return AMDGPU :: VReg_256RegClassID ; case 16 : return AMDGPU :: VReg_512RegClassID ; case 32 : return AMDGPU :: VReg_1024RegClassID ; } } else if ( Is == IS_TTMP ) { switch ( RegWidth ) { default : return - 1 ; case 1 : return AMDGPU :: TTMP_32RegClassID ; case 2 : return AMDGPU :: TTMP_64RegClassID ; case 4 : return AMDGPU :: TTMP_128RegClassID ; case 8 : return AMDGPU :: TTMP_256RegClassID ; case 16 : return AMDGPU :: TTMP_512RegClassID ; } } else if ( Is == IS_SGPR ) { switch ( RegWidth ) { default : return - 1 ; case 1 : return AMDGPU :: SGPR_32RegClassID ; case 2 : return AMDGPU :: SGPR_64RegClassID ; case 3 : return AMDGPU :: SGPR_96RegClassID ; case 4 : return AMDGPU :: SGPR_128RegClassID ; case 5 : return AMDGPU :: SGPR_160RegClassID ; case 6 : return AMDGPU :: SGPR_192RegClassID ; case 8 : return AMDGPU :: SGPR_256RegClassID ; case 16 : return AMDGPU :: SGPR_512RegClassID ; } } else if ( Is == IS_AGPR ) { switch ( RegWidth ) { default : return - 1 ; case 1 : return AMDGPU :: AGPR_32RegClassID ; case 2 : return AMDGPU :: AReg_64RegClassID ; case 3 : return AMDGPU :: AReg_96RegClassID ; case 4 : return AMDGPU :: AReg_128RegClassID ; case 5 : return AMDGPU :: AReg_160RegClassID ; case 6 : return AMDGPU :: AReg_192RegClassID ; case 8 : return AMDGPU :: AReg_256RegClassID ; case 16 : return AMDGPU :: AReg_512RegClassID ; case 32 : return AMDGPU :: AReg_1024RegClassID ; } } return - 1 ; } </s>

Given a machine instruction descriptor , returns the register class constraint for OpNum , or NULL .


<s> static int pa_reloc_rw_mask ( void ) { return 3 ; } </s>


<s> static void rs6000_option_override ( void ) { ( void ) rs6000_option_override_internal ( true ) ; } </s>

Implement TARGET_OPTION_OVERRIDE . On the RS/6000 this is used to define the target cpu type .


<s> void rs6000_emit_sISEL ( machine_mode mode ATTRIBUTE_UNUSED , rtx operands [ ] ) { rs6000_emit_int_cmove ( operands [ 0 ] , operands [ 1 ] , const1_rtx , const0_rtx ) ; } </s>


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( Size , Offset , true ) ; MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; Register AddrReg = MRI . createGenericVirtualRegister ( LLT :: pointer ( 0 , DL . getPointerSizeInBits ( 0 ) ) ) ; MIRBuilder . buildFrameIndex ( AddrReg , FI ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> unsigned MipsSEInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( ( Opc == Mips :: SW ) || ( Opc == Mips :: SD ) || ( Opc == Mips :: SWC1 ) || ( Opc == Mips :: SDC1 ) || ( Opc == Mips :: SDC164 ) ) { if ( ( MI -> getOperand ( 1 ) . isFI ( ) ) && ( MI -> getOperand ( 2 ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( 2 ) ) ) ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s>
bool
Z80AsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNum
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
int
Offset
=
0
;
if
(
ExtraCode
)
{
return
true
;
}
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNum
)
;
assert
(
MO
.
isReg
(
)
&&
"unexpected inline asm memory operand"
)
;
O
<<
Offset
<<
"("
<<
Z80InstPrinter
::
getRegisterName
(
MO
.
getReg
(
)
)
<<
")"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s>
void
X86InstrInfo
::
reMaterialize
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
unsigned
SubIdx
,
const
MachineInstr
&
Orig
,
const
TargetRegisterInfo
&
TRI
)
const
{
bool
ClobbersEFLAGS
=
Orig
.
modifiesRegister
(
X86
::
EFLAGS
,
&
TRI
)
;
if
(
ClobbersEFLAGS
&&
!
isSafeToClobberEFLAGS
(
MBB
,
I
)
)
{
int
Value
;
switch
(
Orig
.
getOpcode
(
)
)
{
case
X86
::
MOV32r0
:
Value
=
0
;
break
;
case
X86
::
MOV32r1
:
Value
=
1
;
break
;
case
X86
::
MOV32r_1
:
Value
=
1
;
break
;
default
:
llvm_unreachable
(
"Unexpected instruction!"
)
;
}
const
DebugLoc
&
DL
=
Orig
.
getDebugLoc
(
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
X86
::
MOV32ri
)
)
.
add
(
Orig
.
getOperand
(
0
)
)
.
addImm
(
Value
)
;
}
else
{
MachineInstr
*
MI
=
MBB
.
getParent
(
)
->
CloneMachineInstr
(
&
Orig
)
;
MBB
.
insert
(
I
,
MI
)
;
}
MachineInstr
&
NewMI
=
*
std
::
prev
(
I
)
;
NewMI
.
substituteRegister
(
Orig
.
getOperand
(
0
)
.
getReg
(
)
,
DestReg
,
SubIdx
,
TRI
)
;
}
</s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s> static HOST_WIDE_INT xtensa_constant_alignment ( const_tree exp , HOST_WIDE_INT align ) { if ( ( TREE_CODE ( exp ) == STRING_CST || TREE_CODE ( exp ) == CONSTRUCTOR ) && ! optimize_size ) return MAX ( align , BITS_PER_WORD ) ; return align ; } </s>

Implement TARGET_CONSTANT_ALIGNMENT . Align string constants and constructors to at least a word boundary . The typical use of this macro is to increase alignment for string constants to be word aligned so that 'strcpy ' calls that copy constants can be done inline .