<s> bool SILowerI1Copies :: runOnMachineFunction ( MachineFunction & MF ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; const TargetRegisterInfo * TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ; MachineBasicBlock :: iterator I , Next ; for ( I = MBB . begin ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; if ( MI . getOpcode ( ) == AMDGPU :: V_MOV_I1 ) { MI . setDesc ( TII -> get ( AMDGPU :: V_MOV_B32_e32 ) ) ; continue ; } if ( MI . getOpcode ( ) != AMDGPU :: COPY || ! TargetRegisterInfo :: isVirtualRegister ( MI . getOperand ( 0 ) . getReg ( ) ) || ! TargetRegisterInfo :: isVirtualRegister ( MI . getOperand ( 1 ) . getReg ( ) ) ) continue ; const TargetRegisterClass * DstRC = MRI . getRegClass ( MI . getOperand ( 0 ) . getReg ( ) ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( MI . getOperand ( 1 ) . getReg ( ) ) ; if ( DstRC == & AMDGPU :: VReg_1RegClass && TRI -> getCommonSubClass ( SrcRC , & AMDGPU :: SGPR_64RegClass ) ) { BuildMI ( MBB , & MI , MI . getDebugLoc ( ) , TII -> get ( AMDGPU :: V_CNDMASK_B32_e64 ) ) . addOperand ( MI . getOperand ( 0 ) ) . addImm ( 0 ) . addImm ( - 1 ) . addOperand ( MI . getOperand ( 1 ) ) . addImm ( 0 ) . addImm ( 0 ) . addImm ( 0 ) . addImm ( 0 ) ; MI . eraseFromParent ( ) ; } else if ( TRI -> getCommonSubClass ( DstRC , & AMDGPU :: SGPR_64RegClass ) && SrcRC == & AMDGPU :: VReg_1RegClass ) { BuildMI ( MBB , & MI , MI . getDebugLoc ( ) , TII -> get ( AMDGPU :: V_CMP_NE_I32_e64 ) ) . addOperand ( MI . getOperand ( 0 ) ) . addImm ( 0 ) . addOperand ( MI . getOperand ( 1 ) ) . addImm ( 0 ) . addImm ( 0 ) . addImm ( 0 ) . addImm ( 0 ) ; MI . eraseFromParent ( ) ; } } } return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool WebAssemblyTargetMachine :: parseMachineFunctionInfo ( const yaml :: MachineFunctionInfo & MFI , PerFunctionMIParsingState & PFS , SMDiagnostic & Error , SMRange & SourceRange ) const { const auto & YamlMFI = static_cast < const yaml :: WebAssemblyFunctionInfo & > ( MFI ) ; MachineFunction & MF = PFS . MF ; MF . getInfo < WebAssemblyFunctionInfo > ( ) -> initializeBaseYamlFields ( YamlMFI ) ; return false ; } </s>

Parse out the target 's MachineFunctionInfo from the YAML reprsentation .

WebAssembly WebAssembly WebAssembly WebAssembly


<s> bool DLXRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> void BPFAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const { if ( Fixup . getKind ( ) == FK_SecRel_4 || Fixup . getKind ( ) == FK_SecRel_8 ) { assert ( Value == 0 ) ; } else if ( Fixup . getKind ( ) == FK_Data_4 || Fixup . getKind ( ) == FK_Data_8 ) { unsigned Size = Fixup . getKind ( ) == FK_Data_4 ? 4 : 8 ; for ( unsigned i = 0 ; i != Size ; ++ i ) { unsigned Idx = IsLittleEndian ? i : Size - i - 1 ; Data [ Fixup . getOffset ( ) + Idx ] = uint8_t ( Value >> ( i * 8 ) ) ; } } else { assert ( Fixup . getKind ( ) == FK_PCRel_2 ) ; Value = ( uint16_t ) ( ( Value - 8 ) / 8 ) ; if ( IsLittleEndian ) { Data [ Fixup . getOffset ( ) + 2 ] = Value & 0xFF ; Data [ Fixup . getOffset ( ) + 3 ] = Value >> 8 ; } else { Data [ Fixup . getOffset ( ) + 2 ] = Value >> 8 ; Data [ Fixup . getOffset ( ) + 3 ] = Value & 0xFF ; } } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool arc_expand_movmem ( rtx * operands ) { rtx dst = operands [ 0 ] ; rtx src = operands [ 1 ] ; rtx dst_addr , src_addr ; HOST_WIDE_INT size ; int align = INTVAL ( operands [ 3 ] ) ; unsigned n_pieces ; int piece = align ; rtx store [ 2 ] ; rtx tmpx [ 2 ] ; int i ; if ( ! CONST_INT_P ( operands [ 2 ] ) ) return false ; size = INTVAL ( operands [ 2 ] ) ; if ( align >= 4 ) n_pieces = ( size + 2 ) / 4U + ( size & 1 ) ; else if ( align == 2 ) n_pieces = ( size + 1 ) / 2U ; else n_pieces = size ; if ( n_pieces >= ( unsigned int ) ( optimize_size ? 3 : 15 ) ) return false ; if ( piece > 4 ) piece = 4 ; dst_addr = force_offsettable ( XEXP ( operands [ 0 ] , 0 ) , size , 0 ) ; src_addr = force_offsettable ( XEXP ( operands [ 1 ] , 0 ) , size , 0 ) ; store [ 0 ] = store [ 1 ] = NULL_RTX ; tmpx [ 0 ] = tmpx [ 1 ] = NULL_RTX ; for ( i = 0 ; size > 0 ; i ^= 1 , size -= piece ) { rtx tmp ; machine_mode mode ; if ( piece > size ) piece = size & - size ; mode = smallest_mode_for_size ( piece * BITS_PER_UNIT , MODE_INT ) ; if ( 0 && tmpx [ i ] && GET_MODE ( tmpx [ i ] ) == mode ) tmp = tmpx [ i ] ; else tmpx [ i ] = tmp = gen_reg_rtx ( mode ) ; dst_addr = force_offsettable ( dst_addr , piece , 1 ) ; src_addr = force_offsettable ( src_addr , piece , 1 ) ; if ( store [ i ] ) emit_insn ( store [ i ] ) ; emit_move_insn ( tmp , change_address ( src , mode , src_addr ) ) ; store [ i ] = gen_move_insn ( change_address ( dst , mode , dst_addr ) , tmp ) ; dst_addr = plus_constant ( Pmode , dst_addr , piece ) ; src_addr = plus_constant ( Pmode , src_addr , piece ) ; } if ( store [ i ] ) emit_insn ( store [ i ] ) ; if ( store [ i ^ 1 ] ) emit_insn ( store [ i ^ 1 ] ) ; return true ; } </s>

Like move_by_pieces , but take account of load latency , and actual offset ranges . Return true on success .


<s> static bool aarch64_integer_truncation_p ( stmt_vec_info stmt_info ) { gassign * assign = dyn_cast < gassign * > ( stmt_info -> stmt ) ; if ( ! assign || ! CONVERT_EXPR_CODE_P ( gimple_assign_rhs_code ( assign ) ) ) return false ; tree lhs_type = TREE_TYPE ( gimple_assign_lhs ( assign ) ) ; tree rhs_type = TREE_TYPE ( gimple_assign_rhs1 ( assign ) ) ; return ( INTEGRAL_TYPE_P ( lhs_type ) && INTEGRAL_TYPE_P ( rhs_type ) && TYPE_PRECISION ( lhs_type ) < TYPE_PRECISION ( rhs_type ) ) ; } </s>

Return true if STMT_INFO is an integer truncation .


<s> bool HexagonInstrInfo :: areMemAccessesTriviallyDisjoint ( const MachineInstr & MIa , const MachineInstr & MIb ) const { if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) || MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; if ( MIa . mayLoad ( ) && ! isMemOp ( MIa ) && MIb . mayLoad ( ) && ! isMemOp ( MIb ) ) return true ; unsigned BasePosA , OffsetPosA ; if ( ! getBaseAndOffsetPosition ( MIa , BasePosA , OffsetPosA ) ) return false ; const MachineOperand & BaseA = MIa . getOperand ( BasePosA ) ; Register BaseRegA = BaseA . getReg ( ) ; unsigned BaseSubA = BaseA . getSubReg ( ) ; unsigned BasePosB , OffsetPosB ; if ( ! getBaseAndOffsetPosition ( MIb , BasePosB , OffsetPosB ) ) return false ; const MachineOperand & BaseB = MIb . getOperand ( BasePosB ) ; Register BaseRegB = BaseB . getReg ( ) ; unsigned BaseSubB = BaseB . getSubReg ( ) ; if ( BaseRegA != BaseRegB || BaseSubA != BaseSubB ) return false ; unsigned SizeA = getMemAccessSize ( MIa ) ; unsigned SizeB = getMemAccessSize ( MIb ) ; const MachineOperand & OffA = MIa . getOperand ( OffsetPosA ) ; const MachineOperand & OffB = MIb . getOperand ( OffsetPosB ) ; if ( ! MIa . getOperand ( OffsetPosA ) . isImm ( ) || ! MIb . getOperand ( OffsetPosB ) . isImm ( ) ) return false ; int OffsetA = isPostIncrement ( MIa ) ? 0 : OffA . getImm ( ) ; int OffsetB = isPostIncrement ( MIb ) ? 0 : OffB . getImm ( ) ; if ( OffsetA > OffsetB ) { uint64_t OffDiff = ( uint64_t ) ( ( int64_t ) OffsetA - ( int64_t ) OffsetB ) ; return SizeB <= OffDiff ; } if ( OffsetA < OffsetB ) { uint64_t OffDiff = ( uint64_t ) ( ( int64_t ) OffsetB - ( int64_t ) OffsetA ) ; return SizeA <= OffDiff ; } return false ; } </s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> static unsigned HOST_WIDE_INT compute_not_to_clear_mask ( tree arg_type , rtx arg_rtx , int regno , uint32_t * padding_bits_to_clear ) { int last_used_bit = 0 ; unsigned HOST_WIDE_INT not_to_clear_mask ; if ( RECORD_OR_UNION_TYPE_P ( arg_type ) ) { not_to_clear_mask = comp_not_to_clear_mask_str_un ( arg_type , & regno , padding_bits_to_clear , 0 , & last_used_bit ) ; if ( last_used_bit != 0 ) padding_bits_to_clear [ regno ] |= ( ( uint32_t ) - 1 ) - ( ( uint32_t ) 1 << last_used_bit ) + 1 ; else not_to_clear_mask &= ~ ( HOST_WIDE_INT_1U << regno ) ; } else { not_to_clear_mask = 0 ; if ( GET_MODE ( arg_rtx ) == BLKmode ) { int i , arg_regs ; rtx reg ; gcc_assert ( TARGET_HARD_FLOAT_ABI ) ; for ( i = 0 ; i < XVECLEN ( arg_rtx , 0 ) ; i ++ ) { reg = XEXP ( XVECEXP ( arg_rtx , 0 , i ) , 0 ) ; gcc_assert ( REG_P ( reg ) ) ; not_to_clear_mask |= HOST_WIDE_INT_1U << REGNO ( reg ) ; arg_regs = ARM_NUM_REGS ( GET_MODE ( reg ) ) ; if ( arg_regs > 1 ) { unsigned HOST_WIDE_INT mask ; mask = HOST_WIDE_INT_1U << ( REGNO ( reg ) + arg_regs ) ; mask -= HOST_WIDE_INT_1U << REGNO ( reg ) ; not_to_clear_mask |= mask ; } } } else { int arg_regs = ARM_NUM_REGS ( GET_MODE ( arg_rtx ) ) ; not_to_clear_mask |= HOST_WIDE_INT_1U << REGNO ( arg_rtx ) ; if ( arg_regs > 1 ) { unsigned HOST_WIDE_INT mask = HOST_WIDE_INT_1U << ( REGNO ( arg_rtx ) + arg_regs ) ; mask -= HOST_WIDE_INT_1U << REGNO ( arg_rtx ) ; not_to_clear_mask |= mask ; } } } return not_to_clear_mask ; } </s>

In the context of ARMv8-M Security Extensions , this function is used for both 'cmse_nonsecure_call ' and 'cmse_nonsecure_entry ' functions to compute what registers are used when returning or passing arguments , which is then returned as a mask . It will also compute a mask to indicate padding/unused bits for each of these registers , and passes this through the PADDING_BITS_TO_CLEAR pointer . The tree of the argument type is passed in ARG_TYPE , the rtl representation of the argument is passed in ARG_RTX and the starting register used to pass this argument or return value is passed in REGNO . It makes use of 'comp_not_to_clear_mask_str_un ' to compute these for struct and union types .


<s> void SparcInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << '%' << StringRef ( getRegisterName ( RegNo ) ) . lower ( ) ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"Hexagon Constant Propagation"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool check ( function_checker & c ) const override { poly_int64 outer_size = GET_MODE_SIZE ( c . arg_mode ( 0 ) ) ; poly_int64 inner_size = GET_MODE_SIZE ( c . ret_mode ( ) ) ; unsigned int nvecs = exact_div ( outer_size , inner_size ) . to_constant ( ) ; return c . require_immediate ( 1 , 0 , nvecs - 1 ) ; } </s>

Perform semantic checks on the call . Return true if the call is valid , otherwise report a suitable error .


"\n********** Patmos Function Splitter **********\n"

"\n********** Finnishing Patmos Function Splitter **********\n"


<s>
void
AArch64TargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this"
)
;
case
ISD
::
BITCAST
:
ReplaceBITCASTResults
(
N
,
Results
,
DAG
)
;
return
;
case
ISD
::
VECREDUCE_ADD
:
case
ISD
::
VECREDUCE_SMAX
:
case
ISD
::
VECREDUCE_SMIN
:
case
ISD
::
VECREDUCE_UMAX
:
case
ISD
::
VECREDUCE_UMIN
:
Results
.
push_back
(
LowerVECREDUCE
(
SDValue
(
N
,
0
)
,
DAG
)
)
;
return
;
case
AArch64ISD
::
SADDV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
ADD
,
AArch64ISD
::
SADDV
)
;
return
;
case
AArch64ISD
::
UADDV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
ADD
,
AArch64ISD
::
UADDV
)
;
return
;
case
AArch64ISD
::
SMINV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
SMIN
,
AArch64ISD
::
SMINV
)
;
return
;
case
AArch64ISD
::
UMINV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
UMIN
,
AArch64ISD
::
UMINV
)
;
return
;
case
AArch64ISD
::
SMAXV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
SMAX
,
AArch64ISD
::
SMAXV
)
;
return
;
case
AArch64ISD
::
UMAXV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
UMAX
,
AArch64ISD
::
UMAXV
)
;
return
;
case
ISD
::
FP_TO_UINT
:
case
ISD
::
FP_TO_SINT
:
assert
(
N
->
getValueType
(
0
)
==
MVT
::
i128
&&
"unexpected illegal conversion"
)
;
return
;
case
ISD
::
ATOMIC_CMP_SWAP
:
ReplaceCMP_SWAP_128Results
(
N
,
Results
,
DAG
)
;
return
;
}
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


Return appropriate code to load up a 1 , 2 , or 4 integer/floating point value .


<s> inline tree function_instance :: vector_type ( unsigned int i ) const { return acle_vector_types [ 0 ] [ type_suffix ( i ) . vector_type ] ; } </s>

Return the vector type associated with type suffix I .


<s> bool RISCVInstrInfo :: isAsCheapAsAMove ( const MachineInstr & MI ) const { const unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : break ; case RISCV :: FSGNJ_D : case RISCV :: FSGNJ_S : return MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 2 ) . isReg ( ) && MI . getOperand ( 1 ) . getReg ( ) == MI . getOperand ( 2 ) . getReg ( ) ; case RISCV :: ADDI : case RISCV :: ORI : case RISCV :: XORI : return ( MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 1 ) . getReg ( ) == RISCV :: X0 ) || ( MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) ; } return MI . isAsCheapAsAMove ( ) ; } </s>

Return true if the instruction is as cheap as a move instruction .


<s> SDNode * MBlazeDAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI . getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"SystemZ Long Branch"
;
}
</s>


<s> void XCoreTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; BSSSection = Ctx . getELFSection ( ".dp.bss" , ELF :: SHT_NOBITS , ELF :: SHF_ALLOC | ELF :: SHF_WRITE | ELF :: XCORE_SHF_DP_SECTION , SectionKind :: getBSS ( ) ) ; BSSSectionLarge = Ctx . getELFSection ( ".dp.bss.large" , ELF :: SHT_NOBITS , ELF :: SHF_ALLOC | ELF :: SHF_WRITE | ELF :: XCORE_SHF_DP_SECTION , SectionKind :: getBSS ( ) ) ; DataSection = Ctx . getELFSection ( ".dp.data" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_WRITE | ELF :: XCORE_SHF_DP_SECTION , SectionKind :: getDataRel ( ) ) ; DataSectionLarge = Ctx . getELFSection ( ".dp.data.large" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_WRITE | ELF :: XCORE_SHF_DP_SECTION , SectionKind :: getDataRel ( ) ) ; DataRelROSection = Ctx . getELFSection ( ".dp.rodata" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_WRITE | ELF :: XCORE_SHF_DP_SECTION , SectionKind :: getReadOnlyWithRel ( ) ) ; DataRelROSectionLarge = Ctx . getELFSection ( ".dp.rodata.large" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_WRITE | ELF :: XCORE_SHF_DP_SECTION , SectionKind :: getReadOnlyWithRel ( ) ) ; ReadOnlySection = Ctx . getELFSection ( ".cp.rodata" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: XCORE_SHF_CP_SECTION , SectionKind :: getReadOnlyWithRel ( ) ) ; ReadOnlySectionLarge = Ctx . getELFSection ( ".cp.rodata.large" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: XCORE_SHF_CP_SECTION , SectionKind :: getReadOnlyWithRel ( ) ) ; MergeableConst4Section = Ctx . getELFSection ( ".cp.rodata.cst4" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_MERGE | ELF :: XCORE_SHF_CP_SECTION , SectionKind :: getMergeableConst4 ( ) ) ; MergeableConst8Section = Ctx . getELFSection ( ".cp.rodata.cst8" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_MERGE | ELF :: XCORE_SHF_CP_SECTION , SectionKind :: getMergeableConst8 ( ) ) ; MergeableConst16Section = Ctx . getELFSection ( ".cp.rodata.cst16" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_MERGE | ELF :: XCORE_SHF_CP_SECTION , SectionKind :: getMergeableConst16 ( ) ) ; CStringSection = Ctx . getELFSection ( ".cp.rodata.string" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_MERGE | ELF :: SHF_STRINGS | ELF :: XCORE_SHF_CP_SECTION , SectionKind :: getReadOnlyWithRel ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s> bool IA64TargetMachine :: addPreEmitPass ( PassManagerBase & PM , bool Fast ) { PM . add ( createIA64BundlingPass ( * this ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static bool aarch64_evpc_rev_global ( struct expand_vec_perm_d * d ) { poly_uint64 nelt = d -> perm . length ( ) ; if ( ! d -> one_vector_p || d -> vec_flags != VEC_SVE_DATA ) return false ; if ( ! d -> perm . series_p ( 0 , 1 , nelt - 1 , - 1 ) ) return false ; if ( d -> testing_p ) return true ; rtx src = gen_rtx_UNSPEC ( d -> vmode , gen_rtvec ( 1 , d -> op0 ) , UNSPEC_REV ) ; emit_set_insn ( d -> target , src ) ; return true ; } </s>

Recognize patterns for the REV insn , which reverses elements within a full vector .


<s>
unsigned
HexagonInstrInfo
::
reduceLoopCount
(
MachineBasicBlock
&
MBB
,
MachineInstr
*
IndVar
,
MachineInstr
&
Cmp
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
SmallVectorImpl
<
MachineInstr
*
>
&
PrevInsts
,
unsigned
Iter
,
unsigned
MaxIter
)
const
{
assert
(
(
!
IndVar
)
&&
isEndLoopN
(
Cmp
.
getOpcode
(
)
)
&&
"Expecting a hardware loop"
)
;
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
DebugLoc
DL
=
Cmp
.
getDebugLoc
(
)
;
SmallPtrSet
<
MachineBasicBlock
*
,
8
>
VisitedBBs
;
MachineInstr
*
Loop
=
findLoopInstr
(
&
MBB
,
Cmp
.
getOpcode
(
)
,
Cmp
.
getOperand
(
0
)
.
getMBB
(
)
,
VisitedBBs
)
;
if
(
!
Loop
)
return
0
;
if
(
Loop
->
getOpcode
(
)
==
Hexagon
::
J2_loop0i
||
Loop
->
getOpcode
(
)
==
Hexagon
::
J2_loop1i
)
{
int64_t
Offset
=
Loop
->
getOperand
(
1
)
.
getImm
(
)
;
if
(
Offset
<=
1
)
Loop
->
eraseFromParent
(
)
;
else
Loop
->
getOperand
(
1
)
.
setImm
(
Offset
1
)
;
return
Offset
1
;
}
assert
(
Loop
->
getOpcode
(
)
==
Hexagon
::
J2_loop0r
&&
"Unexpected instruction"
)
;
unsigned
LoopCount
=
Loop
->
getOperand
(
1
)
.
getReg
(
)
;
unsigned
LoopEnd
=
createVR
(
MF
,
MVT
::
i1
)
;
MachineInstr
*
NewCmp
=
BuildMI
(
&
MBB
,
DL
,
get
(
Hexagon
::
C2_cmpgtui
)
,
LoopEnd
)
.
addReg
(
LoopCount
)
.
addImm
(
1
)
;
unsigned
NewLoopCount
=
createVR
(
MF
,
MVT
::
i32
)
;
MachineInstr
*
NewAdd
=
BuildMI
(
&
MBB
,
DL
,
get
(
Hexagon
::
A2_addi
)
,
NewLoopCount
)
.
addReg
(
LoopCount
)
.
addImm
(
1
)
;
const
HexagonRegisterInfo
&
HRI
=
*
Subtarget
.
getRegisterInfo
(
)
;
for
(
SmallVectorImpl
<
MachineInstr
*
>
::
iterator
I
=
PrevInsts
.
begin
(
)
,
E
=
PrevInsts
.
end
(
)
;
I
!=
E
;
++
I
)
(
*
I
)
->
substituteRegister
(
LoopCount
,
NewLoopCount
,
0
,
HRI
)
;
PrevInsts
.
clear
(
)
;
PrevInsts
.
push_back
(
NewCmp
)
;
PrevInsts
.
push_back
(
NewAdd
)
;
if
(
Iter
==
MaxIter
)
BuildMI
(
&
MBB
,
DL
,
get
(
Hexagon
::
J2_loop0r
)
)
.
addMBB
(
Loop
->
getOperand
(
0
)
.
getMBB
(
)
)
.
addReg
(
NewLoopCount
)
;
if
(
Iter
==
0
)
Loop
->
eraseFromParent
(
)
;
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
Hexagon
::
J2_jumpf
)
)
;
Cond
.
push_back
(
NewCmp
->
getOperand
(
0
)
)
;
return
NewLoopCount
;
}
</s>

Generate code to reduce the loop iteration by one and check if the loop is finished .


<s> rtx ix86_expand_adjust_ufix_to_sfix_si ( rtx val , rtx * xorp ) { REAL_VALUE_TYPE TWO31r ; rtx two31r , tmp [ 4 ] ; machine_mode mode = GET_MODE ( val ) ; machine_mode scalarmode = GET_MODE_INNER ( mode ) ; machine_mode intmode = GET_MODE_SIZE ( mode ) == 32 ? V8SImode : V4SImode ; rtx ( * cmp ) ( rtx , rtx , rtx , rtx ) ; int i ; for ( i = 0 ; i < 3 ; i ++ ) tmp [ i ] = gen_reg_rtx ( mode ) ; real_ldexp ( & TWO31r , & dconst1 , 31 ) ; two31r = const_double_from_real_value ( TWO31r , scalarmode ) ; two31r = ix86_build_const_vector ( mode , 1 , two31r ) ; two31r = force_reg ( mode , two31r ) ; switch ( mode ) { case E_V8SFmode : cmp = gen_avx_maskcmpv8sf3 ; break ; case E_V4SFmode : cmp = gen_sse_maskcmpv4sf3 ; break ; case E_V4DFmode : cmp = gen_avx_maskcmpv4df3 ; break ; case E_V2DFmode : cmp = gen_sse2_maskcmpv2df3 ; break ; default : gcc_unreachable ( ) ; } tmp [ 3 ] = gen_rtx_LE ( mode , two31r , val ) ; emit_insn ( cmp ( tmp [ 0 ] , two31r , val , tmp [ 3 ] ) ) ; tmp [ 1 ] = expand_simple_binop ( mode , AND , tmp [ 0 ] , two31r , tmp [ 1 ] , 0 , OPTAB_DIRECT ) ; if ( intmode == V4SImode || TARGET_AVX2 ) * xorp = expand_simple_binop ( intmode , ASHIFT , gen_lowpart ( intmode , tmp [ 0 ] ) , GEN_INT ( 31 ) , NULL_RTX , 0 , OPTAB_DIRECT ) ; else { rtx two31 = GEN_INT ( HOST_WIDE_INT_1U << 31 ) ; two31 = ix86_build_const_vector ( intmode , 1 , two31 ) ; * xorp = expand_simple_binop ( intmode , AND , gen_lowpart ( intmode , tmp [ 0 ] ) , two31 , NULL_RTX , 0 , OPTAB_DIRECT ) ; } return expand_simple_binop ( mode , MINUS , val , tmp [ 1 ] , tmp [ 2 ] , 0 , OPTAB_DIRECT ) ; } </s>

Adjust a V * SFmode/V * DFmode value VAL so that * sfix_trunc * resp . fix_trunc * pattern can be used on it instead of fixuns_trunc * . This is done by doing just signed conversion if < 0x1p31 , and otherwise by subtracting 0x1p31 first and xoring in 0x80000000 from * XORP afterwards .


<s>
const
MCFixupKindInfo
&
PatmosAsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
Patmos
::
NumTargetFixupKinds
]
=
{
{
"FK_Patmos_BO_7"
,
25
,
7
,
0
}
,
{
"FK_Patmos_SO_7"
,
25
,
7
,
0
}
,
{
"FK_Patmos_WO_7"
,
25
,
7
,
0
}
,
{
"FK_Patmos_abs_ALUi"
,
20
,
12
,
0
}
,
{
"FK_Patmos_abs_CFLi"
,
10
,
22
,
0
}
,
{
"FK_Patmos_abs_ALUl"
,
32
,
32
,
0
}
,
{
"FK_Patmos_stc"
,
14
,
18
,
0
}
,
{
"FK_Patmos_PCrel"
,
10
,
22
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> SDNode * Cpu0DAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = MF -> getInfo < Cpu0MachineFunctionInfo > ( ) -> getGlobalBaseReg ( ) ; return CurDAG -> getRegister ( GlobalBaseReg , getTargetLowering ( ) -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) . getNode ( ) ; } </s>


<s> static unsigned int rs6000_parm_start ( enum machine_mode mode , tree type , unsigned int nwords ) { unsigned int align ; unsigned int parm_offset ; align = function_arg_boundary ( mode , type ) / PARM_BOUNDARY - 1 ; parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6 ; return nwords + ( - ( parm_offset + nwords ) & align ) ; } </s>

For a function parm of MODE and TYPE , return the starting word in the parameter area . NWORDS of the parameter area are already used .


<s> enum aarch64_symbol_type aarch64_classify_symbol ( rtx x , rtx offset ) { if ( GET_CODE ( x ) == LABEL_REF ) { switch ( aarch64_cmodel ) { case AARCH64_CMODEL_LARGE : return SYMBOL_FORCE_TO_MEM ; case AARCH64_CMODEL_TINY_PIC : case AARCH64_CMODEL_TINY : return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL_SPIC : case AARCH64_CMODEL_SMALL_PIC : case AARCH64_CMODEL_SMALL : return SYMBOL_SMALL_ABSOLUTE ; default : gcc_unreachable ( ) ; } } if ( GET_CODE ( x ) == SYMBOL_REF ) { if ( aarch64_tls_symbol_p ( x ) ) return aarch64_classify_tls_symbol ( x ) ; switch ( aarch64_cmodel ) { case AARCH64_CMODEL_TINY : if ( ( SYMBOL_REF_WEAK ( x ) && ! aarch64_symbol_binds_local_p ( x ) ) || INTVAL ( offset ) < - 1048575 || INTVAL ( offset ) > 1048575 ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL : if ( ( SYMBOL_REF_WEAK ( x ) && ! aarch64_symbol_binds_local_p ( x ) ) || ! IN_RANGE ( INTVAL ( offset ) , HOST_WIDE_INT_C ( - 4294967263 ) , HOST_WIDE_INT_C ( 4294967264 ) ) ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_SMALL_ABSOLUTE ; case AARCH64_CMODEL_TINY_PIC : if ( ! aarch64_symbol_binds_local_p ( x ) ) return SYMBOL_TINY_GOT ; return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL_SPIC : case AARCH64_CMODEL_SMALL_PIC : if ( ! aarch64_symbol_binds_local_p ( x ) ) return ( aarch64_cmodel == AARCH64_CMODEL_SMALL_SPIC ? SYMBOL_SMALL_GOT_28K : SYMBOL_SMALL_GOT_4G ) ; return SYMBOL_SMALL_ABSOLUTE ; case AARCH64_CMODEL_LARGE : if ( CONSTANT_POOL_ADDRESS_P ( x ) ) return SYMBOL_SMALL_ABSOLUTE ; else return SYMBOL_FORCE_TO_MEM ; default : gcc_unreachable ( ) ; } } return SYMBOL_FORCE_TO_MEM ; } </s>

Return the method that should be used to access SYMBOL_REF or LABEL_REF X .


<s> virtual const MCObjectFormat & getObjectFormat ( ) const { return Format ; } </s>


<s>
BitVector
ARMBaseRegisterInfo
::
getReservedRegs
(
const
MachineFunction
&
MF
)
const
{
const
ARMSubtarget
&
STI
=
MF
.
getSubtarget
<
ARMSubtarget
>
(
)
;
const
ARMFrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
BitVector
Reserved
(
getNumRegs
(
)
)
;
markSuperRegs
(
Reserved
,
ARM
::
SP
)
;
markSuperRegs
(
Reserved
,
ARM
::
PC
)
;
markSuperRegs
(
Reserved
,
ARM
::
FPSCR
)
;
markSuperRegs
(
Reserved
,
ARM
::
APSR_NZCV
)
;
if
(
TFI
->
hasFP
(
MF
)
)
markSuperRegs
(
Reserved
,
getFramePointerReg
(
STI
)
)
;
if
(
hasBasePointer
(
MF
)
)
markSuperRegs
(
Reserved
,
BasePtr
)
;
if
(
STI
.
isR9Reserved
(
)
)
markSuperRegs
(
Reserved
,
ARM
::
R9
)
;
if
(
!
STI
.
hasD32
(
)
)
{
static_assert
(
ARM
::
D31
==
ARM
::
D16
+
15
,
"Register list not consecutive!"
)
;
for
(
unsigned
R
=
0
;
R
<
16
;
++
R
)
markSuperRegs
(
Reserved
,
ARM
::
D16
+
R
)
;
}
const
TargetRegisterClass
&
RC
=
ARM
::
GPRPairRegClass
;
for
(
unsigned
Reg
:
RC
)
for
(
MCSubRegIterator
SI
(
Reg
,
this
)
;
SI
.
isValid
(
)
;
++
SI
)
if
(
Reserved
.
test
(
*
SI
)
)
markSuperRegs
(
Reserved
,
Reg
)
;
markSuperRegs
(
Reserved
,
ARM
::
ZR
)
;
assert
(
checkAllSuperRegsMarked
(
Reserved
)
)
;
return
Reserved
;
}
</s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static void vax_file_start ( void ) { default_file_start ( ) ; } </s>

When debugging with stabs , we want to output an extra dummy label so that gas can distinguish between D_float and G_float prior to processing the .stabs directive identifying type double .


<s> char * iq2000_output_conditional_branch ( rtx_insn * insn , rtx * operands , int two_operands_p , int float_p , int inverted_p , int length ) { static char buffer [ 200 ] ; enum rtx_code code = GET_CODE ( operands [ 0 ] ) ; int need_z_p ; const char * op1 = "%z2" ; const char * op2 = ( two_operands_p ? ",%z3" : ",%." ) ; const char * comp = ( float_p ? "%F0" : "%C0" ) ; const char * inverted_comp = ( float_p ? "%W0" : "%N0" ) ; iq2000_branch_likely = ( final_sequence && INSN_ANNULLED_BRANCH_P ( insn ) ) ; if ( ! two_operands_p ) { switch ( code ) { case GTU : code = NE ; break ; case LEU : code = EQ ; break ; case GEU : code = EQ ; op1 = "%." ; break ; case LTU : code = NE ; op1 = "%." ; break ; default : break ; } } need_z_p = ( ! float_p && code != EQ && code != NE ) ; if ( need_z_p ) op2 = "" ; buffer [ 0 ] = '\0' ; switch ( length ) { case 4 : case 8 : if ( float_p ) sprintf ( buffer , "b%s%%?\t%%Z2%%1" , inverted_p ? inverted_comp : comp ) ; else sprintf ( buffer , "b%s%s%%?\t%s%s,%%1" , inverted_p ? inverted_comp : comp , need_z_p ? "z" : "" , op1 , op2 ) ; return buffer ; case 12 : case 16 : { const char * target = ( ( iq2000_branch_likely || length == 16 ) ? ".+16" : ".+12" ) ; char * c ; c = strchr ( buffer , '\0' ) ; if ( float_p ) sprintf ( c , "b%s\t%%Z2%s" , inverted_p ? comp : inverted_comp , target ) ; else sprintf ( c , "b%s%s\t%s%s,%s" , inverted_p ? comp : inverted_comp , need_z_p ? "z" : "" , op1 , op2 , target ) ; strcat ( c , "\n\tnop\n\tj\t%1" ) ; if ( length == 16 ) strcat ( buffer , "\n\tnop" ) ; return buffer ; } default : gcc_unreachable ( ) ; } return 0 ; } </s>

Output assembly instructions to perform a conditional branch . INSN is the branch instruction . OPERANDS [ 0 ] is the condition . OPERANDS [ 1 ] is the target of the branch . OPERANDS [ 2 ] is the target of the first operand to the condition . If TWO_OPERANDS_P is nonzero the comparison takes two operands ; OPERANDS [ 3 ] will be the second operand . If INVERTED_P is nonzero we are to branch if the condition does not hold . If FLOAT_P is nonzero this is a floating-point comparison . LENGTH is the length ( in bytes ) of the sequence we are to generate . That tells us whether to generate a simple conditional branch , or a reversed conditional branch around a ` jr ' instruction .


<s> bool aarch64_mov128_immediate ( rtx imm ) { if ( GET_CODE ( imm ) == CONST_INT ) return true ; gcc_assert ( CONST_WIDE_INT_NUNITS ( imm ) == 2 ) ; rtx lo = GEN_INT ( CONST_WIDE_INT_ELT ( imm , 0 ) ) ; rtx hi = GEN_INT ( CONST_WIDE_INT_ELT ( imm , 1 ) ) ; return aarch64_internal_mov_immediate ( NULL_RTX , lo , false , DImode ) + aarch64_internal_mov_immediate ( NULL_RTX , hi , false , DImode ) <= 4 ; } </s>

Return whether imm is a 128-bit immediate which is simple enough to expand inline .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


"Cannot handle this call frame pseudo instruction"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static void tilepro_asm_output_mi_thunk ( FILE * file , tree thunk_fndecl ATTRIBUTE_UNUSED , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { const char * fnname = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( thunk_fndecl ) ) ; rtx this_rtx , funexp ; rtx_insn * insn ; reload_completed = 1 ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , 1 ) ; else this_rtx = gen_rtx_REG ( Pmode , 0 ) ; emit_insn ( gen_addsi3 ( this_rtx , this_rtx , GEN_INT ( delta ) ) ) ; if ( vcall_offset ) { rtx tmp ; tmp = gen_rtx_REG ( Pmode , 29 ) ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , this_rtx ) ) ; emit_insn ( gen_addsi3 ( tmp , tmp , GEN_INT ( vcall_offset ) ) ) ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , tmp ) ) ; emit_insn ( gen_addsi3 ( this_rtx , this_rtx , tmp ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = 1 ; } funexp = XEXP ( DECL_RTL ( function ) , 0 ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx ) ) ; SIBLING_CALL_P ( insn ) = 1 ; insn = get_insns ( ) ; shorten_branches ( insn ) ; assemble_start_function ( thunk_fndecl , fnname ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; assemble_end_function ( thunk_fndecl , fnname ) ; reload_completed = 0 ; } </s>


<s> static void xstormy16_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( * cum < NUM_ARGUMENT_REGISTERS && ( * cum + XSTORMY16_WORD_SIZE ( arg . type , arg . mode ) > NUM_ARGUMENT_REGISTERS ) ) * cum = NUM_ARGUMENT_REGISTERS ; * cum += XSTORMY16_WORD_SIZE ( arg . type , arg . mode ) ; } </s>

Update CUM to advance past an argument in the argument list . The values MODE , TYPE and NAMED describe that argument . Once this is done , the variable CUM is suitable for analyzing the * following * argument with ` TARGET_FUNCTION_ARG ' , etc . This function need not do anything if the argument in question was passed on the stack . The compiler knows how to track the amount of stack space used for arguments without any special help . However , it makes life easier for xstormy16_build_va_list if it does update the word count .


<s> Relocator :: Size X86_64Relocator :: getSize ( Relocation :: Type pType ) const { return X86_64ApplyFunctions [ pType ] . size ; } </s>

Return the number of bytes in the encoding of this instruction , or zero if the encoding size can not be known from the opcode .


<s> static unsigned int mips_global_pointer ( void ) { unsigned int regno ; if ( ! TARGET_USE_GOT ) return GLOBAL_POINTER_REGNUM ; if ( mips_cfun_has_inflexible_gp_ref_p ( ) ) return GLOBAL_POINTER_REGNUM ; if ( TARGET_ABSOLUTE_JUMPS && ! mips_cfun_has_flexible_gp_ref_p ( ) ) return INVALID_REGNUM ; if ( TARGET_CALL_SAVED_GP && crtl -> is_leaf ) for ( regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( ! df_regs_ever_live_p ( regno ) && call_really_used_regs [ regno ] && ! fixed_regs [ regno ] && regno != PIC_FUNCTION_ADDR_REGNUM ) return regno ; return GLOBAL_POINTER_REGNUM ; } </s>

Return the register that should be used as the global pointer within this function . Return 0 if the function does n't need a global pointer .


<s> static inline unsigned ptr_regno_for_savres ( int sel ) { if ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) return ( sel & SAVRES_REG ) == SAVRES_FPR || ( sel & SAVRES_LR ) ? 1 : 12 ; return DEFAULT_ABI == ABI_DARWIN && ( sel & SAVRES_REG ) == SAVRES_FPR ? 1 : 11 ; } </s>

Return the register number used as a pointer by out-of-line save/restore functions .


<s> bool WebAssemblyAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { for ( uint64_t I = 0 ; I < Count ; ++ I ) OS << char ( WebAssembly :: Nop ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .

WebAssembly WebAssembly 0 WebAssembly::Nop


<s> bool ARMTargetLowering :: isUsedByReturnOnly ( SDNode * N ) const { if ( N -> getNumValues ( ) != 1 ) return false ; if ( ! N -> hasNUsesOfValue ( 1 , 0 ) ) return false ; unsigned NumCopies = 0 ; SDNode * Copies [ 2 ] ; SDNode * Use = * N -> use_begin ( ) ; if ( Use -> getOpcode ( ) == ISD :: CopyToReg ) { Copies [ NumCopies ++ ] = Use ; } else if ( Use -> getOpcode ( ) == ARMISD :: VMOVRRD ) { for ( SDNode :: use_iterator UI = Use -> use_begin ( ) , UE = Use -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != ISD :: CopyToReg ) return false ; Copies [ UI . getUse ( ) . getResNo ( ) ] = * UI ; ++ NumCopies ; } } else if ( Use -> getOpcode ( ) == ISD :: BITCAST ) { if ( ! Use -> hasNUsesOfValue ( 1 , 0 ) ) return false ; Use = * Use -> use_begin ( ) ; if ( Use -> getOpcode ( ) != ISD :: CopyToReg || ! Use -> hasNUsesOfValue ( 1 , 0 ) ) return false ; Copies [ NumCopies ++ ] = Use ; } else { return false ; } if ( NumCopies != 1 && NumCopies != 2 ) return false ; bool HasRet = false ; for ( unsigned i = 0 ; i < NumCopies ; ++ i ) { SDNode * Copy = Copies [ i ] ; for ( SDNode :: use_iterator UI = Copy -> use_begin ( ) , UE = Copy -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) == ISD :: CopyToReg ) { SDNode * Use = * UI ; if ( Use == Copies [ 0 ] || Use == Copies [ 1 ] ) continue ; return false ; } if ( UI -> getOpcode ( ) != ARMISD :: RET_FLAG ) return false ; HasRet = true ; } } return HasRet ; } </s>

Return true if result of the specified node is used by a return node only .


<s> static void sparc_conditional_register_usage ( void ) { if ( PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM ) { fixed_regs [ PIC_OFFSET_TABLE_REGNUM ] = 1 ; call_used_regs [ PIC_OFFSET_TABLE_REGNUM ] = 1 ; } if ( TARGET_ARCH32 && fixed_regs [ 5 ] ) fixed_regs [ 5 ] = 1 ; else if ( TARGET_ARCH64 && fixed_regs [ 5 ] == 2 ) fixed_regs [ 5 ] = 0 ; if ( ! TARGET_V9 ) { int regno ; for ( regno = SPARC_FIRST_V9_FP_REG ; regno <= SPARC_LAST_V9_FP_REG ; regno ++ ) fixed_regs [ regno ] = 1 ; for ( regno = SPARC_FIRST_V9_FCC_REG + 1 ; regno <= SPARC_LAST_V9_FCC_REG ; regno ++ ) fixed_regs [ regno ] = 1 ; } if ( ! TARGET_FPU ) { int regno ; for ( regno = 32 ; regno < SPARC_LAST_V9_FCC_REG ; regno ++ ) fixed_regs [ regno ] = 1 ; } if ( fixed_regs [ 2 ] == 2 ) fixed_regs [ 2 ] = ! TARGET_APP_REGS ; if ( fixed_regs [ 3 ] == 2 ) fixed_regs [ 3 ] = ! TARGET_APP_REGS ; if ( TARGET_ARCH32 && fixed_regs [ 4 ] == 2 ) fixed_regs [ 4 ] = ! TARGET_APP_REGS ; else if ( TARGET_CM_EMBMEDANY ) fixed_regs [ 4 ] = 1 ; else if ( fixed_regs [ 4 ] == 2 ) fixed_regs [ 4 ] = 0 ; if ( TARGET_FLAT ) { int regno ; memset ( sparc_leaf_regs , 0 , FIRST_PSEUDO_REGISTER ) ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) leaf_reg_remap [ regno ] = regno ; } if ( TARGET_VIS ) global_regs [ SPARC_GSR_REG ] = 1 ; } </s>

If ! TARGET_FPU , then make the fp registers and fp cc regs fixed so that they wo n't be allocated .


runOnMachineFunction - Emit the function body .


<s>
TargetLowering
::
AtomicExpansionKind
X86TargetLowering
::
shouldExpandAtomicRMWInIR
(
AtomicRMWInst
*
AI
)
const
{
unsigned
NativeWidth
=
Subtarget
->
is64Bit
(
)
64
:
32
;
Type
*
MemType
=
AI
->
getType
(
)
;
if
(
MemType
->
getPrimitiveSizeInBits
(
)
>
NativeWidth
)
{
return
needsCmpXchgNb
(
MemType
)
AtomicExpansionKind
::
CmpXChg
:
AtomicExpansionKind
::
;
}
AtomicRMWInst
::
BinOp
Op
=
AI
->
getOperation
(
)
;
switch
(
Op
)
{
default
:
llvm_unreachable
(
"Unknown atomic operation"
)
;
case
AtomicRMWInst
::
Xchg
:
case
AtomicRMWInst
::
Add
:
case
AtomicRMWInst
::
Sub
:
return
AtomicExpansionKind
::
;
case
AtomicRMWInst
::
Or
:
case
AtomicRMWInst
::
And
:
case
AtomicRMWInst
::
Xor
:
return
!
AI
->
use_empty
(
)
AtomicExpansionKind
::
CmpXChg
:
AtomicExpansionKind
::
;
case
AtomicRMWInst
::
Nand
:
case
AtomicRMWInst
::
Max
:
case
AtomicRMWInst
::
Min
:
case
AtomicRMWInst
::
UMax
:
case
AtomicRMWInst
::
UMin
:
return
AtomicExpansionKind
::
CmpXChg
;
}
}
</s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


"value of %<-mfixed-range%> must have form REG1-REG2"

Parse the -mfixed-range= option string .


<s>
unsigned
X86TTI
::
getArithmeticInstrCost
(
unsigned
Opcode
,
Type
*
Ty
)
const
{
std
::
pair
<
unsigned
,
MVT
>
LT
=
TLI
->
getTypeLegalizationCost
(
Ty
)
;
int
ISD
=
TLI
->
InstructionOpcodeToISD
(
Opcode
)
;
assert
(
ISD
&&
"Invalid opcode"
)
;
static
const
CostTblEntry
<
MVT
>
AVX1CostTable
[
]
=
{
{
ISD
::
MUL
,
MVT
::
v8i32
,
4
}
,
{
ISD
::
SUB
,
MVT
::
v8i32
,
4
}
,
{
ISD
::
ADD
,
MVT
::
v8i32
,
4
}
,
{
ISD
::
MUL
,
MVT
::
v4i64
,
4
}
,
{
ISD
::
SUB
,
MVT
::
v4i64
,
4
}
,
{
ISD
::
ADD
,
MVT
::
v4i64
,
4
}
,
}
;
if
(
ST
->
hasAVX
(
)
)
{
int
Idx
=
CostTableLookup
<
MVT
>
(
AVX1CostTable
,
array_lengthof
(
AVX1CostTable
)
,
ISD
,
LT
.
second
)
;
if
(
Idx
!=
1
)
return
LT
.
first
*
AVX1CostTable
[
Idx
]
.
Cost
;
}
return
TargetTransformInfo
::
getArithmeticInstrCost
(
Opcode
,
Ty
)
;
}
</s>

This is an approximation of reciprocal throughput of a math/logic op .


"Didn't find MI in its own basic block?"

getOffsetOf - Return the current offset of the specified machine instruction from the start of the function .


<s>
static
void
rs6000_file_start
(
void
)
{
char
buffer
[
80
]
;
const
char
*
start
=
buffer
;
FILE
*
file
=
asm_out_file
;
rs6000_default_cpu
=
TARGET_CPU_DEFAULT
;
default_file_start
(
)
;
if
(
flag_verbose_asm
)
{
sprintf
(
buffer
,
"\n%s rs6000/powerpc options:"
,
ASM_COMMENT_START
)
;
if
(
rs6000_default_cpu
!=
0
&&
rs6000_default_cpu
[
0
]
!=
'\0'
)
{
fprintf
(
file
,
"%s --with-cpu=%s"
,
start
,
rs6000_default_cpu
)
;
start
=
""
;
}
if
(
global_options_set
.
x_rs6000_cpu_index
)
{
fprintf
(
file
,
"%s -mcpu=%s"
,
start
,
processor_target_table
[
rs6000_cpu_index
]
.
name
)
;
start
=
""
;
}
if
(
global_options_set
.
x_rs6000_tune_index
)
{
fprintf
(
file
,
"%s -mtune=%s"
,
start
,
processor_target_table
[
rs6000_tune_index
]
.
name
)
;
start
=
""
;
}
if
(
PPC405_ERRATUM77
)
{
fprintf
(
file
,
"%s PPC405CR_ERRATUM77"
,
start
)
;
start
=
""
;
}
switch
(
rs6000_sdata
)
{
case
SDATA_NONE
:
fprintf
(
file
,
"%s -msdata=none"
,
start
)
;
start
=
""
;
break
;
case
SDATA_DATA
:
fprintf
(
file
,
"%s -msdata=data"
,
start
)
;
start
=
""
;
break
;
case
SDATA_SYSV
:
fprintf
(
file
,
"%s -msdata=sysv"
,
start
)
;
start
=
""
;
break
;
case
SDATA_EABI
:
fprintf
(
file
,
"%s -msdata=eabi"
,
start
)
;
start
=
""
;
break
;
}
if
(
rs6000_sdata
&&
g_switch_value
)
{
fprintf
(
file
,
"%s -G %d"
,
start
,
g_switch_value
)
;
start
=
""
;
}
if
(
*
start
==
'\0'
)
putc
(
'\n'
,
file
)
;
}
if
(
!
(
rs6000_default_cpu
&&
rs6000_default_cpu
[
0
]
)
&&
!
global_options_set
.
x_rs6000_cpu_index
)
{
fputs
(
"\t.machine "
,
asm_out_file
)
;
if
(
(
rs6000_isa_flags
&
OPTION_MASK_MODULO
)
!=
0
)
fputs
(
"power9\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_DIRECT_MOVE
)
!=
0
)
fputs
(
"power8\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_POPCNTD
)
!=
0
)
fputs
(
"power7\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_CMPB
)
!=
0
)
fputs
(
"power6\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_POPCNTB
)
!=
0
)
fputs
(
"power5\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_MFCRF
)
!=
0
)
fputs
(
"power4\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_POWERPC64
)
!=
0
)
fputs
(
"ppc64\n"
,
asm_out_file
)
;
else
fputs
(
"ppc\n"
,
asm_out_file
)
;
}
if
(
DEFAULT_ABI
==
ABI_ELFv2
)
fprintf
(
file
,
"\t.abiversion 2\n"
)
;
}
</s>

Do anything needed at the start of the asm file .


<s> static inline int mov_insn_size ( machine_mode mode , bool consider_sh2a ) { const int mode_sz = GET_MODE_SIZE ( mode ) ; if ( ( consider_sh2a && TARGET_SH2A_DOUBLE && mode == DFmode ) || ( TARGET_FMOVD && mode == DFmode ) ) return mode_sz ; else { const int max_mov_sz = GET_MODE_SIZE ( SImode ) ; return mode_sz >= max_mov_sz ? max_mov_sz : mode_sz ; } } </s>

Determine the size of the fundamental move insn that will be used for the specified mode .


<s> unsigned RV16KRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? RV16K :: X2 : RV16K :: X1 ; } </s>


<s> void check_label_emit ( ) { if ( mvs_need_base_reload ) { mvs_need_base_reload = 0 ; mvs_page_code += 4 ; fprintf ( assembler_source , "\tL\t%d,%d(,%d)\n" , BASE_REGISTER , ( mvs_page_num - function_base_page ) * 4 , PAGE_REGISTER ) ; } } </s>

Emit reload of base register if indicated . This is to eliminate multiple reloads when several labels are generated pointing to the same place in the code . The page table is written at the end of the function . The entries in the page table look like .LPGT0 : // PGT0 EQU * .long .LPG0 // DC A ( PG0 ) .long .LPG1 // DC A ( PG1 ) while the prologue generates L r4 , =A ( .LPGT0 ) Note that this paging scheme breaks down if a single subroutine has more than about 10MB of code in it ... as long as humans write code , this should n't be a problem ...


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ReserveX18 ( TT . isOSDarwin ( ) || TT . isOSWindows ( ) ) , IsLittle ( LittleEndian ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS , CPU ) ) , TSInfo ( ) , TLInfo ( TM , * this ) { CallLoweringInfo . reset ( new AArch64CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new AArch64LegalizerInfo ( * this ) ) ; auto * RBI = new AArch64RegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( createAArch64InstructionSelector ( * static_cast < const AArch64TargetMachine * > ( & TM ) , * this , * RBI ) ) ; RegBankInfo . reset ( RBI ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> static int bfin_register_move_cost ( machine_mode mode , reg_class_t class1 , reg_class_t class2 ) { if ( ( class1 == CCREGS && ! reg_class_subset_p ( class2 , DREGS ) ) || ( class2 == CCREGS && ! reg_class_subset_p ( class1 , DREGS ) ) ) return 4 ; if ( optimize_size ) return 2 ; if ( GET_MODE_CLASS ( mode ) == MODE_INT ) { if ( TEST_HARD_REG_BIT ( reg_class_contents [ class1 ] , REG_A0 ) || TEST_HARD_REG_BIT ( reg_class_contents [ class1 ] , REG_A1 ) || TEST_HARD_REG_BIT ( reg_class_contents [ class2 ] , REG_A0 ) || TEST_HARD_REG_BIT ( reg_class_contents [ class2 ] , REG_A1 ) ) return 20 ; } return 2 ; } </s>

Return the cost of moving data from a register in class CLASS1 to one in class CLASS2 . A cost of 2 is the default .


<s>
static
int
c4x_valid_operands
(
enum
rtx_code
code
,
rtx
*
operands
,
enum
machine_mode
mode
ATTRIBUTE_UNUSED
,
int
force
)
{
rtx
op0
;
rtx
op1
;
rtx
op2
;
enum
rtx_code
code1
;
enum
rtx_code
code2
;
if
(
code
==
IF_THEN_ELSE
)
return
1
||
(
operands
[
0
]
==
operands
[
2
]
||
operands
[
0
]
==
operands
[
3
]
)
;
if
(
code
==
COMPARE
)
{
op1
=
operands
[
0
]
;
op2
=
operands
[
1
]
;
}
else
{
op1
=
operands
[
1
]
;
op2
=
operands
[
2
]
;
}
op0
=
operands
[
0
]
;
if
(
GET_CODE
(
op0
)
==
SUBREG
)
op0
=
SUBREG_REG
(
op0
)
;
if
(
GET_CODE
(
op1
)
==
SUBREG
)
op1
=
SUBREG_REG
(
op1
)
;
if
(
GET_CODE
(
op2
)
==
SUBREG
)
op2
=
SUBREG_REG
(
op2
)
;
code1
=
GET_CODE
(
op1
)
;
code2
=
GET_CODE
(
op2
)
;
if
(
code1
==
REG
&&
code2
==
REG
)
return
1
;
if
(
code1
==
MEM
&&
code2
==
MEM
)
{
if
(
c4x_S_indirect
(
op1
)
&&
c4x_S_indirect
(
op2
)
)
return
1
;
return
c4x_R_indirect
(
op1
)
&&
c4x_R_indirect
(
op2
)
;
}
if
(
code1
==
code2
)
return
0
;
if
(
code1
==
REG
)
{
switch
(
code2
)
{
case
CONST_INT
:
if
(
c4x_J_constant
(
op2
)
&&
c4x_R_indirect
(
op1
)
)
return
1
;
break
;
case
CONST_DOUBLE
:
if
(
!
c4x_H_constant
(
op2
)
)
return
0
;
break
;
case
MEM
:
break
;
default
:
fatal_insn
(
"c4x_valid_operands: Internal error"
,
op2
)
;
break
;
}
if
(
GET_CODE
(
op0
)
==
SCRATCH
)
return
1
;
if
(
!
REG_P
(
op0
)
)
return
0
;
return
!
force
||
code
==
COMPARE
||
REGNO
(
op1
)
==
REGNO
(
op0
)
;
}
if
(
code
==
ASHIFTRT
||
code
==
LSHIFTRT
||
code
==
ASHIFT
||
code
==
COMPARE
)
return
code2
==
REG
&&
(
c4x_S_indirect
(
op1
)
||
c4x_R_indirect
(
op1
)
)
;
if
(
code2
==
REG
)
{
switch
(
code1
)
{
case
CONST_INT
:
break
;
case
CONST_DOUBLE
:
if
(
!
c4x_H_constant
(
op1
)
)
return
0
;
break
;
case
MEM
:
break
;
default
:
abort
(
)
;
break
;
}
if
(
GET_CODE
(
op0
)
==
SCRATCH
)
return
1
;
if
(
!
REG_P
(
op0
)
)
return
0
;
return
!
force
||
REGNO
(
op1
)
==
REGNO
(
op0
)
;
}
if
(
c4x_J_constant
(
op1
)
&&
c4x_R_indirect
(
op2
)
)
return
1
;
return
0
;
}
</s>

Validate combination of src operands . Note that the operands have been screened by the src_operand predicate . We just have to check that the combination of operands is valid . If FORCE is set , ensure that the destination regno is valid if we have a 2 operand insn .


<s> bool KudeyarAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { KudeyarFI = MF . getInfo < KudeyarMachineFunctionInfo > ( ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>


<s> bool X86TTIImpl :: isLegalMaskedExpandLoad ( Type * DataTy ) { if ( ! isa < VectorType > ( DataTy ) ) return false ; if ( ! ST -> hasAVX512 ( ) ) return false ; if ( DataTy -> getVectorNumElements ( ) == 1 ) return false ; Type * ScalarTy = DataTy -> getVectorElementType ( ) ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == 32 || IntWidth == 64 || ( ( IntWidth == 8 || IntWidth == 16 ) && ST -> hasVBMI2 ( ) ) ; } </s>

Return true if the target supports masked expand load .


<s>
bool
AArch64InstrInfo
::
shouldClusterMemOps
(
MachineInstr
&
FirstLdSt
,
unsigned
BaseReg1
,
MachineInstr
&
SecondLdSt
,
unsigned
BaseReg2
,
unsigned
NumLoads
)
const
{
if
(
BaseReg1
!=
BaseReg2
)
return
false
;
if
(
NumLoads
>
1
)
return
false
;
if
(
!
isPairableLdStInst
(
FirstLdSt
)
||
!
isPairableLdStInst
(
SecondLdSt
)
)
return
false
;
unsigned
FirstOpc
=
FirstLdSt
.
getOpcode
(
)
;
unsigned
SecondOpc
=
SecondLdSt
.
getOpcode
(
)
;
if
(
!
canPairLdStOpc
(
FirstOpc
,
SecondOpc
)
)
return
false
;
if
(
!
isCandidateToMergeOrPair
(
FirstLdSt
)
||
!
isCandidateToMergeOrPair
(
SecondLdSt
)
)
return
false
;
int64_t
Offset1
=
FirstLdSt
.
getOperand
(
2
)
.
getImm
(
)
;
if
(
isUnscaledLdSt
(
FirstOpc
)
&&
!
scaleOffset
(
FirstOpc
,
Offset1
)
)
return
false
;
int64_t
Offset2
=
SecondLdSt
.
getOperand
(
2
)
.
getImm
(
)
;
if
(
isUnscaledLdSt
(
SecondOpc
)
&&
!
scaleOffset
(
SecondOpc
,
Offset2
)
)
return
false
;
if
(
Offset1
>
63
||
Offset1
<
64
)
return
false
;
assert
(
Offset1
<=
Offset2
&&
"Caller should have ordered offsets."
)
;
return
Offset1
+
1
==
Offset2
;
}
</s>

Returns true if the two given memory operations should be scheduled adjacent .


<s> bool runOnMachineFunction ( MachineFunction & F ) { bool Changed = false ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; return Changed ; } </s>


<s> MachineBasicBlock * getMBB ( ) { return MBB ; } </s>

Return a reference to the basic block containing this bundle .


<s> void AVRTargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { SDLoc DL ( N ) ; switch ( N -> getOpcode ( ) ) { case ISD :: ADD : { if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) ) { SDValue Sub = DAG . getNode ( ISD :: SUB , DL , N -> getValueType ( 0 ) , N -> getOperand ( 0 ) , DAG . getConstant ( - C -> getAPIntValue ( ) , DL , C -> getValueType ( 0 ) ) ) ; Results . push_back ( Sub ) ; } break ; } default : { SDValue Res = LowerOperation ( SDValue ( N , 0 ) , DAG ) ; for ( unsigned I = 0 , E = Res -> getNumValues ( ) ; I != E ; ++ I ) Results . push_back ( Res . getValue ( I ) ) ; break ; } } } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> bool rx_is_legitimate_constant ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { switch ( GET_CODE ( x ) ) { case CONST : x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == PLUS ) { if ( ! CONST_INT_P ( XEXP ( x , 1 ) ) ) return false ; x = XEXP ( x , 0 ) ; gcc_assert ( ! CONST_INT_P ( x ) ) ; } switch ( GET_CODE ( x ) ) { case LABEL_REF : case SYMBOL_REF : return true ; case UNSPEC : return XINT ( x , 1 ) == UNSPEC_CONST || XINT ( x , 1 ) == UNSPEC_PID_ADDR ; default : gcc_unreachable ( ) ; } break ; case LABEL_REF : case SYMBOL_REF : return true ; case CONST_DOUBLE : return ( rx_max_constant_size == 0 || rx_max_constant_size == 4 ) ; case CONST_VECTOR : return false ; default : gcc_assert ( CONST_INT_P ( x ) ) ; break ; } return ok_for_max_constant ( INTVAL ( x ) ) ; } </s>

Returns true if X a legitimate constant for an immediate operand on the RX . X is already known to satisfy CONSTANT_P .


<s> ArrayRef < std :: pair < int , const char * >> AMDGPUInstrInfo :: getSerializableTargetIndices ( ) const { static const std :: pair < int , const char * > TargetIndices [ ] = { { AMDGPU :: TI_CONSTDATA_START , "amdgpu-constdata-start" } , { AMDGPU :: TI_SCRATCH_RSRC_DWORD0 , "amdgpu-scratch-rsrc-dword0" } , { AMDGPU :: TI_SCRATCH_RSRC_DWORD1 , "amdgpu-scratch-rsrc-dword1" } , { AMDGPU :: TI_SCRATCH_RSRC_DWORD2 , "amdgpu-scratch-rsrc-dword2" } , { AMDGPU :: TI_SCRATCH_RSRC_DWORD3 , "amdgpu-scratch-rsrc-dword3" } } ; return makeArrayRef ( TargetIndices ) ; } </s>

Return an array that contains the ids of the target indices ( used for the TargetIndex machine operand ) and their names .


<s> static rtx transcode_memory_rtx ( rtx m , rtx newbase , rtx_insn * before ) { rtx base , index , addendr ; int addend = 0 ; int need_es = 0 ; if ( ! MEM_P ( m ) ) return m ; if ( GET_MODE ( XEXP ( m , 0 ) ) == SImode ) { rtx new_m ; rtx seg = rl78_hi8 ( XEXP ( m , 0 ) ) ; if ( ! TARGET_ES0 ) { emit_insn_before ( EM ( gen_movqi ( A , seg ) ) , before ) ; emit_insn_before ( EM ( gen_movqi_to_es ( A ) ) , before ) ; } record_content ( A , NULL_RTX ) ; new_m = gen_rtx_MEM ( GET_MODE ( m ) , rl78_lo16 ( XEXP ( m , 0 ) ) ) ; MEM_COPY_ATTRIBUTES ( new_m , m ) ; m = new_m ; need_es = 1 ; } characterize_address ( XEXP ( m , 0 ) , & base , & index , & addendr ) ; gcc_assert ( index == NULL_RTX ) ; if ( base == NULL_RTX ) return m ; if ( addendr && GET_CODE ( addendr ) == CONST_INT ) addend = INTVAL ( addendr ) ; gcc_assert ( REG_P ( base ) ) ; gcc_assert ( REG_P ( newbase ) ) ; int limit = 256 - GET_MODE_SIZE ( GET_MODE ( m ) ) ; if ( REGNO ( base ) == SP_REG ) { if ( addend >= 0 && addend <= limit ) return m ; } if ( addend < 0 || ( addend > limit && REGNO ( newbase ) != BC_REG ) || ( addendr && ( GET_CODE ( addendr ) != CONST_INT ) && ( ( REGNO ( newbase ) != BC_REG ) ) ) ) { EM ( emit_insn_before ( gen_movhi ( AX , base ) , before ) ) ; EM ( emit_insn_before ( gen_addhi3 ( AX , AX , addendr ) , before ) ) ; EM ( emit_insn_before ( gen_movhi ( newbase , AX ) , before ) ) ; record_content ( AX , NULL_RTX ) ; record_content ( newbase , NULL_RTX ) ; base = newbase ; addend = 0 ; addendr = 0 ; } else { base = gen_and_emit_move ( newbase , base , before , true ) ; } if ( addend ) { record_content ( base , NULL_RTX ) ; base = gen_rtx_PLUS ( HImode , base , GEN_INT ( addend ) ) ; } else if ( addendr ) { record_content ( base , NULL_RTX ) ; base = gen_rtx_PLUS ( HImode , base , addendr ) ; } if ( need_es ) { m = change_address ( m , GET_MODE ( m ) , gen_es_addr ( base ) ) ; cfun -> machine -> uses_es = true ; } else m = change_address ( m , GET_MODE ( m ) , base ) ; return m ; } </s>

If M is MEM ( REG ) or MEM ( PLUS ( REG , INT ) ) and REG is virtual then copy it into NEWBASE and return the updated MEM . Otherwise just return M. Any needed insns are emitted before BEFORE .


<s> void MBlazeFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MBlazeFunctionInfo * MBlazeFI = MF . getInfo < MBlazeFunctionInfo > ( ) ; const MBlazeInstrInfo & TII = * static_cast < const MBlazeInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; CallingConv :: ID CallConv = MF . getFunction ( ) -> getCallingConv ( ) ; bool requiresRA = CallConv == CallingConv :: MBLAZE_INTR ; int FPOffset = MBlazeFI -> getFPStackOffset ( ) ; int RAOffset = MBlazeFI -> getRAStackOffset ( ) ; if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( MBlaze :: ADD ) , MBlaze :: R1 ) . addReg ( MBlaze :: R19 ) . addReg ( MBlaze :: R0 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( MBlaze :: LWI ) , MBlaze :: R19 ) . addReg ( MBlaze :: R1 ) . addImm ( FPOffset ) ; } if ( MFI -> adjustsStack ( ) || requiresRA ) { BuildMI ( MBB , MBBI , dl , TII . get ( MBlaze :: LWI ) , MBlaze :: R15 ) . addReg ( MBlaze :: R1 ) . addImm ( RAOffset ) ; } int StackSize = ( int ) MFI -> getStackSize ( ) ; if ( StackSize ) { BuildMI ( MBB , MBBI , dl , TII . get ( MBlaze :: ADDIK ) , MBlaze :: R1 ) . addReg ( MBlaze :: R1 ) . addImm ( StackSize ) ; } } </s>


Return an array that contains the MMO target flag values and their names .


<s> void ARMBaseRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { ARMFunctionInfo * AFI = MBB -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? ARM :: ADDri : ( AFI -> isThumb1OnlyFunction ( ) ? ARM :: tADDrSPi : ARM :: t2ADDri ) ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , 0 , this , MF ) ) ; MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ) ; if ( ! AFI -> isThumb1OnlyFunction ( ) ) AddDefaultCC ( MIB ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .

ARM ARM ARM ARM ARM::ADDri ARM::tADDrSPi ARM::t2ADDri 0


<s> unsigned PPCRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const PPCFrameLowering * TFI = getFrameLowering ( MF ) ; if ( ! TM . isPPC64 ( ) ) return TFI -> hasFP ( MF ) ? PPC :: R31 : PPC :: R1 ; else return TFI -> hasFP ( MF ) ? PPC :: X31 : PPC :: X1 ; } </s>


<s>
void
avr_output_addr_vec
(
rtx_insn
*
labl
,
rtx
table
)
{
FILE
*
stream
=
asm_out_file
;
app_disable
(
)
;
if
(
DECL_SECTION_NAME
(
current_function_decl
)
&&
symtab_node
::
get
(
current_function_decl
)
&&
!
symtab_node
::
get
(
current_function_decl
)
->
implicit_section
)
{
switch_to_section
(
current_function_section
(
)
)
;
fprintf
(
stream
,
"\t.subsection\t1\n"
)
;
}
else
{
const
char
*
sec_name
=
".jumptables.gcc"
;
tree
asm_name
=
DECL_ASSEMBLER_NAME
(
current_function_decl
)
;
const
char
*
fname
=
IDENTIFIER_POINTER
(
asm_name
)
;
fname
=
targetm
.
strip_name_encoding
(
fname
)
;
sec_name
=
ACONCAT
(
(
sec_name
,
"."
,
fname
,
)
)
;
fprintf
(
stream
,
"\t.section\t%s,\"%s\",@progbits\n"
,
sec_name
,
AVR_HAVE_JMP_CALL
"a"
:
"ax"
)
;
}
ASM_OUTPUT_ALIGN
(
stream
,
1
)
;
targetm
.
asm_out
.
internal_label
(
stream
,
"L"
,
CODE_LABEL_NUMBER
(
labl
)
)
;
int
vlen
=
XVECLEN
(
table
,
0
)
;
for
(
int
idx
=
0
;
idx
<
vlen
;
idx
++
)
{
int
value
=
CODE_LABEL_NUMBER
(
XEXP
(
XVECEXP
(
table
,
0
,
idx
)
,
0
)
)
;
if
(
AVR_HAVE_JMP_CALL
)
fprintf
(
stream
,
"\t.word gs(.L%d)\n"
,
value
)
;
else
fprintf
(
stream
,
"\trjmp .L%d\n"
,
value
)
;
}
in_section
=
;
switch_to_section
(
current_function_section
(
)
)
;
}
</s>

Emit jump tables out-of-line so that branches crossing the table get shorter offsets . If we have JUMP + CALL , then put the tables in a dedicated non-.text section so that CALLs get better chance to be relaxed to RCALLs . We emit the tables by hand because ` function_rodata_section ' does not work as expected , cf . PR71151 , and we do * NOT * want the table to be in .rodata , hence setting JUMP_TABLES_IN_TEXT_SECTION = 0 is of limited use ; and setting it to 1 attributes table lengths to branch offsets ... Moreover , fincal.c keeps switching section before each table entry which we find too fragile as to rely on section caching .


"Can't store this register to stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> TargetIRAnalysis WebAssemblyTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( const Function & F ) { return TargetTransformInfo ( WebAssemblyTTIImpl ( this , F ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


<s> int mcore_modify_comparison ( enum rtx_code code ) { rtx op1 = arch_compare_op1 ; if ( GET_CODE ( op1 ) == CONST_INT ) { int val = INTVAL ( op1 ) ; switch ( code ) { case LE : if ( CONST_OK_FOR_J ( val + 1 ) ) { arch_compare_op1 = GEN_INT ( val + 1 ) ; return 1 ; } break ; default : break ; } } return 0 ; } </s>

Check to see if a comparison against a constant can be made more efficient by incrementing/decrementing the constant to get one that is more efficient to load .


<s> bool arm_pad_arg_upward ( machine_mode mode ATTRIBUTE_UNUSED , const_tree type ) { if ( ! TARGET_AAPCS_BASED ) return DEFAULT_FUNCTION_ARG_PADDING ( mode , type ) == upward ; if ( type && BYTES_BIG_ENDIAN && INTEGRAL_TYPE_P ( type ) ) return false ; return true ; } </s>

For use by FUNCTION_ARG_PADDING ( MODE , TYPE ) . Return true if an argument passed on the stack should be padded upwards , i.e . if the least-significant byte has useful data . For legacy APCS ABIs we use the default . For AAPCS based ABIs small aggregate types are placed in the lowest memory address .


<s> bool SIRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & Fn ) const { return Fn . getFrameInfo ( ) . hasStackObjects ( ) ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> static rtx rs6000_legitimize_tls_address_aix ( rtx addr , enum tls_model model ) { rtx sym , mem , tocref , tlsreg , tmpreg , dest ; const char * name ; char * tlsname ; sym = force_const_mem ( GET_MODE ( addr ) , addr ) ; if ( constant_pool_expr_p ( XEXP ( sym , 0 ) ) && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( get_pool_constant ( XEXP ( sym , 0 ) ) , Pmode ) ) { tocref = create_TOC_reference ( XEXP ( sym , 0 ) , NULL_RTX ) ; mem = gen_const_mem ( Pmode , tocref ) ; set_mem_alias_set ( mem , get_TOC_alias_set ( ) ) ; } else return sym ; if ( model == TLS_MODEL_GLOBAL_DYNAMIC || model == TLS_MODEL_LOCAL_DYNAMIC ) { name = XSTR ( XVECEXP ( XEXP ( mem , 0 ) , 0 , 0 ) , 0 ) ; tlsname = XALLOCAVEC ( char , strlen ( name ) + 1 ) ; strcpy ( tlsname , "*LCM" ) ; strcat ( tlsname , name + 3 ) ; rtx modaddr = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( tlsname ) ) ; SYMBOL_REF_FLAGS ( modaddr ) |= SYMBOL_FLAG_LOCAL ; tocref = create_TOC_reference ( modaddr , NULL_RTX ) ; rtx modmem = gen_const_mem ( Pmode , tocref ) ; set_mem_alias_set ( modmem , get_TOC_alias_set ( ) ) ; rtx modreg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( modreg , modmem ) ) ; tmpreg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( tmpreg , mem ) ) ; dest = gen_reg_rtx ( Pmode ) ; if ( TARGET_32BIT ) emit_insn ( gen_tls_get_addrsi ( dest , modreg , tmpreg ) ) ; else emit_insn ( gen_tls_get_addrdi ( dest , modreg , tmpreg ) ) ; return dest ; } else if ( TARGET_32BIT ) { tlsreg = gen_reg_rtx ( SImode ) ; emit_insn ( gen_tls_get_tpointer ( tlsreg ) ) ; } else { tlsreg = gen_rtx_REG ( DImode , 13 ) ; xcoff_tls_exec_model_detected = true ; } tmpreg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( tmpreg , mem ) ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , gen_rtx_MINUS ( Pmode , addr , tlsreg ) ) ; dest = force_reg ( Pmode , gen_rtx_PLUS ( Pmode , tmpreg , tlsreg ) ) ; return dest ; } </s>


"Could not generate addis value for fusion"

Emit the addis instruction that will be part of a fused instruction sequence .


<s> static rtx pru_function_arg ( cumulative_args_t cum_v , const function_arg_info & arg ) { rtx return_rtx = NULL_RTX ; int regi = pru_function_arg_regi ( cum_v , arg . mode , arg . type , arg . named ) ; if ( regi >= 0 ) return_rtx = gen_rtx_REG ( arg . mode , regi ) ; return return_rtx ; } </s>

Define where to put the arguments to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . ARG is a description of the argument .


<s>
static
void
rs6000_output_savres_externs
(
FILE
*
file
)
{
rs6000_stack_t
*
info
=
rs6000_stack_info
(
)
;
if
(
TARGET_DEBUG_STACK
)
debug_stack_info
(
info
)
;
if
(
info
->
first_fp_reg_save
<
64
&&
!
TARGET_MACHO
&&
!
TARGET_ELF
)
{
char
*
name
;
int
regno
=
info
->
first_fp_reg_save
32
;
if
(
(
info
->
savres_strategy
&
SAVE_INLINE_FPRS
)
==
0
)
{
bool
lr
=
(
info
->
savres_strategy
&
SAVE_NOINLINE_FPRS_SAVES_LR
)
!=
0
;
int
sel
=
SAVRES_SAVE
|
SAVRES_FPR
|
(
lr
SAVRES_LR
:
0
)
;
name
=
rs6000_savres_routine_name
(
regno
,
sel
)
;
fprintf
(
file
,
"\t.extern %s\n"
,
name
)
;
}
if
(
(
info
->
savres_strategy
&
REST_INLINE_FPRS
)
==
0
)
{
bool
lr
=
(
info
->
savres_strategy
&
REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
)
==
0
;
int
sel
=
SAVRES_FPR
|
(
lr
SAVRES_LR
:
0
)
;
name
=
rs6000_savres_routine_name
(
regno
,
sel
)
;
fprintf
(
file
,
"\t.extern %s\n"
,
name
)
;
}
}
}
</s>

Output .extern statements for the save/restore routines we use .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Darwin PPC Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> SMLoc getStartLoc ( ) const { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> void OutgoingValueHandler :: assignValueToReg ( Register ValVReg , const CCValAssign & VA , const EVT & VT ) { Register PhysReg = VA . getLocReg ( ) ; const MipsSubtarget & STI = static_cast < const MipsSubtarget & > ( MIRBuilder . getMF ( ) . getSubtarget ( ) ) ; if ( VT == MVT :: f64 && PhysReg >= Mips :: A0 && PhysReg <= Mips :: A3 ) { MIRBuilder . buildInstr ( STI . isFP64bit ( ) ? Mips :: ExtractElementF64_64 : Mips :: ExtractElementF64 ) . addDef ( PhysReg + ( STI . isLittle ( ) ? 1 : 0 ) ) . addUse ( ValVReg ) . addImm ( 1 ) . constrainAllUses ( MIRBuilder . getTII ( ) , * STI . getRegisterInfo ( ) , * STI . getRegBankInfo ( ) ) ; MIRBuilder . buildInstr ( STI . isFP64bit ( ) ? Mips :: ExtractElementF64_64 : Mips :: ExtractElementF64 ) . addDef ( PhysReg + ( STI . isLittle ( ) ? 0 : 1 ) ) . addUse ( ValVReg ) . addImm ( 0 ) . constrainAllUses ( MIRBuilder . getTII ( ) , * STI . getRegisterInfo ( ) , * STI . getRegBankInfo ( ) ) ; } else if ( VT == MVT :: f32 && PhysReg >= Mips :: A0 && PhysReg <= Mips :: A3 ) { MIRBuilder . buildInstr ( Mips :: MFC1 ) . addDef ( PhysReg ) . addUse ( ValVReg ) . constrainAllUses ( MIRBuilder . getTII ( ) , * STI . getRegisterInfo ( ) , * STI . getRegBankInfo ( ) ) ; } else { Register ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildCopy ( PhysReg , ExtReg ) ; MIB . addUse ( PhysReg , RegState :: Implicit ) ; } } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> const char * MSP430TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return NULL ; case MSP430ISD :: RET_FLAG : return "MSP430ISD::RET_FLAG" ; case MSP430ISD :: RRA : return "MSP430ISD::RRA" ; case MSP430ISD :: RLA : return "MSP430ISD::RLA" ; case MSP430ISD :: RRC : return "MSP430ISD::RRC" ; case MSP430ISD :: CALL : return "MSP430ISD::CALL" ; case MSP430ISD :: Wrapper : return "MSP430ISD::Wrapper" ; case MSP430ISD :: BR_CC : return "MSP430ISD::BR_CC" ; case MSP430ISD :: CMP : return "MSP430ISD::CMP" ; case MSP430ISD :: SELECT_CC : return "MSP430ISD::SELECT_CC" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s>
unsigned
LanaiTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
,
SelectionDAG
&
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"pc"
,
Lanai
::
PC
)
.
Case
(
"sp"
,
Lanai
::
SP
)
.
Case
(
"fp"
,
Lanai
::
FP
)
.
Case
(
"rr1"
,
Lanai
::
RR1
)
.
Case
(
"r10"
,
Lanai
::
R10
)
.
Case
(
"rr2"
,
Lanai
::
RR2
)
.
Case
(
"r11"
,
Lanai
::
R11
)
.
Case
(
"rca"
,
Lanai
::
RCA
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> void ix86_expand_vector_init ( bool mmx_ok , rtx target , rtx vals ) { machine_mode mode = GET_MODE ( target ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; int n_elts = GET_MODE_NUNITS ( mode ) ; int n_var = 0 , one_var = - 1 ; bool all_same = true , all_const_zero = true ; int i ; rtx x ; if ( n_elts != XVECLEN ( vals , 0 ) ) { rtx subtarget = target ; x = XVECEXP ( vals , 0 , 0 ) ; gcc_assert ( GET_MODE_INNER ( GET_MODE ( x ) ) == inner_mode ) ; if ( GET_MODE_NUNITS ( GET_MODE ( x ) ) * 2 == n_elts ) { rtx ops [ 2 ] = { XVECEXP ( vals , 0 , 0 ) , XVECEXP ( vals , 0 , 1 ) } ; if ( inner_mode == QImode || inner_mode == HImode || inner_mode == TImode || inner_mode == HFmode ) { unsigned int n_bits = n_elts * GET_MODE_SIZE ( inner_mode ) ; scalar_mode elt_mode = inner_mode == TImode ? DImode : SImode ; n_bits /= GET_MODE_SIZE ( elt_mode ) ; mode = mode_for_vector ( elt_mode , n_bits ) . require ( ) ; inner_mode = mode_for_vector ( elt_mode , n_bits / 2 ) . require ( ) ; ops [ 0 ] = gen_lowpart ( inner_mode , ops [ 0 ] ) ; ops [ 1 ] = gen_lowpart ( inner_mode , ops [ 1 ] ) ; subtarget = gen_reg_rtx ( mode ) ; } ix86_expand_vector_init_concat ( mode , subtarget , ops , 2 ) ; if ( subtarget != target ) emit_move_insn ( target , gen_lowpart ( GET_MODE ( target ) , subtarget ) ) ; return ; } gcc_unreachable ( ) ; } for ( i = 0 ; i < n_elts ; ++ i ) { x = XVECEXP ( vals , 0 , i ) ; if ( ! ( CONST_SCALAR_INT_P ( x ) || CONST_DOUBLE_P ( x ) || CONST_FIXED_P ( x ) ) ) n_var ++ , one_var = i ; else if ( x != CONST0_RTX ( inner_mode ) ) all_const_zero = false ; if ( i > 0 && ! rtx_equal_p ( x , XVECEXP ( vals , 0 , 0 ) ) ) all_same = false ; } if ( n_var == 0 ) { emit_move_insn ( target , gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , 0 ) ) ) ; return ; } if ( all_same && ix86_expand_vector_init_duplicate ( mmx_ok , mode , target , XVECEXP ( vals , 0 , 0 ) ) ) return ; if ( n_var == 1 ) { if ( all_const_zero && ix86_expand_vector_init_one_nonzero ( mmx_ok , mode , target , XVECEXP ( vals , 0 , one_var ) , one_var ) ) return ; if ( ix86_expand_vector_init_one_var ( mmx_ok , mode , target , vals , one_var ) ) return ; } ix86_expand_vector_init_general ( mmx_ok , mode , target , vals ) ; } </s>

Initialize vector TARGET via VALS . Suppress the use of MMX instructions unless MMX_OK is true .


<s> static void mips_sim_init ( struct mips_sim * state , state_t dfa_state ) { state -> issue_rate = mips_issue_rate ( ) ; state -> dfa_state = dfa_state ; mips_sim_reset ( state ) ; } </s>

Initialize STATE before its first use . DFA_STATE points to an allocated but uninitialized DFA state .


<s> static bool tilepro_frame_pointer_required ( void ) { return crtl -> calls_eh_return || cfun -> calls_alloca ; } </s>


"missing architecture name in 'arch' target %s"

"unknown value %qs for 'arch' target %s"

"invalid feature modifier %qs for 'arch' target %s"

Handle the ARCH_STR argument to the arch= target attribute . PRAGMA_OR_ATTR is used in potential error messages .


<s> bool rx_is_restricted_memory_address ( rtx mem , machine_mode mode ) { if ( ! rx_is_legitimate_address ( mode , mem , reload_in_progress || reload_completed ) ) return false ; switch ( GET_CODE ( mem ) ) { case REG : return true ; case PRE_DEC : case POST_INC : return false ; case PLUS : { rtx base , index ; base = XEXP ( mem , 0 ) ; index = XEXP ( mem , 1 ) ; if ( ! RX_REG_P ( base ) || ! CONST_INT_P ( index ) ) return false ; return IN_RANGE ( INTVAL ( index ) , 0 , ( 0x10000 * GET_MODE_SIZE ( mode ) ) - 1 ) ; } case SYMBOL_REF : return true ; default : gcc_unreachable ( ) ; } } </s>

Returns TRUE for simple memory addreses , ie ones that do not involve register indirect addressing or pre/post increment/decrement .


<s> virtual bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const LLVM_OVERRIDE { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> bool pru_regno_ok_for_base_p ( int regno , bool strict_p ) { if ( ! HARD_REGISTER_NUM_P ( regno ) && ! strict_p ) return true ; return ( GP_REG_P ( regno ) || regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) ; } </s>

Return true if register REGNO is a valid base register . STRICT_P is true if REG_OK_STRICT is in effect .


<s> bool rs6000_emit_int_cmove ( rtx dest , rtx op , rtx true_cond , rtx false_cond ) { rtx condition_rtx , cr ; machine_mode mode = GET_MODE ( dest ) ; enum rtx_code cond_code ; rtx ( * isel_func ) ( rtx , rtx , rtx , rtx , rtx ) ; bool signedp ; if ( mode != SImode && ( ! TARGET_POWERPC64 || mode != DImode ) ) return false ; if ( GET_MODE_CLASS ( GET_MODE ( XEXP ( op , 0 ) ) ) == MODE_CC ) return false ; condition_rtx = rs6000_generate_compare ( op , mode ) ; cond_code = GET_CODE ( condition_rtx ) ; cr = XEXP ( condition_rtx , 0 ) ; signedp = GET_MODE ( cr ) == CCmode ; isel_func = ( mode == SImode ? ( signedp ? gen_isel_cc_si : gen_isel_ccuns_si ) : ( signedp ? gen_isel_cc_di : gen_isel_ccuns_di ) ) ; switch ( cond_code ) { case LT : case GT : case LTU : case GTU : case EQ : break ; default : { std :: swap ( false_cond , true_cond ) ; PUT_CODE ( condition_rtx , reverse_condition ( cond_code ) ) ; } break ; } false_cond = force_reg ( mode , false_cond ) ; if ( true_cond != const0_rtx ) true_cond = force_reg ( mode , true_cond ) ; emit_insn ( isel_func ( dest , condition_rtx , true_cond , false_cond , cr ) ) ; return true ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < PMLImport > ( ) ; AU . setPreservesAll ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> inline tree function_instance :: tuple_type ( unsigned int i ) const { unsigned int num_vectors = vectors_per_tuple ( ) ; return acle_vector_types [ num_vectors - 1 ] [ type_suffix ( i ) . vector_type ] ; } </s>

If the function operates on tuples of vectors , return the tuple type associated with type suffix I , otherwise return the vector type associated with type suffix I .


<s> bool RISCVFrameLowering :: canUseAsEpilogue ( const MachineBasicBlock & MBB ) const { MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ; const auto * RVFI = MBB . getParent ( ) -> getInfo < RISCVMachineFunctionInfo > ( ) ; if ( ! RVFI -> useSaveRestoreLibCalls ( ) ) return true ; if ( MBB . succ_size ( ) > 1 ) return false ; MachineBasicBlock * SuccMBB = MBB . succ_empty ( ) ? TmpMBB -> getFallThrough ( ) : * MBB . succ_begin ( ) ; if ( ! SuccMBB ) return true ; return SuccMBB -> isReturnBlock ( ) && SuccMBB -> size ( ) == 1 ; } </s>

Check whether or not the given MBB can be used as a epilogue for the target .


"MMIX Internal: %s is not a shiftable integer"

Print the presumed shiftable wyde argument shifted into place ( to be output with an operand ) .


<s> static bool sh_cannot_copy_insn_p ( rtx_insn * insn ) { if ( ! reload_completed || ! flag_pic ) return false ; if ( ! NONJUMP_INSN_P ( insn ) ) return false ; if ( asm_noperands ( insn ) >= 0 ) return false ; rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == CLOBBER || GET_CODE ( pat ) == USE ) return false ; if ( TARGET_FDPIC && GET_CODE ( pat ) == PARALLEL ) { rtx t = XVECEXP ( pat , 0 , XVECLEN ( pat , 0 ) - 1 ) ; if ( GET_CODE ( t ) == USE && unspec_caller_rtx_p ( XEXP ( t , 0 ) ) ) return true ; } if ( GET_CODE ( pat ) != SET ) return false ; pat = SET_SRC ( pat ) ; if ( unspec_caller_rtx_p ( pat ) ) return true ; return false ; } </s>

Indicate that INSN can not be duplicated . This is true for insn that generates a unique label .


<s> void expand_prologue ( ) { tree func_attr ; int size ; int regno ; rtx scratch ; if ( reload_completed != 1 ) abort ( ) ; size = get_frame_size ( ) ; create_regs_rtx ( ) ; func_attr = TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ; current_function_interrupt = lookup_attribute ( "interrupt" , func_attr ) != NULL_TREE ; current_function_trap = lookup_attribute ( "trap" , func_attr ) != NULL_TREE ; if ( current_function_args_info . nregs == 2 ) scratch = iy_reg ; else scratch = ix_reg ; if ( current_function_interrupt ) { emit_move_after_reload ( stack_push_word , m68hc11_soft_tmp_reg , scratch ) ; emit_move_after_reload ( stack_push_word , gen_rtx ( REG , HImode , SOFT_Z_REGNUM ) , scratch ) ; emit_move_after_reload ( stack_push_word , gen_rtx ( REG , HImode , SOFT_SAVED_XY_REGNUM ) , scratch ) ; } if ( frame_pointer_needed ) emit_move_after_reload ( stack_push_word , hard_frame_pointer_rtx , scratch ) ; if ( TARGET_M6812 && ( size > 4 || size == 3 ) ) { emit_insn ( gen_addhi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - size ) ) ) ; } else if ( size > 8 ) { rtx insn ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , gen_rtx_SET ( VOIDmode , stack_pointer_rtx , gen_rtx_PLUS ( HImode , stack_pointer_rtx , GEN_INT ( - size ) ) ) , gen_rtx_CLOBBER ( VOIDmode , scratch ) ) ) ; emit_insn ( insn ) ; } else { int i ; for ( i = 2 ; i <= size ; i += 2 ) emit_move_after_reload ( stack_push_word , ix_reg , 0 ) ; if ( size & 1 ) emit_insn ( gen_addhi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - 1 ) ) ) ; } if ( frame_pointer_needed ) emit_move_after_reload ( hard_frame_pointer_rtx , stack_pointer_rtx , scratch ) ; for ( regno = SOFT_REG_FIRST ; regno <= SOFT_REG_LAST ; regno ++ ) { if ( regs_ever_live [ regno ] && ! call_used_regs [ regno ] ) { emit_move_after_reload ( stack_push_word , gen_rtx ( REG , HImode , regno ) , scratch ) ; } } } </s>


<s> bool Z80oldTargetLowering :: IsEligibleForTailCallOptimization ( SDValue Callee , CallingConv :: ID CalleeCC , bool isVarArg , Type * RetTy , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SmallVectorImpl < ISD :: InputArg > & Ins , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function & CallerF = MF . getFunction ( ) ; CallingConv :: ID CallerCC = CallerF . getCallingConv ( ) ; if ( CalleeCC != CallingConv :: C || CallerCC != CallingConv :: C ) { return false ; } LLVMContext & C = * DAG . getContext ( ) ; if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , RetCC_Z80old_C , RetCC_Z80old_C ) ) { return false ; } if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , 16 > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , getCCAssignFn ( CalleeCC ) ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; for ( unsigned i = 0 , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; ISD :: ArgFlagsTy Flags = Outs [ i ] . Flags ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) { return false ; } if ( VA . isMemLoc ( ) && ! MatchingStackOffset ( Arg , VA . getLocMemOffset ( ) , Flags , MFI , MRI , TII ) ) { return false ; } } } } return true ; } </s>

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization .


<s> const MCExpr * getSubExpr ( ) const { return SubExpr ; } </s>

getSubExpr - Get the child of this expression .


<s> MachineBasicBlock * SITargetLowering :: EmitInstrWithCustomInserter ( MachineInstr * MI , MachineBasicBlock * BB ) const { MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; MachineBasicBlock :: iterator I = MI ; switch ( MI -> getOpcode ( ) ) { default : return AMDGPUTargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; case AMDGPU :: BRANCH : return BB ; case AMDGPU :: SI_WQM : LowerSI_WQM ( MI , * BB , I , MRI ) ; break ; } return BB ; } </s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> const RISCVRegisterInfo * getRegisterInfo ( ) const override { return & RegInfo ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static rtx frv_ifcvt_rewrite_mem ( rtx mem , machine_mode mode , rtx insn ) { rtx addr = XEXP ( mem , 0 ) ; if ( ! frv_legitimate_address_p_1 ( mode , addr , reload_completed , TRUE , FALSE ) ) { if ( GET_CODE ( addr ) == PLUS ) { rtx addr_op0 = XEXP ( addr , 0 ) ; rtx addr_op1 = XEXP ( addr , 1 ) ; if ( GET_CODE ( addr_op0 ) == REG && CONSTANT_P ( addr_op1 ) ) { rtx reg = frv_ifcvt_load_value ( addr_op1 , insn ) ; if ( ! reg ) return NULL_RTX ; addr = gen_rtx_PLUS ( Pmode , addr_op0 , reg ) ; } else return NULL_RTX ; } else if ( CONSTANT_P ( addr ) ) addr = frv_ifcvt_load_value ( addr , insn ) ; else return NULL_RTX ; if ( addr == NULL_RTX ) return NULL_RTX ; else if ( XEXP ( mem , 0 ) != addr ) return change_address ( mem , mode , addr ) ; } return mem ; } </s>

Update a MEM used in conditional code that might contain an offset to put the offset into a scratch register , so that the conditional load/store operations can be used . This function returns the original pointer if the MEM is valid to use in conditional code , NULL if we ca n't load up the offset into a temporary register , or the new MEM if we were successful .


<s> bool Cpu0PassConfig :: addInstSelector ( ) { addPass ( createCpu0SEISelDAG ( getCpu0TargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static int get_csky_barrier_cost ( rtx_insn * insn ) { int base_cost = 50 ; rtx next = next_nonnote_insn ( insn ) ; if ( next != NULL && GET_CODE ( next ) == CODE_LABEL ) base_cost -= 20 ; switch ( GET_CODE ( insn ) ) { case CODE_LABEL : return 50 ; case INSN : case CALL_INSN : return base_cost ; case JUMP_INSN : return base_cost - 10 ; default : return base_cost + 10 ; } } </s>

Return the cost of forcibly inserting a barrier after INSN .


<s>
void
R600SchedStrategy
::
releaseBottomNode
(
SUnit
*
SU
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Bottom Releasing "
;
DAG
->
dumpNode
(
*
SU
)
)
;
if
(
isPhysicalRegCopy
(
SU
->
getInstr
(
)
)
)
{
PhysicalRegCopy
.
push_back
(
SU
)
;
return
;
}
int
IK
=
getInstKind
(
SU
)
;
if
(
IK
==
IDOther
)
Available
[
IDOther
]
.
push_back
(
SU
)
;
else
Pending
[
IK
]
.
push_back
(
SU
)
;
}
</s>

Currently only scheduling top-down , so this method is empty .


<s> static unsigned findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const TargetRegisterInfo & TRI , bool Is64Bit ) { const MachineFunction * MF = MBB . getParent ( ) ; const Function * F = MF -> getFunction ( ) ; if ( ! F || MF -> getMMI ( ) . callsEHReturn ( ) ) return 0 ; static const uint16_t CallerSavedRegs32Bit [ ] = { X86 :: EAX , X86 :: EDX , X86 :: ECX , 0 } ; static const uint16_t CallerSavedRegs64Bit [ ] = { X86 :: RAX , X86 :: RDX , X86 :: RCX , X86 :: RSI , X86 :: RDI , X86 :: R8 , X86 :: R9 , X86 :: R10 , X86 :: R11 , 0 } ; unsigned Opc = MBBI -> getOpcode ( ) ; switch ( Opc ) { default : return 0 ; case X86 :: RET : case X86 :: RETI : case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: NACL_CG_TCRETURNdi64 : case X86 :: NACL_CG_TCRETURNri64 : case X86 :: TCRETURNmi64 : case X86 :: EH_RETURN : case X86 :: EH_RETURN64 : { SmallSet < uint16_t , 8 > Uses ; for ( unsigned i = 0 , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , & TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } const uint16_t * CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit ; for ( ; * CS ; ++ CS ) if ( ! Uses . count ( * CS ) ) return * CS ; } } return 0 ; } </s>

findDeadCallerSavedReg - Return a caller-saved register that is n't live when it reaches the `` return '' instruction .


<s> hashval_t toc_hasher :: hash ( toc_hash_struct * thc ) { return rs6000_hash_constant ( thc -> key ) ^ thc -> key_mode ; } </s>

Hash function for builtin functions with up to 3 arguments and a return type .


<s> bool MipsFastISel :: fastLowerCall ( CallLoweringInfo & CLI ) { if ( ! TargetSupported ) return false ; CallingConv :: ID CC = CLI . CallConv ; bool IsTailCall = CLI . IsTailCall ; bool IsVarArg = CLI . IsVarArg ; const Value * Callee = CLI . Callee ; MCSymbol * Symbol = CLI . Symbol ; if ( CC == CallingConv :: Fast ) return false ; if ( IsTailCall ) return false ; if ( IsVarArg ) return false ; MVT RetVT ; if ( CLI . RetTy -> isVoidTy ( ) ) RetVT = MVT :: isVoid ; else if ( ! isTypeSupported ( CLI . RetTy , RetVT ) ) return false ; for ( auto Flag : CLI . OutFlags ) if ( Flag . isInReg ( ) || Flag . isSRet ( ) || Flag . isNest ( ) || Flag . isByVal ( ) ) return false ; SmallVector < MVT , 16 > OutVTs ; OutVTs . reserve ( CLI . OutVals . size ( ) ) ; for ( auto * Val : CLI . OutVals ) { MVT VT ; if ( ! isTypeLegal ( Val -> getType ( ) , VT ) && ! ( VT == MVT :: i1 || VT == MVT :: i8 || VT == MVT :: i16 ) ) return false ; if ( VT . isVector ( ) || VT . getSizeInBits ( ) > 64 ) return false ; OutVTs . push_back ( VT ) ; } Address Addr ; if ( ! computeCallAddress ( Callee , Addr ) ) return false ; unsigned NumBytes ; if ( ! processCallArgs ( CLI , OutVTs , NumBytes ) ) return false ; if ( ! Addr . getGlobalValue ( ) ) return false ; unsigned DestAddress ; if ( Symbol ) DestAddress = materializeExternalCallSym ( Symbol ) ; else DestAddress = materializeGV ( Addr . getGlobalValue ( ) , MVT :: i32 ) ; emitInst ( TargetOpcode :: COPY , Mips :: T9 ) . addReg ( DestAddress ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Mips :: JALR ) , Mips :: RA ) . addReg ( Mips :: T9 ) ; for ( auto Reg : CLI . OutRegs ) MIB . addReg ( Reg , RegState :: Implicit ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( * FuncInfo . MF , CC ) ) ; CLI . Call = MIB ; return finishCall ( CLI , RetVT , NumBytes ) ; } </s>

This method is called by target-independent code to do target- specific call lowering .


"Invalid number of NOP bytes requested!"

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> rtx sfunc_uses_reg ( rtx insn ) { int i ; rtx pattern , part , reg_part , reg ; if ( GET_CODE ( insn ) != INSN ) return 0 ; pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) != PARALLEL || get_attr_type ( insn ) != TYPE_SFUNC ) return 0 ; for ( reg_part = 0 , i = XVECLEN ( pattern , 0 ) - 1 ; i >= 1 ; i -- ) { part = XVECEXP ( pattern , 0 , i ) ; if ( GET_CODE ( part ) == USE && GET_MODE ( XEXP ( part , 0 ) ) == SImode ) reg_part = part ; } if ( ! reg_part ) return 0 ; reg = XEXP ( reg_part , 0 ) ; for ( i = XVECLEN ( pattern , 0 ) - 1 ; i >= 0 ; i -- ) { part = XVECEXP ( pattern , 0 , i ) ; if ( part == reg_part || GET_CODE ( part ) == CLOBBER ) continue ; if ( reg_mentioned_p ( reg , ( ( GET_CODE ( part ) == SET && GET_CODE ( SET_DEST ( part ) ) == REG ) ? SET_SRC ( part ) : part ) ) ) return 0 ; } return reg ; } </s>

If the instruction INSN is implemented by a special function , and we can positively find the register that is used to call the sfunc , and this register is not used anywhere else in this instruction - except as the destination of a set , return this register ; else , return 0 .


<s>
void
mmix_asm_output_addr_diff_elt
(
FILE
*
stream
,
rtx
body
ATTRIBUTE_UNUSED
,
int
value
,
int
rel
)
{
fprintf
(
stream
,
"\tTETRA L%d-L%d\n"
,
value
,
rel
)
;
}
</s>


"\t%@ Function supports interworking.\n"

"\t%@ Fast Interrupt Service Routine.\n"

"\t%@ Naked Function: prologue and epilogue provided by programmer.\n"

"\t%@ Volatile: function does not return.\n"

"\t%@ Nested: function declared inside another function.\n"

"\t%@ Stack Align: May be called with mis-aligned SP.\n"

"\t%@ args = %d, pretend = %d, frame = %wd\n"

"\t%@ frame_needed = %d, uses_anonymous_args = %d\n"

Place some comments into the assembler stream describing the current function .


<s> StackOffset R600FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const R600RegisterInfo * RI = MF . getSubtarget < R600Subtarget > ( ) . getRegisterInfo ( ) ; FrameReg = RI -> getFrameRegister ( MF ) ; unsigned OffsetBytes = 2 * ( getStackWidth ( MF ) * 4 ) ; int UpperBound = FI == - 1 ? MFI . getNumObjects ( ) : FI ; for ( int i = MFI . getObjectIndexBegin ( ) ; i < UpperBound ; ++ i ) { OffsetBytes = alignTo ( OffsetBytes , MFI . getObjectAlign ( i ) ) ; OffsetBytes += MFI . getObjectSize ( i ) ; OffsetBytes = alignTo ( OffsetBytes , Align ( 4 ) ) ; } if ( FI != - 1 ) OffsetBytes = alignTo ( OffsetBytes , MFI . getObjectAlign ( FI ) ) ; return StackOffset :: getFixed ( OffsetBytes / ( getStackWidth ( MF ) * 4 ) ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s>
void
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
)
const
override
{
unsigned
Size
=
1
<<
getFixupKindLog2Size
(
Fixup
.
getKind
(
)
)
;
assert
(
Fixup
.
getOffset
(
)
+
Size
<=
DataSize
&&
"Invalid fixup offset!"
)
;
assert
(
isIntN
(
Size
*
8
+
1
,
Value
)
&&
"Value does not fit in the Fixup field"
)
;
for
(
unsigned
i
=
0
;
i
!=
Size
;
++
i
)
Data
[
Fixup
.
getOffset
(
)
+
i
]
=
uint8_t
(
Value
>>
(
i
*
8
)
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static rtx_code_label * add_constant ( rtx x , machine_mode mode , rtx last_value ) { int i ; rtx_code_label * lab , * new_rtx ; label_ref_list_t ref , newref ; for ( i = 0 ; i < pool_size ; i ++ ) { if ( x -> code == pool_vector [ i ] . value -> code && mode == pool_vector [ i ] . mode ) { if ( x -> code == CODE_LABEL ) { if ( XINT ( x , 3 ) != XINT ( pool_vector [ i ] . value , 3 ) ) continue ; } if ( rtx_equal_p ( x , pool_vector [ i ] . value ) ) { lab = new_rtx = 0 ; if ( ! last_value || ! i || ! rtx_equal_p ( last_value , pool_vector [ i - 1 ] . value ) ) { new_rtx = gen_label_rtx ( ) ; LABEL_REFS ( new_rtx ) = pool_vector [ i ] . label ; pool_vector [ i ] . label = lab = new_rtx ; } if ( lab && pool_window_label ) { newref = label_ref_list_d_pool . allocate ( ) ; newref -> label = pool_window_label ; ref = pool_vector [ pool_window_last ] . wend ; newref -> next = ref ; pool_vector [ pool_window_last ] . wend = newref ; } if ( new_rtx ) pool_window_label = new_rtx ; pool_window_last = i ; return lab ; } } } pool_vector [ pool_size ] . value = x ; if ( last_value && rtx_equal_p ( last_value , pool_vector [ pool_size - 1 ] . value ) ) { lab = 0 ; pool_vector [ pool_size - 1 ] . part_of_sequence_p = true ; } else lab = gen_label_rtx ( ) ; pool_vector [ pool_size ] . mode = mode ; pool_vector [ pool_size ] . label = lab ; pool_vector [ pool_size ] . wend = NULL ; pool_vector [ pool_size ] . part_of_sequence_p = ( lab == 0 ) ; if ( lab && pool_window_label ) { newref = label_ref_list_d_pool . allocate ( ) ; newref -> label = pool_window_label ; ref = pool_vector [ pool_window_last ] . wend ; newref -> next = ref ; pool_vector [ pool_window_last ] . wend = newref ; } if ( lab ) pool_window_label = lab ; pool_window_last = pool_size ; pool_size ++ ; return lab ; } </s>

Add a constant to the pool and return its label .


<s> void mips_d_register_target_info ( void ) { const struct d_target_info_spec handlers [ ] = { { "floatAbi" , mips_d_handle_target_float_abi } , { NULL , NULL } , } ; d_add_target_info_handlers ( handlers ) ; } </s>


<s> bool MipsInstrInfo :: HasLoadDelaySlot ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { case Mips :: LB : case Mips :: LBu : case Mips :: LH : case Mips :: LHu : case Mips :: LW : case Mips :: LWR : case Mips :: LWL : return true ; default : return false ; } } </s>

Predicate to determine if an instruction has a load delay slot .

Mips Mips Mips::LB Mips::LBu Mips::LH Mips::LHu Mips::LW Mips::LWR Mips::LWL


<s>
SDValue
LM32TargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_LM32
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
LM32ISD
::
RetFlag
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


"Cannot load this register from a stack slot!"

Load the specified register of the given register class from the specified stack frame index .


<s> bool HexagonAsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , AsmToken ID , OperandVector & Operands ) { getLexer ( ) . UnLex ( ID ) ; return parseInstruction ( Operands ) ; } </s>

ParseInstruction - Parse one assembly instruction .


<s> static rtx frv_expand_voidbinop_builtin ( enum insn_code icode , tree call ) { rtx pat ; rtx op0 = frv_read_argument ( call , 0 ) ; rtx op1 = frv_read_argument ( call , 1 ) ; machine_mode mode0 = insn_data [ icode ] . operand [ 0 ] . mode ; rtx addr ; if ( GET_CODE ( op0 ) != MEM ) { rtx reg = op0 ; if ( ! offsettable_address_p ( 0 , mode0 , op0 ) ) { reg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , reg , op0 ) ) ; } op0 = gen_rtx_MEM ( SImode , reg ) ; } addr = XEXP ( op0 , 0 ) ; if ( ! offsettable_address_p ( 0 , mode0 , addr ) ) addr = copy_to_mode_reg ( Pmode , op0 ) ; op0 = change_address ( op0 , V4SImode , addr ) ; op1 = frv_legitimize_argument ( icode , 1 , op1 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return 0 ; } </s>

Expand builtins that take two operands , the first operand being a pointer to ints and return void .


<s> bool X86TTIImpl :: isLegalNTStore ( Type * DataType , llvm :: Align Alignment ) { unsigned DataSize = DL . getTypeStoreSize ( DataType ) ; if ( ST -> hasSSE4A ( ) && ( DataType -> isFloatTy ( ) || DataType -> isDoubleTy ( ) ) ) return true ; if ( Alignment < DataSize || DataSize < 4 || DataSize > 32 || ! isPowerOf2_32 ( DataSize ) ) return false ; if ( DataSize == 32 ) return ST -> hasAVX ( ) ; else if ( DataSize == 16 ) return ST -> hasSSE1 ( ) ; return true ; } </s>

Return true if the target supports nontemporal store .


<s> bool alpha_emit_setcc ( rtx operands [ ] , machine_mode cmp_mode ) { enum rtx_code cmp_code ; enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; rtx op0 = operands [ 2 ] , op1 = operands [ 3 ] ; rtx tmp ; if ( cmp_mode == TFmode ) { op0 = alpha_emit_xfloating_compare ( & code , op0 , op1 ) ; op1 = const0_rtx ; cmp_mode = DImode ; } if ( cmp_mode == DFmode && ! TARGET_FIX ) return 0 ; cmp_code = UNKNOWN ; switch ( code ) { case EQ : case LE : case LT : case LEU : case LTU : case UNORDERED : if ( cmp_mode == DFmode ) cmp_code = code , code = NE ; break ; case NE : if ( cmp_mode == DImode && op1 == const0_rtx ) break ; case ORDERED : cmp_code = reverse_condition ( code ) ; code = EQ ; break ; case GE : case GT : case GEU : case GTU : if ( cmp_mode == DImode && op1 == const0_rtx ) break ; code = swap_condition ( code ) ; if ( cmp_mode == DFmode ) cmp_code = code , code = NE ; std :: swap ( op0 , op1 ) ; break ; default : gcc_unreachable ( ) ; } if ( cmp_mode == DImode ) { if ( ! register_operand ( op0 , DImode ) ) op0 = force_reg ( DImode , op0 ) ; if ( ! reg_or_8bit_operand ( op1 , DImode ) ) op1 = force_reg ( DImode , op1 ) ; } if ( cmp_code != UNKNOWN ) { tmp = gen_reg_rtx ( cmp_mode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , gen_rtx_fmt_ee ( cmp_code , cmp_mode , op0 , op1 ) ) ) ; op0 = cmp_mode != DImode ? gen_lowpart ( DImode , tmp ) : tmp ; op1 = const0_rtx ; } emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , gen_rtx_fmt_ee ( code , DImode , op0 , op1 ) ) ) ; return true ; } </s>

Certain simplifications can be done to make invalid setcc operations valid . Return the final comparison , or NULL if we ca n't work .


<s> Triple :: ObjectFormatType getFormat ( ) const override { return Triple :: ObjectFormatType :: ELF ; } </s>


<s> static void aarch64_autovectorize_vector_sizes ( vector_sizes * sizes ) { if ( TARGET_SVE ) sizes -> safe_push ( BYTES_PER_SVE_VECTOR ) ; sizes -> safe_push ( 16 ) ; sizes -> safe_push ( 8 ) ; } </s>

Return a list of possible vector sizes for the vectorizer to iterate over .


<s> virtual const uint16_t * getCalleeSavedRegs ( const MachineFunction * MF = 0 ) const { static const uint16_t CalleeSavedRegs [ ] = { 0 } ; return CalleeSavedRegs ; } </s>


<s> virtual bool addPassesToEmitMC ( PassManagerBase & , MCContext * & , raw_ostream & , bool = true ) { return true ; } </s>

Add passes to the specified pass manager to get machine code emitted with the MCJIT .


Called via walk_stores . DATA points to a hash table we can use to establish a unique SYMBOL_REF for each counter , which corresponds to a caller-callee pair . X is a store which we want to examine for an UNSPEC_PROF , which would be an address loaded into a register , or directly used in a MEM . If we found an UNSPEC_PROF , if we encounter a new counter the first time , write out a description and a data allocation for a 32 bit counter . Also , fill in the appropriate symbol_ref into each UNSPEC_PROF instance .


<s> static void c6x_gen_bundles ( void ) { basic_block bb ; rtx_insn * insn , * next , * last_call ; FOR_EACH_BB_FN ( bb , cfun ) { rtx_insn * insn , * next ; rtx_insn * slot [ 15 ] ; int n_filled = 0 ; int first_slot = 0 ; for ( insn = BB_HEAD ( bb ) ; ; insn = next ) { int at_end ; rtx delete_this = NULL_RTX ; if ( NONDEBUG_INSN_P ( insn ) ) { if ( CALL_P ( insn ) ) { first_slot ++ ; if ( n_filled ) { memmove ( & slot [ 1 ] , & slot [ 0 ] , n_filled * sizeof ( slot [ 0 ] ) ) ; } if ( ! shadow_p ( insn ) ) { PUT_MODE ( insn , TImode ) ; if ( n_filled ) PUT_MODE ( slot [ 1 ] , VOIDmode ) ; } n_filled ++ ; slot [ 0 ] = insn ; } else { slot [ n_filled ++ ] = insn ; } } next = NEXT_INSN ( insn ) ; while ( next && insn != BB_END ( bb ) && ! ( NONDEBUG_INSN_P ( next ) && GET_CODE ( PATTERN ( next ) ) != USE && GET_CODE ( PATTERN ( next ) ) != CLOBBER ) ) { insn = next ; next = NEXT_INSN ( insn ) ; } at_end = insn == BB_END ( bb ) ; if ( delete_this == NULL_RTX && ( at_end || ( GET_MODE ( next ) == TImode && ! ( shadow_p ( next ) && CALL_P ( next ) ) ) ) ) { if ( n_filled >= 2 ) gen_one_bundle ( slot , n_filled , first_slot ) ; n_filled = 0 ; first_slot = 0 ; } if ( at_end ) break ; } } last_call = NULL ; for ( insn = get_insns ( ) ; insn ; insn = next ) { next = NEXT_INSN ( insn ) ; if ( CALL_P ( insn ) || ( INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == SEQUENCE && CALL_P ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) ) ) ) last_call = insn ; if ( ! NOTE_P ( insn ) || NOTE_KIND ( insn ) != NOTE_INSN_CALL_ARG_LOCATION ) continue ; if ( NEXT_INSN ( last_call ) == insn ) continue ; SET_NEXT_INSN ( PREV_INSN ( insn ) ) = NEXT_INSN ( insn ) ; SET_PREV_INSN ( NEXT_INSN ( insn ) ) = PREV_INSN ( insn ) ; SET_PREV_INSN ( insn ) = last_call ; SET_NEXT_INSN ( insn ) = NEXT_INSN ( last_call ) ; SET_PREV_INSN ( NEXT_INSN ( insn ) ) = insn ; SET_NEXT_INSN ( PREV_INSN ( insn ) ) = insn ; last_call = insn ; } } </s>

Move all parallel instructions into SEQUENCEs , so that no subsequent passes try to insert labels in the middle .


<s> const X86Subtarget & getSubtarget ( ) const { return * Subtarget ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


<s> SDValue AMDGPUTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , SDLoc DL , SelectionDAG & DAG ) const { return DAG . getNode ( AMDGPUISD :: RET_FLAG , DL , MVT :: Other , Chain ) ; } </s>