<s> static M680x0RelType getType ( unsigned Kind , MCSymbolRefExpr :: VariantKind & Modifier , bool & IsPCRel ) { switch ( Kind ) { default : llvm_unreachable ( "Unimplemented" ) ; case FK_Data_4 : case FK_PCRel_4 : return RT_32 ; case FK_PCRel_2 : case FK_Data_2 : return RT_16 ; case FK_PCRel_1 : case FK_Data_1 : return RT_8 ; } } </s>

Overload to return most specific vector type .


<s> virtual const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> const TargetRegisterClass * M68kRegisterInfo :: intRegClass ( unsigned size ) const { return & M68k :: DR32RegClass ; } </s>


<s> bool runOnModule ( Module & M ) override { WorkList . clear ( ) ; if ( skipModule ( M ) ) return false ; bool Changed = false ; ValueReplacer Replacer ; DIBuilder DIB ( M , false ) ; for ( auto & F : M . functions ( ) ) { for ( auto & BB : F ) { for ( auto & I : BB ) { if ( AllocaInst * AI = dyn_cast < AllocaInst > ( & I ) ) { const PointerType * T = AI -> getType ( ) ; unsigned AS = llvm :: isTpcVectorType ( T -> getElementType ( ) ) ? 2 : 1 ; Constant * Init = UndefValue :: get ( T -> getElementType ( ) ) ; StringRef ainame = AI -> getName ( ) ; StringRef cutname = ainame ; std :: string ss = ainame . str ( ) ; size_t posa = ss . find ( "." ) ; if ( posa != std :: string :: npos ) { ss = ss . substr ( 0 , posa ) ; cutname = StringRef ( ss ) ; } auto * GV = new GlobalVariable ( M , T -> getElementType ( ) , false , GlobalValue :: PrivateLinkage , Init , ainame , nullptr , GlobalValue :: NotThreadLocal , AS ) ; Replacer . replace ( AI , GV ) ; Changed = true ; } } } } return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> bool MLxExpansion :: runOnMachineFunction ( MachineFunction & Fn ) { if ( skipFunction ( * Fn . getFunction ( ) ) ) return false ; TII = static_cast < const ARMBaseInstrInfo * > ( Fn . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; const ARMSubtarget * STI = & Fn . getSubtarget < ARMSubtarget > ( ) ; if ( ! STI -> expandMLx ( ) ) return false ; isLikeA9 = STI -> isLikeA9 ( ) || STI -> isSwift ( ) ; isSwift = STI -> isSwift ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : Fn ) Modified |= ExpandFPMLxInstructions ( MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool UPTInstrInfo :: isAsCheapAsAMove ( const MachineInstr & MI ) const { return MI . isAsCheapAsAMove ( ) ; } </s>

Return true if the instruction is as cheap as a move instruction .


<s> void MOSPassConfig :: addIRPasses ( ) { addPass ( createMOSNoRecursePass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> bool X86TargetLowering :: isUsedByReturnOnly ( SDNode * N , SDValue & Chain ) const { if ( N -> getNumValues ( ) != 1 ) return false ; if ( ! N -> hasNUsesOfValue ( 1 , 0 ) ) return false ; SDValue TCChain = Chain ; SDNode * Copy = * N -> use_begin ( ) ; if ( Copy -> getOpcode ( ) == ISD :: CopyToReg ) { if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - 1 ) . getValueType ( ) == MVT :: Glue ) return false ; TCChain = Copy -> getOperand ( 0 ) ; } else if ( Copy -> getOpcode ( ) != ISD :: FP_EXTEND ) return false ; bool HasRet = false ; for ( SDNode :: use_iterator UI = Copy -> use_begin ( ) , UE = Copy -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != X86ISD :: RET_FLAG ) return false ; HasRet = true ; } if ( ! HasRet ) return false ; Chain = TCChain ; return true ; } </s>

Return true if result of the specified node is used by a return node only .


<s>
const
char
*
WebAssemblyAsmPrinter
::
toString
(
MVT
VT
)
const
{
switch
(
VT
.
SimpleTy
)
{
default
:
break
;
case
MVT
::
f32
:
return
"f32"
;
case
MVT
::
f64
:
return
"f64"
;
case
MVT
::
i32
:
return
"i32"
;
case
MVT
::
i64
:
return
"i64"
;
}
DEBUG
(
dbgs
(
)
<<
"Invalid type "
<<
EVT
(
VT
)
.
getEVTString
(
)
<<
'\n'
)
;
llvm_unreachable
(
"invalid type"
)
;
return
"<invalid>"
;
}
</s>

Convert to a decimal representation in a string .


<s>
bool
AArch64FrameLowering
::
restoreCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
;
SmallVector
<
RegPairInfo
,
8
>
RegPairs
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
bool
NeedShadowCallStackProlog
=
false
;
computeCalleeSaveRegisterPairs
(
MF
,
CSI
,
TRI
,
RegPairs
,
NeedShadowCallStackProlog
)
;
auto
EmitMI
=
[
&
]
(
const
RegPairInfo
&
RPI
)
{
unsigned
Reg1
=
RPI
.
Reg1
;
unsigned
Reg2
=
RPI
.
Reg2
;
unsigned
LdrOpc
;
if
(
RPI
.
IsGPR
)
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPXi
:
AArch64
::
LDRXui
;
else
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPDi
:
AArch64
::
LDRDui
;
LLVM_DEBUG
(
dbgs
(
)
<<
"CSR restore: ("
<<
printReg
(
Reg1
,
TRI
)
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
printReg
(
Reg2
,
TRI
)
;
dbgs
(
)
<<
") -> fi#("
<<
RPI
.
FrameIdx
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
RPI
.
FrameIdx
+
1
;
dbgs
(
)
<<
")\n"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
LdrOpc
)
)
;
if
(
RPI
.
isPaired
(
)
)
{
MIB
.
addReg
(
Reg2
,
getDefRegState
(
true
)
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
+
1
)
,
MachineMemOperand
::
MOLoad
,
8
,
8
)
)
;
}
MIB
.
addReg
(
Reg1
,
getDefRegState
(
true
)
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
RPI
.
Offset
)
.
setMIFlag
(
MachineInstr
::
FrameDestroy
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
)
,
MachineMemOperand
::
MOLoad
,
8
,
8
)
)
;
}
;
if
(
ReverseCSRRestoreSeq
)
for
(
const
RegPairInfo
&
RPI
:
reverse
(
RegPairs
)
)
EmitMI
(
RPI
)
;
else
for
(
const
RegPairInfo
&
RPI
:
RegPairs
)
EmitMI
(
RPI
)
;
if
(
NeedShadowCallStackProlog
)
{
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AArch64
::
LDRXpre
)
)
.
addReg
(
AArch64
::
X18
,
RegState
::
Define
)
.
addReg
(
AArch64
::
LR
,
RegState
::
Define
)
.
addReg
(
AArch64
::
X18
)
.
addImm
(
8
)
.
setMIFlag
(
MachineInstr
::
FrameDestroy
)
;
}
return
true
;
}
</s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> unsigned SIInstrInfo :: getAddressSpaceForPseudoSourceKind ( unsigned Kind ) const { switch ( Kind ) { case PseudoSourceValue :: Stack : case PseudoSourceValue :: FixedStack : return ST . getAMDGPUAS ( ) . PRIVATE_ADDRESS ; case PseudoSourceValue :: ConstantPool : case PseudoSourceValue :: GOT : case PseudoSourceValue :: JumpTable : case PseudoSourceValue :: GlobalValueCallEntry : case PseudoSourceValue :: ExternalSymbolCallEntry : case PseudoSourceValue :: TargetCustom : return ST . getAMDGPUAS ( ) . CONSTANT_ADDRESS ; } return ST . getAMDGPUAS ( ) . FLAT_ADDRESS ; } </s>

getAddressSpaceForPseudoSourceKind - Given the kind of memory ( e.g .


<s> inline tree function_instance :: displacement_vector_type ( ) const { return acle_vector_types [ 0 ] [ mode_suffix ( ) . displacement_vector_type ] ; } </s>

Return the type of the function 's vector index or offset argument , or null if does n't have a vector index or offset argument .


<s> unsigned PPCRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const PPCFrameLowering * TFI = getFrameLowering ( MF ) ; const unsigned DefaultSafety = 1 ; switch ( RC -> getID ( ) ) { default : return 0 ; case PPC :: G8RC_NOX0RegClassID : case PPC :: GPRC_NOR0RegClassID : case PPC :: SPERCRegClassID : case PPC :: G8RCRegClassID : case PPC :: GPRCRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 32 - FP - DefaultSafety ; } case PPC :: F8RCRegClassID : case PPC :: F4RCRegClassID : case PPC :: VRRCRegClassID : case PPC :: VFRCRegClassID : case PPC :: VSLRCRegClassID : return 32 - DefaultSafety ; case PPC :: VSRCRegClassID : case PPC :: VSFRCRegClassID : case PPC :: VSSRCRegClassID : return 64 - DefaultSafety ; case PPC :: CRRCRegClassID : return 8 - DefaultSafety ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> virtual const TargetSubtargetInfo * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> void mt_expand_eh_return ( rtx * operands ) { if ( GET_CODE ( operands [ 0 ] ) != REG || REGNO ( operands [ 0 ] ) != EH_RETURN_STACKADJ_REGNO ) { rtx sp = EH_RETURN_STACKADJ_RTX ; emit_move_insn ( sp , operands [ 0 ] ) ; operands [ 0 ] = sp ; } emit_insn ( gen_eh_epilogue ( operands [ 0 ] ) ) ; } </s>

Generate code for the `` eh_return '' pattern .


<s> SDValue AArch64TargetLowering :: getAddr ( NodeTy * N , SelectionDAG & DAG , unsigned Flags ) const { LLVM_DEBUG ( dbgs ( ) << "AArch64TargetLowering::getAddr\n" ) ; SDLoc DL ( N ) ; EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Hi = getTargetNode ( N , Ty , DAG , AArch64II :: MO_PAGE | Flags ) ; SDValue Lo = getTargetNode ( N , Ty , DAG , AArch64II :: MO_PAGEOFF | AArch64II :: MO_NC | Flags ) ; SDValue ADRP = DAG . getNode ( AArch64ISD :: ADRP , DL , Ty , Hi ) ; return DAG . getNode ( AArch64ISD :: ADDlow , DL , Ty , ADRP , Lo ) ; } </s>

Return the address accessed by this recipe .


<s> unsigned TPCSchedStrategy :: getRegPressure ( SUnit * SU , const TargetRegisterClass * RC ) { unsigned res = 0 ; const llvm :: MachineFunction & MF = * SU -> getInstr ( ) -> getParent ( ) -> getParent ( ) ; const TargetRegisterInfo & TRI = * MF . getSubtarget ( ) . getRegisterInfo ( ) ; const RegPressureTracker & TopRPTracker = DAG -> getTopRPTracker ( ) ; RegPressureTracker & RPTracker = const_cast < RegPressureTracker & > ( TopRPTracker ) ; const int * rcps = TRI . getRegClassPressureSets ( RC ) ; std :: vector < unsigned > pressure ; std :: vector < unsigned > MaxPressure ; RPTracker . getDownwardPressure ( SU -> getInstr ( ) , pressure , MaxPressure ) ; int j = 0 ; while ( rcps [ j ] >= 0 ) { if ( res < pressure [ rcps [ j ] ] ) res = pressure [ rcps [ j ] ] ; j ++ ; } if ( RC == & TPC :: ADRFRegClass ) { res += liveInsADRF ; } return res ; } </s>

Get register pressure for the entire scheduling region before scheduling .


<s> int mmix_local_regno ( int regno ) { return regno <= MMIX_LAST_STACK_REGISTER_REGNUM && ! call_used_regs [ regno ] ; } </s>

LOCAL_REGNO . All registers that are part of the register stack and that will be saved are local .


<s>
void
Cpu0InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
=
0
,
ZeroReg
=
0
;
if
(
Cpu0
::
CPURegsRegClass
.
contains
(
DestReg
)
)
{
if
(
Cpu0
::
CPURegsRegClass
.
contains
(
SrcReg
)
)
Opc
=
Cpu0
::
ADD
,
ZeroReg
=
Cpu0
::
ZERO
;
else
if
(
SrcReg
==
Cpu0
::
HI
)
Opc
=
Cpu0
::
MFHI
,
SrcReg
=
0
;
else
if
(
SrcReg
==
Cpu0
::
LO
)
Opc
=
Cpu0
::
MFLO
,
SrcReg
=
0
;
else
if
(
SrcReg
==
Cpu0
::
SW
)
Opc
=
Cpu0
::
ADD
,
ZeroReg
=
Cpu0
::
ZERO
;
}
else
if
(
Cpu0
::
CPURegsRegClass
.
contains
(
SrcReg
)
)
{
if
(
DestReg
==
Cpu0
::
HI
)
Opc
=
Cpu0
::
MTHI
,
DestReg
=
0
;
else
if
(
DestReg
==
Cpu0
::
LO
)
Opc
=
Cpu0
::
MTLO
,
DestReg
=
0
;
else
if
(
DestReg
==
Cpu0
::
SW
)
Opc
=
Cpu0
::
CMP
,
ZeroReg
=
Cpu0
::
ZERO
;
}
assert
(
Opc
&&
"Cannot copy registers"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
)
;
if
(
DestReg
)
MIB
.
addReg
(
DestReg
,
RegState
::
Define
)
;
if
(
ZeroReg
)
MIB
.
addReg
(
ZeroReg
)
;
if
(
SrcReg
)
MIB
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> const DataLayout * getDataLayout ( ) const { return & DL ; } </s>


<s> static void riscv_conditional_register_usage ( void ) { if ( TARGET_RVE ) { for ( int r = 16 ; r <= 31 ; r ++ ) fixed_regs [ r ] = 1 ; } if ( riscv_abi == ABI_ILP32E ) { for ( int r = 16 ; r <= 31 ; r ++ ) call_used_regs [ r ] = 1 ; } if ( ! TARGET_HARD_FLOAT ) { for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) fixed_regs [ regno ] = call_used_regs [ regno ] = 1 ; } if ( UNITS_PER_FP_ARG == 0 ) { for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) call_used_regs [ regno ] = 1 ; } if ( ! TARGET_VECTOR ) { for ( int regno = V_REG_FIRST ; regno <= V_REG_LAST ; regno ++ ) fixed_regs [ regno ] = call_used_regs [ regno ] = 1 ; fixed_regs [ VTYPE_REGNUM ] = call_used_regs [ VTYPE_REGNUM ] = 1 ; fixed_regs [ VL_REGNUM ] = call_used_regs [ VL_REGNUM ] = 1 ; } } </s>


<s> SDNode * PPCDAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * TM . getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = BB -> getParent ( ) -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc dl = DebugLoc :: getUnknownLoc ( ) ; if ( PPCLowering . getPointerTy ( ) == MVT :: i32 ) { GlobalBaseReg = RegInfo -> createVirtualRegister ( PPC :: GPRCRegisterClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) , PPC :: LR ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( PPC :: G8RCRegisterClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR8 ) , PPC :: LR8 ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR8 ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , PPCLowering . getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


Add the named attribute to a class and its vtable and rtti .


<s> unsigned SparcInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == SP :: LDri || MI -> getOpcode ( ) == SP :: LDXri || MI -> getOpcode ( ) == SP :: LDFri || MI -> getOpcode ( ) == SP :: LDDFri || MI -> getOpcode ( ) == SP :: LDQFri ) { if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> Clone ( FeatureBitset FeatureMask , Function * OrigF , Function * NewF ) : FeatureMask ( FeatureMask ) , OrigF ( OrigF ) , NewF ( NewF ) { } </s>

Clone - Creates a clone of the specified SUnit .


<s>
SDValue
AAPTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
isVarArg
,
Ins
,
DL
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .

AAP
AAP
ISD::InputArg
"Unsupported calling convention"


<s> static void sparc64_initialize_trampoline ( rtx m_tramp , rtx fnaddr , rtx cxt ) { emit_move_insn ( adjust_address ( m_tramp , SImode , 0 ) , GEN_INT ( trunc_int_for_mode ( 0x83414000 , SImode ) ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , 4 ) , GEN_INT ( trunc_int_for_mode ( 0xca586018 , SImode ) ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , 8 ) , GEN_INT ( trunc_int_for_mode ( 0x81c14000 , SImode ) ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , 12 ) , GEN_INT ( trunc_int_for_mode ( 0xca586010 , SImode ) ) ) ; emit_move_insn ( adjust_address ( m_tramp , DImode , 16 ) , cxt ) ; emit_move_insn ( adjust_address ( m_tramp , DImode , 24 ) , fnaddr ) ; emit_insn ( gen_flushdi ( validize_mem ( adjust_address ( m_tramp , DImode , 0 ) ) ) ) ; if ( sparc_cpu != PROCESSOR_ULTRASPARC && sparc_cpu != PROCESSOR_ULTRASPARC3 && sparc_cpu != PROCESSOR_NIAGARA && sparc_cpu != PROCESSOR_NIAGARA2 && sparc_cpu != PROCESSOR_NIAGARA3 && sparc_cpu != PROCESSOR_NIAGARA4 ) emit_insn ( gen_flushdi ( validize_mem ( adjust_address ( m_tramp , DImode , 8 ) ) ) ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , "__enable_execute_stack" ) , LCT_NORMAL , VOIDmode , 1 , XEXP ( m_tramp , 0 ) , Pmode ) ; } </s>

The 64 bit version is simpler because it makes more sense to load the values as `` immediate '' data out of the trampoline . It 's also easier since we can read the PC without clobbering a register .


<s> bool SITargetLowering :: isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const { return isFlatGlobalAddrSpace ( SrcAS ) && isFlatGlobalAddrSpace ( DestAS ) ; } </s>

Returns true if a cast between SrcAS and DestAS is a noop .


<s> static rtx mep_convert_regnum ( const struct cgen_regnum_operand * regnum , rtx arg ) { if ( regnum -> count == 0 ) return arg ; if ( GET_CODE ( arg ) != CONST_INT || INTVAL ( arg ) < 0 || INTVAL ( arg ) >= regnum -> count ) return 0 ; return gen_rtx_REG ( SImode , INTVAL ( arg ) + regnum -> base ) ; } </s>

Apply regnum conversions to ARG using the description given by REGNUM . Return the new argument on success and null on failure .


<s> AMDGPUSubtarget & AMDGPUSubtarget :: initializeSubtargetDependencies ( const Triple & TT , StringRef GPU , StringRef FS ) { SmallString < 256 > FullFS ( "+promote-alloca,+fp64-denormals," ) ; if ( isAmdHsaOS ( ) ) FullFS += "+flat-for-global," ; FullFS += FS ; ParseSubtargetFeatures ( GPU , FullFS ) ; if ( getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) { FP32Denormals = false ; FP64Denormals = false ; } if ( MaxPrivateElementSize == 0 ) MaxPrivateElementSize = 16 ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool mayNeedRelaxation ( const MCInst & ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s>
bool
AArch64AsmPrinter
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
const
{
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
)
return
false
;
assert
(
!
MO
.
getSubReg
(
)
&&
"Subregs should be eliminated!"
)
;
MCOp
=
MCOperand
::
CreateReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
CreateImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_FPImmediate
:
{
assert
(
MO
.
getFPImm
(
)
->
isZero
(
)
&&
"Only fp imm 0.0 is supported"
)
;
MCOp
=
MCOperand
::
CreateFPImm
(
0.0
)
;
break
;
}
case
MachineOperand
::
MO_BlockAddress
:
MCOp
=
lowerSymbolOperand
(
MO
,
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
lowerSymbolOperand
(
MO
,
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
lowerSymbolOperand
(
MO
,
getSymbol
(
MO
.
getGlobal
(
)
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
CreateExpr
(
MCSymbolRefExpr
::
Create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
OutContext
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
MCOp
=
lowerSymbolOperand
(
MO
,
GetJTISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
MCOp
=
lowerSymbolOperand
(
MO
,
GetCPISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_RegisterMask
:
return
false
;
}
return
true
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> const char * MMIXTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( MMIXISD :: NodeType ) Opcode ) { case MMIXISD :: FIRST_NUMBER : break ; case MMIXISD :: RET_FLAG : return "MMIXISD::RET_FLAG" ; case MMIXISD :: CALL : return "MMIXISD::CALL" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static bool s390_call_saved_register_used ( tree call_expr ) { CUMULATIVE_ARGS cum_v ; cumulative_args_t cum ; tree parameter ; machine_mode mode ; tree type ; rtx parm_rtx ; int reg , i ; INIT_CUMULATIVE_ARGS ( cum_v , NULL , NULL , 0 , 0 ) ; cum = pack_cumulative_args ( & cum_v ) ; for ( i = 0 ; i < call_expr_nargs ( call_expr ) ; i ++ ) { parameter = CALL_EXPR_ARG ( call_expr , i ) ; gcc_assert ( parameter ) ; if ( TREE_CODE ( parameter ) == ERROR_MARK ) return true ; type = TREE_TYPE ( parameter ) ; gcc_assert ( type ) ; mode = TYPE_MODE ( type ) ; gcc_assert ( mode ) ; if ( pass_by_reference ( & cum_v , mode , type , true ) ) { mode = Pmode ; type = build_pointer_type ( type ) ; } parm_rtx = s390_function_arg ( cum , mode , type , true ) ; s390_function_arg_advance ( cum , mode , type , true ) ; if ( ! parm_rtx ) continue ; if ( REG_P ( parm_rtx ) ) { for ( reg = 0 ; reg < HARD_REGNO_NREGS ( REGNO ( parm_rtx ) , GET_MODE ( parm_rtx ) ) ; reg ++ ) if ( ! call_used_regs [ reg + REGNO ( parm_rtx ) ] ) return true ; } if ( GET_CODE ( parm_rtx ) == PARALLEL ) { int i ; for ( i = 0 ; i < XVECLEN ( parm_rtx , 0 ) ; i ++ ) { rtx r = XEXP ( XVECEXP ( parm_rtx , 0 , i ) , 0 ) ; gcc_assert ( REG_P ( r ) ) ; for ( reg = 0 ; reg < HARD_REGNO_NREGS ( REGNO ( r ) , GET_MODE ( r ) ) ; reg ++ ) if ( ! call_used_regs [ reg + REGNO ( r ) ] ) return true ; } } } return false ; } </s>

Checks whether the given ARGUMENT_LIST would use a caller saved register . This is used to decide whether sibling call optimization could be performed on the respective function call .


<s> bool TOYFrameLowering :: hasFP ( const MachineFunction & MF ) const { return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


Compute the size of the local area and the size to be adjusted by the prologue and epilogue .


<s> MachineInstr * foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , ArrayRef < unsigned > Ops , MachineInstr * LoadMI ) const override { return nullptr ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> unsigned PPCTargetLowering :: getByValTypeAlignment ( Type * Ty , const DataLayout & DL ) const { Align Alignment = Subtarget . isPPC64 ( ) ? Align ( 8 ) : Align ( 4 ) ; if ( Subtarget . hasAltivec ( ) ) getMaxByValAlign ( Ty , Alignment , Align ( 16 ) ) ; return Alignment . value ( ) ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


<s> bool X86TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( ! VT . isSimple ( ) ) return false ; MVT SVT = VT . getSimpleVT ( ) ; if ( VT . getSizeInBits ( ) == 64 ) return false ; if ( ( SVT . is128BitVector ( ) && Subtarget -> hasSSSE3 ( ) ) || ( SVT . is256BitVector ( ) && Subtarget -> hasInt256 ( ) ) ) { bool isLegal = true ; for ( unsigned I = 0 , E = M . size ( ) ; I != E ; ++ I ) { if ( M [ I ] >= ( int ) SVT . getVectorNumElements ( ) || ShuffleCrosses128bitLane ( SVT , I , M [ I ] ) ) { isLegal = false ; break ; } } if ( isLegal ) return true ; } return ( SVT . getVectorNumElements ( ) == 2 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isMOVLMask ( M , SVT ) || isSHUFPMask ( M , SVT ) || isPSHUFDMask ( M , SVT ) || isPSHUFHWMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isPSHUFLWMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isPALIGNRMask ( M , SVT , Subtarget ) || isUNPCKLMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isUNPCKHMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isUNPCKL_v_undef_Mask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isUNPCKH_v_undef_Mask ( M , SVT , Subtarget -> hasInt256 ( ) ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> bool X86TargetLowering :: isScalarFPTypeInSSEReg ( EVT VT ) const { return ( VT == MVT :: f64 && Subtarget . hasSSE2 ( ) ) || ( VT == MVT :: f32 && Subtarget . hasSSE1 ( ) ) || ( VT == MVT :: f16 && Subtarget . hasFP16 ( ) ) ; } </s>

Return true if the specified scalar FP type is computed in an SSE register , not on the X87 floating point stack .


<s> bool HexagonInstrInfo :: isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumInstrs , BranchProbability Probability ) const { return NumInstrs <= 4 ; } </s>

Return true if it 's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion .


"Function has local memory argument.  Promoting to "

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s>
StringRef
ARM64MCExpr
::
getVariantKindName
(
)
const
{
switch
(
static_cast
<
uint32_t
>
(
getKind
(
)
)
)
{
case
VK_CALL
:
return
""
;
case
VK_LO12
:
return
":lo12:"
;
case
VK_ABS_G3
:
return
":abs_g3:"
;
case
VK_ABS_G2
:
return
":abs_g2:"
;
case
VK_ABS_G2_S
:
return
":abs_g2_s:"
;
case
VK_ABS_G2_NC
:
return
":abs_g2_nc:"
;
case
VK_ABS_G1
:
return
":abs_g1:"
;
case
VK_ABS_G1_S
:
return
":abs_g1_s:"
;
case
VK_ABS_G1_NC
:
return
":abs_g1_nc:"
;
case
VK_ABS_G0
:
return
":abs_g0:"
;
case
VK_ABS_G0_S
:
return
":abs_g0_s:"
;
case
VK_ABS_G0_NC
:
return
":abs_g0_nc:"
;
case
VK_DTPREL_G2
:
return
":dtprel_g2:"
;
case
VK_DTPREL_G1
:
return
":dtprel_g1:"
;
case
VK_DTPREL_G1_NC
:
return
":dtprel_g1_nc:"
;
case
VK_DTPREL_G0
:
return
":dtprel_g0:"
;
case
VK_DTPREL_G0_NC
:
return
":dtprel_g0_nc:"
;
case
VK_DTPREL_LO12
:
return
":dtprel_lo12:"
;
case
VK_DTPREL_LO12_NC
:
return
":dtprel_lo12_nc:"
;
case
VK_TPREL_G2
:
return
":tprel_g2:"
;
case
VK_TPREL_G1
:
return
":tprel_g1:"
;
case
VK_TPREL_G1_NC
:
return
":tprel_g1_nc:"
;
case
VK_TPREL_G0
:
return
":tprel_g0:"
;
case
VK_TPREL_G0_NC
:
return
":tprel_g0_nc:"
;
case
VK_TPREL_LO12
:
return
":tprel_lo12:"
;
case
VK_TPREL_LO12_NC
:
return
":tprel_lo12_nc:"
;
case
VK_TLSDESC_LO12
:
return
":tlsdesc_lo12:"
;
case
VK_ABS_PAGE
:
return
""
;
case
VK_GOT_PAGE
:
return
":got:"
;
case
VK_GOT_LO12
:
return
":got_lo12:"
;
case
VK_GOTTPREL_PAGE
:
return
":gottprel:"
;
case
VK_GOTTPREL_LO12_NC
:
return
":gottprel_lo12:"
;
case
VK_GOTTPREL_G1
:
return
":gottprel_g1:"
;
case
VK_GOTTPREL_G0_NC
:
return
":gottprel_g0_nc:"
;
case
VK_TLSDESC
:
return
""
;
case
VK_TLSDESC_PAGE
:
return
":tlsdesc:"
;
default
:
llvm_unreachable
(
"Invalid ELF symbol kind"
)
;
}
}
</s>

Convert the variant kind into an ELF-appropriate modifier ( e.g .


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const override { unsigned Size = 0 ; switch ( ( unsigned ) Fixup . getKind ( ) ) { case FK_Data_1 : Size = 1 ; break ; case FK_Data_2 : Size = 2 ; break ; case FK_Data_4 : Size = 4 ; break ; case FK_Data_8 : Size = 8 ; break ; default : return ; } for ( unsigned i = 0 ; i < Size ; ++ i ) { Data [ i + Fixup . getOffset ( ) ] |= static_cast < uint8_t > ( Value >> ( i * 8 ) ) ; } return ; } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool SIMemoryLegalizer :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; SIMemOpAccess MOA ( MF ) ; CC = SICacheControl :: create ( MF . getSubtarget < SISubtarget > ( ) ) ; for ( auto & MBB : MF ) { for ( auto MI = MBB . begin ( ) ; MI != MBB . end ( ) ; ++ MI ) { if ( ! ( MI -> getDesc ( ) . TSFlags & SIInstrFlags :: maybeAtomic ) ) continue ; if ( const auto & MOI = MOA . getLoadInfo ( MI ) ) Changed |= expandLoad ( MOI . getValue ( ) , MI ) ; else if ( const auto & MOI = MOA . getStoreInfo ( MI ) ) Changed |= expandStore ( MOI . getValue ( ) , MI ) ; else if ( const auto & MOI = MOA . getAtomicFenceInfo ( MI ) ) Changed |= expandAtomicFence ( MOI . getValue ( ) , MI ) ; else if ( const auto & MOI = MOA . getAtomicCmpxchgOrRmwInfo ( MI ) ) Changed |= expandAtomicCmpxchgOrRmw ( MOI . getValue ( ) , MI ) ; } } Changed |= removeAtomicPseudoMIs ( ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .

AMDGPU SI SI SI SI SIInstrFlags::maybeAtomic


"SIInstrInfo::storeRegToStackSlot - Do not know how to"

Store the specified register of the given register class to the specified stack frame index .


<s> EVT ARMTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , const AttributeList & FuncAttributes ) const { if ( ( ! IsMemset || ZeroMemset ) && Subtarget -> hasNEON ( ) && ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { bool Fast ; if ( Size >= 16 && ( memOpAlign ( SrcAlign , DstAlign , 16 ) || ( allowsMisalignedMemoryAccesses ( MVT :: v2f64 , 0 , 1 , & Fast ) && Fast ) ) ) { return MVT :: v2f64 ; } else if ( Size >= 8 && ( memOpAlign ( SrcAlign , DstAlign , 8 ) || ( allowsMisalignedMemoryAccesses ( MVT :: f64 , 0 , 1 , & Fast ) && Fast ) ) ) { return MVT :: f64 ; } } return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> unsigned PPCDispatchGroupSBHazardRecognizer :: PreEmitNoops ( SUnit * SU ) { if ( isLoadAfterStore ( SU ) && CurSlots < 6 ) { unsigned Directive = DAG -> TM . getSubtarget < PPCSubtarget > ( ) . getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_PWR6 || Directive == PPC :: DIR_PWR7 || Directive == PPC :: DIR_PWR8 ) return 1 ; return 5 - CurSlots ; } return ScoreboardHazardRecognizer :: PreEmitNoops ( SU ) ; } </s>

PreEmitNoops - This callback is invoked prior to emitting an instruction .


<s> static poly_int64 aarch64_vl_bytes ( machine_mode mode , unsigned int vec_flags ) { if ( vec_flags & VEC_PARTIAL ) return GET_MODE_SIZE ( mode ) ; if ( vec_flags & VEC_SVE_DATA ) return BYTES_PER_SVE_VECTOR ; gcc_assert ( vec_flags & VEC_SVE_PRED ) ; return BYTES_PER_SVE_PRED ; } </s>

Return the number of defined bytes in one constituent vector of SVE mode MODE , which has vector flags VEC_FLAGS .


<s> XCoreSubtarget :: XCoreSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : XCoreGenSubtargetInfo ( TT , CPU , FS ) , InstrInfo ( ) , FrameLowering ( * this ) , TLInfo ( TM , * this ) , TSInfo ( * TM . getDataLayout ( ) ) { } </s>

This constructor initializes the data members to match that of the specified triple .


<s> static void m68k_split_offset ( rtx x , rtx * base , HOST_WIDE_INT * offset ) { * offset = 0 ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) { * offset += INTVAL ( XEXP ( x , 1 ) ) ; x = XEXP ( x , 0 ) ; } * base = x ; } </s>

Split X into a base and a constant offset , storing them in * BASE and * OFFSET respectively .


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( Size , Offset , true ) ; MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; Register AddrReg = MRI . createGenericVirtualRegister ( LLT :: pointer ( AMDGPUAS :: PRIVATE_ADDRESS , 32 ) ) ; MIRBuilder . buildFrameIndex ( AddrReg , FI ) ; StackUsed = std :: max ( StackUsed , Size + Offset ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> void nds32_construct_isr_vectors_information ( tree func_attrs , const char * func_name ) { tree save_all , partial_save ; tree nested , not_nested , nested_ready ; tree intr , excp , reset ; save_all = lookup_attribute ( "save_all" , func_attrs ) ; partial_save = lookup_attribute ( "partial_save" , func_attrs ) ; nested = lookup_attribute ( "nested" , func_attrs ) ; not_nested = lookup_attribute ( "not_nested" , func_attrs ) ; nested_ready = lookup_attribute ( "nested_ready" , func_attrs ) ; intr = lookup_attribute ( "interrupt" , func_attrs ) ; excp = lookup_attribute ( "exception" , func_attrs ) ; reset = lookup_attribute ( "reset" , func_attrs ) ; if ( ! intr && ! excp && ! reset ) return ; if ( intr || excp ) { tree id_list ; id_list = ( intr ) ? ( TREE_VALUE ( intr ) ) : ( TREE_VALUE ( excp ) ) ; while ( id_list ) { tree id ; int vector_id ; unsigned int vector_number_offset ; vector_number_offset = ( intr ) ? ( 9 ) : ( 0 ) ; id = TREE_VALUE ( id_list ) ; vector_id = TREE_INT_CST_LOW ( id ) + vector_number_offset ; nds32_isr_vectors [ vector_id ] . category = ( intr ) ? ( NDS32_ISR_INTERRUPT ) : ( NDS32_ISR_EXCEPTION ) ; strcpy ( nds32_isr_vectors [ vector_id ] . func_name , func_name ) ; if ( save_all ) nds32_isr_vectors [ vector_id ] . save_reg = NDS32_SAVE_ALL ; else if ( partial_save ) nds32_isr_vectors [ vector_id ] . save_reg = NDS32_PARTIAL_SAVE ; if ( nested ) nds32_isr_vectors [ vector_id ] . nested_type = NDS32_NESTED ; else if ( not_nested ) nds32_isr_vectors [ vector_id ] . nested_type = NDS32_NOT_NESTED ; else if ( nested_ready ) nds32_isr_vectors [ vector_id ] . nested_type = NDS32_NESTED_READY ; id_list = TREE_CHAIN ( id_list ) ; } } else { tree id_list ; tree id ; tree nmi , warm ; nds32_isr_vectors [ 0 ] . category = NDS32_ISR_RESET ; id_list = TREE_VALUE ( reset ) ; id = TREE_VALUE ( id_list ) ; nds32_isr_vectors [ 0 ] . total_n_vectors = TREE_INT_CST_LOW ( id ) + 8 + 1 ; strcpy ( nds32_isr_vectors [ 0 ] . func_name , func_name ) ; nmi = lookup_attribute ( "nmi" , func_attrs ) ; warm = lookup_attribute ( "warm" , func_attrs ) ; if ( nmi != NULL_TREE ) { tree nmi_func_list ; tree nmi_func ; nmi_func_list = TREE_VALUE ( nmi ) ; nmi_func = TREE_VALUE ( nmi_func_list ) ; strcpy ( nds32_isr_vectors [ 0 ] . nmi_name , IDENTIFIER_POINTER ( nmi_func ) ) ; } if ( warm != NULL_TREE ) { tree warm_func_list ; tree warm_func ; warm_func_list = TREE_VALUE ( warm ) ; warm_func = TREE_VALUE ( warm_func_list ) ; strcpy ( nds32_isr_vectors [ 0 ] . warm_name , IDENTIFIER_POINTER ( warm_func ) ) ; } } } </s>

Function to construct isr vectors information array . We DO NOT HAVE TO check if the attributes are valid because those works are supposed to be done on nds32_merge_decl_attributes ( ) and nds32_insert_attributes ( ) .


<s> void MipsTargetELFStreamer :: finish ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; const MCObjectFileInfo & OFI = * MCA . getContext ( ) . getObjectFileInfo ( ) ; MCSection & TextSection = * OFI . getTextSection ( ) ; MCA . registerSection ( TextSection ) ; MCSection & DataSection = * OFI . getDataSection ( ) ; MCA . registerSection ( DataSection ) ; MCSection & BSSSection = * OFI . getBSSSection ( ) ; MCA . registerSection ( BSSSection ) ; TextSection . setAlignment ( std :: max ( 16u , TextSection . getAlignment ( ) ) ) ; DataSection . setAlignment ( std :: max ( 16u , DataSection . getAlignment ( ) ) ) ; BSSSection . setAlignment ( std :: max ( 16u , BSSSection . getAlignment ( ) ) ) ; if ( RoundSectionSizes ) { MCStreamer & OS = getStreamer ( ) ; for ( MCSection & S : MCA ) { MCSectionELF & Section = static_cast < MCSectionELF & > ( S ) ; unsigned Alignment = Section . getAlignment ( ) ; if ( Alignment ) { OS . SwitchSection ( & Section ) ; if ( Section . UseCodeAlign ( ) ) OS . EmitCodeAlignment ( Alignment , Alignment ) ; else OS . EmitValueToAlignment ( Alignment , 0 , 1 , Alignment ) ; } } } const FeatureBitset & Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI_O32 ; else if ( getABI ( ) . IsN32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI2 ; if ( Features [ Mips :: FeatureGP64Bit ] ) { if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_32BITMODE ; } else if ( Features [ Mips :: FeatureMips64r2 ] || Features [ Mips :: FeatureMips64 ] ) EFlags |= ELF :: EF_MIPS_32BITMODE ; if ( EFlags & ELF :: EF_MIPS_CPIC && getABI ( ) . IsN64 ( ) ) EFlags |= ELF :: EF_MIPS_PIC ; MCA . setELFHeaderEFlags ( EFlags ) ; MipsELFStreamer & MEF = static_cast < MipsELFStreamer & > ( Streamer ) ; MEF . EmitMipsOptionRecords ( ) ; emitMipsAbiFlags ( ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> bool ARMLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { const TargetMachine & TM = Fn . getTarget ( ) ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; TII = TM . getInstrInfo ( ) ; TRI = TM . getRegisterInfo ( ) ; RS = new RegScavenger ( ) ; isThumb2 = AFI -> isThumb2Function ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= LoadStoreMultipleOpti ( MBB ) ; Modified |= MergeReturnIntoLDM ( MBB ) ; } delete RS ; return Modified ; } </s>


<s> bool ARMAsmParser :: ParseInstruction ( const StringRef & Name , SMLoc NameLoc , SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { OwningPtr < ARMOperand > Op ; ARMOperand :: CreateToken ( Op , Name , NameLoc ) ; Operands . push_back ( Op . take ( ) ) ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { OwningPtr < ARMOperand > Op ; if ( ParseOperand ( Op ) ) return true ; Operands . push_back ( Op . take ( ) ) ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( ParseOperand ( Op ) ) return true ; Operands . push_back ( Op . take ( ) ) ; } } return false ; } </s>

ParseInstruction - Parse one assembly instruction .


<s> bool SPIRVAsmPrinter :: doInitialization ( Module & M ) { ModuleSectionsEmitted = false ; return AsmPrinter :: doInitialization ( M ) ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> bool MipsSETargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , Align , MachineMemOperand :: Flags , bool * Fast ) const { MVT :: SimpleValueType SVT = VT . getSimpleVT ( ) . SimpleTy ; if ( Subtarget . systemSupportsUnalignedAccess ( ) ) { if ( Fast ) * Fast = true ; return true ; } switch ( SVT ) { case MVT :: i64 : case MVT :: i32 : if ( Fast ) * Fast = true ; return true ; default : return false ; } } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> rtx thumb_legitimize_address ( rtx x , rtx orig_x , machine_mode mode ) { if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , 1 ) ) && ( INTVAL ( XEXP ( x , 1 ) ) >= 32 * GET_MODE_SIZE ( mode ) || INTVAL ( XEXP ( x , 1 ) ) < 0 ) ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; HOST_WIDE_INT offset = INTVAL ( xop1 ) ; if ( optimize_size && offset >= 0 && offset < 256 + 31 * GET_MODE_SIZE ( mode ) ) { HOST_WIDE_INT delta ; if ( offset >= 256 ) delta = offset - ( 256 - GET_MODE_SIZE ( mode ) ) ; else if ( offset < 32 * GET_MODE_SIZE ( mode ) + 8 ) delta = 31 * GET_MODE_SIZE ( mode ) ; else delta = offset & ( ~ 31 * GET_MODE_SIZE ( mode ) ) ; xop0 = force_operand ( plus_constant ( Pmode , xop0 , offset - delta ) , NULL_RTX ) ; x = plus_constant ( Pmode , xop0 , delta ) ; } else if ( offset < 0 && offset > - 256 ) x = force_operand ( x , NULL_RTX ) ; else { xop1 = force_reg ( SImode , xop1 ) ; x = gen_rtx_PLUS ( SImode , xop0 , xop1 ) ; } } else if ( GET_CODE ( x ) == PLUS && s_register_operand ( XEXP ( x , 1 ) , SImode ) && ! s_register_operand ( XEXP ( x , 0 ) , SImode ) ) { rtx xop0 = force_operand ( XEXP ( x , 0 ) , NULL_RTX ) ; x = gen_rtx_PLUS ( SImode , xop0 , XEXP ( x , 1 ) ) ; } if ( flag_pic ) { rtx new_x = legitimize_pic_address ( orig_x , mode , NULL_RTX , NULL_RTX , false ) ; if ( new_x != orig_x ) x = new_x ; } return x ; } </s>

Try machine-dependent ways of modifying an illegitimate Thumb address to be legitimate . If we find one , return the new , valid address .


<s>
void
SIInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
DestReg
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
SIMachineFunctionInfo
*
MFI
=
MF
->
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MachineFrameInfo
&
FrameInfo
=
MF
->
getFrameInfo
(
)
;
const
DebugLoc
&
DL
=
MBB
.
findDebugLoc
(
MI
)
;
unsigned
Align
=
FrameInfo
.
getObjectAlignment
(
FrameIndex
)
;
unsigned
Size
=
FrameInfo
.
getObjectSize
(
FrameIndex
)
;
unsigned
SpillSize
=
TRI
->
getSpillSize
(
*
RC
)
;
MachinePointerInfo
PtrInfo
=
MachinePointerInfo
::
getFixedStack
(
*
MF
,
FrameIndex
)
;
MachineMemOperand
*
MMO
=
MF
->
getMachineMemOperand
(
PtrInfo
,
MachineMemOperand
::
MOLoad
,
Size
,
Align
)
;
if
(
RI
.
isSGPRClass
(
RC
)
)
{
MFI
->
setHasSpilledSGPRs
(
)
;
const
MCInstrDesc
&
OpDesc
=
get
(
getSGPRSpillRestoreOpcode
(
SpillSize
)
)
;
if
(
TargetRegisterInfo
::
isVirtualRegister
(
DestReg
)
&&
SpillSize
==
4
)
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
MRI
.
constrainRegClass
(
DestReg
,
&
AMDGPU
::
SReg_32_XM0RegClass
)
;
}
if
(
RI
.
spillSGPRToVGPR
(
)
)
FrameInfo
.
setStackID
(
FrameIndex
,
TargetStackID
::
SGPRSpill
)
;
MachineInstrBuilder
Spill
=
BuildMI
(
MBB
,
MI
,
DL
,
OpDesc
,
DestReg
)
.
addFrameIndex
(
FrameIndex
)
.
addMemOperand
(
MMO
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
,
RegState
::
Implicit
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
,
RegState
::
Implicit
)
;
if
(
ST
.
hasScalarStores
(
)
)
{
Spill
.
addReg
(
AMDGPU
::
M0
,
RegState
::
ImplicitDefine
|
RegState
::
Dead
)
;
}
return
;
}
assert
(
RI
.
hasVGPRs
(
RC
)
&&
"Only VGPR spilling expected"
)
;
unsigned
Opcode
=
getVGPRSpillRestoreOpcode
(
SpillSize
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opcode
)
,
DestReg
)
.
addFrameIndex
(
FrameIndex
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> int ia64_epilogue_uses ( int regno ) { switch ( regno ) { case R_GR ( 1 ) : return ! ( TARGET_AUTO_PIC || TARGET_NO_PIC ) ; case IN_REG ( 0 ) : case IN_REG ( 1 ) : case IN_REG ( 2 ) : case IN_REG ( 3 ) : case IN_REG ( 4 ) : case IN_REG ( 5 ) : case IN_REG ( 6 ) : case IN_REG ( 7 ) : return lookup_attribute ( "syscall_linkage" , TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ) != NULL ; case R_BR ( 0 ) : return 1 ; case AR_PFS_REGNUM : return 1 ; default : return 0 ; } } </s>

Return true if REGNO is used by the epilogue .


" EXPORTed [base class of exported class]\n"

Decide if a base class of a class should also have its vtable and rtti exported .


"last register name %s must be an odd register"

Parse -mirq-ctrl-saved=RegisterRange , blink , lp_copunt . The register range is specified as two registers separated by a dash . It always starts with r0 , and its upper limit is fp register . blink and lp_count registers are optional .


<s> SMLoc getStartLoc ( ) const { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> void UnwindOpcodeAssembler :: EmitRegSave ( uint32_t RegSave ) { if ( RegSave == 0u ) { EmitInt8 ( ARM :: EHABI :: UNWIND_OPCODE_POP_RA_AUTH_CODE ) ; return ; } if ( RegSave & ( 1u << 4 ) ) { uint32_t Mask = RegSave & 0xff0u ; uint32_t Range = countTrailingOnes ( Mask >> 5 ) ; Mask &= ~ ( 0xffffffe0u << Range ) ; uint32_t UnmaskedReg = RegSave & 0xfff0u & ( ~ Mask ) ; if ( UnmaskedReg == 0u ) { EmitInt8 ( ARM :: EHABI :: UNWIND_OPCODE_POP_REG_RANGE_R4 | Range ) ; RegSave &= 0x000fu ; } else if ( UnmaskedReg == ( 1u << 14 ) ) { EmitInt8 ( ARM :: EHABI :: UNWIND_OPCODE_POP_REG_RANGE_R4_R14 | Range ) ; RegSave &= 0x000fu ; } } if ( ( RegSave & 0xfff0u ) != 0 ) EmitInt16 ( ARM :: EHABI :: UNWIND_OPCODE_POP_REG_MASK_R4 | ( RegSave >> 4 ) ) ; if ( ( RegSave & 0x000fu ) != 0 ) EmitInt16 ( ARM :: EHABI :: UNWIND_OPCODE_POP_REG_MASK | ( RegSave & 0x000fu ) ) ; } </s>

Emit unwind opcodes for .save directives .


<s>
const
char
*
output_probe_stack_range
(
rtx
reg1
,
rtx
reg2
)
{
static
int
labelno
=
0
;
char
loop_lab
[
32
]
;
rtx
xops
[
2
]
;
ASM_GENERATE_INTERNAL_LABEL
(
loop_lab
,
"LPSRL"
,
labelno
++
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
loop_lab
)
;
xops
[
0
]
=
reg1
;
xops
[
1
]
=
GEN_INT
(
PROBE_INTERVAL
)
;
output_asm_insn
(
"addi %0,%0,%1"
,
xops
)
;
xops
[
1
]
=
gen_rtx_REG
(
Pmode
,
0
)
;
output_asm_insn
(
"stw %1,0(%0)"
,
xops
)
;
xops
[
1
]
=
reg2
;
if
(
TARGET_64BIT
)
output_asm_insn
(
"cmpd 0,%0,%1"
,
xops
)
;
else
output_asm_insn
(
"cmpw 0,%0,%1"
,
xops
)
;
fputs
(
"\tbne 0,"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
loop_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
return
""
;
}
</s>

Wrapper around the output_probe_stack_range routines .


<s> void MCallSubGraph :: view ( ) { ViewGraph ( * this , "MCallSubGraph" ) ; } </s>

Opens a viewer to show the GraphViz visualization of the regions .


<s> static bool microblaze_const_double_ok ( rtx op , machine_mode mode ) { REAL_VALUE_TYPE d ; if ( GET_CODE ( op ) != CONST_DOUBLE ) return 0 ; if ( GET_MODE ( op ) == VOIDmode ) return 1 ; if ( mode != SFmode && mode != DFmode ) return 0 ; if ( op == CONST0_RTX ( mode ) ) return 1 ; d = * CONST_DOUBLE_REAL_VALUE ( op ) ; if ( REAL_VALUE_ISNAN ( d ) ) return FALSE ; if ( REAL_VALUE_NEGATIVE ( d ) ) d = real_value_negate ( & d ) ; if ( mode == DFmode ) { if ( real_less ( & d , & dfhigh ) && real_less ( & dflow , & d ) ) return 1 ; } else { if ( real_less ( & d , & sfhigh ) && real_less ( & sflow , & d ) ) return 1 ; } return 0 ; } </s>

Return truth value if a CONST_DOUBLE is ok to be a legitimate constant .


<s>
static
rtx
mips_prepare_builtin_arg
(
enum
insn_code
icode
,
unsigned
int
op
,
tree
*
arglist
)
{
rtx
value
;
enum
machine_mode
mode
;
value
=
expand_expr
(
TREE_VALUE
(
*
arglist
)
,
NULL_RTX
,
VOIDmode
,
0
)
;
mode
=
insn_data
[
icode
]
.
operand
[
op
]
.
mode
;
if
(
!
insn_data
[
icode
]
.
operand
[
op
]
.
predicate
(
value
,
mode
)
)
{
value
=
copy_to_mode_reg
(
mode
,
value
)
;
if
(
!
insn_data
[
icode
]
.
operand
[
op
]
.
predicate
(
value
,
mode
)
)
{
error
(
"invalid argument to builtin function"
)
;
return
const0_rtx
;
}
}
*
arglist
=
TREE_CHAIN
(
*
arglist
)
;
return
value
;
}
</s>

Take the head of argument list * ARGLIST and convert it into a form suitable for input operand OP of instruction ICODE . Return the value and point * ARGLIST at the next element of the list .

mips
0
"invalid argument to builtin function"


<s> StringRef getPassName ( ) const override { return AVR_EXPAND_PSEUDO_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> static void rs6000_eliminate_indexed_memrefs ( rtx operands [ 2 ] ) { if ( reload_in_progress ) return ; if ( GET_CODE ( operands [ 0 ] ) == MEM && GET_CODE ( XEXP ( operands [ 0 ] , 0 ) ) != REG && ! legitimate_constant_pool_address_p ( XEXP ( operands [ 0 ] , 0 ) , GET_MODE ( operands [ 0 ] ) , false ) ) operands [ 0 ] = replace_equiv_address ( operands [ 0 ] , copy_addr_to_reg ( XEXP ( operands [ 0 ] , 0 ) ) ) ; if ( GET_CODE ( operands [ 1 ] ) == MEM && GET_CODE ( XEXP ( operands [ 1 ] , 0 ) ) != REG && ! legitimate_constant_pool_address_p ( XEXP ( operands [ 1 ] , 0 ) , GET_MODE ( operands [ 1 ] ) , false ) ) operands [ 1 ] = replace_equiv_address ( operands [ 1 ] , copy_addr_to_reg ( XEXP ( operands [ 1 ] , 0 ) ) ) ; } </s>

Helper for the following . Get rid of [ r+r ] memory refs in cases where it wo n't work ( TImode , TFmode ) .


<s> static rtx ix86_load_bounds ( rtx slot , rtx ptr , rtx slot_no ) { rtx reg = gen_reg_rtx ( BNDmode ) ; rtx addr ; addr = ix86_get_arg_address_for_bt ( slot , slot_no , arg_pointer_rtx ) ; if ( ! ptr ) { gcc_assert ( MEM_P ( slot ) ) ; ptr = copy_addr_to_reg ( slot ) ; } emit_insn ( BNDmode == BND64mode ? gen_bnd64_ldx ( reg , addr , ptr ) : gen_bnd32_ldx ( reg , addr , ptr ) ) ; return reg ; } </s>

Expand pass uses this hook to load bounds for function parameter PTR passed in SLOT in case its bounds are not passed in a register . If SLOT is a memory , then bounds are loaded as for regular pointer loaded from memory . PTR may be NULL in case SLOT is a memory . In such case value of PTR ( if required ) may be loaded from SLOT . If SLOT is NULL or a register then SLOT_NO is an integer constant holding number of the target dependent special slot which should be used to obtain bounds . Return loaded bounds .


<s> bool Error ( SMLoc L , const Twine & Msg , ArrayRef < SMRange > Ranges = None ) { return getParser ( ) . Error ( L , Msg , Ranges ) ; } </s>

Return an error at the location L , with the message Msg .


This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> void R600PassConfig :: addPreSched2 ( ) { addPass ( createR600EmitClauseMarkers ( ) ) ; if ( EnableR600IfConvert ) addPass ( & IfConverterID ) ; addPass ( createR600ClauseMergePass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> void MMIXFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MMIXRegisterInfo * RI = STI . getRegisterInfo ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; uint64_t StackAlign = RI -> needsStackRealignment ( MF ) ? MFI . getMaxAlignment ( ) : getStackAlignment ( ) ; uint64_t MaxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; if ( MFI . hasVarSizedObjects ( ) ) MaxCallFrameSize = alignTo ( MaxCallFrameSize , StackAlign ) ; MFI . setMaxCallFrameSize ( MaxCallFrameSize ) ; if ( ! ( hasReservedCallFrame ( MF ) && MFI . adjustsStack ( ) ) ) FrameSize += MaxCallFrameSize ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI . setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


"cannot combine a base of type %qT with"

Require arguments ARGNO and ARGNO + 1 to form an ADR-style address , i.e . one with a vector of base addresses and a vector of displacements . The overloaded function 's mode suffix determines the units of the displacement ( bytes for `` _offset '' , elements for `` _index '' ) . Return the associated mode suffix on success , otherwise report an error and return MODE_none .


<s> void PIC16Overlay :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesAll ( ) ; AU . addRequired < CallGraph > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool AArch64TargetLowering :: isExtFreeImpl ( const Instruction * Ext ) const { if ( isa < FPExtInst > ( Ext ) ) return false ; if ( Ext -> getType ( ) -> isVectorTy ( ) ) return false ; for ( const Use & U : Ext -> uses ( ) ) { const Instruction * Instr = cast < Instruction > ( U . getUser ( ) ) ; switch ( Instr -> getOpcode ( ) ) { case Instruction :: Shl : if ( ! isa < ConstantInt > ( Instr -> getOperand ( 1 ) ) ) return false ; break ; case Instruction :: GetElementPtr : { gep_type_iterator GTI = gep_type_begin ( Instr ) ; auto & DL = Ext -> getModule ( ) -> getDataLayout ( ) ; std :: advance ( GTI , U . getOperandNo ( ) - 1 ) ; Type * IdxTy = GTI . getIndexedType ( ) ; uint64_t ShiftAmt = countTrailingZeros ( DL . getTypeStoreSizeInBits ( IdxTy ) ) - 3 ; if ( ShiftAmt == 0 || ShiftAmt > 4 ) return false ; break ; } case Instruction :: Trunc : if ( Instr -> getType ( ) == Ext -> getOperand ( 0 ) -> getType ( ) ) continue ; LLVM_FALLTHROUGH ; default : return false ; } } return true ; } </s>

Return true if the extension represented by I is free .


<s> static bool arm_evpc_neon_vuzp ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> nelt ; rtx out0 , out1 , in0 , in1 ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; int first_elem ; int swap_nelt ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; swap_nelt = BYTES_BIG_ENDIAN && ! d -> one_vector_p && GET_MODE_SIZE ( d -> vmode ) == 8 ? d -> nelt : 0 ; first_elem = d -> perm [ neon_endian_lane_map ( d -> vmode , 0 ) ] ^ swap_nelt ; if ( first_elem == neon_endian_lane_map ( d -> vmode , 0 ) ) odd = 0 ; else if ( first_elem == neon_endian_lane_map ( d -> vmode , 1 ) ) odd = 1 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt ; i ++ ) { unsigned elt = ( neon_pair_endian_lane_map ( d -> vmode , i ) * 2 + odd ) & mask ; if ( ( d -> perm [ i ] ^ swap_nelt ) != neon_pair_endian_lane_map ( d -> vmode , elt ) ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vuzpv16qi_internal ; break ; case V8QImode : gen = gen_neon_vuzpv8qi_internal ; break ; case V8HImode : gen = gen_neon_vuzpv8hi_internal ; break ; case V4HImode : gen = gen_neon_vuzpv4hi_internal ; break ; case V8HFmode : gen = gen_neon_vuzpv8hf_internal ; break ; case V4HFmode : gen = gen_neon_vuzpv4hf_internal ; break ; case V4SImode : gen = gen_neon_vuzpv4si_internal ; break ; case V2SImode : gen = gen_neon_vuzpv2si_internal ; break ; case V2SFmode : gen = gen_neon_vuzpv2sf_internal ; break ; case V4SFmode : gen = gen_neon_vuzpv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d -> op1 ; if ( swap_nelt != 0 ) std :: swap ( in0 , in1 ) ; out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( odd ) std :: swap ( out0 , out1 ) ; emit_insn ( gen ( out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s> void PPCPassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( & getPPCTargetMachine ( ) ) ) ; bool UsePrefetching = TM -> getTargetTriple ( ) . getVendor ( ) == Triple :: BGQ && getOptLevel ( ) != CodeGenOpt :: None ; if ( EnablePrefetch . getNumOccurrences ( ) > 0 ) UsePrefetching = EnablePrefetch ; if ( UsePrefetching ) addPass ( createPPCLoopDataPrefetchPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> MachineInstr * foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const { return 0 ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> unsigned HexagonInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case Hexagon :: L2_loadri_io : case Hexagon :: L2_loadrd_io : case Hexagon :: V6_vL32b_ai : case Hexagon :: V6_vL32b_nt_ai : case Hexagon :: V6_vL32Ub_ai : case Hexagon :: LDriw_pred : case Hexagon :: LDriw_mod : case Hexagon :: PS_vloadrq_ai : case Hexagon :: PS_vloadrw_ai : case Hexagon :: PS_vloadrw_nt_ai : { const MachineOperand OpFI = MI . getOperand ( 1 ) ; if ( ! OpFI . isFI ( ) ) return 0 ; const MachineOperand OpOff = MI . getOperand ( 2 ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != 0 ) return 0 ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } case Hexagon :: L2_ploadrit_io : case Hexagon :: L2_ploadrif_io : case Hexagon :: L2_ploadrdt_io : case Hexagon :: L2_ploadrdf_io : { const MachineOperand OpFI = MI . getOperand ( 2 ) ; if ( ! OpFI . isFI ( ) ) return 0 ; const MachineOperand OpOff = MI . getOperand ( 3 ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != 0 ) return 0 ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> void ix86_emit_swdivsf ( rtx res , rtx a , rtx b , machine_mode mode ) { rtx x0 , x1 , e0 , e1 ; x0 = gen_reg_rtx ( mode ) ; e0 = gen_reg_rtx ( mode ) ; e1 = gen_reg_rtx ( mode ) ; x1 = gen_reg_rtx ( mode ) ; b = force_reg ( mode , b ) ; if ( mode == V16SFmode || mode == V8DFmode ) emit_insn ( gen_rtx_SET ( x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , b ) , UNSPEC_RCP14 ) ) ) ; else emit_insn ( gen_rtx_SET ( x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , b ) , UNSPEC_RCP ) ) ) ; emit_insn ( gen_rtx_SET ( e0 , gen_rtx_MULT ( mode , x0 , b ) ) ) ; emit_insn ( gen_rtx_SET ( e0 , gen_rtx_MULT ( mode , x0 , e0 ) ) ) ; emit_insn ( gen_rtx_SET ( e1 , gen_rtx_PLUS ( mode , x0 , x0 ) ) ) ; emit_insn ( gen_rtx_SET ( x1 , gen_rtx_MINUS ( mode , e1 , e0 ) ) ) ; emit_insn ( gen_rtx_SET ( res , gen_rtx_MULT ( mode , a , x1 ) ) ) ; } </s>


<s> bool X86TTIImpl :: isLegalMaskedGather ( Type * DataTy , Align Alignment ) { if ( ! ( ST -> hasAVX512 ( ) || ( ST -> hasFastGather ( ) && ST -> hasAVX2 ( ) ) ) ) return false ; if ( auto * DataVTy = dyn_cast < FixedVectorType > ( DataTy ) ) { unsigned NumElts = DataVTy -> getNumElements ( ) ; if ( NumElts == 1 || ! isPowerOf2_32 ( NumElts ) ) return false ; } Type * ScalarTy = DataTy -> getScalarType ( ) ; if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == 32 || IntWidth == 64 ; } </s>

Return true if the target supports masked gather .


<s> BitVector SIRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; reserveRegisterTuples ( Reserved , AMDGPU :: EXEC ) ; reserveRegisterTuples ( Reserved , AMDGPU :: FLAT_SCR ) ; reserveRegisterTuples ( Reserved , AMDGPU :: M0 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_SHARED_BASE ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_SHARED_LIMIT ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_PRIVATE_BASE ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_PRIVATE_LIMIT ) ; reserveRegisterTuples ( Reserved , AMDGPU :: XNACK_MASK ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TBA ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TMA ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP0_TTMP1 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP2_TTMP3 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP4_TTMP5 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP6_TTMP7 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP8_TTMP9 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP10_TTMP11 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP12_TTMP13 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP14_TTMP15 ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; unsigned MaxNumSGPRs = ST . getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = AMDGPU :: SGPR_32RegClass . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = AMDGPU :: SGPR_32RegClass . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } unsigned MaxNumVGPRs = ST . getMaxNumVGPRs ( MF ) ; unsigned TotalNumVGPRs = AMDGPU :: VGPR_32RegClass . getNumRegs ( ) ; for ( unsigned i = MaxNumVGPRs ; i < TotalNumVGPRs ; ++ i ) { unsigned Reg = AMDGPU :: VGPR_32RegClass . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } const SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , ScratchWaveOffsetReg ) ; } unsigned ScratchRSrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRSrcReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , ScratchRSrcReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , ScratchWaveOffsetReg ) ) ; } unsigned StackPtrReg = MFI -> getStackPtrOffsetReg ( ) ; if ( StackPtrReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , StackPtrReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , StackPtrReg ) ) ; } unsigned FrameReg = MFI -> getFrameOffsetReg ( ) ; if ( FrameReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , FrameReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , FrameReg ) ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> MVT :: SimpleValueType getCmpLibcallReturnType ( ) const override { return MVT :: i16 ; } </s>

Return the ValueType for comparison libcalls .


<s> bool SIFixSGPRCopies :: runOnMachineFunction ( MachineFunction & MF ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const TargetRegisterInfo * TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { MachineInstr & MI = * I ; if ( MI . getOpcode ( ) != AMDGPU :: PHI ) { continue ; } unsigned Reg = MI . getOperand ( 0 ) . getReg ( ) ; const TargetRegisterClass * RC = inferRegClass ( TRI , MRI , Reg ) ; if ( TRI -> getCommonSubClass ( RC , & AMDGPU :: VReg_32RegClass ) ) { MRI . constrainRegClass ( Reg , & AMDGPU :: VReg_32RegClass ) ; } } } return false ; } </s>

runOnMachineFunction - Emit the function body .


<s>
void
BT
::
run
(
)
{
reset
(
)
;
assert
(
FlowQ
.
empty
(
)
)
;
using
MachineFlowGraphTraits
=
GraphTraits
<
const
MachineFunction
*
>
;
const
MachineBasicBlock
*
Entry
=
MachineFlowGraphTraits
::
getEntryNode
(
&
MF
)
;
unsigned
MaxBN
=
0
;
for
(
const
MachineBasicBlock
&
B
:
MF
)
{
assert
(
B
.
getNumber
(
)
>=
0
&&
"Disconnected block"
)
;
unsigned
BN
=
B
.
getNumber
(
)
;
if
(
BN
>
MaxBN
)
MaxBN
=
BN
;
}
BitVector
BlockScanned
(
MaxBN
+
1
)
;
int
EntryN
=
Entry
->
getNumber
(
)
;
FlowQ
.
push
(
CFGEdge
(
1
,
EntryN
)
)
;
while
(
!
FlowQ
.
empty
(
)
||
!
UseQ
.
empty
(
)
)
{
runEdgeQueue
(
BlockScanned
)
;
runUseQueue
(
)
;
}
if
(
Trace
)
print_cells
(
dbgs
(
)
<<
"Cells after propagation:\n"
)
;
}
</s>

Run the analysis pass over a function and produce a dominator tree .


<s> bool HexagonTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { EVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == ISD :: SEXTLOAD ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; if ( ST -> getValue ( ) . getValueType ( ) == MVT :: i64 && ST -> isTruncatingStore ( ) ) { return false ; } } else { return false ; } bool isInc = false ; bool isLegal = getIndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; int ShiftAmount = VT . getSizeInBits ( ) / 16 ; if ( isLegal && Is_PostInc_S4_Offset ( Offset . getNode ( ) , ShiftAmount ) ) { AM = isInc ? ISD :: POST_INC : ISD :: POST_DEC ; return true ; } return false ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .


<s>
const
TargetRegisterClass
*
MCS51RegisterInfo
::
getLargestLegalSuperClass
(
const
TargetRegisterClass
*
RC
,
const
MachineFunction
&
MF
)
const
{
const
TargetRegisterInfo
*
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
if
(
TRI
->
isTypeLegalForClass
(
*
RC
,
MVT
::
i16
)
)
{
return
&
MCS51
::
DREGSRegClass
;
}
if
(
TRI
->
isTypeLegalForClass
(
*
RC
,
MVT
::
i8
)
)
{
return
&
MCS51
::
GPR8RegClass
;
}
llvm_unreachable
(
"Invalid register size"
)
;
}
</s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .


<s> bool MipsPassConfig :: addPreEmitPass ( ) { MipsTargetMachine & TM = getMipsTargetMachine ( ) ; addPass ( createMipsDelaySlotFillerPass ( TM ) ) ; if ( TM . getSubtarget < MipsSubtarget > ( ) . hasStandardEncoding ( ) ) addPass ( createMipsLongBranchPass ( TM ) ) ; if ( TM . getSubtarget < MipsSubtarget > ( ) . inMips16Mode ( ) ) addPass ( createMipsConstantIslandPass ( TM ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips


<s>
bool
HexagonPacketizer
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MF
.
getProperties
(
)
.
set
(
MachineFunctionProperties
::
Property
::
FailsVerification
)
;
auto
&
HST
=
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
;
HII
=
HST
.
getInstrInfo
(
)
;
HRI
=
HST
.
getRegisterInfo
(
)
;
auto
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
auto
*
AA
=
&
getAnalysis
<
AAResultsWrapperPass
>
(
)
.
getAAResults
(
)
;
auto
*
MBPI
=
&
getAnalysis
<
MachineBranchProbabilityInfo
>
(
)
;
if
(
EnableGenAllInsnClass
)
HII
->
genAllInsnTimingClasses
(
MF
)
;
bool
MinOnly
=
Minimal
||
DisablePacketizer
||
!
HST
.
usePackets
(
)
||
skipFunction
(
MF
.
getFunction
(
)
)
;
HexagonPacketizerList
Packetizer
(
MF
,
MLI
,
AA
,
MBPI
,
MinOnly
)
;
assert
(
Packetizer
.
getResourceTracker
(
)
&&
"Empty DFA table!"
)
;
for
(
MachineBasicBlock
&
MB
:
MF
)
{
for
(
MachineInstr
&
MI
:
llvm
::
make_early_inc_range
(
MB
)
)
if
(
MI
.
isKill
(
)
)
MB
.
erase
(
&
MI
)
;
}
if
(
HST
.
isTinyCoreWithDuplex
(
)
)
HII
->
translateInstrsForDup
(
MF
,
true
)
;
for
(
auto
&
MB
:
MF
)
{
auto
Begin
=
MB
.
begin
(
)
,
End
=
MB
.
end
(
)
;
while
(
Begin
!=
End
)
{
MachineBasicBlock
::
iterator
RB
=
Begin
;
while
(
RB
!=
End
&&
HII
->
isSchedulingBoundary
(
*
RB
,
&
MB
,
MF
)
)
++
RB
;
MachineBasicBlock
::
iterator
RE
=
RB
;
while
(
RE
!=
End
&&
!
HII
->
isSchedulingBoundary
(
*
RE
,
&
MB
,
MF
)
)
++
RE
;
if
(
RE
!=
End
)
++
RE
;
if
(
RB
!=
End
)
Packetizer
.
PacketizeMIs
(
&
MB
,
RB
,
RE
)
;
Begin
=
RE
;
}
}
if
(
HST
.
isTinyCoreWithDuplex
(
)
)
HII
->
translateInstrsForDup
(
MF
,
false
)
;
Packetizer
.
unpacketizeSoloInstrs
(
MF
)
;
return
true
;
}
</s>

Hexagon
Hexagon
Hexagon
Hexagon
"Empty DFA table!"


<s> static void eco32_function_arg_advance ( cumulative_args_t cum , enum machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { * get_cumulative_args ( cum ) += eco32_num_arg_regs ( mode , type ) ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> bool AArch64TargetLowering :: allowsMisalignedMemoryAccesses ( LLT Ty , unsigned AddrSpace , Align Alignment , MachineMemOperand :: Flags Flags , bool * Fast ) const { if ( Subtarget -> requiresStrictAlign ( ) ) return false ; if ( Fast ) { * Fast = ! Subtarget -> isMisaligned128StoreSlow ( ) || Ty . getSizeInBytes ( ) != 16 || Alignment <= 2 || Ty == LLT :: fixed_vector ( 2 , 64 ) ; } return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"R600 Emit Clause Markers Pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool X86InstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Cond , unsigned TrueReg , unsigned FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( ! Subtarget . hasCMov ( ) ) return false ; if ( Cond . size ( ) != 1 ) return false ; if ( ( X86 :: CondCode ) Cond [ 0 ] . getImm ( ) > X86 :: LAST_VALID_COND ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( X86 :: GR16RegClass . hasSubClassEq ( RC ) || X86 :: GR32RegClass . hasSubClassEq ( RC ) || X86 :: GR64RegClass . hasSubClassEq ( RC ) ) { CondCycles = 2 ; TrueCycles = 2 ; FalseCycles = 2 ; return true ; } return false ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> void SystemZHazardRecognizer :: Reset ( ) { CurrGroupSize = 0 ; clearProcResCounters ( ) ; GrpCount = 0 ; LastFPdOpCycleIdx = UINT_MAX ; DEBUG ( CurGroupDbg = "" ; ) ; } </s>


<s> static rtx aarch64_emit_move ( rtx dest , rtx src ) { return ( can_create_pseudo_p ( ) ? emit_move_insn ( dest , src ) : emit_move_insn_1 ( dest , src ) ) ; } </s>

Emit a move from SRC to DEST . Assume that the move expanders can handle all moves if ! can_create_pseudo_p ( ) . The distinction is important because , unlike emit_move_insn , the move expanders know how to force Pmode objects into the constant pool even when the constant pool address is not itself legitimate .


<s>
const
char
*
output_v8plus_mult
(
rtx_insn
*
insn
,
rtx
*
operands
,
const
char
*
opcode
)
{
char
mulstr
[
32
]
;
gcc_assert
(
!
TARGET_ARCH64
)
;
if
(
sparc_check_64
(
operands
[
1
]
,
insn
)
<=
0
)
output_asm_insn
(
"srl\t%L1, 0, %L1"
,
operands
)
;
if
(
which_alternative
==
1
)
output_asm_insn
(
"sllx\t%H1, 32, %H1"
,
operands
)
;
if
(
GET_CODE
(
operands
[
2
]
)
==
CONST_INT
)
{
if
(
which_alternative
==
1
)
{
output_asm_insn
(
"or\t%L1, %H1, %H1"
,
operands
)
;
sprintf
(
mulstr
,
"%s\t%%H1, %%2, %%L0"
,
opcode
)
;
output_asm_insn
(
mulstr
,
operands
)
;
return
"srlx\t%L0, 32, %H0"
;
}
else
{
output_asm_insn
(
"sllx\t%H1, 32, %3"
,
operands
)
;
output_asm_insn
(
"or\t%L1, %3, %3"
,
operands
)
;
sprintf
(
mulstr
,
"%s\t%%3, %%2, %%3"
,
opcode
)
;
output_asm_insn
(
mulstr
,
operands
)
;
output_asm_insn
(
"srlx\t%3, 32, %H0"
,
operands
)
;
return
"mov\t%3, %L0"
;
}
}
else
if
(
rtx_equal_p
(
operands
[
1
]
,
operands
[
2
]
)
)
{
if
(
which_alternative
==
1
)
{
output_asm_insn
(
"or\t%L1, %H1, %H1"
,
operands
)
;
sprintf
(
mulstr
,
"%s\t%%H1, %%H1, %%L0"
,
opcode
)
;
output_asm_insn
(
mulstr
,
operands
)
;
return
"srlx\t%L0, 32, %H0"
;
}
else
{
output_asm_insn
(
"sllx\t%H1, 32, %3"
,
operands
)
;
output_asm_insn
(
"or\t%L1, %3, %3"
,
operands
)
;
sprintf
(
mulstr
,
"%s\t%%3, %%3, %%3"
,
opcode
)
;
output_asm_insn
(
mulstr
,
operands
)
;
output_asm_insn
(
"srlx\t%3, 32, %H0"
,
operands
)
;
return
"mov\t%3, %L0"
;
}
}
if
(
sparc_check_64
(
operands
[
2
]
,
insn
)
<=
0
)
output_asm_insn
(
"srl\t%L2, 0, %L2"
,
operands
)
;
if
(
which_alternative
==
1
)
{
output_asm_insn
(
"or\t%L1, %H1, %H1"
,
operands
)
;
output_asm_insn
(
"sllx\t%H2, 32, %L1"
,
operands
)
;
output_asm_insn
(
"or\t%L2, %L1, %L1"
,
operands
)
;
sprintf
(
mulstr
,
"%s\t%%H1, %%L1, %%L0"
,
opcode
)
;
output_asm_insn
(
mulstr
,
operands
)
;
return
"srlx\t%L0, 32, %H0"
;
}
else
{
output_asm_insn
(
"sllx\t%H1, 32, %3"
,
operands
)
;
output_asm_insn
(
"sllx\t%H2, 32, %4"
,
operands
)
;
output_asm_insn
(
"or\t%L1, %3, %3"
,
operands
)
;
output_asm_insn
(
"or\t%L2, %4, %4"
,
operands
)
;
sprintf
(
mulstr
,
"%s\t%%3, %%4, %%3"
,
opcode
)
;
output_asm_insn
(
mulstr
,
operands
)
;
output_asm_insn
(
"srlx\t%3, 32, %H0"
,
operands
)
;
return
"mov\t%3, %L0"
;
}
}
</s>

Output a wide multiply instruction in V8+ mode . INSN is the instruction , OPERANDS are its operands and OPCODE is the mnemonic to be used .


<s> static void do_ifelse ( machine_mode cmpmode , rtx_code comparison , rtx a , rtx b , rtx cr , rtx true_label ) { gcc_assert ( ( a == NULL_RTX && b == NULL_RTX && cr != NULL_RTX ) || ( a != NULL_RTX && b != NULL_RTX ) ) ; if ( cr != NULL_RTX ) gcc_assert ( GET_MODE ( cr ) == cmpmode ) ; else cr = gen_reg_rtx ( cmpmode ) ; rtx label_ref = gen_rtx_LABEL_REF ( VOIDmode , true_label ) ; if ( a != NULL_RTX ) emit_move_insn ( cr , gen_rtx_COMPARE ( cmpmode , a , b ) ) ; rtx cmp_rtx = gen_rtx_fmt_ee ( comparison , VOIDmode , cr , const0_rtx ) ; rtx ifelse = gen_rtx_IF_THEN_ELSE ( VOIDmode , cmp_rtx , label_ref , pc_rtx ) ; rtx j = emit_jump_insn ( gen_rtx_SET ( pc_rtx , ifelse ) ) ; JUMP_LABEL ( j ) = true_label ; LABEL_NUSES ( true_label ) += 1 ; } </s>

Do a branch for an if/else decision . CMPMODE is the mode to use for the comparison . COMPARISON is the rtx code for the compare needed . A is the first thing to be compared . B is the second thing to be compared . CR is the condition code reg input , or NULL_RTX . TRUE_LABEL is the label to branch to if the condition is true . The return value is the CR used for the comparison . If CR is null_rtx , then a new register of CMPMODE is generated . If A and B are both null_rtx , then CR must not be null , and the compare is not generated so you can use this with a dot form insn .


<s> static const char * m68hc11_strip_name_encoding ( const char * str ) { return str + ( * str == '*' || * str == '@' || * str == '&' ) ; } </s>


<s> bool SILowerControlFlowPass :: runOnMachineFunction ( MachineFunction & MF ) { bool HaveKill = false ; unsigned Depth = 0 ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , Next = llvm :: next ( I ) ; I != MBB . end ( ) ; I = Next ) { Next = llvm :: next ( I ) ; MachineInstr & MI = * I ; switch ( MI . getOpcode ( ) ) { default : break ; case AMDGPU :: SI_IF : ++ Depth ; If ( MI ) ; break ; case AMDGPU :: SI_ELSE : Else ( MI ) ; break ; case AMDGPU :: SI_BREAK : Break ( MI ) ; break ; case AMDGPU :: SI_IF_BREAK : IfBreak ( MI ) ; break ; case AMDGPU :: SI_ELSE_BREAK : ElseBreak ( MI ) ; break ; case AMDGPU :: SI_LOOP : ++ Depth ; Loop ( MI ) ; break ; case AMDGPU :: SI_END_CF : if ( -- Depth == 0 && HaveKill ) { SkipIfDead ( MI ) ; HaveKill = false ; } EndCf ( MI ) ; break ; case AMDGPU :: SI_KILL : if ( Depth == 0 ) SkipIfDead ( MI ) ; else HaveKill = true ; Kill ( MI ) ; break ; case AMDGPU :: S_BRANCH : Branch ( MI ) ; break ; } } } return true ; } </s>


<s> void AVRPassConfig :: addPreSched2 ( ) { addPass ( createAVRExpandPseudoPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> OperandMatchResultTy CSKYAsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { const AsmToken & Tok = getParser ( ) . getTok ( ) ; StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( matchRegisterNameHelper ( ( MCRegister & ) RegNo , Name ) ) return MatchOperand_NoMatch ; getParser ( ) . Lex ( ) ; return MatchOperand_Success ; } </s>

tryParseRegister - parse one register if possible


<s> static bool m32c_function_needs_enter ( void ) { rtx_insn * insn ; struct sequence_stack * seq ; rtx sp = gen_rtx_REG ( Pmode , SP_REGNO ) ; rtx fb = gen_rtx_REG ( Pmode , FB_REGNO ) ; insn = get_insns ( ) ; for ( seq = crtl -> emit . sequence_stack ; seq ; insn = seq -> first , seq = seq -> next ) ; while ( insn ) { if ( reg_mentioned_p ( sp , insn ) ) return true ; if ( reg_mentioned_p ( fb , insn ) ) return true ; insn = NEXT_INSN ( insn ) ; } return false ; } </s>

Returns TRUE if the current function needs to use the ENTER/EXIT opcodes . If the function does n't need the frame base or stack pointer , it can use the simpler RTS opcode .


<s>
bool
PIC16AsmPrinter
::
doInitialization
(
Module
&
M
)
{
bool
Result
=
AsmPrinter
::
doInitialization
(
M
)
;
OutStreamer
.
EmitRawText
(
StringRef
(
"\n#include p16f1xxx.inc"
)
)
;
OutStreamer
.
EmitRawText
(
StringRef
(
"#include stdmacros.inc"
)
)
;
for
(
Module
::
global_iterator
I
=
M
.
global_begin
(
)
,
E
=
M
.
global_end
(
)
;
I
!=
E
;
++
I
)
{
if
(
I
->
isDeclaration
(
)
)
{
ExternalVarDecls
.
push_back
(
I
)
;
continue
;
}
if
(
I
->
hasExternalLinkage
(
)
||
I
->
hasCommonLinkage
(
)
)
{
ExternalVarDefs
.
push_back
(
I
)
;
}
if
(
!
I
->
hasAvailableExternallyLinkage
(
)
)
{
const
MCSection
*
S
=
getObjFileLowering
(
)
.
SectionForGlobal
(
I
,
Mang
,
TM
)
;
I
->
setSection
(
(
(
const
PIC16Section
*
)
S
)
->
getName
(
)
)
;
}
}
DbgInfo
.
BeginModule
(
M
)
;
EmitFunctionDecls
(
M
)
;
EmitUndefinedVars
(
M
)
;
EmitDefinedVars
(
M
)
;
EmitIData
(
M
)
;
EmitUData
(
M
)
;
EmitRomData
(
M
)
;
EmitSharedUdata
(
M
)
;
EmitUserSections
(
M
)
;
return
Result
;
}
</s>

Set up the AsmPrinter when we are working on a new module .


<s> bool MCS51FrameLowering :: canSimplifyCallFramePseudos ( const MachineFunction & MF ) const { return true ; } </s>

canSimplifyCallFramePseudos - If there is a reserved call frame , the call frame pseudos can be simplified .


<s> bool AVRTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { int64_t Offs = AM . BaseOffs ; if ( AM . BaseGV && ! AM . HasBaseReg && AM . Scale == 0 && Offs == 0 ) { return true ; } if ( isa < PointerType > ( Ty ) && AS == AVR :: ProgramMemory ) { return false ; } if ( Offs < 0 ) Offs = - Offs ; if ( AM . BaseGV == nullptr && AM . HasBaseReg && AM . Scale == 0 && isUInt < 6 > ( Offs ) ) { return true ; } return false ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


"%Klane index must be a constant immediate"

Expand a Neon builtin , i.e . those registered only if TARGET_NEON holds . Most of these are `` special '' because they do n't have symbolic constants defined per-instruction or per instruction-variant . Instead , the required info is looked up in the table neon_builtin_data .


<s> void MOSRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator MI , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { MachineFunction & MF = * MI -> getMF ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; assert ( ! SPAdj ) ; int Idx = MI -> getOperand ( FIOperandNum ) . getIndex ( ) ; int64_t Offset = MFI . getObjectOffset ( Idx ) ; if ( FIOperandNum + 1 < MI -> getNumOperands ( ) && MI -> getOperand ( FIOperandNum + 1 ) . isImm ( ) ) Offset += MI -> getOperand ( FIOperandNum + 1 ) . getImm ( ) ; else Offset += MI -> getOperand ( FIOperandNum ) . getOffset ( ) ; if ( MFI . getStackID ( Idx ) == TargetStackID :: Default ) { Offset += MFI . getStackSize ( ) ; } switch ( MI -> getOpcode ( ) ) { default : MI -> getOperand ( FIOperandNum ) . ChangeToTargetIndex ( MOS :: TI_STATIC_STACK , Offset , MI -> getOperand ( FIOperandNum ) . getTargetFlags ( ) ) ; break ; case MOS :: AddrLostk : case MOS :: AddrHistk : case MOS :: LDStk : case MOS :: STStk : MI -> getOperand ( FIOperandNum ) . ChangeToRegister ( getFrameRegister ( MF ) , false ) ; MI -> getOperand ( FIOperandNum + 1 ) . setImm ( Offset ) ; break ; } switch ( MI -> getOpcode ( ) ) { default : break ; case MOS :: AddrLostk : expandAddrLostk ( MI ) ; break ; case MOS :: AddrHistk : expandAddrHistk ( MI ) ; break ; case MOS :: LDStk : case MOS :: STStk : expandLDSTStk ( MI ) ; break ; } } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .

MOS MOS 1 1 1 MOS::TI_STATIC_STACK MOS::AddrLostk MOS::AddrHistk MOS::LDStk MOS::STStk 1 MOS::AddrLostk MOS::AddrHistk MOS::LDStk MOS::STStk


"Do not know how to return this many arguments!"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s>
static
void
output_reg_adjust
(
rtx
reg
,
int
n
)
{
const
char
*
s
;
gcc_assert
(
GET_MODE
(
reg
)
==
SImode
&&
n
>=
12
&&
n
!=
0
&&
n
<=
12
)
;
switch
(
n
)
{
case
12
:
s
=
"add%.l #12,%0"
;
break
;
case
8
:
s
=
"addq%.l #8,%0"
;
break
;
case
4
:
s
=
"addq%.l #4,%0"
;
break
;
case
12
:
s
=
"sub%.l #12,%0"
;
break
;
case
8
:
s
=
"subq%.l #8,%0"
;
break
;
case
4
:
s
=
"subq%.l #4,%0"
;
break
;
default
:
gcc_unreachable
(
)
;
s
=
;
}
output_asm_insn
(
s
,
&
reg
)
;
}
</s>

Output assembler code to adjust REG by N .


<s>
static
void
init_device
(
)
{
init_hsa_runtime_functions
(
)
;
XHSA
(
hsa_fns
.
hsa_init_fn
(
)
,
"Initialize run-time"
)
;
XHSA_CMP
(
hsa_fns
.
hsa_iterate_agents_fn
(
get_gpu_agent
,
)
,
status
==
HSA_STATUS_SUCCESS
||
status
==
HSA_STATUS_INFO_BREAK
,
"Find a device"
)
;
uint32_t
queue_size
=
0
;
XHSA
(
hsa_fns
.
hsa_agent_get_info_fn
(
device
,
HSA_AGENT_INFO_QUEUE_MAX_SIZE
,
&
queue_size
)
,
"Find max queue size"
)
;
XHSA
(
hsa_fns
.
hsa_queue_create_fn
(
device
,
queue_size
,
HSA_QUEUE_TYPE_SINGLE
,
,
,
UINT32_MAX
,
UINT32_MAX
,
&
queue
)
,
"Set up a device queue"
)
;
XHSA_CMP
(
hsa_fns
.
hsa_agent_iterate_regions_fn
(
device
,
get_kernarg_region
,
)
,
status
==
HSA_STATUS_SUCCESS
||
status
==
HSA_STATUS_INFO_BREAK
,
"Locate kernargs memory"
)
;
}
</s>

Initialize the HSA Runtime library and GPU device .

gcn
"Initialize run-time"
"Find a device"
0
"Find max queue size"
"Set up a device queue"
"Locate kernargs memory"


"MMIX Internal: Last named vararg would not fit in a register"


<s> void PPCRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { unsigned ADDriOpc = Subtarget . isPPC64 ( ) ? PPC :: ADDI8 : PPC :: ADDI ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , 0 , this , MF ) ) ; BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .


<s> const TargetRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static struct unw_reg_state * dup_state_stack ( struct unw_reg_state * rs ) { struct unw_reg_state * copy , * prev = NULL , * first = NULL ; while ( rs ) { copy = alloc_reg_state ( ) ; memcpy ( copy , rs , sizeof ( * copy ) ) ; if ( first ) prev -> next = copy ; else first = copy ; rs = rs -> next ; prev = copy ; } return first ; } </s>

Make a copy of the state stack . Non-recursive to avoid stack overflows .


<s> static int mergeSPUpdates ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , bool doMergeWithPrevious ) { if ( ( doMergeWithPrevious && MBBI == MBB . begin ( ) ) || ( ! doMergeWithPrevious && MBBI == MBB . end ( ) ) ) return 0 ; MachineBasicBlock :: iterator PI = doMergeWithPrevious ? prior ( MBBI ) : MBBI ; MachineBasicBlock :: iterator NI = doMergeWithPrevious ? 0 : llvm :: next ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = 0 ; if ( ( Opc == X86 :: ADD64ri32 || Opc == X86 :: ADD64ri8 || Opc == X86 :: ADD32ri || Opc == X86 :: ADD32ri8 || Opc == X86 :: LEA32r || Opc == X86 :: LEA64_32r ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { Offset += PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == X86 :: SUB64ri32 || Opc == X86 :: SUB64ri8 || Opc == X86 :: SUB32ri || Opc == X86 :: SUB32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { Offset -= PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } return Offset ; } </s>

Check the instruction before/after the passed instruction .


<s> void MOSAsmBackend :: relaxInstruction ( MCInst & Inst , const MCSubtargetInfo & STI ) const { unsigned Opcode = relaxInstructionTo ( Inst , STI ) ; if ( Opcode != 0 ) { Inst . setOpcode ( Opcode ) ; } } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> static bool rx_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { if ( decl == NULL ) return false ; if ( is_fast_interrupt_func ( NULL_TREE ) || is_interrupt_func ( NULL_TREE ) || is_naked_func ( NULL_TREE ) ) return false ; return true ; } </s>

Return nonzero if it is ok to make a tail-call to DECL , a function_decl or NULL if this is an indirect call , using EXP


<s> bool X86FastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { X86AddressMode AM ; if ( ! X86SelectAddress ( LI -> getOperand ( 0 ) , AM ) ) return false ; const X86InstrInfo & XII = ( const X86InstrInfo & ) TII ; unsigned Size = TD . getTypeAllocSize ( LI -> getType ( ) ) ; unsigned Alignment = LI -> getAlignment ( ) ; SmallVector < MachineOperand , 8 > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , MI , OpNo , AddrOps , Size , Alignment ) ; if ( Result == 0 ) return false ; FuncInfo . MBB -> insert ( FuncInfo . InsertPt , Result ) ; MI -> eraseFromParent ( ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> SDValue PPCTargetLowering :: getRecipEstimate ( SDValue Operand , SelectionDAG & DAG , int Enabled , int & RefinementSteps ) const { EVT VT = Operand . getValueType ( ) ; if ( ( VT == MVT :: f32 && Subtarget . hasFRES ( ) ) || ( VT == MVT :: f64 && Subtarget . hasFRE ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasAltivec ( ) ) || ( VT == MVT :: v2f64 && Subtarget . hasVSX ( ) ) ) { if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = getEstimateRefinementSteps ( VT , Subtarget ) ; return DAG . getNode ( PPCISD :: FRE , SDLoc ( Operand ) , VT , Operand ) ; } return SDValue ( ) ; } </s>

Return a reciprocal estimate value for the input operand .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Alpha Machine Code Emitter"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static void aarch64_analyze_bb_vinfo ( bb_vec_info bb_vinfo , aarch64_vector_costs * costs ) { costs -> vec_flags = aarch64_classify_vector_mode ( bb_vinfo -> vector_mode ) ; } </s>

Do one-time initialization of COSTS given that we 're costing the block vectorization described by BB_VINFO .


<s> void ix86_expand_reduc_v4sf ( rtx ( * fn ) ( rtx , rtx , rtx ) , rtx dest , rtx in ) { rtx tmp1 , tmp2 , tmp3 ; tmp1 = gen_reg_rtx ( V4SFmode ) ; tmp2 = gen_reg_rtx ( V4SFmode ) ; tmp3 = gen_reg_rtx ( V4SFmode ) ; emit_insn ( gen_sse_movhlps ( tmp1 , in , in ) ) ; emit_insn ( fn ( tmp2 , tmp1 , in ) ) ; emit_insn ( gen_sse_shufps_1 ( tmp3 , tmp2 , tmp2 , GEN_INT ( 1 ) , GEN_INT ( 1 ) , GEN_INT ( 1 + 4 ) , GEN_INT ( 1 + 4 ) ) ) ; emit_insn ( fn ( dest , tmp2 , tmp3 ) ) ; } </s>

Expand a vector reduction on V4SFmode for SSE1 . FN is the binary pattern to reduce ; DEST is the destination ; IN is the input vector .


<s> bool WebAssembly :: mayThrow ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { case WebAssembly :: THROW : case WebAssembly :: THROW_S : case WebAssembly :: RETHROW : case WebAssembly :: RETHROW_S : return true ; } if ( isCallIndirect ( MI . getOpcode ( ) ) ) return true ; if ( ! MI . isCall ( ) ) return false ; const MachineOperand & MO = MI . getOperand ( getCalleeOpNo ( MI . getOpcode ( ) ) ) ; assert ( MO . isGlobal ( ) || MO . isSymbol ( ) ) ; if ( MO . isSymbol ( ) ) { const char * Name = MO . getSymbolName ( ) ; if ( strcmp ( Name , "memcpy" ) == 0 || strcmp ( Name , "memmove" ) == 0 || strcmp ( Name , "memset" ) == 0 ) return false ; return true ; } const auto * F = dyn_cast < Function > ( MO . getGlobal ( ) ) ; if ( ! F ) return true ; if ( F -> doesNotThrow ( ) ) return false ; if ( F -> getName ( ) == CxaBeginCatchFn || F -> getName ( ) == PersonalityWrapperFn || F -> getName ( ) == ClangCallTerminateFn || F -> getName ( ) == StdTerminateFn ) return false ; return true ; } </s>

Return true if this instruction may throw an exception .


<s> void DCPU16InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> void AArch64PassConfig :: addPreEmitPass ( ) { if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Aggressive && EnableLoadStoreOpt ) addPass ( createAArch64LoadStoreOptimizationPass ( ) ) ; if ( EnableA53Fix835769 ) addPass ( createAArch64A53Fix835769 ( ) ) ; if ( EnableBranchTargets ) addPass ( createAArch64BranchTargetsPass ( ) ) ; if ( BranchRelaxation ) addPass ( & BranchRelaxationPassID ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardLongjmpPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCompressJumpTables ) addPass ( createAArch64CompressJumpTablesPass ( ) ) ; addPass ( createAArch64ExpandHardenedPseudosPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; addPass ( createUnpackMachineBundles ( nullptr ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static const char * mips_get_compress_off_name ( unsigned int flags ) { if ( flags == MASK_MIPS16 ) return "nomips16" ; if ( flags == MASK_MICROMIPS ) return "nomicromips" ; return "nocompression" ; } </s>

Return the attribute name that forbids MASK_MIPS16 and MASK_MICROMIPS flags FLAGS .

mips "nomips16" "nomicromips" "nocompression"


<s> void HSAILPassConfig :: addPreRegAlloc ( ) { } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static bool rs6000_must_pass_in_stack ( machine_mode mode , const_tree type ) { if ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT ) return must_pass_in_stack_var_size ( mode , type ) ; else return must_pass_in_stack_var_size_or_pad ( mode , type ) ; } </s>

Return true if TYPE must be passed on the stack and not in registers .


"Only Linux target is expected to contain LOAD_STACK_GUARD"

This function is called for all pseudo instructions that remain after register allocation .


"-fpic and -fPIC not supported without -mdsbt on this target"


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittleEndian ? i : ( NumBytes - 1 - i ) ; Data [ Offset + i ] |= uint8_t ( ( Value >> ( Idx * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void addImm ( int64_t imm ) { Imm += imm ; } </s>


<s>
void
AArch64TargetLowering
::
computeKnownBitsForTargetNode
(
const
SDValue
Op
,
KnownBits
&
Known
,
const
APInt
&
DemandedElts
,
const
SelectionDAG
&
DAG
,
unsigned
Depth
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
break
;
case
AArch64ISD
::
CSEL
:
{
KnownBits
Known2
;
Known
=
DAG
.
computeKnownBits
(
Op
->
getOperand
(
0
)
,
Depth
+
1
)
;
Known2
=
DAG
.
computeKnownBits
(
Op
->
getOperand
(
1
)
,
Depth
+
1
)
;
Known
.
Zero
&=
Known2
.
Zero
;
Known
.
One
&=
Known2
.
One
;
break
;
}
case
AArch64ISD
::
LOADgot
:
case
AArch64ISD
::
ADDlow
:
{
if
(
!
Subtarget
->
isTargetILP32
(
)
)
break
;
Known
.
Zero
=
APInt
::
getHighBitsSet
(
64
,
32
)
;
break
;
}
case
ISD
::
INTRINSIC_W_CHAIN
:
{
ConstantSDNode
*
CN
=
cast
<
ConstantSDNode
>
(
Op
->
getOperand
(
1
)
)
;
Intrinsic
::
ID
IntID
=
static_cast
<
Intrinsic
::
ID
>
(
CN
->
getZExtValue
(
)
)
;
switch
(
IntID
)
{
default
:
return
;
case
Intrinsic
::
aarch64_ldaxr
:
case
Intrinsic
::
aarch64_ldxr
:
{
unsigned
BitWidth
=
Known
.
getBitWidth
(
)
;
EVT
VT
=
cast
<
MemIntrinsicSDNode
>
(
Op
)
->
getMemoryVT
(
)
;
unsigned
MemBits
=
VT
.
getScalarSizeInBits
(
)
;
Known
.
Zero
|=
APInt
::
getHighBitsSet
(
BitWidth
,
BitWidth
MemBits
)
;
return
;
}
}
break
;
}
case
ISD
::
INTRINSIC_WO_CHAIN
:
case
ISD
::
INTRINSIC_VOID
:
{
unsigned
IntNo
=
cast
<
ConstantSDNode
>
(
Op
.
getOperand
(
0
)
)
->
getZExtValue
(
)
;
switch
(
IntNo
)
{
default
:
break
;
case
Intrinsic
::
aarch64_neon_umaxv
:
case
Intrinsic
::
aarch64_neon_uminv
:
{
MVT
VT
=
Op
.
getOperand
(
1
)
.
getValueType
(
)
.
getSimpleVT
(
)
;
unsigned
BitWidth
=
Known
.
getBitWidth
(
)
;
if
(
VT
==
MVT
::
v8i8
||
VT
==
MVT
::
v16i8
)
{
assert
(
BitWidth
>=
8
&&
"Unexpected width!"
)
;
APInt
Mask
=
APInt
::
getHighBitsSet
(
BitWidth
,
BitWidth
8
)
;
Known
.
Zero
|=
Mask
;
}
else
if
(
VT
==
MVT
::
v4i16
||
VT
==
MVT
::
v8i16
)
{
assert
(
BitWidth
>=
16
&&
"Unexpected width!"
)
;
APInt
Mask
=
APInt
::
getHighBitsSet
(
BitWidth
,
BitWidth
16
)
;
Known
.
Zero
|=
Mask
;
}
break
;
}
break
;
}
}
}
}
</s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> bool SystemZTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { if ( Subtarget . hasVector ( ) ) VerifyVectorTypes ( Outs ) ; SmallVector < CCValAssign , 16 > RetLocs ; CCState RetCCInfo ( CallConv , isVarArg , MF , RetLocs , Context ) ; return RetCCInfo . CheckReturn ( Outs , RetCC_SystemZ ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .

SystemZ SystemZ ISD::OutputArg 16 SystemZ


<s>
void
OR1KInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
OR1K
::
GPRRegClass
.
contains
(
DestReg
,
SrcReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
OR1K
::
ORI
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
0
)
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
</s>


<s> void PPCPassConfig :: addPreEmitPass ( ) { addPass ( createPPCPreEmitPeepholePass ( ) ) ; addPass ( createPPCExpandISELPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCEarlyReturnPass ( ) ) ; addPass ( createPPCBranchSelectionPass ( ) ) ; } </s>


<s> MachineInstr * SIInstrInfo :: commuteInstruction ( MachineInstr * MI , bool NewMI ) const { MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; if ( MI -> getNumOperands ( ) < 3 || ! MI -> getOperand ( 1 ) . isReg ( ) ) return nullptr ; if ( isVOP2 ( MI -> getOpcode ( ) ) && MI -> getOperand ( 1 ) . isReg ( ) && RI . isSGPRClass ( MRI . getRegClass ( MI -> getOperand ( 1 ) . getReg ( ) ) ) ) return nullptr ; if ( ! MI -> getOperand ( 2 ) . isReg ( ) ) { if ( NewMI || MI -> getOperand ( 2 ) . isFPImm ( ) || ( ! isVOP2 ( MI -> getOpcode ( ) ) && ! isVOP3 ( MI -> getOpcode ( ) ) ) ) { return nullptr ; } if ( isVOP3 ( MI -> getOpcode ( ) ) && ( MI -> getOperand ( AMDGPU :: getNamedOperandIdx ( MI -> getOpcode ( ) , AMDGPU :: OpName :: abs ) ) . getImm ( ) || MI -> getOperand ( AMDGPU :: getNamedOperandIdx ( MI -> getOpcode ( ) , AMDGPU :: OpName :: neg ) ) . getImm ( ) ) ) return nullptr ; unsigned Reg = MI -> getOperand ( 1 ) . getReg ( ) ; unsigned SubReg = MI -> getOperand ( 1 ) . getSubReg ( ) ; MI -> getOperand ( 1 ) . ChangeToImmediate ( MI -> getOperand ( 2 ) . getImm ( ) ) ; MI -> getOperand ( 2 ) . ChangeToRegister ( Reg , false ) ; MI -> getOperand ( 2 ) . setSubReg ( SubReg ) ; } else { MI = TargetInstrInfo :: commuteInstruction ( MI , NewMI ) ; } if ( MI ) MI -> setDesc ( get ( commuteOpcode ( MI -> getOpcode ( ) ) ) ) ; return MI ; } </s>

This method commutes the operands of the given machine instruction MI .


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & ) const override { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> unsigned RV16KInstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { if ( BytesRemoved ) * BytesRemoved = 0 ; MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return 0 ; if ( ! I -> getDesc ( ) . isUnconditionalBranch ( ) && ! I -> getDesc ( ) . isConditionalBranch ( ) ) return 0 ; I -> eraseFromParent ( ) ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return 1 ; -- I ; if ( ! I -> getDesc ( ) . isConditionalBranch ( ) ) return 1 ; I -> eraseFromParent ( ) ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; return 2 ; } </s>

Remove the branching code at the end of the specific MBB .


<s> bool hasAndNot ( SDValue Y ) const override { EVT VT = Y . getValueType ( ) ; if ( ! VT . isVector ( ) ) return hasAndNotCompare ( Y ) ; TypeSize TS = VT . getSizeInBits ( ) ; return ! TS . isScalable ( ) && TS . getFixedValue ( ) >= 64 ; } </s>

Return true if the target has a bitwise and-not operation : X = ~A & B This can be used to simplify select or other instructions .