<s>
bool
RISCVAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
if
(
getSTI
(
)
.
getFeatureBits
(
)
[
RISCV
::
FeatureRelax
]
)
{
auto
*
Assembler
=
getTargetStreamer
(
)
.
getStreamer
(
)
.
getAssemblerPtr
(
)
;
if
(
Assembler
!=
nullptr
)
{
RISCVAsmBackend
&
MAB
=
static_cast
<
RISCVAsmBackend
&
>
(
Assembler
->
getBackend
(
)
)
;
MAB
.
setForceRelocs
(
)
;
}
}
Operands
.
push_back
(
RISCVOperand
::
createToken
(
Name
,
NameLoc
,
isRV64
(
)
)
)
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
return
false
;
if
(
parseOperand
(
Operands
,
Name
)
)
return
true
;
unsigned
OperandIdx
=
1
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
getLexer
(
)
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
)
return
true
;
++
OperandIdx
;
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
getParser
(
)
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
getParser
(
)
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

RI5CY
RISCV
RISCV::FeatureRelax
RISCV
RISCV
RISCV
1
"unexpected token"


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: CreateImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ; } </s>


<s> bool GCNPassConfig :: addInstSelector ( ) { AMDGPUPassConfig :: addInstSelector ( ) ; addPass ( & SIFixSGPRCopiesID ) ; addPass ( createSILowerI1CopiesPass ( ) ) ; addPass ( createSIFixupVectorISelPass ( ) ) ; addPass ( createSIAddIMGInitPass ( ) ) ; addPass ( & UnreachableMachineBlockElimID ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static unsigned int h8300_constant_length ( rtx constant ) { if ( GET_CODE ( constant ) == CONST_INT && IN_RANGE ( INTVAL ( constant ) , - 0x8000 , 0x7fff ) ) return 2 ; if ( Pmode == HImode || h8300_tiny_constant_address_p ( constant ) ) return 2 ; return 4 ; } </s>

Return the size of the given address or displacement constant .


<s> bool MipsAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { this -> MF = & MF ; SetupMachineFunction ( MF ) ; EmitConstantPool ( MF . getConstantPool ( ) ) ; EmitJumpTableInfo ( MF . getJumpTableInfo ( ) , MF ) ; O << "\n\n" ; emitFunctionStart ( MF ) ; for ( MachineFunction :: const_iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( I != MF . begin ( ) ) { printBasicBlockLabel ( I , true , true ) ; O << '\n' ; } for ( MachineBasicBlock :: const_iterator II = I -> begin ( ) , E = I -> end ( ) ; II != E ; ++ II ) { printInstruction ( II ) ; ++ EmittedInsts ; } O << '\n' ; } emitFunctionEnd ( MF ) ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s>
static
void
mips_output_cplocal
(
void
)
{
if
(
!
TARGET_EXPLICIT_RELOCS
&&
cfun
->
machine
->
global_pointer
>
0
&&
cfun
->
machine
->
global_pointer
!=
GLOBAL_POINTER_REGNUM
)
output_asm_insn
(
".cplocal %+"
,
0
)
;
}
</s>

If we 're generating n32 or n64 abicalls , and the current function does not use $ 28 as its global pointer , emit a cplocal directive . Use pic_offset_table_rtx as the argument to the directive .


<s> void MOSPassConfig :: addPreEmitPass ( ) { addPass ( & BranchRelaxationPassID ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> AtomicOrdering getOrdering ( ) const { return Ordering ; } </s>

Returns the ordering constraint of this store instruction .


<s> int loongarch_split_const_insns ( rtx x ) { unsigned int low , high ; low = loongarch_const_insns ( loongarch_subword ( x , false ) ) ; high = loongarch_const_insns ( loongarch_subword ( x , true ) ) ; gcc_assert ( low > 0 && high > 0 ) ; return low + high ; } </s>

X is a doubleword constant that can be handled by splitting it into two words and loading each word separately . Return the number of instructions required to do this .


<s>
void
XCoreRegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected"
)
;
MachineInstr
&
MI
=
*
II
;
MachineOperand
&
FrameOp
=
MI
.
getOperand
(
FIOperandNum
)
;
int
FrameIndex
=
FrameOp
.
getIndex
(
)
;
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
const
XCoreInstrInfo
&
TII
=
*
static_cast
<
const
XCoreInstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
const
XCoreFrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
int
Offset
=
MF
.
getFrameInfo
(
)
.
getObjectOffset
(
FrameIndex
)
;
int
StackSize
=
MF
.
getFrameInfo
(
)
.
getStackSize
(
)
;
LLVM_DEBUG
(
errs
(
)
<<
"\nFunction         : "
<<
MF
.
getName
(
)
<<
"\n"
)
;
LLVM_DEBUG
(
errs
(
)
<<
"<--------->\n"
)
;
LLVM_DEBUG
(
MI
.
print
(
errs
(
)
)
)
;
LLVM_DEBUG
(
errs
(
)
<<
"FrameIndex         : "
<<
FrameIndex
<<
"\n"
)
;
LLVM_DEBUG
(
errs
(
)
<<
"FrameOffset        : "
<<
Offset
<<
"\n"
)
;
LLVM_DEBUG
(
errs
(
)
<<
"StackSize          : "
<<
StackSize
<<
"\n"
)
;
Offset
+=
StackSize
;
unsigned
FrameReg
=
getFrameRegister
(
MF
)
;
if
(
MI
.
isDebugValue
(
)
)
{
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
)
;
return
;
}
Offset
+=
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
0
)
;
assert
(
Offset
%
4
==
0
&&
"Misaligned stack offset"
)
;
LLVM_DEBUG
(
errs
(
)
<<
"Offset             : "
<<
Offset
<<
"\n"
<<
"<--------->\n"
)
;
Offset
/=
4
;
unsigned
Reg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
assert
(
XCore
::
GRRegsRegClass
.
contains
(
Reg
)
&&
"Unexpected register operand"
)
;
if
(
TFI
->
hasFP
(
MF
)
)
{
if
(
isImmUs
(
Offset
)
)
InsertFPImmInst
(
II
,
TII
,
Reg
,
FrameReg
,
Offset
)
;
else
InsertFPConstInst
(
II
,
TII
,
Reg
,
FrameReg
,
Offset
,
RS
)
;
}
else
{
if
(
isImmU16
(
Offset
)
)
InsertSPImmInst
(
II
,
TII
,
Reg
,
Offset
)
;
else
InsertSPConstInst
(
II
,
TII
,
Reg
,
Offset
,
RS
)
;
}
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
MBB
.
erase
(
II
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .

XCore
XCore
0
"Unexpected"
XCore
XCore
XCore
"\nFunction         : "
"\n"
"<--------->\n"
"FrameIndex         : "
"\n"
"FrameOffset        : "
"\n"
"StackSize          : "
"\n"
1
1
1
0
4
0
"Misaligned stack offset"
"Offset             : "
"\n"
"<--------->\n"
4
0
XCore::GRRegsRegClass
"Unexpected register operand"


"%qE attribute only applies to variables"

Handle aux attribute . The auxiliary registers are addressed using special instructions lr and sr . The attribute 'aux ' indicates if a variable refers to the aux-regs and what is the register number desired .


<s> void TGSIMCInstPrinter :: printRegName ( raw_ostream & os , unsigned reg ) const { os << getRegisterName ( reg ) ; } </s>


<s> static void emit_csky_regs_pop ( unsigned long mask ) { int num_regs = 0 ; int i , j ; rtx par ; for ( i = 0 ; i < CSKY_NGPR_REGS ; i ++ ) if ( mask & ( 1 << i ) ) num_regs ++ ; gcc_assert ( num_regs && num_regs <= 12 ) ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs + 1 ) ) ; XVECEXP ( par , 0 , 0 ) = ret_rtx ; for ( i = 0 ; i < CSKY_NGPR_REGS ; i ++ ) if ( mask & ( 1 << i ) ) { rtx reg = gen_rtx_REG ( SImode , i ) ; rtx addr = plus_constant ( Pmode , stack_pointer_rtx , 4 * num_regs ) ; rtx tmp = gen_frame_mem ( SImode , gen_rtx_POST_MODIFY ( Pmode , stack_pointer_rtx , addr ) ) ; XVECEXP ( par , 0 , 1 ) = gen_rtx_SET ( reg , gen_rtx_UNSPEC ( SImode , gen_rtvec ( 1 , tmp ) , UNSPEC_PUSHPOP_MULT ) ) ; break ; } for ( j = 2 , i ++ ; j < ( num_regs + 1 ) ; i ++ ) if ( mask & ( 1 << i ) ) { rtx reg = gen_rtx_REG ( SImode , i ) ; XVECEXP ( par , 0 , j ) = gen_rtx_USE ( VOIDmode , reg ) ; j ++ ; } par = emit_jump_insn ( par ) ; } </s>

Generate and emit an insn pattern that we will recognize as a pop_multi . SAVED_REGS_MASK shows which registers need to be restored . Unfortunately , since this insn does not reflect very well the actual semantics of the operation , we need to annotate the insn for the benefit of DWARF2 frame unwind information .


<s> bool canMergeStoresTo ( unsigned AddressSpace , EVT MemVT ) const override { return ( MemVT . getSizeInBits ( ) <= 32 ) ; } </s>

Returns if it 's reasonable to merge stores to MemVT size .


<s> void ia64_expand_vecint_cmov ( rtx operands [ ] ) { machine_mode mode = GET_MODE ( operands [ 0 ] ) ; enum rtx_code code = GET_CODE ( operands [ 3 ] ) ; bool negate ; rtx cmp , x , ot , of ; cmp = gen_reg_rtx ( mode ) ; negate = ia64_expand_vecint_compare ( code , mode , cmp , operands [ 4 ] , operands [ 5 ] ) ; ot = operands [ 1 + negate ] ; of = operands [ 2 - negate ] ; if ( ot == CONST0_RTX ( mode ) ) { if ( of == CONST0_RTX ( mode ) ) { emit_move_insn ( operands [ 0 ] , ot ) ; return ; } x = gen_rtx_NOT ( mode , cmp ) ; x = gen_rtx_AND ( mode , x , of ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , x ) ) ; } else if ( of == CONST0_RTX ( mode ) ) { x = gen_rtx_AND ( mode , cmp , ot ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , x ) ) ; } else { rtx t , f ; t = gen_reg_rtx ( mode ) ; x = gen_rtx_AND ( mode , cmp , operands [ 1 + negate ] ) ; emit_insn ( gen_rtx_SET ( VOIDmode , t , x ) ) ; f = gen_reg_rtx ( mode ) ; x = gen_rtx_NOT ( mode , cmp ) ; x = gen_rtx_AND ( mode , x , operands [ 2 - negate ] ) ; emit_insn ( gen_rtx_SET ( VOIDmode , f , x ) ) ; x = gen_rtx_IOR ( mode , t , f ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , x ) ) ; } } </s>

Emit an integral vector conditional move .


<s>
bool
ARCInstrInfo
::
reverseBranchCondition
(
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
assert
(
(
Cond
.
size
(
)
==
3
)
&&
"Invalid ARC branch condition!"
)
;
Cond
[
2
]
.
setImm
(
getOppositeBranchCondition
(
(
ARCCC
::
CondCode
)
Cond
[
2
]
.
getImm
(
)
)
)
;
return
false
;
}
</s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> bool WebAssembly :: isCatch ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { case WebAssembly :: CATCH_I32 : case WebAssembly :: CATCH_I64 : case WebAssembly :: CATCH_ALL : return true ; default : return false ; } } </s>

Return 'true ' if the clause and index Idx is a catch clause .


<s> bool R600InstrInfo :: PredicateInstruction ( MachineInstr * MI , const SmallVectorImpl < MachineOperand > & Pred ) const { int PIdx = MI -> findFirstPredOperandIdx ( ) ; if ( PIdx != - 1 ) { MachineOperand & PMO = MI -> getOperand ( PIdx ) ; PMO . setReg ( Pred [ 2 ] . getReg ( ) ) ; MachineInstrBuilder MIB ( * MI -> getParent ( ) -> getParent ( ) , MI ) ; MIB . addReg ( AMDGPU :: PREDICATE_BIT , RegState :: Implicit ) ; return true ; } return false ; } </s>

Convert the instruction into a predicated instruction .


<s> static void expand_block_set_2 ( rtx dst , rtx dst_reg , rtx value_rtx , rtx bytes_rtx ) { unsigned HOST_WIDE_INT bytes = UINTVAL ( bytes_rtx ) ; unsigned int rem = bytes % 2 ; value_rtx = convert_to_mode ( Pmode , value_rtx , 1 ) ; emit_library_call ( wrd_memset_libfunc , LCT_NORMAL , VOIDmode , 3 , dst_reg , Pmode , value_rtx , Pmode , convert_to_mode ( TYPE_MODE ( sizetype ) , GEN_INT ( bytes >> 1 ) , TYPE_UNSIGNED ( sizetype ) ) , TYPE_MODE ( sizetype ) ) ; if ( rem == 0 ) return ; dst = replace_equiv_address_nv ( dst , dst_reg ) ; bytes -= rem ; emit_move_insn ( adjust_address_nv ( dst , QImode , bytes ) , convert_to_mode ( QImode , value_rtx , 1 ) ) ; } </s>

Generate a call to a library function to set BYTES_RTX bytes of DST with address DST_REG to VALUE_RTX in 2-byte chunks .


<s> inline static void aarch64_print_hint_for_core ( const char * str ) { aarch64_print_hint_for_core_or_arch ( str , false ) ; } </s>

Print a hint with a suggestion for a core name that most closely resembles what the user passed in STR .


<s> bool ARMTargetLowering :: isTruncateFree ( EVT SrcVT , EVT DstVT ) const { if ( SrcVT . isVector ( ) || DstVT . isVector ( ) || ! SrcVT . isInteger ( ) || ! DstVT . isInteger ( ) ) return false ; unsigned SrcBits = SrcVT . getSizeInBits ( ) ; unsigned DestBits = DstVT . getSizeInBits ( ) ; return ( SrcBits == 64 && DestBits == 32 ) ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s>
SDValue
XCoreTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_XCore
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
if
(
RVLocs
[
i
]
.
isRegLoc
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
XCoreISD
::
RETSP
,
dl
,
MVT
::
Other
,
Chain
,
DAG
.
getConstant
(
0
,
MVT
::
i32
)
,
Flag
)
;
else
return
DAG
.
getNode
(
XCoreISD
::
RETSP
,
dl
,
MVT
::
Other
,
Chain
,
DAG
.
getConstant
(
0
,
MVT
::
i32
)
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> const char * Cpu0TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case Cpu0ISD :: JmpLink : return "Cpu0ISD::JmpLink" ; case Cpu0ISD :: TailCall : return "Cpu0ISD::TailCall" ; case Cpu0ISD :: Hi : return "Cpu0ISD::Hi" ; case Cpu0ISD :: Lo : return "Cpu0ISD::Lo" ; case Cpu0ISD :: GPRel : return "Cpu0ISD::GPRel" ; case Cpu0ISD :: Ret : return "Cpu0ISD::Ret" ; case Cpu0ISD :: EH_RETURN : return "Cpu0ISD::EH_RETURN" ; case Cpu0ISD :: DivRem : return "Cpu0ISD::DivRem" ; case Cpu0ISD :: DivRemU : return "Cpu0ISD::DivRemU" ; case Cpu0ISD :: Wrapper : return "Cpu0ISD::Wrapper" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static int shcompact_byref ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , bool named ) { unsigned HOST_WIDE_INT size ; if ( type ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; if ( cum -> arg_count [ SH_ARG_INT ] < NPARM_REGS ( SImode ) && ( ! named || GET_SH_ARG_CLASS ( mode ) == SH_ARG_INT || ( GET_SH_ARG_CLASS ( mode ) == SH_ARG_FLOAT && cum -> arg_count [ SH_ARG_FLOAT ] >= NPARM_REGS ( SFmode ) ) ) && size > 4 && ! SHCOMPACT_FORCE_ON_STACK ( mode , type ) && ! SH5_WOULD_BE_PARTIAL_NREGS ( * cum , mode , type , named ) ) return size ; else return 0 ; } </s>

Whether an argument must be passed by reference . On SHcompact , we pretend arguments wider than 32-bits that would have been passed in registers are passed by reference , so that an SHmedia trampoline loads them into the full 64-bits registers .


<s> machine_mode select_cc_mode ( enum rtx_code op , rtx x , rtx y ) { if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) { switch ( op ) { case EQ : case NE : case UNORDERED : case ORDERED : case UNLT : case UNLE : case UNGT : case UNGE : case UNEQ : return CCFPmode ; case LT : case LE : case GT : case GE : case LTGT : return CCFPEmode ; default : gcc_unreachable ( ) ; } } else if ( ( GET_CODE ( x ) == PLUS || GET_CODE ( x ) == MINUS || GET_CODE ( x ) == NEG || GET_CODE ( x ) == ASHIFT ) && y == const0_rtx ) { if ( TARGET_ARCH64 && GET_MODE ( x ) == DImode ) return CCXNZmode ; else return CCNZmode ; } else { if ( GET_CODE ( x ) == NOT && y == constm1_rtx ) { if ( TARGET_ARCH64 && GET_MODE ( x ) == DImode ) return CCXCmode ; else return CCCmode ; } if ( ! TARGET_ARCH64 && GET_MODE ( x ) == DImode ) { if ( GET_CODE ( y ) == UNSPEC && ( XINT ( y , 1 ) == UNSPEC_ADDV || XINT ( y , 1 ) == UNSPEC_SUBV || XINT ( y , 1 ) == UNSPEC_NEGV ) ) return CCVmode ; else return CCCmode ; } if ( TARGET_ARCH64 && GET_MODE ( x ) == DImode ) return CCXmode ; else return CCmode ; } } </s>

Given a comparison code ( EQ , NE , etc . ) and the first operand of a COMPARE , return the mode to be used for the comparison . For floating-point , CCFP [ E ] mode is used . CC_NOOVmode should be used when the first operand is a PLUS , MINUS , NEG , or ASHIFT . CCmode should be used when no special processing is needed .


<s> static void sh_function_arg_advance ( cumulative_args_t ca_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * ca = get_cumulative_args ( ca_v ) ; if ( ca -> force_mem ) ca -> force_mem = false ; if ( ( TARGET_HITACHI || ca -> renesas_abi ) && TARGET_FPU_DOUBLE ) { if ( mode == SFmode && ca -> free_single_fp_reg ) { ca -> free_single_fp_reg = 0 ; return ; } if ( mode == DFmode && sh_round_reg ( * ca , DFmode ) != sh_round_reg ( * ca , SFmode ) ) { ca -> free_single_fp_reg = ( sh_round_reg ( * ca , SFmode ) + BASE_ARG_REG ( mode ) ) ; } } if ( ! ( ( TARGET_SH4 || TARGET_SH2A ) || ca -> renesas_abi ) || sh_pass_in_reg_p ( * ca , mode , type ) ) ( ca -> arg_count [ ( int ) get_sh_arg_class ( mode ) ] = ( sh_round_reg ( * ca , mode ) + ( mode == BLKmode ? CEIL ( int_size_in_bytes ( type ) , UNITS_PER_WORD ) : CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ) ) ) ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> void arc_expand_prologue ( void ) { int size ; unsigned int gmask = cfun -> machine -> frame_info . gmask ; unsigned int frame_size_to_allocate ; int first_offset = 0 ; unsigned int fn_type = arc_compute_function_type ( cfun ) ; if ( ARC_NAKED_P ( fn_type ) ) { if ( flag_stack_usage_info ) current_function_static_stack_size = 0 ; return ; } size = arc_compute_frame_size ( ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = size ; frame_size_to_allocate = size ; gcc_assert ( ! ( size == 0 && gmask ) ) ; if ( cfun -> machine -> frame_info . pretend_size != 0 ) { gcc_assert ( cfun -> machine -> frame_info . pretend_size <= 32 ) ; frame_stack_add ( - ( HOST_WIDE_INT ) cfun -> machine -> frame_info . pretend_size ) ; frame_size_to_allocate -= cfun -> machine -> frame_info . pretend_size ; } if ( ARC_AUTO_IRQ_P ( fn_type ) && ! ARC_FAST_INTERRUPT_P ( fn_type ) ) { arc_dwarf_emit_irq_save_regs ( ) ; } if ( arc_must_save_return_addr ( cfun ) && ! ARC_AUTOBLINK_IRQ_P ( fn_type ) ) { rtx ra = gen_rtx_REG ( SImode , RETURN_ADDR_REGNUM ) ; rtx mem = gen_frame_mem ( Pmode , gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ) ; frame_move_inc ( mem , ra , stack_pointer_rtx , 0 ) ; frame_size_to_allocate -= UNITS_PER_WORD ; } if ( cfun -> machine -> frame_info . reg_size ) { first_offset = - cfun -> machine -> frame_info . reg_size ; arc_save_restore ( stack_pointer_rtx , gmask , 0 , & first_offset ) ; frame_size_to_allocate -= cfun -> machine -> frame_info . reg_size ; } if ( cfun -> machine -> frame_info . millicode_end_reg > 0 && arc_must_save_return_addr ( cfun ) ) { HOST_WIDE_INT tmp = cfun -> machine -> frame_info . reg_size ; emit_insn ( gen_rtx_SET ( gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) , gen_rtx_MEM ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , tmp ) ) ) ) ; } if ( arc_frame_pointer_needed ( ) && ! ARC_AUTOFP_IRQ_P ( fn_type ) ) { rtx addr = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( - UNITS_PER_WORD + first_offset ) ) ; rtx mem = gen_frame_mem ( Pmode , gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , addr ) ) ; frame_move_inc ( mem , frame_pointer_rtx , stack_pointer_rtx , 0 ) ; frame_size_to_allocate -= UNITS_PER_WORD ; first_offset = 0 ; } if ( arc_frame_pointer_needed ( ) ) { frame_move ( frame_pointer_rtx , stack_pointer_rtx ) ; } frame_size_to_allocate -= first_offset ; if ( frame_size_to_allocate > 0 ) { frame_stack_add ( ( HOST_WIDE_INT ) 0 - frame_size_to_allocate ) ; if ( arc_frame_pointer_needed ( ) ) emit_insn ( gen_stack_tie ( stack_pointer_rtx , hard_frame_pointer_rtx ) ) ; } } </s>

Set up the stack and frame pointer ( if desired ) for the function .


<s> static bool m32r_legitimate_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { return ! ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && ( GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == SYMBOL_REF || GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == LABEL_REF ) && CONST_INT_P ( XEXP ( XEXP ( x , 0 ) , 1 ) ) && UINTVAL ( XEXP ( XEXP ( x , 0 ) , 1 ) ) > 32767 ) ; } </s>

Implement TARGET_LEGITIMATE_CONSTANT_P We do n't allow ( plus symbol large-constant ) as the relocations ca n't describe it . INTVAL > 32767 handles both 16-bit and 24-bit relocations . We allow all CONST_DOUBLE 's as the md file patterns will force the constant to memory if they ca n't handle them .


<s> static machine_mode ix86_cc_modes_compatible ( machine_mode m1 , machine_mode m2 ) { if ( m1 == m2 ) return m1 ; if ( GET_MODE_CLASS ( m1 ) != MODE_CC || GET_MODE_CLASS ( m2 ) != MODE_CC ) return VOIDmode ; if ( ( m1 == CCGCmode && m2 == CCGOCmode ) || ( m1 == CCGOCmode && m2 == CCGCmode ) ) return CCGCmode ; if ( m1 == CCZmode && ( m2 == CCGCmode || m2 == CCGOCmode ) ) return m2 ; else if ( m2 == CCZmode && ( m1 == CCGCmode || m1 == CCGOCmode ) ) return m1 ; switch ( m1 ) { default : gcc_unreachable ( ) ; case CCmode : case CCGCmode : case CCGOCmode : case CCNOmode : case CCAmode : case CCCmode : case CCOmode : case CCSmode : case CCZmode : switch ( m2 ) { default : return VOIDmode ; case CCmode : case CCGCmode : case CCGOCmode : case CCNOmode : case CCAmode : case CCCmode : case CCOmode : case CCSmode : case CCZmode : return CCmode ; } case CCFPmode : case CCFPUmode : return VOIDmode ; } } </s>

If two condition code modes are compatible , return a condition code mode which is compatible with both . Otherwise , return VOIDmode .


<s> bool ARMSubtarget :: enableMachineScheduler ( ) const { return useMachineScheduler ( ) ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


<s>
void
SPIRVMCInstLower
::
lower
(
const
MachineInstr
*
MI
,
MCInst
&
OutMI
,
const
MachineFunction
*
CurMF
,
SPIRV
::
ModuleAnalysisInfo
*
MAI
)
const
{
OutMI
.
setOpcode
(
MI
->
getOpcode
(
)
)
;
const
MachineFunction
*
MF
=
MI
->
getMF
(
)
;
for
(
unsigned
i
=
0
,
e
=
MI
->
getNumOperands
(
)
;
i
!=
e
;
++
i
)
{
const
MachineOperand
&
MO
=
MI
->
getOperand
(
i
)
;
MCOperand
MCOp
;
switch
(
MO
.
getType
(
)
)
{
default
:
MI
->
print
(
errs
(
)
)
;
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_GlobalAddress
:
{
Register
FuncReg
=
MAI
->
getFuncReg
(
MO
.
getGlobal
(
)
->
getGlobalIdentifier
(
)
)
;
assert
(
FuncReg
.
isValid
(
)
&&
"Cannot find function Id"
)
;
MCOp
=
MCOperand
::
createReg
(
FuncReg
)
;
break
;
}
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
createReg
(
MAI
->
getOrCreateMBBRegister
(
*
MO
.
getMBB
(
)
)
)
;
break
;
case
MachineOperand
::
MO_Register
:
{
Register
NewReg
=
MAI
->
getRegisterAlias
(
MF
,
MO
.
getReg
(
)
)
;
bool
IsOldReg
=
!
CurMF
||
!
NewReg
.
isValid
(
)
;
MCOp
=
MCOperand
::
createReg
(
IsOldReg
MO
.
getReg
(
)
:
NewReg
)
;
break
;
}
case
MachineOperand
::
MO_Immediate
:
if
(
MI
->
getOpcode
(
)
==
SPIRV
::
OpExtInst
&&
i
==
2
)
{
Register
Reg
=
MAI
->
getExtInstSetReg
(
MO
.
getImm
(
)
)
;
MCOp
=
MCOperand
::
createReg
(
Reg
)
;
}
else
{
MCOp
=
MCOperand
::
createImm
(
MO
.
getImm
(
)
)
;
}
break
;
case
MachineOperand
::
MO_FPImmediate
:
MCOp
=
MCOperand
::
createDFPImm
(
MO
.
getFPImm
(
)
->
getValueAPF
(
)
.
convertToFloat
(
)
)
;
break
;
}
OutMI
.
addOperand
(
MCOp
)
;
}
}
</s>

SPIRV
SPIRV
SPIRV::ModuleAnalysisInfo
0
"unknown operand type"
"Cannot find function Id"
SPIRV::OpExtInst
2


<s> bool X86FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; const X86Subtarget & STI = MF . getTarget ( ) . getSubtarget < X86Subtarget > ( ) ; unsigned Opc = STI . is64Bit ( ) ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - 1 ] . getFrameIdx ( ) , RC , TRI ) ; -- MI ; MI -> setFlag ( MachineInstr :: FrameSetup ) ; ++ MI ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> int shift_insns_rtx ( rtx insn ) { rtx set_src = SET_SRC ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) ) ; int shift_count = INTVAL ( XEXP ( set_src , 1 ) ) ; enum rtx_code shift_code = GET_CODE ( set_src ) ; switch ( shift_code ) { case ASHIFTRT : return ashiftrt_insns [ shift_count ] ; case LSHIFTRT : case ASHIFT : return shift_insns [ shift_count ] ; default : gcc_unreachable ( ) ; } } </s>

This is used in length attributes in sh.md to help compute the length of arbitrary constant shift instructions .


"unimplemented opcode in encodeInstruction()"

"Pseudo opcode found in encodeInstruction()"

Encode the given Inst to bytes and append to CB .


<s> static bool nvptx_pass_by_reference ( cumulative_args_t ARG_UNUSED ( cum ) , machine_mode mode , const_tree type , bool ARG_UNUSED ( named ) ) { return pass_in_memory ( mode , type , false ) ; } </s>

Types with a mode other than those supported by the machine are passed by reference in memory .


Output the assembly for a call instruction .


<s> void init ( ) { memset ( this , 0 , sizeof * this ) ; } </s>

Initialize the machine model for instruction scheduling .


<s>
void
J2FrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
auto
&
MFI
=
MF
.
getFrameInfo
(
)
;
auto
StackSize
=
MFI
.
getStackSize
(
)
MFI
.
getCalleeSavedInfo
(
)
.
size
(
)
*
4
;
auto
&
TTI
=
*
static_cast
<
const
J2Subtarget
&
>
(
MF
.
getSubtarget
(
)
)
.
getInstrInfo
(
)
;
if
(
StackSize
==
0
)
return
;
auto
it
=
MBB
.
begin
(
)
;
it
=
std
::
next
(
it
,
MFI
.
getCalleeSavedInfo
(
)
.
size
(
)
)
;
DebugLoc
DL
;
if
(
hasFP
(
MF
)
)
BuildMI
(
MBB
,
it
,
DL
,
TTI
.
get
(
J2
::
MOV32rr
)
,
J2
::
R14
)
.
addReg
(
J2
::
R15
)
;
if
(
isInt
<
8
>
(
StackSize
)
)
BuildMI
(
MBB
,
it
,
DL
,
TTI
.
get
(
J2
::
ADDri
)
,
J2
::
R15
)
.
addReg
(
J2
::
R15
)
.
addImm
(
StackSize
)
;
else
{
llvm_unreachable
(
"Not implemented yet"
)
;
}
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> AArch64TargetLowering :: ConstraintType AArch64TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'z' : return C_Other ; case 'x' : case 'w' : return C_RegisterClass ; case 'Q' : return C_Memory ; } } else if ( Constraint . size ( ) == 3 && Constraint [ 0 ] == 'U' && Constraint [ 1 ] == 'p' && ( Constraint [ 2 ] == 'l' || Constraint [ 2 ] == 'a' ) ) { return C_RegisterClass ; } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s>
void
UPTFrameLowering
::
emitEpilogue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
LLVM_DEBUG
(
dbgs
(
)
<<
">> FrameLowering::emitEpilogue <<\n"
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
getLastNonDebugInstr
(
)
;
DebugLoc
dl
=
MBBI
->
getDebugLoc
(
)
;
uint64_t
StackSize
=
computeStackSize
(
MF
)
;
if
(
!
StackSize
)
{
return
;
}
unsigned
StackReg
=
UPT
::
SP
;
unsigned
OffsetReg
=
materializeOffset
(
MF
,
MBB
,
MBBI
,
(
unsigned
)
StackSize
)
;
if
(
OffsetReg
)
{
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
UPT
::
ADDR
)
,
StackReg
)
.
addReg
(
StackReg
)
.
addReg
(
OffsetReg
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
}
else
{
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
UPT
::
ADDI
)
,
StackReg
)
.
addReg
(
StackReg
)
.
addImm
(
StackSize
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
}
}
</s>

UPT
UPT
">> FrameLowering::emitEpilogue <<\n"
UPT::SP
UPT::ADDR
UPT::ADDI


"multiversioning needs ifunc which is not supported "

Make a dispatcher declaration for the multi-versioned function DECL . Calls to DECL function will be replaced with calls to the dispatcher by the front-end . Returns the decl of the dispatcher function .


<s> static bool general_scalar_to_vector_candidate_p ( rtx_insn * insn , enum machine_mode mode ) { rtx def_set = pseudo_reg_set ( insn ) ; if ( ! def_set ) return false ; rtx src = SET_SRC ( def_set ) ; rtx dst = SET_DEST ( def_set ) ; if ( GET_CODE ( src ) == COMPARE ) return convertible_comparison_p ( insn , mode ) ; if ( ( GET_MODE ( src ) != mode && ! CONST_INT_P ( src ) ) || GET_MODE ( dst ) != mode ) return false ; if ( ! REG_P ( dst ) && ! MEM_P ( dst ) ) return false ; switch ( GET_CODE ( src ) ) { case ASHIFTRT : if ( ! TARGET_AVX512VL ) return false ; case ASHIFT : case LSHIFTRT : if ( ! CONST_INT_P ( XEXP ( src , 1 ) ) || ! IN_RANGE ( INTVAL ( XEXP ( src , 1 ) ) , 0 , GET_MODE_BITSIZE ( mode ) - 1 ) ) return false ; break ; case SMAX : case SMIN : case UMAX : case UMIN : if ( ( mode == DImode && ! TARGET_AVX512VL ) || ( mode == SImode && ! TARGET_SSE4_1 ) ) return false ; case AND : case IOR : case XOR : case PLUS : case MINUS : if ( ! REG_P ( XEXP ( src , 1 ) ) && ! MEM_P ( XEXP ( src , 1 ) ) && ! CONST_INT_P ( XEXP ( src , 1 ) ) ) return false ; if ( GET_MODE ( XEXP ( src , 1 ) ) != mode && ! CONST_INT_P ( XEXP ( src , 1 ) ) ) return false ; if ( GET_CODE ( src ) != AND || GET_CODE ( XEXP ( src , 0 ) ) != NOT ) break ; src = XEXP ( src , 0 ) ; case NOT : break ; case NEG : if ( GET_CODE ( XEXP ( src , 0 ) ) != ABS ) break ; src = XEXP ( src , 0 ) ; case ABS : if ( ( mode == DImode && ! TARGET_AVX512VL ) || ( mode == SImode && ! TARGET_SSSE3 ) ) return false ; break ; case REG : return true ; case MEM : case CONST_INT : return REG_P ( dst ) ; default : return false ; } if ( ! REG_P ( XEXP ( src , 0 ) ) && ! MEM_P ( XEXP ( src , 0 ) ) && ! CONST_INT_P ( XEXP ( src , 0 ) ) ) return false ; if ( GET_MODE ( XEXP ( src , 0 ) ) != mode && ! CONST_INT_P ( XEXP ( src , 0 ) ) ) return false ; return true ; } </s>

The general version of scalar_to_vector_candidate_p .


<s> void FISCMCInstLower :: Initialize ( Mangler * M , MCContext * C ) { Mang = M ; Ctx = C ; } </s>

This method must be called before any actual lowering is done .


"dynamic alloca in the static alloca map?"

Emit an alloca address in a register using target-specific logic .


<s>
const
char
*
emit_fusion_p9_store
(
rtx
mem
,
rtx
reg
,
rtx
tmp_reg
)
{
machine_mode
mode
=
GET_MODE
(
reg
)
;
rtx
hi
;
rtx
lo
;
rtx
addr
;
const
char
*
store_string
;
int
r
;
if
(
GET_CODE
(
reg
)
==
SUBREG
)
{
gcc_assert
(
SUBREG_BYTE
(
reg
)
==
0
)
;
reg
=
SUBREG_REG
(
reg
)
;
}
if
(
!
REG_P
(
reg
)
)
fatal_insn
(
"emit_fusion_p9_store, bad reg #1"
,
reg
)
;
r
=
REGNO
(
reg
)
;
if
(
FP_REGNO_P
(
r
)
)
{
if
(
mode
==
SFmode
)
store_string
=
"stfs"
;
else
if
(
mode
==
DFmode
)
store_string
=
"stfd"
;
else
gcc_unreachable
(
)
;
}
else
if
(
ALTIVEC_REGNO_P
(
r
)
&&
TARGET_P9_DFORM_SCALAR
)
{
if
(
mode
==
SFmode
)
store_string
=
"stxssp"
;
else
if
(
mode
==
DFmode
||
mode
==
DImode
)
store_string
=
"stxsd"
;
else
gcc_unreachable
(
)
;
}
else
if
(
INT_REGNO_P
(
r
)
)
{
switch
(
mode
)
{
case
E_QImode
:
store_string
=
"stb"
;
break
;
case
E_HImode
:
store_string
=
"sth"
;
break
;
case
E_SImode
:
case
E_SFmode
:
store_string
=
"stw"
;
break
;
case
E_DImode
:
case
E_DFmode
:
if
(
!
TARGET_POWERPC64
)
gcc_unreachable
(
)
;
store_string
=
"std"
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
else
fatal_insn
(
"emit_fusion_p9_store, bad reg #2"
,
reg
)
;
if
(
!
MEM_P
(
mem
)
)
fatal_insn
(
"emit_fusion_p9_store not MEM"
,
mem
)
;
addr
=
XEXP
(
mem
,
0
)
;
fusion_split_address
(
addr
,
&
hi
,
&
lo
)
;
emit_fusion_addis
(
tmp_reg
,
hi
,
"power9 store fusion"
,
GET_MODE_NAME
(
mode
)
)
;
emit_fusion_load_store
(
reg
,
tmp_reg
,
lo
,
store_string
)
;
return
""
;
}
</s>

Return a string to fuse an addis instruction with a store using extended fusion . The address that is used is the logical address that was formed during peephole2 : ( lo_sum ( high ) ( low-part ) ) The code is complicated , so we call output_asm_insn directly , and just return `` '' .

powerpcspe
0
"emit_fusion_p9_store, bad reg #1"
"stfs"
"stfd"
"stxssp"
"stxsd"
"stb"
"sth"
"stw"
"std"
"emit_fusion_p9_store, bad reg #2"
"emit_fusion_p9_store not MEM"
0
"power9 store fusion"
""


<s>
static
int
s390_sched_variable_issue
(
FILE
*
file
,
int
verbose
,
rtx_insn
*
insn
,
int
more
)
{
last_scheduled_insn
=
insn
;
if
(
s390_tune
>=
PROCESSOR_2827_ZEC12
&&
reload_completed
&&
recog_memoized
(
insn
)
>=
0
)
{
unsigned
int
mask
=
s390_get_sched_attrmask
(
insn
)
;
if
(
(
mask
&
S390_SCHED_ATTR_MASK_CRACKED
)
!=
0
||
(
mask
&
S390_SCHED_ATTR_MASK_EXPANDED
)
!=
0
)
s390_sched_state
=
S390_SCHED_STATE_CRACKED
;
else
if
(
(
mask
&
S390_SCHED_ATTR_MASK_ENDGROUP
)
!=
0
||
(
mask
&
S390_SCHED_ATTR_MASK_GROUPALONE
)
!=
0
)
s390_sched_state
=
S390_SCHED_STATE_NORMAL
;
else
{
switch
(
s390_sched_state
)
{
case
0
:
case
1
:
case
2
:
case
S390_SCHED_STATE_NORMAL
:
if
(
s390_sched_state
==
S390_SCHED_STATE_NORMAL
)
s390_sched_state
=
1
;
else
s390_sched_state
++
;
break
;
case
S390_SCHED_STATE_CRACKED
:
s390_sched_state
=
S390_SCHED_STATE_NORMAL
;
break
;
}
}
if
(
s390_tune
>=
PROCESSOR_2964_Z13
)
{
int
units
,
i
;
unsigned
unit_mask
,
m
=
1
;
unit_mask
=
s390_get_unit_mask
(
insn
,
&
units
)
;
gcc_assert
(
units
<=
MAX_SCHED_UNITS
)
;
for
(
i
=
0
;
i
<
units
;
i
++
,
m
<<=
1
)
if
(
m
&
unit_mask
)
last_scheduled_unit_distance
[
i
]
=
0
;
else
if
(
last_scheduled_unit_distance
[
i
]
<
MAX_SCHED_MIX_DISTANCE
)
last_scheduled_unit_distance
[
i
]
++
;
}
if
(
verbose
>
5
)
{
unsigned
int
sched_mask
;
sched_mask
=
s390_get_sched_attrmask
(
insn
)
;
fprintf
(
file
,
";;\t\tBACKEND: insn %d: "
,
INSN_UID
(
insn
)
)
;
PRINT_SCHED_ATTR
(
S390_SCHED_ATTR_MASK_CRACKED
,
cracked
)
;
PRINT_SCHED_ATTR
(
S390_SCHED_ATTR_MASK_EXPANDED
,
expanded
)
;
PRINT_SCHED_ATTR
(
S390_SCHED_ATTR_MASK_ENDGROUP
,
endgroup
)
;
PRINT_SCHED_ATTR
(
S390_SCHED_ATTR_MASK_GROUPALONE
,
groupalone
)
;
if
(
s390_tune
>=
PROCESSOR_2964_Z13
)
{
unsigned
int
unit_mask
,
m
=
1
;
int
units
,
j
;
unit_mask
=
s390_get_unit_mask
(
insn
,
&
units
)
;
fprintf
(
file
,
"(units:"
)
;
for
(
j
=
0
;
j
<
units
;
j
++
,
m
<<=
1
)
if
(
m
&
unit_mask
)
fprintf
(
file
,
" %d"
,
j
)
;
fprintf
(
file
,
")"
)
;
}
fprintf
(
file
,
" sched state: %d\n"
,
s390_sched_state
)
;
if
(
s390_tune
>=
PROCESSOR_2964_Z13
)
{
int
units
,
j
;
s390_get_unit_mask
(
insn
,
&
units
)
;
fprintf
(
file
,
";;\t\tBACKEND: units unused for: "
)
;
for
(
j
=
0
;
j
<
units
;
j
++
)
fprintf
(
file
,
"%d:%d "
,
j
,
last_scheduled_unit_distance
[
j
]
)
;
fprintf
(
file
,
"\n"
)
;
}
}
}
if
(
GET_CODE
(
PATTERN
(
insn
)
)
!=
USE
&&
GET_CODE
(
PATTERN
(
insn
)
)
!=
CLOBBER
)
return
more
1
;
else
return
more
;
}
</s>

This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after the scheduler has issued INSN . It stores the last issued insn into last_scheduled_insn in order to make it available for s390_sched_reorder .


<s> void print ( const TargetRegisterInfo * TRI = nullptr ) const { dbgs ( ) << printReg ( Reg , TRI , SubReg ) ; } </s>

print - Print a debug representation of the operand to the given stream .


<s>
const
char
*
getPassName
(
)
const
{
return
"ARM64 Conditional Compares"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool CJGInstrInfo :: isUnpredicatedTerminator ( const MachineInstr & MI ) const { if ( ! MI . isTerminator ( ) ) return false ; if ( MI . isBranch ( ) && ! MI . isBarrier ( ) ) return true ; if ( ! MI . isPredicable ( ) ) return true ; return ! isPredicated ( MI ) ; } </s>

Returns true if the instruction is a terminator instruction that has not been predicated .


<s> static rtx nvptx_expand_shuffle ( tree exp , rtx target , machine_mode mode , int ignore ) { if ( ignore ) return target ; rtx src = expand_expr ( CALL_EXPR_ARG ( exp , 0 ) , NULL_RTX , mode , EXPAND_NORMAL ) ; if ( ! REG_P ( src ) ) src = copy_to_mode_reg ( mode , src ) ; rtx idx = expand_expr ( CALL_EXPR_ARG ( exp , 1 ) , NULL_RTX , SImode , EXPAND_NORMAL ) ; rtx op = expand_expr ( CALL_EXPR_ARG ( exp , 2 ) , NULL_RTX , SImode , EXPAND_NORMAL ) ; if ( ! REG_P ( idx ) && GET_CODE ( idx ) != CONST_INT ) idx = copy_to_mode_reg ( SImode , idx ) ; rtx pat = nvptx_gen_shuffle ( target , src , idx , ( nvptx_shuffle_kind ) INTVAL ( op ) ) ; if ( pat ) emit_insn ( pat ) ; return target ; } </s>


<s> enum direction function_arg_padding ( machine_mode mode , const_tree type ) { if ( TARGET_ARCH64 && type && AGGREGATE_TYPE_P ( type ) ) return upward ; return DEFAULT_FUNCTION_ARG_PADDING ( mode , type ) ; } </s>

Handle the FUNCTION_ARG_PADDING macro . For the 64 bit ABI structs are always stored left shifted in their argument slot .


<s> const MCPhysReg * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( STI . isTargetNaCl ( ) ) return CSR_NaCl_SaveList ; const MCPhysReg * RegList = ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ; if ( ! MF ) return RegList ; const Function * F = MF -> getFunction ( ) ; if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F -> hasFnAttribute ( "interrupt" ) ) { if ( STI . isMClass ( ) ) { return CSR_AAPCS_SaveList ; } else if ( F -> getFnAttribute ( "interrupt" ) . getValueAsString ( ) == "FIQ" ) { return CSR_FIQ_SaveList ; } else { return CSR_GenericInt_SaveList ; } } return RegList ; } </s>


<s> void rs6000_expand_interleave ( rtx target , rtx op0 , rtx op1 , bool highp ) { machine_mode vmode = GET_MODE ( target ) ; unsigned i , high , nelt = GET_MODE_NUNITS ( vmode ) ; rtx perm [ 16 ] ; high = ( highp ? 0 : nelt / 2 ) ; for ( i = 0 ; i < nelt / 2 ; i ++ ) { perm [ i * 2 ] = GEN_INT ( i + high ) ; perm [ i * 2 + 1 ] = GEN_INT ( i + nelt + high ) ; } rs6000_do_expand_vec_perm ( target , op0 , op1 , vmode , nelt , perm ) ; } </s>


<s> const uint16_t * Z80RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { Z80 :: BC , Z80 :: DE , Z80 :: IX , Z80 :: IY , 0 } ; return CalleeSavedRegs ; } </s>


<s>
void
addExpr
(
MCInst
&
Inst
,
const
MCExpr
*
Expr
)
const
{
assert
(
Expr
&&
"Expr shouldn't be null!"
)
;
int64_t
Imm
=
0
;
RISCVMCExpr
::
VariantKind
VK
;
bool
IsConstant
=
evaluateConstantImm
(
Expr
,
Imm
,
VK
)
;
if
(
IsConstant
)
Inst
.
addOperand
(
MCOperand
::
createImm
(
Imm
)
)
;
else
Inst
.
addOperand
(
MCOperand
::
createExpr
(
Expr
)
)
;
}
</s>


<s>
SDValue
TeeRISCTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
MF
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_TeeRISC
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
TeeRISC
::
R1
,
MVT
::
i32
)
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
SDValue
Val
=
OutVals
[
i
]
;
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
if
(
RVLocs
[
i
]
.
getValVT
(
)
!=
RVLocs
[
i
]
.
getLocVT
(
)
)
Val
=
DAG
.
getNode
(
ISD
::
BITCAST
,
dl
,
RVLocs
[
i
]
.
getLocVT
(
)
,
Val
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
Val
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
TeeRISC_ISD
::
RET
,
dl
,
MVT
::
Other
,
&
RetOps
[
0
]
,
RetOps
.
size
(
)
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static enum flt_eval_method riscv_excess_precision ( enum excess_precision_type type ) { switch ( type ) { case EXCESS_PRECISION_TYPE_FAST : case EXCESS_PRECISION_TYPE_STANDARD : return ( ( TARGET_ZFH || TARGET_ZHINX ) ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16 : FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ) ; case EXCESS_PRECISION_TYPE_IMPLICIT : case EXCESS_PRECISION_TYPE_FLOAT16 : return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16 ; default : gcc_unreachable ( ) ; } return FLT_EVAL_METHOD_UNPREDICTABLE ; } </s>

Set the value of FLT_EVAL_METHOD . ISO/IEC TS 18661-3 defines two values that we 'd like to make use of : 0 : evaluate all operations and constants , whose semantic type has at most the range and precision of type float , to the range and precision of float ; evaluate all other operations and constants to the range and precision of the semantic type ; N , where _FloatN is a supported interchange floating type evaluate all operations and constants , whose semantic type has at most the range and precision of _FloatN type , to the range and precision of the _FloatN type ; evaluate all other operations and constants to the range and precision of the semantic type ; If we have the zfh/zhinx extensions then we support _Float16 in native precision , so we should set this to 16 .


"EBP/ESI restoration only required on win32"

"restoring EBP/ESI on non-32-bit target"

"end of registration object above normal EBP position!"

"32-bit frames with WinEH must use FramePtr or BasePtr"

Sets up EBP and optionally ESI based on the incoming EBP value .


<s> static void mips_macc_chains_record ( rtx insn ) { if ( get_attr_may_clobber_hilo ( insn ) ) mips_macc_chains_last_hilo = insn ; } </s>

A TUNE_MACC_CHAINS helper function . Record that instruction INSN has been scheduled , updating mips_macc_chains_last_hilo appropriately .


<s> bool NVPTXAsmPrinter :: doFinalization ( Module & M ) { if ( ! GlobalsEmitted ) { emitGlobals ( M ) ; GlobalsEmitted = true ; } Module :: GlobalListType & global_list = M . getGlobalList ( ) ; int i , n = global_list . size ( ) ; GlobalVariable * * gv_array = new GlobalVariable * [ n ] ; i = 0 ; for ( Module :: global_iterator I = global_list . begin ( ) , E = global_list . end ( ) ; I != E ; ++ I ) gv_array [ i ++ ] = & * I ; while ( ! global_list . empty ( ) ) global_list . remove ( global_list . begin ( ) ) ; bool ret = AsmPrinter :: doFinalization ( M ) ; for ( i = 0 ; i < n ; i ++ ) global_list . insert ( global_list . end ( ) , gv_array [ i ] ) ; delete [ ] gv_array ; return ret ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> int rs6000_trampoline_size ( void ) { int ret = 0 ; switch ( DEFAULT_ABI ) { default : gcc_unreachable ( ) ; case ABI_AIX : ret = ( TARGET_32BIT ) ? 12 : 24 ; break ; case ABI_ELFv2 : gcc_assert ( ! TARGET_32BIT ) ; ret = 32 ; break ; case ABI_DARWIN : case ABI_V4 : ret = ( TARGET_32BIT ) ? 40 : 48 ; break ; } return ret ; } </s>

Length in units of the trampoline for entering a nested function .


<s> unsigned AMDGPUAsmParser :: checkTargetMatchPredicate ( MCInst & Inst ) { uint64_t TSFlags = MII . get ( Inst . getOpcode ( ) ) . TSFlags ; if ( ( getForcedEncodingSize ( ) == 32 && ( TSFlags & SIInstrFlags :: VOP3 ) ) || ( getForcedEncodingSize ( ) == 64 && ! ( TSFlags & SIInstrFlags :: VOP3 ) ) || ( isForcedDPP ( ) && ! ( TSFlags & SIInstrFlags :: DPP ) ) || ( isForcedSDWA ( ) && ! ( TSFlags & SIInstrFlags :: SDWA ) ) ) return Match_InvalidOperand ; if ( ( TSFlags & SIInstrFlags :: VOP3 ) && ( TSFlags & SIInstrFlags :: VOPAsmPrefer32Bit ) && getForcedEncodingSize ( ) != 64 ) return Match_PreferE32 ; if ( Inst . getOpcode ( ) == AMDGPU :: V_MAC_F32_sdwa_vi || Inst . getOpcode ( ) == AMDGPU :: V_MAC_F16_sdwa_vi ) { auto OpNum = AMDGPU :: getNamedOperandIdx ( Inst . getOpcode ( ) , AMDGPU :: OpName :: dst_sel ) ; const auto & Op = Inst . getOperand ( OpNum ) ; if ( ! Op . isImm ( ) || Op . getImm ( ) != AMDGPU :: SDWA :: SdwaSel :: DWORD ) { return Match_InvalidOperand ; } } if ( TSFlags & SIInstrFlags :: FLAT ) { auto Opcode = Inst . getOpcode ( ) ; auto OpNum = AMDGPU :: getNamedOperandIdx ( Opcode , AMDGPU :: OpName :: offset ) ; const auto & Op = Inst . getOperand ( OpNum ) ; if ( ! hasFlatOffsets ( ) && Op . getImm ( ) != 0 ) return Match_InvalidOperand ; if ( isGFX10 ( ) ) { if ( TSFlags & SIInstrFlags :: IsNonFlatSeg ) { if ( ! isInt < 12 > ( Op . getImm ( ) ) ) return Match_InvalidOperand ; } else { if ( ! isUInt < 11 > ( Op . getImm ( ) ) ) return Match_InvalidOperand ; } } } return Match_Success ; } </s>

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


<s> PPCTargetLowering :: ConstraintType PPCTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'b' : case 'r' : case 'f' : case 'v' : case 'y' : return C_RegisterClass ; case 'Z' : return C_Memory ; } } else if ( Constraint == "wc" ) { return C_RegisterClass ; } else if ( Constraint == "wa" || Constraint == "wd" || Constraint == "wf" || Constraint == "ws" ) { return C_RegisterClass ; } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .

PowerPC PPC PPC 1 0 "wc" "wa" "wd" "wf" "ws"


<s> ScheduleHazardRecognizer * PPCInstrInfo :: CreateTargetHazardRecognizer ( const TargetMachine * TM , const ScheduleDAG * DAG ) const { unsigned Directive = TM -> getSubtarget < PPCSubtarget > ( ) . getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_440 || Directive == PPC :: DIR_A2 || Directive == PPC :: DIR_E500mc || Directive == PPC :: DIR_E5500 ) { const InstrItineraryData * II = TM -> getInstrItineraryData ( ) ; return new PPCScoreboardHazardRecognizer ( II , DAG ) ; } return TargetInstrInfo :: CreateTargetHazardRecognizer ( TM , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .


<s> static ArrayRef < MCPhysReg > getAllSGPR128 ( const GCNSubtarget & ST , const MachineFunction & MF ) { return makeArrayRef ( AMDGPU :: SGPR_128RegClass . begin ( ) , ST . getMaxNumSGPRs ( MF ) / 4 ) ; } </s>

Return all SGPR128 which satisfy the waves per execution unit requirement of the subtarget .


<s> void s390_reload_symref_address ( rtx reg , rtx mem , rtx scratch , bool tomem ) { if ( CONST_INT_P ( mem ) || GET_CODE ( mem ) == CONST_DOUBLE || GET_CODE ( mem ) == CONST ) mem = force_const_mem ( GET_MODE ( reg ) , mem ) ; gcc_assert ( MEM_P ( mem ) ) ; if ( ! tomem && REGNO ( reg ) < FIRST_PSEUDO_REGISTER && REGNO_REG_CLASS ( REGNO ( reg ) ) == ADDR_REGS && GET_MODE ( reg ) == GET_MODE ( scratch ) ) scratch = reg ; s390_reload_larl_operand ( scratch , XEXP ( mem , 0 ) , scratch ) ; if ( tomem ) emit_move_insn ( replace_equiv_address ( mem , scratch ) , reg ) ; else emit_move_insn ( reg , replace_equiv_address ( mem , scratch ) ) ; } </s>

Generate what is necessary to move between REG and MEM using SCRATCH . The direction is given by TOMEM .


<s>
SDValue
AMDGPUTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
Op
.
getNode
(
)
->
dump
(
)
;
llvm_unreachable
(
"Custom lowering code for this"
"instruction is not implemented yet!"
)
;
break
;
case
ISD
::
SIGN_EXTEND_INREG
:
return
LowerSIGN_EXTEND_INREG
(
Op
,
DAG
)
;
case
ISD
::
CONCAT_VECTORS
:
return
LowerCONCAT_VECTORS
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_SUBVECTOR
:
return
LowerEXTRACT_SUBVECTOR
(
Op
,
DAG
)
;
case
ISD
::
FrameIndex
:
return
LowerFrameIndex
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
UDIVREM
:
return
LowerUDIVREM
(
Op
,
DAG
)
;
case
ISD
::
SDIVREM
:
return
LowerSDIVREM
(
Op
,
DAG
)
;
case
ISD
::
FREM
:
return
LowerFREM
(
Op
,
DAG
)
;
case
ISD
::
FCEIL
:
return
LowerFCEIL
(
Op
,
DAG
)
;
case
ISD
::
FTRUNC
:
return
LowerFTRUNC
(
Op
,
DAG
)
;
case
ISD
::
FRINT
:
return
LowerFRINT
(
Op
,
DAG
)
;
case
ISD
::
FNEARBYINT
:
return
LowerFNEARBYINT
(
Op
,
DAG
)
;
case
ISD
::
FROUND
:
return
LowerFROUND
(
Op
,
DAG
)
;
case
ISD
::
FFLOOR
:
return
LowerFFLOOR
(
Op
,
DAG
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerSINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
UINT_TO_FP
:
return
LowerUINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_SINT
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_UINT
(
Op
,
DAG
)
;
}
return
Op
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

AMDGPU
AMDGPU
"Custom lowering code for this"
"instruction is not implemented yet!"
ISD::SIGN_EXTEND_INREG
SI
ISD::CONCAT_VECTORS
ISD::EXTRACT_SUBVECTOR
ISD::FrameIndex
ISD::INTRINSIC_WO_CHAIN
SI
ISD::UDIVREM
ISD::SDIVREM
ISD::FREM
ISD::FCEIL
ISD::FTRUNC
ISD::FRINT
ISD::FNEARBYINT
ISD::FROUND
ISD::FFLOOR
ISD::SINT_TO_FP
SI
ISD::UINT_TO_FP
ISD::FP_TO_SINT
SI
ISD::FP_TO_UINT


<s> bool AMDGPUInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock * MBB = MI -> getParent ( ) ; int OffsetOpIdx = AMDGPU :: getNamedOperandIdx ( MI -> getOpcode ( ) , AMDGPU :: OpName :: addr ) ; int RegOpIdx = OffsetOpIdx + 1 ; int ChanOpIdx = AMDGPU :: getNamedOperandIdx ( MI -> getOpcode ( ) , AMDGPU :: OpName :: chan ) ; if ( isRegisterLoad ( * MI ) ) { int DstOpIdx = AMDGPU :: getNamedOperandIdx ( MI -> getOpcode ( ) , AMDGPU :: OpName :: dst ) ; unsigned RegIndex = MI -> getOperand ( RegOpIdx ) . getImm ( ) ; unsigned Channel = MI -> getOperand ( ChanOpIdx ) . getImm ( ) ; unsigned Address = calculateIndirectAddress ( RegIndex , Channel ) ; unsigned OffsetReg = MI -> getOperand ( OffsetOpIdx ) . getReg ( ) ; if ( OffsetReg == AMDGPU :: INDIRECT_BASE_ADDR ) { buildMovInstr ( MBB , MI , MI -> getOperand ( DstOpIdx ) . getReg ( ) , getIndirectAddrRegClass ( ) -> getRegister ( Address ) ) ; } else { buildIndirectRead ( MBB , MI , MI -> getOperand ( DstOpIdx ) . getReg ( ) , Address , OffsetReg ) ; } } else if ( isRegisterStore ( * MI ) ) { int ValOpIdx = AMDGPU :: getNamedOperandIdx ( MI -> getOpcode ( ) , AMDGPU :: OpName :: val ) ; unsigned RegIndex = MI -> getOperand ( RegOpIdx ) . getImm ( ) ; unsigned Channel = MI -> getOperand ( ChanOpIdx ) . getImm ( ) ; unsigned Address = calculateIndirectAddress ( RegIndex , Channel ) ; unsigned OffsetReg = MI -> getOperand ( OffsetOpIdx ) . getReg ( ) ; if ( OffsetReg == AMDGPU :: INDIRECT_BASE_ADDR ) { buildMovInstr ( MBB , MI , getIndirectAddrRegClass ( ) -> getRegister ( Address ) , MI -> getOperand ( ValOpIdx ) . getReg ( ) ) ; } else { buildIndirectWrite ( MBB , MI , MI -> getOperand ( ValOpIdx ) . getReg ( ) , calculateIndirectAddress ( RegIndex , Channel ) , OffsetReg ) ; } } else { return false ; } MBB -> erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s>
bool
SIAnnotateControlFlow
::
runOnFunction
(
Function
&
F
)
{
DT
=
&
getAnalysis
<
DominatorTreeWrapperPass
>
(
)
.
getDomTree
(
)
;
LI
=
&
getAnalysis
<
LoopInfoWrapperPass
>
(
)
.
getLoopInfo
(
)
;
DA
=
&
getAnalysis
<
LegacyDivergenceAnalysis
>
(
)
;
TargetPassConfig
&
TPC
=
getAnalysis
<
TargetPassConfig
>
(
)
;
const
TargetMachine
&
TM
=
TPC
.
getTM
<
TargetMachine
>
(
)
;
initialize
(
*
F
.
getParent
(
)
,
TM
.
getSubtarget
<
GCNSubtarget
>
(
F
)
)
;
for
(
df_iterator
<
BasicBlock
*
>
I
=
df_begin
(
&
F
.
getEntryBlock
(
)
)
,
E
=
df_end
(
&
F
.
getEntryBlock
(
)
)
;
I
!=
E
;
++
I
)
{
BasicBlock
*
BB
=
*
I
;
BranchInst
*
Term
=
dyn_cast
<
BranchInst
>
(
BB
->
getTerminator
(
)
)
;
if
(
!
Term
||
Term
->
isUnconditional
(
)
)
{
if
(
isTopOfStack
(
BB
)
)
closeControlFlow
(
BB
)
;
continue
;
}
if
(
I
.
nodeVisited
(
Term
->
getSuccessor
(
1
)
)
)
{
if
(
isTopOfStack
(
BB
)
)
closeControlFlow
(
BB
)
;
if
(
DT
->
dominates
(
Term
->
getSuccessor
(
1
)
,
BB
)
)
handleLoop
(
Term
)
;
continue
;
}
if
(
isTopOfStack
(
BB
)
)
{
PHINode
*
Phi
=
dyn_cast
<
PHINode
>
(
Term
->
getCondition
(
)
)
;
if
(
Phi
&&
Phi
->
getParent
(
)
==
BB
&&
isElse
(
Phi
)
)
{
insertElse
(
Term
)
;
eraseIfUnused
(
Phi
)
;
continue
;
}
closeControlFlow
(
BB
)
;
}
openIf
(
Term
)
;
}
if
(
!
Stack
.
empty
(
)
)
{
report_fatal_error
(
"failed to annotate CFG"
)
;
}
return
true
;
}
</s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void UPTInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { unsigned Opc = 0 , ZeroReg = 0 ; Opc = UPT :: ADDR , ZeroReg = UPT :: ZERO ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( UPT :: ADDR ) ) ; if ( DestReg ) MIB . addReg ( DestReg , RegState :: Define ) ; if ( ZeroReg ) MIB . addReg ( UPT :: ZERO ) ; if ( SrcReg ) MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } </s>

UPT UPT 0 0 UPT::ADDR UPT::ZERO UPT::ADDR UPT::ZERO


<s> MCSymbol * XtensaMCInstLower :: GetExternalSymbolSymbol ( const MachineOperand & MO ) const { return Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; } </s>

Return the MCSymbol for the specified ExternalSymbol .


<s> bool quad_address_p ( rtx addr , machine_mode mode , bool strict ) { rtx op0 , op1 ; if ( GET_MODE_SIZE ( mode ) != 16 ) return false ; if ( legitimate_indirect_address_p ( addr , strict ) ) return true ; if ( VECTOR_MODE_P ( mode ) && ! mode_supports_vsx_dform_quad ( mode ) ) return false ; if ( GET_CODE ( addr ) != PLUS ) return false ; op0 = XEXP ( addr , 0 ) ; if ( ! REG_P ( op0 ) || ! INT_REG_OK_FOR_BASE_P ( op0 , strict ) ) return false ; op1 = XEXP ( addr , 1 ) ; if ( ! CONST_INT_P ( op1 ) ) return false ; return quad_address_offset_p ( INTVAL ( op1 ) ) ; } </s>

Return true if the ADDR is an acceptable address for a quad memory operation of mode MODE ( either LQ/STQ for general purpose registers , or LXV/STXV for vector registers under ISA 3.0 . GPR_P is true if this address is intended for LQ/STQ . If it is false , the address is intended for the ISA 3.0 LXV/STXV instruction .


<s> std :: pair < SDValue , SDValue > SystemZSelectionDAGInfo :: EmitTargetCodeForStrcmp ( SelectionDAG & DAG , SDLoc DL , SDValue Chain , SDValue Src1 , SDValue Src2 , MachinePointerInfo Op1PtrInfo , MachinePointerInfo Op2PtrInfo ) const { SDVTList VTs = DAG . getVTList ( Src1 . getValueType ( ) , MVT :: Other , MVT :: Glue ) ; SDValue Unused = DAG . getNode ( SystemZISD :: STRCMP , DL , VTs , Chain , Src1 , Src2 , DAG . getConstant ( 0 , MVT :: i32 ) ) ; Chain = Unused . getValue ( 1 ) ; SDValue Glue = Chain . getValue ( 2 ) ; return std :: make_pair ( addIPMSequence ( DL , Glue , DAG ) , Chain ) ; } </s>

Emit target-specific code that performs a strcmp , in cases where that is faster than a libcall .


<s> bool X86TargetLowering :: isUsedByReturnOnly ( SDNode * N ) const { if ( N -> getNumValues ( ) != 1 ) return false ; if ( ! N -> hasNUsesOfValue ( 1 , 0 ) ) return false ; SDNode * Copy = * N -> use_begin ( ) ; if ( Copy -> getOpcode ( ) != ISD :: CopyToReg && Copy -> getOpcode ( ) != ISD :: FP_EXTEND ) return false ; bool HasRet = false ; for ( SDNode :: use_iterator UI = Copy -> use_begin ( ) , UE = Copy -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != X86ISD :: RET_FLAG ) return false ; HasRet = true ; } return HasRet ; } </s>

Return true if result of the specified node is used by a return node only .


<s> bool LC3PassConfig :: addPreISel ( ) { return false ; } </s>


<s> static rtx safe_vector_operand ( rtx x , enum machine_mode mode ) { if ( x == const0_rtx ) x = CONST0_RTX ( mode ) ; return x ; } </s>

Errors in the source file can cause expand_expr to return const0_rtx where we expect a vector . To avoid crashing , use one of the vector clear instructions .


<s> outliner :: InstrType RISCVInstrInfo :: getOutliningType ( MachineBasicBlock :: iterator & MBBI , unsigned Flags ) const { MachineInstr & MI = * MBBI ; MachineBasicBlock * MBB = MI . getParent ( ) ; const TargetRegisterInfo * TRI = MBB -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; if ( MI . isPosition ( ) ) { if ( MI . isCFIInstruction ( ) ) return outliner :: InstrType :: Invisible ; return outliner :: InstrType :: Illegal ; } if ( MI . isInlineAsm ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . isTerminator ( ) && ! MBB -> succ_empty ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . isReturn ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . modifiesRegister ( RISCV :: X5 , TRI ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( RISCV :: X5 ) ) return outliner :: InstrType :: Illegal ; for ( const auto & MO : MI . operands ( ) ) if ( MO . isMBB ( ) || MO . isBlockAddress ( ) || MO . isCPI ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . isMetaInstruction ( ) ) return outliner :: InstrType :: Invisible ; return outliner :: InstrType :: Legal ; } </s>

Returns how or if MIT should be outlined .


<s> const unsigned * MSP430RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const TargetFrameInfo * TFI = MF -> getTarget ( ) . getFrameInfo ( ) ; const Function * F = MF -> getFunction ( ) ; static const unsigned CalleeSavedRegs [ ] = { MSP430 :: FPW , MSP430 :: R5W , MSP430 :: R6W , MSP430 :: R7W , MSP430 :: R8W , MSP430 :: R9W , MSP430 :: R10W , MSP430 :: R11W , 0 } ; static const unsigned CalleeSavedRegsFP [ ] = { MSP430 :: R5W , MSP430 :: R6W , MSP430 :: R7W , MSP430 :: R8W , MSP430 :: R9W , MSP430 :: R10W , MSP430 :: R11W , 0 } ; static const unsigned CalleeSavedRegsIntr [ ] = { MSP430 :: FPW , MSP430 :: R5W , MSP430 :: R6W , MSP430 :: R7W , MSP430 :: R8W , MSP430 :: R9W , MSP430 :: R10W , MSP430 :: R11W , MSP430 :: R12W , MSP430 :: R13W , MSP430 :: R14W , MSP430 :: R15W , 0 } ; static const unsigned CalleeSavedRegsIntrFP [ ] = { MSP430 :: R5W , MSP430 :: R6W , MSP430 :: R7W , MSP430 :: R8W , MSP430 :: R9W , MSP430 :: R10W , MSP430 :: R11W , MSP430 :: R12W , MSP430 :: R13W , MSP430 :: R14W , MSP430 :: R15W , 0 } ; if ( TFI -> hasFP ( * MF ) ) return ( F -> getCallingConv ( ) == CallingConv :: MSP430_INTR ? CalleeSavedRegsIntrFP : CalleeSavedRegsFP ) ; else return ( F -> getCallingConv ( ) == CallingConv :: MSP430_INTR ? CalleeSavedRegsIntr : CalleeSavedRegs ) ; } </s>


<s>
TargetTransformInfo
::
PopcntSupportKind
AArch64TTIImpl
::
getPopcntSupport
(
unsigned
TyWidth
)
{
assert
(
isPowerOf2_32
(
TyWidth
)
&&
"Ty width must be power of 2"
)
;
if
(
TyWidth
==
32
||
TyWidth
==
64
)
return
TTI
::
PSK_FastHardware
;
return
TTI
::
PSK_Software
;
}
</s>

Return hardware support for population count .


<s> bool X86FrameLowering :: enableShrinkWrapping ( const MachineFunction & MF ) const { bool CompactUnwind = MF . getMMI ( ) . getContext ( ) . getObjectFileInfo ( ) -> getCompactUnwindSection ( ) != nullptr ; return ( MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) || hasFP ( MF ) || ! CompactUnwind ) && MF . getFunction ( ) . getCallingConv ( ) != CallingConv :: HiPE && ! MF . shouldSplitStack ( ) ; } </s>

Returns true if the target will correctly handle shrink wrapping .


"Basic block should contain at least a RET but is empty"

runOnMachineFunction - Emit the function body .


<s> unsigned MipsInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( ( Opc == Mips :: LW ) || ( Opc == Mips :: LW_P8 ) || ( Opc == Mips :: LD ) || ( Opc == Mips :: LD_P8 ) || ( Opc == Mips :: LWC1 ) || ( Opc == Mips :: LWC1_P8 ) || ( Opc == Mips :: LDC1 ) || ( Opc == Mips :: LDC164 ) || ( Opc == Mips :: LDC164_P8 ) ) { if ( ( MI -> getOperand ( 1 ) . isFI ( ) ) && ( MI -> getOperand ( 2 ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( 2 ) ) ) ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> int arc_eligible_for_epilogue_delay ( rtx trial , int slot ) { gcc_assert ( ! slot ) ; if ( get_attr_length ( trial ) == 1 && current_frame_info . gmask == 0 && ! reg_mentioned_p ( stack_pointer_rtx , PATTERN ( trial ) ) && ! reg_mentioned_p ( frame_pointer_rtx , PATTERN ( trial ) ) ) return 1 ; return 0 ; } </s>

Return true if TRIAL is a valid insn for the epilogue delay slot . Any single length instruction which does n't reference the stack or frame pointer or any call-saved register is OK. SLOT will always be 0 .


<s>
static
void
riscv_print_operand_reloc
(
FILE
*
file
,
rtx
op
,
bool
hi_reloc
)
{
const
char
*
reloc
;
switch
(
riscv_classify_symbolic_expression
(
op
)
)
{
case
SYMBOL_ABSOLUTE
:
reloc
=
hi_reloc
"%hi"
:
"%lo"
;
break
;
case
SYMBOL_PCREL
:
reloc
=
hi_reloc
"%pcrel_hi"
:
"%pcrel_lo"
;
break
;
case
SYMBOL_TLS_LE
:
reloc
=
hi_reloc
"%tprel_hi"
:
"%tprel_lo"
;
break
;
default
:
output_operand_lossage
(
"invalid use of '%%%c'"
,
hi_reloc
'h'
:
'R'
)
;
return
;
}
fprintf
(
file
,
"%s("
,
reloc
)
;
output_addr_const
(
file
,
riscv_strip_unspec_address
(
op
)
)
;
fputc
(
')'
,
file
)
;
}
</s>

Print symbolic operand OP , which is part of a HIGH or LO_SUM in context CONTEXT . HI_RELOC indicates a high-part reloc .


<s> static enum rs6000_reg_type register_to_reg_type ( rtx reg , bool * is_altivec ) { HOST_WIDE_INT regno ; enum reg_class rclass ; if ( GET_CODE ( reg ) == SUBREG ) reg = SUBREG_REG ( reg ) ; if ( ! REG_P ( reg ) ) return NO_REG_TYPE ; regno = REGNO ( reg ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) { if ( ! lra_in_progress && ! reload_completed ) return PSEUDO_REG_TYPE ; regno = true_regnum ( reg ) ; if ( regno < 0 || regno >= FIRST_PSEUDO_REGISTER ) return PSEUDO_REG_TYPE ; } gcc_assert ( regno >= 0 ) ; if ( is_altivec && ALTIVEC_REGNO_P ( regno ) ) * is_altivec = true ; rclass = rs6000_regno_regclass [ regno ] ; return reg_class_to_reg_type [ ( int ) rclass ] ; } </s>

Classify a register type . Because the FMRGOW/FMRGEW instructions only work on traditional floating point registers , and the VMRGOW/VMRGEW instructions only work on the traditional altivec registers , note if an altivec register was chosen .


<s> TargetLowering :: ConstraintWeight RISCVTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'a' : case 'd' : case 'r' : if ( CallOperandVal -> getType ( ) -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatingPointTy ( ) ) weight = CW_Register ; break ; case 'I' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isUInt < 8 > ( C -> getZExtValue ( ) ) ) weight = CW_Constant ; break ; case 'J' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isUInt < 12 > ( C -> getZExtValue ( ) ) ) weight = CW_Constant ; break ; case 'K' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isInt < 16 > ( C -> getSExtValue ( ) ) ) weight = CW_Constant ; break ; case 'L' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isInt < 20 > ( C -> getSExtValue ( ) ) ) weight = CW_Constant ; break ; case 'M' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( C -> getZExtValue ( ) == 0x7fffffff ) weight = CW_Constant ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> void x86_order_regs_for_local_alloc ( void ) { int pos = 0 ; int i ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( GENERAL_REGNO_P ( i ) && call_used_or_fixed_reg_p ( i ) ) reg_alloc_order [ pos ++ ] = i ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( GENERAL_REGNO_P ( i ) && ! call_used_or_fixed_reg_p ( i ) ) reg_alloc_order [ pos ++ ] = i ; if ( ! TARGET_SSE_MATH ) for ( i = FIRST_STACK_REG ; i <= LAST_STACK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_SSE_REG ; i <= LAST_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_REX_SSE_REG ; i <= LAST_REX_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_MASK_REG ; i <= LAST_MASK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; if ( TARGET_SSE_MATH ) for ( i = FIRST_STACK_REG ; i <= LAST_STACK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_MMX_REG ; i <= LAST_MMX_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; while ( pos < FIRST_PSEUDO_REGISTER ) reg_alloc_order [ pos ++ ] = 0 ; } </s>

Order the registers for register allocator .


"\t.repeat (gcc@n@bytes - gcc@here) / 4\n"

Output text that to appear at the beginning of an assembler file .


<s> bool SystemZAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == ".insn" ) return ParseDirectiveInsn ( DirectiveID . getLoc ( ) ) ; if ( IDVal == ".machine" ) return ParseDirectiveMachine ( DirectiveID . getLoc ( ) ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> const char * SparcTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return nullptr ; case SPISD :: CMPICC : return "SPISD::CMPICC" ; case SPISD :: CMPFCC : return "SPISD::CMPFCC" ; case SPISD :: BRICC : return "SPISD::BRICC" ; case SPISD :: BRXCC : return "SPISD::BRXCC" ; case SPISD :: BRFCC : return "SPISD::BRFCC" ; case SPISD :: SELECT_ICC : return "SPISD::SELECT_ICC" ; case SPISD :: SELECT_XCC : return "SPISD::SELECT_XCC" ; case SPISD :: SELECT_FCC : return "SPISD::SELECT_FCC" ; case SPISD :: Hi : return "SPISD::Hi" ; case SPISD :: Lo : return "SPISD::Lo" ; case SPISD :: FTOI : return "SPISD::FTOI" ; case SPISD :: ITOF : return "SPISD::ITOF" ; case SPISD :: FTOX : return "SPISD::FTOX" ; case SPISD :: XTOF : return "SPISD::XTOF" ; case SPISD :: CALL : return "SPISD::CALL" ; case SPISD :: RET_FLAG : return "SPISD::RET_FLAG" ; case SPISD :: GLOBAL_BASE_REG : return "SPISD::GLOBAL_BASE_REG" ; case SPISD :: FLUSHW : return "SPISD::FLUSHW" ; case SPISD :: TLS_ADD : return "SPISD::TLS_ADD" ; case SPISD :: TLS_LD : return "SPISD::TLS_LD" ; case SPISD :: TLS_CALL : return "SPISD::TLS_CALL" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s>
void
HexagonHazardRecognizer
::
AdvanceCycle
(
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Advance cycle, clear state\n"
)
;
Resources
->
clearResources
(
)
;
if
(
DotCurPNum
!=
1
&&
DotCurPNum
!=
(
int
)
PacketNum
)
{
UsesDotCur
=
nullptr
;
DotCurPNum
=
1
;
}
UsesLoad
=
false
;
PrefVectorStoreNew
=
nullptr
;
PacketNum
++
;
RegDefs
.
clear
(
)
;
}
</s>

AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled can not issue in the current cycle , either because of latency or resource conflicts .


<s> bool isMachineVerifierClean ( ) const override { return false ; } </s>

Returns true if the target is expected to pass all machine verifier checks .


<s> SDValue NVPTXTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { CodeGenOpt :: Level OptLevel = getTargetMachine ( ) . getOptLevel ( ) ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : case ISD :: FADD : return PerformADDCombine ( N , DCI , STI , OptLevel ) ; case ISD :: MUL : return PerformMULCombine ( N , DCI , OptLevel ) ; case ISD :: SHL : return PerformSHLCombine ( N , DCI , OptLevel ) ; case ISD :: AND : return PerformANDCombine ( N , DCI ) ; case ISD :: SELECT : return PerformSELECTCombine ( N , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

NVPTX NVPTX ISD::ADD ISD::FADD ISD::MUL ISD::SHL ISD::AND ISD::SELECT


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"rvex Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
int
X86TTIImpl
::
getScalarizationOverhead
(
Type
*
Ty
,
bool
Insert
,
bool
Extract
)
{
assert
(
Ty
->
isVectorTy
(
)
&&
"Can only scalarize vectors"
)
;
int
Cost
=
0
;
for
(
int
i
=
0
,
e
=
Ty
->
getVectorNumElements
(
)
;
i
<
e
;
++
i
)
{
if
(
Insert
)
Cost
+=
getVectorInstrCost
(
Instruction
::
InsertElement
,
Ty
,
i
)
;
if
(
Extract
)
Cost
+=
getVectorInstrCost
(
Instruction
::
ExtractElement
,
Ty
,
i
)
;
}
return
Cost
;
}
</s>

Estimate the overhead of scalarizing an instruction .


<s> const MCFixupKindInfo & AMDGPUAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ AMDGPU :: NumTargetFixupKinds ] = { { "fixup_si_sopp_br" , 0 , 16 , MCFixupKindInfo :: FKF_IsPCRel } , { "fixup_si_rodata" , 0 , 32 , 0 } , { "fixup_si_end_of_text" , 0 , 32 , MCFixupKindInfo :: FKF_IsPCRel } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } </s>


<s> bool lowerCall ( MachineIRBuilder & MIRBuilder , CallingConv :: ID CallConv , const MachineOperand & Callee , const ArgInfo & OrigRet , ArrayRef < ArgInfo > OrigArgs ) const override { return lowerCall ( MIRBuilder , CallConv , Callee , OrigRet , OrigArgs , 0 ) ; } </s>

This hook must be implemented to lower the given call instruction , including argument and return value marshalling .


<s> static machine_mode aarch64_simd_container_mode ( scalar_mode mode , poly_int64 width ) { if ( TARGET_SVE && known_eq ( width , BITS_PER_SVE_VECTOR ) ) switch ( mode ) { case E_DFmode : return VNx2DFmode ; case E_SFmode : return VNx4SFmode ; case E_HFmode : return VNx8HFmode ; case E_DImode : return VNx2DImode ; case E_SImode : return VNx4SImode ; case E_HImode : return VNx8HImode ; case E_QImode : return VNx16QImode ; default : return word_mode ; } gcc_assert ( known_eq ( width , 64 ) || known_eq ( width , 128 ) ) ; if ( TARGET_SIMD ) { if ( known_eq ( width , 128 ) ) switch ( mode ) { case E_DFmode : return V2DFmode ; case E_SFmode : return V4SFmode ; case E_HFmode : return V8HFmode ; case E_SImode : return V4SImode ; case E_HImode : return V8HImode ; case E_QImode : return V16QImode ; case E_DImode : return V2DImode ; default : break ; } else switch ( mode ) { case E_SFmode : return V2SFmode ; case E_HFmode : return V4HFmode ; case E_SImode : return V2SImode ; case E_HImode : return V4HImode ; case E_QImode : return V8QImode ; default : break ; } } return word_mode ; } </s>

Return appropriate SIMD container for MODE within a vector of WIDTH bits .


<s> int registers_ok_for_ldd_peep ( rtx reg1 , rtx reg2 ) { if ( GET_CODE ( reg1 ) != REG || GET_CODE ( reg2 ) != REG ) return 0 ; if ( REGNO ( reg1 ) % 2 != 0 ) return 0 ; if ( TARGET_V9 && SPARC_INT_REG_P ( REGNO ( reg1 ) ) ) return 0 ; return ( REGNO ( reg1 ) == REGNO ( reg2 ) - 1 ) ; } </s>

Return 1 if REGNO ( reg1 ) is even and REGNO ( reg1 ) == REGNO ( reg2 ) - 1 . This makes them candidates for using ldd and std insns . Note reg1 and reg2 * must * be hard registers .


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> const MipsTargetLowering * MipsTargetLowering :: create ( const MipsTargetMachine & TM , const MipsSubtarget & STI ) { if ( STI . inMips16Mode ( ) ) return llvm :: createMips16TargetLowering ( TM , STI ) ; return llvm :: createMipsSETargetLowering ( TM , STI ) ; } </s>


"Floating-point constant is not a positive zero."

Emit the floating-point constant +0.0 in a register using target- specific logic .


<s> bool AMDGPUPassConfig :: addPostRegAlloc ( ) { const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; addPass ( createSIShrinkInstructionsPass ( ) ) ; if ( ST . getGeneration ( ) > AMDGPUSubtarget :: NORTHERN_ISLANDS ) { addPass ( createSIInsertWaits ( * TM ) ) ; } return false ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


"Do not know how to custom type legalize this operation!"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s>
void
CAHPFrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
unsigned
FPReg
=
getFPReg
(
)
;
unsigned
SPReg
=
getSPReg
(
)
;
DebugLoc
DL
;
determineFrameLayout
(
MF
)
;
uint64_t
StackSize
=
MFI
.
getStackSize
(
)
;
if
(
StackSize
==
0
&&
!
MFI
.
adjustsStack
(
)
)
return
;
adjustReg
(
MBB
,
MBBI
,
DL
,
SPReg
,
SPReg
,
StackSize
,
MachineInstr
::
FrameSetup
)
;
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
.
getCalleeSavedInfo
(
)
;
std
::
advance
(
MBBI
,
CSI
.
size
(
)
)
;
if
(
hasFP
(
MF
)
)
adjustReg
(
MBB
,
MBBI
,
DL
,
FPReg
,
SPReg
,
StackSize
,
MachineInstr
::
FrameSetup
)
;
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

CAHP
CAHP
"Shrink-wrapping not yet supported"
0


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> bool ARMTargetLowering :: isLegalAddImmediate ( int64_t Imm ) const { return ARM_AM :: getSOImmVal ( Imm ) != - 1 ; } </s>

Return true if the specified immediate is legal add immediate , that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register .


<s> AArch64Subtarget & AArch64Subtarget :: initializeSubtargetDependencies ( StringRef FS ) { if ( CPUString . empty ( ) ) CPUString = "generic" ; ParseSubtargetFeatures ( CPUString , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> unsigned PPCTargetLowering :: combineRepeatedFPDivisors ( ) const { switch ( Subtarget . getCPUDirective ( ) ) { default : return 3 ; case PPC :: DIR_440 : case PPC :: DIR_A2 : case PPC :: DIR_E500 : case PPC :: DIR_E500mc : case PPC :: DIR_E5500 : return 2 ; } } </s>

Indicate whether this target prefers to combine FDIVs with the same divisor .


<s> int aarch64_epilogue_uses ( int regno ) { if ( epilogue_completed ) { if ( regno == LR_REGNUM ) return 1 ; } return 0 ; } </s>

Return 1 if the register is used by the epilogue . We need to say the return register is used , but only after epilogue generation is complete . Note that in the case of sibcalls , the values `` used by the epilogue '' are considered live at the start of the called function . For SIMD functions we need to return 1 for FP registers that are saved and restored by a function but are not zero in call_used_regs . If we do not do this optimizations may remove the restore of the register .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { const LanaiSubtarget & Subtarget = MF . getSubtarget < LanaiSubtarget > ( ) ; TII = Subtarget . getInstrInfo ( ) ; TRI = Subtarget . getRegisterInfo ( ) ; bool Changed = false ; for ( MachineFunction :: iterator FI = MF . begin ( ) , FE = MF . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> const SNESRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool MipsCallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , unsigned VReg ) const { MachineInstrBuilder Ret = MIRBuilder . buildInstrNoInsert ( Mips :: RetRA ) ; if ( Val != nullptr ) { if ( ! isSupportedType ( Val -> getType ( ) ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const MipsTargetLowering & TLI = * getTLI < MipsTargetLowering > ( ) ; SmallVector < ArgInfo , 8 > RetInfos ; SmallVector < unsigned , 8 > OrigArgIndices ; ArgInfo ArgRetInfo ( VReg , Val -> getType ( ) ) ; setArgFlags ( ArgRetInfo , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( ArgRetInfo , 0 , RetInfos , OrigArgIndices ) ; SmallVector < ISD :: OutputArg , 8 > Outs ; subTargetRegTypeForCallingConv ( MIRBuilder , RetInfos , OrigArgIndices , [ & ] ( ISD :: ArgFlagsTy flags , EVT vt , EVT argvt , bool used , unsigned origIdx , unsigned partOffs ) { Outs . emplace_back ( flags , vt , argvt , used , origIdx , partOffs ) ; } ) ; SmallVector < CCValAssign , 16 > ArgLocs ; MipsCCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , TLI . CCAssignFnForReturn ( ) ) ; OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , Ret ) ; if ( ! RetHandler . handle ( ArgLocs , RetInfos ) ) { return false ; } } MIRBuilder . insertInstr ( Ret ) ; return true ; } </s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> static rtx gen_conditional_move ( rtx cmp ) { enum rtx_code code = GET_CODE ( cmp ) ; rtx op0 = branch_cmp [ 0 ] ; rtx op1 = branch_cmp [ 1 ] ; if ( branch_type == CMP_SI ) { if ( ( code == GT ) && ( op1 == constm1_rtx ) ) { code = GE ; op1 = const0_rtx ; } cmp = gen_rtx_fmt_ee ( code , VOIDmode , cc0_rtx , const0_rtx ) ; if ( boolean_operator ( cmp , VOIDmode ) ) { if ( op0 == const0_rtx ) { op0 = op1 ; op1 = const0_rtx ; } if ( op1 != const0_rtx ) { op0 = expand_binop ( SImode , sub_optab , op0 , op1 , 0 , 0 , OPTAB_LIB_WIDEN ) ; op1 = const0_rtx ; } } else if ( branch_operator ( cmp , VOIDmode ) ) { if ( op0 == const0_rtx ) { op0 = op1 ; op1 = const0_rtx ; switch ( code ) { case LT : code = GE ; break ; case GE : code = LT ; break ; default : gcc_unreachable ( ) ; } } if ( op1 != const0_rtx ) return 0 ; } else return 0 ; return gen_rtx_fmt_ee ( code , VOIDmode , op0 , op1 ) ; } if ( TARGET_HARD_FLOAT && ( branch_type == CMP_SF ) ) return gen_float_relational ( code , op0 , op1 ) ; return 0 ; } </s>

Emit the common code for conditional moves . OPERANDS is the array of operands passed to the conditional move define_expand .


<s> bool GBZ80PassConfig :: addInstSelector ( ) { addPass ( createGBZ80ISelDag ( getGBZ80TargetMachine ( ) , getOptLevel ( ) ) ) ; addPass ( createGBZ80PostISelPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool PPCTTIImpl :: isLSRCostLess ( const TargetTransformInfo :: LSRCost & C1 , const TargetTransformInfo :: LSRCost & C2 ) { if ( ! LsrNoInsnsCost ) return std :: tie ( C1 . Insns , C1 . NumRegs , C1 . AddRecCost , C1 . NumIVMuls , C1 . NumBaseAdds , C1 . ScaleCost , C1 . ImmCost , C1 . SetupCost ) < std :: tie ( C2 . Insns , C2 . NumRegs , C2 . AddRecCost , C2 . NumIVMuls , C2 . NumBaseAdds , C2 . ScaleCost , C2 . ImmCost , C2 . SetupCost ) ; else return TargetTransformInfoImplBase :: isLSRCostLess ( C1 , C2 ) ; } </s>

Return true if LSR cost of C1 is lower than C2 .


<s> bool isNonallocatableRegisterCalleeSave ( MCRegister Reg ) const override { return Reg == PPC :: LR || Reg == PPC :: LR8 ; } </s>

Some targets have non-allocatable registers that are n't technically part of the explicit callee saved register list , but should be handled as such in certain cases .


<s>
StringRef
getPassName
(
)
const
override
{
return
"R600 Emit Clause Markers Pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static void microblaze_block_move_loop ( rtx dest , rtx src , HOST_WIDE_INT length ) { rtx_code_label * label ; rtx src_reg , dest_reg , final_src ; HOST_WIDE_INT leftover ; leftover = length % MAX_MOVE_BYTES ; length -= leftover ; microblaze_adjust_block_mem ( src , MAX_MOVE_BYTES , & src_reg , & src ) ; microblaze_adjust_block_mem ( dest , MAX_MOVE_BYTES , & dest_reg , & dest ) ; final_src = expand_simple_binop ( Pmode , PLUS , src_reg , GEN_INT ( length ) , 0 , 0 , OPTAB_WIDEN ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; microblaze_block_move_straight ( dest , src , MAX_MOVE_BYTES ) ; emit_move_insn ( src_reg , plus_constant ( Pmode , src_reg , MAX_MOVE_BYTES ) ) ; emit_move_insn ( dest_reg , plus_constant ( Pmode , dest_reg , MAX_MOVE_BYTES ) ) ; emit_insn ( gen_cbranchsi4 ( gen_rtx_NE ( SImode , src_reg , final_src ) , src_reg , final_src , label ) ) ; if ( leftover ) microblaze_block_move_straight ( dest , src , leftover ) ; } </s>

Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES per iteration . LENGTH must be at least MAX_MOVE_BYTES . Assume that the memory regions do not overlap .


"Wrong register class for memory operand."

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> bool MipsFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || TRI -> needsStackRealignment ( MF ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> const SHUXIInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s>
const
char
*
getPassName
(
)
const
override
{
return
"R600 Vector Registers Merge Pass"
;
}
</s>


<s> static bool mips_vectorize_vec_perm_const ( machine_mode vmode , machine_mode op_mode , rtx target , rtx op0 , rtx op1 , const vec_perm_indices & sel ) { if ( vmode != op_mode ) return false ; struct expand_vec_perm_d d ; int i , nelt , which ; unsigned char orig_perm [ MAX_VECT_LEN ] ; bool ok ; d . target = target ; if ( op0 ) { rtx nop0 = force_reg ( vmode , op0 ) ; if ( op0 == op1 ) op1 = nop0 ; op0 = nop0 ; } if ( op1 ) op1 = force_reg ( vmode , op1 ) ; d . op0 = op0 ; d . op1 = op1 ; d . vmode = vmode ; gcc_assert ( VECTOR_MODE_P ( vmode ) ) ; d . nelt = nelt = GET_MODE_NUNITS ( vmode ) ; d . testing_p = ! target ; memset ( orig_perm , 0 , MAX_VECT_LEN ) ; for ( i = which = 0 ; i < nelt ; ++ i ) { int ei = sel [ i ] & ( 2 * nelt - 1 ) ; which |= ( ei < nelt ? 1 : 2 ) ; orig_perm [ i ] = ei ; } memcpy ( d . perm , orig_perm , MAX_VECT_LEN ) ; switch ( which ) { default : gcc_unreachable ( ) ; case 3 : d . one_vector_p = false ; if ( d . testing_p || ! rtx_equal_p ( d . op0 , d . op1 ) ) break ; case 2 : for ( i = 0 ; i < nelt ; ++ i ) d . perm [ i ] &= nelt - 1 ; d . op0 = d . op1 ; d . one_vector_p = true ; break ; case 1 : d . op1 = d . op0 ; d . one_vector_p = true ; break ; } if ( d . testing_p ) { d . target = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 1 ) ; d . op1 = d . op0 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 2 ) ; if ( ! d . one_vector_p ) d . op1 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 3 ) ; start_sequence ( ) ; ok = mips_expand_vec_perm_const_1 ( & d ) ; end_sequence ( ) ; return ok ; } ok = mips_expand_vec_perm_const_1 ( & d ) ; if ( ! ok && which == 3 ) { d . op0 = op0 ; d . op1 = op1 ; d . one_vector_p = false ; memcpy ( d . perm , orig_perm , MAX_VECT_LEN ) ; ok = mips_expand_vec_perm_const_1 ( & d ) ; } return ok ; } </s>


<s> bool AMDGPUCFGStructurizer :: prepare ( ) { bool Changed = false ; LLVM_DEBUG ( dbgs ( ) << "AMDGPUCFGStructurizer::prepare\n" ; ) ; orderBlocks ( FuncRep ) ; SmallVector < MachineBasicBlock * , DEFAULT_VEC_SLOTS > RetBlks ; for ( MachineLoopInfo :: iterator It = MLI -> begin ( ) , E = MLI -> end ( ) ; It != E ; ++ It ) { MachineLoop * LoopRep = ( * It ) ; MBBVector ExitingMBBs ; LoopRep -> getExitingBlocks ( ExitingMBBs ) ; if ( ExitingMBBs . size ( ) == 0 ) { MachineBasicBlock * DummyExitBlk = normalizeInfiniteLoopExit ( LoopRep ) ; if ( DummyExitBlk ) RetBlks . push_back ( DummyExitBlk ) ; } } for ( SmallVectorImpl < MachineBasicBlock * > :: const_iterator It = OrderedBlks . begin ( ) , E = OrderedBlks . end ( ) ; It != E ; ++ It ) { MachineBasicBlock * MBB = * It ; removeUnconditionalBranch ( MBB ) ; removeRedundantConditionalBranch ( MBB ) ; if ( isReturnBlock ( MBB ) ) { RetBlks . push_back ( MBB ) ; } assert ( MBB -> succ_size ( ) <= 2 ) ; } if ( RetBlks . size ( ) >= 2 ) { addDummyExitBlock ( RetBlks ) ; Changed = true ; } return Changed ; } </s>

prepare - Reset state and prepare for a new spill placement computation .


"Patmos Single-Path Bundling (machine code)"


<s>
void
ARMHazardRecognizer
::
EmitInstruction
(
SUnit
*
SU
)
{
MachineInstr
*
MI
=
SU
->
getInstr
(
)
;
unsigned
Opcode
=
MI
->
getOpcode
(
)
;
if
(
ITBlockSize
)
{
ITBlockSize
;
}
else
if
(
Opcode
==
ARM
::
t2IT
)
{
unsigned
Mask
=
MI
->
getOperand
(
1
)
.
getImm
(
)
;
unsigned
NumTZ
=
CountTrailingZeros_32
(
Mask
)
;
assert
(
NumTZ
<=
3
&&
"Invalid IT mask!"
)
;
ITBlockSize
=
4
NumTZ
;
MachineBasicBlock
::
iterator
I
=
MI
;
for
(
unsigned
i
=
0
;
i
<
ITBlockSize
;
++
i
)
{
do
{
++
I
;
}
while
(
I
->
isDebugValue
(
)
)
;
ITBlockMIs
[
ITBlockSize
1
i
]
=
&
*
I
;
}
}
if
(
!
MI
->
isDebugValue
(
)
)
{
LastMI
=
MI
;
FpMLxStalls
=
0
;
}
ScoreboardHazardRecognizer
::
EmitInstruction
(
SU
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> const MipsSubtarget * getSubtargetImpl ( ) const override { if ( Subtarget ) return Subtarget ; return & DefaultSubtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static bool c6x_in_small_data_p ( const_tree exp ) { if ( TREE_CODE ( exp ) == STRING_CST ) return false ; if ( TREE_CODE ( exp ) == FUNCTION_DECL ) return false ; if ( TREE_CODE ( exp ) == VAR_DECL && DECL_WEAK ( exp ) ) return false ; if ( TREE_CODE ( exp ) == VAR_DECL && DECL_SECTION_NAME ( exp ) ) { const char * section = DECL_SECTION_NAME ( exp ) ; if ( strcmp ( section , ".neardata" ) == 0 || startswith ( section , ".neardata." ) || startswith ( section , ".gnu.linkonce.s." ) || strcmp ( section , ".bss" ) == 0 || startswith ( section , ".bss." ) || startswith ( section , ".gnu.linkonce.sb." ) || strcmp ( section , ".rodata" ) == 0 || startswith ( section , ".rodata." ) || startswith ( section , ".gnu.linkonce.s2." ) ) return true ; } else return PLACE_IN_SDATA_P ( exp ) ; return false ; } </s>

Return true if EXP goes in small data/bss .


<s> bool RISCVRegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , Register Reg , int & FrameIdx ) const { const auto * RVFI = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; if ( ! RVFI -> useSaveRestoreLibCalls ( MF ) ) return false ; auto FII = FixedCSRFIMap . find ( Reg ) ; if ( FII == FixedCSRFIMap . end ( ) ) return false ; FrameIdx = FII -> second ; return true ; } </s>

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register .


<s> bool AMDGPULateCodeGenPrepare :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; AC = & getAnalysis < AssumptionCacheTracker > ( ) . getAssumptionCache ( F ) ; DA = & getAnalysis < LegacyDivergenceAnalysis > ( ) ; bool Changed = false ; for ( auto & BB : F ) for ( auto BI = BB . begin ( ) , BE = BB . end ( ) ; BI != BE ; ) { Instruction * I = & * BI ++ ; Changed |= visit ( * I ) ; } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> unsigned MipsInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( ( Opc == Mips :: SW ) || ( Opc == Mips :: SW_P8 ) || ( Opc == Mips :: SD ) || ( Opc == Mips :: SD_P8 ) || ( Opc == Mips :: SWC1 ) || ( Opc == Mips :: SWC1_P8 ) || ( Opc == Mips :: SDC1 ) || ( Opc == Mips :: SDC164 ) || ( Opc == Mips :: SDC164_P8 ) ) { if ( ( MI -> getOperand ( 1 ) . isFI ( ) ) && ( MI -> getOperand ( 2 ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( 2 ) ) ) ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64Bit ) : LLVMTargetMachine ( T , TT , CPU , FS , RM , CM , OL ) , Subtarget ( TT , CPU , FS , StackAlignmentOverride , is64Bit ) , FrameLowering ( * this , Subtarget ) , ELFWriterInfo ( is64Bit , true ) { if ( getRelocationModel ( ) == Reloc :: Static ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . is64Bit ( ) ) { Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; } else if ( Subtarget . isTargetCygMing ( ) ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . isTargetDarwin ( ) ) { if ( getRelocationModel ( ) == Reloc :: PIC_ ) Subtarget . setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; Subtarget . setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( Subtarget . isTargetELF ( ) ) { Subtarget . setPICStyle ( PICStyles :: GOT ) ; } if ( FloatABIType == FloatABI :: Default ) FloatABIType = FloatABI :: Hard ; } </s>


"Unable to generate load/store offset for fusion"

Emit a D-form load or store instruction that is the second instruction of a fusion sequence .


<s>
StringRef
getPassName
(
)
const
override
{
return
"SystemZ Comparison Elimination"
;
}
</s>

SystemZ
"SystemZ Comparison Elimination"


<s> void TLCS900InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s>
unsigned
HexagonInstrInfo
::
reduceLoopCount
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
&
PreHeader
,
MachineInstr
*
IndVar
,
MachineInstr
&
Cmp
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
SmallVectorImpl
<
MachineInstr
*
>
&
PrevInsts
,
unsigned
Iter
,
unsigned
MaxIter
)
const
{
assert
(
(
!
IndVar
)
&&
isEndLoopN
(
Cmp
.
getOpcode
(
)
)
&&
"Expecting a hardware loop"
)
;
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
DebugLoc
DL
=
Cmp
.
getDebugLoc
(
)
;
SmallPtrSet
<
MachineBasicBlock
*
,
8
>
VisitedBBs
;
MachineInstr
*
Loop
=
findLoopInstr
(
&
MBB
,
Cmp
.
getOpcode
(
)
,
Cmp
.
getOperand
(
0
)
.
getMBB
(
)
,
VisitedBBs
)
;
if
(
!
Loop
)
return
0
;
if
(
Loop
->
getOpcode
(
)
==
Hexagon
::
J2_loop0i
||
Loop
->
getOpcode
(
)
==
Hexagon
::
J2_loop1i
)
{
int64_t
Offset
=
Loop
->
getOperand
(
1
)
.
getImm
(
)
;
if
(
Offset
<=
1
)
Loop
->
eraseFromParent
(
)
;
else
Loop
->
getOperand
(
1
)
.
setImm
(
Offset
1
)
;
return
Offset
1
;
}
assert
(
Loop
->
getOpcode
(
)
==
Hexagon
::
J2_loop0r
&&
"Unexpected instruction"
)
;
Register
LoopCount
=
Loop
->
getOperand
(
1
)
.
getReg
(
)
;
unsigned
LoopEnd
=
createVR
(
MF
,
MVT
::
i1
)
;
MachineInstr
*
NewCmp
=
BuildMI
(
&
MBB
,
DL
,
get
(
Hexagon
::
C2_cmpgtui
)
,
LoopEnd
)
.
addReg
(
LoopCount
)
.
addImm
(
1
)
;
unsigned
NewLoopCount
=
createVR
(
MF
,
MVT
::
i32
)
;
MachineInstr
*
NewAdd
=
BuildMI
(
&
MBB
,
DL
,
get
(
Hexagon
::
A2_addi
)
,
NewLoopCount
)
.
addReg
(
LoopCount
)
.
addImm
(
1
)
;
const
HexagonRegisterInfo
&
HRI
=
*
Subtarget
.
getRegisterInfo
(
)
;
for
(
SmallVectorImpl
<
MachineInstr
*
>
::
iterator
I
=
PrevInsts
.
begin
(
)
,
E
=
PrevInsts
.
end
(
)
;
I
!=
E
;
++
I
)
(
*
I
)
->
substituteRegister
(
LoopCount
,
NewLoopCount
,
0
,
HRI
)
;
PrevInsts
.
clear
(
)
;
PrevInsts
.
push_back
(
NewCmp
)
;
PrevInsts
.
push_back
(
NewAdd
)
;
if
(
Iter
==
MaxIter
)
BuildMI
(
&
MBB
,
DL
,
get
(
Hexagon
::
J2_loop0r
)
)
.
addMBB
(
Loop
->
getOperand
(
0
)
.
getMBB
(
)
)
.
addReg
(
NewLoopCount
)
;
if
(
Iter
==
0
)
Loop
->
eraseFromParent
(
)
;
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
Hexagon
::
J2_jumpf
)
)
;
Cond
.
push_back
(
NewCmp
->
getOperand
(
0
)
)
;
return
NewLoopCount
;
}
</s>

Generate code to reduce the loop iteration by one and check if the loop is finished .


<s> ArrayRef < std :: pair < int , const char * >> WebAssemblyInstrInfo :: getSerializableTargetIndices ( ) const { static const std :: pair < int , const char * > TargetIndices [ ] = { { WebAssembly :: TI_LOCAL_START , "wasm-local-start" } , { WebAssembly :: TI_GLOBAL_START , "wasm-global-start" } , { WebAssembly :: TI_OPERAND_STACK_START , "wasm-operator-stack-start" } } ; return makeArrayRef ( TargetIndices ) ; } </s>

Return an array that contains the ids of the target indices ( used for the TargetIndex machine operand ) and their names .


<s> void frv_expand_epilogue ( bool emit_return ) { frv_stack_t * info = frv_stack_info ( ) ; rtx fp = frame_pointer_rtx ; rtx sp = stack_pointer_rtx ; rtx return_addr ; int fp_offset ; fp_offset = info -> reg_offset [ FRAME_POINTER_REGNUM ] ; if ( ! crtl -> sp_is_unchanging ) emit_insn ( gen_addsi3 ( sp , fp , frv_frame_offset_rtx ( - fp_offset ) ) ) ; frv_frame_access_standard_regs ( FRV_LOAD , info ) ; if ( info -> save_p [ LR_REGNO ] ) { int lr_offset ; rtx mem ; lr_offset = info -> reg_offset [ LR_REGNO ] ; if ( frame_pointer_needed ) mem = frv_frame_mem ( Pmode , fp , lr_offset - fp_offset ) ; else mem = frv_frame_mem ( Pmode , sp , lr_offset ) ; return_addr = gen_rtx_REG ( Pmode , TEMP_REGNO ) ; emit_insn ( gen_rtx_SET ( VOIDmode , return_addr , mem ) ) ; } else return_addr = gen_rtx_REG ( Pmode , LR_REGNO ) ; if ( frame_pointer_needed ) { emit_insn ( gen_rtx_SET ( VOIDmode , fp , gen_rtx_MEM ( Pmode , fp ) ) ) ; emit_use ( fp ) ; } if ( info -> total_size != 0 ) { rtx offset = frv_frame_offset_rtx ( info -> total_size ) ; emit_insn ( gen_stack_adjust ( sp , sp , offset ) ) ; } if ( crtl -> calls_eh_return ) emit_insn ( gen_stack_adjust ( sp , sp , EH_RETURN_STACKADJ_RTX ) ) ; if ( emit_return ) emit_jump_insn ( gen_epilogue_return ( return_addr ) ) ; else { rtx lr = return_addr ; if ( REGNO ( return_addr ) != LR_REGNO ) { lr = gen_rtx_REG ( Pmode , LR_REGNO ) ; emit_move_insn ( lr , return_addr ) ; } emit_use ( lr ) ; } } </s>

Called after register allocation to add any instructions needed for the epilogue . Using an epilogue insn is favored compared to putting all of the instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook , since it allows the scheduler to intermix instructions with the saves of the caller saved registers . In some cases , it might be necessary to emit a barrier instruction as the last insn to prevent such scheduling .


<s>
bool
AVRAsmBackend
::
writeNopData
(
uint64_t
Count
,
MCObjectWriter
*
OW
)
const
{
assert
(
(
Count
%
2
)
==
0
&&
"NOP instructions must be 2 bytes"
)
;
OW
->
WriteZeros
(
Count
)
;
return
true
;
}
</s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> void xstormy16_expand_epilogue ( ) { struct xstormy16_stack_layout layout ; rtx mem_pop_rtx ; int regno ; const int ifun = xstormy16_interrupt_function_p ( ) ; mem_pop_rtx = gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ; mem_pop_rtx = gen_rtx_MEM ( HImode , mem_pop_rtx ) ; layout = xstormy16_compute_stack_layout ( ) ; if ( layout . locals_size ) { if ( frame_pointer_needed && layout . sp_minus_fp == layout . locals_size ) emit_move_insn ( stack_pointer_rtx , hard_frame_pointer_rtx ) ; else emit_addhi3_postreload ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - layout . locals_size ) ) ; } for ( regno = FIRST_PSEUDO_REGISTER - 1 ; regno >= 0 ; regno -- ) if ( REG_NEEDS_SAVE ( regno , ifun ) ) emit_move_insn ( gen_rtx_REG ( HImode , regno ) , mem_pop_rtx ) ; if ( layout . stdarg_save_size ) emit_addhi3_postreload ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - layout . stdarg_save_size ) ) ; if ( ifun ) emit_jump_insn ( gen_return_internal_interrupt ( ) ) ; else emit_jump_insn ( gen_return_internal ( ) ) ; } </s>

Called after register allocation to add any instructions needed for the epilogue . Using an epilogue insn is favored compared to putting all of the instructions in the TARGET_ASM_FUNCTION_PROLOGUE macro , since it allows the scheduler to intermix instructions with the saves of the caller saved registers . In some cases , it might be necessary to emit a barrier instruction as the last insn to prevent such scheduling .