<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> unsigned int pass_cc_fusion :: execute ( function * ) { cc_fusion ( ) . execute ( ) ; return 0 ; } </s>


<s> static bool rs6000_libgcc_floating_mode_supported_p ( scalar_float_mode mode ) { switch ( mode ) { case E_SFmode : case E_DFmode : case E_TFmode : return true ; case E_KFmode : return TARGET_FLOAT128_TYPE && ! TARGET_IEEEQUAD ; default : return false ; } } </s>

Target hook for libgcc_floating_mode_supported_p .


<s> unsigned getNumFixupKinds ( ) const override { return 0 ; } </s>

Get the number of target specific fixup kinds .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == 0 ) Inst . addOperand ( MCOperand :: CreateImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ; } </s>


<s> static int insn_get_clock ( rtx insn ) { return insn_uid_get_clock ( INSN_UID ( insn ) ) ; } </s>

Return the clock cycle we set for INSN .


<s> SDValue NVPTXTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { CodeGenOpt :: Level OptLevel = getTargetMachine ( ) . getOptLevel ( ) ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : case ISD :: FADD : return PerformADDCombine ( N , DCI , STI , OptLevel ) ; case ISD :: MUL : return PerformMULCombine ( N , DCI , OptLevel ) ; case ISD :: SHL : return PerformSHLCombine ( N , DCI , OptLevel ) ; case ISD :: AND : return PerformANDCombine ( N , DCI ) ; case ISD :: UREM : case ISD :: SREM : return PerformREMCombine ( N , DCI , OptLevel ) ; case ISD :: SETCC : return PerformSETCCCombine ( N , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

NVPTX NVPTX ISD::ADD ISD::FADD ISD::MUL ISD::SHL ISD::AND ISD::UREM ISD::SREM ISD::SETCC


<s> static void get_scratch_register_on_entry ( struct scratch_reg * sr ) { int regno ; sr -> saved = false ; if ( TARGET_64BIT ) { regno = R11_REG ; } else { tree decl = current_function_decl , fntype = TREE_TYPE ( decl ) ; bool fastcall_p = lookup_attribute ( "fastcall" , TYPE_ATTRIBUTES ( fntype ) ) != NULL_TREE ; bool thiscall_p = lookup_attribute ( "thiscall" , TYPE_ATTRIBUTES ( fntype ) ) != NULL_TREE ; bool static_chain_p = DECL_STATIC_CHAIN ( decl ) ; int regparm = ix86_function_regparm ( fntype , decl ) ; int drap_regno = crtl -> drap_reg ? REGNO ( crtl -> drap_reg ) : INVALID_REGNUM ; if ( ( regparm < 1 || ( fastcall_p && ! static_chain_p ) ) && drap_regno != AX_REG ) regno = AX_REG ; else if ( thiscall_p && ! static_chain_p && drap_regno != AX_REG ) regno = AX_REG ; else if ( regparm < 2 && ! thiscall_p && drap_regno != DX_REG ) regno = DX_REG ; else if ( regparm < 3 && ! fastcall_p && ! thiscall_p && ! static_chain_p && drap_regno != CX_REG ) regno = CX_REG ; else if ( ix86_save_reg ( BX_REG , true ) ) regno = BX_REG ; else if ( ! ( regparm == 3 && static_chain_p ) && ix86_save_reg ( SI_REG , true ) ) regno = SI_REG ; else if ( ix86_save_reg ( DI_REG , true ) ) regno = DI_REG ; else { regno = ( drap_regno == AX_REG ? DX_REG : AX_REG ) ; sr -> saved = true ; } } sr -> reg = gen_rtx_REG ( Pmode , regno ) ; if ( sr -> saved ) { rtx insn = emit_insn ( gen_push ( sr -> reg ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } </s>

Return a short-lived scratch register for use on function entry . In 32-bit mode , it is valid only after the registers are saved in the prologue . This register must be released by means of release_scratch_register_on_entry once it is dead .


<s> void rs6000_aix_emit_builtin_unwind_init ( ) { rtx mem ; rtx stack_top = gen_reg_rtx ( Pmode ) ; rtx opcode_addr = gen_reg_rtx ( Pmode ) ; insn_after_throw = gen_reg_rtx ( SImode ) ; mem = gen_rtx_MEM ( Pmode , hard_frame_pointer_rtx ) ; emit_move_insn ( stack_top , mem ) ; mem = gen_rtx_MEM ( Pmode , gen_rtx_PLUS ( Pmode , stack_top , GEN_INT ( 2 * GET_MODE_SIZE ( Pmode ) ) ) ) ; emit_move_insn ( opcode_addr , mem ) ; emit_move_insn ( insn_after_throw , gen_rtx_MEM ( SImode , opcode_addr ) ) ; } </s>

If _Unwind_ * has been called from within the same module , toc register is not guaranteed to be saved to 40 ( 1 ) on function entry . Save it there in that case .


<s> const OR1KRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> MCDisassembler :: DecodeStatus X86GenericDisassembler :: getInstruction ( MCInst & instr , uint64_t & size , const MemoryObject & region , uint64_t address , raw_ostream & vStream , raw_ostream & cStream ) const { InternalInstruction internalInstr ; dlog_t loggerFn = logger ; if ( & vStream == & nulls ( ) ) loggerFn = 0 ; int ret = decodeInstruction ( & internalInstr , regionReader , ( void * ) & region , loggerFn , ( void * ) & vStream , address , fMode ) ; if ( ret ) { size = internalInstr . readerCursor - address ; return Fail ; } else { size = internalInstr . length ; return ( ! translateInstruction ( instr , internalInstr ) ) ? Success : Fail ; } } </s>

Returns the disassembly of a single instruction .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> void relaxInstruction ( const MCInst & , const MCSubtargetInfo & , MCInst & ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s>
bool
TPCInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
OS
,
StringRef
Alias
,
unsigned
OpNo0
,
unsigned
OpNo1
)
{
OS
<<
"\t"
<<
Alias
<<
" "
;
printOperand
(
MI
,
OpNo0
,
OS
)
;
OS
<<
", "
;
printOperand
(
MI
,
OpNo1
,
OS
)
;
return
true
;
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s> bool isLegalMaskedScatter ( Type * Ty , MaybeAlign Alignment ) { return isLegalMaskedGather ( Ty , Alignment ) ; } </s>

Return true if the target supports masked scatter .


<s> static void frv_finish_packet ( void ( * handle_packet ) ( void ) ) { if ( frv_packet . num_insns > 0 ) { handle_packet ( ) ; state_transition ( frv_packet . dfa_state , 0 ) ; frv_start_packet ( ) ; } } </s>

Finish the current packet , if any , and start a new one . Call HANDLE_PACKET with FRV_PACKET describing the completed packet .


<s> bool sparc_expand_conditional_move ( machine_mode mode , rtx * operands ) { enum rtx_code rc = GET_CODE ( operands [ 1 ] ) ; machine_mode cmp_mode ; rtx cc_reg , dst , cmp ; cmp = operands [ 1 ] ; if ( GET_MODE ( XEXP ( cmp , 0 ) ) == DImode && ! TARGET_ARCH64 ) return false ; if ( GET_MODE ( XEXP ( cmp , 0 ) ) == TFmode && ! TARGET_HARD_QUAD ) cmp = sparc_emit_float_lib_cmp ( XEXP ( cmp , 0 ) , XEXP ( cmp , 1 ) , rc ) ; cmp_mode = GET_MODE ( XEXP ( cmp , 0 ) ) ; rc = GET_CODE ( cmp ) ; dst = operands [ 0 ] ; if ( ! rtx_equal_p ( operands [ 2 ] , dst ) && ! rtx_equal_p ( operands [ 3 ] , dst ) ) { if ( reg_overlap_mentioned_p ( dst , cmp ) ) dst = gen_reg_rtx ( mode ) ; emit_move_insn ( dst , operands [ 3 ] ) ; } else if ( operands [ 2 ] == dst ) { operands [ 2 ] = operands [ 3 ] ; if ( GET_MODE_CLASS ( cmp_mode ) == MODE_FLOAT ) rc = reverse_condition_maybe_unordered ( rc ) ; else rc = reverse_condition ( rc ) ; } if ( XEXP ( cmp , 1 ) == const0_rtx && GET_CODE ( XEXP ( cmp , 0 ) ) == REG && cmp_mode == DImode && v9_regcmp_p ( rc ) ) cc_reg = XEXP ( cmp , 0 ) ; else cc_reg = gen_compare_reg_1 ( rc , XEXP ( cmp , 0 ) , XEXP ( cmp , 1 ) ) ; cmp = gen_rtx_fmt_ee ( rc , GET_MODE ( cc_reg ) , cc_reg , const0_rtx ) ; emit_insn ( gen_rtx_SET ( dst , gen_rtx_IF_THEN_ELSE ( mode , cmp , operands [ 2 ] , dst ) ) ) ; if ( dst != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , dst ) ; return true ; } </s>

Emit code to conditionally move either OPERANDS [ 2 ] or OPERANDS [ 3 ] into OPERANDS [ 0 ] in MODE . OPERANDS [ 1 ] is the operator of the condition .


<s> static void aarch64_emit_bic ( machine_mode mode , rtx dst , rtx s1 , rtx s2 , int shift ) { rtx shift_rtx = GEN_INT ( shift ) ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; switch ( mode ) { case E_SImode : gen = gen_and_one_cmpl_lshrsi3 ; break ; case E_DImode : gen = gen_and_one_cmpl_lshrdi3 ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( dst , s2 , shift_rtx , s1 ) ) ; } </s>


<s> enum aarch_parse_opt_result aarch_parse_branch_protection ( const char * const_str , char * * last_str ) { char * str_root = xstrdup ( const_str ) ; char * token_save = NULL ; char * str = strtok_r ( str_root , "+" , & token_save ) ; enum aarch_parse_opt_result res = AARCH_PARSE_OK ; if ( ! str ) res = AARCH_PARSE_MISSING_ARG ; else { char * next_str = strtok_r ( NULL , "+" , & token_save ) ; aarch_handle_no_branch_protection ( NULL , NULL ) ; while ( str && res == AARCH_PARSE_OK ) { const aarch_branch_protect_type * type = aarch_branch_protect_types ; bool found = false ; while ( type && type -> name && ! found && res == AARCH_PARSE_OK ) { if ( strcmp ( str , type -> name ) == 0 ) { found = true ; res = type -> handler ( str , next_str ) ; str = next_str ; next_str = strtok_r ( NULL , "+" , & token_save ) ; } else type ++ ; } if ( found && res == AARCH_PARSE_OK ) { bool found_subtype = true ; while ( found_subtype ) { found_subtype = false ; const aarch_branch_protect_type * subtype = type -> subtypes ; while ( str && subtype && subtype -> name && ! found_subtype && res == AARCH_PARSE_OK ) { if ( strcmp ( str , subtype -> name ) == 0 ) { found_subtype = true ; res = subtype -> handler ( str , next_str ) ; str = next_str ; next_str = strtok_r ( NULL , "+" , & token_save ) ; } else subtype ++ ; } } } else if ( ! found ) res = AARCH_PARSE_INVALID_ARG ; } } if ( last_str ) { if ( str ) strcpy ( * last_str , str ) ; else * last_str = NULL ; } if ( res == AARCH_PARSE_OK ) { if ( ! accepted_branch_protection_string ) accepted_branch_protection_string = ( char * ) xmalloc ( BRANCH_PROTECT_STR_MAX + 1 ) ; strncpy ( accepted_branch_protection_string , const_str , BRANCH_PROTECT_STR_MAX + 1 ) ; accepted_branch_protection_string [ BRANCH_PROTECT_STR_MAX ] = '\0' ; } return res ; } </s>

Parses CONST_STR for branch protection features specified in aarch64_branch_protect_types , and set any global variables required . Returns the parsing result and assigns LAST_STR to the last processed token from CONST_STR so that it can be used for error reporting .


"64-bit code requested on a subtarget that doesn't support it!"

This constructor initializes the data members to match that of the specified triple .


<s> static struct constant_pool * s390_alloc_pool ( void ) { struct constant_pool * pool ; size_t i ; pool = ( struct constant_pool * ) xmalloc ( sizeof * pool ) ; pool -> next = NULL ; for ( i = 0 ; i < NR_C_MODES ; i ++ ) pool -> constants [ i ] = NULL ; pool -> execute = NULL ; pool -> label = gen_label_rtx ( ) ; pool -> first_insn = NULL ; pool -> pool_insn = NULL ; pool -> insns = BITMAP_ALLOC ( NULL ) ; pool -> size = 0 ; pool -> emit_pool_after = NULL ; return pool ; } </s>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { const R600Subtarget & ST = MF . getSubtarget < R600Subtarget > ( ) ; TII = ST . getInstrInfo ( ) ; for ( MachineFunction :: iterator BB = MF . begin ( ) , BB_E = MF . end ( ) ; BB != BB_E ; ++ BB ) { MachineBasicBlock & MBB = * BB ; MachineBasicBlock :: iterator I = MBB . begin ( ) ; if ( I != MBB . end ( ) && I -> getOpcode ( ) == R600 :: CF_ALU ) continue ; for ( MachineBasicBlock :: iterator E = MBB . end ( ) ; I != E ; ) { if ( isALU ( * I ) ) { auto next = MakeALUClause ( MBB , I ) ; assert ( next != I ) ; I = next ; } else ++ I ; } } return false ; } </s>

runOnMachineFunction - Emit the function body .


<s>
bool
HexagonInstrInfo
::
PredicateInstruction
(
MachineInstr
*
MI
,
ArrayRef
<
MachineOperand
>
Cond
)
const
{
if
(
Cond
.
empty
(
)
||
isEndLoopN
(
Cond
[
0
]
.
getImm
(
)
)
)
{
DEBUG
(
dbgs
(
)
<<
"\nCannot predicate:"
;
MI
->
dump
(
)
;
)
;
return
false
;
}
int
Opc
=
MI
->
getOpcode
(
)
;
assert
(
isPredicable
(
MI
)
&&
"Expected predicable instruction"
)
;
bool
invertJump
=
predOpcodeHasNot
(
Cond
)
;
MachineBasicBlock
&
B
=
*
MI
->
getParent
(
)
;
DebugLoc
DL
=
MI
->
getDebugLoc
(
)
;
unsigned
PredOpc
=
getCondOpcode
(
Opc
,
invertJump
)
;
MachineInstrBuilder
T
=
BuildMI
(
B
,
MI
,
DL
,
get
(
PredOpc
)
)
;
unsigned
NOp
=
0
,
NumOps
=
MI
->
getNumOperands
(
)
;
while
(
NOp
<
NumOps
)
{
MachineOperand
&
Op
=
MI
->
getOperand
(
NOp
)
;
if
(
!
Op
.
isReg
(
)
||
!
Op
.
isDef
(
)
||
Op
.
isImplicit
(
)
)
break
;
T
.
addOperand
(
Op
)
;
NOp
++
;
}
unsigned
PredReg
,
PredRegPos
,
PredRegFlags
;
bool
GotPredReg
=
getPredReg
(
Cond
,
PredReg
,
PredRegPos
,
PredRegFlags
)
;
(
void
)
GotPredReg
;
assert
(
GotPredReg
)
;
T
.
addReg
(
PredReg
,
PredRegFlags
)
;
while
(
NOp
<
NumOps
)
T
.
addOperand
(
MI
->
getOperand
(
NOp
++
)
)
;
MI
->
setDesc
(
get
(
PredOpc
)
)
;
while
(
unsigned
n
=
MI
->
getNumOperands
(
)
)
MI
->
RemoveOperand
(
n
1
)
;
for
(
unsigned
i
=
0
,
n
=
T
->
getNumOperands
(
)
;
i
<
n
;
++
i
)
MI
->
addOperand
(
T
->
getOperand
(
i
)
)
;
MachineBasicBlock
::
instr_iterator
TI
=
&
*
T
;
B
.
erase
(
TI
)
;
MachineRegisterInfo
&
MRI
=
B
.
getParent
(
)
->
getRegInfo
(
)
;
MRI
.
clearKillFlags
(
PredReg
)
;
return
true
;
}
</s>

Convert the instruction into a predicated instruction .


<s> bool AMDGPUPeepholeOpt :: runOnFunction ( Function & MF ) { mChanged = false ; mF = & MF ; mSTM = & TM . getSubtarget < AMDGPUSubtarget > ( ) ; if ( mDebug ) { MF . dump ( ) ; } mCTX = & MF . getType ( ) -> getContext ( ) ; mConvertAtomics = true ; safeNestedForEach ( MF . begin ( ) , MF . end ( ) , MF . begin ( ) -> begin ( ) , std :: bind1st ( std :: mem_fun ( & AMDGPUPeepholeOpt :: instLevelOptimizations ) , this ) ) ; doAtomicConversionIfNeeded ( MF ) ; doIsConstCallConversionIfNeeded ( ) ; if ( mDebug ) { MF . dump ( ) ; } return mChanged ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void GCNPassConfig :: addPreRegAlloc ( ) { addPass ( createSIShrinkInstructionsPass ( ) ) ; addPass ( createSIWholeQuadModePass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s>
const
char
*
mcore_output_movedouble
(
rtx
operands
[
]
,
machine_mode
mode
ATTRIBUTE_UNUSED
)
{
rtx
dst
=
operands
[
0
]
;
rtx
src
=
operands
[
1
]
;
if
(
GET_CODE
(
dst
)
==
REG
)
{
if
(
GET_CODE
(
src
)
==
REG
)
{
int
dstreg
=
REGNO
(
dst
)
;
int
srcreg
=
REGNO
(
src
)
;
if
(
srcreg
+
1
==
dstreg
)
return
"mov	%R0,%R1\n\tmov	%0,%1"
;
else
return
"mov	%0,%1\n\tmov	%R0,%R1"
;
}
else
if
(
GET_CODE
(
src
)
==
MEM
)
{
rtx
memexp
=
XEXP
(
src
,
0
)
;
int
dstreg
=
REGNO
(
dst
)
;
int
basereg
=
1
;
if
(
GET_CODE
(
memexp
)
==
LABEL_REF
)
return
"lrw\t%0,[%1]\n\tlrw\t%R0,[%R1]"
;
else
if
(
GET_CODE
(
memexp
)
==
REG
)
basereg
=
REGNO
(
memexp
)
;
else
if
(
GET_CODE
(
memexp
)
==
PLUS
)
{
if
(
GET_CODE
(
XEXP
(
memexp
,
0
)
)
==
REG
)
basereg
=
REGNO
(
XEXP
(
memexp
,
0
)
)
;
else
if
(
GET_CODE
(
XEXP
(
memexp
,
1
)
)
==
REG
)
basereg
=
REGNO
(
XEXP
(
memexp
,
1
)
)
;
else
gcc_unreachable
(
)
;
}
else
gcc_unreachable
(
)
;
if
(
dstreg
==
basereg
)
{
return
"ldw\t%R0,%R1\n\tldw\t%0,%1"
;
}
else
return
"ldw\t%0,%1\n\tldw\t%R0,%R1"
;
}
else
if
(
GET_CODE
(
src
)
==
CONST_INT
)
{
if
(
TARGET_LITTLE_END
)
{
if
(
CONST_OK_FOR_I
(
INTVAL
(
src
)
)
)
output_asm_insn
(
"movi	%0,%1"
,
operands
)
;
else
if
(
CONST_OK_FOR_M
(
INTVAL
(
src
)
)
)
output_asm_insn
(
"bgeni	%0,%P1"
,
operands
)
;
else
if
(
CONST_OK_FOR_N
(
INTVAL
(
src
)
)
)
output_asm_insn
(
"bmaski	%0,%N1"
,
operands
)
;
else
gcc_unreachable
(
)
;
if
(
INTVAL
(
src
)
<
0
)
return
"bmaski	%R0,32"
;
else
return
"movi	%R0,0"
;
}
else
{
if
(
CONST_OK_FOR_I
(
INTVAL
(
src
)
)
)
output_asm_insn
(
"movi	%R0,%1"
,
operands
)
;
else
if
(
CONST_OK_FOR_M
(
INTVAL
(
src
)
)
)
output_asm_insn
(
"bgeni	%R0,%P1"
,
operands
)
;
else
if
(
CONST_OK_FOR_N
(
INTVAL
(
src
)
)
)
output_asm_insn
(
"bmaski	%R0,%N1"
,
operands
)
;
else
gcc_unreachable
(
)
;
if
(
INTVAL
(
src
)
<
0
)
return
"bmaski	%0,32"
;
else
return
"movi	%0,0"
;
}
}
else
gcc_unreachable
(
)
;
}
else
if
(
GET_CODE
(
dst
)
==
MEM
&&
GET_CODE
(
src
)
==
REG
)
return
"stw\t%1,%0\n\tstw\t%R1,%R0"
;
else
gcc_unreachable
(
)
;
}
</s>

Return a sequence of instructions to perform DI or DF move . Since the MCORE can not move a DI or DF in one instruction , we have to take care when we see overlapping source and dest registers .


<s> static void ix86_test_loading_call_insn ( ) { if ( ! TARGET_SSE ) return ; rtl_dump_test t ( SELFTEST_LOCATION , locate_file ( "x86_64/call-insn.rtl" ) ) ; rtx_insn * insn = get_insns ( ) ; ASSERT_EQ ( CALL_INSN , GET_CODE ( insn ) ) ; ASSERT_TRUE ( RTX_FLAG ( insn , jump ) ) ; rtx pat = PATTERN ( insn ) ; ASSERT_EQ ( CALL , GET_CODE ( SET_SRC ( pat ) ) ) ; { ASSERT_EQ ( EXPR_LIST , GET_CODE ( REG_NOTES ( insn ) ) ) ; rtx_expr_list * note0 = as_a < rtx_expr_list * > ( REG_NOTES ( insn ) ) ; ASSERT_EQ ( REG_CALL_DECL , REG_NOTE_KIND ( note0 ) ) ; rtx_expr_list * note1 = note0 -> next ( ) ; ASSERT_EQ ( REG_EH_REGION , REG_NOTE_KIND ( note1 ) ) ; ASSERT_EQ ( NULL , note1 -> next ( ) ) ; } { rtx_expr_list * usage = as_a < rtx_expr_list * > ( CALL_INSN_FUNCTION_USAGE ( insn ) ) ; ASSERT_EQ ( EXPR_LIST , GET_CODE ( usage ) ) ; ASSERT_EQ ( DFmode , GET_MODE ( usage ) ) ; ASSERT_EQ ( USE , GET_CODE ( usage -> element ( ) ) ) ; ASSERT_EQ ( NULL , usage -> next ( ) ) ; } } </s>

Verify that the RTL loader copes with a call_insn dump . This test is target-specific since the dump contains a target-specific hard reg name .


<s> bool AArch64PassConfig :: addInstSelector ( ) { addPass ( createAArch64ISelDAG ( getAArch64TargetMachine ( ) , getOptLevel ( ) ) ) ; if ( getAArch64Subtarget ( ) . isTargetELF ( ) && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createAArch64CleanupLocalDynamicTLSPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> RegisterAggr & RegisterAggr :: insert ( const RegisterAggr & RG ) { Units |= RG . Units ; return * this ; } </s>

insert - Append entry to the vector if it does n't already exist .


<s>
AVR
::
Fixups
AVRMCExpr
::
getFixupKind
(
)
const
{
AVR
::
Fixups
Kind
=
AVR
::
Fixups
::
LastTargetFixupKind
;
switch
(
getKind
(
)
)
{
case
VK_AVR_LO8
:
Kind
=
isNegated
(
)
AVR
::
fixup_lo8_ldi_neg
:
AVR
::
fixup_lo8_ldi
;
break
;
case
VK_AVR_HI8
:
Kind
=
isNegated
(
)
AVR
::
fixup_hi8_ldi_neg
:
AVR
::
fixup_hi8_ldi
;
break
;
case
VK_AVR_HH8
:
Kind
=
isNegated
(
)
AVR
::
fixup_hh8_ldi_neg
:
AVR
::
fixup_hh8_ldi
;
break
;
case
VK_AVR_HHI8
:
Kind
=
isNegated
(
)
AVR
::
fixup_ms8_ldi_neg
:
AVR
::
fixup_ms8_ldi
;
break
;
case
VK_AVR_PM_LO8
:
Kind
=
isNegated
(
)
AVR
::
fixup_lo8_ldi_pm_neg
:
AVR
::
fixup_lo8_ldi_pm
;
break
;
case
VK_AVR_PM_HI8
:
Kind
=
isNegated
(
)
AVR
::
fixup_hi8_ldi_pm_neg
:
AVR
::
fixup_hi8_ldi_pm
;
break
;
case
VK_AVR_PM_HH8
:
Kind
=
isNegated
(
)
AVR
::
fixup_hh8_ldi_pm_neg
:
AVR
::
fixup_hh8_ldi_pm
;
break
;
case
VK_AVR_None
:
llvm_unreachable
(
"Uninitialized expression"
)
;
}
return
Kind
;
}
</s>

getFixupKind - Get the fixup kind of this expression .


<s> void SIInstrInfo :: legalizeOpWithMove ( MachineInstr & MI , unsigned OpIdx ) const { MachineBasicBlock :: iterator I = MI ; MachineBasicBlock * MBB = MI . getParent ( ) ; MachineOperand & MO = MI . getOperand ( OpIdx ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; const SIRegisterInfo * TRI = static_cast < const SIRegisterInfo * > ( MRI . getTargetRegisterInfo ( ) ) ; unsigned RCID = get ( MI . getOpcode ( ) ) . OpInfo [ OpIdx ] . RegClass ; const TargetRegisterClass * RC = RI . getRegClass ( RCID ) ; unsigned Size = TRI -> getRegSizeInBits ( * RC ) ; unsigned Opcode = ( Size == 64 ) ? AMDGPU :: V_MOV_B64_PSEUDO : AMDGPU :: V_MOV_B32_e32 ; if ( MO . isReg ( ) ) Opcode = AMDGPU :: COPY ; else if ( RI . isSGPRClass ( RC ) ) Opcode = ( Size == 64 ) ? AMDGPU :: S_MOV_B64 : AMDGPU :: S_MOV_B32 ; const TargetRegisterClass * VRC = RI . getEquivalentVGPRClass ( RC ) ; if ( RI . getCommonSubClass ( & AMDGPU :: VReg_64RegClass , VRC ) ) VRC = & AMDGPU :: VReg_64RegClass ; else VRC = & AMDGPU :: VGPR_32RegClass ; Register Reg = MRI . createVirtualRegister ( VRC ) ; DebugLoc DL = MBB -> findDebugLoc ( I ) ; BuildMI ( * MI . getParent ( ) , I , DL , get ( Opcode ) , Reg ) . add ( MO ) ; MO . ChangeToRegister ( Reg , false ) ; } </s>

Legalize the OpIndex operand of this instruction by inserting a MOV .


<s>
void
FISCAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
isPCRel
)
const
{
unsigned
NumBytes
=
4
;
Value
=
adjustFixupValue
(
Fixup
,
Value
)
;
if
(
!
Value
)
return
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
(
NumBytes
i
1
)
*
8
)
)
&
0xff
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static rtx cr16_struct_value_rtx ( tree fntype ATTRIBUTE_UNUSED , int incoming ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( Pmode , cr16_ret_register ( ) ) ; } </s>

Implements hook TARGET_STRUCT_VALUE_RTX .


<s>
bool
R600ClauseMergePass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
TII
=
static_cast
<
const
R600InstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
for
(
MachineFunction
::
iterator
BB
=
MF
.
begin
(
)
,
BB_E
=
MF
.
end
(
)
;
BB
!=
BB_E
;
++
BB
)
{
MachineBasicBlock
&
MBB
=
*
BB
;
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
,
E
=
MBB
.
end
(
)
;
MachineBasicBlock
::
iterator
LatestCFAlu
=
E
;
while
(
I
!=
E
)
{
MachineInstr
*
MI
=
I
++
;
if
(
(
!
TII
->
canBeConsideredALU
(
MI
)
&&
!
isCFAlu
(
MI
)
)
||
TII
->
mustBeLastInClause
(
MI
->
getOpcode
(
)
)
)
LatestCFAlu
=
E
;
if
(
!
isCFAlu
(
MI
)
)
continue
;
cleanPotentialDisabledCFAlu
(
MI
)
;
if
(
LatestCFAlu
!=
E
&&
mergeIfPossible
(
LatestCFAlu
,
MI
)
)
{
MI
->
eraseFromParent
(
)
;
}
else
{
assert
(
MI
->
getOperand
(
8
)
.
getImm
(
)
&&
"CF ALU instruction disabled"
)
;
LatestCFAlu
=
MI
;
}
}
}
return
false
;
}
</s>


<s>
const
char
*
getPassName
(
)
const
override
{
return
"SI Lower control flow instructions"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> int tilegx_initial_elimination_offset ( int from , int to ) { int total_size = compute_total_frame_size ( ) ; if ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) { return ( total_size - crtl -> args . pretend_args_size - tilegx_saved_regs_size ( ) ) ; } else if ( from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) { return - ( crtl -> args . pretend_args_size + tilegx_saved_regs_size ( ) ) ; } else if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) { return STACK_POINTER_OFFSET + total_size ; } else if ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) { return STACK_POINTER_OFFSET ; } else gcc_unreachable ( ) ; } </s>


<s> bool WebAssemblyTargetLowering :: shouldSimplifyDemandedVectorElts ( SDValue Op , const TargetLoweringOpt & TLO ) const { if ( Op . getOpcode ( ) == ISD :: BUILD_VECTOR && TLO . LegalOps && TLO . LegalTys ) return false ; return true ; } </s>

Return true if the target supports simplifying demanded vector elements by converting them to undefs .


<s> void UPTAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BR_JT : return lowerBR_JT ( Op , DAG ) ; case ISD :: BRCOND : return lowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return lowerConstantPool ( Op , DAG ) ; case ISD :: GlobalAddress : return lowerGlobalAddress ( Op , DAG ) ; case ISD :: BlockAddress : return lowerBlockAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return lowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return lowerJumpTable ( Op , DAG ) ; case ISD :: SELECT : return lowerSELECT ( Op , DAG ) ; case ISD :: SELECT_CC : return lowerSELECT_CC ( Op , DAG ) ; case ISD :: SETCC : return lowerSETCC ( Op , DAG ) ; case ISD :: VASTART : return lowerVASTART ( Op , DAG ) ; case ISD :: FCOPYSIGN : return lowerFCOPYSIGN ( Op , DAG ) ; case ISD :: FRAMEADDR : return lowerFRAMEADDR ( Op , DAG ) ; case ISD :: RETURNADDR : return lowerRETURNADDR ( Op , DAG ) ; case ISD :: EH_RETURN : return lowerEH_RETURN ( Op , DAG ) ; case ISD :: ATOMIC_FENCE : return lowerATOMIC_FENCE ( Op , DAG ) ; case ISD :: SHL_PARTS : return lowerShiftLeftParts ( Op , DAG ) ; case ISD :: SRA_PARTS : return lowerShiftRightParts ( Op , DAG , true ) ; case ISD :: SRL_PARTS : return lowerShiftRightParts ( Op , DAG , false ) ; case ISD :: LOAD : return lowerLOAD ( Op , DAG ) ; case ISD :: STORE : return lowerSTORE ( Op , DAG ) ; case ISD :: ADD : return lowerADD ( Op , DAG ) ; case ISD :: FP_TO_SINT : return lowerFP_TO_SINT ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::BR_JT ISD::BRCOND ISD::ConstantPool ISD::GlobalAddress ISD::BlockAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::SELECT ISD::SELECT_CC ISD::SETCC ISD::VASTART ISD::FCOPYSIGN ISD::FRAMEADDR ISD::RETURNADDR ISD::EH_RETURN ISD::ATOMIC_FENCE ISD::SHL_PARTS ISD::SRA_PARTS ISD::SRL_PARTS ISD::LOAD ISD::STORE ISD::ADD ISD::FP_TO_SINT


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; } </s>


<s> rtx mmix_dynamic_chain_address ( rtx frame ) { return plus_constant ( frame , - 8 ) ; } </s>


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64Bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , Options . StackAlignmentOverride , is64Bit ) , FrameLowering ( * this , Subtarget ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) { if ( getRelocationModel ( ) == Reloc :: Static ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . is64Bit ( ) ) { Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; } else if ( Subtarget . isTargetCygMing ( ) ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . isTargetDarwin ( ) ) { if ( getRelocationModel ( ) == Reloc :: PIC_ ) Subtarget . setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; Subtarget . setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( Subtarget . isTargetELF ( ) ) { Subtarget . setPICStyle ( PICStyles :: GOT ) ; } if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = FloatABI :: Hard ; } </s>


<s> static void rs6000_set_handled_components ( sbitmap components ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; for ( int i = info -> first_gp_reg_save ; i < 32 ; i ++ ) if ( bitmap_bit_p ( components , i ) ) cfun -> machine -> gpr_is_wrapped_separately [ i ] = true ; if ( bitmap_bit_p ( components , 0 ) ) cfun -> machine -> lr_is_wrapped_separately = true ; } </s>


"target CPU does not support THUMB instructions"

"target CPU does not support unaligned accesses"

Reset options between modes that the user has specified .


<s> static void ft32_setup_incoming_varargs ( cumulative_args_t cum_v , machine_mode mode , tree type ATTRIBUTE_UNUSED , int * pretend_size , int no_rtl ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int named_size = GET_MODE_SIZE ( SImode ) * ( * cum - FT32_R0 ) + GET_MODE_SIZE ( mode ) ; if ( named_size < 24 ) * pretend_size = 24 - named_size ; else * pretend_size = 0 ; } </s>

Worker function for TARGET_SETUP_INCOMING_VARARGS .


<s> bool X86TargetLowering :: isLegalStoreImmediate ( int64_t Imm ) const { return isInt < 32 > ( Imm ) ; } </s>

Return true if the specified immediate is legal for the value input of a store instruction .


<s> bool X86AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : break ; case 'H' : printMemReference ( MI , OpNo , O , "H" ) ; return false ; case 'P' : printMemReference ( MI , OpNo , O , "no-rip" ) ; return false ; } } printMemReference ( MI , OpNo , O ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> bool AMDGPUCodeGenPrepare :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; const AMDGPUTargetMachine & TM = TPC -> getTM < AMDGPUTargetMachine > ( ) ; ST = & TM . getSubtarget < GCNSubtarget > ( F ) ; AC = & getAnalysis < AssumptionCacheTracker > ( ) . getAssumptionCache ( F ) ; DA = & getAnalysis < LegacyDivergenceAnalysis > ( ) ; auto * DTWP = getAnalysisIfAvailable < DominatorTreeWrapperPass > ( ) ; DT = DTWP ? & DTWP -> getDomTree ( ) : nullptr ; HasUnsafeFPMath = hasUnsafeFPMath ( F ) ; HasFP32Denormals = ST -> hasFP32Denormals ( F ) ; bool MadeChange = false ; Function :: iterator NextBB ; for ( Function :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; FI = NextBB ) { BasicBlock * BB = & * FI ; NextBB = std :: next ( FI ) ; BasicBlock :: iterator Next ; for ( BasicBlock :: iterator I = BB -> begin ( ) , E = BB -> end ( ) ; I != E ; I = Next ) { Next = std :: next ( I ) ; MadeChange |= visit ( * I ) ; if ( Next != E ) { BasicBlock * NextInstBB = Next -> getParent ( ) ; if ( NextInstBB != BB ) { BB = NextInstBB ; E = BB -> end ( ) ; FE = F . end ( ) ; } } } } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool rs6000_is_valid_and_mask ( rtx mask , machine_mode mode ) { int nb , ne ; if ( ! rs6000_is_valid_mask ( mask , & nb , & ne , mode ) ) return false ; if ( mode == DImode ) return ( ne == 0 || nb == 63 || ( nb < 32 && ne <= nb ) ) ; if ( mode == SImode ) return ( nb < 32 && ne < 32 ) ; return false ; } </s>

Return whether MASK ( a CONST_INT ) is a valid mask for any rlwinm , rldicl , or rldicr instruction , to implement an AND with it in mode MODE .


<s>
char
*
aarch64_output_ptrue
(
machine_mode
mode
,
char
suffix
)
{
unsigned
int
nunits
;
static
char
buf
[
sizeof
(
"ptrue\t%0.N, vlNNNNN"
)
]
;
if
(
GET_MODE_NUNITS
(
mode
)
.
is_constant
(
&
nunits
)
)
snprintf
(
buf
,
sizeof
(
buf
)
,
"ptrue\t%%0.%c, vl%d"
,
suffix
,
nunits
)
;
else
snprintf
(
buf
,
sizeof
(
buf
)
,
"ptrue\t%%0.%c, all"
,
suffix
)
;
return
buf
;
}
</s>

Return the asm format for a PTRUE instruction whose destination has mode MODE . SUFFIX is the element size suffix .

aarch64
"ptrue\t%0.N, vlNNNNN"
"ptrue\t%%0.%c, vl%d"
"ptrue\t%%0.%c, all"


"Following single-path roots were not found:\n"

"Single-path code generation failed due to "

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s>
const
ARMGOT
&
ARMGNULDBackend
::
getGOT
(
)
const
{
assert
(
m_pGOT
!=
&&
"GOT section not exist"
)
;
return
*
m_pGOT
;
}
</s>

Return a pseudo source value referencing the global offset table ( or something the like ) .


<s> SIScheduleBlocks SIScheduleBlockCreator :: getBlocks ( SISchedulerBlockCreatorVariant BlockVariant ) { std :: map < SISchedulerBlockCreatorVariant , SIScheduleBlocks > :: iterator B = Blocks . find ( BlockVariant ) ; if ( B == Blocks . end ( ) ) { SIScheduleBlocks Res ; createBlocksForVariant ( BlockVariant ) ; topologicalSort ( ) ; scheduleInsideBlocks ( ) ; fillStats ( ) ; Res . Blocks = CurrentBlocks ; Res . TopDownIndex2Block = TopDownIndex2Block ; Res . TopDownBlock2Index = TopDownBlock2Index ; Blocks [ BlockVariant ] = Res ; return Res ; } else { return B -> second ; } } </s>

Get a list of the basic blocks which make up this loop .


"Unmatched number of shufflevectors and indices"

Lower interleaved load ( s ) into target specific instructions/intrinsics .


<s>
CCAssignFn
*
AMDGPUCallLowering
::
CCAssignFnForReturn
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
{
switch
(
CC
)
{
case
CallingConv
::
AMDGPU_KERNEL
:
case
CallingConv
::
SPIR_KERNEL
:
llvm_unreachable
(
"kernels should not be handled here"
)
;
case
CallingConv
::
AMDGPU_VS
:
case
CallingConv
::
AMDGPU_GS
:
case
CallingConv
::
AMDGPU_PS
:
case
CallingConv
::
AMDGPU_CS
:
case
CallingConv
::
AMDGPU_HS
:
case
CallingConv
::
AMDGPU_ES
:
case
CallingConv
::
AMDGPU_LS
:
return
RetCC_SI_Shader
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
case
CallingConv
::
Cold
:
return
RetCC_AMDGPU_Func
;
default
:
report_fatal_error
(
"Unsupported calling convention."
)
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .

AMDGPU
AMDGPU
AMDGPU
"kernels should not be handled here"
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
SI
AMDGPU
"Unsupported calling convention."


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & TM . getSubtarget < ARMSubtarget > ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s>
StringRef
getPassName
(
)
const
override
{
return
"AMDGPU Pre-RA optimizations"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
bool
PatmosSinglePathInfo
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
Root
)
{
delete
Root
;
Root
=
;
}
auto
curfunc
=
MF
.
getFunction
(
)
.
getName
(
)
;
if
(
isConverting
(
MF
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"[Single-Path] Analyze '"
<<
curfunc
<<
"'\n"
)
;
analyzeFunction
(
MF
)
;
}
return
false
;
}
</s>

Patmos
Patmos
"[Single-Path] Analyze '"
"'\n"


<s> bool can_be_rotated_to_lowbits ( unsigned HOST_WIDE_INT c , int lowbits , int * rot ) { int clz = HOST_BITS_PER_WIDE_INT - lowbits ; int lz = clz_hwi ( c ) ; if ( lz >= clz ) { * rot = 0 ; return true ; } int tz = ctz_hwi ( c ) ; if ( lz + tz >= clz ) { * rot = HOST_BITS_PER_WIDE_INT - tz ; return true ; } const int rot_bits = lowbits + 1 ; unsigned HOST_WIDE_INT rc = ( c >> rot_bits ) | ( c << ( clz - 1 ) ) ; tz = ctz_hwi ( rc ) ; if ( clz_hwi ( rc ) + tz >= clz ) { * rot = HOST_BITS_PER_WIDE_INT - ( tz + rot_bits ) ; return true ; } return false ; } </s>

Check if C ( as 64bit integer ) can be rotated to a constant which constains nonzero bits at the LOWBITS low bits only . Return true if C can be rotated to such constant . If so , * ROT is written to the number by which C is rotated . Return false otherwise .


<s> void ARMPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableARMLoadStoreOpt ) addPass ( createARMLoadStoreOptimizationPass ( ) ) ; addPass ( new ARMExecutionDomainFix ( ) ) ; addPass ( createBreakFalseDeps ( ) ) ; } addPass ( createARMExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createThumb2SizeReductionPass ( [ this ] ( const Function & F ) { return this -> TM -> getSubtarget < ARMSubtarget > ( F ) . restrictIT ( ) ; } ) ) ; addPass ( createIfConverter ( [ ] ( const MachineFunction & MF ) { return ! MF . getSubtarget < ARMSubtarget > ( ) . isThumb1Only ( ) ; } ) ) ; } addPass ( createThumb2ITBlockPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> const char * KudeyarAsmPrinter :: getCurrentABIString ( ) const { { } return "abi32" ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 FP Stackifier"
;
}
</s>


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> void emitFunctionType ( const MCSymbolWasm * ) override { } </s>


<s> static bool s390_fix_long_loop_prediction ( rtx_insn * insn ) { rtx set = single_set ( insn ) ; rtx code_label , label_ref , new_label ; rtx_insn * uncond_jump ; rtx_insn * cur_insn ; rtx tmp ; int distance ; if ( ! set || SET_DEST ( set ) != pc_rtx || GET_CODE ( SET_SRC ( set ) ) != IF_THEN_ELSE ) return false ; if ( ANY_RETURN_P ( XEXP ( SET_SRC ( set ) , 1 ) ) && XEXP ( SET_SRC ( set ) , 2 ) == pc_rtx ) return false ; label_ref = ( GET_CODE ( XEXP ( SET_SRC ( set ) , 1 ) ) == LABEL_REF ? XEXP ( SET_SRC ( set ) , 1 ) : XEXP ( SET_SRC ( set ) , 2 ) ) ; gcc_assert ( GET_CODE ( label_ref ) == LABEL_REF ) ; code_label = XEXP ( label_ref , 0 ) ; if ( INSN_ADDRESSES ( INSN_UID ( code_label ) ) == - 1 || INSN_ADDRESSES ( INSN_UID ( insn ) ) == - 1 || ( INSN_ADDRESSES ( INSN_UID ( insn ) ) - INSN_ADDRESSES ( INSN_UID ( code_label ) ) < PREDICT_DISTANCE ) ) return false ; for ( distance = 0 , cur_insn = PREV_INSN ( insn ) ; distance < PREDICT_DISTANCE - 6 ; distance += get_attr_length ( cur_insn ) , cur_insn = PREV_INSN ( cur_insn ) ) if ( ! cur_insn || JUMP_P ( cur_insn ) || LABEL_P ( cur_insn ) ) return false ; new_label = gen_label_rtx ( ) ; uncond_jump = emit_jump_insn_after ( gen_rtx_SET ( pc_rtx , gen_rtx_LABEL_REF ( VOIDmode , code_label ) ) , insn ) ; emit_label_after ( new_label , uncond_jump ) ; tmp = XEXP ( SET_SRC ( set ) , 1 ) ; XEXP ( SET_SRC ( set ) , 1 ) = XEXP ( SET_SRC ( set ) , 2 ) ; XEXP ( SET_SRC ( set ) , 2 ) = tmp ; INSN_CODE ( insn ) = - 1 ; XEXP ( label_ref , 0 ) = new_label ; JUMP_LABEL ( insn ) = new_label ; JUMP_LABEL ( uncond_jump ) = code_label ; return true ; } </s>

On z10 and later the dynamic branch prediction must see the backward jump within a certain windows . If not it falls back to the static prediction . This function rearranges the loop backward branch in a way which makes the static prediction always correct . The function returns true if it added an instruction .


<s> static int m32r_is_insn ( rtx insn ) { return ( NONDEBUG_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER ) ; } </s>

Return true if INSN is real instruction bearing insn .


<s>
unsigned
XCoreInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
getLastNonDebugInstr
(
)
;
if
(
I
==
MBB
.
end
(
)
)
return
0
;
if
(
!
IsBRU
(
I
->
getOpcode
(
)
)
&&
!
IsCondBranch
(
I
->
getOpcode
(
)
)
)
return
0
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
if
(
I
==
MBB
.
begin
(
)
)
return
1
;
I
;
if
(
!
IsCondBranch
(
I
->
getOpcode
(
)
)
)
return
1
;
I
->
eraseFromParent
(
)
;
return
2
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"NVPTX Replace Image Handles"
;
}
</s>


"Trying to obtain non-reserved register \""

Return the register ID of the name passed in .


<s> const TargetRegisterClass * ARMTargetLowering :: getRegClassFor ( MVT VT ) const { if ( Subtarget -> hasNEON ( ) ) { if ( VT == MVT :: v4i64 ) return & ARM :: QQPRRegClass ; if ( VT == MVT :: v8i64 ) return & ARM :: QQQQPRRegClass ; } return TargetLowering :: getRegClassFor ( VT ) ; } </s>

Return the register class that should be used for the specified value type .

ARM ARM MVT::v4i64 ARM::QQPRRegClass MVT::v8i64 ARM::QQQQPRRegClass


"TODO implement argument passing on stack"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> bool PPCCTRLoops :: runOnFunction ( Function & F ) { LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolution > ( ) ; DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; DataLayoutPass * DLP = getAnalysisIfAvailable < DataLayoutPass > ( ) ; DL = DLP ? & DLP -> getDataLayout ( ) : nullptr ; auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ; LibInfo = TLIP ? & TLIP -> getTLI ( ) : nullptr ; bool MadeChange = false ; for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) { Loop * L = * I ; if ( ! L -> getParentLoop ( ) ) MadeChange |= convertToCTRLoop ( L ) ; } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void ARMPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createARMLoadStoreOptimizationPass ( ) ) ; if ( getARMSubtarget ( ) . hasNEON ( ) ) addPass ( createExecutionDependencyFixPass ( & ARM :: DPRRegClass ) ) ; } addPass ( createARMExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( ! getARMSubtarget ( ) . isThumb1Only ( ) ) { if ( getARMSubtarget ( ) . restrictIT ( ) && ! getARMSubtarget ( ) . prefers32BitThumb ( ) ) addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( & IfConverterID ) ; } } if ( getARMSubtarget ( ) . isThumb2 ( ) ) addPass ( createThumb2ITBlockPass ( ) ) ; } </s>

ARM ARM ARM ARM ARM::DPRRegClass ARM ARM ARM ARM ARM


<s> static void mark_reg_gr_used_mask ( rtx reg , void * data ATTRIBUTE_UNUSED ) { unsigned int regno = REGNO ( reg ) ; if ( regno < 32 ) { unsigned int i , n = hard_regno_nregs [ regno ] [ GET_MODE ( reg ) ] ; for ( i = 0 ; i < n ; ++ i ) current_frame_info . gr_used_mask |= 1 << ( regno + i ) ; } } </s>

Helper function for ia64_compute_frame_size , called through diddle_return_value . Mark REG in current_frame_info.gr_used_mask .


"__builtin_arc_aligned with non-constant alignment"

"invalid alignment value for __builtin_arc_aligned"

Helper to expand __builtin_arc_aligned ( void * val , int alignval ) .


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { MachineFunction & MF = MIRBuilder . getMF ( ) ; LLT p0 = LLT :: pointer ( 0 , 64 ) ; LLT s64 = LLT :: scalar ( 64 ) ; if ( IsTailCall ) { Offset += FPDiff ; int FI = MF . getFrameInfo ( ) . CreateFixedObject ( Size , Offset , true ) ; auto FIReg = MIRBuilder . buildFrameIndex ( p0 , FI ) ; MPO = MachinePointerInfo :: getFixedStack ( MF , FI ) ; return FIReg . getReg ( 0 ) ; } if ( ! SPReg ) SPReg = MIRBuilder . buildCopy ( p0 , Register ( AArch64 :: SP ) ) . getReg ( 0 ) ; auto OffsetReg = MIRBuilder . buildConstant ( s64 , Offset ) ; auto AddrReg = MIRBuilder . buildPtrAdd ( p0 , SPReg , OffsetReg ) ; MPO = MachinePointerInfo :: getStack ( MF , Offset ) ; return AddrReg . getReg ( 0 ) ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> BitVector SIRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AMDGPU :: INDIRECT_BASE_ADDR ) ; reserveRegisterTuples ( Reserved , AMDGPU :: EXEC ) ; reserveRegisterTuples ( Reserved , AMDGPU :: FLAT_SCR ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TBA ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TMA ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP0_TTMP1 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP2_TTMP3 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP4_TTMP5 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP6_TTMP7 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP8_TTMP9 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP10_TTMP11 ) ; const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; unsigned MaxNumSGPRs = ST . getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = AMDGPU :: SGPR_32RegClass . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = AMDGPU :: SGPR_32RegClass . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } unsigned MaxNumVGPRs = ST . getMaxNumVGPRs ( MF ) ; unsigned TotalNumVGPRs = AMDGPU :: VGPR_32RegClass . getNumRegs ( ) ; for ( unsigned i = MaxNumVGPRs ; i < TotalNumVGPRs ; ++ i ) { unsigned Reg = AMDGPU :: VGPR_32RegClass . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } const SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , ScratchWaveOffsetReg ) ; } unsigned ScratchRSrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRSrcReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , ScratchRSrcReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , ScratchWaveOffsetReg ) ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool VETargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { return VT == MVT :: f32 || VT == MVT :: f64 ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> int64_t getStackPointerBias ( ) const { return is64Bit ( ) ? 2047 : 0 ; } </s>

The 64-bit ABI uses biased stack and frame pointers , so the stack frame of the current function is the area from [ sp+BIAS ] to [ fp+BIAS ] .


<s> bool PPCFunctionInfo :: isLiveInSExt ( Register VReg ) const { for ( const std :: pair < Register , ISD :: ArgFlagsTy > & LiveIn : LiveInAttrs ) if ( LiveIn . first == VReg ) return LiveIn . second . isSExt ( ) ; return false ; } </s>

This function returns true if the specified vreg is a live-in register and sign-extended .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < TargetTransformInfoWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void HexagonFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned TargetAlign = MF . getTarget ( ) . getSubtargetImpl ( ) -> getFrameLowering ( ) -> getStackAlignment ( ) ; unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = RoundUpToAlignment ( maxCallFrameSize , TargetAlign ) ; MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = RoundUpToAlignment ( FrameSize , TargetAlign ) ; MFI -> setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s>
bool
DeadCodeElimination
::
collect
(
)
{
LiveNodes
.
clear
(
)
;
SetVector
<
NodeId
>
WorkQ
;
for
(
NodeAddr
<
BlockNode
*
>
BA
:
DFG
.
getFunc
(
)
.
Addr
->
members
(
DFG
)
)
for
(
NodeAddr
<
InstrNode
*
>
IA
:
BA
.
Addr
->
members
(
DFG
)
)
scanInstr
(
IA
,
WorkQ
)
;
while
(
!
WorkQ
.
empty
(
)
)
{
NodeId
N
=
*
WorkQ
.
begin
(
)
;
WorkQ
.
remove
(
N
)
;
LiveNodes
.
insert
(
N
)
;
auto
RA
=
DFG
.
addr
<
RefNode
*
>
(
N
)
;
if
(
DFG
.
IsDef
(
RA
)
)
processDef
(
RA
,
WorkQ
)
;
else
processUse
(
RA
,
WorkQ
)
;
}
if
(
trace
(
)
)
{
dbgs
(
)
<<
"Live nodes:\n"
;
for
(
NodeId
N
:
LiveNodes
)
{
auto
RA
=
DFG
.
addr
<
RefNode
*
>
(
N
)
;
dbgs
(
)
<<
PrintNode
<
RefNode
*
>
(
RA
,
DFG
)
<<
"\n"
;
}
}
auto
IsDead
=
[
this
]
(
NodeAddr
<
InstrNode
*
>
IA
)
->
bool
{
for
(
NodeAddr
<
DefNode
*
>
DA
:
IA
.
Addr
->
members_if
(
DFG
.
IsDef
,
DFG
)
)
if
(
LiveNodes
.
count
(
DA
.
Id
)
)
return
false
;
return
true
;
}
;
for
(
NodeAddr
<
BlockNode
*
>
BA
:
DFG
.
getFunc
(
)
.
Addr
->
members
(
DFG
)
)
{
for
(
NodeAddr
<
InstrNode
*
>
IA
:
BA
.
Addr
->
members
(
DFG
)
)
{
for
(
NodeAddr
<
RefNode
*
>
RA
:
IA
.
Addr
->
members
(
DFG
)
)
if
(
!
LiveNodes
.
count
(
RA
.
Id
)
)
DeadNodes
.
insert
(
RA
.
Id
)
;
if
(
DFG
.
IsCode
<
NodeAttrs
::
Stmt
>
(
IA
)
)
if
(
isLiveInstr
(
NodeAddr
<
StmtNode
*
>
(
IA
)
.
Addr
->
getCode
(
)
)
)
continue
;
if
(
IsDead
(
IA
)
)
{
DeadInstrs
.
insert
(
IA
.
Id
)
;
if
(
trace
(
)
)
dbgs
(
)
<<
"Dead instr: "
<<
PrintNode
<
InstrNode
*
>
(
IA
,
DFG
)
<<
"\n"
;
}
}
}
return
!
DeadNodes
.
empty
(
)
;
}
</s>

Analyze the given instruction MI and fill in the Uses , Defs and DeadDefs list based on the MachineOperand flags .

Hexagon
"Live nodes:\n"
"\n"
"Dead instr: "
"\n"


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Mips Hazard Schedule"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"SGPR spill should have been removed in SILowerSGPRSpills"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


"Instr doesn't have FrameIndex operand!"

"Requesting 64-bit offset in 32-bit immediate!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s>
NVPTXSubtarget
&
NVPTXSubtarget
::
initializeSubtargetDependencies
(
StringRef
CPU
,
StringRef
FS
)
{
if
(
CPU
.
empty
(
)
&&
FS
.
size
(
)
)
llvm_unreachable
(
"we are not using FeatureStr"
)
;
TargetName
=
CPU
.
empty
(
)
"sm_20"
:
CPU
;
ParseSubtargetFeatures
(
TargetName
,
FS
)
;
if
(
PTXVersion
==
0
)
{
PTXVersion
=
32
;
}
return
*
this
;
}
</s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool SIInstrInfo :: isOperandLegal ( const MachineInstr * MI , unsigned OpIdx , const MachineOperand * MO ) const { const MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const MCInstrDesc & InstDesc = get ( MI -> getOpcode ( ) ) ; const MCOperandInfo & OpInfo = InstDesc . OpInfo [ OpIdx ] ; const TargetRegisterClass * DefinedRC = OpInfo . RegClass != - 1 ? RI . getRegClass ( OpInfo . RegClass ) : nullptr ; if ( ! MO ) MO = & MI -> getOperand ( OpIdx ) ; if ( isVALU ( * MI ) && usesConstantBus ( MRI , * MO , DefinedRC -> getSize ( ) ) ) { unsigned SGPRUsed = MO -> isReg ( ) ? MO -> getReg ( ) : ( unsigned ) AMDGPU :: NoRegister ; for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i == OpIdx ) continue ; const MachineOperand & Op = MI -> getOperand ( i ) ; if ( Op . isReg ( ) && Op . getReg ( ) != SGPRUsed && usesConstantBus ( MRI , Op , getOpSize ( * MI , i ) ) ) { return false ; } } } if ( MO -> isReg ( ) ) { assert ( DefinedRC ) ; const TargetRegisterClass * RC = TargetRegisterInfo :: isVirtualRegister ( MO -> getReg ( ) ) ? MRI . getRegClass ( MO -> getReg ( ) ) : RI . getPhysRegClass ( MO -> getReg ( ) ) ; return RI . getCommonSubClass ( RC , RI . getRegClass ( OpInfo . RegClass ) ) == RC ; } assert ( MO -> isImm ( ) || MO -> isTargetIndex ( ) || MO -> isFI ( ) ) ; if ( ! DefinedRC ) { return true ; } return isImmOperandLegal ( MI , OpIdx , * MO ) ; } </s>

Check if MO is a legal operand if it was the OpIdx Operand for MI .


<s> bool isMem ( ) const { return false ; } </s>


<s> bool aarch64_sve_prefetch_operand_p ( rtx op , machine_mode mode ) { struct aarch64_address_info addr ; if ( ! aarch64_classify_address ( & addr , op , mode , false , ADDR_QUERY_ANY ) ) return false ; if ( addr . type == ADDRESS_REG_IMM ) return offset_6bit_signed_scaled_p ( mode , addr . const_offset ) ; return addr . type == ADDRESS_REG_REG ; } </s>

Return true if OP is a valid address for an SVE PRF [ BHWD ] instruction , addressing memory of mode MODE .


<s> int branch_dest ( rtx branch ) { rtx pat = PATTERN ( branch ) ; rtx dest = ( GET_CODE ( pat ) == PARALLEL ? SET_SRC ( XVECEXP ( pat , 0 , 0 ) ) : SET_SRC ( pat ) ) ; int dest_uid ; if ( GET_CODE ( dest ) == IF_THEN_ELSE ) dest = XEXP ( dest , XEXP ( dest , 1 ) == pc_rtx ? 2 : 1 ) ; dest = XEXP ( dest , 0 ) ; dest_uid = INSN_UID ( dest ) ; return INSN_ADDRESSES ( dest_uid ) ; } </s>

Return the destination address of BRANCH . We need to use this instead of get_attr_length , because the cbranch_with_nops pattern conservatively sets its length to 6 , and we still prefer to use shorter sequences .


<s> static bool mips_cfun_has_flexible_gp_ref_p ( void ) { if ( TARGET_ABICALLS_PIC2 && ! reload_completed && crtl -> uses_const_pool ) return true ; return mips_find_gp_ref ( & cfun -> machine -> has_flexible_gp_insn_p , mips_insn_has_flexible_gp_ref_p ) ; } </s>

Return true if the current function references the global pointer , but if those references do not inherently require the global pointer to be $ 28 . Assume ! mips_cfun_has_inflexible_gp_ref_p ( ) .


Return true if X is a legitimate address with a 14-bit offset shifted 2 . MODE is the mode of the value being accessed .


<s>
static
void
arm_option_print
(
FILE
*
file
,
int
indent
,
struct
cl_target_option
*
ptr
)
{
int
flags
=
ptr
->
x_target_flags
;
const
char
*
fpu_name
;
fpu_name
=
(
ptr
->
x_arm_fpu_index
==
TARGET_FPU_auto
"auto"
:
all_fpus
[
ptr
->
x_arm_fpu_index
]
.
name
)
;
fprintf
(
file
,
"%*sselected isa %s\n"
,
indent
,
""
,
TARGET_THUMB2_P
(
flags
)
"thumb2"
:
TARGET_THUMB_P
(
flags
)
"thumb1"
:
"arm"
)
;
if
(
ptr
->
x_arm_arch_string
)
fprintf
(
file
,
"%*sselected architecture %s\n"
,
indent
,
""
,
ptr
->
x_arm_arch_string
)
;
if
(
ptr
->
x_arm_cpu_string
)
fprintf
(
file
,
"%*sselected CPU %s\n"
,
indent
,
""
,
ptr
->
x_arm_cpu_string
)
;
if
(
ptr
->
x_arm_tune_string
)
fprintf
(
file
,
"%*sselected tune %s\n"
,
indent
,
""
,
ptr
->
x_arm_tune_string
)
;
fprintf
(
file
,
"%*sselected fpu %s\n"
,
indent
,
""
,
fpu_name
)
;
}
</s>

arm
"auto"
"%*sselected isa %s\n"
""
"thumb2"
"thumb1"
"arm"
"%*sselected architecture %s\n"
""
"%*sselected CPU %s\n"
""
"%*sselected tune %s\n"
""
"%*sselected fpu %s\n"
""


<s>
bool
CAHPInstrInfo
::
reverseBranchCondition
(
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
assert
(
(
Cond
.
size
(
)
==
3
)
&&
"Invalid branch condition!"
)
;
bool
ShouldSwap
=
false
;
switch
(
Cond
[
0
]
.
getImm
(
)
)
{
case
CAHP
::
BEQ
:
Cond
[
0
]
.
setImm
(
CAHP
::
BNE
)
;
break
;
case
CAHP
::
BNE
:
Cond
[
0
]
.
setImm
(
CAHP
::
BEQ
)
;
break
;
case
CAHP
::
BLT
:
Cond
[
0
]
.
setImm
(
CAHP
::
BLE
)
;
ShouldSwap
=
true
;
break
;
case
CAHP
::
BLE
:
Cond
[
0
]
.
setImm
(
CAHP
::
BLT
)
;
ShouldSwap
=
true
;
break
;
case
CAHP
::
BLTU
:
Cond
[
0
]
.
setImm
(
CAHP
::
BLEU
)
;
ShouldSwap
=
true
;
break
;
case
CAHP
::
BLEU
:
Cond
[
0
]
.
setImm
(
CAHP
::
BLTU
)
;
ShouldSwap
=
true
;
break
;
}
if
(
ShouldSwap
)
{
using
std
::
swap
;
swap
(
Cond
[
1
]
,
Cond
[
2
]
)
;
}
return
false
;
}
</s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> bool ARMTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( Subtarget -> isThumb1Only ( ) ) return false ; EVT VT ; SDValue Ptr ; unsigned Align ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; Align = LD -> getAlignment ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == ISD :: SEXTLOAD ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Align = ST -> getAlignment ( ) ; } else return false ; bool isInc ; bool isLegal = false ; if ( VT . isVector ( ) ) isLegal = Subtarget -> hasMVEIntegerOps ( ) && getMVEIndexedAddressParts ( Ptr . getNode ( ) , VT , Align , isSEXTLoad , Subtarget -> isLittle ( ) , Base , Offset , isInc , DAG ) ; else { if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = getARMIndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; } if ( ! isLegal ) return false ; AM = isInc ? ISD :: PRE_INC : ISD :: PRE_DEC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .

ARM ARM ISD::MemIndexedMode ISD::SEXTLOAD ARM ISD::PRE_INC ISD::PRE_DEC


<s> bool cris_constant_index_p ( const_rtx x ) { return ( CRIS_CONSTANT_P ( x ) && ( ! flag_pic || cris_valid_pic_const ( x , true ) ) ) ; } </s>

No symbol can be used as an index ( or more correct , as a base ) together with a register with PIC ; the PIC register must be there .


<s> int sparc_split_reg_mem_legitimate ( rtx reg , rtx mem ) { gcc_assert ( reload_completed ) ; if ( ! offsettable_memref_p ( mem ) ) return 0 ; if ( ( REGNO ( reg ) % 2 ) == 0 && mem_min_alignment ( mem , 8 ) ) return 0 ; return 1 ; } </s>

Return 1 if REG and MEM are legitimate enough to allow the various MEM < -- > REG splits to be run .


<s>
bool
X86AsmParser
::
processInstruction
(
MCInst
&
Inst
,
const
OperandVector
&
Ops
)
{
switch
(
Inst
.
getOpcode
(
)
)
{
default
:
return
false
;
case
X86
::
VMOVZPQILo2PQIrr
:
case
X86
::
VMOVAPDrr
:
case
X86
::
VMOVAPDYrr
:
case
X86
::
VMOVAPSrr
:
case
X86
::
VMOVAPSYrr
:
case
X86
::
VMOVDQArr
:
case
X86
::
VMOVDQAYrr
:
case
X86
::
VMOVDQUrr
:
case
X86
::
VMOVDQUYrr
:
case
X86
::
VMOVUPDrr
:
case
X86
::
VMOVUPDYrr
:
case
X86
::
VMOVUPSrr
:
case
X86
::
VMOVUPSYrr
:
{
if
(
X86II
::
isX86_64ExtendedReg
(
Inst
.
getOperand
(
0
)
.
getReg
(
)
)
||
!
X86II
::
isX86_64ExtendedReg
(
Inst
.
getOperand
(
1
)
.
getReg
(
)
)
)
return
false
;
unsigned
NewOpc
;
switch
(
Inst
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Invalid opcode"
)
;
case
X86
::
VMOVZPQILo2PQIrr
:
NewOpc
=
X86
::
VMOVPQI2QIrr
;
break
;
case
X86
::
VMOVAPDrr
:
NewOpc
=
X86
::
VMOVAPDrr_REV
;
break
;
case
X86
::
VMOVAPDYrr
:
NewOpc
=
X86
::
VMOVAPDYrr_REV
;
break
;
case
X86
::
VMOVAPSrr
:
NewOpc
=
X86
::
VMOVAPSrr_REV
;
break
;
case
X86
::
VMOVAPSYrr
:
NewOpc
=
X86
::
VMOVAPSYrr_REV
;
break
;
case
X86
::
VMOVDQArr
:
NewOpc
=
X86
::
VMOVDQArr_REV
;
break
;
case
X86
::
VMOVDQAYrr
:
NewOpc
=
X86
::
VMOVDQAYrr_REV
;
break
;
case
X86
::
VMOVDQUrr
:
NewOpc
=
X86
::
VMOVDQUrr_REV
;
break
;
case
X86
::
VMOVDQUYrr
:
NewOpc
=
X86
::
VMOVDQUYrr_REV
;
break
;
case
X86
::
VMOVUPDrr
:
NewOpc
=
X86
::
VMOVUPDrr_REV
;
break
;
case
X86
::
VMOVUPDYrr
:
NewOpc
=
X86
::
VMOVUPDYrr_REV
;
break
;
case
X86
::
VMOVUPSrr
:
NewOpc
=
X86
::
VMOVUPSrr_REV
;
break
;
case
X86
::
VMOVUPSYrr
:
NewOpc
=
X86
::
VMOVUPSYrr_REV
;
break
;
}
Inst
.
setOpcode
(
NewOpc
)
;
return
true
;
}
case
X86
::
VMOVSDrr
:
case
X86
::
VMOVSSrr
:
{
if
(
X86II
::
isX86_64ExtendedReg
(
Inst
.
getOperand
(
0
)
.
getReg
(
)
)
||
!
X86II
::
isX86_64ExtendedReg
(
Inst
.
getOperand
(
2
)
.
getReg
(
)
)
)
return
false
;
unsigned
NewOpc
;
switch
(
Inst
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Invalid opcode"
)
;
case
X86
::
VMOVSDrr
:
NewOpc
=
X86
::
VMOVSDrr_REV
;
break
;
case
X86
::
VMOVSSrr
:
NewOpc
=
X86
::
VMOVSSrr_REV
;
break
;
}
Inst
.
setOpcode
(
NewOpc
)
;
return
true
;
}
}
}
</s>

Process a single instruction and collect debug info anchors .


<s> bool X86TargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { if ( ! CI -> isTailCall ( ) || getTargetMachine ( ) . Options . DisableTailCalls ) return false ; CallSite CS ( CI ) ; CallingConv :: ID CalleeCC = CS . getCallingConv ( ) ; if ( ! IsTailCallConvention ( CalleeCC ) && ! IsCCallConvention ( CalleeCC ) ) return false ; return true ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> rtx rs6000_internal_arg_pointer ( void ) { if ( flag_split_stack && ( lookup_attribute ( "no_split_stack" , DECL_ATTRIBUTES ( cfun -> decl ) ) == NULL ) ) { if ( cfun -> machine -> split_stack_arg_pointer == NULL_RTX ) { rtx pat ; cfun -> machine -> split_stack_arg_pointer = gen_reg_rtx ( Pmode ) ; REG_POINTER ( cfun -> machine -> split_stack_arg_pointer ) = 1 ; pat = gen_rtx_SET ( cfun -> machine -> split_stack_arg_pointer , gen_rtx_REG ( Pmode , 12 ) ) ; push_topmost_sequence ( ) ; emit_insn_after ( pat , get_insns ( ) ) ; pop_topmost_sequence ( ) ; } rtx ret = plus_constant ( Pmode , cfun -> machine -> split_stack_arg_pointer , FIRST_PARM_OFFSET ( current_function_decl ) ) ; return copy_to_reg ( ret ) ; } return virtual_incoming_args_rtx ; } </s>

Return the internal arg pointer used for function incoming arguments . When -fsplit-stack , the arg pointer is r12 so we need to copy it to a pseudo in order for it to be preserved over calls and suchlike . We 'd really like to use a pseudo here for the internal arg pointer but data-flow analysis is not prepared to accept pseudos as live at the beginning of a function .


<s>
static
wasm
::
ValType
getType
(
const
TargetRegisterClass
*
RC
)
{
if
(
RC
==
&
WebAssembly
::
I32RegClass
)
return
wasm
::
ValType
::
I32
;
if
(
RC
==
&
WebAssembly
::
I64RegClass
)
return
wasm
::
ValType
::
I64
;
if
(
RC
==
&
WebAssembly
::
F32RegClass
)
return
wasm
::
ValType
::
F32
;
if
(
RC
==
&
WebAssembly
::
F64RegClass
)
return
wasm
::
ValType
::
F64
;
if
(
RC
==
&
WebAssembly
::
V128RegClass
)
return
wasm
::
ValType
::
V128
;
if
(
RC
==
&
WebAssembly
::
EXTERNREFRegClass
)
return
wasm
::
ValType
::
EXTERNREF
;
if
(
RC
==
&
WebAssembly
::
FUNCREFRegClass
)
return
wasm
::
ValType
::
FUNCREF
;
llvm_unreachable
(
"Unexpected register class"
)
;
}
</s>

Overload to return most specific vector type .

WebAssembly
wasm::ValType
WebAssembly::I32RegClass
wasm::ValType
WebAssembly::I64RegClass
wasm::ValType
WebAssembly::F32RegClass
wasm::ValType
WebAssembly::F64RegClass
wasm::ValType
WebAssembly::V128RegClass
wasm::ValType
WebAssembly::EXTERNREFRegClass
wasm::ValType
WebAssembly::FUNCREFRegClass
wasm::ValType
"Unexpected register class"


<s> static bool bfin_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { int size = int_size_in_bytes ( type ) ; return size > 2 * UNITS_PER_WORD || size == - 1 ; } </s>

Decide whether a type should be returned in memory ( true ) or in a register ( false ) . This is called by the macro RETURN_IN_MEMORY .


<s> bool TMS320C64XTargetMachine :: addPreRegAlloc ( PassManagerBase & PM , CodeGenOpt :: Level ) { bool wantScheduleForm ; switch ( ClusterOpt ) { default : wantScheduleForm = false ; break ; case ClusterUAS : case ClusterUAS_none : case ClusterUAS_rand : case ClusterUAS_mwp : wantScheduleForm = true ; break ; } if ( Subtarget . enableClusterAssignment ( ) ) { if ( wantScheduleForm ) PM . add ( createTMS320C64XBranchDelayExpander ( * this ) ) ; PM . add ( createTMS320C64XClusterAssignment ( * this , ClusterOpt ) ) ; if ( wantScheduleForm ) PM . add ( createTMS320C64XBranchDelayReducer ( * this ) ) ; } return false ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> bool XCoreTargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createXCoreISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s>
void
Mips16InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
=
0
;
if
(
Mips
::
CPU16RegsRegClass
.
contains
(
DestReg
)
&&
Mips
::
GPR32RegClass
.
contains
(
SrcReg
)
)
Opc
=
Mips
::
MoveR3216
;
else
if
(
Mips
::
GPR32RegClass
.
contains
(
DestReg
)
&&
Mips
::
CPU16RegsRegClass
.
contains
(
SrcReg
)
)
Opc
=
Mips
::
Move32R16
;
else
if
(
(
SrcReg
==
Mips
::
HI
)
&&
(
Mips
::
CPU16RegsRegClass
.
contains
(
DestReg
)
)
)
Opc
=
Mips
::
Mfhi16
,
SrcReg
=
0
;
else
if
(
(
SrcReg
==
Mips
::
LO
)
&&
(
Mips
::
CPU16RegsRegClass
.
contains
(
DestReg
)
)
)
Opc
=
Mips
::
Mflo16
,
SrcReg
=
0
;
assert
(
Opc
&&
"Cannot copy registers"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
)
;
if
(
DestReg
)
MIB
.
addReg
(
DestReg
,
RegState
::
Define
)
;
if
(
SrcReg
)
MIB
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> Register getExceptionSelectorRegister ( const Constant * PersonalityFn ) const override { return XCore :: R1 ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .


<s> void SNESMCCodeEmitter :: emitInstruction ( uint64_t Val , unsigned Size , const MCSubtargetInfo & STI , raw_ostream & OS ) const { const uint16_t * Words = reinterpret_cast < uint16_t const * > ( & Val ) ; size_t WordCount = Size / 2 ; for ( int64_t i = WordCount - 1 ; i >= 0 ; -- i ) { uint16_t Word = Words [ i ] ; OS << ( uint8_t ) ( ( Word & 0x00ff ) >> 0 ) ; OS << ( uint8_t ) ( ( Word & 0xff00 ) >> 8 ) ; } } </s>

Targets should implement this to emit instructions .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCInstFragment * DF , const MCAsmLayout & Layout ) const { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> void tilepro_final_prescan_insn ( rtx_insn * insn ) { insn_mode = GET_MODE ( insn ) ; } </s>

Implement FINAL_PRESCAN_INSN . This is used to emit bundles .


<s>
bool
HexagonFrameLowering
::
hasFP
(
const
MachineFunction
&
MF
)
const
{
if
(
MF
.
getFunction
(
)
->
hasFnAttribute
(
Attribute
::
Naked
)
)
return
false
;
auto
&
MFI
=
MF
.
getFrameInfo
(
)
;
auto
&
HRI
=
*
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getRegisterInfo
(
)
;
bool
HasExtraAlign
=
HRI
.
needsStackRealignment
(
MF
)
;
bool
HasAlloca
=
MFI
.
hasVarSizedObjects
(
)
;
if
(
MF
.
getTarget
(
)
.
getOptLevel
(
)
==
CodeGenOpt
::
)
return
true
;
if
(
HasAlloca
||
HasExtraAlign
)
return
true
;
if
(
MFI
.
getStackSize
(
)
>
0
)
{
const
TargetMachine
&
TM
=
MF
.
getTarget
(
)
;
if
(
TM
.
Options
.
DisableFramePointerElim
(
MF
)
||
!
EliminateFramePointer
)
return
true
;
if
(
EnableStackOVFSanitizer
)
return
true
;
}
const
auto
&
HMFI
=
*
MF
.
getInfo
<
HexagonMachineFunctionInfo
>
(
)
;
if
(
MFI
.
hasCalls
(
)
||
HMFI
.
hasClobberLR
(
)
)
return
true
;
assert
(
MFI
.
isCalleeSavedInfoValid
(
)
&&
"Need to know CSI"
)
;
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
.
getCalleeSavedInfo
(
)
;
if
(
useSpillFunction
(
MF
,
CSI
)
||
useRestoreFunction
(
MF
,
CSI
)
)
return
true
;
return
false
;
}
</s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .

Hexagon
Hexagon
Hexagon
0
Hexagon
"Need to know CSI"


<s> void MipsAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const { MCFixupKind Kind = Fixup . getKind ( ) ; MCContext & Ctx = Asm . getContext ( ) ; Value = adjustFixupValue ( Fixup , Value , Ctx ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { case FK_Data_2 : case Mips :: fixup_Mips_16 : case Mips :: fixup_MICROMIPS_PC10_S1 : FullSize = 2 ; break ; case FK_Data_8 : case Mips :: fixup_Mips_64 : FullSize = 8 ; break ; case FK_Data_4 : default : FullSize = 4 ; break ; } uint64_t CurVal = 0 ; bool microMipsLEByteOrder = needsMMLEByteOrder ( ( unsigned ) Kind ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? ( microMipsLEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - 1 - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? ( microMipsLEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool NVPTXPrologEpilogPass :: runOnMachineFunction ( MachineFunction & MF ) { const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const TargetFrameLowering & TFI = * STI . getFrameLowering ( ) ; const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; bool Modified = false ; calculateFrameObjectOffsets ( MF ) ; for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) { for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ++ I ) { MachineInstr * MI = I ; for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( ! MI -> getOperand ( i ) . isFI ( ) ) continue ; TRI . eliminateFrameIndex ( MI , 0 , i , nullptr ) ; Modified = true ; } } } TFI . emitPrologue ( MF , MF . front ( ) ) ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( ! I -> empty ( ) && I -> back ( ) . isReturn ( ) ) TFI . emitEpilogue ( MF , * I ) ; } return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool PPCLinuxAsmPrinter :: doFinalization ( Module & M ) { const DataLayout * TD = TM . getDataLayout ( ) ; bool isPPC64 = TD -> getPointerSizeInBits ( ) == 64 ; PPCTargetStreamer & TS = static_cast < PPCTargetStreamer & > ( * OutStreamer . getTargetStreamer ( ) ) ; if ( ! TOC . empty ( ) ) { const MCSectionELF * Section ; if ( isPPC64 ) Section = OutStreamer . getContext ( ) . getELFSection ( ".toc" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; else Section = OutStreamer . getContext ( ) . getELFSection ( ".got2" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; OutStreamer . SwitchSection ( Section ) ; for ( MapVector < MCSymbol * , MCSymbol * > :: iterator I = TOC . begin ( ) , E = TOC . end ( ) ; I != E ; ++ I ) { OutStreamer . EmitLabel ( I -> second ) ; MCSymbol * S = OutContext . GetOrCreateSymbol ( I -> first -> getName ( ) ) ; if ( isPPC64 ) TS . emitTCEntry ( * S ) ; else OutStreamer . EmitSymbolValue ( S , 4 ) ; } } MachineModuleInfoELF & MMIELF = MMI -> getObjFileInfo < MachineModuleInfoELF > ( ) ; MachineModuleInfoELF :: SymbolListTy Stubs = MMIELF . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


"OR1K PIC Global Base Reg Initialization"

getPassName - Return a nice clean name for a pass .


<s> std :: pair < unsigned , const TargetRegisterClass * > SparcTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'f' : return std :: make_pair ( 0U , & SP :: FPRegsRegClass ) ; case 'r' : if ( VT == MVT :: v2i32 ) return std :: make_pair ( 0U , & SP :: IntPairRegClass ) ; else return std :: make_pair ( 0U , & SP :: IntRegsRegClass ) ; } } else if ( ! Constraint . empty ( ) && Constraint . size ( ) <= 5 && Constraint [ 0 ] == '{' && * ( Constraint . end ( ) - 1 ) == '}' ) { StringRef name ( Constraint . data ( ) + 1 , Constraint . size ( ) - 2 ) ; uint64_t intVal = 0 ; if ( name . substr ( 0 , 1 ) . equals ( "r" ) && ! name . substr ( 1 ) . getAsInteger ( 10 , intVal ) && intVal <= 31 ) { const char regTypes [ ] = { 'g' , 'o' , 'l' , 'i' } ; char regType = regTypes [ intVal / 8 ] ; char regIdx = '0' + ( intVal % 8 ) ; char tmp [ ] = { '{' , regType , regIdx , '}' , 0 } ; std :: string newConstraint = std :: string ( tmp ) ; return TargetLowering :: getRegForInlineAsmConstraint ( TRI , newConstraint , VT ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> bool SystemZInstrInfo :: isPredicable ( MachineInstr * MI ) const { unsigned Opcode = MI -> getOpcode ( ) ; return STI . hasLoadStoreOnCond ( ) && getConditionalMove ( Opcode ) ; } </s>

Return true if the specified instruction can be predicated .


<s> bool addRange ( uint64_t Start , uint64_t End , Instruction * Inst ) { auto I = std :: lower_bound ( Ranges . begin ( ) , Ranges . end ( ) , Start , [ ] ( const Range & LHS , uint64_t RHS ) { return LHS . End <= RHS ; } ) ; if ( I != Ranges . end ( ) && End > I -> Start ) { return false ; } Ranges . insert ( I , { Start , End , Inst } ) ; return true ; } </s>

addRange - Add an address range to the list of ranges for this unit .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Mips Assembly Printer"
;
}
</s>


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
k_Immediate
:
OS
<<
"Imm<"
;
Imm
.
Val
->
print
(
OS
)
;
OS
<<
">"
;
break
;
case
k_Memory
:
OS
<<
"Mem<"
;
Mem
.
Base
->
print
(
OS
)
;
OS
<<
", "
;
Mem
.
Off
->
print
(
OS
)
;
OS
<<
">"
;
break
;
case
k_PhysRegister
:
OS
<<
"PhysReg<"
<<
PhysReg
.
Num
<<
">"
;
break
;
case
k_RegisterIndex
:
OS
<<
"RegIdx<"
<<
RegIdx
.
Index
<<
":"
<<
RegIdx
.
Kind
<<
">"
;
break
;
case
k_Token
:
OS
<<
Tok
.
Data
;
break
;
case
k_RegList
:
OS
<<
"RegList< "
;
for
(
auto
Reg
:
(
*
RegList
.
List
)
)
OS
<<
Reg
<<
" "
;
OS
<<
">"
;
break
;
case
k_RegPair
:
OS
<<
"RegPair<"
<<
RegIdx
.
Index
<<
","
<<
RegIdx
.
Index
+
1
<<
">"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> static void reorg_emit_nops ( rtx_insn * * call_labels ) { bool first ; rtx last_call ; rtx_insn * prev ; int prev_clock , earliest_bb_end ; int prev_implicit_nops ; rtx_insn * insn = get_insns ( ) ; insn = next_real_insn ( insn ) ; last_call = prev = NULL ; prev_clock = - 1 ; earliest_bb_end = 0 ; prev_implicit_nops = 0 ; first = true ; while ( insn ) { int this_clock = - 1 ; rtx_insn * next ; int max_cycles = 0 ; next = next_real_insn ( insn ) ; if ( DEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER || shadow_or_blockage_p ( insn ) || JUMP_TABLE_DATA_P ( insn ) ) goto next_insn ; if ( ! c6x_flag_schedule_insns2 ) PUT_MODE ( insn , TImode ) ; else { int cycles ; this_clock = insn_get_clock ( insn ) ; if ( this_clock != prev_clock ) { PUT_MODE ( insn , TImode ) ; if ( ! first ) { cycles = this_clock - prev_clock ; cycles -= prev_implicit_nops ; if ( cycles > 1 ) { rtx nop = emit_nop_after ( cycles - 1 , prev ) ; insn_set_clock ( nop , prev_clock + prev_implicit_nops + 1 ) ; } } prev_clock = this_clock ; if ( last_call && insn_get_clock ( last_call ) + 6 <= this_clock ) { emit_label_before ( call_labels [ INSN_UID ( last_call ) ] , insn ) ; last_call = NULL_RTX ; } prev_implicit_nops = 0 ; } } if ( recog_memoized ( insn ) >= 0 && ( c6x_flag_schedule_insns2 || ! returning_call_p ( insn ) ) ) { max_cycles = get_attr_cycles ( insn ) ; if ( get_attr_type ( insn ) == TYPE_CALLP ) prev_implicit_nops = 5 ; } else max_cycles = 1 ; if ( returning_call_p ( insn ) ) last_call = insn ; if ( c6x_flag_schedule_insns2 ) { gcc_assert ( this_clock >= 0 ) ; if ( earliest_bb_end < this_clock + max_cycles ) earliest_bb_end = this_clock + max_cycles ; } else if ( max_cycles > 1 ) emit_nop_after ( max_cycles - 1 , insn ) ; prev = insn ; first = false ; next_insn : if ( c6x_flag_schedule_insns2 && ( next == NULL_RTX || ( GET_MODE ( next ) == TImode && INSN_INFO_ENTRY ( INSN_UID ( next ) ) . ebb_start ) ) && earliest_bb_end > 0 ) { int cycles = earliest_bb_end - prev_clock ; if ( cycles > 1 ) { prev = emit_nop_after ( cycles - 1 , prev ) ; insn_set_clock ( prev , prev_clock + prev_implicit_nops + 1 ) ; } earliest_bb_end = 0 ; prev_clock = - 1 ; first = true ; if ( last_call ) emit_label_after ( call_labels [ INSN_UID ( last_call ) ] , prev ) ; last_call = NULL_RTX ; } insn = next ; } } </s>

Called as part of c6x_reorg . This function emits multi-cycle NOP insns as required for correctness . CALL_LABELS is the array that holds the return labels for call insns ; we emit these here if scheduling was run earlier .


<s>
bool
AArch64MCInstLower
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
const
{
switch
(
MO
.
getType
(
)
)
{
default
:
assert
(
0
&&
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
)
return
false
;
MCOp
=
MCOperand
::
CreateReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_RegisterMask
:
return
false
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
CreateImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
CreateExpr
(
MCSymbolRefExpr
::
Create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
Ctx
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
LowerSymbolOperand
(
MO
,
GetGlobalAddressSymbol
(
MO
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
LowerSymbolOperand
(
MO
,
GetExternalSymbolSymbol
(
MO
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
MCOp
=
LowerSymbolOperand
(
MO
,
Printer
.
GetJTISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
MCOp
=
LowerSymbolOperand
(
MO
,
Printer
.
GetCPISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_BlockAddress
:
MCOp
=
LowerSymbolOperand
(
MO
,
Printer
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
)
;
break
;
}
return
true
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> static void ix86_emit_mode_set ( int entity , int mode , int prev_mode ATTRIBUTE_UNUSED , HARD_REG_SET regs_live ) { switch ( entity ) { case AVX_U128 : if ( mode == AVX_U128_CLEAN ) ix86_avx_emit_vzeroupper ( regs_live ) ; break ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : case I387_MASK_PM : if ( mode != I387_CW_ANY && mode != I387_CW_UNINITIALIZED ) emit_i387_cw_initialization ( mode ) ; break ; default : gcc_unreachable ( ) ; } } </s>

Generate one or more insns to set ENTITY to MODE . HARD_REG_LIVE is the set of hard registers live at the point where the insn ( s ) are to be inserted .


<s> void rs6000_emit_swdiv ( rtx dst , rtx n , rtx d , bool note_p ) { machine_mode mode = GET_MODE ( dst ) ; rtx one , x0 , e0 , x1 , xprev , eprev , xnext , enext , u , v ; int i ; int passes = ( TARGET_RECIP_PRECISION ) ? 1 : 3 ; if ( mode == DFmode || mode == V2DFmode ) passes ++ ; enum insn_code code = optab_handler ( smul_optab , mode ) ; insn_gen_fn gen_mul = GEN_FCN ( code ) ; gcc_assert ( code != CODE_FOR_nothing ) ; one = rs6000_load_constant_and_splat ( mode , dconst1 ) ; x0 = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , d ) , UNSPEC_FRES ) ) ) ; if ( passes > 1 ) { e0 = gen_reg_rtx ( mode ) ; rs6000_emit_nmsub ( e0 , d , x0 , one ) ; x1 = gen_reg_rtx ( mode ) ; rs6000_emit_madd ( x1 , e0 , x0 , x0 ) ; for ( i = 0 , xprev = x1 , eprev = e0 ; i < passes - 2 ; ++ i , xprev = xnext , eprev = enext ) { enext = gen_reg_rtx ( mode ) ; emit_insn ( gen_mul ( enext , eprev , eprev ) ) ; xnext = gen_reg_rtx ( mode ) ; rs6000_emit_madd ( xnext , enext , xprev , xprev ) ; } } else xprev = x0 ; u = gen_reg_rtx ( mode ) ; emit_insn ( gen_mul ( u , n , xprev ) ) ; v = gen_reg_rtx ( mode ) ; rs6000_emit_nmsub ( v , d , u , n ) ; rs6000_emit_madd ( dst , v , xprev , u ) ; if ( note_p ) add_reg_note ( get_last_insn ( ) , REG_EQUAL , gen_rtx_DIV ( mode , n , d ) ) ; } </s>

Newton-Raphson approximation of floating point divide DST = N/D . If NOTE_P , add a reg_note saying that this was a division . Support both scalar and vector divide . Assumes no trapping math and finite arguments .


<s> static int thumb1_base_register_rtx_p ( rtx x , machine_mode mode , int strict_p ) { int regno ; if ( ! REG_P ( x ) ) return 0 ; regno = REGNO ( x ) ; if ( strict_p ) return THUMB1_REGNO_MODE_OK_FOR_BASE_P ( regno , mode ) ; return ( regno <= LAST_LO_REGNUM || regno > LAST_VIRTUAL_REGISTER || regno == FRAME_POINTER_REGNUM || ( GET_MODE_SIZE ( mode ) >= 4 && ( regno == STACK_POINTER_REGNUM || regno >= FIRST_PSEUDO_REGISTER || x == hard_frame_pointer_rtx || x == arg_pointer_rtx ) ) ) ; } </s>

Return nonzero if X is valid as a 16-bit Thumb state base register .


<s> virtual const TargetFrameInfo * getFrameInfo ( ) const { return & FrameInfo ; } </s>

getFrameInfo - Return the frame info object for the current function .


<s> static HARD_REG_SET ix86_zero_call_used_regs ( HARD_REG_SET need_zeroed_hardregs ) { HARD_REG_SET zeroed_hardregs ; bool all_sse_zeroed = false ; int all_st_zeroed_num = 0 ; bool all_mm_zeroed = false ; CLEAR_HARD_REG_SET ( zeroed_hardregs ) ; rtx zero_all_vec_insn = zero_all_vector_registers ( need_zeroed_hardregs ) ; if ( zero_all_vec_insn ) { emit_insn ( zero_all_vec_insn ) ; all_sse_zeroed = true ; } bool exit_with_mmx_mode = ( crtl -> return_rtx && ( MMX_REG_P ( crtl -> return_rtx ) ) ) ; if ( ! exit_with_mmx_mode ) { all_st_zeroed_num = zero_all_st_registers ( need_zeroed_hardregs ) ; if ( all_st_zeroed_num > 0 ) for ( unsigned int regno = FIRST_STACK_REG ; regno <= LAST_STACK_REG ; regno ++ ) if ( all_st_zeroed_num == 8 || ! ( ( all_st_zeroed_num >= 6 && regno == REGNO ( crtl -> return_rtx ) ) || ( all_st_zeroed_num == 6 && ( regno == ( REGNO ( crtl -> return_rtx ) + 1 ) ) ) ) ) SET_HARD_REG_BIT ( zeroed_hardregs , regno ) ; } else { unsigned int exit_mmx_regno = REGNO ( crtl -> return_rtx ) ; all_mm_zeroed = zero_all_mm_registers ( need_zeroed_hardregs , exit_mmx_regno ) ; if ( all_mm_zeroed ) for ( unsigned int regno = FIRST_MMX_REG ; regno <= LAST_MMX_REG ; regno ++ ) if ( regno != exit_mmx_regno ) SET_HARD_REG_BIT ( zeroed_hardregs , regno ) ; } for ( unsigned int regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) { if ( ! TEST_HARD_REG_BIT ( need_zeroed_hardregs , regno ) ) continue ; if ( ! zero_call_used_regno_p ( regno , all_sse_zeroed , exit_with_mmx_mode && ! all_mm_zeroed ) ) continue ; SET_HARD_REG_BIT ( zeroed_hardregs , regno ) ; machine_mode mode = zero_call_used_regno_mode ( regno ) ; rtx reg = gen_rtx_REG ( mode , regno ) ; rtx tmp = gen_rtx_SET ( reg , CONST0_RTX ( mode ) ) ; switch ( mode ) { case E_SImode : if ( ! TARGET_USE_MOV0 || optimize_insn_for_size_p ( ) ) { rtx clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , tmp , clob ) ) ; } case E_V4SFmode : case E_HImode : case E_V2SImode : emit_insn ( tmp ) ; break ; default : gcc_unreachable ( ) ; } } return zeroed_hardregs ; } </s>

Generate a sequence of instructions that zero registers specified by NEED_ZEROED_HARDREGS . Return the ZEROED_HARDREGS that are actually zeroed .


<s>
const
char
*
output_probe_stack_range
(
rtx
reg1
,
rtx
reg2
)
{
static
int
labelno
=
0
;
char
loop_lab
[
32
]
;
rtx
xops
[
3
]
;
ASM_GENERATE_INTERNAL_LABEL
(
loop_lab
,
"LPSRL"
,
labelno
++
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
loop_lab
)
;
xops
[
0
]
=
reg1
;
xops
[
1
]
=
GEN_INT
(
PROBE_INTERVAL
)
;
output_asm_insn
(
"addl %0 = %1, %0"
,
xops
)
;
fputs
(
"\t;;\n"
,
asm_out_file
)
;
output_asm_insn
(
"probe.w.fault %0, 0"
,
xops
)
;
xops
[
1
]
=
reg2
;
xops
[
2
]
=
gen_rtx_REG
(
BImode
,
PR_REG
(
6
)
)
;
output_asm_insn
(
"cmp.eq %2, %I2 = %0, %1"
,
xops
)
;
fprintf
(
asm_out_file
,
"\t(%s) br.cond.dpnt "
,
reg_names
[
PR_REG
(
7
)
]
)
;
assemble_name_raw
(
asm_out_file
,
loop_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
return
""
;
}
</s>

Wrapper around the output_probe_stack_range routines .


"Unable to get the legal offset for nil instruction."

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s>
static
void
rs6000_file_start
(
void
)
{
size_t
i
;
char
buffer
[
80
]
;
const
char
*
start
=
buffer
;
struct
rs6000_cpu_select
*
ptr
;
const
char
*
default_cpu
=
TARGET_CPU_DEFAULT
;
FILE
*
file
=
asm_out_file
;
default_file_start
(
)
;
if
(
(
TARGET_DEFAULT
^
target_flags
)
&
MASK_64BIT
)
default_cpu
=
0
;
if
(
flag_verbose_asm
)
{
sprintf
(
buffer
,
"\n%s rs6000/powerpc options:"
,
ASM_COMMENT_START
)
;
rs6000_select
[
0
]
.
string
=
default_cpu
;
for
(
i
=
0
;
i
<
ARRAY_SIZE
(
rs6000_select
)
;
i
++
)
{
ptr
=
&
rs6000_select
[
i
]
;
if
(
ptr
->
string
!=
(
char
*
)
0
&&
ptr
->
string
[
0
]
!=
'\0'
)
{
fprintf
(
file
,
"%s %s%s"
,
start
,
ptr
->
name
,
ptr
->
string
)
;
start
=
""
;
}
}
if
(
PPC405_ERRATUM77
)
{
fprintf
(
file
,
"%s PPC405CR_ERRATUM77"
,
start
)
;
start
=
""
;
}
switch
(
rs6000_sdata
)
{
case
SDATA_NONE
:
fprintf
(
file
,
"%s -msdata=none"
,
start
)
;
start
=
""
;
break
;
case
SDATA_DATA
:
fprintf
(
file
,
"%s -msdata=data"
,
start
)
;
start
=
""
;
break
;
case
SDATA_SYSV
:
fprintf
(
file
,
"%s -msdata=sysv"
,
start
)
;
start
=
""
;
break
;
case
SDATA_EABI
:
fprintf
(
file
,
"%s -msdata=eabi"
,
start
)
;
start
=
""
;
break
;
}
if
(
rs6000_sdata
&&
g_switch_value
)
{
fprintf
(
file
,
"%s -G "
HOST_WIDE_INT_PRINT_UNSIGNED
,
start
,
g_switch_value
)
;
start
=
""
;
}
if
(
*
start
==
'\0'
)
putc
(
'\n'
,
file
)
;
}
if
(
DEFAULT_ABI
==
ABI_AIX
||
(
TARGET_ELF
&&
flag_pic
==
2
)
)
{
toc_section
(
)
;
text_section
(
)
;
}
}
</s>

Do anything needed at the start of the asm file .


<s> static bool mn10300_rtx_costs ( rtx x , int code , int outer_code , int * total ) { switch ( code ) { case CONST_INT : if ( INTVAL ( x ) == 0 && outer_code == SET ) * total = 0 ; else if ( INT_8_BITS ( INTVAL ( x ) ) ) * total = 1 ; else if ( INT_16_BITS ( INTVAL ( x ) ) || ( INTVAL ( x ) & 0xffff ) == 0 || ( INTVAL ( x ) & 0xffff0000 ) == 0 ) * total = 2 ; else * total = 4 ; return true ; case CONST : case LABEL_REF : case SYMBOL_REF : * total = 6 ; return true ; case CONST_DOUBLE : * total = 8 ; return true ; case MOD : case DIV : case MULT : * total = 8 ; return true ; default : return false ; } } </s>

Implement the TARGET_RTX_COSTS hook . Speed-relative costs are relative to COSTS_N_INSNS , which is intended to represent cycles . Size-relative costs are in bytes .


<s> static int get_insn_side ( rtx_insn * insn , enum attr_units units ) { if ( units == UNITS_D_ADDR ) return ( get_attr_addr_regfile ( insn ) == ADDR_REGFILE_A ? 0 : 1 ) ; else { enum attr_dest_regfile rf = get_attr_dest_regfile ( insn ) ; if ( rf == DEST_REGFILE_ANY ) return get_attr_type ( insn ) == TYPE_BRANCH ? 0 : 1 ; else return rf == DEST_REGFILE_A ? 0 : 1 ; } } </s>

Compute the side of the machine used by INSN , which reserves UNITS . This must match the reservations in the scheduling description .


<s> const char * LC3TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return NULL ; case LC3ISD :: RET_FLAG : return "RetFlag" ; case LC3ISD :: LOAD_SYM : return "LOAD_SYM" ; case LC3ISD :: MOVEi16 : return "MOVEi16" ; case LC3ISD :: CALL : return "CALL" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> void ix86_expand_truncdf_32 ( rtx operand0 , rtx operand1 ) { machine_mode mode = GET_MODE ( operand0 ) ; rtx xa , xa2 , TWO52 , tmp , one , res , mask ; rtx_code_label * label ; TWO52 = ix86_gen_TWO52 ( mode ) ; res = copy_to_reg ( operand1 ) ; xa = ix86_expand_sse_fabs ( res , & mask ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; xa2 = expand_simple_binop ( mode , PLUS , xa , TWO52 , NULL_RTX , 0 , OPTAB_DIRECT ) ; xa2 = expand_simple_binop ( mode , MINUS , xa2 , TWO52 , xa2 , 0 , OPTAB_DIRECT ) ; one = force_reg ( mode , const_double_from_real_value ( dconst1 , mode ) ) ; tmp = ix86_expand_sse_compare_mask ( UNGT , xa2 , xa , false ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_AND ( mode , one , tmp ) ) ) ; tmp = expand_simple_binop ( mode , MINUS , xa2 , tmp , NULL_RTX , 0 , OPTAB_DIRECT ) ; if ( HONOR_SIGNED_ZEROS ( mode ) && flag_rounding_math ) tmp = ix86_expand_sse_fabs ( tmp , NULL ) ; ix86_sse_copysign_to_positive ( res , tmp , res , mask ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; emit_move_insn ( operand0 , res ) ; } </s>

Expand SSE sequence for computing trunc from OPERAND1 storing into OPERAND0 .


"2003f Eliminate Pseudo Instr FI_MALKRZ"

getPassName - Return a nice clean name for a pass .


<s> static reg_class_t pa_secondary_reload ( bool in_p , rtx x , reg_class_t rclass_i , machine_mode mode , secondary_reload_info * sri ) { int regno ; enum reg_class rclass = ( enum reg_class ) rclass_i ; if ( rclass == R1_REGS ) return NO_REGS ; if ( REG_P ( x ) ) { regno = REGNO ( x ) ; if ( rclass == BASE_REG_CLASS && regno < FIRST_PSEUDO_REGISTER ) return NO_REGS ; } else regno = - 1 ; if ( GET_CODE ( x ) == MEM && GET_CODE ( XEXP ( x , 0 ) ) == MEM ) return NO_REGS ; if ( flag_pic && FP_REG_CLASS_P ( rclass ) && ( GET_CODE ( x ) == CONST_INT || GET_CODE ( x ) == CONST_DOUBLE ) ) { switch ( mode ) { case E_SImode : sri -> icode = CODE_FOR_reload_insi_r1 ; break ; case E_DImode : sri -> icode = CODE_FOR_reload_indi_r1 ; break ; case E_SFmode : sri -> icode = CODE_FOR_reload_insf_r1 ; break ; case E_DFmode : sri -> icode = CODE_FOR_reload_indf_r1 ; break ; default : gcc_unreachable ( ) ; } return NO_REGS ; } if ( pa_symbolic_expression_p ( x ) ) { if ( GET_CODE ( x ) == HIGH ) x = XEXP ( x , 0 ) ; if ( flag_pic || ! read_only_operand ( x , VOIDmode ) ) { switch ( mode ) { case E_SImode : sri -> icode = CODE_FOR_reload_insi_r1 ; break ; case E_DImode : sri -> icode = CODE_FOR_reload_indi_r1 ; break ; default : gcc_unreachable ( ) ; } return NO_REGS ; } } if ( regno >= FIRST_PSEUDO_REGISTER || GET_CODE ( x ) == SUBREG ) regno = true_regnum ( x ) ; if ( ( regno >= FIRST_PSEUDO_REGISTER || regno == - 1 ) && FP_REG_CLASS_P ( rclass ) ) { if ( MEM_P ( x ) ) { x = XEXP ( x , 0 ) ; if ( IS_INDEX_ADDR_P ( x ) ) return NO_REGS ; } sri -> icode = ( in_p ? direct_optab_handler ( reload_in_optab , mode ) : direct_optab_handler ( reload_out_optab , mode ) ) ; return NO_REGS ; } if ( rclass == SHIFT_REGS ) { if ( regno >= FIRST_PSEUDO_REGISTER || regno < 0 ) { sri -> icode = ( in_p ? direct_optab_handler ( reload_in_optab , mode ) : direct_optab_handler ( reload_out_optab , mode ) ) ; return NO_REGS ; } if ( FP_REG_CLASS_P ( REGNO_REG_CLASS ( regno ) ) ) return GENERAL_REGS ; } if ( regno >= 0 && regno < FIRST_PSEUDO_REGISTER && REGNO_REG_CLASS ( regno ) == SHIFT_REGS && FP_REG_CLASS_P ( rclass ) ) return GENERAL_REGS ; return NO_REGS ; } </s>

Inform reload about cases where moving X with a mode MODE to or from a register in RCLASS requires an extra scratch or immediate register . Return the class needed for the immediate register .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"WebAssembly Prepare For LiveIntervals"
;
}
</s>

WebAssembly
"WebAssembly Prepare For LiveIntervals"


"%qs attribute only applies to functions"

Handle an `` interrupt '' attribute ; arguments as in struct attribute_spec.handler .


<s> const SIRegisterInfo & getRegisterInfo ( ) const override { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> InstructionCost RISCVTTIImpl :: getMinMaxReductionCost ( VectorType * Ty , VectorType * CondTy , bool IsUnsigned , TTI :: TargetCostKind CostKind ) { if ( ! isa < FixedVectorType > ( Ty ) ) return BaseT :: getMinMaxReductionCost ( Ty , CondTy , IsUnsigned , CostKind ) ; if ( ! ST -> useRVVForFixedLengthVectors ( ) ) return BaseT :: getMinMaxReductionCost ( Ty , CondTy , IsUnsigned , CostKind ) ; if ( Ty -> getScalarSizeInBits ( ) > ST -> getMaxELENForFixedLengthVectors ( ) ) return BaseT :: getMinMaxReductionCost ( Ty , CondTy , IsUnsigned , CostKind ) ; InstructionCost BaseCost = 2 ; unsigned VL = cast < FixedVectorType > ( Ty ) -> getNumElements ( ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; return ( LT . first - 1 ) + BaseCost + Log2_32_Ceil ( VL ) ; } </s>

Try to calculate op costs for min/max reduction operations .


"Load should return a value and a chain"

LowerOperation - Provide custom lowering hooks for some operations .


<s> static void set_callers_may_not_allocate_frame ( function * fn ) { basic_block bb ; gimple_stmt_iterator gsi ; gimple * stmt ; tree called_fn_tree ; function * called_fn ; if ( fn -> cfg == NULL ) return ; FOR_EACH_BB_FN ( bb , fn ) { for ( gsi = gsi_start_bb ( bb ) ; ! gsi_end_p ( gsi ) ; gsi_next ( & gsi ) ) { stmt = gsi_stmt ( gsi ) ; if ( is_gimple_call ( stmt ) ) { called_fn_tree = gimple_call_fndecl ( stmt ) ; if ( called_fn_tree != NULL ) { called_fn = DECL_STRUCT_FUNCTION ( called_fn_tree ) ; if ( called_fn != NULL ) called_fn -> machine -> callers_may_not_allocate_frame = true ; } } } } return ; } </s>

Set the callers_may_not_allocate_frame flag for any function which function FN calls because FN may not allocate a frame header .


<s> static void AnalyzeArguments ( CCState & State , SmallVectorImpl < CCValAssign > & ArgLocs , const SmallVectorImpl < ArgT > & Args ) { static const uint16_t RegList [ ] = { MD :: R0 , MD :: R1 , MD :: R2 , MD :: R3 } ; static const unsigned NbRegs = array_lengthof ( RegList ) ; if ( State . isVarArg ( ) ) { AnalyzeVarArgs ( State , Args ) ; return ; } SmallVector < unsigned , 4 > ArgsParts ; ParseFunctionArgs ( Args , ArgsParts ) ; unsigned RegsLeft = NbRegs ; bool UseStack = false ; unsigned ValNo = 0 ; for ( unsigned i = 0 , e = ArgsParts . size ( ) ; i != e ; i ++ ) { MVT ArgVT = Args [ ValNo ] . VT ; ISD :: ArgFlagsTy ArgFlags = Args [ ValNo ] . Flags ; MVT LocVT = ArgVT ; CCValAssign :: LocInfo LocInfo = CCValAssign :: Full ; if ( ArgFlags . isByVal ( ) ) { State . HandleByVal ( ValNo ++ , ArgVT , LocVT , LocInfo , 2 , 2 , ArgFlags ) ; continue ; } unsigned Parts = ArgsParts [ i ] ; if ( ! UseStack && Parts <= RegsLeft ) { unsigned FirstVal = ValNo ; for ( unsigned j = 0 ; j < Parts ; j ++ ) { unsigned Reg = State . AllocateReg ( RegList , NbRegs ) ; State . addLoc ( CCValAssign :: getReg ( ValNo ++ , ArgVT , Reg , LocVT , LocInfo ) ) ; RegsLeft -- ; } } else { UseStack = true ; for ( unsigned j = 0 ; j < Parts ; j ++ ) { if ( ArgFlags . isByVal ( ) ) { State . HandleByVal ( ValNo ++ , ArgVT , LocVT , LocInfo , 4 , 4 , ArgFlags ) ; continue ; } if ( LocVT == MVT :: i32 || LocVT == MVT :: f32 ) { unsigned Offset1 = State . AllocateStack ( 4 , 4 ) ; State . addLoc ( CCValAssign :: getMem ( ValNo ++ , ArgVT , Offset1 , LocVT , LocInfo ) ) ; continue ; } } } } } </s>

The function will invoke AnalyzeCallOperands .


<s> static section * ft32_select_section ( tree decl , int reloc , unsigned HOST_WIDE_INT align ) { if ( TREE_TYPE ( decl ) != error_mark_node && TYPE_ADDR_SPACE ( TREE_TYPE ( decl ) ) == ADDR_SPACE_PM ) { if ( ! DECL_P ( decl ) ) return get_section ( "._pm" , SECTION_WRITE | SECTION_DEBUG , NULL ) ; return get_named_section ( decl , "._pm" , reloc ) ; } return default_elf_select_section ( decl , reloc , align ) ; } </s>


<s> std :: pair < SDValue , SDValue > SystemZSelectionDAGInfo :: EmitTargetCodeForMemchr ( SelectionDAG & DAG , SDLoc DL , SDValue Chain , SDValue Src , SDValue Char , SDValue Length , MachinePointerInfo SrcPtrInfo ) const { EVT PtrVT = Src . getValueType ( ) ; SDVTList VTs = DAG . getVTList ( PtrVT , MVT :: Other , MVT :: Glue ) ; Length = DAG . getZExtOrTrunc ( Length , DL , PtrVT ) ; Char = DAG . getZExtOrTrunc ( Char , DL , MVT :: i32 ) ; Char = DAG . getNode ( ISD :: AND , DL , MVT :: i32 , Char , DAG . getConstant ( 255 , DL , MVT :: i32 ) ) ; SDValue Limit = DAG . getNode ( ISD :: ADD , DL , PtrVT , Src , Length ) ; SDValue End = DAG . getNode ( SystemZISD :: SEARCH_STRING , DL , VTs , Chain , Limit , Src , Char ) ; Chain = End . getValue ( 1 ) ; SDValue Glue = End . getValue ( 2 ) ; SDValue Ops [ ] = { End , DAG . getConstant ( 0 , DL , PtrVT ) , DAG . getConstant ( SystemZ :: CCMASK_SRST , DL , MVT :: i32 ) , DAG . getConstant ( SystemZ :: CCMASK_SRST_FOUND , DL , MVT :: i32 ) , Glue } ; VTs = DAG . getVTList ( PtrVT , MVT :: Glue ) ; End = DAG . getNode ( SystemZISD :: SELECT_CCMASK , DL , VTs , Ops ) ; return std :: make_pair ( End , Chain ) ; } </s>

Emit target-specific code that performs a memchr , in cases where that is faster than a libcall .


<s> bool Thumb1FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned CFSize = MFI . getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( 1 << 8 ) - 1 ) * 4 / 2 ) return false ; return ! MFI . hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> void PPCPostRASchedStrategy :: enterMBB ( MachineBasicBlock * MBB ) { PostGenericScheduler :: enterMBB ( MBB ) ; } </s>

Tell the strategy that MBB is about to be processed .


<s> static bool ix86_tieable_integer_mode_p ( machine_mode mode ) { switch ( mode ) { case E_HImode : case E_SImode : return true ; case E_QImode : return TARGET_64BIT || ! TARGET_PARTIAL_REG_STALL ; case E_DImode : return TARGET_64BIT ; default : return false ; } } </s>

A subroutine of ix86_modes_tieable_p . Return true if MODE is a tieable integer mode .


<s> static void moxie_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain_value ) { rtx mem , fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp , SImode , 4 ) ; emit_move_insn ( mem , chain_value ) ; mem = adjust_address ( m_tramp , SImode , 16 ) ; emit_move_insn ( mem , fnaddr ) ; } </s>

Worker function for TARGET_TRAMPOLINE_INIT .


"CAHP DAG->DAG Pattern Instruction Selection"


<s> const char * X86_64Relocator :: getName ( Relocation :: Type pType ) const { return X86_64ApplyFunctions [ pType ] . name ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .