<s>
void
HexagonHazardRecognizer
::
EmitInstruction
(
SUnit
*
SU
)
{
MachineInstr
*
MI
=
SU
->
getInstr
(
)
;
if
(
!
MI
)
return
;
for
(
ConstMIOperands
MO
(
*
MI
)
;
MO
.
isValid
(
)
;
++
MO
)
if
(
MO
->
isReg
(
)
&&
MO
->
isDef
(
)
&&
!
MO
->
isImplicit
(
)
)
RegDefs
.
insert
(
MO
->
getReg
(
)
)
;
if
(
TII
->
isZeroCost
(
MI
->
getOpcode
(
)
)
)
return
;
if
(
!
Resources
->
canReserveResources
(
*
MI
)
)
{
assert
(
TII
->
mayBeNewStore
(
*
MI
)
&&
"Expecting .new store"
)
;
MachineFunction
*
MF
=
MI
->
getParent
(
)
->
getParent
(
)
;
MachineInstr
*
NewMI
=
MF
->
CreateMachineInstr
(
TII
->
get
(
TII
->
getDotNewOp
(
*
MI
)
)
,
MI
->
getDebugLoc
(
)
)
;
assert
(
Resources
->
canReserveResources
(
*
NewMI
)
)
;
Resources
->
reserveResources
(
*
NewMI
)
;
MF
->
DeleteMachineInstr
(
NewMI
)
;
}
else
Resources
->
reserveResources
(
*
MI
)
;
DEBUG
(
dbgs
(
)
<<
" Add instruction "
<<
*
MI
)
;
if
(
TII
->
mayBeCurLoad
(
*
MI
)
)
for
(
auto
&
S
:
SU
->
Succs
)
if
(
S
.
isAssignedRegDep
(
)
&&
S
.
getLatency
(
)
==
0
&&
SU
->
getHeight
(
)
==
S
.
getSUnit
(
)
->
getHeight
(
)
)
{
UsesDotCur
=
S
.
getSUnit
(
)
;
DotCurPNum
=
PacketNum
;
break
;
}
if
(
SU
==
UsesDotCur
)
{
UsesDotCur
=
nullptr
;
DotCurPNum
=
1
;
}
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .

Hexagon
Hexagon
"Expecting .new store"
" Add instruction "
0
1


<s>
const
char
*
getPassName
(
)
const
{
return
"R600 Vector Registers Merge Pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> Optional < MCFixupKind > ARMAsmBackendELF :: getFixupKind ( StringRef Name ) const { unsigned Type = llvm :: StringSwitch < unsigned > ( Name ) . Case ( "BFD_RELOC_NONE" , ELF :: R_ARM_NONE ) . Case ( "BFD_RELOC_8" , ELF :: R_ARM_ABS8 ) . Case ( "BFD_RELOC_16" , ELF :: R_ARM_ABS16 ) . Case ( "BFD_RELOC_32" , ELF :: R_ARM_ABS32 ) . Default ( - 1u ) ; if ( Type == - 1u ) return None ; return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> static void convert_to_callp ( rtx_insn * insn ) { rtx lab ; extract_insn ( insn ) ; if ( GET_CODE ( PATTERN ( insn ) ) == SET ) { rtx dest = recog_data . operand [ 0 ] ; lab = recog_data . operand [ 1 ] ; PATTERN ( insn ) = gen_callp_value ( dest , lab ) ; INSN_CODE ( insn ) = CODE_FOR_callp_value ; } else { lab = recog_data . operand [ 0 ] ; PATTERN ( insn ) = gen_callp ( lab ) ; INSN_CODE ( insn ) = CODE_FOR_callp ; } } </s>

Convert the pattern of INSN , which must be a CALL_INSN , into a callp .


<s> static void avr_addr_space_diagnose_usage ( addr_space_t as , location_t loc ) { ( void ) avr_addr_space_supported_p ( as , loc ) ; } </s>

Implement ` TARGET_ADDR_SPACE_DIAGNOSE_USAGE ' .


<s> rtx function_expander :: generate_insn ( insn_code icode ) { expand_insn ( icode , m_ops . length ( ) , m_ops . address ( ) ) ; return function_returns_void_p ( ) ? const0_rtx : m_ops [ 0 ] . value ; } </s>

Generate instruction ICODE , given that its operands have already been added to M_OPS . Return the value of the first operand .


<s> static bool arm_is_segment_info_known ( rtx orig , bool * is_readonly ) { * is_readonly = false ; if ( LABEL_REF_P ( orig ) ) { * is_readonly = true ; return true ; } if ( SYMBOL_REF_P ( orig ) ) { if ( CONSTANT_POOL_ADDRESS_P ( orig ) ) { * is_readonly = true ; return true ; } if ( SYMBOL_REF_LOCAL_P ( orig ) && ! SYMBOL_REF_EXTERNAL_P ( orig ) && SYMBOL_REF_DECL ( orig ) && ( ! DECL_P ( SYMBOL_REF_DECL ( orig ) ) || ! DECL_COMMON ( SYMBOL_REF_DECL ( orig ) ) ) ) { tree decl = SYMBOL_REF_DECL ( orig ) ; tree init = ( TREE_CODE ( decl ) == VAR_DECL ) ? DECL_INITIAL ( decl ) : ( TREE_CODE ( decl ) == CONSTRUCTOR ) ? decl : 0 ; int reloc = 0 ; bool named_section , readonly ; if ( init && init != error_mark_node ) reloc = compute_reloc_for_constant ( init ) ; named_section = TREE_CODE ( decl ) == VAR_DECL && lookup_attribute ( "section" , DECL_ATTRIBUTES ( decl ) ) ; readonly = decl_readonly_section ( decl , reloc ) ; if ( named_section ) return false ; * is_readonly = readonly ; return true ; } return false ; } gcc_unreachable ( ) ; } </s>

Try to determine whether an object , referenced via ORIG , will be placed in the text or data segment . This is used in FDPIC mode , to decide which relocations to use when accessing ORIG . * IS_READONLY is set to true if ORIG is a read-only location , false otherwise . Return true if we could determine the location of ORIG , false otherwise . * IS_READONLY is valid only when we return true .


<s> bool s390_match_ccmode ( rtx insn , enum machine_mode req_mode ) { int i ; if ( req_mode == VOIDmode ) return false ; if ( GET_CODE ( PATTERN ( insn ) ) == SET ) return s390_match_ccmode_set ( PATTERN ( insn ) , req_mode ) ; if ( GET_CODE ( PATTERN ( insn ) ) == PARALLEL ) for ( i = 0 ; i < XVECLEN ( PATTERN ( insn ) , 0 ) ; i ++ ) { rtx set = XVECEXP ( PATTERN ( insn ) , 0 , i ) ; if ( GET_CODE ( set ) == SET ) if ( ! s390_match_ccmode_set ( set , req_mode ) ) return false ; } return true ; } </s>

Return true if every SET in INSN that sets the CC register has source and destination with matching CC modes and that CC mode is at least as constrained as REQ_MODE .


<s> bool Thumb1FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; bool isVarArg = AFI -> getArgRegsSaveSize ( ) > 0 ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , TII . get ( ARM :: tPOP ) ) ; AddDefaultPred ( MIB ) ; bool NumRegs = false ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( Reg == ARM :: LR ) { if ( isVarArg ) continue ; Reg = ARM :: PC ; ( * MIB ) . setDesc ( TII . get ( ARM :: tPOP_RET ) ) ; MIB . copyImplicitOps ( & * MI ) ; MI = MBB . erase ( MI ) ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; NumRegs = true ; } if ( NumRegs ) MBB . insert ( MI , & * MIB ) ; else MF . DeleteMachineInstr ( MIB ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s>
void
SparcFrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
SparcMachineFunctionInfo
*
FuncInfo
=
MF
.
getInfo
<
SparcMachineFunctionInfo
>
(
)
;
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
const
SparcInstrInfo
&
TII
=
*
static_cast
<
const
SparcInstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
dl
=
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
int
NumBytes
=
(
int
)
MFI
->
getStackSize
(
)
;
unsigned
SAVEri
=
SP
::
SAVEri
;
unsigned
SAVErr
=
SP
::
SAVErr
;
if
(
FuncInfo
->
isLeafProc
(
)
)
{
if
(
NumBytes
==
0
)
return
;
SAVEri
=
SP
::
ADDri
;
SAVErr
=
SP
::
ADDrr
;
}
NumBytes
=
MF
.
getSubtarget
<
SparcSubtarget
>
(
)
.
getAdjustedFrameSize
(
NumBytes
)
;
emitSPAdjustment
(
MF
,
MBB
,
MBBI
,
NumBytes
,
SAVErr
,
SAVEri
)
;
MachineModuleInfo
&
MMI
=
MF
.
getMMI
(
)
;
const
MCRegisterInfo
*
MRI
=
MMI
.
getContext
(
)
.
getRegisterInfo
(
)
;
unsigned
regFP
=
MRI
->
getDwarfRegNum
(
SP
::
I6
,
true
)
;
unsigned
CFIIndex
=
MMI
.
addFrameInst
(
MCCFIInstruction
::
createDefCfaRegister
(
nullptr
,
regFP
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
TargetOpcode
::
CFI_INSTRUCTION
)
)
.
addCFIIndex
(
CFIIndex
)
;
CFIIndex
=
MMI
.
addFrameInst
(
MCCFIInstruction
::
createWindowSave
(
nullptr
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
TargetOpcode
::
CFI_INSTRUCTION
)
)
.
addCFIIndex
(
CFIIndex
)
;
unsigned
regInRA
=
MRI
->
getDwarfRegNum
(
SP
::
I7
,
true
)
;
unsigned
regOutRA
=
MRI
->
getDwarfRegNum
(
SP
::
O7
,
true
)
;
CFIIndex
=
MMI
.
addFrameInst
(
MCCFIInstruction
::
createRegister
(
nullptr
,
regOutRA
,
regInRA
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
TargetOpcode
::
CFI_INSTRUCTION
)
)
.
addCFIIndex
(
CFIIndex
)
;
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Sparc
Sparc
Sparc
Sparc
"Shrink-wrapping not yet supported"
Sparc
Sparc
SP::SAVEri
SP::SAVErr
0
SP::ADDri
SP::ADDrr
Sparc
SP
SP::I6
SP::I7
SP::O7


<s> const TargetRegisterInfo * getRegisterInfo ( ) const override { return getSubtargetImpl ( ) -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool hasReservedCallFrame ( const MachineFunction & MF ) const override { return true ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> bool MipsPassConfig :: addInstSelector ( ) { PM . add ( createMipsISelDag ( getMipsTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static int ix86_avx_u128_mode_after ( int mode , rtx_insn * insn ) { rtx pat = PATTERN ( insn ) ; if ( vzeroupper_operation ( pat , VOIDmode ) || vzeroall_operation ( pat , VOIDmode ) ) return AVX_U128_CLEAN ; if ( CALL_P ( insn ) ) { bool avx_reg256_found = false ; note_stores ( pat , ix86_check_avx256_stores , & avx_reg256_found ) ; return avx_reg256_found ? AVX_U128_DIRTY : AVX_U128_CLEAN ; } return mode ; } </s>

Calculate mode of upper 128bit AVX registers after the insn .


<s> static void rl78_alloc_physical_registers_op1 ( rtx_insn * insn ) { if ( rtx_equal_p ( OP ( 0 ) , OP ( 1 ) ) ) { OP ( 0 ) = OP ( 1 ) = transcode_memory_rtx ( OP ( 1 ) , DE , insn ) ; } else { if ( MEM_P ( OP ( 0 ) ) && already_contains ( HL , XEXP ( OP ( 0 ) , 0 ) ) ) { OP ( 0 ) = transcode_memory_rtx ( OP ( 0 ) , HL , insn ) ; OP ( 1 ) = transcode_memory_rtx ( OP ( 1 ) , BC , insn ) ; } else { OP ( 0 ) = transcode_memory_rtx ( OP ( 0 ) , BC , insn ) ; OP ( 1 ) = transcode_memory_rtx ( OP ( 1 ) , HL , insn ) ; } } MAYBE_OK ( insn ) ; OP ( 0 ) = move_from_acc ( 0 , insn ) ; MAYBE_OK ( insn ) ; OP ( 1 ) = move_to_acc ( 1 , insn ) ; MUST_BE_OK ( insn ) ; } </s>

Devirtualize an insn of the form ( SET ( op ) ( unop ( op ) ) ) .


<s> void MipsSEFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; const MipsSEInstrInfo & TII = * static_cast < const MipsSEInstrInfo * > ( STI . getInstrInfo ( ) ) ; const MipsRegisterInfo & RegInfo = * static_cast < const MipsRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; unsigned SP = ABI . GetStackPtr ( ) ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned ZERO = ABI . GetNullPtr ( ) ; unsigned MOVE = ABI . GetGPRMoveOp ( ) ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( MOVE ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( MipsFI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = ABI . ArePtrs64bit ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = 0 ; J < 4 ; ++ J ) { TII . loadRegFromStackSlot ( MBB , I , ABI . GetEhDataReg ( J ) , MipsFI -> getEhDataRegFI ( J ) , RC , & RegInfo ) ; } } uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize , MBB , MBBI ) ; } </s>

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips 0 Mips Mips::GPR64RegClass Mips::GPR32RegClass 0 0 4 Mips


<s> void GCNPassConfig :: addPreEmitPass ( ) { addPass ( & PostRAHazardRecognizerID ) ; if ( EnableSIInsertWaitcntsPass ) addPass ( createSIInsertWaitcntsPass ( ) ) ; else addPass ( createSIInsertWaitsPass ( ) ) ; addPass ( createSIShrinkInstructionsPass ( ) ) ; addPass ( & SIInsertSkipsPassID ) ; addPass ( createSIMemoryLegalizerPass ( ) ) ; addPass ( createSIDebuggerInsertNopsPass ( ) ) ; addPass ( & BranchRelaxationPassID ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool aarch64_mask_and_shift_for_ubfiz_p ( machine_mode mode , rtx mask , rtx shft_amnt ) { return CONST_INT_P ( mask ) && CONST_INT_P ( shft_amnt ) && INTVAL ( shft_amnt ) < GET_MODE_BITSIZE ( mode ) && exact_log2 ( ( INTVAL ( mask ) >> INTVAL ( shft_amnt ) ) + 1 ) >= 0 && ( INTVAL ( mask ) & ( ( 1 << INTVAL ( shft_amnt ) ) - 1 ) ) == 0 ; } </s>

Return true if the mask and a shift amount from an RTX of the form ( x < < SHFT_AMNT ) & MASK are valid to combine into a UBFIZ instruction of mode MODE . See the * andim_ashift < mode > _bfiz pattern .


<s> void ARMPassConfig :: addPreEmitPass2 ( ) { addPass ( createARMFixCortexA57AES1742098Pass ( ) ) ; addPass ( createARMBranchTargetsPass ( ) ) ; addPass ( createARMConstantIslandPass ( ) ) ; addPass ( createARMLowOverheadLoopsPass ( ) ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) { addPass ( createCFGuardLongjmpPass ( ) ) ; addPass ( createEHContGuardCatchretPass ( ) ) ; } } </s>

Targets may add passes immediately before machine code is emitted in this callback .


<s> bool frv_can_eliminate ( const int from , const int to ) { return ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true ) ; } </s>

Worker function for TARGET_CAN_ELIMINATE .


<s>
bool
MCS51AsmParser
::
MatchAndEmitInstruction
(
SMLoc
Loc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MatchingInlineAsm
)
;
switch
(
MatchResult
)
{
case
Match_Success
:
return
emit
(
Inst
,
Loc
,
Out
)
;
case
Match_MissingFeature
:
return
missingFeature
(
Loc
,
ErrorInfo
)
;
case
Match_InvalidOperand
:
return
invalidOperand
(
Loc
,
Operands
,
ErrorInfo
)
;
case
Match_MnemonicFail
:
return
Error
(
Loc
,
"invalid instruction"
)
;
default
:
return
true
;
}
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> bool SITypeRewriter :: doInitialization ( Module & M ) { Mod = & M ; v16i8 = VectorType :: get ( Type :: getInt8Ty ( M . getContext ( ) ) , 16 ) ; v4i32 = VectorType :: get ( Type :: getInt32Ty ( M . getContext ( ) ) , 4 ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> bool mask_low_and_shift_p ( machine_mode mode , rtx mask , rtx shift , int maxlen ) { return IN_RANGE ( mask_low_and_shift_len ( mode , mask , shift ) , 1 , maxlen ) ; } </s>

Check if MASK and SHIFT are valid in mask-low-and-shift-left operation if MAXLEN is the maxium length of consecutive bits that can make up MASK . MODE is the mode of the operation . See mask_low_and_shift_len for the actual definition .


<s> bool isCheapToSpeculateCtlz ( ) const override { return true ; } </s>

Return true if it is cheap to speculate a call to intrinsic ctlz .


<s> void VideoCore4RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; int frameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; uint64_t stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ; int64_t spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( frameIndex ) ; unsigned reg = getFrameRegister ( MF ) ; int64_t offset = spOffset + ( int64_t ) stackSize ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( reg , false , false , true ) ; MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( offset ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> tree gimple_folder :: load_store_cookie ( tree type ) { return build_int_cst ( build_pointer_type ( type ) , TYPE_ALIGN ( type ) ) ; } </s>

Return the alignment and TBAA argument to an internal load or store function like IFN_MASK_LOAD or IFN_MASK_STORE , given that it accesses memory elements of type TYPE .


"Can't break virtual register dependencies."

Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum .


<s>
bool
ARMLowOverheadLoops
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
!
static_cast
<
const
ARMSubtarget
&
>
(
MF
.
getSubtarget
(
)
)
.
hasLOB
(
)
)
return
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM Loops on "
<<
MF
.
getName
(
)
<<
" ------------- \n"
)
;
auto
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
TII
=
static_cast
<
const
ARMBaseInstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
BBUtils
=
std
::
unique_ptr
<
ARMBasicBlockUtils
>
(
new
ARMBasicBlockUtils
(
MF
)
)
;
BBUtils
->
computeAllBlockSizes
(
)
;
BBUtils
->
adjustBBOffsetsAfter
(
&
MF
.
front
(
)
)
;
bool
Changed
=
false
;
for
(
auto
ML
:
MLI
)
{
if
(
!
ML
->
getParentLoop
(
)
)
Changed
|=
ProcessLoop
(
ML
)
;
}
Changed
|=
RevertNonLoops
(
MF
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

ARM
ARM
ARM
"ARM Loops on "
" ------------- \n"
ARM
ARM
ARM


<s> static int arc_check_release31a ( rtx_insn * pred , rtx_insn * succ ) { if ( ! pred || ! INSN_P ( pred ) || ! succ || ! INSN_P ( succ ) ) return 0 ; if ( ! JUMP_P ( pred ) && ! single_set ( pred ) ) return 0 ; if ( ! JUMP_P ( succ ) && ! single_set ( succ ) ) return 0 ; if ( TARGET_HS && ( arc_tune == ARC_TUNE_ARCHS4X_REL31A ) ) switch ( get_attr_type ( pred ) ) { case TYPE_STORE : switch ( get_attr_type ( succ ) ) { case TYPE_BRCC : case TYPE_BRCC_NO_DELAY_SLOT : case TYPE_LOOP_END : return 1 ; default : break ; } break ; case TYPE_BRCC : case TYPE_BRCC_NO_DELAY_SLOT : case TYPE_LOOP_END : if ( get_attr_type ( succ ) == TYPE_STORE ) return 1 ; break ; default : break ; } return 0 ; } </s>

When compiling for release 310a , insert a nop before any conditional jump .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> void ARMPassConfig :: addPreEmitPass2 ( ) { addPass ( createARMConstantIslandPass ( ) ) ; addPass ( createARMLowOverheadLoopsPass ( ) ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardLongjmpPass ( ) ) ; } </s>


<s> bool mayLoad ( ) const { return Load ; } </s>

Return true if this instruction could possibly read memory .


<s> void TPCAAWrapperPass :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesAll ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s>
unsigned
MipsMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
)
const
{
if
(
MO
.
isReg
(
)
)
{
unsigned
Reg
=
MO
.
getReg
(
)
;
unsigned
RegNo
=
getMipsRegisterNumbering
(
Reg
)
;
return
RegNo
;
}
else
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
else
if
(
MO
.
isFPImm
(
)
)
{
return
static_cast
<
unsigned
>
(
APFloat
(
MO
.
getFPImm
(
)
)
.
bitcastToAPInt
(
)
.
getHiBits
(
32
)
.
getLimitedValue
(
)
)
;
}
else
if
(
MO
.
isExpr
(
)
)
{
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
MCExpr
::
ExprKind
Kind
=
Expr
->
getKind
(
)
;
unsigned
Ret
=
0
;
if
(
Kind
==
MCExpr
::
Binary
)
{
const
MCBinaryExpr
*
BE
=
static_cast
<
const
MCBinaryExpr
*
>
(
Expr
)
;
Expr
=
BE
->
getLHS
(
)
;
Kind
=
Expr
->
getKind
(
)
;
const
MCConstantExpr
*
CE
=
dyn_cast
<
MCConstantExpr
>
(
BE
->
getRHS
(
)
)
;
assert
(
(
Kind
==
MCExpr
::
SymbolRef
)
&&
CE
&&
"Binary expression must be sym+const."
)
;
Ret
=
CE
->
getValue
(
)
;
}
if
(
Kind
==
MCExpr
::
SymbolRef
)
{
Mips
::
Fixups
FixupKind
;
switch
(
cast
<
MCSymbolRefExpr
>
(
Expr
)
->
getKind
(
)
)
{
case
MCSymbolRefExpr
::
VK_Mips_GPREL
:
FixupKind
=
Mips
::
fixup_Mips_GPREL16
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_GOT_CALL
:
FixupKind
=
Mips
::
fixup_Mips_CALL16
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_GOT
:
FixupKind
=
Mips
::
fixup_Mips_GOT16
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_ABS_HI
:
FixupKind
=
Mips
::
fixup_Mips_HI16
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_ABS_LO
:
FixupKind
=
Mips
::
fixup_Mips_LO16
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_TLSGD
:
FixupKind
=
Mips
::
fixup_Mips_TLSGD
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_GOTTPREL
:
FixupKind
=
Mips
::
fixup_Mips_GOTTPREL
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_TPREL_HI
:
FixupKind
=
Mips
::
fixup_Mips_TPREL_HI
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_TPREL_LO
:
FixupKind
=
Mips
::
fixup_Mips_TPREL_LO
;
break
;
default
:
return
Ret
;
}
Fixups
.
push_back
(
MCFixup
::
Create
(
0
,
Expr
,
MCFixupKind
(
FixupKind
)
)
)
;
}
return
Ret
;
}
llvm_unreachable
(
"Unable to encode MCOperand!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> Register CSKYTargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) const { return CSKY :: R1 ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .


<s> bool AArch64InstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Cond , unsigned DstReg , unsigned TrueReg , unsigned FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( ! RI . getCommonSubClass ( RC , MRI . getRegClass ( DstReg ) ) ) return false ; unsigned ExtraCondLat = Cond . size ( ) != 1 ; if ( AArch64 :: GPR64allRegClass . hasSubClassEq ( RC ) || AArch64 :: GPR32allRegClass . hasSubClassEq ( RC ) ) { CondCycles = 1 + ExtraCondLat ; TrueCycles = FalseCycles = 1 ; if ( canFoldIntoCSel ( MRI , TrueReg ) ) TrueCycles = 0 ; else if ( canFoldIntoCSel ( MRI , FalseReg ) ) FalseCycles = 0 ; return true ; } if ( AArch64 :: FPR64RegClass . hasSubClassEq ( RC ) || AArch64 :: FPR32RegClass . hasSubClassEq ( RC ) ) { CondCycles = 5 + ExtraCondLat ; TrueCycles = FalseCycles = 2 ; return true ; } return false ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> void ARMInstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , const MachineInstr * Orig ) const { DebugLoc dl = Orig -> getDebugLoc ( ) ; if ( Orig -> getOpcode ( ) == ARM :: MOVi2pieces ) { RI . emitLoadConstPool ( MBB , I , DestReg , Orig -> getOperand ( 1 ) . getImm ( ) , Orig -> getOperand ( 2 ) . getImm ( ) , Orig -> getOperand ( 3 ) . getReg ( ) , this , false , dl ) ; return ; } MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( Orig ) ; MI -> getOperand ( 0 ) . setReg ( DestReg ) ; MBB . insert ( I , MI ) ; } </s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s> bool MOSFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MFI . isFrameAddressTaken ( ) || MFI . hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void ix86_expand_copysign ( rtx operands [ ] ) { machine_mode mode , vmode ; rtx dest , vdest , op0 , op1 , mask , op2 , op3 ; mode = GET_MODE ( operands [ 0 ] ) ; if ( mode == HFmode ) vmode = V8HFmode ; else if ( mode == SFmode ) vmode = V4SFmode ; else if ( mode == DFmode ) vmode = V2DFmode ; else if ( mode == TFmode ) vmode = mode ; else gcc_unreachable ( ) ; if ( rtx_equal_p ( operands [ 1 ] , operands [ 2 ] ) ) { emit_move_insn ( operands [ 0 ] , operands [ 1 ] ) ; return ; } dest = operands [ 0 ] ; vdest = lowpart_subreg ( vmode , dest , mode ) ; if ( vdest == NULL_RTX ) vdest = gen_reg_rtx ( vmode ) ; else dest = NULL_RTX ; op1 = lowpart_subreg ( vmode , force_reg ( mode , operands [ 2 ] ) , mode ) ; mask = ix86_build_signbit_mask ( vmode , 0 , 0 ) ; if ( CONST_DOUBLE_P ( operands [ 1 ] ) ) { op0 = simplify_unary_operation ( ABS , mode , operands [ 1 ] , mode ) ; if ( op0 == CONST0_RTX ( mode ) ) { emit_move_insn ( vdest , gen_rtx_AND ( vmode , mask , op1 ) ) ; if ( dest ) emit_move_insn ( dest , lowpart_subreg ( mode , vdest , vmode ) ) ; return ; } if ( GET_MODE_SIZE ( mode ) < 16 ) op0 = ix86_build_const_vector ( vmode , false , op0 ) ; op0 = force_reg ( vmode , op0 ) ; } else op0 = lowpart_subreg ( vmode , force_reg ( mode , operands [ 1 ] ) , mode ) ; op2 = gen_reg_rtx ( vmode ) ; op3 = gen_reg_rtx ( vmode ) ; emit_move_insn ( op2 , gen_rtx_AND ( vmode , gen_rtx_NOT ( vmode , mask ) , op0 ) ) ; emit_move_insn ( op3 , gen_rtx_AND ( vmode , mask , op1 ) ) ; emit_move_insn ( vdest , gen_rtx_IOR ( vmode , op2 , op3 ) ) ; if ( dest ) emit_move_insn ( dest , lowpart_subreg ( mode , vdest , vmode ) ) ; } </s>

Expand a copysign operation . Special case operand 0 being a constant .


<s> bool RISCVInstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( TargetInstrInfo :: isSchedulingBoundary ( MI , MBB , MF ) ) { return true ; } switch ( MI . getOpcode ( ) ) { case RISCV :: LOOP0setup : case RISCV :: LOOP1setup : case RISCV :: LOOP0setupi : case RISCV :: LOOP1setupi : return true ; default : ; } return false ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> const uint32_t * ARMBaseRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; if ( STI . isTargetNaCl ( ) ) return CSR_NaCl_RegMask ; if ( CC == CallingConv :: GHC ) return CSR_NoRegs_RegMask ; return STI . isTargetDarwin ( ) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void AArch64PreLegalizerCombiner :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < TargetPassConfig > ( ) ; AU . setPreservesCFG ( ) ; getSelectionDAGFallbackAnalysisUsage ( AU ) ; AU . addRequired < GISelKnownBitsAnalysis > ( ) ; AU . addPreserved < GISelKnownBitsAnalysis > ( ) ; if ( ! IsOptNone ) { AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; } MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> int arm_coproc_mem_operand ( rtx op , bool wb ) { return arm_coproc_mem_operand_wb ( op , wb ? 2 : 1 ) ; } </s>

Return TRUE if OP is a valid coprocessor memory address pattern . WB if true if writeback address modes are allowed .


<s> static tree aarch64_int_or_fp_type ( machine_mode mode , enum aarch64_type_qualifiers qualifiers ) { ? unsigned_int ## M ## _type_node : int ## M ## _type_node ) ; switch ( mode ) { case E_QImode : return QUAL_TYPE ( QI ) ; case E_HImode : return QUAL_TYPE ( HI ) ; case E_SImode : return QUAL_TYPE ( SI ) ; case E_DImode : return QUAL_TYPE ( DI ) ; case E_TImode : return QUAL_TYPE ( TI ) ; case E_OImode : return aarch64_simd_intOI_type_node ; case E_CImode : return aarch64_simd_intCI_type_node ; case E_XImode : return aarch64_simd_intXI_type_node ; case E_HFmode : return aarch64_fp16_type_node ; case E_SFmode : return float_type_node ; case E_DFmode : return double_type_node ; case E_BFmode : return bfloat16_type_node ; default : gcc_unreachable ( ) ; } } </s>

Helper function for aarch64_simd_builtin_type .


<s> unsigned internalKnownBits ( ) const { return Unalign ? Unalign : KnownBits ; } </s>

Compute the number of known offset bits internally to this block .


<s> const Triple & getTargetTriple ( ) const { return TargetTriple ; } </s>

Get the target triple which is a string describing the target host .


<s> unsigned X86FrameLowering :: getInitialCFARegister ( const MachineFunction & MF ) const { return TRI -> getDwarfRegNum ( StackPtr , true ) ; } </s>


<s> static rtx_insn * mips_call_tls_get_addr ( rtx sym , enum mips_symbol_type type , rtx v0 ) { rtx loc , a0 ; rtx_insn * insn ; a0 = gen_rtx_REG ( Pmode , GP_ARG_FIRST ) ; if ( ! mips_tls_symbol ) mips_tls_symbol = init_one_libfunc ( "__tls_get_addr" ) ; loc = mips_unspec_address ( sym , type ) ; start_sequence ( ) ; emit_insn ( gen_rtx_SET ( a0 , gen_rtx_LO_SUM ( Pmode , pic_offset_table_rtx , loc ) ) ) ; insn = mips_expand_call ( MIPS_CALL_NORMAL , v0 , mips_tls_symbol , const0_rtx , NULL_RTX , false ) ; RTL_CONST_CALL_P ( insn ) = 1 ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , a0 ) ; insn = get_insns ( ) ; end_sequence ( ) ; return insn ; } </s>

Return an instruction sequence that calls __tls_get_addr . SYM is the TLS symbol we are referencing and TYPE is the symbol type to use ( either global dynamic or local dynamic ) . V0 is an RTX for the return value location .


<s> bool mergeStoresAfterLegalization ( EVT ) const override { return false ; } </s>

Do not merge vector stores after legalization because that may conflict with x86-specific store splitting optimizations .


<s>
bool
FISCAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNum
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
int
Offset
=
0
;
if
(
ExtraCode
)
return
true
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNum
)
;
assert
(
MO
.
isReg
(
)
&&
"unexpected inline asm memory operand"
)
;
O
<<
"["
<<
FISCInstPrinter
::
getRegisterName
(
MO
.
getReg
(
)
)
<<
", "
<<
Offset
<<
"]"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .

FISC
FISC
0
"unexpected inline asm memory operand"
"["
FISC
", "
"]"


<s>
static
reg_class_t
m32c_preferred_reload_class
(
rtx
x
,
reg_class_t
rclass
)
{
reg_class_t
newclass
=
rclass
;
fprintf
(
stderr
,
"\npreferred_reload_class for %s is "
,
class_names
[
rclass
]
)
;
if
(
rclass
==
NO_REGS
)
rclass
=
GET_MODE
(
x
)
==
QImode
HL_REGS
:
R03_REGS
;
if
(
reg_classes_intersect_p
(
rclass
,
CR_REGS
)
)
{
switch
(
GET_MODE
(
x
)
)
{
case
QImode
:
newclass
=
HL_REGS
;
break
;
default
:
break
;
}
}
else
if
(
newclass
==
QI_REGS
&&
GET_MODE_SIZE
(
GET_MODE
(
x
)
)
>
2
)
newclass
=
SI_REGS
;
else
if
(
GET_MODE_SIZE
(
GET_MODE
(
x
)
)
>
4
&&
!
reg_class_subset_p
(
R03_REGS
,
rclass
)
)
newclass
=
DI_REGS
;
rclass
=
reduce_class
(
rclass
,
newclass
,
rclass
)
;
if
(
GET_MODE
(
x
)
==
QImode
)
rclass
=
reduce_class
(
rclass
,
HL_REGS
,
rclass
)
;
fprintf
(
stderr
,
"%s\n"
,
class_names
[
rclass
]
)
;
debug_rtx
(
x
)
;
if
(
GET_CODE
(
x
)
==
MEM
&&
GET_CODE
(
XEXP
(
x
,
0
)
)
==
PLUS
&&
GET_CODE
(
XEXP
(
XEXP
(
x
,
0
)
,
0
)
)
==
PLUS
)
fprintf
(
stderr
,
"Glorm!\n"
)
;
return
rclass
;
}
</s>

Implements PREFERRED_RELOAD_CLASS . In general , prefer general registers of the appropriate size .


<s> unsigned ARMTargetLowering :: getABIAlignmentForCallingConv ( Type * ArgTy , DataLayout DL ) const { if ( ! ArgTy -> isVectorTy ( ) ) return DL . getABITypeAlignment ( ArgTy ) ; return std :: min ( DL . getABITypeAlignment ( ArgTy ) , ( unsigned ) DL . getStackAlignment ( ) . value ( ) ) ; } </s>

Return the correct alignment for the current calling convention .


<s> const TargetRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static bool alpha_vector_mode_supported_p ( machine_mode mode ) { return mode == V8QImode || mode == V4HImode || mode == V2SImode ; } </s>

Alpha implements a couple of integer vector mode operations when TARGET_MAX is enabled . We do not check TARGET_MAX here , however , which allows the vectorizer to operate on e.g . move instructions , or when expand_vector_operations can do something useful .


<s> bool X86FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) && ! MF . getInfo < X86MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> ConstantPool * AssemblerConstantPools :: getConstantPool ( const MCSection * Section ) { ConstantPoolMapTy :: iterator CP = ConstantPools . find ( Section ) ; if ( CP == ConstantPools . end ( ) ) return nullptr ; return & CP -> second ; } </s>

Return a pseudo source value referencing the constant pool .


<s> TargetLowering :: AtomicExpansionKind X86TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { auto PTy = cast < PointerType > ( LI -> getPointerOperand ( ) -> getType ( ) ) ; return needsCmpXchgNb ( PTy -> getElementType ( ) ) ? AtomicExpansionKind :: CmpXChg : AtomicExpansionKind :: None ; } </s>

Returns how the given ( atomic ) load should be expanded by the IR-level AtomicExpand pass .


<s> unsigned SIInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const MCInstrDesc & Desc = getMCOpcodeFromPseudo ( Opc ) ; unsigned DescSize = Desc . getSize ( ) ; if ( isFixedSize ( MI ) ) { unsigned Size = DescSize ; if ( MI . isBranch ( ) && ST . hasOffset3fBug ( ) ) Size += 4 ; return Size ; } if ( isVALU ( MI ) || isSALU ( MI ) ) { if ( isDPP ( MI ) ) return DescSize ; bool HasLiteral = false ; for ( int I = 0 , E = MI . getNumExplicitOperands ( ) ; I != E ; ++ I ) { const MachineOperand & Op = MI . getOperand ( I ) ; const MCOperandInfo & OpInfo = Desc . OpInfo [ I ] ; if ( isLiteralConstantLike ( Op , OpInfo ) ) { HasLiteral = true ; break ; } } return HasLiteral ? DescSize + 4 : DescSize ; } if ( isMIMG ( MI ) ) { int VAddr0Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: vaddr0 ) ; if ( VAddr0Idx < 0 ) return 8 ; int RSrcIdx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: srsrc ) ; return 8 + 4 * ( ( RSrcIdx - VAddr0Idx + 2 ) / 4 ) ; } switch ( Opc ) { case TargetOpcode :: BUNDLE : return getInstBundleSize ( MI ) ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) , & ST ) ; } default : if ( MI . isMetaInstruction ( ) ) return 0 ; return DescSize ; } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> void s390_reload_symref_address ( rtx reg , rtx mem , rtx scratch , bool tomem ) { if ( CONST_INT_P ( mem ) || GET_CODE ( mem ) == CONST_DOUBLE || GET_CODE ( mem ) == CONST_WIDE_INT || GET_CODE ( mem ) == CONST_VECTOR || GET_CODE ( mem ) == CONST ) mem = force_const_mem ( GET_MODE ( reg ) , mem ) ; gcc_assert ( MEM_P ( mem ) ) ; if ( ! tomem && REGNO ( reg ) < FIRST_PSEUDO_REGISTER && REGNO_REG_CLASS ( REGNO ( reg ) ) == ADDR_REGS && GET_MODE ( reg ) == GET_MODE ( scratch ) ) scratch = reg ; s390_reload_larl_operand ( scratch , XEXP ( mem , 0 ) , scratch ) ; if ( tomem ) emit_move_insn ( replace_equiv_address ( mem , scratch ) , reg ) ; else emit_move_insn ( reg , replace_equiv_address ( mem , scratch ) ) ; } </s>

Generate what is necessary to move between REG and MEM using SCRATCH . The direction is given by TOMEM .


<s> bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , BranchProbability Probability ) const override { return true ; } </s>

Return true if it 's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion .


<s> bool R600InstrInfo :: fitsReadPortLimitations ( const std :: vector < MachineInstr * > & IG , const DenseMap < unsigned , unsigned > & PV , std :: vector < BankSwizzle > & ValidSwizzle , bool isLastAluTrans ) const { std :: vector < std :: vector < std :: pair < int , unsigned > > > IGSrcs ; ValidSwizzle . clear ( ) ; unsigned ConstCount ; BankSwizzle TransBS = ALU_VEC_012_SCL_210 ; for ( unsigned i = 0 , e = IG . size ( ) ; i < e ; ++ i ) { IGSrcs . push_back ( ExtractSrcs ( IG [ i ] , PV , ConstCount ) ) ; unsigned Op = getOperandIdx ( IG [ i ] -> getOpcode ( ) , AMDGPU :: OpName :: bank_swizzle ) ; ValidSwizzle . push_back ( ( R600InstrInfo :: BankSwizzle ) IG [ i ] -> getOperand ( Op ) . getImm ( ) ) ; } std :: vector < std :: pair < int , unsigned > > TransOps ; if ( ! isLastAluTrans ) return FindSwizzleForVectorSlot ( IGSrcs , ValidSwizzle , TransOps , TransBS ) ; TransOps = std :: move ( IGSrcs . back ( ) ) ; IGSrcs . pop_back ( ) ; ValidSwizzle . pop_back ( ) ; static const R600InstrInfo :: BankSwizzle TransSwz [ ] = { ALU_VEC_012_SCL_210 , ALU_VEC_021_SCL_122 , ALU_VEC_120_SCL_212 , ALU_VEC_102_SCL_221 } ; for ( unsigned i = 0 ; i < 4 ; i ++ ) { TransBS = TransSwz [ i ] ; if ( ! isConstCompatible ( TransBS , TransOps , ConstCount ) ) continue ; bool Result = FindSwizzleForVectorSlot ( IGSrcs , ValidSwizzle , TransOps , TransBS ) ; if ( Result ) { ValidSwizzle . push_back ( TransBS ) ; return true ; } } return false ; } </s>

Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first ( in lexical order ) BankSwizzle affectation starting from the one already provided in the Instruction Group MIs that fits Read Port limitations in BS if available .


<s> bool GCNScheduleDAGMILive :: isTriviallyReMaterializable ( const MachineInstr & MI , AAResults * AA ) { if ( ! TII -> isTriviallyReMaterializable ( MI , AA ) ) return false ; for ( const MachineOperand & MO : MI . operands ( ) ) if ( MO . isReg ( ) && MO . isUse ( ) && MO . getReg ( ) . isVirtual ( ) ) return false ; return true ; } </s>

Return true if the instruction is trivially rematerializable , meaning it has no side effects and requires no operands that are n't always available .


<s> void avr_expand_prologue ( void ) { HARD_REG_SET set ; HOST_WIDE_INT size ; size = get_frame_size ( ) + avr_outgoing_args_size ( ) ; cfun -> machine -> stack_usage = 0 ; if ( cfun -> machine -> is_naked ) { return ; } avr_regs_to_save ( & set ) ; if ( cfun -> machine -> is_interrupt || cfun -> machine -> is_signal ) { int treg = AVR_TMP_REGNO ; if ( cfun -> machine -> is_interrupt ) emit_insn ( gen_enable_interrupt ( ) ) ; if ( cfun -> machine -> gasisr . maybe ) { cfun -> machine -> gasisr . yes = 1 ; treg = avr_hregs_split_reg ( & set ) ; if ( treg < 0 ) treg = AVR_TMP_REGNO ; cfun -> machine -> gasisr . regno = treg ; cfun -> machine -> stack_usage += 3 + ( treg != AVR_TMP_REGNO ) ; emit_insn ( gen_gasisr ( GEN_INT ( GASISR_Prologue ) , GEN_INT ( treg ) ) ) ; } else { emit_push_byte ( AVR_ZERO_REGNO , true ) ; emit_push_byte ( AVR_TMP_REGNO , true ) ; emit_push_sfr ( sreg_rtx , false , false , AVR_TMP_REGNO ) ; emit_move_insn ( zero_reg_rtx , const0_rtx ) ; emit_use ( zero_reg_rtx ) ; } if ( AVR_HAVE_RAMPD ) emit_push_sfr ( rampd_rtx , false , true , treg ) ; if ( AVR_HAVE_RAMPX && TEST_HARD_REG_BIT ( set , REG_X ) && TEST_HARD_REG_BIT ( set , REG_X + 1 ) ) { emit_push_sfr ( rampx_rtx , false , true , treg ) ; } if ( AVR_HAVE_RAMPY && ( frame_pointer_needed || ( TEST_HARD_REG_BIT ( set , REG_Y ) && TEST_HARD_REG_BIT ( set , REG_Y + 1 ) ) ) ) { emit_push_sfr ( rampy_rtx , false , true , treg ) ; } if ( AVR_HAVE_RAMPZ && TEST_HARD_REG_BIT ( set , REG_Z ) && TEST_HARD_REG_BIT ( set , REG_Z + 1 ) ) { emit_push_sfr ( rampz_rtx , false , AVR_HAVE_RAMPD , treg ) ; } } avr_prologue_setup_frame ( size , set ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = cfun -> machine -> stack_usage + INCOMING_FRAME_SP_OFFSET ; } </s>


<s>
bool
SIRegisterInfo
::
eliminateSGPRToVGPRSpillFrameIndex
(
MachineBasicBlock
::
iterator
MI
,
int
FI
,
RegScavenger
*
RS
,
LiveIntervals
*
LIS
)
const
{
bool
NeedsCFI
=
false
;
switch
(
MI
->
getOpcode
(
)
)
{
case
AMDGPU
::
SI_SPILL_S1024_CFI_SAVE
:
case
AMDGPU
::
SI_SPILL_S512_CFI_SAVE
:
case
AMDGPU
::
SI_SPILL_S256_CFI_SAVE
:
case
AMDGPU
::
SI_SPILL_S224_CFI_SAVE
:
case
AMDGPU
::
SI_SPILL_S192_CFI_SAVE
:
case
AMDGPU
::
SI_SPILL_S160_CFI_SAVE
:
case
AMDGPU
::
SI_SPILL_S128_CFI_SAVE
:
case
AMDGPU
::
SI_SPILL_S96_CFI_SAVE
:
case
AMDGPU
::
SI_SPILL_S64_CFI_SAVE
:
case
AMDGPU
::
SI_SPILL_S32_CFI_SAVE
:
NeedsCFI
=
true
;
LLVM_FALLTHROUGH
;
case
AMDGPU
::
SI_SPILL_S1024_SAVE
:
case
AMDGPU
::
SI_SPILL_S512_SAVE
:
case
AMDGPU
::
SI_SPILL_S256_SAVE
:
case
AMDGPU
::
SI_SPILL_S224_SAVE
:
case
AMDGPU
::
SI_SPILL_S192_SAVE
:
case
AMDGPU
::
SI_SPILL_S160_SAVE
:
case
AMDGPU
::
SI_SPILL_S128_SAVE
:
case
AMDGPU
::
SI_SPILL_S96_SAVE
:
case
AMDGPU
::
SI_SPILL_S64_SAVE
:
case
AMDGPU
::
SI_SPILL_S32_SAVE
:
return
spillSGPR
(
MI
,
FI
,
RS
,
LIS
,
true
,
NeedsCFI
)
;
case
AMDGPU
::
SI_SPILL_S1024_RESTORE
:
case
AMDGPU
::
SI_SPILL_S512_RESTORE
:
case
AMDGPU
::
SI_SPILL_S256_RESTORE
:
case
AMDGPU
::
SI_SPILL_S224_RESTORE
:
case
AMDGPU
::
SI_SPILL_S192_RESTORE
:
case
AMDGPU
::
SI_SPILL_S160_RESTORE
:
case
AMDGPU
::
SI_SPILL_S128_RESTORE
:
case
AMDGPU
::
SI_SPILL_S96_RESTORE
:
case
AMDGPU
::
SI_SPILL_S64_RESTORE
:
case
AMDGPU
::
SI_SPILL_S32_RESTORE
:
return
restoreSGPR
(
MI
,
FI
,
RS
,
LIS
,
true
)
;
default
:
llvm_unreachable
(
"not an SGPR spill instruction"
)
;
}
}
</s>


<s> bool aarch64_sve_ld1r_operand_p ( rtx op ) { struct aarch64_address_info addr ; scalar_mode mode ; return ( MEM_P ( op ) && is_a < scalar_mode > ( GET_MODE ( op ) , & mode ) && aarch64_classify_address ( & addr , XEXP ( op , 0 ) , mode , false ) && addr . type == ADDRESS_REG_IMM && offset_6bit_unsigned_scaled_p ( mode , addr . const_offset ) ) ; } </s>

Return true if OP is a valid MEM operand for an SVE LD1R instruction .


<s> bool NVPTXTTIImpl :: isSourceOfDivergence ( const Value * V ) { if ( const Argument * Arg = dyn_cast < Argument > ( V ) ) return ! isKernelFunction ( * Arg -> getParent ( ) ) ; if ( const Instruction * I = dyn_cast < Instruction > ( V ) ) { if ( const LoadInst * LI = dyn_cast < LoadInst > ( I ) ) { unsigned AS = LI -> getPointerAddressSpace ( ) ; return AS == ADDRESS_SPACE_GENERIC || AS == ADDRESS_SPACE_LOCAL ; } if ( I -> isAtomic ( ) ) return true ; if ( const IntrinsicInst * II = dyn_cast < IntrinsicInst > ( I ) ) { if ( readsThreadIndex ( II ) || readsLaneId ( II ) ) return true ; if ( isNVVMAtomic ( II ) ) return true ; } if ( isa < CallInst > ( I ) ) return true ; } return false ; } </s>

Returns whether V is a source of divergence .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequiredID ( MachineDominatorsID ) ; AU . addRequiredID ( MachineLoopInfoID ) ; AU . addPreserved < SlotIndexes > ( ) ; AU . addPreserved < LiveIntervals > ( ) ; AU . addPreservedID ( LiveVariablesID ) ; AU . addPreservedID ( MachineLoopInfoID ) ; AU . addPreservedID ( MachineDominatorsID ) ; AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void R600TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { switch ( N -> getOpcode ( ) ) { default : AMDGPUTargetLowering :: ReplaceNodeResults ( N , Results , DAG ) ; return ; case ISD :: FP_TO_UINT : if ( N -> getValueType ( 0 ) == MVT :: i1 ) { Results . push_back ( LowerFPTOUINT ( N -> getOperand ( 0 ) , DAG ) ) ; return ; } case ISD :: FP_TO_SINT : { SDValue Result ; if ( expandFP_TO_SINT ( N , Result , DAG ) ) Results . push_back ( Result ) ; return ; } case ISD :: SDIVREM : { SDValue Op = SDValue ( N , 1 ) ; SDValue RES = LowerSDIVREM ( Op , DAG ) ; Results . push_back ( RES ) ; Results . push_back ( RES . getValue ( 1 ) ) ; break ; } case ISD :: UDIVREM : { SDValue Op = SDValue ( N , 0 ) ; LowerUDIVREM64 ( Op , DAG , Results ) ; break ; } } } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s>
void
relaxInstruction
(
const
MCInst
&
Inst
,
MCInst
&
Res
)
const
override
{
llvm_unreachable
(
"relaxInstruction() unimplemented"
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> unsigned SIInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const MCInstrDesc & Desc = getMCOpcodeFromPseudo ( Opc ) ; unsigned DescSize = Desc . getSize ( ) ; if ( isFixedSize ( MI ) ) { unsigned Size = DescSize ; if ( MI . isBranch ( ) && ST . hasOffset3fBug ( ) ) Size += 4 ; return Size ; } if ( isVALU ( MI ) || isSALU ( MI ) ) { int Src0Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src0 ) ; if ( Src0Idx == - 1 ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src0Idx ) , Desc . OpInfo [ Src0Idx ] ) ) return isVOP3 ( MI ) ? 12 : ( DescSize + 4 ) ; int Src1Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src1 ) ; if ( Src1Idx == - 1 ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src1Idx ) , Desc . OpInfo [ Src1Idx ] ) ) return isVOP3 ( MI ) ? 12 : ( DescSize + 4 ) ; int Src2Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src2 ) ; if ( Src2Idx == - 1 ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src2Idx ) , Desc . OpInfo [ Src2Idx ] ) ) return isVOP3 ( MI ) ? 12 : ( DescSize + 4 ) ; return DescSize ; } if ( isMIMG ( MI ) ) { int VAddr0Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: vaddr0 ) ; if ( VAddr0Idx < 0 ) return 8 ; int RSrcIdx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: srsrc ) ; return 8 + 4 * ( ( RSrcIdx - VAddr0Idx + 2 ) / 4 ) ; } switch ( Opc ) { case TargetOpcode :: BUNDLE : return getInstBundleSize ( MI ) ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) , & ST ) ; } default : if ( MI . isMetaInstruction ( ) ) return 0 ; return DescSize ; } } </s>


<s> const TargetRegisterClass * SIInstrInfo :: getOpRegClass ( const MachineInstr & MI , unsigned OpNo ) const { const MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const MCInstrDesc & Desc = get ( MI . getOpcode ( ) ) ; if ( MI . isVariadic ( ) || OpNo >= Desc . getNumOperands ( ) || Desc . OpInfo [ OpNo ] . RegClass == - 1 ) { Register Reg = MI . getOperand ( OpNo ) . getReg ( ) ; if ( Register :: isVirtualRegister ( Reg ) ) return MRI . getRegClass ( Reg ) ; return RI . getPhysRegClass ( Reg ) ; } unsigned RCID = Desc . OpInfo [ OpNo ] . RegClass ; return RI . getRegClass ( RCID ) ; } </s>

Return the correct register class for OpNo .


<s> StringRef getName ( ) const { return Name ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> void NVPTXAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; if ( static_cast < NVPTXTargetMachine & > ( TM ) . getDrvInterface ( ) == NVPTX :: CUDA ) emitLineNumberAsDotLoc ( * MI ) ; MCInst Inst ; lowerToMCInst ( MI , Inst ) ; EmitToStreamer ( * OutStreamer , Inst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createTeeRISCELFObjectWriter ( OS , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


"%<-mindirect-branch=%s%> and %<-mcmodel=large%> are not "

"%<-mindirect-branch%> and %<-fcf-protection%> are not "

"%<-mfunction-return=%s%> and %<-mcmodel=large%> are not "

"%<-mfunction-return%> and %<-fcf-protection%> are not "

Set the indirect_branch_type field from the function FNDECL .


<s>
unsigned
SIInstrInfo
::
getInstSizeInBytes
(
const
MachineInstr
&
MI
)
const
{
unsigned
Opc
=
MI
.
getOpcode
(
)
;
const
MCInstrDesc
&
Desc
=
getMCOpcodeFromPseudo
(
Opc
)
;
unsigned
DescSize
=
Desc
.
getSize
(
)
;
if
(
DescSize
==
8
||
DescSize
==
4
)
return
DescSize
;
assert
(
DescSize
==
0
)
;
if
(
isVALU
(
MI
)
||
isSALU
(
MI
)
)
{
int
Src0Idx
=
AMDGPU
::
getNamedOperandIdx
(
Opc
,
AMDGPU
::
OpName
::
src0
)
;
if
(
Src0Idx
==
1
)
return
4
;
if
(
isLiteralConstant
(
MI
.
getOperand
(
Src0Idx
)
,
getOpSize
(
MI
,
Src0Idx
)
)
)
return
8
;
int
Src1Idx
=
AMDGPU
::
getNamedOperandIdx
(
Opc
,
AMDGPU
::
OpName
::
src1
)
;
if
(
Src1Idx
==
1
)
return
4
;
if
(
isLiteralConstant
(
MI
.
getOperand
(
Src1Idx
)
,
getOpSize
(
MI
,
Src1Idx
)
)
)
return
8
;
return
4
;
}
switch
(
Opc
)
{
case
TargetOpcode
::
IMPLICIT_DEF
:
case
TargetOpcode
::
KILL
:
case
TargetOpcode
::
DBG_VALUE
:
case
TargetOpcode
::
BUNDLE
:
case
TargetOpcode
::
EH_LABEL
:
return
0
;
case
TargetOpcode
::
INLINEASM
:
{
const
MachineFunction
*
MF
=
MI
.
getParent
(
)
->
getParent
(
)
;
const
char
*
AsmStr
=
MI
.
getOperand
(
0
)
.
getSymbolName
(
)
;
return
getInlineAsmLength
(
AsmStr
,
*
MF
->
getTarget
(
)
.
getMCAsmInfo
(
)
)
;
}
default
:
llvm_unreachable
(
"unable to find instruction size"
)
;
}
}
</s>


<s>
bool
TVMInstrInfo
::
PredicateInstruction
(
MachineInstr
&
MI
,
ArrayRef
<
MachineOperand
>
Pred
)
const
{
if
(
MI
.
getOpcode
(
)
!=
TVM
::
THROW
||
Pred
.
size
(
)
!=
2
)
{
return
false
;
}
assert
(
isPredicable
(
MI
)
&&
"Expected predicable instruction"
)
;
assert
(
Pred
[
0
]
.
isImm
(
)
&&
"Expected immediate for 'Inverted'"
)
;
assert
(
Pred
[
1
]
.
isReg
(
)
&&
"Expected register for 'Cond'"
)
;
bool
Inverted
=
Pred
[
0
]
.
getImm
(
)
;
auto
ErrCode
=
MI
.
getOperand
(
0
)
;
MI
.
RemoveOperand
(
0
)
;
MI
.
setDesc
(
get
(
Inverted
TVM
::
THROWIFNOT
:
TVM
::
THROWIF
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
add
(
Pred
[
1
]
)
.
add
(
ErrCode
)
;
return
true
;
}
</s>

Convert the instruction into a predicated instruction .


<s> static tree avr_build_builtin_va_list ( void ) { avr_adjust_type_node ( & ta_type_node , TAmode , 0 ) ; avr_adjust_type_node ( & uta_type_node , UTAmode , 0 ) ; avr_adjust_type_node ( & sat_ta_type_node , TAmode , 1 ) ; avr_adjust_type_node ( & sat_uta_type_node , UTAmode , 1 ) ; unsigned_long_long_accum_type_node = uta_type_node ; long_long_accum_type_node = ta_type_node ; sat_unsigned_long_long_accum_type_node = sat_uta_type_node ; sat_long_long_accum_type_node = sat_ta_type_node ; return std_build_builtin_va_list ( ) ; } </s>

Implement ` TARGET_BUILD_BUILTIN_VA_LIST ' .


<s> static inline bool offset_9bit_signed_unscaled_p ( machine_mode mode ATTRIBUTE_UNUSED , HOST_WIDE_INT offset ) { return offset >= - 256 && offset < 256 ; } </s>

Return true if OFFSET is a signed 9-bit value .


<s> unsigned PPCFrameLowering :: determineFrameLayout ( MachineFunction & MF , bool UpdateMF , bool UseEstimate ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = UseEstimate ? MFI -> estimateStackSize ( MF ) : MFI -> getStackSize ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - 1 ; const PPCRegisterInfo * RegInfo = static_cast < const PPCRegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; bool DisableRedZone = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoRedZone ) ; if ( ! DisableRedZone && ( Subtarget . isPPC64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == 0 ) && FrameSize <= 224 && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! RegInfo -> hasBasePointer ( MF ) ) { if ( UpdateMF ) MFI -> setStackSize ( 0 ) ; return 0 ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( Subtarget . isPPC64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setStackSize ( FrameSize ) ; return FrameSize ; } </s>

Determine the frame layout but do not update the machine function .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
Mips
::
NumTargetFixupKinds
]
=
{
{
"fixup_Mips_16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_32"
,
0
,
32
,
0
}
,
{
"fixup_Mips_REL32"
,
0
,
32
,
0
}
,
{
"fixup_Mips_26"
,
0
,
26
,
0
}
,
{
"fixup_Mips_HI16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_LO16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GPREL16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_LITERAL"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GOT_Global"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GOT_Local"
,
0
,
16
,
0
}
,
{
"fixup_Mips_PC16"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_Mips_CALL16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GPREL32"
,
0
,
32
,
0
}
,
{
"fixup_Mips_SHIFT5"
,
6
,
5
,
0
}
,
{
"fixup_Mips_SHIFT6"
,
6
,
5
,
0
}
,
{
"fixup_Mips_64"
,
0
,
64
,
0
}
,
{
"fixup_Mips_TLSGD"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GOTTPREL"
,
0
,
16
,
0
}
,
{
"fixup_Mips_TPREL_HI"
,
0
,
16
,
0
}
,
{
"fixup_Mips_TPREL_LO"
,
0
,
16
,
0
}
,
{
"fixup_Mips_TLSLDM"
,
0
,
16
,
0
}
,
{
"fixup_Mips_DTPREL_HI"
,
0
,
16
,
0
}
,
{
"fixup_Mips_DTPREL_LO"
,
0
,
16
,
0
}
,
{
"fixup_Mips_Branch_PCRel"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_Mips_GPOFF_HI"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GPOFF_LO"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GOT_PAGE"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GOT_OFST"
,
0
,
16
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


"Cannot store this register to stack slot!"

Store the specified register of the given register class to the specified stack frame index .


<s>
Function
*
MBlazeIntrinsicInfo
::
getDeclaration
(
Module
*
M
,
unsigned
IntrID
,
Type
*
*
Tys
,
unsigned
numTy
)
const
{
assert
(
!
isOverloaded
(
IntrID
)
&&
"MBlaze intrinsics are not overloaded"
)
;
AttrListPtr
AList
=
getAttributes
(
M
->
getContext
(
)
,
(
mblazeIntrinsic
::
ID
)
IntrID
)
;
return
cast
<
Function
>
(
M
->
getOrInsertFunction
(
getName
(
IntrID
)
,
getType
(
M
->
getContext
(
)
,
IntrID
)
,
AList
)
)
;
}
</s>

Create or insert an LLVM Function declaration for an intrinsic , and return it .

MBlaze
MBlaze
"MBlaze intrinsics are not overloaded"
mblazeIntrinsic::ID


<s> bool Z80Operand :: isToken ( ) const { return this -> Kind == k_Token ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { getLoopAnalysisUsage ( AU ) ; } </s>


<s>
static
MCSymbol
*
GetSymbolFromOperand
(
const
MachineOperand
&
MO
,
AsmPrinter
&
AP
)
{
const
TargetMachine
&
TM
=
AP
.
TM
;
Mangler
*
Mang
=
AP
.
Mang
;
const
DataLayout
*
DL
=
TM
.
getDataLayout
(
)
;
MCContext
&
Ctx
=
AP
.
OutContext
;
bool
isDarwin
=
TM
.
getTargetTriple
(
)
.
isOSDarwin
(
)
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
)
{
if
(
isDarwin
)
Suffix
=
"$stub"
;
}
else
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
Suffix
=
"$non_lazy_ptr"
;
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
->
getPrivateGlobalPrefix
(
)
;
unsigned
PrefixLen
=
Name
.
size
(
)
;
if
(
!
MO
.
isGlobal
(
)
)
{
assert
(
MO
.
isSymbol
(
)
&&
"Isn't a symbol reference"
)
;
Mangler
::
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
,
*
DL
)
;
}
else
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
TM
.
getNameWithPrefix
(
Name
,
GV
,
*
Mang
)
;
}
unsigned
OrigLen
=
Name
.
size
(
)
PrefixLen
;
Name
+=
Suffix
;
MCSymbol
*
Sym
=
Ctx
.
getOrCreateSymbol
(
Name
)
;
StringRef
OrigName
=
StringRef
(
Name
)
.
substr
(
PrefixLen
,
OrigLen
)
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
&&
isDarwin
)
{
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
getMachOMMI
(
AP
)
.
getFnStubEntry
(
Sym
)
;
if
(
StubSym
.
getPointer
(
)
)
return
Sym
;
if
(
MO
.
isGlobal
(
)
)
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
else
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
Ctx
.
getOrCreateSymbol
(
OrigName
)
,
false
)
;
}
return
Sym
;
}
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
{
MachineModuleInfoMachO
&
MachO
=
getMachOMMI
(
AP
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_HIDDEN_FLAG
)
MachO
.
getHiddenGVStubEntry
(
Sym
)
:
MachO
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
return
Sym
;
}
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


<s> bool ix86_can_use_return_insn_p ( void ) { struct ix86_frame frame ; if ( ! reload_completed || frame_pointer_needed || cfun -> machine -> func_type != TYPE_NORMAL ) return 0 ; if ( crtl -> args . pops_args && crtl -> args . size >= 32768 ) return 0 ; ix86_compute_frame_layout ( & frame ) ; return ( frame . stack_pointer_offset == UNITS_PER_WORD && ( frame . nregs + frame . nsseregs ) == 0 ) ; } </s>

Return 1 if it is appropriate to emit ` ret ' instructions in the body of a function . Do this only if the epilogue is simple , needing a couple of insns . Prior to reloading , we ca n't tell how many registers must be saved , so return 0 then . Return 0 if there is no frame marker to de-allocate .


<s> unsigned J2RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return J2 :: R14 ; } </s>


<s> static bool nvptx_call_insn_is_syscall_p ( rtx_insn * insn ) { rtx pat = PATTERN ( insn ) ; gcc_checking_assert ( GET_CODE ( pat ) == PARALLEL ) ; pat = XVECEXP ( pat , 0 , 0 ) ; if ( GET_CODE ( pat ) == SET ) pat = SET_SRC ( pat ) ; gcc_checking_assert ( GET_CODE ( pat ) == CALL && GET_CODE ( XEXP ( pat , 0 ) ) == MEM ) ; rtx addr = XEXP ( XEXP ( pat , 0 ) , 0 ) ; if ( GET_CODE ( addr ) != SYMBOL_REF ) return false ; const char * name = XSTR ( addr , 0 ) ; return ( ! strcmp ( name , "vprintf" ) || ! strcmp ( name , "*vprintf" ) || ! strcmp ( name , "*malloc" ) || ! strcmp ( name , "*free" ) ) ; } </s>

Return true if given call insn references one of the functions provided by the CUDA runtime : malloc , free , vprintf .


"Pseudo opcode found in EmitInstruction()"


<s> bool h8sx_mergeable_memrefs_p ( rtx lhs , rtx rhs ) { if ( GET_CODE ( rhs ) == MEM && GET_CODE ( lhs ) == MEM ) { rhs = XEXP ( rhs , 0 ) ; lhs = XEXP ( lhs , 0 ) ; if ( GET_CODE ( rhs ) == PRE_INC || GET_CODE ( rhs ) == PRE_DEC ) return rtx_equal_p ( XEXP ( rhs , 0 ) , lhs ) ; if ( GET_CODE ( lhs ) == POST_INC || GET_CODE ( lhs ) == POST_DEC ) return rtx_equal_p ( rhs , XEXP ( lhs , 0 ) ) ; if ( rtx_equal_p ( rhs , lhs ) ) return true ; } return false ; } </s>

Return true if LHS and RHS are memory references that can be mapped to the same h8sx assembly operand . LHS appears as the destination of an instruction and RHS appears as a source . Three cases are allowed : - RHS is @ +Rn or @ -Rn , LHS is @ Rn - RHS is @ Rn , LHS is @ Rn+ or @ Rn- - RHS and LHS have the same address and neither has side effects .


<s> bool AMDGPUAsmParser :: usesConstantBus ( const MCInst & Inst , unsigned OpIdx ) { const MCOperand & MO = Inst . getOperand ( OpIdx ) ; if ( MO . isImm ( ) ) { return ! isInlineConstant ( Inst , OpIdx ) ; } else if ( MO . isReg ( ) ) { auto Reg = MO . getReg ( ) ; const MCRegisterInfo * TRI = getContext ( ) . getRegisterInfo ( ) ; auto PReg = mc2PseudoReg ( Reg ) ; return isSGPR ( PReg , TRI ) && PReg != SGPR_NULL ; } else { return true ; } } </s>

Returns true if this operand uses the constant bus .


<s> void sh_emit_scc_to_t ( enum rtx_code code , rtx op0 , rtx op1 ) { rtx t_reg = get_t_reg_rtx ( ) ; enum rtx_code oldcode = code ; machine_mode mode ; switch ( code ) { case NE : gcc_unreachable ( ) ; case LT : code = GT ; break ; case LE : code = GE ; break ; case LTU : code = GTU ; break ; case LEU : code = GEU ; break ; default : break ; } if ( code != oldcode ) std :: swap ( op0 , op1 ) ; mode = GET_MODE ( op0 ) ; if ( mode == VOIDmode ) mode = GET_MODE ( op1 ) ; op0 = force_reg ( mode , op0 ) ; if ( ( code != EQ && code != NE && ( op1 != const0_rtx || code == GTU || code == GEU || code == LTU || code == LEU ) ) || ( mode == DImode && op1 != const0_rtx ) || ( TARGET_SH2E && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) ) op1 = force_reg ( mode , op1 ) ; sh_emit_set_t_insn ( gen_rtx_SET ( VOIDmode , t_reg , gen_rtx_fmt_ee ( code , SImode , op0 , op1 ) ) , mode ) ; } </s>

Prepare the operands for an scc instruction ; make sure that the compare has been done and the result is in T_REG .


<s> enum reg_class mcore_reload_class ( rtx x , enum reg_class class ) { if ( reg_class_subset_p ( LRW_REGS , class ) && ! mcore_r15_operand_p ( x ) ) return LRW_REGS ; return class ; } </s>

Return the reg_class to use when reloading the rtx X into the class CLASS . If X is too complex to move directly into r15 , prefer to use LRW_REGS instead .


<s>
const
char
*
output_move_const_into_data_reg
(
rtx
*
operands
)
{
int
i
;
i
=
INTVAL
(
operands
[
1
]
)
;
switch
(
const_method
(
operands
[
1
]
)
)
{
case
MVZ
:
return
"mvsw %1,%0"
;
case
MVS
:
return
"mvzw %1,%0"
;
case
MOVQ
:
return
"moveq %1,%0"
;
case
NOTB
:
CC_STATUS_INIT
;
operands
[
1
]
=
GEN_INT
(
i
^
0xff
)
;
return
"moveq %1,%0\n\tnot%.b %0"
;
case
NOTW
:
CC_STATUS_INIT
;
operands
[
1
]
=
GEN_INT
(
i
^
0xffff
)
;
return
"moveq %1,%0\n\tnot%.w %0"
;
case
NEGW
:
CC_STATUS_INIT
;
return
"moveq #-128,%0\n\tneg%.w %0"
;
case
SWAP
:
{
unsigned
u
=
i
;
operands
[
1
]
=
GEN_INT
(
(
u
<<
16
)
|
(
u
>>
16
)
)
;
return
"moveq %1,%0\n\tswap %0"
;
}
case
MOVL
:
return
"move%.l %1,%0"
;
default
:
gcc_unreachable
(
)
;
}
}
</s>

Return an instruction to move CONST_INT OPERANDS [ 1 ] into data register OPERANDS [ 0 ] .


<s> bool addPassesToEmitMC ( PassManagerBase & , MCContext * & , raw_pwrite_stream & , bool = true ) override { return true ; } </s>

Add passes to the specified pass manager to get machine code emitted with the MCJIT .


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override { ScheduleDAGMI * DAG = createGenericSchedPostRA ( C ) ; const ARMSubtarget & ST = C -> MF -> getSubtarget < ARMSubtarget > ( ) ; if ( ST . hasFusion ( ) ) DAG -> addMutation ( createARMMacroFusionDAGMutation ( ) ) ; return DAG ; } </s>

Similar to createMachineScheduler but used when postRA machine scheduling is enabled .


<s>
void
HexagonHazardRecognizer
::
Reset
(
)
{
DEBUG
(
dbgs
(
)
<<
"Reset hazard recognizer\n"
)
;
Resources
->
clearResources
(
)
;
PacketNum
=
0
;
UsesDotCur
=
nullptr
;
DotCurPNum
=
1
;
RegDefs
.
clear
(
)
;
}
</s>


<s> static void add_insn_window ( rtx_insn * insn , dispatch_windows * window_list , int num_uops ) { int byte_len = min_insn_size ( insn ) ; int num_insn = window_list -> num_insn ; int imm_size ; sched_insn_info * window = window_list -> window ; enum dispatch_group group = get_insn_group ( insn ) ; enum insn_path path = get_insn_path ( insn ) ; int num_imm_operand ; int num_imm32_operand ; int num_imm64_operand ; if ( ! window_list -> violation && group != disp_cmp && ! fits_dispatch_window ( insn ) ) window_list -> violation = true ; imm_size = get_num_immediates ( insn , & num_imm_operand , & num_imm32_operand , & num_imm64_operand ) ; window [ num_insn ] . insn = insn ; window [ num_insn ] . byte_len = byte_len ; window [ num_insn ] . group = group ; window [ num_insn ] . path = path ; window [ num_insn ] . imm_bytes = imm_size ; window_list -> window_size += byte_len ; window_list -> num_insn = num_insn + 1 ; window_list -> num_uops = window_list -> num_uops + num_uops ; window_list -> imm_size += imm_size ; window_list -> num_imm += num_imm_operand ; window_list -> num_imm_32 += num_imm32_operand ; window_list -> num_imm_64 += num_imm64_operand ; if ( group == disp_store ) window_list -> num_stores += 1 ; else if ( group == disp_load || group == disp_prefetch ) window_list -> num_loads += 1 ; else if ( group == disp_load_store ) { window_list -> num_stores += 1 ; window_list -> num_loads += 1 ; } } </s>

Add an instruction INSN with NUM_UOPS micro-operations to the dispatch window WINDOW_LIST .


<s> FPGASubtarget & FPGASubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { initializeEnvironment ( ) ; initSubtargetFeatures ( CPU , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s>
StringRef
getPassName
(
)
const
override
{
return
"WebAssembly Fix Function Bitcasts"
;
}
</s>

getPassName - Return a nice clean name for a pass .

WebAssembly
"WebAssembly Fix Function Bitcasts"


<s> virtual void storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { storeRegToStack ( MBB , MBBI , SrcReg , isKill , FrameIndex , RC , TRI , 0 ) ; } </s>


<s> unsigned getExceptionPointerRegister ( const Constant * PersonalityFn ) const override { return ABI . IsN64 ( ) ? Mips :: A0_64 : Mips :: A0 ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
X86
::
NumTargetFixupKinds
]
=
{
{
"reloc_riprel_4byte"
,
0
,
4
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
,
}
,
{
"reloc_riprel_4byte_movq_load"
,
0
,
4
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
,
}
,
{
"reloc_signed_4byte"
,
0
,
4
*
8
,
0
}
,
{
"reloc_global_offset_table"
,
0
,
4
*
8
,
0
}
,
{
"reloc_global_offset_table8"
,
0
,
8
*
8
,
0
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> int frv_class_max_nregs ( enum reg_class class , enum machine_mode mode ) { if ( class == ACCG_REGS ) return GET_MODE_SIZE ( mode ) ; else return ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } </s>

A C expression for the maximum number of consecutive registers of class RCLASS needed to hold a value of mode MODE . This is closely related to the macro ` HARD_REGNO_NREGS ' . In fact , the value of the macro ` CLASS_MAX_NREGS ( RCLASS , MODE ) ' should be the maximum value of ` HARD_REGNO_NREGS ( REGNO , MODE ) ' for all REGNO values in the class RCLASS . This macro helps control the handling of multiple-word values in the reload pass . This declaration is required .


<s>
StringRef
getPassName
(
)
const
override
{
return
"MCS51 DAG->DAG Instruction Selection"
;
}
</s>


Subroutine of aarch64_sve_expand_vector_init . Works as follows : ( a ) Initialize TARGET by broadcasting element NELTS_REQD - 1 of BUILDER . ( b ) Skip trailing elements from BUILDER , which are the same as element NELTS_REQD - 1 . ( c ) Insert earlier elements in reverse order in TARGET using insr .


<s> const TargetRegisterClass * MipsRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return Subtarget . isABI_N64 ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> void rs6000_expand_vector_set ( rtx target , rtx val , int elt ) { enum machine_mode mode = GET_MODE ( target ) ; enum machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx reg = gen_reg_rtx ( mode ) ; rtx mask , mem , x ; int width = GET_MODE_SIZE ( inner_mode ) ; int i ; mem = assign_stack_temp ( mode , GET_MODE_SIZE ( inner_mode ) , 0 ) ; emit_move_insn ( adjust_address_nv ( mem , inner_mode , 0 ) , val ) ; x = gen_rtx_UNSPEC ( VOIDmode , gen_rtvec ( 1 , const0_rtx ) , UNSPEC_LVE ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , gen_rtx_SET ( VOIDmode , reg , mem ) , x ) ) ) ; mask = gen_rtx_PARALLEL ( V16QImode , rtvec_alloc ( 16 ) ) ; for ( i = 0 ; i < 16 ; ++ i ) XVECEXP ( mask , 0 , i ) = GEN_INT ( i ) ; for ( i = 0 ; i < width ; ++ i ) XVECEXP ( mask , 0 , elt * width + i ) = GEN_INT ( i + 0x10 ) ; x = gen_rtx_CONST_VECTOR ( V16QImode , XVEC ( mask , 0 ) ) ; x = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , target , reg , force_reg ( V16QImode , x ) ) , UNSPEC_VPERM ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , x ) ) ; } </s>


<s>
void
NVPTXTargetStreamer
::
changeSection
(
const
MCSection
*
CurSection
,
MCSection
*
Section
,
const
MCExpr
*
SubSection
,
raw_ostream
&
OS
)
{
assert
(
!
SubSection
&&
"SubSection is not null!"
)
;
const
MCObjectFileInfo
*
FI
=
getStreamer
(
)
.
getContext
(
)
.
getObjectFileInfo
(
)
;
if
(
isDwarfSection
(
FI
,
CurSection
)
)
OS
<<
"//\t}\n"
;
if
(
isDwarfSection
(
FI
,
Section
)
)
{
for
(
const
std
::
string
&
S
:
DwarfFiles
)
getStreamer
(
)
.
EmitRawText
(
S
.
data
(
)
)
;
DwarfFiles
.
clear
(
)
;
OS
<<
"//\t.section"
;
Section
->
PrintSwitchToSection
(
*
getStreamer
(
)
.
getContext
(
)
.
getAsmInfo
(
)
,
FI
->
getTargetTriple
(
)
,
OS
,
SubSection
)
;
OS
<<
"//\t{\n"
;
}
}
</s>

Update streamer for a new active section .

NVPTX
NVPTX
"SubSection is not null!"
"//\t}\n"
"//\t.section"
"//\t{\n"


<s> unsigned AArch64AsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { AArch64Operand & Op = static_cast < AArch64Operand & > ( AsmOp ) ; int64_t ExpectedVal ; switch ( Kind ) { default : return Match_InvalidOperand ; case MCK__HASH_0 : ExpectedVal = 0 ; break ; case MCK__HASH_1 : ExpectedVal = 1 ; break ; case MCK__HASH_12 : ExpectedVal = 12 ; break ; case MCK__HASH_16 : ExpectedVal = 16 ; break ; case MCK__HASH_2 : ExpectedVal = 2 ; break ; case MCK__HASH_24 : ExpectedVal = 24 ; break ; case MCK__HASH_3 : ExpectedVal = 3 ; break ; case MCK__HASH_32 : ExpectedVal = 32 ; break ; case MCK__HASH_4 : ExpectedVal = 4 ; break ; case MCK__HASH_48 : ExpectedVal = 48 ; break ; case MCK__HASH_6 : ExpectedVal = 6 ; break ; case MCK__HASH_64 : ExpectedVal = 64 ; break ; case MCK__HASH_8 : ExpectedVal = 8 ; break ; } if ( ! Op . isImm ( ) ) return Match_InvalidOperand ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ; if ( ! CE ) return Match_InvalidOperand ; if ( CE -> getValue ( ) == ExpectedVal ) return Match_Success ; return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> bool SparcAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; O << '[' ; printMemOperand ( MI , OpNo ) ; O << ']' ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


"Constant Island pass failed to converge!"

"Branch Fix Up pass failed to converge!"

runOnMachineFunction - Emit the function body .


<s>
bool
R600ClauseMergePass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
const
R600Subtarget
&
ST
=
MF
.
getSubtarget
<
R600Subtarget
>
(
)
;
TII
=
ST
.
getInstrInfo
(
)
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
,
E
=
MBB
.
end
(
)
;
MachineBasicBlock
::
iterator
LatestCFAlu
=
E
;
while
(
I
!=
E
)
{
MachineInstr
&
MI
=
*
I
++
;
if
(
(
!
TII
->
canBeConsideredALU
(
MI
)
&&
!
isCFAlu
(
MI
)
)
||
TII
->
mustBeLastInClause
(
MI
.
getOpcode
(
)
)
)
LatestCFAlu
=
E
;
if
(
!
isCFAlu
(
MI
)
)
continue
;
cleanPotentialDisabledCFAlu
(
MI
)
;
if
(
LatestCFAlu
!=
E
&&
mergeIfPossible
(
*
LatestCFAlu
,
MI
)
)
{
MI
.
eraseFromParent
(
)
;
}
else
{
assert
(
MI
.
getOperand
(
8
)
.
getImm
(
)
&&
"CF ALU instruction disabled"
)
;
LatestCFAlu
=
MI
;
}
}
}
return
false
;
}
</s>


"\tmove\t%s,%s\t\t# save current return address\n"

"\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from  stack\n"


<s> bool ARM64TargetLowering :: isDesirableToCommuteWithShift ( const SDNode * N ) const { EVT VT = N -> getValueType ( 0 ) ; if ( N -> getOpcode ( ) == ISD :: AND && ( VT == MVT :: i32 || VT == MVT :: i64 ) && isa < ConstantSDNode > ( N -> getOperand ( 1 ) ) ) { uint64_t TruncMask = N -> getConstantOperandVal ( 1 ) ; if ( isMask_64 ( TruncMask ) && N -> getOperand ( 0 ) . getOpcode ( ) == ISD :: SRL && isa < ConstantSDNode > ( N -> getOperand ( 0 ) -> getOperand ( 1 ) ) ) return false ; } return true ; } </s>

Return true if it is profitable to move this shift by a constant amount through its operand , adjusting any immediate operands as necessary to preserve semantics .


"Thumb1 does not have ldr to high register"

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s> bool SystemZAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { SystemZInstPrinter :: printAddress ( MAI , MI -> getOperand ( OpNo ) . getReg ( ) , MI -> getOperand ( OpNo + 1 ) . getImm ( ) , MI -> getOperand ( OpNo + 2 ) . getReg ( ) , OS ) ; return false ; } </s>


<s> bool SIInstrInfo :: isIgnorableUse ( const MachineOperand & MO ) const { return MO . getReg ( ) == AMDGPU :: EXEC && MO . isImplicit ( ) && isVALU ( * MO . getParent ( ) ) ; } </s>

Given MO is a PhysReg use return if it can be ignored for the purpose of instruction rematerialization or sinking .


<s> static int fast_interrupt_p ( tree node ATTRIBUTE_UNUSED ) { tree list = M32C_ATTRIBUTES ( node ) ; while ( list ) { if ( is_attribute_p ( "fast_interrupt" , TREE_PURPOSE ( list ) ) ) return 1 ; list = TREE_CHAIN ( list ) ; } return 0 ; } </s>

Returns TRUE if the given tree has the `` fast_interrupt '' attribute .


<s> static rtx arc_get_ccfsm_cond ( struct arc_ccfsm * statep , bool reverse ) { rtx cond = statep -> cond ; int raw_cc = get_arc_condition_code ( cond ) ; if ( reverse ) raw_cc = ARC_INVERSE_CONDITION_CODE ( raw_cc ) ; if ( statep -> cc == raw_cc ) return copy_rtx ( cond ) ; gcc_assert ( ARC_INVERSE_CONDITION_CODE ( raw_cc ) == statep -> cc ) ; machine_mode ccm = GET_MODE ( XEXP ( cond , 0 ) ) ; enum rtx_code code = reverse_condition ( GET_CODE ( cond ) ) ; if ( code == UNKNOWN || ccm == CC_FP_GTmode || ccm == CC_FP_GEmode ) code = reverse_condition_maybe_unordered ( GET_CODE ( cond ) ) ; return gen_rtx_fmt_ee ( code , GET_MODE ( cond ) , copy_rtx ( XEXP ( cond , 0 ) ) , copy_rtx ( XEXP ( cond , 1 ) ) ) ; } </s>

Return a copy of COND from * STATEP , inverted if that is indicated by the CC field of * STATEP .


<s> const DataLayout * getDataLayout ( ) const override { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> void storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , Register SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const override { storeRegToStack ( MBB , MBBI , SrcReg , isKill , FrameIndex , RC , TRI , 0 ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s>
SDValue
LEGTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unimplemented operand"
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

LEG
LEG
"Unimplemented operand"
ISD::GlobalAddress


<s> void s390_expand_cs ( machine_mode mode , rtx btarget , rtx vtarget , rtx mem , rtx cmp , rtx new_rtx , bool is_weak ) { switch ( mode ) { case TImode : case DImode : case SImode : s390_expand_cs_tdsi ( mode , btarget , vtarget , mem , cmp , new_rtx , is_weak ) ; break ; case HImode : case QImode : s390_expand_cs_hqi ( mode , btarget , vtarget , mem , cmp , new_rtx , is_weak ) ; break ; default : gcc_unreachable ( ) ; } } </s>

Expand an atomic compare and swap operation . MEM is the memory location , CMP the old value to compare MEM with and NEW_RTX the value to set if CMP == MEM .


<s> bool SystemZTargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const { return isInt < 32 > ( Imm ) || isUInt < 32 > ( Imm ) ; } </s>

Return true if the specified immediate is legal icmp immediate , that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register .


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCRelaxableFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
{
assert
(
0
&&
"RelaxInstruction() unimplemented"
)
;
return
false
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .

Videocore
0
"RelaxInstruction() unimplemented"


<s> void F2003fPassConfig :: addPreEmitPass ( ) { addPass ( createF2003fFiMalkrzPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> unsigned X86TTIImpl :: getScalarizationOverhead ( Type * Ty , const APInt & DemandedElts , bool Insert , bool Extract ) { auto * VecTy = cast < VectorType > ( Ty ) ; unsigned Cost = 0 ; if ( Insert ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; MVT MScalarTy = LT . second . getScalarType ( ) ; if ( ( MScalarTy == MVT :: i16 && ST -> hasSSE2 ( ) ) || ( MScalarTy . isInteger ( ) && ST -> hasSSE41 ( ) ) || ( MScalarTy == MVT :: f32 && ST -> hasSSE41 ( ) ) ) { if ( LT . second . getSizeInBits ( ) <= 128 ) { Cost += BaseT :: getScalarizationOverhead ( Ty , DemandedElts , Insert , false ) ; } else { unsigned NumSubVecs = LT . second . getSizeInBits ( ) / 128 ; Cost += ( PowerOf2Ceil ( NumSubVecs ) - 1 ) * LT . first ; Cost += DemandedElts . countPopulation ( ) ; if ( MScalarTy == MVT :: f32 ) for ( unsigned i = 0 , e = VecTy -> getNumElements ( ) ; i < e ; i += 4 ) if ( DemandedElts [ i ] ) Cost -- ; } } else if ( LT . second . isVector ( ) ) { if ( Ty -> isIntOrIntVectorTy ( ) ) Cost += DemandedElts . countPopulation ( ) ; unsigned NumElts = LT . second . getVectorNumElements ( ) ; unsigned Pow2Elts = PowerOf2Ceil ( VecTy -> getNumElements ( ) ) ; Cost += ( std :: min < unsigned > ( NumElts , Pow2Elts ) - 1 ) * LT . first ; } } if ( Extract ) Cost += BaseT :: getScalarizationOverhead ( Ty , DemandedElts , false , Extract ) ; return Cost ; } </s>

Estimate the overhead of scalarizing an instruction .


"********** Exception Info Calculation **********\n"


<s> bool ARMAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AFI = MF . getInfo < ARMFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) { NaClAlignAllJumpTargetsAndConstantPools ( MF ) ; } return AsmPrinter :: runOnMachineFunction ( MF ) ; } </s>


<s> SDValue CreateLiveInRegister ( SelectionDAG & DAG , const TargetRegisterClass * RC , unsigned Reg , EVT VT ) const { return CreateLiveInRegister ( DAG , RC , Reg , VT , SDLoc ( DAG . getEntryNode ( ) ) ) ; } </s>

Helper function that adds Reg to the LiveIn list of the DAG 's MachineFunction .


<s> void StackFixup :: annotate ( const Stack & stack ) { Stack curStack ( stack ) ; for ( auto & p : Changes ) { curStack += p . first ; p . second = curStack . toString ( ) ; } } </s>


<s> int M68kRegisterInfo :: getRegisterOrder ( unsigned Reg , const TargetRegisterClass & TRC ) const { for ( unsigned i = 0 ; i < TRC . getNumRegs ( ) ; ++ i ) { if ( regsOverlap ( Reg , TRC . getRegister ( i ) ) ) { return i ; } } return - 1 ; } </s>

Return index of a register within a register class , otherwise return -1 .


<s> bool arc_check_multi ( rtx op , bool push_p ) { HOST_WIDE_INT len = XVECLEN ( op , 0 ) ; unsigned int regno , i , start ; unsigned int memp = push_p ? 0 : 1 ; rtx elt ; if ( len <= 1 ) return false ; start = 1 ; elt = XVECEXP ( op , 0 , 0 ) ; if ( ! push_p && GET_CODE ( elt ) == RETURN ) start = 2 ; for ( i = start , regno = ENTER_LEAVE_START_REG ; i < len ; i ++ , regno ++ ) { rtx elt = XVECEXP ( op , 0 , i ) ; rtx reg , mem , addr ; if ( GET_CODE ( elt ) != SET ) return false ; mem = XEXP ( elt , memp ) ; reg = XEXP ( elt , 1 - memp ) ; if ( ! REG_P ( reg ) || ! MEM_P ( mem ) ) return false ; if ( REGNO ( reg ) == RETURN_ADDR_REGNUM && i == start ) regno = 12 ; else if ( REGNO ( reg ) == HARD_FRAME_POINTER_REGNUM ) ++ i ; else if ( REGNO ( reg ) != regno ) return false ; addr = XEXP ( mem , 0 ) ; if ( GET_CODE ( addr ) == PLUS ) { if ( ! rtx_equal_p ( stack_pointer_rtx , XEXP ( addr , 0 ) ) || ! CONST_INT_P ( XEXP ( addr , 1 ) ) ) return false ; } else { if ( ! rtx_equal_p ( stack_pointer_rtx , addr ) ) return false ; } } return true ; } </s>

Helper for { push/pop } _multi_operand : check if rtx OP is a suitable construct to match either enter or leave instruction . Which one which is selected by PUSH_P argument .


<s> bool ARMTargetLowering :: shouldInsertFencesForAtomic ( const Instruction * I ) const { return InsertFencesForAtomic ; } </s>

Helper functions for atomic operations .


<s> void AGCELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; TextSection = ( MCSection * ) Ctx . getELFSection ( "BLOCK2" , ELF :: SHT_PROGBITS , ELF :: SHF_EXECINSTR | ELF :: SHF_ALLOC ) ; } </s>

This method must be called before any actual lowering is done .


<s> void emitBytes ( StringRef Data ) override { EmitMappingSymbol ( "$d" ) ; MCELFStreamer :: emitBytes ( Data ) ; } </s>

Emit the bytes in Data into the output .


<s> CCAssignFn * ARMTargetLowering :: CCAssignFnForReturn ( CallingConv :: ID CC , bool isVarArg ) const { return CCAssignFnForNode ( CC , true , isVarArg ) ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> bool isTargetEHABICompatible ( ) const { return ( TargetTriple . getEnvironment ( ) == Triple :: EABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: EABIHF || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: Android ) && ! isTargetDarwin ( ) && ! isTargetWindows ( ) && ! isTargetNaCl ( ) && ! EnableARMDwarfEH ; } </s>

Tests whether the target supports the EHABI exception handling standard .


<s> SDValue SICTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SDNode * CallNode , const Type * RetTy ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; SICCC SICCCInfo ( CallConv , ABI . IsO32 ( ) , CCInfo ) ; SICCCInfo . analyzeCallResult ( Ins , Subtarget . abiUsesSoftFloat ( ) , CallNode , RetTy ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( 1 ) ; InFlag = Val . getValue ( 2 ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( ISD :: BITCAST , DL , RVLocs [ i ] . getValVT ( ) , Val ) ; InVals . push_back ( Val ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> bool WebAssemblySubtarget :: enableMachineScheduler ( ) const { return true ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


<s> static inline tree def_builtin ( HOST_WIDE_INT mask , HOST_WIDE_INT mask2 , const char * name , enum ix86_builtin_func_type tcode , enum ix86_builtins code ) { tree decl = NULL_TREE ; if ( ! ( mask & OPTION_MASK_ISA_64BIT ) || TARGET_64BIT ) { ix86_builtins_isa [ ( int ) code ] . isa = mask ; ix86_builtins_isa [ ( int ) code ] . isa2 = mask2 ; mask &= ~ OPTION_MASK_ISA_64BIT ; if ( ( mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512VL ) && mask != OPTION_MASK_ISA_AVX512VL ) mask &= ~ OPTION_MASK_ISA_AVX512VL ; if ( ( mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512BW ) && mask != OPTION_MASK_ISA_AVX512BW ) mask &= ~ OPTION_MASK_ISA_AVX512BW ; if ( ( ( mask2 == 0 || ( mask2 & ix86_isa_flags2 ) != 0 ) && ( mask == 0 || ( mask & ix86_isa_flags ) != 0 ) ) || ( ( mask & OPTION_MASK_ISA_MMX ) != 0 && TARGET_MMX_WITH_SSE ) || ( mask2 == OPTION_MASK_ISA2_AVXVNNI ) || ( mask2 == OPTION_MASK_ISA2_AVXIFMA ) || ( mask2 == ( OPTION_MASK_ISA2_AVXNECONVERT | OPTION_MASK_ISA2_AVX512BF16 ) ) || ( lang_hooks . builtin_function == lang_hooks . builtin_function_ext_scope ) ) { tree type = ix86_get_builtin_func_type ( tcode ) ; decl = add_builtin_function ( name , type , code , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ ( int ) code ] = decl ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = false ; } else { deferred_isa_values |= mask ; deferred_isa_values2 |= mask2 ; ix86_builtins [ ( int ) code ] = NULL_TREE ; ix86_builtins_isa [ ( int ) code ] . tcode = tcode ; ix86_builtins_isa [ ( int ) code ] . name = name ; ix86_builtins_isa [ ( int ) code ] . const_p = false ; ix86_builtins_isa [ ( int ) code ] . pure_p = false ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = true ; } } return decl ; } </s>

Add a SPARC builtin function with NAME , ICODE , CODE and TYPE . Return the function decl or NULL_TREE if the builtin was not added .


<s> Optional < Instruction * > AArch64TTIImpl :: instCombineIntrinsic ( InstCombiner & IC , IntrinsicInst & II ) const { Intrinsic :: ID IID = II . getIntrinsicID ( ) ; switch ( IID ) { default : break ; case Intrinsic :: aarch64_sve_convert_from_svbool : return instCombineConvertFromSVBool ( IC , II ) ; case Intrinsic :: aarch64_sve_dup : return instCombineSVEDup ( IC , II ) ; case Intrinsic :: aarch64_sve_cmpne : case Intrinsic :: aarch64_sve_cmpne_wide : return instCombineSVECmpNE ( IC , II ) ; case Intrinsic :: aarch64_sve_rdffr : return instCombineRDFFR ( IC , II ) ; case Intrinsic :: aarch64_sve_lasta : case Intrinsic :: aarch64_sve_lastb : return instCombineSVELast ( IC , II ) ; case Intrinsic :: aarch64_sve_cntd : return instCombineSVECntElts ( IC , II , 2 ) ; case Intrinsic :: aarch64_sve_cntw : return instCombineSVECntElts ( IC , II , 4 ) ; case Intrinsic :: aarch64_sve_cnth : return instCombineSVECntElts ( IC , II , 8 ) ; case Intrinsic :: aarch64_sve_cntb : return instCombineSVECntElts ( IC , II , 16 ) ; case Intrinsic :: aarch64_sve_ptest_any : case Intrinsic :: aarch64_sve_ptest_first : case Intrinsic :: aarch64_sve_ptest_last : return instCombineSVEPTest ( IC , II ) ; case Intrinsic :: aarch64_sve_mul : case Intrinsic :: aarch64_sve_fmul : return instCombineSVEVectorMul ( IC , II ) ; case Intrinsic :: aarch64_sve_tbl : return instCombineSVETBL ( IC , II ) ; } return None ; } </s>

Targets can implement their own combinations for target-specific intrinsics .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createPatmosELFObjectWriter ( OS , OSType ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> gimple * gimple_folder :: fold_to_ptrue ( ) { tree svbool_type = TREE_TYPE ( lhs ) ; tree bool_type = TREE_TYPE ( svbool_type ) ; unsigned int element_bytes = type_suffix ( 0 ) . element_bytes ; tree_vector_builder builder ( svbool_type , element_bytes , 1 ) ; builder . quick_push ( build_all_ones_cst ( bool_type ) ) ; for ( unsigned int i = 1 ; i < element_bytes ; ++ i ) builder . quick_push ( build_zero_cst ( bool_type ) ) ; return gimple_build_assign ( lhs , builder . build ( ) ) ; } </s>

Fold the call to a PTRUE , taking the element size from type suffix 0 .


<s>
static
void
rl78_start_function
(
FILE
*
file
,
HOST_WIDE_INT
hwi_local
ATTRIBUTE_UNUSED
)
{
int
i
;
if
(
cfun
->
machine
->
framesize
==
0
)
return
;
fprintf
(
file
,
"\t; start of function\n"
)
;
if
(
cfun
->
machine
->
framesize_regs
)
{
fprintf
(
file
,
"\t; push %d:"
,
cfun
->
machine
->
framesize_regs
)
;
for
(
i
=
0
;
i
<
16
;
i
++
)
if
(
cfun
->
machine
->
need_to_push
[
i
]
)
fprintf
(
file
,
" %s"
,
word_regnames
[
i
*
2
]
)
;
fprintf
(
file
,
"\n"
)
;
}
if
(
frame_pointer_needed
)
fprintf
(
file
,
"\t; $fp points here (r22)\n"
)
;
if
(
cfun
->
machine
->
framesize_locals
)
fprintf
(
file
,
"\t; locals: %d byte%s\n"
,
cfun
->
machine
->
framesize_locals
,
cfun
->
machine
->
framesize_locals
==
1
""
:
"s"
)
;
if
(
cfun
->
machine
->
framesize_outgoing
)
fprintf
(
file
,
"\t; outgoing: %d byte%s\n"
,
cfun
->
machine
->
framesize_outgoing
,
cfun
->
machine
->
framesize_outgoing
==
1
""
:
"s"
)
;
if
(
cfun
->
machine
->
uses_es
)
fprintf
(
file
,
"\t; uses ES register\n"
)
;
if
(
MUST_SAVE_MDUC_REGISTERS
)
fprintf
(
file
,
"\t; preserves MDUC registers\n"
)
;
}
</s>

We do n't use this to actually emit the function prologue . We use this to insert a comment in the asm file describing the function .


<s> static rtx gen_movdi_x ( rtx dest , rtx src , rtx offset ATTRIBUTE_UNUSED ) { return gen_movdi ( dest , src ) ; } </s>

Wrapper functions that discards the CONST_INT spill offset . These exist so that we can give gr_spill/gr_fill the offset they need and use a consistant function interface .


<s> bool aarch_pac_insn_p ( rtx x ) { if ( ! x || ! INSN_P ( x ) ) return false ; rtx pat = PATTERN ( x ) ; if ( GET_CODE ( pat ) == SET ) { rtx tmp = XEXP ( pat , 1 ) ; if ( tmp && ( ( GET_CODE ( tmp ) == UNSPEC && XINT ( tmp , 1 ) == UNSPEC_PAC_NOP ) || ( GET_CODE ( tmp ) == UNSPEC_VOLATILE && XINT ( tmp , 1 ) == VUNSPEC_PACBTI_NOP ) ) ) return true ; } return false ; } </s>

Check if X ( or any sub-rtx of X ) is a PACIASP/PACIBSP instruction .


<s> static rtx get_pic_reg ( void ) { if ( ! reload_completed && ! reload_in_progress ) abort ( ) ; if ( ! cfun -> machine -> pic_reg ) { if ( crtl -> is_leaf && ! df_regs_ever_live_p ( LAST_ARG_REGNUM ) ) cfun -> machine -> pic_reg = gen_rtx_REG ( SImode , LAST_ARG_REGNUM ) ; else cfun -> machine -> pic_reg = pic_offset_table_rtx ; } return cfun -> machine -> pic_reg ; } </s>

For PIC mode we 've reserved PIC_OFFSET_TABLE_REGNUM , which is a caller saved register . For leaf functions it is more efficient to use a volatile register because we wo n't need to save and restore the pic register . This routine is only valid after register allocation is completed , so we can pick an unused register .


<s> static struct machine_function * riscv_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function > ( ) ; } </s>

Allocate a chunk of memory for per-function machine-dependent data .


<s> BitVector SystemZRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( SystemZ :: R11D ) ; Reserved . set ( SystemZ :: R11L ) ; Reserved . set ( SystemZ :: R11H ) ; Reserved . set ( SystemZ :: R10Q ) ; } Reserved . set ( SystemZ :: R15D ) ; Reserved . set ( SystemZ :: R15L ) ; Reserved . set ( SystemZ :: R15H ) ; Reserved . set ( SystemZ :: R14Q ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void Cpu0AsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( Fixup , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { default : FullSize = 4 ; break ; } uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - 1 - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool SITargetLowering :: shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const { return true ; } </s>

Returns true if it is beneficial to convert a load of a constant to just the constant itself .


<s> bool RISCVTargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { return CI -> isTailCall ( ) ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> static unsigned HOST_WIDE_INT loongarch_asan_shadow_offset ( void ) { return TARGET_64BIT ? ( HOST_WIDE_INT_1 << 46 ) : 0 ; } </s>

Implement the TARGET_ASAN_SHADOW_OFFSET hook .


<s> bool AMDGPUAtomicOptimizer :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) { return false ; } DA = & getAnalysis < LegacyDivergenceAnalysis > ( ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; DominatorTreeWrapperPass * const DTW = getAnalysisIfAvailable < DominatorTreeWrapperPass > ( ) ; DT = DTW ? & DTW -> getDomTree ( ) : nullptr ; const TargetPassConfig & TPC = getAnalysis < TargetPassConfig > ( ) ; const TargetMachine & TM = TPC . getTM < TargetMachine > ( ) ; const GCNSubtarget & ST = TM . getSubtarget < GCNSubtarget > ( F ) ; HasDPP = ST . hasDPP ( ) ; visit ( F ) ; const bool Changed = ! ToReplace . empty ( ) ; for ( ReplacementInfo & Info : ToReplace ) { optimizeAtomic ( * Info . I , Info . Op , Info . ValIdx , Info . ValDivergent ) ; } ToReplace . clear ( ) ; return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void pa_hpux_asm_output_external ( FILE * file , tree decl , const char * name ) { extern_symbol * p = VEC_safe_push ( extern_symbol , gc , extern_symbols , NULL ) ; gcc_assert ( file == asm_out_file ) ; p -> decl = decl ; p -> name = name ; } </s>

Mark DECL ( name NAME ) as an external reference ( assembler output file FILE ) . This saves the names to output at the end of the file if actually referenced .


<s> enum rtx_code ix86_reverse_condition ( enum rtx_code code , machine_mode mode ) { return ( mode != CCFPmode && mode != CCFPUmode ? reverse_condition ( code ) : reverse_condition_maybe_unordered ( code ) ) ; } </s>


<s> bool alpha_split_const_mov ( machine_mode mode , rtx * operands ) { HOST_WIDE_INT i0 ; rtx temp = NULL_RTX ; i0 = alpha_extract_integer ( operands [ 1 ] ) ; temp = alpha_emit_set_const ( operands [ 0 ] , mode , i0 , 3 , false ) ; if ( ! temp && TARGET_BUILD_CONSTANTS ) temp = alpha_emit_set_long_const ( operands [ 0 ] , i0 ) ; if ( temp ) { if ( ! rtx_equal_p ( operands [ 0 ] , temp ) ) emit_move_insn ( operands [ 0 ] , temp ) ; return true ; } return false ; } </s>

Operand 1 is known to be a constant , and should require more than one instruction to load . Emit that multi-part load .


<s> TargetPassConfig * J2TargetMachine :: createPassConfig ( PassManagerBase & PM ) { struct J2PassConfig : public TargetPassConfig { J2PassConfig ( J2TargetMachine * TM , PassManagerBase & PM ) : TargetPassConfig ( * TM , PM ) { } J2TargetMachine & getJ2TargetMachine ( ) const { return getTM < J2TargetMachine > ( ) ; } bool addInstSelector ( ) override { addPass ( new J2DAGToDAGISel ( getJ2TargetMachine ( ) ) ) ; return false ; } void addPreEmitPass ( ) override { addPass ( createJ2DelaySlotFillerPass ( getJ2TargetMachine ( ) ) ) ; addPass ( createJ2ConstantIslandPass ( ) ) ; } } ; return new J2PassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> static int branch_dest ( rtx branch ) { rtx pat = PATTERN ( branch ) ; rtx dest = ( GET_CODE ( pat ) == PARALLEL ? SET_SRC ( XVECEXP ( pat , 0 , 0 ) ) : SET_SRC ( pat ) ) ; int dest_uid ; if ( GET_CODE ( dest ) == IF_THEN_ELSE ) dest = XEXP ( dest , XEXP ( dest , 1 ) == pc_rtx ? 2 : 1 ) ; dest = XEXP ( dest , 0 ) ; dest_uid = INSN_UID ( dest ) ; return INSN_ADDRESSES ( dest_uid ) ; } </s>

Return the destination address of BRANCH . We need to use this instead of get_attr_length , because the cbranch_with_nops pattern conservatively sets its length to 6 , and we still prefer to use shorter sequences .


<s> static bool fpop_insn_p ( rtx_insn * insn ) { if ( GET_CODE ( PATTERN ( insn ) ) != SET ) return false ; switch ( get_attr_type ( insn ) ) { case TYPE_FPMOVE : case TYPE_FPCMOVE : case TYPE_FP : case TYPE_FPCMP : case TYPE_FPMUL : case TYPE_FPDIVS : case TYPE_FPSQRTS : case TYPE_FPDIVD : case TYPE_FPSQRTD : return true ; default : return false ; } } </s>

True if INSN is a floating-point instruction .


<s>
void
AVRRegisterInfo
::
splitReg
(
unsigned
Reg
,
unsigned
&
LoReg
,
unsigned
&
HiReg
)
const
{
assert
(
AVR
::
DREGSRegClass
.
contains
(
Reg
)
&&
"can only split 16-bit registers"
)
;
LoReg
=
getSubReg
(
Reg
,
AVR
::
sub_lo
)
;
HiReg
=
getSubReg
(
Reg
,
AVR
::
sub_hi
)
;
}
</s>

Splits a 16-bit DREGS register into the lo/hi register pair .

AVR
AVR
AVR::DREGSRegClass
"can only split 16-bit registers"
AVR::sub_lo
AVR::sub_hi