<s> void RISCVFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( hasFP ( MF ) ) { SavedRegs . set ( RISCV :: X1 ) ; SavedRegs . set ( RISCV :: X8 ) ; } if ( hasBP ( MF ) ) SavedRegs . set ( RISCVABI :: getBPReg ( ) ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MF . getFunction ( ) . hasFnAttribute ( "interrupt" ) && MFI . hasCalls ( ) ) { static const MCPhysReg CSRegs [ ] = { RISCV :: X1 , RISCV :: X5 , RISCV :: X6 , RISCV :: X7 , RISCV :: X10 , RISCV :: X11 , RISCV :: X12 , RISCV :: X13 , RISCV :: X14 , RISCV :: X15 , RISCV :: X16 , RISCV :: X17 , RISCV :: X28 , RISCV :: X29 , RISCV :: X30 , RISCV :: X31 , 0 } ; for ( unsigned i = 0 ; CSRegs [ i ] ; ++ i ) SavedRegs . set ( CSRegs [ i ] ) ; if ( MF . getSubtarget < RISCVSubtarget > ( ) . hasStdExtD ( ) || MF . getSubtarget < RISCVSubtarget > ( ) . hasStdExtF ( ) ) { const MCPhysReg * Regs = MF . getRegInfo ( ) . getCalleeSavedRegs ( ) ; for ( unsigned i = 0 ; Regs [ i ] ; ++ i ) if ( RISCV :: FPR32RegClass . contains ( Regs [ i ] ) || RISCV :: FPR64RegClass . contains ( Regs [ i ] ) ) SavedRegs . set ( Regs [ i ] ) ; } } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> bool MipsMCCodeEmitter :: isMicroMips ( const MCSubtargetInfo & STI ) const { return STI . getFeatureBits ( ) [ Mips :: FeatureMicroMips ] ; } </s>

Check whether a given symbol has been flagged with MICROMIPS flag .


<s> BitVector HexagonRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( Hexagon :: R29 ) ; Reserved . set ( Hexagon :: R30 ) ; Reserved . set ( Hexagon :: R31 ) ; Reserved . set ( Hexagon :: PC ) ; Reserved . set ( Hexagon :: D14 ) ; Reserved . set ( Hexagon :: D15 ) ; Reserved . set ( Hexagon :: LC0 ) ; Reserved . set ( Hexagon :: LC1 ) ; Reserved . set ( Hexagon :: SA0 ) ; Reserved . set ( Hexagon :: SA1 ) ; Reserved . set ( Hexagon :: UGP ) ; Reserved . set ( Hexagon :: GP ) ; Reserved . set ( Hexagon :: CS0 ) ; Reserved . set ( Hexagon :: CS1 ) ; Reserved . set ( Hexagon :: CS ) ; Reserved . set ( Hexagon :: USR ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
ARM
::
NumTargetFixupKinds
]
=
{
{
"fixup_arm_ldst_pcrel_12"
,
1
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_ldst_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_pcrel_10"
,
1
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_pcrel_10"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_thumb_adr_pcrel_10"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_adr_pcrel_12"
,
1
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_adr_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_condbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_uncondbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_condbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_uncondbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_br"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_bl"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_blx"
,
7
,
21
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cb"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cp"
,
1
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_bcc"
,
1
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
TargetAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


"Unexpected base pointer for inline asm memory operand."

"Unexpected offset for inline asm memory operand."

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( CommentStream ) HasCustomInstComment = EmitAnyX86InstComments ( MI , * CommentStream , getRegisterName ) ; if ( TSFlags & X86II :: LOCK ) OS << "\tlock\n" ; if ( MI -> getOpcode ( ) == X86 :: CALLpcrel32 && ( getAvailableFeatures ( ) & X86 :: Mode64Bit ) != 0 ) { OS << "\tcallq\t" ; printPCRelImm ( MI , 0 , OS ) ; } else if ( ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool runOnFunction ( Function & F ) override { if ( skipFunction ( F ) ) return false ; AliasAnalysis & AA = getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; AssumptionCache & AC = getAnalysis < AssumptionCacheTracker > ( ) . getAssumptionCache ( F ) ; DominatorTree & DT = getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; TargetLibraryInfo & TLI = getAnalysis < TargetLibraryInfoWrapperPass > ( ) . getTLI ( F ) ; auto & TM = getAnalysis < TargetPassConfig > ( ) . getTM < HexagonTargetMachine > ( ) ; HexagonVectorCombine HVC ( F , AA , AC , DT , TLI , TM ) ; return HVC . run ( ) ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool SPUTargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createSPUNopFillerPass ( * this ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool MipsHazardSchedule :: runOnMachineFunction ( MachineFunction & MF ) { const MipsSubtarget * STI = & static_cast < const MipsSubtarget & > ( MF . getSubtarget ( ) ) ; if ( ! STI -> hasMips32r6 ( ) || STI -> inMicroMipsMode ( ) ) return false ; bool Changed = false ; const MipsInstrInfo * TII = STI -> getInstrInfo ( ) ; for ( MachineFunction :: iterator FI = MF . begin ( ) ; FI != MF . end ( ) ; ++ FI ) { for ( Iter I = FI -> begin ( ) ; I != FI -> end ( ) ; ++ I ) { if ( ! TII -> HasForbiddenSlot ( * I ) ) continue ; Iter Inst ; bool LastInstInFunction = std :: next ( I ) == FI -> end ( ) && std :: next ( FI ) == MF . end ( ) ; if ( ! LastInstInFunction ) { Inst = getNextMachineInstr ( std :: next ( I ) , & * FI ) ; } if ( LastInstInFunction || ! TII -> SafeInForbiddenSlot ( * Inst ) ) { Changed = true ; MIBundleBuilder ( & * I ) . append ( BuildMI ( MF , I -> getDebugLoc ( ) , TII -> get ( Mips :: NOP ) ) ) ; NumInsertedNops ++ ; } } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .

Mips Mips Mips Mips Mips Mips Mips Mips::NOP


<s> void advance ( ) { assert ( Current != - 1 ) ; Current = Set . V . find_next ( Current ) ; } </s>

Advance across the current instruction .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Hexagon early if conversion"
;
}
</s>

getPassName - Return a nice clean name for a pass .


The actual update/transfer function which has to be implemented by the derived classes .


<s> MCSection * getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , unsigned & Align , const GlobalObject * GO ) const override { return ReadOnlySection ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


"Do not know how to return this many arguments!"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> bool PPCInstrInfo :: isBDNZ ( unsigned Opcode ) const { return ( Opcode == ( Subtarget . isPPC64 ( ) ? PPC :: BDNZ8 : PPC :: BDNZ ) ) ; } </s>

Check Opcode is BDNZ ( Decrement CTR and branch if it is still nonzero ) .


<s>
static
void
riscv_emit_attribute
(
)
{
fprintf
(
asm_out_file
,
"\t.attribute arch, \"%s\"\n"
,
riscv_arch_str
(
)
.
c_str
(
)
)
;
fprintf
(
asm_out_file
,
"\t.attribute unaligned_access, %d\n"
,
TARGET_STRICT_ALIGN
0
:
1
)
;
fprintf
(
asm_out_file
,
"\t.attribute stack_align, %d\n"
,
riscv_stack_boundary
/
8
)
;
}
</s>

Auxiliary function to emit RISC-V ELF attribute .


<s> RISCVSubtarget & RISCVSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS , bool Is64Bit ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = Is64Bit ? "generic-rv64" : "generic-rv32" ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( Is64Bit ) { XLenVT = MVT :: i64 ; XLen = 64 ; } return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> void X86InstrInfo :: breakPartialRegDependency ( MachineInstr & MI , unsigned OpNum , const TargetRegisterInfo * TRI ) const { unsigned Reg = MI . getOperand ( OpNum ) . getReg ( ) ; if ( MI . killsRegister ( Reg , TRI ) ) return ; if ( X86 :: VR128RegClass . contains ( Reg ) ) { unsigned Opc = Subtarget . hasAVX ( ) ? X86 :: VXORPSrr : X86 :: XORPSrr ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( Opc ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; MI . addRegisterKilled ( Reg , TRI , true ) ; } else if ( X86 :: VR256RegClass . contains ( Reg ) ) { unsigned XReg = TRI -> getSubReg ( Reg , X86 :: sub_xmm ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( X86 :: VXORPSrr ) , XReg ) . addReg ( XReg , RegState :: Undef ) . addReg ( XReg , RegState :: Undef ) . addReg ( Reg , RegState :: ImplicitDefine ) ; MI . addRegisterKilled ( Reg , TRI , true ) ; } else if ( X86 :: GR64RegClass . contains ( Reg ) ) { unsigned XReg = TRI -> getSubReg ( Reg , X86 :: sub_32bit ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( X86 :: XOR32rr ) , XReg ) . addReg ( XReg , RegState :: Undef ) . addReg ( XReg , RegState :: Undef ) . addReg ( Reg , RegState :: ImplicitDefine ) ; MI . addRegisterKilled ( Reg , TRI , true ) ; } else if ( X86 :: GR32RegClass . contains ( Reg ) ) { BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( X86 :: XOR32rr ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; MI . addRegisterKilled ( Reg , TRI , true ) ; } } </s>

Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum .


<s> SDNode * SITargetLowering :: legalizeTargetIndependentNode ( SDNode * Node , SelectionDAG & DAG ) const { if ( Node -> getOpcode ( ) == ISD :: CopyToReg ) { RegisterSDNode * DestReg = cast < RegisterSDNode > ( Node -> getOperand ( 1 ) ) ; SDValue SrcVal = Node -> getOperand ( 2 ) ; if ( SrcVal . getValueType ( ) == MVT :: i1 && TargetRegisterInfo :: isPhysicalRegister ( DestReg -> getReg ( ) ) ) { SDLoc SL ( Node ) ; MachineRegisterInfo & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue VReg = DAG . getRegister ( MRI . createVirtualRegister ( & AMDGPU :: VReg_1RegClass ) , MVT :: i1 ) ; SDNode * Glued = Node -> getGluedNode ( ) ; SDValue ToVReg = DAG . getCopyToReg ( Node -> getOperand ( 0 ) , SL , VReg , SrcVal , SDValue ( Glued , Glued ? Glued -> getNumValues ( ) - 1 : 0 ) ) ; SDValue ToResultReg = DAG . getCopyToReg ( ToVReg , SL , SDValue ( DestReg , 0 ) , VReg , ToVReg . getValue ( 1 ) ) ; DAG . ReplaceAllUsesWith ( Node , ToResultReg . getNode ( ) ) ; DAG . RemoveDeadNode ( Node ) ; return ToResultReg . getNode ( ) ; } } SmallVector < SDValue , 8 > Ops ; for ( unsigned i = 0 ; i < Node -> getNumOperands ( ) ; ++ i ) { if ( ! isFrameIndexOp ( Node -> getOperand ( i ) ) ) { Ops . push_back ( Node -> getOperand ( i ) ) ; continue ; } SDLoc DL ( Node ) ; Ops . push_back ( SDValue ( DAG . getMachineNode ( AMDGPU :: S_MOV_B32 , DL , Node -> getOperand ( i ) . getValueType ( ) , Node -> getOperand ( i ) ) , 0 ) ) ; } DAG . UpdateNodeOperands ( Node , Ops ) ; return Node ; } </s>

Legalize target independent instructions ( e.g .


<s> bool P2FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = & MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || TRI -> needsStackRealignment ( MF ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static bool s390_function_ok_for_sibcall ( tree decl , tree exp ) { if ( TARGET_TPF_PROFILING ) return false ; if ( ! TARGET_64BIT && flag_pic && decl && ! targetm . binds_local_p ( decl ) ) return false ; return ! s390_call_saved_register_used ( exp ) ; } </s>

Return true if the given call expression can be turned into a sibling call . DECL holds the declaration of the function to be called whereas EXP is the call expression itself .


<s> void GCNPassConfig :: addPreSched2 ( ) { if ( TM -> getOptLevel ( ) > CodeGenOpt :: None ) addPass ( createSIShrinkInstructionsPass ( ) ) ; addPass ( & SIPostRABundlerID ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


"invalid name (\"%s\") in %<target(\"tune=\")%> pragma or attribute"

Handle the argument STR to the tune= target attribute . PRAGMA_OR_ATTR is used in potential error messages .


<s> bool AArch64InstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return false ; if ( I -> getOpcode ( ) == AArch64 :: SpeculationBarrierISBDSBEndBB || I -> getOpcode ( ) == AArch64 :: SpeculationBarrierSBEndBB ) { -- I ; } if ( ! isUnpredicatedTerminator ( * I ) ) return false ; MachineInstr * LastInst = & * I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { if ( isUncondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } if ( isCondBranchOpcode ( LastOpc ) ) { parseCondBranch ( LastInst , TBB , Cond ) ; return false ; } return true ; } MachineInstr * SecondLastInst = & * I ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; if ( AllowModify && isUncondBranchOpcode ( LastOpc ) ) { while ( isUncondBranchOpcode ( SecondLastOpc ) ) { LastInst -> eraseFromParent ( ) ; LastInst = SecondLastInst ; LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { TBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } else { SecondLastInst = & * I ; SecondLastOpc = SecondLastInst -> getOpcode ( ) ; } } } if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( * -- I ) ) return true ; if ( isCondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { parseCondBranch ( SecondLastInst , TBB , Cond ) ; FBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } if ( isUncondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { TBB = SecondLastInst -> getOperand ( 0 ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } if ( isIndirectBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return true ; } return true ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> void MipsTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_WRITE | MCSectionELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , MCSectionELF :: SHT_NOBITS , MCSectionELF :: SHF_WRITE | MCSectionELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s> SDValue HexagonTargetLowering :: LowerCallResult ( SDValue Chain , SDValue Glue , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SmallVectorImpl < SDValue > & OutVals , SDValue Callee ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; if ( Subtarget . useHVXOps ( ) ) CCInfo . AnalyzeCallResult ( Ins , RetCC_Hexagon_HVX ) ; else CCInfo . AnalyzeCallResult ( Ins , RetCC_Hexagon ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { SDValue RetVal ; if ( RVLocs [ i ] . getValVT ( ) == MVT :: i1 ) { auto & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue FR0 = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , MVT :: i32 , Glue ) ; Register PredR = MRI . createVirtualRegister ( & Hexagon :: PredRegsRegClass ) ; SDValue TPR = DAG . getCopyToReg ( FR0 . getValue ( 1 ) , dl , PredR , FR0 . getValue ( 0 ) , FR0 . getValue ( 2 ) ) ; RetVal = DAG . getCopyFromReg ( TPR . getValue ( 0 ) , dl , PredR , MVT :: i1 ) ; Glue = TPR . getValue ( 1 ) ; Chain = TPR . getValue ( 0 ) ; } else { RetVal = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , Glue ) ; Glue = RetVal . getValue ( 2 ) ; Chain = RetVal . getValue ( 1 ) ; } InVals . push_back ( RetVal . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> bool ARCRegisterInfo :: needsFrameMoves ( const MachineFunction & MF ) { return MF . getMMI ( ) . hasDebugInfo ( ) || MF . getFunction ( ) -> needsUnwindTableEntry ( ) ; } </s>


<s>
void
HexagonAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
MCInst
MCB
;
MCB
.
setOpcode
(
Hexagon
::
BUNDLE
)
;
MCB
.
addOperand
(
MCOperand
::
createImm
(
0
)
)
;
const
MCInstrInfo
&
MCII
=
*
Subtarget
->
getInstrInfo
(
)
;
if
(
MI
->
isBundle
(
)
)
{
assert
(
Subtarget
->
usePackets
(
)
&&
"Support for packets is disabled"
)
;
const
MachineBasicBlock
*
MBB
=
MI
->
getParent
(
)
;
MachineBasicBlock
::
const_instr_iterator
MII
=
MI
->
getIterator
(
)
;
for
(
++
MII
;
MII
!=
MBB
->
instr_end
(
)
&&
MII
->
isInsideBundle
(
)
;
++
MII
)
if
(
!
MII
->
isDebugValue
(
)
&&
!
MII
->
isImplicitDef
(
)
)
HexagonLowerToMC
(
MCII
,
&
*
MII
,
MCB
,
*
this
)
;
}
else
{
HexagonLowerToMC
(
MCII
,
MI
,
MCB
,
*
this
)
;
}
const
MachineFunction
&
MF
=
*
MI
->
getParent
(
)
->
getParent
(
)
;
const
auto
&
HII
=
*
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getInstrInfo
(
)
;
if
(
MI
->
isBundle
(
)
&&
HII
.
getBundleNoShuf
(
*
MI
)
)
HexagonMCInstrInfo
::
setMemReorderDisabled
(
MCB
)
;
MCContext
&
Ctx
=
OutStreamer
->
getContext
(
)
;
bool
Ok
=
HexagonMCInstrInfo
::
canonicalizePacket
(
MCII
,
*
Subtarget
,
Ctx
,
MCB
,
nullptr
)
;
assert
(
Ok
)
;
(
void
)
Ok
;
if
(
HexagonMCInstrInfo
::
bundleSize
(
MCB
)
==
0
)
return
;
OutStreamer
->
EmitInstruction
(
MCB
,
getSubtargetInfo
(
)
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .

Hexagon
Hexagon
Hexagon::BUNDLE
0
"Support for packets is disabled"
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
0


<s> int ia64_register_move_cost ( enum machine_mode mode , enum reg_class from , enum reg_class to ) { if ( to == ADDL_REGS ) to = GR_REGS ; if ( from == ADDL_REGS ) from = GR_REGS ; if ( from < to ) { enum reg_class tmp = to ; to = from , from = tmp ; } if ( mode == XFmode || mode == RFmode ) { if ( to != GR_REGS || from != GR_REGS ) return MEMORY_MOVE_COST ( mode , to , 0 ) ; else return 3 ; } switch ( to ) { case PR_REGS : if ( from == PR_REGS ) return 3 ; if ( from != GR_REGS ) return MEMORY_MOVE_COST ( mode , to , 0 ) ; break ; case BR_REGS : if ( from != GR_REGS && from != GR_AND_BR_REGS ) return MEMORY_MOVE_COST ( mode , to , 0 ) ; break ; case AR_I_REGS : case AR_M_REGS : if ( from != GR_REGS ) return MEMORY_MOVE_COST ( mode , to , 0 ) ; break ; case GR_REGS : case FR_REGS : case FP_REGS : case GR_AND_FR_REGS : case GR_AND_BR_REGS : case ALL_REGS : break ; default : gcc_unreachable ( ) ; } return 2 ; } </s>

Calulate the cost of moving data from a register in class FROM to one in class TO , using MODE .


<s> unsigned X86AsmBackend :: getMaximumNopSize ( ) const { if ( ! STI . hasFeature ( X86 :: FeatureNOPL ) && ! STI . hasFeature ( X86 :: Mode64Bit ) ) return 1 ; if ( STI . getFeatureBits ( ) [ X86 :: FeatureFast7ByteNOP ] ) return 7 ; if ( STI . getFeatureBits ( ) [ X86 :: FeatureFast15ByteNOP ] ) return 15 ; if ( STI . getFeatureBits ( ) [ X86 :: FeatureFast11ByteNOP ] ) return 11 ; return 10 ; } </s>

Returns the maximum size of a nop in bytes on this target .


Implement TARGET_MAX_NOCE_IFCVT_SEQ_COST . Like the default implementation , but returns a lower bound .


<s> gimple * fold ( gimple_folder & f ) const override { if ( tree amount = uniform_integer_cst_p ( gimple_call_arg ( f . call , 2 ) ) ) { if ( wi :: to_widest ( amount ) >= 0 ) { function_instance instance ( "svlsl" , functions :: svlsl , shapes :: binary_uint_opt_n , MODE_n , f . type_suffix_ids , f . pred ) ; gcall * call = as_a < gcall * > ( f . redirect_call ( instance ) ) ; gimple_call_set_arg ( call , 2 , amount ) ; return call ; } int element_bits = f . type_suffix ( 0 ) . element_bits ; if ( wi :: to_widest ( amount ) >= - element_bits ) { amount = wide_int_to_tree ( TREE_TYPE ( amount ) , - wi :: to_wide ( amount ) ) ; function_instance instance ( "svrshr" , functions :: svrshr , shapes :: shift_right_imm , MODE_n , f . type_suffix_ids , f . pred ) ; gcall * call = as_a < gcall * > ( f . redirect_call ( instance ) ) ; gimple_call_set_arg ( call , 2 , amount ) ; return call ; } } return NULL ; } </s>

Try to fold the call . Return the new statement on success and null on failure .


<s> static int frame_restore_reg ( rtx reg , HOST_WIDE_INT offset ) { rtx addr , insn ; if ( offset ) { rtx tmp = plus_constant ( Pmode , stack_pointer_rtx , offset + GET_MODE_SIZE ( GET_MODE ( reg ) ) ) ; addr = gen_frame_mem ( GET_MODE ( reg ) , gen_rtx_POST_MODIFY ( Pmode , stack_pointer_rtx , tmp ) ) ; } else addr = gen_frame_mem ( GET_MODE ( reg ) , gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ) ; insn = frame_move_inc ( reg , addr , stack_pointer_rtx , 0 ) ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; if ( reg == hard_frame_pointer_rtx ) add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , stack_pointer_rtx , GET_MODE_SIZE ( GET_MODE ( reg ) ) + offset ) ) ; else add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , GET_MODE_SIZE ( GET_MODE ( reg ) ) + offset ) ) ) ; return GET_MODE_SIZE ( GET_MODE ( reg ) ) + offset ; } </s>

Helper for epilogue : emit frame load with post_modify or post_inc to restore register REG from stack . The initial offset is passed via OFFSET .


"After expanding ARM pseudo instructions."

runOnMachineFunction - Emit the function body .


<s> unsigned SystemZInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { if ( MI . getOpcode ( ) == TargetOpcode :: INLINEASM ) { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } return MI . getDesc ( ) . getSize ( ) ; } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> rtx alpha_legitimize_reload_address ( rtx x , machine_mode mode ATTRIBUTE_UNUSED , int opnum , int type , int ind_levels ATTRIBUTE_UNUSED ) { if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && REG_P ( XEXP ( XEXP ( x , 0 ) , 0 ) ) && CONST_INT_P ( XEXP ( XEXP ( x , 0 ) , 1 ) ) && CONST_INT_P ( XEXP ( x , 1 ) ) ) { push_reload ( XEXP ( x , 0 ) , NULL_RTX , & XEXP ( x , 0 ) , NULL , BASE_REG_CLASS , GET_MODE ( x ) , VOIDmode , 0 , 0 , opnum , ( enum reload_type ) type ) ; return x ; } if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , 0 ) ) && REGNO ( XEXP ( x , 0 ) ) < FIRST_PSEUDO_REGISTER && REGNO_OK_FOR_BASE_P ( REGNO ( XEXP ( x , 0 ) ) ) && CONST_INT_P ( XEXP ( x , 1 ) ) ) { HOST_WIDE_INT val = INTVAL ( XEXP ( x , 1 ) ) ; HOST_WIDE_INT low = ( ( val & 0xffff ) ^ 0x8000 ) - 0x8000 ; HOST_WIDE_INT high = ( ( ( val - low ) & 0xffffffff ) ^ 0x80000000 ) - 0x80000000 ; if ( high + low != val ) return NULL_RTX ; x = gen_rtx_PLUS ( GET_MODE ( x ) , gen_rtx_PLUS ( GET_MODE ( x ) , XEXP ( x , 0 ) , GEN_INT ( high ) ) , GEN_INT ( low ) ) ; push_reload ( XEXP ( x , 0 ) , NULL_RTX , & XEXP ( x , 0 ) , NULL , BASE_REG_CLASS , GET_MODE ( x ) , VOIDmode , 0 , 0 , opnum , ( enum reload_type ) type ) ; return x ; } return NULL_RTX ; } </s>

Try a machine-dependent way of reloading an illegitimate address operand . If we find one , push the reload and return the new rtx .


<s> MCSection * getSectionForConstant ( SectionKind Kind , const Constant * C ) const override { return ReadOnlySection ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> void MipsTargetELFStreamer :: emitAssignment ( MCSymbol * S , const MCExpr * Value ) { auto * Symbol = cast < MCSymbolELF > ( S ) ; if ( Value -> getKind ( ) != MCExpr :: SymbolRef ) return ; const auto & RhsSym = cast < MCSymbolELF > ( static_cast < const MCSymbolRefExpr * > ( Value ) -> getSymbol ( ) ) ; if ( ! ( RhsSym . getOther ( ) & ELF :: STO_MIPS_MICROMIPS ) ) return ; Symbol -> setOther ( ELF :: STO_MIPS_MICROMIPS ) ; } </s>


<s> static inline void aarch64_sub_sp ( rtx temp1 , rtx temp2 , poly_int64 delta , bool frame_related_p ) { aarch64_add_offset ( Pmode , stack_pointer_rtx , stack_pointer_rtx , - delta , temp1 , temp2 , frame_related_p ) ; } </s>

Subtract DELTA from the stack pointer , marking the instructions frame-related if FRAME_RELATED_P . TEMP1 is available as a temporary if nonnull .


<s> void i386_pe_encode_section_info ( tree decl , rtx rtl , int first ) { rtx symbol ; int flags ; default_encode_section_info ( decl , rtl , first ) ; if ( ! MEM_P ( rtl ) ) return ; symbol = XEXP ( rtl , 0 ) ; gcc_assert ( GET_CODE ( symbol ) == SYMBOL_REF ) ; switch ( TREE_CODE ( decl ) ) { case FUNCTION_DECL : case VAR_DECL : break ; default : return ; } flags = ( SYMBOL_REF_FLAGS ( symbol ) & ~ ( SYMBOL_FLAG_DLLIMPORT | SYMBOL_FLAG_DLLEXPORT ) ) ; if ( i386_pe_determine_dllexport_p ( decl ) ) flags |= SYMBOL_FLAG_DLLEXPORT ; else if ( i386_pe_determine_dllimport_p ( decl ) ) flags |= SYMBOL_FLAG_DLLIMPORT ; SYMBOL_REF_FLAGS ( symbol ) = flags ; } </s>

Cover function to implement ENCODE_SECTION_INFO .


"JIT does not support pseudo instruction GETPCX yet!"

Targets should implement this to emit instructions .


<s> static rtx mips_expand_builtin_bposge ( enum mips_builtin_type builtin_type , rtx target ) { rtx label1 , label2 , if_then_else ; rtx cmp_result ; int cmp_value ; if ( target == 0 || GET_MODE ( target ) != SImode ) target = gen_reg_rtx ( SImode ) ; cmp_result = gen_rtx_REG ( CCDSPmode , CCDSP_PO_REGNUM ) ; if ( builtin_type == MIPS_BUILTIN_BPOSGE32 ) cmp_value = 32 ; else gcc_assert ( 0 ) ; emit_move_insn ( target , const0_rtx ) ; label1 = gen_label_rtx ( ) ; label2 = gen_label_rtx ( ) ; if_then_else = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( GE , CCDSPmode , cmp_result , GEN_INT ( cmp_value ) ) , gen_rtx_LABEL_REF ( VOIDmode , label1 ) , pc_rtx ) ; emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , if_then_else ) ) ; emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_LABEL_REF ( VOIDmode , label2 ) ) ) ; emit_barrier ( ) ; emit_label ( label1 ) ; emit_move_insn ( target , const1_rtx ) ; emit_label ( label2 ) ; return target ; } </s>

Expand a bposge builtin of type BUILTIN_TYPE . TARGET , if nonnull , suggests a good place to put the boolean result . The sequence we want is li target , 0 bposge * label1 j label2 label1 : li target , 1 label2 :


<s> static inline int addsubcosts ( rtx x ) { if ( GET_MODE ( x ) == SImode ) { rtx op0 = XEXP ( x , 0 ) ; rtx op1 = XEXP ( x , 1 ) ; if ( GET_CODE ( x ) == PLUS ) { if ( GET_CODE ( op0 ) == AND && XEXP ( op0 , 1 ) == const1_rtx && ( GET_CODE ( op1 ) == PLUS || ( GET_CODE ( op1 ) == MULT && XEXP ( op1 , 1 ) == const2_rtx ) ) ) return 1 ; if ( GET_CODE ( op0 ) == MULT && XEXP ( op0 , 1 ) == const2_rtx && GET_CODE ( op1 ) == LSHIFTRT && CONST_INT_P ( XEXP ( op1 , 1 ) ) && INTVAL ( XEXP ( op1 , 1 ) ) == 31 ) return 1 ; } if ( treg_set_expr ( op1 , SImode ) ) return 1 ; if ( treg_set_expr ( op0 , SImode ) ) return 1 ; } const int cost_scale = GET_MODE_SIZE ( GET_MODE ( x ) ) > UNITS_PER_WORD ? 2 : 1 ; if ( REG_P ( XEXP ( x , 1 ) ) || GET_CODE ( XEXP ( x , 1 ) ) == SUBREG ) return 1 * cost_scale ; if ( CONST_INT_P ( XEXP ( x , 1 ) ) && CONST_OK_FOR_ADD ( INTVAL ( XEXP ( x , 1 ) ) ) ) return 1 * cost_scale ; return 3 * cost_scale ; } </s>

Return the cost of an addition or a subtraction .


<s> bool isImm ( ) const { return Kind == MachineOperand :: MO_Immediate ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool M88kFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , MutableArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { return false ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> void BTFDebug :: endModule ( ) { if ( MapDefNotCollected ) { processGlobals ( true ) ; MapDefNotCollected = false ; } processGlobals ( false ) ; for ( auto & DataSec : DataSecEntries ) addType ( std :: move ( DataSec . second ) ) ; for ( auto & Fixup : FixupDerivedTypes ) { StringRef TypeName = Fixup . first ; bool IsUnion = Fixup . second . first ; uint32_t StructTypeId = 0 ; for ( const auto & StructType : StructTypes ) { if ( StructType -> getName ( ) == TypeName ) { StructTypeId = StructType -> getId ( ) ; break ; } } if ( StructTypeId == 0 ) { auto FwdTypeEntry = std :: make_unique < BTFTypeFwd > ( TypeName , IsUnion ) ; StructTypeId = addType ( std :: move ( FwdTypeEntry ) ) ; } for ( auto & DType : Fixup . second . second ) { DType -> setPointeeType ( StructTypeId ) ; } } for ( const auto & TypeEntry : TypeEntries ) TypeEntry -> completeType ( * this ) ; emitBTFSection ( ) ; emitBTFExtSection ( ) ; } </s>

Emit all exception information that should come after the content .


<s> static bool rs6000_expand_vec_perm_const_1 ( rtx target , rtx op0 , rtx op1 , unsigned char perm0 , unsigned char perm1 ) { rtx x ; if ( ( perm0 & 2 ) == ( perm1 & 2 ) ) { if ( perm0 & 2 ) op0 = op1 ; else op1 = op0 ; } if ( rtx_equal_p ( op0 , op1 ) ) { perm0 = perm0 & 1 ; perm1 = ( perm1 & 1 ) + 2 ; } else if ( perm0 & 2 ) { if ( perm1 & 2 ) return false ; perm0 -= 2 ; perm1 += 2 ; std :: swap ( op0 , op1 ) ; } else if ( ( perm1 & 2 ) == 0 ) return false ; if ( target != NULL ) { machine_mode vmode , dmode ; rtvec v ; vmode = GET_MODE ( target ) ; gcc_assert ( GET_MODE_NUNITS ( vmode ) == 2 ) ; dmode = mode_for_vector ( GET_MODE_INNER ( vmode ) , 4 ) ; x = gen_rtx_VEC_CONCAT ( dmode , op0 , op1 ) ; v = gen_rtvec ( 2 , GEN_INT ( perm0 ) , GEN_INT ( perm1 ) ) ; x = gen_rtx_VEC_SELECT ( vmode , x , gen_rtx_PARALLEL ( VOIDmode , v ) ) ; emit_insn ( gen_rtx_SET ( target , x ) ) ; } return true ; } </s>

Expand a Paired Single or VSX Permute Doubleword constant permutation . Return true if we match an efficient implementation .


<s> void MipsTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { Known . resetAll ( ) ; switch ( Op . getOpcode ( ) ) { default : break ; case ISD :: INTRINSIC_WO_CHAIN : { switch ( cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ) { default : break ; case Intrinsic :: cheri_round_representable_length : if ( Subtarget . isCheri256 ( ) ) { Known = DAG . computeKnownBits ( Op . getOperand ( 1 ) ) ; } else if ( Subtarget . isCheri128 ( ) ) { KnownBits KnownLengthBits = DAG . computeKnownBits ( Op . getOperand ( 1 ) ) ; uint64_t MinLength = KnownLengthBits . One . getZExtValue ( ) ; uint64_t MaxLength = ( ~ KnownLengthBits . Zero ) . getZExtValue ( ) ; uint64_t MinMask = cc128_get_alignment_mask ( MinLength ) ; uint64_t MaxMask = cc128_get_alignment_mask ( MaxLength ) ; uint64_t MinRoundedLength = ( MinLength + ~ MinMask ) & MinMask ; uint64_t MaxRoundedLength = ( MaxLength + ~ MaxMask ) & MaxMask ; bool MinRoundedOverflow = MinRoundedLength < MinLength ; bool MaxRoundedOverflow = MaxRoundedLength < MaxLength ; uint64_t MinMaxRoundedAgreeMask = MinRoundedLength ^ ~ MaxRoundedLength ; uint64_t InputKnownMask = ( KnownLengthBits . Zero | KnownLengthBits . One ) . getZExtValue ( ) ; uint64_t LeadingKnownBits = countLeadingOnes ( MinMaxRoundedAgreeMask ) ; uint64_t LeadingKnownMask = MinRoundedOverflow == MaxRoundedOverflow ? maskLeadingOnes < uint64_t > ( LeadingKnownBits ) : 0 ; uint64_t TrailingKnownBits = countTrailingOnes ( MinMaxRoundedAgreeMask ) ; uint64_t TrailingKnownMask = maskTrailingOnes < uint64_t > ( TrailingKnownBits ) & InputKnownMask ; uint64_t KnownMask = LeadingKnownMask | TrailingKnownMask ; Known . Zero |= ~ MinRoundedLength & KnownMask ; Known . One |= MinRoundedLength & KnownMask ; } break ; case Intrinsic :: cheri_representable_alignment_mask : if ( Subtarget . isCheri256 ( ) ) { Known . setAllOnes ( ) ; } else if ( Subtarget . isCheri128 ( ) ) { KnownBits KnownLengthBits = DAG . computeKnownBits ( Op . getOperand ( 1 ) ) ; uint64_t MinLength = KnownLengthBits . One . getZExtValue ( ) ; uint64_t MaxLength = ( ~ KnownLengthBits . Zero ) . getZExtValue ( ) ; Known . Zero |= ~ cc128_get_alignment_mask ( MinLength ) ; Known . One |= cc128_get_alignment_mask ( MaxLength ) ; } break ; } } } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> bool Thumb1FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; bool isVarArg = AFI -> getArgRegsSaveSize ( ) > 0 ; DebugLoc DL = MI != MBB . end ( ) ? MI -> getDebugLoc ( ) : DebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , TII . get ( ARM :: tPOP ) ) ; AddDefaultPred ( MIB ) ; bool NeedsPop = false ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( Reg == ARM :: LR ) { if ( MBB . succ_empty ( ) ) { if ( isVarArg ) continue ; if ( ! STI . hasV5TOps ( ) ) continue ; Reg = ARM :: PC ; ( * MIB ) . setDesc ( TII . get ( ARM :: tPOP_RET ) ) ; if ( MI != MBB . end ( ) ) MIB . copyImplicitOps ( * MI ) ; MI = MBB . erase ( MI ) ; } else continue ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; NeedsPop = true ; } if ( NeedsPop ) MBB . insert ( MI , & * MIB ) ; else MF . DeleteMachineInstr ( MIB ) ; return true ; } </s>


<s> SDValue GBZ80TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : return PerformADDCombine ( N , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> void X86InstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , unsigned SubIdx , const MachineInstr * Orig , const TargetRegisterInfo & TRI ) const { DebugLoc DL = Orig -> getDebugLoc ( ) ; bool Clone = true ; unsigned Opc = Orig -> getOpcode ( ) ; switch ( Opc ) { default : break ; case X86 :: MOV8r0 : case X86 :: MOV16r0 : case X86 :: MOV32r0 : case X86 :: MOV64r0 : { if ( ! isSafeToClobberEFLAGS ( MBB , I ) ) { switch ( Opc ) { default : break ; case X86 :: MOV8r0 : Opc = X86 :: MOV8ri ; break ; case X86 :: MOV16r0 : Opc = X86 :: MOV16ri ; break ; case X86 :: MOV32r0 : Opc = X86 :: MOV32ri ; break ; case X86 :: MOV64r0 : Opc = X86 :: MOV64ri64i32 ; break ; } Clone = false ; } break ; } } if ( Clone ) { MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( Orig ) ; MBB . insert ( I , MI ) ; } else { BuildMI ( MBB , I , DL , get ( Opc ) ) . addOperand ( Orig -> getOperand ( 0 ) ) . addImm ( 0 ) ; } MachineInstr * NewMI = prior ( I ) ; NewMI -> substituteRegister ( Orig -> getOperand ( 0 ) . getReg ( ) , DestReg , SubIdx , TRI ) ; } </s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s> static bool ix86_lea_outperforms ( rtx_insn * insn , unsigned int regno0 , unsigned int regno1 , unsigned int regno2 , int split_cost , bool has_scale ) { int dist_define , dist_use ; if ( TARGET_SILVERMONT || TARGET_GOLDMONT || TARGET_GOLDMONT_PLUS || TARGET_TREMONT || TARGET_INTEL ) { if ( has_scale ) return true ; if ( split_cost < 1 ) return false ; if ( regno0 == regno1 || regno0 == regno2 ) return false ; return true ; } dist_define = distance_non_agu_define ( regno1 , regno2 , insn ) ; dist_use = distance_agu_use ( regno0 , insn ) ; if ( dist_define < 0 || dist_define >= LEA_MAX_STALL ) { if ( dist_use < 0 && split_cost == 0 ) return TARGET_64BIT || IX86_LEA_PRIORITY ; else return true ; } dist_define += split_cost + IX86_LEA_PRIORITY ; if ( dist_use < 0 ) return dist_define > LEA_MAX_STALL ; return dist_define >= dist_use ; } </s>

Return true if usage of lea INSN has performance advantage over a sequence of instructions . Instructions sequence has SPLIT_COST cycles higher latency than lea latency .


<s> static const char * s390_mangle_type ( const_tree type ) { type = TYPE_MAIN_VARIANT ( type ) ; if ( TREE_CODE ( type ) != VOID_TYPE && TREE_CODE ( type ) != BOOLEAN_TYPE && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE ) return NULL ; if ( type == s390_builtin_types [ BT_BV16QI ] ) return "U6__boolc" ; if ( type == s390_builtin_types [ BT_BV8HI ] ) return "U6__bools" ; if ( type == s390_builtin_types [ BT_BV4SI ] ) return "U6__booli" ; if ( type == s390_builtin_types [ BT_BV2DI ] ) return "U6__booll" ; if ( type == long_double_type_node && TARGET_LONG_DOUBLE_128 ) return "g" ; return NULL ; } </s>


"This eliminateFrameIndex does not support Thumb1!"

"Instr doesn't have FrameIndex operand!"

"This code isn't needed if offset already handled!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> static bool mn10300_handle_option ( size_t code , const char * arg ATTRIBUTE_UNUSED , int value ) { switch ( code ) { case OPT_mam33 : mn10300_processor = value ? PROCESSOR_AM33 : PROCESSOR_MN10300 ; return true ; case OPT_mam33_2 : mn10300_processor = ( value ? PROCESSOR_AM33_2 : MIN ( PROCESSOR_AM33 , PROCESSOR_DEFAULT ) ) ; return true ; default : return true ; } } </s>


<s> bool AMDGPUTargetLowering :: shouldReduceLoadWidth ( SDNode * N , ISD :: LoadExtType , EVT NewVT ) const { unsigned NewSize = NewVT . getStoreSizeInBits ( ) ; if ( NewSize == 32 ) return true ; EVT OldVT = N -> getValueType ( 0 ) ; unsigned OldSize = OldVT . getStoreSizeInBits ( ) ; MemSDNode * MN = cast < MemSDNode > ( N ) ; unsigned AS = MN -> getAddressSpace ( ) ; if ( OldSize >= 32 && NewSize < 32 && MN -> getAlignment ( ) >= 4 && ( AS == AMDGPUAS :: CONSTANT_ADDRESS || AS == AMDGPUAS :: CONSTANT_ADDRESS_32BIT || ( isa < LoadSDNode > ( N ) && AS == AMDGPUAS :: GLOBAL_ADDRESS && MN -> isInvariant ( ) ) ) && AMDGPUInstrInfo :: isUniformMMO ( MN -> getMemOperand ( ) ) ) return false ; return ( OldSize < 32 ) ; } </s>

Return true if we believe it is correct and profitable to reduce the load node to a smaller type .


<s> bool SIInstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { return TargetInstrInfo :: isSchedulingBoundary ( MI , MBB , MF ) || MI . modifiesRegister ( AMDGPU :: EXEC , & RI ) ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> void m68hc11_notice_update_cc ( rtx exp , rtx insn ATTRIBUTE_UNUSED ) { if ( GET_CODE ( exp ) == SET ) { if ( SET_DEST ( exp ) == pc_rtx ) ; else if ( GET_CODE ( SET_SRC ( exp ) ) == CALL ) { CC_STATUS_INIT ; } else if ( SET_DEST ( exp ) == cc0_rtx ) { cc_status . flags = 0 ; cc_status . value1 = XEXP ( exp , 0 ) ; cc_status . value2 = XEXP ( exp , 1 ) ; } else { cc_status . flags = 0 ; cc_status . value1 = XEXP ( exp , 0 ) ; cc_status . value2 = XEXP ( exp , 1 ) ; } } else { CC_STATUS_INIT ; } if ( cc_status . value2 != 0 ) switch ( GET_CODE ( cc_status . value2 ) ) { case IOR : case XOR : case AND : break ; case NOT : if ( GET_MODE ( cc_status . value2 ) != QImode ) CC_STATUS_INIT ; break ; case PLUS : case MINUS : case MULT : case DIV : case UDIV : case MOD : case UMOD : case NEG : if ( GET_MODE ( cc_status . value2 ) != VOIDmode ) cc_status . flags |= CC_NO_OVERFLOW ; break ; case ASHIFT : case ROTATE : case ROTATERT : if ( GET_MODE ( cc_status . value2 ) != VOIDmode ) cc_status . flags |= CC_NO_OVERFLOW ; break ; case MEM : case SYMBOL_REF : case REG : case CONST_INT : cc_status . flags |= CC_NO_OVERFLOW ; break ; default : break ; } if ( cc_status . value1 && GET_CODE ( cc_status . value1 ) == REG && cc_status . value2 && reg_overlap_mentioned_p ( cc_status . value1 , cc_status . value2 ) ) cc_status . value2 = 0 ; else if ( cc_status . value1 && side_effects_p ( cc_status . value1 ) ) cc_status . value1 = 0 ; else if ( cc_status . value2 && side_effects_p ( cc_status . value2 ) ) cc_status . value2 = 0 ; } </s>

Store in cc_status the expressions that the condition codes will describe after execution of an instruction whose pattern is EXP . Do not alter them if the instruction would not alter the cc 's .


<s> void FISCFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; uint64_t StackSize = computeStackSize ( MF ) ; if ( ! StackSize ) return ; unsigned StackReg = FISC :: SP ; unsigned OffsetReg = materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ; if ( OffsetReg ) { BuildMI ( MBB , MBBI , dl , TII . get ( FISC :: ADDrr ) , StackReg ) . addReg ( StackReg ) . addReg ( OffsetReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( FISC :: ADDri ) , StackReg ) . addReg ( StackReg ) . addImm ( StackSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } } </s>

FISC FISC FISC::SP FISC::ADDrr FISC::ADDri


<s> bool MipsAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; printOperand ( MI , OpNo ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> const UPTRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void SparcInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & O ) { if ( ! printAliasInstr ( MI , Address , STI , O ) && ! printSparcAliasInstr ( MI , STI , O ) ) printInstruction ( MI , Address , STI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> uint16_t getDiscriminator ( ) const { return Discriminator ; } </s>

Get the Discriminator of this MCDwarfLoc .


<s> int s390_label_align ( rtx label ) { rtx_insn * prev_insn = prev_active_insn ( label ) ; rtx set , src ; if ( prev_insn == NULL_RTX ) goto old ; set = single_set ( prev_insn ) ; if ( set == NULL_RTX ) goto old ; src = SET_SRC ( set ) ; if ( GET_CODE ( src ) == UNSPEC && XINT ( src , 1 ) == UNSPEC_MAIN_BASE ) return 0 ; old : return align_labels_log ; } </s>

Return the alignment for LABEL . We default to the -falign-labels value except for the literal pool base label .


<s> static void replace_swapped_aligned_store ( swap_web_entry * insn_entry , rtx_insn * store_insn ) { unsigned uid = INSN_UID ( store_insn ) ; gcc_assert ( insn_entry [ uid ] . is_swap && insn_entry [ uid ] . is_store ) ; rtx body = PATTERN ( store_insn ) ; rtx dest_address = XEXP ( SET_DEST ( body ) , 0 ) ; rtx swap_reg = XEXP ( SET_SRC ( body ) , 0 ) ; gcc_assert ( REG_P ( dest_address ) || rs6000_sum_of_two_registers_p ( dest_address ) ) ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( store_insn ) ; df_ref use ; rtx_insn * swap_insn = NULL ; unsigned uid2 = 0 ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( ! rtx_equal_p ( DF_REF_REG ( use ) , swap_reg ) ) continue ; gcc_assert ( def_link && def_link -> ref && ! def_link -> next && ! DF_REF_IS_ARTIFICIAL ( def_link -> ref ) ) ; swap_insn = DF_REF_INSN ( def_link -> ref ) ; uid2 = INSN_UID ( swap_insn ) ; gcc_assert ( insn_entry [ uid2 ] . is_swap && ! insn_entry [ uid2 ] . is_load && ! insn_entry [ uid2 ] . is_store ) ; break ; } gcc_assert ( swap_insn ) ; rtx set = single_set ( store_insn ) ; gcc_assert ( set ) ; rtx dest_exp = SET_DEST ( set ) ; rtx src_exp = XEXP ( SET_SRC ( body ) , 0 ) ; enum machine_mode mode = GET_MODE ( dest_exp ) ; gcc_assert ( MEM_P ( dest_exp ) ) ; gcc_assert ( MEM_ALIGN ( dest_exp ) >= 128 ) ; rtx stvx ; stvx = rs6000_gen_stvx ( mode , dest_exp , src_exp ) ; rtx_insn * new_insn = emit_insn_before ( stvx , store_insn ) ; rtx new_body = PATTERN ( new_insn ) ; gcc_assert ( ( GET_CODE ( new_body ) == SET ) && MEM_P ( SET_DEST ( new_body ) ) ) ; basic_block bb = BLOCK_FOR_INSN ( store_insn ) ; set_block_for_insn ( new_insn , bb ) ; if ( cfun -> can_throw_non_call_exceptions && BB_END ( bb ) == store_insn ) { rtx note = find_reg_note ( store_insn , REG_EH_REGION , NULL_RTX ) ; if ( note ) add_reg_note ( new_insn , REG_EH_REGION , XEXP ( note , 0 ) ) ; } df_insn_rescan ( new_insn ) ; df_insn_delete ( store_insn ) ; remove_insn ( store_insn ) ; store_insn -> set_deleted ( ) ; uid2 = INSN_UID ( swap_insn ) ; mark_swaps_for_removal ( insn_entry , uid2 ) ; replace_swap_with_copy ( insn_entry , uid2 ) ; } </s>

Given that STORE_INSN represents an aligned store-with-swap of a swapped value , replace the store with an aligned store ( without swap ) and replace the swap with a copy insn .


"%<__BELOW100__%> attribute only applies to variables"

"%<__BELOW100__%> attribute not allowed "

Handle an `` below '' attribute ; arguments as in struct attribute_spec.handler .


<s> void AArch64FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { if ( ! MF . hasEHFunclets ( ) ) return ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; WinEHFuncInfo & EHInfo = * MF . getWinEHFuncInfo ( ) ; MachineBasicBlock & MBB = MF . front ( ) ; auto MBBI = MBB . begin ( ) ; while ( MBBI != MBB . end ( ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) ) ++ MBBI ; if ( MBBI -> isTerminator ( ) ) return ; int UnwindHelpFI = MFI . CreateStackObject ( 8 , 16 , false ) ; EHInfo . UnwindHelpFrameIdx = UnwindHelpFI ; DebugLoc DL ; RS -> enterBasicBlock ( MBB ) ; unsigned DstReg = RS -> scavengeRegister ( & AArch64 :: GPR64RegClass , MBBI , 0 ) ; BuildMI ( MBB , MBBI , DL , TII . get ( AArch64 :: MOVi64imm ) , DstReg ) . addImm ( - 2 ) ; BuildMI ( MBB , MBBI , DL , TII . get ( AArch64 :: STURXi ) ) . addReg ( DstReg , getKillRegState ( true ) ) . addFrameIndex ( UnwindHelpFI ) . addImm ( 0 ) ; } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s>
PPC
::
Predicate
PPC
::
getSwappedPredicate
(
PPC
::
Predicate
Opcode
)
{
switch
(
Opcode
)
{
case
PPC
::
PRED_EQ
:
return
PPC
::
PRED_EQ
;
case
PPC
::
PRED_NE
:
return
PPC
::
PRED_NE
;
case
PPC
::
PRED_LT
:
return
PPC
::
PRED_GT
;
case
PPC
::
PRED_GE
:
return
PPC
::
PRED_LE
;
case
PPC
::
PRED_GT
:
return
PPC
::
PRED_LT
;
case
PPC
::
PRED_LE
:
return
PPC
::
PRED_GE
;
case
PPC
::
PRED_NU
:
return
PPC
::
PRED_NU
;
case
PPC
::
PRED_UN
:
return
PPC
::
PRED_UN
;
case
PPC
::
PRED_EQ_MINUS
:
return
PPC
::
PRED_EQ_MINUS
;
case
PPC
::
PRED_NE_MINUS
:
return
PPC
::
PRED_NE_MINUS
;
case
PPC
::
PRED_LT_MINUS
:
return
PPC
::
PRED_GT_MINUS
;
case
PPC
::
PRED_GE_MINUS
:
return
PPC
::
PRED_LE_MINUS
;
case
PPC
::
PRED_GT_MINUS
:
return
PPC
::
PRED_LT_MINUS
;
case
PPC
::
PRED_LE_MINUS
:
return
PPC
::
PRED_GE_MINUS
;
case
PPC
::
PRED_NU_MINUS
:
return
PPC
::
PRED_NU_MINUS
;
case
PPC
::
PRED_UN_MINUS
:
return
PPC
::
PRED_UN_MINUS
;
case
PPC
::
PRED_EQ_PLUS
:
return
PPC
::
PRED_EQ_PLUS
;
case
PPC
::
PRED_NE_PLUS
:
return
PPC
::
PRED_NE_PLUS
;
case
PPC
::
PRED_LT_PLUS
:
return
PPC
::
PRED_GT_PLUS
;
case
PPC
::
PRED_GE_PLUS
:
return
PPC
::
PRED_LE_PLUS
;
case
PPC
::
PRED_GT_PLUS
:
return
PPC
::
PRED_LT_PLUS
;
case
PPC
::
PRED_LE_PLUS
:
return
PPC
::
PRED_GE_PLUS
;
case
PPC
::
PRED_NU_PLUS
:
return
PPC
::
PRED_NU_PLUS
;
case
PPC
::
PRED_UN_PLUS
:
return
PPC
::
PRED_UN_PLUS
;
case
PPC
::
PRED_BIT_SET
:
case
PPC
::
PRED_BIT_UNSET
:
llvm_unreachable
(
"Invalid use of bit predicate code"
)
;
}
llvm_unreachable
(
"Unknown PPC branch opcode!"
)
;
}
</s>

This is a static version that you can use without an instruction available .


<s> static bool arm_evpc_neon_vuzp ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> perm . length ( ) ; rtx out0 , out1 , in0 , in1 ; int first_elem ; int swap_nelt ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; swap_nelt = BYTES_BIG_ENDIAN && ! d -> one_vector_p && GET_MODE_SIZE ( d -> vmode ) == 8 ? nelt : 0 ; first_elem = d -> perm [ neon_endian_lane_map ( d -> vmode , 0 ) ] ^ swap_nelt ; if ( first_elem == neon_endian_lane_map ( d -> vmode , 0 ) ) odd = 0 ; else if ( first_elem == neon_endian_lane_map ( d -> vmode , 1 ) ) odd = 1 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt ; i ++ ) { unsigned elt = ( neon_pair_endian_lane_map ( d -> vmode , i ) * 2 + odd ) & mask ; if ( ( d -> perm [ i ] ^ swap_nelt ) != neon_pair_endian_lane_map ( d -> vmode , elt ) ) return false ; } if ( d -> testing_p ) return true ; in0 = d -> op0 ; in1 = d -> op1 ; if ( swap_nelt != 0 ) std :: swap ( in0 , in1 ) ; out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( odd ) std :: swap ( out0 , out1 ) ; emit_insn ( gen_neon_vuzp_internal ( d -> vmode , out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s> Constant * AMDGPULibCalls :: getFunction ( Module * M , const FuncInfo & fInfo ) { return EnablePreLink ? AMDGPULibFunc :: getOrInsertFunction ( M , fInfo ) : AMDGPULibFunc :: getFunction ( M , fInfo ) ; } </s>

getFunction - Return this trace 's parent function .


<s> static rtx sh_function_arg ( cumulative_args_t ca_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * ca = get_cumulative_args ( ca_v ) ; machine_mode mode = arg . mode ; if ( arg . end_marker_p ( ) ) return ca -> renesas_abi ? const1_rtx : const0_rtx ; if ( sh_pass_in_reg_p ( * ca , mode , arg . type ) && ( arg . named || ! ( TARGET_HITACHI || ca -> renesas_abi ) ) ) { int regno ; if ( mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN && ( ! FUNCTION_ARG_SCmode_WART || ( sh_round_reg ( * ca , mode ) & 1 ) ) ) { rtx r1 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SFmode , BASE_ARG_REG ( mode ) + ( sh_round_reg ( * ca , mode ) ^ 1 ) ) , const0_rtx ) ; rtx r2 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SFmode , BASE_ARG_REG ( mode ) + ( ( sh_round_reg ( * ca , mode ) + 1 ) ^ 1 ) ) , GEN_INT ( 4 ) ) ; return gen_rtx_PARALLEL ( SCmode , gen_rtvec ( 2 , r1 , r2 ) ) ; } if ( ( TARGET_HITACHI || ca -> renesas_abi ) && ca -> free_single_fp_reg && mode == SFmode ) return gen_rtx_REG ( mode , ca -> free_single_fp_reg ) ; regno = ( BASE_ARG_REG ( mode ) + sh_round_reg ( * ca , mode ) ) ^ ( mode == SFmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN && ! TARGET_HITACHI && ! ca -> renesas_abi ) ; return gen_rtx_REG ( mode , regno ) ; } return NULL_RTX ; } </s>

Define where to put the arguments to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . On SH the first args are normally in registers and the rest are pushed . Any arg that starts within the first NPARM_REGS words is at least partially passed in a register unless its data type forbids .


<s>
void
RISCVMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
verifyInstructionPredicates
(
MI
,
computeAvailableFeatures
(
STI
.
getFeatureBits
(
)
)
)
;
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
unsigned
Size
=
Desc
.
getSize
(
)
;
if
(
MI
.
getOpcode
(
)
==
RISCV
::
PseudoCALLReg
||
MI
.
getOpcode
(
)
==
RISCV
::
PseudoCALL
||
MI
.
getOpcode
(
)
==
RISCV
::
PseudoTAIL
||
MI
.
getOpcode
(
)
==
RISCV
::
PseudoJump
)
{
expandFunctionCall
(
MI
,
OS
,
Fixups
,
STI
)
;
MCNumEmitted
+=
2
;
return
;
}
if
(
MI
.
getOpcode
(
)
==
RISCV
::
PseudoAddTPRel
)
{
expandAddTPRel
(
MI
,
OS
,
Fixups
,
STI
)
;
MCNumEmitted
+=
1
;
return
;
}
switch
(
Size
)
{
default
:
llvm_unreachable
(
"Unhandled encodeInstruction length!"
)
;
case
2
:
{
uint16_t
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
support
::
endian
::
write
<
uint16_t
>
(
OS
,
Bits
,
support
::
little
)
;
break
;
}
case
4
:
{
uint32_t
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
support
::
endian
::
write
(
OS
,
Bits
,
support
::
little
)
;
break
;
}
}
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .

RISCV
RISCV
RISCV::PseudoCALLReg
RISCV::PseudoCALL
RISCV::PseudoTAIL
RISCV::PseudoJump
2
RISCV::PseudoAddTPRel
1
"Unhandled encodeInstruction length!"
2
support::endian
support::little
4
support::endian
support::little


"Unmatched number of shufflevectors and indices"

Lower interleaved load ( s ) into target specific instructions/intrinsics .


<s>
void
Mips16InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
=
0
;
if
(
Mips
::
CPU16RegsRegClass
.
contains
(
DestReg
)
&&
Mips
::
GPR32RegClass
.
contains
(
SrcReg
)
)
Opc
=
Mips
::
MoveR3216
;
else
if
(
Mips
::
GPR32RegClass
.
contains
(
DestReg
)
&&
Mips
::
CPU16RegsRegClass
.
contains
(
SrcReg
)
)
Opc
=
Mips
::
Move32R16
;
else
if
(
(
SrcReg
==
Mips
::
HI0
)
&&
(
Mips
::
CPU16RegsRegClass
.
contains
(
DestReg
)
)
)
Opc
=
Mips
::
Mfhi16
,
SrcReg
=
0
;
else
if
(
(
SrcReg
==
Mips
::
LO0
)
&&
(
Mips
::
CPU16RegsRegClass
.
contains
(
DestReg
)
)
)
Opc
=
Mips
::
Mflo16
,
SrcReg
=
0
;
assert
(
Opc
&&
"Cannot copy registers"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
)
;
if
(
DestReg
)
MIB
.
addReg
(
DestReg
,
RegState
::
Define
)
;
if
(
SrcReg
)
MIB
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> void AArch64TargetStreamer :: finish ( ) { ConstantPools -> emitAll ( Streamer ) ; if ( MarkBTIProperty ) emitNoteSection ( ELF :: GNU_PROPERTY_AARCH64_FEATURE_1_BTI ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> void AArch64PassConfig :: addPreEmitPass ( ) { if ( PACStack :: doDummyPA ( ) ) addPass ( createAArch64DummyPA ( ) ) ; if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Aggressive && EnableLoadStoreOpt ) addPass ( createAArch64LoadStoreOptimizationPass ( ) ) ; if ( EnableA53Fix835769 ) addPass ( createAArch64A53Fix835769 ( ) ) ; if ( BranchRelaxation ) addPass ( & BranchRelaxationPassID ) ; if ( EnableBranchTargets ) addPass ( createAArch64BranchTargetsPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCompressJumpTables ) addPass ( createAArch64CompressJumpTablesPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


Implement TARGET_MODES_TIEABLE_P . Do n't allow floating-point modes to be tied , since type punning of single-precision and double-precision is implementation defined .


<s> void createdInstr ( MachineInstr & MI ) override { InstList . insert ( & MI ) ; } </s>

An instruction has been created and inserted into the function .


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) -> findAssociatedFragment ( ) ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


"instruction requires a CPU feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> static bool riscv_legitimate_address_p ( enum machine_mode mode , rtx x , bool strict_p ) { struct riscv_address_info addr ; return riscv_classify_address ( & addr , x , mode , strict_p ) ; } </s>


<s> bool HexagonInstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( MI . isDebugInstr ( ) ) return false ; if ( MI . isCall ( ) ) { if ( doesNotReturn ( MI ) ) return true ; for ( auto I : MBB -> successors ( ) ) if ( I -> isEHPad ( ) ) return true ; } if ( MI . getDesc ( ) . isTerminator ( ) || MI . isPosition ( ) ) return true ; if ( MI . isInlineAsm ( ) && ! ScheduleInlineAsm ) return true ; return false ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> int memory_reload_operand ( rtx operand , enum machine_mode mode ATTRIBUTE_UNUSED ) { return GET_CODE ( operand ) == MEM && GET_CODE ( XEXP ( operand , 0 ) ) == PLUS && ( ( GET_CODE ( XEXP ( XEXP ( operand , 0 ) , 0 ) ) == REG && GET_CODE ( XEXP ( XEXP ( operand , 0 ) , 1 ) ) == CONST_INT ) || ( GET_CODE ( XEXP ( XEXP ( operand , 0 ) , 1 ) ) == REG && GET_CODE ( XEXP ( XEXP ( operand , 0 ) , 0 ) ) == CONST_INT ) ) ; } </s>


<s> static int aarch64_simd_clone_usable ( struct cgraph_node * node ) { switch ( node -> simdclone -> vecsize_mangle ) { case 'n' : if ( ! TARGET_SIMD ) return - 1 ; return 0 ; default : gcc_unreachable ( ) ; } } </s>


"%qE attribute only applies to functions"


<s> bool X86FixupSetCCPass :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; MRI = & MF . getRegInfo ( ) ; TII = MF . getSubtarget < X86Subtarget > ( ) . getInstrInfo ( ) ; SmallVector < MachineInstr * , 4 > ToErase ; for ( auto & MBB : MF ) { MachineInstr * FlagsDefMI = nullptr ; for ( auto & MI : MBB ) { if ( MI . definesRegister ( X86 :: EFLAGS ) ) FlagsDefMI = & MI ; if ( MI . getOpcode ( ) != X86 :: SETCCr ) continue ; MachineInstr * ZExt = nullptr ; for ( auto & Use : MRI -> use_instructions ( MI . getOperand ( 0 ) . getReg ( ) ) ) if ( Use . getOpcode ( ) == X86 :: MOVZX32rr8 ) ZExt = & Use ; if ( ! ZExt ) continue ; if ( ! FlagsDefMI ) continue ; if ( FlagsDefMI -> readsRegister ( X86 :: EFLAGS ) ) continue ; ++ NumSubstZexts ; Changed = true ; const TargetRegisterClass * RC = MF . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ? & X86 :: GR32RegClass : & X86 :: GR32_ABCDRegClass ; Register ZeroReg = MRI -> createVirtualRegister ( RC ) ; Register InsertReg = MRI -> createVirtualRegister ( RC ) ; BuildMI ( MBB , FlagsDefMI , MI . getDebugLoc ( ) , TII -> get ( X86 :: MOV32r0 ) , ZeroReg ) ; BuildMI ( * ZExt -> getParent ( ) , ZExt , ZExt -> getDebugLoc ( ) , TII -> get ( X86 :: INSERT_SUBREG ) , InsertReg ) . addReg ( ZeroReg ) . addReg ( MI . getOperand ( 0 ) . getReg ( ) ) . addImm ( X86 :: sub_8bit ) ; MRI -> replaceRegWith ( ZExt -> getOperand ( 0 ) . getReg ( ) , InsertReg ) ; ToErase . push_back ( ZExt ) ; } } for ( auto & I : ToErase ) I -> eraseFromParent ( ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s>
bool
HexagonOptAddrMode
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
bool
Changed
=
false
;
auto
&
HST
=
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
HII
=
HST
.
getInstrInfo
(
)
;
HRI
=
HST
.
getRegisterInfo
(
)
;
const
auto
&
MDF
=
getAnalysis
<
MachineDominanceFrontier
>
(
)
;
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
const
TargetOperandInfo
TOI
(
*
HII
)
;
DataFlowGraph
G
(
MF
,
*
HII
,
*
HRI
,
*
MDT
,
MDF
,
TOI
)
;
G
.
build
(
BuildOptions
::
KeepDeadPhis
)
;
DFG
=
&
G
;
Liveness
L
(
*
MRI
,
*
DFG
)
;
L
.
computePhiInfo
(
)
;
LV
=
&
L
;
Deleted
.
clear
(
)
;
NodeAddr
<
FuncNode
*
>
FA
=
DFG
->
getFunc
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"==== [RefMap#]=====:\n "
<<
Print
<
NodeAddr
<
FuncNode
*
>>
(
FA
,
*
DFG
)
<<
"\n"
)
;
for
(
NodeAddr
<
BlockNode
*
>
BA
:
FA
.
Addr
->
members
(
*
DFG
)
)
Changed
|=
processBlock
(
BA
)
;
for
(
auto
MI
:
Deleted
)
MI
->
eraseFromParent
(
)
;
if
(
Changed
)
{
G
.
build
(
)
;
L
.
computeLiveIns
(
)
;
L
.
resetLiveIns
(
)
;
L
.
resetKills
(
)
;
}
return
Changed
;
}
</s>

Hexagon
Hexagon
Hexagon
"==== [RefMap#]=====:\n "
"\n"


<s> static bool iv_p ( rtx_insn * insn , rtx reg , struct loop * loop ) { df_ref ause ; unsigned regno = REGNO ( reg ) ; if ( regno == SP_REGNUM ) return false ; for ( ause = DF_REG_USE_CHAIN ( regno ) ; ause ; ause = DF_REF_NEXT_REG ( ause ) ) { if ( ! DF_REF_INSN_INFO ( ause ) || ! NONDEBUG_INSN_P ( DF_REF_INSN ( ause ) ) ) continue ; if ( insn != DF_REF_INSN ( ause ) ) continue ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref def_rec ; FOR_EACH_INSN_INFO_DEF ( def_rec , insn_info ) { rtx_insn * insn = DF_REF_INSN ( def_rec ) ; basic_block bb = BLOCK_FOR_INSN ( insn ) ; if ( dominated_by_p ( CDI_DOMINATORS , bb , loop -> header ) && bb -> loop_father == loop ) { if ( recog_memoized ( insn ) < 0 ) continue ; rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) != SET ) continue ; rtx x = SET_SRC ( pat ) ; if ( GET_CODE ( x ) == ZERO_EXTRACT || GET_CODE ( x ) == ZERO_EXTEND || GET_CODE ( x ) == SIGN_EXTEND ) x = XEXP ( x , 0 ) ; if ( MEM_P ( x ) ) continue ; if ( GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == POST_DEC || GET_CODE ( x ) == PRE_INC || GET_CODE ( x ) == PRE_DEC ) return true ; else if ( BINARY_P ( x ) && ( CONST_INT_P ( XEXP ( x , 0 ) ) || CONST_INT_P ( XEXP ( x , 1 ) ) ) ) { rtx stride = ( CONST_INT_P ( XEXP ( x , 0 ) ) ? XEXP ( x , 0 ) : XEXP ( x , 1 ) ) ; if ( INTVAL ( stride ) < MAX_PREFETCH_STRIDE ) return true ; } } } return false ; } return false ; } </s>

Find the use def chain in which INSN exists and then see if there is a definition inside the loop and outside it . We use this as a simple approximation to determine whether the base register is an IV . The basic idea is to find INSN in the use-def chains for its base register and find all definitions that reach it . Of all these definitions , there should be at least one definition that is a simple addition of a constant value , either as a binary operation or a pre or post update . The function returns true if the base register is estimated to be an IV .


<s>
bool
Z80DAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
char
ConstraintCode
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
assert
(
ConstraintCode
==
'm'
&&
"unexpected asm memory constraint"
)
;
OutOps
.
push_back
(
Op
)
;
return
false
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s>
void
M88kInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MBBI
,
const
DebugLoc
&
DL
,
MCRegister
DestReg
,
MCRegister
SrcReg
,
bool
KillSrc
)
const
{
if
(
M88k
::
GPR64RCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
copyPhysReg
(
MBB
,
MBBI
,
DL
,
RI
.
getSubReg
(
DestReg
,
M88k
::
sub_hi
)
,
RI
.
getSubReg
(
SrcReg
,
M88k
::
sub_hi
)
,
KillSrc
)
;
MachineInstrBuilder
(
*
MBB
.
getParent
(
)
,
std
::
prev
(
MBBI
)
)
.
addReg
(
SrcReg
,
RegState
::
Implicit
)
;
copyPhysReg
(
MBB
,
MBBI
,
DL
,
RI
.
getSubReg
(
DestReg
,
M88k
::
sub_lo
)
,
RI
.
getSubReg
(
SrcReg
,
M88k
::
sub_lo
)
,
KillSrc
)
;
MachineInstrBuilder
(
*
MBB
.
getParent
(
)
,
std
::
prev
(
MBBI
)
)
.
addReg
(
SrcReg
,
(
getKillRegState
(
KillSrc
)
|
RegState
::
Implicit
)
)
;
return
;
}
if
(
M88k
::
GPRRCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
M88k
::
ORrr
)
,
DestReg
)
.
addReg
(
M88k
::
R0
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
return
;
}
unsigned
Opc
;
if
(
M88k
::
XRRCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
M88k
::
MOVxx
;
else
if
(
M88k
::
GPRRCRegClass
.
contains
(
DestReg
)
&&
M88k
::
XRRCRegClass
.
contains
(
SrcReg
)
)
Opc
=
M88k
::
MOVrxs
;
else
if
(
M88k
::
GPR64RCRegClass
.
contains
(
DestReg
)
&&
M88k
::
XRRCRegClass
.
contains
(
SrcReg
)
)
Opc
=
M88k
::
MOVrxd
;
else
if
(
M88k
::
XRRCRegClass
.
contains
(
DestReg
)
&&
M88k
::
GPRRCRegClass
.
contains
(
SrcReg
)
)
Opc
=
M88k
::
MOVxrs
;
else
if
(
M88k
::
XRRCRegClass
.
contains
(
DestReg
)
&&
M88k
::
GPR64RCRegClass
.
contains
(
SrcReg
)
)
Opc
=
M88k
::
MOVxrd
;
else
llvm_unreachable
(
"m88: Impossible reg-to-reg copy"
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == & ARM :: GPRRegClass || RC == & ARM :: tGPRRegClass || RC == & ARM :: tcGPRRegClass || RC == & ARM :: rGPRRegClass || RC == & ARM :: GPRnopcRegClass ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2LDRi12 ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } if ( ARM :: GPRPairRegClass . hasSubClassEq ( RC ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( DestReg , & ARM :: GPRPair_with_gsub_1_in_rGPRRegClass ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( ARM :: t2LDRDi8 ) ) ; AddDReg ( MIB , DestReg , ARM :: gsub_0 , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , ARM :: gsub_1 , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ; AddDefaultPred ( MIB ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; } ARMBaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC , TRI ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> int64_t getOffset ( ) { return Offset ; } </s>

Get the offest of a string in the string table .


<s> static bool expand_perm_with_vpdi ( const struct expand_vec_perm_d & d ) { bool vpdi1_p = false ; bool vpdi4_p = false ; rtx op0_reg , op1_reg ; if ( d . nelt != 2 ) return false ; if ( d . perm [ 0 ] == 0 && d . perm [ 1 ] == 3 ) vpdi1_p = true ; if ( d . perm [ 0 ] == 1 && d . perm [ 1 ] == 2 ) vpdi4_p = true ; if ( ! vpdi1_p && ! vpdi4_p ) return false ; if ( d . testing_p ) return true ; op0_reg = force_reg ( GET_MODE ( d . op0 ) , d . op0 ) ; op1_reg = force_reg ( GET_MODE ( d . op1 ) , d . op1 ) ; if ( vpdi1_p ) emit_insn ( gen_vpdi1 ( d . vmode , d . target , op0_reg , op1_reg ) ) ; if ( vpdi4_p ) emit_insn ( gen_vpdi4 ( d . vmode , d . target , op0_reg , op1_reg ) ) ; return true ; } </s>

Try to expand the vector permute operation described by D using the vector permute doubleword immediate instruction vpdi . Return true if vpdi could be used . VPDI allows 4 different immediate values ( 0 , 1 , 4 , 5 ) . The 0 and 5 cases are covered by vmrhg and vmrlg already . So we only care about the 1 , 4 cases here . 1 - First element of src1 and second of src2 4 - Second element of src1 and first of src2


<s> rtx frv_index_memory ( rtx memref , enum machine_mode mode , int index ) { rtx base = XEXP ( memref , 0 ) ; if ( GET_CODE ( base ) == PRE_MODIFY ) base = XEXP ( base , 0 ) ; return change_address ( memref , mode , plus_constant ( base , index * GET_MODE_SIZE ( mode ) ) ) ; } </s>

Given a memory reference MEMREF , interpret the referenced memory as an array of MODE values , and return a reference to the element specified by INDEX . Assume that any pre-modification implicit in MEMREF has already happened . MEMREF must be a legitimate operand for modes larger than SImode . GO_IF_LEGITIMATE_ADDRESS forbids register+register addresses , which this function can not handle .


<s>
static
void
avr_asm_function_begin_epilogue
(
FILE
*
file
)
{
fprintf
(
file
,
"/* epilogue start */\n"
)
;
}
</s>

Implement ` TARGET_ASM_FUNCTION_BEGIN_EPILOGUE ' .


<s>
unsigned
X86TTI
::
getArithmeticInstrCost
(
unsigned
Opcode
,
Type
*
Ty
)
const
{
std
::
pair
<
unsigned
,
MVT
>
LT
=
TLI
->
getTypeLegalizationCost
(
Ty
)
;
int
ISD
=
TLI
->
InstructionOpcodeToISD
(
Opcode
)
;
assert
(
ISD
&&
"Invalid opcode"
)
;
static
const
X86CostTblEntry
AVX1CostTable
[
]
=
{
{
ISD
::
MUL
,
MVT
::
v8i32
,
4
}
,
{
ISD
::
SUB
,
MVT
::
v8i32
,
4
}
,
{
ISD
::
ADD
,
MVT
::
v8i32
,
4
}
,
{
ISD
::
MUL
,
MVT
::
v4i64
,
4
}
,
{
ISD
::
SUB
,
MVT
::
v4i64
,
4
}
,
{
ISD
::
ADD
,
MVT
::
v4i64
,
4
}
,
}
;
if
(
ST
->
hasAVX
(
)
)
{
int
Idx
=
FindInTable
(
AVX1CostTable
,
array_lengthof
(
AVX1CostTable
)
,
ISD
,
LT
.
second
)
;
if
(
Idx
!=
1
)
return
LT
.
first
*
AVX1CostTable
[
Idx
]
.
Cost
;
}
return
TargetTransformInfo
::
getArithmeticInstrCost
(
Opcode
,
Ty
)
;
}
</s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> bool BPFPassConfig :: addInstSelector ( ) { addPass ( createBPFISelDag ( getBPFTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> unsigned int ix86_local_alignment ( tree exp , machine_mode mode , unsigned int align , bool may_lower ) { tree type , decl ; if ( exp && DECL_P ( exp ) ) { type = TREE_TYPE ( exp ) ; decl = exp ; } else { type = exp ; decl = NULL ; } if ( may_lower && ! TARGET_64BIT && align == 64 && ix86_preferred_stack_boundary < 64 && ( mode == DImode || ( type && TYPE_MODE ( type ) == DImode ) ) && ( ! type || ( ! TYPE_USER_ALIGN ( type ) && ! TYPE_ATOMIC ( strip_array_types ( type ) ) ) ) && ( ! decl || ! DECL_USER_ALIGN ( decl ) ) ) align = 32 ; if ( ! type ) { if ( mode == XFmode && align < GET_MODE_ALIGNMENT ( DFmode ) ) align = GET_MODE_ALIGNMENT ( DFmode ) ; return align ; } if ( TARGET_IAMCU ) return align ; if ( TARGET_64BIT && optimize_function_for_speed_p ( cfun ) && TARGET_SSE ) { if ( AGGREGATE_TYPE_P ( type ) && ( va_list_type_node == NULL_TREE || ( TYPE_MAIN_VARIANT ( type ) != TYPE_MAIN_VARIANT ( va_list_type_node ) ) ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && wi :: geu_p ( wi :: to_wide ( TYPE_SIZE ( type ) ) , 128 ) && align < 128 ) return 128 ; } if ( TREE_CODE ( type ) == ARRAY_TYPE ) { if ( TYPE_MODE ( TREE_TYPE ( type ) ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( type ) ) ) && align < 128 ) return 128 ; } else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) { if ( TYPE_MODE ( type ) == DCmode && align < 64 ) return 64 ; if ( ( TYPE_MODE ( type ) == XCmode || TYPE_MODE ( type ) == TCmode ) && align < 128 ) return 128 ; } else if ( ( TREE_CODE ( type ) == RECORD_TYPE || TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == QUAL_UNION_TYPE ) && TYPE_FIELDS ( type ) ) { if ( DECL_MODE ( TYPE_FIELDS ( type ) ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( DECL_MODE ( TYPE_FIELDS ( type ) ) ) && align < 128 ) return 128 ; } else if ( TREE_CODE ( type ) == REAL_TYPE || TREE_CODE ( type ) == VECTOR_TYPE || TREE_CODE ( type ) == INTEGER_TYPE ) { if ( TYPE_MODE ( type ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( TYPE_MODE ( type ) ) && align < 128 ) return 128 ; } return align ; } </s>

Compute the alignment for a local variable . TYPE is the data type , and ALIGN is the alignment that the object would ordinarily have . The value of this macro is used instead of that alignment to align the object .


<s> int mcore_num_arg_regs ( machine_mode mode , const_tree type ) { int size ; function_arg_info arg ( const_cast < tree > ( type ) , mode , true ) ; if ( targetm . calls . must_pass_in_stack ( arg ) ) return 0 ; if ( type && mode == BLKmode ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; return ROUND_ADVANCE ( size ) ; } </s>

Compute the number of word sized registers needed to hold a function argument of mode MODE and type TYPE .


<s>
void
SIRegisterInfo
::
resolveFrameIndex
(
MachineInstr
&
MI
,
Register
BaseReg
,
int64_t
Offset
)
const
{
const
SIInstrInfo
*
TII
=
ST
.
getInstrInfo
(
)
;
bool
IsFlat
=
TII
->
isFLATScratch
(
MI
)
;
bool
SeenFI
=
false
;
for
(
const
MachineOperand
&
MO
:
MI
.
operands
(
)
)
{
if
(
MO
.
isFI
(
)
)
{
if
(
SeenFI
)
llvm_unreachable
(
"should not see multiple frame indices"
)
;
SeenFI
=
true
;
}
}
MachineOperand
*
FIOp
=
TII
->
getNamedOperand
(
MI
,
IsFlat
AMDGPU
::
OpName
::
saddr
:
AMDGPU
::
OpName
::
vaddr
)
;
MachineOperand
*
OffsetOp
=
TII
->
getNamedOperand
(
MI
,
AMDGPU
::
OpName
::
offset
)
;
int64_t
NewOffset
=
OffsetOp
->
getImm
(
)
+
Offset
;
assert
(
FIOp
&&
FIOp
->
isFI
(
)
&&
"frame index must be address operand"
)
;
assert
(
TII
->
isMUBUF
(
MI
)
||
TII
->
isFLATScratch
(
MI
)
)
;
if
(
IsFlat
)
{
assert
(
TII
->
isLegalFLATOffset
(
NewOffset
,
AMDGPUAS
::
PRIVATE_ADDRESS
,
true
)
&&
"offset should be legal"
)
;
FIOp
->
ChangeToRegister
(
BaseReg
,
false
)
;
OffsetOp
->
setImm
(
NewOffset
)
;
return
;
}
MachineOperand
*
SOffset
=
TII
->
getNamedOperand
(
MI
,
AMDGPU
::
OpName
::
soffset
)
;
assert
(
SOffset
->
isImm
(
)
&&
SOffset
->
getImm
(
)
==
0
)
;
assert
(
SIInstrInfo
::
isLegalMUBUFImmOffset
(
NewOffset
)
&&
"offset should be legal"
)
;
FIOp
->
ChangeToRegister
(
BaseReg
,
false
)
;
OffsetOp
->
setImm
(
NewOffset
)
;
}
</s>

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .

AMDGPU
SI
SI
"should not see multiple frame indices"
AMDGPU::OpName
AMDGPU::OpName
AMDGPU::OpName
"frame index must be address operand"
AMDGPU
"offset should be legal"
AMDGPU::OpName
0
SI
"offset should be legal"


"  r%d def in insn %d isn't convertible\n"

"  r%d use in insn %d isn't convertible\n"

Check REF 's chain to add new insns into a queue and find registers requiring conversion . Return true if OK , false if the analysis was aborted .


<s> static void emit_reg_adjust ( rtx reg1 , int n ) { rtx reg2 ; gcc_assert ( GET_MODE ( reg1 ) == SImode && - 12 <= n && n != 0 && n <= 12 ) ; reg1 = copy_rtx ( reg1 ) ; reg2 = copy_rtx ( reg1 ) ; if ( n < 0 ) emit_insn ( gen_subsi3 ( reg1 , reg2 , GEN_INT ( - n ) ) ) ; else if ( n > 0 ) emit_insn ( gen_addsi3 ( reg1 , reg2 , GEN_INT ( n ) ) ) ; else gcc_unreachable ( ) ; } </s>


<s> void NVPTXTTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP , OptimizationRemarkEmitter * ORE ) { BaseT :: getUnrollingPreferences ( L , SE , UP , ORE ) ; UP . Partial = UP . Runtime = true ; UP . PartialThreshold = UP . Threshold / 4 ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> static rtx frv_expand_mrdacc_builtin ( enum insn_code icode , tree call ) { rtx pat ; rtx target = gen_reg_rtx ( SImode ) ; rtx op0 = frv_read_argument ( call , 0 ) ; op0 = frv_int_to_acc ( icode , 1 , op0 ) ; if ( ! op0 ) return NULL_RTX ; pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return target ; } </s>

Expand MRDACC and MRDACCG . These builtins take a single accumulator number or accumulator guard number as argument and return an SI integer .


<s> const RegisterBankInfo :: InstructionMapping & MOSRegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { const auto & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; const auto & MRI = MI . getMF ( ) -> getRegInfo ( ) ; unsigned NumOperands = MI . getNumOperands ( ) ; SmallVector < const ValueMapping * , 8 > ValMappings ( NumOperands ) ; for ( const auto & I : enumerate ( MI . operands ( ) ) ) { if ( ! I . value ( ) . isReg ( ) ) continue ; if ( MI . isPHI ( ) && I . index ( ) == 1 ) { NumOperands = 1 ; break ; } LLT Ty = MRI . getType ( I . value ( ) . getReg ( ) ) ; ValMappings [ I . index ( ) ] = & getValueMapping ( 0 , Ty . getSizeInBits ( ) , MOS :: AnyRegBank ) ; } return getInstructionMapping ( 1 , 1 , getOperandsMapping ( ValMappings ) , NumOperands ) ; } </s>

Get the mapping of the different operands of MI on the register bank .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> const TargetRegisterClass * MSP430RegisterInfo :: getPointerRegClass ( unsigned Kind ) const { return & MSP430 :: GR16RegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> MachineBasicBlock :: const_iterator getNext ( ) const { return NextMI ; } </s>


<s> bool SystemZShortenInst :: runOnMachineFunction ( MachineFunction & F ) { TII = static_cast < const SystemZInstrInfo * > ( F . getTarget ( ) . getInstrInfo ( ) ) ; bool Changed = false ; for ( auto & MBB : F ) Changed |= processBlock ( MBB ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> static rtx xtensa_builtin_saveregs ( void ) { rtx gp_regs ; int arg_words = crtl -> args . info . arg_words ; int gp_left = MAX_ARGS_IN_REGISTERS - arg_words ; if ( gp_left <= 0 ) return const0_rtx ; gp_regs = assign_stack_local ( BLKmode , MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD , - 1 ) ; set_mem_alias_set ( gp_regs , get_varargs_alias_set ( ) ) ; cfun -> machine -> need_a7_copy = TARGET_WINDOWED_ABI ; cfun -> machine -> vararg_a7 = true ; move_block_from_reg ( GP_ARG_FIRST + arg_words , adjust_address ( gp_regs , BLKmode , arg_words * UNITS_PER_WORD ) , gp_left ) ; if ( cfun -> machine -> vararg_a7_copy != 0 ) emit_insn_before ( cfun -> machine -> vararg_a7_copy , get_insns ( ) ) ; return XEXP ( gp_regs , 0 ) ; } </s>

Save the incoming argument registers on the stack . Returns the address of the saved registers .


<s> static bool ix86_valid_target_attribute_p ( tree fndecl , tree ARG_UNUSED ( name ) , tree args , int ARG_UNUSED ( flags ) ) { struct gcc_options func_options ; tree new_target , new_optimize ; bool ret = true ; if ( TREE_VALUE ( args ) && TREE_CODE ( TREE_VALUE ( args ) ) == STRING_CST && TREE_CHAIN ( args ) == NULL_TREE && strcmp ( TREE_STRING_POINTER ( TREE_VALUE ( args ) ) , "default" ) == 0 ) return true ; tree old_optimize = build_optimization_node ( & global_options ) ; tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( ! func_optimize ) func_optimize = old_optimize ; memset ( & func_options , 0 , sizeof ( func_options ) ) ; init_options_struct ( & func_options , NULL ) ; lang_hooks . init_options_struct ( & func_options ) ; cl_optimization_restore ( & func_options , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_restore ( & func_options , TREE_TARGET_OPTION ( target_option_default_node ) ) ; new_target = ix86_valid_target_attribute_tree ( args , & func_options , & global_options_set ) ; new_optimize = build_optimization_node ( & func_options ) ; if ( new_target == error_mark_node ) ret = false ; else if ( fndecl && new_target ) { DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = new_target ; if ( old_optimize != new_optimize ) DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) = new_optimize ; } finalize_options_struct ( & func_options ) ; return ret ; } </s>

Hook to validate attribute ( ( target ( `` string '' ) ) ) .


<s> bool R600InstrInfo :: fitsConstReadLimitations ( const std :: vector < MachineInstr * > & MIs ) const { std :: vector < unsigned > Consts ; SmallSet < int64_t , 4 > Literals ; for ( unsigned i = 0 , n = MIs . size ( ) ; i < n ; i ++ ) { MachineInstr & MI = * MIs [ i ] ; if ( ! isALUInstr ( MI . getOpcode ( ) ) ) continue ; for ( const auto & Src : getSrcs ( MI ) ) { if ( Src . first -> getReg ( ) == R600 :: ALU_LITERAL_X ) Literals . insert ( Src . second ) ; if ( Literals . size ( ) > 4 ) return false ; if ( Src . first -> getReg ( ) == R600 :: ALU_CONST ) Consts . push_back ( Src . second ) ; if ( R600 :: R600_KC0RegClass . contains ( Src . first -> getReg ( ) ) || R600 :: R600_KC1RegClass . contains ( Src . first -> getReg ( ) ) ) { unsigned Index = RI . getEncodingValue ( Src . first -> getReg ( ) ) & 0xff ; unsigned Chan = RI . getHWRegChan ( Src . first -> getReg ( ) ) ; Consts . push_back ( ( Index << 2 ) | Chan ) ; } } } return fitsConstReadLimitations ( Consts ) ; } </s>

Same but using const index set instead of MI set .


<s> bool SITargetLowering :: isTypeDesirableForOp ( unsigned Op , EVT VT ) const { if ( Subtarget -> has16BitInsts ( ) && VT == MVT :: i16 ) { switch ( Op ) { case ISD :: LOAD : case ISD :: STORE : case ISD :: AND : case ISD :: OR : case ISD :: XOR : case ISD :: SELECT : return true ; default : return false ; } } if ( VT == MVT :: i1 && Op == ISD :: SETCC ) return false ; return TargetLowering :: isTypeDesirableForOp ( Op , VT ) ; } </s>

Return true if the target has native support for the specified value type and it is 'desirable ' to use the type for the given node type .

AMDGPU SI MVT::i16 ISD::LOAD ISD::STORE ISD::AND ISD::OR ISD::XOR ISD::SELECT MVT::i1 ISD::SETCC


<s> static void rs6000_print_isa_options ( FILE * file , int indent , const char * string , HOST_WIDE_INT flags ) { rs6000_print_options_internal ( file , indent , string , flags , "-m" , & rs6000_opt_masks [ 0 ] , ARRAY_SIZE ( rs6000_opt_masks ) ) ; } </s>

Helper function to print the current isa options on a line .


<s> bool AMDGPUFixFunctionBitcasts :: runOnModule ( Module & M ) { Modified = false ; visit ( M ) ; return Modified ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> virtual const WDC65816RegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
static
SDValue
getTargetNode
(
SDValue
Op
,
SelectionDAG
&
DAG
,
unsigned
Flag
)
{
EVT
Ty
=
Op
.
getValueType
(
)
;
if
(
GlobalAddressSDNode
*
N
=
dyn_cast
<
GlobalAddressSDNode
>
(
Op
)
)
return
DAG
.
getTargetGlobalAddress
(
N
->
getGlobal
(
)
,
Op
.
getDebugLoc
(
)
,
Ty
,
0
,
Flag
)
;
if
(
ExternalSymbolSDNode
*
N
=
dyn_cast
<
ExternalSymbolSDNode
>
(
Op
)
)
return
DAG
.
getTargetExternalSymbol
(
N
->
getSymbol
(
)
,
Ty
,
Flag
)
;
if
(
BlockAddressSDNode
*
N
=
dyn_cast
<
BlockAddressSDNode
>
(
Op
)
)
return
DAG
.
getTargetBlockAddress
(
N
->
getBlockAddress
(
)
,
Ty
,
0
,
Flag
)
;
if
(
JumpTableSDNode
*
N
=
dyn_cast
<
JumpTableSDNode
>
(
Op
)
)
return
DAG
.
getTargetJumpTable
(
N
->
getIndex
(
)
,
Ty
,
Flag
)
;
if
(
ConstantPoolSDNode
*
N
=
dyn_cast
<
ConstantPoolSDNode
>
(
Op
)
)
return
DAG
.
getTargetConstantPool
(
N
->
getConstVal
(
)
,
Ty
,
N
->
getAlignment
(
)
,
N
->
getOffset
(
)
,
Flag
)
;
llvm_unreachable
(
"Unexpected node type."
)
;
return
SDValue
(
)
;
}
</s>

Retrieve the target node this edge connects to .


<s> void AMDGPUAsmPrinter :: emitStartOfAsmFile ( Module & M ) { if ( isHsaAbiVersion3 ( getGlobalSTI ( ) ) ) { std :: string ExpectedTarget ; raw_string_ostream ExpectedTargetOS ( ExpectedTarget ) ; IsaInfo :: streamIsaVersion ( getGlobalSTI ( ) , ExpectedTargetOS ) ; getTargetStreamer ( ) -> EmitDirectiveAMDGCNTarget ( ExpectedTarget ) ; } if ( TM . getTargetTriple ( ) . getOS ( ) != Triple :: AMDHSA && TM . getTargetTriple ( ) . getOS ( ) != Triple :: AMDPAL ) return ; if ( TM . getTargetTriple ( ) . getOS ( ) == Triple :: AMDHSA ) HSAMetadataStream -> begin ( M ) ; if ( TM . getTargetTriple ( ) . getOS ( ) == Triple :: AMDPAL ) getTargetStreamer ( ) -> getPALMetadata ( ) -> readFromIR ( M ) ; if ( isHsaAbiVersion3 ( getGlobalSTI ( ) ) ) return ; if ( TM . getTargetTriple ( ) . getOS ( ) == Triple :: AMDHSA ) getTargetStreamer ( ) -> EmitDirectiveHSACodeObjectVersion ( 2 , 1 ) ; IsaVersion Version = getIsaVersion ( getGlobalSTI ( ) -> getCPU ( ) ) ; getTargetStreamer ( ) -> EmitDirectiveHSACodeObjectISA ( Version . Major , Version . Minor , Version . Stepping , "AMD" , "AMDGPU" ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the start of their file .


<s> bool RISCVExpandSDMA :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const RISCVInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; bool Modified = false ; for ( auto & MBB : MF ) Modified |= expandMBB ( MBB ) ; return Modified ; } </s>


<s> static struct machine_function * mips_init_machine_status ( void ) { return ( ( struct machine_function * ) ggc_alloc_cleared ( sizeof ( struct machine_function ) ) ) ; } </s>

Allocate a chunk of memory for per-function machine-dependent data .


<s> static bool arm_evpc_neon_vtrn ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> nelt ; rtx out0 , out1 , in0 , in1 ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; if ( d -> perm [ 0 ] == 0 ) odd = 0 ; else if ( d -> perm [ 0 ] == 1 ) odd = 1 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt ; i += 2 ) { if ( d -> perm [ i ] != i + odd ) return false ; if ( d -> perm [ i + 1 ] != ( ( i + nelt + odd ) & mask ) ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vtrnv16qi_internal ; break ; case V8QImode : gen = gen_neon_vtrnv8qi_internal ; break ; case V8HImode : gen = gen_neon_vtrnv8hi_internal ; break ; case V4HImode : gen = gen_neon_vtrnv4hi_internal ; break ; case V8HFmode : gen = gen_neon_vtrnv8hf_internal ; break ; case V4HFmode : gen = gen_neon_vtrnv4hf_internal ; break ; case V4SImode : gen = gen_neon_vtrnv4si_internal ; break ; case V2SImode : gen = gen_neon_vtrnv2si_internal ; break ; case V2SFmode : gen = gen_neon_vtrnv2sf_internal ; break ; case V4SFmode : gen = gen_neon_vtrnv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN ) { std :: swap ( in0 , in1 ) ; odd = ! odd ; } out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( odd ) std :: swap ( out0 , out1 ) ; emit_insn ( gen ( out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s> void rs6000_expand_vector_extract ( rtx target , rtx vec , int elt ) { enum machine_mode mode = GET_MODE ( vec ) ; enum machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx mem , x ; mem = assign_stack_temp ( mode , GET_MODE_SIZE ( mode ) , 0 ) ; mem = adjust_address_nv ( mem , mode , elt * GET_MODE_SIZE ( inner_mode ) ) ; x = gen_rtx_UNSPEC ( VOIDmode , gen_rtvec ( 1 , const0_rtx ) , UNSPEC_STVE ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , gen_rtx_SET ( VOIDmode , mem , vec ) , x ) ) ) ; emit_move_insn ( target , adjust_address_nv ( mem , inner_mode , 0 ) ) ; } </s>

Extract field ELT from VEC into TARGET .


<s> void SparcTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { SDValue Result ( nullptr , 0 ) ; if ( Constraint . length ( ) > 1 ) return ; char ConstraintLetter = Constraint [ 0 ] ; switch ( ConstraintLetter ) { default : break ; case 'I' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isInt < 13 > ( C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ; break ; } return ; } } if ( Result . getNode ( ) ) { Ops . push_back ( Result ) ; return ; } TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; } </s>

Lower the specified operand into the Ops vector .


<s> bool WebAssemblyEHRestoreStackPointer :: runOnMachineFunction ( MachineFunction & MF ) { const auto * FrameLowering = static_cast < const WebAssemblyFrameLowering * > ( MF . getSubtarget ( ) . getFrameLowering ( ) ) ; if ( ! FrameLowering -> needsPrologForEH ( MF ) ) return false ; bool Changed = false ; for ( auto & MBB : MF ) { if ( ! MBB . isEHPad ( ) ) continue ; Changed = true ; auto InsertPos = MBB . begin ( ) ; if ( WebAssembly :: isCatch ( * MBB . begin ( ) ) ) InsertPos ++ ; FrameLowering -> writeSPToGlobal ( WebAssembly :: SP32 , MF , MBB , InsertPos , MBB . begin ( ) -> getDebugLoc ( ) ) ; } return Changed ; } </s>

WebAssembly WebAssembly WebAssembly WebAssembly::isCatch WebAssembly::SP32


<s> bool HexagonFixupHwLoops :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; return fixupLoopInstrs ( MF ) ; } </s>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; const PPCSubtarget & STI = MF . getSubtarget < PPCSubtarget > ( ) ; if ( ! STI . hasVSX ( ) || ! STI . needsSwapsForVSXMemOps ( ) ) return false ; bool Changed = false ; initialize ( MF ) ; if ( gatherVectorInstructions ( ) ) { formWebs ( ) ; recordUnoptimizableWebs ( ) ; markSwapsForRemoval ( ) ; Changed = removeSwaps ( ) ; } delete EC ; return Changed ; } </s>


<s> const uint32_t * XtensaRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { return 0 ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> virtual const X86RegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>


<s> const char * AArch64TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case AArch64ISD :: BR_CC : return "AArch64ISD::BR_CC" ; case AArch64ISD :: Call : return "AArch64ISD::Call" ; case AArch64ISD :: FPMOV : return "AArch64ISD::FPMOV" ; case AArch64ISD :: GOTLoad : return "AArch64ISD::GOTLoad" ; case AArch64ISD :: BFI : return "AArch64ISD::BFI" ; case AArch64ISD :: EXTR : return "AArch64ISD::EXTR" ; case AArch64ISD :: Ret : return "AArch64ISD::Ret" ; case AArch64ISD :: SBFX : return "AArch64ISD::SBFX" ; case AArch64ISD :: SELECT_CC : return "AArch64ISD::SELECT_CC" ; case AArch64ISD :: SETCC : return "AArch64ISD::SETCC" ; case AArch64ISD :: TC_RETURN : return "AArch64ISD::TC_RETURN" ; case AArch64ISD :: THREAD_POINTER : return "AArch64ISD::THREAD_POINTER" ; case AArch64ISD :: TLSDESCCALL : return "AArch64ISD::TLSDESCCALL" ; case AArch64ISD :: WrapperLarge : return "AArch64ISD::WrapperLarge" ; case AArch64ISD :: WrapperSmall : return "AArch64ISD::WrapperSmall" ; case AArch64ISD :: NEON_BSL : return "AArch64ISD::NEON_BSL" ; case AArch64ISD :: NEON_MOVIMM : return "AArch64ISD::NEON_MOVIMM" ; case AArch64ISD :: NEON_MVNIMM : return "AArch64ISD::NEON_MVNIMM" ; case AArch64ISD :: NEON_FMOVIMM : return "AArch64ISD::NEON_FMOVIMM" ; case AArch64ISD :: NEON_CMP : return "AArch64ISD::NEON_CMP" ; case AArch64ISD :: NEON_CMPZ : return "AArch64ISD::NEON_CMPZ" ; case AArch64ISD :: NEON_TST : return "AArch64ISD::NEON_TST" ; case AArch64ISD :: NEON_QSHLs : return "AArch64ISD::NEON_QSHLs" ; case AArch64ISD :: NEON_QSHLu : return "AArch64ISD::NEON_QSHLu" ; case AArch64ISD :: NEON_VDUP : return "AArch64ISD::NEON_VDUP" ; case AArch64ISD :: NEON_VDUPLANE : return "AArch64ISD::NEON_VDUPLANE" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> rtx ix86_build_signbit_mask ( machine_mode mode , bool vect , bool invert ) { machine_mode vec_mode , imode ; wide_int w ; rtx mask , v ; switch ( mode ) { case V16SImode : case V16SFmode : case V8SImode : case V4SImode : case V8SFmode : case V4SFmode : vec_mode = mode ; imode = SImode ; break ; case V8DImode : case V4DImode : case V2DImode : case V8DFmode : case V4DFmode : case V2DFmode : vec_mode = mode ; imode = DImode ; break ; case TImode : case TFmode : vec_mode = VOIDmode ; imode = TImode ; break ; default : gcc_unreachable ( ) ; } machine_mode inner_mode = GET_MODE_INNER ( mode ) ; w = wi :: set_bit_in_zero ( GET_MODE_BITSIZE ( inner_mode ) - 1 , GET_MODE_BITSIZE ( inner_mode ) ) ; if ( invert ) w = wi :: bit_not ( w ) ; mask = immed_wide_int_const ( w , imode ) ; mask = gen_lowpart ( inner_mode , mask ) ; if ( vec_mode == VOIDmode ) return force_reg ( inner_mode , mask ) ; v = ix86_build_const_vector ( vec_mode , vect , mask ) ; return force_reg ( vec_mode , v ) ; } </s>

A subroutine of ix86_expand_fp_absneg_operator and copysign expanders . Create a mask for the sign bit in MODE for an SSE register . If VECT is true , then replicate the mask for all elements of the vector register . If INVERT is true , then create a mask excluding the sign bit .


<s> SDNode * PPCDAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * TM . getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc dl ; if ( PPCLowering . getPointerTy ( ) == MVT :: i32 ) { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: GPRC_NOR0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: G8RC_NOX0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR8 ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR8 ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , PPCLowering . getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static bool nvptx_truly_noop_truncation ( poly_uint64 , poly_uint64 ) { return false ; } </s>


<s> static bool microblaze_frame_pointer_required ( void ) { if ( cfun -> calls_alloca ) return true ; return false ; } </s>


"SystemZ Local Dynamic TLS Access Clean-up"

getPassName - Return a nice clean name for a pass .


<s> bool X86TargetLowering :: isIntDivCheap ( EVT VT , AttributeList Attr ) const { bool OptSize = Attr . hasAttribute ( AttributeList :: FunctionIndex , Attribute :: MinSize ) ; return OptSize && ! VT . isVector ( ) ; } </s>

Return true if integer divide is usually cheaper than a sequence of several shifts , adds , and multiplies for this target .