<s>
SDValue
AArch64TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom lower this!"
)
;
case
ISD
::
FADD
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
ADD_F128
)
;
case
ISD
::
FSUB
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
SUB_F128
)
;
case
ISD
::
FMUL
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
MUL_F128
)
;
case
ISD
::
FDIV
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
DIV_F128
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
,
true
)
;
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
,
false
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
,
true
)
;
case
ISD
::
UINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
,
false
)
;
case
ISD
::
FP_ROUND
:
return
LowerFP_ROUND
(
Op
,
DAG
)
;
case
ISD
::
FP_EXTEND
:
return
LowerFP_EXTEND
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
BRCOND
:
return
LowerBRCOND
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddressELF
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
LowerSELECT
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
case
ISD
::
VACOPY
:
return
LowerVACOPY
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
BUILD_VECTOR
:
return
LowerBUILD_VECTOR
(
Op
,
DAG
,
getSubtarget
(
)
)
;
case
ISD
::
CONCAT_VECTORS
:
return
LowerCONCAT_VECTORS
(
Op
,
DAG
)
;
case
ISD
::
VECTOR_SHUFFLE
:
return
LowerVECTOR_SHUFFLE
(
Op
,
DAG
)
;
}
return
SDValue
(
)
;
}
</s>


"WebAssembly should not have callee-saved registers"

"Functions needing frame pointers not yet supported"

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> void PPCPostRASchedStrategy :: tryCandidate ( SchedCandidate & Cand , SchedCandidate & TryCand ) { PostGenericScheduler :: tryCandidate ( Cand , TryCand ) ; if ( ! Cand . isValid ( ) ) return ; if ( TryCand . Reason != NodeOrder && TryCand . Reason != NoCand ) return ; if ( biasAddiCandidate ( Cand , TryCand ) ) return ; } </s>

Apply a set of heuristics to a new candidate .


<s> SMRange getLocRange ( ) const { return SMRange ( StartLoc , EndLoc ) ; } </s>

getLocRange - Get the range between the first and last token of this operand .


"%s instructions aren%'t allowed in a function with "

Establish appropriate back-end context for processing the function FNDECL . The argument might be NULL to indicate processing at top level , outside of any function scope .


<s> unsigned AArch64RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const AArch64FrameLowering * TFI = getFrameLowering ( MF ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case AArch64 :: GPR32RegClassID : case AArch64 :: GPR32spRegClassID : case AArch64 :: GPR32allRegClassID : case AArch64 :: GPR64spRegClassID : case AArch64 :: GPR64allRegClassID : case AArch64 :: GPR64RegClassID : case AArch64 :: GPR32commonRegClassID : case AArch64 :: GPR64commonRegClassID : return 32 - 1 - ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) - MF . getSubtarget < AArch64Subtarget > ( ) . getNumXRegisterReserved ( ) - hasBasePointer ( MF ) ; case AArch64 :: FPR8RegClassID : case AArch64 :: FPR16RegClassID : case AArch64 :: FPR32RegClassID : case AArch64 :: FPR64RegClassID : case AArch64 :: FPR128RegClassID : return 32 ; case AArch64 :: MatrixIndexGPR32_12_15RegClassID : return 4 ; case AArch64 :: DDRegClassID : case AArch64 :: DDDRegClassID : case AArch64 :: DDDDRegClassID : case AArch64 :: QQRegClassID : case AArch64 :: QQQRegClassID : case AArch64 :: QQQQRegClassID : return 32 ; case AArch64 :: FPR128_loRegClassID : case AArch64 :: FPR64_loRegClassID : case AArch64 :: FPR16_loRegClassID : return 16 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


"********** Memory Intrinsic Results **********\n"

"MemIntrinsicResults expects liveness tracking"

runOnMachineFunction - Emit the function body .


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
)
;
break
;
case
ISD
::
SIGN_EXTEND
:
case
ISD
::
ZERO_EXTEND
:
Res
=
ExpandVectorExtension
(
N
,
DAG
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
ATOMIC_LOAD_ADD
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMADD64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_AND
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMAND64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_NAND
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMNAND64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_OR
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMOR64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_SUB
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMSUB64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_XOR
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMXOR64_DAG
)
;
return
;
case
ISD
::
ATOMIC_SWAP
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMSWAP64_DAG
)
;
return
;
case
ISD
::
ATOMIC_CMP_SWAP
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMCMPXCHG64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_MIN
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMMIN64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_UMIN
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMUMIN64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_MAX
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMMAX64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_UMAX
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMUMAX64_DAG
)
;
return
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> void NVPTXFrameLowering :: emitPrologue ( MachineFunction & MF ) const { if ( MF . getFrameInfo ( ) -> hasStackObjects ( ) ) { MachineBasicBlock & MBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = DebugLoc ( ) ; if ( tm . getSubtargetImpl ( ) -> hasGenericLdSt ( ) ) { if ( is64bit ) { MachineInstr * MI = BuildMI ( MBB , MBBI , dl , tm . getInstrInfo ( ) -> get ( NVPTX :: cvta_local_yes_64 ) , NVPTX :: VRFrame ) . addReg ( NVPTX :: VRFrameLocal ) ; BuildMI ( MBB , MI , dl , tm . getInstrInfo ( ) -> get ( NVPTX :: IMOV64rr ) , NVPTX :: VRFrameLocal ) . addReg ( NVPTX :: VRDepot ) ; } else { MachineInstr * MI = BuildMI ( MBB , MBBI , dl , tm . getInstrInfo ( ) -> get ( NVPTX :: cvta_local_yes ) , NVPTX :: VRFrame ) . addReg ( NVPTX :: VRFrameLocal ) ; BuildMI ( MBB , MI , dl , tm . getInstrInfo ( ) -> get ( NVPTX :: IMOV32rr ) , NVPTX :: VRFrameLocal ) . addReg ( NVPTX :: VRDepot ) ; } } else { if ( is64bit ) BuildMI ( MBB , MBBI , dl , tm . getInstrInfo ( ) -> get ( NVPTX :: IMOV64rr ) , NVPTX :: VRFrame ) . addReg ( NVPTX :: VRDepot ) ; else BuildMI ( MBB , MBBI , dl , tm . getInstrInfo ( ) -> get ( NVPTX :: IMOV32rr ) , NVPTX :: VRFrame ) . addReg ( NVPTX :: VRDepot ) ; } } } </s>

NVPTX NVPTX NVPTX::cvta_local_yes_64 NVPTX::VRFrame NVPTX::VRFrameLocal NVPTX::IMOV64rr NVPTX::VRFrameLocal NVPTX::VRDepot NVPTX::cvta_local_yes NVPTX::VRFrame NVPTX::VRFrameLocal NVPTX::IMOV32rr NVPTX::VRFrameLocal NVPTX::VRDepot NVPTX::IMOV64rr NVPTX::VRFrame NVPTX::VRDepot NVPTX::IMOV32rr NVPTX::VRFrame NVPTX::VRDepot


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


"256-bit vector operations only available in AVX2"

Change the opcode of MI to execute in Domain .


<s> bool X86TargetLowering :: isShuffleMaskLegal ( ArrayRef < int > M , EVT VT ) const { if ( ! VT . isSimple ( ) ) return false ; if ( VT . getSimpleVT ( ) . getScalarType ( ) == MVT :: i1 ) return false ; if ( VT . getSimpleVT ( ) . getSizeInBits ( ) == 64 ) return false ; return isTypeLegal ( VT . getSimpleVT ( ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"STI CBEA SPU Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool MipsTargetObjectFile :: IsConstantInSmallSection ( const Constant * CN , const TargetMachine & TM ) const { return ( static_cast < const MipsTargetMachine & > ( TM ) . getSubtargetImpl ( ) -> useSmallSection ( ) && LocalSData && IsInSmallSection ( TM . getDataLayout ( ) -> getTypeAllocSize ( CN -> getType ( ) ) ) ) ; } </s>

Return true if this constant should be placed into small data section .


<s> uint64_t HexagonInstrInfo :: getType ( const MachineInstr & MI ) const { const uint64_t F = MI . getDesc ( ) . TSFlags ; return ( F >> HexagonII :: TypePos ) & HexagonII :: TypeMask ; } </s>

Overload to return most specific vector type .

Hexagon Hexagon HexagonII::TypePos HexagonII::TypeMask


<s> static bool ix86_notrack_prefixed_insn_p ( rtx insn ) { if ( ! insn || ! ( ( flag_cf_protection & CF_BRANCH ) ) ) return false ; if ( CALL_P ( insn ) ) { rtx call = get_call_rtx_from ( insn ) ; gcc_assert ( call != NULL_RTX ) ; rtx addr = XEXP ( call , 0 ) ; if ( MEM_P ( addr ) && GET_CODE ( XEXP ( addr , 0 ) ) == SYMBOL_REF ) return false ; else return find_reg_note ( insn , REG_CALL_NOCF_CHECK , 0 ) ; } if ( JUMP_P ( insn ) && ! flag_cet_switch ) { rtx target = JUMP_LABEL ( insn ) ; if ( target == NULL_RTX || ANY_RETURN_P ( target ) ) return false ; rtx_insn * label = as_a < rtx_insn * > ( target ) ; rtx_insn * table = next_insn ( label ) ; if ( table == NULL_RTX || ! JUMP_TABLE_DATA_P ( table ) ) return false ; else return true ; } return false ; } </s>

Return 1 if control tansfer instruction INSN should be encoded with notrack prefix .


<s> unsigned RISCVInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : { if ( MI . getParent ( ) && MI . getParent ( ) -> getParent ( ) ) { const auto MF = MI . getMF ( ) ; const auto & TM = static_cast < const RISCVTargetMachine & > ( MF -> getTarget ( ) ) ; const MCRegisterInfo & MRI = * TM . getMCRegisterInfo ( ) ; const MCSubtargetInfo & STI = * TM . getMCSubtargetInfo ( ) ; const RISCVSubtarget & ST = MF -> getSubtarget < RISCVSubtarget > ( ) ; if ( isCompressibleInst ( MI , & ST , MRI , STI ) ) return 2 ; } return get ( Opcode ) . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return 0 ; case RISCV :: PseudoCALLReg : case RISCV :: PseudoCALL : case RISCV :: PseudoJump : case RISCV :: PseudoTAIL : case RISCV :: PseudoLLA : case RISCV :: PseudoLA : case RISCV :: PseudoLA_TLS_IE : case RISCV :: PseudoLA_TLS_GD : return 8 ; case RISCV :: PseudoAtomicLoadNand32 : case RISCV :: PseudoAtomicLoadNand64 : return 20 ; case RISCV :: PseudoMaskedAtomicSwap32 : case RISCV :: PseudoMaskedAtomicLoadAdd32 : case RISCV :: PseudoMaskedAtomicLoadSub32 : return 28 ; case RISCV :: PseudoMaskedAtomicLoadNand32 : return 32 ; case RISCV :: PseudoMaskedAtomicLoadMax32 : case RISCV :: PseudoMaskedAtomicLoadMin32 : return 44 ; case RISCV :: PseudoMaskedAtomicLoadUMax32 : case RISCV :: PseudoMaskedAtomicLoadUMin32 : return 36 ; case RISCV :: PseudoCmpXchg32 : case RISCV :: PseudoCmpXchg64 : return 16 ; case RISCV :: PseudoMaskedCmpXchg32 : return 32 ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const auto & TM = static_cast < const RISCVTargetMachine & > ( MF . getTarget ( ) ) ; return getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> void split_double_mode ( machine_mode mode , rtx operands [ ] , int num , rtx lo_half [ ] , rtx hi_half [ ] ) { machine_mode half_mode ; unsigned int byte ; switch ( mode ) { case TImode : half_mode = DImode ; break ; case DImode : half_mode = SImode ; break ; default : gcc_unreachable ( ) ; } byte = GET_MODE_SIZE ( half_mode ) ; while ( num -- ) { rtx op = operands [ num ] ; if ( MEM_P ( op ) ) { lo_half [ num ] = adjust_address ( op , half_mode , 0 ) ; hi_half [ num ] = adjust_address ( op , half_mode , byte ) ; } else { lo_half [ num ] = simplify_gen_subreg ( half_mode , op , GET_MODE ( op ) == VOIDmode ? mode : GET_MODE ( op ) , 0 ) ; hi_half [ num ] = simplify_gen_subreg ( half_mode , op , GET_MODE ( op ) == VOIDmode ? mode : GET_MODE ( op ) , byte ) ; } } } </s>

Split one or more double-mode RTL references into pairs of half-mode references . The RTL can be REG , offsettable MEM , integer constant , or CONST_DOUBLE . `` operands '' is a pointer to an array of double-mode RTLs to split and `` num '' is its length . lo_half and hi_half are output arrays that parallel `` operands '' .


<s> static void ix86_expand_divmod_libfunc ( rtx libfunc , machine_mode mode , rtx op0 , rtx op1 , rtx * quot_p , rtx * rem_p ) { rtx rem = assign_386_stack_local ( mode , SLOT_TEMP ) ; rtx quot = emit_library_call_value ( libfunc , NULL_RTX , LCT_NORMAL , mode , op0 , mode , op1 , mode , XEXP ( rem , 0 ) , Pmode ) ; * quot_p = quot ; * rem_p = rem ; } </s>


<s> void changedInstr ( MachineInstr & MI ) override { } </s>

This instruction was mutated in some way .


getTargetNodeName - This method returns the name of a target specific


<s>
bool
AArch64AsmPrinter
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
const
{
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
)
return
false
;
assert
(
!
MO
.
getSubReg
(
)
&&
"Subregs should be eliminated!"
)
;
MCOp
=
MCOperand
::
CreateReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
CreateImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_FPImmediate
:
{
assert
(
MO
.
getFPImm
(
)
->
isZero
(
)
&&
"Only fp imm 0.0 is supported"
)
;
MCOp
=
MCOperand
::
CreateFPImm
(
0.0
)
;
break
;
}
case
MachineOperand
::
MO_BlockAddress
:
MCOp
=
lowerSymbolOperand
(
MO
,
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
lowerSymbolOperand
(
MO
,
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
lowerSymbolOperand
(
MO
,
Mang
->
getSymbol
(
MO
.
getGlobal
(
)
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
CreateExpr
(
MCSymbolRefExpr
::
Create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
OutContext
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
MCOp
=
lowerSymbolOperand
(
MO
,
GetJTISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
MCOp
=
lowerSymbolOperand
(
MO
,
GetCPISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_RegisterMask
:
return
false
;
}
return
true
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


"Can't return value from vararg function in memory"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s>
static
void
recombine_lvx_pattern
(
rtx_insn
*
insn
,
del_info
*
to_delete
)
{
rtx
body
=
PATTERN
(
insn
)
;
gcc_assert
(
GET_CODE
(
body
)
==
SET
&&
(
GET_CODE
(
SET_SRC
(
body
)
)
==
VEC_SELECT
||
pattern_is_rotate64
(
body
)
)
&&
MEM_P
(
XEXP
(
SET_SRC
(
body
)
,
0
)
)
)
;
rtx
mem
=
XEXP
(
SET_SRC
(
body
)
,
0
)
;
rtx
base_reg
=
XEXP
(
mem
,
0
)
;
auto_vec
<
rtx_insn
*
>
and_insns
;
auto_vec
<
rtx
>
and_ops
;
bool
is_any_def_and
=
find_alignment_op
(
insn
,
base_reg
,
&
and_insns
,
&
and_ops
)
;
if
(
is_any_def_and
)
{
gcc_assert
(
and_insns
.
length
(
)
==
and_ops
.
length
(
)
)
;
df_ref
def
;
struct
df_insn_info
*
insn_info
=
DF_INSN_INFO_GET
(
insn
)
;
FOR_EACH_INSN_INFO_DEF
(
def
,
insn_info
)
{
struct
df_link
*
link
=
DF_REF_CHAIN
(
def
)
;
if
(
!
link
||
link
->
next
)
break
;
rtx_insn
*
swap_insn
=
DF_REF_INSN
(
link
->
ref
)
;
if
(
!
insn_is_swap_p
(
swap_insn
)
||
insn_is_load_p
(
swap_insn
)
||
insn_is_store_p
(
swap_insn
)
)
break
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace
=
true
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace_insn
=
swap_insn
;
rtx
new_reg
=
0
;
rtx
and_mask
=
0
;
for
(
unsigned
i
=
0
;
i
<
and_insns
.
length
(
)
;
i
++
)
{
rtx_insn
*
and_insn
=
and_insns
[
i
]
;
rtx
and_op
=
and_ops
[
i
]
;
rtx
and_base
=
XEXP
(
and_op
,
0
)
;
if
(
!
new_reg
)
{
new_reg
=
gen_reg_rtx
(
GET_MODE
(
and_base
)
)
;
and_mask
=
XEXP
(
and_op
,
1
)
;
}
rtx
copy
=
gen_rtx_SET
(
new_reg
,
and_base
)
;
rtx_insn
*
new_insn
=
emit_insn_after
(
copy
,
and_insn
)
;
set_block_for_insn
(
new_insn
,
BLOCK_FOR_INSN
(
and_insn
)
)
;
df_insn_rescan
(
new_insn
)
;
}
XEXP
(
mem
,
0
)
=
gen_rtx_AND
(
GET_MODE
(
new_reg
)
,
new_reg
,
and_mask
)
;
SET_SRC
(
body
)
=
mem
;
INSN_CODE
(
insn
)
=
1
;
df_insn_rescan
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"lvx opportunity found at %d\n"
,
INSN_UID
(
insn
)
)
;
}
}
}
</s>

If INSN is the load for an lvx pattern , put it in canonical form .


"Unhandled instruction encoding format!"

Targets should implement this to emit instructions .


<s> static void arm_reorg ( void ) { rtx insn ; HOST_WIDE_INT address = 0 ; Mfix * fix ; minipool_fix_head = minipool_fix_tail = NULL ; insn = get_insns ( ) ; gcc_assert ( GET_CODE ( insn ) == NOTE ) ; for ( insn = next_nonnote_insn ( insn ) ; insn ; insn = next_nonnote_insn ( insn ) ) { if ( TARGET_CIRRUS_FIX_INVALID_INSNS && ( arm_cirrus_insn_p ( insn ) || GET_CODE ( insn ) == JUMP_INSN || arm_memory_load_p ( insn ) ) ) cirrus_reorg ( insn ) ; if ( GET_CODE ( insn ) == BARRIER ) push_minipool_barrier ( insn , address ) ; else if ( INSN_P ( insn ) ) { rtx table ; note_invalid_constants ( insn , address , true ) ; address += get_attr_length ( insn ) ; if ( ( table = is_jump_table ( insn ) ) != NULL ) { address += get_jump_table_size ( table ) ; insn = table ; } } } fix = minipool_fix_head ; while ( fix ) { Mfix * ftmp ; Mfix * fdel ; Mfix * last_added_fix ; Mfix * last_barrier = NULL ; Mfix * this_fix ; while ( fix && GET_CODE ( fix -> insn ) == BARRIER ) fix = fix -> next ; if ( fix == NULL ) break ; last_added_fix = NULL ; for ( ftmp = fix ; ftmp ; ftmp = ftmp -> next ) { if ( GET_CODE ( ftmp -> insn ) == BARRIER ) { if ( ftmp -> address >= minipool_vector_head -> max_address ) break ; last_barrier = ftmp ; } else if ( ( ftmp -> minipool = add_minipool_forward_ref ( ftmp ) ) == NULL ) break ; last_added_fix = ftmp ; } if ( last_barrier != NULL ) { for ( fdel = last_barrier -> next ; fdel && fdel != ftmp ; fdel = fdel -> next ) { fdel -> minipool -> refcount -- ; fdel -> minipool = NULL ; } ftmp = last_barrier ; } else { HOST_WIDE_INT max_address ; gcc_assert ( ftmp ) ; max_address = minipool_vector_head -> max_address ; if ( ftmp -> address < max_address ) max_address = ftmp -> address ; last_barrier = create_fix_barrier ( last_added_fix , max_address ) ; } assign_minipool_offsets ( last_barrier ) ; while ( ftmp ) { if ( GET_CODE ( ftmp -> insn ) != BARRIER && ( ( ftmp -> minipool = add_minipool_backward_ref ( ftmp ) ) == NULL ) ) break ; ftmp = ftmp -> next ; } for ( this_fix = fix ; this_fix && ftmp != this_fix ; this_fix = this_fix -> next ) if ( GET_CODE ( this_fix -> insn ) != BARRIER ) { rtx addr = plus_constant ( gen_rtx_LABEL_REF ( VOIDmode , minipool_vector_label ) , this_fix -> minipool -> offset ) ; * this_fix -> loc = gen_rtx_MEM ( this_fix -> mode , addr ) ; } dump_minipool ( last_barrier -> insn ) ; fix = ftmp ; } after_arm_reorg = 1 ; obstack_free ( & minipool_obstack , minipool_startobj ) ; } </s>

Gcc puts the pool in the wrong place for ARM , since we can only load addresses a limited distance around the pc . We do some special munging to move the constant pool values to the correct point in the code .


<s> int mmix_print_operand_punct_valid_p ( int code ATTRIBUTE_UNUSED ) { return code == '+' || code == '.' ; } </s>


<s> static void frv_io_union ( struct frv_io * x , const struct frv_io * y ) { if ( x -> type != y -> type ) x -> type = FRV_IO_UNKNOWN ; if ( ! frv_same_doubleword_p ( x , y ) ) { x -> const_address = 0 ; x -> var_address = 0 ; } } </s>

Generalize I/O operation X so that it covers both X and Y .


<s> bool HexagonNoExtendOperand :: classof ( MCExpr const * E ) { return E -> getKind ( ) == MCExpr :: Target ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> bool PPCInstrInfo :: analyzeCompare ( const MachineInstr & MI , Register & SrcReg , Register & SrcReg2 , int64_t & Mask , int64_t & Value ) const { unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { default : return false ; case PPC :: CMPWI : case PPC :: CMPLWI : case PPC :: CMPDI : case PPC :: CMPLDI : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; Value = MI . getOperand ( 2 ) . getImm ( ) ; Mask = 0xFFFF ; return true ; case PPC :: CMPW : case PPC :: CMPLW : case PPC :: CMPD : case PPC :: CMPLD : case PPC :: FCMPUS : case PPC :: FCMPUD : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 2 ) . getReg ( ) ; Value = 0 ; Mask = 0 ; return true ; } } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s>
bool
PPCInstrInfo
::
SubsumesPredicate
(
ArrayRef
<
MachineOperand
>
Pred1
,
ArrayRef
<
MachineOperand
>
Pred2
)
const
{
assert
(
Pred1
.
size
(
)
==
2
&&
"Invalid PPC first predicate"
)
;
assert
(
Pred2
.
size
(
)
==
2
&&
"Invalid PPC second predicate"
)
;
if
(
Pred1
[
1
]
.
getReg
(
)
==
PPC
::
CTR8
||
Pred1
[
1
]
.
getReg
(
)
==
PPC
::
CTR
)
return
false
;
if
(
Pred2
[
1
]
.
getReg
(
)
==
PPC
::
CTR8
||
Pred2
[
1
]
.
getReg
(
)
==
PPC
::
CTR
)
return
false
;
if
(
Pred1
[
1
]
.
getReg
(
)
!=
Pred2
[
1
]
.
getReg
(
)
)
return
false
;
PPC
::
Predicate
P1
=
(
PPC
::
Predicate
)
Pred1
[
0
]
.
getImm
(
)
;
PPC
::
Predicate
P2
=
(
PPC
::
Predicate
)
Pred2
[
0
]
.
getImm
(
)
;
if
(
P1
==
P2
)
return
true
;
if
(
P1
==
PPC
::
PRED_LE
&&
(
P2
==
PPC
::
PRED_LT
||
P2
==
PPC
::
PRED_EQ
)
)
return
true
;
if
(
P1
==
PPC
::
PRED_GE
&&
(
P2
==
PPC
::
PRED_GT
||
P2
==
PPC
::
PRED_EQ
)
)
return
true
;
return
false
;
}
</s>

Returns true if the first specified predicate subsumes the second , e.g .


<s>
static
void
avr_move_bits
(
rtx
*
xop
,
unsigned
int
map
,
bool
fixp_p
,
int
*
plen
)
{
int
t_bit_src
=
1
;
for
(
int
b
=
0
;
b
<
8
;
b
++
)
for
(
int
bit_dest
=
0
;
bit_dest
<
8
;
bit_dest
++
)
{
int
bit_src
=
avr_map
(
map
,
bit_dest
)
;
if
(
b
!=
bit_src
||
bit_src
>=
8
||
(
bit_dest
==
bit_src
&&
!
fixp_p
)
)
continue
;
if
(
t_bit_src
!=
bit_src
)
{
t_bit_src
=
bit_src
;
xop
[
3
]
=
GEN_INT
(
bit_src
)
;
avr_asm_len
(
"bst %T1%T3"
,
xop
,
plen
,
1
)
;
}
xop
[
3
]
=
GEN_INT
(
bit_dest
)
;
avr_asm_len
(
"bld %T0%T3"
,
xop
,
plen
,
1
)
;
}
}
</s>

Insert bits from XOP [ 1 ] into XOP [ 0 ] according to MAP . XOP [ 0 ] and XOP [ 1 ] do n't overlap . If FIXP_P = true : Move all bits according to MAP using BLD/BST sequences . If FIXP_P = false : Just move the bit if its position in the destination is different to its source position .


"built-in function %qE not supported for MIPS16"

Expand builtin functions . This is called from TARGET_EXPAND_BUILTIN .


<s> const MachineBasicBlock :: const_iterator getNext ( ) const { return NextMI ; } </s>


<s> bool AArch64RegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { if ( MF . getFunction ( ) -> hasFnAttribute ( "no-realign-stack" ) ) return false ; return true ; } </s>

True if the stack can be realigned for the target .


<s>
void
Z80InstrInfo
::
reMaterialize
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DstReg
,
unsigned
SubIdx
,
const
MachineInstr
&
Orig
,
const
TargetRegisterInfo
&
TRI
)
const
{
if
(
!
Orig
.
modifiesRegister
(
Z80
::
F
,
&
TRI
)
||
MBB
.
computeRegisterLiveness
(
&
TRI
,
Z80
::
F
,
I
)
==
MachineBasicBlock
::
LQR_Dead
)
return
TargetInstrInfo
::
reMaterialize
(
MBB
,
I
,
DstReg
,
SubIdx
,
Orig
,
TRI
)
;
unsigned
Opc
;
int
Val
;
switch
(
Orig
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unexpected instruction!"
)
;
case
Z80
::
LD8r0
:
Opc
=
Z80
::
LD8ri
;
Val
=
0
;
break
;
case
Z80
::
LD24r0
:
Opc
=
Z80
::
LD24ri
;
Val
=
0
;
break
;
case
Z80
::
LD24r_1
:
Opc
=
Z80
::
LD24ri
;
Val
=
1
;
break
;
}
BuildMI
(
MBB
,
I
,
Orig
.
getDebugLoc
(
)
,
get
(
Opc
)
)
.
addReg
(
DstReg
,
RegState
::
Define
,
SubIdx
)
.
addImm
(
Val
)
;
}
</s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s> int pa_fpstore_bypass_p ( rtx_insn * out_insn , rtx_insn * in_insn ) { machine_mode store_mode ; machine_mode other_mode ; rtx set ; if ( recog_memoized ( in_insn ) < 0 || ( get_attr_type ( in_insn ) != TYPE_FPSTORE && get_attr_type ( in_insn ) != TYPE_FPSTORE_LOAD ) || recog_memoized ( out_insn ) < 0 ) return 0 ; store_mode = GET_MODE ( SET_SRC ( PATTERN ( in_insn ) ) ) ; set = single_set ( out_insn ) ; if ( ! set ) return 0 ; other_mode = GET_MODE ( SET_SRC ( set ) ) ; return ( GET_MODE_SIZE ( store_mode ) == GET_MODE_SIZE ( other_mode ) ) ; } </s>

Return nonzero if there is a bypass for the output of OUT_INSN and the fp store IN_INSN .


<s> BitVector TMS320C64XRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( TMS320C64X :: B15 ) ; Reserved . set ( TMS320C64X :: A15 ) ; Reserved . set ( TMS320C64X :: A14 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


"Could not generate addis value for fusion"

Emit the addis instruction that will be part of a fused instruction sequence .


<s> const uint16_t * AVRRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { CallingConv :: ID CC = MF -> getFunction ( ) . getCallingConv ( ) ; return ( ( CC == CallingConv :: AVR_INTR || CC == CallingConv :: AVR_SIGNAL ) ? CSR_Interrupts_SaveList : CSR_Normal_SaveList ) ; } </s>


<s> bool has ( unsigned R ) const { if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) return true ; MapType :: const_iterator F = Map . find ( R ) ; return F != Map . end ( ) ; } </s>

Tests whether a library function is available .


<s> static rtx mips_call_tls_get_addr ( rtx sym , enum mips_symbol_type type , rtx v0 ) { rtx insn , loc , tga , a0 ; a0 = gen_rtx_REG ( Pmode , GP_ARG_FIRST ) ; if ( ! mips_tls_symbol ) mips_tls_symbol = init_one_libfunc ( "__tls_get_addr" ) ; loc = mips_unspec_address ( sym , type ) ; start_sequence ( ) ; emit_insn ( gen_rtx_SET ( Pmode , a0 , gen_rtx_LO_SUM ( Pmode , pic_offset_table_rtx , loc ) ) ) ; tga = gen_rtx_MEM ( Pmode , mips_tls_symbol ) ; insn = emit_call_insn ( gen_call_value ( v0 , tga , const0_rtx , const0_rtx ) ) ; CONST_OR_PURE_CALL_P ( insn ) = 1 ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , v0 ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , a0 ) ; insn = get_insns ( ) ; end_sequence ( ) ; return insn ; } </s>

Return an instruction sequence that calls __tls_get_addr . SYM is the TLS symbol we are referencing and TYPE is the symbol type to use ( either global dynamic or local dynamic ) . V0 is an RTX for the return value location .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
Kind
==
k_Register
&&
"Invalid access!"
)
;
return
Reg
.
Num
;
}
</s>

Returns the register associated with this edge .


<s> unsigned AArch64InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case AArch64 :: STRWui : case AArch64 :: STRXui : case AArch64 :: STRBui : case AArch64 :: STRHui : case AArch64 :: STRSui : case AArch64 :: STRDui : case AArch64 :: STRQui : case AArch64 :: STR_PXI : case AArch64 :: STR_ZXI : case AArch64 :: STR_ZZXI : case AArch64 :: STR_ZZZXI : case AArch64 :: STR_ZZZZXI : if ( MI -> getOperand ( 0 ) . getSubReg ( ) == 0 && MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> static HOST_WIDE_INT compute_frame_size ( HOST_WIDE_INT size , HOST_WIDE_INT sa_size ) { if ( TARGET_ABI_OPEN_VMS ) return ALPHA_ROUND ( sa_size + ( alpha_procedure_type == PT_STACK ? 8 : 0 ) + size + crtl -> args . pretend_args_size ) ; else return ALPHA_ROUND ( crtl -> outgoing_args_size ) + sa_size + ALPHA_ROUND ( size + crtl -> args . pretend_args_size ) ; } </s>

Typical stack layout should looks like this after the function 's prologue : | | -- ^ | | \ | | | arguments saved | Increasing | | on the stack | addresses PARENT arg pointer - > | | / -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - | | - space for argument split between regs & stack -- CHILD | | \ < -- ( return address here ) | | other call | | saved registers | | / -- frame pointer - > | | \ ___ | | local | | | variables |f | | / |r -- |a | | \ |m | | outgoing |e | | arguments | | Decreasing ( hard ) frame pointer | | / | | addresses and stack pointer - > | | / _|_ | -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- V


<s> int mt_initial_elimination_offset ( int from , int to ) { mt_compute_frame_size ( get_frame_size ( ) ) ; if ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) return 0 ; else if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) return current_frame_info . total_size ; else if ( from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM ) return current_frame_info . total_size ; else gcc_unreachable ( ) ; } </s>


<s> inline const AMDGPURegisterInfo * AMDGPUSubtarget :: getRegisterInfo ( ) const { if ( getGeneration ( ) >= SOUTHERN_ISLANDS ) return static_cast < const SISubtarget * > ( this ) -> getRegisterInfo ( ) ; return static_cast < const R600Subtarget * > ( this ) -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool X86TTIImpl :: isLegalMaskedScatter ( Type * DataType ) { return isLegalMaskedGather ( DataType ) ; } </s>

Return true if the target supports masked scatter .


<s> void avr_cpu_cpp_builtins ( struct cpp_reader * pfile ) { builtin_define_std ( "AVR" ) ; if ( avr_arch -> macro ) cpp_define_formatted ( pfile , "__AVR_ARCH__=%s" , avr_arch -> macro ) ; if ( AVR_HAVE_RAMPD ) cpp_define ( pfile , "__AVR_HAVE_RAMPD__" ) ; if ( AVR_HAVE_RAMPX ) cpp_define ( pfile , "__AVR_HAVE_RAMPX__" ) ; if ( AVR_HAVE_RAMPY ) cpp_define ( pfile , "__AVR_HAVE_RAMPY__" ) ; if ( AVR_HAVE_RAMPZ ) cpp_define ( pfile , "__AVR_HAVE_RAMPZ__" ) ; if ( AVR_HAVE_ELPM ) cpp_define ( pfile , "__AVR_HAVE_ELPM__" ) ; if ( AVR_HAVE_ELPMX ) cpp_define ( pfile , "__AVR_HAVE_ELPMX__" ) ; if ( AVR_HAVE_MOVW ) cpp_define ( pfile , "__AVR_HAVE_MOVW__" ) ; if ( AVR_HAVE_LPMX ) cpp_define ( pfile , "__AVR_HAVE_LPMX__" ) ; if ( avr_arch -> asm_only ) cpp_define ( pfile , "__AVR_ASM_ONLY__" ) ; if ( AVR_HAVE_MUL ) { cpp_define ( pfile , "__AVR_ENHANCED__" ) ; cpp_define ( pfile , "__AVR_HAVE_MUL__" ) ; } if ( AVR_HAVE_JMP_CALL ) cpp_define ( pfile , "__AVR_HAVE_JMP_CALL__" ) ; if ( avr_arch -> have_jmp_call ) cpp_define ( pfile , "__AVR_MEGA__" ) ; if ( AVR_SHORT_CALLS ) cpp_define ( pfile , "__AVR_SHORT_CALLS__" ) ; if ( AVR_XMEGA ) cpp_define ( pfile , "__AVR_XMEGA__" ) ; if ( AVR_TINY ) { cpp_define ( pfile , "__AVR_TINY__" ) ; cpp_define_formatted ( pfile , "__AVR_TINY_PM_BASE_ADDRESS__=0x%x" , avr_arch -> flash_pm_offset ) ; } if ( avr_arch -> flash_pm_offset ) cpp_define_formatted ( pfile , "__AVR_PM_BASE_ADDRESS__=0x%x" , avr_arch -> flash_pm_offset ) ; if ( AVR_HAVE_EIJMP_EICALL ) { cpp_define ( pfile , "__AVR_HAVE_EIJMP_EICALL__" ) ; cpp_define ( pfile , "__AVR_3_BYTE_PC__" ) ; } else { cpp_define ( pfile , "__AVR_2_BYTE_PC__" ) ; } if ( AVR_HAVE_8BIT_SP ) cpp_define ( pfile , "__AVR_HAVE_8BIT_SP__" ) ; else cpp_define ( pfile , "__AVR_HAVE_16BIT_SP__" ) ; if ( AVR_HAVE_SPH ) cpp_define ( pfile , "__AVR_HAVE_SPH__" ) ; else cpp_define ( pfile , "__AVR_SP8__" ) ; if ( TARGET_NO_INTERRUPTS ) cpp_define ( pfile , "__NO_INTERRUPTS__" ) ; if ( TARGET_SKIP_BUG ) { cpp_define ( pfile , "__AVR_ERRATA_SKIP__" ) ; if ( AVR_HAVE_JMP_CALL ) cpp_define ( pfile , "__AVR_ERRATA_SKIP_JMP_CALL__" ) ; } if ( TARGET_RMW ) cpp_define ( pfile , "__AVR_ISA_RMW__" ) ; cpp_define_formatted ( pfile , "__AVR_SFR_OFFSET__=0x%x" , avr_arch -> sfr_offset ) ; cpp_define ( pfile , "__WITH_AVRLIBC__" ) ; if ( lang_GNU_C ( ) ) { for ( int i = 0 ; i < ADDR_SPACE_COUNT ; i ++ ) if ( ! ADDR_SPACE_GENERIC_P ( i ) && avr_addr_space_supported_p ( ( addr_space_t ) i ) ) { const char * name = avr_addrspace [ i ] . name ; char * Name = ( char * ) alloca ( 1 + strlen ( name ) ) ; cpp_define ( pfile , avr_toupper ( Name , name ) ) ; } } cpp_define ( pfile , "__BUILTIN_AVR_" # NAME ) ; cpp_define_formatted ( pfile , "__INT24_MAX__=8388607%s" , INT_TYPE_SIZE == 8 ? "LL" : "L" ) ; cpp_define ( pfile , "__INT24_MIN__=(-__INT24_MAX__-1)" ) ; cpp_define_formatted ( pfile , "__UINT24_MAX__=16777215%s" , INT_TYPE_SIZE == 8 ? "ULL" : "UL" ) ; } </s>

Worker function for TARGET_CPU_CPP_BUILTINS .


<s>
SDValue
AMDGPUTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
Op
.
getNode
(
)
->
dump
(
)
;
llvm_unreachable
(
"Custom lowering code for this"
"instruction is not implemented yet!"
)
;
break
;
case
ISD
::
SIGN_EXTEND_INREG
:
return
LowerSIGN_EXTEND_INREG
(
Op
,
DAG
)
;
case
ISD
::
CONCAT_VECTORS
:
return
LowerCONCAT_VECTORS
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_SUBVECTOR
:
return
LowerEXTRACT_SUBVECTOR
(
Op
,
DAG
)
;
case
ISD
::
FrameIndex
:
return
LowerFrameIndex
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
UDIVREM
:
return
LowerUDIVREM
(
Op
,
DAG
)
;
case
ISD
::
SDIVREM
:
return
LowerSDIVREM
(
Op
,
DAG
)
;
case
ISD
::
FREM
:
return
LowerFREM
(
Op
,
DAG
)
;
case
ISD
::
FCEIL
:
return
LowerFCEIL
(
Op
,
DAG
)
;
case
ISD
::
FTRUNC
:
return
LowerFTRUNC
(
Op
,
DAG
)
;
case
ISD
::
FRINT
:
return
LowerFRINT
(
Op
,
DAG
)
;
case
ISD
::
FNEARBYINT
:
return
LowerFNEARBYINT
(
Op
,
DAG
)
;
case
ISD
::
FROUND
:
return
LowerFROUND
(
Op
,
DAG
)
;
case
ISD
::
FFLOOR
:
return
LowerFFLOOR
(
Op
,
DAG
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerSINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
UINT_TO_FP
:
return
LowerUINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_SINT
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_UINT
(
Op
,
DAG
)
;
}
return
Op
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> void rs6000_emit_cbranch ( machine_mode mode , rtx operands [ ] ) { rtx condition_rtx , loc_ref ; condition_rtx = rs6000_generate_compare ( operands [ 0 ] , mode ) ; loc_ref = gen_rtx_LABEL_REF ( VOIDmode , operands [ 3 ] ) ; emit_jump_insn ( gen_rtx_SET ( pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , condition_rtx , loc_ref , pc_rtx ) ) ) ; } </s>

Emit a branch of kind CODE to location LOC .


<s> void MipsTargetELFStreamer :: finish ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; const MCObjectFileInfo & OFI = * MCA . getContext ( ) . getObjectFileInfo ( ) ; MCSection & TextSection = * OFI . getTextSection ( ) ; MCA . registerSection ( TextSection ) ; MCSection & DataSection = * OFI . getDataSection ( ) ; MCA . registerSection ( DataSection ) ; MCSection & BSSSection = * OFI . getBSSSection ( ) ; MCA . registerSection ( BSSSection ) ; TextSection . setAlignment ( std :: max ( 16u , TextSection . getAlignment ( ) ) ) ; DataSection . setAlignment ( std :: max ( 16u , DataSection . getAlignment ( ) ) ) ; BSSSection . setAlignment ( std :: max ( 16u , BSSSection . getAlignment ( ) ) ) ; const FeatureBitset & Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI_O32 ; else if ( getABI ( ) . IsN32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI2 ; if ( Features [ Mips :: FeatureGP64Bit ] ) { if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_32BITMODE ; } else if ( Features [ Mips :: FeatureMips64r2 ] || Features [ Mips :: FeatureMips64 ] ) EFlags |= ELF :: EF_MIPS_32BITMODE ; if ( EFlags & ELF :: EF_MIPS_CPIC && getABI ( ) . IsN64 ( ) ) EFlags |= ELF :: EF_MIPS_PIC ; MCA . setELFHeaderEFlags ( EFlags ) ; MipsELFStreamer & MEF = static_cast < MipsELFStreamer & > ( Streamer ) ; MEF . EmitMipsOptionRecords ( ) ; emitMipsAbiFlags ( ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


"expression value must be representable in 32 bits"

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


"Instructions with multiple result values not implemented"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool MVEGatherScatterLowering :: runOnFunction ( Function & F ) { if ( ! EnableMaskedGatherScatters ) return false ; auto & TPC = getAnalysis < TargetPassConfig > ( ) ; auto & TM = TPC . getTM < TargetMachine > ( ) ; auto * ST = & TM . getSubtarget < ARMSubtarget > ( F ) ; if ( ! ST -> hasMVEIntegerOps ( ) ) return false ; SmallVector < IntrinsicInst * , 4 > Gathers ; for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & I ) ; if ( II && II -> getIntrinsicID ( ) == Intrinsic :: masked_gather ) Gathers . push_back ( II ) ; } } if ( Gathers . empty ( ) ) return false ; for ( IntrinsicInst * I : Gathers ) lowerGather ( I ) ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool NVPTXPrologEpilogPass :: runOnMachineFunction ( MachineFunction & MF ) { const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const TargetFrameLowering & TFI = * STI . getFrameLowering ( ) ; const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; bool Modified = false ; calculateFrameObjectOffsets ( MF ) ; for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) { for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ++ I ) { MachineInstr * MI = I ; for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( ! MI -> getOperand ( i ) . isFI ( ) ) continue ; TRI . eliminateFrameIndex ( MI , 0 , i , nullptr ) ; Modified = true ; } } } TFI . emitPrologue ( MF ) ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( ! I -> empty ( ) && I -> back ( ) . isReturn ( ) ) TFI . emitEpilogue ( MF , * I ) ; } return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> static rtx xstormy16_function_value ( const_tree valtype , const_tree func ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode mode ; mode = TYPE_MODE ( valtype ) ; PROMOTE_MODE ( mode , 0 , valtype ) ; return gen_rtx_REG ( mode , RETURN_VALUE_REGNUM ) ; } </s>


<s> bool isFMAFasterThanFMulAndFAdd ( EVT VT ) const override { return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


"Relocation required in an instruction that we cannot encode!"

getMachineOpValue - Return binary encoding of operand .


<s> yaml :: MachineFunctionInfo * AArch64TargetMachine :: convertFuncInfoToYAML ( const MachineFunction & MF ) const { const auto * MFI = MF . getInfo < AArch64FunctionInfo > ( ) ; return new yaml :: AArch64FunctionInfo ( * MFI ) ; } </s>

Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo .


<s> static ARMOperand * CreateMem ( unsigned BaseRegNum , const MCConstantExpr * OffsetImm , unsigned OffsetRegNum , ARM_AM :: ShiftOpc ShiftType , unsigned ShiftImm , unsigned Alignment , bool isNegative , SMLoc S , SMLoc E , SMLoc AlignmentLoc = SMLoc ( ) ) { ARMOperand * Op = new ARMOperand ( k_Memory ) ; Op -> Memory . BaseRegNum = BaseRegNum ; Op -> Memory . OffsetImm = OffsetImm ; Op -> Memory . OffsetRegNum = OffsetRegNum ; Op -> Memory . ShiftType = ShiftType ; Op -> Memory . ShiftImm = ShiftImm ; Op -> Memory . Alignment = Alignment ; Op -> Memory . isNegative = isNegative ; Op -> StartLoc = S ; Op -> EndLoc = E ; Op -> AlignmentLoc = AlignmentLoc ; return Op ; } </s>


<s> std :: pair < unsigned , const TargetRegisterClass * > SPUTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'b' : case 'r' : if ( VT == MVT :: i64 ) return std :: make_pair ( 0U , SPU :: R64CRegisterClass ) ; return std :: make_pair ( 0U , SPU :: R32CRegisterClass ) ; case 'f' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , SPU :: R32FPRegisterClass ) ; else if ( VT == MVT :: f64 ) return std :: make_pair ( 0U , SPU :: R64FPRegisterClass ) ; break ; case 'v' : return std :: make_pair ( 0U , SPU :: GPRCRegisterClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> void Thumb2InstrInfo :: ReplaceTailWithBranchTo ( MachineBasicBlock :: iterator Tail , MachineBasicBlock * NewDest ) const { MachineBasicBlock * MBB = Tail -> getParent ( ) ; ARMFunctionInfo * AFI = MBB -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; if ( ! AFI -> hasITBlocks ( ) ) { TargetInstrInfoImpl :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; return ; } unsigned PredReg = 0 ; ARMCC :: CondCodes CC = getInstrPredicate ( Tail , PredReg ) ; MachineBasicBlock :: iterator MBBI = Tail ; if ( CC != ARMCC :: AL ) -- MBBI ; TargetInstrInfoImpl :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; if ( CC != ARMCC :: AL ) { MachineBasicBlock :: iterator E = MBB -> begin ( ) ; unsigned Count = 4 ; while ( Count && MBBI != E ) { if ( MBBI -> isDebugValue ( ) ) { -- MBBI ; continue ; } if ( MBBI -> getOpcode ( ) == ARM :: t2IT ) { unsigned Mask = MBBI -> getOperand ( 1 ) . getImm ( ) ; if ( Count == 4 ) MBBI -> eraseFromParent ( ) ; else { unsigned MaskOn = 1 << Count ; unsigned MaskOff = ~ ( MaskOn - 1 ) ; MBBI -> getOperand ( 1 ) . setImm ( ( Mask & MaskOff ) | MaskOn ) ; } return ; } -- MBBI ; -- Count ; } } } </s>

Delete the instruction OldInst and everything after it , replacing it with an unconditional branch to NewDest .


<s> static unsigned long arm_compute_save_reg0_reg12_mask ( void ) { unsigned long func_type = arm_current_func_type ( ) ; unsigned long save_reg_mask = 0 ; unsigned int reg ; if ( IS_INTERRUPT ( func_type ) ) { unsigned int max_reg ; if ( ARM_FUNC_TYPE ( func_type ) == ARM_FT_FIQ ) max_reg = 7 ; else max_reg = 12 ; for ( reg = 0 ; reg <= max_reg ; reg ++ ) if ( reg_needs_saving_p ( reg ) ) save_reg_mask |= ( 1 << reg ) ; if ( PIC_REGISTER_MAY_NEED_SAVING && crtl -> uses_pic_offset_table ) save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM ; } else if ( IS_VOLATILE ( func_type ) ) { if ( frame_pointer_needed ) save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM ; if ( df_regs_ever_live_p ( ARM_HARD_FRAME_POINTER_REGNUM ) ) save_reg_mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM ; if ( df_regs_ever_live_p ( THUMB_HARD_FRAME_POINTER_REGNUM ) ) save_reg_mask |= 1 << THUMB_HARD_FRAME_POINTER_REGNUM ; } else { for ( reg = 0 ; reg <= 11 ; reg ++ ) if ( df_regs_ever_live_p ( reg ) && callee_saved_reg_p ( reg ) ) save_reg_mask |= ( 1 << reg ) ; if ( frame_pointer_needed ) save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM ; if ( PIC_REGISTER_MAY_NEED_SAVING && ( df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) || crtl -> uses_pic_offset_table ) ) save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM ; if ( IS_STACKALIGN ( func_type ) ) save_reg_mask |= 1 ; } if ( crtl -> calls_eh_return ) { unsigned int i ; for ( i = 0 ; ; i ++ ) { reg = EH_RETURN_DATA_REGNO ( i ) ; if ( reg == INVALID_REGNUM ) break ; save_reg_mask |= 1 << reg ; } } return save_reg_mask ; } </s>

Compute the register save mask for registers 0 through 12 inclusive . This code is used by arm_compute_save_reg_mask .


<s>
bool
SIFoldOperands
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
const
SIInstrInfo
*
TII
=
static_cast
<
const
SIInstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
const
SIRegisterInfo
&
TRI
=
TII
->
getRegisterInfo
(
)
;
for
(
MachineFunction
::
iterator
BI
=
MF
.
begin
(
)
,
BE
=
MF
.
end
(
)
;
BI
!=
BE
;
++
BI
)
{
MachineBasicBlock
&
MBB
=
*
BI
;
MachineBasicBlock
::
iterator
I
,
Next
;
for
(
I
=
MBB
.
begin
(
)
;
I
!=
MBB
.
end
(
)
;
I
=
Next
)
{
Next
=
std
::
next
(
I
)
;
MachineInstr
&
MI
=
*
I
;
if
(
!
isSafeToFold
(
MI
.
getOpcode
(
)
)
)
continue
;
unsigned
OpSize
=
TII
->
getOpSize
(
MI
,
1
)
;
MachineOperand
&
OpToFold
=
MI
.
getOperand
(
1
)
;
bool
FoldingImm
=
OpToFold
.
isImm
(
)
;
if
(
!
FoldingImm
&&
!
OpToFold
.
isReg
(
)
)
continue
;
if
(
FoldingImm
&&
!
TII
->
isInlineConstant
(
OpToFold
,
OpSize
)
&&
!
MRI
.
hasOneUse
(
MI
.
getOperand
(
0
)
.
getReg
(
)
)
)
continue
;
if
(
OpToFold
.
isReg
(
)
&&
(
!
TargetRegisterInfo
::
isVirtualRegister
(
OpToFold
.
getReg
(
)
)
||
OpToFold
.
getSubReg
(
)
)
)
continue
;
SmallVector
<
MachineInstr
*
,
4
>
CopiesToReplace
;
std
::
vector
<
FoldCandidate
>
FoldList
;
for
(
MachineRegisterInfo
::
use_iterator
Use
=
MRI
.
use_begin
(
MI
.
getOperand
(
0
)
.
getReg
(
)
)
,
E
=
MRI
.
use_end
(
)
;
Use
!=
E
;
++
Use
)
{
MachineInstr
*
UseMI
=
Use
->
getParent
(
)
;
foldOperand
(
OpToFold
,
UseMI
,
Use
.
getOperandNo
(
)
,
FoldList
,
CopiesToReplace
,
TII
,
TRI
,
MRI
)
;
}
for
(
MachineInstr
*
Copy
:
CopiesToReplace
)
Copy
->
addImplicitDefUseOperands
(
MF
)
;
for
(
FoldCandidate
&
Fold
:
FoldList
)
{
if
(
updateOperand
(
Fold
,
TRI
)
)
{
if
(
!
Fold
.
isImm
(
)
)
{
assert
(
Fold
.
OpToFold
&&
Fold
.
OpToFold
->
isReg
(
)
)
;
MRI
.
clearKillFlags
(
Fold
.
OpToFold
->
getReg
(
)
)
;
}
DEBUG
(
dbgs
(
)
<<
"Folded source from "
<<
MI
<<
" into OpNo "
<<
Fold
.
UseOpNo
<<
" of "
<<
*
Fold
.
UseMI
<<
'\n'
)
;
}
}
}
}
return
false
;
}
</s>


<s> bool X86TargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createX86ISelDag ( * this , OptLevel ) ) ; if ( EnableFastISel ) PM . add ( createDeadMachineInstructionElimPass ( ) ) ; PM . add ( createX87FPRegKillInserterPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s>
static
const
char
*
avr_out_store_psi
(
rtx_insn
*
insn
,
rtx
*
op
,
int
*
plen
)
{
rtx
dest
=
op
[
0
]
;
rtx
src
=
op
[
1
]
;
rtx
base
=
XEXP
(
dest
,
0
)
;
int
reg_base
=
true_regnum
(
base
)
;
if
(
CONSTANT_ADDRESS_P
(
base
)
)
{
int
n_words
=
AVR_TINY
3
:
6
;
return
avr_asm_len
(
"sts %m0,%A1"
CR_TAB
"sts %m0+1,%B1"
CR_TAB
"sts %m0+2,%C1"
,
op
,
plen
,
n_words
)
;
}
if
(
reg_base
>
0
)
{
if
(
AVR_TINY
)
return
avr_out_store_psi_reg_no_disp_tiny
(
insn
,
op
,
plen
)
;
if
(
reg_base
==
REG_X
)
{
gcc_assert
(
!
reg_overlap_mentioned_p
(
base
,
src
)
)
;
avr_asm_len
(
"st %0+,%A1"
CR_TAB
"st %0+,%B1"
CR_TAB
"st %0,%C1"
,
op
,
plen
,
3
)
;
if
(
!
reg_unused_after
(
insn
,
base
)
)
avr_asm_len
(
"sbiw r26,2"
,
op
,
plen
,
1
)
;
return
""
;
}
else
return
avr_asm_len
(
"st %0,%A1"
CR_TAB
"std %0+1,%B1"
CR_TAB
"std %0+2,%C1"
,
op
,
plen
,
3
)
;
}
else
if
(
GET_CODE
(
base
)
==
PLUS
)
{
int
disp
=
INTVAL
(
XEXP
(
base
,
1
)
)
;
if
(
AVR_TINY
)
return
avr_out_store_psi_reg_disp_tiny
(
insn
,
op
,
plen
)
;
reg_base
=
REGNO
(
XEXP
(
base
,
0
)
)
;
if
(
disp
>
MAX_LD_OFFSET
(
GET_MODE
(
dest
)
)
)
{
if
(
reg_base
!=
REG_Y
)
fatal_insn
(
"incorrect insn:"
,
insn
)
;
if
(
disp
<=
63
+
MAX_LD_OFFSET
(
GET_MODE
(
dest
)
)
)
return
avr_asm_len
(
"adiw r28,%o0-61"
CR_TAB
"std Y+61,%A1"
CR_TAB
"std Y+62,%B1"
CR_TAB
"std Y+63,%C1"
CR_TAB
"sbiw r28,%o0-61"
,
op
,
plen
,
5
)
;
return
avr_asm_len
(
"subi r28,lo8(-%o0)"
CR_TAB
"sbci r29,hi8(-%o0)"
CR_TAB
"st Y,%A1"
CR_TAB
"std Y+1,%B1"
CR_TAB
"std Y+2,%C1"
CR_TAB
"subi r28,lo8(%o0)"
CR_TAB
"sbci r29,hi8(%o0)"
,
op
,
plen
,
7
)
;
}
if
(
reg_base
==
REG_X
)
{
gcc_assert
(
!
reg_overlap_mentioned_p
(
XEXP
(
base
,
0
)
,
src
)
)
;
avr_asm_len
(
"adiw r26,%o0"
CR_TAB
"st X+,%A1"
CR_TAB
"st X+,%B1"
CR_TAB
"st X,%C1"
,
op
,
plen
,
4
)
;
if
(
!
reg_unused_after
(
insn
,
XEXP
(
base
,
0
)
)
)
avr_asm_len
(
"sbiw r26,%o0+2"
,
op
,
plen
,
1
)
;
return
""
;
}
return
avr_asm_len
(
"std %A0,%A1"
CR_TAB
"std %B0,%B1"
CR_TAB
"std %C0,%C1"
,
op
,
plen
,
3
)
;
}
else
if
(
GET_CODE
(
base
)
==
PRE_DEC
)
return
avr_asm_len
(
"st %0,%C1"
CR_TAB
"st %0,%B1"
CR_TAB
"st %0,%A1"
,
op
,
plen
,
3
)
;
else
if
(
GET_CODE
(
base
)
==
POST_INC
)
return
avr_asm_len
(
"st %0,%A1"
CR_TAB
"st %0,%B1"
CR_TAB
"st %0,%C1"
,
op
,
plen
,
3
)
;
fatal_insn
(
"unknown move insn:"
,
insn
)
;
return
""
;
}
</s>

Handle store of 24-bit type from register or zero to memory .


<s>
std
::
string
getNodeLabel
(
const
SCANode
*
N
,
const
SpillCostAnalysisGraph
&
G
)
{
MCGNode
*
mcgNode
=
N
->
getMCGNode
(
)
;
std
::
string
tmp
;
raw_string_ostream
s
(
tmp
)
;
if
(
mcgNode
->
isUnknown
(
)
)
s
<<
"<UNKNOWN-"
<<
*
mcgNode
->
getType
(
)
<<
">"
;
else
{
s
<<
mcgNode
->
getMF
(
)
->
getFunction
(
)
->
getName
(
)
;
}
s
<<
(
N
->
hasCallFreePath
(
)
"* (occ:"
:
" (occ:"
)
<<
N
->
getOccupancy
(
)
<<
", spill:"
<<
N
->
getSpillCost
(
)
<<
")\n"
<<
"[rem:"
<<
N
->
getRemainingOccupancy
(
)
<<
", maxdisp:"
<<
N
->
getMaxDisplacement
(
)
<<
"]"
;
return
s
.
str
(
)
;
}
</s>

Print a DDG node either in concise form ( -ddg-dot-only ) or verbose mode ( -ddg-dot ) .

Patmos
"<UNKNOWN-"
">"
"* (occ:"
" (occ:"
", spill:"
")\n"
"[rem:"
", maxdisp:"
"]"


"unimplemented opcode in encodeInstruction()"

Encode the given Inst to bytes and append to CB .


<s> void X86TargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( Subtarget . getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) || Subtarget . getTargetTriple ( ) . isWindowsItaniumEnvironment ( ) ) { M . getOrInsertGlobal ( "__security_cookie" , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; FunctionCallee SecurityCheckCookie = M . getOrInsertFunction ( "__security_check_cookie" , Type :: getVoidTy ( M . getContext ( ) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; if ( Function * F = dyn_cast < Function > ( SecurityCheckCookie . getCallee ( ) ) ) { F -> setCallingConv ( CallingConv :: X86_FastCall ) ; F -> addAttribute ( 1 , Attribute :: AttrKind :: InReg ) ; } return ; } StringRef GuardMode = M . getStackProtectorGuard ( ) ; if ( ( GuardMode == "tls" || GuardMode . empty ( ) ) && hasStackGuardSlotTLS ( Subtarget . getTargetTriple ( ) ) ) return ; TargetLowering :: insertSSPDeclarations ( M ) ; } </s>

Inserts necessary declarations for SSP ( stack protection ) purpose .


<s> static void iq2000_emit_frame_related_store ( rtx mem , rtx reg , HOST_WIDE_INT offset ) { rtx dwarf_address = plus_constant ( stack_pointer_rtx , offset ) ; rtx dwarf_mem = gen_rtx_MEM ( GET_MODE ( reg ) , dwarf_address ) ; iq2000_annotate_frame_insn ( emit_move_insn ( mem , reg ) , gen_rtx_SET ( GET_MODE ( reg ) , dwarf_mem , reg ) ) ; } </s>

Emit a move instruction that stores REG in MEM . Make the instruction frame related and note that it stores REG at ( SP + OFFSET ) .


<s> bool sh_cfun_attr_renesas_p ( void ) { return sh_attr_renesas_p ( current_function_decl ) ; } </s>

True if __attribute__ ( ( renesas ) ) or -mrenesas , for the current function .


<s> const unsigned & getLoc ( ) const { return loc ; } </s>

Get the source location of the point where the field was defined .


<s> const MipsTargetLowering * MipsTargetLowering :: create ( const MipsTargetMachine & TM , const MipsSubtarget & STI ) { if ( STI . inMips16Mode ( ) ) return createMips16TargetLowering ( TM , STI ) ; return createMipsSETargetLowering ( TM , STI ) ; } </s>


<s> void LanaiMCCodeEmitter :: encodeInstruction ( const MCInst & Inst , raw_ostream & Ostream , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & SubtargetInfo ) const { unsigned Value = getBinaryCodeForInstr ( Inst , Fixups , SubtargetInfo ) ; ++ MCNumEmitted ; for ( int i = ( 4 - 1 ) * 8 ; i >= 0 ; i -= 8 ) Ostream << static_cast < char > ( ( Value >> i ) & 0xff ) ; } </s>


<s>
void
RISCVDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
MVT
XLenVT
=
Subtarget
->
getXLenVT
(
)
;
SDLoc
DL
(
Node
)
;
EVT
VT
=
Node
->
getValueType
(
0
)
;
switch
(
Opcode
)
{
case
ISD
::
Constant
:
{
auto
ConstNode
=
cast
<
ConstantSDNode
>
(
Node
)
;
if
(
VT
==
XLenVT
&&
ConstNode
->
isNullValue
(
)
)
{
SDValue
New
=
CurDAG
->
getCopyFromReg
(
CurDAG
->
getEntryNode
(
)
,
SDLoc
(
Node
)
,
RISCV
::
X0
,
XLenVT
)
;
ReplaceNode
(
Node
,
New
.
getNode
(
)
)
;
return
;
}
int64_t
Imm
=
ConstNode
->
getSExtValue
(
)
;
if
(
XLenVT
==
MVT
::
i64
)
{
ReplaceNode
(
Node
,
selectImm
(
CurDAG
,
SDLoc
(
Node
)
,
Imm
,
XLenVT
)
)
;
return
;
}
break
;
}
case
ISD
::
FrameIndex
:
{
SDValue
Imm
=
CurDAG
->
getTargetConstant
(
0
,
DL
,
XLenVT
)
;
int
FI
=
cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
VT
)
;
ReplaceNode
(
Node
,
CurDAG
->
getMachineNode
(
RISCV
::
ADDI
,
DL
,
VT
,
TFI
,
Imm
)
)
;
return
;
}
case
ISD
::
SRL
:
{
if
(
!
Subtarget
->
is64Bit
(
)
)
break
;
SDValue
Op0
=
Node
->
getOperand
(
0
)
;
SDValue
Op1
=
Node
->
getOperand
(
1
)
;
uint64_t
Mask
;
if
(
Op1
.
getOpcode
(
)
==
ISD
::
Constant
&&
isConstantMask
(
Op0
.
getNode
(
)
,
Mask
)
)
{
uint64_t
ShAmt
=
cast
<
ConstantSDNode
>
(
Op1
.
getNode
(
)
)
->
getZExtValue
(
)
;
if
(
(
Mask
|
maskTrailingOnes
<
uint64_t
>
(
ShAmt
)
)
==
0xffffffff
)
{
SDValue
ShAmtVal
=
CurDAG
->
getTargetConstant
(
ShAmt
,
SDLoc
(
Node
)
,
XLenVT
)
;
CurDAG
->
SelectNodeTo
(
Node
,
RISCV
::
SRLIW
,
XLenVT
,
Op0
.
getOperand
(
0
)
,
ShAmtVal
)
;
return
;
}
}
}
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> static void mips_setup_incoming_varargs ( cumulative_args_t cum , const function_arg_info & arg , int * pretend_size ATTRIBUTE_UNUSED , int no_rtl ) { CUMULATIVE_ARGS local_cum ; int gp_saved , fp_saved ; local_cum = * get_cumulative_args ( cum ) ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) ) mips_function_arg_advance ( pack_cumulative_args ( & local_cum ) , arg ) ; gp_saved = MAX_ARGS_IN_REGISTERS - local_cum . num_gprs ; fp_saved = ( EABI_FLOAT_VARARGS_P ? MAX_ARGS_IN_REGISTERS - local_cum . num_fprs : 0 ) ; if ( ! no_rtl ) { if ( gp_saved > 0 ) { rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , REG_PARM_STACK_SPACE ( cfun -> decl ) - gp_saved * UNITS_PER_WORD ) ; mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . num_gprs + GP_ARG_FIRST , mem , gp_saved ) ; } if ( fp_saved > 0 ) { machine_mode mode ; int off , i ; off = ROUND_DOWN ( - gp_saved * UNITS_PER_WORD , UNITS_PER_FPVALUE ) ; off -= fp_saved * UNITS_PER_FPREG ; mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode ; for ( i = local_cum . num_fprs ; i < MAX_ARGS_IN_REGISTERS ; i += MAX_FPRS_PER_FMT ) { rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , off ) ; mem = gen_frame_mem ( mode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; mips_emit_move ( mem , gen_rtx_REG ( mode , FP_ARG_FIRST + i ) ) ; off += UNITS_PER_HWFPVALUE ; } } } if ( REG_PARM_STACK_SPACE ( cfun -> decl ) == 0 ) cfun -> machine -> varargs_size = ( gp_saved * UNITS_PER_WORD + fp_saved * UNITS_PER_FPREG ) ; } </s>


<s> static int avr_num_arg_regs ( enum machine_mode mode , tree type ) { int size ; if ( mode == BLKmode ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; return ( size + 1 ) & ~ 1 ; } </s>

Returns the number of registers to allocate for a function argument .


<s> bool HSAILInstrInfo :: isCoalescableExtInstr ( const MachineInstr & MI , unsigned & SrcReg , unsigned & DstReg , unsigned & SubIdx ) const { return false ; } </s>

isCoalescableExtInstr - Return true if the instruction is a `` coalescable '' extension instruction .


<s> bool preferZeroCompareBranch ( ) const override { return true ; } </s>

Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare .


<s> bool isMem ( ) const override { return Kind == k_Memory ; } </s>


<s> static bool mips_expand_vpc_loongson_bcast ( struct expand_vec_perm_d * d ) { unsigned i , elt ; rtx t0 , t1 ; if ( ! ( TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS ) ) return false ; if ( d -> vmode != V8QImode ) return false ; if ( ! d -> one_vector_p ) return false ; elt = d -> perm [ 0 ] ; for ( i = 1 ; i < 8 ; ++ i ) if ( d -> perm [ i ] != elt ) return false ; if ( d -> testing_p ) return true ; t0 = gen_reg_rtx ( V8QImode ) ; if ( elt < 4 ) emit_insn ( gen_loongson_punpcklbh ( t0 , d -> op0 , d -> op0 ) ) ; else emit_insn ( gen_loongson_punpckhbh ( t0 , d -> op0 , d -> op0 ) ) ; elt &= 3 ; elt *= 0x55 ; t1 = gen_reg_rtx ( V4HImode ) ; emit_insn ( gen_loongson_pshufh ( t1 , gen_lowpart ( V4HImode , t0 ) , force_reg ( SImode , GEN_INT ( elt ) ) ) ) ; emit_move_insn ( d -> target , gen_lowpart ( V8QImode , t1 ) ) ; return true ; } </s>

Recognize broadcast patterns for the Loongson .


<s>
static
void
adjust_splat
(
rtx_insn
*
insn
)
{
rtx
body
=
PATTERN
(
insn
)
;
rtx
unspec
=
XEXP
(
body
,
1
)
;
int
half_elts
=
GET_MODE_NUNITS
(
GET_MODE
(
unspec
)
)
>>
1
;
int
lane
=
INTVAL
(
XVECEXP
(
unspec
,
0
,
1
)
)
;
lane
=
lane
>=
half_elts
lane
half_elts
:
lane
+
half_elts
;
XVECEXP
(
unspec
,
0
,
1
)
=
GEN_INT
(
lane
)
;
INSN_CODE
(
insn
)
=
1
;
df_insn_rescan
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Changing lane for splat %d\n"
,
INSN_UID
(
insn
)
)
;
}
</s>

Given OP that contains a vector direct-splat operation , adjust the index of the source lane to account for the doubleword swap .


<s> static MCAsmInfo * createMCAsmInfo ( const Target & T , StringRef TT ) { Triple TheTriple ( TT ) ; switch ( TheTriple . getOS ( ) ) { default : return new MBlazeMCAsmInfo ( ) ; } } </s>

createMCAsmInfo - Create a MCAsmInfo implementation for the specified target triple .


"interrupt and naked attributes are not compatible"

"only DWARF debug format is supported for interrupt "

Set the func_type field from the function FNDECL .


<s>
bool
MipsConstantIslands
::
isBBInRange
(
MachineInstr
*
MI
,
MachineBasicBlock
*
DestBB
,
unsigned
MaxDisp
)
{
unsigned
PCAdj
=
4
;
unsigned
BrOffset
=
getOffsetOf
(
MI
)
+
PCAdj
;
unsigned
DestOffset
=
BBInfo
[
DestBB
->
getNumber
(
)
]
.
Offset
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Branch of destination "
<<
printMBBReference
(
*
DestBB
)
<<
" from "
<<
printMBBReference
(
*
MI
->
getParent
(
)
)
<<
" max delta="
<<
MaxDisp
<<
" from "
<<
getOffsetOf
(
MI
)
<<
" to "
<<
DestOffset
<<
" offset "
<<
int
(
DestOffset
BrOffset
)
<<
"\t"
<<
*
MI
)
;
if
(
BrOffset
<=
DestOffset
)
{
if
(
DestOffset
BrOffset
<=
MaxDisp
)
return
true
;
}
else
{
if
(
BrOffset
DestOffset
<=
MaxDisp
)
return
true
;
}
return
false
;
}
</s>

isBBInRange - Returns true if the distance between specific MI and specific BB can fit in MI 's displacement field .

Mips
Mips
4
"Branch of destination "
" from "
" max delta="
" from "
" to "
" offset "
"\t"


<s> SDNode * PPCDAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * PPCSubTarget -> getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; const Module * M = MF -> getFunction ( ) . getParent ( ) ; DebugLoc dl ; if ( PPCLowering -> getPointerTy ( CurDAG -> getDataLayout ( ) ) == MVT :: i32 ) { if ( PPCSubTarget -> isTargetELF ( ) ) { GlobalBaseReg = PPC :: R30 ; if ( M -> getPICLevel ( ) == PICLevel :: SmallPIC ) { BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MoveGOTtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; MF -> getInfo < PPCFunctionInfo > ( ) -> setUsesPICBase ( true ) ; } else { BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; unsigned TempReg = RegInfo -> createVirtualRegister ( & PPC :: GPRCRegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: UpdateGBR ) , GlobalBaseReg ) . addReg ( TempReg , RegState :: Define ) . addReg ( GlobalBaseReg ) ; MF -> getInfo < PPCFunctionInfo > ( ) -> setUsesPICBase ( true ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: GPRC_and_GPRC_NOR0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: G8RC_and_G8RC_NOX0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR8 ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR8 ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , PPCLowering -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

PowerPC PPC PPC PPC MVT::i32 PPC PPC::R30 PPC::MoveGOTtoLR PPC::MFLR PPC PPC::MovePCtoLR PPC::MFLR PPC::GPRCRegClass PPC::UpdateGBR PPC PPC::GPRC_and_GPRC_NOR0RegClass PPC::MovePCtoLR PPC::MFLR PPC::G8RC_and_G8RC_NOX0RegClass PPC::MovePCtoLR8 PPC::MFLR8 PPC


<s>
void
DLXDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
return
;
}
EVT
VT
=
Node
->
getValueType
(
0
)
;
switch
(
Opcode
)
{
case
ISD
::
Constant
:
if
(
VT
==
MVT
::
i32
)
{
ConstantSDNode
*
ConstNode
=
cast
<
ConstantSDNode
>
(
Node
)
;
if
(
ConstNode
->
isNullValue
(
)
)
{
SDValue
New
=
CurDAG
->
getCopyFromReg
(
CurDAG
->
getEntryNode
(
)
,
SDLoc
(
Node
)
,
DLX
::
R0
,
MVT
::
i32
)
;
return
ReplaceNode
(
Node
,
New
.
getNode
(
)
)
;
}
if
(
ConstNode
->
isAllOnesValue
(
)
)
{
SDValue
New
=
CurDAG
->
getCopyFromReg
(
CurDAG
->
getEntryNode
(
)
,
SDLoc
(
Node
)
,
DLX
::
R1
,
MVT
::
i32
)
;
return
ReplaceNode
(
Node
,
New
.
getNode
(
)
)
;
}
}
break
;
case
ISD
::
FrameIndex
:
selectFrameIndex
(
Node
)
;
return
;
default
:
break
;
}
SelectCode
(
Node
)
;
}
</s>


" is return block without RETURN instr\n"

Convenience function that returns true if the block ends in a return instruction .


<s> bool ARMFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) return true ; return ( RegInfo -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Hexagon early if conversion"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void LC3PassConfig :: addPreEmitPass ( ) { } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


"Unexpected instruction for custom inserter!"

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static void emitSPUpdate ( bool isARM , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , const ARMBaseInstrInfo & TII , int NumBytes , unsigned MIFlags = MachineInstr :: NoFlags , ARMCC :: CondCodes Pred = ARMCC :: AL , unsigned PredReg = 0 ) { emitRegPlusImmediate ( isARM , MBB , MBBI , dl , TII , ARM :: SP , ARM :: SP , NumBytes , MIFlags , Pred , PredReg ) ; } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .

ARM ARM ARM ARMCC::CondCodes ARMCC::AL 0 ARM ARM::SP ARM::SP


<s> static inline bool fp_valid_at ( HOST_WIDE_INT cfa_offset ) { const struct machine_frame_state & fs = cfun -> machine -> fs ; if ( fs . sp_realigned && cfa_offset > fs . sp_realigned_fp_last ) { gcc_assert ( cfa_offset >= fs . sp_realigned_offset ) ; return false ; } return fs . fp_valid ; } </s>

Determine if the frame pointer is valid for accessing the CFA_OFFSET in the frame save area . The register is saved at CFA - CFA_OFFSET .


<s> bool AMDGPUCallLowering :: canLowerReturn ( MachineFunction & MF , CallingConv :: ID CallConv , SmallVectorImpl < BaseArgInfo > & Outs , bool IsVarArg ) const { if ( AMDGPU :: isEntryFunctionCC ( CallConv ) ) return true ; SmallVector < CCValAssign , 16 > ArgLocs ; const SITargetLowering & TLI = * getTLI < SITargetLowering > ( ) ; CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , MF . getFunction ( ) . getContext ( ) ) ; return checkReturn ( CCInfo , Outs , TLI . CCAssignFnForReturn ( CallConv , IsVarArg ) ) ; } </s>

This hook must be implemented to check whether the return values described by Outs can fit into the return registers .

AMDGPU AMDGPU AMDGPU::isEntryFunctionCC 16 SI SI


<s> bool ARMLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { const TargetMachine & TM = Fn . getTarget ( ) ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; TII = TM . getInstrInfo ( ) ; TRI = TM . getRegisterInfo ( ) ; RS = new RegScavenger ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= LoadStoreMultipleOpti ( MBB ) ; Modified |= MergeReturnIntoLDM ( MBB ) ; } delete RS ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> static void ready_reorder ( rtx_insn * * ready , int nready ) { if ( nready == 2 ) swap_reorder ( ready , nready ) ; else if ( nready > 2 ) qsort ( ready , nready , sizeof ( rtx_insn * ) , rank_for_reorder ) ; } </s>

Sort the ready list READY by ascending priority , using the SCHED_REORDER macro .


<s> unsigned VEAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & GOp , unsigned Kind ) { VEOperand & Op = ( VEOperand & ) GOp ; switch ( Kind ) { default : break ; case MCK_F32 : if ( Op . isReg ( ) && VEOperand :: MorphToF32Reg ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; case MCK_I32 : if ( Op . isReg ( ) && VEOperand :: MorphToI32Reg ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; case MCK_F128 : if ( Op . isReg ( ) && VEOperand :: MorphToF128Reg ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; case MCK_MISC : if ( Op . isImm ( ) && VEOperand :: MorphToMISCReg ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; } return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> SMLoc getLoc ( ) const { return getParser ( ) . getTok ( ) . getLoc ( ) ; } </s>

Get the source location of the point where the field was defined .


<s> bool RISCVExpandAtomicPseudo :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const RISCVInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; bool Modified = false ; for ( auto & MBB : MF ) Modified |= expandMBB ( MBB ) ; return Modified ; } </s>


<s> const char * standard_80387_constant_opcode ( rtx x ) { switch ( standard_80387_constant_p ( x ) ) { case 1 : return "fldz" ; case 2 : return "fld1" ; case 3 : return "fldlg2" ; case 4 : return "fldln2" ; case 5 : return "fldl2e" ; case 6 : return "fldl2t" ; case 7 : return "fldpi" ; case 8 : case 9 : return "#" ; default : gcc_unreachable ( ) ; } } </s>

Return the opcode of the special instruction to be used to load the constant X .


<s> Register getExceptionPointerRegister ( const Constant * PersonalityFn ) const override { return XCore :: R0 ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


"%qs applied to type %qT, which already has a size"

"%qs requires an integer constant expression"

An attribute callback for the `` arm_sve_vector_bits '' attribute .


<s>
void
avr_output_addr_vec_elt
(
FILE
*
stream
,
int
value
)
{
progmem_section
(
)
;
if
(
AVR_MEGA
)
fprintf
(
stream
,
"\t.word pm(.L%d)\n"
,
value
)
;
else
fprintf
(
stream
,
"\trjmp .L%d\n"
,
value
)
;
jump_tables_size
++
;
}
</s>

Worker function for ` ASM_OUTPUT_ADDR_VEC_ELT ' .

avr
"\t.word pm(.L%d)\n"
"\trjmp .L%d\n"


<s> bool BlackfinAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; O << '[' ; printOperand ( MI , OpNo , O ) ; O << ']' ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s>
MachineBasicBlock
*
SparcTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
const
TargetInstrInfo
&
TII
=
*
getTargetMachine
(
)
.
getInstrInfo
(
)
;
unsigned
BROpcode
;
unsigned
CC
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown SELECT_CC!"
)
;
case
SP
::
SELECT_CC_Int_ICC
:
case
SP
::
SELECT_CC_FP_ICC
:
case
SP
::
SELECT_CC_DFP_ICC
:
BROpcode
=
SP
::
BCOND
;
break
;
case
SP
::
SELECT_CC_Int_FCC
:
case
SP
::
SELECT_CC_FP_FCC
:
case
SP
::
SELECT_CC_DFP_FCC
:
BROpcode
=
SP
::
FBCOND
;
break
;
}
CC
=
(
SPCC
::
CondCodes
)
MI
->
getOperand
(
3
)
.
getImm
(
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
It
=
BB
;
++
It
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
sinkMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
F
->
insert
(
It
,
copy0MBB
)
;
F
->
insert
(
It
,
sinkMBB
)
;
sinkMBB
->
splice
(
sinkMBB
->
begin
(
)
,
BB
,
llvm
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
BB
->
end
(
)
)
;
sinkMBB
->
transferSuccessorsAndUpdatePHIs
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
sinkMBB
)
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
BROpcode
)
)
.
addMBB
(
sinkMBB
)
.
addImm
(
CC
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
sinkMBB
;
BuildMI
(
*
BB
,
BB
->
begin
(
)
,
dl
,
TII
.
get
(
SP
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
MI
->
eraseFromParent
(
)
;
return
BB
;
}
</s>


<s> bool ARMBaseInstrInfo :: analyzeCompare ( const MachineInstr & MI , Register & SrcReg , Register & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI . getOpcode ( ) ) { default : break ; case ARM :: CMPri : case ARM :: t2CMPri : case ARM :: tCMPi8 : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 1 ) . getImm ( ) ; return true ; case ARM :: CMPrr : case ARM :: t2CMPrr : case ARM :: tCMPr : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 1 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case ARM :: TSTri : case ARM :: t2TSTri : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = MI . getOperand ( 1 ) . getImm ( ) ; CmpValue = 0 ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


"%<#pragma%> GHS endXXX does not match "


<s> static unsigned int compute_vrsave_mask ( ) { unsigned int i , mask = 0 ; for ( i = FIRST_ALTIVEC_REGNO ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( regs_ever_live [ i ] ) mask |= ALTIVEC_REG_BIT ( i ) ; if ( mask == 0 ) return mask ; for ( i = FIRST_ALTIVEC_REGNO ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( call_used_regs [ i ] ) mask |= ALTIVEC_REG_BIT ( i ) ; for ( i = cfun -> args_info . vregno ; i >= ALTIVEC_ARG_MIN_REG ; -- i ) mask &= ~ ALTIVEC_REG_BIT ( i ) ; { bool yes = false ; diddle_return_value ( is_altivec_return_reg , & yes ) ; if ( yes ) mask &= ~ ALTIVEC_REG_BIT ( ALTIVEC_ARG_RETURN ) ; } return mask ; } </s>

Return a 32-bit mask of the AltiVec registers we need to set in VRSAVE . Bit n of the return value is 1 if Vn is live . The MSB in the 32-bit word is 0 .


<s> void AnalyzeFormalArguments ( const SmallVectorImpl < ISD :: InputArg > & Ins , CCAssignFn Fn ) { PreAnalyzeFormalArguments ( Ins , Fn ) ; CCState :: AnalyzeFormalArguments ( Ins , Fn ) ; } </s>

AnalyzeFormalArguments - Analyze an array of argument values , incorporating info about the formals into this state .


<s> void mt_print_operand_address ( FILE * file , rtx addr ) { if ( GET_CODE ( addr ) == AND && GET_CODE ( XEXP ( addr , 1 ) ) == CONST_INT && INTVAL ( XEXP ( addr , 1 ) ) == - 3 ) mt_print_operand_simple_address ( file , XEXP ( addr , 0 ) ) ; else mt_print_operand_simple_address ( file , addr ) ; } </s>


<s> bool isIntDivCheap ( EVT VT , AttributeList Attr ) const override { return true ; } </s>

Return true if integer divide is usually cheaper than a sequence of several shifts , adds , and multiplies for this target .


<s> bool ARMBaseTargetMachine :: addPreSched2 ( PassManagerBase & PM ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( ! Subtarget . isThumb1Only ( ) ) PM . add ( createARMLoadStoreOptimizationPass ( ) ) ; if ( Subtarget . hasNEON ( ) ) PM . add ( createExecutionDependencyFixPass ( & ARM :: DPRRegClass ) ) ; } PM . add ( createARMExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( ! Subtarget . isThumb1Only ( ) ) PM . add ( createIfConverterPass ( ) ) ; } if ( Subtarget . isThumb2 ( ) ) PM . add ( createThumb2ITBlockPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> static void s390_regs_ever_clobbered ( char regs_ever_clobbered [ ] ) { basic_block cur_bb ; rtx_insn * cur_insn ; unsigned int i ; memset ( regs_ever_clobbered , 0 , 32 ) ; if ( ! crtl -> is_leaf ) { for ( i = 0 ; i < 32 ; i ++ ) regs_ever_clobbered [ i ] = call_really_used_regs [ i ] ; } if ( crtl -> calls_eh_return || cfun -> machine -> has_landing_pad_p ) for ( i = 0 ; EH_RETURN_DATA_REGNO ( i ) != INVALID_REGNUM ; i ++ ) if ( crtl -> calls_eh_return || ( cfun -> machine -> has_landing_pad_p && df_regs_ever_live_p ( EH_RETURN_DATA_REGNO ( i ) ) ) ) regs_ever_clobbered [ EH_RETURN_DATA_REGNO ( i ) ] = 1 ; if ( crtl -> saves_all_registers ) for ( i = 0 ; i < 32 ; i ++ ) if ( ! call_really_used_regs [ i ] ) regs_ever_clobbered [ i ] = 1 ; FOR_EACH_BB_FN ( cur_bb , cfun ) { FOR_BB_INSNS ( cur_bb , cur_insn ) { rtx pat ; if ( ! INSN_P ( cur_insn ) ) continue ; pat = PATTERN ( cur_insn ) ; if ( epilogue_completed && RTX_FRAME_RELATED_P ( cur_insn ) ) { if ( GET_CODE ( pat ) == SET && GENERAL_REG_P ( SET_DEST ( pat ) ) ) { if ( GET_MODE ( SET_SRC ( pat ) ) == DImode && FP_REG_P ( SET_SRC ( pat ) ) ) continue ; if ( GET_CODE ( SET_SRC ( pat ) ) == MEM ) continue ; } if ( GET_CODE ( pat ) == PARALLEL && load_multiple_operation ( pat , VOIDmode ) ) continue ; } note_stores ( pat , s390_reg_clobbered_rtx , regs_ever_clobbered ) ; } } } </s>

Walks through all basic blocks of the current function looking for clobbered hard regs using s390_reg_clobbered_rtx . The fields of the passed integer array REGS_EVER_CLOBBERED are set to one for each of those regs .


<s> bool MipsTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( ! AM . HasBaseReg ) break ; return false ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


"\t ! references to jmptbl section entries\n"

"\t ! references to vector section entries\n"

Function to emit isr reset handler content . Including all jmptbl/vector references , jmptbl section , vector section , nmi handler section , and warm handler section .


<s> MVT X86TargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i1 && Subtarget . hasAVX512 ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; MVT RegisterVT ; unsigned NumRegisters ; std :: tie ( RegisterVT , NumRegisters ) = handleMaskRegisterForCallingConv ( NumElts , CC , Subtarget ) ; if ( RegisterVT != MVT :: INVALID_SIMPLE_VALUE_TYPE ) return RegisterVT ; } if ( VT == MVT :: v3f16 && Subtarget . hasFP16 ( ) ) return MVT :: v8f16 ; if ( ( VT == MVT :: f64 || VT == MVT :: f80 ) && ! Subtarget . is64Bit ( ) && ! Subtarget . hasX87 ( ) ) return MVT :: i32 ; return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


<s> bool HexagonInstrInfo :: ClobbersPredicate ( MachineInstr & MI , std :: vector < MachineOperand > & Pred , bool SkipDead ) const { const HexagonRegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( MO . isReg ( ) ) { if ( ! MO . isDef ( ) ) continue ; const TargetRegisterClass * RC = HRI . getMinimalPhysRegClass ( MO . getReg ( ) ) ; if ( RC == & Hexagon :: PredRegsRegClass ) { Pred . push_back ( MO ) ; return true ; } continue ; } else if ( MO . isRegMask ( ) ) { for ( unsigned PR : Hexagon :: PredRegsRegClass ) { if ( ! MI . modifiesRegister ( PR , & HRI ) ) continue ; Pred . push_back ( MO ) ; return true ; } } } return false ; } </s>

If the specified instruction defines any predicate or condition code register ( s ) used for predication , returns true as well as the definition predicate ( s ) by reference .

Hexagon Hexagon Hexagon Hexagon::PredRegsRegClass Hexagon::PredRegsRegClass


<s> static void tilepro_expand_high_multiply ( rtx result , rtx op1 , rtx op2 , bool sign ) { rtx tmp0 = gen_reg_rtx ( SImode ) ; rtx tmp1 = gen_reg_rtx ( SImode ) ; rtx tmp2 = gen_reg_rtx ( SImode ) ; rtx tmp3 = gen_reg_rtx ( SImode ) ; rtx tmp4 = gen_reg_rtx ( SImode ) ; rtx tmp5 = gen_reg_rtx ( SImode ) ; rtx tmp6 = gen_reg_rtx ( SImode ) ; rtx tmp7 = gen_reg_rtx ( SImode ) ; rtx tmp8 = gen_reg_rtx ( SImode ) ; rtx tmp9 = gen_reg_rtx ( SImode ) ; rtx tmp10 = gen_reg_rtx ( SImode ) ; rtx tmp11 = gen_reg_rtx ( SImode ) ; rtx tmp12 = gen_reg_rtx ( SImode ) ; rtx tmp13 = gen_reg_rtx ( SImode ) ; rtx result_lo = gen_reg_rtx ( SImode ) ; if ( sign ) { emit_insn ( gen_insn_mulhl_su ( tmp0 , op1 , op2 ) ) ; emit_insn ( gen_insn_mulhl_su ( tmp1 , op2 , op1 ) ) ; emit_insn ( gen_insn_mulll_uu ( tmp2 , op1 , op2 ) ) ; emit_insn ( gen_insn_mulhh_ss ( tmp3 , op1 , op2 ) ) ; } else { emit_insn ( gen_insn_mulhl_uu ( tmp0 , op1 , op2 ) ) ; emit_insn ( gen_insn_mulhl_uu ( tmp1 , op2 , op1 ) ) ; emit_insn ( gen_insn_mulll_uu ( tmp2 , op1 , op2 ) ) ; emit_insn ( gen_insn_mulhh_uu ( tmp3 , op1 , op2 ) ) ; } emit_move_insn ( tmp4 , ( gen_rtx_ASHIFT ( SImode , tmp0 , GEN_INT ( 16 ) ) ) ) ; emit_move_insn ( tmp5 , ( gen_rtx_ASHIFT ( SImode , tmp1 , GEN_INT ( 16 ) ) ) ) ; emit_move_insn ( tmp6 , ( gen_rtx_PLUS ( SImode , tmp4 , tmp5 ) ) ) ; emit_move_insn ( result_lo , ( gen_rtx_PLUS ( SImode , tmp2 , tmp6 ) ) ) ; emit_move_insn ( tmp7 , gen_rtx_LTU ( SImode , tmp6 , tmp4 ) ) ; emit_move_insn ( tmp8 , gen_rtx_LTU ( SImode , result_lo , tmp2 ) ) ; if ( sign ) { emit_move_insn ( tmp9 , ( gen_rtx_ASHIFTRT ( SImode , tmp0 , GEN_INT ( 16 ) ) ) ) ; emit_move_insn ( tmp10 , ( gen_rtx_ASHIFTRT ( SImode , tmp1 , GEN_INT ( 16 ) ) ) ) ; } else { emit_move_insn ( tmp9 , ( gen_rtx_LSHIFTRT ( SImode , tmp0 , GEN_INT ( 16 ) ) ) ) ; emit_move_insn ( tmp10 , ( gen_rtx_LSHIFTRT ( SImode , tmp1 , GEN_INT ( 16 ) ) ) ) ; } emit_move_insn ( tmp11 , ( gen_rtx_PLUS ( SImode , tmp3 , tmp7 ) ) ) ; emit_move_insn ( tmp12 , ( gen_rtx_PLUS ( SImode , tmp8 , tmp9 ) ) ) ; emit_move_insn ( tmp13 , ( gen_rtx_PLUS ( SImode , tmp11 , tmp12 ) ) ) ; emit_move_insn ( result , ( gen_rtx_PLUS ( SImode , tmp13 , tmp10 ) ) ) ; } </s>

Expand a high multiply pattern in SImode . RESULT , OP1 , OP2 are the operands , and SIGN is true if it 's a signed multiply , and false if it 's an unsigned multiply .


<s> Relocator :: Result none ( Relocation & pReloc , HexagonRelocator & pParent ) { return Relocator :: OK ; } </s>

Returns true if none of the bits are set .


<s> virtual const PPCRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
const
char
*
avr_out_tstsi
(
rtx_insn
*
insn
,
rtx
*
op
,
int
*
plen
)
{
if
(
compare_sign_p
(
insn
)
)
{
avr_asm_len
(
"tst %D0"
,
op
,
plen
,
1
)
;
}
else
if
(
reg_unused_after
(
insn
,
op
[
0
]
)
&&
compare_eq_p
(
insn
)
)
{
avr_asm_len
(
"or %A0,%B0"
CR_TAB
"or %A0,%C0"
CR_TAB
"or %A0,%D0"
,
op
,
plen
,
3
)
;
}
else
{
avr_out_compare
(
insn
,
op
,
plen
)
;
}
return
""
;
}
</s>


<s> bool update ( int O , int M ) { UpdateType Type = classifyUpdateByMask ( M ) ; if ( Type == Intermixed ) return false ; if ( Start == INT_MIN ) { Start = Stop = O ; updateMask ( M ) ; return true ; } else if ( Type == Descending && O == Start - 4 ) { Start -= 4 ; updateMask ( M ) ; return true ; } else if ( Type == Ascending && O == Stop + 4 ) { Stop += 4 ; updateMask ( M ) ; return true ; } return false ; } </s>


<s> static bool nvptx_split_reg_p ( machine_mode mode ) { if ( COMPLEX_MODE_P ( mode ) ) return true ; if ( mode == TImode ) return true ; return false ; } </s>

Like maybe_split_mode , but only return whether or not the mode needs to be split .


<s> static void ix86_emit_save_regs_using_mov ( HOST_WIDE_INT cfa_offset ) { unsigned int regno ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ! SSE_REGNO_P ( regno ) && ix86_save_reg ( regno , true ) ) { ix86_emit_save_reg_using_mov ( word_mode , regno , cfa_offset ) ; cfa_offset -= UNITS_PER_WORD ; } } </s>

Emit code to save registers using MOV insns . First register is restored from POINTER + OFFSET .


<s> bool AMDGPUIntrinsicInfo :: isOverloaded ( unsigned id ) const { } </s>

Returns true if the intrinsic can be overloaded .


<s> TargetPassConfig * Comet2TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new Comet2PassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> virtual void EmitInstruction ( const MachineInstr * MI ) { MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; TOYMCInstLower MCInstLowering ( MI -> getParent ( ) -> getParent ( ) -> getContext ( ) , * this ) ; do { MCInst TmpInst0 ; MCInstLowering . Lower ( I ++ , TmpInst0 ) ; OutStreamer . EmitInstruction ( TmpInst0 ) ; } while ( ( I != E ) && I -> isInsideBundle ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool ix86_expand_vecmul_qihi ( rtx dest , rtx op1 , rtx op2 ) { machine_mode himode , qimode = GET_MODE ( dest ) ; rtx hop1 , hop2 , hdest ; rtx ( * gen_extend ) ( rtx , rtx ) ; rtx ( * gen_truncate ) ( rtx , rtx ) ; if ( qimode == E_V64QImode ) return false ; if ( ! TARGET_AVX512BW ) return false ; if ( ( qimode == V8QImode || qimode == V16QImode ) && ! TARGET_AVX512VL ) return false ; if ( qimode == V32QImode && ( TARGET_PREFER_AVX128 || TARGET_PREFER_AVX256 ) ) return false ; switch ( qimode ) { case E_V8QImode : himode = V8HImode ; gen_extend = gen_zero_extendv8qiv8hi2 ; gen_truncate = gen_truncv8hiv8qi2 ; break ; case E_V16QImode : himode = V16HImode ; gen_extend = gen_zero_extendv16qiv16hi2 ; gen_truncate = gen_truncv16hiv16qi2 ; break ; case E_V32QImode : himode = V32HImode ; gen_extend = gen_zero_extendv32qiv32hi2 ; gen_truncate = gen_truncv32hiv32qi2 ; break ; default : gcc_unreachable ( ) ; } hop1 = gen_reg_rtx ( himode ) ; hop2 = gen_reg_rtx ( himode ) ; hdest = gen_reg_rtx ( himode ) ; emit_insn ( gen_extend ( hop1 , op1 ) ) ; emit_insn ( gen_extend ( hop2 , op2 ) ) ; emit_insn ( gen_rtx_SET ( hdest , simplify_gen_binary ( MULT , himode , hop1 , hop2 ) ) ) ; emit_insn ( gen_truncate ( dest , hdest ) ) ; return true ; } </s>

Optimize vector MUL generation for V8QI , V16QI and V32QI under TARGET_AVX512BW . i.e . for v16qi a * b , it has vpmovzxbw ymm2 , xmm0 vpmovzxbw ymm3 , xmm1 vpmullw ymm4 , ymm2 , ymm3 vpmovwb xmm0 , ymm4 it would take less instructions than ix86_expand_vecop_qihi . Return true if success .


<s> MCSymbol * AArch64MCInstLower :: GetExternalSymbolSymbol ( const MachineOperand & MO ) const { return Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; } </s>

Return the MCSymbol for the specified ExternalSymbol .


<s> static section * pa_som_tm_clone_table_section ( void ) { return som_tm_clone_table_section ; } </s>


<s> static MachineInstr * getVRegDef ( unsigned Reg , const MachineInstr * Insert , const MachineRegisterInfo & MRI , const LiveIntervals & LIS ) { if ( MachineInstr * Def = MRI . getUniqueVRegDef ( Reg ) ) return Def ; if ( const VNInfo * ValNo = LIS . getInterval ( Reg ) . getVNInfoBefore ( LIS . getInstructionIndex ( * Insert ) ) ) return LIS . getInstructionFromIndex ( ValNo -> def ) ; return nullptr ; } </s>

getVRegDef - Return the machine instr that defines the specified virtual register or null if none is found .


<s> static inline bool is_naked_func ( tree decl = current_function_decl ) { return has_attr ( ATTR_NAKED , decl ) ; } </s>

Returns true if the provided function has the `` naked '' attribute .


<s> bool RISCVTargetMachine :: isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DstAS ) const { const bool SrcIsCheri = isCheriPointer ( SrcAS , nullptr ) ; const bool DestIsCheri = isCheriPointer ( DstAS , nullptr ) ; if ( ( SrcIsCheri || DestIsCheri ) && ( SrcIsCheri != DestIsCheri ) ) return false ; return true ; } </s>

Returns true if a cast between SrcAS and DestAS is a noop .


<s> static int function_arg_slotno ( const struct sparc_args * cum , enum machine_mode mode , tree type , int named , int incoming_p , int * pregno , int * ppadding ) { int regbase = ( incoming_p ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST ) ; int slotno = cum -> words ; enum mode_class mclass ; int regno ; * ppadding = 0 ; if ( type && TREE_ADDRESSABLE ( type ) ) return - 1 ; if ( TARGET_ARCH32 && mode == BLKmode && type && TYPE_ALIGN ( type ) % PARM_BOUNDARY != 0 ) return - 1 ; if ( TARGET_ARCH64 && ( type ? TYPE_ALIGN ( type ) : GET_MODE_ALIGNMENT ( mode ) ) >= 128 && ( slotno & 1 ) != 0 ) slotno ++ , * ppadding = 1 ; mclass = GET_MODE_CLASS ( mode ) ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) { if ( TREE_CODE ( TREE_TYPE ( type ) ) == REAL_TYPE ) { gcc_assert ( mode == BLKmode ) ; } else { gcc_assert ( mode != BLKmode ) ; mclass = MODE_FLOAT ; } } switch ( mclass ) { case MODE_FLOAT : case MODE_COMPLEX_FLOAT : if ( TARGET_ARCH64 && TARGET_FPU && named ) { if ( slotno >= SPARC_FP_ARG_MAX ) return - 1 ; regno = SPARC_FP_ARG_FIRST + slotno * 2 ; if ( GET_MODE_SIZE ( mode ) <= 4 ) regno ++ ; break ; } case MODE_INT : case MODE_COMPLEX_INT : if ( slotno >= SPARC_INT_ARG_MAX ) return - 1 ; regno = regbase + slotno ; break ; case MODE_RANDOM : if ( mode == VOIDmode ) return - 1 ; gcc_assert ( mode == BLKmode ) ; if ( TARGET_ARCH32 || ! type || ( TREE_CODE ( type ) == UNION_TYPE ) ) { if ( slotno >= SPARC_INT_ARG_MAX ) return - 1 ; regno = regbase + slotno ; } else { int intregs_p = 0 , fpregs_p = 0 , packed_p = 0 ; if ( TREE_CODE ( type ) == VECTOR_TYPE ) fpregs_p = 1 ; else scan_record_type ( type , & intregs_p , & fpregs_p , & packed_p ) ; if ( packed_p || ! named ) fpregs_p = 0 , intregs_p = 1 ; if ( fpregs_p && slotno >= SPARC_FP_ARG_MAX ) return - 1 ; if ( ! fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX ) return - 1 ; return slotno ; } break ; default : gcc_unreachable ( ) ; } * pregno = regno ; return slotno ; } </s>

Compute the slot number to pass an argument in . Return the slot number or -1 if passing on the stack . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . INCOMING_P is zero for FUNCTION_ARG , nonzero for FUNCTION_INCOMING_ARG . * PREGNO records the register number to use if scalar type . * PPADDING records the amount of padding needed in words .


<s> static void aarch64_option_restore ( struct gcc_options * opts , struct cl_target_option * ptr ) { opts -> x_explicit_tune_core = ptr -> x_explicit_tune_core ; selected_tune = aarch64_get_tune_cpu ( ptr -> x_explicit_tune_core ) ; opts -> x_explicit_arch = ptr -> x_explicit_arch ; selected_arch = aarch64_get_arch ( ptr -> x_explicit_arch ) ; opts -> x_aarch64_override_tune_string = ptr -> x_aarch64_override_tune_string ; aarch64_override_options_internal ( opts ) ; } </s>

Implements TARGET_OPTION_RESTORE . Restore the backend codegen decisions using the information saved in PTR .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s>
void
AMDGPUAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
,
MCContext
&
Ctx
)
const
{
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
uint32_t
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
Data
[
Offset
+
i
]
|=
static_cast
<
uint8_t
>
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
bool
isMem
(
)
const
{
llvm_unreachable
(
"No isMem"
)
;
}
</s>


<s> bool SITargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & CI , unsigned IntrID ) const { switch ( IntrID ) { case Intrinsic :: amdgcn_atomic_inc : case Intrinsic :: amdgcn_atomic_dec : { Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: getVT ( CI . getType ( ) ) ; Info . ptrVal = CI . getOperand ( 0 ) ; Info . align = 0 ; const ConstantInt * Vol = dyn_cast < ConstantInt > ( CI . getOperand ( 4 ) ) ; Info . vol = ! Vol || ! Vol -> isZero ( ) ; Info . readMem = true ; Info . writeMem = true ; return true ; } default : return false ; } } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s>
void
AlphaInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
DestReg
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
DebugLoc
::
getUnknownLoc
(
)
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
if
(
RC
==
Alpha
::
F4RCRegisterClass
)
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Alpha
::
LDS
)
,
DestReg
)
.
addFrameIndex
(
FrameIdx
)
.
addReg
(
Alpha
::
F31
)
;
else
if
(
RC
==
Alpha
::
F8RCRegisterClass
)
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Alpha
::
LDT
)
,
DestReg
)
.
addFrameIndex
(
FrameIdx
)
.
addReg
(
Alpha
::
F31
)
;
else
if
(
RC
==
Alpha
::
GPRCRegisterClass
)
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Alpha
::
LDQ
)
,
DestReg
)
.
addFrameIndex
(
FrameIdx
)
.
addReg
(
Alpha
::
F31
)
;
else
llvm_unreachable
(
"Unhandled register class"
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> static bool mmix_rtx_costs ( rtx x ATTRIBUTE_UNUSED , int code ATTRIBUTE_UNUSED , int outer_code ATTRIBUTE_UNUSED , int opno ATTRIBUTE_UNUSED , int * total ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { return false ; } </s>


<s> void ARMPassConfig :: addPreEmitPass ( ) { addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( createUnpackMachineBundles ( [ ] ( const MachineFunction & MF ) { return MF . getSubtarget < ARMSubtarget > ( ) . isThumb2 ( ) ; } ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createARMOptimizeBarriersPass ( ) ) ; addPass ( createARMConstantIslandPass ( ) ) ; addPass ( createARMLowOverheadLoopsPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
void
ARMAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
IsPCRel
,
nullptr
,
IsLittleEndian
,
true
)
;
if
(
!
Value
)
return
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
unsigned
FullSizeBytes
;
if
(
!
IsLittleEndian
)
{
FullSizeBytes
=
getFixupKindContainerSizeBytes
(
Fixup
.
getKind
(
)
)
;
assert
(
(
Offset
+
FullSizeBytes
)
<=
DataSize
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FullSizeBytes
&&
"Invalid fixup size!"
)
;
}
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
IsLittleEndian
i
:
(
FullSizeBytes
1
i
)
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>


<s>
SDValue
MSP430TargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
isVarArg
,
Ins
,
dl
,
DAG
,
InVals
)
;
case
CallingConv
::
MSP430_INTR
:
if
(
Ins
.
empty
(
)
)
return
Chain
;
else
{
report_fatal_error
(
"ISRs cannot have arguments"
)
;
return
SDValue
(
)
;
}
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> static int spu_sched_adjust_cost ( rtx_insn * insn , int dep_type , rtx_insn * dep_insn , int cost , unsigned int ) { rtx set ; if ( INSN_CODE ( insn ) == CODE_FOR_blockage || INSN_CODE ( dep_insn ) == CODE_FOR_blockage ) return 0 ; if ( ( INSN_P ( insn ) && get_attr_length ( insn ) == 0 ) || ( INSN_P ( dep_insn ) && get_attr_length ( dep_insn ) == 0 ) ) return 0 ; if ( INSN_CODE ( insn ) == CODE_FOR_iprefetch && INSN_CODE ( dep_insn ) == CODE_FOR_iprefetch ) return 8 ; if ( ( INSN_CODE ( insn ) == CODE_FOR_iprefetch || INSN_CODE ( insn ) == CODE_FOR_hbr ) && ( INSN_CODE ( dep_insn ) == CODE_FOR_iprefetch || INSN_CODE ( dep_insn ) == CODE_FOR_hbr ) ) return 2 ; if ( INSN_CODE ( insn ) == CODE_FOR_iprefetch || INSN_CODE ( dep_insn ) == CODE_FOR_iprefetch ) return 0 ; if ( CALL_P ( insn ) ) { rtx target = get_branch_target ( insn ) ; if ( GET_CODE ( target ) != REG || ! set_of ( target , insn ) ) return cost - 2 ; return cost ; } if ( CALL_P ( dep_insn ) ) return cost - 2 ; if ( INSN_CODE ( insn ) == CODE_FOR__return && ( set = single_set ( dep_insn ) ) && GET_CODE ( SET_DEST ( set ) ) == REG && REGNO ( SET_DEST ( set ) ) == LINK_REGISTER_REGNUM ) return 20 ; if ( JUMP_P ( insn ) && dep_type == REG_DEP_ANTI ) return insn_sched_cost ( dep_insn ) - 3 ; return cost ; } </s>


<s> bool valid_sf_si_move ( rtx dest , rtx src , machine_mode mode ) { if ( TARGET_ALLOW_SF_SUBREG ) return true ; if ( mode != SFmode && GET_MODE_CLASS ( mode ) != MODE_INT ) return true ; if ( ! SUBREG_P ( src ) || ! sf_subreg_operand ( src , mode ) ) return true ; if ( SUBREG_P ( dest ) ) { rtx dest_subreg = SUBREG_REG ( dest ) ; rtx src_subreg = SUBREG_REG ( src ) ; return GET_MODE ( dest_subreg ) == GET_MODE ( src_subreg ) ; } return false ; } </s>

Return whether a SFmode or SImode move can be done without converting one mode to another . This arrises when we have : ( SUBREG : SF ( REG : SI ... ) ) ( SUBREG : SI ( REG : SF ... ) ) and one of the values is in a floating point/vector register , where SFmode scalars are stored in DFmode format .