<s> StringRef getPassName ( ) const override { return MCS51_RELAX_MEM_OPS_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> bool ARMTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { if ( ! Subtarget -> hasVFP3 ( ) ) return false ; if ( VT == MVT :: f32 ) return ARM_AM :: getFP32Imm ( Imm ) != - 1 ; if ( VT == MVT :: f64 && ! Subtarget -> isFPOnlySP ( ) ) return ARM_AM :: getFP64Imm ( Imm ) != - 1 ; return false ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> static tree rs6000_init_stack_protect_guard ( void ) { if ( rs6000_stack_protector_guard == SSP_GLOBAL ) return default_stack_protect_guard ( ) ; return NULL_TREE ; } </s>

Only create the global variable for the stack protect guard if we are using the global flavor of that guard .


<s> void flushPendingInstructions ( MCStreamer & Out ) override { if ( ! inImplicitITBlock ( ) ) { assert ( PendingConditionalInsts . size ( ) == 0 ) ; return ; } MCInst ITInst ; ITInst . setOpcode ( ARM :: t2IT ) ; ITInst . addOperand ( MCOperand :: createImm ( ITState . Cond ) ) ; ITInst . addOperand ( MCOperand :: createImm ( ITState . Mask ) ) ; Out . emitInstruction ( ITInst , getSTI ( ) ) ; assert ( PendingConditionalInsts . size ( ) <= 4 ) ; for ( const MCInst & Inst : PendingConditionalInsts ) { Out . emitInstruction ( Inst , getSTI ( ) ) ; } PendingConditionalInsts . clear ( ) ; ITState . Mask = 0 ; ITState . CurPosition = ~ 0U ; } </s>

Ensure that all previously parsed instructions have been emitted to the output streamer , if the target does not emit them immediately .


<s> bool MOSPassConfig :: addIRTranslator ( ) { addPass ( new IRTranslator ( getOptLevel ( ) ) ) ; return false ; } </s>

This method should install an IR translator pass , which converts from LLVM code to machine instructions with possibly generic opcodes .


<s> static rtx mmix_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( mode , MMIX_RETURN_VALUE_REGNUM ) ; } </s>


<s> bool AArch64InstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( TargetInstrInfo :: isSchedulingBoundary ( MI , MBB , MF ) ) return true ; switch ( MI . getOpcode ( ) ) { case AArch64 :: DSB : case AArch64 :: ISB : return true ; default : ; } return isSEHInstruction ( MI ) ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> static rtx frv_frame_offset_rtx ( int offset ) { rtx offset_rtx = GEN_INT ( offset ) ; if ( IN_RANGE_P ( offset , - 2048 , 2047 ) ) return offset_rtx ; else { rtx reg_rtx = gen_rtx_REG ( SImode , OFFSET_REGNO ) ; if ( IN_RANGE_P ( offset , - 32768 , 32767 ) ) emit_insn ( gen_movsi ( reg_rtx , offset_rtx ) ) ; else { emit_insn ( gen_movsi_high ( reg_rtx , offset_rtx ) ) ; emit_insn ( gen_movsi_lo_sum ( reg_rtx , offset_rtx ) ) ; } return reg_rtx ; } } </s>

Return an rtx with the value OFFSET , which will either be a register or a signed 12-bit integer . It can be used as the second operand in an `` add '' instruction , or as the index in a load or store . The function returns a constant rtx if OFFSET is small enough , otherwise it loads the constant into register OFFSET_REGNO and returns that .


<s>
FunctionType
*
AMDGPUIntrinsicInfo
::
getType
(
LLVMContext
&
Context
,
unsigned
ID
,
ArrayRef
<
Type
*
>
Tys
)
const
{
llvm_unreachable
(
"unhandled intrinsic"
)
;
}
</s>

Overload to return most specific vector type .


<s> const unsigned * X86RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { bool callsEHReturn = false ; bool ghcCall = false ; if ( MF ) { callsEHReturn = MF -> getMMI ( ) . callsEHReturn ( ) ; const Function * F = MF -> getFunction ( ) ; ghcCall = ( F ? F -> getCallingConv ( ) == CallingConv :: GHC : false ) ; } static const unsigned GhcCalleeSavedRegs [ ] = { 0 } ; static const unsigned CalleeSavedRegs32Bit [ ] = { X86 :: ESI , X86 :: EDI , X86 :: EBX , X86 :: EBP , 0 } ; static const unsigned CalleeSavedRegs32EHRet [ ] = { X86 :: EAX , X86 :: EDX , X86 :: ESI , X86 :: EDI , X86 :: EBX , X86 :: EBP , 0 } ; static const unsigned CalleeSavedRegs64Bit [ ] = { X86 :: RBX , X86 :: R12 , X86 :: R13 , X86 :: R14 , X86 :: R15 , X86 :: RBP , 0 } ; static const unsigned CalleeSavedRegs64EHRet [ ] = { X86 :: RAX , X86 :: RDX , X86 :: RBX , X86 :: R12 , X86 :: R13 , X86 :: R14 , X86 :: R15 , X86 :: RBP , 0 } ; static const unsigned CalleeSavedRegsWin64 [ ] = { X86 :: RBX , X86 :: RBP , X86 :: RDI , X86 :: RSI , X86 :: R12 , X86 :: R13 , X86 :: R14 , X86 :: R15 , X86 :: XMM6 , X86 :: XMM7 , X86 :: XMM8 , X86 :: XMM9 , X86 :: XMM10 , X86 :: XMM11 , X86 :: XMM12 , X86 :: XMM13 , X86 :: XMM14 , X86 :: XMM15 , 0 } ; if ( ghcCall ) { return GhcCalleeSavedRegs ; } else if ( Is64Bit ) { if ( IsWin64 ) return CalleeSavedRegsWin64 ; else return ( callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit ) ; } else { return ( callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit ) ; } } </s>


<s> static bool riscv_allocate_stack_slots_for_args ( ) { return ! riscv_naked_function_p ( current_function_decl ) ; } </s>


<s> bool X86IndirectBranchTrackingPass :: runOnMachineFunction ( MachineFunction & MF ) { const X86Subtarget & SubTarget = MF . getSubtarget < X86Subtarget > ( ) ; Metadata * isCFProtectionSupported = MF . getMMI ( ) . getModule ( ) -> getModuleFlag ( "cf-protection-branch" ) ; const X86TargetMachine * TM = static_cast < const X86TargetMachine * > ( & MF . getTarget ( ) ) ; bool isJITwithCET = TM -> isJIT ( ) ; bool isJITwithCET = false ; if ( ! isCFProtectionSupported && ! IndirectBranchTracking && ! isJITwithCET ) return false ; bool Changed = false ; TII = SubTarget . getInstrInfo ( ) ; EndbrOpcode = SubTarget . is64Bit ( ) ? X86 :: ENDBR64 : X86 :: ENDBR32 ; if ( ( TM -> getCodeModel ( ) == CodeModel :: Large || MF . getFunction ( ) . hasAddressTaken ( ) || ! MF . getFunction ( ) . hasLocalLinkage ( ) ) && ! MF . getFunction ( ) . doesNoCfCheck ( ) ) { auto MBB = MF . begin ( ) ; Changed |= addENDBR ( * MBB , MBB -> begin ( ) ) ; } for ( auto & MBB : MF ) { if ( MBB . hasAddressTaken ( ) ) Changed |= addENDBR ( MBB , MBB . begin ( ) ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( I -> isCall ( ) && IsCallReturnTwice ( I -> getOperand ( 0 ) ) ) Changed |= addENDBR ( MBB , std :: next ( I ) ) ; } if ( TM -> Options . ExceptionModel == ExceptionHandling :: SjLj ) { for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( MBB . isEHPad ( ) ) { if ( I -> isDebugInstr ( ) ) continue ; Changed |= addENDBR ( MBB , I ) ; break ; } else if ( I -> isEHLabel ( ) ) { MCSymbol * Sym = I -> getOperand ( 0 ) . getMCSymbol ( ) ; if ( ! MF . hasCallSiteLandingPad ( Sym ) ) continue ; Changed |= addENDBR ( MBB , std :: next ( I ) ) ; break ; } } } else if ( MBB . isEHPad ( ) ) { for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( ! I -> isEHLabel ( ) ) continue ; Changed |= addENDBR ( MBB , std :: next ( I ) ) ; break ; } } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool MipsAsmParser :: ParseInstruction ( StringRef Name , SMLoc NameLoc , SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { return true ; } </s>

ParseInstruction - Parse one assembly instruction .


<s>
SDValue
Cpu0TargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_Cpu0
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
assert
(
RVLocs
.
size
(
)
<=
1
&&
"Too many values to return!"
)
;
if
(
RVLocs
.
size
(
)
>
0
)
{
CCValAssign
&
VA
=
RVLocs
[
0
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
0
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
if
(
DAG
.
getMachineFunction
(
)
.
getFunction
(
)
->
hasStructRetAttr
(
)
)
{
assert
(
false
&&
"Not yet implemented"
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
RVLocs
.
size
(
)
==
0
Cpu0ISD
::
Ret
:
Cpu0ISD
::
RetValue
,
dl
,
MVT
::
Other
,
&
RetOps
[
0
]
,
RetOps
.
size
(
)
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> Register ARMBaseRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , int FrameIdx , int64_t Offset ) const { ARMFunctionInfo * AFI = MBB -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? ARM :: ADDri : ( AFI -> isThumb1OnlyFunction ( ) ? ARM :: tADDframe : ARM :: t2ADDri ) ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; Register BaseReg = MRI . createVirtualRegister ( & ARM :: GPRRegClass ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , 0 , this , MF ) ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ; if ( ! AFI -> isThumb1OnlyFunction ( ) ) MIB . add ( predOps ( ARMCC :: AL ) ) . add ( condCodeOp ( ) ) ; return BaseReg ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .

ARM ARM ARM ARM ARM::ADDri ARM::tADDframe ARM::t2ADDri ARM::GPRRegClass 0 ARMCC::AL


"force: group count = %d, can_issue_more = %d\n"

"done force: group count = %d, can_issue_more = %d\n"

Utility of the function redefine_groups . Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS in the same dispatch group . If so , insert nops before NEXT_INSN , in order to keep it `` far '' ( in a separate group ) from GROUP_INSNS , following one of the following schemes , depending on the value of the flag -minsert_sched_nops = X : ( 1 ) X == sched_finish_regroup_exact : insert exactly as many nops as needed in order to force NEXT_INSN into a separate group . ( 2 ) X < sched_finish_regroup_exact : insert exactly X nops . GROUP_END , CAN_ISSUE_MORE and GROUP_COUNT record the state after nop insertion ( has a group just ended , how many vacant issue slots remain in the last group , and how many dispatch groups were encountered so far ) .


<s> static void riscv_extend_comparands ( rtx_code code , rtx * op0 , rtx * op1 ) { if ( GET_MODE_SIZE ( word_mode ) > GET_MODE_SIZE ( GET_MODE ( * op0 ) ) . to_constant ( ) ) { if ( unsigned_condition ( code ) == code && ( GET_MODE ( * op0 ) == QImode && ! ( GET_CODE ( * op0 ) == SUBREG && SUBREG_PROMOTED_VAR_P ( * op0 ) && SUBREG_PROMOTED_SIGNED_P ( * op0 ) && ( CONST_INT_P ( * op1 ) || ( GET_CODE ( * op1 ) == SUBREG && SUBREG_PROMOTED_VAR_P ( * op1 ) && SUBREG_PROMOTED_SIGNED_P ( * op1 ) ) ) ) ) ) { * op0 = gen_rtx_ZERO_EXTEND ( word_mode , * op0 ) ; if ( CONST_INT_P ( * op1 ) ) * op1 = GEN_INT ( ( uint8_t ) INTVAL ( * op1 ) ) ; else * op1 = gen_rtx_ZERO_EXTEND ( word_mode , * op1 ) ; } else { * op0 = gen_rtx_SIGN_EXTEND ( word_mode , * op0 ) ; if ( * op1 != const0_rtx ) * op1 = gen_rtx_SIGN_EXTEND ( word_mode , * op1 ) ; } } } </s>

Sign- or zero-extend OP0 and OP1 for integer comparisons .


<s> bool HexagonAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , OS ) ; case 'L' : case 'H' : { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( ! MO . isReg ( ) ) return true ; Register RegNumber = MO . getReg ( ) ; if ( Hexagon :: DoubleRegsRegClass . contains ( RegNumber ) ) RegNumber = TRI -> getSubReg ( RegNumber , ExtraCode [ 0 ] == 'L' ? Hexagon :: isub_lo : Hexagon :: isub_hi ) ; OS << HexagonInstPrinter :: getRegisterName ( RegNumber ) ; return false ; } case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) OS << "i" ; return false ; } } printOperand ( MI , OpNo , OS ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> bool isToken ( ) const override { return Kind == OpKind :: Token ; } </s>


<s> static inline unsigned long * ia64_rse_skip_regs ( unsigned long * addr , long num_regs ) { long delta = ia64_rse_slot_num ( addr ) + num_regs ; if ( num_regs < 0 ) delta -= 0x3e ; return addr + num_regs + delta / 0x3f ; } </s>

The inverse of the above : given bspstore and the number of registers , calculate ar.bsp .


<s> static bool spu_addr_space_subset_p ( addr_space_t subset , addr_space_t superset ) { gcc_assert ( subset == ADDR_SPACE_GENERIC || subset == ADDR_SPACE_EA ) ; gcc_assert ( superset == ADDR_SPACE_GENERIC || superset == ADDR_SPACE_EA ) ; if ( subset == superset ) return true ; else if ( ! TARGET_ADDRESS_SPACE_CONVERSION ) return false ; else return ( subset == ADDR_SPACE_GENERIC && superset == ADDR_SPACE_EA ) ; } </s>

Determine if one named address space is a subset of another .


<s> static reg_class_t xstormy16_preferred_reload_class ( rtx x , reg_class_t rclass ) { if ( rclass == GENERAL_REGS && ( MEM_P ( x ) || GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == PRE_DEC || GET_CODE ( x ) == PRE_MODIFY ) ) return EIGHT_REGS ; return rclass ; } </s>

Worker function for TARGET_PREFERRED_RELOAD_CLASS and TARGET_PREFERRED_OUTPUT_RELOAD_CLASS .


<s> int m32r_expand_block_move ( rtx operands [ ] ) { rtx orig_dst = operands [ 0 ] ; rtx orig_src = operands [ 1 ] ; rtx bytes_rtx = operands [ 2 ] ; rtx align_rtx = operands [ 3 ] ; int constp = CONST_INT_P ( bytes_rtx ) ; HOST_WIDE_INT bytes = constp ? INTVAL ( bytes_rtx ) : 0 ; int align = INTVAL ( align_rtx ) ; int leftover ; rtx src_reg ; rtx dst_reg ; if ( constp && bytes <= 0 ) return 1 ; dst_reg = copy_addr_to_reg ( XEXP ( orig_dst , 0 ) ) ; src_reg = copy_addr_to_reg ( XEXP ( orig_src , 0 ) ) ; if ( align > UNITS_PER_WORD ) align = UNITS_PER_WORD ; if ( optimize_size || ! constp || align != UNITS_PER_WORD ) { block_move_call ( dst_reg , src_reg , bytes_rtx ) ; return 0 ; } leftover = bytes % MAX_MOVE_BYTES ; bytes -= leftover ; if ( bytes ) { rtx_code_label * label = NULL ; rtx final_src = NULL_RTX ; rtx at_a_time = GEN_INT ( MAX_MOVE_BYTES ) ; rtx rounded_total = GEN_INT ( bytes ) ; rtx new_dst_reg = gen_reg_rtx ( SImode ) ; rtx new_src_reg = gen_reg_rtx ( SImode ) ; if ( bytes > MAX_MOVE_BYTES ) { final_src = gen_reg_rtx ( Pmode ) ; if ( INT16_P ( bytes ) ) emit_insn ( gen_addsi3 ( final_src , src_reg , rounded_total ) ) ; else { emit_insn ( gen_movsi ( final_src , rounded_total ) ) ; emit_insn ( gen_addsi3 ( final_src , final_src , src_reg ) ) ; } label = gen_label_rtx ( ) ; emit_label ( label ) ; } emit_insn ( gen_movmemsi_internal ( dst_reg , src_reg , at_a_time , new_dst_reg , new_src_reg ) ) ; emit_move_insn ( dst_reg , new_dst_reg ) ; emit_move_insn ( src_reg , new_src_reg ) ; emit_insn ( gen_addsi3 ( dst_reg , dst_reg , GEN_INT ( 4 ) ) ) ; if ( bytes > MAX_MOVE_BYTES ) { rtx test = gen_rtx_NE ( VOIDmode , src_reg , final_src ) ; emit_jump_insn ( gen_cbranchsi4 ( test , src_reg , final_src , label ) ) ; } } if ( leftover ) emit_insn ( gen_movmemsi_internal ( dst_reg , src_reg , GEN_INT ( leftover ) , gen_reg_rtx ( SImode ) , gen_reg_rtx ( SImode ) ) ) ; return 1 ; } </s>

Expand string/block move operations . operands [ 0 ] is the pointer to the destination . operands [ 1 ] is the pointer to the source . operands [ 2 ] is the number of bytes to move . operands [ 3 ] is the alignment .


<s> bool X86WinAllocaExpander :: runOnMachineFunction ( MachineFunction & MF ) { if ( ! MF . getInfo < X86MachineFunctionInfo > ( ) -> hasWinAlloca ( ) ) return false ; MRI = & MF . getRegInfo ( ) ; STI = & MF . getSubtarget < X86Subtarget > ( ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; StackPtr = TRI -> getStackRegister ( ) ; SlotSize = TRI -> getSlotSize ( ) ; StackProbeSize = 4096 ; if ( MF . getFunction ( ) -> hasFnAttribute ( "stack-probe-size" ) ) { MF . getFunction ( ) -> getFnAttribute ( "stack-probe-size" ) . getValueAsString ( ) . getAsInteger ( 0 , StackProbeSize ) ; } LoweringMap Lowerings ; computeLowerings ( MF , Lowerings ) ; for ( auto & P : Lowerings ) lower ( P . first , P . second ) ; return true ; } </s>


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( ( N -> getOpcode ( ) == X86ISD :: CALL && ! Subtarget -> callRegIndirect ( ) ) || ( N -> getOpcode ( ) == X86ISD :: TC_RETURN && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; MVT SrcVT = N -> getOperand ( 0 ) . getSimpleValueType ( ) ; MVT DstVT = N -> getSimpleValueType ( 0 ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const X86TargetLowering * X86Lowering = static_cast < const X86TargetLowering * > ( getTargetLowering ( ) ) ; bool SrcIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } MVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s>
void
output_dbcc_and_branch
(
rtx
*
operands
)
{
switch
(
GET_CODE
(
operands
[
3
]
)
)
{
case
EQ
:
output_asm_insn
(
"dbeq %0,%l1\n\tjeq %l2"
,
operands
)
;
break
;
case
NE
:
output_asm_insn
(
"dbne %0,%l1\n\tjne %l2"
,
operands
)
;
break
;
case
GT
:
output_asm_insn
(
"dbgt %0,%l1\n\tjgt %l2"
,
operands
)
;
break
;
case
GTU
:
output_asm_insn
(
"dbhi %0,%l1\n\tjhi %l2"
,
operands
)
;
break
;
case
LT
:
output_asm_insn
(
"dblt %0,%l1\n\tjlt %l2"
,
operands
)
;
break
;
case
LTU
:
output_asm_insn
(
"dbcs %0,%l1\n\tjcs %l2"
,
operands
)
;
break
;
case
GE
:
output_asm_insn
(
"dbge %0,%l1\n\tjge %l2"
,
operands
)
;
break
;
case
GEU
:
output_asm_insn
(
"dbcc %0,%l1\n\tjcc %l2"
,
operands
)
;
break
;
case
LE
:
output_asm_insn
(
"dble %0,%l1\n\tjle %l2"
,
operands
)
;
break
;
case
LEU
:
output_asm_insn
(
"dbls %0,%l1\n\tjls %l2"
,
operands
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
switch
(
GET_MODE
(
operands
[
0
]
)
)
{
case
SImode
:
output_asm_insn
(
"clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1"
,
operands
)
;
break
;
case
HImode
:
break
;
default
:
gcc_unreachable
(
)
;
}
}
</s>

Output a dbCC ; jCC sequence . Note we do not handle the floating point version of this sequence ( Fdbcc ) . We also do not handle alternative conditions when CC_NO_OVERFLOW is set . It is assumed that valid_dbcc_comparison_p and flags_in_68881 will kick those out before we get here .


<s> MVT SPIRVTargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT . isVector ( ) && VT . getVectorNumElements ( ) == 3 ) { if ( VT . getVectorElementType ( ) == MVT :: i1 ) return MVT :: v4i1 ; else if ( VT . getVectorElementType ( ) == MVT :: i8 ) return MVT :: v4i8 ; } return getRegisterType ( Context , VT ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


"Unhandled instruction encoding format!"

Targets should implement this to emit instructions .


<s> static tree altivec_build_resolved_builtin ( tree * args , int n , tree fntype , tree ret_type , rs6000_gen_builtins bif_id , rs6000_gen_builtins ovld_id ) { tree argtypes = TYPE_ARG_TYPES ( fntype ) ; tree arg_type [ MAX_OVLD_ARGS ] ; tree fndecl = rs6000_builtin_decls [ bif_id ] ; for ( int i = 0 ; i < n ; i ++ ) { arg_type [ i ] = TREE_VALUE ( argtypes ) ; argtypes = TREE_CHAIN ( argtypes ) ; } if ( n == 3 && ovld_id == RS6000_OVLD_VEC_CMPGE_P && bif_id != RS6000_BIF_VCMPGEFP_P && bif_id != RS6000_BIF_XVCMPGEDP_P ) { std :: swap ( args [ 1 ] , args [ 2 ] ) ; std :: swap ( arg_type [ 1 ] , arg_type [ 2 ] ) ; args [ 0 ] = fold_build2 ( BIT_XOR_EXPR , TREE_TYPE ( args [ 0 ] ) , args [ 0 ] , build_int_cst ( NULL_TREE , 2 ) ) ; } for ( int j = 0 ; j < n ; j ++ ) args [ j ] = fully_fold_convert ( arg_type [ j ] , args [ j ] ) ; gcc_assert ( MAX_OVLD_ARGS <= 4 ) ; tree call ; switch ( n ) { case 0 : call = build_call_expr ( fndecl , 0 ) ; break ; case 1 : call = build_call_expr ( fndecl , 1 , args [ 0 ] ) ; break ; case 2 : call = build_call_expr ( fndecl , 2 , args [ 0 ] , args [ 1 ] ) ; break ; case 3 : call = build_call_expr ( fndecl , 3 , args [ 0 ] , args [ 1 ] , args [ 2 ] ) ; break ; case 4 : call = build_call_expr ( fndecl , 4 , args [ 0 ] , args [ 1 ] , args [ 2 ] , args [ 3 ] ) ; break ; default : gcc_unreachable ( ) ; } return fold_convert ( ret_type , call ) ; } </s>

Build a tree for a function call to an Altivec non-overloaded builtin . The overloaded builtin that matched the types and args is described by DESC . The N arguments are given in ARGS , respectively . Actually the only thing it does is calling fold_convert on ARGS , with a small exception for vec_ { all , any } _ { ge , le } predicates .


<s>
unsigned
char
M68kSubtarget
::
classifyGlobalReference
(
const
GlobalValue
*
GV
,
const
Module
&
M
)
const
{
if
(
TM
.
shouldAssumeDSOLocal
(
M
,
GV
)
)
return
classifyLocalReference
(
GV
)
;
switch
(
TM
.
getCodeModel
(
)
)
{
default
:
llvm_unreachable
(
"Unsupported code model"
)
;
case
CodeModel
::
Small
:
case
CodeModel
::
Kernel
:
{
if
(
isPositionIndependent
(
)
)
return
M68kII
::
MO_GOTPCREL
;
return
M68kII
::
MO_PC_RELATIVE_ADDRESS
;
}
case
CodeModel
::
Medium
:
{
if
(
isPositionIndependent
(
)
)
return
M68kII
::
MO_GOTPCREL
;
if
(
atLeastM68020
(
)
)
return
M68kII
::
MO_PC_RELATIVE_ADDRESS
;
return
M68kII
::
MO_ABSOLUTE_ADDRESS
;
}
}
}
</s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


"Caller should have checked for a comparison"

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> void aarch64_emit_sve_pred_move ( rtx dest , rtx pred , rtx src ) { expand_operand ops [ 3 ] ; machine_mode mode = GET_MODE ( dest ) ; create_output_operand ( & ops [ 0 ] , dest , mode ) ; create_input_operand ( & ops [ 1 ] , pred , GET_MODE ( pred ) ) ; create_input_operand ( & ops [ 2 ] , src , mode ) ; expand_insn ( code_for_aarch64_pred_mov ( mode ) , 3 , ops ) ; } </s>

Emit an SVE predicated move from SRC to DEST . PRED is a predicate that is known to contain PTRUE .


<s>
bool
AMDGPUMCInstLower
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
const
{
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
createImm
(
MO
.
getImm
(
)
)
;
return
true
;
case
MachineOperand
::
MO_Register
:
MCOp
=
MCOperand
::
createReg
(
AMDGPU
::
getMCReg
(
MO
.
getReg
(
)
,
ST
)
)
;
return
true
;
case
MachineOperand
::
MO_MachineBasicBlock
:
{
if
(
MO
.
getTargetFlags
(
)
!=
0
)
{
MCOp
=
MCOperand
::
createExpr
(
getLongBranchBlockExpr
(
*
MO
.
getParent
(
)
->
getParent
(
)
,
MO
)
)
;
}
else
{
MCOp
=
MCOperand
::
createExpr
(
MCSymbolRefExpr
::
create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
Ctx
)
)
;
}
return
true
;
}
case
MachineOperand
::
MO_GlobalAddress
:
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
SmallString
<
128
>
SymbolName
;
AP
.
getNameWithPrefix
(
SymbolName
,
GV
)
;
MCSymbol
*
Sym
=
Ctx
.
getOrCreateSymbol
(
SymbolName
)
;
const
MCExpr
*
SymExpr
=
MCSymbolRefExpr
::
create
(
Sym
,
getVariantKind
(
MO
.
getTargetFlags
(
)
)
,
Ctx
)
;
const
MCExpr
*
Expr
=
MCBinaryExpr
::
createAdd
(
SymExpr
,
MCConstantExpr
::
create
(
MO
.
getOffset
(
)
,
Ctx
)
,
Ctx
)
;
MCOp
=
MCOperand
::
createExpr
(
Expr
)
;
return
true
;
}
case
MachineOperand
::
MO_ExternalSymbol
:
{
MCSymbol
*
Sym
=
Ctx
.
getOrCreateSymbol
(
StringRef
(
MO
.
getSymbolName
(
)
)
)
;
Sym
->
setExternal
(
true
)
;
const
MCSymbolRefExpr
*
Expr
=
MCSymbolRefExpr
::
create
(
Sym
,
Ctx
)
;
MCOp
=
MCOperand
::
createExpr
(
Expr
)
;
return
true
;
}
case
MachineOperand
::
MO_RegisterMask
:
return
false
;
}
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .

AMDGPU
AMDGPU
"unknown operand type"
AMDGPU::getMCReg
0
128


<s> gimple * gimple_fold_builtin ( unsigned int code , gimple_stmt_iterator * gsi , gcall * stmt ) { registered_function & rfn = * ( * registered_functions ) [ code ] ; return gimple_folder ( rfn . instance , rfn . decl , gsi , stmt ) . fold ( ) ; } </s>

Attempt to fold STMT , given that it 's a call to the SVE function with subcode CODE . Return the new statement on success and null on failure . Insert any other new statements at GSI .


<s> static void scan_record_type ( const_tree type , int * intregs_p , int * fpregs_p , int * packed_p ) { tree field ; for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) == FIELD_DECL ) { if ( TREE_CODE ( TREE_TYPE ( field ) ) == RECORD_TYPE ) scan_record_type ( TREE_TYPE ( field ) , intregs_p , fpregs_p , 0 ) ; else if ( ( FLOAT_TYPE_P ( TREE_TYPE ( field ) ) || TREE_CODE ( TREE_TYPE ( field ) ) == VECTOR_TYPE ) && TARGET_FPU ) * fpregs_p = 1 ; else * intregs_p = 1 ; if ( packed_p && DECL_PACKED ( field ) ) * packed_p = 1 ; } } } </s>

Scan the record type TYPE and return the following predicates : - INTREGS_P : the record contains at least one field or sub-field that is eligible for promotion in integer registers . - FP_REGS_P : the record contains at least one field or sub-field that is eligible for promotion in floating-point registers . - PACKED_P : the record contains at least one field that is packed . Sub-fields are not taken into account for the PACKED_P predicate .


"getIntImmCost can only estimate cost of materialising integers"

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this , Options . StackAlignmentOverride ) { if ( getRelocationModel ( ) == Reloc :: Static ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . is64Bit ( ) ) { Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; } else if ( Subtarget . isTargetCOFF ( ) ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . isTargetDarwin ( ) ) { if ( getRelocationModel ( ) == Reloc :: PIC_ ) Subtarget . setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; Subtarget . setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( Subtarget . isTargetELF ( ) ) { Subtarget . setPICStyle ( PICStyles :: GOT ) ; } if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = FloatABI :: Hard ; if ( Subtarget . isTargetWin64 ( ) ) this -> Options . TrapUnreachable = true ; initAsmInfo ( ) ; } </s>


runOnMachineFunction - Emit the function body .


<s> const DataLayout * getDataLayout ( ) const override { return getSubtargetImpl ( ) -> getDataLayout ( ) ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> static struct constant_pool * s390_mainpool_start ( void ) { struct constant_pool * pool ; rtx_insn * insn ; pool = s390_alloc_pool ( ) ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == SET && GET_CODE ( SET_SRC ( PATTERN ( insn ) ) ) == UNSPEC_VOLATILE && XINT ( SET_SRC ( PATTERN ( insn ) ) , 1 ) == UNSPECV_MAIN_POOL ) { if ( pool -> pool_insn ) { insn = PREV_INSN ( insn ) ; delete_insn ( NEXT_INSN ( insn ) ) ; continue ; } pool -> pool_insn = insn ; } if ( ! TARGET_CPU_ZARCH && s390_execute_label ( insn ) ) { s390_add_execute ( pool , insn ) ; } else if ( NONJUMP_INSN_P ( insn ) || CALL_P ( insn ) ) { rtx pool_ref = NULL_RTX ; find_constant_pool_ref ( PATTERN ( insn ) , & pool_ref ) ; if ( pool_ref ) { rtx constant = get_pool_constant ( pool_ref ) ; machine_mode mode = get_pool_mode ( pool_ref ) ; s390_add_constant ( pool , constant , mode ) ; } } if ( NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_SWITCH_TEXT_SECTIONS && ! pool -> emit_pool_after ) pool -> emit_pool_after = PREV_INSN ( insn ) ; } gcc_assert ( pool -> pool_insn || pool -> size == 0 ) ; if ( pool -> size >= 4096 ) { remove_insn ( pool -> pool_insn ) ; s390_free_pool ( pool ) ; pool = NULL ; } if ( pool && ! pool -> emit_pool_after ) pool -> emit_pool_after = get_last_insn ( ) ; return pool ; } </s>

Collect main literal pool . Return NULL on overflow .


<s> const DataLayout * getDataLayout ( ) const override { return & DL ; } </s>


<s> static rtx riscv_emit_binary ( enum rtx_code code , rtx dest , rtx x , rtx y ) { return riscv_emit_set ( dest , gen_rtx_fmt_ee ( code , GET_MODE ( dest ) , x , y ) ) ; } </s>

Emit an instruction of the form ( set DEST ( CODE X Y ) ) .


<s> int current_function_special_page_vector ( rtx x ) { int num ; if ( ( GET_CODE ( x ) == SYMBOL_REF ) && ( SYMBOL_REF_FLAGS ( x ) & SYMBOL_FLAG_FUNCVEC_FUNCTION ) ) { tree list ; tree t = SYMBOL_REF_DECL ( x ) ; if ( TREE_CODE ( t ) != FUNCTION_DECL ) return 0 ; list = M32C_ATTRIBUTES ( t ) ; while ( list ) { if ( is_attribute_p ( "function_vector" , TREE_PURPOSE ( list ) ) ) { num = TREE_INT_CST_LOW ( TREE_VALUE ( TREE_VALUE ( list ) ) ) ; return num ; } list = TREE_CHAIN ( list ) ; } return 0 ; } else return 0 ; } </s>

If the function is assigned the attribute 'function_vector ' , it returns the function vector number , otherwise returns zero .


" Instructions Emitted in this clause\n"

ScheduleDAGMI has scheduled an instruction - tell HazardRec about it .


<s> void emitZerofill ( MCSection * Section , MCSymbol * Symbol = nullptr , uint64_t Size = 0 , unsigned ByteAlignment = 0 , SMLoc Loc = SMLoc ( ) ) override { } </s>

Emit the zerofill section and an optional symbol .


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , computeDataLayout ( TT , is64bit ) , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < SparcELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this , is64bit ) { initAsmInfo ( ) ; } </s>


<s> bool ldsRequiresM0Init ( ) const { return getGeneration ( ) < GFX9 ; } </s>

Return if most LDS instructions have an m0 use that require m0 to be initialized .


"no low registers available for popping high registers"

The bits which are n't usefully expanded as rtl .


<s> static int ix86_fp_cmp_code_to_pcmp_immediate ( enum rtx_code code ) { switch ( code ) { case EQ : return 0x08 ; case NE : return 0x04 ; case GT : return 0x16 ; case LE : return 0x1a ; case GE : return 0x15 ; case LT : return 0x19 ; default : gcc_unreachable ( ) ; } } </s>

Helper for ix86_cmp_code_to_pcmp_immediate for fp modes .


<s> bool FPGATTIImpl :: isSourceOfDivergence ( const Value * V ) { if ( const Argument * Arg = dyn_cast < Argument > ( V ) ) return ! IsKernelFunction ( * Arg -> getParent ( ) ) ; if ( const Instruction * I = dyn_cast < Instruction > ( V ) ) { if ( const LoadInst * LI = dyn_cast < LoadInst > ( I ) ) { unsigned AS = LI -> getPointerAddressSpace ( ) ; return AS == 0 ; } if ( const AllocaInst * AI = dyn_cast < AllocaInst > ( I ) ) { unsigned AS = AI -> getType ( ) -> getPointerAddressSpace ( ) ; return AS == 0 ; } if ( I -> isAtomic ( ) ) return true ; if ( const IntrinsicInst * II = dyn_cast < IntrinsicInst > ( I ) ) { if ( readsLocalId ( II ) ) return true ; if ( readWorkgroupInvariant ( II ) ) return false ; if ( isPureFunction ( II ) ) return false ; } if ( isa < CallInst > ( I ) ) return true ; } return false ; } </s>

Returns whether V is a source of divergence .


<s> static int riscv_build_integer ( struct riscv_integer_op * codes , HOST_WIDE_INT value , enum machine_mode mode ) { int cost = riscv_build_integer_1 ( codes , value , mode ) ; if ( value > 0 && cost > 2 ) { struct riscv_integer_op alt_codes [ RISCV_MAX_INTEGER_OPS ] ; int alt_cost , shift = clz_hwi ( value ) ; HOST_WIDE_INT shifted_val ; shifted_val = ( value << shift ) | ( ( ( ( HOST_WIDE_INT ) 1 ) << shift ) - 1 ) ; alt_cost = 1 + riscv_build_integer_1 ( alt_codes , shifted_val , mode ) ; if ( alt_cost < cost ) { alt_codes [ alt_cost - 1 ] . code = LSHIFTRT ; alt_codes [ alt_cost - 1 ] . value = shift ; memcpy ( codes , alt_codes , sizeof ( alt_codes ) ) ; cost = alt_cost ; } shifted_val = value << shift ; alt_cost = 1 + riscv_build_integer_1 ( alt_codes , shifted_val , mode ) ; if ( alt_cost < cost ) { alt_codes [ alt_cost - 1 ] . code = LSHIFTRT ; alt_codes [ alt_cost - 1 ] . value = shift ; memcpy ( codes , alt_codes , sizeof ( alt_codes ) ) ; cost = alt_cost ; } } return cost ; } </s>

Fill CODES with a sequence of rtl operations to load VALUE . Return the number of operations needed .


<s> bool msp430_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( ( mode1 == PSImode || mode2 == SImode ) || ( mode1 == SImode || mode2 == PSImode ) ) return false ; return ( ( GET_MODE_CLASS ( mode1 ) == MODE_FLOAT || GET_MODE_CLASS ( mode1 ) == MODE_COMPLEX_FLOAT ) == ( GET_MODE_CLASS ( mode2 ) == MODE_FLOAT || GET_MODE_CLASS ( mode2 ) == MODE_COMPLEX_FLOAT ) ) ; } </s>


<s> bool Z80TargetLowering :: IsEligibleForTailCallOptimization ( SDValue Callee , CallingConv :: ID CalleeCC , bool isVarArg , Type * RetTy , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SmallVectorImpl < ISD :: InputArg > & Ins , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function * CallerF = MF . getFunction ( ) ; CallingConv :: ID CallerCC = CallerF -> getCallingConv ( ) ; if ( CalleeCC != CallingConv :: C || CallerCC != CallingConv :: C ) return false ; LLVMContext & C = * DAG . getContext ( ) ; if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , RetCC_Z80_C , RetCC_Z80_C ) ) return false ; if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , 16 > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , getCCAssignFn ( CalleeCC ) ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; for ( unsigned i = 0 , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; ISD :: ArgFlagsTy Flags = Outs [ i ] . Flags ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( VA . isMemLoc ( ) && ! MatchingStackOffset ( Arg , VA . getLocMemOffset ( ) , Flags , MFI , MRI , TII ) ) return false ; } } } return true ; } </s>

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization .


<s>
void
Mips16FrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
const
Mips16InstrInfo
&
TII
=
*
static_cast
<
const
Mips16InstrInfo
*
>
(
STI
.
getInstrInfo
(
)
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
dl
;
uint64_t
StackSize
=
MFI
.
getStackSize
(
)
;
if
(
StackSize
==
0
&&
!
MFI
.
adjustsStack
(
)
)
return
;
MachineModuleInfo
&
MMI
=
MF
.
getMMI
(
)
;
const
MCRegisterInfo
*
MRI
=
MMI
.
getContext
(
)
.
getRegisterInfo
(
)
;
MachineLocation
DstML
,
SrcML
;
TII
.
makeFrame
(
Mips
::
SP
,
StackSize
,
MBB
,
MBBI
)
;
unsigned
CFIIndex
=
MMI
.
addFrameInst
(
MCCFIInstruction
::
createDefCfaOffset
(
nullptr
,
StackSize
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
TargetOpcode
::
CFI_INSTRUCTION
)
)
.
addCFIIndex
(
CFIIndex
)
;
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
.
getCalleeSavedInfo
(
)
;
if
(
CSI
.
size
(
)
)
{
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
.
getCalleeSavedInfo
(
)
;
for
(
std
::
vector
<
CalleeSavedInfo
>
::
const_iterator
I
=
CSI
.
begin
(
)
,
E
=
CSI
.
end
(
)
;
I
!=
E
;
++
I
)
{
int64_t
Offset
=
MFI
.
getObjectOffset
(
I
->
getFrameIdx
(
)
)
;
unsigned
Reg
=
I
->
getReg
(
)
;
unsigned
DReg
=
MRI
->
getDwarfRegNum
(
Reg
,
true
)
;
unsigned
CFIIndex
=
MMI
.
addFrameInst
(
MCCFIInstruction
::
createOffset
(
nullptr
,
DReg
,
Offset
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
TargetOpcode
::
CFI_INSTRUCTION
)
)
.
addCFIIndex
(
CFIIndex
)
;
}
}
if
(
hasFP
(
MF
)
)
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Mips
::
MoveR3216
)
,
Mips
::
S0
)
.
addReg
(
Mips
::
SP
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Mips
Mips
"Shrink-wrapping not yet supported"
Mips
Mips
0
Mips::SP
Mips::MoveR3216
Mips::S0
Mips::SP


"First entry in the cond vector not imm-val"

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> LM32TargetLowering :: ConstraintType LM32TargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'd' : case 'y' : case 'f' : return C_RegisterClass ; break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> const SparcRegisterInfo * getRegisterInfo ( ) const override { return getSubtargetImpl ( ) -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
bool
MipsAsmPrinter
::
doInitialization
(
Module
&
M
)
{
Mang
=
new
Mangler
(
M
,
""
,
TAI
->
getPrivateGlobalPrefix
(
)
)
;
O
<<
"\t.section .mdebug."
<<
emitCurrentABIString
(
)
<<
'\n'
;
if
(
Subtarget
->
isABI_EABI
(
)
)
O
<<
"\t.section .gcc_compiled_long"
<<
(
Subtarget
->
isGP32bit
(
)
"32"
:
"64"
)
<<
'\n'
;
O
<<
"\t.previous"
<<
'\n'
;
return
false
;
}
</s>

Set up the AsmPrinter when we are working on a new module .


<s> void rs6000_expand_interleave ( rtx target , rtx op0 , rtx op1 , bool highp ) { machine_mode vmode = GET_MODE ( target ) ; unsigned i , high , nelt = GET_MODE_NUNITS ( vmode ) ; vec_perm_builder perm ( nelt , nelt , 1 ) ; high = ( highp ? 0 : nelt / 2 ) ; for ( i = 0 ; i < nelt / 2 ; i ++ ) { perm . quick_push ( i + high ) ; perm . quick_push ( i + nelt + high ) ; } rs6000_do_expand_vec_perm ( target , op0 , op1 , vmode , perm ) ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> OperandMatchResultTy MINA32AsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { const AsmToken & Tok = getParser ( ) . getTok ( ) ; if ( Tok . is ( AsmToken :: Identifier ) ) { std :: string lowerCase = Tok . getString ( ) . lower ( ) ; RegNo = matchRegisterName ( lowerCase ) ; if ( RegNo != 0 ) { return MatchOperand_Success ; } } return MatchOperand_NoMatch ; } </s>

tryParseRegister - parse one register if possible


<s> bool X86TTIImpl :: isLegalMaskedLoad ( Type * DataTy ) { if ( isa < VectorType > ( DataTy ) && DataTy -> getVectorNumElements ( ) == 1 ) return false ; Type * ScalarTy = DataTy -> getScalarType ( ) ; int DataWidth = isa < PointerType > ( ScalarTy ) ? DL . getPointerSizeInBits ( ) : ScalarTy -> getPrimitiveSizeInBits ( ) ; return ( ( DataWidth == 32 || DataWidth == 64 ) && ST -> hasAVX ( ) ) || ( ( DataWidth == 8 || DataWidth == 16 ) && ST -> hasBWI ( ) ) ; } </s>

Return true if the target supports masked load .


<s> std :: pair < unsigned , const TargetRegisterClass * > AArch64TargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & AArch64 :: GPR64commonRegClass ) ; return std :: make_pair ( 0U , & AArch64 :: GPR32commonRegClass ) ; case 'w' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , & AArch64 :: FPR32RegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & AArch64 :: FPR64RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & AArch64 :: FPR128RegClass ) ; break ; case 'x' : if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & AArch64 :: FPR128_loRegClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( AArch64 :: NZCV ) , & AArch64 :: CCRRegClass ) ; std :: pair < unsigned , const TargetRegisterClass * > Res ; Res = TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; if ( ! Res . second ) { unsigned Size = Constraint . size ( ) ; if ( ( Size == 4 || Size == 5 ) && Constraint [ 0 ] == '{' && tolower ( Constraint [ 1 ] ) == 'v' && Constraint [ Size - 1 ] == '}' ) { const std :: string Reg = std :: string ( & Constraint [ 2 ] , & Constraint [ Size - 1 ] ) ; int RegNo = atoi ( Reg . c_str ( ) ) ; if ( RegNo >= 0 && RegNo <= 31 ) { Res . first = AArch64 :: FPR128RegClass . getRegister ( RegNo ) ; Res . second = & AArch64 :: FPR128RegClass ; } } } return Res ; } </s>

Given a physical register constraint ( e.g .


<s> PPCTargetLowering :: ConstraintType PPCTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'b' : case 'r' : case 'f' : case 'v' : case 'y' : return C_RegisterClass ; case 'Z' : return C_Memory ; } } else if ( Constraint == "wc" ) { return C_RegisterClass ; } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>


"WebAssembly doesn't support non-C calling conventions"

"WebAssembly hasn't implemented inalloca arguments"

"WebAssembly hasn't implemented nest arguments"

"WebAssembly hasn't implemented cons regs arguments"

"WebAssembly hasn't implemented cons regs last arguments"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> static bool v850_output_addr_const_extra ( FILE * file , rtx x ) { if ( GET_CODE ( x ) != TRUNCATE ) return false ; x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == MINUS && GET_CODE ( XEXP ( x , 0 ) ) == LABEL_REF ) { rtx_code_label * label = dyn_cast < rtx_code_label * > ( XEXP ( XEXP ( x , 0 ) , 0 ) ) ; if ( label && label -> deleted ( ) ) return true ; } output_addr_const ( file , x ) ; return true ; } </s>

When assemble_integer is used to emit the offsets for a switch table it can encounter ( TRUNCATE : HI ( MINUS : SI ( LABEL_REF : SI ) ( LABEL_REF : SI ) ) ) . output_addr_const will normally barf at this , but it is OK to omit the truncate and just emit the difference of the two labels . The .hword directive will automatically handle the truncation for us . Returns 1 if rtx was handled , 0 otherwise .


<s> static char * rs6000_offload_options ( void ) { if ( TARGET_64BIT ) return xstrdup ( "-foffload-abi=lp64" ) ; else return xstrdup ( "-foffload-abi=ilp32" ) ; } </s>

Implement the TARGET_OFFLOAD_OPTIONS hook .


"No ISEL instructions in this function\n"

runOnMachineFunction - Emit the function body .


"Only support MVT::i32 register passing"

"Can only pass arguments as either registers or via the stack"


<s> void aarch64_expand_compare_and_swap ( rtx operands [ ] ) { rtx bval , rval , mem , oldval , newval , is_weak , mod_s , mod_f , x ; machine_mode mode , cmp_mode ; rtx ( * gen ) ( rtx , rtx , rtx , rtx , rtx , rtx , rtx ) ; bval = operands [ 0 ] ; rval = operands [ 1 ] ; mem = operands [ 2 ] ; oldval = operands [ 3 ] ; newval = operands [ 4 ] ; is_weak = operands [ 5 ] ; mod_s = operands [ 6 ] ; mod_f = operands [ 7 ] ; mode = GET_MODE ( mem ) ; cmp_mode = mode ; if ( INTVAL ( mod_f ) == MEMMODEL_ACQUIRE && INTVAL ( mod_s ) == MEMMODEL_RELEASE ) mod_s = GEN_INT ( MEMMODEL_ACQ_REL ) ; switch ( mode ) { case QImode : case HImode : cmp_mode = SImode ; rval = gen_reg_rtx ( SImode ) ; oldval = convert_modes ( SImode , mode , oldval , true ) ; case SImode : case DImode : if ( ! aarch64_plus_operand ( oldval , mode ) ) oldval = force_reg ( cmp_mode , oldval ) ; break ; default : gcc_unreachable ( ) ; } switch ( mode ) { case QImode : gen = gen_atomic_compare_and_swapqi_1 ; break ; case HImode : gen = gen_atomic_compare_and_swaphi_1 ; break ; case SImode : gen = gen_atomic_compare_and_swapsi_1 ; break ; case DImode : gen = gen_atomic_compare_and_swapdi_1 ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( rval , mem , oldval , newval , is_weak , mod_s , mod_f ) ) ; if ( mode == QImode || mode == HImode ) emit_move_insn ( operands [ 1 ] , gen_lowpart ( mode , rval ) ) ; x = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_EQ ( SImode , x , const0_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , bval , x ) ) ; } </s>


<s> static const uint16_t * lookup ( unsigned opcode , unsigned domain ) { for ( const uint16_t ( & Row ) [ 3 ] : ReplaceableInstrs ) if ( Row [ domain - 1 ] == opcode ) return Row ; return nullptr ; } </s>

This method finds the value with the given Name in the the symbol table .


<s> const TargetRegisterClass * SIInstrInfo :: getRegClass ( const MCInstrDesc & TID , unsigned OpNum , const TargetRegisterInfo * TRI , const MachineFunction & MF ) const { if ( OpNum >= TID . getNumOperands ( ) ) return nullptr ; auto RegClass = TID . OpInfo [ OpNum ] . RegClass ; bool IsAllocatable = false ; if ( TID . TSFlags & ( SIInstrFlags :: DS | SIInstrFlags :: FLAT ) ) { const int VDstIdx = AMDGPU :: getNamedOperandIdx ( TID . Opcode , AMDGPU :: OpName :: vdst ) ; const int DataIdx = AMDGPU :: getNamedOperandIdx ( TID . Opcode , ( TID . TSFlags & SIInstrFlags :: DS ) ? AMDGPU :: OpName :: data0 : AMDGPU :: OpName :: vdata ) ; if ( DataIdx != - 1 ) { IsAllocatable = VDstIdx != - 1 || AMDGPU :: getNamedOperandIdx ( TID . Opcode , AMDGPU :: OpName :: data1 ) != - 1 ; } } return adjustAllocatableRegClass ( ST , RI , MF . getRegInfo ( ) , TID , RegClass , IsAllocatable ) ; } </s>

Given a machine instruction descriptor , returns the register class constraint for OpNum , or NULL .

AMDGPU SI SIInstrFlags::DS SIInstrFlags::FLAT AMDGPU::getNamedOperandIdx AMDGPU::OpName AMDGPU::getNamedOperandIdx SIInstrFlags::DS AMDGPU::OpName AMDGPU::OpName 1 1 AMDGPU::getNamedOperandIdx AMDGPU::OpName 1


<s>
void
output_pop_multiple
(
rtx
insn
,
rtx
*
operands
)
{
char
buf
[
80
]
;
int
ok
;
ok
=
analyze_pop_multiple_operation
(
PATTERN
(
insn
)
)
;
gcc_assert
(
ok
)
;
if
(
first_dreg_to_save
==
8
)
sprintf
(
buf
,
"( p5:%d ) = [sp++];\n"
,
first_preg_to_save
)
;
else
if
(
first_preg_to_save
==
6
)
sprintf
(
buf
,
"( r7:%d ) = [sp++];\n"
,
first_dreg_to_save
)
;
else
sprintf
(
buf
,
"( r7:%d, p5:%d ) = [sp++];\n"
,
first_dreg_to_save
,
first_preg_to_save
)
;
output_asm_insn
(
buf
,
operands
)
;
}
</s>

Emit assembly code for one multi-register pop described by INSN , with operands in OPERANDS .


<s> uint64_t MipsAbiFlags :: size ( ) { return sizeof ( ElfMipsAbiFlags ) ; } </s>

The number of name/type pairs is returned .


<s> void R600MCCodeEmitter :: Emit ( uint64_t Value , raw_ostream & OS ) const { for ( unsigned i = 0 ; i < 8 ; i ++ ) { EmitByte ( ( Value >> ( 8 * i ) ) & 0xff , OS ) ; } } </s>


<s> bool memreg_operand ( rtx op , machine_mode mode ATTRIBUTE_UNUSED ) { return MEM_P ( op ) && REG_P ( XEXP ( op , 0 ) ) ; } </s>

Return 1 if OP is ( mem ( reg ... ) ) . This is used in insn length calcs .


<s> SDNode * SparcDAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = TM . getSubtargetImpl ( ) -> getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI -> getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s>
void
AArch64Operand
::
print
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
k_FPImm
:
OS
<<
"<fpimm "
<<
getFPImm
(
)
.
bitcastToAPInt
(
)
.
getZExtValue
(
)
;
if
(
!
getFPImmIsExact
(
)
)
OS
<<
" (inexact)"
;
OS
<<
">"
;
break
;
case
k_Barrier
:
{
StringRef
Name
=
getBarrierName
(
)
;
if
(
!
Name
.
empty
(
)
)
OS
<<
"<barrier "
<<
Name
<<
">"
;
else
OS
<<
"<barrier invalid #"
<<
getBarrier
(
)
<<
">"
;
break
;
}
case
k_Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
k_ShiftedImm
:
{
unsigned
Shift
=
getShiftedImmShift
(
)
;
OS
<<
"<shiftedimm "
;
OS
<<
*
getShiftedImmVal
(
)
;
OS
<<
", lsl #"
<<
AArch64_AM
::
getShiftValue
(
Shift
)
<<
">"
;
break
;
}
case
k_CondCode
:
OS
<<
"<condcode "
<<
getCondCode
(
)
<<
">"
;
break
;
case
k_VectorList
:
{
OS
<<
"<vectorlist "
;
unsigned
Reg
=
getVectorListStart
(
)
;
for
(
unsigned
i
=
0
,
e
=
getVectorListCount
(
)
;
i
!=
e
;
++
i
)
OS
<<
Reg
+
i
<<
" "
;
OS
<<
">"
;
break
;
}
case
k_VectorIndex
:
OS
<<
"<vectorindex "
<<
getVectorIndex
(
)
<<
">"
;
break
;
case
k_SysReg
:
OS
<<
"<sysreg: "
<<
getSysReg
(
)
<<
'>'
;
break
;
case
k_Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
case
k_SysCR
:
OS
<<
"c"
<<
getSysCR
(
)
;
break
;
case
k_Prefetch
:
{
StringRef
Name
=
getPrefetchName
(
)
;
if
(
!
Name
.
empty
(
)
)
OS
<<
"<prfop "
<<
Name
<<
">"
;
else
OS
<<
"<prfop invalid #"
<<
getPrefetch
(
)
<<
">"
;
break
;
}
case
k_PSBHint
:
OS
<<
getPSBHintName
(
)
;
break
;
case
k_BTIHint
:
OS
<<
getBTIHintName
(
)
;
break
;
case
k_Register
:
OS
<<
"<register "
<<
getReg
(
)
<<
">"
;
if
(
!
getShiftExtendAmount
(
)
&&
!
hasShiftExtendAmount
(
)
)
break
;
LLVM_FALLTHROUGH
;
case
k_ShiftExtend
:
OS
<<
"<"
<<
AArch64_AM
::
getShiftExtendName
(
getShiftExtendType
(
)
)
<<
" #"
<<
getShiftExtendAmount
(
)
;
if
(
!
hasShiftExtendAmount
(
)
)
OS
<<
"<imp>"
;
OS
<<
'>'
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

AArch64
AArch64
"<fpimm "
" (inexact)"
">"
"<barrier "
">"
"<barrier invalid #"
">"
"<shiftedimm "
", lsl #"
AArch64_AM::getShiftValue
">"
"<condcode "
">"
"<vectorlist "
0
" "
">"
"<vectorindex "
">"
"<sysreg: "
"'"
"'"
"c"
"<prfop "
">"
"<prfop invalid #"
">"
"<register "
">"
"<"
AArch64_AM::getShiftExtendName
" #"
"<imp>"


"Memory Intrinsic results: call to builtin function "

"with wrong signature, from/to mismatch"

optimizeCall - Take the given call instruction and return a more optimal value to replace the instruction with or 0 if a more optimal form ca n't be found .


<s> static bool arm_evpc_neon_vuzp ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> perm . length ( ) ; rtx out0 , out1 , in0 , in1 ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; int first_elem ; int swap_nelt ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; swap_nelt = BYTES_BIG_ENDIAN && ! d -> one_vector_p && GET_MODE_SIZE ( d -> vmode ) == 8 ? nelt : 0 ; first_elem = d -> perm [ neon_endian_lane_map ( d -> vmode , 0 ) ] ^ swap_nelt ; if ( first_elem == neon_endian_lane_map ( d -> vmode , 0 ) ) odd = 0 ; else if ( first_elem == neon_endian_lane_map ( d -> vmode , 1 ) ) odd = 1 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt ; i ++ ) { unsigned elt = ( neon_pair_endian_lane_map ( d -> vmode , i ) * 2 + odd ) & mask ; if ( ( d -> perm [ i ] ^ swap_nelt ) != neon_pair_endian_lane_map ( d -> vmode , elt ) ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case E_V16QImode : gen = gen_neon_vuzpv16qi_internal ; break ; case E_V8QImode : gen = gen_neon_vuzpv8qi_internal ; break ; case E_V8HImode : gen = gen_neon_vuzpv8hi_internal ; break ; case E_V4HImode : gen = gen_neon_vuzpv4hi_internal ; break ; case E_V8HFmode : gen = gen_neon_vuzpv8hf_internal ; break ; case E_V4HFmode : gen = gen_neon_vuzpv4hf_internal ; break ; case E_V4SImode : gen = gen_neon_vuzpv4si_internal ; break ; case E_V2SImode : gen = gen_neon_vuzpv2si_internal ; break ; case E_V2SFmode : gen = gen_neon_vuzpv2sf_internal ; break ; case E_V4SFmode : gen = gen_neon_vuzpv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d -> op1 ; if ( swap_nelt != 0 ) std :: swap ( in0 , in1 ) ; out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( odd ) std :: swap ( out0 , out1 ) ; emit_insn ( gen ( out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


"internal error: cris_side_effect_mode_ok with bad operands"

Check various objections to the side-effect . Used in the test-part of an anonymous insn describing an insn with a possible side-effect . Returns nonzero if the implied side-effect is ok. code : PLUS or MULT ops : An array of rtx : es . lreg , rreg , rval , The variables multop and other_op are indexes into this , or -1 if they are not applicable . lreg : The register that gets assigned in the side-effect . rreg : One register in the side-effect expression rval : The other register , or an int . multop : An integer to multiply rval with . other_op : One of the entities of the main effect , whose mode we must consider .


"This eliminateCallFramePseudoInstr does not support Thumb1!"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool RISCVTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; Optional < unsigned > FirstMaskArgument ; if ( Subtarget . hasStdExtV ( ) ) FirstMaskArgument = preAssignMask ( Outs ) ; for ( unsigned i = 0 , e = Outs . size ( ) ; i != e ; ++ i ) { MVT VT = Outs [ i ] . VT ; ISD :: ArgFlagsTy ArgFlags = Outs [ i ] . Flags ; RISCVABI :: ABI ABI = MF . getSubtarget < RISCVSubtarget > ( ) . getTargetABI ( ) ; if ( CC_RISCV ( MF . getDataLayout ( ) , ABI , i , VT , VT , CCValAssign :: Full , ArgFlags , CCInfo , true , true , nullptr , * this , FirstMaskArgument ) ) return false ; } return true ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .

RI5CY RISCV ISD::OutputArg 16 0 ISD::ArgFlagsTy RISCVABI::ABI RISCV RISCV


<s> virtual const KudeyarInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> bool HexagonAsmParser :: isLabel ( AsmToken & Token ) { MCAsmLexer & Lexer = getLexer ( ) ; AsmToken const & Second = Lexer . getTok ( ) ; AsmToken Third = Lexer . peekTok ( ) ; StringRef String = Token . getString ( ) ; if ( Token . is ( AsmToken :: TokenKind :: LCurly ) || Token . is ( AsmToken :: TokenKind :: RCurly ) ) return false ; if ( ! Token . is ( AsmToken :: TokenKind :: Identifier ) ) return true ; if ( ! MatchRegisterName ( String . lower ( ) ) ) return true ; ( void ) Second ; assert ( Second . is ( AsmToken :: Colon ) ) ; StringRef Raw ( String . data ( ) , Third . getString ( ) . data ( ) - String . data ( ) + Third . getString ( ) . size ( ) ) ; std :: string Collapsed = Raw ; Collapsed . erase ( std :: remove_if ( Collapsed . begin ( ) , Collapsed . end ( ) , isspace ) , Collapsed . end ( ) ) ; StringRef Whole = Collapsed ; std :: pair < StringRef , StringRef > DotSplit = Whole . split ( '.' ) ; if ( ! MatchRegisterName ( DotSplit . first . lower ( ) ) ) return true ; return false ; } </s>

Returns true if the MachineInstr represents a label .


<s> bool pre_incdec_with_reg ( rtx op , unsigned int reg ) { if ( GET_CODE ( op ) != MEM ) return false ; op = XEXP ( op , 0 ) ; if ( GET_CODE ( op ) != PRE_DEC && GET_CODE ( op ) != PRE_INC ) return false ; op = XEXP ( op , 0 ) ; if ( ! REG_P ( op ) ) return false ; return REGNO ( op ) == reg ; } </s>

Return TRUE if OP is a PRE_INC or PRE_DEC instruction using REG , FALSE otherwise .


<s> static bool moxie_function_value_regno_p ( const unsigned int regno ) { return ( regno == MOXIE_R0 ) ; } </s>

Handle TARGET_FUNCTION_VALUE_REGNO_P . We always return values in register $ r0 for moxie .


<s> unsigned int rs6000_function_arg_boundary ( machine_mode mode , const_tree type ) { machine_mode elt_mode ; int n_elts ; rs6000_discover_homogeneous_aggregate ( mode , type , & elt_mode , & n_elts ) ; if ( DEFAULT_ABI == ABI_V4 && ( GET_MODE_SIZE ( mode ) == 8 || ( TARGET_HARD_FLOAT && ! is_complex_IBM_long_double ( mode ) && FLOAT128_2REG_P ( mode ) ) ) ) return 64 ; else if ( FLOAT128_VECTOR_P ( mode ) ) return 128 ; else if ( type && TREE_CODE ( type ) == VECTOR_TYPE && int_size_in_bytes ( type ) >= 8 && int_size_in_bytes ( type ) < 16 ) return 64 ; else if ( ALTIVEC_OR_VSX_VECTOR_MODE ( elt_mode ) || ( type && TREE_CODE ( type ) == VECTOR_TYPE && int_size_in_bytes ( type ) >= 16 ) ) return 128 ; if ( ( ( DEFAULT_ABI == ABI_AIX && ! rs6000_compat_align_parm ) || DEFAULT_ABI == ABI_ELFv2 ) && type && TYPE_ALIGN ( type ) > 64 ) { if ( AGGREGATE_TYPE_P ( type ) && ! SCALAR_FLOAT_MODE_P ( elt_mode ) ) return 128 ; } if ( TARGET_MACHO && rs6000_darwin64_abi && mode == BLKmode && type && TYPE_ALIGN ( type ) > 64 ) return 128 ; return PARM_BOUNDARY ; } </s>

If defined , a C expression that gives the alignment boundary , in bits , of an argument with the specified mode and type . If it is not defined , PARM_BOUNDARY is used for all arguments . V.4 wants long longs and doubles to be double word aligned . Just testing the mode size is a boneheaded way to do this as it means that other types such as complex int are also double word aligned . However , we 're stuck with this because changing the ABI might break existing library interfaces . Quadword align Altivec/VSX vectors . Quadword align large synthetic vector types .


<s>
bool
HexagonExpandCondsets
::
split
(
MachineInstr
&
MI
,
std
::
set
<
unsigned
>
&
UpdRegs
)
{
if
(
TfrLimitActive
)
{
if
(
TfrCounter
>=
TfrLimit
)
return
false
;
TfrCounter
++
;
}
DEBUG
(
dbgs
(
)
<<
"\nsplitting "
<<
printMBBReference
(
*
MI
.
getParent
(
)
)
<<
": "
<<
MI
)
;
MachineOperand
&
MD
=
MI
.
getOperand
(
0
)
;
MachineOperand
&
MP
=
MI
.
getOperand
(
1
)
;
assert
(
MD
.
isDef
(
)
)
;
unsigned
DR
=
MD
.
getReg
(
)
,
DSR
=
MD
.
getSubReg
(
)
;
bool
ReadUndef
=
MD
.
isUndef
(
)
;
MachineBasicBlock
::
iterator
At
=
MI
;
auto
updateRegs
=
[
&
UpdRegs
]
(
const
MachineInstr
&
MI
)
->
void
{
for
(
auto
&
Op
:
MI
.
operands
(
)
)
if
(
Op
.
isReg
(
)
)
UpdRegs
.
insert
(
Op
.
getReg
(
)
)
;
}
;
MachineOperand
&
ST
=
MI
.
getOperand
(
2
)
;
MachineOperand
&
SF
=
MI
.
getOperand
(
3
)
;
if
(
ST
.
isReg
(
)
&&
SF
.
isReg
(
)
)
{
RegisterRef
RT
(
ST
)
;
if
(
RT
==
RegisterRef
(
SF
)
)
{
updateRegs
(
MI
)
;
MI
.
setDesc
(
HII
->
get
(
TargetOpcode
::
COPY
)
)
;
unsigned
S
=
getRegState
(
ST
)
;
while
(
MI
.
getNumOperands
(
)
>
1
)
MI
.
RemoveOperand
(
MI
.
getNumOperands
(
)
1
)
;
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
MachineInstrBuilder
(
MF
,
MI
)
.
addReg
(
RT
.
Reg
,
S
,
RT
.
Sub
)
;
return
true
;
}
}
MachineInstr
*
TfrT
=
genCondTfrFor
(
ST
,
At
,
DR
,
DSR
,
MP
,
true
,
ReadUndef
,
false
)
;
MachineInstr
*
TfrF
=
genCondTfrFor
(
SF
,
At
,
DR
,
DSR
,
MP
,
false
,
ReadUndef
,
true
)
;
LIS
->
InsertMachineInstrInMaps
(
*
TfrT
)
;
LIS
->
InsertMachineInstrInMaps
(
*
TfrF
)
;
updateRegs
(
MI
)
;
removeInstr
(
MI
)
;
return
true
;
}
</s>

Split into substrings around the occurrences of a separator character .


<s> inline set_of_reg sh_find_set_of_reg ( rtx reg , rtx_insn * insn , F stepfunc , bool ignore_reg_reg_copies = false ) { set_of_reg result ; result . insn = insn ; result . set_rtx = NULL_RTX ; result . set_src = NULL_RTX ; if ( ! REG_P ( reg ) || insn == NULL_RTX ) return result ; rtx_insn * previnsn = insn ; for ( result . insn = stepfunc ( insn ) ; result . insn != NULL_RTX ; previnsn = result . insn , result . insn = stepfunc ( result . insn ) ) { if ( BARRIER_P ( result . insn ) ) break ; if ( ! NONJUMP_INSN_P ( result . insn ) ) continue ; if ( reg_set_p ( reg , result . insn ) ) { result . set_rtx = set_of ( reg , result . insn ) ; if ( result . set_rtx == NULL_RTX || GET_CODE ( result . set_rtx ) != SET ) break ; result . set_src = XEXP ( result . set_rtx , 1 ) ; if ( ignore_reg_reg_copies && REG_P ( result . set_src ) ) { reg = result . set_src ; continue ; } if ( ignore_reg_reg_copies && SUBREG_P ( result . set_src ) && REG_P ( SUBREG_REG ( result . set_src ) ) ) { reg = SUBREG_REG ( result . set_src ) ; continue ; } break ; } } if ( result . insn == NULL ) result . insn = previnsn ; if ( result . set_src != NULL ) gcc_assert ( result . insn != NULL && result . set_rtx != NULL ) ; return result ; } </s>

Given a reg rtx and a start insn , try to find the insn that sets the specified reg by using the specified insn stepping function , such as 'prev_nonnote_insn_bb ' . When the insn is found , try to extract the rtx of the reg set .


<s> static rtx ix86_static_chain ( const_tree fndecl_or_type , bool incoming_p ) { unsigned regno ; if ( TARGET_64BIT ) { regno = R10_REG ; } else { const_tree fntype , fndecl ; unsigned int ccvt ; regno = CX_REG ; if ( TREE_CODE ( fndecl_or_type ) == FUNCTION_DECL ) { fntype = TREE_TYPE ( fndecl_or_type ) ; fndecl = fndecl_or_type ; } else { fntype = fndecl_or_type ; fndecl = NULL ; } ccvt = ix86_get_callcvt ( fntype ) ; if ( ( ccvt & IX86_CALLCVT_FASTCALL ) != 0 ) { regno = AX_REG ; } else if ( ( ccvt & IX86_CALLCVT_THISCALL ) != 0 ) { regno = AX_REG ; } else if ( ix86_function_regparm ( fntype , fndecl ) == 3 ) { if ( incoming_p ) { if ( fndecl == current_function_decl && ! ix86_static_chain_on_stack ) { gcc_assert ( ! reload_completed ) ; ix86_static_chain_on_stack = true ; } return gen_frame_mem ( SImode , plus_constant ( Pmode , arg_pointer_rtx , - 8 ) ) ; } regno = SI_REG ; } } return gen_rtx_REG ( Pmode , regno ) ; } </s>

Find a location for the static chain incoming to a nested function . This is a register , unless all free registers are used by arguments .


<s> SDValue LanaiSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & , const SDLoc & , SDValue , SDValue , SDValue , SDValue Size , unsigned , bool , bool , MachinePointerInfo , MachinePointerInfo ) const { ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; if ( ! ConstantSize ) return SDValue ( ) ; return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .


<s> void nvptx_expand_call ( rtx retval , rtx address ) { rtx callee = XEXP ( address , 0 ) ; rtx varargs = NULL_RTX ; unsigned parallel = 0 ; if ( ! call_insn_operand ( callee , Pmode ) ) { callee = force_reg ( Pmode , callee ) ; address = change_address ( address , QImode , callee ) ; } if ( GET_CODE ( callee ) == SYMBOL_REF ) { tree decl = SYMBOL_REF_DECL ( callee ) ; if ( decl != NULL_TREE ) { if ( DECL_STATIC_CHAIN ( decl ) ) cfun -> machine -> has_chain = true ; tree attr = oacc_get_fn_attrib ( decl ) ; if ( attr ) { tree dims = TREE_VALUE ( attr ) ; parallel = GOMP_DIM_MASK ( GOMP_DIM_MAX ) - 1 ; for ( int ix = 0 ; ix != GOMP_DIM_MAX ; ix ++ ) { if ( TREE_PURPOSE ( dims ) && ! integer_zerop ( TREE_PURPOSE ( dims ) ) ) break ; parallel ^= GOMP_DIM_MASK ( ix ) ; dims = TREE_CHAIN ( dims ) ; } } } } unsigned nargs = cfun -> machine -> num_args ; if ( cfun -> machine -> is_varadic ) { varargs = gen_reg_rtx ( Pmode ) ; emit_move_insn ( varargs , stack_pointer_rtx ) ; } rtvec vec = rtvec_alloc ( nargs + 1 ) ; rtx pat = gen_rtx_PARALLEL ( VOIDmode , vec ) ; int vec_pos = 0 ; rtx call = gen_rtx_CALL ( VOIDmode , address , const0_rtx ) ; rtx tmp_retval = retval ; if ( retval ) { if ( ! nvptx_register_operand ( retval , GET_MODE ( retval ) ) ) tmp_retval = gen_reg_rtx ( GET_MODE ( retval ) ) ; call = gen_rtx_SET ( tmp_retval , call ) ; } XVECEXP ( pat , 0 , vec_pos ++ ) = call ; for ( rtx arg = cfun -> machine -> call_args ; arg ; arg = XEXP ( arg , 1 ) ) XVECEXP ( pat , 0 , vec_pos ++ ) = gen_rtx_USE ( VOIDmode , XEXP ( arg , 0 ) ) ; if ( varargs ) XVECEXP ( pat , 0 , vec_pos ++ ) = gen_rtx_USE ( VOIDmode , varargs ) ; gcc_assert ( vec_pos = XVECLEN ( pat , 0 ) ) ; nvptx_emit_forking ( parallel , true ) ; emit_call_insn ( pat ) ; nvptx_emit_joining ( parallel , true ) ; if ( tmp_retval != retval ) emit_move_insn ( retval , tmp_retval ) ; } </s>


<s> bool TeakInstrInfo :: isPredicated ( const MachineInstr & MI ) const { if ( MI . isBundle ( ) ) { MachineBasicBlock :: const_instr_iterator I = MI . getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI . getParent ( ) -> instr_end ( ) ; while ( ++ I != E && I -> isInsideBundle ( ) ) { int PIdx = I -> findFirstPredOperandIdx ( ) ; if ( PIdx != - 1 && I -> getOperand ( PIdx ) . getImm ( ) != TeakCC :: True ) return true ; } return false ; } int PIdx = MI . findFirstPredOperandIdx ( ) ; return PIdx != - 1 && MI . getOperand ( PIdx ) . getImm ( ) != TeakCC :: True ; } </s>

Returns true if the instruction is already predicated .


<s>
void
CSKYInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
MCRegister
DestReg
,
MCRegister
SrcReg
,
bool
KillSrc
)
const
{
MachineRegisterInfo
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
if
(
CSKY
::
GPRRegClass
.
contains
(
SrcReg
)
&&
CSKY
::
CARRYRegClass
.
contains
(
DestReg
)
)
{
if
(
STI
.
hasE2
(
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
CSKY
::
BTSTI32
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
0
)
;
}
else
{
assert
(
SrcReg
<
CSKY
::
R8
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
CSKY
::
BTSTI16
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
0
)
;
}
return
;
}
if
(
CSKY
::
CARRYRegClass
.
contains
(
SrcReg
)
&&
CSKY
::
GPRRegClass
.
contains
(
DestReg
)
)
{
if
(
STI
.
hasE2
(
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
CSKY
::
MVC32
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
else
{
assert
(
DestReg
<
CSKY
::
R16
)
;
assert
(
DestReg
<
CSKY
::
R8
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
CSKY
::
MOVI16
)
,
DestReg
)
.
addImm
(
0
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
CSKY
::
ADDC16
)
)
.
addReg
(
DestReg
,
RegState
::
Define
)
.
addReg
(
SrcReg
,
RegState
::
Define
)
.
addReg
(
DestReg
,
getKillRegState
(
true
)
)
.
addReg
(
DestReg
,
getKillRegState
(
true
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
true
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
CSKY
::
BTSTI16
)
)
.
addReg
(
SrcReg
,
RegState
::
Define
|
getDeadRegState
(
KillSrc
)
)
.
addReg
(
DestReg
)
.
addImm
(
0
)
;
}
return
;
}
unsigned
Opcode
=
0
;
if
(
CSKY
::
GPRRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
CSKY
::
MOV32
;
else
{
LLVM_DEBUG
(
dbgs
(
)
<<
"src = "
<<
SrcReg
<<
", dst = "
<<
DestReg
)
;
LLVM_DEBUG
(
I
->
dump
(
)
)
;
llvm_unreachable
(
"Unknown RegisterClass"
)
;
}
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opcode
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> bool MipsSEInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock & MBB = * MI -> getParent ( ) ; bool isMicroMips = TM . getSubtarget < MipsSubtarget > ( ) . inMicroMipsMode ( ) ; unsigned Opc ; switch ( MI -> getDesc ( ) . getOpcode ( ) ) { default : return false ; case Mips :: RetRA : expandRetRA ( MBB , MI , Mips :: RET ) ; break ; case Mips :: PseudoMFHI : Opc = isMicroMips ? Mips :: MFHI16_MM : Mips :: MFHI ; expandPseudoMFHiLo ( MBB , MI , Opc ) ; break ; case Mips :: PseudoMFLO : Opc = isMicroMips ? Mips :: MFLO16_MM : Mips :: MFLO ; expandPseudoMFHiLo ( MBB , MI , Opc ) ; break ; case Mips :: PseudoMFHI64 : expandPseudoMFHiLo ( MBB , MI , Mips :: MFHI64 ) ; break ; case Mips :: PseudoMFLO64 : expandPseudoMFHiLo ( MBB , MI , Mips :: MFLO64 ) ; break ; case Mips :: PseudoMTLOHI : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO , Mips :: MTHI , false ) ; break ; case Mips :: PseudoMTLOHI64 : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO64 , Mips :: MTHI64 , false ) ; break ; case Mips :: PseudoMTLOHI_DSP : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO_DSP , Mips :: MTHI_DSP , true ) ; break ; case Mips :: PseudoCVT_S_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_D32_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_D32_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_S_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_L , Mips :: DMTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_W , Mips :: MTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_L , Mips :: DMTC1 , true ) ; break ; case Mips :: BuildPairF64 : expandBuildPairF64 ( MBB , MI , false ) ; break ; case Mips :: BuildPairF64_64 : expandBuildPairF64 ( MBB , MI , true ) ; break ; case Mips :: ExtractElementF64 : expandExtractElementF64 ( MBB , MI , false ) ; break ; case Mips :: ExtractElementF64_64 : expandExtractElementF64 ( MBB , MI , true ) ; break ; case Mips :: MIPSeh_return32 : case Mips :: MIPSeh_return64 : expandEhReturn ( MBB , MI ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> static unsigned int aarch64_case_values_threshold ( void ) { if ( optimize > 2 && selected_cpu -> tune -> max_case_values != 0 ) return selected_cpu -> tune -> max_case_values ; else return optimize_size ? default_case_values_threshold ( ) : 17 ; } </s>


<s>
void
M68kMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
unsigned
Opcode
=
MI
.
getOpcode
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"EncodeInstruction: "
<<
MCII
.
getName
(
Opcode
)
<<
"("
<<
Opcode
<<
")\n"
)
;
APInt
EncodedInst
(
16
,
0U
)
;
APInt
Scratch
(
16
,
0U
)
;
getBinaryCodeForInstr
(
MI
,
Fixups
,
EncodedInst
,
Scratch
,
STI
)
;
ArrayRef
<
uint64_t
>
Data
(
EncodedInst
.
getRawData
(
)
,
EncodedInst
.
getNumWords
(
)
)
;
int64_t
InstSize
=
EncodedInst
.
getBitWidth
(
)
;
for
(
uint64_t
Word
:
Data
)
{
for
(
int
i
=
0
;
i
<
4
&&
InstSize
>
0
;
++
i
,
InstSize
-=
16
)
{
support
::
endian
::
write
<
uint16_t
>
(
OS
,
static_cast
<
uint16_t
>
(
Word
)
,
support
::
big
)
;
Word
>>=
16
;
}
}
}
</s>

Encode the given Inst to bytes and append to CB .


<s> void ia64_asm_output_external ( FILE * file , tree decl , const char * name ) { if ( TREE_SYMBOL_REFERENCED ( DECL_ASSEMBLER_NAME ( decl ) ) ) { int need_visibility = ( ( * targetm . binds_local_p ) ( decl ) && maybe_assemble_visibility ( decl ) ) ; if ( ( TARGET_HPUX_LD || ! TARGET_GNU_AS ) && TREE_CODE ( decl ) == FUNCTION_DECL ) ( * targetm . asm_out . globalize_decl_name ) ( file , decl ) ; else if ( need_visibility && ! TARGET_GNU_AS ) ( * targetm . asm_out . globalize_label ) ( file , name ) ; } } </s>

Emit text to declare externally defined variables and functions , because the Intel assembler does not support undefined externals .


<s> void MSP430RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( ! TFI -> hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; uint64_t Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = 0 ; if ( Old -> getOpcode ( ) == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( MSP430 :: SUB16ri ) , MSP430 :: SPW ) . addReg ( MSP430 :: SPW ) . addImm ( Amount ) ; } else { assert ( Old -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) ; uint64_t CalleeAmt = Old -> getOperand ( 1 ) . getImm ( ) ; Amount -= CalleeAmt ; if ( Amount ) New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( MSP430 :: ADD16ri ) , MSP430 :: SPW ) . addReg ( MSP430 :: SPW ) . addImm ( Amount ) ; } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { MachineInstr * Old = I ; MachineInstr * New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( MSP430 :: SUB16ri ) , MSP430 :: SPW ) . addReg ( MSP430 :: SPW ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } MBB . erase ( I ) ; } </s>


<s> bool AArch64FastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Add : case Instruction :: Sub : return selectAddSub ( I ) ; case Instruction :: Mul : return selectMul ( I ) ; case Instruction :: SDiv : return selectSDiv ( I ) ; case Instruction :: SRem : if ( ! selectBinaryOp ( I , ISD :: SREM ) ) return selectRem ( I , ISD :: SREM ) ; return true ; case Instruction :: URem : if ( ! selectBinaryOp ( I , ISD :: UREM ) ) return selectRem ( I , ISD :: UREM ) ; return true ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return selectShift ( I ) ; case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : return selectLogicalOp ( I ) ; case Instruction :: Br : return selectBranch ( I ) ; case Instruction :: IndirectBr : return selectIndirectBr ( I ) ; case Instruction :: BitCast : if ( ! FastISel :: selectBitCast ( I ) ) return selectBitCast ( I ) ; return true ; case Instruction :: FPToSI : if ( ! selectCast ( I , ISD :: FP_TO_SINT ) ) return selectFPToInt ( I , true ) ; return true ; case Instruction :: FPToUI : return selectFPToInt ( I , false ) ; case Instruction :: ZExt : case Instruction :: SExt : return selectIntExt ( I ) ; case Instruction :: Trunc : if ( ! selectCast ( I , ISD :: TRUNCATE ) ) return selectTrunc ( I ) ; return true ; case Instruction :: FPExt : return selectFPExt ( I ) ; case Instruction :: FPTrunc : return selectFPTrunc ( I ) ; case Instruction :: SIToFP : if ( ! selectCast ( I , ISD :: SINT_TO_FP ) ) return selectIntToFP ( I , true ) ; return true ; case Instruction :: UIToFP : return selectIntToFP ( I , false ) ; case Instruction :: Load : return selectLoad ( I ) ; case Instruction :: Store : return selectStore ( I ) ; case Instruction :: FCmp : case Instruction :: ICmp : return selectCmp ( I ) ; case Instruction :: Select : return selectSelect ( I ) ; case Instruction :: Ret : return selectRet ( I ) ; case Instruction :: FRem : return selectFRem ( I ) ; case Instruction :: GetElementPtr : return selectGetElementPtr ( I ) ; } return selectOperator ( I , I -> getOpcode ( ) ) ; ( void ) & CC_AArch64_DarwinPCS_VarArg ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s>
void
WebAssemblyMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
assert
(
false
&&
"FIXME: not implemented yet"
)
;
}
</s>

WebAssembly
WebAssembly
"FIXME: not implemented yet"


<s>
const
char
*
output_condmove_single
(
rtx
operands
[
]
,
rtx
insn
)
{
rtx
dest
=
operands
[
2
]
;
rtx
src
=
operands
[
3
]
;
if
(
GET_CODE
(
dest
)
==
REG
)
{
int
dest_regno
=
REGNO
(
dest
)
;
machine_mode
mode
=
GET_MODE
(
dest
)
;
if
(
GPR_P
(
dest_regno
)
)
{
if
(
GET_CODE
(
src
)
==
REG
)
{
int
src_regno
=
REGNO
(
src
)
;
if
(
GPR_P
(
src_regno
)
)
return
"cmov %z3, %2, %1, %e0"
;
else
if
(
FPR_P
(
src_regno
)
)
return
"cmovfg %3, %2, %1, %e0"
;
}
else
if
(
GET_CODE
(
src
)
==
MEM
)
{
switch
(
mode
)
{
default
:
break
;
case
E_QImode
:
return
"cldsb%I3%U3 %M3, %2, %1, %e0"
;
case
E_HImode
:
return
"cldsh%I3%U3 %M3, %2, %1, %e0"
;
case
E_SImode
:
case
E_SFmode
:
return
"cld%I3%U3 %M3, %2, %1, %e0"
;
}
}
else
if
(
ZERO_P
(
src
)
)
return
"cmov %., %2, %1, %e0"
;
}
else
if
(
FPR_P
(
dest_regno
)
)
{
if
(
GET_CODE
(
src
)
==
REG
)
{
int
src_regno
=
REGNO
(
src
)
;
if
(
GPR_P
(
src_regno
)
)
return
"cmovgf %3, %2, %1, %e0"
;
else
if
(
FPR_P
(
src_regno
)
)
{
if
(
TARGET_HARD_FLOAT
)
return
"cfmovs %3,%2,%1,%e0"
;
else
return
"cmor %3, %3, %2, %1, %e0"
;
}
}
else
if
(
GET_CODE
(
src
)
==
MEM
)
{
if
(
mode
==
SImode
||
mode
==
SFmode
)
return
"cldf%I3%U3 %M3, %2, %1, %e0"
;
}
else
if
(
ZERO_P
(
src
)
)
return
"cmovgf %., %2, %1, %e0"
;
}
}
else
if
(
GET_CODE
(
dest
)
==
MEM
)
{
if
(
GET_CODE
(
src
)
==
REG
)
{
int
src_regno
=
REGNO
(
src
)
;
machine_mode
mode
=
GET_MODE
(
dest
)
;
if
(
GPR_P
(
src_regno
)
)
{
switch
(
mode
)
{
default
:
break
;
case
E_QImode
:
return
"cstb%I2%U2 %3, %M2, %1, %e0"
;
case
E_HImode
:
return
"csth%I2%U2 %3, %M2, %1, %e0"
;
case
E_SImode
:
case
E_SFmode
:
return
"cst%I2%U2 %3, %M2, %1, %e0"
;
}
}
else
if
(
FPR_P
(
src_regno
)
&&
(
mode
==
SImode
||
mode
==
SFmode
)
)
return
"cstf%I2%U2 %3, %M2, %1, %e0"
;
}
else
if
(
ZERO_P
(
src
)
)
{
machine_mode
mode
=
GET_MODE
(
dest
)
;
switch
(
mode
)
{
default
:
break
;
case
E_QImode
:
return
"cstb%I2%U2 %., %M2, %1, %e0"
;
case
E_HImode
:
return
"csth%I2%U2 %., %M2, %1, %e0"
;
case
E_SImode
:
case
E_SFmode
:
return
"cst%I2%U2 %., %M2, %1, %e0"
;
}
}
}
fatal_insn
(
"bad output_condmove_single operand"
,
insn
)
;
return
""
;
}
</s>

Return a string to output a single word conditional move . Operand0 -- EQ/NE of ccr register and 0 Operand1 -- CCR register Operand2 -- destination Operand3 -- source


<s>
void
LanaiDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
return
;
}
EVT
VT
=
Node
->
getValueType
(
0
)
;
switch
(
Opcode
)
{
case
ISD
::
Constant
:
if
(
VT
==
MVT
::
i32
)
{
ConstantSDNode
*
ConstNode
=
cast
<
ConstantSDNode
>
(
Node
)
;
if
(
ConstNode
->
isNullValue
(
)
)
{
SDValue
New
=
CurDAG
->
getCopyFromReg
(
CurDAG
->
getEntryNode
(
)
,
SDLoc
(
Node
)
,
Lanai
::
R0
,
MVT
::
i32
)
;
return
ReplaceNode
(
Node
,
New
.
getNode
(
)
)
;
}
if
(
ConstNode
->
isAllOnesValue
(
)
)
{
SDValue
New
=
CurDAG
->
getCopyFromReg
(
CurDAG
->
getEntryNode
(
)
,
SDLoc
(
Node
)
,
Lanai
::
R1
,
MVT
::
i32
)
;
return
ReplaceNode
(
Node
,
New
.
getNode
(
)
)
;
}
}
break
;
case
ISD
::
FrameIndex
:
selectFrameIndex
(
Node
)
;
return
;
default
:
break
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> unsigned getPrefetchDistance ( ) const override { return 4500 ; } </s>

Return the preferred prefetch distance in terms of instructions .


<s> static machine_mode zero_call_used_regno_mode ( const unsigned int regno ) { if ( GENERAL_REGNO_P ( regno ) ) return SImode ; else if ( SSE_REGNO_P ( regno ) ) return V4SFmode ; else if ( MASK_REGNO_P ( regno ) ) return HImode ; else if ( MMX_REGNO_P ( regno ) ) return V2SImode ; else gcc_unreachable ( ) ; } </s>

Return the machine_mode that is used to zero register REGNO .


<s> const MipsSubtarget * MipsTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool hasMips16Attr = ! F . getFnAttribute ( "mips16" ) . hasAttribute ( Attribute :: None ) ; bool hasNoMips16Attr = ! F . getFnAttribute ( "nomips16" ) . hasAttribute ( Attribute :: None ) ; bool HasMicroMipsAttr = ! F . getFnAttribute ( "micromips" ) . hasAttribute ( Attribute :: None ) ; bool HasNoMicroMipsAttr = ! F . getFnAttribute ( "nomicromips" ) . hasAttribute ( Attribute :: None ) ; bool softFloat = F . hasFnAttribute ( "use-soft-float" ) && F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( hasMips16Attr ) FS += FS . empty ( ) ? "+mips16" : ",+mips16" ; else if ( hasNoMips16Attr ) FS += FS . empty ( ) ? "-mips16" : ",-mips16" ; if ( HasMicroMipsAttr ) FS += FS . empty ( ) ? "+micromips" : ",+micromips" ; else if ( HasNoMicroMipsAttr ) FS += FS . empty ( ) ? "-micromips" : ",-micromips" ; if ( softFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < MipsSubtarget > ( TargetTriple , CPU , FS , isLittle , * this , MaybeAlign ( Options . StackAlignmentOverride ) ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

Mips Mips Mips "target-cpu" "target-features" Mips "mips16" Mips "nomips16" Mips "micromips" Mips "nomicromips" "use-soft-float" "use-soft-float" "true" Mips "+mips16" ",+mips16" Mips "-mips16" ",-mips16" Mips "+micromips" ",+micromips" Mips "-micromips" ",-micromips" "+soft-float" ",+soft-float" Mips


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { TargetTransformInfo :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> unsigned SIRegisterInfo :: getRegPressureSetLimit ( const MachineFunction & MF , unsigned Idx ) const { const AMDGPUSubtarget & STI = MF . getSubtarget < AMDGPUSubtarget > ( ) ; unsigned SGPRLimit = getNumSGPRsAllowed ( STI . getGeneration ( ) , STI . getMaxWavesPerCU ( ) ) ; unsigned VGPRLimit = getNumVGPRsAllowed ( STI . getMaxWavesPerCU ( ) ) ; unsigned VSLimit = SGPRLimit + VGPRLimit ; if ( SGPRPressureSets . test ( Idx ) && VGPRPressureSets . test ( Idx ) ) { return VSLimit ; } if ( SGPRPressureSets . test ( Idx ) ) return SGPRLimit ; return VGPRLimit ; } </s>

Get the register unit pressure limit for this dimension .


<s> bool GCNTTIImpl :: isInlineAsmSourceOfDivergence ( const CallInst * CI , ArrayRef < unsigned > Indices ) const { if ( Indices . size ( ) > 1 ) return true ; const DataLayout & DL = CI -> getModule ( ) -> getDataLayout ( ) ; const SIRegisterInfo * TRI = ST -> getRegisterInfo ( ) ; TargetLowering :: AsmOperandInfoVector TargetConstraints = TLI -> ParseConstraints ( DL , ST -> getRegisterInfo ( ) , * CI ) ; const int TargetOutputIdx = Indices . empty ( ) ? - 1 : Indices [ 0 ] ; int OutputIdx = 0 ; for ( auto & TC : TargetConstraints ) { if ( TC . Type != InlineAsm :: isOutput ) continue ; if ( TargetOutputIdx != - 1 && TargetOutputIdx != OutputIdx ++ ) continue ; TLI -> ComputeConstraintToUse ( TC , SDValue ( ) ) ; const TargetRegisterClass * RC = TLI -> getRegForInlineAsmConstraint ( TRI , TC . ConstraintCode , TC . ConstraintVT ) . second ; if ( ! RC || ! TRI -> isSGPRClass ( RC ) ) return true ; } return false ; } </s>

Analyze if the results of inline asm are divergent .


<s> size_t ARMToTHMStub :: size ( ) const { return m_Size ; } </s>

The number of name/type pairs is returned .


<s> unsigned getMask ( ) const { return Mask << Shift ; } </s>


<s>
SDValue
AMDGPUTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
Op
.
getNode
(
)
->
dump
(
)
;
assert
(
0
&&
"Custom lowering code for this"
"instruction is not implemented yet!"
)
;
break
;
case
ISD
::
SDIV
:
return
LowerSDIV
(
Op
,
DAG
)
;
case
ISD
::
SREM
:
return
LowerSREM
(
Op
,
DAG
)
;
case
ISD
::
SIGN_EXTEND_INREG
:
return
LowerSIGN_EXTEND_INREG
(
Op
,
DAG
)
;
case
ISD
::
BRCOND
:
return
LowerBRCOND
(
Op
,
DAG
)
;
case
ISD
::
CONCAT_VECTORS
:
return
LowerCONCAT_VECTORS
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_SUBVECTOR
:
return
LowerEXTRACT_SUBVECTOR
(
Op
,
DAG
)
;
case
ISD
::
FrameIndex
:
return
LowerFrameIndex
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
UDIVREM
:
return
LowerUDIVREM
(
Op
,
DAG
)
;
case
ISD
::
UINT_TO_FP
:
return
LowerUINT_TO_FP
(
Op
,
DAG
)
;
}
return
Op
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s>
StringRef
RISCVMCExpr
::
getVariantKindName
(
VariantKind
Kind
)
{
switch
(
Kind
)
{
default
:
llvm_unreachable
(
"Invalid ELF symbol kind"
)
;
case
VK_RISCV_LO
:
return
"lo"
;
case
VK_RISCV_HI
:
return
"hi"
;
case
VK_RISCV_PCREL_LO
:
return
"pcrel_lo"
;
case
VK_RISCV_PCREL_HI
:
return
"pcrel_hi"
;
case
VK_RISCV_GOT_HI
:
return
"got_pcrel_hi"
;
case
VK_RISCV_TPREL_LO
:
return
"tprel_lo"
;
case
VK_RISCV_TPREL_HI
:
return
"tprel_hi"
;
case
VK_RISCV_TPREL_ADD
:
return
"tprel_add"
;
case
VK_RISCV_TLS_GOT_HI
:
return
"tls_ie_pcrel_hi"
;
case
VK_RISCV_TLS_GD_HI
:
return
"tls_gd_pcrel_hi"
;
}
}
</s>

Convert the variant kind into an ELF-appropriate modifier ( e.g .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( ! skipFunction ( MF . getFunction ( ) ) ) { initialize ( MF ) ; checkingIllegalXADD ( ) ; } return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool SITargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty ) const { if ( AM . BaseGV ) return false ; if ( ! isUInt < 16 > ( AM . BaseOffs ) ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( AM . HasBaseReg && AM . BaseOffs ) return false ; break ; case 2 : if ( AM . HasBaseReg || AM . BaseOffs ) return false ; break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> size_t ARMToARMStub :: size ( ) const { return m_Size ; } </s>


<s> unsigned ARMTTI :: getIntImmCost ( const APInt & Imm , Type * Ty ) const { assert ( Ty -> isIntegerTy ( ) ) ; unsigned Bits = Ty -> getPrimitiveSizeInBits ( ) ; if ( Bits == 0 || Bits > 32 ) return 4 ; int32_t SImmVal = Imm . getSExtValue ( ) ; uint32_t ZImmVal = Imm . getZExtValue ( ) ; if ( ! ST -> isThumb ( ) ) { if ( ( SImmVal >= 0 && SImmVal < 65536 ) || ( ARM_AM :: getSOImmVal ( ZImmVal ) != - 1 ) || ( ARM_AM :: getSOImmVal ( ~ ZImmVal ) != - 1 ) ) return 1 ; return ST -> hasV6T2Ops ( ) ? 2 : 3 ; } else if ( ST -> isThumb2 ( ) ) { if ( ( SImmVal >= 0 && SImmVal < 65536 ) || ( ARM_AM :: getT2SOImmVal ( ZImmVal ) != - 1 ) || ( ARM_AM :: getT2SOImmVal ( ~ ZImmVal ) != - 1 ) ) return 1 ; return ST -> hasV6T2Ops ( ) ? 2 : 3 ; } else { if ( SImmVal >= 0 && SImmVal < 256 ) return 1 ; if ( ( ~ ZImmVal < 256 ) || ARM_AM :: isThumbImmShiftedVal ( ZImmVal ) ) return 2 ; return 3 ; } return 2 ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> void xstormy16_emit_cbranch ( enum rtx_code code , rtx loc ) { rtx op0 = xstormy16_compare_op0 ; rtx op1 = xstormy16_compare_op1 ; rtx condition_rtx , loc_ref , branch , cy_clobber ; rtvec vec ; enum machine_mode mode ; mode = GET_MODE ( op0 ) ; gcc_assert ( mode == HImode || mode == SImode ) ; if ( mode == SImode && ( code == GT || code == LE || code == GTU || code == LEU ) ) { int unsigned_p = ( code == GTU || code == LEU ) ; int gt_p = ( code == GT || code == GTU ) ; rtx lab = NULL_RTX ; if ( gt_p ) lab = gen_label_rtx ( ) ; xstormy16_emit_cbranch ( unsigned_p ? LTU : LT , gt_p ? lab : loc ) ; xstormy16_emit_cbranch ( gt_p ? NE : EQ , loc ) ; if ( gt_p ) emit_label ( lab ) ; return ; } else if ( mode == SImode && ( code == NE || code == EQ ) && op1 != const0_rtx ) { rtx lab = NULL_RTX ; int num_words = GET_MODE_BITSIZE ( mode ) / BITS_PER_WORD ; int i ; if ( code == EQ ) lab = gen_label_rtx ( ) ; for ( i = 0 ; i < num_words - 1 ; i ++ ) { xstormy16_compare_op0 = simplify_gen_subreg ( word_mode , op0 , mode , i * UNITS_PER_WORD ) ; xstormy16_compare_op1 = simplify_gen_subreg ( word_mode , op1 , mode , i * UNITS_PER_WORD ) ; xstormy16_emit_cbranch ( NE , code == EQ ? lab : loc ) ; } xstormy16_compare_op0 = simplify_gen_subreg ( word_mode , op0 , mode , i * UNITS_PER_WORD ) ; xstormy16_compare_op1 = simplify_gen_subreg ( word_mode , op1 , mode , i * UNITS_PER_WORD ) ; xstormy16_emit_cbranch ( code , loc ) ; if ( code == EQ ) emit_label ( lab ) ; return ; } if ( mode != HImode ) { rtx tmp ; tmp = gen_reg_rtx ( mode ) ; emit_move_insn ( tmp , op0 ) ; op0 = tmp ; } condition_rtx = gen_rtx_fmt_ee ( code , mode , op0 , op1 ) ; loc_ref = gen_rtx_LABEL_REF ( VOIDmode , loc ) ; branch = gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , condition_rtx , loc_ref , pc_rtx ) ) ; cy_clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_SCRATCH ( BImode ) ) ; if ( mode == HImode ) vec = gen_rtvec ( 2 , branch , cy_clobber ) ; else if ( code == NE || code == EQ ) vec = gen_rtvec ( 2 , branch , gen_rtx_CLOBBER ( VOIDmode , op0 ) ) ; else { rtx sub ; sub = gen_rtx_SET ( VOIDmode , op0 , gen_rtx_MINUS ( SImode , op0 , op1 ) ) ; sub = gen_rtx_CLOBBER ( SImode , op0 ) ; vec = gen_rtvec ( 3 , branch , sub , cy_clobber ) ; } emit_jump_insn ( gen_rtx_PARALLEL ( VOIDmode , vec ) ) ; } </s>

Emit a branch of kind CODE to location LOC .


<s> bool isFPImm ( ) const { return Kind == k_FPImm ; } </s>

isFPImm - Tests if this is a MO_FPImmediate operand .


<s> static tree arm_gimplify_va_arg_expr ( tree valist , tree type , gimple_seq * pre_p , gimple_seq * post_p ) { valist = arm_extract_valist_ptr ( valist ) ; return std_gimplify_va_arg_expr ( valist , type , pre_p , post_p ) ; } </s>


<s> const AVRMCExpr * AVRMCExpr :: create ( VariantKind Kind , const MCExpr * Expr , bool Negated , MCContext & Ctx ) { return new ( Ctx ) AVRMCExpr ( Kind , Expr , Negated ) ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"Nyuzi Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"Can only insert epilog into returning blocks"


<s>
DecodeStatus
P2Disassembler
::
getInstruction
(
MCInst
&
Instr
,
uint64_t
&
Size
,
ArrayRef
<
uint8_t
>
Bytes
,
uint64_t
Address
,
raw_ostream
&
CStream
)
const
{
uint32_t
Insn
;
DecodeStatus
Result
;
Result
=
readInstruction
(
Bytes
,
Address
,
Size
,
Insn
)
;
if
(
Result
==
MCDisassembler
::
Fail
)
return
MCDisassembler
::
Fail
;
unsigned
cond
=
fieldFromInstruction
(
Insn
,
28
,
4
)
;
Instr
.
setFlags
(
(
Instr
.
getFlags
(
)
&
0xf
)
|
cond
)
;
LLVM_DEBUG
(
errs
(
)
<<
"get instruction: "
<<
Insn
<<
"\n"
)
;
Result
=
decodeInstruction
(
DecoderTableP232
,
Instr
,
Insn
,
Address
,
this
,
STI
)
;
if
(
Result
!=
MCDisassembler
::
Fail
)
{
return
Result
;
}
return
MCDisassembler
::
Fail
;
}
</s>

Returns the disassembly of a single instruction .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < X86Subtarget > ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; return true ; } </s>


<s> bool isConditionalBranch ( const MCInst & Inst ) const override { if ( Inst . getOpcode ( ) == AArch64 :: Bcc && Inst . getOperand ( 0 ) . getImm ( ) == A64CC :: AL ) return false ; return MCInstrAnalysis :: isConditionalBranch ( Inst ) ; } </s>

Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block .


<s> unsigned size ( ) const { return Insts . size ( ) ; } </s>


<s> CountValueType getType ( ) const { return Kind ; } </s>

Overload to return most specific vector type .


<s> static void nvptx_goacc_reduction_setup ( gcall * call , offload_attrs * oa ) { gimple_stmt_iterator gsi = gsi_for_stmt ( call ) ; tree lhs = gimple_call_lhs ( call ) ; tree var = gimple_call_arg ( call , 2 ) ; int level = TREE_INT_CST_LOW ( gimple_call_arg ( call , 3 ) ) ; gimple_seq seq = NULL ; push_gimplify_context ( true ) ; if ( level != GOMP_DIM_GANG ) { tree ref_to_res = gimple_call_arg ( call , 1 ) ; if ( ! integer_zerop ( ref_to_res ) ) var = build_simple_mem_ref ( ref_to_res ) ; } if ( level == GOMP_DIM_WORKER || ( level == GOMP_DIM_VECTOR && oa -> vector_length > PTX_WARP_SIZE ) ) { tree offset = gimple_call_arg ( call , 5 ) ; tree call = nvptx_get_shared_red_addr ( TREE_TYPE ( var ) , offset , level == GOMP_DIM_VECTOR ) ; tree ptr = make_ssa_name ( TREE_TYPE ( call ) ) ; gimplify_assign ( ptr , call , & seq ) ; tree ref = build_simple_mem_ref ( ptr ) ; TREE_THIS_VOLATILE ( ref ) = 1 ; gimplify_assign ( ref , var , & seq ) ; } if ( lhs ) gimplify_assign ( lhs , var , & seq ) ; pop_gimplify_context ( NULL ) ; gsi_replace_with_seq ( & gsi , seq , true ) ; } </s>

NVPTX implementation of GOACC_REDUCTION_SETUP .


<s> static bool mips_valid_lo_sum_p ( enum mips_symbol_type symbol_type , machine_mode mode ) { if ( mips_symbol_insns ( symbol_type , mode ) == 0 ) return false ; if ( mips_lo_relocs [ symbol_type ] == NULL ) return false ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && GET_MODE_BITSIZE ( mode ) > GET_MODE_ALIGNMENT ( mode ) ) return false ; return true ; } </s>

Return true if a LO_SUM can address a value of mode MODE when the LO_SUM symbol has type SYMBOL_TYPE .


<s>
static
void
rs6000_elf_asm_out_constructor
(
rtx
symbol
,
int
priority
)
{
const
char
*
section
=
".ctors"
;
char
buf
[
16
]
;
if
(
priority
!=
DEFAULT_INIT_PRIORITY
)
{
sprintf
(
buf
,
".ctors.%.5u"
,
MAX_INIT_PRIORITY
priority
)
;
section
=
buf
;
}
switch_to_section
(
get_section
(
section
,
SECTION_WRITE
,
)
)
;
assemble_align
(
POINTER_SIZE
)
;
if
(
TARGET_RELOCATABLE
)
{
fputs
(
"\t.long ("
,
asm_out_file
)
;
output_addr_const
(
asm_out_file
,
symbol
)
;
fputs
(
")@fixup\n"
,
asm_out_file
)
;
}
else
assemble_integer
(
symbol
,
POINTER_SIZE
/
BITS_PER_UNIT
,
POINTER_SIZE
,
1
)
;
}
</s>


<s> static hash_set < set_info * > get_all_sets ( set_info * set , bool real_p , bool phi_p , bool param_p ) { if ( real_p && phi_p && param_p ) return get_all_sets ( safe_dyn_cast < phi_info * > ( set ) , REAL_SET | PHI_SET | BB_HEAD_SET | BB_END_SET ) ; else if ( real_p && param_p ) return get_all_sets ( safe_dyn_cast < phi_info * > ( set ) , REAL_SET | BB_HEAD_SET | BB_END_SET ) ; else if ( real_p ) return get_all_sets ( safe_dyn_cast < phi_info * > ( set ) , REAL_SET ) ; return hash_set < set_info * > ( ) ; } </s>

Recursively find all define instructions . The kind of instruction is specified by the DEF_TYPE .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"MIPS16 Hard Float Pass"
;
}
</s>


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { const X86TargetMachine * TM = static_cast < const X86TargetMachine * > ( & MF . getTarget ( ) ) ; const X86RegisterInfo * X86RI = TM -> getRegisterInfo ( ) ; MachineRegisterInfo & RI = MF . getRegInfo ( ) ; X86MachineFunctionInfo * FuncInfo = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned StackAlignment = X86RI -> getStackAlignment ( ) ; for ( unsigned RegNum = TargetRegisterInfo :: FirstVirtualRegister ; RegNum < RI . getLastVirtReg ( ) ; ++ RegNum ) if ( RI . getRegClass ( RegNum ) -> getAlignment ( ) > StackAlignment ) { FuncInfo -> setReserveFP ( true ) ; return true ; } return false ; } </s>


<s> bool HexagonMCInstrInfo :: isExtended ( MCInstrInfo const & MCII , MCInst const & MCI ) { uint64_t const F = HexagonMCInstrInfo :: getDesc ( MCII , MCI ) . TSFlags ; return ( F >> HexagonII :: ExtendedPos ) & HexagonII :: ExtendedMask ; } </s>

Test if the given EVT is extended ( as opposed to being simple ) .

Hexagon Hexagon Hexagon HexagonII::ExtendedPos HexagonII::ExtendedMask


<s> static hashval_t unspec_prof_hash ( const void * x ) { const_rtx u = ( const_rtx ) x ; const_rtx s1 = XVECEXP ( u , 0 , 1 ) ; return ( htab_hash_string ( XSTR ( XVECEXP ( u , 0 , 0 ) , 0 ) ) ^ ( s1 -> code == SYMBOL_REF ? htab_hash_string ( XSTR ( s1 , 0 ) ) : 0 ) ) ; } </s>

Hash function for UNSPEC_PROF htab . Use both the caller 's name and the callee 's name ( if known ) .


<s> const SICSubtarget * getSubtargetImpl ( ) const { return & DefaultSubtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .