<s> void ix86_register_pragmas ( void ) { targetm . target_option . pragma_parse = ix86_pragma_target_parse ; c_register_addr_space ( "__seg_fs" , ADDR_SPACE_SEG_FS ) ; c_register_addr_space ( "__seg_gs" , ADDR_SPACE_SEG_GS ) ; REGISTER_SUBTARGET_PRAGMAS ( ) ; } </s>

Register target pragmas . We need to add the hook for parsing # pragma GCC option here rather than in i386.cc since it will pull in various preprocessor functions , and those are not present in languages like fortran without a preprocessor .


<s> static int gen_v9_scc ( rtx dest , enum rtx_code compare_code , rtx x , rtx y ) { if ( ! TARGET_ARCH64 && ( GET_MODE ( x ) == DImode || GET_MODE ( dest ) == DImode ) ) return 0 ; if ( TARGET_ARCH64 && GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_INT && y == const0_rtx && v9_regcmp_p ( compare_code ) ) { rtx op0 = x ; rtx temp ; if ( compare_code == NE && GET_MODE ( dest ) == DImode && rtx_equal_p ( op0 , dest ) ) { emit_insn ( gen_rtx_SET ( VOIDmode , dest , gen_rtx_IF_THEN_ELSE ( DImode , gen_rtx_fmt_ee ( compare_code , DImode , op0 , const0_rtx ) , const1_rtx , dest ) ) ) ; return 1 ; } if ( reg_overlap_mentioned_p ( dest , op0 ) ) { op0 = gen_reg_rtx ( GET_MODE ( x ) ) ; emit_move_insn ( op0 , x ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , dest , const0_rtx ) ) ; if ( GET_MODE ( op0 ) != DImode ) { temp = gen_reg_rtx ( DImode ) ; convert_move ( temp , op0 , 0 ) ; } else temp = op0 ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , gen_rtx_IF_THEN_ELSE ( GET_MODE ( dest ) , gen_rtx_fmt_ee ( compare_code , DImode , temp , const0_rtx ) , const1_rtx , dest ) ) ) ; return 1 ; } else { x = gen_compare_reg_1 ( compare_code , x , y ) ; y = const0_rtx ; gcc_assert ( GET_MODE ( x ) != CC_NOOVmode && GET_MODE ( x ) != CCX_NOOVmode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , const0_rtx ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , gen_rtx_IF_THEN_ELSE ( GET_MODE ( dest ) , gen_rtx_fmt_ee ( compare_code , GET_MODE ( x ) , x , y ) , const1_rtx , dest ) ) ) ; return 1 ; } } </s>

This function is used for v9 only . CODE is the code for an Scc 's comparison . OPERANDS [ 0 ] is the target of the Scc insn . OPERANDS [ 1 ] is the value we compare against const0_rtx ( which has n't been generated yet ) . This function is needed to turn ( set ( reg : SI 110 ) ( gt ( reg : CCX 100 % icc ) ( const_int 0 ) ) ) into ( set ( reg : SI 110 ) ( gt : DI ( reg : CCX 100 % icc ) ( const_int 0 ) ) ) IE : The instruction recognizer needs to see the mode of the comparison to find the right instruction . We could use `` gt : DI '' right in the define_expand , but leaving it out allows us to handle DI , SI , etc . We refer to the global sparc compare operands sparc_compare_op0 and sparc_compare_op1 .


<s> bool ARM64AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( ( Count & 3 ) != 0 ) { for ( uint64_t i = 0 , e = ( Count & 3 ) ; i != e ; ++ i ) OW -> Write8 ( 0 ) ; } Count /= 4 ; for ( uint64_t i = 0 ; i != Count ; ++ i ) OW -> Write32 ( 0xd503201f ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s>
bool
VLIWResourceModel
::
reserveResources
(
SUnit
*
SU
)
{
bool
startNewCycle
=
false
;
if
(
!
SU
)
{
ResourcesModel
->
clearResources
(
)
;
Packet
.
clear
(
)
;
TotalPackets
++
;
return
false
;
}
if
(
!
isResourceAvailable
(
SU
)
)
{
ResourcesModel
->
clearResources
(
)
;
Packet
.
clear
(
)
;
TotalPackets
++
;
startNewCycle
=
true
;
}
switch
(
SU
->
getInstr
(
)
->
getOpcode
(
)
)
{
default
:
ResourcesModel
->
reserveResources
(
SU
->
getInstr
(
)
)
;
break
;
case
TargetOpcode
::
EXTRACT_SUBREG
:
case
TargetOpcode
::
INSERT_SUBREG
:
case
TargetOpcode
::
SUBREG_TO_REG
:
case
TargetOpcode
::
REG_SEQUENCE
:
case
TargetOpcode
::
IMPLICIT_DEF
:
case
TargetOpcode
::
KILL
:
case
TargetOpcode
::
PROLOG_LABEL
:
case
TargetOpcode
::
EH_LABEL
:
case
TargetOpcode
::
COPY
:
case
TargetOpcode
::
INLINEASM
:
break
;
}
Packet
.
push_back
(
SU
)
;
DEBUG
(
dbgs
(
)
<<
"Packet["
<<
TotalPackets
<<
"]:\n"
)
;
for
(
unsigned
i
=
0
,
e
=
Packet
.
size
(
)
;
i
!=
e
;
++
i
)
{
DEBUG
(
dbgs
(
)
<<
"\t["
<<
i
<<
"] SU("
)
;
DEBUG
(
dbgs
(
)
<<
Packet
[
i
]
->
NodeNum
<<
")\t"
)
;
DEBUG
(
Packet
[
i
]
->
getInstr
(
)
->
dump
(
)
)
;
}
if
(
Packet
.
size
(
)
>=
InstrItins
->
SchedModel
->
IssueWidth
)
{
ResourcesModel
->
clearResources
(
)
;
Packet
.
clear
(
)
;
TotalPackets
++
;
startNewCycle
=
true
;
}
return
startNewCycle
;
}
</s>


"variadic functions must use the base AAPCS variant"

Get the PCS variant to use for this call . TYPE is the function 's type specification , DECL is the specific declartion . DECL may be null if the call could be indirect or if this is a library call .


<s> void HexagonMCELFStreamer :: EmitInstruction ( const MCInst & MCB , const MCSubtargetInfo & STI , bool ) { assert ( MCB . getOpcode ( ) == Hexagon :: BUNDLE ) ; assert ( HexagonMCInstrInfo :: bundleSize ( MCB ) <= HEXAGON_PACKET_SIZE ) ; assert ( HexagonMCInstrInfo :: bundleSize ( MCB ) > 0 ) ; for ( auto const & I : HexagonMCInstrInfo :: bundleInstructions ( MCB ) ) { MCInst * MCI = const_cast < MCInst * > ( I . getInst ( ) ) ; EmitSymbol ( * MCI ) ; } MCObjectStreamer :: EmitInstruction ( MCB , STI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .

Hexagon Hexagon Hexagon::BUNDLE Hexagon Hexagon 0 Hexagon


<s> void function_builder :: allocate_argument_types ( const function_instance & instance , vec < tree > & argument_types ) const { for ( unsigned int i = 0 ; instance . op_info -> args [ i ] . base_type != NUM_BASE_TYPES ; ++ i ) argument_types . quick_push ( instance . op_info -> args [ i ] . get_tree_type ( instance . type . index ) ) ; } </s>


"AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "


<s> void HexagonDAGToDAGISel :: PreprocessISelDAG ( ) { SelectionDAG & DAG = * CurDAG ; std :: vector < SDNode * > Nodes ; for ( SDNode & Node : DAG . allnodes ( ) ) Nodes . push_back ( & Node ) ; for ( auto I : Nodes ) { if ( I -> getOpcode ( ) != ISD :: OR ) continue ; auto IsZero = [ ] ( const SDValue & V ) -> bool { if ( ConstantSDNode * SC = dyn_cast < ConstantSDNode > ( V . getNode ( ) ) ) return SC -> isNullValue ( ) ; return false ; } ; auto IsSelect0 = [ IsZero ] ( const SDValue & Op ) -> bool { if ( Op . getOpcode ( ) != ISD :: SELECT ) return false ; return IsZero ( Op . getOperand ( 1 ) ) || IsZero ( Op . getOperand ( 2 ) ) ; } ; SDValue N0 = I -> getOperand ( 0 ) , N1 = I -> getOperand ( 1 ) ; EVT VT = I -> getValueType ( 0 ) ; bool SelN0 = IsSelect0 ( N0 ) ; SDValue SOp = SelN0 ? N0 : N1 ; SDValue VOp = SelN0 ? N1 : N0 ; if ( SOp . getOpcode ( ) == ISD :: SELECT && SOp . getNode ( ) -> hasOneUse ( ) ) { SDValue SC = SOp . getOperand ( 0 ) ; SDValue SX = SOp . getOperand ( 1 ) ; SDValue SY = SOp . getOperand ( 2 ) ; SDLoc DLS = SOp ; if ( IsZero ( SY ) ) { SDValue NewOr = DAG . getNode ( ISD :: OR , DLS , VT , SX , VOp ) ; SDValue NewSel = DAG . getNode ( ISD :: SELECT , DLS , VT , SC , NewOr , VOp ) ; DAG . ReplaceAllUsesWith ( I , NewSel . getNode ( ) ) ; } else if ( IsZero ( SX ) ) { SDValue NewOr = DAG . getNode ( ISD :: OR , DLS , VT , SY , VOp ) ; SDValue NewSel = DAG . getNode ( ISD :: SELECT , DLS , VT , SC , VOp , NewOr ) ; DAG . ReplaceAllUsesWith ( I , NewSel . getNode ( ) ) ; } } } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> bool NyuziTTIImpl :: hasBranchDivergence ( ) const { return false ; } </s>

Return true if branch divergence exists .


<s> static int fp_regs_to_save ( void ) { int i , n = 0 ; if ( ! TARGET_AM33_2 ) return 0 ; for ( i = FIRST_FP_REGNUM ; i <= LAST_FP_REGNUM ; ++ i ) if ( df_regs_ever_live_p ( i ) && ! call_really_used_regs [ i ] ) ++ n ; return n ; } </s>

Count the number of FP registers that have to be saved .


Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU R600 AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU


<s> bool AMDGPUInstrInfo :: unfoldMemoryOperand ( SelectionDAG & DAG , SDNode * N , SmallVectorImpl < SDNode * > & NewNodes ) const { return false ; } </s>

unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a store into two or more instruction .


<s> void ARCompactInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; BuildMI ( MBB , MI , DL , get ( ARC :: LDrli ) ) . addReg ( DestReg ) . addFrameIndex ( FrameIdx ) . addImm ( 0 ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s>
bool
RISCVAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
;
MatchResult
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MatchingInlineAsm
)
;
switch
(
MatchResult
)
{
default
:
break
;
case
Match_Success
:
{
if
(
processInstruction
(
Inst
,
IDLoc
,
Instructions
)
)
return
true
;
for
(
unsigned
i
=
0
;
i
<
Instructions
.
size
(
)
;
i
++
)
{
Out
.
EmitInstruction
(
Inst
,
STI
)
;
}
return
false
;
}
Inst
.
setLoc
(
IDLoc
)
;
Out
.
EmitInstruction
(
Inst
,
STI
)
;
return
false
;
}
case
Match_MissingFeature
:
{
assert
(
ErrorInfo
&&
"Unknown missing feature!"
)
;
std
::
string
Msg
=
"instruction requires:"
;
unsigned
Mask
=
1
;
for
(
unsigned
I
=
0
;
I
<
sizeof
(
ErrorInfo
)
*
8
1
;
++
I
)
{
if
(
ErrorInfo
&
Mask
)
{
Msg
+=
" "
;
Msg
+=
getSubtargetFeatureName
(
ErrorInfo
&
Mask
)
;
}
Mask
<<=
1
;
}
return
Error
(
IDLoc
,
Msg
)
;
}
case
Match_InvalidOperand
:
{
SMLoc
ErrorLoc
=
IDLoc
;
if
(
ErrorInfo
!=
~
0U
)
{
if
(
ErrorInfo
>=
Operands
.
size
(
)
)
return
Error
(
IDLoc
,
"too few operands for instruction"
)
;
ErrorLoc
=
(
(
RISCVOperand
&
)
*
Operands
[
ErrorInfo
]
)
.
getStartLoc
(
)
;
if
(
ErrorLoc
==
SMLoc
(
)
)
ErrorLoc
=
IDLoc
;
}
return
Error
(
ErrorLoc
,
"invalid operand for instruction"
)
;
}
case
Match_MnemonicFail
:
return
Error
(
IDLoc
,
"invalid instruction"
)
;
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> bool csky_tls_referenced_p ( rtx x ) { if ( ! TARGET_TLS ) return false ; subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , x , ALL ) { const_rtx x = * iter ; if ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) != 0 ) return true ; if ( GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNSPEC_TLS ) iter . skip_subrtxes ( ) ; } return false ; } </s>

Return TRUE if X contains any references to TLS symbols .


<s> static bool ia64_legitimate_address_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x , bool strict ) { if ( ia64_legitimate_address_reg ( x , strict ) ) return true ; else if ( ( GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == POST_DEC ) && ia64_legitimate_address_reg ( XEXP ( x , 0 ) , strict ) && XEXP ( x , 0 ) != arg_pointer_rtx ) return true ; else if ( GET_CODE ( x ) == POST_MODIFY && ia64_legitimate_address_reg ( XEXP ( x , 0 ) , strict ) && XEXP ( x , 0 ) != arg_pointer_rtx && ia64_legitimate_address_disp ( XEXP ( x , 0 ) , XEXP ( x , 1 ) , strict ) ) return true ; else return false ; } </s>


<s>
void
XCoreFrameLowering
::
emitEpilogue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
getLastNonDebugInstr
(
)
;
const
XCoreInstrInfo
&
TII
=
*
static_cast
<
const
XCoreInstrInfo
*
>
(
MF
.
getTarget
(
)
.
getInstrInfo
(
)
)
;
XCoreFunctionInfo
*
XFI
=
MF
.
getInfo
<
XCoreFunctionInfo
>
(
)
;
DebugLoc
dl
=
MBBI
->
getDebugLoc
(
)
;
bool
FP
=
hasFP
(
MF
)
;
if
(
FP
)
{
unsigned
FramePtr
=
XCore
::
R10
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
XCore
::
SETSP_1r
)
)
.
addReg
(
FramePtr
)
;
}
int
FrameSize
=
MFI
->
getStackSize
(
)
;
assert
(
FrameSize
%
4
==
0
&&
"Misaligned frame size"
)
;
FrameSize
/=
4
;
bool
isU6
=
isImmU6
(
FrameSize
)
;
if
(
!
isU6
&&
!
isImmU16
(
FrameSize
)
)
{
report_fatal_error
(
"emitEpilogue Frame size too big: "
+
Twine
(
FrameSize
)
)
;
}
if
(
FP
)
{
int
FPSpillOffset
=
MFI
->
getObjectOffset
(
XFI
->
getFPSpillSlot
(
)
)
;
FPSpillOffset
+=
FrameSize
*
4
;
loadFromStack
(
MBB
,
MBBI
,
XCore
::
R10
,
FPSpillOffset
,
dl
,
TII
)
;
}
bool
restoreLR
=
XFI
->
getUsesLR
(
)
;
if
(
restoreLR
&&
(
FrameSize
==
0
||
MFI
->
getObjectOffset
(
XFI
->
getLRSpillSlot
(
)
)
!=
0
)
)
{
int
LRSpillOffset
=
MFI
->
getObjectOffset
(
XFI
->
getLRSpillSlot
(
)
)
;
LRSpillOffset
+=
FrameSize
*
4
;
loadFromStack
(
MBB
,
MBBI
,
XCore
::
LR
,
LRSpillOffset
,
dl
,
TII
)
;
restoreLR
=
false
;
}
if
(
FrameSize
)
{
if
(
restoreLR
)
{
assert
(
MFI
->
getObjectOffset
(
XFI
->
getLRSpillSlot
(
)
)
==
0
)
;
assert
(
MBBI
->
getOpcode
(
)
==
XCore
::
RETSP_u6
||
MBBI
->
getOpcode
(
)
==
XCore
::
RETSP_lu6
)
;
int
Opcode
=
(
isU6
)
XCore
::
RETSP_u6
:
XCore
::
RETSP_lu6
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Opcode
)
)
.
addImm
(
FrameSize
)
;
for
(
unsigned
i
=
3
,
e
=
MBBI
->
getNumOperands
(
)
;
i
<
e
;
++
i
)
MIB
->
addOperand
(
MBBI
->
getOperand
(
i
)
)
;
MBB
.
erase
(
MBBI
)
;
}
else
{
int
Opcode
=
(
isU6
)
XCore
::
LDAWSP_ru6
:
XCore
::
LDAWSP_lru6
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Opcode
)
,
XCore
::
SP
)
.
addImm
(
FrameSize
)
;
}
}
}
</s>


<s>
void
CSKYRegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected non-zero SPAdj value"
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .

CSKY
CSKY
0
"Unexpected non-zero SPAdj value"


<s>
ScheduleHazardRecognizer
::
HazardType
HexagonHazardRecognizer
::
getHazardType
(
SUnit
*
SU
,
int
stalls
)
{
MachineInstr
*
MI
=
SU
->
getInstr
(
)
;
if
(
!
MI
||
TII
->
isZeroCost
(
MI
->
getOpcode
(
)
)
)
return
NoHazard
;
if
(
!
Resources
->
canReserveResources
(
*
MI
)
)
{
DEBUG
(
dbgs
(
)
<<
"*** Hazard in cycle "
<<
PacketNum
<<
", "
<<
*
MI
)
;
HazardType
RetVal
=
Hazard
;
if
(
TII
->
mayBeNewStore
(
*
MI
)
)
{
MachineOperand
&
MO
=
MI
->
getOperand
(
MI
->
getNumOperands
(
)
1
)
;
if
(
!
MO
.
isReg
(
)
||
RegDefs
.
count
(
MO
.
getReg
(
)
)
==
0
)
return
Hazard
;
MachineFunction
*
MF
=
MI
->
getParent
(
)
->
getParent
(
)
;
MachineInstr
*
NewMI
=
MF
->
CreateMachineInstr
(
TII
->
get
(
TII
->
getDotNewOp
(
*
MI
)
)
,
MI
->
getDebugLoc
(
)
)
;
if
(
Resources
->
canReserveResources
(
*
NewMI
)
)
RetVal
=
NoHazard
;
DEBUG
(
dbgs
(
)
<<
"*** Try .new version? "
<<
(
RetVal
==
NoHazard
)
<<
"\n"
)
;
MF
->
DeleteMachineInstr
(
NewMI
)
;
}
return
RetVal
;
}
if
(
SU
==
UsesDotCur
&&
DotCurPNum
!=
(
int
)
PacketNum
)
{
DEBUG
(
dbgs
(
)
<<
"*** .cur Hazard in cycle "
<<
PacketNum
<<
", "
<<
*
MI
)
;
return
Hazard
;
}
return
NoHazard
;
}
</s>

getHazardType - Return the hazard type of emitting this node .

Hexagon
Hexagon
"*** Hazard in cycle "
", "
1
0
"*** Try .new version? "
"\n"
"*** .cur Hazard in cycle "
", "


<s> static unsigned char ix86_class_max_nregs ( reg_class_t rclass , machine_mode mode ) { if ( MAYBE_INTEGER_CLASS_P ( rclass ) ) { if ( mode == XFmode ) return ( TARGET_64BIT ? 2 : 3 ) ; else if ( mode == XCmode ) return ( TARGET_64BIT ? 4 : 6 ) ; else return CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ; } else { if ( COMPLEX_MODE_P ( mode ) ) return 2 ; else return 1 ; } } </s>

Implement the TARGET_CLASS_MAX_NREGS hook . On the 80386 , this is the size of MODE in words , except in the FP regs , where a single reg is always enough .


"RegScavenger required for long branching"

"new block should be inserted for expanding unconditional branch"

"Branch offsets outside of the signed 32-bit range not supported"

Insert an unconditional indirect branch at the end of MBB to NewDestBB .


<s> unsigned X86InstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { if ( isFrameLoadOpcode ( MI . getOpcode ( ) ) ) { unsigned Reg ; if ( ( Reg = isLoadFromStackSlot ( MI , FrameIndex ) ) ) return Reg ; const MachineMemOperand * Dummy ; return hasLoadFromStackSlot ( MI , Dummy , FrameIndex ) ; } return 0 ; } </s>

isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s> void mips_final_prescan_insn ( rtx_insn * insn , rtx * opvec , int noperands ) { if ( INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == UNSPEC_VOLATILE && XINT ( PATTERN ( insn ) , 1 ) == UNSPEC_CONSTTABLE ) mips_set_text_contents_type ( asm_out_file , "__pool_" , INTVAL ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) ) , FALSE ) ; if ( mips_need_noat_wrapper_p ( insn , opvec , noperands ) ) mips_push_asm_switch ( & mips_noat ) ; } </s>


<s> void GCNPassConfig :: addPreEmitPass ( ) { addPass ( & PostRAHazardRecognizerID ) ; addPass ( createSIInsertWaitsPass ( ) ) ; addPass ( createSIShrinkInstructionsPass ( ) ) ; addPass ( & SIInsertSkipsPassID ) ; addPass ( createSIDebuggerInsertNopsPass ( ) ) ; addPass ( & BranchRelaxationPassID ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> virtual const TargetRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool MOSInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { MachineIRBuilder Builder ( MI ) ; bool Changed = true ; switch ( MI . getOpcode ( ) ) { default : Changed = false ; break ; case MOS :: INC : case MOS :: DEC : expandIncDec ( Builder ) ; break ; case MOS :: LDAbsIdx : expandLDIdx ( Builder ) ; break ; case MOS :: LDImm1 : expandLDImm1 ( Builder ) ; break ; case MOS :: LDImm16 : expandLDImm16 ( Builder ) ; break ; case MOS :: LDImm16Remat : expandLDImm16Remat ( Builder ) ; break ; case MOS :: LDZ : expandLDZ ( Builder ) ; break ; case MOS :: CMPNZImm : case MOS :: CMPNZImag8 : case MOS :: CMPNZAbs : case MOS :: CMPNZAbsIdx : case MOS :: CMPNZIndirIdx : case MOS :: SBCNZImm : case MOS :: SBCNZImag8 : case MOS :: SBCNZAbs : case MOS :: SBCNZAbsIdx : case MOS :: SBCNZIndirIdx : expandNZ ( Builder ) ; break ; case MOS :: CMPTermImm : case MOS :: CMPTermImag8 : case MOS :: CMPTermAbs : case MOS :: CMPTermIndir : case MOS :: CMPTermIdx : expandCMPTerm ( Builder ) ; break ; case MOS :: GBR : expandGBR ( Builder ) ; break ; } return Changed ; } </s>

This function is called for all pseudo instructions that remain after register allocation .

MOS MOS MOS::INC MOS::DEC MOS::LDAbsIdx MOS::LDImm1 MOS::LDImm16 MOS::LDImm16Remat MOS::LDZ MOS::CMPNZImm MOS::CMPNZImag8 MOS::CMPNZAbs MOS::CMPNZAbsIdx MOS::CMPNZIndirIdx MOS::SBCNZImm MOS::SBCNZImag8 MOS::SBCNZAbs MOS::SBCNZAbsIdx MOS::SBCNZIndirIdx MOS::CMPTermImm MOS::CMPTermImag8 MOS::CMPTermAbs MOS::CMPTermIndir MOS::CMPTermIdx MOS::GBR


<s> void SITargetLowering :: AdjustInstrPostInstrSelection ( MachineInstr * MI , SDNode * Node ) const { const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; if ( TII -> isVOP3 ( MI -> getOpcode ( ) ) ) { TII -> legalizeOperandsVOP3 ( MRI , MI ) ; return ; } if ( TII -> isMIMG ( * MI ) ) { unsigned VReg = MI -> getOperand ( 0 ) . getReg ( ) ; unsigned DmaskIdx = MI -> getNumOperands ( ) == 12 ? 3 : 4 ; unsigned Writemask = MI -> getOperand ( DmaskIdx ) . getImm ( ) ; unsigned BitsSet = 0 ; for ( unsigned i = 0 ; i < 4 ; ++ i ) BitsSet += Writemask & ( 1 << i ) ? 1 : 0 ; const TargetRegisterClass * RC ; switch ( BitsSet ) { default : return ; case 1 : RC = & AMDGPU :: VGPR_32RegClass ; break ; case 2 : RC = & AMDGPU :: VReg_64RegClass ; break ; case 3 : RC = & AMDGPU :: VReg_96RegClass ; break ; } unsigned NewOpcode = TII -> getMaskedMIMGOp ( MI -> getOpcode ( ) , BitsSet ) ; MI -> setDesc ( TII -> get ( NewOpcode ) ) ; MRI . setRegClass ( VReg , RC ) ; return ; } int NoRetAtomicOp = AMDGPU :: getAtomicNoRetOp ( MI -> getOpcode ( ) ) ; if ( NoRetAtomicOp != - 1 ) { if ( ! Node -> hasAnyUseOfValue ( 0 ) ) { MI -> setDesc ( TII -> get ( NoRetAtomicOp ) ) ; MI -> RemoveOperand ( 0 ) ; } return ; } } </s>

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


<s> static rtx sparc_struct_value_rtx ( tree fndecl , int incoming ) { if ( TARGET_ARCH64 ) return 0 ; else { rtx mem ; if ( incoming ) mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , frame_pointer_rtx , STRUCT_VALUE_OFFSET ) ) ; else mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , STRUCT_VALUE_OFFSET ) ) ; if ( incoming == 2 && sparc_std_struct_return && TYPE_SIZE_UNIT ( TREE_TYPE ( fndecl ) ) && TREE_CODE ( TYPE_SIZE_UNIT ( TREE_TYPE ( fndecl ) ) ) == INTEGER_CST ) { rtx ret_reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; rtx scratch = gen_reg_rtx ( SImode ) ; rtx_code_label * endlab = gen_label_rtx ( ) ; tree size = TYPE_SIZE_UNIT ( TREE_TYPE ( fndecl ) ) ; rtx size_rtx = GEN_INT ( TREE_INT_CST_LOW ( size ) & 0xfff ) ; rtx temp_val = assign_stack_local ( Pmode , TREE_INT_CST_LOW ( size ) , 0 ) ; emit_move_insn ( scratch , gen_rtx_MEM ( SImode , plus_constant ( Pmode , ret_reg , 8 ) ) ) ; emit_insn ( gen_add3_insn ( ret_reg , ret_reg , GEN_INT ( 4 ) ) ) ; emit_cmp_and_jump_insns ( scratch , size_rtx , EQ , const0_rtx , SImode , 0 , endlab ) ; emit_insn ( gen_sub3_insn ( ret_reg , ret_reg , GEN_INT ( 4 ) ) ) ; emit_move_insn ( mem , XEXP ( temp_val , 0 ) ) ; emit_label ( endlab ) ; } return mem ; } } </s>

Handle the TARGET_STRUCT_VALUE target hook . Return where to find the structure return value address .


<s> bool PPCSubtarget :: useAA ( ) const { return needsAggressiveScheduling ( DarwinDirective ) ; } </s>

Enable use of alias analysis during code generation ( during MI scheduling , DAGCombine , etc . ) .


"PPC DAG preprocessing replacing:\nOld:    "

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> static char * to_host_file_spec ( char * filespec ) { strcpy ( new_host_filespec , "" ) ; if ( strchr ( filespec , ']' ) || strchr ( filespec , ':' ) ) strcpy ( new_host_filespec , filespec ) ; else { decc$to_vms ( filespec , translate_unix , 1 , 1 ) ; strcpy ( new_host_filespec , filename_buff ) ; } return new_host_filespec ; } </s>

Translate a Unix syntax file specification FILESPEC into VMS syntax . If indicators of VMS syntax found , return input string . Return a pointer to a static buffer .


<s> BitVector SIRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AMDGPU :: INDIRECT_BASE_ADDR ) ; reserveRegisterTuples ( Reserved , AMDGPU :: EXEC ) ; reserveRegisterTuples ( Reserved , AMDGPU :: FLAT_SCR ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TBA ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TMA ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP0_TTMP1 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP2_TTMP3 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP4_TTMP5 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP6_TTMP7 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP8_TTMP9 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP10_TTMP11 ) ; unsigned MaxWorkGroupSGPRCount = getMaxWorkGroupSGPRCount ( MF ) ; unsigned MaxWorkGroupVGPRCount = getMaxWorkGroupVGPRCount ( MF ) ; unsigned NumSGPRs = AMDGPU :: SGPR_32RegClass . getNumRegs ( ) ; unsigned NumVGPRs = AMDGPU :: VGPR_32RegClass . getNumRegs ( ) ; for ( unsigned i = MaxWorkGroupSGPRCount ; i < NumSGPRs ; ++ i ) { unsigned Reg = AMDGPU :: SGPR_32RegClass . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } for ( unsigned i = MaxWorkGroupVGPRCount ; i < NumVGPRs ; ++ i ) { unsigned Reg = AMDGPU :: VGPR_32RegClass . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } const SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , ScratchWaveOffsetReg ) ; } unsigned ScratchRSrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRSrcReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , ScratchRSrcReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , ScratchWaveOffsetReg ) ) ; } const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; if ( ST . debuggerReserveRegs ( ) ) { unsigned ReservedVGPRFirst = MaxWorkGroupVGPRCount - MFI -> getDebuggerReservedVGPRCount ( ) ; for ( unsigned i = ReservedVGPRFirst ; i < MaxWorkGroupVGPRCount ; ++ i ) { unsigned Reg = AMDGPU :: VGPR_32RegClass . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> Relocator :: Size ARMRelocator :: getSize ( Relocation :: Type pType ) const { return 32 ; } </s>

Return the number of bytes in the encoding of this instruction , or zero if the encoding size can not be known from the opcode .


"Encountered a global variable kind that is "

Emit the specified global variable to the .s file .


<s> const WebAssemblyInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> HOST_WIDE_INT rs6000_initial_elimination_offset ( int from , int to ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; HOST_WIDE_INT offset ; if ( from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) offset = info -> push_p ? 0 : - info -> total_size ; else if ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) { offset = info -> push_p ? 0 : - info -> total_size ; if ( FRAME_GROWS_DOWNWARD ) offset += info -> fixed_size + info -> vars_size + info -> parm_size ; } else if ( from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) offset = FRAME_GROWS_DOWNWARD ? info -> fixed_size + info -> vars_size + info -> parm_size : 0 ; else if ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) offset = info -> total_size ; else if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) offset = info -> push_p ? info -> total_size : 0 ; else if ( from == RS6000_PIC_OFFSET_TABLE_REGNUM ) offset = 0 ; else gcc_unreachable ( ) ; return offset ; } </s>

Define the offset between two registers , FROM to be eliminated and its replacement TO , at the start of a routine .


<s> bool AZPRAsmPrinter :: isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { const MachineBasicBlock * Pred = * MBB -> pred_begin ( ) ; MachineBasicBlock :: const_pred_iterator PI = MBB -> pred_begin ( ) , PI2 = PI ; ++ PI2 ; if ( PI2 != MBB -> pred_end ( ) ) return false ; if ( ! Pred -> isLayoutSuccessor ( MBB ) ) return false ; if ( Pred -> empty ( ) ) return true ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> isTerminator ( ) ) ; return ! ( I -> isBarrier ( ) || ( I -> getOpcode ( ) == AZPR :: BE && I -> getOperand ( 0 ) . getReg ( ) == I -> getOperand ( 1 ) . getReg ( ) ) ) ; } </s>

isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


<s> static bool available_occurrence_p ( const bb_info * bb , const vector_insn_info dem ) { insn_info * insn = dem . get_insn ( ) ; if ( dem . has_avl_reg ( ) ) { if ( ! vlmax_avl_p ( dem . get_avl ( ) ) ) { rtx dest = NULL_RTX ; if ( vsetvl_insn_p ( insn -> rtl ( ) ) ) dest = get_vl ( insn -> rtl ( ) ) ; for ( const insn_info * i = insn ; real_insn_and_same_bb_p ( i , bb ) ; i = i -> next_nondebug_insn ( ) ) { if ( read_vl_insn_p ( i -> rtl ( ) ) ) continue ; if ( find_access ( i -> defs ( ) , REGNO ( dem . get_avl ( ) ) ) ) return false ; if ( dest && find_access ( i -> defs ( ) , REGNO ( dest ) ) ) return false ; } } } return true ; } </s>

An `` available occurrence '' is one that is the last occurrence in the basic block and the operands are not modified by following statements in the basic block [ including this insn ] . For VSETVL instruction , we have these following formats : 1. vsetvl zero , rs1 . 2. vsetvl zero , imm . 3. vsetvl rd , rs1 . So base on these circumstances , a DEM is considered as a local available occurrence should satisfy these following conditions : 1 ) . rs1 ( avl ) are not modified by following statements in the basic block . 2 ) . rd ( vl ) are not modified by following statements in the basic block . Note : We do n't need to check VL/VTYPE here since DEM is UNKNOWN if VL/VTYPE is modified prior to the occurrence . This case is already considered as a non-local available occurrence .


<s> bool HexagonBitSimplify :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; auto & HST = MF . getSubtarget < HexagonSubtarget > ( ) ; auto & HRI = * HST . getRegisterInfo ( ) ; auto & HII = * HST . getInstrInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool Changed ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) ; const HexagonEvaluator HE ( HRI , MRI , HII , MF ) ; BitTracker BT ( HE , MF ) ; DEBUG ( BT . trace ( true ) ) ; BT . run ( ) ; MachineBasicBlock & Entry = MF . front ( ) ; RegisterSet AIG ; ConstGeneration ImmG ( BT , HII , MRI ) ; Changed |= visitBlock ( Entry , ImmG , AIG ) ; RegisterSet ARE ; RedundantInstrElimination RIE ( BT , HII , HRI , MRI ) ; bool Ried = visitBlock ( Entry , RIE , ARE ) ; if ( Ried ) { Changed = true ; BT . run ( ) ; } RegisterSet ACG ; CopyGeneration CopyG ( BT , HII , HRI , MRI ) ; Changed |= visitBlock ( Entry , CopyG , ACG ) ; RegisterSet ACP ; CopyPropagation CopyP ( HRI , MRI ) ; Changed |= visitBlock ( Entry , CopyP , ACP ) ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) || Changed ; BT . run ( ) ; RegisterSet ABS ; BitSimplification BitS ( BT , * MDT , HII , HRI , MRI , MF ) ; Changed |= visitBlock ( Entry , BitS , ABS ) ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) || Changed ; if ( Changed ) { for ( auto & B : MF ) for ( auto & I : B ) I . clearKillInfo ( ) ; DeadCodeElimination ( MF , * MDT ) . run ( ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> PPCSubtarget :: PPCSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , PPCTargetMachine & TM , bool is64Bit , CodeGenOpt :: Level OptLevel ) : PPCGenSubtargetInfo ( TT , CPU , FS ) , IsPPC64 ( is64Bit ) , TargetTriple ( TT ) , OptLevel ( OptLevel ) , FrameLowering ( initializeSubtargetDependencies ( CPU , FS ) ) , DL ( getDataLayoutString ( * this ) ) , InstrInfo ( * this ) , JITInfo ( * this ) , TLInfo ( TM ) , TSInfo ( & DL ) { } </s>

This constructor initializes the data members to match that of the specified triple .


<s> virtual const TeeRISCInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> void h8300_swap_out_of_er6 ( rtx addr ) { rtx insn ; if ( REGNO ( addr ) != SP_REG ) emit_move_insn ( addr , hard_frame_pointer_rtx ) ; insn = pop ( HARD_FRAME_POINTER_REGNUM ) ; if ( frame_pointer_needed ) add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , hard_frame_pointer_rtx , 2 * UNITS_PER_WORD ) ) ; else add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - 4 ) ) ) ; } </s>

Move the current value of er6 into ADDR and pop its old value from the stack .


<s> void NVPTXTargetStreamer :: emitRawBytes ( StringRef Data ) { MCTargetStreamer :: emitRawBytes ( Data ) ; const MCAsmInfo * MAI = Streamer . getContext ( ) . getAsmInfo ( ) ; const char * Directive = MAI -> getData8bitsDirective ( ) ; unsigned NumElements = Data . size ( ) ; const unsigned MaxLen = 40 ; unsigned NumChunks = 1 + ( ( NumElements - 1 ) / MaxLen ) ; for ( unsigned I = 0 ; I < NumChunks ; ++ I ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; const char * Label = Directive ; for ( auto It = std :: next ( Data . bytes_begin ( ) , I * MaxLen ) , End = ( I == NumChunks - 1 ) ? Data . bytes_end ( ) : std :: next ( Data . bytes_begin ( ) , ( I + 1 ) * MaxLen ) ; It != End ; ++ It ) { OS << Label << ( unsigned ) * It ; if ( Label == Directive ) Label = "," ; } Streamer . emitRawText ( OS . str ( ) ) ; } } </s>

Emit the bytes in Data into the output .


"Operand must be a register when you're"

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static tree rs6000_fold_builtin ( tree fndecl , int n_args ATTRIBUTE_UNUSED , tree * args , bool ignore ATTRIBUTE_UNUSED ) { if ( DECL_BUILT_IN_CLASS ( fndecl ) == BUILT_IN_MD ) { enum rs6000_builtins fn_code = ( enum rs6000_builtins ) DECL_FUNCTION_CODE ( fndecl ) ; switch ( fn_code ) { case RS6000_BUILTIN_NANQ : case RS6000_BUILTIN_NANSQ : { tree type = TREE_TYPE ( TREE_TYPE ( fndecl ) ) ; const char * str = c_getstr ( * args ) ; int quiet = fn_code == RS6000_BUILTIN_NANQ ; REAL_VALUE_TYPE real ; if ( str && real_nan ( & real , str , quiet , TYPE_MODE ( type ) ) ) return build_real ( type , real ) ; return NULL_TREE ; } case RS6000_BUILTIN_INFQ : case RS6000_BUILTIN_HUGE_VALQ : { tree type = TREE_TYPE ( TREE_TYPE ( fndecl ) ) ; REAL_VALUE_TYPE inf ; real_inf ( & inf ) ; return build_real ( type , inf ) ; } default : break ; } } return SUBTARGET_FOLD_BUILTIN ( fndecl , n_args , args , ignore ) ; return NULL_TREE ; } </s>

Target hook for early folding of built-ins , shamelessly stolen from ia64.cc .


"SIInstrInfo::storeRegToStackSlot - Do not know how to"

Store the specified register of the given register class to the specified stack frame index .


<s> MCInst AArch64InstrInfo :: getNop ( ) const { return MCInstBuilder ( AArch64 :: HINT ) . addImm ( 0 ) ; } </s>

Return the noop instruction to use for a noop .


<s> MachineBasicBlock :: iterator AArch64InstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , const outliner :: TargetCostInfo & TCI ) const { if ( TCI . CallConstructionID == MachineOutlinerTailCall ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: TCRETURNdi ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) . addImm ( 0 ) ) ; return It ; } if ( TCI . CallConstructionID == MachineOutlinerNoLRSave || TCI . CallConstructionID == MachineOutlinerThunk ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: BL ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; return It ; } MachineBasicBlock :: iterator CallPt ; MachineInstr * STRXpre = BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: STRXpre ) ) . addReg ( AArch64 :: SP , RegState :: Define ) . addReg ( AArch64 :: LR ) . addReg ( AArch64 :: SP ) . addImm ( - 16 ) ; It = MBB . insert ( It , STRXpre ) ; It ++ ; It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: BL ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; CallPt = It ; It ++ ; MachineInstr * LDRXpost = BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: LDRXpost ) ) . addReg ( AArch64 :: SP , RegState :: Define ) . addReg ( AArch64 :: LR , RegState :: Define ) . addReg ( AArch64 :: SP ) . addImm ( 16 ) ; It = MBB . insert ( It , LDRXpost ) ; return CallPt ; } </s>

Insert a call to an outlined function into the program .


<s> static int rs6000_emit_p9_fp_minmax ( rtx dest , rtx op , rtx true_cond , rtx false_cond ) { enum rtx_code code = GET_CODE ( op ) ; rtx op0 = XEXP ( op , 0 ) ; rtx op1 = XEXP ( op , 1 ) ; machine_mode compare_mode = GET_MODE ( op0 ) ; machine_mode result_mode = GET_MODE ( dest ) ; bool max_p = false ; if ( result_mode != compare_mode ) return 0 ; if ( code == GE || code == GT ) max_p = true ; else if ( code == LE || code == LT ) max_p = false ; else return 0 ; if ( rtx_equal_p ( op0 , true_cond ) && rtx_equal_p ( op1 , false_cond ) ) ; else if ( rtx_equal_p ( op1 , true_cond ) && rtx_equal_p ( op0 , false_cond ) ) max_p = ! max_p ; else return 0 ; rs6000_emit_minmax ( dest , max_p ? SMAX : SMIN , op0 , op1 ) ; return 1 ; } </s>

ISA 3.0 ( power9 ) minmax subcase to emit a XSMAXCDP or XSMINCDP instruction for SF/DF scalars . Move TRUE_COND to DEST if OP of the operands of the last comparison is nonzero/true , FALSE_COND if it is zero/false . Return 0 if the hardware has no such operation .


<s> static tree sh_symbian_associated_type ( tree decl ) { tree t = NULL_TREE ; if ( TREE_CODE ( TREE_TYPE ( decl ) ) == METHOD_TYPE ) return t ; if ( DECL_CONTEXT ( decl ) && TYPE_P ( DECL_CONTEXT ( decl ) ) ) t = DECL_CONTEXT ( decl ) ; return t ; } </s>

Return the type that we should use to determine if DECL is imported or exported .


<s> bool aarch64_float_const_representable_p ( rtx x ) { int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1 ; int exponent ; unsigned HOST_WIDE_INT mantissa , mask ; REAL_VALUE_TYPE r , m ; bool fail ; x = unwrap_const_vec_duplicate ( x ) ; if ( ! CONST_DOUBLE_P ( x ) ) return false ; if ( GET_MODE ( x ) == VOIDmode || ( GET_MODE ( x ) == HFmode && ! TARGET_FP_F16INST ) ) return false ; r = * CONST_DOUBLE_REAL_VALUE ( x ) ; if ( REAL_VALUE_ISINF ( r ) || REAL_VALUE_ISNAN ( r ) || REAL_VALUE_MINUS_ZERO ( r ) ) return false ; r = real_value_abs ( & r ) ; exponent = REAL_EXP ( & r ) ; real_ldexp ( & m , & r , point_pos - exponent ) ; wide_int w = real_to_integer ( & m , & fail , HOST_BITS_PER_WIDE_INT * 2 ) ; if ( w . ulow ( ) != 0 ) return false ; mantissa = w . elt ( 1 ) ; point_pos -= HOST_BITS_PER_WIDE_INT ; mask = ( ( unsigned HOST_WIDE_INT ) 1 << ( point_pos - 5 ) ) - 1 ; if ( ( mantissa & mask ) != 0 ) return false ; mantissa >>= point_pos - 5 ; if ( mantissa == 0 ) return false ; mantissa &= ~ ( 1 << 4 ) ; gcc_assert ( mantissa <= 15 ) ; exponent = 5 - exponent ; return ( exponent >= 0 && exponent <= 7 ) ; } </s>

Return true iff X can be represented by a quarter-precision floating point immediate operand X . Note , we can not represent 0.0 .


<s> static void annotate_constant_pool_refs ( rtx_insn * insn ) { if ( s390_safe_relative_long_p ( insn ) ) return ; annotate_constant_pool_refs_1 ( & PATTERN ( insn ) ) ; } </s>

Annotate every literal pool reference in X by an UNSPEC_LTREF expression . Fix up MEMs as required .


<s> static inline long long load_byte ( void * skb __attribute__ ( ( unused ) ) , unsigned long long off ) { return __builtin_bpf_load_byte ( off ) ; } </s>

Functions to emit BPF_LD_ABS and BPF_LD_IND instructions . We provide the `` standard '' names as synonyms of the corresponding GCC builtins . Note how the SKB argument is ignored .


<s> void s390_d_target_versions ( void ) { if ( TARGET_64BIT ) { d_add_builtin_version ( "S390X" ) ; d_add_builtin_version ( "SystemZ" ) ; } else d_add_builtin_version ( "S390" ) ; if ( TARGET_SOFT_FLOAT ) d_add_builtin_version ( "D_SoftFloat" ) ; else if ( TARGET_HARD_FLOAT ) d_add_builtin_version ( "D_HardFloat" ) ; } </s>

Implement TARGET_D_CPU_VERSIONS for S/390 and zSeries targets .


<s> static bool mips_orphaned_high_part_p ( mips_offset_table * htab , rtx_insn * insn ) { enum mips_symbol_type type ; rtx x , set ; set = single_set ( insn ) ; if ( set ) { x = SET_SRC ( set ) ; if ( GET_CODE ( x ) == HIGH && absolute_symbolic_operand ( XEXP ( x , 0 ) , VOIDmode ) ) return ! mips_lo_sum_offset_lookup ( htab , XEXP ( x , 0 ) , NO_INSERT ) ; if ( GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNSPEC_LOAD_GOT && mips_symbolic_constant_p ( XVECEXP ( x , 0 , 1 ) , SYMBOL_CONTEXT_LEA , & type ) && type == SYMBOL_GOTOFF_PAGE ) return ! mips_lo_sum_offset_lookup ( htab , XVECEXP ( x , 0 , 1 ) , NO_INSERT ) ; } return false ; } </s>

Return true if INSN is a SET of an orphaned high-part relocation . HTAB is a hash table of mips_lo_sum_offsets that describes all the LO_SUMs in the current function .


"AArch64 FastISel doesn't support types larger than i64"

This is a wrapper around getRegForValue that also takes care of truncating or sign-extending the given getelementptr index value .


<s> bool mips_expand_block_move ( rtx dest , rtx src , rtx length ) { if ( ! ISA_HAS_LWL_LWR ) return false ; if ( CONST_INT_P ( length ) ) { if ( INTVAL ( length ) <= MIPS_MAX_MOVE_BYTES_STRAIGHT ) { mips_block_move_straight ( dest , src , INTVAL ( length ) ) ; return true ; } else if ( optimize ) { mips_block_move_loop ( dest , src , INTVAL ( length ) , MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER ) ; return true ; } } return false ; } </s>

Expand a movmemsi instruction , which copies LENGTH bytes from memory reference SRC to memory reference DEST .


"Cannot adjust stack pointer by more than 32 bits (and adjusting by more than 20 bits never makes sense!)"


<s> int mn10300_symbolic_operand ( rtx op , machine_mode mode ATTRIBUTE_UNUSED ) { switch ( GET_CODE ( op ) ) { case SYMBOL_REF : case LABEL_REF : return 1 ; case CONST : op = XEXP ( op , 0 ) ; return ( ( GET_CODE ( XEXP ( op , 0 ) ) == SYMBOL_REF || GET_CODE ( XEXP ( op , 0 ) ) == LABEL_REF ) && CONST_INT_P ( XEXP ( op , 1 ) ) ) ; default : return 0 ; } } </s>

Return 1 if X contains a symbolic expression . We know these expressions will have one of a few well defined forms , so we need only check those forms .


<s> bool X86InstrInfo :: hasCommutePreference ( MachineInstr & MI , bool & Commute ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode != X86 :: ADD32rr && Opcode != X86 :: ADD64rr ) return false ; const MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; Register Reg1 = MI . getOperand ( 1 ) . getReg ( ) ; Register Reg2 = MI . getOperand ( 2 ) . getReg ( ) ; if ( MachineInstr * Inst = MRI . getUniqueVRegDef ( Reg1 ) ) { if ( isConvertibleLEA ( Inst ) && Inst -> getParent ( ) == MI . getParent ( ) ) { Commute = true ; return true ; } } if ( MachineInstr * Inst = MRI . getUniqueVRegDef ( Reg2 ) ) { if ( isConvertibleLEA ( Inst ) && Inst -> getParent ( ) == MI . getParent ( ) ) { Commute = false ; return true ; } } return false ; } </s>

Returns true if we have preference on the operands order in MI , the commute decision is returned in Commute .


<s> void emitGlobalVariable ( const GlobalVariable * GV ) override { } </s>

Emit the specified global variable to the .s file .


<s> CCAssignFn * X86FastISel :: CCAssignFnForCall ( unsigned CC , bool isTaillCall ) { if ( Subtarget -> is64Bit ( ) ) { if ( Subtarget -> isTargetWin64 ( ) ) return CC_X86_Win64_C ; else return CC_X86_64_C ; } if ( CC == CallingConv :: X86_FastCall ) return CC_X86_32_FastCall ; else if ( CC == CallingConv :: Fast ) return CC_X86_32_FastCC ; else return CC_X86_32_C ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> bool ix86_operands_ok_for_move_multiple ( rtx * operands , bool load , machine_mode mode ) { HOST_WIDE_INT offval_1 , offval_2 , msize ; rtx mem_1 , mem_2 , reg_1 , reg_2 , base_1 , base_2 , offset_1 , offset_2 ; if ( load ) { mem_1 = operands [ 1 ] ; mem_2 = operands [ 3 ] ; reg_1 = operands [ 0 ] ; reg_2 = operands [ 2 ] ; } else { mem_1 = operands [ 0 ] ; mem_2 = operands [ 2 ] ; reg_1 = operands [ 1 ] ; reg_2 = operands [ 3 ] ; } gcc_assert ( REG_P ( reg_1 ) && REG_P ( reg_2 ) ) ; if ( REGNO ( reg_1 ) != REGNO ( reg_2 ) ) return false ; if ( ! extract_base_offset_in_addr ( mem_1 , & base_1 , & offset_1 ) ) return false ; if ( ! extract_base_offset_in_addr ( mem_2 , & base_2 , & offset_2 ) ) return false ; if ( ! rtx_equal_p ( base_1 , base_2 ) ) return false ; offval_1 = INTVAL ( offset_1 ) ; offval_2 = INTVAL ( offset_2 ) ; msize = GET_MODE_SIZE ( mode ) ; if ( offval_1 + msize != offval_2 ) return false ; return true ; } </s>

Given OPERANDS of consecutive load/store , check if we can merge them into move multiple . LOAD is true if they are load instructions . MODE is the mode of memory operands .


<s> static bool riscv_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { return ( to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM ) ; } </s>

Make sure that we 're not trying to eliminate to the wrong hard frame pointer .


<s> LLT SITargetLowering :: getPreferredShiftAmountTy ( LLT Ty ) const { return ( Ty . getScalarSizeInBits ( ) <= 16 && Subtarget -> has16BitInsts ( ) ) ? Ty . changeElementSize ( 16 ) : Ty . changeElementSize ( 32 ) ; } </s>

Return the preferred type to use for a shift opcode , given the shifted amount type is ShiftValueTy .


<s> const MCS51Subtarget * MCS51TargetMachine :: getSubtargetImpl ( const Function & ) const { return & SubTarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static rtx gen_load_const_gp ( rtx reg ) { return PMODE_INSN ( gen_load_const_gp , ( reg ) ) ; } </s>

Return an instruction that copies $ gp into register REG . We want GCC to treat the register 's value as constant , so that its value can be rematerialized on demand .


<s> TargetLoweringBase :: LegalizeTypeAction getPreferredVectorAction ( MVT VT ) const override { if ( VT . getScalarSizeInBits ( ) % 8 == 0 ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s>
StringRef
getPassName
(
)
const
override
{
return
"SI Fix WWM Liveness"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static bool or1k_return_in_memory ( const_tree type , const_tree ) { const HOST_WIDE_INT size = int_size_in_bytes ( type ) ; return ( size == - 1 || size > ( 2 * UNITS_PER_WORD ) ) ; } </s>

worker function for TARGET_RETURN_IN_MEMORY . Returns true if the argument of TYPE should be returned in memory . On OpenRISC this is any value larger than 64-bits .


<s> Liveness ( MachineRegisterInfo & mri , const DataFlowGraph & g ) : DFG ( g ) , TRI ( g . getTRI ( ) ) , PRI ( g . getPRI ( ) ) , MDT ( g . getDT ( ) ) , MDF ( g . getDF ( ) ) , LiveMap ( g . getPRI ( ) ) , NoRegs ( g . getPRI ( ) ) { } </s>

During our initial pass over the program , we determine that things are either alive or maybe alive . More ...


<s> static bool classof ( const ARMConstantPoolValue * APV ) { return APV -> isGlobalValue ( ) || APV -> isBlockAddress ( ) || APV -> isLSDA ( ) || APV -> isPromotedGlobal ( ) ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> void EmitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) override { if ( IsThumb ) EmitThumbMappingSymbol ( ) ; else EmitARMMappingSymbol ( ) ; MCELFStreamer :: EmitInstruction ( Inst , STI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void X86FrameLowering :: BuildCFI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , const MCCFIInstruction & CFIInst ) const { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CFIIndex = MF . addFrameInst ( CFIInst ) ; BuildMI ( MBB , MBBI , DL , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } </s>

Wraps up getting a CFI index and building a MachineInstr for it .


<s> virtual bool runOnFunction ( Function & F ) { visit ( F ) ; return false ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> rtx ix86_build_signbit_mask ( machine_mode mode , bool vect , bool invert ) { machine_mode vec_mode , imode ; wide_int w ; rtx mask , v ; switch ( mode ) { case E_V8HFmode : case E_V16HFmode : case E_V32HFmode : vec_mode = mode ; imode = HImode ; break ; case E_V16SImode : case E_V16SFmode : case E_V8SImode : case E_V4SImode : case E_V8SFmode : case E_V4SFmode : case E_V2SFmode : case E_V2SImode : vec_mode = mode ; imode = SImode ; break ; case E_V8DImode : case E_V4DImode : case E_V2DImode : case E_V8DFmode : case E_V4DFmode : case E_V2DFmode : vec_mode = mode ; imode = DImode ; break ; case E_TImode : case E_TFmode : vec_mode = VOIDmode ; imode = TImode ; break ; default : gcc_unreachable ( ) ; } machine_mode inner_mode = GET_MODE_INNER ( mode ) ; w = wi :: set_bit_in_zero ( GET_MODE_BITSIZE ( inner_mode ) - 1 , GET_MODE_BITSIZE ( inner_mode ) ) ; if ( invert ) w = wi :: bit_not ( w ) ; mask = immed_wide_int_const ( w , imode ) ; mask = gen_lowpart ( inner_mode , mask ) ; if ( vec_mode == VOIDmode ) return force_reg ( inner_mode , mask ) ; v = ix86_build_const_vector ( vec_mode , vect , mask ) ; return force_reg ( vec_mode , v ) ; } </s>

A subroutine of ix86_expand_fp_absneg_operator and copysign expanders . Create a mask for the sign bit in MODE for an SSE register . If VECT is true , then replicate the mask for all elements of the vector register . If INVERT is true , then create a mask excluding the sign bit .


<s> bool HexagonSplitConst32AndConst64 :: runOnMachineFunction ( MachineFunction & Fn ) { auto & HST = Fn . getSubtarget < HexagonSubtarget > ( ) ; auto & HTM = static_cast < const HexagonTargetMachine & > ( Fn . getTarget ( ) ) ; auto & TLOF = * HTM . getObjFileLowering ( ) ; if ( HST . useSmallData ( ) && TLOF . isSmallDataEnabled ( HTM ) ) return false ; const TargetInstrInfo * TII = HST . getInstrInfo ( ) ; const TargetRegisterInfo * TRI = HST . getRegisterInfo ( ) ; for ( MachineBasicBlock & B : Fn ) { for ( auto I = B . begin ( ) , E = B . end ( ) ; I != E ; ) { MachineInstr & MI = * I ; ++ I ; unsigned Opc = MI . getOpcode ( ) ; if ( Opc == Hexagon :: CONST32 ) { unsigned DestReg = MI . getOperand ( 0 ) . getReg ( ) ; uint64_t ImmValue = MI . getOperand ( 1 ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( B , MI , DL , TII -> get ( Hexagon :: A2_tfrsi ) , DestReg ) . addImm ( ImmValue ) ; B . erase ( & MI ) ; } else if ( Opc == Hexagon :: CONST64 ) { unsigned DestReg = MI . getOperand ( 0 ) . getReg ( ) ; int64_t ImmValue = MI . getOperand ( 1 ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; unsigned DestLo = TRI -> getSubReg ( DestReg , Hexagon :: isub_lo ) ; unsigned DestHi = TRI -> getSubReg ( DestReg , Hexagon :: isub_hi ) ; int32_t LowWord = ( ImmValue & 0xFFFFFFFF ) ; int32_t HighWord = ( ImmValue >> 32 ) & 0xFFFFFFFF ; BuildMI ( B , MI , DL , TII -> get ( Hexagon :: A2_tfrsi ) , DestLo ) . addImm ( LowWord ) ; BuildMI ( B , MI , DL , TII -> get ( Hexagon :: A2_tfrsi ) , DestHi ) . addImm ( HighWord ) ; B . erase ( & MI ) ; } } } return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> static void loongarch_print_operand_punctuation ( FILE * file , int ch ) { switch ( ch ) { case '.' : fputs ( reg_names [ GP_REG_FIRST + 0 ] , file ) ; break ; case '$' : fputs ( reg_names [ STACK_POINTER_REGNUM ] , file ) ; break ; default : gcc_unreachable ( ) ; break ; } } </s>

Print the text for PRINT_OPERAND punctation character CH to FILE . The punctuation characters are : ' . ' Print the name of the register with a hard-wired zero ( zero or $ r0 ) . ' $ ' Print the name of the stack pointer register ( sp or $ r3 ) . See also loongarch_init_print_operand_punct .


<s> unsigned PPCTTI :: getIntImmCost ( Intrinsic :: ID IID , unsigned Idx , const APInt & Imm , Type * Ty ) const { if ( DisablePPCConstHoist ) return TargetTransformInfo :: getIntImmCost ( IID , Idx , Imm , Ty ) ; assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return ~ 0U ; switch ( IID ) { default : return TCC_Free ; case Intrinsic :: sadd_with_overflow : case Intrinsic :: uadd_with_overflow : case Intrinsic :: ssub_with_overflow : case Intrinsic :: usub_with_overflow : if ( ( Idx == 1 ) && Imm . getBitWidth ( ) <= 64 && isInt < 16 > ( Imm . getSExtValue ( ) ) ) return TCC_Free ; break ; } return PPCTTI :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s>
std
::
vector
<
const
SUnit
*
>
GCNMinRegScheduler
::
schedule
(
ArrayRef
<
const
SUnit
*
>
TopRoots
,
const
ScheduleDAG
&
DAG
)
{
const
auto
&
SUnits
=
DAG
.
SUnits
;
std
::
vector
<
const
SUnit
*
>
Schedule
;
Schedule
.
reserve
(
SUnits
.
size
(
)
)
;
initNumPreds
(
SUnits
)
;
int
StepNo
=
0
;
for
(
auto
SU
:
TopRoots
)
{
RQ
.
push_back
(
*
new
(
Alloc
.
Allocate
(
)
)
Candidate
(
SU
,
StepNo
)
)
;
}
releaseSuccessors
(
&
DAG
.
EntrySU
,
StepNo
)
;
while
(
!
RQ
.
empty
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"\n=== Picking candidate, Step = "
<<
StepNo
<<
"\n"
"Ready queue:"
;
for
(
auto
&
C
:
RQ
)
dbgs
(
)
<<
' '
<<
C
.
SU
->
NodeNum
<<
"(P"
<<
C
.
Priority
<<
')'
;
dbgs
(
)
<<
'\n'
;
)
;
auto
C
=
pickCandidate
(
)
;
assert
(
C
)
;
RQ
.
remove
(
*
C
)
;
auto
SU
=
C
->
SU
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Selected "
;
DAG
.
dumpNode
(
*
SU
)
)
;
releaseSuccessors
(
SU
,
StepNo
)
;
Schedule
.
push_back
(
SU
)
;
setIsScheduled
(
SU
)
;
if
(
getReadySuccessors
(
SU
)
==
0
)
bumpPredsPriority
(
SU
,
StepNo
)
;
++
StepNo
;
}
assert
(
SUnits
.
size
(
)
==
Schedule
.
size
(
)
)
;
return
Schedule
;
}
</s>

Schedule - This is called back from ScheduleDAGInstrs : :Run ( ) when it 's time to do some work .

AMDGPU
0
"\n=== Picking candidate, Step = "
"\n"
"Ready queue:"
"(P"
"Selected "
0


<s> static rtx function_arg_record_value ( tree type , enum machine_mode mode , int slotno , int named , int regbase ) { HOST_WIDE_INT typesize = int_size_in_bytes ( type ) ; struct function_arg_record_value_parms parms ; unsigned int nregs ; parms . ret = NULL_RTX ; parms . slotno = slotno ; parms . named = named ; parms . regbase = regbase ; parms . stack = 0 ; parms . nregs = 0 ; parms . intoffset = 0 ; function_arg_record_value_1 ( type , 0 , & parms , false ) ; if ( parms . intoffset != - 1 ) { unsigned int startbit , endbit ; int intslots , this_slotno ; startbit = parms . intoffset & - BITS_PER_WORD ; endbit = ( typesize * BITS_PER_UNIT + BITS_PER_WORD - 1 ) & - BITS_PER_WORD ; intslots = ( endbit - startbit ) / BITS_PER_WORD ; this_slotno = slotno + parms . intoffset / BITS_PER_WORD ; if ( intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno ) { intslots = MAX ( 0 , SPARC_INT_ARG_MAX - this_slotno ) ; parms . stack = 1 ; } parms . nregs += intslots ; } nregs = parms . nregs ; if ( nregs == 0 ) { if ( typesize <= 0 ) { return gen_rtx_REG ( mode , regbase ) ; } else { nregs = ( typesize + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } if ( nregs + slotno > SPARC_INT_ARG_MAX ) nregs = SPARC_INT_ARG_MAX - slotno ; } gcc_assert ( nregs != 0 ) ; parms . ret = gen_rtx_PARALLEL ( mode , rtvec_alloc ( parms . stack + nregs ) ) ; if ( parms . stack ) XVECEXP ( parms . ret , 0 , 0 ) = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; parms . nregs = 0 ; parms . intoffset = 0 ; function_arg_record_value_2 ( type , 0 , & parms , false ) ; function_arg_record_value_3 ( typesize * BITS_PER_UNIT , & parms ) ; gcc_assert ( parms . nregs == nregs ) ; return parms . ret ; } </s>

Used by function_arg and sparc_function_value_1 to implement the complex conventions of the 64-bit ABI for passing and returning structures . Return an expression valid as a return value for the FUNCTION_ARG and TARGET_FUNCTION_VALUE . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . MODE is the argument 's machine mode . SLOTNO is the index number of the argument 's slot in the parameter array . NAMED is true if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . REGBASE is the regno of the base register for the parameter array .


<s> bool MipsFastISel :: fastSelectInstruction ( const Instruction * I ) { if ( ! TargetSupported ) return false ; switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Load : return SelectLoad ( I ) ; case Instruction :: Store : return SelectStore ( I ) ; case Instruction :: Ret : return SelectRet ( I ) ; } return false ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> virtual const AlphaSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> virtual const SPURegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void prepare_move_operands ( rtx * operands , enum machine_mode mode ) { if ( GET_CODE ( operands [ 0 ] ) == MEM && ! reg_or_0_operand ( operands [ 1 ] , mode ) ) operands [ 1 ] = force_reg ( mode , operands [ 1 ] ) ; } </s>

Prepare operands for a move define_expand in MODE .


<s> static bool cr16_legitimate_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ATTRIBUTE_UNUSED ) { return 1 ; } </s>

Implement TARGET_LEGITIMATE_CONSTANT_P Nonzero if X is a legitimate constant for an immediate operand on the target machine . You can assume that X satisfies CONSTANT_P . In cr16c treat legitimize float constant as an immediate operand .


<s> static void init_float128_ibm ( machine_mode mode ) { if ( ! TARGET_XL_COMPAT ) { set_optab_libfunc ( add_optab , mode , "__gcc_qadd" ) ; set_optab_libfunc ( sub_optab , mode , "__gcc_qsub" ) ; set_optab_libfunc ( smul_optab , mode , "__gcc_qmul" ) ; set_optab_libfunc ( sdiv_optab , mode , "__gcc_qdiv" ) ; if ( ! TARGET_HARD_FLOAT ) { set_optab_libfunc ( neg_optab , mode , "__gcc_qneg" ) ; set_optab_libfunc ( eq_optab , mode , "__gcc_qeq" ) ; set_optab_libfunc ( ne_optab , mode , "__gcc_qne" ) ; set_optab_libfunc ( gt_optab , mode , "__gcc_qgt" ) ; set_optab_libfunc ( ge_optab , mode , "__gcc_qge" ) ; set_optab_libfunc ( lt_optab , mode , "__gcc_qlt" ) ; set_optab_libfunc ( le_optab , mode , "__gcc_qle" ) ; set_optab_libfunc ( unord_optab , mode , "__gcc_qunord" ) ; set_conv_libfunc ( sext_optab , mode , SFmode , "__gcc_stoq" ) ; set_conv_libfunc ( sext_optab , mode , DFmode , "__gcc_dtoq" ) ; set_conv_libfunc ( trunc_optab , SFmode , mode , "__gcc_qtos" ) ; set_conv_libfunc ( trunc_optab , DFmode , mode , "__gcc_qtod" ) ; set_conv_libfunc ( sfix_optab , SImode , mode , "__gcc_qtoi" ) ; set_conv_libfunc ( ufix_optab , SImode , mode , "__gcc_qtou" ) ; set_conv_libfunc ( sfloat_optab , mode , SImode , "__gcc_itoq" ) ; set_conv_libfunc ( ufloat_optab , mode , SImode , "__gcc_utoq" ) ; } } else { set_optab_libfunc ( add_optab , mode , "_xlqadd" ) ; set_optab_libfunc ( sub_optab , mode , "_xlqsub" ) ; set_optab_libfunc ( smul_optab , mode , "_xlqmul" ) ; set_optab_libfunc ( sdiv_optab , mode , "_xlqdiv" ) ; } if ( mode == IFmode ) { set_conv_libfunc ( sext_optab , mode , SDmode , "__dpd_extendsdtf" ) ; set_conv_libfunc ( sext_optab , mode , DDmode , "__dpd_extendddtf" ) ; set_conv_libfunc ( trunc_optab , mode , TDmode , "__dpd_trunctdtf" ) ; set_conv_libfunc ( trunc_optab , SDmode , mode , "__dpd_trunctfsd" ) ; set_conv_libfunc ( trunc_optab , DDmode , mode , "__dpd_trunctfdd" ) ; set_conv_libfunc ( sext_optab , TDmode , mode , "__dpd_extendtftd" ) ; set_conv_libfunc ( sfix_optab , DImode , mode , "__fixtfdi" ) ; set_conv_libfunc ( ufix_optab , DImode , mode , "__fixunstfdi" ) ; set_conv_libfunc ( sfloat_optab , mode , DImode , "__floatditf" ) ; set_conv_libfunc ( ufloat_optab , mode , DImode , "__floatunditf" ) ; if ( TARGET_POWERPC64 ) { set_conv_libfunc ( sfix_optab , TImode , mode , "__fixtfti" ) ; set_conv_libfunc ( ufix_optab , TImode , mode , "__fixunstfti" ) ; set_conv_libfunc ( sfloat_optab , mode , TImode , "__floattitf" ) ; set_conv_libfunc ( ufloat_optab , mode , TImode , "__floatuntitf" ) ; } } } </s>

Set up AIX/Darwin/64-bit Linux quad floating point routines .


<s>
Value
*
PPCTargetLowering
::
emitMaskedAtomicRMWIntrinsic
(
IRBuilderBase
&
Builder
,
AtomicRMWInst
*
AI
,
Value
*
AlignedAddr
,
Value
*
Incr
,
Value
*
Mask
,
Value
*
ShiftAmt
,
AtomicOrdering
Ord
)
const
{
assert
(
EnableQuadwordAtomics
&&
Subtarget
.
hasQuadwordAtomics
(
)
&&
"Only support quadword now"
)
;
Module
*
M
=
Builder
.
GetInsertBlock
(
)
->
getParent
(
)
->
getParent
(
)
;
Type
*
ValTy
=
AlignedAddr
->
getType
(
)
->
getPointerElementType
(
)
;
assert
(
ValTy
->
getPrimitiveSizeInBits
(
)
==
128
)
;
Function
*
RMW
=
Intrinsic
::
getDeclaration
(
M
,
getIntrinsicForAtomicRMWBinOp128
(
AI
->
getOperation
(
)
)
)
;
Type
*
Int64Ty
=
Type
::
getInt64Ty
(
M
->
getContext
(
)
)
;
Value
*
IncrLo
=
Builder
.
CreateTrunc
(
Incr
,
Int64Ty
,
"incr_lo"
)
;
Value
*
IncrHi
=
Builder
.
CreateTrunc
(
Builder
.
CreateLShr
(
Incr
,
64
)
,
Int64Ty
,
"incr_hi"
)
;
Value
*
Addr
=
Builder
.
CreateBitCast
(
AlignedAddr
,
Type
::
getInt8PtrTy
(
M
->
getContext
(
)
)
)
;
Value
*
LoHi
=
Builder
.
CreateCall
(
RMW
,
{
Addr
,
IncrLo
,
IncrHi
}
)
;
Value
*
Lo
=
Builder
.
CreateExtractValue
(
LoHi
,
0
,
"lo"
)
;
Value
*
Hi
=
Builder
.
CreateExtractValue
(
LoHi
,
1
,
"hi"
)
;
Lo
=
Builder
.
CreateZExt
(
Lo
,
ValTy
,
"lo64"
)
;
Hi
=
Builder
.
CreateZExt
(
Hi
,
ValTy
,
"hi64"
)
;
return
Builder
.
CreateOr
(
Lo
,
Builder
.
CreateShl
(
Hi
,
ConstantInt
::
get
(
ValTy
,
64
)
)
,
"val64"
)
;
}
</s>

Perform a masked atomicrmw using a target-specific intrinsic .


<s>
void
ARMAsmPrinter
::
emitMachineConstantPoolValue
(
MachineConstantPoolValue
*
MCPV
)
{
const
DataLayout
&
DL
=
getDataLayout
(
)
;
int
Size
=
DL
.
getTypeAllocSize
(
MCPV
->
getType
(
)
)
;
ARMConstantPoolValue
*
ACPV
=
static_cast
<
ARMConstantPoolValue
*
>
(
MCPV
)
;
if
(
ACPV
->
isPromotedGlobal
(
)
)
{
auto
*
ACPC
=
cast
<
ARMConstantPoolConstant
>
(
ACPV
)
;
for
(
const
auto
*
GV
:
ACPC
->
promotedGlobals
(
)
)
{
if
(
!
EmittedPromotedGlobalLabels
.
count
(
GV
)
)
{
MCSymbol
*
GVSym
=
getSymbol
(
GV
)
;
OutStreamer
->
emitLabel
(
GVSym
)
;
EmittedPromotedGlobalLabels
.
insert
(
GV
)
;
}
}
return
emitGlobalConstant
(
DL
,
ACPC
->
getPromotedGlobalInit
(
)
)
;
}
MCSymbol
*
MCSym
;
if
(
ACPV
->
isLSDA
(
)
)
{
MCSym
=
getMBBExceptionSym
(
MF
->
front
(
)
)
;
}
else
if
(
ACPV
->
isBlockAddress
(
)
)
{
const
BlockAddress
*
BA
=
cast
<
ARMConstantPoolConstant
>
(
ACPV
)
->
getBlockAddress
(
)
;
MCSym
=
GetBlockAddressSymbol
(
BA
)
;
}
else
if
(
ACPV
->
isGlobalValue
(
)
)
{
const
GlobalValue
*
GV
=
cast
<
ARMConstantPoolConstant
>
(
ACPV
)
->
getGV
(
)
;
unsigned
char
TF
=
Subtarget
->
isTargetMachO
(
)
ARMII
::
MO_NONLAZY
:
0
;
MCSym
=
GetARMGVSymbol
(
GV
,
TF
)
;
}
else
if
(
ACPV
->
isMachineBasicBlock
(
)
)
{
const
MachineBasicBlock
*
MBB
=
cast
<
ARMConstantPoolMBB
>
(
ACPV
)
->
getMBB
(
)
;
MCSym
=
MBB
->
getSymbol
(
)
;
}
else
{
assert
(
ACPV
->
isExtSymbol
(
)
&&
"unrecognized constant pool value"
)
;
auto
Sym
=
cast
<
ARMConstantPoolSymbol
>
(
ACPV
)
->
getSymbol
(
)
;
MCSym
=
GetExternalSymbolSymbol
(
Sym
)
;
}
const
MCExpr
*
Expr
=
MCSymbolRefExpr
::
create
(
MCSym
,
getModifierVariantKind
(
ACPV
->
getModifier
(
)
)
,
OutContext
)
;
if
(
ACPV
->
getPCAdjustment
(
)
)
{
MCSymbol
*
PCLabel
=
getPICLabel
(
DL
.
getPrivateGlobalPrefix
(
)
,
getFunctionNumber
(
)
,
ACPV
->
getLabelId
(
)
,
OutContext
)
;
const
MCExpr
*
PCRelExpr
=
MCSymbolRefExpr
::
create
(
PCLabel
,
OutContext
)
;
PCRelExpr
=
MCBinaryExpr
::
createAdd
(
PCRelExpr
,
MCConstantExpr
::
create
(
ACPV
->
getPCAdjustment
(
)
,
OutContext
)
,
OutContext
)
;
if
(
ACPV
->
mustAddCurrentAddress
(
)
)
{
MCSymbol
*
DotSym
=
OutContext
.
createTempSymbol
(
)
;
OutStreamer
->
emitLabel
(
DotSym
)
;
const
MCExpr
*
DotExpr
=
MCSymbolRefExpr
::
create
(
DotSym
,
OutContext
)
;
PCRelExpr
=
MCBinaryExpr
::
createSub
(
PCRelExpr
,
DotExpr
,
OutContext
)
;
}
Expr
=
MCBinaryExpr
::
createSub
(
Expr
,
PCRelExpr
,
OutContext
)
;
}
OutStreamer
->
emitValue
(
Expr
,
Size
)
;
}
</s>

EmitMachineConstantPoolValue - Print a machine constantpool value to the .s file .

ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARMII::MO_NONLAZY
0
ARM
ARM
"unrecognized constant pool value"
ARM


<s> void pru_register_abicheck_pass ( void ) { opt_pass * tiabi_check = make_pass_tiabi_check ( g ) ; struct register_pass_info tiabi_check_info = { tiabi_check , "*warn_unused_result" , 1 , PASS_POS_INSERT_AFTER } ; register_pass ( & tiabi_check_info ) ; } </s>


<s> bool X86FastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Load : return X86SelectLoad ( I ) ; case Instruction :: Store : return X86SelectStore ( I ) ; case Instruction :: Ret : return X86SelectRet ( I ) ; case Instruction :: ICmp : case Instruction :: FCmp : return X86SelectCmp ( I ) ; case Instruction :: ZExt : return X86SelectZExt ( I ) ; case Instruction :: SExt : return X86SelectSExt ( I ) ; case Instruction :: Br : return X86SelectBranch ( I ) ; case Instruction :: LShr : case Instruction :: AShr : case Instruction :: Shl : return X86SelectShift ( I ) ; case Instruction :: SDiv : case Instruction :: UDiv : case Instruction :: SRem : case Instruction :: URem : return X86SelectDivRem ( I ) ; case Instruction :: Select : return X86SelectSelect ( I ) ; case Instruction :: Trunc : return X86SelectTrunc ( I ) ; case Instruction :: FPExt : return X86SelectFPExt ( I ) ; case Instruction :: FPTrunc : return X86SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return X86SelectSIToFP ( I ) ; case Instruction :: UIToFP : return X86SelectUIToFP ( I ) ; case Instruction :: IntToPtr : case Instruction :: PtrToInt : { EVT SrcVT = TLI . getValueType ( DL , I -> getOperand ( 0 ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) ; if ( DstVT . bitsGT ( SrcVT ) ) return X86SelectZExt ( I ) ; if ( DstVT . bitsLT ( SrcVT ) ) return X86SelectTrunc ( I ) ; unsigned Reg = getRegForValue ( I -> getOperand ( 0 ) ) ; if ( Reg == 0 ) return false ; updateValueMap ( I , Reg ) ; return true ; } case Instruction :: BitCast : { if ( ! Subtarget -> hasSSE2 ( ) ) return false ; MVT SrcVT , DstVT ; if ( ! isTypeLegal ( I -> getOperand ( 0 ) -> getType ( ) , SrcVT ) || ! isTypeLegal ( I -> getType ( ) , DstVT ) ) return false ; if ( ! SrcVT . isVector ( ) || ! DstVT . isVector ( ) || SrcVT . getVectorElementType ( ) == MVT :: i1 || DstVT . getVectorElementType ( ) == MVT :: i1 ) return false ; unsigned Reg = getRegForValue ( I -> getOperand ( 0 ) ) ; if ( Reg == 0 ) return false ; updateValueMap ( I , Reg ) ; return true ; } } return false ; } </s>


<s> bool AArch64LoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { if ( skipFunction ( Fn . getFunction ( ) ) ) return false ; Subtarget = & static_cast < const AArch64Subtarget & > ( Fn . getSubtarget ( ) ) ; TII = static_cast < const AArch64InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; TRI = Subtarget -> getRegisterInfo ( ) ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; ModifiedRegUnits . init ( * TRI ) ; UsedRegUnits . init ( * TRI ) ; DefinedInBB . init ( * TRI ) ; bool Modified = false ; bool enableNarrowZeroStOpt = ! Subtarget -> requiresStrictAlign ( ) ; for ( auto & MBB : Fn ) { auto M = optimizeBlock ( MBB , enableNarrowZeroStOpt ) ; Modified |= M ; } return Modified ; } </s>


<s> void DLXFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s>
void
Nios2DAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> bool MipsAsmPrinter :: isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { const MachineBasicBlock * Pred = * MBB -> pred_begin ( ) ; if ( const BasicBlock * bb = Pred -> getBasicBlock ( ) ) if ( isa < SwitchInst > ( bb -> getTerminator ( ) ) ) return false ; if ( MBB -> isEHPad ( ) || MBB -> pred_empty ( ) ) return false ; MachineBasicBlock :: const_pred_iterator PI = MBB -> pred_begin ( ) , PI2 = PI ; ++ PI2 ; if ( PI2 != MBB -> pred_end ( ) ) return false ; if ( ! Pred -> isLayoutSuccessor ( MBB ) ) return false ; if ( Pred -> empty ( ) ) return true ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> isTerminator ( ) ) ; return ! I -> isBarrier ( ) ; } </s>

isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


<s> void aarch64_register_pragmas ( void ) { targetm . target_option . pragma_parse = aarch64_pragma_target_parse ; } </s>


<s> static bool use_toc_relative_ref ( rtx sym ) { return ( ( constant_pool_expr_p ( sym ) && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( get_pool_constant ( sym ) , get_pool_mode ( sym ) ) ) || ( TARGET_CMODEL == CMODEL_MEDIUM && SYMBOL_REF_LOCAL_P ( sym ) ) ) ; } </s>

Return true iff the given SYMBOL_REF refers to a constant pool entry that we have put in the TOC , or for cmodel=medium , if the SYMBOL_REF can be addressed relative to the toc pointer .


<s> static bool msp430_special_register_convention_p ( const char * name ) { int i ; for ( i = 0 ; special_convention_function_names [ i ] ; i ++ ) if ( ! strcmp ( name , special_convention_function_names [ i ] ) ) return true ; return false ; } </s>

TRUE if the function passed is a `` speical '' function . Special functions pass two DImode parameters in registers .


<s> bool HexagonInstrInfo :: isPredicable ( const MachineInstr & MI ) const { if ( ! MI . getDesc ( ) . isPredicable ( ) ) return false ; if ( MI . isCall ( ) || isTailCall ( MI ) ) { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; if ( ! MF . getSubtarget < HexagonSubtarget > ( ) . usePredicatedCalls ( ) ) return false ; } return true ; } </s>

Return true if the specified instruction can be predicated .


"LVI load hardening is only supported on 64-bit"

runOnMachineFunction - Emit the function body .


<s> static unsigned int nvptx_function_arg_boundary ( machine_mode mode , const_tree type ) { unsigned int boundary = type ? TYPE_ALIGN ( type ) : GET_MODE_BITSIZE ( mode ) ; if ( boundary > BITS_PER_WORD ) return 2 * BITS_PER_WORD ; if ( mode == BLKmode ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; if ( size > 4 ) return 2 * BITS_PER_WORD ; if ( boundary < BITS_PER_WORD ) { if ( size >= 3 ) return BITS_PER_WORD ; if ( size >= 2 ) return 2 * BITS_PER_UNIT ; } } return boundary ; } </s>


<s> SDValue MipsTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SDNode * CallNode , const Type * RetTy ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; MipsCC MipsCCInfo ( CallConv , Subtarget . isABI_O32 ( ) , Subtarget . isFP64bit ( ) , CCInfo ) ; MipsCCInfo . analyzeCallResult ( Ins , Subtarget . abiUsesSoftFloat ( ) , CallNode , RetTy ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( 1 ) ; InFlag = Val . getValue ( 2 ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( ISD :: BITCAST , DL , RVLocs [ i ] . getValVT ( ) , Val ) ; InVals . push_back ( Val ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> MVT X86TargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT == MVT :: v32i1 && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return MVT :: v32i8 ; if ( VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i1 && Subtarget . hasAVX512 ( ) && ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) || ( VT . getVectorNumElements ( ) > 16 && ! Subtarget . hasBWI ( ) ) || ( VT . getVectorNumElements ( ) > 64 && Subtarget . hasBWI ( ) ) ) ) return MVT :: i8 ; if ( ( VT == MVT :: v32i16 || VT == MVT :: v64i8 ) && ! EnableOldKNLABI && Subtarget . useAVX512Regs ( ) && ! Subtarget . hasBWI ( ) ) return MVT :: v16i32 ; return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


<s> void PPCPassConfig :: addIRPasses ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCBoolRetToIntPass ( ) ) ; addPass ( createAtomicExpandPass ( ) ) ; bool UsePrefetching = TM -> getTargetTriple ( ) . getVendor ( ) == Triple :: BGQ && getOptLevel ( ) != CodeGenOpt :: None ; if ( EnablePrefetch . getNumOccurrences ( ) > 0 ) UsePrefetching = EnablePrefetch ; if ( UsePrefetching ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Default && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> const uint16_t * X86RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { switch ( MF -> getFunction ( ) -> getCallingConv ( ) ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_SaveList ; case CallingConv :: WebKit_JS : return CSR_64_SaveList ; case CallingConv :: AnyReg : return CSR_MostRegs_64_SaveList ; case CallingConv :: Intel_OCL_BI : { bool HasAVX = TM . getSubtarget < X86Subtarget > ( ) . hasAVX ( ) ; bool HasAVX512 = TM . getSubtarget < X86Subtarget > ( ) . hasAVX512 ( ) ; if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_MostRegs_64_SaveList ; break ; default : break ; } bool CallsEHReturn = MF -> getMMI ( ) . callsEHReturn ( ) ; bool IsNaCl = TM . getSubtarget < X86Subtarget > ( ) . isTargetNaCl ( ) ; if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_SaveList ; if ( IsNaCl ) { if ( CallsEHReturn ) return CSR_NaCl64EHRet_SaveList ; return CSR_NaCl64_SaveList ; } if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; } if ( CallsEHReturn ) return CSR_32EHRet_SaveList ; return CSR_32_SaveList ; } </s>


<s> bool MipsTargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const MipsSubtarget & Subtarget = TM . getSubtarget < MipsSubtarget > ( ) ; if ( ! Subtarget . useSmallSection ( ) ) return false ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ; if ( Kind . isMergeable1ByteCString ( ) ) return false ; Type * Ty = GV -> getType ( ) -> getElementType ( ) ; return IsInSmallSection ( TM . getDataLayout ( ) -> getTypeAllocSize ( Ty ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> bool is ( KindTy K ) const { return ( Kind == K ) ; } </s>


"For each split Type there should be exactly one VReg."

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


"%<#pragma GCC arm%> requires a string parameter"

"unknown %<#pragma GCC arm%> option %qs"


<s> bool AArch64RegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { const AArch64FrameLowering & TFI = * getFrameLowering ( MF ) ; return TFI . hasFP ( MF ) ; } </s>

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot .


<s>
void
GeneralShuffle
::
add
(
SDValue
Op
,
unsigned
Elem
)
{
unsigned
BytesPerElement
=
VT
.
getVectorElementType
(
)
.
getStoreSize
(
)
;
EVT
FromVT
=
Op
.
getNode
(
)
Op
.
getValueType
(
)
:
VT
;
unsigned
FromBytesPerElement
=
FromVT
.
getVectorElementType
(
)
.
getStoreSize
(
)
;
assert
(
FromBytesPerElement
>=
BytesPerElement
&&
"Invalid EXTRACT_VECTOR_ELT"
)
;
unsigned
Byte
=
(
(
Elem
*
FromBytesPerElement
)
%
SystemZ
::
VectorBytes
+
(
FromBytesPerElement
BytesPerElement
)
)
;
while
(
Op
.
getNode
(
)
)
{
if
(
Op
.
getOpcode
(
)
==
ISD
::
BITCAST
)
Op
=
Op
.
getOperand
(
0
)
;
else
if
(
Op
.
getOpcode
(
)
==
ISD
::
VECTOR_SHUFFLE
&&
Op
.
hasOneUse
(
)
)
{
SmallVector
<
int
,
SystemZ
::
VectorBytes
>
OpBytes
;
getVPermMask
(
cast
<
ShuffleVectorSDNode
>
(
Op
)
,
OpBytes
)
;
int
NewByte
;
if
(
!
getShuffleInput
(
OpBytes
,
Byte
,
BytesPerElement
,
NewByte
)
)
break
;
if
(
NewByte
<
0
)
{
addUndef
(
)
;
return
;
}
Op
=
Op
.
getOperand
(
unsigned
(
NewByte
)
/
SystemZ
::
VectorBytes
)
;
Byte
=
unsigned
(
NewByte
)
%
SystemZ
::
VectorBytes
;
}
else
if
(
Op
.
getOpcode
(
)
==
ISD
::
UNDEF
)
{
addUndef
(
)
;
return
;
}
else
break
;
}
unsigned
OpNo
=
0
;
for
(
;
OpNo
<
Ops
.
size
(
)
;
++
OpNo
)
if
(
Ops
[
OpNo
]
==
Op
)
break
;
if
(
OpNo
==
Ops
.
size
(
)
)
Ops
.
push_back
(
Op
)
;
unsigned
Base
=
OpNo
*
SystemZ
::
VectorBytes
+
Byte
;
for
(
unsigned
I
=
0
;
I
<
BytesPerElement
;
++
I
)
Bytes
.
push_back
(
Base
+
I
)
;
}
</s>


<s> void Nios2InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << getRegisterName ( RegNo ) ; } </s>


<s> static void ix86_expand_divmod_libfunc ( rtx libfunc , machine_mode mode , rtx op0 , rtx op1 , rtx * quot_p , rtx * rem_p ) { rtx rem = assign_386_stack_local ( mode , SLOT_TEMP ) ; rtx quot = emit_library_call_value ( libfunc , NULL_RTX , LCT_NORMAL , mode , 3 , op0 , GET_MODE ( op0 ) , op1 , GET_MODE ( op1 ) , XEXP ( rem , 0 ) , Pmode ) ; * quot_p = quot ; * rem_p = rem ; } </s>


<s> llvm :: FastISel * X86 :: createFastISel ( MachineFunction & mf , DenseMap < const Value * , unsigned > & vm , DenseMap < const BasicBlock * , MachineBasicBlock * > & bm , DenseMap < const AllocaInst * , int > & am , SmallSet < const Instruction * , 8 > & cil ) { return new X86FastISel ( mf , vm , bm , am , cil ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> bool HexagonInstrInfo :: ClobbersPredicate ( MachineInstr & MI , std :: vector < MachineOperand > & Pred , bool SkipDead ) const { const HexagonRegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; for ( unsigned oper = 0 ; oper < MI . getNumOperands ( ) ; ++ oper ) { MachineOperand MO = MI . getOperand ( oper ) ; if ( MO . isReg ( ) ) { if ( ! MO . isDef ( ) ) continue ; const TargetRegisterClass * RC = HRI . getMinimalPhysRegClass ( MO . getReg ( ) ) ; if ( RC == & Hexagon :: PredRegsRegClass ) { Pred . push_back ( MO ) ; return true ; } continue ; } else if ( MO . isRegMask ( ) ) { for ( unsigned PR : Hexagon :: PredRegsRegClass ) { if ( ! MI . modifiesRegister ( PR , & HRI ) ) continue ; Pred . push_back ( MO ) ; return true ; } } } return false ; } </s>

If the specified instruction defines any predicate or condition code register ( s ) used for predication , returns true as well as the definition predicate ( s ) by reference .

Hexagon Hexagon Hexagon 0 Hexagon::PredRegsRegClass Hexagon::PredRegsRegClass


<s> void BPFFrameLowering :: emitPrologue ( MachineFunction & MF ) const { } </s>


<s> SDNode * TOYDAGToDAGISel :: Select ( SDNode * N ) { return SelectCode ( N ) ; } </s>


<s> void RISCVTargetStreamer :: emitTargetAttributes ( const MCSubtargetInfo & STI ) { if ( STI . hasFeature ( RISCV :: FeatureRV32E ) ) emitAttribute ( RISCVAttrs :: STACK_ALIGN , RISCVAttrs :: ALIGN_4 ) ; else emitAttribute ( RISCVAttrs :: STACK_ALIGN , RISCVAttrs :: ALIGN_16 ) ; std :: string Arch = "rv32" ; if ( STI . hasFeature ( RISCV :: Feature64Bit ) ) Arch = "rv64" ; if ( STI . hasFeature ( RISCV :: FeatureRV32E ) ) Arch += "e1p9" ; else Arch += "i2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtM ) ) Arch += "_m2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtA ) ) Arch += "_a2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtF ) ) Arch += "_f2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtD ) ) Arch += "_d2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtC ) ) Arch += "_c2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtB ) ) Arch += "_b0p93" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtV ) ) Arch += "_v0p10" ; if ( STI . hasFeature ( RISCV :: FeatureExtZfh ) ) Arch += "_zfh0p1" ; if ( STI . hasFeature ( RISCV :: FeatureExtZba ) ) Arch += "_zba0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbb ) ) Arch += "_zbb0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbc ) ) Arch += "_zbc0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbe ) ) Arch += "_zbe0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbf ) ) Arch += "_zbf0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbm ) ) Arch += "_zbm0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbp ) ) Arch += "_zbp0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbproposedc ) ) Arch += "_zbproposedc0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbr ) ) Arch += "_zbr0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbs ) ) Arch += "_zbs0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbt ) ) Arch += "_zbt0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZvamo ) ) Arch += "_zvamo0p10" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZvlsseg ) ) Arch += "_zvlsseg0p10" ; emitTextAttribute ( RISCVAttrs :: ARCH , Arch ) ; } </s>

Emit the build attributes that only depend on the hardware that we expect .


<s>
static
void
cr16_print_operand
(
FILE
*
file
,
rtx
x
,
int
code
)
{
int
ptr_dereference
=
0
;
switch
(
code
)
{
case
'd'
:
{
const
char
*
cr16_cmp_str
;
switch
(
GET_CODE
(
x
)
)
{
case
EQ
:
cr16_cmp_str
=
"eq"
;
break
;
case
NE
:
cr16_cmp_str
=
"ne"
;
break
;
case
GT
:
cr16_cmp_str
=
"lt"
;
break
;
case
GTU
:
cr16_cmp_str
=
"lo"
;
break
;
case
LT
:
cr16_cmp_str
=
"gt"
;
break
;
case
LTU
:
cr16_cmp_str
=
"hi"
;
break
;
case
GE
:
cr16_cmp_str
=
"le"
;
break
;
case
GEU
:
cr16_cmp_str
=
"ls"
;
break
;
case
LE
:
cr16_cmp_str
=
"ge"
;
break
;
case
LEU
:
cr16_cmp_str
=
"hs"
;
break
;
default
:
gcc_unreachable
(
)
;
}
fprintf
(
file
,
"%s"
,
cr16_cmp_str
)
;
return
;
}
case
'$'
:
putc
(
'$'
,
file
)
;
return
;
case
'p'
:
if
(
GET_CODE
(
x
)
==
REG
)
{
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
x
)
]
)
;
return
;
}
break
;
case
'b'
:
fprintf
(
file
,
"0x%lx"
,
INTVAL
(
x
)
)
;
return
;
case
'r'
:
fprintf
(
file
,
"%d"
,
cr16_operand_bit_pos
(
INTVAL
(
x
)
,
0
)
)
;
return
;
case
's'
:
fprintf
(
file
,
"%d"
,
cr16_operand_bit_pos
(
INTVAL
(
x
)
,
1
)
)
;
return
;
case
'g'
:
ptr_dereference
=
1
;
case
'f'
:
case
0
:
switch
(
GET_CODE
(
x
)
)
{
case
REG
:
if
(
GET_MODE_BITSIZE
(
GET_MODE
(
x
)
)
>
BITS_PER_WORD
)
{
if
(
LONG_REG_P
(
REGNO
(
x
)
)
)
fprintf
(
file
,
"(%s)"
,
reg_names
[
REGNO
(
x
)
]
)
;
else
fprintf
(
file
,
"(%s,%s)"
,
reg_names
[
REGNO
(
x
)
+
1
]
,
reg_names
[
REGNO
(
x
)
]
)
;
}
else
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
x
)
]
)
;
return
;
case
MEM
:
output_address
(
GET_MODE
(
x
)
,
XEXP
(
x
,
0
)
)
;
return
;
case
CONST_DOUBLE
:
{
long
l
;
REAL_VALUE_TO_TARGET_SINGLE
(
*
CONST_DOUBLE_REAL_VALUE
(
x
)
,
l
)
;
fprintf
(
file
,
"$0x%lx"
,
l
)
;
return
;
}
case
CONST_INT
:
{
fprintf
(
file
,
"$%ld"
,
INTVAL
(
x
)
)
;
return
;
}
case
UNSPEC
:
switch
(
XINT
(
x
,
1
)
)
{
default
:
gcc_unreachable
(
)
;
}
break
;
default
:
if
(
!
ptr_dereference
)
{
putc
(
'$'
,
file
)
;
}
cr16_print_operand_address
(
file
,
VOIDmode
,
x
)
;
return
;
}
gcc_unreachable
(
)
;
default
:
output_operand_lossage
(
"invalid %%xn code"
)
;
}
gcc_unreachable
(
)
;
}
</s>

Implements the macro PRINT_OPERAND defined in cr16.h .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; if ( TT . isOSBinFormatMachO ( ) ) this -> Options . TrapUnreachable = true ; if ( getOptLevel ( ) <= EnableGlobalISelAtO ) setGlobalISel ( true ) ; } </s>


<s> static rtx_insn * calculate_pic_address_constant ( rtx reg , rtx pic_reg , rtx orig ) { rtx pat ; rtx mem ; pat = gen_calculate_pic_address ( reg , pic_reg , orig ) ; mem = SET_SRC ( pat ) ; gcc_assert ( MEM_P ( mem ) && ! MEM_VOLATILE_P ( mem ) ) ; MEM_READONLY_P ( mem ) = 1 ; MEM_NOTRAP_P ( mem ) = 1 ; return emit_insn ( pat ) ; } </s>

Generate insns to calculate the address of ORIG in pic mode .


<s> static bool nvptx_strict_argument_naming ( cumulative_args_t cum_v ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; return cum -> fntype == NULL_TREE || stdarg_p ( cum -> fntype ) ; } </s>

Handle the TARGET_STRICT_ARGUMENT_NAMING target hook . For nvptx , we know how to handle functions declared as stdarg : by passing an extra pointer to the unnamed arguments . However , the Fortran frontend can produce a different situation , where a function pointer is declared with no arguments , but the actual function and calls to it take more arguments . In that case , we want to ensure the call matches the definition of the function .


"unknown register class in storeRegToStack"

Load the specified register of the given register class from the specified stack frame index .


<s> static void spu_emit_branch_hint ( rtx_insn * before , rtx_insn * branch , rtx target , int distance , sbitmap blocks ) { rtx branch_label = 0 ; rtx_insn * hint ; rtx_insn * insn ; rtx_jump_table_data * table ; if ( before == 0 || branch == 0 || target == 0 ) return ; if ( distance > 600 ) return ; if ( NOTE_INSN_BASIC_BLOCK_P ( before ) ) before = NEXT_INSN ( before ) ; branch_label = gen_label_rtx ( ) ; LABEL_NUSES ( branch_label ) ++ ; LABEL_PRESERVE_P ( branch_label ) = 1 ; insn = emit_label_before ( branch_label , branch ) ; branch_label = gen_rtx_LABEL_REF ( VOIDmode , branch_label ) ; bitmap_set_bit ( blocks , BLOCK_FOR_INSN ( branch ) -> index ) ; hint = emit_insn_before ( gen_hbr ( branch_label , target ) , before ) ; recog_memoized ( hint ) ; INSN_LOCATION ( hint ) = INSN_LOCATION ( branch ) ; HINTED_P ( branch ) = 1 ; if ( GET_CODE ( target ) == LABEL_REF ) HINTED_P ( XEXP ( target , 0 ) ) = 1 ; else if ( tablejump_p ( branch , 0 , & table ) ) { rtvec vec ; int j ; if ( GET_CODE ( PATTERN ( table ) ) == ADDR_VEC ) vec = XVEC ( PATTERN ( table ) , 0 ) ; else vec = XVEC ( PATTERN ( table ) , 1 ) ; for ( j = GET_NUM_ELEM ( vec ) - 1 ; j >= 0 ; -- j ) HINTED_P ( XEXP ( RTVEC_ELT ( vec , j ) , 0 ) ) = 1 ; } if ( distance >= 588 ) { insn = emit_insn_before ( gen_blockage ( ) , hint ) ; recog_memoized ( insn ) ; INSN_LOCATION ( insn ) = INSN_LOCATION ( hint ) ; } else if ( distance <= 8 * 4 ) { int d ; for ( d = distance ; d < 8 * 4 ; d += 4 ) { insn = emit_insn_after ( gen_nopn_nv ( gen_rtx_REG ( SImode , 127 ) ) , hint ) ; recog_memoized ( insn ) ; INSN_LOCATION ( insn ) = INSN_LOCATION ( hint ) ; } insn = emit_insn_after ( gen_blockage ( ) , hint ) ; recog_memoized ( insn ) ; INSN_LOCATION ( insn ) = INSN_LOCATION ( hint ) ; if ( CALL_P ( branch ) && distance < 8 * 4 ) { insn = emit_insn_before ( gen_blockage ( ) , branch ) ; recog_memoized ( insn ) ; INSN_LOCATION ( insn ) = INSN_LOCATION ( branch ) ; } } } </s>


<s>
SDValue
RISCVTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
report_fatal_error
(
"unimplemented operand"
)
;
case
ISD
::
GlobalAddress
:
return
lowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
lowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
lowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
lowerSELECT
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
lowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
lowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
lowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
BITCAST
:
{
assert
(
Subtarget
.
is64Bit
(
)
&&
Subtarget
.
hasStdExtF
(
)
&&
"Unexpected custom legalisation"
)
;
SDLoc
DL
(
Op
)
;
SDValue
Op0
=
Op
.
getOperand
(
0
)
;
if
(
Op
.
getValueType
(
)
!=
MVT
::
f32
||
Op0
.
getValueType
(
)
!=
MVT
::
i32
)
return
SDValue
(
)
;
SDValue
NewOp0
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
DL
,
MVT
::
i64
,
Op0
)
;
SDValue
FPConv
=
DAG
.
getNode
(
RISCVISD
::
FMV_W_X_RV64
,
DL
,
MVT
::
f32
,
NewOp0
)
;
return
FPConv
;
}
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> void SparcAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { switch ( MI -> getOpcode ( ) ) { default : break ; case TargetOpcode :: DBG_VALUE : return ; case SP :: GETPCX : LowerGETPCXAndEmitMCInsts ( MI , getSubtargetInfo ( ) ) ; return ; } MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { MCInst TmpInst ; LowerSparcMachineInstrToMCInst ( & * I , TmpInst , * this ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } while ( ( ++ I != E ) && I -> isInsideBundle ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool AMDGPUTTIImpl :: isSourceOfDivergence ( const Value * V ) const { if ( const Argument * A = dyn_cast < Argument > ( V ) ) return ! isArgPassedInSGPR ( A ) ; if ( const LoadInst * Load = dyn_cast < LoadInst > ( V ) ) return Load -> getPointerAddressSpace ( ) == ST -> getAMDGPUAS ( ) . PRIVATE_ADDRESS ; if ( isa < AtomicRMWInst > ( V ) || isa < AtomicCmpXchgInst > ( V ) ) return true ; if ( const IntrinsicInst * Intrinsic = dyn_cast < IntrinsicInst > ( V ) ) return AMDGPU :: isIntrinsicSourceOfDivergence ( Intrinsic -> getIntrinsicID ( ) ) ; if ( isa < CallInst > ( V ) || isa < InvokeInst > ( V ) ) return true ; return false ; } </s>

Returns whether V is a source of divergence .

AMDGPU AMDGPU AMDGPU AMDGPU::isIntrinsicSourceOfDivergence


<s> bool mips_hard_regno_rename_ok ( unsigned int old_reg ATTRIBUTE_UNUSED , unsigned int new_reg ) { if ( cfun -> machine -> interrupt_handler_p && ! df_regs_ever_live_p ( new_reg ) ) return false ; return true ; } </s>

Return nonzero if register OLD_REG can be renamed to register NEW_REG .


<s> MachineInstr * SparcInstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , int FI ) const { if ( Ops . size ( ) != 1 ) return NULL ; unsigned OpNum = Ops [ 0 ] ; bool isFloat = false ; MachineInstr * NewMI = NULL ; switch ( MI -> getOpcode ( ) ) { case SP :: ORrr : if ( MI -> getOperand ( 1 ) . isReg ( ) && MI -> getOperand ( 1 ) . getReg ( ) == SP :: G0 && MI -> getOperand ( 0 ) . isReg ( ) && MI -> getOperand ( 2 ) . isReg ( ) ) { if ( OpNum == 0 ) NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( SP :: STri ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( MI -> getOperand ( 2 ) . getReg ( ) ) ; else NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( SP :: LDri ) , MI -> getOperand ( 0 ) . getReg ( ) ) . addFrameIndex ( FI ) . addImm ( 0 ) ; } break ; case SP :: FMOVS : isFloat = true ; case SP :: FMOVD : if ( OpNum == 0 ) { unsigned SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; bool isKill = MI -> getOperand ( 1 ) . isKill ( ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isFloat ? SP :: STFri : SP :: STDFri ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , false , false , isKill ) ; } else { unsigned DstReg = MI -> getOperand ( 0 ) . getReg ( ) ; bool isDead = MI -> getOperand ( 0 ) . isDead ( ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isFloat ? SP :: LDFri : SP :: LDDFri ) ) . addReg ( DstReg , true , false , false , isDead ) . addFrameIndex ( FI ) . addImm ( 0 ) ; } break ; } return NewMI ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


"LR & FP are always handled in emitPrologue"

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s>
PPCTTI
::
PopcntSupportKind
PPCTTI
::
getPopcntSupport
(
unsigned
TyWidth
)
const
{
assert
(
isPowerOf2_32
(
TyWidth
)
&&
"Ty width must be power of 2"
)
;
if
(
ST
->
hasPOPCNTD
(
)
&&
TyWidth
<=
64
)
return
PSK_FastHardware
;
return
PSK_Software
;
}
</s>

Return hardware support for population count .

PowerPC
PPC
PPC
"Ty width must be power of 2"
64


<s> void MSP430RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( ! TFI -> hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; uint64_t Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = 0 ; if ( Old -> getOpcode ( ) == getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( MSP430 :: SUB16ri ) , MSP430 :: SPW ) . addReg ( MSP430 :: SPW ) . addImm ( Amount ) ; } else { assert ( Old -> getOpcode ( ) == getCallFrameDestroyOpcode ( ) ) ; uint64_t CalleeAmt = Old -> getOperand ( 1 ) . getImm ( ) ; Amount -= CalleeAmt ; if ( Amount ) New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( MSP430 :: ADD16ri ) , MSP430 :: SPW ) . addReg ( MSP430 :: SPW ) . addImm ( Amount ) ; } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { MachineInstr * Old = I ; MachineInstr * New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( MSP430 :: SUB16ri ) , MSP430 :: SPW ) . addReg ( MSP430 :: SPW ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> int tilegx_asm_preferred_eh_data_format ( int code ATTRIBUTE_UNUSED , int global ) { int type = TARGET_32BIT ? DW_EH_PE_sdata4 : DW_EH_PE_sdata8 ; return ( global ? DW_EH_PE_indirect : 0 ) | DW_EH_PE_pcrel | type ; } </s>

Select a format to encode pointers in exception handling data . CODE is 0 for data , 1 for code labels , 2 for function pointers . GLOBAL is true if the symbol may be affected by dynamic relocations .


<s>
unsigned
CJGInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
I
->
getOpcode
(
)
!=
CJG
::
JMP
&&
I
->
getOpcode
(
)
!=
CJG
::
JCC
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .

CJG
CJG
"code size not handled"
0
CJG::JMP
CJG::JCC


<s> static bool rs6000_builtin_valid_without_lhs ( enum rs6000_builtins fn_code ) { switch ( fn_code ) { case ALTIVEC_BUILTIN_STVX_V16QI : case ALTIVEC_BUILTIN_STVX_V8HI : case ALTIVEC_BUILTIN_STVX_V4SI : case ALTIVEC_BUILTIN_STVX_V4SF : case ALTIVEC_BUILTIN_STVX_V2DI : case ALTIVEC_BUILTIN_STVX_V2DF : return true ; default : return false ; } } </s>

Helper function to sort out which built-ins may be valid without having a LHS .


<s>
static
void
cr16_print_operand
(
FILE
*
file
,
rtx
x
,
int
code
)
{
int
ptr_dereference
=
0
;
switch
(
code
)
{
case
'd'
:
{
const
char
*
cr16_cmp_str
;
switch
(
GET_CODE
(
x
)
)
{
case
EQ
:
cr16_cmp_str
=
"eq"
;
break
;
case
NE
:
cr16_cmp_str
=
"ne"
;
break
;
case
GT
:
cr16_cmp_str
=
"lt"
;
break
;
case
GTU
:
cr16_cmp_str
=
"lo"
;
break
;
case
LT
:
cr16_cmp_str
=
"gt"
;
break
;
case
LTU
:
cr16_cmp_str
=
"hi"
;
break
;
case
GE
:
cr16_cmp_str
=
"le"
;
break
;
case
GEU
:
cr16_cmp_str
=
"ls"
;
break
;
case
LE
:
cr16_cmp_str
=
"ge"
;
break
;
case
LEU
:
cr16_cmp_str
=
"hs"
;
break
;
default
:
gcc_unreachable
(
)
;
}
fprintf
(
file
,
"%s"
,
cr16_cmp_str
)
;
return
;
}
case
'$'
:
putc
(
'$'
,
file
)
;
return
;
case
'p'
:
if
(
GET_CODE
(
x
)
==
REG
)
{
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
x
)
]
)
;
return
;
}
break
;
case
'b'
:
fprintf
(
file
,
"0x%lx"
,
INTVAL
(
x
)
)
;
return
;
case
'r'
:
fprintf
(
file
,
"%d"
,
cr16_operand_bit_pos
(
INTVAL
(
x
)
,
0
)
)
;
return
;
case
's'
:
fprintf
(
file
,
"%d"
,
cr16_operand_bit_pos
(
INTVAL
(
x
)
,
1
)
)
;
return
;
case
'g'
:
ptr_dereference
=
1
;
case
'f'
:
case
0
:
switch
(
GET_CODE
(
x
)
)
{
case
REG
:
if
(
GET_MODE_BITSIZE
(
GET_MODE
(
x
)
)
>
BITS_PER_WORD
)
{
if
(
LONG_REG_P
(
REGNO
(
x
)
)
)
fprintf
(
file
,
"(%s)"
,
reg_names
[
REGNO
(
x
)
]
)
;
else
fprintf
(
file
,
"(%s,%s)"
,
reg_names
[
REGNO
(
x
)
+
1
]
,
reg_names
[
REGNO
(
x
)
]
)
;
}
else
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
x
)
]
)
;
return
;
case
MEM
:
output_address
(
XEXP
(
x
,
0
)
)
;
return
;
case
CONST_DOUBLE
:
{
REAL_VALUE_TYPE
r
;
long
l
;
REAL_VALUE_FROM_CONST_DOUBLE
(
r
,
x
)
;
REAL_VALUE_TO_TARGET_SINGLE
(
r
,
l
)
;
fprintf
(
file
,
"$0x%lx"
,
l
)
;
return
;
}
case
CONST_INT
:
{
fprintf
(
file
,
"$%ld"
,
INTVAL
(
x
)
)
;
return
;
}
case
UNSPEC
:
switch
(
XINT
(
x
,
1
)
)
{
default
:
gcc_unreachable
(
)
;
}
break
;
default
:
if
(
!
ptr_dereference
)
{
putc
(
'$'
,
file
)
;
}
cr16_print_operand_address
(
file
,
x
)
;
return
;
}
default
:
output_operand_lossage
(
"invalid %%xn code"
)
;
}
gcc_unreachable
(
)
;
}
</s>