<s> unsigned SITargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( CC != CallingConv :: AMDGPU_KERNEL && VT . isVector ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; EVT ScalarVT = VT . getScalarType ( ) ; unsigned Size = ScalarVT . getSizeInBits ( ) ; if ( Size == 32 ) return NumElts ; if ( Size == 64 ) return 2 * NumElts ; if ( Size == 16 && Subtarget -> has16BitInsts ( ) && isPowerOf2_32 ( NumElts ) ) return VT . getVectorNumElements ( ) / 2 ; } return TargetLowering :: getNumRegistersForCallingConv ( Context , CC , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s> static rtx moxie_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( mode , MOXIE_R0 ) ; } </s>

Define how to find the value returned by a library function . We always return values in register $ r0 for moxie .


"address spaces are not supported for reduced "

"address space %qs not supported for devices with "

Return true if we support address space AS for the architecture in effect and false , otherwise . If LOC is not UNKNOWN_LOCATION then also issue a respective error .


<s> bool addGCPasses ( ) override { return false ; } </s>

addGCPasses - Add late codegen passes that analyze code for garbage collection .


<s> static rtx sparc_function_arg_1 ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named , bool incoming ) { const CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int regbase = ( incoming ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST ) ; int slotno , regno , padding ; enum mode_class mclass = GET_MODE_CLASS ( mode ) ; slotno = function_arg_slotno ( cum , mode , type , named , incoming , & regno , & padding ) ; if ( slotno == - 1 ) return 0 ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( ( TARGET_ARCH32 && size <= 8 ) || ( TARGET_ARCH64 && size <= 16 ) ) ; if ( mode == BLKmode ) return function_arg_vector_value ( size , SPARC_FP_ARG_FIRST + 2 * slotno ) ; mclass = MODE_FLOAT ; } if ( TARGET_ARCH32 ) return gen_rtx_REG ( mode , regno ) ; if ( type && TREE_CODE ( type ) == RECORD_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; return function_arg_record_value ( type , mode , slotno , named , regbase ) ; } else if ( type && TREE_CODE ( type ) == UNION_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; return function_arg_union_value ( size , mode , slotno , regno ) ; } else if ( ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) && SPARC_FP_REG_P ( regno ) ) { rtx reg = gen_rtx_REG ( mode , regno ) ; if ( cum -> prototype_p || cum -> libcall_p ) return reg ; else { rtx v0 , v1 ; if ( ( regno - SPARC_FP_ARG_FIRST ) < SPARC_INT_ARG_MAX * 2 ) { int intreg ; if ( incoming ) return reg ; intreg = ( SPARC_OUTGOING_INT_ARG_FIRST + ( regno - SPARC_FP_ARG_FIRST ) / 2 ) ; v0 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , intreg ) , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , v0 , v1 ) ) ; } else { v0 = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , v0 , v1 ) ) ; } } } else if ( type && AGGREGATE_TYPE_P ( type ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; mode = mode_for_size ( size * BITS_PER_UNIT , MODE_INT , 0 ) ; } return gen_rtx_REG ( mode , regno ) ; } </s>

Determine where to put an argument to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . NAMED is true if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . INCOMING_P is false for TARGET_FUNCTION_ARG , true for TARGET_FUNCTION_INCOMING_ARG .


<s> enum rtx_code ix86_fp_compare_code_to_integer ( enum rtx_code code ) { switch ( code ) { case GT : return GTU ; case GE : return GEU ; case ORDERED : case UNORDERED : return code ; break ; case UNEQ : return EQ ; break ; case UNLT : return LTU ; break ; case UNLE : return LEU ; break ; case LTGT : return NE ; break ; default : return UNKNOWN ; } } </s>

Convert comparison codes we use to represent FP comparison to integer code that will result in proper branch . Return UNKNOWN if no such code is available .


<s> int h8300_funcvec_function_p ( tree func ) { tree a ; if ( TREE_CODE ( func ) != FUNCTION_DECL ) return 0 ; a = lookup_attribute ( "function_vector" , DECL_ATTRIBUTES ( func ) ) ; return a != NULL_TREE ; } </s>

Return nonzero if FUNC is a function that should be called through the function vector .


<s> pure_scalable_type_info :: analysis_result pure_scalable_type_info :: analyze_record ( const_tree type ) { for ( tree field = TYPE_FIELDS ( type ) ; field ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( DECL_SIZE ( field ) && integer_zerop ( DECL_SIZE ( field ) ) ) continue ; pure_scalable_type_info field_info ; analysis_result subresult = field_info . analyze ( TREE_TYPE ( field ) ) ; if ( subresult == NO_ABI_IDENTITY ) continue ; if ( subresult != IS_PST ) return subresult ; tree bitpos = bit_position ( field ) ; gcc_assert ( poly_int_tree_p ( bitpos ) ) ; poly_widest_int wide_bytepos = exact_div ( wi :: to_poly_widest ( bitpos ) , BITS_PER_UNIT ) ; poly_uint64 bytepos ; if ( ! wide_bytepos . to_uhwi ( & bytepos ) || pieces . length ( ) + field_info . pieces . length ( ) > MAX_PIECES ) return DOESNT_MATTER ; gcc_assert ( ! field_info . pieces . is_empty ( ) ) ; for ( unsigned int i = 0 ; i < field_info . pieces . length ( ) ; ++ i ) { piece p = field_info . pieces [ i ] ; p . offset += bytepos ; add_piece ( p ) ; } } return pieces . is_empty ( ) ? NO_ABI_IDENTITY : IS_PST ; } </s>

Subroutine of analyze for handling RECORD_TYPEs .


"Some operands reg class are incompatible!"

optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare ; remove Compare if possible .


<s> bool AArch64Subtarget :: useAA ( ) const { return UseAA ; } </s>

Enable use of alias analysis during code generation ( during MI scheduling , DAGCombine , etc . ) .


<s> static void add_compiler_branch_island ( tree label_name , tree function_name , int line_number ) { branch_island bi = { function_name , label_name , line_number } ; vec_safe_push ( branch_islands , bi ) ; } </s>

Remember to generate a branch island for far calls to the given function .


<s> bool HexagonGenMux :: runOnMachineFunction ( MachineFunction & MF ) { HII = MF . getSubtarget < HexagonSubtarget > ( ) . getInstrInfo ( ) ; HRI = MF . getSubtarget < HexagonSubtarget > ( ) . getRegisterInfo ( ) ; bool Changed = false ; for ( auto & I : MF ) Changed |= genMuxInBlock ( I ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> unsigned int mips_hard_regno_nregs ( int regno , machine_mode mode ) { if ( ST_REG_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + 3 ) / 4 ; if ( FP_REG_P ( regno ) ) { if ( MSA_SUPPORTED_MODE_P ( mode ) ) return 1 ; return ( GET_MODE_SIZE ( mode ) + UNITS_PER_FPREG - 1 ) / UNITS_PER_FPREG ; } return ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } </s>


"Dangerous instruction in branch delay slot!"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static unsigned long thumb1_compute_save_reg_mask ( void ) { unsigned long mask ; unsigned reg ; mask = 0 ; for ( reg = 0 ; reg < 12 ; reg ++ ) if ( df_regs_ever_live_p ( reg ) && callee_saved_reg_p ( reg ) ) mask |= 1 << reg ; if ( frame_pointer_needed ) mask |= 1 << HARD_FRAME_POINTER_REGNUM ; if ( flag_pic && ! TARGET_SINGLE_PIC_BASE && arm_pic_register != INVALID_REGNUM && crtl -> uses_pic_offset_table ) mask |= 1 << PIC_OFFSET_TABLE_REGNUM ; if ( ! frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0 ) mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM ; if ( mask & 0xff || thumb_force_lr_save ( ) ) mask |= ( 1 << LR_REGNUM ) ; if ( ( mask & 0xff ) == 0 && ( ( mask & 0x0f00 ) || TARGET_BACKTRACE ) ) { reg = thumb_find_work_register ( 1 << LAST_LO_REGNUM ) ; if ( reg * UNITS_PER_WORD <= ( unsigned ) arm_size_return_regs ( ) ) reg = LAST_LO_REGNUM ; if ( callee_saved_reg_p ( reg ) ) mask |= 1 << reg ; } if ( ( CALLER_INTERWORKING_SLOT_SIZE + ROUND_UP_WORD ( get_frame_size ( ) ) + crtl -> outgoing_args_size ) >= 504 ) { for ( reg = LAST_ARG_REGNUM + 1 ; reg <= LAST_LO_REGNUM ; reg ++ ) if ( mask & ( 1 << reg ) ) break ; if ( reg > LAST_LO_REGNUM ) { mask |= 1 << LAST_LO_REGNUM ; } } return mask ; } </s>

Compute a bit mask of which registers need to be saved on the stack for the current function .


<s>
const
char
*
arm_output_shift
(
rtx
*
operands
,
int
set_flags
)
{
char
pattern
[
100
]
;
static
const
char
flag_chars
[
3
]
=
{
'?'
,
'.'
,
'!'
}
;
const
char
*
shift
;
HOST_WIDE_INT
val
;
char
c
;
c
=
flag_chars
[
set_flags
]
;
shift
=
shift_op
(
operands
[
3
]
,
&
val
)
;
if
(
shift
)
{
if
(
val
!=
1
)
operands
[
2
]
=
GEN_INT
(
val
)
;
sprintf
(
pattern
,
"%s%%%c\t%%0, %%1, %%2"
,
shift
,
c
)
;
}
else
sprintf
(
pattern
,
"mov%%%c\t%%0, %%1"
,
c
)
;
output_asm_insn
(
pattern
,
operands
)
;
return
""
;
}
</s>

Output assembly for a shift instruction . SET_FLAGS determines how the instruction modifies the condition codes . 0 - Do not set condition codes . 1 - Set condition codes . 2 - Use smallest instruction .


<s> rtx gen_datalabel_ref ( rtx sym ) { const char * str ; if ( GET_CODE ( sym ) == LABEL_REF ) return gen_rtx_CONST ( GET_MODE ( sym ) , gen_rtx_UNSPEC ( GET_MODE ( sym ) , gen_rtvec ( 1 , sym ) , UNSPEC_DATALABEL ) ) ; gcc_assert ( GET_CODE ( sym ) == SYMBOL_REF ) ; str = XSTR ( sym , 0 ) ; str = IDENTIFIER_POINTER ( get_identifier ( str ) ) ; XSTR ( sym , 0 ) = str ; return sym ; } </s>

Prefix a symbol_ref name with `` datalabel '' .


<s>
bool
AArch64FrameLowering
::
hasFP
(
const
MachineFunction
&
MF
)
const
{
const
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
const
TargetRegisterInfo
*
RegInfo
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
assert
(
!
RegInfo
->
needsStackRealignment
(
MF
)
&&
"No stack realignment on AArch64!"
)
;
return
(
MFI
->
hasCalls
(
)
||
MFI
->
hasVarSizedObjects
(
)
||
MFI
->
isFrameAddressTaken
(
)
||
MFI
->
hasStackMap
(
)
||
MFI
->
hasPatchPoint
(
)
)
;
}
</s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static bool c6x_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { int size = int_size_in_bytes ( type ) ; return size > 2 * UNITS_PER_WORD || size == - 1 ; } </s>

Decide whether a type should be returned in memory ( true ) or in a register ( false ) . This is called by the macro TARGET_RETURN_IN_MEMORY .


<s> void RISCVInstrInfo :: buildOutlinedFrame ( MachineBasicBlock & MBB , MachineFunction & MF , const outliner :: OutlinedFunction & OF ) const { bool Changed = true ; while ( Changed ) { Changed = false ; auto I = MBB . begin ( ) ; auto E = MBB . end ( ) ; for ( ; I != E ; ++ I ) { if ( I -> isCFIInstruction ( ) ) { I -> removeFromParent ( ) ; Changed = true ; break ; } } } MBB . addLiveIn ( RISCV :: X5 ) ; MBB . insert ( MBB . end ( ) , BuildMI ( MF , DebugLoc ( ) , get ( RISCV :: JALR ) ) . addReg ( RISCV :: X0 , RegState :: Define ) . addReg ( RISCV :: X5 ) . addImm ( 0 ) ) ; } </s>

Insert a custom frame for outlined functions .


<s>
void
recordRelocation
(
MCAssembler
&
Asm
,
const
MCAsmLayout
&
Layout
,
const
MCFragment
*
Fragment
,
const
MCFixup
&
Fixup
,
MCValue
Target
,
bool
&
IsPCRel
,
uint64_t
&
FixedValue
)
override
{
assert
(
!
"Not implemented"
)
;
}
</s>


"Encountered a global variable kind that is "

Emit the specified global variable to the .s file .


<s> const CAHPSubtarget * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool TVMPassConfig :: addInstSelector ( ) { ( void ) TargetPassConfig :: addInstSelector ( ) ; addPass ( createTVMISelDag ( getTVMTargetMachine ( ) , getOptLevel ( ) ) ) ; addPass ( createTVMArgumentMove ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static bool csky_allocate_stack_slots_for_args ( void ) { return ! CSKY_FUNCTION_IS_NAKED ( get_csky_current_func_type ( ) ) ; } </s>


<s> void aarch64_expand_mov_immediate ( rtx dest , rtx imm ) { machine_mode mode = GET_MODE ( dest ) ; gcc_assert ( mode == SImode || mode == DImode ) ; if ( GET_CODE ( imm ) == SYMBOL_REF || GET_CODE ( imm ) == LABEL_REF || GET_CODE ( imm ) == CONST ) { rtx mem , base , offset ; enum aarch64_symbol_type sty ; split_const ( imm , & base , & offset ) ; sty = aarch64_classify_symbol ( base , offset , SYMBOL_CONTEXT_ADR ) ; switch ( sty ) { case SYMBOL_FORCE_TO_MEM : if ( offset != const0_rtx && targetm . cannot_force_const_mem ( mode , imm ) ) { gcc_assert ( can_create_pseudo_p ( ) ) ; base = aarch64_force_temporary ( mode , dest , base ) ; base = aarch64_add_offset ( mode , NULL , base , INTVAL ( offset ) ) ; aarch64_emit_move ( dest , base ) ; return ; } mem = force_const_mem ( ptr_mode , imm ) ; gcc_assert ( mem ) ; if ( mode != ptr_mode ) mem = gen_rtx_ZERO_EXTEND ( mode , mem ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , mem ) ) ; return ; case SYMBOL_SMALL_TLSGD : case SYMBOL_SMALL_TLSDESC : case SYMBOL_SMALL_GOTTPREL : case SYMBOL_SMALL_GOT : case SYMBOL_TINY_GOT : if ( offset != const0_rtx ) { gcc_assert ( can_create_pseudo_p ( ) ) ; base = aarch64_force_temporary ( mode , dest , base ) ; base = aarch64_add_offset ( mode , NULL , base , INTVAL ( offset ) ) ; aarch64_emit_move ( dest , base ) ; return ; } case SYMBOL_SMALL_TPREL : case SYMBOL_SMALL_ABSOLUTE : case SYMBOL_TINY_ABSOLUTE : aarch64_load_symref_appropriately ( dest , imm , sty ) ; return ; default : gcc_unreachable ( ) ; } } if ( ! CONST_INT_P ( imm ) ) { if ( GET_CODE ( imm ) == HIGH ) emit_insn ( gen_rtx_SET ( VOIDmode , dest , imm ) ) ; else { rtx mem = force_const_mem ( mode , imm ) ; gcc_assert ( mem ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , mem ) ) ; } return ; } aarch64_internal_mov_immediate ( dest , imm , true , GET_MODE ( dest ) ) ; } </s>

Set DEST to immediate IMM . For SVE vector modes , GEN_VEC_DUPLICATE is a pattern that can be used to set DEST to a replicated scalar element .


"perfect balance of FMUL/FMA chains between the "

"%d more FMUL/FMA chains scheduled on the second "

"%d more FMUL/FMA chains scheduled on the first "

Perform the renaming of all chains with FMUL or FMADD/FMSUB involved with the objective of keeping FPU pipeline balanced in term of instructions and having FMADD/FMSUB with dependencies on previous FMUL or FMADD/FMSUB be scheduled on the same pipeline .


<s> bool Z80PassConfig :: addInstSelector ( ) { addPass ( createZ80ISelDag ( getZ80TargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>


<s> bool M680x0DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & static_cast < const M680x0Subtarget & > ( MF . getSubtarget ( ) ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>


<s> bool PPCInstrInfo :: isUnpredicatedTerminator ( const MachineInstr * MI ) const { if ( ! MI -> isTerminator ( ) ) return false ; if ( MI -> isBranch ( ) && ! MI -> isBarrier ( ) ) return true ; return ! isPredicated ( MI ) ; } </s>

Returns true if the instruction is a terminator instruction that has not been predicated .


<s> void MipsSETargetLowering :: addMSAFloatType ( MVT :: SimpleValueType Ty , const TargetRegisterClass * RC ) { addRegisterClass ( Ty , RC ) ; for ( unsigned Opc = 0 ; Opc < ISD :: BUILTIN_OP_END ; ++ Opc ) setOperationAction ( Opc , Ty , Expand ) ; setOperationAction ( ISD :: LOAD , Ty , Legal ) ; setOperationAction ( ISD :: STORE , Ty , Legal ) ; setOperationAction ( ISD :: BITCAST , Ty , Legal ) ; if ( Ty != MVT :: v8f16 ) { setOperationAction ( ISD :: FADD , Ty , Legal ) ; setOperationAction ( ISD :: FDIV , Ty , Legal ) ; setOperationAction ( ISD :: FLOG2 , Ty , Legal ) ; setOperationAction ( ISD :: FMUL , Ty , Legal ) ; setOperationAction ( ISD :: FRINT , Ty , Legal ) ; setOperationAction ( ISD :: FSQRT , Ty , Legal ) ; setOperationAction ( ISD :: FSUB , Ty , Legal ) ; } } </s>

Enable MSA support for the given floating-point type and Register class .

Mips Mips MVT::SimpleValueType 0 ISD::BUILTIN_OP_END ISD::LOAD ISD::STORE ISD::BITCAST MVT::v8f16 ISD::FADD ISD::FDIV ISD::FLOG2 ISD::FMUL ISD::FRINT ISD::FSQRT ISD::FSUB


<s> static bool v2df_reduction_p ( rtx op ) { if ( GET_MODE ( op ) != V2DFmode ) return false ; enum rtx_code code = GET_CODE ( op ) ; if ( code != PLUS && code != SMIN && code != SMAX ) return false ; rtx concat = XEXP ( op , 0 ) ; if ( GET_CODE ( concat ) != VEC_CONCAT ) return false ; rtx select0 = XEXP ( concat , 0 ) ; rtx select1 = XEXP ( concat , 1 ) ; if ( GET_CODE ( select0 ) != VEC_SELECT || GET_CODE ( select1 ) != VEC_SELECT ) return false ; rtx reg0 = XEXP ( select0 , 0 ) ; rtx reg1 = XEXP ( select1 , 0 ) ; if ( ! rtx_equal_p ( reg0 , reg1 ) || ! REG_P ( reg0 ) ) return false ; rtx parallel0 = XEXP ( select0 , 1 ) ; rtx parallel1 = XEXP ( select1 , 1 ) ; if ( GET_CODE ( parallel0 ) != PARALLEL || GET_CODE ( parallel1 ) != PARALLEL ) return false ; if ( ! rtx_equal_p ( XVECEXP ( parallel0 , 0 , 0 ) , const1_rtx ) || ! rtx_equal_p ( XVECEXP ( parallel1 , 0 , 0 ) , const0_rtx ) ) return false ; return true ; } </s>

Return TRUE iff OP matches a V2DF reduction pattern . See the definition of vsx_reduc_ < VEC_reduc_name > _v2df in vsx.md .


<s> static bool mips_offset_within_alignment_p ( rtx x , HOST_WIDE_INT offset ) { HOST_WIDE_INT align ; align = SYMBOL_REF_DECL ( x ) ? DECL_ALIGN_UNIT ( SYMBOL_REF_DECL ( x ) ) : 1 ; return IN_RANGE ( offset , 0 , align - 1 ) ; } </s>

Return true if OFFSET is within the range [ 0 , ALIGN ) , where ALIGN is the alignment in bytes of SYMBOL_REF X .


<s> unsigned PPCTargetLowering :: getByValTypeAlignment ( Type * Ty ) const { if ( Subtarget . isDarwin ( ) ) return 4 ; unsigned Align = Subtarget . isPPC64 ( ) ? 8 : 4 ; if ( Subtarget . hasAltivec ( ) || Subtarget . hasQPX ( ) ) getMaxByValAlign ( Ty , Align , Subtarget . hasQPX ( ) ? 32 : 16 ) ; return Align ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


<s> static void mips_init_print_operand_punct ( void ) { const char * p ; for ( p = "()[]<>*#/?~.@^+$:!" ; * p ; p ++ ) mips_print_operand_punct [ ( unsigned char ) * p ] = true ; } </s>


<s> const XtensaInstrInfo * XtensaSubtarget :: getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> bool RISCVAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { if ( ! AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , OS ) ) return false ; const MachineOperand & MO = MI -> getOperand ( OpNo ) ; if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'z' : if ( MO . isImm ( ) && MO . getImm ( ) == 0 ) { OS << RISCVInstPrinter :: getRegisterName ( RISCV :: X0 ) ; return false ; } break ; case 'i' : if ( ! MO . isReg ( ) ) OS << 'i' ; return false ; } } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate : OS << MO . getImm ( ) ; return false ; case MachineOperand :: MO_Register : OS << RISCVInstPrinter :: getRegisterName ( MO . getReg ( ) ) ; return false ; case MachineOperand :: MO_GlobalAddress : PrintSymbolOperand ( MO , OS ) ; return false ; case MachineOperand :: MO_BlockAddress : { MCSymbol * Sym = GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; Sym -> print ( OS , MAI ) ; return false ; } default : break ; } return true ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> bool HexagonEvaluator :: evaluate ( const MachineInstr & BI , const CellMapType & Inputs , BranchTargetList & Targets , bool & FallsThru ) const { unsigned Opc = BI . getOpcode ( ) ; bool SimpleBranch = false ; bool Negated = false ; switch ( Opc ) { case Hexagon :: J2_jumpf : case Hexagon :: J2_jumpfpt : case Hexagon :: J2_jumpfnew : case Hexagon :: J2_jumpfnewpt : Negated = true ; case Hexagon :: J2_jumpt : case Hexagon :: J2_jumptpt : case Hexagon :: J2_jumptnew : case Hexagon :: J2_jumptnewpt : SimpleBranch = true ; break ; case Hexagon :: J2_jump : Targets . insert ( BI . getOperand ( 0 ) . getMBB ( ) ) ; FallsThru = false ; return true ; default : return false ; } if ( ! SimpleBranch ) return false ; RegisterRef PR = BI . getOperand ( 0 ) ; RegisterCell PC = getCell ( PR , Inputs ) ; const BT :: BitValue & Test = PC [ 0 ] ; if ( ! Test . is ( 0 ) && ! Test . is ( 1 ) ) return false ; if ( ! Test . is ( ! Negated ) ) { FallsThru = true ; return true ; } Targets . insert ( BI . getOperand ( 1 ) . getMBB ( ) ) ; FallsThru = false ; return true ; } </s>

evaluate - Evaluate Expr and append the resulting set to Elts .


<s> void function_expander :: add_fixed_operand ( rtx x ) { m_ops . safe_grow ( m_ops . length ( ) + 1 , true ) ; create_fixed_operand ( & m_ops . last ( ) , x ) ; } </s>

Add an operand that must be X . The only way of legitimizing an invalid X is to reload the address of a MEM .


Define the ` __builtin_va_list ' type for the ABI .


<s>
void
ScheduleDAGPostRA
::
dumpSchedule
(
)
const
{
for
(
MachineBasicBlock
::
iterator
MI
=
begin
(
)
,
ME
=
end
(
)
;
MI
!=
ME
;
++
MI
)
{
if
(
SUnit
*
SU
=
getSUnit
(
&
(
*
MI
)
)
)
SU
->
dump
(
this
)
;
else
if
(
MI
->
isDebugValue
(
)
)
dbgs
(
)
<<
"Debug Value\n"
;
else
dbgs
(
)
<<
"Missing SUnit\n"
;
}
}
</s>

Patmos
"Debug Value\n"
"Missing SUnit\n"


<s> static bool aarch64_composite_type_p ( const_tree type , machine_mode mode ) { if ( aarch64_short_vector_p ( type , mode ) ) return false ; if ( type && ( AGGREGATE_TYPE_P ( type ) || TREE_CODE ( type ) == COMPLEX_TYPE ) ) return true ; if ( mode == BLKmode || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_INT ) return true ; return false ; } </s>

Return TRUE if the type , as described by TYPE and MODE , is a composite type as described in AAPCS64 \S 4.3 . This includes aggregate , union and array types . The C99 floating-point complex types are also considered as composite types , according to AAPCS64 \S 7.1.1 . The complex integer types , which are GCC extensions and out of the scope of AAPCS64 , are treated as composite types here as well . Note that MODE itself is not sufficient in determining whether a type is such a composite type or not . This is because stor-layout.c : compute_record_mode may have already changed the MODE ( BLKmode ) of a RECORD_TYPE TYPE to some other mode . For example , a structure with only one field may have its MODE set to the mode of the field . Also an integer mode whose size matches the size of the RECORD_TYPE type may be used to substitute the original mode ( i.e . BLKmode ) in certain circumstances . In other words , MODE can not be solely relied on .


<s> MCSection * MipsTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , Align & Alignment ) const { if ( IsConstantInSmallSection ( DL , C , * TM ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: getSectionForConstant ( DL , Kind , C , Alignment ) ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> Sched :: Preference ARMTargetLowering :: getSchedulingPreference ( SDNode * N ) const { unsigned NumVals = N -> getNumValues ( ) ; if ( ! NumVals ) return Sched :: RegPressure ; for ( unsigned i = 0 ; i != NumVals ; ++ i ) { EVT VT = N -> getValueType ( i ) ; if ( VT . isFloatingPoint ( ) || VT . isVector ( ) ) return Sched :: Latency ; } if ( ! N -> isMachineOpcode ( ) ) return Sched :: RegPressure ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; const TargetInstrDesc & TID = TII -> get ( N -> getMachineOpcode ( ) ) ; if ( TID . mayLoad ( ) ) return Sched :: Latency ; const InstrItineraryData & Itins = getTargetMachine ( ) . getInstrItineraryData ( ) ; if ( ! Itins . isEmpty ( ) && Itins . getStageLatency ( TID . getSchedClass ( ) ) > 2 ) return Sched :: Latency ; return Sched :: RegPressure ; } </s>


<s> OperandMatchResultTy LanaiAsmParser :: tryParseRegister ( unsigned & RegNum , SMLoc & StartLoc , SMLoc & EndLoc ) { const AsmToken & Tok = getParser ( ) . getTok ( ) ; StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; std :: unique_ptr < LanaiOperand > Op = parseRegister ( true ) ; if ( Op == nullptr ) return MatchOperand_NoMatch ; RegNum = Op -> getReg ( ) ; return MatchOperand_Success ; } </s>

tryParseRegister - parse one register if possible


<s> static int s390_sched_score ( rtx_insn * insn ) { unsigned int mask = s390_get_sched_attrmask ( insn ) ; int score = 0 ; switch ( sched_state . group_state ) { case 0 : if ( ( mask & S390_SCHED_ATTR_MASK_CRACKED ) != 0 || ( mask & S390_SCHED_ATTR_MASK_EXPANDED ) != 0 ) score += 5 ; if ( ( mask & S390_SCHED_ATTR_MASK_GROUPALONE ) != 0 ) score += 10 ; break ; case 1 : if ( ( mask & S390_SCHED_ATTR_MASK_CRACKED ) == 0 && ( mask & S390_SCHED_ATTR_MASK_EXPANDED ) == 0 && ( mask & S390_SCHED_ATTR_MASK_GROUPALONE ) == 0 ) score += 10 ; if ( ( mask & S390_SCHED_ATTR_MASK_ENDGROUP ) == 0 ) score += 5 ; if ( sched_state . group_of_two && ( mask & S390_SCHED_ATTR_MASK_GROUPOFTWO ) != 0 ) score += 15 ; break ; case 2 : if ( ( mask & S390_SCHED_ATTR_MASK_CRACKED ) == 0 && ( mask & S390_SCHED_ATTR_MASK_EXPANDED ) == 0 && ( mask & S390_SCHED_ATTR_MASK_GROUPALONE ) == 0 ) score += 10 ; if ( ( mask & S390_SCHED_ATTR_MASK_ENDGROUP ) != 0 ) score += 10 ; if ( ( mask & S390_SCHED_ATTR_MASK_GROUPOFTWO ) != 0 ) score = MAX ( 0 , score - 15 ) ; break ; } if ( s390_tune >= PROCESSOR_2964_Z13 ) { int units , i ; unsigned unit_mask , m = 1 ; unit_mask = s390_get_unit_mask ( insn , & units ) ; gcc_assert ( units <= MAX_SCHED_UNITS ) ; for ( i = 0 ; i < units ; i ++ , m <<= 1 ) if ( m & unit_mask ) score += ( last_scheduled_unit_distance [ i ] [ sched_state . side ] * MAX_SCHED_MIX_SCORE / MAX_SCHED_MIX_DISTANCE ) ; int other_side = 1 - sched_state . side ; if ( s390_is_longrunning ( insn ) ) { if ( s390_is_fxd ( insn ) ) { if ( fxd_longrunning [ sched_state . side ] && fxd_longrunning [ other_side ] <= fxd_longrunning [ sched_state . side ] ) score = MAX ( 0 , score - 10 ) ; else if ( fxd_longrunning [ other_side ] >= fxd_longrunning [ sched_state . side ] ) score += 10 ; } if ( s390_is_fpd ( insn ) ) { if ( fpd_longrunning [ sched_state . side ] && fpd_longrunning [ other_side ] <= fpd_longrunning [ sched_state . side ] ) score = MAX ( 0 , score - 10 ) ; else if ( fpd_longrunning [ other_side ] >= fpd_longrunning [ sched_state . side ] ) score += 10 ; } } } return score ; } </s>

Return the scheduling score for INSN . The higher the score the better . The score is calculated from the OOO scheduling attributes of INSN and the scheduling state s390_sched_state .


<s> bool isCheapToSpeculateCttz ( ) const override { return true ; } </s>

Return true if it is cheap to speculate a call to intrinsic cttz .


<s>
StringRef
getPassName
(
)
const
override
{
return
"SPIRV Pre-GISel Legalizer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"stack frame not a multiple of octabyte: %wd"

Expands the function epilogue into RTX .


<s> bool PatmosPostRASchedStrategy :: isSchedulingBoundary ( const MachineInstr * MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) { if ( MI -> isDebugValue ( ) ) return false ; if ( MI -> getDesc ( ) . isTerminator ( ) || MI -> isLabel ( ) ) return true ; if ( MI -> isInlineAsm ( ) ) return true ; return MI -> isBarrier ( ) || MI -> isBranch ( ) || MI -> isCall ( ) || MI -> isReturn ( ) ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> MachineInstr * Z80oldInstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr & MI , ArrayRef < unsigned > Ops , MachineBasicBlock :: iterator InsertPt , MachineInstr & LoadMI , LiveIntervals * LIS ) const { return nullptr ; llvm_unreachable ( "Unimplemented" ) ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> bool AMDGPUSubtarget :: makeLIDRangeMetadata ( Instruction * I ) const { Function * Kernel = I -> getParent ( ) -> getParent ( ) ; unsigned MinSize = 0 ; unsigned MaxSize = getFlatWorkGroupSizes ( * Kernel ) . second ; bool IdQuery = false ; if ( auto * CI = dyn_cast < CallInst > ( I ) ) { const Function * F = CI -> getCalledFunction ( ) ; if ( F ) { unsigned Dim = UINT_MAX ; switch ( F -> getIntrinsicID ( ) ) { case Intrinsic :: amdgcn_workitem_id_x : case Intrinsic :: r600_read_tidig_x : IdQuery = true ; case Intrinsic :: r600_read_local_size_x : Dim = 0 ; break ; case Intrinsic :: amdgcn_workitem_id_y : case Intrinsic :: r600_read_tidig_y : IdQuery = true ; case Intrinsic :: r600_read_local_size_y : Dim = 1 ; break ; case Intrinsic :: amdgcn_workitem_id_z : case Intrinsic :: r600_read_tidig_z : IdQuery = true ; case Intrinsic :: r600_read_local_size_z : Dim = 2 ; break ; default : break ; } if ( Dim <= 3 ) { if ( auto Node = Kernel -> getMetadata ( "reqd_work_group_size" ) ) if ( Node -> getNumOperands ( ) == 3 ) MinSize = MaxSize = mdconst :: extract < ConstantInt > ( Node -> getOperand ( Dim ) ) -> getZExtValue ( ) ; } } } if ( ! MaxSize ) return false ; if ( IdQuery ) MinSize = 0 ; else ++ MaxSize ; MDBuilder MDB ( I -> getContext ( ) ) ; MDNode * MaxWorkGroupSizeRange = MDB . createRange ( APInt ( 32 , MinSize ) , APInt ( 32 , MaxSize ) ) ; I -> setMetadata ( LLVMContext :: MD_range , MaxWorkGroupSizeRange ) ; return true ; } </s>

Creates value range metadata on an workitemid . * intrinsic call or load .


<s> unsigned MipsFunctionInfo :: getGlobalBaseReg ( ) { if ( GlobalBaseReg ) return GlobalBaseReg ; const MipsSubtarget & ST = MF . getTarget ( ) . getSubtarget < MipsSubtarget > ( ) ; const TargetRegisterClass * RC = ST . isABI_N64 ( ) ? ( const TargetRegisterClass * ) & Mips :: CPU64RegsRegClass : ( const TargetRegisterClass * ) & Mips :: CPURegsRegClass ; return GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

Mips Mips Mips Mips Mips::CPU64RegsRegClass Mips::CPURegsRegClass


"X86-64 PIC uses RIP relative addressing"


<s> const GBZ80RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


"z/Architecture mode not supported on %s"

"64-bit ABI not supported in ESA/390 mode"

"-mbackchain -mpacked-stack -mhard-float are not supported "

"-mstack-size implies use of -mstack-guard"

"stack size must be greater than the stack guard value"

"stack size must not be greater than 64k"

"-mstack-guard implies use of -mstack-size"

Set global variables as needed for the options enabled .


"Only base registers and frame indices are supported."

Returns true if the two given memory operations should be scheduled adjacent .


<s> void ARMTargetStreamer :: emitCurrentConstantPool ( ) { ConstantPools -> emitForCurrentSection ( Streamer ) ; } </s>

Callback used to implement the .ltorg directive .


<s> bool ARMAsmParser :: ParseInstruction ( const StringRef & Name , SMLoc NameLoc , SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { Operands . push_back ( new ARMOperand ( ARMOperand :: CreateToken ( Name ) ) ) ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { ARMOperand Op ; if ( ParseOperand ( Op ) ) return true ; Operands . push_back ( new ARMOperand ( Op ) ) ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( ParseOperand ( Op ) ) return true ; Operands . push_back ( new ARMOperand ( Op ) ) ; } } return false ; } </s>

ParseInstruction - Parse one assembly instruction .


<s> MachineBasicBlock :: iterator RISCVInstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , const outliner :: Candidate & C ) const { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( RISCV :: PseudoCALLReg ) , RISCV :: X5 ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) , 0 , RISCVII :: MO_CALL ) ) ; return It ; } </s>

Insert a call to an outlined function into the program .


<s> static void pdp11_conditional_register_usage ( void ) { int i ; HARD_REG_SET x ; if ( ! TARGET_FPU ) { COPY_HARD_REG_SET ( x , reg_class_contents [ ( int ) FPU_REGS ] ) ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( x , i ) ) fixed_regs [ i ] = call_used_regs [ i ] = 1 ; } if ( TARGET_AC0 ) call_used_regs [ AC0_REGNUM ] = 1 ; if ( TARGET_UNIX_ASM ) { reg_names [ 8 ] = "fr0" ; reg_names [ 9 ] = "fr1" ; reg_names [ 10 ] = "fr2" ; reg_names [ 11 ] = "fr3" ; reg_names [ 12 ] = "fr4" ; reg_names [ 13 ] = "fr5" ; } } </s>

Make sure everything 's fine if we * do n't * have an FPU . This assumes that putting a register in fixed_regs will keep the compiler 's mitts completely off it . We do n't bother to zero it out of register classes . Also fix incompatible register naming with the UNIX assembler .


<s> int aarch_crypto_can_dual_issue ( rtx_insn * producer_insn , rtx_insn * consumer_insn ) { rtx producer_set , consumer_set ; rtx producer_src , consumer_src ; producer_set = single_set ( producer_insn ) ; consumer_set = single_set ( consumer_insn ) ; producer_src = producer_set ? SET_SRC ( producer_set ) : NULL ; consumer_src = consumer_set ? SET_SRC ( consumer_set ) : NULL ; if ( producer_src && consumer_src && GET_CODE ( producer_src ) == UNSPEC && GET_CODE ( consumer_src ) == UNSPEC && ( ( XINT ( producer_src , 1 ) == UNSPEC_AESE && XINT ( consumer_src , 1 ) == UNSPEC_AESMC ) || ( XINT ( producer_src , 1 ) == UNSPEC_AESD && XINT ( consumer_src , 1 ) == UNSPEC_AESIMC ) ) ) { unsigned int regno = REGNO ( SET_DEST ( producer_set ) ) ; return ( REGNO ( SET_DEST ( consumer_set ) ) == regno || ! reload_completed ) && REGNO ( XVECEXP ( consumer_src , 0 , 0 ) ) == regno ; } return 0 ; } </s>

In ARMv8-A there 's a general expectation that AESE/AESMC and AESD/AESIMC sequences of the form : AESE Vn , _ AESMC Vn , Vn will issue both instructions in a single cycle on super-scalar implementations . This function identifies such pairs .


<s> bool ix86_dep_by_shift_count ( const_rtx set_insn , const_rtx use_insn ) { return ix86_dep_by_shift_count_body ( PATTERN ( set_insn ) , PATTERN ( use_insn ) ) ; } </s>

Return true if destination reg of SET_INSN is shift count of USE_INSN .


<s> M68K_CONST_METHOD m68k_const_method ( HOST_WIDE_INT i ) { unsigned u ; if ( USE_MOVQ ( i ) ) return MOVQ ; if ( ! TARGET_COLDFIRE ) { if ( USE_MOVQ ( i ^ 0xff ) ) return NOTB ; if ( USE_MOVQ ( i ^ 0xffff ) ) return NOTW ; if ( i == - 65408 ) return NEGW ; } u = i ; if ( USE_MOVQ ( ( u >> 16 ) | ( u << 16 ) ) ) return SWAP ; if ( TARGET_ISAB ) { if ( i >= 0 && i <= 65535 ) return MVZ ; if ( i >= - 32768 && i <= 32767 ) return MVS ; } return MOVL ; } </s>

Return the type of move that should be used for integer I .


<s> int MipsSEFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; if ( MFI . isFixedObjectIndex ( FI ) ) FrameReg = hasFP ( MF ) ? ABI . GetFramePtr ( ) : ABI . GetStackPtr ( ) ; else FrameReg = hasBP ( MF ) ? ABI . GetBasePtr ( ) : ABI . GetStackPtr ( ) ; return MFI . getObjectOffset ( FI ) + MFI . getStackSize ( ) - getOffsetOfLocalArea ( ) + MFI . getOffsetAdjustment ( ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> HOST_WIDE_INT const_vector_elt_as_int ( rtx op , unsigned int elt ) { rtx tmp ; gcc_assert ( GET_MODE ( op ) != V2DImode && GET_MODE ( op ) != V2DFmode ) ; tmp = CONST_VECTOR_ELT ( op , elt ) ; if ( GET_MODE ( op ) == V4SFmode || GET_MODE ( op ) == V2SFmode ) tmp = gen_lowpart ( SImode , tmp ) ; return INTVAL ( tmp ) ; } </s>

Interpret element ELT of the CONST_VECTOR OP as an integer value . If the mode of OP is MODE_VECTOR_INT , this simply returns the corresponding element of the vector , but for V4SFmode , the corresponding `` float '' is interpreted as an SImode integer .


<s> unsigned getReg ( ) const override { return 0 ; } </s>

Returns the register associated with this edge .


"r%d has non convertible definition in insn %d\n"

"Removing insn %d from candidates list\n"

The DImode version of remove_non_convertible_regs .


<s>
void
MipsRegisterBankInfo
::
applyMappingImpl
(
const
OperandsMapper
&
OpdMapper
)
const
{
MachineInstr
&
MI
=
OpdMapper
.
getMI
(
)
;
InstListTy
NewInstrs
;
MachineIRBuilder
B
(
MI
)
;
MachineFunction
*
MF
=
MI
.
getMF
(
)
;
MachineRegisterInfo
&
MRI
=
OpdMapper
.
getMRI
(
)
;
InstManager
NewInstrObserver
(
NewInstrs
)
;
GISelObserverWrapper
WrapperObserver
(
&
NewInstrObserver
)
;
LegalizerHelper
Helper
(
*
MF
,
WrapperObserver
,
B
)
;
LegalizationArtifactCombiner
ArtCombiner
(
B
,
MF
->
getRegInfo
(
)
,
*
MF
->
getSubtarget
(
)
.
getLegalizerInfo
(
)
)
;
switch
(
MI
.
getOpcode
(
)
)
{
case
TargetOpcode
::
G_LOAD
:
case
TargetOpcode
::
G_STORE
:
case
TargetOpcode
::
G_PHI
:
case
TargetOpcode
::
G_SELECT
:
{
Helper
.
narrowScalar
(
MI
,
0
,
LLT
::
scalar
(
32
)
)
;
while
(
!
NewInstrs
.
empty
(
)
)
{
MachineInstr
*
NewMI
=
NewInstrs
.
pop_back_val
(
)
;
if
(
NewMI
->
getOpcode
(
)
==
TargetOpcode
::
G_UNMERGE_VALUES
)
{
SmallVector
<
MachineInstr
*
,
2
>
DeadInstrs
;
ArtCombiner
.
tryCombineMerges
(
*
NewMI
,
DeadInstrs
)
;
for
(
MachineInstr
*
DeadMI
:
DeadInstrs
)
DeadMI
->
eraseFromParent
(
)
;
}
else
if
(
NewMI
->
getOpcode
(
)
==
TargetOpcode
::
G_MERGE_VALUES
)
continue
;
else
for
(
auto
Op
:
NewMI
->
operands
(
)
)
{
if
(
Op
.
isReg
(
)
)
{
assert
(
MRI
.
getType
(
Op
.
getReg
(
)
)
.
getSizeInBits
(
)
==
32
&&
"Only 32 bit gprb is handled here.\n"
)
;
MRI
.
setRegBank
(
Op
.
getReg
(
)
,
getRegBank
(
Mips
::
GPRBRegBankID
)
)
;
}
}
}
return
;
}
case
TargetOpcode
::
G_UNMERGE_VALUES
:
{
SmallVector
<
MachineInstr
*
,
2
>
DeadInstrs
;
ArtCombiner
.
tryCombineMerges
(
MI
,
DeadInstrs
)
;
for
(
MachineInstr
*
DeadMI
:
DeadInstrs
)
DeadMI
->
eraseFromParent
(
)
;
return
;
}
default
:
break
;
}
return
applyDefaultMapping
(
OpdMapper
)
;
}
</s>


<s> bool LanaiAsmParser :: ParseDirective ( AsmToken ) { return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> static int m68k_return_pops_args ( tree fundecl , tree funtype , int size ) { return ( ( TARGET_RTD && ( ! fundecl || TREE_CODE ( fundecl ) != IDENTIFIER_NODE ) && ( ! stdarg_p ( funtype ) ) ) ? size : 0 ) ; } </s>

On the 68000 , the RTS insn can not pop anything . On the 68010 , the RTD insn may be used to pop them if the number of args is fixed , but if the number is variable then the caller must pop them all . RTD ca n't be used for library calls now because the library is compiled with the Unix compiler . Use of RTD is a selectable option , since it is incompatible with standard Unix calling sequences . If the option is not selected , the caller must always pop the args .


<s> bool TOYPassConfig :: addPreISel ( ) { return false ; } </s>


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , Options ) , JITInfo ( ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = Subtarget . isTargetHardFloat ( ) ? FloatABI :: Hard : FloatABI :: Soft ; } </s>


<s>
const
char
*
getPassName
(
)
const
{
return
"Merge internal globals"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
unsigned
HexagonInstrInfo
::
getSize
(
const
MachineInstr
&
MI
)
const
{
if
(
MI
.
isDebugInstr
(
)
||
MI
.
isPosition
(
)
)
return
0
;
unsigned
Size
=
MI
.
getDesc
(
)
.
getSize
(
)
;
if
(
!
Size
)
Size
=
HEXAGON_INSTR_SIZE
;
if
(
isConstExtended
(
MI
)
||
isExtended
(
MI
)
)
Size
+=
HEXAGON_INSTR_SIZE
;
if
(
BranchRelaxAsmLarge
&&
MI
.
getOpcode
(
)
==
Hexagon
::
INLINEASM
)
{
const
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
const
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
const
MCAsmInfo
*
MAI
=
MF
->
getTarget
(
)
.
getMCAsmInfo
(
)
;
unsigned
NumDefs
=
0
;
for
(
;
MI
.
getOperand
(
NumDefs
)
.
isReg
(
)
&&
MI
.
getOperand
(
NumDefs
)
.
isDef
(
)
;
++
NumDefs
)
assert
(
NumDefs
!=
MI
.
getNumOperands
(
)
2
&&
"No asm string?"
)
;
assert
(
MI
.
getOperand
(
NumDefs
)
.
isSymbol
(
)
&&
"No asm string?"
)
;
const
char
*
AsmStr
=
MI
.
getOperand
(
NumDefs
)
.
getSymbolName
(
)
;
Size
=
getInlineAsmLength
(
AsmStr
,
*
MAI
)
;
}
return
Size
;
}
</s>

Return the number of bytes in the encoding of this instruction , or zero if the encoding size can not be known from the opcode .


<s> TargetPassConfig * RISCVTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new RISCVPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> void mn10300_gen_multiple_store ( int mask ) { if ( mask != 0 ) { int i ; int count ; rtx par ; int pari ; count = 0 ; for ( i = 0 ; i <= LAST_EXTENDED_REGNUM ; i ++ ) if ( ( mask & ( 1 << i ) ) != 0 ) count += 1 ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count + 1 ) ) ; XVECEXP ( par , 0 , 0 ) = gen_rtx_SET ( SImode , stack_pointer_rtx , gen_rtx_PLUS ( SImode , stack_pointer_rtx , GEN_INT ( - count * 4 ) ) ) ; pari = 1 ; for ( i = LAST_EXTENDED_REGNUM ; i >= 0 ; i -- ) if ( ( mask & ( 1 << i ) ) != 0 ) { rtx address = gen_rtx_PLUS ( SImode , stack_pointer_rtx , GEN_INT ( - pari * 4 ) ) ; XVECEXP ( par , 0 , pari ) = gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( SImode , address ) , gen_rtx_REG ( SImode , i ) ) ; pari += 1 ; } par = emit_insn ( par ) ; RTX_FRAME_RELATED_P ( par ) = 1 ; } } </s>

Generate an instruction that pushes several registers onto the stack . Register K will be saved if bit K in MASK is set . The function does nothing if MASK is zero . To be compatible with the `` movm '' instruction , the lowest-numbered register must be stored in the lowest slot . If MASK is the set { R1 , ... , RN } , where R1 ... RN are ordered least first , the generated instruction will have the form : ( parallel ( set ( reg : SI 9 ) ( plus : SI ( reg : SI 9 ) ( const_int -N * 4 ) ) ) ( set ( mem : SI ( plus : SI ( reg : SI 9 ) ( const_int -1 * 4 ) ) ) ( reg : SI RN ) ) ... ( set ( mem : SI ( plus : SI ( reg : SI 9 ) ( const_int -N * 4 ) ) ) ( reg : SI R1 ) ) )


<s> rtx m32c_return_addr_rtx ( int count ) { enum machine_mode mode ; int offset ; rtx ra_mem ; if ( count ) return NULL_RTX ; if ( TARGET_A24 ) { mode = SImode ; offset = 4 ; } else { mode = HImode ; offset = 2 ; } ra_mem = gen_rtx_MEM ( mode , plus_constant ( gen_rtx_REG ( Pmode , FP_REGNO ) , offset ) ) ; return copy_to_mode_reg ( mode , ra_mem ) ; } </s>

Implements RETURN_ADDR_RTX . Note that R8C and M16C push 24 bits ( yes , THREE bytes ) onto the stack for the return address , but we do n't support pointers bigger than 16 bits on those chips . This will likely wreak havoc with exception unwinding . FIXME .


<s> static void mcore_setup_incoming_varargs ( cumulative_args_t args_so_far_v , const function_arg_info & arg , int * ptr_pretend_size ATTRIBUTE_UNUSED , int second_time ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * args_so_far = get_cumulative_args ( args_so_far_v ) ; current_function_anonymous_args = 1 ; number_of_regs_before_varargs = * args_so_far + mcore_num_arg_regs ( arg . mode , arg . type ) ; number_of_regs_before_varargs = * args_so_far ; if ( number_of_regs_before_varargs > NPARM_REGS ) number_of_regs_before_varargs = NPARM_REGS ; } </s>

Keep track of some information about varargs for the prolog .


<s>
int
AArch64AsmParser
::
tryParseRegister
(
)
{
const
AsmToken
&
Tok
=
Parser
.
getTok
(
)
;
assert
(
Tok
.
is
(
AsmToken
::
Identifier
)
&&
"Token is not an Identifier"
)
;
std
::
string
lowerCase
=
Tok
.
getString
(
)
.
lower
(
)
;
unsigned
RegNum
=
matchRegisterNameAlias
(
lowerCase
,
false
)
;
if
(
RegNum
==
0
)
RegNum
=
StringSwitch
<
unsigned
>
(
lowerCase
)
.
Case
(
"fp"
,
AArch64
::
FP
)
.
Case
(
"lr"
,
AArch64
::
LR
)
.
Case
(
"x31"
,
AArch64
::
XZR
)
.
Case
(
"w31"
,
AArch64
::
WZR
)
.
Default
(
0
)
;
if
(
RegNum
==
0
)
return
1
;
Parser
.
Lex
(
)
;
return
RegNum
;
}
</s>

tryParseRegister - parse one register if possible


<s> bool pa_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { return ( int_size_in_bytes ( type ) > ( TARGET_64BIT ? 16 : 8 ) || int_size_in_bytes ( type ) <= 0 ) ; } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


<s> void Thumb1RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; if ( ! TFI -> hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; DebugLoc dl = Old -> getDebugLoc ( ) ; unsigned Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { unsigned Align = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; Amount = ( Amount + Align - 1 ) / Align * Align ; unsigned Opc = Old -> getOpcode ( ) ; if ( Opc == ARM :: ADJCALLSTACKDOWN || Opc == ARM :: tADJCALLSTACKDOWN ) { emitSPUpdate ( MBB , I , TII , dl , * this , - Amount ) ; } else { assert ( Opc == ARM :: ADJCALLSTACKUP || Opc == ARM :: tADJCALLSTACKUP ) ; emitSPUpdate ( MBB , I , TII , dl , * this , Amount ) ; } } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> void mips_expand_conditional_trap ( rtx comparison ) { rtx op0 , op1 ; machine_mode mode ; enum rtx_code code ; code = GET_CODE ( comparison ) ; switch ( code ) { case GT : case LE : case GTU : case LEU : code = swap_condition ( code ) ; op0 = XEXP ( comparison , 1 ) ; op1 = XEXP ( comparison , 0 ) ; break ; default : op0 = XEXP ( comparison , 0 ) ; op1 = XEXP ( comparison , 1 ) ; break ; } mode = GET_MODE ( XEXP ( comparison , 0 ) ) ; op0 = force_reg ( mode , op0 ) ; if ( ! ( ISA_HAS_COND_TRAPI ? arith_operand ( op1 , mode ) : reg_or_0_operand ( op1 , mode ) ) ) op1 = force_reg ( mode , op1 ) ; emit_insn ( gen_rtx_TRAP_IF ( VOIDmode , gen_rtx_fmt_ee ( code , mode , op0 , op1 ) , const0_rtx ) ) ; } </s>

Perform the comparison in COMPARISON , then trap if the condition holds .


<s> static void mcore_print_operand ( FILE * stream , rtx x , int code ) { switch ( code ) { case 'N' : if ( INTVAL ( x ) == - 1 ) fprintf ( asm_out_file , "32" ) ; else fprintf ( asm_out_file , "%d" , exact_log2 ( INTVAL ( x ) + 1 ) ) ; break ; case 'P' : fprintf ( asm_out_file , "%d" , exact_log2 ( INTVAL ( x ) & 0xffffffff ) ) ; break ; case 'Q' : fprintf ( asm_out_file , "%d" , exact_log2 ( ~ INTVAL ( x ) ) ) ; break ; case 'O' : fprintf ( asm_out_file , HOST_WIDE_INT_PRINT_DEC , INTVAL ( x ) ) ; break ; case 'M' : fprintf ( asm_out_file , HOST_WIDE_INT_PRINT_DEC , - INTVAL ( x ) ) ; break ; case 'R' : switch ( GET_CODE ( x ) ) { case REG : fputs ( reg_names [ REGNO ( x ) + 1 ] , ( stream ) ) ; break ; case MEM : mcore_print_operand_address ( stream , XEXP ( adjust_address ( x , SImode , 4 ) , 0 ) ) ; break ; default : gcc_unreachable ( ) ; } break ; case 'U' : fprintf ( asm_out_file , "%s-%s" , reg_names [ REGNO ( x ) ] , reg_names [ REGNO ( x ) + 3 ] ) ; break ; case 'x' : fprintf ( asm_out_file , HOST_WIDE_INT_PRINT_HEX , INTVAL ( x ) ) ; break ; case 'X' : fprintf ( asm_out_file , HOST_WIDE_INT_PRINT_DEC , 3 - INTVAL ( x ) / 8 ) ; break ; default : switch ( GET_CODE ( x ) ) { case REG : fputs ( reg_names [ REGNO ( x ) ] , ( stream ) ) ; break ; case MEM : output_address ( XEXP ( x , 0 ) ) ; break ; default : output_addr_const ( stream , x ) ; break ; } break ; } } </s>

Print operand x ( an rtx ) in assembler syntax to file stream according to modifier code . ' R ' print the next register or memory location along , ie the lsw in a double word value ' O ' print a constant without the # 'M ' print a constant as its negative ' P ' print log2 of a power of two ' Q ' print log2 of an inverse of a power of two ' U ' print register for ldm/stm instruction ' X ' print byte number for xtrbN instruction .


<s> static rtx frv_expand_binopimm_builtin ( enum insn_code icode , tree call , rtx target ) { rtx pat ; rtx op0 = frv_read_argument ( call , 0 ) ; rtx op1 = frv_read_argument ( call , 1 ) ; if ( ! frv_check_constant_argument ( icode , 2 , op1 ) ) return NULL_RTX ; target = frv_legitimize_target ( icode , target ) ; op0 = frv_legitimize_argument ( icode , 1 , op0 ) ; pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return target ; } </s>

Expand builtins that take two operands and the second is immediate .


<s> const RISCVRegisterInfo * getRegisterInfo ( ) const override { return & RegInfo ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
bool
HexagonOptAddrMode
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
bool
Changed
=
false
;
auto
&
HST
=
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
HII
=
HST
.
getInstrInfo
(
)
;
HRI
=
HST
.
getRegisterInfo
(
)
;
const
auto
&
MDF
=
getAnalysis
<
MachineDominanceFrontier
>
(
)
;
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
const
TargetOperandInfo
TOI
(
*
HII
)
;
DataFlowGraph
G
(
MF
,
*
HII
,
*
HRI
,
*
MDT
,
MDF
,
TOI
)
;
G
.
build
(
BuildOptions
::
KeepDeadPhis
)
;
DFG
=
&
G
;
Liveness
L
(
*
MRI
,
*
DFG
)
;
L
.
computePhiInfo
(
)
;
LV
=
&
L
;
Deleted
.
clear
(
)
;
NodeAddr
<
FuncNode
*
>
FA
=
DFG
->
getFunc
(
)
;
DEBUG
(
dbgs
(
)
<<
"==== [RefMap#]=====:\n "
<<
Print
<
NodeAddr
<
FuncNode
*
>>
(
FA
,
*
DFG
)
<<
"\n"
)
;
for
(
NodeAddr
<
BlockNode
*
>
BA
:
FA
.
Addr
->
members
(
*
DFG
)
)
Changed
|=
processBlock
(
BA
)
;
for
(
auto
MI
:
Deleted
)
MI
->
eraseFromParent
(
)
;
if
(
Changed
)
{
G
.
build
(
)
;
L
.
computeLiveIns
(
)
;
L
.
resetLiveIns
(
)
;
L
.
resetKills
(
)
;
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

Hexagon
Hexagon
Hexagon
"==== [RefMap#]=====:\n "
"\n"


<s> const uint16_t * OpenRISCRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const TargetFrameLowering * TFI = MF -> getTarget ( ) . getFrameLowering ( ) ; return ( TFI -> hasFP ( * MF ) ? CSR_FP_SaveList : CSR_SaveList ) ; } </s>


<s> bool HexagonCommonGEP :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; for ( Function :: iterator A = F . begin ( ) , Z = F . end ( ) ; A != Z ; ++ A ) for ( BasicBlock :: iterator I = A -> begin ( ) , E = A -> end ( ) ; I != E ; ++ I ) if ( isa < InvokeInst > ( I ) || isa < LandingPadInst > ( I ) ) return false ; Fn = & F ; DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; PDT = & getAnalysis < PostDominatorTreeWrapperPass > ( ) . getPostDomTree ( ) ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; Ctx = & F . getContext ( ) ; Nodes . clear ( ) ; Uses . clear ( ) ; NodeOrder . clear ( ) ; SpecificBumpPtrAllocator < GepNode > Allocator ; Mem = & Allocator ; collect ( ) ; common ( ) ; NodeToValueMap Loc ; computeNodePlacement ( Loc ) ; materialize ( Loc ) ; removeDeadCode ( ) ; verifyFunction ( F ) ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> AArch64Subtarget :: AArch64Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasFPARMv8 ( false ) , HasNEON ( false ) , HasCrypto ( false ) , HasCRC ( false ) , HasZeroCycleRegMove ( false ) , HasZeroCycleZeroing ( false ) , CPUString ( CPU ) , TargetTriple ( TT ) , DL ( isTargetMachO ( ) ? "e-m:o-i64:64-i128:128-n32:64-S128" : ( LittleEndian ? "e-m:e-i64:64-i128:128-n32:64-S128" : "E-m:e-i64:64-i128:128-n32:64-S128" ) ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS ) ) , TSInfo ( & DL ) , TLInfo ( TM ) { } </s>

This constructor initializes the data members to match that of the specified triple .


<s> enum reg_class alpha_preferred_reload_class ( rtx x , enum reg_class rclass ) { if ( x == CONST0_RTX ( GET_MODE ( x ) ) ) return rclass ; if ( CONST_INT_P ( x ) || GET_CODE ( x ) == CONST_DOUBLE || GET_CODE ( x ) == CONST_VECTOR ) { if ( rclass == FLOAT_REGS ) return NO_REGS ; if ( rclass == ALL_REGS ) return GENERAL_REGS ; return rclass ; } if ( CONSTANT_P ( x ) ) return ( rclass == ALL_REGS ? GENERAL_REGS : rclass ) ; return rclass ; } </s>

On the Alpha , all ( non-symbolic ) constants except zero go into a floating-point register via memory . Note that we can not return anything that is not a subset of CLASS , and that some symbolic constants can not be dropped to memory .


<s> bool X86InstrInfo :: isCoalescableExtInstr ( const MachineInstr & MI , unsigned & SrcReg , unsigned & DstReg , unsigned & SubIdx ) const { switch ( MI . getOpcode ( ) ) { default : break ; case X86 :: MOVSX16rr8 : case X86 :: MOVZX16rr8 : case X86 :: MOVSX32rr8 : case X86 :: MOVZX32rr8 : case X86 :: MOVSX64rr8 : case X86 :: MOVZX64rr8 : if ( ! TM . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ) return false ; case X86 :: MOVSX32rr16 : case X86 :: MOVZX32rr16 : case X86 :: MOVSX64rr16 : case X86 :: MOVZX64rr16 : case X86 :: MOVSX64rr32 : case X86 :: MOVZX64rr32 : { if ( MI . getOperand ( 0 ) . getSubReg ( ) || MI . getOperand ( 1 ) . getSubReg ( ) ) return false ; SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; DstReg = MI . getOperand ( 0 ) . getReg ( ) ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( 0 ) ; case X86 :: MOVSX16rr8 : case X86 :: MOVZX16rr8 : case X86 :: MOVSX32rr8 : case X86 :: MOVZX32rr8 : case X86 :: MOVSX64rr8 : case X86 :: MOVZX64rr8 : SubIdx = X86 :: sub_8bit ; break ; case X86 :: MOVSX32rr16 : case X86 :: MOVZX32rr16 : case X86 :: MOVSX64rr16 : case X86 :: MOVZX64rr16 : SubIdx = X86 :: sub_16bit ; break ; case X86 :: MOVSX64rr32 : case X86 :: MOVZX64rr32 : SubIdx = X86 :: sub_32bit ; break ; } return true ; } } return false ; } </s>

isCoalescableExtInstr - Return true if the instruction is a `` coalescable '' extension instruction .


<s> MVT BPFTargetLowering :: getScalarShiftAmountTy ( const DataLayout & DL , EVT VT ) const { return ( getHasAlu32 ( ) && VT == MVT :: i32 ) ? MVT :: i32 : MVT :: i64 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> ScheduleHazardRecognizer :: HazardType GCNHazardRecognizer :: getHazardType ( SUnit * SU , int Stalls ) { MachineInstr * MI = SU -> getInstr ( ) ; if ( MI -> isBundle ( ) ) return NoHazard ; if ( SIInstrInfo :: isSMRD ( * MI ) && checkSMRDHazards ( MI ) > 0 ) return NoopHazard ; if ( ( SIInstrInfo :: isVMEM ( * MI ) || SIInstrInfo :: isFLAT ( * MI ) ) && checkVMEMHazards ( MI ) > 0 ) return NoopHazard ; if ( ST . hasNSAtoVMEMBug ( ) && checkNSAtoVMEMHazard ( MI ) > 0 ) return NoopHazard ; if ( checkFPAtomicToDenormModeHazard ( MI ) > 0 ) return NoopHazard ; if ( ST . hasNoDataDepHazard ( ) ) return NoHazard ; if ( SIInstrInfo :: isVALU ( * MI ) && checkVALUHazards ( MI ) > 0 ) return NoopHazard ; if ( SIInstrInfo :: isDPP ( * MI ) && checkDPPHazards ( MI ) > 0 ) return NoopHazard ; if ( isDivFMas ( MI -> getOpcode ( ) ) && checkDivFMasHazards ( MI ) > 0 ) return NoopHazard ; if ( isRWLane ( MI -> getOpcode ( ) ) && checkRWLaneHazards ( MI ) > 0 ) return NoopHazard ; if ( isSGetReg ( MI -> getOpcode ( ) ) && checkGetRegHazards ( MI ) > 0 ) return NoopHazard ; if ( isSSetReg ( MI -> getOpcode ( ) ) && checkSetRegHazards ( MI ) > 0 ) return NoopHazard ; if ( isRFE ( MI -> getOpcode ( ) ) && checkRFEHazards ( MI ) > 0 ) return NoopHazard ; if ( ST . hasReadM0MovRelInterpHazard ( ) && ( TII . isVINTRP ( * MI ) || isSMovRel ( MI -> getOpcode ( ) ) ) && checkReadM0Hazards ( MI ) > 0 ) return NoopHazard ; if ( ST . hasReadM0SendMsgHazard ( ) && isSendMsgTraceDataOrGDS ( TII , * MI ) && checkReadM0Hazards ( MI ) > 0 ) return NoopHazard ; if ( SIInstrInfo :: isMAI ( * MI ) && checkMAIHazards ( MI ) > 0 ) return NoopHazard ; if ( MI -> mayLoadOrStore ( ) && checkMAILdStHazards ( MI ) > 0 ) return NoopHazard ; if ( MI -> isInlineAsm ( ) && checkInlineAsmHazards ( MI ) > 0 ) return NoopHazard ; return NoHazard ; } </s>

getHazardType - Return the hazard type of emitting this node .


<s> static void push_regs ( HARD_REG_SET * mask , bool interrupt_handler ) { bool skip_fpscr = false ; for ( int i = interrupt_handler ? LAST_BANKED_REG + 1 : 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { if ( i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD && hard_reg_set_intersect_p ( * mask , reg_class_contents [ DF_REGS ] ) ) { HARD_REG_SET unsaved ; push ( FPSCR_REG ) ; COMPL_HARD_REG_SET ( unsaved , * mask ) ; fpscr_set_from_mem ( NORMAL_MODE ( FP_MODE ) , unsaved ) ; skip_fpscr = true ; } if ( i != PR_REG && ( i != FPSCR_REG || ! skip_fpscr ) && TEST_HARD_REG_BIT ( * mask , i ) ) { if ( ! ( sh_cfun_resbank_handler_p ( ) && ( ( i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG ) || i == MACH_REG || i == MACL_REG || i == GBR_REG ) ) ) push ( i ) ; } } if ( interrupt_handler ) { bool use_movml = false ; if ( TARGET_SH2A ) { unsigned int count = 0 ; for ( int i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) if ( TEST_HARD_REG_BIT ( * mask , i ) ) count ++ ; else break ; if ( count == LAST_BANKED_REG - FIRST_BANKED_REG + 1 ) use_movml = true ; } if ( sh_cfun_resbank_handler_p ( ) ) ; else if ( use_movml ) { rtx x , mem , reg , set ; rtx sp_reg = gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) ; emit_insn ( gen_blockage ( ) ) ; x = gen_movml_push_banked ( sp_reg ) ; x = emit_frame_insn ( x ) ; for ( int i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) { mem = gen_rtx_MEM ( SImode , plus_constant ( Pmode , sp_reg , i * 4 ) ) ; reg = gen_rtx_REG ( SImode , i ) ; add_reg_note ( x , REG_CFA_OFFSET , gen_rtx_SET ( mem , reg ) ) ; } set = gen_rtx_SET ( sp_reg , plus_constant ( Pmode , sp_reg , - 32 ) ) ; add_reg_note ( x , REG_CFA_ADJUST_CFA , set ) ; emit_insn ( gen_blockage ( ) ) ; } else for ( int i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) if ( TEST_HARD_REG_BIT ( * mask , i ) ) push ( i ) ; } if ( TEST_HARD_REG_BIT ( * mask , PR_REG ) && ! sh_cfun_resbank_handler_p ( ) ) push ( PR_REG ) ; } </s>

Generate code to push the regs specified in the mask . remember that the mask is of the internal shape of the regs , not the external shape - so go through the renumber vector


<s> static bool hasTailCall ( const MachineBasicBlock & MBB ) { MachineBasicBlock :: const_iterator I = MBB . getLastNonDebugInstr ( ) ; unsigned RetOpc = I -> getOpcode ( ) ; return RetOpc == Hexagon :: PS_tailcall_i || RetOpc == Hexagon :: PS_tailcall_r ; } </s>

Returns true if the function contains a tail call .


"Pseudo flag setting opcodes only exist in Selection DAG"

"Non-flag-setting Thumb1 mov is v6-only"

"Unsupported register in Thumb1 push/pop"

Perform target-specific instruction verification .


<s> void WebAssemblyPassConfig :: addPostRegAlloc ( ) { disablePass ( & MachineCopyPropagationID ) ; disablePass ( & PostRAMachineSinkingID ) ; disablePass ( & PostRASchedulerID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & StackMapLivenessID ) ; disablePass ( & LiveDebugValuesID ) ; disablePass ( & PatchableFunctionID ) ; disablePass ( & ShrinkWrapID ) ; TargetPassConfig :: addPostRegAlloc ( ) ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> uint64_t R600MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) { if ( HAS_NATIVE_OPERANDS ( MCII . get ( MI . getOpcode ( ) ) . TSFlags ) ) return MRI . getEncodingValue ( MO . getReg ( ) ) ; return getHWReg ( MO . getReg ( ) ) ; } if ( MO . isExpr ( ) ) { const MCSymbolRefExpr * Expr = cast < MCSymbolRefExpr > ( MO . getExpr ( ) ) ; const unsigned offset = ( & MO == & MI . getOperand ( 0 ) ) ? 0 : 4 ; Fixups . push_back ( MCFixup :: create ( offset , Expr , FK_SecRel_4 , MI . getLoc ( ) ) ) ; return 0 ; } assert ( MO . isImm ( ) ) ; return MO . getImm ( ) ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> MachineInstr * X86FrameLowering :: emitStackProbe ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , DebugLoc DL , bool InProlog ) const { const X86Subtarget & STI = MF . getSubtarget < X86Subtarget > ( ) ; if ( STI . isTargetWindowsCoreCLR ( ) ) { if ( InProlog ) { return emitStackProbeInlineStub ( MF , MBB , MBBI , DL , true ) ; } else { return emitStackProbeInline ( MF , MBB , MBBI , DL , false ) ; } } else { return emitStackProbeCall ( MF , MBB , MBBI , DL , InProlog ) ; } } </s>


<s> static void rs6000_free_sched_context ( void * _sc ) { gcc_assert ( _sc != NULL ) ; free ( _sc ) ; } </s>


<s> void RISCVPassConfig :: addPreEmitPass2 ( ) { addPass ( createRISCVExpandPseudoPass ( ) ) ; addPass ( createPULPFixupHwLoops ( ) ) ; addPass ( createRISCVExpandAtomicPseudoPass ( ) ) ; } </s>

Targets may add passes immediately before machine code is emitted in this callback .


<s>
SDValue
MSP430TargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
if
(
CallConv
==
CallingConv
::
MSP430_INTR
&&
!
Outs
.
empty
(
)
)
{
report_fatal_error
(
"ISRs cannot return any value"
)
;
return
SDValue
(
)
;
}
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_MSP430
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
if
(
RVLocs
[
i
]
.
isRegLoc
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
unsigned
Opc
=
(
CallConv
==
CallingConv
::
MSP430_INTR
MSP430ISD
::
RETI_FLAG
:
MSP430ISD
::
RET_FLAG
)
;
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
Opc
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
return
DAG
.
getNode
(
Opc
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool MipsAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == ".ent" ) { Parser . Lex ( ) ; return false ; } if ( IDVal == ".end" ) { Parser . Lex ( ) ; return false ; } if ( IDVal == ".frame" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".set" ) { return parseDirectiveSet ( ) ; } if ( IDVal == ".fmask" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".mask" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".gpword" ) { parseDirectiveGpWord ( ) ; return false ; } if ( IDVal == ".word" ) { parseDirectiveWord ( 4 , DirectiveID . getLoc ( ) ) ; return false ; } if ( IDVal == ".mips_hack_stocg" ) return parseDirectiveMipsHackStocg ( ) ; if ( IDVal == ".mips_hack_elf_flags" ) return parseDirectiveMipsHackELFFlags ( ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool AMDGPUTargetLowering :: isCheapToSpeculateCtlz ( ) const { return true ; } </s>

Return true if it is cheap to speculate a call to intrinsic ctlz .


<s>
void
Thumb1InstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
Register
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
->
hasSuperClassEq
(
&
ARM
::
tGPRRegClass
)
||
(
Register
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
->
hasSuperClassEq
(
&
ARM
::
tGPRRegClass
)
||
(
Register
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
,
MachineMemOperand
::
MOLoad
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlign
(
FI
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tLDRspi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .

ARM
ARM::tGPRRegClass
ARM
"Unknown regclass!"
ARM::tGPRRegClass
ARM
ARM::tLDRspi
0
ARMCC::AL


<s> void MipsOptimizeMathLibCalls :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < TargetLibraryInfo > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> int arc_unalign_branch_p ( rtx branch ) { rtx note ; if ( ! TARGET_UNALIGN_BRANCH ) return 0 ; if ( get_attr_delay_slot_filled ( branch ) == DELAY_SLOT_FILLED_YES && ! NEXT_INSN ( branch ) -> deleted ( ) ) return 0 ; note = find_reg_note ( branch , REG_BR_PROB , 0 ) ; return ( ! note || ( arc_unalign_prob_threshold && ! br_prob_note_reliable_p ( note ) ) || INTVAL ( XEXP ( note , 0 ) ) < arc_unalign_prob_threshold ) ; } </s>

Return nonzero iff BRANCH should be unaligned if possible by upsizing a previous instruction .


<s> bool X86TargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty , unsigned AS ) const { CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; Reloc :: Model R = getTargetMachine ( ) . getRelocationModel ( ) ; if ( ! X86 :: isOffsetSuitableForCodeModel ( AM . BaseOffs , M , AM . BaseGV != nullptr ) ) return false ; if ( AM . BaseGV ) { unsigned GVFlags = Subtarget -> ClassifyGlobalReference ( AM . BaseGV , getTargetMachine ( ) ) ; if ( isGlobalStubReference ( GVFlags ) ) return false ; if ( AM . HasBaseReg && isGlobalRelativeToPICBase ( GVFlags ) ) return false ; if ( ( M != CodeModel :: Small || R != Reloc :: Static ) && Subtarget -> is64Bit ( ) && ( AM . BaseOffs || AM . Scale > 1 ) ) return false ; } switch ( AM . Scale ) { case 0 : case 1 : case 2 : case 4 : case 8 : break ; case 3 : case 5 : case 9 : if ( AM . HasBaseReg ) return false ; break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> SDValue X86TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: EXTRACT_VECTOR_ELT : return PerformEXTRACT_VECTOR_ELTCombine ( N , DAG , DCI ) ; case ISD :: VSELECT : case ISD :: SELECT : return PerformSELECTCombine ( N , DAG , DCI , Subtarget ) ; case X86ISD :: CMOV : return PerformCMOVCombine ( N , DAG , DCI ) ; case ISD :: ADD : return PerformAddCombine ( N , DAG , Subtarget ) ; case ISD :: SUB : return PerformSubCombine ( N , DAG , Subtarget ) ; case X86ISD :: ADC : return PerformADCCombine ( N , DAG , DCI ) ; case ISD :: MUL : return PerformMulCombine ( N , DAG , DCI ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: AND : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: OR : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: XOR : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: LOAD : return PerformLOADCombine ( N , DAG , Subtarget ) ; case ISD :: STORE : return PerformSTORECombine ( N , DAG , Subtarget ) ; case ISD :: SINT_TO_FP : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case ISD :: FADD : return PerformFADDCombine ( N , DAG , Subtarget ) ; case ISD :: FSUB : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case X86ISD :: FXOR : case X86ISD :: FOR : return PerformFORCombine ( N , DAG ) ; case X86ISD :: FAND : return PerformFANDCombine ( N , DAG ) ; case X86ISD :: BT : return PerformBTCombine ( N , DAG , DCI ) ; case X86ISD :: VZEXT_MOVL : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case ISD :: ZERO_EXTEND : return PerformZExtCombine ( N , DAG , Subtarget ) ; case ISD :: SIGN_EXTEND : return PerformSExtCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: TRUNCATE : return PerformTruncateCombine ( N , DAG , DCI ) ; case X86ISD :: SETCC : return PerformSETCCCombine ( N , DAG ) ; case X86ISD :: SHUFP : case X86ISD :: PALIGN : case X86ISD :: UNPCKH : case X86ISD :: UNPCKL : case X86ISD :: MOVHLPS : case X86ISD :: MOVLHPS : case X86ISD :: PSHUFD : case X86ISD :: PSHUFHW : case X86ISD :: PSHUFLW : case X86ISD :: MOVSS : case X86ISD :: MOVSD : case X86ISD :: VPERMILP : case X86ISD :: VPERM2X128 : case ISD :: VECTOR_SHUFFLE : return PerformShuffleCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s>
static
rtx
m32c_legitimize_address
(
rtx
x
,
rtx
oldx
ATTRIBUTE_UNUSED
,
machine_mode
mode
)
{
fprintf
(
stderr
,
"m32c_legitimize_address for mode %s\n"
,
mode_name
[
mode
]
)
;
debug_rtx
(
x
)
;
fprintf
(
stderr
,
"\n"
)
;
if
(
GET_CODE
(
x
)
==
PLUS
&&
GET_CODE
(
XEXP
(
x
,
0
)
)
==
REG
&&
REGNO
(
XEXP
(
x
,
0
)
)
==
FB_REGNO
&&
GET_CODE
(
XEXP
(
x
,
1
)
)
==
CONST_INT
&&
(
INTVAL
(
XEXP
(
x
,
1
)
)
<
128
||
INTVAL
(
XEXP
(
x
,
1
)
)
>
(
128
GET_MODE_SIZE
(
mode
)
)
)
)
{
rtx
temp
=
gen_reg_rtx
(
Pmode
)
;
x
=
copy_rtx
(
x
)
;
emit_insn
(
gen_rtx_SET
(
VOIDmode
,
temp
,
XEXP
(
x
,
0
)
)
)
;
XEXP
(
x
,
0
)
=
temp
;
}
return
x
;
}
</s>

Implements LEGITIMIZE_ADDRESS . The only address we really have to worry about is frame base offsets , as $ fb has a limited displacement range . We deal with this by attempting to reload $ fb itself into an address register ; that seems to result in the best code .


<s> bool X86TargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty ) const { CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; Reloc :: Model R = getTargetMachine ( ) . getRelocationModel ( ) ; if ( ! X86 :: isOffsetSuitableForCodeModel ( AM . BaseOffs , M , AM . BaseGV != nullptr ) ) return false ; if ( AM . BaseGV ) { unsigned GVFlags = Subtarget -> ClassifyGlobalReference ( AM . BaseGV , getTargetMachine ( ) ) ; if ( isGlobalStubReference ( GVFlags ) ) return false ; if ( AM . HasBaseReg && isGlobalRelativeToPICBase ( GVFlags ) ) return false ; if ( ( M != CodeModel :: Small || R != Reloc :: Static ) && Subtarget -> is64Bit ( ) && ( AM . BaseOffs || AM . Scale > 1 ) ) return false ; } switch ( AM . Scale ) { case 0 : case 1 : case 2 : case 4 : case 8 : break ; case 3 : case 5 : case 9 : if ( AM . HasBaseReg ) return false ; break ; default : return false ; } return true ; } </s>


<s> static void rs6000_finish_cost ( void * data , unsigned * prologue_cost , unsigned * body_cost , unsigned * epilogue_cost ) { rs6000_cost_data * cost_data = ( rs6000_cost_data * ) data ; if ( cost_data -> loop_info ) { rs6000_adjust_vect_cost_per_loop ( cost_data ) ; rs6000_density_test ( cost_data ) ; } if ( cost_data -> loop_info ) { loop_vec_info vec_info = loop_vec_info_for_loop ( cost_data -> loop_info ) ; if ( ! rs6000_vect_nonmem && LOOP_VINFO_VECT_FACTOR ( vec_info ) == 2 && LOOP_REQUIRES_VERSIONING ( vec_info ) ) cost_data -> cost [ vect_body ] += 10000 ; } * prologue_cost = cost_data -> cost [ vect_prologue ] ; * body_cost = cost_data -> cost [ vect_body ] ; * epilogue_cost = cost_data -> cost [ vect_epilogue ] ; } </s>


<s> bool mayNeedRelaxation ( MCInst const & ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> bool MBlazeTargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createMBlazeDelaySlotFillerPass ( * this ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void AMDGPUTargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { switch ( N -> getOpcode ( ) ) { case ISD :: SIGN_EXTEND_INREG : return ; case ISD :: LOAD : { SDNode * Node = LowerLOAD ( SDValue ( N , 0 ) , DAG ) . getNode ( ) ; if ( ! Node ) return ; Results . push_back ( SDValue ( Node , 0 ) ) ; Results . push_back ( SDValue ( Node , 1 ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( N , 1 ) , SDValue ( Node , 1 ) ) ; return ; } case ISD :: STORE : { SDValue Lowered = LowerSTORE ( SDValue ( N , 0 ) , DAG ) ; if ( Lowered . getNode ( ) ) Results . push_back ( Lowered ) ; return ; } default : return ; } } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> bool F2003fInstrInfo :: isUnpredicatedTerminator ( const MachineInstr & MI ) const { if ( ! MI . isTerminator ( ) ) return false ; if ( MI . isBranch ( ) && ! MI . isBarrier ( ) ) return true ; if ( ! MI . isPredicable ( ) ) return true ; return ! isPredicated ( MI ) ; } </s>

Returns true if the instruction is a terminator instruction that has not been predicated .


<s>
bool
HexagonPassConfig
::
addInstSelector
(
)
{
HexagonTargetMachine
&
TM
=
getHexagonTargetMachine
(
)
;
bool
NoOpt
=
(
getOptLevel
(
)
==
CodeGenOpt
::
)
;
if
(
!
NoOpt
)
addPass
(
createHexagonRemoveExtendArgs
(
TM
)
)
;
addPass
(
createHexagonISelDag
(
TM
,
getOptLevel
(
)
)
)
;
if
(
!
NoOpt
)
{
addPass
(
createHexagonPeephole
(
)
)
;
printAndVerify
(
"After hexagon peephole pass"
)
;
}
return
false
;
}
</s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .

Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
"After hexagon peephole pass"


<s> bool X86TTIImpl :: isLegalMaskedLoad ( Type * DataTy , Align Alignment ) { if ( ! ST -> hasAVX ( ) ) return false ; if ( isa < VectorType > ( DataTy ) && cast < FixedVectorType > ( DataTy ) -> getNumElements ( ) == 1 ) return false ; Type * ScalarTy = DataTy -> getScalarType ( ) ; if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ScalarTy -> isHalfTy ( ) && ST -> hasBWI ( ) && ST -> hasFP16 ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == 32 || IntWidth == 64 || ( ( IntWidth == 8 || IntWidth == 16 ) && ST -> hasBWI ( ) ) ; } </s>

Return true if the target supports masked load .


<s> static bool indirectable_address_p ( rtx x , bool strict , bool indirect ) { if ( indirectable_constant_address_p ( x , indirect ) || BASE_REGISTER_P ( x , strict ) ) return true ; if ( GET_CODE ( x ) != PLUS || ! BASE_REGISTER_P ( XEXP ( x , 0 ) , strict ) || ( flag_pic && ! CONST_INT_P ( XEXP ( x , 1 ) ) ) ) return false ; return indirectable_constant_address_p ( XEXP ( x , 1 ) , indirect ) ; } </s>

Nonzero if X is an address which can be indirected . External symbols could be in a sharable image library , so we disallow those .


<s> bool aarch64_sve_float_mul_immediate_p ( rtx x ) { rtx elt ; return ( const_vec_duplicate_p ( x , & elt ) && CONST_DOUBLE_P ( elt ) && ( real_equal ( CONST_DOUBLE_REAL_VALUE ( elt ) , & dconsthalf ) || real_equal ( CONST_DOUBLE_REAL_VALUE ( elt ) , & dconst2 ) ) ) ; } </s>

Return true if X is a valid immediate operand for an SVE FMUL instruction .


<s> unsigned RISCVTargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { switch ( Op . getOpcode ( ) ) { default : break ; case RISCVISD :: SLLW : case RISCVISD :: SRAW : case RISCVISD :: SRLW : case RISCVISD :: DIVW : case RISCVISD :: DIVUW : case RISCVISD :: REMUW : return 33 ; } return 1 ; } </s>

Determine the number of bits in the operation that are sign bits .

RISCV RISCV RISCVISD::SLLW RISCVISD::SRAW RISCVISD::SRLW RISCVISD::DIVW RISCVISD::DIVUW RISCVISD::REMUW 33 1


<s> bool X86TTIImpl :: isLegalMaskedLoad ( Type * DataTy , Align Alignment ) { if ( ! ST -> hasAVX ( ) ) return false ; if ( isa < VectorType > ( DataTy ) && cast < FixedVectorType > ( DataTy ) -> getNumElements ( ) == 1 ) return false ; Type * ScalarTy = DataTy -> getScalarType ( ) ; if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == 32 || IntWidth == 64 || ( ( IntWidth == 8 || IntWidth == 16 ) && ST -> hasBWI ( ) ) ; } </s>


<s> bool isLegalNTStore ( Type * DataType , Align Alignment ) { if ( auto * DataTypeVTy = dyn_cast < VectorType > ( DataType ) ) { unsigned NumElements = DataTypeVTy -> getNumElements ( ) ; unsigned EltSize = DataTypeVTy -> getElementType ( ) -> getScalarSizeInBits ( ) ; return NumElements > 1 && isPowerOf2_64 ( NumElements ) && EltSize >= 8 && EltSize <= 128 && isPowerOf2_64 ( EltSize ) ; } return BaseT :: isLegalNTStore ( DataType , Alignment ) ; } </s>

Return true if the target supports nontemporal store .


"Lowering returned the wrong number of results!"

This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types .


<s>
void
ARMTTIImpl
::
getUnrollingPreferences
(
Loop
*
L
,
ScalarEvolution
&
SE
,
TTI
::
UnrollingPreferences
&
UP
)
{
if
(
!
ST
->
isMClass
(
)
)
return
BasicTTIImplBase
::
getUnrollingPreferences
(
L
,
SE
,
UP
)
;
UP
.
OptSizeThreshold
=
0
;
UP
.
PartialOptSizeThreshold
=
0
;
if
(
L
->
getHeader
(
)
->
getParent
(
)
->
hasOptSize
(
)
)
return
;
if
(
!
ST
->
isThumb2
(
)
)
return
;
SmallVector
<
BasicBlock
*
,
4
>
ExitingBlocks
;
L
->
getExitingBlocks
(
ExitingBlocks
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Loop has:\n"
<<
"Blocks: "
<<
L
->
getNumBlocks
(
)
<<
"\n"
<<
"Exit blocks: "
<<
ExitingBlocks
.
size
(
)
<<
"\n"
)
;
if
(
ExitingBlocks
.
size
(
)
>
2
)
return
;
if
(
ST
->
hasBranchPredictor
(
)
&&
L
->
getNumBlocks
(
)
>
4
)
return
;
unsigned
Cost
=
0
;
for
(
auto
*
BB
:
L
->
getBlocks
(
)
)
{
for
(
auto
&
I
:
*
BB
)
{
if
(
isa
<
CallInst
>
(
I
)
||
isa
<
InvokeInst
>
(
I
)
)
{
ImmutableCallSite
CS
(
&
I
)
;
if
(
const
Function
*
F
=
CS
.
getCalledFunction
(
)
)
{
if
(
!
isLoweredToCall
(
F
)
)
continue
;
}
return
;
}
if
(
I
.
getType
(
)
->
isVectorTy
(
)
)
return
;
SmallVector
<
const
Value
*
,
4
>
Operands
(
I
.
value_op_begin
(
)
,
I
.
value_op_end
(
)
)
;
Cost
+=
getUserCost
(
&
I
,
Operands
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Cost of loop: "
<<
Cost
<<
"\n"
)
;
UP
.
Partial
=
true
;
UP
.
Runtime
=
true
;
UP
.
UpperBound
=
true
;
UP
.
UnrollRemainder
=
true
;
UP
.
DefaultUnrollRuntimeCount
=
4
;
UP
.
UnrollAndJam
=
true
;
UP
.
UnrollAndJamInnerLoopThreshold
=
60
;
if
(
Cost
<
12
)
UP
.
Force
=
true
;
}
</s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> bool runOnMachineFunction ( MachineFunction & F ) override { bool Changed = false ; Subtarget = & F . getSubtarget < SparcSubtarget > ( ) ; F . getRegInfo ( ) . invalidateLiveness ( ) ; for ( MachineBasicBlock & MBB : F ) Changed |= runOnMachineBasicBlock ( MBB ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> static unsigned aarch64_add_stmt_cost ( class vec_info * vinfo , void * data , int count , enum vect_cost_for_stmt kind , struct _stmt_vec_info * stmt_info , tree vectype , int misalign , enum vect_cost_model_location where ) { auto * costs = static_cast < aarch64_vector_costs * > ( data ) ; unsigned retval = 0 ; if ( flag_vect_cost_model ) { int stmt_cost = aarch64_builtin_vectorization_cost ( kind , vectype , misalign ) ; loop_vec_info loop_vinfo = dyn_cast < loop_vec_info > ( vinfo ) ; bb_vec_info bb_vinfo = dyn_cast < bb_vec_info > ( vinfo ) ; if ( ! costs -> analyzed_vinfo && aarch64_use_new_vector_costs_p ( ) ) { if ( loop_vinfo ) aarch64_analyze_loop_vinfo ( loop_vinfo , costs ) ; else aarch64_analyze_bb_vinfo ( bb_vinfo , costs ) ; costs -> analyzed_vinfo = true ; } if ( stmt_info && aarch64_use_new_vector_costs_p ( ) ) { if ( vectype && aarch64_sve_only_stmt_p ( stmt_info , vectype ) ) costs -> saw_sve_only_op = true ; stmt_cost = aarch64_detect_scalar_stmt_subtype ( vinfo , kind , stmt_info , stmt_cost ) ; if ( vectype && costs -> vec_flags ) stmt_cost = aarch64_detect_vector_stmt_subtype ( vinfo , kind , stmt_info , vectype , where , stmt_cost ) ; } if ( stmt_info && vectype && aarch64_sve_mode_p ( TYPE_MODE ( vectype ) ) ) stmt_cost = aarch64_sve_adjust_stmt_cost ( vinfo , kind , stmt_info , vectype , stmt_cost ) ; if ( stmt_info && aarch64_use_new_vector_costs_p ( ) ) { stmt_cost = aarch64_adjust_stmt_cost ( kind , stmt_info , vectype , stmt_cost ) ; auto * issue_info = aarch64_tune_params . vec_costs -> issue_info ; if ( loop_vinfo && issue_info && costs -> vec_flags && where == vect_body && vectype && stmt_cost != 0 ) { aarch64_count_ops ( vinfo , costs , count , kind , stmt_info , vectype , 0 , & costs -> scalar_ops , issue_info -> scalar , vect_nunits_for_cost ( vectype ) ) ; if ( aarch64_sve_mode_p ( vinfo -> vector_mode ) && issue_info -> sve ) { aarch64_count_ops ( vinfo , costs , count , kind , stmt_info , vectype , VEC_ADVSIMD , & costs -> advsimd_ops , issue_info -> advsimd , aarch64_estimated_sve_vq ( ) ) ; aarch64_count_ops ( vinfo , costs , count , kind , stmt_info , vectype , VEC_ANY_SVE , & costs -> sve_ops , issue_info -> sve , 1 ) ; } else aarch64_count_ops ( vinfo , costs , count , kind , stmt_info , vectype , VEC_ADVSIMD , & costs -> advsimd_ops , issue_info -> advsimd , 1 ) ; } if ( where == vect_body && costs -> unrolled_advsimd_niters ) costs -> unrolled_advsimd_stmts += count * costs -> unrolled_advsimd_niters ; } if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( vinfo , stmt_info ) ) count *= 50 ; retval = ( unsigned ) ( count * stmt_cost ) ; costs -> region [ where ] += retval ; } return retval ; } </s>


<s> static bool riscv_classify_address ( struct riscv_address_info * info , rtx x , machine_mode mode , bool strict_p ) { switch ( GET_CODE ( x ) ) { case REG : case SUBREG : info -> type = ADDRESS_REG ; info -> reg = x ; info -> offset = const0_rtx ; return riscv_valid_base_register_p ( info -> reg , mode , strict_p ) ; case PLUS : info -> type = ADDRESS_REG ; info -> reg = XEXP ( x , 0 ) ; info -> offset = XEXP ( x , 1 ) ; return ( riscv_valid_base_register_p ( info -> reg , mode , strict_p ) && riscv_valid_offset_p ( info -> offset , mode ) ) ; case LO_SUM : info -> type = ADDRESS_LO_SUM ; info -> reg = XEXP ( x , 0 ) ; info -> offset = XEXP ( x , 1 ) ; info -> symbol_type = riscv_classify_symbolic_expression ( info -> offset ) ; return ( riscv_valid_base_register_p ( info -> reg , mode , strict_p ) && riscv_valid_lo_sum_p ( info -> symbol_type , mode , info -> offset ) ) ; case CONST_INT : info -> type = ADDRESS_CONST_INT ; return SMALL_OPERAND ( INTVAL ( x ) ) ; default : return false ; } } </s>

Return true if X is a valid address for machine mode MODE . If it is , fill in INFO appropriately . STRICT_P is true if REG_OK_STRICT is in effect .


<s> static unsigned long arm_isr_value ( tree argument ) { const isr_attribute_arg * ptr ; const char * arg ; if ( argument == NULL_TREE ) return ARM_FT_ISR ; if ( TREE_VALUE ( argument ) == NULL_TREE || TREE_CODE ( TREE_VALUE ( argument ) ) != STRING_CST ) return ARM_FT_UNKNOWN ; arg = TREE_STRING_POINTER ( TREE_VALUE ( argument ) ) ; for ( ptr = isr_attribute_args ; ptr -> arg != NULL ; ptr ++ ) if ( streq ( arg , ptr -> arg ) ) return ptr -> return_value ; return ARM_FT_UNKNOWN ; } </s>

Returns the ( interrupt ) function type of the current function , or ARM_FT_UNKNOWN if the type can not be determined .


<s>
Register
PPCTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
LLT
VT
,
const
MachineFunction
&
MF
)
const
{
bool
isPPC64
=
Subtarget
.
isPPC64
(
)
;
bool
IsDarwinABI
=
Subtarget
.
isDarwinABI
(
)
;
bool
is64Bit
=
isPPC64
&&
VT
==
LLT
::
scalar
(
64
)
;
if
(
!
is64Bit
&&
VT
!=
LLT
::
scalar
(
32
)
)
report_fatal_error
(
"Invalid register global variable type"
)
;
Register
Reg
=
StringSwitch
<
Register
>
(
RegName
)
.
Case
(
"r1"
,
is64Bit
PPC
::
X1
:
PPC
::
R1
)
.
Case
(
"r2"
,
(
IsDarwinABI
||
isPPC64
)
Register
(
)
:
PPC
::
R2
)
.
Case
(
"r13"
,
(
!
isPPC64
&&
IsDarwinABI
)
Register
(
)
:
(
is64Bit
PPC
::
X13
:
PPC
::
R13
)
)
.
Default
(
Register
(
)
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


"Cannot store this register to stack slot!"

Store the specified register of the given register class to the specified stack frame index .


<s> static rtx emit_frame_save ( rtx frame_reg , machine_mode mode , unsigned int regno , int offset , HOST_WIDE_INT frame_reg_to_sp ) { rtx reg , insn ; gcc_checking_assert ( ! ( ( TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE ( mode ) ) || ( TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) ) || ( TARGET_E500_DOUBLE && mode == DFmode ) || ( TARGET_SPE_ABI && SPE_VECTOR_MODE ( mode ) && ! SPE_CONST_OFFSET_OK ( offset ) ) ) ) ; reg = gen_rtx_REG ( mode , regno ) ; insn = emit_insn ( gen_frame_store ( reg , frame_reg , offset ) ) ; return rs6000_frame_related ( insn , frame_reg , frame_reg_to_sp , NULL_RTX , NULL_RTX ) ; } </s>

Save a register into the frame , and emit RTX_FRAME_RELATED_P notes . Save REGNO into [ FRAME_REG + OFFSET ] in mode MODE .


<s> rtx fusion_wrap_memory_address ( rtx old_mem ) { rtx old_addr = XEXP ( old_mem , 0 ) ; rtvec v = gen_rtvec ( 1 , old_addr ) ; rtx new_addr = gen_rtx_UNSPEC ( Pmode , v , UNSPEC_FUSION_ADDIS ) ; return replace_equiv_address_nv ( old_mem , new_addr , false ) ; } </s>

Wrap a TOC address that can be fused to indicate that special fusion processing is needed .


<s> bool aarch64_sve_arith_immediate_p ( machine_mode mode , rtx x , bool negate_p ) { rtx elt = unwrap_const_vec_duplicate ( x ) ; if ( ! CONST_INT_P ( elt ) ) return false ; HOST_WIDE_INT val = INTVAL ( elt ) ; if ( negate_p ) val = - val ; val &= GET_MODE_MASK ( GET_MODE_INNER ( mode ) ) ; if ( val & 0xff ) return IN_RANGE ( val , 0 , 0xff ) ; return IN_RANGE ( val , 0 , 0xff00 ) ; } </s>

Return true if X is a valid immediate for the SVE ADD and SUB instructions . Negate X first if NEGATE_P is true .


<s>
void
i386_pe_seh_cold_init
(
FILE
*
f
,
const
char
*
name
)
{
struct
seh_frame_state
*
seh
;
HOST_WIDE_INT
alloc_offset
,
offset
;
if
(
!
TARGET_SEH
)
return
;
if
(
cfun
->
is_thunk
)
return
;
seh
=
cfun
->
machine
->
seh
;
fputs
(
"\t.seh_proc\t"
,
f
)
;
assemble_name
(
f
,
name
)
;
fputc
(
'\n'
,
f
)
;
if
(
crtl
->
accesses_prior_frames
)
alloc_offset
=
seh
->
cfa_offset
;
else
alloc_offset
=
seh
->
sp_offset
;
offset
=
alloc_offset
INCOMING_FRAME_SP_OFFSET
;
if
(
offset
>
0
&&
offset
<
SEH_MAX_FRAME_SIZE
)
fprintf
(
f
,
"\t.seh_stackalloc\t"
HOST_WIDE_INT_PRINT_DEC
"\n"
,
offset
)
;
for
(
int
regno
=
0
;
regno
<
FIRST_PSEUDO_REGISTER
;
regno
++
)
if
(
seh
->
reg_offset
[
regno
]
>
0
)
{
fputs
(
(
SSE_REGNO_P
(
regno
)
"\t.seh_savexmm\t"
:
GENERAL_REGNO_P
(
regno
)
"\t.seh_savereg\t"
:
(
gcc_unreachable
(
)
,
""
)
)
,
f
)
;
print_reg
(
gen_rtx_REG
(
DImode
,
regno
)
,
0
,
f
)
;
fprintf
(
f
,
", "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
alloc_offset
seh
->
reg_offset
[
regno
]
)
;
}
if
(
seh
->
cfa_reg
!=
stack_pointer_rtx
)
{
offset
=
alloc_offset
seh
->
cfa_offset
;
gcc_assert
(
(
offset
&
15
)
==
0
)
;
gcc_assert
(
IN_RANGE
(
offset
,
0
,
240
)
)
;
fputs
(
"\t.seh_setframe\t"
,
f
)
;
print_reg
(
seh
->
cfa_reg
,
0
,
f
)
;
fprintf
(
f
,
", "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
offset
)
;
}
if
(
crtl
->
accesses_prior_frames
)
{
offset
=
seh
->
sp_offset
alloc_offset
;
if
(
offset
>
0
&&
offset
<
SEH_MAX_FRAME_SIZE
)
fprintf
(
f
,
"\t.seh_stackalloc\t"
HOST_WIDE_INT_PRINT_DEC
"\n"
,
offset
)
;
}
fputs
(
"\t.seh_endprologue\n"
,
f
)
;
}
</s>

Emit assembler directives to reconstruct the SEH state .


<s> static bool arm_cannot_copy_insn_p ( rtx insn ) { rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == PARALLEL && GET_CODE ( XVECEXP ( pat , 0 , 0 ) ) == SET ) { rtx rhs = SET_SRC ( XVECEXP ( pat , 0 , 0 ) ) ; if ( GET_CODE ( rhs ) == UNSPEC && XINT ( rhs , 1 ) == UNSPEC_PIC_BASE ) return TRUE ; if ( GET_CODE ( rhs ) == MEM && GET_CODE ( XEXP ( rhs , 0 ) ) == UNSPEC && XINT ( XEXP ( rhs , 0 ) , 1 ) == UNSPEC_PIC_BASE ) return TRUE ; } return FALSE ; } </s>

Must not copy any rtx that uses a pc-relative address .


<s> void AMDGPUPALMetadata :: reset ( ) { MsgPackDoc . clear ( ) ; Registers = MsgPackDoc . getEmptyNode ( ) ; HwStages = MsgPackDoc . getEmptyNode ( ) ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s> static bool dimode_scalar_to_vector_candidate_p ( rtx_insn * insn ) { rtx def_set = single_set ( insn ) ; if ( ! def_set ) return false ; if ( has_non_address_hard_reg ( insn ) ) return false ; rtx src = SET_SRC ( def_set ) ; rtx dst = SET_DEST ( def_set ) ; if ( GET_CODE ( src ) == COMPARE ) return convertible_comparison_p ( insn ) ; if ( ( GET_MODE ( src ) != DImode && ! CONST_INT_P ( src ) ) || GET_MODE ( dst ) != DImode ) return false ; if ( ! REG_P ( dst ) && ! MEM_P ( dst ) ) return false ; switch ( GET_CODE ( src ) ) { case ASHIFT : case LSHIFTRT : if ( ! CONST_INT_P ( XEXP ( src , 1 ) ) || ! IN_RANGE ( INTVAL ( XEXP ( src , 1 ) ) , 0 , 63 ) ) return false ; break ; case PLUS : case MINUS : case IOR : case XOR : case AND : if ( ! REG_P ( XEXP ( src , 1 ) ) && ! MEM_P ( XEXP ( src , 1 ) ) && ! CONST_INT_P ( XEXP ( src , 1 ) ) ) return false ; break ; case NEG : case NOT : break ; case REG : return true ; case MEM : case CONST_INT : return REG_P ( dst ) ; default : return false ; } if ( ! REG_P ( XEXP ( src , 0 ) ) && ! MEM_P ( XEXP ( src , 0 ) ) && ! CONST_INT_P ( XEXP ( src , 0 ) ) && ( GET_CODE ( src ) != AND || GET_CODE ( XEXP ( src , 0 ) ) != NOT || ! REG_P ( XEXP ( XEXP ( src , 0 ) , 0 ) ) ) ) return false ; if ( ( GET_MODE ( XEXP ( src , 0 ) ) != DImode && ! CONST_INT_P ( XEXP ( src , 0 ) ) ) || ( GET_CODE ( src ) != NEG && GET_CODE ( src ) != NOT && GET_MODE ( XEXP ( src , 1 ) ) != DImode && ! CONST_INT_P ( XEXP ( src , 1 ) ) ) ) return false ; return true ; } </s>

The DImode version of scalar_to_vector_candidate_p .


<s>
bool
PPCAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
{
if
(
ExtraCode
[
1
]
!=
0
)
return
true
;
switch
(
ExtraCode
[
0
]
)
{
default
:
return
true
;
case
'y'
:
{
const
char
*
RegName
=
"r0"
;
if
(
!
Subtarget
->
isDarwin
(
)
)
RegName
=
stripRegisterPrefix
(
RegName
)
;
O
<<
RegName
<<
", "
;
printOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
}
case
'U'
:
case
'X'
:
{
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
return
false
;
}
}
}
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
O
<<
"0("
;
printOperand
(
MI
,
OpNo
,
O
)
;
O
<<
")"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> void SITargetLowering :: finalizeLowering ( MachineFunction & MF ) const { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; SIMachineFunctionInfo * Info = MF . getInfo < SIMachineFunctionInfo > ( ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const SIRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; if ( Info -> isEntryFunction ( ) ) { reservePrivateMemoryRegs ( getTargetMachine ( ) , MF , * TRI , * Info ) ; } assert ( ! TRI -> isSubRegister ( Info -> getScratchRSrcReg ( ) , Info -> getStackPtrOffsetReg ( ) ) ) ; if ( Info -> getStackPtrOffsetReg ( ) != AMDGPU :: SP_REG ) MRI . replaceRegWith ( AMDGPU :: SP_REG , Info -> getStackPtrOffsetReg ( ) ) ; if ( Info -> getScratchRSrcReg ( ) != AMDGPU :: PRIVATE_RSRC_REG ) MRI . replaceRegWith ( AMDGPU :: PRIVATE_RSRC_REG , Info -> getScratchRSrcReg ( ) ) ; if ( Info -> getFrameOffsetReg ( ) != AMDGPU :: FP_REG ) MRI . replaceRegWith ( AMDGPU :: FP_REG , Info -> getFrameOffsetReg ( ) ) ; Info -> limitOccupancy ( MF ) ; if ( ST . isWave32 ( ) && ! MF . empty ( ) ) { const SIInstrInfo * TII = ST . getInstrInfo ( ) ; DebugLoc DL ; MachineBasicBlock & MBB = MF . front ( ) ; MachineBasicBlock :: iterator I = MBB . getFirstNonDebugInstr ( ) ; BuildMI ( MBB , I , DL , TII -> get ( TargetOpcode :: IMPLICIT_DEF ) , AMDGPU :: VCC_HI ) ; for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { TII -> fixImplicitOperands ( MI ) ; } } } TargetLoweringBase :: finalizeLowering ( MF ) ; } </s>

Execute target specific actions to finalize target lowering .


<s> rtx aarch64_ptrue_reg ( machine_mode mode ) { gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL ) ; rtx reg = force_reg ( VNx16BImode , CONSTM1_RTX ( VNx16BImode ) ) ; return gen_lowpart ( mode , reg ) ; } </s>

Return an all-true predicate register of mode MODE .


<s> void BPFAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { if ( Fixup . getKind ( ) == FK_SecRel_4 || Fixup . getKind ( ) == FK_SecRel_8 ) { assert ( Value == 0 ) ; } else if ( Fixup . getKind ( ) == FK_Data_4 || Fixup . getKind ( ) == FK_Data_8 ) { unsigned Size = Fixup . getKind ( ) == FK_Data_4 ? 4 : 8 ; for ( unsigned i = 0 ; i != Size ; ++ i ) { unsigned Idx = IsLittleEndian ? i : Size - i ; Data [ Fixup . getOffset ( ) + Idx ] = uint8_t ( Value >> ( i * 8 ) ) ; } } else { assert ( Fixup . getKind ( ) == FK_PCRel_2 ) ; Value = ( uint16_t ) ( ( Value - 8 ) / 8 ) ; if ( IsLittleEndian ) { Data [ Fixup . getOffset ( ) + 2 ] = Value & 0xFF ; Data [ Fixup . getOffset ( ) + 3 ] = Value >> 8 ; } else { Data [ Fixup . getOffset ( ) + 2 ] = Value >> 8 ; Data [ Fixup . getOffset ( ) + 3 ] = Value & 0xFF ; } } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool PPCInstrInfo :: getMachineCombinerPatterns ( MachineInstr & Root , SmallVectorImpl < MachineCombinerPattern :: MC_PATTERN > & Patterns ) const { if ( Subtarget . getTargetMachine ( ) . getOptLevel ( ) != CodeGenOpt :: Aggressive ) return false ; if ( ! Root . getParent ( ) -> getParent ( ) -> getTarget ( ) . Options . UnsafeFPMath ) return false ; return TargetInstrInfo :: getMachineCombinerPatterns ( Root , Patterns ) ; } </s>

Return true when there is potentially a faster code sequence for an instruction chain ending in Root .


<s> void HexagonPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) { if ( EnableInstSimplify ) addPass ( createInstSimplifyLegacyPass ( ) ) ; addPass ( createDeadCodeEliminationPass ( ) ) ; } addPass ( createAtomicExpandPass ( ) ) ; if ( ! NoOpt ) { if ( EnableInitialCFGCleanup ) addPass ( createCFGSimplificationPass ( SimplifyCFGOptions ( ) . forwardSwitchCondToPhi ( true ) . convertSwitchToLookupTable ( true ) . needCanonicalLoops ( false ) . hoistCommonInsts ( true ) . sinkCommonInsts ( true ) ) ) ; if ( EnableLoopPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableCommGEP ) addPass ( createHexagonCommonGEP ( ) ) ; if ( EnableGenExtract ) addPass ( createHexagonGenExtract ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s>
void
emitValueImpl
(
const
MCExpr
*
Value
,
unsigned
Size
,
SMLoc
Loc
)
override
{
if
(
const
MCSymbolRefExpr
*
SRE
=
dyn_cast_or_null
<
MCSymbolRefExpr
>
(
Value
)
)
{
if
(
SRE
->
getKind
(
)
==
MCSymbolRefExpr
::
VK_ARM_SBREL
&&
!
(
Size
==
4
)
)
{
getContext
(
)
.
reportError
(
Loc
,
"relocated expression must be 32-bit"
)
;
return
;
}
getOrCreateDataFragment
(
)
;
}
emitDataMappingSymbol
(
)
;
MCELFStreamer
::
emitValueImpl
(
Value
,
Size
,
Loc
)
;
}
</s>

Overriding these functions allows us to dismiss all labels that are candidates for marking as microMIPS when .word/.long/.4byte etc directives are emitted .

ARM
ARM
4
"relocated expression must be 32-bit"


<s> void VideocoreMCInstLower :: Initialize ( Mangler * M , MCContext * C ) { Mang = M ; Ctx = C ; } </s>

This method must be called before any actual lowering is done .


<s> AArch64Subtarget :: AArch64Subtarget ( StringRef TT , StringRef CPU , StringRef FS ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , HasNEON ( false ) , HasCrypto ( false ) , TargetTriple ( TT ) { ParseSubtargetFeatures ( CPU , FS ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> bool aarch64_move_imm ( HOST_WIDE_INT val , machine_mode mode ) { scalar_int_mode int_mode ; if ( ! is_a < scalar_int_mode > ( mode , & int_mode ) ) return false ; if ( aarch64_movw_imm ( val , int_mode ) || aarch64_movw_imm ( ~ val , int_mode ) ) return 1 ; return aarch64_bitmask_imm ( val , int_mode ) ; } </s>

Return true if val is an immediate that can be loaded into a register in a single instruction .