<s> unsigned PPCFrameLowering :: determineFrameLayout ( MachineFunction & MF , bool UpdateMF , bool UseEstimate ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = UseEstimate ? MFI -> estimateStackSize ( MF ) : MFI -> getStackSize ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - 1 ; const PPCRegisterInfo * RegInfo = static_cast < const PPCRegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; bool DisableRedZone = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoRedZone ) ; if ( ! DisableRedZone && ( Subtarget . isPPC64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == 0 ) && FrameSize <= 224 && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! RegInfo -> hasBasePointer ( MF ) ) { if ( UpdateMF ) MFI -> setStackSize ( 0 ) ; return 0 ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( Subtarget . isPPC64 ( ) , Subtarget . isDarwinABI ( ) , Subtarget . isELFv2ABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setStackSize ( FrameSize ) ; return FrameSize ; } </s>

Determine the frame layout but do not update the machine function .


<s>
bool
ARMPassConfig
::
addPreSched2
(
)
{
if
(
getOptLevel
(
)
!=
CodeGenOpt
::
)
{
if
(
!
getARMSubtarget
(
)
.
isThumb1Only
(
)
)
{
PM
->
add
(
createARMLoadStoreOptimizationPass
(
)
)
;
printAndVerify
(
"After ARM load / store optimizer"
)
;
}
if
(
getARMSubtarget
(
)
.
hasNEON
(
)
)
PM
->
add
(
createExecutionDependencyFixPass
(
&
ARM
::
DPRRegClass
)
)
;
}
PM
->
add
(
createARMExpandPseudoPass
(
)
)
;
if
(
getOptLevel
(
)
!=
CodeGenOpt
::
)
{
if
(
!
getARMSubtarget
(
)
.
isThumb1Only
(
)
)
addPass
(
IfConverterID
)
;
}
if
(
getARMSubtarget
(
)
.
isThumb2
(
)
)
PM
->
add
(
createThumb2ITBlockPass
(
)
)
;
return
true
;
}
</s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .

ARM
ARM
ARM
ARM
"After ARM load / store optimizer"
ARM
ARM::DPRRegClass
ARM
ARM
ARM


<s>
unsigned
assignCustomValue
(
const
ARMCallLowering
::
ArgInfo
&
Arg
,
ArrayRef
<
CCValAssign
>
VAs
)
override
{
assert
(
Arg
.
Regs
.
size
(
)
==
1
&&
"Can't handle multple regs yet"
)
;
CCValAssign
VA
=
VAs
[
0
]
;
assert
(
VA
.
needsCustom
(
)
&&
"Value doesn't need custom handling"
)
;
if
(
VA
.
getValVT
(
)
!=
MVT
::
f64
)
return
0
;
CCValAssign
NextVA
=
VAs
[
1
]
;
assert
(
NextVA
.
needsCustom
(
)
&&
"Value doesn't need custom handling"
)
;
assert
(
NextVA
.
getValVT
(
)
==
MVT
::
f64
&&
"Unsupported type"
)
;
assert
(
VA
.
getValNo
(
)
==
NextVA
.
getValNo
(
)
&&
"Values belong to different arguments"
)
;
assert
(
VA
.
isRegLoc
(
)
&&
"Value should be in reg"
)
;
assert
(
NextVA
.
isRegLoc
(
)
&&
"Value should be in reg"
)
;
Register
NewRegs
[
]
=
{
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
32
)
)
,
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
32
)
)
}
;
assignValueToReg
(
NewRegs
[
0
]
,
VA
.
getLocReg
(
)
,
VA
)
;
assignValueToReg
(
NewRegs
[
1
]
,
NextVA
.
getLocReg
(
)
,
NextVA
)
;
bool
IsLittle
=
MIRBuilder
.
getMF
(
)
.
getSubtarget
<
ARMSubtarget
>
(
)
.
isLittle
(
)
;
if
(
!
IsLittle
)
std
::
swap
(
NewRegs
[
0
]
,
NewRegs
[
1
]
)
;
MIRBuilder
.
buildMerge
(
Arg
.
Regs
[
0
]
,
NewRegs
)
;
return
1
;
}
</s>

Handle custom values , which may be passed into one or more of VAs .


<s> static rtx crx_struct_value_rtx ( tree fntype ATTRIBUTE_UNUSED , int incoming ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( Pmode , CRX_STRUCT_VALUE_REGNUM ) ; } </s>

Implements hook TARGET_STRUCT_VALUE_RTX .


<s> bool X86FrameLowering :: enableShrinkWrapping ( const MachineFunction & MF ) const { return ( MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoUnwind ) || hasFP ( MF ) ) && MF . getFunction ( ) -> getCallingConv ( ) != CallingConv :: HiPE && ! MF . shouldSplitStack ( ) ; } </s>

Returns true if the target will correctly handle shrink wrapping .


"Unable to create a unique discriminator "

"for instruction with memory operand in: "

". This is likely due to a large macro expansion. \n"

"New discriminator shouldn't be present in set"

runOnMachineFunction - Emit the function body .


<s> bool AMDGPULowerIntrinsics :: makeLIDRangeMetadata ( Function & F ) const { auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; const TargetMachine & TM = TPC -> getTM < TargetMachine > ( ) ; bool Changed = false ; for ( auto * U : F . users ( ) ) { auto * CI = dyn_cast < CallInst > ( U ) ; if ( ! CI ) continue ; Changed |= AMDGPUSubtarget :: get ( TM , F ) . makeLIDRangeMetadata ( CI ) ; } return Changed ; } </s>

Creates value range metadata on an workitemid . * intrinsic call or load .


<s> rtx nds32_expand_load_multiple ( int base_regno , int count , rtx base_addr , rtx basemem , bool update_base_reg_p , rtx * update_base_reg ) { int par_index ; int offset ; int start_idx ; rtx result ; rtx new_addr , mem , reg ; if ( count == 1 ) { reg = gen_rtx_REG ( SImode , base_regno ) ; if ( update_base_reg_p ) { * update_base_reg = gen_reg_rtx ( SImode ) ; return gen_unaligned_load_update_base_w ( * update_base_reg , reg , base_addr ) ; } else return gen_unaligned_load_w ( reg , gen_rtx_MEM ( SImode , base_addr ) ) ; } if ( update_base_reg_p ) { result = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count + 1 ) ) ; start_idx = 1 ; } else { result = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; start_idx = 0 ; } if ( update_base_reg_p ) { offset = count * 4 ; new_addr = plus_constant ( Pmode , base_addr , offset ) ; * update_base_reg = gen_reg_rtx ( SImode ) ; XVECEXP ( result , 0 , 0 ) = gen_rtx_SET ( * update_base_reg , new_addr ) ; } for ( par_index = 0 ; par_index < count ; par_index ++ ) { offset = par_index * 4 ; new_addr = plus_constant ( Pmode , base_addr , offset ) ; mem = adjust_automodify_address_nv ( basemem , SImode , new_addr , offset ) ; reg = gen_rtx_REG ( SImode , base_regno + par_index ) ; XVECEXP ( result , 0 , ( par_index + start_idx ) ) = gen_rtx_SET ( reg , mem ) ; } return result ; } </s>

Functions to expand load_multiple and store_multiple . They are auxiliary extern functions to help create rtx template . Check nds32-multiple.md file for the patterns .


<s> static inline bool is_naked_func ( const_tree decl ) { return has_func_attr ( decl , "naked" ) ; } </s>

Returns true if the provided function has the `` naked '' attribute .


<s> static std :: string getGraphName ( const agraph & G ) { return G . MF -> getFunction ( ) . getName ( ) . str ( ) ; } </s>

Generate a title for the graph in DOT format .


<s> static int mips_multipass_dfa_lookahead ( void ) { if ( mips_tune == PROCESSOR_SB1 ) return 4 ; return 0 ; } </s>


<s> bool X86InstrInfo :: findCommutedOpIndices ( MachineInstr * MI , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { switch ( MI -> getOpcode ( ) ) { case X86 :: VFMADDPDr231r : case X86 :: VFMADDPSr231r : case X86 :: VFMADDSDr231r : case X86 :: VFMADDSSr231r : case X86 :: VFMSUBPDr231r : case X86 :: VFMSUBPSr231r : case X86 :: VFMSUBSDr231r : case X86 :: VFMSUBSSr231r : case X86 :: VFNMADDPDr231r : case X86 :: VFNMADDPSr231r : case X86 :: VFNMADDSDr231r : case X86 :: VFNMADDSSr231r : case X86 :: VFNMSUBPDr231r : case X86 :: VFNMSUBPSr231r : case X86 :: VFNMSUBSDr231r : case X86 :: VFNMSUBSSr231r : case X86 :: VFMADDPDr231rY : case X86 :: VFMADDPSr231rY : case X86 :: VFMSUBPDr231rY : case X86 :: VFMSUBPSr231rY : case X86 :: VFNMADDPDr231rY : case X86 :: VFNMADDPSr231rY : case X86 :: VFNMSUBPDr231rY : case X86 :: VFNMSUBPSr231rY : SrcOpIdx1 = 2 ; SrcOpIdx2 = 3 ; return true ; default : return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; } } </s>

Returns true iff the routine could find two commutable operands in the given machine instruction .


<s> void aarch64_split_simd_move ( rtx dst , rtx src ) { machine_mode src_mode = GET_MODE ( src ) ; machine_mode dst_mode = GET_MODE ( dst ) ; gcc_assert ( VECTOR_MODE_P ( dst_mode ) ) ; if ( REG_P ( dst ) && REG_P ( src ) ) { rtx ( * gen ) ( rtx , rtx ) ; gcc_assert ( VECTOR_MODE_P ( src_mode ) ) ; switch ( src_mode ) { case V16QImode : gen = gen_aarch64_split_simd_movv16qi ; break ; case V8HImode : gen = gen_aarch64_split_simd_movv8hi ; break ; case V4SImode : gen = gen_aarch64_split_simd_movv4si ; break ; case V2DImode : gen = gen_aarch64_split_simd_movv2di ; break ; case V4SFmode : gen = gen_aarch64_split_simd_movv4sf ; break ; case V2DFmode : gen = gen_aarch64_split_simd_movv2df ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( dst , src ) ) ; return ; } } </s>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < TGSISubtarget > ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; return true ; } </s>


<s> bool riscv_v_ext_vector_mode_p ( machine_mode mode ) { case MODE ## mode : \ return REQUIREMENT ; switch ( mode ) { default : return false ; } return false ; } </s>

Return true if mode is the RVV enabled mode . For example : 'VNx1DI ' mode is disabled if MIN_VLEN == 32 . 'VNx1SI ' mode is enabled if MIN_VLEN == 32 .


<s> static const char * detect_processor_aix ( void ) { switch ( _system_configuration . implementation ) { case 0x0008 : return "601" ; case 0x0020 : return "603" ; case 0x0010 : return "604" ; case 0x0040 : return "620" ; case 0x0080 : return "630" ; case 0x0100 : case 0x0200 : case 0x0400 : return "rs64" ; case 0x0800 : return "power4" ; case 0x2000 : if ( _system_configuration . version == 0x0F0000 ) return "power5" ; else return "power5+" ; case 0x4000 : return "power6" ; case 0x8000 : return "power7" ; case 0x10000 : return "power8" ; default : return "powerpc" ; } } </s>

Returns the processor implementation on AIX .


Return the DataLayout associated with the module this SCEV instance is operating on .


<s> static bool rs6000_mode_dependent_address_p ( const_rtx addr , addr_space_t as ATTRIBUTE_UNUSED ) { return rs6000_mode_dependent_address_ptr ( addr ) ; } </s>


<s> inline machine_mode function_expander :: index_mode ( void ) const { return TYPE_MODE ( op_info -> args [ 1 ] . get_tree_type ( type . index ) ) ; } </s>

Return the machine_mode of the corresponding index type .


<s> static const char * aarch64_mangle_type ( const_tree type ) { if ( lang_hooks . types_compatible_p ( CONST_CAST_TREE ( type ) , va_list_type ) ) return "St9__va_list" ; if ( TYPE_NAME ( type ) != NULL ) return aarch64_mangle_builtin_type ( type ) ; return NULL ; } </s>


"movhi hi(%s), r0, r11\n\tmovea lo(%s), r11, r11\n\tjarl .+4, r10\n\tadd 4, r10\n\tjmp r11"

Construct a JARL instruction to a routine that will perform the equivalent of the RTL passed as a parameter . This RTL is a function prologue that saves some of the registers r20 - r31 onto the stack , and possibly acquires some stack space as well . The code has already verified that the RTL matches these requirements .


<s> unsigned AMDGPUInstrInfo :: getOpcodeAfterMemoryUnfold ( unsigned Opc , bool UnfoldLoad , bool UnfoldStore , unsigned * LoadRegIndex ) const { return 0 ; } </s>

getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode .


<s> bool rs6000_builtin_is_supported_p ( enum rs6000_builtins fncode ) { HOST_WIDE_INT fnmask = rs6000_builtin_info [ fncode ] . mask ; if ( ( fnmask & rs6000_builtin_mask ) != fnmask ) return false ; else return true ; } </s>

Check whether a builtin function is supported in this target configuration .


<s> bool X86ATTAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : break ; case 'P' : printOperand ( MI , OpNo , "mem" ) ; return false ; } } printMemReference ( MI , OpNo ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> const AMDGPURegisterInfo & AMDGPUInstrInfo :: getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static void mips_for_each_saved_reg ( HOST_WIDE_INT sp_offset , mips_save_restore_fn fn ) { enum machine_mode fpr_mode ; HOST_WIDE_INT offset ; int regno ; offset = cfun -> machine -> frame . gp_sp_offset - sp_offset ; for ( regno = GP_REG_LAST ; regno >= GP_REG_FIRST ; regno -- ) if ( BITSET_P ( cfun -> machine -> frame . mask , regno - GP_REG_FIRST ) ) { mips_save_restore_reg ( gpr_mode , regno , offset , fn ) ; offset -= GET_MODE_SIZE ( gpr_mode ) ; } offset = cfun -> machine -> frame . fp_sp_offset - sp_offset ; fpr_mode = ( TARGET_SINGLE_FLOAT ? SFmode : DFmode ) ; for ( regno = ( FP_REG_LAST - FP_INC + 1 ) ; regno >= FP_REG_FIRST ; regno -= FP_INC ) if ( BITSET_P ( cfun -> machine -> frame . fmask , regno - FP_REG_FIRST ) ) { mips_save_restore_reg ( fpr_mode , regno , offset , fn ) ; offset -= GET_MODE_SIZE ( fpr_mode ) ; } } </s>

Call FN for each register that is saved by the current function . SP_OFFSET is the offset of the current stack pointer from the start of the frame .


<s> Register OutgoingValueHandler :: getStackAddress ( const CCValAssign & VA , MachineMemOperand * & MMO ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; const TargetFrameLowering * TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; LLT p0 = LLT :: pointer ( 0 , 32 ) ; LLT s32 = LLT :: scalar ( 32 ) ; Register SPReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildCopy ( SPReg , Register ( Mips :: SP ) ) ; Register OffsetReg = MRI . createGenericVirtualRegister ( s32 ) ; unsigned Offset = VA . getLocMemOffset ( ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; Register AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildPtrAdd ( AddrReg , SPReg , OffsetReg ) ; MachinePointerInfo MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ; unsigned Size = alignTo ( VA . getValVT ( ) . getSizeInBits ( ) , 8 ) / 8 ; unsigned Align = MinAlign ( TFL -> getStackAlignment ( ) , Offset ) ; MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , Align ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


Output code for switching uniform-simt state . ENTERING indicates whether we are entering or leaving non-uniform execution region .


<s> unsigned getMaxPrefetchIterationsAhead ( ) const { return MaxPrefetchIterationsAhead ; } </s>

Return the maximum prefetch distance in terms of loop iterations .


<s>
static
void
recombine_stvx_pattern
(
rtx_insn
*
insn
,
del_info
*
to_delete
)
{
rtx
body
=
PATTERN
(
insn
)
;
gcc_assert
(
GET_CODE
(
body
)
==
SET
&&
GET_CODE
(
SET_DEST
(
body
)
)
==
MEM
&&
GET_CODE
(
SET_SRC
(
body
)
)
==
VEC_SELECT
)
;
rtx
mem
=
SET_DEST
(
body
)
;
rtx
base_reg
=
XEXP
(
mem
,
0
)
;
rtx
and_operation
=
find_alignment_op
(
insn
,
base_reg
)
;
if
(
and_operation
!=
0
)
{
rtx
src_reg
=
XEXP
(
SET_SRC
(
body
)
,
0
)
;
df_ref
src_use
;
struct
df_insn_info
*
insn_info
=
DF_INSN_INFO_GET
(
insn
)
;
FOR_EACH_INSN_INFO_USE
(
src_use
,
insn_info
)
{
if
(
!
rtx_equal_p
(
DF_REF_REG
(
src_use
)
,
src_reg
)
)
continue
;
struct
df_link
*
link
=
DF_REF_CHAIN
(
src_use
)
;
if
(
!
link
||
link
->
next
)
break
;
rtx_insn
*
swap_insn
=
DF_REF_INSN
(
link
->
ref
)
;
if
(
!
insn_is_swap_p
(
swap_insn
)
||
insn_is_load_p
(
swap_insn
)
||
insn_is_store_p
(
swap_insn
)
)
break
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace
=
true
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace_insn
=
swap_insn
;
XEXP
(
mem
,
0
)
=
and_operation
;
SET_SRC
(
body
)
=
src_reg
;
INSN_CODE
(
insn
)
=
1
;
df_insn_rescan
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"stvx opportunity found at %d\n"
,
INSN_UID
(
insn
)
)
;
}
}
}
</s>

If INSN is the store for an stvx pattern , put it in canonical form .


<s> bool PPCCTRLoops :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; TM = & TPC -> getTM < PPCTargetMachine > ( ) ; STI = TM -> getSubtargetImpl ( F ) ; TLI = STI -> getTargetLowering ( ) ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; TTI = & getAnalysis < TargetTransformInfoWrapperPass > ( ) . getTTI ( F ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ; LibInfo = TLIP ? & TLIP -> getTLI ( ) : nullptr ; PreserveLCSSA = mustPreserveAnalysisID ( LCSSAID ) ; SchedModel . init ( STI ) ; bool MadeChange = false ; for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) { Loop * L = * I ; if ( ! L -> getParentLoop ( ) ) MadeChange |= convertToCTRLoop ( L ) ; } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool DeadCodeElimination :: isDead ( unsigned R ) const { for ( const MachineOperand & MO : MRI . use_operands ( R ) ) { const MachineInstr * UseI = MO . getParent ( ) ; if ( UseI -> isDebugValue ( ) ) continue ; if ( UseI -> isPHI ( ) ) { assert ( ! UseI -> getOperand ( 0 ) . getSubReg ( ) ) ; Register DR = UseI -> getOperand ( 0 ) . getReg ( ) ; if ( DR == R ) continue ; } return false ; } return true ; } </s>

isDead - Returns true if this is a dead def kill slot .


<s> static void avr_output_progmem_section_asm_op ( const char * data ) { fprintf ( asm_out_file , "\t.section\t%s,\"a\",@progbits\n" , data ) ; } </s>

Unnamed section callback for progmem * .data sections .


<s>
SDValue
LanaiTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
MUL
:
return
LowerMUL
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
case
ISD
::
SETCCE
:
return
LowerSETCCE
(
Op
,
DAG
)
;
case
ISD
::
SRL_PARTS
:
return
LowerSRL_PARTS
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

Lanai
Lanai
ISD::MUL
ISD::BR_CC
ISD::ConstantPool
ISD::GlobalAddress
ISD::BlockAddress
ISD::JumpTable
ISD::SELECT_CC
ISD::SETCC
ISD::SETCCE
ISD::SRL_PARTS
ISD::VASTART
ISD::DYNAMIC_STACKALLOC
ISD::RETURNADDR
ISD::FRAMEADDR
"unimplemented operand"


<s> static bool ix86_swap_binary_operands_p ( enum rtx_code code , machine_mode mode , rtx operands [ ] ) { rtx dst = operands [ 0 ] ; rtx src1 = operands [ 1 ] ; rtx src2 = operands [ 2 ] ; if ( GET_RTX_CLASS ( code ) != RTX_COMM_ARITH && GET_RTX_CLASS ( code ) != RTX_COMM_COMPARE ) return false ; if ( rtx_equal_p ( dst , src1 ) ) return false ; if ( rtx_equal_p ( dst , src2 ) ) return true ; if ( immediate_operand ( src2 , mode ) ) return false ; if ( immediate_operand ( src1 , mode ) ) return true ; if ( MEM_P ( src2 ) ) return false ; if ( MEM_P ( src1 ) ) return true ; return false ; } </s>

Helper function of ix86_fixup_binary_operands to canonicalize operand order . Returns true if the operands should be swapped .


<s> bool AMDGPUPassConfig :: addPreEmitPass ( ) { const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . device ( ) -> getGeneration ( ) <= AMDGPUDeviceInfo :: HD6XXX ) { addPass ( createAMDGPUCFGPreparationPass ( * TM ) ) ; addPass ( createAMDGPUCFGStructurizerPass ( * TM ) ) ; addPass ( createR600EmitClauseMarkers ( * TM ) ) ; addPass ( createR600ExpandSpecialInstrsPass ( * TM ) ) ; addPass ( & FinalizeMachineBundlesID ) ; addPass ( createR600Packetizer ( * TM ) ) ; addPass ( createR600ControlFlowFinalizer ( * TM ) ) ; } else { addPass ( createSILowerControlFlowPass ( * TM ) ) ; } return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
bool
FixupBWInstPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
!
FixupBWInsts
)
return
false
;
this
->
MF
=
&
MF
;
TII
=
MF
.
getSubtarget
<
X86Subtarget
>
(
)
.
getInstrInfo
(
)
;
OptForSize
=
MF
.
getFunction
(
)
->
optForSize
(
)
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
DEBUG
(
dbgs
(
)
<<
"Start X86FixupBWInsts\n"
;
)
;
for
(
auto
&
MBB
:
MF
)
processBasicBlock
(
MF
,
MBB
)
;
DEBUG
(
dbgs
(
)
<<
"End X86FixupBWInsts\n"
;
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


"BPF DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> static inline struct loongarch_abi isa_default_abi ( const struct loongarch_isa * isa ) { struct loongarch_abi abi ; switch ( isa -> fpu ) { case ISA_EXT_FPU64 : if ( isa -> base == ISA_BASE_LA64V100 ) abi . base = ABI_BASE_LP64D ; break ; case ISA_EXT_FPU32 : if ( isa -> base == ISA_BASE_LA64V100 ) abi . base = ABI_BASE_LP64F ; break ; case ISA_EXT_NOFPU : if ( isa -> base == ISA_BASE_LA64V100 ) abi . base = ABI_BASE_LP64S ; break ; default : gcc_unreachable ( ) ; } abi . ext = ABI_EXT_BASE ; return abi ; } </s>

Returns the default ABI for the given instruction set .


<s> static bool is_microcoded_insn ( rtx_insn * insn ) { if ( ! insn || ! NONDEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; if ( rs6000_tune == PROCESSOR_CELL ) return get_attr_cell_micro ( insn ) == CELL_MICRO_ALWAYS ; if ( rs6000_sched_groups && ( rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5 ) ) { enum attr_type type = get_attr_type ( insn ) ; if ( ( type == TYPE_LOAD && get_attr_update ( insn ) == UPDATE_YES && get_attr_sign_extend ( insn ) == SIGN_EXTEND_YES ) || ( ( type == TYPE_LOAD || type == TYPE_STORE ) && get_attr_update ( insn ) == UPDATE_YES && get_attr_indexed ( insn ) == INDEXED_YES ) || type == TYPE_MFCR ) return true ; } return false ; } </s>

The function returns a true if INSN is microcoded . Return false otherwise .


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> static int riscv_flatten_aggregate_argument ( const_tree type , riscv_aggregate_field fields [ 2 ] ) { if ( ! type || TREE_CODE ( type ) != RECORD_TYPE ) return - 1 ; return riscv_flatten_aggregate_field ( type , fields , 0 , 0 ) ; } </s>

Identify candidate aggregates for passing in floating-point registers . Candidates have at most two fields after flattening .


<s> void MSP430RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned BasePtr = ( TFI -> hasFP ( MF ) ? MSP430 :: FPW : MSP430 :: SPW ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; Offset += 2 ; if ( ! TFI -> hasFP ( MF ) ) Offset += MF . getFrameInfo ( ) -> getStackSize ( ) ; else Offset += 2 ; Offset += MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ; if ( MI . getOpcode ( ) == MSP430 :: ADD16ri ) { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MI . setDesc ( TII . get ( MSP430 :: MOV16rr ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; if ( Offset == 0 ) return ; unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ; if ( Offset < 0 ) BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( MSP430 :: SUB16ri ) , DstReg ) . addReg ( DstReg ) . addImm ( - Offset ) ; else BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( MSP430 :: ADD16ri ) , DstReg ) . addReg ( DstReg ) . addImm ( Offset ) ; return ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool empty ( ) const { return List . empty ( ) ; } </s>

Determine whether this version information is empty ( e.g. , all version components are zero ) .


<s> MCSection * MipsTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , unsigned & Align , const GlobalObject * GO ) const { if ( IsConstantInSmallSection ( DL , C , * TM ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: getSectionForConstant ( DL , Kind , C , Align , GO ) ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> static rtx mips_function_value ( const_tree valtype , const_tree fn_decl_or_type , bool outgoing ATTRIBUTE_UNUSED ) { return mips_function_value_1 ( valtype , fn_decl_or_type , VOIDmode ) ; } </s>

Implement FUNCTION_VALUE and LIBCALL_VALUE . For normal calls , VALTYPE is the return type and MODE is VOIDmode . For libcalls , VALTYPE is null and MODE is the mode of the return value .


<s> bool X86InstrInfo :: shouldScheduleLoadsNear ( SDNode * Load1 , SDNode * Load2 , int64_t Offset1 , int64_t Offset2 , unsigned NumLoads ) const { assert ( Offset2 > Offset1 ) ; if ( ( Offset2 - Offset1 ) / 8 > 64 ) return false ; unsigned Opc1 = Load1 -> getMachineOpcode ( ) ; unsigned Opc2 = Load2 -> getMachineOpcode ( ) ; if ( Opc1 != Opc2 ) return false ; switch ( Opc1 ) { default : break ; case X86 :: LD_Fp32m : case X86 :: LD_Fp64m : case X86 :: LD_Fp80m : case X86 :: MMX_MOVD64rm : case X86 :: MMX_MOVQ64rm : return false ; } EVT VT = Load1 -> getValueType ( 0 ) ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : if ( TM . getSubtargetImpl ( ) -> is64Bit ( ) ) { if ( NumLoads >= 3 ) return false ; } else if ( NumLoads ) { return false ; } break ; case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : case MVT :: i64 : case MVT :: f32 : case MVT :: f64 : if ( NumLoads ) return false ; break ; } return true ; } </s>

shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine ( in conjunction with areLoadsFromSameBasePtr ) if two loads should be scheduled togther .


<s> bool OptimizePICCall :: runOnMachineFunction ( MachineFunction & F ) { if ( F . getSubtarget < MipsSubtarget > ( ) . inMips16Mode ( ) ) return false ; MachineDominatorTree * MDT = & getAnalysis < MachineDominatorTree > ( ) ; bool Changed = false ; SmallVector < MBBInfo , 8 > WorkList ( 1 , MBBInfo ( MDT -> getRootNode ( ) ) ) ; while ( ! WorkList . empty ( ) ) { MBBInfo & MBBI = WorkList . back ( ) ; if ( MBBI . isVisited ( ) ) { MBBI . postVisit ( ) ; WorkList . pop_back ( ) ; continue ; } MBBI . preVisit ( ScopedHT ) ; Changed |= visitNode ( MBBI ) ; const MachineDomTreeNode * Node = MBBI . getNode ( ) ; WorkList . append ( Node -> begin ( ) , Node -> end ( ) ) ; } return Changed ; } </s>


<s> void pa_d_target_versions ( void ) { if ( TARGET_64BIT ) d_add_builtin_version ( "HPPA64" ) ; else d_add_builtin_version ( "HPPA" ) ; if ( TARGET_SOFT_FLOAT ) d_add_builtin_version ( "D_SoftFloat" ) ; else d_add_builtin_version ( "D_HardFloat" ) ; } </s>

Implement TARGET_D_CPU_VERSIONS for HPPA targets .


<s> static void s390_end_pool ( struct constant_pool * pool , rtx insn ) { rtx pool_size = GEN_INT ( pool -> size + 8 ) ; if ( ! insn ) insn = get_last_insn ( ) ; pool -> pool_insn = emit_insn_after ( gen_pool ( pool_size ) , insn ) ; INSN_ADDRESSES_NEW ( pool -> pool_insn , - 1 ) ; } </s>

End range of instructions covered by POOL at INSN and emit placeholder insn representing the pool .


"loadRegFromStackSlot should not be called for PTX"

Load the specified register of the given register class from the specified stack frame index .


<s> bool isScalarFPTypeInSSEReg ( MVT VT ) const { return ( VT == MVT :: f64 && X86ScalarSSEf64 ) || ( VT == MVT :: f32 && X86ScalarSSEf32 ) ; } </s>

Return true if the specified scalar FP type is computed in an SSE register , not on the X87 floating point stack .


<s> int gen_v9_scc ( enum rtx_code compare_code , register rtx * operands ) { rtx temp , op0 , op1 ; if ( ! TARGET_ARCH64 && ( GET_MODE ( sparc_compare_op0 ) == DImode || GET_MODE ( operands [ 0 ] ) == DImode ) ) return 0 ; op0 = sparc_compare_op0 ; op1 = sparc_compare_op1 ; if ( TARGET_ARCH64 && GET_MODE_CLASS ( GET_MODE ( op0 ) ) == MODE_INT && op1 == const0_rtx && v9_regcmp_p ( compare_code ) ) { if ( compare_code == NE && GET_MODE ( operands [ 0 ] ) == DImode && rtx_equal_p ( op0 , operands [ 0 ] ) ) { emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , gen_rtx_IF_THEN_ELSE ( DImode , gen_rtx_fmt_ee ( compare_code , DImode , op0 , const0_rtx ) , const1_rtx , operands [ 0 ] ) ) ) ; return 1 ; } if ( reg_overlap_mentioned_p ( operands [ 0 ] , op0 ) ) { op0 = gen_reg_rtx ( GET_MODE ( sparc_compare_op0 ) ) ; emit_move_insn ( op0 , sparc_compare_op0 ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , const0_rtx ) ) ; if ( GET_MODE ( op0 ) != DImode ) { temp = gen_reg_rtx ( DImode ) ; convert_move ( temp , op0 , 0 ) ; } else temp = op0 ; emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , gen_rtx_IF_THEN_ELSE ( GET_MODE ( operands [ 0 ] ) , gen_rtx_fmt_ee ( compare_code , DImode , temp , const0_rtx ) , const1_rtx , operands [ 0 ] ) ) ) ; return 1 ; } else { operands [ 1 ] = gen_compare_reg ( compare_code , op0 , op1 ) ; switch ( GET_MODE ( operands [ 1 ] ) ) { case CCmode : case CCXmode : case CCFPEmode : case CCFPmode : break ; default : gcc_unreachable ( ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , const0_rtx ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , gen_rtx_IF_THEN_ELSE ( GET_MODE ( operands [ 0 ] ) , gen_rtx_fmt_ee ( compare_code , GET_MODE ( operands [ 1 ] ) , operands [ 1 ] , const0_rtx ) , const1_rtx , operands [ 0 ] ) ) ) ; return 1 ; } } </s>

This function is used for v9 only . CODE is the code for an Scc 's comparison . OPERANDS [ 0 ] is the target of the Scc insn . OPERANDS [ 1 ] is the value we compare against const0_rtx ( which has n't been generated yet ) . This function is needed to turn ( set ( reg : SI 110 ) ( gt ( reg : CCX 100 % icc ) ( const_int 0 ) ) ) into ( set ( reg : SI 110 ) ( gt : DI ( reg : CCX 100 % icc ) ( const_int 0 ) ) ) IE : The instruction recognizer needs to see the mode of the comparison to find the right instruction . We could use `` gt : DI '' right in the define_expand , but leaving it out allows us to handle DI , SI , etc . We refer to the global sparc compare operands sparc_compare_op0 and sparc_compare_op1 .


<s> std :: pair < unsigned , const TargetRegisterClass * > XCoreTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'r' : return std :: make_pair ( 0U , & XCore :: GRRegsRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


"missing value in %<target()%> pragma or attribute"

"invalid feature modifier %s of value (\"%s\") in "

Parse an architecture extensions target attribute string specified in STR . For example `` +fp+nosimd '' . Show any errors if needed . Return TRUE if successful . Update aarch64_isa_flags to reflect the ISA features modified . PRAGMA_OR_ATTR is used in potential error messages .


<s> static int c_prefix ( const char * str ) { static const char * const prefixes [ ] = { "attiny" , "atmega" , "atxmega" , "ata" , "at90" } ; int i , n = ( int ) ( sizeof ( prefixes ) / sizeof ( * prefixes ) ) ; for ( i = 0 ; i < n ; i ++ ) if ( str_prefix_p ( str , prefixes [ i ] ) ) return i ; return n ; } </s>

Used by string comparator to group MCUs by their name prefix like `` attiny '' or `` atmega '' .

avr "attiny" "atmega" "atxmega" "ata" "at90" 0


<s> void cris_conditional_register_usage ( ) { if ( flag_pic ) fixed_regs [ PIC_OFFSET_TABLE_REGNUM ] = call_used_regs [ PIC_OFFSET_TABLE_REGNUM ] = 1 ; } </s>


<s> static Mfix * create_csky_fix_barrier ( Mfix * fix , Mfix * fix_next , HOST_WIDE_INT max_address ) { rtx_barrier * barrier ; rtx_insn * from = ( fix ? fix -> insn : get_insns ( ) ) ; rtx_insn * selected = NULL ; int selected_cost ; HOST_WIDE_INT selected_address = 0 ; Mfix * new_fix ; HOST_WIDE_INT count = ( fix ? fix -> address : 0 ) ; HOST_WIDE_INT max_count = max_address ; rtx_code_label * label = gen_label_rtx ( ) ; selected_cost = get_csky_barrier_cost ( from ) ; while ( from && count < max_count ) { int new_cost ; rtx_jump_table_data * table ; count += get_attr_length ( from ) ; if ( tablejump_p ( from , NULL , & table ) ) { count += get_csky_jump_table_size ( table ) ; new_cost = get_csky_barrier_cost ( from ) ; if ( count < max_count && ( ! selected || new_cost <= selected_cost ) ) { selected = table ; selected_cost = new_cost ; selected_address = count ; } from = NEXT_INSN ( table ) ; continue ; } new_cost = get_csky_barrier_cost ( from ) ; if ( count < max_count && ( ! selected || new_cost <= selected_cost ) ) { selected = from ; selected_cost = new_cost ; selected_address = count ; } from = NEXT_INSN ( from ) ; } gcc_assert ( selected ) ; from = emit_jump_insn_after ( gen_jump ( label ) , selected ) ; JUMP_LABEL ( from ) = label ; barrier = emit_barrier_after ( from ) ; emit_label_after ( label , barrier ) ; new_fix = ( Mfix * ) obstack_alloc ( & minipool_obstack , sizeof ( * new_fix ) ) ; new_fix -> insn = barrier ; new_fix -> address = selected_address ; if ( fix ) { new_fix -> next = fix -> next ; fix -> next = new_fix ; } else new_fix -> next = fix_next ; return new_fix ; } </s>

Find the best place in the insn stream in the range ( FIX- > address , MAX_ADDRESS ) to forcibly insert a minipool barrier . Create the barrier by inserting a jump and add a new fix entry for it .


<s> bool WebAssemblyFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const auto * RegInfo = MF . getSubtarget < WebAssemblySubtarget > ( ) . getRegisterInfo ( ) ; return MFI -> isFrameAddressTaken ( ) || MFI -> hasVarSizedObjects ( ) || MFI -> hasStackMap ( ) || MFI -> hasPatchPoint ( ) || RegInfo -> needsStackRealignment ( MF ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


"Alignment not a multiple of the instruction size:"

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> unsigned PPCRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; if ( ! TM . isPPC64 ( ) ) return TFI -> hasFP ( MF ) ? PPC :: R31 : PPC :: R1 ; else return TFI -> hasFP ( MF ) ? PPC :: X31 : PPC :: X1 ; } </s>


<s> static bool aarch64_evpc_ext ( struct expand_vec_perm_d * d ) { unsigned int i , nelt = d -> nelt ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; rtx offset ; unsigned int location = d -> perm [ 0 ] ; for ( i = 1 ; i < nelt ; i ++ ) { unsigned int required = location + i ; if ( d -> one_vector_p ) { required &= ( nelt - 1 ) ; } if ( d -> perm [ i ] != required ) return false ; } switch ( d -> vmode ) { case V16QImode : gen = gen_aarch64_extv16qi ; break ; case V8QImode : gen = gen_aarch64_extv8qi ; break ; case V4HImode : gen = gen_aarch64_extv4hi ; break ; case V8HImode : gen = gen_aarch64_extv8hi ; break ; case V2SImode : gen = gen_aarch64_extv2si ; break ; case V4SImode : gen = gen_aarch64_extv4si ; break ; case V4HFmode : gen = gen_aarch64_extv4hf ; break ; case V8HFmode : gen = gen_aarch64_extv8hf ; break ; case V2SFmode : gen = gen_aarch64_extv2sf ; break ; case V4SFmode : gen = gen_aarch64_extv4sf ; break ; case V2DImode : gen = gen_aarch64_extv2di ; break ; case V2DFmode : gen = gen_aarch64_extv2df ; break ; default : return false ; } if ( d -> testing_p ) return true ; if ( BYTES_BIG_ENDIAN && ( location != 0 ) ) { std :: swap ( d -> op0 , d -> op1 ) ; location = nelt - location ; } offset = GEN_INT ( location ) ; emit_insn ( gen ( d -> target , d -> op0 , d -> op1 , offset ) ) ; return true ; } </s>


<s> unsigned CSKYInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : return 0 ; case CSKY :: ST16B : case CSKY :: ST16H : case CSKY :: ST16W : case CSKY :: ST32B : case CSKY :: ST32H : case CSKY :: ST32W : case CSKY :: FST_S : case CSKY :: FST_D : case CSKY :: f2FST_S : case CSKY :: f2FST_D : case CSKY :: SPILL_CARRY : break ; } if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> static bool iq2000_handle_option ( size_t code , const char * arg , int value ATTRIBUTE_UNUSED ) { switch ( code ) { case OPT_mcpu_ : if ( strcmp ( arg , "iq10" ) == 0 ) iq2000_tune = PROCESSOR_IQ10 ; else if ( strcmp ( arg , "iq2000" ) == 0 ) iq2000_tune = PROCESSOR_IQ2000 ; else return false ; return true ; case OPT_march_ : return ( strcmp ( arg , "default" ) == 0 || strcmp ( arg , "DEFAULT" ) == 0 || strcmp ( arg , "iq2000" ) == 0 ) ; default : return true ; } } </s>


<s> static rtx eco32_function_arg ( cumulative_args_t cum_v , enum machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( targetm . calls . must_pass_in_stack ( mode , type ) ) return NULL_RTX ; if ( ! named || ( * cum >= ECO32_NUM_ARG_REGS ) ) return NULL_RTX ; return gen_rtx_REG ( mode , * cum + ECO32_FIRST_ARG_REGNO ) ; } </s>

On the ECO32 the first ECO32_MAX_PARM_REGS args are normally in registers and the rest are pushed .


<s> bool ShouldShrinkFPConstant ( EVT VT ) const { return VT != MVT :: f128 ; } </s>

If true , then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime .


<s> void OutgoingValueHandler :: assignValueToAddress ( Register ValVReg , const CCValAssign & VA ) { MachineMemOperand * MMO ; Register Addr = getStackAddress ( VA , MMO ) ; Register ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildStore ( ExtReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> bool AArch64RegisterInfo :: isConstantPhysReg ( MCRegister PhysReg ) const { return PhysReg == AArch64 :: WZR || PhysReg == AArch64 :: XZR ; } </s>

Returns true if PhysReg is unallocatable and constant throughout the function .


"This resolveFrameIndex does not support Thumb1!"

"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> int SparcFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const SparcSubtarget & Subtarget = MF . getSubtarget < SparcSubtarget > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const SparcRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; const SparcMachineFunctionInfo * FuncInfo = MF . getInfo < SparcMachineFunctionInfo > ( ) ; bool isFixed = MFI . isFixedObjectIndex ( FI ) ; bool UseFP ; if ( FuncInfo -> isLeafProc ( ) ) { UseFP = false ; } else if ( isFixed ) { UseFP = true ; } else if ( RegInfo -> needsStackRealignment ( MF ) ) { UseFP = false ; } else { UseFP = true ; } int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) + Subtarget . getStackPointerBias ( ) ; if ( UseFP ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FrameOffset ; } else { FrameReg = SP :: O6 ; return FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ; } } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .

Sparc Sparc Sparc Sparc Sparc Sparc Sparc SP::O6


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Hexagon Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> Register SystemZRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const SystemZFrameLowering * TFI = getFrameLowering ( MF ) ; const SystemZSubtarget * Subtarget = & MF . getSubtarget < SystemZSubtarget > ( ) ; SystemZCallingConventionRegisters * Regs = Subtarget -> getSpecialRegisters ( ) ; return TFI -> hasFP ( MF ) ? Regs -> getFramePointerRegister ( ) : Regs -> getStackPointerRegister ( ) ; } </s>

SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ


<s>
SDValue
RISCVTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
analyzeOutputArgs
(
DAG
.
getMachineFunction
(
)
,
CCInfo
,
Outs
,
true
,
nullptr
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
<
e
;
++
i
)
{
SDValue
Val
=
OutVals
[
i
]
;
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
assert
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
Full
&&
"Unexpected CCValAssign::LocInfo"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
Val
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
{
RetOps
.
push_back
(
Flag
)
;
}
return
DAG
.
getNode
(
RISCVISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static rtx rs6000_adjust_atomic_subword ( rtx orig_mem , rtx * pshift , rtx * pmask ) { rtx addr , align , shift , mask , mem ; HOST_WIDE_INT shift_mask ; machine_mode mode = GET_MODE ( orig_mem ) ; shift_mask = ( mode == QImode ? 0x18 : 0x10 ) ; addr = XEXP ( orig_mem , 0 ) ; addr = force_reg ( GET_MODE ( addr ) , addr ) ; align = expand_simple_binop ( Pmode , AND , addr , GEN_INT ( - 4 ) , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; mem = gen_rtx_MEM ( SImode , align ) ; MEM_VOLATILE_P ( mem ) = MEM_VOLATILE_P ( orig_mem ) ; if ( MEM_ALIAS_SET ( orig_mem ) == ALIAS_SET_MEMORY_BARRIER ) set_mem_alias_set ( mem , ALIAS_SET_MEMORY_BARRIER ) ; shift = gen_reg_rtx ( SImode ) ; addr = gen_lowpart ( SImode , addr ) ; rtx tmp = gen_reg_rtx ( SImode ) ; emit_insn ( gen_ashlsi3 ( tmp , addr , GEN_INT ( 3 ) ) ) ; emit_insn ( gen_andsi3 ( shift , tmp , GEN_INT ( shift_mask ) ) ) ; if ( BYTES_BIG_ENDIAN ) shift = expand_simple_binop ( SImode , XOR , shift , GEN_INT ( shift_mask ) , shift , 1 , OPTAB_LIB_WIDEN ) ; * pshift = shift ; mask = expand_simple_binop ( SImode , ASHIFT , GEN_INT ( GET_MODE_MASK ( mode ) ) , shift , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; * pmask = mask ; return mem ; } </s>

A subroutine of the various atomic expanders . For sub-word operations , we must adjust things to operate on SImode . Given the original MEM , return a new aligned memory . Also build and return the quantities by which to shift and mask .


<s> static unsigned int arc_autovectorize_vector_modes ( vector_modes * modes , bool ) { if ( TARGET_PLUS_QMACW ) { modes -> quick_push ( V4HImode ) ; modes -> quick_push ( V2HImode ) ; } return 0 ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LoopInfo > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> int compare_eq_p ( rtx insn ) { RTX_CODE cond = compare_condition ( insn ) ; return ( cond == EQ || cond == NE ) ; } </s>

Returns nonzero if INSN is a compare insn with the EQ or NE condition .


<s> bool MipsCallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < Register > VRegs ) const { MachineInstrBuilder Ret = MIRBuilder . buildInstrNoInsert ( Mips :: RetRA ) ; if ( Val != nullptr && ! isSupportedReturnType ( Val -> getType ( ) ) ) return false ; if ( ! VRegs . empty ( ) ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const MipsTargetLowering & TLI = * getTLI < MipsTargetLowering > ( ) ; SmallVector < ArgInfo , 8 > RetInfos ; SmallVector < unsigned , 8 > OrigArgIndices ; ArgInfo ArgRetInfo ( VRegs , Val -> getType ( ) ) ; setArgFlags ( ArgRetInfo , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( DL , ArgRetInfo , 0 , RetInfos , OrigArgIndices ) ; SmallVector < ISD :: OutputArg , 8 > Outs ; subTargetRegTypeForCallingConv ( F , RetInfos , OrigArgIndices , Outs ) ; SmallVector < CCValAssign , 16 > ArgLocs ; MipsCCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , TLI . CCAssignFnForReturn ( ) ) ; setLocInfo ( ArgLocs , Outs ) ; OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , Ret ) ; if ( ! RetHandler . handle ( ArgLocs , RetInfos ) ) { return false ; } } MIRBuilder . insertInstr ( Ret ) ; return true ; } </s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> void function_builder :: register_function_group ( const function_group_info & group ) { ( * group . shape ) -> build ( * this , group ) ; } </s>


<s> const TargetRegisterClass * X86RegisterInfo :: getGPRsForTailCall ( const MachineFunction & MF ) const { const Function & F = MF . getFunction ( ) ; if ( IsWin64 || ( F . getCallingConv ( ) == CallingConv :: Win64 ) ) return & X86 :: GR64_TCW64RegClass ; else if ( Is64Bit ) return & X86 :: GR64_TCRegClass ; bool hasHipeCC = ( F . getCallingConv ( ) == CallingConv :: HiPE ) ; if ( hasHipeCC ) return & X86 :: GR32RegClass ; return & X86 :: GR32_TCRegClass ; } </s>

getGPRsForTailCall - Returns a register class with registers that can be used in forming tail calls .


<s> bool NVPTXAllocaHoisting :: runOnFunction ( Function & function ) { bool functionModified = false ; Function :: iterator I = function . begin ( ) ; TerminatorInst * firstTerminatorInst = ( I ++ ) -> getTerminator ( ) ; for ( Function :: iterator E = function . end ( ) ; I != E ; ++ I ) { for ( BasicBlock :: iterator BI = I -> begin ( ) , BE = I -> end ( ) ; BI != BE ; ) { AllocaInst * allocaInst = dyn_cast < AllocaInst > ( BI ++ ) ; if ( allocaInst && isa < ConstantInt > ( allocaInst -> getArraySize ( ) ) ) { allocaInst -> moveBefore ( firstTerminatorInst ) ; functionModified = true ; } } } return functionModified ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static bool classof ( const AArch64MCExpr * E ) { return E -> getKind ( ) == VK_AUTH || E -> getKind ( ) == VK_AUTHADDR ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> static inline unsigned long ia64_rse_num_regs ( unsigned long * bspstore , unsigned long * bsp ) { unsigned long slots = ( bsp - bspstore ) ; return slots - ( ia64_rse_slot_num ( bspstore ) + slots ) / 0x40 ; } </s>

Calculate the number of registers in the dirty partition starting at BSPSTORE with a size of DIRTY bytes . This is n't simply DIRTY divided by eight because the 64th slot is used to store ar.rnat .


<s> virtual const AZPRSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> FastISel * ARM :: createFastISel ( FunctionLoweringInfo & funcInfo ) { const TargetMachine & TM = funcInfo . MF -> getTarget ( ) ; const ARMSubtarget * Subtarget = & TM . getSubtarget < ARMSubtarget > ( ) ; if ( Subtarget -> isTargetIOS ( ) && ! Subtarget -> isThumb1Only ( ) && ! DisableARMFastISel ) return new ARMFastISel ( funcInfo ) ; return 0 ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .

ARM ARM::createFastISel ARM ARM ARM ARM 0


<s> void MipsSEFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; const MipsSEInstrInfo & TII = * static_cast < const MipsSEInstrInfo * > ( STI . getInstrInfo ( ) ) ; const MipsRegisterInfo & RegInfo = * static_cast < const MipsRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; unsigned SP = ABI . GetStackPtr ( ) ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned ZERO = ABI . GetNullPtr ( ) ; unsigned MOVE = ABI . GetGPRMoveOp ( ) ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI . getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , DL , TII . get ( MOVE ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( MipsFI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = ABI . ArePtrs64bit ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI . getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = 0 ; J < 4 ; ++ J ) { TII . loadRegFromStackSlot ( MBB , I , ABI . GetEhDataReg ( J ) , MipsFI -> getEhDataRegFI ( J ) , RC , & RegInfo ) ; } } if ( MF . getFunction ( ) . hasFnAttribute ( "interrupt" ) ) emitInterruptEpilogueStub ( MF , MBB ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize , MBB , MBBI ) ; } </s>

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips 0 Mips Mips::GPR64RegClass Mips::GPR32RegClass 0 0 4 Mips "interrupt"


<s> bool RISCVAsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { if ( Fixup . getKind ( ) >= FirstLiteralRelocationKind ) return true ; switch ( Fixup . getTargetKind ( ) ) { default : break ; case FK_Data_1 : case FK_Data_2 : case FK_Data_4 : case FK_Data_8 : if ( Target . isAbsolute ( ) ) return false ; break ; case RISCV :: fixup_riscv_got_hi20 : case RISCV :: fixup_riscv_tls_got_hi20 : case RISCV :: fixup_riscv_tls_gd_hi20 : case RISCV :: fixup_riscv_captab_pcrel_hi20 : case RISCV :: fixup_riscv_tls_ie_captab_pcrel_hi20 : case RISCV :: fixup_riscv_tls_gd_captab_pcrel_hi20 : return true ; } return STI . getFeatureBits ( ) [ RISCV :: FeatureRelax ] || ForceRelocs ; } </s>

Hook to check if a relocation is needed for some target specific reason .


<s>
static
rtx
riscv_expand_builtin_insn
(
enum
insn_code
icode
,
unsigned
int
n_ops
,
struct
expand_operand
*
ops
,
bool
has_target_p
)
{
if
(
!
maybe_expand_insn
(
icode
,
n_ops
,
ops
)
)
{
error
(
"invalid argument to built-in function"
)
;
return
has_target_p
gen_reg_rtx
(
ops
[
0
]
.
mode
)
:
const0_rtx
;
}
return
has_target_p
ops
[
0
]
.
value
:
const0_rtx
;
}
</s>

Expand instruction ICODE as part of a built-in function sequence . Use the first NOPS elements of OPS as the instruction 's operands . HAS_TARGET_P is true if operand 0 is a target ; it is false if the instruction has no target . Return the target rtx if HAS_TARGET_P , otherwise return const0_rtx .


<s> bool DirectXTargetMachine :: addPassesToEmitFile ( PassManagerBase & PM , raw_pwrite_stream & Out , raw_pwrite_stream * DwoOut , CodeGenFileType FileType , bool DisableVerify , MachineModuleInfoWrapperPass * MMIWP ) { PM . add ( createDXILOpLoweringLegacyPass ( ) ) ; PM . add ( createDXILPrepareModulePass ( ) ) ; PM . add ( createDXILTranslateMetadataPass ( ) ) ; switch ( FileType ) { case CGFT_AssemblyFile : PM . add ( createPrintModulePass ( Out , "" , true ) ) ; break ; case CGFT_ObjectFile : PM . add ( createDXILWriterPass ( Out ) ) ; break ; case CGFT_Null : break ; } return false ; } </s>

Add passes to the specified pass manager to get the specified file emitted .


"created and used with different architectures / ABIs"

"created and used with different endianness"


"Found `main` function with incorrect type: "

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> static int vfp_emit_fstmx ( int base_reg , int count ) { rtx par ; rtx dwarf ; rtx tmp , reg ; int i ; if ( count == 2 && ! arm_arch6 ) { if ( base_reg == LAST_VFP_REGNUM - 3 ) base_reg -= 2 ; count ++ ; } par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; dwarf = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( count + 1 ) ) ; reg = gen_rtx_REG ( DFmode , base_reg ) ; base_reg += 2 ; XVECEXP ( par , 0 , 0 ) = gen_rtx_SET ( VOIDmode , gen_frame_mem ( BLKmode , gen_rtx_PRE_DEC ( BLKmode , stack_pointer_rtx ) ) , gen_rtx_UNSPEC ( BLKmode , gen_rtvec ( 1 , reg ) , UNSPEC_PUSH_MULT ) ) ; tmp = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , gen_rtx_PLUS ( SImode , stack_pointer_rtx , GEN_INT ( - ( count * 8 + 4 ) ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , 0 ) = tmp ; tmp = gen_rtx_SET ( VOIDmode , gen_frame_mem ( DFmode , stack_pointer_rtx ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , 1 ) = tmp ; for ( i = 1 ; i < count ; i ++ ) { reg = gen_rtx_REG ( DFmode , base_reg ) ; base_reg += 2 ; XVECEXP ( par , 0 , i ) = gen_rtx_USE ( VOIDmode , reg ) ; tmp = gen_rtx_SET ( VOIDmode , gen_frame_mem ( DFmode , gen_rtx_PLUS ( SImode , stack_pointer_rtx , GEN_INT ( i * 8 ) ) ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , i + 1 ) = tmp ; } par = emit_insn ( par ) ; REG_NOTES ( par ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , dwarf , REG_NOTES ( par ) ) ; RTX_FRAME_RELATED_P ( par ) = 1 ; return count * 8 + 4 ; } </s>

Emit RTL to save block of VFP register pairs to the stack . Returns the number of bytes pushed .


<s> unsigned RISCVInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : return 0 ; case RISCV :: LB : case RISCV :: LBU : case RISCV :: LH : case RISCV :: LHU : case RISCV :: LW : case RISCV :: FLW : case RISCV :: LWU : case RISCV :: LD : case RISCV :: FLD : case RISCV :: VLE_V_um : break ; } if ( ( MI . getOpcode ( ) == RISCV :: VLE_V_um ) && MI . getOperand ( 1 ) . isFI ( ) ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } else if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> const uint32_t * PPCRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; if ( CC == CallingConv :: AnyReg ) { if ( Subtarget . hasVSX ( ) ) return CSR_64_AllRegs_VSX_RegMask ; if ( Subtarget . hasAltivec ( ) ) return CSR_64_AllRegs_Altivec_RegMask ; return CSR_64_AllRegs_RegMask ; } if ( Subtarget . isAIXABI ( ) ) { return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_PPC64_Altivec_RegMask : CSR_PPC64_RegMask ) : ( Subtarget . hasAltivec ( ) ? CSR_AIX32_Altivec_RegMask : CSR_AIX32_RegMask ) ; } if ( CC == CallingConv :: Cold ) { return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_SVR64_ColdCC_Altivec_RegMask : CSR_SVR64_ColdCC_RegMask ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR32_ColdCC_Altivec_RegMask : ( Subtarget . hasSPE ( ) ? CSR_SVR32_ColdCC_SPE_RegMask : CSR_SVR32_ColdCC_RegMask ) ) ; } return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_PPC64_Altivec_RegMask : CSR_PPC64_RegMask ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR432_Altivec_RegMask : ( Subtarget . hasSPE ( ) ? CSR_SVR432_SPE_RegMask : CSR_SVR432_RegMask ) ) ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .

PowerPC PPC PPC PPC PPC PPC PPC PPC PPC PPC PPC


<s> void sparc_d_register_target_info ( void ) { const struct d_target_info_spec handlers [ ] = { { "floatAbi" , sparc_d_handle_target_float_abi } , { NULL , NULL } , } ; d_add_target_info_handlers ( handlers ) ; } </s>


<s> bool TriCorePassConfig :: addPreISel ( ) { return false ; } </s>


<s> static rtx mips_prepare_builtin_target ( enum insn_code icode , unsigned int op , rtx target ) { enum machine_mode mode ; mode = insn_data [ icode ] . operand [ op ] . mode ; if ( target == 0 || ! insn_data [ icode ] . operand [ op ] . predicate ( target , mode ) ) target = gen_reg_rtx ( mode ) ; return target ; } </s>

Return an rtx suitable for output operand OP of instruction ICODE . If TARGET is non-null , try to use it where possible .


<s> const AVRRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
void
HexagonFrameLowering
::
emitEpilogue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
MachineBasicBlock
::
iterator
MBBI
=
std
::
prev
(
MBB
.
end
(
)
)
;
DebugLoc
dl
=
MBBI
->
getDebugLoc
(
)
;
if
(
hasFP
(
MF
)
||
MF
.
getTarget
(
)
.
getOptLevel
(
)
==
CodeGenOpt
::
)
{
MachineBasicBlock
::
iterator
MBBI
=
std
::
prev
(
MBB
.
end
(
)
)
;
MachineBasicBlock
::
iterator
MBBI_end
=
MBB
.
end
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
if
(
MBBI
->
getOpcode
(
)
==
Hexagon
::
EH_RETURN_JMPR
)
{
assert
(
MBBI
->
getOperand
(
0
)
.
isReg
(
)
&&
"Offset should be in register!"
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Hexagon
::
L2_deallocframe
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Hexagon
::
A2_add
)
,
Hexagon
::
R29
)
.
addReg
(
Hexagon
::
R29
)
.
addReg
(
Hexagon
::
R28
)
;
return
;
}
if
(
MBBI
->
getOpcode
(
)
==
Hexagon
::
JMPret
&&
!
DisableDeallocRet
)
{
MachineBasicBlock
::
iterator
BeforeJMPR
=
MBB
.
begin
(
)
==
MBBI
MBBI
:
std
::
prev
(
MBBI
)
;
if
(
BeforeJMPR
!=
MBBI
&&
BeforeJMPR
->
getOpcode
(
)
==
Hexagon
::
RESTORE_DEALLOC_RET_JMP_V4
)
{
MBB
.
erase
(
MBBI
)
;
return
;
}
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MBBI_end
,
dl
,
TII
.
get
(
Hexagon
::
L4_return
)
)
;
MIB
->
copyImplicitOps
(
*
MBB
.
getParent
(
)
,
&
*
MBBI
)
;
MBB
.
erase
(
MBBI
)
;
}
else
{
MachineBasicBlock
::
iterator
Term
=
MBB
.
getFirstTerminator
(
)
;
MachineBasicBlock
::
iterator
I
=
Term
==
MBB
.
begin
(
)
MBB
.
end
(
)
:
std
::
prev
(
Term
)
;
if
(
I
!=
MBB
.
end
(
)
&&
I
->
getOpcode
(
)
==
Hexagon
::
RESTORE_DEALLOC_BEFORE_TAILCALL_V4
)
return
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Hexagon
::
L2_deallocframe
)
)
;
}
}
}
</s>


<s> const NVPTXTargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


<s>
int
M68kRegisterInfo
::
getSpillRegisterOrder
(
unsigned
Reg
)
const
{
int
Result
=
getRegisterOrder
(
Reg
,
*
getRegClass
(
M68k
::
SPILLRegClassID
)
)
;
assert
(
Result
>=
0
&&
"Can not determine spill order"
)
;
return
Result
;
}
</s>

Return spill order index of a register , if there is none then trap .


<s> void PPCPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { initializePPCVSXFMAMutatePass ( * PassRegistry :: getPassRegistry ( ) ) ; insertPass ( VSXFMAMutateEarly ? & RegisterCoalescerID : & MachineSchedulerID , & PPCVSXFMAMutateID ) ; } if ( getPPCTargetMachine ( ) . isPositionIndependent ( ) ) { addPass ( & LiveVariablesID ) ; addPass ( createPPCTLSDynamicCallPass ( ) ) ; } if ( EnableExtraTOCRegDeps ) addPass ( createPPCTOCRegDepsPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & MachinePipelinerID ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s>
unsigned
getOffsetReg
(
)
const
{
assert
(
isRegBase
(
)
&&
"Invalid offset register access!"
)
;
return
OffsetReg
;
}
</s>

Get the offset register of the pointer value .


<s> TargetLowering :: ConstraintWeight OR1KTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'O' : if ( isa < ConstantInt > ( CallOperandVal ) ) weight = CW_Constant ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> bool HexagonTargetLowering :: allowsMemoryAccess ( LLVMContext & Context , const DataLayout & DL , EVT VT , unsigned AddrSpace , Align Alignment , MachineMemOperand :: Flags Flags , bool * Fast ) const { MVT SVT = VT . getSimpleVT ( ) ; if ( Subtarget . isHVXVectorType ( SVT , true ) ) return allowsHvxMemoryAccess ( SVT , Flags , Fast ) ; return TargetLoweringBase :: allowsMemoryAccess ( Context , DL , VT , AddrSpace , Alignment , Flags , Fast ) ; } </s>

This function returns true if the memory access is aligned or if the target allows this specific unaligned memory access .


<s> virtual const TLCS900Subtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static int function_arg_partial_bytes ( cumulative_args_t cum_v , machine_mode mode , tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( ( mode == BLKmode || GET_MODE_CLASS ( mode ) != MODE_COMPLEX_INT || GET_MODE_CLASS ( mode ) != MODE_COMPLEX_FLOAT ) && cum -> arg_words < MAX_ARGS_IN_REGISTERS ) { int words ; if ( mode == BLKmode ) words = ( ( int_size_in_bytes ( type ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ) ; else words = ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; if ( words + cum -> arg_words <= MAX_ARGS_IN_REGISTERS ) return 0 ; return ( MAX_ARGS_IN_REGISTERS - cum -> arg_words ) * UNITS_PER_WORD ; } else if ( mode == DImode && cum -> arg_words == MAX_ARGS_IN_REGISTERS - 1 ) return UNITS_PER_WORD ; return 0 ; } </s>

Return number of bytes of argument to put in registers .


<s> bool arc_text_label ( rtx_insn * label ) { rtx_insn * next ; gcc_assert ( GET_CODE ( label ) == CODE_LABEL || ( GET_CODE ( label ) == NOTE && NOTE_KIND ( label ) == NOTE_INSN_DELETED_LABEL ) ) ; next = next_nonnote_insn ( label ) ; if ( next ) return ( ! JUMP_TABLE_DATA_P ( next ) || GET_CODE ( PATTERN ( next ) ) != ADDR_VEC ) ; else if ( ! PREV_INSN ( label ) ) return true ; return false ; } </s>

Return true if LABEL is in executable code .


<s> bool isToken ( ) const override { return Kind == Token ; } </s>


<s> unsigned X86InstrInfo :: isStoreToStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { if ( isFrameStoreOpcode ( MI . getOpcode ( ) ) ) { unsigned Reg ; if ( ( Reg = isStoreToStackSlot ( MI , FrameIndex ) ) ) return Reg ; const MachineMemOperand * Dummy ; return hasStoreToStackSlot ( MI , Dummy , FrameIndex ) ; } return 0 ; } </s>

isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


"This code is for instructions with 3 or less operands"


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { if ( isConditionalBranch ( Inst ) ) { int64_t Imm ; if ( Size == 2 ) Imm = Inst . getOperand ( 1 ) . getImm ( ) ; else Imm = Inst . getOperand ( 2 ) . getImm ( ) ; Target = Addr + Imm ; return true ; } if ( Inst . getOpcode ( ) == RISCV :: C_JAL || Inst . getOpcode ( ) == RISCV :: C_J ) { Target = Addr + Inst . getOperand ( 0 ) . getImm ( ) ; return true ; } if ( Inst . getOpcode ( ) == RISCV :: JAL ) { Target = Addr + Inst . getOperand ( 1 ) . getImm ( ) ; return true ; } return false ; } </s>

Given a branch instruction try to get the address the branch targets .


<s> void VideoCore4FrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; determineFrameLayout ( MF ) ; const VideoCore4InstrInfo & TII = * static_cast < const VideoCore4InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; const VideoCore4RegisterInfo & RI = * static_cast < const VideoCore4RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; MachineBasicBlock :: iterator MI = MBB . begin ( ) ; DebugLoc dl = MI != MBB . end ( ) ? MI -> getDebugLoc ( ) : DebugLoc ( ) ; int stacksize = ( int ) MFI -> getStackSize ( ) ; if ( hasFP ( MF ) ) stacksize += 4 ; TII . adjustStackPtr ( - stacksize , MBB , MI ) ; if ( hasFP ( MF ) ) { unsigned FP = RI . getFrameRegister ( MF ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static void loongarch_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; struct loongarch_arg_info info ; loongarch_get_arg_info ( & info , cum , arg . mode , arg . type , arg . named , false ) ; cum -> num_fprs = info . fpr_offset + info . num_fprs ; cum -> num_gprs = info . gpr_offset + info . num_gprs ; } </s>


"LowerFormalArguments Unhandled argument type: "

"functions with VarArgs or StructRet are not supported"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> void MipsSEInstrInfo :: adjustStackPtr ( unsigned SP , int64_t Amount , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const MipsSubtarget & STI = Subtarget ; DebugLoc DL ; unsigned ADDu = STI . isABI_N64 ( ) ? Mips :: DADDu : Mips :: ADDu ; unsigned ADDiu = STI . isABI_N64 ( ) ? Mips :: DADDiu : Mips :: ADDiu ; if ( Amount == 0 ) return ; if ( isInt < 16 > ( Amount ) ) BuildMI ( MBB , I , DL , get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; else { unsigned Reg = loadImmediate ( Amount , MBB , I , DL , nullptr ) ; BuildMI ( MBB , I , DL , get ( ADDu ) , SP ) . addReg ( SP ) . addReg ( Reg , RegState :: Kill ) ; } } </s>

Mips Mips Mips Mips::DADDu Mips::ADDu Mips::DADDiu Mips::ADDiu 0 16


<s> const uint32_t * RISCVRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { if ( Subtarget . isRV64 ( ) ) if ( Subtarget . hasD ( ) ) return CSR_RV64D_RegMask ; else if ( Subtarget . hasF ( ) ) return CSR_RV64F_RegMask ; else return CSR_RV64_RegMask ; else if ( Subtarget . hasD ( ) ) return CSR_RV32D_RegMask ; else if ( Subtarget . hasF ( ) ) return CSR_RV32F_RegMask ; else return CSR_RV32_RegMask ; } </s>


<s> unsigned SIRegisterInfo :: getRegPressureSetLimit ( const MachineFunction & MF , unsigned Idx ) const { if ( Idx == getVGPRPressureSet ( ) ) return getRegPressureLimit ( & AMDGPU :: VGPR_32RegClass , const_cast < MachineFunction & > ( MF ) ) ; if ( Idx == getSGPRPressureSet ( ) ) return getRegPressureLimit ( & AMDGPU :: SGPR_32RegClass , const_cast < MachineFunction & > ( MF ) ) ; return AMDGPURegisterInfo :: getRegPressureSetLimit ( MF , Idx ) ; } </s>

Get the register unit pressure limit for this dimension .


<s> bool HexagonTargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( Kind . isBSS ( ) || Kind . isData ( ) || Kind . isCommon ( ) ) { Type * Ty = GV -> getType ( ) -> getElementType ( ) ; return IsInSmallSection ( GV -> getParent ( ) -> getDataLayout ( ) . getTypeAllocSize ( Ty ) ) ; } return false ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineModuleInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"AArch64 Condition Optimizer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static bool currently_supported_simd_type ( tree t , tree b ) { if ( COMPLEX_FLOAT_TYPE_P ( t ) ) return false ; if ( TYPE_SIZE ( t ) != TYPE_SIZE ( b ) ) return false ; return supported_simd_type ( t ) ; } </s>

Return true for types that currently are supported as SIMD return or argument types .


<s> void addPreRegAlloc ( ) override { if ( getOptLevel ( ) == CodeGenOpt :: None ) { addPass ( & DeadMachineInstructionElimID ) ; } } </s>


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> const AVRInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> void WebAssemblyPassConfig :: addPostRegAlloc ( ) { disablePass ( & ShrinkWrapID ) ; disablePass ( & MachineCopyPropagationID ) ; disablePass ( & PostRASchedulerID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & StackMapLivenessID ) ; disablePass ( & LiveDebugValuesID ) ; disablePass ( & PatchableFunctionID ) ; TargetPassConfig :: addPostRegAlloc ( ) ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> X86GenInstrInfo :: MachineOutlinerInstrType X86InstrInfo :: getOutliningType ( MachineBasicBlock :: iterator & MIT , unsigned Flags ) const { MachineInstr & MI = * MIT ; if ( MI . isDebugValue ( ) || MI . isIndirectDebugValue ( ) ) return MachineOutlinerInstrType :: Invisible ; if ( isTailCall ( MI ) ) return MachineOutlinerInstrType :: Legal ; if ( MI . isTerminator ( ) || MI . isReturn ( ) ) { if ( MI . getParent ( ) -> succ_empty ( ) ) return MachineOutlinerInstrType :: Legal ; return MachineOutlinerInstrType :: Illegal ; } if ( MI . modifiesRegister ( X86 :: RSP , & RI ) || MI . readsRegister ( X86 :: RSP , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( X86 :: RSP ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( X86 :: RSP ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . readsRegister ( X86 :: RIP , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( X86 :: RIP ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( X86 :: RIP ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . isPosition ( ) ) return MachineOutlinerInstrType :: Illegal ; for ( const MachineOperand & MOP : MI . operands ( ) ) if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return MachineOutlinerInstrType :: Illegal ; return MachineOutlinerInstrType :: Legal ; } </s>

Returns how or if MIT should be outlined .


<s> bool AArch64TargetLowering :: isExtFreeImpl ( const Instruction * Ext ) const { if ( isa < FPExtInst > ( Ext ) ) return false ; if ( Ext -> getType ( ) -> isVectorTy ( ) ) return false ; for ( const Use & U : Ext -> uses ( ) ) { const Instruction * Instr = cast < Instruction > ( U . getUser ( ) ) ; switch ( Instr -> getOpcode ( ) ) { case Instruction :: Shl : if ( ! isa < ConstantInt > ( Instr -> getOperand ( 1 ) ) ) return false ; break ; case Instruction :: GetElementPtr : { gep_type_iterator GTI = gep_type_begin ( Instr ) ; auto & DL = Ext -> getModule ( ) -> getDataLayout ( ) ; std :: advance ( GTI , U . getOperandNo ( ) ) ; Type * IdxTy = * GTI ; uint64_t ShiftAmt = countTrailingZeros ( DL . getTypeStoreSizeInBits ( IdxTy ) ) - 3 ; if ( ShiftAmt == 0 || ShiftAmt > 4 ) return false ; break ; } case Instruction :: Trunc : if ( Instr -> getType ( ) == Ext -> getOperand ( 0 ) -> getType ( ) ) continue ; default : return false ; } } return true ; } </s>

Return true if the extension represented by I is free .


<s> const MCPhysReg * TL45RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CC_Save_SaveList ; } </s>


"density %d%%, cost %d exceeds threshold, penalizing "

Test for likely overcommitment of vector hardware resources . If a loop iteration is relatively large , and too large a percentage of instructions in the loop are vectorized , the cost model may not adequately reflect delays from unavailable vector resources . Penalize the loop body cost for this case .


<s>
void
ARM64FrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
const
TargetFrameLowering
*
TFI
=
MF
.
getTarget
(
)
.
getFrameLowering
(
)
;
const
ARM64InstrInfo
*
TII
=
static_cast
<
const
ARM64InstrInfo
*
>
(
MF
.
getTarget
(
)
.
getInstrInfo
(
)
)
;
if
(
!
TFI
->
hasReservedCallFrame
(
MF
)
)
{
MachineInstr
*
Old
=
I
;
DebugLoc
DL
=
Old
->
getDebugLoc
(
)
;
unsigned
Amount
=
Old
->
getOperand
(
0
)
.
getImm
(
)
;
if
(
Amount
!=
0
)
{
unsigned
Align
=
TFI
->
getStackAlignment
(
)
;
Amount
=
(
Amount
+
Align
1
)
/
Align
*
Align
;
unsigned
Opc
=
Old
->
getOpcode
(
)
;
if
(
Opc
==
ARM64
::
ADJCALLSTACKDOWN
)
{
emitFrameOffset
(
MBB
,
I
,
DL
,
ARM64
::
SP
,
ARM64
::
SP
,
Amount
,
TII
)
;
}
else
{
assert
(
Opc
==
ARM64
::
ADJCALLSTACKUP
&&
"expected ADJCALLSTACKUP"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
ARM64
::
SP
,
ARM64
::
SP
,
Amount
,
TII
)
;
}
}
}
MBB
.
erase
(
I
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> void erasingInstr ( MachineInstr & MI ) override { } </s>


<s> bool PPCTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { if ( ! VT . isSimple ( ) || ! Subtarget . hasVSX ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case MVT :: f32 : case MVT :: f64 : case MVT :: ppcf128 : return Imm . isPosZero ( ) ; } } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> static void mmix_target_asm_function_epilogue ( FILE * stream ) { fputc ( '\n' , stream ) ; } </s>


<s> TargetIRAnalysis ARMBaseTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( const Function & F ) { return TargetTransformInfo ( ARMTTIImpl ( this , F ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


<s> static HOST_WIDE_INT s390_constant_alignment ( const_tree , HOST_WIDE_INT align ) { return MAX ( align , 16 ) ; } </s>

Implement TARGET_CONSTANT_ALIGNMENT . Alignment on even addresses for LARL instruction .


<s> void J2InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MI != MBB . end ( ) ? MI -> getDebugLoc ( ) : DebugLoc ( ) ; BuildMI ( MBB , MI , DL , get ( J2 :: MOV32rm ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) ; } </s>


<s> bool SIInstrInfo :: isBasicBlockPrologue ( const MachineInstr & MI ) const { return ! MI . isTerminator ( ) && MI . getOpcode ( ) != AMDGPU :: COPY && MI . modifiesRegister ( AMDGPU :: EXEC , & RI ) ; } </s>

True if the instruction is bound to the top of its basic block and no other instructions shall be inserted before it .


<s> bool ARMFastISel :: fastLowerArguments ( ) { if ( ! FuncInfo . CanLowerReturn ) return false ; const Function * F = FuncInfo . Fn ; if ( F -> isVarArg ( ) ) return false ; CallingConv :: ID CC = F -> getCallingConv ( ) ; switch ( CC ) { default : return false ; case CallingConv :: Fast : case CallingConv :: C : case CallingConv :: ARM_AAPCS_VFP : case CallingConv :: ARM_AAPCS : case CallingConv :: ARM_APCS : break ; } unsigned Idx = 1 ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( Idx > 4 ) return false ; if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) ) return false ; Type * ArgTy = I -> getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( DL , ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : break ; default : return false ; } } static const uint16_t GPRArgRegs [ ] = { ARM :: R0 , ARM :: R1 , ARM :: R2 , ARM :: R3 } ; const TargetRegisterClass * RC = & ARM :: rGPRRegClass ; Idx = 0 ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { unsigned SrcReg = GPRArgRegs [ Idx ] ; unsigned DstReg = FuncInfo . MF -> addLiveIn ( SrcReg , RC ) ; unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( DstReg , getKillRegState ( true ) ) ; updateValueMap ( I , ResultReg ) ; } return true ; } </s>

This method is called by target-independent code to do target- specific argument lowering .


<s> bool AArch64InstrInfo :: isThroughputPattern ( MachineCombinerPattern Pattern ) const { switch ( Pattern ) { default : break ; case MachineCombinerPattern :: FMULADDS_OP1 : case MachineCombinerPattern :: FMULADDS_OP2 : case MachineCombinerPattern :: FMULSUBS_OP1 : case MachineCombinerPattern :: FMULSUBS_OP2 : case MachineCombinerPattern :: FMULADDD_OP1 : case MachineCombinerPattern :: FMULADDD_OP2 : case MachineCombinerPattern :: FMULSUBD_OP1 : case MachineCombinerPattern :: FMULSUBD_OP2 : case MachineCombinerPattern :: FMLAv1i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv1i32_indexed_OP2 : case MachineCombinerPattern :: FMLAv1i64_indexed_OP1 : case MachineCombinerPattern :: FMLAv1i64_indexed_OP2 : case MachineCombinerPattern :: FMLAv2f32_OP2 : case MachineCombinerPattern :: FMLAv2f32_OP1 : case MachineCombinerPattern :: FMLAv2f64_OP1 : case MachineCombinerPattern :: FMLAv2f64_OP2 : case MachineCombinerPattern :: FMLAv2i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv2i32_indexed_OP2 : case MachineCombinerPattern :: FMLAv2i64_indexed_OP1 : case MachineCombinerPattern :: FMLAv2i64_indexed_OP2 : case MachineCombinerPattern :: FMLAv4f32_OP1 : case MachineCombinerPattern :: FMLAv4f32_OP2 : case MachineCombinerPattern :: FMLAv4i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv4i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv1i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv1i64_indexed_OP2 : case MachineCombinerPattern :: FMLSv2i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv2i64_indexed_OP2 : case MachineCombinerPattern :: FMLSv2f32_OP2 : case MachineCombinerPattern :: FMLSv2f64_OP2 : case MachineCombinerPattern :: FMLSv4i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv4f32_OP2 : return true ; } return false ; } </s>

Return true when a code sequence can improve throughput .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < TPCSubtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool AMDGPUAAResult :: pointsToConstantMemory ( const MemoryLocation & Loc , bool OrLocal ) { const Value * Base = GetUnderlyingObject ( Loc . Ptr , DL ) ; if ( Base -> getType ( ) -> getPointerAddressSpace ( ) == AS . CONSTANT_ADDRESS || Base -> getType ( ) -> getPointerAddressSpace ( ) == AS . CONSTANT_ADDRESS_32BIT ) { return true ; } if ( const GlobalVariable * GV = dyn_cast < GlobalVariable > ( Base ) ) { if ( GV -> isConstant ( ) ) return true ; } else if ( const Argument * Arg = dyn_cast < Argument > ( Base ) ) { const Function * F = Arg -> getParent ( ) ; switch ( F -> getCallingConv ( ) ) { default : return AAResultBase :: pointsToConstantMemory ( Loc , OrLocal ) ; case CallingConv :: AMDGPU_LS : case CallingConv :: AMDGPU_HS : case CallingConv :: AMDGPU_ES : case CallingConv :: AMDGPU_GS : case CallingConv :: AMDGPU_VS : case CallingConv :: AMDGPU_PS : case CallingConv :: AMDGPU_CS : case CallingConv :: AMDGPU_KERNEL : case CallingConv :: SPIR_KERNEL : break ; } unsigned ArgNo = Arg -> getArgNo ( ) ; if ( F -> hasParamAttribute ( ArgNo , Attribute :: NoAlias ) && ( F -> hasParamAttribute ( ArgNo , Attribute :: ReadNone ) || F -> hasParamAttribute ( ArgNo , Attribute :: ReadOnly ) ) ) { return true ; } } return AAResultBase :: pointsToConstantMemory ( Loc , OrLocal ) ; } </s>

A convenience wrapper around the primary pointsToConstantMemory interface .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU


<s>
SDValue
MandarinTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
Op
.
dump
(
)
;
DAG
.
dump
(
)
;
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_VECTOR_ELT
:
return
LowerEXTRACT_VECTOR_ELT
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
case
ISD
::
ConstantPool
:
return
LowerAddress
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> rtx ix86_libcall_value ( machine_mode mode ) { return ix86_function_value_1 ( NULL , NULL , mode , mode ) ; } </s>

Define how to find the value returned by a library function assuming the value has mode MODE .


<s> static bool exact_dependency_1 ( rtx addr , rtx insn ) { enum rtx_code code ; const char * format_ptr ; int i , j ; code = GET_CODE ( insn ) ; switch ( code ) { case MEM : if ( rtx_equal_p ( addr , insn ) ) return true ; break ; case REG : CASE_CONST_ANY : case SYMBOL_REF : case CODE_LABEL : case PC : case EXPR_LIST : return false ; default : break ; } format_ptr = GET_RTX_FORMAT ( code ) ; for ( i = 0 ; i < GET_RTX_LENGTH ( code ) ; i ++ ) { switch ( * format_ptr ++ ) { case 'e' : if ( exact_dependency_1 ( addr , XEXP ( insn , i ) ) ) return true ; break ; case 'E' : for ( j = 0 ; j < XVECLEN ( insn , i ) ; j ++ ) if ( exact_dependency_1 ( addr , XVECEXP ( insn , i , j ) ) ) return true ; break ; } } return false ; } </s>

Helper function for exact_store_load_dependency . Return true if addr is found in insn .


<s> Value * AArch64TargetLowering :: getSSPStackGuardCheck ( const Module & M ) const { if ( Subtarget -> getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) ) return M . getFunction ( "__security_check_cookie" ) ; return TargetLowering :: getSSPStackGuardCheck ( M ) ; } </s>

If the target has a standard stack protection check function that performs validation and error handling , returns the function .


<s> bool isImm ( int64_t MinValue , int64_t MaxValue ) const { return Kind == OpKind_Imm && inRange ( Imm , MinValue , MaxValue ) ; } </s>


<s> void Mips16TargetLowering :: getOpndList ( SmallVectorImpl < SDValue > & Ops , std :: deque < std :: pair < unsigned , SDValue > > & RegsToPass , bool IsPICCall , bool GlobalOrExternal , bool InternalLinkage , CallLoweringInfo & CLI , SDValue Callee , SDValue Chain ) const { SelectionDAG & DAG = CLI . DAG ; const char * Mips16HelperFunction = 0 ; bool NeedMips16Helper = false ; if ( getTargetMachine ( ) . Options . UseSoftFloat && Mips16HardFloat ) { bool LookupHelper = true ; if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( CLI . Callee ) ) { if ( NoHelperNeeded . find ( S -> getSymbol ( ) ) != NoHelperNeeded . end ( ) ) { LookupHelper = false ; } } if ( LookupHelper ) Mips16HelperFunction = getMips16HelperFunction ( CLI . RetTy , CLI . Args , NeedMips16Helper ) ; } SDValue JumpTarget = Callee ; if ( IsPICCall || ! GlobalOrExternal ) { unsigned V0Reg = Mips :: V0 ; if ( NeedMips16Helper ) { RegsToPass . push_front ( std :: make_pair ( V0Reg , Callee ) ) ; JumpTarget = DAG . getExternalSymbol ( Mips16HelperFunction , getPointerTy ( ) ) ; JumpTarget = getAddrGlobal ( JumpTarget , DAG , MipsII :: MO_GOT ) ; } else RegsToPass . push_front ( std :: make_pair ( ( unsigned ) Mips :: T9 , Callee ) ) ; } Ops . push_back ( JumpTarget ) ; MipsTargetLowering :: getOpndList ( Ops , RegsToPass , IsPICCall , GlobalOrExternal , InternalLinkage , CLI , Callee , Chain ) ; } </s>

This function fills Ops , which is the list of operands that will later be used when a function call node is created .

Mips Mips Mips 0 Mips Mips Mips Mips Mips Mips::V0 Mips Mips MipsII::MO_GOT Mips::T9 Mips


<s> bool isLittleEndian ( ) const { return IsLittle ; } </s>

Tests whether the target triple is little endian .


"256-bit vector operations only available in AVX2"

Change the opcode of MI to execute in Domain .


<s> void SystemZTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { if ( Constraint . length ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'I' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isUInt < 8 > ( C -> getZExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getZExtValue ( ) , Op . getValueType ( ) ) ) ; return ; case 'J' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isUInt < 12 > ( C -> getZExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getZExtValue ( ) , Op . getValueType ( ) ) ) ; return ; case 'K' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isInt < 16 > ( C -> getSExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getSExtValue ( ) , Op . getValueType ( ) ) ) ; return ; case 'L' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isInt < 20 > ( C -> getSExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getSExtValue ( ) , Op . getValueType ( ) ) ) ; return ; case 'M' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( C -> getZExtValue ( ) == 0x7fffffff ) Ops . push_back ( DAG . getTargetConstant ( C -> getZExtValue ( ) , Op . getValueType ( ) ) ) ; return ; } } TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; } </s>

Lower the specified operand into the Ops vector .


<s> int compute_plussi_cc ( rtx * operands ) { enum machine_mode mode = GET_MODE ( operands [ 0 ] ) ; gcc_assert ( mode == SImode ) ; if ( TARGET_H8300 ) { return CC_CLOBBER ; } else { if ( GET_CODE ( operands [ 2 ] ) == CONST_INT && register_operand ( operands [ 1 ] , VOIDmode ) ) { HOST_WIDE_INT intval = INTVAL ( operands [ 2 ] ) ; if ( TARGET_H8300SX && ( intval >= 1 && intval <= 7 ) ) return CC_SET_ZN ; if ( TARGET_H8300SX && ( intval >= - 7 && intval <= - 1 ) ) return CC_SET_ZN ; switch ( ( unsigned int ) intval & 0xffffffff ) { case 0x00000001 : case 0x00000002 : case 0x00000004 : return CC_NONE_0HIT ; case 0xffffffff : case 0xfffffffe : case 0xfffffffc : return CC_NONE_0HIT ; case 0x00010000 : case 0x00020000 : return CC_CLOBBER ; case 0xffff0000 : case 0xfffe0000 : return CC_CLOBBER ; } if ( ( intval & 0xffff ) == 0 ) return CC_CLOBBER ; } return CC_SET_ZN ; } } </s>

Compute which flag bits are valid after an addition insn .


<s> static bool insn_references_regno_p ( rtx_insn * insn , unsigned int regno , enum attr_type type ) { struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref ref ; for ( ref = DF_INSN_INFO_DEFS ( insn_info ) ; ref ; ref = DF_REF_NEXT_LOC ( ref ) ) if ( DF_REF_REGNO ( ref ) == regno ) return true ; if ( type == TYPE_LOAD || type == TYPE_FPLOAD || type == TYPE_VECLOAD ) for ( ref = DF_INSN_INFO_USES ( insn_info ) ; ref ; ref = DF_REF_NEXT_LOC ( ref ) ) if ( DF_REF_REGNO ( ref ) == regno ) return true ; return false ; } </s>

Check whether INSN contains a reference to REGNO that will inhibit the PCREL_OPT optimization . If TYPE is a load or store instruction , return true if there is a definition of REGNO . If TYPE is a load instruction , then return true of there is a use of REGNO .


<s> int SystemZHazardRecognizer :: groupingCost ( SUnit * SU ) const { const MCSchedClassDesc * SC = getSchedClass ( SU ) ; if ( ! SC -> isValid ( ) ) return 0 ; if ( SC -> BeginGroup ) { if ( CurrGroupSize ) return 3 - CurrGroupSize ; return - 1 ; } if ( SC -> EndGroup ) { unsigned resultingGroupSize = ( CurrGroupSize + getNumDecoderSlots ( SU ) ) ; if ( resultingGroupSize < 3 ) return ( 3 - resultingGroupSize ) ; return - 1 ; } return 0 ; } </s>

Return the cost of decoder grouping for SU .


<s> static void mips_multi_add_insn ( const char * format , ... ) { struct mips_multi_member * member ; va_list ap ; unsigned int i ; rtx op ; member = mips_multi_add ( ) ; member -> is_label_p = false ; member -> format = format ; va_start ( ap , format ) ; i = 0 ; while ( ( op = va_arg ( ap , rtx ) ) ) member -> operands [ i ++ ] = op ; va_end ( ap ) ; mips_multi_num_insns ++ ; } </s>

Add a normal insn with the given asm format to the current multi-insn sequence . The other arguments are a null-terminated list of operands .


<s>
StringRef
XtensaAsmPrinter
::
getPassName
(
)
const
{
return
"Xtensa Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> unsigned RISCVAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { RISCVOperand & Op = static_cast < RISCVOperand & > ( AsmOp ) ; if ( ! Op . isReg ( ) ) return Match_InvalidOperand ; MCRegister Reg = Op . getReg ( ) ; bool IsRegFPR64 = RISCVMCRegisterClasses [ RISCV :: FPR64RegClassID ] . contains ( Reg ) ; bool IsRegFPR64C = RISCVMCRegisterClasses [ RISCV :: FPR64CRegClassID ] . contains ( Reg ) ; bool IsRegVR = RISCVMCRegisterClasses [ RISCV :: VRRegClassID ] . contains ( Reg ) ; if ( ( IsRegFPR64 && Kind == MCK_FPR32 ) || ( IsRegFPR64C && Kind == MCK_FPR32C ) ) { Op . Reg . RegNum = convertFPR64ToFPR32 ( Reg ) ; return Match_Success ; } if ( IsRegFPR64 && Kind == MCK_FPR16 ) { Op . Reg . RegNum = convertFPR64ToFPR16 ( Reg ) ; return Match_Success ; } if ( IsRegVR && ( Kind == MCK_VRM2 || Kind == MCK_VRM4 || Kind == MCK_VRM8 ) ) { Op . Reg . RegNum = convertVRToVRMx ( * getContext ( ) . getRegisterInfo ( ) , Reg , Kind ) ; if ( Op . Reg . RegNum == 0 ) return Match_InvalidOperand ; return Match_Success ; } return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .

RISCV RISCV RISCV RISCV RISCV RISCV::FPR64RegClassID RISCV RISCV::FPR64CRegClassID RISCV RISCV::VRRegClassID 0


<s>
bool
DeadCodeElimination
::
erase
(
const
SetVector
<
NodeId
>
&
Nodes
)
{
if
(
Nodes
.
empty
(
)
)
return
false
;
NodeList
DRNs
,
DINs
;
for
(
auto
I
:
Nodes
)
{
auto
BA
=
DFG
.
addr
<
NodeBase
*
>
(
I
)
;
uint16_t
Type
=
BA
.
Addr
->
getType
(
)
;
if
(
Type
==
NodeAttrs
::
Ref
)
{
DRNs
.
push_back
(
DFG
.
addr
<
RefNode
*
>
(
I
)
)
;
continue
;
}
uint16_t
Kind
=
BA
.
Addr
->
getKind
(
)
;
if
(
Kind
==
NodeAttrs
::
Stmt
||
Kind
==
NodeAttrs
::
Phi
)
{
for
(
auto
N
:
NodeAddr
<
CodeNode
*
>
(
BA
)
.
Addr
->
members
(
DFG
)
)
DRNs
.
push_back
(
N
)
;
DINs
.
push_back
(
DFG
.
addr
<
InstrNode
*
>
(
I
)
)
;
}
else
{
llvm_unreachable
(
"Unexpected code node"
)
;
return
false
;
}
}
auto
UsesFirst
=
[
]
(
NodeAddr
<
RefNode
*
>
A
,
NodeAddr
<
RefNode
*
>
B
)
->
bool
{
uint16_t
KindA
=
A
.
Addr
->
getKind
(
)
,
KindB
=
B
.
Addr
->
getKind
(
)
;
if
(
KindA
==
NodeAttrs
::
Use
&&
KindB
==
NodeAttrs
::
Def
)
return
true
;
if
(
KindA
==
NodeAttrs
::
Def
&&
KindB
==
NodeAttrs
::
Use
)
return
false
;
return
A
.
Id
<
B
.
Id
;
}
;
llvm
::
sort
(
DRNs
,
UsesFirst
)
;
if
(
trace
(
)
)
dbgs
(
)
<<
"Removing dead ref nodes:\n"
;
for
(
NodeAddr
<
RefNode
*
>
RA
:
DRNs
)
{
if
(
trace
(
)
)
dbgs
(
)
<<
"  "
<<
PrintNode
<
RefNode
*
>
(
RA
,
DFG
)
<<
'\n'
;
if
(
DFG
.
IsUse
(
RA
)
)
DFG
.
unlinkUse
(
RA
,
true
)
;
else
if
(
DFG
.
IsDef
(
RA
)
)
DFG
.
unlinkDef
(
RA
,
true
)
;
}
for
(
NodeAddr
<
InstrNode
*
>
IA
:
DINs
)
{
NodeAddr
<
BlockNode
*
>
BA
=
IA
.
Addr
->
getOwner
(
DFG
)
;
BA
.
Addr
->
removeMember
(
IA
,
DFG
)
;
if
(
!
DFG
.
IsCode
<
NodeAttrs
::
Stmt
>
(
IA
)
)
continue
;
MachineInstr
*
MI
=
NodeAddr
<
StmtNode
*
>
(
IA
)
.
Addr
->
getCode
(
)
;
if
(
trace
(
)
)
dbgs
(
)
<<
"erasing: "
<<
*
MI
;
MI
->
eraseFromParent
(
)
;
}
return
true
;
}
</s>

erase - Erases an element identified by Key , if it exists .

Hexagon
"Unexpected code node"
"Removing dead ref nodes:\n"
"  "
"erasing: "


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
VE
::
NumTargetFixupKinds
]
=
{
{
"fixup_ve_reflong"
,
0
,
32
,
0
}
,
{
"fixup_ve_hi32"
,
0
,
32
,
0
}
,
{
"fixup_ve_lo32"
,
0
,
32
,
0
}
,
{
"fixup_ve_pc_hi32"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ve_pc_lo32"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ve_got_hi32"
,
0
,
32
,
0
}
,
{
"fixup_ve_got_lo32"
,
0
,
32
,
0
}
,
{
"fixup_ve_gotoff_hi32"
,
0
,
32
,
0
}
,
{
"fixup_ve_gotoff_lo32"
,
0
,
32
,
0
}
,
{
"fixup_ve_plt_hi32"
,
0
,
32
,
0
}
,
{
"fixup_ve_plt_lo32"
,
0
,
32
,
0
}
,
{
"fixup_ve_tls_gd_hi32"
,
0
,
32
,
0
}
,
{
"fixup_ve_tls_gd_lo32"
,
0
,
32
,
0
}
,
{
"fixup_ve_tpoff_hi32"
,
0
,
32
,
0
}
,
{
"fixup_ve_tpoff_lo32"
,
0
,
32
,
0
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> bool ARM64TargetLowering :: isZExtFree ( SDValue Val , EVT VT2 ) const { EVT VT1 = Val . getValueType ( ) ; if ( isZExtFree ( VT1 , VT2 ) ) { return true ; } if ( Val . getOpcode ( ) != ISD :: LOAD ) return false ; return ( VT1 . isSimple ( ) && VT1 . isInteger ( ) && VT2 . isSimple ( ) && VT2 . isInteger ( ) && VT1 . getSizeInBits ( ) <= 32 ) ; } </s>

Return true if zero-extending the specific node Val to type VT2 is free ( either because it 's implicitly zero-extended such as ARM ldrb / ldrh or because it 's folded such as X86 zero-extending loads ) .


<s> void SIAnnotateControlFlow :: push ( BasicBlock * BB , Value * Saved ) { Stack . push_back ( std :: make_pair ( BB , Saved ) ) ; } </s>


<s> MachineBasicBlock :: iterator XCoreInstrInfo :: loadImmediate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned Reg , uint64_t Value ) const { DebugLoc dl ; if ( MI != MBB . end ( ) ) dl = MI -> getDebugLoc ( ) ; if ( isImmMskBitp ( Value ) ) { int N = Log2_32 ( Value ) + 1 ; return BuildMI ( MBB , MI , dl , get ( XCore :: MKMSK_rus ) , Reg ) . addImm ( N ) ; } if ( isImmU16 ( Value ) ) { int Opcode = isImmU6 ( Value ) ? XCore :: LDC_ru6 : XCore :: LDC_lru6 ; return BuildMI ( MBB , MI , dl , get ( Opcode ) , Reg ) . addImm ( Value ) ; } MachineConstantPool * ConstantPool = MBB . getParent ( ) -> getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Value ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; return BuildMI ( MBB , MI , dl , get ( XCore :: LDWCP_lru6 ) , Reg ) . addConstantPoolIndex ( Idx ) ; } </s>

Emit a series of instructions to load an immediate .


<s> Align ARMTargetLowering :: getABIAlignmentForCallingConv ( Type * ArgTy , DataLayout DL ) const { const Align ABITypeAlign ( DL . getABITypeAlignment ( ArgTy ) ) ; if ( ! ArgTy -> isVectorTy ( ) ) return ABITypeAlign ; return std :: min ( ABITypeAlign , DL . getStackAlignment ( ) ) ; } </s>

Return the correct alignment for the current calling convention .


<s> static void do_dispatch ( rtx_insn * insn , int mode ) { if ( mode == DISPATCH_INIT ) init_dispatch_sched ( ) ; else if ( mode == ADD_TO_DISPATCH_WINDOW ) add_to_dispatch_window ( insn ) ; } </s>

This routine is the driver of the dispatch scheduler .


<s> SDValue HexagonTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & dl , SelectionDAG & DAG ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; if ( Subtarget . useHVXOps ( ) ) CCInfo . AnalyzeReturn ( Outs , RetCC_Hexagon_HVX ) ; else CCInfo . AnalyzeReturn ( Outs , RetCC_Hexagon ) ; SDValue Flag ; SmallVector < SDValue , 4 > RetOps ( 1 , Chain ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( 1 ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } RetOps [ 0 ] = Chain ; if ( Flag . getNode ( ) ) RetOps . push_back ( Flag ) ; return DAG . getNode ( HexagonISD :: RET_FLAG , dl , MVT :: Other , RetOps ) ; } </s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .