<s>
const
MCFixupKindInfo
&
XtensaAsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
Xtensa
::
NumTargetFixupKinds
]
=
{
{
"fixup_xtensa_ldst_imm4_scale2"
,
12
,
4
,
0
}
,
{
"fixup_xtensa_jump_target"
,
6
,
18
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_xtensa_cond_branch12_target"
,
12
,
12
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> virtual const Tile64RegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
void
AlphaInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
DebugLoc
::
getUnknownLoc
(
)
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
if
(
RC
==
Alpha
::
F4RCRegisterClass
)
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Alpha
::
STS
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIdx
)
.
addReg
(
Alpha
::
F31
)
;
else
if
(
RC
==
Alpha
::
F8RCRegisterClass
)
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Alpha
::
STT
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIdx
)
.
addReg
(
Alpha
::
F31
)
;
else
if
(
RC
==
Alpha
::
GPRCRegisterClass
)
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Alpha
::
STQ
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIdx
)
.
addReg
(
Alpha
::
F31
)
;
else
llvm_unreachable
(
"Unhandled register class"
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> static bool str_prefix_p ( const char * str , const char * prefix ) { return strncmp ( str , prefix , strlen ( prefix ) ) == 0 ; } </s>

Return true iff STR starts with PREFIX .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"NVPTX specific alloca hoisting"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static bool nios2_legitimate_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { rtx base , offset ; split_const ( x , & base , & offset ) ; return GET_CODE ( base ) != SYMBOL_REF || ! SYMBOL_REF_TLS_MODEL ( base ) ; } </s>


<s>
bool
MSP430BSel
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
MF
=
&
mf
;
TII
=
static_cast
<
const
MSP430InstrInfo
*
>
(
MF
->
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
if
(
!
BranchSelectEnabled
)
return
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"\n********** "
<<
getPassName
(
)
<<
" **********\n"
)
;
OffsetVector
BlockOffsets
;
unsigned
FunctionSize
=
measureFunction
(
BlockOffsets
)
;
if
(
isInRage
(
FunctionSize
)
)
{
return
false
;
}
bool
MadeChange
=
false
;
while
(
expandBranches
(
BlockOffsets
)
)
MadeChange
=
true
;
return
MadeChange
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> void s390_reload_larl_operand ( rtx reg , rtx addr , rtx scratch ) { HOST_WIDE_INT addend ; rtx symref ; if ( ! s390_loadrelative_operand_p ( addr , & symref , & addend ) ) gcc_unreachable ( ) ; if ( ! ( addend & 1 ) ) emit_move_insn ( reg , addr ) ; else { if ( REGNO ( reg ) < FIRST_PSEUDO_REGISTER && REGNO_REG_CLASS ( REGNO ( reg ) ) == ADDR_REGS ) scratch = reg ; gcc_assert ( REGNO ( scratch ) < FIRST_PSEUDO_REGISTER ) ; gcc_assert ( REGNO_REG_CLASS ( REGNO ( scratch ) ) == ADDR_REGS ) ; if ( addend != 1 ) emit_move_insn ( scratch , gen_rtx_CONST ( Pmode , gen_rtx_PLUS ( Pmode , symref , GEN_INT ( addend - 1 ) ) ) ) ; else emit_move_insn ( scratch , symref ) ; s390_load_address ( reg , gen_rtx_PLUS ( Pmode , scratch , const1_rtx ) ) ; } } </s>

ADDR is moved into REG using larl . If ADDR is n't a valid larl operand SCRATCH is used to reload the even part of the address and adding one .


<s>
std
::
vector
<
const
SUnit
*
>
GCNILPScheduler
::
schedule
(
ArrayRef
<
const
SUnit
*
>
BotRoots
,
const
ScheduleDAG
&
DAG
)
{
auto
&
SUnits
=
const_cast
<
ScheduleDAG
&
>
(
DAG
)
.
SUnits
;
std
::
vector
<
SUnit
>
SUSavedCopy
;
SUSavedCopy
.
resize
(
SUnits
.
size
(
)
)
;
for
(
const
SUnit
&
SU
:
SUnits
)
SUSavedCopy
[
SU
.
NodeNum
]
=
SU
;
SUNumbers
.
assign
(
SUnits
.
size
(
)
,
0
)
;
for
(
const
SUnit
&
SU
:
SUnits
)
CalcNodeSethiUllmanNumber
(
&
SU
,
SUNumbers
)
;
for
(
auto
SU
:
BotRoots
)
{
AvailQueue
.
push_back
(
*
new
(
Alloc
.
Allocate
(
)
)
Candidate
(
const_cast
<
SUnit
*
>
(
SU
)
)
)
;
}
releasePredecessors
(
&
DAG
.
ExitSU
)
;
std
::
vector
<
const
SUnit
*
>
Schedule
;
Schedule
.
reserve
(
SUnits
.
size
(
)
)
;
while
(
true
)
{
if
(
AvailQueue
.
empty
(
)
&&
!
PendingQueue
.
empty
(
)
)
{
auto
EarliestSU
=
std
::
min_element
(
PendingQueue
.
begin
(
)
,
PendingQueue
.
end
(
)
,
[
=
]
(
const
Candidate
&
C1
,
const
Candidate
&
C2
)
{
return
C1
.
SU
->
getHeight
(
)
<
C2
.
SU
->
getHeight
(
)
;
}
)
->
SU
;
advanceToCycle
(
std
::
max
(
CurCycle
+
1
,
EarliestSU
->
getHeight
(
)
)
)
;
}
if
(
AvailQueue
.
empty
(
)
)
break
;
LLVM_DEBUG
(
dbgs
(
)
<<
"\n=== Picking candidate\n"
"Ready queue:"
;
for
(
auto
&
C
:
AvailQueue
)
dbgs
(
)
<<
' '
<<
C
.
SU
->
NodeNum
;
dbgs
(
)
<<
'\n'
;
)
;
auto
C
=
pickCandidate
(
)
;
assert
(
C
)
;
AvailQueue
.
remove
(
*
C
)
;
auto
SU
=
C
->
SU
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Selected "
;
SU
->
dump
(
&
DAG
)
)
;
advanceToCycle
(
SU
->
getHeight
(
)
)
;
releasePredecessors
(
SU
)
;
Schedule
.
push_back
(
SU
)
;
SU
->
isScheduled
=
true
;
}
assert
(
SUnits
.
size
(
)
==
Schedule
.
size
(
)
)
;
std
::
reverse
(
Schedule
.
begin
(
)
,
Schedule
.
end
(
)
)
;
for
(
auto
&
SU
:
SUnits
)
SU
=
SUSavedCopy
[
SU
.
NodeNum
]
;
return
Schedule
;
}
</s>

Schedule - This is called back from ScheduleDAGInstrs : :Run ( ) when it 's time to do some work .

AMDGPU
0
1
"\n=== Picking candidate\n"
"Ready queue:"
"Selected "


<s> bool RISCVSubtarget :: enableSubRegLiveness ( ) const { return EnableSubRegLiveness ; } </s>

Enable tracking of subregister liveness in register allocator .


<s>
SDValue
VETargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
BlockAddress
:
return
lowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
lowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
lowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
lowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
lowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
LOAD
:
return
lowerLOAD
(
Op
,
DAG
)
;
case
ISD
::
STORE
:
return
lowerSTORE
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
lowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
VAARG
:
return
lowerVAARG
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

VE
VE
"Should not custom lower this!"
ISD::BlockAddress
ISD::ConstantPool
ISD::DYNAMIC_STACKALLOC
ISD::GlobalAddress
ISD::GlobalTLSAddress
ISD::LOAD
ISD::STORE
ISD::VASTART
ISD::VAARG


<s> int AMDGPUInstrInfo :: pseudoToMCOpcode ( int Opcode ) const { int MCOp = AMDGPU :: getMCOpcode ( Opcode , AMDGPUSubtargetToSISubtarget ( ST . getGeneration ( ) ) ) ; if ( MCOp == - 1 ) return Opcode ; if ( MCOp == ( uint16_t ) - 1 ) return - 1 ; return MCOp ; } </s>

Return a target-specific opcode if Opcode is a pseudo instruction .


<s> static int loongarch_immediate_operand_p ( int code , HOST_WIDE_INT x ) { switch ( code ) { case ASHIFT : case ASHIFTRT : case LSHIFTRT : return true ; case ROTATE : case ROTATERT : return true ; case AND : case IOR : case XOR : return IMM12_OPERAND_UNSIGNED ( x ) ; case PLUS : case LT : case LTU : return IMM12_OPERAND ( x ) ; case EQ : case NE : case GT : case GTU : return x == 0 ; case GE : case GEU : return x == 1 ; case LE : return IMM12_OPERAND ( x + 1 ) ; case LEU : return IMM12_OPERAND ( x + 1 ) && x + 1 != 0 ; case SIGN_EXTRACT : case ZERO_EXTRACT : return 1 ; default : return x == 0 ; } } </s>

Return true if there is a instruction that implements CODE and if that instruction accepts X as an immediate operand .


"internal error: instruction without _e64 suffix "

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> MCSection * getExplicitSectionGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler & Mang , const TargetMachine & TM ) const override { return DataSection ; } </s>

Targets should implement this method to assign a section to globals with an explicit section specfied .


<s> BitVector FISCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( FISC :: SP ) ; Reserved . set ( FISC :: LR ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
static
void
nds32_asm_function_epilogue
(
FILE
*
file
)
{
fprintf
(
file
,
"\t! END EPILOGUE\n"
)
;
}
</s>

The content produced from this function will be placed after epilogue body .


"Load should return a value and a chain"


<s> const MCS51RegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>


<s> unsigned int compute_logical_op_length ( machine_mode mode , rtx * operands ) { enum rtx_code code = GET_CODE ( operands [ 3 ] ) ; const unsigned HOST_WIDE_INT intval = ( unsigned HOST_WIDE_INT ) ( ( GET_CODE ( operands [ 2 ] ) == CONST_INT ) && register_operand ( operands [ 1 ] , VOIDmode ) ? INTVAL ( operands [ 2 ] ) : 0x55555555 ) ; const unsigned HOST_WIDE_INT det = ( code != AND ) ? intval : ~ intval ; const unsigned HOST_WIDE_INT b0 = ( det >> 0 ) & 0xff ; const unsigned HOST_WIDE_INT b1 = ( det >> 8 ) & 0xff ; const unsigned HOST_WIDE_INT w0 = ( det >> 0 ) & 0xffff ; const unsigned HOST_WIDE_INT w1 = ( det >> 16 ) & 0xffff ; int lower_half_easy_p = 0 ; int upper_half_easy_p = 0 ; unsigned int length = 0 ; switch ( mode ) { case E_HImode : if ( b0 != 0 && b1 != 0 ) { length = h8300_length_from_table ( operands [ 1 ] , operands [ 2 ] , & logicw_length_table ) ; } else { if ( b0 != 0 ) length += 2 ; if ( b1 != 0 ) length += 2 ; } break ; case E_SImode : lower_half_easy_p = ( b0 == 0 || b1 == 0 || ( code != IOR && w0 == 0xffff ) ) ; upper_half_easy_p = ( ( code != IOR && w1 == 0xffff ) || ( code == AND && w1 == 0xff00 ) ) ; if ( w0 != 0 && w1 != 0 && ! ( lower_half_easy_p && upper_half_easy_p ) && ! ( code == IOR && w1 == 0xffff && ( w0 & 0x8000 ) != 0 && lower_half_easy_p ) ) { length = h8300_length_from_table ( operands [ 1 ] , operands [ 2 ] , & logicl_length_table ) ; } else { if ( w0 == 0xffff && ( code != IOR ) ) { length += 2 ; } else if ( ( b0 != 0 ) && ( b1 != 0 ) ) { length += 4 ; } else { if ( b0 != 0 ) length += 2 ; if ( b1 != 0 ) length += 2 ; } if ( w1 == 0xffff && ( code != IOR ) ) { length += 2 ; } else if ( code == IOR && w1 == 0xffff && ( w0 & 0x8000 ) != 0 ) { length += 2 ; } else if ( code == AND && w1 == 0xff00 ) { length += 2 ; } else { if ( w1 != 0 ) length += 4 ; } } break ; default : gcc_unreachable ( ) ; } return length ; } </s>


<s> static rtx sparc_function_value_1 ( const_tree type , machine_mode mode , bool outgoing ) { int regbase = ( outgoing ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST ) ; enum mode_class mclass = GET_MODE_CLASS ( mode ) ; int regno ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( ( TARGET_ARCH32 && size <= 8 ) || ( TARGET_ARCH64 && size <= 32 ) ) ; if ( mode == BLKmode ) return function_arg_vector_value ( size , SPARC_FP_ARG_FIRST ) ; mclass = MODE_FLOAT ; } if ( TARGET_ARCH64 && type ) { if ( TREE_CODE ( type ) == RECORD_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 32 ) ; return function_arg_record_value ( type , mode , 0 , 1 , regbase ) ; } else if ( TREE_CODE ( type ) == UNION_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 32 ) ; return function_arg_union_value ( size , mode , 0 , regbase ) ; } else if ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) ; else if ( AGGREGATE_TYPE_P ( type ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 32 ) ; mode = mode_for_size ( size * BITS_PER_UNIT , MODE_INT , 0 ) ; if ( mode == BLKmode ) return function_arg_union_value ( size , mode , 0 , regbase ) ; else mclass = MODE_INT ; } else if ( mclass == MODE_INT && GET_MODE_SIZE ( mode ) < UNITS_PER_WORD ) mode = word_mode ; } else if ( TARGET_ARCH32 && mclass == MODE_INT && GET_MODE_SIZE ( mode ) < UNITS_PER_WORD ) mode = word_mode ; if ( ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) && TARGET_FPU ) regno = SPARC_FP_ARG_FIRST ; else regno = regbase ; return gen_rtx_REG ( mode , regno ) ; } </s>

Handle TARGET_FUNCTION_VALUE , and TARGET_LIBCALL_VALUE target hook . For v9 , function return values are subject to the same rules as arguments , except that up to 32 bytes may be returned in registers .


<s> const uint16_t * X86RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { bool callsEHReturn = false ; bool ghcCall = false ; bool oclBiCall = false ; bool hipeCall = false ; bool HasAVX = TM . getSubtarget < X86Subtarget > ( ) . hasAVX ( ) ; if ( MF ) { callsEHReturn = MF -> getMMI ( ) . callsEHReturn ( ) ; const Function * F = MF -> getFunction ( ) ; ghcCall = ( F ? F -> getCallingConv ( ) == CallingConv :: GHC : false ) ; oclBiCall = ( F ? F -> getCallingConv ( ) == CallingConv :: Intel_OCL_BI : false ) ; hipeCall = ( F ? F -> getCallingConv ( ) == CallingConv :: HiPE : false ) ; } if ( ghcCall || hipeCall ) return CSR_NoRegs_SaveList ; if ( oclBiCall ) { if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; } if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_SaveList ; if ( callsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; } if ( callsEHReturn ) return CSR_32EHRet_SaveList ; return CSR_32_SaveList ; } </s>


<s> iterator end ( ) const { return Masks . end ( ) ; } </s>

Get a const_iterator to the end of the symbol table .


<s> rtx h8300_return_addr_rtx ( int count , rtx frame ) { rtx ret ; if ( count == 0 ) ret = gen_rtx_MEM ( Pmode , gen_rtx_REG ( Pmode , RETURN_ADDRESS_POINTER_REGNUM ) ) ; else if ( flag_omit_frame_pointer ) return ( rtx ) 0 ; else ret = gen_rtx_MEM ( Pmode , memory_address ( Pmode , plus_constant ( frame , UNITS_PER_WORD ) ) ) ; set_mem_alias_set ( ret , get_frame_alias_set ( ) ) ; return ret ; } </s>


<s> static bool mips_expand_vpc_loongson_even_odd ( struct expand_vec_perm_d * d ) { unsigned i , odd , nelt = d -> nelt ; rtx t0 , t1 , t2 , t3 ; if ( ! ( TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS ) ) return false ; if ( nelt < 4 ) return false ; odd = d -> perm [ 0 ] ; if ( odd > 1 ) return false ; for ( i = 1 ; i < nelt ; ++ i ) if ( d -> perm [ i ] != i * 2 + odd ) return false ; if ( d -> testing_p ) return true ; t0 = gen_reg_rtx ( d -> vmode ) ; t1 = gen_reg_rtx ( d -> vmode ) ; switch ( d -> vmode ) { case V4HImode : emit_insn ( gen_loongson_punpckhhw ( t0 , d -> op0 , d -> op1 ) ) ; emit_insn ( gen_loongson_punpcklhw ( t1 , d -> op0 , d -> op1 ) ) ; if ( odd ) emit_insn ( gen_loongson_punpckhhw ( d -> target , t1 , t0 ) ) ; else emit_insn ( gen_loongson_punpcklhw ( d -> target , t1 , t0 ) ) ; break ; case V8QImode : t2 = gen_reg_rtx ( d -> vmode ) ; t3 = gen_reg_rtx ( d -> vmode ) ; emit_insn ( gen_loongson_punpckhbh ( t0 , d -> op0 , d -> op1 ) ) ; emit_insn ( gen_loongson_punpcklbh ( t1 , d -> op0 , d -> op1 ) ) ; emit_insn ( gen_loongson_punpckhbh ( t2 , t1 , t0 ) ) ; emit_insn ( gen_loongson_punpcklbh ( t3 , t1 , t0 ) ) ; if ( odd ) emit_insn ( gen_loongson_punpckhbh ( d -> target , t3 , t2 ) ) ; else emit_insn ( gen_loongson_punpcklbh ( d -> target , t3 , t2 ) ) ; break ; default : gcc_unreachable ( ) ; } return true ; } </s>

Recognize patterns for even-odd extraction .


<s> static void aarch64_print_operand_address ( FILE * f , machine_mode mode , rtx x ) { if ( ! aarch64_print_address_internal ( f , mode , x , ADDR_QUERY_ANY ) ) output_addr_const ( f , x ) ; } </s>

Print address ' x ' of a memory access with mode 'mode ' .


<s> WebAssemblyTargetMachine :: WebAssemblyTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT . isArch64Bit ( ) ? "e-m:e-p:64:64-i64:64-n32:64-S128" : "e-m:e-p:32:32-i64:64-n32:64-S128" , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < WebAssemblyTargetObjectFile > ( ) ) { this -> Options . TrapUnreachable = true ; initAsmInfo ( ) ; } </s>

Create an WebAssembly architecture model .

WebAssembly WebAssembly WebAssembly "e-m:e-p:64:64-i64:64-n32:64-S128" "e-m:e-p:32:32-i64:64-n32:64-S128" WebAssembly


<s> unsigned getFlatAddressSpace ( ) const { if ( IsGraphicsShader ) return - 1 ; return ST -> hasFlatAddressSpace ( ) ? AMDGPUAS :: FLAT_ADDRESS : AMDGPUAS :: UNKNOWN_ADDRESS_SPACE ; } </s>

Returns the address space ID for a target 's 'flat ' address space .


<s> unsigned getStackAlignment ( ) const { return 4 ; } </s>

Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget .


<s>
static
void
riscv_file_start
(
void
)
{
default_file_start
(
)
;
fprintf
(
asm_out_file
,
"\t.option %spic\n"
,
(
flag_pic
""
:
"no"
)
)
;
}
</s>


<s> int easy_df_const ( rtx op ) { REAL_VALUE_TYPE r ; long l [ 2 ] ; REAL_VALUE_FROM_CONST_DOUBLE ( r , op ) ; REAL_VALUE_TO_TARGET_DOUBLE ( r , l ) ; if ( l [ 0 ] == 0 && l [ 1 ] == 0 ) return 1 ; if ( ( l [ 0 ] & 0xffff ) == 0 && l [ 1 ] == 0 ) return 1 ; return 0 ; } </s>

Return 1 if OP is a DFmode const we want to handle inline . This must match the code in the movdf pattern . It is used by the ' H ' CONST_DOUBLE_OK_FOR_LETTER .


<s> TargetLoweringBase :: LegalizeTypeAction SITargetLowering :: getPreferredVectorAction ( MVT VT ) const { if ( VT . getVectorNumElements ( ) != 1 && VT . getScalarType ( ) . bitsLE ( MVT :: i16 ) ) return TypeSplitVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> static bool ix86_vector_duplicate_value ( machine_mode mode , rtx target , rtx val ) { bool ok ; rtx_insn * insn ; rtx dup ; recog_data_d recog_data_save = recog_data ; dup = gen_vec_duplicate ( mode , val ) ; insn = emit_insn ( gen_rtx_SET ( target , dup ) ) ; if ( recog_memoized ( insn ) < 0 ) { rtx_insn * seq ; machine_mode innermode = GET_MODE_INNER ( mode ) ; rtx reg ; start_sequence ( ) ; reg = force_reg ( innermode , val ) ; if ( GET_MODE ( reg ) != innermode ) reg = gen_lowpart ( innermode , reg ) ; SET_SRC ( PATTERN ( insn ) ) = gen_vec_duplicate ( mode , reg ) ; seq = get_insns ( ) ; end_sequence ( ) ; if ( seq ) emit_insn_before ( seq , insn ) ; ok = recog_memoized ( insn ) >= 0 ; gcc_assert ( ok ) ; } recog_data = recog_data_save ; return true ; } </s>

A subroutine of ix86_expand_vector_init_duplicate . Tries to fill target with val via vec_duplicate .


<s>
enum
cris_pic_symbol_type
cris_pic_symbol_type_of
(
rtx
x
)
{
switch
(
GET_CODE
(
x
)
)
{
case
SYMBOL_REF
:
return
SYMBOL_REF_LOCAL_P
(
x
)
cris_gotrel_symbol
:
cris_got_symbol
;
case
LABEL_REF
:
return
cris_gotrel_symbol
;
case
CONST
:
return
cris_pic_symbol_type_of
(
XEXP
(
x
,
0
)
)
;
case
PLUS
:
case
MINUS
:
{
enum
cris_pic_symbol_type
t1
=
cris_pic_symbol_type_of
(
XEXP
(
x
,
0
)
)
;
enum
cris_pic_symbol_type
t2
=
cris_pic_symbol_type_of
(
XEXP
(
x
,
1
)
)
;
gcc_assert
(
t1
==
cris_no_symbol
||
t2
==
cris_no_symbol
)
;
if
(
t1
==
cris_got_symbol
||
t1
==
cris_got_symbol
)
return
cris_got_symbol_needing_fixup
;
return
t1
!=
cris_no_symbol
t1
:
t2
;
}
case
CONST_INT
:
case
CONST_DOUBLE
:
return
cris_no_symbol
;
case
UNSPEC
:
return
cris_invalid_pic_symbol
;
default
:
fatal_insn
(
"unrecognized supposed constant"
,
x
)
;
}
gcc_unreachable
(
)
;
}
</s>

Helper function to find the right PIC-type symbol to generate , given the original ( non-PIC ) representation .


<s> static type_suffix_index long_type_suffix ( function_resolver & r , type_suffix_index type ) { unsigned int element_bits = type_suffixes [ type ] . element_bits ; if ( type_suffixes [ type ] . integer_p && element_bits < 64 ) return find_type_suffix ( type_suffixes [ type ] . tclass , element_bits * 2 ) ; r . report_no_such_form ( type ) ; return NUM_TYPE_SUFFIXES ; } </s>

TYPE is the largest type suffix associated with the arguments of R , but the result is twice as wide . Return the associated type suffix if it exists , otherwise report an appropriate error and return NUM_TYPE_SUFFIXES .


<s> static tree gcn_goacc_get_worker_red_decl ( tree type , unsigned offset ) { machine_function * machfun = cfun -> machine ; if ( TREE_CODE ( type ) == REFERENCE_TYPE ) type = TREE_TYPE ( type ) ; tree var_type = build_qualified_type ( type , ( TYPE_QUALS ( type ) | ENCODE_QUAL_ADDR_SPACE ( ADDR_SPACE_LDS ) ) ) ; gcc_assert ( offset < ( machfun -> reduction_limit - machfun -> reduction_base ) ) ; tree ptr_type = build_pointer_type ( var_type ) ; tree addr = build_int_cst ( ptr_type , machfun -> reduction_base + offset ) ; return build_simple_mem_ref ( addr ) ; } </s>

Return a temporary variable decl to use for an OpenACC worker reduction .


doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> std :: pair < unsigned , const TargetRegisterClass * > MSP430TargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'r' : if ( VT == MVT :: i8 ) return std :: make_pair ( 0U , & MSP430 :: GR8RegClass ) ; return std :: make_pair ( 0U , & MSP430 :: GR16RegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> static void nvptx_reorg ( void ) { compute_bb_for_insn ( ) ; thread_prologue_and_epilogue_insns ( ) ; bb_insn_map_t bb_insn_map ; nvptx_split_blocks ( & bb_insn_map ) ; df_clear_flags ( DF_LR_RUN_DCE ) ; df_set_flags ( DF_NO_INSN_RESCAN | DF_NO_HARD_REGS ) ; df_live_add_problem ( ) ; df_live_set_all_dirty ( ) ; df_analyze ( ) ; regstat_init_n_sets_and_refs ( ) ; if ( dump_file ) df_dump ( dump_file ) ; int max_regs = max_reg_num ( ) ; for ( int i = LAST_VIRTUAL_REGISTER + 1 ; i < max_regs ; i ++ ) if ( REG_N_SETS ( i ) == 0 && REG_N_REFS ( i ) == 0 ) regno_reg_rtx [ i ] = const0_rtx ; tree attr = oacc_get_fn_attrib ( current_function_decl ) ; if ( attr ) { unsigned mask = 0 ; tree dims = TREE_VALUE ( attr ) ; unsigned ix ; for ( ix = 0 ; ix != GOMP_DIM_MAX ; ix ++ , dims = TREE_CHAIN ( dims ) ) { int size = TREE_INT_CST_LOW ( TREE_VALUE ( dims ) ) ; tree allowed = TREE_PURPOSE ( dims ) ; if ( size != 1 && ! ( allowed && integer_zerop ( allowed ) ) ) mask |= GOMP_DIM_MASK ( ix ) ; } gcc_assert ( ! ( mask & GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ) || ( mask & GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) ) ) ; parallel * pars = nvptx_discover_pars ( & bb_insn_map ) ; nvptx_process_pars ( pars ) ; nvptx_neuter_pars ( pars , mask , 0 ) ; delete pars ; } nvptx_reorg_subreg ( ) ; if ( TARGET_UNIFORM_SIMT ) nvptx_reorg_uniform_simt ( ) ; regstat_free_n_sets_and_refs ( ) ; df_finish_pass ( true ) ; } </s>

Clean up subreg operands . In ptx assembly , everything is typed , and the presence of subregs would break the rules for most instructions . Replace them with a suitable new register of the right size , plus conversion copyin/copyout instructions .


Return an array that contains the direct target flag values and their names .

PowerPC PPC PPC "ppc-lo" "ppc-ha" "ppc-tprel-lo" "ppc-tprel-ha" "ppc-dtprel-lo" "ppc-tlsld-lo" "ppc-toc-lo" "ppc-tls"


<s> const char * AMDGPUDisassembler :: getRegClassName ( unsigned RegClassID ) const { return getContext ( ) . getRegisterInfo ( ) -> getRegClassName ( & AMDGPUMCRegisterClasses [ RegClassID ] ) ; } </s>

Returns the name of the register class .


<s>
const
MCPhysReg
*
AArch64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_AArch64_NoRegs_SaveList
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_AArch64_AllRegs_SaveList
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
CXX_FAST_TLS
)
return
MF
->
getInfo
<
AArch64FunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_AArch64_CXX_TLS_Darwin_PE_SaveList
:
CSR_AArch64_CXX_TLS_Darwin_SaveList
;
else
return
CSR_AArch64_AAPCS_SaveList
;
}
</s>


<s> void Initialize ( MCAsmParser & Parser ) override { MCAsmParserExtension :: Initialize ( Parser ) ; DefaultFunctionTable = GetOrCreateFunctionTableSymbol ( getContext ( ) , "__indirect_function_table" ) ; if ( ! STI -> checkFeatures ( "+reference-types" ) ) DefaultFunctionTable -> setOmitFromLinkingSection ( ) ; } </s>

This method must be called before any actual lowering is done .


<s> static void alpha_extract_integer ( rtx x , HOST_WIDE_INT * p0 , HOST_WIDE_INT * p1 ) { HOST_WIDE_INT i0 , i1 ; if ( GET_CODE ( x ) == CONST_VECTOR ) x = simplify_subreg ( DImode , x , GET_MODE ( x ) , 0 ) ; if ( CONST_INT_P ( x ) ) { i0 = INTVAL ( x ) ; i1 = - ( i0 < 0 ) ; } else if ( HOST_BITS_PER_WIDE_INT >= 64 ) { i0 = CONST_DOUBLE_LOW ( x ) ; i1 = - ( i0 < 0 ) ; } else { i0 = CONST_DOUBLE_LOW ( x ) ; i1 = CONST_DOUBLE_HIGH ( x ) ; } * p0 = i0 ; * p1 = i1 ; } </s>

Given an integral CONST_INT , CONST_DOUBLE , or CONST_VECTOR , return the low 64 bits .


<s> void X86InstrInfo :: buildOutlinedFrame ( MachineBasicBlock & MBB , MachineFunction & MF , const outliner :: OutlinedFunction & OF ) const { if ( OF . FrameConstructionID == MachineOutlinerTailCall ) return ; MachineInstr * retq = BuildMI ( MF , DebugLoc ( ) , get ( X86 :: RET64 ) ) ; MBB . insert ( MBB . end ( ) , retq ) ; } </s>

Insert a custom frame for outlined functions .


<s> void MipsSEFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; const MipsSEInstrInfo & TII = * static_cast < const MipsSEInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; const MipsRegisterInfo & RegInfo = * static_cast < const MipsRegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; unsigned SP = STI . isABI_N64 ( ) ? Mips :: SP_64 : Mips :: SP ; unsigned FP = STI . isABI_N64 ( ) ? Mips :: FP_64 : Mips :: FP ; unsigned ZERO = STI . isABI_N64 ( ) ? Mips :: ZERO_64 : Mips :: ZERO ; unsigned ADDu = STI . isABI_N64 ( ) ? Mips :: DADDu : Mips :: ADDu ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( ADDu ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( MipsFI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = 0 ; J < 4 ; ++ J ) { TII . loadRegFromStackSlot ( MBB , I , ehDataReg ( J ) , MipsFI -> getEhDataRegFI ( J ) , RC , & RegInfo ) ; } } uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize , MBB , MBBI ) ; } </s>


<s> bool X86TargetMachine :: addPostRegAlloc ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createX86FloatingPointStackifierPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s>
SDValue
RV16KTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
report_fatal_error
(
"unimplemented operand"
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
LowerSELECT
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

RV16K
RV16K
"unimplemented operand"
ISD::GlobalAddress
ISD::BlockAddress
ISD::BR_CC
ISD::SELECT
ISD::FRAMEADDR
ISD::RETURNADDR


<s> bool X86PassConfig :: addILPOpts ( ) { addPass ( & EarlyIfConverterID ) ; if ( EnableMachineCombinerPass ) addPass ( & MachineCombinerID ) ; return true ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .


<s> void OutgoingValueHandler :: assignValueToReg ( unsigned ValVReg , const CCValAssign & VA , const EVT & VT ) { unsigned PhysReg = VA . getLocReg ( ) ; const MipsSubtarget & STI = static_cast < const MipsSubtarget & > ( MIRBuilder . getMF ( ) . getSubtarget ( ) ) ; if ( VT == MVT :: f64 && PhysReg >= Mips :: A0 && PhysReg <= Mips :: A3 ) { MIRBuilder . buildInstr ( STI . isFP64bit ( ) ? Mips :: ExtractElementF64_64 : Mips :: ExtractElementF64 ) . addDef ( PhysReg + ( STI . isLittle ( ) ? 1 : 0 ) ) . addUse ( ValVReg ) . addImm ( 1 ) . constrainAllUses ( MIRBuilder . getTII ( ) , * STI . getRegisterInfo ( ) , * STI . getRegBankInfo ( ) ) ; MIRBuilder . buildInstr ( STI . isFP64bit ( ) ? Mips :: ExtractElementF64_64 : Mips :: ExtractElementF64 ) . addDef ( PhysReg + ( STI . isLittle ( ) ? 0 : 1 ) ) . addUse ( ValVReg ) . addImm ( 0 ) . constrainAllUses ( MIRBuilder . getTII ( ) , * STI . getRegisterInfo ( ) , * STI . getRegBankInfo ( ) ) ; } else if ( VT == MVT :: f32 && PhysReg >= Mips :: A0 && PhysReg <= Mips :: A3 ) { MIRBuilder . buildInstr ( Mips :: MFC1 ) . addDef ( PhysReg ) . addUse ( ValVReg ) . constrainAllUses ( MIRBuilder . getTII ( ) , * STI . getRegisterInfo ( ) , * STI . getRegBankInfo ( ) ) ; } else { unsigned ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildCopy ( PhysReg , ExtReg ) ; MIB . addUse ( PhysReg , RegState :: Implicit ) ; } } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


"; WARNING: The following code is valid only with MASM v8.x"

"; This version of MASM is usually shipped with Microsoft "

"; or (possible) further versions. Unfortunately, there is no "

"; dllexported symbols in the earlier versions of MASM in fully "

"_drectve\t segment info alias('.drectve')\n"


" is return block without RETURN instr\n"

Convenience function that returns true if the block ends in a return instruction .


<s> void AMDGPUPreLegalizerCombiner :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < TargetPassConfig > ( ) ; AU . setPreservesCFG ( ) ; getSelectionDAGFallbackAnalysisUsage ( AU ) ; AU . addRequired < GISelKnownBitsAnalysis > ( ) ; AU . addPreserved < GISelKnownBitsAnalysis > ( ) ; if ( ! IsOptNone ) { AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; } AU . addRequired < GISelCSEAnalysisWrapperPass > ( ) ; AU . addPreserved < GISelCSEAnalysisWrapperPass > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static rtx ix86_get_drap_rtx ( void ) { if ( ix86_force_drap || ! ACCUMULATE_OUTGOING_ARGS ) crtl -> need_drap = true ; if ( stack_realign_drap ) { unsigned int regno = find_drap_reg ( ) ; rtx drap_vreg ; rtx arg_ptr ; rtx_insn * seq , * insn ; arg_ptr = gen_rtx_REG ( Pmode , regno ) ; crtl -> drap_reg = arg_ptr ; start_sequence ( ) ; drap_vreg = copy_to_reg ( arg_ptr ) ; seq = get_insns ( ) ; end_sequence ( ) ; insn = emit_insn_before ( seq , NEXT_INSN ( entry_of_function ( ) ) ) ; if ( ! optimize ) { add_reg_note ( insn , REG_CFA_SET_VDRAP , drap_vreg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } return drap_vreg ; } else return NULL ; } </s>

Handle the TARGET_GET_DRAP_RTX hook . Return NULL if no DRAP is needed or an rtx for DRAP otherwise .


<s> static bool shift_p ( rtx x , enum rtx_code code , int amount ) { return ( GET_CODE ( x ) == code && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT && INTVAL ( XEXP ( x , 1 ) ) == amount ) ; } </s>

Determine whether X is a shift with code CODE and an integer amount AMOUNT .


<s> void X86AsmInstrumentation :: EmitInstruction ( MCStreamer & Out , const MCInst & Inst ) { Out . EmitInstruction ( Inst , STI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < AAResultsWrapperPass > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> void printPCRelImm ( const MCInst * MI , uint64_t , unsigned OpNo , raw_ostream & O ) { printPCRelImm ( MI , OpNo , O ) ; } </s>


"built-in function %s requires Nios II R%d"

Implement TARGET_EXPAND_BUILTIN . Expand an expression EXP that calls a built-in function , with result going to TARGET if that 's convenient ( and in mode MODE if that 's convenient ) . SUBTARGET may be used as the target for computing one of EXP 's operands . IGNORE is nonzero if the value is to be ignored .


"  Copied r%d to a scalar register r%d for insn %d\n"

Convert all definitions of register REGNO and fix its uses . Scalar copies may be created in case register is used in not convertible insn .


<s> SDValue SystemZTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ZERO_EXTEND : return combineZERO_EXTEND ( N , DCI ) ; case ISD :: SIGN_EXTEND : return combineSIGN_EXTEND ( N , DCI ) ; case ISD :: SIGN_EXTEND_INREG : return combineSIGN_EXTEND_INREG ( N , DCI ) ; case SystemZISD :: MERGE_HIGH : case SystemZISD :: MERGE_LOW : return combineMERGE ( N , DCI ) ; case ISD :: LOAD : return combineLOAD ( N , DCI ) ; case ISD :: STORE : return combineSTORE ( N , DCI ) ; case ISD :: EXTRACT_VECTOR_ELT : return combineEXTRACT_VECTOR_ELT ( N , DCI ) ; case SystemZISD :: JOIN_DWORDS : return combineJOIN_DWORDS ( N , DCI ) ; case ISD :: FP_ROUND : return combineFP_ROUND ( N , DCI ) ; case ISD :: FP_EXTEND : return combineFP_EXTEND ( N , DCI ) ; case ISD :: BSWAP : return combineBSWAP ( N , DCI ) ; case SystemZISD :: BR_CCMASK : return combineBR_CCMASK ( N , DCI ) ; case SystemZISD :: SELECT_CCMASK : return combineSELECT_CCMASK ( N , DCI ) ; case SystemZISD :: GET_CCMASK : return combineGET_CCMASK ( N , DCI ) ; case ISD :: SDIV : case ISD :: UDIV : case ISD :: SREM : case ISD :: UREM : return combineIntDIVREM ( N , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> static int rs6000_builtin_vectorization_cost ( enum vect_cost_for_stmt type_of_cost , tree vectype , int misalign ) { unsigned elements ; tree elem_type ; switch ( type_of_cost ) { case scalar_stmt : case scalar_load : case scalar_store : case vector_stmt : case vector_load : case vector_store : case vec_to_scalar : case scalar_to_vec : case cond_branch_not_taken : return 1 ; case vec_perm : if ( TARGET_VSX ) return 3 ; else return 1 ; case vec_promote_demote : if ( TARGET_VSX ) return 4 ; else return 1 ; case cond_branch_taken : return 3 ; case unaligned_load : case vector_gather_load : if ( TARGET_EFFICIENT_UNALIGNED_VSX ) return 1 ; if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == 2 ) return 2 ; if ( elements == 4 ) { switch ( misalign ) { case 8 : return 2 ; case - 1 : case 4 : case 12 : return 22 ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return 2 ; case unaligned_store : case vector_scatter_store : if ( TARGET_EFFICIENT_UNALIGNED_VSX ) return 1 ; if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == 2 ) return 2 ; if ( elements == 4 ) { switch ( misalign ) { case 8 : return 2 ; case - 1 : case 4 : case 12 : return 23 ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return 2 ; case vec_construct : elem_type = TREE_TYPE ( vectype ) ; if ( SCALAR_FLOAT_TYPE_P ( elem_type ) && TYPE_PRECISION ( elem_type ) == 32 ) return 5 ; else if ( INTEGRAL_TYPE_P ( elem_type ) ) { if ( TARGET_P9_VECTOR ) return TYPE_VECTOR_SUBPARTS ( vectype ) - 1 + 2 ; else return TYPE_VECTOR_SUBPARTS ( vectype ) - 1 + 5 ; } else return 2 ; default : gcc_unreachable ( ) ; } } </s>


<s> static bool visium_class_likely_spilled_p ( reg_class_t rclass ATTRIBUTE_UNUSED ) { return false ; } </s>

Return true if pseudos that have been assigned to registers of RCLASS would likely be spilled because registers of RCLASS are needed for spill registers .


"could not locate MCU data file %<devices.csv%>"

Main entry point to load the MCU data for the given -mmcu into extracted_mcu_data . First , the `` devices.csv '' MCU data file is searched for , if it is found , and the MCU has a record in it , then that data is used . Otherwise , hard_msp430_mcu_data ( initialized at the bottom of this file ) is searched for the MCU name . This function only needs to be executed once , but it can be first called from a number of different locations .


<s> unsigned X86VectorTargetTransformInfo :: getNumberOfRegisters ( bool Vector ) const { const X86Subtarget & ST = TLI -> getTargetMachine ( ) . getSubtarget < X86Subtarget > ( ) ; if ( ST . is64Bit ( ) ) return 16 ; return 8 ; } </s>


<s> int pa_attr_length_millicode_call ( rtx_insn * insn ) { unsigned long distance = - 1 ; unsigned long total = IN_NAMED_SECTION_P ( cfun -> decl ) ? 0 : total_code_bytes ; if ( INSN_ADDRESSES_SET_P ( ) ) { distance = ( total + insn_current_reference_address ( insn ) ) ; if ( distance < total ) distance = - 1 ; } if ( TARGET_64BIT ) { if ( ! TARGET_LONG_CALLS && distance < 7600000 ) return 8 ; return 20 ; } else if ( TARGET_PORTABLE_RUNTIME ) return 24 ; else { if ( ! TARGET_LONG_CALLS && distance < MAX_PCREL17F_OFFSET ) return 8 ; if ( ! flag_pic ) return 12 ; return 24 ; } } </s>

Return the attribute length for the millicode call instruction INSN . The length must match the code generated by pa_output_millicode_call . We include the delay slot in the returned length as it is better to over estimate the length than to under estimate it .


<s> rtx visium_return_addr_rtx ( int count , rtx frame ATTRIBUTE_UNUSED ) { if ( count != 0 ) return NULL_RTX ; visium_frame_needed = true ; return gen_frame_mem ( Pmode , plus_constant ( Pmode , hard_frame_pointer_rtx , 4 ) ) ; } </s>

A C expression whose value is RTL representing the value of the return address for the frame COUNT steps up from the current frame , after the prologue . FRAMEADDR is the frame pointer of the COUNT frame , or the frame pointer of the COUNT - 1 frame if ` RETURN_ADDR_IN_PREVIOUS_FRAME ' is defined . The value of the expression must always be the correct address when COUNT is zero , but may be ` NULL_RTX ' if there is not way to determine the return address of other frames .


<s> static void tilegx_reorg ( void ) { compute_bb_for_insn ( ) ; if ( flag_reorder_blocks_and_partition ) { tilegx_fixup_pcrel_references ( ) ; } if ( flag_schedule_insns_after_reload ) { split_all_insns ( ) ; timevar_push ( TV_SCHED2 ) ; schedule_insns ( ) ; timevar_pop ( TV_SCHED2 ) ; tilegx_gen_bundles ( ) ; } df_analyze ( ) ; if ( flag_var_tracking ) { timevar_push ( TV_VAR_TRACKING ) ; variable_tracking_main ( ) ; reorder_var_tracking_notes ( ) ; timevar_pop ( TV_VAR_TRACKING ) ; } df_finish_pass ( false ) ; } </s>

Perform machine dependent operations on the rtl chain INSNS .


<s> std :: string AMDGPUIntrinsicInfo :: getName ( unsigned IntrID , Type * * Tys , unsigned NumTys ) const { return getName ( IntrID , makeArrayRef ( Tys , NumTys ) ) . str ( ) ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> void eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const override { MBB . erase ( MI ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool csky_valid_fpuv2_mem_operand ( rtx op ) { struct csky_address addr ; if ( GET_CODE ( op ) != MEM ) return false ; if ( ! decompose_csky_address ( XEXP ( op , 0 ) , & addr ) ) return false ; if ( ! is_csky_address_register_rtx_p ( addr . base , 0 ) ) return false ; if ( addr . index ) { if ( ! is_csky_address_register_rtx_p ( addr . index , 0 ) ) return false ; if ( addr . scale == 1 || addr . scale == 2 || addr . scale == 4 || addr . scale == 8 ) return true ; return false ; } else if ( addr . disp ) { rtx disp = addr . disp ; if ( ! CONST_INT_P ( disp ) ) return false ; if ( ( ( unsigned ) INTVAL ( disp ) % 4 ) == 0 && ( unsigned ) INTVAL ( disp ) <= ( unsigned ) 1020 ) return true ; return false ; } return true ; } </s>

Support for the Q memory constraint . Returns true if OP is a MEM RTX with an address consisting of base + index or base + displacement .


<s>
TargetTransformInfo
MipsTargetMachine
::
getTargetTransformInfo
(
const
Function
&
F
)
const
{
if
(
Subtarget
->
allowMixed16_32
(
)
)
{
LLVM_DEBUG
(
errs
(
)
<<
"No Target Transform Info Pass Added\n"
)
;
return
TargetTransformInfo
(
F
.
getParent
(
)
->
getDataLayout
(
)
)
;
}
LLVM_DEBUG
(
errs
(
)
<<
"Target Transform Info Pass Added\n"
)
;
return
TargetTransformInfo
(
BasicTTIImpl
(
this
,
F
)
)
;
}
</s>

Get a TargetTransformInfo implementation for the target .

Mips
Mips
"No Target Transform Info Pass Added\n"
"Target Transform Info Pass Added\n"


<s> static void mips_sim_finish_insn ( struct mips_sim * state , rtx insn ) { if ( JUMP_P ( insn ) ) mips_sim_issue_nop ( state ) ; switch ( GET_CODE ( SEQ_BEGIN ( insn ) ) ) { case CODE_LABEL : case CALL_INSN : mips_sim_reset ( state ) ; break ; case JUMP_INSN : if ( INSN_ANNULLED_BRANCH_P ( SEQ_BEGIN ( insn ) ) ) mips_sim_reset ( state ) ; break ; default : break ; } } </s>

Update simulation state STATE so that it 's ready to accept the instruction after INSN . INSN should be part of the main rtl chain , not a member of a SEQUENCE .


<s> void UPTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { if ( ! printAliasInstr ( MI , O ) ) printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static bool arm_vectorize_vec_perm_const ( machine_mode vmode , machine_mode op_mode , rtx target , rtx op0 , rtx op1 , const vec_perm_indices & sel ) { if ( vmode != op_mode ) return false ; struct expand_vec_perm_d d ; int i , nelt , which ; if ( ! VALID_NEON_DREG_MODE ( vmode ) && ! VALID_NEON_QREG_MODE ( vmode ) ) return false ; d . target = target ; if ( op0 ) { rtx nop0 = force_reg ( vmode , op0 ) ; if ( op0 == op1 ) op1 = nop0 ; op0 = nop0 ; } if ( op1 ) op1 = force_reg ( vmode , op1 ) ; d . op0 = op0 ; d . op1 = op1 ; d . vmode = vmode ; gcc_assert ( VECTOR_MODE_P ( d . vmode ) ) ; d . testing_p = ! target ; nelt = GET_MODE_NUNITS ( d . vmode ) ; for ( i = which = 0 ; i < nelt ; ++ i ) { int ei = sel [ i ] & ( 2 * nelt - 1 ) ; which |= ( ei < nelt ? 1 : 2 ) ; } switch ( which ) { default : gcc_unreachable ( ) ; case 3 : d . one_vector_p = false ; if ( d . testing_p || ! rtx_equal_p ( op0 , op1 ) ) break ; case 2 : d . op0 = op1 ; d . one_vector_p = true ; break ; case 1 : d . op1 = op0 ; d . one_vector_p = true ; break ; } d . perm . new_vector ( sel . encoding ( ) , d . one_vector_p ? 1 : 2 , nelt ) ; if ( ! d . testing_p ) return arm_expand_vec_perm_const_1 ( & d ) ; d . target = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 1 ) ; d . op1 = d . op0 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 2 ) ; if ( ! d . one_vector_p ) d . op1 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 3 ) ; start_sequence ( ) ; bool ret = arm_expand_vec_perm_const_1 ( & d ) ; end_sequence ( ) ; return ret ; } </s>


<s> static bool or1k_legitimate_address_p ( machine_mode , rtx x , bool strict_p ) { rtx base , addend ; switch ( GET_CODE ( x ) ) { case REG : base = x ; break ; case PLUS : base = XEXP ( x , 0 ) ; addend = XEXP ( x , 1 ) ; if ( ! REG_P ( base ) ) return false ; if ( ! strict_p && virtual_frame_reg_operand ( base , VOIDmode ) ) return CONST_INT_P ( addend ) ; if ( ! satisfies_constraint_I ( addend ) ) return false ; break ; case LO_SUM : base = XEXP ( x , 0 ) ; if ( ! REG_P ( base ) ) return false ; x = XEXP ( x , 1 ) ; switch ( GET_CODE ( x ) ) { case CONST : case SYMBOL_REF : case LABEL_REF : break ; case UNSPEC : switch ( XINT ( x , 1 ) ) { case UNSPEC_GOT : case UNSPEC_GOTOFF : case UNSPEC_TPOFF : case UNSPEC_GOTTPOFF : break ; default : return false ; } break ; default : return false ; } break ; default : return false ; } unsigned regno = REGNO ( base ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) { if ( strict_p ) regno = reg_renumber [ regno ] ; else return true ; } if ( strict_p ) return regno <= 31 ; else return REGNO_OK_FOR_BASE_P ( regno ) ; } </s>

Worker for TARGET_LEGITIMATE_ADDRESS_P . Returns true if X is a legitimate address RTX on OpenRISC .


<s> static void vr4130_true_reg_dependence_p_1 ( rtx x , const_rtx pat ATTRIBUTE_UNUSED , void * data ) { rtx * insn_ptr ; insn_ptr = ( rtx * ) data ; if ( REG_P ( x ) && * insn_ptr != 0 && reg_referenced_p ( x , PATTERN ( * insn_ptr ) ) ) * insn_ptr = 0 ; } </s>

A note_stores callback used by vr4130_true_reg_dependence_p . DATA points to an rtx that is initially an instruction . Nullify the rtx if the instruction uses the value of register X .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"PowerPC Machine Code Emitter"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool aarch64_is_long_call_p ( rtx sym ) { return aarch64_decl_is_long_call_p ( SYMBOL_REF_DECL ( sym ) ) ; } </s>

Return true if calls to symbol-ref SYM should be treated as long-calls ( ie called via a register ) .


"Hardware instruction generated for atomic "

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


"********** Replace Physical Registers **********\n"

"LiveIntervals shouldn't be active yet!"

runOnMachineFunction - Emit the function body .


<s> const MCPhysReg * M88kRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_M88k_SaveList ; } </s>


<s> TargetTransformInfo TPCTargetMachine :: getTargetTransformInfo ( const Function & F ) { return TargetTransformInfo ( TPCTTIImpl ( this , F ) ) ; } </s>


"failed to parse register and immediate pair"

ParseInstruction - Parse one assembly instruction .


<s>
bool
AMDGPUAsmParser
::
isInlineConstant
(
const
MCInst
&
Inst
,
unsigned
OpIdx
)
const
{
const
MCInstrDesc
&
Desc
=
MII
.
get
(
Inst
.
getOpcode
(
)
)
;
if
(
!
AMDGPU
::
isSISrcOperand
(
Desc
,
OpIdx
)
)
{
return
false
;
}
const
MCOperand
&
MO
=
Inst
.
getOperand
(
OpIdx
)
;
int64_t
Val
=
MO
.
getImm
(
)
;
auto
OpSize
=
AMDGPU
::
getOperandSize
(
Desc
,
OpIdx
)
;
switch
(
OpSize
)
{
case
8
:
return
AMDGPU
::
isInlinableLiteral64
(
Val
,
hasInv2PiInlineImm
(
)
)
;
case
4
:
return
AMDGPU
::
isInlinableLiteral32
(
Val
,
hasInv2PiInlineImm
(
)
)
;
case
2
:
{
const
unsigned
OperandType
=
Desc
.
OpInfo
[
OpIdx
]
.
OperandType
;
if
(
OperandType
==
AMDGPU
::
OPERAND_REG_IMM_INT16
||
OperandType
==
AMDGPU
::
OPERAND_REG_INLINE_C_INT16
||
OperandType
==
AMDGPU
::
OPERAND_REG_INLINE_AC_INT16
)
return
AMDGPU
::
isInlinableIntLiteral
(
Val
)
;
if
(
OperandType
==
AMDGPU
::
OPERAND_REG_INLINE_C_V2INT16
||
OperandType
==
AMDGPU
::
OPERAND_REG_INLINE_AC_V2INT16
||
OperandType
==
AMDGPU
::
OPERAND_REG_IMM_V2INT16
)
return
AMDGPU
::
isInlinableIntLiteralV216
(
Val
)
;
if
(
OperandType
==
AMDGPU
::
OPERAND_REG_INLINE_C_V2FP16
||
OperandType
==
AMDGPU
::
OPERAND_REG_INLINE_AC_V2FP16
||
OperandType
==
AMDGPU
::
OPERAND_REG_IMM_V2FP16
)
return
AMDGPU
::
isInlinableLiteralV216
(
Val
,
hasInv2PiInlineImm
(
)
)
;
return
AMDGPU
::
isInlinableLiteral16
(
Val
,
hasInv2PiInlineImm
(
)
)
;
}
default
:
llvm_unreachable
(
"invalid operand size"
)
;
}
}
</s>

returns true if the operand OpIdx in MI is a valid inline immediate .


"\ninit_cumulative_args, fntype = 0x%.8lx"

Handle the INIT_CUMULATIVE_ARGS macro . Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is 0 .


<s> int ccr_bit ( rtx op , int scc_p ) { enum rtx_code code = GET_CODE ( op ) ; machine_mode cc_mode ; int cc_regnum ; int base_bit ; rtx reg ; if ( ! COMPARISON_P ( op ) ) return - 1 ; reg = XEXP ( op , 0 ) ; if ( ! REG_P ( reg ) || ! CR_REGNO_P ( REGNO ( reg ) ) ) return - 1 ; cc_mode = GET_MODE ( reg ) ; cc_regnum = REGNO ( reg ) ; base_bit = 4 * ( cc_regnum - CR0_REGNO ) ; validate_condition_mode ( code , cc_mode ) ; if ( scc_p ) switch ( code ) { case EQ : case GT : case LT : case UNORDERED : case GTU : case LTU : break ; default : return - 1 ; } switch ( code ) { case NE : return scc_p ? base_bit + 3 : base_bit + 2 ; case EQ : return base_bit + 2 ; case GT : case GTU : case UNLE : return base_bit + 1 ; case LT : case LTU : case UNGE : return base_bit ; case ORDERED : case UNORDERED : return base_bit + 3 ; case GE : case GEU : return scc_p ? base_bit + 3 : base_bit ; case LE : case LEU : return scc_p ? base_bit + 3 : base_bit + 1 ; default : return - 1 ; } } </s>

Given a comparison operation , return the bit number in CCR to test . We know this is a valid comparison . SCC_P is 1 if this is for an scc . That means that % D will have been used instead of % C , so the bits will be in different places . Return -1 if OP is n't a valid comparison for some reason .


<s> unsigned int compute_plussi_length ( rtx * operands ) { enum machine_mode mode = GET_MODE ( operands [ 0 ] ) ; gcc_assert ( mode == SImode ) ; if ( TARGET_H8300 ) { if ( GET_CODE ( operands [ 2 ] ) == REG ) return 6 ; if ( GET_CODE ( operands [ 2 ] ) == CONST_INT ) { HOST_WIDE_INT n = INTVAL ( operands [ 2 ] ) ; if ( ( n & 0xffffff ) == 0 ) return 2 ; if ( ( n & 0xffff ) == 0 ) return 4 ; if ( ( n & 0xff ) == 0 ) return 6 ; } return 8 ; } else { if ( GET_CODE ( operands [ 2 ] ) == CONST_INT && register_operand ( operands [ 1 ] , VOIDmode ) ) { HOST_WIDE_INT intval = INTVAL ( operands [ 2 ] ) ; if ( TARGET_H8300SX && ( intval >= 1 && intval <= 7 ) ) return 2 ; if ( TARGET_H8300SX && ( intval >= - 7 && intval <= - 1 ) ) return 2 ; switch ( ( unsigned int ) intval & 0xffffffff ) { case 0x00000001 : case 0x00000002 : case 0x00000004 : return 2 ; case 0xffffffff : case 0xfffffffe : case 0xfffffffc : return 2 ; case 0x00010000 : case 0x00020000 : return 2 ; case 0xffff0000 : case 0xfffe0000 : return 2 ; } if ( ( intval & 0xffff ) == 0 ) return 4 ; } if ( GET_CODE ( operands [ 2 ] ) == CONST_INT && INTVAL ( operands [ 2 ] ) < 0 ) return h8300_length_from_table ( operands [ 0 ] , GEN_INT ( - INTVAL ( operands [ 2 ] ) ) , & addl_length_table ) ; else return h8300_length_from_table ( operands [ 0 ] , operands [ 2 ] , & addl_length_table ) ; return 6 ; } } </s>

Compute the length of an addition insn .


<s> static bool flow_dependent_p ( rtx insn , rtx dep_insn ) { rtx tmp = PATTERN ( insn ) ; note_stores ( PATTERN ( dep_insn ) , flow_dependent_p_1 , & tmp ) ; return tmp == NULL_RTX ; } </s>

Check if INSN is flow-dependent on DEP_INSN . Can also be used to check if DEP_INSN is anti-flow dependent on INSN .


<s> ATTRIBUTE_UNUSED static section * x86_64_elf_select_section ( tree decl , int reloc , unsigned HOST_WIDE_INT align ) { if ( ix86_in_large_data_p ( decl ) ) { const char * sname = NULL ; unsigned int flags = SECTION_WRITE | SECTION_LARGE ; switch ( categorize_decl_for_section ( decl , reloc ) ) { case SECCAT_DATA : sname = ".ldata" ; break ; case SECCAT_DATA_REL : sname = ".ldata.rel" ; break ; case SECCAT_DATA_REL_LOCAL : sname = ".ldata.rel.local" ; break ; case SECCAT_DATA_REL_RO : sname = ".ldata.rel.ro" ; break ; case SECCAT_DATA_REL_RO_LOCAL : sname = ".ldata.rel.ro.local" ; break ; case SECCAT_BSS : sname = ".lbss" ; flags |= SECTION_BSS ; break ; case SECCAT_RODATA : case SECCAT_RODATA_MERGE_STR : case SECCAT_RODATA_MERGE_STR_INIT : case SECCAT_RODATA_MERGE_CONST : sname = ".lrodata" ; flags &= ~ SECTION_WRITE ; break ; case SECCAT_SRODATA : case SECCAT_SDATA : case SECCAT_SBSS : gcc_unreachable ( ) ; case SECCAT_TEXT : case SECCAT_TDATA : case SECCAT_TBSS : break ; } if ( sname ) { if ( ! DECL_P ( decl ) ) return get_section ( sname , flags , NULL ) ; return get_named_section ( decl , sname , reloc ) ; } } return default_elf_select_section ( decl , reloc , align ) ; } </s>

switch to the appropriate section for output of DECL . DECL is either a ` VAR_DECL ' node or a constant of some sort . RELOC indicates whether forming the initial value of DECL requires link-time relocations .


<s> unsigned MipsFunctionInfo :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( & getGlobalBaseRegClass ( MF ) ) ; return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> std :: pair < unsigned , const TargetRegisterClass * > SPUTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'b' : case 'r' : if ( VT == MVT :: i64 ) return std :: make_pair ( 0U , & SPU :: R64CRegClass ) ; return std :: make_pair ( 0U , & SPU :: R32CRegClass ) ; case 'f' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , & SPU :: R32FPRegClass ) ; if ( VT == MVT :: f64 ) return std :: make_pair ( 0U , & SPU :: R64FPRegClass ) ; break ; case 'v' : return std :: make_pair ( 0U , & SPU :: GPRCRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> static bool rtx_ok_for_offset_p ( machine_mode mode , rtx op ) { if ( ! CONST_INT_P ( op ) || INTVAL ( op ) < 0 ) return false ; switch ( mode ) { case E_QImode : return INTVAL ( op ) <= 31 ; case E_HImode : return ( INTVAL ( op ) % 2 ) == 0 && INTVAL ( op ) < 63 ; case E_SImode : case E_SFmode : return ( INTVAL ( op ) % 4 ) == 0 && INTVAL ( op ) < 127 ; case E_DImode : case E_DFmode : return ( INTVAL ( op ) % 4 ) == 0 && INTVAL ( op ) < 123 ; default : return false ; } } </s>

Return true if OP is an offset suitable for use as a displacement in the address of a memory access in mode MODE .


<s>
void
SystemZInstrInfo
::
insertSelect
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DstReg
,
ArrayRef
<
MachineOperand
>
Pred
,
unsigned
TrueReg
,
unsigned
FalseReg
)
const
{
MachineRegisterInfo
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
const
TargetRegisterClass
*
RC
=
MRI
.
getRegClass
(
DstReg
)
;
assert
(
Pred
.
size
(
)
==
2
&&
"Invalid condition"
)
;
unsigned
CCValid
=
Pred
[
0
]
.
getImm
(
)
;
unsigned
CCMask
=
Pred
[
1
]
.
getImm
(
)
;
unsigned
Opc
;
if
(
SystemZ
::
GRX32BitRegClass
.
hasSubClassEq
(
RC
)
)
{
if
(
STI
.
hasLoadStoreOnCond2
(
)
)
Opc
=
SystemZ
::
LOCRMux
;
else
{
Opc
=
SystemZ
::
LOCR
;
MRI
.
constrainRegClass
(
DstReg
,
&
SystemZ
::
GR32BitRegClass
)
;
}
}
else
if
(
SystemZ
::
GR64BitRegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
SystemZ
::
LOCGR
;
else
llvm_unreachable
(
"Invalid register class"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DstReg
)
.
addReg
(
FalseReg
)
.
addReg
(
TrueReg
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
;
}
</s>

Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true , and FalseReg to DstReg when Cond is false .


<s> unsigned getNumFixupKinds ( ) const override { return SHUXI :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const override { if ( Fixup . getKind ( ) >= FirstLiteralRelocationKind ) return ; Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = Endian == support :: little ? i : ( NumBytes - 1 ) - i ; Data [ Offset + Idx ] |= uint8_t ( ( Value >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void PPCInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { const char * RegName = getRegisterName ( RegNo ) ; if ( RegName [ 0 ] == 'q' ) { std :: string RN ( RegName ) ; RN [ 0 ] = 'f' ; OS << RN ; return ; } OS << RegName ; } </s>


<s> void AArch64LongBranchStub :: applyFixup ( Relocation & pSrcReloc , IRBuilder & pBuilder , BranchIsland & pIsland ) { LDSymbol * symbol = pSrcReloc . symInfo ( ) -> outSymbol ( ) ; uint64_t dest = symbol -> fragRef ( ) -> frag ( ) -> getParent ( ) -> getSection ( ) . addr ( ) + symbol -> fragRef ( ) -> getOutputOffset ( ) ; uint64_t src = pIsland . getParent ( ) -> getSection ( ) . addr ( ) + pIsland . offset ( ) + pIsland . size ( ) ; if ( isValidForADRP ( src , dest ) ) { m_pData = ADRP_TEMPLATE ; m_Name = "adrp_veneer" ; m_Size = sizeof ( ADRP_TEMPLATE ) ; getFixupList ( ) . clear ( ) ; addFixup ( 0x0 , 0 , llvm :: ELF :: R_AARCH64_ADR_PREL_PG_HI21 ) ; addFixup ( 0x4 , 0 , llvm :: ELF :: R_AARCH64_ADD_ABS_LO12_NC ) ; } Stub :: applyFixup ( pSrcReloc , pBuilder , pIsland ) ; } </s>


<s> bool SNESTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { EVT VT ; SDLoc DL ( N ) ; if ( const LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; if ( LD -> getExtensionType ( ) != ISD :: NON_EXTLOAD ) return false ; } else if ( const StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; if ( SNES :: isProgramMemoryAccess ( ST ) ) { return false ; } } else { return false ; } if ( VT != MVT :: i8 && VT != MVT :: i16 ) { return false ; } if ( Op -> getOpcode ( ) != ISD :: ADD && Op -> getOpcode ( ) != ISD :: SUB ) { return false ; } if ( const ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ) { int RHSC = RHS -> getSExtValue ( ) ; if ( Op -> getOpcode ( ) == ISD :: SUB ) RHSC = - RHSC ; if ( ( VT == MVT :: i16 && RHSC != 2 ) || ( VT == MVT :: i8 && RHSC != 1 ) ) { return false ; } Base = Op -> getOperand ( 0 ) ; Offset = DAG . getConstant ( RHSC , DL , MVT :: i8 ) ; AM = ISD :: POST_INC ; return true ; } return false ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .


<s> bool XCorePassConfig :: addInstSelector ( ) { addPass ( createXCoreISelDag ( getXCoreTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s>
SDNode
*
SystemZDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
return
0
;
}
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
switch
(
Opcode
)
{
case
ISD
::
OR
:
case
ISD
::
XOR
:
if
(
Node
->
getValueType
(
0
)
==
MVT
::
i64
)
if
(
ConstantSDNode
*
Op1
=
dyn_cast
<
ConstantSDNode
>
(
Node
->
getOperand
(
1
)
)
)
{
uint64_t
Val
=
Op1
->
getZExtValue
(
)
;
if
(
!
SystemZ
::
isImmLF
(
Val
)
&&
!
SystemZ
::
isImmHF
(
Val
)
)
Node
=
splitLargeImmediate
(
Opcode
,
Node
,
Node
->
getOperand
(
0
)
,
Val
uint32_t
(
Val
)
,
uint32_t
(
Val
)
)
;
}
break
;
case
ISD
::
Constant
:
if
(
Node
->
getValueType
(
0
)
==
MVT
::
i64
)
{
uint64_t
Val
=
cast
<
ConstantSDNode
>
(
Node
)
->
getZExtValue
(
)
;
if
(
!
SystemZ
::
isImmLF
(
Val
)
&&
!
SystemZ
::
isImmHF
(
Val
)
&&
!
isInt
<
32
>
(
Val
)
)
Node
=
splitLargeImmediate
(
ISD
::
OR
,
Node
,
SDValue
(
)
,
Val
uint32_t
(
Val
)
,
uint32_t
(
Val
)
)
;
}
break
;
case
ISD
::
ATOMIC_LOAD_SUB
:
if
(
ConstantSDNode
*
Op2
=
dyn_cast
<
ConstantSDNode
>
(
Node
->
getOperand
(
2
)
)
)
{
uint64_t
Value
=
Op2
->
getZExtValue
(
)
;
EVT
VT
=
Node
->
getValueType
(
0
)
;
if
(
VT
==
MVT
::
i32
||
isInt
<
32
>
(
Value
)
)
{
SDValue
Ops
[
]
=
{
Node
->
getOperand
(
0
)
,
Node
->
getOperand
(
1
)
,
CurDAG
->
getConstant
(
int32_t
(
Value
)
,
VT
)
}
;
Node
=
CurDAG
->
MorphNodeTo
(
Node
,
ISD
::
ATOMIC_LOAD_ADD
,
Node
->
getVTList
(
)
,
Ops
,
array_lengthof
(
Ops
)
)
;
}
}
break
;
}
SDNode
*
ResNode
=
SelectCode
(
Node
)
;
DEBUG
(
errs
(
)
<<
"=> "
;
if
(
ResNode
==
||
ResNode
==
Node
)
Node
->
dump
(
CurDAG
)
;
else
ResNode
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
;
)
;
return
ResNode
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s>
void
XCoreInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
bool
GRDest
=
XCore
::
GRRegsRegClass
.
contains
(
DestReg
)
;
bool
GRSrc
=
XCore
::
GRRegsRegClass
.
contains
(
SrcReg
)
;
if
(
GRDest
&&
GRSrc
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
XCore
::
ADD_2rus
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
0
)
;
return
;
}
if
(
GRDest
&&
SrcReg
==
XCore
::
SP
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
XCore
::
LDAWSP_ru6
)
,
DestReg
)
.
addImm
(
0
)
;
return
;
}
if
(
DestReg
==
XCore
::
SP
&&
GRSrc
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
XCore
::
SETSP_1r
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
return
;
}
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
</s>


<s> static bool aarch64_evpc_trn ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> nelt ; rtx out , in0 , in1 , x ; rtx ( * gen ) ( rtx , rtx , rtx ) ; machine_mode vmode = d -> vmode ; if ( GET_MODE_UNIT_SIZE ( vmode ) > 8 ) return false ; if ( d -> perm [ 0 ] == 0 ) odd = 0 ; else if ( d -> perm [ 0 ] == 1 ) odd = 1 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt ; i += 2 ) { if ( d -> perm [ i ] != i + odd ) return false ; if ( d -> perm [ i + 1 ] != ( ( i + nelt + odd ) & mask ) ) return false ; } if ( d -> testing_p ) return true ; in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN ) { x = in0 , in0 = in1 , in1 = x ; odd = ! odd ; } out = d -> target ; if ( odd ) { switch ( vmode ) { case V16QImode : gen = gen_aarch64_trn2v16qi ; break ; case V8QImode : gen = gen_aarch64_trn2v8qi ; break ; case V8HImode : gen = gen_aarch64_trn2v8hi ; break ; case V4HImode : gen = gen_aarch64_trn2v4hi ; break ; case V4SImode : gen = gen_aarch64_trn2v4si ; break ; case V2SImode : gen = gen_aarch64_trn2v2si ; break ; case V2DImode : gen = gen_aarch64_trn2v2di ; break ; case V4HFmode : gen = gen_aarch64_trn2v4hf ; break ; case V8HFmode : gen = gen_aarch64_trn2v8hf ; break ; case V4SFmode : gen = gen_aarch64_trn2v4sf ; break ; case V2SFmode : gen = gen_aarch64_trn2v2sf ; break ; case V2DFmode : gen = gen_aarch64_trn2v2df ; break ; default : return false ; } } else { switch ( vmode ) { case V16QImode : gen = gen_aarch64_trn1v16qi ; break ; case V8QImode : gen = gen_aarch64_trn1v8qi ; break ; case V8HImode : gen = gen_aarch64_trn1v8hi ; break ; case V4HImode : gen = gen_aarch64_trn1v4hi ; break ; case V4SImode : gen = gen_aarch64_trn1v4si ; break ; case V2SImode : gen = gen_aarch64_trn1v2si ; break ; case V2DImode : gen = gen_aarch64_trn1v2di ; break ; case V4HFmode : gen = gen_aarch64_trn1v4hf ; break ; case V8HFmode : gen = gen_aarch64_trn1v8hf ; break ; case V4SFmode : gen = gen_aarch64_trn1v4sf ; break ; case V2SFmode : gen = gen_aarch64_trn1v2sf ; break ; case V2DFmode : gen = gen_aarch64_trn1v2df ; break ; default : return false ; } } emit_insn ( gen ( out , in0 , in1 ) ) ; return true ; } </s>

Recognize patterns suitable for the TRN instructions .


"Unknown fence ordering in emitLeadingFence"


"PatmosInstrInfo::PredicateInstruction() can't handle bundles"

"Cannot predicate an instruction already predicated."

Convert the instruction into a predicated instruction .


Function to tell the preprocessor about the defines for the current target .


<s> static enum insn_code aarch64_constant_pool_reload_icode ( machine_mode mode ) { switch ( mode ) { case E_SFmode : return CODE_FOR_aarch64_reload_movcpsfdi ; case E_DFmode : return CODE_FOR_aarch64_reload_movcpdfdi ; case E_TFmode : return CODE_FOR_aarch64_reload_movcptfdi ; case E_V8QImode : return CODE_FOR_aarch64_reload_movcpv8qidi ; case E_V16QImode : return CODE_FOR_aarch64_reload_movcpv16qidi ; case E_V4HImode : return CODE_FOR_aarch64_reload_movcpv4hidi ; case E_V8HImode : return CODE_FOR_aarch64_reload_movcpv8hidi ; case E_V2SImode : return CODE_FOR_aarch64_reload_movcpv2sidi ; case E_V4SImode : return CODE_FOR_aarch64_reload_movcpv4sidi ; case E_V2DImode : return CODE_FOR_aarch64_reload_movcpv2didi ; case E_V2DFmode : return CODE_FOR_aarch64_reload_movcpv2dfdi ; default : gcc_unreachable ( ) ; } gcc_unreachable ( ) ; } </s>

Return the reload icode required for a constant pool in mode .


"insertNop does not support MIPS16e mode at this time"


<s> void emitInst ( uint32_t Inst ) { char Buffer [ 4 ] ; for ( unsigned I = 0 ; I < 4 ; ++ I ) { Buffer [ I ] = uint8_t ( Inst ) ; Inst >>= 8 ; } EmitA64MappingSymbol ( ) ; MCELFStreamer :: emitBytes ( StringRef ( Buffer , 4 ) ) ; } </s>

Callback used to implement the .inst directive .


"SRetReturnReg should have been set in LowerFormalArguments()."

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> SDValue X86TargetLowering :: getPICJumpTableRelocBase ( SDValue Table , SelectionDAG & DAG ) const { if ( ! Subtarget -> is64Bit ( ) ) return DAG . getNode ( X86ISD :: GlobalBaseReg , SDLoc ( ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; return Table ; } </s>

Returns relocation base for the given PIC jumptable .


<s> Register getGlobalBaseReg ( ) const { return GlobalBaseReg ; } </s>


<s> static void frv_reorg_packet ( void ) { frv_fill_unused_units ( GROUP_I ) ; frv_fill_unused_units ( GROUP_FM ) ; frv_align_label ( ) ; } </s>

Subroutine of frv_reorg , called after each packet has been constructed in frv_packet .


<s> bool SITargetLowering :: isFMAFasterThanFMulAndFAdd ( EVT VT ) const { VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f32 : return false ; case MVT :: f64 : return true ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> MVT WebAssemblyTargetLowering :: getPointerTy ( const DataLayout & DL , uint32_t AS ) const { if ( AS == WebAssembly :: WasmAddressSpace :: WASM_ADDRESS_SPACE_EXTERNREF ) return MVT :: externref ; if ( AS == WebAssembly :: WasmAddressSpace :: WASM_ADDRESS_SPACE_FUNCREF ) return MVT :: funcref ; return TargetLowering :: getPointerTy ( DL , AS ) ; } </s>

Return the pointer type for the given address space , defaults to the pointer type from the data layout .

WebAssembly WebAssembly WebAssembly::WasmAddressSpace MVT::externref WebAssembly::WasmAddressSpace MVT::funcref


<s> static rtx frv_expand_set_builtin ( enum insn_code icode , tree call , rtx target ) { rtx pat ; rtx op0 = frv_read_argument ( call , 0 ) ; if ( ! frv_check_constant_argument ( icode , 1 , op0 ) ) return NULL_RTX ; target = frv_legitimize_target ( icode , target ) ; pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return target ; } </s>

Expand builtins that take a single , constant argument . At the moment , only MHDSETS falls into this category .


<s> static void mips_block_move_loop ( rtx dest , rtx src , HOST_WIDE_INT length ) { rtx label , src_reg , dest_reg , final_src ; HOST_WIDE_INT leftover ; leftover = length % MAX_MOVE_BYTES ; length -= leftover ; mips_adjust_block_mem ( src , MAX_MOVE_BYTES , & src_reg , & src ) ; mips_adjust_block_mem ( dest , MAX_MOVE_BYTES , & dest_reg , & dest ) ; final_src = expand_simple_binop ( Pmode , PLUS , src_reg , GEN_INT ( length ) , 0 , 0 , OPTAB_WIDEN ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; mips_block_move_straight ( dest , src , MAX_MOVE_BYTES ) ; emit_move_insn ( src_reg , plus_constant ( src_reg , MAX_MOVE_BYTES ) ) ; emit_move_insn ( dest_reg , plus_constant ( dest_reg , MAX_MOVE_BYTES ) ) ; if ( Pmode == DImode ) emit_insn ( gen_cmpdi ( src_reg , final_src ) ) ; else emit_insn ( gen_cmpsi ( src_reg , final_src ) ) ; emit_jump_insn ( gen_bne ( label ) ) ; if ( leftover ) mips_block_move_straight ( dest , src , leftover ) ; } </s>

Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES per iteration . LENGTH must be at least MAX_MOVE_BYTES . Assume that the memory regions do not overlap .


<s> bool X86DAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 , Op2 , Op3 , Op4 ; switch ( ConstraintCode ) { case 'o' : case 'v' : default : return true ; case 'm' : if ( ! SelectAddr ( 0 , Op , Op0 , Op1 , Op2 , Op3 , Op4 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; OutOps . push_back ( Op2 ) ; OutOps . push_back ( Op3 ) ; OutOps . push_back ( Op4 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> static tree sparc_gimplify_va_arg ( tree valist , tree type , gimple_seq * pre_p , gimple_seq * post_p ) { HOST_WIDE_INT size , rsize , align ; tree addr , incr ; bool indirect ; tree ptrtype = build_pointer_type ( type ) ; if ( pass_by_reference ( NULL , TYPE_MODE ( type ) , type , false ) ) { indirect = true ; size = rsize = UNITS_PER_WORD ; align = 0 ; } else { indirect = false ; size = int_size_in_bytes ( type ) ; rsize = ( size + UNITS_PER_WORD - 1 ) & - UNITS_PER_WORD ; align = 0 ; if ( TARGET_ARCH64 ) { if ( TYPE_ALIGN ( type ) >= 2 * ( unsigned ) BITS_PER_WORD ) align = 2 * UNITS_PER_WORD ; if ( AGGREGATE_TYPE_P ( type ) ) { if ( size == 0 ) size = rsize = UNITS_PER_WORD ; else size = rsize ; } } } incr = valist ; if ( align ) { incr = fold_build_pointer_plus_hwi ( incr , align - 1 ) ; incr = fold_convert ( sizetype , incr ) ; incr = fold_build2 ( BIT_AND_EXPR , sizetype , incr , size_int ( - align ) ) ; incr = fold_convert ( ptr_type_node , incr ) ; } gimplify_expr ( & incr , pre_p , post_p , is_gimple_val , fb_rvalue ) ; addr = incr ; if ( BYTES_BIG_ENDIAN && size < rsize ) addr = fold_build_pointer_plus_hwi ( incr , rsize - size ) ; if ( indirect ) { addr = fold_convert ( build_pointer_type ( ptrtype ) , addr ) ; addr = build_va_arg_indirect_ref ( addr ) ; } else if ( align == 0 && TYPE_ALIGN ( type ) > BITS_PER_WORD ) { tree tmp = create_tmp_var ( type , "va_arg_tmp" ) ; tree dest_addr = build_fold_addr_expr ( tmp ) ; tree copy = build_call_expr ( builtin_decl_implicit ( BUILT_IN_MEMCPY ) , 3 , dest_addr , addr , size_int ( rsize ) ) ; TREE_ADDRESSABLE ( tmp ) = 1 ; gimplify_and_add ( copy , pre_p ) ; addr = dest_addr ; } else addr = fold_convert ( ptrtype , addr ) ; incr = fold_build_pointer_plus_hwi ( incr , rsize ) ; gimplify_assign ( valist , incr , post_p ) ; return build_va_arg_indirect_ref ( addr ) ; } </s>


<s> void emitFill ( const MCExpr & NumBytes , uint64_t FillValue , SMLoc Loc ) override { EmitMappingSymbol ( "$d" ) ; MCObjectStreamer :: emitFill ( NumBytes , FillValue , Loc ) ; } </s>

Emit Size bytes worth of the value specified by FillValue .


"FP elimination on a non-leaf function is not supported"

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> void SITargetLowering :: computeKnownBitsForTargetInstr ( GISelKnownBits & KB , Register R , KnownBits & Known , const APInt & DemandedElts , const MachineRegisterInfo & MRI , unsigned Depth ) const { const MachineInstr * MI = MRI . getVRegDef ( R ) ; switch ( MI -> getOpcode ( ) ) { case AMDGPU :: G_INTRINSIC : { switch ( MI -> getIntrinsicID ( ) ) { case Intrinsic :: amdgcn_workitem_id_x : knownBitsForWorkitemID ( * getSubtarget ( ) , KB , Known , 0 ) ; break ; case Intrinsic :: amdgcn_workitem_id_y : knownBitsForWorkitemID ( * getSubtarget ( ) , KB , Known , 1 ) ; break ; case Intrinsic :: amdgcn_workitem_id_z : knownBitsForWorkitemID ( * getSubtarget ( ) , KB , Known , 2 ) ; break ; case Intrinsic :: amdgcn_mbcnt_lo : case Intrinsic :: amdgcn_mbcnt_hi : { unsigned Size = MRI . getType ( R ) . getSizeInBits ( ) ; Known . Zero . setHighBits ( Size - getSubtarget ( ) -> getWavefrontSizeLog2 ( ) ) ; break ; } case Intrinsic :: amdgcn_groupstaticsize : { Known . Zero . setHighBits ( countLeadingZeros ( getSubtarget ( ) -> getLocalMemorySize ( ) ) ) ; break ; } } break ; } case AMDGPU :: G_AMDGPU_BUFFER_LOAD_UBYTE : Known . Zero . setHighBits ( 24 ) ; break ; case AMDGPU :: G_AMDGPU_BUFFER_LOAD_USHORT : Known . Zero . setHighBits ( 16 ) ; break ; } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> int nds32_adjust_insn_length ( rtx_insn * insn , int length ) { int adjust_value = 0 ; switch ( recog_memoized ( insn ) ) { case CODE_FOR_call_internal : case CODE_FOR_call_value_internal : { if ( NDS32_ALIGN_P ( ) ) { rtx_insn * next_insn = next_active_insn ( insn ) ; if ( next_insn && get_attr_length ( next_insn ) != 2 ) adjust_value += 2 ; } if ( find_reg_note ( insn , REG_NORETURN , NULL_RTX ) ) { if ( TARGET_16_BIT ) adjust_value += 2 ; else adjust_value += 4 ; } } return length + adjust_value ; default : return length ; } } </s>

Computing the Length of an Insn . Modifies the length assigned to instruction INSN . LEN is the initially computed length of the insn .


<s> SMLoc getStartLoc ( ) const { return Start ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> bool sh_legitimate_index_p ( machine_mode mode , rtx op , bool consider_sh2a , bool allow_zero ) { if ( ! CONST_INT_P ( op ) ) return false ; if ( TARGET_SHMEDIA ) { int size ; if ( mode == VOIDmode ) return satisfies_constraint_I06 ( op ) ; size = GET_MODE_SIZE ( mode ) ; return ( ! ( INTVAL ( op ) & ( size - 1 ) ) && INTVAL ( op ) >= - 512 * size && INTVAL ( op ) < 512 * size ) ; } else { const HOST_WIDE_INT offset = INTVAL ( op ) ; const int max_disp = sh_max_mov_insn_displacement ( mode , consider_sh2a ) ; const int align_mask = mov_insn_alignment_mask ( mode , consider_sh2a ) ; if ( ! allow_zero && max_disp < 1 ) return false ; return offset >= 0 && offset <= max_disp && ( offset & align_mask ) == 0 ; } } </s>

Return TRUE for a valid displacement for the REG+disp addressing with MODE .


<s> void R600PassConfig :: addPreSched2 ( ) { addPass ( createR600EmitClauseMarkers ( ) , false ) ; if ( EnableR600IfConvert ) addPass ( & IfConverterID , false ) ; addPass ( createR600ClauseMergePass ( * TM ) , false ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> const TargetRegisterClass * X86RegisterInfo :: getSubClassWithSubReg ( const TargetRegisterClass * RC , unsigned Idx ) const { if ( ! Is64Bit && Idx == X86 :: sub_8bit ) Idx = X86 :: sub_8bit_hi ; return X86GenRegisterInfo :: getSubClassWithSubReg ( RC , Idx ) ; } </s>

Returns the largest legal sub-class of RC that supports the sub-register index Idx .


<s> unsigned SIRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; const SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; unsigned Occupancy = ST . getOccupancyWithLocalMemSize ( MFI -> getLDSSize ( ) , MF . getFunction ( ) ) ; switch ( RC -> getID ( ) ) { default : return AMDGPURegisterInfo :: getRegPressureLimit ( RC , MF ) ; case AMDGPU :: VGPR_32RegClassID : return std :: min ( ST . getMaxNumVGPRs ( Occupancy ) , ST . getMaxNumVGPRs ( MF ) ) ; case AMDGPU :: SGPR_32RegClassID : return std :: min ( ST . getMaxNumSGPRs ( Occupancy , true ) , ST . getMaxNumSGPRs ( MF ) ) ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .

AMDGPU SI SI SI SI SI AMDGPU AMDGPU::VGPR_32RegClassID AMDGPU::SGPR_32RegClassID


<s> void X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const X86InstrInfo & TII = * TM . getInstrInfo ( ) ; const X86RegisterInfo & RegInfo = * TM . getRegisterInfo ( ) ; unsigned StackPtr = RegInfo . getStackRegister ( ) ; bool reseveCallFrame = hasReservedCallFrame ( MF ) ; int Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; bool IsLP64 = STI . isTarget64BitLP64 ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reseveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t CalleeAmt = isDestroy ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reseveCallFrame ) { if ( Amount == 0 ) return ; unsigned StackAlign = TM . getFrameLowering ( ) -> getStackAlignment ( ) ; Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = nullptr ; if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( IsLP64 , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; Amount -= CalleeAmt ; if ( Amount ) { unsigned Opc = getADDriOpcode ( IsLP64 , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } return ; } if ( Opcode == TII . getCallFrameDestroyOpcode ( ) && CalleeAmt ) { unsigned Opc = getSUBriOpcode ( IsLP64 , CalleeAmt ) ; MachineInstr * New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! std :: prev ( I ) -> isCall ( ) ) -- I ; MBB . insert ( I , New ) ; } } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static bool mmix_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { if ( aligned_p ) switch ( size ) { case 1 : if ( GET_CODE ( x ) != CONST_INT ) { assemble_integer_with_op ( "\t.byte\t" , x ) ; return true ; } fputs ( "\tBYTE\t" , asm_out_file ) ; mmix_print_operand ( asm_out_file , x , 'B' ) ; fputc ( '\n' , asm_out_file ) ; return true ; case 2 : if ( GET_CODE ( x ) != CONST_INT ) { aligned_p = 0 ; break ; } fputs ( "\tWYDE\t" , asm_out_file ) ; mmix_print_operand ( asm_out_file , x , 'W' ) ; fputc ( '\n' , asm_out_file ) ; return true ; case 4 : if ( GET_CODE ( x ) != CONST_INT ) { aligned_p = 0 ; break ; } fputs ( "\tTETRA\t" , asm_out_file ) ; mmix_print_operand ( asm_out_file , x , 'L' ) ; fputc ( '\n' , asm_out_file ) ; return true ; case 8 : gcc_assert ( GET_CODE ( x ) != CONST_DOUBLE ) ; assemble_integer_with_op ( "\tOCTA\t" , x ) ; return true ; } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . Use mmix_print_operand for WYDE and TETRA . Use mmix_output_octa to output 8-byte CONST_DOUBLEs .


<s> unsigned Mips16InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> unsigned PPCRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; const unsigned DefaultSafety = 1 ; switch ( RC -> getID ( ) ) { default : return 0 ; case PPC :: G8RC_NOX0RegClassID : case PPC :: GPRC_NOR0RegClassID : case PPC :: G8RCRegClassID : case PPC :: GPRCRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 32 - FP - DefaultSafety ; } case PPC :: F8RCRegClassID : case PPC :: F4RCRegClassID : case PPC :: VRRCRegClassID : case PPC :: VFRCRegClassID : case PPC :: VSLRCRegClassID : case PPC :: VSHRCRegClassID : return 32 - DefaultSafety ; case PPC :: VSRCRegClassID : case PPC :: VSFRCRegClassID : return 64 - DefaultSafety ; case PPC :: CRRCRegClassID : return 8 - DefaultSafety ; } } </s>


<s> unsigned PIC16InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == PIC16 :: movwf && MI -> getOperand ( 0 ) . isReg ( ) && MI -> getOperand ( 1 ) . isSymbol ( ) ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s>
static
void
avr_option_override
(
void
)
{
flag_delete_null_pointer_checks
=
0
;
if
(
avr_strict_X
)
flag_caller_saves
=
0
;
if
(
(
flag_unwind_tables
||
flag_non_call_exceptions
||
flag_asynchronous_unwind_tables
)
&&
!
ACCUMULATE_OUTGOING_ARGS
)
{
flag_omit_frame_pointer
=
0
;
}
if
(
flag_pic
==
1
)
warning
(
OPT_fpic
,
"-fpic is not supported"
)
;
if
(
flag_pic
==
2
)
warning
(
OPT_fPIC
,
"-fPIC is not supported"
)
;
if
(
flag_pie
==
1
)
warning
(
OPT_fpie
,
"-fpie is not supported"
)
;
if
(
flag_pie
==
2
)
warning
(
OPT_fPIE
,
"-fPIE is not supported"
)
;
if
(
!
avr_set_core_architecture
(
)
)
return
;
avr_addr
.
sreg
=
0x3F
+
avr_arch
->
sfr_offset
;
avr_addr
.
rampz
=
0x3B
+
avr_arch
->
sfr_offset
;
avr_addr
.
rampy
=
0x3A
+
avr_arch
->
sfr_offset
;
avr_addr
.
rampx
=
0x39
+
avr_arch
->
sfr_offset
;
avr_addr
.
rampd
=
0x38
+
avr_arch
->
sfr_offset
;
avr_addr
.
ccp
=
(
AVR_TINY
0x3C
:
0x34
)
+
avr_arch
->
sfr_offset
;
avr_addr
.
sp_l
=
0x3D
+
avr_arch
->
sfr_offset
;
avr_addr
.
sp_h
=
avr_addr
.
sp_l
+
1
;
init_machine_status
=
avr_init_machine_status
;
avr_log_set_avr_log
(
)
;
avr_register_passes
(
)
;
}
</s>


<s> DecodeStatus MipsDisassembler :: getInstruction ( MCInst & instr , uint64_t & Size , const MemoryObject & Region , uint64_t Address , raw_ostream & vStream , raw_ostream & cStream ) const { uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Region , Address , Size , Insn , isBigEndian , IsMicroMips ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( IsMicroMips ) { Result = decodeInstruction ( DecoderTableMicroMips32 , instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } Result = decodeInstruction ( DecoderTableMips32 , instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s> bool WebAssemblyTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { switch ( Intrinsic ) { case Intrinsic :: wasm_atomic_notify : Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: i32 ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . align = Align ( 4 ) ; Info . flags = MachineMemOperand :: MOVolatile | MachineMemOperand :: MOLoad ; return true ; case Intrinsic :: wasm_atomic_wait_i32 : Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: i32 ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . align = Align ( 4 ) ; Info . flags = MachineMemOperand :: MOVolatile | MachineMemOperand :: MOLoad ; return true ; case Intrinsic :: wasm_atomic_wait_i64 : Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: i64 ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . align = Align ( 8 ) ; Info . flags = MachineMemOperand :: MOVolatile | MachineMemOperand :: MOLoad ; return true ; default : return false ; } } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> bool MVEGatherScatterLowering :: runOnFunction ( Function & F ) { if ( ! EnableMaskedGatherScatters ) return false ; auto & TPC = getAnalysis < TargetPassConfig > ( ) ; auto & TM = TPC . getTM < TargetMachine > ( ) ; auto * ST = & TM . getSubtarget < ARMSubtarget > ( F ) ; if ( ! ST -> hasMVEIntegerOps ( ) ) return false ; SmallVector < IntrinsicInst * , 4 > Gathers ; SmallVector < IntrinsicInst * , 4 > Scatters ; for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & I ) ; if ( II && II -> getIntrinsicID ( ) == Intrinsic :: masked_gather ) Gathers . push_back ( II ) ; else if ( II && II -> getIntrinsicID ( ) == Intrinsic :: masked_scatter ) Scatters . push_back ( II ) ; } } bool Changed = false ; for ( IntrinsicInst * I : Gathers ) Changed |= lowerGather ( I ) ; for ( IntrinsicInst * I : Scatters ) Changed |= lowerScatter ( I ) ; return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


Expand cpymem , as if from a __builtin_memcpy . Return true if we succeed , otherwise return false .


<s> static int avr_memory_move_cost ( machine_mode mode , reg_class_t rclass ATTRIBUTE_UNUSED , bool in ATTRIBUTE_UNUSED ) { return ( mode == QImode ? 2 : mode == HImode ? 4 : mode == SImode ? 8 : mode == SFmode ? 8 : 16 ) ; } </s>


<s> BitVector ARMBaseRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( ARM :: SP ) ; Reserved . set ( ARM :: PC ) ; Reserved . set ( ARM :: FPSCR ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( FramePtr ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( BasePtr ) ; if ( STI . isR9Reserved ( ) ) Reserved . set ( ARM :: R9 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .

ARM ARM ARM::SP ARM::PC ARM::FPSCR ARM::R9


"-mcpu must be empty(default:cpu032II), cpu032I or cpu032II"

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


"the ABI of passing aggregates with %d-byte alignment"

If defined , a C expression that gives the alignment boundary , in bits , of an argument with the specified mode and type . If it is not defined , PARM_BOUNDARY is used for all arguments . V.4 wants long longs and doubles to be double word aligned . Just testing the mode size is a boneheaded way to do this as it means that other types such as complex int are also double word aligned . However , we 're stuck with this because changing the ABI might break existing library interfaces . Quadword align Altivec/VSX vectors . Quadword align large synthetic vector types .


<s> const LM32RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { MachineFunctionPass :: getAnalysisUsage ( AU ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < MachineDominanceFrontier > ( ) ; AU . setPreservesAll ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void X86InstructionSelector :: beginFunction ( const MachineFunction & MF ) { OptForSize = MF . getFunction ( ) -> optForSize ( ) ; OptForMinSize = MF . getFunction ( ) -> optForMinSize ( ) ; AvailableFeatures = computeAvailableFeatures ( & MF , & STI ) ; } </s>

Gather pre-function exception information .


"architecture %qs supported for assembler only"

Outputs some appropriate text to go at the start of an assembler file .


<s> inline static rtx emit_set_insn ( rtx x , rtx y ) { return emit_insn ( gen_rtx_SET ( x , y ) ) ; } </s>

Emit an insn that 's a simple single-set . Both the operands must be known to be valid .


<s> void ARMBaseInstrInfo :: buildOutlinedFrame ( MachineBasicBlock & MBB , MachineFunction & MF , const outliner :: OutlinedFunction & OF ) const { if ( OF . FrameConstructionID == MachineOutlinerTailCall ) return ; if ( OF . FrameConstructionID == MachineOutlinerThunk ) { MachineInstr * Call = & * -- MBB . instr_end ( ) ; bool isThumb = Subtarget . isThumb ( ) ; unsigned FuncOp = isThumb ? 2 : 0 ; unsigned Opc = Call -> getOperand ( FuncOp ) . isReg ( ) ? isThumb ? ARM :: tTAILJMPr : ARM :: TAILJMPr : isThumb ? Subtarget . isTargetMachO ( ) ? ARM :: tTAILJMPd : ARM :: tTAILJMPdND : ARM :: TAILJMPd ; MachineInstrBuilder MIB = BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Opc ) ) . add ( Call -> getOperand ( FuncOp ) ) ; if ( isThumb && ! Call -> getOperand ( FuncOp ) . isReg ( ) ) MIB . add ( predOps ( ARMCC :: AL ) ) ; Call -> eraseFromParent ( ) ; return ; } BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Subtarget . getReturnOpcode ( ) ) ) . add ( predOps ( ARMCC :: AL ) ) ; } </s>

Insert a custom frame for outlined functions .

ARM ARM 2 0 ARM::tTAILJMPr ARM::TAILJMPr ARM::tTAILJMPd ARM::tTAILJMPdND ARM::TAILJMPd ARMCC::AL ARMCC::AL


<s> bool TPCInstrInfo :: isPredicated ( const MachineInstr & MI ) const { if ( MI . getOpcode ( ) == TPC :: JMPR ) { return true ; } const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( MCID . getNumOperands ( ) > 1 ) { const MachineOperand & PossiblePred = MI . getOperand ( MCID . getNumOperands ( ) - 2 ) ; const MachineOperand & PossiblePol = MI . getOperand ( MCID . getNumOperands ( ) - 1 ) ; if ( ! PossiblePol . isImm ( ) || ! PossiblePred . isReg ( ) ) return false ; Register PReg = PossiblePred . getReg ( ) ; if ( PReg == TPC :: SP0 || PReg == TPC :: VP0 ) return false ; const TargetRegisterClass * RC ; if ( PReg . isPhysical ( ) ) { RC = getClassOfPhysicalRegister ( PReg , RI ) ; } else { const MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; RC = MRI . getRegClass ( PReg ) ; } return TPC :: SPRFRegClass . hasSubClassEq ( RC ) || TPC :: VPRFRegClass . hasSubClassEq ( RC ) ; } return false ; } </s>

Returns true if the instruction is already predicated .


<s> tree d30v_build_va_list ( ) { tree f_arg_ptr , f_arg_num , record , type_decl ; tree int_type_node ; record = make_lang_type ( RECORD_TYPE ) ; type_decl = build_decl ( TYPE_DECL , get_identifier ( "__va_list_tag" ) , record ) ; int_type_node = make_signed_type ( INT_TYPE_SIZE ) ; f_arg_ptr = build_decl ( FIELD_DECL , get_identifier ( "__va_arg_ptr" ) , ptr_type_node ) ; f_arg_num = build_decl ( FIELD_DECL , get_identifier ( "__va_arg_num" ) , int_type_node ) ; DECL_FIELD_CONTEXT ( f_arg_ptr ) = record ; DECL_FIELD_CONTEXT ( f_arg_num ) = record ; TREE_CHAIN ( record ) = type_decl ; TYPE_NAME ( record ) = type_decl ; TYPE_FIELDS ( record ) = f_arg_ptr ; TREE_CHAIN ( f_arg_ptr ) = f_arg_num ; layout_type ( record ) ; return build_array_type ( record , build_index_type ( size_zero_node ) ) ; } </s>


<s> bool aarch_mm_needs_acquire ( rtx const_int ) { enum memmodel model = memmodel_from_int ( INTVAL ( const_int ) ) ; return ! ( is_mm_relaxed ( model ) || is_mm_consume ( model ) || is_mm_release ( model ) ) ; } </s>

Return non-zero if the RTX representing a memory model is a memory model that needs acquire semantics .


<s> void X86InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Alignment = std :: max < uint32_t > ( RC -> getSize ( ) , 16 ) ; bool isAligned = ( MF . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , Subtarget ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) , DestReg ) , FrameIdx ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> static bool vectorize_vec_perm_const_1 ( const struct expand_vec_perm_d & d ) { if ( expand_perm_with_merge ( d ) ) return true ; if ( expand_perm_with_vster ( d ) ) return true ; if ( expand_perm_with_vstbrq ( d ) ) return true ; if ( expand_perm_with_vpdi ( d ) ) return true ; if ( expand_perm_with_rot ( d ) ) return true ; return false ; } </s>

Try to find the best sequence for the vector permute operation described by D. Return true if the operation could be expanded .


<s> static bool match_auli_pcrel ( rtx_insn * insn ) { rtx pattern = PATTERN ( insn ) ; rtx high ; rtx unspec ; if ( GET_CODE ( pattern ) != SET ) return false ; if ( GET_CODE ( SET_SRC ( pattern ) ) != PLUS ) return false ; high = XEXP ( SET_SRC ( pattern ) , 1 ) ; if ( GET_CODE ( high ) != HIGH || GET_CODE ( XEXP ( high , 0 ) ) != CONST ) return false ; unspec = XEXP ( XEXP ( high , 0 ) , 0 ) ; return ( GET_CODE ( unspec ) == UNSPEC && XINT ( unspec , 1 ) == UNSPEC_PCREL_SYM ) ; } </s>

Returns whether INSN is a pc-relative auli insn .


"Not expecting modifiers with immediates"

This method commutes the operands of the given machine instruction MI .


<s> rtx spu_const ( machine_mode mode , HOST_WIDE_INT val ) { rtx inner ; rtvec v ; int units , i ; gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_INT || GET_MODE_CLASS ( mode ) == MODE_FLOAT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT ) ; if ( GET_MODE_CLASS ( mode ) == MODE_INT ) return immed_double_const ( val , 0 , mode ) ; if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return hwint_to_const_double ( mode , val ) ; if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) inner = immed_double_const ( val , 0 , GET_MODE_INNER ( mode ) ) ; else inner = hwint_to_const_double ( GET_MODE_INNER ( mode ) , val ) ; units = GET_MODE_NUNITS ( mode ) ; v = rtvec_alloc ( units ) ; for ( i = 0 ; i < units ; ++ i ) RTVEC_ELT ( v , i ) = inner ; return gen_rtx_CONST_VECTOR ( mode , v ) ; } </s>

Given VAL , generate a constant appropriate for MODE . If MODE is a vector mode , every element will be VAL . For TImode , VAL will be zero extended to 128 bits .


<s> unsigned TeakInstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL , int * BytesAdded ) const { unsigned NumInserted = 0 ; if ( BytesAdded ) * BytesAdded = 0 ; if ( Cond . size ( ) > 0 ) { const MachineInstrBuilder & builder = BuildMI ( MBB , MBB . end ( ) , DL , get ( Teak :: BRRCond_rel7 ) ) ; builder . addMBB ( TBB ) . add ( Cond [ 0 ] ) ; NumInserted ++ ; if ( BytesAdded ) * BytesAdded += 1 ; } if ( Cond . empty ( ) || FBB ) { BuildMI ( MBB , MBB . end ( ) , DL , get ( Teak :: BRR_rel7 ) ) . addMBB ( Cond . empty ( ) ? TBB : FBB ) ; NumInserted ++ ; if ( BytesAdded ) * BytesAdded += 1 ; } return NumInserted ; } </s>

Insert branch code into the end of the specified MachineBasicBlock .


<s> int call_operand ( rtx op , enum machine_mode mode ) { if ( GET_CODE ( op ) != MEM ) return 0 ; op = XEXP ( op , 0 ) ; return call_address_operand ( op , mode ) ; } </s>

Call insn on SPARC can take a PC-relative constant address , or any regular memory address .


<s>
void
rs6000_aix_asm_output_dwarf_table_ref
(
char
*
frame_table_label
)
{
fprintf
(
asm_out_file
,
"\t.ref %s\n"
,
(
*
targetm
.
strip_name_encoding
)
(
frame_table_label
)
)
;
}
</s>

Issue assembly directives that create a reference to the given DWARF FRAME_TABLE_LABEL from the current function section .


<s>
void
WebAssemblyPassConfig
::
addOptimizedRegAlloc
(
FunctionPass
*
RegAllocPass
)
{
assert
(
!
RegAllocPass
&&
"WebAssembly uses no regalloc!"
)
;
addRegAllocPasses
(
true
)
;
}
</s>

addOptimizedRegAlloc - Add passes related to register allocation .

WebAssembly
WebAssembly
"WebAssembly uses no regalloc!"


<s> static bool nios2_fpu_compare_enabled ( enum rtx_code cond , machine_mode mode ) { if ( mode == SFmode ) switch ( cond ) { case EQ : return N2FPU_OP_ENABLED_P ( fcmpeqs ) ; case NE : return N2FPU_OP_ENABLED_P ( fcmpnes ) ; case GT : return N2FPU_OP_ENABLED_P ( fcmpgts ) ; case GE : return N2FPU_OP_ENABLED_P ( fcmpges ) ; case LT : return N2FPU_OP_ENABLED_P ( fcmplts ) ; case LE : return N2FPU_OP_ENABLED_P ( fcmples ) ; default : break ; } else if ( mode == DFmode ) switch ( cond ) { case EQ : return N2FPU_OP_ENABLED_P ( fcmpeqd ) ; case NE : return N2FPU_OP_ENABLED_P ( fcmpned ) ; case GT : return N2FPU_OP_ENABLED_P ( fcmpgtd ) ; case GE : return N2FPU_OP_ENABLED_P ( fcmpged ) ; case LT : return N2FPU_OP_ENABLED_P ( fcmpltd ) ; case LE : return N2FPU_OP_ENABLED_P ( fcmpled ) ; default : break ; } return false ; } </s>

Return true if COND comparison for mode MODE is enabled under current settings .


<s> SMLoc getLoc ( ) const { return getParser ( ) . getTok ( ) . getLoc ( ) ; } </s>

Get the source location of the point where the field was defined .


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT ) const override { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .