<s> bool SITargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Align , bool * IsFast ) const { if ( IsFast ) * IsFast = false ; if ( VT == MVT :: Other || ( VT != MVT :: Other && VT . getSizeInBits ( ) > 1024 && VT . getStoreSize ( ) > 16 ) ) { return false ; } if ( AddrSpace == AMDGPUASI . LOCAL_ADDRESS || AddrSpace == AMDGPUASI . REGION_ADDRESS ) { bool AlignedBy4 = ( Align % 4 == 0 ) ; if ( IsFast ) * IsFast = AlignedBy4 ; return AlignedBy4 ; } if ( ! Subtarget -> hasUnalignedScratchAccess ( ) && ( AddrSpace == AMDGPUASI . PRIVATE_ADDRESS || AddrSpace == AMDGPUASI . FLAT_ADDRESS ) ) { return false ; } if ( Subtarget -> hasUnalignedBufferAccess ( ) ) { if ( IsFast ) { * IsFast = ( AddrSpace == AMDGPUASI . CONSTANT_ADDRESS || AddrSpace == AMDGPUASI . CONSTANT_ADDRESS_32BIT ) ? ( Align % 4 == 0 ) : true ; } return true ; } if ( VT . bitsLT ( MVT :: i32 ) ) return false ; if ( IsFast ) * IsFast = true ; return VT . bitsGT ( MVT :: i32 ) && Align % 4 == 0 ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> const char * mips_output_probe_stack_range ( rtx reg1 , rtx reg2 ) { static int labelno = 0 ; char loop_lab [ 32 ] , end_lab [ 32 ] , tmp [ 64 ] ; rtx xops [ 2 ] ; ASM_GENERATE_INTERNAL_LABEL ( loop_lab , "LPSRL" , labelno ) ; ASM_GENERATE_INTERNAL_LABEL ( end_lab , "LPSRE" , labelno ++ ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , loop_lab ) ; xops [ 0 ] = reg1 ; xops [ 1 ] = reg2 ; strcpy ( tmp , "%(%<beq\t%0,%1," ) ; output_asm_insn ( strcat ( tmp , & end_lab [ 1 ] ) , xops ) ; xops [ 1 ] = GEN_INT ( - PROBE_INTERVAL ) ; if ( TARGET_64BIT && TARGET_LONG64 ) output_asm_insn ( "daddiu\t%0,%0,%1" , xops ) ; else output_asm_insn ( "addiu\t%0,%0,%1" , xops ) ; fprintf ( asm_out_file , "\tb\t" ) ; assemble_name_raw ( asm_out_file , loop_lab ) ; fputc ( '\n' , asm_out_file ) ; if ( TARGET_64BIT ) output_asm_insn ( "sd\t$0,0(%0)%)" , xops ) ; else output_asm_insn ( "sw\t$0,0(%0)%)" , xops ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , end_lab ) ; return "" ; } </s>

Probe a range of stack addresses from REG1 to REG2 inclusive . These are absolute addresses .


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & ) const override { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> static void cris_output_addr_const ( FILE * file , rtx x ) { in_code ++ ; output_addr_const ( file , x ) ; in_code -- ; } </s>

Use from within code , from e.g . PRINT_OPERAND and PRINT_OPERAND_ADDRESS . Macros used in output_addr_const need to emit different things depending on whether code operand or constant is emitted .


<s> bool X86InstrInfo :: isHighLatencyDef ( int opc ) const { switch ( opc ) { default : return false ; case X86 :: DIVSDrm : case X86 :: DIVSDrm_Int : case X86 :: DIVSDrr : case X86 :: DIVSDrr_Int : case X86 :: DIVSSrm : case X86 :: DIVSSrm_Int : case X86 :: DIVSSrr : case X86 :: DIVSSrr_Int : case X86 :: SQRTPDm : case X86 :: SQRTPDr : case X86 :: SQRTPSm : case X86 :: SQRTPSr : case X86 :: SQRTSDm : case X86 :: SQRTSDm_Int : case X86 :: SQRTSDr : case X86 :: SQRTSDr_Int : case X86 :: SQRTSSm : case X86 :: SQRTSSm_Int : case X86 :: SQRTSSr : case X86 :: SQRTSSr_Int : case X86 :: VDIVSDrm : case X86 :: VDIVSDrm_Int : case X86 :: VDIVSDrr : case X86 :: VDIVSDrr_Int : case X86 :: VDIVSSrm : case X86 :: VDIVSSrm_Int : case X86 :: VDIVSSrr : case X86 :: VDIVSSrr_Int : case X86 :: VSQRTPDm : case X86 :: VSQRTPDr : case X86 :: VSQRTPSm : case X86 :: VSQRTPSr : case X86 :: VSQRTSDm : case X86 :: VSQRTSDm_Int : case X86 :: VSQRTSDr : case X86 :: VSQRTSSm : case X86 :: VSQRTSSm_Int : case X86 :: VSQRTSSr : case X86 :: VSQRTPDZm : case X86 :: VSQRTPDZr : case X86 :: VSQRTPSZm : case X86 :: VSQRTPSZr : case X86 :: VSQRTSDZm : case X86 :: VSQRTSDZm_Int : case X86 :: VSQRTSDZr : case X86 :: VSQRTSSZm_Int : case X86 :: VSQRTSSZr : case X86 :: VSQRTSSZm : case X86 :: VDIVSDZrm : case X86 :: VDIVSDZrr : case X86 :: VDIVSSZrm : case X86 :: VDIVSSZrr : case X86 :: VGATHERQPSZrm : case X86 :: VGATHERQPDZrm : case X86 :: VGATHERDPDZrm : case X86 :: VGATHERDPSZrm : case X86 :: VPGATHERQDZrm : case X86 :: VPGATHERQQZrm : case X86 :: VPGATHERDDZrm : case X86 :: VPGATHERDQZrm : case X86 :: VSCATTERQPDZmr : case X86 :: VSCATTERQPSZmr : case X86 :: VSCATTERDPDZmr : case X86 :: VSCATTERDPSZmr : case X86 :: VPSCATTERQDZmr : case X86 :: VPSCATTERQQZmr : case X86 :: VPSCATTERDDZmr : case X86 :: VPSCATTERDQZmr : return true ; } } </s>

Return true if this opcode has high latency to its result .


<s> static int arc_compute_millicode_save_restore_regs ( uint64_t gmask , struct arc_frame_info * frame ) { int regno ; int start_reg = 13 , end_reg = 25 ; for ( regno = start_reg ; regno <= end_reg && ( gmask & ( 1ULL << regno ) ) ; ) regno ++ ; end_reg = regno - 1 ; if ( regno - start_reg >= 3 - ( crtl -> is_leaf == 0 ) ) { frame -> millicode_start_reg = 13 ; frame -> millicode_end_reg = regno - 1 ; return 1 ; } return 0 ; } </s>

Return non-zero if there are registers to be saved or loaded using millicode thunks . We can only use consecutive sequences starting with r13 , and not going beyond r25 . GMASK is a bitmask of registers to save . This function sets FRAME- > millicod_start_reg .. FRAME- > millicode_end_reg to the range of registers to be saved / restored with a millicode call .


<s> bool umips_save_restore_pattern_p ( bool save_p , rtx pattern ) { int n ; unsigned int i ; HOST_WIDE_INT first_offset = 0 ; rtx first_base = 0 ; unsigned int regmask = 0 ; for ( n = 0 ; n < XVECLEN ( pattern , 0 ) ; n ++ ) { rtx set , reg , mem , this_base ; HOST_WIDE_INT this_offset ; set = XVECEXP ( pattern , 0 , n ) ; if ( GET_CODE ( set ) != SET ) return false ; mem = save_p ? SET_DEST ( set ) : SET_SRC ( set ) ; if ( ! MEM_P ( mem ) || MEM_VOLATILE_P ( mem ) ) return false ; mips_split_plus ( XEXP ( mem , 0 ) , & this_base , & this_offset ) ; if ( ! REG_P ( this_base ) ) return false ; if ( n == 0 ) { if ( ! UMIPS_12BIT_OFFSET_P ( this_offset ) ) return false ; first_base = this_base ; first_offset = this_offset ; } else { if ( REGNO ( this_base ) != REGNO ( first_base ) || this_offset != first_offset + UNITS_PER_WORD * n ) return false ; } reg = save_p ? SET_SRC ( set ) : SET_DEST ( set ) ; if ( ! REG_P ( reg ) ) return false ; regmask |= 1 << REGNO ( reg ) ; } for ( i = 0 ; i < ARRAY_SIZE ( umips_swm_mask ) ; i ++ ) if ( regmask == umips_swm_mask [ i ] ) return true ; return false ; } </s>

Return true if PATTERN matches the kind of instruction generated by umips_build_save_restore . SAVE_P is true for store .


<s>
void
SIMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
uint64_t
Encoding
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
unsigned
bytes
=
Desc
.
getSize
(
)
;
for
(
unsigned
i
=
0
;
i
<
bytes
;
i
++
)
{
OS
.
write
(
(
uint8_t
)
(
(
Encoding
>>
(
8
*
i
)
)
&
0xff
)
)
;
}
if
(
bytes
>
4
)
return
;
for
(
unsigned
i
=
0
,
e
=
MI
.
getNumOperands
(
)
;
i
<
e
;
++
i
)
{
if
(
!
isSrcOperand
(
Desc
,
i
)
)
continue
;
int
RCID
=
Desc
.
OpInfo
[
i
]
.
RegClass
;
const
MCRegisterClass
&
RC
=
MRI
.
getRegClass
(
RCID
)
;
const
MCOperand
&
Op
=
MI
.
getOperand
(
i
)
;
if
(
getLitEncoding
(
Op
,
RC
.
getSize
(
)
)
!=
255
)
continue
;
int64_t
Imm
=
0
;
if
(
Op
.
isImm
(
)
)
Imm
=
Op
.
getImm
(
)
;
else
if
(
!
Op
.
isExpr
(
)
)
llvm_unreachable
(
"Must be immediate or expr"
)
;
for
(
unsigned
j
=
0
;
j
<
4
;
j
++
)
{
OS
.
write
(
(
uint8_t
)
(
(
Imm
>>
(
8
*
j
)
)
&
0xff
)
)
;
}
break
;
}
}
</s>

Encode the given Inst to bytes and append to CB .


<s> TargetLoweringBase :: LegalizeTypeAction HexagonTargetLowering :: getPreferredVectorAction ( MVT VT ) const { if ( VT . getVectorNumElements ( ) == 1 ) return TargetLoweringBase :: TypeScalarizeVector ; MVT ElemTy = VT . getVectorElementType ( ) ; if ( ElemTy == MVT :: i1 ) return TargetLoweringBase :: TypeWidenVector ; if ( Subtarget . useHVXOps ( ) ) { ArrayRef < MVT > Tys = Subtarget . getHVXElementTypes ( ) ; if ( llvm :: find ( Tys , ElemTy ) != Tys . end ( ) ) { unsigned HwWidth = 8 * Subtarget . getVectorLength ( ) ; unsigned VecWidth = VT . getSizeInBits ( ) ; if ( VecWidth >= HwWidth / 2 && VecWidth < HwWidth ) return TargetLoweringBase :: TypeWidenVector ; } } return TargetLoweringBase :: TypeSplitVector ; } </s>

Customize the preferred legalization strategy for certain types .


<s> int h8300_shift_needs_scratch_p ( int count , machine_mode mode , enum rtx_code type ) { enum h8_cpu cpu ; int a , lr , ar ; if ( GET_MODE_BITSIZE ( mode ) <= count ) return 1 ; if ( TARGET_H8300S ) cpu = H8_S ; else cpu = H8_300H ; switch ( mode ) { case E_QImode : a = shift_alg_qi [ cpu ] [ SHIFT_ASHIFT ] [ count ] ; lr = shift_alg_qi [ cpu ] [ SHIFT_LSHIFTRT ] [ count ] ; ar = shift_alg_qi [ cpu ] [ SHIFT_ASHIFTRT ] [ count ] ; break ; case E_HImode : a = shift_alg_hi [ cpu ] [ SHIFT_ASHIFT ] [ count ] ; lr = shift_alg_hi [ cpu ] [ SHIFT_LSHIFTRT ] [ count ] ; ar = shift_alg_hi [ cpu ] [ SHIFT_ASHIFTRT ] [ count ] ; break ; case E_SImode : a = shift_alg_si [ cpu ] [ SHIFT_ASHIFT ] [ count ] ; lr = shift_alg_si [ cpu ] [ SHIFT_LSHIFTRT ] [ count ] ; ar = shift_alg_si [ cpu ] [ SHIFT_ASHIFTRT ] [ count ] ; break ; default : gcc_unreachable ( ) ; } if ( type == CLOBBER ) return ( a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP || ( TARGET_H8300H && mode == SImode && count == 8 ) ) ; else if ( type == ASHIFT ) return ( a == SHIFT_LOOP || ( TARGET_H8300H && mode == SImode && count == 8 ) ) ; else if ( type == LSHIFTRT ) return ( lr == SHIFT_LOOP || ( TARGET_H8300H && mode == SImode && count == 8 ) ) ; else if ( type == ASHIFTRT ) return ( ar == SHIFT_LOOP || ( TARGET_H8300H && mode == SImode && count == 8 ) ) ; } </s>

Given COUNT and MODE of a shift , return 1 if a scratch reg may be needed for some shift with COUNT and MODE . Return 0 otherwise .


<s> bool SHUXIInstrInfo :: isUnpredicatedTerminator ( const MachineInstr & MI ) const { if ( ! MI . isTerminator ( ) ) return false ; if ( MI . isBranch ( ) && ! MI . isBarrier ( ) ) return true ; if ( ! MI . isPredicable ( ) ) return true ; return ! isPredicated ( MI ) ; } </s>

Returns true if the instruction is a terminator instruction that has not been predicated .


<s> bool Thumb1FrameInfo :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; unsigned CFSize = FFI -> getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( 1 << 8 ) - 1 ) * 4 / 2 ) return false ; return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> unsigned MipsRegisterInfo :: getFrameRegister ( MachineFunction & MF ) const { return hasFP ( MF ) ? Mips :: FP : Mips :: SP ; } </s>


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == 0 ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s> bool aarch64_sve_scalar_inc_dec_immediate_p ( rtx x ) { poly_int64 value ; return ( poly_int_rtx_p ( x , & value ) && ( aarch64_sve_cnt_immediate_p ( value ) || aarch64_sve_cnt_immediate_p ( - value ) ) ) ; } </s>

Return true if we can add X using a single SVE INC or DEC instruction .


"variable %q+D must be const in order to be put into"

Add the section attribute if the variable is in progmem .


<s> void push ( NestingType NT ) { NestingStack . push_back ( NT ) ; } </s>


<s> static void aarch64_pop_regs ( unsigned regno1 , unsigned regno2 , HOST_WIDE_INT adjustment , rtx * cfi_ops ) { machine_mode mode = ( regno1 <= R30_REGNUM ) ? DImode : DFmode ; rtx reg1 = gen_rtx_REG ( mode , regno1 ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg1 , * cfi_ops ) ; if ( regno2 == INVALID_REGNUM ) { rtx mem = plus_constant ( Pmode , stack_pointer_rtx , adjustment ) ; mem = gen_rtx_POST_MODIFY ( Pmode , stack_pointer_rtx , mem ) ; emit_move_insn ( reg1 , gen_rtx_MEM ( mode , mem ) ) ; } else { rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg2 , * cfi_ops ) ; emit_insn ( aarch64_gen_loadwb_pair ( mode , stack_pointer_rtx , reg1 , reg2 , adjustment ) ) ; } } </s>

Pop the two registers numbered REGNO1 , REGNO2 from the stack , adjusting it afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes into CFI_OPS .


<s> void function_expander :: add_mem_operand ( machine_mode mode , rtx addr ) { gcc_assert ( VECTOR_MODE_P ( mode ) || mode == OImode ) ; rtx mem = gen_rtx_MEM ( mode , memory_address ( mode , addr ) ) ; set_mem_align ( mem , GET_MODE_ALIGNMENT ( GET_MODE_INNER ( mode ) ) ) ; add_fixed_operand ( mem ) ; } </s>

Add a memory operand with mode MODE and address ADDR .


initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool MBlazeTargetMachine :: addInstSelector ( PassManagerBase & PM ) { PM . add ( createMBlazeISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static bool spu_vector_mode_supported_p ( machine_mode mode ) { switch ( mode ) { case V16QImode : case V8HImode : case V4SImode : case V2DImode : case V4SFmode : case V2DFmode : return true ; default : return false ; } } </s>

Similarly for vector modes . `` Supported '' here is less strict . At least some operations are supported ; need to check optabs or builtins for further details .


<s> void PatmosSinglePathInfo :: dump ( ) const { print ( dbgs ( ) ) ; } </s>

Dump the plan to stderr ( for debugging ) .


<s> static int mcore_arg_partial_bytes ( cumulative_args_t cum , machine_mode mode , tree type , bool named ) { int reg = ROUND_REG ( * get_cumulative_args ( cum ) , mode ) ; if ( named == 0 ) return 0 ; if ( targetm . calls . must_pass_in_stack ( mode , type ) ) return 0 ; if ( reg >= NPARM_REGS ) return 0 ; if ( reg + mcore_num_arg_regs ( mode , type ) <= NPARM_REGS ) return 0 ; reg = NPARM_REGS - reg ; return reg * UNITS_PER_WORD ; } </s>

Returns the number of bytes of argument registers required to hold * part * of a parameter of machine mode MODE and type TYPE ( which may be NULL if the type is not known ) . If the argument fits entirely in the argument registers , or entirely on the stack , then 0 is returned . CUM is the number of argument registers already used by earlier parameters to the function .


<s> bool FPMover :: runOnMachineFunction ( MachineFunction & F ) { if ( TM . getSubtarget < SparcSubtarget > ( ) . isV9 ( ) ) return false ; bool Changed = false ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> void iq2000_expand_epilogue ( void ) { HOST_WIDE_INT tsize = cfun -> machine -> total_size ; rtx tsize_rtx = GEN_INT ( tsize ) ; rtx tmp_rtx = ( rtx ) 0 ; if ( iq2000_can_use_return_insn ( ) ) { emit_jump_insn ( gen_return ( ) ) ; return ; } if ( tsize > 32767 ) { tmp_rtx = gen_rtx_REG ( Pmode , IQ2000_TEMP1_REGNUM ) ; emit_move_insn ( tmp_rtx , tsize_rtx ) ; tsize_rtx = tmp_rtx ; } if ( tsize > 0 ) { if ( frame_pointer_needed ) { emit_insn ( gen_blockage ( ) ) ; emit_insn ( gen_movsi ( stack_pointer_rtx , hard_frame_pointer_rtx ) ) ; } save_restore_insns ( 0 ) ; if ( current_function_calls_eh_return ) { rtx eh_ofs = EH_RETURN_STACKADJ_RTX ; emit_insn ( gen_addsi3 ( eh_ofs , eh_ofs , tsize_rtx ) ) ; tsize_rtx = eh_ofs ; } emit_insn ( gen_blockage ( ) ) ; if ( tsize != 0 || current_function_calls_eh_return ) { emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , tsize_rtx ) ) ; } } if ( current_function_calls_eh_return ) { emit_move_insn ( gen_rtx_REG ( Pmode , HARD_FRAME_POINTER_REGNUM ) , stack_pointer_rtx ) ; emit_insn ( gen_rtx_USE ( VOIDmode , gen_rtx_REG ( Pmode , HARD_FRAME_POINTER_REGNUM ) ) ) ; emit_jump_insn ( gen_eh_return_internal ( ) ) ; } else emit_jump_insn ( gen_return_internal ( gen_rtx_REG ( Pmode , GP_REG_FIRST + 31 ) ) ) ; } </s>

Expand the epilogue into a bunch of separate insns .


<s> constexpr u16 Index ( ) const { return this -> storage + offset ; } </s>

Index field , for use by the object file implementation .


<s> void microblaze_expand_epilogue ( void ) { HOST_WIDE_INT fsiz = current_frame_info . total_size ; rtx fsiz_rtx = GEN_INT ( fsiz ) ; rtx reg_rtx ; rtx mem_rtx ; if ( microblaze_can_use_return_insn ( ) ) { emit_jump_insn ( gen_return_internal ( gen_rtx_REG ( Pmode , GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM ) ) ) ; return ; } if ( fsiz > 0 ) { if ( ! crtl -> is_leaf || interrupt_handler ) { mem_rtx = gen_rtx_MEM ( SImode , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , const0_rtx ) ) ; if ( interrupt_handler ) MEM_VOLATILE_P ( mem_rtx ) = 1 ; reg_rtx = gen_rtx_REG ( SImode , MB_ABI_SUB_RETURN_ADDR_REGNUM ) ; emit_move_insn ( reg_rtx , mem_rtx ) ; } if ( frame_pointer_needed ) emit_insn ( gen_movsi ( stack_pointer_rtx , hard_frame_pointer_rtx ) ) ; save_restore_insns ( 0 ) ; emit_insn ( gen_blockage ( ) ) ; emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , fsiz_rtx ) ) ; } emit_jump_insn ( gen_return_internal ( gen_rtx_REG ( Pmode , GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM ) ) ) ; } </s>


<s> bool ARCInstrInfo :: getBaseAndOffsetPosition ( const MachineInstr & MI , unsigned & BasePos , unsigned & OffsetPos ) const { if ( ! MI . mayLoad ( ) && ! MI . mayStore ( ) ) return false ; BasePos = 1 ; OffsetPos = 2 ; if ( isPostIncrement ( MI ) || isPreIncrement ( MI ) ) { BasePos ++ ; OffsetPos ++ ; } if ( ! MI . getOperand ( BasePos ) . isReg ( ) || ! MI . getOperand ( OffsetPos ) . isImm ( ) ) return false ; return true ; } </s>

Return true if the instruction contains a base register and offset .


<s> virtual BitVector getReservedRegs ( const MachineFunction & MF ) const { assert ( ! "Unimplemented" ) ; return BitVector ( ) ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> const char * getPassName ( ) const override { return AARCH64_BR_RELAX_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> static bool isLiveOut ( const MachineBasicBlock & MBB , unsigned Reg ) { for ( MachineBasicBlock * Succ : MBB . successors ( ) ) { if ( Succ -> isLiveIn ( Reg ) ) return true ; } return false ; } </s>

isLiveOut - Determine if Reg is live out from MBB , when not considering PHI nodes .


<s> void OR1KAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { customEmitInstruction ( I ++ ) ; } while ( ( I != E ) && I -> isInsideBundle ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
bool
FalkorHWPFFix
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
auto
&
ST
=
static_cast
<
const
AArch64Subtarget
&
>
(
Fn
.
getSubtarget
(
)
)
;
if
(
ST
.
getProcFamily
(
)
!=
AArch64Subtarget
::
Falkor
)
return
false
;
if
(
skipFunction
(
Fn
.
getFunction
(
)
)
)
return
false
;
TII
=
static_cast
<
const
AArch64InstrInfo
*
>
(
ST
.
getInstrInfo
(
)
)
;
TRI
=
ST
.
getRegisterInfo
(
)
;
assert
(
TRI
->
trackLivenessAfterRegAlloc
(
Fn
)
&&
"Register liveness not available!"
)
;
MachineLoopInfo
&
LI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
Modified
=
false
;
for
(
MachineLoop
*
I
:
LI
)
for
(
auto
L
=
df_begin
(
I
)
,
LE
=
df_end
(
I
)
;
L
!=
LE
;
++
L
)
if
(
L
->
empty
(
)
)
runOnLoop
(
*
*
L
,
Fn
)
;
return
Modified
;
}
</s>


<s>
const
char
*
nds32_output_casesi_pc_relative
(
rtx
*
operands
)
{
machine_mode
mode
;
rtx
diff_vec
;
diff_vec
=
PATTERN
(
NEXT_INSN
(
as_a
<
rtx_insn
*
>
(
operands
[
1
]
)
)
)
;
gcc_assert
(
GET_CODE
(
diff_vec
)
==
ADDR_DIFF_VEC
)
;
output_asm_insn
(
"la\t$ta, %l1"
,
operands
)
;
mode
=
GET_MODE
(
diff_vec
)
;
switch
(
mode
)
{
case
E_QImode
:
output_asm_insn
(
"lb\t%2, [$ta + %0 << 0]"
,
operands
)
;
break
;
case
E_HImode
:
output_asm_insn
(
"lh\t%2, [$ta + %0 << 1]"
,
operands
)
;
break
;
case
E_SImode
:
output_asm_insn
(
"lw\t%2, [$ta + %0 << 2]"
,
operands
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
output_asm_insn
(
"add\t$ta, %2, $ta"
,
operands
)
;
if
(
TARGET_16_BIT
)
return
"jr5\t$ta"
;
else
return
"jr\t$ta"
;
}
</s>

Function to generate PC relative jump table . Refer to nds32.md for more details . The following is the sample for the case that diff value can be presented in '.short ' size . addi $ r1 , $ r1 , - ( case_lower_bound ) slti $ ta , $ r1 , ( case_number ) beqz $ ta , .L_skip_label la $ ta , .L35 ! get jump table address lh $ r1 , [ $ ta + $ r1 < < 1 ] ! load symbol diff from jump table entry addi $ ta , $ r1 , $ ta jr5 $ ta ! jump table entry L35 : .short .L25-.L35 .short .L26-.L35 .short .L27-.L35 .short .L28-.L35 .short .L29-.L35 .short .L30-.L35 .short .L31-.L35 .short .L32-.L35 .short .L33-.L35 .short .L34-.L35


<s> static bool c6x_callee_copies ( cumulative_args_t cum_v ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , const_tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { return true ; } </s>


<s> void print ( raw_ostream & OS ) const override { switch ( Kind ) { case Immediate : OS << * getImm ( ) ; break ; case Token : OS << "'" << getToken ( ) << "'" ; break ; } } </s>

print - Print a debug representation of the operand to the given stream .


<s> std :: pair < SDValue , SDValue > SystemZSelectionDAGInfo :: EmitTargetCodeForStrcpy ( SelectionDAG & DAG , SDLoc DL , SDValue Chain , SDValue Dest , SDValue Src , MachinePointerInfo DestPtrInfo , MachinePointerInfo SrcPtrInfo , bool isStpcpy ) const { SDVTList VTs = DAG . getVTList ( Dest . getValueType ( ) , MVT :: Other ) ; SDValue EndDest = DAG . getNode ( SystemZISD :: STPCPY , DL , VTs , Chain , Dest , Src , DAG . getConstant ( 0 , DL , MVT :: i32 ) ) ; return std :: make_pair ( isStpcpy ? EndDest : Dest , EndDest . getValue ( 1 ) ) ; } </s>

Emit target-specific code that performs a strcpy or stpcpy , in cases where that is faster than a libcall .


<s> bool DCPU16InstrInfo :: isUnpredicatedTerminator ( const MachineInstr * MI ) const { if ( ! MI -> isTerminator ( ) ) return false ; if ( MI -> isBranch ( ) && ! MI -> isBarrier ( ) ) return true ; if ( ! MI -> isPredicable ( ) ) return true ; return ! isPredicated ( MI ) ; } </s>

Returns true if the instruction is a terminator instruction that has not been predicated .


<s> bool small_data_pattern ( rtx op , machine_mode ) { if ( GET_CODE ( op ) == SEQUENCE ) return false ; subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , op , ALL ) { const_rtx x = * iter ; if ( GET_CODE ( x ) == PLUS && rtx_equal_p ( XEXP ( x , 0 ) , pic_offset_table_rtx ) ) iter . skip_subrtxes ( ) ; else if ( arc_rewrite_small_data_p ( x ) ) return true ; } return false ; } </s>

Return true if OP refers to small data symbols directly , not through a PLUS .


<s> void assignValueToAddress ( Register ValVReg , Register Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { if ( VA . getLocInfo ( ) == CCValAssign :: LocInfo :: AExt ) { Size = VA . getLocVT ( ) . getSizeInBits ( ) / 8 ; ValVReg = MIRBuilder . buildAnyExt ( LLT :: scalar ( Size * 8 ) , ValVReg ) . getReg ( 0 ) ; } MachineFunction & MF = MIRBuilder . getMF ( ) ; auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , inferAlignFromPtrInfo ( MF , MPO ) ) ; MIRBuilder . buildStore ( ValVReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> unsigned char X86Subtarget :: classifyGlobalFunctionReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return X86II :: MO_NO_FLAG ; if ( isTargetCOFF ( ) ) { if ( GV -> hasDLLImportStorageClass ( ) ) return X86II :: MO_DLLIMPORT ; return X86II :: MO_COFFSTUB ; } const Function * F = dyn_cast_or_null < Function > ( GV ) ; if ( isTargetELF ( ) ) { if ( is64Bit ( ) && F && ( CallingConv :: X86_RegCall == F -> getCallingConv ( ) ) ) return X86II :: MO_GOTPCREL ; if ( ( ( F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) ) || ( ! F && M . getRtLibUseGOT ( ) ) ) && is64Bit ( ) ) return X86II :: MO_GOTPCREL ; return X86II :: MO_PLT ; } if ( is64Bit ( ) ) { if ( F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) ) return X86II :: MO_GOTPCREL ; return X86II :: MO_NO_FLAG ; } return X86II :: MO_NO_FLAG ; } </s>

Classify a global function reference for the current subtarget .


<s> int avr_accumulate_outgoing_args ( void ) { if ( ! cfun ) return TARGET_ACCUMULATE_OUTGOING_ARGS ; return ( TARGET_ACCUMULATE_OUTGOING_ARGS && ! ( cfun -> calls_setjmp || cfun -> has_nonlocal_label ) ) ; } </s>

Implement ` ACCUMULATE_OUTGOING_ARGS ' .


<s> int mask_low_and_shift_len ( machine_mode mode , rtx mask , rtx shift ) { HOST_WIDE_INT shval ; shval = INTVAL ( shift ) & ( GET_MODE_BITSIZE ( mode ) - 1 ) ; return exact_log2 ( ( UINTVAL ( mask ) >> shval ) + 1 ) ; } </s>

The canonical form of a mask-low-and-shift-left operation is ( and ( ashift X SHIFT ) MASK ) where MASK has the lower SHIFT number of bits cleared . Thus we need to shift MASK to the right before checking if it is a valid mask value . MODE is the mode of the operation . If true return the length of the mask , otherwise return -1 .


<s> static void release_options_strings ( char * * option_strings ) { for ( unsigned i = 0 ; i < IX86_FUNCTION_SPECIFIC_MAX ; i ++ ) free ( option_strings [ i ] ) ; } </s>


<s> BitVector LEGRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( LEG :: SP ) ; Reserved . set ( LEG :: LR ) ; return Reserved ; } </s>


"frame pointer should not have been eliminated"

"SecondSPAdjustAmount should be greater than zero"


<s> void x86_order_regs_for_local_alloc ( void ) { int pos = 0 ; int i ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( GENERAL_REGNO_P ( i ) && call_used_regs [ i ] ) reg_alloc_order [ pos ++ ] = i ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( GENERAL_REGNO_P ( i ) && ! call_used_regs [ i ] ) reg_alloc_order [ pos ++ ] = i ; if ( ! TARGET_SSE_MATH ) for ( i = FIRST_STACK_REG ; i <= LAST_STACK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_SSE_REG ; i <= LAST_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_REX_SSE_REG ; i <= LAST_REX_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_MASK_REG ; i <= LAST_MASK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; if ( TARGET_SSE_MATH ) for ( i = FIRST_STACK_REG ; i <= LAST_STACK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_MMX_REG ; i <= LAST_MMX_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; while ( pos < FIRST_PSEUDO_REGISTER ) reg_alloc_order [ pos ++ ] = 0 ; } </s>

Order the registers for register allocator .


<s> bool PPCCTRLoops :: runOnFunction ( Function & F ) { LI = & getAnalysis < LoopInfo > ( ) ; SE = & getAnalysis < ScalarEvolution > ( ) ; DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; DataLayoutPass * DLP = getAnalysisIfAvailable < DataLayoutPass > ( ) ; DL = DLP ? & DLP -> getDataLayout ( ) : 0 ; LibInfo = getAnalysisIfAvailable < TargetLibraryInfo > ( ) ; bool MadeChange = false ; for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) { Loop * L = * I ; if ( ! L -> getParentLoop ( ) ) MadeChange |= convertToCTRLoop ( L ) ; } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static bool ix86_vector_duplicate_value ( machine_mode mode , rtx target , rtx val ) { bool ok ; rtx_insn * insn ; rtx dup ; dup = gen_vec_duplicate ( mode , val ) ; insn = emit_insn ( gen_rtx_SET ( target , dup ) ) ; if ( recog_memoized ( insn ) < 0 ) { rtx_insn * seq ; machine_mode innermode = GET_MODE_INNER ( mode ) ; rtx reg ; start_sequence ( ) ; reg = force_reg ( innermode , val ) ; if ( GET_MODE ( reg ) != innermode ) reg = gen_lowpart ( innermode , reg ) ; SET_SRC ( PATTERN ( insn ) ) = gen_vec_duplicate ( mode , reg ) ; seq = get_insns ( ) ; end_sequence ( ) ; if ( seq ) emit_insn_before ( seq , insn ) ; ok = recog_memoized ( insn ) >= 0 ; gcc_assert ( ok ) ; } return true ; } </s>

A subroutine of ix86_expand_vector_init_duplicate . Tries to fill target with val via vec_duplicate .


<s> static void nios2_trampoline_init ( rtx m_tramp , tree fndecl , rtx cxt ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx ctx_reg = force_reg ( Pmode , cxt ) ; rtx addr = force_reg ( Pmode , XEXP ( m_tramp , 0 ) ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , "__trampoline_setup" ) , LCT_NORMAL , VOIDmode , addr , Pmode , fnaddr , Pmode , ctx_reg , Pmode ) ; } </s>

Emit RTL insns to initialize the variable parts of a trampoline . FNADDR is an RTX for the address of the function 's pure code . CXT is an RTX for the static chain value for the function . On Nios II , we handle this by a library call .


"Call frame pseudos should only be used for dynamic stack adjustment"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> const MCPhysReg * MipsRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const MipsSubtarget & Subtarget = MF -> getSubtarget < MipsSubtarget > ( ) ; const Function * F = MF -> getFunction ( ) ; if ( F -> hasFnAttribute ( "interrupt" ) ) { if ( Subtarget . hasMips64 ( ) ) return Subtarget . hasMips64r6 ( ) ? CSR_Interrupt_64R6_SaveList : CSR_Interrupt_64_SaveList ; else return Subtarget . hasMips32r6 ( ) ? CSR_Interrupt_32R6_SaveList : CSR_Interrupt_32_SaveList ; } if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_SaveList ; if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_SaveList ; if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_SaveList ; if ( Subtarget . isFP64bit ( ) ) return CSR_O32_FP64_SaveList ; if ( Subtarget . isFPXX ( ) ) return CSR_O32_FPXX_SaveList ; return CSR_O32_SaveList ; } </s>

Mips Mips Mips Mips "interrupt" Mips Mips Mips


<s>
bool
ARMBaseInstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
TBB
=
nullptr
;
FBB
=
nullptr
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
if
(
I
==
MBB
.
begin
(
)
)
return
false
;
I
;
while
(
isPredicated
(
*
I
)
||
I
->
isTerminator
(
)
||
I
->
isDebugValue
(
)
)
{
bool
CantAnalyze
=
false
;
while
(
I
->
isDebugValue
(
)
||
!
I
->
isTerminator
(
)
)
{
if
(
I
==
MBB
.
begin
(
)
)
return
false
;
I
;
}
if
(
isIndirectBranchOpcode
(
I
->
getOpcode
(
)
)
||
isJumpTableBranchOpcode
(
I
->
getOpcode
(
)
)
)
{
CantAnalyze
=
true
;
}
else
if
(
isUncondBranchOpcode
(
I
->
getOpcode
(
)
)
)
{
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
}
else
if
(
isCondBranchOpcode
(
I
->
getOpcode
(
)
)
)
{
if
(
!
Cond
.
empty
(
)
)
return
true
;
assert
(
!
FBB
&&
"FBB should have been null."
)
;
FBB
=
TBB
;
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
Cond
.
push_back
(
I
->
getOperand
(
1
)
)
;
Cond
.
push_back
(
I
->
getOperand
(
2
)
)
;
}
else
if
(
I
->
isReturn
(
)
)
{
CantAnalyze
=
!
isPredicated
(
*
I
)
;
}
else
{
return
true
;
}
if
(
!
isPredicated
(
*
I
)
&&
(
isUncondBranchOpcode
(
I
->
getOpcode
(
)
)
||
isIndirectBranchOpcode
(
I
->
getOpcode
(
)
)
||
isJumpTableBranchOpcode
(
I
->
getOpcode
(
)
)
||
I
->
isReturn
(
)
)
)
{
Cond
.
clear
(
)
;
FBB
=
nullptr
;
if
(
AllowModify
)
{
MachineBasicBlock
::
iterator
DI
=
std
::
next
(
I
)
;
while
(
DI
!=
MBB
.
end
(
)
)
{
MachineInstr
&
InstToDelete
=
*
DI
;
++
DI
;
InstToDelete
.
eraseFromParent
(
)
;
}
}
}
if
(
CantAnalyze
)
return
true
;
if
(
I
==
MBB
.
begin
(
)
)
return
false
;
I
;
}
return
false
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> BitVector NVPTXRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; for ( unsigned Reg = NVPTX :: ENVREG0 ; Reg <= NVPTX :: ENVREG31 ; ++ Reg ) { markSuperRegs ( Reserved , Reg ) ; } markSuperRegs ( Reserved , NVPTX :: VRFrame32 ) ; markSuperRegs ( Reserved , NVPTX :: VRFrameLocal32 ) ; markSuperRegs ( Reserved , NVPTX :: VRFrame64 ) ; markSuperRegs ( Reserved , NVPTX :: VRFrameLocal64 ) ; markSuperRegs ( Reserved , NVPTX :: VRDepot ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> MandarinTargetLowering :: ConstraintType MandarinTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'r' : return C_RegisterClass ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> const char * BPFTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( BPFISD :: NodeType ) Opcode ) { case BPFISD :: FIRST_NUMBER : break ; case BPFISD :: RET_FLAG : return "BPFISD::RET_FLAG" ; case BPFISD :: CALL : return "BPFISD::CALL" ; case BPFISD :: SELECT_CC : return "BPFISD::SELECT_CC" ; case BPFISD :: BR_CC : return "BPFISD::BR_CC" ; case BPFISD :: Wrapper : return "BPFISD::Wrapper" ; case BPFISD :: MEMCPY : return "BPFISD::MEMCPY" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> getFnAttributes ( ) . hasAttribute ( Attributes :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( N -> getOpcode ( ) == X86ISD :: CALL || ( N -> getOpcode ( ) == X86ISD :: TC_RETURN && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; EVT SrcVT = N -> getOperand ( 0 ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( 0 ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; bool SrcIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> void Z80Operand :: print ( raw_ostream & OS ) const { } </s>

print - Print a debug representation of the operand to the given stream .


<s> TargetLowering :: AtomicExpansionKind SITargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * CmpX ) const { return CmpX -> getPointerAddressSpace ( ) == AMDGPUAS :: PRIVATE_ADDRESS ? AtomicExpansionKind :: NotAtomic : AtomicExpansionKind :: None ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> static bool is_nonpipeline_insn ( rtx_insn * insn ) { enum attr_type type ; if ( ! insn || ! NONDEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; type = get_attr_type ( insn ) ; if ( type == TYPE_MUL || type == TYPE_DIV || type == TYPE_SDIV || type == TYPE_DDIV || type == TYPE_SSQRT || type == TYPE_DSQRT || type == TYPE_MFCR || type == TYPE_MFCRF || type == TYPE_MFJMPR ) { return true ; } return false ; } </s>

Return true if the instruction is nonpipelined on the Cell .


<s> static rtx frv_dwarf_store ( rtx reg , int offset ) { rtx set = gen_rtx_SET ( gen_rtx_MEM ( GET_MODE ( reg ) , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) , reg ) ; RTX_FRAME_RELATED_P ( set ) = 1 ; return set ; } </s>

Generate a frame-related expression : ( set REG ( mem ( plus ( sp ) ( const_int OFFSET ) ) ) ) . Such expressions are used in FRAME_RELATED_EXPR notes for more complex instructions . Marking the expressions as frame-related is superfluous if the note contains just a single set . But if the note contains a PARALLEL or SEQUENCE that has several sets , each set must be individually marked as frame-related .


<s> static void do_isel ( rtx dest , rtx cmp , rtx src_t , rtx src_f , rtx cr ) { if ( GET_MODE ( dest ) == DImode ) emit_insn ( gen_isel_cc_di ( dest , cmp , src_t , src_f , cr ) ) ; else emit_insn ( gen_isel_cc_si ( dest , cmp , src_t , src_f , cr ) ) ; } </s>

Emit an isel of the proper mode for DEST . DEST is the isel destination register . SRC1 is the isel source if CR is true . SRC2 is the isel source if CR is false . CR is the condition for the isel .


<s> unsigned PPCTTI :: getIntImmCost ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) const { if ( DisablePPCConstHoist ) return TargetTransformInfo :: getIntImmCost ( Opcode , Idx , Imm , Ty ) ; assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return ~ 0U ; unsigned ImmIdx = ~ 0U ; bool ShiftedFree = false , RunFree = false , UnsignedFree = false , ZeroFree = false ; switch ( Opcode ) { default : return TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TCC_Basic ; return TCC_Free ; case Instruction :: And : RunFree = true ; case Instruction :: Add : case Instruction :: Or : case Instruction :: Xor : ShiftedFree = true ; case Instruction :: Sub : case Instruction :: Mul : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : ImmIdx = 1 ; break ; case Instruction :: ICmp : UnsignedFree = true ; ImmIdx = 1 ; case Instruction :: Select : ZeroFree = true ; break ; case Instruction :: PHI : case Instruction :: Call : case Instruction :: Ret : case Instruction :: Load : case Instruction :: Store : break ; } if ( ZeroFree && Imm == 0 ) return TCC_Free ; if ( Idx == ImmIdx && Imm . getBitWidth ( ) <= 64 ) { if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) return TCC_Free ; if ( RunFree ) { if ( Imm . getBitWidth ( ) <= 32 && ( isShiftedMask_32 ( Imm . getZExtValue ( ) ) || isShiftedMask_32 ( ~ Imm . getZExtValue ( ) ) ) ) return TCC_Free ; if ( ST -> isPPC64 ( ) && ( isShiftedMask_64 ( Imm . getZExtValue ( ) ) || isShiftedMask_64 ( ~ Imm . getZExtValue ( ) ) ) ) return TCC_Free ; } if ( UnsignedFree && isUInt < 16 > ( Imm . getZExtValue ( ) ) ) return TCC_Free ; if ( ShiftedFree && ( Imm . getZExtValue ( ) & 0xFFFF ) == 0 ) return TCC_Free ; } return PPCTTI :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> void ARMTargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( ! Subtarget -> getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) ) return TargetLowering :: insertSSPDeclarations ( M ) ; M . getOrInsertGlobal ( "__security_cookie" , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; FunctionCallee SecurityCheckCookie = M . getOrInsertFunction ( "__security_check_cookie" , Type :: getVoidTy ( M . getContext ( ) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; if ( Function * F = dyn_cast < Function > ( SecurityCheckCookie . getCallee ( ) ) ) F -> addAttribute ( 1 , Attribute :: AttrKind :: InReg ) ; } </s>

Inserts necessary declarations for SSP ( stack protection ) purpose .


<s> std :: unique_ptr < PBQPRAConstraint > AArch64Subtarget :: getCustomPBQPConstraints ( ) const { return balanceFPOps ( ) ? std :: make_unique < A57ChainingConstraint > ( ) : nullptr ; } </s>

Return PBQPConstraint ( s ) for the target .


<s>
void
MipsDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
if
(
trySelect
(
Node
)
)
return
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
ADD
:
if
(
Node
->
getSimpleValueType
(
0
)
.
isVector
(
)
&&
selectVecAddAsVecSubIfProfitable
(
Node
)
)
return
;
break
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
ReplaceNode
(
Node
,
getGlobalBaseReg
(
false
)
)
;
return
;
case
ISD
::
LOAD
:
case
ISD
::
STORE
:
assert
(
(
Subtarget
->
systemSupportsUnalignedAccess
(
cast
<
MemSDNode
>
(
Node
)
->
getAddressSpace
(
)
)
||
(
cast
<
MemSDNode
>
(
Node
)
->
getMemoryVT
(
)
.
getSizeInBits
(
)
/
8
)
<=
cast
<
MemSDNode
>
(
Node
)
->
getAlignment
(
)
)
&&
"Unexpected unaligned loads/stores."
)
;
break
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

Mips
Mips
"== "
"\n"
1
ISD::ADD
0
ISD::GLOBAL_OFFSET_TABLE
ISD::LOAD
ISD::STORE
8
"Unexpected unaligned loads/stores."


<s> BitVector Z80RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const Z80FrameLowering * TFI = getFrameLowering ( MF ) ; Reserved . set ( Z80 :: SPS ) ; Reserved . set ( Z80 :: PC ) ; if ( TFI -> hasFP ( MF ) ) { for ( MCSubRegIterator I ( Z80 :: IX , this , true ) ; I . isValid ( ) ; ++ I ) { Reserved . set ( * I ) ; } } return Reserved ; } </s>


<s> bool X86InstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Cond , Register DstReg , Register TrueReg , Register FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( ! Subtarget . canUseCMOV ( ) ) return false ; if ( Cond . size ( ) != 1 ) return false ; if ( ( X86 :: CondCode ) Cond [ 0 ] . getImm ( ) > X86 :: LAST_VALID_COND ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( X86 :: GR16RegClass . hasSubClassEq ( RC ) || X86 :: GR32RegClass . hasSubClassEq ( RC ) || X86 :: GR64RegClass . hasSubClassEq ( RC ) ) { CondCycles = 2 ; TrueCycles = 2 ; FalseCycles = 2 ; return true ; } return false ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> static bool is_load_insn1 ( rtx pat , rtx * load_mem ) { if ( ! pat || pat == NULL_RTX ) return false ; if ( GET_CODE ( pat ) == SET ) { if ( REG_P ( SET_DEST ( pat ) ) ) return find_mem_ref ( SET_SRC ( pat ) , load_mem ) ; else return false ; } if ( GET_CODE ( pat ) == PARALLEL ) { int i ; for ( i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) if ( is_load_insn1 ( XVECEXP ( pat , 0 , i ) , load_mem ) ) return true ; } return false ; } </s>

Determine if PAT is a PATTERN of a load insn .


<s> void X86FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; int64_t TailCallReturnAddrDelta = X86FI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < 0 ) { MFI . CreateFixedObject ( - TailCallReturnAddrDelta , TailCallReturnAddrDelta - SlotSize , true ) ; } if ( TRI -> hasBasePointer ( MF ) ) { SavedRegs . set ( TRI -> getBaseRegister ( ) ) ; if ( MF . hasEHFunclets ( ) ) { int FI = MFI . CreateSpillStackObject ( SlotSize , SlotSize ) ; X86FI -> setHasSEHFramePtrSave ( true ) ; X86FI -> setSEHFramePtrSaveIndex ( FI ) ; } } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> void R600TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { switch ( N -> getOpcode ( ) ) { default : AMDGPUTargetLowering :: ReplaceNodeResults ( N , Results , DAG ) ; return ; case ISD :: FP_TO_UINT : Results . push_back ( LowerFPTOUINT ( N -> getOperand ( 0 ) , DAG ) ) ; return ; case ISD :: LOAD : { SDNode * Node = LowerLOAD ( SDValue ( N , 0 ) , DAG ) . getNode ( ) ; Results . push_back ( SDValue ( Node , 0 ) ) ; Results . push_back ( SDValue ( Node , 1 ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( N , 1 ) , SDValue ( Node , 1 ) ) ; return ; } case ISD :: STORE : SDNode * Node = LowerSTORE ( SDValue ( N , 0 ) , DAG ) . getNode ( ) ; Results . push_back ( SDValue ( Node , 0 ) ) ; return ; } } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> bool gen_ldm_seq ( rtx * operands , int nops , bool sort_regs ) { int regs [ MAX_LDM_STM_OPS ] , mem_order [ MAX_LDM_STM_OPS ] ; rtx mems [ MAX_LDM_STM_OPS ] ; int i , j , base_reg ; rtx base_reg_rtx ; HOST_WIDE_INT offset ; int write_back = FALSE ; int ldm_case ; rtx addr ; ldm_case = load_multiple_sequence ( operands , nops , regs , mem_order , & base_reg , & offset , ! sort_regs ) ; if ( ldm_case == 0 ) return false ; if ( sort_regs ) for ( i = 0 ; i < nops - 1 ; i ++ ) for ( j = i + 1 ; j < nops ; j ++ ) if ( regs [ i ] > regs [ j ] ) { int t = regs [ i ] ; regs [ i ] = regs [ j ] ; regs [ j ] = t ; } base_reg_rtx = gen_rtx_REG ( Pmode , base_reg ) ; if ( TARGET_THUMB1 ) { gcc_assert ( ldm_case == 1 || ldm_case == 5 ) ; write_back = true ; for ( i = 0 ; i < nops ; i ++ ) if ( base_reg == regs [ i ] ) write_back = false ; if ( write_back && ! peep2_reg_dead_p ( nops , base_reg_rtx ) ) return false ; } if ( ldm_case == 5 ) { rtx newbase = TARGET_THUMB1 ? base_reg_rtx : gen_rtx_REG ( SImode , regs [ 0 ] ) ; emit_insn ( gen_addsi3 ( newbase , base_reg_rtx , GEN_INT ( offset ) ) ) ; offset = 0 ; base_reg_rtx = newbase ; } for ( i = 0 ; i < nops ; i ++ ) { addr = plus_constant ( Pmode , base_reg_rtx , offset + i * 4 ) ; mems [ i ] = adjust_automodify_address_nv ( operands [ nops + mem_order [ i ] ] , SImode , addr , 0 ) ; } emit_insn ( arm_gen_load_multiple_1 ( nops , regs , mems , base_reg_rtx , write_back ? offset + i * 4 : 0 ) ) ; return true ; } </s>

Called from a peephole2 expander to turn a sequence of loads into an LDM instruction . OPERANDS are the operands found by the peephole matcher ; NOPS indicates how many separate loads we are trying to combine . SORT_REGS is true if we can reorder the registers because they are used commutatively subsequently . Returns true iff we could generate a new instruction .


<s> void DLXInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annotation , const MCSubtargetInfo & ) { if ( ! printAlias ( MI , OS ) && ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annotation ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> SDValue Cpu0TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; unsigned Opc = N -> getOpcode ( ) ; switch ( Opc ) { default : break ; case ISD :: SDIVREM : case ISD :: UDIVREM : return performDivRemCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s>
bool
ARMConstantIslands
::
isBBInRange
(
MachineInstr
*
MI
,
MachineBasicBlock
*
DestBB
,
unsigned
MaxDisp
)
{
unsigned
PCAdj
=
isThumb
4
:
8
;
unsigned
BrOffset
=
getOffsetOf
(
MI
)
+
PCAdj
;
unsigned
DestOffset
=
BBInfo
[
DestBB
->
getNumber
(
)
]
.
Offset
;
DEBUG
(
dbgs
(
)
<<
"Branch of destination BB#"
<<
DestBB
->
getNumber
(
)
<<
" from BB#"
<<
MI
->
getParent
(
)
->
getNumber
(
)
<<
" max delta="
<<
MaxDisp
<<
" from "
<<
getOffsetOf
(
MI
)
<<
" to "
<<
DestOffset
<<
" offset "
<<
int
(
DestOffset
BrOffset
)
<<
"\t"
<<
*
MI
)
;
if
(
BrOffset
<=
DestOffset
)
{
if
(
DestOffset
BrOffset
<=
MaxDisp
)
return
true
;
}
else
{
if
(
BrOffset
DestOffset
<=
MaxDisp
)
return
true
;
}
return
false
;
}
</s>

isBBInRange - Returns true if the distance between specific MI and specific BB can fit in MI 's displacement field .

ARM
ARM
4
8
"Branch of destination BB#"
" from BB#"
" max delta="
" from "
" to "
" offset "
"\t"


<s> static bool vr4130_swap_insns_p ( rtx insn1 , rtx insn2 ) { rtx dep ; for ( dep = INSN_DEPEND ( insn1 ) ; dep != 0 ; dep = XEXP ( dep , 1 ) ) if ( REG_NOTE_KIND ( dep ) == REG_DEP_ANTI && INSN_PRIORITY ( XEXP ( dep , 0 ) ) > INSN_PRIORITY ( insn2 ) && recog_memoized ( XEXP ( dep , 0 ) ) >= 0 && get_attr_vr4130_class ( XEXP ( dep , 0 ) ) == VR4130_CLASS_ALU ) return false ; if ( vr4130_last_insn != 0 && recog_memoized ( insn1 ) >= 0 && recog_memoized ( insn2 ) >= 0 ) { enum attr_vr4130_class class1 = get_attr_vr4130_class ( insn1 ) ; enum attr_vr4130_class class2 = get_attr_vr4130_class ( insn2 ) ; if ( class1 != class2 || class1 == VR4130_CLASS_ALU ) { bool dep1 = vr4130_true_reg_dependence_p ( insn1 ) ; bool dep2 = vr4130_true_reg_dependence_p ( insn2 ) ; if ( dep1 != dep2 ) return dep1 ; if ( class1 != VR4130_CLASS_ALU && recog_memoized ( vr4130_last_insn ) >= 0 && class1 == get_attr_vr4130_class ( vr4130_last_insn ) ) return true ; } } return false ; } </s>

A TUNE_MIPS4130 helper function . Given that INSN1 is at the head of the ready queue and that INSN2 is the instruction after it , return true if it is worth promoting INSN2 ahead of INSN1 . Look for cases in which INSN1 and INSN2 can probably issue in parallel , but for which ( INSN2 , INSN1 ) should be less sensitive to instruction alignment than ( INSN1 , INSN2 ) . See 4130.md for more details .


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { if ( ! Subtarget -> isAAPCS_ABI ( ) || Subtarget -> isTargetMachO ( ) || Subtarget -> isTargetWindows ( ) ) return SDValue ( ) ; const ARMTargetLowering & TLI = * static_cast < const ARMTargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Type * IntPtrTy = TLI . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( MVT :: i32 ) ) Src = DAG . getNode ( ISD :: TRUNCATE , dl , MVT :: i32 , Src ) ; else Src = DAG . getNode ( ISD :: ZERO_EXTEND , dl , MVT :: i32 , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , & Args , 0 ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } </s>

Emit target-specific code that performs a memset .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { TII = MF . getSubtarget < PPCSubtarget > ( ) . getInstrInfo ( ) ; LIS = & getAnalysis < LiveIntervals > ( ) ; bool Changed = false ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed = true ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> unsigned NVPTXTTI :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , OperandValueKind Opd1Info , OperandValueKind Opd2Info , OperandValueProperties Opd1PropInfo , OperandValueProperties Opd2PropInfo ) const { std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Ty ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return TargetTransformInfo :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: ADD : case ISD :: MUL : case ISD :: XOR : case ISD :: OR : case ISD :: AND : if ( LT . second . SimpleTy == MVT :: i64 ) return 2 * LT . first ; return TargetTransformInfo :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .

NVPTX NVPTX ISD::ADD ISD::MUL ISD::XOR ISD::OR ISD::AND MVT::i64 2


<s> enum m68k_function_kind m68k_get_function_kind ( tree func ) { tree a ; gcc_assert ( TREE_CODE ( func ) == FUNCTION_DECL ) ; a = lookup_attribute ( "interrupt" , DECL_ATTRIBUTES ( func ) ) ; if ( a != NULL_TREE ) return m68k_fk_interrupt_handler ; a = lookup_attribute ( "interrupt_handler" , DECL_ATTRIBUTES ( func ) ) ; if ( a != NULL_TREE ) return m68k_fk_interrupt_handler ; a = lookup_attribute ( "interrupt_thread" , DECL_ATTRIBUTES ( func ) ) ; if ( a != NULL_TREE ) return m68k_fk_interrupt_thread ; return m68k_fk_normal_function ; } </s>

Return m68k_fk_interrupt_handler if FUNC has an `` interrupt '' or `` interrupt_handler '' attribute and interrupt_thread if FUNC has an `` interrupt_thread '' attribute . Otherwise , return m68k_fk_normal_function .


"ReadCycleWrite is only to be used on riscv32"

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> void SIInstrInfo :: insertNoops ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned Quantity ) const { DebugLoc DL = MBB . findDebugLoc ( MI ) ; while ( Quantity > 0 ) { unsigned Arg = std :: min ( Quantity , 8u ) ; Quantity -= Arg ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: S_NOP ) ) . addImm ( Arg - 1 ) ; } } </s>

Insert noops into the instruction stream at the specified point .


<s> Register CAHPRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? CAHP :: X2 : CAHP :: X1 ; } </s>


<s> rtx arc_eh_return_address_location ( void ) { rtx mem ; int offset ; struct arc_frame_info * afi ; arc_compute_frame_size ( ) ; afi = & cfun -> machine -> frame_info ; gcc_assert ( crtl -> calls_eh_return ) ; gcc_assert ( afi -> save_return_addr ) ; gcc_assert ( afi -> extra_size >= 4 ) ; offset = afi -> reg_size + afi -> extra_size - 4 ; mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , frame_pointer_rtx , offset ) ) ; MEM_VOLATILE_P ( mem ) = 1 ; return mem ; } </s>

Return rtx for the location of the return address on the stack , suitable for use in __builtin_eh_return . The new return address will be written to this location in order to redirect the return to the exception handler .


<s> const char * msp430_get_linker_devices_include_path ( int argc ATTRIBUTE_UNUSED , const char * * argv ATTRIBUTE_UNUSED ) { char * devices_csv_path ; if ( msp430_check_env_var_for_devices ( & devices_csv_path ) ) return NULL ; return concat ( "-L" , msp430_dirname ( devices_csv_path ) , NULL ) ; } </s>

Spec function . Used to place the path to the MSP430-GCC support files on the command line , prefixed with `` -L '' , so the linker finds the linker scripts in that directory .


<s> static int sequent_regs_live ( ) { int reg ; int live_seq = 0 ; int cur_seq = 0 ; for ( reg = 0 ; reg < 18 ; ++ reg ) { if ( ! call_used_regs [ reg ] ) { if ( regs_ever_live [ reg ] ) { ++ live_seq ; ++ cur_seq ; } else cur_seq = 0 ; } } if ( ! frame_pointer_needed ) { if ( regs_ever_live [ REG_Y ] ) { ++ live_seq ; ++ cur_seq ; } else cur_seq = 0 ; if ( regs_ever_live [ REG_Y + 1 ] ) { ++ live_seq ; ++ cur_seq ; } else cur_seq = 0 ; } else { cur_seq += 2 ; live_seq += 2 ; } return ( cur_seq == live_seq ) ? live_seq : 0 ; } </s>

This function checks sequence of live registers


<s> unsigned MipsAsmParser :: checkEarlyTargetMatchPredicate ( MCInst & Inst , const OperandVector & Operands ) { switch ( Inst . getOpcode ( ) ) { default : return Match_Success ; case Mips :: DATI : case Mips :: DAHI : if ( static_cast < MipsOperand & > ( * Operands [ 1 ] ) . isValidForTie ( static_cast < MipsOperand & > ( * Operands [ 2 ] ) ) ) return Match_Success ; return Match_RequiresSameSrcAndDst ; } } </s>

Validate the instruction match against any complex target predicates before rendering any operands to it .

Mips Mips Mips::DATI Mips::DAHI Mips 1 Mips 2


<s> static bool xstormy16_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { return regno != 16 || mode == BImode ; } </s>


"getMemOperandWithOffset only supports base "

Get the base operand and byte offset of an instruction that reads/writes memory .


<s> void AArch64RegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MCInstrDesc & MCID = TII -> get ( AArch64 :: ADDXri ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; MRI . constrainRegClass ( BaseReg , TII -> getRegClass ( MCID , 0 , this , MF ) ) ; unsigned Shifter = AArch64_AM :: getShifterImm ( AArch64_AM :: LSL , 0 ) ; BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) . addImm ( Shifter ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .


<s> MCELFStreamer & SHUXITargetELFStreamer :: getStreamer ( ) { return static_cast < MCELFStreamer & > ( Streamer ) ; } </s>

Return the output streamer for the assembler .


<s> static HOST_WIDE_INT riscv_vector_alignment ( const_tree type ) { if ( GET_MODE_CLASS ( TYPE_MODE ( type ) ) == MODE_VECTOR_BOOL ) return 8 ; widest_int min_size = constant_lower_bound ( wi :: to_poly_widest ( TYPE_SIZE ( type ) ) ) ; return wi :: umin ( min_size , 128 ) . to_uhwi ( ) ; } </s>


This method should return the register where the return address can be found .


"Extending floating point arguments not supported yet"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s>
SUnit
*
TPCSchedStrategy
::
pickNodeBidrectional
(
bool
&
IsTopNode
)
{
if
(
SUnit
*
SU
=
Bot
.
pickOnlyChoice
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Picked only Bottom\n"
)
;
IsTopNode
=
false
;
return
SU
;
}
if
(
SUnit
*
SU
=
Top
.
pickOnlyChoice
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Picked only Top\n"
)
;
IsTopNode
=
true
;
return
SU
;
}
SchedCandidate
BotCand
;
CandResult
BotResult
=
pickNodeFromQueue
(
Bot
.
Available
,
DAG
->
getBotRPTracker
(
)
,
BotCand
)
;
assert
(
BotResult
!=
NoCand
&&
"failed to find the first candidate"
)
;
if
(
BotResult
==
SingleExcess
||
BotResult
==
SingleCritical
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Prefered Bottom Node\n"
)
;
IsTopNode
=
false
;
return
BotCand
.
SU
;
}
SchedCandidate
TopCand
;
CandResult
TopResult
=
pickNodeFromQueue
(
Top
.
Available
,
DAG
->
getTopRPTracker
(
)
,
TopCand
)
;
assert
(
TopResult
!=
NoCand
&&
"failed to find the first candidate"
)
;
if
(
TopResult
==
SingleExcess
||
TopResult
==
SingleCritical
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Prefered Top Node\n"
)
;
IsTopNode
=
true
;
return
TopCand
.
SU
;
}
if
(
BotResult
==
SingleMax
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Prefered Bottom Node SingleMax\n"
)
;
IsTopNode
=
false
;
return
BotCand
.
SU
;
}
if
(
TopResult
==
SingleMax
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Prefered Top Node SingleMax\n"
)
;
IsTopNode
=
true
;
return
TopCand
.
SU
;
}
if
(
TopCand
.
SCost
>
BotCand
.
SCost
||
BotCand
.
SU
->
getInstr
(
)
->
isPseudo
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Prefered Top Node Cost\n"
)
;
IsTopNode
=
true
;
return
TopCand
.
SU
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Prefered Bottom in Node order\n"
)
;
IsTopNode
=
false
;
return
BotCand
.
SU
;
}
</s>

Pick the best candidate node from either the top or bottom queue .

TPC
TPC
"Picked only Bottom\n"
"Picked only Top\n"
"failed to find the first candidate"
"Prefered Bottom Node\n"
"failed to find the first candidate"
"Prefered Top Node\n"
"Prefered Bottom Node SingleMax\n"
"Prefered Top Node SingleMax\n"
"Prefered Top Node Cost\n"
"Prefered Bottom in Node order\n"


<s> unsigned getNumFixupKinds ( ) const override { return DLX :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


"\nEntering Simple VSETVL PASS and Handling %d basic blocks for "

Simple m_vsetvl_insert vsetvl for optimize == 0 .


<s> unsigned PPCAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand * AsmOp , unsigned Kind ) { int64_t ImmVal ; switch ( Kind ) { case MCK_0 : ImmVal = 0 ; break ; case MCK_1 : ImmVal = 1 ; break ; default : return Match_InvalidOperand ; } PPCOperand * Op = static_cast < PPCOperand * > ( AsmOp ) ; if ( Op -> isImm ( ) && Op -> getImm ( ) == ImmVal ) return Match_Success ; return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


"Pseudo flag-setting opcodes must be marked with 'hasPostISelHook'"

"expect uninitialized optional cc_out operand"

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


<s> static inline unsigned long ia64_rse_slot_num ( unsigned long * addr ) { return ( ( ( unsigned long ) addr ) >> 3 ) & 0x3f ; } </s>


<s> static bool microblaze_valid_index_register_p ( rtx x , machine_mode mode ATTRIBUTE_UNUSED , int strict ) { if ( ! strict && GET_CODE ( x ) == SUBREG ) x = SUBREG_REG ( x ) ; return ( GET_CODE ( x ) == REG && microblaze_regno_ok_for_base_p ( REGNO ( x ) , strict ) ) ; } </s>

Return true if X is a valid index register for the given mode . Allow only hard registers if STRICT .


<s> void m32r_expand_epilogue ( void ) { int regno ; int noepilogue = FALSE ; int total_size ; gcc_assert ( current_frame_info . initialized ) ; total_size = current_frame_info . total_size ; if ( total_size == 0 ) { rtx insn = get_last_insn ( ) ; if ( insn && NOTE_P ( insn ) ) insn = prev_nonnote_insn ( insn ) ; if ( insn && BARRIER_P ( insn ) ) noepilogue = TRUE ; } if ( ! noepilogue ) { unsigned int var_size = current_frame_info . var_size ; unsigned int args_size = current_frame_info . args_size ; unsigned int gmask = current_frame_info . gmask ; int can_trust_sp_p = ! cfun -> calls_alloca ; if ( flag_exceptions ) emit_insn ( gen_blockage ( ) ) ; if ( can_trust_sp_p ) { unsigned int reg_offset = var_size + args_size ; if ( reg_offset == 0 ) ; else if ( reg_offset < 32768 ) emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( reg_offset ) ) ) ; else { rtx tmp = gen_rtx_REG ( Pmode , PROLOGUE_TMP_REGNUM ) ; emit_insn ( gen_movsi ( tmp , GEN_INT ( reg_offset ) ) ) ; emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , tmp ) ) ; } } else if ( frame_pointer_needed ) { unsigned int reg_offset = var_size + args_size ; if ( reg_offset == 0 ) emit_insn ( gen_movsi ( stack_pointer_rtx , frame_pointer_rtx ) ) ; else if ( reg_offset < 32768 ) emit_insn ( gen_addsi3 ( stack_pointer_rtx , frame_pointer_rtx , GEN_INT ( reg_offset ) ) ) ; else { rtx tmp = gen_rtx_REG ( Pmode , PROLOGUE_TMP_REGNUM ) ; emit_insn ( gen_movsi ( tmp , GEN_INT ( reg_offset ) ) ) ; emit_insn ( gen_movsi ( stack_pointer_rtx , frame_pointer_rtx ) ) ; emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , tmp ) ) ; } } else gcc_unreachable ( ) ; if ( current_frame_info . save_lr ) pop ( RETURN_ADDR_REGNUM ) ; gmask &= ~ ( FRAME_POINTER_MASK | RETURN_ADDR_MASK ) ; for ( regno = M32R_MAX_INT_REGS - 1 ; regno >= 0 ; -- regno ) { if ( ( gmask & ( 1L << regno ) ) != 0 ) pop ( regno ) ; } if ( current_frame_info . save_fp ) pop ( FRAME_POINTER_REGNUM ) ; if ( current_frame_info . pretend_size != 0 ) emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( current_frame_info . pretend_size ) ) ) ; emit_insn ( gen_blockage ( ) ) ; } } </s>

Expand the m32r epilogue as a series of insns .


runOnMachineFunction - Emit the function body .


<s> static void h8300_init_libfuncs ( void ) { set_optab_libfunc ( smul_optab , HImode , "__mulhi3" ) ; set_optab_libfunc ( sdiv_optab , HImode , "__divhi3" ) ; set_optab_libfunc ( udiv_optab , HImode , "__udivhi3" ) ; set_optab_libfunc ( smod_optab , HImode , "__modhi3" ) ; set_optab_libfunc ( umod_optab , HImode , "__umodhi3" ) ; } </s>

Perform target dependent optabs initialization .


<s>
static
void
symbian_add_attribute
(
tree
node
,
const
char
*
attr_name
)
{
tree
attrs
;
tree
attr
;
attrs
=
DECL_P
(
node
)
DECL_ATTRIBUTES
(
node
)
:
TYPE_ATTRIBUTES
(
node
)
;
if
(
lookup_attribute
(
attr_name
,
attrs
)
!=
NULL_TREE
)
return
;
attr
=
get_identifier
(
attr_name
)
;
if
(
DECL_P
(
node
)
)
DECL_ATTRIBUTES
(
node
)
=
tree_cons
(
attr
,
NULL_TREE
,
attrs
)
;
else
TYPE_ATTRIBUTES
(
node
)
=
tree_cons
(
attr
,
NULL_TREE
,
attrs
)
;
fprintf
(
stderr
,
"propogate %s attribute"
,
attr_name
)
;
print_node_brief
(
stderr
,
" to"
,
node
,
0
)
;
fprintf
(
stderr
,
"\n"
)
;
}
</s>

Add the named attribute to the given node . Copes with both DECLs and TYPEs . Will only add the attribute if it is not already present .

sh
"propogate %s attribute"
" to"
0
"\n"


<s> const CallLowering * MipsSubtarget :: getCallLowering ( ) const { return CallLoweringInfo . get ( ) ; } </s>


<s> static void microblaze_elf_asm_destructor ( rtx symbol , int priority ) { microblaze_elf_asm_cdtor ( symbol , priority , false ) ; } </s>

Add a function to the list of static destructors .


<s> static rtx frv_legitimize_target ( enum insn_code icode , rtx target ) { machine_mode mode = insn_data [ icode ] . operand [ 0 ] . mode ; if ( ! target || GET_MODE ( target ) != mode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , mode ) ) return gen_reg_rtx ( mode ) ; else return target ; } </s>

Return a legitimate rtx for instruction ICODE 's return value . Use TARGET if it 's not null , has the right mode , and satisfies operand 0 's predicate .


<s> bool X86RegisterInfo :: hasReservedCallFrame ( MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> static bool xtensa_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { return ( ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > 4 * UNITS_PER_WORD ) ; } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


<s> TargetLowering :: AtomicExpansionKind ARMTargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { unsigned Size = LI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return ( ( Size == 64 ) && ! Subtarget -> isMClass ( ) ) ? AtomicExpansionKind :: LLOnly : AtomicExpansionKind :: None ; } </s>

Returns how the given ( atomic ) load should be expanded by the IR-level AtomicExpand pass .


"WebAssembly Replace Physical Registers"

getPassName - Return a nice clean name for a pass .


<s> static unsigned long get_csky_current_func_type ( void ) { if ( CSKY_FUNCTION_TYPE ( cfun -> machine -> func_type ) == CSKY_FT_UNKNOWN ) { unsigned long type = CSKY_FT_UNKNOWN ; tree a ; tree attr ; gcc_assert ( TREE_CODE ( current_function_decl ) == FUNCTION_DECL ) ; attr = DECL_ATTRIBUTES ( current_function_decl ) ; a = lookup_attribute ( "naked" , attr ) ; if ( a != NULL_TREE ) type |= CSKY_FT_NAKED ; a = lookup_attribute ( "isr" , attr ) ; if ( a == NULL_TREE ) a = lookup_attribute ( "interrupt" , attr ) ; if ( a == NULL_TREE ) type |= CSKY_FT_NORMAL ; else type |= get_csky_isr_type ( TREE_VALUE ( a ) ) ; cfun -> machine -> func_type = type ; } return cfun -> machine -> func_type ; } </s>

Classify cfun as a normal function or some sort of interrupt handler , and set the corresponding bits in cfun- > machine- > func_type .


<s>
bool
processBlock
(
MachineBasicBlock
&
MBB
)
{
bool
Changed
=
false
;
SmallVector
<
MachineInstr
*
,
4
>
ToDelete
;
for
(
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
,
IE
=
MBB
.
end
(
)
;
I
!=
IE
;
++
I
)
{
MachineInstr
*
MI
=
I
;
if
(
MI
->
getOpcode
(
)
==
PPC
::
XXLOR
&&
MI
->
getOperand
(
0
)
.
getReg
(
)
==
MI
->
getOperand
(
1
)
.
getReg
(
)
&&
MI
->
getOperand
(
0
)
.
getReg
(
)
==
MI
->
getOperand
(
2
)
.
getReg
(
)
)
ToDelete
.
push_back
(
MI
)
;
}
if
(
!
ToDelete
.
empty
(
)
)
Changed
=
true
;
for
(
unsigned
i
=
0
,
ie
=
ToDelete
.
size
(
)
;
i
!=
ie
;
++
i
)
{
DEBUG
(
dbgs
(
)
<<
"Removing VSX self-copy: "
<<
*
ToDelete
[
i
]
)
;
ToDelete
[
i
]
->
eraseFromParent
(
)
;
}
return
Changed
;
}
</s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s> void GCNPassConfig :: addPreRegAlloc ( ) { if ( LateCFGStructurize ) { addPass ( createAMDGPUMachineCFGStructurizerPass ( ) ) ; } } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


"This eliminateCallFramePseudoInstr does not support Thumb1!"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesAll ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; AU . addRequired < MachineDominatorTree > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"NOP insertion pass"
;
}
</s>


<s>
void
AMDGPURegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
MI
,
int
SPAdj
,
RegScavenger
*
RS
)
const
{
assert
(
!
"Subroutines not supported yet"
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static bool rs6000_output_addr_const_extra ( FILE * file , rtx x ) { if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , 1 ) ) { case UNSPEC_TOCREL : gcc_checking_assert ( GET_CODE ( XVECEXP ( x , 0 , 0 ) ) == SYMBOL_REF && REG_P ( XVECEXP ( x , 0 , 1 ) ) && REGNO ( XVECEXP ( x , 0 , 1 ) ) == TOC_REGISTER ) ; output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; if ( x == tocrel_base && tocrel_offset != const0_rtx ) { if ( INTVAL ( tocrel_offset ) >= 0 ) fprintf ( file , "+" ) ; output_addr_const ( file , CONST_CAST_RTX ( tocrel_offset ) ) ; } if ( ! TARGET_AIX || ( TARGET_ELF && TARGET_MINIMAL_TOC ) ) { putc ( '-' , file ) ; assemble_name ( file , toc_label_name ) ; need_toc_init = 1 ; } else if ( TARGET_ELF ) fputs ( "@toc" , file ) ; return true ; case UNSPEC_MACHOPIC_OFFSET : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; putc ( '-' , file ) ; machopic_output_function_base_name ( file ) ; return true ; } return false ; } </s>


<s> static void emit_unlikely_jump ( rtx cond , rtx label ) { rtx very_unlikely = GEN_INT ( REG_BR_PROB_BASE / 100 - 1 ) ; rtx x ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , cond , label , pc_rtx ) ; x = emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , x ) ) ; REG_NOTES ( x ) = gen_rtx_EXPR_LIST ( REG_BR_PROB , very_unlikely , NULL_RTX ) ; } </s>

Mark the previous jump instruction as unlikely .


<s> SDValue ARMTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : return PerformADDCombine ( N , DCI ) ; case ISD :: SUB : return PerformSUBCombine ( N , DCI ) ; case ISD :: MUL : return PerformMULCombine ( N , DCI , Subtarget ) ; case ISD :: OR : return PerformORCombine ( N , DCI , Subtarget ) ; case ARMISD :: VMOVRRD : return PerformVMOVRRDCombine ( N , DCI ) ; case ARMISD :: VDUPLANE : return PerformVDUPLANECombine ( N , DCI ) ; case ISD :: INTRINSIC_WO_CHAIN : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DCI . DAG , Subtarget ) ; case ISD :: SIGN_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: ANY_EXTEND : return PerformExtendCombine ( N , DCI . DAG , Subtarget ) ; case ISD :: SELECT_CC : return PerformSELECT_CCCombine ( N , DCI . DAG , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

ARM ARM ISD::ADD ISD::SUB ISD::MUL ISD::OR ARMISD::VMOVRRD ARMISD::VDUPLANE ISD::INTRINSIC_WO_CHAIN ISD::SHL ISD::SRA ISD::SRL ISD::SIGN_EXTEND ISD::ZERO_EXTEND ISD::ANY_EXTEND ISD::SELECT_CC


<s> unsigned SparcAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & GOp , unsigned Kind ) { SparcOperand & Op = ( SparcOperand & ) GOp ; if ( Op . isFloatOrDoubleReg ( ) ) { switch ( Kind ) { default : break ; case MCK_DFPRegs : if ( ! Op . isFloatReg ( ) || SparcOperand :: MorphToDoubleReg ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; case MCK_QFPRegs : if ( SparcOperand :: MorphToQuadReg ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; } } return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .

Sparc Sparc Sparc Sparc SparcOperand::MorphToDoubleReg SparcOperand::MorphToQuadReg


<s> void MipsAsmPrinter :: emitFrameDirective ( ) { const TargetRegisterInfo & RI = * TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) -> getStackSize ( ) ; getTargetStreamer ( ) . emitFrame ( stackReg , stackSize , returnReg ) ; } </s>


<s>
bool
AArch64InstrInfo
::
getMemOperandWithOffsetWidth
(
const
MachineInstr
&
LdSt
,
const
MachineOperand
*
&
BaseOp
,
int64_t
&
Offset
,
unsigned
&
Width
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
LdSt
.
mayLoadOrStore
(
)
&&
"Expected a memory operation."
)
;
if
(
LdSt
.
getNumExplicitOperands
(
)
==
3
)
{
if
(
(
!
LdSt
.
getOperand
(
1
)
.
isReg
(
)
&&
!
LdSt
.
getOperand
(
1
)
.
isFI
(
)
)
||
!
LdSt
.
getOperand
(
2
)
.
isImm
(
)
)
return
false
;
}
else
if
(
LdSt
.
getNumExplicitOperands
(
)
==
4
)
{
if
(
!
LdSt
.
getOperand
(
1
)
.
isReg
(
)
||
(
!
LdSt
.
getOperand
(
2
)
.
isReg
(
)
&&
!
LdSt
.
getOperand
(
2
)
.
isFI
(
)
)
||
!
LdSt
.
getOperand
(
3
)
.
isImm
(
)
)
return
false
;
}
else
return
false
;
unsigned
Scale
=
0
;
int64_t
Dummy1
,
Dummy2
;
if
(
!
getMemOpInfo
(
LdSt
.
getOpcode
(
)
,
Scale
,
Width
,
Dummy1
,
Dummy2
)
)
return
false
;
if
(
LdSt
.
getNumExplicitOperands
(
)
==
3
)
{
BaseOp
=
&
LdSt
.
getOperand
(
1
)
;
Offset
=
LdSt
.
getOperand
(
2
)
.
getImm
(
)
*
Scale
;
}
else
{
assert
(
LdSt
.
getNumExplicitOperands
(
)
==
4
&&
"invalid number of operands"
)
;
BaseOp
=
&
LdSt
.
getOperand
(
2
)
;
Offset
=
LdSt
.
getOperand
(
3
)
.
getImm
(
)
*
Scale
;
}
if
(
!
BaseOp
->
isReg
(
)
&&
!
BaseOp
->
isFI
(
)
)
return
false
;
return
true
;
}
</s>

Return true if get the base operand , byte offset of an instruction and the memory width .


<s>
StringRef
getPassName
(
)
const
override
{
return
"WebAssembly Late Prepare Exception"
;
}
</s>

WebAssembly
"WebAssembly Late Prepare Exception"


<s> static const char * get_trap_mode_suffix ( ) { enum attr_trap_suffix s = get_attr_trap_suffix ( current_output_insn ) ; switch ( s ) { case TRAP_SUFFIX_NONE : return NULL ; case TRAP_SUFFIX_SU : if ( alpha_fptm >= ALPHA_FPTM_SU ) return "su" ; return NULL ; case TRAP_SUFFIX_SUI : if ( alpha_fptm >= ALPHA_FPTM_SUI ) return "sui" ; return NULL ; case TRAP_SUFFIX_V_SV : switch ( alpha_fptm ) { case ALPHA_FPTM_N : return NULL ; case ALPHA_FPTM_U : return "v" ; case ALPHA_FPTM_SU : case ALPHA_FPTM_SUI : return "sv" ; } break ; case TRAP_SUFFIX_V_SV_SVI : switch ( alpha_fptm ) { case ALPHA_FPTM_N : return NULL ; case ALPHA_FPTM_U : return "v" ; case ALPHA_FPTM_SU : return "sv" ; case ALPHA_FPTM_SUI : return "svi" ; } break ; case TRAP_SUFFIX_U_SU_SUI : switch ( alpha_fptm ) { case ALPHA_FPTM_N : return NULL ; case ALPHA_FPTM_U : return "u" ; case ALPHA_FPTM_SU : return "su" ; case ALPHA_FPTM_SUI : return "sui" ; } break ; } abort ( ) ; } </s>

Return the trap mode suffix applicable to the current instruction , or NULL .

alpha "su" "sui" "v" "sv" "v" "sv" "svi" "u" "su" "sui"


<s> int X86FrameLowering :: mergeSPUpdates ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , bool doMergeWithPrevious ) const { if ( ( doMergeWithPrevious && MBBI == MBB . begin ( ) ) || ( ! doMergeWithPrevious && MBBI == MBB . end ( ) ) ) return 0 ; MachineBasicBlock :: iterator PI = doMergeWithPrevious ? std :: prev ( MBBI ) : MBBI ; MachineBasicBlock :: iterator NI = doMergeWithPrevious ? nullptr : std :: next ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = 0 ; if ( ( Opc == X86 :: ADD64ri32 || Opc == X86 :: ADD64ri8 || Opc == X86 :: ADD32ri || Opc == X86 :: ADD32ri8 || Opc == X86 :: LEA32r || Opc == X86 :: LEA64_32r ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { Offset += PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == X86 :: SUB64ri32 || Opc == X86 :: SUB64ri8 || Opc == X86 :: SUB32ri || Opc == X86 :: SUB32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { Offset -= PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } return Offset ; } </s>

Check the instruction before/after the passed instruction .


<s> static machine_mode mode_from_flags ( unsigned int f ) { if ( f & CC_FLAG_FP ) return CC_Fmode ; if ( f & CC_FLAG_O ) { if ( f & CC_FLAG_C ) return CCmode ; else return CC_ZSOmode ; } else if ( f & CC_FLAG_C ) return CC_ZSCmode ; else return CC_ZSmode ; } </s>

Convert a set of flags to a CC_MODE that can implement it .


<s> tree arm_valid_target_attribute_tree ( tree args , struct gcc_options * opts , struct gcc_options * opts_set ) { struct cl_target_option cl_opts ; if ( ! arm_valid_target_attribute_rec ( args , opts ) ) return NULL_TREE ; cl_target_option_save ( & cl_opts , opts ) ; arm_configure_build_target ( & arm_active_target , & cl_opts , opts_set , false ) ; arm_option_check_internal ( opts ) ; arm_option_override_internal ( opts , opts_set ) ; return build_target_option_node ( opts ) ; } </s>

Return a TARGET_OPTION_NODE tree of the target options listed or NULL .


<s> void SystemZPostRASchedStrategy :: advanceTo ( MachineBasicBlock :: iterator NextBegin ) { MachineBasicBlock :: iterator LastEmittedMI = HazardRec -> getLastEmittedMI ( ) ; MachineBasicBlock :: iterator I = ( ( LastEmittedMI != nullptr && LastEmittedMI -> getParent ( ) == MBB ) ? std :: next ( LastEmittedMI ) : MBB -> begin ( ) ) ; for ( ; I != NextBegin ; ++ I ) { if ( I -> isPosition ( ) || I -> isDebugInstr ( ) ) continue ; HazardRec -> emitInstruction ( & * I ) ; } } </s>

advanceTo - Advance the specified iterator to point to the Segment containing the specified position , or end ( ) if the position is past the end of the range .


<s> TargetTransformInfo NyuziTargetMachine :: getTargetTransformInfo ( const Function & F ) { return TargetTransformInfo ( NyuziTTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> unsigned AMDGPUSubtarget :: getMaxLocalMemSizeWithWaveCount ( unsigned NWaves ) const { switch ( NWaves ) { case 10 : return 1638 ; case 9 : return 1820 ; case 8 : return 2048 ; case 7 : return 2340 ; case 6 : return 2730 ; case 5 : return 3276 ; case 4 : return 4096 ; case 3 : return 5461 ; case 2 : return 8192 ; default : return getLocalMemorySize ( ) ; } } </s>

Return the amount of LDS that can be used that will not restrict the occupancy lower than WaveCount .


<s> bool ARM64InstrInfo :: analyzeCompare ( const MachineInstr * MI , unsigned & SrcReg , unsigned & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case ARM64 :: SUBSWrr : case ARM64 :: SUBSWrs : case ARM64 :: SUBSWrx : case ARM64 :: SUBSXrr : case ARM64 :: SUBSXrs : case ARM64 :: SUBSXrx : case ARM64 :: ADDSWrr : case ARM64 :: ADDSWrs : case ARM64 :: ADDSWrx : case ARM64 :: ADDSXrr : case ARM64 :: ADDSXrs : case ARM64 :: ADDSXrx : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; SrcReg2 = MI -> getOperand ( 2 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case ARM64 :: SUBSWri : case ARM64 :: ADDSWri : case ARM64 :: SUBSXri : case ARM64 :: ADDSXri : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = MI -> getOperand ( 2 ) . getImm ( ) ; return true ; case ARM64 :: ANDSWri : case ARM64 :: ANDSXri : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = ARM64_AM :: decodeLogicalImmediate ( MI -> getOperand ( 2 ) . getImm ( ) , MI -> getOpcode ( ) == ARM64 :: ANDSWri ? 32 : 64 ) ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> bool R600InstrInfo :: isLegalToSplitMBBAt ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) const { for ( MachineInstr :: const_mop_iterator I = MBBI -> operands_begin ( ) , E = MBBI -> operands_end ( ) ; I != E ; ++ I ) { if ( I -> isReg ( ) && ! TargetRegisterInfo :: isVirtualRegister ( I -> getReg ( ) ) && I -> isUse ( ) && RI . isPhysRegLiveAcrossClauses ( I -> getReg ( ) ) ) return false ; } return true ; } </s>

Return true if it 's legal to split the given basic block at the specified instruction ( i.e .


"%qT uses address space %qs beyond flash of %d KiB"

"%s %q+D uses address space %qs beyond flash of %d KiB"

"pointer targeting address space %qs must be const in %qT"

"pointer targeting address space %qs must be const"

Sanity check NODE so that all pointers targeting non-generic address spaces go along with CONST qualifier . Writing to these address spaces should be detected and complained about as early as possible .


<s> bool X86FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const X86RegisterInfo * RegInfo = static_cast < const X86RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; unsigned SlotSize = RegInfo -> getSlotSize ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned CalleeSavedFrameSize = 0 ; int SpillSlotOffset = getOffsetOfLocalArea ( ) + X86FI -> getTCReturnAddrDelta ( ) ; if ( hasFP ( MF ) ) { SpillSlotOffset -= SlotSize ; MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; unsigned FPReg = RegInfo -> getFrameRegister ( MF ) ; for ( unsigned i = 0 ; i < CSI . size ( ) ; ++ i ) { if ( TRI -> regsOverlap ( CSI [ i ] . getReg ( ) , FPReg ) ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - 1 ] . setFrameIdx ( SlotIndex ) ; } X86FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = RegInfo -> getMinimalPhysRegClass ( Reg ) ; SpillSlotOffset -= abs ( SpillSlotOffset ) % RC -> getAlignment ( ) ; SpillSlotOffset -= RC -> getSize ( ) ; int SlotIndex = MFI -> CreateFixedSpillStackObject ( RC -> getSize ( ) , SpillSlotOffset ) ; CSI [ i - 1 ] . setFrameIdx ( SlotIndex ) ; MFI -> ensureMaxAlignment ( RC -> getAlignment ( ) ) ; } return true ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> bool X86TargetLowering :: isUsedByReturnOnly ( SDNode * N , SDValue & Chain ) const { if ( N -> getNumValues ( ) != 1 || ! N -> hasNUsesOfValue ( 1 , 0 ) ) return false ; SDValue TCChain = Chain ; SDNode * Copy = * N -> use_begin ( ) ; if ( Copy -> getOpcode ( ) == ISD :: CopyToReg ) { if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - 1 ) . getValueType ( ) == MVT :: Glue ) return false ; TCChain = Copy -> getOperand ( 0 ) ; } else if ( Copy -> getOpcode ( ) != ISD :: FP_EXTEND ) return false ; bool HasRet = false ; for ( const SDNode * U : Copy -> uses ( ) ) { if ( U -> getOpcode ( ) != X86ISD :: RET_FLAG ) return false ; if ( U -> getNumOperands ( ) > 4 ) return false ; if ( U -> getNumOperands ( ) == 4 && U -> getOperand ( U -> getNumOperands ( ) - 1 ) . getValueType ( ) != MVT :: Glue ) return false ; HasRet = true ; } if ( ! HasRet ) return false ; Chain = TCChain ; return true ; } </s>

Return true if result of the specified node is used by a return node only .


"Lanai branch conditions should have one component."

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> static void mmix_reorg ( void ) { int regno ; for ( regno = MMIX_LAST_STACK_REGISTER_REGNUM ; regno >= 0 ; regno -- ) if ( ( regs_ever_live [ regno ] && ! call_used_regs [ regno ] ) || ( regno == MMIX_FRAME_POINTER_REGNUM && frame_pointer_needed ) ) break ; if ( ! TARGET_ABI_GNU && regno < current_function_args_info . regs - 1 ) { regno = current_function_args_info . regs - 1 ; if ( regno > MMIX_RETURN_VALUE_REGNUM - 1 ) regno = MMIX_RETURN_VALUE_REGNUM - 1 ; } cfun -> machine -> highest_saved_stack_register = regno ; } </s>

Implement TARGET_MACHINE_DEPENDENT_REORG . No actual rearrangements done here ; just virtually by calculating the highest saved stack register number used to modify the register numbers at output time .


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> bool X86TargetLowering :: isLegalAddImmediate ( int64_t Imm ) const { return isInt < 32 > ( Imm ) ; } </s>

Return true if the specified immediate is legal add immediate , that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register .


<s> const char * i386_nlm_strip_name_encoding ( const char * str ) { const char * name = default_strip_name_encoding ( str ) ; if ( * str != '*' && ( * name == '_' || * name == '@' ) ) { const char * p = strchr ( name + 1 , '@' ) ; if ( p ) { ++ name ; if ( ISDIGIT ( p [ 1 ] ) ) name = ggc_alloc_string ( name , p - name ) ; else { gcc_assert ( ISDIGIT ( * name ) ) ; name ++ ; gcc_assert ( name == p ) ; } } } return name ; } </s>

Strip the stdcall/fastcall/regparm pre-/suffix .


<s> int GBZ80InstrInfo :: getSPAdjust ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { case GB :: PUSH : return - 2 ; case GB :: POP : return 2 ; case GB :: ADD_SP_e : return ( int8_t ) MI . getOperand ( 0 ) . getImm ( ) ; } return TargetInstrInfo :: getSPAdjust ( MI ) ; } </s>

getSPAdjust - This returns the stack pointer adjustment made by this instruction .


"Should never see frame index on non-address operand"

Get the offset from the referenced frame index in the instruction , if there is one .


<s> unsigned AMDGPUSubtarget :: getOccupancyWithLocalMemSize ( uint32_t Bytes , const Function & F ) const { unsigned WorkGroupSize = getFlatWorkGroupSizes ( F ) . second ; unsigned WorkGroupsPerCu = getMaxWorkGroupsPerCU ( WorkGroupSize ) ; if ( ! WorkGroupsPerCu ) return 0 ; unsigned MaxWaves = getMaxWavesPerEU ( ) ; unsigned Limit = getLocalMemorySize ( ) * MaxWaves / WorkGroupsPerCu ; unsigned NumWaves = Limit / ( Bytes ? Bytes : 1u ) ; NumWaves = std :: min ( NumWaves , MaxWaves ) ; NumWaves = std :: max ( NumWaves , 1u ) ; return NumWaves ; } </s>

Inverse of getMaxLocalMemWithWaveCount .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MemorySSAWrapperPass > ( ) ; AU . setPreservesAll ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> int mcore_dllimport_name_p ( const char * symbol ) { return symbol [ 0 ] == '@' && symbol [ 1 ] == 'i' && symbol [ 2 ] == '.' ; } </s>

Return non-zero if SYMBOL is marked as being dllimport 'd .


<s>
static
int
match_const_restriction
(
typeinfo
*
typedata
)
{
int
oldpos
=
pos
;
if
(
linebuf
[
pos
]
==
'<'
)
{
safe_inc_pos
(
)
;
oldpos
=
pos
;
char
*
x
=
match_integer
(
)
;
if
(
x
==
)
{
diag
(
oldpos
,
"malformed integer.\n"
)
;
return
0
;
}
consume_whitespace
(
)
;
if
(
linebuf
[
pos
]
==
'>'
)
{
typedata
->
restr
=
RES_BITS
;
typedata
->
val1
=
x
;
safe_inc_pos
(
)
;
return
1
;
}
else
if
(
linebuf
[
pos
]
!=
','
)
{
diag
(
pos
,
"malformed restriction.\n"
)
;
return
0
;
}
safe_inc_pos
(
)
;
oldpos
=
pos
;
char
*
y
=
match_integer
(
)
;
if
(
y
==
)
{
diag
(
oldpos
,
"malformed integer.\n"
)
;
return
0
;
}
typedata
->
restr
=
RES_RANGE
;
typedata
->
val1
=
x
;
typedata
->
val2
=
y
;
consume_whitespace
(
)
;
if
(
linebuf
[
pos
]
!=
'>'
)
{
diag
(
pos
,
"malformed restriction.\n"
)
;
return
0
;
}
safe_inc_pos
(
)
;
return
1
;
}
else
if
(
match_bracketed_pair
(
typedata
,
'{'
,
'}'
,
RES_VALUES
)
||
match_bracketed_pair
(
typedata
,
'['
,
']'
,
RES_VAR_RANGE
)
)
return
1
;
return
0
;
}
</s>

A const int argument may be restricted to certain values . This is indicated by one of the following occurring after the `` int ' token : < x > restricts the constant to x bits , interpreted as unsigned < x , y > restricts the constant to the inclusive range [ x , y ] [ x , y ] restricts the constant to the inclusive range [ x , y ] , but only applies if the argument is constant . { x , y } restricts the constant to one of two values , x or y . Here x and y are integer tokens . Note that the `` const '' token is a lie when the restriction is [ x , y ] , but this simplifies the parsing significantly and is hopefully forgivable . Return 1 for success , else 0 .


<s> static const char * arm_identify_fpu_from_isa ( sbitmap isa ) { auto_sbitmap fpubits ( isa_num_bits ) ; auto_sbitmap cand_fpubits ( isa_num_bits ) ; bitmap_and ( fpubits , isa , isa_all_fpubits ) ; if ( bitmap_empty_p ( fpubits ) ) return "softvfp" ; for ( unsigned int i = 0 ; i < ARRAY_SIZE ( all_fpus ) ; i ++ ) { arm_initialize_isa ( cand_fpubits , all_fpus [ i ] . isa_bits ) ; if ( bitmap_equal_p ( fpubits , cand_fpubits ) ) return all_fpus [ i ] . name ; } gcc_unreachable ( ) ; } </s>

Match an ISA feature bitmap to a named FPU . We always use the first entry that exactly matches the feature set , so that we effectively canonicalize the FPU name for the assembler .


"Didn't find MI in its own basic block?"

getOffsetOf - Return the current offset of the specified machine instruction from the start of the function .


<s> const MipsSubtarget * MipsTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool hasMips16Attr = F . getFnAttribute ( "mips16" ) . isValid ( ) ; bool hasNoMips16Attr = F . getFnAttribute ( "nomips16" ) . isValid ( ) ; bool HasMicroMipsAttr = F . getFnAttribute ( "micromips" ) . isValid ( ) ; bool HasNoMicroMipsAttr = F . getFnAttribute ( "nomicromips" ) . isValid ( ) ; bool softFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsBool ( ) ; if ( hasMips16Attr ) FS += FS . empty ( ) ? "+mips16" : ",+mips16" ; else if ( hasNoMips16Attr ) FS += FS . empty ( ) ? "-mips16" : ",-mips16" ; if ( HasMicroMipsAttr ) FS += FS . empty ( ) ? "+micromips" : ",+micromips" ; else if ( HasNoMicroMipsAttr ) FS += FS . empty ( ) ? "-micromips" : ",-micromips" ; if ( softFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < MipsSubtarget > ( TargetTriple , CPU , FS , isLittle , * this , MaybeAlign ( Options . StackAlignmentOverride ) ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

Mips Mips Mips "target-cpu" "target-features" Mips "mips16" Mips "nomips16" Mips "micromips" Mips "nomicromips" "use-soft-float" Mips "+mips16" ",+mips16" Mips "-mips16" ",-mips16" Mips "+micromips" ",+micromips" Mips "-micromips" ",-micromips" "+soft-float" ",+soft-float" Mips


<s> void SIFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const SIMachineFunctionInfo * FuncInfo = MF . getInfo < SIMachineFunctionInfo > ( ) ; if ( FuncInfo -> isEntryFunction ( ) ) return ; const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; const SIInstrInfo * TII = ST . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; for ( const SIMachineFunctionInfo :: SGPRSpillVGPRCSR & Reg : FuncInfo -> getSGPRSpillVGPRs ( ) ) { if ( ! Reg . FI . hasValue ( ) ) continue ; TII -> loadRegFromStackSlot ( MBB , MBBI , Reg . VGPR , Reg . FI . getValue ( ) , & AMDGPU :: VGPR_32RegClass , & TII -> getRegisterInfo ( ) ) ; } unsigned StackPtrReg = FuncInfo -> getStackPtrOffsetReg ( ) ; if ( StackPtrReg == AMDGPU :: NoRegister ) return ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; uint32_t NumBytes = MFI . getStackSize ( ) ; DebugLoc DL ; if ( NumBytes != 0 && hasSP ( MF ) ) { uint32_t RoundedSize = FuncInfo -> isStackRealigned ( ) ? NumBytes + MFI . getMaxAlignment ( ) : NumBytes ; BuildMI ( MBB , MBBI , DL , TII -> get ( AMDGPU :: S_SUB_U32 ) , StackPtrReg ) . addReg ( StackPtrReg ) . addImm ( RoundedSize * ST . getWavefrontSize ( ) ) ; } } </s>

AMDGPU SI SI SI SI SI SI SI AMDGPU::VGPR_32RegClass AMDGPU::NoRegister 0 AMDGPU::S_SUB_U32


<s> bool AlphaTargetMachine :: addPreEmitPass ( PassManagerBase & PM , bool Fast ) { PM . add ( createAlphaBranchSelectionPass ( ) ) ; return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static rtx avr_find_unused_d_reg ( rtx_insn * insn , rtx exclude ) { bool isr_p = ( avr_interrupt_function_p ( current_function_decl ) || avr_signal_function_p ( current_function_decl ) ) ; for ( int regno = 16 ; regno < 32 ; regno ++ ) { rtx reg = all_regs_rtx [ regno ] ; if ( ( exclude && reg_overlap_mentioned_p ( exclude , reg ) ) || fixed_regs [ regno ] ) { continue ; } if ( ! df_regs_ever_live_p ( regno ) && ( TREE_THIS_VOLATILE ( current_function_decl ) || cfun -> machine -> is_OS_task || cfun -> machine -> is_OS_main || ( ! isr_p && call_used_regs [ regno ] ) ) ) { return reg ; } if ( df_regs_ever_live_p ( regno ) && reg_unused_after ( insn , reg ) ) { return reg ; } } return NULL_RTX ; } </s>

Fixme : This is a hack because secondary reloads do n't works as expected . Find an unused d-register to be used as scratch in INSN . EXCLUDE is either NULL_RTX or some register . In the case where EXCLUDE is a register , skip all possible return values that overlap EXCLUDE . The policy for the returned register is similar to that of ` reg_unused_after ' , i.e . the returned register may overlap the SET_DEST of INSN . Return a QImode d-register or NULL_RTX if nothing found .


<s> bool aarch64_sve_ldff1_operand_p ( rtx op ) { if ( ! MEM_P ( op ) ) return false ; struct aarch64_address_info addr ; if ( ! aarch64_classify_address ( & addr , XEXP ( op , 0 ) , GET_MODE ( op ) , false ) ) return false ; if ( addr . type == ADDRESS_REG_IMM ) return known_eq ( addr . const_offset , 0 ) ; return addr . type == ADDRESS_REG_REG ; } </s>

Return true if OP is a valid MEM operand for an SVE LDFF1 instruction .


<s> void ia64_expand_unpack ( rtx operands [ 3 ] , bool unsignedp , bool highp ) { rtx sign = ia64_unpack_sign ( operands [ 1 ] , unsignedp ) ; ia64_unpack_assemble ( operands [ 0 ] , operands [ 1 ] , sign , highp ) ; } </s>

Emit an integral vector unpack operation .


<s> static void * rs6000_init_cost ( struct loop * loop_info ) { rs6000_cost_data * data = XNEW ( struct _rs6000_cost_data ) ; data -> loop_info = loop_info ; data -> cost [ vect_prologue ] = 0 ; data -> cost [ vect_body ] = 0 ; data -> cost [ vect_epilogue ] = 0 ; rs6000_vect_nonmem = false ; return data ; } </s>