<s> int neon_immediate_valid_for_shift ( rtx op , machine_mode mode , rtx * modconst , int * elementwidth , bool isleftshift ) { unsigned int innersize = GET_MODE_UNIT_SIZE ( mode ) ; unsigned int n_elts = CONST_VECTOR_NUNITS ( op ) , i ; unsigned HOST_WIDE_INT last_elt = 0 ; unsigned HOST_WIDE_INT maxshift ; for ( i = 0 ; i < n_elts ; i ++ ) { rtx el = CONST_VECTOR_ELT ( op , i ) ; unsigned HOST_WIDE_INT elpart ; if ( CONST_INT_P ( el ) ) elpart = INTVAL ( el ) ; else if ( CONST_DOUBLE_P ( el ) ) return 0 ; else gcc_unreachable ( ) ; if ( i != 0 && elpart != last_elt ) return 0 ; last_elt = elpart ; } maxshift = innersize * 8 ; if ( isleftshift ) { if ( last_elt >= maxshift ) return 0 ; } else { if ( last_elt == 0 || last_elt > maxshift ) return 0 ; } if ( elementwidth ) * elementwidth = innersize * 8 ; if ( modconst ) * modconst = CONST_VECTOR_ELT ( op , 0 ) ; return 1 ; } </s>

Return TRUE if rtx OP is legal for use in a VSHR or VSHL instruction . If the immediate is valid , write a constant suitable for using as an operand to VSHR/VSHL to * MODCONST and the corresponding element width to * ELEMENTWIDTH . ISLEFTSHIFT is for determine left or right shift , because they have different limitations .


<s> bool SparcFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool ARMPassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( ) ) ; return false ; } </s>

This method should install a ( global ) instruction selector pass , which converts possibly generic instructions to fully target-specific instructions , thereby constraining all generic virtual registers to register classes .


<s> void setRoot ( CostLeaf * val ) { Root = val ; } </s>

Set the current root tag of the SelectionDAG .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; ST = & MF . getSubtarget < GCNSubtarget > ( ) ; if ( ! ST -> hasHardClauses ( ) ) return false ; const SIInstrInfo * SII = ST -> getInstrInfo ( ) ; const TargetRegisterInfo * TRI = ST -> getRegisterInfo ( ) ; bool Changed = false ; for ( auto & MBB : MF ) { ClauseInfo CI ; for ( auto & MI : MBB ) { HardClauseType Type = getHardClauseType ( MI ) ; int64_t Dummy1 ; bool Dummy2 ; unsigned Dummy3 ; SmallVector < const MachineOperand * , 4 > BaseOps ; if ( Type <= LAST_REAL_HARDCLAUSE_TYPE ) { if ( ! SII -> getMemOperandsWithOffsetWidth ( MI , BaseOps , Dummy1 , Dummy2 , Dummy3 , TRI ) ) { Type = HARDCLAUSE_ILLEGAL ; } } if ( CI . Length == 64 || ( CI . Length && Type != HARDCLAUSE_INTERNAL && ( Type != CI . Type || ! SII -> shouldClusterMemOps ( CI . BaseOps , BaseOps , 2 , 2 ) ) ) ) { Changed |= emitClause ( CI , SII ) ; CI = ClauseInfo ( ) ; } if ( CI . Length ) { ++ CI . Length ; if ( Type != HARDCLAUSE_INTERNAL ) { CI . Last = & MI ; CI . BaseOps = std :: move ( BaseOps ) ; } } else if ( Type <= LAST_REAL_HARDCLAUSE_TYPE ) { CI = ClauseInfo { Type , & MI , & MI , 1 , std :: move ( BaseOps ) } ; } } if ( CI . Length ) Changed |= emitClause ( CI , SII ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> TargetPassConfig * XCoreTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new XCorePassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> const uint32_t * TOYRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { return CC_Save_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


"iwmmxt requires an AAPCS compatible ABI for proper operation"

"iwmmxt abi requires an iwmmxt capable cpu"

"target CPU does not support interworking"

"AAPCS does not support %<-mcaller-super-interworking%>"

"AAPCS does not support %<-mcallee-super-interworking%>"

"target CPU does not support ARMv8-M Security Extensions"

"ARMv8-M Security Extensions incompatible with selected FPU"

"%<-mfloat-abi=hard%>: selected architecture lacks an FPU"

Perform some validation between the desired architecture and the rest of the options .


<s> bool nios2_emit_move_sequence ( rtx * operands , machine_mode mode ) { rtx to = operands [ 0 ] ; rtx from = operands [ 1 ] ; if ( ! register_operand ( to , mode ) && ! reg_or_0_operand ( from , mode ) ) { gcc_assert ( can_create_pseudo_p ( ) ) ; from = copy_to_mode_reg ( mode , from ) ; } if ( CONSTANT_P ( from ) ) { if ( CONST_INT_P ( from ) ) { if ( ! SMALL_INT ( INTVAL ( from ) ) && ! SMALL_INT_UNSIGNED ( INTVAL ( from ) ) && ! UPPER16_INT ( INTVAL ( from ) ) ) { HOST_WIDE_INT high = ( INTVAL ( from ) + 0x8000 ) & ~ 0xffff ; HOST_WIDE_INT low = INTVAL ( from ) & 0xffff ; emit_move_insn ( to , gen_int_mode ( high , SImode ) ) ; emit_insn ( gen_add2_insn ( to , gen_int_mode ( low , HImode ) ) ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , copy_rtx ( from ) ) ; return true ; } } else if ( gprel_constant_p ( from ) || r0rel_constant_p ( from ) ) ; else if ( nios2_large_constant_p ( from ) ) { if ( ! nios2_large_constant_allowed ( ) || nios2_large_unspec_reloc_p ( from ) ) { rtx lo = nios2_split_large_constant ( from , to ) ; emit_insn ( gen_rtx_SET ( to , lo ) ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , copy_rtx ( operands [ 1 ] ) ) ; return true ; } } else { from = nios2_legitimize_constant_address ( from ) ; if ( CONSTANT_P ( from ) ) { emit_insn ( gen_rtx_SET ( to , gen_rtx_HIGH ( Pmode , copy_rtx ( from ) ) ) ) ; emit_insn ( gen_rtx_SET ( to , gen_rtx_LO_SUM ( Pmode , to , from ) ) ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , copy_rtx ( operands [ 1 ] ) ) ; return true ; } } } operands [ 0 ] = to ; operands [ 1 ] = from ; return false ; } </s>


<s> TargetPassConfig * X86TargetMachine :: createPassConfig ( PassManagerBase & PM ) { X86PassConfig * PC = new X86PassConfig ( this , PM ) ; if ( X86EarlyIfConv && Subtarget . hasCMov ( ) ) PC -> enablePass ( & EarlyIfConverterID ) ; return PC ; } </s>


<s> bool ARMAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'a' : if ( MI -> getOperand ( OpNum ) . isReg ( ) ) { O << "[" << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << "]" ; return false ; } case 'c' : if ( ! MI -> getOperand ( OpNum ) . isImm ( ) ) return true ; printNoHashImmediate ( MI , OpNum , O ) ; return false ; case 'P' : case 'q' : printOperand ( MI , OpNum , O ) ; return false ; case 'Q' : if ( TM . getTargetData ( ) -> isLittleEndian ( ) ) break ; case 'R' : if ( TM . getTargetData ( ) -> isBigEndian ( ) ) break ; case 'H' : if ( ! MI -> getOperand ( OpNum ) . isReg ( ) || OpNum + 1 == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNum + 1 ) . isReg ( ) ) return true ; ++ OpNum ; } } printOperand ( MI , OpNum , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static void csky_conditional_register_usage ( void ) { if ( TARGET_MINI_REGISTERS ) { int i ; for ( i = ( CSKY_LAST_MINI_REGNUM + 1 ) ; i < 32 ; i ++ ) { fixed_regs [ i ] = 1 ; call_used_regs [ i ] = 1 ; call_really_used_regs [ i ] = 1 ; } } else if ( CSKY_TARGET_ARCH ( CK802 ) || CSKY_TARGET_ARCH ( CK803 ) || ! TARGET_HIGH_REGISTERS ) { int i ; for ( i = CSKY_FIRST_HIGH_REGNUM ; i <= CSKY_LAST_HIGH_REGNUM ; i ++ ) { fixed_regs [ i ] = 1 ; call_used_regs [ i ] = 1 ; call_really_used_regs [ i ] = 1 ; } } if ( CSKY_TARGET_ARCH ( CK801 ) || CSKY_TARGET_ARCH ( CK802 ) ) { fixed_regs [ CSKY_LR_REGNUM ] = 1 ; call_used_regs [ CSKY_LR_REGNUM ] = 1 ; call_really_used_regs [ CSKY_LR_REGNUM ] = 0 ; } if ( ! TARGET_DSP ) { fixed_regs [ CSKY_HI_REGNUM ] = 1 ; call_used_regs [ CSKY_HI_REGNUM ] = 1 ; call_really_used_regs [ CSKY_HI_REGNUM ] = 1 ; fixed_regs [ CSKY_LO_REGNUM ] = 1 ; call_used_regs [ CSKY_LO_REGNUM ] = 1 ; call_really_used_regs [ CSKY_LO_REGNUM ] = 1 ; } if ( ! TARGET_HARD_FLOAT ) { int regno ; for ( regno = CSKY_FIRST_VFP_REGNUM ; regno <= CSKY_LAST_VFP_REGNUM ; regno ++ ) { fixed_regs [ regno ] = 1 ; call_used_regs [ regno ] = 1 ; call_really_used_regs [ regno ] = 1 ; } } if ( flag_pic ) { fixed_regs [ PIC_OFFSET_TABLE_REGNUM ] = 1 ; call_used_regs [ PIC_OFFSET_TABLE_REGNUM ] = 1 ; call_really_used_regs [ PIC_OFFSET_TABLE_REGNUM ] = 0 ; } } </s>

Implement TARGET_CONDITIONAL_REGISTER_USAGE . Conditionally modify five variables fixed_regs , call_used_regs , global_regs , reg_names , and reg_class_contents , to take into account any dependence of these register sets on target flags . CK801 has registers r0-r8 and r13-r15 . CK802 and CK803 have registers r0-r15 ( the `` low '' registers ) . Other cpus use registers r0-r31 with -mhigh-registers , otherwise also only r0-r15 . CK801 only has 16-bit instructions , most of which can only reference r0-r7 ( the `` mini '' registers ) . So we mark regs outside that range as fixed . -msmart can be used on other arch variants to force the same behavior because it results in smaller code size . TODO : investigate whether it 's beneficial to use r8-r13 as a spill class when TARGET_MINI_REGISTERS instead of making them unusable by the register allocator .


<s> rtx arm_stack_protect_tls_canary_mem ( bool reload ) { rtx tp = gen_reg_rtx ( SImode ) ; if ( reload ) emit_insn ( gen_reload_tp_hard ( tp ) ) ; else emit_insn ( gen_load_tp_hard ( tp ) ) ; rtx reg = gen_reg_rtx ( SImode ) ; rtx offset = GEN_INT ( arm_stack_protector_guard_offset ) ; emit_set_insn ( reg , gen_rtx_PLUS ( SImode , tp , offset ) ) ; return gen_rtx_MEM ( SImode , reg ) ; } </s>

Generate insns that produce the address of the stack canary


<s>
void
XCoreRegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected"
)
;
MachineInstr
&
MI
=
*
II
;
MachineOperand
&
FrameOp
=
MI
.
getOperand
(
FIOperandNum
)
;
int
FrameIndex
=
FrameOp
.
getIndex
(
)
;
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
const
XCoreInstrInfo
&
TII
=
*
static_cast
<
const
XCoreInstrInfo
*
>
(
MF
.
getTarget
(
)
.
getInstrInfo
(
)
)
;
const
TargetFrameLowering
*
TFI
=
MF
.
getTarget
(
)
.
getFrameLowering
(
)
;
int
Offset
=
MF
.
getFrameInfo
(
)
->
getObjectOffset
(
FrameIndex
)
;
int
StackSize
=
MF
.
getFrameInfo
(
)
->
getStackSize
(
)
;
DEBUG
(
errs
(
)
<<
"\nFunction         : "
<<
MF
.
getName
(
)
<<
"\n"
)
;
DEBUG
(
errs
(
)
<<
"<--------->\n"
)
;
DEBUG
(
MI
.
print
(
errs
(
)
)
)
;
DEBUG
(
errs
(
)
<<
"FrameIndex         : "
<<
FrameIndex
<<
"\n"
)
;
DEBUG
(
errs
(
)
<<
"FrameOffset        : "
<<
Offset
<<
"\n"
)
;
DEBUG
(
errs
(
)
<<
"StackSize          : "
<<
StackSize
<<
"\n"
)
;
Offset
+=
StackSize
;
unsigned
FrameReg
=
getFrameRegister
(
MF
)
;
if
(
MI
.
isDebugValue
(
)
)
{
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
)
;
return
;
}
Offset
+=
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
0
)
;
assert
(
Offset
%
4
==
0
&&
"Misaligned stack offset"
)
;
DEBUG
(
errs
(
)
<<
"Offset             : "
<<
Offset
<<
"\n"
<<
"<--------->\n"
)
;
Offset
/=
4
;
unsigned
Reg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
assert
(
XCore
::
GRRegsRegClass
.
contains
(
Reg
)
&&
"Unexpected register operand"
)
;
if
(
TFI
->
hasFP
(
MF
)
)
{
if
(
isImmUs
(
Offset
)
)
InsertFPImmInst
(
II
,
TII
,
Reg
,
FrameReg
,
Offset
)
;
else
InsertFPConstInst
(
II
,
TII
,
Reg
,
FrameReg
,
Offset
,
RS
)
;
}
else
{
if
(
isImmU16
(
Offset
)
)
InsertSPImmInst
(
II
,
TII
,
Reg
,
Offset
)
;
else
InsertSPConstInst
(
II
,
TII
,
Reg
,
Offset
,
RS
)
;
}
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
MBB
.
erase
(
II
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .

XCore
XCore
0
"Unexpected"
XCore
XCore
"\nFunction         : "
"\n"
"<--------->\n"
"FrameIndex         : "
"\n"
"FrameOffset        : "
"\n"
"StackSize          : "
"\n"
1
1
1
0
4
0
"Misaligned stack offset"
"Offset             : "
"\n"
"<--------->\n"
4
0
XCore::GRRegsRegClass
"Unexpected register operand"


<s> void TOYInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , get ( TOY :: STORErr ) ) . addReg ( SrcReg ) . addFrameIndex ( FI ) . addReg ( TOY :: ZERO ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool runOnMachineFunction ( MachineFunction & F ) { bool Changed = false ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; return Changed ; } </s>


<s> std :: pair < unsigned , const TargetRegisterClass * > ARMTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'l' : case 'r' : return std :: make_pair ( 0U , ARM :: GPRRegisterClass ) ; case 'w' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , ARM :: SPRRegisterClass ) ; if ( VT == MVT :: f64 ) return std :: make_pair ( 0U , ARM :: DPRRegisterClass ) ; break ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> bool WebAssemblyPassConfig :: addInstSelector ( ) { ( void ) TargetPassConfig :: addInstSelector ( ) ; addPass ( createWebAssemblyISelDag ( getWebAssemblyTargetMachine ( ) , getOptLevel ( ) ) ) ; addPass ( createWebAssemblyArgumentMove ( ) ) ; addPass ( createWebAssemblySetP2AlignOperands ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .

WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly


<s> static bool classof ( const VEMCExpr * ) { return true ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> unsigned HexagonTTIImpl :: getNumberOfRegisters ( bool Vector ) const { if ( Vector ) return useHVX ( ) ? 32 : 0 ; return 32 ; } </s>


<s> unsigned X86InstrInfo :: getPartialRegUpdateClearance ( const MachineInstr & MI , unsigned OpNum , const TargetRegisterInfo * TRI ) const { if ( OpNum != 0 || ! hasPartialRegUpdate ( MI . getOpcode ( ) , Subtarget ) ) return 0 ; const MachineOperand & MO = MI . getOperand ( 0 ) ; Register Reg = MO . getReg ( ) ; if ( Reg . isVirtual ( ) ) { if ( MO . readsReg ( ) || MI . readsVirtualRegister ( Reg ) ) return 0 ; } else { if ( MI . readsRegister ( Reg , TRI ) ) return 0 ; } return PartialRegUpdateClearance ; } </s>

Inform the BreakFalseDeps pass how many idle instructions we would like before a partial register update .


<s> bool RISCVInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { switch ( MI -> getOpcode ( ) ) { default : return false ; } } </s>

This function is called for all pseudo instructions that remain after register allocation .


"WebAssembly doesn't support non-C calling conventions"

"WebAssembly hasn't implemented inalloca arguments"

"WebAssembly hasn't implemented nest arguments"

"WebAssembly hasn't implemented cons regs arguments"

"WebAssembly hasn't implemented cons regs last arguments"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> static void mips_reorg ( void ) { if ( TARGET_MIPS16 ) mips16_lay_out_constants ( ) ; else if ( TARGET_EXPLICIT_RELOCS ) { if ( mips_flag_delayed_branch ) dbr_schedule ( get_insns ( ) , dump_file ) ; mips_avoid_hazards ( ) ; if ( TUNE_MIPS4130 && TARGET_VR4130_ALIGN ) vr4130_align_insns ( ) ; } } </s>


<s> static void detect_l2_cache ( struct cache_desc * level2 ) { unsigned eax , ebx , ecx , edx ; unsigned assoc ; __cpuid ( 0x80000006 , eax , ebx , ecx , edx ) ; level2 -> sizekb = ( ecx >> 16 ) & 0xffff ; level2 -> line = ecx & 0xff ; assoc = ( ecx >> 12 ) & 0xf ; if ( assoc == 6 ) assoc = 8 ; else if ( assoc == 8 ) assoc = 16 ; else if ( assoc >= 0xa && assoc <= 0xc ) assoc = 32 + ( assoc - 0xa ) * 16 ; else if ( assoc >= 0xd && assoc <= 0xe ) assoc = 96 + ( assoc - 0xd ) * 32 ; level2 -> assoc = assoc ; } </s>

Detect L2 cache parameters using CPUID extended function 0x80000006 .


<s>
SDValue
MSP430TargetLowering
::
LowerCall
(
SDValue
Chain
,
SDValue
Callee
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
bool
doesNotRet
,
bool
&
isTailCall
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
OutVals
,
Ins
,
dl
,
DAG
,
InVals
)
;
case
CallingConv
::
MSP430_INTR
:
report_fatal_error
(
"ISRs cannot be called directly"
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .


<s> static unsigned int mips_autovectorize_vector_sizes ( void ) { return ISA_HAS_MSA ? 16 : 0 ; } </s>


<s>
static
unsigned
getScalarSizeInBits
(
Type
*
Ty
)
{
unsigned
Size
=
(
Ty
->
isPtrOrPtrVectorTy
(
)
64U
:
Ty
->
getScalarSizeInBits
(
)
)
;
assert
(
Size
>
0
&&
"Element must have non-zero size."
)
;
return
Size
;
}
</s>

If this is a vector type , return the getPrimitiveSizeInBits value for the element type .


<s> bool runOnMachineFunction ( MachineFunction & F ) override { AArch64FI = F . getInfo < AArch64FunctionInfo > ( ) ; STI = static_cast < const AArch64Subtarget * > ( & F . getSubtarget ( ) ) ; return AsmPrinter :: runOnMachineFunction ( F ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool MSP430TargetLowering :: isZExtFree ( EVT VT1 , EVT VT2 ) const { return false && VT1 == MVT :: i8 && VT2 == MVT :: i16 ; } </s>

Return true if zero-extending the specific node Val to type VT2 is free ( either because it 's implicitly zero-extended such as ARM ldrb / ldrh or because it 's folded such as X86 zero-extending loads ) .


<s> unsigned int compute_a_shift_length ( rtx insn ATTRIBUTE_UNUSED , rtx * operands ) { rtx shift = operands [ 3 ] ; enum machine_mode mode = GET_MODE ( shift ) ; enum rtx_code code = GET_CODE ( shift ) ; enum shift_type shift_type ; enum shift_mode shift_mode ; struct shift_info info ; unsigned int wlength = 0 ; switch ( mode ) { case QImode : shift_mode = QIshift ; break ; case HImode : shift_mode = HIshift ; break ; case SImode : shift_mode = SIshift ; break ; default : gcc_unreachable ( ) ; } switch ( code ) { case ASHIFTRT : shift_type = SHIFT_ASHIFTRT ; break ; case LSHIFTRT : shift_type = SHIFT_LSHIFTRT ; break ; case ASHIFT : shift_type = SHIFT_ASHIFT ; break ; default : gcc_unreachable ( ) ; } if ( GET_CODE ( operands [ 2 ] ) != CONST_INT ) { get_shift_alg ( shift_type , shift_mode , 1 , & info ) ; return ( 4 + h8300_asm_insn_count ( info . shift1 ) ) * 2 ; } else { int n = INTVAL ( operands [ 2 ] ) ; if ( n < 0 ) n = 0 ; else if ( ( unsigned int ) n > GET_MODE_BITSIZE ( mode ) ) n = GET_MODE_BITSIZE ( mode ) ; get_shift_alg ( shift_type , shift_mode , n , & info ) ; switch ( info . alg ) { case SHIFT_SPECIAL : wlength += h8300_asm_insn_count ( info . special ) ; if ( strstr ( info . special , "xor.l" ) != NULL ) wlength ++ ; case SHIFT_INLINE : n = info . remainder ; if ( info . shift2 != NULL ) { wlength += h8300_asm_insn_count ( info . shift2 ) * ( n / 2 ) ; n = n % 2 ; } wlength += h8300_asm_insn_count ( info . shift1 ) * n ; return 2 * wlength ; case SHIFT_ROT_AND : { int m = GET_MODE_BITSIZE ( mode ) - n ; gcc_assert ( info . shift1 ) ; if ( info . shift2 != NULL ) { wlength += h8300_asm_insn_count ( info . shift2 ) * ( m / 2 ) ; m = m % 2 ; } wlength += h8300_asm_insn_count ( info . shift1 ) * m ; switch ( mode ) { case QImode : wlength += 1 ; break ; case HImode : wlength += 2 ; break ; case SImode : gcc_assert ( ! TARGET_H8300 ) ; wlength += 3 ; break ; default : gcc_unreachable ( ) ; } return 2 * wlength ; } case SHIFT_LOOP : if ( info . shift2 != NULL ) { wlength += 3 + h8300_asm_insn_count ( info . shift2 ) ; if ( n % 2 ) wlength += h8300_asm_insn_count ( info . shift1 ) ; } else { wlength += 3 + h8300_asm_insn_count ( info . shift1 ) ; } return 2 * wlength ; default : gcc_unreachable ( ) ; } } } </s>


<s> void Reset ( ) { Ops . clear ( ) ; OpBegins . clear ( ) ; OpBegins . push_back ( 0 ) ; HasPersonality = 0 ; } </s>


<s>
ScheduleHazardRecognizer
*
PPCInstrInfo
::
CreateTargetPostRAHazardRecognizer
(
const
InstrItineraryData
*
II
,
const
ScheduleDAG
*
DAG
)
const
{
unsigned
Directive
=
TM
.
getSubtarget
<
PPCSubtarget
>
(
)
.
getDarwinDirective
(
)
;
if
(
Directive
!=
PPC
::
DIR_440
&&
Directive
!=
PPC
::
DIR_A2
&&
Directive
!=
PPC
::
DIR_E500mc
&&
Directive
!=
PPC
::
DIR_E5500
)
{
const
TargetInstrInfo
*
TII
=
TM
.
getInstrInfo
(
)
;
assert
(
TII
&&
"No InstrInfo?"
)
;
return
new
PPCHazardRecognizer970
(
*
TII
)
;
}
return
new
PPCScoreboardHazardRecognizer
(
II
,
DAG
)
;
}
</s>

Allocate and return a hazard recognizer to use for by non-scheduling passes .


<s> static void s390_regs_ever_clobbered ( char regs_ever_clobbered [ ] ) { basic_block cur_bb ; rtx_insn * cur_insn ; unsigned int i ; memset ( regs_ever_clobbered , 0 , 32 ) ; if ( ! crtl -> is_leaf ) { for ( i = 0 ; i < 32 ; i ++ ) regs_ever_clobbered [ i ] = call_used_regs [ i ] ; } if ( crtl -> calls_eh_return || cfun -> machine -> has_landing_pad_p ) for ( i = 0 ; EH_RETURN_DATA_REGNO ( i ) != INVALID_REGNUM ; i ++ ) if ( crtl -> calls_eh_return || ( cfun -> machine -> has_landing_pad_p && df_regs_ever_live_p ( EH_RETURN_DATA_REGNO ( i ) ) ) ) regs_ever_clobbered [ EH_RETURN_DATA_REGNO ( i ) ] = 1 ; if ( crtl -> saves_all_registers ) for ( i = 0 ; i < 32 ; i ++ ) if ( ! call_used_regs [ i ] ) regs_ever_clobbered [ i ] = 1 ; FOR_EACH_BB_FN ( cur_bb , cfun ) { FOR_BB_INSNS ( cur_bb , cur_insn ) { rtx pat ; if ( ! INSN_P ( cur_insn ) ) continue ; pat = PATTERN ( cur_insn ) ; if ( epilogue_completed && RTX_FRAME_RELATED_P ( cur_insn ) ) { if ( GET_CODE ( pat ) == SET && GENERAL_REG_P ( SET_DEST ( pat ) ) ) { if ( GET_MODE ( SET_SRC ( pat ) ) == DImode && FP_REG_P ( SET_SRC ( pat ) ) ) continue ; if ( GET_CODE ( SET_SRC ( pat ) ) == MEM ) continue ; } if ( GET_CODE ( pat ) == PARALLEL && load_multiple_operation ( pat , VOIDmode ) ) continue ; } note_stores ( cur_insn , s390_reg_clobbered_rtx , regs_ever_clobbered ) ; } } } </s>

Walks through all basic blocks of the current function looking for clobbered hard regs using s390_reg_clobbered_rtx . The fields of the passed integer array REGS_EVER_CLOBBERED are set to one for each of those regs .


<s> bool nds32_tls_referenced_p ( rtx x ) { if ( ! targetm . have_tls ) return false ; if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS ) x = XEXP ( XEXP ( x , 0 ) , 0 ) ; if ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) ) return true ; return false ; } </s>

Return true if X contains a thread-local symbol .


<s> bool ARMCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const { auto & TLI = * getTLI < ARMTargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb1Only ( ) ) return false ; if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; const auto & DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasPassPointeeByValueCopyAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; OutgoingValueAssigner ArgAssigner ( AssignFn ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) ) ; SmallVector < ArgInfo , 8 > SplitArgInfos ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArgInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArgInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArgInfo , SplitArgInfos , DL , F . getCallingConv ( ) ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; if ( ! determineAndHandleAssignments ( ArgHandler , ArgAssigner , SplitArgInfos , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> void Mips16FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( STI . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( StackSize == 0 && ! MFI . adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; TII . makeFrame ( Mips :: SP , StackSize , MBB , MBBI ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , StackSize ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; if ( ! CSI . empty ( ) ) { const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( const CalleeSavedInfo & I : CSI ) { int64_t Offset = MFI . getObjectOffset ( I . getFrameIdx ( ) ) ; unsigned Reg = I . getReg ( ) ; unsigned DReg = MRI -> getDwarfRegNum ( Reg , true ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DReg , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: MoveR3216 ) , Mips :: S0 ) . addReg ( Mips :: SP ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Mips Mips Mips Mips 0 Mips::SP Mips::MoveR3216 Mips::S0 Mips::SP


<s> bool enableSubRegLiveness ( ) const override { return true ; } </s>

Enable tracking of subregister liveness in register allocator .


<s>
void
xstormy16_output_addr_vec
(
FILE
*
file
,
rtx
label
ATTRIBUTE_UNUSED
,
rtx
table
)
{
int
vlen
,
idx
;
current_function_section
(
current_function_decl
)
;
vlen
=
XVECLEN
(
table
,
0
)
;
for
(
idx
=
0
;
idx
<
vlen
;
idx
++
)
{
fputs
(
"\tjmpf "
,
file
)
;
output_asm_label
(
XEXP
(
XVECEXP
(
table
,
0
,
idx
)
,
0
)
)
;
fputc
(
'\n'
,
file
)
;
}
}
</s>

Output an ADDR_VEC . It is output as a sequence of 'jmpf ' instructions , without label or alignment or any other special constructs . We know that the previous instruction will be the ` tablejump_pcrel ' output above . TODO : it might be nice to output 'br ' instructions if they could all reach .


<s> void X86InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Alignment = std :: max < uint32_t > ( RC -> getSize ( ) , 16 ) ; bool isAligned = ( MF . getTarget ( ) . getSubtargetImpl ( ) -> getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , Subtarget ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) , DestReg ) , FrameIdx ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


Do one-time initialization of COSTS given that we 're costing the loop vectorization described by LOOP_VINFO .


<s> static bool cris_rtx_costs ( rtx x , int code , int outer_code , int * total ) { switch ( code ) { case CONST_INT : { HOST_WIDE_INT val = INTVAL ( x ) ; if ( val == 0 ) * total = 0 ; else if ( val < 32 && val >= - 32 ) * total = 1 ; else if ( val <= 32767 && val >= - 32768 ) * total = 2 ; else * total = 4 ; return true ; } case LABEL_REF : * total = 6 ; return true ; case CONST : case SYMBOL_REF : * total = 6 ; return true ; case CONST_DOUBLE : if ( x != CONST0_RTX ( GET_MODE ( x ) == VOIDmode ? DImode : GET_MODE ( x ) ) ) * total = 12 ; else * total = 0 ; return true ; case MULT : if ( GET_CODE ( XEXP ( x , 1 ) ) != CONST_INT || exact_log2 ( INTVAL ( XEXP ( x , 1 ) ) < 0 ) ) { if ( TARGET_HAS_MUL_INSNS ) { * total = COSTS_N_INSNS ( 1 ) + COSTS_N_INSNS ( 1 ) / 2 ; return true ; } * total = COSTS_N_INSNS ( 132 ) ; return true ; } return false ; case UDIV : case MOD : case UMOD : case DIV : if ( GET_CODE ( XEXP ( x , 1 ) ) != CONST_INT || exact_log2 ( INTVAL ( XEXP ( x , 1 ) ) < 0 ) ) { * total = COSTS_N_INSNS ( 260 ) ; return true ; } return false ; case AND : if ( GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT && GET_CODE ( XEXP ( x , 0 ) ) != CONST_INT && ! CONST_OK_FOR_LETTER_P ( INTVAL ( XEXP ( x , 1 ) ) , 'I' ) ) { * total = ( rtx_cost ( XEXP ( x , 0 ) , outer_code ) + 2 + 2 * GET_MODE_NUNITS ( GET_MODE ( XEXP ( x , 0 ) ) ) ) ; return true ; } return false ; case ZERO_EXTEND : case SIGN_EXTEND : * total = rtx_cost ( XEXP ( x , 0 ) , outer_code ) ; return true ; default : return false ; } } </s>

Compute a ( partial ) cost for rtx X . Return true if the complete cost has been computed , and false if subexpressions should be scanned . In either case , * TOTAL contains the cost result .


<s> static rtx frv_expand_int_void2arg ( enum insn_code icode , tree arglist ) { rtx pat ; rtx op0 = frv_read_argument ( & arglist ) ; rtx op1 = frv_read_argument ( & arglist ) ; op0 = frv_legitimize_argument ( icode , 1 , op0 ) ; op1 = frv_legitimize_argument ( icode , 1 , op1 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return NULL_RTX ; } </s>

Expand builtins that take two long operands and return void .


<s> rtx alpha_use_linkage ( rtx linkage ATTRIBUTE_UNUSED , tree cfundecl ATTRIBUTE_UNUSED , int lflag ATTRIBUTE_UNUSED , int rflag ATTRIBUTE_UNUSED ) { return NULL_RTX ; } </s>

Return a SYMBOL_REF representing the reference to the .linkage entry of function FUNC built for calls made from CFUNDECL . LFLAG is 1 if this is the reference to the linkage pointer value , 0 if this is the reference to the function entry value . RFLAG is 1 if this a reduced reference ( code address only ) , 0 if this is a full reference .


<s> bool MipsRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MipsSubtarget & Subtarget = MF . getSubtarget < MipsSubtarget > ( ) ; unsigned FP = Subtarget . isGP32bit ( ) ? Mips :: FP : Mips :: FP_64 ; unsigned BP = Subtarget . isGP32bit ( ) ? Mips :: S7 : Mips :: S7_64 ; if ( ! Subtarget . hasStandardEncoding ( ) ) return false ; if ( ! MF . getRegInfo ( ) . canReserveReg ( FP ) ) return false ; if ( Subtarget . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) ) return true ; return MF . getRegInfo ( ) . canReserveReg ( BP ) ; } </s>

True if the stack can be realigned for the target .


<s> bool AMDGPUPromoteAlloca :: doInitialization ( Module & M ) { if ( ! TM ) return false ; Mod = & M ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> int mmix_opposite_regno ( int regno , int incoming ) { if ( incoming && regno == MMIX_OUTGOING_RETURN_VALUE_REGNUM ) return MMIX_RETURN_VALUE_REGNUM ; if ( ! incoming && regno == MMIX_RETURN_VALUE_REGNUM ) return MMIX_OUTGOING_RETURN_VALUE_REGNUM ; if ( ! mmix_function_arg_regno_p ( regno , incoming ) ) return regno ; return regno - ( incoming ? MMIX_FIRST_INCOMING_ARG_REGNUM - MMIX_FIRST_ARG_REGNUM : MMIX_FIRST_ARG_REGNUM - MMIX_FIRST_INCOMING_ARG_REGNUM ) ; } </s>

INCOMING_REGNO and OUTGOING_REGNO worker function . Those two macros must only be applied to function argument registers and the function return value register for the opposite use . FIXME : for their current use in gcc , it 'd be better with an explicit specific additional FUNCTION_INCOMING_ARG_REGNO_P a'la TARGET_FUNCTION_ARG / TARGET_FUNCTION_INCOMING_ARG instead of forcing the target to commit to a fixed mapping and for any unspecified register use . Particularly when thinking about the return-value , it is better to imagine INCOMING_REGNO and OUTGOING_REGNO as named CALLEE_TO_CALLER_REGNO and INNER_REGNO as named CALLER_TO_CALLEE_REGNO because the direction . The `` incoming '' and `` outgoing '' is from the perspective of the parameter-registers , but the same macro is ( must be , lacking an alternative like suggested above ) used to map the return-value-register from the same perspective . To make directions even more confusing , the macro MMIX_OUTGOING_RETURN_VALUE_REGNUM holds the number of the register in which to return a value , i.e . INCOMING_REGNO for the return-value- register as received from a called function ; the return-value on the way out .


<s> static rtx_insn * frame_emit_store ( int regno , rtx addr , HOST_WIDE_INT offset ) { rtx reg = gen_rtx_REG ( V4SImode , regno ) ; rtx mem = gen_frame_mem ( V4SImode , gen_rtx_PLUS ( Pmode , addr , GEN_INT ( offset ) ) ) ; return emit_insn ( gen_movv4si ( mem , reg ) ) ; } </s>

Emit a store in the stack frame to save REGNO at address ADDR , and emit the corresponding REG_CFA_OFFSET note described by CFA and CFA_OFFSET . Return the emitted insn .


"Stack realignment in presence of dynamic allocas is "

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static bool i386_asm_output_addr_const_extra ( FILE * file , rtx x ) { rtx op ; if ( GET_CODE ( x ) != UNSPEC ) return false ; op = XVECEXP ( x , 0 , 0 ) ; switch ( XINT ( x , 1 ) ) { case UNSPEC_GOTOFF : output_addr_const ( file , op ) ; fputs ( "@gotoff" , file ) ; break ; case UNSPEC_GOTTPOFF : output_addr_const ( file , op ) ; fputs ( "@gottpoff" , file ) ; break ; case UNSPEC_TPOFF : output_addr_const ( file , op ) ; fputs ( "@tpoff" , file ) ; break ; case UNSPEC_NTPOFF : output_addr_const ( file , op ) ; if ( TARGET_64BIT ) fputs ( "@tpoff" , file ) ; else fputs ( "@ntpoff" , file ) ; break ; case UNSPEC_DTPOFF : output_addr_const ( file , op ) ; fputs ( "@dtpoff" , file ) ; break ; case UNSPEC_GOTNTPOFF : output_addr_const ( file , op ) ; if ( TARGET_64BIT ) fputs ( ASSEMBLER_DIALECT == ASM_ATT ? "@gottpoff(%rip)" : "@gottpoff[rip]" , file ) ; else fputs ( "@gotntpoff" , file ) ; break ; case UNSPEC_INDNTPOFF : output_addr_const ( file , op ) ; fputs ( "@indntpoff" , file ) ; break ; case UNSPEC_MACHOPIC_OFFSET : output_addr_const ( file , op ) ; putc ( '-' , file ) ; machopic_output_function_base_name ( file ) ; break ; default : return false ; } return true ; } </s>

Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA .


<s> unsigned int sparc_regmode_natural_size ( machine_mode mode ) { const enum mode_class cl = GET_MODE_CLASS ( mode ) ; if ( ( cl == MODE_FLOAT || cl == MODE_VECTOR_INT ) && GET_MODE_SIZE ( mode ) <= 4 ) return 4 ; return UNITS_PER_WORD ; } </s>

On the SPARC , any mode which naturally allocates into the single float registers should return 4 here .


<s>
bool
SystemZRegisterInfo
::
shouldCoalesce
(
MachineInstr
*
MI
,
const
TargetRegisterClass
*
SrcRC
,
unsigned
SubReg
,
const
TargetRegisterClass
*
DstRC
,
unsigned
DstSubReg
,
const
TargetRegisterClass
*
NewRC
,
LiveIntervals
&
LIS
)
const
{
assert
(
MI
->
isCopy
(
)
&&
"Only expecting COPY instructions"
)
;
if
(
!
(
NewRC
->
hasSuperClassEq
(
&
SystemZ
::
GR128BitRegClass
)
&&
(
getRegSizeInBits
(
*
SrcRC
)
<=
64
||
getRegSizeInBits
(
*
DstRC
)
<=
64
)
)
)
return
true
;
unsigned
WideOpNo
=
(
getRegSizeInBits
(
*
SrcRC
)
==
128
1
:
0
)
;
unsigned
GR128Reg
=
MI
->
getOperand
(
WideOpNo
)
.
getReg
(
)
;
unsigned
GRNarReg
=
MI
->
getOperand
(
(
WideOpNo
==
1
)
0
:
1
)
.
getReg
(
)
;
LiveInterval
&
IntGR128
=
LIS
.
getInterval
(
GR128Reg
)
;
LiveInterval
&
IntGRNar
=
LIS
.
getInterval
(
GRNarReg
)
;
MachineBasicBlock
*
MBB
=
MI
->
getParent
(
)
;
MachineInstr
*
FirstMI_GR128
=
LIS
.
getInstructionFromIndex
(
IntGR128
.
beginIndex
(
)
)
;
MachineInstr
*
FirstMI_GRNar
=
LIS
.
getInstructionFromIndex
(
IntGRNar
.
beginIndex
(
)
)
;
MachineInstr
*
LastMI_GR128
=
LIS
.
getInstructionFromIndex
(
IntGR128
.
endIndex
(
)
)
;
MachineInstr
*
LastMI_GRNar
=
LIS
.
getInstructionFromIndex
(
IntGRNar
.
endIndex
(
)
)
;
if
(
(
!
FirstMI_GR128
||
FirstMI_GR128
->
getParent
(
)
!=
MBB
)
||
(
!
FirstMI_GRNar
||
FirstMI_GRNar
->
getParent
(
)
!=
MBB
)
||
(
!
LastMI_GR128
||
LastMI_GR128
->
getParent
(
)
!=
MBB
)
||
(
!
LastMI_GRNar
||
LastMI_GRNar
->
getParent
(
)
!=
MBB
)
)
return
false
;
MachineBasicBlock
::
iterator
MII
=
nullptr
,
MEE
=
nullptr
;
if
(
WideOpNo
==
1
)
{
MII
=
FirstMI_GR128
;
MEE
=
LastMI_GRNar
;
}
else
{
MII
=
FirstMI_GRNar
;
MEE
=
LastMI_GR128
;
}
BitVector
PhysClobbered
(
getNumRegs
(
)
)
;
MEE
++
;
for
(
;
MII
!=
MEE
;
++
MII
)
{
for
(
const
MachineOperand
&
MO
:
MII
->
operands
(
)
)
if
(
MO
.
isReg
(
)
&&
isPhysicalRegister
(
MO
.
getReg
(
)
)
)
{
for
(
MCSuperRegIterator
SI
(
MO
.
getReg
(
)
,
this
,
true
)
;
SI
.
isValid
(
)
;
++
SI
)
if
(
NewRC
->
contains
(
*
SI
)
)
{
PhysClobbered
.
set
(
*
SI
)
;
break
;
}
}
}
unsigned
const
DemandedFreeGR128
=
3
;
if
(
PhysClobbered
.
count
(
)
>
(
NewRC
->
getNumRegs
(
)
DemandedFreeGR128
)
)
return
false
;
return
true
;
}
</s>


<s> void init_cumulative_args ( CUMULATIVE_ARGS * cum , tree fntype , rtx libname ATTRIBUTE_UNUSED ) { static CUMULATIVE_ARGS zero_cum ; * cum = zero_cum ; cum -> nregs = max_arg_registers ; cum -> arg_regs = arg_regs ; cum -> call_cookie = CALL_NORMAL ; if ( fntype && lookup_attribute ( "shortcall" , TYPE_ATTRIBUTES ( fntype ) ) ) cum -> call_cookie |= CALL_SHORT ; else if ( fntype && lookup_attribute ( "longcall" , TYPE_ATTRIBUTES ( fntype ) ) ) cum -> call_cookie |= CALL_LONG ; return ; } </s>

Handle the INIT_CUMULATIVE_ARGS macro . Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is 0 .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addRequiredID ( PHIEliminationID ) ; AU . addRequiredID ( TwoAddressInstructionPassID ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static char * aarch64_offload_options ( void ) { if ( TARGET_ILP32 ) return xstrdup ( "-foffload-abi=ilp32" ) ; else return xstrdup ( "-foffload-abi=lp64" ) ; } </s>

Implement the TARGET_OFFLOAD_OPTIONS hook .


<s> bool hasMFence ( ) const { return hasSSE2 ( ) || is64Bit ( ) ; } </s>

Use mfence if we have SSE2 or we 're on x86-64 ( even if we asked for no-sse2 ) .


<s> bool X86TargetLowering :: isVectorClearMaskLegal ( const SmallVectorImpl < int > & Mask , EVT VT ) const { unsigned NumElts = VT . getVectorNumElements ( ) ; if ( NumElts == 2 ) return true ; if ( NumElts == 4 && VT . getSizeInBits ( ) == 128 ) { return ( isMOVLMask ( Mask , VT ) || isCommutedMOVLMask ( Mask , VT , true ) || isSHUFPMask ( Mask , VT ) || isCommutedSHUFPMask ( Mask , VT ) ) ; } return false ; } </s>


<s> bool isReg ( ) const override { return Kind == k_Register ; } </s>


<s> bool ARMTargetLowering :: preferIncOfAddToSubOfNot ( EVT VT ) const { if ( ! Subtarget -> hasNEON ( ) ) { if ( Subtarget -> isThumb1Only ( ) ) return VT . getScalarSizeInBits ( ) <= 32 ; return true ; } return VT . isScalarInteger ( ) ; } </s>

These two forms are equivalent : sub y , ( xor x , -1 ) add ( add x , 1 ) , y The variant with two add 's is IR-canonical .


<s>
void
BlackfinInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
=
I
!=
MBB
.
end
(
)
I
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
if
(
inClass
(
BF
::
DPRegClass
,
DestReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
LOAD32fi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
if
(
inClass
(
BF
::
D16RegClass
,
DestReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
LOAD16fi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
if
(
inClass
(
BF
::
AnyCCRegClass
,
DestReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
LOAD8fi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
llvm_unreachable
(
"Cannot load regclass from stack slot"
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


"Unknown opcode to check as cheap as a move!"

Return true if the instruction is as cheap as a move instruction .


"\n******** JVM Offset allocation ********\n"

runOnMachineFunction - Emit the function body .


<s> static rtx sparc_function_arg_1 ( cumulative_args_t cum_v , const function_arg_info & arg , bool incoming ) { const CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; const int regbase = incoming ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST ; int slotno , regno , padding ; tree type = arg . type ; machine_mode mode = arg . mode ; enum mode_class mclass = GET_MODE_CLASS ( mode ) ; bool named = arg . named ; slotno = function_arg_slotno ( cum , mode , type , named , incoming , & regno , & padding ) ; if ( slotno == - 1 ) return 0 ; if ( type && VECTOR_INTEGER_TYPE_P ( type ) ) mclass = MODE_FLOAT ; if ( TARGET_ARCH32 ) return gen_rtx_REG ( mode , regno ) ; if ( type && TREE_CODE ( type ) == RECORD_TYPE ) { const int size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; return function_arg_record_value ( type , mode , slotno , named , regbase ) ; } else if ( type && TREE_CODE ( type ) == UNION_TYPE ) { const int size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; return function_arg_union_value ( size , mode , slotno , regno ) ; } else if ( type && VECTOR_TYPE_P ( type ) && mode == BLKmode ) { const int size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; return function_arg_vector_value ( size , slotno , named , regno ) ; } else if ( ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) && SPARC_FP_REG_P ( regno ) ) { rtx reg = gen_rtx_REG ( mode , regno ) ; if ( cum -> prototype_p || cum -> libcall_p ) return reg ; else { rtx v0 , v1 ; if ( ( regno - SPARC_FP_ARG_FIRST ) < SPARC_INT_ARG_MAX * 2 ) { int intreg ; if ( incoming ) return reg ; intreg = ( SPARC_OUTGOING_INT_ARG_FIRST + ( regno - SPARC_FP_ARG_FIRST ) / 2 ) ; v0 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , intreg ) , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , v0 , v1 ) ) ; } else { v0 = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , v0 , v1 ) ) ; } } } else if ( type && AGGREGATE_TYPE_P ( type ) ) { const int size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; mode = int_mode_for_size ( size * BITS_PER_UNIT , 0 ) . else_blk ( ) ; } return gen_rtx_REG ( mode , regno ) ; } </s>

Determine where to put an argument to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . NAMED is true if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . INCOMING_P is false for TARGET_FUNCTION_ARG , true for TARGET_FUNCTION_INCOMING_ARG .


<s> unsigned X86FrameLowering :: getWinEHFuncletFrameSize ( const MachineFunction & MF ) const { unsigned CSSize = MF . getInfo < X86MachineFunctionInfo > ( ) -> getCalleeSavedFrameSize ( ) ; unsigned UsedSize ; EHPersonality Personality = classifyEHPersonality ( MF . getFunction ( ) . getPersonalityFn ( ) ) ; if ( Personality == EHPersonality :: CoreCLR ) { UsedSize = getPSPSlotOffsetFromSP ( MF ) + SlotSize ; } else { UsedSize = MF . getFrameInfo ( ) . getMaxCallFrameSize ( ) ; } unsigned FrameSizeMinusRBP = alignTo ( CSSize + UsedSize , getStackAlignment ( ) ) ; return FrameSizeMinusRBP - CSSize ; } </s>

Funclets only need to account for space for the callee saved registers , as the locals are accounted for in the parent 's stack frame .


<s> static tree sparc_builtin_decl ( unsigned code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= SPARC_BUILTIN_MAX ) return error_mark_node ; return sparc_builtins [ code ] ; } </s>


<s> static void cris_function_arg_advance ( cumulative_args_t ca_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * ca = get_cumulative_args ( ca_v ) ; ca -> regs += ( 3 + CRIS_FUNCTION_ARG_SIZE ( arg . mode , arg . type ) ) / 4 ; } </s>

Worker function for TARGET_FUNCTION_ARG_ADVANCE .


<s> Register AArch64RegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , int FrameIdx , int64_t Offset ) const { MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; const AArch64InstrInfo * TII = MF . getSubtarget < AArch64Subtarget > ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII -> get ( AArch64 :: ADDXri ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; Register BaseReg = MRI . createVirtualRegister ( & AArch64 :: GPR64spRegClass ) ; MRI . constrainRegClass ( BaseReg , TII -> getRegClass ( MCID , 0 , this , MF ) ) ; unsigned Shifter = AArch64_AM :: getShifterImm ( AArch64_AM :: LSL , 0 ) ; BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) . addImm ( Shifter ) ; return BaseReg ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .


<s> void tool_cleanup ( bool from_signal ATTRIBUTE_UNUSED ) { if ( ptx_cfile_name ) maybe_unlink ( ptx_cfile_name ) ; if ( ptx_name ) maybe_unlink ( ptx_name ) ; if ( omp_requires_file ) maybe_unlink ( omp_requires_file ) ; } </s>


<s> bool HexagonInstrInfo :: SubsumesPredicate ( ArrayRef < MachineOperand > Pred1 , ArrayRef < MachineOperand > Pred2 ) const { return false ; } </s>

Returns true if the first specified predicate subsumes the second , e.g .


<s> SDValue MipsTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; unsigned Opc = N -> getOpcode ( ) ; switch ( Opc ) { default : break ; case ISD :: SDIVREM : case ISD :: UDIVREM : return performDivRemCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SELECT : return performSELECTCombine ( N , DAG , DCI , Subtarget ) ; case MipsISD :: CMovFP_F : case MipsISD :: CMovFP_T : return performCMovFPCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: AND : return performANDCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: OR : return performORCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: ADD : return performADDCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: AssertZext : return performAssertZextCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SHL : return performSHLCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SUB : return performSUBCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips Mips ISD::SDIVREM ISD::UDIVREM ISD::SELECT MipsISD::CMovFP_F MipsISD::CMovFP_T ISD::AND ISD::OR ISD::ADD ISD::AssertZext ISD::SHL ISD::SUB


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BRCOND : return LowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return LowerConstantPool ( Op , DAG ) ; case ISD :: DYNAMIC_STACKALLOC : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: BlockAddress : return LowerBlockAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return LowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( Op , DAG ) ; case ISD :: SELECT : return LowerSELECT ( Op , DAG ) ; case ISD :: SETCC : return LowerSETCC ( Op , DAG ) ; case ISD :: VASTART : return LowerVASTART ( Op , DAG ) ; case ISD :: FCOPYSIGN : return LowerFCOPYSIGN ( Op , DAG ) ; case ISD :: FABS : return LowerFABS ( Op , DAG ) ; case ISD :: FRAMEADDR : return LowerFRAMEADDR ( Op , DAG ) ; case ISD :: MEMBARRIER : return LowerMEMBARRIER ( Op , DAG ) ; case ISD :: ATOMIC_FENCE : return LowerATOMIC_FENCE ( Op , DAG ) ; case ISD :: SHL_PARTS : return LowerShiftLeftParts ( Op , DAG ) ; case ISD :: SRA_PARTS : return LowerShiftRightParts ( Op , DAG , true ) ; case ISD :: SRL_PARTS : return LowerShiftRightParts ( Op , DAG , false ) ; case ISD :: LOAD : return LowerLOAD ( Op , DAG ) ; case ISD :: STORE : return LowerSTORE ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::BRCOND ISD::ConstantPool ISD::DYNAMIC_STACKALLOC ISD::GlobalAddress ISD::BlockAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::SELECT ISD::SETCC ISD::VASTART ISD::FCOPYSIGN ISD::FABS ISD::FRAMEADDR ISD::MEMBARRIER ISD::ATOMIC_FENCE ISD::SHL_PARTS ISD::SRA_PARTS ISD::SRL_PARTS ISD::LOAD ISD::STORE


<s> Sched :: Preference PPCTargetLowering :: getSchedulingPreference ( SDNode * N ) const { if ( DisableILPPref || PPCSubTarget . enableMachineScheduler ( ) ) return TargetLowering :: getSchedulingPreference ( N ) ; return Sched :: ILP ; } </s>


"SIInstrInfo::storeRegToStackSlot - Do not know how to"

Store the specified register of the given register class to the specified stack frame index .


<s> bool AArch64TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( AM . BaseGV ) return false ; if ( AM . HasBaseReg && AM . BaseOffs && AM . Scale ) return false ; if ( Ty -> isVectorTy ( ) && Ty -> getVectorIsScalable ( ) ) return AM . HasBaseReg && ! AM . BaseOffs && ! AM . Scale ; uint64_t NumBytes = 0 ; if ( Ty -> isSized ( ) ) { uint64_t NumBits = DL . getTypeSizeInBits ( Ty ) ; NumBytes = NumBits / 8 ; if ( ! isPowerOf2_64 ( NumBits ) ) NumBytes = 0 ; } if ( ! AM . Scale ) { int64_t Offset = AM . BaseOffs ; if ( isInt < 9 > ( Offset ) ) return true ; unsigned shift = Log2_64 ( NumBytes ) ; if ( NumBytes && Offset > 0 && ( Offset / NumBytes ) <= ( 1LL << 12 ) - 1 && ( Offset >> shift ) << shift == Offset ) return true ; return false ; } return AM . Scale == 1 || ( AM . Scale > 0 && ( uint64_t ) AM . Scale == NumBytes ) ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> bool MipsTargetObjectFile :: IsConstantInSmallSection ( const Constant * CN , const TargetMachine & TM ) const { return ( TM . getSubtarget < MipsSubtarget > ( ) . useSmallSection ( ) && LocalSData && IsInSmallSection ( TM . getSubtargetImpl ( ) -> getDataLayout ( ) -> getTypeAllocSize ( CN -> getType ( ) ) ) ) ; } </s>

Return true if this constant should be placed into small data section .


<s> void AVRFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( hasFP ( MF ) ) { SavedRegs . set ( AVR :: R29R28 ) ; SavedRegs . set ( AVR :: R29 ) ; SavedRegs . set ( AVR :: R28 ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> static void aarch64_save_callee_saves ( machine_mode mode , HOST_WIDE_INT start_offset , unsigned start , unsigned limit , bool skip_wb ) { rtx_insn * insn ; rtx ( * gen_mem_ref ) ( machine_mode , rtx ) = ( frame_pointer_needed ? gen_frame_mem : gen_rtx_MEM ) ; unsigned regno ; unsigned regno2 ; for ( regno = aarch64_next_callee_save ( start , limit ) ; regno <= limit ; regno = aarch64_next_callee_save ( regno + 1 , limit ) ) { rtx reg , mem ; HOST_WIDE_INT offset ; if ( skip_wb && ( regno == cfun -> machine -> frame . wb_candidate1 || regno == cfun -> machine -> frame . wb_candidate2 ) ) continue ; reg = gen_rtx_REG ( mode , regno ) ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno ] ; mem = gen_mem_ref ( mode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; regno2 = aarch64_next_callee_save ( regno + 1 , limit ) ; if ( regno2 <= limit && ( ( cfun -> machine -> frame . reg_offset [ regno ] + UNITS_PER_WORD ) == cfun -> machine -> frame . reg_offset [ regno2 ] ) ) { rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; rtx mem2 ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno2 ] ; mem2 = gen_mem_ref ( mode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; insn = emit_insn ( aarch64_gen_store_pair ( mode , mem , reg , mem2 , reg2 ) ) ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , 0 , 1 ) ) = 1 ; regno = regno2 ; } else insn = emit_move_insn ( mem , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } </s>

Emit code to save the callee-saved registers from register number START to LIMIT to the stack at the location starting at offset START_OFFSET , skipping any write-back candidates if SKIP_WB is true .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
IMMEDIATE
:
OS
<<
"Imm: "
<<
getImm
(
)
<<
"\n"
;
break
;
case
TOKEN
:
OS
<<
"Token: "
<<
getToken
(
)
<<
"\n"
;
break
;
case
REGISTER
:
OS
<<
"Reg: %r"
<<
getReg
(
)
<<
"\n"
;
break
;
case
MEMORY_IMM
:
OS
<<
"MemImm: "
<<
*
getMemOffset
(
)
<<
"\n"
;
break
;
case
MEMORY_REG_IMM
:
OS
<<
"MemRegImm: "
<<
getMemBaseReg
(
)
<<
"+"
<<
*
getMemOffset
(
)
<<
"\n"
;
break
;
case
MEMORY_REG_REG
:
assert
(
getMemOffset
(
)
==
nullptr
)
;
OS
<<
"MemRegReg: "
<<
getMemBaseReg
(
)
<<
"+"
<<
"%r"
<<
getMemOffsetReg
(
)
<<
"\n"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

Lanai
"Imm: "
"\n"
"Token: "
"\n"
"Reg: %r"
"\n"
"MemImm: "
"\n"
"MemRegImm: "
"+"
"\n"
"MemRegReg: "
"+"
"%r"
"\n"


<s> static inline bool offset_4bit_signed_scaled_p ( machine_mode mode , poly_int64 offset ) { HOST_WIDE_INT multiple ; return ( constant_multiple_p ( offset , GET_MODE_SIZE ( mode ) , & multiple ) && IN_RANGE ( multiple , - 8 , 7 ) ) ; } </s>

Return true if OFFSET is a signed 4-bit value multiplied by the size of MODE .


<s> static HOST_WIDE_INT int_log2 ( HOST_WIDE_INT power ) { HOST_WIDE_INT shift = 0 ; while ( ( ( ( HOST_WIDE_INT ) 1 << shift ) & power ) == 0 ) { gcc_assert ( shift <= 31 ) ; shift ++ ; } return shift ; } </s>

Obtain the shift from the POWER of two .


<s> static void i386_solaris_elf_named_section ( const char * name , unsigned int flags , tree decl ) { if ( TARGET_64BIT && strcmp ( name , ".eh_frame" ) == 0 ) { fprintf ( asm_out_file , "\t.section\t%s,\"%s\",@unwind\n" , name , flags & SECTION_WRITE ? "aw" : "a" ) ; return ; } if ( HAVE_COMDAT_GROUP && flags & SECTION_LINKONCE ) { solaris_elf_asm_comdat_section ( name , flags , decl ) ; return ; } default_elf_asm_named_section ( name , flags , decl ) ; } </s>

Solaris named-section hook . Parameters are as for named_section_real .


<s> bool MipsPassConfig :: addInstSelector ( ) { addPass ( createMipsModuleISelDag ( getMipsTargetMachine ( ) ) ) ; addPass ( createMips16ISelDag ( getMipsTargetMachine ( ) ) ) ; addPass ( createMipsSEISelDag ( getMipsTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void mmix_conditional_register_usage ( void ) { int i ; if ( TARGET_ABI_GNU ) { static const int gnu_abi_reg_alloc_order [ ] = MMIX_GNU_ABI_REG_ALLOC_ORDER ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) reg_alloc_order [ i ] = gnu_abi_reg_alloc_order [ i ] ; for ( i = 15 ; i <= 30 ; i ++ ) call_used_regs [ i ] = 0 ; for ( i = MMIX_RESERVED_GNU_ARG_0_REGNUM ; i < MMIX_RESERVED_GNU_ARG_0_REGNUM + MMIX_MAX_ARGS_IN_REGS ; i ++ ) fixed_regs [ i ] = 0 ; } if ( ! TARGET_TOPLEVEL_SYMBOLS ) for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( reg_names [ i ] [ 0 ] == ':' ) reg_names [ i ] ++ ; } </s>


<s> SDNode * HexagonDAGToDAGISel :: Select ( SDNode * N ) { if ( N -> isMachineOpcode ( ) ) { N -> setNodeId ( - 1 ) ; return nullptr ; } switch ( N -> getOpcode ( ) ) { case ISD :: Constant : return SelectConstant ( N ) ; case ISD :: ConstantFP : return SelectConstantFP ( N ) ; case ISD :: ADD : return SelectAdd ( N ) ; case ISD :: SHL : return SelectSHL ( N ) ; case ISD :: LOAD : return SelectLoad ( N ) ; case ISD :: STORE : return SelectStore ( N ) ; case ISD :: SELECT : return SelectSelect ( N ) ; case ISD :: TRUNCATE : return SelectTruncate ( N ) ; case ISD :: MUL : return SelectMul ( N ) ; case ISD :: ZERO_EXTEND : return SelectZeroExtend ( N ) ; case ISD :: INTRINSIC_WO_CHAIN : return SelectIntrinsicWOChain ( N ) ; } return SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .

Hexagon Hexagon 1 ISD::Constant ISD::ConstantFP ISD::ADD ISD::SHL ISD::LOAD ISD::STORE ISD::SELECT ISD::TRUNCATE ISD::MUL ISD::ZERO_EXTEND ISD::INTRINSIC_WO_CHAIN


<s>
void
CJGDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
SDLoc
dl
(
Node
)
;
switch
(
Node
->
getOpcode
(
)
)
{
default
:
break
;
case
ISD
::
FrameIndex
:
{
assert
(
Node
->
getValueType
(
0
)
==
MVT
::
i32
)
;
int
FI
=
cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
MVT
::
i32
)
;
if
(
Node
->
hasOneUse
(
)
)
{
CurDAG
->
SelectNodeTo
(
Node
,
CJG
::
ADDri
,
MVT
::
i32
,
TFI
,
CurDAG
->
getTargetConstant
(
0
,
dl
,
MVT
::
i32
)
)
;
return
;
}
ReplaceNode
(
Node
,
CurDAG
->
getMachineNode
(
CJG
::
ADDri
,
dl
,
MVT
::
i32
,
TFI
,
CurDAG
->
getTargetConstant
(
0
,
dl
,
MVT
::
i32
)
)
)
;
return
;
}
}
SelectCode
(
Node
)
;
}
</s>


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"SPU nop/lnop Filler"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool isSubregFoldable ( ) const override { return true ; } </s>

Check whether the target can fold a load that feeds a subreg operand ( or a subreg operand that feeds a store ) .


<s> int SystemZHazardRecognizer :: groupingCost ( SUnit * SU ) const { const MCSchedClassDesc * SC = DAG -> getSchedClass ( SU ) ; if ( ! SC -> isValid ( ) ) return 0 ; if ( SC -> BeginGroup ) { if ( CurrGroupSize ) return 3 - CurrGroupSize ; return - 1 ; } if ( SC -> EndGroup ) { unsigned resultingGroupSize = ( CurrGroupSize + getNumDecoderSlots ( SU ) ) ; if ( resultingGroupSize < 3 ) return ( 3 - resultingGroupSize ) ; return - 1 ; } return 0 ; } </s>

Return the cost of decoder grouping for SU .


runOnMachineFunction - Emit the function body .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { TII = static_cast < const R600InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = & TII -> getRegisterInfo ( ) ; DEBUG ( MF . dump ( ) ; ) ; OrderedBlks . clear ( ) ; Visited . clear ( ) ; FuncRep = & MF ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; DEBUG ( dbgs ( ) << "LoopInfo:\n" ; PrintLoopinfo ( * MLI ) ; ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; DEBUG ( MDT -> print ( dbgs ( ) , ( const llvm :: Module * ) nullptr ) ; ) ; PDT = & getAnalysis < MachinePostDominatorTree > ( ) ; DEBUG ( PDT -> print ( dbgs ( ) ) ; ) ; prepare ( ) ; run ( ) ; DEBUG ( MF . dump ( ) ; ) ; return true ; } </s>


"getIntImmCost can only estimate cost of materialising integers"

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> void MipsInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; BuildMI ( MBB , MI , DL , get ( Mips :: NOP ) ) ; } </s>

Insert a noop into the instruction stream at the specified point .


<s> int nds32_can_use_bitci_p ( int ival ) { return ( TARGET_ISA_V3 && ( ival < 0 ) && satisfies_constraint_Iu15 ( gen_int_mode ( ~ ival , SImode ) ) ) ; } </s>

Function to check if 'bitci ' instruction can be used with IVAL .


Return nonzero if register OLD_REG can be renamed to register NEW_REG .


"AArch64 FastISel doesn't support types larger than i64"

This is a wrapper around getRegForValue that also takes care of truncating or sign-extending the given getelementptr index value .


<s> const TargetFrameLowering :: SpillSlot * AMDGPUFrameLowering :: getCalleeSavedSpillSlots ( unsigned & NumEntries ) const { NumEntries = 0 ; return nullptr ; } </s>

getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs , that contains an entry for each callee saved register that must be spilled to a particular stack location if it is spilled .


<s> unsigned AMDGPURegisterBankInfo :: copyCost ( const RegisterBank & Dst , const RegisterBank & Src , unsigned Size ) const { if ( Dst . getID ( ) == AMDGPU :: SGPRRegBankID && Src . getID ( ) == AMDGPU :: VGPRRegBankID ) { return std :: numeric_limits < unsigned > :: max ( ) ; } if ( Size == 1 && Dst . getID ( ) == AMDGPU :: SCCRegBankID && ( Src . getID ( ) == AMDGPU :: SGPRRegBankID || Src . getID ( ) == AMDGPU :: VGPRRegBankID || Src . getID ( ) == AMDGPU :: VCCRegBankID ) ) return std :: numeric_limits < unsigned > :: max ( ) ; if ( Dst . getID ( ) == AMDGPU :: SCCRegBankID && Src . getID ( ) == AMDGPU :: VCCRegBankID ) return std :: numeric_limits < unsigned > :: max ( ) ; return RegisterBankInfo :: copyCost ( Dst , Src , Size ) ; } </s>

Get the cost of a copy from B to A , or put differently , get the cost of A = COPY B .

AMDGPU AMDGPU AMDGPU::SGPRRegBankID AMDGPU::VGPRRegBankID 1 AMDGPU::SCCRegBankID AMDGPU::SGPRRegBankID AMDGPU::VGPRRegBankID AMDGPU::VCCRegBankID AMDGPU::SCCRegBankID AMDGPU::VCCRegBankID


<s> void PTXFrameInfo :: emitPrologue ( MachineFunction & MF ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = 0 ; i != 4 ; ++ i ) Data [ Offset + i ] |= uint8_t ( ( Value >> ( ( 4 - i - 1 ) * 8 ) ) & 0xff ) ; } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool HexagonRegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { return MF . getSubtarget < HexagonSubtarget > ( ) . getFrameLowering ( ) -> hasFP ( MF ) ; } </s>

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot .


<s> const RegisterBankInfo :: InstructionMapping & AMDGPURegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { const RegisterBankInfo :: InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; SmallVector < const ValueMapping * , 8 > OpdsMapping ( MI . getNumOperands ( ) ) ; bool IsComplete = true ; switch ( MI . getOpcode ( ) ) { default : IsComplete = false ; break ; case AMDGPU :: G_CONSTANT : { unsigned Size = MRI . getType ( MI . getOperand ( 0 ) . getReg ( ) ) . getSizeInBits ( ) ; OpdsMapping [ 0 ] = AMDGPU :: getValueMapping ( AMDGPU :: SGPRRegBankID , Size ) ; break ; } case AMDGPU :: G_GEP : { for ( unsigned i = 0 , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { if ( ! MI . getOperand ( i ) . isReg ( ) ) continue ; unsigned Size = MRI . getType ( MI . getOperand ( i ) . getReg ( ) ) . getSizeInBits ( ) ; OpdsMapping [ i ] = AMDGPU :: getValueMapping ( AMDGPU :: SGPRRegBankID , Size ) ; } break ; } case AMDGPU :: G_STORE : { assert ( MI . getOperand ( 0 ) . isReg ( ) ) ; unsigned Size = MRI . getType ( MI . getOperand ( 0 ) . getReg ( ) ) . getSizeInBits ( ) ; const ValueMapping * ValMapping = AMDGPU :: getValueMapping ( AMDGPU :: VGPRRegBankID , Size ) ; const ValueMapping * PtrMapping = AMDGPU :: getValueMapping ( AMDGPU :: VGPRRegBankID , 64 ) ; OpdsMapping [ 0 ] = ValMapping ; OpdsMapping [ 1 ] = PtrMapping ; break ; } case AMDGPU :: G_LOAD : return getInstrMappingForLoad ( MI ) ; } if ( ! IsComplete ) { unsigned BankID = AMDGPU :: SGPRRegBankID ; unsigned Size = 0 ; for ( unsigned Idx = 0 ; Idx < MI . getNumOperands ( ) ; ++ Idx ) { if ( MI . getOperand ( Idx ) . isReg ( ) ) Size = getSizeInBits ( MI . getOperand ( Idx ) . getReg ( ) , MRI , * TRI ) ; OpdsMapping . push_back ( AMDGPU :: getValueMapping ( BankID , Size ) ) ; } } return getInstructionMapping ( 1 , 1 , getOperandsMapping ( OpdsMapping ) , MI . getNumOperands ( ) ) ; } </s>

Get the mapping of the different operands of MI on the register bank .


"RegScavenger required for long branching"

"new block should be inserted for expanding unconditional branch"

"Branch offsets outside of the signed 32-bit range not supported"

Insert an unconditional indirect branch at the end of MBB to NewDestBB .


<s> int direct_return ( void ) { return ( TARGET_ABI_OSF && reload_completed && alpha_sa_size ( ) == 0 && get_frame_size ( ) == 0 && crtl -> outgoing_args_size == 0 && crtl -> args . pretend_args_size == 0 ) ; } </s>

Return non-zero if this function is known to have a null epilogue .


<s>
const
TargetRegisterClass
*
AVRRegisterInfo
::
getLargestLegalSuperClass
(
const
TargetRegisterClass
*
RC
,
const
MachineFunction
&
MF
)
const
{
const
TargetRegisterInfo
*
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
if
(
TRI
->
isTypeLegalForClass
(
*
RC
,
MVT
::
i16
)
)
{
return
&
AVR
::
DREGSRegClass
;
}
if
(
TRI
->
isTypeLegalForClass
(
*
RC
,
MVT
::
i8
)
)
{
return
&
AVR
::
GPR8RegClass
;
}
llvm_unreachable
(
"Invalid register size"
)
;
}
</s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .


<s> void PIC16RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool MSP430TargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { LoadSDNode * LD = cast < LoadSDNode > ( N ) ; if ( LD -> getExtensionType ( ) != ISD :: NON_EXTLOAD ) return false ; EVT VT = LD -> getMemoryVT ( ) ; if ( VT != MVT :: i8 && VT != MVT :: i16 ) return false ; if ( Op -> getOpcode ( ) != ISD :: ADD ) return false ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ) { uint64_t RHSC = RHS -> getZExtValue ( ) ; if ( ( VT == MVT :: i16 && RHSC != 2 ) || ( VT == MVT :: i8 && RHSC != 1 ) ) return false ; Base = Op -> getOperand ( 0 ) ; Offset = DAG . getConstant ( RHSC , SDLoc ( N ) , VT ) ; AM = ISD :: POST_INC ; return true ; } return false ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .


<s> static rtx nvptx_static_chain ( const_tree fndecl , bool incoming_p ) { if ( ! DECL_STATIC_CHAIN ( fndecl ) ) return NULL ; if ( incoming_p ) return gen_rtx_REG ( Pmode , STATIC_CHAIN_REGNUM ) ; else return gen_rtx_REG ( Pmode , OUTGOING_STATIC_CHAIN_REGNUM ) ; } </s>


<s> unsigned getByValTypeAlignment ( Type * Ty , const DataLayout & DL ) const override { return 4 ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


<s> bool rs6000_split_128bit_ok_p ( rtx operands [ ] ) { if ( ! reload_completed ) return false ; if ( ! gpr_or_gpr_p ( operands [ 0 ] , operands [ 1 ] ) ) return false ; if ( quad_load_store_p ( operands [ 0 ] , operands [ 1 ] ) ) return false ; return true ; } </s>

Return true if a 128-bit move needs to be split .


<s>
static
void
nds32_asm_function_epilogue
(
FILE
*
file
,
HOST_WIDE_INT
size
ATTRIBUTE_UNUSED
)
{
fprintf
(
file
,
"\t! END EPILOGUE\n"
)
;
}
</s>

The content produced from this function will be placed after epilogue body .


<s> static void visium_setup_incoming_varargs ( cumulative_args_t pcum_v , const function_arg_info & arg , int * pretend_size ATTRIBUTE_UNUSED , int no_rtl ) { cumulative_args_t local_args_so_far ; CUMULATIVE_ARGS local_copy ; CUMULATIVE_ARGS * locargs ; int gp_saved , fp_saved , size ; local_args_so_far . p = & local_copy ; locargs = get_cumulative_args ( pcum_v ) ; local_args_so_far . magic = CUMULATIVE_ARGS_MAGIC ; local_copy . grcount = locargs -> grcount ; local_copy . frcount = locargs -> frcount ; local_copy . stack_words = locargs -> stack_words ; TARGET_FUNCTION_ARG_ADVANCE ( local_args_so_far , arg ) ; locargs = get_cumulative_args ( local_args_so_far ) ; gp_saved = MAX_ARGS_IN_GP_REGISTERS - locargs -> grcount ; fp_saved = ( TARGET_FPU ? MAX_ARGS_IN_FP_REGISTERS - locargs -> frcount : 0 ) ; size = ( gp_saved * UNITS_PER_WORD ) + ( fp_saved * UNITS_PER_HWFPVALUE ) ; if ( ! no_rtl && size > 0 ) { rtx ptr = force_reg ( Pmode , plus_constant ( Pmode , virtual_incoming_args_rtx , - size ) ) ; if ( gp_saved > 0 ) { rtx mem = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , ptr , fp_saved * UNITS_PER_HWFPVALUE ) ) ; MEM_NOTRAP_P ( mem ) = 1 ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( locargs -> grcount + GP_ARG_FIRST , mem , gp_saved ) ; } if ( fp_saved > 0 ) { rtx mem = gen_rtx_MEM ( BLKmode , ptr ) ; MEM_NOTRAP_P ( mem ) = 1 ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; gcc_assert ( UNITS_PER_WORD == UNITS_PER_HWFPVALUE ) ; move_block_from_reg ( locargs -> frcount + FP_ARG_FIRST , mem , fp_saved ) ; } } visium_reg_parm_save_area_size = size ; } </s>

Store the anonymous register arguments into the stack so that all the arguments appear to have been passed consecutively on the stack .


<s> unsigned HexagonMCInst :: getUnits ( const HexagonTargetMachine * TM ) const { const HexagonInstrInfo * QII = TM -> getSubtargetImpl ( ) -> getInstrInfo ( ) ; const InstrItineraryData * II = TM -> getSubtargetImpl ( ) -> getInstrItineraryData ( ) ; const InstrStage * IS = II -> beginStage ( QII -> get ( this -> getOpcode ( ) ) . getSchedClass ( ) ) ; return ( IS -> getUnits ( ) ) ; } </s>


<s>
bool
X86InstrInfo
::
isReallyTriviallyReMaterializable
(
const
MachineInstr
*
MI
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
X86
::
MOV8rm
:
case
X86
::
MOV16rm
:
case
X86
::
MOV32rm
:
case
X86
::
MOV64rm
:
case
X86
::
LD_Fp64m
:
case
X86
::
MOVSSrm
:
case
X86
::
MOVSDrm
:
case
X86
::
MOVAPSrm
:
case
X86
::
MOVAPDrm
:
case
X86
::
MOVDQArm
:
case
X86
::
MMX_MOVD64rm
:
case
X86
::
MMX_MOVQ64rm
:
{
if
(
MI
->
getOperand
(
1
)
.
isReg
(
)
&&
MI
->
getOperand
(
2
)
.
isImm
(
)
&&
MI
->
getOperand
(
3
)
.
isReg
(
)
&&
MI
->
getOperand
(
3
)
.
getReg
(
)
==
0
&&
(
MI
->
getOperand
(
4
)
.
isCPI
(
)
||
(
MI
->
getOperand
(
4
)
.
isGlobal
(
)
&&
isGVStub
(
MI
->
getOperand
(
4
)
.
getGlobal
(
)
,
TM
)
)
)
)
{
unsigned
BaseReg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
if
(
BaseReg
==
0
)
return
true
;
if
(
!
ReMatPICStubLoad
&&
MI
->
getOperand
(
4
)
.
isGlobal
(
)
)
return
false
;
const
MachineFunction
&
MF
=
*
MI
->
getParent
(
)
->
getParent
(
)
;
const
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
bool
isPICBase
=
false
;
for
(
MachineRegisterInfo
::
def_iterator
I
=
MRI
.
def_begin
(
BaseReg
)
,
E
=
MRI
.
def_end
(
)
;
I
!=
E
;
++
I
)
{
MachineInstr
*
DefMI
=
I
.
getOperand
(
)
.
getParent
(
)
;
if
(
DefMI
->
getOpcode
(
)
!=
X86
::
MOVPC32r
)
return
false
;
assert
(
!
isPICBase
&&
"More than one PIC base?"
)
;
isPICBase
=
true
;
}
return
isPICBase
;
}
return
false
;
}
case
X86
::
LEA32r
:
case
X86
::
LEA64r
:
{
if
(
MI
->
getOperand
(
2
)
.
isImm
(
)
&&
MI
->
getOperand
(
3
)
.
isReg
(
)
&&
MI
->
getOperand
(
3
)
.
getReg
(
)
==
0
&&
!
MI
->
getOperand
(
4
)
.
isReg
(
)
)
{
if
(
!
MI
->
getOperand
(
1
)
.
isReg
(
)
)
return
true
;
unsigned
BaseReg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
if
(
BaseReg
==
0
)
return
true
;
const
MachineFunction
&
MF
=
*
MI
->
getParent
(
)
->
getParent
(
)
;
const
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
return
regIsPICBase
(
BaseReg
,
MRI
)
;
}
return
false
;
}
}
return
true
;
}
</s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> X86Subtarget :: X86Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const X86TargetMachine & TM , unsigned StackAlignOverride ) : X86GenSubtargetInfo ( TT , CPU , FS ) , X86ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TargetTriple ( TT ) , DL ( computeDataLayout ( TargetTriple ) ) , StackAlignOverride ( StackAlignOverride ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , TSInfo ( DL ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM ) , FrameLowering ( TargetFrameLowering :: StackGrowsDown , getStackAlignment ( ) , is64Bit ( ) ? - 8 : - 4 ) { if ( TM . getRelocationModel ( ) == Reloc :: Static ) { setPICStyle ( PICStyles :: None ) ; } else if ( is64Bit ( ) ) { setPICStyle ( PICStyles :: RIPRel ) ; } else if ( isTargetCOFF ( ) ) { setPICStyle ( PICStyles :: None ) ; } else if ( isTargetDarwin ( ) ) { if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( TM . getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( isTargetELF ( ) ) { setPICStyle ( PICStyles :: GOT ) ; } } </s>

This constructor initializes the data members to match that of the specified triple .


<s>
SDValue
TVMTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
LOAD
:
return
LowerLoad
(
Op
,
DAG
)
;
case
ISD
::
STORE
:
return
LowerStore
(
Op
,
DAG
)
;
case
ISD
::
ExternalSymbol
:
return
LowerExternalSymbol
(
Op
,
DAG
)
;
case
ISD
::
BR
:
return
LowerBR
(
Op
,
DAG
)
;
case
ISD
::
BRCOND
:
return
LowerBRCOND
(
Op
,
DAG
)
;
case
ISD
::
TargetFrameIndex
:
case
ISD
::
FrameIndex
:
return
LowerFrameIndex
(
Op
,
DAG
)
;
case
ISD
::
CopyToReg
:
return
LowerCopyToReg
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_W_CHAIN
:
return
LowerINTRINSIC_W_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

TVM
TVM
ISD::GlobalAddress
ISD::LOAD
ISD::STORE
ISD::ExternalSymbol
ISD::BR
ISD::BRCOND
ISD::TargetFrameIndex
ISD::FrameIndex
ISD::CopyToReg
ISD::INTRINSIC_W_CHAIN
ISD::INTRINSIC_WO_CHAIN
"unimplemented operand"


<s> bool AArch64PassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnablePromoteConstant ) addPass ( createAArch64PromoteConstantPass ( ) ) ; if ( ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE ) { bool OnlyOptimizeForSize = ( TM -> getOptLevel ( ) < CodeGenOpt :: Aggressive ) && ( EnableGlobalMerge == cl :: BOU_UNSET ) ; addPass ( createGlobalMergePass ( TM , 4095 , OnlyOptimizeForSize ) ) ; } if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAddressTypePromotion ) addPass ( createAArch64AddressTypePromotionPass ( ) ) ; return false ; } </s>


Returns assembly code to perform a DImode shift using a 64-bit global or out register on SPARC-V8+ .


<s> bool X86FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; const X86Subtarget & STI = MF . getSubtarget < X86Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } unsigned Opc = STI . is64Bit ( ) ? X86 :: POP64r : X86 :: POP32r ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool m68k_matches_q_p ( rtx x ) { struct m68k_address address ; return ( m68k_legitimate_mem_p ( x , & address ) && address . code == UNKNOWN && address . base && ! address . offset && ! address . index ) ; } </s>

Return true if X matches the ' Q ' constraint . It must be a memory with a base address and no constant offset or index .


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> bool PPCFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( ! Subtarget . isSVR4ABI ( ) ) return false ; MachineFunction * MF = MBB . getParent ( ) ; const PPCInstrInfo & TII = * static_cast < const PPCInstrInfo * > ( MF -> getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc DL ; bool CRSpilled = false ; MachineInstrBuilder CRMIB ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsCRField = PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ; MBB . addLiveIn ( Reg ) ; if ( CRSpilled && IsCRField ) { CRMIB . addReg ( Reg , RegState :: ImplicitKill ) ; continue ; } if ( IsCRField ) { PPCFunctionInfo * FuncInfo = MF -> getInfo < PPCFunctionInfo > ( ) ; if ( Subtarget . isPPC64 ( ) ) { FuncInfo -> addMustSaveCR ( Reg ) ; } else { CRSpilled = true ; FuncInfo -> setSpillsCR ( ) ; CRMIB = BuildMI ( * MF , DL , TII . get ( PPC :: MFCR ) , PPC :: R12 ) . addReg ( Reg , RegState :: ImplicitKill ) ; MBB . insert ( MI , CRMIB ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( PPC :: STW ) ) . addReg ( PPC :: R12 , getKillRegState ( true ) ) , CSI [ i ] . getFrameIdx ( ) ) ) ; } } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static void microblaze_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; cum -> arg_number ++ ; switch ( mode ) { case VOIDmode : break ; default : gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_INT || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) ; cum -> gp_reg_found = 1 ; cum -> arg_words += ( ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ) ; break ; case BLKmode : cum -> gp_reg_found = 1 ; cum -> arg_words += ( ( int_size_in_bytes ( type ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ) ; break ; case SFmode : cum -> arg_words ++ ; if ( ! cum -> gp_reg_found && cum -> arg_number <= 2 ) cum -> fp_code += 1 << ( ( cum -> arg_number - 1 ) * 2 ) ; break ; case DFmode : cum -> arg_words += 2 ; if ( ! cum -> gp_reg_found && cum -> arg_number <= 2 ) cum -> fp_code += 2 << ( ( cum -> arg_number - 1 ) * 2 ) ; break ; case DImode : cum -> gp_reg_found = 1 ; cum -> arg_words += 2 ; break ; case QImode : case HImode : case SImode : case TImode : cum -> gp_reg_found = 1 ; cum -> arg_words ++ ; break ; } } </s>

Advance the argument to the next argument position .


<s> void alpha_emit_xfloating_cvt ( enum rtx_code orig_code , rtx operands [ ] ) { int noperands = 1 , mode ; rtx out_operands [ 2 ] ; rtx func ; enum rtx_code code = orig_code ; if ( code == UNSIGNED_FIX ) code = FIX ; func = alpha_lookup_xfloating_lib_func ( code ) ; out_operands [ 0 ] = operands [ 1 ] ; switch ( code ) { case FIX : mode = alpha_compute_xfloating_mode_arg ( code , ALPHA_FPRM_CHOP ) ; out_operands [ 1 ] = GEN_INT ( mode ) ; noperands = 2 ; break ; case FLOAT_TRUNCATE : mode = alpha_compute_xfloating_mode_arg ( code , alpha_fprm ) ; out_operands [ 1 ] = GEN_INT ( mode ) ; noperands = 2 ; break ; default : break ; } alpha_emit_xfloating_libcall ( func , operands [ 0 ] , out_operands , noperands , gen_rtx_fmt_e ( orig_code , GET_MODE ( operands [ 0 ] ) , operands [ 1 ] ) ) ; } </s>

Emit an X_floating library function call for a conversion .


<s> unsigned RISCVInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : { return get ( Opcode ) . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return 0 ; case RISCV :: PseudoCALLReg : case RISCV :: PseudoCALL : case RISCV :: PseudoTAIL : case RISCV :: PseudoLLA : case RISCV :: PseudoLA : case RISCV :: PseudoLA_TLS_IE : case RISCV :: PseudoLA_TLS_GD : return 8 ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const auto & TM = static_cast < const RISCVTargetMachine & > ( MF . getTarget ( ) ) ; return getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> static int visium_register_move_cost ( enum machine_mode mode , reg_class_t from , reg_class_t to ) { const int numwords = ( GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD ) ? 1 : 2 ; if ( from == MDB || to == MDB ) return 4 ; else if ( from == MDC || to == MDC || ( from == FP_REGS ) != ( to == FP_REGS ) ) return 4 * numwords ; else return 2 * numwords ; } </s>

Return the cost of moving data of mode MODE from a register in class FROM to one in class TO . A value of 2 is the default ; other values are interpreted relative to that .


<s> static bool mips_valid_lo_sum_p ( enum mips_symbol_type symbol_type , machine_mode mode ) { if ( mips_symbol_insns ( symbol_type , mode ) == 0 ) return false ; if ( mips_lo_relocs [ symbol_type ] == NULL ) return false ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && GET_MODE_BITSIZE ( mode ) > GET_MODE_ALIGNMENT ( mode ) ) return false ; if ( MSA_SUPPORTED_MODE_P ( mode ) ) return false ; return true ; } </s>

Return true if a LO_SUM can address a value of mode MODE when the LO_SUM symbol has type SYMBOL_TYPE .


<s> static rtx rs6000_emit_stack_reset ( rs6000_stack_t * info , rtx frame_reg_rtx , HOST_WIDE_INT frame_off , unsigned updt_regno ) { if ( frame_off == 0 && REGNO ( frame_reg_rtx ) == updt_regno ) return NULL_RTX ; rtx updt_reg_rtx = gen_rtx_REG ( Pmode , updt_regno ) ; if ( DEFAULT_ABI == ABI_V4 || ( TARGET_SPE_ABI && info -> spe_64bit_regs_used != 0 && info -> first_gp_reg_save != 32 ) ) return emit_insn ( gen_stack_restore_tie ( updt_reg_rtx , frame_reg_rtx , GEN_INT ( frame_off ) ) ) ; if ( frame_off != 0 ) return emit_insn ( gen_add3_insn ( updt_reg_rtx , frame_reg_rtx , GEN_INT ( frame_off ) ) ) ; else return emit_move_insn ( updt_reg_rtx , frame_reg_rtx ) ; return NULL_RTX ; } </s>

Emit a sequence of insns , including a stack tie if needed , for resetting the stack pointer . If UPDT_REGNO is not 1 , then do n't reset the stack pointer , but move the base of the frame into reg UPDT_REGNO for use by out-of-line register restore routines .


<s> const DLXTargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


<s> static void arc_init_reg_tables ( void ) { int i ; for ( i = 0 ; i < NUM_MACHINE_MODES ; i ++ ) { machine_mode m = ( machine_mode ) i ; switch ( GET_MODE_CLASS ( m ) ) { case MODE_INT : case MODE_PARTIAL_INT : case MODE_COMPLEX_INT : if ( GET_MODE_SIZE ( m ) <= 4 ) arc_mode_class [ i ] = 1 << ( int ) S_MODE ; else if ( GET_MODE_SIZE ( m ) == 8 ) arc_mode_class [ i ] = 1 << ( int ) D_MODE ; else if ( GET_MODE_SIZE ( m ) == 16 ) arc_mode_class [ i ] = 1 << ( int ) T_MODE ; else if ( GET_MODE_SIZE ( m ) == 32 ) arc_mode_class [ i ] = 1 << ( int ) O_MODE ; else arc_mode_class [ i ] = 0 ; break ; case MODE_FLOAT : case MODE_COMPLEX_FLOAT : if ( GET_MODE_SIZE ( m ) <= 4 ) arc_mode_class [ i ] = 1 << ( int ) SF_MODE ; else if ( GET_MODE_SIZE ( m ) == 8 ) arc_mode_class [ i ] = 1 << ( int ) DF_MODE ; else if ( GET_MODE_SIZE ( m ) == 16 ) arc_mode_class [ i ] = 1 << ( int ) TF_MODE ; else if ( GET_MODE_SIZE ( m ) == 32 ) arc_mode_class [ i ] = 1 << ( int ) OF_MODE ; else arc_mode_class [ i ] = 0 ; break ; case MODE_VECTOR_INT : if ( GET_MODE_SIZE ( m ) == 4 ) arc_mode_class [ i ] = ( 1 << ( int ) S_MODE ) ; else if ( GET_MODE_SIZE ( m ) == 8 ) arc_mode_class [ i ] = ( 1 << ( int ) D_MODE ) ; else arc_mode_class [ i ] = ( 1 << ( int ) V_MODE ) ; break ; case MODE_CC : default : if ( i == ( int ) CCmode || i == ( int ) CC_ZNmode || i == ( int ) CC_Zmode || i == ( int ) CC_Cmode || i == CC_FP_GTmode || i == CC_FP_GEmode || i == CC_FP_ORDmode || i == CC_FPUmode || i == CC_FPU_UNEQmode ) arc_mode_class [ i ] = 1 << ( int ) C_MODE ; else arc_mode_class [ i ] = 0 ; break ; } } } </s>


<s> static struct machine_function * arc_init_machine_status ( void ) { struct machine_function * machine ; machine = ggc_cleared_alloc < machine_function > ( ) ; machine -> fn_type = ARC_FUNCTION_UNKNOWN ; machine -> force_short_suffix = - 1 ; return machine ; } </s>

The usual ; we set up our machine_function data .


<s> bool isCheapToSpeculateCttz ( ) const override { return true ; } </s>

Return true if it is cheap to speculate a call to intrinsic cttz .


<s> static inline built_in_function complex_multiply_builtin_code ( machine_mode mode ) { gcc_assert ( IN_RANGE ( mode , MIN_MODE_COMPLEX_FLOAT , MAX_MODE_COMPLEX_FLOAT ) ) ; int func = BUILT_IN_COMPLEX_MUL_MIN + mode - MIN_MODE_COMPLEX_FLOAT ; return ( built_in_function ) func ; } </s>

Internal function to return the built-in function id for the complex multiply operation for a given mode .


<s> void pdp11_output_labelref ( FILE * file , const char * name ) { if ( ! TARGET_DEC_ASM ) fputs ( USER_LABEL_PREFIX , file ) ; fputs ( name , file ) ; } </s>

This emits a ( user ) label , which gets a `` _ '' prefix except for DEC assembler output .


"enabling backtrace support is only meaningful when compiling for the Thumb"

"enabling callee interworking support is only meaningful when compiling for the Thumb"

"-g with -mno-apcs-frame may not give sensible debugging"

"can not use -mtp=cp15 with 16-bit Thumb"

"-mslow-flash-data only supports non-pic code on armv7-m targets"

"-mpure-code only supports non-pic code on armv7-m targets"

Check any incompatible options that the user has specified .


<s> static rtx tilegx_emit_cc_test ( enum rtx_code code , rtx op0 , rtx op1 , machine_mode cmp_mode , bool eq_ne_only ) { enum rtx_code branch_code ; rtx temp ; if ( cmp_mode == SFmode || cmp_mode == DFmode ) { temp = gen_reg_rtx ( DImode ) ; tilegx_emit_setcc_internal ( temp , code , op0 , op1 , cmp_mode ) ; return gen_rtx_fmt_ee ( NE , VOIDmode , temp , const0_rtx ) ; } if ( op1 == const0_rtx && ( code == EQ || code == NE || ( ! eq_ne_only && signed_compare_p ( code ) ) ) ) { op0 = force_reg ( cmp_mode , op0 ) ; return gen_rtx_fmt_ee ( code , VOIDmode , op0 , const0_rtx ) ; } switch ( code ) { case EQ : case LE : case LT : case LEU : case LTU : branch_code = NE ; break ; case NE : case GE : case GT : case GEU : case GTU : code = reverse_condition ( code ) ; branch_code = EQ ; break ; default : gcc_unreachable ( ) ; } if ( CONST_INT_P ( op1 ) && ( ! satisfies_constraint_I ( op1 ) || code == LEU ) ) { HOST_WIDE_INT n = INTVAL ( op1 ) ; switch ( code ) { case EQ : if ( n != - 128 && add_operand ( GEN_INT ( - n ) , DImode ) && ! ( symbolic_operand ( op0 , VOIDmode ) || ( REG_P ( op0 ) && REG_POINTER ( op0 ) ) ) ) { if ( GET_MODE ( op0 ) != DImode ) { rtx temp2 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_extendsidi2 ( temp2 , op0 ) ) ; op0 = temp2 ; } else { op0 = force_reg ( DImode , op0 ) ; } temp = gen_reg_rtx ( DImode ) ; emit_move_insn ( temp , gen_rtx_PLUS ( DImode , op0 , GEN_INT ( - n ) ) ) ; return gen_rtx_fmt_ee ( reverse_condition ( branch_code ) , VOIDmode , temp , const0_rtx ) ; } break ; case LEU : if ( n == - 1 ) break ; case LTU : { int first = exact_log2 ( code == LTU ? n : n + 1 ) ; if ( first != - 1 ) { op0 = force_reg ( cmp_mode , op0 ) ; temp = gen_reg_rtx ( cmp_mode ) ; emit_move_insn ( temp , gen_rtx_ASHIFTRT ( cmp_mode , op0 , GEN_INT ( first ) ) ) ; return gen_rtx_fmt_ee ( reverse_condition ( branch_code ) , VOIDmode , temp , const0_rtx ) ; } } break ; default : break ; } } temp = gen_reg_rtx ( DImode ) ; tilegx_emit_setcc_internal ( temp , code , op0 , op1 , cmp_mode ) ; return gen_rtx_fmt_ee ( branch_code , VOIDmode , temp , const0_rtx ) ; } </s>

Generate the comparison for a DImode conditional branch .


"only initialized variables can be placed into "

Handle a `` progmem '' attribute ; arguments as in struct attribute_spec.handler .


<s> static bool aarch64_function_value_regno_p ( const unsigned int regno ) { if ( regno == R0_REGNUM || regno == R1_REGNUM ) return true ; if ( regno >= V0_REGNUM && regno < V0_REGNUM + HA_MAX_NUM_FLDS ) return ! TARGET_GENERAL_REGS_ONLY ; return false ; } </s>

Implements TARGET_FUNCTION_VALUE_REGNO_P . Return true if REGNO is the number of a hard register in which the values of called function may come back .


"TVM doesn't support non-C calling conventions"

"TVM hasn't implemented inalloca arguments"

"TVM hasn't implemented cons regs arguments"

"TVM hasn't implemented cons regs last arguments"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


"lane index must be a constant immediate"

"total size and element size must be a nonzero "

Expand an AArch64 AdvSIMD builtin ( intrinsic ) .


<s> static MCAsmInfo * createMCAsmInfo ( const MCRegisterInfo & , const Triple & TT ) { if ( TT . isOSBinFormatELF ( ) ) return new WebAssemblyMCAsmInfoELF ( TT ) ; return new WebAssemblyMCAsmInfo ( TT ) ; } </s>

createMCAsmInfo - Create a MCAsmInfo implementation for the specified target triple .


<s>
const
char
*
getPassName
(
)
const
{
return
"rvex VLIW Packetizer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"Caller should have checked for a comparison"

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> virtual const AMDGPUInstrInfo * getInstrInfo ( ) const { return InstrInfo . get ( ) ; } </s>


"JIT relocation model must be set to static or default!"

runOnMachineFunction - Emit the function body .


<s>
static
int
getMemScale
(
MachineInstr
*
MI
)
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Opcode has unknown scale!"
)
;
case
AArch64
::
LDRBBui
:
case
AArch64
::
LDURBBi
:
case
AArch64
::
LDRSBWui
:
case
AArch64
::
LDURSBWi
:
case
AArch64
::
STRBBui
:
case
AArch64
::
STURBBi
:
return
1
;
case
AArch64
::
LDRHHui
:
case
AArch64
::
LDURHHi
:
case
AArch64
::
LDRSHWui
:
case
AArch64
::
LDURSHWi
:
case
AArch64
::
STRHHui
:
case
AArch64
::
STURHHi
:
return
2
;
case
AArch64
::
LDRSui
:
case
AArch64
::
LDURSi
:
case
AArch64
::
LDRSWui
:
case
AArch64
::
LDURSWi
:
case
AArch64
::
LDRWui
:
case
AArch64
::
LDURWi
:
case
AArch64
::
STRSui
:
case
AArch64
::
STURSi
:
case
AArch64
::
STRWui
:
case
AArch64
::
STURWi
:
case
AArch64
::
LDPSi
:
case
AArch64
::
LDPSWi
:
case
AArch64
::
LDPWi
:
case
AArch64
::
STPSi
:
case
AArch64
::
STPWi
:
return
4
;
case
AArch64
::
LDRDui
:
case
AArch64
::
LDURDi
:
case
AArch64
::
LDRXui
:
case
AArch64
::
LDURXi
:
case
AArch64
::
STRDui
:
case
AArch64
::
STURDi
:
case
AArch64
::
STRXui
:
case
AArch64
::
STURXi
:
case
AArch64
::
LDPDi
:
case
AArch64
::
LDPXi
:
case
AArch64
::
STPDi
:
case
AArch64
::
STPXi
:
return
8
;
case
AArch64
::
LDRQui
:
case
AArch64
::
LDURQi
:
case
AArch64
::
STRQui
:
case
AArch64
::
STURQi
:
case
AArch64
::
LDPQi
:
case
AArch64
::
STPQi
:
return
16
;
}
}
</s>

Scaling factor for ( scaled or unscaled ) load or store .


<s>
void
XCoreRegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected"
)
;
MachineInstr
&
MI
=
*
II
;
MachineOperand
&
FrameOp
=
MI
.
getOperand
(
FIOperandNum
)
;
int
FrameIndex
=
FrameOp
.
getIndex
(
)
;
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
const
XCoreInstrInfo
&
TII
=
*
static_cast
<
const
XCoreInstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
const
XCoreFrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
int
Offset
=
MF
.
getFrameInfo
(
)
.
getObjectOffset
(
FrameIndex
)
;
int
StackSize
=
MF
.
getFrameInfo
(
)
.
getStackSize
(
)
;
LLVM_DEBUG
(
errs
(
)
<<
"\nFunction         : "
<<
MF
.
getName
(
)
<<
"\n"
)
;
LLVM_DEBUG
(
errs
(
)
<<
"<--------->\n"
)
;
LLVM_DEBUG
(
MI
.
print
(
errs
(
)
)
)
;
LLVM_DEBUG
(
errs
(
)
<<
"FrameIndex         : "
<<
FrameIndex
<<
"\n"
)
;
LLVM_DEBUG
(
errs
(
)
<<
"FrameOffset        : "
<<
Offset
<<
"\n"
)
;
LLVM_DEBUG
(
errs
(
)
<<
"StackSize          : "
<<
StackSize
<<
"\n"
)
;
Offset
+=
StackSize
;
Register
FrameReg
=
getFrameRegister
(
MF
)
;
if
(
MI
.
isDebugValue
(
)
)
{
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
)
;
return
;
}
Offset
+=
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
0
)
;
assert
(
Offset
%
4
==
0
&&
"Misaligned stack offset"
)
;
LLVM_DEBUG
(
errs
(
)
<<
"Offset             : "
<<
Offset
<<
"\n"
<<
"<--------->\n"
)
;
Offset
/=
4
;
unsigned
Reg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
assert
(
XCore
::
GRRegsRegClass
.
contains
(
Reg
)
&&
"Unexpected register operand"
)
;
if
(
TFI
->
hasFP
(
MF
)
)
{
if
(
isImmUs
(
Offset
)
)
InsertFPImmInst
(
II
,
TII
,
Reg
,
FrameReg
,
Offset
)
;
else
InsertFPConstInst
(
II
,
TII
,
Reg
,
FrameReg
,
Offset
,
RS
)
;
}
else
{
if
(
isImmU16
(
Offset
)
)
InsertSPImmInst
(
II
,
TII
,
Reg
,
Offset
)
;
else
InsertSPConstInst
(
II
,
TII
,
Reg
,
Offset
,
RS
)
;
}
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
MBB
.
erase
(
II
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .

XCore
XCore
0
"Unexpected"
XCore
XCore
XCore
"\nFunction         : "
"\n"
"<--------->\n"
"FrameIndex         : "
"\n"
"FrameOffset        : "
"\n"
"StackSize          : "
"\n"
1
1
1
0
4
0
"Misaligned stack offset"
"Offset             : "
"\n"
"<--------->\n"
4
0
XCore::GRRegsRegClass
"Unexpected register operand"