<s> MachineInstr * SIInstrInfo :: convertToThreeAddress ( MachineFunction :: iterator & MBB , MachineInstr & MI , LiveVariables * LV ) const { bool IsF16 = false ; switch ( MI . getOpcode ( ) ) { default : return nullptr ; case AMDGPU :: V_MAC_F16_e64 : IsF16 = true ; LLVM_FALLTHROUGH ; case AMDGPU :: V_MAC_F32_e64 : break ; case AMDGPU :: V_MAC_F16_e32 : IsF16 = true ; LLVM_FALLTHROUGH ; case AMDGPU :: V_MAC_F32_e32 : { int Src0Idx = AMDGPU :: getNamedOperandIdx ( MI . getOpcode ( ) , AMDGPU :: OpName :: src0 ) ; const MachineOperand * Src0 = & MI . getOperand ( Src0Idx ) ; if ( Src0 -> isImm ( ) && ! isInlineConstant ( MI , Src0Idx , * Src0 ) ) return nullptr ; break ; } } const MachineOperand * Dst = getNamedOperand ( MI , AMDGPU :: OpName :: vdst ) ; const MachineOperand * Src0 = getNamedOperand ( MI , AMDGPU :: OpName :: src0 ) ; const MachineOperand * Src0Mods = getNamedOperand ( MI , AMDGPU :: OpName :: src0_modifiers ) ; const MachineOperand * Src1 = getNamedOperand ( MI , AMDGPU :: OpName :: src1 ) ; const MachineOperand * Src1Mods = getNamedOperand ( MI , AMDGPU :: OpName :: src1_modifiers ) ; const MachineOperand * Src2 = getNamedOperand ( MI , AMDGPU :: OpName :: src2 ) ; const MachineOperand * Clamp = getNamedOperand ( MI , AMDGPU :: OpName :: clamp ) ; const MachineOperand * Omod = getNamedOperand ( MI , AMDGPU :: OpName :: omod ) ; return BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( IsF16 ? AMDGPU :: V_MAD_F16 : AMDGPU :: V_MAD_F32 ) ) . add ( * Dst ) . addImm ( Src0Mods ? Src0Mods -> getImm ( ) : 0 ) . add ( * Src0 ) . addImm ( Src1Mods ? Src1Mods -> getImm ( ) : 0 ) . add ( * Src1 ) . addImm ( 0 ) . add ( * Src2 ) . addImm ( Clamp ? Clamp -> getImm ( ) : 0 ) . addImm ( Omod ? Omod -> getImm ( ) : 0 ) ; } </s>

convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag .


"Invalid offset within MOS instruction for modifier!"

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static rtx arm_expand_ternop_builtin ( enum insn_code icode , tree exp , rtx target ) { rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , 0 ) ; tree arg1 = CALL_EXPR_ARG ( exp , 1 ) ; tree arg2 = CALL_EXPR_ARG ( exp , 2 ) ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; rtx op2 = expand_normal ( arg2 ) ; machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; machine_mode mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ 2 ] . mode ; machine_mode mode2 = insn_data [ icode ] . operand [ 3 ] . mode ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( VECTOR_MODE_P ( mode2 ) ) op2 = safe_vector_operand ( op2 , mode2 ) ; if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; gcc_assert ( ( GET_MODE ( op0 ) == mode0 || GET_MODE ( op0 ) == VOIDmode ) && ( GET_MODE ( op1 ) == mode1 || GET_MODE ( op1 ) == VOIDmode ) && ( GET_MODE ( op2 ) == mode2 || GET_MODE ( op2 ) == VOIDmode ) ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ 2 ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; if ( ! ( * insn_data [ icode ] . operand [ 3 ] . predicate ) ( op2 , mode2 ) ) op2 = copy_to_mode_reg ( mode2 , op2 ) ; pat = GEN_FCN ( icode ) ( target , op0 , op1 , op2 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>


<s> bool ix86_expand_fp_movcc ( rtx operands [ ] ) { machine_mode mode = GET_MODE ( operands [ 0 ] ) ; enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; rtx tmp , compare_op ; rtx op0 = XEXP ( operands [ 1 ] , 0 ) ; rtx op1 = XEXP ( operands [ 1 ] , 1 ) ; if ( TARGET_SSE_MATH && SSE_FLOAT_MODE_P ( mode ) ) { machine_mode cmode ; cmode = GET_MODE ( op0 ) ; if ( cmode == VOIDmode ) cmode = GET_MODE ( op1 ) ; if ( cmode != mode ) return false ; code = ix86_prepare_sse_fp_compare_args ( operands [ 0 ] , code , & op0 , & op1 ) ; if ( code == UNKNOWN ) return false ; if ( ix86_expand_sse_fp_minmax ( operands [ 0 ] , code , op0 , op1 , operands [ 2 ] , operands [ 3 ] ) ) return true ; tmp = ix86_expand_sse_cmp ( operands [ 0 ] , code , op0 , op1 , operands [ 2 ] , operands [ 3 ] ) ; ix86_expand_sse_movcc ( operands [ 0 ] , tmp , operands [ 2 ] , operands [ 3 ] ) ; return true ; } if ( GET_MODE ( op0 ) == TImode || ( GET_MODE ( op0 ) == DImode && ! TARGET_64BIT ) ) return false ; compare_op = ix86_expand_compare ( code , op0 , op1 ) ; if ( ! fcmov_comparison_operator ( compare_op , VOIDmode ) ) { tmp = gen_reg_rtx ( QImode ) ; ix86_expand_setcc ( tmp , code , op0 , op1 ) ; compare_op = ix86_expand_compare ( NE , tmp , const0_rtx ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , gen_rtx_IF_THEN_ELSE ( mode , compare_op , operands [ 2 ] , operands [ 3 ] ) ) ) ; return true ; } </s>

Expand a floating-point conditional move . Return true if successful .


<s> static sbitmap aarch64_get_separate_components ( void ) { sbitmap components = sbitmap_alloc ( LAST_SAVED_REGNUM + 1 ) ; bitmap_clear ( components ) ; for ( unsigned regno = 0 ; regno <= LAST_SAVED_REGNUM ; regno ++ ) if ( aarch64_register_saved_on_entry ( regno ) ) { machine_mode mode = aarch64_reg_save_mode ( regno ) ; if ( mode == VNx2DImode && BYTES_BIG_ENDIAN ) continue ; poly_int64 offset = cfun -> machine -> frame . reg_offset [ regno ] ; if ( flag_stack_clash_protection && maybe_ne ( cfun -> machine -> frame . below_hard_fp_saved_regs_size , 0 ) && known_eq ( offset , 0 ) ) continue ; if ( frame_pointer_needed ) offset -= cfun -> machine -> frame . below_hard_fp_saved_regs_size ; else offset += crtl -> outgoing_args_size ; if ( aarch64_sve_mode_p ( mode ) ? offset_9bit_signed_scaled_p ( mode , offset ) : offset_12bit_unsigned_scaled_p ( mode , offset ) ) bitmap_set_bit ( components , regno ) ; } if ( frame_pointer_needed ) bitmap_clear_bit ( components , HARD_FRAME_POINTER_REGNUM ) ; if ( cfun -> machine -> frame . spare_pred_reg != INVALID_REGNUM ) bitmap_clear_bit ( components , cfun -> machine -> frame . spare_pred_reg ) ; unsigned reg1 = cfun -> machine -> frame . wb_candidate1 ; unsigned reg2 = cfun -> machine -> frame . wb_candidate2 ; if ( reg2 != INVALID_REGNUM ) bitmap_clear_bit ( components , reg2 ) ; if ( reg1 != INVALID_REGNUM ) bitmap_clear_bit ( components , reg1 ) ; bitmap_clear_bit ( components , LR_REGNUM ) ; bitmap_clear_bit ( components , SP_REGNUM ) ; return components ; } </s>


A subroutine of expand_vec_perm_even_odd_1 . Implement extract-even and extract-odd permutations of two V32QImode and V16QImode operand with two vpshufb insns , vpor and vpermq . We should have already failed all two or three instruction sequences .


<s> static rtx ix86_expand_sse_comi ( const struct builtin_description * d , tree exp , rtx target ) { rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , 0 ) ; tree arg1 = CALL_EXPR_ARG ( exp , 1 ) ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; machine_mode mode0 = insn_data [ d -> icode ] . operand [ 0 ] . mode ; machine_mode mode1 = insn_data [ d -> icode ] . operand [ 1 ] . mode ; enum rtx_code comparison = d -> comparison ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( d -> flag & BUILTIN_DESC_SWAP_OPERANDS ) std :: swap ( op0 , op1 ) ; target = gen_reg_rtx ( SImode ) ; emit_move_insn ( target , const0_rtx ) ; target = gen_rtx_SUBREG ( QImode , target , 0 ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! insn_data [ d -> icode ] . operand [ 0 ] . predicate ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ( optimize && ! register_operand ( op1 , mode1 ) ) || ! insn_data [ d -> icode ] . operand [ 1 ] . predicate ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( d -> icode ) ( op0 , op1 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; emit_insn ( gen_rtx_SET ( VOIDmode , gen_rtx_STRICT_LOW_PART ( VOIDmode , target ) , gen_rtx_fmt_ee ( comparison , QImode , SET_DEST ( pat ) , const0_rtx ) ) ) ; return SUBREG_REG ( target ) ; } </s>

Subroutine of ix86_expand_builtin to take care of comi insns .


"\t\tcvta.local.u%d %%r%d, %%simtstack_ar + "

Output code for allocating per-lane storage and switching soft-stack pointer . ENTERING indicates whether we are entering or leaving non-uniform execution . PTR is the register pointing to allocated storage , it is assigned to on entering and used to restore state on leaving . SIZE and ALIGN are used only on entering .


<s> int standard_sse_constant_p ( rtx x ) { machine_mode mode = GET_MODE ( x ) ; if ( x == const0_rtx || x == CONST0_RTX ( GET_MODE ( x ) ) ) return 1 ; if ( vector_all_ones_operand ( x , mode ) ) switch ( mode ) { case V16QImode : case V8HImode : case V4SImode : case V2DImode : if ( TARGET_SSE2 ) return 2 ; case V32QImode : case V16HImode : case V8SImode : case V4DImode : if ( TARGET_AVX2 ) return 2 ; case V64QImode : case V32HImode : case V16SImode : case V8DImode : if ( TARGET_AVX512F ) return 2 ; default : break ; } return 0 ; } </s>

Return 1 if X is all 0s and 2 if x is all 1s in supported SSE/AVX vector mode .


<s> const PPCTargetMachine & getTargetMachine ( ) const { return TM ; } </s>

Return the target machine ( if available ) .


<s> machreg_t inet_lnaof ( machreg_t in ) { return _inet_lnaof ( in << SHIFT_BITS ) ; } </s>

< arpa/inet.h > has unsigned long inet_lnaof ( struct in_addr ) ; ( IRIX 6.2 ) in_addr_t inet_lnaof ( struct in_addr ) ; ( IRIX 6.5 ) in_addr_t is a 32-bit int .


<s> bool rs6000_quadword_masked_address_p ( const_rtx expr ) { if ( GET_CODE ( expr ) == AND ) { const_rtx operand1 = XEXP ( expr , 0 ) ; const_rtx operand2 = XEXP ( expr , 1 ) ; if ( ( REG_P ( operand1 ) || rs6000_sum_of_two_registers_p ( operand1 ) ) && CONST_SCALAR_INT_P ( operand2 ) && INTVAL ( operand2 ) == - 16 ) return true ; } return false ; } </s>

Return true iff EXPR represents an address expression that masks off the low-order 4 bits in the style of an lvx or stvx rtl pattern .


<s> bool Cpu0TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> void ix86_expand_fp_absneg_operator ( enum rtx_code code , machine_mode mode , rtx operands [ ] ) { rtx mask , set , dst , src ; bool use_sse = false ; bool vector_mode = VECTOR_MODE_P ( mode ) ; machine_mode vmode = mode ; if ( vector_mode ) use_sse = true ; else if ( mode == TFmode ) use_sse = true ; else if ( TARGET_SSE_MATH ) { use_sse = SSE_FLOAT_MODE_P ( mode ) ; if ( mode == SFmode ) vmode = V4SFmode ; else if ( mode == DFmode ) vmode = V2DFmode ; } if ( use_sse ) mask = ix86_build_signbit_mask ( vmode , vector_mode , code == ABS ) ; else mask = NULL_RTX ; dst = operands [ 0 ] ; src = operands [ 1 ] ; set = gen_rtx_fmt_e ( code , mode , src ) ; set = gen_rtx_SET ( dst , set ) ; if ( mask ) { rtx use , clob ; rtvec par ; use = gen_rtx_USE ( VOIDmode , mask ) ; if ( vector_mode ) par = gen_rtvec ( 2 , set , use ) ; else { clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; par = gen_rtvec ( 3 , set , use , clob ) ; } emit_insn ( gen_rtx_PARALLEL ( VOIDmode , par ) ) ; } else emit_insn ( set ) ; } </s>

Generate code for floating point ABS or NEG .


<s> static void aarch64_emit_store_exclusive ( machine_mode mode , rtx bval , rtx mem , rtx rval , rtx model_rtx ) { if ( mode == TImode ) emit_insn ( gen_aarch64_store_exclusive_pair ( bval , mem , operand_subword ( rval , 0 , 0 , TImode ) , operand_subword ( rval , 1 , 0 , TImode ) , model_rtx ) ) ; else emit_insn ( gen_aarch64_store_exclusive ( mode , bval , mem , rval , model_rtx ) ) ; } </s>


<s> static void arm_add_cfa_adjust_cfa_note ( rtx insn , int size , rtx dest , rtx src ) { rtx dwarf ; RTX_FRAME_RELATED_P ( insn ) = 1 ; dwarf = gen_rtx_SET ( dest , plus_constant ( Pmode , src , size ) ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , dwarf ) ; } </s>

Add a REG_CFA_ADJUST_CFA REG note to INSN . SIZE is the offset to be adjusted . DEST and SRC might be stack_pointer_rtx or hard_frame_pointer_rtx .


<s> const MSP430Subtarget * getSubtargetImpl ( ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> MachineInstr * SIInstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr & MI , ArrayRef < unsigned > Ops , MachineBasicBlock :: iterator InsertPt , int FrameIndex , LiveIntervals * LIS , VirtRegMap * VRM ) const { if ( MI . isFullCopy ( ) ) { Register DstReg = MI . getOperand ( 0 ) . getReg ( ) ; Register SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; if ( DstReg == AMDGPU :: M0 && SrcReg . isVirtual ( ) ) { MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & AMDGPU :: SReg_32_XM0RegClass ) ; return nullptr ; } if ( SrcReg == AMDGPU :: M0 && DstReg . isVirtual ( ) ) { MF . getRegInfo ( ) . constrainRegClass ( DstReg , & AMDGPU :: SReg_32_XM0RegClass ) ; return nullptr ; } } return nullptr ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s>
bool
AArch64InstrInfo
::
shouldClusterMemOps
(
MachineInstr
&
FirstLdSt
,
MachineInstr
&
SecondLdSt
,
unsigned
NumLoads
)
const
{
if
(
NumLoads
>
1
)
return
false
;
if
(
!
isPairableLdStInst
(
FirstLdSt
)
||
!
isPairableLdStInst
(
SecondLdSt
)
)
return
false
;
unsigned
FirstOpc
=
FirstLdSt
.
getOpcode
(
)
;
unsigned
SecondOpc
=
SecondLdSt
.
getOpcode
(
)
;
if
(
!
canPairLdStOpc
(
FirstOpc
,
SecondOpc
)
)
return
false
;
if
(
!
isCandidateToMergeOrPair
(
FirstLdSt
)
||
!
isCandidateToMergeOrPair
(
SecondLdSt
)
)
return
false
;
int64_t
Offset1
=
FirstLdSt
.
getOperand
(
2
)
.
getImm
(
)
;
if
(
isUnscaledLdSt
(
FirstOpc
)
&&
!
scaleOffset
(
FirstOpc
,
Offset1
)
)
return
false
;
int64_t
Offset2
=
SecondLdSt
.
getOperand
(
2
)
.
getImm
(
)
;
if
(
isUnscaledLdSt
(
SecondOpc
)
&&
!
scaleOffset
(
SecondOpc
,
Offset2
)
)
return
false
;
if
(
Offset1
>
63
||
Offset1
<
64
)
return
false
;
assert
(
Offset1
<=
Offset2
&&
"Caller should have ordered offsets."
)
;
return
Offset1
+
1
==
Offset2
;
}
</s>

Returns true if the two given memory operations should be scheduled adjacent .


<s> const PPCSubtarget * PPCTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < PPCSubtarget > ( TargetTriple , CPU , computeFSAdditions ( FS , getOptLevel ( ) , getTargetTriple ( ) ) , * this ) ; } return I . get ( ) ; } </s>

PowerPC PPC PPC "target-cpu" "target-features" PPC


<s> static bool nds32_pic_tls_group ( rtx_insn * def_insn , enum nds32_relax_insn_type relax_type , int sym_type ) { df_ref def_record ; df_link * link ; rtx_insn * use_insn = NULL ; rtx pat , new_pat ; def_record = DF_INSN_DEFS ( def_insn ) ; for ( link = DF_REF_CHAIN ( def_record ) ; link ; link = link -> next ) { if ( ! DF_REF_INSN_INFO ( link -> ref ) ) continue ; use_insn = DF_REF_INSN ( link -> ref ) ; if ( ! dominated_by_p ( CDI_DOMINATORS , BLOCK_FOR_INSN ( use_insn ) , BLOCK_FOR_INSN ( def_insn ) ) ) return FALSE ; if ( ! active_insn_p ( use_insn ) ) return FALSE ; switch ( relax_type ) { case RELAX_ORI : if ( ( sym_type == UNSPEC_TLSLE || sym_type == UNSPEC_GOTOFF ) && ( recog_memoized ( use_insn ) == CODE_FOR_addsi3 ) ) { pat = XEXP ( PATTERN ( use_insn ) , 1 ) ; new_pat = gen_rtx_UNSPEC ( SImode , gen_rtvec ( 2 , XEXP ( pat , 0 ) , XEXP ( pat , 1 ) ) , UNSPEC_ADD32 ) ; validate_replace_rtx ( pat , new_pat , use_insn ) ; nds32_group_infos . safe_push ( use_insn ) ; } else if ( nds32_plus_reg_load_store_p ( use_insn ) && ! nds32_sp_base_or_plus_load_store_p ( use_insn ) ) nds32_group_infos . safe_push ( use_insn ) ; else return FALSE ; break ; default : return FALSE ; } } return TRUE ; } </s>

Group the PIC and TLS relax candidate instructions for linker .


<s> static void epiphany_trampoline_init ( rtx tramp_mem , tree fndecl , rtx cxt ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx tramp = force_reg ( Pmode , XEXP ( tramp_mem , 0 ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( Pmode , tramp , 0 ) ) , gen_rtx_IOR ( SImode , GEN_INT ( 0x4002000b ) , EPIPHANY_LOW_RTX ( fnaddr ) ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( Pmode , tramp , 4 ) ) , gen_rtx_IOR ( SImode , GEN_INT ( 0x5002000b ) , EPIPHANY_HIGH_RTX ( fnaddr ) ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( Pmode , tramp , 8 ) ) , gen_rtx_IOR ( SImode , GEN_INT ( 0x2002800b ) , EPIPHANY_LOW_RTX ( cxt ) ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( Pmode , tramp , 12 ) ) , gen_rtx_IOR ( SImode , GEN_INT ( 0x3002800b ) , EPIPHANY_HIGH_RTX ( cxt ) ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( Pmode , tramp , 16 ) ) , GEN_INT ( 0x0802014f ) ) ; } </s>

Emit RTL insns to initialize the variable parts of a trampoline . FNADDR is an RTX for the address of the function 's pure code . CXT is an RTX for the static chain value for the function .


<s> void AlphaInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; BuildMI ( MBB , MI , DL , get ( Alpha :: BISr ) , Alpha :: R31 ) . addReg ( Alpha :: R31 ) . addReg ( Alpha :: R31 ) ; } </s>

Insert a noop into the instruction stream at the specified point .


"insertBranch must not be told to insert a fallthrough"

"AVR branch conditions have one component!"

"Unconditional branch with multiple successors!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> bool arc_sets_cc_p ( rtx_insn * insn ) { if ( NONJUMP_INSN_P ( insn ) ) if ( rtx_sequence * seq = dyn_cast < rtx_sequence * > ( PATTERN ( insn ) ) ) insn = seq -> insn ( seq -> len ( ) - 1 ) ; return arc_attr_type ( insn ) == TYPE_COMPARE ; } </s>

Return true if insn sets the condition codes .


<s> void thumb2_asm_output_opcode ( FILE * stream ) { char buff [ 5 ] ; int n ; if ( arm_condexec_mask ) { for ( n = 0 ; n < arm_condexec_masklen ; n ++ ) buff [ n ] = ( arm_condexec_mask & ( 1 << n ) ) ? 't' : 'e' ; buff [ n ] = 0 ; asm_fprintf ( stream , "i%s\t%s\n\t" , buff , arm_condition_codes [ arm_current_cc ] ) ; arm_condexec_mask = 0 ; } } </s>


<s> bool Thumb1FrameInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > 0 ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , TII . get ( ARM :: tPOP ) ) ; AddDefaultPred ( MIB ) ; bool NumRegs = false ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( Reg == ARM :: LR ) { if ( isVarArg ) continue ; Reg = ARM :: PC ; ( * MIB ) . setDesc ( TII . get ( ARM :: tPOP_RET ) ) ; MI = MBB . erase ( MI ) ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; NumRegs = true ; } if ( NumRegs ) MBB . insert ( MI , & * MIB ) ; else MF . DeleteMachineInstr ( MIB ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s>
bool
MipsAsmParser
::
ParseInstruction
(
StringRef
Name
,
SMLoc
NameLoc
,
SmallVectorImpl
<
MCParsedAsmOperand
*
>
&
Operands
)
{
if
(
requestsDoubleOperand
(
Name
)
)
{
setFpFormat
(
FP_FORMAT_D
)
;
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Name
,
NameLoc
)
)
;
}
else
{
setDefaultFpFormat
(
)
;
size_t
Start
=
0
,
Next
=
Name
.
find
(
'.'
)
;
StringRef
Mnemonic
=
Name
.
slice
(
Start
,
Next
)
;
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Mnemonic
,
NameLoc
)
)
;
if
(
Next
!=
StringRef
::
npos
)
{
size_t
Dot
=
Name
.
find
(
'.'
,
Next
+
1
)
;
StringRef
Format
=
Name
.
slice
(
Next
,
Dot
)
;
if
(
Dot
==
StringRef
::
npos
)
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Format
,
NameLoc
)
)
;
else
{
if
(
Name
.
startswith
(
"c."
)
)
{
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
"."
,
NameLoc
)
)
;
int
Cc
=
ConvertCcString
(
Format
)
;
if
(
Cc
==
1
)
{
return
Error
(
NameLoc
,
"Invalid conditional code"
)
;
}
SMLoc
E
=
SMLoc
::
getFromPointer
(
Parser
.
getTok
(
)
.
getLoc
(
)
.
getPointer
(
)
1
)
;
Operands
.
push_back
(
MipsOperand
::
CreateImm
(
MCConstantExpr
::
Create
(
Cc
,
getContext
(
)
)
,
NameLoc
,
E
)
)
;
}
else
{
return
parseMathOperation
(
Name
,
NameLoc
,
Operands
)
;
}
Format
=
Name
.
slice
(
Dot
,
StringRef
::
npos
)
;
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Format
,
NameLoc
)
)
;
}
setFpFormat
(
Format
)
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
EatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
EatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
EatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Mips
Mips
MipsOperand::CreateToken
0
MipsOperand::CreateToken
1
MipsOperand::CreateToken
"c."
MipsOperand::CreateToken
"."
1
"Invalid conditional code"
1
MipsOperand::CreateImm
MipsOperand::CreateToken
"unexpected token in argument list"
"unexpected token in argument list"
"unexpected token in argument list"


<s> int HexagonFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; FrameReg = RI -> getFrameRegister ( MF ) ; return MF . getFrameInfo ( ) -> getObjectOffset ( FI ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> SDValue HexagonTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( isHvxOperation ( N , DCI . DAG ) ) { if ( SDValue V = PerformHvxDAGCombine ( N , DCI ) ) return V ; return SDValue ( ) ; } SDValue Op ( N , 0 ) ; const SDLoc & dl ( Op ) ; unsigned Opc = Op . getOpcode ( ) ; if ( Opc == HexagonISD :: P2D ) { SDValue P = Op . getOperand ( 0 ) ; switch ( P . getOpcode ( ) ) { case HexagonISD :: PTRUE : return DCI . DAG . getConstant ( - 1 , dl , ty ( Op ) ) ; case HexagonISD :: PFALSE : return getZero ( dl , ty ( Op ) , DCI . DAG ) ; default : break ; } } else if ( Opc == ISD :: VSELECT ) { SDValue Cond = Op . getOperand ( 0 ) ; if ( Cond -> getOpcode ( ) == ISD :: XOR ) { SDValue C0 = Cond . getOperand ( 0 ) , C1 = Cond . getOperand ( 1 ) ; if ( C1 -> getOpcode ( ) == HexagonISD :: PTRUE ) { SDValue VSel = DCI . DAG . getNode ( ISD :: VSELECT , dl , ty ( Op ) , C0 , Op . getOperand ( 2 ) , Op . getOperand ( 1 ) ) ; return VSel ; } } } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> bool HexagonInstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( MI . isDebugInstr ( ) ) return false ; if ( MI . isCall ( ) ) { if ( doesNotReturn ( MI ) ) return true ; for ( auto I : MBB -> successors ( ) ) if ( I -> isEHPad ( ) ) return true ; } if ( MI . getDesc ( ) . isTerminator ( ) || MI . isPosition ( ) ) return true ; if ( MI . getOpcode ( ) == TargetOpcode :: INLINEASM_BR ) return true ; if ( MI . isInlineAsm ( ) && ! ScheduleInlineAsm ) return true ; return false ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> static void pdp11_asm_print_operand ( FILE * file , rtx x , int code ) { REAL_VALUE_TYPE r ; long sval [ 2 ] ; if ( code == '#' ) fprintf ( file , "#" ) ; else if ( code == '@' ) { if ( TARGET_UNIX_ASM ) fprintf ( file , "*" ) ; else fprintf ( file , "@" ) ; } else if ( GET_CODE ( x ) == REG ) fprintf ( file , "%s" , reg_names [ REGNO ( x ) ] ) ; else if ( GET_CODE ( x ) == MEM ) output_address ( XEXP ( x , 0 ) ) ; else if ( GET_CODE ( x ) == CONST_DOUBLE && GET_MODE ( x ) != SImode ) { REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; REAL_VALUE_TO_TARGET_DOUBLE ( r , sval ) ; fprintf ( file , "$%#lo" , sval [ 0 ] >> 16 ) ; } else { putc ( '$' , file ) ; output_addr_const_pdp11 ( file , x ) ; } } </s>

Special format operators handled here : # -- output the correct immediate operand marker for the assembler dialect . @ -- output the correct indirect marker for the assembler dialect . o -- emit a constant value as a number ( not an immediate operand ) in octal .


<s> bool empty ( ) const { return getSGPRNum ( ) == 0 && getVGPRNum ( ) == 0 ; } </s>

Determine whether this version information is empty ( e.g. , all version components are zero ) .


<s> static void ix86_emit_cmove ( rtx dst , rtx src , enum rtx_code code , rtx op1 , rtx op2 ) { rtx t ; if ( TARGET_CMOVE ) { t = ix86_expand_compare ( code , op1 , op2 ) ; emit_insn ( gen_rtx_SET ( dst , gen_rtx_IF_THEN_ELSE ( GET_MODE ( dst ) , t , src , dst ) ) ) ; } else { rtx_code_label * nomove = gen_label_rtx ( ) ; emit_cmp_and_jump_insns ( op1 , op2 , reverse_condition ( code ) , const0_rtx , GET_MODE ( op1 ) , 1 , nomove ) ; emit_move_insn ( dst , src ) ; emit_label ( nomove ) ; } } </s>

Emit conditional move of SRC to DST with condition OP1 CODE OP2 .


<s> static int comparator ( const void * va , const void * vb ) { const avr_mcu_t * mcu_a = * ( const avr_mcu_t * const * ) va ; const avr_mcu_t * mcu_b = * ( const avr_mcu_t * const * ) vb ; const char * a = mcu_a -> name ; const char * b = mcu_b -> name ; int c = c_prefix ( a ) - c_prefix ( b ) ; if ( c ) return c ; c = ( int ) mcu_a -> flash_size - ( int ) mcu_b -> flash_size ; if ( c ) return c ; while ( * a && * b ) { c = c_number ( a ) - c_number ( b ) ; if ( c ) return c ; if ( * a != * b ) return * a - * b ; a ++ ; b ++ ; } return * a - * b ; } </s>

Compare two MCUs and order them for easy lookup .


Function to tell the preprocessor about the defines for the current target .


"cannot optimize division for both latency and throughput"


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; bool Changed = false ; if ( MF . size ( ) < 2 ) return Changed ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed = true ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool X86AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { static const uint8_t Nops [ 10 ] [ 10 ] = { { 0x90 } , { 0x66 , 0x90 } , { 0x0f , 0x1f , 0x00 } , { 0x0f , 0x1f , 0x40 , 0x00 } , { 0x0f , 0x1f , 0x44 , 0x00 , 0x00 } , { 0x66 , 0x0f , 0x1f , 0x44 , 0x00 , 0x00 } , { 0x0f , 0x1f , 0x80 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x66 , 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x66 , 0x2e , 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , } ; if ( ! STI . getFeatureBits ( ) [ X86 :: FeatureNOPL ] ) { for ( uint64_t i = 0 ; i < Count ; ++ i ) OW -> write8 ( 0x90 ) ; return true ; } uint64_t MaxNopLength = 10 ; if ( STI . getFeatureBits ( ) [ X86 :: ProcIntelSLM ] ) MaxNopLength = 7 ; else if ( STI . getFeatureBits ( ) [ X86 :: FeatureFast15ByteNOP ] ) MaxNopLength = 15 ; else if ( STI . getFeatureBits ( ) [ X86 :: FeatureFast11ByteNOP ] ) MaxNopLength = 11 ; do { const uint8_t ThisNopLength = ( uint8_t ) std :: min ( Count , MaxNopLength ) ; const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10 ; for ( uint8_t i = 0 ; i < Prefixes ; i ++ ) OW -> write8 ( 0x66 ) ; const uint8_t Rest = ThisNopLength - Prefixes ; for ( uint8_t i = 0 ; i < Rest ; i ++ ) OW -> write8 ( Nops [ Rest - 1 ] [ i ] ) ; Count -= ThisNopLength ; } while ( Count != 0 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s>
static
void
process_cfa_register
(
FILE
*
out_file
,
rtx
pat
,
bool
unwind
)
{
rtx
dest
=
SET_DEST
(
pat
)
;
rtx
src
=
SET_SRC
(
pat
)
;
int
dest_regno
=
REGNO
(
dest
)
;
int
src_regno
;
if
(
src
==
pc_rtx
)
{
if
(
unwind
)
fprintf
(
out_file
,
"\t.save rp, r%d\n"
,
ia64_debugger_regno
(
dest_regno
)
)
;
return
;
}
src_regno
=
REGNO
(
src
)
;
switch
(
src_regno
)
{
case
PR_REG
(
0
)
:
gcc_assert
(
dest_regno
==
current_frame_info
.
r
[
reg_save_pr
]
)
;
if
(
unwind
)
fprintf
(
out_file
,
"\t.save pr, r%d\n"
,
ia64_debugger_regno
(
dest_regno
)
)
;
break
;
case
AR_UNAT_REGNUM
:
gcc_assert
(
dest_regno
==
current_frame_info
.
r
[
reg_save_ar_unat
]
)
;
if
(
unwind
)
fprintf
(
out_file
,
"\t.save ar.unat, r%d\n"
,
ia64_debugger_regno
(
dest_regno
)
)
;
break
;
case
AR_LC_REGNUM
:
gcc_assert
(
dest_regno
==
current_frame_info
.
r
[
reg_save_ar_lc
]
)
;
if
(
unwind
)
fprintf
(
out_file
,
"\t.save ar.lc, r%d\n"
,
ia64_debugger_regno
(
dest_regno
)
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
</s>

This function processes a SET pattern for REG_CFA_REGISTER .

ia64
"\t.save rp, r%d\n"
0
"\t.save pr, r%d\n"
"\t.save ar.unat, r%d\n"
"\t.save ar.lc, r%d\n"


<s> bool TPCSetIndxCoalescer :: runOnMachineFunction ( MachineFunction & Func ) { if ( skipFunction ( Func . getFunction ( ) ) ) return false ; if ( ! EnableSetIndxCoalescer ) return false ; MF = & Func ; MRI = & MF -> getRegInfo ( ) ; TII = MF -> getSubtarget ( ) . getInstrInfo ( ) ; NumReplaced = 0 ; RemovedInstrs . clear ( ) ; AddedInstrs . clear ( ) ; bool Changed = false ; for ( auto & BB : Func ) { for ( auto & I : BB ) { if ( RemovedInstrs . count ( & I ) == 0 ) if ( isSET_INDX ( I . getOpcode ( ) ) ) { if ( processSetIndx ( & I ) ) Changed = true ; } } } for ( MachineInstr * MI : RemovedInstrs ) MI -> eraseFromParent ( ) ; return Changed ; } </s>


Constant pools are per function only when PC relative literal loads are true or we are in the large memory model .


<s> rtx rs6000_got_register ( rtx value ATTRIBUTE_UNUSED ) { if ( ! can_create_pseudo_p ( ) && ! df_regs_ever_live_p ( RS6000_PIC_OFFSET_TABLE_REGNUM ) ) df_set_regs_ever_live ( RS6000_PIC_OFFSET_TABLE_REGNUM , true ) ; crtl -> uses_pic_offset_table = 1 ; return pic_offset_table_rtx ; } </s>


<s> static rtx tilegx_got_symbol ( void ) { if ( g_got_symbol == NULL ) g_got_symbol = gen_rtx_SYMBOL_REF ( Pmode , "_GLOBAL_OFFSET_TABLE_" ) ; return g_got_symbol ; } </s>

Return the SYMBOL_REF for _GLOBAL_OFFSET_TABLE_ .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 EFLAGS copy lowering"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static bool aarch64_evpc_zip ( struct expand_vec_perm_d * d ) { unsigned int i , high , mask , nelt = d -> nelt ; rtx out , in0 , in1 , x ; rtx ( * gen ) ( rtx , rtx , rtx ) ; machine_mode vmode = d -> vmode ; if ( GET_MODE_UNIT_SIZE ( vmode ) > 8 ) return false ; high = nelt / 2 ; if ( d -> perm [ 0 ] == high ) ; else if ( d -> perm [ 0 ] == 0 ) high = 0 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt / 2 ; i ++ ) { unsigned elt = ( i + high ) & mask ; if ( d -> perm [ i * 2 ] != elt ) return false ; elt = ( elt + nelt ) & mask ; if ( d -> perm [ i * 2 + 1 ] != elt ) return false ; } if ( d -> testing_p ) return true ; in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN ) { x = in0 , in0 = in1 , in1 = x ; high = ! high ; } out = d -> target ; if ( high ) { switch ( vmode ) { case V16QImode : gen = gen_aarch64_zip2v16qi ; break ; case V8QImode : gen = gen_aarch64_zip2v8qi ; break ; case V8HImode : gen = gen_aarch64_zip2v8hi ; break ; case V4HImode : gen = gen_aarch64_zip2v4hi ; break ; case V4SImode : gen = gen_aarch64_zip2v4si ; break ; case V2SImode : gen = gen_aarch64_zip2v2si ; break ; case V2DImode : gen = gen_aarch64_zip2v2di ; break ; case V4HFmode : gen = gen_aarch64_zip2v4hf ; break ; case V8HFmode : gen = gen_aarch64_zip2v8hf ; break ; case V4SFmode : gen = gen_aarch64_zip2v4sf ; break ; case V2SFmode : gen = gen_aarch64_zip2v2sf ; break ; case V2DFmode : gen = gen_aarch64_zip2v2df ; break ; default : return false ; } } else { switch ( vmode ) { case V16QImode : gen = gen_aarch64_zip1v16qi ; break ; case V8QImode : gen = gen_aarch64_zip1v8qi ; break ; case V8HImode : gen = gen_aarch64_zip1v8hi ; break ; case V4HImode : gen = gen_aarch64_zip1v4hi ; break ; case V4SImode : gen = gen_aarch64_zip1v4si ; break ; case V2SImode : gen = gen_aarch64_zip1v2si ; break ; case V2DImode : gen = gen_aarch64_zip1v2di ; break ; case V4HFmode : gen = gen_aarch64_zip1v4hf ; break ; case V8HFmode : gen = gen_aarch64_zip1v8hf ; break ; case V4SFmode : gen = gen_aarch64_zip1v4sf ; break ; case V2SFmode : gen = gen_aarch64_zip1v2sf ; break ; case V2DFmode : gen = gen_aarch64_zip1v2df ; break ; default : return false ; } } emit_insn ( gen ( out , in0 , in1 ) ) ; return true ; } </s>

Recognize patterns suitable for the ZIP instructions .


<s> static bool mips_use_blocks_for_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , const_rtx x ATTRIBUTE_UNUSED ) { return ! TARGET_MIPS16_PCREL_LOADS ; } </s>

Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P . We ca n't use blocks for constants when we 're using a per-function constant pool .


<s> void OR1KPassConfig :: addPreEmitPass ( ) { addPass ( createOR1KDelaySlotFillerPass ( ) ) ; addPass ( createNEMESISPass ( ) ) ; addPass ( createZDCPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool ARMFrameInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned PushOpc = AFI -> isThumbFunction ( ) ? ARM :: t2STMDB_UPD : ARM :: STMDB_UPD ; unsigned PushOneOpc = AFI -> isThumbFunction ( ) ? ARM :: t2STR_PRE : ARM :: STR_PRE ; unsigned FltOpc = ARM :: VSTMDDB_UPD ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & isARMArea1Register ) ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & isARMArea2Register ) ; emitPushInst ( MBB , MI , CSI , FltOpc , 0 , true , & isARMArea3Register ) ; return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> int mips_const_insns ( rtx x ) { struct mips_integer_op codes [ MIPS_MAX_INTEGER_OPS ] ; enum mips_symbol_type symbol_type ; rtx offset ; switch ( GET_CODE ( x ) ) { case HIGH : if ( ! mips_symbolic_constant_p ( XEXP ( x , 0 ) , SYMBOL_CONTEXT_LEA , & symbol_type ) || ! mips_split_p [ symbol_type ] ) return 0 ; return TARGET_MIPS16 ? 4 : 1 ; case CONST_INT : if ( TARGET_MIPS16 ) return ( IN_RANGE ( INTVAL ( x ) , 0 , 255 ) ? 1 : SMALL_OPERAND_UNSIGNED ( INTVAL ( x ) ) ? 2 : IN_RANGE ( - INTVAL ( x ) , 0 , 255 ) ? 2 : SMALL_OPERAND_UNSIGNED ( - INTVAL ( x ) ) ? 3 : 0 ) ; return mips_build_integer ( codes , INTVAL ( x ) ) ; case CONST_VECTOR : if ( MSA_SUPPORTED_MODE_P ( GET_MODE ( x ) ) && mips_const_vector_same_int_p ( x , GET_MODE ( x ) , - 512 , 511 ) ) return 1 ; case CONST_DOUBLE : return ! TARGET_MIPS16 && x == CONST0_RTX ( GET_MODE ( x ) ) ? 1 : 0 ; case CONST : if ( CONST_GP_P ( x ) ) return 1 ; if ( mips_symbolic_constant_p ( x , SYMBOL_CONTEXT_LEA , & symbol_type ) ) return mips_symbol_insns ( symbol_type , MAX_MACHINE_MODE ) ; split_const ( x , & x , & offset ) ; if ( offset != 0 ) { int n = mips_const_insns ( x ) ; if ( n != 0 ) { if ( SMALL_INT ( offset ) ) return n + 1 ; else if ( ! targetm . cannot_force_const_mem ( GET_MODE ( x ) , x ) ) return n + 1 + mips_build_integer ( codes , INTVAL ( offset ) ) ; } } return 0 ; case SYMBOL_REF : case LABEL_REF : return mips_symbol_insns ( mips_classify_symbol ( x , SYMBOL_CONTEXT_LEA ) , MAX_MACHINE_MODE ) ; default : return 0 ; } } </s>


<s> Type * getType ( ) const { return Root -> getType ( ) ; } </s>

Overload to return most specific vector type .


<s> bool MOSInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { auto I = MBB . getFirstTerminator ( ) ; while ( I != MBB . end ( ) && I -> isCompare ( ) ) ++ I ; if ( I == MBB . end ( ) ) return false ; if ( ! I -> isBranch ( ) ) return true ; auto FirstBR = I ++ ; if ( FirstBR -> isPreISelOpcode ( ) ) return true ; TBB = getBranchDestBlock ( * FirstBR ) ; if ( ! TBB ) return true ; if ( FirstBR -> isConditionalBranch ( ) ) { Cond . push_back ( FirstBR -> getOperand ( 1 ) ) ; Cond . push_back ( FirstBR -> getOperand ( 2 ) ) ; } if ( I == MBB . end ( ) ) return false ; if ( ! I -> isBranch ( ) ) return true ; auto SecondBR = I ++ ; if ( I != MBB . end ( ) ) return true ; if ( ! SecondBR -> isUnconditionalBranch ( ) || SecondBR -> isPreISelOpcode ( ) ) return true ; FBB = getBranchDestBlock ( * SecondBR ) ; if ( ! FBB ) return true ; return false ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> bool compact_sda_memory_operand ( rtx op , machine_mode mode , bool short_p ) { rtx addr ; int size ; int align = 0 ; int mask = 0 ; if ( GET_CODE ( op ) != MEM ) return false ; if ( mode == VOIDmode ) mode = GET_MODE ( op ) ; size = GET_MODE_SIZE ( mode ) ; if ( size > UNITS_PER_WORD ) return false ; addr = XEXP ( op , 0 ) ; if ( ! legitimate_small_data_address_p ( addr , mode ) ) return false ; if ( ! short_p || size == 1 ) return true ; align = get_symbol_alignment ( addr ) ; switch ( mode ) { case E_HImode : mask = 1 ; break ; default : mask = 3 ; break ; } if ( align && ( ( align & mask ) == 0 ) ) return true ; return false ; } </s>

volatile cache option still to be handled .


<s> static int alpha_adjust_cost ( rtx_insn * insn , rtx link , rtx_insn * dep_insn , int cost ) { enum attr_type dep_insn_type ; if ( REG_NOTE_KIND ( link ) != 0 ) return cost ; if ( recog_memoized ( insn ) < 0 || recog_memoized ( dep_insn ) < 0 ) return cost ; dep_insn_type = get_attr_type ( dep_insn ) ; if ( dep_insn_type == TYPE_ILD || dep_insn_type == TYPE_FLD || dep_insn_type == TYPE_LDSYM ) cost += alpha_memory_latency - 1 ; return cost ; } </s>

Adjust the cost of a scheduling dependency . Return the new cost of a dependency LINK or INSN on DEP_INSN . COST is the current cost .


<s> TargetTransformInfo BPFTargetMachine :: getTargetTransformInfo ( const Function & F ) const { return TargetTransformInfo ( BPFTTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> void WebAssemblyFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { auto & MFI = MF . getFrameInfo ( ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( ! needsSP ( MF , MFI ) || ! needsSPWriteback ( MF , MFI ) ) return ; const auto * TII = MF . getSubtarget < WebAssemblySubtarget > ( ) . getInstrInfo ( ) ; auto & MRI = MF . getRegInfo ( ) ; auto InsertPt = MBB . getFirstTerminator ( ) ; DebugLoc DL ; if ( InsertPt != MBB . end ( ) ) DL = InsertPt -> getDebugLoc ( ) ; unsigned SPReg = 0 ; MachineBasicBlock :: iterator InsertAddr = InsertPt ; if ( StackSize ) { const TargetRegisterClass * PtrRC = MRI . getTargetRegisterInfo ( ) -> getPointerRegClass ( MF ) ; unsigned OffsetReg = MRI . createVirtualRegister ( PtrRC ) ; InsertAddr = BuildMI ( MBB , InsertPt , DL , TII -> get ( WebAssembly :: CONST_I32 ) , OffsetReg ) . addImm ( StackSize ) ; SPReg = MRI . createVirtualRegister ( PtrRC ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( WebAssembly :: ADD_I32 ) , SPReg ) . addReg ( hasFP ( MF ) ? WebAssembly :: FP32 : WebAssembly :: SP32 ) . addReg ( OffsetReg ) ; } else { SPReg = hasFP ( MF ) ? WebAssembly :: FP32 : WebAssembly :: SP32 ; } writeSPToMemory ( SPReg , MF , MBB , InsertAddr , InsertPt , DL ) ; } </s>


<s> bool X86FastISel :: isTypeLegal ( const Type * Ty , MVT & VT , bool AllowI1 ) { EVT evt = TLI . getValueType ( Ty , true ) ; if ( evt == MVT :: Other || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; if ( VT == MVT :: f64 && ! X86ScalarSSEf64 ) return false ; if ( VT == MVT :: f32 && ! X86ScalarSSEf32 ) return false ; if ( VT == MVT :: f80 ) return false ; return ( AllowI1 && VT == MVT :: i1 ) || TLI . isTypeLegal ( VT ) ; } </s>


<s> void PPCTTI :: getUnrollingPreferences ( const Function * F , Loop * L , UnrollingPreferences & UP ) const { if ( TM -> getSubtarget < PPCSubtarget > ( F ) . getDarwinDirective ( ) == PPC :: DIR_A2 ) { UP . Partial = UP . Runtime = true ; } TargetTransformInfo :: getUnrollingPreferences ( F , L , UP ) ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"SI annotate control flow"
;
}
</s>


<s> bool isReg ( ) const override { return isRegKind ( ) && ! Reg . Mods . hasModifiers ( ) ; } </s>


<s> bool AMDGPULateCodeGenPrepare :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; AC = & getAnalysis < AssumptionCacheTracker > ( ) . getAssumptionCache ( F ) ; DA = & getAnalysis < LegacyDivergenceAnalysis > ( ) ; bool Changed = false ; for ( auto & BB : F ) for ( Instruction & I : llvm :: make_early_inc_range ( BB ) ) Changed |= visit ( I ) ; return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool HexagonGenInsert :: removeDeadCode ( MachineDomTreeNode * N ) { bool Changed = false ; for ( auto * DTN : children < MachineDomTreeNode * > ( N ) ) Changed |= removeDeadCode ( DTN ) ; MachineBasicBlock * B = N -> getBlock ( ) ; std :: vector < MachineInstr * > Instrs ; for ( auto I = B -> rbegin ( ) , E = B -> rend ( ) ; I != E ; ++ I ) Instrs . push_back ( & * I ) ; for ( auto I = Instrs . begin ( ) , E = Instrs . end ( ) ; I != E ; ++ I ) { MachineInstr * MI = * I ; unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == TargetOpcode :: LIFETIME_START || Opc == TargetOpcode :: LIFETIME_END ) continue ; bool Store = false ; if ( MI -> isInlineAsm ( ) || ! MI -> isSafeToMove ( nullptr , Store ) ) continue ; bool AllDead = true ; SmallVector < unsigned , 2 > Regs ; for ( const MachineOperand & MO : MI -> operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; Register R = MO . getReg ( ) ; if ( ! R . isVirtual ( ) || ! MRI -> use_nodbg_empty ( R ) ) { AllDead = false ; break ; } Regs . push_back ( R ) ; } if ( ! AllDead ) continue ; B -> erase ( MI ) ; for ( unsigned I = 0 , N = Regs . size ( ) ; I != N ; ++ I ) MRI -> markUsesInDebugValueAsUndef ( Regs [ I ] ) ; Changed = true ; } return Changed ; } </s>

Remove all dead instructions between the I and E .


<s> static rtx gen_frame_mem_offset ( enum machine_mode mode , rtx reg , int offset ) { rtx int_rtx , offset_rtx ; int_rtx = GEN_INT ( offset ) ; if ( ( TARGET_SPE_ABI && SPE_VECTOR_MODE ( mode ) ) || ( TARGET_E500_DOUBLE && mode == DFmode ) ) { offset_rtx = gen_rtx_REG ( Pmode , FIXED_SCRATCH ) ; emit_move_insn ( offset_rtx , int_rtx ) ; } else offset_rtx = int_rtx ; return gen_rtx_MEM ( mode , gen_rtx_PLUS ( Pmode , reg , offset_rtx ) ) ; } </s>

Emit an offset memory reference suitable for a frame store , while converting to a valid addressing mode .


<s> bool X86ATTAsmParser :: ParseInstruction ( const StringRef & Name , SMLoc NameLoc , SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { StringRef PatchedName = StringSwitch < StringRef > ( Name ) . Case ( "sal" , "shl" ) . Case ( "salb" , "shlb" ) . Case ( "sall" , "shll" ) . Case ( "salq" , "shlq" ) . Case ( "salw" , "shlw" ) . Case ( "repe" , "rep" ) . Case ( "repz" , "rep" ) . Case ( "repnz" , "repne" ) . Default ( Name ) ; Operands . push_back ( X86Operand :: CreateToken ( PatchedName , NameLoc ) ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( getLexer ( ) . is ( AsmToken :: Star ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( X86Operand :: CreateToken ( "*" , Loc ) ) ; Parser . Lex ( ) ; } if ( X86Operand * Op = ParseOperand ( ) ) Operands . push_back ( Op ) ; else return true ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( X86Operand * Op = ParseOperand ( ) ) Operands . push_back ( Op ) ; else return true ; } } if ( ( Name . startswith ( "shr" ) || Name . startswith ( "sar" ) || Name . startswith ( "shl" ) ) && Operands . size ( ) == 3 && static_cast < X86Operand * > ( Operands [ 1 ] ) -> isImm ( ) && isa < MCConstantExpr > ( static_cast < X86Operand * > ( Operands [ 1 ] ) -> getImm ( ) ) && cast < MCConstantExpr > ( static_cast < X86Operand * > ( Operands [ 1 ] ) -> getImm ( ) ) -> getValue ( ) == 1 ) Operands . erase ( Operands . begin ( ) + 1 ) ; return false ; } </s>

ParseInstruction - Parse one assembly instruction .


<s>
const
char
*
output_condmove_single
(
rtx
operands
[
]
,
rtx
insn
)
{
rtx
dest
=
operands
[
2
]
;
rtx
src
=
operands
[
3
]
;
if
(
GET_CODE
(
dest
)
==
REG
)
{
int
dest_regno
=
REGNO
(
dest
)
;
enum
machine_mode
mode
=
GET_MODE
(
dest
)
;
if
(
GPR_P
(
dest_regno
)
)
{
if
(
GET_CODE
(
src
)
==
REG
)
{
int
src_regno
=
REGNO
(
src
)
;
if
(
GPR_P
(
src_regno
)
)
return
"cmov %z3, %2, %1, %e0"
;
else
if
(
FPR_P
(
src_regno
)
)
return
"cmovfg %3, %2, %1, %e0"
;
}
else
if
(
GET_CODE
(
src
)
==
MEM
)
{
switch
(
mode
)
{
default
:
break
;
case
QImode
:
return
"cldsb%I3%U3 %M3, %2, %1, %e0"
;
case
HImode
:
return
"cldsh%I3%U3 %M3, %2, %1, %e0"
;
case
SImode
:
case
SFmode
:
return
"cld%I3%U3 %M3, %2, %1, %e0"
;
}
}
else
if
(
ZERO_P
(
src
)
)
return
"cmov %., %2, %1, %e0"
;
}
else
if
(
FPR_P
(
dest_regno
)
)
{
if
(
GET_CODE
(
src
)
==
REG
)
{
int
src_regno
=
REGNO
(
src
)
;
if
(
GPR_P
(
src_regno
)
)
return
"cmovgf %3, %2, %1, %e0"
;
else
if
(
FPR_P
(
src_regno
)
)
{
if
(
TARGET_HARD_FLOAT
)
return
"cfmovs %3,%2,%1,%e0"
;
else
return
"cmor %3, %3, %2, %1, %e0"
;
}
}
else
if
(
GET_CODE
(
src
)
==
MEM
)
{
if
(
mode
==
SImode
||
mode
==
SFmode
)
return
"cldf%I3%U3 %M3, %2, %1, %e0"
;
}
else
if
(
ZERO_P
(
src
)
)
return
"cmovgf %., %2, %1, %e0"
;
}
}
else
if
(
GET_CODE
(
dest
)
==
MEM
)
{
if
(
GET_CODE
(
src
)
==
REG
)
{
int
src_regno
=
REGNO
(
src
)
;
enum
machine_mode
mode
=
GET_MODE
(
dest
)
;
if
(
GPR_P
(
src_regno
)
)
{
switch
(
mode
)
{
default
:
break
;
case
QImode
:
return
"cstb%I2%U2 %3, %M2, %1, %e0"
;
case
HImode
:
return
"csth%I2%U2 %3, %M2, %1, %e0"
;
case
SImode
:
case
SFmode
:
return
"cst%I2%U2 %3, %M2, %1, %e0"
;
}
}
else
if
(
FPR_P
(
src_regno
)
&&
(
mode
==
SImode
||
mode
==
SFmode
)
)
return
"cstf%I2%U2 %3, %M2, %1, %e0"
;
}
else
if
(
ZERO_P
(
src
)
)
{
enum
machine_mode
mode
=
GET_MODE
(
dest
)
;
switch
(
mode
)
{
default
:
break
;
case
QImode
:
return
"cstb%I2%U2 %., %M2, %1, %e0"
;
case
HImode
:
return
"csth%I2%U2 %., %M2, %1, %e0"
;
case
SImode
:
case
SFmode
:
return
"cst%I2%U2 %., %M2, %1, %e0"
;
}
}
}
fatal_insn
(
"bad output_condmove_single operand"
,
insn
)
;
return
""
;
}
</s>

Return a string to output a single word conditional move . Operand0 -- EQ/NE of ccr register and 0 Operand1 -- CCR register Operand2 -- destination Operand3 -- source


"You cannot use the same Regs with MOVSX_RR"

"You cannot use the same Reg Classes with MOVSX_RR"


<s> bool AArch64LowerHomogeneousPrologEpilog :: runOnModule ( Module & M ) { if ( skipModule ( M ) ) return false ; MachineModuleInfo * MMI = & getAnalysis < MachineModuleInfoWrapperPass > ( ) . getMMI ( ) ; return AArch64LowerHomogeneousPE ( & M , MMI ) . run ( ) ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> bool mayStore ( ) const { return Store ; } </s>

Return true if this instruction could possibly modify memory .


<s> unsigned getSize ( ) const { return Size ; } </s>

Return the number of bytes in the encoding of this instruction , or zero if the encoding size can not be known from the opcode .


<s> void rs6000_expand_vector_init ( rtx target , rtx vals ) { enum machine_mode mode = GET_MODE ( target ) ; enum machine_mode inner_mode = GET_MODE_INNER ( mode ) ; int n_elts = GET_MODE_NUNITS ( mode ) ; int n_var = 0 , one_var = - 1 ; bool all_same = true , all_const_zero = true ; rtx x , mem ; int i ; for ( i = 0 ; i < n_elts ; ++ i ) { x = XVECEXP ( vals , 0 , i ) ; if ( ! CONSTANT_P ( x ) ) ++ n_var , one_var = i ; else if ( x != CONST0_RTX ( inner_mode ) ) all_const_zero = false ; if ( i > 0 && ! rtx_equal_p ( x , XVECEXP ( vals , 0 , 0 ) ) ) all_same = false ; } if ( n_var == 0 ) { if ( mode != V4SFmode && all_const_zero ) { emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_XOR ( mode , target , target ) ) ) ; return ; } else if ( mode != V4SFmode && easy_vector_constant ( vals , mode ) ) { emit_insn ( gen_rtx_SET ( VOIDmode , target , vals ) ) ; return ; } else if ( all_same ) ; else { emit_move_insn ( target , gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , 0 ) ) ) ; return ; } } if ( all_same ) { mem = assign_stack_temp ( mode , GET_MODE_SIZE ( inner_mode ) , 0 ) ; emit_move_insn ( adjust_address_nv ( mem , inner_mode , 0 ) , XVECEXP ( vals , 0 , 0 ) ) ; x = gen_rtx_UNSPEC ( VOIDmode , gen_rtvec ( 1 , const0_rtx ) , UNSPEC_LVE ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , gen_rtx_SET ( VOIDmode , target , mem ) , x ) ) ) ; x = gen_rtx_VEC_SELECT ( inner_mode , target , gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 1 , const0_rtx ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_VEC_DUPLICATE ( mode , x ) ) ) ; return ; } if ( n_var == 1 ) { rtx copy = copy_rtx ( vals ) ; XVECEXP ( copy , 0 , one_var ) = XVECEXP ( vals , 0 , ( one_var + 1 ) % n_elts ) ; rs6000_expand_vector_init ( target , copy ) ; rs6000_expand_vector_set ( target , XVECEXP ( vals , 0 , one_var ) , one_var ) ; return ; } mem = assign_stack_temp ( mode , GET_MODE_SIZE ( mode ) , 0 ) ; for ( i = 0 ; i < n_elts ; i ++ ) emit_move_insn ( adjust_address_nv ( mem , inner_mode , i * GET_MODE_SIZE ( inner_mode ) ) , XVECEXP ( vals , 0 , i ) ) ; emit_move_insn ( target , mem ) ; } </s>


"stack limit expression is not supported"

Emit the correct code for allocating stack space , as insns . If COPY_R12 , make sure a copy of the old frame is left in r12 . The generated code may use hard register 0 as a temporary .


<s> const MCPhysReg * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const ARMSubtarget & STI = MF -> getSubtarget < ARMSubtarget > ( ) ; bool UseSplitPush = STI . splitFramePushPop ( * MF ) ; const MCPhysReg * RegList = STI . isTargetDarwin ( ) ? CSR_iOS_SaveList : ( UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList ) ; const Function * F = MF -> getFunction ( ) ; if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F -> hasFnAttribute ( "interrupt" ) ) { if ( STI . isMClass ( ) ) { return UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList ; } else if ( F -> getFnAttribute ( "interrupt" ) . getValueAsString ( ) == "FIQ" ) { return CSR_FIQ_SaveList ; } else { return CSR_GenericInt_SaveList ; } } if ( STI . getTargetLowering ( ) -> supportSwiftError ( ) && F -> getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) { if ( STI . isTargetDarwin ( ) ) return CSR_iOS_SwiftError_SaveList ; return UseSplitPush ? CSR_AAPCS_SplitPush_SwiftError_SaveList : CSR_AAPCS_SwiftError_SaveList ; } if ( STI . isTargetDarwin ( ) && F -> getCallingConv ( ) == CallingConv :: CXX_FAST_TLS ) return MF -> getInfo < ARMFunctionInfo > ( ) -> isSplitCSR ( ) ? CSR_iOS_CXX_TLS_PE_SaveList : CSR_iOS_CXX_TLS_SaveList ; return RegList ; } </s>

ARM ARM ARM ARM "interrupt" "interrupt" "FIQ" ARM


<s> static unsigned int aarch64_unspec_cond_code ( rtx_code code ) { switch ( code ) { case NE : return UNSPEC_COND_FCMNE ; case EQ : return UNSPEC_COND_FCMEQ ; case LT : return UNSPEC_COND_FCMLT ; case GT : return UNSPEC_COND_FCMGT ; case LE : return UNSPEC_COND_FCMLE ; case GE : return UNSPEC_COND_FCMGE ; case UNORDERED : return UNSPEC_COND_FCMUO ; default : gcc_unreachable ( ) ; } } </s>

Return the UNSPEC_COND_ * code for comparison CODE .


<s> bool tilepro_can_use_return_insn_p ( void ) { return ( reload_completed && cfun -> static_chain_decl == 0 && compute_total_frame_size ( ) == 0 && tilepro_current_function_is_leaf ( ) && ! crtl -> profile && ! df_regs_ever_live_p ( TILEPRO_LINK_REGNUM ) ) ; } </s>

Return nonzero if this function is known to have a null epilogue . This allows the optimizer to omit jumps to jumps if no stack was created .


"getBranchTargetOpValueMM expects only expressions or immediates"

getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch target operand .


<s> void PPCXCOFFStreamer :: emitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) { PPCMCCodeEmitter * Emitter = static_cast < PPCMCCodeEmitter * > ( getAssembler ( ) . getEmitterPtr ( ) ) ; if ( ! Emitter -> isPrefixedInstruction ( Inst ) ) { MCXCOFFStreamer :: emitInstruction ( Inst , STI ) ; return ; } emitPrefixedInstruction ( Inst , STI ) ; } </s>

Targets should implement this to emit instructions .


<s> static bool aarch64_bti_j_insn_p ( rtx_insn * insn ) { if ( ! insn || ! INSN_P ( insn ) ) return false ; rtx pat = PATTERN ( insn ) ; return GET_CODE ( pat ) == UNSPEC_VOLATILE && XINT ( pat , 1 ) == UNSPECV_BTI_J ; } </s>


Hook to validate the current # pragma GCC target and set the arch custom mode state . If ARGS is NULL , then POP_TARGET is used to reset the options .


<s>
MachineBasicBlock
::
iterator
AArch64FrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
const
AArch64InstrInfo
*
TII
=
static_cast
<
const
AArch64InstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
DebugLoc
DL
=
I
->
getDebugLoc
(
)
;
unsigned
Opc
=
I
->
getOpcode
(
)
;
bool
IsDestroy
=
Opc
==
TII
->
getCallFrameDestroyOpcode
(
)
;
uint64_t
CalleePopAmount
=
IsDestroy
I
->
getOperand
(
1
)
.
getImm
(
)
:
0
;
const
TargetFrameLowering
*
TFI
=
MF
.
getSubtarget
(
)
.
getFrameLowering
(
)
;
if
(
!
TFI
->
hasReservedCallFrame
(
MF
)
)
{
unsigned
Align
=
getStackAlignment
(
)
;
int64_t
Amount
=
I
->
getOperand
(
0
)
.
getImm
(
)
;
Amount
=
alignTo
(
Amount
,
Align
)
;
if
(
!
IsDestroy
)
Amount
=
Amount
;
if
(
CalleePopAmount
==
0
)
{
assert
(
Amount
>
0xffffff
&&
Amount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
Amount
,
TII
)
;
}
}
else
if
(
CalleePopAmount
!=
0
)
{
assert
(
CalleePopAmount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
CalleePopAmount
,
TII
)
;
}
return
MBB
.
erase
(
I
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static void * ix86_init_cost ( class loop * ) { unsigned * cost = XNEWVEC ( unsigned , 3 ) ; cost [ vect_prologue ] = cost [ vect_body ] = cost [ vect_epilogue ] = 0 ; return cost ; } </s>


<s> bool AArch64LowerHomogeneousPE :: run ( ) { bool Changed = false ; for ( auto & F : * M ) { if ( F . empty ( ) ) continue ; MachineFunction * MF = MMI -> getMachineFunction ( F ) ; if ( ! MF ) continue ; Changed |= runOnMachineFunction ( * MF ) ; } return Changed ; } </s>

Run the analysis pass over a function and produce a dominator tree .


<s> const RegisterBankInfo * RISCVSubtarget :: getRegBankInfo ( ) const { return RegBankInfo . get ( ) ; } </s>

If the information for the register banks is available , return it .


<s> const J2Subtarget * getSubtargetImpl ( const Function & F ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static bool aarch64_sve_pred_mode_p ( machine_mode mode ) { return ( TARGET_SVE && ( mode == VNx16BImode || mode == VNx8BImode || mode == VNx4BImode || mode == VNx2BImode ) ) ; } </s>

Return true if MODE is an SVE predicate mode .


<s>
void
ARMBaseInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
DebugLoc
::
getUnknownLoc
(
)
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
if
(
RC
==
ARM
::
GPRRegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
LDR
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addReg
(
0
)
.
addImm
(
0
)
)
;
}
else
if
(
RC
==
ARM
::
DPRRegisterClass
||
RC
==
ARM
::
DPR_VFP2RegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
FLDD
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
)
;
}
else
if
(
RC
==
ARM
::
SPRRegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
FLDS
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
)
;
}
else
{
assert
(
RC
==
ARM
::
QPRRegisterClass
&&
"Unknown regclass!"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
VLDRQ
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> const Region * getRegionFor ( const MachineBasicBlock * MBB ) { const auto * ML = MLI . getLoopFor ( MBB ) ; const auto * WE = WEI . getExceptionFor ( MBB ) ; if ( ! ML && ! WE ) return nullptr ; if ( ( ML && ! WE ) || ( ML && WE && ML -> getNumBlocks ( ) < WE -> getNumBlocks ( ) ) ) { if ( LoopMap . count ( ML ) ) return LoopMap [ ML ] . get ( ) ; LoopMap [ ML ] = llvm :: make_unique < ConcreteRegion < MachineLoop >> ( ML ) ; return LoopMap [ ML ] . get ( ) ; } else { if ( ExceptionMap . count ( WE ) ) return ExceptionMap [ WE ] . get ( ) ; ExceptionMap [ WE ] = llvm :: make_unique < ConcreteRegion < WebAssemblyException >> ( WE ) ; return ExceptionMap [ WE ] . get ( ) ; } } </s>

Get the smallest region that contains a BasicBlock .


<s> unsigned RISCVInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { return isSimpleMove ( MI , FrameIndex , RISCVII :: SimpleLoad ) ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> const KudeyarInstrInfo * getInstrInfo ( ) { return getTargetMachine ( ) . getInstrInfo ( ) ; } </s>


<s> enum reg_class pdp11_regno_reg_class ( int regno ) { if ( regno == ARG_POINTER_REGNUM ) return NOTSP_REG ; else if ( regno == CC_REGNUM || regno == FCC_REGNUM ) return CC_REGS ; else if ( regno > AC3_REGNUM ) return NO_LOAD_FPU_REGS ; else if ( regno >= AC0_REGNUM ) return LOAD_FPU_REGS ; else if ( regno == 6 ) return NOTR0_REG ; else if ( regno < 6 ) return NOTSP_REG ; else return GENERAL_REGS ; } </s>

Return the class number of the smallest class containing reg number REGNO .


<s> int HexagonInstrInfo :: getMinValue ( const MachineInstr * MI ) const { const uint64_t F = MI -> getDesc ( ) . TSFlags ; unsigned isSigned = ( F >> HexagonII :: ExtentSignedPos ) & HexagonII :: ExtentSignedMask ; unsigned bits = ( F >> HexagonII :: ExtentBitsPos ) & HexagonII :: ExtentBitsMask ; if ( isSigned ) return - 1 << ( bits - 1 ) ; else return 0 ; } </s>

Return the minimal unsigned value possible given these KnownBits .

Hexagon Hexagon HexagonII::ExtentSignedPos HexagonII::ExtentSignedMask HexagonII::ExtentBitsPos HexagonII::ExtentBitsMask 1 1 0


<s> bool RISCVAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { bool HasStdExtC = STI . getFeatureBits ( ) [ RISCV :: FeatureStdExtC ] ; unsigned MinNopLen = HasStdExtC ? 2 : 4 ; if ( ( Count % MinNopLen ) != 0 ) return false ; uint64_t Nop32Count = Count / 4 ; for ( uint64_t i = Nop32Count ; i != 0 ; -- i ) OS . write ( "\x13\0\0\0" , 4 ) ; if ( HasStdExtC ) { uint64_t Nop16Count = ( Count - Nop32Count * 4 ) / 2 ; for ( uint64_t i = Nop16Count ; i != 0 ; -- i ) OS . write ( "\x01\0" , 2 ) ; } return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
Cpu0
::
NumTargetFixupKinds
]
=
{
{
"fixup_Cpu0_16"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_32"
,
0
,
32
,
0
}
,
{
"fixup_Cpu0_REL32"
,
0
,
32
,
0
}
,
{
"fixup_Cpu0_24"
,
0
,
24
,
0
}
,
{
"fixup_Cpu0_HI16"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_LO16"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_GPREL16"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_LITERAL"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_GOT_Global"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_GOT_Local"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_PC24"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_Cpu0_CALL24"
,
0
,
24
,
0
}
,
{
"fixup_Cpu0_GPREL32"
,
0
,
32
,
0
}
,
{
"fixup_Cpu0_SHIFT5"
,
6
,
5
,
0
}
,
{
"fixup_Cpu0_SHIFT6"
,
6
,
5
,
0
}
,
{
"fixup_Cpu0_64"
,
0
,
64
,
0
}
,
{
"fixup_Cpu0_TLSGD"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_GOTTPREL"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_TPREL_HI"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_TPREL_LO"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_TLSLDM"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_DTPREL_HI"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_DTPREL_LO"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_Branch_PCRel"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s>
void
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
)
const
override
{
unsigned
NumBytes
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
.
TargetSize
/
8
;
Value
=
adjustFixupValue
(
Fixup
.
getKind
(
)
,
Value
)
;
if
(
!
Value
)
return
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static inline bool s390_preserve_gpr_arg_in_range_p ( int first , int last ) { int num_arg_regs = MIN ( crtl -> args . info . gprs + cfun -> va_list_gpr_size , GP_ARG_NUM_REG ) ; return ( num_arg_regs && s390_preserve_args_p && first <= GPR2_REGNUM + num_arg_regs - 1 && last >= GPR2_REGNUM ) ; } </s>

Return TRUE if any of the registers in range [ FIRST , LAST ] is saved because of -mpreserve-args .


<s> const uint16_t * PPCRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( Subtarget . isDarwinABI ( ) ) return Subtarget . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_SaveList : CSR_Darwin64_SaveList ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_SaveList : CSR_Darwin32_SaveList ) ; return Subtarget . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_SVR464_Altivec_SaveList : CSR_SVR464_SaveList ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR432_Altivec_SaveList : CSR_SVR432_SaveList ) ; } </s>


<s> void print ( raw_ostream & OS , const TargetMachine * TM = 0 ) const { if ( isReg ( ) ) { OS << PrintReg ( getReg ( ) ) ; } if ( isImm ( ) ) { OS << getImm ( ) ; } } </s>

print - Print a debug representation of the operand to the given stream .


<s> bool AArch64RedundantCopyElimination :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) Changed |= optimizeCopy ( & MBB ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( OSType ) ; return createSparcELFObjectWriter ( OS , is64Bit ( ) , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> unsigned MipsCodeEmitter :: getBranchTargetOpValue ( const MachineInstr & MI , unsigned OpNo ) const { MachineOperand MO = MI . getOperand ( OpNo ) ; emitMachineBasicBlock ( MO . getMBB ( ) , getRelocation ( MI , MO ) ) ; return 0 ; } </s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s> static bool riscv_compressed_lw_offset_p ( rtx x ) { return ( CONST_INT_P ( x ) && ( INTVAL ( x ) & 3 ) == 0 && IN_RANGE ( INTVAL ( x ) , 0 , CSW_MAX_OFFSET ) ) ; } </s>

Return true if x is an unsigned 5-bit immediate scaled by 4 .


<s> bool RedundantInstrElimination :: processBlock ( MachineBasicBlock & B , const RegisterSet & ) { bool Changed = false ; for ( auto I = B . begin ( ) , E = B . end ( ) , NextI = I ; I != E ; ++ I ) { NextI = std :: next ( I ) ; MachineInstr * MI = & * I ; if ( MI -> getOpcode ( ) == TargetOpcode :: COPY ) continue ; if ( MI -> hasUnmodeledSideEffects ( ) || MI -> isInlineAsm ( ) ) continue ; unsigned NumD = MI -> getDesc ( ) . getNumDefs ( ) ; if ( NumD != 1 ) continue ; BitTracker :: RegisterRef RD = MI -> getOperand ( 0 ) ; if ( ! BT . has ( RD . Reg ) ) continue ; const BitTracker :: RegisterCell & DC = BT . lookup ( RD . Reg ) ; auto At = MI -> isPHI ( ) ? B . getFirstNonPHI ( ) : MachineBasicBlock :: iterator ( MI ) ; for ( auto & Op : MI -> uses ( ) ) { if ( ! Op . isReg ( ) ) continue ; BitTracker :: RegisterRef RS = Op ; if ( ! BT . has ( RS . Reg ) ) continue ; if ( ! HBS :: isTransparentCopy ( RD , RS , MRI ) ) continue ; unsigned BN , BW ; if ( ! HBS :: getSubregMask ( RS , BN , BW , MRI ) ) continue ; const BitTracker :: RegisterCell & SC = BT . lookup ( RS . Reg ) ; if ( ! usedBitsEqual ( RD , RS ) && ! HBS :: isEqual ( DC , 0 , SC , BN , BW ) ) continue ; DebugLoc DL = MI -> getDebugLoc ( ) ; const TargetRegisterClass * FRC = HBS :: getFinalVRegClass ( RD , MRI ) ; unsigned NewR = MRI . createVirtualRegister ( FRC ) ; BuildMI ( B , At , DL , HII . get ( TargetOpcode :: COPY ) , NewR ) . addReg ( RS . Reg , 0 , RS . Sub ) ; HBS :: replaceSubWithSub ( RD . Reg , RD . Sub , NewR , 0 , MRI ) ; BT . put ( BitTracker :: RegisterRef ( NewR ) , SC ) ; Changed = true ; break ; } } return Changed ; } </s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s> MipsExprKind getKind ( ) const { return Kind ; } </s>


<s> void changeSection ( MCSection * Section , const MCExpr * Subsection ) override { LastMappingSymbols [ getPreviousSection ( ) . first ] = LastEMS ; LastEMS = LastMappingSymbols . lookup ( Section ) ; MCELFStreamer :: changeSection ( Section , Subsection ) ; } </s>

Update streamer for a new active section .


<s>
MachineBasicBlock
*
SparcTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown SELECT_CC!"
)
;
case
SP
::
SELECT_CC_Int_ICC
:
case
SP
::
SELECT_CC_FP_ICC
:
case
SP
::
SELECT_CC_DFP_ICC
:
case
SP
::
SELECT_CC_QFP_ICC
:
return
expandSelectCC
(
MI
,
BB
,
SP
::
BCOND
)
;
case
SP
::
SELECT_CC_Int_FCC
:
case
SP
::
SELECT_CC_FP_FCC
:
case
SP
::
SELECT_CC_DFP_FCC
:
case
SP
::
SELECT_CC_QFP_FCC
:
return
expandSelectCC
(
MI
,
BB
,
SP
::
FBCOND
)
;
case
SP
::
EH_SJLJ_SETJMP32ri
:
case
SP
::
EH_SJLJ_SETJMP32rr
:
return
emitEHSjLjSetJmp
(
MI
,
BB
)
;
case
SP
::
EH_SJLJ_LONGJMP32rr
:
case
SP
::
EH_SJLJ_LONGJMP32ri
:
return
emitEHSjLjLongJmp
(
MI
,
BB
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static tree altivec_build_resolved_builtin ( tree * args , int n , const struct altivec_builtin_types * desc ) { tree impl_fndecl = rs6000_builtin_decls [ desc -> overloaded_code ] ; tree ret_type = rs6000_builtin_type ( desc -> ret_type ) ; tree argtypes = TYPE_ARG_TYPES ( TREE_TYPE ( impl_fndecl ) ) ; tree arg_type [ 4 ] ; tree call ; int i ; for ( i = 0 ; i < n ; i ++ ) arg_type [ i ] = TREE_VALUE ( argtypes ) , argtypes = TREE_CHAIN ( argtypes ) ; if ( n == 3 && desc -> code == ALTIVEC_BUILTIN_VEC_VCMPGE_P && desc -> overloaded_code != ALTIVEC_BUILTIN_VCMPGEFP_P && desc -> overloaded_code != VSX_BUILTIN_XVCMPGEDP_P ) { std :: swap ( args [ 1 ] , args [ 2 ] ) ; std :: swap ( arg_type [ 1 ] , arg_type [ 2 ] ) ; args [ 0 ] = fold_build2 ( BIT_XOR_EXPR , TREE_TYPE ( args [ 0 ] ) , args [ 0 ] , build_int_cst ( NULL_TREE , 2 ) ) ; } switch ( n ) { case 0 : call = build_call_expr ( impl_fndecl , 0 ) ; break ; case 1 : call = build_call_expr ( impl_fndecl , 1 , fully_fold_convert ( arg_type [ 0 ] , args [ 0 ] ) ) ; break ; case 2 : call = build_call_expr ( impl_fndecl , 2 , fully_fold_convert ( arg_type [ 0 ] , args [ 0 ] ) , fully_fold_convert ( arg_type [ 1 ] , args [ 1 ] ) ) ; break ; case 3 : call = build_call_expr ( impl_fndecl , 3 , fully_fold_convert ( arg_type [ 0 ] , args [ 0 ] ) , fully_fold_convert ( arg_type [ 1 ] , args [ 1 ] ) , fully_fold_convert ( arg_type [ 2 ] , args [ 2 ] ) ) ; break ; case 4 : call = build_call_expr ( impl_fndecl , 4 , fully_fold_convert ( arg_type [ 0 ] , args [ 0 ] ) , fully_fold_convert ( arg_type [ 1 ] , args [ 1 ] ) , fully_fold_convert ( arg_type [ 2 ] , args [ 2 ] ) , fully_fold_convert ( arg_type [ 3 ] , args [ 3 ] ) ) ; break ; default : gcc_unreachable ( ) ; } return fold_convert ( ret_type , call ) ; } </s>

Build a tree for a function call to an Altivec non-overloaded builtin . The overloaded builtin that matched the types and args is described by DESC . The N arguments are given in ARGS , respectively . Actually the only thing it does is calling fold_convert on ARGS , with a small exception for vec_ { all , any } _ { ge , le } predicates .


<s> virtual unsigned int execute ( function * ) { return rest_of_insert_bti ( ) ; } </s>


<s> static bool aarch64_check_builtin_call ( location_t loc , vec < location_t > arg_loc , tree fndecl , tree orig_fndecl , unsigned int nargs , tree * args ) { unsigned int code = DECL_MD_FUNCTION_CODE ( fndecl ) ; unsigned int subcode = code >> AARCH64_BUILTIN_SHIFT ; switch ( code & AARCH64_BUILTIN_CLASS ) { case AARCH64_BUILTIN_GENERAL : return true ; case AARCH64_BUILTIN_SVE : return aarch64_sve :: check_builtin_call ( loc , arg_loc , subcode , orig_fndecl , nargs , args ) ; } gcc_unreachable ( ) ; } </s>


<s> static int ia64_unspec_may_trap_p ( const_rtx x , unsigned flags ) { switch ( XINT ( x , 1 ) ) { case UNSPEC_LDA : case UNSPEC_LDS : case UNSPEC_LDSA : case UNSPEC_LDCCLR : case UNSPEC_CHKACLR : case UNSPEC_CHKS : return may_trap_p_1 ( XVECEXP ( x , 0 , 0 ) , flags ) ; } return default_unspec_may_trap_p ( x , flags ) ; } </s>

Implement targetm.unspec_may_trap_p hook .


<s> void SparcPassConfig :: addPreEmitPass ( ) { addPass ( createSparcDelaySlotFillerPass ( getSparcTargetMachine ( ) ) ) ; if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> ignoreZeroFlag ( ) ) { addPass ( new IgnoreZeroFlag ( getSparcTargetMachine ( ) ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> performSDIVReplace ( ) ) { addPass ( new ReplaceSDIV ( getSparcTargetMachine ( ) ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> fixCallImmediates ( ) ) { addPass ( new FixCALL ( getSparcTargetMachine ( ) ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> fixFSMULD ( ) ) { addPass ( new FixFSMULD ( getSparcTargetMachine ( ) ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> replaceFMULS ( ) ) { addPass ( new ReplaceFMULS ( getSparcTargetMachine ( ) ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> preventRoundChange ( ) ) { addPass ( new PreventRoundChange ( getSparcTargetMachine ( ) ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> fixAllFDIVSQRT ( ) ) { addPass ( new FixAllFDIVSQRT ( getSparcTargetMachine ( ) ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> insertNOPsLoadStore ( ) ) { addPass ( new InsertNOPsLoadStore ( getSparcTargetMachine ( ) ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> insertNOPLoad ( ) ) { addPass ( new InsertNOPLoad ( getSparcTargetMachine ( ) ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> flushCacheLineSWAP ( ) ) { addPass ( new FlushCacheLineSWAP ( getSparcTargetMachine ( ) ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> insertNOPDoublePrecision ( ) ) { addPass ( new InsertNOPDoublePrecision ( getSparcTargetMachine ( ) ) ) ; } } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc


<s> static machine_mode arm_floatn_mode ( int n , bool extended ) { if ( ! extended && n == 16 ) return arm_fp16_format == ARM_FP16_FORMAT_IEEE ? HFmode : VOIDmode ; return default_floatn_mode ( n , extended ) ; } </s>

Implement TARGET_FLOATN_MODE . Make very sure that we do n't provide _Float16 if we are using anything other than ieee format for 16-bit floating point . Otherwise , punt to the default implementation .


<s> bool SIInstrInfo :: hasModifiers ( unsigned Opcode ) const { return AMDGPU :: getNamedOperandIdx ( Opcode , AMDGPU :: OpName :: src0_modifiers ) != - 1 ; } </s>

Return true if this instruction has any modifiers .


<s> void Cpu0InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI , O ) ; O << ";" ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> std :: string getName ( ) const { std :: stringstream s ; if ( MBB ) s << MBB -> getName ( ) . str ( ) << "[" << ID << "]" ; else { s << "header" << ID ; } return s . str ( ) ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s>
static
void
rs6000_parse_tls_size_option
(
void
)
{
if
(
rs6000_tls_size_string
==
0
)
return
;
else
if
(
strcmp
(
rs6000_tls_size_string
,
"16"
)
==
0
)
rs6000_tls_size
=
16
;
else
if
(
strcmp
(
rs6000_tls_size_string
,
"32"
)
==
0
)
rs6000_tls_size
=
32
;
else
if
(
strcmp
(
rs6000_tls_size_string
,
"64"
)
==
0
)
rs6000_tls_size
=
64
;
else
error
(
"bad value %qs for -mtls-size switch"
,
rs6000_tls_size_string
)
;
}
</s>

Validate and record the size specified with the -mtls-size option .


<s>
static
const
char
*
avr_out_load_psi_reg_no_disp_tiny
(
rtx_insn
*
insn
,
rtx
*
op
,
int
*
plen
)
{
rtx
dest
=
op
[
0
]
;
rtx
src
=
op
[
1
]
;
rtx
base
=
XEXP
(
src
,
0
)
;
int
reg_dest
=
true_regnum
(
dest
)
;
int
reg_base
=
true_regnum
(
base
)
;
if
(
reg_base
==
reg_dest
)
{
return
avr_asm_len
(
TINY_ADIW
(
%
E1
,
%
F1
,
2
)
CR_TAB
"ld %C0,%1"
CR_TAB
"ld __tmp_reg__,-%1"
CR_TAB
TINY_SBIW
(
%
E1
,
%
F1
,
1
)
CR_TAB
"ld %A0,%1"
CR_TAB
"mov %B0,__tmp_reg__"
,
op
,
plen
,
8
)
;
}
else
{
avr_asm_len
(
"ld %A0,%1+"
CR_TAB
"ld %B0,%1+"
CR_TAB
"ld %C0,%1"
,
op
,
plen
,
3
)
;
if
(
reg_dest
!=
reg_base
2
&&
!
reg_unused_after
(
insn
,
base
)
)
{
avr_asm_len
(
TINY_SBIW
(
%
E1
,
%
F1
,
2
)
,
op
,
plen
,
2
)
;
}
return
""
;
}
}
</s>

Handle loads of 24-bit types from memory to register .


<s> bool PPCTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_PPC ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> bool MipsTargetMachine :: addInstSelector ( PassManagerBase & PM , bool Fast ) { PM . add ( createMipsISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> TargetTransformInfo DLXTargetMachine :: getTargetTransformInfo ( const Function & F ) { return TargetTransformInfo ( DLXTTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> bool GeneralShuffle :: add ( SDValue Op , unsigned Elem ) { unsigned BytesPerElement = VT . getVectorElementType ( ) . getStoreSize ( ) ; EVT FromVT = Op . getNode ( ) ? Op . getValueType ( ) : VT ; unsigned FromBytesPerElement = FromVT . getVectorElementType ( ) . getStoreSize ( ) ; if ( FromBytesPerElement < BytesPerElement ) return false ; unsigned Byte = ( ( Elem * FromBytesPerElement ) % SystemZ :: VectorBytes + ( FromBytesPerElement - BytesPerElement ) ) ; while ( Op . getNode ( ) ) { if ( Op . getOpcode ( ) == ISD :: BITCAST ) Op = Op . getOperand ( 0 ) ; else if ( Op . getOpcode ( ) == ISD :: VECTOR_SHUFFLE && Op . hasOneUse ( ) ) { SmallVector < int , SystemZ :: VectorBytes > OpBytes ; getVPermMask ( cast < ShuffleVectorSDNode > ( Op ) , OpBytes ) ; int NewByte ; if ( ! getShuffleInput ( OpBytes , Byte , BytesPerElement , NewByte ) ) break ; if ( NewByte < 0 ) { addUndef ( ) ; return true ; } Op = Op . getOperand ( unsigned ( NewByte ) / SystemZ :: VectorBytes ) ; Byte = unsigned ( NewByte ) % SystemZ :: VectorBytes ; } else if ( Op . isUndef ( ) ) { addUndef ( ) ; return true ; } else break ; } unsigned OpNo = 0 ; for ( ; OpNo < Ops . size ( ) ; ++ OpNo ) if ( Ops [ OpNo ] == Op ) break ; if ( OpNo == Ops . size ( ) ) Ops . push_back ( Op ) ; unsigned Base = OpNo * SystemZ :: VectorBytes + Byte ; for ( unsigned I = 0 ; I < BytesPerElement ; ++ I ) Bytes . push_back ( Base + I ) ; return true ; } </s>


"Invalid number of NOP bytes requested!"

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s>
unsigned
HexagonTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
SelectionDAG
&
DAG
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"r19"
,
Hexagon
::
R19
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> const TargetRegisterClass * Thumb1RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & ARM :: tGPRRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> void ARMPassConfig :: addIRPasses ( ) { if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( TM ) ) ; const ARMSubtarget * Subtarget = & getARMSubtarget ( ) ; if ( Subtarget -> hasAnyDataBarrier ( ) && ! Subtarget -> isThumb1Only ( ) ) if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BRCOND : return LowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return LowerConstantPool ( Op , DAG ) ; case ISD :: DYNAMIC_STACKALLOC : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: BlockAddress : return LowerBlockAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return LowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( Op , DAG ) ; case ISD :: SELECT : return LowerSELECT ( Op , DAG ) ; case ISD :: SELECT_CC : return LowerSELECT_CC ( Op , DAG ) ; case ISD :: SETCC : return LowerSETCC ( Op , DAG ) ; case ISD :: VASTART : return LowerVASTART ( Op , DAG ) ; case ISD :: FCOPYSIGN : return LowerFCOPYSIGN ( Op , DAG ) ; case ISD :: FABS : return LowerFABS ( Op , DAG ) ; case ISD :: FRAMEADDR : return LowerFRAMEADDR ( Op , DAG ) ; case ISD :: RETURNADDR : return LowerRETURNADDR ( Op , DAG ) ; case ISD :: MEMBARRIER : return LowerMEMBARRIER ( Op , DAG ) ; case ISD :: ATOMIC_FENCE : return LowerATOMIC_FENCE ( Op , DAG ) ; case ISD :: SHL_PARTS : return LowerShiftLeftParts ( Op , DAG ) ; case ISD :: SRA_PARTS : return LowerShiftRightParts ( Op , DAG , true ) ; case ISD :: SRL_PARTS : return LowerShiftRightParts ( Op , DAG , false ) ; case ISD :: LOAD : return LowerLOAD ( Op , DAG ) ; case ISD :: STORE : return LowerSTORE ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::BRCOND ISD::ConstantPool ISD::DYNAMIC_STACKALLOC ISD::GlobalAddress ISD::BlockAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::SELECT ISD::SELECT_CC ISD::SETCC ISD::VASTART ISD::FCOPYSIGN ISD::FABS ISD::FRAMEADDR ISD::RETURNADDR ISD::MEMBARRIER ISD::ATOMIC_FENCE ISD::SHL_PARTS ISD::SRA_PARTS ISD::SRL_PARTS ISD::LOAD ISD::STORE


<s> static int cbranch_predicted_taken_p ( rtx insn ) { rtx x = find_reg_note ( insn , REG_BR_PROB , 0 ) ; if ( x ) { int pred_val = INTVAL ( XEXP ( x , 0 ) ) ; return pred_val >= REG_BR_PROB_BASE / 2 ; } return 0 ; } </s>

Return nonzero if INSN is annotated with a REG_BR_PROB note that indicates it 's a branch that 's predicted taken .


"force: group count = %d, can_issue_more = %d\n"

"done force: group count = %d, can_issue_more = %d\n"

Utility of the function redefine_groups . Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS in the same dispatch group . If so , insert nops before NEXT_INSN , in order to keep it `` far '' ( in a separate group ) from GROUP_INSNS , following one of the following schemes , depending on the value of the flag -minsert_sched_nops = X : ( 1 ) X == sched_finish_regroup_exact : insert exactly as many nops as needed in order to force NEXT_INSN into a separate group . ( 2 ) X < sched_finish_regroup_exact : insert exactly X nops . GROUP_END , CAN_ISSUE_MORE and GROUP_COUNT record the state after nop insertion ( has a group just ended , how many vacant issue slots remain in the last group , and how many dispatch groups were encountered so far ) .


<s> bool SIModeRegister :: runOnMachineFunction ( MachineFunction & MF ) { BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const SIInstrInfo * TII = ST . getInstrInfo ( ) ; for ( MachineBasicBlock & BB : MF ) processBlockPhase1 ( BB , TII ) ; for ( MachineBasicBlock & BB : MF ) Phase2List . push ( & BB ) ; while ( ! Phase2List . empty ( ) ) { processBlockPhase2 ( * Phase2List . front ( ) , TII ) ; Phase2List . pop ( ) ; } for ( MachineBasicBlock & BB : MF ) processBlockPhase3 ( BB , TII ) ; BlockInfo . clear ( ) ; return NumSetregInserted > 0 ; } </s>

runOnMachineFunction - Emit the function body .


<s>
bool
RISCVAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Operands
.
push_back
(
RISCVOperand
::
createToken
(
Name
,
NameLoc
,
isRV64
(
)
)
)
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
return
false
;
bool
ForceImmediate
=
(
Name
==
"call"
||
Name
==
"tail"
)
;
if
(
parseOperand
(
Operands
,
ForceImmediate
)
)
return
true
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
getLexer
(
)
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
false
)
)
return
true
;
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
getParser
(
)
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
getParser
(
)
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

RISCV
RISCV
RISCV
"call"
"tail"
"unexpected token"


<s> static bool nds32_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( regno >= FIRST_PSEUDO_REGISTER ) return true ; if ( ( TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE ) && NDS32_IS_FPR_REGNUM ( regno ) ) { if ( NDS32_IS_EXT_FPR_REGNUM ( regno ) ) return ( NDS32_FPR_REGNO_OK_FOR_DOUBLE ( regno ) && ( mode == DFmode ) ) ; else if ( mode == SFmode || mode == SImode ) return NDS32_FPR_REGNO_OK_FOR_SINGLE ( regno ) ; else if ( mode == DFmode ) return NDS32_FPR_REGNO_OK_FOR_DOUBLE ( regno ) ; return false ; } if ( regno <= NDS32_LAST_GPR_REGNUM ) return ( targetm . hard_regno_nregs ( regno , mode ) == 1 || ! ( ( regno ) & 1 ) ) ; return false ; } </s>


<s> static void reorg_emit_nops ( rtx * call_labels ) { bool first ; rtx last_call ; rtx_insn * prev ; int prev_clock , earliest_bb_end ; int prev_implicit_nops ; rtx_insn * insn = get_insns ( ) ; insn = next_real_insn ( insn ) ; last_call = prev = NULL ; prev_clock = - 1 ; earliest_bb_end = 0 ; prev_implicit_nops = 0 ; first = true ; while ( insn ) { int this_clock = - 1 ; rtx_insn * next ; int max_cycles = 0 ; next = next_real_insn ( insn ) ; if ( DEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER || shadow_or_blockage_p ( insn ) || JUMP_TABLE_DATA_P ( insn ) ) goto next_insn ; if ( ! c6x_flag_schedule_insns2 ) PUT_MODE ( insn , TImode ) ; else { int cycles ; this_clock = insn_get_clock ( insn ) ; if ( this_clock != prev_clock ) { PUT_MODE ( insn , TImode ) ; if ( ! first ) { cycles = this_clock - prev_clock ; cycles -= prev_implicit_nops ; if ( cycles > 1 ) { rtx nop = emit_nop_after ( cycles - 1 , prev ) ; insn_set_clock ( nop , prev_clock + prev_implicit_nops + 1 ) ; } } prev_clock = this_clock ; if ( last_call && insn_get_clock ( last_call ) + 6 <= this_clock ) { emit_label_before ( call_labels [ INSN_UID ( last_call ) ] , insn ) ; last_call = NULL_RTX ; } prev_implicit_nops = 0 ; } } if ( recog_memoized ( insn ) >= 0 && ( c6x_flag_schedule_insns2 || ! returning_call_p ( insn ) ) ) { max_cycles = get_attr_cycles ( insn ) ; if ( get_attr_type ( insn ) == TYPE_CALLP ) prev_implicit_nops = 5 ; } else max_cycles = 1 ; if ( returning_call_p ( insn ) ) last_call = insn ; if ( c6x_flag_schedule_insns2 ) { gcc_assert ( this_clock >= 0 ) ; if ( earliest_bb_end < this_clock + max_cycles ) earliest_bb_end = this_clock + max_cycles ; } else if ( max_cycles > 1 ) emit_nop_after ( max_cycles - 1 , insn ) ; prev = insn ; first = false ; next_insn : if ( c6x_flag_schedule_insns2 && ( next == NULL_RTX || ( GET_MODE ( next ) == TImode && INSN_INFO_ENTRY ( INSN_UID ( next ) ) . ebb_start ) ) && earliest_bb_end > 0 ) { int cycles = earliest_bb_end - prev_clock ; if ( cycles > 1 ) { prev = emit_nop_after ( cycles - 1 , prev ) ; insn_set_clock ( prev , prev_clock + prev_implicit_nops + 1 ) ; } earliest_bb_end = 0 ; prev_clock = - 1 ; first = true ; if ( last_call ) emit_label_after ( call_labels [ INSN_UID ( last_call ) ] , prev ) ; last_call = NULL_RTX ; } insn = next ; } } </s>

Called as part of c6x_reorg . This function emits multi-cycle NOP insns as required for correctness . CALL_LABELS is the array that holds the return labels for call insns ; we emit these here if scheduling was run earlier .


<s> static int hppa_address_cost ( rtx X , machine_mode mode ATTRIBUTE_UNUSED , addr_space_t as ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { switch ( GET_CODE ( X ) ) { case REG : case PLUS : case LO_SUM : return 1 ; case HIGH : return 2 ; default : return 4 ; } } </s>

For the HPPA , REG and REG+CONST is cost 0 and addresses involving symbolic constants are cost 2 . PIC addresses are very expensive . It is no coincidence that this has the same structure as GO_IF_LEGITIMATE_ADDRESS .


<s>
MachineBasicBlock
*
WebAssemblyTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
const
TargetInstrInfo
&
TII
=
*
Subtarget
->
getInstrInfo
(
)
;
DebugLoc
DL
=
MI
.
getDebugLoc
(
)
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unexpected instr type to insert"
)
;
case
WebAssembly
::
FP_TO_SINT_I32_F32
:
return
LowerFPToInt
(
MI
,
DL
,
BB
,
TII
,
false
,
false
,
false
,
WebAssembly
::
I32_TRUNC_S_F32
)
;
case
WebAssembly
::
FP_TO_UINT_I32_F32
:
return
LowerFPToInt
(
MI
,
DL
,
BB
,
TII
,
true
,
false
,
false
,
WebAssembly
::
I32_TRUNC_U_F32
)
;
case
WebAssembly
::
FP_TO_SINT_I64_F32
:
return
LowerFPToInt
(
MI
,
DL
,
BB
,
TII
,
false
,
true
,
false
,
WebAssembly
::
I64_TRUNC_S_F32
)
;
case
WebAssembly
::
FP_TO_UINT_I64_F32
:
return
LowerFPToInt
(
MI
,
DL
,
BB
,
TII
,
true
,
true
,
false
,
WebAssembly
::
I64_TRUNC_U_F32
)
;
case
WebAssembly
::
FP_TO_SINT_I32_F64
:
return
LowerFPToInt
(
MI
,
DL
,
BB
,
TII
,
false
,
false
,
true
,
WebAssembly
::
I32_TRUNC_S_F64
)
;
case
WebAssembly
::
FP_TO_UINT_I32_F64
:
return
LowerFPToInt
(
MI
,
DL
,
BB
,
TII
,
true
,
false
,
true
,
WebAssembly
::
I32_TRUNC_U_F64
)
;
case
WebAssembly
::
FP_TO_SINT_I64_F64
:
return
LowerFPToInt
(
MI
,
DL
,
BB
,
TII
,
false
,
true
,
true
,
WebAssembly
::
I64_TRUNC_S_F64
)
;
case
WebAssembly
::
FP_TO_UINT_I64_F64
:
return
LowerFPToInt
(
MI
,
DL
,
BB
,
TII
,
true
,
true
,
true
,
WebAssembly
::
I64_TRUNC_U_F64
)
;
case
WebAssembly
::
CALL_RESULTS
:
case
WebAssembly
::
RET_CALL_RESULTS
:
return
LowerCallResults
(
MI
,
DL
,
BB
,
Subtarget
,
TII
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { bool Changed = false ; for ( MachineBasicBlock & B : llvm :: make_early_inc_range ( MF ) ) if ( processBlock ( B ) ) Changed = true ; return Changed ; } </s>


<s> bool isMem ( ) const override { return false ; } </s>


<s>
void
scalar_chain
::
add_insn
(
bitmap
candidates
,
unsigned
int
insn_uid
)
{
if
(
bitmap_bit_p
(
insns
,
insn_uid
)
)
return
;
if
(
dump_file
)
fprintf
(
dump_file
,
"  Adding insn %d to chain #%d\n"
,
insn_uid
,
chain_id
)
;
bitmap_set_bit
(
insns
,
insn_uid
)
;
rtx_insn
*
insn
=
DF_INSN_UID_GET
(
insn_uid
)
->
insn
;
rtx
def_set
=
single_set
(
insn
)
;
if
(
def_set
&&
REG_P
(
SET_DEST
(
def_set
)
)
&&
!
HARD_REGISTER_P
(
SET_DEST
(
def_set
)
)
)
bitmap_set_bit
(
defs
,
REGNO
(
SET_DEST
(
def_set
)
)
)
;
df_ref
ref
;
for
(
ref
=
DF_INSN_UID_DEFS
(
insn_uid
)
;
ref
;
ref
=
DF_REF_NEXT_LOC
(
ref
)
)
if
(
!
HARD_REGISTER_P
(
DF_REF_REG
(
ref
)
)
)
analyze_register_chain
(
candidates
,
ref
)
;
for
(
ref
=
DF_INSN_UID_USES
(
insn_uid
)
;
ref
;
ref
=
DF_REF_NEXT_LOC
(
ref
)
)
if
(
!
DF_REF_REG_MEM_P
(
ref
)
)
analyze_register_chain
(
candidates
,
ref
)
;
}
</s>

Add instruction into a chain . Return true if OK , false if the search was aborted .


<s> std :: vector < std :: string > push ( Px a ) { return D ( "push" , R ( a ) ) ; } </s>


<s> X86TargetLowering :: ConstraintType X86TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'R' : case 'q' : case 'Q' : case 'f' : case 't' : case 'u' : case 'y' : case 'x' : case 'v' : case 'Y' : case 'l' : case 'k' : return C_RegisterClass ; case 'a' : case 'b' : case 'c' : case 'd' : case 'S' : case 'D' : case 'A' : return C_Register ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'G' : case 'C' : case 'e' : case 'Z' : return C_Other ; default : break ; } } else if ( Constraint . size ( ) == 2 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'Y' : switch ( Constraint [ 1 ] ) { default : break ; case 'z' : case '0' : return C_Register ; case 'i' : case 'm' : case 'k' : case 't' : case '2' : return C_RegisterClass ; } } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> Register AMDGPURegisterBankInfo :: handleD16VData ( MachineIRBuilder & B , MachineRegisterInfo & MRI , Register Reg ) const { if ( ! Subtarget . hasUnpackedD16VMem ( ) ) return Reg ; const LLT S16 = LLT :: scalar ( 16 ) ; LLT StoreVT = MRI . getType ( Reg ) ; if ( ! StoreVT . isVector ( ) || StoreVT . getElementType ( ) != S16 ) return Reg ; auto Unmerge = B . buildUnmerge ( S16 , Reg ) ; SmallVector < Register , 4 > WideRegs ; for ( int I = 0 , E = Unmerge -> getNumOperands ( ) - 1 ; I != E ; ++ I ) WideRegs . push_back ( Unmerge . getReg ( I ) ) ; const LLT S32 = LLT :: scalar ( 32 ) ; int NumElts = StoreVT . getNumElements ( ) ; return B . buildMerge ( LLT :: fixed_vector ( NumElts , S32 ) , WideRegs ) . getReg ( 0 ) ; } </s>

Handle register layout difference for f16 images for some subtargets .


<s> static void arm_relayout_function ( tree fndecl ) { if ( DECL_USER_ALIGN ( fndecl ) ) return ; tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( ! callee_tree ) callee_tree = target_option_default_node ; struct cl_target_option * opts = TREE_TARGET_OPTION ( callee_tree ) ; SET_DECL_ALIGN ( fndecl , FUNCTION_ALIGNMENT ( FUNCTION_BOUNDARY_P ( opts -> x_target_flags ) ) ) ; } </s>

Hook to fix function 's alignment affected by target attribute .


"Stack realignment in presence of dynamic allocas is "

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> InstructionCost GCNTTIImpl :: getArithmeticReductionCost ( unsigned Opcode , VectorType * Ty , Optional < FastMathFlags > FMF , TTI :: TargetCostKind CostKind ) { if ( TTI :: requiresOrderedReduction ( FMF ) ) return BaseT :: getArithmeticReductionCost ( Opcode , Ty , FMF , CostKind ) ; EVT OrigTy = TLI -> getValueType ( DL , Ty ) ; if ( ! ST -> hasVOP3PInsts ( ) || OrigTy . getScalarSizeInBits ( ) != 16 ) return BaseT :: getArithmeticReductionCost ( Opcode , Ty , FMF , CostKind ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; return LT . first * getFullRateInstrCost ( ) ; } </s>

Calculate the cost of vector reduction intrinsics .


<s> const MCPhysReg * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const ARMSubtarget & STI = MF -> getSubtarget < ARMSubtarget > ( ) ; const MCPhysReg * RegList = STI . isTargetDarwin ( ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ; const Function * F = MF -> getFunction ( ) ; if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F -> hasFnAttribute ( "interrupt" ) ) { if ( STI . isMClass ( ) ) { return CSR_AAPCS_SaveList ; } else if ( F -> getFnAttribute ( "interrupt" ) . getValueAsString ( ) == "FIQ" ) { return CSR_FIQ_SaveList ; } else { return CSR_GenericInt_SaveList ; } } if ( STI . isTargetDarwin ( ) && F -> getCallingConv ( ) == CallingConv :: CXX_FAST_TLS ) return MF -> getInfo < ARMFunctionInfo > ( ) -> isSplitCSR ( ) ? CSR_iOS_CXX_TLS_PE_SaveList : CSR_iOS_CXX_TLS_SaveList ; return RegList ; } </s>


<s> MachineBasicBlock * MipsSETargetLowering :: EmitInstrWithCustomInserter ( MachineInstr * MI , MachineBasicBlock * BB ) const { switch ( MI -> getOpcode ( ) ) { default : return MipsTargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; case Mips :: BPOSGE32_PSEUDO : return emitBPOSGE32 ( MI , BB ) ; case Mips :: SNZ_B_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_B ) ; case Mips :: SNZ_H_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_H ) ; case Mips :: SNZ_W_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_W ) ; case Mips :: SNZ_D_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_D ) ; case Mips :: SNZ_V_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_V ) ; case Mips :: SZ_B_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_B ) ; case Mips :: SZ_H_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_H ) ; case Mips :: SZ_W_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_W ) ; case Mips :: SZ_D_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_D ) ; case Mips :: SZ_V_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_V ) ; case Mips :: COPY_FW_PSEUDO : return emitCOPY_FW ( MI , BB ) ; case Mips :: COPY_FD_PSEUDO : return emitCOPY_FD ( MI , BB ) ; case Mips :: INSERT_FW_PSEUDO : return emitINSERT_FW ( MI , BB ) ; case Mips :: INSERT_FD_PSEUDO : return emitINSERT_FD ( MI , BB ) ; case Mips :: FILL_FW_PSEUDO : return emitFILL_FW ( MI , BB ) ; case Mips :: FILL_FD_PSEUDO : return emitFILL_FD ( MI , BB ) ; case Mips :: FEXP2_W_1_PSEUDO : return emitFEXP2_W_1 ( MI , BB ) ; case Mips :: FEXP2_D_1_PSEUDO : return emitFEXP2_D_1 ( MI , BB ) ; } } </s>


"instructions, but the target does not support ARM mode execution."

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .