<s> static void alpha_expand_unaligned_load_words ( rtx * out_regs , rtx smem , HOST_WIDE_INT words , HOST_WIDE_INT ofs ) { rtx const im8 = GEN_INT ( - 8 ) ; rtx const i64 = GEN_INT ( 64 ) ; rtx ext_tmps [ MAX_MOVE_WORDS ] , data_regs [ MAX_MOVE_WORDS + 1 ] ; rtx sreg , areg , tmp , smema ; HOST_WIDE_INT i ; smema = XEXP ( smem , 0 ) ; if ( GET_CODE ( smema ) == LO_SUM ) smema = force_reg ( Pmode , smema ) ; for ( i = 0 ; i < words ; ++ i ) { data_regs [ i ] = out_regs [ i ] ; ext_tmps [ i ] = gen_reg_rtx ( DImode ) ; } data_regs [ words ] = gen_reg_rtx ( DImode ) ; if ( ofs != 0 ) smem = adjust_address ( smem , GET_MODE ( smem ) , ofs ) ; for ( i = 0 ; i < words ; ++ i ) { tmp = change_address ( smem , DImode , gen_rtx_AND ( DImode , plus_constant ( smema , 8 * i ) , im8 ) ) ; set_mem_alias_set ( tmp , 0 ) ; emit_move_insn ( data_regs [ i ] , tmp ) ; } tmp = change_address ( smem , DImode , gen_rtx_AND ( DImode , plus_constant ( smema , 8 * words - 1 ) , im8 ) ) ; set_mem_alias_set ( tmp , 0 ) ; emit_move_insn ( data_regs [ words ] , tmp ) ; sreg = copy_addr_to_reg ( smema ) ; areg = expand_binop ( DImode , and_optab , sreg , GEN_INT ( 7 ) , NULL , 1 , OPTAB_WIDEN ) ; if ( WORDS_BIG_ENDIAN ) emit_move_insn ( sreg , plus_constant ( sreg , 7 ) ) ; for ( i = 0 ; i < words ; ++ i ) { if ( WORDS_BIG_ENDIAN ) { emit_insn ( gen_extqh_be ( data_regs [ i ] , data_regs [ i ] , sreg ) ) ; emit_insn ( gen_extxl_be ( ext_tmps [ i ] , data_regs [ i + 1 ] , i64 , sreg ) ) ; } else { emit_insn ( gen_extxl_le ( data_regs [ i ] , data_regs [ i ] , i64 , sreg ) ) ; emit_insn ( gen_extqh_le ( ext_tmps [ i ] , data_regs [ i + 1 ] , sreg ) ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , ext_tmps [ i ] , gen_rtx_IF_THEN_ELSE ( DImode , gen_rtx_EQ ( DImode , areg , const0_rtx ) , const0_rtx , ext_tmps [ i ] ) ) ) ; } for ( i = 0 ; i < words ; ++ i ) { out_regs [ i ] = expand_binop ( DImode , ior_optab , data_regs [ i ] , ext_tmps [ i ] , data_regs [ i ] , 1 , OPTAB_WIDEN ) ; } } </s>

Load an integral number of consecutive unaligned quadwords .


<s> void HexagonCommonGEP :: removeDeadCode ( ) { ValueVect BO ; BO . push_back ( & Fn -> front ( ) ) ; for ( unsigned i = 0 ; i < BO . size ( ) ; ++ i ) { BasicBlock * B = cast < BasicBlock > ( BO [ i ] ) ; for ( auto DTN : children < DomTreeNode * > ( DT -> getNode ( B ) ) ) BO . push_back ( DTN -> getBlock ( ) ) ; } for ( unsigned i = BO . size ( ) ; i > 0 ; -- i ) { BasicBlock * B = cast < BasicBlock > ( BO [ i - 1 ] ) ; BasicBlock :: InstListType & IL = B -> getInstList ( ) ; typedef BasicBlock :: InstListType :: reverse_iterator reverse_iterator ; ValueVect Ins ; for ( reverse_iterator I = IL . rbegin ( ) , E = IL . rend ( ) ; I != E ; ++ I ) Ins . push_back ( & * I ) ; for ( ValueVect :: iterator I = Ins . begin ( ) , E = Ins . end ( ) ; I != E ; ++ I ) { Instruction * In = cast < Instruction > ( * I ) ; if ( isInstructionTriviallyDead ( In ) ) In -> eraseFromParent ( ) ; } } } </s>

Remove all dead instructions between the I and E .


<s> int barrier_align ( rtx_insn * barrier_or_label ) { if ( ! barrier_or_label ) return 0 ; if ( LABEL_P ( barrier_or_label ) && NEXT_INSN ( barrier_or_label ) && JUMP_TABLE_DATA_P ( NEXT_INSN ( barrier_or_label ) ) ) return 2 ; if ( BARRIER_P ( barrier_or_label ) && PREV_INSN ( barrier_or_label ) && JUMP_TABLE_DATA_P ( PREV_INSN ( barrier_or_label ) ) ) { rtx pat = PATTERN ( PREV_INSN ( barrier_or_label ) ) ; return ( ( optimize_size || ( ( unsigned ) XVECLEN ( pat , 1 ) * GET_MODE_SIZE ( GET_MODE ( pat ) ) <= ( unsigned ) 1 << ( CACHE_LOG - 2 ) ) ) ? 1 : align_jumps_log ) ; } rtx_insn * next = next_active_insn ( barrier_or_label ) ; if ( ! next ) return 0 ; rtx pat = PATTERN ( next ) ; if ( GET_CODE ( pat ) == UNSPEC_VOLATILE && XINT ( pat , 1 ) == UNSPECV_ALIGN ) return 0 ; if ( optimize_size ) return 0 ; if ( ! TARGET_SH2 || ! optimize ) return align_jumps_log ; if ( mdep_reorg_phase > SH_FIXUP_PCLOAD ) { int slot , credit ; bool jump_to_next = false ; rtx_insn * prev = prev_real_insn ( prev_active_insn ( barrier_or_label ) ) ; for ( slot = 2 , credit = ( 1 << ( CACHE_LOG - 2 ) ) + 2 ; credit >= 0 && prev && NONJUMP_INSN_P ( prev ) ; prev = prev_real_insn ( prev ) ) { jump_to_next = false ; if ( GET_CODE ( PATTERN ( prev ) ) == USE || GET_CODE ( PATTERN ( prev ) ) == CLOBBER ) continue ; if ( rtx_sequence * prev_seq = dyn_cast < rtx_sequence * > ( PATTERN ( prev ) ) ) { prev = prev_seq -> insn ( 1 ) ; if ( INSN_UID ( prev ) == INSN_UID ( next ) ) { jump_to_next = true ; continue ; } } if ( slot && get_attr_in_delay_slot ( prev ) == IN_DELAY_SLOT_YES ) slot = 0 ; credit -= get_attr_length ( prev ) ; } if ( prev && jump_to_label_p ( prev ) ) { rtx_insn * x ; if ( jump_to_next || next_real_insn ( JUMP_LABEL ( prev ) ) == next || JUMP_LABEL ( prev ) == next_nonnote_insn ( next ) || ( x = ( NEXT_INSN ( NEXT_INSN ( PREV_INSN ( prev ) ) ) ) , ( INSN_P ( x ) && ( INSN_CODE ( x ) == CODE_FOR_block_branch_redirect || INSN_CODE ( x ) == CODE_FOR_indirect_jump_scratch || INSN_CODE ( x ) == CODE_FOR_stuff_delay_slot ) ) ) ) { rtx pat = PATTERN ( prev ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , 0 , 0 ) ; if ( credit - slot >= ( GET_CODE ( SET_SRC ( pat ) ) == PC ? 2 : 0 ) ) return 0 ; } } } return align_jumps_log ; } </s>

BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following a barrier . Return the base 2 logarithm of the desired alignment .


<s>
unsigned
SparcInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugInstr
(
)
)
continue
;
if
(
I
->
getOpcode
(
)
!=
SP
::
BA
&&
I
->
getOpcode
(
)
!=
SP
::
BCOND
&&
I
->
getOpcode
(
)
!=
SP
::
FBCOND
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .

Sparc
Sparc
"code size not handled"
0
SP::BA
SP::BCOND
SP::FBCOND


<s> unsigned LEGInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { assert ( 0 && "Unimplemented" ) ; return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> void rs6000_emit_le_vsx_store ( rtx dest , rtx source , machine_mode mode ) { gcc_assert ( can_create_pseudo_p ( ) ) ; if ( mode == TImode || mode == V1TImode ) { mode = V2DImode ; dest = adjust_address ( dest , V2DImode , 0 ) ; source = gen_lowpart ( V2DImode , source ) ; } rtx tmp = gen_reg_rtx_and_attrs ( source ) ; rs6000_emit_le_vsx_permute ( tmp , source , mode ) ; rs6000_emit_le_vsx_permute ( dest , tmp , mode ) ; } </s>

Emit a little-endian store to vector memory location DEST from VSX register SOURCE in mode MODE . The store is done with two permuting insn 's that represent an xxpermdi and an stxvd2x .


<s> Candidate & back ( ) { return rbegin ( ) -> second . back ( ) ; } </s>

back - Get the last character in the string .


<s> bool HexagonFrameLowering :: enableCalleeSaveSkip ( const MachineFunction & MF ) const { const auto & F = MF . getFunction ( ) ; assert ( F . hasFnAttribute ( Attribute :: NoReturn ) && F . getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) && ! F . getFunction ( ) . hasFnAttribute ( Attribute :: UWTable ) ) ; ( void ) F ; return MF . getSubtarget < HexagonSubtarget > ( ) . noreturnStackElim ( ) ; } </s>

Returns true if the target can safely skip saving callee-saved registers for noreturn nounwind functions .


<s> bool isOffsetOfLocal ( ) const override { return isImm ( ) && Imm . LocalRef ; } </s>

isOffsetOfLocal - Do we need to emit code to get the offset of the local variable , rather than its value ? Only valid when parsing MS-style inline assembly .


<s> bool X86PassConfig :: addILPOpts ( ) { if ( EnableCondBrFoldingPass ) addPass ( createX86CondBrFolding ( ) ) ; addPass ( & EarlyIfConverterID ) ; if ( EnableMachineCombinerPass ) addPass ( & MachineCombinerID ) ; addPass ( createX86CmovConverterPass ( ) ) ; return true ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .


<s>
void
SHUXIInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
SHUXI
::
GPRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
SHUXI
::
CPYrr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
else
{
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
}
</s>

SHUXI
SHUXI
SHUXI::GPRegsRegClass
SHUXI::CPYrr
"Impossible reg-to-reg copy"


<s> static rtx get_replacement ( struct reg_replace * r ) { if ( r -> n_allocated == r -> n_in_use ) r -> replacement [ r -> n_allocated ++ ] = gen_reg_rtx ( r -> mode ) ; return r -> replacement [ r -> n_in_use ++ ] ; } </s>

Allocate or reuse a replacement in R and return the rtx .


<s> bool TPCFrameLowering :: hasFP ( const MachineFunction & MF ) const { return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> const CallLowering * RISCVSubtarget :: getCallLowering ( ) const { return CallLoweringInfo . get ( ) ; } </s>


<s>
void
loongarch_output_external
(
FILE
*
file
,
tree
decl
,
const
char
*
name
)
{
default_elf_asm_output_external
(
file
,
decl
,
name
)
;
if
(
TREE_SYMBOL_REFERENCED
(
DECL_ASSEMBLER_NAME
(
decl
)
)
)
{
if
(
loongarch_in_small_data_p
(
decl
)
)
{
fputs
(
"\t.extern\t"
,
file
)
;
assemble_name
(
file
,
name
)
;
fprintf
(
file
,
", "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
int_size_in_bytes
(
TREE_TYPE
(
decl
)
)
)
;
}
}
}
</s>


<s> static bool ft32_function_value_regno_p ( const unsigned int regno ) { return ( regno == FT32_R0 ) ; } </s>

Handle TARGET_FUNCTION_VALUE_REGNO_P . We always return values in register $ r0 for ft32 .


<s> static rtx mips_expand_builtin_direct ( enum insn_code icode , rtx target , tree exp , bool has_target_p ) { struct expand_operand ops [ MAX_RECOG_OPERANDS ] ; int opno , argno ; opno = 0 ; if ( has_target_p ) create_output_operand ( & ops [ opno ++ ] , target , TYPE_MODE ( TREE_TYPE ( exp ) ) ) ; gcc_assert ( opno + call_expr_nargs ( exp ) == insn_data [ icode ] . n_generator_args ) ; for ( argno = 0 ; argno < call_expr_nargs ( exp ) ; argno ++ ) mips_prepare_builtin_arg ( & ops [ opno ++ ] , exp , argno ) ; return mips_expand_builtin_insn ( icode , opno , ops , has_target_p ) ; } </s>

Expand a MIPS_BUILTIN_DIRECT function . ICODE is the code of the .md pattern and ARGLIST is the list of function arguments . TARGET , if nonnull , suggests a good place to put the result . HAS_TARGET indicates the function must return something .


<s> bool ARMBaseInstrInfo :: shouldSink ( const MachineInstr & MI ) const { if ( isPredicated ( MI ) ) return true ; MachineBasicBlock :: const_iterator Next = & MI ; ++ Next ; unsigned SrcReg , SrcReg2 ; int CmpMask , CmpValue ; bool IsThumb1 ; if ( Next != MI . getParent ( ) -> end ( ) && analyzeCompare ( * Next , SrcReg , SrcReg2 , CmpMask , CmpValue ) && isRedundantFlagInstr ( & * Next , SrcReg , SrcReg2 , CmpValue , & MI , IsThumb1 ) ) return false ; return true ; } </s>

Return true if the instruction should be sunk by MachineSink .


<s> bool ARMTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , CCAssignFnForReturn ( CallConv , isVarArg ) ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> static bool sh_function_value_regno_p ( const unsigned int regno ) { return regno == FIRST_RET_REG || ( TARGET_SH2E && regno == FIRST_FP_RET_REG ) ; } </s>

Return true if N is a possible register number of function value .


<s>
StringRef
getPassName
(
)
const
override
{
return
"AVR Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> unsigned Cpu0MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; unsigned RegNo = Ctx . getRegisterInfo ( ) -> getEncodingValue ( Reg ) ; return RegNo ; } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isFPImm ( ) ) { return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( 32 ) . getLimitedValue ( ) ) ; } assert ( MO . isExpr ( ) ) ; return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> void aarch64_init_fcmla_laneq_builtins ( void ) { unsigned int i = 0 ; for ( i = 0 ; i < ARRAY_SIZE ( aarch64_fcmla_lane_builtin_data ) ; ++ i ) { aarch64_fcmla_laneq_builtin_datum * d = & aarch64_fcmla_lane_builtin_data [ i ] ; tree argtype = aarch64_simd_builtin_type ( d -> mode , qualifier_none ) ; machine_mode quadmode = GET_MODE_2XWIDER_MODE ( d -> mode ) . require ( ) ; tree quadtype = aarch64_simd_builtin_type ( quadmode , qualifier_none ) ; tree lanetype = aarch64_simd_builtin_type ( SImode , qualifier_lane_pair_index ) ; tree ftype = build_function_type_list ( argtype , argtype , argtype , quadtype , lanetype , NULL_TREE ) ; tree attrs = aarch64_get_attributes ( FLAG_FP , d -> mode ) ; tree fndecl = aarch64_general_add_builtin ( d -> name , ftype , d -> fcode , attrs ) ; aarch64_builtin_decls [ d -> fcode ] = fndecl ; } } </s>

Due to the architecture not providing lane variant of the lane instructions for fcmla we ca n't use the standard simd builtin expansion code , but we still want the majority of the validation that would normally be done .


<s>
unsigned
getReg
(
)
const
{
assert
(
(
Kind
==
Register
||
Kind
==
CCOut
)
&&
"Invalid access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s> bool HexagonInstrInfo :: isIndirectCall ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { case Hexagon :: J2_callr : case Hexagon :: J2_callrf : case Hexagon :: J2_callrt : case Hexagon :: PS_call_nr : return true ; } return false ; } </s>

Return true if the callsite is an indirect call .


<s> static SDValue LowerCallResult ( SDValue Chain , SDValue InFlag , const SmallVectorImpl < CCValAssign > & RVLocs , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { SmallVector < std :: pair < int , unsigned > , 4 > ResultMemLocs ; for ( unsigned i = 0 , e = RVLocs . size ( ) ; i != e ; ++ i ) { const CCValAssign & VA = RVLocs [ i ] ; if ( VA . isRegLoc ( ) ) { Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; ResultMemLocs . push_back ( std :: make_pair ( VA . getLocMemOffset ( ) , InVals . size ( ) ) ) ; InVals . push_back ( SDValue ( ) ) ; } } SmallVector < SDValue , 4 > MemOpChains ; for ( unsigned i = 0 , e = ResultMemLocs . size ( ) ; i != e ; ++ i ) { int offset = ResultMemLocs [ i ] . first ; unsigned index = ResultMemLocs [ i ] . second ; SDVTList VTs = DAG . getVTList ( MVT :: i32 , MVT :: Other ) ; SDValue Ops [ ] = { Chain , DAG . getConstant ( offset / 4 , MVT :: i32 ) } ; SDValue load = DAG . getNode ( XCoreISD :: LDWSP , dl , VTs , Ops ) ; InVals [ index ] = load ; MemOpChains . push_back ( load . getValue ( 1 ) ) ; } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( ISD :: TokenFactor , dl , MVT :: Other , MemOpChains ) ; return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> const MCPhysReg * SystemZRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_SystemZ_SaveList ; } </s>


Initialize machine-specific if-conversion data . On the FR-V , we do n't have any extra fields per se , but it is useful hook to initialize the static storage .


<s>
void
MCS51DAGToDAGISel
::
Select
(
SDNode
*
N
)
{
if
(
N
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
errs
(
)
<<
"== "
;
N
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
N
->
setNodeId
(
1
)
;
return
;
}
if
(
trySelect
(
N
)
)
return
;
SelectCode
(
N
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> int cr16_initial_elimination_offset ( int from , int to ) { cr16_compute_save_regs ( ) ; cr16_compute_frame ( ) ; if ( ( ( from ) == FRAME_POINTER_REGNUM ) && ( ( to ) == STACK_POINTER_REGNUM ) ) return ( ACCUMULATE_OUTGOING_ARGS ? ( HOST_WIDE_INT ) crtl -> outgoing_args_size : 0 ) ; else if ( ( ( from ) == ARG_POINTER_REGNUM ) && ( ( to ) == FRAME_POINTER_REGNUM ) ) return ( current_frame_info . reg_size + current_frame_info . var_size ) ; else if ( ( ( from ) == ARG_POINTER_REGNUM ) && ( ( to ) == STACK_POINTER_REGNUM ) ) return ( current_frame_info . reg_size + current_frame_info . var_size + ( ACCUMULATE_OUTGOING_ARGS ? ( HOST_WIDE_INT ) crtl -> outgoing_args_size : 0 ) ) ; else gcc_unreachable ( ) ; } </s>

Implements the macro INITIAL_ELIMINATION_OFFSET , return the OFFSET .


<s> bool X86TargetLowering :: hasAndNotCompare ( SDValue Y ) const { EVT VT = Y . getValueType ( ) ; if ( VT . isVector ( ) ) return false ; if ( ! Subtarget . hasBMI ( ) ) return false ; if ( VT != MVT :: i32 && VT != MVT :: i64 ) return false ; return true ; } </s>

Return true if the target should transform : ( X & Y ) == Y � ? ( ~X & Y ) == 0 ( X & Y ) ! = Y � ? ( ~X & Y ) ! = 0 .


<s> bool RISCVPassConfig :: addLegalizeMachineIR ( ) { addPass ( new Legalizer ( ) ) ; return false ; } </s>

This method should install a legalize pass , which converts the instruction sequence into one that can be selected by the target .


<s> rtx gen_mhi ( void ) { return gen_rtx_REG ( SImode , TARGET_BIG_ENDIAN ? 58 : 59 ) ; } </s>

Return a REG rtx for mhi . N.B . the gcc-internal representation may differ from the hardware register number in order to allow the generic code to correctly split the concatenation of mhi and mlo .


<s> unsigned XNCMRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { llvm_unreachable ( 0 ) ; } </s>


<s>
bool
CAHPAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Operands
.
push_back
(
CAHPOperand
::
createToken
(
Name
,
NameLoc
)
)
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
return
false
;
if
(
parseOperand
(
Operands
)
)
return
true
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
getLexer
(
)
.
Lex
(
)
;
if
(
parseOperand
(
Operands
)
)
return
true
;
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
getParser
(
)
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
getParser
(
)
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

CAHP
CAHP
CAHPOperand::createToken
"unexpected token"


<s> bool PPCTTIImpl :: isLSRCostLess ( TargetTransformInfo :: LSRCost & C1 , TargetTransformInfo :: LSRCost & C2 ) { if ( ! LsrNoInsnsCost ) return std :: tie ( C1 . Insns , C1 . NumRegs , C1 . AddRecCost , C1 . NumIVMuls , C1 . NumBaseAdds , C1 . ScaleCost , C1 . ImmCost , C1 . SetupCost ) < std :: tie ( C2 . Insns , C2 . NumRegs , C2 . AddRecCost , C2 . NumIVMuls , C2 . NumBaseAdds , C2 . ScaleCost , C2 . ImmCost , C2 . SetupCost ) ; else return TargetTransformInfoImplBase :: isLSRCostLess ( C1 , C2 ) ; } </s>

Return true if LSR cost of C1 is lower than C2 .


<s> bool ARMAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'a' : case 'c' : printOperand ( MI , OpNo , "no_hash" ) ; return false ; case 'P' : printOperand ( MI , OpNo ) ; return false ; case 'Q' : if ( TM . getTargetData ( ) -> isLittleEndian ( ) ) break ; case 'R' : if ( TM . getTargetData ( ) -> isBigEndian ( ) ) break ; case 'H' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + 1 == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + 1 ) . isReg ( ) ) return true ; ++ OpNo ; } } printOperand ( MI , OpNo ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


"Hexagon generate \"insert\" instructions"


"AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "


<s> int sparc_absnegfloat_split_legitimate ( rtx x , rtx y ) { if ( GET_CODE ( x ) != REG ) return 0 ; if ( GET_CODE ( y ) != REG ) return 0 ; if ( REGNO ( x ) == REGNO ( y ) ) return 0 ; return 1 ; } </s>

Return 1 if x and y are some kind of REG and they refer to different hard registers . This test is guaranteed to be run after reload .


"Check for a non-legal type in this operation\n"

LowerOperation - Provide custom lowering hooks for some operations .


<s> unsigned AMDGPUIntrinsicInfo :: lookupName ( const char * Name , unsigned Len ) const { if ( ! StringRef ( Name , Len ) . startswith ( "llvm." ) ) return 0 ; AMDGPUIntrinsic :: ID IntrinsicID = ( AMDGPUIntrinsic :: ID ) Intrinsic :: not_intrinsic ; IntrinsicID = getIntrinsicForGCCBuiltin ( "AMDGPU" , Name ) ; if ( IntrinsicID != ( AMDGPUIntrinsic :: ID ) Intrinsic :: not_intrinsic ) { return IntrinsicID ; } return 0 ; } </s>


<s> static void add_attribute ( const char * mode , tree * attributes ) { size_t len = strlen ( mode ) ; tree value = build_string ( len , mode ) ; TREE_TYPE ( value ) = build_array_type ( char_type_node , build_index_type ( size_int ( len ) ) ) ; * attributes = tree_cons ( get_identifier ( "target" ) , build_tree_list ( NULL_TREE , value ) , * attributes ) ; } </s>


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


"-mno-mpy supported only for ARC700 or ARCv2"

"-mno-dpfp-lrsr supported only with -mdpfp"

"FPX fast and compact options cannot be specified together"

"-mspfp_fast not available on ARC600 or ARC601"

"PIC is not supported for %s. Generating non-PIC code only.."

Called by OVERRIDE_OPTIONS to initialize various things .


<s> unsigned char AArch64Subtarget :: ClassifyGlobalReference ( const GlobalValue * GV , const TargetMachine & TM ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) ) return AArch64II :: MO_GOT ; if ( ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) { if ( GV -> hasDLLImportStorageClass ( ) ) return AArch64II :: MO_GOT | AArch64II :: MO_DLLIMPORT ; if ( getTargetTriple ( ) . isOSWindows ( ) ) return AArch64II :: MO_GOT | AArch64II :: MO_COFFSTUB ; return AArch64II :: MO_GOT ; } if ( ( useSmallAddressing ( ) || TM . getCodeModel ( ) == CodeModel :: Tiny ) && GV -> hasExternalWeakLinkage ( ) ) return AArch64II :: MO_GOT ; return AArch64II :: MO_NO_FLAG ; } </s>

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be referenced for the current subtarget .


<s>
static
const
char
*
shift_op
(
rtx
op
,
HOST_WIDE_INT
*
amountp
)
{
const
char
*
mnem
;
enum
rtx_code
code
=
GET_CODE
(
op
)
;
switch
(
code
)
{
case
ROTATE
:
if
(
!
CONST_INT_P
(
XEXP
(
op
,
1
)
)
)
{
output_operand_lossage
(
"invalid shift operand"
)
;
return
;
}
code
=
ROTATERT
;
*
amountp
=
32
INTVAL
(
XEXP
(
op
,
1
)
)
;
mnem
=
"ror"
;
break
;
case
ASHIFT
:
case
ASHIFTRT
:
case
LSHIFTRT
:
case
ROTATERT
:
mnem
=
arm_shift_nmem
(
code
)
;
if
(
CONST_INT_P
(
XEXP
(
op
,
1
)
)
)
{
*
amountp
=
INTVAL
(
XEXP
(
op
,
1
)
)
;
}
else
if
(
REG_P
(
XEXP
(
op
,
1
)
)
)
{
*
amountp
=
1
;
return
mnem
;
}
else
{
output_operand_lossage
(
"invalid shift operand"
)
;
return
;
}
break
;
case
MULT
:
if
(
!
CONST_INT_P
(
XEXP
(
op
,
1
)
)
)
{
output_operand_lossage
(
"invalid shift operand"
)
;
return
;
}
*
amountp
=
INTVAL
(
XEXP
(
op
,
1
)
)
&
0xFFFFFFFF
;
if
(
*
amountp
&
(
*
amountp
1
)
)
{
output_operand_lossage
(
"invalid shift operand"
)
;
return
;
}
*
amountp
=
int_log2
(
*
amountp
)
;
return
ARM_LSL_NAME
;
default
:
output_operand_lossage
(
"invalid shift operand"
)
;
return
;
}
if
(
code
==
ROTATERT
)
*
amountp
&=
31
;
else
if
(
*
amountp
!=
(
*
amountp
&
31
)
)
{
if
(
code
==
ASHIFT
)
mnem
=
"lsr"
;
*
amountp
=
32
;
}
if
(
*
amountp
==
0
)
return
;
return
mnem
;
}
</s>

Ensure valid constant shifts and return the appropriate shift mnemonic for the operation code . The returned result should not be overwritten . OP is the rtx code of the shift . On exit , * AMOUNTP will be -1 if the shift is by a register , or a constant shift .


<s> virtual const SystemZInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> static void mn10300_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; cum -> nbytes += ( mode != BLKmode ? ( GET_MODE_SIZE ( mode ) + 3 ) & ~ 3 : ( int_size_in_bytes ( type ) + 3 ) & ~ 3 ) ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


"MVP WebAssembly can only return up to one value"

"WebAssembly doesn't support non-C calling conventions"

"WebAssembly hasn't implemented inalloca results"

"WebAssembly hasn't implemented cons regs results"

"WebAssembly hasn't implemented cons regs last results"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> const RISCVSubtarget * RISCVTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; std :: string Key = CPU + FS ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < RISCVSubtarget > ( TargetTriple , CPU , FS , Options . MCOptions . getABIName ( ) , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

RISCV RISCV RISCV "target-cpu" "target-features" RISCV


<s> void AMDGPUPassConfig :: addCodeGenPrepare ( ) { TargetPassConfig :: addCodeGenPrepare ( ) ; if ( EnableLoadStoreVectorizer ) addPass ( createLoadStoreVectorizerPass ( ) ) ; } </s>

Add pass to prepare the LLVM IR for code generation .


<s> static rtx nios2_split_plus_large_constant ( rtx op0 , rtx op1 ) { rtx temp = gen_reg_rtx ( Pmode ) ; op0 = force_reg ( Pmode , op0 ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_HIGH ( Pmode , copy_rtx ( op1 ) ) ) ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_PLUS ( Pmode , op0 , temp ) ) ) ; return gen_rtx_LO_SUM ( Pmode , temp , copy_rtx ( op1 ) ) ; } </s>

Split an RTX of the form ( plus op0 op1 ) where op1 is a large constant into ( set temp ( high op1 ) ) ( set temp ( plus op0 temp ) ) ( lo_sum temp op1 ) returning the lo_sum expression as the value .


<s> int s390_single_part ( rtx op , enum machine_mode mode , enum machine_mode part_mode , int def ) { unsigned HOST_WIDE_INT value = 0 ; int n_parts = GET_MODE_SIZE ( mode ) / GET_MODE_SIZE ( part_mode ) ; unsigned HOST_WIDE_INT part_mask = ( ( unsigned HOST_WIDE_INT ) 1 << GET_MODE_BITSIZE ( part_mode ) ) - 1 ; int i , part = - 1 ; if ( GET_CODE ( op ) != CONST_INT ) return - 1 ; for ( i = 0 ; i < n_parts ; i ++ ) { if ( i == 0 ) value = ( unsigned HOST_WIDE_INT ) INTVAL ( op ) ; else value >>= GET_MODE_BITSIZE ( part_mode ) ; if ( ( value & part_mask ) != ( def & part_mask ) ) { if ( part != - 1 ) return - 1 ; else part = i ; } } return part == - 1 ? - 1 : n_parts - 1 - part ; } </s>

If OP is an integer constant of mode MODE with exactly one part of mode PART_MODE unequal to DEF , return the number of that part . Otherwise , return -1 .


<s> const uint16_t * SNESRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_Normal_SaveList ; } </s>


<s> unsigned AVRInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : { const MCInstrDesc & Desc = get ( Opcode ) ; return Desc . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return 0 ; case TargetOpcode :: INLINEASM : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const AVRTargetMachine & TM = static_cast < const AVRTargetMachine & > ( MF . getTarget ( ) ) ; const AVRSubtarget & STI = MF . getSubtarget < AVRSubtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; return TII . getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> bool AArch64CompressJumpTables :: runOnMachineFunction ( MachineFunction & MFIn ) { bool Changed = false ; MF = & MFIn ; const auto & ST = MF -> getSubtarget < AArch64Subtarget > ( ) ; TII = ST . getInstrInfo ( ) ; if ( ST . force32BitJumpTables ( ) && ! MF -> getFunction ( ) . hasMinSize ( ) ) return false ; scanFunction ( ) ; for ( MachineBasicBlock & MBB : * MF ) { int Offset = BlockInfo [ MBB . getNumber ( ) ] ; for ( MachineInstr & MI : MBB ) { Changed |= compressJumpTable ( MI , Offset ) ; Offset += TII -> getInstSizeInBytes ( MI ) ; } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> static rtx loongarch_legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , machine_mode mode ) { rtx base , addr ; HOST_WIDE_INT offset ; if ( loongarch_tls_symbol_p ( x ) ) return loongarch_legitimize_tls_address ( x ) ; if ( loongarch_split_symbol ( NULL , x , mode , & addr ) ) return loongarch_force_address ( addr , mode ) ; loongarch_split_plus ( x , & base , & offset ) ; if ( offset != 0 ) { if ( ! loongarch_valid_base_register_p ( base , mode , false ) ) base = copy_to_mode_reg ( Pmode , base ) ; addr = loongarch_add_offset ( NULL , base , offset ) ; return loongarch_force_address ( addr , mode ) ; } return x ; } </s>

This function is used to implement LEGITIMIZE_ADDRESS . If X can be legitimized in a way that the generic machinery might not expect , return a new address , otherwise return NULL . MODE is the mode of the memory being accessed .


<s>
const
char
*
avr_out_round
(
rtx_insn
*
insn
ATTRIBUTE_UNUSED
,
rtx
*
xop
,
int
*
plen
)
{
machine_mode
mode
=
GET_MODE
(
xop
[
0
]
)
;
machine_mode
imode
=
int_mode_for_mode
(
mode
)
;
int
fbit
=
(
int
)
GET_MODE_FBIT
(
mode
)
;
double_int
i_add
=
double_int_zero
.
set_bit
(
fbit
1
INTVAL
(
xop
[
2
]
)
)
;
wide_int
wi_add
=
wi
::
set_bit_in_zero
(
fbit
1
INTVAL
(
xop
[
2
]
)
,
GET_MODE_PRECISION
(
imode
)
)
;
int
len_add
=
0
,
*
plen_add
=
plen
&
len_add
:
;
int
len_and
=
0
,
*
plen_and
=
plen
&
len_and
:
;
rtx
xadd
=
const_fixed_from_double_int
(
i_add
,
mode
)
;
rtx
xpattern
,
xsrc
,
op
[
4
]
;
xsrc
=
SIGNED_FIXED_POINT_MODE_P
(
mode
)
gen_rtx_SS_PLUS
(
mode
,
xop
[
1
]
,
xadd
)
:
gen_rtx_US_PLUS
(
mode
,
xop
[
1
]
,
xadd
)
;
xpattern
=
gen_rtx_SET
(
VOIDmode
,
xop
[
0
]
,
xsrc
)
;
op
[
0
]
=
xop
[
0
]
;
op
[
1
]
=
xop
[
1
]
;
op
[
2
]
=
xadd
;
avr_out_plus
(
xpattern
,
op
,
plen_add
,
,
false
)
;
avr_asm_len
(
"rjmp 1f"
CR_TAB
"0:"
,
,
plen_add
,
1
)
;
rtx
xreg
=
simplify_gen_subreg
(
imode
,
xop
[
0
]
,
mode
,
0
)
;
rtx
xmask
=
immed_wide_int_const
(
wi_add
wi_add
,
imode
)
;
xpattern
=
gen_rtx_SET
(
VOIDmode
,
xreg
,
gen_rtx_AND
(
imode
,
xreg
,
xmask
)
)
;
op
[
0
]
=
xreg
;
op
[
1
]
=
xreg
;
op
[
2
]
=
xmask
;
op
[
3
]
=
gen_rtx_SCRATCH
(
QImode
)
;
avr_out_bitop
(
xpattern
,
op
,
plen_and
)
;
avr_asm_len
(
"1:"
,
,
plen
,
0
)
;
if
(
plen
)
*
plen
=
len_add
+
len_and
;
return
""
;
}
</s>

Output fixed-point rounding . XOP [ 0 ] = XOP [ 1 ] is the operand to round . XOP [ 2 ] is the rounding point , a CONST_INT . The function prints the instruction sequence if PLEN = NULL and computes the length in words of the sequence if PLEN ! = NULL . Most of this function deals with preparing operands for calls to ` avr_out_plus ' and ` avr_out_bitop ' .


<s> void AMDGPUAsmPrinter :: emitFunctionEntryLabel ( ) { if ( TM . getTargetTriple ( ) . getOS ( ) == Triple :: AMDHSA && isHsaAbiVersion3 ( getGlobalSTI ( ) ) ) { AsmPrinter :: emitFunctionEntryLabel ( ) ; return ; } const SIMachineFunctionInfo * MFI = MF -> getInfo < SIMachineFunctionInfo > ( ) ; const GCNSubtarget & STM = MF -> getSubtarget < GCNSubtarget > ( ) ; if ( MFI -> isEntryFunction ( ) && STM . isAmdHsaOrMesa ( MF -> getFunction ( ) ) ) { SmallString < 128 > SymbolName ; getNameWithPrefix ( SymbolName , & MF -> getFunction ( ) ) , getTargetStreamer ( ) -> EmitAMDGPUSymbolType ( SymbolName , ELF :: STT_AMDGPU_HSA_KERNEL ) ; } if ( DumpCodeInstEmitter ) { DisasmLines . push_back ( MF -> getName ( ) . str ( ) + ":" ) ; DisasmLineMaxLen = std :: max ( DisasmLineMaxLen , DisasmLines . back ( ) . size ( ) ) ; HexLines . push_back ( "" ) ; } AsmPrinter :: emitFunctionEntryLabel ( ) ; } </s>

EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function .

AMDGPU AMDGPU SI SI 128 AMDGPU AMDGPU ":" ""


<s> void X86InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , Register DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { if ( RC -> getID ( ) == X86 :: TILERegClassID ) { unsigned Opc = X86 :: TILELOADD ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; Register VirtReg = RegInfo . createVirtualRegister ( & X86 :: GR64_NOSPRegClass ) ; MachineInstr * NewMI = BuildMI ( MBB , MI , DebugLoc ( ) , get ( X86 :: MOV64ri ) , VirtReg ) . addImm ( 64 ) ; NewMI = addFrameReference ( BuildMI ( MBB , MI , DebugLoc ( ) , get ( Opc ) , DestReg ) , FrameIdx ) ; MachineOperand & MO = NewMI -> getOperand ( 3 ) ; MO . setReg ( VirtReg ) ; MO . setIsKill ( true ) ; } else if ( RC -> getID ( ) == X86 :: TILECFGRegClassID ) { unsigned Opc = X86 :: PLDTILECFG ; addFrameReference ( BuildMI ( MBB , MI , DebugLoc ( ) , get ( Opc ) , DestReg ) , FrameIdx ) ; } else { const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Alignment = std :: max < uint32_t > ( TRI -> getSpillSize ( * RC ) , 16 ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlign ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , Subtarget ) ; addFrameReference ( BuildMI ( MBB , MI , DebugLoc ( ) , get ( Opc ) , DestReg ) , FrameIdx ) ; } } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> EVT MipsTargetLowering :: getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const { if ( Subtarget . hasMips64 ( ) ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Mips Expand Pseudo"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
void
AMDGPUCallLowering
::
splitToValueTypes
(
MachineIRBuilder
&
B
,
const
ArgInfo
&
OrigArg
,
unsigned
OrigArgIdx
,
SmallVectorImpl
<
ArgInfo
>
&
SplitArgs
,
const
DataLayout
&
DL
,
CallingConv
::
ID
CallConv
,
SplitArgTy
PerformArgSplit
)
const
{
const
SITargetLowering
&
TLI
=
*
getTLI
<
SITargetLowering
>
(
)
;
LLVMContext
&
Ctx
=
OrigArg
.
Ty
->
getContext
(
)
;
if
(
OrigArg
.
Ty
->
isVoidTy
(
)
)
return
;
SmallVector
<
EVT
,
4
>
SplitVTs
;
ComputeValueVTs
(
TLI
,
DL
,
OrigArg
.
Ty
,
SplitVTs
)
;
assert
(
OrigArg
.
Regs
.
size
(
)
==
SplitVTs
.
size
(
)
)
;
int
SplitIdx
=
0
;
for
(
EVT
VT
:
SplitVTs
)
{
Register
Reg
=
OrigArg
.
Regs
[
SplitIdx
]
;
Type
*
Ty
=
VT
.
getTypeForEVT
(
Ctx
)
;
LLT
LLTy
=
getLLTForType
(
*
Ty
,
DL
)
;
if
(
OrigArgIdx
==
AttributeList
::
ReturnIndex
&&
VT
.
isScalarInteger
(
)
)
{
unsigned
ExtendOp
=
TargetOpcode
::
G_ANYEXT
;
if
(
OrigArg
.
Flags
[
0
]
.
isSExt
(
)
)
{
assert
(
OrigArg
.
Regs
.
size
(
)
==
1
&&
"expect only simple return values"
)
;
ExtendOp
=
TargetOpcode
::
G_SEXT
;
}
else
if
(
OrigArg
.
Flags
[
0
]
.
isZExt
(
)
)
{
assert
(
OrigArg
.
Regs
.
size
(
)
==
1
&&
"expect only simple return values"
)
;
ExtendOp
=
TargetOpcode
::
G_ZEXT
;
}
EVT
ExtVT
=
TLI
.
getTypeForExtReturn
(
Ctx
,
VT
,
extOpcodeToISDExtOpcode
(
ExtendOp
)
)
;
if
(
ExtVT
!=
VT
)
{
VT
=
ExtVT
;
Ty
=
ExtVT
.
getTypeForEVT
(
Ctx
)
;
LLTy
=
getLLTForType
(
*
Ty
,
DL
)
;
Reg
=
B
.
buildInstr
(
ExtendOp
,
{
LLTy
}
,
{
Reg
}
)
.
getReg
(
0
)
;
}
}
unsigned
NumParts
=
TLI
.
getNumRegistersForCallingConv
(
Ctx
,
CallConv
,
VT
)
;
MVT
RegVT
=
TLI
.
getRegisterTypeForCallingConv
(
Ctx
,
CallConv
,
VT
)
;
if
(
NumParts
==
1
)
{
SplitArgs
.
emplace_back
(
Reg
,
Ty
,
OrigArg
.
Flags
,
OrigArg
.
IsFixed
)
;
++
SplitIdx
;
continue
;
}
SmallVector
<
Register
,
8
>
SplitRegs
;
Type
*
PartTy
=
EVT
(
RegVT
)
.
getTypeForEVT
(
Ctx
)
;
LLT
PartLLT
=
getLLTForType
(
*
PartTy
,
DL
)
;
MachineRegisterInfo
&
MRI
=
*
B
.
getMRI
(
)
;
for
(
unsigned
i
=
0
;
i
<
NumParts
;
++
i
)
{
Register
PartReg
=
MRI
.
createGenericVirtualRegister
(
PartLLT
)
;
SplitRegs
.
push_back
(
PartReg
)
;
SplitArgs
.
emplace_back
(
ArrayRef
<
Register
>
(
PartReg
)
,
PartTy
,
OrigArg
.
Flags
)
;
}
PerformArgSplit
(
SplitRegs
,
Reg
,
LLTy
,
PartLLT
,
SplitIdx
)
;
++
SplitIdx
;
}
}
</s>

Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> bool function_checker :: require_immediate_lane_index ( unsigned int rel_argno , unsigned int group_size ) { unsigned int argno = m_base_arg + rel_argno ; if ( ! argument_exists_p ( argno ) ) return true ; machine_mode mode = TYPE_MODE ( type_argument_type ( m_fntype , argno ) ) ; gcc_assert ( VECTOR_MODE_P ( mode ) ) ; unsigned int nlanes = 128 / ( group_size * GET_MODE_UNIT_BITSIZE ( mode ) ) ; return require_immediate_range ( rel_argno , 0 , nlanes - 1 ) ; } </s>

Check that argument REL_ARGNO is suitable for indexing argument REL_ARGNO - 1 , in groups of GROUP_SIZE elements . REL_ARGNO counts from the end of the predication arguments .


<s>
bool
X86AsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
SetupMachineFunction
(
MF
)
;
if
(
Subtarget
->
isTargetCOFF
(
)
)
{
const
Function
*
F
=
MF
.
getFunction
(
)
;
O
<<
"\t.def\t "
<<
*
CurrentFnSym
<<
";\t.scl\t"
<<
(
F
->
hasInternalLinkage
(
)
COFF
::
C_STAT
:
COFF
::
C_EXT
)
<<
";\t.type\t"
<<
(
COFF
::
DT_FCN
<<
COFF
::
N_BTSHFT
)
<<
";\t.endef\n"
;
}
EmitFunctionHeader
(
)
;
EmitFunctionBody
(
)
;
return
false
;
}
</s>


<s> const MCPhysReg * PPCTargetLowering :: getScratchRegisters ( CallingConv :: ID ) const { static const MCPhysReg ScratchRegs [ ] = { PPC :: X12 , PPC :: LR8 , PPC :: CTR8 , 0 } ; return ScratchRegs ; } </s>

Returns a 0 terminated array of registers that can be safely used as scratch registers .


<s> unsigned X86RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? FramePtr : StackPtr ; } </s>


<s> bool PPCAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'c' : break ; case 'L' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + 1 == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + 1 ) . isReg ( ) ) return true ; ++ OpNo ; break ; case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << "i" ; return false ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> virtual MVT getShiftAmountTy ( EVT LHSTy ) const { return MVT :: i32 ; } </s>

Returns the type for the shift amount of a shift opcode .


<s> void HexagonInstPrinter :: printRegName ( raw_ostream & O , unsigned RegNo ) const { O << getRegName ( RegNo ) ; } </s>


<s> static int s390_function_arg_size ( enum machine_mode mode , tree type ) { if ( type ) return int_size_in_bytes ( type ) ; if ( mode != BLKmode ) return GET_MODE_SIZE ( mode ) ; gcc_unreachable ( ) ; } </s>

Return the size in bytes of a function argument of type TYPE and/or mode MODE . At least one of TYPE or MODE must be specified .


"Frame offsets outside of the signed 32-bit range not supported"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


This function is used to print CPU tuning information as comment in assembler file . Pointers are not printed for now .


<s> std :: pair < const TargetRegisterClass * , uint8_t > X86TargetLowering :: findRepresentativeClass ( EVT VT ) const { const TargetRegisterClass * RRC = 0 ; uint8_t Cost = 1 ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( VT ) ; case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : case MVT :: i64 : RRC = ( Subtarget -> is64Bit ( ) ? X86 :: GR64RegisterClass : X86 :: GR32RegisterClass ) ; break ; case MVT :: v8i8 : case MVT :: v4i16 : case MVT :: v2i32 : case MVT :: v1i64 : RRC = X86 :: VR64RegisterClass ; break ; case MVT :: f32 : case MVT :: f64 : case MVT :: v16i8 : case MVT :: v8i16 : case MVT :: v4i32 : case MVT :: v2i64 : case MVT :: v4f32 : case MVT :: v2f64 : case MVT :: v32i8 : case MVT :: v8i32 : case MVT :: v4i64 : case MVT :: v8f32 : case MVT :: v4f64 : RRC = X86 :: VR128RegisterClass ; break ; } return std :: make_pair ( RRC , Cost ) ; } </s>

Return the largest legal super-reg register class of the register class for the specified type and its associated `` cost '' .


<s> static void seh_cfa_offset ( FILE * f , struct seh_frame_state * seh , rtx pat ) { rtx dest , src ; HOST_WIDE_INT reg_offset ; dest = SET_DEST ( pat ) ; src = SET_SRC ( pat ) ; gcc_assert ( MEM_P ( dest ) ) ; dest = XEXP ( dest , 0 ) ; if ( REG_P ( dest ) ) reg_offset = 0 ; else { gcc_assert ( GET_CODE ( dest ) == PLUS ) ; reg_offset = INTVAL ( XEXP ( dest , 1 ) ) ; dest = XEXP ( dest , 0 ) ; } gcc_assert ( dest == seh -> cfa_reg ) ; seh_emit_save ( f , seh , src , seh -> cfa_offset - reg_offset ) ; } </s>


<s> void LEGInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( LEG :: STR ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> const char * SparcTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case SPISD :: CMPICC : return "SPISD::CMPICC" ; case SPISD :: CMPFCC : return "SPISD::CMPFCC" ; case SPISD :: BRICC : return "SPISD::BRICC" ; case SPISD :: BRXCC : return "SPISD::BRXCC" ; case SPISD :: BRFCC : return "SPISD::BRFCC" ; case SPISD :: SELECT_ICC : return "SPISD::SELECT_ICC" ; case SPISD :: SELECT_XCC : return "SPISD::SELECT_XCC" ; case SPISD :: SELECT_FCC : return "SPISD::SELECT_FCC" ; case SPISD :: Hi : return "SPISD::Hi" ; case SPISD :: Lo : return "SPISD::Lo" ; case SPISD :: FTOI : return "SPISD::FTOI" ; case SPISD :: ITOF : return "SPISD::ITOF" ; case SPISD :: CALL : return "SPISD::CALL" ; case SPISD :: RET_FLAG : return "SPISD::RET_FLAG" ; case SPISD :: GLOBAL_BASE_REG : return "SPISD::GLOBAL_BASE_REG" ; case SPISD :: FLUSHW : return "SPISD::FLUSHW" ; } } </s>

getTargetNodeName - This method returns the name of a target specific

Sparc Sparc 0 SPISD::CMPICC "SPISD::CMPICC" SPISD::CMPFCC "SPISD::CMPFCC" SPISD::BRICC "SPISD::BRICC" SPISD::BRXCC "SPISD::BRXCC" SPISD::BRFCC "SPISD::BRFCC" SPISD::SELECT_ICC "SPISD::SELECT_ICC" SPISD::SELECT_XCC "SPISD::SELECT_XCC" SPISD::SELECT_FCC "SPISD::SELECT_FCC" SPISD::Hi "SPISD::Hi" SPISD::Lo "SPISD::Lo" SPISD::FTOI "SPISD::FTOI" SPISD::ITOF "SPISD::ITOF" SPISD::CALL "SPISD::CALL" SPISD::RET_FLAG "SPISD::RET_FLAG" SPISD::GLOBAL_BASE_REG "SPISD::GLOBAL_BASE_REG" SPISD::FLUSHW "SPISD::FLUSHW"


<s> bool AVRPassConfig :: addInstSelector ( ) { addPass ( createAVRISelDag ( getAVRTargetMachine ( ) , getOptLevel ( ) ) ) ; addPass ( createAVRFrameAnalyzerPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


"getIntImmCost can only estimate cost of materialising integers"

Calculate the cost of materializing a 64-bit value .


<s> bool HexagonSubtarget :: enableMachineScheduler ( ) const { if ( DisableHexagonMISched . getNumOccurrences ( ) ) return ! DisableHexagonMISched ; return true ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


<s>
SDValue
AlphaDAGToDAGISel
::
getGlobalBaseReg
(
)
{
unsigned
GP
=
0
;
for
(
MachineRegisterInfo
::
livein_iterator
ii
=
RegInfo
->
livein_begin
(
)
,
ee
=
RegInfo
->
livein_end
(
)
;
ii
!=
ee
;
++
ii
)
if
(
ii
->
first
==
Alpha
::
R29
)
{
GP
=
ii
->
second
;
break
;
}
assert
(
GP
&&
"GOT PTR not in liveins"
)
;
return
CurDAG
->
getCopyFromReg
(
CurDAG
->
getEntryNode
(
)
,
DebugLoc
::
getUnknownLoc
(
)
,
GP
,
MVT
::
i64
)
;
}
</s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> void WebAssemblyPassConfig :: addIRPasses ( ) { if ( TM -> Options . ThreadModel == ThreadModel :: Single ) { addPass ( createLowerAtomicPass ( ) ) ; addPass ( new StripThreadLocal ( ) ) ; } else { addPass ( createAtomicExpandPass ( ) ) ; } addPass ( createWebAssemblyAddMissingPrototypes ( ) ) ; addPass ( createWebAssemblyLowerGlobalDtors ( ) ) ; addPass ( createWebAssemblyFixFunctionBitcasts ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createWebAssemblyOptimizeReturned ( ) ) ; if ( ! EnableEmException && TM -> Options . ExceptionModel == ExceptionHandling :: None ) { addPass ( createLowerInvokePass ( ) ) ; addPass ( createUnreachableBlockEliminationPass ( ) ) ; } if ( EnableEmException || EnableEmSjLj ) addPass ( createWebAssemblyLowerEmscriptenEHSjLj ( EnableEmException , EnableEmSjLj ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly


<s>
StringRef
getPassName
(
)
const
override
{
return
"TVM Prepare For LiveIntervals"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
void
AMDGPUAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
)
const
{
switch
(
(
unsigned
)
Fixup
.
getKind
(
)
)
{
case
AMDGPU
::
fixup_si_sopp_br
:
{
int64_t
BrImm
=
(
(
int64_t
)
Value
4
)
/
4
;
if
(
!
isInt
<
16
>
(
BrImm
)
)
report_fatal_error
(
"branch size exceeds simm16"
)
;
uint16_t
*
Dst
=
(
uint16_t
*
)
(
Data
+
Fixup
.
getOffset
(
)
)
;
*
Dst
=
BrImm
;
break
;
}
default
:
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static bool frv_regstate_conflict_p ( regstate_t cond1 , regstate_t cond2 ) { if ( ( cond1 & REGSTATE_IF_EITHER ) == 0 || ( cond2 & REGSTATE_IF_EITHER ) == 0 ) return true ; if ( ( cond1 & REGSTATE_CC_MASK ) != ( cond2 & REGSTATE_CC_MASK ) ) return true ; if ( ( cond1 & cond2 & REGSTATE_IF_EITHER ) != 0 ) return true ; return false ; } </s>

Return true if something accessed under condition COND2 can conflict with something written under condition COND1 .


<s> bool TeakTargetLowering :: shouldReduceLoadWidth ( SDNode * Load , ISD :: LoadExtType ExtTy , EVT NewVT ) const { if ( NewVT . getSizeInBits ( ) == 8 ) return false ; return TargetLowering :: shouldReduceLoadWidth ( Load , ExtTy , NewVT ) ; } </s>

Return true if we believe it is correct and profitable to reduce the load node to a smaller type .


<s> TargetLowering :: ConstraintWeight PPCTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; if ( StringRef ( constraint ) == "wc" && type -> isIntegerTy ( 1 ) ) return CW_Register ; else if ( ( StringRef ( constraint ) == "wa" || StringRef ( constraint ) == "wd" || StringRef ( constraint ) == "wf" ) && type -> isVectorTy ( ) ) return CW_Register ; else if ( StringRef ( constraint ) == "ws" && type -> isDoubleTy ( ) ) return CW_Register ; else if ( StringRef ( constraint ) == "wi" && type -> isIntegerTy ( 64 ) ) return CW_Register ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'b' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; case 'd' : if ( type -> isDoubleTy ( ) ) weight = CW_Register ; break ; case 'v' : if ( type -> isVectorTy ( ) ) weight = CW_Register ; break ; case 'y' : weight = CW_Register ; break ; case 'Z' : weight = CW_Memory ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .

PowerPC PPC "wc" 1 "wa" "wd" "wf" "ws" "wi" 64


<s> void CSKYTargetStreamer :: emitTargetAttributes ( const MCSubtargetInfo & STI ) { } </s>

Emit the build attributes that only depend on the hardware that we expect .


<s> void SystemZPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & IfConverterID ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Hexagon Common GEP"
;
}
</s>


<s> SDValue getAddr ( NodeTy * N , SelectionDAG & DAG , bool IsLocal = true ) const { SDLoc DL ( N ) ; EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; unsigned Flag = CSKYII :: MO_None ; bool IsPIC = isPositionIndependent ( ) ; if ( IsPIC ) Flag = IsLocal ? CSKYII :: MO_GOTOFF : IsCall ? CSKYII :: MO_PLT32 : CSKYII :: MO_GOT32 ; SDValue TCPV = getTargetConstantPoolValue ( N , Ty , DAG , Flag ) ; SDValue TV = getTargetNode ( N , DL , Ty , DAG , Flag ) ; SDValue Addr = DAG . getNode ( CSKYISD :: LOAD_ADDR , DL , Ty , { TV , TCPV } ) ; if ( ! IsPIC ) return Addr ; SDValue Result = DAG . getNode ( ISD :: ADD , DL , Ty , { DAG . getGLOBAL_OFFSET_TABLE ( Ty ) , Addr } ) ; if ( IsLocal ) return Result ; return DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; } </s>

Return the address accessed by this recipe .


<s> static reg_class_t ix86_preferred_reload_class ( rtx x , reg_class_t regclass ) { machine_mode mode = GET_MODE ( x ) ; if ( regclass == NO_REGS ) return NO_REGS ; if ( x == CONST0_RTX ( mode ) ) return regclass ; if ( CONSTANT_P ( x ) && ( MAYBE_MMX_CLASS_P ( regclass ) || MAYBE_SSE_CLASS_P ( regclass ) || MAYBE_MASK_CLASS_P ( regclass ) ) ) return NO_REGS ; if ( TARGET_SSE_MATH && ! TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P ( mode ) ) return SSE_CLASS_P ( regclass ) ? regclass : NO_REGS ; if ( CONST_DOUBLE_P ( x ) ) { if ( reg_class_subset_p ( regclass , GENERAL_REGS ) ) return regclass ; if ( TARGET_80387 && standard_80387_constant_p ( x ) > 0 ) { if ( regclass == FLOAT_SSE_REGS ) return FLOAT_REGS ; if ( regclass == FP_TOP_SSE_REGS ) return FP_TOP_REG ; if ( regclass == FP_SECOND_SSE_REGS ) return FP_SECOND_REG ; if ( regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS ) return regclass ; } return NO_REGS ; } if ( GET_CODE ( x ) == PLUS ) return reg_class_subset_p ( regclass , GENERAL_REGS ) ? regclass : NO_REGS ; if ( GET_MODE ( x ) == QImode && ! CONSTANT_P ( x ) ) { if ( reg_class_subset_p ( regclass , Q_REGS ) ) return regclass ; if ( reg_class_subset_p ( Q_REGS , regclass ) ) return Q_REGS ; return NO_REGS ; } return regclass ; } </s>

Put float CONST_DOUBLE in the constant pool instead of fp regs . QImode must go into class Q_REGS . Narrow ALL_REGS to GENERAL_REGS . This supports allowing movsf and movdf to do mem-to-mem moves through integer regs .


"SIInstrInfo::storeRegToStackSlot - Do not know how to"


<s> static bool mips_rtx_constant_in_small_data_p ( machine_mode mode ) { return ( ! TARGET_EMBEDDED_DATA && TARGET_LOCAL_SDATA && GET_MODE_SIZE ( mode ) <= mips_small_data_threshold ) ; } </s>

Return true if rtx constants of mode MODE should be put into a small data section .


<s> static reg_class_t csky_preferred_reload_class ( rtx x , reg_class_t rclass ) { if ( TARGET_HARD_FLOAT && CONST_DOUBLE_P ( x ) && ( GET_MODE ( x ) == DFmode || GET_MODE ( x ) == SFmode ) && rclass == NO_REGS ) return GENERAL_REGS ; return rclass ; } </s>

Implement TARGET_PREFERRED_RELOAD_CLASS . Given an rtx X being reloaded into a reg required to be in class CLASS , return the class of reg to actually use . In general this is just CLASS .


<s> static void emit_frame_store_1 ( rtx value , rtx base_reg , HOST_WIDE_INT frame_bias , HOST_WIDE_INT base_ofs , rtx frame_reg ) { rtx addr , mem ; rtx_insn * insn ; addr = plus_constant ( Pmode , base_reg , base_ofs ) ; mem = gen_frame_mem ( DImode , addr ) ; insn = emit_move_insn ( mem , value ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( frame_bias || value != frame_reg ) { if ( frame_bias ) { addr = plus_constant ( Pmode , stack_pointer_rtx , frame_bias + base_ofs ) ; mem = gen_rtx_MEM ( DImode , addr ) ; } add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( mem , frame_reg ) ) ; } } </s>

Generates a store with the proper unwind info attached . VALUE is stored at BASE_REG+BASE_OFS . If FRAME_BIAS is nonzero , then BASE_REG contains SP+FRAME_BIAS , and that is the unwind info that should be generated . If FRAME_REG ! = VALUE , then VALUE is being stored on behalf of FRAME_REG , and FRAME_REG should be present in the unwind .


<s> static rtx aarch64_speculation_safe_value ( machine_mode mode , rtx result , rtx val , rtx failval ) { if ( ! aarch64_track_speculation ) return default_speculation_safe_value ( mode , result , val , failval ) ; if ( ! REG_P ( val ) ) val = copy_to_mode_reg ( mode , val ) ; if ( ! aarch64_reg_or_zero ( failval , mode ) ) failval = copy_to_mode_reg ( mode , failval ) ; emit_insn ( gen_despeculate_copy ( mode , result , val , failval ) ) ; return result ; } </s>

Override the default target speculation_safe_value .


<s> bool AArch64InstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF , bool OutlineFromLinkOnceODRs ) const { const Function & F = MF . getFunction ( ) ; if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) ) return false ; AArch64FunctionInfo * AFI = MF . getInfo < AArch64FunctionInfo > ( ) ; if ( ! AFI || AFI -> hasRedZone ( ) . getValueOr ( true ) ) return false ; return true ; } </s>

Return true if the function can safely be outlined from .


<s>
BitVector
ARMBaseRegisterInfo
::
getReservedRegs
(
const
MachineFunction
&
MF
)
const
{
const
ARMSubtarget
&
STI
=
MF
.
getSubtarget
<
ARMSubtarget
>
(
)
;
const
ARMFrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
BitVector
Reserved
(
getNumRegs
(
)
)
;
markSuperRegs
(
Reserved
,
ARM
::
SP
)
;
markSuperRegs
(
Reserved
,
ARM
::
PC
)
;
markSuperRegs
(
Reserved
,
ARM
::
FPSCR
)
;
markSuperRegs
(
Reserved
,
ARM
::
APSR_NZCV
)
;
if
(
TFI
->
hasFP
(
MF
)
||
STI
.
isTargetDarwin
(
)
)
markSuperRegs
(
Reserved
,
getFramePointerReg
(
STI
)
)
;
if
(
hasBasePointer
(
MF
)
)
markSuperRegs
(
Reserved
,
BasePtr
)
;
for
(
size_t
R
=
0
;
R
<
ARM
::
GPRRegClass
.
getNumRegs
(
)
;
++
R
)
{
if
(
STI
.
isGPRegisterReserved
(
R
)
)
{
markSuperRegs
(
Reserved
,
ARM
::
R0
+
R
)
;
}
}
if
(
!
STI
.
hasD32
(
)
)
{
static_assert
(
ARM
::
D31
==
ARM
::
D16
+
15
,
"Register list not consecutive!"
)
;
for
(
unsigned
R
=
0
;
R
<
16
;
++
R
)
markSuperRegs
(
Reserved
,
ARM
::
D16
+
R
)
;
}
const
TargetRegisterClass
&
RC
=
ARM
::
GPRPairRegClass
;
for
(
unsigned
Reg
:
RC
)
for
(
MCSubRegIterator
SI
(
Reg
,
this
)
;
SI
.
isValid
(
)
;
++
SI
)
if
(
Reserved
.
test
(
*
SI
)
)
markSuperRegs
(
Reserved
,
Reg
)
;
markSuperRegs
(
Reserved
,
ARM
::
ZR
)
;
assert
(
checkAllSuperRegsMarked
(
Reserved
)
)
;
return
Reserved
;
}
</s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void sparc_expand_prologue ( void ) { HOST_WIDE_INT size ; rtx_insn * insn ; sparc_leaf_function_p = optimize > 0 && crtl -> is_leaf && only_leaf_regs_used ( ) ; size = sparc_compute_frame_size ( get_frame_size ( ) , sparc_leaf_function_p ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = size ; if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK ) { if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { if ( size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT ) sparc_emit_probe_stack_range ( STACK_CHECK_PROTECT , size - STACK_CHECK_PROTECT ) ; } else if ( size > 0 ) sparc_emit_probe_stack_range ( STACK_CHECK_PROTECT , size ) ; } if ( size == 0 ) ; else if ( sparc_leaf_function_p ) { rtx size_int_rtx = GEN_INT ( - size ) ; if ( size <= 4096 ) insn = emit_insn ( gen_stack_pointer_inc ( size_int_rtx ) ) ; else if ( size <= 8192 ) { insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - 4096 ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( 4096 - size ) ) ) ; } else { rtx size_rtx = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( size_rtx , size_int_rtx ) ; insn = emit_insn ( gen_stack_pointer_inc ( size_rtx ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_stack_pointer_inc ( size_int_rtx ) ) ; } RTX_FRAME_RELATED_P ( insn ) = 1 ; } else { rtx size_int_rtx = GEN_INT ( - size ) ; if ( size <= 4096 ) emit_window_save ( size_int_rtx ) ; else if ( size <= 8192 ) { emit_window_save ( GEN_INT ( - 4096 ) ) ; emit_insn ( gen_stack_pointer_inc ( GEN_INT ( 4096 - size ) ) ) ; emit_insn ( gen_frame_blockage ( ) ) ; } else { rtx size_rtx = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( size_rtx , size_int_rtx ) ; emit_window_save ( size_rtx ) ; } } if ( sparc_leaf_function_p ) { sparc_frame_base_reg = stack_pointer_rtx ; sparc_frame_base_offset = size + SPARC_STACK_BIAS ; } else { sparc_frame_base_reg = hard_frame_pointer_rtx ; sparc_frame_base_offset = SPARC_STACK_BIAS ; } if ( sparc_n_global_fp_regs > 0 ) emit_save_or_restore_global_fp_regs ( sparc_frame_base_reg , sparc_frame_base_offset - sparc_apparent_frame_size , SORR_SAVE ) ; if ( crtl -> uses_pic_offset_table ) load_got_register ( ) ; sparc_prologue_data_valid_p = true ; } </s>

Expand the function prologue . The prologue is responsible for reserving storage for the frame , saving the call-saved registers and loading the PIC register if needed .


<s> void KudeyarInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { unsigned Opc ; Opc = Kudeyar :: MOV_RR ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } </s>


<s> bool SIInsertWaits :: runOnMachineFunction ( MachineFunction & MF ) { bool Changes = false ; TII = static_cast < const SIInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = static_cast < const SIRegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; MRI = & MF . getRegInfo ( ) ; WaitedOn = ZeroCounts ; LastIssued = ZeroCounts ; LastOpcodeType = OTHER ; LastInstWritesM0 = false ; ReturnsVoid = MF . getInfo < SIMachineFunctionInfo > ( ) -> returnsVoid ( ) ; memset ( & UsedRegs , 0 , sizeof ( UsedRegs ) ) ; memset ( & DefinedRegs , 0 , sizeof ( DefinedRegs ) ) ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { if ( I -> getOpcode ( ) == AMDGPU :: S_BARRIER ) Changes |= insertWait ( MBB , I , LastIssued ) ; else Changes |= insertWait ( MBB , I , handleOperands ( * I ) ) ; pushInstruction ( MBB , I ) ; handleSendMsg ( MBB , I ) ; } Changes |= insertWait ( MBB , MBB . getFirstTerminator ( ) , LastIssued ) ; if ( ! ReturnsVoid ) { MachineBasicBlock :: iterator I = MBB . getFirstTerminator ( ) ; if ( I != MBB . end ( ) && I -> getOpcode ( ) == AMDGPU :: S_ENDPGM ) I -> eraseFromParent ( ) ; } } return Changes ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool OR1KRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> bool mips_emit_scc ( enum rtx_code code , rtx target ) { if ( GET_MODE_CLASS ( GET_MODE ( cmp_operands [ 0 ] ) ) != MODE_INT ) return false ; target = gen_lowpart ( GET_MODE ( cmp_operands [ 0 ] ) , target ) ; if ( code == EQ || code == NE ) { rtx zie = mips_zero_if_equal ( cmp_operands [ 0 ] , cmp_operands [ 1 ] ) ; mips_emit_binary ( code , target , zie , const0_rtx ) ; } else mips_emit_int_relational ( code , 0 , target , cmp_operands [ 0 ] , cmp_operands [ 1 ] ) ; return true ; } </s>

Try comparing cmp_operands [ 0 ] and cmp_operands [ 1 ] using rtl code CODE . Store the result in TARGET and return true if successful . On 64-bit targets , TARGET may be wider than cmp_operands [ 0 ] .


"CFProtection used on invalid architecture!"

This virtual method can be overridden by targets that want to emit something at the start of their file .


<s> bool PPCSubtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = TargetSubtargetInfo :: ANTIDEP_CRITICAL ; CriticalPathRCs . clear ( ) ; if ( isPPC64 ( ) ) CriticalPathRCs . push_back ( & PPC :: G8RCRegClass ) ; else CriticalPathRCs . push_back ( & PPC :: GPRCRegClass ) ; CriticalPathRCs . push_back ( & PPC :: F8RCRegClass ) ; CriticalPathRCs . push_back ( & PPC :: VRRCRegClass ) ; return OptLevel >= CodeGenOpt :: Default ; } </s>

True if the subtarget should run a scheduler after register allocation .

PowerPC PPC PPC PPC::G8RCRegClass PPC::GPRCRegClass PPC::F8RCRegClass PPC::VRRCRegClass


<s> bool WinEHStatePass :: doInitialization ( Module & M ) { TheModule = & M ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> static bool compute_int_layout ( int bitpos , assign_data_t * data , int * pnregs ) { if ( data -> intoffset < 0 ) return false ; const int intoffset = data -> intoffset ; data -> intoffset = - 1 ; const int this_slotno = data -> slotno + intoffset / BITS_PER_WORD ; const unsigned int startbit = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; const unsigned int endbit = ROUND_UP ( bitpos , BITS_PER_WORD ) ; int nregs = ( endbit - startbit ) / BITS_PER_WORD ; if ( nregs > 0 && nregs > SPARC_INT_ARG_MAX - this_slotno ) { nregs = SPARC_INT_ARG_MAX - this_slotno ; data -> stack = 1 ; } if ( nregs <= 0 ) return false ; * pnregs = nregs ; return true ; } </s>

A subroutine of function_arg_record_value . Compute the number of integer registers to be assigned between PARMS- > intoffset and BITPOS . Return true if at least one integer register is assigned or false otherwise .


<s> BitVector SparcRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const SparcSubtarget & Subtarget = MF . getSubtarget < SparcSubtarget > ( ) ; Reserved . set ( SP :: G1 ) ; if ( ReserveAppRegisters ) { Reserved . set ( SP :: G2 ) ; Reserved . set ( SP :: G3 ) ; Reserved . set ( SP :: G4 ) ; } if ( ! Subtarget . is64Bit ( ) ) Reserved . set ( SP :: G5 ) ; Reserved . set ( SP :: O6 ) ; Reserved . set ( SP :: I6 ) ; Reserved . set ( SP :: I7 ) ; Reserved . set ( SP :: G0 ) ; Reserved . set ( SP :: G6 ) ; Reserved . set ( SP :: G7 ) ; Reserved . set ( SP :: G0_G1 ) ; if ( ReserveAppRegisters ) Reserved . set ( SP :: G2_G3 ) ; if ( ReserveAppRegisters || ! Subtarget . is64Bit ( ) ) Reserved . set ( SP :: G4_G5 ) ; Reserved . set ( SP :: O6_O7 ) ; Reserved . set ( SP :: I6_I7 ) ; Reserved . set ( SP :: G6_G7 ) ; if ( ! Subtarget . isV9 ( ) ) { for ( unsigned n = 0 ; n != 16 ; ++ n ) { for ( MCRegAliasIterator AI ( SP :: D16 + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; } } for ( unsigned n = 0 ; n < 31 ; n ++ ) Reserved . set ( SP :: ASR1 + n ) ; return Reserved ; } </s>


<s> static int arm_cortex_m_branch_cost ( bool speed_p , bool predictable_p ) { return ( TARGET_32BIT && speed_p ) ? 1 : arm_default_branch_cost ( speed_p , predictable_p ) ; } </s>

Thumb-2 branches are relatively cheap on Cortex-M processors ( `` 1 + P cycles '' on Cortex-M4 , where P varies from 1 to 3 according to some criteria ) , since sequences of non-executed instructions in IT blocks probably take the same amount of time as executed instructions ( and the IT instruction itself takes space in icache ) . This function was experimentally determined to give good results on a popular embedded benchmark .


<s> void ARMTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { unsigned BitWidth = Known . getBitWidth ( ) ; Known . resetAll ( ) ; switch ( Op . getOpcode ( ) ) { default : break ; case ARMISD :: ADDC : case ARMISD :: ADDE : case ARMISD :: SUBC : case ARMISD :: SUBE : if ( Op . getResNo ( ) == 0 ) { SDValue LHS = Op . getOperand ( 0 ) ; SDValue RHS = Op . getOperand ( 1 ) ; if ( Op -> getOpcode ( ) == ARMISD :: ADDE && isNullConstant ( LHS ) && isNullConstant ( RHS ) ) { Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - 1 ) ; return ; } } break ; case ARMISD :: CMOV : { DAG . computeKnownBits ( Op . getOperand ( 0 ) , Known , Depth + 1 ) ; if ( Known . isUnknown ( ) ) return ; KnownBits KnownRHS ; DAG . computeKnownBits ( Op . getOperand ( 1 ) , KnownRHS , Depth + 1 ) ; Known . Zero &= KnownRHS . Zero ; Known . One &= KnownRHS . One ; return ; } case ISD :: INTRINSIC_W_CHAIN : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ; Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case Intrinsic :: arm_ldaex : case Intrinsic :: arm_ldrex : { EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } } case ARMISD :: BFI : { DAG . computeKnownBits ( Op . getOperand ( 0 ) , Known , Depth + 1 ) ; ConstantSDNode * CI = cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ; const APInt & Mask = CI -> getAPIntValue ( ) ; Known . Zero &= Mask ; Known . One &= Mask ; return ; } } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> static int s390_adjust_priority ( rtx_insn * insn , int priority ) { if ( ! INSN_P ( insn ) ) return priority ; if ( s390_tune != PROCESSOR_2084_Z990 && s390_tune != PROCESSOR_2094_Z9_109 && s390_tune != PROCESSOR_2097_Z10 && s390_tune != PROCESSOR_2817_Z196 && s390_tune != PROCESSOR_2827_ZEC12 ) return priority ; switch ( s390_safe_attr_type ( insn ) ) { case TYPE_FSTOREDF : case TYPE_FSTORESF : priority = priority << 3 ; break ; case TYPE_STORE : case TYPE_STM : priority = priority << 1 ; break ; default : break ; } return priority ; } </s>

A C statement ( sans semicolon ) to update the integer scheduling priority INSN_PRIORITY ( INSN ) . Reduce the priority to execute the INSN earlier , increase the priority to execute INSN later . Do not define this macro if you do not need to adjust the scheduling priorities of insns . A LA instruction maybe scheduled later , since the pipeline bypasses the calculated value .


<s> bool AArch64TargetLowering :: isFMAFasterThanFMulAndFAdd ( const Function & F , Type * Ty ) const { switch ( Ty -> getScalarType ( ) -> getTypeID ( ) ) { case Type :: FloatTyID : case Type :: DoubleTyID : return true ; default : return false ; } } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


"********** Memory Intrinsic Results **********\n"

"MemIntrinsicResults expects liveness tracking"


<s> bool SITargetLowering :: isShuffleMaskLegal ( ArrayRef < int > , EVT ) const { return false ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s>
bool
PPCTargetLowering
::
isFPExtFree
(
EVT
DestVT
,
EVT
SrcVT
)
const
{
assert
(
DestVT
.
isFloatingPoint
(
)
&&
SrcVT
.
isFloatingPoint
(
)
&&
"invalid fpext types"
)
;
if
(
DestVT
==
MVT
::
f128
)
return
false
;
return
true
;
}
</s>

Return true if an fpext operation is free ( for instance , because single-precision floating-point numbers are implicitly extended to double-precision ) .

PowerPC
PPC
"invalid fpext types"
MVT::f128


<s> static reg_class_t m32c_preferred_output_reload_class ( rtx x , reg_class_t rclass ) { return m32c_preferred_reload_class ( x , rclass ) ; } </s>


"Stack realignment in presence of dynamic allocas is not supported with"


<s> void ix86_split_fp_branch ( enum rtx_code code , rtx op1 , rtx op2 , rtx target1 , rtx target2 , rtx tmp ) { rtx condition ; rtx i ; if ( target2 != pc_rtx ) { std :: swap ( target1 , target2 ) ; code = reverse_condition_maybe_unordered ( code ) ; } condition = ix86_expand_fp_compare ( code , op1 , op2 , tmp ) ; i = emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , condition , target1 , target2 ) ) ) ; if ( split_branch_probability >= 0 ) add_int_reg_note ( i , REG_BR_PROB , split_branch_probability ) ; } </s>

Split branch based on floating point condition .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( ! skipFunction ( MF . getFunction ( ) ) ) { initialize ( MF ) ; } return removeLD ( ) ; } </s>


<s> static bool expand_vec_perm_pshufb2 ( struct expand_vec_perm_d * d ) { rtx rperm [ 2 ] [ 16 ] , vperm , l , h , op , m128 ; unsigned int i , nelt , eltsz ; if ( ! TARGET_SSSE3 || GET_MODE_SIZE ( d -> vmode ) != 16 ) return false ; gcc_assert ( ! d -> one_operand_p ) ; if ( d -> testing_p ) return true ; nelt = d -> nelt ; eltsz = GET_MODE_SIZE ( GET_MODE_INNER ( d -> vmode ) ) ; m128 = GEN_INT ( - 128 ) ; for ( i = 0 ; i < nelt ; ++ i ) { unsigned j , e = d -> perm [ i ] ; unsigned which = ( e >= nelt ) ; if ( e >= nelt ) e -= nelt ; for ( j = 0 ; j < eltsz ; ++ j ) { rperm [ which ] [ i * eltsz + j ] = GEN_INT ( e * eltsz + j ) ; rperm [ 1 - which ] [ i * eltsz + j ] = m128 ; } } vperm = gen_rtx_CONST_VECTOR ( V16QImode , gen_rtvec_v ( 16 , rperm [ 0 ] ) ) ; vperm = force_reg ( V16QImode , vperm ) ; l = gen_reg_rtx ( V16QImode ) ; op = gen_lowpart ( V16QImode , d -> op0 ) ; emit_insn ( gen_ssse3_pshufbv16qi3 ( l , op , vperm ) ) ; vperm = gen_rtx_CONST_VECTOR ( V16QImode , gen_rtvec_v ( 16 , rperm [ 1 ] ) ) ; vperm = force_reg ( V16QImode , vperm ) ; h = gen_reg_rtx ( V16QImode ) ; op = gen_lowpart ( V16QImode , d -> op1 ) ; emit_insn ( gen_ssse3_pshufbv16qi3 ( h , op , vperm ) ) ; op = d -> target ; if ( d -> vmode != V16QImode ) op = gen_reg_rtx ( V16QImode ) ; emit_insn ( gen_iorv16qi3 ( op , l , h ) ) ; if ( op != d -> target ) emit_move_insn ( d -> target , gen_lowpart ( d -> vmode , op ) ) ; return true ; } </s>

A subroutine of expand_vec_perm_even_odd_1 . Implement the double-word permutation with two pshufb insns and an ior . We should have already failed all two instruction sequences .


<s>
void
HexagonInstPrinter
::
printInst
(
const
HexagonMCInst
*
MI
,
raw_ostream
&
O
,
StringRef
Annot
)
{
const
char
packetPadding
[
]
=
"      "
;
const
char
startPacket
=
'{'
,
endPacket
=
'}'
;
if
(
MI
->
getOpcode
(
)
==
Hexagon
::
ENDLOOP0
)
{
assert
(
MI
->
isEndPacket
(
)
&&
"Loop end must also end the packet"
)
;
if
(
MI
->
isStartPacket
(
)
)
{
HexagonMCInst
Nop
;
StringRef
NoAnnot
;
Nop
.
setOpcode
(
Hexagon
::
NOP
)
;
Nop
.
setStartPacket
(
MI
->
isStartPacket
(
)
)
;
printInst
(
&
Nop
,
O
,
NoAnnot
)
;
}
if
(
MI
->
isEndPacket
(
)
)
O
<<
packetPadding
<<
endPacket
;
printInstruction
(
MI
,
O
)
;
}
else
{
if
(
MI
->
isStartPacket
(
)
)
O
<<
packetPadding
<<
startPacket
<<
'\n'
;
printInstruction
(
MI
,
O
)
;
if
(
MI
->
isEndPacket
(
)
)
O
<<
'\n'
<<
packetPadding
<<
endPacket
;
}
printAnnotation
(
O
,
Annot
)
;
}
</s>

Print the specified MCInst to the specified raw_ostream .

Hexagon
Hexagon
Hexagon
"      "
Hexagon::ENDLOOP0
"Loop end must also end the packet"
Hexagon
Hexagon::NOP


<s> bool ARM64FastISel :: isTypeLegal ( Type * Ty , MVT & VT ) { EVT evt = TLI . getValueType ( Ty , true ) ; if ( evt == MVT :: Other || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; return TLI . isTypeLegal ( VT ) ; } </s>


<s> static void cygwin_d_register_target_info ( void ) { const struct d_target_info_spec handlers [ ] = { { "objectFormat" , cygwin_d_handle_target_object_format } , { NULL , NULL } , } ; d_add_target_info_handlers ( handlers ) ; } </s>

Implement TARGET_D_REGISTER_OS_TARGET_INFO for Cygwin targets .


<s> static int push_data_area ( v850_data_area data_area ) { data_area_stack_element * elem ; elem = ( data_area_stack_element * ) xmalloc ( sizeof ( * elem ) ) ; if ( elem == NULL ) return 0 ; elem -> prev = data_area_stack ; elem -> data_area = data_area ; data_area_stack = elem ; return 1 ; } </s>


<s>
bool
PPCInstrInfo
::
isReallyTriviallyReMaterializable
(
const
MachineInstr
&
MI
,
AliasAnalysis
*
AA
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown rematerializable operation!"
)
;
break
;
case
PPC
::
LI
:
case
PPC
::
LI8
:
case
PPC
::
PLI
:
case
PPC
::
PLI8
:
case
PPC
::
LIS
:
case
PPC
::
LIS8
:
case
PPC
::
ADDIStocHA
:
case
PPC
::
ADDIStocHA8
:
case
PPC
::
ADDItocL
:
case
PPC
::
LOAD_STACK_GUARD
:
case
PPC
::
XXLXORz
:
case
PPC
::
XXLXORspz
:
case
PPC
::
XXLXORdpz
:
case
PPC
::
XXLEQVOnes
:
case
PPC
::
XXSPLTI32DX
:
case
PPC
::
XXSPLTIW
:
case
PPC
::
XXSPLTIDP
:
case
PPC
::
V_SET0B
:
case
PPC
::
V_SET0H
:
case
PPC
::
V_SET0
:
case
PPC
::
V_SETALLONESB
:
case
PPC
::
V_SETALLONESH
:
case
PPC
::
V_SETALLONES
:
case
PPC
::
CRSET
:
case
PPC
::
CRUNSET
:
case
PPC
::
XXSETACCZ
:
return
true
;
}
return
false
;
}
</s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ReserveXRegister ( AArch64 :: GPR64commonRegClass . getNumRegs ( ) ) , CustomCallSavedXRegs ( AArch64 :: GPR64commonRegClass . getNumRegs ( ) ) , IsLittle ( LittleEndian ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS , CPU ) ) , TSInfo ( ) , TLInfo ( TM , * this ) { if ( AArch64 :: isX18ReservedByDefault ( TT ) ) ReserveXRegister . set ( 18 ) ; CallLoweringInfo . reset ( new AArch64CallLowering ( * getTargetLowering ( ) ) ) ; InlineAsmLoweringInfo . reset ( new InlineAsmLowering ( getTargetLowering ( ) ) ) ; Legalizer . reset ( new AArch64LegalizerInfo ( * this ) ) ; auto * RBI = new AArch64RegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( createAArch64InstructionSelector ( * static_cast < const AArch64TargetMachine * > ( & TM ) , * this , * RBI ) ) ; RegBankInfo . reset ( RBI ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


"unimplemented opcode in encodeInstruction()"

Encode the given Inst to bytes and append to CB .


<s> bool ARMTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , const Type * Ty ) const { EVT VT = getValueType ( Ty , true ) ; if ( ! isLegalAddressImmediate ( AM . BaseOffs , VT , Subtarget ) ) return false ; if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( Subtarget -> isThumb1Only ( ) ) return false ; default : if ( AM . BaseOffs ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( Subtarget -> isThumb2 ( ) ) return isLegalT2ScaledAddressingMode ( AM , VT ) ; int Scale = AM . Scale ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case MVT :: i1 : case MVT :: i8 : case MVT :: i32 : if ( Scale < 0 ) Scale = - Scale ; if ( Scale == 1 ) return true ; return isPowerOf2_32 ( Scale & ~ 1 ) ; case MVT :: i16 : case MVT :: i64 : if ( ( ( unsigned ) AM . HasBaseReg + Scale ) <= 2 ) return true ; return false ; case MVT :: isVoid : if ( Scale & 1 ) return false ; return isPowerOf2_32 ( Scale ) ; } break ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s>
bool
RISCVInstrInfo
::
isBranchOffsetInRange
(
unsigned
BranchOp
,
int64_t
BrOffset
)
const
{
unsigned
XLen
=
STI
.
getXLen
(
)
;
switch
(
BranchOp
)
{
default
:
llvm_unreachable
(
"Unexpected opcode!"
)
;
case
RISCV
::
BEQ
:
case
RISCV
::
BNE
:
case
RISCV
::
BLT
:
case
RISCV
::
BGE
:
case
RISCV
::
BLTU
:
case
RISCV
::
BGEU
:
case
RISCV
::
P_BEQIMM
:
case
RISCV
::
P_BNEIMM
:
return
isIntN
(
13
,
BrOffset
)
;
case
RISCV
::
JAL
:
case
RISCV
::
PseudoBR
:
return
isIntN
(
21
,
BrOffset
)
;
case
RISCV
::
PseudoJump
:
return
isIntN
(
32
,
SignExtend64
(
BrOffset
+
0x800
,
XLen
)
)
;
}
}
</s>

Determine if the branch target is in range .


<s> void SparcFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( ! DisableLeafProc && isLeafProc ( MF ) ) { SparcMachineFunctionInfo * MFI = MF . getInfo < SparcMachineFunctionInfo > ( ) ; MFI -> setLeafProc ( true ) ; remapRegsForLeafProc ( MF ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> bool SIRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const SIMachineFunctionInfo * Info = MF . getInfo < SIMachineFunctionInfo > ( ) ; if ( Info -> isEntryFunction ( ) ) return false ; return TargetRegisterInfo :: canRealignStack ( MF ) ; } </s>

True if the stack can be realigned for the target .


<s>
const
char
*
output_reload_insisf
(
rtx
*
op
,
rtx
clobber_reg
,
int
*
len
)
{
if
(
AVR_HAVE_MOVW
&&
!
test_hard_reg_class
(
LD_REGS
,
op
[
0
]
)
&&
(
CONST_INT_P
(
op
[
1
]
)
||
CONST_FIXED_P
(
op
[
1
]
)
||
CONST_DOUBLE_P
(
op
[
1
]
)
)
)
{
int
len_clr
,
len_noclr
;
output_reload_in_const
(
op
,
clobber_reg
,
&
len_clr
,
true
)
;
output_reload_in_const
(
op
,
clobber_reg
,
&
len_noclr
,
false
)
;
if
(
len_noclr
len_clr
==
4
)
{
avr_asm_len
(
"mov %A0,__zero_reg__"
CR_TAB
"mov %B0,__zero_reg__"
CR_TAB
"movw %C0,%A0"
,
&
op
[
0
]
,
len
,
3
)
;
output_reload_in_const
(
op
,
clobber_reg
,
len
,
true
)
;
if
(
len
)
*
len
+=
3
;
return
""
;
}
}
output_reload_in_const
(
op
,
clobber_reg
,
len
,
false
)
;
return
""
;
}
</s>

Reload a SI or SF compile time constant OP [ 1 ] into the register OP [ 0 ] . CLOBBER_REG is a QI clobber reg needed to move vast majority of consts into a NO_LD_REGS register . If CLOBBER_REG is NULL_RTX we either do n't need a clobber reg or have to cook one up . LEN == NULL : Output instructions . LEN ! = NULL : Output nothing . Set * LEN to number of words occupied by the insns printed . Return `` '' .


<s> bool AArch64TargetLowering :: isVectorLoadExtDesirable ( SDValue ExtVal ) const { return ExtVal . getValueType ( ) . isScalableVector ( ) ; } </s>

Return true if folding a vector load into ExtVal ( a sign , zero , or any extend node ) is profitable .


<s> void NyuziAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } while ( ( ++ I != E ) && I -> isInsideBundle ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> SDNode * HexagonDAGToDAGISel :: Select ( SDNode * N ) { if ( N -> isMachineOpcode ( ) ) return NULL ; switch ( N -> getOpcode ( ) ) { case ISD :: Constant : return SelectConstant ( N ) ; case ISD :: ADD : return SelectAdd ( N ) ; case ISD :: SHL : return SelectSHL ( N ) ; case ISD :: LOAD : return SelectLoad ( N ) ; case ISD :: STORE : return SelectStore ( N ) ; case ISD :: SELECT : return SelectSelect ( N ) ; case ISD :: TRUNCATE : return SelectTruncate ( N ) ; case ISD :: MUL : return SelectMul ( N ) ; case ISD :: ZERO_EXTEND : return SelectZeroExtend ( N ) ; case ISD :: INTRINSIC_WO_CHAIN : return SelectIntrinsicWOChain ( N ) ; } return SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .

Hexagon Hexagon ISD::Constant ISD::ADD ISD::SHL ISD::LOAD ISD::STORE ISD::SELECT ISD::TRUNCATE ISD::MUL ISD::ZERO_EXTEND ISD::INTRINSIC_WO_CHAIN


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addRequired < PostDominatorTreeWrapperPass > ( ) ; AU . addPreserved < PostDominatorTreeWrapperPass > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void MipsAsmPrinter :: emitEndOfAsmFile ( Module & M ) { for ( std :: map < const char * , const Mips16HardFloatInfo :: FuncSignature * > :: const_iterator it = StubsNeeded . begin ( ) ; it != StubsNeeded . end ( ) ; ++ it ) { const char * Symbol = it -> first ; const Mips16HardFloatInfo :: FuncSignature * Signature = it -> second ; EmitFPCallStub ( Symbol , Signature ) ; } OutStreamer -> SwitchSection ( OutContext . getObjectFileInfo ( ) -> getTextSection ( ) ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s>
unsigned
SIInstrInfo
::
getInstSizeInBytes
(
const
MachineInstr
&
MI
)
const
{
unsigned
Opc
=
MI
.
getOpcode
(
)
;
const
MCInstrDesc
&
Desc
=
getMCOpcodeFromPseudo
(
Opc
)
;
unsigned
DescSize
=
Desc
.
getSize
(
)
;
if
(
DescSize
==
8
||
DescSize
==
4
)
return
DescSize
;
assert
(
DescSize
==
0
)
;
if
(
isVALU
(
MI
)
||
isSALU
(
MI
)
)
{
int
Src0Idx
=
AMDGPU
::
getNamedOperandIdx
(
Opc
,
AMDGPU
::
OpName
::
src0
)
;
if
(
Src0Idx
==
1
)
return
4
;
if
(
isLiteralConstantLike
(
MI
.
getOperand
(
Src0Idx
)
,
getOpSize
(
MI
,
Src0Idx
)
)
)
return
8
;
int
Src1Idx
=
AMDGPU
::
getNamedOperandIdx
(
Opc
,
AMDGPU
::
OpName
::
src1
)
;
if
(
Src1Idx
==
1
)
return
4
;
if
(
isLiteralConstantLike
(
MI
.
getOperand
(
Src1Idx
)
,
getOpSize
(
MI
,
Src1Idx
)
)
)
return
8
;
return
4
;
}
switch
(
Opc
)
{
case
TargetOpcode
::
IMPLICIT_DEF
:
case
TargetOpcode
::
KILL
:
case
TargetOpcode
::
DBG_VALUE
:
case
TargetOpcode
::
BUNDLE
:
case
TargetOpcode
::
EH_LABEL
:
return
0
;
case
TargetOpcode
::
INLINEASM
:
{
const
MachineFunction
*
MF
=
MI
.
getParent
(
)
->
getParent
(
)
;
const
char
*
AsmStr
=
MI
.
getOperand
(
0
)
.
getSymbolName
(
)
;
return
getInlineAsmLength
(
AsmStr
,
*
MF
->
getTarget
(
)
.
getMCAsmInfo
(
)
)
;
}
default
:
llvm_unreachable
(
"unable to find instruction size"
)
;
}
}
</s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> int neon_struct_mem_operand ( rtx op ) { rtx ind ; if ( ! ( reload_in_progress || reload_completed ) && ( reg_mentioned_p ( frame_pointer_rtx , op ) || reg_mentioned_p ( arg_pointer_rtx , op ) || reg_mentioned_p ( virtual_incoming_args_rtx , op ) || reg_mentioned_p ( virtual_outgoing_args_rtx , op ) || reg_mentioned_p ( virtual_stack_dynamic_rtx , op ) || reg_mentioned_p ( virtual_stack_vars_rtx , op ) ) ) return FALSE ; if ( ! MEM_P ( op ) ) return FALSE ; ind = XEXP ( op , 0 ) ; if ( reload_completed && ( LABEL_REF_P ( ind ) || ( GET_CODE ( ind ) == CONST && GET_CODE ( XEXP ( ind , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( ind , 0 ) , 0 ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( ind , 0 ) , 1 ) ) ) ) ) return TRUE ; if ( REG_P ( ind ) ) return arm_address_register_rtx_p ( ind , 0 ) ; if ( GET_CODE ( ind ) == POST_INC || GET_CODE ( ind ) == PRE_DEC ) return arm_address_register_rtx_p ( XEXP ( ind , 0 ) , 0 ) ; return FALSE ; } </s>

Return TRUE if OP is a mem suitable for loading/storing a Neon struct type .


<s> unsigned int compute_a_shift_length ( rtx operands [ 3 ] , rtx_code code ) { enum machine_mode mode = GET_MODE ( operands [ 0 ] ) ; enum shift_type shift_type ; enum shift_mode shift_mode ; struct shift_info info ; unsigned int wlength = 0 ; switch ( mode ) { case E_QImode : shift_mode = QIshift ; break ; case E_HImode : shift_mode = HIshift ; break ; case E_SImode : shift_mode = SIshift ; break ; default : gcc_unreachable ( ) ; } switch ( code ) { case ASHIFTRT : shift_type = SHIFT_ASHIFTRT ; break ; case LSHIFTRT : shift_type = SHIFT_LSHIFTRT ; break ; case ASHIFT : shift_type = SHIFT_ASHIFT ; break ; default : gcc_unreachable ( ) ; } if ( GET_CODE ( operands [ 2 ] ) != CONST_INT ) { get_shift_alg ( shift_type , shift_mode , 1 , & info ) ; return ( 4 + h8300_asm_insn_count ( info . shift1 ) ) * 2 ; } else { int n = INTVAL ( operands [ 2 ] ) ; if ( n < 0 ) n = 0 ; else if ( ( unsigned int ) n > GET_MODE_BITSIZE ( mode ) ) n = GET_MODE_BITSIZE ( mode ) ; get_shift_alg ( shift_type , shift_mode , n , & info ) ; switch ( info . alg ) { case SHIFT_SPECIAL : wlength += h8300_asm_insn_count ( info . special ) ; if ( strstr ( info . special , "xor.l" ) != NULL ) wlength ++ ; case SHIFT_INLINE : n = info . remainder ; if ( info . shift2 != NULL ) { wlength += h8300_asm_insn_count ( info . shift2 ) * ( n / 2 ) ; n = n % 2 ; } wlength += h8300_asm_insn_count ( info . shift1 ) * n ; return 2 * wlength ; case SHIFT_ROT_AND : { int m = GET_MODE_BITSIZE ( mode ) - n ; gcc_assert ( info . shift1 ) ; if ( info . shift2 != NULL ) { wlength += h8300_asm_insn_count ( info . shift2 ) * ( m / 2 ) ; m = m % 2 ; } wlength += h8300_asm_insn_count ( info . shift1 ) * m ; switch ( mode ) { case E_QImode : wlength += 1 ; break ; case E_HImode : wlength += 2 ; break ; case E_SImode : wlength += 3 ; break ; default : gcc_unreachable ( ) ; } return 2 * wlength ; } case SHIFT_LOOP : if ( info . shift2 != NULL ) { wlength += 3 + h8300_asm_insn_count ( info . shift2 ) ; if ( n % 2 ) wlength += h8300_asm_insn_count ( info . shift1 ) ; } else { wlength += 3 + h8300_asm_insn_count ( info . shift1 ) ; } return 2 * wlength ; default : gcc_unreachable ( ) ; } } } </s>


<s> static void arc_setup_incoming_varargs ( cumulative_args_t args_so_far , machine_mode mode , tree type , int * pretend_size , int no_rtl ) { int first_anon_arg ; CUMULATIVE_ARGS next_cum ; next_cum = * get_cumulative_args ( args_so_far ) ; arc_function_arg_advance ( pack_cumulative_args ( & next_cum ) , mode , type , 1 ) ; first_anon_arg = next_cum ; if ( first_anon_arg < MAX_ARC_PARM_REGS ) { int first_reg_offset = first_anon_arg ; if ( ! no_rtl ) { rtx regblock = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , arg_pointer_rtx , FIRST_PARM_OFFSET ( 0 ) ) ) ; move_block_from_reg ( first_reg_offset , regblock , MAX_ARC_PARM_REGS - first_reg_offset ) ; } * pretend_size = ( ( MAX_ARC_PARM_REGS - first_reg_offset ) * UNITS_PER_WORD ) ; } } </s>

Do any needed setup for a variadic function . For the ARC , we must create a register parameter block , and then copy any anonymous arguments in registers to memory . CUM has not been updated for the last named argument which has type TYPE and mode MODE , and we rely on this fact .


<s> BitVector AArch64RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const AArch64FrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , AArch64 :: WSP ) ; markSuperRegs ( Reserved , AArch64 :: WZR ) ; if ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) markSuperRegs ( Reserved , AArch64 :: W29 ) ; for ( size_t i = 0 ; i < AArch64 :: GPR32commonRegClass . getNumRegs ( ) ; ++ i ) { if ( MF . getSubtarget < AArch64Subtarget > ( ) . isXRegisterReserved ( i ) ) markSuperRegs ( Reserved , AArch64 :: GPR32commonRegClass . getRegister ( i ) ) ; } if ( hasBasePointer ( MF ) ) markSuperRegs ( Reserved , AArch64 :: W19 ) ; if ( MF . getFunction ( ) . hasFnAttribute ( Attribute :: SpeculativeLoadHardening ) ) markSuperRegs ( Reserved , AArch64 :: W16 ) ; if ( MF . getFunction ( ) . isPagerando ( ) ) markSuperRegs ( Reserved , AArch64 :: W20 ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
const
CallLowering
*
X86Subtarget
::
getCallLowering
(
)
const
{
assert
(
GISel
&&
"Access to GlobalISel APIs not set"
)
;
return
GISel
->
getCallLowering
(
)
;
}
</s>


<s> static rtx_insn * mips_break_sequence ( rtx_insn * insn ) { rtx_insn * before = PREV_INSN ( insn ) ; rtx_insn * branch = SEQ_BEGIN ( insn ) ; rtx_insn * ds = SEQ_END ( insn ) ; remove_insn ( insn ) ; add_insn_after ( ds , before , NULL ) ; add_insn_after ( branch , ds , NULL ) ; return ds ; } </s>

Remove a SEQUENCE and replace it with the delay slot instruction followed by the branch and return the instruction in the delay slot . Return the first of the two new instructions . Subroutine of mips_reorg_process_insns .


<s> bool X86PartialReduction :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; auto & TM = TPC -> getTM < X86TargetMachine > ( ) ; ST = TM . getSubtargetImpl ( F ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; bool MadeChange = false ; for ( auto & BB : F ) { for ( auto & I : BB ) { auto * EE = dyn_cast < ExtractElementInst > ( & I ) ; if ( ! EE ) continue ; bool ReduceInOneBB ; Value * Root = matchAddReduction ( * EE , ReduceInOneBB ) ; if ( ! Root ) continue ; SmallVector < Instruction * , 8 > Leaves ; collectLeaves ( Root , Leaves ) ; for ( Instruction * I : Leaves ) { if ( tryMAddReplacement ( I , ReduceInOneBB ) ) { MadeChange = true ; continue ; } if ( I != Root && trySADReplacement ( I ) ) MadeChange = true ; } } } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> const MCExpr * getSubExpr ( ) const { return Expr ; } </s>

getSubExpr - Get the child of this expression .


<s> void btf_ext_init ( void ) { btf_ext_info_section = get_section ( BTF_EXT_INFO_SECTION_NAME , BTF_EXT_INFO_SECTION_FLAGS , NULL ) ; ASM_GENERATE_INTERNAL_LABEL ( btf_ext_info_section_label , BTF_EXT_INFO_SECTION_LABEL , btf_ext_label_num ++ ) ; vec_alloc ( bpf_core_sections , 1 ) ; } </s>

Initialize sections , labels , and data structures for BTF.ext output .


<s> static enum attr_op_type sched_attr_op_type ( rtx_insn * insn , bool opx_p , bool address_p ) { rtx op ; op = sched_get_operand ( insn , opx_p ) ; if ( op == NULL ) { gcc_assert ( ! reload_completed ) ; return OP_TYPE_RN ; } if ( address_p ) return sched_address_type ( QImode , op ) ; if ( memory_operand ( op , VOIDmode ) ) return sched_address_type ( GET_MODE ( op ) , XEXP ( op , 0 ) ) ; if ( register_operand ( op , VOIDmode ) ) { if ( ( ! reload_completed && FLOAT_MODE_P ( GET_MODE ( op ) ) ) || ( reload_completed && FP_REG_P ( op ) ) ) return OP_TYPE_FPN ; return OP_TYPE_RN ; } if ( GET_CODE ( op ) == CONST_INT ) { int ival ; ival = INTVAL ( op ) ; switch ( get_attr_type ( insn ) ) { case TYPE_ALUQ_L : if ( IN_RANGE ( ival , 1 , 8 ) || IN_RANGE ( ival , - 8 , - 1 ) ) return OP_TYPE_IMM_Q ; gcc_assert ( ! reload_completed ) ; break ; case TYPE_MOVEQ_L : if ( USE_MOVQ ( ival ) ) return OP_TYPE_IMM_Q ; gcc_assert ( ! reload_completed ) ; break ; case TYPE_MOV3Q_L : if ( valid_mov3q_const ( ival ) ) return OP_TYPE_IMM_Q ; gcc_assert ( ! reload_completed ) ; break ; default : break ; } if ( IN_RANGE ( ival , - 0x8000 , 0x7fff ) ) return OP_TYPE_IMM_W ; return OP_TYPE_IMM_L ; } if ( GET_CODE ( op ) == CONST_DOUBLE ) { switch ( GET_MODE ( op ) ) { case SFmode : return OP_TYPE_IMM_W ; case VOIDmode : case DFmode : return OP_TYPE_IMM_L ; default : gcc_unreachable ( ) ; } } if ( GET_CODE ( op ) == CONST || symbolic_operand ( op , VOIDmode ) || LABEL_P ( op ) ) { switch ( GET_MODE ( op ) ) { case QImode : return OP_TYPE_IMM_Q ; case HImode : return OP_TYPE_IMM_W ; case SImode : return OP_TYPE_IMM_L ; default : if ( symbolic_operand ( m68k_unwrap_symbol ( op , false ) , VOIDmode ) ) return OP_TYPE_IMM_W ; return OP_TYPE_IMM_L ; } } gcc_assert ( ! reload_completed ) ; if ( FLOAT_MODE_P ( GET_MODE ( op ) ) ) return OP_TYPE_FPN ; return OP_TYPE_RN ; } </s>

Return type of INSN 's operand X ( if OPX_P ) or operand Y ( if ! OPX_P ) . If ADDRESS_P is true , return type of memory location operand refers to .


<s> static rtx mips_expand_builtin_compare ( enum mips_builtin_type builtin_type , enum insn_code icode , enum mips_fp_condition cond , rtx target , tree arglist ) { rtx label1 , label2 , if_then_else ; rtx pat , cmp_result , ops [ MAX_RECOG_OPERANDS ] ; rtx target_if_equal , target_if_unequal ; int cmp_value , i ; if ( target == 0 || GET_MODE ( target ) != SImode ) target = gen_reg_rtx ( SImode ) ; cmp_result = mips_prepare_builtin_target ( icode , 0 , 0 ) ; for ( i = 1 ; i < insn_data [ icode ] . n_operands - 1 ; i ++ ) ops [ i ] = mips_prepare_builtin_arg ( icode , i , & arglist ) ; switch ( insn_data [ icode ] . n_operands ) { case 4 : pat = GEN_FCN ( icode ) ( cmp_result , ops [ 1 ] , ops [ 2 ] , GEN_INT ( cond ) ) ; break ; case 6 : pat = GEN_FCN ( icode ) ( cmp_result , ops [ 1 ] , ops [ 2 ] , ops [ 3 ] , ops [ 4 ] , GEN_INT ( cond ) ) ; break ; default : gcc_unreachable ( ) ; } if ( builtin_type == MIPS_BUILTIN_CMP_ALL ) { cmp_value = - 1 ; target_if_equal = const1_rtx ; target_if_unequal = const0_rtx ; } else { cmp_value = 0 ; target_if_equal = const0_rtx ; target_if_unequal = const1_rtx ; if ( builtin_type == MIPS_BUILTIN_CMP_UPPER ) cmp_result = simplify_gen_subreg ( CCmode , cmp_result , CCV2mode , 4 ) ; else if ( builtin_type == MIPS_BUILTIN_CMP_LOWER ) cmp_result = simplify_gen_subreg ( CCmode , cmp_result , CCV2mode , 0 ) ; } emit_move_insn ( target , target_if_equal ) ; emit_insn ( pat ) ; label1 = gen_label_rtx ( ) ; label2 = gen_label_rtx ( ) ; if_then_else = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( NE , GET_MODE ( cmp_result ) , cmp_result , GEN_INT ( cmp_value ) ) , gen_rtx_LABEL_REF ( VOIDmode , label1 ) , pc_rtx ) ; emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , if_then_else ) ) ; emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_LABEL_REF ( VOIDmode , label2 ) ) ) ; emit_barrier ( ) ; emit_label ( label1 ) ; emit_move_insn ( target , target_if_unequal ) ; emit_label ( label2 ) ; return target ; } </s>

Expand a comparison builtin of type BUILTIN_TYPE . ICODE is the code of the comparison instruction and COND is the condition it should test . ARGLIST is the list of function arguments and TARGET , if nonnull , suggests a good place to put the boolean result .


<s> bool ARMFastISel :: isTypeLegal ( const Type * Ty , MVT & VT ) { EVT evt = TLI . getValueType ( Ty , true ) ; if ( evt == MVT :: Other || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; return TLI . isTypeLegal ( VT ) ; } </s>


<s> bool ARMTargetLowering :: isMulAddWithConstProfitable ( const SDValue & AddNode , const SDValue & ConstNode ) const { const EVT VT = AddNode . getValueType ( ) ; if ( VT . isVector ( ) || VT . getScalarSizeInBits ( ) > 32 ) return true ; const ConstantSDNode * C0Node = cast < ConstantSDNode > ( AddNode . getOperand ( 1 ) ) ; const ConstantSDNode * C1Node = cast < ConstantSDNode > ( ConstNode ) ; const int64_t C0 = C0Node -> getSExtValue ( ) ; APInt CA = C0Node -> getAPIntValue ( ) * C1Node -> getAPIntValue ( ) ; if ( ! isLegalAddImmediate ( C0 ) || isLegalAddImmediate ( CA . getSExtValue ( ) ) ) return true ; if ( ConstantMaterializationCost ( ( unsigned ) CA . getZExtValue ( ) , Subtarget ) > 1 ) return false ; return true ; } </s>

Return true if it may be profitable to transform ( mul ( add x , c1 ) , c2 ) - > ( add ( mul x , c2 ) , c1 * c2 ) .


<s> unsigned getOffsetReg ( ) const { return OffsetReg ; } </s>

Get the offset register of the pointer value .


<s> bool AArch64FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( MF . hasEHFunclets ( ) ) return true ; if ( MFI . hasCalls ( ) && MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) return true ; if ( MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || RegInfo -> needsStackRealignment ( MF ) ) return true ; if ( ! MFI . isMaxCallFrameSizeComputed ( ) || MFI . getMaxCallFrameSize ( ) > DefaultSafeSPDisplacement ) return true ; return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .