<s> Optional < MCFixupKind > ARMAsmBackend :: getFixupKind ( StringRef Name ) const { if ( STI . getTargetTriple ( ) . isOSBinFormatELF ( ) && Name == "R_ARM_NONE" ) return FK_NONE ; return MCAsmBackend :: getFixupKind ( Name ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s>
unsigned
assignCustomValue
(
ARMCallLowering
::
ArgInfo
&
Arg
,
ArrayRef
<
CCValAssign
>
VAs
)
override
{
assert
(
Arg
.
Regs
.
size
(
)
==
1
&&
"Can't handle multple regs yet"
)
;
CCValAssign
VA
=
VAs
[
0
]
;
assert
(
VA
.
needsCustom
(
)
&&
"Value doesn't need custom handling"
)
;
if
(
VA
.
getValVT
(
)
!=
MVT
::
f64
)
return
0
;
CCValAssign
NextVA
=
VAs
[
1
]
;
assert
(
NextVA
.
needsCustom
(
)
&&
"Value doesn't need custom handling"
)
;
assert
(
NextVA
.
getValVT
(
)
==
MVT
::
f64
&&
"Unsupported type"
)
;
assert
(
VA
.
getValNo
(
)
==
NextVA
.
getValNo
(
)
&&
"Values belong to different arguments"
)
;
assert
(
VA
.
isRegLoc
(
)
&&
"Value should be in reg"
)
;
assert
(
NextVA
.
isRegLoc
(
)
&&
"Value should be in reg"
)
;
Register
NewRegs
[
]
=
{
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
32
)
)
,
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
32
)
)
}
;
assignValueToReg
(
NewRegs
[
0
]
,
VA
.
getLocReg
(
)
,
VA
)
;
assignValueToReg
(
NewRegs
[
1
]
,
NextVA
.
getLocReg
(
)
,
NextVA
)
;
bool
IsLittle
=
MIRBuilder
.
getMF
(
)
.
getSubtarget
<
ARMSubtarget
>
(
)
.
isLittle
(
)
;
if
(
!
IsLittle
)
std
::
swap
(
NewRegs
[
0
]
,
NewRegs
[
1
]
)
;
MIRBuilder
.
buildMerge
(
Arg
.
Regs
[
0
]
,
NewRegs
)
;
return
1
;
}
</s>

Handle custom values , which may be passed into one or more of VAs .


<s> void MipsTargetELFStreamer :: finish ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; const MCObjectFileInfo & OFI = * MCA . getContext ( ) . getObjectFileInfo ( ) ; MCSection & TextSection = * OFI . getTextSection ( ) ; MCA . registerSection ( TextSection ) ; MCSection & DataSection = * OFI . getDataSection ( ) ; MCA . registerSection ( DataSection ) ; MCSection & BSSSection = * OFI . getBSSSection ( ) ; MCA . registerSection ( BSSSection ) ; TextSection . setAlignment ( Align ( std :: max ( 16u , TextSection . getAlignment ( ) ) ) ) ; DataSection . setAlignment ( Align ( std :: max ( 16u , DataSection . getAlignment ( ) ) ) ) ; BSSSection . setAlignment ( Align ( std :: max ( 16u , BSSSection . getAlignment ( ) ) ) ) ; if ( RoundSectionSizes ) { MCStreamer & OS = getStreamer ( ) ; for ( MCSection & S : MCA ) { MCSectionELF & Section = static_cast < MCSectionELF & > ( S ) ; unsigned Alignment = Section . getAlignment ( ) ; if ( Alignment ) { OS . SwitchSection ( & Section ) ; if ( Section . useCodeAlign ( ) ) OS . emitCodeAlignment ( Alignment , & STI , Alignment ) ; else OS . emitValueToAlignment ( Alignment , 0 , 1 , Alignment ) ; } } } const FeatureBitset & Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI_O32 ; else if ( getABI ( ) . IsN32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI2 ; if ( Features [ Mips :: FeatureGP64Bit ] ) { if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_32BITMODE ; } else if ( Features [ Mips :: FeatureMips64r2 ] || Features [ Mips :: FeatureMips64 ] ) EFlags |= ELF :: EF_MIPS_32BITMODE ; if ( ! Features [ Mips :: FeatureNoABICalls ] ) EFlags |= ELF :: EF_MIPS_CPIC ; if ( Pic ) EFlags |= ELF :: EF_MIPS_PIC | ELF :: EF_MIPS_CPIC ; MCA . setELFHeaderEFlags ( EFlags ) ; MipsELFStreamer & MEF = static_cast < MipsELFStreamer & > ( Streamer ) ; MEF . EmitMipsOptionRecords ( ) ; emitMipsAbiFlags ( ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> virtual const mprocSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
unsigned
getGlobalBaseReg
(
)
const
{
WDC_LOG
(
"Returning "
<<
GlobalBaseReg
)
;
return
GlobalBaseReg
;
}
</s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static int unicosmk_need_dex ( rtx x ATTRIBUTE_UNUSED ) { return 0 ; } </s>

Return the DEX number if X must be replaced by a DEX expression and 0 otherwise .


<s> bool SystemZInstrInfo :: isUnpredicatedTerminator ( const MachineInstr * MI ) const { const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( ! MCID . isTerminator ( ) ) return false ; if ( MCID . isBranch ( ) && ! MCID . isBarrier ( ) ) return true ; if ( ! MCID . isPredicable ( ) ) return true ; return ! isPredicated ( MI ) ; } </s>

Returns true if the instruction is a terminator instruction that has not been predicated .


<s> EVT ARMTargetLowering :: getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const { if ( ( Op . isMemcpy ( ) || Op . isZeroMemset ( ) ) && Subtarget -> hasNEON ( ) && ! FuncAttributes . hasFnAttr ( Attribute :: NoImplicitFloat ) ) { bool Fast ; if ( Op . size ( ) >= 16 && ( Op . isAligned ( Align ( 16 ) ) || ( allowsMisalignedMemoryAccesses ( MVT :: v2f64 , 0 , Align ( 1 ) , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) { return MVT :: v2f64 ; } else if ( Op . size ( ) >= 8 && ( Op . isAligned ( Align ( 8 ) ) || ( allowsMisalignedMemoryAccesses ( MVT :: f64 , 0 , Align ( 1 ) , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) { return MVT :: f64 ; } } return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> DecodeStatus M68kDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CStream ) const { DecodeStatus Result ; auto MakeUp = [ & ] ( APInt & Insn , unsigned InstrBits ) { unsigned Idx = Insn . getBitWidth ( ) >> 3 ; unsigned RoundUp = alignTo ( InstrBits , Align ( 16 ) ) ; if ( RoundUp > Insn . getBitWidth ( ) ) Insn = Insn . zext ( RoundUp ) ; RoundUp = RoundUp >> 3 ; for ( ; Idx < RoundUp ; Idx += 2 ) { Insn . insertBits ( support :: endian :: read16be ( & Bytes [ Idx ] ) , Idx * 8 , 16 ) ; } } ; APInt Insn ( 16 , support :: endian :: read16be ( Bytes . data ( ) ) ) ; Size = 2 ; Result = decodeInstruction ( DecoderTable80 , Instr , Insn , Address , this , STI , MakeUp ) ; if ( Result == DecodeStatus :: Success ) Size = InstrLenTable [ Instr . getOpcode ( ) ] >> 3 ; return Result ; } </s>

Returns the disassembly of a single instruction .


<s>
SDValue
VETargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
LLVM_DEBUG
(
dbgs
(
)
<<
"::LowerOperation"
;
Op
->
print
(
dbgs
(
)
)
;
)
;
unsigned
Opcode
=
Op
.
getOpcode
(
)
;
switch
(
Opcode
)
{
case
ISD
::
ATOMIC_FENCE
:
return
lowerATOMIC_FENCE
(
Op
,
DAG
)
;
case
ISD
::
ATOMIC_SWAP
:
return
lowerATOMIC_SWAP
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
lowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
lowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
lowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
EH_SJLJ_LONGJMP
:
return
lowerEH_SJLJ_LONGJMP
(
Op
,
DAG
)
;
case
ISD
::
EH_SJLJ_SETJMP
:
return
lowerEH_SJLJ_SETJMP
(
Op
,
DAG
)
;
case
ISD
::
EH_SJLJ_SETUP_DISPATCH
:
return
lowerEH_SJLJ_SETUP_DISPATCH
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
lowerFRAMEADDR
(
Op
,
DAG
,
*
this
,
Subtarget
)
;
case
ISD
::
GlobalAddress
:
return
lowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
lowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
lowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
lowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
LOAD
:
return
lowerLOAD
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
lowerRETURNADDR
(
Op
,
DAG
,
*
this
,
Subtarget
)
;
case
ISD
::
BUILD_VECTOR
:
return
lowerBUILD_VECTOR
(
Op
,
DAG
)
;
case
ISD
::
STORE
:
return
lowerSTORE
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
lowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
VAARG
:
return
lowerVAARG
(
Op
,
DAG
)
;
case
ISD
::
INSERT_VECTOR_ELT
:
return
lowerINSERT_VECTOR_ELT
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_VECTOR_ELT
:
return
lowerEXTRACT_VECTOR_ELT
(
Op
,
DAG
)
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"::LowerOperation_VVP"
;
Op
->
print
(
dbgs
(
)
)
;
)
;
if
(
ISD
::
isVPOpcode
(
Opcode
)
)
return
lowerToVVP
(
Op
,
DAG
)
;
switch
(
Opcode
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
VEISD
::
VEC_BROADCAST
:
if
(
getAnnotatedNodeAVL
(
Op
)
.
second
)
return
Op
;
return
legalizeInternalVectorOp
(
Op
,
DAG
)
;
case
ISD
::
MLOAD
:
case
ISD
::
MSTORE
:
if
(
isMaskArithmetic
(
Op
)
&&
isPackedVectorType
(
Op
.
getValueType
(
)
)
)
return
splitMaskArithmetic
(
Op
,
DAG
)
;
return
lowerToVVP
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> unsigned getReg ( unsigned RC , unsigned RegNo ) const { return * ( RegInfo -> getRegClass ( RC ) . begin ( ) + RegNo ) ; } </s>

Returns the register associated with this edge .


<s> bool isImm ( ) const { return Kind == Immediate ; } </s>


<s> bool SystemZRegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator SaveMBBI , MachineBasicBlock :: iterator & UseMBBI , const TargetRegisterClass * RC , unsigned Reg ) const { MachineFunction & MF = * MBB . getParent ( ) ; const SystemZFrameLowering * TFI = static_cast < const SystemZFrameLowering * > ( TM . getFrameLowering ( ) ) ; unsigned Base = getFrameRegister ( MF ) ; uint64_t Offset = TFI -> getEmergencySpillSlotOffset ( MF ) ; DebugLoc DL ; unsigned LoadOpcode , StoreOpcode ; TII . getLoadStoreOpcodes ( RC , LoadOpcode , StoreOpcode ) ; BuildMI ( MBB , SaveMBBI , DL , TII . get ( StoreOpcode ) ) . addReg ( Reg , RegState :: Kill ) . addReg ( Base ) . addImm ( Offset ) . addReg ( 0 ) ; BuildMI ( MBB , UseMBBI , DL , TII . get ( LoadOpcode ) , Reg ) . addReg ( Base ) . addImm ( Offset ) . addReg ( 0 ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .


<s> bool X86FastISel :: isTypeLegal ( const Type * Ty , MVT & VT , bool AllowI1 ) { VT = TLI . getValueType ( Ty , true ) ; if ( VT == MVT :: Other || ! VT . isSimple ( ) ) return false ; if ( VT == MVT :: f64 && ! X86ScalarSSEf64 ) return false ; if ( VT == MVT :: f32 && ! X86ScalarSSEf32 ) return false ; if ( VT == MVT :: f80 ) return false ; return ( AllowI1 && VT == MVT :: i1 ) || TLI . isTypeLegal ( VT ) ; } </s>


<s> static bool aarch64_reads_global_state_p ( aarch64_simd_builtin_datum * d ) { unsigned int flags = aarch64_call_properties ( d ) ; if ( flags & FLAG_READ_FPCR ) return true ; return flags & FLAG_READ_MEMORY ; } </s>

Return true if calls to the function could read some form of global state .


<s> bool RISCVTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { if ( VT == MVT :: f16 && ! Subtarget . hasStdExtZfhmin ( ) ) return false ; if ( VT == MVT :: f32 && ! Subtarget . hasStdExtF ( ) ) return false ; if ( VT == MVT :: f64 && ! Subtarget . hasStdExtD ( ) ) return false ; if ( Imm . isNegZero ( ) ) return false ; return Imm . isZero ( ) ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesAll ( ) ; if ( Subtarget -> isTargetDarwin ( ) || Subtarget -> isTargetELF ( ) || Subtarget -> isTargetCygMing ( ) ) { AU . addRequired < MachineModuleInfo > ( ) ; } AU . addRequired < DwarfWriter > ( ) ; AsmPrinter :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> int VEFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) ; FrameReg = VE :: SX11 ; return FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> static void nvptx_print_address_operand ( FILE * file , rtx x , machine_mode ) { rtx off ; if ( GET_CODE ( x ) == CONST ) x = XEXP ( x , 0 ) ; switch ( GET_CODE ( x ) ) { case PLUS : off = XEXP ( x , 1 ) ; output_address ( VOIDmode , XEXP ( x , 0 ) ) ; fprintf ( file , "+" ) ; output_address ( VOIDmode , off ) ; break ; case SYMBOL_REF : case LABEL_REF : output_addr_const ( file , x ) ; break ; default : gcc_assert ( GET_CODE ( x ) != MEM ) ; nvptx_print_operand ( file , x , 0 ) ; break ; } } </s>

Subroutine of nvptx_print_operand ; used to print a memory reference X to FILE .


<s> static bool frv_legitimate_constant_p ( machine_mode mode , rtx x ) { if ( TARGET_FDPIC ) return LEGITIMATE_PIC_OPERAND_P ( x ) ; if ( GET_CODE ( x ) != CONST_DOUBLE ) return TRUE ; if ( GET_MODE ( x ) == VOIDmode || mode == DImode ) return TRUE ; if ( x == CONST0_RTX ( mode ) ) return TRUE ; if ( ! TARGET_HAS_FPRS ) return TRUE ; if ( mode == DFmode && ! TARGET_DOUBLE ) return TRUE ; return FALSE ; } </s>

A C expression that is nonzero if X is a legitimate constant for an immediate operand on the target machine . You can assume that X satisfies ` CONSTANT_P ' , so you need not check this . In fact , ` 1 ' is a suitable definition for this macro on machines where anything ` CONSTANT_P ' is valid .


<s> TargetLowering :: AtomicExpansionKind PPCTargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { unsigned Size = AI -> getNewValOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( shouldInlineQuadwordAtomics ( ) && Size == 128 ) return AtomicExpansionKind :: MaskedIntrinsic ; return TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AI ) ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> void MipsFrameInfo :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = prior ( MBB . end ( ) ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; const MipsInstrInfo & TII = * static_cast < const MipsInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; int FPOffset = MipsFI -> getFPStackOffset ( ) ; int RAOffset = MipsFI -> getRAStackOffset ( ) ; if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDu ) , Mips :: SP ) . addReg ( Mips :: FP ) . addReg ( Mips :: ZERO ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: LW ) , Mips :: FP ) . addImm ( FPOffset ) . addReg ( Mips :: SP ) ; } if ( MFI -> adjustsStack ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: LW ) , Mips :: RA ) . addImm ( RAOffset ) . addReg ( Mips :: SP ) ; } if ( NumBytes ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDiu ) , Mips :: SP ) . addReg ( Mips :: SP ) . addImm ( NumBytes ) ; } } </s>

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips::ADDu Mips::SP Mips::FP Mips::ZERO Mips::LW Mips::FP Mips::SP Mips::LW Mips::RA Mips::SP Mips::ADDiu Mips::SP Mips::SP


<s> unsigned R600MCCodeEmitter :: getHWRegChan ( unsigned reg ) const { return MRI . getEncodingValue ( reg ) >> HW_CHAN_SHIFT ; } </s>

get the HW encoding for a register 's channel .


<s> int alpha_split_conditional_move ( enum rtx_code code , rtx dest , rtx cond , rtx t_rtx , rtx f_rtx ) { HOST_WIDE_INT t , f , diff ; machine_mode mode ; rtx target , subtarget , tmp ; mode = GET_MODE ( dest ) ; t = INTVAL ( t_rtx ) ; f = INTVAL ( f_rtx ) ; diff = t - f ; if ( ( ( code == NE || code == EQ ) && diff < 0 ) || ( code == GE || code == GT ) ) { code = reverse_condition ( code ) ; diff = t , t = f , f = diff ; diff = t - f ; } subtarget = target = dest ; if ( mode != DImode ) { target = gen_lowpart ( DImode , dest ) ; if ( can_create_pseudo_p ( ) ) subtarget = gen_reg_rtx ( DImode ) ; else subtarget = target ; } if ( f == 0 && exact_log2 ( diff ) > 0 && ( diff <= 8 || alpha_tune == PROCESSOR_EV6 ) ) { tmp = gen_rtx_fmt_ee ( code , DImode , cond , const0_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , copy_rtx ( subtarget ) , tmp ) ) ; tmp = gen_rtx_ASHIFT ( DImode , copy_rtx ( subtarget ) , GEN_INT ( exact_log2 ( t ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , tmp ) ) ; } else if ( f == 0 && t == - 1 ) { tmp = gen_rtx_fmt_ee ( code , DImode , cond , const0_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , copy_rtx ( subtarget ) , tmp ) ) ; emit_insn ( gen_negdi2 ( target , copy_rtx ( subtarget ) ) ) ; } else if ( diff == 1 || diff == 4 || diff == 8 ) { rtx add_op ; tmp = gen_rtx_fmt_ee ( code , DImode , cond , const0_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , copy_rtx ( subtarget ) , tmp ) ) ; if ( diff == 1 ) emit_insn ( gen_adddi3 ( target , copy_rtx ( subtarget ) , GEN_INT ( f ) ) ) ; else { add_op = GEN_INT ( f ) ; if ( sext_add_operand ( add_op , mode ) ) { tmp = gen_rtx_MULT ( DImode , copy_rtx ( subtarget ) , GEN_INT ( diff ) ) ; tmp = gen_rtx_PLUS ( DImode , tmp , add_op ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , tmp ) ) ; } else return 0 ; } } else return 0 ; return 1 ; } </s>

Simplify a conditional move of two constants into a setcc with arithmetic . This is done with a splitter since combine would just undo the work if done during code generation . It also catches cases we would n't have before cse .


<s> void X86PassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( new X86ExecutionDomainFix ( ) ) ; addPass ( createBreakFalseDeps ( ) ) ; } addPass ( createShadowCallStackPass ( ) ) ; addPass ( createX86IndirectBranchTrackingPass ( ) ) ; if ( UseVZeroUpper ) addPass ( createX86IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86FixupBWInsts ( ) ) ; addPass ( createX86PadShortFunctions ( ) ) ; addPass ( createX86FixupLEAs ( ) ) ; addPass ( createX86EvexToVexInsts ( ) ) ; } addPass ( createX86DiscriminateMemOpsPass ( ) ) ; addPass ( createX86InsertPrefetchPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void WebAssemblyExceptionInfo :: releaseMemory ( ) { BBMap . clear ( ) ; TopLevelExceptions . clear ( ) ; } </s>

releaseMemory ( ) - This member can be implemented by a pass if it wants to be able to release its memory when it is no longer needed .


<s> bool ARMBaseInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned TCycles , unsigned TExtra , MachineBasicBlock & FMBB , unsigned FCycles , unsigned FExtra , const BranchProbability & Probability ) const { if ( ! TCycles || ! FCycles ) return false ; unsigned TUnpredCost = Probability . scale ( TCycles ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FCycles ) ; unsigned UnpredCost = TUnpredCost + FUnpredCost ; UnpredCost += 1 ; UnpredCost += Subtarget . getMispredictionPenalty ( ) / 10 ; return ( TCycles + FCycles + TExtra + FExtra ) <= UnpredCost ; } </s>


<s> static bool avr_move_fixed_operands ( rtx * op , rtx * hreg , unsigned mask ) { for ( ; mask ; mask >>= 1 , op ++ , hreg ++ ) if ( ( mask & 1 ) && * hreg ) emit_move_insn ( * hreg , * op ) ; return true ; } </s>

Helper for the function below : If bit n of MASK is set and HREG [ n ] ! = NULL , then emit a move insn to copy OP [ n ] to HREG [ n ] . Otherwise do nothing for that n. Return TRUE .


<s>
static
void
recombine_lvx_pattern
(
rtx_insn
*
insn
,
del_info
*
to_delete
)
{
rtx
body
=
PATTERN
(
insn
)
;
gcc_assert
(
GET_CODE
(
body
)
==
SET
&&
GET_CODE
(
SET_SRC
(
body
)
)
==
VEC_SELECT
&&
GET_CODE
(
XEXP
(
SET_SRC
(
body
)
,
0
)
)
==
MEM
)
;
rtx
mem
=
XEXP
(
SET_SRC
(
body
)
,
0
)
;
rtx
base_reg
=
XEXP
(
mem
,
0
)
;
rtx_insn
*
and_insn
;
rtx
and_operation
=
find_alignment_op
(
insn
,
base_reg
,
&
and_insn
)
;
if
(
and_operation
!=
0
)
{
df_ref
def
;
struct
df_insn_info
*
insn_info
=
DF_INSN_INFO_GET
(
insn
)
;
FOR_EACH_INSN_INFO_DEF
(
def
,
insn_info
)
{
struct
df_link
*
link
=
DF_REF_CHAIN
(
def
)
;
if
(
!
link
||
link
->
next
)
break
;
rtx_insn
*
swap_insn
=
DF_REF_INSN
(
link
->
ref
)
;
if
(
!
insn_is_swap_p
(
swap_insn
)
||
insn_is_load_p
(
swap_insn
)
||
insn_is_store_p
(
swap_insn
)
)
break
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace
=
true
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace_insn
=
swap_insn
;
rtx
and_base
=
XEXP
(
and_operation
,
0
)
;
rtx
new_reg
=
gen_reg_rtx
(
GET_MODE
(
and_base
)
)
;
rtx
copy
=
gen_rtx_SET
(
new_reg
,
and_base
)
;
rtx_insn
*
new_insn
=
emit_insn_after
(
copy
,
and_insn
)
;
set_block_for_insn
(
new_insn
,
BLOCK_FOR_INSN
(
and_insn
)
)
;
df_insn_rescan
(
new_insn
)
;
XEXP
(
mem
,
0
)
=
gen_rtx_AND
(
GET_MODE
(
and_base
)
,
new_reg
,
XEXP
(
and_operation
,
1
)
)
;
SET_SRC
(
body
)
=
mem
;
INSN_CODE
(
insn
)
=
1
;
df_insn_rescan
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"lvx opportunity found at %d\n"
,
INSN_UID
(
insn
)
)
;
}
}
}
</s>

If INSN is the load for an lvx pattern , put it in canonical form .


<s> static void arc_finalize_pic ( void ) { rtx pat ; rtx baseptr_rtx = gen_rtx_REG ( Pmode , PIC_OFFSET_TABLE_REGNUM ) ; if ( crtl -> uses_pic_offset_table == 0 ) return ; gcc_assert ( flag_pic != 0 ) ; pat = gen_rtx_SYMBOL_REF ( Pmode , "_DYNAMIC" ) ; pat = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , pat ) , ARC_UNSPEC_GOT ) ; pat = gen_rtx_CONST ( Pmode , pat ) ; pat = gen_rtx_SET ( baseptr_rtx , pat ) ; emit_insn ( pat ) ; } </s>

If the function has any GOTOFF relocations , then the GOTBASE register has to be setup in the prologue The instruction needed at the function start for setting up the GOTBASE register is add rdest , pc , -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The rtl to be emitted for this should be : set ( reg basereg ) ( plus ( reg pc ) ( const ( unspec ( symref _DYNAMIC ) 3 ) ) ) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --


<s> unsigned getMaxNumElements ( ElementCount VF , const Function * F = nullptr ) const { if ( ! VF . isScalable ( ) ) return VF . getFixedValue ( ) ; unsigned MaxNumVScale = 16 ; if ( F && F -> hasFnAttribute ( Attribute :: VScaleRange ) ) { unsigned VScaleMax = F -> getFnAttribute ( Attribute :: VScaleRange ) . getVScaleRangeArgs ( ) . second ; if ( VScaleMax > 0 ) MaxNumVScale = VScaleMax ; } return MaxNumVScale * VF . getKnownMinValue ( ) ; } </s>

Try to return an estimate cost factor that can be used as a multiplier when scalarizing an operation for a vector with ElementCount VF .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < MachinePostDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> bool sh_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_FPU_ANY && ( ( mode == V2SFmode ) || ( mode == V4SFmode ) || ( mode == V16SFmode ) ) ) return true ; else if ( TARGET_SHMEDIA && ( ( mode == V8QImode ) || ( mode == V2HImode ) || ( mode == V4HImode ) || ( mode == V2SImode ) ) ) return true ; return false ; } </s>

Implements target hook vector_mode_supported_p .


<s> void setFlags ( uint16_t F ) { setAttrs ( NodeAttrs :: set_flags ( getAttrs ( ) , F ) ) ; } </s>


<s> AtomicExpansionKind shouldCastAtomicStoreInIR ( StoreInst * SI ) const override { return AtomicExpansionKind :: None ; } </s>

Returns how the given ( atomic ) store should be cast by the IR-level AtomicExpand pass into .


For stack frames that ca n't be allocated with a single ADDI instruction , compute the best value to initially allocate . It must at a minimum allocate enough space to spill the callee-saved registers .


<s> static bool alpha_cannot_force_const_mem ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { enum rtx_code code = GET_CODE ( x ) ; return code == SYMBOL_REF || code == LABEL_REF || code == CONST ; } </s>

Primarily this is required for TLS symbols , but given that our move patterns * ought * to be able to handle any symbol at any time , we should never be spilling symbolic operands to the constant pool , ever .


<s> bool VEInstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { VECC :: CondCode CC = static_cast < VECC :: CondCode > ( Cond [ 0 ] . getImm ( ) ) ; Cond [ 0 ] . setImm ( GetOppositeBranchCondition ( CC ) ) ; return false ; } </s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> void SparcAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { switch ( MI -> getOpcode ( ) ) { default : break ; case TargetOpcode :: DBG_VALUE : return ; case SP :: GETPCX : LowerGETPCXAndEmitMCInsts ( MI , getSubtargetInfo ( ) ) ; return ; } MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { MCInst TmpInst ; LowerSparcMachineInstrToMCInst ( I , TmpInst , * this ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } while ( ( ++ I != E ) && I -> isInsideBundle ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool M68kAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { if ( Count % 2 != 0 ) return false ; uint64_t NumNops = Count / 2 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) { OS << "\x4E\x71" ; } return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> static int ia64_function_arg_words ( const_tree type , machine_mode mode ) { int words ; if ( mode == BLKmode ) words = int_size_in_bytes ( type ) ; else words = GET_MODE_SIZE ( mode ) ; return ( words + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } </s>

Return the number of words required to hold a quantity of TYPE and MODE when passed as an argument .


<s> unsigned AArch64RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? AArch64 :: FP : AArch64 :: SP ; } </s>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { ForCodeSize = MF . getFunction ( ) . hasOptSize ( ) ; Subtarget = & MF . getSubtarget < AArch64Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> void aarch64_expand_vec_perm ( rtx target , rtx op0 , rtx op1 , rtx sel , unsigned int nelt ) { machine_mode vmode = GET_MODE ( target ) ; bool one_vector_p = rtx_equal_p ( op0 , op1 ) ; rtx mask ; mask = aarch64_simd_gen_const_vector_dup ( vmode , one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; sel = expand_simple_binop ( vmode , AND , sel , mask , NULL , 0 , OPTAB_LIB_WIDEN ) ; if ( BYTES_BIG_ENDIAN ) { if ( ! one_vector_p ) mask = aarch64_simd_gen_const_vector_dup ( vmode , nelt - 1 ) ; sel = expand_simple_binop ( vmode , XOR , sel , mask , NULL , 0 , OPTAB_LIB_WIDEN ) ; } aarch64_expand_vec_perm_1 ( target , op0 , op1 , sel ) ; } </s>

Expand a vec_perm with the operands given by TARGET , OP0 , OP1 and SEL . NELT is the number of elements in the vector .


<s> static rtx ia64_function_arg ( cumulative_args_t cum , const function_arg_info & arg ) { return ia64_function_arg_1 ( cum , arg , false ) ; } </s>

Implement TARGET_FUNCION_ARG target hook .


<s>
SDValue
XCoreTargetLowering
::
LowerCall
(
SDValue
Chain
,
SDValue
Callee
,
unsigned
CallConv
,
bool
isVarArg
,
bool
isTailCall
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .

XCore
XCore
ISD::OutputArg
ISD::InputArg
"Unsupported calling convention"


<s> int same_cmp_preceding_p ( rtx_insn * i3 ) { rtx_insn * i1 , * i2 ; i2 = prev_nonnote_insn ( i3 ) ; if ( i2 == NULL ) return 0 ; i1 = prev_nonnote_insn ( i2 ) ; if ( i1 == NULL ) return 0 ; return ( INSN_P ( i1 ) && rtx_equal_p ( PATTERN ( i1 ) , PATTERN ( i3 ) ) && any_condjump_p ( i2 ) && onlyjump_p ( i2 ) ) ; } </s>

Return nonzero if we have the same comparison insn as I3 two insns before I3 . I3 is assumed to be a comparison insn .


<s> unsigned getFramePred ( const MachineInstr & MI ) const { assert ( isFrameInstr ( MI ) ) ; return MI . getOperand ( 3 ) . getReg ( ) ; } </s>

Returns predicate register associated with the given frame instruction .


<s> static void aarch64_save_callee_saves ( machine_mode mode , poly_int64 start_offset , unsigned start , unsigned limit , bool skip_wb ) { rtx_insn * insn ; unsigned regno ; unsigned regno2 ; for ( regno = aarch64_next_callee_save ( start , limit ) ; regno <= limit ; regno = aarch64_next_callee_save ( regno + 1 , limit ) ) { rtx reg , mem ; poly_int64 offset ; int offset_diff ; if ( skip_wb && ( regno == cfun -> machine -> frame . wb_candidate1 || regno == cfun -> machine -> frame . wb_candidate2 ) ) continue ; if ( cfun -> machine -> reg_is_wrapped_separately [ regno ] ) continue ; reg = gen_rtx_REG ( mode , regno ) ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno ] ; mem = gen_frame_mem ( mode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; regno2 = aarch64_next_callee_save ( regno + 1 , limit ) ; offset_diff = cfun -> machine -> frame . reg_offset [ regno2 ] - cfun -> machine -> frame . reg_offset [ regno ] ; if ( regno2 <= limit && ! cfun -> machine -> reg_is_wrapped_separately [ regno2 ] && known_eq ( GET_MODE_SIZE ( mode ) , offset_diff ) ) { rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; rtx mem2 ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno2 ] ; mem2 = gen_frame_mem ( mode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; insn = emit_insn ( aarch64_gen_store_pair ( mode , mem , reg , mem2 , reg2 ) ) ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , 0 , 1 ) ) = 1 ; regno = regno2 ; } else insn = emit_move_insn ( mem , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } </s>

Emit code to save the callee-saved registers from register number START to LIMIT to the stack at the location starting at offset START_OFFSET , skipping any write-back candidates if SKIP_WB is true .


<s>
SDValue
MSP430TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
SHL
:
case
ISD
::
SRL
:
case
ISD
::
SRA
:
return
LowerShifts
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ExternalSymbol
:
return
LowerExternalSymbol
(
Op
,
DAG
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SIGN_EXTEND
:
return
LowerSIGN_EXTEND
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

MSP430
MSP430
ISD::SHL
ISD::SRL
ISD::SRA
ISD::GlobalAddress
ISD::BlockAddress
ISD::ExternalSymbol
ISD::SETCC
ISD::BR_CC
ISD::SELECT_CC
ISD::SIGN_EXTEND
ISD::RETURNADDR
ISD::FRAMEADDR
ISD::VASTART
"unimplemented operand"


<s> void HexagonDAGToDAGISel :: PreprocessISelDAG ( ) { SelectionDAG & DAG = * CurDAG ; std :: vector < SDNode * > Nodes ; for ( SDNode & Node : DAG . allnodes ( ) ) Nodes . push_back ( & Node ) ; for ( auto I : Nodes ) { if ( I -> getOpcode ( ) != ISD :: OR ) continue ; auto IsZero = [ ] ( const SDValue & V ) -> bool { if ( ConstantSDNode * SC = dyn_cast < ConstantSDNode > ( V . getNode ( ) ) ) return SC -> isNullValue ( ) ; return false ; } ; auto IsSelect0 = [ IsZero ] ( const SDValue & Op ) -> bool { if ( Op . getOpcode ( ) != ISD :: SELECT ) return false ; return IsZero ( Op . getOperand ( 1 ) ) || IsZero ( Op . getOperand ( 2 ) ) ; } ; SDValue N0 = I -> getOperand ( 0 ) , N1 = I -> getOperand ( 1 ) ; EVT VT = I -> getValueType ( 0 ) ; bool SelN0 = IsSelect0 ( N0 ) ; SDValue SOp = SelN0 ? N0 : N1 ; SDValue VOp = SelN0 ? N1 : N0 ; if ( SOp . getOpcode ( ) == ISD :: SELECT && SOp . getNode ( ) -> hasOneUse ( ) ) { SDValue SC = SOp . getOperand ( 0 ) ; SDValue SX = SOp . getOperand ( 1 ) ; SDValue SY = SOp . getOperand ( 2 ) ; SDLoc DLS = SOp ; if ( IsZero ( SY ) ) { SDValue NewOr = DAG . getNode ( ISD :: OR , DLS , VT , SX , VOp ) ; SDValue NewSel = DAG . getNode ( ISD :: SELECT , DLS , VT , SC , NewOr , VOp ) ; DAG . ReplaceAllUsesWith ( I , NewSel . getNode ( ) ) ; } else if ( IsZero ( SX ) ) { SDValue NewOr = DAG . getNode ( ISD :: OR , DLS , VT , SY , VOp ) ; SDValue NewSel = DAG . getNode ( ISD :: SELECT , DLS , VT , SC , VOp , NewOr ) ; DAG . ReplaceAllUsesWith ( I , NewSel . getNode ( ) ) ; } } } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> static int arm_adjust_cost ( rtx insn , rtx link , rtx dep , int cost ) { rtx i_pat , d_pat ; if ( arm_tune_xscale && REG_NOTE_KIND ( link ) == 0 && recog_memoized ( insn ) >= 0 && recog_memoized ( dep ) >= 0 ) { int shift_opnum = get_attr_shift ( insn ) ; enum attr_type attr_type = get_attr_type ( dep ) ; if ( shift_opnum != 0 && ( attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG ) ) { rtx shifted_operand ; int opno ; extract_insn ( insn ) ; shifted_operand = recog_data . operand [ shift_opnum ] ; extract_insn ( dep ) ; preprocess_constraints ( ) ; for ( opno = 0 ; opno < recog_data . n_operands ; opno ++ ) { if ( recog_data . operand_type [ opno ] == OP_IN ) continue ; if ( reg_overlap_mentioned_p ( recog_data . operand [ opno ] , shifted_operand ) ) return 2 ; } } } if ( REG_NOTE_KIND ( link ) == REG_DEP_ANTI || REG_NOTE_KIND ( link ) == REG_DEP_OUTPUT ) return 0 ; if ( REG_NOTE_KIND ( link ) == 0 && GET_CODE ( insn ) == CALL_INSN ) return 1 ; if ( ( i_pat = single_set ( insn ) ) != NULL && GET_CODE ( SET_SRC ( i_pat ) ) == MEM && ( d_pat = single_set ( dep ) ) != NULL && GET_CODE ( SET_DEST ( d_pat ) ) == MEM ) { rtx src_mem = XEXP ( SET_SRC ( i_pat ) , 0 ) ; if ( ( GET_CODE ( src_mem ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( src_mem ) ) || reg_mentioned_p ( stack_pointer_rtx , src_mem ) || reg_mentioned_p ( frame_pointer_rtx , src_mem ) || reg_mentioned_p ( hard_frame_pointer_rtx , src_mem ) ) return 1 ; } return cost ; } </s>

This function implements the target macro TARGET_SCHED_ADJUST_COST . It corrects the value of COST based on the relationship between INSN and DEP through the dependence LINK . It returns the new value . There is a per-core adjust_cost hook to adjust scheduler costs and the per-core hook can choose to completely override the generic adjust_cost function . Only put bits of code into arm_adjust_cost that are common across all cores .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
if
(
Kind
>=
FirstTargetFixupKind
)
assert
(
"Invalid kind!"
)
;
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
}
</s>


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s>
const
char
*
MipsAsmPrinter
::
getCurrentABIString
(
)
const
{
switch
(
static_cast
<
MipsTargetMachine
&
>
(
TM
)
.
getABI
(
)
.
GetEnumValue
(
)
)
{
case
MipsABIInfo
::
ABI
::
O32
:
return
"abi32"
;
case
MipsABIInfo
::
ABI
::
N32
:
return
"abiN32"
;
case
MipsABIInfo
::
ABI
::
N64
:
return
"abi64"
;
case
MipsABIInfo
::
ABI
::
EABI
:
return
"eabi32"
;
default
:
llvm_unreachable
(
"Unknown Mips ABI"
)
;
}
}
</s>

Mips
Mips
Mips
Mips
"abi32"
Mips
"abiN32"
Mips
"abi64"
Mips
"eabi32"
"Unknown Mips ABI"


<s> unsigned getNumFixupKinds ( ) const { return 4 ; } </s>

Get the number of target specific fixup kinds .


<s> static int ix86_nsaved_regs ( void ) { int nregs = 0 ; int regno ; for ( regno = FIRST_PSEUDO_REGISTER - 1 ; regno >= 0 ; regno -- ) if ( ix86_save_reg ( regno , true ) ) nregs ++ ; return nregs ; } </s>

Return number of registers to be saved on the stack .


<s> int PPCTTIImpl :: getIntImmCost ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) { if ( DisablePPCConstHoist ) return BaseT :: getIntImmCost ( Opcode , Idx , Imm , Ty ) ; assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return ~ 0U ; unsigned ImmIdx = ~ 0U ; bool ShiftedFree = false , RunFree = false , UnsignedFree = false , ZeroFree = false ; switch ( Opcode ) { default : return TTI :: TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: And : RunFree = true ; case Instruction :: Add : case Instruction :: Or : case Instruction :: Xor : ShiftedFree = true ; case Instruction :: Sub : case Instruction :: Mul : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : ImmIdx = 1 ; break ; case Instruction :: ICmp : UnsignedFree = true ; ImmIdx = 1 ; case Instruction :: Select : ZeroFree = true ; break ; case Instruction :: PHI : case Instruction :: Call : case Instruction :: Ret : case Instruction :: Load : case Instruction :: Store : break ; } if ( ZeroFree && Imm == 0 ) return TTI :: TCC_Free ; if ( Idx == ImmIdx && Imm . getBitWidth ( ) <= 64 ) { if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; if ( RunFree ) { if ( Imm . getBitWidth ( ) <= 32 && ( isShiftedMask_32 ( Imm . getZExtValue ( ) ) || isShiftedMask_32 ( ~ Imm . getZExtValue ( ) ) ) ) return TTI :: TCC_Free ; if ( ST -> isPPC64 ( ) && ( isShiftedMask_64 ( Imm . getZExtValue ( ) ) || isShiftedMask_64 ( ~ Imm . getZExtValue ( ) ) ) ) return TTI :: TCC_Free ; } if ( UnsignedFree && isUInt < 16 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( ShiftedFree && ( Imm . getZExtValue ( ) & 0xFFFF ) == 0 ) return TTI :: TCC_Free ; } return PPCTTIImpl :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> unsigned X86TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i1 && Subtarget . hasAVX512 ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; MVT RegisterVT ; unsigned NumRegisters ; std :: tie ( RegisterVT , NumRegisters ) = handleMaskRegisterForCallingConv ( NumElts , CC , Subtarget ) ; if ( RegisterVT != MVT :: INVALID_SIMPLE_VALUE_TYPE ) return NumRegisters ; } return TargetLowering :: getNumRegistersForCallingConv ( Context , CC , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s> static bool aarch64_can_inline_p ( tree caller , tree callee ) { tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET ( caller ) ; tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET ( callee ) ; if ( ! callee_tree ) return true ; struct cl_target_option * caller_opts = TREE_TARGET_OPTION ( caller_tree ? caller_tree : target_option_default_node ) ; struct cl_target_option * callee_opts = TREE_TARGET_OPTION ( callee_tree ) ; if ( ( caller_opts -> x_aarch64_isa_flags & callee_opts -> x_aarch64_isa_flags ) != callee_opts -> x_aarch64_isa_flags ) return false ; if ( ( TARGET_STRICT_ALIGN_P ( caller_opts -> x_target_flags ) != TARGET_STRICT_ALIGN_P ( callee_opts -> x_target_flags ) ) && ! ( ! TARGET_STRICT_ALIGN_P ( callee_opts -> x_target_flags ) && TARGET_STRICT_ALIGN_P ( caller_opts -> x_target_flags ) ) ) return false ; bool always_inline = lookup_attribute ( "always_inline" , DECL_ATTRIBUTES ( callee ) ) ; if ( always_inline ) return true ; if ( caller_opts -> x_aarch64_cmodel_var != callee_opts -> x_aarch64_cmodel_var ) return false ; if ( caller_opts -> x_aarch64_tls_dialect != callee_opts -> x_aarch64_tls_dialect ) return false ; if ( ! aarch64_tribools_ok_for_inlining_p ( caller_opts -> x_aarch64_fix_a53_err835769 , callee_opts -> x_aarch64_fix_a53_err835769 , 2 , TARGET_FIX_ERR_A53_835769_DEFAULT ) ) return false ; if ( ! aarch64_tribools_ok_for_inlining_p ( caller_opts -> x_aarch64_fix_a53_err843419 , callee_opts -> x_aarch64_fix_a53_err843419 , 2 , TARGET_FIX_ERR_A53_843419 ) ) return false ; if ( ! aarch64_tribools_ok_for_inlining_p ( caller_opts -> x_flag_omit_leaf_frame_pointer , callee_opts -> x_flag_omit_leaf_frame_pointer , 2 , 1 ) ) return false ; if ( callee_opts -> x_aarch64_override_tune_string != NULL && caller_opts -> x_aarch64_override_tune_string == NULL ) return false ; if ( callee_opts -> x_aarch64_override_tune_string && caller_opts -> x_aarch64_override_tune_string && ( strcmp ( callee_opts -> x_aarch64_override_tune_string , caller_opts -> x_aarch64_override_tune_string ) != 0 ) ) return false ; return true ; } </s>

Implement TARGET_CAN_INLINE_P . Decide whether it is valid to inline CALLEE into CALLER based on target-specific info . Make sure that the caller and callee have compatible architectural features . Then go through the other possible target attributes and see if they can block inlining . Try not to reject always_inline callees unless they are incompatible architecturally .


<s> Register WebAssemblyRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const auto & MFI = MF . getInfo < WebAssemblyFunctionInfo > ( ) ; if ( MFI -> isFrameBaseVirtual ( ) ) return MFI -> getFrameBaseVreg ( ) ; static const unsigned Regs [ 2 ] [ 2 ] = { { WebAssembly :: SP32 , WebAssembly :: SP64 } , { WebAssembly :: FP32 , WebAssembly :: FP64 } } ; const WebAssemblyFrameLowering * TFI = getFrameLowering ( MF ) ; return Regs [ TFI -> hasFP ( MF ) ] [ TT . isArch64Bit ( ) ] ; } </s>


<s> static NodeRef getEntryNode ( const agraph & G ) { return G . Blocks . front ( ) ; } </s>

Return the token chain corresponding to the entry of the function .


<s> int c4x_label_conflict ( rtx insn , rtx jump , rtx db ) { while ( insn ) { if ( GET_CODE ( insn ) == CODE_LABEL ) { if ( CODE_LABEL_NUMBER ( jump ) == CODE_LABEL_NUMBER ( insn ) ) return 1 ; if ( CODE_LABEL_NUMBER ( db ) == CODE_LABEL_NUMBER ( insn ) ) return 0 ; } insn = PREV_INSN ( insn ) ; } return 1 ; } </s>

Check for while loop inside a decrement and branch loop .


<s> static const char * ix86_mangle_type ( const_tree type ) { type = TYPE_MAIN_VARIANT ( type ) ; if ( TREE_CODE ( type ) != VOID_TYPE && TREE_CODE ( type ) != BOOLEAN_TYPE && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE ) return NULL ; switch ( TYPE_MODE ( type ) ) { case TFmode : return "g" ; case XFmode : return "e" ; default : return NULL ; } } </s>

Return the mangling of TYPE if it is an extended fundamental type .


"SIInstrInfo::storeRegToStackSlot - Do not know how to"

Store the specified register of the given register class to the specified stack frame index .


<s> static int ia64_issue_rate ( void ) { return 6 ; } </s>

Return the maximum number of instructions a cpu can issue .


<s> bool mem_operand_gpr ( rtx op , machine_mode mode ) { unsigned HOST_WIDE_INT offset ; int extra ; rtx addr = XEXP ( op , 0 ) ; op = address_offset ( addr ) ; if ( op == NULL_RTX ) return true ; offset = INTVAL ( op ) ; if ( TARGET_POWERPC64 && ( offset & 3 ) != 0 ) return false ; extra = GET_MODE_SIZE ( mode ) - UNITS_PER_WORD ; if ( extra < 0 ) extra = 0 ; if ( GET_CODE ( addr ) == LO_SUM ) offset = ( ( offset & 0xffff ) ^ 0x8000 ) - 0x8000 ; return offset + 0x8000 < 0x10000u - extra ; } </s>

Return true if the MEM operand is a memory operand suitable for use with a ( full width , possibly multiple ) gpr load/store . On powerpc64 this means the offset must be divisible by 4 . Implements ' Y ' constraint . Accept direct , indexed , offset , lo_sum and tocref . Since this is a constraint function we know the operand has satisfied a suitable memory predicate . Offsetting a lo_sum should not be allowed , except where we know by alignment that a 32k boundary is not crossed . Note that by `` offsetting '' here we mean a further offset to access parts of the MEM . It 's fine to have a lo_sum where the inner address is offset from a sym , since the same sym+offset will appear in the high part of the address calculation .


<s> static void do_link ( rtx spreg , HOST_WIDE_INT frame_size , bool all ) { frame_size += arg_area_size ( ) ; if ( all || stack_frame_needed_p ( ) || ( must_save_rets_p ( ) && must_save_fp_p ( ) ) ) emit_link_insn ( spreg , frame_size ) ; else { if ( must_save_rets_p ( ) ) { rtx pat = gen_movsi ( gen_rtx_MEM ( Pmode , gen_rtx_PRE_DEC ( Pmode , spreg ) ) , bfin_rets_rtx ) ; rtx_insn * insn = emit_insn ( pat ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } if ( must_save_fp_p ( ) ) { rtx pat = gen_movsi ( gen_rtx_MEM ( Pmode , gen_rtx_PRE_DEC ( Pmode , spreg ) ) , gen_rtx_REG ( Pmode , REG_FP ) ) ; rtx_insn * insn = emit_insn ( pat ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } add_to_reg ( spreg , - frame_size , 1 , 0 ) ; } } </s>

Save RETS and FP , and allocate a stack frame . ALL is true if the function must save all its registers ( true only for certain interrupt handlers ) .


"LowerFormalArguments Unhandled argument type: "

"functions with VarArgs or StructRet are not supported"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s>
int
frv_initial_elimination_offset
(
int
from
,
int
to
)
{
frv_stack_t
*
info
=
frv_stack_info
(
)
;
int
ret
=
0
;
if
(
to
==
STACK_POINTER_REGNUM
&&
from
==
ARG_POINTER_REGNUM
)
ret
=
info
->
total_size
info
->
pretend_size
;
else
if
(
to
==
STACK_POINTER_REGNUM
&&
from
==
FRAME_POINTER_REGNUM
)
ret
=
info
->
reg_offset
[
FRAME_POINTER_REGNUM
]
;
else
if
(
to
==
FRAME_POINTER_REGNUM
&&
from
==
ARG_POINTER_REGNUM
)
ret
=
(
info
->
total_size
info
->
reg_offset
[
FRAME_POINTER_REGNUM
]
info
->
pretend_size
)
;
else
gcc_unreachable
(
)
;
if
(
TARGET_DEBUG_STACK
)
fprintf
(
stderr
,
"Eliminate %s to %s by adding %d\n"
,
reg_names
[
from
]
,
reg_names
[
to
]
,
ret
)
;
return
ret
;
}
</s>

See frv_stack_info for more details on the frv stack frame .

frv
0
"Eliminate %s to %s by adding %d\n"


<s> static int ix86_save_reg ( unsigned int regno , int maybe_eh_return ) { if ( pic_offset_table_rtx && regno == REAL_PIC_OFFSET_TABLE_REGNUM && ( regs_ever_live [ REAL_PIC_OFFSET_TABLE_REGNUM ] || current_function_profile || current_function_calls_eh_return || current_function_uses_const_pool ) ) { if ( ix86_select_alt_pic_regnum ( ) != INVALID_REGNUM ) return 0 ; return 1 ; } if ( current_function_calls_eh_return && maybe_eh_return ) { unsigned i ; for ( i = 0 ; ; i ++ ) { unsigned test = EH_RETURN_DATA_REGNO ( i ) ; if ( test == INVALID_REGNUM ) break ; if ( test == regno ) return 1 ; } } if ( cfun -> machine -> force_align_arg_pointer && regno == REGNO ( cfun -> machine -> force_align_arg_pointer ) ) return 1 ; return ( regs_ever_live [ regno ] && ! call_used_regs [ regno ] && ! fixed_regs [ regno ] && ( regno != HARD_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) ) ; } </s>


<s> bool ARMTargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const { if ( ! Subtarget -> isThumb ( ) ) return ARM_AM :: getSOImmVal ( llvm :: abs64 ( Imm ) ) != - 1 ; if ( Subtarget -> isThumb2 ( ) ) return ARM_AM :: getT2SOImmVal ( llvm :: abs64 ( Imm ) ) != - 1 ; return Imm >= 0 && Imm <= 255 ; } </s>

Return true if the specified immediate is legal icmp immediate , that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register .


<s> const TargetRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> TargetTransformInfo MOSTargetMachine :: getTargetTransformInfo ( const Function & F ) const { return TargetTransformInfo ( MOSTTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> static int nios2_arg_partial_bytes ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; HOST_WIDE_INT param_size = arg . promoted_size_in_bytes ( ) ; gcc_assert ( param_size >= 0 ) ; param_size = ( UNITS_PER_WORD - 1 + param_size ) / UNITS_PER_WORD ; if ( cum -> regs_used < NUM_ARG_REGS && cum -> regs_used + param_size > NUM_ARG_REGS ) return ( NUM_ARG_REGS - cum -> regs_used ) * UNITS_PER_WORD ; return 0 ; } </s>

Return number of bytes , at the beginning of the argument , that must be put in registers . 0 is the argument is entirely in registers or entirely in memory .


<s> static void undo_split_delayed_nonbranch ( rtx_insn * insn ) { int icode = recog_memoized ( insn ) ; enum attr_type type ; rtx prev_pat , insn_pat ; rtx_insn * prev ; if ( icode < 0 ) return ; type = get_attr_type ( insn ) ; if ( type != TYPE_LOAD_SHADOW && type != TYPE_MULT_SHADOW ) return ; prev = PREV_INSN ( insn ) ; prev_pat = PATTERN ( prev ) ; insn_pat = PATTERN ( insn ) ; if ( GET_CODE ( prev_pat ) == COND_EXEC ) { prev_pat = COND_EXEC_CODE ( prev_pat ) ; insn_pat = COND_EXEC_CODE ( insn_pat ) ; } gcc_assert ( GET_CODE ( prev_pat ) == UNSPEC && ( ( XINT ( prev_pat , 1 ) == UNSPEC_REAL_LOAD && type == TYPE_LOAD_SHADOW ) || ( XINT ( prev_pat , 1 ) == UNSPEC_REAL_MULT && type == TYPE_MULT_SHADOW ) ) ) ; insn_pat = gen_rtx_SET ( VOIDmode , SET_DEST ( insn_pat ) , XVECEXP ( prev_pat , 0 , 1 ) ) ; insn_pat = duplicate_cond ( insn_pat , prev ) ; PATTERN ( insn ) = insn_pat ; INSN_CODE ( insn ) = - 1 ; delete_insn ( prev ) ; } </s>

Examine if INSN is the result of splitting a load into a real load and a shadow , and if so , undo the transformation .


<s> static void mt_set_memflags_1 ( rtx x , int in_struct_p , int volatile_p ) { int i ; switch ( GET_CODE ( x ) ) { case SEQUENCE : case PARALLEL : for ( i = XVECLEN ( x , 0 ) - 1 ; i >= 0 ; i -- ) mt_set_memflags_1 ( XVECEXP ( x , 0 , i ) , in_struct_p , volatile_p ) ; break ; case INSN : mt_set_memflags_1 ( PATTERN ( x ) , in_struct_p , volatile_p ) ; break ; case SET : mt_set_memflags_1 ( SET_DEST ( x ) , in_struct_p , volatile_p ) ; mt_set_memflags_1 ( SET_SRC ( x ) , in_struct_p , volatile_p ) ; break ; case MEM : MEM_IN_STRUCT_P ( x ) = in_struct_p ; MEM_VOLATILE_P ( x ) = volatile_p ; break ; default : break ; } } </s>

Subfunction of the following function . Update the flags of any MEM found in part of X .


<s> bool SystemZExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const SystemZInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; bool Modified = false ; for ( auto & MBB : MF ) Modified |= expandMBB ( MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


"internal error: builtin function %s already processed"

Add a SPARC builtin function with NAME , ICODE , CODE and TYPE . Return the function decl or NULL_TREE if the builtin was not added .


<s> unsigned getNumFixupKinds ( ) const { return 7 ; } </s>

Get the number of target specific fixup kinds .


<s> bool KudeyarTargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const KudeyarSubtarget & Subtarget = TM . getSubtarget < KudeyarSubtarget > ( ) ; if ( Subtarget . isLinux ( ) ) return false ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ; if ( Kind . isMergeable1ByteCString ( ) ) return false ; Type * Ty = GV -> getType ( ) -> getElementType ( ) ; return IsInSmallSection ( TM . getDataLayout ( ) -> getTypeAllocSize ( Ty ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> bool CSKYFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


"Wasn't expecting to be able to lower this!"

LowerOperation - Provide custom lowering hooks for some operations .


"position-independent code requires the Linux ABI"

"PIC support for %<-fstack-limit-symbol%>"

"%<-mgprel-sec=%> not supported with PIC"

"%<-mr0rel-sec=%> not supported with PIC"

"%<-mgprel-sec=%> argument is not a valid regular expression"

"%<-mr0rel-sec=%> argument is not a valid regular expression"

"BMX instructions are only supported with R2 architecture"

"CDX instructions are only supported with R2 architecture"


<s> bool MipsSEDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < MipsSubtarget > ( ) ; if ( Subtarget -> inMips16Mode ( ) ) return false ; return MipsDAGToDAGISel :: runOnMachineFunction ( MF ) ; } </s>


<s> void insertSSPDeclarations ( Module & M ) const override { } </s>

Inserts necessary declarations for SSP ( stack protection ) purpose .


<s>
const
char
*
pa_output_64bit_and
(
rtx
*
operands
)
{
if
(
GET_CODE
(
operands
[
2
]
)
==
CONST_INT
&&
INTVAL
(
operands
[
2
]
)
!=
0
)
{
unsigned
HOST_WIDE_INT
mask
=
INTVAL
(
operands
[
2
]
)
;
int
ls0
,
ls1
,
ms0
,
p
,
len
;
for
(
ls0
=
0
;
ls0
<
HOST_BITS_PER_WIDE_INT
;
ls0
++
)
if
(
(
mask
&
(
(
unsigned
HOST_WIDE_INT
)
1
<<
ls0
)
)
==
0
)
break
;
for
(
ls1
=
ls0
;
ls1
<
HOST_BITS_PER_WIDE_INT
;
ls1
++
)
if
(
(
mask
&
(
(
unsigned
HOST_WIDE_INT
)
1
<<
ls1
)
)
!=
0
)
break
;
for
(
ms0
=
ls1
;
ms0
<
HOST_BITS_PER_WIDE_INT
;
ms0
++
)
if
(
(
mask
&
(
(
unsigned
HOST_WIDE_INT
)
1
<<
ms0
)
)
==
0
)
break
;
gcc_assert
(
ms0
==
HOST_BITS_PER_WIDE_INT
)
;
if
(
ls1
==
HOST_BITS_PER_WIDE_INT
)
{
len
=
ls0
;
gcc_assert
(
len
)
;
operands
[
2
]
=
GEN_INT
(
len
)
;
return
"extrd,u %1,63,%2,%0"
;
}
else
{
p
=
63
ls0
;
len
=
ls1
ls0
;
operands
[
2
]
=
GEN_INT
(
p
)
;
operands
[
3
]
=
GEN_INT
(
len
)
;
return
"depdi 0,%2,%3,%0"
;
}
}
else
return
"and %1,%2,%0"
;
}
</s>

Return a string to perform a bitwise-and of operands [ 1 ] with operands [ 2 ] storing the result in operands [ 0 ] .


<s> void MSP430FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const MSP430InstrInfo & TII = * static_cast < const MSP430InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; unsigned StackAlign = getStackAlignment ( ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; uint64_t Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = 0 ; if ( Old -> getOpcode ( ) == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( MSP430 :: SUB16ri ) , MSP430 :: SPW ) . addReg ( MSP430 :: SPW ) . addImm ( Amount ) ; } else { assert ( Old -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) ; uint64_t CalleeAmt = Old -> getOperand ( 1 ) . getImm ( ) ; Amount -= CalleeAmt ; if ( Amount ) New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( MSP430 :: ADD16ri ) , MSP430 :: SPW ) . addReg ( MSP430 :: SPW ) . addImm ( Amount ) ; } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { MachineInstr * Old = I ; MachineInstr * New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( MSP430 :: SUB16ri ) , MSP430 :: SPW ) . addReg ( MSP430 :: SPW ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> void SparcAsmPrinter :: emitFunctionBodyStart ( ) { if ( ! MF -> getSubtarget < SparcSubtarget > ( ) . is64Bit ( ) ) return ; const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const unsigned globalRegs [ ] = { SP :: G2 , SP :: G3 , SP :: G6 , SP :: G7 , 0 } ; for ( unsigned i = 0 ; globalRegs [ i ] != 0 ; ++ i ) { unsigned reg = globalRegs [ i ] ; if ( MRI . use_empty ( reg ) ) continue ; if ( reg == SP :: G6 || reg == SP :: G7 ) getTargetStreamer ( ) . emitSparcRegisterIgnore ( reg ) ; else getTargetStreamer ( ) . emitSparcRegisterScratch ( reg ) ; } } </s>

Targets can override this to emit stuff before the first basic block in the function .


<s> void XCoreInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) && ! I -> isDebugInstr ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ; BuildMI ( MBB , I , DL , get ( XCore :: STWFI ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) . addMemOperand ( MMO ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool aarch64_legitimate_address_p ( machine_mode mode , rtx x , bool strict_p , aarch64_addr_query_type type ) { struct aarch64_address_info addr ; return aarch64_classify_address ( & addr , x , mode , strict_p , type ) ; } </s>

Return TRUE if X is a legitimate address for accessing memory in mode MODE . OUTER_CODE will be PARALLEL if this is a load/store pair operation .


<s> bool TPCRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { return false ; } </s>

True if the stack can be realigned for the target .


"This eliminateCallFramePseudoInstr does not support Thumb1!"


<s> bool AArch64TargetLowering :: shouldReduceLoadWidth ( SDNode * Load , ISD :: LoadExtType ExtTy , EVT NewVT ) const { if ( ! TargetLoweringBase :: shouldReduceLoadWidth ( Load , ExtTy , NewVT ) ) return false ; if ( ExtTy != ISD :: NON_EXTLOAD ) return true ; MemSDNode * Mem = dyn_cast < MemSDNode > ( Load ) ; assert ( Mem ) ; const SDValue & Base = Mem -> getBasePtr ( ) ; if ( Base . getOpcode ( ) == ISD :: ADD && Base . getOperand ( 1 ) . getOpcode ( ) == ISD :: SHL && Base . getOperand ( 1 ) . hasOneUse ( ) && Base . getOperand ( 1 ) . getOperand ( 1 ) . getOpcode ( ) == ISD :: Constant ) { if ( Mem -> getMemoryVT ( ) . isScalableVector ( ) ) return false ; uint64_t ShiftAmount = Base . getOperand ( 1 ) . getConstantOperandVal ( 1 ) ; uint64_t LoadBytes = Mem -> getMemoryVT ( ) . getSizeInBits ( ) / 8 ; if ( ShiftAmount == Log2_32 ( LoadBytes ) ) return false ; } return true ; } </s>

Return true if we believe it is correct and profitable to reduce the load node to a smaller type .


<s> StringRef ARMInstPrinter :: getOpcodeName ( unsigned Opcode ) const { return getInstructionName ( Opcode ) ; } </s>

Return a string representation for an opcode .


"Module has aliases, which NVPTX does not support."

"Module has a nontrivial global ctor, which NVPTX does not support."

"Module has a nontrivial global dtor, which NVPTX does not support."

Set up the AsmPrinter when we are working on a new module .


<s> void GCNPassConfig :: addOptimizedRegAlloc ( ) { if ( OptExecMaskPreRA ) { insertPass ( & MachineSchedulerID , & SIOptimizeExecMaskingPreRAID ) ; insertPass ( & SIOptimizeExecMaskingPreRAID , & SIFormMemoryClausesID ) ; } else { insertPass ( & MachineSchedulerID , & SIFormMemoryClausesID ) ; } insertPass ( & PHIEliminationID , & SILowerControlFlowID , false ) ; insertPass ( & RegisterCoalescerID , & SIPreAllocateWWMRegsID , false ) ; if ( EnableDCEInRA ) insertPass ( & DetectDeadLanesID , & DeadMachineInstructionElimID ) ; TargetPassConfig :: addOptimizedRegAlloc ( ) ; } </s>

addOptimizedRegAlloc - Add passes related to register allocation .


<s> BufferType :: const_iterator end ( ) const { return Buffer . end ( ) ; } </s>

Get a const_iterator to the end of the symbol table .


<s> const AGCSubtarget * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static void v850_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( ! TARGET_GCC_ABI ) cum -> nbytes += ( ( arg . promoted_size_in_bytes ( ) + UNITS_PER_WORD - 1 ) & - UNITS_PER_WORD ) ; else cum -> nbytes += ( ( ( arg . type && int_size_in_bytes ( arg . type ) > 8 ? GET_MODE_SIZE ( Pmode ) : ( HOST_WIDE_INT ) arg . promoted_size_in_bytes ( ) ) + UNITS_PER_WORD - 1 ) & - UNITS_PER_WORD ) ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> bool HexagonTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( Ty -> isSized ( ) ) { unsigned A = DL . getABITypeAlignment ( Ty ) ; if ( ( AM . BaseOffs % A ) != 0 ) return false ; if ( ! isInt < 11 > ( AM . BaseOffs >> Log2_32 ( A ) ) ) return false ; } if ( AM . BaseGV ) return false ; int Scale = AM . Scale ; if ( Scale < 0 ) Scale = - Scale ; switch ( Scale ) { case 0 : break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> SITargetLowering :: ConstraintType SITargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 's' : case 'v' : case 'a' : return C_RegisterClass ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> bool SITargetLowering :: isReassocProfitable ( SelectionDAG & DAG , SDValue N0 , SDValue N1 ) const { if ( ! N0 . hasOneUse ( ) ) return false ; if ( N0 -> isDivergent ( ) || ! N1 -> isDivergent ( ) ) return true ; return ( DAG . isBaseWithConstantOffset ( N0 ) && hasMemSDNodeUser ( * N0 -> use_begin ( ) ) ) ; } </s>

Control the following reassociation of operands : ( op ( op x , c1 ) , y ) - > ( op ( op x , y ) , c1 ) where N0 is ( op x , c1 ) and N1 is y .


<s> NVPTXTargetLowering :: ConstraintType NVPTXTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'b' : case 'r' : case 'h' : case 'c' : case 'l' : case 'f' : case 'd' : case '0' : case 'N' : return C_RegisterClass ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>


<s> void neon_split_vcombine ( rtx operands [ 3 ] ) { unsigned int dest = REGNO ( operands [ 0 ] ) ; unsigned int src1 = REGNO ( operands [ 1 ] ) ; unsigned int src2 = REGNO ( operands [ 2 ] ) ; machine_mode halfmode = GET_MODE ( operands [ 1 ] ) ; unsigned int halfregs = HARD_REGNO_NREGS ( src1 , halfmode ) ; rtx destlo , desthi ; if ( src1 == dest && src2 == dest + halfregs ) { emit_note ( NOTE_INSN_DELETED ) ; return ; } destlo = gen_rtx_REG_offset ( operands [ 0 ] , halfmode , dest , 0 ) ; desthi = gen_rtx_REG_offset ( operands [ 0 ] , halfmode , dest + halfregs , GET_MODE_SIZE ( halfmode ) ) ; if ( src2 == dest && src1 == dest + halfregs ) { rtx x = gen_rtx_SET ( VOIDmode , destlo , operands [ 1 ] ) ; rtx y = gen_rtx_SET ( VOIDmode , desthi , operands [ 2 ] ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , x , y ) ) ) ; return ; } if ( ! reg_overlap_mentioned_p ( operands [ 2 ] , destlo ) ) { if ( src1 != dest ) emit_move_insn ( destlo , operands [ 1 ] ) ; if ( src2 != dest + halfregs ) emit_move_insn ( desthi , operands [ 2 ] ) ; } else { if ( src2 != dest + halfregs ) emit_move_insn ( desthi , operands [ 2 ] ) ; if ( src1 != dest ) emit_move_insn ( destlo , operands [ 1 ] ) ; } } </s>

Split operands into moves from op [ 1 ] + op [ 2 ] into op [ 0 ] .


<s>
void
TL45RegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
MachineInstr
&
MI
=
*
II
;
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"\nFunction : "
<<
MF
.
getName
(
)
<<
"\n"
;
dbgs
(
)
<<
"<--------->\n"
<<
MI
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
uint64_t
StackSize
=
MF
.
getFrameInfo
(
)
.
getStackSize
(
)
;
int64_t
SPOffset
=
MF
.
getFrameInfo
(
)
.
getObjectOffset
(
FrameIndex
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"FrameIndex : "
<<
FrameIndex
<<
"\n"
<<
"spOffset   : "
<<
SPOffset
<<
"\n"
<<
"stackSize  : "
<<
StackSize
<<
"\n"
<<
"alignment  : "
<<
MF
.
getFrameInfo
(
)
.
getObjectAlignment
(
FrameIndex
)
<<
"\n"
)
;
unsigned
OpNo
=
FIOperandNum
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
.
getCalleeSavedInfo
(
)
;
int
MinCSFI
=
0
;
int
MaxCSFI
=
1
;
if
(
CSI
.
size
(
)
)
{
MinCSFI
=
CSI
[
0
]
.
getFrameIdx
(
)
;
MaxCSFI
=
CSI
[
CSI
.
size
(
)
1
]
.
getFrameIdx
(
)
;
}
unsigned
FrameReg
;
FrameReg
=
TL45
::
sp
;
int64_t
Offset
;
bool
IsKill
=
false
;
Offset
=
SPOffset
+
(
int64_t
)
StackSize
;
Offset
+=
MI
.
getOperand
(
OpNo
+
1
)
.
getImm
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Offset     : "
<<
Offset
<<
"\n"
<<
"<--------->\n"
)
;
if
(
!
MI
.
isDebugValue
(
)
&&
!
TL45InstrInfo
::
validImmediate
(
MI
.
getOpcode
(
)
,
FrameReg
,
Offset
)
)
{
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
DebugLoc
DL
=
II
->
getDebugLoc
(
)
;
unsigned
NewImm
;
const
TL45InstrInfo
&
TII
=
*
static_cast
<
const
TL45InstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
FrameReg
=
TII
.
loadImmediate
(
FrameReg
,
Offset
,
MBB
,
II
,
DL
,
NewImm
)
;
Offset
=
SignExtend64
<
16
>
(
NewImm
)
;
}
MI
.
getOperand
(
OpNo
)
.
ChangeToRegister
(
FrameReg
,
false
,
false
,
IsKill
)
;
MI
.
getOperand
(
OpNo
+
1
)
.
ChangeToImmediate
(
Offset
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> std :: pair < unsigned , const TargetRegisterClass * > SparcTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : if ( VT == MVT :: v2i32 ) return std :: make_pair ( 0U , & SP :: IntPairRegClass ) ; else return std :: make_pair ( 0U , & SP :: IntRegsRegClass ) ; } } else if ( ! Constraint . empty ( ) && Constraint . size ( ) <= 5 && Constraint [ 0 ] == '{' && * ( Constraint . end ( ) - 1 ) == '}' ) { StringRef name ( Constraint . data ( ) + 1 , Constraint . size ( ) - 2 ) ; uint64_t intVal = 0 ; if ( name . substr ( 0 , 1 ) . equals ( "r" ) && ! name . substr ( 1 ) . getAsInteger ( 10 , intVal ) && intVal <= 31 ) { const char regTypes [ ] = { 'g' , 'o' , 'l' , 'i' } ; char regType = regTypes [ intVal / 8 ] ; char regIdx = '0' + ( intVal % 8 ) ; char tmp [ ] = { '{' , regType , regIdx , '}' , 0 } ; std :: string newConstraint = std :: string ( tmp ) ; return TargetLowering :: getRegForInlineAsmConstraint ( TRI , newConstraint , VT ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> unsigned getNumBlocks ( ) const override { return Unit -> getNumBlocks ( ) ; } </s>

Get the number of blocks in this loop in constant time .


"%s instructions aren%'t allowed in a function with "

Establish appropriate back-end context for processing the function FNDECL . The argument might be NULL to indicate processing at top level , outside of any function scope .


<s> static bool swap_top_of_ready_list ( rtx_insn * * ready , int n_ready ) { rtx_insn * top = ready [ n_ready - 1 ] ; rtx_insn * next = ready [ n_ready - 2 ] ; rtx set ; sd_iterator_def sd_it ; dep_t dep ; int clock1 = - 1 ; int clock2 = - 1 ; if ( ! TARGET_CPU_P ( SILVERMONT ) && ! TARGET_CPU_P ( INTEL ) ) return false ; if ( ! NONDEBUG_INSN_P ( top ) ) return false ; if ( ! NONJUMP_INSN_P ( top ) ) return false ; if ( ! NONDEBUG_INSN_P ( next ) ) return false ; if ( ! NONJUMP_INSN_P ( next ) ) return false ; set = single_set ( top ) ; if ( ! set ) return false ; set = single_set ( next ) ; if ( ! set ) return false ; if ( INSN_PRIORITY_KNOWN ( top ) && INSN_PRIORITY_KNOWN ( next ) ) { if ( INSN_PRIORITY ( top ) != INSN_PRIORITY ( next ) ) return false ; FOR_EACH_DEP ( top , SD_LIST_RES_BACK , sd_it , dep ) { rtx pro ; pro = DEP_PRO ( dep ) ; if ( ! NONDEBUG_INSN_P ( pro ) ) continue ; if ( INSN_TICK ( pro ) > clock1 ) clock1 = INSN_TICK ( pro ) ; } FOR_EACH_DEP ( next , SD_LIST_RES_BACK , sd_it , dep ) { rtx pro ; pro = DEP_PRO ( dep ) ; if ( ! NONDEBUG_INSN_P ( pro ) ) continue ; if ( INSN_TICK ( pro ) > clock2 ) clock2 = INSN_TICK ( pro ) ; } if ( clock1 == clock2 ) { enum attr_memory memory1 , memory2 ; memory1 = get_attr_memory ( top ) ; memory2 = get_attr_memory ( next ) ; if ( memory2 == MEMORY_LOAD && memory1 != MEMORY_LOAD ) return true ; } return ( bool ) ( clock2 < clock1 ) ; } return false ; } </s>

Try to find the best candidate on the top of ready list if two insns have the same priority - candidate is best if its dependees were scheduled earlier . Applied for Silvermont only . Return true if top 2 insns must be interchanged .


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , JIT , TT . getArch ( ) == Triple :: x86_64 ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) { if ( ( TT . isOSWindows ( ) && TT . getArch ( ) == Triple :: x86_64 ) || TT . isPS4 ( ) || TT . isOSBinFormatMachO ( ) ) this -> Options . TrapUnreachable = true ; initAsmInfo ( ) ; } </s>


<s> bool TeeRISCFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
MachineBasicBlock
*
SHUXITargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
unsigned
Opc
=
MI
.
getOpcode
(
)
;
const
TargetInstrInfo
&
TII
=
*
BB
->
getParent
(
)
->
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
dl
=
MI
.
getDebugLoc
(
)
;
assert
(
Opc
==
SHUXI
::
Select
&&
"Unexpected instr type to insert"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
I
=
++
BB
->
getIterator
(
)
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
copy1MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
F
->
insert
(
I
,
copy0MBB
)
;
F
->
insert
(
I
,
copy1MBB
)
;
copy1MBB
->
splice
(
copy1MBB
->
begin
(
)
,
BB
,
std
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
BB
->
end
(
)
)
;
copy1MBB
->
transferSuccessorsAndUpdatePHIs
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
copy1MBB
)
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
SHUXI
::
JCC
)
)
.
addMBB
(
copy1MBB
)
.
addImm
(
MI
.
getOperand
(
3
)
.
getImm
(
)
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
copy1MBB
)
;
BB
=
copy1MBB
;
BuildMI
(
*
BB
,
BB
->
begin
(
)
,
dl
,
TII
.
get
(
SHUXI
::
PHI
)
,
MI
.
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
.
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
.
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
MI
.
eraseFromParent
(
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


"Trying RISCV32Only_16 table (16-bit Instruction):\n"

"Trying RISCV_C table (16-bit Instruction):\n"

Returns the disassembly of a single instruction .


<s>
void
aarch64_print_patchable_function_entry
(
FILE
*
file
,
unsigned
HOST_WIDE_INT
patch_area_size
,
bool
record_p
)
{
if
(
cfun
->
machine
->
label_is_assembled
&&
aarch64_bti_enabled
(
)
&&
!
cgraph_node
::
get
(
cfun
->
decl
)
->
only_called_directly_p
(
)
)
{
rtx_insn
*
insn
=
next_real_nondebug_insn
(
get_insns
(
)
)
;
if
(
insn
&&
INSN_P
(
insn
)
&&
GET_CODE
(
PATTERN
(
insn
)
)
==
UNSPEC_VOLATILE
&&
XINT
(
PATTERN
(
insn
)
,
1
)
==
UNSPECV_BTI_C
)
delete_insn
(
insn
)
;
asm_fprintf
(
file
,
"\thint\t34 // bti c\n"
)
;
}
default_print_patchable_function_entry
(
file
,
patch_area_size
,
record_p
)
;
}
</s>

Implement PRINT_PATCHABLE_FUNCTION_ENTRY . Check if the patch area is after the function label and emit a BTI if necessary .


"Peephole: call to builtin function with "

runOnMachineFunction - Emit the function body .


<s> bool MipsSEInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock & MBB = * MI -> getParent ( ) ; switch ( MI -> getDesc ( ) . getOpcode ( ) ) { default : return false ; case Mips :: RetRA : expandRetRA ( MBB , MI , Mips :: RET ) ; break ; case Mips :: PseudoCVT_S_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_D32_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_D32_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_S_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_L , Mips :: DMTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_W , Mips :: MTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_L , Mips :: DMTC1 , true ) ; break ; case Mips :: BuildPairF64 : expandBuildPairF64 ( MBB , MI , false ) ; break ; case Mips :: BuildPairF64_64 : expandBuildPairF64 ( MBB , MI , true ) ; break ; case Mips :: ExtractElementF64 : expandExtractElementF64 ( MBB , MI , false ) ; break ; case Mips :: ExtractElementF64_64 : expandExtractElementF64 ( MBB , MI , true ) ; break ; case Mips :: MIPSeh_return32 : case Mips :: MIPSeh_return64 : expandEhReturn ( MBB , MI ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> BitVector AArch64RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const AArch64FrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , AArch64 :: WSP ) ; markSuperRegs ( Reserved , AArch64 :: WZR ) ; if ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) markSuperRegs ( Reserved , AArch64 :: W29 ) ; if ( MF . getSubtarget < AArch64Subtarget > ( ) . isX18Reserved ( ) ) markSuperRegs ( Reserved , AArch64 :: W18 ) ; if ( MF . getSubtarget < AArch64Subtarget > ( ) . isX20Reserved ( ) ) markSuperRegs ( Reserved , AArch64 :: W20 ) ; if ( hasBasePointer ( MF ) ) markSuperRegs ( Reserved , AArch64 :: W19 ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void rs6000_emit_le_vsx_store ( rtx dest , rtx source , machine_mode mode ) { rtx tmp , permute_src , permute_tmp ; gcc_assert ( ! reload_in_progress && ! lra_in_progress && ! reload_completed ) ; if ( mode == TImode || mode == V1TImode ) { mode = V2DImode ; dest = adjust_address ( dest , V2DImode , 0 ) ; source = gen_lowpart ( V2DImode , source ) ; } tmp = can_create_pseudo_p ( ) ? gen_reg_rtx_and_attrs ( source ) : source ; permute_src = rs6000_gen_le_vsx_permute ( source , mode ) ; permute_tmp = rs6000_gen_le_vsx_permute ( tmp , mode ) ; emit_insn ( gen_rtx_SET ( tmp , permute_src ) ) ; emit_insn ( gen_rtx_SET ( dest , permute_tmp ) ) ; } </s>

Emit a little-endian store to vector memory location DEST from VSX register SOURCE in mode MODE . The store is done with two permuting insn 's that represent an xxpermdi and an stxvd2x .


"Code generation for MIPS-I is not implemented"

"Code generation for MIPS-V is not implemented"

"MSA requires a 64-bit FPU register file (FR=1 mode). "

"-mattr=+nooddspreg requires the O32 ABI."

"FPXX is not permitted for the N32/N64 ABI's."

"position-independent code requires '-mabicalls'"

"warning: cannot use small-data accesses for '-mabicalls'"

This constructor initializes the data members to match that of the specified triple .


<s> static bool arm_r3_live_at_start_p ( void ) { return REGNO_REG_SET_P ( df_get_live_out ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) , 3 ) ; } </s>

Return true if r3 is live at the start of the function .


<s> void setKind ( BaseKind K ) { Kind = K ; } </s>


<s> int getOperandLatency ( const InstrItineraryData * ItinData , SDNode * DefNode , unsigned DefIdx , SDNode * UseNode , unsigned UseIdx ) const override { return PPCGenInstrInfo :: getOperandLatency ( ItinData , DefNode , DefIdx , UseNode , UseIdx ) ; } </s>

Compute and return the use operand latency of a given pair of def and use .


<s>
void
MipsInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
unsigned
Opc
=
0
;
if
(
RC
==
Mips
::
CPURegsRegisterClass
)
Opc
=
IsN64
Mips
::
LW_P8
:
Mips
::
LW
;
else
if
(
RC
==
Mips
::
CPU64RegsRegisterClass
)
Opc
=
IsN64
Mips
::
LD_P8
:
Mips
::
LD
;
else
if
(
RC
==
Mips
::
FGR32RegisterClass
)
Opc
=
IsN64
Mips
::
LWC1_P8
:
Mips
::
LWC1
;
else
if
(
RC
==
Mips
::
AFGR64RegisterClass
)
Opc
=
Mips
::
LDC1
;
else
if
(
RC
==
Mips
::
FGR64RegisterClass
)
Opc
=
IsN64
Mips
::
LDC164_P8
:
Mips
::
LDC164
;
assert
(
Opc
&&
"Register class not handled!"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> static void mips_expand_vi_constant ( machine_mode vmode , unsigned nelt , rtx target , rtx vals ) { rtvec vec = shallow_copy_rtvec ( XVEC ( vals , 0 ) ) ; unsigned i ; for ( i = 0 ; i < nelt ; ++ i ) { rtx elem = RTVEC_ELT ( vec , i ) ; if ( ! mips_constant_elt_p ( elem ) ) RTVEC_ELT ( vec , i ) = CONST0_RTX ( GET_MODE ( elem ) ) ; } emit_move_insn ( target , gen_rtx_CONST_VECTOR ( vmode , vec ) ) ; } </s>

A subroutine of mips_expand_vec_init , replacing all of the non-constant elements of VALS with zeros , copy the constant vector to TARGET .


<s> int ix86_attr_length_vex_default ( rtx_insn * insn , bool has_0f_opcode , bool has_vex_w ) { int i , reg_only = 2 + 1 ; bool has_mem = false ; if ( ! has_0f_opcode || has_vex_w ) return 3 + 1 ; if ( ! TARGET_64BIT ) return 2 + 1 ; extract_insn_cached ( insn ) ; for ( i = recog_data . n_operands - 1 ; i >= 0 ; -- i ) if ( REG_P ( recog_data . operand [ i ] ) ) { if ( GET_MODE ( recog_data . operand [ i ] ) == DImode && GENERAL_REG_P ( recog_data . operand [ i ] ) ) return 3 + 1 ; if ( REX_INT_REGNO_P ( recog_data . operand [ i ] ) || REX_SSE_REGNO_P ( recog_data . operand [ i ] ) ) reg_only = 3 + 1 ; } else if ( MEM_P ( recog_data . operand [ i ] ) ) { if ( x86_extended_reg_mentioned_p ( recog_data . operand [ i ] ) ) return 3 + 1 ; has_mem = true ; } return has_mem ? 2 + 1 : reg_only ; } </s>

Compute default value for `` length_vex '' attribute . It includes 2 or 3 byte VEX prefix and 1 opcode byte .


<s> void erase ( iterator it ) { m_SectToExData . erase ( it ) ; } </s>

erase - Erases an element identified by Key , if it exists .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> unsigned getMask ( ) const { return Mask ; } </s>


<s> void visium_expand_int_cstore ( rtx * operands , enum machine_mode mode ) { enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; rtx op0 = operands [ 0 ] , op1 = operands [ 2 ] , op2 = operands [ 3 ] , sltu ; bool reverse = false ; switch ( code ) { case EQ : case NE : if ( op2 != const0_rtx ) op1 = force_reg ( mode , gen_rtx_XOR ( mode , op1 , op2 ) ) ; op1 = gen_rtx_NOT ( mode , op1 ) ; op2 = constm1_rtx ; if ( code == EQ ) reverse = true ; break ; case LEU : case GEU : code = reverse_condition ( code ) ; reverse = true ; case LTU : case GTU : if ( code == GTU ) { rtx tmp = op1 ; op1 = op2 ; op2 = tmp ; } break ; default : gcc_unreachable ( ) ; } sltu = gen_rtx_LTU ( SImode , op1 , op2 ) ; if ( reverse ) { rtx tmp = copy_to_mode_reg ( SImode , gen_rtx_NEG ( SImode , sltu ) ) ; emit_insn ( gen_add3_insn ( op0 , tmp , const1_rtx ) ) ; } else emit_insn ( gen_rtx_SET ( VOIDmode , op0 , sltu ) ) ; } </s>

Expand a cstore of OPERANDS in MODE for EQ/NE/LTU/GTU/GEU/LEU . We generate the result in the C flag and use the ADC/SUBC instructions to write it into the destination register . It would also be possible to implement support for LT/GT/LE/GE by means of the RFLAG instruction followed by some shifts , but this can pessimize the generated code .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> param_iterator arg_begin ( ) const { return ArgumentParams . begin ( ) ; } </s>

Return the iterator pointing to the beginning of the argument list .


"constant argument %d for builtin %qF is invalid (%s)"

"constant argument %d for builtin %qF is out of range (0-%wu)"

"constant argument %d for builtin %qF is out of range "

Return true if ARG is appropriate as argument number ARGNUM of builtin DECL . The operand flags from s390-builtins.def have to passed as OP_FLAGS .


<s> static int s390_sched_score ( rtx_insn * insn ) { unsigned int mask = s390_get_sched_attrmask ( insn ) ; int score = 0 ; switch ( s390_sched_state ) { case 0 : if ( ( mask & S390_OOO_SCHED_ATTR_MASK_CRACKED ) != 0 || ( mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED ) != 0 ) score += 5 ; if ( ( mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE ) != 0 ) score += 10 ; case 1 : if ( ( mask & S390_OOO_SCHED_ATTR_MASK_CRACKED ) == 0 && ( mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED ) == 0 && ( mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE ) == 0 ) score += 10 ; if ( ( mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP ) == 0 ) score += 5 ; break ; case 2 : if ( ( mask & S390_OOO_SCHED_ATTR_MASK_CRACKED ) == 0 && ( mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED ) == 0 && ( mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE ) == 0 ) score += 10 ; if ( ( mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP ) != 0 ) score += 10 ; break ; case S390_OOO_SCHED_STATE_NORMAL : if ( ( mask & S390_OOO_SCHED_ATTR_MASK_CRACKED ) == 0 && ( mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED ) == 0 ) score += 5 ; if ( ( mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE ) != 0 ) score += 10 ; break ; case S390_OOO_SCHED_STATE_CRACKED : if ( ( mask & S390_OOO_SCHED_ATTR_MASK_CRACKED ) != 0 || ( mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED ) != 0 ) score += 5 ; break ; } return score ; } </s>

Return the scheduling score for INSN . The higher the score the better . The score is calculated from the OOO scheduling attributes of INSN and the scheduling state s390_sched_state .


<s> static void aarch64_update_cpp_builtins ( cpp_reader * pfile ) { aarch64_def_or_undef ( flag_unsafe_math_optimizations , "__ARM_FP_FAST" , pfile ) ; builtin_define_with_int_value ( "__ARM_ARCH" , aarch64_architecture_version ) ; builtin_define_with_int_value ( "__ARM_SIZEOF_MINIMAL_ENUM" , flag_short_enums ? 1 : 4 ) ; aarch64_def_or_undef ( TARGET_BIG_END , "__AARCH64EB__" , pfile ) ; aarch64_def_or_undef ( TARGET_BIG_END , "__ARM_BIG_ENDIAN" , pfile ) ; aarch64_def_or_undef ( ! TARGET_BIG_END , "__AARCH64EL__" , pfile ) ; aarch64_def_or_undef ( TARGET_FLOAT , "__ARM_FEATURE_FMA" , pfile ) ; if ( TARGET_FLOAT || TARGET_SIMD ) { builtin_define_with_int_value ( "__ARM_FP" , 0x0E ) ; builtin_define ( "__ARM_FP16_FORMAT_IEEE" ) ; builtin_define ( "__ARM_FP16_ARGS" ) ; } else cpp_undef ( pfile , "__ARM_FP" ) ; aarch64_def_or_undef ( TARGET_SIMD , "__ARM_FEATURE_NUMERIC_MAXMIN" , pfile ) ; aarch64_def_or_undef ( TARGET_SIMD , "__ARM_NEON" , pfile ) ; aarch64_def_or_undef ( TARGET_CRC32 , "__ARM_FEATURE_CRC32" , pfile ) ; cpp_undef ( pfile , "__AARCH64_CMODEL_TINY__" ) ; cpp_undef ( pfile , "__AARCH64_CMODEL_SMALL__" ) ; cpp_undef ( pfile , "__AARCH64_CMODEL_LARGE__" ) ; switch ( aarch64_cmodel ) { case AARCH64_CMODEL_TINY : case AARCH64_CMODEL_TINY_PIC : builtin_define ( "__AARCH64_CMODEL_TINY__" ) ; break ; case AARCH64_CMODEL_SMALL : case AARCH64_CMODEL_SMALL_PIC : builtin_define ( "__AARCH64_CMODEL_SMALL__" ) ; break ; case AARCH64_CMODEL_LARGE : builtin_define ( "__AARCH64_CMODEL_LARGE__" ) ; break ; default : break ; } aarch64_def_or_undef ( TARGET_ILP32 , "_ILP32" , pfile ) ; aarch64_def_or_undef ( TARGET_ILP32 , "__ILP32__" , pfile ) ; aarch64_def_or_undef ( TARGET_CRYPTO , "__ARM_FEATURE_CRYPTO" , pfile ) ; aarch64_def_or_undef ( TARGET_SIMD_RDMA , "__ARM_FEATURE_QRDMX" , pfile ) ; } </s>

Undefine/redefine macros that depend on the current backend state and may need to change when a target pragma modifies the backend state .


<s> const uint32_t * AVRRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const AVRMachineFunctionInfo * AFI = MF . getInfo < AVRMachineFunctionInfo > ( ) ; return AFI -> isInterruptOrSignalHandler ( ) ? CSR_Interrupts_RegMask : CSR_Normal_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool RV16KAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { if ( ( Count % 2 ) != 0 ) return false ; Count /= 2 ; for ( uint64_t i = 0 ; i < Count ; ++ i ) OS . write ( "\0\0" , 2 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> void LC3bAsmPrinter :: emitFrameDirective ( ) { } </s>


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCRelaxableFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
{
assert
(
0
&&
"RelaxInstruction() unimplemented"
)
;
return
false
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .

Mips
0
"RelaxInstruction() unimplemented"


<s> static bool mips_scalar_mode_supported_p ( scalar_mode mode ) { if ( ALL_FIXED_POINT_MODE_P ( mode ) && GET_MODE_PRECISION ( mode ) <= 2 * BITS_PER_WORD ) return true ; return default_scalar_mode_supported_p ( mode ) ; } </s>


<s>
bool
RISCVInstrInfo
::
reverseBranchCondition
(
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
assert
(
(
Cond
.
size
(
)
==
3
)
&&
"Invalid branch condition!"
)
;
auto
CC
=
static_cast
<
RISCVCC
::
CondCode
>
(
Cond
[
0
]
.
getImm
(
)
)
;
Cond
[
0
]
.
setImm
(
getOppositeBranchCondition
(
CC
)
)
;
return
false
;
}
</s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Hexagon Split TFRCondSets"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
void
SIWholeQuadMode
::
processBlock
(
MachineBasicBlock
&
MBB
,
unsigned
LiveMaskReg
,
bool
isEntry
)
{
auto
BII
=
Blocks
.
find
(
&
MBB
)
;
if
(
BII
==
Blocks
.
end
(
)
)
return
;
const
BlockInfo
&
BI
=
BII
->
second
;
if
(
!
(
BI
.
InNeeds
&
StateWQM
)
)
return
;
if
(
!
isEntry
&&
!
(
BI
.
Needs
&
StateExact
)
&&
BI
.
OutNeeds
!=
StateExact
)
return
;
DEBUG
(
dbgs
(
)
<<
"\nProcessing block BB#"
<<
MBB
.
getNumber
(
)
<<
":\n"
)
;
unsigned
SavedWQMReg
=
0
;
bool
WQMFromExec
=
isEntry
;
char
State
=
isEntry
StateExact
:
StateWQM
;
auto
II
=
MBB
.
getFirstNonPHI
(
)
,
IE
=
MBB
.
end
(
)
;
if
(
isEntry
)
++
II
;
MachineBasicBlock
::
iterator
First
=
IE
;
for
(
;
;
)
{
MachineBasicBlock
::
iterator
Next
=
II
;
char
Needs
=
0
;
char
OutNeeds
=
0
;
if
(
First
==
IE
)
First
=
II
;
if
(
II
!=
IE
)
{
MachineInstr
&
MI
=
*
II
;
if
(
requiresCorrectState
(
MI
)
)
{
auto
III
=
Instructions
.
find
(
&
MI
)
;
if
(
III
!=
Instructions
.
end
(
)
)
{
Needs
=
III
->
second
.
Needs
;
OutNeeds
=
III
->
second
.
OutNeeds
;
}
}
if
(
MI
.
isTerminator
(
)
&&
!
Needs
&&
OutNeeds
==
StateExact
)
Needs
=
StateExact
;
if
(
MI
.
getOpcode
(
)
==
AMDGPU
::
SI_ELSE
&&
BI
.
OutNeeds
==
StateExact
)
MI
.
getOperand
(
3
)
.
setImm
(
1
)
;
++
Next
;
}
else
{
if
(
BI
.
OutNeeds
&
StateWQM
)
Needs
=
StateWQM
;
else
if
(
BI
.
OutNeeds
==
StateExact
)
Needs
=
StateExact
;
}
if
(
Needs
)
{
if
(
Needs
!=
State
)
{
MachineBasicBlock
::
iterator
Before
=
prepareInsertion
(
MBB
,
First
,
II
,
Needs
==
StateWQM
,
Needs
==
StateExact
||
WQMFromExec
)
;
if
(
Needs
==
StateExact
)
{
if
(
!
WQMFromExec
&&
(
OutNeeds
&
StateWQM
)
)
SavedWQMReg
=
MRI
->
createVirtualRegister
(
&
AMDGPU
::
SReg_64RegClass
)
;
toExact
(
MBB
,
Before
,
SavedWQMReg
,
LiveMaskReg
)
;
}
else
{
assert
(
WQMFromExec
==
(
SavedWQMReg
==
0
)
)
;
toWQM
(
MBB
,
Before
,
SavedWQMReg
)
;
if
(
SavedWQMReg
)
{
LIS
->
createAndComputeVirtRegInterval
(
SavedWQMReg
)
;
SavedWQMReg
=
0
;
}
}
State
=
Needs
;
}
First
=
IE
;
}
if
(
II
==
IE
)
break
;
II
=
Next
;
}
}
</s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s> static int n_regs_saved_by_prologue ( void ) { e_funkind fkind = funkind ( TREE_TYPE ( current_function_decl ) ) ; bool is_inthandler = fkind != SUBROUTINE ; tree attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ; bool all = ( lookup_attribute ( "saveall" , attrs ) != NULL_TREE || ( is_inthandler && ! current_function_is_leaf ) ) ; int ndregs = all ? 8 : n_dregs_to_save ( is_inthandler ) ; int npregs = all ? 6 : n_pregs_to_save ( is_inthandler ) ; int n = ndregs + npregs ; if ( all || stack_frame_needed_p ( ) ) n += 2 ; else { if ( must_save_fp_p ( ) ) n ++ ; if ( ! current_function_is_leaf ) n ++ ; } if ( fkind != SUBROUTINE ) { int i ; n ++ ; if ( lookup_attribute ( "nesting" , attrs ) ) n ++ ; for ( i = REG_P7 + 1 ; i < REG_CC ; i ++ ) if ( all || regs_ever_live [ i ] || ( ! leaf_function_p ( ) && call_used_regs [ i ] ) ) n += i == REG_A0 || i == REG_A1 ? 2 : 1 ; } return n ; } </s>

Return the number of registers pushed during the prologue .


<s> int alpha_store_data_bypass_p ( rtx_insn * out_insn , rtx_insn * in_insn ) { rtx in_set = single_set ( in_insn ) ; if ( in_set ) return alpha_store_data_bypass_p_1 ( out_insn , in_set ) ; rtx in_pat = PATTERN ( in_insn ) ; if ( GET_CODE ( in_pat ) != PARALLEL ) return false ; for ( int i = 0 ; i < XVECLEN ( in_pat , 0 ) ; i ++ ) { rtx in_exp = XVECEXP ( in_pat , 0 , i ) ; if ( GET_CODE ( in_exp ) == CLOBBER || GET_CODE ( in_exp ) == USE || GET_CODE ( in_exp ) == TRAP_IF ) continue ; gcc_assert ( GET_CODE ( in_exp ) == SET ) ; if ( ! alpha_store_data_bypass_p_1 ( out_insn , in_exp ) ) return false ; } return true ; } </s>

True if the dependency between OUT_INSN and IN_INSN is on the store data not the address operand ( s ) of the store . IN_INSN and OUT_INSN must be either a single_set or a PARALLEL with SETs inside . This alpha-specific version of store_data_bypass_p ignores TRAP_IF that would result in assertion failure ( and internal compiler error ) in the generic store_data_bypass_p function .


<s> static bool rs6000_vectorize_vec_perm_const_ok ( machine_mode vmode , const unsigned char * sel ) { if ( TARGET_ALTIVEC ) return true ; if ( ( TARGET_PAIRED_FLOAT && vmode == V2SFmode ) || ( TARGET_SPE && vmode == V2SImode ) ) { rtx op0 = gen_raw_REG ( vmode , LAST_VIRTUAL_REGISTER + 1 ) ; rtx op1 = gen_raw_REG ( vmode , LAST_VIRTUAL_REGISTER + 2 ) ; return rs6000_expand_vec_perm_const_1 ( NULL , op0 , op1 , sel [ 0 ] , sel [ 1 ] ) ; } return false ; } </s>

Test whether a constant permutation is supported .


<s>
static
void
cris_print_operand_address
(
FILE
*
file
,
machine_mode
,
rtx
x
)
{
putc
(
'['
,
file
)
;
if
(
CONSTANT_ADDRESS_P
(
x
)
)
cris_output_addr_const
(
file
,
x
)
;
else
if
(
cris_base_or_autoincr_p
(
x
,
true
)
)
cris_print_base
(
x
,
file
)
;
else
if
(
GET_CODE
(
x
)
==
PLUS
)
{
rtx
x1
,
x2
;
x1
=
XEXP
(
x
,
0
)
;
x2
=
XEXP
(
x
,
1
)
;
if
(
cris_base_p
(
x1
,
true
)
)
{
cris_print_base
(
x1
,
file
)
;
cris_print_index
(
x2
,
file
)
;
}
else
if
(
cris_base_p
(
x2
,
true
)
)
{
cris_print_base
(
x2
,
file
)
;
cris_print_index
(
x1
,
file
)
;
}
else
LOSE_AND_RETURN
(
"unrecognized address"
,
x
)
;
}
else
if
(
MEM_P
(
x
)
)
{
putc
(
'['
,
file
)
;
cris_print_base
(
XEXP
(
x
,
0
)
,
file
)
;
putc
(
']'
,
file
)
;
}
else
LOSE_AND_RETURN
(
"unrecognized address"
,
x
)
;
putc
(
']'
,
file
)
;
}
</s>


<s> const Triple & getTargetTriple ( ) const { return TargetTriple ; } </s>

Get the target triple which is a string describing the target host .


<s> void altivec_expand_stvex_be ( rtx op0 , rtx op1 , machine_mode mode , unsigned unspec ) { machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx tmp = gen_reg_rtx ( mode ) ; rtx stvx = gen_rtx_UNSPEC ( inner_mode , gen_rtvec ( 1 , tmp ) , unspec ) ; rtx sel = swap_selector_for_mode ( mode ) ; rtx vperm ; gcc_assert ( REG_P ( op1 ) ) ; vperm = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , op1 , op1 , sel ) , UNSPEC_VPERM ) ; emit_insn ( gen_rtx_SET ( tmp , vperm ) ) ; emit_insn ( gen_rtx_SET ( op0 , stvx ) ) ; } </s>

Generate code for a `` stve * x '' built-in for a little endian target with -maltivec=be specified . Issue the store preceded by an element-reversing permute .


<s> bool MipsTargetLowering :: shouldFoldConstantShiftPairToMask ( const SDNode * N , CombineLevel Level ) const { if ( N -> getOperand ( 0 ) . getValueType ( ) . isVector ( ) ) return false ; return true ; } </s>

Return true if it is profitable to fold a pair of shifts into a mask .


<s> void * getAdjustedAnalysisPointer ( const void * ID ) override { if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo * ) this ; return this ; } </s>

getAdjustedAnalysisPointer - This method is used when a pass implements an analysis interface through multiple inheritance .


<s>
void
maybe_unlink
(
const
char
*
file
)
{
if
(
!
debug
)
{
if
(
unlink_if_ordinary
(
file
)
&&
errno
!=
ENOENT
)
fatal_error
(
input_location
,
"deleting file %s: %m"
,
file
)
;
}
else
fprintf
(
stderr
,
"[Leaving %s]\n"
,
file
)
;
}
</s>

Unlink a temporary file unless requested otherwise .

nvptx
"deleting file %s: %m"
"[Leaving %s]\n"


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveAArch64CodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } if ( getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) { this -> Options . TrapUnreachable = true ; } if ( this -> Options . TLSSize == 0 ) this -> Options . TLSSize = 24 ; if ( ( getCodeModel ( ) == CodeModel :: Small || getCodeModel ( ) == CodeModel :: Kernel ) && this -> Options . TLSSize > 32 ) this -> Options . TLSSize = 32 ; else if ( getCodeModel ( ) == CodeModel :: Tiny && this -> Options . TLSSize > 24 ) this -> Options . TLSSize = 24 ; if ( getOptLevel ( ) <= EnableGlobalISelAtO && TT . getArch ( ) != Triple :: aarch64_32 && ! ( getCodeModel ( ) == CodeModel :: Large && TT . isOSBinFormatMachO ( ) ) ) { setGlobalISel ( true ) ; setGlobalISelAbort ( GlobalISelAbortMode :: Disable ) ; } setMachineOutliner ( true ) ; setSupportsDefaultOutlining ( true ) ; } </s>


<s> void PPCPassConfig :: addIRPasses ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCBoolRetToIntPass ( ) ) ; addPass ( createAtomicExpandPass ( & getPPCTargetMachine ( ) ) ) ; bool UsePrefetching = TM -> getTargetTriple ( ) . getVendor ( ) == Triple :: BGQ && getOptLevel ( ) != CodeGenOpt :: None ; if ( EnablePrefetch . getNumOccurrences ( ) > 0 ) UsePrefetching = EnablePrefetch ; if ( UsePrefetching ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Default && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static bool mips_expand_vselect ( rtx target , rtx op0 , const unsigned char * perm , unsigned nelt ) { rtx rperm [ MAX_VECT_LEN ] , x ; rtx_insn * insn ; unsigned i ; for ( i = 0 ; i < nelt ; ++ i ) rperm [ i ] = GEN_INT ( perm [ i ] ) ; x = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( nelt , rperm ) ) ; x = gen_rtx_VEC_SELECT ( GET_MODE ( target ) , op0 , x ) ; x = gen_rtx_SET ( VOIDmode , target , x ) ; insn = emit_insn ( x ) ; if ( recog_memoized ( insn ) < 0 ) { remove_insn ( insn ) ; return false ; } return true ; } </s>

Construct ( set target ( vec_select op0 ( parallel perm ) ) ) and return true if that 's a valid instruction in the active ISA .


<s> extern machine_mode vax_select_cc_mode ( enum rtx_code op , rtx x ATTRIBUTE_UNUSED , rtx y ATTRIBUTE_UNUSED ) { switch ( op ) { default : gcc_unreachable ( ) ; case NE : case EQ : return CCZmode ; case GE : case LT : return CCNmode ; case GT : case LE : return CCNZmode ; case GEU : case GTU : case LEU : case LTU : return CCmode ; } } </s>

Given a comparison code ( NE , EQ , etc . ) and the operands of a COMPARE , return the mode to be used for the comparison . As we have the same interpretation of condition codes across all the instructions we just return the narrowest mode suitable for the comparison code requested .