<s> static bool arc_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { if ( size == UNITS_PER_WORD && aligned_p && ( ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( x ) ) || GET_CODE ( x ) == LABEL_REF ) ) { fputs ( "\t.word\t%st(" , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; fputs ( ")\n" , asm_out_file ) ; return true ; } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook to assemble an integer object . The ARC version needs to emit a special directive for references to labels and function symbols .


<s> static int ix86_mode_needed ( int entity , rtx_insn * insn ) { switch ( entity ) { case AVX_U128 : return ix86_avx_u128_mode_needed ( insn ) ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : case I387_MASK_PM : return ix86_i387_mode_needed ( entity , insn ) ; default : gcc_unreachable ( ) ; } return 0 ; } </s>

Return needed mode for entity in optimize_mode_switching pass .


<s> int frv_legitimate_constant_p ( rtx x ) { enum machine_mode mode = GET_MODE ( x ) ; if ( TARGET_FDPIC ) return LEGITIMATE_PIC_OPERAND_P ( x ) ; if ( GET_CODE ( x ) != CONST_DOUBLE ) return TRUE ; if ( mode == VOIDmode || mode == DImode ) return TRUE ; if ( x == CONST0_RTX ( mode ) ) return TRUE ; if ( ! TARGET_HAS_FPRS ) return TRUE ; if ( mode == DFmode && ! TARGET_DOUBLE ) return TRUE ; return FALSE ; } </s>

A C expression that is nonzero if X is a legitimate constant for an immediate operand on the target machine . You can assume that X satisfies ` CONSTANT_P ' , so you need not check this . In fact , ` 1 ' is a suitable definition for this macro on machines where anything ` CONSTANT_P ' is valid .


<s> const uint32_t * MipsRegisterInfo :: getCallPreservedMask ( CallingConv :: ID ) const { if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_RegMask ; if ( Subtarget . isFPXX ( ) ) return CSR_O32_FPXX_RegMask ; return CSR_O32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> unsigned aarch64_dbx_register_number ( unsigned regno ) { if ( GP_REGNUM_P ( regno ) ) return AARCH64_DWARF_R0 + regno - R0_REGNUM ; else if ( regno == SP_REGNUM ) return AARCH64_DWARF_SP ; else if ( FP_REGNUM_P ( regno ) ) return AARCH64_DWARF_V0 + regno - V0_REGNUM ; return DWARF_FRAME_REGISTERS ; } </s>

Provide a mapping from gcc register numbers to dwarf register numbers .


<s> static bool avr_function_ok_for_sibcall ( tree decl_callee , tree exp_callee ) { tree fntype_callee ; if ( cfun -> machine -> sibcall_fails || TARGET_CALL_PROLOGUES ) { return false ; } fntype_callee = TREE_TYPE ( CALL_EXPR_FN ( exp_callee ) ) ; if ( decl_callee ) { decl_callee = TREE_TYPE ( decl_callee ) ; } else { decl_callee = fntype_callee ; while ( FUNCTION_TYPE != TREE_CODE ( decl_callee ) && METHOD_TYPE != TREE_CODE ( decl_callee ) ) { decl_callee = TREE_TYPE ( decl_callee ) ; } } if ( cfun -> machine -> is_interrupt || cfun -> machine -> is_signal || cfun -> machine -> is_naked || avr_naked_function_p ( decl_callee ) || ( avr_OS_task_function_p ( decl_callee ) != cfun -> machine -> is_OS_task ) || ( avr_OS_main_function_p ( decl_callee ) != cfun -> machine -> is_OS_main ) ) { return false ; } return true ; } </s>

Decide whether we can make a sibling call to a function . DECL is the declaration of the function being targeted by the call and EXP is the CALL_EXPR representing the call .


<s>
MachineBasicBlock
*
MSP430TargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
unsigned
Opc
=
MI
.
getOpcode
(
)
;
if
(
Opc
==
MSP430
::
Shl8
||
Opc
==
MSP430
::
Shl16
||
Opc
==
MSP430
::
Sra8
||
Opc
==
MSP430
::
Sra16
||
Opc
==
MSP430
::
Srl8
||
Opc
==
MSP430
::
Srl16
||
Opc
==
MSP430
::
Rrcl8
||
Opc
==
MSP430
::
Rrcl16
)
return
EmitShiftInstr
(
MI
,
BB
)
;
const
TargetInstrInfo
&
TII
=
*
BB
->
getParent
(
)
->
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
dl
=
MI
.
getDebugLoc
(
)
;
assert
(
(
Opc
==
MSP430
::
Select16
||
Opc
==
MSP430
::
Select8
)
&&
"Unexpected instr type to insert"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
I
=
++
BB
->
getIterator
(
)
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
copy1MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
F
->
insert
(
I
,
copy0MBB
)
;
F
->
insert
(
I
,
copy1MBB
)
;
copy1MBB
->
splice
(
copy1MBB
->
begin
(
)
,
BB
,
std
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
BB
->
end
(
)
)
;
copy1MBB
->
transferSuccessorsAndUpdatePHIs
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
copy1MBB
)
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
MSP430
::
JCC
)
)
.
addMBB
(
copy1MBB
)
.
addImm
(
MI
.
getOperand
(
3
)
.
getImm
(
)
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
copy1MBB
)
;
BB
=
copy1MBB
;
BuildMI
(
*
BB
,
BB
->
begin
(
)
,
dl
,
TII
.
get
(
MSP430
::
PHI
)
,
MI
.
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
.
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
.
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
MI
.
eraseFromParent
(
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


"All return types should use a single register"

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s>
static
SDValue
getTargetNode
(
SDValue
Op
,
SelectionDAG
&
DAG
,
unsigned
Flag
)
{
EVT
Ty
=
Op
.
getValueType
(
)
;
if
(
GlobalAddressSDNode
*
N
=
dyn_cast
<
GlobalAddressSDNode
>
(
Op
)
)
return
DAG
.
getTargetGlobalAddress
(
N
->
getGlobal
(
)
,
SDLoc
(
Op
)
,
Ty
,
0
,
Flag
)
;
if
(
ExternalSymbolSDNode
*
N
=
dyn_cast
<
ExternalSymbolSDNode
>
(
Op
)
)
return
DAG
.
getTargetExternalSymbol
(
N
->
getSymbol
(
)
,
Ty
,
Flag
)
;
if
(
BlockAddressSDNode
*
N
=
dyn_cast
<
BlockAddressSDNode
>
(
Op
)
)
return
DAG
.
getTargetBlockAddress
(
N
->
getBlockAddress
(
)
,
Ty
,
0
,
Flag
)
;
if
(
JumpTableSDNode
*
N
=
dyn_cast
<
JumpTableSDNode
>
(
Op
)
)
return
DAG
.
getTargetJumpTable
(
N
->
getIndex
(
)
,
Ty
,
Flag
)
;
if
(
ConstantPoolSDNode
*
N
=
dyn_cast
<
ConstantPoolSDNode
>
(
Op
)
)
return
DAG
.
getTargetConstantPool
(
N
->
getConstVal
(
)
,
Ty
,
N
->
getAlignment
(
)
,
N
->
getOffset
(
)
,
Flag
)
;
llvm_unreachable
(
"Unexpected node type."
)
;
return
SDValue
(
)
;
}
</s>

Retrieve the target node this edge connects to .


<s> void ARMWinCOFFStreamer :: finishImpl ( ) { emitFrames ( nullptr ) ; emitWindowsUnwindTables ( ) ; MCWinCOFFStreamer :: finishImpl ( ) ; } </s>


<s> SDNode * SICDAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = MF -> getInfo < SICFunctionInfo > ( ) -> getGlobalBaseReg ( ) ; return CurDAG -> getRegister ( GlobalBaseReg , getTargetLowering ( ) -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> int s390_N_constraint_str ( const char * str , HOST_WIDE_INT value ) { machine_mode mode , part_mode ; int def ; int part , part_goal ; if ( str [ 0 ] == 'x' ) part_goal = - 1 ; else part_goal = str [ 0 ] - '0' ; switch ( str [ 1 ] ) { case 'Q' : part_mode = QImode ; break ; case 'H' : part_mode = HImode ; break ; case 'S' : part_mode = SImode ; break ; default : return 0 ; } switch ( str [ 2 ] ) { case 'H' : mode = HImode ; break ; case 'S' : mode = SImode ; break ; case 'D' : mode = DImode ; break ; default : return 0 ; } switch ( str [ 3 ] ) { case '0' : def = 0 ; break ; case 'F' : def = - 1 ; break ; default : return 0 ; } if ( GET_MODE_SIZE ( mode ) <= GET_MODE_SIZE ( part_mode ) ) return 0 ; part = s390_single_part ( GEN_INT ( value ) , mode , part_mode , def ) ; if ( part < 0 ) return 0 ; if ( part_goal != - 1 && part_goal != part ) return 0 ; return 1 ; } </s>

Evaluates constraint strings starting with letter N. Parameter STR contains the letters following letter `` N '' in the constraint string . Returns true if VALUE matches the constraint .


<s> int mn10300_legitimate_pic_operand_p ( rtx x ) { const char * fmt ; int i ; if ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF ) return 0 ; if ( GET_CODE ( x ) == UNSPEC && ( XINT ( x , 1 ) == UNSPEC_PIC || XINT ( x , 1 ) == UNSPEC_GOT || XINT ( x , 1 ) == UNSPEC_GOTOFF || XINT ( x , 1 ) == UNSPEC_PLT || XINT ( x , 1 ) == UNSPEC_GOTSYM_OFF ) ) return 1 ; fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( x , i ) - 1 ; j >= 0 ; j -- ) if ( ! mn10300_legitimate_pic_operand_p ( XVECEXP ( x , i , j ) ) ) return 0 ; } else if ( fmt [ i ] == 'e' && ! mn10300_legitimate_pic_operand_p ( XEXP ( x , i ) ) ) return 0 ; } return 1 ; } </s>

Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol is n't protected by a PIC unspec ; nonzero otherwise .


<s> unsigned AVRRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { return AVR :: R28 ; } return AVR :: SP ; } </s>


<s>
void
m32c_output_reg_pop
(
FILE
*
s
,
int
regno
)
{
if
(
regno
==
FLG_REGNO
)
fprintf
(
s
,
"\tpopc\tflg\n"
)
;
else
fprintf
(
s
,
"\tpop.%c\t%s"
,
" bwll"
[
reg_push_size
(
regno
)
]
,
reg_names
[
regno
]
)
;
}
</s>


<s> VSETVLIInfo intersect ( const VSETVLIInfo & Other ) const { if ( ! Other . isValid ( ) ) return * this ; if ( ! isValid ( ) ) return Other ; if ( isUnknown ( ) || Other . isUnknown ( ) ) return VSETVLIInfo :: getUnknown ( ) ; if ( * this == Other ) return * this ; if ( hasSameAVL ( Other ) && hasSameVLMAX ( Other ) ) { VSETVLIInfo MergeInfo = * this ; MergeInfo . SEWLMULRatioOnly = true ; return MergeInfo ; } return VSETVLIInfo :: getUnknown ( ) ; } </s>

Intersect this set with a temporary other set in place .


<s> bool HexagonGenPredicate :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; TII = MF . getSubtarget < HexagonSubtarget > ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget < HexagonSubtarget > ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; PredGPRs . clear ( ) ; PUsers . clear ( ) ; G2P . clear ( ) ; bool Changed = false ; collectPredicateGPR ( MF ) ; for ( SetOfReg :: iterator I = PredGPRs . begin ( ) , E = PredGPRs . end ( ) ; I != E ; ++ I ) processPredicateGPR ( * I ) ; bool Again ; do { Again = false ; VectOfInst Processed , Copy ; using iterator = VectOfInst :: iterator ; Copy = PUsers ; for ( iterator I = Copy . begin ( ) , E = Copy . end ( ) ; I != E ; ++ I ) { MachineInstr * MI = * I ; bool Done = convertToPredForm ( MI ) ; if ( Done ) { Processed . insert ( MI ) ; Again = true ; } } Changed |= Again ; auto Done = [ Processed ] ( MachineInstr * MI ) -> bool { return Processed . count ( MI ) ; } ; PUsers . remove_if ( Done ) ; } while ( Again ) ; Changed |= eliminatePredCopies ( MF ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> void EmitInstruction ( const MachineInstr * MI ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; printInstruction ( MI , OS ) ; OutStreamer . EmitRawText ( OS . str ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static bool const_load_sequence_p ( swap_web_entry * insn_entry , rtx insn ) { unsigned uid = INSN_UID ( insn ) ; if ( ! insn_entry [ uid ] . is_swap || insn_entry [ uid ] . is_load ) return false ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref use ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( ! def_link || def_link -> next ) return false ; rtx def_insn = DF_REF_INSN ( def_link -> ref ) ; unsigned uid2 = INSN_UID ( def_insn ) ; if ( ! insn_entry [ uid2 ] . is_load || ! insn_entry [ uid2 ] . is_swap ) return false ; rtx body = PATTERN ( def_insn ) ; if ( GET_CODE ( body ) != SET || GET_CODE ( SET_SRC ( body ) ) != VEC_SELECT || GET_CODE ( XEXP ( SET_SRC ( body ) , 0 ) ) != MEM ) return false ; rtx mem = XEXP ( SET_SRC ( body ) , 0 ) ; rtx base_reg = XEXP ( mem , 0 ) ; df_ref base_use ; insn_info = DF_INSN_INFO_GET ( def_insn ) ; FOR_EACH_INSN_INFO_USE ( base_use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( base_use ) , base_reg ) ) continue ; struct df_link * base_def_link = DF_REF_CHAIN ( base_use ) ; if ( ! base_def_link || base_def_link -> next ) return false ; rtx tocrel_insn = DF_REF_INSN ( base_def_link -> ref ) ; rtx tocrel_body = PATTERN ( tocrel_insn ) ; rtx base , offset ; if ( GET_CODE ( tocrel_body ) != SET ) return false ; rtx tocrel_expr = SET_SRC ( tocrel_body ) ; if ( GET_CODE ( tocrel_expr ) == MEM ) tocrel_expr = XEXP ( tocrel_expr , 0 ) ; if ( ! toc_relative_expr_p ( tocrel_expr , false ) ) return false ; split_const ( XVECEXP ( tocrel_base , 0 , 0 ) , & base , & offset ) ; if ( GET_CODE ( base ) != SYMBOL_REF || ! CONSTANT_POOL_ADDRESS_P ( base ) ) return false ; } } return true ; } </s>

Return TRUE if insn is a swap fed by a load from the constant pool .


<s> void s390_output_pool_entry ( rtx exp , machine_mode mode , unsigned int align ) { switch ( GET_MODE_CLASS ( mode ) ) { case MODE_FLOAT : case MODE_DECIMAL_FLOAT : gcc_assert ( GET_CODE ( exp ) == CONST_DOUBLE ) ; assemble_real ( * CONST_DOUBLE_REAL_VALUE ( exp ) , as_a < scalar_float_mode > ( mode ) , align ) ; break ; case MODE_INT : assemble_integer ( exp , GET_MODE_SIZE ( mode ) , align , 1 ) ; mark_symbol_refs_as_used ( exp ) ; break ; case MODE_VECTOR_INT : case MODE_VECTOR_FLOAT : { int i ; machine_mode inner_mode ; gcc_assert ( GET_CODE ( exp ) == CONST_VECTOR ) ; inner_mode = GET_MODE_INNER ( GET_MODE ( exp ) ) ; for ( i = 0 ; i < XVECLEN ( exp , 0 ) ; i ++ ) s390_output_pool_entry ( XVECEXP ( exp , 0 , i ) , inner_mode , i == 0 ? align : GET_MODE_BITSIZE ( inner_mode ) ) ; } break ; default : gcc_unreachable ( ) ; } } </s>

Output the constant pool entry EXP in mode MODE with alignment ALIGN .


<s>
bool
HexagonPacketizer
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
auto
&
HST
=
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
;
if
(
DisablePacketizer
||
!
HST
.
usePackets
(
)
||
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
HII
=
HST
.
getInstrInfo
(
)
;
HRI
=
HST
.
getRegisterInfo
(
)
;
auto
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
auto
*
AA
=
&
getAnalysis
<
AAResultsWrapperPass
>
(
)
.
getAAResults
(
)
;
auto
*
MBPI
=
&
getAnalysis
<
MachineBranchProbabilityInfo
>
(
)
;
if
(
EnableGenAllInsnClass
)
HII
->
genAllInsnTimingClasses
(
MF
)
;
HexagonPacketizerList
Packetizer
(
MF
,
MLI
,
AA
,
MBPI
)
;
assert
(
Packetizer
.
getResourceTracker
(
)
&&
"Empty DFA table!"
)
;
for
(
auto
&
MB
:
MF
)
{
auto
End
=
MB
.
end
(
)
;
auto
MI
=
MB
.
begin
(
)
;
while
(
MI
!=
End
)
{
auto
NextI
=
std
::
next
(
MI
)
;
if
(
MI
->
isKill
(
)
)
{
MB
.
erase
(
MI
)
;
End
=
MB
.
end
(
)
;
}
MI
=
NextI
;
}
}
for
(
auto
&
MB
:
MF
)
{
auto
Begin
=
MB
.
begin
(
)
,
End
=
MB
.
end
(
)
;
while
(
Begin
!=
End
)
{
MachineBasicBlock
::
iterator
RB
=
Begin
;
while
(
RB
!=
End
&&
HII
->
isSchedulingBoundary
(
*
RB
,
&
MB
,
MF
)
)
++
RB
;
MachineBasicBlock
::
iterator
RE
=
RB
;
while
(
RE
!=
End
&&
!
HII
->
isSchedulingBoundary
(
*
RE
,
&
MB
,
MF
)
)
++
RE
;
if
(
RE
!=
End
)
++
RE
;
if
(
RB
!=
End
)
Packetizer
.
PacketizeMIs
(
&
MB
,
RB
,
RE
)
;
Begin
=
RE
;
}
}
Packetizer
.
unpacketizeSoloInstrs
(
MF
)
;
return
true
;
}
</s>

Hexagon
Hexagon
Hexagon
Hexagon
"Empty DFA table!"


<s>
virtual
const
char
*
getPassName
(
)
const
LLVM_OVERRIDE
{
return
"ARM Assembly / Object Emitter"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> enum machine_mode mmix_select_cc_mode ( RTX_CODE op , rtx x , rtx y ATTRIBUTE_UNUSED ) { if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) { if ( op == ORDERED || op == UNORDERED || op == UNGE || op == UNGT || op == UNLE || op == UNLT ) return CC_FUNmode ; if ( op == EQ || op == NE ) return CC_FPEQmode ; return CC_FPmode ; } if ( op == GTU || op == LTU || op == GEU || op == LEU ) return CC_UNSmode ; return CCmode ; } </s>


<s> static std :: unique_ptr < FISCOperand > CreateMem ( unsigned Base , const MCExpr * Off , SMLoc S , SMLoc E ) { auto Op = make_unique < FISCOperand > ( k_Memory ) ; Op -> Mem . Base = Base ; Op -> Mem . Off = Off ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>


<s> int pa_insn_refs_are_delayed ( rtx_insn * insn ) { return ( ( NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) != SEQUENCE && GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER && get_attr_type ( insn ) == TYPE_MILLI ) ) ; } </s>

Return nonzero if references for INSN are delayed . Millicode insns are actually function calls with some special constraints on arguments and register usage . Millicode calls always expect their arguments in the integer argument registers , and always return their result in % r29 ( ret1 ) . They are expected to clobber their arguments , % r1 , % r29 , and the return pointer which is % r31 on 32-bit and % r2 on 64-bit , and nothing else . This function tells reorg that the references to arguments and millicode calls do not appear to happen until after the millicode call . This allows reorg to put insns which set the argument registers into the delay slot of the millicode call -- thus they act more like traditional CALL_INSNs . Note we can not consider side effects of the insn to be delayed because the branch and link insn will clobber the return pointer . If we happened to use the return pointer in the delay slot of the call , then we lose . get_attr_type will try to recognize the given insn , so make sure to filter out things it will not accept -- SEQUENCE , USE and CLOBBER insns in particular .


<s> static void mips_expand_vi_constant ( machine_mode vmode , unsigned nelt , rtx target , rtx vals ) { rtvec vec = shallow_copy_rtvec ( XVEC ( vals , 0 ) ) ; unsigned i ; for ( i = 0 ; i < nelt ; ++ i ) { if ( ! mips_constant_elt_p ( RTVEC_ELT ( vec , i ) ) ) RTVEC_ELT ( vec , i ) = const0_rtx ; } emit_move_insn ( target , gen_rtx_CONST_VECTOR ( vmode , vec ) ) ; } </s>

A subroutine of mips_expand_vec_init , replacing all of the non-constant elements of VALS with zeros , copy the constant vector to TARGET .


<s> static bool is_load_insn ( rtx insn , rtx * load_mem ) { if ( ! insn || ! INSN_P ( insn ) ) return false ; if ( CALL_P ( insn ) ) return false ; return is_load_insn1 ( PATTERN ( insn ) , load_mem ) ; } </s>


<s>
static
const
char
*
avr_out_movqi_r_mr_reg_disp_tiny
(
rtx_insn
*
insn
,
rtx
op
[
]
,
int
*
plen
)
{
rtx
dest
=
op
[
0
]
;
rtx
src
=
op
[
1
]
;
rtx
x
=
XEXP
(
src
,
0
)
;
avr_asm_len
(
TINY_ADIW
(
%
I1
,
%
J1
,
%
o1
)
CR_TAB
"ld %0,%b1"
,
op
,
plen
,
3
)
;
if
(
!
reg_overlap_mentioned_p
(
dest
,
XEXP
(
x
,
0
)
)
&&
!
reg_unused_after
(
insn
,
XEXP
(
x
,
0
)
)
)
avr_asm_len
(
TINY_SBIW
(
%
I1
,
%
J1
,
%
o1
)
,
op
,
plen
,
2
)
;
return
""
;
}
</s>

Same as out_movqi_r_mr , but TINY does not have ADIW or SBIW


<s> const TargetRegisterClass * SIInstrInfo :: getOpRegClass ( const MachineInstr & MI , unsigned OpNo ) const { const MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const MCInstrDesc & Desc = get ( MI . getOpcode ( ) ) ; if ( MI . isVariadic ( ) || OpNo >= Desc . getNumOperands ( ) || Desc . OpInfo [ OpNo ] . RegClass == - 1 ) { unsigned Reg = MI . getOperand ( OpNo ) . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) return MRI . getRegClass ( Reg ) ; return RI . getPhysRegClass ( Reg ) ; } unsigned RCID = Desc . OpInfo [ OpNo ] . RegClass ; return RI . getRegClass ( RCID ) ; } </s>

Return the correct register class for OpNo .


<s> bool X86FastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { const Value * Ptr = LI -> getPointerOperand ( ) ; X86AddressMode AM ; if ( ! X86SelectAddress ( Ptr , AM ) ) return false ; const X86InstrInfo & XII = ( const X86InstrInfo & ) TII ; unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; SmallVector < MachineOperand , 8 > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , * MI , OpNo , AddrOps , FuncInfo . InsertPt , Size , LI -> getAlign ( ) , true ) ; if ( ! Result ) return false ; unsigned OperandNo = 0 ; for ( MachineInstr :: mop_iterator I = Result -> operands_begin ( ) , E = Result -> operands_end ( ) ; I != E ; ++ I , ++ OperandNo ) { MachineOperand & MO = * I ; if ( ! MO . isReg ( ) || MO . isDef ( ) || MO . getReg ( ) != AM . IndexReg ) continue ; Register IndexReg = constrainOperandRegClass ( Result -> getDesc ( ) , MO . getReg ( ) , OperandNo ) ; if ( IndexReg == MO . getReg ( ) ) continue ; MO . setReg ( IndexReg ) ; } uint32_t Hash = MI -> getPrototypeHash ( ) ; if ( Hash ) Result -> setPrototypeHash ( MI -> getPrototypeHash ( ) ) ; Result -> addMemOperand ( * FuncInfo . MF , createMachineMemOperandFor ( LI ) ) ; Result -> cloneInstrSymbols ( * FuncInfo . MF , * MI ) ; MachineBasicBlock :: iterator I ( MI ) ; removeDeadCode ( I , std :: next ( I ) ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> static void frv_extract_membar ( struct frv_io * io , rtx_insn * insn ) { extract_insn ( insn ) ; io -> type = ( enum frv_io_type ) INTVAL ( recog_data . operand [ 2 ] ) ; io -> const_address = INTVAL ( recog_data . operand [ 1 ] ) ; io -> var_address = XEXP ( recog_data . operand [ 0 ] , 0 ) ; } </s>

Fill IO with information about the load or store associated with membar instruction INSN .


<s> static bool alg_usable_p ( enum stringop_alg alg , bool memset , bool have_as ) { if ( alg == no_stringop ) return false ; if ( alg == vector_loop ) return TARGET_SSE || TARGET_AVX ; if ( alg == rep_prefix_1_byte || alg == rep_prefix_4_byte || alg == rep_prefix_8_byte ) { if ( have_as ) return false ; if ( fixed_regs [ CX_REG ] || fixed_regs [ DI_REG ] || ( memset ? fixed_regs [ AX_REG ] : fixed_regs [ SI_REG ] ) ) return false ; } return true ; } </s>

Return true if ALG can be used in current context . Assume we expand memset if MEMSET is true .


<s> void PPC64LinuxTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; } </s>

This method must be called before any actual lowering is done .


<s> static tree alpha_fold_builtin_insxx ( tree op [ ] , unsigned HOST_WIDE_INT opint [ ] , long op_const , unsigned HOST_WIDE_INT bytemask , bool is_high ) { if ( ( op_const & 1 ) && opint [ 0 ] == 0 ) return build_int_cst ( long_integer_type_node , 0 ) ; if ( op_const & 2 ) { unsigned HOST_WIDE_INT temp , loc , byteloc ; tree * zap_op = NULL ; loc = opint [ 1 ] & 7 ; if ( BYTES_BIG_ENDIAN ) loc ^= 7 ; bytemask <<= loc ; temp = opint [ 0 ] ; if ( is_high ) { byteloc = ( 64 - ( loc * 8 ) ) & 0x3f ; if ( byteloc == 0 ) zap_op = op ; else temp >>= byteloc ; bytemask >>= 8 ; } else { byteloc = loc * 8 ; if ( byteloc == 0 ) zap_op = op ; else temp <<= byteloc ; } opint [ 0 ] = temp ; opint [ 1 ] = bytemask ; return alpha_fold_builtin_zapnot ( zap_op , opint , op_const ) ; } return NULL ; } </s>

Fold the builtins for the INS family of instructions .


<s> void ARMDAGToDAGISel :: PreprocessISelDAG ( ) { if ( ! Subtarget -> hasV6T2Ops ( ) ) return ; bool isThumb2 = Subtarget -> isThumb ( ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( N -> getOpcode ( ) != ISD :: ADD ) continue ; SDValue N0 = N -> getOperand ( 0 ) ; SDValue N1 = N -> getOperand ( 1 ) ; unsigned And_imm = 0 ; if ( ! isOpcWithIntImmediate ( N1 . getNode ( ) , ISD :: AND , And_imm ) ) { if ( isOpcWithIntImmediate ( N0 . getNode ( ) , ISD :: AND , And_imm ) ) std :: swap ( N0 , N1 ) ; } if ( ! And_imm ) continue ; unsigned TZ = countTrailingZeros ( And_imm ) ; if ( TZ != 1 && TZ != 2 ) continue ; And_imm >>= TZ ; if ( And_imm & ( And_imm + 1 ) ) continue ; SDValue Srl = N1 . getOperand ( 0 ) ; unsigned Srl_imm = 0 ; if ( ! isOpcWithIntImmediate ( Srl . getNode ( ) , ISD :: SRL , Srl_imm ) || ( Srl_imm <= 2 ) ) continue ; SDValue CPTmp0 ; SDValue CPTmp1 ; SDValue CPTmp2 ; if ( isThumb2 ) { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) ) continue ; } else { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) || SelectRegShifterOperand ( N0 , CPTmp0 , CPTmp1 , CPTmp2 ) ) continue ; } Srl = CurDAG -> getNode ( ISD :: SRL , SDLoc ( Srl ) , MVT :: i32 , Srl . getOperand ( 0 ) , CurDAG -> getConstant ( Srl_imm + TZ , SDLoc ( Srl ) , MVT :: i32 ) ) ; N1 = CurDAG -> getNode ( ISD :: AND , SDLoc ( N1 ) , MVT :: i32 , Srl , CurDAG -> getConstant ( And_imm , SDLoc ( Srl ) , MVT :: i32 ) ) ; N1 = CurDAG -> getNode ( ISD :: SHL , SDLoc ( N1 ) , MVT :: i32 , N1 , CurDAG -> getConstant ( TZ , SDLoc ( Srl ) , MVT :: i32 ) ) ; CurDAG -> UpdateNodeOperands ( N , N0 , N1 ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> void print ( raw_ostream & OS ) const override { switch ( Kind ) { case Token : OS << "Tok:" << Tok . Tok ; break ; case Integer : OS << "Int:" << Int . Val ; break ; case Float : OS << "Flt:" << Flt . Val ; break ; case Symbol : OS << "Sym:" << Sym . Exp ; break ; } } </s>

print - Print a debug representation of the operand to the given stream .


"all ColorKinds should be handled by the switch above"

Dump the plan to stderr ( for debugging ) .


<s> static bool arm_function_in_section_p ( tree decl , section * section ) { if ( ! decl_binds_to_current_def_p ( decl ) ) return false ; if ( ! DECL_SECTION_NAME ( decl ) ) { if ( flag_function_sections || DECL_COMDAT_GROUP ( decl ) ) return false ; } return function_section ( decl ) == section ; } </s>

Return true if DECL is known to be linked into section SECTION .


<s> const uint32_t * AArch64RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return CSR_AArch64_NoRegs_RegMask ; if ( CC == CallingConv :: AnyReg ) return CSR_AArch64_AllRegs_RegMask ; if ( CC == CallingConv :: CXX_FAST_TLS ) return CSR_AArch64_CXX_TLS_Darwin_RegMask ; else return CSR_AArch64_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


"X86-specific target pass should not be run without a target "

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> void AMDGPUPassConfig :: addCodeGenPrepare ( ) { if ( TM -> getTargetTriple ( ) . getArch ( ) == Triple :: amdgcn ) addPass ( createAMDGPUAnnotateKernelFeaturesPass ( ) ) ; if ( TM -> getTargetTriple ( ) . getArch ( ) == Triple :: amdgcn && EnableLowerKernelArguments ) addPass ( createAMDGPULowerKernelArgumentsPass ( ) ) ; addPass ( & AMDGPUPerfHintAnalysisID ) ; TargetPassConfig :: addCodeGenPrepare ( ) ; if ( EnableLoadStoreVectorizer . getNumOccurrences ( ) ? EnableLoadStoreVectorizer : TM -> getOptLevel ( ) > CodeGenOpt :: Less ) addPass ( createLoadStoreVectorizerPass ( ) ) ; addPass ( createLowerSwitchPass ( ) ) ; } </s>

Add pass to prepare the LLVM IR for code generation .


<s> void SITargetLowering :: AdjustInstrPostInstrSelection ( MachineInstr * MI , SDNode * Node ) const { const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; if ( TII -> isMIMG ( MI -> getOpcode ( ) ) ) { unsigned VReg = MI -> getOperand ( 0 ) . getReg ( ) ; unsigned Writemask = MI -> getOperand ( 1 ) . getImm ( ) ; unsigned BitsSet = 0 ; for ( unsigned i = 0 ; i < 4 ; ++ i ) BitsSet += Writemask & ( 1 << i ) ? 1 : 0 ; const TargetRegisterClass * RC ; switch ( BitsSet ) { default : return ; case 1 : RC = & AMDGPU :: VReg_32RegClass ; break ; case 2 : RC = & AMDGPU :: VReg_64RegClass ; break ; case 3 : RC = & AMDGPU :: VReg_96RegClass ; break ; } unsigned NewOpcode = TII -> getMaskedMIMGOp ( MI -> getOpcode ( ) , BitsSet ) ; MI -> setDesc ( TII -> get ( NewOpcode ) ) ; MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; MRI . setRegClass ( VReg , RC ) ; return ; } int NoRetAtomicOp = AMDGPU :: getAtomicNoRetOp ( MI -> getOpcode ( ) ) ; if ( NoRetAtomicOp != - 1 ) { if ( ! Node -> hasAnyUseOfValue ( 0 ) ) { MI -> setDesc ( TII -> get ( NoRetAtomicOp ) ) ; MI -> RemoveOperand ( 0 ) ; } return ; } } </s>

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


<s>
static
void
bpf_compute_frame_layout
(
void
)
{
int
stack_alignment
=
STACK_BOUNDARY
/
BITS_PER_UNIT
;
int
padding_locals
,
regno
;
cfun
->
machine
->
local_vars_size
=
get_frame_size
(
)
;
padding_locals
=
cfun
->
machine
->
local_vars_size
%
stack_alignment
;
if
(
padding_locals
)
padding_locals
=
stack_alignment
padding_locals
;
cfun
->
machine
->
local_vars_size
+=
padding_locals
;
if
(
TARGET_XBPF
)
{
for
(
regno
=
0
;
regno
<
FIRST_PSEUDO_REGISTER
;
regno
++
)
if
(
(
df_regs_ever_live_p
(
regno
)
&&
!
call_used_or_fixed_reg_p
(
regno
)
)
||
(
cfun
->
calls_alloca
&&
regno
==
STACK_POINTER_REGNUM
)
)
cfun
->
machine
->
callee_saved_reg_size
+=
8
;
}
if
(
(
cfun
->
machine
->
local_vars_size
+
cfun
->
machine
->
callee_saved_reg_size
)
>
bpf_frame_limit
)
{
static
int
stack_limit_exceeded
=
0
;
if
(
!
stack_limit_exceeded
)
error
(
"eBPF stack limit exceeded"
)
;
stack_limit_exceeded
=
1
;
}
}
</s>

Compute the size of the function 's stack frame , including the local area and the register-save area .


<s>
MCDisassembler
::
DecodeStatus
WebAssemblyDisassembler
::
onSymbolStart
(
StringRef
Name
,
uint64_t
&
Size
,
ArrayRef
<
uint8_t
>
Bytes
,
uint64_t
Address
,
raw_ostream
&
VStream
,
raw_ostream
&
CStream
)
const
{
Size
=
0
;
if
(
Address
==
0
)
{
int64_t
FunctionCount
;
if
(
!
nextLEB
(
FunctionCount
,
Bytes
,
Size
,
false
)
)
return
MCDisassembler
::
Fail
;
outs
(
)
<<
"        # "
<<
FunctionCount
<<
" functions in section."
;
}
else
{
int64_t
BodySize
,
LocalEntryCount
;
if
(
!
nextLEB
(
BodySize
,
Bytes
,
Size
,
false
)
||
!
nextLEB
(
LocalEntryCount
,
Bytes
,
Size
,
false
)
)
return
MCDisassembler
::
Fail
;
if
(
LocalEntryCount
)
{
outs
(
)
<<
"        .local "
;
for
(
int64_t
I
=
0
;
I
<
LocalEntryCount
;
I
++
)
{
int64_t
Count
,
Type
;
if
(
!
nextLEB
(
Count
,
Bytes
,
Size
,
false
)
||
!
nextLEB
(
Type
,
Bytes
,
Size
,
false
)
)
return
MCDisassembler
::
Fail
;
for
(
int64_t
J
=
0
;
J
<
Count
;
J
++
)
{
if
(
I
||
J
)
outs
(
)
<<
", "
;
outs
(
)
<<
WebAssembly
::
anyTypeToString
(
Type
)
;
}
}
}
}
outs
(
)
<<
"\n"
;
return
MCDisassembler
::
Success
;
}
</s>

Used to perform separate target specific disassembly for a particular symbol .

WebAssembly
WebAssembly
0
0
"        # "
" functions in section."
"        .local "
0
0
", "
WebAssembly::anyTypeToString
"\n"


<s> void X86InstrInfo :: breakPartialRegDependency ( MachineBasicBlock :: iterator MI , unsigned OpNum , const TargetRegisterInfo * TRI ) const { unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; if ( MI -> killsRegister ( Reg , TRI ) ) return ; if ( X86 :: VR128RegClass . contains ( Reg ) ) { bool HasAVX = Subtarget . hasAVX ( ) ; unsigned Opc = HasAVX ? X86 :: VXORPSrr : X86 :: XORPSrr ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , get ( Opc ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; } else if ( X86 :: VR256RegClass . contains ( Reg ) ) { unsigned XReg = TRI -> getSubReg ( Reg , X86 :: sub_xmm ) ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , get ( X86 :: VXORPSrr ) , XReg ) . addReg ( XReg , RegState :: Undef ) . addReg ( XReg , RegState :: Undef ) . addReg ( Reg , RegState :: ImplicitDefine ) ; } else return ; MI -> addRegisterKilled ( Reg , TRI , true ) ; } </s>

Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum .


<s> const MipsSubtarget * MipsTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool hasMips16Attr = ! F . getFnAttribute ( "mips16" ) . hasAttribute ( Attribute :: None ) ; bool hasNoMips16Attr = ! F . getFnAttribute ( "nomips16" ) . hasAttribute ( Attribute :: None ) ; bool HasMicroMipsAttr = ! F . getFnAttribute ( "micromips" ) . hasAttribute ( Attribute :: None ) ; bool HasNoMicroMipsAttr = ! F . getFnAttribute ( "nomicromips" ) . hasAttribute ( Attribute :: None ) ; bool softFloat = F . hasFnAttribute ( "use-soft-float" ) && F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( hasMips16Attr ) FS += FS . empty ( ) ? "+mips16" : ",+mips16" ; else if ( hasNoMips16Attr ) FS += FS . empty ( ) ? "-mips16" : ",-mips16" ; if ( HasMicroMipsAttr ) FS += FS . empty ( ) ? "+micromips" : ",+micromips" ; else if ( HasNoMicroMipsAttr ) FS += FS . empty ( ) ? "-micromips" : ",-micromips" ; if ( softFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < MipsSubtarget > ( TargetTriple , CPU , FS , isLittle , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

Mips Mips Mips "target-cpu" "target-features" Mips "mips16" Mips "nomips16" Mips "micromips" Mips "nomicromips" "use-soft-float" "use-soft-float" "true" Mips "+mips16" ",+mips16" Mips "-mips16" ",-mips16" Mips "+micromips" ",+micromips" Mips "-micromips" ",-micromips" "+soft-float" ",+soft-float" Mips


<s> void RISCVPassConfig :: addPreEmitPass2 ( ) { addPass ( createRISCVExpandPseudoPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createRISCVPulpHWLoopsPass ( ) ) ; } } </s>

Targets may add passes immediately before machine code is emitted in this callback .


<s> static bool tilegx_frame_pointer_required ( void ) { return crtl -> calls_eh_return || cfun -> calls_alloca ; } </s>


<s> void visium_expand_prologue ( void ) { const int frame_size = visium_compute_frame_size ( get_frame_size ( ) ) ; const int save_area_size = current_frame_info . save_area_size ; const int reg_size1 = current_frame_info . reg_size1 ; const int max_reg1 = current_frame_info . max_reg1 ; const int reg_size2 = current_frame_info . reg_size2 ; const int var_size = current_frame_info . var_size ; const int save_fp = current_frame_info . save_fp ; const int save_lr = current_frame_info . save_lr ; const int lr_slot = current_frame_info . lr_slot ; const int local_frame_offset = ( save_fp + save_lr + lr_slot ) * UNITS_PER_WORD ; const int combine = current_frame_info . combine ; int reg_size ; int first_reg ; int fsize ; visium_frame_size = frame_size ; if ( flag_stack_usage_info ) current_function_static_stack_size = frame_size ; if ( reg_size2 ) { visium_save_regs ( reg_size1 + save_area_size , reg_size1 , 0 , max_reg1 ) ; reg_size = reg_size2 ; first_reg = max_reg1 + 1 ; fsize = local_frame_offset + var_size + reg_size2 ; } else { reg_size = reg_size1 ; first_reg = 0 ; fsize = local_frame_offset + var_size + reg_size1 + save_area_size ; } if ( reg_size && ! combine ) visium_save_regs ( fsize - local_frame_offset - var_size , reg_size , first_reg , FIRST_PSEUDO_REGISTER - 1 ) ; if ( reg_size && combine ) visium_save_regs ( fsize , local_frame_offset + var_size + reg_size , first_reg , FIRST_PSEUDO_REGISTER - 1 ) ; else if ( fsize ) { const int alloc_size = reg_size ? local_frame_offset + var_size : fsize ; if ( alloc_size > 65535 ) { rtx tmp = gen_rtx_REG ( SImode , PROLOGUE_TMP_REGNUM ) , insn ; emit_insn ( gen_movsi ( tmp , GEN_INT ( alloc_size ) ) ) ; insn = emit_frame_insn ( gen_subsi3_flags ( stack_pointer_rtx , stack_pointer_rtx , tmp ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( - alloc_size ) ) ) ) ; } else emit_frame_insn ( gen_addsi3_flags ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - alloc_size ) ) ) ; } if ( save_fp ) emit_frame_insn ( gen_movsi ( gen_frame_mem ( SImode , stack_pointer_rtx ) , hard_frame_pointer_rtx ) ) ; if ( frame_pointer_needed ) emit_frame_insn ( gen_stack_save ( ) ) ; if ( save_lr ) { rtx base_rtx , mem ; if ( cfun -> machine -> frame_needed ) base_rtx = hard_frame_pointer_rtx ; else base_rtx = stack_pointer_rtx ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , base_rtx , save_fp * UNITS_PER_WORD ) ) ; emit_frame_insn ( gen_movsi ( mem , gen_rtx_REG ( SImode , LINK_REGNUM ) ) ) ; } } </s>

This function generates the code for function entry .


<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < 512 > Key ; Key . reserve ( CPU . size ( ) + FS . size ( ) ) ; Key += CPU ; Key += FS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) Key += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; unsigned CPUFSWidth = Key . size ( ) ; unsigned PreferVectorWidthOverride = 0 ; if ( F . hasFnAttribute ( "prefer-vector-width" ) ) { StringRef Val = F . getFnAttribute ( "prefer-vector-width" ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( 0 , Width ) ) { Key += ",prefer-vector-width=" ; Key += Val ; PreferVectorWidthOverride = Width ; } } unsigned RequiredVectorWidth = UINT32_MAX ; if ( F . hasFnAttribute ( "required-vector-width" ) ) { StringRef Val = F . getFnAttribute ( "required-vector-width" ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( 0 , Width ) ) { Key += ",required-vector-width=" ; Key += Val ; RequiredVectorWidth = Width ; } } FS = Key . slice ( CPU . size ( ) , CPUFSWidth ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < X86Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride , PreferVectorWidthOverride , RequiredVectorWidth ) ; } return I . get ( ) ; } </s>


<s> bool SIInstrInfo :: moveFlatAddrToVGPR ( MachineInstr & Inst ) const { unsigned Opc = Inst . getOpcode ( ) ; int OldSAddrIdx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: saddr ) ; if ( OldSAddrIdx < 0 ) return false ; assert ( isSegmentSpecificFLAT ( Inst ) ) ; int NewOpc = AMDGPU :: getGlobalVaddrOp ( Opc ) ; if ( NewOpc < 0 ) NewOpc = AMDGPU :: getFlatScratchInstSVfromSS ( Opc ) ; if ( NewOpc < 0 ) return false ; MachineRegisterInfo & MRI = Inst . getMF ( ) -> getRegInfo ( ) ; MachineOperand & SAddr = Inst . getOperand ( OldSAddrIdx ) ; if ( RI . isSGPRReg ( MRI , SAddr . getReg ( ) ) ) return false ; int NewVAddrIdx = AMDGPU :: getNamedOperandIdx ( NewOpc , AMDGPU :: OpName :: vaddr ) ; if ( NewVAddrIdx < 0 ) return false ; int OldVAddrIdx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: vaddr ) ; MachineInstr * VAddrDef = nullptr ; if ( OldVAddrIdx >= 0 ) { MachineOperand & VAddr = Inst . getOperand ( OldVAddrIdx ) ; VAddrDef = MRI . getUniqueVRegDef ( VAddr . getReg ( ) ) ; if ( ! VAddrDef || VAddrDef -> getOpcode ( ) != AMDGPU :: V_MOV_B32_e32 || ! VAddrDef -> getOperand ( 1 ) . isImm ( ) || VAddrDef -> getOperand ( 1 ) . getImm ( ) != 0 ) return false ; } const MCInstrDesc & NewDesc = get ( NewOpc ) ; Inst . setDesc ( NewDesc ) ; if ( OldVAddrIdx == NewVAddrIdx ) { MachineOperand & NewVAddr = Inst . getOperand ( NewVAddrIdx ) ; MRI . removeRegOperandFromUseList ( & NewVAddr ) ; MRI . moveOperands ( & NewVAddr , & SAddr , 1 ) ; Inst . RemoveOperand ( OldSAddrIdx ) ; MRI . removeRegOperandFromUseList ( & NewVAddr ) ; MRI . addRegOperandToUseList ( & NewVAddr ) ; } else { assert ( OldSAddrIdx == NewVAddrIdx ) ; if ( OldVAddrIdx >= 0 ) { int NewVDstIn = AMDGPU :: getNamedOperandIdx ( NewOpc , AMDGPU :: OpName :: vdst_in ) ; if ( NewVDstIn != - 1 ) { int OldVDstIn = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: vdst_in ) ; Inst . untieRegOperand ( OldVDstIn ) ; } Inst . RemoveOperand ( OldVAddrIdx ) ; if ( NewVDstIn != - 1 ) { int NewVDst = AMDGPU :: getNamedOperandIdx ( NewOpc , AMDGPU :: OpName :: vdst ) ; Inst . tieOperands ( NewVDst , NewVDstIn ) ; } } } if ( VAddrDef && MRI . use_nodbg_empty ( VAddrDef -> getOperand ( 0 ) . getReg ( ) ) ) VAddrDef -> eraseFromParent ( ) ; return true ; } </s>

Change SADDR form of a FLAT Inst to its VADDR form if saddr operand was moved to VGPR .


<s> bool PPCTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { if ( ! VT . isSimple ( ) || ! Subtarget . hasVSX ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case MVT :: f32 : case MVT :: f64 : if ( Subtarget . hasPrefixInstrs ( ) ) { return true ; } LLVM_FALLTHROUGH ; case MVT :: ppcf128 : return Imm . isPosZero ( ) ; } } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s>
void
X86InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
Register
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
assert
(
MF
.
getFrameInfo
(
)
.
getObjectSize
(
FrameIdx
)
>=
TRI
->
getSpillSize
(
*
RC
)
&&
"Stack slot too small for store"
)
;
if
(
RC
->
getID
(
)
==
X86
::
TILERegClassID
)
{
unsigned
Opc
=
X86
::
TILESTORED
;
MachineRegisterInfo
&
RegInfo
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
Register
VirtReg
=
RegInfo
.
createVirtualRegister
(
&
X86
::
GR64_NOSPRegClass
)
;
BuildMI
(
MBB
,
MI
,
DebugLoc
(
)
,
get
(
X86
::
MOV64ri
)
,
VirtReg
)
.
addImm
(
64
)
;
MachineInstr
*
NewMI
=
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DebugLoc
(
)
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
MachineOperand
&
MO
=
NewMI
->
getOperand
(
2
)
;
MO
.
setReg
(
VirtReg
)
;
MO
.
setIsKill
(
true
)
;
}
else
if
(
RC
->
getID
(
)
==
X86
::
TILECFGRegClassID
)
{
unsigned
Opc
=
X86
::
PSTTILECFG
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DebugLoc
(
)
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
}
else
{
unsigned
Alignment
=
std
::
max
<
uint32_t
>
(
TRI
->
getSpillSize
(
*
RC
)
,
16
)
;
bool
isAligned
=
(
Subtarget
.
getFrameLowering
(
)
->
getStackAlign
(
)
>=
Alignment
)
||
RI
.
canRealignStack
(
MF
)
;
unsigned
Opc
=
getStoreRegOpcode
(
SrcReg
,
RC
,
isAligned
,
Subtarget
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DebugLoc
(
)
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool FixFunctionBitcasts :: runOnModule ( Module & M ) { SmallVector < std :: pair < Use * , Function * > , 0 > Uses ; SmallPtrSet < Constant * , 2 > ConstantBCs ; for ( Function & F : M ) FindUses ( & F , F , Uses , ConstantBCs ) ; DenseMap < std :: pair < Function * , FunctionType * > , Function * > Wrappers ; for ( auto & UseFunc : Uses ) { Use * U = UseFunc . first ; Function * F = UseFunc . second ; PointerType * PTy = cast < PointerType > ( U -> get ( ) -> getType ( ) ) ; FunctionType * Ty = dyn_cast < FunctionType > ( PTy -> getElementType ( ) ) ; if ( ! Ty ) continue ; if ( Ty -> isVarArg ( ) || F -> isVarArg ( ) ) continue ; auto Pair = Wrappers . insert ( std :: make_pair ( std :: make_pair ( F , Ty ) , nullptr ) ) ; if ( Pair . second ) Pair . first -> second = CreateWrapper ( F , Ty ) ; Function * Wrapper = Pair . first -> second ; if ( ! Wrapper ) continue ; if ( isa < Constant > ( U -> get ( ) ) ) U -> get ( ) -> replaceAllUsesWith ( Wrapper ) ; else U -> set ( Wrapper ) ; } return true ; } </s>


<s> pure_scalable_type_info :: analysis_result pure_scalable_type_info :: analyze_array ( const_tree type ) { pure_scalable_type_info element_info ; analysis_result result = element_info . analyze ( TREE_TYPE ( type ) ) ; if ( result != IS_PST ) return result ; tree nelts_minus_one = array_type_nelts ( type ) ; if ( ! tree_fits_uhwi_p ( nelts_minus_one ) ) return DOESNT_MATTER ; unsigned HOST_WIDE_INT count = tree_to_uhwi ( nelts_minus_one ) ; if ( count > MAX_PIECES ) return DOESNT_MATTER ; count += 1 ; if ( count * element_info . pieces . length ( ) > MAX_PIECES ) return DOESNT_MATTER ; poly_uint64 element_bytes ; if ( ! poly_int_tree_p ( TYPE_SIZE_UNIT ( TREE_TYPE ( type ) ) , & element_bytes ) ) gcc_unreachable ( ) ; gcc_assert ( ! element_info . pieces . is_empty ( ) ) ; for ( unsigned int i = 0 ; i < count ; ++ i ) for ( unsigned int j = 0 ; j < element_info . pieces . length ( ) ; ++ j ) { piece p = element_info . pieces [ j ] ; p . offset += i * element_bytes ; add_piece ( p ) ; } return IS_PST ; } </s>

Subroutine of analyze for handling ARRAY_TYPEs .


<s> void rvexInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << '$' << StringRef ( getRegisterName ( RegNo ) ) . lower ( ) ; } </s>


<s> bool AArch64TargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , unsigned Intrinsic ) const { switch ( Intrinsic ) { case Intrinsic :: arm_neon_vld1 : case Intrinsic :: arm_neon_vld2 : case Intrinsic :: arm_neon_vld3 : case Intrinsic :: arm_neon_vld4 : case Intrinsic :: aarch64_neon_vld1x2 : case Intrinsic :: aarch64_neon_vld1x3 : case Intrinsic :: aarch64_neon_vld1x4 : case Intrinsic :: arm_neon_vld2lane : case Intrinsic :: arm_neon_vld3lane : case Intrinsic :: arm_neon_vld4lane : { Info . opc = ISD :: INTRINSIC_W_CHAIN ; uint64_t NumElts = getDataLayout ( ) -> getTypeAllocSize ( I . getType ( ) ) / 8 ; Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , MVT :: i64 , NumElts ) ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Value * AlignArg = I . getArgOperand ( I . getNumArgOperands ( ) - 1 ) ; Info . align = cast < ConstantInt > ( AlignArg ) -> getZExtValue ( ) ; Info . vol = false ; Info . readMem = true ; Info . writeMem = false ; return true ; } case Intrinsic :: arm_neon_vst1 : case Intrinsic :: arm_neon_vst2 : case Intrinsic :: arm_neon_vst3 : case Intrinsic :: arm_neon_vst4 : case Intrinsic :: aarch64_neon_vst1x2 : case Intrinsic :: aarch64_neon_vst1x3 : case Intrinsic :: aarch64_neon_vst1x4 : case Intrinsic :: arm_neon_vst2lane : case Intrinsic :: arm_neon_vst3lane : case Intrinsic :: arm_neon_vst4lane : { Info . opc = ISD :: INTRINSIC_VOID ; unsigned NumElts = 0 ; for ( unsigned ArgI = 1 , ArgE = I . getNumArgOperands ( ) ; ArgI < ArgE ; ++ ArgI ) { Type * ArgTy = I . getArgOperand ( ArgI ) -> getType ( ) ; if ( ! ArgTy -> isVectorTy ( ) ) break ; NumElts += getDataLayout ( ) -> getTypeAllocSize ( ArgTy ) / 8 ; } Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , MVT :: i64 , NumElts ) ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Value * AlignArg = I . getArgOperand ( I . getNumArgOperands ( ) - 1 ) ; Info . align = cast < ConstantInt > ( AlignArg ) -> getZExtValue ( ) ; Info . vol = false ; Info . readMem = false ; Info . writeMem = true ; return true ; } default : break ; } return false ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static bool pru_valid_addr_expr_p ( machine_mode mode , rtx base , rtx offset , bool strict_p ) { if ( ! strict_p && GET_CODE ( base ) == SUBREG ) base = SUBREG_REG ( base ) ; if ( ! strict_p && GET_CODE ( offset ) == SUBREG ) offset = SUBREG_REG ( offset ) ; if ( REG_P ( base ) && pru_regno_ok_for_base_p ( REGNO ( base ) , strict_p ) && ( ( CONST_INT_P ( offset ) && pru_valid_const_ubyte_offset ( mode , INTVAL ( offset ) ) ) || ( REG_P ( offset ) && pru_regno_ok_for_index_p ( REGNO ( offset ) , strict_p ) ) ) ) return true ; else if ( REG_P ( base ) && pru_regno_ok_for_index_p ( REGNO ( base ) , strict_p ) && ctable_base_operand ( offset , VOIDmode ) ) return true ; else return false ; } </s>

Return true if the address expression formed by BASE + OFFSET is valid . Note that the following address is not handled here : base CTABLE constant base + UBYTE constant offset The constants will be folded . The ctable_addr_operand predicate will take care of the validation . The CTABLE base+offset split will happen during operand printing .


"sorry, I don't know how to store this sort of reg in the stack\n"


<s> static std :: unique_ptr < MCS51Operand > CreateReg ( unsigned RegNum , SMLoc S , SMLoc E ) { return std :: make_unique < MCS51Operand > ( RegNum , S , E ) ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> static int pa_arg_partial_bytes ( cumulative_args_t cum_v , machine_mode mode , tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; unsigned int max_arg_words = 8 ; unsigned int offset = 0 ; if ( ! TARGET_64BIT ) return 0 ; if ( pa_function_arg_size ( mode , type ) > 1 && ( cum -> words & 1 ) ) offset = 1 ; if ( cum -> words + offset + pa_function_arg_size ( mode , type ) <= max_arg_words ) return 0 ; else if ( cum -> words + offset >= max_arg_words ) return 0 ; else return ( max_arg_words - cum -> words - offset ) * UNITS_PER_WORD ; } </s>

If this arg would be passed totally in registers or totally on the stack , then this routine should return zero .


<s>
std
::
string
AMDGPUIntrinsicInfo
::
getName
(
unsigned
IntrID
,
Type
*
*
Tys
,
unsigned
numTys
)
const
{
static
const
char
*
const
names
[
]
=
{
}
;
if
(
IntrID
<
Intrinsic
::
num_intrinsics
)
{
return
nullptr
;
}
assert
(
IntrID
<
AMDGPUIntrinsic
::
num_AMDGPU_intrinsics
&&
"Invalid intrinsic ID"
)
;
std
::
string
Result
(
names
[
IntrID
Intrinsic
::
num_intrinsics
]
)
;
return
Result
;
}
</s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> static struct machine_function * mmix_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function > ( ) ; } </s>


<s>
static
void
vax_output_mi_thunk
(
FILE
*
file
,
tree
thunk
ATTRIBUTE_UNUSED
,
HOST_WIDE_INT
delta
,
HOST_WIDE_INT
vcall_offset
ATTRIBUTE_UNUSED
,
tree
function
)
{
const
char
*
fnname
=
IDENTIFIER_POINTER
(
DECL_ASSEMBLER_NAME
(
thunk
)
)
;
assemble_start_function
(
thunk
,
fnname
)
;
fprintf
(
file
,
"\t.word 0x0ffc\n\taddl2 $"
HOST_WIDE_INT_PRINT_DEC
,
delta
)
;
asm_fprintf
(
file
,
",4(%Rap)\n"
)
;
fprintf
(
file
,
"\tjmp "
)
;
assemble_name
(
file
,
XSTR
(
XEXP
(
DECL_RTL
(
function
)
,
0
)
,
0
)
)
;
fprintf
(
file
,
"+2\n"
)
;
assemble_end_function
(
thunk
,
fnname
)
;
}
</s>

Output code to add DELTA to the first argument , and then jump to FUNCTION . Used for C++ multiple inheritance . .mask ^m < r2 , r3 , r4 , r5 , r6 , r7 , r8 , r9 , r10 , r11 > # conservative entry mask addl2 $ DELTA , 4 ( ap ) # adjust first argument jmp FUNCTION+2 # jump beyond FUNCTION 's entry mask


<s> DecodeStatus PPCDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & OS , raw_ostream & CS ) const { Size = 4 ; if ( Bytes . size ( ) < 4 ) { Size = 0 ; return MCDisassembler :: Fail ; } uint32_t Inst = ( Bytes [ 0 ] << 24 ) | ( Bytes [ 1 ] << 16 ) | ( Bytes [ 2 ] << 8 ) | ( Bytes [ 3 ] << 0 ) ; return decodeInstruction ( DecoderTable32 , MI , Inst , Address , this , STI ) ; } </s>

Returns the disassembly of a single instruction .


<s> void AArch64MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; if ( MI . getOpcode ( ) == AArch64 :: TLSDESCCALL ) { MCFixupKind Fixup = MCFixupKind ( AArch64 :: fixup_aarch64_tlsdesc_call ) ; Fixups . push_back ( MCFixup :: create ( 0 , MI . getOperand ( 0 ) . getExpr ( ) , Fixup ) ) ; return ; } uint64_t Binary = getBinaryCodeForInstr ( MI , Fixups , STI ) ; support :: endian :: Writer < support :: little > ( OS ) . write < uint32_t > ( Binary ) ; ++ MCNumEmitted ; } </s>

Encode the given Inst to bytes and append to CB .


"SIInstrInfo::loadRegFromStackSlot - Do not know how to"

Load the specified register of the given register class from the specified stack frame index .


"%qE attribute only applies to functions"

Handle a `` longcall '' attribute ; arguments as in struct attribute_spec.handler .


<s> static int store_with_one_insn_p ( rtx mem ) { machine_mode mode = GET_MODE ( mem ) ; rtx addr = XEXP ( mem , 0 ) ; if ( mode == BLKmode ) return 0 ; if ( GET_MODE_SIZE ( mode ) >= 16 ) return 1 ; if ( GET_CODE ( addr ) == SYMBOL_REF ) { tree decl = MEM_EXPR ( mem ) ; if ( decl && TREE_CODE ( decl ) == VAR_DECL && GET_MODE ( mem ) == TYPE_MODE ( TREE_TYPE ( decl ) ) ) return 1 ; decl = SYMBOL_REF_DECL ( addr ) ; if ( decl && TREE_CODE ( decl ) == VAR_DECL && GET_MODE ( mem ) == TYPE_MODE ( TREE_TYPE ( decl ) ) ) return 1 ; } return 0 ; } </s>

Return TRUE if we are certain the mem refers to a complete object which is both 16-byte aligned and padded to a 16-byte boundary . This would make it safe to store with a single instruction . We guarantee the alignment and padding for static objects by aligning all of them to 16-bytes . ( DATA_ALIGNMENT and TARGET_CONSTANT_ALIGNMENT . ) FIXME : We currently can not guarantee this for objects on the stack because assign_parm_setup_stack calls assign_stack_local with the alignment of the parameter mode and in that case the alignment never gets adjusted by LOCAL_ALIGNMENT .


<s>
void
AMDGPUAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
Value
=
adjustFixupValue
(
Fixup
,
Value
,
&
Asm
.
getContext
(
)
)
;
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
uint32_t
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
Data
[
Offset
+
i
]
|=
static_cast
<
uint8_t
>
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static bool rs6000_vector_mode_supported_p ( machine_mode mode ) { if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) && ! FLOAT128_IEEE_P ( mode ) ) return true ; else return false ; } </s>

Target hook for vector_mode_supported_p .


<s> int expand_block_clear ( rtx operands [ ] ) { rtx orig_dest = operands [ 0 ] ; rtx bytes_rtx = operands [ 1 ] ; rtx align_rtx = operands [ 3 ] ; bool constp = ( GET_CODE ( bytes_rtx ) == CONST_INT ) ; HOST_WIDE_INT align ; HOST_WIDE_INT bytes ; int offset ; int clear_bytes ; int clear_step ; if ( ! constp ) return 0 ; gcc_assert ( GET_CODE ( align_rtx ) == CONST_INT ) ; align = INTVAL ( align_rtx ) * BITS_PER_UNIT ; bytes = INTVAL ( bytes_rtx ) ; if ( bytes <= 0 ) return 1 ; if ( TARGET_ALTIVEC && align >= 128 ) clear_step = 16 ; else if ( TARGET_POWERPC64 && ( align >= 64 || ! STRICT_ALIGNMENT ) ) clear_step = 8 ; else if ( TARGET_SPE && align >= 64 ) clear_step = 8 ; else clear_step = 4 ; if ( optimize_size && bytes > 3 * clear_step ) return 0 ; if ( ! optimize_size && bytes > 8 * clear_step ) return 0 ; for ( offset = 0 ; bytes > 0 ; offset += clear_bytes , bytes -= clear_bytes ) { machine_mode mode = BLKmode ; rtx dest ; if ( bytes >= 16 && TARGET_ALTIVEC && align >= 128 ) { clear_bytes = 16 ; mode = V4SImode ; } else if ( bytes >= 8 && TARGET_SPE && align >= 64 ) { clear_bytes = 8 ; mode = V2SImode ; } else if ( bytes >= 8 && TARGET_POWERPC64 && ( align >= 64 || ! STRICT_ALIGNMENT ) ) { clear_bytes = 8 ; mode = DImode ; if ( offset == 0 && align < 64 ) { rtx addr ; addr = XEXP ( orig_dest , 0 ) ; if ( ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) && GET_CODE ( XEXP ( addr , 1 ) ) == CONST_INT && ( INTVAL ( XEXP ( addr , 1 ) ) & 3 ) != 0 ) { addr = copy_addr_to_reg ( addr ) ; orig_dest = replace_equiv_address ( orig_dest , addr ) ; } } } else if ( bytes >= 4 && ( align >= 32 || ! STRICT_ALIGNMENT ) ) { clear_bytes = 4 ; mode = SImode ; } else if ( bytes >= 2 && ( align >= 16 || ! STRICT_ALIGNMENT ) ) { clear_bytes = 2 ; mode = HImode ; } else { clear_bytes = 1 ; mode = QImode ; } dest = adjust_address ( orig_dest , mode , offset ) ; emit_move_insn ( dest , CONST0_RTX ( mode ) ) ; } return 1 ; } </s>

Expand a block clear operation , and return 1 if successful . Return 0 if we should let the compiler generate normal code . operands [ 0 ] is the destination operands [ 1 ] is the length operands [ 3 ] is the alignment


"internal error: builtin function %qs already processed"

Add a SPARC builtin function with NAME , ICODE , CODE and TYPE . Return the function decl or NULL_TREE if the builtin was not added .


<s> unsigned MSP430RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? MSP430 :: FPW : MSP430 :: SPW ; } </s>


<s> void DXILBitcodeWriter :: write ( ) { Stream . EnterSubblock ( bitc :: MODULE_BLOCK_ID , 3 ) ; DXILBitcodeWriter :: writeModuleVersion ( ) ; writeBlockInfo ( ) ; writeAttributeGroupTable ( ) ; writeAttributeTable ( ) ; writeTypeTable ( ) ; writeComdats ( ) ; writeModuleInfo ( ) ; writeModuleConstants ( ) ; writeModuleMetadataKinds ( ) ; writeModuleMetadata ( ) ; writeFunctionLevelValueSymbolTable ( M . getValueSymbolTable ( ) ) ; if ( VE . shouldPreserveUseListOrder ( ) ) writeUseListBlock ( nullptr ) ; for ( const Function & F : M ) if ( ! F . isDeclaration ( ) ) writeFunction ( F ) ; Stream . ExitBlock ( ) ; } </s>

Write the profile to a string output stream OS .


<s> unsigned PPCDispatchGroupSBHazardRecognizer :: PreEmitNoops ( SUnit * SU ) { if ( isLoadAfterStore ( SU ) && CurSlots < 6 ) { unsigned Directive = DAG -> TM . getSubtarget < PPCSubtarget > ( ) . getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_PWR6 || Directive == PPC :: DIR_PWR7 ) return 1 ; return 5 - CurSlots ; } return ScoreboardHazardRecognizer :: PreEmitNoops ( SU ) ; } </s>

PreEmitNoops - This callback is invoked prior to emitting an instruction .


"RegScavenger required for long branching"

"new block should be inserted for expanding unconditional branch"

"Branch offsets outside of the signed 32-bit range not supported"

Insert an unconditional indirect branch at the end of MBB to NewDestBB .


<s> int VideocoreAsmParser :: tryParseRegister ( ) { const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return 0 ; std :: string lowerCase = Tok . getString ( ) . lower ( ) ; unsigned RegNum = MatchRegisterName ( lowerCase ) ; if ( ! RegNum ) { RegNum = StringSwitch < unsigned > ( lowerCase ) . Case ( "r25" , VC :: SP ) . Case ( "r26" , VC :: LR ) . Case ( "r30" , VC :: SR ) . Case ( "r31" , VC :: PC ) . Default ( 0 ) ; } if ( ! RegNum ) return - 1 ; Parser . Lex ( ) ; return RegNum ; } </s>

tryParseRegister - parse one register if possible


"MIa must load from or modify a memory location"

"MIb must load from or modify a memory location"

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> void h8300_expand_epilogue ( bool sibcall_p ) { int regno ; int saved_regs ; int n_regs ; HOST_WIDE_INT frame_size ; bool returned_p ; if ( h8300_os_task_function_p ( current_function_decl ) ) return ; frame_size = round_frame_size ( get_frame_size ( ) ) ; returned_p = false ; h8300_emit_stack_adjustment ( 1 , frame_size ) ; saved_regs = compute_saved_regs ( ) ; for ( regno = FIRST_PSEUDO_REGISTER - 1 ; regno >= 0 ; regno -= n_regs ) { n_regs = 1 ; if ( saved_regs & ( 1 << regno ) ) { if ( TARGET_H8300S ) { if ( ( TARGET_H8300SX || ( regno & 3 ) == 3 ) && ( ( saved_regs << 3 >> regno ) & 0x0f ) == 0x0f ) n_regs = 4 ; else if ( ( TARGET_H8300SX || ( regno & 3 ) == 2 ) && ( ( saved_regs << 2 >> regno ) & 0x07 ) == 0x07 ) n_regs = 3 ; else if ( ( TARGET_H8300SX || ( regno & 1 ) == 1 ) && ( ( saved_regs << 1 >> regno ) & 0x03 ) == 0x03 ) n_regs = 2 ; } if ( TARGET_H8300SX && ! sibcall_p && ! frame_pointer_needed && frame_size == 0 && ( saved_regs & ( ( 1 << ( regno - n_regs + 1 ) ) - 1 ) ) == 0 ) returned_p = true ; h8300_push_pop ( regno - n_regs + 1 , n_regs , true , returned_p ) ; } } if ( frame_pointer_needed ) { if ( TARGET_H8300SX && ! sibcall_p ) returned_p = true ; h8300_push_pop ( HARD_FRAME_POINTER_REGNUM , 1 , true , returned_p ) ; } if ( ! returned_p && ! sibcall_p ) emit_jump_insn ( ret_rtx ) ; } </s>

Generate RTL code for the function epilogue .


<s> const char * PatmosTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return NULL ; case PatmosISD :: RET_FLAG : return "PatmosISD::RET_FLAG" ; case PatmosISD :: CALL : return "PatmosISD::CALL" ; case PatmosISD :: MUL : return "PatmosISD::MUL" ; case PatmosISD :: MULU : return "PatmosISD::MULU" ; } } </s>

getTargetNodeName - This method returns the name of a target specific

Patmos Patmos PatmosISD::RET_FLAG "PatmosISD::RET_FLAG" PatmosISD::CALL "PatmosISD::CALL" PatmosISD::MUL "PatmosISD::MUL" PatmosISD::MULU "PatmosISD::MULU"


<s> TargetPassConfig * MSP430TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new MSP430PassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> int regs_used ( rtx x , int is_dest ) { enum rtx_code code ; const char * fmt ; int i , used = 0 ; if ( ! x ) return used ; code = GET_CODE ( x ) ; switch ( code ) { case REG : if ( REGNO ( x ) < 16 ) return ( ( ( 1 << HARD_REGNO_NREGS ( 0 , GET_MODE ( x ) ) ) - 1 ) << ( REGNO ( x ) + is_dest ) ) ; return 0 ; case SUBREG : { rtx y = SUBREG_REG ( x ) ; if ( GET_CODE ( y ) != REG ) break ; if ( REGNO ( y ) < 16 ) return ( ( ( 1 << HARD_REGNO_NREGS ( 0 , GET_MODE ( x ) ) ) - 1 ) << ( REGNO ( y ) + subreg_regno_offset ( REGNO ( y ) , GET_MODE ( y ) , SUBREG_BYTE ( x ) , GET_MODE ( x ) ) + is_dest ) ) ; return 0 ; } case SET : return regs_used ( SET_SRC ( x ) , 0 ) | regs_used ( SET_DEST ( x ) , 16 ) ; case RETURN : return 0x00ffff00 ; case CLOBBER : is_dest = 1 ; break ; case MEM : is_dest = 0 ; break ; case CALL : used |= 0x00ff00f0 ; break ; default : break ; } fmt = GET_RTX_FORMAT ( code ) ; for ( i = GET_RTX_LENGTH ( code ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { register int j ; for ( j = XVECLEN ( x , i ) - 1 ; j >= 0 ; j -- ) used |= regs_used ( XVECEXP ( x , i , j ) , is_dest ) ; } else if ( fmt [ i ] == 'e' ) used |= regs_used ( XEXP ( x , i ) , is_dest ) ; } return used ; } </s>

Given a X , a pattern of an insn or a part of it , return a mask of used general registers . Bits 0 .. 15 mean that the respective registers are used as inputs in the instruction . Bits 16 .. 31 mean that the registers 0 .. 15 , respectively , are used as outputs , or are clobbered . IS_DEST should be set to 16 if X is the destination of a SET , else to 0 .


<s> Relocator :: Size HexagonRelocator :: getSize ( Relocation :: Type pType ) const { return 32 ; } </s>

Return the number of bytes in the encoding of this instruction , or zero if the encoding size can not be known from the opcode .


<s> bool AMDGPUCodeGenPrepare :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; const TargetMachine & TM = TPC -> getTM < TargetMachine > ( ) ; ST = & TM . getSubtarget < SISubtarget > ( F ) ; DA = & getAnalysis < DivergenceAnalysis > ( ) ; HasUnsafeFPMath = hasUnsafeFPMath ( F ) ; bool MadeChange = false ; for ( BasicBlock & BB : F ) { BasicBlock :: iterator Next ; for ( BasicBlock :: iterator I = BB . begin ( ) , E = BB . end ( ) ; I != E ; I = Next ) { Next = std :: next ( I ) ; MadeChange |= visit ( * I ) ; } } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool SIInstrInfo :: findCommutedOpIndices ( MachineInstr * MI , unsigned & SrcOpIdx0 , unsigned & SrcOpIdx1 ) const { const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( ! MCID . isCommutable ( ) ) return false ; unsigned Opc = MI -> getOpcode ( ) ; int Src0Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src0 ) ; if ( Src0Idx == - 1 ) return false ; if ( ! MI -> getOperand ( Src0Idx ) . isReg ( ) ) return false ; int Src1Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src1 ) ; if ( Src1Idx == - 1 ) return false ; MachineOperand & Src1 = MI -> getOperand ( Src1Idx ) ; if ( Src1 . isImm ( ) ) { if ( ! isVOP2 ( MI -> getOpcode ( ) ) && ! isVOP3 ( MI -> getOpcode ( ) ) ) return false ; } else if ( Src1 . isReg ( ) ) { if ( hasModifiersSet ( * MI , AMDGPU :: OpName :: src0_modifiers ) || hasModifiersSet ( * MI , AMDGPU :: OpName :: src1_modifiers ) ) return false ; } else return false ; return fixCommutedOpIndices ( SrcOpIdx0 , SrcOpIdx1 , Src0Idx , Src1Idx ) ; } </s>

Returns true iff the routine could find two commutable operands in the given machine instruction .

AMDGPU SI AMDGPU::getNamedOperandIdx AMDGPU::OpName 1 AMDGPU::getNamedOperandIdx AMDGPU::OpName 1 AMDGPU::OpName AMDGPU::OpName


"Unknown opcode to check as cheap as a move!"

Return true if the instruction is as cheap as a move instruction .


<s> BaseKind getKind ( ) const { return Kind ; } </s>


<s> bool AMDGPUAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( ! AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , O ) ) return false ; if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { case 'r' : break ; default : return true ; } } const MachineOperand & MO = MI -> getOperand ( OpNo ) ; if ( MO . isReg ( ) ) { AMDGPUInstPrinter :: printRegOperand ( MO . getReg ( ) , O , * MF -> getSubtarget ( ) . getRegisterInfo ( ) ) ; return false ; } return true ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s>
bool
RISCVInsertVSETVLI
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
const
RISCVSubtarget
&
ST
=
MF
.
getSubtarget
<
RISCVSubtarget
>
(
)
;
if
(
!
ST
.
hasStdExtV
(
)
)
return
false
;
TII
=
ST
.
getInstrInfo
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
assert
(
BlockInfo
.
empty
(
)
&&
"Expect empty block infos"
)
;
BlockInfo
.
resize
(
MF
.
getNumBlockIDs
(
)
)
;
bool
HaveVectorOp
=
false
;
for
(
const
MachineBasicBlock
&
MBB
:
MF
)
HaveVectorOp
|=
computeVLVTYPEChanges
(
MBB
)
;
if
(
HaveVectorOp
)
{
for
(
const
MachineBasicBlock
&
MBB
:
MF
)
{
WorkList
.
push
(
&
MBB
)
;
BlockInfo
[
MBB
.
getNumber
(
)
]
.
InQueue
=
true
;
}
while
(
!
WorkList
.
empty
(
)
)
{
const
MachineBasicBlock
&
MBB
=
*
WorkList
.
front
(
)
;
WorkList
.
pop
(
)
;
computeIncomingVLVTYPE
(
MBB
)
;
}
for
(
MachineBasicBlock
&
MBB
:
MF
)
emitVSETVLIs
(
MBB
)
;
}
BlockInfo
.
clear
(
)
;
return
HaveVectorOp
;
}
</s>

runOnMachineFunction - Emit the function body .

RISCV
RISCV
RISCV
RISCV
"Expect empty block infos"


<s> bool HexagonAsmParser :: isLabel ( AsmToken & Token ) { MCAsmLexer & Lexer = getLexer ( ) ; AsmToken const & Second = Lexer . getTok ( ) ; AsmToken Third = Lexer . peekTok ( ) ; StringRef String = Token . getString ( ) ; if ( Token . is ( AsmToken :: TokenKind :: LCurly ) || Token . is ( AsmToken :: TokenKind :: RCurly ) ) return false ; if ( String . lower ( ) == "vwhist256" && Second . is ( AsmToken :: Colon ) && Third . getString ( ) . lower ( ) == "sat" ) return false ; if ( ! Token . is ( AsmToken :: TokenKind :: Identifier ) ) return true ; if ( ! matchRegister ( String . lower ( ) ) ) return true ; assert ( Second . is ( AsmToken :: Colon ) ) ; StringRef Raw ( String . data ( ) , Third . getString ( ) . data ( ) - String . data ( ) + Third . getString ( ) . size ( ) ) ; std :: string Collapsed = std :: string ( Raw ) ; Collapsed . erase ( llvm :: remove_if ( Collapsed , isSpace ) , Collapsed . end ( ) ) ; StringRef Whole = Collapsed ; std :: pair < StringRef , StringRef > DotSplit = Whole . split ( '.' ) ; if ( ! matchRegister ( DotSplit . first . lower ( ) ) ) return true ; return false ; } </s>

Returns true if the MachineInstr represents a label .


The darwin64 ABI calls for us to recurse down through structs , looking for elements passed in registers . Unfortunately , we have to track int register count here also because of misalignments in powerpc alignment mode .


<s> inline void assign_registers ( const_tree field , HOST_WIDE_INT bitpos , bool fp , assign_data_t * data ) { if ( fp ) { assign_int_registers ( bitpos , data ) ; assign_fp_registers ( field , bitpos , data ) ; } else { if ( data -> intoffset < 0 ) data -> intoffset = bitpos ; } } </s>

A subroutine of function_arg_record_value . Assign FIELD and the bits of the structure between PARMS- > intoffset and BITPOS to registers .


<s> unsigned getLoc ( ) const { return loc ; } </s>

Get the source location of the point where the field was defined .


<s> static void ft32_compute_frame ( void ) { int stack_alignment = STACK_BOUNDARY / BITS_PER_UNIT ; int padding_locals ; int regno ; cfun -> machine -> local_vars_size = get_frame_size ( ) ; padding_locals = cfun -> machine -> local_vars_size % stack_alignment ; if ( padding_locals ) padding_locals = stack_alignment - padding_locals ; cfun -> machine -> local_vars_size += padding_locals ; cfun -> machine -> callee_saved_reg_size = 0 ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ( ! call_used_regs [ regno ] ) ) cfun -> machine -> callee_saved_reg_size += 4 ; cfun -> machine -> size_for_adjusting_sp = crtl -> args . pretend_args_size + cfun -> machine -> local_vars_size + ( ACCUMULATE_OUTGOING_ARGS ? crtl -> outgoing_args_size : 0 ) ; } </s>

Compute the size of the local area and the size to be adjusted by the * prologue and epilogue .


<s>
void
addExpr
(
MCInst
&
Inst
,
const
MCExpr
*
Expr
)
const
{
assert
(
Expr
&&
"Expr shouldn't be null!"
)
;
int64_t
Imm
=
0
;
RISCVMCExpr
::
VariantKind
VK
=
RISCVMCExpr
::
VK_RISCV_None
;
bool
IsConstant
=
evaluateConstantImm
(
Expr
,
Imm
,
VK
)
;
if
(
IsConstant
)
Inst
.
addOperand
(
MCOperand
::
createImm
(
Imm
)
)
;
else
Inst
.
addOperand
(
MCOperand
::
createExpr
(
Expr
)
)
;
}
</s>

RISCV
"Expr shouldn't be null!"
0
RISCV
RISCV
RISCV


<s> static unsigned size ( const agraph & G ) { return G . Blocks . size ( ) ; } </s>

The number of name/type pairs is returned .


<s> bool X86TTIImpl :: isLegalMaskedGather ( Type * DataTy , MaybeAlign Alignment ) { if ( ! ( ST -> hasAVX512 ( ) || ( ST -> hasFastGather ( ) && ST -> hasAVX2 ( ) ) ) ) return false ; if ( isa < VectorType > ( DataTy ) ) { unsigned NumElts = DataTy -> getVectorNumElements ( ) ; if ( NumElts == 1 || ! isPowerOf2_32 ( NumElts ) ) return false ; } Type * ScalarTy = DataTy -> getScalarType ( ) ; if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == 32 || IntWidth == 64 ; } </s>

Return true if the target supports masked gather .


<s>
SDValue
AArch64TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom lower this!"
)
;
case
ISD
::
FADD
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
ADD_F128
)
;
case
ISD
::
FSUB
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
SUB_F128
)
;
case
ISD
::
FMUL
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
MUL_F128
)
;
case
ISD
::
FDIV
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
DIV_F128
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
,
true
)
;
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
,
false
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
,
true
)
;
case
ISD
::
UINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
,
false
)
;
case
ISD
::
FP_ROUND
:
return
LowerFP_ROUND
(
Op
,
DAG
)
;
case
ISD
::
FP_EXTEND
:
return
LowerFP_EXTEND
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
BRCOND
:
return
LowerBRCOND
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddressELF
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
LowerSELECT
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
case
ISD
::
VACOPY
:
return
LowerVACOPY
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
BUILD_VECTOR
:
return
LowerBUILD_VECTOR
(
Op
,
DAG
,
getSubtarget
(
)
)
;
case
ISD
::
VECTOR_SHUFFLE
:
return
LowerVECTOR_SHUFFLE
(
Op
,
DAG
)
;
}
return
SDValue
(
)
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> static void save_reg ( int regno , unsigned offset ) { rtx reg = gen_rtx_REG ( SImode , regno ) ; rtx addr = plus_constant ( Pmode , stack_pointer_rtx , offset , false ) ; rtx_insn * insn = emit_move_insn ( gen_frame_mem ( Pmode , addr ) , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Generate save/restore of register REGNO at SP + OFFSET . Used by the prologue/epilogue expand routines .


<s>
static
void
thumb_pop
(
FILE
*
f
,
unsigned
long
mask
)
{
int
regno
;
int
lo_mask
=
mask
&
0xFF
;
int
pushed_words
=
0
;
gcc_assert
(
mask
)
;
if
(
lo_mask
==
0
&&
(
mask
&
(
1
<<
PC_REGNUM
)
)
)
{
thumb_exit
(
f
,
1
)
;
return
;
}
fprintf
(
f
,
"\tpop\t{"
)
;
for
(
regno
=
0
;
regno
<=
LAST_LO_REGNUM
;
regno
++
,
lo_mask
>>=
1
)
{
if
(
lo_mask
&
1
)
{
asm_fprintf
(
f
,
"%r"
,
regno
)
;
if
(
(
lo_mask
&
~
1
)
!=
0
)
fprintf
(
f
,
", "
)
;
pushed_words
++
;
}
}
if
(
mask
&
(
1
<<
PC_REGNUM
)
)
{
if
(
TARGET_INTERWORK
||
TARGET_BACKTRACE
||
crtl
->
calls_eh_return
||
IS_CMSE_ENTRY
(
arm_current_func_type
(
)
)
)
{
fprintf
(
f
,
"}\n"
)
;
thumb_exit
(
f
,
1
)
;
return
;
}
else
{
if
(
mask
&
0xFF
)
fprintf
(
f
,
", "
)
;
asm_fprintf
(
f
,
"%r"
,
PC_REGNUM
)
;
}
}
fprintf
(
f
,
"}\n"
)
;
}
</s>

Emit code to push or pop registers to or from the stack . F is the assembly file . MASK is the registers to pop .


<s> machine_mode ix86_fp_compare_mode ( enum rtx_code ) { return TARGET_IEEE_FP ? CCFPUmode : CCFPmode ; } </s>

Figure out whether to use ordered or unordered fp comparisons . Return the appropriate mode to use .


<s> SDNode * MipsDAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = MF -> getInfo < MipsFunctionInfo > ( ) -> getGlobalBaseReg ( ) ; return CurDAG -> getRegister ( GlobalBaseReg , getTargetLowering ( ) -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static int arc_save_callee_enter ( unsigned int gmask , bool save_blink , bool save_fp , HOST_WIDE_INT offset ) { int start_reg = ENTER_LEAVE_START_REG ; int end_reg = ENTER_LEAVE_END_REG ; int regno , indx , off , nregs ; rtx insn , reg , mem ; int frame_allocated = 0 ; for ( regno = start_reg ; regno <= end_reg && ( gmask & ( 1L << regno ) ) ; ) regno ++ ; end_reg = regno - 1 ; nregs = end_reg - start_reg + 1 ; nregs += save_blink ? 1 : 0 ; nregs += save_fp ? 1 : 0 ; if ( offset ) frame_stack_add ( offset ) ; insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nregs + ( save_fp ? 1 : 0 ) + 1 ) ) ; indx = 0 ; reg = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - nregs * UNITS_PER_WORD ) ) ; RTX_FRAME_RELATED_P ( reg ) = 1 ; XVECEXP ( insn , 0 , indx ++ ) = reg ; off = nregs * UNITS_PER_WORD ; if ( save_blink ) { reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , off ) ) ; XVECEXP ( insn , 0 , indx ) = gen_rtx_SET ( mem , reg ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , 0 , indx ++ ) ) = 1 ; off -= UNITS_PER_WORD ; save_blink = false ; } for ( regno = start_reg ; regno <= end_reg ; regno ++ , indx ++ , off -= UNITS_PER_WORD ) { reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , off ) ) ; XVECEXP ( insn , 0 , indx ) = gen_rtx_SET ( mem , reg ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , 0 , indx ) ) = 1 ; gmask = gmask & ~ ( 1L << regno ) ; } if ( save_fp ) { mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , off ) ) ; XVECEXP ( insn , 0 , indx ) = gen_rtx_SET ( mem , hard_frame_pointer_rtx ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , 0 , indx ++ ) ) = 1 ; off -= UNITS_PER_WORD ; XVECEXP ( insn , 0 , indx ) = gen_rtx_SET ( hard_frame_pointer_rtx , stack_pointer_rtx ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , 0 , indx ++ ) ) = 1 ; save_fp = false ; } gcc_assert ( off == 0 ) ; insn = frame_insn ( insn ) ; add_reg_note ( insn , REG_INC , stack_pointer_rtx ) ; frame_allocated = nregs * UNITS_PER_WORD ; return frame_allocated - offset ; } </s>

ARC prologue , save the registers using enter instruction . Leave instruction can also save $ blink ( SAVE_BLINK ) and $ fp ( SAVE_FP ) register .


<s> rtx disi_highpart ( rtx in ) { return simplify_gen_subreg ( SImode , in , DImode , TARGET_BIG_ENDIAN ? 0 : 4 ) ; } </s>

Return the SImode highpart of the DImode value IN .


<s> void P2TargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { Base :: Initialize ( Ctx , TM ) ; ProgmemDataSection = Ctx . getELFSection ( ".progmem.data" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ; } </s>

This method must be called before any actual lowering is done .


<s> bool ARMBaseInstrInfo :: isPredicated ( const MachineInstr * MI ) const { if ( MI -> isBundle ( ) ) { MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; while ( ++ I != E && I -> isInsideBundle ( ) ) { int PIdx = I -> findFirstPredOperandIdx ( ) ; if ( PIdx != - 1 && I -> getOperand ( PIdx ) . getImm ( ) != ARMCC :: AL ) return true ; } return false ; } int PIdx = MI -> findFirstPredOperandIdx ( ) ; return PIdx != - 1 && MI -> getOperand ( PIdx ) . getImm ( ) != ARMCC :: AL ; } </s>

Returns true if the instruction is already predicated .


<s> MipsTargetLowering :: ConstraintType MipsTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'd' : case 'y' : case 'f' : return C_RegisterClass ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> X86TargetLowering :: ConstraintType X86TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'R' : case 'q' : case 'Q' : case 'f' : case 't' : case 'u' : case 'y' : case 'x' : case 'v' : case 'l' : case 'k' : return C_RegisterClass ; case 'a' : case 'b' : case 'c' : case 'd' : case 'S' : case 'D' : case 'A' : return C_Register ; case 'I' : case 'J' : case 'K' : case 'N' : case 'G' : case 'L' : case 'M' : return C_Immediate ; case 'C' : case 'e' : case 'Z' : return C_Other ; default : break ; } } else if ( Constraint . size ( ) == 2 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'Y' : switch ( Constraint [ 1 ] ) { default : break ; case 'z' : return C_Register ; case 'i' : case 'm' : case 'k' : case 't' : case '2' : return C_RegisterClass ; } } } else if ( parseConstraintCode ( Constraint ) != X86 :: COND_INVALID ) return C_Other ; return TargetLowering :: getConstraintType ( Constraint ) ; } </s>


<s> bool empty ( ) const { return Q . empty ( ) ; } </s>

Determine whether this version information is empty ( e.g. , all version components are zero ) .


"mips16 and nomips16 specified on the same function"

Reset the subtarget for the Mips target .


<s>
bool
RISCVInstrInfo
::
reverseBranchCondition
(
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
if
(
Cond
[
0
]
.
getImm
(
)
==
RISCV
::
HwlpBranch
)
{
return
true
;
}
assert
(
(
Cond
.
size
(
)
==
3
)
&&
"Invalid branch condition!"
)
;
Cond
[
0
]
.
setImm
(
getOppositeBranchOpcode
(
Cond
[
0
]
.
getImm
(
)
)
)
;
return
false
;
}
</s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> bool X86RegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; if ( ! MF . getTarget ( ) . Options . RealignStack ) return false ; if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ; if ( MFI -> hasVarSizedObjects ( ) ) return MRI -> canReserveReg ( BasePtr ) ; return true ; } </s>

True if the stack can be realigned for the target .


"getIntImmCost can only estimate cost of materialising integers"

Calculate the cost of materializing a 64-bit value .


<s> static const char * mmix_strip_name_encoding ( const char * name ) { for ( ; ( * name == '@' || * name == '*' ) ; name ++ ) ; return name ; } </s>


<s> static bool avr_function_ok_for_sibcall ( tree decl_callee , tree exp_callee ) { tree fntype_callee ; if ( cfun -> machine -> sibcall_fails || TARGET_CALL_PROLOGUES ) { return false ; } fntype_callee = TREE_TYPE ( CALL_EXPR_FN ( exp_callee ) ) ; if ( decl_callee ) { decl_callee = TREE_TYPE ( decl_callee ) ; } else { decl_callee = fntype_callee ; while ( FUNCTION_TYPE != TREE_CODE ( decl_callee ) && METHOD_TYPE != TREE_CODE ( decl_callee ) ) { decl_callee = TREE_TYPE ( decl_callee ) ; } } if ( cfun -> machine -> is_interrupt || cfun -> machine -> is_signal || cfun -> machine -> is_naked || avr_naked_function_p ( decl_callee ) ) { return false ; } return true ; } </s>

Decide whether we can make a sibling call to a function . DECL is the declaration of the function being targeted by the call and EXP is the CALL_EXPR representing the call .


<s>
const
MCFixupKindInfo
&
X86AsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
X86
::
NumTargetFixupKinds
]
=
{
{
"reloc_riprel_4byte"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_movq_load"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_relax"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_relax_rex"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_signed_4byte"
,
0
,
32
,
0
}
,
{
"reloc_signed_4byte_relax"
,
0
,
32
,
0
}
,
{
"reloc_global_offset_table"
,
0
,
32
,
0
}
,
{
"reloc_global_offset_table8"
,
0
,
64
,
0
}
,
{
"reloc_branch_4byte_pcrel"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
assert
(
Infos
[
Kind
FirstTargetFixupKind
]
.
Name
&&
"Empty fixup name!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> static tree fully_fold_convert ( tree type , tree expr ) { tree result = fold_convert ( type , expr ) ; bool maybe_const = true ; if ( ! c_dialect_cxx ( ) ) result = c_fully_fold ( result , false , & maybe_const ) ; return result ; } </s>

In addition to calling fold_convert for EXPR of type TYPE , also call c_fully_fold to remove any C_MAYBE_CONST_EXPRs that could be hiding there ( PR47197 ) .


<s> static void nvptx_assemble_value ( unsigned HOST_WIDE_INT val , unsigned size ) { val &= ( ( unsigned HOST_WIDE_INT ) 2 << ( size * BITS_PER_UNIT - 1 ) ) - 1 ; for ( unsigned part = 0 ; size ; size -= part ) { val >>= part * BITS_PER_UNIT ; part = init_frag . size - init_frag . offset ; if ( part > size ) part = size ; unsigned HOST_WIDE_INT partial = val << ( init_frag . offset * BITS_PER_UNIT ) ; init_frag . val |= partial & init_frag . mask ; init_frag . offset += part ; if ( init_frag . offset == init_frag . size ) output_init_frag ( NULL ) ; } } </s>

Add value VAL sized SIZE to the data we 're emitting , and keep writing out chunks as they fill up .


<s> static void abort_with_insn ( rtx insn , const char * reason ) { error ( reason ) ; debug_rtx ( insn ) ; fancy_abort ( __FILE__ , __LINE__ , __FUNCTION__ ) ; } </s>

Abort after printing out a specific insn .


<s> NVPTXSubtarget & NVPTXSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { TargetName = CPU . empty ( ) ? "sm_20" : CPU ; ParseSubtargetFeatures ( TargetName , FS ) ; if ( PTXVersion == 0 ) { PTXVersion = 32 ; } return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


Return the DataLayout associated with the module this SCEV instance is operating on .


<s> ARMSubtarget :: ARMSubtarget ( const Module & M , const std :: string & FS , bool thumb ) : ARMArchVersion ( V4T ) , HasVFP2 ( false ) , IsThumb ( thumb ) , UseThumbBacktraces ( false ) , IsR9Reserved ( false ) , stackAlignment ( 4 ) , TargetType ( isELF ) , TargetABI ( ARM_ABI_APCS ) { std :: string CPU = "generic" ; ParseSubtargetFeatures ( FS , CPU ) ; const std :: string & TT = M . getTargetTriple ( ) ; unsigned Len = TT . length ( ) ; unsigned Idx = 0 ; if ( Len >= 5 && TT . substr ( 0 , 4 ) == "armv" ) Idx = 4 ; else if ( Len >= 6 && TT . substr ( 0 , 6 ) == "thumb" ) { IsThumb = true ; if ( Len >= 7 && TT [ 5 ] == 'v' ) Idx = 6 ; } if ( Idx ) { unsigned SubVer = TT [ Idx ] ; if ( SubVer > '4' && SubVer <= '9' ) { if ( SubVer >= '6' ) ARMArchVersion = V6 ; else if ( SubVer == '5' ) { ARMArchVersion = V5T ; if ( Len >= Idx + 3 && TT [ Idx + 1 ] == 't' && TT [ Idx + 2 ] == 'e' ) ARMArchVersion = V5TE ; } } } if ( Len >= 10 ) { if ( TT . find ( "-darwin" ) != std :: string :: npos ) TargetType = isDarwin ; } else if ( TT . empty ( ) ) { TargetType = isDarwin ; } if ( TT . find ( "eabi" ) != std :: string :: npos ) TargetABI = ARM_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = 8 ; if ( isTargetDarwin ( ) ) { UseThumbBacktraces = true ; IsR9Reserved = true ; } } </s>

This constructor initializes the data members to match that of the specified triple .


<s> void ARMInstPrinter :: printInst ( const MCInst * MI ) { printInstruction ( MI ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


"unknown value %qs for 'tune' target %s"

Handle the argument STR to the tune= target attribute . PRAGMA_OR_ATTR is used in potential error messages .


<s> std :: pair < unsigned , const TargetRegisterClass * > PPCTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'b' : if ( VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RC_NOX0RegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRC_NOR0RegClass ) ; case 'r' : if ( VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RCRegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRCRegClass ) ; case 'f' : if ( VT == MVT :: f32 || VT == MVT :: i32 ) return std :: make_pair ( 0U , & PPC :: F4RCRegClass ) ; if ( VT == MVT :: f64 || VT == MVT :: i64 ) return std :: make_pair ( 0U , & PPC :: F8RCRegClass ) ; break ; case 'v' : return std :: make_pair ( 0U , & PPC :: VRRCRegClass ) ; case 'y' : return std :: make_pair ( 0U , & PPC :: CRRCRegClass ) ; } } std :: pair < unsigned , const TargetRegisterClass * > R = TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; if ( R . first && VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) && PPC :: GPRCRegClass . contains ( R . first ) ) { const TargetRegisterInfo * TRI = getTargetMachine ( ) . getRegisterInfo ( ) ; return std :: make_pair ( TRI -> getMatchingSuperReg ( R . first , PPC :: sub_32 , & PPC :: G8RCRegClass ) , & PPC :: G8RCRegClass ) ; } return R ; } </s>

Given a physical register constraint ( e.g .


<s> bool isImm ( ) const override { return Kind == Immediate ; } </s>


<s> bool ARMTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , unsigned Intrinsic ) const { switch ( Intrinsic ) { case Intrinsic :: arm_neon_vld1 : case Intrinsic :: arm_neon_vld2 : case Intrinsic :: arm_neon_vld3 : case Intrinsic :: arm_neon_vld4 : case Intrinsic :: arm_neon_vld2lane : case Intrinsic :: arm_neon_vld3lane : case Intrinsic :: arm_neon_vld4lane : { Info . opc = ISD :: INTRINSIC_W_CHAIN ; uint64_t NumElts = getTargetData ( ) -> getTypeAllocSize ( I . getType ( ) ) / 8 ; Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , MVT :: i64 , NumElts ) ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Value * AlignArg = I . getArgOperand ( I . getNumArgOperands ( ) - 1 ) ; Info . align = cast < ConstantInt > ( AlignArg ) -> getZExtValue ( ) ; Info . vol = false ; Info . readMem = true ; Info . writeMem = false ; return true ; } case Intrinsic :: arm_neon_vst1 : case Intrinsic :: arm_neon_vst2 : case Intrinsic :: arm_neon_vst3 : case Intrinsic :: arm_neon_vst4 : case Intrinsic :: arm_neon_vst2lane : case Intrinsic :: arm_neon_vst3lane : case Intrinsic :: arm_neon_vst4lane : { Info . opc = ISD :: INTRINSIC_VOID ; unsigned NumElts = 0 ; for ( unsigned ArgI = 1 , ArgE = I . getNumArgOperands ( ) ; ArgI < ArgE ; ++ ArgI ) { const Type * ArgTy = I . getArgOperand ( ArgI ) -> getType ( ) ; if ( ! ArgTy -> isVectorTy ( ) ) break ; NumElts += getTargetData ( ) -> getTypeAllocSize ( ArgTy ) / 8 ; } Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , MVT :: i64 , NumElts ) ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Value * AlignArg = I . getArgOperand ( I . getNumArgOperands ( ) - 1 ) ; Info . align = cast < ConstantInt > ( AlignArg ) -> getZExtValue ( ) ; Info . vol = false ; Info . readMem = false ; Info . writeMem = true ; return true ; } default : break ; } return false ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s>
StringRef
getPassName
(
)
const
override
{
return
"MVE gather/scatter lowering"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> unsigned BPFMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups ) const { if ( MO . isReg ( ) ) return getBPFRegisterNumbering ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; assert ( MO . isExpr ( ) ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; assert ( Kind == MCExpr :: SymbolRef ) ; if ( MI . getOpcode ( ) == BPF :: JAL ) { Fixups . push_back ( MCFixup :: Create ( 0 , Expr , FK_SecRel_4 ) ) ; } else if ( MI . getOpcode ( ) == BPF :: LD_imm64 ) { Fixups . push_back ( MCFixup :: Create ( 0 , Expr , FK_SecRel_8 ) ) ; } else { Fixups . push_back ( MCFixup :: Create ( 0 , Expr , FK_PCRel_2 ) ) ; } return 0 ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> bool aarch64_high_bits_all_ones_p ( HOST_WIDE_INT i ) { return exact_log2 ( - i ) != HOST_WIDE_INT_M1 ; } </s>

Return true if I 's bits are consecutive ones from the MSB .


<s> bool MSP430AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: MSP430_INTR ) EmitInterruptVectorSection ( MF ) ; SetupMachineFunction ( MF ) ; EmitFunctionBody ( ) ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> static rtx conditionalize_nonjump ( rtx pat , rtx cond , rtx insn , bool annulled ) { if ( GET_CODE ( pat ) == SET ) { rtx src = SET_SRC ( pat ) ; if ( COMMUTATIVE_P ( src ) ) { rtx src0 = XEXP ( src , 0 ) ; rtx src1 = XEXP ( src , 1 ) ; rtx dst = SET_DEST ( pat ) ; if ( rtx_equal_p ( src1 , dst ) && ! rtx_equal_p ( src0 , dst ) && REG_P ( src0 ) ) pat = gen_rtx_SET ( VOIDmode , dst , gen_rtx_fmt_ee ( GET_CODE ( src ) , GET_MODE ( src ) , src1 , src0 ) ) ; } } if ( RTX_FRAME_RELATED_P ( insn ) ) { gcc_assert ( annulled ) ; rtx note = alloc_reg_note ( REG_FRAME_RELATED_EXPR , pat , REG_NOTES ( insn ) ) ; validate_change ( insn , & REG_NOTES ( insn ) , note , 1 ) ; } pat = gen_rtx_COND_EXEC ( VOIDmode , cond , pat ) ; return pat ; } </s>

Return version of PAT conditionalized with COND , which is part of INSN . ANNULLED indicates if INSN is an annulled delay-slot insn . Register further changes if necessary .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; const PPCSubtarget & STI = MF . getSubtarget < PPCSubtarget > ( ) ; if ( ! STI . hasVSX ( ) ) return false ; LIS = & getAnalysis < LiveIntervals > ( ) ; TII = STI . getInstrInfo ( ) ; bool Changed = false ; if ( DisableVSXFMAMutate ) return Changed ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed = true ; } return Changed ; } </s>


<s> bool X86IndirectBranchTrackingPass :: runOnMachineFunction ( MachineFunction & MF ) { const X86Subtarget & SubTarget = MF . getSubtarget < X86Subtarget > ( ) ; Metadata * isCFProtectionSupported = MF . getMMI ( ) . getModule ( ) -> getModuleFlag ( "cf-protection-branch" ) ; if ( ! isCFProtectionSupported && ! IndirectBranchTracking ) return false ; bool Changed = false ; TII = SubTarget . getInstrInfo ( ) ; EndbrOpcode = SubTarget . is64Bit ( ) ? X86 :: ENDBR64 : X86 :: ENDBR32 ; if ( ( MF . getFunction ( ) . hasAddressTaken ( ) || ! MF . getFunction ( ) . hasLocalLinkage ( ) ) && ! MF . getFunction ( ) . doesNoCfCheck ( ) ) { auto MBB = MF . begin ( ) ; Changed |= addENDBR ( * MBB , MBB -> begin ( ) ) ; } for ( auto & MBB : MF ) { if ( MBB . hasAddressTaken ( ) ) Changed |= addENDBR ( MBB , MBB . begin ( ) ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( ! I -> isCall ( ) ) continue ; if ( IsCallReturnTwice ( I -> getOperand ( 0 ) ) ) Changed |= addENDBR ( MBB , std :: next ( I ) ) ; } } return Changed ; } </s>


"  Copied r%d to a vector register r%d for insn %d\n"

Make vector copies for all register REGNO definitions and replace its uses in a chain .


<s> void ix86_override_options_after_change ( void ) { ix86_default_align ( & global_options ) ; ix86_recompute_optlev_based_flags ( & global_options , & global_options_set ) ; } </s>

Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE hook .


<s> static int arc_address_cost ( rtx addr ) { switch ( GET_CODE ( addr ) ) { case REG : return 1 ; case LABEL_REF : case SYMBOL_REF : case CONST : return 2 ; case PLUS : { register rtx plus0 = XEXP ( addr , 0 ) ; register rtx plus1 = XEXP ( addr , 1 ) ; if ( GET_CODE ( plus0 ) != REG ) break ; switch ( GET_CODE ( plus1 ) ) { case CONST_INT : return SMALL_INT ( plus1 ) ? 1 : 2 ; case CONST : case SYMBOL_REF : case LABEL_REF : return 2 ; default : break ; } break ; } default : break ; } return 4 ; } </s>

Provide the costs of an addressing mode that contains ADDR . If ADDR is not a valid address , its cost is irrelevant .


<s> bool Thumb2ITBlockPass :: runOnMachineFunction ( MachineFunction & Fn ) { const ARMSubtarget & STI = static_cast < const ARMSubtarget & > ( Fn . getSubtarget ( ) ) ; if ( ! STI . isThumb2 ( ) ) return false ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( STI . getInstrInfo ( ) ) ; TRI = STI . getRegisterInfo ( ) ; restrictIT = STI . restrictIT ( ) ; if ( ! AFI -> isThumbFunction ( ) ) return false ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ) { MachineBasicBlock & MBB = * MFI ; ++ MFI ; Modified |= InsertITInstructions ( MBB ) ; } if ( Modified ) AFI -> setHasITBlocks ( true ) ; return Modified ; } </s>


<s> bool PPCAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == ".word" ) ParseDirectiveWord ( 2 , DirectiveID ) ; else if ( IDVal == ".llong" ) ParseDirectiveWord ( 8 , DirectiveID ) ; else if ( IDVal == ".tc" ) ParseDirectiveTC ( isPPC64 ( ) ? 8 : 4 , DirectiveID ) ; else if ( IDVal == ".machine" ) ParseDirectiveMachine ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".abiversion" ) ParseDirectiveAbiVersion ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".localentry" ) ParseDirectiveLocalEntry ( DirectiveID . getLoc ( ) ) ; else if ( IDVal . startswith ( ".gnu_attribute" ) ) ParseGNUAttribute ( DirectiveID . getLoc ( ) ) ; else return true ; return false ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> MVT :: SimpleValueType getCmpLibcallReturnType ( ) const override { return MVT :: i8 ; } </s>

Return the ValueType for comparison libcalls .


<s> unsigned MOSInstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL , int * BytesAdded ) const { const MOSSubtarget & STI = MBB . getParent ( ) -> getSubtarget < MOSSubtarget > ( ) ; MachineIRBuilder Builder ( MBB , MBB . end ( ) ) ; unsigned NumAdded = 0 ; if ( BytesAdded ) * BytesAdded = 0 ; auto * UBB = TBB ; if ( ! Cond . empty ( ) ) { assert ( TBB ) ; assert ( Cond . size ( ) == 2 ) ; UBB = FBB ; Register Reg = Cond [ 0 ] . getReg ( ) ; unsigned Opcode = Reg . isVirtual ( ) || ! MOS :: FlagRegClass . contains ( Reg ) ? MOS :: GBR : MOS :: BR ; auto BR = Builder . buildInstr ( Opcode ) . addMBB ( TBB ) ; for ( const MachineOperand & Op : Cond ) BR . add ( Op ) ; ++ NumAdded ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( * BR ) ; } if ( UBB ) { auto JMP = Builder . buildInstr ( STI . has65C02 ( ) ? MOS :: BRA : MOS :: JMP ) . addMBB ( UBB ) ; ++ NumAdded ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( * JMP ) ; } return NumAdded ; } </s>

Insert branch code into the end of the specified MachineBasicBlock .

MOS MOS MOS MOS 0 0 2 0 MOS::FlagRegClass MOS::GBR MOS::BR MOS::BRA MOS::JMP