<s> DecodeStatus HexagonDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , MemoryObject const & Region , uint64_t Address , raw_ostream & os , raw_ostream & cs ) const { std :: array < uint8_t , 4 > Bytes ; Size = 4 ; if ( Region . readBytes ( Address , Bytes . size ( ) , Bytes . data ( ) ) == - 1 ) { return MCDisassembler :: Fail ; } uint32_t insn = llvm :: support :: endian :: read < uint32_t , llvm :: support :: little , llvm :: support :: unaligned > ( Bytes . data ( ) ) ; insn &= ~ static_cast < uint32_t > ( HexagonII :: InstParseBits :: INST_PARSE_MASK ) ; return decodeInstruction ( DecoderTable32 , MI , insn , Address , this , STI ) ; } </s>

Hexagon Hexagon 4 4 1 support::endian support::little support::unaligned HexagonII::InstParseBits


<s> static rtx frv_expand_mrdacc_builtin ( enum insn_code icode , tree arglist ) { rtx pat ; rtx target = gen_reg_rtx ( SImode ) ; rtx op0 = frv_read_argument ( & arglist ) ; op0 = frv_int_to_acc ( icode , 1 , op0 ) ; if ( ! op0 ) return NULL_RTX ; pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return target ; } </s>

Expand MRDACC and MRDACCG . These builtins take a single accumulator number or accumulator guard number as argument and return an SI integer .


<s> bool X86TargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { const IntrinsicData * IntrData = getIntrinsicWithChain ( Intrinsic ) ; if ( ! IntrData ) return false ; Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . flags = MachineMemOperand :: MONone ; Info . offset = 0 ; switch ( IntrData -> Type ) { case TRUNCATE_TO_MEM_VI8 : case TRUNCATE_TO_MEM_VI16 : case TRUNCATE_TO_MEM_VI32 : { Info . ptrVal = I . getArgOperand ( 0 ) ; MVT VT = MVT :: getVT ( I . getArgOperand ( 1 ) -> getType ( ) ) ; MVT ScalarVT = MVT :: INVALID_SIMPLE_VALUE_TYPE ; if ( IntrData -> Type == TRUNCATE_TO_MEM_VI8 ) ScalarVT = MVT :: i8 ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI16 ) ScalarVT = MVT :: i16 ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI32 ) ScalarVT = MVT :: i32 ; Info . memVT = MVT :: getVectorVT ( ScalarVT , VT . getVectorNumElements ( ) ) ; Info . align = 1 ; Info . flags |= MachineMemOperand :: MOStore ; break ; } default : return false ; } return true ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> bool sh2a_function_vector_p ( tree func ) { if ( TREE_CODE ( func ) != FUNCTION_DECL ) return false ; for ( tree list = SH_ATTRIBUTES ( func ) ; list ; list = TREE_CHAIN ( list ) ) if ( is_attribute_p ( "function_vector" , TREE_PURPOSE ( list ) ) ) return true ; return false ; } </s>

Returns true if FUNC has been assigned the attribute `` function_vector '' .


<s> static void arm_output_mi_thunk ( FILE * file , tree thunk , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { const char * fnname = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( thunk ) ) ; assemble_start_function ( thunk , fnname ) ; if ( TARGET_32BIT ) arm32_output_mi_thunk ( file , thunk , delta , vcall_offset , function ) ; else arm_thumb1_mi_thunk ( file , thunk , delta , vcall_offset , function ) ; assemble_end_function ( thunk , fnname ) ; } </s>

Output code to add DELTA to the first argument , and then jump to FUNCTION . Used for C++ multiple inheritance .


<s> bool RISCVAsmBackend :: fixupNeedsRelaxationAdvanced ( const MCFixup & Fixup , bool Resolved , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout , const bool WasForced ) const { if ( ! Resolved && ! WasForced ) return true ; int64_t Offset = int64_t ( Value ) ; switch ( Fixup . getTargetKind ( ) ) { default : return false ; case RISCV :: fixup_riscv_rvc_branch : return Offset > 254 || Offset < - 256 ; case RISCV :: fixup_riscv_rvc_jump : return Offset > 2046 || Offset < - 2048 ; } } </s>

Target specific predicate for whether a given fixup requires the associated instruction to be relaxed .


<s> static void save_restore_insns ( int prologue ) { rtx base_reg_rtx , reg_rtx , mem_rtx , isr_reg_rtx = 0 , isr_mem_rtx = 0 ; rtx isr_msr_rtx = 0 , insn ; long mask = current_frame_info . mask ; HOST_WIDE_INT gp_offset ; int regno ; if ( frame_pointer_needed && ! BITSET_P ( mask , HARD_FRAME_POINTER_REGNUM - GP_REG_FIRST ) ) gcc_unreachable ( ) ; if ( mask == 0 ) return ; gp_offset = current_frame_info . gp_offset ; gcc_assert ( gp_offset > 0 ) ; base_reg_rtx = stack_pointer_rtx ; if ( microblaze_is_interrupt_variant ( ) ) { isr_mem_rtx = gen_rtx_MEM ( SImode , gen_rtx_PLUS ( Pmode , base_reg_rtx , GEN_INT ( current_frame_info . gp_offset - UNITS_PER_WORD ) ) ) ; MEM_VOLATILE_P ( isr_mem_rtx ) = 1 ; isr_reg_rtx = gen_rtx_REG ( SImode , MB_ABI_MSR_SAVE_REG ) ; isr_msr_rtx = gen_rtx_REG ( SImode , ST_REG ) ; } if ( microblaze_is_interrupt_variant ( ) && ! prologue ) { emit_move_insn ( isr_reg_rtx , isr_mem_rtx ) ; emit_move_insn ( isr_msr_rtx , isr_reg_rtx ) ; emit_insn ( gen_rtx_USE ( SImode , isr_reg_rtx ) ) ; emit_insn ( gen_rtx_USE ( SImode , isr_msr_rtx ) ) ; } for ( regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) { if ( BITSET_P ( mask , regno - GP_REG_FIRST ) ) { if ( regno == MB_ABI_SUB_RETURN_ADDR_REGNUM ) continue ; reg_rtx = gen_rtx_REG ( SImode , regno ) ; insn = gen_rtx_PLUS ( Pmode , base_reg_rtx , GEN_INT ( gp_offset ) ) ; mem_rtx = gen_rtx_MEM ( SImode , insn ) ; if ( microblaze_is_interrupt_variant ( ) || save_volatiles ) MEM_VOLATILE_P ( mem_rtx ) = 1 ; if ( prologue ) { insn = emit_move_insn ( mem_rtx , reg_rtx ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } else { insn = emit_move_insn ( reg_rtx , mem_rtx ) ; } gp_offset += GET_MODE_SIZE ( SImode ) ; } } if ( microblaze_is_interrupt_variant ( ) && prologue ) { emit_move_insn ( isr_reg_rtx , isr_msr_rtx ) ; emit_move_insn ( isr_mem_rtx , isr_reg_rtx ) ; emit_insn ( gen_rtx_USE ( SImode , isr_reg_rtx ) ) ; emit_insn ( gen_rtx_USE ( SImode , isr_msr_rtx ) ) ; } } </s>

Save or restore instructions based on whether this is the prologue or epilogue . prologue is 1 for the prologue .


<s> unsigned RISCVAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { RISCVOperand & Op = static_cast < RISCVOperand & > ( AsmOp ) ; if ( ! Op . isReg ( ) ) return Match_InvalidOperand ; MCRegister Reg = Op . getReg ( ) ; bool IsRegFPR64 = RISCVMCRegisterClasses [ RISCV :: FPR64RegClassID ] . contains ( Reg ) ; bool IsRegFPR64C = RISCVMCRegisterClasses [ RISCV :: FPR64CRegClassID ] . contains ( Reg ) ; if ( ( IsRegFPR64 && Kind == MCK_FPR32 ) || ( IsRegFPR64C && Kind == MCK_FPR32C ) ) { Op . Reg . RegNum = convertFPR64ToFPR32 ( Reg ) ; return Match_Success ; } if ( IsRegFPR64 && Kind == MCK_FPR16 ) { Op . Reg . RegNum = convertFPR64ToFPR16 ( Reg ) ; return Match_Success ; } return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> void rs6000_call_aix ( rtx value , rtx func_desc , rtx flag , rtx cookie ) { const bool direct_call_p = GET_CODE ( func_desc ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( func_desc ) ; rtx toc_reg = gen_rtx_REG ( Pmode , TOC_REGNUM ) ; rtx toc_load = NULL_RTX ; rtx toc_restore = NULL_RTX ; rtx func_addr ; rtx abi_reg = NULL_RTX ; rtx call [ 4 ] ; int n_call ; rtx insn ; if ( INTVAL ( cookie ) & CALL_LONG ) func_desc = rs6000_longcall_ref ( func_desc ) ; if ( GET_CODE ( func_desc ) != SYMBOL_REF || ( DEFAULT_ABI == ABI_AIX && ! SYMBOL_REF_FUNCTION_P ( func_desc ) ) ) { rtx stack_ptr = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; rtx stack_toc_offset = GEN_INT ( RS6000_TOC_SAVE_SLOT ) ; rtx stack_toc_mem = gen_frame_mem ( Pmode , gen_rtx_PLUS ( Pmode , stack_ptr , stack_toc_offset ) ) ; rtx stack_toc_unspec = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , stack_toc_offset ) , UNSPEC_TOCSLOT ) ; toc_restore = gen_rtx_SET ( toc_reg , stack_toc_unspec ) ; if ( TARGET_SAVE_TOC_INDIRECT && ! cfun -> calls_alloca ) cfun -> machine -> save_toc_in_prologue = true ; else { MEM_VOLATILE_P ( stack_toc_mem ) = 1 ; emit_move_insn ( stack_toc_mem , toc_reg ) ; } if ( DEFAULT_ABI == ABI_ELFv2 ) { func_addr = gen_rtx_REG ( Pmode , 12 ) ; emit_move_insn ( func_addr , func_desc ) ; abi_reg = func_addr ; } else { func_desc = force_reg ( Pmode , func_desc ) ; func_addr = gen_reg_rtx ( Pmode ) ; emit_move_insn ( func_addr , gen_rtx_MEM ( Pmode , func_desc ) ) ; rtx func_toc_offset = GEN_INT ( GET_MODE_SIZE ( Pmode ) ) ; rtx func_toc_mem = gen_rtx_MEM ( Pmode , gen_rtx_PLUS ( Pmode , func_desc , func_toc_offset ) ) ; toc_load = gen_rtx_USE ( VOIDmode , func_toc_mem ) ; if ( ! direct_call_p && TARGET_POINTERS_TO_NESTED_FUNCTIONS && ! chain_already_loaded ( get_current_sequence ( ) -> next -> last ) ) { rtx sc_reg = gen_rtx_REG ( Pmode , STATIC_CHAIN_REGNUM ) ; rtx func_sc_offset = GEN_INT ( 2 * GET_MODE_SIZE ( Pmode ) ) ; rtx func_sc_mem = gen_rtx_MEM ( Pmode , gen_rtx_PLUS ( Pmode , func_desc , func_sc_offset ) ) ; emit_move_insn ( sc_reg , func_sc_mem ) ; abi_reg = sc_reg ; } } } else { abi_reg = toc_reg ; func_addr = func_desc ; } call [ 0 ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_addr ) , flag ) ; if ( value != NULL_RTX ) call [ 0 ] = gen_rtx_SET ( value , call [ 0 ] ) ; n_call = 1 ; if ( toc_load ) call [ n_call ++ ] = toc_load ; if ( toc_restore ) call [ n_call ++ ] = toc_restore ; call [ n_call ++ ] = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( n_call , call ) ) ; insn = emit_call_insn ( insn ) ; if ( abi_reg ) use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , abi_reg ) ; } </s>

Expand code to perform a call under the AIX or ELFv2 ABI .


<s>
void
Mips16InstrInfo
::
adjustStackPtr
(
unsigned
SP
,
int64_t
Amount
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
DebugLoc
DL
=
I
!=
MBB
.
end
(
)
I
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
if
(
isInt
<
16
>
(
Amount
)
)
{
if
(
Amount
<
0
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
SaveDecSpF16
)
)
.
addImm
(
Amount
)
;
else
if
(
Amount
>
0
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
RestoreIncSpF16
)
)
.
addImm
(
Amount
)
;
}
else
assert
(
false
&&
"adjust stack pointer amount exceeded"
)
;
}
</s>


<s>
void
NVPTXAsmPrinter
::
emitHeader
(
Module
&
M
,
raw_ostream
&
O
,
const
NVPTXSubtarget
&
STI
)
{
O
<<
"//\n"
;
O
<<
"// Generated by LLVM NVPTX Back-End\n"
;
O
<<
"//\n"
;
O
<<
"\n"
;
unsigned
PTXVersion
=
STI
.
getPTXVersion
(
)
;
O
<<
".version "
<<
(
PTXVersion
/
10
)
<<
"."
<<
(
PTXVersion
%
10
)
<<
"\n"
;
O
<<
".target "
;
O
<<
STI
.
getTargetName
(
)
;
const
NVPTXTargetMachine
&
NTM
=
static_cast
<
const
NVPTXTargetMachine
&
>
(
TM
)
;
if
(
NTM
.
getDrvInterface
(
)
==
NVPTX
::
NVCL
)
O
<<
", texmode_independent"
;
if
(
MMI
&&
MMI
->
hasDebugInfo
(
)
)
O
<<
"//, debug"
;
O
<<
"\n"
;
O
<<
".address_size "
;
if
(
NTM
.
is64Bit
(
)
)
O
<<
"64"
;
else
O
<<
"32"
;
O
<<
"\n"
;
O
<<
"\n"
;
}
</s>

Emit the header for this unit , not including the initial length field .

NVPTX
NVPTX
NVPTX
"//\n"
"// Generated by LLVM NVPTX Back-End\n"
"//\n"
"\n"
".version "
10
"."
10
"\n"
".target "
NVPTX
NVPTX
NVPTX::NVCL
", texmode_independent"
"//, debug"
"\n"
".address_size "
"64"
"32"
"\n"
"\n"


<s>
void
TOYMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
if
(
Desc
.
getSize
(
)
!=
4
)
{
llvm_unreachable
(
"Unexpected instruction size!"
)
;
}
const
uint32_t
Binary
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
EmitConstant
(
Binary
,
Desc
.
getSize
(
)
,
OS
)
;
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .

TOY
TOY
4
"Unexpected instruction size!"


<s> void MetadataStreamerV3 :: begin ( const Module & Mod ) { emitVersion ( ) ; emitPrintf ( Mod ) ; getRootMetadata ( "amdhsa.kernels" ) = HSAMetadataDoc -> getArrayNode ( ) ; } </s>


<s> const char * ARMTargetLowering :: LowerXConstraint ( EVT ConstraintVT ) const { if ( ! Subtarget -> hasVFP2 ( ) ) return "r" ; if ( ConstraintVT . isFloatingPoint ( ) ) return "w" ; if ( ConstraintVT . isVector ( ) && Subtarget -> hasNEON ( ) && ( ConstraintVT . getSizeInBits ( ) == 64 || ConstraintVT . getSizeInBits ( ) == 128 ) ) return "w" ; return "r" ; } </s>

Try to replace an X constraint , which matches anything , with another that has more specific requirements based on the type of the corresponding operand .


<s> rtx ia64_function_value ( tree valtype , tree func ATTRIBUTE_UNUSED ) { enum machine_mode mode ; enum machine_mode hfa_mode ; mode = TYPE_MODE ( valtype ) ; hfa_mode = hfa_element_mode ( valtype , 0 ) ; if ( hfa_mode != VOIDmode ) { rtx loc [ 8 ] ; int i ; int hfa_size ; int byte_size ; int offset ; hfa_size = GET_MODE_SIZE ( hfa_mode ) ; byte_size = ( ( mode == BLKmode ) ? int_size_in_bytes ( valtype ) : GET_MODE_SIZE ( mode ) ) ; offset = 0 ; for ( i = 0 ; offset < byte_size ; i ++ ) { loc [ i ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( hfa_mode , FR_ARG_FIRST + i ) , GEN_INT ( offset ) ) ; offset += hfa_size ; } return gen_rtx_PARALLEL ( mode , gen_rtvec_v ( i , loc ) ) ; } else if ( FLOAT_TYPE_P ( valtype ) && mode != TFmode && mode != TCmode ) return gen_rtx_REG ( mode , FR_ARG_FIRST ) ; else { bool need_parallel = false ; if ( BYTES_BIG_ENDIAN && ( mode == BLKmode || ( valtype && AGGREGATE_TYPE_P ( valtype ) ) ) ) need_parallel = true ; else if ( mode == XFmode || mode == XCmode || mode == RFmode ) need_parallel = true ; if ( need_parallel ) { rtx loc [ 8 ] ; int offset ; int bytesize ; int i ; offset = 0 ; bytesize = int_size_in_bytes ( valtype ) ; if ( bytesize == 0 ) return gen_rtx_REG ( mode , GR_RET_FIRST ) ; for ( i = 0 ; offset < bytesize ; i ++ ) { loc [ i ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , GR_RET_FIRST + i ) , GEN_INT ( offset ) ) ; offset += UNITS_PER_WORD ; } return gen_rtx_PARALLEL ( mode , gen_rtvec_v ( i , loc ) ) ; } return gen_rtx_REG ( mode , GR_RET_FIRST ) ; } } </s>

Return rtx for register that holds the function return value .


"unrecognized interrupt vector argument of %qE attribute"

"numeric argument of %qE attribute must be in range [0-63]"

"argument of %qE attribute is not a string constant "

"%qE attribute only applies to functions"

"critical attribute has no effect on interrupt functions"


<s> inline GCNRegPressure max ( const GCNRegPressure & P1 , const GCNRegPressure & P2 ) { GCNRegPressure Res ; for ( unsigned I = 0 ; I < GCNRegPressure :: TOTAL_KINDS ; ++ I ) Res . Value [ I ] = std :: max ( P1 . Value [ I ] , P2 . Value [ I ] ) ; return Res ; } </s>

Returns the maximum possible frequency , the saturation value .


<s>
const
char
*
arm_output_iwmmxt_tinsr
(
rtx
*
operands
)
{
int
mask
=
INTVAL
(
operands
[
3
]
)
;
int
i
;
char
templ
[
50
]
;
int
units
=
mode_nunits
[
GET_MODE
(
operands
[
0
]
)
]
;
gcc_assert
(
(
mask
&
(
mask
1
)
)
==
0
)
;
for
(
i
=
0
;
i
<
units
;
++
i
)
{
if
(
(
mask
&
0x01
)
==
1
)
{
break
;
}
mask
>>=
1
;
}
gcc_assert
(
i
<
units
)
;
{
switch
(
GET_MODE
(
operands
[
0
]
)
)
{
case
E_V8QImode
:
sprintf
(
templ
,
"tinsrb%%?\t%%0, %%2, #%d"
,
i
)
;
break
;
case
E_V4HImode
:
sprintf
(
templ
,
"tinsrh%%?\t%%0, %%2, #%d"
,
i
)
;
break
;
case
E_V2SImode
:
sprintf
(
templ
,
"tinsrw%%?\t%%0, %%2, #%d"
,
i
)
;
break
;
default
:
gcc_unreachable
(
)
;
break
;
}
output_asm_insn
(
templ
,
operands
)
;
}
return
""
;
}
</s>

Output assembly for a WMMX tinsr instruction .


<s> void ix86_add_new_builtins ( HOST_WIDE_INT isa , HOST_WIDE_INT isa2 ) { isa &= ~ OPTION_MASK_ISA_64BIT ; if ( ( isa & deferred_isa_values ) == 0 && ( isa2 & deferred_isa_values2 ) == 0 && ( ( deferred_isa_values & OPTION_MASK_ISA_MMX ) == 0 || ! ( TARGET_64BIT && ( isa & OPTION_MASK_ISA_SSE2 ) != 0 ) ) ) return ; deferred_isa_values &= ~ isa ; deferred_isa_values2 &= ~ isa2 ; if ( TARGET_64BIT && ( isa & OPTION_MASK_ISA_SSE2 ) != 0 ) deferred_isa_values &= ~ OPTION_MASK_ISA_MMX ; int i ; tree saved_current_target_pragma = current_target_pragma ; current_target_pragma = NULL_TREE ; for ( i = 0 ; i < ( int ) IX86_BUILTIN_MAX ; i ++ ) { if ( ( ( ix86_builtins_isa [ i ] . isa & isa ) != 0 || ( ix86_builtins_isa [ i ] . isa2 & isa2 ) != 0 || ( ( ix86_builtins_isa [ i ] . isa & OPTION_MASK_ISA_MMX ) != 0 && TARGET_64BIT && ( isa & OPTION_MASK_ISA_SSE2 ) != 0 ) ) && ix86_builtins_isa [ i ] . set_and_not_built_p ) { tree decl , type ; ix86_builtins_isa [ i ] . set_and_not_built_p = false ; type = ix86_get_builtin_func_type ( ix86_builtins_isa [ i ] . tcode ) ; decl = add_builtin_function_ext_scope ( ix86_builtins_isa [ i ] . name , type , i , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ i ] = decl ; if ( ix86_builtins_isa [ i ] . const_p ) TREE_READONLY ( decl ) = 1 ; if ( ix86_builtins_isa [ i ] . pure_p ) DECL_PURE_P ( decl ) = 1 ; } } current_target_pragma = saved_current_target_pragma ; } </s>

Add any new builtin functions for a given ISA that may not have been declared . This saves a bit of space compared to adding all of the declarations to the tree , even if we did n't use them .


<s>
MCSymbol
*
X86MCInstLower
::
GetSymbolFromOperand
(
const
MachineOperand
&
MO
)
const
{
const
Triple
&
TT
=
TM
.
getTargetTriple
(
)
;
if
(
MO
.
isGlobal
(
)
&&
TT
.
isOSBinFormatELF
(
)
)
return
AsmPrinter
.
getSymbolPreferLocal
(
*
MO
.
getGlobal
(
)
)
;
const
DataLayout
&
DL
=
MF
.
getDataLayout
(
)
;
assert
(
(
MO
.
isGlobal
(
)
||
MO
.
isSymbol
(
)
||
MO
.
isMBB
(
)
)
&&
"Isn't a symbol reference"
)
;
MCSymbol
*
Sym
=
nullptr
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
switch
(
MO
.
getTargetFlags
(
)
)
{
case
X86II
::
MO_DLLIMPORT
:
Name
+=
"__imp_"
;
break
;
case
X86II
::
MO_COFFSTUB
:
Name
+=
".refptr."
;
break
;
case
X86II
::
MO_DARWIN_NONLAZY
:
case
X86II
::
MO_DARWIN_NONLAZY_PIC_BASE
:
Suffix
=
"$non_lazy_ptr"
;
break
;
}
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
.
getPrivateGlobalPrefix
(
)
;
if
(
MO
.
isGlobal
(
)
)
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
AsmPrinter
.
getNameWithPrefix
(
Name
,
GV
)
;
}
else
if
(
MO
.
isSymbol
(
)
)
{
Mangler
::
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
,
DL
)
;
}
else
if
(
MO
.
isMBB
(
)
)
{
assert
(
Suffix
.
empty
(
)
)
;
Sym
=
MO
.
getMBB
(
)
->
getSymbol
(
)
;
}
Name
+=
Suffix
;
if
(
!
Sym
)
Sym
=
Ctx
.
getOrCreateSymbol
(
Name
)
;
switch
(
MO
.
getTargetFlags
(
)
)
{
default
:
break
;
case
X86II
::
MO_COFFSTUB
:
{
MachineModuleInfoCOFF
&
MMICOFF
=
MF
.
getMMI
(
)
.
getObjFileInfo
<
MachineModuleInfoCOFF
>
(
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
MMICOFF
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AsmPrinter
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
true
)
;
}
break
;
}
case
X86II
::
MO_DARWIN_NONLAZY
:
case
X86II
::
MO_DARWIN_NONLAZY_PIC_BASE
:
{
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
getMachOMMI
(
)
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AsmPrinter
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
break
;
}
}
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


<s>
virtual
void
print
(
raw_ostream
&
O
)
const
{
switch
(
Kind
)
{
case
k_Token
:
O
<<
"Token: \""
<<
getToken
(
)
<<
"\""
;
break
;
case
k_Register
:
O
<<
"Register: "
<<
getReg
(
)
;
break
;
case
k_Immediate
:
O
<<
"Immediate: \""
<<
*
getImm
(
)
<<
"\""
;
break
;
case
k_Memri
:
{
O
<<
"Memri: \""
<<
getReg
(
)
<<
'+'
<<
*
getImm
(
)
<<
"\""
;
break
;
}
}
O
<<
"\n"
;
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> void rs6000_emit_dot_insn ( rtx dst , rtx src , int dot , rtx ccreg ) { if ( dot == 0 ) { emit_move_insn ( dst , src ) ; return ; } if ( cc_reg_not_cr0_operand ( ccreg , CCmode ) ) { emit_move_insn ( dst , src ) ; emit_move_insn ( ccreg , gen_rtx_COMPARE ( CCmode , dst , const0_rtx ) ) ; return ; } rtx ccset = gen_rtx_SET ( ccreg , gen_rtx_COMPARE ( CCmode , src , const0_rtx ) ) ; if ( dot == 1 ) { rtx clobber = gen_rtx_CLOBBER ( VOIDmode , dst ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , ccset , clobber ) ) ) ; } else { rtx set = gen_rtx_SET ( dst , src ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , ccset , set ) ) ) ; } } </s>

Emit a potentially record-form instruction , setting DST from SRC . If DOT is 0 , that is all ; otherwise , set CCREG to the result of the signed comparison of DST with zero . If DOT is 1 , the generated RTL does n't care about the DST result ; if DOT is 2 , it does . If CCREG is CR0 do a single dot insn ( as a PARALLEL ) ; otherwise , do a SET and a separate COMPARE .


<s> void print ( raw_ostream & OS , const TargetRegisterInfo * TRI = nullptr ) const { if ( isReg ( ) ) { OS << printReg ( Contents . R . Reg , TRI , Contents . R . Sub ) ; } if ( isImm ( ) ) { OS << Contents . ImmVal ; } } </s>


<s> bool RISCVTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace = 0 , unsigned Align = 1 , MachineMemOperand :: Flags Flags = MachineMemOperand :: MONone , bool * Fast = nullptr ) const { if ( Subtarget . hasPULPExtV2 ( ) ) { if ( Fast ) { * Fast = false ; } return true ; } return false ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s>
bool
X86CondBrFolding
::
analyzeCompare
(
const
MachineInstr
&
MI
,
unsigned
&
SrcReg
,
int
&
CmpValue
)
{
unsigned
SrcRegIndex
=
0
;
unsigned
ValueIndex
=
0
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
return
false
;
case
X86
::
CMP64ri32
:
case
X86
::
CMP64ri8
:
case
X86
::
CMP32ri
:
case
X86
::
CMP32ri8
:
case
X86
::
CMP16ri
:
case
X86
::
CMP16ri8
:
case
X86
::
CMP8ri
:
SrcRegIndex
=
0
;
ValueIndex
=
1
;
break
;
case
X86
::
SUB64ri32
:
case
X86
::
SUB64ri8
:
case
X86
::
SUB32ri
:
case
X86
::
SUB32ri8
:
case
X86
::
SUB16ri
:
case
X86
::
SUB16ri8
:
case
X86
::
SUB8ri
:
SrcRegIndex
=
1
;
ValueIndex
=
2
;
break
;
}
SrcReg
=
MI
.
getOperand
(
SrcRegIndex
)
.
getReg
(
)
;
assert
(
MI
.
getOperand
(
ValueIndex
)
.
isImm
(
)
&&
"Expecting Imm operand"
)
;
CmpValue
=
MI
.
getOperand
(
ValueIndex
)
.
getImm
(
)
;
return
true
;
}
</s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> void MSP430FrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MSP430MachineFunctionInfo * MSP430FI = MF . getInfo < MSP430MachineFunctionInfo > ( ) ; const MSP430InstrInfo & TII = * static_cast < const MSP430InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; uint64_t NumBytes = 0 ; if ( hasFP ( MF ) ) { uint64_t FrameSize = StackSize - 2 ; NumBytes = FrameSize - MSP430FI -> getCalleeSavedFrameSize ( ) ; MFI -> setOffsetAdjustment ( - NumBytes ) ; BuildMI ( MBB , MBBI , DL , TII . get ( MSP430 :: PUSH16r ) ) . addReg ( MSP430 :: FPW , RegState :: Kill ) ; BuildMI ( MBB , MBBI , DL , TII . get ( MSP430 :: MOV16rr ) , MSP430 :: FPW ) . addReg ( MSP430 :: SPW ) ; for ( MachineFunction :: iterator I = std :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( MSP430 :: FPW ) ; } else NumBytes = StackSize - MSP430FI -> getCalleeSavedFrameSize ( ) ; while ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == MSP430 :: PUSH16r ) ) ++ MBBI ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes ) { if ( NumBytes ) { MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( MSP430 :: SUB16ri ) , MSP430 :: SPW ) . addReg ( MSP430 :: SPW ) . addImm ( NumBytes ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; } } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool MBlazeTargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createMBlazeISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


"No offset range is defined for this opcode. "

"Please define it in the above switch statement!"


<s> static bool sched_mem_operand_p ( rtx_insn * insn , bool opx_p ) { switch ( sched_get_opxy_mem_type ( insn , opx_p ) ) { case OP_TYPE_MEM1 : case OP_TYPE_MEM6 : return true ; default : return false ; } } </s>

Return true , if X or Y ( depending on OPX_P ) operand of INSN is a MEM .


<s> bool AArch64TargetLowering :: shouldExpandGetActiveLaneMask ( EVT ResVT , EVT OpVT ) const { if ( ! Subtarget -> hasSVE ( ) ) return true ; if ( ResVT != MVT :: nxv2i1 && ResVT != MVT :: nxv4i1 && ResVT != MVT :: nxv8i1 && ResVT != MVT :: nxv16i1 ) return true ; if ( OpVT != MVT :: i32 && OpVT != MVT :: i64 ) return true ; return false ; } </s>

Return true if the @ llvm.get.active.lane.mask intrinsic should be expanded using generic code in SelectionDAGBuilder .


<s> static enum insn_code tilegx_multiply_get_opcode ( const struct tilegx_multiply_insn_seq_entry * entry ) { return tilegx_multiply_insn_seq_decode_opcode [ entry -> compressed_opcode ] ; } </s>


<s> bool MipsDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < MipsSubtarget > ( ) ; bool Ret = SelectionDAGISel :: runOnMachineFunction ( MF ) ; processFunctionAfterISel ( MF ) ; return Ret ; } </s>

runOnMachineFunction - Emit the function body .


<s>
bool
AArch64CallLowering
::
lowerReturn
(
MachineIRBuilder
&
MIRBuilder
,
const
Value
*
Val
,
unsigned
VReg
)
const
{
MachineFunction
&
MF
=
MIRBuilder
.
getMF
(
)
;
const
Function
&
F
=
*
MF
.
getFunction
(
)
;
auto
MIB
=
MIRBuilder
.
buildInstrNoInsert
(
AArch64
::
RET_ReallyLR
)
;
assert
(
(
(
Val
&&
VReg
)
||
(
!
Val
&&
!
VReg
)
)
&&
"Return value without a vreg"
)
;
bool
Success
=
true
;
if
(
VReg
)
{
const
AArch64TargetLowering
&
TLI
=
*
getTLI
<
AArch64TargetLowering
>
(
)
;
CCAssignFn
*
AssignFn
=
TLI
.
CCAssignFnForReturn
(
F
.
getCallingConv
(
)
)
;
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
auto
&
DL
=
F
.
getParent
(
)
->
getDataLayout
(
)
;
ArgInfo
OrigArg
{
VReg
,
Val
->
getType
(
)
}
;
setArgFlags
(
OrigArg
,
AttributeList
::
ReturnIndex
,
DL
,
F
)
;
SmallVector
<
ArgInfo
,
8
>
SplitArgs
;
splitToValueTypes
(
OrigArg
,
SplitArgs
,
DL
,
MRI
,
F
.
getCallingConv
(
)
,
[
&
]
(
unsigned
Reg
,
uint64_t
Offset
)
{
MIRBuilder
.
buildExtract
(
Reg
,
VReg
,
Offset
)
;
}
)
;
OutgoingArgHandler
Handler
(
MIRBuilder
,
MRI
,
MIB
,
AssignFn
,
AssignFn
)
;
Success
=
handleAssignments
(
MIRBuilder
,
SplitArgs
,
Handler
)
;
}
MIRBuilder
.
insertInstr
(
MIB
)
;
return
Success
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> static rtx nvptx_get_unisimt_predicate ( ) { rtx & pred = cfun -> machine -> unisimt_predicate ; return pred ? pred : pred = gen_reg_rtx ( BImode ) ; } </s>

Return a BImode `` predicate '' register for uniform-simt , similar to above .


<s> bool isMemUseUpRegs ( ) const override { return UseUpRegs ; } </s>

isMemUseUpRegs - Is memory operand use up regs , for example , intel MS inline asm may use ARR [ baseReg + IndexReg + ... ] which may use up regs in [ ... ] expr , so ARR [ baseReg + IndexReg + ... ] can not use extra reg for ARR .


<s> void GCNHazardRecognizer :: AdvanceCycle ( ) { if ( ! CurrCycleInstr ) return ; if ( CurrCycleInstr -> getOpcode ( ) == AMDGPU :: IMPLICIT_DEF ) return ; else if ( CurrCycleInstr -> isDebugInstr ( ) ) return ; unsigned NumWaitStates = TII . getNumWaitStates ( * CurrCycleInstr ) ; EmittedInstrs . push_front ( CurrCycleInstr ) ; for ( unsigned i = 1 , e = std :: min ( NumWaitStates , getMaxLookAhead ( ) ) ; i < e ; ++ i ) { EmittedInstrs . push_front ( nullptr ) ; } EmittedInstrs . resize ( getMaxLookAhead ( ) ) ; CurrCycleInstr = nullptr ; } </s>

AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled can not issue in the current cycle , either because of latency or resource conflicts .


<s> const MSP430InstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> bool SystemZFrameInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; SystemZMachineFunctionInfo * MFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; unsigned CalleeFrameSize = 0 ; unsigned LowReg = 0 , HighReg = 0 , StartOffset = - 1U , EndOffset = 0 ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! SystemZ :: FP64RegClass . contains ( Reg ) ) { unsigned Offset = RegSpillOffsets [ Reg ] ; CalleeFrameSize += 8 ; if ( StartOffset > Offset ) { LowReg = Reg ; StartOffset = Offset ; } if ( EndOffset < Offset ) { HighReg = Reg ; EndOffset = RegSpillOffsets [ Reg ] ; } } } MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ; MFI -> setLowReg ( LowReg ) ; MFI -> setHighReg ( HighReg ) ; if ( StartOffset ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( ( LowReg == HighReg ? SystemZ :: MOV64mr : SystemZ :: MOV64mrm ) ) ) ; MIB . addReg ( SystemZ :: R15D ) . addImm ( StartOffset ) ; if ( LowReg == HighReg ) MIB . addReg ( 0 ) ; MIB . addReg ( LowReg , RegState :: Kill ) ; if ( LowReg != HighReg ) MIB . addReg ( HighReg , RegState :: Kill ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; if ( Reg != LowReg && Reg != HighReg ) MIB . addReg ( Reg , RegState :: ImplicitKill ) ; } } for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( SystemZ :: FP64RegClass . contains ( Reg ) ) { MBB . addLiveIn ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i ] . getFrameIdx ( ) , & SystemZ :: FP64RegClass , TRI ) ; } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> static HOST_WIDE_INT nvptx_vector_alignment ( const_tree type ) { unsigned HOST_WIDE_INT align ; tree size = TYPE_SIZE ( type ) ; if ( tree_fits_uhwi_p ( size ) ) { align = tree_to_uhwi ( size ) ; align = MIN ( align , BIGGEST_ALIGNMENT ) ; } else align = BIGGEST_ALIGNMENT ; align = MAX ( align , GET_MODE_ALIGNMENT ( TYPE_MODE ( type ) ) ) ; return align ; } </s>

Limit vector alignments to BIGGEST_ALIGNMENT .


<s> bool X86AsmParser :: processInstruction ( MCInst & Inst , const OperandVector & Ops ) { return false ; } </s>

Process a single instruction and collect debug info anchors .


"ignoring -fschedule-insns because of exception "

"unwind tables currently require either a frame pointer "

"or -maccumulate-outgoing-args for correctness"

Implement TARGET_OPTION_OVERRIDE macro . Validate and override various options , and do some machine dependent initialization .


<s> unsigned ARMBaseInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case ARM :: STRrs : case ARM :: t2STRs : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isReg ( ) && MI . getOperand ( 3 ) . isImm ( ) && MI . getOperand ( 2 ) . getReg ( ) == 0 && MI . getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: STRi12 : case ARM :: t2STRi12 : case ARM :: tSTRspi : case ARM :: VSTRD : case ARM :: VSTRS : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VST1q64 : case ARM :: VST1d64TPseudo : case ARM :: VST1d64QPseudo : if ( MI . getOperand ( 0 ) . isFI ( ) && MI . getOperand ( 2 ) . getSubReg ( ) == 0 ) { FrameIndex = MI . getOperand ( 0 ) . getIndex ( ) ; return MI . getOperand ( 2 ) . getReg ( ) ; } break ; case ARM :: VSTMQIA : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> inline tree get_svbool_t ( void ) { return acle_vector_types [ 0 ] [ VECTOR_TYPE_svbool_t ] ; } </s>


<s> static bool need_to_save_reg ( unsigned int regno ) { if ( ! fixed_regs [ regno ] && ! call_used_regs [ regno ] && df_regs_ever_live_p ( regno ) ) return true ; if ( flag_pic && ( regno == PIC_OFFSET_TABLE_REGNUM || regno == TILEGX_PIC_TEXT_LABEL_REGNUM ) && ( crtl -> uses_pic_offset_table || crtl -> saves_all_registers ) ) return true ; if ( crtl -> calls_eh_return ) { unsigned i ; for ( i = 0 ; EH_RETURN_DATA_REGNO ( i ) != INVALID_REGNUM ; i ++ ) { if ( regno == EH_RETURN_DATA_REGNO ( i ) ) return true ; } } return false ; } </s>

Return whether REGNO needs to be saved in the stack frame .


<s>
void
SparcInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
numSubRegs
=
0
;
unsigned
movOpc
=
0
;
const
unsigned
*
subRegIdx
=
nullptr
;
const
unsigned
DFP_FP_SubRegsIdx
[
]
=
{
SP
::
sub_even
,
SP
::
sub_odd
}
;
const
unsigned
QFP_DFP_SubRegsIdx
[
]
=
{
SP
::
sub_even64
,
SP
::
sub_odd64
}
;
const
unsigned
QFP_FP_SubRegsIdx
[
]
=
{
SP
::
sub_even
,
SP
::
sub_odd
,
SP
::
sub_odd64_then_sub_even
,
SP
::
sub_odd64_then_sub_odd
}
;
if
(
SP
::
IntRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
SP
::
ORrr
)
,
DestReg
)
.
addReg
(
SP
::
G0
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
if
(
SP
::
FPRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
SP
::
FMOVS
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
if
(
SP
::
DFPRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
if
(
Subtarget
.
isV9
(
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
SP
::
FMOVD
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
else
{
subRegIdx
=
DFP_FP_SubRegsIdx
;
numSubRegs
=
2
;
movOpc
=
SP
::
FMOVS
;
}
}
else
if
(
SP
::
QFPRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
if
(
Subtarget
.
isV9
(
)
)
{
if
(
Subtarget
.
hasHardQuad
(
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
SP
::
FMOVQ
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
else
{
subRegIdx
=
QFP_DFP_SubRegsIdx
;
numSubRegs
=
2
;
movOpc
=
SP
::
FMOVD
;
}
}
else
{
subRegIdx
=
QFP_FP_SubRegsIdx
;
numSubRegs
=
4
;
movOpc
=
SP
::
FMOVS
;
}
}
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
if
(
numSubRegs
==
0
||
subRegIdx
==
nullptr
||
movOpc
==
0
)
return
;
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
MachineInstr
*
MovMI
=
nullptr
;
for
(
unsigned
i
=
0
;
i
!=
numSubRegs
;
++
i
)
{
unsigned
Dst
=
TRI
->
getSubReg
(
DestReg
,
subRegIdx
[
i
]
)
;
unsigned
Src
=
TRI
->
getSubReg
(
SrcReg
,
subRegIdx
[
i
]
)
;
assert
(
Dst
&&
Src
&&
"Bad sub-register"
)
;
MovMI
=
BuildMI
(
MBB
,
I
,
DL
,
get
(
movOpc
)
,
Dst
)
.
addReg
(
Src
)
;
}
MovMI
->
addRegisterDefined
(
DestReg
,
TRI
)
;
if
(
KillSrc
)
MovMI
->
addRegisterKilled
(
SrcReg
,
TRI
)
;
}
</s>


<s> ScheduleHazardRecognizer :: HazardType Thumb2HazardRecognizer :: getHazardType ( SUnit * SU ) { if ( ITBlockSize ) { MachineInstr * MI = SU -> getInstr ( ) ; if ( ! MI -> isDebugValue ( ) && MI != ITBlockMIs [ ITBlockSize - 1 ] ) return Hazard ; } return PostRAHazardRecognizer :: getHazardType ( SU ) ; } </s>

getHazardType - Return the hazard type of emitting this node .


<s> StackOffset SIFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const SIRegisterInfo * RI = MF . getSubtarget < GCNSubtarget > ( ) . getRegisterInfo ( ) ; FrameReg = RI -> getFrameRegister ( MF ) ; return StackOffset :: getFixed ( MF . getFrameInfo ( ) . getObjectOffset ( FI ) ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> unsigned MipsMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups ) const { if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; unsigned RegNo = Ctx . getRegisterInfo ( ) . getEncodingValue ( Reg ) ; return RegNo ; } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isFPImm ( ) ) { return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( 32 ) . getLimitedValue ( ) ) ; } assert ( MO . isExpr ( ) ) ; return getExprOpValue ( MO . getExpr ( ) , Fixups ) ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> unsigned MBlazeInstrInfo :: getGlobalBaseReg ( MachineFunction * MF ) const { MBlazeFunctionInfo * MBlazeFI = MF -> getInfo < MBlazeFunctionInfo > ( ) ; unsigned GlobalBaseReg = MBlazeFI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg != 0 ) return GlobalBaseReg ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; const TargetInstrInfo * TII = MF -> getTarget ( ) . getInstrInfo ( ) ; GlobalBaseReg = RegInfo . createVirtualRegister ( MBlaze :: CPURegsRegisterClass ) ; BuildMI ( FirstMBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , GlobalBaseReg ) . addReg ( MBlaze :: R20 ) ; RegInfo . addLiveIn ( MBlaze :: R20 ) ; MBlazeFI -> setGlobalBaseReg ( GlobalBaseReg ) ; return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

MBlaze MBlaze MBlaze MBlaze MBlaze MBlaze 0 MBlaze::CPURegsRegisterClass MBlaze::R20 MBlaze::R20 MBlaze


<s> int SparcSubtarget :: getAdjustedFrameSize ( int frameSize ) const { if ( is64Bit ( ) ) { frameSize += 128 ; frameSize = alignTo ( frameSize , 16 ) ; } else { frameSize += 92 ; frameSize = alignTo ( frameSize , 8 ) ; } return frameSize ; } </s>

Given a actual stack size as determined by FrameInfo , this function returns adjusted framesize which includes space for RSA , return address , and frame poitner .


<s> static tree ix86_d_handle_target_float_abi ( void ) { const char * abi ; if ( ! ( TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ) ) abi = "soft" ; else abi = "hard" ; return build_string_literal ( strlen ( abi ) + 1 , abi ) ; } </s>

Handle a call to ` __traits ( getTargetInfo , `` floatAbi '' ) ' .


<s> void init ( VLIWMachineScheduler * dag , const TargetSchedModel * smodel ) { DAG = dag ; SchedModel = smodel ; } </s>

Initialize the machine model for instruction scheduling .


<s> rtx s390_get_thread_pointer ( void ) { rtx tp = gen_reg_rtx ( Pmode ) ; emit_move_insn ( tp , gen_rtx_REG ( Pmode , TP_REGNUM ) ) ; mark_reg_pointer ( tp , BITS_PER_WORD ) ; return tp ; } </s>

Load the thread pointer into a register .


<s>
bool
SITargetLowering
::
isLegalAddressingMode
(
const
DataLayout
&
DL
,
const
AddrMode
&
AM
,
Type
*
Ty
,
unsigned
AS
,
Instruction
*
I
)
const
{
if
(
AM
.
BaseGV
)
return
false
;
if
(
AS
==
AMDGPUASI
.
GLOBAL_ADDRESS
)
return
isLegalGlobalAddressingMode
(
AM
)
;
if
(
AS
==
AMDGPUASI
.
CONSTANT_ADDRESS
||
AS
==
AMDGPUASI
.
CONSTANT_ADDRESS_32BIT
)
{
if
(
AM
.
BaseOffs
%
4
!=
0
)
return
isLegalMUBUFAddressingMode
(
AM
)
;
if
(
DL
.
getTypeStoreSize
(
Ty
)
<
4
)
return
isLegalGlobalAddressingMode
(
AM
)
;
if
(
Subtarget
->
getGeneration
(
)
==
SISubtarget
::
SOUTHERN_ISLANDS
)
{
if
(
!
isUInt
<
8
>
(
AM
.
BaseOffs
/
4
)
)
return
false
;
}
else
if
(
Subtarget
->
getGeneration
(
)
==
SISubtarget
::
SEA_ISLANDS
)
{
if
(
!
isUInt
<
32
>
(
AM
.
BaseOffs
/
4
)
)
return
false
;
}
else
if
(
Subtarget
->
getGeneration
(
)
>=
SISubtarget
::
VOLCANIC_ISLANDS
)
{
if
(
!
isUInt
<
20
>
(
AM
.
BaseOffs
)
)
return
false
;
}
else
llvm_unreachable
(
"unhandled generation"
)
;
if
(
AM
.
Scale
==
0
)
return
true
;
if
(
AM
.
Scale
==
1
&&
AM
.
HasBaseReg
)
return
true
;
return
false
;
}
else
if
(
AS
==
AMDGPUASI
.
PRIVATE_ADDRESS
)
{
return
isLegalMUBUFAddressingMode
(
AM
)
;
}
else
if
(
AS
==
AMDGPUASI
.
LOCAL_ADDRESS
||
AS
==
AMDGPUASI
.
REGION_ADDRESS
)
{
if
(
!
isUInt
<
16
>
(
AM
.
BaseOffs
)
)
return
false
;
if
(
AM
.
Scale
==
0
)
return
true
;
if
(
AM
.
Scale
==
1
&&
AM
.
HasBaseReg
)
return
true
;
return
false
;
}
else
if
(
AS
==
AMDGPUASI
.
FLAT_ADDRESS
||
AS
==
AMDGPUASI
.
UNKNOWN_ADDRESS_SPACE
)
{
return
isLegalFlatAddressingMode
(
AM
)
;
}
else
{
llvm_unreachable
(
"unhandled address space"
)
;
}
}
</s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> std :: pair < unsigned , const TargetRegisterClass * > PPCTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'b' : if ( VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RC_NOX0RegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRC_NOR0RegClass ) ; case 'r' : if ( VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RCRegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRCRegClass ) ; case 'f' : if ( VT == MVT :: f32 || VT == MVT :: i32 ) return std :: make_pair ( 0U , & PPC :: F4RCRegClass ) ; if ( VT == MVT :: f64 || VT == MVT :: i64 ) return std :: make_pair ( 0U , & PPC :: F8RCRegClass ) ; break ; case 'v' : return std :: make_pair ( 0U , & PPC :: VRRCRegClass ) ; case 'y' : return std :: make_pair ( 0U , & PPC :: CRRCRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> virtual const rvexInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> static machine_mode rs6000_eh_return_filter_mode ( void ) { return TARGET_32BIT ? SImode : word_mode ; } </s>


"ARC DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> static bool z8k_function_value_regno_p ( const unsigned int regno ) { return TARGET_STD_RET ? ( regno >= 4 && regno <= 7 ) : regno == 2 ; } </s>

True if N is a possible register number for a function value as seen by the caller .


For stack frames that ca n't be allocated with a single ADDI instruction , compute the best value to initially allocate . It must at a minimum allocate enough space to spill the callee-saved registers .


<s> bool mips_expand_ext_as_unaligned_load ( rtx dest , rtx src , HOST_WIDE_INT width , HOST_WIDE_INT bitpos , bool unsigned_p ) { rtx left , right , temp ; rtx dest1 = NULL_RTX ; if ( GET_MODE ( dest ) == DImode && ( REG_P ( dest ) || ( SUBREG_P ( dest ) && ! MEM_P ( SUBREG_REG ( dest ) ) ) ) && GET_MODE_BITSIZE ( SImode ) == width ) { dest1 = dest ; dest = gen_reg_rtx ( SImode ) ; } if ( ! mips_get_unaligned_mem ( src , width , bitpos , & left , & right ) ) return false ; temp = gen_reg_rtx ( GET_MODE ( dest ) ) ; if ( GET_MODE ( dest ) == DImode ) { emit_insn ( gen_mov_ldl ( temp , src , left ) ) ; emit_insn ( gen_mov_ldr ( dest , copy_rtx ( src ) , right , temp ) ) ; } else { emit_insn ( gen_mov_lwl ( temp , src , left ) ) ; emit_insn ( gen_mov_lwr ( dest , copy_rtx ( src ) , right , temp ) ) ; } if ( dest1 ) { if ( unsigned_p ) emit_insn ( gen_zero_extendsidi2 ( dest1 , dest ) ) ; else emit_insn ( gen_extendsidi2 ( dest1 , dest ) ) ; } return true ; } </s>

Try to use left/right loads to expand an `` extv '' or `` extzv '' pattern . DEST , SRC , WIDTH and BITPOS are the operands passed to the expander ; the operation is the equivalent of : ( set DEST ( * _extract SRC WIDTH BITPOS ) ) Return true on success .


<s> static unsigned riscv_pass_mode_in_fpr_p ( enum machine_mode mode ) { if ( GET_MODE_UNIT_SIZE ( mode ) <= UNITS_PER_FP_ARG ) { if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return 1 ; if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) return 2 ; } return 0 ; } </s>

If MODE represents an argument that can be passed or returned in floating-point registers , return the number of registers , else 0 .


<s> bool insertEdge ( Register Reg ) { return Edges . insert ( Reg ) . second ; } </s>

Update the call graph after inserting a new edge .


<s> RegisterBankInfo :: InstructionMappings AArch64RegisterBankInfo :: getInstrAlternativeMappings ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_OR : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned Size = getSizeInBits ( MI . getOperand ( 0 ) . getReg ( ) , MRI , TRI ) ; if ( Size != 32 && Size != 64 ) break ; if ( MI . getNumOperands ( ) != 3 ) break ; InstructionMappings AltMappings ; InstructionMapping GPRMapping ( 1 , 1 , 3 ) ; InstructionMapping FPRMapping ( 2 , 1 , 3 ) ; for ( unsigned Idx = 0 ; Idx != 3 ; ++ Idx ) { GPRMapping . setOperandMapping ( Idx , Size , getRegBank ( AArch64 :: GPRRegBankID ) ) ; FPRMapping . setOperandMapping ( Idx , Size , getRegBank ( AArch64 :: FPRRegBankID ) ) ; } AltMappings . emplace_back ( std :: move ( GPRMapping ) ) ; AltMappings . emplace_back ( std :: move ( FPRMapping ) ) ; return AltMappings ; } default : break ; } return RegisterBankInfo :: getInstrAlternativeMappings ( MI ) ; } </s>


<s> static rtx nvptx_function_value ( const_tree type , const_tree ARG_UNUSED ( func ) , bool outgoing ) { machine_mode mode = promote_return ( TYPE_MODE ( type ) ) ; if ( outgoing ) { gcc_assert ( cfun ) ; cfun -> machine -> return_mode = mode ; return gen_rtx_REG ( mode , NVPTX_RETURN_REGNUM ) ; } return nvptx_libcall_value ( mode , NULL_RTX ) ; } </s>

TARGET_FUNCTION_VALUE implementation . Returns an RTX representing the place where function FUNC returns or receives a value of data type TYPE .


Targets may add passes immediately before machine code is emitted in this callback .


<s> bool SPIRVPassConfig :: addIRTranslator ( ) { addPass ( new IRTranslator ( getOptLevel ( ) ) ) ; return false ; } </s>

This method should install an IR translator pass , which converts from LLVM code to machine instructions with possibly generic opcodes .


<s> bool n9_3r2w_consumed_by_ex_dep_p ( rtx_insn * consumer , rtx def_reg ) { rtx use_rtx ; switch ( get_attr_type ( consumer ) ) { case TYPE_ALU : case TYPE_PBSAD : case TYPE_MUL : use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_ALU_SHIFT : use_rtx = extract_shift_reg ( consumer ) ; break ; case TYPE_PBSADA : return pbsada_insn_ra_rb_dep_reg_p ( consumer , def_reg ) ; case TYPE_MAC : use_rtx = extract_mac_non_acc_rtx ( consumer ) ; break ; case TYPE_DIV : if ( INSN_CODE ( consumer ) == CODE_FOR_divmodsi4 || INSN_CODE ( consumer ) == CODE_FOR_udivmodsi4 ) use_rtx = SET_SRC ( parallel_element ( consumer , 0 ) ) ; else use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_MMU : if ( GET_CODE ( PATTERN ( consumer ) ) == SET ) use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; else return true ; break ; case TYPE_LOAD : case TYPE_STORE : use_rtx = extract_mem_rtx ( consumer ) ; break ; case TYPE_LOAD_MULTIPLE : case TYPE_STORE_MULTIPLE : use_rtx = extract_base_reg ( consumer ) ; break ; case TYPE_BRANCH : use_rtx = PATTERN ( consumer ) ; break ; default : gcc_unreachable ( ) ; } if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; return false ; } </s>

Check the dependency between the producer defining DEF_REG and CONSUMER requiring input operand at EX .


<s> static bool s390_expand_vec_compare_scalar ( enum rtx_code * code , rtx cmp1 , rtx cmp2 , rtx * cc ) { machine_mode cmp_mode ; bool swap_p = false ; switch ( * code ) { case EQ : cmp_mode = CCVEQmode ; break ; case NE : cmp_mode = CCVEQmode ; break ; case GT : cmp_mode = CCVFHmode ; break ; case GE : cmp_mode = CCVFHEmode ; break ; case UNLE : cmp_mode = CCVFHmode ; break ; case UNLT : cmp_mode = CCVFHEmode ; break ; case LT : cmp_mode = CCVFHmode ; * code = GT ; swap_p = true ; break ; case LE : cmp_mode = CCVFHEmode ; * code = GE ; swap_p = true ; break ; case UNGE : cmp_mode = CCVFHmode ; * code = UNLE ; swap_p = true ; break ; case UNGT : cmp_mode = CCVFHEmode ; * code = UNLT ; swap_p = true ; break ; default : return false ; } if ( swap_p ) { rtx tmp = cmp2 ; cmp2 = cmp1 ; cmp1 = tmp ; } * cc = gen_rtx_REG ( cmp_mode , CC_REGNUM ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , gen_rtx_SET ( * cc , gen_rtx_COMPARE ( cmp_mode , cmp1 , cmp2 ) ) , gen_rtx_CLOBBER ( VOIDmode , gen_rtx_SCRATCH ( V2DImode ) ) ) ) ) ; return true ; } </s>

Helper function for s390_emit_compare . If possible emit a 64 bit FP compare using the single element variant of vector instructions . Replace CODE with the comparison code to be used in the CC reg compare and return the condition code register RTX in CC .


<s> TargetPassConfig * XtensaTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new XtensaPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> static bool tilegx_scalar_mode_supported_p ( machine_mode mode ) { switch ( mode ) { case QImode : case HImode : case SImode : case DImode : case TImode : return true ; case SFmode : case DFmode : return true ; default : return false ; } } </s>


<s> BitVector SystemZRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( SystemZ :: R11D ) ; Reserved . set ( SystemZ :: R11W ) ; Reserved . set ( SystemZ :: R10Q ) ; } Reserved . set ( SystemZ :: R15D ) ; Reserved . set ( SystemZ :: R15W ) ; Reserved . set ( SystemZ :: R14Q ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static void ft32_setup_incoming_varargs ( cumulative_args_t cum_v , const function_arg_info & arg , int * pretend_size , int no_rtl ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int named_size = 0 ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) ) named_size = GET_MODE_SIZE ( SImode ) * ( * cum - FT32_R0 ) + GET_MODE_SIZE ( arg . mode ) ; if ( named_size < 24 ) * pretend_size = 24 - named_size ; else * pretend_size = 0 ; } </s>

Worker function for TARGET_SETUP_INCOMING_VARARGS .


<s> unsigned SNESAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned ExpectedKind ) { SNESOperand & Op = static_cast < SNESOperand & > ( AsmOp ) ; MatchClassKind Expected = static_cast < MatchClassKind > ( ExpectedKind ) ; if ( Op . isImm ( ) ) { if ( MCConstantExpr const * Const = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ) { int64_t RegNum = Const -> getValue ( ) ; std :: ostringstream RegName ; RegName << "r" << RegNum ; RegNum = MatchRegisterName ( RegName . str ( ) . c_str ( ) ) ; if ( RegNum != SNES :: NoRegister ) { Op . makeReg ( RegNum ) ; if ( validateOperandClass ( Op , Expected ) == Match_Success ) { return Match_Success ; } } } } if ( Op . isReg ( ) ) { if ( isSubclass ( Expected , MCK_MainRegs ) ) { unsigned correspondingDREG = toDREG ( Op . getReg ( ) ) ; if ( correspondingDREG != SNES :: NoRegister ) { Op . makeReg ( correspondingDREG ) ; return validateOperandClass ( Op , Expected ) ; } } } return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .

SNES SNES SNES SNES "r" SNES::NoRegister SNES::NoRegister


<s> static bool avr_hard_regno_call_part_clobbered ( unsigned regno , machine_mode mode ) { if ( ! avr_hard_regno_mode_ok ( regno , mode ) ) return 0 ; return ( ( regno <= LAST_CALLEE_SAVED_REG && regno + GET_MODE_SIZE ( mode ) > 1 + LAST_CALLEE_SAVED_REG ) || ( regno < REG_Y && regno + GET_MODE_SIZE ( mode ) > REG_Y ) || ( regno < REG_Z && regno + GET_MODE_SIZE ( mode ) > REG_Z ) ) ; } </s>

Implement ` HARD_REGNO_CALL_PART_CLOBBERED ' .


"Opcode has no flag setting equivalent!"

Return the opcode that set flags when possible .


<s> static void arc_setup_incoming_varargs ( cumulative_args_t args_so_far , const function_arg_info & arg , int * pretend_size , int no_rtl ) { int first_anon_arg ; CUMULATIVE_ARGS next_cum ; next_cum = * get_cumulative_args ( args_so_far ) ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) ) arc_function_arg_advance ( pack_cumulative_args ( & next_cum ) , arg ) ; first_anon_arg = next_cum ; if ( FUNCTION_ARG_REGNO_P ( first_anon_arg ) ) { int first_reg_offset = first_anon_arg ; if ( ! no_rtl ) { rtx regblock = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , arg_pointer_rtx , FIRST_PARM_OFFSET ( 0 ) ) ) ; move_block_from_reg ( first_reg_offset , regblock , MAX_ARC_PARM_REGS - first_reg_offset ) ; } * pretend_size = ( ( MAX_ARC_PARM_REGS - first_reg_offset ) * UNITS_PER_WORD ) ; } } </s>

Do any needed setup for a variadic function . For the ARC , we must create a register parameter block , and then copy any anonymous arguments in registers to memory . CUM has not been updated for the last named argument which has type TYPE and mode MODE , and we rely on this fact .


<s> static void visium_add_cfa_restore_note ( rtx reg ) { cfa_restores = alloc_reg_note ( REG_CFA_RESTORE , reg , cfa_restores ) ; } </s>

Queue a REG_CFA_RESTORE note until next stack manipulation insn .


<s> bool PPCTargetLowering :: SelectAddressRegReg ( SDValue N , SDValue & Base , SDValue & Index , SelectionDAG & DAG , MaybeAlign EncodingAlignment ) const { if ( SelectAddressPCRel ( N , Base ) ) return false ; int16_t Imm = 0 ; if ( N . getOpcode ( ) == ISD :: ADD ) { if ( hasSPE ( ) && SelectAddressEVXRegReg ( N , Base , Index , DAG ) ) return true ; if ( isIntS16Immediate ( N . getOperand ( 1 ) , Imm ) && ( ! EncodingAlignment || isAligned ( * EncodingAlignment , Imm ) ) ) return false ; if ( N . getOperand ( 1 ) . getOpcode ( ) == PPCISD :: Lo ) return false ; Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } else if ( N . getOpcode ( ) == ISD :: OR ) { if ( isIntS16Immediate ( N . getOperand ( 1 ) , Imm ) && ( ! EncodingAlignment || isAligned ( * EncodingAlignment , Imm ) ) ) return false ; KnownBits LHSKnown = DAG . computeKnownBits ( N . getOperand ( 0 ) ) ; if ( LHSKnown . Zero . getBoolValue ( ) ) { KnownBits RHSKnown = DAG . computeKnownBits ( N . getOperand ( 1 ) ) ; if ( ~ ( LHSKnown . Zero | RHSKnown . Zero ) == 0 ) { Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } } } return false ; } </s>

SelectAddressRegReg - Given the specified addressed , check to see if it can be more efficiently represented as [ r+imm ] .


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const TargetInstrInfo & TII , const DebugLoc & dl , const ThumbRegisterInfo & MRI , int NumBytes , unsigned MIFlags = MachineInstr :: NoFlags ) { emitThumbRegPlusImmediate ( MBB , MBBI , dl , ARM :: SP , ARM :: SP , NumBytes , TII , MRI , MIFlags ) ; } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> BitVector TGSIRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector rsv ( getNumRegs ( ) ) ; rsv . set ( TGSI :: TEMP0x ) ; rsv . set ( TGSI :: TEMP0y ) ; rsv . set ( TGSI :: TEMP0z ) ; rsv . set ( TGSI :: TEMP0w ) ; rsv . set ( TGSI :: TEMP0 ) ; rsv . set ( TGSI :: SV0x ) ; rsv . set ( TGSI :: SV0y ) ; rsv . set ( TGSI :: SV0z ) ; rsv . set ( TGSI :: SV0w ) ; rsv . set ( TGSI :: SV0 ) ; rsv . set ( TGSI :: SV1x ) ; rsv . set ( TGSI :: SV1y ) ; rsv . set ( TGSI :: SV1z ) ; rsv . set ( TGSI :: SV1w ) ; rsv . set ( TGSI :: SV1 ) ; rsv . set ( TGSI :: SV2x ) ; rsv . set ( TGSI :: SV2y ) ; rsv . set ( TGSI :: SV2z ) ; rsv . set ( TGSI :: SV2w ) ; rsv . set ( TGSI :: SV2 ) ; rsv . set ( TGSI :: SV3x ) ; rsv . set ( TGSI :: SV3y ) ; rsv . set ( TGSI :: SV3z ) ; rsv . set ( TGSI :: SV3w ) ; rsv . set ( TGSI :: SV3 ) ; rsv . set ( TGSI :: SV4x ) ; rsv . set ( TGSI :: SV4y ) ; rsv . set ( TGSI :: SV4z ) ; rsv . set ( TGSI :: SV4w ) ; rsv . set ( TGSI :: SV4 ) ; rsv . set ( TGSI :: ADDR0x ) ; rsv . set ( TGSI :: ADDR0y ) ; rsv . set ( TGSI :: ADDR0z ) ; rsv . set ( TGSI :: ADDR0w ) ; rsv . set ( TGSI :: ADDR0 ) ; return rsv ; } </s>


<s>
MachineBasicBlock
*
Z80TargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unexpected instr type to insert"
)
;
case
Z80
::
Select8
:
case
Z80
::
Select16
:
case
Z80
::
Select24
:
return
EmitLoweredSelect
(
MI
,
BB
)
;
case
Z80
::
SExt8
:
case
Z80
::
SExt16
:
case
Z80
::
SExt24
:
return
EmitLoweredSExt
(
MI
,
BB
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static void nvptx_goacc_reduction_fini ( gcall * call , offload_attrs * oa ) { gimple_stmt_iterator gsi = gsi_for_stmt ( call ) ; tree lhs = gimple_call_lhs ( call ) ; tree ref_to_res = gimple_call_arg ( call , 1 ) ; tree var = gimple_call_arg ( call , 2 ) ; int level = TREE_INT_CST_LOW ( gimple_call_arg ( call , 3 ) ) ; enum tree_code op = ( enum tree_code ) TREE_INT_CST_LOW ( gimple_call_arg ( call , 4 ) ) ; gimple_seq seq = NULL ; tree r = NULL_TREE ; push_gimplify_context ( true ) ; if ( level == GOMP_DIM_VECTOR && oa -> vector_length == PTX_WARP_SIZE ) { for ( int shfl = PTX_WARP_SIZE / 2 ; shfl > 0 ; shfl = shfl >> 1 ) { tree other_var = make_ssa_name ( TREE_TYPE ( var ) ) ; nvptx_generate_vector_shuffle ( gimple_location ( call ) , other_var , var , shfl , & seq ) ; r = make_ssa_name ( TREE_TYPE ( var ) ) ; gimplify_assign ( r , fold_build2 ( op , TREE_TYPE ( var ) , var , other_var ) , & seq ) ; var = r ; } } else { tree accum = NULL_TREE ; if ( level == GOMP_DIM_WORKER || level == GOMP_DIM_VECTOR ) { tree offset = gimple_call_arg ( call , 5 ) ; tree call = nvptx_get_shared_red_addr ( TREE_TYPE ( var ) , offset , level == GOMP_DIM_VECTOR ) ; tree ptr = make_ssa_name ( TREE_TYPE ( call ) ) ; gimplify_assign ( ptr , call , & seq ) ; accum = ptr ; } else if ( integer_zerop ( ref_to_res ) ) r = var ; else accum = ref_to_res ; if ( accum ) { gsi_insert_seq_before ( & gsi , seq , GSI_SAME_STMT ) ; seq = NULL ; r = nvptx_reduction_update ( gimple_location ( call ) , & gsi , accum , var , op , level ) ; } } if ( lhs ) gimplify_assign ( lhs , r , & seq ) ; pop_gimplify_context ( NULL ) ; gsi_replace_with_seq ( & gsi , seq , true ) ; } </s>

NVPTX implementation of GOACC_REDUCTION_FINI .


<s>
bool
SystemZDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
SystemZAddressingMode
::
AddrForm
Form
;
SystemZAddressingMode
::
DispRange
DispRange
;
SDValue
Base
,
Disp
,
Index
;
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
case
InlineAsm
::
Constraint_Q
:
Form
=
SystemZAddressingMode
::
FormBD
;
DispRange
=
SystemZAddressingMode
::
Disp12Only
;
break
;
case
InlineAsm
::
Constraint_R
:
Form
=
SystemZAddressingMode
::
FormBDXNormal
;
DispRange
=
SystemZAddressingMode
::
Disp12Only
;
break
;
case
InlineAsm
::
Constraint_S
:
Form
=
SystemZAddressingMode
::
FormBD
;
DispRange
=
SystemZAddressingMode
::
Disp20Only
;
break
;
case
InlineAsm
::
Constraint_T
:
case
InlineAsm
::
Constraint_m
:
Form
=
SystemZAddressingMode
::
FormBDXNormal
;
DispRange
=
SystemZAddressingMode
::
Disp20Only
;
break
;
}
if
(
selectBDXAddr
(
Form
,
DispRange
,
Op
,
Base
,
Disp
,
Index
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Disp
)
;
OutOps
.
push_back
(
Index
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .

SystemZ
SystemZ
SystemZAddressingMode::AddrForm
SystemZAddressingMode::DispRange
"Unexpected asm memory constraint"
SystemZAddressingMode::FormBD
SystemZAddressingMode::Disp12Only
SystemZAddressingMode::FormBDXNormal
SystemZAddressingMode::Disp12Only
SystemZAddressingMode::FormBD
SystemZAddressingMode::Disp20Only
SystemZAddressingMode::FormBDXNormal
SystemZAddressingMode::Disp20Only


<s> MSP430Subtarget :: MSP430Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : MSP430GenSubtargetInfo ( TT , CPU , FS ) , DL ( "e-m:e-p:16:16-i32:16:32-n8:16" ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM ) , TSInfo ( DL ) { } </s>

This constructor initializes the data members to match that of the specified triple .


<s> void AMDGPURegisterBankInfo :: split64BitValueForMapping ( MachineIRBuilder & B , SmallVector < unsigned , 2 > & Regs , unsigned Reg ) const { LLT S32 = LLT :: scalar ( 32 ) ; MachineRegisterInfo * MRI = B . getMRI ( ) ; unsigned LoLHS = MRI -> createGenericVirtualRegister ( S32 ) ; unsigned HiLHS = MRI -> createGenericVirtualRegister ( S32 ) ; const RegisterBank * Bank = getRegBank ( Reg , * MRI , * TRI ) ; MRI -> setRegBank ( LoLHS , * Bank ) ; MRI -> setRegBank ( HiLHS , * Bank ) ; Regs . push_back ( LoLHS ) ; Regs . push_back ( HiLHS ) ; B . buildInstr ( AMDGPU :: G_UNMERGE_VALUES ) . addDef ( LoLHS ) . addDef ( HiLHS ) . addUse ( Reg ) ; } </s>

Split 64-bit value Reg into two 32-bit halves and populate them into Regs .


<s> bool SIMemoryLegalizer :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; SIMemOpAccess MOA ( MF ) ; CC = SICacheControl :: create ( MF . getSubtarget < GCNSubtarget > ( ) ) ; for ( auto & MBB : MF ) { for ( auto MI = MBB . begin ( ) ; MI != MBB . end ( ) ; ++ MI ) { if ( MI -> getOpcode ( ) == TargetOpcode :: BUNDLE && MI -> mayLoadOrStore ( ) ) { MachineBasicBlock :: instr_iterator II ( MI -> getIterator ( ) ) ; for ( MachineBasicBlock :: instr_iterator I = ++ II , E = MBB . instr_end ( ) ; I != E && I -> isBundledWithPred ( ) ; ++ I ) { I -> unbundleFromPred ( ) ; for ( MachineOperand & MO : I -> operands ( ) ) if ( MO . isReg ( ) ) MO . setIsInternalRead ( false ) ; } MI -> eraseFromParent ( ) ; MI = II -> getIterator ( ) ; } if ( ! ( MI -> getDesc ( ) . TSFlags & SIInstrFlags :: maybeAtomic ) ) continue ; if ( const auto & MOI = MOA . getLoadInfo ( MI ) ) Changed |= expandLoad ( MOI . getValue ( ) , MI ) ; else if ( const auto & MOI = MOA . getStoreInfo ( MI ) ) Changed |= expandStore ( MOI . getValue ( ) , MI ) ; else if ( const auto & MOI = MOA . getAtomicFenceInfo ( MI ) ) Changed |= expandAtomicFence ( MOI . getValue ( ) , MI ) ; else if ( const auto & MOI = MOA . getAtomicCmpxchgOrRmwInfo ( MI ) ) Changed |= expandAtomicCmpxchgOrRmw ( MOI . getValue ( ) , MI ) ; } } Changed |= removeAtomicPseudoMIs ( ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .

AMDGPU SI SI SI SIInstrFlags::maybeAtomic


<s> static bool arc_must_save_return_addr ( struct function * func ) { if ( func -> machine -> frame_info . save_return_addr ) return true ; return false ; } </s>

Return true if the return address must be saved in the current function , otherwise return false .


<s>
StringRef
getPassName
(
)
const
override
{
return
"MINA32 DAG->DAG Instruction Selection"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> const RISCVTargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


"Successfully decoded 64-bit instruction."

"Not a 64-bit instruction, falling back to 32-bit."

"Successfully decoded 16-bit instruction with limm."

"Not a 16-bit instruction with limm, try without it."

Returns the disassembly of a single instruction .


<s> virtual const ARMBaseInstrInfo * getInstrInfo ( ) const { return InstrInfo . get ( ) ; } </s>


<s> int romp_using_r14 ( ) { return ( write_symbols != NO_DEBUG || current_function_profile || get_pool_size ( ) != 0 || romp_makes_calls ( ) ) ; } </s>

Return non-zero if this function will use r14 as a pointer to its constant pool .


<s> const char * mips_output_sync_loop ( rtx_insn * insn , rtx * operands ) { mips_branch_likely = TARGET_FIX_R10000 ; mips_process_sync_loop ( insn , operands ) ; mips_push_asm_switch ( & mips_noreorder ) ; mips_push_asm_switch ( & mips_nomacro ) ; mips_push_asm_switch ( & mips_noat ) ; mips_start_ll_sc_sync_block ( ) ; mips_multi_write ( ) ; mips_end_ll_sc_sync_block ( ) ; mips_pop_asm_switch ( & mips_noat ) ; mips_pop_asm_switch ( & mips_nomacro ) ; mips_pop_asm_switch ( & mips_noreorder ) ; return "" ; } </s>

Output and/or return the asm template for sync loop INSN , which has the operands given by OPERANDS .


"********** Replace Physical Registers **********\n"

"LiveIntervals shouldn't be active yet!"


<s> MVT :: SimpleValueType PIC16TargetLowering :: getSetCCResultType ( EVT ValType ) const { return MVT :: i8 ; } </s>

Return the value type to use for ISD : :SETCC .


<s> void initialize ( Attributor & A ) override { Function * F = getAssociatedFunction ( ) ; CallingConv :: ID CC = F -> getCallingConv ( ) ; bool CallingConvSupportsAllImplicits = ( CC != CallingConv :: AMDGPU_Gfx ) ; if ( AMDGPU :: isGraphics ( F -> getCallingConv ( ) ) ) { indicatePessimisticFixpoint ( ) ; return ; } for ( StringRef Attr : ImplicitAttrNames ) { if ( F -> hasFnAttribute ( Attr ) ) Attributes . insert ( Attr ) ; } if ( CallingConvSupportsAllImplicits && F -> hasAddressTaken ( nullptr , true , true , true ) ) { for ( StringRef AttrName : ImplicitAttrNames ) { Attributes . insert ( AttrName ) ; } } } </s>

Initialize the strategy after building the DAG for a new region .


<s> static void s390_register_info_arg_fpr ( ) { int i ; int min_stdarg_fpr = INT_MAX , max_stdarg_fpr = - 1 ; int min_preserve_fpr = INT_MAX , max_preserve_fpr = - 1 ; int min_fpr , max_fpr ; if ( cfun -> stdarg && TARGET_HARD_FLOAT && cfun -> va_list_fpr_size && crtl -> args . info . fprs < FP_ARG_NUM_REG ) { min_stdarg_fpr = crtl -> args . info . fprs ; max_stdarg_fpr = min_stdarg_fpr + cfun -> va_list_fpr_size - 1 ; if ( max_stdarg_fpr >= FP_ARG_NUM_REG ) max_stdarg_fpr = FP_ARG_NUM_REG - 1 ; min_stdarg_fpr += FPR0_REGNUM ; max_stdarg_fpr += FPR0_REGNUM ; } if ( s390_preserve_args_p && crtl -> args . info . fprs ) { min_preserve_fpr = FPR0_REGNUM ; max_preserve_fpr = MIN ( FPR0_REGNUM + FP_ARG_NUM_REG - 1 , FPR0_REGNUM + crtl -> args . info . fprs - 1 ) ; } min_fpr = MIN ( min_stdarg_fpr , min_preserve_fpr ) ; max_fpr = MAX ( max_stdarg_fpr , max_preserve_fpr ) ; if ( max_fpr == - 1 ) return ; for ( i = min_fpr ; i <= max_fpr ; i ++ ) cfun_set_fpr_save ( i ) ; } </s>

Set the bits in fpr_bitmap for FPRs which need to be saved due to stdarg or -mpreserve-args . This is a helper routine for s390_register_info .


<s> bool HexagonBitSimplify :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; auto & HST = MF . getSubtarget < HexagonSubtarget > ( ) ; auto & HRI = * HST . getRegisterInfo ( ) ; auto & HII = * HST . getInstrInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool Changed ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) ; const HexagonEvaluator HE ( HRI , MRI , HII , MF ) ; BitTracker BT ( HE , MF ) ; DEBUG ( BT . trace ( true ) ) ; BT . run ( ) ; MachineBasicBlock & Entry = MF . front ( ) ; RegisterSet AIG ; ConstGeneration ImmG ( BT , HII , MRI ) ; Changed |= visitBlock ( Entry , ImmG , AIG ) ; RegisterSet ARE ; RedundantInstrElimination RIE ( BT , HII , MRI ) ; Changed |= visitBlock ( Entry , RIE , ARE ) ; RegisterSet ACG ; CopyGeneration CopyG ( BT , HII , MRI ) ; Changed |= visitBlock ( Entry , CopyG , ACG ) ; RegisterSet ACP ; CopyPropagation CopyP ( HRI , MRI ) ; Changed |= visitBlock ( Entry , CopyP , ACP ) ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) || Changed ; BT . run ( ) ; RegisterSet ABS ; BitSimplification BitS ( BT , HII , MRI ) ; Changed |= visitBlock ( Entry , BitS , ABS ) ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) || Changed ; if ( Changed ) { for ( auto & B : MF ) for ( auto & I : B ) I . clearKillInfo ( ) ; DeadCodeElimination ( MF , * MDT ) . run ( ) ; } return Changed ; } </s>


"Cannot store this register to stack slot!"

Store the specified register of the given register class to the specified stack frame index .


<s> static bool s390_legitimate_constant_p ( machine_mode mode , rtx op ) { if ( TARGET_VX && VECTOR_MODE_P ( mode ) && GET_CODE ( op ) == CONST_VECTOR ) { if ( GET_MODE_SIZE ( mode ) != 16 ) return 0 ; if ( ! satisfies_constraint_j00 ( op ) && ! satisfies_constraint_jm1 ( op ) && ! satisfies_constraint_jKK ( op ) && ! satisfies_constraint_jxx ( op ) && ! satisfies_constraint_jyy ( op ) ) return 0 ; } if ( ! SYMBOLIC_CONST ( op ) ) return 1 ; if ( larl_operand ( op , mode ) ) return 1 ; if ( TLS_SYMBOLIC_CONST ( op ) ) return 0 ; if ( flag_pic ) return 1 ; return 0 ; } </s>

Returns true if the constant value OP is a legitimate general operand . It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE .


<s> bool fixupNeedsRelaxationAdvanced ( const MCFixup & Fixup , bool Resolved , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout , const bool WasForced ) const override { return false ; } </s>

Target specific predicate for whether a given fixup requires the associated instruction to be relaxed .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == 0 ) Inst . addOperand ( MCOperand :: CreateImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> InstructionCost getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: TargetCostKind CostKind = TTI :: TCK_RecipThroughput , TTI :: OperandValueKind Opd1Info = TTI :: OK_AnyValue , TTI :: OperandValueKind Opd2Info = TTI :: OK_AnyValue , TTI :: OperandValueProperties Opd1PropInfo = TTI :: OP_None , TTI :: OperandValueProperties Opd2PropInfo = TTI :: OP_None , ArrayRef < const Value * > Args = ArrayRef < const Value * > ( ) , const Instruction * CxtI = nullptr ) { int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: MUL : case ISD :: SDIV : case ISD :: UDIV : case ISD :: UREM : return 64 * BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .

Lanai ISD::MUL ISD::SDIV ISD::UDIV ISD::UREM 64


<s> bool arm_validize_comparison ( rtx * comparison , rtx * op1 , rtx * op2 ) { enum rtx_code code = GET_CODE ( * comparison ) ; int code_int ; machine_mode mode = ( GET_MODE ( * op1 ) == VOIDmode ) ? GET_MODE ( * op2 ) : GET_MODE ( * op1 ) ; gcc_assert ( GET_MODE ( * op1 ) != VOIDmode || GET_MODE ( * op2 ) != VOIDmode ) ; if ( code == UNEQ || code == LTGT ) return false ; code_int = ( int ) code ; arm_canonicalize_comparison ( & code_int , op1 , op2 , 0 ) ; PUT_CODE ( * comparison , ( enum rtx_code ) code_int ) ; switch ( mode ) { case E_SImode : if ( ! arm_add_operand ( * op1 , mode ) ) * op1 = force_reg ( mode , * op1 ) ; if ( ! arm_add_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; return true ; case E_DImode : if ( ! cmpdi_operand ( * op1 , mode ) ) * op1 = force_reg ( mode , * op1 ) ; if ( ! cmpdi_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; return true ; case E_HFmode : if ( ! TARGET_VFP_FP16INST ) break ; mode = SFmode ; * op1 = convert_to_mode ( mode , * op1 , 1 ) ; * op2 = convert_to_mode ( mode , * op2 , 1 ) ; case E_SFmode : case E_DFmode : if ( ! vfp_compare_operand ( * op1 , mode ) ) * op1 = force_reg ( mode , * op1 ) ; if ( ! vfp_compare_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; return true ; default : break ; } return false ; } </s>

Returns true if a valid comparison operation and makes the operands in a form that is valid .


<s> Optional < uint64_t > X86MCInstrAnalysis :: evaluateMemoryOperandAddress ( const MCInst & Inst , uint64_t Addr , uint64_t Size ) const { const MCInstrDesc & MCID = Info -> get ( Inst . getOpcode ( ) ) ; int MemOpStart = X86II :: getMemoryOperandNo ( MCID . TSFlags ) ; if ( MemOpStart == - 1 ) return None ; MemOpStart += X86II :: getOperandBias ( MCID ) ; const MCOperand & SegReg = Inst . getOperand ( MemOpStart + X86 :: AddrSegmentReg ) ; const MCOperand & BaseReg = Inst . getOperand ( MemOpStart + X86 :: AddrBaseReg ) ; const MCOperand & IndexReg = Inst . getOperand ( MemOpStart + X86 :: AddrIndexReg ) ; const MCOperand & ScaleAmt = Inst . getOperand ( MemOpStart + X86 :: AddrScaleAmt ) ; const MCOperand & Disp = Inst . getOperand ( MemOpStart + X86 :: AddrDisp ) ; if ( SegReg . getReg ( ) != 0 || IndexReg . getReg ( ) != 0 || ScaleAmt . getImm ( ) != 1 || ! Disp . isImm ( ) ) return None ; if ( BaseReg . getReg ( ) == X86 :: RIP ) return Addr + Size + Disp . getImm ( ) ; return None ; } </s>

Given an instruction tries to get the address of a memory operand .


<s> MCContext & getContext ( ) const { return Streamer . getContext ( ) ; } </s>

Return the LLVMContext used by the analysis .


"Wasn't expecting to be able to lower this!"

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool X86TargetLowering :: isGAPlusOffset ( SDNode * N , const GlobalValue * & GA , int64_t & Offset ) const { if ( N -> getOpcode ( ) == X86ISD :: Wrapper ) { if ( isa < GlobalAddressSDNode > ( N -> getOperand ( 0 ) ) ) { GA = cast < GlobalAddressSDNode > ( N -> getOperand ( 0 ) ) -> getGlobal ( ) ; Offset = cast < GlobalAddressSDNode > ( N -> getOperand ( 0 ) ) -> getOffset ( ) ; return true ; } } return TargetLowering :: isGAPlusOffset ( N , GA , Offset ) ; } </s>

Returns true ( and the GlobalValue and the offset ) if the node is a GlobalAddress + offset .


<s>
void
SPURegisterInfo
::
determineFrameLayout
(
MachineFunction
&
MF
)
const
{
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
unsigned
FrameSize
=
MFI
->
getStackSize
(
)
;
unsigned
TargetAlign
=
MF
.
getTarget
(
)
.
getFrameInfo
(
)
->
getStackAlignment
(
)
;
unsigned
Align
=
std
::
max
(
TargetAlign
,
MFI
->
getMaxAlignment
(
)
)
;
assert
(
isPowerOf2_32
(
Align
)
&&
"Alignment is not power of 2"
)
;
unsigned
AlignMask
=
Align
1
;
unsigned
maxCallFrameSize
=
MFI
->
getMaxCallFrameSize
(
)
;
if
(
MFI
->
hasVarSizedObjects
(
)
)
maxCallFrameSize
=
(
maxCallFrameSize
+
AlignMask
)
&
~
AlignMask
;
MFI
->
setMaxCallFrameSize
(
maxCallFrameSize
)
;
FrameSize
+=
maxCallFrameSize
;
FrameSize
=
(
FrameSize
+
AlignMask
)
&
~
AlignMask
;
MFI
->
setStackSize
(
FrameSize
)
;
}
</s>

Determine the frame layout but do not update the machine function .

CellSPU
SPU
"Alignment is not power of 2"
1


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < AAResultsWrapperPass > ( ) ; AU . addRequired < MemorySSAWrapperPass > ( ) ; AU . setPreservesAll ( ) ; } </s>


<s> bool AArch64FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; static const LoadStoreMethod PossibleClasses [ ] = { { & AArch64 :: GPR64RegClass , AArch64 :: LSPair64_LDR , AArch64 :: LS64_LDR } , { & AArch64 :: FPR64RegClass , AArch64 :: LSFPPair64_LDR , AArch64 :: LSFP64_LDR } , } ; const unsigned NumClasses = llvm :: array_lengthof ( PossibleClasses ) ; emitFrameMemOps ( false , MBB , MBBI , CSI , TRI , PossibleClasses , NumClasses ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> virtual void schedNode ( SUnit * SU , bool IsTopNode ) { } </s>

ScheduleDAGMI has scheduled an instruction - tell HazardRec about it .


<s> void SystemZPostRASchedStrategy :: initialize ( ScheduleDAGMI * dag ) { DEBUG ( HazardRec -> dumpState ( ) ; ) ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < MachineDominanceFrontier > ( ) ; AU . setPreservesAll ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> void ARMPassConfig :: addIRPasses ( ) { if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( SimplifyCFGOptions ( ) . hoistCommonInsts ( true ) . sinkCommonInsts ( true ) , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < ARMSubtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST . isThumb1Only ( ) ; } ) ) ; addPass ( createMVEGatherScatterLoweringPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( createARMParallelDSPPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardCheckPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> bool X86InstrInfo :: getConstValDefinedInReg ( const MachineInstr & MI , const Register Reg , int64_t & ImmVal ) const { if ( MI . getOpcode ( ) != X86 :: MOV32ri && MI . getOpcode ( ) != X86 :: MOV64ri ) return false ; if ( ! MI . getOperand ( 1 ) . isImm ( ) || MI . getOperand ( 0 ) . getReg ( ) != Reg ) return false ; ImmVal = MI . getOperand ( 1 ) . getImm ( ) ; return true ; } </s>

Returns true if MI is an instruction that defines Reg to have a constant value and the value is recorded in ImmVal .


<s> const LoongArchSubtarget & getSubtarget ( ) const { return Subtarget ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


<s> MachineBasicBlock * AMDGPUCFGStructurizer :: clone ( MachineBasicBlock * MBB ) { MachineFunction * Func = MBB -> getParent ( ) ; MachineBasicBlock * NewMBB = Func -> CreateMachineBasicBlock ( ) ; Func -> push_back ( NewMBB ) ; for ( MachineBasicBlock :: iterator It = MBB -> begin ( ) , E = MBB -> end ( ) ; It != E ; ++ It ) { MachineInstr * MI = Func -> CloneMachineInstr ( It ) ; NewMBB -> push_back ( MI ) ; } return NewMBB ; } </s>

Make a functionally equivalent copy of this MachineFunctionInfo in MF .


<s> bool AVRTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { if ( CallConv == CallingConv :: AVR_BUILTIN ) { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_AVR_BUILTIN ) ; } unsigned TotalBytes = getTotalArgumentsSizeInBytes ( Outs ) ; return TotalBytes <= 8 ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> unsigned SIInstrInfo :: readlaneVGPRToSGPR ( unsigned SrcReg , MachineInstr & UseMI , MachineRegisterInfo & MRI ) const { const TargetRegisterClass * VRC = MRI . getRegClass ( SrcReg ) ; const TargetRegisterClass * SRC = RI . getEquivalentSGPRClass ( VRC ) ; unsigned DstReg = MRI . createVirtualRegister ( SRC ) ; unsigned SubRegs = VRC -> getSize ( ) / 4 ; SmallVector < unsigned , 8 > SRegs ; for ( unsigned i = 0 ; i < SubRegs ; ++ i ) { unsigned SGPR = MRI . createVirtualRegister ( & AMDGPU :: SGPR_32RegClass ) ; BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( AMDGPU :: V_READFIRSTLANE_B32 ) , SGPR ) . addReg ( SrcReg , 0 , RI . getSubRegFromChannel ( i ) ) ; SRegs . push_back ( SGPR ) ; } MachineInstrBuilder MIB = BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( AMDGPU :: REG_SEQUENCE ) , DstReg ) ; for ( unsigned i = 0 ; i < SubRegs ; ++ i ) { MIB . addReg ( SRegs [ i ] ) ; MIB . addImm ( RI . getSubRegFromChannel ( i ) ) ; } return DstReg ; } </s>

Copy a value from a VGPR ( SrcReg ) to SGPR .


<s> static void emit_pred_op ( unsigned icode , rtx mask , rtx dest , rtx src , rtx len , machine_mode mask_mode , bool vlmax_p ) { insn_expander < 8 > e ; machine_mode mode = GET_MODE ( dest ) ; e . add_output_operand ( dest , mode ) ; if ( mask ) e . add_input_operand ( mask , GET_MODE ( mask ) ) ; else e . add_all_one_mask_operand ( mask_mode ) ; e . add_vundef_operand ( mode ) ; e . add_input_operand ( src , GET_MODE ( src ) ) ; if ( len ) e . add_input_operand ( len , Pmode ) ; else { rtx vlmax = gen_reg_rtx ( Pmode ) ; emit_vlmax_vsetvl ( mode , vlmax ) ; e . add_input_operand ( vlmax , Pmode ) ; } if ( GET_MODE_CLASS ( mode ) != MODE_VECTOR_BOOL ) e . add_policy_operand ( get_prefer_tail_policy ( ) , get_prefer_mask_policy ( ) ) ; if ( vlmax_p ) e . add_avl_type_operand ( avl_type :: VLMAX ) ; else e . add_avl_type_operand ( avl_type :: NONVLMAX ) ; e . expand ( ( enum insn_code ) icode , MEM_P ( dest ) || MEM_P ( src ) ) ; } </s>

Emit an RVV unmask & & vl mov from SRC to DEST .


<s> void SITargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { switch ( N -> getOpcode ( ) ) { case ISD :: INSERT_VECTOR_ELT : { if ( SDValue Res = lowerINSERT_VECTOR_ELT ( SDValue ( N , 0 ) , DAG ) ) Results . push_back ( Res ) ; return ; } case ISD :: EXTRACT_VECTOR_ELT : { if ( SDValue Res = lowerEXTRACT_VECTOR_ELT ( SDValue ( N , 0 ) , DAG ) ) Results . push_back ( Res ) ; return ; } default : break ; } } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


"CFGuard check mechanism only used on 32-bit X86"

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
static
void
bounds_check
(
rtx
operand
,
HOST_WIDE_INT
low
,
HOST_WIDE_INT
high
,
const_tree
exp
,
const
char
*
desc
)
{
HOST_WIDE_INT
lane
;
gcc_assert
(
CONST_INT_P
(
operand
)
)
;
lane
=
INTVAL
(
operand
)
;
if
(
lane
<
low
||
lane
>=
high
)
{
if
(
exp
)
error_at
(
EXPR_LOCATION
(
exp
)
,
"%s %wd out of range %wd - %wd"
,
desc
,
lane
,
low
,
high
1
)
;
else
error
(
"%s %wd out of range %wd - %wd"
,
desc
,
lane
,
low
,
high
1
)
;
}
}
</s>

Ensure OPERAND lies between LOW ( inclusive ) and HIGH ( exclusive ) . Raise ERR if it does n't . FIXME : NEON bounds checks occur late in compilation , so reported source locations are bogus .


<s> static bool need_to_save_reg ( unsigned int regno ) { if ( ! call_used_or_fixed_reg_p ( regno ) && df_regs_ever_live_p ( regno ) ) return true ; if ( flag_pic && ( regno == PIC_OFFSET_TABLE_REGNUM || regno == TILEPRO_PIC_TEXT_LABEL_REGNUM ) && ( crtl -> uses_pic_offset_table || crtl -> saves_all_registers ) ) return true ; if ( crtl -> calls_eh_return ) { unsigned i ; for ( i = 0 ; EH_RETURN_DATA_REGNO ( i ) != INVALID_REGNUM ; i ++ ) { if ( regno == EH_RETURN_DATA_REGNO ( i ) ) return true ; } } return false ; } </s>

Return whether REGNO needs to be saved in the stack frame .


<s> void X86AsmParser :: emitInstruction ( MCInst & Inst , OperandVector & Operands , MCStreamer & Out ) { Out . emitInstruction ( Inst , getSTI ( ) ) ; } </s>

Targets should implement this to emit instructions .


<s> void arc_ccfsm_record_branch_deleted ( ) { arc_ccfsm_state += 2 ; current_insn_set_cc_p = last_insn_set_cc_p ; } </s>

Record a branch is n't output because subsequent insns can be conditionalized .


<s> void HexagonShuffler :: append ( MCInst const * ID , MCInst const * Extender , unsigned S , bool X ) { HexagonInstr PI ( & TUL , MCII , ID , Extender , S , X ) ; Packet . push_back ( PI ) ; } </s>


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const PPCFrameLowering * TFI = getFrameLowering ( MF ) ; markSuperRegs ( Reserved , PPC :: ZERO ) ; markSuperRegs ( Reserved , PPC :: FP ) ; markSuperRegs ( Reserved , PPC :: BP ) ; markSuperRegs ( Reserved , PPC :: CTR ) ; markSuperRegs ( Reserved , PPC :: CTR8 ) ; markSuperRegs ( Reserved , PPC :: R1 ) ; markSuperRegs ( Reserved , PPC :: LR ) ; markSuperRegs ( Reserved , PPC :: LR8 ) ; markSuperRegs ( Reserved , PPC :: RM ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) markSuperRegs ( Reserved , PPC :: VRSAVE ) ; if ( Subtarget . isSVR4ABI ( ) ) { const PPCFunctionInfo * FuncInfo = MF . getInfo < PPCFunctionInfo > ( ) ; if ( ! TM . isPPC64 ( ) || FuncInfo -> usesTOCBasePtr ( ) || MF . hasInlineAsm ( ) ) markSuperRegs ( Reserved , PPC :: R2 ) ; markSuperRegs ( Reserved , PPC :: R13 ) ; } if ( TM . isPPC64 ( ) ) markSuperRegs ( Reserved , PPC :: R13 ) ; if ( TFI -> needsFP ( MF ) ) markSuperRegs ( Reserved , PPC :: R31 ) ; bool IsPositionIndependent = TM . isPositionIndependent ( ) ; if ( hasBasePointer ( MF ) ) { if ( Subtarget . isSVR4ABI ( ) && ! TM . isPPC64 ( ) && IsPositionIndependent ) markSuperRegs ( Reserved , PPC :: R29 ) ; else markSuperRegs ( Reserved , PPC :: R30 ) ; } if ( Subtarget . isSVR4ABI ( ) && ! TM . isPPC64 ( ) && IsPositionIndependent ) markSuperRegs ( Reserved , PPC :: R30 ) ; if ( ! Subtarget . hasAltivec ( ) ) for ( TargetRegisterClass :: iterator I = PPC :: VRRCRegClass . begin ( ) , IE = PPC :: VRRCRegClass . end ( ) ; I != IE ; ++ I ) markSuperRegs ( Reserved , * I ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .

PowerPC PPC PPC PPC PPC PPC::ZERO PPC::FP PPC::BP PPC::CTR PPC::CTR8 PPC::R1 PPC::LR PPC::LR8 PPC::RM PPC::VRSAVE PPC PPC PPC PPC::R2 PPC::R13 PPC PPC::R13 PPC::R31 PPC PPC::R29 PPC::R30 PPC PPC::R30 PPC::VRRCRegClass PPC::VRRCRegClass


<s> void reset ( unsigned RequiredSize ) { RequiredShadowSize = RequiredSize ; CurrentShadowSize = 0 ; InShadow = true ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s> bool HexagonInstrInfo :: isDuplexPair ( const MachineInstr * MIa , const MachineInstr * MIb ) const { HexagonII :: SubInstructionGroup MIaG = getDuplexCandidateGroup ( MIa ) ; HexagonII :: SubInstructionGroup MIbG = getDuplexCandidateGroup ( MIb ) ; return ( isDuplexPairMatch ( MIaG , MIbG ) || isDuplexPairMatch ( MIbG , MIaG ) ) ; } </s>

Symmetrical . See if these two instructions are fit for duplex pair .

Hexagon Hexagon HexagonII::SubInstructionGroup HexagonII::SubInstructionGroup


<s> static bool mips_function_value_regno_p ( const unsigned int regno ) { if ( regno == GP_RETURN || regno == FP_RETURN || ( FP_RETURN != GP_RETURN && regno == FP_RETURN + 2 ) ) return true ; if ( ( mips_abi == ABI_32 && TARGET_FLOAT32 ) && FP_RETURN != GP_RETURN && ( regno == FP_RETURN + 1 || regno == FP_RETURN + 3 ) ) return true ; return false ; } </s>

Implement TARGET_FUNCTION_VALUE_REGNO_P . On the MIPS , R2 R3 and F0 F2 are the only register thus used .


<s> SDValue XNCMTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_XNCM ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> BitVector MSP430RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; Reserved . set ( MSP430 :: PCW ) ; Reserved . set ( MSP430 :: SPW ) ; Reserved . set ( MSP430 :: SRW ) ; Reserved . set ( MSP430 :: CGW ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( MSP430 :: FPW ) ; return Reserved ; } </s>


"optionally flag setting instruction missing optional def operand"

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


<s> rtx frv_return_addr_rtx ( int count , rtx frame ) { if ( count != 0 ) return const0_rtx ; cfun -> machine -> frame_needed = 1 ; return gen_rtx_MEM ( Pmode , plus_constant ( frame , 8 ) ) ; } </s>

A C expression whose value is RTL representing the value of the return address for the frame COUNT steps up from the current frame , after the prologue . FRAMEADDR is the frame pointer of the COUNT frame , or the frame pointer of the COUNT - 1 frame if ` RETURN_ADDR_IN_PREVIOUS_FRAME ' is defined . The value of the expression must always be the correct address when COUNT is zero , but may be ` NULL_RTX ' if there is not way to determine the return address of other frames .


<s> void SystemZPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None && getSystemZTargetMachine ( ) . getSubtargetImpl ( ) -> hasLoadStoreOnCond ( ) ) addPass ( & IfConverterID ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> inline set_of_reg sh_find_set_of_reg ( rtx reg , rtx_insn * insn , F stepfunc , bool ignore_reg_reg_copies = false ) { set_of_reg result ; result . insn = insn ; result . set_rtx = NULL_RTX ; result . set_src = NULL_RTX ; if ( ! REG_P ( reg ) || insn == NULL_RTX ) return result ; for ( rtx_insn * i = stepfunc ( insn ) ; i != NULL_RTX ; i = stepfunc ( i ) ) { if ( BARRIER_P ( i ) ) break ; if ( ! INSN_P ( i ) || DEBUG_INSN_P ( i ) ) continue ; if ( reg_set_p ( reg , i ) ) { if ( CALL_P ( i ) ) break ; result . insn = i ; result . set_rtx = set_of ( reg , i ) ; if ( result . set_rtx == NULL_RTX || GET_CODE ( result . set_rtx ) != SET ) break ; result . set_src = XEXP ( result . set_rtx , 1 ) ; if ( ignore_reg_reg_copies && REG_P ( result . set_src ) ) { reg = result . set_src ; continue ; } if ( ignore_reg_reg_copies && SUBREG_P ( result . set_src ) && REG_P ( SUBREG_REG ( result . set_src ) ) ) { reg = SUBREG_REG ( result . set_src ) ; continue ; } break ; } } if ( result . set_src != NULL ) gcc_assert ( result . insn != NULL && result . set_rtx != NULL ) ; return result ; } </s>

Given a reg rtx and a start insn , try to find the insn that sets the specified reg by using the specified insn stepping function , such as 'prev_nonnote_insn_bb ' . When the insn is found , try to extract the rtx of the reg set .


<s> void ExportClustering :: apply ( ScheduleDAGInstrs * DAG ) { const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( DAG -> TII ) ; SmallVector < SUnit * , 8 > Chain ; unsigned PosCount = 0 ; for ( SUnit & SU : DAG -> SUnits ) { if ( ! isExport ( SU ) ) continue ; Chain . push_back ( & SU ) ; if ( isPositionExport ( TII , & SU ) ) PosCount ++ ; removeExportDependencies ( DAG , SU ) ; SmallVector < SDep , 4 > Succs ( SU . Succs ) ; for ( SDep Succ : Succs ) removeExportDependencies ( DAG , * Succ . getSUnit ( ) ) ; } if ( Chain . size ( ) > 1 ) { sortChain ( TII , Chain , PosCount ) ; buildCluster ( Chain , DAG ) ; } } </s>

Apply the profile inference algorithm for a given function .


<s> bool NVPTXAsmPrinter :: doFinalization ( Module & M ) { bool HasDebugInfo = MMI && MMI -> hasDebugInfo ( ) ; if ( ! GlobalsEmitted ) { emitGlobals ( M ) ; GlobalsEmitted = true ; } Module :: GlobalListType & global_list = M . getGlobalList ( ) ; int i , n = global_list . size ( ) ; GlobalVariable * * gv_array = new GlobalVariable * [ n ] ; i = 0 ; for ( Module :: global_iterator I = global_list . begin ( ) , E = global_list . end ( ) ; I != E ; ++ I ) gv_array [ i ++ ] = & * I ; while ( ! global_list . empty ( ) ) global_list . remove ( global_list . begin ( ) ) ; bool ret = AsmPrinter :: doFinalization ( M ) ; for ( i = 0 ; i < n ; i ++ ) global_list . insert ( global_list . end ( ) , gv_array [ i ] ) ; clearAnnotationCache ( & M ) ; delete [ ] gv_array ; if ( HasDebugInfo ) static_cast < NVPTXTargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) -> closeLastSection ( ) ; static_cast < NVPTXTargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) -> outputDwarfFileDirectives ( ) ; return ret ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> void RISCVInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & O ) { bool Res = false ; const MCInst * NewMI = MI ; MCInst UncompressedMI ; if ( ! NoAliases ) Res = uncompressInst ( UncompressedMI , * MI , MRI , STI ) ; if ( Res ) NewMI = const_cast < MCInst * > ( & UncompressedMI ) ; if ( NoAliases || ! printAliasInstr ( NewMI , Address , STI , O ) ) printInstruction ( NewMI , Address , STI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> SDValue BPFSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , bool AlwaysInline , bool MustPreserveCheriCapabilities , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; if ( ! ConstantSize ) return SDValue ( ) ; unsigned CopyLen = ConstantSize -> getZExtValue ( ) ; unsigned StoresNumEstimate = alignTo ( CopyLen , Alignment ) >> Log2 ( Alignment ) ; if ( StoresNumEstimate > getCommonMaxStoresPerMemFunc ( ) ) return SDValue ( ) ; SDVTList VTs = DAG . getVTList ( MVT :: Other , MVT :: Glue ) ; Dst = DAG . getNode ( BPFISD :: MEMCPY , dl , VTs , Chain , Dst , Src , DAG . getConstant ( CopyLen , dl , MVT :: i64 ) , DAG . getConstant ( Alignment . value ( ) , dl , MVT :: i64 ) ) ; return Dst . getValue ( 0 ) ; } </s>

Emit target-specific code that performs a memcpy .


<s> static bool mem_shadd_or_shadd_rtx_p ( rtx x ) { return ( ( GET_CODE ( x ) == ASHIFT || GET_CODE ( x ) == MULT ) && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT && ( ( GET_CODE ( x ) == ASHIFT && pa_shadd_constant_p ( INTVAL ( XEXP ( x , 1 ) ) ) ) || ( GET_CODE ( x ) == MULT && pa_mem_shadd_constant_p ( INTVAL ( XEXP ( x , 1 ) ) ) ) ) ) ; } </s>

Helper for hppa_legitimize_address . Given X , return true if it is a left shift by 1 , 2 or 3 positions or a multiply by 2 , 4 or 8 . This respectively represent canonical shift-add rtxs or scaled memory addresses .


"failed to spill SGPR to VGPR when allocated"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> unsigned TL45MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) { return getTL45RegisterNumbering ( MO . getReg ( ) ) ; } if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } return 0 ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> static void tilepro_va_start ( tree valist , rtx nextarg ATTRIBUTE_UNUSED ) { tree f_args , f_skip ; tree args , skip , t ; f_args = TYPE_FIELDS ( TREE_TYPE ( valist ) ) ; f_skip = TREE_CHAIN ( f_args ) ; args = build3 ( COMPONENT_REF , TREE_TYPE ( f_args ) , valist , f_args , NULL_TREE ) ; skip = build3 ( COMPONENT_REF , TREE_TYPE ( f_skip ) , valist , f_skip , NULL_TREE ) ; t = make_tree ( TREE_TYPE ( args ) , virtual_incoming_args_rtx ) ; t = fold_build_pointer_plus_hwi ( t , UNITS_PER_WORD * ( crtl -> args . info - TILEPRO_NUM_ARG_REGS ) ) ; if ( crtl -> args . pretend_args_size > 0 ) t = fold_build_pointer_plus_hwi ( t , - STACK_POINTER_OFFSET ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( args ) , args , t ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( skip ) , virtual_incoming_args_rtx ) ; t = fold_build_pointer_plus_hwi ( t , - STACK_POINTER_OFFSET ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( skip ) , skip , t ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; } </s>