<s>
void
Mips16FrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
const
Mips16InstrInfo
&
TII
=
*
static_cast
<
const
Mips16InstrInfo
*
>
(
STI
.
getInstrInfo
(
)
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
dl
;
uint64_t
StackSize
=
MFI
.
getStackSize
(
)
;
if
(
StackSize
==
0
&&
!
MFI
.
adjustsStack
(
)
)
return
;
MachineModuleInfo
&
MMI
=
MF
.
getMMI
(
)
;
const
MCRegisterInfo
*
MRI
=
MMI
.
getContext
(
)
.
getRegisterInfo
(
)
;
TII
.
makeFrame
(
Mips
::
SP
,
StackSize
,
MBB
,
MBBI
)
;
unsigned
CFIIndex
=
MF
.
addFrameInst
(
MCCFIInstruction
::
createDefCfaOffset
(
nullptr
,
StackSize
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
TargetOpcode
::
CFI_INSTRUCTION
)
)
.
addCFIIndex
(
CFIIndex
)
;
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
.
getCalleeSavedInfo
(
)
;
if
(
!
CSI
.
empty
(
)
)
{
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
.
getCalleeSavedInfo
(
)
;
for
(
std
::
vector
<
CalleeSavedInfo
>
::
const_iterator
I
=
CSI
.
begin
(
)
,
E
=
CSI
.
end
(
)
;
I
!=
E
;
++
I
)
{
int64_t
Offset
=
MFI
.
getObjectOffset
(
I
->
getFrameIdx
(
)
)
;
unsigned
Reg
=
I
->
getReg
(
)
;
unsigned
DReg
=
MRI
->
getDwarfRegNum
(
Reg
,
true
)
;
unsigned
CFIIndex
=
MF
.
addFrameInst
(
MCCFIInstruction
::
createOffset
(
nullptr
,
DReg
,
Offset
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
TargetOpcode
::
CFI_INSTRUCTION
)
)
.
addCFIIndex
(
CFIIndex
)
;
}
}
if
(
hasFP
(
MF
)
)
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Mips
::
MoveR3216
)
,
Mips
::
S0
)
.
addReg
(
Mips
::
SP
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Mips
Mips
"Shrink-wrapping not yet supported"
Mips
Mips
0
Mips::SP
Mips::MoveR3216
Mips::S0
Mips::SP


<s> bool ARMLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { STI = & static_cast < const ARMSubtarget & > ( Fn . getSubtarget ( ) ) ; TL = STI -> getTargetLowering ( ) ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; RS = new RegScavenger ( ) ; isThumb2 = AFI -> isThumb2Function ( ) ; isThumb1 = AFI -> isThumbFunction ( ) && ! isThumb2 ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= LoadStoreMultipleOpti ( MBB ) ; if ( STI -> hasV5TOps ( ) ) Modified |= MergeReturnIntoLDM ( MBB ) ; } delete RS ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool AArch64AsmParser :: ParseDirective ( AsmToken DirectiveID ) { const MCObjectFileInfo :: Environment Format = getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ; bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; bool IsCOFF = Format == MCObjectFileInfo :: IsCOFF ; auto IDVal = DirectiveID . getIdentifier ( ) . lower ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == ".arch" ) parseDirectiveArch ( Loc ) ; else if ( IDVal == ".cpu" ) parseDirectiveCPU ( Loc ) ; else if ( IDVal == ".tlsdesccall" ) parseDirectiveTLSDescCall ( Loc ) ; else if ( IDVal == ".ltorg" || IDVal == ".pool" ) parseDirectiveLtorg ( Loc ) ; else if ( IDVal == ".unreq" ) parseDirectiveUnreq ( Loc ) ; else if ( IDVal == ".inst" ) parseDirectiveInst ( Loc ) ; else if ( IDVal == ".cfi_negate_ra_state" ) parseDirectiveCFINegateRAState ( ) ; else if ( IDVal == ".cfi_b_key_frame" ) parseDirectiveCFIBKeyFrame ( ) ; else if ( IDVal == ".arch_extension" ) parseDirectiveArchExtension ( Loc ) ; else if ( IsMachO ) { if ( IDVal == MCLOHDirectiveName ( ) ) parseDirectiveLOH ( IDVal , Loc ) ; else return true ; } else if ( IsCOFF ) { if ( IDVal == ".seh_stackalloc" ) parseDirectiveSEHAllocStack ( Loc ) ; else if ( IDVal == ".seh_endprologue" ) parseDirectiveSEHPrologEnd ( Loc ) ; else if ( IDVal == ".seh_save_r19r20_x" ) parseDirectiveSEHSaveR19R20X ( Loc ) ; else if ( IDVal == ".seh_save_fplr" ) parseDirectiveSEHSaveFPLR ( Loc ) ; else if ( IDVal == ".seh_save_fplr_x" ) parseDirectiveSEHSaveFPLRX ( Loc ) ; else if ( IDVal == ".seh_save_reg" ) parseDirectiveSEHSaveReg ( Loc ) ; else if ( IDVal == ".seh_save_reg_x" ) parseDirectiveSEHSaveRegX ( Loc ) ; else if ( IDVal == ".seh_save_regp" ) parseDirectiveSEHSaveRegP ( Loc ) ; else if ( IDVal == ".seh_save_regp_x" ) parseDirectiveSEHSaveRegPX ( Loc ) ; else if ( IDVal == ".seh_save_lrpair" ) parseDirectiveSEHSaveLRPair ( Loc ) ; else if ( IDVal == ".seh_save_freg" ) parseDirectiveSEHSaveFReg ( Loc ) ; else if ( IDVal == ".seh_save_freg_x" ) parseDirectiveSEHSaveFRegX ( Loc ) ; else if ( IDVal == ".seh_save_fregp" ) parseDirectiveSEHSaveFRegP ( Loc ) ; else if ( IDVal == ".seh_save_fregp_x" ) parseDirectiveSEHSaveFRegPX ( Loc ) ; else if ( IDVal == ".seh_set_fp" ) parseDirectiveSEHSetFP ( Loc ) ; else if ( IDVal == ".seh_add_fp" ) parseDirectiveSEHAddFP ( Loc ) ; else if ( IDVal == ".seh_nop" ) parseDirectiveSEHNop ( Loc ) ; else if ( IDVal == ".seh_save_next" ) parseDirectiveSEHSaveNext ( Loc ) ; else if ( IDVal == ".seh_startepilogue" ) parseDirectiveSEHEpilogStart ( Loc ) ; else if ( IDVal == ".seh_endepilogue" ) parseDirectiveSEHEpilogEnd ( Loc ) ; else if ( IDVal == ".seh_trap_frame" ) parseDirectiveSEHTrapFrame ( Loc ) ; else if ( IDVal == ".seh_pushframe" ) parseDirectiveSEHMachineFrame ( Loc ) ; else if ( IDVal == ".seh_context" ) parseDirectiveSEHContext ( Loc ) ; else if ( IDVal == ".seh_clear_unwound_to_call" ) parseDirectiveSEHClearUnwoundToCall ( Loc ) ; else return true ; } else return true ; return false ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


"Unrecognized Hexagon processor version"

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s>
int
arc_output_commutative_cond_exec
(
rtx
*
operands
,
bool
output_p
)
{
enum
rtx_code
commutative_op
=
GET_CODE
(
operands
[
3
]
)
;
const
char
*
pat
=
;
gcc_assert
(
!
CONSTANT_P
(
operands
[
1
]
)
)
;
switch
(
commutative_op
)
{
case
AND
:
if
(
satisfies_constraint_C1p
(
operands
[
2
]
)
)
pat
=
"bmsk%? %0,%1,%Z2"
;
else
if
(
satisfies_constraint_C2p
(
operands
[
2
]
)
)
{
operands
[
2
]
=
GEN_INT
(
(
~
INTVAL
(
operands
[
2
]
)
)
)
;
pat
=
"bmskn%? %0,%1,%Z2"
;
}
else
if
(
satisfies_constraint_Ccp
(
operands
[
2
]
)
)
pat
=
"bclr%? %0,%1,%M2"
;
else
if
(
satisfies_constraint_CnL
(
operands
[
2
]
)
)
pat
=
"bic%? %0,%1,%n2-1"
;
break
;
case
IOR
:
if
(
satisfies_constraint_C0p
(
operands
[
2
]
)
)
pat
=
"bset%? %0,%1,%z2"
;
break
;
case
XOR
:
if
(
satisfies_constraint_C0p
(
operands
[
2
]
)
)
pat
=
"bxor%? %0,%1,%z2"
;
break
;
case
PLUS
:
return
arc_output_addsi
(
operands
,
true
,
output_p
)
;
default
:
break
;
}
if
(
output_p
)
output_asm_insn
(
pat
pat
:
"%O3.%d5 %0,%1,%2"
,
operands
)
;
if
(
pat
||
REG_P
(
operands
[
2
]
)
||
satisfies_constraint_L
(
operands
[
2
]
)
)
return
4
;
return
8
;
}
</s>

Emit code for an commutative_cond_exec instruction with OPERANDS . Return the length of the instruction . If OUTPUT_P is false , do n't actually output the instruction , just return its length .


<s> unsigned WebAssemblyFastISel :: zeroExtend ( unsigned Reg , const Value * V , MVT :: SimpleValueType From , MVT :: SimpleValueType To ) { if ( To == MVT :: i64 ) { if ( From == MVT :: i64 ) return copyValue ( Reg ) ; Reg = zeroExtendToI32 ( Reg , V , From ) ; Register Result = createResultReg ( & WebAssembly :: I64RegClass ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( WebAssembly :: I64_EXTEND_U_I32 ) , Result ) . addReg ( Reg ) ; return Result ; } if ( To == MVT :: i32 ) return zeroExtendToI32 ( Reg , V , From ) ; return 0 ; } </s>

Return a new range in the specified integer type , which must be strictly larger than the current type .


"ARM pre- register allocation load / store optimization pass"

getPassName - Return a nice clean name for a pass .


<s> int sh_loop_align ( rtx label ) { rtx next = label ; do next = next_nonnote_insn ( next ) ; while ( next && GET_CODE ( next ) == CODE_LABEL ) ; if ( ! next || ! INSN_P ( next ) || GET_CODE ( PATTERN ( next ) ) == ADDR_DIFF_VEC || recog_memoized ( next ) == CODE_FOR_consttable_2 ) return 0 ; return align_loops_log ; } </s>

If we are inside a phony loop , almost any kind of label can turn up as the first one in the loop . Aligning a braf label causes incorrect switch destination addresses ; we can detect braf labels because they are followed by a BARRIER . Applying loop alignment to small constant or switch tables is a waste of space , so we suppress this too .


<s> static int tilegx_multiply_get_num_ops ( const struct tilegx_multiply_insn_seq * seq ) { int i ; for ( i = tilegx_multiply_insn_seq_MAX_OPERATIONS - 1 ; i >= 0 ; i -- ) if ( tilegx_multiply_get_opcode ( & seq -> op [ i ] ) != CODE_FOR_nothing ) return i + 1 ; gcc_unreachable ( ) ; } </s>


<s> void SparcRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const SparcSubtarget & Subtarget = MF . getSubtarget < SparcSubtarget > ( ) ; const SparcFrameLowering * TFI = getFrameLowering ( MF ) ; unsigned FrameReg ; int Offset ; Offset = TFI -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) ; Offset += MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ; if ( ! Subtarget . isV9 ( ) || ! Subtarget . hasHardQuad ( ) ) { if ( MI . getOpcode ( ) == SP :: STQFri ) { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; unsigned SrcReg = MI . getOperand ( 2 ) . getReg ( ) ; unsigned SrcEvenReg = getSubReg ( SrcReg , SP :: sub_even64 ) ; unsigned SrcOddReg = getSubReg ( SrcReg , SP :: sub_odd64 ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( SP :: STDFri ) ) . addReg ( FrameReg ) . addImm ( 0 ) . addReg ( SrcEvenReg ) ; replaceFI ( MF , * StMI , * StMI , dl , 0 , Offset , FrameReg ) ; MI . setDesc ( TII . get ( SP :: STDFri ) ) ; MI . getOperand ( 2 ) . setReg ( SrcOddReg ) ; Offset += 8 ; } else if ( MI . getOpcode ( ) == SP :: LDQFri ) { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; unsigned DestReg = MI . getOperand ( 0 ) . getReg ( ) ; unsigned DestEvenReg = getSubReg ( DestReg , SP :: sub_even64 ) ; unsigned DestOddReg = getSubReg ( DestReg , SP :: sub_odd64 ) ; MachineInstr * LdMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( SP :: LDDFri ) , DestEvenReg ) . addReg ( FrameReg ) . addImm ( 0 ) ; replaceFI ( MF , * LdMI , * LdMI , dl , 1 , Offset , FrameReg ) ; MI . setDesc ( TII . get ( SP :: LDDFri ) ) ; MI . getOperand ( 0 ) . setReg ( DestOddReg ) ; Offset += 8 ; } } replaceFI ( MF , II , MI , dl , FIOperandNum , Offset , FrameReg ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> void PIC16AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; printInstruction ( MI , OS ) ; OutStreamer . EmitRawText ( OS . str ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 Encode Literals"
;
}
</s>


<s>
SDNode
*
MipsDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
std
::
pair
<
bool
,
SDNode
*
>
Ret
=
selectNode
(
Node
)
;
if
(
Ret
.
first
)
return
Ret
.
second
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
return
getGlobalBaseReg
(
)
;
case
ISD
::
LOAD
:
case
ISD
::
STORE
:
assert
(
cast
<
MemSDNode
>
(
Node
)
->
getMemoryVT
(
)
.
getSizeInBits
(
)
/
8
<=
cast
<
MemSDNode
>
(
Node
)
->
getAlignment
(
)
&&
"Unexpected unaligned loads/stores."
)
;
break
;
}
SDNode
*
ResNode
=
SelectCode
(
Node
)
;
DEBUG
(
errs
(
)
<<
"=> "
)
;
if
(
ResNode
==
||
ResNode
==
Node
)
DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
else
DEBUG
(
ResNode
->
dump
(
CurDAG
)
)
;
DEBUG
(
errs
(
)
<<
"\n"
)
;
return
ResNode
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

Mips
Mips
"Selecting: "
"\n"
"== "
"\n"
1
ISD::GLOBAL_OFFSET_TABLE
ISD::LOAD
ISD::STORE
8
"Unexpected unaligned loads/stores."
"=> "
"\n"


<s> bool AVRMCExpr :: evaluateAsConstant ( int64_t & Result ) const { MCValue Value ; bool isRelocatable = getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ; if ( ! isRelocatable ) return false ; if ( Value . isAbsolute ( ) ) { Result = evaluateAsInt64 ( Value . getConstant ( ) ) ; return true ; } return false ; } </s>

Evaluates the fixup as a constant value .


<s>
unsigned
X86TTIImpl
::
getScalarizationOverhead
(
Type
*
Ty
,
bool
Insert
,
bool
Extract
)
{
assert
(
Ty
->
isVectorTy
(
)
&&
"Can only scalarize vectors"
)
;
unsigned
Cost
=
0
;
for
(
int
i
=
0
,
e
=
Ty
->
getVectorNumElements
(
)
;
i
<
e
;
++
i
)
{
if
(
Insert
)
Cost
+=
getVectorInstrCost
(
Instruction
::
InsertElement
,
Ty
,
i
)
;
if
(
Extract
)
Cost
+=
getVectorInstrCost
(
Instruction
::
ExtractElement
,
Ty
,
i
)
;
}
return
Cost
;
}
</s>

Estimate the overhead of scalarizing an instruction .


<s> const CallLowering * M68kSubtarget :: getCallLowering ( ) const { return CallLoweringInfo . get ( ) ; } </s>


"function_arg_pass_by_reference: V4 IEEE 128-bit\n"

"non-standard ABI extension with no compatibility guarantee"

A C expression that indicates when an argument must be passed by reference . If nonzero for an argument , a copy of that argument is made in memory and a pointer to the argument is passed instead of the argument itself . The pointer is passed in whatever way is appropriate for passing a pointer to that type . Under V.4 , aggregates and long double are passed by reference . As an extension to all 32-bit ABIs , AltiVec vectors are passed by reference unless the AltiVec vector extension ABI is in force . As an extension to all ABIs , variable sized types are passed by reference .


<s> virtual const WDC65816RegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool X86TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( VT . getSizeInBits ( ) == 64 ) return false ; return ( VT . getVectorNumElements ( ) == 2 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isMOVLMask ( M , VT ) || isSHUFPMask ( M , VT , Subtarget -> hasAVX ( ) ) || isPSHUFDMask ( M , VT ) || isPSHUFHWMask ( M , VT , Subtarget -> hasAVX2 ( ) ) || isPSHUFLWMask ( M , VT , Subtarget -> hasAVX2 ( ) ) || isPALIGNRMask ( M , VT , Subtarget ) || isUNPCKLMask ( M , VT , Subtarget -> hasAVX2 ( ) ) || isUNPCKHMask ( M , VT , Subtarget -> hasAVX2 ( ) ) || isUNPCKL_v_undef_Mask ( M , VT , Subtarget -> hasAVX2 ( ) ) || isUNPCKH_v_undef_Mask ( M , VT , Subtarget -> hasAVX2 ( ) ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> void SparcFrameLowering :: emitPrologue ( MachineFunction & MF ) const { SparcMachineFunctionInfo * FuncInfo = MF . getInfo < SparcMachineFunctionInfo > ( ) ; MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const SparcInstrInfo & TII = * static_cast < const SparcInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; unsigned SAVEri = SP :: SAVEri ; unsigned SAVErr = SP :: SAVErr ; if ( FuncInfo -> isLeafProc ( ) ) { if ( NumBytes == 0 ) return ; SAVEri = SP :: ADDri ; SAVErr = SP :: ADDrr ; } NumBytes = - MF . getTarget ( ) . getSubtarget < SparcSubtarget > ( ) . getAdjustedFrameSize ( NumBytes ) ; emitSPAdjustment ( MF , MBB , MBBI , NumBytes , SAVErr , SAVEri ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; unsigned regFP = MRI -> getDwarfRegNum ( SP :: I6 , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , regFP ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createWindowSave ( nullptr ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; unsigned regInRA = MRI -> getDwarfRegNum ( SP :: I7 , true ) ; unsigned regOutRA = MRI -> getDwarfRegNum ( SP :: O7 , true ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createRegister ( nullptr , regOutRA , regInRA ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } </s>

Sparc Sparc Sparc Sparc Sparc Sparc SP::SAVEri SP::SAVErr 0 SP::ADDri SP::ADDrr Sparc SP SP::I6 SP::I7 SP::O7


<s>
const
char
*
getPassName
(
)
const
override
{
return
"SI insert wait  instructions"
;
}
</s>


<s> static void recombine_lvx_stvx_patterns ( function * fun ) { int i ; basic_block bb ; rtx_insn * insn ; int num_insns = get_max_uid ( ) ; del_info * to_delete = XCNEWVEC ( del_info , num_insns ) ; FOR_ALL_BB_FN ( bb , fun ) FOR_BB_INSNS ( bb , insn ) { if ( ! NONDEBUG_INSN_P ( insn ) ) continue ; if ( insn_is_load_p ( insn ) && insn_is_swap_p ( insn ) ) recombine_lvx_pattern ( insn , to_delete ) ; else if ( insn_is_store_p ( insn ) && insn_is_swap_p ( insn ) ) recombine_stvx_pattern ( insn , to_delete ) ; } for ( i = 0 ; i < num_insns ; i ++ ) if ( to_delete [ i ] . replace ) { rtx swap_body = PATTERN ( to_delete [ i ] . replace_insn ) ; rtx src_reg = XEXP ( SET_SRC ( swap_body ) , 0 ) ; rtx copy = gen_rtx_SET ( SET_DEST ( swap_body ) , src_reg ) ; rtx_insn * new_insn = emit_insn_before ( copy , to_delete [ i ] . replace_insn ) ; set_block_for_insn ( new_insn , BLOCK_FOR_INSN ( to_delete [ i ] . replace_insn ) ) ; df_insn_rescan ( new_insn ) ; df_insn_delete ( to_delete [ i ] . replace_insn ) ; remove_insn ( to_delete [ i ] . replace_insn ) ; to_delete [ i ] . replace_insn -> set_deleted ( ) ; } free ( to_delete ) ; } </s>

Look for patterns created from builtin lvx and stvx calls , and canonicalize them to be properly recognized as such .


<s> static int riscv_flatten_aggregate_argument ( const_tree type , riscv_aggregate_field fields [ 2 ] , bool ignore_zero_width_bit_field_p ) { if ( ! type || TREE_CODE ( type ) != RECORD_TYPE ) return - 1 ; return riscv_flatten_aggregate_field ( type , fields , 0 , 0 , ignore_zero_width_bit_field_p ) ; } </s>

Identify candidate aggregates for passing in floating-point registers . Candidates have at most two fields after flattening .


<s> bool X86TargetLowering :: isUsedByReturnOnly ( SDNode * N , SDValue & Chain ) const { if ( N -> getNumValues ( ) != 1 ) return false ; if ( ! N -> hasNUsesOfValue ( 1 , 0 ) ) return false ; SDValue TCChain = Chain ; SDNode * Copy = * N -> use_begin ( ) ; if ( Copy -> getOpcode ( ) == ISD :: CopyToReg ) { if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - 1 ) . getValueType ( ) == MVT :: Glue ) return false ; TCChain = Copy -> getOperand ( 0 ) ; } else if ( Copy -> getOpcode ( ) != ISD :: FP_EXTEND ) return false ; bool HasRet = false ; for ( SDNode :: use_iterator UI = Copy -> use_begin ( ) , UE = Copy -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != X86ISD :: RET_FLAG ) return false ; if ( UI -> getNumOperands ( ) > 4 ) return false ; if ( UI -> getNumOperands ( ) == 4 && UI -> getOperand ( UI -> getNumOperands ( ) - 1 ) . getValueType ( ) != MVT :: Glue ) return false ; HasRet = true ; } if ( ! HasRet ) return false ; Chain = TCChain ; return true ; } </s>

Return true if result of the specified node is used by a return node only .


<s>
int
IA64RegisterInfo
::
getDwarfRegNum
(
unsigned
RegNum
,
bool
isEH
)
const
{
assert
(
0
&&
"What is the dwarf register number"
)
;
return
1
;
}
</s>

Map a target register to an equivalent dwarf register number .


<s> static enum flt_eval_method aarch64_excess_precision ( enum excess_precision_type type ) { switch ( type ) { case EXCESS_PRECISION_TYPE_FAST : case EXCESS_PRECISION_TYPE_STANDARD : return ( TARGET_FP_F16INST ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16 : FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ) ; case EXCESS_PRECISION_TYPE_IMPLICIT : return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16 ; default : gcc_unreachable ( ) ; } return FLT_EVAL_METHOD_UNPREDICTABLE ; } </s>

Set the value of FLT_EVAL_METHOD . ISO/IEC TS 18661-3 defines two values that we 'd like to make use of : 0 : evaluate all operations and constants , whose semantic type has at most the range and precision of type float , to the range and precision of float ; evaluate all other operations and constants to the range and precision of the semantic type ; N , where _FloatN is a supported interchange floating type evaluate all operations and constants , whose semantic type has at most the range and precision of _FloatN type , to the range and precision of the _FloatN type ; evaluate all other operations and constants to the range and precision of the semantic type ; If we have the ARMv8.2-A extensions then we support _Float16 in native precision , so we should set this to 16 . Otherwise , we support the type , but want to evaluate expressions in float precision , so set this to 0 .


<s> bool AMDGPUInstrInfo :: isSafeToMoveRegClassDefs ( const TargetRegisterClass * RC ) const { return true ; } </s>

isSafeToMoveRegClassDefs - Return true if it 's safe to move a machine instruction that defines the specified register class .


<s> bool BPFRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> static void avr_insert_attributes ( tree node , tree * attributes ) { if ( TREE_CODE ( node ) == VAR_DECL && ( TREE_STATIC ( node ) || DECL_EXTERNAL ( node ) ) && avr_progmem_p ( node , * attributes ) ) { static const char dsec [ ] = ".progmem.data" ; * attributes = tree_cons ( get_identifier ( "section" ) , build_tree_list ( NULL , build_string ( strlen ( dsec ) , dsec ) ) , * attributes ) ; TREE_READONLY ( node ) = 1 ; } } </s>

Add the section attribute if the variable is in progmem .


<s> const Function & getFunction ( ) const { return Fn ; } </s>

getFunction - Return this trace 's parent function .


<s> bool XNCMPassConfig :: addInstSelector ( ) { PM . add ( createXNCMISelDag ( getXNCMTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> unsigned ARMFastISel :: fastMaterializeAlloca ( const AllocaInst * AI ) { if ( ! FuncInfo . StaticAllocaMap . count ( AI ) ) return 0 ; MVT VT ; if ( ! isLoadTypeLegal ( AI -> getType ( ) , VT ) ) return 0 ; DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( AI ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { unsigned Opc = isThumb2 ? ARM :: t2ADDri : ARM :: ADDri ; const TargetRegisterClass * RC = TLI . getRegClassFor ( VT ) ; Register ResultReg = createResultReg ( RC ) ; ResultReg = constrainOperandRegClass ( TII . get ( Opc ) , ResultReg , 0 ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addFrameIndex ( SI -> second ) . addImm ( 0 ) ) ; return ResultReg ; } return 0 ; } </s>

Emit an alloca address in a register using target-specific logic .


<s>
StringRef
getPassName
(
)
const
override
{
return
"ARM Execution Domain Fix"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
int
SparcRegisterInfo
::
getDwarfRegNum
(
unsigned
RegNum
,
bool
isEH
)
const
{
assert
(
0
&&
"What is the dwarf register number"
)
;
return
1
;
}
</s>


<s> static bool reg_offset_addressing_ok_p ( machine_mode mode ) { switch ( mode ) { case E_V16QImode : case E_V8HImode : case E_V4SFmode : case E_V4SImode : case E_V2DFmode : case E_V2DImode : case E_V1TImode : case E_TImode : case E_TFmode : case E_KFmode : if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) ) return mode_supports_dq_form ( mode ) ; break ; case E_OOmode : case E_XOmode : return TARGET_MMA ; case E_SDmode : if ( TARGET_NO_SDMODE_STACK ) return false ; break ; default : break ; } return true ; } </s>

Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p .


<s> bool HexagonGenInsert :: isConstant ( unsigned VR ) const { const BitTracker :: RegisterCell & RC = CMS -> lookup ( VR ) ; uint16_t W = RC . width ( ) ; for ( uint16_t i = 0 ; i < W ; ++ i ) { const BitTracker :: BitValue & BV = RC [ i ] ; if ( BV . is ( 0 ) || BV . is ( 1 ) ) continue ; return false ; } return true ; } </s>

Returns true if we know the value of all bits .


"this operation requires the SVE ISA extension"

"you can enable SVE using the command-line"

" option %<-march%>, or by using the %<target%>"

Report when we try to do something that requires SVE when SVE is disabled . This is an error of last resort and is n't very high-quality . It usually involves attempts to measure the vector length in some way .


<s> BitVector SPURegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( SPU :: R0 ) ; Reserved . set ( SPU :: R1 ) ; Reserved . set ( SPU :: R2 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool X86InstrInfo :: hasHighOperandLatency ( const InstrItineraryData * ItinData , const MachineRegisterInfo * MRI , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * UseMI , unsigned UseIdx ) const { switch ( DefMI -> getOpcode ( ) ) { default : return false ; case X86 :: DIVSDrm : case X86 :: DIVSDrm_Int : case X86 :: DIVSDrr : case X86 :: DIVSDrr_Int : case X86 :: DIVSSrm : case X86 :: DIVSSrm_Int : case X86 :: DIVSSrr : case X86 :: DIVSSrr_Int : case X86 :: SQRTPDm : case X86 :: SQRTPDm_Int : case X86 :: SQRTPDr : case X86 :: SQRTPDr_Int : case X86 :: SQRTPSm : case X86 :: SQRTPSm_Int : case X86 :: SQRTPSr : case X86 :: SQRTPSr_Int : case X86 :: SQRTSDm : case X86 :: SQRTSDm_Int : case X86 :: SQRTSDr : case X86 :: SQRTSDr_Int : case X86 :: SQRTSSm : case X86 :: SQRTSSm_Int : case X86 :: SQRTSSr : case X86 :: SQRTSSr_Int : return true ; } } </s>

Compute operand latency between a def of 'Reg ' and a use in the current loop .


"unknown parameter to option -mtune-ctrl: %s"

parse -mtune-ctrl= option . When DUMP is true , print the features that are explicitly set .


<s> static void s390_reg_clobbered_rtx ( rtx setreg , const_rtx set_insn ATTRIBUTE_UNUSED , void * data ) { char * regs_ever_clobbered = ( char * ) data ; unsigned int i , regno ; machine_mode mode = GET_MODE ( setreg ) ; if ( GET_CODE ( setreg ) == SUBREG ) { rtx inner = SUBREG_REG ( setreg ) ; if ( ! GENERAL_REG_P ( inner ) && ! FP_REG_P ( inner ) ) return ; regno = subreg_regno ( setreg ) ; } else if ( GENERAL_REG_P ( setreg ) || FP_REG_P ( setreg ) ) regno = REGNO ( setreg ) ; else return ; for ( i = regno ; i < end_hard_regno ( mode , regno ) ; i ++ ) regs_ever_clobbered [ i ] = 1 ; } </s>

Helper function for s390_regs_ever_clobbered . Sets the fields in DATA for all clobbered hard regs in SETREG .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { TM = static_cast < const PPCTargetMachine * > ( & MF . getTarget ( ) ) ; TII = TM -> getInstrInfo ( ) ; bool Changed = false ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed = true ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool or1k_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( REGNO_REG_CLASS ( regno ) == FLAG_REGS ) return mode == BImode ; return true ; } </s>

Worker for TARGET_HARD_REGNO_MODE_OK . Returns true if the hard register REGNO is ok for storing values of mode MODE .


<s> ArrayRef < uint64_t > getReferencedAddresses ( ) const override { return ReferencedAddresses ; } </s>

Get the MCSymbolizer 's list of addresses that were referenced by symbolizable operands but not resolved to a symbol .


<s> bool AMDGPUCFGStructurizer :: prepare ( ) { bool Changed = false ; DEBUG ( dbgs ( ) << "AMDGPUCFGStructurizer::prepare\n" ; ) ; orderBlocks ( FuncRep ) ; SmallVector < MachineBasicBlock * , DEFAULT_VEC_SLOTS > RetBlks ; for ( MachineLoopInfo :: iterator It = MLI -> begin ( ) , E = MLI -> end ( ) ; It != E ; ++ It ) { MachineLoop * LoopRep = ( * It ) ; MBBVector ExitingMBBs ; LoopRep -> getExitingBlocks ( ExitingMBBs ) ; if ( ExitingMBBs . size ( ) == 0 ) { MachineBasicBlock * DummyExitBlk = normalizeInfiniteLoopExit ( LoopRep ) ; if ( DummyExitBlk ) RetBlks . push_back ( DummyExitBlk ) ; } } for ( SmallVectorImpl < MachineBasicBlock * > :: const_iterator It = OrderedBlks . begin ( ) , E = OrderedBlks . end ( ) ; It != E ; ++ It ) { MachineBasicBlock * MBB = * It ; removeUnconditionalBranch ( MBB ) ; removeRedundantConditionalBranch ( MBB ) ; if ( isReturnBlock ( MBB ) ) { RetBlks . push_back ( MBB ) ; } assert ( MBB -> succ_size ( ) <= 2 ) ; } if ( RetBlks . size ( ) >= 2 ) { addDummyExitBlock ( RetBlks ) ; Changed = true ; } return Changed ; } </s>

prepare - Reset state and prepare for a new spill placement computation .


<s> SDNode * SITargetLowering :: PostISelFolding ( MachineSDNode * Node , SelectionDAG & DAG ) const { const SIInstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; unsigned Opcode = Node -> getMachineOpcode ( ) ; if ( TII -> isMIMG ( Opcode ) && ! TII -> get ( Opcode ) . mayStore ( ) && ! TII -> isGather4 ( Opcode ) ) { return adjustWritemask ( Node , DAG ) ; } if ( Opcode == AMDGPU :: INSERT_SUBREG || Opcode == AMDGPU :: REG_SEQUENCE ) { legalizeTargetIndependentNode ( Node , DAG ) ; return Node ; } switch ( Opcode ) { case AMDGPU :: V_DIV_SCALE_F32 : case AMDGPU :: V_DIV_SCALE_F64 : { SDValue Src0 = Node -> getOperand ( 0 ) ; SDValue Src1 = Node -> getOperand ( 1 ) ; SDValue Src2 = Node -> getOperand ( 2 ) ; if ( ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) != AMDGPU :: IMPLICIT_DEF ) && ( Src0 == Src1 || Src0 == Src2 ) ) break ; MVT VT = Src0 . getValueType ( ) . getSimpleVT ( ) ; const TargetRegisterClass * RC = getRegClassFor ( VT ) ; MachineRegisterInfo & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue UndefReg = DAG . getRegister ( MRI . createVirtualRegister ( RC ) , VT ) ; SDValue ImpDef = DAG . getCopyToReg ( DAG . getEntryNode ( ) , SDLoc ( Node ) , UndefReg , Src0 , SDValue ( ) ) ; if ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) == AMDGPU :: IMPLICIT_DEF ) { if ( Src1 . isMachineOpcode ( ) && Src1 . getMachineOpcode ( ) != AMDGPU :: IMPLICIT_DEF ) Src0 = Src1 ; else if ( Src2 . isMachineOpcode ( ) && Src2 . getMachineOpcode ( ) != AMDGPU :: IMPLICIT_DEF ) Src0 = Src2 ; else { assert ( Src1 . getMachineOpcode ( ) == AMDGPU :: IMPLICIT_DEF ) ; Src0 = UndefReg ; Src1 = UndefReg ; } } else break ; SmallVector < SDValue , 4 > Ops = { Src0 , Src1 , Src2 } ; for ( unsigned I = 3 , N = Node -> getNumOperands ( ) ; I != N ; ++ I ) Ops . push_back ( Node -> getOperand ( I ) ) ; Ops . push_back ( ImpDef . getValue ( 1 ) ) ; return DAG . getMachineNode ( Opcode , SDLoc ( Node ) , Node -> getVTList ( ) , Ops ) ; } default : break ; } return Node ; } </s>

Fold the instructions after selecting them .


<s> virtual unsigned getJumpTableEncoding ( ) const { return MachineJumpTableInfo :: EK_Custom32 ; } </s>

Return the entry encoding for a jump table in the current function .


<s> static bool is_load_p ( rtx_insn * insn ) { enum attr_itanium_class insn_class = ia64_safe_itanium_class ( insn ) ; return ( ( insn_class == ITANIUM_CLASS_LD || insn_class == ITANIUM_CLASS_FLD ) && get_attr_check_load ( insn ) == CHECK_LOAD_NO ) ; } </s>

Return TRUE if INSN is a load ( either normal or speculative , but not a speculation check ) , FALSE otherwise .


"      \"\", RS6000_BIF_NONE, NULL_TREE, NULL\n"

Write the decls and initializers for rs6000_overload_info [ ] and rs6000_instance_info [ ] .


" is allocatable: function has no frame pointer"

Return the register ID of the name passed in .


<s> bool ix86_vec_interleave_v2df_operator_ok ( rtx operands [ 3 ] , bool high ) { if ( MEM_P ( operands [ 0 ] ) ) return rtx_equal_p ( operands [ 0 ] , operands [ 1 + high ] ) ; if ( MEM_P ( operands [ 1 ] ) && MEM_P ( operands [ 2 ] ) ) return false ; return true ; } </s>

Return TRUE if the operands to a vec_interleave_ { high , low } v2df are ok , keeping in mind the possible movddup alternative .


<s> void cris_expand_return ( bool on_stack ) { emit_jump_insn ( gen_rtx_RETURN ( VOIDmode ) ) ; CRIS_ASSERT ( cfun -> machine -> return_type != CRIS_RETINSN_RET || ! on_stack ) ; CRIS_ASSERT ( cfun -> machine -> return_type != CRIS_RETINSN_JUMP || on_stack ) ; cfun -> machine -> return_type = on_stack ? CRIS_RETINSN_JUMP : CRIS_RETINSN_RET ; } </s>

Expand a return insn ( just one insn ) marked as using SRP or stack slot depending on parameter ON_STACK .


<s> bool alpha_legitimate_address_p ( enum machine_mode mode , rtx x , int strict ) { if ( mode == DImode && GET_CODE ( x ) == AND && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT && INTVAL ( XEXP ( x , 1 ) ) == - 8 ) x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == SUBREG && ( GET_MODE_SIZE ( GET_MODE ( x ) ) < GET_MODE_SIZE ( GET_MODE ( SUBREG_REG ( x ) ) ) ) ) x = SUBREG_REG ( x ) ; if ( REG_P ( x ) && ( strict ? STRICT_REG_OK_FOR_BASE_P ( x ) : NONSTRICT_REG_OK_FOR_BASE_P ( x ) ) ) return true ; if ( CONSTANT_ADDRESS_P ( x ) ) return true ; if ( LINKAGE_SYMBOL_REF_P ( x ) ) return true ; if ( GET_CODE ( x ) == PLUS ) { rtx ofs = XEXP ( x , 1 ) ; x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == SUBREG && ( GET_MODE_SIZE ( GET_MODE ( x ) ) < GET_MODE_SIZE ( GET_MODE ( SUBREG_REG ( x ) ) ) ) ) x = SUBREG_REG ( x ) ; if ( REG_P ( x ) ) { if ( ! strict && NONSTRICT_REG_OK_FP_BASE_P ( x ) && GET_CODE ( ofs ) == CONST_INT ) return true ; if ( ( strict ? STRICT_REG_OK_FOR_BASE_P ( x ) : NONSTRICT_REG_OK_FOR_BASE_P ( x ) ) && CONSTANT_ADDRESS_P ( ofs ) ) return true ; } } else if ( TARGET_EXPLICIT_RELOCS ) { if ( small_symbolic_operand ( x , Pmode ) ) return true ; if ( GET_CODE ( x ) == LO_SUM ) { rtx ofs = XEXP ( x , 1 ) ; x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == SUBREG && ( GET_MODE_SIZE ( GET_MODE ( x ) ) < GET_MODE_SIZE ( GET_MODE ( SUBREG_REG ( x ) ) ) ) ) x = SUBREG_REG ( x ) ; if ( ! ( REG_P ( x ) && ( strict ? STRICT_REG_OK_FOR_BASE_P ( x ) : NONSTRICT_REG_OK_FOR_BASE_P ( x ) ) ) ) return false ; if ( local_symbolic_operand ( ofs , Pmode ) || dtp32_symbolic_operand ( ofs , Pmode ) || tp32_symbolic_operand ( ofs , Pmode ) ) return true ; } } return false ; } </s>

legitimate_address_p recognizes an RTL expression that is a valid memory address for an instruction . The MODE argument is the machine mode for the MEM expression that wants to use this address . For Alpha , we have either a constant address or the sum of a register and a constant address , or just a register . For DImode , any of those forms can be surrounded with an AND that clear the low-order three bits ; this is an `` unaligned '' access .


<s> bool PPCTTIImpl :: getTgtMemIntrinsic ( IntrinsicInst * Inst , MemIntrinsicInfo & Info ) { switch ( Inst -> getIntrinsicID ( ) ) { case Intrinsic :: ppc_altivec_lvx : case Intrinsic :: ppc_altivec_lvxl : case Intrinsic :: ppc_altivec_lvebx : case Intrinsic :: ppc_altivec_lvehx : case Intrinsic :: ppc_altivec_lvewx : case Intrinsic :: ppc_vsx_lxvd2x : case Intrinsic :: ppc_vsx_lxvw4x : case Intrinsic :: ppc_vsx_lxvd2x_be : case Intrinsic :: ppc_vsx_lxvw4x_be : case Intrinsic :: ppc_vsx_lxvl : case Intrinsic :: ppc_vsx_lxvll : case Intrinsic :: ppc_mma_lxvp : { Info . PtrVal = Inst -> getArgOperand ( 0 ) ; Info . ReadMem = true ; Info . WriteMem = false ; return true ; } case Intrinsic :: ppc_altivec_stvx : case Intrinsic :: ppc_altivec_stvxl : case Intrinsic :: ppc_altivec_stvebx : case Intrinsic :: ppc_altivec_stvehx : case Intrinsic :: ppc_altivec_stvewx : case Intrinsic :: ppc_vsx_stxvd2x : case Intrinsic :: ppc_vsx_stxvw4x : case Intrinsic :: ppc_vsx_stxvd2x_be : case Intrinsic :: ppc_vsx_stxvw4x_be : case Intrinsic :: ppc_vsx_stxvl : case Intrinsic :: ppc_vsx_stxvll : case Intrinsic :: ppc_mma_stxvp : { Info . PtrVal = Inst -> getArgOperand ( 1 ) ; Info . ReadMem = false ; Info . WriteMem = true ; return true ; } default : break ; } return false ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> bool mem_operand_gpr ( rtx op , machine_mode mode ) { unsigned HOST_WIDE_INT offset ; int extra ; rtx addr = XEXP ( op , 0 ) ; op = address_offset ( addr ) ; if ( op == NULL_RTX ) return true ; offset = INTVAL ( op ) ; if ( TARGET_POWERPC64 && ( offset & 3 ) != 0 ) return false ; extra = GET_MODE_SIZE ( mode ) - UNITS_PER_WORD ; if ( extra < 0 ) extra = 0 ; if ( GET_CODE ( addr ) == LO_SUM ) offset = ( ( offset & 0xffff ) ^ 0x8000 ) - 0x8000 ; return offset + 0x8000 < 0x10000u - extra ; } </s>

Return true if the MEM operand is a memory operand suitable for use with a ( full width , possibly multiple ) gpr load/store . On powerpc64 this means the offset must be divisible by 4 . Implements ' Y ' constraint . Accept direct , indexed , offset , lo_sum and tocref . Since this is a constraint function we know the operand has satisfied a suitable memory predicate . Offsetting a lo_sum should not be allowed , except where we know by alignment that a 32k boundary is not crossed . Note that by `` offsetting '' here we mean a further offset to access parts of the MEM . It 's fine to have a lo_sum where the inner address is offset from a sym , since the same sym+offset will appear in the high part of the address calculation .


<s> static ARMCC :: CondCodes getPredicate ( const MachineInstr * MI , const Thumb2InstrInfo * TII ) { unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == ARM :: tBcc || Opc == ARM :: t2Bcc ) return ARMCC :: AL ; return TII -> getPredicate ( MI ) ; } </s>

Returns the comparison predicate underlying the intrinsic .

ARM ARMCC::CondCodes ARM::tBcc ARM::t2Bcc ARMCC::AL


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { for ( uint64_t i = 0 ; i != Count ; ++ i ) OW -> Write8 ( 0 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> bool splitFramePushPop ( ) const { return isTargetMachO ( ) ; } </s>

Returns true if the frame setup is split into two separate pushes ( first r0-r7 , lr then r8-r11 ) , principally so that the frame pointer is adjacent to lr .


<s> void Mips16FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( STI . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( StackSize == 0 && ! MFI . adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; TII . makeFrame ( Mips :: SP , StackSize , MBB , MBBI ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , StackSize ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; if ( ! CSI . empty ( ) ) { const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( const CalleeSavedInfo & I : CSI ) { int64_t Offset = MFI . getObjectOffset ( I . getFrameIdx ( ) ) ; Register Reg = I . getReg ( ) ; unsigned DReg = MRI -> getDwarfRegNum ( Reg , true ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DReg , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: MoveR3216 ) , Mips :: S0 ) . addReg ( Mips :: SP ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Mips Mips Mips Mips 0 Mips::SP Mips::MoveR3216 Mips::S0 Mips::SP


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { bool is64 = getPointerSize ( ) == 8 ; return createPPCMachObjectWriter ( OS , is64 , ( is64 ? MachO :: CPU_TYPE_POWERPC64 : MachO :: CPU_TYPE_POWERPC ) , MachO :: CPU_SUBTYPE_POWERPC_ALL ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s>
static
void
arm_unwind_emit_set
(
FILE
*
out_file
,
rtx
p
)
{
rtx
e0
;
rtx
e1
;
unsigned
reg
;
e0
=
XEXP
(
p
,
0
)
;
e1
=
XEXP
(
p
,
1
)
;
switch
(
GET_CODE
(
e0
)
)
{
case
MEM
:
if
(
GET_CODE
(
XEXP
(
e0
,
0
)
)
!=
PRE_DEC
||
!
REG_P
(
XEXP
(
XEXP
(
e0
,
0
)
,
0
)
)
||
REGNO
(
XEXP
(
XEXP
(
e0
,
0
)
,
0
)
)
!=
SP_REGNUM
)
abort
(
)
;
asm_fprintf
(
out_file
,
"\t.save "
)
;
if
(
IS_VFP_REGNUM
(
REGNO
(
e1
)
)
)
asm_fprintf
(
out_file
,
"{d%d}\n"
,
(
REGNO
(
e1
)
FIRST_VFP_REGNUM
)
/
2
)
;
else
asm_fprintf
(
out_file
,
"{%r}\n"
,
REGNO
(
e1
)
)
;
break
;
case
REG
:
if
(
REGNO
(
e0
)
==
SP_REGNUM
)
{
if
(
GET_CODE
(
e1
)
!=
PLUS
||
!
REG_P
(
XEXP
(
e1
,
0
)
)
||
REGNO
(
XEXP
(
e1
,
0
)
)
!=
SP_REGNUM
||
!
CONST_INT_P
(
XEXP
(
e1
,
1
)
)
)
abort
(
)
;
asm_fprintf
(
out_file
,
"\t.pad #%wd\n"
,
INTVAL
(
XEXP
(
e1
,
1
)
)
)
;
}
else
if
(
REGNO
(
e0
)
==
HARD_FRAME_POINTER_REGNUM
)
{
HOST_WIDE_INT
offset
;
if
(
GET_CODE
(
e1
)
==
PLUS
)
{
if
(
!
REG_P
(
XEXP
(
e1
,
0
)
)
||
!
CONST_INT_P
(
XEXP
(
e1
,
1
)
)
)
abort
(
)
;
reg
=
REGNO
(
XEXP
(
e1
,
0
)
)
;
offset
=
INTVAL
(
XEXP
(
e1
,
1
)
)
;
asm_fprintf
(
out_file
,
"\t.setfp %r, %r, #%wd\n"
,
HARD_FRAME_POINTER_REGNUM
,
reg
,
offset
)
;
}
else
if
(
REG_P
(
e1
)
)
{
reg
=
REGNO
(
e1
)
;
asm_fprintf
(
out_file
,
"\t.setfp %r, %r\n"
,
HARD_FRAME_POINTER_REGNUM
,
reg
)
;
}
else
abort
(
)
;
}
else
if
(
REG_P
(
e1
)
&&
REGNO
(
e1
)
==
SP_REGNUM
)
{
asm_fprintf
(
out_file
,
"\t.movsp %r\n"
,
REGNO
(
e0
)
)
;
}
else
if
(
GET_CODE
(
e1
)
==
PLUS
&&
REG_P
(
XEXP
(
e1
,
0
)
)
&&
REGNO
(
XEXP
(
e1
,
0
)
)
==
SP_REGNUM
&&
CONST_INT_P
(
XEXP
(
e1
,
1
)
)
)
{
asm_fprintf
(
out_file
,
"\t.movsp %r, #%d\n"
,
REGNO
(
e0
)
,
(
int
)
INTVAL
(
XEXP
(
e1
,
1
)
)
)
;
}
else
abort
(
)
;
break
;
default
:
abort
(
)
;
}
}
</s>


<s> const LegalizerInfo * PPCSubtarget :: getLegalizerInfo ( ) const { return Legalizer . get ( ) ; } </s>

Expose LegalizerInfo so the clients can re-use .


<s> static void vr4130_align_insns ( void ) { struct mips_sim state ; rtx insn , subinsn , last , last2 , next ; bool aligned_p ; dfa_start ( ) ; last = 0 ; last2 = 0 ; aligned_p = true ; mips_sim_init ( & state , alloca ( state_size ( ) ) ) ; for ( insn = get_insns ( ) ; insn != 0 ; insn = next ) { unsigned int length ; next = NEXT_INSN ( insn ) ; vr4130_avoid_branch_rt_conflict ( insn ) ; if ( USEFUL_INSN_P ( insn ) ) FOR_EACH_SUBINSN ( subinsn , insn ) { mips_sim_wait_insn ( & state , subinsn ) ; if ( state . insns_left != state . issue_rate && ! CALL_P ( subinsn ) ) { if ( subinsn == SEQ_BEGIN ( insn ) && aligned_p ) { emit_insn_after ( gen_nop ( ) , last2 ) ; aligned_p = false ; } else if ( subinsn != SEQ_BEGIN ( insn ) && ! aligned_p ) { emit_insn_after ( gen_nop ( ) , last ) ; aligned_p = true ; } } mips_sim_issue_insn ( & state , subinsn ) ; } mips_sim_finish_insn ( & state , insn ) ; length = get_attr_length ( insn ) ; if ( length > 0 ) { if ( NONJUMP_INSN_P ( SEQ_BEGIN ( insn ) ) && ( recog_memoized ( insn ) < 0 || length >= 8 ) ) { next = emit_insn_after ( gen_align ( GEN_INT ( 3 ) ) , insn ) ; next = NEXT_INSN ( next ) ; mips_sim_next_cycle ( & state ) ; aligned_p = true ; } else if ( length & 4 ) aligned_p = ! aligned_p ; last2 = last ; last = insn ; } if ( LABEL_P ( insn ) && label_to_alignment ( insn ) >= 3 ) aligned_p = true ; } dfa_finish ( ) ; } </s>

Implement -mvr4130-align . Go through each basic block and simulate the processor pipeline . If we find that a pair of instructions could execute in parallel , and the first of those instruction is not 8-byte aligned , insert a nop to make it aligned .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> virtual bool isReg ( ) const LLVM_OVERRIDE { return Kind == KindReg ; } </s>


<s> bool isToken ( ) const { return Kind == k_Token ; } </s>


<s> ScheduleHazardRecognizer * PPCInstrInfo :: CreateTargetHazardRecognizer ( const TargetMachine * TM , const ScheduleDAG * DAG ) const { unsigned Directive = TM -> getSubtarget < PPCSubtarget > ( ) . getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_440 || Directive == PPC :: DIR_A2 || Directive == PPC :: DIR_E500mc || Directive == PPC :: DIR_E5500 ) { const InstrItineraryData * II = TM -> getInstrItineraryData ( ) ; return new ScoreboardHazardRecognizer ( II , DAG ) ; } return TargetInstrInfo :: CreateTargetHazardRecognizer ( TM , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .


<s> StringRef const TPCMCInstrInfo :: getName ( MCInstrInfo const & MCII , MCInst const & MCI ) { return MCII . getName ( MCI . getOpcode ( ) ) ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"AMDGPU Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static const char * rs6000_xcoff_visibility ( tree decl ) { static const char * const visibility_types [ ] = { "" , ",protected" , ",hidden" , ",internal" } ; enum symbol_visibility vis = DECL_VISIBILITY ( decl ) ; if ( TREE_CODE ( decl ) == FUNCTION_DECL && cgraph_node :: get ( decl ) && cgraph_node :: get ( decl ) -> instrumentation_clone && cgraph_node :: get ( decl ) -> instrumented_version ) vis = DECL_VISIBILITY ( cgraph_node :: get ( decl ) -> instrumented_version -> decl ) ; return visibility_types [ vis ] ; } </s>

Helper function to calculate visibility of a DECL and return the value as a const string .

powerpcspe "" ",protected" ",hidden" ",internal"


"Splitting double registers in function: "

"Register partitioning: (partition #0 is fixed)\n"

runOnMachineFunction - Emit the function body .


<s> static void frv_add_insn_to_packet ( rtx insn ) { struct frv_packet_group * packet_group ; packet_group = & frv_packet . groups [ frv_unit_groups [ frv_insn_unit ( insn ) ] ] ; packet_group -> insns [ packet_group -> num_insns ++ ] = insn ; frv_packet . insns [ frv_packet . num_insns ++ ] = insn ; frv_registers_update ( PATTERN ( insn ) ) ; } </s>

Add instruction INSN to the current packet .


<s> void R600SchedStrategy :: initialize ( ScheduleDAGMI * dag ) { DAG = dag ; TII = static_cast < const R600InstrInfo * > ( DAG -> TII ) ; TRI = static_cast < const R600RegisterInfo * > ( DAG -> TRI ) ; MRI = & DAG -> MRI ; CurInstKind = IDOther ; CurEmitted = 0 ; OccupedSlotsMask = 15 ; InstKindLimit [ IDAlu ] = TII -> getMaxAlusPerClause ( ) ; InstKindLimit [ IDOther ] = 32 ; const AMDGPUSubtarget & ST = DAG -> TM . getSubtarget < AMDGPUSubtarget > ( ) ; InstKindLimit [ IDFetch ] = ST . getTexVTXClauseSize ( ) ; AluInstCount = 0 ; FetchInstCount = 0 ; } </s>

Initialize the strategy after building the DAG for a new region .


<s>
bool
AArch64AdvSIMDScalar
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
bool
Changed
=
false
;
DEBUG
(
dbgs
(
)
<<
"***** AArch64AdvSIMDScalar *****\n"
)
;
if
(
skipFunction
(
*
mf
.
getFunction
(
)
)
)
return
false
;
MRI
=
&
mf
.
getRegInfo
(
)
;
TII
=
mf
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
for
(
MachineFunction
::
iterator
I
=
mf
.
begin
(
)
,
E
=
mf
.
end
(
)
;
I
!=
E
;
++
I
)
if
(
processMachineBasicBlock
(
&
*
I
)
)
Changed
=
true
;
return
Changed
;
}
</s>


<s>
const
char
*
avr_out_round
(
rtx_insn
*
insn
ATTRIBUTE_UNUSED
,
rtx
*
xop
,
int
*
plen
)
{
machine_mode
mode
=
GET_MODE
(
xop
[
0
]
)
;
machine_mode
imode
=
int_mode_for_mode
(
mode
)
;
int
fbit
=
(
int
)
GET_MODE_FBIT
(
mode
)
;
double_int
i_add
=
double_int_zero
.
set_bit
(
fbit
1
INTVAL
(
xop
[
2
]
)
)
;
wide_int
wi_add
=
wi
::
set_bit_in_zero
(
fbit
1
INTVAL
(
xop
[
2
]
)
,
GET_MODE_PRECISION
(
imode
)
)
;
int
len_add
=
0
,
*
plen_add
=
plen
&
len_add
:
;
int
len_and
=
0
,
*
plen_and
=
plen
&
len_and
:
;
rtx
xadd
=
const_fixed_from_double_int
(
i_add
,
mode
)
;
rtx
xpattern
,
xsrc
,
op
[
4
]
;
xsrc
=
SIGNED_FIXED_POINT_MODE_P
(
mode
)
gen_rtx_SS_PLUS
(
mode
,
xop
[
1
]
,
xadd
)
:
gen_rtx_US_PLUS
(
mode
,
xop
[
1
]
,
xadd
)
;
xpattern
=
gen_rtx_SET
(
xop
[
0
]
,
xsrc
)
;
op
[
0
]
=
xop
[
0
]
;
op
[
1
]
=
xop
[
1
]
;
op
[
2
]
=
xadd
;
avr_out_plus
(
xpattern
,
op
,
plen_add
,
,
false
)
;
avr_asm_len
(
"rjmp 1f"
CR_TAB
"0:"
,
,
plen_add
,
1
)
;
rtx
xreg
=
simplify_gen_subreg
(
imode
,
xop
[
0
]
,
mode
,
0
)
;
rtx
xmask
=
immed_wide_int_const
(
wi_add
wi_add
,
imode
)
;
xpattern
=
gen_rtx_SET
(
xreg
,
gen_rtx_AND
(
imode
,
xreg
,
xmask
)
)
;
op
[
0
]
=
xreg
;
op
[
1
]
=
xreg
;
op
[
2
]
=
xmask
;
op
[
3
]
=
gen_rtx_SCRATCH
(
QImode
)
;
avr_out_bitop
(
xpattern
,
op
,
plen_and
)
;
avr_asm_len
(
"1:"
,
,
plen
,
0
)
;
if
(
plen
)
*
plen
=
len_add
+
len_and
;
return
""
;
}
</s>

Output fixed-point rounding . XOP [ 0 ] = XOP [ 1 ] is the operand to round . XOP [ 2 ] is the rounding point , a CONST_INT . The function prints the instruction sequence if PLEN = NULL and computes the length in words of the sequence if PLEN ! = NULL . Most of this function deals with preparing operands for calls to ` avr_out_plus ' and ` avr_out_bitop ' .


<s> bool runOnModule ( Module & M ) override { return runLowerConstExpr ( M ) ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> static rtx aarch64_move_pointer ( rtx pointer , int amount ) { rtx next = plus_constant ( Pmode , XEXP ( pointer , 0 ) , amount ) ; return adjust_automodify_address ( pointer , GET_MODE ( pointer ) , next , amount ) ; } </s>

Return a new RTX holding the result of moving POINTER forward by AMOUNT bytes .


<s> unsigned AMDGPURegisterBankInfo :: copyCost ( const RegisterBank & Dst , const RegisterBank & Src , unsigned Size ) const { if ( Dst . getID ( ) == AMDGPU :: SGPRRegBankID && ( isVectorRegisterBank ( Src ) || Src . getID ( ) == AMDGPU :: VCCRegBankID ) ) { return std :: numeric_limits < unsigned > :: max ( ) ; } if ( Size == 1 && ( Dst . getID ( ) == AMDGPU :: SGPRRegBankID ) && ( isVectorRegisterBank ( Src ) || Src . getID ( ) == AMDGPU :: SGPRRegBankID || Src . getID ( ) == AMDGPU :: VCCRegBankID ) ) return std :: numeric_limits < unsigned > :: max ( ) ; if ( Dst . getID ( ) == AMDGPU :: AGPRRegBankID && Src . getID ( ) == AMDGPU :: AGPRRegBankID ) return 4 ; return RegisterBankInfo :: copyCost ( Dst , Src , Size ) ; } </s>

Get the cost of a copy from B to A , or put differently , get the cost of A = COPY B .

AMDGPU AMDGPU AMDGPU::SGPRRegBankID AMDGPU::VCCRegBankID 1 AMDGPU::SGPRRegBankID AMDGPU::SGPRRegBankID AMDGPU::VCCRegBankID AMDGPU::AGPRRegBankID AMDGPU::AGPRRegBankID 4


<s> bool MipsSubtarget :: enablePostRAScheduler ( ) const { return true ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s> MCSection * LanaiTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , Align & Alignment ) const { if ( isConstantInSmallSection ( DL , C ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: getSectionForConstant ( DL , Kind , C , Alignment ) ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> static bool iq2000_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { return ( ( int_size_in_bytes ( type ) > ( 2 * UNITS_PER_WORD ) ) || ( int_size_in_bytes ( type ) == - 1 ) ) ; } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


<s>
void
RISCVDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
SDLoc
DL
(
Node
)
;
DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
return
;
}
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
switch
(
Opcode
)
{
case
ISD
::
FrameIndex
:
{
SDValue
imm
=
CurDAG
->
getTargetConstant
(
0
,
DL
,
Subtarget
.
isRV64
(
)
MVT
::
i64
:
MVT
::
i32
)
;
int
FI
=
cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
getTargetLowering
(
)
->
getPointerTy
(
CurDAG
->
getDataLayout
(
)
)
)
;
unsigned
Opc
=
Subtarget
.
isRV64
(
)
RISCV
::
ADDI64
:
RISCV
::
ADDI
;
EVT
VT
=
Subtarget
.
isRV64
(
)
MVT
::
i64
:
MVT
::
i32
;
if
(
Node
->
hasOneUse
(
)
)
{
CurDAG
->
SelectNodeTo
(
Node
,
Opc
,
VT
,
TFI
,
imm
)
;
return
;
}
ReplaceNode
(
Node
,
CurDAG
->
getMachineNode
(
Opc
,
DL
,
VT
,
TFI
,
imm
)
)
;
return
;
}
}
SelectCode
(
Node
)
;
return
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s>
SDValue
VETargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
VAARG
:
return
LowerVAARG
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

VE
VE
"Should not custom lower this!"
ISD::BlockAddress
ISD::GlobalAddress
ISD::GlobalTLSAddress
ISD::VASTART
ISD::VAARG


<s> void ARMPassConfig :: addIRPasses ( ) { if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( 1 , false , false , true , true , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < ARMSubtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST . isThumb1Only ( ) ; } ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> bool WinEHStatePass :: doFinalization ( Module & M ) { assert ( TheModule == & M ) ; TheModule = nullptr ; EHLinkRegistrationTy = nullptr ; CXXEHRegistrationTy = nullptr ; SEHRegistrationTy = nullptr ; return false ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> PPCSubtarget :: PPCSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , bool is64Bit ) : PPCGenSubtargetInfo ( TT , CPU , FS ) , StackAlignment ( 16 ) , DarwinDirective ( PPC :: DIR_NONE ) , IsGigaProcessor ( false ) , Has64BitSupport ( false ) , Use64BitRegs ( false ) , IsPPC64 ( is64Bit ) , HasAltivec ( false ) , HasFSQRT ( false ) , HasSTFIWX ( false ) , IsBookE ( false ) , HasLazyResolverStubs ( false ) , IsJITCodeModel ( false ) , TargetTriple ( TT ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "generic" ; if ( CPUName == "generic" ) CPUName = GetCurrentPowerPCCPU ( ) ; ParseSubtargetFeatures ( CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( is64Bit ) { Has64BitSupport = true ; Use64BitRegs = true ; } if ( use64BitRegs ( ) && ! has64BitSupport ( ) ) Use64BitRegs = false ; if ( isDarwin ( ) ) HasLazyResolverStubs = true ; } </s>

This constructor initializes the data members to match that of the specified triple .

PowerPC PPC PPC PPC 16 PPC::DIR_NONE PPC "generic" "generic"


<s>
const
char
*
pa_output_block_clear
(
rtx
*
operands
,
int
size_is_constant
ATTRIBUTE_UNUSED
)
{
int
align
=
INTVAL
(
operands
[
3
]
)
;
unsigned
long
n_bytes
=
INTVAL
(
operands
[
2
]
)
;
if
(
align
>
(
TARGET_64BIT
8
:
4
)
)
align
=
(
TARGET_64BIT
8
:
4
)
;
switch
(
align
)
{
case
8
:
operands
[
2
]
=
GEN_INT
(
n_bytes
16
)
;
output_asm_insn
(
"ldi %2,%1"
,
operands
)
;
output_asm_insn
(
"std,ma %%r0,8(%0)"
,
operands
)
;
output_asm_insn
(
"addib,>= -16,%1,.-4"
,
operands
)
;
output_asm_insn
(
"std,ma %%r0,8(%0)"
,
operands
)
;
if
(
n_bytes
%
16
!=
0
)
{
operands
[
2
]
=
GEN_INT
(
n_bytes
%
8
)
;
if
(
n_bytes
%
16
>=
8
)
output_asm_insn
(
"std,ma %%r0,8(%0)"
,
operands
)
;
if
(
n_bytes
%
8
!=
0
)
output_asm_insn
(
"stdby,e %%r0,%2(%0)"
,
operands
)
;
}
return
""
;
case
4
:
operands
[
2
]
=
GEN_INT
(
n_bytes
8
)
;
output_asm_insn
(
"ldi %2,%1"
,
operands
)
;
output_asm_insn
(
"{stws|stw},ma %%r0,4(%0)"
,
operands
)
;
output_asm_insn
(
"addib,>= -8,%1,.-4"
,
operands
)
;
output_asm_insn
(
"{stws|stw},ma %%r0,4(%0)"
,
operands
)
;
if
(
n_bytes
%
8
!=
0
)
{
operands
[
2
]
=
GEN_INT
(
n_bytes
%
4
)
;
if
(
n_bytes
%
8
>=
4
)
output_asm_insn
(
"{stws|stw},ma %%r0,4(%0)"
,
operands
)
;
if
(
n_bytes
%
4
!=
0
)
output_asm_insn
(
"{stbys|stby},e %%r0,%2(%0)"
,
operands
)
;
}
return
""
;
case
2
:
operands
[
2
]
=
GEN_INT
(
n_bytes
4
)
;
output_asm_insn
(
"ldi %2,%1"
,
operands
)
;
output_asm_insn
(
"{sths|sth},ma %%r0,2(%0)"
,
operands
)
;
output_asm_insn
(
"addib,>= -4,%1,.-4"
,
operands
)
;
output_asm_insn
(
"{sths|sth},ma %%r0,2(%0)"
,
operands
)
;
if
(
n_bytes
%
4
!=
0
)
{
if
(
n_bytes
%
4
>=
2
)
output_asm_insn
(
"{sths|sth},ma %%r0,2(%0)"
,
operands
)
;
if
(
n_bytes
%
2
!=
0
)
output_asm_insn
(
"stb %%r0,0(%0)"
,
operands
)
;
}
return
""
;
case
1
:
operands
[
2
]
=
GEN_INT
(
n_bytes
2
)
;
output_asm_insn
(
"ldi %2,%1"
,
operands
)
;
output_asm_insn
(
"{stbs|stb},ma %%r0,1(%0)"
,
operands
)
;
output_asm_insn
(
"addib,>= -2,%1,.-4"
,
operands
)
;
output_asm_insn
(
"{stbs|stb},ma %%r0,1(%0)"
,
operands
)
;
if
(
n_bytes
%
2
!=
0
)
output_asm_insn
(
"stb %%r0,0(%0)"
,
operands
)
;
return
""
;
default
:
gcc_unreachable
(
)
;
}
}
</s>

Emit code to perform a block clear . OPERANDS [ 0 ] is the destination pointer as a REG , clobbered . OPERANDS [ 1 ] is a register for temporary storage . OPERANDS [ 2 ] is the size as a CONST_INT OPERANDS [ 3 ] is the alignment safe to use , as a CONST_INT .


<s> const SparcSubtarget * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static void or1k_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int nreg = CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ; gcc_assert ( nreg <= 2 ) ; if ( named ) * cum += nreg ; } </s>

Worker for TARGET_FUNCTION_ARG_ADVANCE . Update the cumulative args descriptor CUM_V to advance past the next function argument . Note , this is not called for arguments passed on the stack .


<s> void split_double_mode ( machine_mode mode , rtx operands [ ] , int num , rtx lo_half [ ] , rtx hi_half [ ] ) { machine_mode half_mode ; unsigned int byte ; rtx mem_op = NULL_RTX ; int mem_num = 0 ; switch ( mode ) { case E_TImode : half_mode = DImode ; break ; case E_DImode : half_mode = SImode ; break ; case E_P2HImode : half_mode = HImode ; break ; case E_P2QImode : half_mode = QImode ; break ; default : gcc_unreachable ( ) ; } byte = GET_MODE_SIZE ( half_mode ) ; while ( num -- ) { rtx op = operands [ num ] ; if ( MEM_P ( op ) ) { if ( mem_op && rtx_equal_p ( op , mem_op ) ) { lo_half [ num ] = lo_half [ mem_num ] ; hi_half [ num ] = hi_half [ mem_num ] ; } else { mem_op = op ; mem_num = num ; lo_half [ num ] = adjust_address ( op , half_mode , 0 ) ; hi_half [ num ] = adjust_address ( op , half_mode , byte ) ; } } else { lo_half [ num ] = simplify_gen_subreg ( half_mode , op , GET_MODE ( op ) == VOIDmode ? mode : GET_MODE ( op ) , 0 ) ; rtx tmp = simplify_gen_subreg ( half_mode , op , GET_MODE ( op ) == VOIDmode ? mode : GET_MODE ( op ) , byte ) ; hi_half [ num ] = tmp ? tmp : gen_reg_rtx ( half_mode ) ; } } } </s>

Split one or more double-mode RTL references into pairs of half-mode references . The RTL can be REG , offsettable MEM , integer constant , or CONST_DOUBLE . `` operands '' is a pointer to an array of double-mode RTLs to split and `` num '' is its length . lo_half and hi_half are output arrays that parallel `` operands '' .


<s>
const
MCExpr
*
SystemZMCInstLower
::
getExpr
(
const
MachineOperand
&
MO
,
MCSymbolRefExpr
::
VariantKind
Kind
)
const
{
const
MCSymbol
*
Symbol
;
bool
HasOffset
=
true
;
switch
(
MO
.
getType
(
)
)
{
case
MachineOperand
::
MO_MachineBasicBlock
:
Symbol
=
MO
.
getMBB
(
)
->
getSymbol
(
)
;
HasOffset
=
false
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
Symbol
=
Mang
->
getSymbol
(
MO
.
getGlobal
(
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
Symbol
=
AsmPrinter
.
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
Symbol
=
AsmPrinter
.
GetJTISymbol
(
MO
.
getIndex
(
)
)
;
HasOffset
=
false
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
Symbol
=
AsmPrinter
.
GetCPISymbol
(
MO
.
getIndex
(
)
)
;
break
;
case
MachineOperand
::
MO_BlockAddress
:
Symbol
=
AsmPrinter
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
;
break
;
default
:
llvm_unreachable
(
"unknown operand type"
)
;
}
const
MCExpr
*
Expr
=
MCSymbolRefExpr
::
Create
(
Symbol
,
Kind
,
Ctx
)
;
if
(
HasOffset
)
if
(
int64_t
Offset
=
MO
.
getOffset
(
)
)
{
const
MCExpr
*
OffsetExpr
=
MCConstantExpr
::
Create
(
Offset
,
Ctx
)
;
Expr
=
MCBinaryExpr
::
CreateAdd
(
Expr
,
OffsetExpr
,
Ctx
)
;
}
return
Expr
;
}
</s>

Implementation of the SCEVPredicate interface .


<s>
SDValue
LoongArchTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
analyzeOutputArgs
(
CCInfo
,
Outs
,
CC_LoongArch
)
;
SDValue
Glue
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
<
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Glue
)
;
Glue
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Glue
.
getNode
(
)
)
RetOps
.
push_back
(
Glue
)
;
return
DAG
.
getNode
(
LoongArchISD
::
RET
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> int aarch64_fpconst_pow_of_2 ( rtx x ) { const REAL_VALUE_TYPE * r ; if ( ! CONST_DOUBLE_P ( x ) ) return - 1 ; r = CONST_DOUBLE_REAL_VALUE ( x ) ; if ( REAL_VALUE_NEGATIVE ( * r ) || REAL_VALUE_ISNAN ( * r ) || REAL_VALUE_ISINF ( * r ) || ! real_isinteger ( r , DFmode ) ) return - 1 ; return exact_log2 ( real_to_integer ( r ) ) ; } </s>

If X is a positive CONST_DOUBLE with a value that is a power of 2 return the log2 of that value . Otherwise return -1 .


<s> bool PatmosSPBundling :: runOnMachineFunction ( MachineFunction & MF ) { PSPI = & getAnalysis < PatmosSinglePathInfo > ( ) ; PostDom = & getAnalysis < MachinePostDominatorTree > ( ) ; if ( PSPI -> isConverting ( MF ) && STC . enableBundling ( TM . getOptLevel ( ) ) ) { SPBlocks += MF . size ( ) ; doBundlingFunction ( PSPI -> getRootScope ( ) ) ; } return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool avr_emit_cpymemhi ( rtx * xop ) { HOST_WIDE_INT count ; machine_mode loop_mode ; addr_space_t as = MEM_ADDR_SPACE ( xop [ 1 ] ) ; rtx loop_reg , addr1 , a_src , a_dest , insn , xas ; rtx a_hi8 = NULL_RTX ; if ( avr_mem_flash_p ( xop [ 0 ] ) ) return false ; if ( ! CONST_INT_P ( xop [ 2 ] ) ) return false ; count = INTVAL ( xop [ 2 ] ) ; if ( count <= 0 ) return false ; a_src = XEXP ( xop [ 1 ] , 0 ) ; a_dest = XEXP ( xop [ 0 ] , 0 ) ; if ( PSImode == GET_MODE ( a_src ) ) { gcc_assert ( as == ADDR_SPACE_MEMX ) ; loop_mode = ( count < 0x100 ) ? QImode : HImode ; loop_reg = gen_rtx_REG ( loop_mode , 24 ) ; emit_move_insn ( loop_reg , gen_int_mode ( count , loop_mode ) ) ; addr1 = simplify_gen_subreg ( HImode , a_src , PSImode , 0 ) ; a_hi8 = simplify_gen_subreg ( QImode , a_src , PSImode , 2 ) ; } else { int segment = avr_addrspace [ as ] . segment ; if ( segment && avr_n_flash > 1 ) { a_hi8 = GEN_INT ( segment ) ; emit_move_insn ( rampz_rtx , a_hi8 = copy_to_mode_reg ( QImode , a_hi8 ) ) ; } else if ( ! ADDR_SPACE_GENERIC_P ( as ) ) { as = ADDR_SPACE_FLASH ; } addr1 = a_src ; loop_mode = ( count <= 0x100 ) ? QImode : HImode ; loop_reg = copy_to_mode_reg ( loop_mode , gen_int_mode ( count , loop_mode ) ) ; } xas = GEN_INT ( as ) ; emit_move_insn ( lpm_addr_reg_rtx , addr1 ) ; emit_move_insn ( gen_rtx_REG ( HImode , REG_X ) , a_dest ) ; gcc_assert ( TMP_REGNO == LPM_REGNO ) ; if ( as != ADDR_SPACE_MEMX ) { rtx ( * fun ) ( rtx , rtx , rtx ) = QImode == loop_mode ? gen_cpymem_qi : gen_cpymem_hi ; insn = fun ( xas , loop_reg , loop_reg ) ; } else { rtx ( * fun ) ( rtx , rtx ) = QImode == loop_mode ? gen_cpymemx_qi : gen_cpymemx_hi ; emit_move_insn ( gen_rtx_REG ( QImode , 23 ) , a_hi8 ) ; insn = fun ( xas , GEN_INT ( avr_addr . rampz ) ) ; } set_mem_addr_space ( SET_SRC ( XVECEXP ( insn , 0 , 0 ) ) , as ) ; emit_insn ( insn ) ; return true ; } </s>

Worker function for cpymemhi expander . XOP [ 0 ] Destination as MEM : BLK XOP [ 1 ] Source `` `` XOP [ 2 ] # Bytes to copy Return TRUE if the expansion is accomplished . Return FALSE if the operand compination is not supported .


<s> unsigned R600InstrInfo :: calculateIndirectAddress ( unsigned RegIndex , unsigned Channel ) const { assert ( Channel == 0 ) ; return RegIndex ; } </s>

Calculate the `` Indirect Address '' for the given RegIndex and Channel .


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> bool use_mask_predication_p ( ) const override { return false ; } </s>

We choose to return true by default since most of the intrinsics use mask predication .


<s>
bool
AMDGPUAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
switch
(
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MatchingInlineAsm
)
)
{
default
:
break
;
case
Match_Success
:
Inst
.
setLoc
(
IDLoc
)
;
Out
.
EmitInstruction
(
Inst
,
STI
)
;
return
false
;
case
Match_MissingFeature
:
return
Error
(
IDLoc
,
"instruction not supported on this GPU"
)
;
case
Match_MnemonicFail
:
return
Error
(
IDLoc
,
"unrecognized instruction mnemonic"
)
;
case
Match_InvalidOperand
:
{
SMLoc
ErrorLoc
=
IDLoc
;
if
(
ErrorInfo
!=
~
0ULL
)
{
if
(
ErrorInfo
>=
Operands
.
size
(
)
)
{
if
(
isForcedVOP3
(
)
)
{
AMDGPUOperand
&
LastOp
=
(
(
AMDGPUOperand
&
)
*
Operands
[
Operands
.
size
(
)
1
]
)
;
if
(
LastOp
.
isRegKind
(
)
||
(
LastOp
.
isImm
(
)
&&
LastOp
.
getImmTy
(
)
!=
AMDGPUOperand
::
ImmTyNone
)
)
{
SMLoc
S
=
Parser
.
getTok
(
)
.
getLoc
(
)
;
Operands
.
push_back
(
AMDGPUOperand
::
CreateImm
(
0
,
S
,
AMDGPUOperand
::
ImmTyClamp
)
)
;
Operands
.
push_back
(
AMDGPUOperand
::
CreateImm
(
0
,
S
,
AMDGPUOperand
::
ImmTyOMod
)
)
;
bool
Res
=
MatchAndEmitInstruction
(
IDLoc
,
Opcode
,
Operands
,
Out
,
ErrorInfo
,
MatchingInlineAsm
)
;
if
(
!
Res
)
return
Res
;
}
}
return
Error
(
IDLoc
,
"too few operands for instruction"
)
;
}
ErrorLoc
=
(
(
AMDGPUOperand
&
)
*
Operands
[
ErrorInfo
]
)
.
getStartLoc
(
)
;
if
(
ErrorLoc
==
SMLoc
(
)
)
ErrorLoc
=
IDLoc
;
}
return
Error
(
ErrorLoc
,
"invalid operand for instruction"
)
;
}
}
llvm_unreachable
(
"Implement any new match types added!"
)
;
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .

AMDGPU
AMDGPU
"instruction not supported on this GPU"
"unrecognized instruction mnemonic"
0ULL
AMDGPU
AMDGPU
1
AMDGPU
AMDGPU
0
AMDGPU
AMDGPU
0
AMDGPU
"too few operands for instruction"
AMDGPU
"invalid operand for instruction"
"Implement any new match types added!"


<s> bool ARMPassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge && ! getARMSubtarget ( ) . isTargetNaCl ( ) ) addPass ( createGlobalMergePass ( TM -> getTargetLowering ( ) ) ) ; return false ; } </s>


"Callee saved registers requested for unknown architecture "


<s> const J2RegisterInfo * getRegisterInfo ( ) const override { return & RegisterInfo ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
virtual
const
char
*
getPassName
(
)
const
LLVM_OVERRIDE
{
return
"ARM Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool ix86_expand_mask_vec_cmp ( rtx dest , enum rtx_code code , rtx cmp_op0 , rtx cmp_op1 ) { machine_mode mask_mode = GET_MODE ( dest ) ; machine_mode cmp_mode = GET_MODE ( cmp_op0 ) ; rtx imm = GEN_INT ( ix86_cmp_code_to_pcmp_immediate ( code , cmp_mode ) ) ; int unspec_code ; rtx unspec ; switch ( code ) { case LEU : case GTU : case GEU : case LTU : unspec_code = UNSPEC_UNSIGNED_PCMP ; break ; default : unspec_code = UNSPEC_PCMP ; } unspec = gen_rtx_UNSPEC ( mask_mode , gen_rtvec ( 3 , cmp_op0 , cmp_op1 , imm ) , unspec_code ) ; emit_insn ( gen_rtx_SET ( dest , unspec ) ) ; return true ; } </s>


"Don't know yet how to store a FSR16 to stack slot"

"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s>
void
ARMAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
,
MCContext
&
Ctx
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
IsPCRel
,
Ctx
,
IsLittleEndian
,
true
)
;
if
(
!
Value
)
return
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
unsigned
FullSizeBytes
;
if
(
!
IsLittleEndian
)
{
FullSizeBytes
=
getFixupKindContainerSizeBytes
(
Fixup
.
getKind
(
)
)
;
assert
(
(
Offset
+
FullSizeBytes
)
<=
DataSize
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FullSizeBytes
&&
"Invalid fixup size!"
)
;
}
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
IsLittleEndian
i
:
(
FullSizeBytes
1
i
)
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


" is allocatable: function has no frame pointer"

Return the register ID of the name passed in .


<s> unsigned TVMRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return TVM :: SP ; } </s>


<s> static section * rs6000_elf_select_rtx_section ( machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ) { if ( ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( x , mode ) ) return toc_section ; else return default_elf_select_rtx_section ( mode , x , align ) ; } </s>

A C statement or statements to switch to the appropriate section for output of RTX in mode MODE . You can assume that RTX is some kind of constant in RTL . The argument MODE is redundant except in the case of a ` const_int ' rtx . Select the section by calling ` text_section ' or one of the alternatives for other sections . Do not define this macro if you put all constants in the read-only data section .


<s> inline void classify_registers ( const_tree , int bitpos , bool fp , classify_data_t * data ) { if ( fp ) { data -> fp_regs = true ; if ( bitpos < BITS_PER_WORD ) data -> fp_regs_in_first_word = true ; } } </s>

A subroutine of function_arg_slotno . Classify the field .


<s> static void ix86_emit_restore_sse_regs_using_mov ( HOST_WIDE_INT cfa_offset , bool maybe_eh_return ) { unsigned int regno ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( SSE_REGNO_P ( regno ) && ix86_save_reg ( regno , maybe_eh_return , true ) ) { rtx reg = gen_rtx_REG ( V4SFmode , regno ) ; rtx mem ; unsigned int align = GET_MODE_ALIGNMENT ( V4SFmode ) ; mem = choose_baseaddr ( cfa_offset , & align ) ; mem = gen_rtx_MEM ( V4SFmode , mem ) ; align = MIN ( GET_MODE_ALIGNMENT ( V4SFmode ) , align ) ; gcc_assert ( ! ( cfa_offset & ( align / BITS_PER_UNIT - 1 ) ) ) ; set_mem_align ( mem , align ) ; emit_insn ( gen_rtx_SET ( reg , mem ) ) ; ix86_add_cfa_restore_note ( NULL , reg , cfa_offset ) ; cfa_offset -= GET_MODE_SIZE ( V4SFmode ) ; } } </s>

Emit code to restore saved registers using MOV insns . First register is restored from CFA - CFA_OFFSET .


<s> void alpha_split_compare_and_swap ( rtx operands [ ] ) { rtx cond , retval , mem , oldval , newval ; bool is_weak ; enum memmodel mod_s , mod_f ; machine_mode mode ; rtx label1 , label2 , x ; cond = operands [ 0 ] ; retval = operands [ 1 ] ; mem = operands [ 2 ] ; oldval = operands [ 3 ] ; newval = operands [ 4 ] ; is_weak = ( operands [ 5 ] != const0_rtx ) ; mod_s = ( enum memmodel ) INTVAL ( operands [ 6 ] ) ; mod_f = ( enum memmodel ) INTVAL ( operands [ 7 ] ) ; mode = GET_MODE ( mem ) ; alpha_pre_atomic_barrier ( mod_s ) ; label1 = NULL_RTX ; if ( ! is_weak ) { label1 = gen_rtx_LABEL_REF ( DImode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label1 , 0 ) ) ; } label2 = gen_rtx_LABEL_REF ( DImode , gen_label_rtx ( ) ) ; emit_load_locked ( mode , retval , mem ) ; x = gen_lowpart ( DImode , retval ) ; if ( oldval == const0_rtx ) { emit_move_insn ( cond , const0_rtx ) ; x = gen_rtx_NE ( DImode , x , const0_rtx ) ; } else { x = gen_rtx_EQ ( DImode , x , oldval ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cond , x ) ) ; x = gen_rtx_EQ ( DImode , cond , const0_rtx ) ; } emit_unlikely_jump ( x , label2 ) ; emit_move_insn ( cond , newval ) ; emit_store_conditional ( mode , cond , mem , gen_lowpart ( mode , cond ) ) ; if ( ! is_weak ) { x = gen_rtx_EQ ( DImode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label1 ) ; } if ( mod_f != MEMMODEL_RELAXED ) emit_label ( XEXP ( label2 , 0 ) ) ; alpha_post_atomic_barrier ( mod_s ) ; if ( mod_f == MEMMODEL_RELAXED ) emit_label ( XEXP ( label2 , 0 ) ) ; } </s>


<s> static unsigned int riscv_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( FP_REG_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + UNITS_PER_FP_REG - 1 ) / UNITS_PER_FP_REG ; return ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } </s>


<s>
bool
SystemZAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
;
FeatureBitset
MissingFeatures
;
MatchResult
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MissingFeatures
,
MatchingInlineAsm
)
;
switch
(
MatchResult
)
{
case
Match_Success
:
Inst
.
setLoc
(
IDLoc
)
;
Out
.
EmitInstruction
(
Inst
,
getSTI
(
)
)
;
return
false
;
case
Match_MissingFeature
:
{
assert
(
MissingFeatures
.
any
(
)
&&
"Unknown missing feature!"
)
;
std
::
string
Msg
=
"instruction requires:"
;
for
(
unsigned
I
=
0
,
E
=
MissingFeatures
.
size
(
)
;
I
!=
E
;
++
I
)
{
if
(
MissingFeatures
[
I
]
)
{
Msg
+=
" "
;
Msg
+=
getSubtargetFeatureName
(
I
)
;
}
}
return
Error
(
IDLoc
,
Msg
)
;
}
case
Match_InvalidOperand
:
{
SMLoc
ErrorLoc
=
IDLoc
;
if
(
ErrorInfo
!=
~
0ULL
)
{
if
(
ErrorInfo
>=
Operands
.
size
(
)
)
return
Error
(
IDLoc
,
"too few operands for instruction"
)
;
ErrorLoc
=
(
(
SystemZOperand
&
)
*
Operands
[
ErrorInfo
]
)
.
getStartLoc
(
)
;
if
(
ErrorLoc
==
SMLoc
(
)
)
ErrorLoc
=
IDLoc
;
}
return
Error
(
ErrorLoc
,
"invalid operand for instruction"
)
;
}
case
Match_MnemonicFail
:
{
FeatureBitset
FBS
=
ComputeAvailableFeatures
(
getSTI
(
)
.
getFeatureBits
(
)
)
;
std
::
string
Suggestion
=
SystemZMnemonicSpellCheck
(
(
(
SystemZOperand
&
)
*
Operands
[
0
]
)
.
getToken
(
)
,
FBS
)
;
return
Error
(
IDLoc
,
"invalid instruction"
+
Suggestion
,
(
(
SystemZOperand
&
)
*
Operands
[
0
]
)
.
getLocRange
(
)
)
;
}
}
llvm_unreachable
(
"Unexpected match type"
)
;
}
</s>

SystemZ
SystemZ
"Unknown missing feature!"
"instruction requires:"
0
" "
0ULL
"too few operands for instruction"
SystemZ
"invalid operand for instruction"
SystemZ
SystemZ
0
"invalid instruction"
SystemZ
0
"Unexpected match type"


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
ATOMIC_LOAD_ADD
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMADD64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_AND
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMAND64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_NAND
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMNAND64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_OR
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMOR64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_SUB
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMSUB64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_XOR
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMXOR64_DAG
)
;
return
;
case
ISD
::
ATOMIC_SWAP
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMSWAP64_DAG
)
;
return
;
case
ISD
::
ATOMIC_CMP_SWAP
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMCMPXCHG64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_MIN
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMMIN64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_UMIN
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMUMIN64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_MAX
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMMAX64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_UMAX
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMUMAX64_DAG
)
;
return
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> StringRef X86TargetLowering :: getStackProbeSymbolName ( MachineFunction & MF ) const { if ( MF . getFunction ( ) -> hasFnAttribute ( "probe-stack" ) ) return MF . getFunction ( ) -> getFnAttribute ( "probe-stack" ) . getValueAsString ( ) ; if ( ! Subtarget . isOSWindows ( ) || Subtarget . isTargetMachO ( ) ) return "" ; if ( Subtarget . is64Bit ( ) ) return Subtarget . isTargetCygMing ( ) ? "___chkstk_ms" : "__chkstk" ; return Subtarget . isTargetCygMing ( ) ? "_alloca" : "_chkstk" ; } </s>

Returns the name of the symbol used to emit stack probes or the empty string if not applicable .


<s> AArch64Subtarget :: AArch64Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasFPARMv8 ( false ) , HasNEON ( false ) , HasCrypto ( false ) , HasCRC ( false ) , HasZeroCycleRegMove ( false ) , HasZeroCycleZeroing ( false ) , IsLittle ( LittleEndian ) , CPUString ( CPU ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS ) ) , TSInfo ( TM . getDataLayout ( ) ) , TLInfo ( TM , * this ) { } </s>

This constructor initializes the data members to match that of the specified triple .


<s> static void split_alu_insn ( rtx_insn * insn , rtx * lhs , rtx * rhs1 , rtx * rhs2 ) { rtx pat = PATTERN ( insn ) ; gcc_assert ( GET_CODE ( pat ) == SET ) ; * lhs = SET_DEST ( pat ) ; * rhs1 = XEXP ( SET_SRC ( pat ) , 0 ) ; if ( GET_RTX_CLASS ( GET_CODE ( SET_SRC ( pat ) ) ) != RTX_UNARY ) * rhs2 = XEXP ( SET_SRC ( pat ) , 1 ) ; return ; } </s>

Splits out the operands of an ALU insn , places them in * LHS , * RHS1 , * RHS2 .


<s> bool CSKYAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { MCP = MF . getConstantPool ( ) ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MCSubtargetInfo & NewSTI = OutStreamer -> getContext ( ) . getSubtargetCopy ( * TM . getMCSubtargetInfo ( ) ) ; NewSTI . setFeatureBits ( MF . getSubtarget ( ) . getFeatureBits ( ) ) ; Subtarget = & NewSTI ; return AsmPrinter :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s>
void
output_ascii
(
FILE
*
file
,
const
char
*
p
,
int
size
)
{
int
i
;
fprintf
(
file
,
"\t.byte "
)
;
for
(
i
=
0
;
i
<
size
;
i
++
)
{
register
int
c
=
p
[
i
]
;
if
(
c
<
0
)
c
+=
256
;
fprintf
(
file
,
"%#o"
,
c
)
;
if
(
i
<
size
1
)
putc
(
','
,
file
)
;
}
putc
(
'\n'
,
file
)
;
}
</s>

Output an assembler pseudo-op to write an ASCII string of N characters starting at P to FILE . On the RS/6000 , we have to do this using the .byte operation and write out special characters outside the quoted string . Also , the assembler is broken ; very long strings are truncated , so we must artificially break them up early .


<s> void avr_init_cumulative_args ( CUMULATIVE_ARGS * cum , tree fntype , rtx libname , tree fndecl ATTRIBUTE_UNUSED ) { cum -> nregs = AVR_TINY ? 6 : 18 ; cum -> regno = FIRST_CUM_REG ; if ( ! libname && stdarg_p ( fntype ) ) cum -> nregs = 0 ; cfun -> machine -> sibcall_fails = 0 ; } </s>

Initializing the variable cum for the state at the beginning of the argument list .


<s> void reset ( ) { Inst2Replace = nullptr ; BackedgeInst = nullptr ; DepChains . clear ( ) ; Iterations = - 1 ; } </s>

Reset an existing scalar value for Def and a given Instance .


"\n********** Finished Patmos Delay Slot Filler **********\n"


<s> bool X86TTIImpl :: canMacroFuseCmp ( ) { return ST -> hasMacroFusion ( ) ; } </s>

Return true if the target can fuse a compare and branch .


<s> uint8_t get_ratio ( ) const { return m_ratio ; } </s>


<s> virtual bool isDivergentRegClass ( const TargetRegisterClass * RC ) const override { return ! isSGPRClass ( RC ) ; } </s>

Returns true if the register class is considered divergent .


<s> static void extract_devices_dir_from_collect_gcc ( char * * devices_loc ) { char * t_devices_loc = * devices_loc ; t_devices_loc = msp430_dirname ( msp430_dirname ( t_devices_loc ) ) ; t_devices_loc = concat ( t_devices_loc , rest_of_devices_path , NULL ) ; * devices_loc = t_devices_loc ; } </s>


"Too many temporary registers allocated\n"

Return a register which will be loaded with a value if an IF block is converted to conditional execution . This is used to rewrite instructions that use constants to ones that just use registers .


<s>
bool
SNESAsmParser
::
MatchAndEmitInstruction
(
SMLoc
Loc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MatchingInlineAsm
)
;
switch
(
MatchResult
)
{
case
Match_Success
:
return
emit
(
Inst
,
Loc
,
Out
)
;
case
Match_MissingFeature
:
return
missingFeature
(
Loc
,
ErrorInfo
)
;
case
Match_InvalidOperand
:
return
invalidOperand
(
Loc
,
Operands
,
ErrorInfo
)
;
case
Match_MnemonicFail
:
return
Error
(
Loc
,
"invalid instruction"
)
;
default
:
return
true
;
}
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s>
RISCVSubtarget
&
RISCVSubtarget
::
initializeSubtargetDependencies
(
const
Triple
&
TT
,
StringRef
CPU
,
StringRef
TuneCPU
,
StringRef
FS
,
StringRef
ABIName
)
{
bool
Is64Bit
=
TT
.
isArch64Bit
(
)
;
if
(
CPU
.
empty
(
)
)
CPU
=
Is64Bit
"generic-rv64"
:
"generic-rv32"
;
if
(
CPU
==
"generic"
)
report_fatal_error
(
Twine
(
"CPU 'generic' is not supported. Use "
)
+
(
Is64Bit
"generic-rv64"
:
"generic-rv32"
)
)
;
if
(
TuneCPU
.
empty
(
)
)
TuneCPU
=
CPU
;
ParseSubtargetFeatures
(
CPU
,
TuneCPU
,
FS
)
;
if
(
Is64Bit
)
{
XLenVT
=
MVT
::
i64
;
XLen
=
64
;
}
TargetABI
=
RISCVABI
::
computeTargetABI
(
TT
,
getFeatureBits
(
)
,
ABIName
)
;
RISCVFeatures
::
validate
(
TT
,
getFeatureBits
(
)
)
;
return
*
this
;
}
</s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


Clear caller saved registers not used to pass return values and leaked condition flags before exiting a cmse_nonsecure_entry function .


<s>
const
MCPhysReg
*
Z80RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
switch
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
CSR_Z80_C_SaveList
;
case
CallingConv
::
PreserveAll
:
return
CSR_Z80_AllRegs_SaveList
;
}
}
</s>


<s> bool arm_coproc_builtin_available ( enum unspecv builtin ) { if ( TARGET_THUMB1 ) return false ; switch ( builtin ) { case VUNSPEC_CDP : case VUNSPEC_LDC : case VUNSPEC_LDCL : case VUNSPEC_STC : case VUNSPEC_STCL : case VUNSPEC_MCR : case VUNSPEC_MRC : if ( arm_arch4 ) return true ; break ; case VUNSPEC_CDP2 : case VUNSPEC_LDC2 : case VUNSPEC_LDC2L : case VUNSPEC_STC2 : case VUNSPEC_STC2L : case VUNSPEC_MCR2 : case VUNSPEC_MRC2 : if ( arm_arch5t ) return true ; break ; case VUNSPEC_MCRR : case VUNSPEC_MRRC : if ( arm_arch6 || arm_arch5te ) return true ; break ; case VUNSPEC_MCRR2 : case VUNSPEC_MRRC2 : if ( arm_arch6 ) return true ; break ; default : gcc_unreachable ( ) ; } return false ; } </s>

This function checks for the availability of the coprocessor builtin passed in BUILTIN for the current target . Returns true if it is available and false otherwise . If a BUILTIN is passed for which this function has not been implemented it will cause an exception .


<s> static bool csky_legitimate_address_p ( machine_mode mode , rtx addr , bool strict_p ) { enum rtx_code code = GET_CODE ( addr ) ; if ( reload_completed && ( ( code == LABEL_REF ) || ( code == CONST && GET_CODE ( XEXP ( addr , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( addr , 0 ) , 1 ) ) ) ) ) return 1 ; if ( is_csky_address_register_rtx_p ( addr , strict_p ) ) return 1 ; else if ( GET_CODE ( addr ) == LABEL_REF ) return 1 ; if ( code == PLUS ) { rtx xop0 = XEXP ( addr , 0 ) ; rtx xop1 = XEXP ( addr , 1 ) ; return ( ( is_csky_address_register_rtx_p ( xop0 , strict_p ) && csky_legitimate_index_p ( mode , xop1 , strict_p ) ) || ( is_csky_address_register_rtx_p ( xop1 , strict_p ) && csky_legitimate_index_p ( mode , xop0 , strict_p ) ) ) ; } return 0 ; } </s>

Implement TARGET_LEGITIMATE_ADDRESS_P . Recognizes RTL expressions that are valid memory addresses for an instruction . The MODE argument is the machine mode for the MEM expression that wants to use this address . It only recognizes address in canonical form . LEGITIMIZE_ADDRESS should convert common non-canonical forms to canonical form so that they will be recognized .


<s> bool AMDGPUPassConfig :: addPreEmitPass ( ) { const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) { addPass ( createAMDGPUCFGPreparationPass ( * TM ) ) ; addPass ( createAMDGPUCFGStructurizerPass ( * TM ) ) ; addPass ( createR600ExpandSpecialInstrsPass ( * TM ) ) ; addPass ( & FinalizeMachineBundlesID ) ; addPass ( createR600Packetizer ( * TM ) ) ; addPass ( createR600ControlFlowFinalizer ( * TM ) ) ; } else { addPass ( createSILowerControlFlowPass ( * TM ) ) ; } return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool FPGATTIImpl :: shouldBuildLookupTables ( ) { return false ; } </s>

Return true if switches should be turned into lookup tables for the target .


<s> uint64_t flags ( ) const { return llvm :: ELF :: EF_ARM_EABI_VER5 ; } </s>

Get the flags for this GlobalValue ( see struct GVFlags ) .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"A57 FP Anti-dependency breaker"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"Unknown fence ordering in emitLeadingFence"


<s> static void s390_reorg ( void ) { bool pool_overflow = false ; int hw_before , hw_after ; if ( s390_tune == PROCESSOR_2964_Z13 ) s390_adjust_loops ( ) ; split_all_insns_noflow ( ) ; for ( ; ; ) { struct constant_pool * pool = NULL ; if ( ! pool_overflow ) { pool = s390_mainpool_start ( ) ; if ( ! pool ) pool_overflow = true ; } if ( pool_overflow ) pool = s390_chunkify_start ( ) ; if ( ! TARGET_CPU_ZARCH && s390_split_branches ( ) ) { if ( pool_overflow ) s390_chunkify_cancel ( pool ) ; else s390_mainpool_cancel ( pool ) ; continue ; } if ( pool_overflow ) s390_chunkify_finish ( pool ) ; else s390_mainpool_finish ( pool ) ; cfun -> machine -> split_branches_pending_p = false ; break ; } if ( TARGET_CPU_ZARCH ) { rtx_insn * insn , * target ; rtx label ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { label = s390_execute_label ( insn ) ; if ( ! label ) continue ; gcc_assert ( label != const0_rtx ) ; target = emit_label ( XEXP ( label , 0 ) ) ; INSN_ADDRESSES_NEW ( target , - 1 ) ; if ( JUMP_P ( insn ) ) { target = emit_jump_insn ( s390_execute_target ( insn ) ) ; JUMP_LABEL ( target ) = JUMP_LABEL ( insn ) ; } else target = emit_insn ( s390_execute_target ( insn ) ) ; INSN_ADDRESSES_NEW ( target , - 1 ) ; } } s390_optimize_prologue ( ) ; if ( s390_tune >= PROCESSOR_2097_Z10 ) { rtx_insn * insn ; bool insn_added_p = false ; shorten_branches ( get_insns ( ) ) ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( ! INSN_P ( insn ) || INSN_CODE ( insn ) <= 0 ) continue ; if ( JUMP_P ( insn ) ) insn_added_p |= s390_fix_long_loop_prediction ( insn ) ; if ( ( GET_CODE ( PATTERN ( insn ) ) == PARALLEL || GET_CODE ( PATTERN ( insn ) ) == SET ) && s390_tune == PROCESSOR_2097_Z10 ) insn_added_p |= s390_z10_optimize_cmp ( insn ) ; } if ( insn_added_p ) shorten_branches ( get_insns ( ) ) ; } s390_function_num_hotpatch_hw ( current_function_decl , & hw_before , & hw_after ) ; if ( hw_after > 0 ) { rtx_insn * insn ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( active_insn_p ( insn ) || BARRIER_P ( insn ) || LABEL_P ( insn ) ) break ; while ( insn && hw_after > 0 ) { if ( hw_after >= 3 && TARGET_CPU_ZARCH ) { emit_insn_before ( gen_nop_6_byte ( ) , insn ) ; hw_after -= 3 ; } else if ( hw_after >= 2 ) { emit_insn_before ( gen_nop_4_byte ( ) , insn ) ; hw_after -= 2 ; } else { emit_insn_before ( gen_nop_2_byte ( ) , insn ) ; hw_after -= 1 ; } } } } </s>


<s> iterator begin ( ) const { return SubExceptions . begin ( ) ; } </s>


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s> static int mips_mode_rep_extended ( scalar_int_mode mode , scalar_int_mode mode_rep ) { if ( TARGET_64BIT && mode == SImode && mode_rep == DImode ) return SIGN_EXTEND ; return UNKNOWN ; } </s>


<s>
StringRef
AArch64MCExpr
::
getVariantKindName
(
)
const
{
switch
(
static_cast
<
uint32_t
>
(
getKind
(
)
)
)
{
case
VK_CALL
:
return
""
;
case
VK_LO12
:
return
":lo12:"
;
case
VK_ABS_G3
:
return
":abs_g3:"
;
case
VK_ABS_G2
:
return
":abs_g2:"
;
case
VK_ABS_G2_S
:
return
":abs_g2_s:"
;
case
VK_ABS_G2_NC
:
return
":abs_g2_nc:"
;
case
VK_ABS_G1
:
return
":abs_g1:"
;
case
VK_ABS_G1_S
:
return
":abs_g1_s:"
;
case
VK_ABS_G1_NC
:
return
":abs_g1_nc:"
;
case
VK_ABS_G0
:
return
":abs_g0:"
;
case
VK_ABS_G0_S
:
return
":abs_g0_s:"
;
case
VK_ABS_G0_NC
:
return
":abs_g0_nc:"
;
case
VK_DTPREL_G2
:
return
":dtprel_g2:"
;
case
VK_DTPREL_G1
:
return
":dtprel_g1:"
;
case
VK_DTPREL_G1_NC
:
return
":dtprel_g1_nc:"
;
case
VK_DTPREL_G0
:
return
":dtprel_g0:"
;
case
VK_DTPREL_G0_NC
:
return
":dtprel_g0_nc:"
;
case
VK_DTPREL_HI12
:
return
":dtprel_hi12:"
;
case
VK_DTPREL_LO12
:
return
":dtprel_lo12:"
;
case
VK_DTPREL_LO12_NC
:
return
":dtprel_lo12_nc:"
;
case
VK_TPREL_G2
:
return
":tprel_g2:"
;
case
VK_TPREL_G1
:
return
":tprel_g1:"
;
case
VK_TPREL_G1_NC
:
return
":tprel_g1_nc:"
;
case
VK_TPREL_G0
:
return
":tprel_g0:"
;
case
VK_TPREL_G0_NC
:
return
":tprel_g0_nc:"
;
case
VK_TPREL_HI12
:
return
":tprel_hi12:"
;
case
VK_TPREL_LO12
:
return
":tprel_lo12:"
;
case
VK_TPREL_LO12_NC
:
return
":tprel_lo12_nc:"
;
case
VK_TLSDESC_LO12
:
return
":tlsdesc_lo12:"
;
case
VK_ABS_PAGE
:
return
""
;
case
VK_ABS_PAGE_NC
:
return
":pg_hi21_nc:"
;
case
VK_GOT
:
return
":got:"
;
case
VK_GOT_PAGE
:
return
":got:"
;
case
VK_GOT_LO12
:
return
":got_lo12:"
;
case
VK_GOTTPREL
:
return
":gottprel:"
;
case
VK_GOTTPREL_PAGE
:
return
":gottprel:"
;
case
VK_GOTTPREL_LO12_NC
:
return
":gottprel_lo12:"
;
case
VK_GOTTPREL_G1
:
return
":gottprel_g1:"
;
case
VK_GOTTPREL_G0_NC
:
return
":gottprel_g0_nc:"
;
case
VK_TLSDESC
:
return
""
;
case
VK_TLSDESC_PAGE
:
return
":tlsdesc:"
;
case
VK_SECREL_LO12
:
return
":secrel_lo12:"
;
case
VK_SECREL_HI12
:
return
":secrel_hi12:"
;
default
:
llvm_unreachable
(
"Invalid ELF symbol kind"
)
;
}
}
</s>

Convert the variant kind into an ELF-appropriate modifier ( e.g .


<s> static int elf_dcachebsize ( void ) { int fd ; fd = open ( "/proc/self/auxv" , O_RDONLY ) ; if ( fd != - 1 ) { char buf [ 1024 ] ; ElfW ( auxv_t ) * av ; ssize_t n ; n = read ( fd , buf , sizeof ( buf ) ) ; close ( fd ) ; if ( n > 0 ) { for ( av = ( ElfW ( auxv_t ) * ) buf ; av -> a_type != AT_NULL ; ++ av ) switch ( av -> a_type ) { case AT_DCACHEBSIZE : return av -> a_un . a_val ; default : break ; } } } </s>

Returns AT_DCACHEBSIZE if present , otherwise generic 32 .


"Unrecognized Hexagon processor version"


<s> bool HexagonInstrInfo :: getBaseAndOffsetPosition ( const MachineInstr & MI , unsigned & BasePos , unsigned & OffsetPos ) const { if ( isMemOp ( MI ) ) { BasePos = 0 ; OffsetPos = 1 ; } else if ( MI . mayStore ( ) ) { BasePos = 0 ; OffsetPos = 1 ; } else if ( MI . mayLoad ( ) ) { BasePos = 1 ; OffsetPos = 2 ; } else return false ; if ( isPredicated ( MI ) ) { BasePos ++ ; OffsetPos ++ ; } if ( isPostIncrement ( MI ) ) { BasePos ++ ; OffsetPos ++ ; } if ( ! MI . getOperand ( BasePos ) . isReg ( ) || ! MI . getOperand ( OffsetPos ) . isImm ( ) ) return false ; return true ; } </s>

Return true if the instruction contains a base register and offset .


<s> BitVector HexagonRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( Hexagon :: R29 ) ; Reserved . set ( Hexagon :: R30 ) ; Reserved . set ( Hexagon :: R31 ) ; Reserved . set ( Hexagon :: SA0 ) ; Reserved . set ( Hexagon :: LC0 ) ; Reserved . set ( Hexagon :: SA1 ) ; Reserved . set ( Hexagon :: LC1 ) ; Reserved . set ( Hexagon :: USR ) ; Reserved . set ( Hexagon :: PC ) ; Reserved . set ( Hexagon :: UGP ) ; Reserved . set ( Hexagon :: GP ) ; Reserved . set ( Hexagon :: CS0 ) ; Reserved . set ( Hexagon :: CS1 ) ; Reserved . set ( Hexagon :: C8 ) ; Reserved . set ( Hexagon :: USR_OVF ) ; for ( int x = Reserved . find_first ( ) ; x >= 0 ; x = Reserved . find_next ( x ) ) markSuperRegs ( Reserved , x ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool AArch64TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { if ( ! getTargetMachine ( ) . getTargetTriple ( ) . isOSBinFormatELF ( ) ) return false ; return Subtarget -> ClassifyGlobalReference ( GA -> getGlobal ( ) , getTargetMachine ( ) ) == AArch64II :: MO_NO_FLAG ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> unsigned MipsRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; bool IsN64 = static_cast < const MipsTargetMachine & > ( MF . getTarget ( ) ) . getABI ( ) . IsN64 ( ) ; if ( Subtarget . inMips16Mode ( ) ) return TFI -> hasFP ( MF ) ? Mips :: S0 : Mips :: SP ; else return TFI -> hasFP ( MF ) ? ( IsN64 ? Mips :: FP_64 : Mips :: FP ) : ( IsN64 ? Mips :: SP_64 : Mips :: SP ) ; } </s>

Mips Mips Mips Mips Mips::S0 Mips::SP Mips::FP_64 Mips::FP Mips::SP_64 Mips::SP