<s> void DLXInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator Position , const DebugLoc & DL , unsigned DestinationRegister , unsigned SourceRegister , bool KillSource ) const { } </s>


"missing value in %<target()%> pragma or attribute"

"invalid feature modifier %s of value (\"%s\") in "

Parse an architecture extensions target attribute string specified in STR . For example `` +fp+nosimd '' . Show any errors if needed . Return TRUE if successful . Update aarch64_isa_flags to reflect the ISA features modified . PRAGMA_OR_ATTR is used in potential error messages .


"instruction requires a CPU feature not currently enabled"

"flag setting instruction only valid outside IT block"

"instruction only valid inside IT block"

"instruction variant requires ARMv6 or later"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> bool NVPTXAsmPrinter :: doFinalization ( Module & M ) { bool HasDebugInfo = MMI && MMI -> hasDebugInfo ( ) ; if ( ! GlobalsEmitted ) { emitGlobals ( M ) ; GlobalsEmitted = true ; } bool ret = AsmPrinter :: doFinalization ( M ) ; clearAnnotationCache ( & M ) ; if ( HasDebugInfo ) { static_cast < NVPTXTargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) -> closeLastSection ( ) ; OutStreamer -> emitRawText ( "\t.section\t.debug_loc\t{\t}" ) ; } static_cast < NVPTXTargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) -> outputDwarfFileDirectives ( ) ; return ret ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .

NVPTX NVPTX NVPTX "\t.section\t.debug_loc\t{\t}" NVPTX


<s> static X86Operand CreateReg ( unsigned RegNo ) { X86Operand Res ; Res . Kind = Register ; Res . Reg . RegNo = RegNo ; return Res ; } </s>

CreateReg - Allocate a single virtual register for the given type .


"movhi hi(%s), r0, r11\n\tmovea lo(%s), r11, r11\n\tjarl .+4, r10\n\tadd 4, r10\n\tjmp r11"

Construct a JARL instruction to a routine that will perform the equivalent of the RTL passed as a parameter . This RTL is a function prologue that saves some of the registers r20 - r31 onto the stack , and possibly acquires some stack space as well . The code has already verified that the RTL matches these requirements .


<s>
bool
SystemZAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
SmallVectorImpl
<
MCParsedAsmOperand
*
>
&
Operands
,
MCStreamer
&
Out
,
unsigned
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
;
MatchResult
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MatchingInlineAsm
)
;
switch
(
MatchResult
)
{
default
:
break
;
case
Match_Success
:
Inst
.
setLoc
(
IDLoc
)
;
Out
.
EmitInstruction
(
Inst
,
STI
)
;
return
false
;
case
Match_MissingFeature
:
{
assert
(
ErrorInfo
&&
"Unknown missing feature!"
)
;
std
::
string
Msg
=
"instruction requires:"
;
unsigned
Mask
=
1
;
for
(
unsigned
I
=
0
;
I
<
sizeof
(
ErrorInfo
)
*
8
1
;
++
I
)
{
if
(
ErrorInfo
&
Mask
)
{
Msg
+=
" "
;
Msg
+=
getSubtargetFeatureName
(
ErrorInfo
&
Mask
)
;
}
Mask
<<=
1
;
}
return
Error
(
IDLoc
,
Msg
)
;
}
case
Match_InvalidOperand
:
{
SMLoc
ErrorLoc
=
IDLoc
;
if
(
ErrorInfo
!=
~
0U
)
{
if
(
ErrorInfo
>=
Operands
.
size
(
)
)
return
Error
(
IDLoc
,
"too few operands for instruction"
)
;
ErrorLoc
=
(
(
SystemZOperand
*
)
Operands
[
ErrorInfo
]
)
->
getStartLoc
(
)
;
if
(
ErrorLoc
==
SMLoc
(
)
)
ErrorLoc
=
IDLoc
;
}
return
Error
(
ErrorLoc
,
"invalid operand for instruction"
)
;
}
case
Match_MnemonicFail
:
return
Error
(
IDLoc
,
"invalid instruction"
)
;
}
llvm_unreachable
(
"Unexpected match type"
)
;
}
</s>


<s> static int rs6000_use_sched_lookahead ( void ) { switch ( rs6000_tune ) { case PROCESSOR_PPC8540 : case PROCESSOR_PPC8548 : return 4 ; case PROCESSOR_CELL : return ( reload_completed ? 8 : 0 ) ; default : return 0 ; } } </s>

Return how many instructions to look ahead for better insn scheduling .


<s> bool PatmosInstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { int64_t invflag = Cond [ 1 ] . getImm ( ) ; Cond [ 1 ] . setImm ( ( invflag ) ? 0 : - 1 ) ; return false ; } </s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> ArrayRef < std :: pair < int , const char * >> SIInstrInfo :: getSerializableTargetIndices ( ) const { static const std :: pair < int , const char * > TargetIndices [ ] = { { AMDGPU :: TI_CONSTDATA_START , "amdgpu-constdata-start" } , { AMDGPU :: TI_SCRATCH_RSRC_DWORD0 , "amdgpu-scratch-rsrc-dword0" } , { AMDGPU :: TI_SCRATCH_RSRC_DWORD1 , "amdgpu-scratch-rsrc-dword1" } , { AMDGPU :: TI_SCRATCH_RSRC_DWORD2 , "amdgpu-scratch-rsrc-dword2" } , { AMDGPU :: TI_SCRATCH_RSRC_DWORD3 , "amdgpu-scratch-rsrc-dword3" } } ; return makeArrayRef ( TargetIndices ) ; } </s>

Return an array that contains the ids of the target indices ( used for the TargetIndex machine operand ) and their names .


<s> void MSP430InstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & O ) { if ( ! printAliasInstr ( MI , O ) ) printInstruction ( MI , Address , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> EVT AArch64TargetLowering :: getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const { bool CanImplicitFloat = ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; bool CanUseNEON = Subtarget -> hasNEON ( ) && CanImplicitFloat ; bool CanUseFP = Subtarget -> hasFPARMv8 ( ) && CanImplicitFloat ; bool IsSmallMemset = Op . isMemset ( ) && Op . size ( ) < 32 ; auto AlignmentIsAcceptable = [ & ] ( EVT VT , Align AlignCheck ) { if ( Op . isAligned ( AlignCheck ) ) return true ; bool Fast ; return allowsMisalignedMemoryAccesses ( VT , 0 , 1 , MachineMemOperand :: MONone , & Fast ) && Fast ; } ; if ( CanUseNEON && Op . isMemset ( ) && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: v2i64 , Align ( 16 ) ) ) return MVT :: v2i64 ; if ( CanUseFP && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: f128 , Align ( 16 ) ) ) return MVT :: f128 ; if ( Op . size ( ) >= 8 && AlignmentIsAcceptable ( MVT :: i64 , Align ( 8 ) ) ) return MVT :: i64 ; if ( Op . size ( ) >= 4 && AlignmentIsAcceptable ( MVT :: i32 , Align ( 4 ) ) ) return MVT :: i32 ; return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> static void aarch64_finish_cost ( void * data , unsigned * prologue_cost , unsigned * body_cost , unsigned * epilogue_cost ) { auto * costs = static_cast < aarch64_vector_costs * > ( data ) ; * prologue_cost = costs -> region [ vect_prologue ] ; * body_cost = costs -> region [ vect_body ] ; * epilogue_cost = costs -> region [ vect_epilogue ] ; if ( costs -> is_loop && costs -> vec_flags && aarch64_use_new_vector_costs_p ( ) ) * body_cost = aarch64_adjust_body_cost ( costs , * body_cost ) ; } </s>


<s> CCAssignFn * AArch64FastISel :: CCAssignFnForCall ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: WebKit_JS ) return CC_AArch64_WebKit_JS ; if ( CC == CallingConv :: GHC ) return CC_AArch64_GHC ; return Subtarget -> isTargetDarwin ( ) ? CC_AArch64_DarwinPCS : CC_AArch64_AAPCS ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> static bool alpha_vms_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { alpha_sa_size ( ) ; switch ( alpha_procedure_type ) { case PT_NULL : return to == STACK_POINTER_REGNUM ; case PT_REGISTER : case PT_STACK : return ( to != STACK_POINTER_REGNUM || vms_unwind_regno != HARD_FRAME_POINTER_REGNUM ) ; } gcc_unreachable ( ) ; } </s>

Worker function for TARGET_CAN_ELIMINATE .


<s> void MipsTargetMachine :: resetSubtarget ( MachineFunction * MF ) { DEBUG ( dbgs ( ) << "resetSubtarget\n" ) ; Subtarget = const_cast < MipsSubtarget * > ( getSubtargetImpl ( * MF -> getFunction ( ) ) ) ; MF -> setSubtarget ( Subtarget ) ; return ; } </s>

Reset the subtarget for the Mips target .


<s> bool fixupNeedsRelaxationAdvanced ( const MCFixup & Fixup , bool Resolved , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { MCInst const & MCB = DF -> getInst ( ) ; assert ( HexagonMCInstrInfo :: isBundle ( MCB ) ) ; * RelaxTarget = nullptr ; MCInst & MCI = const_cast < MCInst & > ( HexagonMCInstrInfo :: instruction ( MCB , Fixup . getOffset ( ) / HEXAGON_INSTR_SIZE ) ) ; if ( ! Resolved ) { switch ( ( unsigned ) Fixup . getKind ( ) ) { case fixup_Hexagon_B22_PCREL : default : return false ; break ; case fixup_Hexagon_B13_PCREL : case fixup_Hexagon_B15_PCREL : case fixup_Hexagon_B9_PCREL : case fixup_Hexagon_B7_PCREL : { if ( HexagonMCInstrInfo :: bundleSize ( MCB ) < HEXAGON_PACKET_SIZE ) { ++ relaxedCnt ; * RelaxTarget = & MCI ; return true ; } else { return false ; } break ; } } } bool Relaxable = isInstRelaxable ( MCI ) ; if ( Relaxable == false ) return false ; MCFixupKind Kind = Fixup . getKind ( ) ; int64_t sValue = Value ; int64_t maxValue ; switch ( ( unsigned ) Kind ) { case fixup_Hexagon_B7_PCREL : maxValue = 1 << 8 ; break ; case fixup_Hexagon_B9_PCREL : maxValue = 1 << 10 ; break ; case fixup_Hexagon_B15_PCREL : maxValue = 1 << 16 ; break ; case fixup_Hexagon_B22_PCREL : maxValue = 1 << 23 ; break ; default : maxValue = INT64_MAX ; break ; } bool isFarAway = - maxValue > sValue || sValue > maxValue - 1 ; if ( isFarAway ) { if ( HexagonMCInstrInfo :: bundleSize ( MCB ) < HEXAGON_PACKET_SIZE ) { ++ relaxedCnt ; * RelaxTarget = & MCI ; return true ; } } return false ; } </s>

Target specific predicate for whether a given fixup requires the associated instruction to be relaxed .


<s> std :: unique_ptr < MCObjectWriter > createObjectWriter ( raw_pwrite_stream & OS ) const override { return createHexagonELFObjectWriter ( OS , OSABI , CPU ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static void CreateMem ( OwningPtr < ARMOperand > & Op , unsigned BaseRegNum , bool OffsetIsReg , const MCExpr * Offset , unsigned OffsetRegNum , bool OffsetRegShifted , enum ShiftType ShiftType , const MCExpr * ShiftAmount , bool Preindexed , bool Postindexed , bool Negative , bool Writeback , SMLoc S , SMLoc E ) { Op . reset ( new ARMOperand ) ; Op -> Kind = Memory ; Op -> Mem . BaseRegNum = BaseRegNum ; Op -> Mem . OffsetIsReg = OffsetIsReg ; Op -> Mem . Offset = Offset ; Op -> Mem . OffsetRegNum = OffsetRegNum ; Op -> Mem . OffsetRegShifted = OffsetRegShifted ; Op -> Mem . ShiftType = ShiftType ; Op -> Mem . ShiftAmount = ShiftAmount ; Op -> Mem . Preindexed = Preindexed ; Op -> Mem . Postindexed = Postindexed ; Op -> Mem . Negative = Negative ; Op -> Mem . Writeback = Writeback ; Op -> StartLoc = S ; Op -> EndLoc = E ; } </s>


<s> static bool classof ( const MCExpr * E ) { return E -> getKind ( ) == MCExpr :: Target ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s>
bool
PPCDarwinAsmPrinter
::
doInitialization
(
Module
&
M
)
{
static
const
char
*
const
CPUDirectives
[
]
=
{
""
,
"ppc"
,
"ppc601"
,
"ppc602"
,
"ppc603"
,
"ppc7400"
,
"ppc750"
,
"ppc970"
,
"ppc64"
}
;
unsigned
Directive
=
Subtarget
.
getDarwinDirective
(
)
;
if
(
Subtarget
.
isGigaProcessor
(
)
&&
Directive
<
PPC
::
DIR_970
)
Directive
=
PPC
::
DIR_970
;
if
(
Subtarget
.
hasAltivec
(
)
&&
Directive
<
PPC
::
DIR_7400
)
Directive
=
PPC
::
DIR_7400
;
if
(
Subtarget
.
isPPC64
(
)
&&
Directive
<
PPC
::
DIR_970
)
Directive
=
PPC
::
DIR_64
;
assert
(
Directive
<=
PPC
::
DIR_64
&&
"Directive out of range."
)
;
O
<<
"\t.machine "
<<
CPUDirectives
[
Directive
]
<<
'\n'
;
bool
Result
=
AsmPrinter
::
doInitialization
(
M
)
;
assert
(
MMI
)
;
TargetLoweringObjectFileMachO
&
TLOFMacho
=
static_cast
<
TargetLoweringObjectFileMachO
&
>
(
getObjFileLowering
(
)
)
;
OutStreamer
.
SwitchSection
(
TLOFMacho
.
getTextCoalSection
(
)
)
;
if
(
TM
.
getRelocationModel
(
)
==
Reloc
::
PIC_
)
{
OutStreamer
.
SwitchSection
(
TLOFMacho
.
getMachOSection
(
"__TEXT"
,
"__picsymbolstub1"
,
MCSectionMachO
::
S_SYMBOL_STUBS
|
MCSectionMachO
::
S_ATTR_PURE_INSTRUCTIONS
,
32
,
SectionKind
::
getText
(
)
)
)
;
}
else
if
(
TM
.
getRelocationModel
(
)
==
Reloc
::
DynamicNoPIC
)
{
OutStreamer
.
SwitchSection
(
TLOFMacho
.
getMachOSection
(
"__TEXT"
,
"__symbol_stub1"
,
MCSectionMachO
::
S_SYMBOL_STUBS
|
MCSectionMachO
::
S_ATTR_PURE_INSTRUCTIONS
,
16
,
SectionKind
::
getText
(
)
)
)
;
}
OutStreamer
.
SwitchSection
(
getObjFileLowering
(
)
.
getTextSection
(
)
)
;
return
Result
;
}
</s>

Set up the AsmPrinter when we are working on a new module .


<s>
unsigned
assignCustomValue
(
const
llvm
::
ARMCallLowering
::
ArgInfo
&
Arg
,
ArrayRef
<
CCValAssign
>
VAs
)
override
{
CCValAssign
VA
=
VAs
[
0
]
;
assert
(
VA
.
needsCustom
(
)
&&
"Value doesn't need custom handling"
)
;
assert
(
VA
.
getValVT
(
)
==
MVT
::
f64
&&
"Unsupported type"
)
;
CCValAssign
NextVA
=
VAs
[
1
]
;
assert
(
NextVA
.
needsCustom
(
)
&&
"Value doesn't need custom handling"
)
;
assert
(
NextVA
.
getValVT
(
)
==
MVT
::
f64
&&
"Unsupported type"
)
;
assert
(
VA
.
getValNo
(
)
==
NextVA
.
getValNo
(
)
&&
"Values belong to different arguments"
)
;
assert
(
VA
.
isRegLoc
(
)
&&
"Value should be in reg"
)
;
assert
(
NextVA
.
isRegLoc
(
)
&&
"Value should be in reg"
)
;
unsigned
NewRegs
[
]
=
{
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
32
)
)
,
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
32
)
)
}
;
assignValueToReg
(
NewRegs
[
0
]
,
VA
.
getLocReg
(
)
,
VA
)
;
assignValueToReg
(
NewRegs
[
1
]
,
NextVA
.
getLocReg
(
)
,
NextVA
)
;
bool
IsLittle
=
MIRBuilder
.
getMF
(
)
.
getSubtarget
<
ARMSubtarget
>
(
)
.
isLittle
(
)
;
if
(
!
IsLittle
)
std
::
swap
(
NewRegs
[
0
]
,
NewRegs
[
1
]
)
;
MIRBuilder
.
buildSequence
(
Arg
.
Reg
,
NewRegs
,
{
0
,
32
}
)
;
return
1
;
}
</s>

Handle custom values , which may be passed into one or more of VAs .


<s> void ix86_initialize_callee_abi ( unsigned int abi_id ) { gcc_assert ( abi_id == ABI_VZEROUPPER ) ; predefined_function_abi & vzeroupper_abi = function_abis [ abi_id ] ; if ( ! vzeroupper_abi . initialized_p ( ) ) { HARD_REG_SET full_reg_clobbers ; CLEAR_HARD_REG_SET ( full_reg_clobbers ) ; vzeroupper_abi . initialize ( ABI_VZEROUPPER , full_reg_clobbers ) ; } } </s>

Initialize function_abis with corresponding abi_id , currently only handle vzeroupper .


<s> StringRef getPassName ( ) const override { return ARM_EXPAND_PSEUDO_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> bool PPCSubtarget :: enableMachinePipeliner ( ) const { return ( DarwinDirective == PPC :: DIR_PWR9 ) && EnableMachinePipeliner ; } </s>

True if the subtarget should run MachinePipeliner .


<s> bool rs6000_is_valid_insert_mask ( rtx mask , rtx shift , machine_mode mode ) { int nb , ne ; if ( ! rs6000_is_valid_mask ( mask , & nb , & ne , mode ) ) return false ; int n = GET_MODE_PRECISION ( mode ) ; int sh = INTVAL ( XEXP ( shift , 1 ) ) ; if ( sh < 0 || sh >= n ) return false ; rtx_code code = GET_CODE ( shift ) ; if ( sh == 0 ) code = ROTATE ; if ( code == ROTATE && sh >= 0 && nb >= ne && ne >= sh ) code = ASHIFT ; if ( code == ROTATE && sh >= 0 && nb >= ne && nb < sh ) { code = LSHIFTRT ; sh = n - sh ; } if ( mode == DImode && code == ROTATE ) return ( ne == sh ) ; if ( mode == SImode && code == ROTATE ) return ( nb < 32 && ne < 32 && sh < 32 ) ; if ( ne > nb ) return false ; if ( code == ASHIFT && ne < sh ) return false ; if ( nb < 32 && ne < 32 && sh < 32 && ! ( code == LSHIFTRT && nb >= 32 - sh ) ) return true ; if ( code == LSHIFTRT ) sh = 64 - sh ; if ( ne == sh ) return ! ( code == LSHIFTRT && nb >= sh ) ; return false ; } </s>

Return whether MASK ( a CONST_INT ) is a valid mask for any rlwimi or rldimi instruction , to implement an insert with shift SHIFT ( a ROTATE , ASHIFT , or LSHIFTRT ) in mode MODE .


<s> bool AMDGPUInstrInfo :: isPredicated ( const MachineInstr * MI ) const { return false ; } </s>

Returns true if the instruction is already predicated .


<s> bool SystemZInstrInfo :: isPredicable ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == SystemZ :: Return || Opcode == SystemZ :: Return_XPLINK || Opcode == SystemZ :: Trap || Opcode == SystemZ :: CallJG || Opcode == SystemZ :: CallBR ) return true ; return false ; } </s>

Return true if the specified instruction can be predicated .

SystemZ SystemZ SystemZ::Return SystemZ::Return_XPLINK SystemZ::Trap SystemZ::CallJG SystemZ::CallBR


<s> unsigned PPCFrameLowering :: determineFrameLayout ( MachineFunction & MF , bool UpdateMF , bool UseEstimate ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = UseEstimate ? MFI -> estimateStackSize ( MF ) : MFI -> getStackSize ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - 1 ; bool DisableRedZone = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoRedZone ) ; if ( ! DisableRedZone && ( Subtarget . isPPC64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == 0 ) && FrameSize <= 224 && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ( ! ALIGN_STACK || MaxAlign <= TargetAlign ) ) { if ( UpdateMF ) MFI -> setStackSize ( 0 ) ; return 0 ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getMinCallFrameSize ( Subtarget . isPPC64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setStackSize ( FrameSize ) ; return FrameSize ; } </s>

Determine the frame layout but do not update the machine function .


<s>
void
MBlazeOperand
::
dump
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
Immediate
:
getImm
(
)
->
print
(
OS
)
;
break
;
case
Register
:
OS
<<
"<register R"
;
OS
<<
MBlazeRegisterInfo
::
getRegisterNumbering
(
getReg
(
)
)
<<
">"
;
break
;
case
Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
case
Memory
:
{
OS
<<
"<memory R"
;
OS
<<
MBlazeRegisterInfo
::
getRegisterNumbering
(
getMemBase
(
)
)
;
OS
<<
", "
;
unsigned
RegOff
=
getMemOffReg
(
)
;
if
(
RegOff
)
OS
<<
"R"
<<
MBlazeRegisterInfo
::
getRegisterNumbering
(
RegOff
)
;
else
OS
<<
getMemOff
(
)
;
OS
<<
">"
;
}
break
;
case
Fsl
:
getFslImm
(
)
->
print
(
OS
)
;
break
;
}
}
</s>

Dump the plan to stderr ( for debugging ) .

MBlaze
MBlaze
"<register R"
MBlaze
">"
"'"
"'"
"<memory R"
MBlaze
", "
"R"
MBlaze
">"


<s>
const
MCPhysReg
*
PPCRegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
const
PPCSubtarget
&
Subtarget
=
MF
->
getSubtarget
<
PPCSubtarget
>
(
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
{
if
(
!
TM
.
isPPC64
(
)
&&
Subtarget
.
isAIXABI
(
)
)
report_fatal_error
(
"AnyReg unimplemented on 32-bit AIX."
)
;
if
(
Subtarget
.
hasVSX
(
)
)
return
CSR_64_AllRegs_VSX_SaveList
;
if
(
Subtarget
.
hasAltivec
(
)
)
return
CSR_64_AllRegs_Altivec_SaveList
;
return
CSR_64_AllRegs_SaveList
;
}
bool
SaveR2
=
MF
->
getRegInfo
(
)
.
isAllocatable
(
PPC
::
X2
)
&&
!
Subtarget
.
isUsingPCRelativeCalls
(
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
Cold
)
{
if
(
Subtarget
.
isAIXABI
(
)
)
report_fatal_error
(
"Cold calling unimplemented on AIX."
)
;
if
(
TM
.
isPPC64
(
)
)
{
if
(
Subtarget
.
hasAltivec
(
)
)
return
SaveR2
CSR_SVR64_ColdCC_R2_Altivec_SaveList
:
CSR_SVR64_ColdCC_Altivec_SaveList
;
return
SaveR2
CSR_SVR64_ColdCC_R2_SaveList
:
CSR_SVR64_ColdCC_SaveList
;
}
if
(
Subtarget
.
hasAltivec
(
)
)
return
CSR_SVR32_ColdCC_Altivec_SaveList
;
else
if
(
Subtarget
.
hasSPE
(
)
)
return
CSR_SVR32_ColdCC_SPE_SaveList
;
return
CSR_SVR32_ColdCC_SaveList
;
}
if
(
TM
.
isPPC64
(
)
)
{
if
(
Subtarget
.
hasAltivec
(
)
)
return
SaveR2
CSR_PPC64_R2_Altivec_SaveList
:
CSR_PPC64_Altivec_SaveList
;
return
SaveR2
CSR_PPC64_R2_SaveList
:
CSR_PPC64_SaveList
;
}
if
(
Subtarget
.
isAIXABI
(
)
)
return
CSR_AIX32_SaveList
;
if
(
Subtarget
.
hasAltivec
(
)
)
return
CSR_SVR432_Altivec_SaveList
;
else
if
(
Subtarget
.
hasSPE
(
)
)
return
CSR_SVR432_SPE_SaveList
;
return
CSR_SVR432_SaveList
;
}
</s>

PowerPC
PPC
PPC
PPC
PPC
"AnyReg unimplemented on 32-bit AIX."
PPC::X2
"Cold calling unimplemented on AIX."
PPC
PPC
PPC
PPC
PPC
PPC


"-misched-topdown incompatible with -misched-bottomup"

Initialize the strategy after building the DAG for a new region .


"AMDGPU DAG->DAG Pattern Instruction Selection"


<s> void AArch64PassConfig :: addPreLegalizeMachineIR ( ) { bool IsOptNone = getOptLevel ( ) == CodeGenOpt :: None ; addPass ( createAArch64PreLegalizeCombiner ( IsOptNone ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before legalization .


<s>
const
MipsMCExpr
*
MipsMCExpr
::
Create
(
MCSymbolRefExpr
::
VariantKind
VK
,
const
MCExpr
*
Expr
,
MCContext
&
Ctx
)
{
VariantKind
Kind
;
switch
(
VK
)
{
case
MCSymbolRefExpr
::
VK_Mips_ABS_LO
:
Kind
=
VK_Mips_LO
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_ABS_HI
:
Kind
=
VK_Mips_HI
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_HIGHER
:
Kind
=
VK_Mips_HIGHER
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_HIGHEST
:
Kind
=
VK_Mips_HIGHEST
;
break
;
default
:
llvm_unreachable
(
"Invalid kind!"
)
;
}
return
new
(
Ctx
)
MipsMCExpr
(
Kind
,
Expr
)
;
}
</s>

Construct a unary instruction , given the opcode and an operand .

Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
"Invalid kind!"
Mips


"unknown MIR custom pseudo source value"

Implement target specific parsing of target custom pseudo source value .


<s> bool AMDGPUPassConfig :: addPreEmitPass ( ) { const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . device ( ) -> getGeneration ( ) <= AMDGPUDeviceInfo :: HD6XXX ) { addPass ( createAMDGPUCFGPreparationPass ( * TM ) ) ; addPass ( createAMDGPUCFGStructurizerPass ( * TM ) ) ; addPass ( createR600ExpandSpecialInstrsPass ( * TM ) ) ; addPass ( & FinalizeMachineBundlesID ) ; addPass ( createR600LowerConstCopy ( * TM ) ) ; } else { addPass ( createSILowerControlFlowPass ( * TM ) ) ; } return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool MSP430FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , MutableArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) BuildMI ( MBB , MI , DL , TII . get ( MSP430 :: POP16r ) , CSI [ i ] . getReg ( ) ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool WebAssemblyPassConfig :: addILPOpts ( ) { ( void ) TargetPassConfig :: addILPOpts ( ) ; return true ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .


<s> static bool aarch64_const_vec_all_in_range_p ( rtx vec , HOST_WIDE_INT minval , HOST_WIDE_INT maxval ) { if ( GET_CODE ( vec ) != CONST_VECTOR || GET_MODE_CLASS ( GET_MODE ( vec ) ) != MODE_VECTOR_INT ) return false ; int nunits ; if ( ! CONST_VECTOR_STEPPED_P ( vec ) ) nunits = const_vector_encoded_nelts ( vec ) ; else if ( ! CONST_VECTOR_NUNITS ( vec ) . is_constant ( & nunits ) ) return false ; for ( int i = 0 ; i < nunits ; i ++ ) { rtx vec_elem = CONST_VECTOR_ELT ( vec , i ) ; if ( ! CONST_INT_P ( vec_elem ) || ! IN_RANGE ( INTVAL ( vec_elem ) , minval , maxval ) ) return false ; } return true ; } </s>

Return true if VEC is a constant in which every element is in the range [ MINVAL , MAXVAL ] . The elements do not need to have the same value .


<s>
void
setReg
(
unsigned
RegNo
)
{
assert
(
Kind
==
k_Reg
&&
"Invalid access!"
)
;
Reg
=
RegNo
;
}
</s>

Assigns the associated register for this edge .


<s> void frv_initialize_trampoline ( rtx addr , rtx fnaddr , rtx static_chain ) { rtx sc_reg = force_reg ( Pmode , static_chain ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( SImode , "__trampoline_setup" ) , FALSE , VOIDmode , 4 , addr , Pmode , GEN_INT ( frv_trampoline_size ( ) ) , SImode , fnaddr , Pmode , sc_reg , Pmode ) ; } </s>

A C statement to initialize the variable parts of a trampoline . ADDR is an RTX for the address of the trampoline ; FNADDR is an RTX for the address of the nested function ; STATIC_CHAIN is an RTX for the static chain value that should be passed to the function when it is called . The template is : setlo # 0 , < jmp_reg > setlo # 0 , < static_chain > sethi # 0 , < jmp_reg > sethi # 0 , < static_chain > jmpl @ ( gr0 , < jmp_reg > )


<s> MCContext & getContext ( ) const { return Streamer . getContext ( ) ; } </s>

Return the LLVMContext used by the analysis .


<s> int ARMTTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned Bits = Ty -> getPrimitiveSizeInBits ( ) ; if ( Bits == 0 || Imm . getActiveBits ( ) >= 64 ) return 4 ; int64_t SImmVal = Imm . getSExtValue ( ) ; uint64_t ZImmVal = Imm . getZExtValue ( ) ; if ( ! ST -> isThumb ( ) ) { if ( ( SImmVal >= 0 && SImmVal < 65536 ) || ( ARM_AM :: getSOImmVal ( ZImmVal ) != - 1 ) || ( ARM_AM :: getSOImmVal ( ~ ZImmVal ) != - 1 ) ) return 1 ; return ST -> hasV6T2Ops ( ) ? 2 : 3 ; } if ( ST -> isThumb2 ( ) ) { if ( ( SImmVal >= 0 && SImmVal < 65536 ) || ( ARM_AM :: getT2SOImmVal ( ZImmVal ) != - 1 ) || ( ARM_AM :: getT2SOImmVal ( ~ ZImmVal ) != - 1 ) ) return 1 ; return ST -> hasV6T2Ops ( ) ? 2 : 3 ; } if ( Bits == 8 || ( SImmVal >= 0 && SImmVal < 256 ) ) return 1 ; if ( ( ~ SImmVal < 256 ) || ARM_AM :: isThumbImmShiftedVal ( ZImmVal ) ) return 2 ; return 3 ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> unsigned char ix86_memtag_tag_size ( ) { return IX86_HWASAN_TAG_SIZE ; } </s>


<s>
void
SHUXIDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
SDLoc
dl
(
Node
)
;
switch
(
Node
->
getOpcode
(
)
)
{
default
:
break
;
case
ISD
::
FrameIndex
:
{
assert
(
Node
->
getValueType
(
0
)
==
MVT
::
i32
)
;
int
FI
=
cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
MVT
::
i32
)
;
if
(
Node
->
hasOneUse
(
)
)
{
CurDAG
->
SelectNodeTo
(
Node
,
SHUXI
::
ADDri
,
MVT
::
i32
,
TFI
,
CurDAG
->
getTargetConstant
(
0
,
dl
,
MVT
::
i32
)
)
;
return
;
}
ReplaceNode
(
Node
,
CurDAG
->
getMachineNode
(
SHUXI
::
ADDri
,
dl
,
MVT
::
i32
,
TFI
,
CurDAG
->
getTargetConstant
(
0
,
dl
,
MVT
::
i32
)
)
)
;
return
;
}
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> static int nvptx_simt_vf ( ) { return PTX_WARP_SIZE ; } </s>

Implement TARGET_SIMT_VF target hook : number of threads in a warp .


<s> int AArch64FrameLowering :: getNonLocalFrameIndexReference ( const MachineFunction & MF , int FI ) const { return getSEHFrameIndexOffset ( MF , FI ) ; } </s>

getNonLocalFrameIndexReference - This method returns the offset used to reference a frame index location .


<s> void TriCoreRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ; unsigned FI = FIOp . getIndex ( ) ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; unsigned BasePtr = ( TFI -> hasFP ( MF ) ? TriCore :: A14 : TriCore :: A10 ) ; unsigned ImmOpIdx = 0 ; if ( MI . getOpcode ( ) == TriCore :: ADDrc ) { int Offset = MFI -> getObjectOffset ( FI ) ; Offset = - Offset ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MI . setDesc ( TII . get ( TriCore :: MOV_Drr ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; if ( Offset == 0 ) return ; unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ; if ( Offset < 0 ) { BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( TriCore :: ADDrc ) , DstReg ) . addReg ( DstReg ) . addImm ( Offset ) ; } else BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( TriCore :: ADDrc ) , DstReg ) . addReg ( DstReg ) . addImm ( - Offset ) ; return ; } ImmOpIdx = FIOperandNum + 1 ; MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ; int Offset = MFI -> getObjectOffset ( FI ) ; FIOp . ChangeToRegister ( BasePtr , false ) ; ImmOp . setImm ( Offset ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s>
Register
MipsOutgoingValueHandler
::
extendRegister
(
Register
ValReg
,
const
CCValAssign
&
VA
)
{
LLT
LocTy
{
VA
.
getLocVT
(
)
}
;
switch
(
VA
.
getLocInfo
(
)
)
{
case
CCValAssign
::
SExt
:
{
return
MIRBuilder
.
buildSExt
(
LocTy
,
ValReg
)
.
getReg
(
0
)
;
}
case
CCValAssign
::
ZExt
:
{
return
MIRBuilder
.
buildZExt
(
LocTy
,
ValReg
)
.
getReg
(
0
)
;
}
case
CCValAssign
::
AExt
:
{
return
MIRBuilder
.
buildAnyExt
(
LocTy
,
ValReg
)
.
getReg
(
0
)
;
}
case
CCValAssign
::
Full
:
return
ValReg
;
default
:
break
;
}
llvm_unreachable
(
"unable to extend register"
)
;
}
</s>

Extend a register to the location type given in VA , capped at extending to at most MaxSize bits .


<s> void HexagonInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ) ; if ( Hexagon :: IntRegsRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: S2_storeri_io ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( Hexagon :: DoubleRegsRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: S2_storerd_io ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( Hexagon :: PredRegsRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: STriw_pred ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else { llvm_unreachable ( "Unimplemented" ) ; } } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> unsigned X86InstrInfo :: getFMA3OpcodeToCommuteOperands ( const MachineInstr & MI , unsigned SrcOpIdx1 , unsigned SrcOpIdx2 , const X86InstrFMA3Group & FMA3Group ) const { unsigned Opc = MI . getOpcode ( ) ; if ( SrcOpIdx1 > SrcOpIdx2 ) std :: swap ( SrcOpIdx1 , SrcOpIdx2 ) ; if ( FMA3Group . isIntrinsic ( ) && SrcOpIdx1 == 1 ) return 0 ; int Case = getThreeSrcCommuteCase ( MI . getDesc ( ) . TSFlags , SrcOpIdx1 , SrcOpIdx2 ) ; if ( Case < 0 ) return 0 ; const unsigned Form132Index = 0 ; const unsigned Form213Index = 1 ; const unsigned Form231Index = 2 ; static const unsigned FormMapping [ ] [ 3 ] = { { Form231Index , Form213Index , Form132Index } , { Form132Index , Form231Index , Form213Index } , { Form213Index , Form132Index , Form231Index } } ; unsigned FMAForms [ 3 ] ; if ( FMA3Group . isRegOpcodeFromGroup ( Opc ) ) { FMAForms [ 0 ] = FMA3Group . getReg132Opcode ( ) ; FMAForms [ 1 ] = FMA3Group . getReg213Opcode ( ) ; FMAForms [ 2 ] = FMA3Group . getReg231Opcode ( ) ; } else { FMAForms [ 0 ] = FMA3Group . getMem132Opcode ( ) ; FMAForms [ 1 ] = FMA3Group . getMem213Opcode ( ) ; FMAForms [ 2 ] = FMA3Group . getMem231Opcode ( ) ; } unsigned FormIndex ; for ( FormIndex = 0 ; FormIndex < 3 ; FormIndex ++ ) if ( Opc == FMAForms [ FormIndex ] ) break ; FormIndex = FormMapping [ Case ] [ FormIndex ] ; return FMAForms [ FormIndex ] ; } </s>

Returns an adjusted FMA opcode that must be used in FMA instruction that performs the same computations as the given MI but which has the operands SrcOpIdx1 and SrcOpIdx2 commuted .


<s> bool SITargetLowering :: isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const { return isFlatGlobalAddrSpace ( SrcAS , AMDGPUASI ) && isFlatGlobalAddrSpace ( DestAS , AMDGPUASI ) ; } </s>

Returns true if a cast between SrcAS and DestAS is a noop .


<s> BitVector RISCVRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , RISCV :: X0 ) ; markSuperRegs ( Reserved , RISCV :: X1 ) ; markSuperRegs ( Reserved , RISCV :: X2 ) ; markSuperRegs ( Reserved , RISCV :: X3 ) ; markSuperRegs ( Reserved , RISCV :: X4 ) ; markSuperRegs ( Reserved , RISCV :: X8 ) ; markSuperRegs ( Reserved , RISCV :: VCFG ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


"getJumpTargetOpValue expects only expressions or an immediate"

getJumpTargetOpValue - Return binary encoding of the jump target operand .


<s> virtual const MCSection * getExplicitSectionGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler * Mang , const TargetMachine & TM ) const { return DataSection ; } </s>

Targets should implement this method to assign a section to globals with an explicit section specfied .


<s>
bool
AMDGPUAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Name
=
parseMnemonicSuffix
(
Name
)
;
Operands
.
push_back
(
AMDGPUOperand
::
CreateToken
(
this
,
Name
,
NameLoc
)
)
;
bool
IsMIMG
=
Name
.
startswith
(
"image_"
)
;
while
(
!
trySkipToken
(
AsmToken
::
EndOfStatement
)
)
{
OperandMode
Mode
=
OperandMode_Default
;
if
(
IsMIMG
&&
isGFX10Plus
(
)
&&
Operands
.
size
(
)
==
2
)
Mode
=
OperandMode_NSA
;
OperandMatchResultTy
Res
=
parseOperand
(
Operands
,
Name
,
Mode
)
;
trySkipToken
(
AsmToken
::
Comma
)
;
if
(
Res
!=
MatchOperand_Success
)
{
checkUnsupportedInstruction
(
Name
,
NameLoc
)
;
if
(
!
Parser
.
hasPendingError
(
)
)
{
StringRef
Msg
=
(
Res
==
MatchOperand_ParseFail
)
"failed parsing operand."
:
"not a valid operand."
;
Error
(
getLoc
(
)
,
Msg
)
;
}
while
(
!
trySkipToken
(
AsmToken
::
EndOfStatement
)
)
{
Parser
.
Lex
(
)
;
}
return
true
;
}
}
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

AMDGPU
AMDGPU
AMDGPU
"image_"
2
"failed parsing operand."
"not a valid operand."


<s> bool AMDGPUTargetLowering :: isFAbsFree ( EVT VT ) const { assert ( VT . isFloatingPoint ( ) ) ; return VT == MVT :: f32 || VT == MVT :: f64 ; } </s>

Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation .


<s> static bool required_extensions_p ( enum rvv_base_type type ) { return type == RVV_BASE_eew8_index || type == RVV_BASE_eew16_index || type == RVV_BASE_eew32_index || type == RVV_BASE_eew64_index || type == RVV_BASE_float_vector || type == RVV_BASE_double_trunc_float_vector || type == RVV_BASE_double_trunc_vector || type == RVV_BASE_widen_lmul1_vector || type == RVV_BASE_eew8_interpret || type == RVV_BASE_eew16_interpret || type == RVV_BASE_eew32_interpret || type == RVV_BASE_eew64_interpret || type == RVV_BASE_vlmul_ext_x2 || type == RVV_BASE_vlmul_ext_x4 || type == RVV_BASE_vlmul_ext_x8 || type == RVV_BASE_vlmul_ext_x16 || type == RVV_BASE_vlmul_ext_x32 || type == RVV_BASE_vlmul_ext_x64 ; } </s>

Return true if the type has required_extensions .


<s>
void
P2FrameLowering
::
determineCalleeSaves
(
MachineFunction
&
MF
,
BitVector
&
SavedRegs
,
RegScavenger
*
RS
)
const
{
LLVM_DEBUG
(
errs
(
)
<<
"=== Function: "
<<
MF
.
getName
(
)
<<
" ===\n"
)
;
LLVM_DEBUG
(
errs
(
)
<<
"Determining callee saves\n"
)
;
TargetFrameLowering
::
determineCalleeSaves
(
MF
,
SavedRegs
,
RS
)
;
}
</s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> static void query ( const MachineInstr & MI , AliasAnalysis & AA , bool & Read , bool & Write , bool & Effects , bool & StackPointer ) { assert ( ! MI . isTerminator ( ) ) ; if ( MI . isDebugInstr ( ) || MI . isPosition ( ) ) return ; if ( MI . mayLoad ( ) && ! MI . isDereferenceableInvariantLoad ( & AA ) ) Read = true ; if ( MI . mayStore ( ) ) { Write = true ; } else if ( MI . hasOrderedMemoryRef ( ) ) { switch ( MI . getOpcode ( ) ) { case WebAssembly :: DIV_S_I32 : case WebAssembly :: DIV_S_I64 : case WebAssembly :: REM_S_I32 : case WebAssembly :: REM_S_I64 : case WebAssembly :: DIV_U_I32 : case WebAssembly :: DIV_U_I64 : case WebAssembly :: REM_U_I32 : case WebAssembly :: REM_U_I64 : case WebAssembly :: I32_TRUNC_S_F32 : case WebAssembly :: I64_TRUNC_S_F32 : case WebAssembly :: I32_TRUNC_S_F64 : case WebAssembly :: I64_TRUNC_S_F64 : case WebAssembly :: I32_TRUNC_U_F32 : case WebAssembly :: I64_TRUNC_U_F32 : case WebAssembly :: I32_TRUNC_U_F64 : case WebAssembly :: I64_TRUNC_U_F64 : break ; default : if ( ! MI . isCall ( ) ) { Write = true ; Effects = true ; } break ; } } if ( MI . hasUnmodeledSideEffects ( ) ) { switch ( MI . getOpcode ( ) ) { case WebAssembly :: DIV_S_I32 : case WebAssembly :: DIV_S_I64 : case WebAssembly :: REM_S_I32 : case WebAssembly :: REM_S_I64 : case WebAssembly :: DIV_U_I32 : case WebAssembly :: DIV_U_I64 : case WebAssembly :: REM_U_I32 : case WebAssembly :: REM_U_I64 : case WebAssembly :: I32_TRUNC_S_F32 : case WebAssembly :: I64_TRUNC_S_F32 : case WebAssembly :: I32_TRUNC_S_F64 : case WebAssembly :: I64_TRUNC_S_F64 : case WebAssembly :: I32_TRUNC_U_F32 : case WebAssembly :: I64_TRUNC_U_F32 : case WebAssembly :: I32_TRUNC_U_F64 : case WebAssembly :: I64_TRUNC_U_F64 : break ; default : Effects = true ; break ; } } if ( ( MI . getOpcode ( ) == WebAssembly :: GLOBAL_SET_I32 || MI . getOpcode ( ) == WebAssembly :: GLOBAL_SET_I64 ) && strcmp ( MI . getOperand ( 0 ) . getSymbolName ( ) , "__stack_pointer" ) == 0 ) StackPointer = true ; if ( MI . isCall ( ) ) { queryCallee ( MI , Read , Write , Effects , StackPointer ) ; } } </s>

Query a line of the assigned virtual register matrix directly .


<s> static FRV_INLINE bool frv_small_data_reloc_p ( rtx symbol , int reloc ) { return ( GET_CODE ( symbol ) == SYMBOL_REF && SYMBOL_REF_SMALL_P ( symbol ) && ( ! TARGET_FDPIC || flag_pic == 1 ) && ( reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12 ) ) ; } </s>

Return true if SYMBOL is a small data symbol and relocation RELOC can be used to access it directly in a load or store .


<s> void Nios2TargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; } </s>

This method must be called before any actual lowering is done .


<s> bool SICTargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> int frv_emit_cond_move ( rtx dest , rtx test_rtx , rtx src1 , rtx src2 ) { rtx set ; rtx clobber_cc ; rtx test2 ; rtx cr_reg ; rtx if_rtx ; enum rtx_code test = GET_CODE ( test_rtx ) ; rtx cc_reg = frv_emit_comparison ( test , frv_compare_op0 , frv_compare_op1 ) ; enum machine_mode cc_mode = GET_MODE ( cc_reg ) ; if ( GET_CODE ( src1 ) == CONST_INT && GET_CODE ( src2 ) == CONST_INT ) { HOST_WIDE_INT value1 = INTVAL ( src1 ) ; HOST_WIDE_INT value2 = INTVAL ( src2 ) ; if ( value1 == 0 || value2 == 0 ) ; else if ( IN_RANGE_P ( value1 , - 2048 , 2047 ) && IN_RANGE_P ( value2 - value1 , - 2048 , 2047 ) ) ; else { src1 = force_reg ( GET_MODE ( dest ) , src1 ) ; src2 = force_reg ( GET_MODE ( dest ) , src2 ) ; } } else { if ( GET_CODE ( src1 ) == CONST_INT && INTVAL ( src1 ) != 0 ) src1 = force_reg ( GET_MODE ( dest ) , src1 ) ; if ( GET_CODE ( src2 ) == CONST_INT && INTVAL ( src2 ) != 0 ) src2 = force_reg ( GET_MODE ( dest ) , src2 ) ; } test2 = gen_rtx_fmt_ee ( test , cc_mode , cc_reg , const0_rtx ) ; if_rtx = gen_rtx_IF_THEN_ELSE ( GET_MODE ( dest ) , test2 , src1 , src2 ) ; set = gen_rtx_SET ( VOIDmode , dest , if_rtx ) ; cr_reg = ( ( TARGET_ALLOC_CC ) ? gen_reg_rtx ( CC_CCRmode ) : gen_rtx_REG ( CC_CCRmode , ( cc_mode == CC_FPmode ) ? FCR_FIRST : ICR_FIRST ) ) ; clobber_cc = gen_rtx_CLOBBER ( VOIDmode , cr_reg ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set , clobber_cc ) ) ) ; return TRUE ; } </s>

Emit the code for a conditional move , return TRUE if we could do the move .


<s> bool SITargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Align , bool * IsFast ) const { if ( IsFast ) * IsFast = false ; if ( ! VT . isSimple ( ) || VT == MVT :: Other ) return false ; if ( AddrSpace == AMDGPUAS :: LOCAL_ADDRESS ) { bool AlignedBy4 = ( Align % 4 == 0 ) ; if ( IsFast ) * IsFast = AlignedBy4 ; return AlignedBy4 ; } if ( VT . bitsLT ( MVT :: i32 ) ) return false ; if ( IsFast ) * IsFast = true ; return VT . bitsGT ( MVT :: i32 ) && Align % 4 == 0 ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s>
unsigned
MINA32MCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
assert
(
MO
.
isImm
(
)
&&
"did not expect relocated expression"
)
;
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> bool PPCTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( Ty -> isVectorTy ( ) && AM . BaseOffs != 0 ) return false ; if ( AM . BaseOffs <= - ( 1LL << 16 ) || AM . BaseOffs >= ( 1LL << 16 ) - 1 ) return false ; if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( AM . HasBaseReg && AM . BaseOffs ) return false ; break ; case 2 : if ( AM . HasBaseReg || AM . BaseOffs ) return false ; break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s>
unsigned
AArch64TargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
SelectionDAG
&
DAG
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"sp"
,
AArch64
::
SP
)
.
Case
(
"x1"
,
AArch64
::
X1
)
.
Case
(
"w1"
,
AArch64
::
W1
)
.
Case
(
"x2"
,
AArch64
::
X2
)
.
Case
(
"w2"
,
AArch64
::
W2
)
.
Case
(
"x3"
,
AArch64
::
X3
)
.
Case
(
"w3"
,
AArch64
::
W3
)
.
Case
(
"x4"
,
AArch64
::
X4
)
.
Case
(
"w4"
,
AArch64
::
W4
)
.
Case
(
"x5"
,
AArch64
::
X5
)
.
Case
(
"w5"
,
AArch64
::
W5
)
.
Case
(
"x6"
,
AArch64
::
X6
)
.
Case
(
"w6"
,
AArch64
::
W6
)
.
Case
(
"x7"
,
AArch64
::
X7
)
.
Case
(
"w7"
,
AArch64
::
W7
)
.
Case
(
"x18"
,
AArch64
::
X18
)
.
Case
(
"w18"
,
AArch64
::
W18
)
.
Case
(
"x20"
,
AArch64
::
X20
)
.
Case
(
"w20"
,
AArch64
::
W20
)
.
Default
(
0
)
;
if
(
(
(
Reg
==
AArch64
::
X1
||
Reg
==
AArch64
::
W1
)
&&
!
Subtarget
->
isXRegisterReserved
(
1
)
)
||
(
(
Reg
==
AArch64
::
X2
||
Reg
==
AArch64
::
W2
)
&&
!
Subtarget
->
isXRegisterReserved
(
2
)
)
||
(
(
Reg
==
AArch64
::
X3
||
Reg
==
AArch64
::
W3
)
&&
!
Subtarget
->
isXRegisterReserved
(
3
)
)
||
(
(
Reg
==
AArch64
::
X4
||
Reg
==
AArch64
::
W4
)
&&
!
Subtarget
->
isXRegisterReserved
(
4
)
)
||
(
(
Reg
==
AArch64
::
X5
||
Reg
==
AArch64
::
W5
)
&&
!
Subtarget
->
isXRegisterReserved
(
5
)
)
||
(
(
Reg
==
AArch64
::
X6
||
Reg
==
AArch64
::
W6
)
&&
!
Subtarget
->
isXRegisterReserved
(
6
)
)
||
(
(
Reg
==
AArch64
::
X7
||
Reg
==
AArch64
::
W7
)
&&
!
Subtarget
->
isXRegisterReserved
(
7
)
)
||
(
(
Reg
==
AArch64
::
X18
||
Reg
==
AArch64
::
W18
)
&&
!
Subtarget
->
isXRegisterReserved
(
18
)
)
||
(
(
Reg
==
AArch64
::
X20
||
Reg
==
AArch64
::
W20
)
&&
!
Subtarget
->
isXRegisterReserved
(
20
)
)
)
Reg
=
0
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
Twine
(
"Invalid register name \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;
}
</s>

Return the register ID of the name passed in .


<s>
bool
ARMAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNum
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
return
true
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNum
)
;
assert
(
MO
.
isReg
(
)
&&
"unexpected inline asm memory operand"
)
;
O
<<
"["
<<
getRegisterName
(
MO
.
getReg
(
)
)
<<
"]"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .

ARM
ARM
0
"unexpected inline asm memory operand"
"["
"]"


<s>
const
char
*
pa_output_parallel_movb
(
rtx
*
operands
,
rtx_insn
*
insn
)
{
int
length
=
get_attr_length
(
insn
)
;
if
(
length
==
4
)
return
"mov%I1b,tr %1,%0,%2"
;
if
(
length
==
8
)
{
if
(
dbr_sequence_length
(
)
==
0
)
{
if
(
GET_CODE
(
operands
[
1
]
)
==
CONST_INT
)
return
"b %2\n\tldi %1,%0"
;
else
return
"b %2\n\tcopy %1,%0"
;
}
else
{
if
(
GET_CODE
(
operands
[
1
]
)
==
CONST_INT
)
return
"ldi %1,%0\n\tb %2"
;
else
return
"copy %1,%0\n\tb %2"
;
}
}
if
(
GET_CODE
(
operands
[
1
]
)
==
CONST_INT
)
output_asm_insn
(
"ldi %1,%0"
,
operands
)
;
else
output_asm_insn
(
"copy %1,%0"
,
operands
)
;
return
pa_output_lbranch
(
operands
[
2
]
,
insn
,
1
)
;
}
</s>

Output an unconditional move and branch insn .


<s> static bool s390_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( ! TARGET_VX && VECTOR_NOFP_REGNO_P ( regno ) ) return false ; switch ( REGNO_REG_CLASS ( regno ) ) { case VEC_REGS : return ( ( GET_MODE_CLASS ( mode ) == MODE_INT && s390_class_max_nregs ( VEC_REGS , mode ) == 1 ) || mode == DFmode || ( TARGET_VXE && mode == SFmode ) || s390_vector_mode_supported_p ( mode ) ) ; break ; case FP_REGS : if ( TARGET_VX && ( ( GET_MODE_CLASS ( mode ) == MODE_INT && s390_class_max_nregs ( FP_REGS , mode ) == 1 ) || mode == DFmode || s390_vector_mode_supported_p ( mode ) ) ) return true ; if ( REGNO_PAIR_OK ( regno , mode ) ) { if ( mode == SImode || mode == DImode ) return true ; if ( FLOAT_MODE_P ( mode ) && GET_MODE_CLASS ( mode ) != MODE_VECTOR_FLOAT ) return true ; } break ; case ADDR_REGS : if ( FRAME_REGNO_P ( regno ) && mode == Pmode ) return true ; case GENERAL_REGS : if ( REGNO_PAIR_OK ( regno , mode ) ) { if ( TARGET_ZARCH || ( mode != TFmode && mode != TCmode && mode != TDmode ) ) return true ; } break ; case CC_REGS : if ( GET_MODE_CLASS ( mode ) == MODE_CC ) return true ; break ; case ACCESS_REGS : if ( REGNO_PAIR_OK ( regno , mode ) ) { if ( mode == SImode || mode == Pmode ) return true ; } break ; default : return false ; } return false ; } </s>

Return true if it is legal to put a value with MODE into REGNO .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Lanai Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> unsigned ARCompactRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return ARC :: FP ; } </s>


<s>
bool
AArch64InstrInfo
::
isCandidateToMergeOrPair
(
MachineInstr
&
MI
)
const
{
if
(
MI
.
hasOrderedMemoryRef
(
)
)
return
false
;
assert
(
MI
.
getOperand
(
1
)
.
isReg
(
)
&&
"Expected a reg operand."
)
;
if
(
!
MI
.
getOperand
(
2
)
.
isImm
(
)
)
return
false
;
unsigned
BaseReg
=
MI
.
getOperand
(
1
)
.
getReg
(
)
;
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
if
(
MI
.
modifiesRegister
(
BaseReg
,
TRI
)
)
return
false
;
if
(
isLdStPairSuppressed
(
MI
)
)
return
false
;
if
(
Subtarget
.
avoidQuadLdStPairs
(
)
)
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
AArch64
::
LDURQi
:
case
AArch64
::
STURQi
:
case
AArch64
::
LDRQui
:
case
AArch64
::
STRQui
:
return
false
;
}
}
return
true
;
}
</s>

Return true if this is a load/store that can be potentially paired/merged .


<s>
MachineInstr
*
PPCInstrInfo
::
commuteInstruction
(
MachineInstr
*
MI
,
bool
NewMI
)
const
{
MachineFunction
&
MF
=
*
MI
->
getParent
(
)
->
getParent
(
)
;
if
(
MI
->
getOpcode
(
)
!=
PPC
::
RLWIMI
)
return
TargetInstrInfo
::
commuteInstruction
(
MI
,
NewMI
)
;
if
(
MI
->
getOperand
(
3
)
.
getImm
(
)
!=
0
)
return
0
;
unsigned
Reg0
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
unsigned
Reg1
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
unsigned
Reg2
=
MI
->
getOperand
(
2
)
.
getReg
(
)
;
bool
Reg1IsKill
=
MI
->
getOperand
(
1
)
.
isKill
(
)
;
bool
Reg2IsKill
=
MI
->
getOperand
(
2
)
.
isKill
(
)
;
bool
ChangeReg0
=
false
;
if
(
Reg0
==
Reg1
)
{
assert
(
MI
->
getDesc
(
)
.
getOperandConstraint
(
0
,
MCOI
::
TIED_TO
)
&&
"Expecting a two-address instruction!"
)
;
Reg2IsKill
=
false
;
ChangeReg0
=
true
;
}
unsigned
MB
=
MI
->
getOperand
(
4
)
.
getImm
(
)
;
unsigned
ME
=
MI
->
getOperand
(
5
)
.
getImm
(
)
;
if
(
NewMI
)
{
unsigned
Reg0
=
ChangeReg0
Reg2
:
MI
->
getOperand
(
0
)
.
getReg
(
)
;
bool
Reg0IsDead
=
MI
->
getOperand
(
0
)
.
isDead
(
)
;
return
BuildMI
(
MF
,
MI
->
getDebugLoc
(
)
,
MI
->
getDesc
(
)
)
.
addReg
(
Reg0
,
RegState
::
Define
|
getDeadRegState
(
Reg0IsDead
)
)
.
addReg
(
Reg2
,
getKillRegState
(
Reg2IsKill
)
)
.
addReg
(
Reg1
,
getKillRegState
(
Reg1IsKill
)
)
.
addImm
(
(
ME
+
1
)
&
31
)
.
addImm
(
(
MB
1
)
&
31
)
;
}
if
(
ChangeReg0
)
MI
->
getOperand
(
0
)
.
setReg
(
Reg2
)
;
MI
->
getOperand
(
2
)
.
setReg
(
Reg1
)
;
MI
->
getOperand
(
1
)
.
setReg
(
Reg2
)
;
MI
->
getOperand
(
2
)
.
setIsKill
(
Reg1IsKill
)
;
MI
->
getOperand
(
1
)
.
setIsKill
(
Reg2IsKill
)
;
MI
->
getOperand
(
4
)
.
setImm
(
(
ME
+
1
)
&
31
)
;
MI
->
getOperand
(
5
)
.
setImm
(
(
MB
1
)
&
31
)
;
return
MI
;
}
</s>

This method commutes the operands of the given machine instruction MI .


<s> void MipsSEFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const MipsSEInstrInfo & TII = * static_cast < const MipsSEInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( 0 ) . getImm ( ) ; if ( I -> getOpcode ( ) == Mips :: ADJCALLSTACKDOWN ) Amount = - Amount ; unsigned SP = STI . isABI_N64 ( ) ? Mips :: SP_64 : Mips :: SP ; TII . adjustStackPtr ( SP , Amount , MBB , I ) ; } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

Mips Mips Mips Mips 0 Mips::ADJCALLSTACKDOWN Mips::SP_64 Mips::SP


<s> SDValue X86TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: VECTOR_SHUFFLE : return PerformShuffleCombine ( N , DAG , * this ) ; case ISD :: BUILD_VECTOR : return PerformBuildVectorCombine ( N , DAG , DCI , Subtarget , * this ) ; case ISD :: SELECT : return PerformSELECTCombine ( N , DAG , Subtarget ) ; case X86ISD :: CMOV : return PerformCMOVCombine ( N , DAG , DCI ) ; case ISD :: MUL : return PerformMulCombine ( N , DAG , DCI ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DAG , Subtarget ) ; case ISD :: STORE : return PerformSTORECombine ( N , DAG , Subtarget ) ; case X86ISD :: FXOR : case X86ISD :: FOR : return PerformFORCombine ( N , DAG ) ; case X86ISD :: FAND : return PerformFANDCombine ( N , DAG ) ; case X86ISD :: BT : return PerformBTCombine ( N , DAG , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> bool AMDGPUDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < AMDGPUSubtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> static void pru_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { int regi = pru_function_arg_regi ( cum_v , arg . mode , arg . type , arg . named ) ; if ( regi >= 0 ) pru_function_arg_regi_mark_slot ( regi , cum_v , arg . mode , arg . type , arg . named ) ; } </s>

Update the data in CUM to advance over argument ARG .


<s> bool isMem ( ) const { return Kind == k_Memri ; } </s>


<s> rtx rs6000_emit_eqne ( machine_mode mode , rtx op1 , rtx op2 , rtx scratch ) { if ( op2 == const0_rtx ) return op1 ; if ( GET_CODE ( scratch ) == SCRATCH ) scratch = gen_reg_rtx ( mode ) ; if ( logical_operand ( op2 , mode ) ) emit_insn ( gen_rtx_SET ( scratch , gen_rtx_XOR ( mode , op1 , op2 ) ) ) ; else emit_insn ( gen_rtx_SET ( scratch , gen_rtx_PLUS ( mode , op1 , negate_rtx ( mode , op2 ) ) ) ) ; return scratch ; } </s>

Emit RTL that sets a register to zero if OP1 and OP2 are equal . SCRATCH can be used as that dest register . Return the dest register .


<s> static void csky_layout_stack_frame ( void ) { machine_function * infp = cfun -> machine ; int reg_count ; if ( infp -> frame_init_p ) return ; infp -> outbound_size = CSKY_STACK_ALIGN ( crtl -> outgoing_args_size ) ; infp -> local_offset = infp -> outbound_size ; infp -> local_size = CSKY_STACK_ALIGN ( get_frame_size ( ) ) ; infp -> reg_offset = infp -> local_offset + infp -> local_size ; infp -> reg_mask = get_csky_live_regs ( & reg_count ) ; infp -> reg_size = reg_count * UNITS_PER_WORD ; infp -> arg_offset = infp -> reg_offset + infp -> reg_size ; infp -> arg_size = crtl -> args . pretend_args_size ; infp -> frame_size = infp -> arg_offset + infp -> arg_size ; infp -> frame_init_p = reload_completed ; } </s>

Compute the stack frame layout , storing sizes of the various pieces in cfun- > machine . Stack frames constructed in the prologue look like : ... caller 's frame ... incoming SP - > caller 's outbound argument overflow argument spill optional FP - > register save local variables alloca ( ) space adjusted SP - > outbound argument overflow with SP/FP pointing at the base ( low address ) of the respective area , and each area aligned to a word boundary .


<s> bool ARM64TargetLowering :: isFMAFasterThanFMulAndFAdd ( EVT VT ) const { VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f32 : case MVT :: f64 : return true ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> rtx_insn * s390_emit_call ( rtx addr_location , rtx tls_call , rtx result_reg , rtx retaddr_reg ) { bool plt_call = false ; rtx_insn * insn ; rtx vec [ 4 ] = { NULL_RTX } ; int elts = 0 ; rtx * call = & vec [ 0 ] ; rtx * clobber_ret_reg = & vec [ 1 ] ; rtx * use = & vec [ 2 ] ; rtx * clobber_thunk_reg = & vec [ 3 ] ; int i ; if ( GET_CODE ( addr_location ) == SYMBOL_REF ) { if ( flag_pic && ! SYMBOL_REF_LOCAL_P ( addr_location ) ) { if ( TARGET_64BIT || retaddr_reg != NULL_RTX ) { addr_location = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , addr_location ) , UNSPEC_PLT ) ; addr_location = gen_rtx_CONST ( Pmode , addr_location ) ; plt_call = true ; } else addr_location = force_reg ( Pmode , addr_location ) ; } if ( ! TARGET_SMALL_EXEC && ! TARGET_CPU_ZARCH ) { if ( flag_pic ) addr_location = legitimize_pic_address ( addr_location , 0 ) ; else addr_location = force_reg ( Pmode , addr_location ) ; } } if ( retaddr_reg == NULL_RTX && GET_CODE ( addr_location ) != SYMBOL_REF && ! plt_call ) { emit_move_insn ( gen_rtx_REG ( Pmode , SIBCALL_REGNUM ) , addr_location ) ; addr_location = gen_rtx_REG ( Pmode , SIBCALL_REGNUM ) ; } if ( TARGET_INDIRECT_BRANCH_NOBP_CALL && GET_CODE ( addr_location ) != SYMBOL_REF && ! plt_call ) { addr_location = force_reg ( Pmode , addr_location ) ; if ( ! TARGET_CPU_Z10 ) { * clobber_thunk_reg = gen_rtx_REG ( Pmode , INDIRECT_BRANCH_THUNK_REGNUM ) ; * clobber_thunk_reg = gen_rtx_CLOBBER ( VOIDmode , * clobber_thunk_reg ) ; } } addr_location = gen_rtx_MEM ( QImode , addr_location ) ; * call = gen_rtx_CALL ( VOIDmode , addr_location , const0_rtx ) ; if ( result_reg != NULL_RTX ) * call = gen_rtx_SET ( result_reg , * call ) ; if ( retaddr_reg != NULL_RTX ) { * clobber_ret_reg = gen_rtx_CLOBBER ( VOIDmode , retaddr_reg ) ; if ( tls_call != NULL_RTX ) * use = gen_rtx_USE ( VOIDmode , tls_call ) ; } for ( i = 0 ; i < 4 ; i ++ ) if ( vec [ i ] != NULL_RTX ) elts ++ ; if ( elts > 1 ) { rtvec v ; int e = 0 ; v = rtvec_alloc ( elts ) ; for ( i = 0 ; i < 4 ; i ++ ) if ( vec [ i ] != NULL_RTX ) { RTVEC_ELT ( v , e ) = vec [ i ] ; e ++ ; } * call = gen_rtx_PARALLEL ( VOIDmode , v ) ; } insn = emit_call_insn ( * call ) ; if ( ( ! TARGET_64BIT && plt_call ) || tls_call != NULL_RTX ) { gcc_assert ( retaddr_reg != NULL_RTX ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , gen_rtx_REG ( Pmode , 12 ) ) ; } return insn ; } </s>

This function is used by the call expanders of the machine description . It emits the call insn itself together with the necessary operations to adjust the target address and returns the emitted insn . ADDR_LOCATION is the target address rtx TLS_CALL the location of the thread-local symbol RESULT_REG the register where the result of the call should be stored RETADDR_REG the register where the return address should be stored If this parameter is NULL_RTX the call is considered to be a sibling call .


<s> bool isReg ( ) const { return Kind == k_Reg ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addRequired < ReachingDefAnalysis > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
bool
AArch64A53Fix835769
::
runOnMachineFunction
(
MachineFunction
&
F
)
{
DEBUG
(
dbgs
(
)
<<
"***** AArch64A53Fix835769 *****\n"
)
;
bool
Changed
=
false
;
TII
=
F
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
for
(
auto
&
MBB
:
F
)
{
Changed
|=
runOnBasicBlock
(
MBB
)
;
}
return
Changed
;
}
</s>


<s> SDValue TOYTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BR_CC : return LowerBR_CC ( Op , DAG ) ; } } </s>

LowerOperation - Provide custom lowering hooks for some operations .


"All AArch64 cmps should have 2 operands"

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> const DataLayout * getDataLayout ( ) const override { return getSubtargetImpl ( ) -> getDataLayout ( ) ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> ISD :: NodeType getExtendForAtomicCmpSwapArg ( ) const override { return ISD :: SIGN_EXTEND ; } </s>

Returns how the platform 's atomic compare and swap expects its comparison value to be extended ( ZERO_EXTEND , SIGN_EXTEND , or ANY_EXTEND ) .


<s> void generate_6432_conversion ( rtx target , rtx sub_result ) { if ( TARGET_64BIT ) { rtx tmp_reg_ca = gen_reg_rtx ( DImode ) ; emit_insn ( gen_subfdi3_carry_in_xx ( tmp_reg_ca ) ) ; rtx popcnt = gen_reg_rtx ( DImode ) ; emit_insn ( gen_popcntddi2 ( popcnt , sub_result ) ) ; rtx tmp2 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_iordi3 ( tmp2 , popcnt , tmp_reg_ca ) ) ; emit_insn ( gen_movsi ( target , gen_lowpart ( SImode , tmp2 ) ) ) ; } else { rtx tmp_reg_ca = gen_reg_rtx ( SImode ) ; emit_insn ( gen_subfsi3_carry_in_xx ( tmp_reg_ca ) ) ; rtx popcnt = gen_reg_rtx ( SImode ) ; emit_insn ( gen_popcntdsi2 ( popcnt , sub_result ) ) ; emit_insn ( gen_iorsi3 ( target , popcnt , tmp_reg_ca ) ) ; } } </s>

Generate code to convert a DImode-plus-carry subtract result into a SImode result that has the same < 0 / ==0 / > 0 properties to produce the final result from memcmp . TARGET is the rtx for the register to receive the memcmp result . SUB_RESULT is the rtx for the register contining the subtract result .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Hexagon NewValueJump"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> SDValue MSP430TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; AnalyzeReturnValues ( CCInfo , RVLocs , Ins ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s>
static
rtx
avr_addr_space_convert
(
rtx
src
,
tree
type_from
,
tree
type_to
)
{
addr_space_t
as_from
=
TYPE_ADDR_SPACE
(
TREE_TYPE
(
type_from
)
)
;
addr_space_t
as_to
=
TYPE_ADDR_SPACE
(
TREE_TYPE
(
type_to
)
)
;
if
(
avr_log
.
progmem
)
avr_edump
(
"\n%!: op = %r\nfrom = %t\nto = %t\n"
,
src
,
type_from
,
type_to
)
;
if
(
as_from
!=
ADDR_SPACE_MEMX
&&
as_to
==
ADDR_SPACE_MEMX
)
{
int
msb
;
rtx
sym
=
src
;
rtx
reg
=
gen_reg_rtx
(
PSImode
)
;
while
(
CONST
==
GET_CODE
(
sym
)
||
PLUS
==
GET_CODE
(
sym
)
)
sym
=
XEXP
(
sym
,
0
)
;
if
(
SYMBOL_REF_P
(
sym
)
&&
ADDR_SPACE_FLASH
==
AVR_SYMBOL_GET_ADDR_SPACE
(
sym
)
)
{
as_from
=
ADDR_SPACE_FLASH
;
}
msb
=
ADDR_SPACE_GENERIC_P
(
as_from
)
0x80
:
avr_addrspace
[
as_from
]
.
segment
;
src
=
force_reg
(
Pmode
,
src
)
;
emit_insn
(
msb
==
0
gen_zero_extendhipsi2
(
reg
,
src
)
:
gen_n_extendhipsi2
(
reg
,
gen_int_mode
(
msb
,
QImode
)
,
src
)
)
;
return
reg
;
}
if
(
as_from
==
ADDR_SPACE_MEMX
&&
as_to
!=
ADDR_SPACE_MEMX
)
{
rtx
new_src
=
gen_reg_rtx
(
Pmode
)
;
src
=
force_reg
(
PSImode
,
src
)
;
emit_move_insn
(
new_src
,
simplify_gen_subreg
(
Pmode
,
src
,
PSImode
,
0
)
)
;
return
new_src
;
}
return
src
;
}
</s>

Implement ` TARGET_ADDR_SPACE_CONVERT ' .


Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> static void rs6000_output_dwarf_dtprel ( FILE * file , int size , rtx x ) { switch ( size ) { case 4 : fputs ( "\t.long\t" , file ) ; break ; case 8 : fputs ( DOUBLE_INT_ASM_OP , file ) ; break ; default : gcc_unreachable ( ) ; } output_addr_const ( file , x ) ; fputs ( "@dtprel+0x8000" , file ) ; } </s>

This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL . We need to emit DTP-relative relocations .


<s> static unsigned getHashValue ( const CvtDirection & Val ) { return ( Val . SourceType ^ Val . DestinationType ) * 37U ; } </s>

Using name and line to get hash value . It should already be mostly unique .


<s> static bool arc_use_anchors_for_symbol_p ( const_rtx symbol ) { if ( SYMBOL_REF_TLS_MODEL ( symbol ) ) return false ; if ( flag_pic ) return false ; if ( SYMBOL_REF_SMALL_P ( symbol ) ) return false ; return default_use_anchors_for_symbol_p ( symbol ) ; } </s>

Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P . We do n't want to use anchors for small data : the GP register acts as an anchor in that case . We also do n't want to use them for PC-relative accesses , where the PC acts as an anchor . Prohibit also TLS symbols to use anchors .


<s> inline machine_mode function_expander :: vector_mode ( void ) const { return TYPE_MODE ( builtin_types [ type . index ] . vector ) ; } </s>

Return the machine_mode of the corresponding vector type .


"getJumpTargetOpValue expects only expressions"

getJumpTargetOpValue - Return binary encoding of the jump target operand .


<s>
MachineBasicBlock
*
AVRTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
MBB
)
const
{
int
Opc
=
MI
.
getOpcode
(
)
;
switch
(
Opc
)
{
case
AVR
::
Lsl8
:
case
AVR
::
Lsl16
:
case
AVR
::
Lsr8
:
case
AVR
::
Lsr16
:
case
AVR
::
Asr8
:
case
AVR
::
Asr16
:
return
insertShift
(
MI
,
MBB
)
;
case
AVR
::
MULRdRr
:
case
AVR
::
MULSRdRr
:
return
insertMul
(
MI
,
MBB
)
;
}
assert
(
(
Opc
==
AVR
::
Select16
||
Opc
==
AVR
::
Select8
)
&&
"Unexpected instr type to insert"
)
;
const
AVRInstrInfo
&
TII
=
(
const
AVRInstrInfo
&
)
*
MI
.
getParent
(
)
->
getParent
(
)
->
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
dl
=
MI
.
getDebugLoc
(
)
;
MachineFunction
*
MF
=
MBB
->
getParent
(
)
;
const
BasicBlock
*
LLVM_BB
=
MBB
->
getBasicBlock
(
)
;
MachineBasicBlock
*
trueMBB
=
MF
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
falseMBB
=
MF
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineFunction
::
iterator
I
=
MBB
->
getParent
(
)
->
begin
(
)
;
++
I
;
MF
->
insert
(
I
,
trueMBB
)
;
MF
->
insert
(
I
,
falseMBB
)
;
trueMBB
->
splice
(
trueMBB
->
begin
(
)
,
MBB
,
std
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
MBB
->
end
(
)
)
;
trueMBB
->
transferSuccessorsAndUpdatePHIs
(
MBB
)
;
AVRCC
::
CondCodes
CC
=
(
AVRCC
::
CondCodes
)
MI
.
getOperand
(
3
)
.
getImm
(
)
;
BuildMI
(
MBB
,
dl
,
TII
.
getBrCond
(
CC
)
)
.
addMBB
(
trueMBB
)
;
BuildMI
(
MBB
,
dl
,
TII
.
get
(
AVR
::
RJMPk
)
)
.
addMBB
(
falseMBB
)
;
MBB
->
addSuccessor
(
falseMBB
)
;
MBB
->
addSuccessor
(
trueMBB
)
;
BuildMI
(
falseMBB
,
dl
,
TII
.
get
(
AVR
::
RJMPk
)
)
.
addMBB
(
trueMBB
)
;
falseMBB
->
addSuccessor
(
trueMBB
)
;
BuildMI
(
*
trueMBB
,
trueMBB
->
begin
(
)
,
dl
,
TII
.
get
(
AVR
::
PHI
)
,
MI
.
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
.
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
MBB
)
.
addReg
(
MI
.
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
falseMBB
)
;
MI
.
eraseFromParent
(
)
;
return
trueMBB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s>
MachineBasicBlock
::
iterator
AVRFrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
)
const
{
const
AVRSubtarget
&
STI
=
MF
.
getSubtarget
<
AVRSubtarget
>
(
)
;
const
TargetFrameLowering
&
TFI
=
*
STI
.
getFrameLowering
(
)
;
const
AVRInstrInfo
&
TII
=
*
STI
.
getInstrInfo
(
)
;
if
(
TFI
.
hasReservedCallFrame
(
MF
)
)
{
fixStackStores
(
MBB
,
MI
,
TII
,
false
)
;
return
MBB
.
erase
(
MI
)
;
}
DebugLoc
DL
=
MI
->
getDebugLoc
(
)
;
unsigned
int
Opcode
=
MI
->
getOpcode
(
)
;
int
Amount
=
TII
.
getFrameSize
(
*
MI
)
;
if
(
Amount
!=
0
)
{
assert
(
TFI
.
getStackAlignment
(
)
==
1
&&
"Unsupported stack alignment"
)
;
if
(
Opcode
==
TII
.
getCallFrameSetupOpcode
(
)
)
{
fixStackStores
(
MBB
,
MI
,
TII
,
true
)
;
}
else
{
assert
(
Opcode
==
TII
.
getCallFrameDestroyOpcode
(
)
)
;
unsigned
addOpcode
;
if
(
isUInt
<
6
>
(
Amount
)
)
{
addOpcode
=
AVR
::
ADIWRdK
;
}
else
{
addOpcode
=
AVR
::
SUBIWRdK
;
Amount
=
Amount
;
}
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
SPREAD
)
,
AVR
::
R31R30
)
.
addReg
(
AVR
::
SP
)
;
MachineInstr
*
New
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
addOpcode
)
,
AVR
::
R31R30
)
.
addReg
(
AVR
::
R31R30
,
RegState
::
Kill
)
.
addImm
(
Amount
)
;
New
->
getOperand
(
3
)
.
setIsDead
(
)
;
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
SPWRITE
)
,
AVR
::
SP
)
.
addReg
(
AVR
::
R31R30
,
RegState
::
Kill
)
;
}
}
return
MBB
.
erase
(
MI
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool AVRTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; auto CCFunction = CCAssignFnForReturn ( CallConv ) ; return CCInfo . CheckReturn ( Outs , CCFunction ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> virtual const DataLayout * getDataLayout ( ) const { return & DL ; } </s>


<s> void Thumb2RegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , unsigned PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: t2LDRpci ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( ( int64_t ) ARMCC :: AL ) . addReg ( 0 ) . setMIFlags ( MIFlags ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s> bool R600InstrInfo :: PredicateInstruction ( MachineInstr & MI , ArrayRef < MachineOperand > Pred ) const { int PIdx = MI . findFirstPredOperandIdx ( ) ; if ( MI . getOpcode ( ) == R600 :: CF_ALU ) { MI . getOperand ( 8 ) . setImm ( 0 ) ; return true ; } if ( MI . getOpcode ( ) == R600 :: DOT_4 ) { MI . getOperand ( getOperandIdx ( MI , R600 :: OpName :: pred_sel_X ) ) . setReg ( Pred [ 2 ] . getReg ( ) ) ; MI . getOperand ( getOperandIdx ( MI , R600 :: OpName :: pred_sel_Y ) ) . setReg ( Pred [ 2 ] . getReg ( ) ) ; MI . getOperand ( getOperandIdx ( MI , R600 :: OpName :: pred_sel_Z ) ) . setReg ( Pred [ 2 ] . getReg ( ) ) ; MI . getOperand ( getOperandIdx ( MI , R600 :: OpName :: pred_sel_W ) ) . setReg ( Pred [ 2 ] . getReg ( ) ) ; MachineInstrBuilder MIB ( * MI . getParent ( ) -> getParent ( ) , MI ) ; MIB . addReg ( R600 :: PREDICATE_BIT , RegState :: Implicit ) ; return true ; } if ( PIdx != - 1 ) { MachineOperand & PMO = MI . getOperand ( PIdx ) ; PMO . setReg ( Pred [ 2 ] . getReg ( ) ) ; MachineInstrBuilder MIB ( * MI . getParent ( ) -> getParent ( ) , MI ) ; MIB . addReg ( R600 :: PREDICATE_BIT , RegState :: Implicit ) ; return true ; } return false ; } </s>

Convert the instruction into a predicated instruction .


<s> bool SIWholeQuadMode :: runOnMachineFunction ( MachineFunction & MF ) { Instructions . clear ( ) ; Blocks . clear ( ) ; LiveMaskQueries . clear ( ) ; LowerToCopyInstrs . clear ( ) ; CallingConv = MF . getFunction ( ) . getCallingConv ( ) ; ST = & MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST -> getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; LIS = & getAnalysis < LiveIntervals > ( ) ; char GlobalFlags = analyzeFunction ( MF ) ; unsigned LiveMaskReg = 0 ; unsigned Exec = ST -> isWave32 ( ) ? AMDGPU :: EXEC_LO : AMDGPU :: EXEC ; if ( ! ( GlobalFlags & StateWQM ) ) { lowerLiveMaskQueries ( Exec ) ; if ( ! ( GlobalFlags & StateWWM ) ) return ! LiveMaskQueries . empty ( ) ; } else { MachineBasicBlock & Entry = MF . front ( ) ; MachineBasicBlock :: iterator EntryMI = Entry . getFirstNonPHI ( ) ; if ( GlobalFlags & StateExact || ! LiveMaskQueries . empty ( ) ) { LiveMaskReg = MRI -> createVirtualRegister ( TRI -> getBoolRC ( ) ) ; MachineInstr * MI = BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( AMDGPU :: COPY ) , LiveMaskReg ) . addReg ( Exec ) ; LIS -> InsertMachineInstrInMaps ( * MI ) ; } lowerLiveMaskQueries ( LiveMaskReg ) ; if ( GlobalFlags == StateWQM ) { BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( ST -> isWave32 ( ) ? AMDGPU :: S_WQM_B32 : AMDGPU :: S_WQM_B64 ) , Exec ) . addReg ( Exec ) ; lowerCopyInstrs ( ) ; return true ; } } LLVM_DEBUG ( printInfo ( ) ) ; lowerCopyInstrs ( ) ; for ( auto BII : Blocks ) processBlock ( * BII . first , LiveMaskReg , BII . first == & * MF . begin ( ) ) ; LIS -> removeRegUnit ( * MCRegUnitIterator ( AMDGPU :: SCC , TRI ) ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> MVT getScalarShiftAmountTy ( EVT LHSTy ) const override { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> static bool mep_repeat_loop_p ( struct mep_doloop * loop ) { struct mep_doloop_end * end ; rtx fallthrough ; if ( loop -> begin == 0 || loop -> end == 0 || loop -> begin -> next != 0 ) return false ; if ( prev_real_insn ( loop -> end -> label ) != loop -> begin -> insn ) return false ; fallthrough = loop -> end -> fallthrough ; for ( end = loop -> end -> next ; end != 0 ; end = end -> next ) if ( end -> label != loop -> end -> label || ! simplejump_p ( end -> fallthrough ) || next_real_insn ( JUMP_LABEL ( end -> fallthrough ) ) != fallthrough ) return false ; return true ; } </s>

Return true if LOOP can be converted into repeat/repeat_end form ( that is , if it matches cases ( 1 ) or ( 2 ) above ) .


<s>
void
SystemZMCAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
)
const
{
MCFixupKind
Kind
=
Fixup
.
getKind
(
)
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
unsigned
BitSize
=
getFixupKindInfo
(
Kind
)
.
TargetSize
;
unsigned
Size
=
(
BitSize
+
7
)
/
8
;
assert
(
Offset
+
Size
<=
DataSize
&&
"Invalid fixup offset!"
)
;
Value
=
extractBitsForFixup
(
Kind
,
Value
)
;
if
(
BitSize
<
64
)
Value
&=
(
(
uint64_t
)
1
<<
BitSize
)
1
;
unsigned
ShiftValue
=
(
Size
*
8
)
8
;
for
(
unsigned
I
=
0
;
I
!=
Size
;
++
I
)
{
Data
[
Offset
+
I
]
|=
uint8_t
(
Value
>>
ShiftValue
)
;
ShiftValue
-=
8
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static HOST_WIDE_INT aarch64_simd_vector_alignment ( const_tree type ) { if ( GET_MODE_CLASS ( TYPE_MODE ( type ) ) == MODE_VECTOR_BOOL ) return 16 ; widest_int min_size = constant_lower_bound ( wi :: to_poly_widest ( TYPE_SIZE ( type ) ) ) ; return wi :: umin ( min_size , 128 ) . to_uhwi ( ) ; } </s>

Implement target hook TARGET_VECTOR_ALIGNMENT . The AAPCS64 sets the maximum alignment of a vector to 128 bits .


<s>
static
void
*
cygwin_gt_pch_get_address
(
size_t
sz
,
int
fd
)
{
void
*
base
;
off_t
p
=
lseek
(
fd
,
0
,
SEEK_CUR
)
;
if
(
p
==
(
off_t
)
1
)
fatal_error
(
"can't get position in PCH file: %m"
)
;
if
(
(
size_t
)
p
<
sz
)
{
if
(
ftruncate
(
fd
,
sz
)
==
1
)
fatal_error
(
"can't extend PCH file: %m"
)
;
}
base
=
mmap
(
,
sz
,
PROT_READ
|
PROT_WRITE
,
MAP_PRIVATE
,
fd
,
0
)
;
if
(
base
==
MAP_FAILED
)
base
=
;
else
munmap
(
base
,
sz
)
;
if
(
lseek
(
fd
,
p
,
SEEK_SET
)
==
(
off_t
)
1
)
fatal_error
(
"can't set position in PCH file: %m"
)
;
return
base
;
}
</s>

Identify an address that 's likely to be free in a subsequent invocation of the compiler . The area should be able to hold SIZE bytes . FD is an open file descriptor if the host would like to probe with mmap .


<s> static Mnode * add_minipool_forward_ref ( Mfix * fix ) { Mnode * max_mp = NULL ; HOST_WIDE_INT max_address = fix -> address + fix -> forwards ; Mnode * mp ; if ( minipool_vector_head && fix -> address >= minipool_vector_head -> max_address - fix -> fix_size ) return NULL ; for ( mp = minipool_vector_head ; mp != NULL ; mp = mp -> next ) { if ( GET_CODE ( fix -> value ) == GET_CODE ( mp -> value ) && fix -> mode == mp -> mode && ( GET_CODE ( fix -> value ) != CODE_LABEL || ( CODE_LABEL_NUMBER ( fix -> value ) == CODE_LABEL_NUMBER ( mp -> value ) ) ) && rtx_equal_p ( fix -> value , mp -> value ) ) { mp -> refcount ++ ; return move_minipool_fix_forward_ref ( mp , max_mp , max_address ) ; } if ( max_mp == NULL && mp -> max_address > max_address ) max_mp = mp ; if ( ARM_DOUBLEWORD_ALIGN && max_mp == NULL && fix -> fix_size == 8 && mp -> fix_size != 8 ) { max_mp = mp ; max_address = mp -> max_address ; } } mp = xmalloc ( sizeof ( * mp ) ) ; mp -> fix_size = fix -> fix_size ; mp -> mode = fix -> mode ; mp -> value = fix -> value ; mp -> refcount = 1 ; mp -> min_address = - 65536 ; if ( max_mp == NULL ) { mp -> max_address = max_address ; mp -> next = NULL ; mp -> prev = minipool_vector_tail ; if ( mp -> prev == NULL ) { minipool_vector_head = mp ; minipool_vector_label = gen_label_rtx ( ) ; } else mp -> prev -> next = mp ; minipool_vector_tail = mp ; } else { if ( max_address > max_mp -> max_address - mp -> fix_size ) mp -> max_address = max_mp -> max_address - mp -> fix_size ; else mp -> max_address = max_address ; mp -> next = max_mp ; mp -> prev = max_mp -> prev ; max_mp -> prev = mp ; if ( mp -> prev != NULL ) mp -> prev -> next = mp ; else minipool_vector_head = mp ; } max_mp = mp ; while ( mp -> prev != NULL && mp -> prev -> max_address > mp -> max_address - mp -> prev -> fix_size ) { mp -> prev -> max_address = mp -> max_address - mp -> prev -> fix_size ; mp = mp -> prev ; } return max_mp ; } </s>

Add a constant to the minipool for a forward reference . Returns the node added or NULL if the constant will not fit in this pool .


"********* Hexagon Hardware Loops *********\n"


<s> rtx mips_subword ( rtx op , bool high_p ) { unsigned int byte , offset ; machine_mode mode ; mode = GET_MODE ( op ) ; if ( mode == VOIDmode ) mode = TARGET_64BIT ? TImode : DImode ; if ( TARGET_BIG_ENDIAN ? ! high_p : high_p ) byte = UNITS_PER_WORD ; else byte = 0 ; if ( FP_REG_RTX_P ( op ) ) { offset = ( UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0 ) ; return gen_rtx_REG ( word_mode , REGNO ( op ) + offset ) ; } if ( MEM_P ( op ) ) return mips_rewrite_small_data ( adjust_address ( op , word_mode , byte ) ) ; return simplify_gen_subreg ( word_mode , op , mode , byte ) ; } </s>

Return one word of double-word value OP , taking into account the fixed endianness of certain registers . HIGH_P is true to select the high part , false to select the low part .


<s> static rtx mips_return_fpr_single ( machine_mode type_mode , machine_mode value_mode ) { rtx x ; x = gen_rtx_REG ( value_mode , FP_RETURN ) ; if ( type_mode != value_mode ) { x = gen_rtx_EXPR_LIST ( VOIDmode , x , const0_rtx ) ; x = gen_rtx_PARALLEL ( type_mode , gen_rtvec ( 1 , x ) ) ; } return x ; } </s>

Return the representation of an FPR return register when the value being returned in FP_RETURN has mode VALUE_MODE and the return type itself has mode TYPE_MODE . On NewABI targets , the two modes may be different for structures like : struct __attribute__ ( ( packed ) ) foo { float f ; } where we return the SFmode value of `` f '' in FP_RETURN , but where the structure itself has mode BLKmode .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addRequired < ScalarEvolution > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> unsigned PPCRegisterInfo :: getFrameRegister ( MachineFunction & MF ) const { if ( ! Subtarget . isPPC64 ( ) ) return hasFP ( MF ) ? PPC :: R31 : PPC :: R1 ; else return hasFP ( MF ) ? PPC :: X31 : PPC :: X1 ; } </s>


<s> int AMDGPUFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; FrameReg = RI -> getFrameRegister ( MF ) ; unsigned OffsetBytes = 2 * ( getStackWidth ( MF ) * 4 ) ; int UpperBound = FI == - 1 ? MFI -> getNumObjects ( ) : FI ; for ( int i = MFI -> getObjectIndexBegin ( ) ; i < UpperBound ; ++ i ) { OffsetBytes = RoundUpToAlignment ( OffsetBytes , MFI -> getObjectAlignment ( i ) ) ; OffsetBytes += MFI -> getObjectSize ( i ) ; OffsetBytes = RoundUpToAlignment ( OffsetBytes , 4 ) ; } if ( FI != - 1 ) OffsetBytes = RoundUpToAlignment ( OffsetBytes , MFI -> getObjectAlignment ( FI ) ) ; return OffsetBytes / ( getStackWidth ( MF ) * 4 ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s>
MachineInstr
*
LanaiInstrInfo
::
optimizeSelect
(
MachineInstr
&
MI
,
SmallPtrSetImpl
<
MachineInstr
*
>
&
SeenMIs
,
bool
)
const
{
assert
(
MI
.
getOpcode
(
)
==
Lanai
::
SELECT
&&
"unknown select instruction"
)
;
MachineRegisterInfo
&
MRI
=
MI
.
getParent
(
)
->
getParent
(
)
->
getRegInfo
(
)
;
MachineInstr
*
DefMI
=
canFoldIntoSelect
(
MI
.
getOperand
(
1
)
.
getReg
(
)
,
MRI
)
;
bool
Invert
=
!
DefMI
;
if
(
!
DefMI
)
DefMI
=
canFoldIntoSelect
(
MI
.
getOperand
(
2
)
.
getReg
(
)
,
MRI
)
;
if
(
!
DefMI
)
return
nullptr
;
MachineOperand
FalseReg
=
MI
.
getOperand
(
Invert
1
:
2
)
;
unsigned
DestReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
const
TargetRegisterClass
*
PreviousClass
=
MRI
.
getRegClass
(
FalseReg
.
getReg
(
)
)
;
if
(
!
MRI
.
constrainRegClass
(
DestReg
,
PreviousClass
)
)
return
nullptr
;
MachineInstrBuilder
NewMI
=
BuildMI
(
*
MI
.
getParent
(
)
,
MI
,
MI
.
getDebugLoc
(
)
,
DefMI
->
getDesc
(
)
,
DestReg
)
;
const
MCInstrDesc
&
DefDesc
=
DefMI
->
getDesc
(
)
;
for
(
unsigned
i
=
1
,
e
=
DefDesc
.
getNumOperands
(
)
;
i
!=
e
&&
!
DefDesc
.
OpInfo
[
i
]
.
isPredicate
(
)
;
++
i
)
NewMI
.
addOperand
(
DefMI
->
getOperand
(
i
)
)
;
unsigned
CondCode
=
MI
.
getOperand
(
3
)
.
getImm
(
)
;
if
(
Invert
)
NewMI
.
addImm
(
getOppositeCondition
(
LPCC
::
CondCode
(
CondCode
)
)
)
;
else
NewMI
.
addImm
(
CondCode
)
;
NewMI
.
copyImplicitOps
(
MI
)
;
FalseReg
.
setImplicit
(
)
;
NewMI
.
addOperand
(
FalseReg
)
;
NewMI
->
tieOperands
(
0
,
NewMI
->
getNumOperands
(
)
1
)
;
SeenMIs
.
insert
(
NewMI
)
;
SeenMIs
.
erase
(
DefMI
)
;
if
(
DefMI
->
getParent
(
)
!=
MI
.
getParent
(
)
)
NewMI
->
clearKillInfo
(
)
;
DefMI
->
eraseFromParent
(
)
;
return
NewMI
;
}
</s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


<s> bool SITargetLowering :: getAddrModeArguments ( IntrinsicInst * II , SmallVectorImpl < Value * > & Ops , Type * & AccessTy ) const { switch ( II -> getIntrinsicID ( ) ) { case Intrinsic :: amdgcn_atomic_inc : case Intrinsic :: amdgcn_atomic_dec : { Value * Ptr = II -> getArgOperand ( 0 ) ; AccessTy = II -> getType ( ) ; Ops . push_back ( Ptr ) ; return true ; } default : return false ; } } </s>

CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address .


<s> unsigned getMappedIdxOpcForImmOpc ( unsigned ImmOpcode ) const { if ( ! ImmToIdxMap . count ( ImmOpcode ) ) return PPC :: INSTRUCTION_LIST_END ; return ImmToIdxMap . find ( ImmOpcode ) -> second ; } </s>

getMappedIdxOpcForImmOpc - Return the mapped index form load/store opcode for a given imm form load/store opcode ImmFormOpcode .


<s> void SparcFrameLowering :: emitPrologue ( MachineFunction & MF ) const { SparcMachineFunctionInfo * FuncInfo = MF . getInfo < SparcMachineFunctionInfo > ( ) ; MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const SparcInstrInfo & TII = * static_cast < const SparcInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; unsigned SAVEri = SP :: SAVEri ; unsigned SAVErr = SP :: SAVErr ; if ( FuncInfo -> isLeafProc ( ) ) { if ( NumBytes == 0 ) return ; SAVEri = SP :: ADDri ; SAVErr = SP :: ADDrr ; } NumBytes = - SubTarget . getAdjustedFrameSize ( NumBytes ) ; if ( NumBytes >= - 4096 ) { BuildMI ( MBB , MBBI , dl , TII . get ( SAVEri ) , SP :: O6 ) . addReg ( SP :: O6 ) . addImm ( NumBytes ) ; } else { unsigned OffHi = ( unsigned ) NumBytes >> 10U ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: SETHIi ) , SP :: G1 ) . addImm ( OffHi ) ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: ORri ) , SP :: G1 ) . addReg ( SP :: G1 ) . addImm ( NumBytes & ( ( 1 << 10 ) - 1 ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( SAVErr ) , SP :: O6 ) . addReg ( SP :: O6 ) . addReg ( SP :: G1 ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createMachObjectWriter ( new ARMMachObjectWriter ( false , object :: mach :: CTM_ARM , object :: mach :: CSARM_V7 ) , OS , true ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static int ix86_builtin_vectorization_cost ( enum vect_cost_for_stmt type_of_cost , tree vectype , int ) { unsigned elements ; switch ( type_of_cost ) { case scalar_stmt : return ix86_cost -> scalar_stmt_cost ; case scalar_load : return ix86_cost -> scalar_load_cost ; case scalar_store : return ix86_cost -> scalar_store_cost ; case vector_stmt : return ix86_cost -> vec_stmt_cost ; case vector_load : return ix86_cost -> vec_align_load_cost ; case vector_store : return ix86_cost -> vec_store_cost ; case vec_to_scalar : return ix86_cost -> vec_to_scalar_cost ; case scalar_to_vec : return ix86_cost -> scalar_to_vec_cost ; case unaligned_load : case unaligned_store : return ix86_cost -> vec_unalign_load_cost ; case cond_branch_taken : return ix86_cost -> cond_taken_branch_cost ; case cond_branch_not_taken : return ix86_cost -> cond_not_taken_branch_cost ; case vec_perm : case vec_promote_demote : return ix86_cost -> vec_stmt_cost ; case vec_construct : elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; return ix86_cost -> vec_stmt_cost * ( elements / 2 + 1 ) ; default : gcc_unreachable ( ) ; } } </s>


<s> void lm32_expand_epilogue ( void ) { rtx ra_rtx = gen_rtx_REG ( Pmode , RA_REGNUM ) ; lm32_compute_frame_size ( get_frame_size ( ) ) ; if ( current_frame_info . total_size > 0 ) { emit_insn ( gen_blockage ( ) ) ; if ( current_frame_info . reg_save_mask != 0 ) expand_save_restore ( & current_frame_info , 1 ) ; stack_adjust ( current_frame_info . total_size ) ; emit_jump_insn ( gen_return_internal ( ra_rtx ) ) ; } else { emit_jump_insn ( gen_return_internal ( ra_rtx ) ) ; } } </s>

Create an emit instructions for a functions epilogue .


<s> bool R600InstrInfo :: ClobbersPredicate ( MachineInstr & MI , std :: vector < MachineOperand > & Pred , bool SkipDead ) const { return isPredicateSetter ( MI . getOpcode ( ) ) ; } </s>

If the specified instruction defines any predicate or condition code register ( s ) used for predication , returns true as well as the definition predicate ( s ) by reference .


<s> void OR1KAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( ( unsigned ) Kind , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { default : FullSize = 4 ; break ; } uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>


<s> bool NVPTXAsmPrinter :: runOnMachineFunction ( MachineFunction & F ) { nvptxSubtarget = & F . getSubtarget < NVPTXSubtarget > ( ) ; bool Result = AsmPrinter :: runOnMachineFunction ( F ) ; OutStreamer -> EmitRawText ( StringRef ( "}\n" ) ) ; return Result ; } </s>

runOnMachineFunction - Emit the function body .


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ReserveX18 ( TT . isOSDarwin ( ) ) , IsLittle ( LittleEndian ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS , CPU ) ) , TSInfo ( ) , TLInfo ( TM , * this ) , GISel ( ) { GISelAccessor * AArch64GISel = new GISelAccessor ( ) ; AArch64GISelActualAccessor * AArch64GISel = new AArch64GISelActualAccessor ( ) ; AArch64GISel -> CallLoweringInfo . reset ( new AArch64CallLowering ( * getTargetLowering ( ) ) ) ; AArch64GISel -> Legalizer . reset ( new AArch64LegalizerInfo ( ) ) ; auto * RBI = new AArch64RegisterBankInfo ( * getRegisterInfo ( ) ) ; AArch64GISel -> InstSelector . reset ( createAArch64InstructionSelector ( * static_cast < const AArch64TargetMachine * > ( & TM ) , * this , * RBI ) ) ; AArch64GISel -> RegBankInfo . reset ( RBI ) ; setGISelAccessor ( * AArch64GISel ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


"unimplemented opcode in encodeInstruction()"

Encode the given Inst to bytes and append to CB .


<s> void GCNPassConfig :: addFastRegAlloc ( FunctionPass * RegAllocPass ) { insertPass ( & PHIEliminationID , & SILowerControlFlowID , false ) ; insertPass ( & SILowerControlFlowID , & SIFixWWMLivenessID , false ) ; TargetPassConfig :: addFastRegAlloc ( RegAllocPass ) ; } </s>

addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast register allocation .


<s> bool legitimate_reload_constant_p ( rtx op ) { if ( GET_CODE ( op ) == CONST_INT && DISP_IN_RANGE ( INTVAL ( op ) ) ) return true ; if ( GET_CODE ( op ) == CONST_INT && ( CONST_OK_FOR_K ( INTVAL ( op ) ) || CONST_OK_FOR_Os ( INTVAL ( op ) ) ) ) return true ; if ( TARGET_ZARCH && GET_CODE ( op ) == CONST_INT && trunc_int_for_mode ( INTVAL ( op ) , word_mode ) == INTVAL ( op ) && s390_single_part ( op , word_mode , HImode , 0 ) >= 0 ) return true ; if ( TARGET_EXTIMM && GET_CODE ( op ) == CONST_INT && trunc_int_for_mode ( INTVAL ( op ) , word_mode ) == INTVAL ( op ) && s390_single_part ( op , word_mode , SImode , 0 ) >= 0 ) return true ; if ( TARGET_CPU_ZARCH && larl_operand ( op , VOIDmode ) ) return true ; if ( GET_CODE ( op ) == CONST_DOUBLE && CONST_DOUBLE_OK_FOR_CONSTRAINT_P ( op , 'G' , "G" ) ) return true ; if ( GET_CODE ( op ) == CONST_INT && trunc_int_for_mode ( INTVAL ( op ) , word_mode ) != INTVAL ( op ) ) { enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode ; rtx hi = operand_subword ( op , 0 , 0 , dword_mode ) ; rtx lo = operand_subword ( op , 1 , 0 , dword_mode ) ; return legitimate_reload_constant_p ( hi ) && legitimate_reload_constant_p ( lo ) ; } return false ; } </s>

Returns true if the constant value OP is a legitimate general operand during and after reload . The difference to legitimate_constant_p is that this function will not accept a constant that would need to be forced to the literal pool before it can be used as operand .


"LowerFormalArguments Unhandled argument type: "

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> int first_fp_reg_to_save ( void ) { int first_reg ; for ( first_reg = 14 + 32 ; first_reg <= 63 ; first_reg ++ ) if ( save_reg_p ( first_reg ) ) break ; return first_reg ; } </s>


"target CPU does not support THUMB instructions"

"target CPU does not support unaligned accesses"

Reset options between modes that the user has specified .


<s> void SIAnnotateControlFlow :: initialize ( Module & M , const GCNSubtarget & ST ) { LLVMContext & Context = M . getContext ( ) ; Void = Type :: getVoidTy ( Context ) ; Boolean = Type :: getInt1Ty ( Context ) ; IntMask = ST . isWave32 ( ) ? Type :: getInt32Ty ( Context ) : Type :: getInt64Ty ( Context ) ; ReturnStruct = StructType :: get ( Boolean , IntMask ) ; BoolTrue = ConstantInt :: getTrue ( Context ) ; BoolFalse = ConstantInt :: getFalse ( Context ) ; BoolUndef = UndefValue :: get ( Boolean ) ; IntMaskZero = ConstantInt :: get ( IntMask , 0 ) ; If = Intrinsic :: getDeclaration ( & M , Intrinsic :: amdgcn_if , { IntMask } ) ; Else = Intrinsic :: getDeclaration ( & M , Intrinsic :: amdgcn_else , { IntMask , IntMask } ) ; IfBreak = Intrinsic :: getDeclaration ( & M , Intrinsic :: amdgcn_if_break , { IntMask } ) ; Loop = Intrinsic :: getDeclaration ( & M , Intrinsic :: amdgcn_loop , { IntMask } ) ; EndCf = Intrinsic :: getDeclaration ( & M , Intrinsic :: amdgcn_end_cf , { IntMask } ) ; } </s>

Initialize the strategy after building the DAG for a new region .


<s> static bool rs6000_builtin_valid_without_lhs ( enum rs6000_builtins fn_code ) { if ( rs6000_builtin_info [ fn_code ] . attr & RS6000_BTC_VOID ) return true ; switch ( fn_code ) { case ALTIVEC_BUILTIN_STVX_V16QI : case ALTIVEC_BUILTIN_STVX_V8HI : case ALTIVEC_BUILTIN_STVX_V4SI : case ALTIVEC_BUILTIN_STVX_V4SF : case ALTIVEC_BUILTIN_STVX_V2DI : case ALTIVEC_BUILTIN_STVX_V2DF : case VSX_BUILTIN_STXVW4X_V16QI : case VSX_BUILTIN_STXVW4X_V8HI : case VSX_BUILTIN_STXVW4X_V4SF : case VSX_BUILTIN_STXVW4X_V4SI : case VSX_BUILTIN_STXVD2X_V2DF : case VSX_BUILTIN_STXVD2X_V2DI : return true ; default : return false ; } } </s>

Helper function to sort out which built-ins may be valid without having a LHS .


<s>
unsigned
TOYRegisterInfo
::
getFrameRegister
(
const
MachineFunction
&
MF
)
const
{
llvm_unreachable
(
"getFrameRegister not implemented yet"
)
;
}
</s>

TOY
TOY
"getFrameRegister not implemented yet"


<s> void MipsSETargetLowering :: addMSAIntType ( MVT :: SimpleValueType Ty , const TargetRegisterClass * RC ) { addRegisterClass ( Ty , RC ) ; for ( unsigned Opc = 0 ; Opc < ISD :: BUILTIN_OP_END ; ++ Opc ) setOperationAction ( Opc , Ty , Expand ) ; setOperationAction ( ISD :: BITCAST , Ty , Legal ) ; setOperationAction ( ISD :: LOAD , Ty , Legal ) ; setOperationAction ( ISD :: STORE , Ty , Legal ) ; setOperationAction ( ISD :: EXTRACT_VECTOR_ELT , Ty , Custom ) ; setOperationAction ( ISD :: INSERT_VECTOR_ELT , Ty , Legal ) ; setOperationAction ( ISD :: BUILD_VECTOR , Ty , Custom ) ; setOperationAction ( ISD :: UNDEF , Ty , Legal ) ; setOperationAction ( ISD :: ADD , Ty , Legal ) ; setOperationAction ( ISD :: AND , Ty , Legal ) ; setOperationAction ( ISD :: CTLZ , Ty , Legal ) ; setOperationAction ( ISD :: CTPOP , Ty , Legal ) ; setOperationAction ( ISD :: MUL , Ty , Legal ) ; setOperationAction ( ISD :: OR , Ty , Legal ) ; setOperationAction ( ISD :: SDIV , Ty , Legal ) ; setOperationAction ( ISD :: SREM , Ty , Legal ) ; setOperationAction ( ISD :: SHL , Ty , Legal ) ; setOperationAction ( ISD :: SRA , Ty , Legal ) ; setOperationAction ( ISD :: SRL , Ty , Legal ) ; setOperationAction ( ISD :: SUB , Ty , Legal ) ; setOperationAction ( ISD :: SMAX , Ty , Legal ) ; setOperationAction ( ISD :: SMIN , Ty , Legal ) ; setOperationAction ( ISD :: UDIV , Ty , Legal ) ; setOperationAction ( ISD :: UREM , Ty , Legal ) ; setOperationAction ( ISD :: UMAX , Ty , Legal ) ; setOperationAction ( ISD :: UMIN , Ty , Legal ) ; setOperationAction ( ISD :: VECTOR_SHUFFLE , Ty , Custom ) ; setOperationAction ( ISD :: VSELECT , Ty , Legal ) ; setOperationAction ( ISD :: XOR , Ty , Legal ) ; if ( Ty == MVT :: v4i32 || Ty == MVT :: v2i64 ) { setOperationAction ( ISD :: FP_TO_SINT , Ty , Legal ) ; setOperationAction ( ISD :: FP_TO_UINT , Ty , Legal ) ; setOperationAction ( ISD :: SINT_TO_FP , Ty , Legal ) ; setOperationAction ( ISD :: UINT_TO_FP , Ty , Legal ) ; } setOperationAction ( ISD :: SETCC , Ty , Legal ) ; setCondCodeAction ( ISD :: SETNE , Ty , Expand ) ; setCondCodeAction ( ISD :: SETGE , Ty , Expand ) ; setCondCodeAction ( ISD :: SETGT , Ty , Expand ) ; setCondCodeAction ( ISD :: SETUGE , Ty , Expand ) ; setCondCodeAction ( ISD :: SETUGT , Ty , Expand ) ; } </s>

Enable MSA support for the given integer type and Register class .

Mips Mips MVT::SimpleValueType 0 ISD::BUILTIN_OP_END ISD::BITCAST ISD::LOAD ISD::STORE ISD::EXTRACT_VECTOR_ELT ISD::INSERT_VECTOR_ELT ISD::BUILD_VECTOR ISD::UNDEF ISD::ADD ISD::AND ISD::CTLZ ISD::CTPOP ISD::MUL ISD::OR ISD::SDIV ISD::SREM ISD::SHL ISD::SRA ISD::SRL ISD::SUB ISD::SMAX ISD::SMIN ISD::UDIV ISD::UREM ISD::UMAX ISD::UMIN ISD::VECTOR_SHUFFLE ISD::VSELECT ISD::XOR MVT::v4i32 MVT::v2i64 ISD::FP_TO_SINT ISD::FP_TO_UINT ISD::SINT_TO_FP ISD::UINT_TO_FP ISD::SETCC ISD::SETNE ISD::SETGE ISD::SETGT ISD::SETUGE ISD::SETUGT


<s>
StringRef
getPassName
(
)
const
override
{
return
"NVPTX Replace Image Handles"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void MipsPassConfig :: addPreEmitPass ( ) { MipsTargetMachine & TM = getMipsTargetMachine ( ) ; addPass ( createMipsDelaySlotFillerPass ( TM ) ) ; addPass ( createMipsHazardSchedule ( ) ) ; addPass ( createMipsLongBranchPass ( TM ) ) ; addPass ( createMipsConstantIslandPass ( TM ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static rtx adjacent_mem_locations ( rtx mem1 , rtx mem2 ) { rtx reg1 , reg2 ; HOST_WIDE_INT off1 , size1 , off2 , size2 ; if ( MEM_P ( mem1 ) && MEM_P ( mem2 ) && get_memref_parts ( mem1 , & reg1 , & off1 , & size1 ) && get_memref_parts ( mem2 , & reg2 , & off2 , & size2 ) && REGNO ( reg1 ) == REGNO ( reg2 ) ) { if ( off1 + size1 == off2 ) return mem1 ; else if ( off2 + size2 == off1 ) return mem2 ; } return NULL_RTX ; } </s>

If the target storage locations of arguments MEM1 and MEM2 are adjacent , then return the argument that has the lower address . Otherwise , return NULL_RTX .