<s> static SDValue WidenVector ( SDValue V64Reg , SelectionDAG & DAG ) { EVT VT = V64Reg . getValueType ( ) ; unsigned NarrowSize = VT . getVectorNumElements ( ) ; MVT EltTy = VT . getVectorElementType ( ) . getSimpleVT ( ) ; MVT WideTy = MVT :: getVectorVT ( EltTy , 2 * NarrowSize ) ; SDLoc DL ( V64Reg ) ; return DAG . getNode ( ISD :: INSERT_SUBVECTOR , DL , WideTy , DAG . getUNDEF ( WideTy ) , V64Reg , DAG . getConstant ( 0 , MVT :: i32 ) ) ; } </s>

Widen the vector up to the next power of two using INSERT_SUBVECTOR .


<s>
bool
AArch64MCInstLower
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
const
{
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
)
return
false
;
MCOp
=
MCOperand
::
CreateReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_RegisterMask
:
return
false
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
CreateImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
CreateExpr
(
MCSymbolRefExpr
::
Create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
Ctx
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
LowerSymbolOperand
(
MO
,
GetGlobalAddressSymbol
(
MO
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
LowerSymbolOperand
(
MO
,
GetExternalSymbolSymbol
(
MO
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
MCOp
=
LowerSymbolOperand
(
MO
,
Printer
.
GetJTISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
MCOp
=
LowerSymbolOperand
(
MO
,
Printer
.
GetCPISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_BlockAddress
:
MCOp
=
LowerSymbolOperand
(
MO
,
Printer
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
)
;
break
;
}
return
true
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> void Mips16InstrInfo :: adjustStackPtr ( unsigned SP , int64_t Amount , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( isInt < 16 > ( Amount ) ) BuildAddiuSpImm ( MBB , I , Amount ) ; else adjustStackPtrBigUnrestricted ( SP , Amount , MBB , I ) ; } </s>


<s> void altivec_expand_vec_perm_le ( rtx operands [ 4 ] ) { rtx notx , iorx , unspec ; rtx target = operands [ 0 ] ; rtx op0 = operands [ 1 ] ; rtx op1 = operands [ 2 ] ; rtx sel = operands [ 3 ] ; rtx tmp = target ; rtx norreg = gen_reg_rtx ( V16QImode ) ; machine_mode mode = GET_MODE ( target ) ; if ( ! REG_P ( op0 ) ) op0 = force_reg ( mode , op0 ) ; if ( ! REG_P ( op1 ) ) op1 = force_reg ( mode , op1 ) ; if ( ! REG_P ( sel ) ) sel = force_reg ( V16QImode , sel ) ; if ( ! REG_P ( target ) ) tmp = gen_reg_rtx ( mode ) ; notx = gen_rtx_NOT ( V16QImode , sel ) ; iorx = ( TARGET_P8_VECTOR ? gen_rtx_IOR ( V16QImode , notx , notx ) : gen_rtx_AND ( V16QImode , notx , notx ) ) ; emit_insn ( gen_rtx_SET ( norreg , iorx ) ) ; unspec = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , op1 , op0 , norreg ) , UNSPEC_VPERM ) ; if ( ! REG_P ( target ) ) { emit_move_insn ( tmp , unspec ) ; unspec = tmp ; } emit_move_insn ( target , unspec ) ; } </s>

Similarly to altivec_expand_vec_perm_const_le , we must adjust the permute control vector . But here it 's not a constant , so we must generate a vector NAND or NOR to do the adjustment .


<s> static bool rs6000_lra_p ( void ) { return rs6000_lra_flag ; } </s>

Return true if we use LRA instead of reload pass .


<s> static void arm_emit_multi_reg_pop ( unsigned long saved_regs_mask ) { int num_regs = 0 ; int i , j ; rtx par ; rtx dwarf = NULL_RTX ; rtx tmp , reg ; bool return_in_pc = saved_regs_mask & ( 1 << PC_REGNUM ) ; int offset_adj ; int emit_update ; offset_adj = return_in_pc ? 1 : 0 ; for ( i = 0 ; i <= LAST_ARM_REGNUM ; i ++ ) if ( saved_regs_mask & ( 1 << i ) ) num_regs ++ ; gcc_assert ( num_regs && num_regs <= 16 ) ; emit_update = ( saved_regs_mask & ( 1 << SP_REGNUM ) ) ? 0 : 1 ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs + emit_update + offset_adj ) ) ; if ( return_in_pc ) XVECEXP ( par , 0 , 0 ) = ret_rtx ; if ( emit_update ) { tmp = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , 4 * num_regs ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , offset_adj ) = tmp ; } for ( j = 0 , i = 0 ; j < num_regs ; i ++ ) if ( saved_regs_mask & ( 1 << i ) ) { rtx dwarf_reg = reg = gen_rtx_REG ( SImode , i ) ; if ( arm_current_function_pac_enabled_p ( ) && i == IP_REGNUM ) dwarf_reg = gen_rtx_REG ( SImode , RA_AUTH_CODE ) ; if ( ( num_regs == 1 ) && emit_update && ! return_in_pc ) { tmp = gen_frame_mem ( SImode , gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ) ; tmp = emit_insn ( gen_rtx_SET ( reg , tmp ) ) ; REG_NOTES ( tmp ) = alloc_reg_note ( REG_CFA_RESTORE , dwarf_reg , dwarf ) ; return ; } tmp = gen_rtx_SET ( reg , gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , 4 * j ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , j + emit_update + offset_adj ) = tmp ; if ( i != PC_REGNUM ) dwarf = alloc_reg_note ( REG_CFA_RESTORE , dwarf_reg , dwarf ) ; j ++ ; } if ( return_in_pc ) par = emit_jump_insn ( par ) ; else par = emit_insn ( par ) ; REG_NOTES ( par ) = dwarf ; if ( ! return_in_pc ) arm_add_cfa_adjust_cfa_note ( par , UNITS_PER_WORD * num_regs , stack_pointer_rtx , stack_pointer_rtx ) ; } </s>

Generate and emit an insn pattern that we will recognize as a pop_multi . SAVED_REGS_MASK shows which registers need to be restored . Unfortunately , since this insn does not reflect very well the actual semantics of the operation , we need to annotate the insn for the benefit of DWARF2 frame unwind information .


<s> void SIInstrInfo :: reserveIndirectRegisters ( BitVector & Reserved , const MachineFunction & MF ) const { int End = getIndirectIndexEnd ( MF ) ; int Begin = getIndirectIndexBegin ( MF ) ; if ( End == - 1 ) return ; for ( int Index = Begin ; Index <= End ; ++ Index ) Reserved . set ( AMDGPU :: VReg_32RegClass . getRegister ( Index ) ) ; for ( int Index = std :: max ( 0 , Begin - 1 ) ; Index <= End ; ++ Index ) Reserved . set ( AMDGPU :: VReg_64RegClass . getRegister ( Index ) ) ; for ( int Index = std :: max ( 0 , Begin - 2 ) ; Index <= End ; ++ Index ) Reserved . set ( AMDGPU :: VReg_96RegClass . getRegister ( Index ) ) ; for ( int Index = std :: max ( 0 , Begin - 3 ) ; Index <= End ; ++ Index ) Reserved . set ( AMDGPU :: VReg_128RegClass . getRegister ( Index ) ) ; for ( int Index = std :: max ( 0 , Begin - 7 ) ; Index <= End ; ++ Index ) Reserved . set ( AMDGPU :: VReg_256RegClass . getRegister ( Index ) ) ; for ( int Index = std :: max ( 0 , Begin - 15 ) ; Index <= End ; ++ Index ) Reserved . set ( AMDGPU :: VReg_512RegClass . getRegister ( Index ) ) ; } </s>

Reserve the registers that may be accessed using indirect addressing .


<s> const R600RegisterInfo & R600InstrInfo :: getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


"Callee saved registers requested for unknown architecture "


<s> bool SparcDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintCode ) { default : return true ; case 'm' : if ( ! SelectADDRrr ( Op . getNode ( ) , Op , Op0 , Op1 ) ) SelectADDRri ( Op . getNode ( ) , Op , Op0 , Op1 ) ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> unsigned getNumberOfRegisters ( bool Vector ) { if ( Vector ) { if ( ST -> hasNEON ( ) ) return 32 ; return 0 ; } return 31 ; } </s>


<s> void PPCDispatchGroupSBHazardRecognizer :: EmitNoop ( ) { unsigned Directive = DAG -> MF . getSubtarget < PPCSubtarget > ( ) . getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_PWR6 || Directive == PPC :: DIR_PWR7 || Directive == PPC :: DIR_PWR8 || Directive == PPC :: DIR_PWR8 || CurSlots == 6 ) { CurGroup . clear ( ) ; CurSlots = CurBranches = 0 ; } else { CurGroup . push_back ( nullptr ) ; ++ CurSlots ; } } </s>

EmitNoop - This callback is invoked when a noop was added to the instruction stream .


<s>
BitVector
ARMBaseRegisterInfo
::
getReservedRegs
(
const
MachineFunction
&
MF
)
const
{
const
ARMSubtarget
&
STI
=
MF
.
getSubtarget
<
ARMSubtarget
>
(
)
;
const
ARMFrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
BitVector
Reserved
(
getNumRegs
(
)
)
;
markSuperRegs
(
Reserved
,
ARM
::
SP
)
;
markSuperRegs
(
Reserved
,
ARM
::
PC
)
;
markSuperRegs
(
Reserved
,
ARM
::
FPSCR
)
;
markSuperRegs
(
Reserved
,
ARM
::
APSR_NZCV
)
;
if
(
TFI
->
hasFP
(
MF
)
)
markSuperRegs
(
Reserved
,
STI
.
getFramePointerReg
(
)
)
;
if
(
hasBasePointer
(
MF
)
)
markSuperRegs
(
Reserved
,
BasePtr
)
;
if
(
STI
.
isR9Reserved
(
)
)
markSuperRegs
(
Reserved
,
ARM
::
R9
)
;
if
(
!
STI
.
hasD32
(
)
)
{
static_assert
(
ARM
::
D31
==
ARM
::
D16
+
15
,
"Register list not consecutive!"
)
;
for
(
unsigned
R
=
0
;
R
<
16
;
++
R
)
markSuperRegs
(
Reserved
,
ARM
::
D16
+
R
)
;
}
const
TargetRegisterClass
&
RC
=
ARM
::
GPRPairRegClass
;
for
(
unsigned
Reg
:
RC
)
for
(
MCSubRegIterator
SI
(
Reg
,
this
)
;
SI
.
isValid
(
)
;
++
SI
)
if
(
Reserved
.
test
(
*
SI
)
)
markSuperRegs
(
Reserved
,
Reg
)
;
markSuperRegs
(
Reserved
,
ARM
::
ZR
)
;
assert
(
checkAllSuperRegsMarked
(
Reserved
)
)
;
return
Reserved
;
}
</s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> static bool aarch64_tls_symbol_p ( rtx x ) { if ( ! TARGET_HAVE_TLS ) return false ; if ( GET_CODE ( x ) != SYMBOL_REF ) return false ; return SYMBOL_REF_TLS_MODEL ( x ) != 0 ; } </s>

Return true if SYMBOL_REF X is thread local


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT ) const override { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> bool LC2200AsmBackend :: mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> const TargetRegisterClass * getMatchingSuperRegClass ( const TargetRegisterClass * A , const TargetRegisterClass * B , unsigned Idx ) const { return A ; } </s>

getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register in it has a sub-register of the specified sub-register index which is in the specified register class B .


<s> const CSKYRegisterInfo * getRegisterInfo ( ) const override { return & RegInfo ; } </s>


<s> bool AMDGPUPromoteAlloca :: doInitialization ( Module & M ) { if ( ! TM ) return false ; Mod = & M ; DL = & Mod -> getDataLayout ( ) ; MDBuilder MDB ( Mod -> getContext ( ) ) ; MaxWorkGroupSizeRange = MDB . createRange ( APInt ( 32 , 0 ) , APInt ( 32 , 2048 ) ) ; const Triple & TT = TM -> getTargetTriple ( ) ; IsAMDGCN = TT . getArch ( ) == Triple :: amdgcn ; IsAMDHSA = TT . getOS ( ) == Triple :: AMDHSA ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> RegisterBankInfo :: InstructionMappings X86RegisterBankInfo :: getInstrAlternativeMappings ( const MachineInstr & MI ) const { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_LOAD : case TargetOpcode :: G_STORE : { unsigned Size = getSizeInBits ( MI . getOperand ( 0 ) . getReg ( ) , MRI , TRI ) ; if ( Size != 32 && Size != 64 ) break ; unsigned NumOperands = MI . getNumOperands ( ) ; SmallVector < PartialMappingIdx , 4 > OpRegBankIdx ( NumOperands ) ; getInstrPartialMappingIdxs ( MI , MRI , true , OpRegBankIdx ) ; SmallVector < const ValueMapping * , 8 > OpdsMapping ( NumOperands ) ; if ( ! getInstrValueMapping ( MI , OpRegBankIdx , OpdsMapping ) ) break ; RegisterBankInfo :: InstructionMapping Mapping = InstructionMapping { 1 , 1 , getOperandsMapping ( OpdsMapping ) , NumOperands } ; InstructionMappings AltMappings ; AltMappings . emplace_back ( std :: move ( Mapping ) ) ; return AltMappings ; } default : break ; } return RegisterBankInfo :: getInstrAlternativeMappings ( MI ) ; } </s>


<s>
void
SystemZInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MBBI
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
SystemZ
::
GR128BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
copyPhysReg
(
MBB
,
MBBI
,
DL
,
RI
.
getSubReg
(
DestReg
,
SystemZ
::
subreg_h64
)
,
RI
.
getSubReg
(
SrcReg
,
SystemZ
::
subreg_h64
)
,
KillSrc
)
;
copyPhysReg
(
MBB
,
MBBI
,
DL
,
RI
.
getSubReg
(
DestReg
,
SystemZ
::
subreg_l64
)
,
RI
.
getSubReg
(
SrcReg
,
SystemZ
::
subreg_l64
)
,
KillSrc
)
;
return
;
}
if
(
SystemZ
::
GRX32BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
emitGRX32Move
(
MBB
,
MBBI
,
DL
,
DestReg
,
SrcReg
,
SystemZ
::
LR
,
32
,
KillSrc
)
;
return
;
}
unsigned
Opcode
;
if
(
SystemZ
::
GR64BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LGR
;
else
if
(
SystemZ
::
FP32BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
STI
.
hasVector
(
)
SystemZ
::
LDR32
:
SystemZ
::
LER
;
else
if
(
SystemZ
::
FP64BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LDR
;
else
if
(
SystemZ
::
FP128BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LXR
;
else
if
(
SystemZ
::
VR32BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
VLR32
;
else
if
(
SystemZ
::
VR64BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
VLR64
;
else
if
(
SystemZ
::
VR128BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
VLR
;
else
if
(
SystemZ
::
AR32BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
CPYA
;
else
if
(
SystemZ
::
AR32BitRegClass
.
contains
(
DestReg
)
&&
SystemZ
::
GR32BitRegClass
.
contains
(
SrcReg
)
)
Opcode
=
SystemZ
::
SAR
;
else
if
(
SystemZ
::
GR32BitRegClass
.
contains
(
DestReg
)
&&
SystemZ
::
AR32BitRegClass
.
contains
(
SrcReg
)
)
Opcode
=
SystemZ
::
EAR
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
Opcode
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s>
const
char
*
csky_output_ck801_move
(
rtx
insn
ATTRIBUTE_UNUSED
,
rtx
operands
[
]
,
machine_mode
mode
ATTRIBUTE_UNUSED
)
{
rtx
dst
=
operands
[
0
]
;
rtx
src
=
operands
[
1
]
;
struct
csky_address
op1
;
if
(
REG_P
(
dst
)
)
{
if
(
REG_P
(
src
)
)
return
"mov\t%0, %1"
;
else
if
(
GET_CODE
(
src
)
==
MEM
)
{
decompose_csky_address
(
XEXP
(
src
,
0
)
,
&
op1
)
;
if
(
op1
.
label
)
return
"lrw\t%0, %1"
;
else
switch
(
GET_MODE
(
src
)
)
{
case
E_HImode
:
return
"ld.h\t%0, %1"
;
case
E_QImode
:
return
"ld.b\t%0, %1"
;
case
E_SFmode
:
case
E_SImode
:
return
"ld.w\t%0, %1"
;
default
:
gcc_unreachable
(
)
;
}
}
else
if
(
GET_CODE
(
src
)
==
CONST_INT
)
{
if
(
REGNO
(
dst
)
>
7
)
return
"lrw\t%0, %x1\t"
;
else
if
(
CSKY_CONST_OK_FOR_N
(
INTVAL
(
src
)
+
1
)
)
return
"movi\t%0, %1"
;
else
if
(
CSKY_CONST_OK_FOR_T
(
INTVAL
(
src
)
)
)
return
"#"
;
else
if
(
csky_shifted_imm8_constant
(
INTVAL
(
src
)
,
,
)
)
return
"#"
;
else
return
"lrw\t%0, %x1\t"
;
}
else
if
(
GET_CODE
(
src
)
==
CONST_DOUBLE
&&
GET_MODE
(
src
)
==
SFmode
)
{
const
REAL_VALUE_TYPE
*
d
;
long
l
;
d
=
CONST_DOUBLE_REAL_VALUE
(
src
)
;
REAL_VALUE_TO_TARGET_SINGLE
(
*
d
,
l
)
;
operands
[
1
]
=
GEN_INT
(
l
)
;
src
=
operands
[
1
]
;
if
(
CSKY_CONST_OK_FOR_N
(
INTVAL
(
src
)
+
1
)
)
return
"movi\t%0, %1"
;
else
return
"lrw\t%0, %x1\t"
;
}
else
if
(
TARGET_ANCHOR
&&
GET_CODE
(
src
)
==
SYMBOL_REF
)
{
if
(
SYMBOL_REF_FUNCTION_P
(
src
)
)
return
"lrw\t%0, %1@BTEXT"
;
else
return
"lrw\t%0, %1@BDATA"
;
}
else
return
"lrw\t%0, %1"
;
}
else
if
(
GET_CODE
(
dst
)
==
MEM
)
switch
(
GET_MODE
(
dst
)
)
{
case
E_HImode
:
return
"st.h\t%1, %0"
;
case
E_QImode
:
return
"st.b\t%1, %0"
;
case
E_SImode
:
case
E_SFmode
:
return
"st.w\t%1, %0"
;
default
:
gcc_unreachable
(
)
;
}
gcc_unreachable
(
)
;
}
</s>

Output a move of a word or less value . Specific for ck801 .


<s> static rtx frv_expand_mwtacc_builtin ( enum insn_code icode , tree call ) { rtx pat ; rtx op0 = frv_read_argument ( call , 0 ) ; rtx op1 = frv_read_argument ( call , 1 ) ; op0 = frv_int_to_acc ( icode , 0 , op0 ) ; if ( ! op0 ) return NULL_RTX ; op1 = frv_legitimize_argument ( icode , 1 , op1 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( pat ) emit_insn ( pat ) ; return NULL_RTX ; } </s>

Expand MWTACC and MWTACCG . These builtins take an accumulator or accumulator guard as their first argument and an SImode value as their second .


"-target-abi option != target-abi module flag"

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool SIInstrInfo :: hasUnwantedEffectsWhenEXECEmpty ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( MI . mayStore ( ) && isSMRD ( MI ) ) return true ; if ( MI . isReturn ( ) ) return true ; if ( Opcode == AMDGPU :: S_SENDMSG || Opcode == AMDGPU :: S_SENDMSGHALT || Opcode == AMDGPU :: EXP || Opcode == AMDGPU :: EXP_DONE || Opcode == AMDGPU :: DS_ORDERED_COUNT || Opcode == AMDGPU :: S_TRAP || Opcode == AMDGPU :: DS_GWS_INIT || Opcode == AMDGPU :: DS_GWS_BARRIER ) return true ; if ( MI . isCall ( ) || MI . isInlineAsm ( ) ) return true ; if ( Opcode == AMDGPU :: V_READFIRSTLANE_B32 || Opcode == AMDGPU :: V_READLANE_B32 ) return true ; return false ; } </s>

Whether we must prevent this instruction from executing with EXEC = 0 .


<s> rtx_insn * s390_emit_call ( rtx addr_location , rtx tls_call , rtx result_reg , rtx retaddr_reg ) { bool plt31_call_p = false ; rtx_insn * insn ; rtx vec [ 4 ] = { NULL_RTX } ; int elts = 0 ; rtx * call = & vec [ 0 ] ; rtx * clobber_ret_reg = & vec [ 1 ] ; rtx * use = & vec [ 2 ] ; rtx * clobber_thunk_reg = & vec [ 3 ] ; int i ; if ( GET_CODE ( addr_location ) == SYMBOL_REF ) { if ( flag_pic && ! SYMBOL_REF_LOCAL_P ( addr_location ) && ! TARGET_64BIT ) { if ( retaddr_reg != NULL_RTX ) { addr_location = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , addr_location ) , UNSPEC_PLT31 ) ; addr_location = gen_rtx_CONST ( Pmode , addr_location ) ; plt31_call_p = true ; } else addr_location = force_reg ( Pmode , addr_location ) ; } } if ( retaddr_reg == NULL_RTX && GET_CODE ( addr_location ) != SYMBOL_REF && ! plt31_call_p ) { emit_move_insn ( gen_rtx_REG ( Pmode , SIBCALL_REGNUM ) , addr_location ) ; addr_location = gen_rtx_REG ( Pmode , SIBCALL_REGNUM ) ; } if ( TARGET_INDIRECT_BRANCH_NOBP_CALL && GET_CODE ( addr_location ) != SYMBOL_REF && ! plt31_call_p ) { addr_location = force_reg ( Pmode , addr_location ) ; if ( ! TARGET_CPU_Z10 ) { * clobber_thunk_reg = gen_rtx_REG ( Pmode , INDIRECT_BRANCH_THUNK_REGNUM ) ; * clobber_thunk_reg = gen_rtx_CLOBBER ( VOIDmode , * clobber_thunk_reg ) ; } } addr_location = gen_rtx_MEM ( QImode , addr_location ) ; * call = gen_rtx_CALL ( VOIDmode , addr_location , const0_rtx ) ; if ( result_reg != NULL_RTX ) * call = gen_rtx_SET ( result_reg , * call ) ; if ( retaddr_reg != NULL_RTX ) { * clobber_ret_reg = gen_rtx_CLOBBER ( VOIDmode , retaddr_reg ) ; if ( tls_call != NULL_RTX ) * use = gen_rtx_USE ( VOIDmode , tls_call ) ; } for ( i = 0 ; i < 4 ; i ++ ) if ( vec [ i ] != NULL_RTX ) elts ++ ; if ( elts > 1 ) { rtvec v ; int e = 0 ; v = rtvec_alloc ( elts ) ; for ( i = 0 ; i < 4 ; i ++ ) if ( vec [ i ] != NULL_RTX ) { RTVEC_ELT ( v , e ) = vec [ i ] ; e ++ ; } * call = gen_rtx_PARALLEL ( VOIDmode , v ) ; } insn = emit_call_insn ( * call ) ; if ( plt31_call_p || tls_call != NULL_RTX ) { gcc_assert ( retaddr_reg != NULL_RTX ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , gen_rtx_REG ( Pmode , 12 ) ) ; } return insn ; } </s>

This function is used by the call expanders of the machine description . It emits the call insn itself together with the necessary operations to adjust the target address and returns the emitted insn . ADDR_LOCATION is the target address rtx TLS_CALL the location of the thread-local symbol RESULT_REG the register where the result of the call should be stored RETADDR_REG the register where the return address should be stored If this parameter is NULL_RTX the call is considered to be a sibling call .


<s> bool XtensaRegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> void RISCVPassConfig :: addMachineSSAOptimization ( ) { TargetPassConfig :: addMachineSSAOptimization ( ) ; if ( TM -> getTargetTriple ( ) . getArch ( ) == Triple :: riscv64 ) addPass ( createRISCVSExtWRemovalPass ( ) ) ; } </s>

Methods with trivial inline returns are convenient points in the common codegen pass pipeline where targets may insert passes .


<s> const Cpu0TargetLowering * Cpu0TargetLowering :: create ( const Cpu0TargetMachine & TM , const Cpu0Subtarget & STI ) { return llvm :: createCpu0SETargetLowering ( TM , STI ) ; } </s>


<s> bool writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const override { if ( ( Count % 8 ) != 0 ) return false ; for ( uint64_t i = 0 ; i < Count ; i += 8 ) support :: endian :: write < uint64_t > ( OS , 0x7900000000000000ULL , support :: little ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


"X86 Speculative Execution Side Effect Suppression"

getPassName - Return a nice clean name for a pass .


<s> inline static rtx_insn * emit_set_insn ( rtx x , rtx y ) { return emit_insn ( gen_rtx_SET ( x , y ) ) ; } </s>

Emit an insn that 's a simple single-set . Both the operands must be known to be valid .


<s> static struct machine_function * rs6000_init_machine_status ( void ) { return ggc_alloc_cleared ( sizeof ( machine_function ) ) ; } </s>

Functions to init , mark and free struct machine_function . These will be called , via pointer variables , from push_function_context and pop_function_context .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addRequired < LegacyDivergenceAnalysis > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addRequired < TargetPassConfig > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool RISCVTargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> bool M68kCallLowering :: enableBigEndian ( ) const { return true ; } </s>

For targets which want to use big-endian can enable it with enableBigEndian ( ) hook .


<s> const MCPhysReg * TeakRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_SaveList ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"Cheri128 fail hard"
;
}
</s>


"Thumb1 does not have ldr to high register"

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s> bool AMDGPUStructurizeCFG :: runOnRegion ( Region * R , RGPassManager & RGM ) { if ( R -> isTopLevelRegion ( ) ) return false ; Func = R -> getEntry ( ) -> getParent ( ) ; ParentRegion = R ; DT = & getAnalysis < DominatorTree > ( ) ; orderNodes ( ) ; collectInfos ( ) ; createFlow ( ) ; insertConditions ( ) ; rebuildSSA ( ) ; Order . clear ( ) ; Visited . clear ( ) ; Predicates . clear ( ) ; DeletedPhis . clear ( ) ; FlowsInserted . clear ( ) ; return true ; } </s>


<s> static void undo_split_delayed_nonbranch ( rtx_insn * insn ) { int icode = recog_memoized ( insn ) ; enum attr_type type ; rtx prev_pat , insn_pat ; rtx_insn * prev ; if ( icode < 0 ) return ; type = get_attr_type ( insn ) ; if ( type != TYPE_LOAD_SHADOW && type != TYPE_MULT_SHADOW ) return ; prev = PREV_INSN ( insn ) ; prev_pat = PATTERN ( prev ) ; insn_pat = PATTERN ( insn ) ; if ( GET_CODE ( prev_pat ) == COND_EXEC ) { prev_pat = COND_EXEC_CODE ( prev_pat ) ; insn_pat = COND_EXEC_CODE ( insn_pat ) ; } gcc_assert ( GET_CODE ( prev_pat ) == UNSPEC && ( ( XINT ( prev_pat , 1 ) == UNSPEC_REAL_LOAD && type == TYPE_LOAD_SHADOW ) || ( XINT ( prev_pat , 1 ) == UNSPEC_REAL_MULT && type == TYPE_MULT_SHADOW ) ) ) ; insn_pat = gen_rtx_SET ( SET_DEST ( insn_pat ) , XVECEXP ( prev_pat , 0 , 1 ) ) ; insn_pat = duplicate_cond ( insn_pat , prev ) ; PATTERN ( insn ) = insn_pat ; INSN_CODE ( insn ) = - 1 ; delete_insn ( prev ) ; } </s>

Examine if INSN is the result of splitting a load into a real load and a shadow , and if so , undo the transformation .


<s> static rtx_insn * emit_frame_insn ( rtx x ) { rtx_insn * insn = emit_insn ( x ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; return insn ; } </s>

Wrapper around emit_insn that sets RTX_FRAME_RELATED_P on the insn .


This function will set the fpscr from memory . MODE is the mode we are setting it to .


"  /* The fndecl for an overload is arbitrarily the first one\n"

"     for the overload.  We sort out the real types when\n"

"     processing the overload in the gcc front end.  */\n"

"  rs6000_builtin_decls[(int)RS6000_OVLD_%s] = t\n"

"                            NULL, NULL_TREE);\n"

"  rs6000_overload_info[RS6000_OVLD_%s - base]"

"    = &rs6000_instance_info[RS6000_INST_%s];\n\n"

Write code to initialize the overload table .

"                            NULL, NULL_TREE);\n"


<s> bool reg_unused_after ( rtx reg , rtx_insn * insn ) { rtx set = single_set ( insn ) ; if ( set && ! MEM_P ( SET_DEST ( set ) ) && reg_overlap_mentioned_p ( reg , SET_DEST ( set ) ) ) return true ; while ( ( insn = NEXT_INSN ( insn ) ) ) { if ( ! INSN_P ( insn ) ) continue ; rtx_code code = GET_CODE ( insn ) ; if ( code == CODE_LABEL ) return 1 ; if ( code == JUMP_INSN ) return false ; else if ( code == INSN && GET_CODE ( PATTERN ( insn ) ) == SEQUENCE ) { rtx_sequence * seq = as_a < rtx_sequence * > ( PATTERN ( insn ) ) ; bool retval = false ; for ( int i = 0 ; i < seq -> len ( ) ; i ++ ) { rtx_insn * this_insn = seq -> insn ( i ) ; rtx set = single_set ( this_insn ) ; if ( CALL_P ( this_insn ) ) code = CALL_INSN ; else if ( JUMP_P ( this_insn ) ) { if ( INSN_ANNULLED_BRANCH_P ( this_insn ) ) return false ; code = JUMP_INSN ; } if ( set && reg_overlap_mentioned_p ( reg , SET_SRC ( set ) ) ) return false ; if ( set && reg_overlap_mentioned_p ( reg , SET_DEST ( set ) ) ) { if ( ! MEM_P ( SET_DEST ( set ) ) ) retval = true ; else return false ; } if ( set == NULL_RTX && reg_overlap_mentioned_p ( reg , PATTERN ( this_insn ) ) ) return false ; } if ( retval ) return true ; else if ( code == JUMP_INSN ) return false ; } rtx set = single_set ( insn ) ; if ( set && reg_overlap_mentioned_p ( reg , SET_SRC ( set ) ) ) return false ; if ( set && reg_overlap_mentioned_p ( reg , SET_DEST ( set ) ) ) return ! MEM_P ( SET_DEST ( set ) ) ; if ( set == NULL && reg_overlap_mentioned_p ( reg , PATTERN ( insn ) ) ) return false ; if ( code == CALL_INSN && call_used_regs [ REGNO ( reg ) ] ) return true ; } return true ; } </s>

Return nonzero if REG is not used after INSN . We assume REG is a reload reg , and therefore does not live past labels or calls or jumps .


<s> ARMPLT1 * ARMPLT :: create ( ) { ARMPLT1 * plt1_entry = new ( std :: nothrow ) ARMPLT1 ( * m_pSectionData ) ; if ( ! plt1_entry ) fatal ( diag :: fail_allocate_memory_plt ) ; return plt1_entry ; } </s>


<s>
void
dump
(
)
{
cerr
<<
"X86ISelAddressMode "
<<
this
<<
'\n'
;
cerr
<<
"Base.Reg "
;
if
(
Base
.
Reg
.
getNode
(
)
!=
0
)
Base
.
Reg
.
getNode
(
)
->
dump
(
)
;
else
cerr
<<
"nul"
;
cerr
<<
" Base.FrameIndex "
<<
Base
.
FrameIndex
<<
'\n'
;
cerr
<<
" Scale"
<<
Scale
<<
'\n'
;
cerr
<<
"IndexReg "
;
if
(
IndexReg
.
getNode
(
)
!=
0
)
IndexReg
.
getNode
(
)
->
dump
(
)
;
else
cerr
<<
"nul"
;
cerr
<<
" Disp "
<<
Disp
<<
'\n'
;
cerr
<<
"GV "
;
if
(
GV
)
GV
->
dump
(
)
;
else
cerr
<<
"nul"
;
cerr
<<
" CP "
;
if
(
CP
)
CP
->
dump
(
)
;
else
cerr
<<
"nul"
;
cerr
<<
'\n'
;
cerr
<<
"ES "
;
if
(
ES
)
cerr
<<
ES
;
else
cerr
<<
"nul"
;
cerr
<<
" JT"
<<
JT
<<
" Align"
<<
Align
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

X86
"X86ISelAddressMode "
"Base.Reg "
0
"nul"
" Base.FrameIndex "
" Scale"
"IndexReg "
0
"nul"
" Disp "
"GV "
"nul"
" CP "
"nul"
"ES "
"nul"
" JT"
" Align"


<s> static bool m32r_rtx_ok_for_base_p ( const_rtx x , bool strict ) { if ( ! REG_P ( x ) ) return false ; if ( strict ) { if ( GPR_P ( REGNO ( x ) ) ) return true ; } else { if ( GPR_P ( REGNO ( x ) ) || REGNO ( x ) == ARG_POINTER_REGNUM || ! HARD_REGISTER_P ( x ) ) return true ; } return false ; } </s>

True if X is a reg that can be used as a base reg .


<s> const uint32_t * AArch64RegisterInfo :: getWindowsStackProbePreservedMask ( ) const { return CSR_AArch64_StackProbe_Windows_RegMask ; } </s>

Stack probing calls preserve different CSRs to the normal CC .


"JIT relocation model must be set to static or default!"

runOnMachineFunction - Emit the function body .


<s> static bool riscv_function_ok_for_sibcall ( tree decl ATTRIBUTE_UNUSED , tree exp ATTRIBUTE_UNUSED ) { if ( TARGET_SAVE_RESTORE ) return false ; if ( cfun -> machine -> naked_p ) return false ; if ( cfun -> machine -> interrupt_handler_p ) return false ; return true ; } </s>


<s> int GCNTTIImpl :: getMinMaxReductionCost ( VectorType * Ty , VectorType * CondTy , bool IsPairwise , bool IsUnsigned ) { EVT OrigTy = TLI -> getValueType ( DL , Ty ) ; if ( IsPairwise || ! ST -> hasVOP3PInsts ( ) || OrigTy . getScalarSizeInBits ( ) != 16 ) return BaseT :: getMinMaxReductionCost ( Ty , CondTy , IsPairwise , IsUnsigned ) ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; return LT . first * getHalfRateInstrCost ( ) ; } </s>

Try to calculate op costs for min/max reduction operations .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"TeeRISC Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static void frv_io_handle_use ( rtx * x , void * data ) { find_all_hard_regs ( * x , ( HARD_REG_SET * ) data ) ; } </s>

A note_stores callback that applies frv_io_handle_use_1 to an entire rhs value .


<s> static rtx gen_reg_or_parallel ( machine_mode mode , machine_mode orig_mode , unsigned int regno ) { rtx tmp ; if ( orig_mode != BLKmode ) tmp = gen_rtx_REG ( orig_mode , regno ) ; else { tmp = gen_rtx_REG ( mode , regno ) ; tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , const0_rtx ) ; tmp = gen_rtx_PARALLEL ( orig_mode , gen_rtvec ( 1 , tmp ) ) ; } return tmp ; } </s>

We want to pass a value in REGNO whose `` natural '' mode is MODE . However , this may not agree with the mode that the type system has chosen for the register , which is ORIG_MODE . If ORIG_MODE is not BLKmode , then we can go ahead and use it . Otherwise we have to build a PARALLEL instead .


<s> bool RISCVRI5CYIR :: runOnFunction ( Function & F ) { errs ( ) << "runOnFunction(" << F . getName ( ) . str ( ) << ")\n" ; this -> transformBitManipulation ( F ) ; return false ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> unsigned MipsSEInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { unsigned Opc = MI . getOpcode ( ) ; if ( ( Opc == Mips :: SW ) || ( Opc == Mips :: SD ) || ( Opc == Mips :: SWC1 ) || ( Opc == Mips :: SDC1 ) || ( Opc == Mips :: SDC164 ) ) { if ( ( MI . getOperand ( 1 ) . isFI ( ) ) && ( MI . getOperand ( 2 ) . isImm ( ) ) && ( isZeroImm ( MI . getOperand ( 2 ) ) ) ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> bool X86FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( MI ) ; if ( MBB . isEHFuncletEntry ( ) && STI . is32Bit ( ) && STI . isOSWindows ( ) ) return true ; const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Opc = STI . is64Bit ( ) ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool isLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! isLiveIn ) MBB . addLiveIn ( Reg ) ; bool CanKill = ! isLiveIn ; if ( CanKill ) { for ( MCRegAliasIterator AReg ( Reg , TRI , false ) ; AReg . isValid ( ) ; ++ AReg ) { if ( MRI . isLiveIn ( * AReg ) ) { CanKill = false ; break ; } } } BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , getKillRegState ( CanKill ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MVT VT = MVT :: Other ; if ( X86 :: VK16RegClass . contains ( Reg ) ) VT = STI . hasBWI ( ) ? MVT :: v64i1 : MVT :: v16i1 ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg , VT ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - 1 ] . getFrameIdx ( ) , RC , TRI ) ; -- MI ; MI -> setFlag ( MachineInstr :: FrameSetup ) ; ++ MI ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> unsigned X86TargetLowering :: getByValTypeAlignment ( Type * Ty , const DataLayout & DL ) const { if ( Subtarget . is64Bit ( ) ) { unsigned TyAlign = DL . getABITypeAlignment ( Ty ) ; if ( TyAlign > 8 ) return TyAlign ; return 8 ; } unsigned Align = 4 ; if ( Subtarget . hasSSE1 ( ) ) getMaxByValAlign ( Ty , Align ) ; return Align ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


<s> virtual void EmitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) { EmitA64MappingSymbol ( ) ; MCELFStreamer :: EmitInstruction ( Inst , STI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


"Thumb2 instruction size reduction pass"


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> bool iq2000_function_value_regno_p ( const unsigned int regno ) { return ( regno == GP_RETURN ) ; } </s>

Worker function for FUNCTION_VALUE_REGNO_P . On the IQ2000 , R2 and R3 are the only register thus used .


"%qE attribute only applies to interrupt functions"

Generate 'handle_interrupt ' attribute for decls


<s> Register ARMBaseRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; const ARMFrameLowering * TFI = getFrameLowering ( MF ) ; if ( TFI -> hasFP ( MF ) ) return getFramePointerReg ( STI ) ; return ARM :: SP ; } </s>


<s> static bool aarch64_valid_floating_const ( machine_mode mode , rtx x ) { if ( ! CONST_DOUBLE_P ( x ) ) return false ; if ( aarch64_float_const_zero_rtx_p ( x ) ) return true ; if ( ! ( mode == SFmode || mode == DFmode ) ) return false ; return aarch64_float_const_representable_p ( x ) ; } </s>

Return true if X holds either a quarter-precision or floating-point +0.0 constant .


<s> void MBlazeInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; BuildMI ( MBB , MI , DL , get ( MBlaze :: NOP ) ) ; } </s>

Insert a noop into the instruction stream at the specified point .


<s>
void
mmix_asm_output_label
(
FILE
*
stream
,
const
char
*
name
)
{
assemble_name
(
stream
,
name
)
;
fprintf
(
stream
,
"\tIS @\n"
)
;
}
</s>


"Requesting 64-bit offset in 32-bit immediate!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static int mep_insn_dependent_p ( rtx x , rtx y ) { rtx tmp ; gcc_assert ( INSN_P ( x ) ) ; gcc_assert ( INSN_P ( y ) ) ; tmp = PATTERN ( y ) ; note_stores ( PATTERN ( x ) , mep_insn_dependent_p_1 , & tmp ) ; if ( tmp == NULL_RTX ) return 1 ; tmp = PATTERN ( x ) ; note_stores ( PATTERN ( y ) , mep_insn_dependent_p_1 , & tmp ) ; if ( tmp == NULL_RTX ) return 1 ; return 0 ; } </s>

Return true if anything in insn X is ( anti , output , true ) dependent on anything in insn Y .


<s> unsigned NVPTXTTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo ) { std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: ADD : case ISD :: MUL : case ISD :: XOR : case ISD :: OR : case ISD :: AND : if ( LT . second . SimpleTy == MVT :: i64 ) return 2 * LT . first ; return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .

NVPTX NVPTX ISD::ADD ISD::MUL ISD::XOR ISD::OR ISD::AND MVT::i64 2


<s>
void
Thumb1InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
(
PseudoSourceValue
::
getFixedStack
(
FI
)
)
,
MachineMemOperand
::
MOStore
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tSpill
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .

ARM
ARM::tGPRRegisterClass
ARM
"Unknown regclass!"
ARM::tGPRRegisterClass
ARM
ARM::tSpill
0


<s> bool SITypeRewriter :: runOnFunction ( Function & F ) { AttributeSet Set = F . getAttributes ( ) ; Attribute A = Set . getAttribute ( AttributeSet :: FunctionIndex , "ShaderType" ) ; unsigned ShaderType = ShaderType :: COMPUTE ; if ( A . isStringAttribute ( ) ) { StringRef Str = A . getValueAsString ( ) ; Str . getAsInteger ( 0 , ShaderType ) ; } if ( ShaderType == ShaderType :: COMPUTE ) return false ; visit ( F ) ; visit ( F ) ; return false ; } </s>


<s>
void
PPCMIPeephole
::
initialize
(
MachineFunction
&
MFParm
)
{
MF
=
&
MFParm
;
MRI
=
&
MF
->
getRegInfo
(
)
;
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
TII
=
MF
->
getSubtarget
<
PPCSubtarget
>
(
)
.
getInstrInfo
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"*** PowerPC MI peephole pass ***\n\n"
)
;
LLVM_DEBUG
(
MF
->
dump
(
)
)
;
}
</s>

Initialize the strategy after building the DAG for a new region .

PowerPC
PPC
PPC
"*** PowerPC MI peephole pass ***\n\n"


<s>
SDValue
MSP430TargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
if
(
CallConv
==
CallingConv
::
MSP430_INTR
&&
!
Outs
.
empty
(
)
)
report_fatal_error
(
"ISRs cannot return any value"
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
AnalyzeReturnValues
(
CCInfo
,
RVLocs
,
Outs
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
unsigned
Opc
=
(
CallConv
==
CallingConv
::
MSP430_INTR
MSP430ISD
::
RETI_FLAG
:
MSP430ISD
::
RET_FLAG
)
;
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
Opc
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


"// rs6000_variable_issue (more = %d) = %d\n"

Power4 load update and store update instructions are cracked into a load or store and an integer insn which are executed in the same cycle . Branches have their own dispatch slot which does not count against the GCC issue rate , but it changes the program flow so there are no other instructions to issue in this cycle .


Hook to validate the current # pragma GCC target and set the state , and update the macros based on what was changed . If ARGS is NULL , then POP_TARGET is used to reset the options .


<s> static bool call_ABI_of_interest ( tree fndecl ) { if ( rs6000_gnu_attr && symtab -> state == EXPANSION ) { struct cgraph_node * c_node ; if ( fndecl == NULL_TREE ) return true ; if ( DECL_EXTERNAL ( fndecl ) ) return true ; c_node = cgraph_node :: get ( fndecl ) ; c_node = c_node -> ultimate_alias_target ( ) ; return ! c_node -> only_called_directly_p ( ) ; } return false ; } </s>

Return TRUE if a call to function FNDECL may be one that potentially affects the function calling ABI of the object file .


<s> bool RISCVPassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createHardwareLoopsPass ( ) ) ; } return false ; } </s>


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == 0 ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s>
bool
SIAnnotateControlFlow
::
runOnFunction
(
Function
&
F
)
{
DT
=
&
getAnalysis
<
DominatorTreeWrapperPass
>
(
)
.
getDomTree
(
)
;
LI
=
&
getAnalysis
<
LoopInfoWrapperPass
>
(
)
.
getLoopInfo
(
)
;
DA
=
&
getAnalysis
<
LegacyDivergenceAnalysis
>
(
)
;
TargetPassConfig
&
TPC
=
getAnalysis
<
TargetPassConfig
>
(
)
;
const
TargetMachine
&
TM
=
TPC
.
getTM
<
TargetMachine
>
(
)
;
initialize
(
*
F
.
getParent
(
)
,
TM
.
getSubtarget
<
GCNSubtarget
>
(
F
)
)
;
for
(
df_iterator
<
BasicBlock
*
>
I
=
df_begin
(
&
F
.
getEntryBlock
(
)
)
,
E
=
df_end
(
&
F
.
getEntryBlock
(
)
)
;
I
!=
E
;
++
I
)
{
BasicBlock
*
BB
=
*
I
;
BranchInst
*
Term
=
dyn_cast
<
BranchInst
>
(
BB
->
getTerminator
(
)
)
;
if
(
!
Term
||
Term
->
isUnconditional
(
)
)
{
if
(
isTopOfStack
(
BB
)
)
closeControlFlow
(
BB
)
;
continue
;
}
if
(
I
.
nodeVisited
(
Term
->
getSuccessor
(
1
)
)
)
{
if
(
isTopOfStack
(
BB
)
)
closeControlFlow
(
BB
)
;
if
(
DT
->
dominates
(
Term
->
getSuccessor
(
1
)
,
BB
)
)
handleLoop
(
Term
)
;
continue
;
}
if
(
isTopOfStack
(
BB
)
)
{
PHINode
*
Phi
=
dyn_cast
<
PHINode
>
(
Term
->
getCondition
(
)
)
;
if
(
Phi
&&
Phi
->
getParent
(
)
==
BB
&&
isElse
(
Phi
)
&&
!
hasKill
(
BB
)
)
{
insertElse
(
Term
)
;
eraseIfUnused
(
Phi
)
;
continue
;
}
closeControlFlow
(
BB
)
;
}
openIf
(
Term
)
;
}
if
(
!
Stack
.
empty
(
)
)
{
report_fatal_error
(
"failed to annotate CFG"
)
;
}
return
true
;
}
</s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> rtx spu_float_const ( const char * string , machine_mode mode ) { REAL_VALUE_TYPE value ; value = REAL_VALUE_ATOF ( string , mode ) ; return CONST_DOUBLE_FROM_REAL_VALUE ( value , mode ) ; } </s>


<s> int legitimate_pic_operand_p ( rtx x ) { switch ( GET_CODE ( x ) ) { case SYMBOL_REF : return 0 ; case LABEL_REF : return 0 ; case CONST : if ( GET_CODE ( XEXP ( x , 0 ) ) == PLUS && ( GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == SYMBOL_REF || GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == LABEL_REF ) && ( GET_CODE ( XEXP ( XEXP ( x , 0 ) , 1 ) ) == CONST_INT ) ) return 0 ; break ; case MEM : return legitimate_pic_operand_p ( XEXP ( x , 0 ) ) ; default : break ; } return 1 ; } </s>

Return true if OP is a legitimate general operand when generating PIC code . It is given that flag_pic is on and that OP satisfies CONSTANT_P or is a CONST_DOUBLE .


Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calling convention CallConv .


<s> unsigned HexagonTTIImpl :: getIntrinsicInstrCost ( Intrinsic :: ID ID , Type * RetTy , ArrayRef < Type * > Tys , FastMathFlags FMF , unsigned ScalarizationCostPassed ) { if ( ID == Intrinsic :: bswap ) { std :: pair < int , MVT > LT = TLI . getTypeLegalizationCost ( DL , RetTy ) ; return LT . first + 2 ; } return BaseT :: getIntrinsicInstrCost ( ID , RetTy , Tys , FMF , ScalarizationCostPassed ) ; } </s>

Hexagon Hexagon Intrinsic::ID Intrinsic::bswap 2


<s>
bool
AMDGPUAsmParser
::
isInlineConstant
(
const
MCInst
&
Inst
,
unsigned
OpIdx
)
const
{
const
MCInstrDesc
&
Desc
=
MII
.
get
(
Inst
.
getOpcode
(
)
)
;
if
(
!
AMDGPU
::
isSISrcOperand
(
Desc
,
OpIdx
)
)
{
return
false
;
}
const
MCOperand
&
MO
=
Inst
.
getOperand
(
OpIdx
)
;
int64_t
Val
=
MO
.
getImm
(
)
;
auto
OpSize
=
AMDGPU
::
getOperandSize
(
Desc
,
OpIdx
)
;
switch
(
OpSize
)
{
case
8
:
return
AMDGPU
::
isInlinableLiteral64
(
Val
,
hasInv2PiInlineImm
(
)
)
;
case
4
:
return
AMDGPU
::
isInlinableLiteral32
(
Val
,
hasInv2PiInlineImm
(
)
)
;
case
2
:
{
const
unsigned
OperandType
=
Desc
.
OpInfo
[
OpIdx
]
.
OperandType
;
if
(
OperandType
==
AMDGPU
::
OPERAND_REG_INLINE_C_V2INT16
||
OperandType
==
AMDGPU
::
OPERAND_REG_INLINE_C_V2FP16
||
OperandType
==
AMDGPU
::
OPERAND_REG_INLINE_AC_V2INT16
||
OperandType
==
AMDGPU
::
OPERAND_REG_INLINE_AC_V2FP16
||
OperandType
==
AMDGPU
::
OPERAND_REG_IMM_V2INT16
||
OperandType
==
AMDGPU
::
OPERAND_REG_IMM_V2FP16
)
{
return
AMDGPU
::
isInlinableLiteralV216
(
Val
,
hasInv2PiInlineImm
(
)
)
;
}
else
{
return
AMDGPU
::
isInlinableLiteral16
(
Val
,
hasInv2PiInlineImm
(
)
)
;
}
}
default
:
llvm_unreachable
(
"invalid operand size"
)
;
}
}
</s>

returns true if the operand OpIdx in MI is a valid inline immediate .


<s> bool PPCLinuxAsmPrinter :: doFinalization ( Module & M ) { const DataLayout * TD = TM . getDataLayout ( ) ; bool isPPC64 = TD -> getPointerSizeInBits ( ) == 64 ; PPCTargetStreamer & TS = static_cast < PPCTargetStreamer & > ( OutStreamer . getTargetStreamer ( ) ) ; if ( isPPC64 && ! TOC . empty ( ) ) { const MCSectionELF * Section = OutStreamer . getContext ( ) . getELFSection ( ".toc" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; OutStreamer . SwitchSection ( Section ) ; for ( MapVector < MCSymbol * , MCSymbol * > :: iterator I = TOC . begin ( ) , E = TOC . end ( ) ; I != E ; ++ I ) { OutStreamer . EmitLabel ( I -> second ) ; MCSymbol * S = OutContext . GetOrCreateSymbol ( I -> first -> getName ( ) ) ; TS . emitTCEntry ( * S ) ; } } MachineModuleInfoELF & MMIELF = MMI -> getObjFileInfo < MachineModuleInfoELF > ( ) ; MachineModuleInfoELF :: SymbolListTy Stubs = MMIELF . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> static int mep_adjust_cost ( rtx_insn * insn , rtx link , rtx_insn * dep_insn , int cost ) { int cost_specified ; if ( REG_NOTE_KIND ( link ) != 0 ) { if ( REG_NOTE_KIND ( link ) == REG_DEP_OUTPUT && global_reg_mentioned_p ( PATTERN ( insn ) ) && global_reg_mentioned_p ( PATTERN ( dep_insn ) ) ) return 1 ; return 0 ; } if ( recog_memoized ( dep_insn ) < 0 ) return cost ; if ( ! TARGET_H1 ) { cost_specified = get_attr_latency ( dep_insn ) ; if ( cost_specified != 0 ) return cost_specified ; } return cost ; } </s>

Scheduling hooks for VLIW mode . Conceptually this is very simple : we have a two-pack architecture that takes one core insn and one coprocessor insn to make up either a 32- or 64-bit instruction word ( depending on the option bit set in the chip ) . I.e . in VL32 mode , we can pack one 16-bit core insn and one 16-bit cop insn ; in VL64 mode we can pack one 16-bit core insn and one 48-bit cop insn or two 32-bit core/cop insns . In practice , instruction selection will be a bear . Consider in VL64 mode the following insns add $ 1 , 1 cmov $ cr0 , $ 0 these can not pack , since the add is a 16-bit core insn and cmov is a 32-bit cop insn . However , add3 $ 1 , $ 1 , 1 cmov $ cr0 , $ 0 packs just fine . For good VLIW code generation in VL64 mode , we will have to have 32-bit alternatives for many of the common core insns . Not implemented .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 Lower Tile Copy"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> scalar_chain :: ~ scalar_chain ( ) { BITMAP_FREE ( insns ) ; BITMAP_FREE ( defs ) ; BITMAP_FREE ( defs_conv ) ; BITMAP_FREE ( insns_conv ) ; bitmap_obstack_release ( NULL ) ; } </s>


<s> rtx tilepro_eh_return_handler_rtx ( void ) { rtx tmp = gen_frame_mem ( Pmode , hard_frame_pointer_rtx ) ; MEM_VOLATILE_P ( tmp ) = true ; return tmp ; } </s>


Return an array that contains the direct target flag values and their names .


<s> int pa_attr_length_call ( rtx_insn * insn , int sibcall ) { int local_call ; rtx call , call_dest ; tree call_decl ; int length = 0 ; rtx pat = PATTERN ( insn ) ; unsigned long distance = - 1 ; gcc_assert ( CALL_P ( insn ) ) ; if ( INSN_ADDRESSES_SET_P ( ) ) { unsigned long total ; total = IN_NAMED_SECTION_P ( cfun -> decl ) ? 0 : total_code_bytes ; distance = ( total + insn_current_reference_address ( insn ) ) ; if ( distance < total ) distance = - 1 ; } gcc_assert ( GET_CODE ( pat ) == PARALLEL ) ; call = XVECEXP ( pat , 0 , 0 ) ; if ( GET_CODE ( call ) == SET ) call = SET_SRC ( call ) ; gcc_assert ( GET_CODE ( call ) == CALL ) ; call_dest = XEXP ( XEXP ( call , 0 ) , 0 ) ; call_decl = SYMBOL_REF_DECL ( call_dest ) ; local_call = call_decl && targetm . binds_local_p ( call_decl ) ; if ( ! TARGET_LONG_CALLS && ( ( TARGET_PA_20 && ! sibcall && distance < 7600000 ) || distance < MAX_PCREL17F_OFFSET ) ) length += 8 ; else if ( TARGET_64BIT && ! local_call ) length += 24 ; else if ( ( TARGET_LONG_ABS_CALL || local_call ) && ! flag_pic ) length += 12 ; else if ( TARGET_LONG_PIC_SDIFF_CALL || ( TARGET_GAS && ! TARGET_SOM && local_call ) ) { length += 20 ; if ( ! TARGET_PA_20 && ! TARGET_NO_SPACE_REGS && ( ! local_call || flag_pic ) ) length += 8 ; } else { length += 32 ; if ( TARGET_SOM ) length += length_fp_args ( insn ) ; if ( flag_pic ) length += 4 ; if ( ! TARGET_PA_20 ) { if ( ! sibcall ) length += 8 ; if ( ! TARGET_NO_SPACE_REGS && ( ! local_call || flag_pic ) ) length += 8 ; } } return length ; } </s>

Return the attribute length of the call instruction INSN . The SIBCALL flag indicates whether INSN is a regular call or a sibling call . The length returned must be longer than the code actually generated by pa_output_call . Since branch shortening is done before delay branch sequencing , there is no way to determine whether or not the delay slot will be filled during branch shortening . Even when the delay slot is filled , we may have to add a nop if the delay slot contains a branch that ca n't reach its target . Thus , we always have to include the delay slot in the length estimate . This used to be done in pa_adjust_insn_length but we do it here now as some sequences always fill the delay slot and we can save four bytes in the estimate for these sequences .


<s> bool lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) const { return LowerMMIXMachineOperandToMCOperand ( MO , MCOp , * this ) ; } </s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> void SystemZXPLINKFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool AMDGPUPromoteAlloca :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; if ( auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ) TM = & TPC -> getTM < TargetMachine > ( ) ; else return false ; const Triple & TT = TM -> getTargetTriple ( ) ; IsAMDGCN = TT . getArch ( ) == Triple :: amdgcn ; IsAMDHSA = TT . getOS ( ) == Triple :: AMDHSA ; const AMDGPUSubtarget & ST = AMDGPUSubtarget :: get ( * TM , F ) ; if ( ! ST . isPromoteAllocaEnabled ( ) ) return false ; AS = AMDGPU :: getAMDGPUAS ( * F . getParent ( ) ) ; bool SufficientLDS = hasSufficientLocalMem ( F ) ; bool Changed = false ; BasicBlock & EntryBB = * F . begin ( ) ; for ( auto I = EntryBB . begin ( ) , E = EntryBB . end ( ) ; I != E ; ) { AllocaInst * AI = dyn_cast < AllocaInst > ( I ) ; ++ I ; if ( AI ) Changed |= handleAlloca ( * AI , SufficientLDS ) ; } return Changed ; } </s>

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU::getAMDGPUAS


<s> bool VEAsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool mips_store_data_bypass_p ( rtx_insn * out_insn , rtx_insn * in_insn ) { if ( GET_CODE ( PATTERN ( in_insn ) ) == UNSPEC_VOLATILE ) return false ; return store_data_bypass_p ( out_insn , in_insn ) ; } </s>

True if the dependency between OUT_INSN and IN_INSN is on the store data rather than the address . We need this because the cprestore pattern is type `` store '' , but is defined using an UNSPEC_VOLATILE , which causes the default routine to abort . We just return false for that case .


<s> bool SIDebuggerInsertNops :: runOnMachineFunction ( MachineFunction & MF ) { const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; if ( ! ST . debuggerInsertNops ( ) ) return false ; if ( ! MF . getMMI ( ) . hasDebugInfo ( ) ) return false ; const SIInstrInfo * TII = ST . getInstrInfo ( ) ; DenseSet < unsigned > NopInserted ; for ( auto & MBB : MF ) { for ( auto MI = MBB . begin ( ) ; MI != MBB . end ( ) ; ++ MI ) { if ( MI -> isDebugValue ( ) || ! MI -> getDebugLoc ( ) ) continue ; auto DL = MI -> getDebugLoc ( ) ; if ( NopInserted . find ( DL . getLine ( ) ) == NopInserted . end ( ) ) { BuildMI ( MBB , * MI , DL , TII -> get ( AMDGPU :: S_NOP ) ) . addImm ( 0 ) ; NopInserted . insert ( DL . getLine ( ) ) ; } } } return true ; } </s>

runOnMachineFunction - Emit the function body .


<s>
void
ARM64InstrInfo
::
suppressLdStPair
(
MachineInstr
*
MI
)
const
{
if
(
MI
->
memoperands_empty
(
)
)
return
;
assert
(
MOSuppressPair
<
(
1
<<
MachineMemOperand
::
MOTargetNumBits
)
&&
"Too many target MO flags"
)
;
(
*
MI
->
memoperands_begin
(
)
)
->
setFlags
(
MOSuppressPair
<<
MachineMemOperand
::
MOTargetStartBit
)
;
}
</s>

Hint that pairing the given load or store is unprofitable .


<s> static rtx xtensa_builtin_saveregs ( void ) { rtx gp_regs , dest ; int arg_words = current_function_args_info . arg_words ; int gp_left = MAX_ARGS_IN_REGISTERS - arg_words ; if ( gp_left <= 0 ) return const0_rtx ; gp_regs = assign_stack_local ( BLKmode , MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD , - 1 ) ; set_mem_alias_set ( gp_regs , get_varargs_alias_set ( ) ) ; dest = change_address ( gp_regs , SImode , plus_constant ( XEXP ( gp_regs , 0 ) , arg_words * UNITS_PER_WORD ) ) ; cfun -> machine -> need_a7_copy = true ; cfun -> machine -> vararg_a7 = true ; move_block_from_reg ( GP_ARG_FIRST + arg_words , dest , gp_left ) ; return XEXP ( gp_regs , 0 ) ; } </s>

Save the incoming argument registers on the stack . Returns the address of the saved registers .


<s> bool X86InstrInfo :: findCommutedOpIndices ( MachineInstr * MI , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { switch ( MI -> getOpcode ( ) ) { case X86 :: BLENDPDrri : case X86 :: BLENDPSrri : case X86 :: PBLENDWrri : case X86 :: VBLENDPDrri : case X86 :: VBLENDPSrri : case X86 :: VBLENDPDYrri : case X86 :: VBLENDPSYrri : case X86 :: VPBLENDDrri : case X86 :: VPBLENDDYrri : case X86 :: VPBLENDWrri : case X86 :: VPBLENDWYrri : SrcOpIdx1 = 1 ; SrcOpIdx2 = 2 ; return true ; case X86 :: VFMADDPDr231r : case X86 :: VFMADDPSr231r : case X86 :: VFMADDSDr231r : case X86 :: VFMADDSSr231r : case X86 :: VFMSUBPDr231r : case X86 :: VFMSUBPSr231r : case X86 :: VFMSUBSDr231r : case X86 :: VFMSUBSSr231r : case X86 :: VFNMADDPDr231r : case X86 :: VFNMADDPSr231r : case X86 :: VFNMADDSDr231r : case X86 :: VFNMADDSSr231r : case X86 :: VFNMSUBPDr231r : case X86 :: VFNMSUBPSr231r : case X86 :: VFNMSUBSDr231r : case X86 :: VFNMSUBSSr231r : case X86 :: VFMADDPDr231rY : case X86 :: VFMADDPSr231rY : case X86 :: VFMSUBPDr231rY : case X86 :: VFMSUBPSr231rY : case X86 :: VFNMADDPDr231rY : case X86 :: VFNMADDPSr231rY : case X86 :: VFNMSUBPDr231rY : case X86 :: VFNMSUBPSr231rY : SrcOpIdx1 = 2 ; SrcOpIdx2 = 3 ; return true ; default : return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; } } </s>

Returns true iff the routine could find two commutable operands in the given machine instruction .


<s> bool HexagonTargetLowering :: IsEligibleForTailCallOptimization ( SDValue Callee , CallingConv :: ID CalleeCC , bool IsVarArg , bool IsCalleeStructRet , bool IsCallerStructRet , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SmallVectorImpl < ISD :: InputArg > & Ins , SelectionDAG & DAG ) const { const Function & CallerF = DAG . getMachineFunction ( ) . getFunction ( ) ; CallingConv :: ID CallerCC = CallerF . getCallingConv ( ) ; bool CCMatch = CallerCC == CalleeCC ; if ( ! isa < GlobalAddressSDNode > ( Callee ) && ! isa < ExternalSymbolSDNode > ( Callee ) ) { return false ; } if ( ! CCMatch ) { bool R = ( CallerCC == CallingConv :: C || CallerCC == CallingConv :: Fast ) ; bool E = ( CalleeCC == CallingConv :: C || CalleeCC == CallingConv :: Fast ) ; if ( ! R || ! E ) return false ; } if ( IsVarArg ) return false ; if ( IsCalleeStructRet || IsCallerStructRet ) return false ; return true ; } </s>

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization .

Hexagon Hexagon ISD::OutputArg ISD::InputArg


<s> static void rs6000_set_up_by_prologue ( struct hard_reg_set_container * set ) { if ( ! TARGET_SINGLE_PIC_BASE && TARGET_TOC && TARGET_MINIMAL_TOC && ! constant_pool_empty_p ( ) ) add_to_hard_reg_set ( & set -> set , Pmode , RS6000_PIC_OFFSET_TABLE_REGNUM ) ; if ( cfun -> machine -> split_stack_argp_used ) add_to_hard_reg_set ( & set -> set , Pmode , 12 ) ; if ( TARGET_TOC ) remove_from_hard_reg_set ( & set -> set , Pmode , TOC_REGNUM ) ; } </s>

Add r30 to hard reg set if the prologue sets it up and it is not pic_offset_table_rtx .


<s> int X86FrameLowering :: mergeSPUpdates ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , bool doMergeWithPrevious ) const { if ( ( doMergeWithPrevious && MBBI == MBB . begin ( ) ) || ( ! doMergeWithPrevious && MBBI == MBB . end ( ) ) ) return 0 ; MachineBasicBlock :: iterator PI = doMergeWithPrevious ? std :: prev ( MBBI ) : MBBI ; PI = skipDebugInstructionsBackward ( PI , MBB . begin ( ) ) ; if ( doMergeWithPrevious && PI != MBB . begin ( ) && PI -> isCFIInstruction ( ) ) PI = std :: prev ( PI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = 0 ; if ( ( Opc == X86 :: ADD64ri32 || Opc == X86 :: ADD64ri8 || Opc == X86 :: ADD32ri || Opc == X86 :: ADD32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { assert ( PI -> getOperand ( 1 ) . getReg ( ) == StackPtr ) ; Offset = PI -> getOperand ( 2 ) . getImm ( ) ; } else if ( ( Opc == X86 :: LEA32r || Opc == X86 :: LEA64_32r ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr && PI -> getOperand ( 1 ) . getReg ( ) == StackPtr && PI -> getOperand ( 2 ) . getImm ( ) == 1 && PI -> getOperand ( 3 ) . getReg ( ) == X86 :: NoRegister && PI -> getOperand ( 5 ) . getReg ( ) == X86 :: NoRegister ) { Offset = PI -> getOperand ( 4 ) . getImm ( ) ; } else if ( ( Opc == X86 :: SUB64ri32 || Opc == X86 :: SUB64ri8 || Opc == X86 :: SUB32ri || Opc == X86 :: SUB32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { assert ( PI -> getOperand ( 1 ) . getReg ( ) == StackPtr ) ; Offset = - PI -> getOperand ( 2 ) . getImm ( ) ; } else return 0 ; PI = MBB . erase ( PI ) ; if ( PI != MBB . end ( ) && PI -> isCFIInstruction ( ) ) { auto CIs = MBB . getParent ( ) -> getFrameInstructions ( ) ; MCCFIInstruction CI = CIs [ PI -> getOperand ( 0 ) . getCFIIndex ( ) ] ; if ( CI . getOperation ( ) == MCCFIInstruction :: OpDefCfaOffset || CI . getOperation ( ) == MCCFIInstruction :: OpAdjustCfaOffset ) PI = MBB . erase ( PI ) ; } if ( ! doMergeWithPrevious ) MBBI = skipDebugInstructionsForward ( PI , MBB . end ( ) ) ; return Offset ; } </s>

Check the instruction before/after the passed instruction .


"-fstack-check=specific not implemented for MIPS16"

Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE , inclusive . These are offsets from the current stack pointer .


<s>
void
WebAssemblyInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
OS
,
StringRef
Annot
,
const
MCSubtargetInfo
&
)
{
printInstruction
(
MI
,
OS
)
;
const
MCInstrDesc
&
Desc
=
MII
.
get
(
MI
->
getOpcode
(
)
)
;
if
(
Desc
.
isVariadic
(
)
)
for
(
auto
i
=
Desc
.
getNumOperands
(
)
,
e
=
MI
->
getNumOperands
(
)
;
i
<
e
;
++
i
)
{
if
(
i
!=
0
)
OS
<<
", "
;
printOperand
(
MI
,
i
,
OS
)
;
}
printAnnotation
(
OS
,
Annot
)
;
if
(
CommentStream
)
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
WebAssembly
::
LOOP
:
{
uint64_t
TopLabel
=
ControlFlowCounter
++
;
ControlFlowStack
.
push_back
(
std
::
make_pair
(
ControlFlowCounter
++
,
false
)
)
;
printAnnotation
(
OS
,
"label"
+
utostr
(
TopLabel
)
+
':'
)
;
ControlFlowStack
.
push_back
(
std
::
make_pair
(
TopLabel
,
true
)
)
;
break
;
}
case
WebAssembly
::
BLOCK
:
ControlFlowStack
.
push_back
(
std
::
make_pair
(
ControlFlowCounter
++
,
false
)
)
;
break
;
case
WebAssembly
::
END_LOOP
:
ControlFlowStack
.
pop_back
(
)
;
printAnnotation
(
OS
,
"label"
+
utostr
(
ControlFlowStack
.
pop_back_val
(
)
.
first
)
+
':'
)
;
break
;
case
WebAssembly
::
END_BLOCK
:
printAnnotation
(
OS
,
"label"
+
utostr
(
ControlFlowStack
.
pop_back_val
(
)
.
first
)
+
':'
)
;
break
;
}
unsigned
NumFixedOperands
=
Desc
.
NumOperands
;
SmallSet
<
uint64_t
,
8
>
Printed
;
for
(
unsigned
i
=
0
,
e
=
MI
->
getNumOperands
(
)
;
i
<
e
;
++
i
)
{
const
MCOperandInfo
&
Info
=
Desc
.
OpInfo
[
i
]
;
if
(
!
(
i
<
NumFixedOperands
(
Info
.
OperandType
==
WebAssembly
::
OPERAND_BASIC_BLOCK
)
:
(
Desc
.
TSFlags
&
WebAssemblyII
::
VariableOpImmediateIsLabel
)
)
)
continue
;
uint64_t
Depth
=
MI
->
getOperand
(
i
)
.
getImm
(
)
;
if
(
!
Printed
.
insert
(
Depth
)
.
second
)
continue
;
const
auto
&
Pair
=
ControlFlowStack
.
rbegin
(
)
[
Depth
]
;
printAnnotation
(
OS
,
utostr
(
Depth
)
+
": "
+
(
Pair
.
second
"up"
:
"down"
)
+
" to label"
+
utostr
(
Pair
.
first
)
)
;
}
}
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s> void emitSparcRegisterScratch ( unsigned reg ) override { } </s>

Emit `` .register < reg > , # scratch '' .


<s>
const
char
*
nds32_output_32bit_load_s
(
rtx
*
operands
,
int
byte
)
{
char
pattern
[
100
]
;
unsigned
char
size
;
rtx
code
;
code
=
XEXP
(
operands
[
1
]
,
0
)
;
size
=
nds32_byte_to_size
(
byte
)
;
switch
(
GET_CODE
(
code
)
)
{
case
REG
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%csi\t%%0, %%1"
,
size
)
;
break
;
case
SYMBOL_REF
:
case
CONST
:
operands
[
1
]
=
XEXP
(
operands
[
1
]
,
0
)
;
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%csi.gp\t%%0, [ + %%1]"
,
size
)
;
break
;
case
POST_INC
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%csi.bi\t%%0, %%1, %d"
,
size
,
byte
)
;
break
;
case
POST_DEC
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%csi.bi\t%%0, %%1, -%d"
,
size
,
byte
)
;
break
;
case
POST_MODIFY
:
switch
(
GET_CODE
(
XEXP
(
XEXP
(
code
,
1
)
,
1
)
)
)
{
case
REG
:
case
SUBREG
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%cs.bi\t%%0, %%1"
,
size
)
;
break
;
case
CONST_INT
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%csi.bi\t%%0, %%1"
,
size
)
;
break
;
default
:
abort
(
)
;
}
break
;
case
PLUS
:
switch
(
GET_CODE
(
XEXP
(
code
,
1
)
)
)
{
case
REG
:
case
SUBREG
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%cs\t%%0, %%1"
,
size
)
;
break
;
case
CONST_INT
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%csi\t%%0, %%1"
,
size
)
;
break
;
default
:
abort
(
)
;
}
break
;
case
LO_SUM
:
operands
[
2
]
=
XEXP
(
code
,
1
)
;
operands
[
1
]
=
XEXP
(
code
,
0
)
;
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%csi\t%%0, [%%1 + lo12(%%2)]"
,
size
)
;
break
;
default
:
abort
(
)
;
}
output_asm_insn
(
pattern
,
operands
)
;
return
""
;
}
</s>

Output 32-bit load with signed extension .


<s> bool X86InstrInfo :: isReallyTriviallyReMaterializable ( const MachineInstr * MI , AliasAnalysis * AA ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case X86 :: MOV8rm : case X86 :: MOV16rm : case X86 :: MOV32rm : case X86 :: MOV64rm : case X86 :: LD_Fp64m : case X86 :: MOVSSrm : case X86 :: MOVSDrm : case X86 :: MOVAPSrm : case X86 :: MOVUPSrm : case X86 :: MOVAPDrm : case X86 :: MOVDQArm : case X86 :: MOVDQUrm : case X86 :: VMOVSSrm : case X86 :: VMOVSDrm : case X86 :: VMOVAPSrm : case X86 :: VMOVUPSrm : case X86 :: VMOVAPDrm : case X86 :: VMOVDQArm : case X86 :: VMOVDQUrm : case X86 :: VMOVAPSYrm : case X86 :: VMOVUPSYrm : case X86 :: VMOVAPDYrm : case X86 :: VMOVDQAYrm : case X86 :: VMOVDQUYrm : case X86 :: MMX_MOVD64rm : case X86 :: MMX_MOVQ64rm : case X86 :: FsVMOVAPSrm : case X86 :: FsVMOVAPDrm : case X86 :: FsMOVAPSrm : case X86 :: FsMOVAPDrm : { if ( MI -> getOperand ( 1 ) . isReg ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 3 ) . isReg ( ) && MI -> getOperand ( 3 ) . getReg ( ) == 0 && MI -> isInvariantLoad ( AA ) ) { unsigned BaseReg = MI -> getOperand ( 1 ) . getReg ( ) ; if ( BaseReg == 0 || BaseReg == X86 :: RIP ) return true ; if ( ! ReMatPICStubLoad && MI -> getOperand ( 4 ) . isGlobal ( ) ) return false ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; return regIsPICBase ( BaseReg , MRI ) ; } return false ; } case X86 :: LEA32r : case X86 :: LEA64r : { if ( MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 3 ) . isReg ( ) && MI -> getOperand ( 3 ) . getReg ( ) == 0 && ! MI -> getOperand ( 4 ) . isReg ( ) ) { if ( ! MI -> getOperand ( 1 ) . isReg ( ) ) return true ; unsigned BaseReg = MI -> getOperand ( 1 ) . getReg ( ) ; if ( BaseReg == 0 ) return true ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; return regIsPICBase ( BaseReg , MRI ) ; } return false ; } } return true ; } </s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> rtx resolve_reload_operand ( rtx op ) { if ( reload_in_progress ) { rtx tmp = op ; if ( GET_CODE ( tmp ) == SUBREG ) tmp = SUBREG_REG ( tmp ) ; if ( GET_CODE ( tmp ) == REG && REGNO ( tmp ) >= FIRST_PSEUDO_REGISTER ) { op = reg_equiv_memory_loc [ REGNO ( tmp ) ] ; if ( op == 0 ) return 0 ; } } return op ; } </s>

Used by aligned_memory_operand and unaligned_memory_operand to resolve what reload is going to do with OP if it 's a register .


<s> HOST_WIDE_INT alpha_initial_elimination_offset ( unsigned int from , unsigned int to ATTRIBUTE_UNUSED ) { HOST_WIDE_INT ret ; ret = cfun -> machine -> sa_size ; ret += ALPHA_ROUND ( crtl -> outgoing_args_size ) ; switch ( from ) { case FRAME_POINTER_REGNUM : break ; case ARG_POINTER_REGNUM : ret += ( ALPHA_ROUND ( get_frame_size ( ) + crtl -> args . pretend_args_size ) - crtl -> args . pretend_args_size ) ; break ; default : gcc_unreachable ( ) ; } return ret ; } </s>

Define the offset between two registers , one to be eliminated , and the other its replacement , at the start of a routine .


<s> rtx thumb_legitimize_address ( rtx x , rtx orig_x , enum machine_mode mode ) { if ( arm_tls_symbol_p ( x ) ) return legitimize_tls_address ( x , NULL_RTX ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT && ( INTVAL ( XEXP ( x , 1 ) ) >= 32 * GET_MODE_SIZE ( mode ) || INTVAL ( XEXP ( x , 1 ) ) < 0 ) ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; HOST_WIDE_INT offset = INTVAL ( xop1 ) ; if ( optimize_size && offset >= 0 && offset < 256 + 31 * GET_MODE_SIZE ( mode ) ) { HOST_WIDE_INT delta ; if ( offset >= 256 ) delta = offset - ( 256 - GET_MODE_SIZE ( mode ) ) ; else if ( offset < 32 * GET_MODE_SIZE ( mode ) + 8 ) delta = 31 * GET_MODE_SIZE ( mode ) ; else delta = offset & ( ~ 31 * GET_MODE_SIZE ( mode ) ) ; xop0 = force_operand ( plus_constant ( xop0 , offset - delta ) , NULL_RTX ) ; x = plus_constant ( xop0 , delta ) ; } else if ( offset < 0 && offset > - 256 ) x = force_operand ( x , NULL_RTX ) ; else { xop1 = force_reg ( SImode , xop1 ) ; x = gen_rtx_PLUS ( SImode , xop0 , xop1 ) ; } } else if ( GET_CODE ( x ) == PLUS && s_register_operand ( XEXP ( x , 1 ) , SImode ) && ! s_register_operand ( XEXP ( x , 0 ) , SImode ) ) { rtx xop0 = force_operand ( XEXP ( x , 0 ) , NULL_RTX ) ; x = gen_rtx_PLUS ( SImode , xop0 , XEXP ( x , 1 ) ) ; } if ( flag_pic ) { rtx new_x = legitimize_pic_address ( orig_x , mode , NULL_RTX ) ; if ( new_x != orig_x ) x = new_x ; } return x ; } </s>

Try machine-dependent ways of modifying an illegitimate Thumb address to be legitimate . If we find one , return the new , valid address .


<s> static bool cbranch_predicted_p ( rtx_insn * insn ) { rtx x = find_reg_note ( insn , REG_BR_PROB , 0 ) ; if ( x ) { int pred_val = XINT ( x , 0 ) ; return pred_val >= REG_BR_PROB_BASE / 2 ; } return false ; } </s>

Return true if INSN is annotated with a REG_BR_PROB note that indicates it 's a branch that 's predicted taken .


<s> static void vms_asm_out_constructor ( rtx symbol , int priority ATTRIBUTE_UNUSED ) { ctors_section ( ) ; assemble_align ( BITS_PER_WORD ) ; assemble_integer ( symbol , UNITS_PER_WORD , BITS_PER_WORD , 1 ) ; } </s>


<s> bool AArch64AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , const char * ExtraCode , raw_ostream & O ) { const MachineOperand & MO = MI -> getOperand ( OpNum ) ; if ( ! AsmPrinter :: PrintAsmOperand ( MI , OpNum , ExtraCode , O ) ) return false ; if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'w' : case 'x' : if ( MO . isReg ( ) ) return printAsmMRegister ( MO , ExtraCode [ 0 ] , O ) ; if ( MO . isImm ( ) && MO . getImm ( ) == 0 ) { unsigned Reg = ExtraCode [ 0 ] == 'w' ? AArch64 :: WZR : AArch64 :: XZR ; O << AArch64InstPrinter :: getRegisterName ( Reg ) ; return false ; } printOperand ( MI , OpNum , O ) ; return false ; case 'b' : case 'h' : case 's' : case 'd' : case 'q' : if ( MO . isReg ( ) ) { const TargetRegisterClass * RC ; switch ( ExtraCode [ 0 ] ) { case 'b' : RC = & AArch64 :: FPR8RegClass ; break ; case 'h' : RC = & AArch64 :: FPR16RegClass ; break ; case 's' : RC = & AArch64 :: FPR32RegClass ; break ; case 'd' : RC = & AArch64 :: FPR64RegClass ; break ; case 'q' : RC = & AArch64 :: FPR128RegClass ; break ; default : return true ; } return printAsmRegInClass ( MO , RC , false , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } } if ( MO . isReg ( ) ) { Register Reg = MO . getReg ( ) ; if ( AArch64 :: GPR32allRegClass . contains ( Reg ) || AArch64 :: GPR64allRegClass . contains ( Reg ) ) return printAsmMRegister ( MO , 'x' , O ) ; return printAsmRegInClass ( MO , & AArch64 :: FPR128RegClass , true , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> bool WebAssemblyFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> SDValue X86TargetLowering :: getNegatedExpression ( SDValue Op , SelectionDAG & DAG , bool LegalOperations , bool ForCodeSize , NegatibleCost & Cost , unsigned Depth ) const { if ( SDValue Arg = isFNEG ( DAG , Op . getNode ( ) , Depth ) ) { Cost = NegatibleCost :: Cheaper ; return DAG . getBitcast ( Op . getValueType ( ) , Arg ) ; } EVT VT = Op . getValueType ( ) ; EVT SVT = VT . getScalarType ( ) ; unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { case ISD :: FMA : case X86ISD :: FMSUB : case X86ISD :: FNMADD : case X86ISD :: FNMSUB : case X86ISD :: FMADD_RND : case X86ISD :: FMSUB_RND : case X86ISD :: FNMADD_RND : case X86ISD :: FNMSUB_RND : { if ( ! Op . hasOneUse ( ) || ! Subtarget . hasAnyFMA ( ) || ! isTypeLegal ( VT ) || ! ( SVT == MVT :: f32 || SVT == MVT :: f64 ) || ! isOperationLegal ( ISD :: FMA , VT ) ) break ; SmallVector < SDValue , 4 > NewOps ( Op . getNumOperands ( ) , SDValue ( ) ) ; for ( int i = 0 ; i != 3 ; ++ i ) NewOps [ i ] = getCheaperNegatedExpression ( Op . getOperand ( i ) , DAG , LegalOperations , ForCodeSize , Depth + 1 ) ; bool NegA = ! ! NewOps [ 0 ] ; bool NegB = ! ! NewOps [ 1 ] ; bool NegC = ! ! NewOps [ 2 ] ; unsigned NewOpc = negateFMAOpcode ( Opc , NegA != NegB , NegC , true ) ; Cost = ( NegA || NegB || NegC ) ? NegatibleCost :: Cheaper : NegatibleCost :: Neutral ; for ( int i = 0 , e = Op . getNumOperands ( ) ; i != e ; ++ i ) if ( ! NewOps [ i ] ) NewOps [ i ] = Op . getOperand ( i ) ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , VT , NewOps ) ; } case X86ISD :: FRCP : if ( SDValue NegOp0 = getNegatedExpression ( Op . getOperand ( 0 ) , DAG , LegalOperations , ForCodeSize , Cost , Depth + 1 ) ) return DAG . getNode ( Opc , SDLoc ( Op ) , VT , NegOp0 ) ; break ; } return TargetLowering :: getNegatedExpression ( Op , DAG , LegalOperations , ForCodeSize , Cost , Depth ) ; } </s>

Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate that if it is cheaper or neutral to do the negation .


<s> const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> bool PPCInstrInfo :: ClobbersPredicate ( MachineInstr & MI , std :: vector < MachineOperand > & Pred , bool SkipDead ) const { const TargetRegisterClass * RCs [ ] = { & PPC :: CRRCRegClass , & PPC :: CRBITRCRegClass , & PPC :: CTRRCRegClass , & PPC :: CTRRC8RegClass } ; bool Found = false ; for ( const MachineOperand & MO : MI . operands ( ) ) { for ( unsigned c = 0 ; c < array_lengthof ( RCs ) && ! Found ; ++ c ) { const TargetRegisterClass * RC = RCs [ c ] ; if ( MO . isReg ( ) ) { if ( MO . isDef ( ) && RC -> contains ( MO . getReg ( ) ) ) { Pred . push_back ( MO ) ; Found = true ; } } else if ( MO . isRegMask ( ) ) { for ( TargetRegisterClass :: iterator I = RC -> begin ( ) , IE = RC -> end ( ) ; I != IE ; ++ I ) if ( MO . clobbersPhysReg ( * I ) ) { Pred . push_back ( MO ) ; Found = true ; } } } } return Found ; } </s>

If the specified instruction defines any predicate or condition code register ( s ) used for predication , returns true as well as the definition predicate ( s ) by reference .

PowerPC PPC PPC::CRRCRegClass PPC::CRBITRCRegClass PPC::CTRRCRegClass PPC::CTRRC8RegClass 0


<s> bool VideocorePassConfig :: addInstSelector ( ) { addPass ( createVideocoreISelDag ( getVideocoreTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s>
SDValue
LanaiTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
MUL
:
return
LowerMUL
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
case
ISD
::
SHL_PARTS
:
return
LowerSHL_PARTS
(
Op
,
DAG
)
;
case
ISD
::
SRL_PARTS
:
return
LowerSRL_PARTS
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

Lanai
Lanai
ISD::MUL
ISD::BR_CC
ISD::ConstantPool
ISD::GlobalAddress
ISD::BlockAddress
ISD::JumpTable
ISD::SELECT_CC
ISD::SETCC
ISD::SHL_PARTS
ISD::SRL_PARTS
ISD::VASTART
ISD::DYNAMIC_STACKALLOC
ISD::RETURNADDR
ISD::FRAMEADDR
"unimplemented operand"


<s>
SDValue
MCS51TargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
if
(
CallConv
==
CallingConv
::
MCS51_BUILTIN
)
{
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_MCS51_BUILTIN
)
;
}
else
{
analyzeReturnValues
(
Outs
,
CCInfo
)
;
}
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
if
(
MF
.
getFunction
(
)
.
getAttributes
(
)
.
hasAttribute
(
AttributeList
::
FunctionIndex
,
Attribute
::
Naked
)
)
{
return
Chain
;
}
const
MCS51MachineFunctionInfo
*
AFI
=
MF
.
getInfo
<
MCS51MachineFunctionInfo
>
(
)
;
unsigned
RetOpc
=
AFI
->
isInterruptOrSignalHandler
(
)
MCS51ISD
::
RETI_FLAG
:
MCS51ISD
::
RET_FLAG
;
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
{
RetOps
.
push_back
(
Flag
)
;
}
return
DAG
.
getNode
(
RetOpc
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool XCoreTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , const Type * Ty ) const { MVT VT = getValueType ( Ty , true ) ; switch ( VT . getSimpleVT ( ) ) { case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : break ; case MVT :: i1 : VT = MVT :: i8 ; break ; default : VT = MVT :: i32 ; break ; } if ( AM . BaseGV ) { return VT == MVT :: i32 && ! AM . HasBaseReg && AM . Scale == 0 && AM . BaseOffs % 4 == 0 ; } switch ( VT . getSimpleVT ( ) ) { default : return false ; case MVT :: i8 : if ( AM . Scale == 0 ) { return isImmUs ( AM . BaseOffs ) ; } return AM . Scale == 1 && AM . BaseOffs == 0 ; case MVT :: i16 : if ( AM . Scale == 0 ) { return isImmUs2 ( AM . BaseOffs ) ; } return AM . Scale == 2 && AM . BaseOffs == 0 ; case MVT :: i32 : if ( AM . Scale == 0 ) { return isImmUs4 ( AM . BaseOffs ) ; } return AM . Scale == 4 && AM . BaseOffs == 0 ; } return false ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s>
AsmToken
LexToken
(
)
{
if
(
!
Lexer
)
{
SetError
(
SMLoc
(
)
,
"No MCAsmLexer installed"
)
;
return
AsmToken
(
AsmToken
::
Error
,
""
,
0
)
;
}
switch
(
AsmInfo
.
getAssemblerDialect
(
)
)
{
default
:
SetError
(
SMLoc
(
)
,
"Unhandled dialect"
)
;
return
AsmToken
(
AsmToken
::
Error
,
""
,
0
)
;
case
0
:
return
LexTokenUAL
(
)
;
}
}
</s>

LexToken - Read the next token and return its code .


<s>
bool
Emitter
<
CodeEmitter
>
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MMI
=
&
getAnalysis
<
MachineModuleInfo
>
(
)
;
MCE
.
setModuleInfo
(
MMI
)
;
II
=
TM
.
getInstrInfo
(
)
;
TD
=
TM
.
getDataLayout
(
)
;
Is64BitMode
=
TM
.
getSubtarget
<
X86Subtarget
>
(
)
.
is64Bit
(
)
;
IsPIC
=
TM
.
getRelocationModel
(
)
==
Reloc
::
PIC_
;
do
{
DEBUG
(
dbgs
(
)
<<
"JITTing function '"
<<
MF
.
getName
(
)
<<
"'\n"
)
;
MCE
.
startFunction
(
MF
)
;
for
(
MachineFunction
::
iterator
MBB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBB
!=
E
;
++
MBB
)
{
MCE
.
StartMachineBasicBlock
(
MBB
)
;
for
(
MachineBasicBlock
::
iterator
I
=
MBB
->
begin
(
)
,
E
=
MBB
->
end
(
)
;
I
!=
E
;
++
I
)
{
const
MCInstrDesc
&
Desc
=
I
->
getDesc
(
)
;
emitInstruction
(
*
I
,
&
Desc
)
;
if
(
Desc
.
getOpcode
(
)
==
X86
::
MOVPC32r
)
emitInstruction
(
*
I
,
&
II
->
get
(
X86
::
POP32r
)
)
;
++
NumEmitted
;
}
}
}
while
(
MCE
.
finishFunction
(
MF
)
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s>
void
AArch64TargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this"
)
;
case
ISD
::
BITCAST
:
ReplaceBITCASTResults
(
N
,
Results
,
DAG
)
;
return
;
case
AArch64ISD
::
SADDV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
ADD
,
AArch64ISD
::
SADDV
)
;
return
;
case
AArch64ISD
::
UADDV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
ADD
,
AArch64ISD
::
UADDV
)
;
return
;
case
AArch64ISD
::
SMINV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
SMIN
,
AArch64ISD
::
SMINV
)
;
return
;
case
AArch64ISD
::
UMINV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
UMIN
,
AArch64ISD
::
UMINV
)
;
return
;
case
AArch64ISD
::
SMAXV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
SMAX
,
AArch64ISD
::
SMAXV
)
;
return
;
case
AArch64ISD
::
UMAXV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
UMAX
,
AArch64ISD
::
UMAXV
)
;
return
;
case
ISD
::
FP_TO_UINT
:
case
ISD
::
FP_TO_SINT
:
assert
(
N
->
getValueType
(
0
)
==
MVT
::
i128
&&
"unexpected illegal conversion"
)
;
return
;
case
ISD
::
ATOMIC_CMP_SWAP
:
ReplaceCMP_SWAP_128Results
(
N
,
Results
,
DAG
)
;
return
;
}
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


"All regions recorded, starting actual scheduling.\n"

"Retrying function scheduling without clustering.\n"

"Retrying function scheduling with lowest recorded occupancy "

After the schedule has been formed , call this function to combine the instructions from the different stages/cycles .


<s> bool DLXInstrInfo :: analyzeCompare ( const MachineInstr & MI , unsigned & SrcReg , unsigned & SrcReg2 , int & CmpMask , int & CmpValue ) const { return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> TargetIRAnalysis HexagonTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( Function & F ) { return TargetTransformInfo ( HexagonTTIImpl ( this , F ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


<s> static void msp430_compute_frame_info ( void ) { int i ; cfun -> machine -> computed = 1 ; cfun -> machine -> framesize_regs = 0 ; cfun -> machine -> framesize_locals = get_frame_size ( ) ; cfun -> machine -> framesize_outgoing = crtl -> outgoing_args_size ; for ( i = 0 ; i < ARG_POINTER_REGNUM ; i ++ ) if ( msp430_preserve_reg_p ( i ) ) { cfun -> machine -> need_to_save [ i ] = 1 ; cfun -> machine -> framesize_regs += ( TARGET_LARGE ? 4 : 2 ) ; } else cfun -> machine -> need_to_save [ i ] = 0 ; if ( ( cfun -> machine -> framesize_locals + cfun -> machine -> framesize_outgoing ) & 1 ) cfun -> machine -> framesize_locals ++ ; cfun -> machine -> framesize = ( cfun -> machine -> framesize_regs + cfun -> machine -> framesize_locals + cfun -> machine -> framesize_outgoing ) ; } </s>

Compute all the frame-related fields in our machine_function structure .


<s> const char * XCoreTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case XCoreISD :: BL : return "XCoreISD::BL" ; case XCoreISD :: PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper" ; case XCoreISD :: DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper" ; case XCoreISD :: CPRelativeWrapper : return "XCoreISD::CPRelativeWrapper" ; case XCoreISD :: LDWSP : return "XCoreISD::LDWSP" ; case XCoreISD :: STWSP : return "XCoreISD::STWSP" ; case XCoreISD :: RETSP : return "XCoreISD::RETSP" ; case XCoreISD :: LADD : return "XCoreISD::LADD" ; case XCoreISD :: LSUB : return "XCoreISD::LSUB" ; case XCoreISD :: LMUL : return "XCoreISD::LMUL" ; case XCoreISD :: MACCU : return "XCoreISD::MACCU" ; case XCoreISD :: MACCS : return "XCoreISD::MACCS" ; case XCoreISD :: CRC8 : return "XCoreISD::CRC8" ; case XCoreISD :: BR_JT : return "XCoreISD::BR_JT" ; case XCoreISD :: BR_JT32 : return "XCoreISD::BR_JT32" ; case XCoreISD :: FRAME_TO_ARGS_OFFSET : return "XCoreISD::FRAME_TO_ARGS_OFFSET" ; case XCoreISD :: EH_RETURN : return "XCoreISD::EH_RETURN" ; case XCoreISD :: MEMBARRIER : return "XCoreISD::MEMBARRIER" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific

XCore XCore XCoreISD::BL "XCoreISD::BL" XCoreISD::PCRelativeWrapper "XCoreISD::PCRelativeWrapper" XCoreISD::DPRelativeWrapper "XCoreISD::DPRelativeWrapper" XCoreISD::CPRelativeWrapper "XCoreISD::CPRelativeWrapper" XCoreISD::LDWSP "XCoreISD::LDWSP" XCoreISD::STWSP "XCoreISD::STWSP" XCoreISD::RETSP "XCoreISD::RETSP" XCoreISD::LADD "XCoreISD::LADD" XCoreISD::LSUB "XCoreISD::LSUB" XCoreISD::LMUL "XCoreISD::LMUL" XCoreISD::MACCU "XCoreISD::MACCU" XCoreISD::MACCS "XCoreISD::MACCS" XCoreISD::CRC8 "XCoreISD::CRC8" XCoreISD::BR_JT "XCoreISD::BR_JT" XCoreISD::BR_JT32 "XCoreISD::BR_JT32" XCoreISD::FRAME_TO_ARGS_OFFSET "XCoreISD::FRAME_TO_ARGS_OFFSET" XCoreISD::EH_RETURN "XCoreISD::EH_RETURN" XCoreISD::MEMBARRIER "XCoreISD::MEMBARRIER"


<s> static bool rs6000_mode_dependent_address_p ( const_rtx addr , addr_space_t as ATTRIBUTE_UNUSED ) { return rs6000_mode_dependent_address_ptr ( addr ) ; } </s>


<s> bool X86InstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , const SmallVectorImpl < MachineOperand > & Cond , unsigned TrueReg , unsigned FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( ! TM . getSubtarget < X86Subtarget > ( ) . hasCMov ( ) ) return false ; if ( Cond . size ( ) != 1 ) return false ; if ( ( X86 :: CondCode ) Cond [ 0 ] . getImm ( ) > X86 :: COND_S ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( X86 :: GR16RegClass . hasSubClassEq ( RC ) || X86 :: GR32RegClass . hasSubClassEq ( RC ) || X86 :: GR64RegClass . hasSubClassEq ( RC ) ) { CondCycles = 2 ; TrueCycles = 2 ; FalseCycles = 2 ; return true ; } return false ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> static SDValue getAllOnesMask ( MVT VecVT , SDValue VL , SDLoc DL , SelectionDAG & DAG ) { MVT MaskVT = getMaskTypeFor ( VecVT ) ; return DAG . getNode ( RISCVISD :: VMSET_VL , DL , MaskVT , VL ) ; } </s>

Return an all true boolean vector ( mask ) with NumElts lanes .


<s> void AArch64PassConfig :: addPreEmitPass ( ) { if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Aggressive && EnableLoadStoreOpt ) addPass ( createAArch64LoadStoreOptimizationPass ( ) ) ; if ( EnableA53Fix835769 ) addPass ( createAArch64A53Fix835769 ( ) ) ; if ( EnableBranchTargets ) addPass ( createAArch64BranchTargetsPass ( ) ) ; if ( BranchRelaxation ) addPass ( & BranchRelaxationPassID ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) { addPass ( createCFGuardLongjmpPass ( ) ) ; addPass ( createEHContGuardCatchretPass ( ) ) ; } if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCompressJumpTables ) addPass ( createAArch64CompressJumpTablesPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> const uint32_t * AArch64RegisterInfo :: getCustomEHPadPreservedMask ( const MachineFunction & MF ) const { if ( MF . getSubtarget < AArch64Subtarget > ( ) . isTargetLinux ( ) ) return CSR_AArch64_AAPCS_RegMask ; return nullptr ; } </s>

Return a register mask for the registers preserved by the unwinder , or nullptr if no custom mask is needed .


<s>
const
RegisterBank
&
X86RegisterBankInfo
::
getRegBankFromRegClass
(
const
TargetRegisterClass
&
RC
)
const
{
if
(
X86
::
GR8RegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
GR16RegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
GR32RegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
GR64RegClass
.
hasSubClassEq
(
&
RC
)
)
return
getRegBank
(
X86
::
GPRRegBankID
)
;
if
(
X86
::
FR32XRegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
FR64XRegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
VR128XRegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
VR256XRegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
VR512RegClass
.
hasSubClassEq
(
&
RC
)
)
return
getRegBank
(
X86
::
VECRRegBankID
)
;
llvm_unreachable
(
"Unsupported register kind yet."
)
;
}
</s>


<s>
bool
RISCVAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Operands
.
push_back
(
RISCVOperand
::
createToken
(
Name
,
NameLoc
,
isRV64
(
)
)
)
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
return
false
;
if
(
parseOperand
(
Operands
,
Name
)
)
return
true
;
unsigned
OperandIdx
=
1
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
getLexer
(
)
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
)
return
true
;
++
OperandIdx
;
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
getParser
(
)
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
getParser
(
)
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .


<s> unsigned X86TargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { unsigned VTBits = Op . getScalarValueSizeInBits ( ) ; unsigned Opcode = Op . getOpcode ( ) ; switch ( Opcode ) { case X86ISD :: SETCC_CARRY : return VTBits ; case X86ISD :: VSEXT : { SDValue Src = Op . getOperand ( 0 ) ; unsigned Tmp = DAG . ComputeNumSignBits ( Src , Depth + 1 ) ; Tmp += VTBits - Src . getScalarValueSizeInBits ( ) ; return Tmp ; } case X86ISD :: PACKSS : { unsigned SrcBits = Op . getOperand ( 0 ) . getScalarValueSizeInBits ( ) ; unsigned Tmp0 = DAG . ComputeNumSignBits ( Op . getOperand ( 0 ) , Depth + 1 ) ; unsigned Tmp1 = DAG . ComputeNumSignBits ( Op . getOperand ( 1 ) , Depth + 1 ) ; unsigned Tmp = std :: min ( Tmp0 , Tmp1 ) ; if ( Tmp > ( SrcBits - VTBits ) ) return Tmp - ( SrcBits - VTBits ) ; return 1 ; } case X86ISD :: VSHLI : { SDValue Src = Op . getOperand ( 0 ) ; unsigned Tmp = DAG . ComputeNumSignBits ( Src , Depth + 1 ) ; APInt ShiftVal = cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) -> getAPIntValue ( ) ; if ( ShiftVal . uge ( VTBits ) ) return VTBits ; if ( ShiftVal . uge ( Tmp ) ) return 1 ; return Tmp - ShiftVal . getZExtValue ( ) ; } case X86ISD :: VSRAI : { SDValue Src = Op . getOperand ( 0 ) ; unsigned Tmp = DAG . ComputeNumSignBits ( Src , Depth + 1 ) ; APInt ShiftVal = cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) -> getAPIntValue ( ) ; ShiftVal += Tmp ; return ShiftVal . uge ( VTBits ) ? VTBits : ShiftVal . getZExtValue ( ) ; } case X86ISD :: PCMPGT : case X86ISD :: PCMPEQ : case X86ISD :: CMPP : case X86ISD :: VPCOM : case X86ISD :: VPCOMU : return VTBits ; } return 1 ; } </s>

Determine the number of bits in the operation that are sign bits .


<s> const TargetRegisterClass * PPCRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; if ( Subtarget . hasVSX ( ) ) { if ( RC == & PPC :: F8RCRegClass ) return & PPC :: VSFRCRegClass ; else if ( RC == & PPC :: VRRCRegClass ) return & PPC :: VSRCRegClass ; else if ( RC == & PPC :: F4RCRegClass && Subtarget . hasP8Vector ( ) ) return & PPC :: VSSRCRegClass ; } return TargetRegisterInfo :: getLargestLegalSuperClass ( RC , MF ) ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .

PowerPC PPC PPC PPC PPC::F8RCRegClass PPC::VSFRCRegClass PPC::VRRCRegClass PPC::VSRCRegClass PPC::F4RCRegClass PPC::VSSRCRegClass


<s>
const
MCFixupKindInfo
&
TPCAsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
InfosLE
[
TPC
::
NumTargetFixupKinds
]
=
{
{
"fixup_loop"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_loop"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
InfosLE
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> SDValue HexagonTargetLowering :: LowerCallResult ( SDValue Chain , SDValue Glue , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SmallVectorImpl < SDValue > & OutVals , SDValue Callee ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_Hexagon ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { SDValue RetVal ; if ( RVLocs [ i ] . getValVT ( ) == MVT :: i1 ) { auto & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue FR0 = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , MVT :: i32 , Glue ) ; unsigned PredR = MRI . createVirtualRegister ( & Hexagon :: PredRegsRegClass ) ; SDValue TPR = DAG . getCopyToReg ( FR0 . getValue ( 1 ) , dl , PredR , FR0 . getValue ( 0 ) , FR0 . getValue ( 2 ) ) ; RetVal = DAG . getCopyFromReg ( TPR . getValue ( 0 ) , dl , PredR , MVT :: i1 ) ; Glue = TPR . getValue ( 1 ) ; } else { RetVal = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , Glue ) ; Glue = RetVal . getValue ( 2 ) ; } InVals . push_back ( RetVal . getValue ( 0 ) ) ; Chain = RetVal . getValue ( 1 ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> int arm_attr_length_push_multi ( rtx parallel_op , rtx first_op ) { int i , regno , hi_reg ; int num_saves = XVECLEN ( parallel_op , 0 ) ; if ( TARGET_ARM ) return 4 ; if ( TARGET_THUMB1 ) return 2 ; regno = REGNO ( first_op ) ; hi_reg = ( REGNO_REG_CLASS ( regno ) == HI_REGS ) && ( regno != LR_REGNUM ) ; for ( i = 1 ; i < num_saves && ! hi_reg ; i ++ ) { regno = REGNO ( XEXP ( XVECEXP ( parallel_op , 0 , i ) , 0 ) ) ; hi_reg |= ( REGNO_REG_CLASS ( regno ) == HI_REGS ) && ( regno != LR_REGNUM ) ; } if ( ! hi_reg ) return 2 ; return 4 ; } </s>

Compute the atrribute `` length '' of insn `` * push_multi '' . So this function MUST be kept in sync with that insn pattern .


<s> static bool aarch64_evpc_rev_local ( struct expand_vec_perm_d * d ) { HOST_WIDE_INT diff ; unsigned int i , size , unspec ; machine_mode pred_mode ; if ( d -> vec_flags == VEC_SVE_PRED || ! d -> one_vector_p || ! d -> perm [ 0 ] . is_constant ( & diff ) ) return false ; size = ( diff + 1 ) * GET_MODE_UNIT_SIZE ( d -> vmode ) ; if ( size == 8 ) { unspec = UNSPEC_REV64 ; pred_mode = VNx2BImode ; } else if ( size == 4 ) { unspec = UNSPEC_REV32 ; pred_mode = VNx4BImode ; } else if ( size == 2 ) { unspec = UNSPEC_REV16 ; pred_mode = VNx8BImode ; } else return false ; unsigned int step = diff + 1 ; for ( i = 0 ; i < step ; ++ i ) if ( ! d -> perm . series_p ( i , step , diff - i , step ) ) return false ; if ( d -> testing_p ) return true ; rtx src = gen_rtx_UNSPEC ( d -> vmode , gen_rtvec ( 1 , d -> op0 ) , unspec ) ; if ( d -> vec_flags == VEC_SVE_DATA ) { rtx pred = force_reg ( pred_mode , CONSTM1_RTX ( pred_mode ) ) ; src = gen_rtx_UNSPEC ( d -> vmode , gen_rtvec ( 2 , pred , src ) , UNSPEC_MERGE_PTRUE ) ; } emit_set_insn ( d -> target , src ) ; return true ; } </s>

Recognize patterns for the REV { 64,32,16 } insns , which reverse elements within each 64-bit , 32-bit or 16-bit granule .


<s> const MCExpr * getSubExpr ( ) const { return SubExpr ; } </s>

getSubExpr - Get the child of this expression .