<s>
static
void
process_args
(
int
argc
,
char
*
*
argv
)
{
int
i
;
for
(
i
=
1
;
i
<
argc
;
i
++
)
{
if
(
strncmp
(
argv
[
i
]
,
"-L"
,
2
)
==
0
)
{
search_dirs
=
XRESIZEVEC
(
const
char
*
,
search_dirs
,
search_dirs_len
+
1
)
;
search_dirs
[
search_dirs_len
++
]
=
&
argv
[
i
]
[
2
]
;
}
else
if
(
strcmp
(
argv
[
i
]
,
"-v"
)
==
0
)
verbose
++
;
else
if
(
strcmp
(
argv
[
i
]
,
"--version"
)
==
0
)
{
fprintf
(
stdout
,
"VMS Linker\n"
)
;
exit
(
EXIT_SUCCESS
)
;
}
else
if
(
strcmp
(
argv
[
i
]
,
"--help"
)
==
0
)
{
fprintf
(
stdout
,
"VMS Linker\n"
)
;
exit
(
EXIT_SUCCESS
)
;
}
else
if
(
strcmp
(
argv
[
i
]
,
"-g0"
)
==
0
)
addarg
(
"/notraceback"
)
;
else
if
(
strncmp
(
argv
[
i
]
,
"-g"
,
2
)
==
0
)
{
addarg
(
"/debug"
)
;
debug
=
1
;
}
else
if
(
strcmp
(
argv
[
i
]
,
"-static"
)
==
0
)
staticp
=
1
;
else
if
(
strcmp
(
argv
[
i
]
,
"-map"
)
==
0
)
{
char
*
buff
,
*
ptr
;
buff
=
(
char
*
)
xstrdup
(
exefullfilename
)
;
ptr
=
strrchr
(
buff
,
'.'
)
;
if
(
ptr
)
*
ptr
=
0
;
strcat
(
buff
,
".map"
)
;
addarg
(
"/map="
)
;
addarg
(
buff
)
;
addarg
(
".map"
)
;
addarg
(
"/full"
)
;
free
(
buff
)
;
}
else
if
(
strcmp
(
argv
[
i
]
,
"-save-temps"
)
==
0
)
save_temps
=
1
;
else
if
(
strcmp
(
argv
[
i
]
,
"--noinhibit-exec"
)
==
0
)
inhibit_exec
=
0
;
}
}
</s>

Preprocess the number of args ARGC in ARGV . Look for special flags , etc . that must be handled for the VMS linker .


<s> void FISCFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( I -> getOpcode ( ) == FISC :: ADJCALLSTACKUP || I -> getOpcode ( ) == FISC :: ADJCALLSTACKDOWN ) MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

FISC FISC FISC::ADJCALLSTACKUP FISC::ADJCALLSTACKDOWN


<s> static ArgDescriptor createArg ( const ArgDescriptor & Arg , unsigned Mask ) { return ArgDescriptor ( Arg . Reg , Mask , Arg . IsStack , Arg . IsSet ) ; } </s>


<s>
bool
ARM64AsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNum
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
return
true
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNum
)
;
assert
(
MO
.
isReg
(
)
&&
"unexpected inline asm memory operand"
)
;
O
<<
"["
<<
ARM64InstPrinter
::
getRegisterName
(
MO
.
getReg
(
)
)
<<
"]"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> SDValue PPCTargetLowering :: getRecipEstimate ( SDValue Operand , DAGCombinerInfo & DCI , unsigned & RefinementSteps ) const { EVT VT = Operand . getValueType ( ) ; if ( ( VT == MVT :: f32 && Subtarget . hasFRES ( ) ) || ( VT == MVT :: f64 && Subtarget . hasFRE ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasAltivec ( ) ) || ( VT == MVT :: v2f64 && Subtarget . hasVSX ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasQPX ( ) ) || ( VT == MVT :: v4f64 && Subtarget . hasQPX ( ) ) ) { TargetRecip Recips = DCI . DAG . getTarget ( ) . Options . Reciprocals ; std :: string RecipOp = getRecipOp ( "div" , VT ) ; if ( ! Recips . isEnabled ( RecipOp ) ) return SDValue ( ) ; RefinementSteps = Recips . getRefinementSteps ( RecipOp ) ; return DCI . DAG . getNode ( PPCISD :: FRE , SDLoc ( Operand ) , VT , Operand ) ; } return SDValue ( ) ; } </s>

Return a reciprocal estimate value for the input operand .


<s>
void
AMDGPUCallLowering
::
splitToValueTypes
(
MachineIRBuilder
&
B
,
const
ArgInfo
&
OrigArg
,
SmallVectorImpl
<
ArgInfo
>
&
SplitArgs
,
const
DataLayout
&
DL
,
CallingConv
::
ID
CallConv
,
bool
IsOutgoing
,
SplitArgTy
PerformArgSplit
)
const
{
const
SITargetLowering
&
TLI
=
*
getTLI
<
SITargetLowering
>
(
)
;
LLVMContext
&
Ctx
=
OrigArg
.
Ty
->
getContext
(
)
;
if
(
OrigArg
.
Ty
->
isVoidTy
(
)
)
return
;
SmallVector
<
EVT
,
4
>
SplitVTs
;
ComputeValueVTs
(
TLI
,
DL
,
OrigArg
.
Ty
,
SplitVTs
)
;
assert
(
OrigArg
.
Regs
.
size
(
)
==
SplitVTs
.
size
(
)
)
;
int
SplitIdx
=
0
;
for
(
EVT
VT
:
SplitVTs
)
{
Register
Reg
=
OrigArg
.
Regs
[
SplitIdx
]
;
Type
*
Ty
=
VT
.
getTypeForEVT
(
Ctx
)
;
LLT
LLTy
=
getLLTForType
(
*
Ty
,
DL
)
;
if
(
IsOutgoing
&&
VT
.
isScalarInteger
(
)
)
{
unsigned
ExtendOp
=
TargetOpcode
::
G_ANYEXT
;
if
(
OrigArg
.
Flags
[
0
]
.
isSExt
(
)
)
{
assert
(
OrigArg
.
Regs
.
size
(
)
==
1
&&
"expect only simple return values"
)
;
ExtendOp
=
TargetOpcode
::
G_SEXT
;
}
else
if
(
OrigArg
.
Flags
[
0
]
.
isZExt
(
)
)
{
assert
(
OrigArg
.
Regs
.
size
(
)
==
1
&&
"expect only simple return values"
)
;
ExtendOp
=
TargetOpcode
::
G_ZEXT
;
}
EVT
ExtVT
=
TLI
.
getTypeForExtReturn
(
Ctx
,
VT
,
extOpcodeToISDExtOpcode
(
ExtendOp
)
)
;
if
(
ExtVT
.
getSizeInBits
(
)
!=
VT
.
getSizeInBits
(
)
)
{
VT
=
ExtVT
;
Ty
=
ExtVT
.
getTypeForEVT
(
Ctx
)
;
LLTy
=
getLLTForType
(
*
Ty
,
DL
)
;
Reg
=
B
.
buildInstr
(
ExtendOp
,
{
LLTy
}
,
{
Reg
}
)
.
getReg
(
0
)
;
}
}
unsigned
NumParts
=
TLI
.
getNumRegistersForCallingConv
(
Ctx
,
CallConv
,
VT
)
;
MVT
RegVT
=
TLI
.
getRegisterTypeForCallingConv
(
Ctx
,
CallConv
,
VT
)
;
if
(
NumParts
==
1
)
{
SplitArgs
.
emplace_back
(
Reg
,
Ty
,
OrigArg
.
Flags
,
OrigArg
.
IsFixed
)
;
++
SplitIdx
;
continue
;
}
SmallVector
<
Register
,
8
>
SplitRegs
;
Type
*
PartTy
=
EVT
(
RegVT
)
.
getTypeForEVT
(
Ctx
)
;
LLT
PartLLT
=
getLLTForType
(
*
PartTy
,
DL
)
;
MachineRegisterInfo
&
MRI
=
*
B
.
getMRI
(
)
;
for
(
unsigned
i
=
0
;
i
<
NumParts
;
++
i
)
{
Register
PartReg
=
MRI
.
createGenericVirtualRegister
(
PartLLT
)
;
SplitRegs
.
push_back
(
PartReg
)
;
SplitArgs
.
emplace_back
(
ArrayRef
<
Register
>
(
PartReg
)
,
PartTy
,
OrigArg
.
Flags
)
;
}
PerformArgSplit
(
SplitRegs
,
Reg
,
LLTy
,
PartLLT
,
SplitIdx
)
;
++
SplitIdx
;
}
}
</s>

Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> static void nvptx_encode_section_info ( tree decl , rtx rtl , int first ) { default_encode_section_info ( decl , rtl , first ) ; if ( first && MEM_P ( rtl ) ) { nvptx_data_area area = DATA_AREA_GENERIC ; if ( TREE_CONSTANT ( decl ) ) area = DATA_AREA_CONST ; else if ( TREE_CODE ( decl ) == VAR_DECL ) area = TREE_READONLY ( decl ) ? DATA_AREA_CONST : DATA_AREA_GLOBAL ; SET_SYMBOL_DATA_AREA ( XEXP ( rtl , 0 ) , area ) ; } } </s>

Encode the PTX data area that DECL ( which might not actually be a _DECL ) should reside in .


<s> static const char * ia64_mangle_type ( const_tree type ) { type = TYPE_MAIN_VARIANT ( type ) ; if ( TREE_CODE ( type ) != VOID_TYPE && TREE_CODE ( type ) != BOOLEAN_TYPE && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE ) return NULL ; if ( type == float128_type_node || type == float64x_type_node ) return NULL ; if ( ! TARGET_HPUX && TYPE_MODE ( type ) == TFmode ) return "g" ; if ( TYPE_MODE ( type ) == XFmode ) return TARGET_HPUX ? "u9__float80" : "e" ; if ( TYPE_MODE ( type ) == RFmode ) return "u7__fpreg" ; return NULL ; } </s>

Return the mangling of TYPE if it is an extended fundamental type .


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool IsLittle ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , ARMProcClass ( None ) , stackAlignment ( 4 ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TargetABI ( ARM_ABI_UNKNOWN ) , DL ( computeDataLayout ( initializeSubtargetDependencies ( CPU , FS ) ) ) , TSInfo ( DL ) , InstrInfo ( isThumb1Only ( ) ? ( ARMBaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( ARMBaseInstrInfo * ) new ARMInstrInfo ( * this ) : ( ARMBaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM ) , FrameLowering ( ! isThumb1Only ( ) ? new ARMFrameLowering ( * this ) : ( ARMFrameLowering * ) new Thumb1FrameLowering ( * this ) ) { } </s>

This constructor initializes the data members to match that of the specified triple .

ARM ARM ARM ARM ARM ARM 4 ARM ARM ARM ARM ARM ARM ARM


<s> bool X86InstrInfo :: hasLiveCondCodeDef ( MachineInstr & MI ) const { for ( unsigned i = 0 , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == X86 :: EFLAGS && ! MO . isDead ( ) ) { return true ; } } return false ; } </s>

True if MI has a condition code def , e.g .


<s> void ix86_emit_i387_log1p ( rtx op0 , rtx op1 ) { rtx_code_label * label1 = gen_label_rtx ( ) ; rtx_code_label * label2 = gen_label_rtx ( ) ; rtx tmp = gen_reg_rtx ( XFmode ) ; rtx tmp2 = gen_reg_rtx ( XFmode ) ; rtx test ; emit_insn ( gen_absxf2 ( tmp , op1 ) ) ; test = gen_rtx_GE ( VOIDmode , tmp , const_double_from_real_value ( REAL_VALUE_ATOF ( "0.29289321881345247561810596348408353" , XFmode ) , XFmode ) ) ; emit_jump_insn ( gen_cbranchxf4 ( test , XEXP ( test , 0 ) , XEXP ( test , 1 ) , label1 ) ) ; emit_move_insn ( tmp2 , standard_80387_constant_rtx ( 4 ) ) ; emit_insn ( gen_fyl2xp1xf3_i387 ( op0 , op1 , tmp2 ) ) ; emit_jump ( label2 ) ; emit_label ( label1 ) ; emit_move_insn ( tmp , CONST1_RTX ( XFmode ) ) ; emit_insn ( gen_addxf3 ( tmp , op1 , tmp ) ) ; emit_move_insn ( tmp2 , standard_80387_constant_rtx ( 4 ) ) ; emit_insn ( gen_fyl2xxf3_i387 ( op0 , tmp , tmp2 ) ) ; emit_label ( label2 ) ; } </s>

Output code to perform a log1p XFmode calculation .


Internal function to either define or undef the appropriate system macros .


<s> bool nds32_ls_333_p ( rtx rt , rtx ra , rtx imm , machine_mode mode ) { if ( REGNO_REG_CLASS ( REGNO ( rt ) ) == LOW_REGS && REGNO_REG_CLASS ( REGNO ( ra ) ) == LOW_REGS ) { if ( GET_MODE_SIZE ( mode ) == 4 ) return satisfies_constraint_Iu05 ( imm ) ; if ( GET_MODE_SIZE ( mode ) == 2 ) return satisfies_constraint_Iu04 ( imm ) ; if ( GET_MODE_SIZE ( mode ) == 1 ) return satisfies_constraint_Iu03 ( imm ) ; } return false ; } </s>

Function to test 333-form for load/store instructions . This is auxiliary extern function for auxiliary macro in nds32.h . Because it is a little complicated , we use function instead of macro .


<s>
static
void
mips_print_int_branch_condition
(
FILE
*
file
,
enum
rtx_code
code
,
int
letter
)
{
switch
(
code
)
{
case
EQ
:
case
NE
:
case
GT
:
case
GE
:
case
LT
:
case
LE
:
case
GTU
:
case
GEU
:
case
LTU
:
case
LEU
:
fputs
(
GET_RTX_NAME
(
code
)
,
file
)
;
break
;
default
:
output_operand_lossage
(
"'%%%c' is not a valid operand prefix"
,
letter
)
;
break
;
}
}
</s>

PRINT_OPERAND prefix LETTER refers to the integer branch instruction associated with condition CODE . Print the condition part of the opcode to FILE .

mips
"'%%%c' is not a valid operand prefix"


<s> bool LEGTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; if ( ! CCInfo . CheckReturn ( Outs , RetCC_LEG ) ) { return false ; } if ( CCInfo . getNextStackOffset ( ) != 0 && isVarArg ) { return false ; } return true ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> unsigned PPCInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == PPC :: INLINEASM ) { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } else if ( Opcode == TargetOpcode :: STACKMAP ) { StackMapOpers Opers ( & MI ) ; return Opers . getNumPatchBytes ( ) ; } else if ( Opcode == TargetOpcode :: PATCHPOINT ) { PatchPointOpers Opers ( & MI ) ; return Opers . getNumPatchBytes ( ) ; } else { return get ( Opcode ) . getSize ( ) ; } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> static int const_vector_immediate_p ( rtx x ) { int i ; gcc_assert ( GET_CODE ( x ) == CONST_VECTOR ) ; for ( i = 0 ; i < GET_MODE_NUNITS ( GET_MODE ( x ) ) ; i ++ ) if ( GET_CODE ( CONST_VECTOR_ELT ( x , i ) ) != CONST_INT && GET_CODE ( CONST_VECTOR_ELT ( x , i ) ) != CONST_DOUBLE ) return 0 ; return 1 ; } </s>

Return TRUE when X , a CONST_VECTOR , only contains CONST_INTs or CONST_DOUBLEs .


<s> const char * SystemZTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { OPCODE ( RET_FLAG ) ; OPCODE ( CALL ) ; OPCODE ( SIBCALL ) ; OPCODE ( PCREL_WRAPPER ) ; OPCODE ( PCREL_OFFSET ) ; OPCODE ( ICMP ) ; OPCODE ( FCMP ) ; OPCODE ( TM ) ; OPCODE ( BR_CCMASK ) ; OPCODE ( SELECT_CCMASK ) ; OPCODE ( ADJDYNALLOC ) ; OPCODE ( EXTRACT_ACCESS ) ; OPCODE ( UMUL_LOHI64 ) ; OPCODE ( SDIVREM64 ) ; OPCODE ( UDIVREM32 ) ; OPCODE ( UDIVREM64 ) ; OPCODE ( MVC ) ; OPCODE ( MVC_LOOP ) ; OPCODE ( NC ) ; OPCODE ( NC_LOOP ) ; OPCODE ( OC ) ; OPCODE ( OC_LOOP ) ; OPCODE ( XC ) ; OPCODE ( XC_LOOP ) ; OPCODE ( CLC ) ; OPCODE ( CLC_LOOP ) ; OPCODE ( STRCMP ) ; OPCODE ( STPCPY ) ; OPCODE ( SEARCH_STRING ) ; OPCODE ( IPM ) ; OPCODE ( ATOMIC_SWAPW ) ; OPCODE ( ATOMIC_LOADW_ADD ) ; OPCODE ( ATOMIC_LOADW_SUB ) ; OPCODE ( ATOMIC_LOADW_AND ) ; OPCODE ( ATOMIC_LOADW_OR ) ; OPCODE ( ATOMIC_LOADW_XOR ) ; OPCODE ( ATOMIC_LOADW_NAND ) ; OPCODE ( ATOMIC_LOADW_MIN ) ; OPCODE ( ATOMIC_LOADW_MAX ) ; OPCODE ( ATOMIC_LOADW_UMIN ) ; OPCODE ( ATOMIC_LOADW_UMAX ) ; OPCODE ( ATOMIC_CMP_SWAPW ) ; OPCODE ( PREFETCH ) ; } return NULL ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static void nvptx_wpropagate ( bool pre_p , basic_block block , rtx_insn * insn ) { wcast_data_t data ; data . base = gen_reg_rtx ( Pmode ) ; data . offset = 0 ; data . ptr = NULL_RTX ; nvptx_propagate ( block , insn , pre_p ? PM_read : PM_write , wprop_gen , & data ) ; if ( data . offset ) { rtx init = gen_rtx_SET ( data . base , worker_bcast_sym ) ; emit_insn_after ( init , insn ) ; if ( worker_bcast_size < data . offset ) worker_bcast_size = data . offset ; } } </s>

Spill or fill live state that is live at start of BLOCK . PRE_P indicates if this is just before partitioned mode ( do spill ) , or just after it starts ( do fill ) . Sequence is inserted just after INSN . IS_CALL and return as for nvptx_propagate .


"getRegForInlineAsmConstraint Unhandled data type"

Given a physical register constraint ( e.g .


<s> static void vr4130_align_insns ( void ) { struct mips_sim state ; rtx_insn * insn , * subinsn , * last , * last2 , * next ; bool aligned_p ; dfa_start ( ) ; last = 0 ; last2 = 0 ; aligned_p = true ; mips_sim_init ( & state , alloca ( state_size ( ) ) ) ; for ( insn = get_insns ( ) ; insn != 0 ; insn = next ) { unsigned int length ; next = NEXT_INSN ( insn ) ; vr4130_avoid_branch_rt_conflict ( insn ) ; length = get_attr_length ( insn ) ; if ( length > 0 && USEFUL_INSN_P ( insn ) ) FOR_EACH_SUBINSN ( subinsn , insn ) { mips_sim_wait_insn ( & state , subinsn ) ; if ( state . insns_left != state . issue_rate && ! CALL_P ( subinsn ) ) { if ( subinsn == SEQ_BEGIN ( insn ) && aligned_p ) { gcc_assert ( last2 ) ; emit_insn_after ( gen_nop ( ) , last2 ) ; aligned_p = false ; } else if ( subinsn != SEQ_BEGIN ( insn ) && ! aligned_p ) { gcc_assert ( last ) ; emit_insn_after ( gen_nop ( ) , last ) ; aligned_p = true ; } } mips_sim_issue_insn ( & state , subinsn ) ; } mips_sim_finish_insn ( & state , insn ) ; length = get_attr_length ( insn ) ; if ( length > 0 ) { if ( NONJUMP_INSN_P ( SEQ_BEGIN ( insn ) ) && ( recog_memoized ( insn ) < 0 || length >= 8 ) ) { next = emit_insn_after ( gen_align ( GEN_INT ( 3 ) ) , insn ) ; next = NEXT_INSN ( next ) ; mips_sim_next_cycle ( & state ) ; aligned_p = true ; } else if ( length & 4 ) aligned_p = ! aligned_p ; last2 = last ; last = insn ; } if ( LABEL_P ( insn ) && label_to_alignment ( insn ) >= 3 ) aligned_p = true ; } dfa_finish ( ) ; } </s>

Implement -mvr4130-align . Go through each basic block and simulate the processor pipeline . If we find that a pair of instructions could execute in parallel , and the first of those instruction is not 8-byte aligned , insert a nop to make it aligned .


<s>
bool
ARMAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
;
bool
PendConditionalInstruction
=
false
;
SmallVector
<
NearMissInfo
,
4
>
NearMisses
;
MatchResult
=
MatchInstruction
(
Operands
,
Inst
,
NearMisses
,
MatchingInlineAsm
,
PendConditionalInstruction
,
Out
)
;
switch
(
MatchResult
)
{
case
Match_Success
:
LLVM_DEBUG
(
dbgs
(
)
<<
"Parsed as: "
;
Inst
.
dump_pretty
(
dbgs
(
)
,
MII
.
getName
(
Inst
.
getOpcode
(
)
)
)
;
dbgs
(
)
<<
"\n"
)
;
if
(
validateInstruction
(
Inst
,
Operands
)
)
{
forwardITPosition
(
)
;
forwardVPTPosition
(
)
;
return
true
;
}
{
bool
wasInITBlock
=
inITBlock
(
)
;
while
(
processInstruction
(
Inst
,
Operands
,
Out
)
)
LLVM_DEBUG
(
dbgs
(
)
<<
"Changed to: "
;
Inst
.
dump_pretty
(
dbgs
(
)
,
MII
.
getName
(
Inst
.
getOpcode
(
)
)
)
;
dbgs
(
)
<<
"\n"
)
;
if
(
wasInITBlock
&&
hasV8Ops
(
)
&&
isThumb
(
)
&&
!
isV8EligibleForIT
(
&
Inst
)
)
{
Warning
(
IDLoc
,
"deprecated instruction in IT block"
)
;
}
}
forwardITPosition
(
)
;
forwardVPTPosition
(
)
;
if
(
Inst
.
getOpcode
(
)
==
ARM
::
ITasm
)
return
false
;
Inst
.
setLoc
(
IDLoc
)
;
if
(
PendConditionalInstruction
)
{
PendingConditionalInsts
.
push_back
(
Inst
)
;
if
(
isITBlockFull
(
)
||
isITBlockTerminator
(
Inst
)
)
flushPendingInstructions
(
Out
)
;
}
else
{
Out
.
emitInstruction
(
Inst
,
getSTI
(
)
)
;
}
return
false
;
case
Match_NearMisses
:
ReportNearMisses
(
NearMisses
,
IDLoc
,
Operands
)
;
return
true
;
case
Match_MnemonicFail
:
{
FeatureBitset
FBS
=
ComputeAvailableFeatures
(
getSTI
(
)
.
getFeatureBits
(
)
)
;
std
::
string
Suggestion
=
ARMMnemonicSpellCheck
(
(
(
ARMOperand
&
)
*
Operands
[
0
]
)
.
getToken
(
)
,
FBS
)
;
return
Error
(
IDLoc
,
"invalid instruction"
+
Suggestion
,
(
(
ARMOperand
&
)
*
Operands
[
0
]
)
.
getLocRange
(
)
)
;
}
}
llvm_unreachable
(
"Implement any new match types added!"
)
;
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .

ARM
ARM
4
"Parsed as: "
"\n"
"Changed to: "
"\n"
"deprecated instruction in IT block"
ARM::ITasm
ARM
ARM
0
"invalid instruction"
ARM
0
"Implement any new match types added!"


<s> bool bx_p ( rtx op , bool strict ) { if ( GET_CODE ( op ) != MEM ) return false ; return inside_bx_p ( XEXP ( op , 0 ) , strict ) ; } </s>


<s>
MCSymbol
*
DCPU16MCInstLower
::
GetBlockAddressSymbol
(
const
MachineOperand
&
MO
)
const
{
switch
(
MO
.
getTargetFlags
(
)
)
{
default
:
llvm_unreachable
(
"Unknown target flag on GV operand"
)
;
case
0
:
break
;
}
return
Printer
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
;
}
</s>

Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block .


<s> int frv_class_max_nregs ( enum reg_class rclass , machine_mode mode ) { if ( rclass == ACCG_REGS ) return GET_MODE_SIZE ( mode ) ; else return ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } </s>

A C expression for the maximum number of consecutive registers of class RCLASS needed to hold a value of mode MODE . This is closely related to the macro ` HARD_REGNO_NREGS ' . In fact , the value of the macro ` CLASS_MAX_NREGS ( RCLASS , MODE ) ' should be the maximum value of ` HARD_REGNO_NREGS ( REGNO , MODE ) ' for all REGNO values in the class RCLASS . This macro helps control the handling of multiple-word values in the reload pass . This declaration is required .


"multiversioning needs %<ifunc%> which is not supported "

Make a dispatcher declaration for the multi-versioned function DECL . Calls to DECL function will be replaced with calls to the dispatcher by the front-end . Returns the decl of the dispatcher function .


<s> static void rs6000_set_up_by_prologue ( struct hard_reg_set_container * set ) { if ( ! TARGET_SINGLE_PIC_BASE && TARGET_TOC && TARGET_MINIMAL_TOC && ! constant_pool_empty_p ( ) ) add_to_hard_reg_set ( & set -> set , Pmode , RS6000_PIC_OFFSET_TABLE_REGNUM ) ; if ( cfun -> machine -> split_stack_argp_used ) add_to_hard_reg_set ( & set -> set , Pmode , 12 ) ; } </s>

Add r30 to hard reg set if the prologue sets it up and it is not pic_offset_table_rtx .


<s> TargetLowering :: AtomicExpansionKind AArch64TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { if ( Subtarget -> hasLSE ( ) || Subtarget -> outlineAtomics ( ) ) return AtomicExpansionKind :: None ; if ( getTargetMachine ( ) . getOptLevel ( ) == CodeGenOpt :: None ) return AtomicExpansionKind :: None ; unsigned Size = AI -> getCompareOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size > 64 ) return AtomicExpansionKind :: None ; return AtomicExpansionKind :: LLSC ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> rtx alpha_tablejump_best_label ( rtx insn ) { rtx jump_table = alpha_tablejump_addr_vec ( insn ) ; rtx best_label = NULL_RTX ; if ( jump_table ) { int n_labels = XVECLEN ( jump_table , 1 ) ; int best_count = - 1 ; int i , j ; for ( i = 0 ; i < n_labels ; i ++ ) { int count = 1 ; for ( j = i + 1 ; j < n_labels ; j ++ ) if ( XEXP ( XVECEXP ( jump_table , 1 , i ) , 0 ) == XEXP ( XVECEXP ( jump_table , 1 , j ) , 0 ) ) count ++ ; if ( count > best_count ) best_count = count , best_label = XVECEXP ( jump_table , 1 , i ) ; } } return best_label ? best_label : const0_rtx ; } </s>

Return the label of the predicted edge , or CONST0_RTX if we do n't know .


"internal error: instruction without _e64 suffix "


<s> static unsigned size ( const GraphType & G ) { return G . Blocks . size ( ) ; } </s>

The number of name/type pairs is returned .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"SI Type Rewriter"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool has ( unsigned R ) const { if ( ! Register :: isVirtualRegister ( R ) ) return true ; MapType :: const_iterator F = Map . find ( R ) ; return F != Map . end ( ) ; } </s>

Tests whether a library function is available .


<s> unsigned AMDGPUTargetLowering :: computeNumSignBitsForTargetInstr ( GISelKnownBits & Analysis , Register R , const APInt & DemandedElts , const MachineRegisterInfo & MRI , unsigned Depth ) const { const MachineInstr * MI = MRI . getVRegDef ( R ) ; if ( ! MI ) return 1 ; switch ( MI -> getOpcode ( ) ) { case AMDGPU :: G_AMDGPU_BUFFER_LOAD_SBYTE : return 25 ; case AMDGPU :: G_AMDGPU_BUFFER_LOAD_SSHORT : return 17 ; case AMDGPU :: G_AMDGPU_BUFFER_LOAD_UBYTE : return 24 ; case AMDGPU :: G_AMDGPU_BUFFER_LOAD_USHORT : return 16 ; default : return 1 ; } } </s>

This method can be implemented by targets that want to expose additional information about sign bits to GlobalISel combiners .


<s> bool lm32_move_ok ( machine_mode mode , rtx operands [ 2 ] ) { if ( memory_operand ( operands [ 0 ] , mode ) ) return register_or_zero_operand ( operands [ 1 ] , mode ) ; return true ; } </s>


<s> unsigned getBitMask ( unsigned Shift , unsigned Width ) { return ( ( 1 << Width ) - 1 ) << Shift ; } </s>

Return a bitmask with ones set for all of the bits that can be set by an unsigned version of this type .


<s> void avr_register_target_pragmas ( void ) { int i ; gcc_assert ( ADDR_SPACE_GENERIC == ADDR_SPACE_RAM ) ; for ( i = 0 ; i < ADDR_SPACE_COUNT ; i ++ ) { gcc_assert ( i == avr_addrspace [ i ] . id ) ; if ( ! ADDR_SPACE_GENERIC_P ( i ) ) c_register_addr_space ( avr_addrspace [ i ] . name , avr_addrspace [ i ] . id ) ; } targetm . resolve_overloaded_builtin = avr_resolve_overloaded_builtin ; } </s>


"PPC hazards don't support scoreboard lookahead"

getHazardType - Return the hazard type of emitting this node .


<s> static int ix86_issue_rate ( void ) { switch ( ix86_tune ) { case PROCESSOR_PENTIUM : case PROCESSOR_LAKEMONT : case PROCESSOR_BONNELL : case PROCESSOR_SILVERMONT : case PROCESSOR_KNL : case PROCESSOR_INTEL : case PROCESSOR_K6 : case PROCESSOR_BTVER2 : case PROCESSOR_PENTIUM4 : case PROCESSOR_NOCONA : return 2 ; case PROCESSOR_PENTIUMPRO : case PROCESSOR_ATHLON : case PROCESSOR_K8 : case PROCESSOR_AMDFAM10 : case PROCESSOR_GENERIC : case PROCESSOR_BTVER1 : return 3 ; case PROCESSOR_BDVER1 : case PROCESSOR_BDVER2 : case PROCESSOR_BDVER3 : case PROCESSOR_BDVER4 : case PROCESSOR_ZNVER1 : case PROCESSOR_CORE2 : case PROCESSOR_NEHALEM : case PROCESSOR_SANDYBRIDGE : case PROCESSOR_HASWELL : return 4 ; default : return 1 ; } } </s>

Return the maximum number of instructions a cpu can issue .


<s> DecodeStatus SparcDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & VStream , raw_ostream & CStream ) const { uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Bytes , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTableSparc32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s> virtual void EmitInstruction ( const MCInst & Inst ) { const MCInstrDesc & MID = MII . get ( Inst . getOpcode ( ) ) ; count ++ ; size += MID . getSize ( ) ; call |= MID . isCall ( ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> int registers_ok_for_ldd_peep ( rtx reg1 , rtx reg2 ) { if ( GET_CODE ( reg1 ) != REG || GET_CODE ( reg2 ) != REG ) return 0 ; if ( REGNO ( reg1 ) % 2 != 0 ) return 0 ; if ( TARGET_V9 && REGNO ( reg1 ) < 32 ) return 0 ; return ( REGNO ( reg1 ) == REGNO ( reg2 ) - 1 ) ; } </s>

Return 1 if REGNO ( reg1 ) is even and REGNO ( reg1 ) == REGNO ( reg2 ) - 1 . This makes them candidates for using ldd and std insns . Note reg1 and reg2 * must * be hard registers .


<s> bool ARMTargetLowering :: SimplifyDemandedBitsForTargetNode ( SDValue Op , const APInt & OriginalDemandedBits , const APInt & OriginalDemandedElts , KnownBits & Known , TargetLoweringOpt & TLO , unsigned Depth ) const { unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { case ARMISD :: ASRL : case ARMISD :: LSRL : { if ( Op . getResNo ( ) == 0 && ! Op -> hasAnyUseOfValue ( 1 ) && isa < ConstantSDNode > ( Op -> getOperand ( 2 ) ) ) { unsigned ShAmt = Op -> getConstantOperandVal ( 2 ) ; if ( ShAmt < 32 && OriginalDemandedBits . isSubsetOf ( APInt :: getAllOnesValue ( 32 ) << ( 32 - ShAmt ) ) ) return TLO . CombineTo ( Op , TLO . DAG . getNode ( ISD :: SHL , SDLoc ( Op ) , MVT :: i32 , Op . getOperand ( 1 ) , TLO . DAG . getConstant ( 32 - ShAmt , SDLoc ( Op ) , MVT :: i32 ) ) ) ; } break ; } } return TargetLowering :: SimplifyDemandedBitsForTargetNode ( Op , OriginalDemandedBits , OriginalDemandedElts , Known , TLO , Depth ) ; } </s>

Attempt to simplify any target nodes based on the demanded bits/elts , returning true on success .


<s> const TargetRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> StackOffset RISCVFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const auto * RVFI = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; const auto & CSI = getNonLibcallCSI ( MFI . getCalleeSavedInfo ( ) ) ; int MinCSFI = 0 ; int MaxCSFI = - 1 ; int Offset = MFI . getObjectOffset ( FI ) - getOffsetOfLocalArea ( ) + MFI . getOffsetAdjustment ( ) ; uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( CSI . size ( ) ) { MinCSFI = CSI [ 0 ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - 1 ] . getFrameIdx ( ) ; } if ( FI >= MinCSFI && FI <= MaxCSFI ) { FrameReg = RISCV :: X2 ; if ( FirstSPAdjustAmount ) Offset += FirstSPAdjustAmount ; else Offset += MFI . getStackSize ( ) ; } else if ( RI -> needsStackRealignment ( MF ) && ! MFI . isFixedObjectIndex ( FI ) ) { if ( hasBP ( MF ) ) FrameReg = RISCVABI :: getBPReg ( ) ; else FrameReg = RISCV :: X2 ; Offset += MFI . getStackSize ( ) ; if ( FI < 0 ) Offset += RVFI -> getLibCallStackSize ( ) ; } else { FrameReg = RI -> getFrameRegister ( MF ) ; if ( hasFP ( MF ) ) { Offset += RVFI -> getVarArgsSaveSize ( ) ; if ( FI >= 0 ) Offset -= RVFI -> getLibCallStackSize ( ) ; } else { Offset += MFI . getStackSize ( ) ; if ( FI < 0 ) Offset += RVFI -> getLibCallStackSize ( ) ; } } return StackOffset :: getFixed ( Offset ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s>
char
*
aarch64_output_sve_addvl_addpl
(
rtx
dest
,
rtx
base
,
rtx
offset
)
{
static
char
buffer
[
sizeof
(
"addpl\t%x0, %x1, #-"
)
+
3
*
sizeof
(
int
)
]
;
poly_int64
offset_value
=
rtx_to_poly_int64
(
offset
)
;
gcc_assert
(
aarch64_sve_addvl_addpl_immediate_p
(
offset_value
)
)
;
if
(
rtx_equal_p
(
dest
,
base
)
&&
GP_REGNUM_P
(
REGNO
(
dest
)
)
)
{
if
(
aarch64_sve_cnt_immediate_p
(
offset_value
)
)
return
aarch64_output_sve_cnt_immediate
(
"inc"
,
"%x0"
,
offset_value
.
coeffs
[
1
]
,
0
)
;
if
(
aarch64_sve_cnt_immediate_p
(
offset_value
)
)
return
aarch64_output_sve_cnt_immediate
(
"dec"
,
"%x0"
,
offset_value
.
coeffs
[
1
]
,
0
)
;
}
int
factor
=
offset_value
.
coeffs
[
1
]
;
if
(
(
factor
&
15
)
==
0
)
snprintf
(
buffer
,
sizeof
(
buffer
)
,
"addvl\t%%x0, %%x1, #%d"
,
factor
/
16
)
;
else
snprintf
(
buffer
,
sizeof
(
buffer
)
,
"addpl\t%%x0, %%x1, #%d"
,
factor
/
2
)
;
return
buffer
;
}
</s>

Return the asm string for adding ADDVL or ADDPL immediate X to operand 1 and storing the result in operand 0 .


<s> MachineBasicBlock :: iterator XCoreInstrInfo :: loadImmediate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned Reg , uint64_t Value ) const { DebugLoc dl ; if ( MI != MBB . end ( ) ) dl = MI -> getDebugLoc ( ) ; if ( isMask_32 ( Value ) ) { int N = Log2_32 ( Value ) + 1 ; return BuildMI ( MBB , MI , dl , get ( XCore :: MKMSK_rus ) , Reg ) . addImm ( N ) ; } if ( isImmU16 ( Value ) ) { int Opcode = isImmU6 ( Value ) ? XCore :: LDC_ru6 : XCore :: LDC_lru6 ; return BuildMI ( MBB , MI , dl , get ( Opcode ) , Reg ) . addImm ( Value ) ; } MachineConstantPool * ConstantPool = MBB . getParent ( ) -> getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Value ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; return BuildMI ( MBB , MI , dl , get ( XCore :: LDWCP_lru6 ) , Reg ) . addConstantPoolIndex ( Idx ) ; } </s>

Emit a series of instructions to load an immediate .


<s> bool ARMTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { if ( ! Subtarget -> hasVFP3 ( ) ) return false ; if ( VT == MVT :: f32 ) return ARM :: getVFPf32Imm ( Imm ) != - 1 ; if ( VT == MVT :: f64 ) return ARM :: getVFPf64Imm ( Imm ) != - 1 ; return false ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s>
static
void
ia64_globalize_decl_name
(
FILE
*
stream
,
tree
decl
)
{
const
char
*
name
=
XSTR
(
XEXP
(
DECL_RTL
(
decl
)
,
0
)
,
0
)
;
tree
version_attr
=
lookup_attribute
(
"version_id"
,
DECL_ATTRIBUTES
(
decl
)
)
;
if
(
version_attr
)
{
tree
v
=
TREE_VALUE
(
TREE_VALUE
(
version_attr
)
)
;
const
char
*
p
=
TREE_STRING_POINTER
(
v
)
;
fprintf
(
stream
,
"\t.alias %s#, \"%s{%s}\"\n"
,
name
,
name
,
p
)
;
}
targetm
.
asm_out
.
globalize_label
(
stream
,
name
)
;
if
(
TREE_CODE
(
decl
)
==
FUNCTION_DECL
)
ASM_OUTPUT_TYPE_DIRECTIVE
(
stream
,
name
,
"function"
)
;
}
</s>


<s>
void
MipsAsmPrinter
::
emitDebugValue
(
const
MCExpr
*
Value
,
unsigned
Size
)
const
{
if
(
auto
*
MipsExpr
=
dyn_cast
<
MipsMCExpr
>
(
Value
)
)
{
if
(
MipsExpr
&&
MipsExpr
->
getKind
(
)
==
MipsMCExpr
::
MEK_DTPREL
)
{
switch
(
Size
)
{
case
4
:
OutStreamer
->
emitDTPRel32Value
(
MipsExpr
->
getSubExpr
(
)
)
;
break
;
case
8
:
OutStreamer
->
emitDTPRel64Value
(
MipsExpr
->
getSubExpr
(
)
)
;
break
;
default
:
llvm_unreachable
(
"Unexpected size of expression value."
)
;
}
return
;
}
}
AsmPrinter
::
emitDebugValue
(
Value
,
Size
)
;
}
</s>

Emit the directive and value for debug thread local expression .

Mips
Mips
Mips
Mips
Mips
Mips
Mips
4
Mips
8
Mips
"Unexpected size of expression value."


<s> unsigned getReturnOpcode ( ) const { if ( isThumb ( ) ) return ARM :: tBX_RET ; if ( hasV4TOps ( ) ) return ARM :: BX_RET ; return ARM :: MOVPCLR ; } </s>

Returns the correct return opcode for the current feature set .


<s> void WDC65816TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { return LowerOperationWrapper ( N , Results , DAG ) ; } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s>
const
char
*
CSKYTargetLowering
::
getTargetNodeName
(
unsigned
Opcode
)
const
{
switch
(
Opcode
)
{
default
:
llvm_unreachable
(
"unknown CSKYISD node"
)
;
case
CSKYISD
::
NIE
:
return
"CSKYISD::NIE"
;
case
CSKYISD
::
NIR
:
return
"CSKYISD::NIR"
;
case
CSKYISD
::
RET
:
return
"CSKYISD::RET"
;
case
CSKYISD
::
CALL
:
return
"CSKYISD::CALL"
;
case
CSKYISD
::
CALLReg
:
return
"CSKYISD::CALLReg"
;
case
CSKYISD
::
TAIL
:
return
"CSKYISD::TAIL"
;
case
CSKYISD
::
TAILReg
:
return
"CSKYISD::TAILReg"
;
case
CSKYISD
::
LOAD_ADDR
:
return
"CSKYISD::LOAD_ADDR"
;
case
CSKYISD
::
BITCAST_TO_LOHI
:
return
"CSKYISD::BITCAST_TO_LOHI"
;
case
CSKYISD
::
BITCAST_FROM_LOHI
:
return
"CSKYISD::BITCAST_FROM_LOHI"
;
}
}
</s>

getTargetNodeName - This method returns the name of a target specific

CSKY
CSKY
"unknown CSKYISD node"
CSKYISD::NIE
"CSKYISD::NIE"
CSKYISD::NIR
"CSKYISD::NIR"
CSKYISD::RET
"CSKYISD::RET"
CSKYISD::CALL
"CSKYISD::CALL"
CSKYISD::CALLReg
"CSKYISD::CALLReg"
CSKYISD::TAIL
"CSKYISD::TAIL"
CSKYISD::TAILReg
"CSKYISD::TAILReg"
CSKYISD::LOAD_ADDR
"CSKYISD::LOAD_ADDR"
CSKYISD::BITCAST_TO_LOHI
"CSKYISD::BITCAST_TO_LOHI"
CSKYISD::BITCAST_FROM_LOHI
"CSKYISD::BITCAST_FROM_LOHI"


<s>
void
WebAssemblyAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"EmitInstruction: "
<<
*
MI
<<
'\n'
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
WebAssembly
::
ARGUMENT_i32
:
case
WebAssembly
::
ARGUMENT_i32_S
:
case
WebAssembly
::
ARGUMENT_i64
:
case
WebAssembly
::
ARGUMENT_i64_S
:
case
WebAssembly
::
ARGUMENT_f32
:
case
WebAssembly
::
ARGUMENT_f32_S
:
case
WebAssembly
::
ARGUMENT_f64
:
case
WebAssembly
::
ARGUMENT_f64_S
:
case
WebAssembly
::
ARGUMENT_v16i8
:
case
WebAssembly
::
ARGUMENT_v16i8_S
:
case
WebAssembly
::
ARGUMENT_v8i16
:
case
WebAssembly
::
ARGUMENT_v8i16_S
:
case
WebAssembly
::
ARGUMENT_v4i32
:
case
WebAssembly
::
ARGUMENT_v4i32_S
:
case
WebAssembly
::
ARGUMENT_v2i64
:
case
WebAssembly
::
ARGUMENT_v2i64_S
:
case
WebAssembly
::
ARGUMENT_v4f32
:
case
WebAssembly
::
ARGUMENT_v4f32_S
:
case
WebAssembly
::
ARGUMENT_v2f64
:
case
WebAssembly
::
ARGUMENT_v2f64_S
:
break
;
case
WebAssembly
::
FALLTHROUGH_RETURN_I32
:
case
WebAssembly
::
FALLTHROUGH_RETURN_I32_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_I64
:
case
WebAssembly
::
FALLTHROUGH_RETURN_I64_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_F32
:
case
WebAssembly
::
FALLTHROUGH_RETURN_F32_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_F64
:
case
WebAssembly
::
FALLTHROUGH_RETURN_F64_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v16i8
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v16i8_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v8i16
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v8i16_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v4i32
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v4i32_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v2i64
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v2i64_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v4f32
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v4f32_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v2f64
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v2f64_S
:
{
if
(
isVerbose
(
)
)
{
OutStreamer
->
AddComment
(
"fallthrough-return-value"
)
;
OutStreamer
->
AddBlankLine
(
)
;
}
break
;
}
case
WebAssembly
::
FALLTHROUGH_RETURN_VOID
:
case
WebAssembly
::
FALLTHROUGH_RETURN_VOID_S
:
if
(
isVerbose
(
)
)
{
OutStreamer
->
AddComment
(
"fallthrough-return-void"
)
;
OutStreamer
->
AddBlankLine
(
)
;
}
break
;
case
WebAssembly
::
EXTRACT_EXCEPTION_I32
:
case
WebAssembly
::
EXTRACT_EXCEPTION_I32_S
:
if
(
!
WasmKeepRegisters
)
break
;
LLVM_FALLTHROUGH
;
default
:
{
WebAssemblyMCInstLower
MCInstLowering
(
OutContext
,
*
this
)
;
MCInst
TmpInst
;
MCInstLowering
.
lower
(
MI
,
TmpInst
)
;
EmitToStreamer
(
*
OutStreamer
,
TmpInst
)
;
break
;
}
}
}
</s>


<s> bool hasFusion ( ) const { return HasFusion ; } </s>

Return true if the CPU supports any kind of instruction fusion .


"MEMOPw offset is not aligned correctly."

"MEMOPh offset is not aligned correctly."

"No offset range is defined for this opcode. "

"Please define it in the above switch statement!"


"Don't know how to lower this operation."

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool PPCLinuxAsmPrinter :: doFinalization ( Module & M ) { const DataLayout & DL = getDataLayout ( ) ; bool isPPC64 = DL . getPointerSizeInBits ( ) == 64 ; PPCTargetStreamer & TS = static_cast < PPCTargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; if ( ! TOC . empty ( ) ) { MCSectionELF * Section ; if ( isPPC64 ) Section = OutStreamer -> getContext ( ) . getELFSection ( ".toc" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; else Section = OutStreamer -> getContext ( ) . getELFSection ( ".got2" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; OutStreamer -> SwitchSection ( Section ) ; for ( const auto & TOCMapPair : TOC ) { const MCSymbol * const TOCEntryTarget = TOCMapPair . first ; MCSymbol * const TOCEntryLabel = TOCMapPair . second ; OutStreamer -> emitLabel ( TOCEntryLabel ) ; if ( isPPC64 ) { TS . emitTCEntry ( * TOCEntryTarget ) ; } else { OutStreamer -> emitValueToAlignment ( 4 ) ; OutStreamer -> emitSymbolValue ( TOCEntryTarget , 4 ) ; } } } return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> static rtx rs6000_darwin64_record_arg ( CUMULATIVE_ARGS * orig_cum , tree type , int named , bool retval ) { rtx rvec [ FIRST_PSEUDO_REGISTER ] ; int k = 1 , kbase = 1 ; HOST_WIDE_INT typesize = int_size_in_bytes ( type ) ; CUMULATIVE_ARGS copy_cum = * orig_cum ; CUMULATIVE_ARGS * cum = & copy_cum ; if ( ! retval && TYPE_ALIGN ( type ) >= 2 * BITS_PER_WORD && ( cum -> words % 2 ) != 0 ) cum -> words ++ ; cum -> intoffset = 0 ; cum -> use_stack = 0 ; cum -> named = named ; rs6000_darwin64_record_arg_recurse ( cum , type , 0 , rvec , & k ) ; rs6000_darwin64_record_arg_flush ( cum , typesize * BITS_PER_UNIT , rvec , & k ) ; if ( cum -> use_stack ) { if ( retval ) return NULL_RTX ; kbase = 0 ; rvec [ 0 ] = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; } if ( k > 1 || cum -> use_stack ) return gen_rtx_PARALLEL ( BLKmode , gen_rtvec_v ( k - kbase , & rvec [ kbase ] ) ) ; else return NULL_RTX ; } </s>

For the darwin64 ABI , we want to construct a PARALLEL consisting of the register ( s ) to be used for each field and subfield of a struct being passed by value , along with the offset of where the register 's value may be found in the block . FP fields go in FP register , vector fields go in vector registers , and everything else goes in int registers , packed as in memory . This code is also used for function return values . RETVAL indicates whether this is the case . Much of this is taken from the SPARC V9 port , which has a similar calling convention .


<s> static inline enum insn_code rs6000_htm_spr_icode ( bool nonvoid ) { if ( nonvoid ) return ( TARGET_POWERPC64 ) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si ; else return ( TARGET_POWERPC64 ) ? CODE_FOR_htm_mtspr_di : CODE_FOR_htm_mtspr_si ; } </s>

Return the correct ICODE value depending on whether we are setting or reading the HTM SPRs .


<s>
static
void
sparc_file_end
(
void
)
{
if
(
got_helper_needed
)
{
const
char
*
name
=
XSTR
(
got_helper_rtx
,
0
)
;
bool
do_cfi
;
if
(
USE_HIDDEN_LINKONCE
)
{
tree
decl
=
build_decl
(
BUILTINS_LOCATION
,
FUNCTION_DECL
,
get_identifier
(
name
)
,
build_function_type_list
(
void_type_node
,
NULL_TREE
)
)
;
DECL_RESULT
(
decl
)
=
build_decl
(
BUILTINS_LOCATION
,
RESULT_DECL
,
NULL_TREE
,
void_type_node
)
;
TREE_PUBLIC
(
decl
)
=
1
;
TREE_STATIC
(
decl
)
=
1
;
make_decl_one_only
(
decl
,
DECL_ASSEMBLER_NAME
(
decl
)
)
;
DECL_VISIBILITY
(
decl
)
=
VISIBILITY_HIDDEN
;
DECL_VISIBILITY_SPECIFIED
(
decl
)
=
1
;
resolve_unique_section
(
decl
,
0
,
flag_function_sections
)
;
allocate_struct_function
(
decl
,
true
)
;
cfun
->
is_thunk
=
1
;
current_function_decl
=
decl
;
init_varasm_status
(
)
;
assemble_start_function
(
decl
,
name
)
;
}
else
{
const
int
align
=
floor_log2
(
FUNCTION_BOUNDARY
/
BITS_PER_UNIT
)
;
switch_to_section
(
text_section
)
;
if
(
align
>
0
)
ASM_OUTPUT_ALIGN
(
asm_out_file
,
align
)
;
ASM_OUTPUT_LABEL
(
asm_out_file
,
name
)
;
}
do_cfi
=
dwarf2out_do_cfi_asm
(
)
;
if
(
do_cfi
)
output_asm_insn
(
".cfi_startproc"
,
)
;
if
(
flag_delayed_branch
)
{
output_asm_insn
(
"jmp\t%%o7+8"
,
)
;
output_asm_insn
(
" add\t%%o7, %0, %0"
,
&
got_register_rtx
)
;
}
else
{
output_asm_insn
(
"add\t%%o7, %0, %0"
,
&
got_register_rtx
)
;
output_asm_insn
(
"jmp\t%%o7+8"
,
)
;
output_asm_insn
(
" nop"
,
)
;
}
if
(
do_cfi
)
output_asm_insn
(
".cfi_endproc"
,
)
;
}
if
(
NEED_INDICATE_EXEC_STACK
)
file_end_indicate_exec_stack
(
)
;
solaris_file_end
(
)
;
}
</s>

Do whatever processing is required at the end of a file .


<s>
bool
HexagonPassConfig
::
addPreSched2
(
)
{
const
HexagonTargetMachine
&
TM
=
getHexagonTargetMachine
(
)
;
addPass
(
createHexagonCopyToCombine
(
)
)
;
if
(
getOptLevel
(
)
!=
CodeGenOpt
::
)
addPass
(
&
IfConverterID
)
;
addPass
(
createHexagonSplitConst32AndConst64
(
TM
)
)
;
printAndVerify
(
"After hexagon split const32/64 pass"
)
;
return
true
;
}
</s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .

Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
"After hexagon split const32/64 pass"


<s> int arm_apply_result_size ( void ) { int size = 16 ; if ( TARGET_ARM ) { if ( TARGET_HARD_FLOAT_ABI ) { if ( TARGET_FPA ) size += 12 ; if ( TARGET_MAVERICK ) size += 8 ; } if ( TARGET_IWMMXT_ABI ) size += 8 ; } return size ; } </s>

Determine the amount of memory needed to store the possible return registers of an untyped call .


<s> void SPIRVMCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { auto Features = computeAvailableFeatures ( STI . getFeatureBits ( ) ) ; verifyInstructionPredicates ( MI , Features ) ; EndianWriter OSE ( OS , support :: little ) ; const uint64_t OpCode = getBinaryCodeForInstr ( MI , Fixups , STI ) ; const uint32_t NumWords = MI . getNumOperands ( ) + 1 ; const uint32_t FirstWord = ( NumWords << 16 ) | OpCode ; OSE . write < uint32_t > ( FirstWord ) ; if ( hasType ( MI , MCII , MRI ) ) emitTypedInstrOperands ( MI , OSE ) ; else emitUntypedInstrOperands ( MI , OSE ) ; } </s>

Encode the given Inst to bytes and append to CB .


<s> TargetTransformInfo SPIRVTargetMachine :: getTargetTransformInfo ( const Function & F ) const { return TargetTransformInfo ( SPIRVTTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> bool ARMLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { MF = & Fn ; STI = & static_cast < const ARMSubtarget & > ( Fn . getSubtarget ( ) ) ; TL = STI -> getTargetLowering ( ) ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; RegClassInfoValid = false ; isThumb2 = AFI -> isThumb2Function ( ) ; isThumb1 = AFI -> isThumbFunction ( ) && ! isThumb2 ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= LoadStoreMultipleOpti ( MBB ) ; if ( STI -> hasV5TOps ( ) ) Modified |= MergeReturnIntoLDM ( MBB ) ; if ( isThumb1 ) Modified |= CombineMovBx ( MBB ) ; } Allocator . DestroyAll ( ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


"argument must be a 16-bit constant immediate"

Function to expand an expression EXP which calls one of the Transactional Memory Extension ( TME ) builtins FCODE with the result going to TARGET .


<s> enum arc_function_type arc_compute_function_type ( struct function * fun ) { tree decl = fun -> decl ; tree a ; enum arc_function_type fn_type = fun -> machine -> fn_type ; if ( fn_type != ARC_FUNCTION_UNKNOWN ) return fn_type ; fn_type = ARC_FUNCTION_NORMAL ; for ( a = DECL_ATTRIBUTES ( decl ) ; a ; a = TREE_CHAIN ( a ) ) { tree name = TREE_PURPOSE ( a ) , args = TREE_VALUE ( a ) ; if ( name == get_identifier ( "interrupt" ) && list_length ( args ) == 1 && TREE_CODE ( TREE_VALUE ( args ) ) == STRING_CST ) { tree value = TREE_VALUE ( args ) ; if ( ! strcmp ( TREE_STRING_POINTER ( value ) , "ilink1" ) || ! strcmp ( TREE_STRING_POINTER ( value ) , "ilink" ) ) fn_type = ARC_FUNCTION_ILINK1 ; else if ( ! strcmp ( TREE_STRING_POINTER ( value ) , "ilink2" ) ) fn_type = ARC_FUNCTION_ILINK2 ; else gcc_unreachable ( ) ; break ; } } return fun -> machine -> fn_type = fn_type ; } </s>

Type of function DECL . The result is cached . To reset the cache at the end of a function , call with DECL = NULL_TREE .


<s> SDValue SITargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( N ) ; EVT VT = N -> getValueType ( 0 ) ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: SELECT_CC : { N -> dump ( ) ; ConstantSDNode * True , * False ; if ( ( True = dyn_cast < ConstantSDNode > ( N -> getOperand ( 2 ) ) ) && ( False = dyn_cast < ConstantSDNode > ( N -> getOperand ( 3 ) ) ) && True -> isAllOnesValue ( ) && False -> isNullValue ( ) && VT == MVT :: i1 ) { return DAG . getNode ( ISD :: SETCC , DL , VT , N -> getOperand ( 0 ) , N -> getOperand ( 1 ) , N -> getOperand ( 4 ) ) ; } break ; } case ISD :: SETCC : { SDValue Arg0 = N -> getOperand ( 0 ) ; SDValue Arg1 = N -> getOperand ( 1 ) ; SDValue CC = N -> getOperand ( 2 ) ; ConstantSDNode * C = NULL ; ISD :: CondCode CCOp = dyn_cast < CondCodeSDNode > ( CC ) -> get ( ) ; if ( VT == MVT :: i1 && Arg0 . getOpcode ( ) == ISD :: SIGN_EXTEND && Arg0 . getOperand ( 0 ) . getValueType ( ) == MVT :: i1 && ( C = dyn_cast < ConstantSDNode > ( Arg1 ) ) && C -> isNullValue ( ) && CCOp == ISD :: SETNE ) { return SimplifySetCC ( VT , Arg0 . getOperand ( 0 ) , DAG . getConstant ( 0 , MVT :: i1 ) , CCOp , true , DCI , DL ) ; } break ; } } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s>
static
const
struct
riscv_cpu_info
*
riscv_parse_cpu
(
const
char
*
cpu_string
)
{
for
(
unsigned
i
=
0
;
i
<
ARRAY_SIZE
(
riscv_cpu_info_table
)
;
i
++
)
if
(
strcmp
(
riscv_cpu_info_table
[
i
]
.
name
,
cpu_string
)
==
0
)
return
riscv_cpu_info_table
+
i
;
error
(
"unknown cpu %qs for -mtune"
,
cpu_string
)
;
return
riscv_cpu_info_table
;
}
</s>

Return the riscv_cpu_info entry for the given name string .


"WebAssembly can only return up to one value"

"WebAssembly doesn't support non-C calling conventions"

"WebAssembly hasn't implemented inalloca results"

"WebAssembly hasn't implemented cons regs results"

"WebAssembly hasn't implemented cons regs last results"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s>
unsigned
ARMCodeEmitter
::
getMachineOpValue
(
const
MachineInstr
&
MI
,
const
MachineOperand
&
MO
)
const
{
if
(
MO
.
isReg
(
)
)
return
getARMRegisterNumbering
(
MO
.
getReg
(
)
)
;
else
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
else
if
(
MO
.
isFPImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getFPImm
(
)
->
getValueAPF
(
)
.
bitcastToAPInt
(
)
.
getHiBits
(
32
)
.
getLimitedValue
(
)
)
;
else
if
(
MO
.
isGlobal
(
)
)
emitGlobalAddress
(
MO
.
getGlobal
(
)
,
ARM
::
reloc_arm_branch
,
true
,
false
)
;
else
if
(
MO
.
isSymbol
(
)
)
emitExternalSymbolAddress
(
MO
.
getSymbolName
(
)
,
ARM
::
reloc_arm_branch
)
;
else
if
(
MO
.
isCPI
(
)
)
{
const
MCInstrDesc
&
MCID
=
MI
.
getDesc
(
)
;
unsigned
Reloc
=
(
(
MCID
.
TSFlags
&
ARMII
::
FormMask
)
==
ARMII
::
VFPLdStFrm
)
ARM
::
reloc_arm_vfp_cp_entry
:
ARM
::
reloc_arm_cp_entry
;
emitConstPoolAddress
(
MO
.
getIndex
(
)
,
Reloc
)
;
}
else
if
(
MO
.
isJTI
(
)
)
emitJumpTableAddress
(
MO
.
getIndex
(
)
,
ARM
::
reloc_arm_relative
)
;
else
if
(
MO
.
isMBB
(
)
)
emitMachineBasicBlock
(
MO
.
getMBB
(
)
,
ARM
::
reloc_arm_branch
)
;
else
llvm_unreachable
(
"Unable to encode MachineOperand!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> bool X86AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNo ) ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , O ) ; case 'a' : if ( MO . isImm ( ) ) { O << MO . getImm ( ) ; return false ; } if ( MO . isGlobal ( ) || MO . isCPI ( ) || MO . isJTI ( ) || MO . isSymbol ( ) ) { printSymbolOperand ( MO , O ) ; if ( Subtarget -> isPICStyleRIPRel ( ) ) O << "(%rip)" ; return false ; } if ( MO . isReg ( ) ) { O << '(' ; printOperand ( MI , OpNo , O ) ; O << ')' ; return false ; } return true ; case 'c' : if ( MO . isImm ( ) ) O << MO . getImm ( ) ; else if ( MO . isGlobal ( ) || MO . isCPI ( ) || MO . isJTI ( ) || MO . isSymbol ( ) ) printSymbolOperand ( MO , O ) ; else printOperand ( MI , OpNo , O ) ; return false ; case 'A' : if ( MO . isReg ( ) ) { O << '*' ; printOperand ( MI , OpNo , O ) ; return false ; } return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : if ( MO . isReg ( ) ) return printAsmMRegister ( MO , ExtraCode [ 0 ] , O ) ; printOperand ( MI , OpNo , O ) ; return false ; case 'P' : printPCRelImm ( MI , OpNo , O ) ; return false ; case 'n' : if ( MO . isImm ( ) ) { O << - MO . getImm ( ) ; return false ; } O << '-' ; } } printOperand ( MI , OpNo , O , 0 , AsmVariant ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> void emitGlobalVariable ( const GlobalVariable * GV ) override { } </s>

Emit the specified global variable to the .s file .


<s> const SICFrameLowering * SICFrameLowering :: create ( const SICSubtarget & ST ) { return new SICFrameLowering ( ST , ST . stackAlignment ( ) ) ; } </s>


<s> static unsigned int aarch64_dwarf_poly_indeterminate_value ( unsigned int i , unsigned int * factor , int * offset ) { gcc_assert ( i == 1 ) ; * factor = 2 ; * offset = 1 ; return AARCH64_DWARF_VG ; } </s>

Implement the TARGET_DWARF_POLY_INDETERMINATE_VALUE hook .


<s> static void loongarch_emit_float_compare ( enum rtx_code * code , rtx * op0 , rtx * op1 ) { rtx cmp_op0 = * op0 ; rtx cmp_op1 = * op1 ; enum rtx_code cmp_code = * code ; * code = NE ; * op0 = loongarch_allocate_fcc ( FCCmode ) ; * op1 = const0_rtx ; loongarch_emit_binary ( cmp_code , * op0 , cmp_op0 , cmp_op1 ) ; } </s>

Like loongarch_emit_int_compare , but for floating-point comparisons .


"parameter passing for argument of type "

Worker function for TARGET_SETUP_INCOMING_VARARGS . On the ARM , PRETEND_SIZE is set in order to have the prologue push the last named arg and all anonymous args onto the stack . XXX I know the prologue should n't be pushing registers , but it is faster that way .


<s>
const
RegisterBank
&
X86RegisterBankInfo
::
getRegBankFromRegClass
(
const
TargetRegisterClass
&
RC
)
const
{
if
(
X86
::
GR8RegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
GR16RegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
GR32RegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
GR64RegClass
.
hasSubClassEq
(
&
RC
)
)
return
getRegBank
(
X86
::
GPRRegBankID
)
;
llvm_unreachable
(
"Unsupported register kind yet."
)
;
}
</s>


<s> static rtx rs6000_function_value ( const_tree valtype , const_tree fn_decl_or_type ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode mode ; unsigned int regno ; machine_mode elt_mode ; int n_elts ; if ( TARGET_MACHO && rs6000_darwin64_struct_check_p ( TYPE_MODE ( valtype ) , valtype ) ) { CUMULATIVE_ARGS valcum ; rtx valret ; valcum . words = 0 ; valcum . fregno = FP_ARG_MIN_REG ; valcum . vregno = ALTIVEC_ARG_MIN_REG ; valret = rs6000_darwin64_record_arg ( & valcum , valtype , true , true ) ; if ( valret ) return valret ; } mode = TYPE_MODE ( valtype ) ; if ( rs6000_discover_homogeneous_aggregate ( mode , valtype , & elt_mode , & n_elts ) ) { int first_reg , n_regs ; if ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( elt_mode ) ) { first_reg = ( elt_mode == TDmode ) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN ; n_regs = ( GET_MODE_SIZE ( elt_mode ) + 7 ) >> 3 ; } else { first_reg = ALTIVEC_ARG_RETURN ; n_regs = 1 ; } return rs6000_parallel_return ( mode , n_elts , elt_mode , first_reg , n_regs ) ; } if ( TARGET_32BIT && TARGET_POWERPC64 ) switch ( mode ) { default : break ; case DImode : case SCmode : case DCmode : case TCmode : int count = GET_MODE_SIZE ( mode ) / 4 ; return rs6000_parallel_return ( mode , count , SImode , GP_ARG_RETURN , 1 ) ; } if ( ( INTEGRAL_TYPE_P ( valtype ) && GET_MODE_BITSIZE ( mode ) < ( TARGET_32BIT ? 32 : 64 ) ) || POINTER_TYPE_P ( valtype ) ) mode = TARGET_32BIT ? SImode : DImode ; if ( DECIMAL_FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = ( mode == TDmode ) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN ; else if ( SCALAR_FLOAT_TYPE_P ( valtype ) && TARGET_HARD_FLOAT && TARGET_FPRS && ! FLOAT128_VECTOR_P ( mode ) && ( ( TARGET_SINGLE_FLOAT && ( mode == SFmode ) ) || TARGET_DOUBLE_FLOAT ) ) regno = FP_ARG_RETURN ; else if ( TREE_CODE ( valtype ) == COMPLEX_TYPE && targetm . calls . split_complex_arg ) return rs6000_complex_function_value ( mode ) ; else if ( ( TREE_CODE ( valtype ) == VECTOR_TYPE || FLOAT128_VECTOR_P ( mode ) ) && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI && ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) ) regno = ALTIVEC_ARG_RETURN ; else if ( TARGET_E500_DOUBLE && TARGET_HARD_FLOAT && ( mode == DFmode || mode == DCmode || FLOAT128_IBM_P ( mode ) || mode == TCmode ) ) return spe_build_register_parallel ( mode , GP_ARG_RETURN ) ; else regno = GP_ARG_RETURN ; return gen_rtx_REG ( mode , regno ) ; } </s>

Define how to find the value returned by a function . VALTYPE is the data type of the value ( as a tree ) . If the precise function being called is known , FUNC is its FUNCTION_DECL ; otherwise , FUNC is 0 . On the SPE , both FPs and vectors are returned in r3 . On RS/6000 an integer value is in r3 and a floating-point value is in fp1 , unless -msoft-float .


<s> const uint32_t * AArch64RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return CSR_AArch64_NoRegs_RegMask ; if ( CC == CallingConv :: AnyReg ) return CSR_AArch64_AllRegs_RegMask ; if ( CC == CallingConv :: CXX_FAST_TLS ) return CSR_AArch64_CXX_TLS_Darwin_RegMask ; if ( CC == CallingConv :: AArch64_SVE_VectorCall ) return CSR_AArch64_SVE_AAPCS_RegMask ; if ( MF . getSubtarget < AArch64Subtarget > ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) -> getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_AArch64_AAPCS_SwiftError_RegMask ; if ( CC == CallingConv :: PreserveMost ) return CSR_AArch64_RT_MostRegs_RegMask ; else return CSR_AArch64_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void nvptx_function_end ( FILE * file ) { fprintf ( file , "\t}\n" ) ; } </s>

Terminate a function by writing a closing brace to FILE .


<s> bool isMem ( ) const override { return Kind == Memory ; } </s>


<s> Optional < ExtAddrMode > AArch64InstrInfo :: getAddrModeFromMemoryOp ( const MachineInstr & MemI , const TargetRegisterInfo * TRI ) const { const MachineOperand * Base ; int64_t Offset ; bool OffsetIsScalable ; if ( ! getMemOperandWithOffset ( MemI , Base , Offset , OffsetIsScalable , TRI ) ) return None ; if ( ! Base -> isReg ( ) ) return None ; ExtAddrMode AM ; AM . BaseReg = Base -> getReg ( ) ; AM . Displacement = Offset ; AM . ScaledReg = 0 ; return AM ; } </s>

Target dependent implementation to get the values constituting the address MachineInstr that is accessing memory .


"SPARC DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> EVT X86TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return Subtarget . hasAVX512 ( ) ? MVT :: i1 : MVT :: i8 ; if ( VT . isSimple ( ) ) { MVT VVT = VT . getSimpleVT ( ) ; const unsigned NumElts = VVT . getVectorNumElements ( ) ; const MVT EltVT = VVT . getVectorElementType ( ) ; if ( VVT . is512BitVector ( ) ) { if ( Subtarget . hasAVX512 ( ) ) if ( EltVT == MVT :: i32 || EltVT == MVT :: i64 || EltVT == MVT :: f32 || EltVT == MVT :: f64 ) switch ( NumElts ) { case 8 : return MVT :: v8i1 ; case 16 : return MVT :: v16i1 ; } if ( Subtarget . hasBWI ( ) ) if ( EltVT == MVT :: i8 || EltVT == MVT :: i16 ) switch ( NumElts ) { case 32 : return MVT :: v32i1 ; case 64 : return MVT :: v64i1 ; } } if ( VVT . is256BitVector ( ) || VVT . is128BitVector ( ) ) { if ( Subtarget . hasVLX ( ) ) if ( EltVT == MVT :: i32 || EltVT == MVT :: i64 || EltVT == MVT :: f32 || EltVT == MVT :: f64 ) switch ( NumElts ) { case 2 : return MVT :: v2i1 ; case 4 : return MVT :: v4i1 ; case 8 : return MVT :: v8i1 ; } if ( Subtarget . hasBWI ( ) && Subtarget . hasVLX ( ) ) if ( EltVT == MVT :: i8 || EltVT == MVT :: i16 ) switch ( NumElts ) { case 8 : return MVT :: v8i1 ; case 16 : return MVT :: v16i1 ; case 32 : return MVT :: v32i1 ; } } } return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> static opt_scalar_float_mode arm_floatn_mode ( int n , bool extended ) { if ( ! extended && n == 16 ) { if ( arm_fp16_format == ARM_FP16_FORMAT_IEEE ) return HFmode ; return opt_scalar_float_mode ( ) ; } return default_floatn_mode ( n , extended ) ; } </s>

Implement TARGET_FLOATN_MODE . Make very sure that we do n't provide _Float16 if we are using anything other than ieee format for 16-bit floating point . Otherwise , punt to the default implementation .


<s> unsigned PPCRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; const unsigned DefaultSafety = 1 ; switch ( RC -> getID ( ) ) { default : return 0 ; case PPC :: G8RC_NOX0RegClassID : case PPC :: GPRC_NOR0RegClassID : case PPC :: G8RCRegClassID : case PPC :: GPRCRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 32 - FP - DefaultSafety ; } case PPC :: F8RCRegClassID : case PPC :: F4RCRegClassID : case PPC :: VRRCRegClassID : case PPC :: VFRCRegClassID : case PPC :: VSLRCRegClassID : case PPC :: VSHRCRegClassID : return 32 - DefaultSafety ; case PPC :: VSRCRegClassID : case PPC :: VSFRCRegClassID : return 64 - DefaultSafety ; case PPC :: CRRCRegClassID : return 8 - DefaultSafety ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> SUnit * SIScheduleBlock :: pickNode ( ) { SISchedCandidate TopCand ; for ( SUnit * SU : TopReadySUs ) { SISchedCandidate TryCand ; std :: vector < unsigned > pressure ; std :: vector < unsigned > MaxPressure ; TryCand . SU = SU ; TopRPTracker . getDownwardPressure ( SU -> getInstr ( ) , pressure , MaxPressure ) ; TryCand . SGPRUsage = pressure [ AMDGPU :: RegisterPressureSets :: SReg_32 ] ; TryCand . VGPRUsage = pressure [ AMDGPU :: RegisterPressureSets :: VGPR_32 ] ; TryCand . IsLowLatency = DAG -> IsLowLatencySU [ SU -> NodeNum ] ; TryCand . LowLatencyOffset = DAG -> LowLatencyOffset [ SU -> NodeNum ] ; TryCand . HasLowLatencyNonWaitedParent = HasLowLatencyNonWaitedParent [ NodeNum2Index [ SU -> NodeNum ] ] ; tryCandidateTopDown ( TopCand , TryCand ) ; if ( TryCand . Reason != NoCand ) TopCand . setBest ( TryCand ) ; } return TopCand . SU ; } </s>

Pick the next node to schedule , or return NULL .

AMDGPU SI SI SI AMDGPU::RegisterPressureSets AMDGPU::RegisterPressureSets


<s> static int cr16_addr_reg_p ( rtx addr_reg ) { rtx reg ; if ( REG_P ( addr_reg ) ) reg = addr_reg ; else if ( ( GET_CODE ( addr_reg ) == SUBREG ) && REG_P ( SUBREG_REG ( addr_reg ) ) && ( GET_MODE_SIZE ( GET_MODE ( SUBREG_REG ( addr_reg ) ) ) <= UNITS_PER_WORD ) ) reg = SUBREG_REG ( addr_reg ) ; else return FALSE ; if ( GET_MODE ( reg ) != Pmode ) return FALSE ; return TRUE ; } </s>

Helper function to check if is a valid base register that can hold address .


<s> const uint16_t * X86RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { switch ( MF -> getFunction ( ) -> getCallingConv ( ) ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_SaveList ; case CallingConv :: Intel_OCL_BI : { bool HasAVX = TM . getSubtarget < X86Subtarget > ( ) . hasAVX ( ) ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_MostRegs_64_SaveList ; break ; default : break ; } bool CallsEHReturn = MF -> getMMI ( ) . callsEHReturn ( ) ; if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_SaveList ; if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; } if ( CallsEHReturn ) return CSR_32EHRet_SaveList ; return CSR_32_SaveList ; } </s>


<s> bool Mips16DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < MipsSubtarget > ( ) ; if ( ! Subtarget -> inMips16Mode ( ) ) return false ; return MipsDAGToDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> EVT MipsTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { if ( Subtarget -> hasMips64 ( ) ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> bool isCall ( const MCInst & MI , bool * IsIndirectCall ) { unsigned Opcode = MI . getOpcode ( ) ; * IsIndirectCall = false ; switch ( Opcode ) { default : return false ; case Mips :: JAL : case Mips :: BAL : case Mips :: BAL_BR : case Mips :: BLTZAL : case Mips :: BGEZAL : return true ; case Mips :: JALR : assert ( MI . getOperand ( 0 ) . isReg ( ) ) ; if ( MI . getOperand ( 0 ) . getReg ( ) == Mips :: ZERO ) return false ; * IsIndirectCall = true ; return true ; } } </s>

Mips Mips::JAL Mips::BAL Mips::BAL_BR Mips::BLTZAL Mips::BGEZAL Mips::JALR 0 0 Mips::ZERO


<s> TargetLoweringBase :: LegalizeTypeAction HexagonTargetLowering :: getPreferredVectorAction ( MVT VT ) const { unsigned VecLen = VT . getVectorMinNumElements ( ) ; MVT ElemTy = VT . getVectorElementType ( ) ; if ( VecLen == 1 || VT . isScalableVector ( ) ) return TargetLoweringBase :: TypeScalarizeVector ; if ( Subtarget . useHVXOps ( ) ) { unsigned Action = getPreferredHvxVectorAction ( VT ) ; if ( Action != ~ 0u ) return static_cast < TargetLoweringBase :: LegalizeTypeAction > ( Action ) ; } if ( ElemTy == MVT :: i1 ) return TargetLoweringBase :: TypeWidenVector ; if ( ! isPowerOf2_32 ( VecLen ) ) return TargetLoweringBase :: TypeWidenVector ; return TargetLoweringBase :: TypeSplitVector ; } </s>

Customize the preferred legalization strategy for certain types .


<s> static void flow_dependent_p_1 ( rtx x , const_rtx pat ATTRIBUTE_UNUSED , void * data ) { rtx * pinsn = ( rtx * ) data ; if ( * pinsn && reg_referenced_p ( x , * pinsn ) ) * pinsn = NULL_RTX ; } </s>

A helper function for flow_dependent_p called through note_stores .


<s> static bool zero_call_used_regno_p ( const unsigned int regno , bool all_sse_zeroed , bool need_zero_mmx ) { return GENERAL_REGNO_P ( regno ) || ( ! all_sse_zeroed && SSE_REGNO_P ( regno ) ) || MASK_REGNO_P ( regno ) || ( need_zero_mmx && MMX_REGNO_P ( regno ) ) ; } </s>

Check whether the register REGNO should be zeroed on X86 . When ALL_SSE_ZEROED is true , all SSE registers have been zeroed together , no need to zero it again . When NEED_ZERO_MMX is true , MMX registers should be cleared .


<s> BitVector PatmosRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = TM . getFrameLowering ( ) ; Reserved . set ( Patmos :: R0 ) ; Reserved . set ( Patmos :: P0 ) ; Reserved . set ( Patmos :: S0 ) ; Reserved . set ( Patmos :: S1 ) ; Reserved . set ( Patmos :: SL ) ; Reserved . set ( Patmos :: SH ) ; Reserved . set ( Patmos :: S4 ) ; Reserved . set ( Patmos :: SS ) ; Reserved . set ( Patmos :: ST ) ; Reserved . set ( Patmos :: SRB ) ; Reserved . set ( Patmos :: SRO ) ; Reserved . set ( Patmos :: SXB ) ; Reserved . set ( Patmos :: SXO ) ; Reserved . set ( Patmos :: S11 ) ; Reserved . set ( Patmos :: S12 ) ; Reserved . set ( Patmos :: S13 ) ; Reserved . set ( Patmos :: S14 ) ; Reserved . set ( Patmos :: S15 ) ; Reserved . set ( Patmos :: RSP ) ; Reserved . set ( Patmos :: RFP ) ; Reserved . set ( Patmos :: RTR ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( Patmos :: RFP ) ; if ( PatmosSinglePathInfo :: isEnabled ( MF ) ) { Reserved . set ( Patmos :: R26 ) ; Reserved . set ( Patmos :: P6 ) ; Reserved . set ( Patmos :: P7 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { MachineFunctionPass :: getAnalysisUsage ( AU ) ; AU . addRequired < LiveIntervals > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> Instruction * llvm :: getInst ( Value * base , char * instName ) { Function * F = getParentFunction ( base ) ; if ( F == 0 ) return 0 ; for ( inst_iterator it = inst_begin ( F ) , ie = inst_end ( F ) ; it != ie ; ++ it ) { Instruction * I = & * it ; if ( strcmp ( I -> getName ( ) . data ( ) , instName ) == 0 ) { return I ; } } return 0 ; } </s>

If this is a normal dependency , returns the instruction that is depended on .


<s>
void
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
)
const
{
unsigned
Size
=
1
<<
getFixupKindLog2Size
(
Fixup
.
getKind
(
)
)
;
assert
(
Fixup
.
getOffset
(
)
+
Size
<=
DataSize
&&
"Invalid fixup offset!"
)
;
assert
(
isIntN
(
Size
*
8
+
1
,
Value
)
&&
"Value does not fit in the Fixup field"
)
;
for
(
unsigned
i
=
0
;
i
!=
Size
;
++
i
)
Data
[
Fixup
.
getOffset
(
)
+
i
]
=
uint8_t
(
Value
>>
(
i
*
8
)
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static int n_regs_saved_by_prologue ( void ) { e_funkind fkind = funkind ( TREE_TYPE ( current_function_decl ) ) ; bool is_inthandler = fkind != SUBROUTINE ; tree attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ; bool all = ( lookup_attribute ( "saveall" , attrs ) != NULL_TREE || ( is_inthandler && ! crtl -> is_leaf ) ) ; int ndregs = all ? 8 : n_dregs_to_save ( is_inthandler , false ) ; int npregs = all ? 6 : n_pregs_to_save ( is_inthandler , false ) ; int n = ndregs + npregs ; int i ; if ( all || stack_frame_needed_p ( ) ) n += 2 ; else { if ( must_save_fp_p ( ) ) n ++ ; if ( must_save_rets_p ( ) ) n ++ ; } if ( fkind != SUBROUTINE || all ) { n ++ ; if ( ! crtl -> is_leaf || cfun -> machine -> has_hardware_loops || cfun -> machine -> has_loopreg_clobber ) { n += 6 ; } } if ( fkind != SUBROUTINE ) { if ( lookup_attribute ( "nesting" , attrs ) ) n ++ ; } for ( i = REG_P7 + 1 ; i < REG_CC ; i ++ ) if ( all || ( fkind != SUBROUTINE && ( df_regs_ever_live_p ( i ) || ( ! leaf_function_p ( ) && call_used_regs [ i ] ) ) ) ) n += i == REG_A0 || i == REG_A1 ? 2 : 1 ; return n ; } </s>

Return the number of registers pushed during the prologue .


<s> void TriCoreInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << "%" << StringRef ( getRegisterName ( RegNo ) ) . lower ( ) ; } </s>


"********** ARM EXPAND PSEUDO INSTRUCTIONS **********\n"

"After expanding ARM pseudo instructions."


<s> bool WebAssemblyPeephole :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; WebAssemblyFunctionInfo & MFI = * MF . getInfo < WebAssemblyFunctionInfo > ( ) ; for ( auto & MBB : MF ) for ( auto & MI : MBB ) switch ( MI . getOpcode ( ) ) { default : break ; case WebAssembly :: STORE8_I32 : case WebAssembly :: STORE16_I32 : case WebAssembly :: STORE8_I64 : case WebAssembly :: STORE16_I64 : case WebAssembly :: STORE32_I64 : case WebAssembly :: STORE_F32 : case WebAssembly :: STORE_F64 : case WebAssembly :: STORE_I32 : case WebAssembly :: STORE_I64 : { MachineOperand & MO = MI . getOperand ( 0 ) ; unsigned OldReg = MO . getReg ( ) ; if ( OldReg == MI . getOperand ( 3 ) . getReg ( ) && TargetRegisterInfo :: isVirtualRegister ( MI . getOperand ( 3 ) . getReg ( ) ) ) { Changed = true ; unsigned NewReg = MRI . createVirtualRegister ( MRI . getRegClass ( OldReg ) ) ; MO . setReg ( NewReg ) ; MO . setIsDead ( ) ; MFI . stackifyVReg ( NewReg ) ; MFI . addWAReg ( NewReg , WebAssemblyFunctionInfo :: UnusedReg ) ; } } } return Changed ; } </s>


<s> rtx legitimize_reload_address ( rtx ad , enum machine_mode mode ATTRIBUTE_UNUSED , int opnum , int type ) { if ( ! optimize || TARGET_LONG_DISPLACEMENT ) return NULL_RTX ; if ( GET_CODE ( ad ) == PLUS ) { rtx tem = simplify_binary_operation ( PLUS , Pmode , XEXP ( ad , 0 ) , XEXP ( ad , 1 ) ) ; if ( tem ) ad = tem ; } if ( GET_CODE ( ad ) == PLUS && GET_CODE ( XEXP ( ad , 0 ) ) == REG && GET_CODE ( XEXP ( ad , 1 ) ) == CONST_INT && ! DISP_IN_RANGE ( INTVAL ( XEXP ( ad , 1 ) ) ) ) { HOST_WIDE_INT lower = INTVAL ( XEXP ( ad , 1 ) ) & 0xfff ; HOST_WIDE_INT upper = INTVAL ( XEXP ( ad , 1 ) ) ^ lower ; rtx cst , tem , new ; cst = GEN_INT ( upper ) ; if ( ! legitimate_reload_constant_p ( cst ) ) cst = force_const_mem ( Pmode , cst ) ; tem = gen_rtx_PLUS ( Pmode , XEXP ( ad , 0 ) , cst ) ; new = gen_rtx_PLUS ( Pmode , tem , GEN_INT ( lower ) ) ; push_reload ( XEXP ( tem , 1 ) , 0 , & XEXP ( tem , 1 ) , 0 , BASE_REG_CLASS , Pmode , VOIDmode , 0 , 0 , opnum , ( enum reload_type ) type ) ; return new ; } return NULL_RTX ; } </s>

Try a machine-dependent way of reloading an illegitimate address AD operand . If we find one , push the reload and and return the new address . MODE is the mode of the enclosing MEM . OPNUM is the operand number and TYPE is the reload type of the current reload .


<s> const TOYRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> ScheduleHazardRecognizer * HexagonInstrInfo :: CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II , const ScheduleDAG * DAG ) const { if ( UseDFAHazardRec ) return new HexagonHazardRecognizer ( II , this , Subtarget ) ; return TargetInstrInfo :: CreateTargetPostRAHazardRecognizer ( II , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for by non-scheduling passes .


<s> int arx_reg_operand ( rtx op , enum machine_mode mode ) { if ( mode != VOIDmode && mode != GET_MODE ( op ) ) return 0 ; if ( GET_CODE ( op ) == SUBREG ) op = SUBREG_REG ( op ) ; return REG_P ( op ) && ( ! reload_completed || IS_ADDR_REG ( op ) ) ; } </s>

Return true if any one of the address registers .


<s>
void
SIInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
SIMachineFunctionInfo
*
MFI
=
MF
->
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MachineFrameInfo
&
FrameInfo
=
MF
->
getFrameInfo
(
)
;
const
DebugLoc
&
DL
=
MBB
.
findDebugLoc
(
MI
)
;
unsigned
Size
=
FrameInfo
.
getObjectSize
(
FrameIndex
)
;
unsigned
Align
=
FrameInfo
.
getObjectAlignment
(
FrameIndex
)
;
MachinePointerInfo
PtrInfo
=
MachinePointerInfo
::
getFixedStack
(
*
MF
,
FrameIndex
)
;
MachineMemOperand
*
MMO
=
MF
->
getMachineMemOperand
(
PtrInfo
,
MachineMemOperand
::
MOStore
,
Size
,
Align
)
;
unsigned
SpillSize
=
TRI
->
getSpillSize
(
*
RC
)
;
if
(
RI
.
isSGPRClass
(
RC
)
)
{
MFI
->
setHasSpilledSGPRs
(
)
;
const
MCInstrDesc
&
OpDesc
=
get
(
getSGPRSpillSaveOpcode
(
SpillSize
)
)
;
if
(
TargetRegisterInfo
::
isVirtualRegister
(
SrcReg
)
&&
SpillSize
==
4
)
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
MRI
.
constrainRegClass
(
SrcReg
,
&
AMDGPU
::
SReg_32_XM0RegClass
)
;
}
MachineInstrBuilder
Spill
=
BuildMI
(
MBB
,
MI
,
DL
,
OpDesc
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIndex
)
.
addMemOperand
(
MMO
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
,
RegState
::
Implicit
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
,
RegState
::
Implicit
)
;
FrameInfo
.
setStackID
(
FrameIndex
,
TargetStackID
::
SGPRSpill
)
;
if
(
ST
.
hasScalarStores
(
)
)
{
Spill
.
addReg
(
AMDGPU
::
M0
,
RegState
::
ImplicitDefine
|
RegState
::
Dead
)
;
}
return
;
}
assert
(
RI
.
hasVGPRs
(
RC
)
&&
"Only VGPR spilling expected"
)
;
unsigned
Opcode
=
getVGPRSpillSaveOpcode
(
SpillSize
)
;
MFI
->
setHasSpilledVGPRs
(
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opcode
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIndex
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> static bool loongarch_rtx_constant_in_small_data_p ( machine_mode mode ) { return ( GET_MODE_SIZE ( mode ) <= g_switch_value ) ; } </s>

Return true if rtx constants of mode MODE should be put into a small data section .


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> hasFnAttr ( Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( N -> getOpcode ( ) == X86ISD :: CALL || N -> getOpcode ( ) == X86ISD :: TC_RETURN ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; EVT SrcVT = N -> getOperand ( 0 ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( 0 ) ; bool SrcIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , NULL , 0 , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , DstVT , dl , Store , MemTmp , NULL , 0 , MemVT , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { bool is64 = getPointerSize ( ) == 8 ; return createPPCELFObjectWriter ( OS , is64 , isLittleEndian ( ) , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> unsigned MBlazeIntrinsicInfo :: lookupName ( const char * Name , unsigned Len ) const { if ( ! StringRef ( Name , Len ) . startswith ( "llvm." ) ) return 0 ; return 0 ; } </s>


<s> static bool v850_reg_ok_for_base_p ( const_rtx reg , bool strict_p ) { if ( strict_p ) { return REGNO_OK_FOR_BASE_P ( REGNO ( reg ) ) ; } else { return true ; } } </s>

Helper function for ` v850_legitimate_address_p ' .


<s>
std
::
string
getNodeLabel
(
const
ablock
*
AB
,
const
agraph
&
G
)
{
std
::
stringstream
s
;
s
<<
AB
->
getName
(
)
<<
" ("
<<
AB
->
NumPreds
<<
")"
;
s
<<
"\n"
<<
AB
->
Size
<<
" ("
<<
AB
->
SCCSize
<<
")"
;
if
(
AB
->
Region
)
s
<<
"\n"
<<
AB
->
Region
->
getName
(
)
;
return
s
.
str
(
)
;
}
</s>

Print a DDG node either in concise form ( -ddg-dot-only ) or verbose mode ( -ddg-dot ) .


<s> MachineBasicBlock :: iterator MSP430FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const MSP430InstrInfo & TII = * static_cast < const MSP430InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; unsigned StackAlign = getStackAlignment ( ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; uint64_t Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = nullptr ; if ( Old -> getOpcode ( ) == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( MSP430 :: SUB16ri ) , MSP430 :: SP ) . addReg ( MSP430 :: SP ) . addImm ( Amount ) ; } else { assert ( Old -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) ; uint64_t CalleeAmt = Old -> getOperand ( 1 ) . getImm ( ) ; Amount -= CalleeAmt ; if ( Amount ) New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( MSP430 :: ADD16ri ) , MSP430 :: SP ) . addReg ( MSP430 :: SP ) . addImm ( Amount ) ; } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { MachineInstr * Old = I ; MachineInstr * New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( MSP430 :: SUB16ri ) , MSP430 :: SP ) . addReg ( MSP430 :: SP ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> void TOYFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; uint64_t StackSize = computeStackSize ( MF ) ; if ( ! StackSize ) { return ; } unsigned StackReg = TOY :: SP ; unsigned OffsetReg = materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ; if ( OffsetReg ) { BuildMI ( MBB , MBBI , dl , TII . get ( TOY :: ADDrr ) , StackReg ) . addReg ( StackReg ) . addReg ( OffsetReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( TOY :: ADDri ) , StackReg ) . addReg ( StackReg ) . addImm ( StackSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } } </s>


<s> bool isTarget64BitILP32 ( ) const { return In64BitMode && ( TargetTriple . getEnvironment ( ) == Triple :: GNUX32 || TargetTriple . getOS ( ) == Triple :: NaCl ) ; } </s>

Is this x86_64 with the ILP32 programming model ( x32 ABI ) ?


<s>
unsigned
AArch64MCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
else
{
assert
(
MO
.
isImm
(
)
&&
"did not expect relocated expression"
)
;
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
assert
(
0
&&
"Unable to encode MCOperand!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> static HOST_WIDE_INT aarch64_simd_vector_alignment ( const_tree type ) { HOST_WIDE_INT align = tree_to_shwi ( TYPE_SIZE ( type ) ) ; return MIN ( align , 128 ) ; } </s>

Implement target hook TARGET_VECTOR_ALIGNMENT . The AAPCS64 sets the maximum alignment of a vector to 128 bits .


<s>
bool
HexagonInstrInfo
::
PredicateInstruction
(
MachineInstr
&
MI
,
ArrayRef
<
MachineOperand
>
Cond
)
const
{
if
(
Cond
.
empty
(
)
||
isNewValueJump
(
Cond
[
0
]
.
getImm
(
)
)
||
isEndLoopN
(
Cond
[
0
]
.
getImm
(
)
)
)
{
DEBUG
(
dbgs
(
)
<<
"\nCannot predicate:"
;
MI
.
dump
(
)
;
)
;
return
false
;
}
int
Opc
=
MI
.
getOpcode
(
)
;
assert
(
isPredicable
(
MI
)
&&
"Expected predicable instruction"
)
;
bool
invertJump
=
predOpcodeHasNot
(
Cond
)
;
MachineBasicBlock
&
B
=
*
MI
.
getParent
(
)
;
DebugLoc
DL
=
MI
.
getDebugLoc
(
)
;
unsigned
PredOpc
=
getCondOpcode
(
Opc
,
invertJump
)
;
MachineInstrBuilder
T
=
BuildMI
(
B
,
MI
,
DL
,
get
(
PredOpc
)
)
;
unsigned
NOp
=
0
,
NumOps
=
MI
.
getNumOperands
(
)
;
while
(
NOp
<
NumOps
)
{
MachineOperand
&
Op
=
MI
.
getOperand
(
NOp
)
;
if
(
!
Op
.
isReg
(
)
||
!
Op
.
isDef
(
)
||
Op
.
isImplicit
(
)
)
break
;
T
.
addOperand
(
Op
)
;
NOp
++
;
}
unsigned
PredReg
,
PredRegPos
,
PredRegFlags
;
bool
GotPredReg
=
getPredReg
(
Cond
,
PredReg
,
PredRegPos
,
PredRegFlags
)
;
(
void
)
GotPredReg
;
assert
(
GotPredReg
)
;
T
.
addReg
(
PredReg
,
PredRegFlags
)
;
while
(
NOp
<
NumOps
)
T
.
addOperand
(
MI
.
getOperand
(
NOp
++
)
)
;
MI
.
setDesc
(
get
(
PredOpc
)
)
;
while
(
unsigned
n
=
MI
.
getNumOperands
(
)
)
MI
.
RemoveOperand
(
n
1
)
;
for
(
unsigned
i
=
0
,
n
=
T
->
getNumOperands
(
)
;
i
<
n
;
++
i
)
MI
.
addOperand
(
T
->
getOperand
(
i
)
)
;
MachineBasicBlock
::
instr_iterator
TI
=
T
->
getIterator
(
)
;
B
.
erase
(
TI
)
;
MachineRegisterInfo
&
MRI
=
B
.
getParent
(
)
->
getRegInfo
(
)
;
MRI
.
clearKillFlags
(
PredReg
)
;
return
true
;
}
</s>

Convert the instruction into a predicated instruction .


<s>
void
Z80oldInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
IsKill
,
int
FI
,
const
TargetRegisterClass
*
TRC
,
const
TargetRegisterInfo
*
TRI
)
const
{
unsigned
Opc
;
switch
(
TRI
->
getSpillSize
(
*
TRC
)
)
{
default
:
llvm_unreachable
(
"Unexpected regclass size"
)
;
case
1
:
Opc
=
Z80old
::
LD8or
;
break
;
case
2
:
Opc
=
Z80old
::
LD88or
;
break
;
}
BuildMI
(
MBB
,
MI
,
MBB
.
findDebugLoc
(
MI
)
,
get
(
Opc
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addReg
(
SrcReg
,
getKillRegState
(
IsKill
)
)
;
return
;
unsigned
RC
,
LoOpc
,
LoIdx
,
HiOpc
,
HiIdx
,
HiOff
;
bool
Split
=
Z80old
::
splitReg
(
TRI
->
getSpillSize
(
*
TRC
)
,
Z80old
::
LD8or
,
RC
,
LoOpc
,
LoIdx
,
HiOpc
,
HiIdx
,
HiOff
)
;
MachineInstrBuilder
LoMIB
=
addSubReg
(
BuildMI
(
MBB
,
MI
,
MBB
.
findDebugLoc
(
MI
)
,
get
(
LoOpc
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
,
SrcReg
,
LoIdx
,
TRI
,
getKillRegState
(
IsKill
)
)
;
if
(
Split
)
{
MachineInstrBuilder
HiMIB
=
addSubReg
(
BuildMI
(
MBB
,
MI
,
MBB
.
findDebugLoc
(
MI
)
,
get
(
HiOpc
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
HiOff
)
,
SrcReg
,
HiIdx
,
TRI
,
getKillRegState
(
IsKill
)
)
;
if
(
IsKill
)
{
HiMIB
->
addRegisterKilled
(
SrcReg
,
TRI
,
true
)
;
}
}
}
</s>


<s> bool GBZ80InstrInfo :: analyzeBranchPredicate ( MachineBasicBlock & MBB , MachineBranchPredicate & MBP , bool AllowModify ) const { SmallVector < MachineOperand , 4 > Cond ; MachineBasicBlock * FBB = nullptr , * TBB = nullptr ; if ( analyzeBranch ( MBB , TBB , FBB , Cond , AllowModify ) ) return true ; return true ; } </s>

Analyze the branching code at the end of MBB and parse it into the MachineBranchPredicate structure if possible .


<s> unsigned LanaiRegisterInfo :: getFrameRegister ( const MachineFunction & ) const { return Lanai :: FP ; } </s>


<s> bool SparcDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintID ) { default : return true ; case InlineAsm :: Constraint_o : case InlineAsm :: Constraint_m : if ( ! SelectADDRrr ( Op , Op0 , Op1 ) ) SelectADDRri ( Op , Op0 , Op1 ) ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> MCInst M88kInstrInfo :: getNop ( ) const { return MCInstBuilder ( M88k :: ORrr ) . addReg ( M88k :: R0 ) . addReg ( M88k :: R0 ) . addReg ( M88k :: R0 ) ; } </s>

Return the noop instruction to use for a noop .


<s> void thumb2_final_prescan_insn ( rtx_insn * insn ) { rtx_insn * first_insn = insn ; rtx body = PATTERN ( insn ) ; rtx predicate ; enum arm_cond_code code ; int n ; int mask ; int max ; max = MAX_INSN_PER_IT_BLOCK ; if ( arm_condexec_count ) arm_condexec_count -- ; if ( arm_condexec_count ) return ; if ( GET_CODE ( body ) != COND_EXEC ) return ; if ( JUMP_P ( insn ) ) return ; predicate = COND_EXEC_TEST ( body ) ; arm_current_cc = get_arm_condition_code ( predicate ) ; n = get_attr_ce_count ( insn ) ; arm_condexec_count = 1 ; arm_condexec_mask = ( 1 << n ) - 1 ; arm_condexec_masklen = n ; for ( ; ; ) { insn = next_nonnote_insn ( insn ) ; if ( ! NONJUMP_INSN_P ( insn ) && ! JUMP_P ( insn ) ) break ; body = PATTERN ( insn ) ; if ( GET_CODE ( body ) == USE || GET_CODE ( body ) == CLOBBER ) continue ; if ( GET_CODE ( body ) != COND_EXEC ) break ; n = get_attr_ce_count ( insn ) ; if ( arm_condexec_masklen + n > max ) break ; predicate = COND_EXEC_TEST ( body ) ; code = get_arm_condition_code ( predicate ) ; mask = ( 1 << n ) - 1 ; if ( arm_current_cc == code ) arm_condexec_mask |= ( mask << arm_condexec_masklen ) ; else if ( arm_current_cc != ARM_INVERSE_CONDITION_CODE ( code ) ) break ; arm_condexec_count ++ ; arm_condexec_masklen += n ; if ( JUMP_P ( insn ) ) break ; } extract_constrain_insn_cached ( first_insn ) ; } </s>

Tell arm_asm_output_opcode to output IT blocks for conditionally executed instructions .


<s> int legitimate_address_p ( enum machine_mode mode , rtx x , int strict ) { rtx xfoo0 , xfoo1 ; if ( nonindexed_address_p ( x , strict ) ) return 1 ; if ( GET_CODE ( x ) != PLUS ) return 0 ; xfoo0 = XEXP ( x , 0 ) ; xfoo1 = XEXP ( x , 1 ) ; if ( index_term_p ( xfoo0 , mode , strict ) && nonindexed_address_p ( xfoo1 , strict ) ) return 1 ; if ( index_term_p ( xfoo1 , mode , strict ) && nonindexed_address_p ( xfoo0 , strict ) ) return 1 ; if ( indirectable_constant_address_p ( xfoo0 ) && ( BASE_REGISTER_P ( xfoo1 , strict ) || reg_plus_index_p ( xfoo1 , mode , strict ) ) ) return 1 ; if ( indirectable_constant_address_p ( xfoo1 ) && ( BASE_REGISTER_P ( xfoo0 , strict ) || reg_plus_index_p ( xfoo0 , mode , strict ) ) ) return 1 ; return 0 ; } </s>

legitimate_address_p returns 1 if it recognizes an RTL expression `` x '' that is a valid memory address for an instruction . The MODE argument is the machine mode for the MEM expression that wants to use this address .


"********** AArch64 Conditional Compares **********\n"

runOnMachineFunction - Emit the function body .


<s> unsigned getCacheLineSize ( ) const override { return CacheLineSize ; } </s>

Return the target cache line size in bytes .


<s> TargetPassConfig * PPCTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new PPCPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s>
bool
TOYPreRegAlloc
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
DEBUG
(
dbgs
(
)
<<
"********* TOY PreRegAlloc *********\n"
)
;
bool
Changed
=
false
;
Changed
|=
peepholeOpt
(
MF
)
;
return
Changed
;
}
</s>

TOY
TOY
"********* TOY PreRegAlloc *********\n"


<s> bool aarch64_emit_approx_sqrt ( rtx dst , rtx src , bool recp ) { machine_mode mode = GET_MODE ( dst ) ; if ( GET_MODE_INNER ( mode ) == HFmode ) { gcc_assert ( ! recp ) ; return false ; } if ( ! recp ) { if ( ! ( flag_mlow_precision_sqrt || ( aarch64_tune_params . approx_modes -> sqrt & AARCH64_APPROX_MODE ( mode ) ) ) ) return false ; if ( flag_finite_math_only || flag_trapping_math || ! flag_unsafe_math_optimizations || optimize_function_for_size_p ( cfun ) ) return false ; } else gcc_assert ( use_rsqrt_p ( mode ) ) ; machine_mode mmsk = mode_for_int_vector ( mode ) . require ( ) ; rtx xmsk = gen_reg_rtx ( mmsk ) ; if ( ! recp ) emit_insn ( gen_rtx_SET ( xmsk , gen_rtx_NEG ( mmsk , gen_rtx_EQ ( mmsk , src , CONST0_RTX ( mode ) ) ) ) ) ; rtx xdst = gen_reg_rtx ( mode ) ; emit_insn ( ( * get_rsqrte_type ( mode ) ) ( xdst , src ) ) ; int iterations = ( GET_MODE_INNER ( mode ) == DFmode ) ? 3 : 2 ; if ( ( recp && flag_mrecip_low_precision_sqrt ) || ( ! recp && flag_mlow_precision_sqrt ) ) iterations -- ; rtx x1 = gen_reg_rtx ( mode ) ; while ( iterations -- ) { rtx x2 = gen_reg_rtx ( mode ) ; emit_set_insn ( x2 , gen_rtx_MULT ( mode , xdst , xdst ) ) ; emit_insn ( ( * get_rsqrts_type ( mode ) ) ( x1 , src , x2 ) ) ; if ( iterations > 0 ) emit_set_insn ( xdst , gen_rtx_MULT ( mode , xdst , x1 ) ) ; } if ( ! recp ) { rtx xtmp = gen_reg_rtx ( mmsk ) ; emit_set_insn ( xtmp , gen_rtx_AND ( mmsk , gen_rtx_NOT ( mmsk , xmsk ) , gen_rtx_SUBREG ( mmsk , xdst , 0 ) ) ) ; emit_move_insn ( xdst , gen_rtx_SUBREG ( mode , xtmp , 0 ) ) ; emit_set_insn ( xdst , gen_rtx_MULT ( mode , xdst , src ) ) ; } emit_set_insn ( dst , gen_rtx_MULT ( mode , xdst , x1 ) ) ; return true ; } </s>

Emit instruction sequence to compute either the approximate square root or its approximate reciprocal , depending on the flag RECP , and return whether the sequence was emitted or not .


<s> bool TPCAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> static int rs6000_psave_function_arg ( machine_mode mode , const_tree type , int align_words , rtx * rvec ) { int k = 0 ; if ( align_words < GP_ARG_NUM_REG ) { int n_words = rs6000_arg_size ( mode , type ) ; if ( align_words + n_words > GP_ARG_NUM_REG || mode == BLKmode || ( TARGET_32BIT && TARGET_POWERPC64 ) ) { machine_mode rmode = TARGET_32BIT ? SImode : DImode ; int i = 0 ; if ( align_words + n_words > GP_ARG_NUM_REG ) { rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; } do { rtx r = gen_rtx_REG ( rmode , GP_ARG_MIN_REG + align_words ) ; rtx off = GEN_INT ( i ++ * GET_MODE_SIZE ( rmode ) ) ; rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , r , off ) ; } while ( ++ align_words < GP_ARG_NUM_REG && -- n_words != 0 ) ; } else { rtx r = gen_rtx_REG ( mode , GP_ARG_MIN_REG + align_words ) ; rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , r , const0_rtx ) ; } } else { rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; } return k ; } </s>

We have an argument of MODE and TYPE that goes into FPRs or VRs , but must also be copied into the parameter save area starting at offset ALIGN_WORDS . Fill in RVEC with the elements corresponding to the GPRs and/or memory . Return the number of elements used .


<s>
static
int
rs6000_arg_partial_bytes
(
CUMULATIVE_ARGS
*
cum
,
enum
machine_mode
mode
,
tree
type
,
bool
named
)
{
int
ret
=
0
;
int
align_words
;
if
(
DEFAULT_ABI
==
ABI_V4
)
return
0
;
if
(
USE_ALTIVEC_FOR_ARG_P
(
cum
,
mode
,
type
,
named
)
&&
cum
->
nargs_prototype
>=
0
)
return
0
;
if
(
rs6000_darwin64_abi
&&
mode
==
BLKmode
&&
TREE_CODE
(
type
)
==
RECORD_TYPE
&&
int_size_in_bytes
(
type
)
>
0
)
return
0
;
align_words
=
rs6000_parm_start
(
mode
,
type
,
cum
->
words
)
;
if
(
USE_FP_FOR_ARG_P
(
cum
,
mode
,
type
)
&&
!
(
type
&&
(
cum
->
nargs_prototype
<=
0
||
(
DEFAULT_ABI
==
ABI_AIX
&&
TARGET_XL_COMPAT
&&
align_words
>=
GP_ARG_NUM_REG
)
)
)
)
{
if
(
cum
->
fregno
+
(
(
GET_MODE_SIZE
(
mode
)
+
7
)
>>
3
)
>
FP_ARG_MAX_REG
+
1
)
ret
=
(
FP_ARG_MAX_REG
+
1
cum
->
fregno
)
*
8
;
else
if
(
cum
->
nargs_prototype
>=
0
)
return
0
;
}
if
(
align_words
<
GP_ARG_NUM_REG
&&
GP_ARG_NUM_REG
<
align_words
+
rs6000_arg_size
(
mode
,
type
)
)
ret
=
(
GP_ARG_NUM_REG
align_words
)
*
(
TARGET_32BIT
4
:
8
)
;
if
(
ret
!=
0
&&
TARGET_DEBUG_ARG
)
fprintf
(
stderr
,
"rs6000_arg_partial_bytes: %d\n"
,
ret
)
;
return
ret
;
}
</s>

For an arg passed partly in registers and partly in memory , this is the number of bytes passed in registers . For args passed entirely in registers or entirely in memory , zero . When an arg is described by a PARALLEL , perhaps using more than one register type , this function returns the number of bytes used by the first element of the PARALLEL .


<s> int call_operand ( rtx op , enum machine_mode mode ) { if ( GET_CODE ( op ) != MEM ) return 0 ; op = XEXP ( op , 0 ) ; return call_address_operand ( op , mode ) ; } </s>

Call insn on SPARC can take a PC-relative constant address , or any regular memory address .


<s> TargetPassConfig * X86TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new X86PassConfig ( this , PM ) ; } </s>


<s>
Register
OutgoingValueHandler
::
extendRegister
(
Register
ValReg
,
const
CCValAssign
&
VA
)
{
LLT
LocTy
{
VA
.
getLocVT
(
)
}
;
switch
(
VA
.
getLocInfo
(
)
)
{
case
CCValAssign
::
SExt
:
{
return
MIRBuilder
.
buildSExt
(
LocTy
,
ValReg
)
.
getReg
(
0
)
;
}
case
CCValAssign
::
ZExt
:
{
return
MIRBuilder
.
buildZExt
(
LocTy
,
ValReg
)
.
getReg
(
0
)
;
}
case
CCValAssign
::
AExt
:
{
return
MIRBuilder
.
buildAnyExt
(
LocTy
,
ValReg
)
.
getReg
(
0
)
;
}
case
CCValAssign
::
Full
:
return
ValReg
;
default
:
break
;
}
llvm_unreachable
(
"unable to extend register"
)
;
}
</s>

Extend a register to the location type given in VA , capped at extending to at most MaxSize bits .


<s> void mips_conditional_register_usage ( void ) { if ( ! TARGET_DSP ) { int regno ; for ( regno = DSP_ACC_REG_FIRST ; regno <= DSP_ACC_REG_LAST ; regno ++ ) fixed_regs [ regno ] = call_used_regs [ regno ] = 1 ; } if ( ! TARGET_HARD_FLOAT ) { int regno ; for ( regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) fixed_regs [ regno ] = call_used_regs [ regno ] = 1 ; for ( regno = ST_REG_FIRST ; regno <= ST_REG_LAST ; regno ++ ) fixed_regs [ regno ] = call_used_regs [ regno ] = 1 ; } else if ( ! ISA_HAS_8CC ) { int regno ; for ( regno = ST_REG_FIRST ; regno <= ST_REG_LAST ; regno ++ ) fixed_regs [ regno ] = call_used_regs [ regno ] = 1 ; } if ( TARGET_MIPS16 ) { fixed_regs [ 18 ] = call_used_regs [ 18 ] = 1 ; fixed_regs [ 19 ] = call_used_regs [ 19 ] = 1 ; fixed_regs [ 20 ] = call_used_regs [ 20 ] = 1 ; fixed_regs [ 21 ] = call_used_regs [ 21 ] = 1 ; fixed_regs [ 22 ] = call_used_regs [ 22 ] = 1 ; fixed_regs [ 23 ] = call_used_regs [ 23 ] = 1 ; fixed_regs [ 26 ] = call_used_regs [ 26 ] = 1 ; fixed_regs [ 27 ] = call_used_regs [ 27 ] = 1 ; fixed_regs [ 30 ] = call_used_regs [ 30 ] = 1 ; } if ( mips_abi == ABI_64 ) { int regno ; for ( regno = FP_REG_FIRST + 20 ; regno < FP_REG_FIRST + 24 ; regno ++ ) call_really_used_regs [ regno ] = call_used_regs [ regno ] = 1 ; } if ( mips_abi == ABI_N32 ) { int regno ; for ( regno = FP_REG_FIRST + 21 ; regno <= FP_REG_FIRST + 31 ; regno += 2 ) call_really_used_regs [ regno ] = call_used_regs [ regno ] = 1 ; } } </s>


Return appropriate code to load up a 1 , 2 , or 4 integer/floating point value .


<s> const MCPhysReg * TriCoreRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const MCPhysReg CalleeSavedRegs [ ] = { 0 } ; return CalleeSavedRegs ; } </s>


<s> static unsigned selectBinaryOp ( unsigned GenericOpc , unsigned RegBankID , unsigned OpSize ) { switch ( RegBankID ) { case AArch64 :: GPRRegBankID : if ( OpSize == 32 ) { switch ( GenericOpc ) { case TargetOpcode :: G_SHL : return AArch64 :: LSLVWr ; case TargetOpcode :: G_LSHR : return AArch64 :: LSRVWr ; case TargetOpcode :: G_ASHR : return AArch64 :: ASRVWr ; default : return GenericOpc ; } } else if ( OpSize == 64 ) { switch ( GenericOpc ) { case TargetOpcode :: G_GEP : return AArch64 :: ADDXrr ; case TargetOpcode :: G_SHL : return AArch64 :: LSLVXr ; case TargetOpcode :: G_LSHR : return AArch64 :: LSRVXr ; case TargetOpcode :: G_ASHR : return AArch64 :: ASRVXr ; default : return GenericOpc ; } } break ; case AArch64 :: FPRRegBankID : switch ( OpSize ) { case 32 : switch ( GenericOpc ) { case TargetOpcode :: G_FADD : return AArch64 :: FADDSrr ; case TargetOpcode :: G_FSUB : return AArch64 :: FSUBSrr ; case TargetOpcode :: G_FMUL : return AArch64 :: FMULSrr ; case TargetOpcode :: G_FDIV : return AArch64 :: FDIVSrr ; default : return GenericOpc ; } case 64 : switch ( GenericOpc ) { case TargetOpcode :: G_FADD : return AArch64 :: FADDDrr ; case TargetOpcode :: G_FSUB : return AArch64 :: FSUBDrr ; case TargetOpcode :: G_FMUL : return AArch64 :: FMULDrr ; case TargetOpcode :: G_FDIV : return AArch64 :: FDIVDrr ; case TargetOpcode :: G_OR : return AArch64 :: ORRv8i8 ; default : return GenericOpc ; } } break ; } return GenericOpc ; } </s>

Select and emit code for a binary operator instruction , which has an opcode which directly corresponds to the given ISD opcode .