<s> bool AArch64InstrInfo :: isPairableLdStInst ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { default : return false ; case AArch64 :: STRSui : case AArch64 :: STRDui : case AArch64 :: STRQui : case AArch64 :: STRXui : case AArch64 :: STRWui : case AArch64 :: LDRSui : case AArch64 :: LDRDui : case AArch64 :: LDRQui : case AArch64 :: LDRXui : case AArch64 :: LDRWui : case AArch64 :: LDRSWui : case AArch64 :: STURSi : case AArch64 :: STRSpre : case AArch64 :: STURDi : case AArch64 :: STRDpre : case AArch64 :: STURQi : case AArch64 :: STRQpre : case AArch64 :: STURWi : case AArch64 :: STRWpre : case AArch64 :: STURXi : case AArch64 :: STRXpre : case AArch64 :: LDURSi : case AArch64 :: LDRSpre : case AArch64 :: LDURDi : case AArch64 :: LDRDpre : case AArch64 :: LDURQi : case AArch64 :: LDRQpre : case AArch64 :: LDURWi : case AArch64 :: LDRWpre : case AArch64 :: LDURXi : case AArch64 :: LDRXpre : case AArch64 :: LDURSWi : return true ; } } </s>

Return true if pairing the given load or store may be paired with another .


<s> static unsigned s390_loop_unroll_adjust ( unsigned nunroll , struct loop * loop ) { basic_block * bbs ; rtx_insn * insn ; unsigned i ; unsigned mem_count = 0 ; if ( s390_tune < PROCESSOR_2097_Z10 ) return nunroll ; if ( unroll_only_small_loops ) { const unsigned int small_threshold = 12 ; if ( loop -> ninsns > small_threshold ) return 0 ; const unsigned int max_insns = optimize >= 3 ? 36 : 24 ; nunroll = MIN ( nunroll , max_insns / loop -> ninsns ) ; } bbs = get_loop_body ( loop ) ; subrtx_iterator :: array_type array ; for ( i = 0 ; i < loop -> num_nodes ; i ++ ) FOR_BB_INSNS ( bbs [ i ] , insn ) if ( INSN_P ( insn ) && INSN_CODE ( insn ) != - 1 ) { rtx set ; if ( s390_tune >= PROCESSOR_2964_Z13 && loop -> ninsns <= BLOCK_MEM_OPS_LOOP_INSNS && ( ( set = single_set ( insn ) ) != NULL_RTX ) && ( ( GET_MODE ( SET_DEST ( set ) ) == BLKmode && ( GET_MODE ( SET_SRC ( set ) ) == BLKmode || SET_SRC ( set ) == const0_rtx ) ) || ( GET_CODE ( SET_SRC ( set ) ) == COMPARE && GET_MODE ( XEXP ( SET_SRC ( set ) , 0 ) ) == BLKmode && GET_MODE ( XEXP ( SET_SRC ( set ) , 1 ) ) == BLKmode ) ) ) { free ( bbs ) ; return 1 ; } FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , NONCONST ) if ( MEM_P ( * iter ) ) mem_count += 1 ; } free ( bbs ) ; if ( mem_count == 0 ) return nunroll ; switch ( loop_depth ( loop ) ) { case 1 : return MIN ( nunroll , 28 / mem_count ) ; case 2 : return MIN ( nunroll , 22 / mem_count ) ; default : return MIN ( nunroll , 16 / mem_count ) ; } } </s>

This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates a new number struct loop * loop should be unrolled if tuned for cpus with a built-in stride prefetcher . The loop is analyzed for memory accesses by calling check_dpu for each rtx of the loop . Depending on the loop_depth and the amount of memory accesses a new number < =nunroll is returned to improve the behaviour of the hardware prefetch unit .


<s> static rtx gen_safe_HIGH64 ( rtx dest , HOST_WIDE_INT val ) { return gen_rtx_SET ( dest , GEN_INT ( val & ~ ( HOST_WIDE_INT ) 0x3ff ) ) ; } </s>

The optimizer is not to assume anything about exactly which bits are set for a HIGH , they are unspecified . Unfortunately this leads to many missed optimizations during CSE . We mask out the non-HIGH bits , and matches a plain movdi , to alleviate this problem .


"Cannot handle this call frame pseudo instruction"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> void J2FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( hasFP ( MF ) ) SavedRegs . set ( J2 :: R14 ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> void AMDGPUTargetLowering :: AnalyzeReturn ( CCState & State , const SmallVectorImpl < ISD :: OutputArg > & Outs ) const { State . AnalyzeReturn ( Outs , RetCC_SI ) ; } </s>

AnalyzeReturn - Analyze the returned values of a return , incorporating info about the result values into this state .


"Basic block should contain at least a RET but is empty"

runOnMachineFunction - Emit the function body .


<s> bool X86InstrInfo :: analyzeCompare ( const MachineInstr & MI , Register & SrcReg , Register & SrcReg2 , int64_t & CmpMask , int64_t & CmpValue ) const { switch ( MI . getOpcode ( ) ) { default : break ; case X86 :: CMP64ri32 : case X86 :: CMP64ri8 : case X86 :: CMP32ri : case X86 :: CMP32ri8 : case X86 :: CMP16ri : case X86 :: CMP16ri8 : case X86 :: CMP8ri : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; if ( MI . getOperand ( 1 ) . isImm ( ) ) { CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 1 ) . getImm ( ) ; } else { CmpMask = CmpValue = 0 ; } return true ; case X86 :: SUB64rm : case X86 :: SUB32rm : case X86 :: SUB16rm : case X86 :: SUB8rm : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = 0 ; CmpValue = 0 ; return true ; case X86 :: SUB64rr : case X86 :: SUB32rr : case X86 :: SUB16rr : case X86 :: SUB8rr : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 2 ) . getReg ( ) ; CmpMask = 0 ; CmpValue = 0 ; return true ; case X86 :: SUB64ri32 : case X86 :: SUB64ri8 : case X86 :: SUB32ri : case X86 :: SUB32ri8 : case X86 :: SUB16ri : case X86 :: SUB16ri8 : case X86 :: SUB8ri : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; if ( MI . getOperand ( 2 ) . isImm ( ) ) { CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 2 ) . getImm ( ) ; } else { CmpMask = CmpValue = 0 ; } return true ; case X86 :: CMP64rr : case X86 :: CMP32rr : case X86 :: CMP16rr : case X86 :: CMP8rr : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 1 ) . getReg ( ) ; CmpMask = 0 ; CmpValue = 0 ; return true ; case X86 :: TEST8rr : case X86 :: TEST16rr : case X86 :: TEST32rr : case X86 :: TEST64rr : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; if ( MI . getOperand ( 1 ) . getReg ( ) != SrcReg ) return false ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> void TOYInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( TOY :: MOVrr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } </s>


<s> static bool aarch64_vector_data_mode_p ( machine_mode mode ) { return aarch64_classify_vector_mode ( mode ) & VEC_ANY_DATA ; } </s>

Return true if MODE is any of the data vector modes , including structure modes .


<s> void RISCVPassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; addPass ( createRISCVGatherScatterLoweringPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> rtx ix86_find_base_term ( rtx x ) { rtx term ; if ( TARGET_64BIT ) { if ( GET_CODE ( x ) != CONST ) return x ; term = XEXP ( x , 0 ) ; if ( GET_CODE ( term ) == PLUS && ( CONST_INT_P ( XEXP ( term , 1 ) ) || GET_CODE ( XEXP ( term , 1 ) ) == CONST_DOUBLE ) ) term = XEXP ( term , 0 ) ; if ( GET_CODE ( term ) != UNSPEC || ( XINT ( term , 1 ) != UNSPEC_GOTPCREL && XINT ( term , 1 ) != UNSPEC_PCREL ) ) return x ; return XVECEXP ( term , 0 , 0 ) ; } return ix86_delegitimize_address ( x ) ; } </s>

If X is a machine specific address ( i.e . a symbol or label being referenced as a displacement from the GOT implemented using an UNSPEC ) , then return the base term . Otherwise return X .


<s> int aarch_crypto_can_dual_issue ( rtx_insn * producer_insn , rtx_insn * consumer_insn ) { rtx producer_set , consumer_set ; rtx producer_src , consumer_src ; producer_set = single_set ( producer_insn ) ; consumer_set = single_set ( consumer_insn ) ; producer_src = producer_set ? SET_SRC ( producer_set ) : NULL ; consumer_src = consumer_set ? SET_SRC ( consumer_set ) : NULL ; if ( producer_src && consumer_src && GET_CODE ( producer_src ) == UNSPEC && GET_CODE ( consumer_src ) == UNSPEC && ( ( XINT ( producer_src , 1 ) == UNSPEC_AESE && XINT ( consumer_src , 1 ) == UNSPEC_AESMC ) || ( XINT ( producer_src , 1 ) == UNSPEC_AESD && XINT ( consumer_src , 1 ) == UNSPEC_AESIMC ) ) ) { unsigned int regno = REGNO ( SET_DEST ( producer_set ) ) ; return REGNO ( SET_DEST ( consumer_set ) ) == regno && REGNO ( XVECEXP ( consumer_src , 0 , 0 ) ) == regno ; } return 0 ; } </s>

In ARMv8-A there 's a general expectation that AESE/AESMC and AESD/AESIMC sequences of the form : AESE Vn , _ AESMC Vn , Vn will issue both instructions in a single cycle on super-scalar implementations . This function identifies such pairs .


<s> bool isAliased ( const MachineFrameInfo * ) const override { return false ; } </s>

Test whether the memory pointed to by this PseudoSourceValue may also be pointed to by an LLVM IR Value .


Return the union class of CLASS1 and CLASS2 . See the x86-64 PS ABI for details .


<s>
bool
R600VectorRegMerger
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
if
(
skipFunction
(
*
Fn
.
getFunction
(
)
)
)
return
false
;
TII
=
static_cast
<
const
R600InstrInfo
*
>
(
Fn
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
MRI
=
&
(
Fn
.
getRegInfo
(
)
)
;
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
MachineBasicBlock
*
MB
=
&
*
MBB
;
PreviousRegSeq
.
clear
(
)
;
PreviousRegSeqByReg
.
clear
(
)
;
PreviousRegSeqByUndefCount
.
clear
(
)
;
for
(
MachineBasicBlock
::
iterator
MII
=
MB
->
begin
(
)
,
MIIE
=
MB
->
end
(
)
;
MII
!=
MIIE
;
++
MII
)
{
MachineInstr
*
MI
=
MII
;
if
(
MI
->
getOpcode
(
)
!=
AMDGPU
::
REG_SEQUENCE
)
{
if
(
TII
->
get
(
MI
->
getOpcode
(
)
)
.
TSFlags
&
R600_InstFlag
::
TEX_INST
)
{
unsigned
Reg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
for
(
MachineRegisterInfo
::
def_instr_iterator
It
=
MRI
->
def_instr_begin
(
Reg
)
,
E
=
MRI
->
def_instr_end
(
)
;
It
!=
E
;
++
It
)
{
RemoveMI
(
&
(
*
It
)
)
;
}
}
continue
;
}
RegSeqInfo
RSI
(
*
MRI
,
MI
)
;
unsigned
Reg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
if
(
!
areAllUsesSwizzeable
(
Reg
)
)
continue
;
DEBUG
(
dbgs
(
)
<<
"Trying to optimize "
;
MI
->
dump
(
)
;
)
;
RegSeqInfo
CandidateRSI
;
std
::
vector
<
std
::
pair
<
unsigned
,
unsigned
>
>
RemapChan
;
DEBUG
(
dbgs
(
)
<<
"Using common slots...\n"
;
)
;
if
(
tryMergeUsingCommonSlot
(
RSI
,
CandidateRSI
,
RemapChan
)
)
{
RemoveMI
(
CandidateRSI
.
Instr
)
;
MII
=
RebuildVector
(
&
RSI
,
&
CandidateRSI
,
RemapChan
)
;
trackRSI
(
RSI
)
;
continue
;
}
DEBUG
(
dbgs
(
)
<<
"Using free slots...\n"
;
)
;
RemapChan
.
clear
(
)
;
if
(
tryMergeUsingFreeSlot
(
RSI
,
CandidateRSI
,
RemapChan
)
)
{
RemoveMI
(
CandidateRSI
.
Instr
)
;
MII
=
RebuildVector
(
&
RSI
,
&
CandidateRSI
,
RemapChan
)
;
trackRSI
(
RSI
)
;
continue
;
}
trackRSI
(
RSI
)
;
}
}
return
false
;
}
</s>

AMDGPU
R600
R600
AMDGPU::REG_SEQUENCE
R600_InstFlag::TEX_INST
1
SI
0
"Trying to optimize "
SI
"Using common slots...\n"
SI
SI
SI
SI
SI
SI
SI
"Using free slots...\n"
SI
SI
SI
SI
SI
SI
SI
SI
SI


<s>
void
OR1KInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
OR1K
::
GPRRegClass
.
contains
(
DestReg
,
SrcReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
OR1K
::
ORI
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
0
)
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
</s>


<s>
const
char
*
ashlsi3_out
(
rtx_insn
*
insn
,
rtx
operands
[
]
,
int
*
len
)
{
if
(
CONST_INT_P
(
operands
[
2
]
)
)
{
int
k
;
int
*
t
=
len
;
if
(
!
len
)
len
=
&
k
;
switch
(
INTVAL
(
operands
[
2
]
)
)
{
default
:
if
(
INTVAL
(
operands
[
2
]
)
<
32
)
break
;
if
(
AVR_HAVE_MOVW
)
return
*
len
=
3
,
(
"clr %D0"
CR_TAB
"clr %C0"
CR_TAB
"movw %A0,%C0"
)
;
*
len
=
4
;
return
(
"clr %D0"
CR_TAB
"clr %C0"
CR_TAB
"clr %B0"
CR_TAB
"clr %A0"
)
;
case
8
:
{
int
reg0
=
true_regnum
(
operands
[
0
]
)
;
int
reg1
=
true_regnum
(
operands
[
1
]
)
;
*
len
=
4
;
if
(
reg0
>=
reg1
)
return
(
"mov %D0,%C1"
CR_TAB
"mov %C0,%B1"
CR_TAB
"mov %B0,%A1"
CR_TAB
"clr %A0"
)
;
else
return
(
"clr %A0"
CR_TAB
"mov %B0,%A1"
CR_TAB
"mov %C0,%B1"
CR_TAB
"mov %D0,%C1"
)
;
}
case
16
:
{
int
reg0
=
true_regnum
(
operands
[
0
]
)
;
int
reg1
=
true_regnum
(
operands
[
1
]
)
;
if
(
reg0
+
2
==
reg1
)
return
*
len
=
2
,
(
"clr %B0"
CR_TAB
"clr %A0"
)
;
if
(
AVR_HAVE_MOVW
)
return
*
len
=
3
,
(
"movw %C0,%A1"
CR_TAB
"clr %B0"
CR_TAB
"clr %A0"
)
;
else
return
*
len
=
4
,
(
"mov %C0,%A1"
CR_TAB
"mov %D0,%B1"
CR_TAB
"clr %B0"
CR_TAB
"clr %A0"
)
;
}
case
24
:
*
len
=
4
;
return
(
"mov %D0,%A1"
CR_TAB
"clr %C0"
CR_TAB
"clr %B0"
CR_TAB
"clr %A0"
)
;
case
31
:
*
len
=
6
;
return
(
"clr %D0"
CR_TAB
"lsr %A0"
CR_TAB
"ror %D0"
CR_TAB
"clr %C0"
CR_TAB
"clr %B0"
CR_TAB
"clr %A0"
)
;
}
len
=
t
;
}
out_shift_with_cnt
(
"lsl %A0"
CR_TAB
"rol %B0"
CR_TAB
"rol %C0"
CR_TAB
"rol %D0"
,
insn
,
operands
,
len
,
4
)
;
return
""
;
}
</s>


<s> static int fr30_arg_partial_bytes ( cumulative_args_t cum_v , machine_mode mode , tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( named == 0 || * cum >= FR30_NUM_ARG_REGS ) return 0 ; if ( * cum + fr30_num_arg_regs ( mode , type ) <= FR30_NUM_ARG_REGS ) return 0 ; return ( FR30_NUM_ARG_REGS - * cum ) * UNITS_PER_WORD ; } </s>

Returns the number of bytes in which * part * of a parameter of machine mode MODE and tree type TYPE ( which may be NULL if the type is not known ) . If the argument fits entirely in the argument registers , or entirely on the stack , then 0 is returned . CUM is the number of argument registers already used by earlier parameters to the function .


<s>
MachineBasicBlock
::
iterator
AVRFrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
)
const
{
const
AVRSubtarget
&
STI
=
MF
.
getSubtarget
<
AVRSubtarget
>
(
)
;
const
AVRInstrInfo
&
TII
=
*
STI
.
getInstrInfo
(
)
;
if
(
hasReservedCallFrame
(
MF
)
)
{
fixStackStores
(
MBB
,
MI
,
TII
,
false
)
;
return
MBB
.
erase
(
MI
)
;
}
DebugLoc
DL
=
MI
->
getDebugLoc
(
)
;
unsigned
int
Opcode
=
MI
->
getOpcode
(
)
;
int
Amount
=
TII
.
getFrameSize
(
*
MI
)
;
if
(
Amount
!=
0
)
{
assert
(
TFI
.
getStackAlignment
(
)
==
1
&&
"Unsupported stack alignment"
)
;
if
(
Opcode
==
TII
.
getCallFrameSetupOpcode
(
)
)
{
fixStackStores
(
MBB
,
MI
,
TII
,
true
)
;
}
else
{
assert
(
Opcode
==
TII
.
getCallFrameDestroyOpcode
(
)
)
;
unsigned
addOpcode
;
if
(
isUInt
<
6
>
(
Amount
)
)
{
addOpcode
=
AVR
::
ADIWRdK
;
}
else
{
addOpcode
=
AVR
::
SUBIWRdK
;
Amount
=
Amount
;
}
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
SPREAD
)
,
AVR
::
R31R30
)
.
addReg
(
AVR
::
SP
)
;
MachineInstr
*
New
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
addOpcode
)
,
AVR
::
R31R30
)
.
addReg
(
AVR
::
R31R30
,
RegState
::
Kill
)
.
addImm
(
Amount
)
;
New
->
getOperand
(
3
)
.
setIsDead
(
)
;
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
SPWRITE
)
,
AVR
::
SP
)
.
addReg
(
AVR
::
R31R30
,
RegState
::
Kill
)
;
}
}
return
MBB
.
erase
(
MI
)
;
}
</s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"CHERI range checker"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> T pop_front ( ) { T V = Queue . front ( ) ; Queue . pop ( ) ; Set . erase ( V ) ; return V ; } </s>

Remove the node at the front ; never deletes .


<s> rtx cris_return_addr_rtx ( int count , rtx frameaddr ATTRIBUTE_UNUSED ) { cfun -> machine -> needs_return_address_on_stack = 1 ; return count == 0 ? gen_rtx_MEM ( Pmode , plus_constant ( virtual_incoming_args_rtx , - 4 ) ) : NULL_RTX ; } </s>

The RETURN_ADDR_RTX worker . We mark that the return address is used , either by EH or __builtin_return_address , for use by the function prologue and epilogue . FIXME : This is n't optimal ; we just use the mark in the prologue and epilogue to say that the return address is to be stored in the stack frame . We could return SRP for leaf-functions and use the initial-value machinery .


<s> bool MSP430PassConfig :: addInstSelector ( ) { PM . add ( createMSP430ISelDag ( getMSP430TargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s>
void
R600SchedStrategy
::
releaseTopNode
(
SUnit
*
SU
)
{
int
IK
=
getInstKind
(
SU
)
;
DEBUG
(
dbgs
(
)
<<
IK
<<
" <= "
)
;
DEBUG
(
SU
->
dump
(
DAG
)
)
;
Pending
[
IK
]
->
push
(
SU
)
;
}
</s>

SU has had all predecessor dependencies resolved .


<s> static bool nvptx_function_value_regno_p ( const unsigned int regno ) { return regno == NVPTX_RETURN_REGNUM ; } </s>


<s> static bool ignore_vlmul_insn_p ( rtx_insn * rinsn ) { return get_attr_type ( rinsn ) == TYPE_VIMOVVX || get_attr_type ( rinsn ) == TYPE_VFMOVVF || get_attr_type ( rinsn ) == TYPE_VIMOVXV || get_attr_type ( rinsn ) == TYPE_VFMOVFV ; } </s>

Return true if the instruction ignores VLMUL field of VTYPE .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> TargetPassConfig * TPCTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new TPCPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> static bool sh_lra_p ( void ) { return sh_lra_flag ; } </s>

Return true if we use LRA instead of reload pass .


<s> type_suffix_index function_resolver :: infer_tuple_type ( unsigned int argno ) { return infer_vector_or_tuple_type ( argno , vectors_per_tuple ( ) ) ; } </s>

If the function operates on tuples of vectors , require argument ARGNO to be a tuple with the appropriate number of vectors , otherwise require it to be a single vector . Return the associated type suffix on success , using TYPE_SUFFIX_b for predicates . Report an error and return NUM_TYPE_SUFFIXES on failure .


<s> DecodeStatus HexagonDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & os , raw_ostream & cs ) const { DecodeStatus Result = DecodeStatus :: Success ; bool Complete = false ; Size = 0 ; * CurrentBundle = & MI ; MI = HexagonMCInstrInfo :: createBundle ( ) ; while ( Result == Success && Complete == false ) { if ( Bytes . size ( ) < HEXAGON_INSTR_SIZE ) return MCDisassembler :: Fail ; MCInst * Inst = new ( getContext ( ) ) MCInst ; Result = getSingleInstruction ( * Inst , MI , Bytes , Address , os , cs , Complete ) ; MI . addOperand ( MCOperand :: createInst ( Inst ) ) ; Size += HEXAGON_INSTR_SIZE ; Bytes = Bytes . slice ( HEXAGON_INSTR_SIZE ) ; } if ( Result == MCDisassembler :: Fail ) return Result ; HexagonMCChecker Checker ( * MCII , STI , MI , MI , * getContext ( ) . getRegisterInfo ( ) ) ; if ( ! Checker . check ( ) ) return MCDisassembler :: Fail ; return MCDisassembler :: Success ; } </s>

Returns the disassembly of a single instruction .


<s> bool AArch64AsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const { return int64_t ( Value ) != int64_t ( int8_t ( Value ) ) ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> unsigned X86InstrInfo :: isStoreToStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { unsigned Dummy ; if ( isFrameStoreOpcode ( MI . getOpcode ( ) , Dummy ) ) { unsigned Reg ; if ( ( Reg = isStoreToStackSlot ( MI , FrameIndex ) ) ) return Reg ; SmallVector < const MachineMemOperand * , 1 > Accesses ; if ( hasStoreToStackSlot ( MI , Accesses ) ) { FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) -> getFrameIndex ( ) ; return MI . getOperand ( X86 :: AddrNumOperands ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s> void ARMPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createMVEVPTOptimisationsPass ( ) ) ; addPass ( createMLxExpansionPass ( ) ) ; if ( EnableARMLoadStoreOpt ) addPass ( createARMLoadStoreOptimizationPass ( true ) ) ; if ( ! DisableA15SDOptimization ) addPass ( createA15SDOptimizerPass ( ) ) ; } } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> void s390_output_pool_entry ( rtx exp , enum machine_mode mode , unsigned int align ) { REAL_VALUE_TYPE r ; switch ( GET_MODE_CLASS ( mode ) ) { case MODE_FLOAT : gcc_assert ( GET_CODE ( exp ) == CONST_DOUBLE ) ; REAL_VALUE_FROM_CONST_DOUBLE ( r , exp ) ; assemble_real ( r , mode , align ) ; break ; case MODE_INT : assemble_integer ( exp , GET_MODE_SIZE ( mode ) , align , 1 ) ; break ; default : gcc_unreachable ( ) ; } } </s>

Output the constant pool entry EXP in mode MODE with alignment ALIGN .


<s> bool isLegalMaskedStore ( Type * DataTy ) { return isLegalMaskedLoad ( DataTy ) ; } </s>

Return true if the target supports masked store .


<s> void Mips16FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( 0 ) . getImm ( ) ; if ( I -> getOpcode ( ) == Mips :: ADJCALLSTACKDOWN ) Amount = - Amount ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; TII . adjustStackPtr ( Mips :: SP , Amount , MBB , I ) ; } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

Mips Mips 0 Mips::ADJCALLSTACKDOWN Mips Mips Mips::SP


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { MF . getProperties ( ) . set ( MachineFunctionProperties :: Property :: FailsVerification ) ; TII = MF . getSubtarget < R600Subtarget > ( ) . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; LLVM_DEBUG ( MF . dump ( ) ; ) ; OrderedBlks . clear ( ) ; Visited . clear ( ) ; FuncRep = & MF ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; LLVM_DEBUG ( dbgs ( ) << "LoopInfo:\n" ; PrintLoopinfo ( * MLI ) ; ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; LLVM_DEBUG ( MDT -> print ( dbgs ( ) , ( const Module * ) nullptr ) ; ) ; PDT = & getAnalysis < MachinePostDominatorTree > ( ) ; LLVM_DEBUG ( PDT -> print ( dbgs ( ) ) ; ) ; prepare ( ) ; run ( ) ; LLVM_DEBUG ( MF . dump ( ) ; ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s>
void
final_prescan_insn
(
rtx
insn
,
rtx
*
operand
ATTRIBUTE_UNUSED
,
int
num_operands
ATTRIBUTE_UNUSED
)
{
static
int
last_insn_address
=
0
;
const
int
uid
=
INSN_UID
(
insn
)
;
if
(
TARGET_ADDRESSES
)
{
fprintf
(
asm_out_file
,
"; 0x%x %d\n"
,
INSN_ADDRESSES
(
uid
)
,
INSN_ADDRESSES
(
uid
)
last_insn_address
)
;
last_insn_address
=
INSN_ADDRESSES
(
uid
)
;
}
}
</s>

If defined , a C statement to be executed just prior to the output of assembler code for INSN , to modify the extracted operands so they will be output differently . Here the argument OPVEC is the vector containing the operands extracted from INSN , and NOPERANDS is the number of elements of the vector which contain meaningful data for this insn . The contents of this vector are what will be used to convert the insn template into assembler code , so you can change the assembler output by changing the contents of the vector . We use it to check if the current insn needs a nop in front of it because of load delays , and also to update the delay slot statistics .


"_reflect function should not have a body"

"_reflect's return type should be integer"

"Only a call instruction can use _reflect"

"Only one operand expect for _reflect function"

"Format of _reflect function not recognized"

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> bool BPFTargetLowering :: isTruncateFree ( EVT VT1 , EVT VT2 ) const { if ( ! VT1 . isInteger ( ) || ! VT2 . isInteger ( ) ) return false ; unsigned NumBits1 = VT1 . getSizeInBits ( ) ; unsigned NumBits2 = VT2 . getSizeInBits ( ) ; return NumBits1 > NumBits2 ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s>
void
Z80oldTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
LLVM_DEBUG
(
dbgs
(
)
<<
"ReplaceNodeResults: "
;
N
->
dump
(
&
DAG
)
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s>
void
X86FrameLowering
::
inlineStackProbe
(
MachineFunction
&
MF
,
MachineBasicBlock
&
PrologMBB
)
const
{
const
StringRef
ChkStkStubSymbol
=
"__chkstk_stub"
;
MachineInstr
*
ChkStkStub
=
nullptr
;
for
(
MachineInstr
&
MI
:
PrologMBB
)
{
if
(
MI
.
isCall
(
)
&&
MI
.
getOperand
(
0
)
.
isSymbol
(
)
&&
ChkStkStubSymbol
==
MI
.
getOperand
(
0
)
.
getSymbolName
(
)
)
{
ChkStkStub
=
&
MI
;
break
;
}
}
if
(
ChkStkStub
!=
nullptr
)
{
MachineBasicBlock
::
iterator
MBBI
=
std
::
next
(
ChkStkStub
->
getIterator
(
)
)
;
assert
(
std
::
prev
(
MBBI
)
.
operator
==
(
ChkStkStub
)
&&
"MBBI expected after __chkstk_stub."
)
;
DebugLoc
DL
=
PrologMBB
.
findDebugLoc
(
MBBI
)
;
emitStackProbeInline
(
MF
,
PrologMBB
,
MBBI
,
DL
,
true
)
;
ChkStkStub
->
eraseFromParent
(
)
;
}
}
</s>

Replace a StackProbe inline-stub with the actual probe code inline .


<s> virtual EVT getSetCCResultType ( EVT VT ) const { if ( VT . isVector ( ) ) return MVT :: getVectorVT ( MVT :: i1 , VT . getVectorNumElements ( ) ) ; return MVT :: i1 ; } </s>

Return the value type to use for ISD : :SETCC .


<s> bool M68kOperand :: isToken ( ) const { return Kind == Kind :: Token ; } </s>


<s> bool AMDGPUPromoteAllocaToVector :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) || DisablePromoteAllocaToVector ) return false ; const TargetMachine * TM ; if ( auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ) TM = & TPC -> getTM < TargetMachine > ( ) ; else return false ; const AMDGPUSubtarget & ST = AMDGPUSubtarget :: get ( * TM , F ) ; if ( ! ST . isPromoteAllocaEnabled ( ) ) return false ; if ( TM -> getTargetTriple ( ) . getArch ( ) == Triple :: amdgcn ) { const GCNSubtarget & ST = TM -> getSubtarget < GCNSubtarget > ( F ) ; MaxVGPRs = ST . getMaxNumVGPRs ( ST . getWavesPerEU ( F ) . first ) ; } else { MaxVGPRs = 128 ; } bool Changed = false ; BasicBlock & EntryBB = * F . begin ( ) ; SmallVector < AllocaInst * , 16 > Allocas ; for ( Instruction & I : EntryBB ) { if ( AllocaInst * AI = dyn_cast < AllocaInst > ( & I ) ) Allocas . push_back ( AI ) ; } for ( AllocaInst * AI : Allocas ) { if ( handleAlloca ( * AI ) ) Changed = true ; } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static void block_move_call ( rtx dest_reg , rtx src_reg , rtx bytes_rtx ) { if ( GET_MODE ( bytes_rtx ) != VOIDmode && GET_MODE ( bytes_rtx ) != Pmode ) bytes_rtx = convert_to_mode ( Pmode , bytes_rtx , 1 ) ; emit_library_call ( m32r_function_symbol ( "memcpy" ) , LCT_NORMAL , VOIDmode , dest_reg , Pmode , src_reg , Pmode , convert_to_mode ( TYPE_MODE ( sizetype ) , bytes_rtx , TYPE_UNSIGNED ( sizetype ) ) , TYPE_MODE ( sizetype ) ) ; } </s>

Use a library function to move some bytes .


<s> unsigned BlackfinRegisterInfo :: getRARegister ( ) const { return BF :: RETS ; } </s>

This method should return the register where the return address can be found .


<s> virtual unsigned int execute ( function * ) { return rest_of_insert_bti ( ) ; } </s>


<s> unsigned AMDGPURegisterBankInfo :: copyCost ( const RegisterBank & Dst , const RegisterBank & Src , unsigned Size ) const { if ( Dst . getID ( ) == AMDGPU :: SGPRRegBankID && Src . getID ( ) == AMDGPU :: VGPRRegBankID ) return std :: numeric_limits < unsigned > :: max ( ) ; if ( Size == 1 && Dst . getID ( ) == AMDGPU :: SCCRegBankID && Src . getID ( ) == AMDGPU :: SGPRRegBankID ) return std :: numeric_limits < unsigned > :: max ( ) ; return RegisterBankInfo :: copyCost ( Dst , Src , Size ) ; } </s>

Get the cost of a copy from B to A , or put differently , get the cost of A = COPY B .

AMDGPU AMDGPU AMDGPU::SGPRRegBankID AMDGPU::VGPRRegBankID 1 AMDGPU::SCCRegBankID AMDGPU::SGPRRegBankID


<s> enum reg_class mcore_secondary_reload_class ( enum reg_class class , enum machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { if ( TEST_HARD_REG_BIT ( reg_class_contents [ class ] , 15 ) && ! mcore_r15_operand_p ( x ) ) return LRW_REGS ; return NO_REGS ; } </s>

Implement SECONDARY_RELOAD_CLASS . If CLASS contains r15 , and we ca n't directly move X into it , use r1-r14 as a temporary .


<s> bool isMem ( ) const override { return false ; } </s>


<s>
void
M680x0InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
assert
(
MF
.
getFrameInfo
(
)
.
getObjectSize
(
FrameIndex
)
==
4
&&
"Stack slot too small for store"
)
;
unsigned
Opc
=
getStoreRegOpcode
(
SrcReg
,
RC
,
TRI
,
Subtarget
)
;
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
)
,
FrameIndex
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool SIRegisterInfo :: needsFrameBaseReg ( MachineInstr * MI , int64_t Offset ) const { if ( ! MI -> mayLoadOrStore ( ) ) return false ; int64_t FullOffset = Offset + getScratchInstrOffset ( MI ) ; if ( SIInstrInfo :: isMUBUF ( * MI ) ) return ! SIInstrInfo :: isLegalMUBUFImmOffset ( FullOffset ) ; const SIInstrInfo * TII = ST . getInstrInfo ( ) ; return ! TII -> isLegalFLATOffset ( FullOffset , AMDGPUAS :: PRIVATE_ADDRESS , true ) ; } </s>

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s> void function_builder :: add_overloaded_function ( const function_instance & instance , uint64_t required_extensions ) { char * name = get_name ( instance , true ) ; if ( registered_function * * map_value = m_overload_names . get ( name ) ) { gcc_assert ( ( * map_value ) -> instance == instance && ( ( * map_value ) -> required_extensions & ~ required_extensions ) == 0 ) ; obstack_free ( & m_string_obstack , name ) ; } else { registered_function & rfn = add_function ( instance , name , m_overload_type , NULL_TREE , required_extensions , true , m_direct_overloads ) ; m_overload_names . put ( name , & rfn ) ; } } </s>

Add one function decl for INSTANCE , to be used with manual overload resolution . REQUIRED_EXTENSIONS are the set of architecture extensions that the function requires . For simplicity , deal with duplicate attempts to add the same function , including cases in which the new function requires more features than the original one did . In that case we 'll check whether the required features are available as part of resolving the function to the relevant unique function .


<s> unsigned HSAILInstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr * MI , int & FrameIndex ) const { return isLoadFromStackSlot ( MI , FrameIndex ) ; } </s>

isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s>
StringRef
getPassName
(
)
const
override
{
return
"DLX Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> const TeakRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
MachineBasicBlock
::
iterator
AVRFrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
)
const
{
const
AVRSubtarget
&
STI
=
MF
.
getSubtarget
<
AVRSubtarget
>
(
)
;
const
AVRInstrInfo
&
TII
=
*
STI
.
getInstrInfo
(
)
;
if
(
hasReservedCallFrame
(
MF
)
)
{
fixStackStores
(
MBB
,
MI
,
TII
,
false
)
;
return
MBB
.
erase
(
MI
)
;
}
DebugLoc
DL
=
MI
->
getDebugLoc
(
)
;
unsigned
int
Opcode
=
MI
->
getOpcode
(
)
;
int
Amount
=
TII
.
getFrameSize
(
*
MI
)
;
if
(
Amount
!=
0
)
{
assert
(
getStackAlign
(
)
==
Align
(
1
)
&&
"Unsupported stack alignment"
)
;
if
(
Opcode
==
TII
.
getCallFrameSetupOpcode
(
)
)
{
fixStackStores
(
MBB
,
MI
,
TII
,
true
)
;
}
else
{
assert
(
Opcode
==
TII
.
getCallFrameDestroyOpcode
(
)
)
;
unsigned
addOpcode
;
if
(
isUInt
<
6
>
(
Amount
)
)
{
addOpcode
=
AVR
::
ADIWRdK
;
}
else
{
addOpcode
=
AVR
::
SUBIWRdK
;
Amount
=
Amount
;
}
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
SPREAD
)
,
AVR
::
R31R30
)
.
addReg
(
AVR
::
SP
)
;
MachineInstr
*
New
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
addOpcode
)
,
AVR
::
R31R30
)
.
addReg
(
AVR
::
R31R30
,
RegState
::
Kill
)
.
addImm
(
Amount
)
;
New
->
getOperand
(
3
)
.
setIsDead
(
)
;
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
SPWRITE
)
,
AVR
::
SP
)
.
addReg
(
AVR
::
R31R30
,
RegState
::
Kill
)
;
}
}
return
MBB
.
erase
(
MI
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static rtx emit_multi_reg_push ( unsigned long mask ) { int num_regs = 0 ; int num_dwarf_regs ; int i , j ; rtx par ; rtx dwarf ; int dwarf_par_index ; rtx tmp , reg ; for ( i = 0 ; i <= LAST_ARM_REGNUM ; i ++ ) if ( mask & ( 1 << i ) ) num_regs ++ ; gcc_assert ( num_regs && num_regs <= 16 ) ; num_dwarf_regs = num_regs ; if ( mask & ( 1 << PC_REGNUM ) ) num_dwarf_regs -- ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs ) ) ; dwarf = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( num_dwarf_regs + 1 ) ) ; dwarf_par_index = 1 ; for ( i = 0 ; i <= LAST_ARM_REGNUM ; i ++ ) { if ( mask & ( 1 << i ) ) { reg = gen_rtx_REG ( SImode , i ) ; XVECEXP ( par , 0 , 0 ) = gen_rtx_SET ( VOIDmode , gen_frame_mem ( BLKmode , gen_rtx_PRE_DEC ( BLKmode , stack_pointer_rtx ) ) , gen_rtx_UNSPEC ( BLKmode , gen_rtvec ( 1 , reg ) , UNSPEC_PUSH_MULT ) ) ; if ( i != PC_REGNUM ) { tmp = gen_rtx_SET ( VOIDmode , gen_frame_mem ( SImode , stack_pointer_rtx ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , dwarf_par_index ) = tmp ; dwarf_par_index ++ ; } break ; } } for ( j = 1 , i ++ ; j < num_regs ; i ++ ) { if ( mask & ( 1 << i ) ) { reg = gen_rtx_REG ( SImode , i ) ; XVECEXP ( par , 0 , j ) = gen_rtx_USE ( VOIDmode , reg ) ; if ( i != PC_REGNUM ) { tmp = gen_rtx_SET ( VOIDmode , gen_frame_mem ( SImode , plus_constant ( stack_pointer_rtx , 4 * j ) ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , dwarf_par_index ++ ) = tmp ; } j ++ ; } } par = emit_insn ( par ) ; tmp = gen_rtx_SET ( SImode , stack_pointer_rtx , gen_rtx_PLUS ( SImode , stack_pointer_rtx , GEN_INT ( - 4 * num_regs ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , 0 ) = tmp ; REG_NOTES ( par ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , dwarf , REG_NOTES ( par ) ) ; return par ; } </s>

Generate and emit an insn that we will recognize as a push_multi . Unfortunately , since this insn does not reflect very well the actual semantics of the operation , we need to annotate the insn for the benefit of DWARF2 frame unwind information .


"Relocation required in an instruction that we cannot encode!"

getMachineOpValue - Return binary encoding of operand .


<s> bool hasModifiers ( ) const { return getModifiers ( ) . hasModifiers ( ) ; } </s>

Return true if this instruction has any modifiers .


<s>
SDValue
SystemZTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
DL
,
SelectionDAG
&
DAG
)
const
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
SmallVector
<
CCValAssign
,
16
>
RetLocs
;
CCState
RetCCInfo
(
CallConv
,
IsVarArg
,
MF
,
DAG
.
getTarget
(
)
,
RetLocs
,
*
DAG
.
getContext
(
)
)
;
RetCCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_SystemZ
)
;
if
(
RetLocs
.
empty
(
)
)
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
Chain
)
;
SDValue
Glue
;
SmallVector
<
SDValue
,
4
>
RetOps
;
RetOps
.
push_back
(
Chain
)
;
for
(
unsigned
I
=
0
,
E
=
RetLocs
.
size
(
)
;
I
!=
E
;
++
I
)
{
CCValAssign
&
VA
=
RetLocs
[
I
]
;
SDValue
RetValue
=
OutVals
[
I
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
RetValue
=
convertValVTToLocVT
(
DAG
,
DL
,
VA
,
RetValue
)
;
unsigned
Reg
=
VA
.
getLocReg
(
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
Reg
,
RetValue
,
Glue
)
;
Glue
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
Reg
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Glue
.
getNode
(
)
)
RetOps
.
push_back
(
Glue
)
;
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool ix86_hard_regno_mode_ok ( int regno , enum machine_mode mode ) { if ( CC_REGNO_P ( regno ) ) return GET_MODE_CLASS ( mode ) == MODE_CC ; if ( GET_MODE_CLASS ( mode ) == MODE_CC || GET_MODE_CLASS ( mode ) == MODE_RANDOM || GET_MODE_CLASS ( mode ) == MODE_PARTIAL_INT ) return 0 ; if ( FP_REGNO_P ( regno ) ) return VALID_FP_MODE_P ( mode ) ; if ( SSE_REGNO_P ( regno ) ) { return ( VALID_SSE_REG_MODE ( mode ) || VALID_SSE2_REG_MODE ( mode ) || VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( MMX_REGNO_P ( regno ) ) { return ( VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( mode == QImode ) { if ( regno < 4 || TARGET_64BIT ) return 1 ; if ( ! TARGET_PARTIAL_REG_STALL ) return 1 ; return reload_in_progress || reload_completed ; } else if ( VALID_INT_MODE_P ( mode ) ) return 1 ; else if ( VALID_FP_MODE_P ( mode ) ) return 1 ; else if ( VALID_MMX_REG_MODE_3DNOW ( mode ) || VALID_MMX_REG_MODE ( mode ) ) return 1 ; return 0 ; } </s>

Return TRUE if hard register REGNO can hold a value of machine-mode MODE .


<s> static void sh_print_operand_address ( FILE * stream , rtx x ) { switch ( GET_CODE ( x ) ) { case REG : case SUBREG : fprintf ( stream , "@%s" , reg_names [ true_regnum ( x ) ] ) ; break ; case PLUS : { rtx base = XEXP ( x , 0 ) ; rtx index = XEXP ( x , 1 ) ; switch ( GET_CODE ( index ) ) { case CONST_INT : fprintf ( stream , "@(%d,%s)" , ( int ) INTVAL ( index ) , reg_names [ true_regnum ( base ) ] ) ; break ; case REG : case SUBREG : { int base_num = true_regnum ( base ) ; int index_num = true_regnum ( index ) ; fprintf ( stream , "@(r0,%s)" , reg_names [ MAX ( base_num , index_num ) ] ) ; break ; } default : gcc_unreachable ( ) ; } } break ; case PRE_DEC : fprintf ( stream , "@-%s" , reg_names [ true_regnum ( XEXP ( x , 0 ) ) ] ) ; break ; case POST_INC : fprintf ( stream , "@%s+" , reg_names [ true_regnum ( XEXP ( x , 0 ) ) ] ) ; break ; default : x = mark_constant_pool_use ( x ) ; output_addr_const ( stream , x ) ; break ; } } </s>

Print the operand address in x to the stream .


<s> static void tilepro_init_builtins ( void ) { size_t i ; for ( i = 0 ; i < ARRAY_SIZE ( tilepro_builtins ) ; i ++ ) { const struct tilepro_builtin_def * p = & tilepro_builtins [ i ] ; tree ftype , ret_type , arg_type_list = void_list_node ; tree decl ; int j ; for ( j = strlen ( p -> type ) - 1 ; j > 0 ; j -- ) { arg_type_list = tree_cons ( NULL_TREE , char_to_type ( p -> type [ j ] ) , arg_type_list ) ; } ret_type = char_to_type ( p -> type [ 0 ] ) ; ftype = build_function_type ( ret_type , arg_type_list ) ; decl = add_builtin_function ( p -> name , ftype , p -> code , BUILT_IN_MD , NULL , NULL ) ; if ( p -> is_const ) TREE_READONLY ( decl ) = 1 ; TREE_NOTHROW ( decl ) = 1 ; if ( tilepro_builtin_info [ p -> code ] . fndecl == NULL ) tilepro_builtin_info [ p -> code ] . fndecl = decl ; } } </s>


<s> bool NyuziPassConfig :: addInstSelector ( ) { addPass ( createNyuziISelDag ( getNyuziTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> Register getFramePtr ( ) const { return FramePtr ; } </s>

Returns physical register used as frame pointer .


<s>
void
X86InstPrinterCommon
::
printPCRelImm
(
const
MCInst
*
MI
,
uint64_t
Address
,
unsigned
OpNo
,
raw_ostream
&
O
)
{
if
(
SymbolizeOperands
)
return
;
const
MCOperand
&
Op
=
MI
->
getOperand
(
OpNo
)
;
if
(
Op
.
isImm
(
)
)
{
if
(
PrintBranchImmAsAddress
)
{
uint64_t
Target
=
Address
+
Op
.
getImm
(
)
;
if
(
MAI
.
getCodePointerSize
(
)
==
4
)
Target
&=
0xffffffff
;
O
<<
formatHex
(
Target
)
;
}
else
O
<<
formatImm
(
Op
.
getImm
(
)
)
;
}
else
{
assert
(
Op
.
isExpr
(
)
&&
"unknown pcrel immediate operand"
)
;
const
MCConstantExpr
*
BranchTarget
=
dyn_cast
<
MCConstantExpr
>
(
Op
.
getExpr
(
)
)
;
int64_t
Address
;
if
(
BranchTarget
&&
BranchTarget
->
evaluateAsAbsolute
(
Address
)
)
{
O
<<
formatHex
(
(
uint64_t
)
Address
)
;
}
else
{
Op
.
getExpr
(
)
->
print
(
O
,
&
MAI
)
;
}
}
}
</s>


<s> static rtx find_ltrel_base ( rtx x ) { int i , j ; const char * fmt ; if ( GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNSPEC_LTREL_BASE ) return XVECEXP ( x , 0 , 0 ) ; fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'e' ) { rtx fnd = find_ltrel_base ( XEXP ( x , i ) ) ; if ( fnd ) return fnd ; } else if ( fmt [ i ] == 'E' ) { for ( j = 0 ; j < XVECLEN ( x , i ) ; j ++ ) { rtx fnd = find_ltrel_base ( XVECEXP ( x , i , j ) ) ; if ( fnd ) return fnd ; } } } return NULL_RTX ; } </s>

Check whether X contains an UNSPEC_LTREL_BASE . Return its constant pool symbol if found , NULL_RTX otherwise .


<s>
void
WebAssemblyInstPrinter
::
printRegName
(
raw_ostream
&
OS
,
unsigned
RegNo
)
const
{
llvm_unreachable
(
"TODO: implement printRegName"
)
;
}
</s>

WebAssembly
WebAssembly
"TODO: implement printRegName"


<s> bool Z80oldInstrInfo :: isUnpredicatedTerminator ( const MachineInstr & MI ) const { if ( ! MI . isTerminator ( ) ) { return false ; } if ( MI . isBranch ( ) && ! MI . isBarrier ( ) ) { return true ; } if ( ! MI . isPredicable ( ) ) { return true ; } return ! isPredicated ( MI ) ; } </s>

Returns true if the instruction is a terminator instruction that has not been predicated .


<s> SDValue LEGTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InGlue , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { assert ( ! isVarArg && "Unsupported" ) ; SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_LEG ) ; for ( auto & Loc : RVLocs ) { Chain = DAG . getCopyFromReg ( Chain , dl , Loc . getLocReg ( ) , Loc . getValVT ( ) , InGlue ) . getValue ( 1 ) ; InGlue = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s>
void
SIInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
DestReg
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
SIMachineFunctionInfo
*
MFI
=
MBB
.
getParent
(
)
->
getInfo
<
SIMachineFunctionInfo
>
(
)
;
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
if
(
TRI
->
getCommonSubClass
(
RC
,
&
AMDGPU
::
SReg_32RegClass
)
)
{
SIMachineFunctionInfo
::
SpilledReg
Spill
=
MFI
->
SpillTracker
.
getSpilledReg
(
FrameIndex
)
;
assert
(
Spill
.
VGPR
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
AMDGPU
::
V_READLANE_B32
)
,
DestReg
)
.
addReg
(
Spill
.
VGPR
)
.
addImm
(
Spill
.
Lane
)
;
insertNOPs
(
MI
,
3
)
;
}
else
if
(
RI
.
isSGPRClass
(
RC
)
)
{
unsigned
Opcode
;
switch
(
RC
->
getSize
(
)
*
8
)
{
case
64
:
Opcode
=
AMDGPU
::
SI_SPILL_S64_RESTORE
;
break
;
case
128
:
Opcode
=
AMDGPU
::
SI_SPILL_S128_RESTORE
;
break
;
case
256
:
Opcode
=
AMDGPU
::
SI_SPILL_S256_RESTORE
;
break
;
case
512
:
Opcode
=
AMDGPU
::
SI_SPILL_S512_RESTORE
;
break
;
default
:
llvm_unreachable
(
"Cannot spill register class"
)
;
}
SIMachineFunctionInfo
::
SpilledReg
Spill
=
MFI
->
SpillTracker
.
getSpilledReg
(
FrameIndex
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opcode
)
,
DestReg
)
.
addReg
(
Spill
.
VGPR
)
.
addImm
(
FrameIndex
)
;
insertNOPs
(
MI
,
3
)
;
}
else
{
llvm_unreachable
(
"VGPR spilling not supported"
)
;
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> int arith_operand ( rtx op , enum machine_mode mode ) { return ( register_operand ( op , mode ) || GET_CODE ( op ) == CONST_INT ) ; } </s>

Return true if OP is a register , or is a CONST_INT that can fit in a signed 13 bit immediate field . This is an acceptable SImode operand for most 3 address instructions .


<s> static rtx ix86_gen_TWO52 ( machine_mode mode ) { const struct real_format * fmt ; REAL_VALUE_TYPE TWO52r ; rtx TWO52 ; fmt = REAL_MODE_FORMAT ( mode ) ; real_2expN ( & TWO52r , fmt -> p - 1 , mode ) ; TWO52 = const_double_from_real_value ( TWO52r , mode ) ; TWO52 = force_reg ( mode , TWO52 ) ; return TWO52 ; } </s>

Generate and return a rtx of mode MODE for 2 * * n where n is the number of bits of the mantissa of MODE , which must be one of DFmode or SFmode .


<s> static void mips_sim_wait_insn ( struct mips_sim * state , rtx insn ) { mips_sim_wait_regs ( state , insn ) ; mips_sim_wait_units ( state , insn ) ; } </s>

Advance simulation state STATE until INSN is ready to issue .


<s>
void
ARMBaseInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
DebugLoc
::
getUnknownLoc
(
)
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
if
(
RC
==
ARM
::
GPRRegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
STR
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addReg
(
0
)
.
addImm
(
0
)
)
;
}
else
if
(
RC
==
ARM
::
DPRRegisterClass
||
RC
==
ARM
::
DPR_VFP2RegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
FSTD
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
)
;
}
else
if
(
RC
==
ARM
::
SPRRegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
FSTS
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
)
;
}
else
{
assert
(
RC
==
ARM
::
QPRRegisterClass
&&
"Unknown regclass!"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
VSTRQ
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> SDValue SparcTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { if ( Subtarget -> is64Bit ( ) ) return LowerFormalArguments_64 ( Chain , CallConv , IsVarArg , Ins , DL , DAG , InVals ) ; return LowerFormalArguments_32 ( Chain , CallConv , IsVarArg , Ins , DL , DAG , InVals ) ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> void PTXInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printPredicate ( MI , O ) ; switch ( MI -> getOpcode ( ) ) { default : printInstruction ( MI , O ) ; break ; case PTX :: CALL : printCall ( MI , O ) ; } O << ";" ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s>
MachineBasicBlock
*
XCoreTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
const
TargetInstrInfo
&
TII
=
*
getTargetMachine
(
)
.
getInstrInfo
(
)
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
assert
(
(
MI
->
getOpcode
(
)
==
XCore
::
SELECT_CC
)
&&
"Unexpected instr type to insert"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
It
=
BB
;
++
It
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
sinkMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
XCore
::
BRFT_lru6
)
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
sinkMBB
)
;
F
->
insert
(
It
,
copy0MBB
)
;
F
->
insert
(
It
,
sinkMBB
)
;
sinkMBB
->
transferSuccessors
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
sinkMBB
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
XCore
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
3
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
F
->
DeleteMachineInstr
(
MI
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> void rs6000_split_atomic_op ( enum rtx_code code , rtx mem , rtx val , rtx before , rtx after , rtx scratch ) { enum machine_mode mode = GET_MODE ( mem ) ; rtx label , x , cond = gen_rtx_REG ( CCmode , CR0_REGNO ) ; emit_insn ( gen_memory_barrier ( ) ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; label = gen_rtx_LABEL_REF ( VOIDmode , label ) ; if ( before == NULL_RTX ) before = scratch ; emit_load_locked ( mode , before , mem ) ; if ( code == NOT ) x = gen_rtx_AND ( mode , gen_rtx_NOT ( mode , before ) , val ) ; else if ( code == AND ) x = gen_rtx_UNSPEC ( mode , gen_rtvec ( 2 , before , val ) , UNSPEC_AND ) ; else x = gen_rtx_fmt_ee ( code , mode , before , val ) ; if ( after != NULL_RTX ) emit_insn ( gen_rtx_SET ( VOIDmode , after , copy_rtx ( x ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , scratch , x ) ) ; emit_store_conditional ( mode , cond , mem , scratch ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label ) ; emit_insn ( gen_isync ( ) ) ; } </s>

Expand an an atomic fetch-and-operate pattern . CODE is the binary operation to perform . MEM is the memory on which to operate . VAL is the second operand of the binary operator . BEFORE and AFTER are optional locations to return the value of MEM either before of after the operation . SCRATCH is a scratch register .


<s> static Mfix * create_fix_barrier ( Mfix * fix , HOST_WIDE_INT max_address ) { HOST_WIDE_INT count = 0 ; rtx_barrier * barrier ; rtx_insn * from = fix -> insn ; rtx_insn * selected = NULL ; int selected_cost ; HOST_WIDE_INT selected_address ; Mfix * new_fix ; HOST_WIDE_INT max_count = max_address - fix -> address ; rtx_code_label * label = gen_label_rtx ( ) ; selected_cost = arm_barrier_cost ( from ) ; selected_address = fix -> address ; while ( from && count < max_count ) { rtx_jump_table_data * tmp ; int new_cost ; gcc_assert ( ! BARRIER_P ( from ) ) ; if ( LABEL_P ( from ) ) count += get_label_padding ( from ) ; else count += get_attr_length ( from ) ; if ( tablejump_p ( from , NULL , & tmp ) ) { count += get_jump_table_size ( tmp ) ; new_cost = arm_barrier_cost ( from ) ; if ( count < max_count && ( ! selected || new_cost <= selected_cost ) ) { selected = tmp ; selected_cost = new_cost ; selected_address = fix -> address + count ; } from = NEXT_INSN ( tmp ) ; continue ; } new_cost = arm_barrier_cost ( from ) ; if ( count < max_count && ( ! selected || new_cost <= selected_cost ) ) { selected = from ; selected_cost = new_cost ; selected_address = fix -> address + count ; } from = NEXT_INSN ( from ) ; } gcc_assert ( selected ) ; from = emit_jump_insn_after ( gen_jump ( label ) , selected ) ; JUMP_LABEL ( from ) = label ; barrier = emit_barrier_after ( from ) ; emit_label_after ( label , barrier ) ; new_fix = ( Mfix * ) obstack_alloc ( & minipool_obstack , sizeof ( * new_fix ) ) ; new_fix -> insn = barrier ; new_fix -> address = selected_address ; new_fix -> next = fix -> next ; fix -> next = new_fix ; return new_fix ; } </s>

Find the best place in the insn stream in the range ( FIX- > address , MAX_ADDRESS ) to forcibly insert a minipool barrier . Create the barrier by inserting a jump and add a new fix entry for it .


<s> bool ARMTargetLowering :: isShuffleMaskLegal ( ArrayRef < int > M , EVT VT ) const { if ( VT . getVectorNumElements ( ) == 4 && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ 4 ] ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { if ( M [ i ] < 0 ) PFIndexes [ i ] = 8 ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ 0 ] * 9 * 9 * 9 + PFIndexes [ 1 ] * 9 * 9 + PFIndexes [ 2 ] * 9 + PFIndexes [ 3 ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> 30 ) ; if ( Cost <= 4 && ( Subtarget -> hasNEON ( ) || isLegalMVEShuffleOp ( PFEntry ) ) ) return true ; } bool ReverseVEXT , isV_UNDEF ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; if ( EltSize >= 32 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isVREVMask ( M , VT , 64 ) || isVREVMask ( M , VT , 32 ) || isVREVMask ( M , VT , 16 ) ) return true ; else if ( Subtarget -> hasNEON ( ) && ( isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTBLMask ( M , VT ) || isNEONTwoResultShuffleMask ( M , VT , WhichResult , isV_UNDEF ) ) ) return true ; else if ( Subtarget -> hasNEON ( ) && ( VT == MVT :: v8i16 || VT == MVT :: v16i8 ) && isReverseMask ( M , VT ) ) return true ; else return false ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


"converted opcode should be the same except for cc_out"

"expect uninitialized optional cc_out operand"

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


<s> int const_ok_for_op ( HOST_WIDE_INT i , enum rtx_code code ) { if ( const_ok_for_arm ( i ) ) return 1 ; switch ( code ) { case SET : if ( TARGET_HAVE_MOVT && ( i & 0xffff0000 ) == 0 ) return 1 ; else return const_ok_for_arm ( ARM_SIGN_EXTEND ( ~ i ) ) ; case PLUS : if ( TARGET_THUMB2 && ( ( i & 0xfffff000 ) == 0 || ( ( - i ) & 0xfffff000 ) == 0 ) ) return 1 ; case COMPARE : case EQ : case NE : case GT : case LE : case LT : case GE : case GEU : case LTU : case GTU : case LEU : case UNORDERED : case ORDERED : case UNEQ : case UNGE : case UNLT : case UNGT : case UNLE : return const_ok_for_arm ( ARM_SIGN_EXTEND ( - i ) ) ; case MINUS : case XOR : return 0 ; case IOR : if ( TARGET_THUMB2 ) return const_ok_for_arm ( ARM_SIGN_EXTEND ( ~ i ) ) ; return 0 ; case AND : return const_ok_for_arm ( ARM_SIGN_EXTEND ( ~ i ) ) ; default : gcc_unreachable ( ) ; } } </s>

Return true if I is a valid constant for the operation CODE .


<s> static struct machine_function * nds32_init_machine_status ( void ) { struct machine_function * machine ; machine = ggc_cleared_alloc < machine_function > ( ) ; machine -> naked_p = 0 ; machine -> fp_as_gp_p = 0 ; return machine ; } </s>

Function to save and restore machine-specific function data .


<s> static void tilepro_print_operand_address ( FILE * file , rtx addr ) { if ( GET_CODE ( addr ) == POST_DEC || GET_CODE ( addr ) == POST_INC ) { int offset = GET_MODE_SIZE ( output_memory_reference_mode ) ; gcc_assert ( output_memory_reference_mode != VOIDmode ) ; if ( output_memory_autoinc_first ) fprintf ( file , "%s" , reg_names [ REGNO ( XEXP ( addr , 0 ) ) ] ) ; else fprintf ( file , "%d" , GET_CODE ( addr ) == POST_DEC ? - offset : offset ) ; } else if ( GET_CODE ( addr ) == POST_MODIFY ) { gcc_assert ( output_memory_reference_mode != VOIDmode ) ; gcc_assert ( GET_CODE ( XEXP ( addr , 1 ) ) == PLUS ) ; if ( output_memory_autoinc_first ) fprintf ( file , "%s" , reg_names [ REGNO ( XEXP ( addr , 0 ) ) ] ) ; else fprintf ( file , HOST_WIDE_INT_PRINT_DEC , INTVAL ( XEXP ( XEXP ( addr , 1 ) , 1 ) ) ) ; } else tilepro_print_operand ( file , addr , 'r' ) ; } </s>


<s>
void
arm_declare_function_name
(
FILE
*
stream
,
const
char
*
name
,
tree
decl
)
{
tree
target_parts
=
DECL_FUNCTION_SPECIFIC_TARGET
(
decl
)
;
struct
cl_target_option
*
targ_options
;
if
(
target_parts
)
targ_options
=
TREE_TARGET_OPTION
(
target_parts
)
;
else
targ_options
=
TREE_TARGET_OPTION
(
target_option_current_node
)
;
gcc_assert
(
targ_options
)
;
arm_print_asm_arch_directives
(
stream
,
targ_options
)
;
fprintf
(
stream
,
"\t.syntax unified\n"
)
;
if
(
TARGET_THUMB
)
{
if
(
is_called_in_ARM_mode
(
decl
)
||
(
TARGET_THUMB1
&&
!
TARGET_THUMB1_ONLY
&&
cfun
->
is_thunk
)
)
fprintf
(
stream
,
"\t.code 32\n"
)
;
else
if
(
TARGET_THUMB1
)
fprintf
(
stream
,
"\t.code\t16\n\t.thumb_func\n"
)
;
else
fprintf
(
stream
,
"\t.thumb\n\t.thumb_func\n"
)
;
}
else
fprintf
(
stream
,
"\t.arm\n"
)
;
if
(
TARGET_POKE_FUNCTION_NAME
)
arm_poke_function_name
(
stream
,
(
const
char
*
)
name
)
;
}
</s>

Implement ASM_DECLARE_FUNCTION_NAME . Output the ISA features used by the function fndecl .


<s> TargetPassConfig * PTXTargetMachine :: createPassConfig ( PassManagerBase & PM ) { PTXPassConfig * PassConfig = new PTXPassConfig ( this , PM ) ; PassConfig -> disablePass ( PrologEpilogCodeInserterID ) ; return PassConfig ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s>
void
M680x0InstrInfo
::
AddSExt
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
Reg
,
MVT
From
,
MVT
To
)
const
{
if
(
From
==
MVT
::
i8
)
{
unsigned
R
=
Reg
;
if
(
To
==
MVT
::
i32
)
{
R
=
RI
.
getSubReg
(
Reg
,
M680x0
::
MxSubRegIndex16Lo
)
;
assert
(
R
&&
"No viable SUB register available"
)
;
}
BuildMI
(
MBB
,
I
,
DL
,
get
(
M680x0
::
EXT16
)
,
R
)
.
addReg
(
R
)
;
}
if
(
To
==
MVT
::
i32
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
M680x0
::
EXT32
)
,
Reg
)
.
addReg
(
Reg
)
;
}
}
</s>


<s> FastISel * MipsTargetLowering :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) const { if ( ! EnableMipsFastISel ) return TargetLowering :: createFastISel ( funcInfo , libInfo ) ; return Mips :: createFastISel ( funcInfo , libInfo ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"SI prepare scratch registers"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool Thumb1FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( ARM :: tPUSH ) ) ; AddDefaultPred ( MIB ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; bool isKill = true ; if ( Reg == ARM :: LR ) { MachineFunction & MF = * MBB . getParent ( ) ; if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) && MF . getRegInfo ( ) . isLiveIn ( Reg ) ) isKill = false ; } if ( isKill ) MBB . addLiveIn ( Reg ) ; MIB . addReg ( Reg , getKillRegState ( isKill ) ) ; } MIB . setMIFlags ( MachineInstr :: FrameSetup ) ; return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s>
bool
PIC16AsmPrinter
::
doInitialization
(
Module
&
M
)
{
bool
Result
=
AsmPrinter
::
doInitialization
(
M
)
;
O
<<
"\t#include P16F1937.INC\n"
;
EmitExternsAndGlobals
(
M
)
;
EmitInitData
(
M
)
;
EmitUnInitData
(
M
)
;
EmitRomData
(
M
)
;
return
Result
;
}
</s>

Set up the AsmPrinter when we are working on a new module .


<s> int HexagonInstrInfo :: getMaxValue ( const MachineInstr * MI ) const { const uint64_t F = MI -> getDesc ( ) . TSFlags ; unsigned isSigned = ( F >> HexagonII :: ExtentSignedPos ) & HexagonII :: ExtentSignedMask ; unsigned bits = ( F >> HexagonII :: ExtentBitsPos ) & HexagonII :: ExtentBitsMask ; if ( isSigned ) return ~ ( - 1 << ( bits - 1 ) ) ; else return ~ ( - 1 << bits ) ; } </s>

Return the maximal unsigned value possible given these KnownBits .

Hexagon Hexagon HexagonII::ExtentSignedPos HexagonII::ExtentSignedMask HexagonII::ExtentBitsPos HexagonII::ExtentBitsMask 1 1 1


<s> bool SIInstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Cond , Register DstReg , Register TrueReg , Register FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { switch ( Cond [ 0 ] . getImm ( ) ) { case VCCNZ : case VCCZ : { const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = MRI . getRegClass ( TrueReg ) ; if ( MRI . getRegClass ( FalseReg ) != RC ) return false ; int NumInsts = AMDGPU :: getRegBitWidth ( RC -> getID ( ) ) / 32 ; CondCycles = TrueCycles = FalseCycles = NumInsts ; return RI . hasVGPRs ( RC ) && NumInsts <= 6 ; } case SCC_TRUE : case SCC_FALSE : { const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = MRI . getRegClass ( TrueReg ) ; if ( MRI . getRegClass ( FalseReg ) != RC ) return false ; int NumInsts = AMDGPU :: getRegBitWidth ( RC -> getID ( ) ) / 32 ; if ( NumInsts % 2 == 0 ) NumInsts /= 2 ; CondCycles = TrueCycles = FalseCycles = NumInsts ; return RI . isSGPRClass ( RC ) ; } default : return false ; } } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> bool offset_ok_for_ldrd_strd ( HOST_WIDE_INT offset ) { HOST_WIDE_INT max_offset ; if ( TARGET_THUMB2 && ( ( offset & 3 ) != 0 ) ) return false ; if ( TARGET_THUMB2 ) max_offset = 1020 ; else if ( TARGET_ARM ) max_offset = 255 ; else return false ; return ( ( offset <= max_offset ) && ( offset >= - max_offset ) ) ; } </s>

Returns true iff OFFSET is valid for use in an LDRD/STRD instruction , assuming that the address in the base register is word aligned .


<s> rtx bfin_return_addr_rtx ( int count ) { if ( count != 0 ) return const0_rtx ; return get_hard_reg_initial_val ( Pmode , REG_RETS ) ; } </s>

Return the value of the return address for the frame COUNT steps up from the current frame , after the prologue . We punt for everything but the current frame by returning const0_rtx .


<s> unsigned getCallingConv ( ) const { return CallingConv ; } </s>


<s>
unsigned
AArch64TargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"sp"
,
AArch64
::
SP
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> void X86FrameLowering :: emitStackProbe ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , bool InProlog , Optional < MachineFunction :: DebugInstrOperandPair > InstrNum ) const { const X86Subtarget & STI = MF . getSubtarget < X86Subtarget > ( ) ; if ( STI . isTargetWindowsCoreCLR ( ) ) { if ( InProlog ) { BuildMI ( MBB , MBBI , DL , TII . get ( X86 :: STACKALLOC_W_PROBING ) ) . addImm ( 0 ) ; } else { emitStackProbeInline ( MF , MBB , MBBI , DL , false ) ; } } else { emitStackProbeCall ( MF , MBB , MBBI , DL , InProlog , InstrNum ) ; } } </s>


<s> bool MSP430TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_MSP430 ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> void WebAssemblyPassConfig :: addPreEmitPass ( ) { } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( auto CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s> void TeakPassConfig :: addPreEmitPass ( ) { addPass ( createTeakOptimizeMovImmPass ( ) ) ; addPass ( & BranchRelaxationPassID ) ; } </s>


<s> bool PPCTTIImpl :: isHardwareLoopProfitable ( Loop * L , ScalarEvolution & SE , AssumptionCache & AC , TargetLibraryInfo * LibInfo , TTI :: HardwareLoopInfo & HWLoopInfo ) { const PPCTargetMachine & TM = ST -> getTargetMachine ( ) ; TargetSchedModel SchedModel ; SchedModel . init ( ST ) ; unsigned ConstTripCount = SE . getSmallConstantTripCount ( L ) ; if ( ConstTripCount && ConstTripCount < SmallCTRLoopThreshold ) { SmallPtrSet < const Value * , 32 > EphValues ; CodeMetrics :: collectEphemeralValues ( L , & AC , EphValues ) ; CodeMetrics Metrics ; for ( BasicBlock * BB : L -> blocks ( ) ) Metrics . analyzeBasicBlock ( BB , * this , EphValues ) ; if ( Metrics . NumInsts <= ( 6 * SchedModel . getIssueWidth ( ) ) ) return false ; } for ( Loop :: block_iterator I = L -> block_begin ( ) , IE = L -> block_end ( ) ; I != IE ; ++ I ) if ( mightUseCTR ( * I , LibInfo ) ) return false ; SmallVector < BasicBlock * , 4 > ExitingBlocks ; L -> getExitingBlocks ( ExitingBlocks ) ; for ( auto & BB : ExitingBlocks ) { Instruction * TI = BB -> getTerminator ( ) ; if ( ! TI ) continue ; if ( BranchInst * BI = dyn_cast < BranchInst > ( TI ) ) { uint64_t TrueWeight = 0 , FalseWeight = 0 ; if ( ! BI -> isConditional ( ) || ! BI -> extractProfMetadata ( TrueWeight , FalseWeight ) ) continue ; bool TrueIsExit = ! L -> contains ( BI -> getSuccessor ( 0 ) ) ; if ( ( TrueIsExit && FalseWeight < TrueWeight ) || ( ! TrueIsExit && FalseWeight > TrueWeight ) ) return false ; } } LLVMContext & C = L -> getHeader ( ) -> getContext ( ) ; HWLoopInfo . CountType = TM . isPPC64 ( ) ? Type :: getInt64Ty ( C ) : Type :: getInt32Ty ( C ) ; HWLoopInfo . LoopDecrement = ConstantInt :: get ( HWLoopInfo . CountType , 1 ) ; return true ; } </s>

Query the target whether it would be profitable to convert the given loop into a hardware loop .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; AU . addRequired < ScalarEvolution > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static rtx rs6000_pre_atomic_barrier ( rtx mem , enum memmodel model ) { rtx addr = XEXP ( mem , 0 ) ; int strict_p = ( reload_in_progress || reload_completed ) ; if ( ! legitimate_indirect_address_p ( addr , strict_p ) && ! legitimate_indexed_address_p ( addr , strict_p ) ) { addr = force_reg ( Pmode , addr ) ; mem = replace_equiv_address_nv ( mem , addr ) ; } switch ( model ) { case MEMMODEL_RELAXED : case MEMMODEL_CONSUME : case MEMMODEL_ACQUIRE : break ; case MEMMODEL_RELEASE : case MEMMODEL_ACQ_REL : emit_insn ( gen_lwsync ( ) ) ; break ; case MEMMODEL_SEQ_CST : emit_insn ( gen_hwsync ( ) ) ; break ; default : gcc_unreachable ( ) ; } return mem ; } </s>

Expand barriers before and after a load_locked/store_cond sequence .


<s> bool HexagonGenMux :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; HII = MF . getSubtarget < HexagonSubtarget > ( ) . getInstrInfo ( ) ; HRI = MF . getSubtarget < HexagonSubtarget > ( ) . getRegisterInfo ( ) ; bool Changed = false ; for ( auto & I : MF ) Changed |= genMuxInBlock ( I ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


"passing arg %d of %qE discards qualifiers from"

"invalid parameter combination for AltiVec intrinsic"

Implementation of the resolve_overloaded_builtin target hook , to support Altivec 's overloaded builtins .


<s>
void
MCS51InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
DebugLoc
&
DL
,
MCRegister
DestReg
,
MCRegister
SrcReg
,
bool
KillSrc
)
const
{
const
MCS51Subtarget
&
STI
=
MBB
.
getParent
(
)
->
getSubtarget
<
MCS51Subtarget
>
(
)
;
const
MCS51RegisterInfo
&
TRI
=
*
STI
.
getRegisterInfo
(
)
;
unsigned
Opc
;
if
(
MCS51
::
DREGSRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
if
(
STI
.
hasMOVW
(
)
&&
MCS51
::
DREGSMOVWRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
MI
,
DL
,
get
(
MCS51
::
MOVWRdRr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
else
{
Register
DestLo
,
DestHi
,
SrcLo
,
SrcHi
;
TRI
.
splitReg
(
DestReg
,
DestLo
,
DestHi
)
;
TRI
.
splitReg
(
SrcReg
,
SrcLo
,
SrcHi
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
MCS51
::
MOVRdRr
)
,
DestLo
)
.
addReg
(
SrcLo
,
getKillRegState
(
KillSrc
)
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
MCS51
::
MOVRdRr
)
,
DestHi
)
.
addReg
(
SrcHi
,
getKillRegState
(
KillSrc
)
)
;
}
}
else
{
if
(
MCS51
::
GPR8RegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
Opc
=
MCS51
::
MOVRdRr
;
}
else
if
(
SrcReg
==
MCS51
::
SP
&&
MCS51
::
DREGSRegClass
.
contains
(
DestReg
)
)
{
Opc
=
MCS51
::
SPREAD
;
}
else
if
(
DestReg
==
MCS51
::
SP
&&
MCS51
::
DREGSRegClass
.
contains
(
SrcReg
)
)
{
Opc
=
MCS51
::
SPWRITE
;
}
else
{
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
}
</s>


<s> bool aarch64_sve_inc_dec_immediate_p ( rtx x ) { return aarch64_sve_inc_dec_immediate_p ( x , NULL , NULL ) ; } </s>

Return true if X is a valid immediate for an SVE vector INC or DEC instruction .


<s> unsigned X86InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case X86 :: MOV8mr : case X86 :: MOV16mr : case X86 :: MOV16_mr : case X86 :: MOV32mr : case X86 :: MOV32_mr : case X86 :: MOV64mr : case X86 :: ST_FpP64m : case X86 :: MOVSSmr : case X86 :: MOVSDmr : case X86 :: MOVAPSmr : case X86 :: MOVAPDmr : case X86 :: MOVDQAmr : case X86 :: MMX_MOVD64mr : case X86 :: MMX_MOVQ64mr : case X86 :: MMX_MOVNTQmr : if ( MI -> getOperand ( 0 ) . isFI ( ) && MI -> getOperand ( 1 ) . isImm ( ) && MI -> getOperand ( 2 ) . isReg ( ) && MI -> getOperand ( 3 ) . isImm ( ) && MI -> getOperand ( 1 ) . getImm ( ) == 1 && MI -> getOperand ( 2 ) . getReg ( ) == 0 && MI -> getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 0 ) . getIndex ( ) ; return MI -> getOperand ( 4 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s>
bool
AArch64AsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNum
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
&&
ExtraCode
[
0
]
!=
'a'
)
return
true
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNum
)
;
assert
(
MO
.
isReg
(
)
&&
"unexpected inline asm memory operand"
)
;
O
<<
"["
<<
AArch64InstPrinter
::
getRegisterName
(
MO
.
getReg
(
)
)
<<
"]"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> static rtx csky_function_arg ( cumulative_args_t pcum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * pcum = get_cumulative_args ( pcum_v ) ; int reg = pcum -> reg ; machine_mode mode = arg . mode ; if ( FUNCTION_VARG_MODE_P ( mode ) && ! pcum -> is_stdarg ) { reg = pcum -> freg ; if ( reg < CSKY_NPARM_FREGS ) return gen_rtx_REG ( mode , CSKY_FIRST_VFP_REGNUM + reg ) ; else return NULL_RTX ; } if ( reg < CSKY_NPARM_REGS ) return gen_rtx_REG ( mode , CSKY_FIRST_PARM_REGNUM + reg ) ; return NULL_RTX ; } </s>

Determine where to put an argument to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) .


"failed to spill SGPR to VGPR when allocated"


"Can't store this register to stack slot"

Load the specified register of the given register class from the specified stack frame index .


": code %4d = 0x%04x (%4d), prologues %3d, epilogues %3d */\n"

Outputs to the stdio stream FILE some appropriate text to go at the end of an assembler file .


<s> static void rs6000_do_expand_vec_perm ( rtx target , rtx op0 , rtx op1 , machine_mode vmode , unsigned nelt , rtx perm [ ] ) { machine_mode imode ; rtx x ; imode = vmode ; if ( GET_MODE_CLASS ( vmode ) != MODE_VECTOR_INT ) { imode = GET_MODE_INNER ( vmode ) ; imode = mode_for_size ( GET_MODE_BITSIZE ( imode ) , MODE_INT , 0 ) ; imode = mode_for_vector ( imode , nelt ) ; } x = gen_rtx_CONST_VECTOR ( imode , gen_rtvec_v ( nelt , perm ) ) ; x = expand_vec_perm ( vmode , op0 , op1 , x , target ) ; if ( x != target ) emit_move_insn ( target , x ) ; } </s>

A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave .


<s>
bool
NVPTXAsmPrinter
::
doInitialization
(
Module
&
M
)
{
SmallString
<
128
>
Str1
;
raw_svector_ostream
OS1
(
Str1
)
;
MMI
=
getAnalysisIfAvailable
<
MachineModuleInfo
>
(
)
;
MMI
->
AnalyzeModule
(
M
)
;
const_cast
<
TargetLoweringObjectFile
&
>
(
getObjFileLowering
(
)
)
.
Initialize
(
OutContext
,
TM
)
;
Mang
=
new
Mangler
(
TM
.
getSubtargetImpl
(
)
->
getDataLayout
(
)
)
;
emitHeader
(
M
,
OS1
)
;
OutStreamer
.
EmitRawText
(
OS1
.
str
(
)
)
;
if
(
!
M
.
getModuleInlineAsm
(
)
.
empty
(
)
)
{
OutStreamer
.
AddComment
(
"Start of file scope inline assembly"
)
;
OutStreamer
.
AddBlankLine
(
)
;
OutStreamer
.
EmitRawText
(
StringRef
(
M
.
getModuleInlineAsm
(
)
)
)
;
OutStreamer
.
AddBlankLine
(
)
;
OutStreamer
.
AddComment
(
"End of file scope inline assembly"
)
;
OutStreamer
.
AddBlankLine
(
)
;
}
if
(
nvptxSubtarget
.
getDrvInterface
(
)
==
NVPTX
::
CUDA
)
recordAndEmitFilenames
(
M
)
;
GlobalsEmitted
=
false
;
return
false
;
}
</s>

Set up the AsmPrinter when we are working on a new module .

NVPTX
NVPTX
128
"Start of file scope inline assembly"
"End of file scope inline assembly"
NVPTX::CUDA


<s> void GCNIterativeScheduler :: finalizeSchedule ( ) { if ( Regions . empty ( ) ) return ; switch ( Strategy ) { case SCHEDULE_MINREGONLY : scheduleMinReg ( ) ; break ; case SCHEDULE_MINREGFORCED : scheduleMinReg ( true ) ; break ; case SCHEDULE_LEGACYMAXOCCUPANCY : scheduleLegacyMaxOccupancy ( ) ; break ; } } </s>

After the schedule has been formed , call this function to combine the instructions from the different stages/cycles .


<s> void XtensaAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool isMem ( ) const override { return false ; } </s>


<s>
void
XtensaFrameLowering
::
emitEpilogue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
getLastNonDebugInstr
(
)
;
DebugLoc
dl
=
MBBI
->
getDebugLoc
(
)
;
uint64_t
StackSize
=
computeStackSize
(
MF
)
;
if
(
!
StackSize
)
{
return
;
}
llvm_unreachable
(
"Couldn't reach here"
)
;
}
</s>


<s>
const
char
*
getPassName
(
)
const
override
{
return
"ARM64 branch relaxation pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
char
*
xstormy16_output_cbranch_si
(
rtx
op
,
const
char
*
label
,
int
reversed
,
rtx
insn
)
{
static
char
string
[
64
]
;
int
need_longbranch
=
get_attr_length
(
insn
)
>=
8
;
int
really_reversed
=
reversed
^
need_longbranch
;
const
char
*
ccode
;
const
char
*
template
;
char
prevop
[
16
]
;
enum
rtx_code
code
;
code
=
GET_CODE
(
op
)
;
if
(
really_reversed
)
code
=
reverse_condition
(
code
)
;
switch
(
code
)
{
case
EQ
:
ccode
=
"z"
;
break
;
case
NE
:
ccode
=
"nz"
;
break
;
case
GE
:
ccode
=
"ge"
;
break
;
case
LT
:
ccode
=
"lt"
;
break
;
case
GEU
:
ccode
=
"nc"
;
break
;
case
LTU
:
ccode
=
"c"
;
break
;
default
:
gcc_unreachable
(
)
;
}
switch
(
code
)
{
case
EQ
:
case
NE
:
{
int
regnum
;
gcc_assert
(
GET_CODE
(
XEXP
(
op
,
0
)
)
==
REG
)
;
regnum
=
REGNO
(
XEXP
(
op
,
0
)
)
;
sprintf
(
prevop
,
"or %s,%s"
,
reg_names
[
regnum
]
,
reg_names
[
regnum
+
1
]
)
;
}
break
;
case
GE
:
case
LT
:
case
GEU
:
case
LTU
:
strcpy
(
prevop
,
"sbc %2,%3"
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
if
(
need_longbranch
)
template
=
"%s | b%s .+6 | jmpf %s"
;
else
template
=
"%s | b%s %s"
;
sprintf
(
string
,
template
,
prevop
,
ccode
,
label
)
;
return
string
;
}
</s>

Return the string to output a conditional branch to LABEL , which is the operand number of the label , but suitable for the tail of a SImode branch . OP is the conditional expression ( OP is never NULL_RTX ) . REVERSED is non-zero if we should reverse the sense of the comparison . INSN is the insn .


<s> void MipsRegisterInfo :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = prior ( MBB . end ( ) ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; int FPOffset = MipsFI -> getFPStackOffset ( ) ; int RAOffset = MipsFI -> getRAStackOffset ( ) ; if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDu ) , Mips :: SP ) . addReg ( Mips :: FP ) . addReg ( Mips :: ZERO ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: LW ) , Mips :: FP ) . addImm ( FPOffset ) . addReg ( Mips :: SP ) ; } if ( MFI -> hasCalls ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: LW ) , Mips :: RA ) . addImm ( RAOffset ) . addReg ( Mips :: SP ) ; } if ( NumBytes ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDiu ) , Mips :: SP ) . addReg ( Mips :: SP ) . addImm ( NumBytes ) ; } } </s>

Mips Mips Mips Mips Mips Mips Mips Mips::ADDu Mips::SP Mips::FP Mips::ZERO Mips::LW Mips::FP Mips::SP Mips::LW Mips::RA Mips::SP Mips::ADDiu Mips::SP Mips::SP


<s> static void arm32_output_mi_thunk ( FILE * file , tree , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { int this_regno = ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ? R1_REGNUM : R0_REGNUM ) ; rtx temp = gen_rtx_REG ( Pmode , IP_REGNUM ) ; rtx this_rtx = gen_rtx_REG ( Pmode , this_regno ) ; reload_completed = 1 ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; if ( delta != 0 ) arm_split_constant ( PLUS , Pmode , NULL_RTX , delta , this_rtx , this_rtx , false ) ; if ( vcall_offset != 0 ) { emit_move_insn ( temp , gen_rtx_MEM ( Pmode , this_rtx ) ) ; arm_split_constant ( PLUS , Pmode , NULL_RTX , vcall_offset , temp , temp , false ) ; emit_move_insn ( temp , gen_rtx_MEM ( Pmode , temp ) ) ; emit_insn ( gen_add3_insn ( this_rtx , this_rtx , temp ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = 1 ; } rtx funexp = XEXP ( DECL_RTL ( function ) , 0 ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; rtx_insn * insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx , NULL_RTX ) ) ; SIBLING_CALL_P ( insn ) = 1 ; insn = get_insns ( ) ; shorten_branches ( insn ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; reload_completed = 0 ; } </s>


<s>
MachineBasicBlock
::
iterator
SIFrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
int64_t
Amount
=
I
->
getOperand
(
0
)
.
getImm
(
)
;
if
(
Amount
==
0
)
return
MBB
.
erase
(
I
)
;
const
GCNSubtarget
&
ST
=
MF
.
getSubtarget
<
GCNSubtarget
>
(
)
;
const
SIInstrInfo
*
TII
=
ST
.
getInstrInfo
(
)
;
const
DebugLoc
&
DL
=
I
->
getDebugLoc
(
)
;
unsigned
Opc
=
I
->
getOpcode
(
)
;
bool
IsDestroy
=
Opc
==
TII
->
getCallFrameDestroyOpcode
(
)
;
uint64_t
CalleePopAmount
=
IsDestroy
I
->
getOperand
(
1
)
.
getImm
(
)
:
0
;
if
(
!
hasReservedCallFrame
(
MF
)
)
{
unsigned
Align
=
getStackAlignment
(
)
;
Amount
=
alignTo
(
Amount
,
Align
)
;
assert
(
isUInt
<
32
>
(
Amount
)
&&
"exceeded stack address space size"
)
;
const
SIMachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
SIMachineFunctionInfo
>
(
)
;
unsigned
SPReg
=
MFI
->
getStackPtrOffsetReg
(
)
;
unsigned
Op
=
IsDestroy
AMDGPU
::
S_SUB_U32
:
AMDGPU
::
S_ADD_U32
;
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
Op
)
,
SPReg
)
.
addReg
(
SPReg
)
.
addImm
(
Amount
*
ST
.
getWavefrontSize
(
)
)
;
}
else
if
(
CalleePopAmount
!=
0
)
{
llvm_unreachable
(
"is this used?"
)
;
}
return
MBB
.
erase
(
I
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> unsigned SparcRegisterInfo :: getRARegister ( ) const { return SP :: I7 ; } </s>

This method should return the register where the return address can be found .


<s> MachineBasicBlock :: iterator X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { bool reserveCallFrame = hasReservedCallFrame ( MF ) ; unsigned Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = TII . getFrameSize ( * I ) ; uint64_t InternalAmt = ( isDestroy || Amount ) ? TII . getFrameAdjustment ( * I ) : 0 ; I = MBB . erase ( I ) ; auto InsertPos = skipDebugInstructionsForward ( I , MBB . end ( ) ) ; if ( isDestroy && blockEndIsUnreachable ( MBB , I ) ) return I ; if ( ! reserveCallFrame ) { Amount = alignTo ( Amount , getStackAlign ( ) ) ; const Function & F = MF . getFunction ( ) ; bool WindowsCFI = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool DwarfCFI = ! WindowsCFI && MF . needsFrameMoves ( ) ; bool HasDwarfEHHandlers = ! WindowsCFI && ! MF . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < X86MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == 0 ) return I ; Amount -= InternalAmt ; if ( isDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ; int64_t StackAdjustment = isDestroy ? Amount : - Amount ; if ( StackAdjustment ) { StackAdjustment += mergeSPUpdates ( MBB , InsertPos , true ) ; StackAdjustment += mergeSPUpdates ( MBB , InsertPos , false ) ; if ( StackAdjustment ) { if ( ! ( F . hasMinSize ( ) && adjustStackWithPops ( MBB , InsertPos , DL , StackAdjustment ) ) ) BuildStackAdjustment ( MBB , InsertPos , DL , StackAdjustment , false ) ; } } if ( DwarfCFI && ! hasFP ( MF ) ) { int64_t CfaAdjustment = - StackAdjustment ; if ( CfaAdjustment ) { BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , CfaAdjustment ) ) ; } } return I ; } if ( InternalAmt ) { MachineBasicBlock :: iterator CI = I ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( CI != B && ! std :: prev ( CI ) -> isCall ( ) ) -- CI ; BuildStackAdjustment ( MBB , CI , DL , - InternalAmt , false ) ; } return I ; } </s>


<s> SDNode * Cpu0DAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = MF -> getInfo < Cpu0FunctionInfo > ( ) -> getGlobalBaseReg ( ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI . getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> rtx ix86_build_signbit_mask ( enum machine_mode mode , bool vect , bool invert ) { enum machine_mode vec_mode ; HOST_WIDE_INT hi , lo ; int shift = 63 ; rtvec v ; rtx mask ; if ( mode == SFmode ) lo = 0x80000000 , hi = lo < 0 ; else if ( HOST_BITS_PER_WIDE_INT >= 64 ) lo = ( HOST_WIDE_INT ) 1 << shift , hi = - 1 ; else lo = 0 , hi = ( HOST_WIDE_INT ) 1 << ( shift - HOST_BITS_PER_WIDE_INT ) ; if ( invert ) lo = ~ lo , hi = ~ hi ; mask = immed_double_const ( lo , hi , mode == SFmode ? SImode : DImode ) ; mask = gen_lowpart ( mode , mask ) ; if ( mode == SFmode ) { if ( vect ) v = gen_rtvec ( 4 , mask , mask , mask , mask ) ; else v = gen_rtvec ( 4 , mask , CONST0_RTX ( SFmode ) , CONST0_RTX ( SFmode ) , CONST0_RTX ( SFmode ) ) ; vec_mode = V4SFmode ; } else { if ( vect ) v = gen_rtvec ( 2 , mask , mask ) ; else v = gen_rtvec ( 2 , mask , CONST0_RTX ( DFmode ) ) ; vec_mode = V2DFmode ; } return force_reg ( vec_mode , gen_rtx_CONST_VECTOR ( vec_mode , v ) ) ; } </s>

A subroutine of ix86_expand_fp_absneg_operator and copysign expanders . Create a mask for the sign bit in MODE for an SSE register . If VECT is true , then replicate the mask for all elements of the vector register . If INVERT is true , then create a mask excluding the sign bit .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , computeDefaultCPU ( TT , CPU ) , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveAArch64CodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } if ( getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) { this -> Options . TrapUnreachable = true ; } if ( this -> Options . TLSSize == 0 ) this -> Options . TLSSize = 24 ; if ( ( getCodeModel ( ) == CodeModel :: Small || getCodeModel ( ) == CodeModel :: Kernel ) && this -> Options . TLSSize > 32 ) this -> Options . TLSSize = 32 ; else if ( getCodeModel ( ) == CodeModel :: Tiny && this -> Options . TLSSize > 24 ) this -> Options . TLSSize = 24 ; if ( getOptLevel ( ) <= EnableGlobalISelAtO && TT . getArch ( ) != Triple :: aarch64_32 && TT . getArchName ( ) != "arm64e" && ! ( getCodeModel ( ) == CodeModel :: Large && TT . isOSBinFormatMachO ( ) ) ) { setGlobalISel ( true ) ; setGlobalISelAbort ( GlobalISelAbortMode :: Disable ) ; } setMachineOutliner ( true ) ; setSupportsDefaultOutlining ( true ) ; setSupportsDebugEntryValues ( true ) ; } </s>


<s> bool TPCTargetLowering :: isProfitableToHoist ( Instruction * I ) const { if ( I -> getOpcode ( ) == Instruction :: Call ) return false ; return TargetLowering :: isProfitableToHoist ( I ) ; } </s>

Return true if it is profitable to hoist instruction in the then/else to before if .


"********** Abstract Member Accesses **********\n"

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> static rtx frv_expand_store_builtin ( enum insn_code icode , tree arglist ) { rtx op0 = frv_read_argument ( & arglist ) ; rtx op1 = frv_read_argument ( & arglist ) ; rtx cookie = frv_io_address_cookie ( op0 ) ; op0 = frv_volatile_memref ( insn_data [ icode ] . operand [ 0 ] . mode , op0 ) ; convert_move ( op0 , force_reg ( insn_data [ icode ] . operand [ 0 ] . mode , op1 ) , 1 ) ; emit_insn ( GEN_FCN ( icode ) ( copy_rtx ( op0 ) , cookie , GEN_INT ( FRV_IO_WRITE ) ) ) ; cfun -> machine -> has_membar_p = 1 ; return NULL_RTX ; } </s>


<s> void PPCAIXAsmPrinter :: SetupMachineFunction ( MachineFunction & MF ) { CurrentFnDescSym = getSymbol ( & MF . getFunction ( ) ) ; MCSectionXCOFF * FnDescSec = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForFunctionDescriptor ( CurrentFnDescSym ) ) ; cast < MCSymbolXCOFF > ( CurrentFnDescSym ) -> setContainingCsect ( FnDescSec ) ; return AsmPrinter :: SetupMachineFunction ( MF ) ; } </s>

This should be called when a new MachineFunction is being processed from runOnMachineFunction .


<s> enum reg_class secondary_reload_class ( enum reg_class class , enum machine_mode mode ATTRIBUTE_UNUSED , rtx in ) { int regno ; if ( TARGET_ELF || ( DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT ) ) { if ( class != BASE_REGS && ( GET_CODE ( in ) == SYMBOL_REF || GET_CODE ( in ) == HIGH || GET_CODE ( in ) == LABEL_REF || GET_CODE ( in ) == CONST ) ) return BASE_REGS ; } if ( GET_CODE ( in ) == REG ) { regno = REGNO ( in ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) { regno = true_regnum ( in ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) regno = - 1 ; } } else if ( GET_CODE ( in ) == SUBREG ) { regno = true_regnum ( in ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) regno = - 1 ; } else regno = - 1 ; if ( class == GENERAL_REGS || class == BASE_REGS || ( regno >= 0 && INT_REGNO_P ( regno ) ) ) return NO_REGS ; if ( ( regno == - 1 || FP_REGNO_P ( regno ) ) && ( class == FLOAT_REGS || class == NON_SPECIAL_REGS ) ) return NO_REGS ; if ( ( regno == - 1 || ALTIVEC_REGNO_P ( regno ) ) && class == ALTIVEC_REGS ) return NO_REGS ; if ( ( class == CR_REGS || class == CR0_REGS ) && regno >= 0 && CR_REGNO_P ( regno ) ) return NO_REGS ; return GENERAL_REGS ; } </s>

Return the class of any secondary reload register that is needed to move IN into a register in class CLASS using mode MODE . Profiling has showed this routine and its descendants account for a significant amount of compile time ( ~7 % ) . So it has been optimized to reduce redundant computations and eliminate useless function calls . It might be worthwhile to try and make this a leaf function too .


"rs6000_compare_version_priority (%s, %s) => %d\n"

This compares the priority of target features in function DECL1 and DECL2 . It returns positive value if DECL1 is higher priority , negative value if DECL2 is higher priority and 0 if they are the same . Note , priorities are ordered from lowest ( CLONE_DEFAULT ) to highest ( currently CLONE_ISA_3_0 ) .


<s> bool AZPRPassConfig :: addInstSelector ( ) { addPass ( createAZPRISelDag ( getAZPRTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s>
ScheduleHazardRecognizer
::
HazardType
SPUHazardRecognizer
::
getHazardType
(
SUnit
*
SU
)
{
const
SDNode
*
Node
=
SU
->
getNode
(
)
->
getFlaggedMachineNode
(
)
;
ScheduleHazardRecognizer
::
HazardType
retval
=
NoHazard
;
bool
mustBeOdd
=
false
;
switch
(
Node
->
getOpcode
(
)
)
{
case
SPU
::
LQDv16i8
:
case
SPU
::
LQDv8i16
:
case
SPU
::
LQDv4i32
:
case
SPU
::
LQDv4f32
:
case
SPU
::
LQDv2f64
:
case
SPU
::
LQDr128
:
case
SPU
::
LQDr64
:
case
SPU
::
LQDr32
:
case
SPU
::
LQDr16
:
case
SPU
::
LQAv16i8
:
case
SPU
::
LQAv8i16
:
case
SPU
::
LQAv4i32
:
case
SPU
::
LQAv4f32
:
case
SPU
::
LQAv2f64
:
case
SPU
::
LQAr128
:
case
SPU
::
LQAr64
:
case
SPU
::
LQAr32
:
case
SPU
::
LQXv4i32
:
case
SPU
::
LQXr128
:
case
SPU
::
LQXr64
:
case
SPU
::
LQXr32
:
case
SPU
::
LQXr16
:
case
SPU
::
STQDv16i8
:
case
SPU
::
STQDv8i16
:
case
SPU
::
STQDv4i32
:
case
SPU
::
STQDv4f32
:
case
SPU
::
STQDv2f64
:
case
SPU
::
STQDr128
:
case
SPU
::
STQDr64
:
case
SPU
::
STQDr32
:
case
SPU
::
STQDr16
:
case
SPU
::
STQDr8
:
case
SPU
::
STQAv16i8
:
case
SPU
::
STQAv8i16
:
case
SPU
::
STQAv4i32
:
case
SPU
::
STQAv4f32
:
case
SPU
::
STQAv2f64
:
case
SPU
::
STQAr128
:
case
SPU
::
STQAr64
:
case
SPU
::
STQAr32
:
case
SPU
::
STQAr16
:
case
SPU
::
STQAr8
:
case
SPU
::
STQXv16i8
:
case
SPU
::
STQXv8i16
:
case
SPU
::
STQXv4i32
:
case
SPU
::
STQXv4f32
:
case
SPU
::
STQXv2f64
:
case
SPU
::
STQXr128
:
case
SPU
::
STQXr64
:
case
SPU
::
STQXr32
:
case
SPU
::
STQXr16
:
case
SPU
::
STQXr8
:
case
SPU
::
RET
:
mustBeOdd
=
true
;
break
;
default
:
break
;
}
if
(
mustBeOdd
&&
!
EvenOdd
)
retval
=
Hazard
;
DOUT
<<
"SPUHazardRecognizer EvenOdd "
<<
EvenOdd
<<
" Hazard "
<<
retval
<<
"\n"
;
EvenOdd
^=
1
;
return
retval
;
return
NoHazard
;
}
</s>

getHazardType - Return the hazard type of emitting this node .


<s> RCPair ARMTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: tGPRRegClass ) ; return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'h' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: hGPRRegClass ) ; break ; case 'r' : if ( Subtarget -> isThumb1Only ( ) ) return RCPair ( 0U , & ARM :: tGPRRegClass ) ; return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'w' : if ( VT == MVT :: Other ) break ; if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPRRegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPRRegClass ) ; break ; case 'x' : if ( VT == MVT :: Other ) break ; if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPR_8RegClass ) ; break ; case 't' : if ( VT == MVT :: Other ) break ; if ( VT == MVT :: f32 || VT == MVT :: i32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPR_VFP2RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPR_VFP2RegClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( ARM :: CPSR ) , & ARM :: CCRRegClass ) ; return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> int ix86_expand_int_addcc ( rtx operands [ ] ) { enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; rtx compare_op ; rtx val = const0_rtx ; bool fpcmp = false ; enum machine_mode mode = GET_MODE ( operands [ 0 ] ) ; if ( operands [ 3 ] != const1_rtx && operands [ 3 ] != constm1_rtx ) return 0 ; if ( ! ix86_expand_carry_flag_compare ( code , ix86_compare_op0 , ix86_compare_op1 , & compare_op ) ) return 0 ; code = GET_CODE ( compare_op ) ; if ( GET_MODE ( XEXP ( compare_op , 0 ) ) == CCFPmode || GET_MODE ( XEXP ( compare_op , 0 ) ) == CCFPUmode ) { fpcmp = true ; code = ix86_fp_compare_code_to_integer ( code ) ; } if ( code != LTU ) { val = constm1_rtx ; if ( fpcmp ) PUT_CODE ( compare_op , reverse_condition_maybe_unordered ( GET_CODE ( compare_op ) ) ) ; else PUT_CODE ( compare_op , reverse_condition ( GET_CODE ( compare_op ) ) ) ; } PUT_MODE ( compare_op , mode ) ; if ( ( code == LTU ) == ( operands [ 3 ] == constm1_rtx ) ) { switch ( GET_MODE ( operands [ 0 ] ) ) { case QImode : emit_insn ( gen_subqi3_carry ( operands [ 0 ] , operands [ 2 ] , val , compare_op ) ) ; break ; case HImode : emit_insn ( gen_subhi3_carry ( operands [ 0 ] , operands [ 2 ] , val , compare_op ) ) ; break ; case SImode : emit_insn ( gen_subsi3_carry ( operands [ 0 ] , operands [ 2 ] , val , compare_op ) ) ; break ; case DImode : emit_insn ( gen_subdi3_carry_rex64 ( operands [ 0 ] , operands [ 2 ] , val , compare_op ) ) ; break ; default : gcc_unreachable ( ) ; } } else { switch ( GET_MODE ( operands [ 0 ] ) ) { case QImode : emit_insn ( gen_addqi3_carry ( operands [ 0 ] , operands [ 2 ] , val , compare_op ) ) ; break ; case HImode : emit_insn ( gen_addhi3_carry ( operands [ 0 ] , operands [ 2 ] , val , compare_op ) ) ; break ; case SImode : emit_insn ( gen_addsi3_carry ( operands [ 0 ] , operands [ 2 ] , val , compare_op ) ) ; break ; case DImode : emit_insn ( gen_adddi3_carry_rex64 ( operands [ 0 ] , operands [ 2 ] , val , compare_op ) ) ; break ; default : gcc_unreachable ( ) ; } } return 1 ; } </s>

Expand conditional increment or decrement using adb/sbb instructions . The default case using setcc followed by the conditional move can be done by generic code .


<s> tree builtin_decl ( unsigned int code , bool ) { if ( code >= vec_safe_length ( registered_functions ) ) return error_mark_node ; return ( * registered_functions ) [ code ] -> decl ; } </s>

Return the function decl with RVV function subcode CODE , or error_mark_node if no such function exists .


<s> static int alpha_issue_rate ( ) { return ( alpha_cpu == PROCESSOR_EV4 ? 2 : 4 ) ; } </s>

Function to initialize the issue rate used by the scheduler .


<s> TargetStackID :: Value RISCVFrameLowering :: getStackIDForScalableVectors ( ) const { return TargetStackID :: ScalableVector ; } </s>

Returns the StackID that scalable vectors should be associated with .


<s> EVT LM32TargetLowering :: getSetCCResultType ( LLVMContext & Context , EVT VT ) const { return MVT :: i32 ; } </s>

Return the value type to use for ISD : :SETCC .


Return true if the current function must save REGNO .


"WebAssembly should not have callee-saved registers"

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool PPCPassConfig :: addInstSelector ( ) { addPass ( createPPCISelDag ( getPPCTargetMachine ( ) ) ) ; if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCCTRLoopsVerify ( ) ) ; return false ; } </s>


<s> MCSection * getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , Align & Alignment ) const override { return TextSection ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .