<s>
SDValue
PPCTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCRetInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCRetInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_PPC
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
VT
=
VA
.
getValVT
(
)
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
VT
,
InFlag
)
.
getValue
(
1
)
;
InVals
.
push_back
(
Chain
.
getValue
(
0
)
)
;
InFlag
=
Chain
.
getValue
(
2
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static __inline float sh_media_FMAC_S ( float fg , float fh , float fq ) { return fg * fh + fq ; } </s>


"Code generation for MIPS-I is not implemented"

"Code generation for MIPS-V is not implemented"

"MSA requires a 64-bit FPU register file (FR=1 mode). "

"-mattr=+nooddspreg requires the O32 ABI."

"FPXX is not permitted for the N32/N64 ABI's."

"position-independent code requires '-mabicalls'"

"warning: cannot use small-data accesses for '-mabicalls'"

This constructor initializes the data members to match that of the specified triple .


<s>
StringRef
getPassName
(
)
const
override
{
return
"RISCV Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"extended registers have no high halves"

"unsupported operand size for extended register"


<s> const AMDGPUTargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


<s> bool WDC65816PassConfig :: addInstSelector ( ) { addPass ( createWDC65816ISelDag ( getWDC65816TargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void P2MCInstLower :: Initialize ( MCContext * C ) { Ctx = C ; } </s>

This method must be called before any actual lowering is done .


<s>
void
pass_vsetvl
::
compute_local_backward_infos
(
const
bb_info
*
bb
)
{
vector_insn_info
change
;
change
.
set_empty
(
)
;
auto
&
block_info
=
m_vector_manager
->
vector_block_infos
[
bb
->
index
(
)
]
;
block_info
.
reaching_out
=
change
;
for
(
insn_info
*
insn
:
bb
->
reverse_real_nondebug_insns
(
)
)
{
auto
&
info
=
m_vector_manager
->
vector_insn_infos
[
insn
->
uid
(
)
]
;
if
(
info
.
uninit_p
(
)
)
info
=
change
;
else
if
(
info
.
unknown_p
(
)
)
change
=
info
;
else
{
gcc_assert
(
info
.
valid_p
(
)
&&
"Unexpected Invalid demanded info"
)
;
if
(
change
.
valid_p
(
)
)
{
if
(
!
(
propagate_avl_across_demands_p
(
change
,
info
)
&&
!
reg_available_p
(
insn
,
change
)
)
&&
change
.
compatible_p
(
info
)
)
{
info
=
change
.
merge
(
info
)
;
if
(
vsetvl_insn_p
(
insn
->
rtl
(
)
)
)
change_vsetvl_insn
(
insn
,
info
)
;
}
}
change
=
info
;
}
}
block_info
.
local_dem
=
change
;
if
(
block_info
.
local_dem
.
empty_p
(
)
)
block_info
.
reaching_out
=
block_info
.
local_dem
;
}
</s>

Compute demanded information by backward data-flow analysis .

riscv
"Unexpected Invalid demanded info"


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
]
=
{
{
"reloc_riprel_4byte"
,
0
,
4
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_movq_load"
,
0
,
4
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_signed_4byte"
,
0
,
4
*
8
,
0
}
,
{
"reloc_global_offset_table"
,
0
,
4
*
8
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCCodeEmitter
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> rtx ix86_find_base_term ( rtx x ) { rtx term ; if ( TARGET_64BIT ) { if ( GET_CODE ( x ) != CONST ) return x ; term = XEXP ( x , 0 ) ; if ( GET_CODE ( term ) == PLUS && CONST_INT_P ( XEXP ( term , 1 ) ) ) term = XEXP ( term , 0 ) ; if ( GET_CODE ( term ) != UNSPEC || ( XINT ( term , 1 ) != UNSPEC_GOTPCREL && XINT ( term , 1 ) != UNSPEC_PCREL ) ) return x ; return XVECEXP ( term , 0 , 0 ) ; } return ix86_delegitimize_address_1 ( x , true ) ; } </s>

If X is a machine specific address ( i.e . a symbol or label being referenced as a displacement from the GOT implemented using an UNSPEC ) , then return the base term . Otherwise return X .


"SystemZ DAG->DAG Pattern Instruction Selection"


<s> static rtx loongarch_got_load_tls_gd ( rtx dest , rtx sym ) { return gen_got_load_tls_gd ( Pmode , dest , sym ) ; } </s>

Load an entry from the GOT for a TLS GD access .


<s> rtx rs6000_address_for_fpconvert ( rtx x ) { int strict_p = ( reload_in_progress || reload_completed ) ; rtx addr ; gcc_assert ( MEM_P ( x ) ) ; addr = XEXP ( x , 0 ) ; if ( ! legitimate_indirect_address_p ( addr , strict_p ) && ! legitimate_indexed_address_p ( addr , strict_p ) ) { if ( GET_CODE ( addr ) == PRE_INC || GET_CODE ( addr ) == PRE_DEC ) { rtx reg = XEXP ( addr , 0 ) ; HOST_WIDE_INT size = GET_MODE_SIZE ( GET_MODE ( x ) ) ; rtx size_rtx = GEN_INT ( ( GET_CODE ( addr ) == PRE_DEC ) ? - size : size ) ; gcc_assert ( REG_P ( reg ) ) ; emit_insn ( gen_add3_insn ( reg , reg , size_rtx ) ) ; addr = reg ; } else if ( GET_CODE ( addr ) == PRE_MODIFY ) { rtx reg = XEXP ( addr , 0 ) ; rtx expr = XEXP ( addr , 1 ) ; gcc_assert ( REG_P ( reg ) ) ; gcc_assert ( GET_CODE ( expr ) == PLUS ) ; emit_insn ( gen_add3_insn ( reg , XEXP ( expr , 0 ) , XEXP ( expr , 1 ) ) ) ; addr = reg ; } x = replace_equiv_address ( x , copy_addr_to_reg ( addr ) ) ; } return x ; } </s>

Given a memory reference , if it is not a reg or reg+reg addressing , convert to such a form to deal with memory reference instructions like STFIWX that only take reg+reg addressing .


"Unaligned memory access not supported: not "

"DSP extension not enabled: not running pass "

"Only supporting little endian: not running pass "

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , computeDataLayout ( TT , is64bit ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , CM , OL ) , TLOF ( make_unique < SparcELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this , is64bit ) , is64Bit ( is64bit ) { initAsmInfo ( ) ; } </s>


<s> static const char * singlemove_string ( rtx * operands ) { if ( operands [ 1 ] != const0_rtx ) return "mov\t%1,%0" ; return "clr\t%0" ; } </s>

Return the best assembler insn template for moving operands [ 1 ] into operands [ 0 ] as a fullword .


<s> virtual const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> const uint16_t * XtensaRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_Xtensa_SaveList ; } </s>


<s> static bool rs6000_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { unsigned from_size = GET_MODE_SIZE ( from ) ; unsigned to_size = GET_MODE_SIZE ( to ) ; if ( from_size != to_size ) { enum reg_class xclass = ( TARGET_VSX ) ? VSX_REGS : FLOAT_REGS ; if ( reg_classes_intersect_p ( xclass , rclass ) ) { unsigned to_nregs = hard_regno_nregs ( FIRST_FPR_REGNO , to ) ; unsigned from_nregs = hard_regno_nregs ( FIRST_FPR_REGNO , from ) ; bool to_float128_vector_p = FLOAT128_VECTOR_P ( to ) ; bool from_float128_vector_p = FLOAT128_VECTOR_P ( from ) ; if ( to_float128_vector_p && from_float128_vector_p ) return true ; else if ( to_float128_vector_p || from_float128_vector_p ) return false ; if ( ! BYTES_BIG_ENDIAN && ( to == TDmode || from == TDmode ) ) return false ; if ( ( to == DDmode && from == SDmode ) || ( to == SDmode && from == DDmode ) ) return true ; if ( from_size < 8 || to_size < 8 ) return false ; if ( from_size == 8 && ( 8 * to_nregs ) != to_size ) return false ; if ( to_size == 8 && ( 8 * from_nregs ) != from_size ) return false ; return true ; } else return true ; } if ( TARGET_VSX && VSX_REG_CLASS_P ( rclass ) ) { unsigned num_regs = ( from_size + 15 ) / 16 ; if ( hard_regno_nregs ( FIRST_FPR_REGNO , to ) > num_regs || hard_regno_nregs ( FIRST_FPR_REGNO , from ) > num_regs ) return false ; return ( from_size == 8 || from_size == 16 ) ; } if ( TARGET_ALTIVEC && rclass == ALTIVEC_REGS && ( ALTIVEC_VECTOR_MODE ( from ) + ALTIVEC_VECTOR_MODE ( to ) ) == 1 ) return false ; return true ; } </s>


<s> virtual const MCObjectFormat & getObjectFormat ( ) const { return Format ; } </s>


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"RISCV Branch Selector"
;
}
</s>


<s>
bool
X86InstrInfo
::
classifyLEAReg
(
MachineInstr
&
MI
,
const
MachineOperand
&
Src
,
unsigned
Opc
,
bool
AllowSP
,
Register
&
NewSrc
,
bool
&
isKill
,
MachineOperand
&
ImplicitOp
,
LiveVariables
*
LV
)
const
{
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
const
TargetRegisterClass
*
RC
;
if
(
AllowSP
)
{
RC
=
Opc
!=
X86
::
LEA32r
&
X86
::
GR64RegClass
:
&
X86
::
GR32RegClass
;
}
else
{
RC
=
Opc
!=
X86
::
LEA32r
&
X86
::
GR64_NOSPRegClass
:
&
X86
::
GR32_NOSPRegClass
;
}
Register
SrcReg
=
Src
.
getReg
(
)
;
isKill
=
MI
.
killsRegister
(
SrcReg
)
;
if
(
Opc
!=
X86
::
LEA64_32r
)
{
NewSrc
=
SrcReg
;
assert
(
!
Src
.
isUndef
(
)
&&
"Undef op doesn't need optimization"
)
;
if
(
NewSrc
.
isVirtual
(
)
&&
!
MF
.
getRegInfo
(
)
.
constrainRegClass
(
NewSrc
,
RC
)
)
return
false
;
return
true
;
}
if
(
SrcReg
.
isPhysical
(
)
)
{
ImplicitOp
=
Src
;
ImplicitOp
.
setImplicit
(
)
;
NewSrc
=
getX86SubSuperRegister
(
SrcReg
,
64
)
;
assert
(
!
Src
.
isUndef
(
)
&&
"Undef op doesn't need optimization"
)
;
}
else
{
NewSrc
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
RC
)
;
MachineInstr
*
Copy
=
BuildMI
(
*
MI
.
getParent
(
)
,
MI
,
MI
.
getDebugLoc
(
)
,
get
(
TargetOpcode
::
COPY
)
)
.
addReg
(
NewSrc
,
RegState
::
Define
|
RegState
::
Undef
,
X86
::
sub_32bit
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
isKill
=
true
;
if
(
LV
)
LV
->
replaceKillInstruction
(
SrcReg
,
MI
,
*
Copy
)
;
}
return
true
;
}
</s>

Given an operand within a MachineInstr , insert preceding code to put it into the right format for a particular kind of LEA instruction .


<s> bool RISCVFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return true ; MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) DL = MI -> getDebugLoc ( ) ; const char * SpillLibCall = getSpillLibCallName ( * MF , CSI ) ; if ( SpillLibCall ) { BuildMI ( MBB , MI , DL , TII . get ( RISCV :: PseudoCALLReg ) , RISCV :: X5 ) . addExternalSymbol ( SpillLibCall , RISCVII :: MO_CALL ) . setMIFlag ( MachineInstr :: FrameSetup ) ; for ( auto & CS : CSI ) MBB . addLiveIn ( CS . getReg ( ) ) ; } const auto & NonLibcallCSI = getNonLibcallCSI ( * MF , CSI ) ; for ( auto & CS : NonLibcallCSI ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static tree spu_gimplify_va_arg_expr ( tree valist , tree type , gimple_seq * pre_p , gimple_seq * post_p ATTRIBUTE_UNUSED ) { tree f_args , f_skip ; tree args , skip ; HOST_WIDE_INT size , rsize ; tree addr , tmp ; bool pass_by_reference_p ; f_args = TYPE_FIELDS ( TREE_TYPE ( va_list_type_node ) ) ; f_skip = DECL_CHAIN ( f_args ) ; args = build3 ( COMPONENT_REF , TREE_TYPE ( f_args ) , valist , f_args , NULL_TREE ) ; skip = build3 ( COMPONENT_REF , TREE_TYPE ( f_skip ) , valist , f_skip , NULL_TREE ) ; addr = create_tmp_var ( ptr_type_node , "va_arg" ) ; pass_by_reference_p = pass_by_reference ( NULL , TYPE_MODE ( type ) , type , false ) ; if ( pass_by_reference_p ) type = build_pointer_type ( type ) ; size = int_size_in_bytes ( type ) ; rsize = ( ( size + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ) * UNITS_PER_WORD ; tmp = fold_build_pointer_plus_hwi ( unshare_expr ( args ) , rsize ) ; tmp = build2 ( TRUTH_AND_EXPR , boolean_type_node , build2 ( GT_EXPR , boolean_type_node , tmp , unshare_expr ( skip ) ) , build2 ( LE_EXPR , boolean_type_node , unshare_expr ( args ) , unshare_expr ( skip ) ) ) ; tmp = build3 ( COND_EXPR , ptr_type_node , tmp , fold_build_pointer_plus_hwi ( unshare_expr ( skip ) , 32 ) , unshare_expr ( args ) ) ; gimplify_assign ( addr , tmp , pre_p ) ; tmp = fold_build_pointer_plus_hwi ( addr , rsize ) ; gimplify_assign ( unshare_expr ( args ) , tmp , pre_p ) ; addr = fold_convert ( build_pointer_type_for_mode ( type , ptr_mode , true ) , addr ) ; if ( pass_by_reference_p ) addr = build_va_arg_indirect_ref ( addr ) ; return build_va_arg_indirect_ref ( addr ) ; } </s>

Gimplify va_arg by updating the va_list structure VALIST as required to retrieve an argument of type TYPE , and returning that argument . ret = va_arg ( VALIST , TYPE ) ; generates code equivalent to : paddedsize = ( sizeof ( TYPE ) + 15 ) & -16 ; if ( VALIST.__args + paddedsize > VALIST.__skip & & VALIST.__args < = VALIST.__skip ) addr = VALIST.__skip + 32 ; else addr = VALIST.__args ; VALIST.__args = addr + paddedsize ; ret = * ( TYPE * ) addr ;


<s> bool RISCVTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { switch ( Intrinsic ) { default : return false ; case Intrinsic :: riscv_masked_atomicrmw_xchg_i32 : case Intrinsic :: riscv_masked_atomicrmw_add_i32 : case Intrinsic :: riscv_masked_atomicrmw_sub_i32 : case Intrinsic :: riscv_masked_atomicrmw_nand_i32 : case Intrinsic :: riscv_masked_atomicrmw_max_i32 : case Intrinsic :: riscv_masked_atomicrmw_min_i32 : case Intrinsic :: riscv_masked_atomicrmw_umax_i32 : case Intrinsic :: riscv_masked_atomicrmw_umin_i32 : case Intrinsic :: riscv_masked_cmpxchg_i32 : PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 0 ) -> getType ( ) ) ; Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: getVT ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . align = Align ( 4 ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; } } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> unsigned int h8300_insn_length_from_table ( rtx_insn * insn , rtx * operands ) { switch ( get_attr_length_table ( insn ) ) { case LENGTH_TABLE_NONE : gcc_unreachable ( ) ; case LENGTH_TABLE_ADDB : return h8300_binary_length ( insn , & addb_length_table ) ; case LENGTH_TABLE_ADDW : return h8300_binary_length ( insn , & addw_length_table ) ; case LENGTH_TABLE_ADDL : return h8300_binary_length ( insn , & addl_length_table ) ; case LENGTH_TABLE_LOGICB : return h8300_binary_length ( insn , & logicb_length_table ) ; case LENGTH_TABLE_MOVB : return h8300_move_length ( operands , & movb_length_table ) ; case LENGTH_TABLE_MOVW : return h8300_move_length ( operands , & movw_length_table ) ; case LENGTH_TABLE_MOVL : return h8300_move_length ( operands , & movl_length_table ) ; case LENGTH_TABLE_MOVA : return h8300_mova_length ( operands [ 0 ] , operands [ 1 ] , operands [ 2 ] ) ; case LENGTH_TABLE_MOVA_ZERO : return h8300_mova_length ( operands [ 0 ] , operands [ 1 ] , const0_rtx ) ; case LENGTH_TABLE_UNARY : return h8300_unary_length ( operands [ 0 ] ) ; case LENGTH_TABLE_MOV_IMM4 : return 2 + h8300_classify_operand ( operands [ 0 ] , 0 , 0 ) ; case LENGTH_TABLE_SHORT_IMMEDIATE : return h8300_short_immediate_length ( operands [ 0 ] ) ; case LENGTH_TABLE_BITFIELD : return h8300_bitfield_length ( operands [ 0 ] , operands [ 1 ] ) ; case LENGTH_TABLE_BITBRANCH : return h8300_bitfield_length ( operands [ 1 ] , operands [ 2 ] ) - 2 ; default : gcc_unreachable ( ) ; } } </s>

Compute the length of INSN based on its length_table attribute . OPERANDS is the array of its operands .


<s> static void aarch64_init_fp16_types ( void ) { aarch64_fp16_type_node = make_node ( REAL_TYPE ) ; TYPE_PRECISION ( aarch64_fp16_type_node ) = 16 ; layout_type ( aarch64_fp16_type_node ) ; ( * lang_hooks . types . register_builtin_type ) ( aarch64_fp16_type_node , "__fp16" ) ; aarch64_fp16_ptr_type_node = build_pointer_type ( aarch64_fp16_type_node ) ; } </s>

Initialize the backend types that support the user-visible __fp16 type , also initialize a pointer to that type , to be used when forming HFAs .


<s> void AArch64AsmPrinter :: emitFunctionEntryLabel ( ) { if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: AArch64_VectorCall || MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: AArch64_SVE_VectorCall || STI -> getRegisterInfo ( ) -> hasSVEArgsOrReturn ( MF ) ) { auto * TS = static_cast < AArch64TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; TS -> emitDirectiveVariantPCS ( CurrentFnSym ) ; } return AsmPrinter :: emitFunctionEntryLabel ( ) ; } </s>

EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function .


<s>
void
SystemZInstrInfo
::
loadImmediate
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MBBI
,
unsigned
Reg
,
uint64_t
Value
)
const
{
DebugLoc
DL
=
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
unsigned
Opcode
;
if
(
isInt
<
16
>
(
Value
)
)
Opcode
=
SystemZ
::
LGHI
;
else
if
(
SystemZ
::
isImmLL
(
Value
)
)
Opcode
=
SystemZ
::
LLILL
;
else
if
(
SystemZ
::
isImmLH
(
Value
)
)
{
Opcode
=
SystemZ
::
LLILH
;
Value
>>=
16
;
}
else
{
assert
(
isInt
<
32
>
(
Value
)
&&
"Huge values not handled yet"
)
;
Opcode
=
SystemZ
::
LGFI
;
}
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
Opcode
)
,
Reg
)
.
addImm
(
Value
)
;
}
</s>

Emit a series of instructions to load an immediate .

SystemZ
SystemZ
16
SystemZ::LGHI
SystemZ::isImmLL
SystemZ::LLILL
SystemZ::isImmLH
SystemZ::LLILH
16
32
"Huge values not handled yet"
SystemZ::LGFI


<s> bool TeakTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { SDLoc DL ( N ) ; const LoadSDNode * ld = dyn_cast < LoadSDNode > ( N ) ; const StoreSDNode * st = dyn_cast < StoreSDNode > ( N ) ; if ( ! ( ld && ld -> getMemoryVT ( ) == MVT :: i16 ) && ! ( st && st -> getMemoryVT ( ) == MVT :: i16 ) ) return false ; if ( Op -> getOpcode ( ) != ISD :: ADD && Op -> getOpcode ( ) != ISD :: SUB ) return false ; if ( const ConstantSDNode * rhs = dyn_cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ) { int rhsc = rhs -> getSExtValue ( ) ; if ( Op -> getOpcode ( ) == ISD :: SUB ) rhsc = - rhsc ; if ( rhsc != 1 && rhsc != - 1 ) return false ; Base = Op -> getOperand ( 0 ) ; Offset = DAG . getConstant ( rhsc , DL , MVT :: i16 ) ; AM = ISD :: POST_INC ; return true ; } return false ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .


<s> static rtx xtensa_static_chain ( const_tree ARG_UNUSED ( fndecl_or_type ) , bool incoming_p ) { if ( TARGET_WINDOWED_ABI ) { rtx base = incoming_p ? arg_pointer_rtx : stack_pointer_rtx ; return gen_frame_mem ( Pmode , plus_constant ( Pmode , base , - 5 * UNITS_PER_WORD ) ) ; } else return gen_rtx_REG ( Pmode , A8_REG ) ; } </s>

The static chain is passed in memory . Provide rtx giving 'mem ' expressions that denote where they are stored .


"Hexagon-specific loop carried reuse for HVX vectors"

getPassName - Return a nice clean name for a pass .


<s> void SystemZTTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP ) { bool HasCall = false ; unsigned NumStores = 0 ; for ( auto & BB : L -> blocks ( ) ) for ( auto & I : * BB ) { if ( isa < CallInst > ( & I ) || isa < InvokeInst > ( & I ) ) { ImmutableCallSite CS ( & I ) ; if ( const Function * F = CS . getCalledFunction ( ) ) { if ( isLoweredToCall ( F ) ) HasCall = true ; if ( F -> getIntrinsicID ( ) == Intrinsic :: memcpy || F -> getIntrinsicID ( ) == Intrinsic :: memset ) NumStores ++ ; } else { HasCall = true ; } } if ( isa < StoreInst > ( & I ) ) { Type * MemAccessTy = I . getOperand ( 0 ) -> getType ( ) ; NumStores += getMemoryOpCost ( Instruction :: Store , MemAccessTy , 0 , 0 ) ; } } unsigned const Max = ( NumStores ? ( 12 / NumStores ) : UINT_MAX ) ; if ( HasCall ) { UP . FullUnrollMaxCount = Max ; UP . MaxCount = 1 ; return ; } UP . MaxCount = Max ; if ( UP . MaxCount <= 1 ) return ; UP . Partial = UP . Runtime = true ; UP . PartialThreshold = 75 ; UP . DefaultUnrollRuntimeCount = 4 ; UP . AllowExpensiveTripCount = true ; UP . Force = true ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> static bool mmix_rtx_costs ( rtx x ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , int outer_code ATTRIBUTE_UNUSED , int opno ATTRIBUTE_UNUSED , int * total ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { return false ; } </s>


<s> enum reg_class aarch64_regno_regclass ( unsigned regno ) { if ( GP_REGNUM_P ( regno ) ) return GENERAL_REGS ; if ( regno == SP_REGNUM ) return STACK_REG ; if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return POINTER_REGS ; if ( FP_REGNUM_P ( regno ) ) return FP_LO_REGNUM_P ( regno ) ? FP_LO_REGS : FP_REGS ; if ( PR_REGNUM_P ( regno ) ) return PR_LO_REGNUM_P ( regno ) ? PR_LO_REGS : PR_HI_REGS ; return NO_REGS ; } </s>


<s> bool AArch64TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { CCAssignFn * RetCC = CallConv == CallingConv :: WebKit_JS ? RetCC_AArch64_WebKit_JS : RetCC_AArch64_AAPCS ; SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , getTargetMachine ( ) , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> rtx rs6000_gen_le_vsx_permute ( rtx source , machine_mode mode ) { rtx par = gen_rtx_PARALLEL ( VOIDmode , rs6000_const_vec ( mode ) ) ; return gen_rtx_VEC_SELECT ( mode , source , par ) ; } </s>

Generate a permute rtx that represents an lxvd2x , stxvd2x , or xxpermdi for a VSX load or store operation .


<s> void aarch64_expand_sve_mem_move ( rtx dest , rtx src , machine_mode pred_mode ) { machine_mode mode = GET_MODE ( dest ) ; rtx ptrue = aarch64_ptrue_reg ( pred_mode ) ; if ( ! register_operand ( src , mode ) && ! register_operand ( dest , mode ) ) { rtx tmp = gen_reg_rtx ( mode ) ; if ( MEM_P ( src ) ) aarch64_emit_sve_pred_move ( tmp , ptrue , src ) ; else emit_move_insn ( tmp , src ) ; src = tmp ; } aarch64_emit_sve_pred_move ( dest , ptrue , src ) ; } </s>

Expand a pre-RA SVE data move from SRC to DEST in which at least one operand is in memory . In this case we need to use the predicated LD1 and ST1 instead of LDR and STR , both for correctness on big-endian targets and because LD1 and ST1 support a wider range of addressing modes . PRED_MODE is the mode of the predicate . See the comment at the head of aarch64-sve.md for details about the big-endian handling .


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const X86Subtarget & Subtarget = MF . getSubtarget < X86Subtarget > ( ) ; bool HasSSE = Subtarget . hasSSE1 ( ) ; bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return CSR_64_TLS_Darwin_RegMask ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: X86_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_RegMask : CSR_Win64_RegCall_NoSSE_RegMask ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_RegMask : CSR_SysV64_RegCall_NoSSE_RegMask ) ; } } else { return ( HasSSE ? CSR_32_RegCall_RegMask : CSR_32_RegCall_NoSSE_RegMask ) ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: X86_64_Win64 : return CSR_Win64_RegMask ; case CallingConv :: X86_64_SysV : return CSR_64_RegMask ; case CallingConv :: X86_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_64_AllRegs_RegMask ; return CSR_64_AllRegs_NoSSE_RegMask ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_32_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_32_AllRegs_SSE_RegMask ; return CSR_32_AllRegs_RegMask ; } default : break ; } if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_RegMask ; if ( Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) -> getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_64_SwiftError_RegMask ; return CSR_64_RegMask ; } return CSR_32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> SDNode * SparcDAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = TM . getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI . getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static rtx ix86_delegitimize_address ( rtx x ) { return ix86_delegitimize_address_1 ( x , false ) ; } </s>

In the name of slightly smaller debug output , and to cater to general assembler lossage , recognize PIC+GOTOFF and turn it back into a direct symbol reference . On Darwin , this is necessary to avoid a crash , because Darwin has a different PIC label for each routine but the DWARF debugging information is not associated with any particular routine , so it 's necessary to remove references to the PIC label from RTL stored by the DWARF output code .


<s> static bool prologue_saved_reg_p ( int regno ) { gcc_assert ( GP_REG_P ( regno ) ) ; if ( df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) ) return true ; if ( frame_pointer_needed && regno >= HARD_FRAME_POINTER_REGNUM && regno < HARD_FRAME_POINTER_REGNUM + GET_MODE_SIZE ( Pmode ) ) return true ; if ( regno == RA_REGNUM && df_regs_ever_live_p ( RA_REGNUM ) ) return true ; if ( regno == RA_REGNUM + 1 && df_regs_ever_live_p ( RA_REGNUM + 1 ) ) return true ; return false ; } </s>

Return true if REGNO should be saved in the prologue .


<s>
void
LanaiDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
return
;
}
EVT
VT
=
Node
->
getValueType
(
0
)
;
switch
(
Opcode
)
{
case
ISD
::
Constant
:
if
(
VT
==
MVT
::
i32
)
{
ConstantSDNode
*
ConstNode
=
cast
<
ConstantSDNode
>
(
Node
)
;
if
(
ConstNode
->
isZero
(
)
)
{
SDValue
New
=
CurDAG
->
getCopyFromReg
(
CurDAG
->
getEntryNode
(
)
,
SDLoc
(
Node
)
,
Lanai
::
R0
,
MVT
::
i32
)
;
return
ReplaceNode
(
Node
,
New
.
getNode
(
)
)
;
}
if
(
ConstNode
->
isAllOnes
(
)
)
{
SDValue
New
=
CurDAG
->
getCopyFromReg
(
CurDAG
->
getEntryNode
(
)
,
SDLoc
(
Node
)
,
Lanai
::
R1
,
MVT
::
i32
)
;
return
ReplaceNode
(
Node
,
New
.
getNode
(
)
)
;
}
}
break
;
case
ISD
::
FrameIndex
:
selectFrameIndex
(
Node
)
;
return
;
default
:
break
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> SDValue mprocTargetLowering :: LowerCall ( TargetLowering :: CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const { } </s>

This hook must be implemented to lower calls into the specified DAG .


<s> void WebAssemblyPassConfig :: addIRPasses ( ) { addPass ( new CoalesceFeaturesAndStripAtomics ( & getWebAssemblyTargetMachine ( ) ) ) ; addPass ( createAtomicExpandPass ( ) ) ; addPass ( createWebAssemblyAddMissingPrototypes ( ) ) ; addPass ( createWebAssemblyLowerGlobalDtors ( ) ) ; addPass ( createWebAssemblyFixFunctionBitcasts ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createWebAssemblyOptimizeReturned ( ) ) ; basicCheckForEHAndSjLj ( TM ) ; if ( ! WasmEnableEmEH && ! WasmEnableEH ) { addPass ( createLowerInvokePass ( ) ) ; addPass ( createUnreachableBlockEliminationPass ( ) ) ; } if ( WasmEnableEmEH || WasmEnableEmSjLj || WasmEnableSjLj ) addPass ( createWebAssemblyLowerEmscriptenEHSjLj ( ) ) ; addPass ( createIndirectBrExpandPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly


<s> const predefined_function_abi & aarch64_insn_callee_abi ( const rtx_insn * insn ) { rtx pat = PATTERN ( insn ) ; gcc_assert ( GET_CODE ( pat ) == PARALLEL ) ; rtx unspec = XVECEXP ( pat , 0 , 1 ) ; gcc_assert ( GET_CODE ( unspec ) == UNSPEC && XINT ( unspec , 1 ) == UNSPEC_CALLEE_ABI ) ; return function_abis [ INTVAL ( XVECEXP ( unspec , 0 , 0 ) ) ] ; } </s>


<s> static int avr_operand_rtx_cost ( rtx x , enum machine_mode mode , enum rtx_code outer ) { enum rtx_code code = GET_CODE ( x ) ; int total ; switch ( code ) { case REG : case SUBREG : return 0 ; case CONST_INT : case CONST_DOUBLE : return COSTS_N_INSNS ( GET_MODE_SIZE ( mode ) ) ; default : break ; } total = 0 ; avr_rtx_costs ( x , code , outer , & total ) ; return total ; } </s>

Mutually recursive subroutine of avr_rtx_cost for calculating the cost of an RTX operand given its context . X is the rtx of the operand , MODE is its mode , and OUTER is the rtx_code of this operand 's parent operator .


<s> bool SIRegisterInfo :: isAsmClobberable ( const MachineFunction & MF , MCRegister PhysReg ) const { return ! MF . getRegInfo ( ) . isReserved ( PhysReg ) ; } </s>

Returns false if we ca n't guarantee that Physreg , specified as an IR asm clobber constraint , will be preserved across the statement .


<s> const CallLowering * AArch64Subtarget :: getCallLowering ( ) const { if ( ! CallLoweringInfo ) CallLoweringInfo . reset ( new AArch64CallLowering ( TLInfo ) ) ; return CallLoweringInfo . get ( ) ; } </s>


"[Single-Path] Clone functions reachable from single-path roots\n"

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> static void rs6000_set_default_type_attributes ( tree type ) { if ( rs6000_default_long_calls && ( TREE_CODE ( type ) == FUNCTION_TYPE || TREE_CODE ( type ) == METHOD_TYPE ) ) TYPE_ATTRIBUTES ( type ) = tree_cons ( get_identifier ( "longcall" ) , NULL_TREE , TYPE_ATTRIBUTES ( type ) ) ; darwin_set_default_type_attributes ( type ) ; } </s>

Set longcall attributes on all functions declared when rs6000_default_long_calls is true .


<s> bool mergeStoresAfterLegalization ( EVT VT ) const override { return ! useSVEForFixedLengthVectors ( ) ; } </s>

Do not merge vector stores after legalization because that may conflict with x86-specific store splitting optimizations .


<s> int h8300_hard_regno_mode_ok ( int regno , machine_mode mode ) { if ( TARGET_H8300 ) return ( ( regno & 1 ) == 0 ) || ( mode == HImode ) || ( mode == QImode ) ; else return regno == MAC_REG ? mode == SImode : 1 ; } </s>

Worker function for HARD_REGNO_MODE_OK .


<s> bool PPCTargetLowering :: SelectAddressRegRegOnly ( SDValue N , SDValue & Base , SDValue & Index , SelectionDAG & DAG ) const { if ( SelectAddressRegReg ( N , Base , Index , DAG ) ) return true ; if ( N . getOpcode ( ) == ISD :: ADD ) { Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } Base = DAG . getRegister ( Subtarget . isPPC64 ( ) ? PPC :: ZERO8 : PPC :: ZERO , N . getValueType ( ) ) ; Index = N ; return true ; } </s>

SelectAddressRegRegOnly - Given the specified addressed , force it to be represented as an indexed [ r+r ] operation .


<s>
static
X86Operand
*
CreateMem
(
unsigned
SegReg
,
const
MCExpr
*
Disp
,
unsigned
BaseReg
,
unsigned
IndexReg
,
unsigned
Scale
,
SMLoc
StartLoc
,
SMLoc
EndLoc
,
unsigned
Size
=
0
,
bool
NeedSizeDir
=
false
)
{
assert
(
(
SegReg
||
BaseReg
||
IndexReg
)
&&
"Invalid memory operand!"
)
;
assert
(
(
(
Scale
==
1
||
Scale
==
2
||
Scale
==
4
||
Scale
==
8
)
)
&&
"Invalid scale!"
)
;
X86Operand
*
Res
=
new
X86Operand
(
Memory
,
StartLoc
,
EndLoc
)
;
Res
->
Mem
.
SegReg
=
SegReg
;
Res
->
Mem
.
Disp
=
Disp
;
Res
->
Mem
.
BaseReg
=
BaseReg
;
Res
->
Mem
.
IndexReg
=
IndexReg
;
Res
->
Mem
.
Scale
=
Scale
;
Res
->
Mem
.
Size
=
Size
;
Res
->
Mem
.
NeedSizeDir
=
NeedSizeDir
;
Res
->
AddressOf
=
false
;
return
Res
;
}
</s>


<s> int ia64_depz_field_mask ( rtx rop , rtx rshift ) { unsigned HOST_WIDE_INT op = INTVAL ( rop ) ; unsigned HOST_WIDE_INT shift = INTVAL ( rshift ) ; op >>= shift ; return exact_log2 ( op + 1 ) ; } </s>

Check if OP is a mask suitible for use with SHIFT in a dep.z instruction . Return the length of the field , or < = 0 on failure .


<s> tree resolve ( function_resolver & r ) const override { unsigned int i , nargs ; type_suffix_index type ; if ( ! r . check_gp_argument ( 1 , i , nargs ) || ( type = r . infer_vector_type ( i ) ) == NUM_TYPE_SUFFIXES ) return error_mark_node ; if ( type == TYPE_SUFFIX_b ) return r . resolve_to ( r . mode_suffix_id , type ) ; if ( type_suffixes [ type ] . integer_p && type_suffixes [ type ] . element_bits < 64 ) { type_suffix_index wide_suffix = find_type_suffix ( type_suffixes [ type ] . tclass , type_suffixes [ type ] . element_bits * 2 ) ; if ( tree res = r . lookup_form ( r . mode_suffix_id , wide_suffix ) ) return res ; } return r . report_no_such_form ( type ) ; } </s>

If the call is erroneous , report an appropriate error and return error_mark_node . Otherwise , if the function is overloaded , return the decl of the non-overloaded function . Return NULL_TREE otherwise , indicating that the call should be processed in the normal way .


"Only 32/64-bit atomic stores supported"

Perform a store-conditional operation to Addr .


<s>
bool
ThumbDisassembler
::
getInstruction
(
MCInst
&
MI
,
uint64_t
&
Size
,
const
MemoryObject
&
Region
,
uint64_t
Address
,
raw_ostream
&
os
)
const
{
uint32_t
insn
=
0
;
uint16_t
insn1
=
0
;
uint8_t
bytes
[
2
]
;
if
(
Region
.
readBytes
(
Address
,
2
,
(
uint8_t
*
)
bytes
,
)
==
1
)
return
false
;
insn
=
(
bytes
[
1
]
<<
8
)
|
bytes
[
0
]
;
unsigned
bits15_11
=
slice
(
insn
,
15
,
11
)
;
bool
IsThumb2
=
false
;
if
(
bits15_11
==
0x1D
||
bits15_11
==
0x1E
||
bits15_11
==
0x1F
)
{
IsThumb2
=
true
;
if
(
Region
.
readBytes
(
Address
+
2
,
2
,
(
uint8_t
*
)
bytes
,
)
==
1
)
return
false
;
insn1
=
(
bytes
[
1
]
<<
8
)
|
bytes
[
0
]
;
insn
=
(
insn
<<
16
|
insn1
)
;
}
unsigned
Opcode
=
decodeThumbSideEffect
(
IsThumb2
,
insn
)
;
if
(
Thumb2PreloadOpcodeNoPCI
(
Opcode
)
&&
slice
(
insn
,
19
,
16
)
==
15
)
Opcode
=
T2Morph2Preload2PCI
(
Opcode
)
;
ARMFormat
Format
=
ARMFormats
[
Opcode
]
;
Size
=
IsThumb2
4
:
2
;
DEBUG
(
{
errs
(
)
<<
"Opcode="
<<
Opcode
<<
" Name="
<<
ARMUtils
::
OpcodeName
(
Opcode
)
<<
" Format="
<<
stringForARMFormat
(
Format
)
<<
'('
<<
(
int
)
Format
<<
")\n"
;
showBitVector
(
errs
(
)
,
insn
)
;
}
)
;
ARMBasicMCBuilder
*
Builder
=
CreateMCBuilder
(
Opcode
,
Format
)
;
Builder
->
SetSession
(
const_cast
<
Session
*
>
(
&
SO
)
)
;
if
(
!
Builder
)
return
false
;
if
(
!
Builder
->
Build
(
MI
,
insn
)
)
return
false
;
delete
Builder
;
return
true
;
}
</s>

Returns the disassembly of a single instruction .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == 0 ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s> static bool rs6000_vector_alignment_reachable ( const_tree type ATTRIBUTE_UNUSED , bool is_packed ) { if ( is_packed ) return false ; if ( TARGET_32BIT ) { if ( rs6000_alignment_flags == MASK_ALIGN_NATURAL ) return true ; if ( rs6000_alignment_flags == MASK_ALIGN_POWER ) return true ; return false ; } else { if ( TARGET_MACHO ) return false ; return true ; } } </s>

Return true iff , data reference of TYPE can reach vector alignment ( 16 ) after applying N number of iterations . This routine does not determine how may iterations are required to reach desired alignment .


<s> static void xstormy16_print_operand_address ( FILE * file , machine_mode , rtx address ) { HOST_WIDE_INT offset ; int pre_dec , post_inc ; if ( CONST_INT_P ( address ) ) { fprintf ( file , HOST_WIDE_INT_PRINT_DEC , INTVAL ( address ) & 0xFFFF ) ; return ; } if ( CONSTANT_P ( address ) || LABEL_P ( address ) ) { output_addr_const ( file , address ) ; return ; } if ( GET_CODE ( address ) == PLUS ) { gcc_assert ( CONST_INT_P ( XEXP ( address , 1 ) ) ) ; offset = INTVAL ( XEXP ( address , 1 ) ) ; address = XEXP ( address , 0 ) ; } else offset = 0 ; pre_dec = ( GET_CODE ( address ) == PRE_DEC ) ; post_inc = ( GET_CODE ( address ) == POST_INC ) ; if ( pre_dec || post_inc ) address = XEXP ( address , 0 ) ; gcc_assert ( REG_P ( address ) ) ; fputc ( '(' , file ) ; if ( pre_dec ) fputs ( "--" , file ) ; fputs ( reg_names [ REGNO ( address ) ] , file ) ; if ( post_inc ) fputs ( "++" , file ) ; if ( offset != 0 ) fprintf ( file , "," HOST_WIDE_INT_PRINT_DEC , offset ) ; fputc ( ')' , file ) ; } </s>

Print a memory address as an operand to reference that memory location .


<s> SDValue X86TargetLowering :: expandIndirectJTBranch ( const SDLoc & dl , SDValue Value , SDValue Addr , SelectionDAG & DAG ) const { const Module * M = DAG . getMachineFunction ( ) . getMMI ( ) . getModule ( ) ; Metadata * IsCFProtectionSupported = M -> getModuleFlag ( "cf-protection-branch" ) ; if ( IsCFProtectionSupported ) { return DAG . getNode ( X86ISD :: NT_BRIND , dl , MVT :: Other , Value , Addr ) ; } return TargetLowering :: expandIndirectJTBranch ( dl , Value , Addr , DAG ) ; } </s>

Expands target specific indirect branch for the case of JumpTable expansion .


<s> static bool is_cracked_insn ( rtx_insn * insn ) { if ( ! insn || ! NONDEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; if ( rs6000_sched_groups && ( rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5 ) ) { enum attr_type type = get_attr_type ( insn ) ; if ( ( type == TYPE_LOAD && get_attr_sign_extend ( insn ) == SIGN_EXTEND_YES && get_attr_update ( insn ) == UPDATE_NO ) || ( type == TYPE_LOAD && get_attr_sign_extend ( insn ) == SIGN_EXTEND_NO && get_attr_update ( insn ) == UPDATE_YES && get_attr_indexed ( insn ) == INDEXED_NO ) || ( type == TYPE_STORE && get_attr_update ( insn ) == UPDATE_YES && get_attr_indexed ( insn ) == INDEXED_NO ) || ( ( type == TYPE_FPLOAD || type == TYPE_FPSTORE ) && get_attr_update ( insn ) == UPDATE_YES ) || type == TYPE_DELAYED_CR || ( type == TYPE_EXTS && get_attr_dot ( insn ) == DOT_YES ) || ( type == TYPE_SHIFT && get_attr_dot ( insn ) == DOT_YES && get_attr_var_shift ( insn ) == VAR_SHIFT_NO ) || ( type == TYPE_MUL && get_attr_dot ( insn ) == DOT_YES ) || type == TYPE_DIV || ( type == TYPE_INSERT && get_attr_size ( insn ) == SIZE_32 ) ) return true ; } return false ; } </s>

The function returns true if INSN is cracked into 2 instructions by the processor ( and therefore occupies 2 issue slots ) .


<s> bool isImm ( ) const { return Kind == CV_Immediate ; } </s>


<s> bool HexagonEarlyIfConversion :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; auto & ST = MF . getSubtarget < HexagonSubtarget > ( ) ; HII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; MFN = & MF ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MBPI = EnableHexagonBP ? & getAnalysis < MachineBranchProbabilityInfo > ( ) : nullptr ; Deleted . clear ( ) ; bool Changed = false ; for ( MachineLoopInfo :: iterator I = MLI -> begin ( ) , E = MLI -> end ( ) ; I != E ; ++ I ) Changed |= visitLoop ( * I ) ; Changed |= visitLoop ( nullptr ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> static int arc_asm_insn_p ( rtx x ) { int i , j ; if ( x == 0 ) return 0 ; switch ( GET_CODE ( x ) ) { case ASM_OPERANDS : case ASM_INPUT : return 1 ; case SET : return arc_asm_insn_p ( SET_SRC ( x ) ) ; case PARALLEL : j = 0 ; for ( i = XVECLEN ( x , 0 ) - 1 ; i >= 0 ; i -- ) j += arc_asm_insn_p ( XVECEXP ( x , 0 , i ) ) ; if ( j > 0 ) return 1 ; break ; default : break ; } return 0 ; } </s>

Given a rtx , check if it is an assembly instruction or not .


<s> void TOYInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , get ( TOY :: LOADrr ) , DestReg ) . addFrameIndex ( FI ) . addReg ( TOY :: ZERO ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { if ( Inst . getNumOperands ( ) == 0 ) return false ; if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ 0 ] . OperandType == MCOI :: OPERAND_PCREL ) { int64_t Imm = Inst . getOperand ( 0 ) . getImm ( ) ; Target = Addr + Size + Imm ; return true ; } else { int64_t Imm = Inst . getOperand ( 0 ) . getImm ( ) ; if ( Imm == 0 ) return false ; Target = Imm ; return true ; } } </s>

Given a branch instruction try to get the address the branch targets .


<s> static rtx rs6000_pre_atomic_barrier ( rtx mem , enum memmodel model ) { rtx addr = XEXP ( mem , 0 ) ; if ( ! legitimate_indirect_address_p ( addr , reload_completed ) && ! legitimate_indexed_address_p ( addr , reload_completed ) ) { addr = force_reg ( Pmode , addr ) ; mem = replace_equiv_address_nv ( mem , addr ) ; } switch ( model ) { case MEMMODEL_RELAXED : case MEMMODEL_CONSUME : case MEMMODEL_ACQUIRE : break ; case MEMMODEL_RELEASE : case MEMMODEL_ACQ_REL : emit_insn ( gen_lwsync ( ) ) ; break ; case MEMMODEL_SEQ_CST : emit_insn ( gen_hwsync ( ) ) ; break ; default : gcc_unreachable ( ) ; } return mem ; } </s>

Expand barriers before and after a load_locked/store_cond sequence .


<s> bool Z80oldTargetLowering :: isZExtFree ( EVT VT1 , EVT VT2 ) const { return VT1 == MVT :: i16 && VT2 == MVT :: i24 && Subtarget . is24Bit ( ) ; } </s>

Return true if zero-extending the specific node Val to type VT2 is free ( either because it 's implicitly zero-extended such as ARM ldrb / ldrh or because it 's folded such as X86 zero-extending loads ) .


<s> bool M68kRegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> bool BPFIRPeephole :: runOnFunction ( Function & F ) { return BPFIRPeepholeImpl ( F ) ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> unsigned X86InstrInfo :: isStoreToStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { unsigned Dummy ; if ( isFrameStoreOpcode ( MI . getOpcode ( ) , Dummy ) ) { unsigned Reg ; if ( ( Reg = isStoreToStackSlot ( MI , FrameIndex ) ) ) return Reg ; const MachineMemOperand * Dummy ; return hasStoreToStackSlot ( MI , Dummy , FrameIndex ) ; } return 0 ; } </s>

isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s> bool GCNPassConfig :: addInstSelector ( ) { AMDGPUPassConfig :: addInstSelector ( ) ; addPass ( & SIFixSGPRCopiesID ) ; addPass ( createSILowerI1CopiesPass ( ) ) ; addPass ( createSIFixupVectorISelPass ( ) ) ; addPass ( createSIAddIMGInitPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s>
static
void
r10k_insert_cache_barriers
(
void
)
{
int
*
rev_post_order
;
unsigned
int
i
,
n
;
basic_block
bb
;
sbitmap
protected_bbs
;
rtx_insn
*
insn
,
*
end
;
rtx
unprotected_region
;
if
(
TARGET_MIPS16
)
{
sorry
(
"%qs does not support MIPS16 code"
,
"-mr10k-cache-barrier"
)
;
return
;
}
calculate_dominance_info
(
CDI_DOMINATORS
)
;
protected_bbs
=
sbitmap_alloc
(
last_basic_block_for_fn
(
cfun
)
)
;
bitmap_clear
(
protected_bbs
)
;
rev_post_order
=
XNEWVEC
(
int
,
last_basic_block_for_fn
(
cfun
)
)
;
n
=
pre_and_rev_post_order_compute
(
,
rev_post_order
,
false
)
;
for
(
i
=
0
;
i
<
n
;
i
++
)
{
bb
=
BASIC_BLOCK_FOR_FN
(
cfun
,
rev_post_order
[
i
]
)
;
if
(
r10k_protected_bb_p
(
bb
,
protected_bbs
)
)
unprotected_region
=
NULL_RTX
;
else
unprotected_region
=
pc_rtx
;
end
=
NEXT_INSN
(
BB_END
(
bb
)
)
;
for
(
insn
=
BB_HEAD
(
bb
)
;
insn
!=
end
;
insn
=
NEXT_INSN
(
insn
)
)
{
if
(
unprotected_region
&&
USEFUL_INSN_P
(
insn
)
)
{
if
(
recog_memoized
(
insn
)
==
CODE_FOR_mips_cache
)
unprotected_region
=
NULL_RTX
;
else
{
if
(
unprotected_region
==
pc_rtx
)
unprotected_region
=
insn
;
if
(
r10k_needs_protection_p
(
insn
)
)
{
emit_insn_before
(
gen_r10k_cache_barrier
(
)
,
unprotected_region
)
;
unprotected_region
=
NULL_RTX
;
}
}
}
if
(
CALL_P
(
insn
)
)
unprotected_region
=
pc_rtx
;
}
if
(
unprotected_region
==
NULL_RTX
)
bitmap_set_bit
(
protected_bbs
,
bb
->
index
)
;
}
XDELETEVEC
(
rev_post_order
)
;
sbitmap_free
(
protected_bbs
)
;
free_dominance_info
(
CDI_DOMINATORS
)
;
}
</s>

Implement -mr10k-cache-barrier= for the current function .


<s> SDValue SystemZTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ZERO_EXTEND : return combineZERO_EXTEND ( N , DCI ) ; case ISD :: SIGN_EXTEND : return combineSIGN_EXTEND ( N , DCI ) ; case ISD :: SIGN_EXTEND_INREG : return combineSIGN_EXTEND_INREG ( N , DCI ) ; case SystemZISD :: MERGE_HIGH : case SystemZISD :: MERGE_LOW : return combineMERGE ( N , DCI ) ; case ISD :: LOAD : return combineLOAD ( N , DCI ) ; case ISD :: STORE : return combineSTORE ( N , DCI ) ; case ISD :: VECTOR_SHUFFLE : return combineVECTOR_SHUFFLE ( N , DCI ) ; case ISD :: EXTRACT_VECTOR_ELT : return combineEXTRACT_VECTOR_ELT ( N , DCI ) ; case SystemZISD :: JOIN_DWORDS : return combineJOIN_DWORDS ( N , DCI ) ; case ISD :: STRICT_FP_ROUND : case ISD :: FP_ROUND : return combineFP_ROUND ( N , DCI ) ; case ISD :: STRICT_FP_EXTEND : case ISD :: FP_EXTEND : return combineFP_EXTEND ( N , DCI ) ; case ISD :: SINT_TO_FP : case ISD :: UINT_TO_FP : return combineINT_TO_FP ( N , DCI ) ; case ISD :: BSWAP : return combineBSWAP ( N , DCI ) ; case SystemZISD :: BR_CCMASK : return combineBR_CCMASK ( N , DCI ) ; case SystemZISD :: SELECT_CCMASK : return combineSELECT_CCMASK ( N , DCI ) ; case SystemZISD :: GET_CCMASK : return combineGET_CCMASK ( N , DCI ) ; case ISD :: SDIV : case ISD :: UDIV : case ISD :: SREM : case ISD :: UREM : return combineIntDIVREM ( N , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemmove ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { return EmitSpecializedLibcall ( DAG , dl , Chain , Dst , Src , Size , Align , RTLIB :: MEMMOVE ) ; } </s>

Emit target-specific code that performs a memmove .


<s> bool MipsAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & TM . getSubtarget < MipsSubtarget > ( ) ; const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; if ( Subtarget -> inMips16Mode ( ) ) for ( std :: map < const char * , const llvm :: Mips16HardFloatInfo :: FuncSignature * > :: const_iterator it = MipsFI -> StubsNeeded . begin ( ) ; it != MipsFI -> StubsNeeded . end ( ) ; ++ it ) { const char * Symbol = it -> first ; const llvm :: Mips16HardFloatInfo :: FuncSignature * Signature = it -> second ; if ( StubsNeeded . find ( Symbol ) == StubsNeeded . end ( ) ) StubsNeeded [ Symbol ] = Signature ; } MCP = MF . getConstantPool ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) NaClAlignIndirectJumpTargets ( MF ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>

Mips Mips Mips Mips Mips Mips Mips16HardFloatInfo::FuncSignature Mips Mips Mips16HardFloatInfo::FuncSignature


<s> void Tile64FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const { const TargetInstrInfo * TII = MF . getTarget ( ) . getInstrInfo ( ) ; const Tile64RegisterInfo * TRI = static_cast < const Tile64RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; Tile64MachineFunctionInfo * FuncInfo = MF . getInfo < Tile64MachineFunctionInfo > ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; bool hasCalls = MFI -> hasCalls ( ) ; unsigned Offset = FuncInfo -> getArgAreaOffset ( ) + MFI -> getMaxCallFrameSize ( ) ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { MachineBasicBlock & MBB = * I ; for ( MachineBasicBlock :: iterator II = MBB . begin ( ) , IE = MBB . end ( ) ; II != IE ; ++ II ) { MachineInstr * MI = & * II ; if ( MI -> getOpcode ( ) == T64 :: NEWSLOT_ADDR ) { DebugLoc DL = MI -> getDebugLoc ( ) ; MachineBasicBlock :: iterator MBBI ( MI ) ; unsigned Dest = MI -> getOperand ( 0 ) . getReg ( ) ; unsigned Src = MI -> getOperand ( 1 ) . getReg ( ) ; if ( hasCalls ) { TRI -> addOffset ( MBB , MBBI , DL , Dest , Src , Offset ) ; } else { BuildMI ( MBB , MBBI , DL , TII -> get ( T64 :: MOVE ) , Dest ) . addReg ( Src ) ; } ++ II ; MI -> eraseFromParent ( ) ; -- II ; } } } } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> static tree arm_get_cookie_size ( tree type ) { tree size ; if ( ! TARGET_AAPCS_BASED ) return default_cxx_get_cookie_size ( type ) ; size = build_int_cst ( sizetype , 8 ) ; return size ; } </s>

The EABI specifies that all array cookies are 8 bytes long .


<s> bool SystemZInstrInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; SystemZMachineFunctionInfo * MFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; unsigned CalleeFrameSize = 0 ; unsigned LowReg = 0 , HighReg = 0 , StartOffset = - 1U , EndOffset = 0 ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; const TargetRegisterClass * RegClass = CSI [ i ] . getRegClass ( ) ; if ( RegClass != & SystemZ :: FP64RegClass ) { unsigned Offset = RegSpillOffsets [ Reg ] ; CalleeFrameSize += 8 ; if ( StartOffset > Offset ) { LowReg = Reg ; StartOffset = Offset ; } if ( EndOffset < Offset ) { HighReg = Reg ; EndOffset = RegSpillOffsets [ Reg ] ; } } } MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ; MFI -> setLowReg ( LowReg ) ; MFI -> setHighReg ( HighReg ) ; if ( StartOffset ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( ( LowReg == HighReg ? SystemZ :: MOV64mr : SystemZ :: MOV64mrm ) ) ) ; MIB . addReg ( SystemZ :: R15D ) . addImm ( StartOffset ) ; if ( LowReg == HighReg ) MIB . addReg ( 0 ) ; MIB . addReg ( LowReg , RegState :: Kill ) ; if ( LowReg != HighReg ) MIB . addReg ( HighReg , RegState :: Kill ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; if ( Reg != LowReg && Reg != HighReg ) MIB . addReg ( Reg , RegState :: ImplicitKill ) ; } } for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; const TargetRegisterClass * RegClass = CSI [ i ] . getRegClass ( ) ; if ( RegClass == & SystemZ :: FP64RegClass ) { MBB . addLiveIn ( Reg ) ; storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i ] . getFrameIdx ( ) , RegClass ) ; } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s>
void
SystemZPostRASchedStrategy
::
schedNode
(
SUnit
*
SU
,
bool
IsTopNode
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"** Scheduling SU("
<<
SU
->
NodeNum
<<
") "
;
if
(
Available
.
size
(
)
==
1
)
dbgs
(
)
<<
"(only one) "
;
Candidate
c
(
SU
,
*
HazardRec
)
;
c
.
dumpCosts
(
)
;
dbgs
(
)
<<
"\n"
;
)
;
Available
.
erase
(
SU
)
;
HazardRec
->
EmitInstruction
(
SU
)
;
}
</s>

ScheduleDAGMI has scheduled an instruction - tell HazardRec about it .

SystemZ
SystemZ
"** Scheduling SU("
") "
1
"(only one) "
"\n"


<s> bool HexagonTargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( Kind . isBSS ( ) || Kind . isDataNoRel ( ) || Kind . isCommon ( ) ) { Type * Ty = GV -> getType ( ) -> getElementType ( ) ; return IsInSmallSection ( TM . getDataLayout ( ) -> getTypeAllocSize ( Ty ) ) ; } return false ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> const MCExpr * getSubExpr ( ) const { return SubExpr ; } </s>

getSubExpr - Get the child of this expression .


<s> Optional < uint64_t > ARMMCInstrAnalysis :: evaluateMemoryOperandAddress ( const MCInst & Inst , const MCSubtargetInfo * STI , uint64_t Addr , uint64_t Size ) const { const MCInstrDesc & Desc = Info -> get ( Inst . getOpcode ( ) ) ; if ( ! Desc . mayLoad ( ) ) return None ; uint64_t TSFlags = Desc . TSFlags ; unsigned IndexMode = ( TSFlags & ARMII :: IndexModeMask ) >> ARMII :: IndexModeShift ; if ( IndexMode != ARMII :: IndexModeNone ) return None ; unsigned OpIndex = Desc . NumDefs ; while ( OpIndex < Desc . getNumOperands ( ) && Desc . OpInfo [ OpIndex ] . OperandType != MCOI :: OPERAND_MEMORY ) ++ OpIndex ; if ( OpIndex == Desc . getNumOperands ( ) ) return None ; Addr &= ~ 0x3 ; switch ( Desc . TSFlags & ARMII :: FormMask ) { default : Addr += 8 ; break ; case ARMII :: ThumbFrm : Addr += 4 ; break ; case ARMII :: VFPLdStFrm : Addr += STI -> getFeatureBits ( ) [ ARM :: ModeThumb ] ? 4 : 8 ; break ; } unsigned AddrMode = ( TSFlags & ARMII :: AddrModeMask ) ; switch ( AddrMode ) { default : return None ; case ARMII :: AddrMode_i12 : return evaluateMemOpAddrForAddrMode_i12 ( Inst , Desc , OpIndex , Addr ) ; case ARMII :: AddrMode3 : return evaluateMemOpAddrForAddrMode3 ( Inst , Desc , OpIndex , Addr ) ; case ARMII :: AddrMode5 : return evaluateMemOpAddrForAddrMode5 ( Inst , Desc , OpIndex , Addr ) ; case ARMII :: AddrMode5FP16 : return evaluateMemOpAddrForAddrMode5FP16 ( Inst , Desc , OpIndex , Addr ) ; case ARMII :: AddrModeT2_i8s4 : return evaluateMemOpAddrForAddrModeT2_i8s4 ( Inst , Desc , OpIndex , Addr ) ; case ARMII :: AddrModeT2_pc : return evaluateMemOpAddrForAddrModeT2_pc ( Inst , Desc , OpIndex , Addr ) ; case ARMII :: AddrModeT1_s : return evaluateMemOpAddrForAddrModeT1_s ( Inst , Desc , OpIndex , Addr ) ; } } </s>

Given an instruction tries to get the address of a memory operand .


<s> static void cr16_conditional_register_usage ( void ) { if ( flag_pic ) { fixed_regs [ 12 ] = call_used_regs [ 12 ] = 1 ; } } </s>

Implements the macro TARGET_CONDITIONAL_REGISTER_USAGE .


<s> static bool returning_call_p ( rtx_insn * insn ) { if ( CALL_P ( insn ) ) return ( ! SIBLING_CALL_P ( insn ) && get_attr_type ( insn ) != TYPE_CALLP && get_attr_type ( insn ) != TYPE_SHADOW ) ; if ( recog_memoized ( insn ) < 0 ) return false ; if ( get_attr_type ( insn ) == TYPE_CALL ) return true ; return false ; } </s>

Determine whether INSN is a call that needs to have a return label placed .


<s> bool AArch64TargetLowering :: isVectorLoadExtDesirable ( SDValue ExtVal ) const { if ( ExtVal . getValueType ( ) . isScalableVector ( ) ) return true ; return false ; } </s>

Return true if folding a vector load into ExtVal ( a sign , zero , or any extend node ) is profitable .


<s> static int rs6000_variable_issue_1 ( rtx_insn * insn , int more ) { last_scheduled_insn = insn ; if ( GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) { cached_can_issue_more = more ; return cached_can_issue_more ; } if ( insn_terminates_group_p ( insn , current_group ) ) { cached_can_issue_more = 0 ; return cached_can_issue_more ; } if ( recog_memoized ( insn ) < 0 ) return more ; if ( rs6000_sched_groups ) { if ( is_microcoded_insn ( insn ) ) cached_can_issue_more = 0 ; else if ( is_cracked_insn ( insn ) ) cached_can_issue_more = more > 2 ? more - 2 : 0 ; else cached_can_issue_more = more - 1 ; return cached_can_issue_more ; } if ( rs6000_tune == PROCESSOR_CELL && is_nonpipeline_insn ( insn ) ) return 0 ; cached_can_issue_more = more - 1 ; return cached_can_issue_more ; } </s>

Power4 load update and store update instructions are cracked into a load or store and an integer insn which are executed in the same cycle . Branches have their own dispatch slot which does not count against the GCC issue rate , but it changes the program flow so there are no other instructions to issue in this cycle .


<s> bool mips_can_use_return_insn ( void ) { if ( cfun -> machine -> interrupt_handler_p ) return false ; if ( ! reload_completed ) return false ; if ( crtl -> profile ) return false ; if ( mips16_cfun_returns_in_fpr_p ( ) ) return false ; return ( cfun -> machine -> frame . total_size == 0 && ! cfun -> machine -> use_frame_header_for_callee_saved_regs ) ; } </s>

Return nonzero if this function is known to have a null epilogue . This allows the optimizer to omit jumps to jumps if no stack was created .


A helper function to handle isr stuff at the end of asm file .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
Kind
==
Register
&&
"Invalid type access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s> bool PPCInstrInfo :: findCommutedOpIndices ( MachineInstr * MI , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { int AltOpc = PPC :: getAltVSXFMAOpcode ( MI -> getOpcode ( ) ) ; if ( AltOpc == - 1 ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , 2 , 3 ) ; } </s>

Returns true iff the routine could find two commutable operands in the given machine instruction .


<s> MCSection * RISCVELFTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , Align & Alignment ) const { if ( isConstantInSmallSection ( DL , C ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: getSectionForConstant ( DL , Kind , C , Alignment ) ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> bool HexagonInstrInfo :: isExtended ( const MachineInstr & MI ) const { const uint64_t F = MI . getDesc ( ) . TSFlags ; if ( ( F >> HexagonII :: ExtendedPos ) & HexagonII :: ExtendedMask ) return true ; for ( const MachineOperand & MO : MI . operands ( ) ) if ( MO . getTargetFlags ( ) & HexagonII :: HMOTF_ConstExtended ) return true ; return false ; } </s>

Test if the given EVT is extended ( as opposed to being simple ) .

Hexagon Hexagon HexagonII::ExtendedPos HexagonII::ExtendedMask HexagonII::HMOTF_ConstExtended


<s> outliner :: InstrType RISCVInstrInfo :: getOutliningType ( MachineBasicBlock :: iterator & MBBI , unsigned Flags ) const { MachineInstr & MI = * MBBI ; MachineBasicBlock * MBB = MI . getParent ( ) ; const TargetRegisterInfo * TRI = MBB -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; if ( MI . isPosition ( ) ) { if ( MI . isCFIInstruction ( ) ) return outliner :: InstrType :: Invisible ; return outliner :: InstrType :: Illegal ; } if ( MI . isInlineAsm ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . isTerminator ( ) && ! MBB -> succ_empty ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . isReturn ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . modifiesRegister ( RISCV :: X5 , TRI ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( RISCV :: X5 ) ) return outliner :: InstrType :: Illegal ; for ( const auto & MO : MI . operands ( ) ) if ( MO . isMBB ( ) || MO . isBlockAddress ( ) || MO . isCPI ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . isMetaInstruction ( ) ) return outliner :: InstrType :: Invisible ; return outliner :: InstrType :: Legal ; } </s>

Returns how or if MIT should be outlined .


<s> inline Predicate getPredicate ( unsigned Condition , unsigned Hint ) { return ( Predicate ) ( ( Condition & ~ BR_HINT_MASK ) | ( Hint & BR_HINT_MASK ) ) ; } </s>

Returns the comparison predicate underlying the intrinsic .


<s> rtx sh_function_arg ( CUMULATIVE_ARGS * ca , enum machine_mode mode , tree type , int named ) { if ( ! TARGET_SH5 && mode == VOIDmode ) return GEN_INT ( ca -> renesas_abi ? 1 : 0 ) ; if ( ! TARGET_SH5 && PASS_IN_REG_P ( * ca , mode , type ) && ( named || ! ( TARGET_HITACHI || ca -> renesas_abi ) ) ) { int regno ; if ( mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN && ( ! FUNCTION_ARG_SCmode_WART || ( ROUND_REG ( * ca , mode ) & 1 ) ) ) { rtx r1 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SFmode , BASE_ARG_REG ( mode ) + ( ROUND_REG ( * ca , mode ) ^ 1 ) ) , const0_rtx ) ; rtx r2 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SFmode , BASE_ARG_REG ( mode ) + ( ( ROUND_REG ( * ca , mode ) + 1 ) ^ 1 ) ) , GEN_INT ( 4 ) ) ; return gen_rtx_PARALLEL ( SCmode , gen_rtvec ( 2 , r1 , r2 ) ) ; } if ( ( TARGET_HITACHI || ca -> renesas_abi ) && ca -> free_single_fp_reg && mode == SFmode ) return gen_rtx_REG ( mode , ca -> free_single_fp_reg ) ; regno = ( BASE_ARG_REG ( mode ) + ROUND_REG ( * ca , mode ) ) ^ ( mode == SFmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN != 0 && ! TARGET_HITACHI && ! ca -> renesas_abi ) ; return gen_rtx_REG ( mode , regno ) ; } if ( TARGET_SH5 ) { if ( mode == VOIDmode && TARGET_SHCOMPACT ) return GEN_INT ( ca -> call_cookie ) ; if ( mode == SFmode && ca -> free_single_fp_reg ) return SH5_PROTOTYPED_FLOAT_ARG ( * ca , mode , ca -> free_single_fp_reg ) ; if ( ( GET_SH_ARG_CLASS ( mode ) == SH_ARG_FLOAT ) && ( named || ! ca -> prototype_p ) && ca -> arg_count [ ( int ) SH_ARG_FLOAT ] < NPARM_REGS ( SFmode ) ) { if ( ! ca -> prototype_p && TARGET_SHMEDIA ) return SH5_PROTOTYPELESS_FLOAT_ARG ( * ca , mode ) ; return SH5_PROTOTYPED_FLOAT_ARG ( * ca , mode , FIRST_FP_PARM_REG + ca -> arg_count [ ( int ) SH_ARG_FLOAT ] ) ; } if ( ca -> arg_count [ ( int ) SH_ARG_INT ] < NPARM_REGS ( SImode ) && ( ! TARGET_SHCOMPACT || ( ! SHCOMPACT_FORCE_ON_STACK ( mode , type ) && ! SH5_WOULD_BE_PARTIAL_NREGS ( * ca , mode , type , named ) ) ) ) { return gen_rtx_REG ( mode , ( FIRST_PARM_REG + ca -> arg_count [ ( int ) SH_ARG_INT ] ) ) ; } return 0 ; } return 0 ; } </s>

Define where to put the arguments to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . On SH the first args are normally in registers and the rest are pushed . Any arg that starts within the first NPARM_REGS words is at least partially passed in a register unless its data type forbids .


<s> const MCPhysReg * SystemZRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( MF -> getSubtarget ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF -> getFunction ( ) -> getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_SystemZ_SwiftError_SaveList ; return CSR_SystemZ_SaveList ; } </s>


<s>
bool
PPCDarwinAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
this
->
MF
=
&
MF
;
SetupMachineFunction
(
MF
)
;
O
<<
"\n\n"
;
EmitConstantPool
(
MF
.
getConstantPool
(
)
)
;
const
Function
*
F
=
MF
.
getFunction
(
)
;
SwitchToSection
(
TAI
->
SectionForGlobal
(
F
)
)
;
switch
(
F
->
getLinkage
(
)
)
{
default
:
assert
(
0
&&
"Unknown linkage type!"
)
;
case
Function
::
PrivateLinkage
:
case
Function
::
InternalLinkage
:
break
;
case
Function
::
ExternalLinkage
:
O
<<
"\t.globl\t"
<<
CurrentFnName
<<
'\n'
;
break
;
case
Function
::
WeakAnyLinkage
:
case
Function
::
WeakODRLinkage
:
case
Function
::
LinkOnceAnyLinkage
:
case
Function
::
LinkOnceODRLinkage
:
O
<<
"\t.globl\t"
<<
CurrentFnName
<<
'\n'
;
O
<<
"\t.weak_definition\t"
<<
CurrentFnName
<<
'\n'
;
break
;
}
printVisibility
(
CurrentFnName
,
F
->
getVisibility
(
)
)
;
EmitAlignment
(
F
->
hasFnAttr
(
Attribute
::
OptimizeForSize
)
2
:
4
,
F
)
;
O
<<
CurrentFnName
<<
":\n"
;
DW
->
BeginFunction
(
&
MF
)
;
MachineFunction
::
iterator
I
=
MF
.
begin
(
)
;
if
(
++
I
==
MF
.
end
(
)
&&
MF
.
front
(
)
.
empty
(
)
)
O
<<
"\tnop\n"
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
I
!=
MF
.
begin
(
)
)
{
printBasicBlockLabel
(
I
,
true
,
true
,
VerboseAsm
)
;
O
<<
'\n'
;
}
for
(
MachineBasicBlock
::
const_iterator
II
=
I
->
begin
(
)
,
IE
=
I
->
end
(
)
;
II
!=
IE
;
++
II
)
{
printMachineInstruction
(
II
)
;
}
}
EmitJumpTableInfo
(
MF
.
getJumpTableInfo
(
)
,
MF
)
;
DW
->
EndFunction
(
&
MF
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> int avr_simple_epilogue ( void ) { return ( ! frame_pointer_needed && get_frame_size ( ) == 0 && avr_outgoing_args_size ( ) == 0 && avr_regs_to_save ( NULL ) == 0 && ! cfun -> machine -> is_interrupt && ! cfun -> machine -> is_signal && ! cfun -> machine -> is_naked && ! TREE_THIS_VOLATILE ( current_function_decl ) ) ; } </s>

Return 1 if the function epilogue is just a single `` ret '' .


<s> bool sh_hard_regno_rename_ok ( unsigned int old_reg ATTRIBUTE_UNUSED , unsigned int new_reg ) { if ( sh_cfun_interrupt_handler_p ( ) && ! df_regs_ever_live_p ( new_reg ) ) return false ; return true ; } </s>

Return nonzero if register old_reg can be renamed to register new_reg .


<s> static int alpha_multipass_dfa_lookahead ( void ) { return ( alpha_tune == PROCESSOR_EV6 ? 4 : 2 ) ; } </s>

How many alternative schedules to try . This should be as wide as the scheduling freedom in the DFA , but no wider . Making this value too large results extra work for the scheduler . For EV4 , loads can be issued to either IB0 or IB1 , thus we have 2 alternative schedules . For EV5 , we can choose between E0/E1 and FA/FM . For EV6 , an arithmetic insn can be issued to U0/U1/L0/L1 .


<s> bool MipsTargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const MipsSubtarget & Subtarget = TM . getSubtarget < MipsSubtarget > ( ) ; if ( ! Subtarget . useSmallSection ( ) ) return false ; if ( Subtarget . isTargetNaCl ( ) ) return false ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ; if ( Kind . isMergeable1ByteCString ( ) ) return false ; Type * Ty = GV -> getType ( ) -> getElementType ( ) ; return IsInSmallSection ( TM . getDataLayout ( ) -> getTypeAllocSize ( Ty ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> unsigned HexagonTTIImpl :: getCallInstrCost ( Function * F , Type * RetTy , ArrayRef < Type * > Tys ) { return BaseT :: getCallInstrCost ( F , RetTy , Tys ) ; } </s>

Compute a cost of the given call instruction .


<s> void UPTInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , get ( UPT :: LDR ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> static struct machine_function * ix86_init_machine_status ( void ) { struct machine_function * f ; f = ggc_alloc_cleared ( sizeof ( struct machine_function ) ) ; f -> use_fast_prologue_epilogue_nregs = - 1 ; return f ; } </s>

Clear stack slot assignments remembered from previous functions . This is called from INIT_EXPANDERS once before RTL is emitted for each function .


initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


"Replace loads/stores with library calls"

getPassName - Return a nice clean name for a pass .


"instruction requires a CPU feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s>
char
*
aarch64_output_simd_mov_immediate
(
rtx
const_vector
,
machine_mode
mode
,
unsigned
width
)
{
bool
is_valid
;
static
char
templ
[
40
]
;
const
char
*
mnemonic
;
const
char
*
shift_op
;
unsigned
int
lane_count
=
0
;
char
element_char
;
struct
simd_immediate_info
info
=
{
NULL_RTX
,
0
,
0
,
false
,
false
}
;
is_valid
=
aarch64_simd_valid_immediate
(
const_vector
,
mode
,
false
,
&
info
)
;
gcc_assert
(
is_valid
)
;
element_char
=
sizetochar
(
info
.
element_width
)
;
lane_count
=
width
/
info
.
element_width
;
mode
=
GET_MODE_INNER
(
mode
)
;
if
(
mode
==
SFmode
||
mode
==
DFmode
)
{
gcc_assert
(
info
.
shift
==
0
&&
!
info
.
mvn
)
;
if
(
aarch64_float_const_zero_rtx_p
(
info
.
value
)
)
info
.
value
=
GEN_INT
(
0
)
;
else
{
REAL_VALUE_TYPE
r
;
REAL_VALUE_FROM_CONST_DOUBLE
(
r
,
info
.
value
)
;
char
float_buf
[
buf_size
]
=
{
'\0'
}
;
real_to_decimal_for_mode
(
float_buf
,
&
r
,
buf_size
,
buf_size
,
1
,
mode
)
;
if
(
lane_count
==
1
)
snprintf
(
templ
,
sizeof
(
templ
)
,
"fmov\t%%d0, %s"
,
float_buf
)
;
else
snprintf
(
templ
,
sizeof
(
templ
)
,
"fmov\t%%0.%d%c, %s"
,
lane_count
,
element_char
,
float_buf
)
;
return
templ
;
}
}
mnemonic
=
info
.
mvn
"mvni"
:
"movi"
;
shift_op
=
info
.
msl
"msl"
:
"lsl"
;
if
(
lane_count
==
1
)
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%d0, "
HOST_WIDE_INT_PRINT_HEX
,
mnemonic
,
UINTVAL
(
info
.
value
)
)
;
else
if
(
info
.
shift
)
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%0.%d%c, "
HOST_WIDE_INT_PRINT_HEX
", %s %d"
,
mnemonic
,
lane_count
,
element_char
,
UINTVAL
(
info
.
value
)
,
shift_op
,
info
.
shift
)
;
else
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%0.%d%c, "
HOST_WIDE_INT_PRINT_HEX
,
mnemonic
,
lane_count
,
element_char
,
UINTVAL
(
info
.
value
)
)
;
return
templ
;
}
</s>

Returns the string with the instruction for AdvSIMD MOVI , MVNI , ORR or BIC immediate with a CONST_VECTOR of MODE and WIDTH . WHICH selects whether to output MOVI/MVNI , ORR or BIC immediate .


<s> static unsigned int ix86_compat_function_arg_boundary ( machine_mode mode , const_tree type , unsigned int align ) { if ( ! TARGET_64BIT && mode != TDmode && mode != TFmode ) { if ( ! type ) { if ( ! ( TARGET_SSE && SSE_REG_MODE_P ( mode ) ) ) align = PARM_BOUNDARY ; } else { if ( ! ix86_compat_aligned_value_p ( type ) ) align = PARM_BOUNDARY ; } } if ( align > BIGGEST_ALIGNMENT ) align = BIGGEST_ALIGNMENT ; return align ; } </s>

Return the alignment boundary for MODE and TYPE with alignment ALIGN . XXX : This function is obsolete and is only used for checking psABI compatibility with previous versions of GCC .


"interrupt Service Routines cannot be coded in Thumb mode"

Generate the rest of a function 's prologue .


<s> static const char * shift_op ( rtx op , HOST_WIDE_INT * amountp ) { const char * mnem ; enum rtx_code code = GET_CODE ( op ) ; switch ( GET_CODE ( XEXP ( op , 1 ) ) ) { case REG : case SUBREG : * amountp = - 1 ; break ; case CONST_INT : * amountp = INTVAL ( XEXP ( op , 1 ) ) ; break ; default : gcc_unreachable ( ) ; } switch ( code ) { case ASHIFT : mnem = "asl" ; break ; case ASHIFTRT : mnem = "asr" ; break ; case LSHIFTRT : mnem = "lsr" ; break ; case ROTATE : gcc_assert ( * amountp != - 1 ) ; * amountp = 32 - * amountp ; case ROTATERT : mnem = "ror" ; break ; case MULT : gcc_assert ( * amountp != - 1 ) ; * amountp = int_log2 ( * amountp ) ; return "asl" ; default : gcc_unreachable ( ) ; } if ( * amountp != - 1 ) { if ( code == ROTATERT ) * amountp &= 31 ; else if ( * amountp != ( * amountp & 31 ) ) { if ( code == ASHIFT ) mnem = "lsr" ; * amountp = 32 ; } if ( * amountp == 0 ) return NULL ; } return mnem ; } </s>

Ensure valid constant shifts and return the appropriate shift mnemonic for the operation code . The returned result should not be overwritten . OP is the rtx code of the shift . On exit , * AMOUNTP will be -1 if the shift is by a register , or a constant shift .


<s> static inline HOST_WIDE_INT htm_spr_regno ( enum rs6000_builtins code ) { if ( code == HTM_BUILTIN_GET_TFHAR || code == HTM_BUILTIN_SET_TFHAR ) return TFHAR_REGNO ; else if ( code == HTM_BUILTIN_GET_TFIAR || code == HTM_BUILTIN_SET_TFIAR ) return TFIAR_REGNO ; gcc_assert ( code == HTM_BUILTIN_GET_TEXASR || code == HTM_BUILTIN_SET_TEXASR || code == HTM_BUILTIN_GET_TEXASRU || code == HTM_BUILTIN_SET_TEXASRU ) ; return TEXASR_REGNO ; } </s>

Return the appropriate SPR regno associated with the given builtin .


<s> static void do_load_for_compare ( rtx reg , rtx mem , machine_mode mode ) { switch ( GET_MODE ( reg ) ) { case E_DImode : switch ( mode ) { case E_QImode : emit_insn ( gen_zero_extendqidi2 ( reg , mem ) ) ; break ; case E_HImode : { rtx src = mem ; if ( ! BYTES_BIG_ENDIAN ) { src = gen_reg_rtx ( HImode ) ; emit_insn ( gen_bswaphi2 ( src , mem ) ) ; } emit_insn ( gen_zero_extendhidi2 ( reg , src ) ) ; break ; } case E_SImode : { rtx src = mem ; if ( ! BYTES_BIG_ENDIAN ) { src = gen_reg_rtx ( SImode ) ; emit_insn ( gen_bswapsi2 ( src , mem ) ) ; } emit_insn ( gen_zero_extendsidi2 ( reg , src ) ) ; } break ; case E_DImode : if ( ! BYTES_BIG_ENDIAN ) emit_insn ( gen_bswapdi2 ( reg , mem ) ) ; else emit_insn ( gen_movdi ( reg , mem ) ) ; break ; default : gcc_unreachable ( ) ; } break ; case E_SImode : switch ( mode ) { case E_QImode : emit_insn ( gen_zero_extendqisi2 ( reg , mem ) ) ; break ; case E_HImode : { rtx src = mem ; if ( ! BYTES_BIG_ENDIAN ) { src = gen_reg_rtx ( HImode ) ; emit_insn ( gen_bswaphi2 ( src , mem ) ) ; } emit_insn ( gen_zero_extendhisi2 ( reg , src ) ) ; break ; } case E_SImode : if ( ! BYTES_BIG_ENDIAN ) emit_insn ( gen_bswapsi2 ( reg , mem ) ) ; else emit_insn ( gen_movsi ( reg , mem ) ) ; break ; case E_DImode : gcc_unreachable ( ) ; break ; default : gcc_unreachable ( ) ; } break ; default : gcc_unreachable ( ) ; break ; } } </s>

Figure out the correct instructions to generate to load data for block compare . MODE is used for the read from memory , and data is zero extended if REG is wider than MODE . If LE code is being generated , bswap loads are used . REG is the destination register to move the data into . MEM is the memory block being read . MODE is the mode of memory to use for the read .


<s> bool PPCFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( ! Subtarget . isSVR4ABI ( ) ) return false ; MachineFunction * MF = MBB . getParent ( ) ; const PPCInstrInfo & TII = * static_cast < const PPCInstrInfo * > ( MF -> getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc DL ; bool CRSpilled = false ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsCRField = PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ; if ( CRSpilled && IsCRField ) continue ; MBB . addLiveIn ( Reg ) ; if ( IsCRField ) { CRSpilled = true ; if ( Subtarget . isPPC64 ( ) ) { MBB . insert ( MI , BuildMI ( * MF , DL , TII . get ( PPC :: MFCR ) , PPC :: X12 ) ) ; MBB . insert ( MI , BuildMI ( * MF , DL , TII . get ( PPC :: STW ) ) . addReg ( PPC :: X12 , getKillRegState ( true ) ) . addImm ( 8 ) . addReg ( PPC :: X1 ) ) ; } else { MBB . insert ( MI , BuildMI ( * MF , DL , TII . get ( PPC :: MFCR ) , PPC :: R12 ) ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( PPC :: STW ) ) . addReg ( PPC :: R12 , getKillRegState ( true ) ) , CSI [ i ] . getFrameIdx ( ) ) ) ; } PPCFunctionInfo * FuncInfo = MF -> getInfo < PPCFunctionInfo > ( ) ; FuncInfo -> setSpillsCR ( ) ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static struct constant_pool * s390_mainpool_start ( void ) { struct constant_pool * pool ; rtx insn ; pool = s390_alloc_pool ( ) ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( GET_CODE ( insn ) == INSN && GET_CODE ( PATTERN ( insn ) ) == SET && GET_CODE ( SET_SRC ( PATTERN ( insn ) ) ) == UNSPEC_VOLATILE && XINT ( SET_SRC ( PATTERN ( insn ) ) , 1 ) == UNSPECV_MAIN_POOL ) { gcc_assert ( ! pool -> pool_insn ) ; pool -> pool_insn = insn ; } if ( ! TARGET_CPU_ZARCH && s390_execute_label ( insn ) ) { s390_add_execute ( pool , insn ) ; } else if ( GET_CODE ( insn ) == INSN || GET_CODE ( insn ) == CALL_INSN ) { rtx pool_ref = NULL_RTX ; find_constant_pool_ref ( PATTERN ( insn ) , & pool_ref ) ; if ( pool_ref ) { rtx constant = get_pool_constant ( pool_ref ) ; enum machine_mode mode = get_pool_mode ( pool_ref ) ; s390_add_constant ( pool , constant , mode ) ; } } } gcc_assert ( pool -> pool_insn || pool -> size == 0 ) ; if ( pool -> size >= 4096 ) { remove_insn ( pool -> pool_insn ) ; s390_free_pool ( pool ) ; pool = NULL ; } return pool ; } </s>

Collect main literal pool . Return NULL on overflow .


<s> MipsSubtarget & MipsSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS , const TargetMachine & TM ) { std :: string CPUName = MIPS_MC :: selectMipsCPU ( TM . getTargetTriple ( ) , CPU ) ; ParseSubtargetFeatures ( CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( InMips16Mode && ! IsSoftFloat ) InMips16HardFloat = true ; return * this ; } </s>

Mips Mips Mips MIPS_MC::selectMipsCPU Mips Mips


<s>
unsigned
MipsCodeEmitter
::
getMachineOpValue
(
const
MachineInstr
&
MI
,
const
MachineOperand
&
MO
)
const
{
if
(
MO
.
isReg
(
)
)
return
TM
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
else
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
else
if
(
MO
.
isGlobal
(
)
)
emitGlobalAddress
(
MO
.
getGlobal
(
)
,
getRelocation
(
MI
,
MO
)
,
true
)
;
else
if
(
MO
.
isSymbol
(
)
)
emitExternalSymbolAddress
(
MO
.
getSymbolName
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isCPI
(
)
)
emitConstPoolAddress
(
MO
.
getIndex
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isJTI
(
)
)
emitJumpTableAddress
(
MO
.
getIndex
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isMBB
(
)
)
emitMachineBasicBlock
(
MO
.
getMBB
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
llvm_unreachable
(
"Unable to encode MachineOperand!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .

Mips
Mips
"Unable to encode MachineOperand!"
0


<s> void mips_expand_vec_cond_expr ( machine_mode mode , machine_mode vimode , rtx * operands ) { rtx cond = operands [ 3 ] ; rtx cmp_op0 = operands [ 4 ] ; rtx cmp_op1 = operands [ 5 ] ; rtx cmp_res = gen_reg_rtx ( vimode ) ; mips_expand_msa_cmp ( cmp_res , GET_CODE ( cond ) , cmp_op0 , cmp_op1 ) ; if ( operands [ 1 ] == CONSTM1_RTX ( vimode ) && operands [ 2 ] == CONST0_RTX ( vimode ) ) emit_move_insn ( operands [ 0 ] , cmp_res ) ; else { rtx src1 = gen_reg_rtx ( vimode ) ; rtx src2 = gen_reg_rtx ( vimode ) ; rtx mask = gen_reg_rtx ( vimode ) ; rtx bsel ; emit_move_insn ( mask , cmp_res ) ; if ( register_operand ( operands [ 1 ] , mode ) ) { rtx xop1 = operands [ 1 ] ; if ( mode != vimode ) { xop1 = gen_reg_rtx ( vimode ) ; emit_move_insn ( xop1 , gen_rtx_SUBREG ( vimode , operands [ 1 ] , 0 ) ) ; } emit_move_insn ( src1 , xop1 ) ; } else { gcc_assert ( operands [ 1 ] == CONSTM1_RTX ( vimode ) ) ; emit_move_insn ( src1 , mask ) ; } if ( register_operand ( operands [ 2 ] , mode ) ) { rtx xop2 = operands [ 2 ] ; if ( mode != vimode ) { xop2 = gen_reg_rtx ( vimode ) ; emit_move_insn ( xop2 , gen_rtx_SUBREG ( vimode , operands [ 2 ] , 0 ) ) ; } emit_move_insn ( src2 , xop2 ) ; } else { gcc_assert ( operands [ 2 ] == CONST0_RTX ( mode ) ) ; emit_move_insn ( src2 , mask ) ; } bsel = gen_rtx_IOR ( vimode , gen_rtx_AND ( vimode , gen_rtx_NOT ( vimode , mask ) , src2 ) , gen_rtx_AND ( vimode , mask , src1 ) ) ; emit_insn ( gen_rtx_SET ( mask , bsel ) ) ; emit_move_insn ( operands [ 0 ] , gen_rtx_SUBREG ( mode , mask , 0 ) ) ; } } </s>

Expand VEC_COND_EXPR , where : MODE is mode of the result VIMODE equivalent integer mode OPERANDS operands of VEC_COND_EXPR .


<s> void SICFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; SICFunctionInfo * SICFI = MF . getInfo < SICFunctionInfo > ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( MF . getFrameInfo ( ) -> hasCalls ( ) ) setAliasRegs ( MF , SavedRegs , SIC :: L ) ; return ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


"unexpected argument to %<msp430_select_hwmult_lib%>: %s"

"unexpected first argument to %<msp430_select_hwmult_lib%>: %s"

"%<msp430_select_hwmult_lib%> needs one or more arguments"

Implement spec function ` msp430_hwmult_lib麓 .


<s> void XCoreAsmPrinter :: emitFunctionBodyEnd ( ) { getTargetStreamer ( ) . emitCCBottomFunction ( CurrentFnSym -> getName ( ) ) ; } </s>

Targets can override this to emit stuff after the last basic block in the function .


<s>
bool
AArch64DAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_Q
:
OutOps
.
push_back
(
Op
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> tree xtensa_build_va_list ( void ) { tree f_stk , f_reg , f_ndx , record ; record = make_node ( RECORD_TYPE ) ; f_stk = build_decl ( FIELD_DECL , get_identifier ( "__va_stk" ) , ptr_type_node ) ; f_reg = build_decl ( FIELD_DECL , get_identifier ( "__va_reg" ) , ptr_type_node ) ; f_ndx = build_decl ( FIELD_DECL , get_identifier ( "__va_ndx" ) , integer_type_node ) ; DECL_FIELD_CONTEXT ( f_stk ) = record ; DECL_FIELD_CONTEXT ( f_reg ) = record ; DECL_FIELD_CONTEXT ( f_ndx ) = record ; TYPE_FIELDS ( record ) = f_stk ; TREE_CHAIN ( f_stk ) = f_reg ; TREE_CHAIN ( f_reg ) = f_ndx ; layout_type ( record ) ; return record ; } </s>

Create the va_list data type . This structure is set up by __builtin_saveregs . The __va_reg field points to a stack-allocated region holding the contents of the incoming argument registers . The __va_ndx field is an index initialized to the position of the first unnamed ( variable ) argument . This same index is also used to address the arguments passed in memory . Thus , the __va_stk field is initialized to point to the position of the first argument in memory offset to account for the arguments passed in registers . E.G. , if there are 6 argument registers , and each register is 4 bytes , then __va_stk is set to $ sp - ( 6 * 4 ) ; then __va_reg [ N * 4 ] references argument word N for 0 < = N < 6 , and __va_stk [ N * 4 ] references argument word N for N > = 6 .


<s>
bool
FixupBWInstPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
!
FixupBWInsts
||
skipFunction
(
*
MF
.
getFunction
(
)
)
)
return
false
;
this
->
MF
=
&
MF
;
TII
=
MF
.
getSubtarget
<
X86Subtarget
>
(
)
.
getInstrInfo
(
)
;
OptForSize
=
MF
.
getFunction
(
)
->
optForSize
(
)
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
LiveRegs
.
init
(
TII
->
getRegisterInfo
(
)
)
;
DEBUG
(
dbgs
(
)
<<
"Start X86FixupBWInsts\n"
;
)
;
for
(
auto
&
MBB
:
MF
)
processBasicBlock
(
MF
,
MBB
)
;
DEBUG
(
dbgs
(
)
<<
"End X86FixupBWInsts\n"
;
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> int gr5_hazard_bypass_p ( rtx_insn * out_insn , rtx_insn * in_insn ) { rtx out_set , in_set , dest , memexpr ; unsigned int out_reg , in_reg ; if ( GET_CODE ( out_insn ) == CALL_INSN ) return 0 ; out_set = single_set_and_flags ( out_insn ) ; dest = SET_DEST ( out_set ) ; if ( GET_CODE ( dest ) == MEM ) return 0 ; if ( GET_CODE ( dest ) == STRICT_LOW_PART ) dest = XEXP ( dest , 0 ) ; if ( GET_CODE ( dest ) == SUBREG ) dest = SUBREG_REG ( dest ) ; out_reg = REGNO ( dest ) ; in_set = single_set_and_flags ( in_insn ) ; if ( GET_CODE ( SET_SRC ( in_set ) ) == MEM ) memexpr = XEXP ( SET_SRC ( in_set ) , 0 ) ; else memexpr = XEXP ( SET_DEST ( in_set ) , 0 ) ; if ( GET_CODE ( memexpr ) == PLUS ) { memexpr = XEXP ( memexpr , 0 ) ; if ( GET_CODE ( memexpr ) == SUBREG ) in_reg = REGNO ( SUBREG_REG ( memexpr ) ) ; else in_reg = REGNO ( memexpr ) ; if ( in_reg == out_reg ) return 1 ; } else if ( TARGET_MCM ) { if ( GET_CODE ( memexpr ) == STRICT_LOW_PART ) memexpr = XEXP ( memexpr , 0 ) ; if ( GET_CODE ( memexpr ) == SUBREG ) memexpr = SUBREG_REG ( memexpr ) ; in_reg = REGNO ( memexpr ) ; if ( in_reg == out_reg ) return 1 ; } return 0 ; } </s>

This is called with OUT_INSN an instruction setting a ( base ) register and IN_INSN a read or a write . Return 1 if these instructions together constitute a pipeline hazard . On the original architecture , a pipeline data hazard occurs when the Dest of one instruction becomes the SrcA for an immediately following READ or WRITE instruction with a non-zero index ( indexing occurs at the decode stage and so a NOP must be inserted in-between for this to work ) . An example is : move.l r2 , r1 read.l r4,10 ( r2 ) On the MCM , the non-zero index condition is lifted but the hazard is patched up by the hardware through the injection of wait states : move.l r2 , r1 read.l r4 , ( r2 ) We nevertheless try to schedule instructions around this .


"Invalid number of NOP bytes requested!"

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> bool ARMBaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; return ( RealignStack && ! AFI -> isThumb1OnlyFunction ( ) && ! MFI -> hasVarSizedObjects ( ) ) ; } </s>

True if the stack can be realigned for the target .


<s> ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const override { return createTPCMachineScheduler ( C ) ; } </s>

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level .


<s> static machine_mode ix86_cc_modes_compatible ( machine_mode m1 , machine_mode m2 ) { if ( m1 == m2 ) return m1 ; if ( GET_MODE_CLASS ( m1 ) != MODE_CC || GET_MODE_CLASS ( m2 ) != MODE_CC ) return VOIDmode ; if ( ( m1 == CCGCmode && m2 == CCGOCmode ) || ( m1 == CCGOCmode && m2 == CCGCmode ) ) return CCGCmode ; if ( ( m1 == CCNOmode && m2 == CCGOCmode ) || ( m1 == CCGOCmode && m2 == CCNOmode ) ) return CCNOmode ; if ( m1 == CCZmode && ( m2 == CCGCmode || m2 == CCGOCmode || m2 == CCNOmode ) ) return m2 ; else if ( m2 == CCZmode && ( m1 == CCGCmode || m1 == CCGOCmode || m1 == CCNOmode ) ) return m1 ; switch ( m1 ) { default : gcc_unreachable ( ) ; case E_CCmode : case E_CCGCmode : case E_CCGOCmode : case E_CCNOmode : case E_CCAmode : case E_CCCmode : case E_CCOmode : case E_CCPmode : case E_CCSmode : case E_CCZmode : switch ( m2 ) { default : return VOIDmode ; case E_CCmode : case E_CCGCmode : case E_CCGOCmode : case E_CCNOmode : case E_CCAmode : case E_CCCmode : case E_CCOmode : case E_CCPmode : case E_CCSmode : case E_CCZmode : return CCmode ; } case E_CCFPmode : return VOIDmode ; } } </s>

If two condition code modes are compatible , return a condition code mode which is compatible with both . Otherwise , return VOIDmode .


<s> void X86PassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( new X86ExecutionDomainFix ( ) ) ; addPass ( createBreakFalseDeps ( ) ) ; } addPass ( createShadowCallStackPass ( ) ) ; addPass ( createX86IndirectBranchTrackingPass ( ) ) ; if ( UseVZeroUpper ) addPass ( createX86IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86FixupBWInsts ( ) ) ; addPass ( createX86PadShortFunctions ( ) ) ; addPass ( createX86FixupLEAs ( ) ) ; addPass ( createX86EvexToVexInsts ( ) ) ; } } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> unsigned XCoreRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? XCore :: R10 : XCore :: SP ; } </s>


<s> void AMDGPUSymbolizer :: tryAddingPcLoadReferenceComment ( raw_ostream & cStream , int64_t Value , uint64_t Address ) { llvm_unreachable ( "unimplemented" ) ; } </s>

Try to add a comment on the PC-relative load .


<s> SDValue PPCTargetLowering :: LowerCall ( SDValue Chain , SDValue Callee , CallingConv :: ID CallConv , bool isVarArg , bool & isTailCall , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { if ( isTailCall ) isTailCall = IsEligibleForTailCallOptimization ( Callee , CallConv , isVarArg , Ins , DAG ) ; if ( PPCSubTarget . isSVR4ABI ( ) && ! PPCSubTarget . isPPC64 ( ) ) { return LowerCall_SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , Ins , dl , DAG , InVals ) ; } else { return LowerCall_Darwin ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , Ins , dl , DAG , InVals ) ; } } </s>

This hook must be implemented to lower calls into the specified DAG .

PowerPC PPC ISD::OutputArg ISD::InputArg PPC PPC PPC


<s> void MipsSEFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned BP = ABI . IsN64 ( ) ? Mips :: S7_64 : Mips :: S7 ; if ( hasFP ( MF ) ) setAliasRegs ( MF , SavedRegs , FP ) ; if ( hasBP ( MF ) ) setAliasRegs ( MF , SavedRegs , BP ) ; if ( MipsFI -> callsEhReturn ( ) ) MipsFI -> createEhDataRegsFI ( ) ; if ( MipsFI -> isISR ( ) ) MipsFI -> createISRRegFI ( ) ; if ( ExpandPseudo ( MF ) . expand ( ) ) { const TargetRegisterClass & RC = STI . hasMips64 ( ) ? Mips :: GPR64RegClass : Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlignment ( RC ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } uint64_t MaxSPOffset = MF . getInfo < MipsFunctionInfo > ( ) -> getIncomingArgSize ( ) + estimateStackSize ( MF ) ; if ( isInt < 16 > ( MaxSPOffset ) ) return ; const TargetRegisterClass & RC = ABI . ArePtrs64bit ( ) ? Mips :: GPR64RegClass : Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlignment ( RC ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } </s>


<s> static rtx riscv_force_address ( rtx x , enum machine_mode mode ) { if ( ! riscv_legitimate_address_p ( mode , x , false ) ) x = force_reg ( Pmode , x ) ; return x ; } </s>

If X is not a valid address for mode MODE , force it into a register .


<s> bool BlackfinFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return DisableFramePointerElim ( MF ) || MFI -> adjustsStack ( ) || MFI -> hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void tilegx_cpu_cpp_builtins ( struct cpp_reader * pfile ) { builtin_define ( "__tile__" ) ; builtin_define ( "__tilegx__" ) ; builtin_define ( "__tile_chip__=10" ) ; builtin_define ( "__tile_chip_rev__=0" ) ; builtin_assert ( "cpu=tilegx" ) ; builtin_assert ( "machine=tilegx" ) ; if ( TARGET_32BIT ) builtin_define ( "__tilegx32__" ) ; builtin_define ( "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1" ) ; builtin_define ( "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2" ) ; TILEGX_CPU_CPP_ENDIAN_BUILTINS ( ) ; GNU_USER_TARGET_OS_CPP_BUILTINS ( ) ; } </s>


<s>
static
bool
symbian_class_needs_attribute_p
(
tree
ctype
,
const
char
*
attribute_name
)
{
VEC
(
tree
,
gc
)
*
method_vec
;
method_vec
=
CLASSTYPE_METHOD_VEC
(
ctype
)
;
if
(
TYPE_POLYMORPHIC_P
(
ctype
)
&&
method_vec
&&
lookup_attribute
(
attribute_name
,
DECL_ATTRIBUTES
(
VEC_index
(
tree
,
method_vec
,
0
)
)
)
)
return
true
;
if
(
TREE_CODE
(
ctype
)
==
RECORD_TYPE
)
{
unsigned
int
len
;
len
=
method_vec
VEC_length
(
tree
,
method_vec
)
:
0
;
for
(
;
len
;
)
{
tree
member
=
VEC_index
(
tree
,
method_vec
,
len
)
;
if
(
!
member
)
continue
;
for
(
member
=
OVL_CURRENT
(
member
)
;
member
;
member
=
OVL_NEXT
(
member
)
)
{
if
(
TREE_CODE
(
member
)
!=
FUNCTION_DECL
)
continue
;
if
(
DECL_PURE_VIRTUAL_P
(
member
)
)
continue
;
if
(
!
DECL_VIRTUAL_P
(
member
)
)
continue
;
if
(
lookup_attribute
(
attribute_name
,
DECL_ATTRIBUTES
(
member
)
)
)
{
print_node_brief
(
stderr
,
""
,
ctype
,
0
)
;
fprintf
(
stderr
,
" inherits %s because"
,
attribute_name
)
;
print_node_brief
(
stderr
,
""
,
member
,
0
)
;
fprintf
(
stderr
,
" has it.\n"
)
;
return
true
;
}
}
}
}
print_node_brief
(
stderr
,
""
,
ctype
,
0
)
;
fprintf
(
stderr
,
" does not inherit %s\n"
,
attribute_name
)
;
return
false
;
}
</s>

Decide if a class needs to have an attribute because one of its member functions has the attribute .


<s> static int avr_operand_rtx_cost ( rtx x , machine_mode mode , enum rtx_code outer , int opno , bool speed ) { enum rtx_code code = GET_CODE ( x ) ; int total ; switch ( code ) { case REG : case SUBREG : return 0 ; case CONST_INT : case CONST_FIXED : case CONST_DOUBLE : return COSTS_N_INSNS ( GET_MODE_SIZE ( mode ) ) ; default : break ; } total = 0 ; avr_rtx_costs ( x , mode , outer , opno , & total , speed ) ; return total ; } </s>

Mutually recursive subroutine of avr_rtx_cost for calculating the cost of an RTX operand given its context . X is the rtx of the operand , MODE is its mode , and OUTER is the rtx_code of this operand 's parent operator .


<s> Register SIRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const SIFrameLowering * TFI = MF . getSubtarget < GCNSubtarget > ( ) . getFrameLowering ( ) ; const SIMachineFunctionInfo * FuncInfo = MF . getInfo < SIMachineFunctionInfo > ( ) ; return TFI -> hasFP ( MF ) ? FuncInfo -> getFrameOffsetReg ( ) : FuncInfo -> getStackPtrOffsetReg ( ) ; } </s>


"Unexpected register class in CSRsViaCopy!"

"Function should be nounwind in insertCopiesSplitCSR!"

Insert explicit copies in entry and exit blocks .


"Should only have register or immediate operands"

Legalize operands in MI by either commuting it or inserting a copy of src1 .


<s> const_iterator end ( ) const { return Seq . end ( ) ; } </s>

Get a const_iterator to the end of the symbol table .


<s> bool MipsSubtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = TargetSubtargetInfo :: ANTIDEP_CRITICAL ; CriticalPathRCs . clear ( ) ; CriticalPathRCs . push_back ( hasMips64 ( ) ? & Mips :: CPU64RegsRegClass : & Mips :: CPURegsRegClass ) ; return OptLevel >= CodeGenOpt :: Aggressive ; } </s>

True if the subtarget should run a scheduler after register allocation .

Mips Mips Mips Mips::CPU64RegsRegClass Mips::CPURegsRegClass


<s> bool R600InstrInfo :: isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCyles , const BranchProbability & Probability ) const { return true ; } </s>

Return true if it 's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion .