<s> rtx xtensa_builtin_saveregs ( ) { rtx gp_regs , dest ; int arg_words = current_function_arg_words ; int gp_left = MAX_ARGS_IN_REGISTERS - arg_words ; int i ; if ( gp_left == 0 ) return const0_rtx ; gp_regs = assign_stack_local ( BLKmode , MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD , - 1 ) ; MEM_IN_STRUCT_P ( gp_regs ) = 1 ; RTX_UNCHANGING_P ( gp_regs ) = 1 ; RTX_UNCHANGING_P ( XEXP ( gp_regs , 0 ) ) = 1 ; dest = change_address ( gp_regs , SImode , plus_constant ( XEXP ( gp_regs , 0 ) , arg_words * UNITS_PER_WORD ) ) ; for ( i = 0 ; i < gp_left ; i ++ ) { emit_move_insn ( operand_subword ( dest , i , 1 , BLKmode ) , gen_raw_REG ( SImode , GP_ARG_FIRST + arg_words + i ) ) ; } return XEXP ( gp_regs , 0 ) ; } </s>

Save the incoming argument registers on the stack . Returns the address of the saved registers .


"Trying to obtain non-reserved register \""

Return the register ID of the name passed in .


<s> unsigned Tile64InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s>
unsigned
HexagonInstrInfo
::
reduceLoopCount
(
MachineBasicBlock
&
MBB
,
MachineInstr
*
IndVar
,
MachineInstr
&
Cmp
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
SmallVectorImpl
<
MachineInstr
*
>
&
PrevInsts
,
unsigned
Iter
,
unsigned
MaxIter
)
const
{
assert
(
(
!
IndVar
)
&&
isEndLoopN
(
Cmp
.
getOpcode
(
)
)
&&
"Expecting a hardware loop"
)
;
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
DebugLoc
DL
=
Cmp
.
getDebugLoc
(
)
;
SmallPtrSet
<
MachineBasicBlock
*
,
8
>
VisitedBBs
;
MachineInstr
*
Loop
=
findLoopInstr
(
&
MBB
,
Cmp
.
getOpcode
(
)
,
Cmp
.
getOperand
(
0
)
.
getMBB
(
)
,
VisitedBBs
)
;
if
(
!
Loop
)
return
0
;
if
(
Loop
->
getOpcode
(
)
==
Hexagon
::
J2_loop0i
||
Loop
->
getOpcode
(
)
==
Hexagon
::
J2_loop1i
)
{
int64_t
Offset
=
Loop
->
getOperand
(
1
)
.
getImm
(
)
;
if
(
Offset
<=
1
)
Loop
->
eraseFromParent
(
)
;
else
Loop
->
getOperand
(
1
)
.
setImm
(
Offset
1
)
;
return
Offset
1
;
}
assert
(
Loop
->
getOpcode
(
)
==
Hexagon
::
J2_loop0r
&&
"Unexpected instruction"
)
;
unsigned
LoopCount
=
Loop
->
getOperand
(
1
)
.
getReg
(
)
;
unsigned
LoopEnd
=
createVR
(
MF
,
MVT
::
i1
)
;
MachineInstr
*
NewCmp
=
BuildMI
(
&
MBB
,
DL
,
get
(
Hexagon
::
C2_cmpgtui
)
,
LoopEnd
)
.
addReg
(
LoopCount
)
.
addImm
(
1
)
;
unsigned
NewLoopCount
=
createVR
(
MF
,
MVT
::
i32
)
;
MachineInstr
*
NewAdd
=
BuildMI
(
&
MBB
,
DL
,
get
(
Hexagon
::
A2_addi
)
,
NewLoopCount
)
.
addReg
(
LoopCount
)
.
addImm
(
1
)
;
const
auto
&
HRI
=
*
MF
->
getSubtarget
<
HexagonSubtarget
>
(
)
.
getRegisterInfo
(
)
;
for
(
SmallVectorImpl
<
MachineInstr
*
>
::
iterator
I
=
PrevInsts
.
begin
(
)
,
E
=
PrevInsts
.
end
(
)
;
I
!=
E
;
++
I
)
(
*
I
)
->
substituteRegister
(
LoopCount
,
NewLoopCount
,
0
,
HRI
)
;
PrevInsts
.
clear
(
)
;
PrevInsts
.
push_back
(
NewCmp
)
;
PrevInsts
.
push_back
(
NewAdd
)
;
if
(
Iter
==
MaxIter
)
BuildMI
(
&
MBB
,
DL
,
get
(
Hexagon
::
J2_loop0r
)
)
.
addMBB
(
Loop
->
getOperand
(
0
)
.
getMBB
(
)
)
.
addReg
(
NewLoopCount
)
;
if
(
Iter
==
0
)
Loop
->
eraseFromParent
(
)
;
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
Hexagon
::
J2_jumpf
)
)
;
Cond
.
push_back
(
NewCmp
->
getOperand
(
0
)
)
;
return
NewLoopCount
;
}
</s>

Generate code to reduce the loop iteration by one and check if the loop is finished .


<s> MCSymbol * X86AsmPrinter :: GetCPISymbol ( unsigned CPID ) const { if ( Subtarget -> isTargetKnownWindowsMSVC ( ) ) { const MachineConstantPoolEntry & CPE = MF -> getConstantPool ( ) -> getConstants ( ) [ CPID ] ; if ( ! CPE . isMachineConstantPoolEntry ( ) ) { SectionKind Kind = CPE . getSectionKind ( TM . getDataLayout ( ) ) ; const Constant * C = CPE . Val . ConstVal ; if ( const MCSectionCOFF * S = dyn_cast < MCSectionCOFF > ( getObjFileLowering ( ) . getSectionForConstant ( Kind , C ) ) ) { if ( MCSymbol * Sym = S -> getCOMDATSymbol ( ) ) { if ( Sym -> isUndefined ( ) ) OutStreamer . EmitSymbolAttribute ( Sym , MCSA_Global ) ; return Sym ; } } } } return AsmPrinter :: GetCPISymbol ( CPID ) ; } </s>

Return the symbol for the specified constant pool entry .


<s>
int
ARMTTIImpl
::
getNumMemOps
(
const
IntrinsicInst
*
I
)
const
{
MemOp
MOp
;
unsigned
DstAddrSpace
=
~
0u
;
unsigned
SrcAddrSpace
=
~
0u
;
const
Function
*
F
=
I
->
getParent
(
)
->
getParent
(
)
;
if
(
const
auto
*
MC
=
dyn_cast
<
MemTransferInst
>
(
I
)
)
{
ConstantInt
*
C
=
dyn_cast
<
ConstantInt
>
(
MC
->
getLength
(
)
)
;
if
(
!
C
)
return
1
;
const
unsigned
Size
=
C
->
getValue
(
)
.
getZExtValue
(
)
;
const
Align
DstAlign
=
*
MC
->
getDestAlign
(
)
;
const
Align
SrcAlign
=
*
MC
->
getSourceAlign
(
)
;
MOp
=
MemOp
::
Copy
(
Size
,
false
,
DstAlign
,
SrcAlign
,
false
,
false
)
;
DstAddrSpace
=
MC
->
getDestAddressSpace
(
)
;
SrcAddrSpace
=
MC
->
getSourceAddressSpace
(
)
;
}
else
if
(
const
auto
*
MS
=
dyn_cast
<
MemSetInst
>
(
I
)
)
{
ConstantInt
*
C
=
dyn_cast
<
ConstantInt
>
(
MS
->
getLength
(
)
)
;
if
(
!
C
)
return
1
;
const
unsigned
Size
=
C
->
getValue
(
)
.
getZExtValue
(
)
;
const
Align
DstAlign
=
*
MS
->
getDestAlign
(
)
;
MOp
=
MemOp
::
Set
(
Size
,
false
,
DstAlign
,
false
,
false
)
;
DstAddrSpace
=
MS
->
getDestAddressSpace
(
)
;
}
else
llvm_unreachable
(
"Expected a memcpy/move or memset!"
)
;
unsigned
Limit
,
Factor
=
2
;
switch
(
I
->
getIntrinsicID
(
)
)
{
case
Intrinsic
::
memcpy
:
Limit
=
TLI
->
getMaxStoresPerMemcpy
(
F
->
hasMinSize
(
)
)
;
break
;
case
Intrinsic
::
memmove
:
Limit
=
TLI
->
getMaxStoresPerMemmove
(
F
->
hasMinSize
(
)
)
;
break
;
case
Intrinsic
::
memset
:
Limit
=
TLI
->
getMaxStoresPerMemset
(
F
->
hasMinSize
(
)
)
;
Factor
=
1
;
break
;
default
:
llvm_unreachable
(
"Expected a memcpy/move or memset!"
)
;
}
std
::
vector
<
EVT
>
MemOps
;
if
(
getTLI
(
)
->
findOptimalMemOpLowering
(
MemOps
,
Limit
,
MOp
,
DstAddrSpace
,
SrcAddrSpace
,
F
->
getAttributes
(
)
)
)
return
MemOps
.
size
(
)
*
Factor
;
return
1
;
}
</s>

Given a memcpy/memset/memmove instruction , return the number of memory operations performed , via querying findOptimalMemOpLowering .


<s> static int untangle_mova ( int * num_mova , rtx_insn * * first_mova , rtx_insn * new_mova ) { int n_addr = 0 ; int f_target , n_target = 0 ; if ( optimize ) { if ( INSN_ADDRESSES_SIZE ( ) <= ( unsigned ) INSN_UID ( new_mova ) ) return - 1 ; n_addr = INSN_ADDRESSES ( INSN_UID ( new_mova ) ) ; n_target = INSN_ADDRESSES ( INSN_UID ( XEXP ( MOVA_LABELREF ( new_mova ) , 0 ) ) ) ; if ( n_addr > n_target || n_addr + 1022 < n_target ) { fixup_mova ( new_mova ) ; return 1 ; } } if ( ! ( * num_mova ) ++ ) { * first_mova = new_mova ; return 2 ; } if ( ! optimize || ( ( f_target = INSN_ADDRESSES ( INSN_UID ( XEXP ( MOVA_LABELREF ( * first_mova ) , 0 ) ) ) ) >= n_target ) ) return - 1 ; ( * num_mova ) -- ; if ( f_target - INSN_ADDRESSES ( INSN_UID ( * first_mova ) ) > n_target - n_addr ) { fixup_mova ( * first_mova ) ; return 0 ; } else { fixup_mova ( new_mova ) ; return 1 ; } } </s>

NEW_MOVA is a mova we 've just encountered while scanning forward . Update * num_mova , and check if the new mova is not nested within the first one . return 0 if * first_mova was replaced , 1 if new_mova was replaced , 2 if new_mova has been assigned to * first_mova , -1 otherwise ..


<s>
StringRef
getPassName
(
)
const
override
{
return
"Z80old DAG->DAG Instruction Selection"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool mips_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { return ( mode1 == mode2 || ( ! mips_mode_ok_for_mov_fmt_p ( mode1 ) && ! mips_mode_ok_for_mov_fmt_p ( mode2 ) ) ) ; } </s>


<s> bool HexagonConstEvaluator :: evaluate ( const MachineInstr & BrI , const CellMap & Inputs , SetVector < const MachineBasicBlock * > & Targets , bool & FallsThru ) { unsigned Opc = BrI . getOpcode ( ) ; bool SimpleBranch = false ; bool Negated = false ; switch ( Opc ) { case Hexagon :: J2_jumpf : case Hexagon :: J2_jumpfnew : case Hexagon :: J2_jumpfnewpt : Negated = true ; LLVM_FALLTHROUGH ; case Hexagon :: J2_jumpt : case Hexagon :: J2_jumptnew : case Hexagon :: J2_jumptnewpt : SimpleBranch = true ; break ; case Hexagon :: J2_jump : Targets . insert ( BrI . getOperand ( 0 ) . getMBB ( ) ) ; FallsThru = false ; return true ; default : Undetermined : FallsThru = ! BrI . isUnconditionalBranch ( ) ; return false ; } if ( SimpleBranch ) { const MachineOperand & MD = BrI . getOperand ( 0 ) ; RegisterSubReg PR ( MD ) ; if ( PR . SubReg ) goto Undetermined ; assert ( Inputs . has ( PR . Reg ) ) ; const LatticeCell & PredC = Inputs . get ( PR . Reg ) ; if ( PredC . isBottom ( ) ) goto Undetermined ; uint32_t Props = PredC . properties ( ) ; bool CTrue = false , CFalse = false ; if ( Props & ConstantProperties :: Zero ) CFalse = true ; else if ( Props & ConstantProperties :: NonZero ) CTrue = true ; if ( ! CTrue && ! CFalse ) goto Undetermined ; const MachineBasicBlock * BranchTarget = BrI . getOperand ( 1 ) . getMBB ( ) ; FallsThru = false ; if ( ( ! Negated && CTrue ) || ( Negated && CFalse ) ) Targets . insert ( BranchTarget ) ; else if ( ( ! Negated && CFalse ) || ( Negated && CTrue ) ) FallsThru = true ; else goto Undetermined ; } return true ; } </s>

evaluate - Evaluate Expr and append the resulting set to Elts .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s>
void
ARM64TargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this"
)
;
case
ISD
::
FP_TO_UINT
:
case
ISD
::
FP_TO_SINT
:
assert
(
N
->
getValueType
(
0
)
==
MVT
::
i128
&&
"unexpected illegal conversion"
)
;
return
;
}
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> static char * detect_caches_linux ( void ) { unsigned l1_sizekb , l1_line , l1_assoc , l2_sizekb ; const char * platform ; platform = elf_platform ( ) ; if ( platform != NULL ) { l1_line = 128 ; if ( platform [ 5 ] == '6' ) l1_sizekb = 64 ; else l1_sizekb = 32 ; } else { l1_line = elf_dcachebsize ( ) ; l1_sizekb = 32 ; } l1_assoc = 0 ; l2_sizekb = 512 ; return describe_cache ( l1_sizekb , l1_line , l1_assoc , l2_sizekb ) ; } </s>

Returns the description of caches on Linux .


<s> bool MipsTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { if ( VT != MVT :: f32 && VT != MVT :: f64 ) return false ; if ( Imm . isNegZero ( ) ) return false ; return Imm . isZero ( ) ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> RegisterAggr & RegisterAggr :: insert ( RegisterRef RR ) { if ( PhysicalRegisterInfo :: isRegMaskId ( RR . Reg ) ) { const uint32_t * MB = PRI . getRegMaskBits ( RR . Reg ) ; for ( unsigned i = 1 , e = PRI . getTRI ( ) . getNumRegs ( ) ; i != e ; ++ i ) { if ( MB [ i / 32 ] & ( 1u << ( i % 32 ) ) ) continue ; insert ( RegisterRef ( i , LaneBitmask :: getAll ( ) ) ) ; } return * this ; } RegisterRef NR = PRI . normalize ( RR ) ; auto F = Masks . find ( NR . Reg ) ; if ( F == Masks . end ( ) ) Masks . insert ( { NR . Reg , NR . Mask } ) ; else F -> second |= NR . Mask ; if ( PRI . hasPartialOverlaps ( NR . Reg ) ) { for ( MCRegUnitMaskIterator U ( RR . Reg , & PRI . getTRI ( ) ) ; U . isValid ( ) ; ++ U ) { std :: pair < RegisterId , LaneBitmask > P = * U ; if ( P . second . none ( ) || ( P . second & RR . Mask ) . none ( ) ) continue ; ExpUnits . set ( P . first ) ; CheckUnits = true ; } } return * this ; } </s>

insert - Append entry to the vector if it does n't already exist .


<s> Expected < uint64_t > FunctionSym :: getAddress ( const HSACodeObject * CodeObject , const object :: ELF64LEObjectFile :: Elf_Shdr * Text ) const { assert ( Text ) ; auto ElfHeader = CodeObject -> getELFFile ( ) . getHeader ( ) ; if ( ElfHeader . e_type == ELF :: ET_REL ) { return st_value + Text -> sh_addr ; } return st_value ; } </s>

Returns the address of this pointer in this block .


This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL to return a pointer to VERSION_DECL if we are running on a machine that supports the index CLONE_ISA hardware architecture bits . This function will be called during version dispatch to decide which function version to execute . It returns the basic block at the end , to which more conditions can be added .


<s> virtual const TargetSubtargetInfo * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> EVT AArch64TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { bool Fast ; const Function * F = MF . getFunction ( ) ; if ( Subtarget -> hasFPARMv8 ( ) && ! IsMemset && Size >= 16 && ! F -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoImplicitFloat ) && ( memOpAlign ( SrcAlign , DstAlign , 16 ) || ( allowsMisalignedMemoryAccesses ( MVT :: f128 , 0 , 1 , & Fast ) && Fast ) ) ) return MVT :: f128 ; return Size >= 8 ? MVT :: i64 : MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> bool ARMTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { EVT VT = getValueType ( DL , Ty , true ) ; if ( ! isLegalAddressImmediate ( AM . BaseOffs , VT , Subtarget ) ) return false ; if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; default : if ( AM . BaseOffs ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( Subtarget -> isThumb1Only ( ) ) return isLegalT1ScaledAddressingMode ( AM , VT ) ; if ( Subtarget -> isThumb2 ( ) ) return isLegalT2ScaledAddressingMode ( AM , VT ) ; int Scale = AM . Scale ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case MVT :: i1 : case MVT :: i8 : case MVT :: i32 : if ( Scale < 0 ) Scale = - Scale ; if ( Scale == 1 ) return true ; return isPowerOf2_32 ( Scale & ~ 1 ) ; case MVT :: i16 : case MVT :: i64 : if ( Scale == 1 || ( AM . HasBaseReg && Scale == - 1 ) ) return true ; if ( ! AM . HasBaseReg && Scale == 2 ) return true ; return false ; case MVT :: isVoid : if ( Scale & 1 ) return false ; return isPowerOf2_32 ( Scale ) ; } } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


"lowerToVVP called for unexpected SDNode."


<s> MCSymbol * DLXMCInstLower :: GetBlockAddressSymbol ( const MachineOperand & MO ) const { return Printer . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; } </s>

Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block .


<s> static int ix86_avx_u128_mode_after ( int mode , rtx_insn * insn ) { rtx pat = PATTERN ( insn ) ; if ( vzeroupper_operation ( pat , VOIDmode ) || vzeroall_operation ( pat , VOIDmode ) ) return AVX_U128_CLEAN ; if ( CALL_P ( insn ) ) { bool avx_upper_reg_found = false ; note_stores ( pat , ix86_check_avx_upper_stores , & avx_upper_reg_found ) ; return avx_upper_reg_found ? AVX_U128_DIRTY : AVX_U128_CLEAN ; } return mode ; } </s>

Calculate mode of upper 128bit AVX registers after the insn .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> rtx rs6000_emit_fp_cror ( rtx_code code , machine_mode mode , rtx x ) { rtx cond [ 2 ] ; int n = 0 ; if ( code == LTGT || code == LE || code == UNLT ) cond [ n ++ ] = gen_rtx_fmt_ee ( LT , mode , x , const0_rtx ) ; if ( code == LTGT || code == GE || code == UNGT ) cond [ n ++ ] = gen_rtx_fmt_ee ( GT , mode , x , const0_rtx ) ; if ( code == LE || code == GE || code == UNEQ ) cond [ n ++ ] = gen_rtx_fmt_ee ( EQ , mode , x , const0_rtx ) ; if ( code == UNLT || code == UNGT || code == UNEQ ) cond [ n ++ ] = gen_rtx_fmt_ee ( UNORDERED , mode , x , const0_rtx ) ; gcc_assert ( n == 2 ) ; rtx cc = gen_reg_rtx ( CCEQmode ) ; rtx logical = gen_rtx_IOR ( mode , cond [ 0 ] , cond [ 1 ] ) ; emit_insn ( gen_cceq_ior_compare ( mode , cc , logical , cond [ 0 ] , x , cond [ 1 ] , x ) ) ; return cc ; } </s>

Emit code doing a cror of two CR bits , for FP comparisons with a CODE that requires this . The result is mode MODE .


<s> static rtx msp430_get_inner_dest_code ( rtx x ) { enum rtx_code code = GET_CODE ( x ) ; rtx op0 = XEXP ( x , 0 ) ; switch ( code ) { case REG : case SYMBOL_REF : case CONST_INT : case CONST : case LABEL_REF : return x ; case MEM : switch ( GET_CODE ( op0 ) ) { case REG : case SYMBOL_REF : case LABEL_REF : case CONST : case POST_INC : return x ; case PLUS : if ( GET_CODE ( XEXP ( op0 , 0 ) ) == REG ) { if ( GET_CODE ( XEXP ( op0 , 1 ) ) == CONST_INT || GET_CODE ( XEXP ( op0 , 1 ) ) == CONST || GET_CODE ( XEXP ( op0 , 1 ) ) == LABEL_REF || GET_CODE ( XEXP ( op0 , 1 ) ) == SYMBOL_REF ) return x ; else return msp430_get_inner_dest_code ( op0 ) ; } return msp430_get_inner_dest_code ( op0 ) ; default : if ( GET_RTX_FORMAT ( code ) [ 0 ] != 'e' ) return x ; return msp430_get_inner_dest_code ( op0 ) ; } break ; default : if ( op0 == NULL_RTX ) gcc_unreachable ( ) ; else { if ( GET_RTX_FORMAT ( code ) [ 0 ] != 'e' && code != ENTRY_VALUE ) return x ; return msp430_get_inner_dest_code ( op0 ) ; } } } </s>

Recurse within X to find the actual destination operand of the expression . For example : ( plus ( ashift ( minus ( ashift ( reg ) ( const_int ) ...... should return the reg RTX .


"M680X0 DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s>
bool
ARMTargetLowering
::
ExpandInlineAsm
(
CallInst
*
CI
)
const
{
if
(
!
Subtarget
->
hasV6Ops
(
)
)
return
false
;
InlineAsm
*
IA
=
cast
<
InlineAsm
>
(
CI
->
getCalledValue
(
)
)
;
std
::
string
AsmStr
=
IA
->
getAsmString
(
)
;
SmallVector
<
StringRef
,
4
>
AsmPieces
;
SplitString
(
AsmStr
,
AsmPieces
,
";\n"
)
;
switch
(
AsmPieces
.
size
(
)
)
{
default
:
return
false
;
case
1
:
AsmStr
=
AsmPieces
[
0
]
;
AsmPieces
.
clear
(
)
;
SplitString
(
AsmStr
,
AsmPieces
,
" \t,"
)
;
if
(
AsmPieces
.
size
(
)
==
3
&&
AsmPieces
[
0
]
==
"rev"
&&
AsmPieces
[
1
]
==
"$0"
&&
AsmPieces
[
2
]
==
"$1"
&&
IA
->
getConstraintString
(
)
.
compare
(
0
,
4
,
"=l,l"
)
==
0
)
{
const
IntegerType
*
Ty
=
dyn_cast
<
IntegerType
>
(
CI
->
getType
(
)
)
;
if
(
Ty
&&
Ty
->
getBitWidth
(
)
==
32
)
return
IntrinsicLowering
::
LowerToByteSwap
(
CI
)
;
}
break
;
}
return
false
;
}
</s>

This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to .


<s> void rs6000_split_lock_test_and_set ( rtx retval , rtx mem , rtx val , rtx scratch ) { enum machine_mode mode = GET_MODE ( mem ) ; rtx label , x , cond = gen_rtx_REG ( CCmode , CR0_REGNO ) ; emit_insn ( gen_memory_barrier ( ) ) ; label = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label , 0 ) ) ; emit_load_locked ( mode , retval , mem ) ; emit_move_insn ( scratch , val ) ; emit_store_conditional ( mode , cond , mem , scratch ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label ) ; emit_insn ( gen_isync ( ) ) ; } </s>

Expand an atomic test and set operation . MEM is the memory on which to operate . VAL is the value set . SCRATCH is a scratch GPR .


<s> DecodeStatus SystemZDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CS ) const { Size = 0 ; if ( Bytes . size ( ) < 2 ) return MCDisassembler :: Fail ; const uint8_t * Table ; if ( Bytes [ 0 ] < 0x40 ) { Size = 2 ; Table = DecoderTable16 ; } else if ( Bytes [ 0 ] < 0xc0 ) { Size = 4 ; Table = DecoderTable32 ; } else { Size = 6 ; Table = DecoderTable48 ; } if ( Bytes . size ( ) < Size ) { Size = Bytes . size ( ) ; return MCDisassembler :: Fail ; } uint64_t Inst = 0 ; for ( uint64_t I = 0 ; I < Size ; ++ I ) Inst = ( Inst << 8 ) | Bytes [ I ] ; return decodeInstruction ( Table , MI , Inst , Address , this , STI ) ; } </s>

Returns the disassembly of a single instruction .


"unknown flag passed in %<-moverride=%s%> (%s)"

Parse TOKEN , which has length LENGTH to see if it is an option described in FLAG . If it is , return the index bit for that fusion type . If not , error ( printing OPTION_NAME ) and return zero .


<s> bool mn10300_match_ccmode ( rtx insn , machine_mode cc_mode ) { rtx op1 , flags ; machine_mode flags_mode ; gcc_checking_assert ( XVECLEN ( PATTERN ( insn ) , 0 ) == 2 ) ; op1 = XVECEXP ( PATTERN ( insn ) , 0 , 1 ) ; gcc_checking_assert ( GET_CODE ( SET_SRC ( op1 ) ) == COMPARE ) ; flags = SET_DEST ( op1 ) ; flags_mode = GET_MODE ( flags ) ; if ( GET_MODE ( SET_SRC ( op1 ) ) != flags_mode ) return false ; if ( GET_MODE_CLASS ( flags_mode ) != MODE_CC ) return false ; if ( cc_flags_for_mode ( flags_mode ) & ~ cc_flags_for_mode ( cc_mode ) ) return false ; return true ; } </s>

A helper function for matching parallels that set the flags .


"passing %qT to argument %d of %qE, which"

Require argument ARGNO to have vector type TYPE , in cases where this requirement holds for all uses of the function . Return true if the argument has the right form , otherwise report an appropriate error .


<s> bool PPCPassConfig :: addILPOpts ( ) { if ( getPPCSubtarget ( ) . hasISEL ( ) ) { addPass ( & EarlyIfConverterID ) ; return true ; } return false ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .


<s> bool X86CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto DL = MF . getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned Idx = 0 ; for ( const auto & Arg : F . args ( ) ) { if ( Arg . hasAttribute ( Attribute :: ByVal ) || Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: Nest ) || VRegs [ Idx ] . size ( ) > 1 ) return false ; ArgInfo OrigArg ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArg , Idx + AttributeList :: FirstArgIndex , DL , F ) ; if ( ! splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < Register > Regs ) { MIRBuilder . buildMerge ( VRegs [ Idx ] [ 0 ] , Regs ) ; } ) ) return false ; Idx ++ ; } MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; FormalArgHandler Handler ( MIRBuilder , MRI , CC_X86 ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> static bool cr16_class_likely_spilled_p ( reg_class_t rclass ) { if ( ( rclass ) == SHORT_REGS || ( rclass ) == DOUBLE_BASE_REGS || ( rclass ) == LONG_REGS || ( rclass ) == GENERAL_REGS ) return true ; return false ; } </s>


<s> void GCNPassConfig :: addPreEmitPass ( ) { addPass ( & PostRAHazardRecognizerID ) ; if ( EnableSIInsertWaitcntsPass ) addPass ( createSIInsertWaitcntsPass ( ) ) ; else addPass ( createSIInsertWaitsPass ( ) ) ; addPass ( createSIShrinkInstructionsPass ( ) ) ; addPass ( & SIInsertSkipsPassID ) ; addPass ( createSIDebuggerInsertNopsPass ( ) ) ; addPass ( & BranchRelaxationPassID ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> const MINA32RegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


"Cannot store this register into a stack slot!"

Store the specified register of the given register class to the specified stack frame index .


<s> bool riscv_split_symbol ( rtx temp , rtx addr , machine_mode mode , rtx * low_out , bool in_splitter ) { enum riscv_symbol_type symbol_type ; if ( ( GET_CODE ( addr ) == HIGH && mode == MAX_MACHINE_MODE ) || ! riscv_symbolic_constant_p ( addr , & symbol_type ) || riscv_symbol_insns ( symbol_type ) == 0 || ! riscv_split_symbol_type ( symbol_type ) ) return false ; if ( low_out ) switch ( symbol_type ) { case SYMBOL_ABSOLUTE : { rtx high = gen_rtx_HIGH ( Pmode , copy_rtx ( addr ) ) ; high = riscv_force_temporary ( temp , high , in_splitter ) ; * low_out = gen_rtx_LO_SUM ( Pmode , high , addr ) ; } break ; case SYMBOL_PCREL : { static unsigned seqno ; char buf [ 32 ] ; rtx label ; ssize_t bytes = snprintf ( buf , sizeof ( buf ) , ".LA%u" , seqno ) ; gcc_assert ( ( size_t ) bytes < sizeof ( buf ) ) ; label = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; SYMBOL_REF_FLAGS ( label ) |= SYMBOL_FLAG_LOCAL ; if ( ! nonzero_address_p ( addr ) ) SYMBOL_REF_WEAK ( label ) = 1 ; if ( temp == NULL ) temp = gen_reg_rtx ( Pmode ) ; if ( Pmode == DImode ) emit_insn ( gen_auipcdi ( temp , copy_rtx ( addr ) , GEN_INT ( seqno ) ) ) ; else emit_insn ( gen_auipcsi ( temp , copy_rtx ( addr ) , GEN_INT ( seqno ) ) ) ; * low_out = gen_rtx_LO_SUM ( Pmode , temp , label ) ; seqno ++ ; } break ; default : gcc_unreachable ( ) ; } return true ; } </s>

If MODE is MAX_MACHINE_MODE , ADDR appears as a move operand , otherwise it appears in a MEM of that mode . Return true if ADDR is a legitimate constant in that context and can be split into high and low parts . If so , and if LOW_OUT is nonnull , emit the high part and store the low part in * LOW_OUT . Leave * LOW_OUT unchanged otherwise . TEMP is as for riscv_force_temporary and is used to load the high part into a register . When MODE is MAX_MACHINE_MODE , the low part is guaranteed to be a legitimize SET_SRC for an .md pattern , otherwise the low part is guaranteed to be a legitimate address for mode MODE .


<s> Sched :: Preference ARMTargetLowering :: getSchedulingPreference ( SDNode * N ) const { unsigned NumVals = N -> getNumValues ( ) ; if ( ! NumVals ) return Sched :: RegPressure ; for ( unsigned i = 0 ; i != NumVals ; ++ i ) { EVT VT = N -> getValueType ( i ) ; if ( VT == MVT :: Glue || VT == MVT :: Other ) continue ; if ( VT . isFloatingPoint ( ) || VT . isVector ( ) ) return Sched :: Latency ; } if ( ! N -> isMachineOpcode ( ) ) return Sched :: RegPressure ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; const TargetInstrDesc & TID = TII -> get ( N -> getMachineOpcode ( ) ) ; if ( TID . getNumDefs ( ) == 0 ) return Sched :: RegPressure ; if ( ! Itins -> isEmpty ( ) && Itins -> getOperandCycle ( TID . getSchedClass ( ) , 0 ) > 2 ) return Sched :: Latency ; return Sched :: RegPressure ; } </s>


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BRCOND : return LowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return LowerConstantPool ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: BlockAddress : return LowerBlockAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return LowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( Op , DAG ) ; case ISD :: SELECT : return LowerSELECT ( Op , DAG ) ; case ISD :: SELECT_CC : return LowerSELECT_CC ( Op , DAG ) ; case ISD :: SETCC : return LowerSETCC ( Op , DAG ) ; case ISD :: VASTART : return LowerVASTART ( Op , DAG ) ; case ISD :: FCOPYSIGN : return LowerFCOPYSIGN ( Op , DAG ) ; case ISD :: FABS : return LowerFABS ( Op , DAG ) ; case ISD :: FRAMEADDR : return LowerFRAMEADDR ( Op , DAG ) ; case ISD :: RETURNADDR : return LowerRETURNADDR ( Op , DAG ) ; case ISD :: MEMBARRIER : return LowerMEMBARRIER ( Op , DAG ) ; case ISD :: ATOMIC_FENCE : return LowerATOMIC_FENCE ( Op , DAG ) ; case ISD :: SHL_PARTS : return LowerShiftLeftParts ( Op , DAG ) ; case ISD :: SRA_PARTS : return LowerShiftRightParts ( Op , DAG , true ) ; case ISD :: SRL_PARTS : return LowerShiftRightParts ( Op , DAG , false ) ; case ISD :: LOAD : return LowerLOAD ( Op , DAG ) ; case ISD :: STORE : return LowerSTORE ( Op , DAG ) ; case ISD :: INTRINSIC_WO_CHAIN : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case ISD :: INTRINSIC_W_CHAIN : return LowerINTRINSIC_W_CHAIN ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::BRCOND ISD::ConstantPool ISD::GlobalAddress ISD::BlockAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::SELECT ISD::SELECT_CC ISD::SETCC ISD::VASTART ISD::FCOPYSIGN ISD::FABS ISD::FRAMEADDR ISD::RETURNADDR ISD::MEMBARRIER ISD::ATOMIC_FENCE ISD::SHL_PARTS ISD::SRA_PARTS ISD::SRL_PARTS ISD::LOAD ISD::STORE ISD::INTRINSIC_WO_CHAIN ISD::INTRINSIC_W_CHAIN


<s>
const
char
*
emit_fusion_p9_load
(
rtx
reg
,
rtx
mem
,
rtx
tmp_reg
)
{
enum
machine_mode
mode
=
GET_MODE
(
reg
)
;
rtx
hi
;
rtx
lo
;
rtx
addr
;
const
char
*
load_string
;
int
r
;
if
(
GET_CODE
(
mem
)
==
FLOAT_EXTEND
||
GET_CODE
(
mem
)
==
ZERO_EXTEND
)
{
mem
=
XEXP
(
mem
,
0
)
;
mode
=
GET_MODE
(
mem
)
;
}
if
(
GET_CODE
(
reg
)
==
SUBREG
)
{
gcc_assert
(
SUBREG_BYTE
(
reg
)
==
0
)
;
reg
=
SUBREG_REG
(
reg
)
;
}
if
(
!
REG_P
(
reg
)
)
fatal_insn
(
"emit_fusion_p9_load, bad reg #1"
,
reg
)
;
r
=
REGNO
(
reg
)
;
if
(
FP_REGNO_P
(
r
)
)
{
if
(
mode
==
SFmode
)
load_string
=
"lfs"
;
else
if
(
mode
==
DFmode
||
mode
==
DImode
)
load_string
=
"lfd"
;
else
gcc_unreachable
(
)
;
}
else
if
(
ALTIVEC_REGNO_P
(
r
)
&&
TARGET_P9_DFORM_SCALAR
)
{
if
(
mode
==
SFmode
)
load_string
=
"lxssp"
;
else
if
(
mode
==
DFmode
||
mode
==
DImode
)
load_string
=
"lxsd"
;
else
gcc_unreachable
(
)
;
}
else
if
(
INT_REGNO_P
(
r
)
)
{
switch
(
mode
)
{
case
QImode
:
load_string
=
"lbz"
;
break
;
case
HImode
:
load_string
=
"lhz"
;
break
;
case
SImode
:
case
SFmode
:
load_string
=
"lwz"
;
break
;
case
DImode
:
case
DFmode
:
if
(
!
TARGET_POWERPC64
)
gcc_unreachable
(
)
;
load_string
=
"ld"
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
else
fatal_insn
(
"emit_fusion_p9_load, bad reg #2"
,
reg
)
;
if
(
!
MEM_P
(
mem
)
)
fatal_insn
(
"emit_fusion_p9_load not MEM"
,
mem
)
;
addr
=
XEXP
(
mem
,
0
)
;
fusion_split_address
(
addr
,
&
hi
,
&
lo
)
;
emit_fusion_addis
(
tmp_reg
,
hi
,
"power9 load fusion"
,
GET_MODE_NAME
(
mode
)
)
;
emit_fusion_load_store
(
reg
,
tmp_reg
,
lo
,
load_string
)
;
return
""
;
}
</s>

Return a string to fuse an addis instruction with a load using extended fusion . The address that is used is the logical address that was formed during peephole2 : ( lo_sum ( high ) ( low-part ) ) The code is complicated , so we call output_asm_insn directly , and just return `` '' .

rs6000
0
0
"emit_fusion_p9_load, bad reg #1"
"lfs"
"lfd"
"lxssp"
"lxsd"
"lbz"
"lhz"
"lwz"
"ld"
"emit_fusion_p9_load, bad reg #2"
"emit_fusion_p9_load not MEM"
0
"power9 load fusion"
""


<s> const uint16_t * LanaiRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_SaveList ; } </s>


"unable to compute real location of stacked parameter"

Handle a special case when computing the offset of an argument from the frame pointer .


<s> void SITargetLowering :: computeKnownBitsForFrameIndex ( const int FI , KnownBits & Known , const MachineFunction & MF ) const { TargetLowering :: computeKnownBitsForFrameIndex ( FI , Known , MF ) ; Known . Zero . setHighBits ( getSubtarget ( ) -> getKnownHighZeroBitsForFrameIndex ( ) ) ; } </s>

Determine which of the bits of FrameIndex FIOp are known to be 0 .


<s> void AArch64MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; if ( MI . getOpcode ( ) == AArch64 :: TLSDESCCALL ) { MCFixupKind Fixup = MCFixupKind ( AArch64 :: fixup_aarch64_tlsdesc_call ) ; Fixups . push_back ( MCFixup :: create ( 0 , MI . getOperand ( 0 ) . getExpr ( ) , Fixup ) ) ; return ; } if ( MI . getOpcode ( ) == AArch64 :: CompilerBarrier || MI . getOpcode ( ) == AArch64 :: SPACE || MI . getOpcode ( ) == AArch64 :: EH_SjLj_Setup ) { return ; } uint64_t Binary = getBinaryCodeForInstr ( MI , Fixups , STI ) ; support :: endian :: write < uint32_t > ( OS , Binary , support :: little ) ; ++ MCNumEmitted ; } </s>

Encode the given Inst to bytes and append to CB .


<s> void J2InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> void AArch64TargetELFStreamer :: emitInst ( uint32_t Inst ) { getStreamer ( ) . emitInst ( Inst ) ; } </s>

Callback used to implement the .inst directive .


<s> virtual void initializePass ( ) override { pushTTIStack ( this ) ; } </s>

initializePass - This method may be overriden by immutable passes to allow them to perform various initialization actions they require .


<s> MBlazeTargetLowering :: ConstraintType MBlazeTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'd' : case 'y' : case 'f' : return C_RegisterClass ; break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


"Got non-GPR register in .cfi directive!"

tryParseRegister - parse one register if possible


<s> unsigned getMinPrefetchStride ( ) const override { return 2048 ; } </s>

Some HW prefetchers can handle accesses up to a certain constant stride .


<s> static unsigned getNumInterleavedAccesses ( VectorType * VecTy , const DataLayout & DL ) { return ( DL . getTypeSizeInBits ( VecTy ) + 127 ) / 128 ; } </s>

Returns the number of interleaved accesses that will be generated when lowering accesses of the given type .


"%qE attribute only applies to functions"

"ms_abi and sysv_abi attributes are not compatible"

Handle a `` ms_abi '' or `` sysv '' attribute ; arguments as in struct attribute_spec.handler .


<s> bool X86InstrInfo :: findCommutedOpIndices ( MachineInstr & MI , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { switch ( MI . getOpcode ( ) ) { case X86 :: CMPPDrri : case X86 :: CMPPSrri : case X86 :: VCMPPDrri : case X86 :: VCMPPSrri : case X86 :: VCMPPDYrri : case X86 :: VCMPPSYrri : { unsigned Imm = MI . getOperand ( 3 ) . getImm ( ) & 0x7 ; switch ( Imm ) { case 0x00 : case 0x03 : case 0x04 : case 0x07 : return fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , 1 , 2 ) ; } return false ; } default : bool IsIntrinOpcode ; if ( isFMA3 ( MI . getOpcode ( ) , IsIntrinOpcode ) ) return findFMA3CommutedOpIndices ( MI , IsIntrinOpcode , SrcOpIdx1 , SrcOpIdx2 ) ; return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; } return false ; } </s>

Returns true iff the routine could find two commutable operands in the given machine instruction .


<s>
void
AVRInstPrinter
::
printPCRelImm
(
const
MCInst
*
MI
,
unsigned
OpNo
,
raw_ostream
&
O
)
{
if
(
OpNo
>=
MI
->
size
(
)
)
{
O
<<
"<unknown>"
;
return
;
}
const
MCOperand
&
Op
=
MI
->
getOperand
(
OpNo
)
;
if
(
Op
.
isImm
(
)
)
{
int64_t
Imm
=
Op
.
getImm
(
)
;
O
<<
'.'
;
if
(
Imm
>=
0
)
O
<<
'+'
;
O
<<
Imm
;
}
else
{
assert
(
Op
.
isExpr
(
)
&&
"Unknown pcrel immediate operand"
)
;
O
<<
*
Op
.
getExpr
(
)
;
}
}
</s>

AVR
AVR
"<unknown>"
0
"Unknown pcrel immediate operand"


<s> void assignValueToReg ( Register ValVReg , Register PhysReg , CCValAssign & VA ) override { markPhysRegUsed ( PhysReg ) ; IncomingValueHandler :: assignValueToReg ( ValVReg , PhysReg , VA ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s>
bool
AArch64FrameLowering
::
spillCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
;
SmallVector
<
RegPairInfo
,
8
>
RegPairs
;
computeCalleeSaveRegisterPairs
(
MF
,
CSI
,
TRI
,
RegPairs
)
;
for
(
auto
RPII
=
RegPairs
.
rbegin
(
)
,
RPIE
=
RegPairs
.
rend
(
)
;
RPII
!=
RPIE
;
++
RPII
)
{
RegPairInfo
RPI
=
*
RPII
;
unsigned
Reg1
=
RPI
.
Reg1
;
unsigned
Reg2
=
RPI
.
Reg2
;
unsigned
StrOpc
;
if
(
RPI
.
IsGPR
)
StrOpc
=
RPI
.
isPaired
(
)
AArch64
::
STPXi
:
AArch64
::
STRXui
;
else
StrOpc
=
RPI
.
isPaired
(
)
AArch64
::
STPDi
:
AArch64
::
STRDui
;
DEBUG
(
dbgs
(
)
<<
"CSR spill: ("
<<
TRI
->
getName
(
Reg1
)
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
TRI
->
getName
(
Reg2
)
;
dbgs
(
)
<<
") -> fi#("
<<
RPI
.
FrameIdx
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
RPI
.
FrameIdx
+
1
;
dbgs
(
)
<<
")\n"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
StrOpc
)
)
;
MBB
.
addLiveIn
(
Reg1
)
;
if
(
RPI
.
isPaired
(
)
)
{
MBB
.
addLiveIn
(
Reg2
)
;
MIB
.
addReg
(
Reg2
,
getPrologueDeath
(
MF
,
Reg2
)
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
+
1
)
,
MachineMemOperand
::
MOStore
,
8
,
8
)
)
;
}
MIB
.
addReg
(
Reg1
,
getPrologueDeath
(
MF
,
Reg1
)
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
RPI
.
Offset
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
)
,
MachineMemOperand
::
MOStore
,
8
,
8
)
)
;
}
return
true
;
}
</s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s>
SDValue
RISCVTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
report_fatal_error
(
"unimplemented operand"
)
;
case
ISD
::
GlobalAddress
:
return
lowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
lowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
lowerSELECT
(
Op
,
DAG
)
;
}
}
</s>

RISCV
RISCV
"unimplemented operand"
ISD::GlobalAddress
ISD::BlockAddress
ISD::SELECT


<s>
void
BPFAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
)
const
{
if
(
0
)
errs
(
)
<<
"<MCFixup"
<<
" Offset:"
<<
Fixup
.
getOffset
(
)
<<
" Value:"
<<
*
(
Fixup
.
getValue
(
)
)
<<
" Kind:"
<<
Fixup
.
getKind
(
)
<<
" val "
<<
Value
<<
">\n"
;
if
(
Fixup
.
getKind
(
)
==
FK_SecRel_4
||
Fixup
.
getKind
(
)
==
FK_SecRel_8
)
{
assert
(
Value
==
0
)
;
return
;
}
assert
(
Fixup
.
getKind
(
)
==
FK_PCRel_2
)
;
*
(
uint16_t
*
)
&
Data
[
Fixup
.
getOffset
(
)
+
2
]
=
(
uint16_t
)
(
(
Value
8
)
/
8
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> CCAssignFn * GBZ80TargetLowering :: CCAssignFnForReturn ( CallingConv :: ID CC ) const { switch ( CC ) { default : return RetCC_GBZ80 ; } } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> void X86IntelInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS ) { printInstruction ( MI , OS ) ; } </s>


"Can only insert epilog into returning blocks"


<s> void ix86_simd_clone_adjust ( struct cgraph_node * node ) { const char * str = NULL ; if ( ! node -> definition ) return ; gcc_assert ( node -> decl == cfun -> decl ) ; switch ( node -> simdclone -> vecsize_mangle ) { case 'b' : if ( ! TARGET_SSE2 ) str = "sse2" ; break ; case 'c' : if ( TARGET_PREFER_AVX128 ) { if ( ! TARGET_AVX ) str = "avx,prefer-vector-width=256" ; else str = "prefer-vector-width=256" ; } else if ( ! TARGET_AVX ) str = "avx" ; break ; case 'd' : if ( TARGET_PREFER_AVX128 ) { if ( ! TARGET_AVX2 ) str = "avx2,prefer-vector-width=256" ; else str = "prefer-vector-width=256" ; } else if ( ! TARGET_AVX2 ) str = "avx2" ; break ; case 'e' : if ( TARGET_PREFER_AVX256 ) { if ( ! TARGET_AVX512F ) str = "avx512f,prefer-vector-width=512" ; else str = "prefer-vector-width=512" ; } else if ( ! TARGET_AVX512F ) str = "avx512f" ; break ; default : gcc_unreachable ( ) ; } if ( str == NULL ) return ; push_cfun ( NULL ) ; tree args = build_tree_list ( NULL_TREE , build_string ( strlen ( str ) , str ) ) ; bool ok = ix86_valid_target_attribute_p ( node -> decl , NULL , args , 0 ) ; gcc_assert ( ok ) ; pop_cfun ( ) ; ix86_reset_previous_fndecl ( ) ; ix86_set_current_function ( node -> decl ) ; } </s>

Add target attribute to SIMD clone NODE if needed .


<s> LLT AArch64TargetLowering :: getOptimalMemOpLLT ( const MemOp & Op , const AttributeList & FuncAttributes ) const { bool CanImplicitFloat = ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; bool CanUseNEON = Subtarget -> hasNEON ( ) && CanImplicitFloat ; bool CanUseFP = Subtarget -> hasFPARMv8 ( ) && CanImplicitFloat ; bool IsSmallMemset = Op . isMemset ( ) && Op . size ( ) < 32 ; auto AlignmentIsAcceptable = [ & ] ( EVT VT , Align AlignCheck ) { if ( Op . isAligned ( AlignCheck ) ) return true ; bool Fast ; return allowsMisalignedMemoryAccesses ( VT , 0 , Align ( 1 ) , MachineMemOperand :: MONone , & Fast ) && Fast ; } ; if ( CanUseNEON && Op . isMemset ( ) && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: v2i64 , Align ( 16 ) ) ) return LLT :: vector ( 2 , 64 ) ; if ( CanUseFP && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: f128 , Align ( 16 ) ) ) return LLT :: scalar ( 128 ) ; if ( Op . size ( ) >= 8 && AlignmentIsAcceptable ( MVT :: i64 , Align ( 8 ) ) ) return LLT :: scalar ( 64 ) ; if ( Op . size ( ) >= 4 && AlignmentIsAcceptable ( MVT :: i32 , Align ( 4 ) ) ) return LLT :: scalar ( 32 ) ; return LLT ( ) ; } </s>


<s> static tree rs6000_vector_type ( const char * name , tree elt_type , unsigned num_elts ) { tree result = build_vector_type ( elt_type , num_elts ) ; result = build_variant_type_copy ( result ) ; add_builtin_type ( name , result ) ; return result ; } </s>

Create a builtin vector type with a name . Taking care not to give the canonical type a name .


<s> void XCoreInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) && ! I -> isDebugInstr ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ; BuildMI ( MBB , I , DL , get ( XCore :: LDWFI ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) . addMemOperand ( MMO ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> static bool insn_dependent_p ( rtx x , rtx y ) { rtx tmp ; if ( ! INSN_P ( x ) || ! INSN_P ( y ) ) return 0 ; tmp = PATTERN ( y ) ; note_stores ( PATTERN ( x ) , insn_dependent_p_1 , & tmp ) ; if ( tmp == NULL_RTX ) return true ; tmp = PATTERN ( x ) ; note_stores ( PATTERN ( y ) , insn_dependent_p_1 , & tmp ) ; return ( tmp == NULL_RTX ) ; } </s>

Return true if anything in insn X is ( anti , output , true ) dependent on anything in insn Y .


<s> bool ARMTargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createARMISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS . The register allocator chooses GEN_OR_VSX_REGS for the allocno class if GENERAL_REGS and VSX_REGS cost is lower than the memory cost . This happens a lot when TARGET_DIRECT_MOVE makes the register move cost between GENERAL_REGS and VSX_REGS low . It might seem reasonable to use a union class . After all , if usage of vsr is low and gpr high , it might make sense to spill gpr to vsr rather than memory . However , in cases where register pressure of both is high , like the cactus_adm spec test , allowing GEN_OR_VSX_REGS as the allocno class results in bad decisions in the first scheduling pass . This is partly due to an allocno of GEN_OR_VSX_REGS wrongly contributing to the GENERAL_REGS pressure class , which gives too high a pressure for GENERAL_REGS and too low for VSX_REGS . So , force a choice of the subclass here . The best class is also the union if GENERAL_REGS and VSX_REGS have the same cost . In that case we do use GEN_OR_VSX_REGS as the allocno class , since trying to narrow down the class by regno mode is prone to error . For example , SImode is allowed in VSX regs and in some cases ( eg . gcc.target/powerpc/p9-xxbr-3.c do_bswap32_vect ) it would be wrong to choose an allocno of GENERAL_REGS based on SImode .


<s> SDValue HexagonTargetLowering :: getInt ( unsigned IntId , MVT ResTy , ArrayRef < SDValue > Ops , const SDLoc & dl , SelectionDAG & DAG ) const { SmallVector < SDValue , 4 > IntOps ; IntOps . push_back ( DAG . getConstant ( IntId , dl , MVT :: i32 ) ) ; append_range ( IntOps , Ops ) ; return DAG . getNode ( ISD :: INTRINSIC_WO_CHAIN , dl , ResTy , IntOps ) ; } </s>


<s> static rtx sparc_legitimize_pic_address ( rtx orig , rtx reg ) { if ( GET_CODE ( orig ) == SYMBOL_REF || ( GET_CODE ( orig ) == LABEL_REF && ! can_use_mov_pic_label_ref ( orig ) ) ) { bool gotdata_op = false ; rtx pic_ref , address ; rtx_insn * insn ; if ( ! reg ) { gcc_assert ( can_create_pseudo_p ( ) ) ; reg = gen_reg_rtx ( Pmode ) ; } if ( flag_pic == 2 ) { rtx temp_reg = can_create_pseudo_p ( ) ? gen_reg_rtx ( Pmode ) : reg ; if ( TARGET_ARCH64 ) { emit_insn ( gen_movdi_high_pic ( temp_reg , orig ) ) ; emit_insn ( gen_movdi_lo_sum_pic ( temp_reg , temp_reg , orig ) ) ; } else { emit_insn ( gen_movsi_high_pic ( temp_reg , orig ) ) ; emit_insn ( gen_movsi_lo_sum_pic ( temp_reg , temp_reg , orig ) ) ; } address = temp_reg ; gotdata_op = true ; } else address = orig ; crtl -> uses_pic_offset_table = 1 ; if ( gotdata_op ) { if ( TARGET_ARCH64 ) insn = emit_insn ( gen_movdi_pic_gotdata_op ( reg , pic_offset_table_rtx , address , orig ) ) ; else insn = emit_insn ( gen_movsi_pic_gotdata_op ( reg , pic_offset_table_rtx , address , orig ) ) ; } else { pic_ref = gen_const_mem ( Pmode , gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , address ) ) ; insn = emit_move_insn ( reg , pic_ref ) ; } set_unique_reg_note ( insn , REG_EQUAL , orig ) ; return reg ; } else if ( GET_CODE ( orig ) == CONST ) { rtx base , offset ; if ( GET_CODE ( XEXP ( orig , 0 ) ) == PLUS && sparc_pic_register_p ( XEXP ( XEXP ( orig , 0 ) , 0 ) ) ) return orig ; if ( ! reg ) { gcc_assert ( can_create_pseudo_p ( ) ) ; reg = gen_reg_rtx ( Pmode ) ; } gcc_assert ( GET_CODE ( XEXP ( orig , 0 ) ) == PLUS ) ; base = sparc_legitimize_pic_address ( XEXP ( XEXP ( orig , 0 ) , 0 ) , reg ) ; offset = sparc_legitimize_pic_address ( XEXP ( XEXP ( orig , 0 ) , 1 ) , base == reg ? NULL_RTX : reg ) ; if ( GET_CODE ( offset ) == CONST_INT ) { if ( SMALL_INT ( offset ) ) return plus_constant ( Pmode , base , INTVAL ( offset ) ) ; else if ( can_create_pseudo_p ( ) ) offset = force_reg ( Pmode , offset ) ; else gcc_unreachable ( ) ; } return gen_rtx_PLUS ( Pmode , base , offset ) ; } else if ( GET_CODE ( orig ) == LABEL_REF ) crtl -> uses_pic_offset_table = 1 ; return orig ; } </s>

Legitimize PIC addresses . If the address is already position-independent , we return ORIG . Newly generated position-independent addresses go into a reg . This is REG if nonzero , otherwise we allocate register ( s ) as necessary .


<s> static void mips_encode_section_info ( tree decl , rtx rtl , int first ) { default_encode_section_info ( decl , rtl , first ) ; if ( TREE_CODE ( decl ) == FUNCTION_DECL && lookup_attribute ( "long_call" , TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ) ) { rtx symbol = XEXP ( rtl , 0 ) ; SYMBOL_REF_FLAGS ( symbol ) |= SYMBOL_FLAG_LONG_CALL ; } } </s>

Set SYMBOL_REF_FLAGS for the SYMBOL_REF inside RTL , which belongs to DECL . FIRST is true if this is the first time handling this decl .


<s> static inline int atomic_alloc ( unsigned int * mask ) { unsigned int old = * mask , ret , new ; while ( 1 ) { if ( old == 0 ) return - 1 ; ret = old & - old ; new = old & ~ ret ; new = __sync_val_compare_and_swap ( mask , old , new ) ; if ( old == new ) break ; old = new ; } return __builtin_ffs ( ret ) - 1 ; } </s>

MASK is a bitmap describing the allocation state of emergency buffers , with bit set indicating free . Return > = 0 if allocation is successful ; < 0 if failure .


See whether TYPE is a record whose fields should be returned in one floating-point register and one integer register . If so , populate FIELDS accordingly .


<s> static void move_to_end_of_ready ( rtx_insn * * ready , int pos , int lastpos ) { rtx_insn * tmp ; int i ; tmp = ready [ pos ] ; for ( i = pos ; i < lastpos ; i ++ ) ready [ i ] = ready [ i + 1 ] ; ready [ lastpos ] = tmp ; } </s>

Move instruction at POS to the end of the READY list .


<s> bool X86FrameLowering :: stackProbeFunctionModifiesSP ( ) const { return STI . isOSWindows ( ) && ! STI . isTargetWin64 ( ) ; } </s>

Does the stack probe function call return with a modified stack pointer ?


<s> bool ARMBaseInstrInfo :: isCopyInstr ( const MachineInstr & MI , const MachineOperand * & Src , const MachineOperand * & Dest ) const { if ( ! MI . isMoveReg ( ) || ( MI . getOpcode ( ) == ARM :: VORRq && MI . getOperand ( 1 ) . getReg ( ) != MI . getOperand ( 2 ) . getReg ( ) ) ) return false ; Dest = & MI . getOperand ( 0 ) ; Src = & MI . getOperand ( 1 ) ; return true ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


<s> int ia64_produce_address_p ( rtx insn ) { return insn -> call ; } </s>

The following function returns TRUE if INSN produces address for a load/store insn . We will place such insns into M slot because it decreases its latency time .


<s> enum rtx_code arm_canonicalize_comparison ( enum rtx_code code , enum machine_mode mode , rtx * op1 ) { unsigned HOST_WIDE_INT i = INTVAL ( * op1 ) ; unsigned HOST_WIDE_INT maxval ; maxval = ( ( ( unsigned HOST_WIDE_INT ) 1 ) << ( GET_MODE_BITSIZE ( mode ) - 1 ) ) - 1 ; switch ( code ) { case EQ : case NE : return code ; case GT : case LE : if ( i != maxval && ( const_ok_for_arm ( i + 1 ) || const_ok_for_arm ( - ( i + 1 ) ) ) ) { * op1 = GEN_INT ( i + 1 ) ; return code == GT ? GE : LT ; } break ; case GE : case LT : if ( i != ~ maxval && ( const_ok_for_arm ( i - 1 ) || const_ok_for_arm ( - ( i - 1 ) ) ) ) { * op1 = GEN_INT ( i - 1 ) ; return code == GE ? GT : LE ; } break ; case GTU : case LEU : if ( i != ~ ( ( unsigned HOST_WIDE_INT ) 0 ) && ( const_ok_for_arm ( i + 1 ) || const_ok_for_arm ( - ( i + 1 ) ) ) ) { * op1 = GEN_INT ( i + 1 ) ; return code == GTU ? GEU : LTU ; } break ; case GEU : case LTU : if ( i != 0 && ( const_ok_for_arm ( i - 1 ) || const_ok_for_arm ( - ( i - 1 ) ) ) ) { * op1 = GEN_INT ( i - 1 ) ; return code == GEU ? GTU : LEU ; } break ; default : gcc_unreachable ( ) ; } return code ; } </s>

Canonicalize a comparison so that we are more likely to recognize it . This can be done for a few constant compares , where we can make the immediate value easier to load .


<s> void X86InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Alignment = std :: max < uint32_t > ( RC -> getSize ( ) , 16 ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , Subtarget ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) , DestReg ) , FrameIdx ) ; } </s>


<s>
SDValue
MINA32TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
llvm_unreachable
(
"LowerOperation() unimplemented"
)
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> static int s390_issue_rate ( void ) { switch ( s390_tune ) { case PROCESSOR_2084_Z990 : case PROCESSOR_2094_Z9_109 : case PROCESSOR_2094_Z9_EC : case PROCESSOR_2817_Z196 : return 3 ; case PROCESSOR_2097_Z10 : return 2 ; case PROCESSOR_9672_G5 : case PROCESSOR_9672_G6 : case PROCESSOR_2064_Z900 : case PROCESSOR_2827_ZEC12 : case PROCESSOR_2964_Z13 : case PROCESSOR_3906_Z14 : default : return 1 ; } } </s>

The number of instructions that can be issued per cycle .


<s>
const
char
*
output_call_mem
(
rtx
*
operands
)
{
gcc_assert
(
!
arm_arch5
)
;
if
(
TARGET_INTERWORK
)
{
output_asm_insn
(
"ldr%?\t%|ip, %0"
,
operands
)
;
output_asm_insn
(
"mov%?\t%|lr, %|pc"
,
operands
)
;
output_asm_insn
(
"bx%?\t%|ip"
,
operands
)
;
}
else
if
(
regno_use_in
(
LR_REGNUM
,
operands
[
0
]
)
)
{
output_asm_insn
(
"ldr%?\t%|ip, %0"
,
operands
)
;
output_asm_insn
(
"mov%?\t%|lr, %|pc"
,
operands
)
;
if
(
arm_arch4t
)
output_asm_insn
(
"bx%?\t%|ip"
,
operands
)
;
else
output_asm_insn
(
"mov%?\t%|pc, %|ip"
,
operands
)
;
}
else
{
output_asm_insn
(
"mov%?\t%|lr, %|pc"
,
operands
)
;
output_asm_insn
(
"ldr%?\t%|pc, %0"
,
operands
)
;
}
return
""
;
}
</s>

Output a 'call ' insn that is a reference in memory . This is disabled for ARMv5 and we prefer a blx instead because otherwise there 's a significant performance overhead .


<s> static bool pru_hard_regno_scratch_ok ( unsigned int regno ) { if ( ( ! reload_completed || frame_pointer_needed ) && ( IN_RANGE ( regno , HARD_FRAME_POINTER_REGNUM , HARD_FRAME_POINTER_REGNUM + 3 ) || IN_RANGE ( regno , FRAME_POINTER_REGNUM , FRAME_POINTER_REGNUM + 3 ) ) ) return false ; return true ; } </s>

Implement ` TARGET_HARD_REGNO_SCRATCH_OK ' . Returns true if REGNO is safe to be allocated as a scratch register ( for a define_peephole2 ) in the current function .


<s> void AMDGPUTargetMachine :: registerDefaultAliasAnalyses ( AAManager & AAM ) { AAM . registerFunctionAnalysis < AMDGPUAA > ( ) ; } </s>

Allow the target to register alias analyses with the AAManager for use with the new pass manager .


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = Endian == support :: little ? i : ( NumBytes - 1 ) - i ; Data [ Offset + Idx ] |= uint8_t ( ( Value >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> int xt_true_regnum ( rtx x ) { if ( REG_P ( x ) ) { if ( ! HARD_REGISTER_P ( x ) && reg_renumber && ( lra_in_progress || reg_renumber [ REGNO ( x ) ] >= 0 ) ) return reg_renumber [ REGNO ( x ) ] ; return REGNO ( x ) ; } if ( SUBREG_P ( x ) ) { int base = xt_true_regnum ( SUBREG_REG ( x ) ) ; if ( base >= 0 && HARD_REGISTER_NUM_P ( base ) ) { struct subreg_info info ; subreg_get_info ( lra_in_progress ? ( unsigned ) base : REGNO ( SUBREG_REG ( x ) ) , GET_MODE ( SUBREG_REG ( x ) ) , SUBREG_BYTE ( x ) , GET_MODE ( x ) , & info ) ; if ( info . representable_p ) return base + info . offset ; } } return - 1 ; } </s>

This is just like the standard true_regnum ( ) function except that it works even when reg_renumber is not initialized .


<s> bool SIPreEmitPeephole :: runOnMachineFunction ( MachineFunction & MF ) { const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; if ( MBBI == MBB . end ( ) ) continue ; MachineInstr & MI = * MBBI ; switch ( MI . getOpcode ( ) ) { case AMDGPU :: S_CBRANCH_VCCZ : case AMDGPU :: S_CBRANCH_VCCNZ : Changed |= optimizeVccBranch ( MI ) ; break ; default : break ; } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


"Cannot spill SGPR to memory without RegScavenger"

"Exec is already saved, refuse to save again"

prepare - Reset state and prepare for a new spill placement computation .


<s> static int nios2_compute_frame_layout ( void ) { unsigned int regno ; unsigned int save_mask = 0 ; int total_size ; int var_size ; int out_args_size ; int save_reg_size ; int callee_save_reg_size ; if ( cfun -> machine -> initialized ) return cfun -> machine -> total_size ; save_reg_size = 0 ; for ( regno = 0 ; regno <= LAST_GP_REG ; regno ++ ) if ( prologue_saved_reg_p ( regno ) ) { save_mask |= 1 << regno ; save_reg_size += 4 ; } if ( TARGET_HAS_CDX && save_reg_size != 0 ) { if ( ( save_mask & ( 1 << RA_REGNO ) ) == 0 ) { save_mask |= 1 << RA_REGNO ; save_reg_size += 4 ; } for ( regno = 23 ; regno >= 16 ; regno -- ) if ( ( save_mask & ( 1 << regno ) ) != 0 ) { unsigned int i ; for ( i = regno - 1 ; i >= 16 ; i -- ) if ( ( save_mask & ( 1 << i ) ) == 0 ) { save_mask |= 1 << i ; save_reg_size += 4 ; } break ; } } callee_save_reg_size = save_reg_size ; if ( crtl -> calls_eh_return ) { unsigned i ; unsigned r ; for ( i = 0 ; ( r = EH_RETURN_DATA_REGNO ( i ) ) != INVALID_REGNUM ; i ++ ) if ( ! ( save_mask & ( 1 << r ) ) ) { save_mask |= 1 << r ; save_reg_size += 4 ; } } cfun -> machine -> fp_save_offset = 0 ; if ( save_mask & ( 1 << HARD_FRAME_POINTER_REGNUM ) ) { int fp_save_offset = 0 ; for ( regno = 0 ; regno < HARD_FRAME_POINTER_REGNUM ; regno ++ ) if ( save_mask & ( 1 << regno ) ) fp_save_offset += 4 ; cfun -> machine -> fp_save_offset = fp_save_offset ; } var_size = NIOS2_STACK_ALIGN ( get_frame_size ( ) ) ; out_args_size = NIOS2_STACK_ALIGN ( crtl -> outgoing_args_size ) ; total_size = var_size + out_args_size ; save_reg_size = NIOS2_STACK_ALIGN ( save_reg_size ) ; total_size += save_reg_size ; total_size += NIOS2_STACK_ALIGN ( crtl -> args . pretend_args_size ) ; cfun -> machine -> save_mask = save_mask ; cfun -> machine -> total_size = total_size ; cfun -> machine -> var_size = var_size ; cfun -> machine -> args_size = out_args_size ; cfun -> machine -> save_reg_size = save_reg_size ; cfun -> machine -> callee_save_reg_size = callee_save_reg_size ; cfun -> machine -> initialized = reload_completed ; cfun -> machine -> save_regs_offset = out_args_size + var_size ; return total_size ; } </s>

Return the bytes needed to compute the frame pointer from the current stack pointer .


<s> const char * AArch64TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case AArch64ISD :: BR_CC : return "AArch64ISD::BR_CC" ; case AArch64ISD :: Call : return "AArch64ISD::Call" ; case AArch64ISD :: FPMOV : return "AArch64ISD::FPMOV" ; case AArch64ISD :: GOTLoad : return "AArch64ISD::GOTLoad" ; case AArch64ISD :: BFI : return "AArch64ISD::BFI" ; case AArch64ISD :: EXTR : return "AArch64ISD::EXTR" ; case AArch64ISD :: Ret : return "AArch64ISD::Ret" ; case AArch64ISD :: SBFX : return "AArch64ISD::SBFX" ; case AArch64ISD :: SELECT_CC : return "AArch64ISD::SELECT_CC" ; case AArch64ISD :: SETCC : return "AArch64ISD::SETCC" ; case AArch64ISD :: TC_RETURN : return "AArch64ISD::TC_RETURN" ; case AArch64ISD :: THREAD_POINTER : return "AArch64ISD::THREAD_POINTER" ; case AArch64ISD :: TLSDESCCALL : return "AArch64ISD::TLSDESCCALL" ; case AArch64ISD :: WrapperLarge : return "AArch64ISD::WrapperLarge" ; case AArch64ISD :: WrapperSmall : return "AArch64ISD::WrapperSmall" ; case AArch64ISD :: NEON_BSL : return "AArch64ISD::NEON_BSL" ; case AArch64ISD :: NEON_MOVIMM : return "AArch64ISD::NEON_MOVIMM" ; case AArch64ISD :: NEON_MVNIMM : return "AArch64ISD::NEON_MVNIMM" ; case AArch64ISD :: NEON_FMOVIMM : return "AArch64ISD::NEON_FMOVIMM" ; case AArch64ISD :: NEON_CMP : return "AArch64ISD::NEON_CMP" ; case AArch64ISD :: NEON_CMPZ : return "AArch64ISD::NEON_CMPZ" ; case AArch64ISD :: NEON_TST : return "AArch64ISD::NEON_TST" ; case AArch64ISD :: NEON_QSHLs : return "AArch64ISD::NEON_QSHLs" ; case AArch64ISD :: NEON_QSHLu : return "AArch64ISD::NEON_QSHLu" ; case AArch64ISD :: NEON_VDUP : return "AArch64ISD::NEON_VDUP" ; case AArch64ISD :: NEON_VDUPLANE : return "AArch64ISD::NEON_VDUPLANE" ; case AArch64ISD :: NEON_LD1_UPD : return "AArch64ISD::NEON_LD1_UPD" ; case AArch64ISD :: NEON_LD2_UPD : return "AArch64ISD::NEON_LD2_UPD" ; case AArch64ISD :: NEON_LD3_UPD : return "AArch64ISD::NEON_LD3_UPD" ; case AArch64ISD :: NEON_LD4_UPD : return "AArch64ISD::NEON_LD4_UPD" ; case AArch64ISD :: NEON_ST1_UPD : return "AArch64ISD::NEON_ST1_UPD" ; case AArch64ISD :: NEON_ST2_UPD : return "AArch64ISD::NEON_ST2_UPD" ; case AArch64ISD :: NEON_ST3_UPD : return "AArch64ISD::NEON_ST3_UPD" ; case AArch64ISD :: NEON_ST4_UPD : return "AArch64ISD::NEON_ST4_UPD" ; case AArch64ISD :: NEON_VEXTRACT : return "AArch64ISD::NEON_VEXTRACT" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> bool HexagonRegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { const HexagonFrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ; } </s>

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot .


<s> void GCNPassConfig :: addMachineSSAOptimization ( ) { TargetPassConfig :: addMachineSSAOptimization ( ) ; addPass ( & SIFoldOperandsID ) ; if ( EnableDPPCombine ) addPass ( & GCNDPPCombineID ) ; addPass ( & DeadMachineInstructionElimID ) ; addPass ( & SILoadStoreOptimizerID ) ; if ( EnableSDWAPeephole ) { addPass ( & SIPeepholeSDWAID ) ; addPass ( & EarlyMachineLICMID ) ; addPass ( & MachineCSEID ) ; addPass ( & SIFoldOperandsID ) ; addPass ( & DeadMachineInstructionElimID ) ; } addPass ( createSIShrinkInstructionsPass ( ) ) ; } </s>

Methods with trivial inline returns are convenient points in the common codegen pass pipeline where targets may insert passes .


<s> void vms_c_register_includes ( const char * sysroot ATTRIBUTE_UNUSED , const char * iprefix ATTRIBUTE_UNUSED , int stdinc ATTRIBUTE_UNUSED ) { } </s>

Find include modules in the include path .


<s>
void
AMDGPUInstPrinter
::
printOffset
(
const
MCInst
*
MI
,
unsigned
OpNo
,
const
MCSubtargetInfo
&
STI
,
raw_ostream
&
O
)
{
uint16_t
Imm
=
MI
->
getOperand
(
OpNo
)
.
getImm
(
)
;
if
(
Imm
!=
0
)
{
O
<<
" offset:"
;
printU16ImmDecOperand
(
MI
,
OpNo
,
O
)
;
}
}
</s>

This is just convenient handler for printing offsets .


<s> void XCoreRegisterInfo :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const { } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> static struct machine_function * or1k_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function > ( ) ; } </s>

Zero initialization is OK for all current fields .


<s> ISD :: NodeType getExtendForAtomicOps ( ) const override { return ISD :: ANY_EXTEND ; } </s>

Returns how the platform 's atomic operations are extended ( ZERO_EXTEND , SIGN_EXTEND , or ANY_EXTEND ) .


<s>
unsigned
SITargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
SelectionDAG
&
DAG
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"m0"
,
AMDGPU
::
M0
)
.
Case
(
"exec"
,
AMDGPU
::
EXEC
)
.
Case
(
"exec_lo"
,
AMDGPU
::
EXEC_LO
)
.
Case
(
"exec_hi"
,
AMDGPU
::
EXEC_HI
)
.
Case
(
"flat_scratch"
,
AMDGPU
::
FLAT_SCR
)
.
Case
(
"flat_scratch_lo"
,
AMDGPU
::
FLAT_SCR_LO
)
.
Case
(
"flat_scratch_hi"
,
AMDGPU
::
FLAT_SCR_HI
)
.
Default
(
AMDGPU
::
NoRegister
)
;
if
(
Reg
==
AMDGPU
::
NoRegister
)
{
report_fatal_error
(
Twine
(
"invalid register name \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;
}
if
(
Subtarget
->
getGeneration
(
)
==
AMDGPUSubtarget
::
SOUTHERN_ISLANDS
&&
Subtarget
->
getRegisterInfo
(
)
->
regsOverlap
(
Reg
,
AMDGPU
::
FLAT_SCR
)
)
{
report_fatal_error
(
Twine
(
"invalid register \""
+
StringRef
(
RegName
)
+
"\" for subtarget."
)
)
;
}
switch
(
Reg
)
{
case
AMDGPU
::
M0
:
case
AMDGPU
::
EXEC_LO
:
case
AMDGPU
::
EXEC_HI
:
case
AMDGPU
::
FLAT_SCR_LO
:
case
AMDGPU
::
FLAT_SCR_HI
:
if
(
VT
.
getSizeInBits
(
)
==
32
)
return
Reg
;
break
;
case
AMDGPU
::
EXEC
:
case
AMDGPU
::
FLAT_SCR
:
if
(
VT
.
getSizeInBits
(
)
==
64
)
return
Reg
;
break
;
default
:
llvm_unreachable
(
"missing register type checking"
)
;
}
report_fatal_error
(
Twine
(
"invalid type for register \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;
}
</s>

Return the register ID of the name passed in .


<s> void split_double_move ( rtx * operands , enum machine_mode mode ) { bool swap = false ; if ( GET_CODE ( operands [ 0 ] ) == REG && GET_CODE ( operands [ 1 ] ) == REG && REGNO ( operands [ 0 ] ) == REGNO ( operands [ 1 ] ) + 1 ) swap = true ; if ( GET_CODE ( operands [ 0 ] ) == REG && GET_CODE ( operands [ 1 ] ) == MEM ) { rtx op = XEXP ( operands [ 1 ] , 0 ) ; if ( GET_CODE ( op ) == SUBREG ) op = SUBREG_REG ( op ) ; if ( GET_CODE ( op ) == REG && REGNO ( op ) == REGNO ( operands [ 0 ] ) ) swap = true ; if ( GET_CODE ( op ) == PLUS ) { rtx x = XEXP ( op , 0 ) ; rtx y = XEXP ( op , 1 ) ; if ( GET_CODE ( x ) == REG && REGNO ( x ) == REGNO ( operands [ 0 ] ) ) swap = true ; if ( GET_CODE ( y ) == REG && REGNO ( y ) == REGNO ( operands [ 0 ] ) ) swap = true ; } } if ( swap ) { operands [ 2 ] = operand_subword ( operands [ 0 ] , 1 , 1 , mode ) ; operands [ 3 ] = operand_subword ( operands [ 1 ] , 1 , 1 , mode ) ; operands [ 4 ] = operand_subword ( operands [ 0 ] , 0 , 1 , mode ) ; operands [ 5 ] = operand_subword ( operands [ 1 ] , 0 , 1 , mode ) ; } else { operands [ 2 ] = operand_subword ( operands [ 0 ] , 0 , 1 , mode ) ; operands [ 3 ] = operand_subword ( operands [ 1 ] , 0 , 1 , mode ) ; operands [ 4 ] = operand_subword ( operands [ 0 ] , 1 , 1 , mode ) ; operands [ 5 ] = operand_subword ( operands [ 1 ] , 1 , 1 , mode ) ; } } </s>

Split a double move of OPERANDS in MODE .


<s> bool SILowerLiteralConstantsPass :: runOnMachineFunction ( MachineFunction & MF ) { for ( MachineFunction :: iterator BB = MF . begin ( ) , BB_E = MF . end ( ) ; BB != BB_E ; ++ BB ) { MachineBasicBlock & MBB = * BB ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , Next = llvm :: next ( I ) ; I != MBB . end ( ) ; I = Next ) { Next = llvm :: next ( I ) ; MachineInstr & MI = * I ; switch ( MI . getOpcode ( ) ) { default : break ; case AMDGPU :: S_MOV_IMM_I32 : case AMDGPU :: S_MOV_IMM_I64 : case AMDGPU :: V_MOV_IMM_F32 : case AMDGPU :: V_MOV_IMM_I32 : { unsigned MovOpcode ; unsigned LoadLiteralOpcode ; MachineOperand LiteralOp = MI . getOperand ( 1 ) ; if ( AMDGPU :: VReg_32RegClass . contains ( MI . getOperand ( 0 ) . getReg ( ) ) ) { MovOpcode = AMDGPU :: V_MOV_B32_e32 ; } else { MovOpcode = AMDGPU :: S_MOV_B32 ; } if ( LiteralOp . isImm ( ) ) { LoadLiteralOpcode = AMDGPU :: SI_LOAD_LITERAL_I32 ; } else { LoadLiteralOpcode = AMDGPU :: SI_LOAD_LITERAL_F32 ; } MIBundleBuilder Bundle ( MBB , I ) ; Bundle . append ( BuildMI ( MF , MBB . findDebugLoc ( I ) , TII -> get ( MovOpcode ) , MI . getOperand ( 0 ) . getReg ( ) ) . addReg ( AMDGPU :: SI_LITERAL_CONSTANT ) ) . append ( BuildMI ( MF , MBB . findDebugLoc ( I ) , TII -> get ( LoadLiteralOpcode ) ) . addOperand ( MI . getOperand ( 1 ) ) ) ; llvm :: finalizeBundle ( MBB , Bundle . begin ( ) ) ; MI . eraseFromParent ( ) ; break ; } } } } return false ; } </s>


<s>
MipsSubtarget
::
MipsSubtarget
(
const
std
::
string
&
TT
,
const
std
::
string
&
CPU
,
const
std
::
string
&
FS
,
bool
little
,
Reloc
::
Model
_RM
,
MipsTargetMachine
*
_TM
)
:
MipsGenSubtargetInfo
(
TT
,
CPU
,
FS
)
,
MipsArchVersion
(
Mips32
)
,
MipsABI
(
UnknownABI
)
,
IsLittle
(
little
)
,
IsSingleFloat
(
false
)
,
IsFP64bit
(
false
)
,
IsGP64bit
(
false
)
,
HasVFPU
(
false
)
,
IsLinux
(
true
)
,
HasSEInReg
(
false
)
,
HasCondMov
(
false
)
,
HasSwap
(
false
)
,
HasBitCount
(
false
)
,
HasFPIdx
(
false
)
,
InMips16Mode
(
false
)
,
InMips16HardFloat
(
Mips16HardFloat
)
,
InMicroMipsMode
(
false
)
,
HasDSP
(
false
)
,
HasDSPR2
(
false
)
,
AllowMixed16_32
(
Mixed16_32
|
Mips_Os16
)
,
Os16
(
Mips_Os16
)
,
RM
(
_RM
)
,
OverrideMode
(
NoOverride
)
,
TM
(
_TM
)
{
std
::
string
CPUName
=
CPU
;
if
(
CPUName
.
empty
(
)
)
CPUName
=
"mips32"
;
ParseSubtargetFeatures
(
CPUName
,
FS
)
;
PreviousInMips16Mode
=
InMips16Mode
;
InstrItins
=
getInstrItineraryForCPU
(
CPUName
)
;
if
(
MipsABI
==
UnknownABI
)
MipsABI
=
hasMips64
(
)
N64
:
O32
;
assert
(
(
(
!
hasMips64
(
)
&&
(
isABI_O32
(
)
||
isABI_EABI
(
)
)
)
||
(
hasMips64
(
)
&&
(
isABI_N32
(
)
||
isABI_N64
(
)
)
)
)
&&
"Invalid  Arch & ABI pair."
)
;
if
(
TT
.
find
(
"linux"
)
==
std
::
string
::
npos
)
IsLinux
=
false
;
UseSmallSection
=
!
IsLinux
&&
(
RM
==
Reloc
::
Static
)
;
}
</s>

This constructor initializes the data members to match that of the specified triple .

Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
"mips32"
Mips
Mips
Mips
Mips
Mips
Mips
Mips
"Invalid  Arch & ABI pair."
"linux"


<s> rtx neon_make_constant ( rtx vals ) { machine_mode mode = GET_MODE ( vals ) ; rtx target ; rtx const_vec = NULL_RTX ; int n_elts = GET_MODE_NUNITS ( mode ) ; int n_const = 0 ; int i ; if ( GET_CODE ( vals ) == CONST_VECTOR ) const_vec = vals ; else if ( GET_CODE ( vals ) == PARALLEL ) { for ( i = 0 ; i < n_elts ; ++ i ) { rtx x = XVECEXP ( vals , 0 , i ) ; if ( CONST_INT_P ( x ) || CONST_DOUBLE_P ( x ) ) n_const ++ ; } if ( n_const == n_elts ) const_vec = gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , 0 ) ) ; } else gcc_unreachable ( ) ; if ( const_vec != NULL && neon_immediate_valid_for_move ( const_vec , mode , NULL , NULL ) ) return const_vec ; else if ( ( target = neon_vdup_constant ( vals ) ) != NULL_RTX ) return target ; else if ( const_vec != NULL_RTX ) return const_vec ; else return NULL_RTX ; } </s>

Generate code to load VALS , which is a PARALLEL containing only constants ( for vec_init ) or CONST_VECTOR , efficiently into a register . Returns an RTX to copy into the register , or NULL_RTX for a PARALLEL that can not be converted into a CONST_VECTOR .


<s> bool aarch64_float_const_representable_p ( rtx x ) { int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1 ; int exponent ; unsigned HOST_WIDE_INT mantissa , mask ; REAL_VALUE_TYPE r , m ; bool fail ; if ( ! CONST_DOUBLE_P ( x ) ) return false ; if ( GET_MODE ( x ) == VOIDmode || ( GET_MODE ( x ) == HFmode && ! TARGET_FP_F16INST ) ) return false ; r = * CONST_DOUBLE_REAL_VALUE ( x ) ; if ( REAL_VALUE_ISINF ( r ) || REAL_VALUE_ISNAN ( r ) || REAL_VALUE_MINUS_ZERO ( r ) ) return false ; r = real_value_abs ( & r ) ; exponent = REAL_EXP ( & r ) ; real_ldexp ( & m , & r , point_pos - exponent ) ; wide_int w = real_to_integer ( & m , & fail , HOST_BITS_PER_WIDE_INT * 2 ) ; if ( w . ulow ( ) != 0 ) return false ; mantissa = w . elt ( 1 ) ; point_pos -= HOST_BITS_PER_WIDE_INT ; mask = ( ( unsigned HOST_WIDE_INT ) 1 << ( point_pos - 5 ) ) - 1 ; if ( ( mantissa & mask ) != 0 ) return false ; mantissa >>= point_pos - 5 ; if ( mantissa == 0 ) return false ; mantissa &= ~ ( 1 << 4 ) ; gcc_assert ( mantissa <= 15 ) ; exponent = 5 - exponent ; return ( exponent >= 0 && exponent <= 7 ) ; } </s>

Return true iff X can be represented by a quarter-precision floating point immediate operand X . Note , we can not represent 0.0 .


<s> std :: string BTFTypeStruct :: getName ( ) { return STy -> getName ( ) ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> void PPCFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - 1 ; bool DisableRedZone = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoRedZone ) ; if ( ! DisableRedZone && FrameSize <= 224 && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! ( Subtarget . isPPC64 ( ) && Subtarget . isSVR4ABI ( ) && spillsCR ( MF ) ) && ( ! ALIGN_STACK || MaxAlign <= TargetAlign ) ) { MFI -> setStackSize ( 0 ) ; return ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getMinCallFrameSize ( Subtarget . isPPC64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; MFI -> setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s>
SDValue
XCoreTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
isVarArg
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .

XCore
XCore
ISD::InputArg
"Unsupported calling convention"


<s> static rtx_insn * F ( rtx_insn * x ) { RTX_FRAME_RELATED_P ( x ) = 1 ; return x ; } </s>

We use this to wrap all emitted insns in the prologue , so they get the `` frame-related '' ( /f ) flag set .


<s> TargetIRAnalysis NVPTXTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( Function & ) { return TargetTransformInfo ( NVPTXTTIImpl ( this ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


<s> const uint32_t * GBZ80RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { if ( MF . getFunction ( ) . getFunctionType ( ) -> getNumParams ( ) <= 1 ) return CSR_0_1_RegMask ; else return CSR_2_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> int AMDGPUInstrInfo :: pseudoToMCOpcode ( int Opcode ) const { SIEncodingFamily Gen = subtargetEncodingFamily ( ST ) ; if ( get ( Opcode ) . TSFlags & SIInstrFlags :: SDWA ) Gen = ST . getGeneration ( ) == AMDGPUSubtarget :: GFX9 ? SIEncodingFamily :: SDWA9 : SIEncodingFamily :: SDWA ; if ( ( get ( Opcode ) . TSFlags & SIInstrFlags :: F16_ZFILL ) != 0 && ST . getGeneration ( ) >= AMDGPUSubtarget :: GFX9 ) Gen = SIEncodingFamily :: GFX9 ; int MCOp = AMDGPU :: getMCOpcode ( Opcode , Gen ) ; if ( MCOp == - 1 ) return Opcode ; if ( MCOp == ( uint16_t ) - 1 ) return - 1 ; return MCOp ; } </s>

Return a target-specific opcode if Opcode is a pseudo instruction .


<s>
unsigned
PPCTTIImpl
::
getArithmeticInstrCost
(
unsigned
Opcode
,
Type
*
Ty
,
TTI
::
OperandValueKind
Op1Info
,
TTI
::
OperandValueKind
Op2Info
,
TTI
::
OperandValueProperties
Opd1PropInfo
,
TTI
::
OperandValueProperties
Opd2PropInfo
)
{
assert
(
TLI
->
InstructionOpcodeToISD
(
Opcode
)
&&
"Invalid opcode"
)
;
return
BaseT
::
getArithmeticInstrCost
(
Opcode
,
Ty
,
Op1Info
,
Op2Info
,
Opd1PropInfo
,
Opd2PropInfo
)
;
}
</s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> std :: pair < const TargetRegisterClass * , uint8_t > X86TargetLowering :: findRepresentativeClass ( const TargetRegisterInfo * TRI , MVT VT ) const { const TargetRegisterClass * RRC = nullptr ; uint8_t Cost = 1 ; switch ( VT . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( TRI , VT ) ; case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : case MVT :: i64 : RRC = Subtarget -> is64Bit ( ) ? & X86 :: GR64RegClass : & X86 :: GR32RegClass ; break ; case MVT :: x86mmx : RRC = & X86 :: VR64RegClass ; break ; case MVT :: f32 : case MVT :: f64 : case MVT :: v16i8 : case MVT :: v8i16 : case MVT :: v4i32 : case MVT :: v2i64 : case MVT :: v4f32 : case MVT :: v2f64 : case MVT :: v32i8 : case MVT :: v8i32 : case MVT :: v4i64 : case MVT :: v8f32 : case MVT :: v4f64 : RRC = & X86 :: VR128RegClass ; break ; } return std :: make_pair ( RRC , Cost ) ; } </s>

Return the largest legal super-reg register class of the register class for the specified type and its associated `` cost '' .


<s> bool rs6000_split_128bit_ok_p ( rtx operands [ ] ) { if ( ! reload_completed ) return false ; if ( ! gpr_or_gpr_p ( operands [ 0 ] , operands [ 1 ] ) ) return false ; if ( quad_load_store_p ( operands [ 0 ] , operands [ 1 ] ) ) return false ; return true ; } </s>

Return true if a 128-bit move needs to be split .


<s> bool PPCTargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { if ( ! Subtarget . is64BitELFABI ( ) ) return false ; if ( ! CI -> isTailCall ( ) ) return false ; auto & TM = getTargetMachine ( ) ; if ( ! TM . Options . GuaranteedTailCallOpt && DisableSCO ) return false ; const Function * Callee = CI -> getCalledFunction ( ) ; if ( ! Callee || Callee -> isVarArg ( ) ) return false ; const Function * Caller = CI -> getParent ( ) -> getParent ( ) ; if ( ! areCallingConvEligibleForTCO_64SVR4 ( Caller -> getCallingConv ( ) , CI -> getCallingConv ( ) ) ) return false ; return getTargetMachine ( ) . shouldAssumeDSOLocal ( * Caller -> getParent ( ) , Callee ) ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> bool sh_ashlsi_clobbers_t_reg_p ( rtx shift_amount ) { gcc_assert ( CONST_INT_P ( shift_amount ) ) ; const int shift_amount_i = INTVAL ( shift_amount ) & 31 ; if ( shift_amount_i == 31 ) return true ; return ( ashl_lshr_seq [ shift_amount_i ] . clobbers_t & ASHL_CLOBBERS_T ) != 0 ; } </s>

Return true if a shift left consisting of 1/2/8/16 shift instructions will clobber the T bit .


<s> void setType ( GBSectionType T ) { Type = T ; } </s>


<s> static void do_load_for_compare ( rtx reg , rtx mem , machine_mode mode ) { switch ( GET_MODE ( reg ) ) { case DImode : switch ( mode ) { case QImode : emit_insn ( gen_zero_extendqidi2 ( reg , mem ) ) ; break ; case HImode : { rtx src = mem ; if ( ! BYTES_BIG_ENDIAN ) { src = gen_reg_rtx ( HImode ) ; emit_insn ( gen_bswaphi2 ( src , mem ) ) ; } emit_insn ( gen_zero_extendhidi2 ( reg , src ) ) ; break ; } case SImode : { rtx src = mem ; if ( ! BYTES_BIG_ENDIAN ) { src = gen_reg_rtx ( SImode ) ; emit_insn ( gen_bswapsi2 ( src , mem ) ) ; } emit_insn ( gen_zero_extendsidi2 ( reg , src ) ) ; } break ; case DImode : if ( ! BYTES_BIG_ENDIAN ) emit_insn ( gen_bswapdi2 ( reg , mem ) ) ; else emit_insn ( gen_movdi ( reg , mem ) ) ; break ; default : gcc_unreachable ( ) ; } break ; case SImode : switch ( mode ) { case QImode : emit_insn ( gen_zero_extendqisi2 ( reg , mem ) ) ; break ; case HImode : { rtx src = mem ; if ( ! BYTES_BIG_ENDIAN ) { src = gen_reg_rtx ( HImode ) ; emit_insn ( gen_bswaphi2 ( src , mem ) ) ; } emit_insn ( gen_zero_extendhisi2 ( reg , src ) ) ; break ; } case SImode : if ( ! BYTES_BIG_ENDIAN ) emit_insn ( gen_bswapsi2 ( reg , mem ) ) ; else emit_insn ( gen_movsi ( reg , mem ) ) ; break ; case DImode : gcc_unreachable ( ) ; break ; default : gcc_unreachable ( ) ; } break ; default : gcc_unreachable ( ) ; break ; } } </s>

Figure out the correct instructions to generate to load data for block compare . MODE is used for the read from memory , and data is zero extended if REG is wider than MODE . If LE code is being generated , bswap loads are used . REG is the destination register to move the data into . MEM is the memory block being read . MODE is the mode of memory to use for the read .


<s> unsigned VideocoreAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand * AsmOp , unsigned Kind ) { switch ( Kind ) { case MCK_ImmU5 : case MCK_ImmS6 : case MCK_ImmS16 : if ( AsmOp -> isImm ( ) ) return Match_ImmediateTooLarge ; } return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> virtual unsigned int execute ( function * ) { return move_elim_pass ( ) ; } </s>


<s> unsigned char M68kSubtarget :: classifyExternalReference ( const Module & M ) const { if ( TM . shouldAssumeDSOLocal ( M , nullptr ) ) return classifyLocalReference ( nullptr ) ; if ( isPositionIndependent ( ) ) return M68kII :: MO_GOTPCREL ; return M68kII :: MO_GOT ; } </s>

Classify a external variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < TargetPassConfig > ( ) ; ModulePass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
static
unsigned
getRegClass
(
bool
IsVgpr
,
unsigned
RegWidth
)
{
if
(
IsVgpr
)
{
switch
(
RegWidth
)
{
default
:
llvm_unreachable
(
"Unknown register width"
)
;
case
1
:
return
AMDGPU
::
VGPR_32RegClassID
;
case
2
:
return
AMDGPU
::
VReg_64RegClassID
;
case
3
:
return
AMDGPU
::
VReg_96RegClassID
;
case
4
:
return
AMDGPU
::
VReg_128RegClassID
;
case
8
:
return
AMDGPU
::
VReg_256RegClassID
;
case
16
:
return
AMDGPU
::
VReg_512RegClassID
;
}
}
switch
(
RegWidth
)
{
default
:
llvm_unreachable
(
"Unknown register width"
)
;
case
1
:
return
AMDGPU
::
SGPR_32RegClassID
;
case
2
:
return
AMDGPU
::
SGPR_64RegClassID
;
case
4
:
return
AMDGPU
::
SReg_128RegClassID
;
case
8
:
return
AMDGPU
::
SReg_256RegClassID
;
case
16
:
return
AMDGPU
::
SReg_512RegClassID
;
}
}
</s>

Given a machine instruction descriptor , returns the register class constraint for OpNum , or NULL .


<s> void ARMTargetLowering :: initializeSplitCSR ( MachineBasicBlock * Entry ) const { ARMFunctionInfo * AFI = Entry -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; AFI -> setIsSplitCSR ( true ) ; } </s>

Perform necessary initialization to handle a subset of CSRs explicitly via copies .


<s> static void microblaze_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; cum -> arg_number ++ ; switch ( mode ) { case E_VOIDmode : break ; default : gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_INT || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) ; cum -> gp_reg_found = 1 ; cum -> arg_words += ( ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ) ; break ; case E_BLKmode : cum -> gp_reg_found = 1 ; cum -> arg_words += ( ( int_size_in_bytes ( type ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ) ; break ; case E_SFmode : cum -> arg_words ++ ; if ( ! cum -> gp_reg_found && cum -> arg_number <= 2 ) cum -> fp_code += 1 << ( ( cum -> arg_number - 1 ) * 2 ) ; break ; case E_DFmode : cum -> arg_words += 2 ; if ( ! cum -> gp_reg_found && cum -> arg_number <= 2 ) cum -> fp_code += 2 << ( ( cum -> arg_number - 1 ) * 2 ) ; break ; case E_DImode : cum -> gp_reg_found = 1 ; cum -> arg_words += 2 ; break ; case E_QImode : case E_HImode : case E_SImode : case E_TImode : cum -> gp_reg_found = 1 ; cum -> arg_words ++ ; break ; } } </s>

Advance the argument to the next argument position .


<s> const MCGSCANodeMap & getNodes ( ) const { return Nodes ; } </s>

Get the list of nodes in this pi-block .


<s> void SparcDAGToDAGISel :: Select ( SDNode * N ) { SDLoc dl ( N ) ; if ( N -> isMachineOpcode ( ) ) { N -> setNodeId ( - 1 ) ; return ; } switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: INLINEASM : case ISD :: INLINEASM_BR : { if ( tryInlineAsm ( N ) ) return ; break ; } case SPISD :: GLOBAL_BASE_REG : ReplaceNode ( N , getGlobalBaseReg ( ) ) ; return ; case ISD :: SDIV : case ISD :: UDIV : { if ( N -> getValueType ( 0 ) == MVT :: i64 ) break ; SDValue DivLHS = N -> getOperand ( 0 ) ; SDValue DivRHS = N -> getOperand ( 1 ) ; SDValue TopPart ; if ( N -> getOpcode ( ) == ISD :: SDIV ) { TopPart = SDValue ( CurDAG -> getMachineNode ( SP :: SRAri , dl , MVT :: i32 , DivLHS , CurDAG -> getTargetConstant ( 31 , dl , MVT :: i32 ) ) , 0 ) ; } else { TopPart = CurDAG -> getRegister ( SP :: G0 , MVT :: i32 ) ; } TopPart = CurDAG -> getCopyToReg ( CurDAG -> getEntryNode ( ) , dl , SP :: Y , TopPart , SDValue ( ) ) . getValue ( 1 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: SDIV ? SP :: SDIVrr : SP :: UDIVrr ; CurDAG -> SelectNodeTo ( N , Opcode , MVT :: i32 , DivLHS , DivRHS , TopPart ) ; return ; } } SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> const char * VETargetLowering :: getTargetNodeName ( unsigned Opcode ) const { case VEISD :: NAME : \ return "VEISD::" # NAME ; switch ( ( VEISD :: NodeType ) Opcode ) { case VEISD :: FIRST_NUMBER : break ; TARGET_NODE_CASE ( Lo ) TARGET_NODE_CASE ( Hi ) TARGET_NODE_CASE ( GETFUNPLT ) TARGET_NODE_CASE ( GETSTACKTOP ) TARGET_NODE_CASE ( GETTLSADDR ) TARGET_NODE_CASE ( MEMBARRIER ) TARGET_NODE_CASE ( CALL ) TARGET_NODE_CASE ( RET_FLAG ) TARGET_NODE_CASE ( GLOBAL_BASE_REG ) } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

VE VE VEISD::NAME "VEISD::" VEISD::NodeType VEISD::FIRST_NUMBER


<s> Register X86TargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) const { assert ( ! isFuncletEHPersonality ( classifyEHPersonality ( PersonalityFn ) ) ) ; return Subtarget . isTarget64BitLP64 ( ) ? X86 :: RDX : X86 :: EDX ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .


<s> static section * riscv_elf_select_rtx_section ( machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ) { section * s = default_elf_select_rtx_section ( mode , x , align ) ; if ( riscv_size_ok_for_small_data_p ( GET_MODE_SIZE ( mode ) . to_constant ( ) ) ) { if ( startswith ( s -> named . name , ".rodata.cst" ) ) { char * name = ( char * ) alloca ( strlen ( s -> named . name ) + 2 ) ; sprintf ( name , ".s%s" , s -> named . name + 1 ) ; return get_section ( name , s -> named . common . flags , NULL ) ; } if ( s == data_section ) return sdata_section ; } return s ; } </s>

Return a section for X , handling small data .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> bool AArch64TargetLowering :: allowsMisalignedMemoryAccesses ( LLT Ty , unsigned AddrSpace , Align Alignment , MachineMemOperand :: Flags Flags , bool * Fast ) const { if ( Subtarget -> requiresStrictAlign ( ) ) return false ; if ( Fast ) { * Fast = ! Subtarget -> isMisaligned128StoreSlow ( ) || Ty . getSizeInBytes ( ) != 16 || Alignment <= 2 || Ty == LLT :: vector ( 2 , 64 ) ; } return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> static gimple va_list_skip_additions ( tree lhs ) { gimple stmt ; for ( ; ; ) { enum tree_code code ; stmt = SSA_NAME_DEF_STMT ( lhs ) ; if ( gimple_code ( stmt ) == GIMPLE_PHI ) return stmt ; if ( ! is_gimple_assign ( stmt ) || gimple_assign_lhs ( stmt ) != lhs ) return NULL ; if ( TREE_CODE ( gimple_assign_rhs1 ( stmt ) ) != SSA_NAME ) return stmt ; code = gimple_assign_rhs_code ( stmt ) ; if ( ! CONVERT_EXPR_CODE_P ( code ) && ( ( code != PLUS_EXPR && code != POINTER_PLUS_EXPR ) || TREE_CODE ( gimple_assign_rhs2 ( stmt ) ) != INTEGER_CST || ! tree_fits_uhwi_p ( gimple_assign_rhs2 ( stmt ) ) ) ) return stmt ; lhs = gimple_assign_rhs1 ( stmt ) ; } } </s>

Helper function for alpha_stdarg_optimize_hook . Skip over casts and constant additions .


<s> bool enableAggressiveInterleaving ( bool LoopHasReductions ) { return false ; } </s>

Do n't restrict interleaved unrolling to small loops .


<s> static rtx z8k_function_value ( const_tree valtype , const_tree fn_decl_or_type , bool outgoing ATTRIBUTE_UNUSED ) { return z8k_libcall_value ( TYPE_MODE ( valtype ) , NULL ) ; } </s>

Define how to find the value returned by a function . VALTYPE is the data type of the value ( as a tree ) . If the precise function being called is known , FUNC is its FUNCTION_DECL ; otherwise , FUNC is 0 . Two ways to return on the Z8k . in r2/rr2/rq2 for HI , SI , DI stuff or r7/rr6/rq4 stuff .


<s>
void
relaxInstruction
(
const
MCInst
&
,
llvm
::
MCInst
&
)
const
override
{
llvm_unreachable
(
"Cannot relax instructions"
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> void nvptx_record_needed_fndecl ( tree decl ) { if ( TYPE_ARG_TYPES ( TREE_TYPE ( decl ) ) == NULL_TREE ) { tree * slot = needed_fndecls_htab -> find_slot ( decl , INSERT ) ; if ( * slot == NULL ) * slot = decl ; } else nvptx_record_fndecl ( decl ) ; } </s>

Record that we need to emit a ptx decl for DECL . Either do it now , or record it for later in case we have no argument information at this point .


<s> bool arm_can_eliminate ( const int from , const int to ) { return ( ( to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM ) ? false : ( to == STACK_POINTER_REGNUM && frame_pointer_needed ) ? false : ( to == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB ) ? false : ( to == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM ) ? false : true ) ; } </s>

Given FROM and TO register numbers , say whether this elimination is allowed . Frame pointer elimination is automatically handled . All eliminations are permissible . Note that ARG_POINTER_REGNUM and HARD_FRAME_POINTER_REGNUM are in fact the same thing . If we need a frame pointer , we must eliminate FRAME_POINTER_REGNUM into HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or ARG_POINTER_REGNUM .


<s> static unsigned getIntrinsicID ( const SDNode * N ) { unsigned Opcode = N -> getOpcode ( ) ; switch ( Opcode ) { default : return Intrinsic :: not_intrinsic ; case ISD :: INTRINSIC_WO_CHAIN : { unsigned IID = cast < ConstantSDNode > ( N -> getOperand ( 0 ) ) -> getZExtValue ( ) ; if ( IID < Intrinsic :: num_intrinsics ) return IID ; return Intrinsic :: not_intrinsic ; } } } </s>

Return the target intrinsic ID of a function , or 0 .


<s> const LoongArchRegisterInfo * getRegisterInfo ( ) const override { return & RegInfo ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> int riscv_address_insns ( rtx x , machine_mode mode , bool might_split_p ) { struct riscv_address_info addr = { } ; int n = 1 ; if ( ! riscv_classify_address ( & addr , x , mode , false ) ) { return 3 ; } if ( mode != BLKmode && might_split_p ) n += ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; if ( addr . type == ADDRESS_LO_SUM ) n += riscv_symbol_insns ( addr . symbol_type ) - 1 ; return n ; } </s>

Return the number of instructions needed to load or store a value of mode MODE at address X . Return 0 if X is n't valid for MODE . Assume that multiword moves may need to be split into word moves if MIGHT_SPLIT_P , otherwise assume that a single load or store is enough .


"Slot for FP register must be last in order to be found!"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> void insert ( const GepNode * N ) { Map . insert ( std :: make_pair ( N , ++ LastNum ) ) ; } </s>

insert - Append entry to the vector if it does n't already exist .


<s> const TargetRegisterClass * TLCS900RegisterInfo :: getPointerRegClass ( unsigned Kind ) const { return & TLCS900 :: GR16RegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> const char * getPassName ( ) const override { return AARCH64_LOAD_STORE_OPT_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> bool M680x0AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { MMFI = MF . getInfo < M680x0MachineFunctionInfo > ( ) ; MCInstLowering = make_unique < M680x0MCInstLower > ( MF , * this ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s>
bool
ARMTargetLowering
::
allowTruncateForTailCall
(
Type
*
Ty1
,
Type
*
Ty2
)
const
{
if
(
!
Ty1
->
isIntegerTy
(
)
||
!
Ty2
->
isIntegerTy
(
)
)
return
false
;
if
(
!
isTypeLegal
(
EVT
::
getEVT
(
Ty1
)
)
)
return
false
;
assert
(
Ty1
->
getPrimitiveSizeInBits
(
)
<=
64
&&
"i128 is probably not a noop"
)
;
return
true
;
}
</s>

Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail position .

ARM
ARM
64
"i128 is probably not a noop"


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Hexagon Expand Predicate Spill Code"
;
}
</s>

Hexagon
"Hexagon Expand Predicate Spill Code"


<s> static void mips_epilogue_set_cfa ( rtx reg , HOST_WIDE_INT offset ) { rtx_insn * insn ; insn = mips_epilogue_emit_cfa_restores ( ) ; if ( reg != mips_epilogue . cfa_reg || offset != mips_epilogue . cfa_offset ) { RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = alloc_reg_note ( REG_CFA_DEF_CFA , plus_constant ( Pmode , reg , offset ) , REG_NOTES ( insn ) ) ; mips_epilogue . cfa_reg = reg ; mips_epilogue . cfa_offset = offset ; } } </s>

Like mips_epilogue_emit_cfa_restores , but also record that the CFA is now at REG + OFFSET .


<s> bool arm_validize_comparison ( rtx * comparison , rtx * op1 , rtx * op2 ) { enum rtx_code code = GET_CODE ( * comparison ) ; int code_int ; machine_mode mode = ( GET_MODE ( * op1 ) == VOIDmode ) ? GET_MODE ( * op2 ) : GET_MODE ( * op1 ) ; gcc_assert ( GET_MODE ( * op1 ) != VOIDmode || GET_MODE ( * op2 ) != VOIDmode ) ; if ( code == UNEQ || code == LTGT ) return false ; code_int = ( int ) code ; arm_canonicalize_comparison ( & code_int , op1 , op2 , 0 ) ; PUT_CODE ( * comparison , ( enum rtx_code ) code_int ) ; switch ( mode ) { case E_SImode : if ( ! arm_add_operand ( * op1 , mode ) ) * op1 = force_reg ( mode , * op1 ) ; if ( ! arm_add_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; return true ; case E_DImode : return true ; case E_HFmode : if ( ! TARGET_VFP_FP16INST ) break ; mode = SFmode ; * op1 = convert_to_mode ( mode , * op1 , 1 ) ; * op2 = convert_to_mode ( mode , * op2 , 1 ) ; case E_SFmode : case E_DFmode : if ( ! vfp_compare_operand ( * op1 , mode ) ) * op1 = force_reg ( mode , * op1 ) ; if ( ! vfp_compare_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; return true ; default : break ; } return false ; } </s>

Returns true if a valid comparison operation and makes the operands in a form that is valid .


<s>
bool
processBlock
(
MachineBasicBlock
&
MBB
)
{
bool
Changed
=
false
;
bool
Is64Bit
=
MBB
.
getParent
(
)
->
getSubtarget
<
PPCSubtarget
>
(
)
.
isPPC64
(
)
;
for
(
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
,
IE
=
MBB
.
end
(
)
;
I
!=
IE
;
)
{
MachineInstr
*
MI
=
I
;
if
(
MI
->
getOpcode
(
)
!=
PPC
::
ADDItlsgdLADDR
&&
MI
->
getOpcode
(
)
!=
PPC
::
ADDItlsldLADDR
&&
MI
->
getOpcode
(
)
!=
PPC
::
ADDItlsgdLADDR32
&&
MI
->
getOpcode
(
)
!=
PPC
::
ADDItlsldLADDR32
)
{
++
I
;
continue
;
}
DEBUG
(
dbgs
(
)
<<
"TLS Dynamic Call Fixup:\n    "
<<
*
MI
;
)
;
unsigned
OutReg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
unsigned
InReg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
DebugLoc
DL
=
MI
->
getDebugLoc
(
)
;
unsigned
GPR3
=
Is64Bit
PPC
::
X3
:
PPC
::
R3
;
unsigned
Opc1
,
Opc2
;
SmallVector
<
unsigned
,
4
>
OrigRegs
;
OrigRegs
.
push_back
(
OutReg
)
;
OrigRegs
.
push_back
(
InReg
)
;
OrigRegs
.
push_back
(
GPR3
)
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Opcode inconsistency error"
)
;
case
PPC
::
ADDItlsgdLADDR
:
Opc1
=
PPC
::
ADDItlsgdL
;
Opc2
=
PPC
::
GETtlsADDR
;
break
;
case
PPC
::
ADDItlsldLADDR
:
Opc1
=
PPC
::
ADDItlsldL
;
Opc2
=
PPC
::
GETtlsldADDR
;
break
;
case
PPC
::
ADDItlsgdLADDR32
:
Opc1
=
PPC
::
ADDItlsgdL32
;
Opc2
=
PPC
::
GETtlsADDR32
;
break
;
case
PPC
::
ADDItlsldLADDR32
:
Opc1
=
PPC
::
ADDItlsldL32
;
Opc2
=
PPC
::
GETtlsldADDR32
;
break
;
}
MachineInstr
*
Addi
=
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
Opc1
)
,
GPR3
)
.
addReg
(
InReg
)
;
Addi
->
addOperand
(
MI
->
getOperand
(
2
)
)
;
MachineBasicBlock
::
iterator
First
=
I
;
First
;
MachineInstr
*
Call
=
(
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
Opc2
)
,
GPR3
)
.
addReg
(
GPR3
)
)
;
Call
->
addOperand
(
MI
->
getOperand
(
3
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
TargetOpcode
::
COPY
)
,
OutReg
)
.
addReg
(
GPR3
)
;
MachineBasicBlock
::
iterator
Last
=
I
;
Last
;
++
I
;
MI
->
removeFromParent
(
)
;
LIS
->
repairIntervalsInRange
(
&
MBB
,
First
,
Last
,
OrigRegs
)
;
Changed
=
true
;
}
return
Changed
;
}
</s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .