<s> unsigned HexagonInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case Hexagon :: L2_loadrb_io : case Hexagon :: L2_loadrub_io : case Hexagon :: L2_loadrh_io : case Hexagon :: L2_loadruh_io : case Hexagon :: L2_loadri_io : case Hexagon :: L2_loadrd_io : case Hexagon :: V6_vL32b_ai : case Hexagon :: V6_vL32b_ai_128B : case Hexagon :: V6_vL32Ub_ai : case Hexagon :: V6_vL32Ub_ai_128B : case Hexagon :: LDriw_pred : case Hexagon :: LDriw_mod : case Hexagon :: LDriq_pred_V6 : case Hexagon :: LDriq_pred_vec_V6 : case Hexagon :: LDriv_pseudo_V6 : case Hexagon :: LDrivv_pseudo_V6 : case Hexagon :: LDriq_pred_V6_128B : case Hexagon :: LDriq_pred_vec_V6_128B : case Hexagon :: LDriv_pseudo_V6_128B : case Hexagon :: LDrivv_pseudo_V6_128B : { const MachineOperand OpFI = MI -> getOperand ( 1 ) ; if ( ! OpFI . isFI ( ) ) return 0 ; const MachineOperand OpOff = MI -> getOperand ( 2 ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != 0 ) return 0 ; FrameIndex = OpFI . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } case Hexagon :: L2_ploadrbt_io : case Hexagon :: L2_ploadrbf_io : case Hexagon :: L2_ploadrubt_io : case Hexagon :: L2_ploadrubf_io : case Hexagon :: L2_ploadrht_io : case Hexagon :: L2_ploadrhf_io : case Hexagon :: L2_ploadruht_io : case Hexagon :: L2_ploadruhf_io : case Hexagon :: L2_ploadrit_io : case Hexagon :: L2_ploadrif_io : case Hexagon :: L2_ploadrdt_io : case Hexagon :: L2_ploadrdf_io : { const MachineOperand OpFI = MI -> getOperand ( 2 ) ; if ( ! OpFI . isFI ( ) ) return 0 ; const MachineOperand OpOff = MI -> getOperand ( 3 ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != 0 ) return 0 ; FrameIndex = OpFI . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> void RISCVPassConfig :: addPreEmitPass2 ( ) { addPass ( createRISCVExpandPseudoPass ( ) ) ; } </s>

Targets may add passes immediately before machine code is emitted in this callback .


"Code generation for MIPS-I is not implemented"

"Code generation for MIPS-II is not implemented"

"Code generation for MIPS-III is not implemented"

"Code generation for MIPS-V is not implemented"

"MSA requires a 64-bit FPU register file (FR=1 mode). "

This constructor initializes the data members to match that of the specified triple .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Patmos Single-Path Reducer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool SNESTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { int64_t Offs = AM . BaseOffs ; if ( AM . BaseGV && ! AM . HasBaseReg && AM . Scale == 0 && Offs == 0 ) { return true ; } if ( isa < PointerType > ( Ty ) && AS == SNES :: ProgramMemory ) { return false ; } if ( Offs < 0 ) Offs = - Offs ; if ( AM . BaseGV == 0 && AM . HasBaseReg && AM . Scale == 0 && isUInt < 6 > ( Offs ) ) { return true ; } return false ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> static rtx nvptx_function_incoming_arg ( cumulative_args_t cum_v , machine_mode mode , const_tree , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( mode == VOIDmode ) return NULL_RTX ; if ( ! named ) return NULL_RTX ; return gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , GEN_INT ( 1 + cum -> count ) ) , UNSPEC_ARG_REG ) ; } </s>


"loadRegFromStackSlot didn't insert any code!"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s>
void
GBZ80DAGToDAGISel
::
Select
(
SDNode
*
N
)
{
LLVM_DEBUG
(
errs
(
)
<<
"Selecting: "
;
N
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
N
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
errs
(
)
<<
"== "
;
N
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
N
->
setNodeId
(
1
)
;
return
;
}
if
(
trySelect
(
N
)
)
return
;
SelectCode
(
N
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

GBZ80
GB
"Selecting: "
"\n"
"== "
"\n"
1


<s> int HexagonMCInstrInfo :: getMaxValue ( MCInstrInfo const & MCII , MCInst const & MCI ) { const uint64_t F = HexagonMCInstrInfo :: getDesc ( MCII , MCI ) . TSFlags ; bool S = ( F >> HexagonII :: ExtentSignedPos ) & HexagonII :: ExtentSignedMask ; assert ( HexagonMCInstrInfo :: isExtendable ( MCII , MCI ) || HexagonMCInstrInfo :: isExtended ( MCII , MCI ) ) ; if ( S ) return ( 1 << ( HexagonMCInstrInfo :: getExtentBits ( MCII , MCI ) - 1 ) ) - 1 ; return ( 1 << HexagonMCInstrInfo :: getExtentBits ( MCII , MCI ) ) - 1 ; } </s>

Return the maximal unsigned value possible given these KnownBits .


<s> void rs6000_split_compare_and_swap ( rtx retval , rtx mem , rtx oldval , rtx newval , rtx scratch ) { enum machine_mode mode = GET_MODE ( mem ) ; rtx label1 , label2 , x , cond = gen_rtx_REG ( CCmode , CR0_REGNO ) ; emit_insn ( gen_memory_barrier ( ) ) ; label1 = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; label2 = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label1 , 0 ) ) ; emit_load_locked ( mode , retval , mem ) ; x = gen_rtx_COMPARE ( CCmode , retval , oldval ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cond , x ) ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label2 ) ; emit_move_insn ( scratch , newval ) ; emit_store_conditional ( mode , cond , mem , scratch ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label1 ) ; emit_insn ( gen_isync ( ) ) ; emit_label ( XEXP ( label2 , 0 ) ) ; } </s>

Expand an atomic compare and swap operation . MEM is the memory on which to operate . OLDVAL is the old value to be compared . NEWVAL is the new value to be stored . SCRATCH is a scratch GPR .


<s> void ARMBaseRegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , unsigned PredReg ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: LDRcp ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( 0 ) . addImm ( Pred ) . addReg ( PredReg ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s> void ARMBranchTargets :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void MipsPassConfig :: addPreRegAlloc ( ) { addPass ( createMipsOptimizePICCallPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> void HexagonAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst MCI ; HexagonLowerToMC ( MI , MCI , * this ) ; OutStreamer . EmitInstruction ( MCI ) ; return ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> int mmix_shiftable_wyde_value ( unsigned HOST_WIDEST_INT value ) { int i ; int has_candidate = 0 ; for ( i = 0 ; i < 4 ; i ++ ) { if ( value & 65535 ) { if ( has_candidate ) return 0 ; else has_candidate = 1 ; } value >>= 16 ; } return 1 ; } </s>

Return 1 if value is 0 .. 65535 * 2 * * ( 16 * N ) for N=0 .. 3. else return 0 .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"SI Lower i1 Copies"
;
}
</s>


<s> void s390_expand_atomic ( enum machine_mode mode , enum rtx_code code , rtx target , rtx mem , rtx val , bool after ) { struct alignment_context ac ; rtx cmp ; rtx new = gen_reg_rtx ( SImode ) ; rtx orig = gen_reg_rtx ( SImode ) ; rtx csloop = gen_label_rtx ( ) ; gcc_assert ( ! target || register_operand ( target , VOIDmode ) ) ; gcc_assert ( MEM_P ( mem ) ) ; init_alignment_context ( & ac , mem , mode ) ; if ( ! ( ac . aligned && code == SET && MEM_P ( val ) ) ) val = s390_expand_mask_and_shift ( val , mode , ac . shift ) ; if ( code == PLUS || code == MINUS ) emit_move_insn ( orig , val ) ; else if ( code == MULT || code == AND ) val = expand_simple_binop ( SImode , XOR , val , ac . modemaski , NULL_RTX , 1 , OPTAB_DIRECT ) ; cmp = force_reg ( SImode , ac . memsi ) ; emit_label ( csloop ) ; emit_move_insn ( new , cmp ) ; switch ( code ) { case PLUS : case MINUS : val = expand_simple_binop ( SImode , code , new , orig , NULL_RTX , 1 , OPTAB_DIRECT ) ; val = expand_simple_binop ( SImode , AND , val , ac . modemask , NULL_RTX , 1 , OPTAB_DIRECT ) ; case SET : if ( ac . aligned && MEM_P ( val ) ) store_bit_field ( new , GET_MODE_BITSIZE ( mode ) , 0 , SImode , val ) ; else { new = expand_simple_binop ( SImode , AND , new , ac . modemaski , NULL_RTX , 1 , OPTAB_DIRECT ) ; new = expand_simple_binop ( SImode , IOR , new , val , NULL_RTX , 1 , OPTAB_DIRECT ) ; } break ; case AND : case IOR : case XOR : new = expand_simple_binop ( SImode , code , new , val , NULL_RTX , 1 , OPTAB_DIRECT ) ; break ; case MULT : new = expand_simple_binop ( SImode , XOR , new , ac . modemask , NULL_RTX , 1 , OPTAB_DIRECT ) ; new = expand_simple_binop ( SImode , AND , new , val , NULL_RTX , 1 , OPTAB_DIRECT ) ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen_sync_compare_and_swap_ccsi ( cmp , ac . memsi , cmp , new ) ) ; s390_emit_jump ( csloop , gen_rtx_fmt_ee ( NE , CCZ1mode , gen_rtx_REG ( CCZ1mode , CC_REGNUM ) , const0_rtx ) ) ; if ( target ) convert_move ( target , expand_simple_binop ( SImode , LSHIFTRT , after ? new : cmp , ac . shift , NULL_RTX , 1 , OPTAB_DIRECT ) , 1 ) ; } </s>

Expand an atomic operation CODE of mode MODE . MEM is the memory location and VAL the value to play with . If AFTER is true then store the the value MEM holds after the operation , if AFTER is false then store the value MEM holds before the operation . If TARGET is zero then discard that value , else store it to TARGET .


<s>
SICSubtarget
&
SICSubtarget
::
initializeSubtargetDependencies
(
StringRef
CPU
,
StringRef
FS
,
const
TargetMachine
&
TM
)
{
if
(
TargetTriple
.
getArch
(
)
==
Triple
::
sic
)
{
if
(
CPU
.
empty
(
)
||
CPU
==
"generic"
)
{
CPU
=
"sicxe"
;
}
else
if
(
CPU
==
"help"
)
{
CPU
=
""
;
return
*
this
;
}
else
if
(
CPU
!=
"sicse"
&&
CPU
!=
"sicxe"
)
{
CPU
=
"sicxe"
;
}
}
else
{
errs
(
)
<<
"!!!Error, TargetTriple.getArch() = "
<<
TargetTriple
.
getArch
(
)
<<
"CPU = "
<<
CPU
<<
"\n"
;
exit
(
0
)
;
}
if
(
CPU
==
"sicse"
)
SICArchVersion
=
SICSE
;
else
if
(
CPU
==
"sicxe"
)
SICArchVersion
=
SICXE
;
ParseSubtargetFeatures
(
CPU
,
FS
)
;
InstrItins
=
getInstrItineraryForCPU
(
CPU
)
;
return
*
this
;
}
</s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .

SIC
SIC
SIC
"generic"
"sicxe"
"help"
""
"sicse"
"sicxe"
"sicxe"
"!!!Error, TargetTriple.getArch() = "
"CPU = "
"\n"
0
"sicse"
SIC
SIC
"sicxe"
SIC
SIC


<s> bool AMDGPUInstrInfo :: hasLoadFromStackSlot ( const MachineInstr * MI , const MachineMemOperand * & MMO , int & FrameIndex ) const { return false ; } </s>

If the specified machine instruction has a load from a stack slot , return true along with the FrameIndices of the loaded stack slot and the machine mem operands containing the reference .


<s>
bool
runOnMachineFunction
(
MachineFunction
&
F
)
{
bool
Changed
=
false
;
if
(
TM
.
getSubtargetImpl
(
)
->
getCFLType
(
)
!=
PatmosSubtarget
::
CFL_DELAYED
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"\n[DelaySlotKiller] "
<<
F
.
getFunction
(
)
.
getName
(
)
<<
"\n"
)
;
for
(
MachineFunction
::
iterator
FI
=
F
.
begin
(
)
,
FE
=
F
.
end
(
)
;
FI
!=
FE
;
++
FI
)
Changed
|=
killDelaySlots
(
*
FI
)
;
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

Patmos
Patmos
"\n[DelaySlotKiller] "
"\n"


<s> static inline ChildIteratorType child_begin ( NodeType * N ) { return N -> getChildren ( ) . begin ( ) ; } </s>

nodes_iterator/begin/end - Allow iteration over all nodes in the graph


<s> void sparc_emit_membar_for_model ( enum memmodel model , int load_store , int before_after ) { const int LoadLoad = 1 ; const int StoreLoad = 2 ; const int LoadStore = 4 ; const int StoreStore = 8 ; int mm = 0 , implied = 0 ; switch ( sparc_memory_model ) { case SMM_SC : implied = LoadLoad | StoreLoad | LoadStore | StoreStore ; break ; case SMM_TSO : implied |= StoreStore ; if ( load_store == 3 && before_after == 1 ) implied |= StoreLoad ; case SMM_PSO : implied |= LoadLoad | LoadStore ; if ( load_store == 3 && before_after == 2 ) implied |= StoreLoad | StoreStore ; case SMM_RMO : break ; default : gcc_unreachable ( ) ; } if ( before_after & 1 ) { if ( is_mm_release ( model ) || is_mm_acq_rel ( model ) || is_mm_seq_cst ( model ) ) { if ( load_store & 1 ) mm |= LoadLoad | StoreLoad ; if ( load_store & 2 ) mm |= LoadStore | StoreStore ; } } if ( before_after & 2 ) { if ( is_mm_acquire ( model ) || is_mm_acq_rel ( model ) || is_mm_seq_cst ( model ) ) { if ( load_store & 1 ) mm |= LoadLoad | LoadStore ; if ( load_store & 2 ) mm |= StoreLoad | StoreStore ; } } mm &= ~ implied ; if ( mm || before_after == 3 ) emit_insn ( gen_membar ( GEN_INT ( mm ) ) ) ; } </s>

Expand a membar instruction for various use cases . Both the LOAD_STORE and BEFORE_AFTER arguments of the form X_Y . They are two-bit masks where bit 0 indicates that X is true , and bit 1 indicates Y is true .


<s> void MipsAsmPrinter :: emitFrameDirective ( ) { const TargetRegisterInfo & RI = * TM . getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) -> getStackSize ( ) ; OutStreamer . EmitRawText ( "\t.frame\t$" + Twine ( LowercaseString ( MipsInstPrinter :: getRegisterName ( stackReg ) ) ) + "," + Twine ( stackSize ) + ",$" + Twine ( LowercaseString ( MipsInstPrinter :: getRegisterName ( returnReg ) ) ) ) ; } </s>

Mips Mips "\t.frame\t$" Mips "," ",$" Mips


"Can't currently support varsize stack frame"

"Can't insert epilogue before non-ret insn"


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) -> findAssociatedFragment ( ) ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s> rtx rs6000_gen_lvx ( enum machine_mode mode , rtx dest_exp , rtx src_exp ) { rtx lvx ; if ( mode == V16QImode ) lvx = gen_altivec_lvx_v16qi ( dest_exp , src_exp ) ; else if ( mode == V8HImode ) lvx = gen_altivec_lvx_v8hi ( dest_exp , src_exp ) ; else if ( mode == V8HFmode ) lvx = gen_altivec_lvx_v8hf ( dest_exp , src_exp ) ; else if ( mode == V4SImode ) lvx = gen_altivec_lvx_v4si ( dest_exp , src_exp ) ; else if ( mode == V4SFmode ) lvx = gen_altivec_lvx_v4sf ( dest_exp , src_exp ) ; else if ( mode == V2DImode ) lvx = gen_altivec_lvx_v2di ( dest_exp , src_exp ) ; else if ( mode == V2DFmode ) lvx = gen_altivec_lvx_v2df ( dest_exp , src_exp ) ; else if ( mode == V1TImode ) lvx = gen_altivec_lvx_v1ti ( dest_exp , src_exp ) ; else gcc_unreachable ( ) ; rtx new_mem_exp = SET_SRC ( PATTERN ( lvx ) ) ; mimic_memory_attributes_and_flags ( new_mem_exp , src_exp ) ; return lvx ; } </s>

Generate an rtx expression to represent use of the lvx insn to load from memory SRC_EXP into register DEST_EXP with vector mode MODE .


<s> unsigned getMaxInlineSizeThreshold ( ) const { return MaxInlineSizeThreshold ; } </s>

Returns the maximum memset / memcpy size that still makes it profitable to inline the call .


<s> const BPFTargetMachine & getTargetMachine ( ) { return static_cast < const BPFTargetMachine & > ( TM ) ; } </s>

Return the target machine ( if available ) .


<s> int m32c_trampoline_size ( void ) { return TARGET_A16 ? 8 : 10 ; } </s>


<s> rtx ix86_split_stack_guard ( void ) { int offset ; addr_space_t as = DEFAULT_TLS_SEG_REG ; rtx r ; gcc_assert ( flag_split_stack ) ; offset = TARGET_THREAD_SPLIT_STACK_OFFSET ; gcc_unreachable ( ) ; r = GEN_INT ( offset ) ; r = gen_const_mem ( Pmode , r ) ; set_mem_addr_space ( r , as ) ; return r ; } </s>

Return location of the stack guard value in the TLS block .


<s> static bool write_return_type ( std :: stringstream & s , bool for_proto , tree type ) { machine_mode mode = TYPE_MODE ( type ) ; if ( mode == VOIDmode ) return false ; bool return_in_mem = pass_in_memory ( mode , type , true ) ; if ( return_in_mem ) { if ( for_proto ) return return_in_mem ; mode = ( machine_mode ) cfun -> machine -> return_mode ; if ( mode == VOIDmode ) return return_in_mem ; cfun -> machine -> return_mode = VOIDmode ; } else mode = promote_return ( mode ) ; write_return_mode ( s , for_proto , mode ) ; return return_in_mem ; } </s>

Process a function return TYPE to emit a PTX return as a prototype or function prologue declaration . Returns true if return is via an additional pointer parameter . The promotion behavior here must match the regular GCC function return mashalling .


<s> unsigned KudeyarRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? Kudeyar :: FP : Kudeyar :: SP ; } </s>


<s>
bool
SILoadStoreOptimizer
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
const
TargetSubtargetInfo
*
STM
=
MF
.
getTarget
(
)
.
getSubtargetImpl
(
)
;
TRI
=
static_cast
<
const
SIRegisterInfo
*
>
(
STM
->
getRegisterInfo
(
)
)
;
TII
=
static_cast
<
const
SIInstrInfo
*
>
(
STM
->
getInstrInfo
(
)
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
LIS
=
&
getAnalysis
<
LiveIntervals
>
(
)
;
DEBUG
(
dbgs
(
)
<<
"Running SILoadStoreOptimizer\n"
)
;
assert
(
!
MRI
->
isSSA
(
)
)
;
bool
Modified
=
false
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
Modified
|=
optimizeBlock
(
MBB
)
;
return
Modified
;
}
</s>

R600
SI
SI
SI
"Running SILoadStoreOptimizer\n"


<s> int nios2_can_use_return_insn ( void ) { int total_frame_size ; if ( ! reload_completed || crtl -> profile ) return 0 ; total_frame_size = nios2_compute_frame_layout ( ) ; if ( TARGET_HAS_CDX && ! frame_pointer_needed && cfun -> machine -> save_regs_offset <= 60 && ( cfun -> machine -> save_mask & 0x80000000 ) != 0 && ( cfun -> machine -> save_mask & 0xffff ) == 0 && crtl -> args . pretend_args_size == 0 ) return true ; return total_frame_size == 0 ; } </s>

Return nonzero if this function is known to have a null epilogue . This allows the optimizer to omit jumps to jumps if no stack was created .


<s>
void
Z80DAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
if
(
Node
->
isMachineOpcode
(
)
)
{
Node
->
setNodeId
(
1
)
;
return
;
}
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
MVT
XLenVT
=
MVT
::
i16
;
SDLoc
DL
(
Node
)
;
EVT
VT
=
Node
->
getValueType
(
0
)
;
switch
(
Opcode
)
{
case
ISD
::
Constant
:
{
auto
ConstNode
=
cast
<
ConstantSDNode
>
(
Node
)
;
int64_t
Imm
=
ConstNode
->
getSExtValue
(
)
;
if
(
VT
==
MVT
::
i16
||
VT
==
MVT
::
i8
)
{
ReplaceNode
(
Node
,
selectImm
(
CurDAG
,
SDLoc
(
Node
)
,
Imm
,
VT
)
)
;
return
;
}
break
;
}
case
ISD
::
FrameIndex
:
{
int
FI
=
cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
VT
)
;
assert
(
VT
==
MVT
::
i16
&&
"VT should be a pointer type size"
)
;
ReplaceNode
(
Node
,
CurDAG
->
getMachineNode
(
Z80
::
LD16ri
,
DL
,
VT
,
TFI
)
)
;
return
;
}
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> static void arm_asm_emit_except_personality ( rtx personality ) { fputs ( "\t.personality\t" , asm_out_file ) ; output_addr_const ( asm_out_file , personality ) ; fputc ( '\n' , asm_out_file ) ; } </s>


<s> void setError ( unsigned Err ) { Error = Err ; } </s>


<s> int AMDGPUTTIImpl :: getMinMaxReductionCost ( Type * Ty , Type * CondTy , bool IsPairwise , bool IsUnsigned ) { EVT OrigTy = TLI -> getValueType ( DL , Ty ) ; if ( IsPairwise || ! ST -> hasVOP3PInsts ( ) || OrigTy . getScalarSizeInBits ( ) != 16 ) return BaseT :: getMinMaxReductionCost ( Ty , CondTy , IsPairwise , IsUnsigned ) ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; return LT . first * getHalfRateInstrCost ( ) ; } </s>

Try to calculate op costs for min/max reduction operations .


<s> StringRef X86TargetLowering :: getStackProbeSymbolName ( MachineFunction & MF ) const { if ( MF . getFunction ( ) . hasFnAttribute ( "probe-stack" ) ) return MF . getFunction ( ) . getFnAttribute ( "probe-stack" ) . getValueAsString ( ) ; if ( ! Subtarget . isOSWindows ( ) || Subtarget . isTargetMachO ( ) ) return "" ; if ( Subtarget . is64Bit ( ) ) return Subtarget . isTargetCygMing ( ) ? "___chkstk_ms" : "__chkstk" ; return Subtarget . isTargetCygMing ( ) ? "_alloca" : "_chkstk" ; } </s>

Returns the name of the symbol used to emit stack probes or the empty string if not applicable .


<s> EVT SITargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , const AttributeList & FuncAttributes ) const { if ( Size >= 16 && DstAlign >= 4 ) return MVT :: v4i32 ; if ( Size >= 8 && DstAlign >= 4 ) return MVT :: v2i32 ; return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> static bool aarch64_optab_supported_p ( int op , machine_mode , machine_mode , optimization_type opt_type ) { switch ( op ) { case rsqrt_optab : return opt_type == OPTIMIZE_FOR_SPEED && use_rsqrt_p ( ) ; default : return true ; } } </s>

Implement the TARGET_OPTAB_SUPPORTED_P hook .


<s> void R600TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { switch ( N -> getOpcode ( ) ) { default : AMDGPUTargetLowering :: ReplaceNodeResults ( N , Results , DAG ) ; return ; case ISD :: FP_TO_UINT : if ( N -> getValueType ( 0 ) == MVT :: i1 ) { Results . push_back ( lowerFP_TO_UINT ( N -> getOperand ( 0 ) , DAG ) ) ; return ; } case ISD :: FP_TO_SINT : { if ( N -> getValueType ( 0 ) == MVT :: i1 ) { Results . push_back ( lowerFP_TO_SINT ( N -> getOperand ( 0 ) , DAG ) ) ; return ; } SDValue Result ; if ( expandFP_TO_SINT ( N , Result , DAG ) ) Results . push_back ( Result ) ; return ; } case ISD :: SDIVREM : { SDValue Op = SDValue ( N , 1 ) ; SDValue RES = LowerSDIVREM ( Op , DAG ) ; Results . push_back ( RES ) ; Results . push_back ( RES . getValue ( 1 ) ) ; break ; } case ISD :: UDIVREM : { SDValue Op = SDValue ( N , 0 ) ; LowerUDIVREM64 ( Op , DAG , Results ) ; break ; } } } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> TargetLowering :: AtomicExpansionKind SparcTargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { if ( AI -> getOperation ( ) == AtomicRMWInst :: Xchg && AI -> getType ( ) -> getPrimitiveSizeInBits ( ) == 32 ) return AtomicExpansionKind :: None ; return AtomicExpansionKind :: CmpXChg ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s>
void
dump
(
)
{
errs
(
)
<<
"DCPU16ISelAddressMode "
<<
this
<<
'\n'
;
if
(
BaseType
==
RegBase
&&
Base
.
Reg
.
getNode
(
)
!=
0
)
{
errs
(
)
<<
"Base.Reg "
;
Base
.
Reg
.
getNode
(
)
->
dump
(
)
;
}
else
if
(
BaseType
==
FrameIndexBase
)
{
errs
(
)
<<
" Base.FrameIndex "
<<
Base
.
FrameIndex
<<
'\n'
;
}
errs
(
)
<<
" Disp "
<<
Disp
<<
'\n'
;
if
(
GV
)
{
errs
(
)
<<
"GV "
;
GV
->
dump
(
)
;
}
else
if
(
CP
)
{
errs
(
)
<<
" CP "
;
CP
->
dump
(
)
;
errs
(
)
<<
" Align"
<<
Align
<<
'\n'
;
}
else
if
(
ES
)
{
errs
(
)
<<
"ES "
;
errs
(
)
<<
ES
<<
'\n'
;
}
else
if
(
JT
!=
1
)
errs
(
)
<<
" JT"
<<
JT
<<
" Align"
<<
Align
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

Dcpu16
"DCPU16ISelAddressMode "
0
"Base.Reg "
" Base.FrameIndex "
" Disp "
"GV "
" CP "
" Align"
"ES "
1
" JT"
" Align"


<s>
MachineBasicBlock
*
RISCVTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
const
TargetInstrInfo
&
TII
=
*
BB
->
getParent
(
)
->
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
=
MI
.
getDebugLoc
(
)
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unexpected instr type to insert"
)
;
case
RISCV
::
Select_GPR_Using_CC_GPR
:
case
RISCV
::
Select_FPR32_Using_CC_GPR
:
break
;
}
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
I
=
++
BB
->
getIterator
(
)
;
MachineBasicBlock
*
HeadMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
TailMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
IfFalseMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
F
->
insert
(
I
,
IfFalseMBB
)
;
F
->
insert
(
I
,
TailMBB
)
;
TailMBB
->
splice
(
TailMBB
->
begin
(
)
,
HeadMBB
,
std
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
HeadMBB
->
end
(
)
)
;
TailMBB
->
transferSuccessorsAndUpdatePHIs
(
HeadMBB
)
;
HeadMBB
->
addSuccessor
(
IfFalseMBB
)
;
HeadMBB
->
addSuccessor
(
TailMBB
)
;
unsigned
LHS
=
MI
.
getOperand
(
1
)
.
getReg
(
)
;
unsigned
RHS
=
MI
.
getOperand
(
2
)
.
getReg
(
)
;
auto
CC
=
static_cast
<
ISD
::
CondCode
>
(
MI
.
getOperand
(
3
)
.
getImm
(
)
)
;
unsigned
Opcode
=
getBranchOpcodeForIntCondCode
(
CC
)
;
BuildMI
(
HeadMBB
,
DL
,
TII
.
get
(
Opcode
)
)
.
addReg
(
LHS
)
.
addReg
(
RHS
)
.
addMBB
(
TailMBB
)
;
IfFalseMBB
->
addSuccessor
(
TailMBB
)
;
BuildMI
(
*
TailMBB
,
TailMBB
->
begin
(
)
,
DL
,
TII
.
get
(
RISCV
::
PHI
)
,
MI
.
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
.
getOperand
(
4
)
.
getReg
(
)
)
.
addMBB
(
HeadMBB
)
.
addReg
(
MI
.
getOperand
(
5
)
.
getReg
(
)
)
.
addMBB
(
IfFalseMBB
)
;
MI
.
eraseFromParent
(
)
;
return
TailMBB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> void insert ( unsigned BBNum , BasicBlockInfo BBI ) { BBInfo . insert ( BBInfo . begin ( ) + BBNum , BBI ) ; } </s>

insert - Append entry to the vector if it does n't already exist .


<s> rtx ix86_expand_adjust_ufix_to_sfix_si ( rtx val , rtx * xorp ) { REAL_VALUE_TYPE TWO31r ; rtx two31r , tmp [ 4 ] ; machine_mode mode = GET_MODE ( val ) ; machine_mode scalarmode = GET_MODE_INNER ( mode ) ; machine_mode intmode = GET_MODE_SIZE ( mode ) == 32 ? V8SImode : V4SImode ; rtx ( * cmp ) ( rtx , rtx , rtx , rtx ) ; int i ; for ( i = 0 ; i < 3 ; i ++ ) tmp [ i ] = gen_reg_rtx ( mode ) ; real_ldexp ( & TWO31r , & dconst1 , 31 ) ; two31r = const_double_from_real_value ( TWO31r , scalarmode ) ; two31r = ix86_build_const_vector ( mode , 1 , two31r ) ; two31r = force_reg ( mode , two31r ) ; switch ( mode ) { case V8SFmode : cmp = gen_avx_maskcmpv8sf3 ; break ; case V4SFmode : cmp = gen_sse_maskcmpv4sf3 ; break ; case V4DFmode : cmp = gen_avx_maskcmpv4df3 ; break ; case V2DFmode : cmp = gen_sse2_maskcmpv2df3 ; break ; default : gcc_unreachable ( ) ; } tmp [ 3 ] = gen_rtx_LE ( mode , two31r , val ) ; emit_insn ( cmp ( tmp [ 0 ] , two31r , val , tmp [ 3 ] ) ) ; tmp [ 1 ] = expand_simple_binop ( mode , AND , tmp [ 0 ] , two31r , tmp [ 1 ] , 0 , OPTAB_DIRECT ) ; if ( intmode == V4SImode || TARGET_AVX2 ) * xorp = expand_simple_binop ( intmode , ASHIFT , gen_lowpart ( intmode , tmp [ 0 ] ) , GEN_INT ( 31 ) , NULL_RTX , 0 , OPTAB_DIRECT ) ; else { rtx two31 = GEN_INT ( HOST_WIDE_INT_1U << 31 ) ; two31 = ix86_build_const_vector ( intmode , 1 , two31 ) ; * xorp = expand_simple_binop ( intmode , AND , gen_lowpart ( intmode , tmp [ 0 ] ) , two31 , NULL_RTX , 0 , OPTAB_DIRECT ) ; } return expand_simple_binop ( mode , MINUS , val , tmp [ 1 ] , tmp [ 2 ] , 0 , OPTAB_DIRECT ) ; } </s>

Adjust a V * SFmode/V * DFmode value VAL so that * sfix_trunc * resp . fix_trunc * pattern can be used on it instead of fixuns_trunc * . This is done by doing just signed conversion if < 0x1p31 , and otherwise by subtracting 0x1p31 first and xoring in 0x80000000 from * XORP afterwards .


<s> static void compute_regstack_size ( ) { int i ; rtx insn ; a29k_makes_calls = 0 ; for ( insn = get_insns ( ) ; insn ; insn = next_insn ( insn ) ) if ( GET_CODE ( insn ) == CALL_INSN || ( GET_CODE ( insn ) == INSN && GET_CODE ( PATTERN ( insn ) ) == SEQUENCE && GET_CODE ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) ) == CALL_INSN ) ) { a29k_makes_calls = 1 ; break ; } for ( i = R_LR ( 127 ) ; i >= R_LR ( 0 ) ; i -- ) if ( regs_ever_live [ i ] ) break ; a29k_regstack_size = i - ( R_LR ( 0 ) - 1 ) ; if ( a29k_makes_calls && a29k_regstack_size < 2 ) a29k_regstack_size = 2 ; a29k_regstack_size += frame_pointer_needed ; if ( a29k_regstack_size & 1 ) a29k_regstack_size ++ ; } </s>

Compute the size of the register stack , and determine if there are any call instructions .


<s> void GCNPassConfig :: addOptimizedRegAlloc ( FunctionPass * RegAllocPass ) { insertPass ( & MachineSchedulerID , & SIOptimizeExecMaskingPreRAID ) ; insertPass ( & SIOptimizeExecMaskingPreRAID , & SIFormMemoryClausesID ) ; insertPass ( & PHIEliminationID , & SILowerControlFlowID , false ) ; insertPass ( & SILowerControlFlowID , & SIFixWWMLivenessID , false ) ; TargetPassConfig :: addOptimizedRegAlloc ( RegAllocPass ) ; } </s>

addOptimizedRegAlloc - Add passes related to register allocation .


<s> bool RISCVCallLowering :: lowerCall ( MachineIRBuilder & MIRBuilder , CallLoweringInfo & Info ) const { return false ; } </s>

This hook must be implemented to lower the given call instruction , including argument and return value marshalling .


<s> bool isReg ( ) const override { return false ; } </s>


<s> int get_dest_uid ( rtx label , int max_uid ) { rtx_insn * dest = next_real_insn ( label ) ; int dest_uid ; if ( ! dest ) return 0 ; dest_uid = INSN_UID ( dest ) ; while ( dest_uid >= max_uid ) { dest = NEXT_INSN ( dest ) ; dest_uid = INSN_UID ( dest ) ; } if ( JUMP_P ( dest ) && GET_CODE ( PATTERN ( dest ) ) == RETURN ) return 0 ; return dest_uid ; } </s>

Return the UID of the insn that follows the specified label .


<s> bool TPCInstrInfo :: isReallyTriviallyReMaterializable ( const MachineInstr & MI , AAResults * AA ) const { unsigned NumOperands = MI . getDesc ( ) . getNumOperands ( ) ; if ( NumOperands < 3 ) return false ; const MachineOperand & PredMO = MI . getOperand ( NumOperands - 2 ) ; if ( ! PredMO . isReg ( ) ) return false ; return PredMO . getReg ( ) == TPC :: SP0 ; } </s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> virtual const TargetRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static void sparc_asm_function_prologue ( FILE * file ) { if ( ! TARGET_FLAT ) gcc_assert ( sparc_leaf_function_p == crtl -> uses_only_leaf_regs ) ; sparc_output_scratch_registers ( file ) ; } </s>

This function generates the assembly code for function entry , which boils down to emitting the necessary .register directives .


<s>
unsigned
HexagonAsmParser
::
validateTargetOperandClass
(
MCParsedAsmOperand
&
AsmOp
,
unsigned
Kind
)
{
HexagonOperand
*
Op
=
static_cast
<
HexagonOperand
*
>
(
&
AsmOp
)
;
switch
(
Kind
)
{
case
MCK_0
:
{
int64_t
Value
;
return
Op
->
isImm
(
)
&&
Op
->
Imm
.
Val
->
evaluateAsAbsolute
(
Value
)
&&
Value
==
0
Match_Success
:
Match_InvalidOperand
;
}
case
MCK_1
:
{
int64_t
Value
;
return
Op
->
isImm
(
)
&&
Op
->
Imm
.
Val
->
evaluateAsAbsolute
(
Value
)
&&
Value
==
1
Match_Success
:
Match_InvalidOperand
;
}
case
MCK__MINUS_1
:
{
int64_t
Value
;
return
Op
->
isImm
(
)
&&
Op
->
Imm
.
Val
->
evaluateAsAbsolute
(
Value
)
&&
Value
==
1
Match_Success
:
Match_InvalidOperand
;
}
}
if
(
Op
->
Kind
==
HexagonOperand
::
Token
&&
Kind
!=
InvalidMatchClass
)
{
StringRef
myStringRef
=
StringRef
(
Op
->
Tok
.
Data
,
Op
->
Tok
.
Length
)
;
if
(
matchTokenString
(
myStringRef
.
lower
(
)
)
==
(
MatchClassKind
)
Kind
)
return
Match_Success
;
if
(
matchTokenString
(
myStringRef
.
upper
(
)
)
==
(
MatchClassKind
)
Kind
)
return
Match_Success
;
}
DEBUG
(
dbgs
(
)
<<
"Unmatched Operand:"
)
;
DEBUG
(
Op
->
dump
(
)
)
;
DEBUG
(
dbgs
(
)
<<
"\n"
)
;
return
Match_InvalidOperand
;
}
</s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .

Hexagon
Hexagon
Hexagon
Hexagon
0
1
1
Hexagon
"Unmatched Operand:"
"\n"


<s> static inline bool offset_12bit_unsigned_scaled_p ( machine_mode mode , HOST_WIDE_INT offset ) { return ( offset >= 0 && offset < 4096 * GET_MODE_SIZE ( mode ) && offset % GET_MODE_SIZE ( mode ) == 0 ) ; } </s>

Return true if OFFSET is an unsigned 12-bit value multiplied by the size of MODE .


<s> const TargetRegisterClass * X86RegisterInfo :: getCrossCopyRegClass ( const TargetRegisterClass * RC ) const { if ( RC == & X86 :: CCRRegClass ) { if ( Is64Bit ) return & X86 :: GR64RegClass ; else return & X86 :: GR32RegClass ; } return NULL ; } </s>

getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or from .


<s>
static
void
dump_target_flag_bits
(
const
int
flags
)
{
if
(
flags
&
MASK_64BIT
)
fprintf
(
stderr
,
"64BIT "
)
;
if
(
flags
&
MASK_APP_REGS
)
fprintf
(
stderr
,
"APP_REGS "
)
;
if
(
flags
&
MASK_FASTER_STRUCTS
)
fprintf
(
stderr
,
"FASTER_STRUCTS "
)
;
if
(
flags
&
MASK_FLAT
)
fprintf
(
stderr
,
"FLAT "
)
;
if
(
flags
&
MASK_FMAF
)
fprintf
(
stderr
,
"FMAF "
)
;
if
(
flags
&
MASK_FSMULD
)
fprintf
(
stderr
,
"FSMULD "
)
;
if
(
flags
&
MASK_FPU
)
fprintf
(
stderr
,
"FPU "
)
;
if
(
flags
&
MASK_HARD_QUAD
)
fprintf
(
stderr
,
"HARD_QUAD "
)
;
if
(
flags
&
MASK_POPC
)
fprintf
(
stderr
,
"POPC "
)
;
if
(
flags
&
MASK_PTR64
)
fprintf
(
stderr
,
"PTR64 "
)
;
if
(
flags
&
MASK_STACK_BIAS
)
fprintf
(
stderr
,
"STACK_BIAS "
)
;
if
(
flags
&
MASK_UNALIGNED_DOUBLES
)
fprintf
(
stderr
,
"UNALIGNED_DOUBLES "
)
;
if
(
flags
&
MASK_V8PLUS
)
fprintf
(
stderr
,
"V8PLUS "
)
;
if
(
flags
&
MASK_VIS
)
fprintf
(
stderr
,
"VIS "
)
;
if
(
flags
&
MASK_VIS2
)
fprintf
(
stderr
,
"VIS2 "
)
;
if
(
flags
&
MASK_VIS3
)
fprintf
(
stderr
,
"VIS3 "
)
;
if
(
flags
&
MASK_VIS4
)
fprintf
(
stderr
,
"VIS4 "
)
;
if
(
flags
&
MASK_VIS4B
)
fprintf
(
stderr
,
"VIS4B "
)
;
if
(
flags
&
MASK_CBCOND
)
fprintf
(
stderr
,
"CBCOND "
)
;
if
(
flags
&
MASK_DEPRECATED_V8_INSNS
)
fprintf
(
stderr
,
"DEPRECATED_V8_INSNS "
)
;
if
(
flags
&
MASK_LEON
)
fprintf
(
stderr
,
"LEON "
)
;
if
(
flags
&
MASK_LEON3
)
fprintf
(
stderr
,
"LEON3 "
)
;
if
(
flags
&
MASK_SPARCLET
)
fprintf
(
stderr
,
"SPARCLET "
)
;
if
(
flags
&
MASK_SPARCLITE
)
fprintf
(
stderr
,
"SPARCLITE "
)
;
if
(
flags
&
MASK_V8
)
fprintf
(
stderr
,
"V8 "
)
;
if
(
flags
&
MASK_V9
)
fprintf
(
stderr
,
"V9 "
)
;
}
</s>

sparc
"64BIT "
"APP_REGS "
"FASTER_STRUCTS "
"FLAT "
"FMAF "
"FSMULD "
"FPU "
"HARD_QUAD "
"POPC "
"PTR64 "
"STACK_BIAS "
"UNALIGNED_DOUBLES "
"V8PLUS "
"VIS "
"VIS2 "
"VIS3 "
"VIS4 "
"VIS4B "
"CBCOND "
"DEPRECATED_V8_INSNS "
"LEON "
"LEON3 "
"SPARCLET "
"SPARCLITE "
"V8 "
"V9 "


<s> static bool nios2_valid_addr_expr_p ( rtx base , rtx offset , bool strict_p ) { if ( ! strict_p && GET_CODE ( base ) == SUBREG ) base = SUBREG_REG ( base ) ; return ( REG_P ( base ) && nios2_regno_ok_for_base_p ( REGNO ( base ) , strict_p ) && ( offset == NULL_RTX || nios2_valid_addr_offset_p ( offset ) || ( nios2_large_constant_allowed ( ) && nios2_symbolic_constant_p ( offset ) ) || nios2_unspec_reloc_p ( offset ) ) ) ; } </s>

Return true if the address expression formed by BASE + OFFSET is valid .


<s> static int visium_adjust_cost ( rtx_insn * insn , int dep_type , rtx_insn * dep_insn , int cost , unsigned int ) { enum attr_type attr_type ; if ( dep_type == REG_DEP_TRUE ) { if ( ! reload_completed && recog_memoized ( insn ) >= 0 && get_attr_type ( insn ) == TYPE_CMP ) { rtx pat = PATTERN ( insn ) ; gcc_assert ( GET_CODE ( pat ) == SET ) ; rtx src = SET_SRC ( pat ) ; if ( GET_CODE ( src ) == IF_THEN_ELSE && XEXP ( XEXP ( src , 0 ) , 1 ) == const0_rtx && recog_memoized ( dep_insn ) >= 0 ) { enum attr_type dep_attr_type = get_attr_type ( dep_insn ) ; if ( dep_attr_type == TYPE_LOGIC || ( dep_attr_type == TYPE_ARITH && visium_nz_comparison_operator ( XEXP ( src , 0 ) , GET_MODE ( XEXP ( src , 0 ) ) ) ) ) return 0 ; } } return cost ; } if ( recog_memoized ( insn ) < 0 ) return 0 ; attr_type = get_attr_type ( insn ) ; if ( dep_type == REG_DEP_ANTI ) { if ( attr_type == TYPE_REG_FP && visium_cpu == PROCESSOR_GR5 ) { rtx pat = PATTERN ( insn ) ; rtx dep_pat = PATTERN ( dep_insn ) ; if ( GET_CODE ( pat ) != SET || GET_CODE ( dep_pat ) != SET ) return 0 ; if ( reg_mentioned_p ( SET_DEST ( pat ) , SET_SRC ( dep_pat ) ) ) { if ( recog_memoized ( dep_insn ) < 0 ) return 0 ; switch ( get_attr_type ( dep_insn ) ) { case TYPE_FDIV : case TYPE_FSQRT : case TYPE_FTOI : case TYPE_ITOF : case TYPE_FP : case TYPE_FMOVE : return insn_default_latency ( dep_insn ) ; default : return 0 ; } } } else if ( attr_type == TYPE_RET && visium_cpu == PROCESSOR_GR6 ) { rtx dep_pat = PATTERN ( dep_insn ) ; if ( GET_CODE ( dep_pat ) == SET && REG_P ( SET_DEST ( dep_pat ) ) && REGNO ( SET_DEST ( dep_pat ) ) == LINK_REGNUM ) return 8 ; } return 0 ; } else if ( dep_type == REG_DEP_OUTPUT ) { if ( attr_type == TYPE_REG_FP && visium_cpu == PROCESSOR_GR5 ) { rtx pat = PATTERN ( insn ) ; rtx dep_pat = PATTERN ( dep_insn ) ; if ( GET_CODE ( pat ) != SET || GET_CODE ( dep_pat ) != SET ) return 0 ; if ( reg_mentioned_p ( SET_DEST ( pat ) , SET_DEST ( dep_pat ) ) ) { if ( recog_memoized ( dep_insn ) < 0 ) return 0 ; switch ( get_attr_type ( dep_insn ) ) { case TYPE_FDIV : case TYPE_FSQRT : case TYPE_FTOI : case TYPE_ITOF : case TYPE_FP : case TYPE_FMOVE : return insn_default_latency ( dep_insn ) ; default : return 0 ; } } } return 0 ; } return 0 ; } </s>

Adjust the cost of a scheduling dependency . Return the new cost of a dependency LINK of INSN on DEP_INSN . COST is the current cost .


<s>
unsigned
OutgoingValueHandler
::
extendRegister
(
unsigned
ValReg
,
const
CCValAssign
&
VA
)
{
LLT
LocTy
{
VA
.
getLocVT
(
)
}
;
switch
(
VA
.
getLocInfo
(
)
)
{
case
CCValAssign
::
SExt
:
{
unsigned
ExtReg
=
MRI
.
createGenericVirtualRegister
(
LocTy
)
;
MIRBuilder
.
buildSExt
(
ExtReg
,
ValReg
)
;
return
ExtReg
;
}
case
CCValAssign
::
ZExt
:
{
unsigned
ExtReg
=
MRI
.
createGenericVirtualRegister
(
LocTy
)
;
MIRBuilder
.
buildZExt
(
ExtReg
,
ValReg
)
;
return
ExtReg
;
}
case
CCValAssign
::
AExt
:
{
unsigned
ExtReg
=
MRI
.
createGenericVirtualRegister
(
LocTy
)
;
MIRBuilder
.
buildAnyExt
(
ExtReg
,
ValReg
)
;
return
ExtReg
;
}
case
CCValAssign
::
Full
:
return
ValReg
;
default
:
break
;
}
llvm_unreachable
(
"unable to extend register"
)
;
}
</s>

Extend a register to the location type given in VA , capped at extending to at most MaxSize bits .


<s>
unsigned
getReg
(
)
const
{
assert
(
isRegBase
(
)
&&
"Invalid base register access!"
)
;
return
Base
.
Reg
;
}
</s>

Returns the register associated with this edge .

WebAssembly
"Invalid base register access!"


<s> bool HexagonTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AS , unsigned Align , bool * Fast ) const { if ( Fast ) * Fast = false ; return Subtarget . isHVXVectorType ( VT . getSimpleVT ( ) ) ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s>
bool
AArch64InstrInfo
::
isFPRCopy
(
const
MachineInstr
&
MI
)
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
TargetOpcode
::
COPY
:
{
Register
DstReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
return
(
AArch64
::
FPR64RegClass
.
contains
(
DstReg
)
||
AArch64
::
FPR128RegClass
.
contains
(
DstReg
)
)
;
}
case
AArch64
::
ORRv16i8
:
if
(
MI
.
getOperand
(
1
)
.
getReg
(
)
==
MI
.
getOperand
(
2
)
.
getReg
(
)
)
{
assert
(
MI
.
getDesc
(
)
.
getNumOperands
(
)
==
3
&&
MI
.
getOperand
(
0
)
.
isReg
(
)
&&
"invalid ORRv16i8 operands"
)
;
return
true
;
}
break
;
}
return
false
;
}
</s>

Does this instruction rename an FPR without modifying bits ?


<s> void nds32_spilt_doubleword ( rtx * operands , bool load_p ) { int reg = load_p ? 0 : 1 ; int mem = load_p ? 1 : 0 ; rtx reg_rtx = load_p ? operands [ 0 ] : operands [ 1 ] ; rtx mem_rtx = load_p ? operands [ 1 ] : operands [ 0 ] ; rtx low_part [ 2 ] , high_part [ 2 ] ; rtx sub_mem = XEXP ( mem_rtx , 0 ) ; low_part [ reg ] = simplify_gen_subreg ( SImode , reg_rtx , GET_MODE ( reg_rtx ) , 0 ) ; high_part [ reg ] = simplify_gen_subreg ( SImode , reg_rtx , GET_MODE ( reg_rtx ) , 4 ) ; if ( GET_CODE ( sub_mem ) == POST_DEC ) { sub_mem = XEXP ( sub_mem , 0 ) ; low_part [ mem ] = gen_frame_mem ( SImode , gen_rtx_POST_MODIFY ( Pmode , sub_mem , gen_rtx_PLUS ( Pmode , sub_mem , GEN_INT ( 4 ) ) ) ) ; high_part [ mem ] = gen_frame_mem ( SImode , gen_rtx_POST_MODIFY ( Pmode , sub_mem , gen_rtx_PLUS ( Pmode , sub_mem , GEN_INT ( - 12 ) ) ) ) ; } else if ( GET_CODE ( sub_mem ) == POST_MODIFY ) { rtx post_mem = XEXP ( sub_mem , 0 ) ; rtx plus_op = XEXP ( sub_mem , 1 ) ; rtx post_val = XEXP ( plus_op , 1 ) ; low_part [ mem ] = gen_frame_mem ( SImode , gen_rtx_POST_MODIFY ( Pmode , post_mem , gen_rtx_PLUS ( Pmode , post_mem , post_val ) ) ) ; high_part [ mem ] = gen_frame_mem ( SImode , plus_constant ( Pmode , post_mem , 4 ) ) ; } else { low_part [ mem ] = adjust_address ( mem_rtx , SImode , 0 ) ; high_part [ mem ] = adjust_address ( mem_rtx , SImode , 4 ) ; } if ( ( load_p && reg_overlap_mentioned_p ( low_part [ 0 ] , high_part [ 1 ] ) ) || GET_CODE ( sub_mem ) == POST_MODIFY ) { operands [ 2 ] = high_part [ 0 ] ; operands [ 3 ] = high_part [ 1 ] ; operands [ 4 ] = low_part [ 0 ] ; operands [ 5 ] = low_part [ 1 ] ; } else { operands [ 2 ] = low_part [ 0 ] ; operands [ 3 ] = low_part [ 1 ] ; operands [ 4 ] = high_part [ 0 ] ; operands [ 5 ] = high_part [ 1 ] ; } } </s>

Spilt a doubleword instrucion to two single word instructions .


<s> void aarch64_expand_sve_vec_cmp_int ( rtx target , rtx_code code , rtx op0 , rtx op1 ) { machine_mode pred_mode = GET_MODE ( target ) ; machine_mode data_mode = GET_MODE ( op0 ) ; if ( ! aarch64_sve_cmp_operand_p ( code , op1 ) ) op1 = force_reg ( data_mode , op1 ) ; rtx ptrue = force_reg ( pred_mode , CONSTM1_RTX ( pred_mode ) ) ; rtx cond = gen_rtx_fmt_ee ( code , pred_mode , op0 , op1 ) ; aarch64_emit_sve_ptrue_op_cc ( target , ptrue , cond ) ; } </s>

Expand an SVE integer comparison : TARGET = CODE ( OP0 , OP1 ) .


Output at end of assembler file . On the RS/6000 , referencing data should automatically pull in text .


<s>
void
RegisterAggr
::
print
(
raw_ostream
&
OS
)
const
{
OS
<<
'{'
;
for
(
auto
I
:
Masks
)
OS
<<
' '
<<
PrintReg
(
I
.
first
,
&
TRI
)
<<
PrintLaneMaskOpt
(
I
.
second
)
;
OS
<<
" }"
;
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> static void count_unit_reqs ( unit_req_table reqs , rtx_insn * head , rtx_insn * tail ) { rtx_insn * insn ; memset ( reqs , 0 , sizeof ( unit_req_table ) ) ; for ( insn = head ; insn != NEXT_INSN ( tail ) ; insn = NEXT_INSN ( insn ) ) { int side1 , side2 , req1 , req2 ; switch ( get_unit_reqs ( insn , & req1 , & side1 , & req2 , & side2 ) ) { case 2 : reqs [ side2 ] [ req2 ] ++ ; case 1 : reqs [ side1 ] [ req1 ] ++ ; break ; } } } </s>

Walk the insns between and including HEAD and TAIL , and mark the resource requirements in the unit_reqs table .


<s> bool AMDGPUSymbolizer :: tryAddingSymbolicOperand ( MCInst & Inst , raw_ostream & , int64_t Value , uint64_t , bool IsBranch , uint64_t , uint64_t ) { using SymbolInfoTy = std :: tuple < uint64_t , StringRef , uint8_t > ; using SectionSymbolsTy = std :: vector < SymbolInfoTy > ; if ( ! IsBranch ) { return false ; } auto * Symbols = static_cast < SectionSymbolsTy * > ( DisInfo ) ; if ( ! Symbols ) return false ; auto Result = std :: find_if ( Symbols -> begin ( ) , Symbols -> end ( ) , [ Value ] ( const SymbolInfoTy & Val ) { return std :: get < 0 > ( Val ) == static_cast < uint64_t > ( Value ) && std :: get < 2 > ( Val ) == ELF :: STT_NOTYPE ; } ) ; if ( Result != Symbols -> end ( ) ) { auto * Sym = Ctx . getOrCreateSymbol ( std :: get < 1 > ( * Result ) ) ; const auto * Add = MCSymbolRefExpr :: create ( Sym , Ctx ) ; Inst . addOperand ( MCOperand :: createExpr ( Add ) ) ; return true ; } return false ; } </s>

Try to add a symbolic operand instead of Value to the MCInst .


<s> static void s390_register_info_gprtofpr ( ) { int save_reg_slot = FPR0_REGNUM ; int i , j ; if ( ! TARGET_Z10 || ! TARGET_HARD_FLOAT || ! crtl -> is_leaf ) return ; for ( i = 15 ; i >= 6 ; i -- ) { if ( cfun_gpr_save_slot ( i ) == 0 ) continue ; while ( ( ! call_really_used_regs [ save_reg_slot ] || df_regs_ever_live_p ( save_reg_slot ) || cfun_fpr_save_p ( save_reg_slot ) ) && FP_REGNO_P ( save_reg_slot ) ) save_reg_slot ++ ; if ( ! FP_REGNO_P ( save_reg_slot ) ) { for ( j = 6 ; j <= 15 ; j ++ ) if ( FP_REGNO_P ( cfun_gpr_save_slot ( j ) ) ) cfun_gpr_save_slot ( j ) = - 1 ; break ; } cfun_gpr_save_slot ( i ) = save_reg_slot ++ ; } } </s>

Update gpr_save_slots in the frame layout trying to make use of FPRs as GPR save slots . This is a helper routine of s390_register_info .


<s>
SUnit
*
ConvergingVLIWScheduler
::
pickNodeBidrectional
(
bool
&
IsTopNode
)
{
if
(
SUnit
*
SU
=
Bot
.
pickOnlyChoice
(
)
)
{
IsTopNode
=
false
;
return
SU
;
}
if
(
SUnit
*
SU
=
Top
.
pickOnlyChoice
(
)
)
{
IsTopNode
=
true
;
return
SU
;
}
SchedCandidate
BotCand
;
CandResult
BotResult
=
pickNodeFromQueue
(
Bot
.
Available
,
DAG
->
getBotRPTracker
(
)
,
BotCand
)
;
assert
(
BotResult
!=
NoCand
&&
"failed to find the first candidate"
)
;
if
(
BotResult
==
SingleExcess
||
BotResult
==
SingleCritical
)
{
IsTopNode
=
false
;
return
BotCand
.
SU
;
}
SchedCandidate
TopCand
;
CandResult
TopResult
=
pickNodeFromQueue
(
Top
.
Available
,
DAG
->
getTopRPTracker
(
)
,
TopCand
)
;
assert
(
TopResult
!=
NoCand
&&
"failed to find the first candidate"
)
;
if
(
TopResult
==
SingleExcess
||
TopResult
==
SingleCritical
)
{
IsTopNode
=
true
;
return
TopCand
.
SU
;
}
if
(
BotResult
==
SingleMax
)
{
IsTopNode
=
false
;
return
BotCand
.
SU
;
}
if
(
TopResult
==
SingleMax
)
{
IsTopNode
=
true
;
return
TopCand
.
SU
;
}
if
(
TopCand
.
SCost
>
BotCand
.
SCost
)
{
IsTopNode
=
true
;
return
TopCand
.
SU
;
}
IsTopNode
=
false
;
return
BotCand
.
SU
;
}
</s>

Pick the best candidate node from either the top or bottom queue .

Hexagon
"failed to find the first candidate"
"failed to find the first candidate"


<s> bool isCtlzFast ( ) const override { return true ; } </s>

Return true if ctlz instruction is fast .


runOnMachineFunction - Emit the function body .


<s> ScheduleHazardRecognizer :: HazardType GCNHazardRecognizer :: getHazardType ( SUnit * SU , int Stalls ) { MachineInstr * MI = SU -> getInstr ( ) ; if ( SIInstrInfo :: isSMRD ( * MI ) && checkSMRDHazards ( MI ) > 0 ) return NoopHazard ; if ( SIInstrInfo :: isVMEM ( * MI ) && checkVMEMHazards ( MI ) > 0 ) return NoopHazard ; if ( SIInstrInfo :: isDPP ( * MI ) && checkDPPHazards ( MI ) > 0 ) return NoopHazard ; return NoHazard ; } </s>

getHazardType - Return the hazard type of emitting this node .


<s>
Value
*
AArch64TargetLowering
::
emitStoreConditional
(
IRBuilderBase
&
Builder
,
Value
*
Val
,
Value
*
Addr
,
AtomicOrdering
Ord
)
const
{
Module
*
M
=
Builder
.
GetInsertBlock
(
)
->
getParent
(
)
->
getParent
(
)
;
bool
IsRelease
=
isReleaseOrStronger
(
Ord
)
;
if
(
Val
->
getType
(
)
->
getPrimitiveSizeInBits
(
)
==
128
)
{
Intrinsic
::
ID
Int
=
IsRelease
Intrinsic
::
aarch64_stlxp
:
Intrinsic
::
aarch64_stxp
;
Function
*
Stxr
=
Intrinsic
::
getDeclaration
(
M
,
Int
)
;
Type
*
Int64Ty
=
Type
::
getInt64Ty
(
M
->
getContext
(
)
)
;
Value
*
Lo
=
Builder
.
CreateTrunc
(
Val
,
Int64Ty
,
"lo"
)
;
Value
*
Hi
=
Builder
.
CreateTrunc
(
Builder
.
CreateLShr
(
Val
,
64
)
,
Int64Ty
,
"hi"
)
;
Addr
=
Builder
.
CreateBitCast
(
Addr
,
Type
::
getInt8PtrTy
(
M
->
getContext
(
)
)
)
;
return
Builder
.
CreateCall
(
Stxr
,
{
Lo
,
Hi
,
Addr
}
)
;
}
Intrinsic
::
ID
Int
=
IsRelease
Intrinsic
::
aarch64_stlxr
:
Intrinsic
::
aarch64_stxr
;
const
DataLayout
&
DL
=
M
->
getDataLayout
(
)
;
IntegerType
*
IntValTy
=
Builder
.
getIntNTy
(
DL
.
getTypeSizeInBits
(
Val
->
getType
(
)
)
)
;
if
(
Val
->
getType
(
)
->
isPointerTy
(
)
)
Addr
=
Builder
.
CreatePointerCast
(
Addr
,
IntValTy
->
getPointerTo
(
Addr
->
getType
(
)
->
getPointerAddressSpace
(
)
)
)
;
Type
*
Tys
[
]
=
{
Addr
->
getType
(
)
}
;
Function
*
Stxr
=
Intrinsic
::
getDeclaration
(
M
,
Int
,
Tys
)
;
assert
(
!
DL
.
isFatPointer
(
Val
->
getType
(
)
)
&&
"Should not be handled here!"
)
;
if
(
Val
->
getType
(
)
->
isPointerTy
(
)
)
Val
=
Builder
.
CreatePtrToInt
(
Val
,
IntValTy
)
;
else
Val
=
Builder
.
CreateBitCast
(
Val
,
IntValTy
)
;
return
Builder
.
CreateCall
(
Stxr
,
{
Builder
.
CreateZExtOrBitCast
(
Val
,
Stxr
->
getFunctionType
(
)
->
getParamType
(
0
)
)
,
Addr
}
)
;
}
</s>

Perform a store-conditional operation to Addr .


<s> void SystemZTTIImpl :: getUnrollingPreferences ( Loop * L , TTI :: UnrollingPreferences & UP ) { bool HasCall = false ; unsigned NumStores = 0 ; for ( auto & BB : L -> blocks ( ) ) for ( auto & I : * BB ) { if ( isa < CallInst > ( & I ) || isa < InvokeInst > ( & I ) ) { ImmutableCallSite CS ( & I ) ; if ( const Function * F = CS . getCalledFunction ( ) ) { if ( isLoweredToCall ( F ) ) HasCall = true ; if ( F -> getIntrinsicID ( ) == Intrinsic :: memcpy || F -> getIntrinsicID ( ) == Intrinsic :: memset ) NumStores ++ ; } else { HasCall = true ; } } if ( isa < StoreInst > ( & I ) ) { NumStores ++ ; Type * MemAccessTy = I . getOperand ( 0 ) -> getType ( ) ; if ( ( MemAccessTy -> isIntegerTy ( ) || MemAccessTy -> isFloatingPointTy ( ) ) && ( getDataLayout ( ) . getTypeSizeInBits ( MemAccessTy ) == 128 ) ) NumStores ++ ; } } unsigned const Max = ( NumStores ? ( 12 / NumStores ) : UINT_MAX ) ; if ( HasCall ) { UP . FullUnrollMaxCount = Max ; UP . MaxCount = 1 ; return ; } UP . MaxCount = Max ; if ( UP . MaxCount <= 1 ) return ; UP . Partial = UP . Runtime = true ; UP . PartialThreshold = 75 ; UP . DefaultUnrollRuntimeCount = 4 ; UP . AllowExpensiveTripCount = true ; UP . Force = true ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> bool tilepro_bitfield_operand_p ( HOST_WIDE_INT n , int * first_bit , int * last_bit ) { int i ; if ( n == 0 ) return false ; for ( i = 0 ; i < 32 ; i ++ ) { unsigned HOST_WIDE_INT x = rotate_right ( n , i ) ; if ( ! ( x & 1 ) ) continue ; if ( ( x & ( x + 1 ) ) == 0 ) { if ( first_bit != NULL ) * first_bit = i ; if ( last_bit != NULL ) * last_bit = ( i + exact_log2 ( x ^ ( x >> 1 ) ) ) & 31 ; return true ; } } return false ; } </s>

Return true iff n contains exactly one contiguous sequence of 1 bits , possibly wrapping around from high bits to low bits .


<s> void emitCommonSymbol ( MCSymbol * Symbol , uint64_t Size , unsigned ByteAlignment ) override { } </s>


<s> Optional < ParamLoadedValue > AArch64InstrInfo :: describeLoadedValue ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { case AArch64 :: MOVZWi : case AArch64 :: MOVZXi : if ( ! MI . getOperand ( 1 ) . isImm ( ) ) return None ; int Immediate = MI . getOperand ( 1 ) . getImm ( ) ; int Shift = MI . getOperand ( 2 ) . getImm ( ) ; return ParamLoadedValue ( MachineOperand :: CreateImm ( Immediate << Shift ) , nullptr ) ; } return TargetInstrInfo :: describeLoadedValue ( MI ) ; } </s>

Produce the expression describing the MI loading a value into the physical register Reg .


<s> bool MipsAsmPrinter :: lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) { MCOp = MCInstLowering . LowerOperand ( MO ) ; return MCOp . isValid ( ) ; } </s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> SDValue X86TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: EXTRACT_VECTOR_ELT : return PerformEXTRACT_VECTOR_ELTCombine ( N , DAG , * this ) ; case ISD :: VSELECT : case ISD :: SELECT : return PerformSELECTCombine ( N , DAG , DCI , Subtarget ) ; case X86ISD :: CMOV : return PerformCMOVCombine ( N , DAG , DCI ) ; case ISD :: ADD : return PerformAddCombine ( N , DAG , Subtarget ) ; case ISD :: SUB : return PerformSubCombine ( N , DAG , Subtarget ) ; case X86ISD :: ADC : return PerformADCCombine ( N , DAG , DCI ) ; case ISD :: MUL : return PerformMulCombine ( N , DAG , DCI ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: AND : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: OR : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: XOR : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: LOAD : return PerformLOADCombine ( N , DAG , Subtarget ) ; case ISD :: STORE : return PerformSTORECombine ( N , DAG , Subtarget ) ; case ISD :: SINT_TO_FP : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case ISD :: FADD : return PerformFADDCombine ( N , DAG , Subtarget ) ; case ISD :: FSUB : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case X86ISD :: FXOR : case X86ISD :: FOR : return PerformFORCombine ( N , DAG ) ; case X86ISD :: FAND : return PerformFANDCombine ( N , DAG ) ; case X86ISD :: BT : return PerformBTCombine ( N , DAG , DCI ) ; case X86ISD :: VZEXT_MOVL : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case ISD :: ZERO_EXTEND : return PerformZExtCombine ( N , DAG , Subtarget ) ; case ISD :: SIGN_EXTEND : return PerformSExtCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: TRUNCATE : return PerformTruncateCombine ( N , DAG , DCI ) ; case X86ISD :: SETCC : return PerformSETCCCombine ( N , DAG ) ; case X86ISD :: SHUFP : case X86ISD :: PALIGN : case X86ISD :: UNPCKH : case X86ISD :: UNPCKL : case X86ISD :: MOVHLPS : case X86ISD :: MOVLHPS : case X86ISD :: PSHUFD : case X86ISD :: PSHUFHW : case X86ISD :: PSHUFLW : case X86ISD :: MOVSS : case X86ISD :: MOVSD : case X86ISD :: VPERMILP : case X86ISD :: VPERM2X128 : case ISD :: VECTOR_SHUFFLE : return PerformShuffleCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> bool isImm ( ) const override { return Kind == k_Immediate ; } </s>


<s> int ARMTTIImpl :: getFPOpCost ( Type * Ty ) { if ( ST -> hasVFP2 ( ) && ! ST -> isThumb1Only ( ) ) { if ( Ty -> isFloatTy ( ) ) { return TargetTransformInfo :: TCC_Basic ; } if ( Ty -> isDoubleTy ( ) ) { return ST -> isFPOnlySP ( ) ? TargetTransformInfo :: TCC_Expensive : TargetTransformInfo :: TCC_Basic ; } } return TargetTransformInfo :: TCC_Expensive ; } </s>

Return the expected cost of supporting the floating point operation of the specified type .


<s> bool isReg ( ) const override { return Kind == k_Register && ! Reg . isVector ; } </s>


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return createHexagonELFObjectWriter ( OS , OSABI , CPU ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> const ARMBaseRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
int
PPCTTIImpl
::
getArithmeticInstrCost
(
unsigned
Opcode
,
Type
*
Ty
,
TTI
::
TargetCostKind
CostKind
,
TTI
::
OperandValueKind
Op1Info
,
TTI
::
OperandValueKind
Op2Info
,
TTI
::
OperandValueProperties
Opd1PropInfo
,
TTI
::
OperandValueProperties
Opd2PropInfo
,
ArrayRef
<
const
Value
*
>
Args
,
const
Instruction
*
CxtI
)
{
assert
(
TLI
->
InstructionOpcodeToISD
(
Opcode
)
&&
"Invalid opcode"
)
;
if
(
CostKind
!=
TTI
::
TCK_RecipThroughput
)
return
BaseT
::
getArithmeticInstrCost
(
Opcode
,
Ty
,
CostKind
,
Op1Info
,
Op2Info
,
Opd1PropInfo
,
Opd2PropInfo
,
Args
,
CxtI
)
;
int
Cost
=
BaseT
::
getArithmeticInstrCost
(
Opcode
,
Ty
,
CostKind
,
Op1Info
,
Op2Info
,
Opd1PropInfo
,
Opd2PropInfo
)
;
return
vectorCostAdjustment
(
Cost
,
Opcode
,
Ty
,
nullptr
)
;
}
</s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> void i386_djgpp_asm_named_section ( const char * name , unsigned int flags , tree ) { char flagchars [ 8 ] , * f = flagchars ; if ( flags & SECTION_WRITE ) * f ++ = 'w' ; if ( flags & SECTION_CODE ) * f ++ = 'x' ; if ( strncmp ( name , LTO_SECTION_NAME_PREFIX , strlen ( LTO_SECTION_NAME_PREFIX ) ) == 0 ) * f ++ = '0' ; * f ++ = '\0' ; fprintf ( asm_out_file , "\t.section\t%s,\"%s\"\n" , name , flagchars ) ; } </s>


<s> void Thumb2InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { if ( ! ARM :: GPRRegClass . contains ( DestReg , SrcReg ) ) return ARMBaseInstrInfo :: copyPhysReg ( MBB , I , DL , DestReg , SrcReg , KillSrc ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: tMOVr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ) ; } </s>


<s>
SDValue
XNCMTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
SHL
:
case
ISD
::
SRL
:
case
ISD
::
SRA
:
return
LowerShifts
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ExternalSymbol
:
return
LowerExternalSymbol
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SIGN_EXTEND
:
return
LowerSIGN_EXTEND
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

XNCM
XNCM
ISD::SHL
ISD::SRL
ISD::SRA
ISD::GlobalAddress
ISD::BlockAddress
ISD::ExternalSymbol
ISD::BR_CC
ISD::SELECT_CC
ISD::SIGN_EXTEND
"unimplemented operand"


<s> bool LC3bFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


"***** AArch64SpeculationHardening - automatic insertion of "

"***** AArch64SpeculationHardening - track control flow *****\n"


<s> const MCFixup * RISCVMCExpr :: getPCRelHiFixup ( const MCFragment * * DFOut ) const { MCValue AUIPCLoc ; if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( AUIPCLoc , nullptr , nullptr ) ) return nullptr ; const MCSymbolRefExpr * AUIPCSRE = AUIPCLoc . getSymA ( ) ; if ( ! AUIPCSRE ) return nullptr ; const MCSymbol * AUIPCSymbol = & AUIPCSRE -> getSymbol ( ) ; const auto * DF = dyn_cast_or_null < MCDataFragment > ( AUIPCSymbol -> getFragment ( ) ) ; if ( ! DF ) return nullptr ; uint64_t Offset = AUIPCSymbol -> getOffset ( ) ; if ( DF -> getContents ( ) . size ( ) == Offset ) { DF = dyn_cast_or_null < MCDataFragment > ( DF -> getNextNode ( ) ) ; if ( ! DF ) return nullptr ; Offset = 0 ; } for ( const MCFixup & F : DF -> getFixups ( ) ) { if ( F . getOffset ( ) != Offset ) continue ; switch ( ( unsigned ) F . getKind ( ) ) { default : continue ; case RISCV :: fixup_riscv_got_hi20 : case RISCV :: fixup_riscv_tls_got_hi20 : case RISCV :: fixup_riscv_tls_gd_hi20 : case RISCV :: fixup_riscv_pcrel_hi20 : if ( DFOut ) * DFOut = DF ; return & F ; } } return nullptr ; } </s>

Get the corresponding PC-relative HI fixup that a VK_RISCV_PCREL_LO points to , and optionally the fragment containing it .


<s> bool enablePostRAScheduler ( ) const override { return isCortexA53 ( ) || isCortexA57 ( ) ; } </s>

True if the subtarget should run a scheduler after register allocation .


"Frame offsets outside of the signed 32-bit range not supported"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s>
void
WebAssemblyAsmPrinter
::
emitConstantPool
(
)
{
emitDecls
(
*
MMI
->
getModule
(
)
)
;
assert
(
MF
->
getConstantPool
(
)
->
getConstants
(
)
.
empty
(
)
&&
"WebAssembly disables constant pools"
)
;
}
</s>

Print to the current output stream assembly representations of the constants in the constant pool MCP .

WebAssembly
WebAssembly
"WebAssembly disables constant pools"


<s> PIC16SectionType getType ( ) const { return T ; } </s>

Overload to return most specific vector type .


<s> void AMDGPUMCObjectWriter :: writeObject ( MCAssembler & Asm , const MCAsmLayout & Layout ) { for ( MCAssembler :: iterator I = Asm . begin ( ) , E = Asm . end ( ) ; I != E ; ++ I ) { Asm . writeSectionData ( & * I , Layout ) ; } } </s>

Write the object file and returns the number of bytes written .


"********* Hexagon Hardware Loops *********\n"

runOnMachineFunction - Emit the function body .


<s> int crx_hard_regno_mode_ok ( int regno , enum machine_mode mode ) { if ( regno == CC_REGNUM ) return GET_MODE_CLASS ( mode ) == MODE_CC ; if ( GET_MODE_CLASS ( mode ) == MODE_CC ) return 0 ; if ( HILO_REGNO_P ( regno ) ) return mode == SImode || mode == DImode ; return 1 ; } </s>

Return 1 if hard register REGNO can hold a value of machine-mode MODE .


<s> static bool arm_array_mode_supported_p ( machine_mode mode , unsigned HOST_WIDE_INT nelems ) { if ( TARGET_NEON && ! BYTES_BIG_ENDIAN && ( VALID_NEON_DREG_MODE ( mode ) || VALID_NEON_QREG_MODE ( mode ) ) && ( nelems >= 2 && nelems <= 4 ) ) return true ; if ( TARGET_HAVE_MVE && ! BYTES_BIG_ENDIAN && VALID_MVE_MODE ( mode ) && ( nelems == 2 || nelems == 4 ) ) return true ; return false ; } </s>

Implements target hook array_mode_supported_p .


<s> static bool ia64_return_in_memory ( tree valtype , tree fntype ATTRIBUTE_UNUSED ) { enum machine_mode mode ; enum machine_mode hfa_mode ; HOST_WIDE_INT byte_size ; mode = TYPE_MODE ( valtype ) ; byte_size = GET_MODE_SIZE ( mode ) ; if ( mode == BLKmode ) { byte_size = int_size_in_bytes ( valtype ) ; if ( byte_size < 0 ) return true ; } hfa_mode = hfa_element_mode ( valtype , 0 ) ; if ( hfa_mode != VOIDmode ) { int hfa_size = GET_MODE_SIZE ( hfa_mode ) ; if ( byte_size / hfa_size > MAX_ARGUMENT_SLOTS ) return true ; else return false ; } else if ( byte_size > UNITS_PER_WORD * MAX_INT_RETURN_SLOTS ) return true ; else return false ; } </s>

Return 1 if function return value returned in memory . Return 0 if it is in a register .


<s> rtx rs6000_allocate_stack_temp ( machine_mode mode , bool offsettable_p , bool reg_reg_p ) { rtx stack = assign_stack_temp ( mode , GET_MODE_SIZE ( mode ) ) ; rtx addr = XEXP ( stack , 0 ) ; int strict_p = ( reload_in_progress || reload_completed ) ; if ( ! legitimate_indirect_address_p ( addr , strict_p ) ) { if ( offsettable_p && ! rs6000_legitimate_offset_address_p ( mode , addr , strict_p , true ) ) stack = replace_equiv_address ( stack , copy_addr_to_reg ( addr ) ) ; else if ( reg_reg_p && ! legitimate_indexed_address_p ( addr , strict_p ) ) stack = replace_equiv_address ( stack , copy_addr_to_reg ( addr ) ) ; } return stack ; } </s>

Allocate a stack temp and fixup the address so it meets the particular memory requirements ( either offetable or REG+REG addressing ) .


<s> MVT SITargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( CC == CallingConv :: AMDGPU_KERNEL ) return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT ) ; if ( VT . isVector ( ) ) { EVT ScalarVT = VT . getScalarType ( ) ; unsigned Size = ScalarVT . getSizeInBits ( ) ; if ( Size == 32 ) return ScalarVT . getSimpleVT ( ) ; if ( Size > 32 ) return MVT :: i32 ; if ( Size == 16 && Subtarget -> has16BitInsts ( ) ) return VT . isInteger ( ) ? MVT :: v2i16 : MVT :: v2f16 ; } else if ( VT . getSizeInBits ( ) > 32 ) return MVT :: i32 ; return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


<s> void GCNHazardRecognizer :: Reset ( ) { EmittedInstrs . clear ( ) ; } </s>


<s> bool Mips16RegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { DebugLoc DL ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; TII . copyPhysReg ( MBB , I , DL , Mips :: T0 , Reg , true ) ; TII . copyPhysReg ( MBB , UseMI , DL , Reg , Mips :: T0 , true ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .


<s> static bool mips_interrupt_extra_call_saved_reg_p ( unsigned int regno ) { if ( ( ISA_HAS_HILO || TARGET_DSP ) && MD_REG_P ( regno ) ) return true ; if ( TARGET_DSP && DSP_ACC_REG_P ( regno ) ) return true ; if ( GP_REG_P ( regno ) && cfun -> machine -> use_shadow_register_set == SHADOW_SET_NO ) { if ( regno == GP_REG_FIRST ) return false ; if ( KERNEL_REG_P ( regno ) ) return false ; if ( regno == STACK_POINTER_REGNUM ) return false ; return call_really_used_regs [ regno ] ; } return false ; } </s>

Return true if REGNO is a register that is ordinarily call-clobbered but must nevertheless be preserved by an interrupt handler .


"Process function before frame finalized: "

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> const AArch64Subtarget * AArch64TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < AArch64Subtarget > ( TargetTriple , CPU , FS , * this , Subtarget . isLittleEndian ( ) ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; AArch64GISelActualAccessor * GISel = new AArch64GISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new AArch64CallLowering ( * I -> getTargetLowering ( ) ) ) ; GISel -> RegBankInfo . reset ( new AArch64RegisterBankInfo ( * I -> getRegisterInfo ( ) ) ) ; I -> setGISelAccessor ( * GISel ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> int avr_hard_regno_call_part_clobbered ( unsigned regno , machine_mode mode ) { if ( ! avr_hard_regno_mode_ok ( regno , mode ) ) return 0 ; return ( ( regno < 18 && regno + GET_MODE_SIZE ( mode ) > 18 ) || ( regno < REG_Y && regno + GET_MODE_SIZE ( mode ) > REG_Y ) || ( regno < REG_Z && regno + GET_MODE_SIZE ( mode ) > REG_Z ) ) ; } </s>

Implement ` HARD_REGNO_CALL_PART_CLOBBERED ' .


<s> static int cris_memory_move_cost ( machine_mode mode , reg_class_t rclass ATTRIBUTE_UNUSED , bool in ATTRIBUTE_UNUSED ) { if ( mode == QImode || mode == HImode ) return 4 ; else return 6 ; } </s>

Worker function for TARGET_MEMORY_MOVE_COST . This is n't strictly correct for v0 .. 3 in buswidth-8bit mode , but should suffice .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
]
=
{
{
"reloc_pcrel_4byte"
,
0
,
4
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_pcrel_1byte"
,
0
,
1
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_pcrel_2byte"
,
0
,
2
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte"
,
0
,
4
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_movq_load"
,
0
,
4
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCCodeEmitter
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> bool ARMBaseRegisterInfo :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; unsigned CFSize = FFI -> getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( 1 << 12 ) - 1 ) / 2 ) return false ; return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> bool MipsTargetELFStreamer :: emitDirectiveCpRestore ( int Offset , function_ref < unsigned ( ) > GetATReg , SMLoc IDLoc , const MCSubtargetInfo * STI ) { MipsTargetStreamer :: emitDirectiveCpRestore ( Offset , GetATReg , IDLoc , STI ) ; if ( ! Pic || ( getABI ( ) . IsN32 ( ) || getABI ( ) . IsN64 ( ) ) ) return true ; emitStoreWithImmOffset ( Mips :: SW , GPReg , Mips :: SP , Offset , GetATReg , IDLoc , STI ) ; return true ; } </s>


<s> BitVector SystemZRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const SystemZFrameLowering * TFI = getFrameLowering ( MF ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( SystemZ :: R11D ) ; Reserved . set ( SystemZ :: R11L ) ; Reserved . set ( SystemZ :: R11H ) ; Reserved . set ( SystemZ :: R10Q ) ; } Reserved . set ( SystemZ :: R15D ) ; Reserved . set ( SystemZ :: R15L ) ; Reserved . set ( SystemZ :: R15H ) ; Reserved . set ( SystemZ :: R14Q ) ; Reserved . set ( SystemZ :: A0 ) ; Reserved . set ( SystemZ :: A1 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


"convert address space of alloca'ed memory to local"

getPassName - Return a nice clean name for a pass .


<s> static LLT getPow2VectorType ( LLT Ty ) { unsigned NElts = Ty . getNumElements ( ) ; unsigned Pow2NElts = 1 << Log2_32_Ceil ( NElts ) ; return Ty . changeNumElements ( Pow2NElts ) ; } </s>

Widens the length of the given vector MVT up to the nearest power of 2 and returns that type .


<s> static bool classof ( const MCExpr * E ) { return E -> getKind ( ) == MCExpr :: Target ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> void XNCMFrameLowering :: emitPrologue ( MachineFunction & MF ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool MipsDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { bool Ret = SelectionDAGISel :: runOnMachineFunction ( MF ) ; ProcessFunctionAfterISel ( MF ) ; return Ret ; } </s>

runOnMachineFunction - Emit the function body .


<s> static void mep_trampoline_init ( rtx m_tramp , tree fndecl , rtx static_chain ) { rtx addr = XEXP ( m_tramp , 0 ) ; rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , "__mep_trampoline_helper" ) , LCT_NORMAL , VOIDmode , 3 , addr , Pmode , fnaddr , Pmode , static_chain , Pmode ) ; } </s>


<s> const HexagonInstrInfo * getInstrInfo ( ) const override { return getSubtargetImpl ( ) -> getInstrInfo ( ) ; } </s>


<s> int label_mentioned_p ( rtx x ) { const char * fmt ; int i ; if ( GET_CODE ( x ) == LABEL_REF ) return 1 ; if ( GET_CODE ( x ) == UNSPEC ) return 0 ; fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( x , i ) - 1 ; j >= 0 ; j -- ) if ( label_mentioned_p ( XVECEXP ( x , i , j ) ) ) return 1 ; } else if ( fmt [ i ] == 'e' && label_mentioned_p ( XEXP ( x , i ) ) ) return 1 ; } return 0 ; } </s>

Return TRUE if X references a LABEL_REF .


<s> void SICAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( Fixup , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { default : FullSize = 4 ; break ; } uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - 1 - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void PPCRegisterInfo :: adjustStackMapLiveOutMask ( uint32_t * Mask ) const { unsigned PseudoRegs [ ] = { PPC :: ZERO , PPC :: ZERO8 , PPC :: RM } ; for ( unsigned i = 0 , ie = array_lengthof ( PseudoRegs ) ; i != ie ; ++ i ) { unsigned Reg = PseudoRegs [ i ] ; Mask [ Reg / 32 ] &= ~ ( 1u << ( Reg % 32 ) ) ; } } </s>

Prior to adding the live-out mask to a stackmap or patchpoint instruction , provide the target the opportunity to adjust it ( mainly to remove pseudo-registers that should be ignored ) .


<s>
unsigned
SIRegisterInfo
::
getRegPressureSetLimit
(
const
MachineFunction
&
MF
,
unsigned
Idx
)
const
{
if
(
Idx
==
AMDGPU
::
RegisterPressureSets
::
VGPR_32
||
Idx
==
AMDGPU
::
RegisterPressureSets
::
AGPR_32
)
return
getRegPressureLimit
(
&
AMDGPU
::
VGPR_32RegClass
,
const_cast
<
MachineFunction
&
>
(
MF
)
)
;
if
(
Idx
==
AMDGPU
::
RegisterPressureSets
::
SReg_32
)
return
getRegPressureLimit
(
&
AMDGPU
::
SGPR_32RegClass
,
const_cast
<
MachineFunction
&
>
(
MF
)
)
;
llvm_unreachable
(
"Unexpected register pressure set!"
)
;
}
</s>

Get the register unit pressure limit for this dimension .

AMDGPU
SI
AMDGPU::RegisterPressureSets
AMDGPU::RegisterPressureSets
AMDGPU::VGPR_32RegClass
AMDGPU::RegisterPressureSets
AMDGPU::SGPR_32RegClass
"Unexpected register pressure set!"


<s> bool MBlazePassConfig :: addPreEmitPass ( ) { PM -> add ( createMBlazeDelaySlotFillerPass ( getMBlazeTargetMachine ( ) ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
void
HexagonEarlyIfConversion
::
removeBlock
(
MachineBasicBlock
*
B
)
{
DEBUG
(
dbgs
(
)
<<
"Removing block "
<<
PrintMB
(
B
)
<<
"\n"
)
;
MachineDomTreeNode
*
N
=
MDT
->
getNode
(
B
)
;
MachineDomTreeNode
*
IDN
=
N
->
getIDom
(
)
;
if
(
IDN
)
{
MachineBasicBlock
*
IDB
=
IDN
->
getBlock
(
)
;
typedef
GraphTraits
<
MachineDomTreeNode
*
>
GTN
;
typedef
SmallVector
<
MachineDomTreeNode
*
,
4
>
DTNodeVectType
;
DTNodeVectType
Cn
(
GTN
::
child_begin
(
N
)
,
GTN
::
child_end
(
N
)
)
;
for
(
DTNodeVectType
::
iterator
I
=
Cn
.
begin
(
)
,
E
=
Cn
.
end
(
)
;
I
!=
E
;
++
I
)
{
MachineBasicBlock
*
SB
=
(
*
I
)
->
getBlock
(
)
;
MDT
->
changeImmediateDominator
(
SB
,
IDB
)
;
}
}
while
(
B
->
succ_size
(
)
>
0
)
B
->
removeSuccessor
(
B
->
succ_begin
(
)
)
;
for
(
auto
I
=
B
->
pred_begin
(
)
,
E
=
B
->
pred_end
(
)
;
I
!=
E
;
++
I
)
(
*
I
)
->
removeSuccessor
(
B
,
true
)
;
Deleted
.
insert
(
B
)
;
MDT
->
eraseNode
(
B
)
;
MFN
->
erase
(
B
->
getIterator
(
)
)
;
}
</s>

This method completely removes BB from all data structures , including all of the Loop objects it is nested in and our mapping from MachineBasicBlocks to loops .

Hexagon
Hexagon
"Removing block "
"\n"
4
0


<s> unsigned X86RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const X86FrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? FramePtr : StackPtr ; } </s>


"Register sequence is not valid. 'r4-r7' expected"

Process a single instruction and collect debug info anchors .


<s> void ARM64_ELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; } </s>

This method must be called before any actual lowering is done .


"Missing init of reg %u inserted on edge: %d -> %d:"

Find uses of regs that are not defined on all incoming paths , and insert a corresponding def on those . Advantage : Does n't create long live ranges . Disadvantage : More complex , and potentially also more defs .


<s> static HOST_WIDE_INT cris_constant_alignment ( const_tree , HOST_WIDE_INT basic_align ) { return MAX ( cris_preferred_mininum_alignment ( ) , basic_align ) ; } </s>

Implement TARGET_CONSTANT_ALIGNMENT . Note that this hook has the effect of making gcc believe that ALL references to constant stuff ( in code segment , like strings ) have this alignment . That is a rather rushed assumption . Luckily we do not care about the `` alignment '' operand to builtin memcpy ( only place where it counts ) , so it does n't affect any bad spots .


<s> bool X86PartialReduction :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; auto & TM = TPC -> getTM < X86TargetMachine > ( ) ; ST = TM . getSubtargetImpl ( F ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; bool MadeChange = false ; for ( auto & BB : F ) { for ( auto & I : BB ) { auto * EE = dyn_cast < ExtractElementInst > ( & I ) ; if ( ! EE ) continue ; Value * Root = matchAddReduction ( * EE ) ; if ( ! Root ) continue ; SmallVector < Instruction * , 8 > Leaves ; collectLeaves ( Root , Leaves ) ; for ( Instruction * I : Leaves ) { if ( tryMAddReplacement ( I ) ) { MadeChange = true ; continue ; } if ( I != Root && trySADReplacement ( I ) ) MadeChange = true ; } } } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool avr_emit_movmemhi ( rtx * xop ) { HOST_WIDE_INT count ; machine_mode loop_mode ; addr_space_t as = MEM_ADDR_SPACE ( xop [ 1 ] ) ; rtx loop_reg , addr1 , a_src , a_dest , insn , xas ; rtx a_hi8 = NULL_RTX ; if ( avr_mem_flash_p ( xop [ 0 ] ) ) return false ; if ( ! CONST_INT_P ( xop [ 2 ] ) ) return false ; count = INTVAL ( xop [ 2 ] ) ; if ( count <= 0 ) return false ; a_src = XEXP ( xop [ 1 ] , 0 ) ; a_dest = XEXP ( xop [ 0 ] , 0 ) ; if ( PSImode == GET_MODE ( a_src ) ) { gcc_assert ( as == ADDR_SPACE_MEMX ) ; loop_mode = ( count < 0x100 ) ? QImode : HImode ; loop_reg = gen_rtx_REG ( loop_mode , 24 ) ; emit_move_insn ( loop_reg , gen_int_mode ( count , loop_mode ) ) ; addr1 = simplify_gen_subreg ( HImode , a_src , PSImode , 0 ) ; a_hi8 = simplify_gen_subreg ( QImode , a_src , PSImode , 2 ) ; } else { int segment = avr_addrspace [ as ] . segment ; if ( segment && avr_n_flash > 1 ) { a_hi8 = GEN_INT ( segment ) ; emit_move_insn ( rampz_rtx , a_hi8 = copy_to_mode_reg ( QImode , a_hi8 ) ) ; } else if ( ! ADDR_SPACE_GENERIC_P ( as ) ) { as = ADDR_SPACE_FLASH ; } addr1 = a_src ; loop_mode = ( count <= 0x100 ) ? QImode : HImode ; loop_reg = copy_to_mode_reg ( loop_mode , gen_int_mode ( count , loop_mode ) ) ; } xas = GEN_INT ( as ) ; emit_move_insn ( lpm_addr_reg_rtx , addr1 ) ; emit_move_insn ( gen_rtx_REG ( HImode , REG_X ) , a_dest ) ; gcc_assert ( TMP_REGNO == LPM_REGNO ) ; if ( as != ADDR_SPACE_MEMX ) { rtx ( * fun ) ( rtx , rtx , rtx ) = QImode == loop_mode ? gen_movmem_qi : gen_movmem_hi ; insn = fun ( xas , loop_reg , loop_reg ) ; } else { rtx ( * fun ) ( rtx , rtx ) = QImode == loop_mode ? gen_movmemx_qi : gen_movmemx_hi ; emit_move_insn ( gen_rtx_REG ( QImode , 23 ) , a_hi8 ) ; insn = fun ( xas , GEN_INT ( avr_addr . rampz ) ) ; } set_mem_addr_space ( SET_SRC ( XVECEXP ( insn , 0 , 0 ) ) , as ) ; emit_insn ( insn ) ; return true ; } </s>

Worker function for movmemhi expander . XOP [ 0 ] Destination as MEM : BLK XOP [ 1 ] Source `` `` XOP [ 2 ] # Bytes to copy Return TRUE if the expansion is accomplished . Return FALSE if the operand compination is not supported .


"unknown MIR custom pseudo source value"

Implement target specific parsing of target custom pseudo source value .


<s> MVT WebAssemblyTargetLowering :: getScalarShiftAmountTy ( const DataLayout & DL , EVT VT ) const { return VT . getSimpleVT ( ) ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> bool tilegx_expand_muldi ( rtx op0 , rtx op1 , rtx op2 ) { if ( CONST_INT_P ( op2 ) ) { HOST_WIDE_INT n = trunc_int_for_mode ( INTVAL ( op2 ) , DImode ) ; return tilegx_expand_const_muldi ( op0 , op1 , n ) ; } return false ; } </s>


<s> void NVPTXFrameLowering :: emitPrologue ( MachineFunction & MF ) const { if ( MF . getFrameInfo ( ) -> hasStackObjects ( ) ) { MachineBasicBlock & MBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = DebugLoc ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( static_cast < const NVPTXTargetMachine & > ( MF . getTarget ( ) ) . is64Bit ( ) ) { unsigned LocalReg = MRI . createVirtualRegister ( & NVPTX :: Int64RegsRegClass ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , dl , MF . getSubtarget ( ) . getInstrInfo ( ) -> get ( NVPTX :: cvta_local_yes_64 ) , NVPTX :: VRFrame ) . addReg ( LocalReg ) ; BuildMI ( MBB , MI , dl , MF . getSubtarget ( ) . getInstrInfo ( ) -> get ( NVPTX :: MOV_DEPOT_ADDR_64 ) , LocalReg ) . addImm ( MF . getFunctionNumber ( ) ) ; } else { unsigned LocalReg = MRI . createVirtualRegister ( & NVPTX :: Int32RegsRegClass ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , dl , MF . getSubtarget ( ) . getInstrInfo ( ) -> get ( NVPTX :: cvta_local_yes ) , NVPTX :: VRFrame ) . addReg ( LocalReg ) ; BuildMI ( MBB , MI , dl , MF . getSubtarget ( ) . getInstrInfo ( ) -> get ( NVPTX :: MOV_DEPOT_ADDR ) , LocalReg ) . addImm ( MF . getFunctionNumber ( ) ) ; } } } </s>


<s> bool shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) override { return STI . getFeatureBits ( ) [ RISCV :: FeatureRelax ] ; } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> static bool msp430_preserve_reg_p ( int regno ) { if ( regno <= 3 ) return false ; if ( crtl -> calls_eh_return ) return true ; if ( fixed_regs [ regno ] ) return false ; if ( msp430_is_interrupt_func ( ) ) return ! crtl -> is_leaf || df_regs_ever_live_p ( regno ) ; if ( ! call_used_regs [ regno ] && df_regs_ever_live_p ( regno ) ) return true ; return false ; } </s>

This is the one spot that decides if a register is to be saved and restored in the prologue/epilogue .


<s> static bool compute_fp_layout ( const_tree field , HOST_WIDE_INT bitpos , assign_data_t * data , int * pnregs , machine_mode * pmode ) { const int this_slotno = data -> slotno + bitpos / BITS_PER_WORD ; machine_mode mode = DECL_MODE ( field ) ; int nregs , nslots ; if ( TREE_CODE ( TREE_TYPE ( field ) ) == VECTOR_TYPE && mode == BLKmode ) { mode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( field ) ) ) ; nregs = TYPE_VECTOR_SUBPARTS ( TREE_TYPE ( field ) ) ; } else if ( TREE_CODE ( TREE_TYPE ( field ) ) == COMPLEX_TYPE ) { mode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( field ) ) ) ; nregs = 2 ; } else nregs = 1 ; nslots = CEIL_NWORDS ( nregs * GET_MODE_SIZE ( mode ) ) ; if ( nslots > SPARC_FP_ARG_MAX - this_slotno ) { nslots = SPARC_FP_ARG_MAX - this_slotno ; nregs = ( nslots * UNITS_PER_WORD ) / GET_MODE_SIZE ( mode ) ; data -> stack = 1 ; if ( nregs <= 0 ) return false ; } * pnregs = nregs ; * pmode = mode ; return true ; } </s>

A subroutine of function_arg_record_value . Compute the number and the mode of the FP registers to be assigned for FIELD . Return true if at least one FP register is assigned or false otherwise .


<s> int HexagonInstrInfo :: getMaxValue ( const MachineInstr & MI ) const { const uint64_t F = MI . getDesc ( ) . TSFlags ; unsigned isSigned = ( F >> HexagonII :: ExtentSignedPos ) & HexagonII :: ExtentSignedMask ; unsigned bits = ( F >> HexagonII :: ExtentBitsPos ) & HexagonII :: ExtentBitsMask ; if ( isSigned ) return ~ ( - 1U << ( bits - 1 ) ) ; else return ~ ( - 1U << bits ) ; } </s>

Return the maximal unsigned value possible given these KnownBits .

Hexagon Hexagon HexagonII::ExtentSignedPos HexagonII::ExtentSignedMask HexagonII::ExtentBitsPos HexagonII::ExtentBitsMask 1U 1 1U


<s> void ARMHazardRecognizer :: Reset ( ) { LastMI = 0 ; FpMLxStalls = 0 ; ScoreboardHazardRecognizer :: Reset ( ) ; } </s>


<s>
TargetIRAnalysis
MipsTargetMachine
::
getTargetIRAnalysis
(
)
{
return
TargetIRAnalysis
(
[
this
]
(
Function
&
F
)
{
if
(
Subtarget
->
allowMixed16_32
(
)
)
{
DEBUG
(
errs
(
)
<<
"No Target Transform Info Pass Added\n"
)
;
return
TargetTransformInfo
(
F
.
getParent
(
)
->
getDataLayout
(
)
)
;
}
DEBUG
(
errs
(
)
<<
"Target Transform Info Pass Added\n"
)
;
return
TargetTransformInfo
(
BasicTTIImpl
(
this
,
F
)
)
;
}
)
;
}
</s>

Get a TargetIRAnalysis appropriate for the target .

Mips
Mips
"No Target Transform Info Pass Added\n"
"Target Transform Info Pass Added\n"


<s> static void bpf_init_libfuncs ( void ) { set_conv_libfunc ( sext_optab , DFmode , SFmode , "__bpf_extendsfdf2" ) ; set_conv_libfunc ( trunc_optab , SFmode , DFmode , "__bpf_truncdfsf2" ) ; set_conv_libfunc ( sfix_optab , SImode , DFmode , "__bpf_fix_truncdfsi" ) ; set_conv_libfunc ( sfloat_optab , DFmode , SImode , "__bpf_floatsidf" ) ; set_conv_libfunc ( ufloat_optab , DFmode , SImode , "__bpf_floatunsidf" ) ; } </s>

Initialize target-specific function library calls . This is mainly used to call library-provided soft-fp operations , since eBPF does n't support floating-point in `` hardware '' .


<s> static bool insn_uses_reg_p ( rtx_insn * insn , unsigned int reg ) { extract_insn ( insn ) ; return ( ( REG_P ( recog_data . operand [ 1 ] ) && REGNO ( recog_data . operand [ 1 ] ) == reg ) || ( recog_data . n_operands == 3 && REG_P ( recog_data . operand [ 2 ] ) && REGNO ( recog_data . operand [ 2 ] ) == reg ) ) ; } </s>

True if any of INSN 's source register ( s ) is REG .


<s> static bool arc_mode_dependent_address_p ( const_rtx addr , addr_space_t ) { if ( GET_CODE ( addr ) == PLUS && ( GET_CODE ( XEXP ( ( addr ) , 0 ) ) == MULT || ( CONST_INT_P ( XEXP ( ( addr ) , 1 ) ) && ! SMALL_INT ( INTVAL ( XEXP ( ( addr ) , 1 ) ) ) ) ) ) return true ; return false ; } </s>

Return true iff ADDR ( a legitimate address expression ) has an effect that depends on the machine mode it is used for .


<s> gimple * gimple_folder :: fold_to_cstu ( poly_uint64 val ) { return gimple_build_assign ( lhs , build_int_cstu ( TREE_TYPE ( lhs ) , val ) ) ; } </s>


<s> bool RISCVCallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < Register > VRegs , FunctionLoweringInfo & FLI ) const { MachineInstrBuilder Ret = MIRBuilder . buildInstrNoInsert ( RISCV :: PseudoRET ) ; if ( Val != nullptr ) { return false ; } MIRBuilder . insertInstr ( Ret ) ; return true ; } </s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> static rtx sh_allocate_initial_value ( rtx hard_reg ) { rtx x ; if ( REGNO ( hard_reg ) == ( TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG ) ) { if ( crtl -> is_leaf && ! sh_pr_n_sets ( ) && ! ( TARGET_SHCOMPACT && ( ( crtl -> args . info . call_cookie & ~ CALL_COOKIE_RET_TRAMP ( 1 ) ) || crtl -> saves_all_registers ) ) ) x = hard_reg ; else x = gen_frame_mem ( Pmode , return_address_pointer_rtx ) ; } else x = NULL_RTX ; return x ; } </s>

Return where to allocate pseudo for a given hard register initial value .


<s> bool HexagonAsmPrinter :: isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { if ( MBB -> hasAddressTaken ( ) ) return false ; return AsmPrinter :: isBlockOnlyReachableByFallthrough ( MBB ) ; } </s>

isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


<s> int function_arg_boundary ( enum machine_mode mode , tree type ) { unsigned int alignment ; alignment = type ? TYPE_ALIGN ( type ) : GET_MODE_ALIGNMENT ( mode ) ; if ( alignment < PARM_BOUNDARY ) alignment = PARM_BOUNDARY ; if ( alignment > STACK_BOUNDARY ) alignment = STACK_BOUNDARY ; return alignment ; } </s>

If defined , a C expression that gives the alignment boundary , in bits , of an argument with the specified mode and type . If it is not defined , PARM_BOUNDARY is used for all arguments . V.4 wants long longs to be double word aligned . Doubleword align SPE vectors . Quadword align Altivec vectors . Quadword align large synthetic vector types .


<s> unsigned MipsSEInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( ( Opc == Mips :: LW ) || ( Opc == Mips :: LW_P8 ) || ( Opc == Mips :: LD ) || ( Opc == Mips :: LD_P8 ) || ( Opc == Mips :: LWC1 ) || ( Opc == Mips :: LWC1_P8 ) || ( Opc == Mips :: LDC1 ) || ( Opc == Mips :: LDC164 ) || ( Opc == Mips :: LDC164_P8 ) ) { if ( ( MI -> getOperand ( 1 ) . isFI ( ) ) && ( MI -> getOperand ( 2 ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( 2 ) ) ) ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> bool RISCVTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; Optional < unsigned > FirstMaskArgument ; if ( Subtarget . hasStdExtV ( ) ) preAssignMask ( Outs , FirstMaskArgument , CCInfo ) ; for ( unsigned i = 0 , e = Outs . size ( ) ; i != e ; ++ i ) { MVT VT = Outs [ i ] . VT ; ISD :: ArgFlagsTy ArgFlags = Outs [ i ] . Flags ; RISCVABI :: ABI ABI = MF . getSubtarget < RISCVSubtarget > ( ) . getTargetABI ( ) ; if ( CC_RISCV ( MF . getDataLayout ( ) , ABI , i , VT , VT , CCValAssign :: Full , ArgFlags , CCInfo , true , true , nullptr , * this , FirstMaskArgument ) ) return false ; } return true ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .

RISCV RISCV ISD::OutputArg 16 0 ISD::ArgFlagsTy RISCVABI::ABI RISCV RISCV


";; %smode fixup for i%d; addr %lu, range (%ld,%ld): "

Record INSN , which will need fixing up to load a value from the minipool . ADDRESS is the offset of the insn since the start of the function ; LOC is a pointer to the part of the insn which requires fixing ; VALUE is the constant that must be loaded , which is of type MODE .


<s> bool runOnMachineFunction ( MachineFunction & MF ) { fixIMPLICITDEF ( MF ) ; fixNoReturn ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool loongarch_use_ins_ext_p ( rtx op , HOST_WIDE_INT width , HOST_WIDE_INT bitpos ) { if ( ! register_operand ( op , VOIDmode ) || GET_MODE_BITSIZE ( GET_MODE ( op ) ) > BITS_PER_WORD ) return false ; if ( ! IN_RANGE ( width , 1 , GET_MODE_BITSIZE ( GET_MODE ( op ) ) - 1 ) ) return false ; if ( bitpos < 0 || bitpos + width > GET_MODE_BITSIZE ( GET_MODE ( op ) ) ) return false ; return true ; } </s>

Return true if ( zero_extract OP WIDTH BITPOS ) can be used as the source of an `` ext '' instruction or the destination of an `` ins '' instruction . OP must be a register operand and the following conditions must hold : 0 < = BITPOS < GET_MODE_BITSIZE ( GET_MODE ( op ) ) 0 < WIDTH < = GET_MODE_BITSIZE ( GET_MODE ( op ) ) 0 < BITPOS + WIDTH < = GET_MODE_BITSIZE ( GET_MODE ( op ) ) Also reject lengths equal to a word as they are better handled by the move patterns .


<s> bool R600InstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return false ; if ( isBranch ( I -> getOpcode ( ) ) ) return true ; if ( ! isJump ( I -> getOpcode ( ) ) ) { return false ; } while ( I != MBB . begin ( ) && std :: prev ( I ) -> getOpcode ( ) == AMDGPU :: JUMP ) { MachineBasicBlock :: iterator PriorI = std :: prev ( I ) ; if ( AllowModify ) I -> removeFromParent ( ) ; I = PriorI ; } MachineInstr & LastInst = * I ; unsigned LastOpc = LastInst . getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isJump ( ( -- I ) -> getOpcode ( ) ) ) { if ( LastOpc == AMDGPU :: JUMP ) { TBB = LastInst . getOperand ( 0 ) . getMBB ( ) ; return false ; } else if ( LastOpc == AMDGPU :: JUMP_COND ) { auto predSet = I ; while ( ! isPredicateSetter ( predSet -> getOpcode ( ) ) ) { predSet = -- I ; } TBB = LastInst . getOperand ( 0 ) . getMBB ( ) ; Cond . push_back ( predSet -> getOperand ( 1 ) ) ; Cond . push_back ( predSet -> getOperand ( 2 ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( AMDGPU :: PRED_SEL_ONE , false ) ) ; return false ; } return true ; } MachineInstr & SecondLastInst = * I ; unsigned SecondLastOpc = SecondLastInst . getOpcode ( ) ; if ( SecondLastOpc == AMDGPU :: JUMP_COND && LastOpc == AMDGPU :: JUMP ) { auto predSet = -- I ; while ( ! isPredicateSetter ( predSet -> getOpcode ( ) ) ) { predSet = -- I ; } TBB = SecondLastInst . getOperand ( 0 ) . getMBB ( ) ; FBB = LastInst . getOperand ( 0 ) . getMBB ( ) ; Cond . push_back ( predSet -> getOperand ( 1 ) ) ; Cond . push_back ( predSet -> getOperand ( 2 ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( AMDGPU :: PRED_SEL_ONE , false ) ) ; return false ; } return true ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> void KudeyarTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s> bool addRegAssignAndRewriteFast ( ) override { return false ; } </s>

Add core register allocator passes which do the actual register assignment and rewriting .


<s> unsigned PatmosMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { return getMachineOpValue ( MI , MO , Fixups ) ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> const uint16_t * MSP430RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const TargetFrameLowering * TFI = MF -> getTarget ( ) . getFrameLowering ( ) ; const Function * F = MF -> getFunction ( ) ; static const uint16_t CalleeSavedRegs [ ] = { MSP430 :: FPW , MSP430 :: R5W , MSP430 :: R6W , MSP430 :: R7W , MSP430 :: R8W , MSP430 :: R9W , MSP430 :: R10W , MSP430 :: R11W , 0 } ; static const uint16_t CalleeSavedRegsFP [ ] = { MSP430 :: R5W , MSP430 :: R6W , MSP430 :: R7W , MSP430 :: R8W , MSP430 :: R9W , MSP430 :: R10W , MSP430 :: R11W , 0 } ; static const uint16_t CalleeSavedRegsIntr [ ] = { MSP430 :: FPW , MSP430 :: R5W , MSP430 :: R6W , MSP430 :: R7W , MSP430 :: R8W , MSP430 :: R9W , MSP430 :: R10W , MSP430 :: R11W , MSP430 :: R12W , MSP430 :: R13W , MSP430 :: R14W , MSP430 :: R15W , 0 } ; static const uint16_t CalleeSavedRegsIntrFP [ ] = { MSP430 :: R5W , MSP430 :: R6W , MSP430 :: R7W , MSP430 :: R8W , MSP430 :: R9W , MSP430 :: R10W , MSP430 :: R11W , MSP430 :: R12W , MSP430 :: R13W , MSP430 :: R14W , MSP430 :: R15W , 0 } ; if ( TFI -> hasFP ( * MF ) ) return ( F -> getCallingConv ( ) == CallingConv :: MSP430_INTR ? CalleeSavedRegsIntrFP : CalleeSavedRegsFP ) ; else return ( F -> getCallingConv ( ) == CallingConv :: MSP430_INTR ? CalleeSavedRegsIntr : CalleeSavedRegs ) ; } </s>


<s> bool SITargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & CI , MachineFunction & MF , unsigned IntrID ) const { if ( const AMDGPU :: RsrcIntrinsic * RsrcIntr = AMDGPU :: lookupRsrcIntrinsicByIntr ( IntrID ) ) { AttributeList Attr = Intrinsic :: getAttributes ( CI . getContext ( ) , ( Intrinsic :: ID ) IntrID ) ; if ( Attr . hasFnAttribute ( Attribute :: ReadNone ) ) return false ; SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; if ( RsrcIntr -> IsImage ) { Info . ptrVal = MFI -> getImagePSV ( * MF . getSubtarget < SISubtarget > ( ) . getInstrInfo ( ) , CI . getArgOperand ( RsrcIntr -> RsrcArg ) ) ; Info . align = 0 ; } else { Info . ptrVal = MFI -> getBufferPSV ( * MF . getSubtarget < SISubtarget > ( ) . getInstrInfo ( ) , CI . getArgOperand ( RsrcIntr -> RsrcArg ) ) ; } Info . flags = MachineMemOperand :: MODereferenceable ; if ( Attr . hasFnAttribute ( Attribute :: ReadOnly ) ) { Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: getVT ( CI . getType ( ) ) ; Info . flags |= MachineMemOperand :: MOLoad ; } else if ( Attr . hasFnAttribute ( Attribute :: WriteOnly ) ) { Info . opc = ISD :: INTRINSIC_VOID ; Info . memVT = MVT :: getVT ( CI . getArgOperand ( 0 ) -> getType ( ) ) ; Info . flags |= MachineMemOperand :: MOStore ; } else { Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: getVT ( CI . getType ( ) ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MODereferenceable ; Info . flags |= MachineMemOperand :: MOVolatile ; } return true ; } switch ( IntrID ) { case Intrinsic :: amdgcn_atomic_inc : case Intrinsic :: amdgcn_atomic_dec : case Intrinsic :: amdgcn_ds_fadd : case Intrinsic :: amdgcn_ds_fmin : case Intrinsic :: amdgcn_ds_fmax : { Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: getVT ( CI . getType ( ) ) ; Info . ptrVal = CI . getOperand ( 0 ) ; Info . align = 0 ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore ; const ConstantInt * Vol = dyn_cast < ConstantInt > ( CI . getOperand ( 4 ) ) ; if ( ! Vol || ! Vol -> isZero ( ) ) Info . flags |= MachineMemOperand :: MOVolatile ; return true ; } default : return false ; } } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .