<s> static bool microblaze_const_double_ok ( rtx op , machine_mode mode ) { REAL_VALUE_TYPE d ; if ( GET_CODE ( op ) != CONST_DOUBLE ) return 0 ; if ( GET_MODE ( op ) == VOIDmode ) return 1 ; if ( mode != SFmode && mode != DFmode ) return 0 ; if ( op == CONST0_RTX ( mode ) ) return 1 ; REAL_VALUE_FROM_CONST_DOUBLE ( d , op ) ; if ( REAL_VALUE_ISNAN ( d ) ) return FALSE ; if ( REAL_VALUE_NEGATIVE ( d ) ) d = real_value_negate ( & d ) ; if ( mode == DFmode ) { if ( REAL_VALUES_LESS ( d , dfhigh ) && REAL_VALUES_LESS ( dflow , d ) ) return 1 ; } else { if ( REAL_VALUES_LESS ( d , sfhigh ) && REAL_VALUES_LESS ( sflow , d ) ) return 1 ; } return 0 ; } </s>

Return truth value if a CONST_DOUBLE is ok to be a legitimate constant .


<s> TargetLowering :: AtomicExpansionKind AArch64TargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { if ( AI -> isFloatingPointOperation ( ) ) return AtomicExpansionKind :: CmpXChg ; unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size > 128 ) return AtomicExpansionKind :: None ; if ( AI -> getOperation ( ) != AtomicRMWInst :: Nand && Size < 128 ) { if ( Subtarget -> hasLSE ( ) ) return AtomicExpansionKind :: None ; if ( Subtarget -> outlineAtomics ( ) ) { if ( AI -> getOperation ( ) != AtomicRMWInst :: Min && AI -> getOperation ( ) != AtomicRMWInst :: Max && AI -> getOperation ( ) != AtomicRMWInst :: UMin && AI -> getOperation ( ) != AtomicRMWInst :: UMax ) { return AtomicExpansionKind :: None ; } } } if ( getTargetMachine ( ) . getOptLevel ( ) == CodeGenOpt :: None ) return AtomicExpansionKind :: CmpXChg ; return AtomicExpansionKind :: LLSC ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> static rtx sparc_legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , machine_mode mode ) { rtx orig_x = x ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 0 ) ) == MULT ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , 1 ) , force_operand ( XEXP ( x , 0 ) , NULL_RTX ) ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 1 ) ) == MULT ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , 0 ) , force_operand ( XEXP ( x , 1 ) , NULL_RTX ) ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 0 ) ) == PLUS ) x = gen_rtx_PLUS ( Pmode , force_operand ( XEXP ( x , 0 ) , NULL_RTX ) , XEXP ( x , 1 ) ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 1 ) ) == PLUS ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , 0 ) , force_operand ( XEXP ( x , 1 ) , NULL_RTX ) ) ; if ( x != orig_x && sparc_legitimate_address_p ( mode , x , FALSE ) ) return x ; if ( sparc_tls_referenced_p ( x ) ) x = sparc_legitimize_tls_address ( x ) ; else if ( flag_pic ) x = sparc_legitimize_pic_address ( x , NULL_RTX ) ; else if ( GET_CODE ( x ) == PLUS && CONSTANT_ADDRESS_P ( XEXP ( x , 1 ) ) ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , 0 ) , copy_to_mode_reg ( Pmode , XEXP ( x , 1 ) ) ) ; else if ( GET_CODE ( x ) == PLUS && CONSTANT_ADDRESS_P ( XEXP ( x , 0 ) ) ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , 1 ) , copy_to_mode_reg ( Pmode , XEXP ( x , 0 ) ) ) ; else if ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == CONST || GET_CODE ( x ) == LABEL_REF ) x = copy_to_suggested_reg ( x , NULL_RTX , Pmode ) ; return x ; } </s>

Try machine-dependent ways of modifying an illegitimate address X to be legitimate . If we find one , return the new , valid address . OLDX is the address as it was before break_out_memory_refs was called . In some cases it is useful to look at this to decide what needs to be done . MODE is the mode of the operand pointed to by X . On SPARC , change REG+N into REG+REG , and REG+ ( X * Y ) into REG+REG .


<s> bool aarch64_prepare_sve_cond_int_fma ( rtx * operands , rtx_code code ) { machine_mode mode = GET_MODE ( operands [ 0 ] ) ; if ( rtx shifts = aarch64_convert_mult_to_shift ( operands [ 3 ] , code ) ) { rtx product = expand_binop ( mode , vashl_optab , operands [ 2 ] , shifts , NULL_RTX , true , OPTAB_DIRECT ) ; emit_insn ( gen_cond ( code , mode , operands [ 0 ] , operands [ 1 ] , operands [ 4 ] , product , operands [ 5 ] ) ) ; return true ; } operands [ 3 ] = force_reg ( mode , operands [ 3 ] ) ; return false ; } </s>

Likewise , but for a conditional pattern .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"SI insert wait  instructions"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> int arm_legitimate_address_outer_p ( machine_mode mode , rtx x , RTX_CODE outer , int strict_p ) { bool use_ldrd ; enum rtx_code code = GET_CODE ( x ) ; if ( arm_address_register_rtx_p ( x , strict_p ) ) return 1 ; use_ldrd = ( TARGET_LDRD && ( mode == DImode || ( mode == DFmode && ( TARGET_SOFT_FLOAT || TARGET_VFP ) ) ) ) ; if ( code == POST_INC || code == PRE_DEC || ( ( code == PRE_INC || code == POST_DEC ) && ( use_ldrd || GET_MODE_SIZE ( mode ) <= 4 ) ) ) return arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) ; else if ( ( code == POST_MODIFY || code == PRE_MODIFY ) && arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) && GET_CODE ( XEXP ( x , 1 ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( x , 1 ) , 0 ) , XEXP ( x , 0 ) ) ) { rtx addend = XEXP ( XEXP ( x , 1 ) , 1 ) ; if ( use_ldrd && GET_CODE ( x ) == POST_MODIFY && REG_P ( addend ) ) return 0 ; return ( ( use_ldrd || GET_MODE_SIZE ( mode ) <= 4 ) && arm_legitimate_index_p ( mode , addend , outer , strict_p ) ) ; } else if ( reload_completed && ( code == LABEL_REF || ( code == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ) ) ) return 1 ; else if ( mode == TImode || ( TARGET_NEON && VALID_NEON_STRUCT_MODE ( mode ) ) ) return 0 ; else if ( code == PLUS ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; return ( ( arm_address_register_rtx_p ( xop0 , strict_p ) && ( ( CONST_INT_P ( xop1 ) && arm_legitimate_index_p ( mode , xop1 , outer , strict_p ) ) || ( ! strict_p && will_be_in_index_register ( xop1 ) ) ) ) || ( arm_address_register_rtx_p ( xop1 , strict_p ) && arm_legitimate_index_p ( mode , xop0 , outer , strict_p ) ) ) ; } else if ( GET_CODE ( x ) == MINUS ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; return ( arm_address_register_rtx_p ( xop0 , strict_p ) && arm_legitimate_index_p ( mode , xop1 , outer , strict_p ) ) ; } else if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && code == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) && ! ( flag_pic && symbol_mentioned_p ( get_pool_constant ( x ) ) && ! pcrel_constant_p ( get_pool_constant ( x ) ) ) ) return 1 ; return 0 ; } </s>

Return nonzero if X is a valid ARM state address operand .


<s> void SIFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const SIMachineFunctionInfo * FuncInfo = MF . getInfo < SIMachineFunctionInfo > ( ) ; if ( FuncInfo -> isEntryFunction ( ) ) return ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const SIInstrInfo * TII = ST . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; DebugLoc DL ; unsigned ScratchExecCopy = AMDGPU :: NoRegister ; for ( const SIMachineFunctionInfo :: SGPRSpillVGPRCSR & Reg : FuncInfo -> getSGPRSpillVGPRs ( ) ) { if ( ! Reg . FI . hasValue ( ) ) continue ; if ( ScratchExecCopy == AMDGPU :: NoRegister ) { LivePhysRegs LiveRegs ( * ST . getRegisterInfo ( ) ) ; LiveRegs . addLiveIns ( MBB ) ; ScratchExecCopy = findScratchNonCalleeSaveRegister ( MF , LiveRegs , AMDGPU :: SReg_64_XEXECRegClass ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( AMDGPU :: S_OR_SAVEEXEC_B64 ) , ScratchExecCopy ) . addImm ( - 1 ) ; } TII -> loadRegFromStackSlot ( MBB , MBBI , Reg . VGPR , Reg . FI . getValue ( ) , & AMDGPU :: VGPR_32RegClass , & TII -> getRegisterInfo ( ) ) ; } if ( ScratchExecCopy != AMDGPU :: NoRegister ) { BuildMI ( MBB , MBBI , DL , TII -> get ( AMDGPU :: S_MOV_B64 ) , AMDGPU :: EXEC ) . addReg ( ScratchExecCopy ) ; } unsigned StackPtrReg = FuncInfo -> getStackPtrOffsetReg ( ) ; if ( StackPtrReg == AMDGPU :: NoRegister ) return ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; uint32_t NumBytes = MFI . getStackSize ( ) ; if ( NumBytes != 0 && hasSP ( MF ) ) { uint32_t RoundedSize = FuncInfo -> isStackRealigned ( ) ? NumBytes + MFI . getMaxAlignment ( ) : NumBytes ; BuildMI ( MBB , MBBI , DL , TII -> get ( AMDGPU :: S_SUB_U32 ) , StackPtrReg ) . addReg ( StackPtrReg ) . addImm ( RoundedSize * ST . getWavefrontSize ( ) ) ; } } </s>


<s> std :: pair < unsigned , const TargetRegisterClass * > AArch64TargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & AArch64 :: GPR64commonRegClass ) ; return std :: make_pair ( 0U , & AArch64 :: GPR32commonRegClass ) ; case 'w' : if ( VT . getSizeInBits ( ) == 16 ) return std :: make_pair ( 0U , & AArch64 :: FPR16RegClass ) ; if ( VT . getSizeInBits ( ) == 32 ) return std :: make_pair ( 0U , & AArch64 :: FPR32RegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & AArch64 :: FPR64RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & AArch64 :: FPR128RegClass ) ; break ; case 'x' : if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & AArch64 :: FPR128_loRegClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( AArch64 :: NZCV ) , & AArch64 :: CCRRegClass ) ; std :: pair < unsigned , const TargetRegisterClass * > Res ; Res = TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; if ( ! Res . second ) { unsigned Size = Constraint . size ( ) ; if ( ( Size == 4 || Size == 5 ) && Constraint [ 0 ] == '{' && tolower ( Constraint [ 1 ] ) == 'v' && Constraint [ Size - 1 ] == '}' ) { int RegNo ; bool Failed = Constraint . slice ( 2 , Size - 1 ) . getAsInteger ( 10 , RegNo ) ; if ( ! Failed && RegNo >= 0 && RegNo <= 31 ) { if ( VT != MVT :: Other && VT . getSizeInBits ( ) == 64 ) { Res . first = AArch64 :: FPR64RegClass . getRegister ( RegNo ) ; Res . second = & AArch64 :: FPR64RegClass ; } else { Res . first = AArch64 :: FPR128RegClass . getRegister ( RegNo ) ; Res . second = & AArch64 :: FPR128RegClass ; } } } } return Res ; } </s>

Given a physical register constraint ( e.g .


<s> MVT X86TargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT == MVT :: v32i1 && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return MVT :: v32i8 ; if ( ( VT == MVT :: v32i16 || VT == MVT :: v64i8 ) && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) && ! EnableOldKNLABI ) return MVT :: v16i32 ; return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


"\nStack information for function %s:\n"

Print the information about the frv stack offsets , etc . when debugging .


<s> SDNode * MipsDAGToDAGISel :: getGlobalBaseReg ( ) { Register GlobalBaseReg = MF -> getInfo < MipsFunctionInfo > ( ) -> getGlobalBaseReg ( * MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , getTargetLowering ( ) -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"X86 Atom pad short functions"
;
}
</s>


<s> bool loongarch_base_index_address_p ( rtx x , machine_mode mode ) { struct loongarch_address_info addr ; return ( loongarch_classify_address ( & addr , x , mode , false ) && addr . type == ADDRESS_REG_REG && REG_P ( addr . offset ) ) ; } </s>

Return true if X is a legitimate address with base and index . MODE is the mode of the value being accessed .


<s> EVT AArch64TargetLowering :: getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const { bool CanImplicitFloat = ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; bool CanUseNEON = Subtarget -> hasNEON ( ) && CanImplicitFloat ; bool CanUseFP = Subtarget -> hasFPARMv8 ( ) && CanImplicitFloat ; bool IsSmallMemset = Op . isMemset ( ) && Op . size ( ) < 32 ; auto AlignmentIsAcceptable = [ & ] ( EVT VT , Align AlignCheck ) { if ( Op . isAligned ( AlignCheck ) ) return true ; bool Fast ; return allowsMisalignedMemoryAccesses ( VT , 0 , Align ( 1 ) , MachineMemOperand :: MONone , & Fast ) && Fast ; } ; if ( CanUseNEON && Op . isMemset ( ) && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: v2i64 , Align ( 16 ) ) ) return MVT :: v2i64 ; if ( CanUseFP && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: f128 , Align ( 16 ) ) ) return MVT :: f128 ; if ( Op . size ( ) >= 8 && AlignmentIsAcceptable ( MVT :: i64 , Align ( 8 ) ) ) return MVT :: i64 ; if ( Op . size ( ) >= 4 && AlignmentIsAcceptable ( MVT :: i32 , Align ( 4 ) ) ) return MVT :: i32 ; return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> static void register_builtin_type ( vector_type_index type , tree eltype , machine_mode mode ) { builtin_types [ type ] . scalar = eltype ; builtin_types [ type ] . scalar_ptr = build_pointer_type ( eltype ) ; builtin_types [ type ] . scalar_const_ptr = build_const_pointer ( eltype ) ; if ( ! riscv_v_ext_vector_mode_p ( mode ) ) return ; tree vectype = build_vector_type_for_mode ( eltype , mode ) ; gcc_assert ( VECTOR_MODE_P ( TYPE_MODE ( vectype ) ) && TYPE_MODE ( vectype ) == mode && TYPE_MODE_RAW ( vectype ) == mode && TYPE_ALIGN ( vectype ) <= 128 && known_eq ( tree_to_poly_uint64 ( TYPE_SIZE ( vectype ) ) , GET_MODE_BITSIZE ( mode ) ) ) ; vectype = build_distinct_type_copy ( vectype ) ; gcc_assert ( vectype == TYPE_MAIN_VARIANT ( vectype ) ) ; SET_TYPE_STRUCTURAL_EQUALITY ( vectype ) ; TYPE_ARTIFICIAL ( vectype ) = 1 ; TYPE_INDIVISIBLE_P ( vectype ) = 1 ; add_vector_type_attribute ( vectype , vector_types [ type ] . mangled_name ) ; make_type_sizeless ( vectype ) ; abi_vector_types [ type ] = vectype ; lang_hooks . types . register_builtin_type ( vectype , vector_types [ type ] . abi_name ) ; } </s>

Helper function for register a single built-in RVV ABI type .


<s> void HexagonFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { auto & HST = static_cast < const HexagonSubtarget & > ( MF . getSubtarget ( ) ) ; auto & HRI = * HST . getRegisterInfo ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; MachineBasicBlock * PrologB = & MF . front ( ) , * EpilogB = nullptr ; if ( EnableShrinkWrapping ) findShrunkPrologEpilog ( MF , PrologB , EpilogB ) ; bool PrologueStubs = false ; insertCSRSpillsInBlock ( * PrologB , CSI , HRI , PrologueStubs ) ; insertPrologueInBlock ( * PrologB , PrologueStubs ) ; if ( EpilogB ) { insertCSRRestoresInBlock ( * EpilogB , CSI , HRI ) ; insertEpilogueInBlock ( * EpilogB ) ; } else { for ( auto & B : MF ) if ( B . isReturnBlock ( ) ) insertCSRRestoresInBlock ( B , CSI , HRI ) ; for ( auto & B : MF ) if ( B . isReturnBlock ( ) ) insertEpilogueInBlock ( B ) ; for ( auto & B : MF ) { if ( B . empty ( ) ) continue ; MachineInstr * RetI = getReturn ( B ) ; if ( ! RetI || isRestoreCall ( RetI -> getOpcode ( ) ) ) continue ; for ( auto & R : CSI ) RetI -> addOperand ( MachineOperand :: CreateReg ( R . getReg ( ) , false , true ) ) ; } } if ( EpilogB ) { unsigned MaxBN = 0 ; for ( auto & B : MF ) if ( B . getNumber ( ) >= 0 ) MaxBN = std :: max ( MaxBN , unsigned ( B . getNumber ( ) ) ) ; BitVector DoneT ( MaxBN + 1 ) , DoneF ( MaxBN + 1 ) , Path ( MaxBN + 1 ) ; updateExitPaths ( * EpilogB , EpilogB , DoneT , DoneF , Path ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> rtx rs6000_got_register ( rtx value ATTRIBUTE_UNUSED ) { if ( no_new_pseudos && ! regs_ever_live [ RS6000_PIC_OFFSET_TABLE_REGNUM ] ) regs_ever_live [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = 1 ; current_function_uses_pic_offset_table = 1 ; return pic_offset_table_rtx ; } </s>


<s> static void visium_setup_incoming_varargs ( cumulative_args_t pcum_v , machine_mode mode , tree type , int * pretend_size ATTRIBUTE_UNUSED , int no_rtl ) { cumulative_args_t local_args_so_far ; CUMULATIVE_ARGS local_copy ; CUMULATIVE_ARGS * locargs ; int gp_saved , fp_saved , size ; local_args_so_far . p = & local_copy ; locargs = get_cumulative_args ( pcum_v ) ; local_args_so_far . magic = CUMULATIVE_ARGS_MAGIC ; local_copy . grcount = locargs -> grcount ; local_copy . frcount = locargs -> frcount ; local_copy . stack_words = locargs -> stack_words ; TARGET_FUNCTION_ARG_ADVANCE ( local_args_so_far , mode , type , 1 ) ; locargs = get_cumulative_args ( local_args_so_far ) ; gp_saved = MAX_ARGS_IN_GP_REGISTERS - locargs -> grcount ; fp_saved = ( TARGET_FPU ? MAX_ARGS_IN_FP_REGISTERS - locargs -> frcount : 0 ) ; size = ( gp_saved * UNITS_PER_WORD ) + ( fp_saved * UNITS_PER_HWFPVALUE ) ; if ( ! no_rtl && size > 0 ) { rtx ptr = force_reg ( Pmode , plus_constant ( Pmode , virtual_incoming_args_rtx , - size ) ) ; if ( gp_saved > 0 ) { rtx mem = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , ptr , fp_saved * UNITS_PER_HWFPVALUE ) ) ; MEM_NOTRAP_P ( mem ) = 1 ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( locargs -> grcount + GP_ARG_FIRST , mem , gp_saved ) ; } if ( fp_saved > 0 ) { rtx mem = gen_rtx_MEM ( BLKmode , ptr ) ; MEM_NOTRAP_P ( mem ) = 1 ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; gcc_assert ( UNITS_PER_WORD == UNITS_PER_HWFPVALUE ) ; move_block_from_reg ( locargs -> frcount + FP_ARG_FIRST , mem , fp_saved ) ; } } visium_reg_parm_save_area_size = size ; } </s>

Store the anonymous register arguments into the stack so that all the arguments appear to have been passed consecutively on the stack .


<s> bool AMDGPUTargetLowering :: isLoadBitCastBeneficial ( EVT LoadTy , EVT CastTy ) const { if ( LoadTy . getSizeInBits ( ) != CastTy . getSizeInBits ( ) ) return true ; unsigned LScalarSize = LoadTy . getScalarType ( ) . getSizeInBits ( ) ; unsigned CastScalarSize = CastTy . getScalarType ( ) . getSizeInBits ( ) ; return ( ( LScalarSize <= CastScalarSize ) || ( CastScalarSize >= 32 ) || ( LScalarSize < 32 ) ) ; } </s>

Return true if the following transform is beneficial : fold ( conv ( load x ) ) - > ( load ( conv * ) x ) On architectures that do n't natively support some vector loads efficiently , casting the load to a smaller vector of larger types and loading is more efficient , however , this can be undone by optimizations in dag combiner .


<s> TargetLowering :: ConstraintWeight MBlazeTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'd' : case 'y' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


"Unknown architecture specific memory model"

"HLE_ACQUIRE not used with ACQUIRE or stronger memory model"

"HLE_RELEASE not used with RELEASE or stronger memory model"

Validate target specific memory model bits in VAL .


<s>
void
HexagonInstPrinter
::
printSymbol
(
MCInst
const
*
MI
,
unsigned
OpNo
,
raw_ostream
&
O
,
bool
hi
)
const
{
MCOperand
const
&
MO
=
MI
->
getOperand
(
OpNo
)
;
O
<<
'#'
<<
(
hi
"HI"
:
"LO"
)
<<
'('
;
if
(
MO
.
isImm
(
)
)
{
O
<<
'#'
;
printOperand
(
MI
,
OpNo
,
O
)
;
}
else
{
printOperand
(
MI
,
OpNo
,
O
)
;
assert
(
"Unknown symbol operand"
)
;
}
O
<<
')'
;
}
</s>

Hexagon
Hexagon
"HI"
"LO"
"Unknown symbol operand"


<s> static bool pa_can_eliminate ( const int from , const int to ) { if ( TARGET_64BIT && from == ARG_POINTER_REGNUM ) return false ; return ( from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true ) ; } </s>

Given FROM and TO register numbers , say whether this elimination is allowed . Frame pointer elimination is automatically handled .


"Unknown opcode to check as cheap as a move!"

Return true if the instruction is as cheap as a move instruction .


"unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, and 8000\n"

"unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n"

"PIC code generation is not supported in the portable runtime model\n"

"PIC code generation is not compatible with fast indirect calls\n"

"-g is only supported when using GAS on this processor,"

Set global variables as needed for the options enabled .


<s> unsigned MipsInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( ( MI -> getOpcode ( ) == Mips :: SW ) || ( MI -> getOpcode ( ) == Mips :: SWC1 ) || ( MI -> getOpcode ( ) == Mips :: SDC1 ) ) { if ( ( MI -> getOperand ( 2 ) . isFI ( ) ) && ( MI -> getOperand ( 1 ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( 1 ) ) ) ) { FrameIndex = MI -> getOperand ( 2 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> void RISCVELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; } </s>

This method must be called before any actual lowering is done .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static rtx alpha_emit_set_const ( rtx target , machine_mode mode , HOST_WIDE_INT c , int n , bool no_output ) { machine_mode orig_mode = mode ; rtx orig_target = target ; rtx result = 0 ; int i ; if ( ! can_create_pseudo_p ( ) && mode == SImode && REG_P ( target ) && REGNO ( target ) < FIRST_PSEUDO_REGISTER ) { result = alpha_emit_set_const_1 ( target , mode , c , 1 , no_output ) ; if ( result ) return result ; target = no_output ? NULL : gen_lowpart ( DImode , target ) ; mode = DImode ; } else if ( mode == V8QImode || mode == V4HImode || mode == V2SImode ) { target = no_output ? NULL : gen_lowpart ( DImode , target ) ; mode = DImode ; } for ( i = 1 ; i <= n ; i ++ ) { result = alpha_emit_set_const_1 ( target , mode , c , i , no_output ) ; if ( result ) { rtx_insn * insn ; rtx set ; if ( no_output ) return result ; insn = get_last_insn ( ) ; set = single_set ( insn ) ; if ( ! CONSTANT_P ( SET_SRC ( set ) ) ) set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , GEN_INT ( c ) ) ; break ; } } if ( result ) { if ( result == target ) result = orig_target ; else if ( mode != orig_mode ) result = gen_lowpart ( orig_mode , result ) ; } return result ; } </s>

Try to output insns to set TARGET equal to the constant C if it can be done in less than N insns . Do all computations in MODE . Returns the place where the output has been placed if it can be done and the insns have been emitted . If it would take more than N insns , zero is returned and no insns and emitted .


<s> static int s390_check_qrst_address ( char c , rtx op , bool lit_pool_ok ) { rtx symref ; struct s390_address addr ; bool decomposed = false ; if ( ! address_operand ( op , GET_MODE ( op ) ) ) return 0 ; if ( s390_loadrelative_operand_p ( op , & symref , NULL ) && ( ! lit_pool_ok || ! SYMBOL_REF_P ( symref ) || ! CONSTANT_POOL_ADDRESS_P ( symref ) ) ) return 0 ; if ( ! lit_pool_ok ) { if ( ! s390_decompose_address ( op , & addr ) ) return 0 ; if ( addr . literal_pool ) return 0 ; decomposed = true ; } if ( lra_in_progress || reload_completed ) { if ( ! decomposed && ! s390_decompose_address ( op , & addr ) ) return 0 ; decomposed = true ; } switch ( c ) { case 'Q' : if ( ! decomposed && ! s390_decompose_address ( op , & addr ) ) return 0 ; if ( addr . indx ) return 0 ; if ( ! s390_short_displacement ( addr . disp ) ) return 0 ; break ; case 'R' : if ( TARGET_LONG_DISPLACEMENT ) { if ( ! decomposed && ! s390_decompose_address ( op , & addr ) ) return 0 ; if ( ! s390_short_displacement ( addr . disp ) ) return 0 ; } break ; case 'S' : if ( ! decomposed && ! s390_decompose_address ( op , & addr ) ) return 0 ; if ( addr . indx ) return 0 ; break ; case 'T' : break ; default : return 0 ; } return 1 ; } </s>

Return true if the address in OP is valid for constraint letter C if wrapped in a MEM rtx . Set LIT_POOL_OK to true if it literal pool MEMs should be accepted . Only the Q , R , S , T constraint letters are allowed for C .


<s> unsigned AArch64InstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case AArch64 :: LDRWui : case AArch64 :: LDRXui : case AArch64 :: LDRBui : case AArch64 :: LDRHui : case AArch64 :: LDRSui : case AArch64 :: LDRDui : case AArch64 :: LDRQui : if ( MI . getOperand ( 0 ) . getSubReg ( ) == 0 && MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> bool mips_9bit_offset_address_p ( rtx x , machine_mode mode ) { struct mips_address_info addr ; return ( mips_classify_address ( & addr , x , mode , false ) && addr . type == ADDRESS_REG && CONST_INT_P ( addr . offset ) && MIPS_9BIT_OFFSET_P ( INTVAL ( addr . offset ) ) ) ; } </s>

Return true if X is a legitimate address with a 9-bit offset . MODE is the mode of the value being accessed .


<s>
unsigned
MSP430InstrInfo
::
getInstSizeInBytes
(
const
MachineInstr
&
MI
)
const
{
const
MCInstrDesc
&
Desc
=
MI
.
getDesc
(
)
;
switch
(
Desc
.
TSFlags
&
MSP430II
::
SizeMask
)
{
default
:
switch
(
Desc
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown instruction size!"
)
;
case
TargetOpcode
::
CFI_INSTRUCTION
:
case
TargetOpcode
::
EH_LABEL
:
case
TargetOpcode
::
IMPLICIT_DEF
:
case
TargetOpcode
::
KILL
:
case
TargetOpcode
::
DBG_VALUE
:
return
0
;
case
TargetOpcode
::
INLINEASM
:
{
const
MachineFunction
*
MF
=
MI
.
getParent
(
)
->
getParent
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
->
getSubtarget
(
)
.
getInstrInfo
(
)
;
return
TII
.
getInlineAsmLength
(
MI
.
getOperand
(
0
)
.
getSymbolName
(
)
,
*
MF
->
getTarget
(
)
.
getMCAsmInfo
(
)
)
;
}
}
case
MSP430II
::
SizeSpecial
:
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown instruction size!"
)
;
case
MSP430
::
SAR8r1c
:
case
MSP430
::
SAR16r1c
:
return
4
;
}
case
MSP430II
::
Size2Bytes
:
return
2
;
case
MSP430II
::
Size4Bytes
:
return
4
;
case
MSP430II
::
Size6Bytes
:
return
6
;
}
}
</s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> std :: pair < unsigned , const TargetRegisterClass * > WebAssemblyTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , & WebAssembly :: I32RegClass ) ; default : break ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s>
int
PPCTTIImpl
::
getArithmeticInstrCost
(
unsigned
Opcode
,
Type
*
Ty
,
TTI
::
TargetCostKind
CostKind
,
TTI
::
OperandValueKind
Op1Info
,
TTI
::
OperandValueKind
Op2Info
,
TTI
::
OperandValueProperties
Opd1PropInfo
,
TTI
::
OperandValueProperties
Opd2PropInfo
,
ArrayRef
<
const
Value
*
>
Args
,
const
Instruction
*
CxtI
)
{
assert
(
TLI
->
InstructionOpcodeToISD
(
Opcode
)
&&
"Invalid opcode"
)
;
int
Cost
=
BaseT
::
getArithmeticInstrCost
(
Opcode
,
Ty
,
CostKind
,
Op1Info
,
Op2Info
,
Opd1PropInfo
,
Opd2PropInfo
)
;
return
vectorCostAdjustment
(
Cost
,
Opcode
,
Ty
,
nullptr
)
;
}
</s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> void X86PreTileConfig :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesAll ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s>
SDValue
X86TargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
bool
Is64Bit
=
Subtarget
.
is64Bit
(
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_X86
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
CopyVT
=
VA
.
getLocVT
(
)
;
if
(
(
CopyVT
==
MVT
::
f32
||
CopyVT
==
MVT
::
f64
||
CopyVT
==
MVT
::
f128
)
&&
(
(
Is64Bit
||
Ins
[
i
]
.
Flags
.
isInReg
(
)
)
&&
!
Subtarget
.
hasSSE1
(
)
)
)
{
report_fatal_error
(
"SSE register return with SSE disabled"
)
;
}
bool
RoundAfterCopy
=
false
;
if
(
(
VA
.
getLocReg
(
)
==
X86
::
FP0
||
VA
.
getLocReg
(
)
==
X86
::
FP1
)
&&
isScalarFPTypeInSSEReg
(
VA
.
getValVT
(
)
)
)
{
if
(
!
Subtarget
.
hasX87
(
)
)
report_fatal_error
(
"X87 register return with X87 disabled"
)
;
CopyVT
=
MVT
::
f80
;
RoundAfterCopy
=
(
CopyVT
!=
VA
.
getLocVT
(
)
)
;
}
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
CopyVT
,
InFlag
)
.
getValue
(
1
)
;
SDValue
Val
=
Chain
.
getValue
(
0
)
;
if
(
RoundAfterCopy
)
Val
=
DAG
.
getNode
(
ISD
::
FP_ROUND
,
dl
,
VA
.
getValVT
(
)
,
Val
,
DAG
.
getIntPtrConstant
(
1
,
dl
)
)
;
if
(
VA
.
isExtInLoc
(
)
&&
VA
.
getValVT
(
)
.
getScalarType
(
)
==
MVT
::
i1
)
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
InFlag
=
Chain
.
getValue
(
2
)
;
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> void alpha_split_atomic_op ( enum rtx_code code , rtx mem , rtx val , rtx before , rtx after , rtx scratch , enum memmodel model ) { machine_mode mode = GET_MODE ( mem ) ; rtx label , x , cond = gen_rtx_REG ( DImode , REGNO ( scratch ) ) ; alpha_pre_atomic_barrier ( model ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; label = gen_rtx_LABEL_REF ( DImode , label ) ; if ( before == NULL ) before = scratch ; emit_load_locked ( mode , before , mem ) ; if ( code == NOT ) { x = gen_rtx_AND ( mode , before , val ) ; emit_insn ( gen_rtx_SET ( VOIDmode , val , x ) ) ; x = gen_rtx_NOT ( mode , val ) ; } else x = gen_rtx_fmt_ee ( code , mode , before , val ) ; if ( after ) emit_insn ( gen_rtx_SET ( VOIDmode , after , copy_rtx ( x ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , scratch , x ) ) ; emit_store_conditional ( mode , cond , mem , scratch ) ; x = gen_rtx_EQ ( DImode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label ) ; alpha_post_atomic_barrier ( model ) ; } </s>

Expand an an atomic fetch-and-operate pattern . CODE is the binary operation to perform . MEM is the memory on which to operate . VAL is the second operand of the binary operator . BEFORE and AFTER are optional locations to return the value of MEM either before of after the operation . SCRATCH is a scratch register .


<s> static std :: unique_ptr < AArch64Operand > CreateReg ( unsigned RegNum , RegKind Kind , unsigned ElementWidth , SMLoc S , SMLoc E , MCContext & Ctx ) { auto Op = make_unique < AArch64Operand > ( k_Register , Ctx ) ; Op -> Reg . RegNum = RegNum ; Op -> Reg . ElementWidth = ElementWidth ; Op -> Reg . Kind = Kind ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> unsigned SNESInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { case SNES :: STDPtrQRr : case SNES :: STDWPtrQRr : { if ( MI . getOperand ( 0 ) . isFI ( ) && MI . getOperand ( 1 ) . isImm ( ) && MI . getOperand ( 1 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 0 ) . getIndex ( ) ; return MI . getOperand ( 2 ) . getReg ( ) ; } break ; } default : break ; } return 0 ; } </s>


<s> void WebAssemblyFrameLowering :: writeSPToGlobal ( unsigned SrcReg , MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & InsertStore , const DebugLoc & DL ) const { const auto * TII = MF . getSubtarget < WebAssemblySubtarget > ( ) . getInstrInfo ( ) ; const char * ES = "__stack_pointer" ; auto * SPSymbol = MF . createExternalSymbolName ( ES ) ; BuildMI ( MBB , InsertStore , DL , TII -> get ( WebAssembly :: GLOBAL_SET_I32 ) ) . addExternalSymbol ( SPSymbol ) . addReg ( SrcReg ) ; } </s>

Write SP back to __stack_pointer global .


<s> static void register_builtin_types ( ) { tree int8_type_node = get_typenode_from_name ( INT8_TYPE ) ; tree uint8_type_node = get_typenode_from_name ( UINT8_TYPE ) ; tree int16_type_node = get_typenode_from_name ( INT16_TYPE ) ; tree int32_type_node = get_typenode_from_name ( INT32_TYPE ) ; tree int64_type_node = get_typenode_from_name ( INT64_TYPE ) ; machine_mode mode ; VECTOR_MODE_MIN_VLEN_32 , ARGS ... ) \ mode = TARGET_MIN_VLEN > 32 ? VECTOR_MODE ## mode \ : VECTOR_MODE_MIN_VLEN_32 ## mode ; \ register_builtin_type ( VECTOR_TYPE_ ## NAME , SCALAR_TYPE ## _type_node , mode ) ; } </s>

Register the built-in RVV ABI types , such as __rvv_int32m1_t .


<s> Candidate ( SUnit * SU_ ) : SU ( SU_ ) { } </s>


"Loop must have more than one incoming edge!"

Check to see if the loop has a canonical induction variable : an integer recurrence that starts at 0 and increments by one each time through the loop .


<s> bool PPCFastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Load : return SelectLoad ( I ) ; case Instruction :: Store : return SelectStore ( I ) ; case Instruction :: Br : return SelectBranch ( I ) ; case Instruction :: IndirectBr : return SelectIndirectBr ( I ) ; case Instruction :: FPExt : return SelectFPExt ( I ) ; case Instruction :: FPTrunc : return SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return SelectIToFP ( I , true ) ; case Instruction :: UIToFP : return SelectIToFP ( I , false ) ; case Instruction :: FPToSI : return SelectFPToI ( I , true ) ; case Instruction :: FPToUI : return SelectFPToI ( I , false ) ; case Instruction :: Add : return SelectBinaryIntOp ( I , ISD :: ADD ) ; case Instruction :: Or : return SelectBinaryIntOp ( I , ISD :: OR ) ; case Instruction :: Sub : return SelectBinaryIntOp ( I , ISD :: SUB ) ; case Instruction :: Call : if ( dyn_cast < IntrinsicInst > ( I ) ) return false ; return SelectCall ( I ) ; case Instruction :: Ret : return SelectRet ( I ) ; case Instruction :: Trunc : return SelectTrunc ( I ) ; case Instruction :: ZExt : case Instruction :: SExt : return SelectIntExt ( I ) ; default : break ; } return false ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> MCObjectWriter * OR1KAsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( OSType ) ; return createOR1KELFObjectWriter ( OS , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> enum reg_class nds32_regno_reg_class ( int regno ) { if ( regno >= 0 && regno <= 7 ) return LOW_REGS ; else if ( regno >= 8 && regno <= 11 ) return MIDDLE_REGS ; else if ( regno >= 12 && regno <= 14 ) return HIGH_REGS ; else if ( regno == 15 ) return R15_TA_REG ; else if ( regno >= 16 && regno <= 19 ) return MIDDLE_REGS ; else if ( regno >= 20 && regno <= 31 ) return HIGH_REGS ; else if ( regno == 32 || regno == 33 ) return FRAME_REGS ; else return NO_REGS ; } </s>


<s> static bool shadow_type_p ( enum attr_type type ) { return ( type == TYPE_SHADOW || type == TYPE_LOAD_SHADOW || type == TYPE_MULT_SHADOW ) ; } </s>

Return true iff TYPE is one of the shadow types .


<s> void AArch64AsmPrinter :: emitEndOfAsmFile ( Module & M ) { emitHwasanMemaccessSymbols ( M ) ; const Triple & TT = TM . getTargetTriple ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; auto Stubs = MMIMacho . getAuthGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( OutContext . getMachOSection ( "__DATA" , "__auth_ptr" , MachO :: S_REGULAR , SectionKind :: getMetadata ( ) ) ) ; emitAlignment ( Align ( 8 ) ) ; for ( auto & Stub : Stubs ) emitAuthenticatedPointer ( * OutStreamer , Stub . first , Stub . second ) ; OutStreamer -> AddBlankLine ( ) ; } OutStreamer -> emitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } emitStackMaps ( SM ) ; FM . serializeToFaultMapSection ( ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> bool X86InstrInfo :: classifyLEAReg ( MachineInstr * MI , const MachineOperand & Src , unsigned Opc , bool AllowSP , unsigned & NewSrc , bool & isKill , bool & isUndef , MachineOperand & ImplicitOp ) const { MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetRegisterClass * RC ; if ( AllowSP ) { RC = Opc != X86 :: LEA32r ? & X86 :: GR64RegClass : & X86 :: GR32RegClass ; } else { RC = Opc != X86 :: LEA32r ? & X86 :: GR64_NOSPRegClass : & X86 :: GR32_NOSPRegClass ; } unsigned SrcReg = Src . getReg ( ) ; if ( Opc != X86 :: LEA64_32r ) { NewSrc = SrcReg ; isKill = Src . isKill ( ) ; isUndef = Src . isUndef ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( NewSrc ) && ! MF . getRegInfo ( ) . constrainRegClass ( NewSrc , RC ) ) return false ; return true ; } if ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) ) { ImplicitOp = Src ; ImplicitOp . setImplicit ( ) ; NewSrc = getX86SubSuperRegister ( Src . getReg ( ) , 64 ) ; MachineBasicBlock :: LivenessQueryResult LQR = MI -> getParent ( ) -> computeRegisterLiveness ( & getRegisterInfo ( ) , NewSrc , MI ) ; switch ( LQR ) { case MachineBasicBlock :: LQR_Unknown : return false ; case MachineBasicBlock :: LQR_Live : isKill = MI -> killsRegister ( SrcReg ) ; isUndef = false ; break ; default : isKill = false ; isUndef = true ; break ; } } else { NewSrc = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( NewSrc , RegState :: Define | RegState :: Undef , X86 :: sub_32bit ) . addOperand ( Src ) ; isKill = true ; isUndef = false ; } return true ; } </s>

Given an operand within a MachineInstr , insert preceding code to put it into the right format for a particular kind of LEA instruction .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < HexagonSubtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> rtx gen_compare_reg ( enum rtx_code code , rtx x , rtx y ) { enum machine_mode mode = SELECT_CC_MODE ( code , x , y ) ; rtx cc_reg ; if ( sparc_compare_emitted != NULL_RTX ) { cc_reg = sparc_compare_emitted ; sparc_compare_emitted = NULL_RTX ; return cc_reg ; } if ( TARGET_V9 && GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) { int reg ; static int next_fcc_reg = 0 ; static rtx prev_args [ 4 ] [ 2 ] ; for ( reg = 0 ; reg < 4 ; reg ++ ) if ( prev_args [ reg ] [ 0 ] == x && prev_args [ reg ] [ 1 ] == y ) break ; if ( reg == 4 ) { reg = next_fcc_reg ; prev_args [ reg ] [ 0 ] = x ; prev_args [ reg ] [ 1 ] = y ; next_fcc_reg = ( next_fcc_reg + 1 ) & 3 ; } cc_reg = gen_rtx_REG ( mode , reg + SPARC_FIRST_V9_FCC_REG ) ; } cc_reg = gen_reg_rtx ( mode ) ; else if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) cc_reg = gen_rtx_REG ( mode , SPARC_FCC_REG ) ; else cc_reg = gen_rtx_REG ( mode , SPARC_ICC_REG ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cc_reg , gen_rtx_COMPARE ( mode , x , y ) ) ) ; return cc_reg ; } </s>

Emit the compare insn and return the CC reg for the comparison in CMP .


<s> unsigned AVRInstrInfo :: getInstSizeInBytes ( const MachineInstr * MI ) const { unsigned Opcode = MI -> getOpcode ( ) ; switch ( Opcode ) { default : { const MCInstrDesc & Desc = get ( Opcode ) ; return Desc . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return 0 ; case TargetOpcode :: INLINEASM : { const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const AVRTargetMachine & TM = static_cast < const AVRTargetMachine & > ( MF -> getTarget ( ) ) ; const TargetInstrInfo & TII = * TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ; return TII . getInlineAsmLength ( MI -> getOperand ( 0 ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } } } </s>


<s> static int scavenge_reg ( HARD_REG_SET * s ) { int r ; for ( r = FIRST_GENERAL_REG ; r <= LAST_GENERAL_REG ; r ++ ) if ( TEST_HARD_REG_BIT ( * s , r ) ) return r ; return - 1 ; } </s>

Find the number of a general purpose register in S .


"Instr doesn't have FrameIndex operand!"

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


Return true if FNDECL contains calls to vector-partitionable routines .


<s> virtual const XNCMInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> static int avr_regs_to_save ( HARD_REG_SET * set ) { int count ; int int_or_sig_p = cfun -> machine -> is_interrupt || cfun -> machine -> is_signal ; if ( set ) CLEAR_HARD_REG_SET ( * set ) ; count = 0 ; if ( TREE_THIS_VOLATILE ( current_function_decl ) || cfun -> machine -> is_OS_task || cfun -> machine -> is_OS_main ) return 0 ; for ( int reg = 0 ; reg < 32 ; reg ++ ) { if ( fixed_regs [ reg ] ) continue ; if ( ( int_or_sig_p && ! crtl -> is_leaf && call_used_or_fixed_reg_p ( reg ) ) || ( df_regs_ever_live_p ( reg ) && ( int_or_sig_p || ! call_used_or_fixed_reg_p ( reg ) ) && ! ( frame_pointer_needed && ( reg == REG_Y || reg == REG_Y + 1 ) ) ) ) { if ( set ) SET_HARD_REG_BIT ( * set , reg ) ; count ++ ; } } return count ; } </s>

Return the number of hard registers to push/pop in the prologue/epilogue of the current function , and optionally store these registers in SET .


<s>
MachineBasicBlock
*
TL45TargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unexpected instr type to insert"
)
;
case
TL45
::
Select_GRRegs_Using_CC_GRRegs
:
return
emitSelectPseudo
(
MI
,
BB
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> EVT MipsTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , const AttributeList & FuncAttributes ) const { if ( Subtarget . hasMips64 ( ) ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> bool SNESAsmParser :: emit ( MCInst & Inst , SMLoc const & Loc , MCStreamer & Out ) const { Inst . setLoc ( Loc ) ; Out . EmitInstruction ( Inst , STI ) ; return false ; } </s>

Output the remark via the diagnostic handler and to the optimization record file .


<s> const TargetRegisterClass * Thumb1RegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC ) const { if ( ARM :: tGPRRegClass . hasSubClassEq ( RC ) ) return ARM :: tGPRRegisterClass ; return ARMBaseRegisterInfo :: getLargestLegalSuperClass ( RC ) ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .

ARM ARM::tGPRRegClass ARM::tGPRRegisterClass ARM


<s> SDValue AVRTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; if ( CallConv == CallingConv :: AVR_BUILTIN ) { CCInfo . AnalyzeCallResult ( Ins , RetCC_AVR_BUILTIN ) ; } else { analyzeReturnValues ( Ins , CCInfo , Subtarget . hasTinyEncoding ( ) ) ; } for ( CCValAssign const & RVLoc : RVLocs ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLoc . getLocReg ( ) , RVLoc . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> bool X86PassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( getOptLevel ( ) ) ) ; return false ; } </s>

This method should install a ( global ) instruction selector pass , which converts possibly generic instructions to fully target-specific instructions , thereby constraining all generic virtual registers to register classes .


<s> int initial_elimination_offset ( int from , int to ) { const int regs_saved_rounding = 0 ; int save_flags = target_flags ; HARD_REG_SET live_regs_mask ; int regs_saved = calc_live_regs ( & live_regs_mask ) ; int total_auto_space = rounded_frame_size ( regs_saved ) - regs_saved_rounding ; target_flags = save_flags ; int total_saved_regs_space = regs_saved + regs_saved_rounding ; if ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) return total_saved_regs_space + total_auto_space ; if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) return total_saved_regs_space + total_auto_space ; if ( from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) return 0 ; if ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) return rounded_frame_size ( 0 ) ; if ( from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) return rounded_frame_size ( 0 ) ; gcc_assert ( from == RETURN_ADDRESS_POINTER_REGNUM && ( to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM ) ) ; return total_auto_space ; } </s>

Define the offset between two registers , one to be eliminated , and the other its replacement , at the start of a routine .


<s> bool AVRRegisterInfo :: shouldCoalesce ( MachineInstr * MI , const TargetRegisterClass * SrcRC , unsigned SubReg , const TargetRegisterClass * DstRC , unsigned DstSubReg , const TargetRegisterClass * NewRC , LiveIntervals & LIS ) const { if ( this -> getRegClass ( AVR :: PTRDISPREGSRegClassID ) -> hasSubClassEq ( NewRC ) ) { return false ; } return TargetRegisterInfo :: shouldCoalesce ( MI , SrcRC , SubReg , DstRC , DstSubReg , NewRC , LIS ) ; } </s>


<s> static hashval_t hash ( tree t ) { return htab_hash_pointer ( t ) ; } </s>

Hash function for builtin functions with up to 3 arguments and a return type .


"SVE requires vector length in multiples of 128!"

"Minimum SVE vector size should not be larger than its maximum!"

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
void
XCoreAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
SmallString
<
128
>
Str
;
raw_svector_ostream
O
(
Str
)
;
unsigned
src
,
dst
,
srcSR
,
dstSR
;
if
(
TM
.
getInstrInfo
(
)
->
isMoveInstr
(
*
MI
,
src
,
dst
,
srcSR
,
dstSR
)
)
{
O
<<
"\tmov "
<<
getRegisterName
(
dst
)
<<
", "
;
O
<<
getRegisterName
(
src
)
;
}
else
{
printInstruction
(
MI
,
O
)
;
}
OutStreamer
.
EmitRawText
(
O
.
str
(
)
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> int loongarch_address_insns ( rtx x , machine_mode mode , bool might_split_p ) { struct loongarch_address_info addr ; int factor ; if ( ! loongarch_classify_address ( & addr , x , mode , false ) ) return 0 ; if ( mode != BLKmode && might_split_p ) factor = ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; else factor = 1 ; if ( loongarch_classify_address ( & addr , x , mode , false ) ) switch ( addr . type ) { case ADDRESS_REG : case ADDRESS_REG_REG : case ADDRESS_CONST_INT : return factor ; case ADDRESS_LO_SUM : return factor + 1 ; case ADDRESS_SYMBOLIC : return factor * loongarch_symbol_insns ( addr . symbol_type , mode ) ; } return 0 ; } </s>

Return the number of instructions needed to load or store a value of mode MODE at address X . Return 0 if X is n't valid for MODE . Assume that multiword moves may need to be split into word moves if MIGHT_SPLIT_P , otherwise assume that a single load or store is enough .


<s> static void sh_va_start ( tree valist , rtx nextarg ) { tree f_next_o , f_next_o_limit , f_next_fp , f_next_fp_limit , f_next_stack ; tree next_o , next_o_limit , next_fp , next_fp_limit , next_stack ; tree t , u ; int nfp , nint ; if ( ( ! TARGET_SH2E && ! TARGET_SH4 ) || TARGET_HITACHI || sh_cfun_attr_renesas_p ( ) ) { std_expand_builtin_va_start ( valist , nextarg ) ; return ; } f_next_o = TYPE_FIELDS ( va_list_type_node ) ; f_next_o_limit = DECL_CHAIN ( f_next_o ) ; f_next_fp = DECL_CHAIN ( f_next_o_limit ) ; f_next_fp_limit = DECL_CHAIN ( f_next_fp ) ; f_next_stack = DECL_CHAIN ( f_next_fp_limit ) ; next_o = build3 ( COMPONENT_REF , TREE_TYPE ( f_next_o ) , valist , f_next_o , NULL_TREE ) ; next_o_limit = build3 ( COMPONENT_REF , TREE_TYPE ( f_next_o_limit ) , valist , f_next_o_limit , NULL_TREE ) ; next_fp = build3 ( COMPONENT_REF , TREE_TYPE ( f_next_fp ) , valist , f_next_fp , NULL_TREE ) ; next_fp_limit = build3 ( COMPONENT_REF , TREE_TYPE ( f_next_fp_limit ) , valist , f_next_fp_limit , NULL_TREE ) ; next_stack = build3 ( COMPONENT_REF , TREE_TYPE ( f_next_stack ) , valist , f_next_stack , NULL_TREE ) ; u = make_tree ( sizetype , expand_builtin_saveregs ( ) ) ; u = fold_convert ( ptr_type_node , u ) ; t = build2 ( MODIFY_EXPR , ptr_type_node , next_fp , u ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; nfp = crtl -> args . info . arg_count [ SH_ARG_FLOAT ] ; if ( nfp < 8 ) nfp = 8 - nfp ; else nfp = 0 ; u = fold_build_pointer_plus_hwi ( u , UNITS_PER_WORD * nfp ) ; t = build2 ( MODIFY_EXPR , ptr_type_node , next_fp_limit , u ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = build2 ( MODIFY_EXPR , ptr_type_node , next_o , u ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; nint = crtl -> args . info . arg_count [ SH_ARG_INT ] ; if ( nint < 4 ) nint = 4 - nint ; else nint = 0 ; u = fold_build_pointer_plus_hwi ( u , UNITS_PER_WORD * nint ) ; t = build2 ( MODIFY_EXPR , ptr_type_node , next_o_limit , u ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; u = make_tree ( ptr_type_node , nextarg ) ; t = build2 ( MODIFY_EXPR , ptr_type_node , next_stack , u ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; } </s>

Implement ` va_start ' for varargs and stdarg .


<s>
bool
ARMAsmPrinter
::
doInitialization
(
Module
&
M
)
{
bool
Result
=
AsmPrinter
::
doInitialization
(
M
)
;
MMI
=
getAnalysisIfAvailable
<
MachineModuleInfo
>
(
)
;
assert
(
MMI
)
;
DW
=
getAnalysisIfAvailable
<
DwarfWriter
>
(
)
;
assert
(
DW
&&
"Dwarf Writer is not available"
)
;
DW
->
BeginModule
(
&
M
,
MMI
,
O
,
this
,
TAI
)
;
if
(
Subtarget
->
isTargetDarwin
(
)
)
Mang
->
setUseQuotes
(
true
)
;
if
(
Subtarget
->
isTargetELF
(
)
)
{
std
::
string
CPUString
=
Subtarget
->
getCPUString
(
)
;
if
(
CPUString
!=
"generic"
)
O
<<
"\t.cpu "
<<
CPUString
<<
'\n'
;
if
(
Subtarget
->
hasVFP2
(
)
)
O
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
VFP_arch
<<
", 2\n"
;
if
(
!
UnsafeFPMath
)
O
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
ABI_FP_denormal
<<
", 1\n"
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
ABI_FP_exceptions
<<
", 1\n"
;
if
(
FiniteOnlyFPMath
(
)
)
O
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
ABI_FP_number_model
<<
", 1\n"
;
else
O
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
ABI_FP_number_model
<<
", 3\n"
;
O
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
ABI_align8_needed
<<
", 1\n"
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
ABI_align8_preserved
<<
", 1\n"
;
}
return
Result
;
}
</s>

Set up the AsmPrinter when we are working on a new module .

ARM
ARM
"Dwarf Writer is not available"
"generic"
"\t.cpu "
"\t.eabi_attribute "
ARMBuildAttrs::VFP_arch
", 2\n"
"\t.eabi_attribute "
ARMBuildAttrs::ABI_FP_denormal
", 1\n"
"\t.eabi_attribute "
ARMBuildAttrs::ABI_FP_exceptions
", 1\n"
"\t.eabi_attribute "
ARMBuildAttrs::ABI_FP_number_model
", 1\n"
"\t.eabi_attribute "
ARMBuildAttrs::ABI_FP_number_model
", 3\n"
"\t.eabi_attribute "
ARMBuildAttrs::ABI_align8_needed
", 1\n"
"\t.eabi_attribute "
ARMBuildAttrs::ABI_align8_preserved
", 1\n"


<s> bool VLIWResourceModel :: isResourceAvailable ( SUnit * SU , bool IsTop ) { if ( ! SU || ! SU -> getInstr ( ) ) return false ; switch ( SU -> getInstr ( ) -> getOpcode ( ) ) { default : if ( ! ResourcesModel -> canReserveResources ( * SU -> getInstr ( ) ) ) return false ; break ; case TargetOpcode :: EXTRACT_SUBREG : case TargetOpcode :: INSERT_SUBREG : case TargetOpcode :: SUBREG_TO_REG : case TargetOpcode :: REG_SEQUENCE : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: COPY : case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : break ; } MachineBasicBlock * MBB = SU -> getInstr ( ) -> getParent ( ) ; auto & QST = MBB -> getParent ( ) -> getSubtarget < HexagonSubtarget > ( ) ; const auto & QII = * QST . getInstrInfo ( ) ; if ( IsTop ) { for ( unsigned i = 0 , e = Packet . size ( ) ; i != e ; ++ i ) if ( hasDependence ( Packet [ i ] , SU , QII ) ) return false ; } else { for ( unsigned i = 0 , e = Packet . size ( ) ; i != e ; ++ i ) if ( hasDependence ( SU , Packet [ i ] , QII ) ) return false ; } return true ; } </s>

Check if scheduling of this SU is possible in the current packet .


<s> static int alpha_memory_move_cost ( machine_mode , reg_class_t , bool ) { return 2 * alpha_memory_latency ; } </s>

Return the cost of moving data of MODE from a register to or from memory . On the Alpha , bump this up a bit .


<s> const char * output_mod_insn ( int unsignedp , rtx insn ) { if ( unsignedp ) { import_milli ( remU ) ; return output_millicode_call ( insn , gen_rtx_SYMBOL_REF ( SImode , "$$remU" ) ) ; } else { import_milli ( remI ) ; return output_millicode_call ( insn , gen_rtx_SYMBOL_REF ( SImode , "$$remI" ) ) ; } } </s>


<s>
void
BlackfinInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
I
!=
MBB
.
end
(
)
I
->
getDebugLoc
(
)
:
DebugLoc
::
getUnknownLoc
(
)
;
if
(
inClass
(
BF
::
DPRegClass
,
DestReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
LOAD32fi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
if
(
inClass
(
BF
::
D16RegClass
,
DestReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
LOAD16fi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
if
(
inClass
(
BF
::
AnyCCRegClass
,
DestReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
LOAD8fi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
llvm_unreachable
(
"Cannot load regclass from stack slot"
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> int VEFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const VERegisterInfo * RegInfo = STI . getRegisterInfo ( ) ; const VEMachineFunctionInfo * FuncInfo = MF . getInfo < VEMachineFunctionInfo > ( ) ; bool isFixed = MFI . isFixedObjectIndex ( FI ) ; int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) ; if ( FuncInfo -> isLeafProc ( ) ) { FrameReg = VE :: SX11 ; return FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ; } if ( RegInfo -> needsStackRealignment ( MF ) && ! isFixed ) { if ( hasBP ( MF ) ) FrameReg = VE :: SX17 ; else FrameReg = VE :: SX11 ; return FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ; } FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FrameOffset ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> static tree rs6000_builtin_reciprocal ( unsigned int fn , bool md_fn , bool sqrt ATTRIBUTE_UNUSED ) { if ( optimize_insn_for_size_p ( ) ) return NULL_TREE ; if ( md_fn ) switch ( fn ) { case VSX_BUILTIN_XVSQRTDP : if ( ! RS6000_RECIP_AUTO_RSQRTE_P ( V2DFmode ) ) return NULL_TREE ; return rs6000_builtin_decls [ VSX_BUILTIN_RSQRT_2DF ] ; case VSX_BUILTIN_XVSQRTSP : if ( ! RS6000_RECIP_AUTO_RSQRTE_P ( V4SFmode ) ) return NULL_TREE ; return rs6000_builtin_decls [ VSX_BUILTIN_RSQRT_4SF ] ; default : return NULL_TREE ; } else switch ( fn ) { case BUILT_IN_SQRT : if ( ! RS6000_RECIP_AUTO_RSQRTE_P ( DFmode ) ) return NULL_TREE ; return rs6000_builtin_decls [ RS6000_BUILTIN_RSQRT ] ; case BUILT_IN_SQRTF : if ( ! RS6000_RECIP_AUTO_RSQRTE_P ( SFmode ) ) return NULL_TREE ; return rs6000_builtin_decls [ RS6000_BUILTIN_RSQRTF ] ; default : return NULL_TREE ; } } </s>

Returns a code for a target-specific builtin that implements reciprocal of the function , or NULL_TREE if not available .


<s> void XCoreTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; BSSSection = Ctx . getELFSection ( ".dp.bss" , ELF :: SHT_NOBITS , ELF :: SHF_ALLOC | ELF :: SHF_WRITE | ELF :: XCORE_SHF_DP_SECTION ) ; BSSSectionLarge = Ctx . getELFSection ( ".dp.bss.large" , ELF :: SHT_NOBITS , ELF :: SHF_ALLOC | ELF :: SHF_WRITE | ELF :: XCORE_SHF_DP_SECTION ) ; DataSection = Ctx . getELFSection ( ".dp.data" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_WRITE | ELF :: XCORE_SHF_DP_SECTION ) ; DataSectionLarge = Ctx . getELFSection ( ".dp.data.large" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_WRITE | ELF :: XCORE_SHF_DP_SECTION ) ; DataRelROSection = Ctx . getELFSection ( ".dp.rodata" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_WRITE | ELF :: XCORE_SHF_DP_SECTION ) ; DataRelROSectionLarge = Ctx . getELFSection ( ".dp.rodata.large" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_WRITE | ELF :: XCORE_SHF_DP_SECTION ) ; ReadOnlySection = Ctx . getELFSection ( ".cp.rodata" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: XCORE_SHF_CP_SECTION ) ; ReadOnlySectionLarge = Ctx . getELFSection ( ".cp.rodata.large" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: XCORE_SHF_CP_SECTION ) ; MergeableConst4Section = Ctx . getELFSection ( ".cp.rodata.cst4" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_MERGE | ELF :: XCORE_SHF_CP_SECTION , 4 ) ; MergeableConst8Section = Ctx . getELFSection ( ".cp.rodata.cst8" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_MERGE | ELF :: XCORE_SHF_CP_SECTION , 8 ) ; MergeableConst16Section = Ctx . getELFSection ( ".cp.rodata.cst16" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_MERGE | ELF :: XCORE_SHF_CP_SECTION , 16 ) ; CStringSection = Ctx . getELFSection ( ".cp.rodata.string" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_MERGE | ELF :: SHF_STRINGS | ELF :: XCORE_SHF_CP_SECTION ) ; } </s>

This method must be called before any actual lowering is done .


<s> MachineBasicBlock * LinearizedRegion :: getEntry ( ) { return Entry ; } </s>

Get the entry BasicBlock of this RegionNode .


<s> const ARMMCExpr * ARMMCExpr :: create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { return new ( Ctx ) ARMMCExpr ( Kind , Expr ) ; } </s>


<s> static rtx legitimize_pic_address ( rtx orig , rtx reg , rtx picreg ) { rtx addr = orig ; rtx new_rtx = orig ; if ( GET_CODE ( addr ) == SYMBOL_REF || GET_CODE ( addr ) == LABEL_REF ) { int unspec ; rtx tmp ; if ( TARGET_ID_SHARED_LIBRARY ) unspec = UNSPEC_MOVE_PIC ; else if ( GET_CODE ( addr ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( addr ) ) unspec = UNSPEC_FUNCDESC_GOT17M4 ; else unspec = UNSPEC_MOVE_FDPIC ; if ( reg == 0 ) { gcc_assert ( can_create_pseudo_p ( ) ) ; reg = gen_reg_rtx ( Pmode ) ; } tmp = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , addr ) , unspec ) ; new_rtx = gen_const_mem ( Pmode , gen_rtx_PLUS ( Pmode , picreg , tmp ) ) ; emit_move_insn ( reg , new_rtx ) ; if ( picreg == pic_offset_table_rtx ) crtl -> uses_pic_offset_table = 1 ; return reg ; } else if ( GET_CODE ( addr ) == CONST || GET_CODE ( addr ) == PLUS ) { rtx base ; if ( GET_CODE ( addr ) == CONST ) { addr = XEXP ( addr , 0 ) ; gcc_assert ( GET_CODE ( addr ) == PLUS ) ; } if ( XEXP ( addr , 0 ) == picreg ) return orig ; if ( reg == 0 ) { gcc_assert ( can_create_pseudo_p ( ) ) ; reg = gen_reg_rtx ( Pmode ) ; } base = legitimize_pic_address ( XEXP ( addr , 0 ) , reg , picreg ) ; addr = legitimize_pic_address ( XEXP ( addr , 1 ) , base == reg ? NULL_RTX : reg , picreg ) ; if ( GET_CODE ( addr ) == CONST_INT ) { gcc_assert ( ! reload_in_progress && ! reload_completed ) ; addr = force_reg ( Pmode , addr ) ; } if ( GET_CODE ( addr ) == PLUS && CONSTANT_P ( XEXP ( addr , 1 ) ) ) { base = gen_rtx_PLUS ( Pmode , base , XEXP ( addr , 0 ) ) ; addr = XEXP ( addr , 1 ) ; } return gen_rtx_PLUS ( Pmode , base , addr ) ; } return new_rtx ; } </s>

Legitimize PIC addresses . If the address is already position-independent , we return ORIG . Newly generated position-independent addresses go into a reg . This is REG if nonzero , otherwise we allocate register ( s ) as necessary .


<s> void ARMELFStreamer :: reset ( ) { MCTargetStreamer & TS = * getTargetStreamer ( ) ; ARMTargetStreamer & ATS = static_cast < ARMTargetStreamer & > ( TS ) ; ATS . reset ( ) ; MappingSymbolCounter = 0 ; MCELFStreamer :: reset ( ) ; getAssembler ( ) . setELFHeaderEFlags ( ELF :: EF_ARM_EABI_VER5 ) ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s> static void store_reg ( int reg , HOST_WIDE_INT disp , int base ) { rtx dest , src , basereg ; rtx_insn * insn ; src = gen_rtx_REG ( word_mode , reg ) ; basereg = gen_rtx_REG ( Pmode , base ) ; if ( VAL_14_BITS_P ( disp ) ) { dest = gen_rtx_MEM ( word_mode , plus_constant ( Pmode , basereg , disp ) ) ; insn = emit_move_insn ( dest , src ) ; } else if ( TARGET_64BIT && ! VAL_32_BITS_P ( disp ) ) { rtx delta = GEN_INT ( disp ) ; rtx tmpreg = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( tmpreg , delta ) ; insn = emit_move_insn ( tmpreg , gen_rtx_PLUS ( Pmode , tmpreg , basereg ) ) ; if ( DO_FRAME_NOTES ) { add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( tmpreg , gen_rtx_PLUS ( Pmode , basereg , delta ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } dest = gen_rtx_MEM ( word_mode , tmpreg ) ; insn = emit_move_insn ( dest , src ) ; } else { rtx delta = GEN_INT ( disp ) ; rtx high = gen_rtx_PLUS ( Pmode , basereg , gen_rtx_HIGH ( Pmode , delta ) ) ; rtx tmpreg = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( tmpreg , high ) ; dest = gen_rtx_MEM ( word_mode , gen_rtx_LO_SUM ( Pmode , tmpreg , delta ) ) ; insn = emit_move_insn ( dest , src ) ; if ( DO_FRAME_NOTES ) add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( gen_rtx_MEM ( word_mode , gen_rtx_PLUS ( word_mode , basereg , delta ) ) , src ) ) ; } if ( DO_FRAME_NOTES ) RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Emit RTL to store REG at the memory location specified by BASE+DISP . Handle case where DISP > 8k by using the add_high_const patterns . Note in DISP > 8k case , we will leave the high part of the address in % r1 . There is code in expand_hppa_ { prologue , epilogue } that knows this .


<s> bool PPCDarwinAsmPrinter :: doFinalization ( Module & M ) { bool isPPC64 = TM . getDataLayout ( ) -> getPointerSizeInBits ( ) == 64 ; const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetFnStubList ( ) ; if ( ! Stubs . empty ( ) ) EmitFunctionStubs ( Stubs ) ; if ( MAI -> doesSupportExceptionHandling ( ) && MMI ) { const std :: vector < const Function * > & Personalities = MMI -> getPersonalities ( ) ; for ( std :: vector < const Function * > :: const_iterator I = Personalities . begin ( ) , E = Personalities . end ( ) ; I != E ; ++ I ) { if ( * I ) { MCSymbol * NLPSym = GetSymbolWithGlobalValueBase ( * I , "$non_lazy_ptr" ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMIMacho . getGVStubEntry ( NLPSym ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( * I ) , true ) ; } } } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue ( 0 , isPPC64 ? 8 : 4 ) ; else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> static bool aarch64_modifies_global_state_p ( unsigned int f , machine_mode mode ) { unsigned int flags = aarch64_call_properties ( f , mode ) ; if ( flags & FLAG_RAISE_FP_EXCEPTIONS ) return true ; if ( flags & FLAG_PREFETCH_MEMORY ) return true ; return flags & FLAG_WRITE_MEMORY ; } </s>

Return true if calls to the function could modify some form of global state .


<s> bool MipsAsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> static void ia64_vms_init_libfuncs ( void ) { set_optab_libfunc ( sdiv_optab , SImode , "OTS$DIV_I" ) ; set_optab_libfunc ( sdiv_optab , DImode , "OTS$DIV_L" ) ; set_optab_libfunc ( udiv_optab , SImode , "OTS$DIV_UI" ) ; set_optab_libfunc ( udiv_optab , DImode , "OTS$DIV_UL" ) ; set_optab_libfunc ( smod_optab , SImode , "OTS$REM_I" ) ; set_optab_libfunc ( smod_optab , DImode , "OTS$REM_L" ) ; set_optab_libfunc ( umod_optab , SImode , "OTS$REM_UI" ) ; set_optab_libfunc ( umod_optab , DImode , "OTS$REM_UL" ) ; MEM_LIBFUNCS_INIT ; } </s>

Rename the division and modulus functions in VMS .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> MVT :: SimpleValueType SPUTargetLowering :: getSetCCResultType ( EVT VT ) const { MVT :: SimpleValueType retval ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: i1 : case MVT :: i8 : retval = MVT :: i8 ; break ; case MVT :: i16 : retval = MVT :: i16 ; break ; case MVT :: i32 : default : retval = MVT :: i32 ; } return retval ; } </s>

Return the value type to use for ISD : :SETCC .


"loadRegFromStackSlot should not be called for PTX"


<s>
bool
AMDGPUOpenCLEnqueuedBlockLowering
::
runOnModule
(
Module
&
M
)
{
DenseSet
<
Function
*
>
Callers
;
auto
&
C
=
M
.
getContext
(
)
;
bool
Changed
=
false
;
for
(
auto
&
F
:
M
.
functions
(
)
)
{
if
(
F
.
hasFnAttribute
(
"enqueued-block"
)
)
{
if
(
!
F
.
hasOneUse
(
)
||
!
F
.
user_begin
(
)
->
hasOneUse
(
)
||
!
isa
<
ConstantExpr
>
(
*
F
.
user_begin
(
)
)
||
!
isa
<
ConstantExpr
>
(
*
F
.
user_begin
(
)
->
user_begin
(
)
)
)
{
continue
;
}
auto
*
BitCast
=
cast
<
ConstantExpr
>
(
*
F
.
user_begin
(
)
)
;
auto
*
AddrCast
=
cast
<
ConstantExpr
>
(
*
BitCast
->
user_begin
(
)
)
;
auto
RuntimeHandle
=
(
F
.
getName
(
)
+
"_runtime_handle"
)
.
str
(
)
;
auto
*
GV
=
new
GlobalVariable
(
M
,
Type
::
getInt8Ty
(
C
)
->
getPointerTo
(
AMDGPUAS
::
GLOBAL_ADDRESS
)
,
true
,
GlobalValue
::
ExternalLinkage
,
nullptr
,
RuntimeHandle
,
nullptr
,
GlobalValue
::
NotThreadLocal
,
AMDGPUAS
::
GLOBAL_ADDRESS
,
true
)
;
DEBUG
(
dbgs
(
)
<<
"runtime handle created: "
<<
*
GV
<<
'\n'
)
;
auto
*
NewPtr
=
ConstantExpr
::
getPointerCast
(
GV
,
AddrCast
->
getType
(
)
)
;
AddrCast
->
replaceAllUsesWith
(
NewPtr
)
;
F
.
addFnAttr
(
"runtime-handle"
,
RuntimeHandle
)
;
F
.
setLinkage
(
GlobalValue
::
ExternalLinkage
)
;
for
(
auto
U
:
NewPtr
->
users
(
)
)
{
if
(
auto
*
I
=
dyn_cast
<
Instruction
>
(
&
*
U
)
)
{
auto
*
F
=
I
->
getParent
(
)
->
getParent
(
)
;
Callers
.
insert
(
F
)
;
collectCallers
(
F
,
Callers
)
;
}
}
Changed
=
true
;
}
}
for
(
auto
F
:
Callers
)
{
if
(
F
->
getCallingConv
(
)
!=
CallingConv
::
AMDGPU_KERNEL
)
continue
;
F
->
addFnAttr
(
"calls-enqueue-kernel"
)
;
}
return
Changed
;
}
</s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .

AMDGPU
AMDGPU
"enqueued-block"
"_runtime_handle"
AMDGPU
AMDGPU
"runtime handle created: "
"runtime-handle"
AMDGPU
"calls-enqueue-kernel"


<s>
static
void
cris_asm_output_mi_thunk
(
FILE
*
stream
,
tree
thunkdecl
ATTRIBUTE_UNUSED
,
HOST_WIDE_INT
delta
,
HOST_WIDE_INT
vcall_offset
ATTRIBUTE_UNUSED
,
tree
funcdecl
)
{
final_start_function
(
emit_barrier
(
)
,
stream
,
1
)
;
if
(
delta
>
0
)
fprintf
(
stream
,
"\tadd%s "
HOST_WIDE_INT_PRINT_DEC
",$%s\n"
,
ADDITIVE_SIZE_MODIFIER
(
delta
)
,
delta
,
reg_names
[
CRIS_FIRST_ARG_REG
]
)
;
else
if
(
delta
<
0
)
fprintf
(
stream
,
"\tsub%s "
HOST_WIDE_INT_PRINT_DEC
",$%s\n"
,
ADDITIVE_SIZE_MODIFIER
(
delta
)
,
delta
,
reg_names
[
CRIS_FIRST_ARG_REG
]
)
;
if
(
flag_pic
)
{
const
char
*
name
=
XSTR
(
XEXP
(
DECL_RTL
(
funcdecl
)
,
0
)
,
0
)
;
name
=
(
*
targetm
.
strip_name_encoding
)
(
name
)
;
if
(
TARGET_V32
)
{
fprintf
(
stream
,
"\tba "
)
;
assemble_name
(
stream
,
name
)
;
fprintf
(
stream
,
"%s\n"
,
CRIS_PLT_PCOFFSET_SUFFIX
)
;
}
else
{
fprintf
(
stream
,
"add.d "
)
;
assemble_name
(
stream
,
name
)
;
fprintf
(
stream
,
"%s,$pc\n"
,
CRIS_PLT_PCOFFSET_SUFFIX
)
;
}
}
else
{
fprintf
(
stream
,
"jump "
)
;
assemble_name
(
stream
,
XSTR
(
XEXP
(
DECL_RTL
(
funcdecl
)
,
0
)
,
0
)
)
;
fprintf
(
stream
,
"\n"
)
;
if
(
TARGET_V32
)
fprintf
(
stream
,
"\tnop\n"
)
;
}
final_end_function
(
)
;
}
</s>


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Hexagon CFG Optimizer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static rtx gen_stack_pointer_dec ( rtx decrement ) { return gen_rtx_SET ( VOIDmode , stack_pointer_rtx , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , decrement ) ) ; } </s>

Generate a decrement for the stack pointer .


<s> unsigned AMDGPUAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & Op , unsigned Kind ) { AMDGPUOperand & Operand = ( AMDGPUOperand & ) Op ; switch ( Kind ) { case MCK_addr64 : return Operand . isAddr64 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_gds : return Operand . isGDS ( ) ? Match_Success : Match_InvalidOperand ; case MCK_lds : return Operand . isLDS ( ) ? Match_Success : Match_InvalidOperand ; case MCK_glc : return Operand . isGLC ( ) ? Match_Success : Match_InvalidOperand ; case MCK_idxen : return Operand . isIdxen ( ) ? Match_Success : Match_InvalidOperand ; case MCK_offen : return Operand . isOffen ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SSrcB32 : return Operand . isSSrcB32 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SSrcF32 : return Operand . isSSrcF32 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SoppBrTarget : return Operand . isSoppBrTarget ( ) ? Match_Success : Match_InvalidOperand ; case MCK_VReg32OrOff : return Operand . isVReg32OrOff ( ) ? Match_Success : Match_InvalidOperand ; case MCK_InterpSlot : return Operand . isInterpSlot ( ) ? Match_Success : Match_InvalidOperand ; case MCK_Attr : return Operand . isInterpAttr ( ) ? Match_Success : Match_InvalidOperand ; case MCK_AttrChan : return Operand . isAttrChan ( ) ? Match_Success : Match_InvalidOperand ; case MCK_ImmSMEMOffset : return Operand . isSMEMOffset ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SReg_64 : case MCK_SReg_64_XEXEC : return Operand . isNull ( ) ? Match_Success : Match_InvalidOperand ; default : return Match_InvalidOperand ; } } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s>
bool
MipsAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
SmallVectorImpl
<
MCParsedAsmOperand
*
>
&
Operands
)
{
StringRef
Mnemonic
;
setDefaultFpFormat
(
)
;
size_t
Start
=
0
,
Next
=
Name
.
find
(
'.'
)
;
Mnemonic
=
Name
.
slice
(
Start
,
Next
)
;
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Mnemonic
,
NameLoc
)
)
;
if
(
Next
!=
StringRef
::
npos
)
{
size_t
Dot
=
Name
.
find
(
'.'
,
Next
+
1
)
;
StringRef
Format
=
Name
.
slice
(
Next
,
Dot
)
;
if
(
Dot
==
StringRef
::
npos
)
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Format
,
NameLoc
)
)
;
else
{
if
(
Name
.
startswith
(
"c."
)
)
{
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
"."
,
NameLoc
)
)
;
int
Cc
=
ConvertCcString
(
Format
)
;
if
(
Cc
==
1
)
{
return
Error
(
NameLoc
,
"Invalid conditional code"
)
;
}
SMLoc
E
=
SMLoc
::
getFromPointer
(
Parser
.
getTok
(
)
.
getLoc
(
)
.
getPointer
(
)
1
)
;
Operands
.
push_back
(
MipsOperand
::
CreateImm
(
MCConstantExpr
::
Create
(
Cc
,
getContext
(
)
)
,
NameLoc
,
E
)
)
;
}
else
{
return
parseMathOperation
(
Name
,
NameLoc
,
Operands
)
;
}
Format
=
Name
.
slice
(
Dot
,
StringRef
::
npos
)
;
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Format
,
NameLoc
)
)
;
}
setFpFormat
(
Format
)
;
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
ParseOperand
(
Operands
,
Mnemonic
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .


<s> InstructionCost ARMTTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind , Instruction * Inst ) { if ( ( Opcode == Instruction :: SDiv || Opcode == Instruction :: UDiv || Opcode == Instruction :: SRem || Opcode == Instruction :: URem ) && Idx == 1 ) return 0 ; if ( Opcode == Instruction :: GetElementPtr && Idx != 0 ) return 0 ; if ( Opcode == Instruction :: And ) { if ( Imm == 255 || Imm == 65535 ) return 0 ; return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( ~ Imm , Ty , CostKind ) ) ; } if ( Opcode == Instruction :: Add ) return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( - Imm , Ty , CostKind ) ) ; if ( Opcode == Instruction :: ICmp && Imm . isNegative ( ) && Ty -> getIntegerBitWidth ( ) == 32 ) { int64_t NegImm = - Imm . getSExtValue ( ) ; if ( ST -> isThumb2 ( ) && NegImm < 1 << 12 ) return 0 ; if ( ST -> isThumb ( ) && NegImm < 1 << 8 ) return 0 ; } if ( Opcode == Instruction :: Xor && Imm . isAllOnesValue ( ) ) return 0 ; if ( Inst && ( ( ST -> hasV6Ops ( ) && ! ST -> isThumb ( ) ) || ST -> isThumb2 ( ) ) && Ty -> getIntegerBitWidth ( ) <= 32 ) { if ( isSSATMinMaxPattern ( Inst , Imm ) || ( isa < ICmpInst > ( Inst ) && Inst -> hasOneUse ( ) && isSSATMinMaxPattern ( cast < Instruction > ( * Inst -> user_begin ( ) ) , Imm ) ) ) return 0 ; } return getIntImmCost ( Imm , Ty , CostKind ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> int insn_refs_are_delayed ( rtx insn ) { return ( ( GET_CODE ( insn ) == INSN && GET_CODE ( PATTERN ( insn ) ) != SEQUENCE && GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER && get_attr_type ( insn ) == TYPE_MILLI ) ) ; } </s>

Return nonzero if references for INSN are delayed . Millicode insns are actually function calls with some special constraints on arguments and register usage . Millicode calls always expect their arguments in the integer argument registers , and always return their result in % r29 ( ret1 ) . They are expected to clobber their arguments , % r1 , % r29 , and the return pointer which is % r31 on 32-bit and % r2 on 64-bit , and nothing else . This function tells reorg that the references to arguments and millicode calls do not appear to happen until after the millicode call . This allows reorg to put insns which set the argument registers into the delay slot of the millicode call -- thus they act more like traditional CALL_INSNs . Note we can not consider side effects of the insn to be delayed because the branch and link insn will clobber the return pointer . If we happened to use the return pointer in the delay slot of the call , then we lose . get_attr_type will try to recognize the given insn , so make sure to filter out things it will not accept -- SEQUENCE , USE and CLOBBER insns in particular .


<s>
bool
RISCVInstrInfo
::
getMemOperandWithOffsetWidth
(
const
MachineInstr
&
LdSt
,
const
MachineOperand
*
&
BaseReg
,
int64_t
&
Offset
,
unsigned
&
Width
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
LdSt
.
mayLoadOrStore
(
)
&&
"Expected a memory operation."
)
;
if
(
LdSt
.
getNumExplicitOperands
(
)
!=
3
)
return
false
;
if
(
!
LdSt
.
getOperand
(
1
)
.
isReg
(
)
||
!
LdSt
.
getOperand
(
2
)
.
isImm
(
)
)
return
false
;
if
(
!
LdSt
.
hasOneMemOperand
(
)
)
return
false
;
Width
=
(
*
LdSt
.
memoperands_begin
(
)
)
->
getSize
(
)
;
BaseReg
=
&
LdSt
.
getOperand
(
1
)
;
Offset
=
LdSt
.
getOperand
(
2
)
.
getImm
(
)
;
return
true
;
}
</s>

Return true if get the base operand , byte offset of an instruction and the memory width .


<s> pru_byterange pru_calc_byterange ( HOST_WIDE_INT cval , machine_mode mode ) { const pru_byterange invalid_range = { - 1 , - 1 } ; pru_byterange r = invalid_range ; enum { ST_FFS , ST_INRANGE , ST_TRAILING_ZEROS } st = ST_FFS ; int i ; for ( i = 0 ; i < GET_MODE_SIZE ( mode ) ; i ++ ) { const int b = cval & ( ( 1U << BITS_PER_UNIT ) - 1 ) ; cval >>= BITS_PER_UNIT ; if ( b == 0x00 && ( st == ST_FFS || st == ST_TRAILING_ZEROS ) ) ; else if ( b == 0x00 && st == ST_INRANGE ) st = ST_TRAILING_ZEROS ; else if ( b == 0xff && st == ST_FFS ) { st = ST_INRANGE ; r . start = i ; r . nbytes = 1 ; } else if ( b == 0xff && st == ST_INRANGE ) r . nbytes ++ ; else return invalid_range ; } if ( st != ST_TRAILING_ZEROS && st != ST_INRANGE ) return invalid_range ; return r ; } </s>

Parse the given CVAL integer value , and extract the `` filling '' byte range of consecutive 0xff byte values . Rest of bytes must be 0x00 . There must be only one range in the given value . This range would typically be used to calculate the parameters of PRU instructions ZERO and FILL . The parameter MODE determines the maximum byte range to consider in the given input constant . Example input : cval = 0xffffffffffffff00 = -256 mode = SImode Return value : start = 1 nbytes = 3 On error , return a range with -1 for START and NBYTES .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addPreserved < StackProtector > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> const TargetRegisterClass * SystemZRegisterInfo :: getMatchingSuperRegClass ( const TargetRegisterClass * A , const TargetRegisterClass * B , unsigned Idx ) const { switch ( Idx ) { default : return 0 ; case SystemZ :: subreg_32bit : if ( B == SystemZ :: ADDR32RegisterClass ) return A -> getSize ( ) == 8 ? SystemZ :: ADDR64RegisterClass : 0 ; return A ; } } </s>

getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register in it has a sub-register of the specified sub-register index which is in the specified register class B .


<s>
void
X86InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
Register
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
assert
(
MF
.
getFrameInfo
(
)
.
getObjectSize
(
FrameIdx
)
>=
TRI
->
getSpillSize
(
*
RC
)
&&
"Stack slot too small for store"
)
;
unsigned
Alignment
=
std
::
max
<
uint32_t
>
(
TRI
->
getSpillSize
(
*
RC
)
,
16
)
;
bool
isAligned
=
(
Subtarget
.
getFrameLowering
(
)
->
getStackAlign
(
)
>=
Alignment
)
||
RI
.
canRealignStack
(
MF
)
;
unsigned
Opc
=
getStoreRegOpcode
(
SrcReg
,
RC
,
isAligned
,
Subtarget
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DebugLoc
(
)
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> void init_68881_table ( ) { int i ; REAL_VALUE_TYPE r ; enum machine_mode mode ; mode = SFmode ; for ( i = 0 ; i < 7 ; i ++ ) { if ( i == 6 ) mode = DFmode ; r = REAL_VALUE_ATOF ( strings_68881 [ i ] , mode ) ; values_68881 [ i ] = r ; } inited_68881_table = 1 ; } </s>

Set up values_68881 array by converting the decimal values strings_68881 to binary .


<s> static void release_scratch_register_on_entry ( struct scratch_reg * sr ) { if ( sr -> saved ) { rtx addr = gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ; rtx insn = emit_set_insn ( sr -> reg , gen_frame_mem ( SImode , addr ) ) ; rtx x = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , 4 ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , x ) ; } } </s>

Release a scratch register obtained from the preceding function . If RELEASE_VIA_POP is true , we just pop the register off the stack to release it . This is what non-Linux systems use with -fstack-check . Otherwise we use OFFSET to locate the saved register and the allocated stack space becomes part of the local frame and is deallocated by the epilogue .


<s> unsigned getReg ( ) const override { assert ( isReg ( ) ) ; return Reg ; } </s>

Returns the register associated with this edge .


<s> bool NVPTXPeephole :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; bool Changed = false ; for ( auto & MBB : MF ) { auto BlockIter = MBB . begin ( ) ; while ( BlockIter != MBB . end ( ) ) { auto & MI = * BlockIter ++ ; if ( isCVTAToLocalCombinationCandidate ( MI ) ) { CombineCVTAToLocal ( MI ) ; Changed = true ; } } } const NVPTXRegisterInfo * NRI = MF . getSubtarget < NVPTXSubtarget > ( ) . getRegisterInfo ( ) ; const auto & MRI = MF . getRegInfo ( ) ; if ( MRI . use_empty ( NRI -> getFrameRegister ( MF ) ) ) { if ( auto MI = MRI . getUniqueVRegDef ( NRI -> getFrameRegister ( MF ) ) ) { MI -> eraseFromParent ( ) ; } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> tree aarch64_builtin_decl ( unsigned code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= AARCH64_BUILTIN_MAX ) return error_mark_node ; return aarch64_builtin_decls [ code ] ; } </s>


"Last pick result should correspond to re-picking right now"

Pick the best candidate node from either the top or bottom queue .


<s> bool SITargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & CI , MachineFunction & MF , unsigned IntrID ) const { if ( const AMDGPU :: RsrcIntrinsic * RsrcIntr = AMDGPU :: lookupRsrcIntrinsic ( IntrID ) ) { AttributeList Attr = Intrinsic :: getAttributes ( CI . getContext ( ) , ( Intrinsic :: ID ) IntrID ) ; if ( Attr . hasFnAttribute ( Attribute :: ReadNone ) ) return false ; SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; if ( RsrcIntr -> IsImage ) { Info . ptrVal = MFI -> getImagePSV ( * MF . getSubtarget < GCNSubtarget > ( ) . getInstrInfo ( ) , CI . getArgOperand ( RsrcIntr -> RsrcArg ) ) ; Info . align = 0 ; } else { Info . ptrVal = MFI -> getBufferPSV ( * MF . getSubtarget < GCNSubtarget > ( ) . getInstrInfo ( ) , CI . getArgOperand ( RsrcIntr -> RsrcArg ) ) ; } Info . flags = MachineMemOperand :: MODereferenceable ; if ( Attr . hasFnAttribute ( Attribute :: ReadOnly ) ) { Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: getVT ( CI . getType ( ) ) ; Info . flags |= MachineMemOperand :: MOLoad ; } else if ( Attr . hasFnAttribute ( Attribute :: WriteOnly ) ) { Info . opc = ISD :: INTRINSIC_VOID ; Info . memVT = MVT :: getVT ( CI . getArgOperand ( 0 ) -> getType ( ) ) ; Info . flags |= MachineMemOperand :: MOStore ; } else { Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: getVT ( CI . getType ( ) ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MODereferenceable ; Info . flags |= MachineMemOperand :: MOVolatile ; } return true ; } switch ( IntrID ) { case Intrinsic :: amdgcn_atomic_inc : case Intrinsic :: amdgcn_atomic_dec : case Intrinsic :: amdgcn_ds_fadd : case Intrinsic :: amdgcn_ds_fmin : case Intrinsic :: amdgcn_ds_fmax : { Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: getVT ( CI . getType ( ) ) ; Info . ptrVal = CI . getOperand ( 0 ) ; Info . align = 0 ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore ; const ConstantInt * Vol = dyn_cast < ConstantInt > ( CI . getOperand ( 4 ) ) ; if ( ! Vol || ! Vol -> isZero ( ) ) Info . flags |= MachineMemOperand :: MOVolatile ; return true ; } default : return false ; } } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> void ARMHazardRecognizer :: AdvanceCycle ( ) { if ( Stalls && -- Stalls == 0 ) LastMI = 0 ; ScoreboardHazardRecognizer :: AdvanceCycle ( ) ; } </s>

AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled can not issue in the current cycle , either because of latency or resource conflicts .


<s> BitVector SIRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AMDGPU :: EXEC ) ; Reserved . set ( AMDGPU :: EXEC_LO ) ; Reserved . set ( AMDGPU :: EXEC_HI ) ; Reserved . set ( AMDGPU :: INDIRECT_BASE_ADDR ) ; Reserved . set ( AMDGPU :: FLAT_SCR ) ; Reserved . set ( AMDGPU :: VGPR255 ) ; Reserved . set ( AMDGPU :: VGPR254 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> const uint32_t * AArch64RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return CSR_AArch64_NoRegs_RegMask ; if ( CC == CallingConv :: AnyReg ) return CSR_AArch64_AllRegs_RegMask ; if ( CC == CallingConv :: CXX_FAST_TLS ) return CSR_AArch64_CXX_TLS_Darwin_RegMask ; if ( MF . getSubtarget < AArch64Subtarget > ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) -> getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_AArch64_AAPCS_SwiftError_RegMask ; if ( CC == CallingConv :: PreserveMost ) return CSR_AArch64_RT_MostRegs_RegMask ; else return CSR_AArch64_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> const uint32_t * PPCRegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { if ( Subtarget . isDarwinABI ( ) ) return Subtarget . isPPC64 ( ) ? CSR_Darwin64_RegMask : CSR_Darwin32_RegMask ; return Subtarget . isPPC64 ( ) ? CSR_SVR464_RegMask : CSR_SVR432_RegMask ; } </s>


"Unrecognized Hexagon processor version"

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> MachineInstr * ARM64InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , int FrameIndex ) const { if ( MI -> isCopy ( ) ) { unsigned DstReg = MI -> getOperand ( 0 ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; if ( SrcReg == ARM64 :: SP && TargetRegisterInfo :: isVirtualRegister ( DstReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( DstReg , & ARM64 :: GPR64RegClass ) ; return nullptr ; } if ( DstReg == ARM64 :: SP && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & ARM64 :: GPR64RegClass ) ; return nullptr ; } } return nullptr ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> bool X86TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , MF . getTarget ( ) , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_X86 ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> bool arm_coproc_ldc_stc_legitimate_address ( rtx op ) { HOST_WIDE_INT range ; if ( ! MEM_P ( op ) ) return false ; op = XEXP ( op , 0 ) ; if ( REG_P ( op ) ) return true ; switch GET_CODE ( op ) { case PLUS : { if ( ! REG_P ( XEXP ( op , 0 ) ) ) return false ; op = XEXP ( op , 1 ) ; if ( ! CONST_INT_P ( op ) ) return false ; range = INTVAL ( op ) ; if ( ! IN_RANGE ( range , - 1020 , 1020 ) ) return false ; return ( range % 4 ) == 0 ; } case PRE_INC : case POST_INC : case PRE_DEC : case POST_DEC : return REG_P ( XEXP ( op , 0 ) ) ; default : gcc_unreachable ( ) ; } return false ; } </s>

This function returns true if OP is a valid memory operand for the ldc and stc coprocessor instructions and false otherwise .


<s> EVT TPCTargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & Context , EVT VT ) const { if ( VT . isVector ( ) ) { return EVT :: getVectorVT ( Context , MVT :: i1 , VT . getVectorNumElements ( ) ) ; } return MVT :: SimpleValueType :: i1 ; } </s>

Return the value type to use for ISD : :SETCC .


<s> static bool z8k_reg_ok_for_base_p ( rtx op ) { return GET_MODE ( op ) == Pmode && ( REGNO ( op ) > FIRST_PSEUDO_REGISTER || ( REGNO ( op ) != 0 ) ) ; } </s>

True if X is a hard reg that can be used as a base reg or if it is a pseudo reg .


<s>
bool
M68kInstrInfo
::
ExpandMOVSZX_RM
(
MachineInstrBuilder
&
MIB
,
bool
IsSigned
,
const
MCInstrDesc
&
Desc
,
MVT
MVTDst
,
MVT
MVTSrc
)
const
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Expand "
<<
*
MIB
.
getInstr
(
)
<<
" to LOAD and "
)
;
Register
Dst
=
MIB
->
getOperand
(
0
)
.
getReg
(
)
;
unsigned
SubDst
=
RI
.
getSubReg
(
Dst
,
MVTSrc
==
MVT
::
i8
M68k
::
MxSubRegIndex8Lo
:
M68k
::
MxSubRegIndex16Lo
)
;
assert
(
SubDst
&&
"No viable SUB register available"
)
;
MIB
->
setDesc
(
Desc
)
;
MIB
->
getOperand
(
0
)
.
setReg
(
SubDst
)
;
MachineBasicBlock
::
iterator
I
=
MIB
.
getInstr
(
)
;
I
++
;
MachineBasicBlock
&
MBB
=
*
MIB
->
getParent
(
)
;
DebugLoc
DL
=
MIB
->
getDebugLoc
(
)
;
if
(
IsSigned
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Sign Extend"
<<
'\n'
)
;
AddSExt
(
MBB
,
I
,
DL
,
Dst
,
MVTSrc
,
MVTDst
)
;
}
else
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Zero Extend"
<<
'\n'
)
;
AddZExt
(
MBB
,
I
,
DL
,
Dst
,
MVTSrc
,
MVTDst
)
;
}
return
true
;
}
</s>


<s> void split_adds_subs ( machine_mode mode , rtx * operands ) { HOST_WIDE_INT val = INTVAL ( operands [ 1 ] ) ; rtx reg = operands [ 0 ] ; HOST_WIDE_INT sign = 1 ; HOST_WIDE_INT amount ; rtx ( * gen_add ) ( rtx , rtx , rtx ) ; if ( val < 0 ) { val = - val ; sign = - 1 ; } switch ( mode ) { case E_HImode : gen_add = gen_addhi3 ; break ; case E_SImode : gen_add = gen_addsi3 ; break ; default : gcc_unreachable ( ) ; } for ( amount = 4 ; amount > 0 ; amount /= 2 ) { for ( ; val >= amount ; val -= amount ) emit_insn ( gen_add ( reg , reg , GEN_INT ( sign * amount ) ) ) ; } return ; } </s>

Split an add of a small constant into two adds/subs insns .


<s> bool AArch64PostRASchedStrategy :: tryCandidate ( SchedCandidate & Cand , SchedCandidate & TryCand ) { bool OriginalResult = PostGenericScheduler :: tryCandidate ( Cand , TryCand ) ; if ( Cand . isValid ( ) ) { MachineInstr * Instr0 = TryCand . SU -> getInstr ( ) ; MachineInstr * Instr1 = Cand . SU -> getInstr ( ) ; if ( Instr0 && Instr1 && Instr0 -> getOpcode ( ) == Instr1 -> getOpcode ( ) && Instr0 -> getOpcode ( ) == AArch64 :: STPQi ) { MachineOperand & Base0 = Instr0 -> getOperand ( 2 ) ; MachineOperand & Base1 = Instr1 -> getOperand ( 2 ) ; int64_t Off0 = Instr0 -> getOperand ( 3 ) . getImm ( ) ; int64_t Off1 = Instr1 -> getOperand ( 3 ) . getImm ( ) ; if ( Base0 . isIdenticalTo ( Base1 ) && llabs ( Off0 - Off1 ) >= 2 ) { TryCand . Reason = NodeOrder ; return Off0 < Off1 ; } } } return OriginalResult ; } </s>

Apply a set of heuristics to a new candidate .


<s> tree memory_scalar_type ( const function_instance & fi ) const override { type_class_index tclass = fi . type_suffix ( 0 ) . tclass ; unsigned int element_bits = GET_MODE_BITSIZE ( m_to_mode ) ; type_suffix_index suffix = find_type_suffix ( tclass , element_bits ) ; return scalar_types [ type_suffixes [ suffix ] . vector_type ] ; } </s>

If the function addresses memory , return the type of a single scalar memory element .


<s> inline const type_suffix_info & function_instance :: type_suffix ( unsigned int i ) const { return type_suffixes [ type_suffix_ids [ i ] ] ; } </s>

Return information about type suffix I .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; if ( ! ST . hasHardClauses ( ) ) return false ; const SIInstrInfo * SII = ST . getInstrInfo ( ) ; const TargetRegisterInfo * TRI = ST . getRegisterInfo ( ) ; bool Changed = false ; for ( auto & MBB : MF ) { ClauseInfo CI ; for ( auto & MI : MBB ) { HardClauseType Type = getHardClauseType ( MI ) ; int64_t Dummy1 ; bool Dummy2 ; SmallVector < const MachineOperand * , 4 > BaseOps ; if ( Type <= LAST_REAL_HARDCLAUSE_TYPE ) { if ( ! SII -> getMemOperandsWithOffset ( MI , BaseOps , Dummy1 , Dummy2 , TRI ) ) { Type = HARDCLAUSE_ILLEGAL ; } } if ( CI . Length == 64 || ( CI . Length && Type != HARDCLAUSE_INTERNAL && ( Type != CI . Type || ! SII -> shouldClusterMemOps ( CI . BaseOps , BaseOps , 2 ) ) ) ) { Changed |= emitClause ( CI , SII ) ; CI = ClauseInfo ( ) ; } if ( CI . Length ) { ++ CI . Length ; if ( Type != HARDCLAUSE_INTERNAL ) { CI . Last = & MI ; CI . BaseOps = std :: move ( BaseOps ) ; } } else if ( Type <= LAST_REAL_HARDCLAUSE_TYPE ) { CI = ClauseInfo { Type , & MI , & MI , 1 , std :: move ( BaseOps ) } ; } } if ( CI . Length ) Changed |= emitClause ( CI , SII ) ; } return Changed ; } </s>


<s> bool AMDGPUAsmPrinter :: doFinalization ( Module & M ) { const MCSubtargetInfo & STI = * getGlobalSTI ( ) ; if ( ( AMDGPU :: isGFX10Plus ( STI ) || AMDGPU :: isGFX90A ( STI ) ) && ( STI . getTargetTriple ( ) . getOS ( ) == Triple :: AMDHSA || STI . getTargetTriple ( ) . getOS ( ) == Triple :: AMDPAL ) ) { OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; getTargetStreamer ( ) -> EmitCodeEnd ( STI ) ; } return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> bool TeeRISCPassConfig :: addPreEmitPass ( ) { return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool X86AsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == ".word" ) return ParseDirectiveWord ( 2 , DirectiveID . getLoc ( ) ) ; else if ( IDVal . startswith ( ".code" ) ) return ParseDirectiveCode ( IDVal , DirectiveID . getLoc ( ) ) ; else if ( IDVal . startswith ( ".intel_syntax" ) ) { getParser ( ) . setAssemblerDialect ( 1 ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( Parser . getTok ( ) . getString ( ) == "noprefix" ) { Parser . Lex ( ) ; } else return true ; } return false ; } return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool MCS51PassConfig :: addInstSelector ( ) { addPass ( createMCS51ISelDag ( getMCS51TargetMachine ( ) , getOptLevel ( ) ) ) ; addPass ( createMCS51FrameAnalyzerPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool hasAndNotCompare ( SDValue V ) const override { return V . getValueType ( ) . isScalarInteger ( ) ; } </s>

Return true if the target should transform : ( X & Y ) == Y � ? ( ~X & Y ) == 0 ( X & Y ) ! = Y � ? ( ~X & Y ) ! = 0 .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .