<s>
bool
SIInstrInfo
::
isInlineConstant
(
const
MachineOperand
&
MO
,
uint8_t
OperandType
)
const
{
if
(
!
MO
.
isImm
(
)
||
OperandType
<
AMDGPU
::
OPERAND_SRC_FIRST
||
OperandType
>
AMDGPU
::
OPERAND_SRC_LAST
)
return
false
;
int64_t
Imm
=
MO
.
getImm
(
)
;
switch
(
OperandType
)
{
case
AMDGPU
::
OPERAND_REG_IMM_INT32
:
case
AMDGPU
::
OPERAND_REG_IMM_FP32
:
case
AMDGPU
::
OPERAND_REG_IMM_FP32_DEFERRED
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_INT32
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_FP32
:
case
AMDGPU
::
OPERAND_REG_IMM_V2FP32
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_V2FP32
:
case
AMDGPU
::
OPERAND_REG_IMM_V2INT32
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_V2INT32
:
case
AMDGPU
::
OPERAND_REG_INLINE_AC_INT32
:
case
AMDGPU
::
OPERAND_REG_INLINE_AC_FP32
:
{
int32_t
Trunc
=
static_cast
<
int32_t
>
(
Imm
)
;
return
AMDGPU
::
isInlinableLiteral32
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
case
AMDGPU
::
OPERAND_REG_IMM_INT64
:
case
AMDGPU
::
OPERAND_REG_IMM_FP64
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_INT64
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_FP64
:
case
AMDGPU
::
OPERAND_REG_INLINE_AC_FP64
:
return
AMDGPU
::
isInlinableLiteral64
(
MO
.
getImm
(
)
,
ST
.
hasInv2PiInlineImm
(
)
)
;
case
AMDGPU
::
OPERAND_REG_IMM_INT16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_INT16
:
case
AMDGPU
::
OPERAND_REG_INLINE_AC_INT16
:
return
AMDGPU
::
isInlinableIntLiteral
(
Imm
)
;
case
AMDGPU
::
OPERAND_REG_IMM_V2INT16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_V2INT16
:
case
AMDGPU
::
OPERAND_REG_INLINE_AC_V2INT16
:
return
AMDGPU
::
isInlinableIntLiteralV216
(
Imm
)
;
case
AMDGPU
::
OPERAND_REG_IMM_FP16
:
case
AMDGPU
::
OPERAND_REG_IMM_FP16_DEFERRED
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_FP16
:
case
AMDGPU
::
OPERAND_REG_INLINE_AC_FP16
:
{
if
(
isInt
<
16
>
(
Imm
)
||
isUInt
<
16
>
(
Imm
)
)
{
int16_t
Trunc
=
static_cast
<
int16_t
>
(
Imm
)
;
return
ST
.
has16BitInsts
(
)
&&
AMDGPU
::
isInlinableLiteral16
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
return
false
;
}
case
AMDGPU
::
OPERAND_REG_IMM_V2FP16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_V2FP16
:
case
AMDGPU
::
OPERAND_REG_INLINE_AC_V2FP16
:
{
uint32_t
Trunc
=
static_cast
<
uint32_t
>
(
Imm
)
;
return
AMDGPU
::
isInlinableLiteralV216
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
default
:
llvm_unreachable
(
"invalid bitwidth"
)
;
}
}
</s>

returns true if the operand OpIdx in MI is a valid inline immediate .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> MachineInstrBuilder R600InstrInfo :: buildDefaultInstruction ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned Opcode , unsigned DstReg , unsigned Src0Reg , unsigned Src1Reg ) const { MachineInstrBuilder MIB = BuildMI ( MBB , I , MBB . findDebugLoc ( I ) , get ( Opcode ) , DstReg ) ; if ( Src1Reg ) { MIB . addImm ( 0 ) . addImm ( 0 ) ; } MIB . addImm ( 1 ) . addImm ( 0 ) . addImm ( 0 ) . addImm ( 0 ) . addReg ( Src0Reg ) . addImm ( 0 ) . addImm ( 0 ) . addImm ( 0 ) ; if ( Src1Reg ) { MIB . addReg ( Src1Reg ) . addImm ( 0 ) . addImm ( 0 ) . addImm ( 0 ) ; } MIB . addImm ( 1 ) . addReg ( AMDGPU :: PRED_SEL_OFF ) . addImm ( 0 ) ; return MIB ; } </s>

buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers initialized to their default values .


<s> int riscv_load_store_insns ( rtx mem , rtx_insn * insn ) { machine_mode mode ; bool might_split_p ; rtx set ; gcc_assert ( MEM_P ( mem ) ) ; mode = GET_MODE ( mem ) ; might_split_p = true ; if ( GET_MODE_BITSIZE ( mode ) <= 32 ) might_split_p = false ; else if ( GET_MODE_BITSIZE ( mode ) == 64 ) { set = single_set ( insn ) ; if ( set && ! riscv_split_64bit_move_p ( SET_DEST ( set ) , SET_SRC ( set ) ) ) might_split_p = false ; } return riscv_address_insns ( XEXP ( mem , 0 ) , mode , might_split_p ) ; } </s>

Return the number of instructions needed to implement INSN , given that it loads from or stores to MEM .


"Cannot store this register into a stack slot!"

Store the specified register of the given register class to the specified stack frame index .


<s> bool ARMBaseTargetMachine :: addPreSched2 ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt :: None ) { if ( ! Subtarget . isThumb1Only ( ) ) PM . add ( createARMLoadStoreOptimizationPass ( ) ) ; if ( Subtarget . hasNEON ( ) ) PM . add ( createNEONMoveFixPass ( ) ) ; } PM . add ( createARMExpandPseudoPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> bool X86TargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , unsigned Intrinsic ) const { const IntrinsicData * IntrData = getIntrinsicWithChain ( Intrinsic ) ; if ( ! IntrData ) return false ; switch ( IntrData -> Type ) { case LOADA : case LOADU : { Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: getVT ( I . getType ( ) ) ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . align = ( IntrData -> Type == LOADA ? Info . memVT . getSizeInBits ( ) / 8 : 1 ) ; Info . vol = false ; Info . readMem = true ; Info . writeMem = false ; return true ; } default : break ; } return false ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> static void assign_int_registers ( HOST_WIDE_INT bitpos , assign_data_t * data ) { int intoffset = data -> intoffset ; machine_mode mode ; int nregs ; if ( ! compute_int_layout ( bitpos , data , & nregs ) ) return ; if ( intoffset % BITS_PER_WORD != 0 ) mode = smallest_int_mode_for_size ( BITS_PER_WORD - intoffset % BITS_PER_WORD ) ; else mode = word_mode ; const int this_slotno = data -> slotno + intoffset / BITS_PER_WORD ; unsigned int regno = data -> regbase + this_slotno ; intoffset /= BITS_PER_UNIT ; do { rtx reg = gen_rtx_REG ( mode , regno ) ; XVECEXP ( data -> ret , 0 , data -> stack + data -> nregs ) = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( intoffset ) ) ; data -> nregs += 1 ; mode = word_mode ; regno += 1 ; intoffset = ( intoffset | ( UNITS_PER_WORD - 1 ) ) + 1 ; } while ( -- nregs > 0 ) ; } </s>

A subroutine of function_arg_record_value . Assign the bits of the structure between PARMS- > intoffset and BITPOS to integer registers .


<s> bool PPCInstrInfo :: ClobbersPredicate ( MachineInstr & MI , std :: vector < MachineOperand > & Pred , bool SkipDead ) const { const TargetRegisterClass * RCs [ ] = { & PPC :: CRRCRegClass , & PPC :: CRBITRCRegClass , & PPC :: CTRRCRegClass , & PPC :: CTRRC8RegClass } ; bool Found = false ; for ( const MachineOperand & MO : MI . operands ( ) ) { for ( unsigned c = 0 ; c < array_lengthof ( RCs ) && ! Found ; ++ c ) { const TargetRegisterClass * RC = RCs [ c ] ; if ( MO . isReg ( ) ) { if ( MO . isDef ( ) && RC -> contains ( MO . getReg ( ) ) ) { Pred . push_back ( MO ) ; Found = true ; } } else if ( MO . isRegMask ( ) ) { for ( MCPhysReg R : * RC ) if ( MO . clobbersPhysReg ( R ) ) { Pred . push_back ( MO ) ; Found = true ; } } } } return Found ; } </s>

If the specified instruction defines any predicate or condition code register ( s ) used for predication , returns true as well as the definition predicate ( s ) by reference .

PowerPC PPC PPC::CRRCRegClass PPC::CRBITRCRegClass PPC::CTRRCRegClass PPC::CTRRC8RegClass 0


" Declaring this symbol tells the CRT that it should"

"copy all variables from program memory to RAM on startup"

"clear the zeroed data section on startup"

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> unsigned Nios2RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return Nios2 :: SP ; } </s>


"switch %<-mcpu=%s%> conflicts with %<-march=%s%> switch"

"assembler does not support %<-mabi=ilp32%>"

"return address signing is only supported for %<-mabi=lp64%>"


<s> static int frv_function_contains_far_jump ( void ) { rtx insn = get_insns ( ) ; while ( insn != NULL && ! ( GET_CODE ( insn ) == JUMP_INSN && GET_CODE ( PATTERN ( insn ) ) != ADDR_VEC && GET_CODE ( PATTERN ( insn ) ) != ADDR_DIFF_VEC && get_attr_far_jump ( insn ) == FAR_JUMP_YES ) ) insn = NEXT_INSN ( insn ) ; return ( insn != NULL ) ; } </s>

True if the current function contains a far jump .


<s> static int const_int_cost ( HOST_WIDE_INT i ) { switch ( m68k_const_method ( i ) ) { case MOVQ : return 0 ; case MVZ : case MVS : case NOTB : case NOTW : case NEGW : case SWAP : return 1 ; case MOVL : return 2 ; default : gcc_unreachable ( ) ; } } </s>

Return the cost of moving constant I into a data register .


<s>
static
int
m68hc11_address_cost
(
rtx
addr
)
{
int
cost
=
4
;
switch
(
GET_CODE
(
addr
)
)
{
case
REG
:
if
(
REGNO
(
addr
)
<
FIRST_PSEUDO_REGISTER
)
cost
=
0
;
else
cost
=
1
;
break
;
case
SYMBOL_REF
:
cost
=
8
;
break
;
case
LABEL_REF
:
case
CONST
:
cost
=
0
;
break
;
case
PLUS
:
{
register
rtx
plus0
=
XEXP
(
addr
,
0
)
;
register
rtx
plus1
=
XEXP
(
addr
,
1
)
;
if
(
GET_CODE
(
plus0
)
!=
REG
)
break
;
switch
(
GET_CODE
(
plus1
)
)
{
case
CONST_INT
:
if
(
INTVAL
(
plus1
)
>=
2
*
m68hc11_max_offset
||
INTVAL
(
plus1
)
<
m68hc11_min_offset
)
cost
=
3
;
else
if
(
INTVAL
(
plus1
)
>=
m68hc11_max_offset
)
cost
=
2
;
else
cost
=
1
;
if
(
REGNO
(
plus0
)
<
FIRST_PSEUDO_REGISTER
)
cost
+=
0
;
else
cost
+=
1
;
break
;
case
SYMBOL_REF
:
cost
=
8
;
break
;
case
CONST
:
case
LABEL_REF
:
cost
=
0
;
break
;
default
:
break
;
}
break
;
}
case
PRE_DEC
:
case
PRE_INC
:
if
(
SP_REG_P
(
XEXP
(
addr
,
0
)
)
)
cost
=
1
;
break
;
default
:
break
;
}
if
(
debug_m6811
)
{
printf
(
"Address cost: %d for :"
,
cost
)
;
fflush
(
stdout
)
;
debug_rtx
(
addr
)
;
}
return
cost
;
}
</s>

Provide the costs of an addressing mode that contains ADDR . If ADDR is not a valid address , its cost is irrelevant .


<s> bool aarch64_operands_ok_for_ldpstp ( rtx * operands , bool load , machine_mode mode ) { HOST_WIDE_INT offval_1 , offval_2 , msize ; enum reg_class rclass_1 , rclass_2 ; rtx mem_1 , mem_2 , reg_1 , reg_2 , base_1 , base_2 , offset_1 , offset_2 ; if ( load ) { mem_1 = operands [ 1 ] ; mem_2 = operands [ 3 ] ; reg_1 = operands [ 0 ] ; reg_2 = operands [ 2 ] ; gcc_assert ( REG_P ( reg_1 ) && REG_P ( reg_2 ) ) ; if ( REGNO ( reg_1 ) == REGNO ( reg_2 ) ) return false ; } else { mem_1 = operands [ 0 ] ; mem_2 = operands [ 2 ] ; reg_1 = operands [ 1 ] ; reg_2 = operands [ 3 ] ; } if ( MEM_VOLATILE_P ( mem_1 ) || MEM_VOLATILE_P ( mem_2 ) ) return false ; if ( mode == SImode && ( aarch64_tune_params . extra_tuning_flags & AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW ) && ! optimize_size && MEM_ALIGN ( mem_1 ) < 8 * BITS_PER_UNIT ) return false ; extract_base_offset_in_addr ( mem_1 , & base_1 , & offset_1 ) ; if ( base_1 == NULL_RTX || offset_1 == NULL_RTX ) return false ; extract_base_offset_in_addr ( mem_2 , & base_2 , & offset_2 ) ; if ( base_2 == NULL_RTX || offset_2 == NULL_RTX ) return false ; if ( ! rtx_equal_p ( base_1 , base_2 ) ) return false ; gcc_assert ( known_eq ( GET_MODE_SIZE ( GET_MODE ( mem_1 ) ) , GET_MODE_SIZE ( GET_MODE ( mem_2 ) ) ) ) ; offval_1 = INTVAL ( offset_1 ) ; offval_2 = INTVAL ( offset_2 ) ; msize = GET_MODE_SIZE ( mode ) . to_constant ( ) ; if ( offval_1 != ( offval_2 + msize ) && offval_2 != ( offval_1 + msize ) ) return false ; if ( load ) { if ( reg_mentioned_p ( reg_1 , mem_1 ) ) return false ; if ( offval_1 > offval_2 && reg_mentioned_p ( reg_2 , mem_2 ) ) return false ; } if ( ! aarch64_mem_pair_operand ( mem_1 , GET_MODE ( mem_1 ) ) && ! aarch64_mem_pair_operand ( mem_2 , GET_MODE ( mem_2 ) ) ) return false ; if ( REG_P ( reg_1 ) && FP_REGNUM_P ( REGNO ( reg_1 ) ) ) rclass_1 = FP_REGS ; else rclass_1 = GENERAL_REGS ; if ( REG_P ( reg_2 ) && FP_REGNUM_P ( REGNO ( reg_2 ) ) ) rclass_2 = FP_REGS ; else rclass_2 = GENERAL_REGS ; if ( rclass_1 != rclass_2 ) return false ; return true ; } </s>

Given OPERANDS of consecutive load/store , check if we can merge them into ldp/stp . LOAD is true if they are load instructions . MODE is the mode of memory operands .


<s> static void print_address_offset ( FILE * file , rtx off , machine_mode mem_mode ) { rtx pat ; if ( c6x_current_insn != NULL_RTX ) { pat = PATTERN ( c6x_current_insn ) ; if ( GET_CODE ( pat ) == COND_EXEC ) pat = COND_EXEC_CODE ( pat ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , 0 , 0 ) ; if ( GET_CODE ( pat ) == SET && GET_CODE ( SET_SRC ( pat ) ) == UNSPEC && XINT ( SET_SRC ( pat ) , 1 ) == UNSPEC_MISALIGNED_ACCESS ) { gcc_assert ( CONST_INT_P ( off ) && ( INTVAL ( off ) & ( GET_MODE_SIZE ( mem_mode ) - 1 ) ) == 0 ) ; fprintf ( file , "[" HOST_WIDE_INT_PRINT_DEC "]" , INTVAL ( off ) / GET_MODE_SIZE ( mem_mode ) ) ; return ; } } fputs ( "(" , file ) ; output_address ( mem_mode , off ) ; fputs ( ")" , file ) ; } </s>

Subroutine of print_address_operand , print a single address offset OFF for a memory access of mode MEM_MODE , choosing between normal form and scaled form depending on the type of the insn . Misaligned memory references must use the scaled form .


<s>
bool
NVPTXAsmPrinter
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
{
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
MCOp
=
MCOperand
::
createReg
(
encodeVirtualRegister
(
MO
.
getReg
(
)
)
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
createImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
createExpr
(
MCSymbolRefExpr
::
create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
OutContext
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
GetSymbolRef
(
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
GetSymbolRef
(
getSymbol
(
MO
.
getGlobal
(
)
)
)
;
break
;
case
MachineOperand
::
MO_FPImmediate
:
{
const
ConstantFP
*
Cnt
=
MO
.
getFPImm
(
)
;
const
APFloat
&
Val
=
Cnt
->
getValueAPF
(
)
;
switch
(
Cnt
->
getType
(
)
->
getTypeID
(
)
)
{
default
:
report_fatal_error
(
"Unsupported FP type"
)
;
break
;
case
Type
::
HalfTyID
:
MCOp
=
MCOperand
::
createExpr
(
NVPTXFloatMCExpr
::
createConstantFPHalf
(
Val
,
OutContext
)
)
;
break
;
case
Type
::
FloatTyID
:
MCOp
=
MCOperand
::
createExpr
(
NVPTXFloatMCExpr
::
createConstantFPSingle
(
Val
,
OutContext
)
)
;
break
;
case
Type
::
DoubleTyID
:
MCOp
=
MCOperand
::
createExpr
(
NVPTXFloatMCExpr
::
createConstantFPDouble
(
Val
,
OutContext
)
)
;
break
;
}
break
;
}
}
return
true
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .

NVPTX
NVPTX
"unknown operand type"
"Unsupported FP type"
NVPTX
NVPTX
NVPTX


<s>
bool
ARM64DAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
char
ConstraintCode
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
assert
(
ConstraintCode
==
'm'
&&
"unexpected asm memory constraint"
)
;
OutOps
.
push_back
(
Op
)
;
return
false
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> const char * mcore_output_bclri ( rtx dst , int mask ) { rtx out_operands [ 2 ] ; int bit ; out_operands [ 0 ] = dst ; for ( bit = 0 ; bit < 32 ; bit ++ ) { if ( ( mask & 0x1 ) == 0x0 ) { out_operands [ 1 ] = GEN_INT ( bit ) ; output_asm_insn ( "bclri\t%0,%1" , out_operands ) ; } mask >>= 1 ; } return "" ; } </s>

Output a series of bclri 's corresponding to mask .


<s> bool arm_expand_vec_perm_const ( rtx target , rtx op0 , rtx op1 , rtx sel ) { struct expand_vec_perm_d d ; int i , nelt , which ; d . target = target ; d . op0 = op0 ; d . op1 = op1 ; d . vmode = GET_MODE ( target ) ; gcc_assert ( VECTOR_MODE_P ( d . vmode ) ) ; d . nelt = nelt = GET_MODE_NUNITS ( d . vmode ) ; d . testing_p = false ; for ( i = which = 0 ; i < nelt ; ++ i ) { rtx e = XVECEXP ( sel , 0 , i ) ; int ei = INTVAL ( e ) & ( 2 * nelt - 1 ) ; which |= ( ei < nelt ? 1 : 2 ) ; d . perm [ i ] = ei ; } switch ( which ) { default : gcc_unreachable ( ) ; case 3 : d . one_vector_p = false ; if ( ! rtx_equal_p ( op0 , op1 ) ) break ; case 2 : for ( i = 0 ; i < nelt ; ++ i ) d . perm [ i ] &= nelt - 1 ; d . op0 = op1 ; d . one_vector_p = true ; break ; case 1 : d . op1 = op0 ; d . one_vector_p = true ; break ; } return arm_expand_vec_perm_const_1 ( & d ) ; } </s>


<s> TargetLoweringBase :: LegalizeTypeAction NVPTXTargetLowering :: getPreferredVectorAction ( MVT VT ) const { if ( ! VT . isScalableVector ( ) && VT . getVectorNumElements ( ) != 1 && VT . getScalarType ( ) == MVT :: i1 ) return TypeSplitVector ; if ( VT == MVT :: v2f16 ) return TypeLegal ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s> static const uint16_t * lookup ( unsigned opcode , unsigned domain , ArrayRef < uint16_t [ 3 ] > Table ) { for ( const uint16_t ( & Row ) [ 3 ] : Table ) if ( Row [ domain - 1 ] == opcode ) return Row ; return nullptr ; } </s>

This method finds the value with the given Name in the the symbol table .


<s> bool SITargetLowering :: isFMAFasterThanFMulAndFAdd ( EVT VT ) const { VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f32 : return Subtarget -> hasFP32Denormals ( ) && Subtarget -> hasFastFMAF32 ( ) ; case MVT :: f64 : return true ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


"Cannot store this register into a stack slot!"

Store the specified register of the given register class to the specified stack frame index .


<s> static rtx restore_gprs ( rtx base , int offset , int first , int last ) { rtx addr , insn ; addr = plus_constant ( base , offset ) ; addr = gen_rtx_MEM ( Pmode , addr ) ; set_mem_alias_set ( addr , get_frame_alias_set ( ) ) ; if ( first == last ) { if ( TARGET_64BIT ) insn = gen_movdi ( gen_rtx_REG ( Pmode , first ) , addr ) ; else insn = gen_movsi ( gen_rtx_REG ( Pmode , first ) , addr ) ; return insn ; } insn = gen_load_multiple ( gen_rtx_REG ( Pmode , first ) , addr , GEN_INT ( last - first + 1 ) ) ; return insn ; } </s>

Generate insn to restore registers FIRST to LAST from the register save area located at offset OFFSET relative to register BASE .


<s> void ix86_split_simple_return_pop_internal ( rtx popc ) { struct machine_function * m = cfun -> machine ; rtx ecx = gen_rtx_REG ( SImode , CX_REG ) ; rtx_insn * insn ; gcc_assert ( ! TARGET_64BIT ) ; insn = emit_insn ( gen_pop ( ecx ) ) ; m -> fs . cfa_offset -= UNITS_PER_WORD ; m -> fs . sp_offset -= UNITS_PER_WORD ; rtx x = plus_constant ( Pmode , stack_pointer_rtx , UNITS_PER_WORD ) ; x = gen_rtx_SET ( stack_pointer_rtx , x ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , x ) ; add_reg_note ( insn , REG_CFA_REGISTER , gen_rtx_SET ( ecx , pc_rtx ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; x = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , popc ) ; x = gen_rtx_SET ( stack_pointer_rtx , x ) ; insn = emit_insn ( x ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , x ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; emit_jump_insn ( gen_simple_return_indirect_internal ( ecx ) ) ; } </s>

Split simple return with popping POPC bytes from stack to indirect branch with stack adjustment .


<s> void SparcTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { SDValue Result ( nullptr , 0 ) ; if ( Constraint . length ( ) > 1 ) return ; char ConstraintLetter = Constraint [ 0 ] ; switch ( ConstraintLetter ) { default : break ; case 'I' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isInt < 13 > ( C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , Op . getValueType ( ) ) ; break ; } return ; } } if ( Result . getNode ( ) ) { Ops . push_back ( Result ) ; return ; } TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; } </s>

Lower the specified operand into the Ops vector .


<s> void BPFAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { BPFMCInstLower MCInstLowering ( OutContext , * this ) ; MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( OutStreamer , TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool MipsSEInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock & MBB = * MI -> getParent ( ) ; switch ( MI -> getDesc ( ) . getOpcode ( ) ) { default : return false ; case Mips :: RetRA : expandRetRA ( MBB , MI , Mips :: RET ) ; break ; case Mips :: PseudoCVT_S_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_D32_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_D32_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_S_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_L , Mips :: DMTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_W , Mips :: MTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_L , Mips :: DMTC1 , true ) ; break ; case Mips :: BuildPairF64 : expandBuildPairF64 ( MBB , MI ) ; break ; case Mips :: ExtractElementF64 : expandExtractElementF64 ( MBB , MI ) ; break ; case Mips :: PseudoLDC1 : expandDPLoadStore ( MBB , MI , Mips :: LDC1 , Mips :: LWC1 ) ; break ; case Mips :: PseudoSDC1 : expandDPLoadStore ( MBB , MI , Mips :: SDC1 , Mips :: SWC1 ) ; break ; case Mips :: MIPSeh_return32 : case Mips :: MIPSeh_return64 : expandEhReturn ( MBB , MI ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> bool AMDGPUCodeGenPrepare :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; const AMDGPUTargetMachine & TM = TPC -> getTM < AMDGPUTargetMachine > ( ) ; ST = & TM . getSubtarget < SISubtarget > ( F ) ; DA = & getAnalysis < DivergenceAnalysis > ( ) ; HasUnsafeFPMath = hasUnsafeFPMath ( F ) ; AMDGPUASI = TM . getAMDGPUAS ( ) ; bool MadeChange = false ; for ( BasicBlock & BB : F ) { BasicBlock :: iterator Next ; for ( BasicBlock :: iterator I = BB . begin ( ) , E = BB . end ( ) ; I != E ; I = Next ) { Next = std :: next ( I ) ; MadeChange |= visit ( * I ) ; } } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .

AMDGPU AMDGPU AMDGPU AMDGPU SI SI AMDGPU


<s> static bool cortexa7_older_only ( rtx_insn * insn ) { if ( recog_memoized ( insn ) < 0 ) return false ; switch ( get_attr_type ( insn ) ) { case TYPE_ALU_DSP_REG : case TYPE_ALU_SREG : case TYPE_ALUS_SREG : case TYPE_LOGIC_REG : case TYPE_LOGICS_REG : case TYPE_ADC_REG : case TYPE_ADCS_REG : case TYPE_ADR : case TYPE_BFM : case TYPE_REV : case TYPE_MVN_REG : case TYPE_SHIFT_IMM : case TYPE_SHIFT_REG : case TYPE_LOAD_BYTE : case TYPE_LOAD1 : case TYPE_STORE1 : case TYPE_FFARITHS : case TYPE_FADDS : case TYPE_FFARITHD : case TYPE_FADDD : case TYPE_FMOV : case TYPE_F_CVT : case TYPE_FCMPS : case TYPE_FCMPD : case TYPE_FCONSTS : case TYPE_FCONSTD : case TYPE_FMULS : case TYPE_FMACS : case TYPE_FMULD : case TYPE_FMACD : case TYPE_FDIVS : case TYPE_FDIVD : case TYPE_F_MRC : case TYPE_F_MRRC : case TYPE_F_FLAG : case TYPE_F_LOADS : case TYPE_F_STORES : return true ; default : return false ; } } </s>

Return true if and only if this insn can dual-issue only as older .


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: AND : return LowerANDOR ( Op , DAG ) ; case ISD :: BRCOND : return LowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return LowerConstantPool ( Op , DAG ) ; case ISD :: DYNAMIC_STACKALLOC : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case ISD :: FP_TO_SINT : return LowerFP_TO_SINT ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return LowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( Op , DAG ) ; case ISD :: OR : return LowerANDOR ( Op , DAG ) ; case ISD :: SELECT : return LowerSELECT ( Op , DAG ) ; case ISD :: SETCC : return LowerSETCC ( Op , DAG ) ; case ISD :: VASTART : return LowerVASTART ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::AND ISD::BRCOND ISD::ConstantPool ISD::DYNAMIC_STACKALLOC ISD::FP_TO_SINT ISD::GlobalAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::OR ISD::SELECT ISD::SETCC ISD::VASTART


<s> bool X86FastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { const Value * Ptr = LI -> getPointerOperand ( ) ; X86AddressMode AM ; if ( ! X86SelectAddress ( Ptr , AM ) ) return false ; const X86InstrInfo & XII = ( const X86InstrInfo & ) TII ; unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; unsigned Alignment = LI -> getAlignment ( ) ; if ( Alignment == 0 ) Alignment = DL . getABITypeAlignment ( LI -> getType ( ) ) ; SmallVector < MachineOperand , 8 > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , * MI , OpNo , AddrOps , FuncInfo . InsertPt , Size , Alignment , true ) ; if ( ! Result ) return false ; unsigned OperandNo = 0 ; for ( MachineInstr :: mop_iterator I = Result -> operands_begin ( ) , E = Result -> operands_end ( ) ; I != E ; ++ I , ++ OperandNo ) { MachineOperand & MO = * I ; if ( ! MO . isReg ( ) || MO . isDef ( ) || MO . getReg ( ) != AM . IndexReg ) continue ; unsigned IndexReg = constrainOperandRegClass ( Result -> getDesc ( ) , MO . getReg ( ) , OperandNo ) ; if ( IndexReg == MO . getReg ( ) ) continue ; MO . setReg ( IndexReg ) ; } Result -> addMemOperand ( * FuncInfo . MF , createMachineMemOperandFor ( LI ) ) ; Result -> cloneInstrSymbols ( * FuncInfo . MF , * MI ) ; MachineBasicBlock :: iterator I ( MI ) ; removeDeadCode ( I , std :: next ( I ) ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> void SITargetLowering :: AdjustInstrPostInstrSelection ( MachineInstr * MI , SDNode * Node ) const { const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; if ( TII -> isVOP3 ( MI -> getOpcode ( ) ) ) { TII -> legalizeOperandsVOP3 ( MRI , MI ) ; return ; } if ( TII -> isMIMG ( * MI ) ) { unsigned VReg = MI -> getOperand ( 0 ) . getReg ( ) ; unsigned DmaskIdx = MI -> getNumOperands ( ) == 12 ? 3 : 4 ; unsigned Writemask = MI -> getOperand ( DmaskIdx ) . getImm ( ) ; unsigned BitsSet = 0 ; for ( unsigned i = 0 ; i < 4 ; ++ i ) BitsSet += Writemask & ( 1 << i ) ? 1 : 0 ; const TargetRegisterClass * RC ; switch ( BitsSet ) { default : return ; case 1 : RC = & AMDGPU :: VGPR_32RegClass ; break ; case 2 : RC = & AMDGPU :: VReg_64RegClass ; break ; case 3 : RC = & AMDGPU :: VReg_96RegClass ; break ; } unsigned NewOpcode = TII -> getMaskedMIMGOp ( MI -> getOpcode ( ) , BitsSet ) ; MI -> setDesc ( TII -> get ( NewOpcode ) ) ; MRI . setRegClass ( VReg , RC ) ; return ; } int NoRetAtomicOp = AMDGPU :: getAtomicNoRetOp ( MI -> getOpcode ( ) ) ; if ( NoRetAtomicOp != - 1 ) { if ( ! Node -> hasAnyUseOfValue ( 0 ) ) { MI -> setDesc ( TII -> get ( NoRetAtomicOp ) ) ; MI -> RemoveOperand ( 0 ) ; return ; } if ( ( Node -> hasNUsesOfValue ( 1 , 0 ) && Node -> use_begin ( ) -> isMachineOpcode ( ) && Node -> use_begin ( ) -> getMachineOpcode ( ) == AMDGPU :: EXTRACT_SUBREG && ! Node -> use_begin ( ) -> hasAnyUseOfValue ( 0 ) ) ) { unsigned Def = MI -> getOperand ( 0 ) . getReg ( ) ; MI -> setDesc ( TII -> get ( NoRetAtomicOp ) ) ; MI -> RemoveOperand ( 0 ) ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , TII -> get ( AMDGPU :: IMPLICIT_DEF ) , Def ) ; } return ; } } </s>

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


<s>
void
ConvergingVLIWScheduler
::
releaseBottomNode
(
SUnit
*
SU
)
{
assert
(
SU
->
getInstr
(
)
&&
"Scheduled SUnit must have instr"
)
;
for
(
SUnit
::
succ_iterator
I
=
SU
->
Succs
.
begin
(
)
,
E
=
SU
->
Succs
.
end
(
)
;
I
!=
E
;
++
I
)
{
unsigned
SuccReadyCycle
=
I
->
getSUnit
(
)
->
BotReadyCycle
;
unsigned
MinLatency
=
I
->
getLatency
(
)
;
Bot
.
MaxMinLatency
=
std
::
max
(
MinLatency
,
Bot
.
MaxMinLatency
)
;
if
(
SU
->
BotReadyCycle
<
SuccReadyCycle
+
MinLatency
)
SU
->
BotReadyCycle
=
SuccReadyCycle
+
MinLatency
;
}
if
(
!
SU
->
isScheduled
)
Bot
.
releaseNode
(
SU
,
SU
->
BotReadyCycle
)
;
}
</s>

Currently only scheduling top-down , so this method is empty .

Hexagon
"Scheduled SUnit must have instr"


<s> bool MipsTargetObjectFile :: IsConstantInSmallSection ( const Constant * CN , const TargetMachine & TM ) const { return ( TM . getSubtarget < MipsSubtarget > ( ) . useSmallSection ( ) && LocalSData && IsInSmallSection ( TM . getDataLayout ( ) -> getTypeAllocSize ( CN -> getType ( ) ) ) ) ; } </s>

Return true if this constant should be placed into small data section .


"instruction use requires an option to be enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> bool m16_based_address_p ( rtx x , machine_mode mode , insn_operand_predicate_fn offset_predicate ) { struct mips_address_info addr ; return ( mips_classify_address ( & addr , x , mode , false ) && addr . type == ADDRESS_REG && M16_REG_P ( REGNO ( addr . reg ) ) && offset_predicate ( addr . offset , mode ) ) ; } </s>

Return true if X is legitimate for accessing values of mode MODE , if it is based on a MIPS16 register , and if the offset satisfies OFFSET_PREDICATE .


<s> void SystemZInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & O ) { printInstruction ( MI , Address , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> SITargetLowering :: ConstraintType SITargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 's' : case 'v' : return C_RegisterClass ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> static rtx riscv_legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , machine_mode mode ) { rtx addr ; if ( riscv_tls_symbol_p ( x ) ) return riscv_legitimize_tls_address ( x ) ; if ( riscv_split_symbol ( NULL , x , mode , & addr ) ) return riscv_force_address ( addr , mode ) ; if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , 1 ) ) && INTVAL ( XEXP ( x , 1 ) ) != 0 ) { rtx base = XEXP ( x , 0 ) ; HOST_WIDE_INT offset = INTVAL ( XEXP ( x , 1 ) ) ; if ( ! riscv_valid_base_register_p ( base , mode , false ) ) base = copy_to_mode_reg ( Pmode , base ) ; addr = riscv_add_offset ( NULL , base , offset ) ; return riscv_force_address ( addr , mode ) ; } return x ; } </s>

This function is used to implement LEGITIMIZE_ADDRESS . If X can be legitimized in a way that the generic machinery might not expect , return a new address , otherwise return NULL . MODE is the mode of the memory being accessed .


<s> void ARMTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , APInt & KnownZero , APInt & KnownOne , const SelectionDAG & DAG , unsigned Depth ) const { unsigned BitWidth = KnownOne . getBitWidth ( ) ; KnownZero = KnownOne = APInt ( BitWidth , 0 ) ; switch ( Op . getOpcode ( ) ) { default : break ; case ARMISD :: ADDC : case ARMISD :: ADDE : case ARMISD :: SUBC : case ARMISD :: SUBE : if ( Op . getResNo ( ) == 0 ) break ; KnownZero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - 1 ) ; break ; case ARMISD :: CMOV : { DAG . computeKnownBits ( Op . getOperand ( 0 ) , KnownZero , KnownOne , Depth + 1 ) ; if ( KnownZero == 0 && KnownOne == 0 ) return ; APInt KnownZeroRHS , KnownOneRHS ; DAG . computeKnownBits ( Op . getOperand ( 1 ) , KnownZeroRHS , KnownOneRHS , Depth + 1 ) ; KnownZero &= KnownZeroRHS ; KnownOne &= KnownOneRHS ; return ; } case ISD :: INTRINSIC_W_CHAIN : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ; Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case Intrinsic :: arm_ldaex : case Intrinsic :: arm_ldrex : { EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; KnownZero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } } } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> void output_profile_hook ( int labelno ATTRIBUTE_UNUSED ) { if ( TARGET_PROFILE_KERNEL ) return ; if ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) { if ( NO_PROFILE_COUNTERS ) emit_library_call ( init_one_libfunc ( RS6000_MCOUNT ) , LCT_NORMAL , VOIDmode , 0 ) ; else { char buf [ 30 ] ; const char * label_name ; rtx fun ; ASM_GENERATE_INTERNAL_LABEL ( buf , "LP" , labelno ) ; label_name = ggc_strdup ( ( * targetm . strip_name_encoding ) ( buf ) ) ; fun = gen_rtx_SYMBOL_REF ( Pmode , label_name ) ; emit_library_call ( init_one_libfunc ( RS6000_MCOUNT ) , LCT_NORMAL , VOIDmode , 1 , fun , Pmode ) ; } } else if ( DEFAULT_ABI == ABI_DARWIN ) { const char * mcount_name = RS6000_MCOUNT ; int caller_addr_regno = LR_REGNO ; crtl -> uses_pic_offset_table = 1 ; if ( MACHOPIC_INDIRECT && crtl -> uses_pic_offset_table ) caller_addr_regno = 0 ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , mcount_name ) , LCT_NORMAL , VOIDmode , 1 , gen_rtx_REG ( Pmode , caller_addr_regno ) , Pmode ) ; } } </s>


<s> static bool riscv_symbol_binds_local_p ( const_rtx x ) { if ( SYMBOL_REF_P ( x ) ) return ( SYMBOL_REF_DECL ( x ) ? targetm . binds_local_p ( SYMBOL_REF_DECL ( x ) ) : SYMBOL_REF_LOCAL_P ( x ) ) ; else return false ; } </s>


<s> static void frv_output_const_unspec ( FILE * stream , const struct frv_unspec * unspec ) { fprintf ( stream , "#%s(" , unspec_got_name ( unspec -> reloc ) ) ; output_addr_const ( stream , plus_constant ( Pmode , unspec -> symbol , unspec -> offset ) ) ; fputs ( ")" , stream ) ; } </s>

Write the assembler syntax for UNSPEC to STREAM . Note that any offset is added inside the relocation operator .


<s> virtual const SparcInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> void X86PassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createExecutionDependencyFixPass ( & X86 :: VR128XRegClass ) ) ; if ( UseVZeroUpper ) addPass ( createX86IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86FixupBWInsts ( ) ) ; addPass ( createX86PadShortFunctions ( ) ) ; addPass ( createX86FixupLEAs ( ) ) ; addPass ( createX86EvexToVexInsts ( ) ) ; } } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


"Only 24-bit should have 3 byte stack slots"

Load the specified register of the given register class from the specified stack frame index .


<s>
bool
SSEDomainFixPass
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
MF
=
&
mf
;
TII
=
static_cast
<
const
X86InstrInfo
*
>
(
MF
->
getTarget
(
)
.
getInstrInfo
(
)
)
;
TRI
=
MF
->
getTarget
(
)
.
getRegisterInfo
(
)
;
MBB
=
0
;
LiveRegs
=
0
;
Distance
=
0
;
assert
(
NumRegs
==
X86
::
VR128RegClass
.
getNumRegs
(
)
&&
"Bad regclass"
)
;
bool
anyregs
=
false
;
for
(
TargetRegisterClass
::
const_iterator
I
=
X86
::
VR128RegClass
.
begin
(
)
,
E
=
X86
::
VR128RegClass
.
end
(
)
;
I
!=
E
;
++
I
)
if
(
MF
->
getRegInfo
(
)
.
isPhysRegUsed
(
*
I
)
)
{
anyregs
=
true
;
break
;
}
if
(
!
anyregs
)
return
false
;
MachineBasicBlock
*
Entry
=
MF
->
begin
(
)
;
SmallPtrSet
<
MachineBasicBlock
*
,
16
>
Visited
;
for
(
df_ext_iterator
<
MachineBasicBlock
*
,
SmallPtrSet
<
MachineBasicBlock
*
,
16
>
>
DFI
=
df_ext_begin
(
Entry
,
Visited
)
,
DFE
=
df_ext_end
(
Entry
,
Visited
)
;
DFI
!=
DFE
;
++
DFI
)
{
MBB
=
*
DFI
;
enterBasicBlock
(
)
;
for
(
MachineBasicBlock
::
iterator
I
=
MBB
->
begin
(
)
,
E
=
MBB
->
end
(
)
;
I
!=
E
;
++
I
)
{
MachineInstr
*
mi
=
I
;
if
(
mi
->
isDebugValue
(
)
)
continue
;
++
Distance
;
std
::
pair
<
uint16_t
,
uint16_t
>
domp
=
TII
->
GetSSEDomain
(
mi
)
;
if
(
domp
.
first
)
if
(
domp
.
second
)
visitSoftInstr
(
mi
,
domp
.
second
)
;
else
visitHardInstr
(
mi
,
domp
.
first
)
;
else
if
(
LiveRegs
)
visitGenericInstr
(
mi
)
;
}
if
(
LiveRegs
)
LiveOuts
.
insert
(
std
::
make_pair
(
MBB
,
LiveRegs
)
)
;
LiveRegs
=
0
;
}
for
(
LiveOutMap
::
const_iterator
i
=
LiveOuts
.
begin
(
)
,
e
=
LiveOuts
.
end
(
)
;
i
!=
e
;
++
i
)
delete
[
]
i
->
second
;
LiveOuts
.
clear
(
)
;
Avail
.
clear
(
)
;
Allocator
.
DestroyAll
(
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static enum insn_path get_insn_path ( rtx_insn * insn ) { enum attr_amdfam10_decode path = get_attr_amdfam10_decode ( insn ) ; if ( ( int ) path == 0 ) return path_single ; if ( ( int ) path == 1 ) return path_double ; return path_multi ; } </s>

Return single or double path for instructions .


<s> static inline TOCKey getTombstoneKey ( ) { return { nullptr , MCSymbolRefExpr :: VariantKind :: VK_Invalid } ; } </s>

Difference in tombstone is that the Optional is meaningful .


<s> void HexagonTTIImpl :: getUnrollingPreferences ( Loop * L , TTI :: UnrollingPreferences & UP ) { UP . Runtime = UP . Partial = true ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> unsigned BPFMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) return MRI . getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; assert ( MO . isExpr ( ) ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; assert ( Kind == MCExpr :: SymbolRef ) ; if ( MI . getOpcode ( ) == BPF :: JAL ) Fixups . push_back ( MCFixup :: Create ( 0 , Expr , FK_SecRel_4 ) ) ; else if ( MI . getOpcode ( ) == BPF :: LD_imm64 ) Fixups . push_back ( MCFixup :: Create ( 0 , Expr , FK_SecRel_8 ) ) ; else Fixups . push_back ( MCFixup :: Create ( 0 , Expr , FK_PCRel_2 ) ) ; return 0 ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s>
void
DarwinARMAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
Value
=
adjustFixupValue
(
Fixup
,
Value
)
;
if
(
!
Value
)
return
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> uint64_t evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size ) const { if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ 0 ] . OperandType != MCOI :: OPERAND_PCREL ) return - 1ULL ; int64_t Imm = Inst . getOperand ( 0 ) . getImm ( ) ; return Addr + Imm + 8 ; } </s>

Given a branch instruction try to get the address the branch targets .


"Do not know how to lower this BUILD_VECTOR"

Main hook for targets to transform nodes into machine nodes .


<s> bool mips_expand_block_move ( rtx dest , rtx src , rtx length ) { if ( GET_CODE ( length ) == CONST_INT ) { if ( INTVAL ( length ) <= 2 * MAX_MOVE_BYTES ) { mips_block_move_straight ( dest , src , INTVAL ( length ) ) ; return true ; } else if ( optimize ) { mips_block_move_loop ( dest , src , INTVAL ( length ) ) ; return true ; } } return false ; } </s>

Expand a movmemsi instruction , which copies LENGTH bytes from memory reference SRC to memory reference DEST .


<s> MCSection * getNonexecutableStackSection ( MCContext & Ctx ) const override { return nullptr ; } </s>

Targets can implement this method to specify a section to switch to if the translation unit does n't have any trampolines that require an executable stack .


<s> void Mips16InstrInfo :: adjustStackPtr ( unsigned SP , int64_t Amount , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( Amount == 0 ) return ; if ( isInt < 16 > ( Amount ) ) BuildAddiuSpImm ( MBB , I , Amount ) ; else adjustStackPtrBigUnrestricted ( SP , Amount , MBB , I ) ; } </s>


Output assembly code for a specific branch instruction , appending the branch prediction flag to the opcode if appropriate .


<s> int arm_count_ldrdstrd_insns ( rtx * operands , bool load ) { int count ; rtx ops [ 2 ] ; int regnum , memnum ; if ( load ) regnum = 0 , memnum = 1 ; else regnum = 1 , memnum = 0 ; ops [ regnum ] = gen_rtx_REG ( DImode , REGNO ( operands [ 0 ] ) ) ; ops [ memnum ] = adjust_address ( operands [ 2 ] , DImode , 0 ) ; output_move_double ( ops , false , & count ) ; return count ; } </s>

Same as above , but operands are a register/memory pair in SImode . Assumes operands has the base register in position 0 and memory in position 2 ( which is the order provided by the arm_ { ldrd , strd } patterns ) .


<s> bool forceScalarizeMaskedGather ( VectorType * VTy , Align Alignment ) { return true ; } </s>

Return true if the target forces scalarizing of llvm.masked.gather intrinsics .


<s> bool TeakFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TeakSubtarget & STI = MF . getSubtarget < TeakSubtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( unsigned i = 0 ; i < CSI . size ( ) ; i ++ ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ; if ( IsNotLiveIn ) MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( Teak :: PUSH_regnob16 ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .

Teak Teak Teak Teak 0 Teak::PUSH_regnob16


<s> void RISCVInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { bool Res = false ; const MCInst * NewMI = MI ; MCInst UncompressedMI ; if ( ! NoAliases ) Res = uncompressInst ( UncompressedMI , * MI , MRI , STI ) ; if ( Res ) NewMI = const_cast < MCInst * > ( & UncompressedMI ) ; if ( NoAliases || ! printAliasInstr ( NewMI , STI , O ) ) printInstruction ( NewMI , STI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool HexagonGenInsert :: removeDeadCode ( MachineDomTreeNode * N ) { bool Changed = false ; for ( auto * DTN : children < MachineDomTreeNode * > ( N ) ) Changed |= removeDeadCode ( DTN ) ; MachineBasicBlock * B = N -> getBlock ( ) ; std :: vector < MachineInstr * > Instrs ; for ( MachineInstr & MI : llvm :: reverse ( * B ) ) Instrs . push_back ( & MI ) ; for ( MachineInstr * MI : Instrs ) { unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == TargetOpcode :: LIFETIME_START || Opc == TargetOpcode :: LIFETIME_END ) continue ; bool Store = false ; if ( MI -> isInlineAsm ( ) || ! MI -> isSafeToMove ( nullptr , Store ) ) continue ; bool AllDead = true ; SmallVector < unsigned , 2 > Regs ; for ( const MachineOperand & MO : MI -> operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; Register R = MO . getReg ( ) ; if ( ! R . isVirtual ( ) || ! MRI -> use_nodbg_empty ( R ) ) { AllDead = false ; break ; } Regs . push_back ( R ) ; } if ( ! AllDead ) continue ; B -> erase ( MI ) ; for ( unsigned I = 0 , N = Regs . size ( ) ; I != N ; ++ I ) MRI -> markUsesInDebugValueAsUndef ( Regs [ I ] ) ; Changed = true ; } return Changed ; } </s>

Remove all dead instructions between the I and E .


<s> unsigned AMDGPURegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return AMDGPU :: NoRegister ; } </s>


<s> void ix86_expand_vector_move_misalign ( enum machine_mode mode , rtx operands [ ] ) { rtx op0 , op1 , m ; op0 = operands [ 0 ] ; op1 = operands [ 1 ] ; if ( MEM_P ( op1 ) ) { if ( optimize_size ) { op0 = gen_lowpart ( V4SFmode , op0 ) ; op1 = gen_lowpart ( V4SFmode , op1 ) ; emit_insn ( gen_sse_movups ( op0 , op1 ) ) ; return ; } if ( TARGET_SSE2 && GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) { op0 = gen_lowpart ( V16QImode , op0 ) ; op1 = gen_lowpart ( V16QImode , op1 ) ; emit_insn ( gen_sse2_movdqu ( op0 , op1 ) ) ; return ; } if ( TARGET_SSE2 && mode == V2DFmode ) { rtx zero ; if ( TARGET_SSE_SPLIT_REGS ) { emit_insn ( gen_rtx_CLOBBER ( VOIDmode , op0 ) ) ; zero = op0 ; } else { zero = CONST0_RTX ( V2DFmode ) ; } m = adjust_address ( op1 , DFmode , 0 ) ; emit_insn ( gen_sse2_loadlpd ( op0 , zero , m ) ) ; m = adjust_address ( op1 , DFmode , 8 ) ; emit_insn ( gen_sse2_loadhpd ( op0 , op0 , m ) ) ; } else { if ( TARGET_SSE_PARTIAL_REG_DEPENDENCY ) emit_move_insn ( op0 , CONST0_RTX ( mode ) ) ; else emit_insn ( gen_rtx_CLOBBER ( VOIDmode , op0 ) ) ; if ( mode != V4SFmode ) op0 = gen_lowpart ( V4SFmode , op0 ) ; m = adjust_address ( op1 , V2SFmode , 0 ) ; emit_insn ( gen_sse_loadlps ( op0 , op0 , m ) ) ; m = adjust_address ( op1 , V2SFmode , 8 ) ; emit_insn ( gen_sse_loadhps ( op0 , op0 , m ) ) ; } } else if ( MEM_P ( op0 ) ) { if ( optimize_size ) { op0 = gen_lowpart ( V4SFmode , op0 ) ; op1 = gen_lowpart ( V4SFmode , op1 ) ; emit_insn ( gen_sse_movups ( op0 , op1 ) ) ; return ; } if ( TARGET_SSE2 && ! TARGET_SSE_TYPELESS_STORES && GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) { op0 = gen_lowpart ( V16QImode , op0 ) ; op1 = gen_lowpart ( V16QImode , op1 ) ; emit_insn ( gen_sse2_movdqu ( op0 , op1 ) ) ; return ; } if ( TARGET_SSE2 && mode == V2DFmode ) { m = adjust_address ( op0 , DFmode , 0 ) ; emit_insn ( gen_sse2_storelpd ( m , op1 ) ) ; m = adjust_address ( op0 , DFmode , 8 ) ; emit_insn ( gen_sse2_storehpd ( m , op1 ) ) ; } else { if ( mode != V4SFmode ) op1 = gen_lowpart ( V4SFmode , op1 ) ; m = adjust_address ( op0 , V2SFmode , 0 ) ; emit_insn ( gen_sse_storelps ( m , op1 ) ) ; m = adjust_address ( op0 , V2SFmode , 8 ) ; emit_insn ( gen_sse_storehps ( m , op1 ) ) ; } } else gcc_unreachable ( ) ; } </s>

Implement the movmisalign patterns for SSE . Non-SSE modes go straight to ix86_expand_vector_move .


<s>
SDValue
VETargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_VE
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
OutVal
=
OutVals
[
i
]
;
switch
(
VA
.
getLocInfo
(
)
)
{
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
SExt
:
OutVal
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
DL
,
VA
.
getLocVT
(
)
,
OutVal
)
;
break
;
case
CCValAssign
::
ZExt
:
OutVal
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
DL
,
VA
.
getLocVT
(
)
,
OutVal
)
;
break
;
case
CCValAssign
::
AExt
:
OutVal
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
DL
,
VA
.
getLocVT
(
)
,
OutVal
)
;
break
;
case
CCValAssign
::
BCvt
:
{
assert
(
VA
.
getLocVT
(
)
==
MVT
::
i64
)
;
assert
(
VA
.
getValVT
(
)
==
MVT
::
f32
)
;
SDValue
Undef
=
SDValue
(
DAG
.
getMachineNode
(
TargetOpcode
::
IMPLICIT_DEF
,
DL
,
MVT
::
i64
)
,
0
)
;
SDValue
Sub_f32
=
DAG
.
getTargetConstant
(
VE
::
sub_f32
,
DL
,
MVT
::
i32
)
;
OutVal
=
SDValue
(
DAG
.
getMachineNode
(
TargetOpcode
::
INSERT_SUBREG
,
DL
,
MVT
::
i64
,
Undef
,
OutVal
,
Sub_f32
)
,
0
)
;
break
;
}
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
}
assert
(
!
VA
.
needsCustom
(
)
&&
"Unexpected custom lowering"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
OutVal
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
VEISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> unsigned ARMBaseInstrInfo :: getInstrLatency ( const InstrItineraryData * ItinData , const MachineInstr & MI , unsigned * PredCost ) const { if ( MI . isCopyLike ( ) || MI . isInsertSubreg ( ) || MI . isRegSequence ( ) || MI . isImplicitDef ( ) ) return 1 ; if ( MI . isBundle ( ) ) { unsigned Latency = 0 ; MachineBasicBlock :: const_instr_iterator I = MI . getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI . getParent ( ) -> instr_end ( ) ; while ( ++ I != E && I -> isInsideBundle ( ) ) { if ( I -> getOpcode ( ) != ARM :: t2IT ) Latency += getInstrLatency ( ItinData , * I , PredCost ) ; } return Latency ; } const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( PredCost && ( MCID . isCall ( ) || ( MCID . hasImplicitDefOfPhysReg ( ARM :: CPSR ) && ! Subtarget . cheapPredicableCPSRDef ( ) ) ) ) { * PredCost = 1 ; } if ( ! ItinData ) return MI . mayLoad ( ) ? 3 : 1 ; unsigned Class = MCID . getSchedClass ( ) ; if ( ! ItinData -> isEmpty ( ) && ItinData -> getNumMicroOps ( Class ) < 0 ) return getNumMicroOps ( ItinData , MI ) ; unsigned Latency = ItinData -> getStageLatency ( Class ) ; unsigned DefAlign = MI . hasOneMemOperand ( ) ? ( * MI . memoperands_begin ( ) ) -> getAlign ( ) . value ( ) : 0 ; int Adj = adjustDefLatency ( Subtarget , MI , MCID , DefAlign ) ; if ( Adj >= 0 || ( int ) Latency > - Adj ) { return Latency + Adj ; } return Latency ; } </s>

Compute the instruction latency of a given instruction .


"switch %<-mcustom-%s%> conflicts with "

"call to %<__builtin_custom_%s%> conflicts with "

Register a custom code use , and signal error if a conflict was found .


"(zero_extract:SI %s\n\t\t\t (const_int 18)\n\t\t\t (const_int 0))"

"(zero_extract:SI %s\n\t\t\t (const_int 18)\n\t\t\t (const_int 18))"

"(sign_extract:SI %s\n\t\t\t (const_int 18)\n\t\t\t (const_int 0))"

"(sign_extract:SI %s\n\t\t\t (const_int 18)\n\t\t\t (const_int 18))"

"(lshiftrt:SI %s\n\t\t     (const_int 18))"

"(ashiftrt:SI %s\n\t\t     (const_int 18))"

Main program to convert flat files into built-in initialization code .

"(lshiftrt:SI %s\n\t\t     (const_int 18))"

"(ashiftrt:SI %s\n\t\t     (const_int 18))"


This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> void AArch64PassConfig :: addPreRegBankSelect ( ) { bool IsOptNone = getOptLevel ( ) == CodeGenOpt :: None ; if ( ! IsOptNone ) addPass ( createAArch64PostLegalizeCombiner ( IsOptNone ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before the register bank selection .


<s> Align getStackAlignment ( ) const { return Align ( 4 ) ; } </s>

Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget .


<s> void SISubtarget :: overrideSchedPolicy ( MachineSchedPolicy & Policy , unsigned NumRegionInstrs ) const { Policy . ShouldTrackPressure = true ; Policy . OnlyTopDown = false ; Policy . OnlyBottomUp = false ; if ( ! enableSIScheduler ( ) ) Policy . ShouldTrackLaneMasks = true ; } </s>

Override generic scheduling policy within a region .


<s> Register TPCRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return Register ( ) ; } </s>


<s>
unsigned
SITargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
SelectionDAG
&
DAG
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"m0"
,
AMDGPU
::
M0
)
.
Case
(
"exec"
,
AMDGPU
::
EXEC
)
.
Case
(
"exec_lo"
,
AMDGPU
::
EXEC_LO
)
.
Case
(
"exec_hi"
,
AMDGPU
::
EXEC_HI
)
.
Case
(
"flat_scratch"
,
AMDGPU
::
FLAT_SCR
)
.
Case
(
"flat_scratch_lo"
,
AMDGPU
::
FLAT_SCR_LO
)
.
Case
(
"flat_scratch_hi"
,
AMDGPU
::
FLAT_SCR_HI
)
.
Default
(
AMDGPU
::
NoRegister
)
;
if
(
Reg
==
AMDGPU
::
NoRegister
)
{
report_fatal_error
(
Twine
(
"invalid register name \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;
}
if
(
!
Subtarget
->
hasFlatScrRegister
(
)
&&
Subtarget
->
getRegisterInfo
(
)
->
regsOverlap
(
Reg
,
AMDGPU
::
FLAT_SCR
)
)
{
report_fatal_error
(
Twine
(
"invalid register \""
+
StringRef
(
RegName
)
+
"\" for subtarget."
)
)
;
}
switch
(
Reg
)
{
case
AMDGPU
::
M0
:
case
AMDGPU
::
EXEC_LO
:
case
AMDGPU
::
EXEC_HI
:
case
AMDGPU
::
FLAT_SCR_LO
:
case
AMDGPU
::
FLAT_SCR_HI
:
if
(
VT
.
getSizeInBits
(
)
==
32
)
return
Reg
;
break
;
case
AMDGPU
::
EXEC
:
case
AMDGPU
::
FLAT_SCR
:
if
(
VT
.
getSizeInBits
(
)
==
64
)
return
Reg
;
break
;
default
:
llvm_unreachable
(
"missing register type checking"
)
;
}
report_fatal_error
(
Twine
(
"invalid type for register \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;
}
</s>

Return the register ID of the name passed in .


<s> void xstormy16_print_operand_address ( FILE * file , rtx address ) { HOST_WIDE_INT offset ; int pre_dec , post_inc ; if ( GET_CODE ( address ) == CONST_INT ) { fprintf ( file , HOST_WIDE_INT_PRINT_DEC , INTVAL ( address ) & 0xFFFF ) ; return ; } if ( CONSTANT_P ( address ) || GET_CODE ( address ) == CODE_LABEL ) { output_addr_const ( file , address ) ; return ; } if ( GET_CODE ( address ) == PLUS ) { gcc_assert ( GET_CODE ( XEXP ( address , 1 ) ) == CONST_INT ) ; offset = INTVAL ( XEXP ( address , 1 ) ) ; address = XEXP ( address , 0 ) ; } else offset = 0 ; pre_dec = ( GET_CODE ( address ) == PRE_DEC ) ; post_inc = ( GET_CODE ( address ) == POST_INC ) ; if ( pre_dec || post_inc ) address = XEXP ( address , 0 ) ; gcc_assert ( GET_CODE ( address ) == REG ) ; fputc ( '(' , file ) ; if ( pre_dec ) fputs ( "--" , file ) ; fputs ( reg_names [ REGNO ( address ) ] , file ) ; if ( post_inc ) fputs ( "++" , file ) ; if ( offset != 0 ) fprintf ( file , "," HOST_WIDE_INT_PRINT_DEC , offset ) ; fputc ( ')' , file ) ; } </s>

Print a memory address as an operand to reference that memory location .


<s>
void
AArch64Operand
::
print
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
k_FPImm
:
OS
<<
"<fpimm "
<<
getFPImm
(
)
<<
"("
<<
AArch64_AM
::
getFPImmFloat
(
getFPImm
(
)
)
<<
") >"
;
break
;
case
k_Barrier
:
{
bool
Valid
;
StringRef
Name
=
AArch64DB
::
DBarrierMapper
(
)
.
toString
(
getBarrier
(
)
,
Valid
)
;
if
(
Valid
)
OS
<<
"<barrier "
<<
Name
<<
">"
;
else
OS
<<
"<barrier invalid #"
<<
getBarrier
(
)
<<
">"
;
break
;
}
case
k_Immediate
:
getImm
(
)
->
print
(
OS
)
;
break
;
case
k_ShiftedImm
:
{
unsigned
Shift
=
getShiftedImmShift
(
)
;
OS
<<
"<shiftedimm "
;
getShiftedImmVal
(
)
->
print
(
OS
)
;
OS
<<
", lsl #"
<<
AArch64_AM
::
getShiftValue
(
Shift
)
<<
">"
;
break
;
}
case
k_CondCode
:
OS
<<
"<condcode "
<<
getCondCode
(
)
<<
">"
;
break
;
case
k_Register
:
OS
<<
"<register "
<<
getReg
(
)
<<
">"
;
break
;
case
k_VectorList
:
{
OS
<<
"<vectorlist "
;
unsigned
Reg
=
getVectorListStart
(
)
;
for
(
unsigned
i
=
0
,
e
=
getVectorListCount
(
)
;
i
!=
e
;
++
i
)
OS
<<
Reg
+
i
<<
" "
;
OS
<<
">"
;
break
;
}
case
k_VectorIndex
:
OS
<<
"<vectorindex "
<<
getVectorIndex
(
)
<<
">"
;
break
;
case
k_SysReg
:
OS
<<
"<sysreg: "
<<
getSysReg
(
)
<<
'>'
;
break
;
case
k_Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
case
k_SysCR
:
OS
<<
"c"
<<
getSysCR
(
)
;
break
;
case
k_Prefetch
:
{
bool
Valid
;
StringRef
Name
=
AArch64PRFM
::
PRFMMapper
(
)
.
toString
(
getPrefetch
(
)
,
Valid
)
;
if
(
Valid
)
OS
<<
"<prfop "
<<
Name
<<
">"
;
else
OS
<<
"<prfop invalid #"
<<
getPrefetch
(
)
<<
">"
;
break
;
}
case
k_ShiftExtend
:
{
OS
<<
"<"
<<
AArch64_AM
::
getShiftExtendName
(
getShiftExtendType
(
)
)
<<
" #"
<<
getShiftExtendAmount
(
)
;
if
(
!
hasShiftExtendAmount
(
)
)
OS
<<
"<imp>"
;
OS
<<
'>'
;
break
;
}
}
}
</s>

print - Print a debug representation of the operand to the given stream .

AArch64
AArch64
"<fpimm "
"("
AArch64_AM::getFPImmFloat
") >"
AArch64DB::DBarrierMapper
"<barrier "
">"
"<barrier invalid #"
">"
"<shiftedimm "
", lsl #"
AArch64_AM::getShiftValue
">"
"<condcode "
">"
"<register "
">"
"<vectorlist "
0
" "
">"
"<vectorindex "
">"
"<sysreg: "
"'"
"'"
"c"
AArch64PRFM::PRFMMapper
"<prfop "
">"
"<prfop invalid #"
">"
"<"
AArch64_AM::getShiftExtendName
" #"
"<imp>"


<s> SDNode * NVPTXDAGToDAGISel :: Select ( SDNode * N ) { if ( N -> isMachineOpcode ( ) ) return NULL ; SDNode * ResNode = NULL ; switch ( N -> getOpcode ( ) ) { case ISD :: LOAD : ResNode = SelectLoad ( N ) ; break ; case ISD :: STORE : ResNode = SelectStore ( N ) ; break ; case NVPTXISD :: LoadV2 : case NVPTXISD :: LoadV4 : ResNode = SelectLoadVector ( N ) ; break ; case NVPTXISD :: LDGV2 : case NVPTXISD :: LDGV4 : case NVPTXISD :: LDUV2 : case NVPTXISD :: LDUV4 : ResNode = SelectLDGLDUVector ( N ) ; break ; case NVPTXISD :: StoreV2 : case NVPTXISD :: StoreV4 : ResNode = SelectStoreVector ( N ) ; break ; default : break ; } if ( ResNode ) return ResNode ; return SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> static void mmix_file_end ( void ) { data_section ( ) ; } </s>


<s> static void force_into ( rtx value , rtx target ) { value = force_operand ( value , target ) ; if ( ! rtx_equal_p ( value , target ) ) emit_insn ( gen_move_insn ( target , value ) ) ; } </s>

Like force_operand , but guarantees that VALUE ends up in TARGET .


<s> inline static bool isMemIntrinsic ( const std :: string & Name ) { if ( Name . compare ( "@memcpy" ) == 0 || Name . compare ( "@memset" ) == 0 || Name . compare ( "@memmove" ) == 0 ) { return true ; } return false ; } </s>

Test if this node is a memory intrinsic ( with valid pointer information ) .


<s> unsigned M88kInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { case M88k :: LDrib : case M88k :: LDrih : case M88k :: LDriw : case M88k :: LDrid : case M88k :: LDrrsb : case M88k :: LDrrsbu : case M88k :: LDrrsd : case M88k :: LDrrsdu : case M88k :: LDrrsh : case M88k :: LDrrshu : case M88k :: LDrrsw : case M88k :: LDrrswu : case M88k :: LDrrub : case M88k :: LDrrubu : case M88k :: LDrrud : case M88k :: LDrrudu : case M88k :: LDrruh : case M88k :: LDrruhu : case M88k :: LDrruw : case M88k :: LDrruwu : if ( MI . getOperand ( 1 ) . isFI ( ) ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> static int alpha_elf_reloc_rw_mask ( void ) { return flag_pic ? 3 : 2 ; } </s>

Since we do n't have a .dynbss section , we should not allow global relocations in the .rodata section .


<s> extern rtx s390_build_signbit_mask ( machine_mode mode ) { if ( mode == TFmode && TARGET_VXE ) { wide_int mask_val = wi :: set_bit_in_zero ( 127 , 128 ) ; rtx mask = immed_wide_int_const ( mask_val , TImode ) ; return gen_lowpart ( TFmode , mask ) ; } machine_mode inner_mode = GET_MODE_INNER ( mode ) ; int inner_bitsize = GET_MODE_BITSIZE ( inner_mode ) ; wide_int mask_val = wi :: set_bit_in_zero ( inner_bitsize - 1 , inner_bitsize ) ; machine_mode int_mode = related_int_vector_mode ( mode ) . require ( ) ; rtx mask = immed_wide_int_const ( mask_val , GET_MODE_INNER ( int_mode ) ) ; mask = gen_lowpart ( inner_mode , mask ) ; int nunits = GET_MODE_NUNITS ( mode ) ; rtvec v = rtvec_alloc ( nunits ) ; for ( int i = 0 ; i < nunits ; i ++ ) RTVEC_ELT ( v , i ) = mask ; return gen_rtx_CONST_VECTOR ( mode , v ) ; } </s>

Emit a vector constant that contains 1s in each element 's sign bit position and 0s in other positions . MODE is the desired constant 's mode .


<s> bool AArch64SIMDInstrOpt :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; const TargetSubtargetInfo & ST = MF . getSubtarget ( ) ; const AArch64InstrInfo * AAII = static_cast < const AArch64InstrInfo * > ( ST . getInstrInfo ( ) ) ; if ( ! AAII ) return false ; SchedModel . init ( & ST ) ; if ( ! SchedModel . hasInstrSchedModel ( ) ) return false ; bool Changed = false ; for ( auto OptimizationKind : { VectorElem , Interleave } ) { if ( ! shouldExitEarly ( & MF , OptimizationKind ) ) { SmallVector < MachineInstr * , 8 > RemoveMIs ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) { bool InstRewrite ; if ( OptimizationKind == VectorElem ) InstRewrite = optimizeVectElement ( MI ) ; else InstRewrite = optimizeLdStInterleave ( MI ) ; if ( InstRewrite ) { RemoveMIs . push_back ( & MI ) ; Changed = true ; } } } for ( MachineInstr * MI : RemoveMIs ) MI -> eraseFromParent ( ) ; } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool HexagonTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { LSBaseSDNode * LSN = dyn_cast < LSBaseSDNode > ( N ) ; if ( ! LSN ) return false ; EVT VT = LSN -> getMemoryVT ( ) ; if ( ! VT . isSimple ( ) ) return false ; bool IsLegalType = VT == MVT :: i8 || VT == MVT :: i16 || VT == MVT :: i32 || VT == MVT :: i64 || Subtarget . isHVXVectorType ( VT . getSimpleVT ( ) ) ; if ( ! IsLegalType ) return false ; if ( Op -> getOpcode ( ) != ISD :: ADD ) return false ; Base = Op -> getOperand ( 0 ) ; Offset = Op -> getOperand ( 1 ) ; if ( ! isa < ConstantSDNode > ( Offset . getNode ( ) ) ) return false ; AM = ISD :: POST_INC ; int32_t V = cast < ConstantSDNode > ( Offset . getNode ( ) ) -> getSExtValue ( ) ; return Subtarget . getInstrInfo ( ) -> isValidAutoIncImm ( VT , V ) ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .


<s>
void
GCNScheduleDAGMILive
::
schedule
(
)
{
const
SIRegisterInfo
*
SRI
=
static_cast
<
const
SIRegisterInfo
*
>
(
TRI
)
;
std
::
vector
<
MachineInstr
*
>
Unsched
;
Unsched
.
reserve
(
NumRegionInstrs
)
;
for
(
auto
&
I
:
*
this
)
Unsched
.
push_back
(
&
I
)
;
ScheduleDAGMILive
::
schedule
(
)
;
GCNMaxOccupancySchedStrategy
&
S
=
(
GCNMaxOccupancySchedStrategy
&
)
*
SchedImpl
;
std
::
vector
<
unsigned
>
UnschedPressure
=
getRegPressure
(
)
.
MaxSetPressure
;
unsigned
MaxSGPRs
=
std
::
max
(
getTopRPTracker
(
)
.
getPressure
(
)
.
MaxSetPressure
[
SRI
->
getSGPRPressureSet
(
)
]
,
getBotRPTracker
(
)
.
getPressure
(
)
.
MaxSetPressure
[
SRI
->
getSGPRPressureSet
(
)
]
)
;
unsigned
MaxVGPRs
=
std
::
max
(
getTopRPTracker
(
)
.
getPressure
(
)
.
MaxSetPressure
[
SRI
->
getVGPRPressureSet
(
)
]
,
getBotRPTracker
(
)
.
getPressure
(
)
.
MaxSetPressure
[
SRI
->
getVGPRPressureSet
(
)
]
)
;
DEBUG
(
dbgs
(
)
<<
"Pressure after scheduling:\nSGPR = "
<<
MaxSGPRs
<<
"\nVGPR = "
<<
MaxVGPRs
<<
'\n'
)
;
if
(
MaxSGPRs
<=
S
.
SGPRCriticalLimit
&&
MaxVGPRs
<=
S
.
VGPRCriticalLimit
)
{
DEBUG
(
dbgs
(
)
<<
"Pressure in desired limits, done.\n"
)
;
return
;
}
unsigned
WavesAfter
=
getMaxWaves
(
MaxSGPRs
,
MaxVGPRs
,
MF
)
;
unsigned
WavesUnsched
=
getMaxWaves
(
UnschedPressure
[
SRI
->
getSGPRPressureSet
(
)
]
,
UnschedPressure
[
SRI
->
getVGPRPressureSet
(
)
]
,
MF
)
;
DEBUG
(
dbgs
(
)
<<
"Occupancy before scheduling: "
<<
WavesUnsched
<<
", after "
<<
WavesAfter
<<
".\n"
)
;
if
(
WavesAfter
>=
WavesUnsched
)
return
;
DEBUG
(
dbgs
(
)
<<
"Attempting to revert scheduling.\n"
)
;
RegionEnd
=
RegionBegin
;
for
(
MachineInstr
*
MI
:
Unsched
)
{
if
(
MI
->
getIterator
(
)
!=
RegionEnd
)
{
BB
->
remove
(
MI
)
;
BB
->
insert
(
RegionEnd
,
MI
)
;
if
(
LIS
)
{
LIS
->
handleMove
(
*
MI
,
true
)
;
RegisterOperands
RegOpers
;
RegOpers
.
collect
(
*
MI
,
*
TRI
,
MRI
,
ShouldTrackLaneMasks
,
false
)
;
if
(
ShouldTrackLaneMasks
)
{
SlotIndex
SlotIdx
=
LIS
->
getInstructionIndex
(
*
MI
)
.
getRegSlot
(
)
;
RegOpers
.
adjustLaneLiveness
(
*
LIS
,
MRI
,
SlotIdx
,
MI
)
;
}
else
{
RegOpers
.
detectDeadDefs
(
*
MI
,
*
LIS
)
;
}
}
}
RegionEnd
=
MI
->
getIterator
(
)
;
++
RegionEnd
;
DEBUG
(
dbgs
(
)
<<
"Scheduling "
<<
*
MI
)
;
}
RegionBegin
=
Unsched
.
front
(
)
->
getIterator
(
)
;
placeDebugValues
(
)
;
}
</s>

Schedule - This is called back from ScheduleDAGInstrs : :Run ( ) when it 's time to do some work .

AMDGPU
SI
SI
"Pressure after scheduling:\nSGPR = "
"\nVGPR = "
"Pressure in desired limits, done.\n"
"Occupancy before scheduling: "
", after "
".\n"
"Attempting to revert scheduling.\n"
"Scheduling "


Returns the tilegx_multiply_insn_seq for multiplier , or NULL if none exists .


<s> unsigned RISCVTargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { switch ( Op . getOpcode ( ) ) { default : break ; case RISCVISD :: SELECT_CC : { unsigned Tmp = DAG . ComputeNumSignBits ( Op . getOperand ( 3 ) , DemandedElts , Depth + 1 ) ; if ( Tmp == 1 ) return 1 ; unsigned Tmp2 = DAG . ComputeNumSignBits ( Op . getOperand ( 4 ) , DemandedElts , Depth + 1 ) ; return std :: min ( Tmp , Tmp2 ) ; } case RISCVISD :: SLLW : case RISCVISD :: SRAW : case RISCVISD :: SRLW : case RISCVISD :: DIVW : case RISCVISD :: DIVUW : case RISCVISD :: REMUW : case RISCVISD :: ROLW : case RISCVISD :: RORW : case RISCVISD :: GREVW : case RISCVISD :: GORCW : case RISCVISD :: FSLW : case RISCVISD :: FSRW : case RISCVISD :: SHFLW : case RISCVISD :: UNSHFLW : case RISCVISD :: BCOMPRESSW : case RISCVISD :: BDECOMPRESSW : case RISCVISD :: FCVT_W_RTZ_RV64 : case RISCVISD :: FCVT_WU_RTZ_RV64 : case RISCVISD :: STRICT_FCVT_W_RTZ_RV64 : case RISCVISD :: STRICT_FCVT_WU_RTZ_RV64 : return 33 ; case RISCVISD :: SHFL : case RISCVISD :: UNSHFL : { if ( Op . getValueType ( ) == MVT :: i64 && isa < ConstantSDNode > ( Op . getOperand ( 1 ) ) && ( Op . getConstantOperandVal ( 1 ) & 0x10 ) == 0 ) { unsigned Tmp = DAG . ComputeNumSignBits ( Op . getOperand ( 0 ) , Depth + 1 ) ; if ( Tmp > 32 ) return 33 ; } break ; } case RISCVISD :: VMV_X_S : if ( Op . getOperand ( 0 ) . getScalarValueSizeInBits ( ) > Subtarget . getXLen ( ) ) return 1 ; return Subtarget . getXLen ( ) - Op . getOperand ( 0 ) . getScalarValueSizeInBits ( ) + 1 ; } return 1 ; } </s>

Determine the number of bits in the operation that are sign bits .


<s> int move_dest_operand ( rtx op , enum machine_mode mode ) { switch ( GET_CODE ( op ) ) { case REG : return register_operand ( op , mode ) ; case SUBREG : if ( GET_CODE ( SUBREG_REG ( op ) ) == MEM ) return address_operand ( XEXP ( SUBREG_REG ( op ) , 0 ) , mode ) ; else return register_operand ( op , mode ) ; case MEM : return address_operand ( XEXP ( op , 0 ) , mode ) ; default : return 0 ; } } </s>

Return true if OP is an acceptable argument for a move destination .


<s> inline void classify_registers ( const_tree , HOST_WIDE_INT bitpos , bool fp , classify_data_t * data ) { if ( fp ) { data -> fp_regs = true ; if ( bitpos < BITS_PER_WORD ) data -> fp_regs_in_first_word = true ; } else data -> int_regs = true ; } </s>

A subroutine of function_arg_slotno . Classify the field .


<s> unsigned int pure_scalable_type_info :: num_pr ( ) const { unsigned int res = 0 ; for ( unsigned int i = 0 ; i < pieces . length ( ) ; ++ i ) res += pieces [ i ] . num_pr ; return res ; } </s>

Return the total number of predicate registers required by the PST .


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { unsigned LblOperand = Inst . getOpcode ( ) == AArch64 :: Bcc ? 1 : 0 ; if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ LblOperand ] . OperandType != MCOI :: OPERAND_PCREL ) return false ; int64_t Imm = Inst . getOperand ( LblOperand ) . getImm ( ) ; Target = Addr + Imm ; return true ; } </s>

Given a branch instruction try to get the address the branch targets .


<s>
int
AlphaRegisterInfo
::
getDwarfRegNum
(
unsigned
RegNum
,
bool
isEH
)
const
{
assert
(
0
&&
"What is the dwarf register number"
)
;
return
1
;
}
</s>

Map a target register to an equivalent dwarf register number .


<s>
bool
HexagonRDFOpt
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
*
MF
.
getFunction
(
)
)
)
return
false
;
if
(
RDFLimit
.
getPosition
(
)
)
{
if
(
RDFCount
>=
RDFLimit
)
return
false
;
RDFCount
++
;
}
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
const
auto
&
MDF
=
getAnalysis
<
MachineDominanceFrontier
>
(
)
;
const
auto
&
HII
=
*
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getInstrInfo
(
)
;
const
auto
&
HRI
=
*
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getRegisterInfo
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
bool
Changed
;
if
(
RDFDump
)
MF
.
print
(
dbgs
(
)
<<
"Before "
<<
getPassName
(
)
<<
"\n"
,
nullptr
)
;
HexagonRegisterAliasInfo
HAI
(
HRI
)
;
TargetOperandInfo
TOI
(
HII
)
;
DataFlowGraph
G
(
MF
,
HII
,
HRI
,
*
MDT
,
MDF
,
HAI
,
TOI
)
;
G
.
build
(
BuildOptions
::
KeepDeadPhis
)
;
if
(
RDFDump
)
dbgs
(
)
<<
"Starting copy propagation on: "
<<
MF
.
getName
(
)
<<
'\n'
<<
PrintNode
<
FuncNode
*
>
(
G
.
getFunc
(
)
,
G
)
<<
'\n'
;
HexagonCP
CP
(
G
)
;
CP
.
trace
(
RDFDump
)
;
Changed
=
CP
.
run
(
)
;
if
(
RDFDump
)
dbgs
(
)
<<
"Starting dead code elimination on: "
<<
MF
.
getName
(
)
<<
'\n'
<<
PrintNode
<
FuncNode
*
>
(
G
.
getFunc
(
)
,
G
)
<<
'\n'
;
HexagonDCE
DCE
(
G
,
*
MRI
)
;
DCE
.
trace
(
RDFDump
)
;
Changed
|=
DCE
.
run
(
)
;
if
(
Changed
)
{
if
(
RDFDump
)
dbgs
(
)
<<
"Starting liveness recomputation on: "
<<
MF
.
getName
(
)
<<
'\n'
;
Liveness
LV
(
*
MRI
,
G
)
;
LV
.
trace
(
RDFDump
)
;
LV
.
computeLiveIns
(
)
;
LV
.
resetLiveIns
(
)
;
LV
.
resetKills
(
)
;
}
if
(
RDFDump
)
MF
.
print
(
dbgs
(
)
<<
"After "
<<
getPassName
(
)
<<
"\n"
,
nullptr
)
;
return
false
;
}
</s>

Hexagon
Hexagon
Hexagon
Hexagon
"Before "
"\n"
Hexagon
"Starting copy propagation on: "
Hexagon
"Starting dead code elimination on: "
Hexagon
"Starting liveness recomputation on: "
"After "
"\n"


<s> static const char * unicosmk_ssib_name ( void ) { static char name [ 256 ] ; rtx x ; const char * fnname ; int len ; x = DECL_RTL ( cfun -> decl ) ; gcc_assert ( GET_CODE ( x ) == MEM ) ; x = XEXP ( x , 0 ) ; gcc_assert ( GET_CODE ( x ) == SYMBOL_REF ) ; fnname = XSTR ( x , 0 ) ; len = strlen ( fnname ) ; if ( len + SSIB_PREFIX_LEN > 255 ) len = 255 - SSIB_PREFIX_LEN ; strcpy ( name , SSIB_PREFIX ) ; strncpy ( name + SSIB_PREFIX_LEN , fnname , len ) ; name [ len + SSIB_PREFIX_LEN ] = 0 ; return name ; } </s>

Generate the name of the SSIB section for the current function .


<s> static bool mep_expand_setcc_1 ( enum rtx_code code , rtx dest , rtx op1 , rtx op2 ) { rtx tmp ; switch ( code ) { case GT : case GTU : tmp = op1 , op1 = op2 , op2 = tmp ; code = swap_condition ( code ) ; case LT : case LTU : op1 = force_reg ( SImode , op1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , gen_rtx_fmt_ee ( code , SImode , op1 , op2 ) ) ) ; return true ; case EQ : if ( op2 != const0_rtx ) op1 = expand_binop ( SImode , sub_optab , op1 , op2 , NULL , 1 , OPTAB_WIDEN ) ; mep_expand_setcc_1 ( LTU , dest , op1 , const1_rtx ) ; return true ; case NE : if ( optimize_size && op2 != const0_rtx ) return false ; if ( op2 != const0_rtx ) op1 = expand_binop ( SImode , sub_optab , op1 , op2 , NULL , 1 , OPTAB_WIDEN ) ; op2 = gen_reg_rtx ( SImode ) ; mep_expand_setcc_1 ( LTU , op2 , op1 , const1_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , gen_rtx_XOR ( SImode , op2 , const1_rtx ) ) ) ; return true ; case LE : if ( GET_CODE ( op2 ) != CONST_INT || INTVAL ( op2 ) == 0x7ffffff ) return false ; op2 = GEN_INT ( INTVAL ( op2 ) + 1 ) ; return mep_expand_setcc_1 ( LT , dest , op1 , op2 ) ; case LEU : if ( GET_CODE ( op2 ) != CONST_INT || INTVAL ( op2 ) == - 1 ) return false ; op2 = GEN_INT ( trunc_int_for_mode ( INTVAL ( op2 ) + 1 , SImode ) ) ; return mep_expand_setcc_1 ( LTU , dest , op1 , op2 ) ; case GE : if ( GET_CODE ( op2 ) != CONST_INT || INTVAL ( op2 ) == trunc_int_for_mode ( 0x80000000 , SImode ) ) return false ; op2 = GEN_INT ( INTVAL ( op2 ) - 1 ) ; return mep_expand_setcc_1 ( GT , dest , op1 , op2 ) ; case GEU : if ( GET_CODE ( op2 ) != CONST_INT || op2 == const0_rtx ) return false ; op2 = GEN_INT ( trunc_int_for_mode ( INTVAL ( op2 ) - 1 , SImode ) ) ; return mep_expand_setcc_1 ( GTU , dest , op1 , op2 ) ; default : gcc_unreachable ( ) ; } } </s>

Emit a setcc instruction in its entirity .


<s> static void load_lr_save ( int regno , rtx frame_reg_rtx , int offset ) { rtx mem = gen_frame_mem_offset ( Pmode , frame_reg_rtx , offset ) ; rtx reg = gen_rtx_REG ( Pmode , regno ) ; emit_move_insn ( reg , mem ) ; } </s>

Like cr , the move to lr instruction can be scheduled after the stack deallocation , but unlike cr , its stack frame save is still valid . So we only need to emit the cfa_restore on the correct instruction .


<s> void rs6000_expand_interleave ( rtx target , rtx op0 , rtx op1 , bool highp ) { machine_mode vmode = GET_MODE ( target ) ; unsigned i , high , nelt = GET_MODE_NUNITS ( vmode ) ; vec_perm_builder perm ( nelt , nelt , 1 ) ; high = ( highp ? 0 : nelt / 2 ) ; for ( i = 0 ; i < nelt / 2 ; i ++ ) { perm . quick_push ( i + high ) ; perm . quick_push ( i + nelt + high ) ; } rs6000_do_expand_vec_perm ( target , op0 , op1 , vmode , perm ) ; } </s>


<s> rtx aarch64_expand_builtin ( tree exp , rtx target , rtx subtarget ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , int ignore ATTRIBUTE_UNUSED ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , 0 ) ; int fcode = DECL_FUNCTION_CODE ( fndecl ) ; int icode ; rtx pat , op0 ; tree arg0 ; switch ( fcode ) { case AARCH64_BUILTIN_GET_FPCR : case AARCH64_BUILTIN_SET_FPCR : case AARCH64_BUILTIN_GET_FPSR : case AARCH64_BUILTIN_SET_FPSR : if ( ( fcode == AARCH64_BUILTIN_GET_FPCR ) || ( fcode == AARCH64_BUILTIN_GET_FPSR ) ) { icode = ( fcode == AARCH64_BUILTIN_GET_FPSR ) ? CODE_FOR_get_fpsr : CODE_FOR_get_fpcr ; target = gen_reg_rtx ( SImode ) ; pat = GEN_FCN ( icode ) ( target ) ; } else { target = NULL_RTX ; icode = ( fcode == AARCH64_BUILTIN_SET_FPSR ) ? CODE_FOR_set_fpsr : CODE_FOR_set_fpcr ; arg0 = CALL_EXPR_ARG ( exp , 0 ) ; op0 = force_reg ( SImode , expand_normal ( arg0 ) ) ; pat = GEN_FCN ( icode ) ( op0 ) ; } emit_insn ( pat ) ; return target ; } if ( fcode >= AARCH64_SIMD_BUILTIN_BASE && fcode <= AARCH64_SIMD_BUILTIN_MAX ) return aarch64_simd_expand_builtin ( fcode , exp , target ) ; else if ( fcode >= AARCH64_CRC32_BUILTIN_BASE && fcode <= AARCH64_CRC32_BUILTIN_MAX ) return aarch64_crc32_expand_builtin ( fcode , exp , target ) ; if ( fcode == AARCH64_BUILTIN_RSQRT_DF || fcode == AARCH64_BUILTIN_RSQRT_SF || fcode == AARCH64_BUILTIN_RSQRT_V2DF || fcode == AARCH64_BUILTIN_RSQRT_V2SF || fcode == AARCH64_BUILTIN_RSQRT_V4SF ) return aarch64_expand_builtin_rsqrt ( fcode , exp , target ) ; gcc_unreachable ( ) ; } </s>


<s> void MCS51PassConfig :: addIRPasses ( ) { addPass ( createMCS51ShiftExpandPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> void ix86_split_copysign_const ( rtx operands [ ] ) { machine_mode mode , vmode ; rtx dest , op0 , mask , x ; dest = operands [ 0 ] ; op0 = operands [ 1 ] ; mask = operands [ 3 ] ; mode = GET_MODE ( dest ) ; vmode = GET_MODE ( mask ) ; dest = simplify_gen_subreg ( vmode , dest , mode , 0 ) ; x = gen_rtx_AND ( vmode , dest , mask ) ; emit_insn ( gen_rtx_SET ( dest , x ) ) ; if ( op0 != CONST0_RTX ( vmode ) ) { x = gen_rtx_IOR ( vmode , dest , op0 ) ; emit_insn ( gen_rtx_SET ( dest , x ) ) ; } } </s>

Deconstruct a copysign operation into bit masks . Operand 0 is known to be a constant , and so has already been expanded into a vector constant .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"AZPR Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool rs6000_function_ok_for_sibcall ( tree decl , tree exp ) { tree fntype ; if ( CALL_EXPR_STATIC_CHAIN ( exp ) ) return false ; if ( decl ) fntype = TREE_TYPE ( decl ) ; else fntype = TREE_TYPE ( TREE_TYPE ( CALL_EXPR_FN ( exp ) ) ) ; if ( TARGET_ALTIVEC_ABI && TARGET_ALTIVEC_VRSAVE && ! ( decl && decl == current_function_decl ) ) { function_args_iterator args_iter ; tree type ; int nvreg = 0 ; FOREACH_FUNCTION_ARGS ( fntype , type , args_iter ) if ( TREE_CODE ( type ) == VECTOR_TYPE && ALTIVEC_OR_VSX_VECTOR_MODE ( TYPE_MODE ( type ) ) ) nvreg ++ ; FOREACH_FUNCTION_ARGS ( TREE_TYPE ( current_function_decl ) , type , args_iter ) if ( TREE_CODE ( type ) == VECTOR_TYPE && ALTIVEC_OR_VSX_VECTOR_MODE ( TYPE_MODE ( type ) ) ) nvreg -- ; if ( nvreg > 0 ) return false ; } if ( rs6000_decl_ok_for_sibcall ( decl ) ) { tree attr_list = TYPE_ATTRIBUTES ( fntype ) ; if ( ! lookup_attribute ( "longcall" , attr_list ) || lookup_attribute ( "shortcall" , attr_list ) ) return true ; } return false ; } </s>

Say whether a function is a candidate for sibcall handling or not . We do not allow indirect calls to be optimized into sibling calls . Also , we ca n't do it if there are any vector parameters ; there 's nowhere to put the VRsave code so it works ; note that functions with vector parameters are required to have a prototype , so the argument type info must be available here . ( The tail recursion case can work with vector parameters , but there 's no way to distinguish here . )


<s> const DataLayout * getDataLayout ( ) const override { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> bool PPCTargetMachine :: addInstSelector ( PassManagerBase & PM , bool Fast ) { PM . add ( createPPCISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool hasFusion ( ) const { return hasFuseAES ( ) ; } </s>

Return true if the CPU supports any kind of instruction fusion .


<s> bool equals ( const CSKYConstantPoolJT * A ) const { return JTI == A -> JTI && CSKYConstantPoolValue :: equals ( A ) ; } </s>

equals - Check for string equality , this is more efficient than compare ( ) when the relative ordering of inequal strings is n't needed .


<s> SDValue MipsTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SDNode * CallNode , const Type * RetTy ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; MipsCC MipsCCInfo ( CallConv , Subtarget , CCInfo ) ; MipsCCInfo . analyzeCallResult ( Ins , Subtarget . abiUsesSoftFloat ( ) , CallNode , RetTy ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( 1 ) ; InFlag = Val . getValue ( 2 ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( ISD :: BITCAST , DL , RVLocs [ i ] . getValVT ( ) , Val ) ; InVals . push_back ( Val ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s>
void
SystemZMCAsmBackend
::
relaxInstruction
(
const
MCInst
&
Inst
,
MCInst
&
Res
)
const
{
unsigned
Opcode
=
getRelaxedOpcode
(
Inst
.
getOpcode
(
)
)
;
assert
(
Opcode
&&
"Unexpected insn to relax"
)
;
Res
=
Inst
;
Res
.
setOpcode
(
Opcode
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .

SystemZ
SystemZ
"Unexpected insn to relax"


<s> bool ix86_vec_interleave_v2df_operator_ok ( rtx operands [ 3 ] , bool high ) { if ( MEM_P ( operands [ 0 ] ) ) return rtx_equal_p ( operands [ 0 ] , operands [ 1 + high ] ) ; if ( MEM_P ( operands [ 1 ] ) && MEM_P ( operands [ 2 ] ) ) return TARGET_SSE3 && rtx_equal_p ( operands [ 1 ] , operands [ 2 ] ) ; return true ; } </s>

Return TRUE if the operands to a vec_interleave_ { high , low } v2df are ok , keeping in mind the possible movddup alternative .


<s> void GCNHazardRecognizer :: AdvanceCycle ( ) { if ( ! CurrCycleInstr ) return ; const SIInstrInfo * TII = ST . getInstrInfo ( ) ; unsigned NumWaitStates = TII -> getNumWaitStates ( * CurrCycleInstr ) ; EmittedInstrs . push_front ( CurrCycleInstr ) ; for ( unsigned i = 1 , e = std :: min ( NumWaitStates , getMaxLookAhead ( ) ) ; i < e ; ++ i ) { EmittedInstrs . push_front ( nullptr ) ; } EmittedInstrs . resize ( getMaxLookAhead ( ) ) ; CurrCycleInstr = nullptr ; } </s>

AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled can not issue in the current cycle , either because of latency or resource conflicts .


"We assume that variable-sized objects have already been lowered, "

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> int GCNTTIImpl :: getMinMaxReductionCost ( VectorType * Ty , VectorType * CondTy , bool IsPairwise , bool IsUnsigned , TTI :: TargetCostKind CostKind ) { EVT OrigTy = TLI -> getValueType ( DL , Ty ) ; if ( IsPairwise || ! ST -> hasVOP3PInsts ( ) || OrigTy . getScalarSizeInBits ( ) != 16 ) return BaseT :: getMinMaxReductionCost ( Ty , CondTy , IsPairwise , IsUnsigned , CostKind ) ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; return LT . first * getHalfRateInstrCost ( ) ; } </s>

Try to calculate op costs for min/max reduction operations .


<s> static bool has_dispatch ( rtx_insn * insn , int action ) { if ( ( TARGET_BDVER1 || TARGET_BDVER2 || TARGET_BDVER3 || TARGET_BDVER4 || TARGET_ZNVER1 ) && flag_dispatch_scheduler ) switch ( action ) { default : return false ; case IS_DISPATCH_ON : return true ; case IS_CMP : return is_cmp ( insn ) ; case DISPATCH_VIOLATION : return dispatch_violation ( ) ; case FITS_DISPATCH_WINDOW : return fits_dispatch_window ( insn ) ; } return false ; } </s>

Return TRUE if Dispatch Scheduling is supported .


<s> SDValue SITargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { default : return AMDGPUTargetLowering :: LowerOperation ( Op , DAG ) ; case ISD :: BRCOND : return LowerBRCOND ( Op , DAG ) ; case ISD :: SELECT_CC : return LowerSELECT_CC ( Op , DAG ) ; case ISD :: SIGN_EXTEND : return LowerSIGN_EXTEND ( Op , DAG ) ; case ISD :: INTRINSIC_WO_CHAIN : { unsigned IntrinsicID = cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; unsigned NumUserSGPRs = 2 ; switch ( IntrinsicID ) { default : return AMDGPUTargetLowering :: LowerOperation ( Op , DAG ) ; case Intrinsic :: r600_read_ngroups_x : return LowerParameter ( DAG , VT , DL , DAG . getEntryNode ( ) , 0 ) ; case Intrinsic :: r600_read_ngroups_y : return LowerParameter ( DAG , VT , DL , DAG . getEntryNode ( ) , 4 ) ; case Intrinsic :: r600_read_ngroups_z : return LowerParameter ( DAG , VT , DL , DAG . getEntryNode ( ) , 8 ) ; case Intrinsic :: r600_read_global_size_x : return LowerParameter ( DAG , VT , DL , DAG . getEntryNode ( ) , 12 ) ; case Intrinsic :: r600_read_global_size_y : return LowerParameter ( DAG , VT , DL , DAG . getEntryNode ( ) , 16 ) ; case Intrinsic :: r600_read_global_size_z : return LowerParameter ( DAG , VT , DL , DAG . getEntryNode ( ) , 20 ) ; case Intrinsic :: r600_read_local_size_x : return LowerParameter ( DAG , VT , DL , DAG . getEntryNode ( ) , 24 ) ; case Intrinsic :: r600_read_local_size_y : return LowerParameter ( DAG , VT , DL , DAG . getEntryNode ( ) , 28 ) ; case Intrinsic :: r600_read_local_size_z : return LowerParameter ( DAG , VT , DL , DAG . getEntryNode ( ) , 32 ) ; case Intrinsic :: r600_read_tgid_x : return CreateLiveInRegister ( DAG , & AMDGPU :: SReg_32RegClass , AMDGPU :: SReg_32RegClass . getRegister ( NumUserSGPRs + 0 ) , VT ) ; case Intrinsic :: r600_read_tgid_y : return CreateLiveInRegister ( DAG , & AMDGPU :: SReg_32RegClass , AMDGPU :: SReg_32RegClass . getRegister ( NumUserSGPRs + 1 ) , VT ) ; case Intrinsic :: r600_read_tgid_z : return CreateLiveInRegister ( DAG , & AMDGPU :: SReg_32RegClass , AMDGPU :: SReg_32RegClass . getRegister ( NumUserSGPRs + 2 ) , VT ) ; case Intrinsic :: r600_read_tidig_x : return CreateLiveInRegister ( DAG , & AMDGPU :: VReg_32RegClass , AMDGPU :: VGPR0 , VT ) ; case Intrinsic :: r600_read_tidig_y : return CreateLiveInRegister ( DAG , & AMDGPU :: VReg_32RegClass , AMDGPU :: VGPR1 , VT ) ; case Intrinsic :: r600_read_tidig_z : return CreateLiveInRegister ( DAG , & AMDGPU :: VReg_32RegClass , AMDGPU :: VGPR2 , VT ) ; } } } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> static int rs6000_builtin_vectorization_cost ( enum vect_cost_for_stmt type_of_cost , tree vectype , int misalign ) { unsigned elements ; tree elem_type ; switch ( type_of_cost ) { case scalar_stmt : case scalar_store : case vector_stmt : case vector_store : case vec_to_scalar : case scalar_to_vec : case cond_branch_not_taken : return 1 ; case scalar_load : case vector_load : return 2 ; case vec_perm : if ( TARGET_VSX && rs6000_tune == PROCESSOR_POWER7 ) return 3 ; else return 1 ; case vec_promote_demote : if ( TARGET_VSX && rs6000_tune == PROCESSOR_POWER7 ) return 4 ; else return 1 ; case cond_branch_taken : return 3 ; case unaligned_load : case vector_gather_load : if ( TARGET_EFFICIENT_UNALIGNED_VSX ) return 2 ; if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == 2 || elements == 1 ) return 4 ; if ( elements == 4 ) { switch ( misalign ) { case 8 : return 4 ; case - 1 : case 4 : case 12 : return 33 ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return 4 ; case unaligned_store : case vector_scatter_store : if ( TARGET_EFFICIENT_UNALIGNED_VSX ) return 1 ; if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == 2 || elements == 1 ) return 2 ; if ( elements == 4 ) { switch ( misalign ) { case 8 : return 2 ; case - 1 : case 4 : case 12 : return 23 ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return 2 ; case vec_construct : elem_type = TREE_TYPE ( vectype ) ; if ( SCALAR_FLOAT_TYPE_P ( elem_type ) && TYPE_PRECISION ( elem_type ) == 32 ) return 5 ; else if ( INTEGRAL_TYPE_P ( elem_type ) ) { if ( TARGET_P9_VECTOR ) return TYPE_VECTOR_SUBPARTS ( vectype ) - 1 + 2 ; else return TYPE_VECTOR_SUBPARTS ( vectype ) - 1 + 5 ; } else return 2 ; default : gcc_unreachable ( ) ; } } </s>


<s> void GCNPassConfig :: addPreEmitPass ( ) { addPass ( createSIMemoryLegalizerPass ( ) ) ; addPass ( createSIInsertWaitcntsPass ( ) ) ; addPass ( createSIShrinkInstructionsPass ( ) ) ; addPass ( createSIModeRegisterPass ( ) ) ; addPass ( & PostRAHazardRecognizerID ) ; if ( getOptLevel ( ) > CodeGenOpt :: None ) addPass ( & SIInsertHardClausesID ) ; addPass ( & SIRemoveShortExecBranchesID ) ; addPass ( & SIPreEmitPeepholeID ) ; addPass ( & SIInsertSkipsPassID ) ; addPass ( & BranchRelaxationPassID ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> Relocator :: Result unsupported ( Relocation & pReloc , X86_64Relocator & pParent ) { return Relocator :: Unsupported ; } </s>


<s> virtual bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , const BranchProbability & Probability ) const { return NumCycles == 1 ; } </s>

Return true if it 's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion .


<s> static bool cdx_and_immed ( rtx op ) { if ( CONST_INT_P ( op ) ) { HOST_WIDE_INT ival = INTVAL ( op ) ; return ( ival == 1 || ival == 2 || ival == 3 || ival == 4 || ival == 8 || ival == 0xf || ival == 0x10 || ival == 0x1f || ival == 0x20 || ival == 0x3f || ival == 0x7f || ival == 0x80 || ival == 0xff || ival == 0x7ff || ival == 0xff00 || ival == 0xffff ) ; } return false ; } </s>

Returns true if OP is within range of CDX andi.n immediates .


This is used as a target hook to modify the DECL_ASSEMBLER_NAME in the language-independent default hook langhooks , c : lhd_set_decl_assembler_name ( ) and in cp/mangle , c : mangle_decl ( ) .


<s> static void gen_ashift_hi ( int type , int n , rtx reg ) { if ( n < 0 ) { if ( type == ASHIFT ) type = LSHIFTRT ; else type = ASHIFT ; n = - n ; } switch ( type ) { case ASHIFTRT : case LSHIFTRT : { int offset = 0 ; if ( GET_CODE ( reg ) == SUBREG ) { offset = SUBREG_BYTE ( reg ) ; reg = SUBREG_REG ( reg ) ; } gen_ashift ( type , n , gen_rtx_SUBREG ( SImode , reg , offset ) ) ; break ; } case ASHIFT : emit_insn ( gen_ashlhi3_k ( reg , reg , GEN_INT ( n ) ) ) ; break ; } } </s>


<s>
void
X86InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
assert
(
MF
.
getFrameInfo
(
)
->
getObjectSize
(
FrameIdx
)
>=
RC
->
getSize
(
)
&&
"Stack slot too small for store"
)
;
unsigned
Alignment
=
std
::
max
<
uint32_t
>
(
RC
->
getSize
(
)
,
16
)
;
bool
isAligned
=
(
MF
.
getTarget
(
)
.
getSubtargetImpl
(
)
->
getFrameLowering
(
)
->
getStackAlignment
(
)
>=
Alignment
)
||
RI
.
canRealignStack
(
MF
)
;
unsigned
Opc
=
getStoreRegOpcode
(
SrcReg
,
RC
,
isAligned
,
Subtarget
)
;
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool function_instance :: modifies_global_state_p ( ) const { unsigned int flags = call_properties ( ) ; if ( flags & CP_RAISE_FP_EXCEPTIONS ) return true ; return flags & ( CP_WRITE_MEMORY | CP_WRITE_CSR ) ; } </s>

Return true if calls to the function could modify some form of global state .


"instruction requires a CPU feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> void AnalyzeCallResult ( const SmallVectorImpl < ISD :: InputArg > & Ins , CCAssignFn Fn , const Type * RetTy , const char * Func ) { PreAnalyzeCallResult ( Ins , Fn , RetTy , Func ) ; CCState :: AnalyzeCallResult ( Ins , Fn ) ; } </s>

AnalyzeCallResult - Same as above except it 's specialized for calls which produce a single value .


<s> bool WebAssemblyTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { return Outs . size ( ) <= 1 ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .

WebAssembly WebAssembly ISD::OutputArg 1


<s> const int * HexagonRegisterInfo :: getRegClassPressureSets ( const TargetRegisterClass * RC ) const { static const int RCSetsTable [ ] = { 0 , - 1 , 1 , - 1 , 2 , - 1 , 0 , - 1 , - 1 } ; static const unsigned RCSetStartTable [ ] = { 0 , 2 , 4 , 6 , 0 } ; unsigned SetListStart = RCSetStartTable [ RC -> getID ( ) ] ; return & RCSetsTable [ SetListStart ] ; } </s>

Get the dimensions of register pressure impacted by this register class .


<s> bool MipsPassConfig :: addLegalizeMachineIR ( ) { addPass ( new Legalizer ( ) ) ; return false ; } </s>

This method should install a legalize pass , which converts the instruction sequence into one that can be selected by the target .


<s> bool MCS51RelaxMem :: runOnMachineFunction ( MachineFunction & MF ) { bool Modified = false ; const MCS51Subtarget & STI = MF . getSubtarget < MCS51Subtarget > ( ) ; TII = STI . getInstrInfo ( ) ; for ( Block & MBB : MF ) { bool BlockModified = runOnBasicBlock ( MBB ) ; Modified |= BlockModified ; } return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> void Initialize ( MCContext & Ctx , const TargetMachine & TM ) override { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; } </s>

This method must be called before any actual lowering is done .


<s> const char * output_ubranch ( rtx label , rtx_insn * insn ) { return output_branch ( label , "tr" , insn ) ; } </s>

Output an unconditional branch to LABEL . INSN is the instruction .


<s> static void avr_adjust_type_node ( tree * node , machine_mode mode , int sat_p ) { * node = make_node ( FIXED_POINT_TYPE ) ; TYPE_SATURATING ( * node ) = sat_p ; TYPE_UNSIGNED ( * node ) = UNSIGNED_FIXED_POINT_MODE_P ( mode ) ; TYPE_IBIT ( * node ) = GET_MODE_IBIT ( mode ) ; TYPE_FBIT ( * node ) = GET_MODE_FBIT ( mode ) ; TYPE_PRECISION ( * node ) = GET_MODE_BITSIZE ( mode ) ; TYPE_ALIGN ( * node ) = 8 ; SET_TYPE_MODE ( * node , mode ) ; layout_type ( * node ) ; } </s>


<s> void assignValueToAddress ( Register ValVReg , Register Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , 1 ) ; MIRBuilder . buildStore ( ValVReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> bool mips_const_vector_bitimm_clr_p ( rtx op , machine_mode mode ) { if ( GET_CODE ( op ) == CONST_VECTOR && op != CONSTM1_RTX ( mode ) ) { unsigned HOST_WIDE_INT val = ~ UINTVAL ( CONST_VECTOR_ELT ( op , 0 ) ) ; int vlog2 = exact_log2 ( val & GET_MODE_MASK ( GET_MODE_INNER ( mode ) ) ) ; if ( vlog2 != - 1 ) { gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) ; gcc_assert ( vlog2 >= 0 && vlog2 <= GET_MODE_UNIT_BITSIZE ( mode ) - 1 ) ; return mips_const_vector_same_val_p ( op , mode ) ; } } return false ; } </s>

Return true if OP is a constant vector with the number of units in MODE , and each unit has the same bit clear .


"  rs6000_builtin_decls[RS6000_BIF_NONE] = NULL_TREE;\n"

"  rs6000_builtin_decls[RS6000_BIF_MAX] = NULL_TREE;\n"

"  rs6000_builtin_decls[RS6000_OVLD_NONE] = NULL_TREE;\n\n"

Write everything to the initialization file ( rs6000-builtins.cc ) . Return 1 if successful , 0 otherwise .


<s>
MachineBasicBlock
*
SNESTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
MBB
)
const
{
int
Opc
=
MI
.
getOpcode
(
)
;
switch
(
Opc
)
{
case
SNES
::
Lsl8
:
case
SNES
::
Lsl16
:
case
SNES
::
Lsr8
:
case
SNES
::
Lsr16
:
case
SNES
::
Rol8
:
case
SNES
::
Rol16
:
case
SNES
::
Ror8
:
case
SNES
::
Ror16
:
case
SNES
::
Asr8
:
case
SNES
::
Asr16
:
return
insertShift
(
MI
,
MBB
)
;
case
SNES
::
MULRdRr
:
case
SNES
::
MULSRdRr
:
return
insertMul
(
MI
,
MBB
)
;
}
assert
(
(
Opc
==
SNES
::
Select16
||
Opc
==
SNES
::
Select8
)
&&
"Unexpected instr type to insert"
)
;
const
SNESInstrInfo
&
TII
=
(
const
SNESInstrInfo
&
)
*
MI
.
getParent
(
)
->
getParent
(
)
->
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
dl
=
MI
.
getDebugLoc
(
)
;
MachineFunction
*
MF
=
MBB
->
getParent
(
)
;
const
BasicBlock
*
LLVM_BB
=
MBB
->
getBasicBlock
(
)
;
MachineBasicBlock
*
trueMBB
=
MF
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
falseMBB
=
MF
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineFunction
::
iterator
I
;
for
(
I
=
MF
->
begin
(
)
;
I
!=
MF
->
end
(
)
&&
&
(
*
I
)
!=
MBB
;
++
I
)
;
if
(
I
!=
MF
->
end
(
)
)
++
I
;
MF
->
insert
(
I
,
trueMBB
)
;
MF
->
insert
(
I
,
falseMBB
)
;
trueMBB
->
splice
(
trueMBB
->
begin
(
)
,
MBB
,
std
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
MBB
->
end
(
)
)
;
trueMBB
->
transferSuccessorsAndUpdatePHIs
(
MBB
)
;
SNESCC
::
CondCodes
CC
=
(
SNESCC
::
CondCodes
)
MI
.
getOperand
(
3
)
.
getImm
(
)
;
BuildMI
(
MBB
,
dl
,
TII
.
getBrCond
(
CC
)
)
.
addMBB
(
trueMBB
)
;
BuildMI
(
MBB
,
dl
,
TII
.
get
(
SNES
::
RJMPk
)
)
.
addMBB
(
falseMBB
)
;
MBB
->
addSuccessor
(
falseMBB
)
;
MBB
->
addSuccessor
(
trueMBB
)
;
BuildMI
(
falseMBB
,
dl
,
TII
.
get
(
SNES
::
RJMPk
)
)
.
addMBB
(
trueMBB
)
;
falseMBB
->
addSuccessor
(
trueMBB
)
;
BuildMI
(
*
trueMBB
,
trueMBB
->
begin
(
)
,
dl
,
TII
.
get
(
SNES
::
PHI
)
,
MI
.
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
.
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
MBB
)
.
addReg
(
MI
.
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
falseMBB
)
;
MI
.
eraseFromParent
(
)
;
return
trueMBB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> unsigned GBZ80InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { case GB :: ST8_FI : { if ( MI . getOperand ( 1 ) . isFI ( ) ) { FrameIndex = MI . getOperand ( 0 ) . getIndex ( ) ; return MI . getOperand ( 1 ) . getReg ( ) ; } break ; } default : break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .