<s> static reg_class_t mn10300_secondary_reload ( bool in_p , rtx x , reg_class_t rclass_i , machine_mode mode , secondary_reload_info * sri ) { enum reg_class rclass = ( enum reg_class ) rclass_i ; enum reg_class xclass = NO_REGS ; unsigned int xregno = INVALID_REGNUM ; if ( REG_P ( x ) ) { xregno = REGNO ( x ) ; if ( xregno >= FIRST_PSEUDO_REGISTER ) xregno = true_regnum ( x ) ; if ( xregno != INVALID_REGNUM ) xclass = REGNO_REG_CLASS ( xregno ) ; } if ( ! TARGET_AM33 ) { if ( rclass != DATA_REGS && ( mode == QImode || mode == HImode ) && xclass == NO_REGS ) return DATA_REGS ; if ( in_p && rclass == SP_REGS && xclass != ADDRESS_REGS ) return ADDRESS_REGS ; if ( ! in_p && xclass == SP_REGS && rclass != ADDRESS_REGS && rclass != SP_OR_ADDRESS_REGS ) return ADDRESS_REGS ; } if ( in_p && rclass != SP_REGS && rclass != SP_OR_ADDRESS_REGS && rclass != SP_OR_GENERAL_REGS && GET_CODE ( x ) == PLUS && ( XEXP ( x , 0 ) == stack_pointer_rtx || XEXP ( x , 1 ) == stack_pointer_rtx ) ) { sri -> icode = CODE_FOR_reload_plus_sp_const ; return NO_REGS ; } if ( rclass == MDR_REGS && xclass != DATA_REGS ) return DATA_REGS ; if ( xclass == MDR_REGS && rclass != DATA_REGS ) return DATA_REGS ; if ( TARGET_AM33_2 && ( rclass == FP_REGS || xclass == FP_REGS ) && ( xclass == NO_REGS || rclass == NO_REGS ) ) { rtx addr = NULL ; if ( xregno >= FIRST_PSEUDO_REGISTER && xregno != INVALID_REGNUM ) { addr = reg_equiv_mem ( xregno ) ; if ( addr ) addr = XEXP ( addr , 0 ) ; } else if ( MEM_P ( x ) ) addr = XEXP ( x , 0 ) ; if ( addr && CONSTANT_ADDRESS_P ( addr ) ) return GENERAL_REGS ; } return NO_REGS ; } </s>


<s> EVT getSetCCResultType ( const DataLayout & , LLVMContext & , EVT VT ) const override { return MVT :: i32 ; } </s>

Return the value type to use for ISD : :SETCC .


<s> machine_mode memory_vector_mode ( const function_instance & fi ) const OVERRIDE { poly_uint64 nunits = GET_MODE_NUNITS ( fi . vector_mode ( 0 ) ) ; return aarch64_sve_data_mode ( m_to_mode , nunits ) . require ( ) ; } </s>

If the function addresses memory , return a vector mode whose GET_MODE_NUNITS is the number of elements addressed and whose GET_MODE_INNER is the mode of a single scalar memory element .


<s>
void
TeakInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
dbgs
(
)
<<
"loadRegFromStackSlot\n"
;
dbgs
(
)
<<
"ICC live: "
<<
MBB
.
computeRegisterLiveness
(
TRI
,
Teak
::
ICC
,
I
)
<<
"\n"
;
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
if
(
RC
->
hasSuperClassEq
(
&
Teak
::
ABRegsRegClass
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
Teak
::
LOAD_REG_FROM_STACK_PSEUDO_32_SEXT40
)
,
DestReg
)
.
addFrameIndex
(
FrameIndex
)
.
addImm
(
0
)
;
else
BuildMI
(
MBB
,
I
,
DL
,
get
(
Teak
::
LOAD_REG_FROM_STACK_PSEUDO_16
)
,
DestReg
)
.
addFrameIndex
(
FrameIndex
)
.
addImm
(
0
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


"failed to parse register and immediate pair"

ParseInstruction - Parse one assembly instruction .


<s> void ia64_expand_widen_sum ( rtx operands [ 3 ] , bool unsignedp ) { rtx l , h , x , s ; enum machine_mode wmode , mode ; rtx ( * unpack_l ) ( rtx , rtx , rtx ) ; rtx ( * unpack_h ) ( rtx , rtx , rtx ) ; rtx ( * plus ) ( rtx , rtx , rtx ) ; wmode = GET_MODE ( operands [ 0 ] ) ; mode = GET_MODE ( operands [ 1 ] ) ; switch ( mode ) { case V8QImode : unpack_l = gen_unpack1_l ; unpack_h = gen_unpack1_h ; plus = gen_addv4hi3 ; break ; case V4HImode : unpack_l = gen_unpack2_l ; unpack_h = gen_unpack2_h ; plus = gen_addv2si3 ; break ; default : gcc_unreachable ( ) ; } if ( unsignedp ) x = CONST0_RTX ( mode ) ; else { bool neg ; x = gen_reg_rtx ( mode ) ; neg = ia64_expand_vecint_compare ( LT , mode , x , operands [ 1 ] , CONST0_RTX ( mode ) ) ; gcc_assert ( ! neg ) ; } l = gen_reg_rtx ( wmode ) ; h = gen_reg_rtx ( wmode ) ; s = gen_reg_rtx ( wmode ) ; emit_insn ( unpack_l ( gen_lowpart ( mode , l ) , operands [ 1 ] , x ) ) ; emit_insn ( unpack_h ( gen_lowpart ( mode , h ) , operands [ 1 ] , x ) ) ; emit_insn ( plus ( s , l , operands [ 2 ] ) ) ; emit_insn ( plus ( operands [ 0 ] , h , s ) ) ; } </s>

Emit an integral vector widening sum operations .


<s> bool useFPForScavengingIndex ( const MachineFunction & MF ) const override { return false ; } </s>

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot .


"********** Fixing Irreducible Control Flow **********\n"

runOnMachineFunction - Emit the function body .


<s> int c4x_U_constraint ( rtx op ) { return GET_CODE ( op ) == CONST || GET_CODE ( op ) == SYMBOL_REF || GET_CODE ( op ) == LABEL_REF ; } </s>


<s>
unsigned
TOYInstrInfo
::
getGlobalBaseReg
(
MachineFunction
*
MF
)
const
{
llvm_unreachable
(
"getGlobalBaseReg not implemented\n"
)
;
}
</s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

TOY
TOY
"getGlobalBaseReg not implemented\n"


"eliminateCallFramePseudoInstr size too big: "

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static rtx nds32_expand_cctl_builtin ( enum insn_code icode , tree exp , rtx target , bool return_p , const char * name ) { rtx pat ; rtx op0 = nds32_read_argument ( exp , 0 ) ; rtx op1 = nds32_read_argument ( exp , 1 ) ; int op0_num = return_p ? 1 : 0 ; int op1_num = return_p ? 2 : 1 ; if ( return_p ) target = nds32_legitimize_target ( icode , target ) ; if ( ! nds32_check_constant_argument ( icode , op0_num , op0 , name ) ) return NULL_RTX ; op0 = nds32_legitimize_argument ( icode , op0_num , op0 ) ; op1 = nds32_legitimize_argument ( icode , op1_num , op1 ) ; if ( icode == CODE_FOR_cctl_idx_write ) { rtx op2 = nds32_read_argument ( exp , 2 ) ; op2 = nds32_legitimize_argument ( icode , 2 , op2 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 , op2 ) ; } else if ( return_p ) pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; else pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return target ; } </s>


<s> static HOST_WIDE_INT s390_vector_alignment ( const_tree type ) { if ( ! TARGET_VX_ABI ) return default_vector_alignment ( type ) ; if ( TYPE_USER_ALIGN ( type ) ) return TYPE_ALIGN ( type ) ; return MIN ( 64 , tree_to_shwi ( TYPE_SIZE ( type ) ) ) ; } </s>

The vector ABI requires vector types to be aligned on an 8 byte boundary ( our stack alignment ) . However , we allow this to be overriden by the user , while this definitely breaks the ABI .


<s> static int visium_save_reg_p ( int interrupt , int regno ) { switch ( regno ) { case HARD_FRAME_POINTER_REGNUM : return 0 ; case MDC_REGNUM : break ; case 29 : case 30 : return ( interrupt != 0 ) ; default : if ( fixed_regs [ regno ] ) return 0 ; break ; } if ( interrupt ) { if ( crtl -> is_leaf ) { if ( df_regs_ever_live_p ( regno ) ) return 1 ; } else if ( call_used_or_fixed_reg_p ( regno ) ) return 1 ; if ( regno == PROLOGUE_TMP_REGNUM ) { if ( df_regs_ever_live_p ( MDB_REGNUM ) || df_regs_ever_live_p ( MDC_REGNUM ) ) return 1 ; for ( int i = FP_FIRST_REGNUM ; i <= FP_LAST_REGNUM ; i ++ ) if ( df_regs_ever_live_p ( i ) ) return 1 ; } else if ( regno == PROLOGUE_TMP_REGNUM + 1 ) { if ( df_regs_ever_live_p ( MDB_REGNUM ) ) return 1 ; } } return df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) ; } </s>

Return non-zero if register REGNO needs to be saved in the frame .


<s> static int microblaze_interrupt_function_p ( tree func ) { tree a ; if ( TREE_CODE ( func ) != FUNCTION_DECL ) return 0 ; a = lookup_attribute ( "interrupt_handler" , DECL_ATTRIBUTES ( func ) ) ; return a != NULL_TREE ; } </s>

Return true if FUNC is an interrupt function as specified by the `` interrupt_handler '' attribute .


<s>
void
R600SchedStrategy
::
releaseBottomNode
(
SUnit
*
SU
)
{
DEBUG
(
dbgs
(
)
<<
"Bottom Releasing "
;
SU
->
dump
(
DAG
)
;
)
;
if
(
isPhysicalRegCopy
(
SU
->
getInstr
(
)
)
)
{
PhysicalRegCopy
.
push_back
(
SU
)
;
return
;
}
int
IK
=
getInstKind
(
SU
)
;
for
(
MachineInstr
::
const_mop_iterator
I
=
SU
->
getInstr
(
)
->
operands_begin
(
)
,
E
=
SU
->
getInstr
(
)
->
operands_end
(
)
;
I
!=
E
;
++
I
)
{
if
(
I
->
isReg
(
)
&&
I
->
getReg
(
)
==
AMDGPU
::
AR_X
)
{
if
(
I
->
isDef
(
)
)
{
UnscheduledARDefs
.
push_back
(
SU
)
;
}
else
{
UnscheduledARUses
.
push_back
(
SU
)
;
}
return
;
}
}
if
(
IK
==
IDOther
)
Available
[
IDOther
]
.
push_back
(
SU
)
;
else
Pending
[
IK
]
.
push_back
(
SU
)
;
}
</s>

Currently only scheduling top-down , so this method is empty .


<s> static void init_dispatch_sched ( void ) { dispatch_window_list = allocate_window ( ) ; dispatch_window_list1 = allocate_window ( ) ; init_window ( 0 ) ; init_window ( 1 ) ; } </s>

This routine initializes the dispatch scheduling information . It initiates building dispatch scheduler tables and constructs the first dispatch window .


<s> void thumb_reload_out_hi ( rtx * operands ) { emit_insn ( gen_thumb_movhi_clobber ( operands [ 0 ] , operands [ 1 ] , operands [ 2 ] ) ) ; } </s>

Handle storing a half-word to memory during reload .


<s> bool MipsTargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const MipsSubtarget & Subtarget = TM . getSubtarget < MipsSubtarget > ( ) ; if ( Subtarget . isLinux ( ) ) return false ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ; if ( Kind . isMergeable1ByteCString ( ) ) return false ; const Type * Ty = GV -> getType ( ) -> getElementType ( ) ; return IsInSmallSection ( TM . getTargetData ( ) -> getTypeAllocSize ( Ty ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> rtx rs6000_libcall_value ( machine_mode mode ) { unsigned int regno ; if ( TARGET_32BIT && TARGET_POWERPC64 && mode == DImode ) return rs6000_parallel_return ( mode , 2 , SImode , GP_ARG_RETURN , 1 ) ; if ( DECIMAL_FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = ( mode == TDmode ) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN ; else if ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS && ( ( TARGET_SINGLE_FLOAT && mode == SFmode ) || TARGET_DOUBLE_FLOAT ) ) regno = FP_ARG_RETURN ; else if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI ) regno = ALTIVEC_ARG_RETURN ; else if ( COMPLEX_MODE_P ( mode ) && targetm . calls . split_complex_arg ) return rs6000_complex_function_value ( mode ) ; else if ( TARGET_E500_DOUBLE && TARGET_HARD_FLOAT && ( mode == DFmode || mode == DCmode || FLOAT128_IBM_P ( mode ) || mode == TCmode ) ) return spe_build_register_parallel ( mode , GP_ARG_RETURN ) ; else regno = GP_ARG_RETURN ; return gen_rtx_REG ( mode , regno ) ; } </s>

Define how to find the value returned by a library function assuming the value has mode MODE .


<s> static inline bool mips_constant_elt_p ( rtx x ) { return CONST_INT_P ( x ) || GET_CODE ( x ) == CONST_DOUBLE ; } </s>

A subroutine of mips_expand_vec_init , match constant vector elements .


<s> void s390_expand_vec_init ( rtx target , rtx vals ) { machine_mode mode = GET_MODE ( target ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; int n_elts = GET_MODE_NUNITS ( mode ) ; bool all_same = true , all_regs = true , all_const_int = true ; rtx x ; int i ; for ( i = 0 ; i < n_elts ; ++ i ) { x = XVECEXP ( vals , 0 , i ) ; if ( ! CONST_INT_P ( x ) ) all_const_int = false ; if ( i > 0 && ! rtx_equal_p ( x , XVECEXP ( vals , 0 , 0 ) ) ) all_same = false ; if ( ! REG_P ( x ) ) all_regs = false ; } if ( all_same && all_const_int && ( XVECEXP ( vals , 0 , 0 ) == const0_rtx || s390_contiguous_bitmask_vector_p ( XVECEXP ( vals , 0 , 0 ) , NULL , NULL ) || s390_bytemask_vector_p ( XVECEXP ( vals , 0 , 0 ) , NULL ) ) ) { emit_insn ( gen_rtx_SET ( target , gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , 0 ) ) ) ) ; return ; } if ( all_same ) { emit_insn ( gen_rtx_SET ( target , gen_rtx_VEC_DUPLICATE ( mode , XVECEXP ( vals , 0 , 0 ) ) ) ) ; return ; } if ( all_regs && REG_P ( target ) && n_elts == 2 && GET_MODE_SIZE ( inner_mode ) == 8 ) { emit_insn ( gen_rtx_SET ( target , gen_rtx_VEC_CONCAT ( mode , XVECEXP ( vals , 0 , 0 ) , XVECEXP ( vals , 0 , 1 ) ) ) ) ; return ; } if ( TARGET_VXE && ( mode == V4SImode || mode == V4SFmode ) ) { bool found = true ; x = XVECEXP ( vals , 0 , 0 ) ; if ( memory_operand ( x , inner_mode ) ) { for ( i = 1 ; i < n_elts ; ++ i ) found = found && XVECEXP ( vals , 0 , i ) == const0_rtx ; if ( found ) { machine_mode half_mode = ( inner_mode == SFmode ? V2SFmode : V2SImode ) ; emit_insn ( gen_rtx_SET ( target , gen_rtx_VEC_CONCAT ( mode , gen_rtx_VEC_CONCAT ( half_mode , x , const0_rtx ) , gen_rtx_VEC_CONCAT ( half_mode , const0_rtx , const0_rtx ) ) ) ) ; return ; } } } emit_insn ( gen_rtx_SET ( target , CONST0_RTX ( mode ) ) ) ; for ( i = 0 ; i < n_elts ; i ++ ) { rtx elem = XVECEXP ( vals , 0 , i ) ; if ( ! general_operand ( elem , GET_MODE ( elem ) ) ) elem = force_reg ( inner_mode , elem ) ; emit_insn ( gen_rtx_SET ( target , gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , elem , GEN_INT ( i ) , target ) , UNSPEC_VEC_SET ) ) ) ; } } </s>

Emit the RTX necessary to initialize the vector TARGET with values in VALS .


<s> EVT X86TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & Context , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i8 ; if ( VT . getSizeInBits ( ) >= 512 ) { EVT EltVT = VT . getVectorElementType ( ) ; const unsigned NumElts = VT . getVectorNumElements ( ) ; if ( Subtarget . hasAVX512 ( ) ) if ( EltVT == MVT :: i32 || EltVT == MVT :: i64 || EltVT == MVT :: f32 || EltVT == MVT :: f64 ) return EVT :: getVectorVT ( Context , MVT :: i1 , NumElts ) ; if ( Subtarget . hasBWI ( ) ) if ( EltVT == MVT :: i8 || EltVT == MVT :: i16 ) return EVT :: getVectorVT ( Context , MVT :: i1 , NumElts ) ; } if ( VT . isSimple ( ) ) { MVT VVT = VT . getSimpleVT ( ) ; const unsigned NumElts = VVT . getVectorNumElements ( ) ; MVT EltVT = VVT . getVectorElementType ( ) ; if ( Subtarget . hasBWI ( ) && Subtarget . hasVLX ( ) ) return MVT :: getVectorVT ( MVT :: i1 , NumElts ) ; if ( ! isTypeLegal ( VT ) && getTypeAction ( Context , VT ) == TypePromoteInteger ) { EVT LegalVT = getTypeToTransformTo ( Context , VT ) ; EltVT = LegalVT . getVectorElementType ( ) . getSimpleVT ( ) ; } if ( Subtarget . hasVLX ( ) && EltVT . getSizeInBits ( ) >= 32 ) switch ( NumElts ) { case 2 : return MVT :: v2i1 ; case 4 : return MVT :: v4i1 ; case 8 : return MVT :: v8i1 ; } } return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


"\n; VA:: ANSI: %d args before, anon @ #%d, %dtime\n"

Worker function for TARGET_SETUP_INCOMING_VARARGS .


<s> static bool aarch64_legitimate_constant_p ( machine_mode mode , rtx x ) { if ( CONST_INT_P ( x ) || ( CONST_DOUBLE_P ( x ) && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) || GET_CODE ( x ) == CONST_VECTOR ) return true ; unsigned int vec_flags = aarch64_classify_vector_mode ( mode ) ; if ( vec_flags == ( VEC_ADVSIMD | VEC_STRUCT ) ) return false ; if ( vec_flags & VEC_ANY_SVE ) return aarch64_simd_valid_immediate ( x , NULL ) ; if ( GET_CODE ( x ) == HIGH ) x = XEXP ( x , 0 ) ; poly_int64 offset ; if ( poly_int_rtx_p ( x , & offset ) ) return aarch64_offset_temporaries ( false , offset ) <= 1 ; x = strip_offset ( x , & offset ) ; if ( ! offset . is_constant ( ) && aarch64_offset_temporaries ( true , offset ) > 0 ) return false ; if ( maybe_ne ( offset , 0 ) && SYMBOL_REF_P ( x ) && SYMBOL_REF_ANCHOR_P ( x ) ) return false ; if ( SYMBOL_REF_P ( x ) && ! SYMBOL_REF_TLS_MODEL ( x ) ) return true ; if ( GET_CODE ( x ) == LABEL_REF ) return true ; return false ; } </s>

Implement TARGET_LEGITIMATE_CONSTANT_P hook . Return true for constants that should be rematerialized rather than spilled .


<s> static bool sh_assemble_integer ( rtx value , unsigned int size , int aligned_p ) { if ( TARGET_FDPIC && size == UNITS_PER_WORD && GET_CODE ( value ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( value ) ) { fputs ( "\t.long\t" , asm_out_file ) ; output_addr_const ( asm_out_file , value ) ; fputs ( "@FUNCDESC\n" , asm_out_file ) ; return true ; } return default_assemble_integer ( value , size , aligned_p ) ; } </s>

Implementation of TARGET_ASM_INTEGER for SH . Pointers to functions need to be output as pointers to function descriptors for FDPIC .


<s> static int fr30_num_arg_regs ( machine_mode mode , const_tree type ) { int size ; if ( targetm . calls . must_pass_in_stack ( mode , type ) ) return 0 ; if ( type && mode == BLKmode ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; return ( size + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } </s>

Compute the number of word sized registers needed to hold a function argument of mode INT_MODE and tree type TYPE .


<s> static bool global_regs_p ( unsigned first , unsigned last ) { while ( first < last ) if ( global_regs [ first ++ ] ) return true ; return false ; } </s>

Look for user-defined global regs in the range FIRST to LAST-1 . We should not restore these , and so can not use lmw or out-of-line restore functions if there are any . We also ca n't save them ( well , emit frame notes for them ) , because frame unwinding during exception handling will restore saved registers .


<s> const SparcRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool HexagonCommonGEP :: runOnFunction ( Function & F ) { for ( Function :: iterator A = F . begin ( ) , Z = F . end ( ) ; A != Z ; ++ A ) for ( BasicBlock :: iterator I = A -> begin ( ) , E = A -> end ( ) ; I != E ; ++ I ) if ( isa < InvokeInst > ( I ) || isa < LandingPadInst > ( I ) ) return false ; Fn = & F ; DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; PDT = & getAnalysis < PostDominatorTree > ( ) ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; Ctx = & F . getContext ( ) ; Nodes . clear ( ) ; Uses . clear ( ) ; NodeOrder . clear ( ) ; SpecificBumpPtrAllocator < GepNode > Allocator ; Mem = & Allocator ; collect ( ) ; common ( ) ; NodeToValueMap Loc ; computeNodePlacement ( Loc ) ; materialize ( Loc ) ; removeDeadCode ( ) ; verifyFunction ( F ) ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> unsigned LEGInstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { if ( MBB . empty ( ) ) return 0 ; unsigned NumRemoved = 0 ; auto I = MBB . end ( ) ; do { -- I ; unsigned Opc = I -> getOpcode ( ) ; if ( ( Opc == LEG :: B ) || ( Opc == LEG :: Bcc ) ) { auto ToDelete = I ; ++ I ; MBB . erase ( ToDelete ) ; NumRemoved ++ ; } } while ( I != MBB . begin ( ) ) ; return NumRemoved ; } </s>

Remove the branching code at the end of the specific MBB .


<s> bool BPFAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( ( Count % 8 ) != 0 ) return false ; for ( uint64_t i = 0 ; i < Count ; i += 8 ) OW -> write64 ( 0x15000000 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


Return the probing interval for -fstack-clash-protection .


<s>
SDValue
MBlazeTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_MBlaze
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
unsigned
Ret
=
(
CallConv
==
CallingConv
::
MBLAZE_INTR
)
MBlazeISD
::
IRet
:
MBlazeISD
::
Ret
;
unsigned
Reg
=
(
CallConv
==
CallingConv
::
MBLAZE_INTR
)
MBlaze
::
R14
:
MBlaze
::
R15
;
RetOps
.
push_back
(
DAG
.
getRegister
(
Reg
,
MVT
::
i32
)
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
Ret
,
dl
,
MVT
::
Other
,
&
RetOps
[
0
]
,
RetOps
.
size
(
)
)
;
}
</s>


<s> static bool ia64_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { if ( lookup_attribute ( "syscall_linkage" , TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ) ) return false ; return ( decl && ( * targetm . binds_local_p ) ( decl ) ) || TARGET_CONST_GP ; } </s>

True if it is OK to do sibling call optimization for the specified call expression EXP . DECL will be the called function , or NULL if this is an indirect call .


<s> static int first_altivec_reg_to_save ( void ) { int i ; if ( ! TARGET_ALTIVEC_ABI ) return LAST_ALTIVEC_REGNO + 1 ; for ( i = FIRST_ALTIVEC_REGNO + 20 ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( regs_ever_live [ i ] ) break ; return i ; } </s>


<s> void Z80RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


"Instr doesn't have FrameIndex operand!"


<s> X86Subtarget & X86Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { initializeEnvironment ( ) ; resetSubtargetFeatures ( CPU , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> static void mips_sim_wait_insn ( struct mips_sim * state , rtx_insn * insn ) { mips_sim_wait_regs ( state , insn ) ; mips_sim_wait_units ( state , insn ) ; } </s>

Advance simulation state STATE until INSN is ready to issue .


<s>
bool
RV16KAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Operands
.
push_back
(
RV16KOperand
::
createToken
(
Name
,
NameLoc
)
)
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
return
false
;
if
(
parseOperand
(
Operands
)
)
return
true
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
getLexer
(
)
.
Lex
(
)
;
if
(
parseOperand
(
Operands
)
)
return
true
;
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
getParser
(
)
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
getParser
(
)
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .


<s>
SDValue
RISCVTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
report_fatal_error
(
"unimplemented operand"
)
;
case
ISD
::
GlobalAddress
:
return
lowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
lowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
lowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
lowerSELECT
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
lowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
lowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
lowerRETURNADDR
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

RISCV
RISCV
"unimplemented operand"
ISD::GlobalAddress
ISD::BlockAddress
ISD::ConstantPool
ISD::SELECT
ISD::VASTART
ISD::FRAMEADDR
ISD::RETURNADDR


<s> static bool tryAddingSymbolicOperand ( int64_t Value , bool isBranch , uint64_t Address , uint64_t Offset , uint64_t Width , MCInst & MI , const MCDisassembler * Dis ) { return Dis -> tryAddingSymbolicOperand ( MI , Value , Address , isBranch , Offset , Width ) ; } </s>

Try to add a symbolic operand instead of Value to the MCInst .


<s>
void
MipsInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
if
(
RC
==
Mips
::
CPURegsRegisterClass
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
SW
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
else
if
(
RC
==
Mips
::
FGR32RegisterClass
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
SWC1
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
else
if
(
RC
==
Mips
::
AFGR64RegisterClass
)
{
if
(
!
TM
.
getSubtarget
<
MipsSubtarget
>
(
)
.
isMips1
(
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
SDC1
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
}
else
{
const
TargetRegisterInfo
*
TRI
=
MBB
.
getParent
(
)
->
getTarget
(
)
.
getRegisterInfo
(
)
;
const
unsigned
*
SubSet
=
TRI
->
getSubRegisters
(
SrcReg
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
SWC1
)
)
.
addReg
(
SubSet
[
0
]
,
getKillRegState
(
isKill
)
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
SWC1
)
)
.
addReg
(
SubSet
[
1
]
,
getKillRegState
(
isKill
)
)
.
addImm
(
4
)
.
addFrameIndex
(
FI
)
;
}
}
else
llvm_unreachable
(
"Register class not handled!"
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
READ_REGISTER
:
ExpandREAD_REGISTER
(
N
,
Results
,
DAG
)
;
break
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SREM
:
case
ISD
::
UREM
:
Res
=
LowerREM
(
N
,
DAG
)
;
break
;
case
ISD
::
SDIVREM
:
case
ISD
::
UDIVREM
:
Res
=
LowerDivRem
(
SDValue
(
N
,
0
)
,
DAG
)
;
assert
(
Res
.
getNumOperands
(
)
==
2
&&
"DivRem needs two values"
)
;
Results
.
push_back
(
Res
.
getValue
(
0
)
)
;
Results
.
push_back
(
Res
.
getValue
(
1
)
)
;
return
;
case
ISD
::
READCYCLECOUNTER
:
ReplaceREADCYCLECOUNTER
(
N
,
Results
,
DAG
,
Subtarget
)
;
return
;
case
ISD
::
UDIV
:
case
ISD
::
SDIV
:
assert
(
Subtarget
->
isTargetWindows
(
)
&&
"can only expand DIV on Windows"
)
;
return
ExpandDIV_Windows
(
SDValue
(
N
,
0
)
,
DAG
,
N
->
getOpcode
(
)
==
ISD
::
SDIV
,
Results
)
;
case
ISD
::
ATOMIC_CMP_SWAP
:
ReplaceCMP_SWAP_64Results
(
N
,
Results
,
DAG
)
;
return
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

ARM
ARM
"Don't know how to custom expand this!"
ISD::READ_REGISTER
ISD::BITCAST
ISD::SRL
ISD::SRA
ISD::SREM
ISD::UREM
ISD::SDIVREM
ISD::UDIVREM
0
2
"DivRem needs two values"
0
1
ISD::READCYCLECOUNTER
ISD::UDIV
ISD::SDIV
"can only expand DIV on Windows"
0
ISD::SDIV
ISD::ATOMIC_CMP_SWAP


<s> unsigned ARMFastISel :: fastEmitInst_i ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , uint64_t Imm ) { unsigned ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; if ( II . getNumDefs ( ) >= 1 ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addImm ( Imm ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addImm ( Imm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ 0 ] ) ) ; } return ResultReg ; } </s>

Emit a MachineInstr with a single immediate operand , and a result register in the given register class .


"LR & FP are always handled in emitEpilogue"

"loadRegFromStackSlot didn't insert any code!"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static rtx ix86_expand_sse_cmp ( rtx dest , enum rtx_code code , rtx cmp_op0 , rtx cmp_op1 , rtx op_true , rtx op_false ) { machine_mode mode = GET_MODE ( dest ) ; machine_mode cmp_ops_mode = GET_MODE ( cmp_op0 ) ; machine_mode cmp_mode ; bool maskcmp = false ; rtx x ; if ( GET_MODE_SIZE ( cmp_ops_mode ) == 64 ) { cmp_mode = mode_for_size ( GET_MODE_NUNITS ( cmp_ops_mode ) , MODE_INT , 0 ) ; gcc_assert ( cmp_mode != BLKmode ) ; maskcmp = true ; } else cmp_mode = cmp_ops_mode ; cmp_op0 = force_reg ( cmp_ops_mode , cmp_op0 ) ; if ( ! nonimmediate_operand ( cmp_op1 , cmp_ops_mode ) ) cmp_op1 = force_reg ( cmp_ops_mode , cmp_op1 ) ; if ( optimize || ( op_true && reg_overlap_mentioned_p ( dest , op_true ) ) || ( op_false && reg_overlap_mentioned_p ( dest , op_false ) ) ) dest = gen_reg_rtx ( maskcmp ? cmp_mode : mode ) ; if ( maskcmp && ( code == GT || code == EQ ) ) { rtx ( * gen ) ( rtx , rtx , rtx ) ; switch ( cmp_ops_mode ) { case V64QImode : gcc_assert ( TARGET_AVX512BW ) ; gen = code == GT ? gen_avx512bw_gtv64qi3 : gen_avx512bw_eqv64qi3_1 ; break ; case V32HImode : gcc_assert ( TARGET_AVX512BW ) ; gen = code == GT ? gen_avx512bw_gtv32hi3 : gen_avx512bw_eqv32hi3_1 ; break ; case V16SImode : gen = code == GT ? gen_avx512f_gtv16si3 : gen_avx512f_eqv16si3_1 ; break ; case V8DImode : gen = code == GT ? gen_avx512f_gtv8di3 : gen_avx512f_eqv8di3_1 ; break ; default : gen = NULL ; } if ( gen ) { emit_insn ( gen ( dest , cmp_op0 , cmp_op1 ) ) ; return dest ; } } x = gen_rtx_fmt_ee ( code , cmp_mode , cmp_op0 , cmp_op1 ) ; if ( cmp_mode != mode && ! maskcmp ) { x = force_reg ( cmp_ops_mode , x ) ; convert_move ( dest , x , false ) ; } else emit_insn ( gen_rtx_SET ( dest , x ) ) ; return dest ; } </s>

Expand an sse vector comparison . Return the register with the result .


<s>
void
Thumb1InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
&
ARM
::
tGPRRegClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
&
ARM
::
tGPRRegClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
,
MachineMemOperand
::
MOStore
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tSTRspi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
}
}
</s>

ARM
ARM::tGPRRegClass
ARM
"Unknown regclass!"
ARM::tGPRRegClass
ARM
ARM::tSTRspi
0
ARMCC::AL


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
SDValue
AMDGPUTargetLowering
::
LowerCall
(
CallLoweringInfo
&
CLI
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SDValue
Callee
=
CLI
.
Callee
;
SelectionDAG
&
DAG
=
CLI
.
DAG
;
const
Function
&
Fn
=
*
DAG
.
getMachineFunction
(
)
.
getFunction
(
)
;
StringRef
FuncName
(
"<unknown>"
)
;
if
(
const
ExternalSymbolSDNode
*
G
=
dyn_cast
<
ExternalSymbolSDNode
>
(
Callee
)
)
FuncName
=
G
->
getSymbol
(
)
;
else
if
(
const
GlobalAddressSDNode
*
G
=
dyn_cast
<
GlobalAddressSDNode
>
(
Callee
)
)
FuncName
=
G
->
getGlobal
(
)
->
getName
(
)
;
DiagnosticInfoUnsupported
NoCalls
(
Fn
,
"unsupported call to function "
+
FuncName
,
CLI
.
DL
.
getDebugLoc
(
)
)
;
DAG
.
getContext
(
)
->
diagnose
(
NoCalls
)
;
return
SDValue
(
)
;
}
</s>

This hook must be implemented to lower calls into the specified DAG .

AMDGPU
AMDGPU
"<unknown>"
"unsupported call to function "


<s>
void
SystemZInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MBBI
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
SystemZ
::
GR128BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
copyPhysReg
(
MBB
,
MBBI
,
DL
,
RI
.
getSubReg
(
DestReg
,
SystemZ
::
subreg_h64
)
,
RI
.
getSubReg
(
SrcReg
,
SystemZ
::
subreg_h64
)
,
KillSrc
)
;
copyPhysReg
(
MBB
,
MBBI
,
DL
,
RI
.
getSubReg
(
DestReg
,
SystemZ
::
subreg_l64
)
,
RI
.
getSubReg
(
SrcReg
,
SystemZ
::
subreg_l64
)
,
KillSrc
)
;
return
;
}
if
(
SystemZ
::
GRX32BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
emitGRX32Move
(
MBB
,
MBBI
,
DL
,
DestReg
,
SrcReg
,
SystemZ
::
LR
,
32
,
KillSrc
)
;
return
;
}
unsigned
Opcode
;
if
(
SystemZ
::
GR64BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LGR
;
else
if
(
SystemZ
::
FP32BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LER
;
else
if
(
SystemZ
::
FP64BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LDR
;
else
if
(
SystemZ
::
FP128BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LXR
;
else
if
(
SystemZ
::
VR32BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
VLR32
;
else
if
(
SystemZ
::
VR64BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
VLR64
;
else
if
(
SystemZ
::
VR128BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
VLR
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
Opcode
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> uint64_t getNullPointerValue ( unsigned AddrSpace ) const { if ( AddrSpace == AS . LOCAL_ADDRESS || AddrSpace == AS . REGION_ADDRESS ) return - 1 ; return 0 ; } </s>

Get the integer value of a null pointer in the given address space .


runOnMachineFunction - Emit the function body .


<s> MachineInstr * PPCInstrInfo :: findLoopInstr ( MachineBasicBlock & PreHeader ) const { unsigned LOOPi = ( Subtarget . isPPC64 ( ) ? PPC :: MTCTR8loop : PPC :: MTCTRloop ) ; for ( auto & I : PreHeader . instrs ( ) ) if ( I . getOpcode ( ) == LOOPi ) return & I ; return nullptr ; } </s>

Find the hardware loop instruction used to set-up the specified loop .

PowerPC PPC PPC PPC::MTCTR8loop PPC::MTCTRloop


<s> void MipsSEInstrInfo :: adjustStackPtr ( unsigned SP , int64_t Amount , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { MipsABIInfo ABI = Subtarget . getABI ( ) ; DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned ADDu = ABI . GetPtrAdduOp ( ) ; unsigned ADDiu = ABI . GetPtrAddiuOp ( ) ; if ( Amount == 0 ) return ; if ( isInt < 16 > ( Amount ) ) BuildMI ( MBB , I , DL , get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; else { unsigned Reg = loadImmediate ( Amount , MBB , I , DL , nullptr ) ; BuildMI ( MBB , I , DL , get ( ADDu ) , SP ) . addReg ( SP ) . addReg ( Reg , RegState :: Kill ) ; } } </s>


<s> static int need_to_save ( int regno ) { if ( fixed_regs [ regno ] ) return 0 ; if ( crtl -> calls_eh_return ) return 1 ; if ( regno == FP_REGNO ) return 0 ; if ( cfun -> machine -> is_interrupt && ( ! cfun -> machine -> is_leaf || ( regno == A0_REGNO && m32c_function_needs_enter ( ) ) ) ) return 1 ; if ( df_regs_ever_live_p ( regno ) && ( ! call_used_regs [ regno ] || cfun -> machine -> is_interrupt ) ) return 1 ; return 0 ; } </s>

Returns true if the given register needs to be saved by the current function .


<s> uint64_t MipsFrameLowering :: estimateStackSize ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo & TRI = * MF . getSubtarget ( ) . getRegisterInfo ( ) ; int64_t Offset = 0 ; for ( int I = MFI -> getObjectIndexBegin ( ) ; I != 0 ; ++ I ) Offset = std :: max ( Offset , - MFI -> getObjectOffset ( I ) ) ; for ( const MCPhysReg * R = TRI . getCalleeSavedRegs ( & MF ) ; * R ; ++ R ) { unsigned Size = TRI . getMinimalPhysRegClass ( * R ) -> getSize ( ) ; Offset = RoundUpToAlignment ( Offset + Size , Size ) ; } unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; assert ( ! MFI -> getObjectIndexEnd ( ) || MaxAlign ) ; for ( unsigned I = 0 , E = MFI -> getObjectIndexEnd ( ) ; I != E ; ++ I ) Offset = RoundUpToAlignment ( Offset + MFI -> getObjectSize ( I ) , MaxAlign ) ; if ( MFI -> adjustsStack ( ) && hasReservedCallFrame ( MF ) ) Offset = RoundUpToAlignment ( Offset + MFI -> getMaxCallFrameSize ( ) , std :: max ( MaxAlign , getStackAlignment ( ) ) ) ; return RoundUpToAlignment ( Offset , getStackAlignment ( ) ) ; } </s>

Estimate and return the size of the stack frame .


<s> static int stackSlotSize ( ) { return 4 ; } </s>


<s> bool PPCDarwinAsmPrinter :: doFinalization ( Module & M ) { bool isPPC64 = TM . getDataLayout ( ) -> getPointerSizeInBits ( ) == 64 ; const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetFnStubList ( ) ; if ( ! Stubs . empty ( ) ) EmitFunctionStubs ( Stubs ) ; if ( MAI -> doesSupportExceptionHandling ( ) && MMI ) { const std :: vector < const Function * > & Personalities = MMI -> getPersonalities ( ) ; for ( std :: vector < const Function * > :: const_iterator I = Personalities . begin ( ) , E = Personalities . end ( ) ; I != E ; ++ I ) { if ( * I ) { MCSymbol * NLPSym = getSymbolWithGlobalValueBase ( * I , "$non_lazy_ptr" ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMIMacho . getGVStubEntry ( NLPSym ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( * I ) , true ) ; } } } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer -> EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer -> EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer -> EmitIntValue ( 0 , isPPC64 ? 8 : 4 ) ; else OutStreamer -> EmitValue ( MCSymbolRefExpr :: create ( MCSym . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 ) ; } Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer -> EmitLabel ( Stubs [ i ] . first ) ; OutStreamer -> EmitValue ( MCSymbolRefExpr :: create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 ) ; } Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> static rtx restore_fpr ( rtx base , int offset , int regnum ) { rtx addr ; addr = gen_rtx_MEM ( DFmode , plus_constant ( Pmode , base , offset ) ) ; set_mem_alias_set ( addr , get_frame_alias_set ( ) ) ; return emit_move_insn ( gen_rtx_REG ( DFmode , regnum ) , addr ) ; } </s>

Emit insn to restore fpr REGNUM from offset OFFSET relative to register BASE . Return generated insn .


<s> static enum ivms_arg_type ia64_arg_type ( machine_mode mode ) { switch ( mode ) { case E_SFmode : return FS ; case E_DFmode : return FT ; default : return I64 ; } } </s>

Return ivms_arg_type based on machine_mode .


<s> void emitSparcRegisterIgnore ( unsigned reg ) override { } </s>

Emit `` .register < reg > , # ignore '' .


<s> RangeTree :: Node * RangeTree :: add ( Node * N , const OffsetRange & R ) { if ( N == nullptr ) return new Node ( R ) ; if ( N -> Range == R ) { N -> Count ++ ; return N ; } if ( R < N -> Range ) N -> Left = add ( N -> Left , R ) ; else N -> Right = add ( N -> Right , R ) ; return rebalance ( update ( N ) ) ; } </s>


<s> void RISCVFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; SavedRegs . set ( RISCV :: X1 ) ; SavedRegs . set ( RISCV :: X8 ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


";; Emitting minipool after insn %u;\ address %ld; align %d (bytes)\n"


<s> VSETVLIInfo intersect ( const VSETVLIInfo & Other ) const { if ( ! Other . isValid ( ) ) return * this ; if ( ! isValid ( ) ) return Other ; if ( * this == Other ) return * this ; return VSETVLIInfo :: getUnknown ( ) ; } </s>

Intersect this set with a temporary other set in place .


<s>
unsigned
MipsSEInstrInfo
::
getOppositeBranchOpc
(
unsigned
Opc
)
const
{
switch
(
Opc
)
{
default
:
llvm_unreachable
(
"Illegal opcode!"
)
;
case
Mips
::
BEQ
:
return
Mips
::
BNE
;
case
Mips
::
BNE
:
return
Mips
::
BEQ
;
case
Mips
::
BGTZ
:
return
Mips
::
BLEZ
;
case
Mips
::
BGEZ
:
return
Mips
::
BLTZ
;
case
Mips
::
BLTZ
:
return
Mips
::
BGEZ
;
case
Mips
::
BLEZ
:
return
Mips
::
BGTZ
;
case
Mips
::
BEQ64
:
return
Mips
::
BNE64
;
case
Mips
::
BNE64
:
return
Mips
::
BEQ64
;
case
Mips
::
BGTZ64
:
return
Mips
::
BLEZ64
;
case
Mips
::
BGEZ64
:
return
Mips
::
BLTZ64
;
case
Mips
::
BLTZ64
:
return
Mips
::
BGEZ64
;
case
Mips
::
BLEZ64
:
return
Mips
::
BGTZ64
;
case
Mips
::
BC1T
:
return
Mips
::
BC1F
;
case
Mips
::
BC1F
:
return
Mips
::
BC1T
;
case
Mips
::
BEQZC_MM
:
return
Mips
::
BNEZC_MM
;
case
Mips
::
BNEZC_MM
:
return
Mips
::
BEQZC_MM
;
case
Mips
::
BEQZC
:
return
Mips
::
BNEZC
;
case
Mips
::
BNEZC
:
return
Mips
::
BEQZC
;
case
Mips
::
BEQC
:
return
Mips
::
BNEC
;
case
Mips
::
BNEC
:
return
Mips
::
BEQC
;
case
Mips
::
BGTZC
:
return
Mips
::
BLEZC
;
case
Mips
::
BGEZC
:
return
Mips
::
BLTZC
;
case
Mips
::
BLTZC
:
return
Mips
::
BGEZC
;
case
Mips
::
BLEZC
:
return
Mips
::
BGTZC
;
}
}
</s>

getOppositeBranchOpc - Return the inverse of the specified opcode , e.g .


<s> static void pad_bb ( void ) { rtx_insn * insn , * next_insn , * prev_insn , * hbr_insn = 0 ; int length ; int addr ; shorten_branches ( get_insns ( ) ) ; length = 0 ; prev_insn = 0 ; insn = get_insns ( ) ; if ( ! active_insn_p ( insn ) ) insn = next_active_insn ( insn ) ; for ( ; insn ; insn = next_insn ) { next_insn = next_active_insn ( insn ) ; if ( INSN_P ( insn ) && ( INSN_CODE ( insn ) == CODE_FOR_iprefetch || INSN_CODE ( insn ) == CODE_FOR_hbr ) ) { if ( hbr_insn ) { int a0 = INSN_ADDRESSES ( INSN_UID ( hbr_insn ) ) ; int a1 = INSN_ADDRESSES ( INSN_UID ( insn ) ) ; if ( ( a1 - a0 == 8 && GET_MODE ( insn ) != TImode ) || ( a1 - a0 == 4 ) ) { prev_insn = emit_insn_before ( gen_lnop ( ) , insn ) ; PUT_MODE ( prev_insn , GET_MODE ( insn ) ) ; PUT_MODE ( insn , TImode ) ; INSN_LOCATION ( prev_insn ) = INSN_LOCATION ( insn ) ; length += 4 ; } } hbr_insn = insn ; } if ( INSN_P ( insn ) && INSN_CODE ( insn ) == CODE_FOR_blockage && next_insn ) { if ( GET_MODE ( insn ) == TImode ) PUT_MODE ( next_insn , TImode ) ; insn = next_insn ; next_insn = next_active_insn ( insn ) ; } addr = INSN_ADDRESSES ( INSN_UID ( insn ) ) ; if ( ( CALL_P ( insn ) || JUMP_P ( insn ) ) && SCHED_ON_EVEN_P ( insn ) ) { if ( ( ( addr + length ) & 7 ) != 0 ) { emit_nop_for_insn ( prev_insn ) ; length += 4 ; } } else if ( GET_MODE ( insn ) == TImode && ( ( next_insn && GET_MODE ( next_insn ) != TImode ) || get_attr_type ( insn ) == TYPE_MULTI0 ) && ( ( addr + length ) & 7 ) != 0 ) { emit_nop_for_insn ( prev_insn ) ; length += 4 ; } prev_insn = insn ; } } </s>

Insert nops in basic blocks to meet dual issue alignment requirements . Also make sure hbrp and hint instructions are at least one cycle apart , possibly inserting a nop .


<s> bool isReg ( ) const { return Kind == k_Register ; } </s>


<s> void ARMBankConflictHazardRecognizer :: EmitInstruction ( SUnit * SU ) { MachineInstr & MI = * SU -> getInstr ( ) ; if ( ! MI . mayLoad ( ) || MI . mayStore ( ) || MI . getNumMemOperands ( ) != 1 ) return ; auto MO = * MI . memoperands ( ) . begin ( ) ; uint64_t Size1 = MO -> getSize ( ) ; if ( Size1 > 4 ) return ; Accesses . push_back ( & MI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
const
MCPhysReg
*
ARM64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_ARM64_AllRegs_SaveList
;
else
return
CSR_ARM64_AAPCS_SaveList
;
}
</s>


<s> virtual const TargetRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
static
MCSymbol
*
GetSymbolFromOperand
(
const
MachineOperand
&
MO
,
AsmPrinter
&
AP
)
{
const
TargetMachine
&
TM
=
AP
.
TM
;
Mangler
*
Mang
=
AP
.
Mang
;
const
DataLayout
*
DL
=
TM
.
getSubtargetImpl
(
)
->
getDataLayout
(
)
;
MCContext
&
Ctx
=
AP
.
OutContext
;
bool
isDarwin
=
TM
.
getSubtarget
<
PPCSubtarget
>
(
)
.
isDarwin
(
)
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
)
{
if
(
isDarwin
)
Suffix
=
"$stub"
;
}
else
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
Suffix
=
"$non_lazy_ptr"
;
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
->
getPrivateGlobalPrefix
(
)
;
unsigned
PrefixLen
=
Name
.
size
(
)
;
if
(
!
MO
.
isGlobal
(
)
)
{
assert
(
MO
.
isSymbol
(
)
&&
"Isn't a symbol reference"
)
;
Mang
->
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
)
;
}
else
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
TM
.
getNameWithPrefix
(
Name
,
GV
,
*
Mang
)
;
}
unsigned
OrigLen
=
Name
.
size
(
)
PrefixLen
;
Name
+=
Suffix
;
MCSymbol
*
Sym
=
Ctx
.
GetOrCreateSymbol
(
Name
.
str
(
)
)
;
StringRef
OrigName
=
StringRef
(
Name
)
.
substr
(
PrefixLen
,
OrigLen
)
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
&&
isDarwin
)
{
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
getMachOMMI
(
AP
)
.
getFnStubEntry
(
Sym
)
;
if
(
StubSym
.
getPointer
(
)
)
return
Sym
;
if
(
MO
.
isGlobal
(
)
)
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
else
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
Ctx
.
GetOrCreateSymbol
(
OrigName
)
,
false
)
;
}
return
Sym
;
}
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
{
MachineModuleInfoMachO
&
MachO
=
getMachOMMI
(
AP
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_HIDDEN_FLAG
)
MachO
.
getHiddenGVStubEntry
(
Sym
)
:
MachO
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
return
Sym
;
}
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


"getBranchTargetOpValueMMR6 expects only expressions or immediates"

getBranchTargetOpValueMMR6 - Return binary encoding of the branch target operand .


<s> void MipsELFStreamer :: EmitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) { MCELFStreamer :: EmitInstruction ( Inst , STI ) ; MCContext & Context = getContext ( ) ; const MCRegisterInfo * MCRegInfo = Context . getRegisterInfo ( ) ; for ( unsigned OpIndex = 0 ; OpIndex < Inst . getNumOperands ( ) ; ++ OpIndex ) { const MCOperand & Op = Inst . getOperand ( OpIndex ) ; if ( ! Op . isReg ( ) ) continue ; unsigned Reg = Op . getReg ( ) ; RegInfoRecord -> SetPhysRegUsed ( Reg , MCRegInfo ) ; } createPendingLabelRelocs ( ) ; } </s>


<s> static bool rs6000_can_eliminate ( const int from , const int to ) { return ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : from == RS6000_PIC_OFFSET_TABLE_REGNUM ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || constant_pool_empty_p ( ) : true ) ; } </s>

Given FROM and TO register numbers , say whether this elimination is allowed . Frame pointer elimination is automatically handled . For the RS/6000 , if frame pointer elimination is being done , we would like to convert ap into fp , not sp . We need r30 if -mminimal-toc was specified , and there are constant pool references .


<s> static llvm :: Type * getVectorElementType ( llvm :: Type * Ty ) { return llvm :: cast < llvm :: FixedVectorType > ( Ty ) -> getElementType ( ) ; } </s>

Given a vector type , return the type of each element .


<s> int m32r_legitimate_pic_operand_p ( rtx x ) { if ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF ) return 0 ; if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && ( GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == SYMBOL_REF || GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == LABEL_REF ) && ( CONST_INT_P ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ) ) return 0 ; return 1 ; } </s>


<s>
static
void
frv_function_prologue
(
FILE
*
file
,
HOST_WIDE_INT
size
ATTRIBUTE_UNUSED
)
{
if
(
frv_stack_info
(
)
->
total_size
==
0
&&
frv_function_contains_far_jump
(
)
)
{
rtx
insn
;
gcc_assert
(
!
regs_ever_live
[
GPR_FIRST
+
3
]
)
;
fprintf
(
file
,
"\tmovsg lr,gr3\n"
)
;
for
(
insn
=
get_insns
(
)
;
insn
!=
;
insn
=
NEXT_INSN
(
insn
)
)
if
(
GET_CODE
(
insn
)
==
JUMP_INSN
)
{
rtx
pattern
=
PATTERN
(
insn
)
;
if
(
GET_CODE
(
pattern
)
==
PARALLEL
&&
XVECLEN
(
pattern
,
0
)
>=
2
&&
GET_CODE
(
XVECEXP
(
pattern
,
0
,
0
)
)
==
RETURN
&&
GET_CODE
(
XVECEXP
(
pattern
,
0
,
1
)
)
==
USE
)
{
rtx
address
=
XEXP
(
XVECEXP
(
pattern
,
0
,
1
)
,
0
)
;
if
(
GET_CODE
(
address
)
==
REG
&&
REGNO
(
address
)
==
LR_REGNO
)
REGNO
(
address
)
=
GPR_FIRST
+
3
;
}
}
}
frv_pack_insns
(
)
;
memset
(
frv_nops
,
0
,
sizeof
(
frv_nops
)
)
;
}
</s>

For the FRV , this function makes sure that a function with far jumps will return correctly . It also does the VLIW packing .


<s>
void
mt_init_cumulative_args
(
CUMULATIVE_ARGS
*
cum
,
tree
fntype
,
rtx
libname
,
tree
fndecl
ATTRIBUTE_UNUSED
,
int
incoming
)
{
*
cum
=
0
;
if
(
TARGET_DEBUG_ARG
)
{
fprintf
(
stderr
,
"\nmt_init_cumulative_args:"
)
;
if
(
incoming
)
fputs
(
" incoming"
,
stderr
)
;
if
(
fntype
)
{
tree
ret_type
=
TREE_TYPE
(
fntype
)
;
fprintf
(
stderr
,
" return = %s,"
,
tree_code_name
[
(
int
)
TREE_CODE
(
ret_type
)
]
)
;
}
if
(
libname
&&
GET_CODE
(
libname
)
==
SYMBOL_REF
)
fprintf
(
stderr
,
" libname = %s"
,
XSTR
(
libname
,
0
)
)
;
if
(
cfun
->
returns_struct
)
fprintf
(
stderr
,
" return-struct"
)
;
putc
(
'\n'
,
stderr
)
;
}
}
</s>


<s> TargetLowering :: ConstraintWeight PPCTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'b' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; case 'd' : if ( type -> isDoubleTy ( ) ) weight = CW_Register ; break ; case 'v' : if ( type -> isVectorTy ( ) ) weight = CW_Register ; break ; case 'y' : weight = CW_Register ; break ; case 'Z' : weight = CW_Memory ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


"JIT relocation model must be set to static or default!"

runOnMachineFunction - Emit the function body .


<s> unsigned SICMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; unsigned RegNo = Ctx . getRegisterInfo ( ) -> getEncodingValue ( Reg ) ; return RegNo ; } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isFPImm ( ) ) { return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( 32 ) . getLimitedValue ( ) ) ; } assert ( MO . isExpr ( ) ) ; return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> void NVPTXTTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP ) { BaseT :: getUnrollingPreferences ( L , SE , UP ) ; UP . Partial = UP . Runtime = true ; UP . PartialThreshold = UP . Threshold / 4 ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> static tree alpha_fold_builtin_extxx ( tree op [ ] , unsigned HOST_WIDE_INT opint [ ] , long op_const , unsigned HOST_WIDE_INT bytemask , bool is_high ) { long zap_const = 2 ; tree * zap_op = NULL ; if ( op_const & 2 ) { unsigned HOST_WIDE_INT loc ; loc = opint [ 1 ] & 7 ; loc *= BITS_PER_UNIT ; if ( loc != 0 ) { if ( op_const & 1 ) { unsigned HOST_WIDE_INT temp = opint [ 0 ] ; if ( is_high ) temp <<= loc ; else temp >>= loc ; opint [ 0 ] = temp ; zap_const = 3 ; } } else zap_op = op ; } opint [ 1 ] = bytemask ; return alpha_fold_builtin_zapnot ( zap_op , opint , zap_const ) ; } </s>

Fold the builtins for the EXT family of instructions .


<s> static bool noncall_uses_reg ( rtx reg , rtx_insn * insn , rtx * set ) { * set = NULL_RTX ; rtx reg2 = sfunc_uses_reg ( insn ) ; if ( reg2 && REGNO ( reg2 ) == REGNO ( reg ) ) { rtx pattern = single_set ( insn ) ; if ( pattern && REG_P ( SET_DEST ( pattern ) ) && REGNO ( reg ) == REGNO ( SET_DEST ( pattern ) ) ) * set = pattern ; return false ; } if ( ! CALL_P ( insn ) ) { rtx pattern = single_set ( insn ) ; if ( pattern && REG_P ( SET_DEST ( pattern ) ) && REGNO ( reg ) == REGNO ( SET_DEST ( pattern ) ) ) { rtx par , part ; int i ; * set = pattern ; par = PATTERN ( insn ) ; if ( GET_CODE ( par ) == PARALLEL ) for ( i = XVECLEN ( par , 0 ) - 1 ; i >= 0 ; i -- ) { part = XVECEXP ( par , 0 , i ) ; if ( GET_CODE ( part ) != SET && reg_mentioned_p ( reg , part ) ) return true ; } return reg_mentioned_p ( reg , SET_SRC ( pattern ) ) ; } return true ; } rtx pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) == PARALLEL ) { for ( int i = XVECLEN ( pattern , 0 ) - 1 ; i >= 1 ; i -- ) if ( reg_mentioned_p ( reg , XVECEXP ( pattern , 0 , i ) ) ) return true ; pattern = XVECEXP ( pattern , 0 , 0 ) ; } if ( GET_CODE ( pattern ) == SET ) { if ( reg_mentioned_p ( reg , SET_DEST ( pattern ) ) ) { if ( ! REG_P ( SET_DEST ( pattern ) ) || REGNO ( reg ) != REGNO ( SET_DEST ( pattern ) ) ) return true ; * set = pattern ; } pattern = SET_SRC ( pattern ) ; } if ( GET_CODE ( pattern ) != CALL || ! MEM_P ( XEXP ( pattern , 0 ) ) || ! rtx_equal_p ( reg , XEXP ( XEXP ( pattern , 0 ) , 0 ) ) ) return true ; return false ; } </s>

See if the only way in which INSN uses REG is by calling it , or by setting it while calling it . Set * SET to a SET rtx if the register is set by INSN .


<s> bool arm_const_double_by_parts ( rtx val ) { machine_mode mode = GET_MODE ( val ) ; rtx part ; if ( optimize_size || arm_ld_sched ) return true ; if ( mode == VOIDmode ) mode = DImode ; part = gen_highpart_mode ( SImode , mode , val ) ; gcc_assert ( CONST_INT_P ( part ) ) ; if ( const_ok_for_arm ( INTVAL ( part ) ) || const_ok_for_arm ( ~ INTVAL ( part ) ) ) return true ; part = gen_lowpart ( SImode , val ) ; gcc_assert ( CONST_INT_P ( part ) ) ; if ( const_ok_for_arm ( INTVAL ( part ) ) || const_ok_for_arm ( ~ INTVAL ( part ) ) ) return true ; return false ; } </s>

Return true if it is worthwhile to split a 64-bit constant into two 32-bit operations . This is the case if optimizing for size , or if we have load delay slots , or if one 32-bit part can be done with a single data operation .


<s> unsigned AVRInstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { if ( BytesRemoved ) * BytesRemoved = 0 ; MachineBasicBlock :: iterator I = MBB . end ( ) ; unsigned Count = 0 ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) { continue ; } if ( I -> getOpcode ( ) != AVR :: RJMPk && getCondFromBranchOpc ( I -> getOpcode ( ) ) == AVRCC :: COND_INVALID ) { break ; } if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++ Count ; } return Count ; } </s>

Remove the branching code at the end of the specific MBB .


<s> bool RISCVInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . end ( ) ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! isUnpredicatedTerminator ( * I ) ) break ; SmallVector < MachineOperand , 4 > ThisCond ; ThisCond . push_back ( MachineOperand :: CreateImm ( 0 ) ) ; const MachineOperand * ThisTarget ; if ( ! isBranch ( I , ThisCond , ThisTarget ) ) return true ; if ( ! ThisTarget -> isMBB ( ) ) return true ; if ( ThisCond [ 0 ] . getImm ( ) == RISCV :: CCMASK_ANY ) { if ( ! AllowModify ) { TBB = ThisTarget -> getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = 0 ; TBB = ThisTarget -> getMBB ( ) ; continue ; } if ( Cond . empty ( ) ) { FBB = TBB ; TBB = ThisTarget -> getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( ThisCond [ 0 ] . getImm ( ) ) ) ; for ( unsigned int i = 0 ; i < ( I -> getNumExplicitOperands ( ) ) ; i ++ ) Cond . push_back ( I -> getOperand ( i ) ) ; continue ; } assert ( Cond . size ( ) <= 4 ) ; assert ( TBB ) ; if ( TBB != ThisTarget -> getMBB ( ) ) return true ; unsigned OldCond = Cond [ 0 ] . getImm ( ) ; if ( OldCond == ThisCond [ 0 ] . getImm ( ) ) continue ; } return false ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> bool NyuziAsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Mnemonic , SMLoc NameLoc , OperandVector & Operands ) { Operands . push_back ( NyuziOperand :: createToken ( Mnemonic , NameLoc ) ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; for ( ; ; ) { if ( ParseOperand ( Operands , Mnemonic ) ) return true ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) break ; getLexer ( ) . Lex ( ) ; } return false ; } </s>

ParseInstruction - Parse one assembly instruction .


"%s expects a compile time integer constant"

"%s expects a compile time long integer constant"

"rounding to %d bits has no effect for "

"fixed-point value with %d fractional bits"

Expand an expression EXP that calls a built-in function , with result going to TARGET if that 's convenient ( and in mode MODE if that 's convenient ) . SUBTARGET may be used as the target for computing one of EXP 's operands . IGNORE is nonzero if the value is to be ignored .


<s> static bool xtensa_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { return ( ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > ( unsigned ) ( GP_RETURN_LAST - GP_RETURN_FIRST + 1 ) * UNITS_PER_WORD ) ; } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


<s> unsigned constant_generates_xxspltiw ( vec_const_128bit_type * vsx_const ) { if ( ! TARGET_SPLAT_WORD_CONSTANT || ! TARGET_PREFIXED || ! TARGET_VSX ) return 0 ; if ( ! vsx_const -> all_words_same ) return 0 ; if ( vsx_const -> all_bytes_same ) return 0 ; if ( vsx_const -> all_half_words_same ) { unsigned short h_word = vsx_const -> half_words [ 0 ] ; short sign_h_word = ( ( h_word & 0xffff ) ^ 0x8000 ) - 0x8000 ; if ( EASY_VECTOR_15 ( sign_h_word ) ) return 0 ; } unsigned int word = vsx_const -> words [ 0 ] ; int sign_word = ( ( word & 0xffffffff ) ^ 0x80000000 ) - 0x80000000 ; if ( EASY_VECTOR_15 ( sign_word ) ) return 0 ; return vsx_const -> words [ 0 ] ; } </s>

Determine if a vector constant can be loaded with XXSPLTIW . Return zero if the XXSPLTIW instruction can not be used . Otherwise return the immediate value to be used with the XXSPLTIW instruction .


<s> riscv_vector :: vlmul_type get_vlmul ( ) const { return m_vlmul ; } </s>

Helper function to get VLMUL operand . We always have VLMUL value for all RVV instructions that have VTYPE OP .


<s>
unsigned
MSP430InstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugInstr
(
)
)
continue
;
if
(
I
->
getOpcode
(
)
!=
MSP430
::
JMP
&&
I
->
getOpcode
(
)
!=
MSP430
::
JCC
&&
I
->
getOpcode
(
)
!=
MSP430
::
Br
&&
I
->
getOpcode
(
)
!=
MSP430
::
Bm
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>


<s> bool AArch64TargetLowering :: isIntDivCheap ( EVT VT , AttributeSet Attr ) const { bool OptSize = Attr . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ; return OptSize && ! VT . isVector ( ) ; } </s>

Return true if integer divide is usually cheaper than a sequence of several shifts , adds , and multiplies for this target .


<s> bool isStore ( ) const { return Access == AccessTy :: Store ; } </s>

Returns true if this recipe is a store .


<s> bool PPCTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , MachineMemOperand :: Flags , bool * Fast ) const { if ( DisablePPCUnaligned ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( VT . isFloatingPoint ( ) && ! VT . isVector ( ) && ! Subtarget . allowsUnalignedFPAccess ( ) ) return false ; if ( VT . getSimpleVT ( ) . isVector ( ) ) { if ( Subtarget . hasVSX ( ) ) { if ( VT != MVT :: v2f64 && VT != MVT :: v2i64 && VT != MVT :: v4f32 && VT != MVT :: v4i32 ) return false ; } else { return false ; } } if ( VT == MVT :: ppcf128 ) return false ; if ( Fast ) * Fast = true ; return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> int csky_get_movedouble_length ( rtx operands [ ] ) { rtx dst = operands [ 0 ] ; rtx src = operands [ 1 ] ; if ( REG_P ( dst ) ) { if ( REG_P ( src ) ) { int dstreg = REGNO ( dst ) ; int srcreg = REGNO ( src ) ; if ( CSKY_VREG_P ( srcreg ) && CSKY_VREG_P ( dstreg ) ) return 4 ; else return 8 ; } else if ( GET_CODE ( src ) == MEM ) { rtx memexp = XEXP ( src , 0 ) ; int dstreg = REGNO ( dst ) ; struct csky_address op0 ; decompose_csky_address ( XEXP ( src , 0 ) , & op0 ) ; if ( GET_CODE ( memexp ) == LABEL_REF ) return 8 ; if ( CSKY_VREG_P ( dstreg ) ) return 4 ; return 8 ; } else if ( GET_CODE ( src ) == CONST_INT || GET_CODE ( src ) == CONST_DOUBLE ) { split_double ( src , operands + 2 , operands + 3 ) ; if ( CSKY_CONST_OK_FOR_N ( INTVAL ( operands [ 2 ] ) + 1 ) && CSKY_CONST_OK_FOR_N ( INTVAL ( operands [ 3 ] ) + 1 ) && REGNO ( operands [ 0 ] ) < 6 ) return 4 ; else return 8 ; } } else if ( GET_CODE ( dst ) == MEM && GET_CODE ( src ) == REG ) { rtx memexp = XEXP ( dst , 0 ) ; int srcreg = REGNO ( src ) ; int offset = - 1 ; if ( CSKY_VREG_P ( srcreg ) ) return 4 ; if ( GET_CODE ( memexp ) == REG ) offset = 0 ; else if ( GET_CODE ( memexp ) == PLUS ) { if ( GET_CODE ( XEXP ( memexp , 0 ) ) == REG ) offset = INTVAL ( XEXP ( memexp , 1 ) ) ; else if ( GET_CODE ( XEXP ( memexp , 1 ) ) == REG ) offset = INTVAL ( XEXP ( memexp , 0 ) ) ; else gcc_unreachable ( ) ; } else gcc_unreachable ( ) ; if ( srcreg <= 6 && offset <= 1020 ) return 4 ; else if ( ( srcreg == 7 && offset <= 1024 ) || ( srcreg <= 7 && offset == 1024 ) ) return 6 ; else return 8 ; } else gcc_unreachable ( ) ; return 0 ; } </s>

Calculate the instruction 's length for moving double-word data .


<s> bool isImm ( ) const override { return Kind == Immediate ; } </s>


<s>
bool
AArch64FrameLowering
::
restoreCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
std
::
vector
<
CalleeSavedInfo
>
&
CSIWithSVE
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
std
::
vector
<
CalleeSavedInfo
>
CSI
;
for
(
unsigned
i
=
0
;
i
<
CSIWithSVE
.
size
(
)
;
++
i
)
{
if
(
MFI
->
getStackRegionToHandleCSR
(
CSIWithSVE
[
i
]
.
getReg
(
)
)
!=
nullptr
)
continue
;
CSI
.
push_back
(
CSIWithSVE
[
i
]
)
;
}
DebugLoc
DL
;
SmallVector
<
RegPairInfo
,
8
>
RegPairs
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
computeCalleeSaveRegisterPairs
(
MF
,
CSI
,
TRI
,
RegPairs
)
;
for
(
auto
RPII
=
RegPairs
.
begin
(
)
,
RPIE
=
RegPairs
.
end
(
)
;
RPII
!=
RPIE
;
++
RPII
)
{
RegPairInfo
RPI
=
*
RPII
;
unsigned
Reg1
=
RPI
.
Reg1
;
unsigned
Reg2
=
RPI
.
Reg2
;
if
(
MFI
->
getStackRegionToHandleCSR
(
Reg1
)
)
continue
;
unsigned
LdrOpc
;
if
(
RPI
.
IsGPR
)
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPXi
:
AArch64
::
LDRXui
;
else
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPDi
:
AArch64
::
LDRDui
;
DEBUG
(
dbgs
(
)
<<
"CSR restore: ("
<<
TRI
->
getName
(
Reg1
)
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
TRI
->
getName
(
Reg2
)
;
dbgs
(
)
<<
") -> fi#("
<<
RPI
.
FrameIdx
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
RPI
.
FrameIdx
+
1
;
dbgs
(
)
<<
")\n"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
LdrOpc
)
)
;
if
(
RPI
.
isPaired
(
)
)
{
MIB
.
addReg
(
Reg2
,
getDefRegState
(
true
)
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
+
1
)
,
MachineMemOperand
::
MOLoad
,
8
,
8
)
)
;
}
MIB
.
addReg
(
Reg1
,
getDefRegState
(
true
)
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
RPI
.
Offset
)
.
setMIFlag
(
MachineInstr
::
FrameDestroy
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
)
,
MachineMemOperand
::
MOLoad
,
8
,
8
)
)
;
}
return
true
;
}
</s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> int crx_interrupt_function_p ( void ) { tree attributes ; attributes = TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ; return lookup_attribute ( "interrupt" , attributes ) != NULL_TREE ; } </s>

Return nonzero if the current function being compiled is an interrupt * function as specified by the `` interrupt '' attribute .


"\ninit_cumulative_args, fntype = 0x%.8lx"

Handle the INIT_CUMULATIVE_ARGS macro . Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is 0 .


<s> bool RISCVTargetLowering :: hasAndNotCompare ( SDValue Y ) const { EVT VT = Y . getValueType ( ) ; if ( VT . isVector ( ) ) return false ; return Subtarget . hasStdExtZbb ( ) && ! isa < ConstantSDNode > ( Y ) ; } </s>

Return true if the target should transform : ( X & Y ) == Y � ? ( ~X & Y ) == 0 ( X & Y ) ! = Y � ? ( ~X & Y ) ! = 0 .


<s> bool mayAlias ( const MachineFrameInfo * ) const override { return false ; } </s>

Returns true if this instruction 's memory access aliases the memory access of Other .


"********** Lower RefTypes IntPtr Convs **********\n"

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void emitBytes ( const uint8_t * Opcode , size_t Size ) { Ops . insert ( Ops . end ( ) , Opcode , Opcode + Size ) ; OpBegins . push_back ( OpBegins . back ( ) + Size ) ; } </s>

Emit the bytes in Data into the output .


<s>
static
MCSymbol
*
GetSymbolFromOperand
(
const
MachineOperand
&
MO
,
AsmPrinter
&
AP
)
{
const
TargetMachine
&
TM
=
AP
.
TM
;
Mangler
*
Mang
=
AP
.
Mang
;
const
DataLayout
*
DL
=
TM
.
getDataLayout
(
)
;
MCContext
&
Ctx
=
AP
.
OutContext
;
bool
isDarwin
=
Triple
(
TM
.
getTargetTriple
(
)
)
.
isOSDarwin
(
)
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
)
{
if
(
isDarwin
)
Suffix
=
"$stub"
;
}
else
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
Suffix
=
"$non_lazy_ptr"
;
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
->
getPrivateGlobalPrefix
(
)
;
unsigned
PrefixLen
=
Name
.
size
(
)
;
if
(
!
MO
.
isGlobal
(
)
)
{
assert
(
MO
.
isSymbol
(
)
&&
"Isn't a symbol reference"
)
;
Mang
->
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
)
;
}
else
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
TM
.
getNameWithPrefix
(
Name
,
GV
,
*
Mang
)
;
}
unsigned
OrigLen
=
Name
.
size
(
)
PrefixLen
;
Name
+=
Suffix
;
MCSymbol
*
Sym
=
Ctx
.
getOrCreateSymbol
(
Name
)
;
StringRef
OrigName
=
StringRef
(
Name
)
.
substr
(
PrefixLen
,
OrigLen
)
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
&&
isDarwin
)
{
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
getMachOMMI
(
AP
)
.
getFnStubEntry
(
Sym
)
;
if
(
StubSym
.
getPointer
(
)
)
return
Sym
;
if
(
MO
.
isGlobal
(
)
)
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
else
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
Ctx
.
getOrCreateSymbol
(
OrigName
)
,
false
)
;
}
return
Sym
;
}
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
{
MachineModuleInfoMachO
&
MachO
=
getMachOMMI
(
AP
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_HIDDEN_FLAG
)
MachO
.
getHiddenGVStubEntry
(
Sym
)
:
MachO
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
return
Sym
;
}
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


<s> virtual const PIC16RegisterInfo * getRegisterInfo ( ) const { return & ( InstrInfo . getRegisterInfo ( ) ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> int small_data_operand ( rtx op ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED ) { rtx sym_ref ; if ( rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA ) return 0 ; if ( DEFAULT_ABI != ABI_V4 ) return 0 ; if ( TARGET_SPE && ( SPE_VECTOR_MODE ( mode ) || FLOAT_MODE_P ( mode ) ) ) return 0 ; if ( GET_CODE ( op ) == SYMBOL_REF ) sym_ref = op ; else if ( GET_CODE ( op ) != CONST || GET_CODE ( XEXP ( op , 0 ) ) != PLUS || GET_CODE ( XEXP ( XEXP ( op , 0 ) , 0 ) ) != SYMBOL_REF || GET_CODE ( XEXP ( XEXP ( op , 0 ) , 1 ) ) != CONST_INT ) return 0 ; else { rtx sum = XEXP ( op , 0 ) ; HOST_WIDE_INT summand ; summand = INTVAL ( XEXP ( sum , 1 ) ) ; if ( summand < 0 || summand > g_switch_value ) return 0 ; sym_ref = XEXP ( sum , 0 ) ; } return SYMBOL_REF_SMALL_P ( sym_ref ) ; return 0 ; } </s>

Return 1 for an operand in small memory on V.4/eabi .


<s> bool Cpu0PassConfig :: addInstSelector ( ) { addPass ( createCpu0ISelDag ( getCpu0TargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static bool loongarch_legitimate_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { return loongarch_const_insns ( x ) > 0 ; } </s>


<s> void asm_conditional_branch ( rtx insn , rtx * operands , int n_nops , int predict_taken ) { int offset = branch_dest ( insn ) - INSN_ADDRESSES ( INSN_UID ( insn ) ) ; int len = ( offset >= - 1024 && offset <= 1022 ? 0 : offset >= - 4094 && offset <= 4096 ? 1 : 2 ) ; int bp = predict_taken && len == 0 ? 1 : cbranch_predicted_taken_p ( insn ) ; int idx = ( bp << 1 ) | ( GET_CODE ( operands [ 0 ] ) == EQ ? BRF : BRT ) ; output_asm_insn ( ccbranch_templates [ idx ] [ len ] , operands ) ; gcc_assert ( n_nops == 0 || ! bp ) ; if ( len == 0 ) while ( n_nops -- > 0 ) output_asm_insn ( "nop;" , NULL ) ; } </s>

Output INSN , which is a conditional branch instruction with operands OPERANDS . We deal with the various forms of conditional branches that can be generated by bfin_reorg to prevent the hardware from doing speculative loads , by - emitting a sufficient number of nops , if N_NOPS is nonzero , or - always emitting the branch as predicted taken , if PREDICT_TAKEN is true . Either of these is only necessary if the branch is short , otherwise the template we use ends in an unconditional jump which flushes the pipeline anyway .


<s> void SystemZPassConfig :: addPreSched2 ( ) { addPass ( createSystemZExpandPseudoPass ( getSystemZTargetMachine ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & IfConverterID ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> SMLoc getLoc ( ) const { return getParser ( ) . getTok ( ) . getLoc ( ) ; } </s>

Get the source location of the point where the field was defined .


<s> inline unsigned int function_instance :: vectors_per_tuple ( ) const { return base -> vectors_per_tuple ( ) ; } </s>

If the function operates on tuples of vectors , return the number of vectors in the tuples , otherwise return 1 .


<s> format_object < int64_t > formatImm ( int64_t Value ) const { return PrintImmHex ? formatHex ( Value ) : formatDec ( Value ) ; } </s>

Utility function to print immediates in decimal or hex .


<s> rtx m68hc11_gen_lowpart ( enum machine_mode mode , rtx x ) { if ( GET_CODE ( x ) == MEM && m68hc11_auto_inc_p ( XEXP ( x , 0 ) ) ) { return gen_rtx_MEM ( mode , XEXP ( x , 0 ) ) ; } if ( GET_CODE ( x ) == CONST_DOUBLE ) { long l [ 2 ] ; if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) { REAL_VALUE_TYPE r ; if ( GET_MODE ( x ) == SFmode ) { REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; REAL_VALUE_TO_TARGET_SINGLE ( r , l [ 0 ] ) ; } else { rtx first , second ; split_double ( x , & first , & second ) ; return second ; } if ( mode == SImode ) return GEN_INT ( l [ 0 ] ) ; return gen_int_mode ( l [ 0 ] , HImode ) ; } else { l [ 0 ] = CONST_DOUBLE_LOW ( x ) ; } switch ( mode ) { case SImode : return GEN_INT ( l [ 0 ] ) ; case HImode : gcc_assert ( GET_MODE ( x ) == SFmode ) ; return gen_int_mode ( l [ 0 ] , HImode ) ; default : gcc_unreachable ( ) ; } } if ( mode == QImode && D_REG_P ( x ) ) return gen_rtx_REG ( mode , HARD_B_REGNUM ) ; if ( GET_CODE ( x ) == SUBREG && SUBREG_BYTE ( x ) != 0 ) { switch ( mode ) { case SImode : return gen_rtx_SUBREG ( mode , SUBREG_REG ( x ) , SUBREG_BYTE ( x ) + 4 ) ; case HImode : return gen_rtx_SUBREG ( mode , SUBREG_REG ( x ) , SUBREG_BYTE ( x ) + 2 ) ; default : gcc_unreachable ( ) ; } } x = gen_lowpart ( mode , x ) ; if ( GET_CODE ( x ) == MEM ) x = copy_rtx ( x ) ; return x ; } </s>

Low and High part extraction for 68HC11 . These routines are similar to gen_lowpart and gen_highpart but they have been fixed to work for constants and 68HC11 specific registers .


"block as it would convert a WLS from forward to a "

Checks if loop has a backwards branching WLS , and if possible , fixes it .


<s> const uint16_t * VideoCore4RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const TargetFrameLowering * TFI = MF -> getTarget ( ) . getFrameLowering ( ) ; return ( TFI -> hasFP ( * MF ) ? CSR_FP_SaveList : CSR_SaveList ) ; } </s>


"Operand not supported for this instruction."

Helper function for setting instruction flag values .


<s>
StringRef
CSKYMCExpr
::
getVariantKindName
(
VariantKind
Kind
)
{
switch
(
Kind
)
{
default
:
llvm_unreachable
(
"Invalid ELF symbol kind"
)
;
case
VK_CSKY_None
:
case
VK_CSKY_ADDR
:
return
""
;
case
VK_CSKY_ADDR_HI16
:
return
"@HI16"
;
case
VK_CSKY_ADDR_LO16
:
return
"@LO16"
;
case
VK_CSKY_GOT_IMM18_BY4
:
case
VK_CSKY_GOT
:
return
"@GOT"
;
case
VK_CSKY_GOTPC
:
return
"@GOTPC"
;
case
VK_CSKY_GOTOFF
:
return
"@GOTOFF"
;
case
VK_CSKY_PLT_IMM18_BY4
:
case
VK_CSKY_PLT
:
return
"@PLT"
;
case
VK_CSKY_TLSLE
:
return
"@TPOFF"
;
case
VK_CSKY_TLSIE
:
return
"@GOTTPOFF"
;
case
VK_CSKY_TLSGD
:
return
"@TLSGD32"
;
case
VK_CSKY_TLSLDO
:
return
"@TLSLDO32"
;
case
VK_CSKY_TLSLDM
:
return
"@TLSLDM32"
;
}
}
</s>

Convert the variant kind into an ELF-appropriate modifier ( e.g .


<s> static bool mips_canonicalize_int_order_test ( enum rtx_code * code , rtx * cmp1 , machine_mode mode ) { HOST_WIDE_INT plus_one ; if ( mips_int_order_operand_ok_p ( * code , * cmp1 ) ) return true ; if ( CONST_INT_P ( * cmp1 ) ) switch ( * code ) { case LE : plus_one = trunc_int_for_mode ( UINTVAL ( * cmp1 ) + 1 , mode ) ; if ( INTVAL ( * cmp1 ) < plus_one ) { * code = LT ; * cmp1 = force_reg ( mode , GEN_INT ( plus_one ) ) ; return true ; } break ; case LEU : plus_one = trunc_int_for_mode ( UINTVAL ( * cmp1 ) + 1 , mode ) ; if ( plus_one != 0 ) { * code = LTU ; * cmp1 = force_reg ( mode , GEN_INT ( plus_one ) ) ; return true ; } break ; default : break ; } return false ; } </s>

Return true if * CMP1 ( of mode MODE ) is a valid second operand for integer ordering test * CODE , or if an equivalent combination can be formed by adjusting * CODE and * CMP1 . When returning true , update * CODE and * CMP1 with the chosen code and operand , otherwise leave them alone .


<s> void SIFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const SIMachineFunctionInfo * FuncInfo = MF . getInfo < SIMachineFunctionInfo > ( ) ; if ( FuncInfo -> isEntryFunction ( ) ) return ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const SIInstrInfo * TII = ST . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; DebugLoc DL ; unsigned ScratchExecCopy = AMDGPU :: NoRegister ; for ( const SIMachineFunctionInfo :: SGPRSpillVGPRCSR & Reg : FuncInfo -> getSGPRSpillVGPRs ( ) ) { if ( ! Reg . FI . hasValue ( ) ) continue ; if ( ScratchExecCopy == AMDGPU :: NoRegister ) { LivePhysRegs LiveRegs ( * ST . getRegisterInfo ( ) ) ; LiveRegs . addLiveIns ( MBB ) ; ScratchExecCopy = findScratchNonCalleeSaveRegister ( MF , LiveRegs , AMDGPU :: SReg_64_XEXECRegClass ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( AMDGPU :: S_OR_SAVEEXEC_B64 ) , ScratchExecCopy ) . addImm ( - 1 ) ; } TII -> loadRegFromStackSlot ( MBB , MBBI , Reg . VGPR , Reg . FI . getValue ( ) , & AMDGPU :: VGPR_32RegClass , & TII -> getRegisterInfo ( ) ) ; } if ( ScratchExecCopy != AMDGPU :: NoRegister ) { BuildMI ( MBB , MBBI , DL , TII -> get ( AMDGPU :: S_MOV_B64 ) , AMDGPU :: EXEC ) . addReg ( ScratchExecCopy ) ; } if ( hasFP ( MF ) ) { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; uint32_t NumBytes = MFI . getStackSize ( ) ; uint32_t RoundedSize = FuncInfo -> isStackRealigned ( ) ? NumBytes + MFI . getMaxAlignment ( ) : NumBytes ; const unsigned StackPtrReg = FuncInfo -> getStackPtrOffsetReg ( ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( AMDGPU :: S_SUB_U32 ) , StackPtrReg ) . addReg ( StackPtrReg ) . addImm ( RoundedSize * ST . getWavefrontSize ( ) ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } } </s>


<s> unsigned PPCInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case PPC :: LD : case PPC :: LWZ : case PPC :: LFS : case PPC :: LFD : case PPC :: RESTORE_CR : case PPC :: RESTORE_CRBIT : case PPC :: LVX : case PPC :: LXVD2X : case PPC :: QVLFDX : case PPC :: QVLFSXs : case PPC :: QVLFDXb : case PPC :: RESTORE_VRSAVE : if ( MI -> getOperand ( 1 ) . isImm ( ) && ! MI -> getOperand ( 1 ) . getImm ( ) && MI -> getOperand ( 2 ) . isFI ( ) ) { FrameIndex = MI -> getOperand ( 2 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> bool ARCInstrInfo :: isPostIncrement ( const MachineInstr & MI ) const { const MCInstrDesc & MID = MI . getDesc ( ) ; const uint64_t F = MID . TSFlags ; return ( ( F >> TSF_AddrModeOff ) & TSF_AddModeMask ) == PostInc ; } </s>

Return true for post-incremented instructions .


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT ) const override { return MVT :: i8 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> void NVPTXPassConfig :: addIRPasses ( ) { disablePass ( & PrologEpilogCodeInserterID ) ; disablePass ( & MachineCopyPropagationID ) ; disablePass ( & TailDuplicateID ) ; disablePass ( & StackMapLivenessID ) ; disablePass ( & LiveDebugValuesID ) ; disablePass ( & PostRASchedulerID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & PatchableFunctionID ) ; addPass ( createNVVMReflectPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createNVPTXImageOptimizerPass ( ) ) ; addPass ( createNVPTXAssignValidGlobalNamesPass ( ) ) ; addPass ( createGenericToNVVMPass ( ) ) ; addPass ( createNVPTXLowerKernelArgsPass ( & getNVPTXTargetMachine ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addAddressSpaceInferencePasses ( ) ; addStraightLineScalarOptimizationPasses ( ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addEarlyCSEOrGVNPass ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> int symbolic_memory_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { if ( GET_CODE ( op ) == SUBREG ) op = SUBREG_REG ( op ) ; if ( GET_CODE ( op ) != MEM ) return 0 ; op = XEXP ( op , 0 ) ; return ( GET_CODE ( op ) == SYMBOL_REF || GET_CODE ( op ) == CONST || GET_CODE ( op ) == LABEL_REF ) ; } </s>

Returns 1 if OP is a memory reference involving a symbolic constant that is not in the constant pool .


<s>
unsigned
MipsOutgoingValueHandler
::
assignCustomValue
(
CallLowering
::
ArgInfo
&
Arg
,
ArrayRef
<
CCValAssign
>
VAs
,
std
::
function
<
void
(
)
>
*
Thunk
)
{
const
CCValAssign
&
VALo
=
VAs
[
0
]
;
const
CCValAssign
&
VAHi
=
VAs
[
1
]
;
assert
(
VALo
.
getLocVT
(
)
==
MVT
::
i32
&&
VAHi
.
getLocVT
(
)
==
MVT
::
i32
&&
VALo
.
getValVT
(
)
==
MVT
::
f64
&&
VAHi
.
getValVT
(
)
==
MVT
::
f64
&&
"unexpected custom value"
)
;
auto
Unmerge
=
MIRBuilder
.
buildUnmerge
(
{
LLT
::
scalar
(
32
)
,
LLT
::
scalar
(
32
)
}
,
Arg
.
Regs
[
0
]
)
;
Register
Lo
=
Unmerge
.
getReg
(
0
)
;
Register
Hi
=
Unmerge
.
getReg
(
1
)
;
Arg
.
OrigRegs
.
assign
(
Arg
.
Regs
.
begin
(
)
,
Arg
.
Regs
.
end
(
)
)
;
Arg
.
Regs
=
{
Lo
,
Hi
}
;
if
(
!
STI
.
isLittle
(
)
)
std
::
swap
(
Lo
,
Hi
)
;
if
(
Thunk
)
{
*
Thunk
=
[
=
]
(
)
{
MIRBuilder
.
buildCopy
(
VALo
.
getLocReg
(
)
,
Lo
)
;
MIRBuilder
.
buildCopy
(
VAHi
.
getLocReg
(
)
,
Hi
)
;
}
;
return
2
;
}
MIRBuilder
.
buildCopy
(
VALo
.
getLocReg
(
)
,
Lo
)
;
MIRBuilder
.
buildCopy
(
VAHi
.
getLocReg
(
)
,
Hi
)
;
return
2
;
}
</s>

Handle custom values , which may be passed into one or more of VAs .


<s> static MachineInstr * storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , Register SrcReg , unsigned BitSize , int FrameIdx , int Offset , const TargetInstrInfo * TII , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) { unsigned SubIdx = ( BitSize == 8 ) ? X86 :: sub_8bit : X86 :: sub_16bit ; unsigned Opc = ( BitSize == 8 ) ? X86 :: MOV8mr : X86 :: MOV16mr ; if ( BitSize == TRI -> getRegSizeInBits ( * RC ) ) SubIdx = 0 ; MachineInstr * NewMI = addFrameReference ( BuildMI ( MBB , MI , DebugLoc ( ) , TII -> get ( Opc ) ) , FrameIdx , Offset ) . addReg ( SrcReg , 0 , SubIdx ) ; return NewMI ; } </s>

Store the specified register of the given register class to the specified stack frame index .


"%qE attribute applies only to initialized variables"

Handle a `` selectany '' attribute ; arguments as in struct attribute_spec.handler .


<s> bool SIInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { SIMachineFunctionInfo * MFI = MI -> getParent ( ) -> getParent ( ) -> getInfo < SIMachineFunctionInfo > ( ) ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; switch ( MI -> getOpcode ( ) ) { default : return AMDGPUInstrInfo :: expandPostRAPseudo ( MI ) ; case AMDGPU :: SI_SPILL_S512_SAVE : case AMDGPU :: SI_SPILL_S256_SAVE : case AMDGPU :: SI_SPILL_S128_SAVE : case AMDGPU :: SI_SPILL_S64_SAVE : { unsigned NumSubRegs = getNumSubRegsForSpillOp ( MI -> getOpcode ( ) ) ; unsigned FrameIndex = MI -> getOperand ( 2 ) . getImm ( ) ; for ( unsigned i = 0 , e = NumSubRegs ; i < e ; ++ i ) { SIMachineFunctionInfo :: SpilledReg Spill ; unsigned SubReg = RI . getPhysRegSubReg ( MI -> getOperand ( 1 ) . getReg ( ) , & AMDGPU :: SGPR_32RegClass , i ) ; Spill = MFI -> SpillTracker . getSpilledReg ( FrameIndex ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: V_WRITELANE_B32 ) , MI -> getOperand ( 0 ) . getReg ( ) ) . addReg ( SubReg ) . addImm ( Spill . Lane + i ) ; } MI -> eraseFromParent ( ) ; break ; } case AMDGPU :: SI_SPILL_S512_RESTORE : case AMDGPU :: SI_SPILL_S256_RESTORE : case AMDGPU :: SI_SPILL_S128_RESTORE : case AMDGPU :: SI_SPILL_S64_RESTORE : { unsigned NumSubRegs = getNumSubRegsForSpillOp ( MI -> getOpcode ( ) ) ; for ( unsigned i = 0 , e = NumSubRegs ; i < e ; ++ i ) { SIMachineFunctionInfo :: SpilledReg Spill ; unsigned FrameIndex = MI -> getOperand ( 2 ) . getImm ( ) ; unsigned SubReg = RI . getPhysRegSubReg ( MI -> getOperand ( 0 ) . getReg ( ) , & AMDGPU :: SGPR_32RegClass , i ) ; Spill = MFI -> SpillTracker . getSpilledReg ( FrameIndex ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: V_READLANE_B32 ) , SubReg ) . addReg ( MI -> getOperand ( 1 ) . getReg ( ) ) . addImm ( Spill . Lane + i ) ; } MI -> eraseFromParent ( ) ; break ; } } return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> bool ProtectJTSupportPass :: runOnMachineFunction ( MachineFunction & Func ) { if ( ! Func . protectJT ( ) ) return false ; bool modified = false ; for ( MachineFunction :: iterator MBB = Func . begin ( ) ; MBB != Func . end ( ) ; MBB ++ ) { MachineBasicBlock :: iterator MI = MBB -> begin ( ) ; while ( MI != MBB -> end ( ) ) { MachineBasicBlock :: iterator NMI = std :: next ( MI ) ; modified |= handleInst ( * MBB , MI ) ; MI = NMI ; } } return modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool MipsCCState :: originalEVTTypeIsVectorFloat ( EVT Ty ) { if ( Ty . isVector ( ) && Ty . getVectorElementType ( ) . isFloatingPoint ( ) ) return true ; return false ; } </s>

Return true if the original type was vXfXX .


<s> void sparc_expand_vcond ( machine_mode mode , rtx * operands , int ccode , int fcode ) { enum rtx_code code = signed_condition ( GET_CODE ( operands [ 3 ] ) ) ; rtx mask , cop0 , cop1 , fcmp , cmask , bshuf , gsr ; mask = gen_reg_rtx ( Pmode ) ; cop0 = operands [ 4 ] ; cop1 = operands [ 5 ] ; if ( code == LT || code == GE ) { code = swap_condition ( code ) ; std :: swap ( cop0 , cop1 ) ; } gsr = gen_rtx_REG ( DImode , SPARC_GSR_REG ) ; fcmp = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , gen_rtx_fmt_ee ( code , mode , cop0 , cop1 ) ) , fcode ) ; cmask = gen_rtx_UNSPEC ( DImode , gen_rtvec ( 2 , mask , gsr ) , ccode ) ; bshuf = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , operands [ 1 ] , operands [ 2 ] , gsr ) , UNSPEC_BSHUFFLE ) ; emit_insn ( gen_rtx_SET ( mask , fcmp ) ) ; emit_insn ( gen_rtx_SET ( gsr , cmask ) ) ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , bshuf ) ) ; } </s>

Emit code to conditionally move a combination of OPERANDS [ 1 ] and OPERANDS [ 2 ] into OPERANDS [ 0 ] in MODE , depending on the outcome of the comparison of OPERANDS [ 4 ] and OPERANDS [ 5 ] . OPERANDS [ 3 ] is the operator of the condition . FCODE is the machine code to be used for OPERANDS [ 3 ] and CCODE the machine code to be used for the condition mask .


<s>
bool
ARMBlockPlacement
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
const
ARMSubtarget
&
ST
=
MF
.
getSubtarget
<
ARMSubtarget
>
(
)
;
if
(
!
ST
.
hasLOB
(
)
)
return
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
DEBUG_PREFIX
<<
"Running on "
<<
MF
.
getName
(
)
<<
"\n"
)
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
TII
=
static_cast
<
const
ARMBaseInstrInfo
*
>
(
ST
.
getInstrInfo
(
)
)
;
BBUtils
=
std
::
unique_ptr
<
ARMBasicBlockUtils
>
(
new
ARMBasicBlockUtils
(
MF
)
)
;
MF
.
RenumberBlocks
(
)
;
BBUtils
->
computeAllBlockSizes
(
)
;
BBUtils
->
adjustBBOffsetsAfter
(
&
MF
.
front
(
)
)
;
bool
Changed
=
false
;
RevertedWhileLoops
.
clear
(
)
;
for
(
auto
*
ML
:
*
MLI
)
Changed
|=
processPostOrderLoops
(
ML
)
;
for
(
auto
*
WlsInstr
:
RevertedWhileLoops
)
Changed
|=
revertWhileToDoLoop
(
WlsInstr
)
;
return
Changed
;
}
</s>

ARM
ARM
ARM
ARM
"Running on "
"\n"
ARM
ARM
ARM


<s> bool MipsLegalizerInfo :: legalizeCustom ( MachineInstr & MI , MachineRegisterInfo & MRI , MachineIRBuilder & MIRBuilder ) const { using namespace TargetOpcode ; MIRBuilder . setInstr ( MI ) ; switch ( MI . getOpcode ( ) ) { case G_ADD : { unsigned Size = MRI . getType ( MI . getOperand ( 0 ) . getReg ( ) ) . getSizeInBits ( ) ; const LLT sHalf = LLT :: scalar ( Size / 2 ) ; unsigned RHSLow = MRI . createGenericVirtualRegister ( sHalf ) ; unsigned RHSHigh = MRI . createGenericVirtualRegister ( sHalf ) ; unsigned LHSLow = MRI . createGenericVirtualRegister ( sHalf ) ; unsigned LHSHigh = MRI . createGenericVirtualRegister ( sHalf ) ; unsigned ResLow = MRI . createGenericVirtualRegister ( sHalf ) ; unsigned ResHigh = MRI . createGenericVirtualRegister ( sHalf ) ; unsigned Carry = MRI . createGenericVirtualRegister ( sHalf ) ; unsigned TmpResHigh = MRI . createGenericVirtualRegister ( sHalf ) ; MIRBuilder . buildUnmerge ( { RHSHigh , RHSLow } , MI . getOperand ( 2 ) . getReg ( ) ) ; MIRBuilder . buildUnmerge ( { LHSHigh , LHSLow } , MI . getOperand ( 1 ) . getReg ( ) ) ; MIRBuilder . buildAdd ( TmpResHigh , LHSHigh , RHSHigh ) ; MIRBuilder . buildAdd ( ResLow , LHSLow , RHSLow ) ; MIRBuilder . buildICmp ( CmpInst :: ICMP_ULT , Carry , ResLow , LHSLow ) ; MIRBuilder . buildAdd ( ResHigh , TmpResHigh , Carry ) ; MIRBuilder . buildMerge ( MI . getOperand ( 0 ) . getReg ( ) , { ResHigh , ResLow } ) ; MI . eraseFromParent ( ) ; break ; } case G_CONSTANT : { unsigned Size = MRI . getType ( MI . getOperand ( 0 ) . getReg ( ) ) . getSizeInBits ( ) ; const LLT sHalf = LLT :: scalar ( Size / 2 ) ; const APInt & CImmValue = MI . getOperand ( 1 ) . getCImm ( ) -> getValue ( ) ; unsigned ResLow = MRI . createGenericVirtualRegister ( sHalf ) ; unsigned ResHigh = MRI . createGenericVirtualRegister ( sHalf ) ; MIRBuilder . buildConstant ( ResLow , * ConstantInt :: get ( MI . getMF ( ) -> getFunction ( ) . getContext ( ) , CImmValue . trunc ( Size / 2 ) ) ) ; MIRBuilder . buildConstant ( ResHigh , * ConstantInt :: get ( MI . getMF ( ) -> getFunction ( ) . getContext ( ) , CImmValue . lshr ( Size / 2 ) . trunc ( Size / 2 ) ) ) ; MIRBuilder . buildMerge ( MI . getOperand ( 0 ) . getReg ( ) , { ResHigh , ResLow } ) ; MI . eraseFromParent ( ) ; break ; } default : return false ; } return true ; } </s>

Called for instructions with the Custom LegalizationAction .


<s> bool ARMPassConfig :: addPreEmitPass ( ) { if ( getARMSubtarget ( ) . isThumb2 ( ) ) { if ( ! getARMSubtarget ( ) . prefers32BitThumb ( ) ) addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( & UnpackMachineBundlesID ) ; } addPass ( createARMOptimizeBarriersPass ( ) ) ; addPass ( createARMConstantIslandPass ( ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s>
SDValue
MSP430TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
SHL
:
case
ISD
::
SRL
:
case
ISD
::
SRA
:
return
LowerShifts
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
ExternalSymbol
:
return
LowerExternalSymbol
(
Op
,
DAG
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SIGN_EXTEND
:
return
LowerSIGN_EXTEND
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
return
SDValue
(
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> void HexagonFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { auto & HST = MF . getSubtarget < HexagonSubtarget > ( ) ; auto & HRI = * HST . getRegisterInfo ( ) ; SavedRegs . resize ( HRI . getNumRegs ( ) ) ; if ( MF . getInfo < HexagonMachineFunctionInfo > ( ) -> hasEHReturn ( ) ) for ( const MCPhysReg * R = HRI . getCalleeSavedRegs ( & MF ) ; * R ; ++ R ) SavedRegs . set ( * R ) ; SmallVector < unsigned , 8 > NewRegs ; expandSpillMacros ( MF , NewRegs ) ; if ( OptimizeSpillSlots && ! isOptNone ( MF ) ) optimizeSpillSlots ( MF , NewRegs ) ; if ( ! NewRegs . empty ( ) ) { MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; SetVector < const TargetRegisterClass * > SpillRCs ; SpillRCs . insert ( & Hexagon :: IntRegsRegClass ) ; for ( unsigned VR : NewRegs ) SpillRCs . insert ( MRI . getRegClass ( VR ) ) ; for ( auto * RC : SpillRCs ) { if ( ! needToReserveScavengingSpillSlots ( MF , HRI , RC ) ) continue ; unsigned Num = RC == & Hexagon :: IntRegsRegClass ? NumberScavengerSlots : 1 ; unsigned S = RC -> getSize ( ) , A = RC -> getAlignment ( ) ; for ( unsigned i = 0 ; i < Num ; i ++ ) { int NewFI = MFI . CreateSpillStackObject ( S , A ) ; RS -> addScavengingFrameIndex ( NewFI ) ; } } } TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .

Hexagon Hexagon Hexagon Hexagon 8 Hexagon::IntRegsRegClass Hexagon::IntRegsRegClass 1 0


<s> bool inside_x_p ( rtx op , bool strict ) { if ( GET_CODE ( op ) == PLUS ) { rtx lhs = XEXP ( op , 0 ) ; rtx rhs = XEXP ( op , 1 ) ; if ( TARGET_SMALL ) { if ( GET_CODE ( lhs ) == CONST_INT && ok_for_index ( rhs , strict ) ) return true ; if ( GET_CODE ( rhs ) == CONST_INT && ok_for_index ( lhs , strict ) ) return true ; } if ( data_ref_p ( lhs ) ) { if ( ok_for_index ( rhs , strict ) ) { return true ; } } if ( data_ref_p ( rhs ) ) { if ( ok_for_index ( lhs , strict ) ) { return true ; } } } return false ; } </s>


<s>
static
void
nvptx_assemble_undefined_decl
(
FILE
*
file
,
const
char
*
name
,
const_tree
decl
)
{
if
(
TREE_CODE
(
decl
)
!=
VAR_DECL
)
return
;
const
char
*
section
=
nvptx_section_for_decl
(
decl
)
;
fprintf
(
file
,
"// BEGIN%s VAR DECL: "
,
TREE_PUBLIC
(
decl
)
" GLOBAL"
:
""
)
;
assemble_name_raw
(
file
,
name
)
;
fputs
(
"\n"
,
file
)
;
HOST_WIDE_INT
size
=
int_size_in_bytes
(
TREE_TYPE
(
decl
)
)
;
fprintf
(
file
,
".extern %s .b8 "
,
section
)
;
assemble_name_raw
(
file
,
name
)
;
if
(
size
>
0
)
fprintf
(
file
,
"["
HOST_WIDE_INT_PRINT_DEC
"]"
,
size
)
;
fprintf
(
file
,
";\n\n"
)
;
}
</s>

Implement TARGET_ASM_ASSEMBLE_UNDEFINED_DECL . Write an extern declaration only for variable DECL with NAME to FILE .

nvptx
"// BEGIN%s VAR DECL: "
" GLOBAL"
""
"\n"
".extern %s .b8 "
0
"["
"]"
";\n\n"


<s> void function_builder :: append_name ( const char * name ) { obstack_grow ( & m_string_obstack , name , strlen ( name ) ) ; } </s>

Add NAME to the end of the function name being built .


<s>
rtx_code
m68k_output_compare_si
(
rtx
op0
,
rtx
op1
,
rtx_code
code
)
{
rtx_code
tmp
=
m68k_find_flags_value
(
op0
,
op1
,
code
)
;
if
(
tmp
!=
UNKNOWN
)
return
tmp
;
remember_compare_flags
(
op0
,
op1
)
;
rtx
ops
[
2
]
;
ops
[
0
]
=
op0
;
ops
[
1
]
=
op1
;
if
(
op1
==
const0_rtx
&&
(
TARGET_68020
||
TARGET_COLDFIRE
||
!
ADDRESS_REG_P
(
op0
)
)
)
output_asm_insn
(
"tst%.l %0"
,
ops
)
;
else
if
(
GET_CODE
(
op0
)
==
MEM
&&
GET_CODE
(
op1
)
==
MEM
)
output_asm_insn
(
"cmpm%.l %1,%0"
,
ops
)
;
else
if
(
REG_P
(
op1
)
||
(
!
REG_P
(
op0
)
&&
GET_CODE
(
op0
)
!=
MEM
)
)
{
output_asm_insn
(
"cmp%.l %d0,%d1"
,
ops
)
;
std
::
swap
(
flags_compare_op0
,
flags_compare_op1
)
;
return
swap_condition
(
code
)
;
}
else
if
(
!
TARGET_COLDFIRE
&&
ADDRESS_REG_P
(
op0
)
&&
GET_CODE
(
op1
)
==
CONST_INT
&&
INTVAL
(
op1
)
<
0x8000
&&
INTVAL
(
op1
)
>=
0x8000
)
output_asm_insn
(
"cmp%.w %1,%0"
,
ops
)
;
else
output_asm_insn
(
"cmp%.l %d1,%d0"
,
ops
)
;
return
code
;
}
</s>

Emit a comparison between OP0 and OP1 . CODE is the code of the comparison . It is returned , potentially modified if necessary .


<s> void loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const override { loadRegFromStack ( MBB , MBBI , DestReg , FrameIndex , RC , TRI , 0 ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> virtual const TargetRegisterClass * getRepRegClassFor ( MVT VT ) const { if ( VT == MVT :: Untyped ) return Subtarget -> hasDSP ( ) ? & Mips :: ACC64DSPRegClass : & Mips :: ACC64RegClass ; return TargetLowering :: getRepRegClassFor ( VT ) ; } </s>

Return the 'representative ' register class for the specified value type .