<s> int arm_hard_regno_mode_ok ( unsigned int regno , enum machine_mode mode ) { if ( GET_MODE_CLASS ( mode ) == MODE_CC ) return ( regno == CC_REGNUM || ( TARGET_HARD_FLOAT && TARGET_VFP && regno == VFPCC_REGNUM ) ) ; if ( TARGET_THUMB ) return ( ARM_NUM_REGS ( mode ) < 2 ) || ( regno < LAST_LO_REGNUM ) ; if ( TARGET_HARD_FLOAT && TARGET_MAVERICK && IS_CIRRUS_REGNUM ( regno ) ) return ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) || ( mode == DImode ) ; if ( TARGET_HARD_FLOAT && TARGET_VFP && IS_VFP_REGNUM ( regno ) ) { if ( mode == SFmode || mode == SImode ) return TRUE ; if ( mode == DFmode ) return ( ( regno - FIRST_VFP_REGNUM ) & 1 ) == 0 ; return FALSE ; } if ( TARGET_REALLY_IWMMXT ) { if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return mode == SImode ; if ( IS_IWMMXT_REGNUM ( regno ) ) return VALID_IWMMXT_REG_MODE ( mode ) ; } if ( regno <= LAST_ARM_REGNUM ) return ! ( TARGET_LDRD && GET_MODE_SIZE ( mode ) > 4 && ( regno & 1 ) != 0 ) ; if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return GET_MODE_CLASS ( mode ) == MODE_INT ; return ( TARGET_HARD_FLOAT && TARGET_FPA && GET_MODE_CLASS ( mode ) == MODE_FLOAT && regno >= FIRST_FPA_REGNUM && regno <= LAST_FPA_REGNUM ) ; } </s>

Returns true if REGNO is a valid register for holding a quantity of type MODE .


<s> static int m68k_sched_adjust_cost ( rtx_insn * insn , rtx link ATTRIBUTE_UNUSED , rtx_insn * def_insn , int cost ) { int delay ; if ( recog_memoized ( def_insn ) < 0 || recog_memoized ( insn ) < 0 ) return cost ; if ( sched_cfv4_bypass_data . scale == 1 ) { gcc_assert ( sched_cfv4_bypass_data . pro == def_insn && sched_cfv4_bypass_data . con == insn ) ; if ( cost < 3 ) cost = 3 ; sched_cfv4_bypass_data . pro = NULL ; sched_cfv4_bypass_data . con = NULL ; sched_cfv4_bypass_data . scale = 0 ; } else gcc_assert ( sched_cfv4_bypass_data . pro == NULL && sched_cfv4_bypass_data . con == NULL && sched_cfv4_bypass_data . scale == 0 ) ; delay = min_insn_conflict_delay ( sched_adjust_cost_state , def_insn , insn ) ; if ( delay > cost ) cost = delay ; return cost ; } </s>

Implement adjust_cost scheduler hook . Return adjusted COST of dependency LINK between DEF_INSN and INSN .


<s> static inline bool mode_supports_vmx_dform ( machine_mode mode ) { return ( ( reg_addr [ mode ] . addr_mask [ RELOAD_REG_VMX ] & RELOAD_REG_OFFSET ) != 0 ) ; } </s>

Return true if we have D-form addressing in altivec registers .


<s> static bool split_stack_arg_pointer_used_p ( void ) { if ( cfun -> machine -> split_stack_arg_pointer != NULL_RTX && ( ! REG_P ( cfun -> machine -> split_stack_arg_pointer ) || ( REGNO ( cfun -> machine -> split_stack_arg_pointer ) < FIRST_PSEUDO_REGISTER ) ) ) return true ; rtx_insn * insn ; basic_block bb = ENTRY_BLOCK_PTR_FOR_FN ( cfun ) -> next_bb ; FOR_BB_INSNS ( bb , insn ) if ( NONDEBUG_INSN_P ( insn ) ) { if ( CALL_P ( insn ) ) return false ; df_ref use ; FOR_EACH_INSN_USE ( use , insn ) { rtx x = DF_REF_REG ( use ) ; if ( REG_P ( x ) && REGNO ( x ) == 12 ) return true ; } df_ref def ; FOR_EACH_INSN_DEF ( def , insn ) { rtx x = DF_REF_REG ( def ) ; if ( REG_P ( x ) && REGNO ( x ) == 12 ) return false ; } } return bitmap_bit_p ( DF_LR_OUT ( bb ) , 12 ) ; } </s>

Return whether the split-stack arg pointer ( r12 ) is used .


<s> MachineInstr * ARMBaseInstrInfo :: duplicate ( MachineInstr * Orig , MachineFunction & MF ) const { MachineInstr * MI = TargetInstrInfoImpl :: duplicate ( Orig , MF ) ; switch ( Orig -> getOpcode ( ) ) { case ARM :: tLDRpci_pic : case ARM :: t2LDRpci_pic : { unsigned CPI = Orig -> getOperand ( 1 ) . getIndex ( ) ; unsigned PCLabelId = duplicateCPV ( MF , CPI ) ; Orig -> getOperand ( 1 ) . setIndex ( CPI ) ; Orig -> getOperand ( 2 ) . setImm ( PCLabelId ) ; break ; } } return MI ; } </s>

Clones instruction or the whole instruction bundle Orig and insert into MBB before InsertBefore .


<s>
void
ARCInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
dl
,
MCRegister
DestReg
,
MCRegister
SrcReg
,
bool
KillSrc
)
const
{
assert
(
ARC
::
GPR32RegClass
.
contains
(
SrcReg
)
&&
"Only GPR32 src copy supported."
)
;
assert
(
ARC
::
GPR32RegClass
.
contains
(
DestReg
)
&&
"Only GPR32 dest copy supported."
)
;
BuildMI
(
MBB
,
I
,
dl
,
get
(
ARC
::
MOV_rr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> static bool arc_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) { return ( arg . type != 0 && ( TREE_CODE ( TYPE_SIZE ( arg . type ) ) != INTEGER_CST || TREE_ADDRESSABLE ( arg . type ) ) ) ; } </s>

For ARC , All aggregates and arguments greater than 8 bytes are passed by reference .


"Cannot use both printf and hostcall in the same module"

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s>
SDValue
AMDGPUTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
Op
.
getNode
(
)
->
dump
(
)
;
llvm_unreachable
(
"Custom lowering code for this"
"instruction is not implemented yet!"
)
;
break
;
case
ISD
::
SIGN_EXTEND_INREG
:
return
LowerSIGN_EXTEND_INREG
(
Op
,
DAG
)
;
case
ISD
::
CONCAT_VECTORS
:
return
LowerCONCAT_VECTORS
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_SUBVECTOR
:
return
LowerEXTRACT_SUBVECTOR
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
UDIVREM
:
return
LowerUDIVREM
(
Op
,
DAG
)
;
case
ISD
::
SDIVREM
:
return
LowerSDIVREM
(
Op
,
DAG
)
;
case
ISD
::
FREM
:
return
LowerFREM
(
Op
,
DAG
)
;
case
ISD
::
FCEIL
:
return
LowerFCEIL
(
Op
,
DAG
)
;
case
ISD
::
FTRUNC
:
return
LowerFTRUNC
(
Op
,
DAG
)
;
case
ISD
::
FRINT
:
return
LowerFRINT
(
Op
,
DAG
)
;
case
ISD
::
FNEARBYINT
:
return
LowerFNEARBYINT
(
Op
,
DAG
)
;
case
ISD
::
FROUND
:
return
LowerFROUND
(
Op
,
DAG
)
;
case
ISD
::
FFLOOR
:
return
LowerFFLOOR
(
Op
,
DAG
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerSINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
UINT_TO_FP
:
return
LowerUINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_SINT
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_UINT
(
Op
,
DAG
)
;
case
ISD
::
CTLZ
:
case
ISD
::
CTLZ_ZERO_UNDEF
:
return
LowerCTLZ
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
}
return
Op
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool MipsFastISel :: fastLowerCall ( CallLoweringInfo & CLI ) { CallingConv :: ID CC = CLI . CallConv ; bool IsTailCall = CLI . IsTailCall ; bool IsVarArg = CLI . IsVarArg ; const Value * Callee = CLI . Callee ; if ( IsTailCall ) return false ; if ( IsVarArg ) return false ; MVT RetVT ; if ( CLI . RetTy -> isVoidTy ( ) ) RetVT = MVT :: isVoid ; else if ( ! isTypeLegal ( CLI . RetTy , RetVT ) ) return false ; for ( auto Flag : CLI . OutFlags ) if ( Flag . isInReg ( ) || Flag . isSRet ( ) || Flag . isNest ( ) || Flag . isByVal ( ) ) return false ; SmallVector < MVT , 16 > OutVTs ; OutVTs . reserve ( CLI . OutVals . size ( ) ) ; for ( auto * Val : CLI . OutVals ) { MVT VT ; if ( ! isTypeLegal ( Val -> getType ( ) , VT ) && ! ( VT == MVT :: i1 || VT == MVT :: i8 || VT == MVT :: i16 ) ) return false ; if ( VT . isVector ( ) || VT . getSizeInBits ( ) > 64 ) return false ; OutVTs . push_back ( VT ) ; } Address Addr ; if ( ! computeCallAddress ( Callee , Addr ) ) return false ; unsigned NumBytes ; if ( ! processCallArgs ( CLI , OutVTs , NumBytes ) ) return false ; unsigned DestAddress = materializeGV ( Addr . getGlobalValue ( ) , MVT :: i32 ) ; emitInst ( TargetOpcode :: COPY , Mips :: T9 ) . addReg ( DestAddress ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Mips :: JALR ) , Mips :: RA ) . addReg ( Mips :: T9 ) ; for ( auto Reg : CLI . OutRegs ) MIB . addReg ( Reg , RegState :: Implicit ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( CC ) ) ; CLI . Call = MIB ; for ( auto Reg : CLI . OutRegs ) MIB . addReg ( Reg , RegState :: Implicit ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( CC ) ) ; CLI . Call = MIB ; return finishCall ( CLI , RetVT , NumBytes ) ; } </s>

This method is called by target-independent code to do target- specific call lowering .


<s> void AArch64_ELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SupportDebugThreadLocalLocation = false ; } </s>

This method must be called before any actual lowering is done .


<s> HOST_WIDE_INT alpha_initial_elimination_offset ( unsigned int from , unsigned int to ATTRIBUTE_UNUSED ) { HOST_WIDE_INT ret ; ret = alpha_sa_size ( ) ; ret += ALPHA_ROUND ( current_function_outgoing_args_size ) ; switch ( from ) { case FRAME_POINTER_REGNUM : break ; case ARG_POINTER_REGNUM : ret += ( ALPHA_ROUND ( get_frame_size ( ) + current_function_pretend_args_size ) - current_function_pretend_args_size ) ; break ; default : gcc_unreachable ( ) ; } return ret ; } </s>

Define the offset between two registers , one to be eliminated , and the other its replacement , at the start of a routine .


<s> bool rs6000_is_valid_2insn_and ( rtx c , machine_mode mode ) { if ( rs6000_is_valid_mask ( c , NULL , NULL , mode ) ) return true ; unsigned HOST_WIDE_INT val = INTVAL ( c ) ; unsigned HOST_WIDE_INT bit1 = val & - val ; unsigned HOST_WIDE_INT bit2 = ( val + bit1 ) & ~ val ; unsigned HOST_WIDE_INT val1 = ( val + bit1 ) & val ; unsigned HOST_WIDE_INT bit3 = val1 & - val1 ; return rs6000_is_valid_and_mask ( GEN_INT ( val + bit3 - bit2 ) , mode ) ; } </s>

Return whether an AND with C ( a CONST_INT ) in mode MODE can be done using two machine instructions .


<s> bool X86TTIImpl :: isLegalMaskedGather ( Type * DataTy , MaybeAlign Alignment ) { if ( ! ( ST -> hasAVX512 ( ) || ( ST -> hasFastGather ( ) && ST -> hasAVX2 ( ) ) ) ) return false ; if ( auto * DataVTy = dyn_cast < VectorType > ( DataTy ) ) { unsigned NumElts = DataVTy -> getNumElements ( ) ; if ( NumElts == 1 || ! isPowerOf2_32 ( NumElts ) ) return false ; } Type * ScalarTy = DataTy -> getScalarType ( ) ; if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == 32 || IntWidth == 64 ; } </s>

Return true if the target supports masked gather .


<s> bool ARMTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , CCAssignFnForNode ( CallConv , true , isVarArg ) ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> static const char * s390_branch_condition_mnemonic ( rtx code , int inv ) { int mask ; static const char * const mnemonic [ 16 ] = { NULL , "o" , "h" , "nle" , "l" , "nhe" , "lh" , "ne" , "e" , "nlh" , "he" , "nl" , "le" , "nh" , "no" , NULL } ; if ( GET_CODE ( XEXP ( code , 0 ) ) == REG && REGNO ( XEXP ( code , 0 ) ) == CC_REGNUM && ( XEXP ( code , 1 ) == const0_rtx || ( GET_MODE ( XEXP ( code , 0 ) ) == CCRAWmode && CONST_INT_P ( XEXP ( code , 1 ) ) ) ) ) mask = s390_branch_condition_mask ( code ) ; else mask = s390_compare_and_branch_condition_mask ( code ) ; gcc_assert ( mask >= 0 ) ; if ( inv ) mask ^= 15 ; gcc_assert ( mask >= 1 && mask <= 14 ) ; return mnemonic [ mask ] ; } </s>

If INV is false , return assembler mnemonic string to implement a branch specified by CODE . If INV is true , return mnemonic for the corresponding inverted branch .


<s> bool SIInsertWaits :: runOnMachineFunction ( MachineFunction & MF ) { bool Changes = false ; TII = static_cast < const SIInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; TRI = static_cast < const SIRegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; MRI = & MF . getRegInfo ( ) ; WaitedOn = ZeroCounts ; LastIssued = ZeroCounts ; memset ( & UsedRegs , 0 , sizeof ( UsedRegs ) ) ; memset ( & DefinedRegs , 0 , sizeof ( DefinedRegs ) ) ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { Changes |= insertWait ( MBB , I , handleOperands ( * I ) ) ; pushInstruction ( * I ) ; } Changes |= insertWait ( MBB , MBB . getFirstTerminator ( ) , LastIssued ) ; } return Changes ; } </s>

runOnMachineFunction - Emit the function body .


<s> void * getAdjustedAnalysisPointer ( const void * ID ) override { if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo * ) this ; return this ; } </s>

getAdjustedAnalysisPointer - This method is used when a pass implements an analysis interface through multiple inheritance .


<s> bool HexagonInstrInfo :: areMemAccessesTriviallyDisjoint ( MachineInstr & MIa , MachineInstr & MIb , AliasAnalysis * AA ) const { int OffsetA = 0 , OffsetB = 0 ; unsigned SizeA = 0 , SizeB = 0 ; if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) || MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; if ( MIa . mayLoad ( ) && ! isMemOp ( & MIa ) && MIb . mayLoad ( ) && ! isMemOp ( & MIb ) ) return true ; unsigned BaseRegA = getBaseAndOffset ( & MIa , OffsetA , SizeA ) ; if ( ! BaseRegA || ! SizeA ) return false ; unsigned BaseRegB = getBaseAndOffset ( & MIb , OffsetB , SizeB ) ; if ( ! BaseRegB || ! SizeB ) return false ; if ( BaseRegA != BaseRegB ) return false ; if ( OffsetA > OffsetB ) { uint64_t offDiff = ( uint64_t ) ( ( int64_t ) OffsetA - ( int64_t ) OffsetB ) ; return ( SizeB <= offDiff ) ; } else if ( OffsetA < OffsetB ) { uint64_t offDiff = ( uint64_t ) ( ( int64_t ) OffsetB - ( int64_t ) OffsetA ) ; return ( SizeA <= offDiff ) ; } return false ; } </s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


getPassName - Return a nice clean name for a pass .


<s> void TMS320C64XHazardRecognizer :: EmitNoop ( ) { ResourceAssignment :: AdvanceCycle ( ) ; } </s>

EmitNoop - This callback is invoked when a noop was added to the instruction stream .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


"Slot for FPW register must be last in order to be found!"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


"internal error: cris_side_effect_mode_ok with bad operands"

Check various objections to the side-effect . Used in the test-part of an anonymous insn describing an insn with a possible side-effect . Returns nonzero if the implied side-effect is ok. code : PLUS or MULT ops : An array of rtx : es . lreg , rreg , rval , The variables multop and other_op are indexes into this , or -1 if they are not applicable . lreg : The register that gets assigned in the side-effect . rreg : One register in the side-effect expression rval : The other register , or an int . multop : An integer to multiply rval with . other_op : One of the entities of the main effect , whose mode we must consider .


<s>
std
::
string
str
(
)
const
{
std
::
string
S
;
raw_string_ostream
OS
(
S
)
;
OS
<<
"{"
;
StartInst
->
print
(
OS
,
true
)
;
OS
<<
" -> "
;
LastInst
->
print
(
OS
,
true
)
;
if
(
KillInst
)
{
OS
<<
" (kill @ "
;
KillInst
->
print
(
OS
,
true
)
;
OS
<<
")"
;
}
OS
<<
"}"
;
return
OS
.
str
(
)
;
}
</s>

Return the twine contents as a std : :string .


<s> const uint32_t * LanaiRegisterInfo :: getCallPreservedMask ( const MachineFunction & , CallingConv :: ID ) const { return CSR_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> unsigned X86RegisterInfo :: findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI ) const { const MachineFunction * MF = MBB . getParent ( ) ; if ( MF -> callsEHReturn ( ) ) return 0 ; const TargetRegisterClass & AvailableRegs = * getGPRsForTailCall ( * MF ) ; if ( MBBI == MBB . end ( ) ) return 0 ; switch ( MBBI -> getOpcode ( ) ) { default : return 0 ; case TargetOpcode :: PATCHABLE_RET : case X86 :: RET : case X86 :: RET32 : case X86 :: RET64 : case X86 :: RETI32 : case X86 :: RETI64 : case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: TCRETURNmi64 : case X86 :: EH_RETURN : case X86 :: EH_RETURN64 : { SmallSet < uint16_t , 8 > Uses ; for ( unsigned I = 0 , E = MBBI -> getNumOperands ( ) ; I != E ; ++ I ) { MachineOperand & MO = MBBI -> getOperand ( I ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , this , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } for ( auto CS : AvailableRegs ) if ( ! Uses . count ( CS ) && CS != X86 :: RIP && CS != X86 :: RSP && CS != X86 :: ESP ) return CS ; } } return 0 ; } </s>

findDeadCallerSavedReg - Return a caller-saved register that is n't live when it reaches the `` return '' instruction .


<s> static void arc_init_reg_tables ( void ) { int i ; for ( i = 0 ; i < NUM_MACHINE_MODES ; i ++ ) { machine_mode m = ( machine_mode ) i ; switch ( GET_MODE_CLASS ( m ) ) { case MODE_INT : case MODE_PARTIAL_INT : case MODE_COMPLEX_INT : if ( GET_MODE_SIZE ( m ) <= 4 ) arc_mode_class [ i ] = 1 << ( int ) S_MODE ; else if ( GET_MODE_SIZE ( m ) == 8 ) arc_mode_class [ i ] = 1 << ( int ) D_MODE ; else if ( GET_MODE_SIZE ( m ) == 16 ) arc_mode_class [ i ] = 1 << ( int ) T_MODE ; else if ( GET_MODE_SIZE ( m ) == 32 ) arc_mode_class [ i ] = 1 << ( int ) O_MODE ; else arc_mode_class [ i ] = 0 ; break ; case MODE_FLOAT : case MODE_COMPLEX_FLOAT : if ( GET_MODE_SIZE ( m ) <= 4 ) arc_mode_class [ i ] = 1 << ( int ) SF_MODE ; else if ( GET_MODE_SIZE ( m ) == 8 ) arc_mode_class [ i ] = 1 << ( int ) DF_MODE ; else if ( GET_MODE_SIZE ( m ) == 16 ) arc_mode_class [ i ] = 1 << ( int ) TF_MODE ; else if ( GET_MODE_SIZE ( m ) == 32 ) arc_mode_class [ i ] = 1 << ( int ) OF_MODE ; else arc_mode_class [ i ] = 0 ; break ; case MODE_VECTOR_INT : if ( GET_MODE_SIZE ( m ) == 4 ) arc_mode_class [ i ] = ( 1 << ( int ) S_MODE ) ; else if ( GET_MODE_SIZE ( m ) == 8 ) arc_mode_class [ i ] = ( 1 << ( int ) D_MODE ) ; else arc_mode_class [ i ] = ( 1 << ( int ) V_MODE ) ; break ; case MODE_CC : default : if ( i == ( int ) CCmode || i == ( int ) CC_ZNmode || i == ( int ) CC_Zmode || i == ( int ) CC_Cmode || i == CC_FP_GTmode || i == CC_FP_GEmode || i == CC_FP_ORDmode || i == CC_FPUmode || i == CC_FPUEmode || i == CC_FPU_UNEQmode ) arc_mode_class [ i ] = 1 << ( int ) C_MODE ; else arc_mode_class [ i ] = 0 ; break ; } } } </s>


<s>
bool
PPCRegisterInfo
::
needsFrameBaseReg
(
MachineInstr
*
MI
,
int64_t
Offset
)
const
{
assert
(
Offset
<
0
&&
"Local offset must be negative"
)
;
unsigned
OpC
=
MI
->
getOpcode
(
)
;
if
(
!
ImmToIdxMap
.
count
(
OpC
)
)
return
false
;
if
(
(
OpC
==
PPC
::
ADDI
||
OpC
==
PPC
::
ADDI8
)
&&
MI
->
getOperand
(
2
)
.
getImm
(
)
==
0
)
return
false
;
MachineBasicBlock
&
MBB
=
*
MI
->
getParent
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
PPCFrameLowering
*
PPCFI
=
static_cast
<
const
PPCFrameLowering
*
>
(
MF
.
getSubtarget
(
)
.
getFrameLowering
(
)
)
;
unsigned
StackEst
=
PPCFI
->
determineFrameLayout
(
MF
,
false
,
true
)
;
if
(
!
StackEst
)
return
false
;
Offset
+=
StackEst
;
return
!
isFrameOffsetLegal
(
MI
,
Offset
)
;
}
</s>

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .

PowerPC
PPC
0
"Local offset must be negative"
PPC::ADDI
PPC::ADDI8
2
0
PPC
PPC
PPC
PPC


<s> static int microblaze_address_cost ( rtx addr , machine_mode mode ATTRIBUTE_UNUSED , addr_space_t as ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { return COSTS_N_INSNS ( microblaze_address_insns ( addr , GET_MODE ( addr ) ) ) ; } </s>

Provide the costs of an addressing mode that contains ADDR . If ADDR is not a valid address , its cost is irrelevant .


<s> bool R600InstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { MachineOperand & MO = Cond [ 1 ] ; switch ( MO . getImm ( ) ) { case R600 :: PRED_SETE_INT : MO . setImm ( R600 :: PRED_SETNE_INT ) ; break ; case R600 :: PRED_SETNE_INT : MO . setImm ( R600 :: PRED_SETE_INT ) ; break ; case R600 :: PRED_SETE : MO . setImm ( R600 :: PRED_SETNE ) ; break ; case R600 :: PRED_SETNE : MO . setImm ( R600 :: PRED_SETE ) ; break ; default : return true ; } MachineOperand & MO2 = Cond [ 2 ] ; switch ( MO2 . getReg ( ) ) { case R600 :: PRED_SEL_ZERO : MO2 . setReg ( R600 :: PRED_SEL_ONE ) ; break ; case R600 :: PRED_SEL_ONE : MO2 . setReg ( R600 :: PRED_SEL_ZERO ) ; break ; default : return true ; } return false ; } </s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> static int csky_num_arg_regs ( machine_mode mode , const_tree type , bool is_stdarg ) { int size ; if ( type && mode == BLKmode ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; if ( TARGET_HARD_FLOAT_ABI && ! is_stdarg ) { if ( CSKY_VREG_MODE_P ( mode ) && ! TARGET_SINGLE_FPU ) return ( ( CSKY_NUM_WORDS ( size ) + 1 ) / 2 ) ; } return CSKY_NUM_WORDS ( size ) ; } </s>

Return the number of registers ( words ) needed to pass an argument of MODE and TYPE .


<s> bool X86InstrInfo :: hasLiveCondCodeDef ( MachineInstr & MI ) const { for ( const MachineOperand & MO : MI . operands ( ) ) { if ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == X86 :: EFLAGS && ! MO . isDead ( ) ) { return true ; } } return false ; } </s>

True if MI has a condition code def , e.g .


<s> void GCNPassConfig :: addPreEmitPass ( ) { addPass ( createSIMemoryLegalizerPass ( ) ) ; addPass ( createSIInsertWaitcntsPass ( ) ) ; addPass ( createSIShrinkInstructionsPass ( ) ) ; addPass ( createSIModeRegisterPass ( ) ) ; addPass ( & PostRAHazardRecognizerID ) ; addPass ( & SIRemoveShortExecBranchesID ) ; addPass ( & SIPreEmitPeepholeID ) ; addPass ( & SIInsertSkipsPassID ) ; addPass ( & BranchRelaxationPassID ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool mips_expand_vec_perm_const ( rtx operands [ 4 ] ) { struct expand_vec_perm_d d ; int i , nelt , which ; unsigned char orig_perm [ MAX_VECT_LEN ] ; rtx sel ; bool ok ; d . target = operands [ 0 ] ; d . op0 = operands [ 1 ] ; d . op1 = operands [ 2 ] ; sel = operands [ 3 ] ; d . vmode = GET_MODE ( d . target ) ; gcc_assert ( VECTOR_MODE_P ( d . vmode ) ) ; d . nelt = nelt = GET_MODE_NUNITS ( d . vmode ) ; d . testing_p = false ; for ( i = which = 0 ; i < nelt ; ++ i ) { rtx e = XVECEXP ( sel , 0 , i ) ; int ei = INTVAL ( e ) & ( 2 * nelt - 1 ) ; which |= ( ei < nelt ? 1 : 2 ) ; orig_perm [ i ] = ei ; } memcpy ( d . perm , orig_perm , MAX_VECT_LEN ) ; switch ( which ) { default : gcc_unreachable ( ) ; case 3 : d . one_vector_p = false ; if ( ! rtx_equal_p ( d . op0 , d . op1 ) ) break ; case 2 : for ( i = 0 ; i < nelt ; ++ i ) d . perm [ i ] &= nelt - 1 ; d . op0 = d . op1 ; d . one_vector_p = true ; break ; case 1 : d . op1 = d . op0 ; d . one_vector_p = true ; break ; } ok = mips_expand_vec_perm_const_1 ( & d ) ; if ( ! ok && which == 3 ) { d . op0 = operands [ 1 ] ; d . op1 = operands [ 2 ] ; d . one_vector_p = false ; memcpy ( d . perm , orig_perm , MAX_VECT_LEN ) ; ok = mips_expand_vec_perm_const_1 ( & d ) ; } return ok ; } </s>


<s>
bool
A15SDOptimizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
if
(
skipFunction
(
*
Fn
.
getFunction
(
)
)
)
return
false
;
const
ARMSubtarget
&
STI
=
Fn
.
getSubtarget
<
ARMSubtarget
>
(
)
;
if
(
!
(
STI
.
isCortexA15
(
)
&&
STI
.
hasNEON
(
)
)
)
return
false
;
TII
=
STI
.
getInstrInfo
(
)
;
TRI
=
STI
.
getRegisterInfo
(
)
;
MRI
=
&
Fn
.
getRegInfo
(
)
;
bool
Modified
=
false
;
DEBUG
(
dbgs
(
)
<<
"Running on function "
<<
Fn
.
getName
(
)
<<
"\n"
)
;
DeadInstr
.
clear
(
)
;
Replacements
.
clear
(
)
;
for
(
MachineFunction
::
iterator
MFI
=
Fn
.
begin
(
)
,
E
=
Fn
.
end
(
)
;
MFI
!=
E
;
++
MFI
)
{
for
(
MachineBasicBlock
::
iterator
MI
=
MFI
->
begin
(
)
,
ME
=
MFI
->
end
(
)
;
MI
!=
ME
;
)
{
Modified
|=
runOnInstruction
(
&
*
MI
++
)
;
}
}
for
(
std
::
set
<
MachineInstr
*
>
::
iterator
I
=
DeadInstr
.
begin
(
)
,
E
=
DeadInstr
.
end
(
)
;
I
!=
E
;
++
I
)
{
(
*
I
)
->
eraseFromParent
(
)
;
}
return
Modified
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { STI = & static_cast < const M680x0Subtarget & > ( MF . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; MFI = MF . getInfo < M680x0MachineFunctionInfo > ( ) ; FL = STI -> getFrameLowering ( ) ; bool Modified = false ; MOVEMState State ; unsigned Mask = 0 ; unsigned Reg = 0 ; int Offset = 0 ; for ( auto & MBB : MF ) { auto MI = MBB . begin ( ) , E = MBB . end ( ) ; while ( MI != E ) { auto NMI = std :: next ( MI ) ; switch ( MI -> getOpcode ( ) ) { default : if ( State . HasBase ( ) ) { State . SetEnd ( MI ) ; Finish ( MBB , State ) ; Modified = true ; } break ; case M680x0 :: MOVM32jm : Mask = MI -> getOperand ( 1 ) . getImm ( ) ; Reg = MI -> getOperand ( 0 ) . getReg ( ) ; Offset = 0 ; Modified |= ProcessMI ( MBB , MI , State , Mask , Offset , Reg , true ) ; break ; case M680x0 :: MOVM32pm : Mask = MI -> getOperand ( 2 ) . getImm ( ) ; Reg = MI -> getOperand ( 1 ) . getReg ( ) ; Offset = MI -> getOperand ( 0 ) . getImm ( ) ; Modified |= ProcessMI ( MBB , MI , State , Mask , Offset , Reg , true ) ; break ; case M680x0 :: MOVM32mj : Mask = MI -> getOperand ( 0 ) . getImm ( ) ; Reg = MI -> getOperand ( 1 ) . getReg ( ) ; Offset = 0 ; Modified |= ProcessMI ( MBB , MI , State , Mask , Offset , Reg , false ) ; break ; case M680x0 :: MOVM32mp : Mask = MI -> getOperand ( 0 ) . getImm ( ) ; Reg = MI -> getOperand ( 2 ) . getReg ( ) ; Offset = MI -> getOperand ( 1 ) . getImm ( ) ; Modified |= ProcessMI ( MBB , MI , State , Mask , Offset , Reg , false ) ; break ; } MI = NMI ; } if ( State . HasBase ( ) ) { State . SetEnd ( MI ) ; Finish ( MBB , State ) ; } } return Modified ; } </s>


<s>
AVR
::
Fixups
AVRMCExpr
::
getFixupKind
(
)
const
{
AVR
::
Fixups
Kind
=
AVR
::
Fixups
::
LastTargetFixupKind
;
switch
(
getKind
(
)
)
{
case
VK_AVR_LO8
:
Kind
=
isNegated
(
)
AVR
::
fixup_lo8_ldi_neg
:
AVR
::
fixup_lo8_ldi
;
break
;
case
VK_AVR_HI8
:
Kind
=
isNegated
(
)
AVR
::
fixup_hi8_ldi_neg
:
AVR
::
fixup_hi8_ldi
;
break
;
case
VK_AVR_HH8
:
Kind
=
isNegated
(
)
AVR
::
fixup_hh8_ldi_neg
:
AVR
::
fixup_hh8_ldi
;
break
;
case
VK_AVR_HHI8
:
Kind
=
isNegated
(
)
AVR
::
fixup_ms8_ldi_neg
:
AVR
::
fixup_ms8_ldi
;
break
;
case
VK_AVR_PM_LO8
:
Kind
=
isNegated
(
)
AVR
::
fixup_lo8_ldi_pm_neg
:
AVR
::
fixup_lo8_ldi_pm
;
break
;
case
VK_AVR_PM_HI8
:
Kind
=
isNegated
(
)
AVR
::
fixup_hi8_ldi_pm_neg
:
AVR
::
fixup_hi8_ldi_pm
;
break
;
case
VK_AVR_PM_HH8
:
Kind
=
isNegated
(
)
AVR
::
fixup_hh8_ldi_pm_neg
:
AVR
::
fixup_hh8_ldi_pm
;
break
;
case
VK_AVR_PM
:
case
VK_AVR_GS
:
Kind
=
AVR
::
fixup_16_pm
;
break
;
case
VK_AVR_LO8_GS
:
Kind
=
AVR
::
fixup_lo8_ldi_gs
;
break
;
case
VK_AVR_HI8_GS
:
Kind
=
AVR
::
fixup_hi8_ldi_gs
;
break
;
case
VK_AVR_None
:
llvm_unreachable
(
"Uninitialized expression"
)
;
}
return
Kind
;
}
</s>

getFixupKind - Get the fixup kind of this expression .


<s> SDValue MipsSETargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: LOAD : return lowerLOAD ( Op , DAG ) ; case ISD :: STORE : return lowerSTORE ( Op , DAG ) ; case ISD :: SMUL_LOHI : return lowerMulDiv ( Op , MipsISD :: Mult , true , true , DAG ) ; case ISD :: UMUL_LOHI : return lowerMulDiv ( Op , MipsISD :: Multu , true , true , DAG ) ; case ISD :: MULHS : return lowerMulDiv ( Op , MipsISD :: Mult , false , true , DAG ) ; case ISD :: MULHU : return lowerMulDiv ( Op , MipsISD :: Multu , false , true , DAG ) ; case ISD :: MUL : return lowerMulDiv ( Op , MipsISD :: Mult , true , false , DAG ) ; case ISD :: SDIVREM : return lowerMulDiv ( Op , MipsISD :: DivRem , true , true , DAG ) ; case ISD :: UDIVREM : return lowerMulDiv ( Op , MipsISD :: DivRemU , true , true , DAG ) ; case ISD :: INTRINSIC_WO_CHAIN : return lowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case ISD :: INTRINSIC_W_CHAIN : return lowerINTRINSIC_W_CHAIN ( Op , DAG ) ; case ISD :: INTRINSIC_VOID : return lowerINTRINSIC_VOID ( Op , DAG ) ; case ISD :: EXTRACT_VECTOR_ELT : return lowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case ISD :: BUILD_VECTOR : return lowerBUILD_VECTOR ( Op , DAG ) ; case ISD :: VECTOR_SHUFFLE : return lowerVECTOR_SHUFFLE ( Op , DAG ) ; } return MipsTargetLowering :: LowerOperation ( Op , DAG ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::LOAD ISD::STORE ISD::SMUL_LOHI MipsISD::Mult ISD::UMUL_LOHI MipsISD::Multu ISD::MULHS MipsISD::Mult ISD::MULHU MipsISD::Multu ISD::MUL MipsISD::Mult ISD::SDIVREM MipsISD::DivRem ISD::UDIVREM MipsISD::DivRemU ISD::INTRINSIC_WO_CHAIN ISD::INTRINSIC_W_CHAIN ISD::INTRINSIC_VOID ISD::EXTRACT_VECTOR_ELT ISD::BUILD_VECTOR ISD::VECTOR_SHUFFLE Mips


<s> static void get_pc_thunk_name ( char name [ 32 ] , unsigned int regno ) { const char * reg_name = reg_names [ regno ] ; reg_name += 1 ; if ( USE_HIDDEN_LINKONCE ) sprintf ( name , "__sparc_get_pc_thunk.%s" , reg_name ) ; else ASM_GENERATE_INTERNAL_LABEL ( name , "LADDPC" , regno ) ; } </s>

Fills in the label name that should be used for a pc thunk for the given register .


<s>
bool
Cpu0AsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
size_t
Start
=
0
,
Next
=
Name
.
find
(
'.'
)
;
StringRef
Mnemonic
=
Name
.
slice
(
Start
,
Next
)
;
if
(
Mnemonic
==
"ret"
)
Mnemonic
=
"jr"
;
Operands
.
push_back
(
Cpu0Operand
::
CreateToken
(
Mnemonic
,
NameLoc
)
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .


<s> int memory_address_length ( rtx addr , bool lea ) { struct ix86_address parts ; rtx base , index , disp ; int len ; int ok ; if ( GET_CODE ( addr ) == PRE_DEC || GET_CODE ( addr ) == POST_INC || GET_CODE ( addr ) == PRE_MODIFY || GET_CODE ( addr ) == POST_MODIFY ) return 0 ; ok = ix86_decompose_address ( addr , & parts ) ; gcc_assert ( ok ) ; len = ( parts . seg == ADDR_SPACE_GENERIC ) ? 0 : 1 ; if ( TARGET_64BIT && ! lea && ( SImode_address_operand ( addr , VOIDmode ) || ( parts . base && GET_MODE ( parts . base ) == SImode ) || ( parts . index && GET_MODE ( parts . index ) == SImode ) ) ) len ++ ; base = parts . base ; index = parts . index ; disp = parts . disp ; if ( base && SUBREG_P ( base ) ) base = SUBREG_REG ( base ) ; if ( index && SUBREG_P ( index ) ) index = SUBREG_REG ( index ) ; gcc_assert ( base == NULL_RTX || REG_P ( base ) ) ; gcc_assert ( index == NULL_RTX || REG_P ( index ) ) ; if ( base && ! index && ! disp ) { if ( base == arg_pointer_rtx || base == frame_pointer_rtx || REGNO ( base ) == SP_REG || REGNO ( base ) == BP_REG || REGNO ( base ) == R12_REG || REGNO ( base ) == R13_REG ) len ++ ; } else if ( disp && ! base && ! index ) { len += 4 ; if ( ! rip_relative_addr_p ( & parts ) ) len ++ ; } else { if ( disp ) { if ( base && satisfies_constraint_K ( disp ) ) len += 1 ; else len += 4 ; } else if ( base && ( REGNO ( base ) == BP_REG || REGNO ( base ) == R13_REG ) ) len ++ ; if ( index || base == arg_pointer_rtx || base == frame_pointer_rtx || ( base && ( REGNO ( base ) == SP_REG || REGNO ( base ) == R12_REG ) ) ) len ++ ; } return len ; } </s>

Calculate the length of the memory address in the instruction encoding . Does not include the one-byte modrm , opcode , or prefix .


<s> static bool originalTypeIsVectorFloat ( const Type * Ty ) { if ( Ty -> isVectorTy ( ) && Ty -> isFPOrFPVectorTy ( ) ) return true ; return false ; } </s>

Return true if the original type was vXfXX / vXfXX .


<s> SDNode * SparcDAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = TM . getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI -> getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> void MipsAsmPrinter :: emitInlineAsmStart ( const MCSubtargetInfo & StartInfo ) const { MipsTargetStreamer & TS = getTargetStreamer ( ) ; TS . emitDirectiveSetPush ( ) ; TS . emitDirectiveSetAt ( ) ; TS . emitDirectiveSetMacro ( ) ; TS . emitDirectiveSetReorder ( ) ; OutStreamer . AddBlankLine ( ) ; } </s>

Let the target do anything it needs to do before emitting inlineasm .


<s> bool ix86_save_reg ( unsigned int regno , bool maybe_eh_return , bool ignore_outlined ) { if ( cfun -> machine -> no_caller_saved_registers ) { rtx reg = crtl -> return_rtx ; if ( reg ) { unsigned int i = REGNO ( reg ) ; unsigned int nregs = REG_NREGS ( reg ) ; while ( nregs -- > 0 ) if ( ( i + nregs ) == regno ) return false ; } return ( df_regs_ever_live_p ( regno ) && ! fixed_regs [ regno ] && ! STACK_REGNO_P ( regno ) && ! MMX_REGNO_P ( regno ) && ( regno != HARD_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) ) ; } if ( regno == REAL_PIC_OFFSET_TABLE_REGNUM && pic_offset_table_rtx ) { if ( ix86_use_pseudo_pic_reg ( ) ) { if ( ! TARGET_64BIT && flag_pic && crtl -> profile ) return true ; } else if ( df_regs_ever_live_p ( REAL_PIC_OFFSET_TABLE_REGNUM ) || crtl -> profile || crtl -> calls_eh_return || crtl -> uses_const_pool || cfun -> has_nonlocal_label ) return ix86_select_alt_pic_regnum ( ) == INVALID_REGNUM ; } if ( crtl -> calls_eh_return && maybe_eh_return ) { unsigned i ; for ( i = 0 ; ; i ++ ) { unsigned test = EH_RETURN_DATA_REGNO ( i ) ; if ( test == INVALID_REGNUM ) break ; if ( test == regno ) return true ; } } if ( ignore_outlined && cfun -> machine -> call_ms2sysv ) { unsigned count = cfun -> machine -> call_ms2sysv_extra_regs + xlogue_layout :: MIN_REGS ; if ( xlogue_layout :: is_stub_managed_reg ( regno , count ) ) return false ; } if ( crtl -> drap_reg && regno == REGNO ( crtl -> drap_reg ) && ! cfun -> machine -> no_drap_save_restore ) return true ; return ( df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) && ( regno != HARD_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) ) ; } </s>


<s> static unsigned rs6000_add_stmt_cost ( void * data , int count , enum vect_cost_for_stmt kind , struct _stmt_vec_info * stmt_info , int misalign , enum vect_cost_model_location where ) { rs6000_cost_data * cost_data = ( rs6000_cost_data * ) data ; unsigned retval = 0 ; if ( flag_vect_cost_model ) { tree vectype = stmt_info ? stmt_vectype ( stmt_info ) : NULL_TREE ; int stmt_cost = rs6000_builtin_vectorization_cost ( kind , vectype , misalign ) ; stmt_cost += adjust_vectorization_cost ( kind , stmt_info ) ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( stmt_info ) ) count *= 50 ; retval = ( unsigned ) ( count * stmt_cost ) ; cost_data -> cost [ where ] += retval ; if ( ( kind == vec_to_scalar || kind == vec_perm || kind == vec_promote_demote || kind == vec_construct || kind == scalar_to_vec ) || ( where == vect_body && kind == vector_stmt ) ) rs6000_vect_nonmem = true ; } return retval ; } </s>


<s> bool AArch64CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) . isZero ( ) ) continue ; ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , F . getCallingConv ( ) ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; AArch64FunctionInfo * FuncInfo = MF . getInfo < AArch64FunctionInfo > ( ) ; uint64_t StackOffset = Handler . StackUsed ; if ( F . isVarArg ( ) ) { auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; if ( ! Subtarget . isTargetDarwin ( ) ) { return false ; } StackOffset = alignTo ( Handler . StackUsed , Subtarget . isTargetILP32 ( ) ? 4 : 8 ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( 4 , StackOffset , true ) ) ; } if ( doesCalleeRestoreStack ( F . getCallingConv ( ) , MF . getTarget ( ) . Options . GuaranteedTailCallOpt ) ) { StackOffset = alignTo ( StackOffset , 16 ) ; FuncInfo -> setArgumentStackToRestore ( StackOffset ) ; } FuncInfo -> setBytesInStackArgArea ( StackOffset ) ; auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; if ( Subtarget . hasCustomCallingConv ( ) ) Subtarget . getRegisterInfo ( ) -> UpdateCustomCalleeSavedRegs ( MF ) ; handleMustTailForwardedRegisters ( MIRBuilder , AssignFn ) ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> std :: pair < SDValue , SDValue > SystemZSelectionDAGInfo :: EmitTargetCodeForStrcmp ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Src1 , SDValue Src2 , MachinePointerInfo Op1PtrInfo , MachinePointerInfo Op2PtrInfo ) const { SDVTList VTs = DAG . getVTList ( Src1 . getValueType ( ) , MVT :: i32 , MVT :: Other ) ; SDValue Unused = DAG . getNode ( SystemZISD :: STRCMP , DL , VTs , Chain , Src2 , Src1 , DAG . getConstant ( 0 , DL , MVT :: i32 ) ) ; SDValue CCReg = Unused . getValue ( 1 ) ; Chain = Unused . getValue ( 2 ) ; return std :: make_pair ( addIPMSequence ( DL , CCReg , DAG ) , Chain ) ; } </s>

Emit target-specific code that performs a strcmp , in cases where that is faster than a libcall .


<s> void MipsOutgoingValueHandler :: assignValueToReg ( Register ValVReg , Register PhysReg , CCValAssign VA ) { Register ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildCopy ( PhysReg , ExtReg ) ; MIB . addUse ( PhysReg , RegState :: Implicit ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> static machine_mode rs6000_floatn_mode ( int n , bool extended ) { if ( extended ) { switch ( n ) { case 32 : return DFmode ; case 64 : if ( TARGET_FLOAT128_KEYWORD ) return ( FLOAT128_IEEE_P ( TFmode ) ) ? TFmode : KFmode ; else return VOIDmode ; case 128 : return VOIDmode ; default : gcc_unreachable ( ) ; } } else { switch ( n ) { case 32 : return SFmode ; case 64 : return DFmode ; case 128 : if ( TARGET_FLOAT128_KEYWORD ) return ( FLOAT128_IEEE_P ( TFmode ) ) ? TFmode : KFmode ; else return VOIDmode ; default : return VOIDmode ; } } } </s>


<s> bool DLXInstrInfo :: areMemAccessesTriviallyDisjoint ( MachineInstr & MIa , MachineInstr & MIb , AliasAnalysis * ) const { return false ; } </s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> TargetPassConfig * HexagonTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new HexagonPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s>
void
HexagonFrameLowering
::
processFunctionBeforeFrameFinalized
(
MachineFunction
&
MF
,
RegScavenger
*
RS
)
const
{
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
bool
HasAlloca
=
MFI
->
hasVarSizedObjects
(
)
;
bool
NeedsAlign
=
(
MFI
->
getMaxAlignment
(
)
>
getStackAlignment
(
)
)
;
if
(
!
HasAlloca
||
!
NeedsAlign
)
return
;
unsigned
LFS
=
MFI
->
getLocalFrameSize
(
)
;
for
(
int
i
=
0
,
e
=
MFI
->
getObjectIndexEnd
(
)
;
i
!=
e
;
++
i
)
{
if
(
!
MFI
->
isSpillSlotObjectIndex
(
i
)
||
MFI
->
isDeadObjectIndex
(
i
)
)
continue
;
unsigned
S
=
MFI
->
getObjectSize
(
i
)
;
unsigned
A
=
std
::
max
(
MFI
->
getObjectAlignment
(
i
)
,
8U
)
;
MFI
->
setObjectAlignment
(
i
,
8
)
;
LFS
=
alignTo
(
LFS
+
S
,
A
)
;
MFI
->
mapLocalFrameObject
(
i
,
LFS
)
;
}
MFI
->
setLocalFrameSize
(
LFS
)
;
unsigned
A
=
MFI
->
getLocalFrameMaxAlign
(
)
;
assert
(
A
<=
8
&&
"Unexpected local frame alignment"
)
;
if
(
A
==
0
)
MFI
->
setLocalFrameMaxAlign
(
8
)
;
MFI
->
setUseLocalStackAllocationBlock
(
true
)
;
unsigned
AP
=
0
;
if
(
const
MachineInstr
*
AI
=
getAlignaInstr
(
MF
)
)
AP
=
AI
->
getOperand
(
0
)
.
getReg
(
)
;
auto
&
HMFI
=
*
MF
.
getInfo
<
HexagonMachineFunctionInfo
>
(
)
;
HMFI
.
setStackAlignBasePhysReg
(
AP
)
;
}
</s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> const LatticeCell & get ( unsigned R ) const { if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) return Bottom ; MapType :: const_iterator F = Map . find ( R ) ; if ( F != Map . end ( ) ) return F -> second ; return Top ; } </s>

Get the generated Value for a given VPValue and given Part and Lane .


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static bool aarch_macro_fusion_pair_p ( rtx_insn * prev , rtx_insn * curr ) { rtx prev_set = single_set ( prev ) ; rtx curr_set = single_set ( curr ) ; if ( ! prev_set || ! curr_set ) return false ; if ( any_condjump_p ( curr ) ) return false ; if ( ! arm_macro_fusion_p ( ) ) return false ; if ( current_tune -> fusible_ops & tune_params :: FUSE_AES_AESMC && aarch_crypto_can_dual_issue ( prev , curr ) ) return true ; if ( current_tune -> fusible_ops & tune_params :: FUSE_MOVW_MOVT && arm_sets_movw_movt_fusible_p ( prev_set , curr_set ) ) return true ; return false ; } </s>

Implement TARGET_SCHED_MACRO_FUSION_PAIR_P . Return true if PREV and CURR should be kept together during scheduling .


<s> const std :: string & getName ( ) const { return Name ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> unsigned MipsRegisterInfo :: getPICCallReg ( void ) { return Mips :: T9 ; } </s>


<s> const SpillSlot * getCalleeSavedSpillSlots ( unsigned & NumEntries ) const override { static const SpillSlot Offsets [ ] = { { Hexagon :: R17 , - 4 } , { Hexagon :: R16 , - 8 } , { Hexagon :: D8 , - 8 } , { Hexagon :: R19 , - 12 } , { Hexagon :: R18 , - 16 } , { Hexagon :: D9 , - 16 } , { Hexagon :: R21 , - 20 } , { Hexagon :: R20 , - 24 } , { Hexagon :: D10 , - 24 } , { Hexagon :: R23 , - 28 } , { Hexagon :: R22 , - 32 } , { Hexagon :: D11 , - 32 } , { Hexagon :: R25 , - 36 } , { Hexagon :: R24 , - 40 } , { Hexagon :: D12 , - 40 } , { Hexagon :: R27 , - 44 , { Hexagon :: R26 , - 48 , { Hexagon :: D13 , - 48 } } ; NumEntries = array_lengthof ( Offsets ) ; return Offsets ; } bool assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const override ; bool needsAligna ( const MachineFunction & MF ) const ; MachineInstr * getAlignaInstr ( MachineFunction & MF ) const ; private : typedef std :: vector < CalleeSavedInfo > CSIVect ; void expandAlloca ( MachineInstr * AI , const HexagonInstrInfo & TII , unsigned SP , unsigned CF ) const ; void insertPrologueInBlock ( MachineBasicBlock & MBB ) const ; void insertEpilogueInBlock ( MachineBasicBlock & MBB ) const ; bool insertCSRSpillsInBlock ( MachineBasicBlock & MBB , const CSIVect & CSI , const HexagonRegisterInfo & HRI ) const ; bool insertCSRRestoresInBlock ( MachineBasicBlock & MBB , const CSIVect & CSI , const HexagonRegisterInfo & HRI ) const ; void adjustForCalleeSavedRegsSpillCall ( MachineFunction & MF ) const ; bool replacePredRegPseudoSpillCode ( MachineFunction & MF ) const ; bool replaceVecPredRegPseudoSpillCode ( MachineFunction & MF ) const ; void findShrunkPrologEpilog ( MachineFunction & MF , MachineBasicBlock * & PrologB , MachineBasicBlock * & EpilogB ) const ; bool shouldInlineCSR ( llvm :: MachineFunction & , const CSIVect & ) const ; bool useSpillFunction ( MachineFunction & MF , const CSIVect & CSI ) const ; bool useRestoreFunction ( MachineFunction & MF , const CSIVect & CSI ) const ; } </s>

getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs , that contains an entry for each callee saved register that must be spilled to a particular stack location if it is spilled .


<s>
StringRef
getPassName
(
)
const
override
{
return
"ARC Branch Finalization Pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> rtx loongarch_emit_move ( rtx dest , rtx src ) { return ( can_create_pseudo_p ( ) ? emit_move_insn ( dest , src ) : emit_move_insn_1 ( dest , src ) ) ; } </s>

Emit a move from SRC to DEST . Assume that the move expanders can handle all moves if ! can_create_pseudo_p ( ) . The distinction is important because , unlike emit_move_insn , the move expanders know how to force Pmode objects into the constant pool even when the constant pool address is not itself legitimate .


<s> bool HexagonGenInsert :: removeDeadCode ( MachineDomTreeNode * N ) { bool Changed = false ; typedef GraphTraits < MachineDomTreeNode * > GTN ; for ( auto I = GTN :: child_begin ( N ) , E = GTN :: child_end ( N ) ; I != E ; ++ I ) Changed |= removeDeadCode ( * I ) ; MachineBasicBlock * B = N -> getBlock ( ) ; std :: vector < MachineInstr * > Instrs ; for ( auto I = B -> rbegin ( ) , E = B -> rend ( ) ; I != E ; ++ I ) Instrs . push_back ( & * I ) ; for ( auto I = Instrs . begin ( ) , E = Instrs . end ( ) ; I != E ; ++ I ) { MachineInstr * MI = * I ; unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == TargetOpcode :: LIFETIME_START || Opc == TargetOpcode :: LIFETIME_END ) continue ; bool Store = false ; if ( MI -> isInlineAsm ( ) || ! MI -> isSafeToMove ( nullptr , Store ) ) continue ; bool AllDead = true ; SmallVector < unsigned , 2 > Regs ; for ( const MachineOperand & MO : MI -> operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned R = MO . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) || ! MRI -> use_nodbg_empty ( R ) ) { AllDead = false ; break ; } Regs . push_back ( R ) ; } if ( ! AllDead ) continue ; B -> erase ( MI ) ; for ( unsigned I = 0 , N = Regs . size ( ) ; I != N ; ++ I ) MRI -> markUsesInDebugValueAsUndef ( Regs [ I ] ) ; Changed = true ; } return Changed ; } </s>

Remove all dead instructions between the I and E .


<s> static int ix86_fp_cmp_code_to_pcmp_immediate ( enum rtx_code code ) { switch ( code ) { case EQ : return 0x00 ; case NE : return 0x04 ; case GT : return 0x0e ; case LE : return 0x02 ; case GE : return 0x0d ; case LT : return 0x01 ; case UNLE : return 0x0a ; case UNLT : return 0x09 ; case UNGE : return 0x05 ; case UNGT : return 0x06 ; case UNEQ : return 0x18 ; case LTGT : return 0x0c ; case ORDERED : return 0x07 ; case UNORDERED : return 0x03 ; default : gcc_unreachable ( ) ; } } </s>

Helper for ix86_cmp_code_to_pcmp_immediate for fp modes .


<s>
static
void
process_cfa_adjust_cfa
(
FILE
*
asm_out_file
,
rtx
pat
,
rtx
insn
,
bool
unwind
,
bool
frame
)
{
rtx
dest
=
SET_DEST
(
pat
)
;
rtx
src
=
SET_SRC
(
pat
)
;
if
(
dest
==
stack_pointer_rtx
)
{
if
(
GET_CODE
(
src
)
==
PLUS
)
{
rtx
op0
=
XEXP
(
src
,
0
)
;
rtx
op1
=
XEXP
(
src
,
1
)
;
gcc_assert
(
op0
==
dest
&&
GET_CODE
(
op1
)
==
CONST_INT
)
;
if
(
INTVAL
(
op1
)
<
0
)
{
gcc_assert
(
!
frame_pointer_needed
)
;
if
(
unwind
)
fprintf
(
asm_out_file
,
"\t.fframe "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
INTVAL
(
op1
)
)
;
}
else
process_epilogue
(
asm_out_file
,
insn
,
unwind
,
frame
)
;
}
else
{
gcc_assert
(
src
==
hard_frame_pointer_rtx
)
;
process_epilogue
(
asm_out_file
,
insn
,
unwind
,
frame
)
;
}
}
else
if
(
dest
==
hard_frame_pointer_rtx
)
{
gcc_assert
(
src
==
stack_pointer_rtx
)
;
gcc_assert
(
frame_pointer_needed
)
;
if
(
unwind
)
fprintf
(
asm_out_file
,
"\t.vframe r%d\n"
,
ia64_dbx_register_number
(
REGNO
(
dest
)
)
)
;
}
else
gcc_unreachable
(
)
;
}
</s>

This function processes a SET pattern for REG_CFA_ADJUST_CFA .


"For each split Type there should be exactly one VReg."

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


"%qE attribute only applies to functions"

"%qE attribute argument not an integer constant"

"%qE attribute argument should be between 0 to 255"

Handle an 'function_vector ' attribute ; arguments as in struct attribute_spec.handler .


<s> bool SPUPassConfig :: addInstSelector ( ) { PM -> add ( createSPUISelDag ( getSPUTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> tree ix86_builtin_reciprocal ( tree fndecl ) { enum ix86_builtins fn_code = ( enum ix86_builtins ) DECL_MD_FUNCTION_CODE ( fndecl ) ; switch ( fn_code ) { case IX86_BUILTIN_SQRTPS_NR : return ix86_get_builtin ( IX86_BUILTIN_RSQRTPS_NR ) ; case IX86_BUILTIN_SQRTPS_NR256 : return ix86_get_builtin ( IX86_BUILTIN_RSQRTPS_NR256 ) ; default : return NULL_TREE ; } } </s>

Returns a code for a target-specific builtin that implements reciprocal of the function , or NULL_TREE if not available .


<s> DFAPacketizer * R600InstrInfo :: CreateTargetScheduleState ( const TargetSubtargetInfo & STI ) const { const InstrItineraryData * II = STI . getInstrItineraryData ( ) ; return static_cast < const AMDGPUSubtarget & > ( STI ) . createDFAPacketizer ( II ) ; } </s>

Create machine specific model for scheduling .


<s>
static
void
vax_output_mi_thunk
(
FILE
*
file
,
tree
thunk
ATTRIBUTE_UNUSED
,
HOST_WIDE_INT
delta
,
HOST_WIDE_INT
vcall_offset
ATTRIBUTE_UNUSED
,
tree
function
)
{
fprintf
(
file
,
"\t.word 0x0ffc\n\taddl2 $"
HOST_WIDE_INT_PRINT_DEC
,
delta
)
;
asm_fprintf
(
file
,
",4(%Rap)\n"
)
;
fprintf
(
file
,
"\tjmp "
)
;
assemble_name
(
file
,
XSTR
(
XEXP
(
DECL_RTL
(
function
)
,
0
)
,
0
)
)
;
fprintf
(
file
,
"+2\n"
)
;
}
</s>

Output code to add DELTA to the first argument , and then jump to FUNCTION . Used for C++ multiple inheritance . .mask ^m < r2 , r3 , r4 , r5 , r6 , r7 , r8 , r9 , r10 , r11 > # conservative entry mask addl2 $ DELTA , 4 ( ap ) # adjust first argument jmp FUNCTION+2 # jump beyond FUNCTION 's entry mask


"alias without a base object is not yet supported on AIX"

Set up the AsmPrinter when we are working on a new module .


<s> MCELFStreamer & MipsTargetELFStreamer :: getStreamer ( ) { return static_cast < MCELFStreamer & > ( Streamer ) ; } </s>

Return the output streamer for the assembler .


<s> bool ARMBaseInstrInfo :: ClobbersPredicate ( MachineInstr & MI , std :: vector < MachineOperand > & Pred , bool SkipDead ) const { bool Found = false ; for ( unsigned i = 0 , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; bool ClobbersCPSR = MO . isRegMask ( ) && MO . clobbersPhysReg ( ARM :: CPSR ) ; bool IsCPSR = MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == ARM :: CPSR ; if ( ClobbersCPSR || IsCPSR ) { const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( MCID . TSFlags & ARMII :: ThumbArithFlagSetting && MO . isDead ( ) && SkipDead ) continue ; Pred . push_back ( MO ) ; Found = true ; } } return Found ; } </s>

If the specified instruction defines any predicate or condition code register ( s ) used for predication , returns true as well as the definition predicate ( s ) by reference .

ARM ARM 0 ARM::CPSR ARM::CPSR ARMII::ThumbArithFlagSetting


<s> bool pa_return_in_memory ( tree type , tree fntype ATTRIBUTE_UNUSED ) { return ( int_size_in_bytes ( type ) > ( TARGET_64BIT ? 16 : 8 ) || int_size_in_bytes ( type ) <= 0 ) ; } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


<s> static const char * ix86_mangle_fundamental_type ( tree type ) { switch ( TYPE_MODE ( type ) ) { case TFmode : return "g" ; case XFmode : return "e" ; default : return NULL ; } } </s>

Return the mangling of TYPE if it is an extended fundamental type .


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> const MMIXInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> void MipsGOT :: split ( ) { m_MergedLocalSymbols . clear ( ) ; m_MergedGlobalSymbols . clear ( ) ; size_t uniqueCount = 0 ; for ( SymbolUniqueMapType :: const_iterator it = m_InputGlobalSymbols . begin ( ) , end = m_InputGlobalSymbols . end ( ) ; it != end ; ++ it ) { if ( it -> second ) ++ uniqueCount ; } m_MultipartList . back ( ) . m_LocalNum -= m_InputLocalSymbols . size ( ) ; m_MultipartList . back ( ) . m_GlobalNum -= uniqueCount ; m_MultipartList . back ( ) . m_Inputs . erase ( m_pInput ) ; m_MultipartList . push_back ( GOTMultipart ( m_InputLocalSymbols . size ( ) , m_InputGlobalSymbols . size ( ) ) ) ; m_MultipartList . back ( ) . m_Inputs . insert ( m_pInput ) ; } </s>

Split into substrings around the occurrences of a separator character .


<s> int symbolic_operand ( register rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { switch ( GET_CODE ( op ) ) { case SYMBOL_REF : case LABEL_REF : return 1 ; case CONST : op = XEXP ( op , 0 ) ; return ( ( GET_CODE ( XEXP ( op , 0 ) ) == SYMBOL_REF || GET_CODE ( XEXP ( op , 0 ) ) == LABEL_REF ) && GET_CODE ( XEXP ( op , 1 ) ) == CONST_INT ) ; default : return 0 ; } } </s>

Return 1 if X contains a symbolic expression . We know these expressions will have one of a few well defined forms , so we need only check those forms .


"Should only have an r11 thunk on 64-bit targets"

runOnMachineFunction - Emit the function body .


<s> void AMDGPUAsmBackend :: relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const { unsigned RelaxedOpcode = AMDGPU :: getSOPPWithRelaxation ( Inst . getOpcode ( ) ) ; Res . setOpcode ( RelaxedOpcode ) ; Res . addOperand ( Inst . getOperand ( 0 ) ) ; return ; } </s>

Relax the instruction in the given fragment to the next wider instruction .

AMDGPU AMDGPU AMDGPU::getSOPPWithRelaxation 0


<s> static int thumb1_extra_regs_pushed ( arm_stack_offsets * offsets , bool for_prologue ) { HOST_WIDE_INT amount ; unsigned long live_regs_mask = offsets -> saved_regs_mask ; unsigned long l_mask = live_regs_mask & ( for_prologue ? 0x40ff : 0xff ) ; unsigned long high_regs_pushed = bit_count ( live_regs_mask & 0x0f00 ) ; int n_free , reg_base , size ; if ( ! for_prologue && frame_pointer_needed ) amount = offsets -> locals_base - offsets -> saved_regs ; else amount = offsets -> outgoing_args - offsets -> saved_regs ; if ( ! optimize_size && amount != 512 ) return 0 ; if ( high_regs_pushed != 0 ) return 0 ; if ( l_mask == 0 && ( for_prologue || TARGET_BACKTRACE || ( live_regs_mask & 1 << LR_REGNUM ) == 0 || TARGET_INTERWORK || crtl -> args . pretend_args_size != 0 ) ) return 0 ; if ( for_prologue && ( ( flag_pic && arm_pic_register != INVALID_REGNUM ) || ( ! frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0 ) ) ) return 0 ; reg_base = 0 ; n_free = 0 ; if ( ! for_prologue ) { size = arm_size_return_regs ( ) ; reg_base = ARM_NUM_INTS ( size ) ; live_regs_mask >>= reg_base ; } while ( reg_base + n_free < 8 && ! ( live_regs_mask & 1 ) && ( for_prologue || call_used_regs [ reg_base + n_free ] ) ) { live_regs_mask >>= 1 ; n_free ++ ; } if ( n_free == 0 ) return 0 ; gcc_assert ( amount / 4 * 4 == amount ) ; if ( amount >= 512 && ( amount - n_free * 4 ) < 512 ) return ( amount - 508 ) / 4 ; if ( amount <= n_free * 4 ) return amount / 4 ; return 0 ; } </s>

Given the stack offsets and register mask in OFFSETS , decide how many additional registers to push instead of subtracting a constant from SP . For epilogues the principle is the same except we use pop . FOR_PROLOGUE indicates which we 're generating .


<s> static bool or1k_rtx_costs ( rtx x , machine_mode mode , int outer_code , int , int * total , bool ) { switch ( GET_CODE ( x ) ) { case CONST_INT : if ( x == const0_rtx ) * total = 0 ; else if ( ( outer_code == PLUS || outer_code == XOR || outer_code == MULT ) && satisfies_constraint_I ( x ) ) * total = 0 ; else if ( ( outer_code == AND || outer_code == IOR ) && satisfies_constraint_K ( x ) ) * total = 0 ; else if ( satisfies_constraint_I ( x ) || satisfies_constraint_K ( x ) || satisfies_constraint_M ( x ) ) * total = 2 ; else * total = COSTS_N_INSNS ( 2 ) ; return true ; case CONST_DOUBLE : * total = ( x == CONST0_RTX ( mode ) ? 0 : COSTS_N_INSNS ( 2 ) ) ; return true ; case HIGH : * total = 2 ; return true ; case LO_SUM : * total = ( outer_code == MEM ? 0 : 2 ) ; return true ; case CONST : case SYMBOL_REF : case LABEL_REF : if ( outer_code == LO_SUM || outer_code == HIGH ) * total = 0 ; else { * total = COSTS_N_INSNS ( 1 + ( outer_code != MEM ) ) ; } return true ; case PLUS : if ( outer_code == MEM ) * total = 0 ; break ; default : break ; } return false ; } </s>


<s> int fr30_check_multiple_regs ( rtx * operands , int num_operands , int descending ) { if ( descending ) { unsigned int prev_regno = 0 ; while ( num_operands -- ) { if ( GET_CODE ( operands [ num_operands ] ) != REG ) return 0 ; if ( REGNO ( operands [ num_operands ] ) < prev_regno ) return 0 ; prev_regno = REGNO ( operands [ num_operands ] ) ; } } else { unsigned int prev_regno = CONDITION_CODE_REGNUM ; while ( num_operands -- ) { if ( GET_CODE ( operands [ num_operands ] ) != REG ) return 0 ; if ( REGNO ( operands [ num_operands ] ) > prev_regno ) return 0 ; prev_regno = REGNO ( operands [ num_operands ] ) ; } } return 1 ; } </s>

Returns true iff all the registers in the operands array are in descending or ascending order .


<s> void AnalyzeCallOperands ( const SmallVectorImpl < ISD :: OutputArg > & Outs , CCAssignFn Fn ) { ArgIsFixed . clear ( ) ; for ( unsigned i = 0 ; i < Outs . size ( ) ; ++ i ) ArgIsFixed . push_back ( Outs [ i ] . IsFixed ) ; ArgIsShortVector . clear ( ) ; for ( unsigned i = 0 ; i < Outs . size ( ) ; ++ i ) ArgIsShortVector . push_back ( IsShortVectorType ( Outs [ i ] . ArgVT ) ) ; CCState :: AnalyzeCallOperands ( Outs , Fn ) ; } </s>

AnalyzeCallOperands - Same as above except it takes vectors of types and argument flags .


<s> const PatmosTargetMachine & getTargetMachine ( ) const { return TM ; } </s>

Return the target machine ( if available ) .


<s> ScheduleHazardRecognizer * Thumb2InstrInfo :: CreateTargetPostRAHazardRecognizer ( const InstrItineraryData & II ) const { return ( ScheduleHazardRecognizer * ) new Thumb2HazardRecognizer ( II ) ; } </s>

Allocate and return a hazard recognizer to use for by non-scheduling passes .


<s> bool ARMSubtarget :: useFastISel ( ) const { if ( ForceFastISel ) return true ; if ( ! hasV6Ops ( ) ) return false ; return TM . Options . EnableFastISel && ( ( isTargetMachO ( ) && ! isThumb1Only ( ) ) || ( isTargetLinux ( ) && ! isThumb ( ) ) || ( isTargetNaCl ( ) && ! isThumb ( ) ) ) ; } </s>


<s> bool ARCRegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot .


<s> static bool nios2_simple_const_p ( const_rtx cst ) { if ( ! CONST_INT_P ( cst ) ) return false ; HOST_WIDE_INT val = INTVAL ( cst ) ; return SMALL_INT ( val ) || SMALL_INT_UNSIGNED ( val ) || UPPER16_INT ( val ) ; } </s>

Return true if CST is a constant within range of movi/movui/movhi .


<s> void BT :: reset ( ) { EdgeExec . clear ( ) ; InstrExec . clear ( ) ; Map . clear ( ) ; ReachedBB . clear ( ) ; ReachedBB . reserve ( MF . size ( ) ) ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
Register
:
OS
<<
"<register x"
<<
getReg
(
)
<<
">"
;
break
;
case
Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> static bool expand_vec_perm_movs ( struct expand_vec_perm_d * d ) { machine_mode vmode = d -> vmode ; unsigned i , nelt = d -> nelt ; rtx x ; if ( d -> one_operand_p ) return false ; if ( ! ( TARGET_SSE && vmode == V4SFmode ) && ! ( TARGET_MMX_WITH_SSE && vmode == V2SFmode ) && ! ( TARGET_SSE2 && vmode == V2DFmode ) ) return false ; if ( d -> perm [ 0 ] != nelt && d -> perm [ 0 ] != 0 ) return false ; for ( i = 1 ; i < nelt ; ++ i ) if ( d -> perm [ i ] != i + nelt - d -> perm [ 0 ] ) return false ; if ( d -> testing_p ) return true ; if ( d -> perm [ 0 ] == nelt ) x = gen_rtx_VEC_MERGE ( vmode , d -> op1 , d -> op0 , GEN_INT ( 1 ) ) ; else x = gen_rtx_VEC_MERGE ( vmode , d -> op0 , d -> op1 , GEN_INT ( 1 ) ) ; emit_insn ( gen_rtx_SET ( d -> target , x ) ) ; return true ; } </s>

A subroutine of ix86_expand_vec_perm_builtin_1 . Try to implement D using movss or movsd .


<s> EVT VETargetLowering :: getSetCCResultType ( const DataLayout & , LLVMContext & , EVT VT ) const { return MVT :: i64 ; } </s>

Return the value type to use for ISD : :SETCC .


<s> bool ARM64LoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { if ( ! DoLoadStoreOpt ) return false ; const TargetMachine & TM = Fn . getTarget ( ) ; TII = static_cast < const ARM64InstrInfo * > ( TM . getInstrInfo ( ) ) ; TRI = TM . getRegisterInfo ( ) ; bool Modified = false ; for ( auto & MBB : Fn ) Modified |= optimizeBlock ( MBB ) ; return Modified ; } </s>


<s> const F2003fRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


Return true if the vector misalignment factor is supported by the target .


<s> int function_arg_regno_p ( int r ) { return ( r >= 8 && r <= 25 ) ; } </s>

Return true when register may be used to pass function parameters .


<s> void v850_output_local ( FILE * file , tree decl , const char * name , int size , int align ) { fprintf ( file , "%s" , LOCAL_ASM_OP ) ; assemble_name ( file , name ) ; fprintf ( file , "\n" ) ; ASM_OUTPUT_ALIGNED_DECL_COMMON ( file , decl , name , size , align ) ; } </s>

Called via the macro ASM_OUTPUT_DECL_LOCAL


<s> bool SHUXIPassConfig :: addInstSelector ( ) { addPass ( createSHUXIISelDag ( getSHUXITargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


runOnMachineFunction - Emit the function body .


<s> void TeakRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { dbgs ( ) << "eliminateFrameIndex\n" ; MachineInstr & MI = * II ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ; unsigned FI = FIOp . getIndex ( ) ; unsigned ImmOpIdx = 0 ; switch ( MI . getOpcode ( ) ) { default : return ; case Teak :: STORE_REG_TO_STACK_PSEUDO_16 : case Teak :: STORE_REG_TO_STACK_PSEUDO_TRUNC16 : case Teak :: STORE_REG_TO_STACK_PSEUDO_32 : case Teak :: LOAD_REG_FROM_STACK_PSEUDO_16 : case Teak :: LOAD_REG_FROM_STACK_PSEUDO_16_SEXT40 : case Teak :: LOAD_REG_FROM_STACK_PSEUDO_16_ZEXT40 : case Teak :: LOAD_REG_FROM_STACK_PSEUDO_32_SEXT40 : ImmOpIdx = FIOperandNum + 1 ; break ; } MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ; int Offset = MFI . getObjectOffset ( FI ) + MFI . getStackSize ( ) + ImmOp . getImm ( ) ; FIOp . ChangeToRegister ( Teak :: R7 , false ) ; ImmOp . setImm ( - ( Offset >> 1 ) - 1 ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static int arm_adjust_cost ( rtx_insn * insn , rtx link , rtx_insn * dep , int cost ) { rtx i_pat , d_pat ; if ( TARGET_THUMB1 && REG_NOTE_KIND ( link ) == 0 && recog_memoized ( insn ) == CODE_FOR_cbranchsi4_insn && recog_memoized ( dep ) >= 0 && get_attr_conds ( dep ) == CONDS_SET ) return 0 ; if ( current_tune -> sched_adjust_cost != NULL ) { if ( ! current_tune -> sched_adjust_cost ( insn , link , dep , & cost ) ) return cost ; } if ( REG_NOTE_KIND ( link ) == REG_DEP_ANTI || REG_NOTE_KIND ( link ) == REG_DEP_OUTPUT ) return 0 ; if ( REG_NOTE_KIND ( link ) == 0 && CALL_P ( insn ) ) return 1 ; if ( ( i_pat = single_set ( insn ) ) != NULL && MEM_P ( SET_SRC ( i_pat ) ) && ( d_pat = single_set ( dep ) ) != NULL && MEM_P ( SET_DEST ( d_pat ) ) ) { rtx src_mem = XEXP ( SET_SRC ( i_pat ) , 0 ) ; if ( ( GET_CODE ( src_mem ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( src_mem ) ) || reg_mentioned_p ( stack_pointer_rtx , src_mem ) || reg_mentioned_p ( frame_pointer_rtx , src_mem ) || reg_mentioned_p ( hard_frame_pointer_rtx , src_mem ) ) return 1 ; } return cost ; } </s>

This function implements the target macro TARGET_SCHED_ADJUST_COST . It corrects the value of COST based on the relationship between INSN and DEP through the dependence LINK . It returns the new value . There is a per-core adjust_cost hook to adjust scheduler costs and the per-core hook can choose to completely override the generic adjust_cost function . Only put bits of code into arm_adjust_cost that are common across all cores .


<s> TargetLowering :: AtomicExpansionKind RISCVTargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size == 8 || Size == 16 ) return AtomicExpansionKind :: MaskedIntrinsic ; return AtomicExpansionKind :: None ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> SMLoc getStartLoc ( ) const { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> static void s390_save_gprs_to_fprs ( void ) { int i ; if ( ! TARGET_Z10 || ! TARGET_HARD_FLOAT || ! crtl -> is_leaf ) return ; for ( i = 6 ; i < 16 ; i ++ ) { if ( FP_REGNO_P ( cfun_gpr_save_slot ( i ) ) ) { rtx_insn * insn = emit_move_insn ( gen_rtx_REG ( DImode , cfun_gpr_save_slot ( i ) ) , gen_rtx_REG ( DImode , i ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_REGISTER , PATTERN ( insn ) ) ; } } } </s>


<s> static int thumb2_legitimate_address_p ( machine_mode mode , rtx x , int strict_p ) { bool use_ldrd ; enum rtx_code code = GET_CODE ( x ) ; if ( TARGET_HAVE_MVE && VALID_MVE_MODE ( mode ) ) return mve_vector_mem_operand ( mode , x , strict_p ) ; if ( arm_address_register_rtx_p ( x , strict_p ) ) return 1 ; use_ldrd = ( TARGET_LDRD && ( mode == DImode || mode == DFmode ) ) ; if ( code == POST_INC || code == PRE_DEC || ( ( code == PRE_INC || code == POST_DEC ) && ( use_ldrd || GET_MODE_SIZE ( mode ) <= 4 ) ) ) return arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) ; else if ( ( code == POST_MODIFY || code == PRE_MODIFY ) && arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) && GET_CODE ( XEXP ( x , 1 ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( x , 1 ) , 0 ) , XEXP ( x , 0 ) ) ) { rtx addend = XEXP ( XEXP ( x , 1 ) , 1 ) ; HOST_WIDE_INT offset ; if ( ! CONST_INT_P ( addend ) ) return 0 ; offset = INTVAL ( addend ) ; if ( GET_MODE_SIZE ( mode ) <= 4 ) return ( offset > - 256 && offset < 256 ) ; return ( use_ldrd && offset > - 1024 && offset < 1024 && ( offset & 3 ) == 0 ) ; } else if ( reload_completed && ( code == LABEL_REF || ( code == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ) ) ) return 1 ; else if ( mode == TImode || ( TARGET_NEON && VALID_NEON_STRUCT_MODE ( mode ) ) || ( TARGET_HAVE_MVE && VALID_MVE_STRUCT_MODE ( mode ) ) ) return 0 ; else if ( code == PLUS ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; return ( ( arm_address_register_rtx_p ( xop0 , strict_p ) && ( thumb2_legitimate_index_p ( mode , xop1 , strict_p ) || ( ! strict_p && will_be_in_index_register ( xop1 ) ) ) ) || ( arm_address_register_rtx_p ( xop1 , strict_p ) && thumb2_legitimate_index_p ( mode , xop0 , strict_p ) ) ) ; } else if ( can_avoid_literal_pool_for_label_p ( x ) ) return 0 ; else if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && code == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) && ! ( flag_pic && symbol_mentioned_p ( get_pool_constant ( x ) ) && ! pcrel_constant_p ( get_pool_constant ( x ) ) ) ) return 1 ; return 0 ; } </s>

Return nonzero if X is a valid Thumb-2 address operand .


<s> bool ARMBaseInstrInfo :: shouldSink ( const MachineInstr & MI ) const { if ( isPredicated ( MI ) ) return true ; MachineBasicBlock :: const_iterator Next = & MI ; ++ Next ; unsigned SrcReg , SrcReg2 ; int CmpMask , CmpValue ; if ( Next != MI . getParent ( ) -> end ( ) && analyzeCompare ( * Next , SrcReg , SrcReg2 , CmpMask , CmpValue ) && isRedundantFlagInstr ( & * Next , SrcReg , SrcReg2 , CmpValue , & MI ) ) return false ; return true ; } </s>

Return true if the instruction should be sunk by MachineSink .


<s> void MipsSETargetLowering :: addMSAIntType ( MVT :: SimpleValueType Ty , const TargetRegisterClass * RC ) { addRegisterClass ( Ty , RC ) ; for ( unsigned Opc = 0 ; Opc < ISD :: BUILTIN_OP_END ; ++ Opc ) setOperationAction ( Opc , Ty , Expand ) ; setOperationAction ( ISD :: BITCAST , Ty , Legal ) ; setOperationAction ( ISD :: LOAD , Ty , Legal ) ; setOperationAction ( ISD :: STORE , Ty , Legal ) ; setOperationAction ( ISD :: EXTRACT_VECTOR_ELT , Ty , Custom ) ; setOperationAction ( ISD :: INSERT_VECTOR_ELT , Ty , Legal ) ; setOperationAction ( ISD :: BUILD_VECTOR , Ty , Custom ) ; setOperationAction ( ISD :: ADD , Ty , Legal ) ; setOperationAction ( ISD :: AND , Ty , Legal ) ; setOperationAction ( ISD :: CTLZ , Ty , Legal ) ; setOperationAction ( ISD :: CTPOP , Ty , Legal ) ; setOperationAction ( ISD :: MUL , Ty , Legal ) ; setOperationAction ( ISD :: OR , Ty , Legal ) ; setOperationAction ( ISD :: SDIV , Ty , Legal ) ; setOperationAction ( ISD :: SREM , Ty , Legal ) ; setOperationAction ( ISD :: SHL , Ty , Legal ) ; setOperationAction ( ISD :: SRA , Ty , Legal ) ; setOperationAction ( ISD :: SRL , Ty , Legal ) ; setOperationAction ( ISD :: SUB , Ty , Legal ) ; setOperationAction ( ISD :: SMAX , Ty , Legal ) ; setOperationAction ( ISD :: SMIN , Ty , Legal ) ; setOperationAction ( ISD :: UDIV , Ty , Legal ) ; setOperationAction ( ISD :: UREM , Ty , Legal ) ; setOperationAction ( ISD :: UMAX , Ty , Legal ) ; setOperationAction ( ISD :: UMIN , Ty , Legal ) ; setOperationAction ( ISD :: VECTOR_SHUFFLE , Ty , Custom ) ; setOperationAction ( ISD :: VSELECT , Ty , Legal ) ; setOperationAction ( ISD :: XOR , Ty , Legal ) ; if ( Ty == MVT :: v4i32 || Ty == MVT :: v2i64 ) { setOperationAction ( ISD :: FP_TO_SINT , Ty , Legal ) ; setOperationAction ( ISD :: FP_TO_UINT , Ty , Legal ) ; setOperationAction ( ISD :: SINT_TO_FP , Ty , Legal ) ; setOperationAction ( ISD :: UINT_TO_FP , Ty , Legal ) ; } setOperationAction ( ISD :: SETCC , Ty , Legal ) ; setCondCodeAction ( ISD :: SETNE , Ty , Expand ) ; setCondCodeAction ( ISD :: SETGE , Ty , Expand ) ; setCondCodeAction ( ISD :: SETGT , Ty , Expand ) ; setCondCodeAction ( ISD :: SETUGE , Ty , Expand ) ; setCondCodeAction ( ISD :: SETUGT , Ty , Expand ) ; } </s>

Enable MSA support for the given integer type and Register class .

Mips Mips MVT::SimpleValueType 0 ISD::BUILTIN_OP_END ISD::BITCAST ISD::LOAD ISD::STORE ISD::EXTRACT_VECTOR_ELT ISD::INSERT_VECTOR_ELT ISD::BUILD_VECTOR ISD::ADD ISD::AND ISD::CTLZ ISD::CTPOP ISD::MUL ISD::OR ISD::SDIV ISD::SREM ISD::SHL ISD::SRA ISD::SRL ISD::SUB ISD::SMAX ISD::SMIN ISD::UDIV ISD::UREM ISD::UMAX ISD::UMIN ISD::VECTOR_SHUFFLE ISD::VSELECT ISD::XOR MVT::v4i32 MVT::v2i64 ISD::FP_TO_SINT ISD::FP_TO_UINT ISD::SINT_TO_FP ISD::UINT_TO_FP ISD::SETCC ISD::SETNE ISD::SETGE ISD::SETGT ISD::SETUGE ISD::SETUGT


<s> void ix86_d_register_target_info ( void ) { const struct d_target_info_spec handlers [ ] = { { "floatAbi" , ix86_d_handle_target_float_abi } , { "objectFormat" , ix86_d_handle_target_object_format } , { NULL , NULL } , } ; d_add_target_info_handlers ( handlers ) ; } </s>


<s>
SDValue
OR1KTargetLowering
::
LowerCall
(
TargetLowering
::
CallLoweringInfo
&
CLI
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SelectionDAG
&
DAG
=
CLI
.
DAG
;
SDLoc
&
dl
=
CLI
.
DL
;
SmallVector
<
ISD
::
OutputArg
,
32
>
&
Outs
=
CLI
.
Outs
;
SmallVector
<
SDValue
,
32
>
&
OutVals
=
CLI
.
OutVals
;
SmallVector
<
ISD
::
InputArg
,
32
>
&
Ins
=
CLI
.
Ins
;
SDValue
Chain
=
CLI
.
Chain
;
SDValue
Callee
=
CLI
.
Callee
;
bool
&
isTailCall
=
CLI
.
IsTailCall
;
CallingConv
::
ID
CallConv
=
CLI
.
CallConv
;
bool
isVarArg
=
CLI
.
IsVarArg
;
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
OutVals
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .


<s> bool RISCVPassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createBarrierNoopPass ( ) ) ; } return false ; } </s>


<s> static bool mips_valid_pointer_mode ( scalar_int_mode mode ) { return mode == SImode || ( TARGET_64BIT && mode == DImode ) ; } </s>


<s> NVPTXSubtarget :: NVPTXSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const NVPTXTargetMachine & TM ) : NVPTXGenSubtargetInfo ( TT , CPU , CPU , FS ) , PTXVersion ( 0 ) , SmVersion ( 20 ) , TM ( TM ) , TLInfo ( TM , initializeSubtargetDependencies ( CPU , FS ) ) { } </s>

This constructor initializes the data members to match that of the specified module .


<s> SDValue XCoreSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , bool AlwaysInline , bool MustPreserveCheriCapabilities , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { unsigned SizeBitWidth = Size . getValueSizeInBits ( ) ; if ( ! AlwaysInline && Alignment >= Align ( 4 ) && DAG . MaskedValueIsZero ( Size , APInt ( SizeBitWidth , 3 ) ) ) { const TargetLowering & TLI = * DAG . getSubtarget ( ) . getTargetLowering ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; Entry . Node = Src ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMCPY ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalFunctionSymbol ( "__memcpy_4" ) , std :: move ( Args ) ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .


<s> unsigned X86FastISel :: fastMaterializeFloatZero ( const ConstantFP * CF ) { MVT VT ; if ( ! isTypeLegal ( CF -> getType ( ) , VT ) ) return 0 ; bool HasAVX512 = Subtarget -> hasAVX512 ( ) ; unsigned Opc = 0 ; const TargetRegisterClass * RC = nullptr ; switch ( VT . SimpleTy ) { default : return 0 ; case MVT :: f32 : if ( X86ScalarSSEf32 ) { Opc = HasAVX512 ? X86 :: AVX512_FsFLD0SS : X86 :: FsFLD0SS ; RC = HasAVX512 ? & X86 :: FR32XRegClass : & X86 :: FR32RegClass ; } else { Opc = X86 :: LD_Fp032 ; RC = & X86 :: RFP32RegClass ; } break ; case MVT :: f64 : if ( X86ScalarSSEf64 ) { Opc = HasAVX512 ? X86 :: AVX512_FsFLD0SD : X86 :: FsFLD0SD ; RC = HasAVX512 ? & X86 :: FR64XRegClass : & X86 :: FR64RegClass ; } else { Opc = X86 :: LD_Fp064 ; RC = & X86 :: RFP64RegClass ; } break ; case MVT :: f80 : return 0 ; } unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; return ResultReg ; } </s>

Emit the floating-point constant +0.0 in a register using target- specific logic .


<s> SDValue ARMTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : return PerformADDCombine ( N , DCI ) ; case ISD :: SUB : return PerformSUBCombine ( N , DCI ) ; case ARMISD :: FMRRD : return PerformFMRRDCombine ( N , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> static void ix86_function_specific_restore ( struct gcc_options * opts , struct cl_target_option * ptr ) { enum processor_type old_tune = ix86_tune ; enum processor_type old_arch = ix86_arch ; unsigned int ix86_arch_mask ; int i ; opts -> x_flag_pic = flag_pic ; ix86_arch = ( enum processor_type ) ptr -> arch ; ix86_schedule = ( enum attr_cpu ) ptr -> schedule ; ix86_tune = ( enum processor_type ) ptr -> tune ; x86_prefetch_sse = ptr -> prefetch_sse ; opts -> x_ix86_branch_cost = ptr -> branch_cost ; ix86_tune_defaulted = ptr -> tune_defaulted ; ix86_arch_specified = ptr -> arch_specified ; opts -> x_ix86_isa_flags_explicit = ptr -> x_ix86_isa_flags_explicit ; opts -> x_ix86_isa_flags2_explicit = ptr -> x_ix86_isa_flags2_explicit ; opts -> x_recip_mask_explicit = ptr -> x_recip_mask_explicit ; opts -> x_ix86_arch_string = ptr -> x_ix86_arch_string ; opts -> x_ix86_tune_string = ptr -> x_ix86_tune_string ; opts -> x_ix86_cmodel = ptr -> x_ix86_cmodel ; opts -> x_ix86_abi = ptr -> x_ix86_abi ; opts -> x_ix86_asm_dialect = ptr -> x_ix86_asm_dialect ; opts -> x_ix86_branch_cost = ptr -> x_ix86_branch_cost ; opts -> x_ix86_dump_tunes = ptr -> x_ix86_dump_tunes ; opts -> x_ix86_force_align_arg_pointer = ptr -> x_ix86_force_align_arg_pointer ; opts -> x_ix86_force_drap = ptr -> x_ix86_force_drap ; opts -> x_ix86_incoming_stack_boundary_arg = ptr -> x_ix86_incoming_stack_boundary_arg ; opts -> x_ix86_pmode = ptr -> x_ix86_pmode ; opts -> x_ix86_preferred_stack_boundary_arg = ptr -> x_ix86_preferred_stack_boundary_arg ; opts -> x_ix86_recip_name = ptr -> x_ix86_recip_name ; opts -> x_ix86_regparm = ptr -> x_ix86_regparm ; opts -> x_ix86_section_threshold = ptr -> x_ix86_section_threshold ; opts -> x_ix86_sse2avx = ptr -> x_ix86_sse2avx ; opts -> x_ix86_stack_protector_guard = ptr -> x_ix86_stack_protector_guard ; opts -> x_ix86_stringop_alg = ptr -> x_ix86_stringop_alg ; opts -> x_ix86_tls_dialect = ptr -> x_ix86_tls_dialect ; opts -> x_ix86_tune_ctrl_string = ptr -> x_ix86_tune_ctrl_string ; opts -> x_ix86_tune_memcpy_strategy = ptr -> x_ix86_tune_memcpy_strategy ; opts -> x_ix86_tune_memset_strategy = ptr -> x_ix86_tune_memset_strategy ; opts -> x_ix86_tune_no_default = ptr -> x_ix86_tune_no_default ; opts -> x_ix86_veclibabi_type = ptr -> x_ix86_veclibabi_type ; ix86_tune_cost = processor_target_table [ ix86_tune ] . cost ; if ( opts -> x_optimize_size ) ix86_cost = & ix86_size_cost ; else ix86_cost = ix86_tune_cost ; if ( old_arch != ix86_arch ) { ix86_arch_mask = 1u << ix86_arch ; for ( i = 0 ; i < X86_ARCH_LAST ; ++ i ) ix86_arch_features [ i ] = ! ! ( initial_ix86_arch_features [ i ] & ix86_arch_mask ) ; } if ( old_tune != ix86_tune ) set_ix86_tune_features ( ix86_tune , false ) ; } </s>


<s> void emitInst ( uint32_t Inst ) { char Buffer [ 4 ] ; for ( unsigned I = 0 ; I < 4 ; ++ I ) { Buffer [ I ] = uint8_t ( Inst ) ; Inst >>= 8 ; } EmitA64MappingSymbol ( ) ; MCELFStreamer :: EmitBytes ( StringRef ( Buffer , 4 ) ) ; } </s>

Callback used to implement the .inst directive .


<s> bool BPFAdjustOpt :: runOnModule ( Module & M ) { Mod = & M ; for ( Function & F : M ) for ( auto & BB : F ) { adjustBasicBlock ( BB ) ; for ( auto & I : BB ) adjustInst ( I ) ; } return insertPassThrough ( ) ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> void AMDGPUInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << getRegisterName ( RegNo ) ; } </s>


Implements TARGET_ASM_FILE_START . Output the assembly header .


<s> void MOSInstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register DestReg , unsigned SubIdx , const MachineInstr & Orig , const TargetRegisterInfo & TRI ) const { if ( Orig . getOpcode ( ) == MOS :: LDImm16 ) { MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( & Orig ) ; MI -> removeOperand ( 1 ) ; MI -> substituteRegister ( MI -> getOperand ( 0 ) . getReg ( ) , DestReg , SubIdx , TRI ) ; MI -> setDesc ( get ( MOS :: LDImm16Remat ) ) ; MBB . insert ( I , MI ) ; } else { TargetInstrInfo :: reMaterialize ( MBB , I , DestReg , SubIdx , Orig , TRI ) ; } } </s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


"invalid conversion from type %<__vector_quad%>"

"invalid conversion to type %<__vector_quad%>"

"invalid conversion from type %<__vector_pair%>"

"invalid conversion to type %<__vector_pair%>"

"invalid conversion from type %<* __vector_quad%>"

"invalid conversion to type %<* __vector_quad%>"

"invalid conversion from type %<* __vector_pair%>"

"invalid conversion to type %<* __vector_pair%>"


<s> bool AVRDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < AVRSubtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> void PatmosInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { DebugLoc DL ; BuildMI ( MBB , MI , DL , get ( Patmos :: NOP ) ) . addReg ( Patmos :: NoRegister ) . addImm ( 0 ) ; } </s>

Insert a noop into the instruction stream at the specified point .

Patmos Patmos Patmos::NOP Patmos::NoRegister 0


<s>
static
void
s390_output_indirect_thunk_function
(
unsigned
int
regno
,
bool
z10_p
)
{
tree
decl
;
char
thunk_label
[
32
]
;
int
i
;
if
(
z10_p
)
sprintf
(
thunk_label
,
TARGET_INDIRECT_BRANCH_THUNK_NAME_EXRL
,
regno
)
;
else
sprintf
(
thunk_label
,
TARGET_INDIRECT_BRANCH_THUNK_NAME_EX
,
INDIRECT_BRANCH_THUNK_REGNUM
,
regno
)
;
decl
=
build_decl
(
BUILTINS_LOCATION
,
FUNCTION_DECL
,
get_identifier
(
thunk_label
)
,
build_function_type_list
(
void_type_node
,
NULL_TREE
)
)
;
DECL_RESULT
(
decl
)
=
build_decl
(
BUILTINS_LOCATION
,
RESULT_DECL
,
NULL_TREE
,
void_type_node
)
;
TREE_PUBLIC
(
decl
)
=
1
;
TREE_STATIC
(
decl
)
=
1
;
DECL_IGNORED_P
(
decl
)
=
1
;
if
(
USE_HIDDEN_LINKONCE
)
{
cgraph_node
::
create
(
decl
)
->
set_comdat_group
(
DECL_ASSEMBLER_NAME
(
decl
)
)
;
targetm
.
asm_out
.
unique_section
(
decl
,
0
)
;
switch_to_section
(
get_named_section
(
decl
,
,
0
)
)
;
targetm
.
asm_out
.
globalize_label
(
asm_out_file
,
thunk_label
)
;
fputs
(
"\t.hidden\t"
,
asm_out_file
)
;
assemble_name
(
asm_out_file
,
thunk_label
)
;
putc
(
'\n'
,
asm_out_file
)
;
ASM_DECLARE_FUNCTION_NAME
(
asm_out_file
,
thunk_label
,
decl
)
;
}
else
{
switch_to_section
(
text_section
)
;
ASM_OUTPUT_LABEL
(
asm_out_file
,
thunk_label
)
;
}
DECL_INITIAL
(
decl
)
=
make_node
(
BLOCK
)
;
current_function_decl
=
decl
;
allocate_struct_function
(
decl
,
false
)
;
init_function_start
(
decl
)
;
cfun
->
is_thunk
=
true
;
first_function_block_is_cold
=
false
;
final_start_function
(
emit_barrier
(
)
,
asm_out_file
,
1
)
;
if
(
flag_asynchronous_unwind_tables
&&
flag_dwarf2_cfi_asm
)
{
fputs
(
"\t.cfi_signal_frame\n"
,
asm_out_file
)
;
fprintf
(
asm_out_file
,
"\t.cfi_return_column %d\n"
,
regno
)
;
for
(
i
=
0
;
i
<
FPR15_REGNUM
;
i
++
)
fprintf
(
asm_out_file
,
"\t.cfi_same_value %s\n"
,
reg_names
[
i
]
)
;
}
if
(
z10_p
)
{
if
(
!
TARGET_CPU_Z10
)
{
fputs
(
"\t.machine push\n"
,
asm_out_file
)
;
fputs
(
"\t.machine z10\n"
,
asm_out_file
)
;
}
if
(
!
TARGET_ZARCH
)
fputs
(
"\t.machinemode zarch\n"
,
asm_out_file
)
;
fputs
(
"\texrl\t0,1f\n"
,
asm_out_file
)
;
if
(
!
TARGET_ZARCH
)
fputs
(
"\t.machinemode esa\n"
,
asm_out_file
)
;
if
(
!
TARGET_CPU_Z10
)
fputs
(
"\t.machine pop\n"
,
asm_out_file
)
;
}
else
if
(
TARGET_CPU_ZARCH
)
{
fprintf
(
asm_out_file
,
"\tlarl\t%%r%d,1f\n"
,
INDIRECT_BRANCH_THUNK_REGNUM
)
;
fprintf
(
asm_out_file
,
"\tex\t0,0(%%r%d)\n"
,
INDIRECT_BRANCH_THUNK_REGNUM
)
;
}
else
gcc_unreachable
(
)
;
fputs
(
"0:\tj\t0b\n"
,
asm_out_file
)
;
fprintf
(
asm_out_file
,
"1:\tbr\t%%r%d\n"
,
regno
)
;
final_end_function
(
)
;
init_insn_lengths
(
)
;
free_after_compilation
(
cfun
)
;
set_cfun
(
)
;
current_function_decl
=
;
}
</s>

Output an indirect branch trampoline for target register REGNO .


<s> static void replace_constant_pool_with_broadcast ( rtx_insn * insn ) { subrtx_ptr_iterator :: array_type array ; FOR_EACH_SUBRTX_PTR ( iter , array , & PATTERN ( insn ) , ALL ) { rtx * loc = * iter ; rtx x = * loc ; rtx broadcast_mem , vec_dup , constant , first ; machine_mode mode ; if ( ! MEM_P ( x ) || ! SYMBOL_REF_P ( XEXP ( x , 0 ) ) || ! CONSTANT_POOL_ADDRESS_P ( XEXP ( x , 0 ) ) ) continue ; mode = GET_MODE ( x ) ; if ( ! VECTOR_MODE_P ( mode ) ) return ; constant = get_pool_constant ( XEXP ( x , 0 ) ) ; if ( GET_CODE ( constant ) != CONST_VECTOR ) return ; if ( GET_MODE ( constant ) != mode ) { constant = simplify_subreg ( mode , constant , GET_MODE ( constant ) , 0 ) ; if ( constant == NULL_RTX || GET_CODE ( constant ) != CONST_VECTOR ) return ; } first = XVECEXP ( constant , 0 , 0 ) ; for ( int i = 1 ; i < GET_MODE_NUNITS ( mode ) ; ++ i ) { rtx tmp = XVECEXP ( constant , 0 , i ) ; if ( ! rtx_equal_p ( tmp , first ) ) return ; } broadcast_mem = force_const_mem ( GET_MODE_INNER ( mode ) , first ) ; vec_dup = gen_rtx_VEC_DUPLICATE ( mode , broadcast_mem ) ; validate_change ( insn , loc , vec_dup , 0 ) ; return ; } } </s>

Replace all one-value const vector that are referenced by SYMBOL_REFs in x with embedded broadcast . i.e.transform vpaddq .LC0 ( % rip ) , % zmm0 , % zmm0 ret .LC0 : .quad 3 .quad 3 .quad 3 .quad 3 .quad 3 .quad 3 .quad 3 .quad 3 to vpaddq .LC0 ( % rip ) { 1to8 } , % zmm0 , % zmm0 ret .LC0 : .quad 3


<s> bool AArch64TargetLowering :: isMaskAndCmp0FoldingBeneficial ( const Instruction & AndI ) const { ConstantInt * Mask = dyn_cast < ConstantInt > ( AndI . getOperand ( 1 ) ) ; if ( ! Mask ) return false ; return Mask -> getUniqueInteger ( ) . isPowerOf2 ( ) ; } </s>

Return if the target supports combining a chain like :


<s> static void arm_output_mi_thunk ( FILE * file , tree thunk , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { if ( TARGET_32BIT ) arm32_output_mi_thunk ( file , thunk , delta , vcall_offset , function ) ; else arm_thumb1_mi_thunk ( file , thunk , delta , vcall_offset , function ) ; } </s>

Output code to add DELTA to the first argument , and then jump to FUNCTION . Used for C++ multiple inheritance .


<s> SDValue SystemZTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ZERO_EXTEND : return combineZERO_EXTEND ( N , DCI ) ; case ISD :: SIGN_EXTEND : return combineSIGN_EXTEND ( N , DCI ) ; case ISD :: SIGN_EXTEND_INREG : return combineSIGN_EXTEND_INREG ( N , DCI ) ; case SystemZISD :: MERGE_HIGH : case SystemZISD :: MERGE_LOW : return combineMERGE ( N , DCI ) ; case ISD :: LOAD : return combineLOAD ( N , DCI ) ; case ISD :: STORE : return combineSTORE ( N , DCI ) ; case ISD :: VECTOR_SHUFFLE : return combineVECTOR_SHUFFLE ( N , DCI ) ; case ISD :: EXTRACT_VECTOR_ELT : return combineEXTRACT_VECTOR_ELT ( N , DCI ) ; case SystemZISD :: JOIN_DWORDS : return combineJOIN_DWORDS ( N , DCI ) ; case ISD :: FP_ROUND : return combineFP_ROUND ( N , DCI ) ; case ISD :: FP_EXTEND : return combineFP_EXTEND ( N , DCI ) ; case ISD :: BSWAP : return combineBSWAP ( N , DCI ) ; case SystemZISD :: BR_CCMASK : return combineBR_CCMASK ( N , DCI ) ; case SystemZISD :: SELECT_CCMASK : return combineSELECT_CCMASK ( N , DCI ) ; case SystemZISD :: GET_CCMASK : return combineGET_CCMASK ( N , DCI ) ; case ISD :: SDIV : case ISD :: UDIV : case ISD :: SREM : case ISD :: UREM : return combineIntDIVREM ( N , DCI ) ; } return SDValue ( ) ; } </s>


<s> const TargetRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void PPCRegisterInfo :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned TargetAlign = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - 1 ; bool DisableRedZone = MF . getFunction ( ) -> hasFnAttr ( Attribute :: NoRedZone ) ; if ( ! DisableRedZone && FrameSize <= 224 && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ( ! ALIGN_STACK || MaxAlign <= TargetAlign ) ) { MFI -> setStackSize ( 0 ) ; return ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = PPCFrameInfo :: getMinCallFrameSize ( Subtarget . isPPC64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; MFI -> setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s> unsigned MipsRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { switch ( RC -> getID ( ) ) { default : return 0 ; case Mips :: GPR32RegClassID : case Mips :: GPR64RegClassID : case Mips :: DSPRRegClassID : { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return 28 - TFI -> hasFP ( MF ) ; } case Mips :: FGR32RegClassID : return 32 ; case Mips :: AFGR64RegClassID : return 16 ; case Mips :: FGR64RegClassID : return 32 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> MachineInstrBuilder R600InstrInfo :: buildIndirectRead ( MachineBasicBlock * MBB , MachineBasicBlock :: iterator I , unsigned ValueReg , unsigned Address , unsigned OffsetReg ) const { unsigned AddrReg = AMDGPU :: R600_AddrRegClass . getRegister ( Address ) ; MachineInstr * MOVA = buildDefaultInstruction ( * MBB , I , AMDGPU :: MOVA_INT_eg , AMDGPU :: AR_X , OffsetReg ) ; setImmOperand ( MOVA , R600Operands :: WRITE , 0 ) ; MachineInstrBuilder Mov = buildDefaultInstruction ( * MBB , I , AMDGPU :: MOV , ValueReg , AddrReg ) . addReg ( AMDGPU :: AR_X , RegState :: Implicit ) ; setImmOperand ( Mov , R600Operands :: SRC0_REL , 1 ) ; return Mov ; } </s>

Build instruction ( s ) for an indirect register read .


<s> static bool is_store_insn ( rtx insn ) { if ( ! insn || ! INSN_P ( insn ) ) return false ; return is_store_insn1 ( PATTERN ( insn ) ) ; } </s>


<s> static int saved_regs_mentioned ( rtx x ) { int i ; const char * fmt ; RTX_CODE code ; code = GET_CODE ( x ) ; switch ( code ) { case REG : i = REGNO ( x ) ; return ! call_used_regs [ i ] ; case SUBREG : i = REGNO ( SUBREG_REG ( x ) ) ; return ! call_used_regs [ i ] ; default : ; } fmt = GET_RTX_FORMAT ( code ) ; for ( i = GET_RTX_LENGTH ( code ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'e' ) { if ( saved_regs_mentioned ( XEXP ( x , i ) ) ) return 1 ; } else if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( x , i ) - 1 ; j >= 0 ; j -- ) if ( saved_regs_mentioned ( XEXP ( x , i ) ) ) return 1 ; } } return 0 ; } </s>

Return nonzero if there are regs mentioned in the insn that are not all in the call_used regs . This is part of the decision whether an insn can be put in the epilogue .


<s> void AVRMCCodeEmitter :: emitInstruction ( uint64_t Val , unsigned Size , const MCSubtargetInfo & STI , raw_ostream & OS ) const { const uint16_t * Words = reinterpret_cast < uint16_t const * > ( & Val ) ; size_t WordCount = Size / 2 ; for ( int64_t i = WordCount - 1 ; i >= 0 ; -- i ) { uint16_t Word = Words [ i ] ; OS << ( uint8_t ) ( ( Word & 0x00ff ) >> 0 ) ; OS << ( uint8_t ) ( ( Word & 0xff00 ) >> 8 ) ; } } </s>

Targets should implement this to emit instructions .


<s> Register AMDGPURegisterBankInfo :: handleD16VData ( MachineIRBuilder & B , MachineRegisterInfo & MRI , Register Reg ) const { if ( ! Subtarget . hasUnpackedD16VMem ( ) ) return Reg ; const LLT S16 = LLT :: scalar ( 16 ) ; LLT StoreVT = MRI . getType ( Reg ) ; if ( ! StoreVT . isVector ( ) || StoreVT . getElementType ( ) != S16 ) return Reg ; auto Unmerge = B . buildUnmerge ( S16 , Reg ) ; SmallVector < Register , 4 > WideRegs ; for ( int I = 0 , E = Unmerge -> getNumOperands ( ) - 1 ; I != E ; ++ I ) WideRegs . push_back ( Unmerge . getReg ( I ) ) ; const LLT S32 = LLT :: scalar ( 32 ) ; int NumElts = StoreVT . getNumElements ( ) ; return B . buildMerge ( LLT :: vector ( NumElts , S32 ) , WideRegs ) . getReg ( 0 ) ; } </s>

Handle register layout difference for f16 images for some subtargets .


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return CSR_NoRegs_RegMask ; if ( ! Is64Bit ) return CSR_32_RegMask ; if ( IsWin64 ) return CSR_Win64_RegMask ; return CSR_64_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool Mips16FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool prepare_extend_operands ( rtx * operands , enum rtx_code code , machine_mode omode ) { if ( ! TARGET_NO_SDATA_SET && small_data_pattern ( operands [ 1 ] , Pmode ) ) { operands [ 1 ] = gen_rtx_fmt_e ( code , omode , arc_rewrite_small_data ( operands [ 1 ] ) ) ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , operands [ 1 ] ) ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , operands [ 1 ] ) ; emit_move_insn ( operands [ 0 ] , operands [ 0 ] ) ; return true ; } return false ; } </s>

Prepare OPERANDS for an extension using CODE to OMODE . Return true iff the move has been emitted .


<s> static void nvptx_emit_forking ( unsigned mask , bool is_call ) { mask &= ( GOMP_DIM_MASK ( GOMP_DIM_WORKER ) | GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) ) ; if ( mask ) { rtx op = GEN_INT ( mask | ( is_call << GOMP_DIM_MAX ) ) ; if ( ! is_call ) emit_insn ( gen_nvptx_fork ( op ) ) ; emit_insn ( gen_nvptx_forked ( op ) ) ; } } </s>


<s> unsigned LanaiRegisterInfo :: getRARegister ( ) const { return Lanai :: RCA ; } </s>

This method should return the register where the return address can be found .


<s> bool HexagonTargetLowering :: isTruncateFree ( EVT VT1 , EVT VT2 ) const { if ( ! VT1 . isSimple ( ) || ! VT2 . isSimple ( ) ) { return false ; } return ( ( VT1 . getSimpleVT ( ) == MVT :: i64 ) && ( VT2 . getSimpleVT ( ) == MVT :: i32 ) ) ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s> void m32r_initialize_trampoline ( rtx tramp ATTRIBUTE_UNUSED , rtx fnaddr ATTRIBUTE_UNUSED , rtx cxt ATTRIBUTE_UNUSED ) { } </s>

Emit RTL insns to initialize the variable parts of a trampoline . FNADDR is an RTX for the address of the function 's pure code . CXT is an RTX for the static chain value for the function .


<s> void arm_emit_call_insn ( rtx pat , rtx addr , bool sibcall ) { rtx insn ; insn = emit_call_insn ( pat ) ; if ( TARGET_VXWORKS_RTP && flag_pic && ! sibcall && SYMBOL_REF_P ( addr ) && ( SYMBOL_REF_DECL ( addr ) ? ! targetm . binds_local_p ( SYMBOL_REF_DECL ( addr ) ) : ! SYMBOL_REF_LOCAL_P ( addr ) ) ) { require_pic_register ( NULL_RTX , false ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , cfun -> machine -> pic_reg ) ; } if ( TARGET_FDPIC ) { rtx fdpic_reg = gen_rtx_REG ( Pmode , FDPIC_REGNUM ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , fdpic_reg ) ; } if ( TARGET_AAPCS_BASED ) { rtx * fusage = & CALL_INSN_FUNCTION_USAGE ( insn ) ; clobber_reg ( fusage , gen_rtx_REG ( word_mode , IP_REGNUM ) ) ; } } </s>

Emit a call instruction with pattern PAT . ADDR is the address of the call target .


<s> static std :: string getGraphName ( const SpillCostAnalysisGraph & G ) { return "scagraph" ; } </s>

Generate a title for the graph in DOT format .


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .