<s>
SDValue
RISCVTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
report_fatal_error
(
"unimplemented operand"
)
;
case
ISD
::
GlobalAddress
:
return
lowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
lowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
lowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
lowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
lowerSELECT
(
Op
,
DAG
)
;
case
ISD
::
BUILD_VECTOR
:
return
lowerBUILD_VECTOR
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_VECTOR_ELT
:
return
lowerEXTRACT_VECTOR_ELT
(
Op
,
DAG
)
;
case
ISD
::
INSERT_VECTOR_ELT
:
return
lowerINSERT_VECTOR_ELT
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
lowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
lowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
lowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
SHL_PARTS
:
return
lowerShiftLeftParts
(
Op
,
DAG
)
;
case
ISD
::
SRA_PARTS
:
return
lowerShiftRightParts
(
Op
,
DAG
,
true
)
;
case
ISD
::
SRL_PARTS
:
return
lowerShiftRightParts
(
Op
,
DAG
,
false
)
;
case
ISD
::
BITCAST
:
{
assert
(
Subtarget
.
is64Bit
(
)
&&
Subtarget
.
hasStdExtF
(
)
&&
"Unexpected custom legalisation"
)
;
SDLoc
DL
(
Op
)
;
SDValue
Op0
=
Op
.
getOperand
(
0
)
;
if
(
Op
.
getValueType
(
)
!=
MVT
::
f32
||
Op0
.
getValueType
(
)
!=
MVT
::
i32
)
return
SDValue
(
)
;
SDValue
NewOp0
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
DL
,
MVT
::
i64
,
Op0
)
;
SDValue
FPConv
=
DAG
.
getNode
(
RISCVISD
::
FMV_W_X_RV64
,
DL
,
MVT
::
f32
,
NewOp0
)
;
return
FPConv
;
}
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


"Slot for FP register must be last in order to be found!"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s>
SDValue
X86TargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
bool
Is64Bit
=
Subtarget
->
is64Bit
(
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_X86
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
CopyVT
=
VA
.
getValVT
(
)
;
if
(
(
CopyVT
==
MVT
::
f32
||
CopyVT
==
MVT
::
f64
)
&&
(
(
Is64Bit
||
Ins
[
i
]
.
Flags
.
isInReg
(
)
)
&&
!
Subtarget
->
hasXMM
(
)
)
)
{
report_fatal_error
(
"SSE register return with SSE disabled"
)
;
}
SDValue
Val
;
if
(
VA
.
getLocReg
(
)
==
X86
::
ST0
||
VA
.
getLocReg
(
)
==
X86
::
ST1
)
{
if
(
isScalarFPTypeInSSEReg
(
VA
.
getValVT
(
)
)
)
CopyVT
=
MVT
::
f80
;
SDValue
Ops
[
]
=
{
Chain
,
InFlag
}
;
Chain
=
SDValue
(
DAG
.
getMachineNode
(
X86
::
FpPOP_RETVAL
,
dl
,
CopyVT
,
MVT
::
Other
,
MVT
::
Glue
,
Ops
,
2
)
,
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
if
(
CopyVT
!=
VA
.
getValVT
(
)
)
Val
=
DAG
.
getNode
(
ISD
::
FP_ROUND
,
dl
,
VA
.
getValVT
(
)
,
Val
,
DAG
.
getIntPtrConstant
(
1
)
)
;
}
else
{
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
CopyVT
,
InFlag
)
.
getValue
(
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
}
InFlag
=
Chain
.
getValue
(
2
)
;
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> std :: pair < unsigned , const TargetRegisterClass * > MipsTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'd' : case 'y' : case 'r' : return std :: make_pair ( 0U , Mips :: CPURegsRegisterClass ) ; case 'f' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , Mips :: FGR32RegisterClass ) ; if ( VT == MVT :: f64 ) if ( ( ! Subtarget -> isSingleFloat ( ) ) && ( ! Subtarget -> isFP64bit ( ) ) ) return std :: make_pair ( 0U , Mips :: AFGR64RegisterClass ) ; break ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


"execute-only should not generate constant pools"

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


"Can only insert epilog into returning blocks"


"internal error: instruction without _e64 suffix "

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> void TriCoreFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = computeStackSize ( MF ) ; if ( ! StackSize ) { return ; } if ( hasFP ( MF ) ) { MachineFunction :: iterator I ; BuildMI ( MBB , MBBI , dl , TII . get ( TriCore :: MOV_AAsrr ) , TriCore :: A14 ) . addReg ( TriCore :: A10 ) ; for ( I = std :: next ( MF . begin ( ) ) ; I != MF . end ( ) ; ++ I ) I -> addLiveIn ( TriCore :: A14 ) ; } unsigned StackReg = TriCore :: A10 ; unsigned OffsetReg = materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ; if ( OffsetReg ) { BuildMI ( MBB , MBBI , dl , TII . get ( TriCore :: SUB_Arr ) , StackReg ) . addReg ( StackReg ) . addReg ( OffsetReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( TriCore :: SUB_Asc ) ) . addImm ( StackSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool s390_legitimate_address_without_index_p ( rtx op ) { struct s390_address addr ; if ( ! s390_decompose_address ( XEXP ( op , 0 ) , & addr ) ) return false ; if ( addr . indx ) return false ; return true ; } </s>

Return true if CODE is a valid address without index .


Implement target hook libgcc_floating_mode_supported_p .


<s> void expand_prologue ( ) { HOST_WIDE_INT size ; size = get_frame_size ( ) + current_function_outgoing_args_size ; size += ( current_function_outgoing_args_size ? 4 : 0 ) ; if ( current_function_varargs ) { emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( stack_pointer_rtx , 4 ) ) , gen_rtx_REG ( SImode , 0 ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( stack_pointer_rtx , 8 ) ) , gen_rtx_REG ( SImode , 1 ) ) ; } mn10300_gen_multiple_store ( mn10300_get_live_callee_saved_regs ( ) ) ; if ( frame_pointer_needed ) emit_move_insn ( frame_pointer_rtx , stack_pointer_rtx ) ; if ( size ) emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - size ) ) ) ; } </s>


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { GlobalBaseReg = 0 ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; if ( ! PPCSubTarget . isSVR4ABI ( ) ) InsertVRSaveCode ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool match_addli_pcrel ( rtx_insn * insn ) { rtx pattern = PATTERN ( insn ) ; rtx unspec ; if ( GET_CODE ( pattern ) != SET ) return false ; if ( GET_CODE ( SET_SRC ( pattern ) ) != LO_SUM ) return false ; if ( GET_CODE ( XEXP ( SET_SRC ( pattern ) , 1 ) ) != CONST ) return false ; unspec = XEXP ( XEXP ( SET_SRC ( pattern ) , 1 ) , 0 ) ; return ( GET_CODE ( unspec ) == UNSPEC && XINT ( unspec , 1 ) == UNSPEC_PCREL_SYM ) ; } </s>

Returns whether INSN is a pc-relative addli insn .


<s> void PatmosPostRASchedStrategy :: registerRoots ( ) { ReadyQ . initialize ( ) ; } </s>

Notify this strategy that all roots have been released ( including those that depend on EntrySU or ExitSU ) .


<s> void PPCTargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( ! Subtarget . isTargetLinux ( ) ) return TargetLowering :: insertSSPDeclarations ( M ) ; } </s>

Inserts necessary declarations for SSP ( stack protection ) purpose .


<s> Function * AArch64TargetLowering :: getSSPStackGuardCheck ( const Module & M ) const { if ( Subtarget -> getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) ) return M . getFunction ( "__security_check_cookie" ) ; return TargetLowering :: getSSPStackGuardCheck ( M ) ; } </s>

If the target has a standard stack protection check function that performs validation and error handling , returns the function .


<s> X86ProcFamilyEnum getProcFamily ( ) const { return X86ProcFamily ; } </s>


<s> static enum arm_cond_code get_arm_condition_code ( rtx comparison ) { enum arm_cond_code code = maybe_get_arm_condition_code ( comparison ) ; gcc_assert ( code != ARM_NV ) ; return code ; } </s>

Returns the index of the ARM condition code string in ` arm_condition_codes ' . COMPARISON should be an rtx like ` ( eq ( ... ) ( ... ) ) ' .


<s> static bool vax_lra_p ( void ) { return TARGET_LRA ; } </s>

Return true if we use LRA instead of reload pass .


<s> static tree aarch64_simd_builtin_type ( enum machine_mode mode , bool unsigned_p , bool poly_p ) { if ( poly_p ) return aarch64_lookup_simd_builtin_type ( mode , qualifier_poly ) ; else if ( unsigned_p ) return aarch64_lookup_simd_builtin_type ( mode , qualifier_unsigned ) ; else return aarch64_lookup_simd_builtin_type ( mode , qualifier_none ) ; } </s>

Return a type for an operand with specified mode and qualifiers .


<s> static rtx mips_frame_set ( rtx mem , rtx reg ) { rtx set ; if ( REGNO ( reg ) == GP_REG_FIRST + 31 && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31 ) reg = gen_rtx_REG ( GET_MODE ( reg ) , DWARF_FRAME_RETURN_COLUMN ) ; set = gen_rtx_SET ( VOIDmode , mem , reg ) ; RTX_FRAME_RELATED_P ( set ) = 1 ; return set ; } </s>

Return a frame-related rtx that stores register REGNO at ( SP + OFFSET ) . The expression should only be used to store single registers .


<s> static rtx ia64_unpack_sign ( rtx vec , bool unsignedp ) { machine_mode mode = GET_MODE ( vec ) ; rtx zero = CONST0_RTX ( mode ) ; if ( unsignedp ) return zero ; else { rtx sign = gen_reg_rtx ( mode ) ; bool neg ; neg = ia64_expand_vecint_compare ( LT , mode , sign , vec , zero ) ; gcc_assert ( ! neg ) ; return sign ; } } </s>

Return a vector of the sign-extension of VEC .


<s> static void aarch64_update_cpp_builtins ( cpp_reader * pfile ) { aarch64_def_or_undef ( flag_unsafe_math_optimizations , "__ARM_FP_FAST" , pfile ) ; builtin_define_with_int_value ( "__ARM_ARCH" , aarch64_architecture_version ) ; builtin_define_with_int_value ( "__ARM_SIZEOF_MINIMAL_ENUM" , flag_short_enums ? 1 : 4 ) ; aarch64_def_or_undef ( TARGET_BIG_END , "__AARCH64EB__" , pfile ) ; aarch64_def_or_undef ( TARGET_BIG_END , "__ARM_BIG_ENDIAN" , pfile ) ; aarch64_def_or_undef ( ! TARGET_BIG_END , "__AARCH64EL__" , pfile ) ; aarch64_def_or_undef ( TARGET_FLOAT , "__ARM_FEATURE_FMA" , pfile ) ; if ( TARGET_FLOAT || TARGET_SIMD ) { builtin_define_with_int_value ( "__ARM_FP" , 0x0E ) ; builtin_define ( "__ARM_FP16_FORMAT_IEEE" ) ; builtin_define ( "__ARM_FP16_ARGS" ) ; } else cpp_undef ( pfile , "__ARM_FP" ) ; aarch64_def_or_undef ( TARGET_FP_F16INST , "__ARM_FEATURE_FP16_SCALAR_ARITHMETIC" , pfile ) ; aarch64_def_or_undef ( TARGET_SIMD_F16INST , "__ARM_FEATURE_FP16_VECTOR_ARITHMETIC" , pfile ) ; aarch64_def_or_undef ( TARGET_SIMD , "__ARM_FEATURE_NUMERIC_MAXMIN" , pfile ) ; aarch64_def_or_undef ( TARGET_SIMD , "__ARM_NEON" , pfile ) ; aarch64_def_or_undef ( TARGET_CRC32 , "__ARM_FEATURE_CRC32" , pfile ) ; aarch64_def_or_undef ( TARGET_DOTPROD , "__ARM_FEATURE_DOTPROD" , pfile ) ; cpp_undef ( pfile , "__AARCH64_CMODEL_TINY__" ) ; cpp_undef ( pfile , "__AARCH64_CMODEL_SMALL__" ) ; cpp_undef ( pfile , "__AARCH64_CMODEL_LARGE__" ) ; switch ( aarch64_cmodel ) { case AARCH64_CMODEL_TINY : case AARCH64_CMODEL_TINY_PIC : builtin_define ( "__AARCH64_CMODEL_TINY__" ) ; break ; case AARCH64_CMODEL_SMALL : case AARCH64_CMODEL_SMALL_PIC : builtin_define ( "__AARCH64_CMODEL_SMALL__" ) ; break ; case AARCH64_CMODEL_LARGE : builtin_define ( "__AARCH64_CMODEL_LARGE__" ) ; break ; default : break ; } aarch64_def_or_undef ( TARGET_ILP32 , "_ILP32" , pfile ) ; aarch64_def_or_undef ( TARGET_ILP32 , "__ILP32__" , pfile ) ; aarch64_def_or_undef ( TARGET_CRYPTO , "__ARM_FEATURE_CRYPTO" , pfile ) ; aarch64_def_or_undef ( TARGET_SIMD_RDMA , "__ARM_FEATURE_QRDMX" , pfile ) ; aarch64_def_or_undef ( TARGET_SVE , "__ARM_FEATURE_SVE" , pfile ) ; cpp_undef ( pfile , "__ARM_FEATURE_SVE_BITS" ) ; if ( TARGET_SVE ) { int bits ; if ( ! BITS_PER_SVE_VECTOR . is_constant ( & bits ) ) bits = 0 ; builtin_define_with_int_value ( "__ARM_FEATURE_SVE_BITS" , bits ) ; } aarch64_def_or_undef ( TARGET_AES , "__ARM_FEATURE_AES" , pfile ) ; aarch64_def_or_undef ( TARGET_SHA2 , "__ARM_FEATURE_SHA2" , pfile ) ; aarch64_def_or_undef ( TARGET_SHA3 , "__ARM_FEATURE_SHA3" , pfile ) ; aarch64_def_or_undef ( TARGET_SHA3 , "__ARM_FEATURE_SHA512" , pfile ) ; aarch64_def_or_undef ( TARGET_SM4 , "__ARM_FEATURE_SM3" , pfile ) ; aarch64_def_or_undef ( TARGET_SM4 , "__ARM_FEATURE_SM4" , pfile ) ; aarch64_def_or_undef ( TARGET_F16FML , "__ARM_FEATURE_FP16_FML" , pfile ) ; cpp_undef ( pfile , "__FLT_EVAL_METHOD__" ) ; builtin_define_with_int_value ( "__FLT_EVAL_METHOD__" , c_flt_eval_method ( true ) ) ; cpp_undef ( pfile , "__FLT_EVAL_METHOD_C99__" ) ; builtin_define_with_int_value ( "__FLT_EVAL_METHOD_C99__" , c_flt_eval_method ( false ) ) ; } </s>

Undefine/redefine macros that depend on the current backend state and may need to change when a target pragma modifies the backend state .


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & FS , bool isT ) : ARMArchVersion ( V4 ) , ARMFPUType ( None ) , UseNEONForSinglePrecisionFP ( UseNEONFP ) , IsThumb ( isT ) , ThumbMode ( Thumb1 ) , PostRAScheduler ( false ) , IsR9Reserved ( ReserveR9 ) , UseMovt ( UseMOVT ) , stackAlignment ( 4 ) , CPUString ( "generic" ) , TargetType ( isELF ) , TargetABI ( ARM_ABI_APCS ) { if ( FloatABIType == FloatABI :: Default ) FloatABIType = FloatABI :: Soft ; CPUString = ParseSubtargetFeatures ( FS , CPUString ) ; if ( CPUString == "generic" && ( FS . empty ( ) || FS == "generic" ) ) ARMArchVersion = V4T ; unsigned Len = TT . length ( ) ; unsigned Idx = 0 ; if ( Len >= 5 && TT . substr ( 0 , 4 ) == "armv" ) Idx = 4 ; else if ( Len >= 6 && TT . substr ( 0 , 5 ) == "thumb" ) { IsThumb = true ; if ( Len >= 7 && TT [ 5 ] == 'v' ) Idx = 6 ; } if ( Idx ) { unsigned SubVer = TT [ Idx ] ; if ( SubVer >= '7' && SubVer <= '9' ) { ARMArchVersion = V7A ; } else if ( SubVer == '6' ) { ARMArchVersion = V6 ; if ( Len >= Idx + 3 && TT [ Idx + 1 ] == 't' && TT [ Idx + 2 ] == '2' ) ARMArchVersion = V6T2 ; } else if ( SubVer == '5' ) { ARMArchVersion = V5T ; if ( Len >= Idx + 3 && TT [ Idx + 1 ] == 't' && TT [ Idx + 2 ] == 'e' ) ARMArchVersion = V5TE ; } else if ( SubVer == '4' ) { if ( Len >= Idx + 2 && TT [ Idx + 1 ] == 't' ) ARMArchVersion = V4T ; else ARMArchVersion = V4 ; } } if ( ARMArchVersion >= V6T2 ) ThumbMode = Thumb2 ; else if ( ThumbMode >= Thumb2 ) ARMArchVersion = V6T2 ; if ( Len >= 10 ) { if ( TT . find ( "-darwin" ) != std :: string :: npos ) TargetType = isDarwin ; } if ( TT . find ( "eabi" ) != std :: string :: npos ) TargetABI = ARM_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = 8 ; if ( isTargetDarwin ( ) ) IsR9Reserved = ReserveR9 | ( ARMArchVersion < V6 ) ; if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; if ( CPUString == "cortex-a8" ) { if ( UseNEONFP . getPosition ( ) == 0 ) UseNEONForSinglePrecisionFP = true ; } } </s>

This constructor initializes the data members to match that of the specified triple .


<s> static tree builtin_quaternary_function_type ( machine_mode mode_ret , machine_mode mode_arg0 , machine_mode mode_arg1 , machine_mode mode_arg2 , machine_mode mode_arg3 , enum rs6000_builtins builtin ) { tree function_type = NULL ; static tree v2udi_type = builtin_mode_to_type [ V2DImode ] [ 1 ] ; static tree v16uqi_type = builtin_mode_to_type [ V16QImode ] [ 1 ] ; static tree uchar_type = builtin_mode_to_type [ QImode ] [ 1 ] ; static tree xxeval_type = build_function_type_list ( v2udi_type , v2udi_type , v2udi_type , v2udi_type , uchar_type , NULL_TREE ) ; static tree xxpermx_type = build_function_type_list ( v2udi_type , v2udi_type , v2udi_type , v16uqi_type , uchar_type , NULL_TREE ) ; switch ( builtin ) { case P10V_BUILTIN_XXEVAL : gcc_assert ( ( mode_ret == V2DImode ) && ( mode_arg0 == V2DImode ) && ( mode_arg1 == V2DImode ) && ( mode_arg2 == V2DImode ) && ( mode_arg3 == QImode ) ) ; function_type = xxeval_type ; break ; case P10V_BUILTIN_VXXPERMX : gcc_assert ( ( mode_ret == V2DImode ) && ( mode_arg0 == V2DImode ) && ( mode_arg1 == V2DImode ) && ( mode_arg2 == V16QImode ) && ( mode_arg3 == QImode ) ) ; function_type = xxpermx_type ; break ; default : gcc_unreachable ( ) ; } return function_type ; } </s>

Map types for builtin functions with an explicit return type and exactly 4 arguments . Functions with fewer than 3 arguments use builtin_function_type . The number of quaternary built-in functions is very small . Handle each case specially .


<s> static bool expand_vec_perm_v4hi_5 ( struct expand_vec_perm_d * d ) { unsigned char perm2 [ 4 ] ; rtx rmask [ 4 ] ; unsigned i ; rtx t0 , t1 , mask , x ; bool ok ; if ( d -> vmode != V4HImode || d -> one_operand_p ) return false ; if ( d -> testing_p ) return true ; for ( i = 0 ; i < 4 ; ++ i ) { perm2 [ i ] = d -> perm [ i ] & 3 ; rmask [ i ] = ( d -> perm [ i ] & 4 ? const0_rtx : constm1_rtx ) ; } mask = gen_rtx_CONST_VECTOR ( V4HImode , gen_rtvec_v ( 4 , rmask ) ) ; mask = force_reg ( V4HImode , mask ) ; t0 = gen_reg_rtx ( V4HImode ) ; t1 = gen_reg_rtx ( V4HImode ) ; ok = expand_vselect ( t0 , d -> op0 , perm2 , 4 ) ; gcc_assert ( ok ) ; ok = expand_vselect ( t1 , d -> op1 , perm2 , 4 ) ; gcc_assert ( ok ) ; x = gen_rtx_AND ( V4HImode , mask , t0 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , t0 , x ) ) ; x = gen_rtx_NOT ( V4HImode , mask ) ; x = gen_rtx_AND ( V4HImode , x , t1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , t1 , x ) ) ; x = gen_rtx_IOR ( V4HImode , t0 , t1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , d -> target , x ) ) ; return true ; } </s>

A subroutine of ia64_expand_vec_perm_const_1 . Emit a full V4HImode constant permutation via two mux2 and a merge .


<s> bool XNCMAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { return true ; } printSrcMemOperand ( MI , OpNo , O ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s>
StringRef
getPassName
(
)
const
override
{
return
"SI Load / Store Optimizer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> const char * PPCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case PPCISD :: FSEL : return "PPCISD::FSEL" ; case PPCISD :: FCFID : return "PPCISD::FCFID" ; case PPCISD :: FCTIDZ : return "PPCISD::FCTIDZ" ; case PPCISD :: FCTIWZ : return "PPCISD::FCTIWZ" ; case PPCISD :: STFIWX : return "PPCISD::STFIWX" ; case PPCISD :: VMADDFP : return "PPCISD::VMADDFP" ; case PPCISD :: VNMSUBFP : return "PPCISD::VNMSUBFP" ; case PPCISD :: VPERM : return "PPCISD::VPERM" ; case PPCISD :: Hi : return "PPCISD::Hi" ; case PPCISD :: Lo : return "PPCISD::Lo" ; case PPCISD :: TOC_ENTRY : return "PPCISD::TOC_ENTRY" ; case PPCISD :: TOC_RESTORE : return "PPCISD::TOC_RESTORE" ; case PPCISD :: LOAD : return "PPCISD::LOAD" ; case PPCISD :: LOAD_TOC : return "PPCISD::LOAD_TOC" ; case PPCISD :: DYNALLOC : return "PPCISD::DYNALLOC" ; case PPCISD :: GlobalBaseReg : return "PPCISD::GlobalBaseReg" ; case PPCISD :: SRL : return "PPCISD::SRL" ; case PPCISD :: SRA : return "PPCISD::SRA" ; case PPCISD :: SHL : return "PPCISD::SHL" ; case PPCISD :: EXTSW_32 : return "PPCISD::EXTSW_32" ; case PPCISD :: STD_32 : return "PPCISD::STD_32" ; case PPCISD :: CALL_SVR4 : return "PPCISD::CALL_SVR4" ; case PPCISD :: CALL_NOP_SVR4 : return "PPCISD::CALL_NOP_SVR4" ; case PPCISD :: CALL_Darwin : return "PPCISD::CALL_Darwin" ; case PPCISD :: NOP : return "PPCISD::NOP" ; case PPCISD :: MTCTR : return "PPCISD::MTCTR" ; case PPCISD :: BCTRL_Darwin : return "PPCISD::BCTRL_Darwin" ; case PPCISD :: BCTRL_SVR4 : return "PPCISD::BCTRL_SVR4" ; case PPCISD :: RET_FLAG : return "PPCISD::RET_FLAG" ; case PPCISD :: MFCR : return "PPCISD::MFCR" ; case PPCISD :: VCMP : return "PPCISD::VCMP" ; case PPCISD :: VCMPo : return "PPCISD::VCMPo" ; case PPCISD :: LBRX : return "PPCISD::LBRX" ; case PPCISD :: STBRX : return "PPCISD::STBRX" ; case PPCISD :: LARX : return "PPCISD::LARX" ; case PPCISD :: STCX : return "PPCISD::STCX" ; case PPCISD :: COND_BRANCH : return "PPCISD::COND_BRANCH" ; case PPCISD :: MFFS : return "PPCISD::MFFS" ; case PPCISD :: MTFSB0 : return "PPCISD::MTFSB0" ; case PPCISD :: MTFSB1 : return "PPCISD::MTFSB1" ; case PPCISD :: FADDRTZ : return "PPCISD::FADDRTZ" ; case PPCISD :: MTFSF : return "PPCISD::MTFSF" ; case PPCISD :: TC_RETURN : return "PPCISD::TC_RETURN" ; case PPCISD :: CR6SET : return "PPCISD::CR6SET" ; case PPCISD :: CR6UNSET : return "PPCISD::CR6UNSET" ; case PPCISD :: ADDIS_TOC_HA : return "PPCISD::ADDIS_TOC_HA" ; case PPCISD :: LD_TOC_L : return "PPCISD::LD_TOC_L" ; case PPCISD :: ADDI_TOC_L : return "PPCISD::ADDI_TOC_L" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static bool s390_z10_optimize_cmp ( rtx_insn * insn ) { rtx_insn * prev_insn , * next_insn ; bool insn_added_p = false ; rtx cond , * op0 , * op1 ; if ( GET_CODE ( PATTERN ( insn ) ) == PARALLEL ) { rtx pattern = single_set ( insn ) ; if ( ! pattern || SET_DEST ( pattern ) != pc_rtx || GET_CODE ( SET_SRC ( pattern ) ) != IF_THEN_ELSE ) return false ; cond = XEXP ( SET_SRC ( pattern ) , 0 ) ; op0 = & XEXP ( cond , 0 ) ; op1 = & XEXP ( cond , 1 ) ; } else if ( GET_CODE ( PATTERN ( insn ) ) == SET ) { rtx src , dest ; src = SET_SRC ( PATTERN ( insn ) ) ; dest = SET_DEST ( PATTERN ( insn ) ) ; if ( ! REG_P ( dest ) || ! CC_REGNO_P ( REGNO ( dest ) ) || GET_CODE ( src ) != COMPARE ) return false ; cond = NULL_RTX ; op0 = & XEXP ( src , 0 ) ; op1 = & XEXP ( src , 1 ) ; } else return false ; if ( ! REG_P ( * op0 ) || ! REG_P ( * op1 ) ) return false ; if ( GET_MODE_CLASS ( GET_MODE ( * op0 ) ) != MODE_INT ) return false ; prev_insn = prev_active_insn ( insn ) ; if ( prev_insn != NULL_RTX && INSN_P ( prev_insn ) && reg_referenced_p ( * op1 , PATTERN ( prev_insn ) ) ) s390_swap_cmp ( cond , op0 , op1 , insn ) ; next_insn = next_active_insn ( insn ) ; if ( next_insn != NULL_RTX && INSN_P ( next_insn ) && s390_non_addr_reg_read_p ( * op1 , next_insn ) ) { if ( prev_insn != NULL_RTX && INSN_P ( prev_insn ) && s390_non_addr_reg_read_p ( * op0 , prev_insn ) ) { if ( REGNO ( * op1 ) == 0 ) emit_insn_after ( gen_nop_lr1 ( ) , insn ) ; else emit_insn_after ( gen_nop_lr0 ( ) , insn ) ; insn_added_p = true ; } else s390_swap_cmp ( cond , op0 , op1 , insn ) ; } return insn_added_p ; } </s>

On z10 , instructions of the compare-and-branch family have the property to access the register occurring as second operand with its bits complemented . If such a compare is grouped with a second instruction that accesses the same register non-complemented , and if that register 's value is delivered via a bypass , then the pipeline recycles , thereby causing significant performance decline . This function locates such situations and exchanges the two operands of the compare . The function return true whenever it added an insn .


<s> static rtx F ( rtx x ) { RTX_FRAME_RELATED_P ( x ) = 1 ; return x ; } </s>

We use this to wrap all emitted insns in the prologue , so they get the `` frame-related '' ( /f ) flag set .


<s> static inline rtx force_mode ( machine_mode mode , rtx orig ) { if ( mode == GET_MODE ( orig ) ) return orig ; gcc_assert ( REGNO ( orig ) < FIRST_PSEUDO_REGISTER ) ; return gen_rtx_REG ( mode , REGNO ( orig ) ) ; } </s>

Ensure mode of ORIG , a REG rtx , is MODE . Returns either ORIG or a new rtx with the correct mode .


<s> bool SITargetLowering :: shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const { const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; return TII -> isInlineConstant ( Imm ) ; } </s>

Returns true if it is beneficial to convert a load of a constant to just the constant itself .


<s> ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const override { const AMDGPUSubtarget & ST = * getAMDGPUTargetMachine ( ) . getSubtargetImpl ( ) ; if ( ST . getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) return createR600MachineScheduler ( C ) ; return nullptr ; } </s>

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level .


<s> const uint16_t * Dcpu16RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { 0 } ; return CalleeSavedRegs ; } </s>


<s> const uint32_t * LEGRegisterInfo :: getCallPreservedMask ( CallingConv :: ID ) const { return CC_Save_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


"SystemZ DAG->DAG Pattern Instruction Selection"


<s> void ARMDAGToDAGISel :: PreprocessISelDAG ( ) { if ( ! Subtarget -> hasV6T2Ops ( ) ) return ; bool isThumb2 = Subtarget -> isThumb ( ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( N -> getOpcode ( ) != ISD :: ADD ) continue ; SDValue N0 = N -> getOperand ( 0 ) ; SDValue N1 = N -> getOperand ( 1 ) ; unsigned And_imm = 0 ; if ( ! isOpcWithIntImmediate ( N1 . getNode ( ) , ISD :: AND , And_imm ) ) { if ( isOpcWithIntImmediate ( N0 . getNode ( ) , ISD :: AND , And_imm ) ) std :: swap ( N0 , N1 ) ; } if ( ! And_imm ) continue ; unsigned TZ = CountTrailingZeros_32 ( And_imm ) ; if ( TZ != 1 && TZ != 2 ) continue ; And_imm >>= TZ ; if ( And_imm & ( And_imm + 1 ) ) continue ; SDValue Srl = N1 . getOperand ( 0 ) ; unsigned Srl_imm = 0 ; if ( ! isOpcWithIntImmediate ( Srl . getNode ( ) , ISD :: SRL , Srl_imm ) || ( Srl_imm <= 2 ) ) continue ; SDValue CPTmp0 ; SDValue CPTmp1 ; SDValue CPTmp2 ; if ( isThumb2 ) { if ( SelectT2ShifterOperandReg ( N0 , CPTmp0 , CPTmp1 ) ) continue ; } else { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) || SelectRegShifterOperand ( N0 , CPTmp0 , CPTmp1 , CPTmp2 ) ) continue ; } Srl = CurDAG -> getNode ( ISD :: SRL , Srl . getDebugLoc ( ) , MVT :: i32 , Srl . getOperand ( 0 ) , CurDAG -> getConstant ( Srl_imm + TZ , MVT :: i32 ) ) ; N1 = CurDAG -> getNode ( ISD :: AND , N1 . getDebugLoc ( ) , MVT :: i32 , Srl , CurDAG -> getConstant ( And_imm , MVT :: i32 ) ) ; N1 = CurDAG -> getNode ( ISD :: SHL , N1 . getDebugLoc ( ) , MVT :: i32 , N1 , CurDAG -> getConstant ( TZ , MVT :: i32 ) ) ; CurDAG -> UpdateNodeOperands ( N , N0 , N1 ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> MCSection * MipsTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C ) const { if ( IsConstantInSmallSection ( DL , C , * TM ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: getSectionForConstant ( DL , Kind , C ) ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return createARMMachObjectWriter ( OS , false , MachO :: CPU_TYPE_ARM , Subtype ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> XCoreSubtarget :: XCoreSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : XCoreGenSubtargetInfo ( TT , CPU , FS ) { } </s>


<s> const char * MipsTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case MipsISD :: JmpLink : return "MipsISD::JmpLink" ; case MipsISD :: TailCall : return "MipsISD::TailCall" ; case MipsISD :: Hi : return "MipsISD::Hi" ; case MipsISD :: Lo : return "MipsISD::Lo" ; case MipsISD :: GPRel : return "MipsISD::GPRel" ; case MipsISD :: ThreadPointer : return "MipsISD::ThreadPointer" ; case MipsISD :: Ret : return "MipsISD::Ret" ; case MipsISD :: EH_RETURN : return "MipsISD::EH_RETURN" ; case MipsISD :: FPBrcond : return "MipsISD::FPBrcond" ; case MipsISD :: FPCmp : return "MipsISD::FPCmp" ; case MipsISD :: CMovFP_T : return "MipsISD::CMovFP_T" ; case MipsISD :: CMovFP_F : return "MipsISD::CMovFP_F" ; case MipsISD :: FPRound : return "MipsISD::FPRound" ; case MipsISD :: MAdd : return "MipsISD::MAdd" ; case MipsISD :: MAddu : return "MipsISD::MAddu" ; case MipsISD :: MSub : return "MipsISD::MSub" ; case MipsISD :: MSubu : return "MipsISD::MSubu" ; case MipsISD :: DivRem : return "MipsISD::DivRem" ; case MipsISD :: DivRemU : return "MipsISD::DivRemU" ; case MipsISD :: BuildPairF64 : return "MipsISD::BuildPairF64" ; case MipsISD :: ExtractElementF64 : return "MipsISD::ExtractElementF64" ; case MipsISD :: Wrapper : return "MipsISD::Wrapper" ; case MipsISD :: Sync : return "MipsISD::Sync" ; case MipsISD :: Ext : return "MipsISD::Ext" ; case MipsISD :: Ins : return "MipsISD::Ins" ; case MipsISD :: LWL : return "MipsISD::LWL" ; case MipsISD :: LWR : return "MipsISD::LWR" ; case MipsISD :: SWL : return "MipsISD::SWL" ; case MipsISD :: SWR : return "MipsISD::SWR" ; case MipsISD :: LDL : return "MipsISD::LDL" ; case MipsISD :: LDR : return "MipsISD::LDR" ; case MipsISD :: SDL : return "MipsISD::SDL" ; case MipsISD :: SDR : return "MipsISD::SDR" ; case MipsISD :: EXTP : return "MipsISD::EXTP" ; case MipsISD :: EXTPDP : return "MipsISD::EXTPDP" ; case MipsISD :: EXTR_S_H : return "MipsISD::EXTR_S_H" ; case MipsISD :: EXTR_W : return "MipsISD::EXTR_W" ; case MipsISD :: EXTR_R_W : return "MipsISD::EXTR_R_W" ; case MipsISD :: EXTR_RS_W : return "MipsISD::EXTR_RS_W" ; case MipsISD :: SHILO : return "MipsISD::SHILO" ; case MipsISD :: MTHLIP : return "MipsISD::MTHLIP" ; case MipsISD :: MULT : return "MipsISD::MULT" ; case MipsISD :: MULTU : return "MipsISD::MULTU" ; case MipsISD :: MADD_DSP : return "MipsISD::MADD_DSPDSP" ; case MipsISD :: MADDU_DSP : return "MipsISD::MADDU_DSP" ; case MipsISD :: MSUB_DSP : return "MipsISD::MSUB_DSP" ; case MipsISD :: MSUBU_DSP : return "MipsISD::MSUBU_DSP" ; default : return NULL ; } } </s>

Mips Mips MipsISD::JmpLink "MipsISD::JmpLink" MipsISD::TailCall "MipsISD::TailCall" MipsISD::Hi "MipsISD::Hi" MipsISD::Lo "MipsISD::Lo" MipsISD::GPRel "MipsISD::GPRel" MipsISD::ThreadPointer "MipsISD::ThreadPointer" MipsISD::Ret "MipsISD::Ret" MipsISD::EH_RETURN "MipsISD::EH_RETURN" MipsISD::FPBrcond "MipsISD::FPBrcond" MipsISD::FPCmp "MipsISD::FPCmp" MipsISD::CMovFP_T "MipsISD::CMovFP_T" MipsISD::CMovFP_F "MipsISD::CMovFP_F" MipsISD::FPRound "MipsISD::FPRound" MipsISD::MAdd "MipsISD::MAdd" MipsISD::MAddu "MipsISD::MAddu" MipsISD::MSub "MipsISD::MSub" MipsISD::MSubu "MipsISD::MSubu" MipsISD::DivRem "MipsISD::DivRem" MipsISD::DivRemU "MipsISD::DivRemU" MipsISD::BuildPairF64 "MipsISD::BuildPairF64" MipsISD::ExtractElementF64 "MipsISD::ExtractElementF64" MipsISD::Wrapper "MipsISD::Wrapper" MipsISD::Sync "MipsISD::Sync" MipsISD::Ext "MipsISD::Ext" MipsISD::Ins "MipsISD::Ins" MipsISD::LWL "MipsISD::LWL" MipsISD::LWR "MipsISD::LWR" MipsISD::SWL "MipsISD::SWL" MipsISD::SWR "MipsISD::SWR" MipsISD::LDL "MipsISD::LDL" MipsISD::LDR "MipsISD::LDR" MipsISD::SDL "MipsISD::SDL" MipsISD::SDR "MipsISD::SDR" MipsISD::EXTP "MipsISD::EXTP" MipsISD::EXTPDP "MipsISD::EXTPDP" MipsISD::EXTR_S_H "MipsISD::EXTR_S_H" MipsISD::EXTR_W "MipsISD::EXTR_W" MipsISD::EXTR_R_W "MipsISD::EXTR_R_W" MipsISD::EXTR_RS_W "MipsISD::EXTR_RS_W" MipsISD::SHILO "MipsISD::SHILO" MipsISD::MTHLIP "MipsISD::MTHLIP" MipsISD::MULT "MipsISD::MULT" MipsISD::MULTU "MipsISD::MULTU" MipsISD::MADD_DSP "MipsISD::MADD_DSPDSP" MipsISD::MADDU_DSP "MipsISD::MADDU_DSP" MipsISD::MSUB_DSP "MipsISD::MSUB_DSP" MipsISD::MSUBU_DSP "MipsISD::MSUBU_DSP"


<s> void print ( const TargetRegisterInfo * TRI = nullptr ) const { dbgs ( ) << PrintReg ( Reg , TRI , SubReg ) ; } </s>

print - Print a debug representation of the operand to the given stream .


<s> static void rs6000_live_on_entry ( bitmap regs ) { if ( flag_split_stack ) bitmap_set_bit ( regs , 12 ) ; } </s>

We may have to tell the dataflow pass that the split stack prologue is initializing a register .


<s>
const
CallLowering
*
AArch64Subtarget
::
getCallLowering
(
)
const
{
assert
(
GISel
&&
"Access to GlobalISel APIs not set"
)
;
return
GISel
->
getCallLowering
(
)
;
}
</s>


<s> const MCExpr * SparcELFTargetObjectFile :: getTTypeGlobalReference ( const GlobalValue * GV , unsigned Encoding , Mangler & Mang , const TargetMachine & TM , MachineModuleInfo * MMI , MCStreamer & Streamer ) const { if ( Encoding & dwarf :: DW_EH_PE_pcrel ) { MachineModuleInfoELF & ELFMMI = MMI -> getObjFileInfo < MachineModuleInfoELF > ( ) ; MCSymbol * SSym = getSymbolWithGlobalValueBase ( GV , ".DW.stub" , Mang , TM ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = ELFMMI . getGVStubEntry ( SSym ) ; if ( ! StubSym . getPointer ( ) ) { MCSymbol * Sym = TM . getSymbol ( GV , Mang ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Sym , ! GV -> hasLocalLinkage ( ) ) ; } MCContext & Ctx = getContext ( ) ; return SparcMCExpr :: create ( SparcMCExpr :: VK_Sparc_R_DISP32 , MCSymbolRefExpr :: create ( SSym , Ctx ) , Ctx ) ; } return TargetLoweringObjectFileELF :: getTTypeGlobalReference ( GV , Encoding , Mang , TM , MMI , Streamer ) ; } </s>

The mach-o version of this method defaults to returning a stub reference .


<s> static bool classof ( const RISCVMCExpr * ) { return true ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s>
void
RISCVInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MBBI
,
const
DebugLoc
&
DL
,
MCRegister
DstReg
,
MCRegister
SrcReg
,
bool
KillSrc
)
const
{
if
(
RISCV
::
GPRRegClass
.
contains
(
DstReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
RISCV
::
ADDI
)
,
DstReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
0
)
;
return
;
}
unsigned
Opc
;
if
(
RISCV
::
FPR32RegClass
.
contains
(
DstReg
,
SrcReg
)
)
Opc
=
RISCV
::
FSGNJ_S
;
else
if
(
RISCV
::
FPR64RegClass
.
contains
(
DstReg
,
SrcReg
)
)
Opc
=
RISCV
::
FSGNJ_D
;
else
if
(
RISCV
::
VGRRegClass
.
contains
(
DstReg
,
SrcReg
)
||
RISCV
::
VPRRegClass
.
contains
(
DstReg
,
SrcReg
)
||
RISCV
::
VQRRegClass
.
contains
(
DstReg
,
SrcReg
)
||
RISCV
::
VORRegClass
.
contains
(
DstReg
,
SrcReg
)
||
(
RISCV
::
VMASKRegClass
.
contains
(
DstReg
)
&&
RISCV
::
VGRRegClass
.
contains
(
SrcReg
)
)
)
{
Opc
=
RISCV
::
VMV_V_V
;
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
Opc
)
,
RISCV
::
V0
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
return
;
}
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
Opc
)
,
DstReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


"Instr doesn't have FrameIndex operand!"

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s>
void
neon_const_bounds
(
rtx
operand
,
HOST_WIDE_INT
low
,
HOST_WIDE_INT
high
)
{
bounds_check
(
operand
,
low
,
high
,
"constant out of range"
)
;
}
</s>


<s>
unsigned
getOpSize
(
const
MachineInstr
&
MI
,
unsigned
OpNo
)
const
{
const
MachineOperand
&
MO
=
MI
.
getOperand
(
OpNo
)
;
if
(
MO
.
isReg
(
)
)
{
if
(
unsigned
SubReg
=
MO
.
getSubReg
(
)
)
{
assert
(
RI
.
getRegSizeInBits
(
*
RI
.
getSubClassWithSubReg
(
MI
.
getParent
(
)
->
getParent
(
)
->
getRegInfo
(
)
.
getRegClass
(
MO
.
getReg
(
)
)
,
SubReg
)
)
>=
32
&&
"Sub-dword subregs are not supported"
)
;
return
RI
.
getNumChannelsFromSubReg
(
SubReg
)
*
4
;
}
}
return
RI
.
getRegSizeInBits
(
*
getOpRegClass
(
MI
,
OpNo
)
)
/
8
;
}
</s>

This form should usually be preferred since it handles operands with unknown register classes .


<s>
ArrayRef
<
MCPhysReg
>
MipsABIInfo
::
GetVarArgRegs
(
)
const
{
if
(
IsCheriPureCap
(
)
)
return
makeArrayRef
(
CheriCapArgRegs
)
;
if
(
IsO32
(
)
)
return
makeArrayRef
(
O32IntRegs
)
;
if
(
IsN32
(
)
||
IsN64
(
)
)
return
makeArrayRef
(
Mips64IntRegs
)
;
llvm_unreachable
(
"Unhandled ABI"
)
;
}
</s>

The registers to use for the variable argument list .


<s> static bool bfin_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { enum reg_class rclass = REGNO_REG_CLASS ( regno ) ; if ( mode == CCmode ) return false ; if ( mode == V2HImode ) return D_REGNO_P ( regno ) ; if ( rclass == CCREGS ) return mode == BImode ; if ( mode == PDImode || mode == V2PDImode ) return regno == REG_A0 || regno == REG_A1 ; if ( mode == DImode ) return regno < REG_M3 ; if ( mode == SImode && TEST_HARD_REG_BIT ( reg_class_contents [ PROLOGUE_REGS ] , regno ) ) return true ; return TEST_HARD_REG_BIT ( reg_class_contents [ MOST_REGS ] , regno ) ; } </s>

Implement TARGET_HARD_REGNO_MODE_OK . Do not allow to store a value in REG_CC for any mode . Do not allow to store value in pregs if mode is not SI .


<s> static unsigned getHashValue ( const TOCKey & PairVal ) { return detail :: combineHashValue ( DenseMapInfo < const MCSymbol * > :: getHashValue ( PairVal . first ) , DenseMapInfo < int > :: getHashValue ( PairVal . second ) ) ; } </s>

Using name and line to get hash value . It should already be mostly unique .


<s>
void
AArch64FrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
const
AArch64InstrInfo
*
TII
=
static_cast
<
const
AArch64InstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
DebugLoc
DL
=
I
->
getDebugLoc
(
)
;
unsigned
Opc
=
I
->
getOpcode
(
)
;
bool
IsDestroy
=
Opc
==
TII
->
getCallFrameDestroyOpcode
(
)
;
uint64_t
CalleePopAmount
=
IsDestroy
I
->
getOperand
(
1
)
.
getImm
(
)
:
0
;
const
TargetFrameLowering
*
TFI
=
MF
.
getSubtarget
(
)
.
getFrameLowering
(
)
;
if
(
!
TFI
->
hasReservedCallFrame
(
MF
)
)
{
unsigned
Align
=
getStackAlignment
(
)
;
int64_t
Amount
=
I
->
getOperand
(
0
)
.
getImm
(
)
;
Amount
=
alignTo
(
Amount
,
Align
)
;
if
(
!
IsDestroy
)
Amount
=
Amount
;
if
(
CalleePopAmount
==
0
)
{
assert
(
Amount
>
0xffffff
&&
Amount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
Amount
,
TII
)
;
}
}
else
if
(
CalleePopAmount
!=
0
)
{
assert
(
CalleePopAmount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
CalleePopAmount
,
TII
)
;
}
MBB
.
erase
(
I
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> const MCPhysReg * XCoreRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const MCPhysReg CalleeSavedRegs [ ] = { XCore :: R4 , XCore :: R5 , XCore :: R6 , XCore :: R7 , XCore :: R8 , XCore :: R9 , XCore :: R10 , 0 } ; static const MCPhysReg CalleeSavedRegsFP [ ] = { XCore :: R4 , XCore :: R5 , XCore :: R6 , XCore :: R7 , XCore :: R8 , XCore :: R9 , 0 } ; const XCoreFrameLowering * TFI = getFrameLowering ( * MF ) ; if ( TFI -> hasFP ( * MF ) ) return CalleeSavedRegsFP ; return CalleeSavedRegs ; } </s>


<s> void AArch64PassConfig :: addMachineSSAOptimization ( ) { TargetPassConfig :: addMachineSSAOptimization ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createAArch64MIPeepholeOptPass ( ) ) ; } </s>

Methods with trivial inline returns are convenient points in the common codegen pass pipeline where targets may insert passes .


<s> static bool is_load_insn ( rtx insn ) { if ( ! insn || ! INSN_P ( insn ) ) return false ; if ( GET_CODE ( insn ) == CALL_INSN ) return false ; return is_load_insn1 ( PATTERN ( insn ) ) ; } </s>


<s>
const
char
*
vfp_output_fstmx
(
rtx
*
operands
)
{
char
pattern
[
100
]
;
int
p
;
int
base
;
int
i
;
strcpy
(
pattern
,
"fstmfdx\t%m0!, {%P1"
)
;
p
=
strlen
(
pattern
)
;
gcc_assert
(
GET_CODE
(
operands
[
1
]
)
==
REG
)
;
base
=
(
REGNO
(
operands
[
1
]
)
FIRST_VFP_REGNUM
)
/
2
;
for
(
i
=
1
;
i
<
XVECLEN
(
operands
[
2
]
,
0
)
;
i
++
)
{
p
+=
sprintf
(
&
pattern
[
p
]
,
", d%d"
,
base
+
i
)
;
}
strcpy
(
&
pattern
[
p
]
,
"}"
)
;
output_asm_insn
(
pattern
,
operands
)
;
return
""
;
}
</s>

Output the assembly for a store multiple .


<s> void MSP430RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned BasePtr = ( TFI -> hasFP ( MF ) ? MSP430 :: FP : MSP430 :: SP ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; Offset += 2 ; if ( ! TFI -> hasFP ( MF ) ) Offset += MF . getFrameInfo ( ) -> getStackSize ( ) ; else Offset += 2 ; Offset += MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ; if ( MI . getOpcode ( ) == MSP430 :: ADD16ri ) { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MI . setDesc ( TII . get ( MSP430 :: MOV16rr ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; if ( Offset == 0 ) return ; unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ; if ( Offset < 0 ) BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( MSP430 :: SUB16ri ) , DstReg ) . addReg ( DstReg ) . addImm ( - Offset ) ; else BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( MSP430 :: ADD16ri ) , DstReg ) . addReg ( DstReg ) . addImm ( Offset ) ; return ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool isReg ( ) const override { return Kind == k_Register ; } </s>


<s> void SystemZPassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createSystemZElimComparePass ( getSystemZTargetMachine ( ) ) , false ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createSystemZShortenInstPass ( getSystemZTargetMachine ( ) ) , false ) ; addPass ( createSystemZLongBranchPass ( getSystemZTargetMachine ( ) ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
Register
:
OS
<<
"<register "
<<
getReg
(
)
<<
" mods: "
<<
Reg
.
Mods
<<
'>'
;
break
;
case
Immediate
:
OS
<<
'<'
<<
getImm
(
)
;
if
(
getImmTy
(
)
!=
ImmTyNone
)
{
OS
<<
" type: "
;
printImmTy
(
OS
,
getImmTy
(
)
)
;
}
OS
<<
" mods: "
<<
Imm
.
Mods
<<
'>'
;
break
;
case
Token
:
OS
<<
'\''
<<
getToken
(
)
<<
'\''
;
break
;
case
Expression
:
OS
<<
"<expr "
<<
*
Expr
<<
'>'
;
break
;
}
}
</s>

AMDGPU
"<register "
" mods: "
" type: "
" mods: "
"<expr "


<s> static machine_mode rs6000_secondary_memory_needed_mode ( machine_mode mode ) { if ( lra_in_progress && mode == SDmode ) return DDmode ; return mode ; } </s>

Return the mode to be used for memory when a secondary memory location is needed . For SDmode values we need to use DDmode , in all other cases we can use the same mode .


<s> static bool v850_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { return ( to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true ) ; } </s>

Worker function for TARGET_CAN_ELIMINATE .


<s> const MCExpr * AArch64_MachoTargetObjectFile :: getTTypeGlobalReference ( const GlobalValue * GV , unsigned Encoding , const TargetMachine & TM , MachineModuleInfo * MMI , MCStreamer & Streamer ) const { if ( Encoding & ( DW_EH_PE_indirect | DW_EH_PE_pcrel ) ) { const MCSymbol * Sym = TM . getSymbol ( GV ) ; const MCExpr * Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_GOT , getContext ( ) ) ; MCSymbol * PCSym = getContext ( ) . createTempSymbol ( ) ; Streamer . emitLabel ( PCSym ) ; const MCExpr * PC = MCSymbolRefExpr :: create ( PCSym , getContext ( ) ) ; return MCBinaryExpr :: createSub ( Res , PC , getContext ( ) ) ; } return TargetLoweringObjectFileMachO :: getTTypeGlobalReference ( GV , Encoding , TM , MMI , Streamer ) ; } </s>


<s>
SUnit
*
GCNMaxOccupancySchedStrategy
::
pickNode
(
bool
&
IsTopNode
)
{
if
(
DAG
->
top
(
)
==
DAG
->
bottom
(
)
)
{
assert
(
Top
.
Available
.
empty
(
)
&&
Top
.
Pending
.
empty
(
)
&&
Bot
.
Available
.
empty
(
)
&&
Bot
.
Pending
.
empty
(
)
&&
"ReadyQ garbage"
)
;
return
nullptr
;
}
SUnit
*
SU
;
do
{
if
(
RegionPolicy
.
OnlyTopDown
)
{
SU
=
Top
.
pickOnlyChoice
(
)
;
if
(
!
SU
)
{
CandPolicy
NoPolicy
;
TopCand
.
reset
(
NoPolicy
)
;
pickNodeFromQueue
(
Top
,
NoPolicy
,
DAG
->
getTopRPTracker
(
)
,
TopCand
)
;
assert
(
TopCand
.
Reason
!=
NoCand
&&
"failed to find a candidate"
)
;
SU
=
TopCand
.
SU
;
}
IsTopNode
=
true
;
}
else
if
(
RegionPolicy
.
OnlyBottomUp
)
{
SU
=
Bot
.
pickOnlyChoice
(
)
;
if
(
!
SU
)
{
CandPolicy
NoPolicy
;
BotCand
.
reset
(
NoPolicy
)
;
pickNodeFromQueue
(
Bot
,
NoPolicy
,
DAG
->
getBotRPTracker
(
)
,
BotCand
)
;
assert
(
BotCand
.
Reason
!=
NoCand
&&
"failed to find a candidate"
)
;
SU
=
BotCand
.
SU
;
}
IsTopNode
=
false
;
}
else
{
SU
=
pickNodeBidirectional
(
IsTopNode
)
;
}
}
while
(
SU
->
isScheduled
)
;
if
(
SU
->
isTopReady
(
)
)
Top
.
removeReady
(
SU
)
;
if
(
SU
->
isBottomReady
(
)
)
Bot
.
removeReady
(
SU
)
;
DEBUG
(
dbgs
(
)
<<
"Scheduling SU("
<<
SU
->
NodeNum
<<
") "
<<
*
SU
->
getInstr
(
)
)
;
return
SU
;
}
</s>

Pick the next node to schedule , or return NULL .

AMDGPU
"ReadyQ garbage"
"failed to find a candidate"
"failed to find a candidate"
"Scheduling SU("
") "


<s> void AArch64PassConfig :: addPreRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableDeadRegisterElimination ) addPass ( createAArch64DeadRegisterDefinitions ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAdvSIMDScalar ) { addPass ( createAArch64AdvSIMDScalar ( ) ) ; addPass ( & PeepholeOptimizerID ) ; } } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly


<s> static bool sh_unspec_insn_p ( rtx x ) { subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( i , array , x , ALL ) if ( * i != NULL && ( GET_CODE ( * i ) == UNSPEC || GET_CODE ( * i ) == UNSPEC_VOLATILE ) ) return true ; return false ; } </s>

Return true if the specified insn contains any UNSPECs or UNSPEC_VOLATILEs .


<s> const char * aarch64_gen_far_branch ( rtx * operands , int pos_label , const char * dest , const char * branch_format ) { rtx_code_label * tmp_label = gen_label_rtx ( ) ; char label_buf [ 256 ] ; char buffer [ 128 ] ; ASM_GENERATE_INTERNAL_LABEL ( label_buf , dest , CODE_LABEL_NUMBER ( tmp_label ) ) ; const char * label_ptr = targetm . strip_name_encoding ( label_buf ) ; rtx dest_label = operands [ pos_label ] ; operands [ pos_label ] = tmp_label ; snprintf ( buffer , sizeof ( buffer ) , "%s%s" , branch_format , label_ptr ) ; output_asm_insn ( buffer , operands ) ; snprintf ( buffer , sizeof ( buffer ) , "b\t%%l%d\n%s:" , pos_label , label_ptr ) ; operands [ pos_label ] = dest_label ; output_asm_insn ( buffer , operands ) ; return "" ; } </s>

Generate code to enable conditional branches in functions over 1 MiB .


<s>
SDValue
AArch64TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom lower this!"
)
;
case
ISD
::
FADD
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
ADD_F128
)
;
case
ISD
::
FSUB
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
SUB_F128
)
;
case
ISD
::
FMUL
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
MUL_F128
)
;
case
ISD
::
FDIV
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
DIV_F128
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
,
true
)
;
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
,
false
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
,
true
)
;
case
ISD
::
UINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
,
false
)
;
case
ISD
::
FP_ROUND
:
return
LowerFP_ROUND
(
Op
,
DAG
)
;
case
ISD
::
FP_EXTEND
:
return
LowerFP_EXTEND
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
BRCOND
:
return
LowerBRCOND
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddressELF
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
LowerSELECT
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
case
ISD
::
VACOPY
:
return
LowerVACOPY
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
BUILD_VECTOR
:
return
LowerBUILD_VECTOR
(
Op
,
DAG
,
getSubtarget
(
)
)
;
}
return
SDValue
(
)
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool RISCVInstrInfo :: getMemOperandWithOffsetWidth ( const MachineInstr & LdSt , const MachineOperand * & BaseReg , int64_t & Offset , unsigned & Width , const TargetRegisterInfo * TRI ) const { if ( ! LdSt . mayLoadOrStore ( ) ) return false ; if ( LdSt . getNumExplicitOperands ( ) != 3 ) return false ; if ( ! LdSt . getOperand ( 1 ) . isReg ( ) || ! LdSt . getOperand ( 2 ) . isImm ( ) ) return false ; if ( ! LdSt . hasOneMemOperand ( ) ) return false ; Width = ( * LdSt . memoperands_begin ( ) ) -> getSize ( ) ; BaseReg = & LdSt . getOperand ( 1 ) ; Offset = LdSt . getOperand ( 2 ) . getImm ( ) ; return true ; } </s>

Return true if get the base operand , byte offset of an instruction and the memory width .


<s> bool SIFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MFI . hasCalls ( ) ) { if ( MFI . getStackSize ( ) != 0 ) return true ; if ( MF . getInfo < SIMachineFunctionInfo > ( ) -> isEntryFunction ( ) ) return true ; if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) return true ; } return MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || MF . getSubtarget < GCNSubtarget > ( ) . getRegisterInfo ( ) -> needsStackRealignment ( MF ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override { OW -> WriteZeros ( Count ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> void riscv_init_builtins ( void ) { riscv_init_builtin_types ( ) ; riscv_vector :: init_builtins ( ) ; for ( size_t i = 0 ; i < ARRAY_SIZE ( riscv_builtins ) ; i ++ ) { const struct riscv_builtin_description * d = & riscv_builtins [ i ] ; if ( d -> avail ( ) ) { tree type = riscv_build_function_type ( d -> prototype ) ; riscv_builtin_decls [ i ] = add_builtin_function ( d -> name , type , ( i << RISCV_BUILTIN_SHIFT ) + RISCV_BUILTIN_GENERAL , BUILT_IN_MD , NULL , NULL ) ; riscv_builtin_decl_index [ d -> icode ] = i ; } } } </s>


<s> SDValue MipsTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; unsigned opc = N -> getOpcode ( ) ; switch ( opc ) { default : break ; case ISD :: ADDE : return PerformADDECombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SUBE : return PerformSUBECombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SDIVREM : case ISD :: UDIVREM : return PerformDivRemCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SETCC : return PerformSETCCCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: AND : return PerformANDCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: OR : return PerformORCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips Mips ISD::ADDE ISD::SUBE ISD::SDIVREM ISD::UDIVREM ISD::SETCC ISD::AND ISD::OR


<s>
bool
X86InstrInfo
::
expandPostRAPseudo
(
MachineBasicBlock
::
iterator
MI
)
const
{
bool
HasAVX
=
Subtarget
.
hasAVX
(
)
;
MachineInstrBuilder
MIB
(
*
MI
->
getParent
(
)
->
getParent
(
)
,
MI
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
X86
::
MOV32r0
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
XOR32rr
)
)
;
case
X86
::
SETB_C8r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB8rr
)
)
;
case
X86
::
SETB_C16r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB16rr
)
)
;
case
X86
::
SETB_C32r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB32rr
)
)
;
case
X86
::
SETB_C64r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB64rr
)
)
;
case
X86
::
V_SET0
:
case
X86
::
FsFLD0SS
:
case
X86
::
FsFLD0SD
:
return
Expand2AddrUndef
(
MIB
,
get
(
HasAVX
X86
::
VXORPSrr
:
X86
::
XORPSrr
)
)
;
case
X86
::
AVX_SET0
:
assert
(
HasAVX
&&
"AVX not supported"
)
;
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VXORPSYrr
)
)
;
case
X86
::
AVX512_512_SET0
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VPXORDZrr
)
)
;
case
X86
::
V_SETALLONES
:
return
Expand2AddrUndef
(
MIB
,
get
(
HasAVX
X86
::
VPCMPEQDrr
:
X86
::
PCMPEQDrr
)
)
;
case
X86
::
AVX2_SETALLONES
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VPCMPEQDYrr
)
)
;
case
X86
::
TEST8ri_NOREX
:
MI
->
setDesc
(
get
(
X86
::
TEST8ri
)
)
;
return
true
;
case
X86
::
KSET0B
:
case
X86
::
KSET0W
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
KXORWrr
)
)
;
case
X86
::
KSET1B
:
case
X86
::
KSET1W
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
KXNORWrr
)
)
;
}
return
false
;
}
</s>

This function is called for all pseudo instructions that remain after register allocation .


<s> SDValue WebAssemblySelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Dst , SDValue Val , SDValue Size , unsigned Align , bool IsVolatile , MachinePointerInfo DstPtrInfo ) const { if ( ! DAG . getMachineFunction ( ) . getSubtarget < WebAssemblySubtarget > ( ) . hasBulkMemory ( ) ) return SDValue ( ) ; SDValue MemIdx = DAG . getConstant ( 0 , DL , MVT :: i32 ) ; return DAG . getNode ( WebAssemblyISD :: MEMORY_FILL , DL , MVT :: Other , Chain , MemIdx , Dst , DAG . getAnyExtOrTrunc ( Val , DL , MVT :: i32 ) , DAG . getZExtOrTrunc ( Size , DL , MVT :: i32 ) ) ; } </s>

Emit target-specific code that performs a memset .


<s> static unsigned aarch64_add_stmt_cost ( void * data , int count , enum vect_cost_for_stmt kind , struct _stmt_vec_info * stmt_info , int misalign , enum vect_cost_model_location where ) { unsigned * cost = ( unsigned * ) data ; unsigned retval = 0 ; if ( flag_vect_cost_model ) { tree vectype = stmt_info ? stmt_vectype ( stmt_info ) : NULL_TREE ; int stmt_cost = aarch64_builtin_vectorization_cost ( kind , vectype , misalign ) ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( stmt_info ) ) count *= 50 ; retval = ( unsigned ) ( count * stmt_cost ) ; cost [ where ] += retval ; } return retval ; } </s>


isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


<s> OffsetRange & shift ( int32_t S ) { Min += S ; Max += S ; Offset = ( Offset + S ) % Align ; return * this ; } </s>

Create a new AAMDNode that describes this AAMDNode after applying a constant offset to the start of the pointer .


<s> static unsigned int aarch64_sve_adjust_stmt_cost ( class vec_info * vinfo , vect_cost_for_stmt kind , stmt_vec_info stmt_info , tree vectype , unsigned int stmt_cost ) { if ( kind == vector_stmt && aarch64_extending_load_p ( vinfo , stmt_info ) ) stmt_cost = 0 ; if ( kind == vector_stmt && aarch64_integer_truncation_p ( stmt_info ) ) stmt_cost = 0 ; if ( STMT_VINFO_GROUPED_ACCESS ( stmt_info ) ) { stmt_vec_info first = DR_GROUP_FIRST_ELEMENT ( stmt_info ) ; unsigned int count = DR_GROUP_SIZE ( first ) - DR_GROUP_GAP ( first ) ; unsigned int elt_bits = GET_MODE_UNIT_BITSIZE ( TYPE_MODE ( vectype ) ) ; if ( multiple_p ( count * elt_bits , 256 ) && aarch64_advsimd_ldp_stp_p ( kind , stmt_info ) ) stmt_cost *= 2 ; } return stmt_cost ; } </s>

STMT_COST is the cost calculated by aarch64_builtin_vectorization_cost for STMT_INFO , which has cost kind KIND and which when vectorized would operate on vector type VECTYPE . Adjust the cost as necessary for SVE targets .


<s> unsigned PPCTTIImpl :: getIntrinsicInstrCost ( Intrinsic :: ID ID , Type * RetTy , ArrayRef < Type * > Tys , FastMathFlags FMF , unsigned ScalarizationCostPassed , const Instruction * I ) { if ( ID == Intrinsic :: bswap && ST -> hasP9Vector ( ) ) return TLI -> getTypeLegalizationCost ( DL , RetTy ) . first ; return BaseT :: getIntrinsicInstrCost ( ID , RetTy , Tys , FMF , ScalarizationCostPassed , I ) ; } </s>

PowerPC PPC Intrinsic::ID Intrinsic::bswap


<s>
void
dump
(
)
{
dbgs
(
)
<<
"WorkItem, iMask = "
<<
Mask
<<
" :\n"
;
for
(
auto
TI
:
Items
)
TI
->
dump
(
)
;
}
</s>

Dump the plan to stderr ( for debugging ) .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( ! EnableCheri128FailHard ) return false ; InstrInfo = MF . getSubtarget < MipsSubtarget > ( ) . getInstrInfo ( ) ; SmallVector < MachineInstr * , 16 > instrs ; std :: set < MachineBasicBlock * > bbs ; for ( auto & MBB : MF ) for ( auto & MI : MBB ) if ( ( MI . getOpcode ( ) == Mips :: CIncOffset ) || ( MI . getOpcode ( ) == Mips :: CSetOffset ) ) { instrs . push_back ( & MI ) ; bbs . insert ( & MBB ) ; } if ( instrs . empty ( ) ) return false ; MachineRegisterInfo & RI = MF . getRegInfo ( ) ; for ( auto * MI : instrs ) { Register tag_before = RI . createVirtualRegister ( & Mips :: GPR64RegClass ) ; Register tag_after = RI . createVirtualRegister ( & Mips :: GPR64RegClass ) ; auto & MBB = * MI -> getParent ( ) ; BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , InstrInfo -> get ( Mips :: CGetTag ) ) . addDef ( tag_before ) . addUse ( MI -> getOperand ( 1 ) . getReg ( ) ) ; MachineBasicBlock :: iterator after = BuildMI ( * MI -> getParent ( ) , ++ MachineBasicBlock :: iterator ( MI ) , MI -> getDebugLoc ( ) , InstrInfo -> get ( Mips :: CGetTag ) ) . addDef ( tag_after ) . addUse ( MI -> getOperand ( 0 ) . getReg ( ) ) . getInstr ( ) ; auto Sink = MF . CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF . insert ( ++ MachineFunction :: iterator ( MBB ) , Sink ) ; Sink -> splice ( Sink -> begin ( ) , & MBB , std :: next ( after ) , MBB . end ( ) ) ; Sink -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; MBB . addSuccessor ( Sink ) ; assert ( Sink -> getParent ( ) == & MF ) ; after = BuildMI ( MBB , ++ after , MI -> getDebugLoc ( ) , InstrInfo -> get ( Mips :: BEQ64 ) ) . addUse ( tag_after , RegState :: Kill ) . addUse ( tag_before , RegState :: Kill ) . addMBB ( Sink ) ; BuildMI ( MBB , ++ after , MI -> getDebugLoc ( ) , InstrInfo -> get ( Mips :: TRAP ) ) ; } return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> int arm_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( GET_MODE_CLASS ( mode ) == MODE_CC ) return ( regno == CC_REGNUM || ( TARGET_HARD_FLOAT && regno == VFPCC_REGNUM ) ) ; if ( regno == CC_REGNUM && GET_MODE_CLASS ( mode ) != MODE_CC ) return false ; if ( TARGET_THUMB1 ) return ( ARM_NUM_REGS ( mode ) < 2 ) || ( regno < LAST_LO_REGNUM ) ; if ( TARGET_HARD_FLOAT && IS_VFP_REGNUM ( regno ) ) { if ( mode == SFmode || mode == SImode ) return VFP_REGNO_OK_FOR_SINGLE ( regno ) ; if ( mode == DFmode ) return VFP_REGNO_OK_FOR_DOUBLE ( regno ) ; if ( mode == HFmode ) return VFP_REGNO_OK_FOR_SINGLE ( regno ) ; if ( mode == HImode ) return VFP_REGNO_OK_FOR_SINGLE ( regno ) ; if ( TARGET_NEON ) return ( VALID_NEON_DREG_MODE ( mode ) && VFP_REGNO_OK_FOR_DOUBLE ( regno ) ) || ( VALID_NEON_QREG_MODE ( mode ) && NEON_REGNO_OK_FOR_QUAD ( regno ) ) || ( mode == TImode && NEON_REGNO_OK_FOR_NREGS ( regno , 2 ) ) || ( mode == EImode && NEON_REGNO_OK_FOR_NREGS ( regno , 3 ) ) || ( mode == OImode && NEON_REGNO_OK_FOR_NREGS ( regno , 4 ) ) || ( mode == CImode && NEON_REGNO_OK_FOR_NREGS ( regno , 6 ) ) || ( mode == XImode && NEON_REGNO_OK_FOR_NREGS ( regno , 8 ) ) ; return FALSE ; } if ( TARGET_REALLY_IWMMXT ) { if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return mode == SImode ; if ( IS_IWMMXT_REGNUM ( regno ) ) return VALID_IWMMXT_REG_MODE ( mode ) ; } if ( regno <= LAST_ARM_REGNUM ) { if ( ARM_NUM_REGS ( mode ) > 4 ) return FALSE ; if ( TARGET_THUMB2 ) return TRUE ; return ! ( TARGET_LDRD && GET_MODE_SIZE ( mode ) > 4 && ( regno & 1 ) != 0 ) ; } if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return GET_MODE_CLASS ( mode ) == MODE_INT ; return FALSE ; } </s>

Returns true if REGNO is a valid register for holding a quantity of type MODE .


<s> static HOST_WIDE_INT loongarch_constant_alignment ( const_tree exp , HOST_WIDE_INT align ) { if ( TREE_CODE ( exp ) == STRING_CST || TREE_CODE ( exp ) == CONSTRUCTOR ) return MAX ( align , BITS_PER_WORD ) ; return align ; } </s>


<s> void GCNPassConfig :: addFastRegAlloc ( FunctionPass * RegAllocPass ) { TargetPassConfig :: addFastRegAlloc ( RegAllocPass ) ; } </s>

addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast register allocation .


<s> static void m32c_encode_section_info ( tree decl , rtx rtl , int first ) { int extra_flags = 0 ; default_encode_section_info ( decl , rtl , first ) ; if ( TREE_CODE ( decl ) == FUNCTION_DECL && m32c_special_page_vector_p ( decl ) ) extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION ; if ( extra_flags ) SYMBOL_REF_FLAGS ( XEXP ( rtl , 0 ) ) |= extra_flags ; } </s>

Encode symbol attributes of a SYMBOL_REF into its SYMBOL_REF_FLAGS .


<s> static int sh_register_move_cost ( machine_mode mode , reg_class_t srcclass , reg_class_t dstclass ) { if ( dstclass == T_REGS || dstclass == PR_REGS ) return 10 ; if ( dstclass == MAC_REGS && srcclass == MAC_REGS ) return 4 ; if ( mode == SImode && TARGET_FMOVD && REGCLASS_HAS_FP_REG ( srcclass ) && REGCLASS_HAS_FP_REG ( dstclass ) ) return 4 ; if ( REGCLASS_HAS_FP_REG ( dstclass ) && srcclass == T_REGS ) return ( ( TARGET_HARD_SH4 && ! optimize_size ) ? 10 : 7 ) ; if ( ( REGCLASS_HAS_FP_REG ( dstclass ) && srcclass == MAC_REGS ) || ( dstclass == MAC_REGS && REGCLASS_HAS_FP_REG ( srcclass ) ) ) return 9 ; if ( ( REGCLASS_HAS_FP_REG ( dstclass ) && REGCLASS_HAS_GENERAL_REG ( srcclass ) ) || ( REGCLASS_HAS_GENERAL_REG ( dstclass ) && REGCLASS_HAS_FP_REG ( srcclass ) ) ) { int addend = ( mode == Pmode ) ? 40 : 0 ; return ( ( TARGET_FMOVD ? 8 : 12 ) + addend ) * ( ( GET_MODE_SIZE ( mode ) + 7 ) / 8U ) ; } if ( ( dstclass == FPUL_REGS && REGCLASS_HAS_GENERAL_REG ( srcclass ) ) || ( srcclass == FPUL_REGS && REGCLASS_HAS_GENERAL_REG ( dstclass ) ) ) return 5 ; if ( ( dstclass == FPUL_REGS && ( srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS ) ) || ( srcclass == FPUL_REGS && ( dstclass == PR_REGS || dstclass == MAC_REGS ) ) ) return 7 ; if ( ( srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG ( dstclass ) ) || ( dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG ( srcclass ) ) ) return 4 ; if ( TARGET_FMOVD && ! REGCLASS_HAS_GENERAL_REG ( srcclass ) && ! REGCLASS_HAS_GENERAL_REG ( dstclass ) ) return 2 * ( ( GET_MODE_SIZE ( mode ) + 7 ) / 8U ) ; return 2 * ( ( GET_MODE_SIZE ( mode ) + 3 ) / 4U ) ; } </s>

If SECONDARY * _RELOAD_CLASS says something about the src/dst pair , regclass uses this information . Hence , the general register < - > floating point register information here is not used for SFmode .


"without AVX512F enabled changes the ABI"

Return the `` natural '' mode for TYPE . In most cases , this is just TYPE_MODE . But in the case of vector types , it is some vector mode . When we have only some of our vector isa extensions enabled , then there are some modes for which vector_mode_supported_p is false . For these modes , the generic vector support in gcc will choose some non-vector mode in order to implement the type . By computing the natural mode , we 'll select the proper ABI location for the operand and not depend on whatever the middle-end decides to do with these vector types .


<s> static bool rs6000_const_not_ok_for_debug_p ( rtx x ) { if ( GET_CODE ( x ) == UNSPEC ) return true ; if ( GET_CODE ( x ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) ) { rtx c = get_pool_constant ( x ) ; machine_mode cmode = get_pool_mode ( x ) ; if ( ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( c , cmode ) ) return true ; } return false ; } </s>

Return true if X should n't be emitted into the debug info . The linker does n't like .toc section references from .debug_ * sections , so reject .toc section symbols .


<s> void init_cumulative_args ( CUMULATIVE_ARGS * cum , tree fntype , rtx libname , tree fndecl , int caller ) { struct cgraph_local_info * i = NULL ; struct cgraph_node * target = NULL ; memset ( cum , 0 , sizeof ( * cum ) ) ; if ( fndecl ) { target = cgraph_node :: get ( fndecl ) ; if ( target ) { target = target -> function_symbol ( ) ; i = cgraph_node :: local_info ( target -> decl ) ; cum -> call_abi = ix86_function_abi ( target -> decl ) ; } else cum -> call_abi = ix86_function_abi ( fndecl ) ; } else cum -> call_abi = ix86_function_type_abi ( fntype ) ; cum -> caller = caller ; cum -> nregs = ix86_regparm ; if ( TARGET_64BIT ) { cum -> nregs = ( cum -> call_abi == SYSV_ABI ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX ) ; } if ( TARGET_SSE ) { cum -> sse_nregs = SSE_REGPARM_MAX ; if ( TARGET_64BIT ) { cum -> sse_nregs = ( cum -> call_abi == SYSV_ABI ? X86_64_SSE_REGPARM_MAX : X86_64_MS_SSE_REGPARM_MAX ) ; } } if ( TARGET_MMX ) cum -> mmx_nregs = MMX_REGPARM_MAX ; cum -> warn_avx512f = true ; cum -> warn_avx = true ; cum -> warn_sse = true ; cum -> warn_mmx = true ; if ( i && i -> local && i -> can_change_signature ) fntype = TREE_TYPE ( target -> decl ) ; cum -> stdarg = stdarg_p ( fntype ) ; cum -> maybe_vaarg = ( fntype ? ( ! prototype_p ( fntype ) || stdarg_p ( fntype ) ) : ! libname ) ; cum -> bnd_regno = FIRST_BND_REG ; cum -> bnds_in_bt = 0 ; cum -> force_bnd_pass = 0 ; cum -> decl = fndecl ; if ( ! TARGET_64BIT ) { if ( stdarg_p ( fntype ) ) { cum -> nregs = 0 ; cfun -> machine -> arg_reg_available = true ; cum -> sse_nregs = 0 ; cum -> mmx_nregs = 0 ; cum -> warn_avx512f = false ; cum -> warn_avx = false ; cum -> warn_sse = false ; cum -> warn_mmx = false ; return ; } if ( fntype ) { unsigned int ccvt = ix86_get_callcvt ( fntype ) ; if ( ( ccvt & IX86_CALLCVT_THISCALL ) != 0 ) { cum -> nregs = 1 ; cum -> fastcall = 1 ; } else if ( ( ccvt & IX86_CALLCVT_FASTCALL ) != 0 ) { cum -> nregs = 2 ; cum -> fastcall = 1 ; } else cum -> nregs = ix86_function_regparm ( fntype , fndecl ) ; } cum -> float_in_sse = ix86_function_sseregparm ( fntype , fndecl , true ) ; } cfun -> machine -> arg_reg_available = ( cum -> nregs > 0 ) ; } </s>

Handle the INIT_CUMULATIVE_ARGS macro . Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is 0 .


"converted opcode should be the same except for cc_out"

"expect uninitialized optional cc_out operand"

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


<s>
void
relaxInstruction
(
const
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
,
MCInst
&
Res
)
const
override
{
llvm_unreachable
(
"relaxInstruction() unimplemented"
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> bool SSACCmpConv :: isDeadDef ( unsigned DstReg ) { if ( DstReg == ARM64 :: WZR || DstReg == ARM64 :: XZR ) return true ; if ( ! TargetRegisterInfo :: isVirtualRegister ( DstReg ) ) return false ; return MRI -> use_nodbg_empty ( DstReg ) ; } </s>

Return true if this instruction has a dead def .


<s> static bool ix86_must_pass_in_stack ( machine_mode mode , const_tree type ) { if ( must_pass_in_stack_var_size_or_pad ( mode , type ) ) return true ; return ( ! TARGET_64BIT && mode == TImode && type && TREE_CODE ( type ) != VECTOR_TYPE ) ; } </s>

Return if we do not know how to pass TYPE solely in registers .


"ReadCycleWrite is only to be used on riscv32"

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> SDValue X86TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: VECTOR_SHUFFLE : return PerformShuffleCombine ( N , DAG , * this ) ; case ISD :: EXTRACT_VECTOR_ELT : return PerformEXTRACT_VECTOR_ELTCombine ( N , DAG , * this ) ; case ISD :: SELECT : return PerformSELECTCombine ( N , DAG , Subtarget ) ; case X86ISD :: CMOV : return PerformCMOVCombine ( N , DAG , DCI ) ; case ISD :: MUL : return PerformMulCombine ( N , DAG , DCI ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DAG , Subtarget ) ; case ISD :: OR : return PerformOrCombine ( N , DAG , Subtarget ) ; case ISD :: STORE : return PerformSTORECombine ( N , DAG , Subtarget ) ; case X86ISD :: FXOR : case X86ISD :: FOR : return PerformFORCombine ( N , DAG ) ; case X86ISD :: FAND : return PerformFANDCombine ( N , DAG ) ; case X86ISD :: BT : return PerformBTCombine ( N , DAG , DCI ) ; case X86ISD :: VZEXT_MOVL : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case ISD :: MEMBARRIER : return PerformMEMBARRIERCombine ( N , DAG ) ; case ISD :: ZERO_EXTEND : return PerformZExtCombine ( N , DAG ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> static bool arc_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { return ( ( to == FRAME_POINTER_REGNUM ) || ! arc_frame_pointer_needed ( ) ) ; } </s>

Given FROM and TO register numbers , say whether this elimination is allowed . Frame pointer elimination is automatically handled . All eliminations are permissible . If we need a frame pointer , we must eliminate ARG_POINTER_REGNUM into FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM .


<s> static bool rs6000_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { tree type ; if ( decl ) { if ( TARGET_ALTIVEC_VRSAVE ) { for ( type = TYPE_ARG_TYPES ( TREE_TYPE ( decl ) ) ; type ; type = TREE_CHAIN ( type ) ) { if ( TREE_CODE ( TREE_VALUE ( type ) ) == VECTOR_TYPE ) return false ; } } if ( DEFAULT_ABI == ABI_DARWIN || ( * targetm . binds_local_p ) ( decl ) ) { tree attr_list = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; if ( ! lookup_attribute ( "longcall" , attr_list ) || lookup_attribute ( "shortcall" , attr_list ) ) return true ; } } return false ; } </s>

Say whether a function is a candidate for sibcall handling or not . We do not allow indirect calls to be optimized into sibling calls . Also , we ca n't do it if there are any vector parameters ; there 's nowhere to put the VRsave code so it works ; note that functions with vector parameters are required to have a prototype , so the argument type info must be available here . ( The tail recursion case can work with vector parameters , but there 's no way to distinguish here . )


<s> const TargetRegisterClass * Cpu0SERegisterInfo :: intRegClass ( unsigned Size ) const { return & Cpu0 :: CPURegsRegClass ; } </s>


<s>
void
HexagonCommonGEP
::
collect
(
)
{
ValueVect
BO
;
getBlockTraversalOrder
(
&
Fn
->
front
(
)
,
BO
)
;
ValueToNodeMap
NM
;
for
(
Value
*
I
:
BO
)
{
BasicBlock
*
B
=
cast
<
BasicBlock
>
(
I
)
;
for
(
Instruction
&
J
:
*
B
)
if
(
auto
*
GepI
=
dyn_cast
<
GetElementPtrInst
>
(
&
J
)
)
if
(
isHandledGepForm
(
GepI
)
)
processGepInst
(
GepI
,
NM
)
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Gep nodes after initial collection:\n"
<<
Nodes
)
;
}
</s>

Analyze the given instruction MI and fill in the Uses , Defs and DeadDefs list based on the MachineOperand flags .

Hexagon
Hexagon
"Gep nodes after initial collection:\n"


<s> void ARMPassConfig :: addPreEmitPass ( ) { addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( createUnpackMachineBundles ( [ ] ( const MachineFunction & MF ) { return MF . getSubtarget < ARMSubtarget > ( ) . isThumb2 ( ) ; } ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createARMOptimizeBarriersPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> CSKYSubtarget & CSKYSubtarget :: initializeSubtargetDependencies ( const Triple & TT , StringRef CPUName , StringRef TuneCPUName , StringRef FS ) { if ( CPUName . empty ( ) ) CPUName = "generic" ; if ( TuneCPUName . empty ( ) ) TuneCPUName = CPUName ; UseHardFloat = false ; UseHardFloatABI = false ; HasFPUv2SingleFloat = false ; HasFPUv2DoubleFloat = false ; HasFPUv3SingleFloat = false ; HasFPUv3DoubleFloat = false ; HasBTST16 = false ; HasJAVA = false ; HasExtendLrw = false ; HasDoloop = false ; HasHighRegisters = false ; HasE1 = false ; HasE2 = false ; Has2E3 = false ; HasMP = false ; Has3E3r1 = false ; Has3r1E3r2 = false ; Has3r2E3r3 = false ; Has3E7 = false ; HasMP1E2 = false ; Has7E10 = false ; Has10E60 = false ; ParseSubtargetFeatures ( CPUName , TuneCPUName , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> const MCExpr * PPCTargetLowering :: getPICJumpTableRelocBaseExpr ( const MachineFunction * MF , unsigned JTI , MCContext & Ctx ) const { if ( ! Subtarget . isPPC64 ( ) ) return TargetLowering :: getPICJumpTableRelocBaseExpr ( MF , JTI , Ctx ) ; switch ( getTargetMachine ( ) . getCodeModel ( ) ) { case CodeModel :: Default : case CodeModel :: Small : case CodeModel :: Medium : return TargetLowering :: getPICJumpTableRelocBaseExpr ( MF , JTI , Ctx ) ; default : return MCSymbolRefExpr :: create ( MF -> getPICBaseSymbol ( ) , Ctx ) ; } } </s>

This returns the relocation base for the given PIC jumptable , the same as getPICJumpTableRelocBase , but as an MCExpr .


<s> static bool mips_int_order_operand_ok_p ( enum rtx_code code , rtx cmp1 ) { switch ( code ) { case GT : case GTU : return reg_or_0_operand ( cmp1 , VOIDmode ) ; case GE : case GEU : return ! TARGET_MIPS16 && cmp1 == const1_rtx ; case LT : case LTU : return arith_operand ( cmp1 , VOIDmode ) ; case LE : return sle_operand ( cmp1 , VOIDmode ) ; case LEU : return sleu_operand ( cmp1 , VOIDmode ) ; default : gcc_unreachable ( ) ; } } </s>

Return true if CMP1 is a suitable second operand for integer ordering test CODE . See also the * sCC patterns in mips.md .


<s> const WebAssemblyRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool isCheapToSpeculateCtlz ( ) const override { return true ; } </s>

Return true if it is cheap to speculate a call to intrinsic ctlz .


"Hardware instruction generated for atomic "

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> unsigned getEUsPerCU ( ) const { return AMDGPU :: IsaInfo :: getEUsPerCU ( MCSubtargetInfo :: getFeatureBits ( ) ) ; } </s>

Number of SIMDs/EUs ( execution units ) per `` CU '' ( `` compute unit '' ) , where the `` CU '' is the unit onto which workgroups are mapped .


<s> bool M68kTargetLowering :: decomposeMulByConstant ( LLVMContext & Context , EVT VT , SDValue C ) const { return VT . bitsLE ( MVT :: i32 ) || Subtarget . atLeastM68020 ( ) ; } </s>

Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds .


<s>
bool
X86RegisterInfo
::
getRegAllocationHints
(
Register
VirtReg
,
ArrayRef
<
MCPhysReg
>
Order
,
SmallVectorImpl
<
MCPhysReg
>
&
Hints
,
const
MachineFunction
&
MF
,
const
VirtRegMap
*
VRM
,
const
LiveRegMatrix
*
Matrix
)
const
{
const
MachineRegisterInfo
*
MRI
=
&
MF
.
getRegInfo
(
)
;
const
TargetRegisterClass
&
RC
=
*
MRI
->
getRegClass
(
VirtReg
)
;
bool
BaseImplRetVal
=
TargetRegisterInfo
::
getRegAllocationHints
(
VirtReg
,
Order
,
Hints
,
MF
,
VRM
,
Matrix
)
;
if
(
RC
.
getID
(
)
!=
X86
::
TILERegClassID
)
return
BaseImplRetVal
;
ShapeT
VirtShape
=
getTileShape
(
VirtReg
,
const_cast
<
VirtRegMap
*
>
(
VRM
)
,
MRI
)
;
auto
AddHint
=
[
&
]
(
MCPhysReg
PhysReg
)
{
Register
VReg
=
Matrix
->
getOneVReg
(
PhysReg
)
;
if
(
VReg
==
MCRegister
::
NoRegister
)
{
Hints
.
push_back
(
PhysReg
)
;
return
;
}
ShapeT
PhysShape
=
getTileShape
(
VReg
,
const_cast
<
VirtRegMap
*
>
(
VRM
)
,
MRI
)
;
if
(
PhysShape
==
VirtShape
)
Hints
.
push_back
(
PhysReg
)
;
}
;
SmallSet
<
MCPhysReg
,
4
>
CopyHints
;
CopyHints
.
insert
(
Hints
.
begin
(
)
,
Hints
.
end
(
)
)
;
Hints
.
clear
(
)
;
for
(
auto
Hint
:
CopyHints
)
{
if
(
RC
.
contains
(
Hint
)
&&
!
MRI
->
isReserved
(
Hint
)
)
AddHint
(
Hint
)
;
}
for
(
MCPhysReg
PhysReg
:
Order
)
{
if
(
!
CopyHints
.
count
(
PhysReg
)
&&
RC
.
contains
(
PhysReg
)
&&
!
MRI
->
isReserved
(
PhysReg
)
)
AddHint
(
PhysReg
)
;
}
LLVM_DEBUG
(
{
dbgs
(
)
<<
"Hints for virtual register "
<<
format_hex
(
VirtReg
,
8
)
<<
"\n"
;
for
(
auto
Hint
:
Hints
)
{
dbgs
(
)
<<
"tmm"
<<
Hint
<<
","
;
}
dbgs
(
)
<<
"\n"
;
}
</s>

Get a list of 'hint ' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg .


<s> unsigned char X86Subtarget :: classifyGlobalFunctionReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return X86II :: MO_NO_FLAG ; if ( isTargetCOFF ( ) ) { if ( GV -> hasDLLImportStorageClass ( ) ) return X86II :: MO_DLLIMPORT ; return X86II :: MO_COFFSTUB ; } const Function * F = dyn_cast_or_null < Function > ( GV ) ; if ( isTargetELF ( ) ) { if ( is64Bit ( ) && F && ( CallingConv :: X86_RegCall == F -> getCallingConv ( ) ) ) return X86II :: MO_GOTPCREL ; if ( ( ( F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) ) || ( ! F && M . getRtLibUseGOT ( ) ) ) && is64Bit ( ) ) return X86II :: MO_GOTPCREL ; if ( ! is64Bit ( ) && ! GV && TM . getRelocationModel ( ) == Reloc :: Static ) return X86II :: MO_NO_FLAG ; return X86II :: MO_PLT ; } if ( is64Bit ( ) ) { if ( F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) ) return X86II :: MO_GOTPCREL ; return X86II :: MO_NO_FLAG ; } return X86II :: MO_NO_FLAG ; } </s>

Classify a global function reference for the current subtarget .


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BRCOND : return lowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return lowerConstantPool ( Op , DAG ) ; case ISD :: GlobalAddress : return lowerGlobalAddress ( Op , DAG ) ; case ISD :: BlockAddress : return lowerBlockAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return lowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return lowerJumpTable ( Op , DAG ) ; case ISD :: SELECT : return lowerSELECT ( Op , DAG ) ; case ISD :: SETCC : return lowerSETCC ( Op , DAG ) ; case ISD :: VASTART : return lowerVASTART ( Op , DAG ) ; case ISD :: VAARG : return lowerVAARG ( Op , DAG ) ; case ISD :: FCOPYSIGN : return lowerFCOPYSIGN ( Op , DAG ) ; case ISD :: FABS : return lowerFABS ( Op , DAG ) ; case ISD :: FRAMEADDR : return lowerFRAMEADDR ( Op , DAG ) ; case ISD :: RETURNADDR : return lowerRETURNADDR ( Op , DAG ) ; case ISD :: EH_RETURN : return lowerEH_RETURN ( Op , DAG ) ; case ISD :: ATOMIC_FENCE : return lowerATOMIC_FENCE ( Op , DAG ) ; case ISD :: SHL_PARTS : return lowerShiftLeftParts ( Op , DAG ) ; case ISD :: SRA_PARTS : return lowerShiftRightParts ( Op , DAG , true ) ; case ISD :: SRL_PARTS : return lowerShiftRightParts ( Op , DAG , false ) ; case ISD :: LOAD : return lowerLOAD ( Op , DAG ) ; case ISD :: STORE : return lowerSTORE ( Op , DAG ) ; case ISD :: EH_DWARF_CFA : return lowerEH_DWARF_CFA ( Op , DAG ) ; case ISD :: FP_TO_SINT : return lowerFP_TO_SINT ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::BRCOND ISD::ConstantPool ISD::GlobalAddress ISD::BlockAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::SELECT ISD::SETCC ISD::VASTART ISD::VAARG ISD::FCOPYSIGN ISD::FABS ISD::FRAMEADDR ISD::RETURNADDR ISD::EH_RETURN ISD::ATOMIC_FENCE ISD::SHL_PARTS ISD::SRA_PARTS ISD::SRL_PARTS ISD::LOAD ISD::STORE ISD::EH_DWARF_CFA ISD::FP_TO_SINT


<s> bool MipsInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock & MBB = * MI -> getParent ( ) ; switch ( MI -> getDesc ( ) . getOpcode ( ) ) { default : return false ; case Mips :: BuildPairF64 : ExpandBuildPairF64 ( MBB , MI ) ; break ; case Mips :: ExtractElementF64 : ExpandExtractElementF64 ( MBB , MI ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s>
bool
X86CallLowering
::
lowerReturn
(
MachineIRBuilder
&
MIRBuilder
,
const
Value
*
Val
,
unsigned
VReg
)
const
{
assert
(
(
(
Val
&&
VReg
)
||
(
!
Val
&&
!
VReg
)
)
&&
"Return value without a vreg"
)
;
auto
MIB
=
MIRBuilder
.
buildInstrNoInsert
(
X86
::
RET
)
.
addImm
(
0
)
;
if
(
VReg
)
{
MachineFunction
&
MF
=
MIRBuilder
.
getMF
(
)
;
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
auto
&
DL
=
MF
.
getDataLayout
(
)
;
const
Function
&
F
=
*
MF
.
getFunction
(
)
;
ArgInfo
OrigArg
{
VReg
,
Val
->
getType
(
)
}
;
setArgFlags
(
OrigArg
,
AttributeList
::
ReturnIndex
,
DL
,
F
)
;
SmallVector
<
ArgInfo
,
8
>
SplitArgs
;
if
(
!
splitToValueTypes
(
OrigArg
,
SplitArgs
,
DL
,
MRI
,
[
&
]
(
ArrayRef
<
unsigned
>
Regs
)
{
MIRBuilder
.
buildUnmerge
(
Regs
,
VReg
)
;
}
)
)
return
false
;
OutgoingValueHandler
Handler
(
MIRBuilder
,
MRI
,
MIB
,
RetCC_X86
)
;
if
(
!
handleAssignments
(
MIRBuilder
,
SplitArgs
,
Handler
)
)
return
false
;
}
MIRBuilder
.
insertInstr
(
MIB
)
;
return
true
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; for ( MachineBasicBlock & mbb : MF ) { dbgs ( ) << "\n" ; for ( MachineInstr & mi : mbb ) { dbgs ( ) << ">>>" << TII -> getName ( mi . getOpcode ( ) ) << "\n" ; } } } </s>

runOnMachineFunction - Emit the function body .


<s> bool PPCDispatchGroupSBHazardRecognizer :: ShouldPreferAnother ( SUnit * SU ) { const MCInstrDesc * MCID = DAG -> getInstrDesc ( SU ) ; unsigned NSlots ; if ( MCID && mustComeFirst ( MCID , NSlots ) && CurSlots ) return true ; return ScoreboardHazardRecognizer :: ShouldPreferAnother ( SU ) ; } </s>

ShouldPreferAnother - This callback may be invoked if getHazardType returns NoHazard .


<s> unsigned MipsFastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return ( UnsupportedFPMode ) ? 0 : materializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return materializeGV ( GV , VT ) ; else if ( isa < ConstantInt > ( C ) ) return materializeInt ( C , VT ) ; return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s> void s390_register_target_pragmas ( void ) { targetm . resolve_overloaded_builtin = s390_resolve_overloaded_builtin ; targetm . target_option . pragma_parse = s390_pragma_target_parse ; } </s>

This is used to define the REGISTER_TARGET_PRAGMAS macro in s390.h .


<s> static bool indexable_address_p ( rtx xfoo0 , rtx xfoo1 , machine_mode mode , bool strict ) { if ( ! CONSTANT_ADDRESS_P ( xfoo0 ) ) return false ; if ( BASE_REGISTER_P ( xfoo1 , strict ) ) return ! flag_pic || mode == QImode ; if ( flag_pic && symbolic_operand ( xfoo0 , SImode ) ) return false ; return reg_plus_index_p ( xfoo1 , mode , strict ) ; } </s>

Return true if xfoo0 and xfoo1 constitute a valid indexed address .


Execute an already-loaded kernel on the device .


<s> virtual void initializePass ( ) { pushTTIStack ( this ) ; } </s>

initializePass - This method may be overriden by immutable passes to allow them to perform various initialization actions they require .


<s>
void
LC3MCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
if
(
Desc
.
getSize
(
)
!=
2
)
{
llvm_unreachable
(
"Unexpected instruction size!"
)
;
}
const
uint32_t
Binary
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
EmitConstant
(
Binary
,
Desc
.
getSize
(
)
,
OS
)
;
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .


<s> bool quad_address_p ( rtx addr , machine_mode mode , bool strict ) { rtx op0 , op1 ; if ( GET_MODE_SIZE ( mode ) != 16 ) return false ; if ( legitimate_indirect_address_p ( addr , strict ) ) return true ; if ( VECTOR_MODE_P ( mode ) && ! mode_supports_vsx_dform_quad ( mode ) ) return false ; if ( GET_CODE ( addr ) != PLUS ) return false ; op0 = XEXP ( addr , 0 ) ; if ( ! REG_P ( op0 ) || ! INT_REG_OK_FOR_BASE_P ( op0 , strict ) ) return false ; op1 = XEXP ( addr , 1 ) ; if ( ! CONST_INT_P ( op1 ) ) return false ; return quad_address_offset_p ( INTVAL ( op1 ) ) ; } </s>

Return true if the ADDR is an acceptable address for a quad memory operation of mode MODE ( either LQ/STQ for general purpose registers , or LXV/STXV for vector registers under ISA 3.0 . GPR_P is true if this address is intended for LQ/STQ . If it is false , the address is intended for the ISA 3.0 LXV/STXV instruction .


<s> unsigned AMDGPUPALMetadata :: getType ( ) const { return BlobType ; } </s>

Overload to return most specific vector type .


<s> static int ix86_issue_rate ( void ) { switch ( ix86_tune ) { case PROCESSOR_PENTIUM : case PROCESSOR_BONNELL : case PROCESSOR_SILVERMONT : case PROCESSOR_KNL : case PROCESSOR_INTEL : case PROCESSOR_K6 : case PROCESSOR_BTVER2 : case PROCESSOR_PENTIUM4 : case PROCESSOR_NOCONA : return 2 ; case PROCESSOR_PENTIUMPRO : case PROCESSOR_ATHLON : case PROCESSOR_K8 : case PROCESSOR_AMDFAM10 : case PROCESSOR_GENERIC : case PROCESSOR_BTVER1 : return 3 ; case PROCESSOR_BDVER1 : case PROCESSOR_BDVER2 : case PROCESSOR_BDVER3 : case PROCESSOR_BDVER4 : case PROCESSOR_CORE2 : case PROCESSOR_NEHALEM : case PROCESSOR_SANDYBRIDGE : case PROCESSOR_HASWELL : return 4 ; default : return 1 ; } } </s>

Return the maximum number of instructions a cpu can issue .


<s> bool OptimizeLEAPass :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; if ( DisableX86LEAOpt || skipFunction ( MF . getFunction ( ) ) ) return false ; MRI = & MF . getRegInfo ( ) ; TII = MF . getSubtarget < X86Subtarget > ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget < X86Subtarget > ( ) . getRegisterInfo ( ) ; for ( auto & MBB : MF ) { MemOpMap LEAs ; InstrPos . clear ( ) ; findLEAs ( MBB , LEAs ) ; if ( LEAs . empty ( ) ) continue ; Changed |= removeRedundantLEAs ( LEAs ) ; if ( MF . getFunction ( ) . hasOptSize ( ) ) Changed |= removeRedundantAddrCalc ( LEAs ) ; } return Changed ; } </s>


<s>
void
RV16KAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
if
(
!
Value
)
return
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
Ctx
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
unsigned
NumBytes
=
alignTo
(
Info
.
TargetSize
+
Info
.
TargetOffset
,
8
)
/
8
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


"WebAssembly Fix Irreducible Control Flow"

getPassName - Return a nice clean name for a pass .


<s>
void
assignValueToReg
(
Register
ValVReg
,
Register
PhysReg
,
CCValAssign
&
VA
)
override
{
assert
(
VA
.
isRegLoc
(
)
&&
"Value shouldn't be assigned to reg"
)
;
assert
(
VA
.
getLocReg
(
)
==
PhysReg
&&
"Assigning to the wrong reg?"
)
;
auto
ValSize
=
VA
.
getValVT
(
)
.
getSizeInBits
(
)
;
auto
LocSize
=
VA
.
getLocVT
(
)
.
getSizeInBits
(
)
;
assert
(
ValSize
<=
64
&&
"Unsupported value size"
)
;
assert
(
LocSize
<=
64
&&
"Unsupported location size"
)
;
markPhysRegUsed
(
PhysReg
)
;
if
(
ValSize
==
LocSize
)
{
MIRBuilder
.
buildCopy
(
ValVReg
,
PhysReg
)
;
}
else
{
assert
(
ValSize
<
LocSize
&&
"Extensions not supported"
)
;
auto
PhysRegToVReg
=
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
LocSize
)
)
;
MIRBuilder
.
buildCopy
(
PhysRegToVReg
,
PhysReg
)
;
MIRBuilder
.
buildTrunc
(
ValVReg
,
PhysRegToVReg
)
;
}
}
</s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .

ARM
"Value shouldn't be assigned to reg"
"Assigning to the wrong reg?"
64
"Unsupported value size"
64
"Unsupported location size"
"Extensions not supported"


<s> bool X86PassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( ) ) ; return false ; } </s>

This method should install a ( global ) instruction selector pass , which converts possibly generic instructions to fully target-specific instructions , thereby constraining all generic virtual registers to register classes .


<s> uint64_t VESubtarget :: getAdjustedFrameSize ( uint64_t FrameSize ) const { const VEFrameLowering * TFL = getFrameLowering ( ) ; FrameSize += getRsaSize ( ) ; FrameSize = alignTo ( FrameSize , TFL -> getStackAlign ( ) ) ; return FrameSize ; } </s>

Given a actual stack size as determined by FrameInfo , this function returns adjusted framesize which includes space for RSA , return address , and frame poitner .


"Only 32/64-bit atomic stores supported"

Perform a store-conditional operation to Addr .


<s>
void
aarch64_print_hint_for_extensions
(
const
std
::
string
&
str
)
{
auto_vec
<
const
char
*
>
candidates
;
aarch64_get_all_extension_candidates
(
&
candidates
)
;
char
*
s
;
const
char
*
hint
=
candidates_list_and_hint
(
str
.
c_str
(
)
,
s
,
candidates
)
;
if
(
hint
)
inform
(
input_location
,
"valid arguments are: %s;"
" did you mean %qs?"
,
s
,
hint
)
;
else
inform
(
input_location
,
"valid arguments are: %s;"
,
s
)
;
XDELETEVEC
(
s
)
;
}
</s>

Print a hint with a suggestion for an extension name that most closely resembles what the user passed in STR .

aarch64
"valid arguments are: %s;"
" did you mean %qs?"
"valid arguments are: %s;"


<s> const TargetRegisterClass * MOSRegisterInfo :: getCrossCopyRegClass ( const TargetRegisterClass * RC ) const { if ( RC == & MOS :: Imag8RegClass ) return & MOS :: GPRRegClass ; if ( RC == & MOS :: YcRegClass || RC == & MOS :: XYRegClass ) return & MOS :: AImag8RegClass ; return RC ; } </s>

getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or from .

MOS MOS MOS::Imag8RegClass MOS::GPRRegClass MOS::YcRegClass MOS::XYRegClass MOS::AImag8RegClass


<s>
static
tree
resolve_vec_splats
(
resolution
*
res
,
rs6000_gen_builtins
fcode
,
vec
<
tree
,
va_gc
>
*
arglist
,
unsigned
nargs
)
{
const
char
*
name
;
name
=
fcode
==
RS6000_OVLD_VEC_SPLATS
"vec_splats"
:
"vec_promote"
;
if
(
fcode
==
RS6000_OVLD_VEC_SPLATS
&&
nargs
!=
1
)
{
error
(
"builtin %qs only accepts 1 argument"
,
name
)
;
*
res
=
resolved
;
return
error_mark_node
;
}
if
(
fcode
==
RS6000_OVLD_VEC_PROMOTE
&&
nargs
!=
2
)
{
error
(
"builtin %qs only accepts 2 arguments"
,
name
)
;
*
res
=
resolved
;
return
error_mark_node
;
}
if
(
fcode
==
RS6000_OVLD_VEC_PROMOTE
&&
!
INTEGRAL_TYPE_P
(
TREE_TYPE
(
(
*
arglist
)
[
1
]
)
)
)
{
*
res
=
resolved_bad
;
return
error_mark_node
;
}
tree
arg
=
(
*
arglist
)
[
0
]
;
tree
type
=
TREE_TYPE
(
arg
)
;
if
(
!
SCALAR_FLOAT_TYPE_P
(
type
)
&&
!
INTEGRAL_TYPE_P
(
type
)
)
{
*
res
=
resolved_bad
;
return
error_mark_node
;
}
bool
unsigned_p
=
TYPE_UNSIGNED
(
type
)
;
int
size
;
switch
(
TYPE_MODE
(
type
)
)
{
case
E_TImode
:
type
=
unsigned_p
unsigned_V1TI_type_node
:
V1TI_type_node
;
size
=
1
;
break
;
case
E_DImode
:
type
=
unsigned_p
unsigned_V2DI_type_node
:
V2DI_type_node
;
size
=
2
;
break
;
case
E_SImode
:
type
=
unsigned_p
unsigned_V4SI_type_node
:
V4SI_type_node
;
size
=
4
;
break
;
case
E_HImode
:
type
=
unsigned_p
unsigned_V8HI_type_node
:
V8HI_type_node
;
size
=
8
;
break
;
case
E_QImode
:
type
=
unsigned_p
unsigned_V16QI_type_node
:
V16QI_type_node
;
size
=
16
;
break
;
case
E_SFmode
:
type
=
V4SF_type_node
;
size
=
4
;
break
;
case
E_DFmode
:
type
=
V2DF_type_node
;
size
=
2
;
break
;
default
:
*
res
=
resolved_bad
;
return
error_mark_node
;
}
arg
=
save_expr
(
fold_convert
(
TREE_TYPE
(
type
)
,
arg
)
)
;
vec
<
constructor_elt
,
va_gc
>
*
vec
;
vec_alloc
(
vec
,
size
)
;
for
(
int
i
=
0
;
i
<
size
;
i
++
)
{
constructor_elt
elt
=
{
NULL_TREE
,
arg
}
;
vec
->
quick_push
(
elt
)
;
}
*
res
=
resolved
;
return
build_constructor
(
type
,
vec
)
;
}
</s>

Resolve an overloaded vec_splats or vec_promote call and return a tree expression for the resolved call if successful . NARGS is the number of arguments to the call . ARGLIST contains the arguments . RES must be set to indicate the status of the resolution attempt .


<s> unsigned X86FastISel :: fastMaterializeFloatZero ( const ConstantFP * CF ) { MVT VT ; if ( ! isTypeLegal ( CF -> getType ( ) , VT ) ) return 0 ; unsigned Opc = 0 ; const TargetRegisterClass * RC = nullptr ; switch ( VT . SimpleTy ) { default : return 0 ; case MVT :: f32 : if ( X86ScalarSSEf32 ) { Opc = X86 :: FsFLD0SS ; RC = & X86 :: FR32RegClass ; } else { Opc = X86 :: LD_Fp032 ; RC = & X86 :: RFP32RegClass ; } break ; case MVT :: f64 : if ( X86ScalarSSEf64 ) { Opc = X86 :: FsFLD0SD ; RC = & X86 :: FR64RegClass ; } else { Opc = X86 :: LD_Fp064 ; RC = & X86 :: RFP64RegClass ; } break ; case MVT :: f80 : return 0 ; } unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; return ResultReg ; } </s>

Emit the floating-point constant +0.0 in a register using target- specific logic .


"Can't store this register to stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> int m32c_eh_return_data_regno ( int n ) { switch ( n ) { case 0 : return MEM0_REGNO ; case 1 : return MEM0_REGNO + 4 ; default : return INVALID_REGNUM ; } } </s>

Implements EH_RETURN_DATA_REGNO . Choose registers able to hold pointers .


"\n\n// br.call targets referenced (and not defined) above: \n"

"\n\n// (external) symbols referenced (and not defined) above: \n"

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s>
bool
SystemZInstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
!
isUnpredicatedTerminator
(
*
I
)
)
break
;
if
(
!
I
->
isBranch
(
)
)
return
true
;
SystemZII
::
Branch
Branch
(
getBranchInfo
(
*
I
)
)
;
if
(
!
Branch
.
Target
->
isMBB
(
)
)
return
true
;
if
(
Branch
.
Type
!=
SystemZII
::
BranchNormal
)
return
true
;
if
(
Branch
.
CCMask
==
SystemZ
::
CCMASK_ANY
)
{
if
(
!
AllowModify
)
{
TBB
=
Branch
.
Target
->
getMBB
(
)
;
continue
;
}
while
(
std
::
next
(
I
)
!=
MBB
.
end
(
)
)
std
::
next
(
I
)
->
eraseFromParent
(
)
;
Cond
.
clear
(
)
;
FBB
=
nullptr
;
if
(
MBB
.
isLayoutSuccessor
(
Branch
.
Target
->
getMBB
(
)
)
)
{
TBB
=
nullptr
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
continue
;
}
TBB
=
Branch
.
Target
->
getMBB
(
)
;
continue
;
}
if
(
Cond
.
empty
(
)
)
{
FBB
=
TBB
;
TBB
=
Branch
.
Target
->
getMBB
(
)
;
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
Branch
.
CCValid
)
)
;
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
Branch
.
CCMask
)
)
;
continue
;
}
assert
(
Cond
.
size
(
)
==
2
&&
TBB
&&
"Should have seen a conditional branch"
)
;
if
(
TBB
!=
Branch
.
Target
->
getMBB
(
)
)
return
true
;
unsigned
OldCCValid
=
Cond
[
0
]
.
getImm
(
)
;
unsigned
OldCCMask
=
Cond
[
1
]
.
getImm
(
)
;
if
(
OldCCValid
==
Branch
.
CCValid
&&
OldCCMask
==
Branch
.
CCMask
)
continue
;
return
false
;
}
return
false
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .