<s> static bool s390_short_displacement ( rtx disp ) { if ( ! disp ) return true ; if ( ! TARGET_LONG_DISPLACEMENT ) return true ; if ( GET_CODE ( disp ) == CONST_INT ) return INTVAL ( disp ) >= 0 && INTVAL ( disp ) < 4096 ; if ( GET_CODE ( disp ) == CONST && GET_CODE ( XEXP ( disp , 0 ) ) == UNSPEC && ( XINT ( XEXP ( disp , 0 ) , 1 ) == UNSPEC_GOT || XINT ( XEXP ( disp , 0 ) , 1 ) == UNSPEC_GOTNTPOFF ) ) return false ; if ( GET_CODE ( disp ) == CONST ) return true ; return false ; } </s>

Return true if DISP is a valid short displacement .


<s> int msp430_hard_regno_nregs_with_padding ( int regno ATTRIBUTE_UNUSED , machine_mode mode ) { if ( mode == PSImode ) return 2 ; if ( mode == CPSImode ) return 4 ; return msp430_hard_regno_nregs ( regno , mode ) ; } </s>


<s> void GBZ80MCCodeEmitter :: emitInstruction ( uint64_t Val , unsigned Size , const MCSubtargetInfo & STI , raw_ostream & OS ) const { const uint16_t * Words = reinterpret_cast < uint16_t const * > ( & Val ) ; size_t WordCount = Size / 2 ; for ( int64_t i = WordCount - 1 ; i >= 0 ; -- i ) { uint16_t Word = Words [ i ] ; OS << ( uint8_t ) ( ( Word & 0x00ff ) >> 0 ) ; OS << ( uint8_t ) ( ( Word & 0xff00 ) >> 8 ) ; } } </s>

Targets should implement this to emit instructions .


<s> static bool rs6000_function_ok_for_sibcall ( tree decl , tree exp ) { tree fntype ; if ( decl ) fntype = TREE_TYPE ( decl ) ; else fntype = TREE_TYPE ( TREE_TYPE ( CALL_EXPR_FN ( exp ) ) ) ; if ( TARGET_ALTIVEC_ABI && TARGET_ALTIVEC_VRSAVE && ! ( decl && decl == current_function_decl ) ) { function_args_iterator args_iter ; tree type ; int nvreg = 0 ; FOREACH_FUNCTION_ARGS ( fntype , type , args_iter ) if ( TREE_CODE ( type ) == VECTOR_TYPE && ALTIVEC_OR_VSX_VECTOR_MODE ( TYPE_MODE ( type ) ) ) nvreg ++ ; FOREACH_FUNCTION_ARGS ( TREE_TYPE ( current_function_decl ) , type , args_iter ) if ( TREE_CODE ( type ) == VECTOR_TYPE && ALTIVEC_OR_VSX_VECTOR_MODE ( TYPE_MODE ( type ) ) ) nvreg -- ; if ( nvreg > 0 ) return false ; } if ( DEFAULT_ABI == ABI_DARWIN || ( ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) && decl && ! DECL_EXTERNAL ( decl ) && ! DECL_WEAK ( decl ) && ( * targetm . binds_local_p ) ( decl ) ) || ( DEFAULT_ABI == ABI_V4 && ( ! TARGET_SECURE_PLT || ! flag_pic || ( decl && ( * targetm . binds_local_p ) ( decl ) ) ) ) ) { tree attr_list = TYPE_ATTRIBUTES ( fntype ) ; if ( ! lookup_attribute ( "longcall" , attr_list ) || lookup_attribute ( "shortcall" , attr_list ) ) return true ; } return false ; } </s>

Say whether a function is a candidate for sibcall handling or not . We do not allow indirect calls to be optimized into sibling calls . Also , we ca n't do it if there are any vector parameters ; there 's nowhere to put the VRsave code so it works ; note that functions with vector parameters are required to have a prototype , so the argument type info must be available here . ( The tail recursion case can work with vector parameters , but there 's no way to distinguish here . )


<s> void mprocInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool WebAssemblyInstrInfo :: isReallyTriviallyReMaterializable ( const MachineInstr & MI , AAResults * AA ) const { switch ( MI . getOpcode ( ) ) { case WebAssembly :: CONST_I32 : case WebAssembly :: CONST_I64 : case WebAssembly :: CONST_F32 : case WebAssembly :: CONST_F64 : return true ; default : return false ; } } </s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> static tree tilepro_gimplify_va_arg_expr ( tree valist , tree type , gimple_seq * pre_p , gimple_seq * post_p ATTRIBUTE_UNUSED ) { tree f_args , f_skip ; tree args , skip ; HOST_WIDE_INT size , rsize ; tree addr , tmp ; bool pass_by_reference_p ; f_args = TYPE_FIELDS ( va_list_type_node ) ; f_skip = TREE_CHAIN ( f_args ) ; args = build3 ( COMPONENT_REF , TREE_TYPE ( f_args ) , valist , f_args , NULL_TREE ) ; skip = build3 ( COMPONENT_REF , TREE_TYPE ( f_skip ) , valist , f_skip , NULL_TREE ) ; addr = create_tmp_var ( ptr_type_node , "va_arg" ) ; pass_by_reference_p = pass_va_arg_by_reference ( type ) ; if ( pass_by_reference_p ) type = build_pointer_type ( type ) ; size = int_size_in_bytes ( type ) ; rsize = ( ( size + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ) * UNITS_PER_WORD ; if ( TYPE_ALIGN ( type ) > PARM_BOUNDARY ) { gcc_assert ( STACK_BOUNDARY == PARM_BOUNDARY * 2 ) ; tmp = build2 ( BIT_AND_EXPR , sizetype , fold_convert ( sizetype , unshare_expr ( args ) ) , size_int ( PARM_BOUNDARY / 8 ) ) ; tmp = build2 ( POINTER_PLUS_EXPR , ptr_type_node , unshare_expr ( args ) , tmp ) ; gimplify_assign ( unshare_expr ( args ) , tmp , pre_p ) ; } tmp = fold_build_pointer_plus_hwi ( unshare_expr ( args ) , rsize ) ; tmp = build2 ( TRUTH_AND_EXPR , boolean_type_node , build2 ( GT_EXPR , boolean_type_node , tmp , unshare_expr ( skip ) ) , build2 ( LE_EXPR , boolean_type_node , unshare_expr ( args ) , unshare_expr ( skip ) ) ) ; tmp = build3 ( COND_EXPR , ptr_type_node , tmp , build2 ( POINTER_PLUS_EXPR , ptr_type_node , unshare_expr ( skip ) , size_int ( STACK_POINTER_OFFSET ) ) , unshare_expr ( args ) ) ; gimplify_assign ( addr , tmp , pre_p ) ; tmp = fold_build_pointer_plus_hwi ( addr , rsize ) ; gimplify_assign ( unshare_expr ( args ) , tmp , pre_p ) ; addr = fold_convert ( build_pointer_type ( type ) , addr ) ; if ( pass_by_reference_p ) addr = build_va_arg_indirect_ref ( addr ) ; return build_va_arg_indirect_ref ( addr ) ; } </s>

Implement TARGET_GIMPLIFY_VA_ARG_EXPR . Gimplify va_arg by updating the va_list structure VALIST as required to retrieve an argument of type TYPE , and returning that argument . ret = va_arg ( VALIST , TYPE ) ; generates code equivalent to : paddedsize = ( sizeof ( TYPE ) + 3 ) & -4 ; if ( ( VALIST.__args + paddedsize > VALIST.__skip ) & ( VALIST.__args < = VALIST.__skip ) ) addr = VALIST.__skip + STACK_POINTER_OFFSET ; else addr = VALIST.__args ; VALIST.__args = addr + paddedsize ; ret = * ( TYPE * ) addr ;


<s> bool MSP430FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MSP430MachineFunctionInfo * MFI = MF . getInfo < MSP430MachineFunctionInfo > ( ) ; MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( MSP430 :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static void register_svpattern ( ) { auto_vec < string_int_pair , 32 > values ; values . quick_push ( string_int_pair ( "SV_" # UPPER , VALUE ) ) ; AARCH64_FOR_SVPATTERN ( PUSH ) acle_svpattern = lang_hooks . types . simulate_enum_decl ( input_location , "svpattern" , & values ) ; } </s>


"Unable to build a return instruction?!"

"The insertion did not happen where we expected"

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s>
static
const
char
*
avr_out_movqi_r_mr_reg_disp_tiny
(
rtx_insn
*
insn
,
rtx
op
[
]
,
int
*
plen
)
{
rtx
dest
=
op
[
0
]
;
rtx
src
=
op
[
1
]
;
rtx
x
=
XEXP
(
src
,
0
)
;
avr_asm_len
(
TINY_ADIW
(
%
I1
,
%
J1
,
%
o1
)
CR_TAB
"ld %0,%b1"
,
op
,
plen
,
3
)
;
if
(
!
reg_overlap_mentioned_p
(
dest
,
XEXP
(
x
,
0
)
)
&&
!
reg_unused_after
(
insn
,
XEXP
(
x
,
0
)
)
)
avr_asm_len
(
TINY_SBIW
(
%
I1
,
%
J1
,
%
o1
)
,
op
,
plen
,
2
)
;
return
""
;
}
</s>

Same as out_movqi_r_mr , but TINY does not have ADIW or SBIW


<s> int bfin_frame_pointer_required ( void ) { e_funkind fkind = funkind ( TREE_TYPE ( current_function_decl ) ) ; if ( fkind != SUBROUTINE ) return 1 ; if ( TARGET_OMIT_LEAF_FRAME_POINTER && ! current_function_is_leaf ) return 1 ; return 0 ; } </s>

Value should be nonzero if functions must have frame pointers . Zero means the frame pointer need not be set up ( and parms may be accessed via the stack pointer ) in functions that seem suitable .


<s> static void cris_file_start ( void ) { targetm . asm_file_start_app_off = ! ( TARGET_PDEBUG || flag_print_asm_name ) ; default_file_start ( ) ; } </s>

Boilerplate emitted at start of file . NO_APP * only at file start * means faster assembly . It also means comments are not allowed . In some cases comments will be output for debugging purposes . Make sure they are allowed then . We want a .file directive only if TARGET_ELF .


<s> static const char * output_multi_immediate ( rtx * operands , const char * instr1 , const char * instr2 , int immed_op , HOST_WIDE_INT n ) { n &= 0xffffffff ; if ( n == 0 ) { operands [ immed_op ] = const0_rtx ; output_asm_insn ( instr1 , operands ) ; } else { int i ; const char * instr = instr1 ; for ( i = 0 ; i < 32 ; i += 2 ) { if ( n & ( 3 << i ) ) { operands [ immed_op ] = GEN_INT ( n & ( 255 << i ) ) ; output_asm_insn ( instr , operands ) ; instr = instr2 ; i += 6 ; } } } return "" ; } </s>

Output a multiple immediate operation . OPERANDS is the vector of operands referred to in the output patterns . INSTR1 is the output pattern to use for the first constant . INSTR2 is the output pattern to use for subsequent constants . IMMED_OP is the index of the constant slot in OPERANDS . N is the constant value .


<s>
void
GBZ80InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
GBZ80
::
GR8RegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
GBZ80
::
LD8rr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
return
;
}
else
if
(
GBZ80
::
GR16RegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
unsigned
DestSubReg
,
SrcSubReg
;
DestSubReg
=
RI
.
getSubReg
(
DestReg
,
GBZ80
::
subreg_hi
)
;
SrcSubReg
=
RI
.
getSubReg
(
SrcReg
,
GBZ80
::
subreg_hi
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
GBZ80
::
LD8rr
)
,
DestSubReg
)
.
addReg
(
SrcSubReg
)
;
DestSubReg
=
RI
.
getSubReg
(
DestReg
,
GBZ80
::
subreg_lo
)
;
SrcSubReg
=
RI
.
getSubReg
(
SrcReg
,
GBZ80
::
subreg_lo
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
GBZ80
::
LD8rr
)
,
DestSubReg
)
.
addReg
(
SrcSubReg
)
;
if
(
KillSrc
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
GBZ80
::
KILL
)
)
.
addReg
(
SrcReg
)
;
return
;
}
else
if
(
GBZ80
::
GR16RegClass
.
contains
(
DestReg
)
||
GBZ80
::
GR16RegClass
.
contains
(
SrcReg
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
GBZ80
::
PUSH16r
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
GBZ80
::
POP16r
)
,
DestReg
)
;
return
;
}
llvm_unreachable
(
"Imposible reg-to-reg copy"
)
;
}
</s>


<s> int m32c_class_likely_spilled_p ( int regclass ) { if ( regclass == A_REGS ) return 1 ; return reg_class_size [ regclass ] == 1 ; } </s>

Implements CLASS_LIKELY_SPILLED_P . A_REGS is needed for address reloads .


<s> static void vector_init_fpmerge ( rtx target , rtx elt ) { rtx t1 , t2 , t2_low , t3 , t3_low ; t1 = gen_reg_rtx ( V4QImode ) ; elt = convert_modes ( SImode , QImode , elt , true ) ; emit_move_insn ( gen_lowpart ( SImode , t1 ) , elt ) ; t2 = gen_reg_rtx ( V8QImode ) ; t2_low = gen_lowpart ( V4QImode , t2 ) ; emit_insn ( gen_fpmerge_vis ( t2 , t1 , t1 ) ) ; t3 = gen_reg_rtx ( V8QImode ) ; t3_low = gen_lowpart ( V4QImode , t3 ) ; emit_insn ( gen_fpmerge_vis ( t3 , t2_low , t2_low ) ) ; emit_insn ( gen_fpmerge_vis ( target , t3_low , t3_low ) ) ; } </s>

Subroutine of sparc_expand_vector_init . Emit code to initialize all fields of TARGET to ELT in V8QI by means of VIS FPMERGE insn .


"Only register-returns should be created by PCS"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s>
bool
VLIWResourceModel
::
reserveResources
(
SUnit
*
SU
)
{
bool
startNewCycle
=
false
;
if
(
!
SU
)
{
ResourcesModel
->
clearResources
(
)
;
Packet
.
clear
(
)
;
TotalPackets
++
;
return
false
;
}
if
(
!
isResourceAvailable
(
SU
)
)
{
ResourcesModel
->
clearResources
(
)
;
Packet
.
clear
(
)
;
TotalPackets
++
;
startNewCycle
=
true
;
}
switch
(
SU
->
getInstr
(
)
->
getOpcode
(
)
)
{
default
:
ResourcesModel
->
reserveResources
(
*
SU
->
getInstr
(
)
)
;
break
;
case
TargetOpcode
::
EXTRACT_SUBREG
:
case
TargetOpcode
::
INSERT_SUBREG
:
case
TargetOpcode
::
SUBREG_TO_REG
:
case
TargetOpcode
::
REG_SEQUENCE
:
case
TargetOpcode
::
IMPLICIT_DEF
:
case
TargetOpcode
::
KILL
:
case
TargetOpcode
::
CFI_INSTRUCTION
:
case
TargetOpcode
::
EH_LABEL
:
case
TargetOpcode
::
COPY
:
case
TargetOpcode
::
INLINEASM
:
break
;
}
Packet
.
push_back
(
SU
)
;
DEBUG
(
dbgs
(
)
<<
"Packet["
<<
TotalPackets
<<
"]:\n"
)
;
for
(
unsigned
i
=
0
,
e
=
Packet
.
size
(
)
;
i
!=
e
;
++
i
)
{
DEBUG
(
dbgs
(
)
<<
"\t["
<<
i
<<
"] SU("
)
;
DEBUG
(
dbgs
(
)
<<
Packet
[
i
]
->
NodeNum
<<
")\t"
)
;
DEBUG
(
Packet
[
i
]
->
getInstr
(
)
->
dump
(
)
)
;
}
if
(
Packet
.
size
(
)
>=
SchedModel
->
getIssueWidth
(
)
)
{
ResourcesModel
->
clearResources
(
)
;
Packet
.
clear
(
)
;
TotalPackets
++
;
startNewCycle
=
true
;
}
return
startNewCycle
;
}
</s>


<s> const uint16_t * X86RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { bool callsEHReturn = false ; bool ghcCall = false ; if ( MF ) { callsEHReturn = MF -> getMMI ( ) . callsEHReturn ( ) ; const Function * F = MF -> getFunction ( ) ; ghcCall = ( F ? F -> getCallingConv ( ) == CallingConv :: GHC : false ) ; } if ( ghcCall ) return CSR_Ghc_SaveList ; if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_SaveList ; if ( callsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; } if ( callsEHReturn ) return CSR_32EHRet_SaveList ; return CSR_32_SaveList ; } </s>


<s> void print_address_operand ( FILE * file , rtx x ) { switch ( GET_CODE ( x ) ) { case PLUS : output_address ( XEXP ( x , 0 ) ) ; fprintf ( file , "+" ) ; output_address ( XEXP ( x , 1 ) ) ; break ; case PRE_DEC : fprintf ( file , "--" ) ; output_address ( XEXP ( x , 0 ) ) ; break ; case POST_INC : output_address ( XEXP ( x , 0 ) ) ; fprintf ( file , "++" ) ; break ; case POST_DEC : output_address ( XEXP ( x , 0 ) ) ; fprintf ( file , "--" ) ; break ; default : gcc_assert ( GET_CODE ( x ) != MEM ) ; print_operand ( file , x , 0 ) ; break ; } } </s>

Subroutine of print_operand ; used to print a memory reference X to FILE .


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCRelaxableFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
{
assert
(
0
&&
"RelaxInstruction() unimplemented"
)
;
return
false
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static rtx cris_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( mode , CRIS_FIRST_ARG_REG ) ; } </s>

Let 's assume all functions return in r [ CRIS_FIRST_ARG_REG ] for the time being .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s>
LLVM_DUMP_METHOD
void
GCNRegPressure
::
print
(
raw_ostream
&
OS
,
const
GCNSubtarget
*
ST
)
const
{
OS
<<
"VGPRs: "
<<
Value
[
VGPR32
]
<<
' '
;
OS
<<
"AGPRs: "
<<
Value
[
AGPR32
]
;
if
(
ST
)
OS
<<
"(O"
<<
ST
->
getOccupancyWithNumVGPRs
(
getVGPRNum
(
ST
->
hasGFX90AInsts
(
)
)
)
<<
')'
;
OS
<<
", SGPRs: "
<<
getSGPRNum
(
)
;
if
(
ST
)
OS
<<
"(O"
<<
ST
->
getOccupancyWithNumSGPRs
(
getSGPRNum
(
)
)
<<
')'
;
OS
<<
", LVGPR WT: "
<<
getVGPRTuplesWeight
(
)
<<
", LSGPR WT: "
<<
getSGPRTuplesWeight
(
)
;
if
(
ST
)
OS
<<
" -> Occ: "
<<
getOccupancy
(
*
ST
)
;
OS
<<
'\n'
;
}
</s>

print - Print a debug representation of the operand to the given stream .

AMDGPU
"VGPRs: "
"AGPRs: "
"(O"
", SGPRs: "
"(O"
", LVGPR WT: "
", LSGPR WT: "
" -> Occ: "


<s> ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const override { return createR600MachineScheduler ( C ) ; } </s>

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level .


<s> static unsigned long arm_compute_save_core_reg_mask ( void ) { unsigned int save_reg_mask = 0 ; unsigned long func_type = arm_current_func_type ( ) ; unsigned int reg ; if ( IS_NAKED ( func_type ) ) return 0 ; if ( TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM ) save_reg_mask |= ( 1 << ARM_HARD_FRAME_POINTER_REGNUM ) | ( 1 << IP_REGNUM ) | ( 1 << LR_REGNUM ) | ( 1 << PC_REGNUM ) ; save_reg_mask |= arm_compute_save_reg0_reg12_mask ( ) ; if ( arm_current_function_pac_enabled_p ( ) ) save_reg_mask |= 1 << IP_REGNUM ; if ( df_regs_ever_live_p ( LR_REGNUM ) || ( save_reg_mask && optimize_size && ARM_FUNC_TYPE ( func_type ) == ARM_FT_NORMAL && ! crtl -> tail_call_emit && ! crtl -> calls_eh_return ) ) save_reg_mask |= 1 << LR_REGNUM ; if ( cfun -> machine -> lr_save_eliminated ) save_reg_mask &= ~ ( 1 << LR_REGNUM ) ; if ( TARGET_REALLY_IWMMXT && ( ( bit_count ( save_reg_mask ) + ARM_NUM_INTS ( crtl -> args . pretend_args_size + arm_compute_static_chain_stack_bytes ( ) ) ) % 2 ) != 0 ) { for ( reg = 4 ; reg <= 12 ; reg ++ ) if ( ( save_reg_mask & ( 1 << reg ) ) == 0 ) break ; if ( reg <= 12 ) save_reg_mask |= ( 1 << reg ) ; else { cfun -> machine -> sibcall_blocked = 1 ; save_reg_mask |= ( 1 << 3 ) ; } } if ( TARGET_THUMB2 && IS_NESTED ( func_type ) && flag_pic && ( save_reg_mask & THUMB2_WORK_REGS ) == 0 ) { reg = thumb_find_work_register ( 1 << 4 ) ; if ( ! call_used_or_fixed_reg_p ( reg ) ) save_reg_mask |= ( 1 << reg ) ; } return save_reg_mask ; } </s>

Compute a bit mask of which core registers need to be saved on the stack for the current function . This is used by arm_compute_frame_layout , which may add extra registers .


<s> EVT MipsTargetLowering :: getSetCCResultType ( const DataLayout & , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s>
bool
AMDGPUMachineCFGStructurizer
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
const
GCNSubtarget
&
ST
=
MF
.
getSubtarget
<
GCNSubtarget
>
(
)
;
const
SIInstrInfo
*
TII
=
ST
.
getInstrInfo
(
)
;
TRI
=
ST
.
getRegisterInfo
(
)
;
MRI
=
&
(
MF
.
getRegInfo
(
)
)
;
initFallthroughMap
(
MF
)
;
checkRegOnlyPHIInputs
(
MF
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"----STRUCTURIZER START----\n"
)
;
LLVM_DEBUG
(
MF
.
dump
(
)
)
;
Regions
=
&
(
getAnalysis
<
MachineRegionInfoPass
>
(
)
.
getRegionInfo
(
)
)
;
LLVM_DEBUG
(
Regions
->
dump
(
)
)
;
RegionMRT
*
RTree
=
MRT
::
buildMRT
(
MF
,
Regions
,
TII
,
MRI
)
;
setRegionMRT
(
RTree
)
;
initializeSelectRegisters
(
RTree
,
0
,
MRI
,
TII
)
;
LLVM_DEBUG
(
RTree
->
dump
(
TRI
)
)
;
bool
result
=
structurizeRegions
(
RTree
,
true
)
;
delete
RTree
;
LLVM_DEBUG
(
dbgs
(
)
<<
"----STRUCTURIZER END----\n"
)
;
initFallthroughMap
(
MF
)
;
return
result
;
}
</s>

runOnMachineFunction - Emit the function body .

AMDGPU
AMDGPU
SI
"----STRUCTURIZER START----\n"
0
"----STRUCTURIZER END----\n"


<s>
void
Cpu0InstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineMemOperand
*
MMO
=
GetMemOperand
(
MBB
,
FI
,
MachineMemOperand
::
MOLoad
)
;
unsigned
Opc
=
0
;
if
(
Cpu0
::
CPURegsRegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
Cpu0
::
LD
;
assert
(
Opc
&&
"Register class not handled!"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s>
bool
MSP430AsmParser
::
MatchAndEmitInstruction
(
SMLoc
Loc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MatchingInlineAsm
)
;
switch
(
MatchResult
)
{
case
Match_Success
:
Inst
.
setLoc
(
Loc
)
;
Out
.
EmitInstruction
(
Inst
,
STI
)
;
return
false
;
case
Match_MnemonicFail
:
return
Error
(
Loc
,
"invalid instruction mnemonic"
)
;
case
Match_InvalidOperand
:
{
SMLoc
ErrorLoc
=
Loc
;
if
(
ErrorInfo
!=
~
0U
)
{
if
(
ErrorInfo
>=
Operands
.
size
(
)
)
return
Error
(
ErrorLoc
,
"too few operands for instruction"
)
;
ErrorLoc
=
(
(
MSP430Operand
&
)
*
Operands
[
ErrorInfo
]
)
.
getStartLoc
(
)
;
if
(
ErrorLoc
==
SMLoc
(
)
)
ErrorLoc
=
Loc
;
}
return
Error
(
ErrorLoc
,
"invalid operand for instruction"
)
;
}
default
:
return
true
;
}
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> void X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const X86Subtarget & STI = MF . getSubtarget < X86Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; const X86RegisterInfo & RegInfo = * STI . getRegisterInfo ( ) ; unsigned StackPtr = RegInfo . getStackRegister ( ) ; bool reserveCallFrame = hasReservedCallFrame ( MF ) ; unsigned Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; bool IsLP64 = STI . isTarget64BitLP64 ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t InternalAmt = ( isDestroy || Amount ) ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { if ( Amount == 0 ) return ; unsigned StackAlign = getStackAlignment ( ) ; Amount = RoundUpToAlignment ( Amount , StackAlign ) ; MachineInstr * New = nullptr ; Amount -= InternalAmt ; if ( Amount ) { if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( IsLP64 , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; unsigned Opc = getADDriOpcode ( IsLP64 , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } return ; } if ( Opcode == TII . getCallFrameDestroyOpcode ( ) && InternalAmt ) { unsigned Opc = getSUBriOpcode ( IsLP64 , InternalAmt ) ; MachineInstr * New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( InternalAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! std :: prev ( I ) -> isCall ( ) ) -- I ; MBB . insert ( I , New ) ; } } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> void AArch64PassConfig :: addPreRegBankSelect ( ) { bool IsOptNone = getOptLevel ( ) == CodeGenOpt :: None ; if ( ! IsOptNone ) addPass ( createAArch64PostLegalizerCombiner ( IsOptNone ) ) ; addPass ( createAArch64PostLegalizerLowering ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before the register bank selection .


<s> const TargetRegisterClass * MipsSERegisterInfo :: intRegClass ( unsigned Size ) const { if ( Size == 4 ) return & Mips :: CPURegsRegClass ; assert ( Size == 8 ) ; return & Mips :: CPU64RegsRegClass ; } </s>


<s>
bool
AVRFrameLowering
::
spillCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
ArrayRef
<
CalleeSavedInfo
>
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
if
(
CSI
.
empty
(
)
)
{
return
false
;
}
unsigned
CalleeFrameSize
=
0
;
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
AVRSubtarget
&
STI
=
MF
.
getSubtarget
<
AVRSubtarget
>
(
)
;
const
TargetInstrInfo
&
TII
=
*
STI
.
getInstrInfo
(
)
;
AVRMachineFunctionInfo
*
AVRFI
=
MF
.
getInfo
<
AVRMachineFunctionInfo
>
(
)
;
for
(
const
CalleeSavedInfo
&
I
:
llvm
::
reverse
(
CSI
)
)
{
unsigned
Reg
=
I
.
getReg
(
)
;
bool
IsNotLiveIn
=
!
MBB
.
isLiveIn
(
Reg
)
;
assert
(
TRI
->
getRegSizeInBits
(
*
TRI
->
getMinimalPhysRegClass
(
Reg
)
)
==
8
&&
"Invalid register size"
)
;
if
(
IsNotLiveIn
)
{
MBB
.
addLiveIn
(
Reg
)
;
}
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
PUSHRr
)
)
.
addReg
(
Reg
,
getKillRegState
(
IsNotLiveIn
)
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
++
CalleeFrameSize
;
}
AVRFI
->
setCalleeSavedFrameSize
(
CalleeFrameSize
)
;
return
true
;
}
</s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .

AVR
AVR
0
AVR
AVR
AVR
AVR
AVR
8
"Invalid register size"
AVR::PUSHRr
AVR


<s> static machine_mode rs6000_secondary_memory_needed_mode ( machine_mode mode ) { if ( lra_in_progress && mode == SDmode ) return DDmode ; return mode ; } </s>

Return the mode to be used for memory when a secondary memory location is needed . For SDmode values we need to use DDmode , in all other cases we can use the same mode .


<s> int arc_initial_elimination_offset ( int from , int to ) { if ( ! cfun -> machine -> frame_info . initialized ) arc_compute_frame_size ( ) ; if ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) { return ( cfun -> machine -> frame_info . extra_size + cfun -> machine -> frame_info . reg_size ) ; } if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) { return ( cfun -> machine -> frame_info . total_size - cfun -> machine -> frame_info . pretend_size ) ; } if ( ( from == FRAME_POINTER_REGNUM ) && ( to == STACK_POINTER_REGNUM ) ) { return ( cfun -> machine -> frame_info . total_size - ( cfun -> machine -> frame_info . pretend_size + cfun -> machine -> frame_info . extra_size + cfun -> machine -> frame_info . reg_size ) ) ; } if ( ( from == FRAME_POINTER_REGNUM ) && ( to == HARD_FRAME_POINTER_REGNUM ) ) return 0 ; gcc_unreachable ( ) ; } </s>

Define the offset between two registers , one to be eliminated , and the other its replacement , at the start of a routine .


<s> bool runOnModule ( Module & M ) override { return lowerIntrinsics ( M ) ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s>
const
char
*
thumb_load_double_from_address
(
rtx
*
operands
)
{
rtx
addr
;
rtx
base
;
rtx
offset
;
rtx
arg1
;
rtx
arg2
;
gcc_assert
(
GET_CODE
(
operands
[
0
]
)
==
REG
)
;
gcc_assert
(
GET_CODE
(
operands
[
1
]
)
==
MEM
)
;
addr
=
XEXP
(
operands
[
1
]
,
0
)
;
switch
(
GET_CODE
(
addr
)
)
{
case
REG
:
operands
[
2
]
=
adjust_address
(
operands
[
1
]
,
SImode
,
4
)
;
if
(
REGNO
(
operands
[
0
]
)
==
REGNO
(
addr
)
)
{
output_asm_insn
(
"ldr\t%H0, %2"
,
operands
)
;
output_asm_insn
(
"ldr\t%0, %1"
,
operands
)
;
}
else
{
output_asm_insn
(
"ldr\t%0, %1"
,
operands
)
;
output_asm_insn
(
"ldr\t%H0, %2"
,
operands
)
;
}
break
;
case
CONST
:
operands
[
2
]
=
adjust_address
(
operands
[
1
]
,
SImode
,
4
)
;
output_asm_insn
(
"ldr\t%0, %1"
,
operands
)
;
output_asm_insn
(
"ldr\t%H0, %2"
,
operands
)
;
break
;
case
PLUS
:
arg1
=
XEXP
(
addr
,
0
)
;
arg2
=
XEXP
(
addr
,
1
)
;
if
(
CONSTANT_P
(
arg1
)
)
base
=
arg2
,
offset
=
arg1
;
else
base
=
arg1
,
offset
=
arg2
;
gcc_assert
(
GET_CODE
(
base
)
==
REG
)
;
if
(
GET_CODE
(
offset
)
==
REG
)
{
int
reg_offset
=
REGNO
(
offset
)
;
int
reg_base
=
REGNO
(
base
)
;
int
reg_dest
=
REGNO
(
operands
[
0
]
)
;
asm_fprintf
(
asm_out_file
,
"\tadd\t%r, %r, %r"
,
reg_dest
+
1
,
reg_base
,
reg_offset
)
;
asm_fprintf
(
asm_out_file
,
"\tldr\t%r, [%r, #0]"
,
reg_dest
,
reg_dest
+
1
)
;
asm_fprintf
(
asm_out_file
,
"\tldr\t%r, [%r, #4]"
,
reg_dest
+
1
,
reg_dest
+
1
)
;
}
else
{
operands
[
2
]
=
adjust_address
(
operands
[
1
]
,
SImode
,
4
)
;
if
(
REGNO
(
operands
[
0
]
)
==
REGNO
(
base
)
)
{
output_asm_insn
(
"ldr\t%H0, %2"
,
operands
)
;
output_asm_insn
(
"ldr\t%0, %1"
,
operands
)
;
}
else
{
output_asm_insn
(
"ldr\t%0, %1"
,
operands
)
;
output_asm_insn
(
"ldr\t%H0, %2"
,
operands
)
;
}
}
break
;
case
LABEL_REF
:
operands
[
2
]
=
adjust_address
(
operands
[
1
]
,
SImode
,
4
)
;
output_asm_insn
(
"ldr\t%H0, %2"
,
operands
)
;
output_asm_insn
(
"ldr\t%0, %1"
,
operands
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
return
""
;
}
</s>

Handle the case of a double word load into a low register from a computed memory address . The computed address may involve a register which is overwritten by the load .


<s> static bool isBranch ( unsigned Opcode ) { return Opcode == AMDGPU :: BRANCH || Opcode == AMDGPU :: BRANCH_COND_i32 || Opcode == AMDGPU :: BRANCH_COND_f32 ; } </s>

Returns true if this is a conditional , unconditional , or indirect branch .


<s>
void
Finish
(
)
{
const
size_t
VendorHeaderSize
=
4
+
CurrentVendor
.
size
(
)
+
1
;
const
size_t
TagHeaderSize
=
1
+
4
;
Streamer
.
EmitIntValue
(
VendorHeaderSize
+
TagHeaderSize
+
ContentsSize
,
4
)
;
Streamer
.
EmitBytes
(
CurrentVendor
,
0
)
;
Streamer
.
EmitIntValue
(
0
,
1
)
;
Streamer
.
EmitIntValue
(
ARMBuildAttrs
::
File
,
1
)
;
Streamer
.
EmitIntValue
(
TagHeaderSize
+
ContentsSize
,
4
)
;
for
(
unsigned
int
i
=
0
;
i
<
Contents
.
size
(
)
;
++
i
)
{
AttributeItemType
item
=
Contents
[
i
]
;
Streamer
.
EmitULEB128IntValue
(
item
.
Tag
,
0
)
;
switch
(
item
.
Type
)
{
default
:
llvm_unreachable
(
"Invalid attribute type"
)
;
case
AttributeItemType
::
NumericAttribute
:
Streamer
.
EmitULEB128IntValue
(
item
.
IntValue
,
0
)
;
break
;
case
AttributeItemType
::
TextAttribute
:
Streamer
.
EmitBytes
(
item
.
StringValue
.
upper
(
)
,
0
)
;
Streamer
.
EmitIntValue
(
0
,
1
)
;
break
;
}
}
Contents
.
clear
(
)
;
}
</s>

Finish - Do final processing and write the object to the output stream .


<s> bool PPCTargetLowering :: IsEligibleForTailCallOptimization ( SDValue Callee , unsigned CalleeCC , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SelectionDAG & DAG ) const { if ( isVarArg ) return false ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned CallerCC = MF . getFunction ( ) -> getCallingConv ( ) ; if ( CalleeCC == CallingConv :: Fast && CallerCC == CalleeCC ) { for ( unsigned i = 0 ; i != Ins . size ( ) ; i ++ ) { ISD :: ArgFlagsTy Flags = Ins [ i ] . Flags ; if ( Flags . isByVal ( ) ) return false ; } if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) return true ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) return G -> getGlobal ( ) -> hasHiddenVisibility ( ) || G -> getGlobal ( ) -> hasProtectedVisibility ( ) ; } return false ; } </s>

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization .

PowerPC PPC ISD::InputArg 0 ISD::ArgFlagsTy


<s> const uint16_t * rvexRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_O32_SaveList ; } </s>


<s> FISCTargetLowering :: ConstraintType FISCTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'c' : return C_RegisterClass ; case 'R' : return C_Memory ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s>
SDValue
LanaiTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
DL
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
switch
(
CallConv
)
{
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
IsVarArg
,
Ins
,
DL
,
DAG
,
InVals
)
;
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .

Lanai
Lanai
ISD::InputArg
"Unsupported calling convention"


<s> static bool ix86_pass_by_reference ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) { HOST_WIDE_INT msize = GET_MODE_SIZE ( mode ) ; if ( type ) { if ( TREE_CODE ( type ) == ARRAY_TYPE ) return true ; if ( RECORD_OR_UNION_TYPE_P ( type ) ) { msize = int_size_in_bytes ( type ) ; } } return msize != 1 && msize != 2 && msize != 4 && msize != 8 ; } else if ( type && int_size_in_bytes ( type ) == - 1 ) return true ; } return false ; } </s>

A C expression that indicates when an argument must be passed by reference . If nonzero for an argument , a copy of that argument is made in memory and a pointer to the argument is passed instead of the argument itself . The pointer is passed in whatever way is appropriate for passing a pointer to that type .


<s> void IncomingValueHandler :: assignValueToAddress ( Register ValVReg , const CCValAssign & VA ) { if ( VA . getLocInfo ( ) == CCValAssign :: SExt || VA . getLocInfo ( ) == CCValAssign :: ZExt || VA . getLocInfo ( ) == CCValAssign :: AExt ) { auto Load = buildLoad ( LLT :: scalar ( 32 ) , VA ) ; MIRBuilder . buildTrunc ( ValVReg , Load ) ; } else buildLoad ( ValVReg , VA ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> void th_mempair_order_operands ( rtx operands [ 4 ] , bool load_p , machine_mode mode ) { int mem_op = load_p ? 1 : 0 ; bool reversed = false ; if ( ! th_mempair_check_consecutive_mems ( mode , operands + mem_op , operands + mem_op + 2 , & reversed ) ) gcc_unreachable ( ) ; if ( reversed ) { std :: swap ( operands [ 0 ] , operands [ 2 ] ) ; std :: swap ( operands [ 1 ] , operands [ 3 ] ) ; } } </s>

Given OPERANDS of consecutive load/store that can be merged , swap them if they are not in ascending order . Return true if swap was performed .


<s> static bool mmix_pass_by_reference ( const CUMULATIVE_ARGS * argsp , enum machine_mode mode , tree type , bool named ATTRIBUTE_UNUSED ) { if ( targetm . calls . must_pass_in_stack ( mode , type ) ) return true ; if ( MMIX_FUNCTION_ARG_SIZE ( mode , type ) > 8 && ! TARGET_LIBFUNC && ( ! argsp || ! argsp -> lib ) ) return true ; return false ; } </s>

Returns nonzero for everything that goes by reference , 0 for everything that goes by value .


<s> static void gen_int_relational ( enum rtx_code code , rtx result , rtx cmp0 , rtx cmp1 , rtx destination ) { machine_mode mode ; int branch_p ; mode = GET_MODE ( cmp0 ) ; if ( mode == VOIDmode ) mode = GET_MODE ( cmp1 ) ; branch_p = ( destination != 0 ) ; switch ( code ) { case LE : case LT : case LEU : case LTU : { rtx temp ; code = swap_condition ( code ) ; temp = cmp0 ; cmp0 = cmp1 ; cmp1 = temp ; break ; } default : break ; } if ( branch_p ) { rtx insn , cond , label ; if ( ! register_operand ( cmp0 , mode ) ) cmp0 = force_reg ( mode , cmp0 ) ; if ( ! register_operand ( cmp1 , mode ) ) cmp1 = force_reg ( mode , cmp1 ) ; cond = gen_rtx_fmt_ee ( code , mode , cmp0 , cmp1 ) ; label = gen_rtx_LABEL_REF ( VOIDmode , destination ) ; insn = gen_rtx_SET ( pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , cond , label , pc_rtx ) ) ; emit_jump_insn ( insn ) ; } else { if ( ( GET_CODE ( cmp0 ) == CONST_INT ) && ( INTVAL ( cmp0 ) != 0 ) ) cmp0 = force_reg ( mode , cmp0 ) ; if ( GET_CODE ( cmp1 ) == CONST_INT ) { switch ( code ) { case EQ : case NE : case LE : case LT : case GE : case GT : if ( ! satisfies_constraint_K ( cmp1 ) ) cmp1 = force_reg ( mode , cmp1 ) ; break ; case LEU : case LTU : case GEU : case GTU : if ( ! satisfies_constraint_L ( cmp1 ) ) cmp1 = force_reg ( mode , cmp1 ) ; break ; default : gcc_unreachable ( ) ; } } emit_move_insn ( result , gen_rtx_fmt_ee ( code , mode , cmp0 , cmp1 ) ) ; } } </s>

Generate the code to compare two integer values . The return value is the comparison expression .


<s> bool VEInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return false ; if ( ! isUnpredicatedTerminator ( * I ) ) return false ; MachineInstr * LastInst = & * I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { if ( isUncondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } if ( isCondBranchOpcode ( LastOpc ) ) { parseCondBranch ( LastInst , TBB , Cond ) ; return false ; } return true ; } MachineInstr * SecondLastInst = & * I ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; if ( AllowModify && isUncondBranchOpcode ( LastOpc ) ) { while ( isUncondBranchOpcode ( SecondLastOpc ) ) { LastInst -> eraseFromParent ( ) ; LastInst = SecondLastInst ; LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { TBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } SecondLastInst = & * I ; SecondLastOpc = SecondLastInst -> getOpcode ( ) ; } } if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( * -- I ) ) return true ; if ( isCondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { parseCondBranch ( SecondLastInst , TBB , Cond ) ; FBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } if ( isUncondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { TBB = SecondLastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } return true ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


Decide whether to use the unrolling heuristic described above aarch64_vector_costs : :unrolled_advsimd_niters , updating that field if so . LOOP_VINFO describes the loop that we 're vectorizing and COSTS are the costs that we 're calculating for it .


<s> static rtx mips_cprestore_slot ( rtx temp , bool load_p ) { rtx base ; HOST_WIDE_INT offset ; mips_get_cprestore_base_and_offset ( & base , & offset , load_p ) ; return gen_frame_mem ( Pmode , mips_add_offset ( temp , base , offset ) ) ; } </s>

Return a MEM rtx for the cprestore slot . LOAD_P is true if we are going to load from it , false if we are going to store to it . Use TEMP as a temporary register if need be .


"type %qT with %<[[no_unique_address]]%> members "

"type %qT when C++17 is enabled changed to match "

"argument of type %qT not permitted with %<-mgeneral-regs-only%>"

Return true if an argument whose type is TYPE , or mode is MODE , is suitable for passing or returning in VFP registers for the PCS variant selected . If it is , then * BASE_MODE is updated to contain a machine mode describing each element of the argument 's type and * COUNT to hold the number of such elements .


<s> MachineInstr * X86InstrInfo :: optimizeLoadInstr ( MachineInstr * MI , const MachineRegisterInfo * MRI , unsigned & FoldAsLoadDefReg , MachineInstr * & DefMI ) const { if ( FoldAsLoadDefReg == 0 ) return nullptr ; if ( MI -> mayLoad ( ) ) { FoldAsLoadDefReg = 0 ; return nullptr ; } DefMI = MRI -> getVRegDef ( FoldAsLoadDefReg ) ; assert ( DefMI ) ; bool SawStore = false ; if ( ! DefMI -> isSafeToMove ( this , nullptr , SawStore ) ) return nullptr ; unsigned SrcOperandId = 0 ; bool FoundSrcOperand = false ; for ( unsigned i = 0 , e = MI -> getDesc ( ) . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg != FoldAsLoadDefReg ) continue ; if ( MO . getSubReg ( ) || MO . isDef ( ) || FoundSrcOperand ) return nullptr ; SrcOperandId = i ; FoundSrcOperand = true ; } if ( ! FoundSrcOperand ) return nullptr ; SmallVector < unsigned , 8 > Ops ; Ops . push_back ( SrcOperandId ) ; MachineInstr * FoldMI = foldMemoryOperand ( MI , Ops , DefMI ) ; if ( FoldMI ) { FoldAsLoadDefReg = 0 ; return FoldMI ; } return nullptr ; } </s>

optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use .


<s> bool ARMPassConfig :: addPreISel ( ) { if ( ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE ) { bool OnlyOptimizeForSize = ( TM -> getOptLevel ( ) < CodeGenOpt :: Aggressive ) && ( EnableGlobalMerge == cl :: BOU_UNSET ) ; bool MergeExternalByDefault = ! TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ; addPass ( createGlobalMergePass ( TM , 127 , OnlyOptimizeForSize , MergeExternalByDefault ) ) ; } return false ; } </s>


"Invalid number of NOP bytes requested!"

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> static void init_float128_ibm ( machine_mode mode ) { if ( ! TARGET_XL_COMPAT ) { set_optab_libfunc ( add_optab , mode , "__gcc_qadd" ) ; set_optab_libfunc ( sub_optab , mode , "__gcc_qsub" ) ; set_optab_libfunc ( smul_optab , mode , "__gcc_qmul" ) ; set_optab_libfunc ( sdiv_optab , mode , "__gcc_qdiv" ) ; if ( ! TARGET_HARD_FLOAT ) { set_optab_libfunc ( neg_optab , mode , "__gcc_qneg" ) ; set_optab_libfunc ( eq_optab , mode , "__gcc_qeq" ) ; set_optab_libfunc ( ne_optab , mode , "__gcc_qne" ) ; set_optab_libfunc ( gt_optab , mode , "__gcc_qgt" ) ; set_optab_libfunc ( ge_optab , mode , "__gcc_qge" ) ; set_optab_libfunc ( lt_optab , mode , "__gcc_qlt" ) ; set_optab_libfunc ( le_optab , mode , "__gcc_qle" ) ; set_optab_libfunc ( unord_optab , mode , "__gcc_qunord" ) ; set_conv_libfunc ( sext_optab , mode , SFmode , "__gcc_stoq" ) ; set_conv_libfunc ( sext_optab , mode , DFmode , "__gcc_dtoq" ) ; set_conv_libfunc ( trunc_optab , SFmode , mode , "__gcc_qtos" ) ; set_conv_libfunc ( trunc_optab , DFmode , mode , "__gcc_qtod" ) ; set_conv_libfunc ( sfix_optab , SImode , mode , "__gcc_qtoi" ) ; set_conv_libfunc ( ufix_optab , SImode , mode , "__gcc_qtou" ) ; set_conv_libfunc ( sfloat_optab , mode , SImode , "__gcc_itoq" ) ; set_conv_libfunc ( ufloat_optab , mode , SImode , "__gcc_utoq" ) ; } } else { set_optab_libfunc ( add_optab , mode , "_xlqadd" ) ; set_optab_libfunc ( sub_optab , mode , "_xlqsub" ) ; set_optab_libfunc ( smul_optab , mode , "_xlqmul" ) ; set_optab_libfunc ( sdiv_optab , mode , "_xlqdiv" ) ; } if ( mode == IFmode ) { set_conv_libfunc ( sext_optab , mode , SDmode , "__dpd_extendsdtf2" ) ; set_conv_libfunc ( sext_optab , mode , DDmode , "__dpd_extendddtf2" ) ; set_conv_libfunc ( trunc_optab , mode , TDmode , "__dpd_trunctftd2" ) ; set_conv_libfunc ( trunc_optab , SDmode , mode , "__dpd_trunctfsd2" ) ; set_conv_libfunc ( trunc_optab , DDmode , mode , "__dpd_trunctfdd2" ) ; set_conv_libfunc ( sext_optab , TDmode , mode , "__dpd_extendtdtf2" ) ; if ( TARGET_POWERPC64 ) { set_conv_libfunc ( sfix_optab , TImode , mode , "__fixtfti" ) ; set_conv_libfunc ( ufix_optab , TImode , mode , "__fixunstfti" ) ; set_conv_libfunc ( sfloat_optab , mode , TImode , "__floattitf" ) ; set_conv_libfunc ( ufloat_optab , mode , TImode , "__floatuntitf" ) ; } } } </s>

Set up AIX/Darwin/64-bit Linux quad floating point routines .


<s>
bool
X86AsmParser
::
ParseDirective
(
AsmToken
DirectiveID
)
{
MCAsmParser
&
Parser
=
getParser
(
)
;
StringRef
IDVal
=
DirectiveID
.
getIdentifier
(
)
;
if
(
IDVal
.
startswith
(
".code"
)
)
return
ParseDirectiveCode
(
IDVal
,
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
.
startswith
(
".att_syntax"
)
)
{
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.att_syntax noprefix' is not "
"supported: registers must have a "
"'%' prefix in .att_syntax"
)
;
}
getParser
(
)
.
setAssemblerDialect
(
0
)
;
return
false
;
}
else
if
(
IDVal
.
startswith
(
".intel_syntax"
)
)
{
getParser
(
)
.
setAssemblerDialect
(
1
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.intel_syntax prefix' is not "
"supported: registers must not have "
"a '%' prefix in .intel_syntax"
)
;
}
return
false
;
}
else
if
(
IDVal
==
".even"
)
return
parseDirectiveEven
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_proc"
)
return
parseDirectiveFPOProc
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_setframe"
)
return
parseDirectiveFPOSetFrame
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_pushreg"
)
return
parseDirectiveFPOPushReg
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_stackalloc"
)
return
parseDirectiveFPOStackAlloc
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_stackalign"
)
return
parseDirectiveFPOStackAlign
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_endprologue"
)
return
parseDirectiveFPOEndPrologue
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_endproc"
)
return
parseDirectiveFPOEndProc
(
DirectiveID
.
getLoc
(
)
)
;
return
true
;
}
</s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> static void emit_save_or_restore_regs ( int action ) { HOST_WIDE_INT offset ; rtx base ; offset = frame_base_offset - apparent_fsize ; if ( offset < - 4096 || offset + num_gfregs * 4 > 4095 ) { base = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( base , GEN_INT ( offset ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , base , gen_rtx_PLUS ( Pmode , frame_base_reg , base ) ) ) ; offset = 0 ; } else base = frame_base_reg ; offset = save_or_restore_regs ( 0 , 8 , base , offset , action ) ; save_or_restore_regs ( 32 , TARGET_V9 ? 96 : 64 , base , offset , action ) ; } </s>

Emit code to save call-saved registers .


<s> unsigned PPCRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { if ( ! Subtarget . isPPC64 ( ) ) return hasFP ( MF ) ? PPC :: R31 : PPC :: R1 ; else return hasFP ( MF ) ? PPC :: X31 : PPC :: X1 ; } </s>


<s>
void
WebAssemblyInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
auto
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
const
TargetRegisterClass
*
RC
=
TargetRegisterInfo
::
isVirtualRegister
(
DestReg
)
MRI
.
getRegClass
(
DestReg
)
:
MRI
.
getTargetRegisterInfo
(
)
->
getMinimalPhysRegClass
(
DestReg
)
;
unsigned
CopyOpcode
;
if
(
RC
==
&
WebAssembly
::
I32RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_I32
;
else
if
(
RC
==
&
WebAssembly
::
I64RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_I64
;
else
if
(
RC
==
&
WebAssembly
::
F32RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_F32
;
else
if
(
RC
==
&
WebAssembly
::
F64RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_F64
;
else
if
(
RC
==
&
WebAssembly
::
V128RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_V128
;
else
llvm_unreachable
(
"Unexpected register class"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
CopyOpcode
)
,
DestReg
)
.
addReg
(
SrcReg
,
KillSrc
RegState
::
Kill
:
0
)
;
}
</s>


<s>
MachineBasicBlock
*
RISCVTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
MBB
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
case
RISCV
::
SELECT_CC
:
case
RISCV
::
SELECT_CC64
:
case
RISCV
::
FSELECT_CC_F
:
case
RISCV
::
FSELECT_CC_D
:
return
emitSelectCC
(
MI
,
MBB
)
;
case
RISCV
::
CALL
:
case
RISCV
::
CALLREG
:
case
RISCV
::
CALL64
:
case
RISCV
::
CALLREG64
:
return
emitCALL
(
MI
,
MBB
)
;
default
:
llvm_unreachable
(
"Unexpected instr type to insert"
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s>
bool
HexagonExpandCondsets
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
*
MF
.
getFunction
(
)
)
)
return
false
;
HII
=
static_cast
<
const
HexagonInstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
LIS
=
&
getAnalysis
<
LiveIntervals
>
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
LocalImpDefs
.
clear
(
)
;
DEBUG
(
LIS
->
print
(
dbgs
(
)
<<
"Before expand-condsets\n"
,
MF
.
getFunction
(
)
->
getParent
(
)
)
)
;
bool
Changed
=
false
;
std
::
set
<
unsigned
>
SplitUpd
,
PredUpd
;
Changed
|=
coalesceSegments
(
MF
)
;
for
(
auto
&
B
:
MF
)
Changed
|=
splitInBlock
(
B
,
SplitUpd
)
;
updateLiveness
(
SplitUpd
,
true
,
true
,
false
)
;
for
(
auto
&
B
:
MF
)
Changed
|=
predicateInBlock
(
B
,
PredUpd
)
;
updateLiveness
(
PredUpd
,
true
,
true
,
true
)
;
std
::
set
<
unsigned
>
Diff
;
std
::
set_difference
(
SplitUpd
.
begin
(
)
,
SplitUpd
.
end
(
)
,
PredUpd
.
begin
(
)
,
PredUpd
.
end
(
)
,
std
::
inserter
(
Diff
,
Diff
.
begin
(
)
)
)
;
updateLiveness
(
Diff
,
false
,
false
,
true
)
;
for
(
auto
*
ImpD
:
LocalImpDefs
)
removeInstr
(
*
ImpD
)
;
DEBUG
(
{
if
(
Changed
)
LIS
->
print
(
dbgs
(
)
<<
"After expand-condsets\n"
,
MF
.
getFunction
(
)
->
getParent
(
)
)
;
}
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

Hexagon
Hexagon
Hexagon
"Before expand-condsets\n"
"After expand-condsets\n"


<s> unsigned ARMBaseInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case ARM :: LDRrs : case ARM :: t2LDRs : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isReg ( ) && MI . getOperand ( 3 ) . isImm ( ) && MI . getOperand ( 2 ) . getReg ( ) == 0 && MI . getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: LDRi12 : case ARM :: t2LDRi12 : case ARM :: tLDRspi : case ARM :: VLDRD : case ARM :: VLDRS : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VLD1q64 : case ARM :: VLD1d64TPseudo : case ARM :: VLD1d64QPseudo : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VLDMQIA : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> static rtx rs6000_emit_savres_rtx ( rs6000_stack_t * info , rtx frame_reg_rtx , int save_area_offset , int lr_offset , machine_mode reg_mode , int sel ) { int i ; int offset , start_reg , end_reg , n_regs , use_reg ; int reg_size = GET_MODE_SIZE ( reg_mode ) ; rtx sym ; rtvec p ; rtx par , insn ; offset = 0 ; start_reg = ( ( sel & SAVRES_REG ) == SAVRES_GPR ? info -> first_gp_reg_save : ( sel & SAVRES_REG ) == SAVRES_FPR ? info -> first_fp_reg_save : ( sel & SAVRES_REG ) == SAVRES_VR ? info -> first_altivec_reg_save : - 1 ) ; end_reg = ( ( sel & SAVRES_REG ) == SAVRES_GPR ? 32 : ( sel & SAVRES_REG ) == SAVRES_FPR ? 64 : ( sel & SAVRES_REG ) == SAVRES_VR ? LAST_ALTIVEC_REGNO + 1 : - 1 ) ; n_regs = end_reg - start_reg ; p = rtvec_alloc ( 3 + ( ( sel & SAVRES_LR ) ? 1 : 0 ) + ( ( sel & SAVRES_REG ) == SAVRES_VR ? 1 : 0 ) + n_regs ) ; if ( ! ( sel & SAVRES_SAVE ) && ( sel & SAVRES_LR ) ) RTVEC_ELT ( p , offset ++ ) = ret_rtx ; RTVEC_ELT ( p , offset ++ ) = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; sym = rs6000_savres_routine_sym ( info , sel ) ; RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , sym ) ; use_reg = ptr_regno_for_savres ( sel ) ; if ( ( sel & SAVRES_REG ) == SAVRES_VR ) { RTVEC_ELT ( p , offset ++ ) = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , use_reg ) ) ; RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , gen_rtx_REG ( Pmode , 0 ) ) ; } else RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , gen_rtx_REG ( Pmode , use_reg ) ) ; for ( i = 0 ; i < end_reg - start_reg ; i ++ ) RTVEC_ELT ( p , i + offset ) = gen_frame_set ( gen_rtx_REG ( reg_mode , start_reg + i ) , frame_reg_rtx , save_area_offset + reg_size * i , ( sel & SAVRES_SAVE ) != 0 ) ; if ( ( sel & SAVRES_SAVE ) && ( sel & SAVRES_LR ) ) RTVEC_ELT ( p , i + offset ) = gen_frame_store ( gen_rtx_REG ( Pmode , 0 ) , frame_reg_rtx , lr_offset ) ; par = gen_rtx_PARALLEL ( VOIDmode , p ) ; if ( ! ( sel & SAVRES_SAVE ) && ( sel & SAVRES_LR ) ) { insn = emit_jump_insn ( par ) ; JUMP_LABEL ( insn ) = ret_rtx ; } else insn = emit_insn ( par ) ; return insn ; } </s>

Construct a parallel rtx describing the effect of a call to an out-of-line register save/restore routine , and emit the insn or jump_insn as appropriate .


<s> static bool nds32_sp_base_or_plus_load_store_p ( rtx_insn * insn ) { rtx mem_src = NULL_RTX ; switch ( get_attr_type ( insn ) ) { case TYPE_LOAD : mem_src = SET_SRC ( PATTERN ( insn ) ) ; break ; case TYPE_STORE : mem_src = SET_DEST ( PATTERN ( insn ) ) ; break ; default : break ; } if ( mem_src != NULL_RTX ) { if ( ( GET_CODE ( mem_src ) == ZERO_EXTEND ) || ( GET_CODE ( mem_src ) == SIGN_EXTEND ) ) mem_src = XEXP ( mem_src , 0 ) ; if ( ( GET_CODE ( XEXP ( mem_src , 0 ) ) == PLUS ) ) mem_src = XEXP ( mem_src , 0 ) ; if ( REG_P ( XEXP ( mem_src , 0 ) ) && ( ( frame_pointer_needed && REGNO ( XEXP ( mem_src , 0 ) ) == FP_REGNUM ) || REGNO ( XEXP ( mem_src , 0 ) ) == SP_REGNUM ) ) return true ; } return false ; } </s>

Return true if insn is a sp/fp base or sp/fp plus load-store instruction .


<s> bool runOnFunction ( Function & F ) override { visit ( F ) ; return false ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool AArch64InstrInfo :: getMachineCombinerPatterns ( MachineInstr & Root , SmallVectorImpl < MachineCombinerPattern > & Patterns , bool DoRegPressureReduce ) const { if ( getMaddPatterns ( Root , Patterns ) ) return true ; if ( getFMULPatterns ( Root , Patterns ) ) return true ; if ( getFMAPatterns ( Root , Patterns ) ) return true ; return TargetInstrInfo :: getMachineCombinerPatterns ( Root , Patterns , DoRegPressureReduce ) ; } </s>

Return true when there is potentially a faster code sequence for an instruction chain ending in Root .


<s> void PPCPassConfig :: addMachineSSAOptimization ( ) { if ( EnableBranchCoalescing && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCBranchCoalescingPass ( ) ) ; TargetPassConfig :: addMachineSSAOptimization ( ) ; if ( TM -> getTargetTriple ( ) . getArch ( ) == Triple :: ppc64le && ! DisableVSXSwapRemoval ) addPass ( createPPCVSXSwapRemovalPass ( ) ) ; if ( ! DisableMIPeephole ) { addPass ( createPPCMIPeepholePass ( ) ) ; addPass ( & DeadMachineInstructionElimID ) ; } } </s>

Methods with trivial inline returns are convenient points in the common codegen pass pipeline where targets may insert passes .


<s> const char * HexagonTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( HexagonISD :: NodeType ) Opcode ) { case HexagonISD :: ALLOCA : return "HexagonISD::ALLOCA" ; case HexagonISD :: AT_GOT : return "HexagonISD::AT_GOT" ; case HexagonISD :: AT_PCREL : return "HexagonISD::AT_PCREL" ; case HexagonISD :: BARRIER : return "HexagonISD::BARRIER" ; case HexagonISD :: CALL : return "HexagonISD::CALL" ; case HexagonISD :: CALLnr : return "HexagonISD::CALLnr" ; case HexagonISD :: CALLR : return "HexagonISD::CALLR" ; case HexagonISD :: COMBINE : return "HexagonISD::COMBINE" ; case HexagonISD :: CONST32_GP : return "HexagonISD::CONST32_GP" ; case HexagonISD :: CONST32 : return "HexagonISD::CONST32" ; case HexagonISD :: CP : return "HexagonISD::CP" ; case HexagonISD :: DCFETCH : return "HexagonISD::DCFETCH" ; case HexagonISD :: EH_RETURN : return "HexagonISD::EH_RETURN" ; case HexagonISD :: TSTBIT : return "HexagonISD::TSTBIT" ; case HexagonISD :: EXTRACTU : return "HexagonISD::EXTRACTU" ; case HexagonISD :: INSERT : return "HexagonISD::INSERT" ; case HexagonISD :: JT : return "HexagonISD::JT" ; case HexagonISD :: RET_FLAG : return "HexagonISD::RET_FLAG" ; case HexagonISD :: TC_RETURN : return "HexagonISD::TC_RETURN" ; case HexagonISD :: VASL : return "HexagonISD::VASL" ; case HexagonISD :: VASR : return "HexagonISD::VASR" ; case HexagonISD :: VLSR : return "HexagonISD::VLSR" ; case HexagonISD :: VSPLAT : return "HexagonISD::VSPLAT" ; case HexagonISD :: VEXTRACTW : return "HexagonISD::VEXTRACTW" ; case HexagonISD :: VINSERTW0 : return "HexagonISD::VINSERTW0" ; case HexagonISD :: VROR : return "HexagonISD::VROR" ; case HexagonISD :: READCYCLE : return "HexagonISD::READCYCLE" ; case HexagonISD :: VZERO : return "HexagonISD::VZERO" ; case HexagonISD :: D2P : return "HexagonISD::D2P" ; case HexagonISD :: P2D : return "HexagonISD::P2D" ; case HexagonISD :: V2Q : return "HexagonISD::V2Q" ; case HexagonISD :: Q2V : return "HexagonISD::Q2V" ; case HexagonISD :: QCAT : return "HexagonISD::QCAT" ; case HexagonISD :: QTRUE : return "HexagonISD::QTRUE" ; case HexagonISD :: QFALSE : return "HexagonISD::QFALSE" ; case HexagonISD :: TYPECAST : return "HexagonISD::TYPECAST" ; case HexagonISD :: OP_END : break ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

Hexagon Hexagon HexagonISD::NodeType HexagonISD::ALLOCA "HexagonISD::ALLOCA" HexagonISD::AT_GOT "HexagonISD::AT_GOT" HexagonISD::AT_PCREL "HexagonISD::AT_PCREL" HexagonISD::BARRIER "HexagonISD::BARRIER" HexagonISD::CALL "HexagonISD::CALL" HexagonISD::CALLnr "HexagonISD::CALLnr" HexagonISD::CALLR "HexagonISD::CALLR" HexagonISD::COMBINE "HexagonISD::COMBINE" HexagonISD::CONST32_GP "HexagonISD::CONST32_GP" HexagonISD::CONST32 "HexagonISD::CONST32" HexagonISD::CP "HexagonISD::CP" HexagonISD::DCFETCH "HexagonISD::DCFETCH" HexagonISD::EH_RETURN "HexagonISD::EH_RETURN" HexagonISD::TSTBIT "HexagonISD::TSTBIT" HexagonISD::EXTRACTU "HexagonISD::EXTRACTU" HexagonISD::INSERT "HexagonISD::INSERT" HexagonISD::JT "HexagonISD::JT" HexagonISD::RET_FLAG "HexagonISD::RET_FLAG" HexagonISD::TC_RETURN "HexagonISD::TC_RETURN" HexagonISD::VASL "HexagonISD::VASL" HexagonISD::VASR "HexagonISD::VASR" HexagonISD::VLSR "HexagonISD::VLSR" HexagonISD::VSPLAT "HexagonISD::VSPLAT" HexagonISD::VEXTRACTW "HexagonISD::VEXTRACTW" HexagonISD::VINSERTW0 "HexagonISD::VINSERTW0" HexagonISD::VROR "HexagonISD::VROR" HexagonISD::READCYCLE "HexagonISD::READCYCLE" HexagonISD::VZERO "HexagonISD::VZERO" HexagonISD::D2P "HexagonISD::D2P" HexagonISD::P2D "HexagonISD::P2D" HexagonISD::V2Q "HexagonISD::V2Q" HexagonISD::Q2V "HexagonISD::Q2V" HexagonISD::QCAT "HexagonISD::QCAT" HexagonISD::QTRUE "HexagonISD::QTRUE" HexagonISD::QFALSE "HexagonISD::QFALSE" HexagonISD::TYPECAST "HexagonISD::TYPECAST" HexagonISD::OP_END


"Unknown opcode to check as cheap as a move!"

Return true if the instruction is as cheap as a move instruction .


<s> int null_prologue ( ) { if ( ! reload_completed ) return 0 ; if ( ! frame_laid_out ) m88k_layout_frame ( ) ; return ( ! frame_pointer_needed && nregs == 0 && nxregs == 0 && m88k_stack_size == 0 ) ; } </s>

Return true if this function is known to have a null prologue .


<s> static void mcore_add_gc_roots ( ) { ggc_add_rtx_root ( & arch_compare_op0 , 1 ) ; ggc_add_rtx_root ( & arch_compare_op1 , 1 ) ; } </s>

Called to register all of our global variables with the garbage collector .


<s>
void
PTXInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DstReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
for
(
int
i
=
0
,
e
=
sizeof
(
map
)
/
sizeof
(
map
[
0
]
)
;
i
!=
e
;
++
i
)
if
(
PTX
::
RRegs32RegClass
.
contains
(
DstReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
PTX
::
MOVrr
)
,
DstReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
return
;
}
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
</s>


<s> EVT X86TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & Context , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i8 ; if ( VT . isSimple ( ) ) { MVT VVT = VT . getSimpleVT ( ) ; const unsigned NumElts = VVT . getVectorNumElements ( ) ; MVT EltVT = VVT . getVectorElementType ( ) ; if ( VVT . is512BitVector ( ) ) { if ( Subtarget . hasAVX512 ( ) ) if ( EltVT == MVT :: i32 || EltVT == MVT :: i64 || EltVT == MVT :: f32 || EltVT == MVT :: f64 ) switch ( NumElts ) { case 8 : return MVT :: v8i1 ; case 16 : return MVT :: v16i1 ; } if ( Subtarget . hasBWI ( ) ) if ( EltVT == MVT :: i8 || EltVT == MVT :: i16 ) switch ( NumElts ) { case 32 : return MVT :: v32i1 ; case 64 : return MVT :: v64i1 ; } } if ( Subtarget . hasBWI ( ) && Subtarget . hasVLX ( ) ) return MVT :: getVectorVT ( MVT :: i1 , NumElts ) ; if ( ! isTypeLegal ( VT ) && getTypeAction ( Context , VT ) == TypePromoteInteger ) { EVT LegalVT = getTypeToTransformTo ( Context , VT ) ; EltVT = LegalVT . getVectorElementType ( ) . getSimpleVT ( ) ; } if ( Subtarget . hasVLX ( ) && EltVT . getSizeInBits ( ) >= 32 ) switch ( NumElts ) { case 2 : return MVT :: v2i1 ; case 4 : return MVT :: v4i1 ; case 8 : return MVT :: v8i1 ; } } return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> MachineBasicBlock :: iterator end ( ) { assert ( End != nullptr ) ; return End ; } </s>

Get a const_iterator to the end of the symbol table .


<s>
MachineBasicBlock
*
SparcTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown Custom Instruction!"
)
;
case
SP
::
SELECT_CC_Int_ICC
:
case
SP
::
SELECT_CC_FP_ICC
:
case
SP
::
SELECT_CC_DFP_ICC
:
case
SP
::
SELECT_CC_QFP_ICC
:
return
expandSelectCC
(
MI
,
BB
,
SP
::
BCOND
)
;
case
SP
::
SELECT_CC_Int_FCC
:
case
SP
::
SELECT_CC_FP_FCC
:
case
SP
::
SELECT_CC_DFP_FCC
:
case
SP
::
SELECT_CC_QFP_FCC
:
return
expandSelectCC
(
MI
,
BB
,
SP
::
FBCOND
)
;
case
SP
::
EH_SJLJ_SETJMP32ri
:
case
SP
::
EH_SJLJ_SETJMP32rr
:
return
emitEHSjLjSetJmp
(
MI
,
BB
)
;
case
SP
::
EH_SJLJ_LONGJMP32rr
:
case
SP
::
EH_SJLJ_LONGJMP32ri
:
return
emitEHSjLjLongJmp
(
MI
,
BB
)
;
}
}
</s>


<s> SDValue SITargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { default : return AMDGPUTargetLowering :: LowerOperation ( Op , DAG ) ; case ISD :: BRCOND : return LowerBRCOND ( Op , DAG ) ; case ISD :: SELECT_CC : return LowerSELECT_CC ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> void BlackfinRegisterInfo :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const { } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> int sign_extended_p ( rtx x , int bits , rtx insn ) { HOST_WIDE_INT w ; int i , n ; do { while ( REG_P ( x ) ) { x = pdp10_find_last_value ( x , & insn ) ; if ( x == NULL_RTX ) return 0 ; } switch ( GET_CODE ( x ) ) { case ASHIFTRT : n = INTVAL_OR_ELSE ( XEXP ( x , 1 ) , 0 ) ; x = XEXP ( x , 0 ) ; break ; case SIGN_EXTRACT : n = BITS_PER_WORD - INTVAL_OR_ELSE ( XEXP ( x , 1 ) , BITS_PER_WORD ) ; x = NULL_RTX ; break ; case IOR : w = INTVAL_OR_ELSE ( XEXP ( x , 1 ) , 0 ) ; for ( i = BITS_PER_WORD - 1 ; i >= 0 ; i -- ) { if ( ! ( w & ( ( HWINT ( 1 ) ) << i ) ) ) break ; } n = BITS_PER_WORD - i ; x = XEXP ( x , 0 ) ; break ; default : return 0 ; } if ( n >= bits ) return 1 ; bits -= n ; } while ( x ) ; return 0 ; } </s>

Return nonzero iff the last value X was set to before INSN had BITS sign-extended bits .


<s>
uint32_t
AMDGPUTargetLowering
::
getImplicitParameterOffset
(
const
MachineFunction
&
MF
,
const
ImplicitParameter
Param
)
const
{
const
AMDGPUMachineFunction
*
MFI
=
MF
.
getInfo
<
AMDGPUMachineFunction
>
(
)
;
const
AMDGPUSubtarget
&
ST
=
AMDGPUSubtarget
::
get
(
getTargetMachine
(
)
,
MF
.
getFunction
(
)
)
;
unsigned
ExplicitArgOffset
=
ST
.
getExplicitKernelArgOffset
(
MF
.
getFunction
(
)
)
;
unsigned
Alignment
=
ST
.
getAlignmentForImplicitArgPtr
(
)
;
uint64_t
ArgOffset
=
alignTo
(
MFI
->
getExplicitKernArgSize
(
)
,
Alignment
)
+
ExplicitArgOffset
;
switch
(
Param
)
{
case
GRID_DIM
:
return
ArgOffset
;
case
GRID_OFFSET
:
return
ArgOffset
+
4
;
}
llvm_unreachable
(
"unexpected implicit parameter type"
)
;
}
</s>

Helper function that returns the byte offset of the given type of implicit parameter .

AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
4
"unexpected implicit parameter type"


"Requesting 64-bit offset in 32-bit immediate!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < 512 > Key ; Key . reserve ( CPU . size ( ) + FS . size ( ) ) ; Key += CPU ; Key += FS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) Key += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; unsigned CPUFSWidth = Key . size ( ) ; unsigned PreferVectorWidthOverride = 0 ; if ( F . hasFnAttribute ( "prefer-vector-width" ) ) { StringRef Val = F . getFnAttribute ( "prefer-vector-width" ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( 0 , Width ) ) { Key += ",prefer-vector-width=" ; Key += Val ; PreferVectorWidthOverride = Width ; } } unsigned RequiredVectorWidth = UINT32_MAX ; if ( F . hasFnAttribute ( "min-legal-vector-width" ) ) { StringRef Val = F . getFnAttribute ( "min-legal-vector-width" ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( 0 , Width ) ) { Key += ",min-legal-vector-width=" ; Key += Val ; RequiredVectorWidth = Width ; } } FS = Key . slice ( CPU . size ( ) , CPUFSWidth ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < X86Subtarget > ( TargetTriple , CPU , FS , * this , MaybeAlign ( Options . StackAlignmentOverride ) , PreferVectorWidthOverride , RequiredVectorWidth ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static bool loongarch_legitimate_address_p ( machine_mode mode , rtx x , bool strict_p ) { struct loongarch_address_info addr ; return loongarch_classify_address ( & addr , x , mode , strict_p ) ; } </s>


<s> static int s390_check_qrst_address ( char c , rtx op , bool lit_pool_ok ) { struct s390_address addr ; bool decomposed = false ; if ( s390_loadrelative_operand_p ( op , NULL , NULL ) ) return 0 ; if ( ! lit_pool_ok ) { if ( ! s390_decompose_address ( op , & addr ) ) return 0 ; if ( addr . literal_pool ) return 0 ; decomposed = true ; } switch ( c ) { case 'Q' : if ( ! decomposed && ! s390_decompose_address ( op , & addr ) ) return 0 ; if ( addr . indx ) return 0 ; if ( ! s390_short_displacement ( addr . disp ) ) return 0 ; break ; case 'R' : if ( TARGET_LONG_DISPLACEMENT ) { if ( ! decomposed && ! s390_decompose_address ( op , & addr ) ) return 0 ; if ( ! s390_short_displacement ( addr . disp ) ) return 0 ; } break ; case 'S' : if ( ! TARGET_LONG_DISPLACEMENT ) return 0 ; if ( ! decomposed && ! s390_decompose_address ( op , & addr ) ) return 0 ; if ( addr . indx ) return 0 ; if ( s390_short_displacement ( addr . disp ) ) return 0 ; break ; case 'T' : if ( ! TARGET_LONG_DISPLACEMENT ) return 0 ; if ( ( decomposed || s390_decompose_address ( op , & addr ) ) && s390_short_displacement ( addr . disp ) ) return 0 ; break ; default : return 0 ; } return 1 ; } </s>

Return true if the address in OP is valid for constraint letter C if wrapped in a MEM rtx . Set LIT_POOL_OK to true if it literal pool MEMs should be accepted . Only the Q , R , S , T constraint letters are allowed for C .


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( ( N -> getOpcode ( ) == X86ISD :: CALL && ! Subtarget -> callRegIndirect ( ) ) || ( N -> getOpcode ( ) == X86ISD :: TC_RETURN && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; MVT SrcVT = N -> getOperand ( 0 ) . getSimpleValueType ( ) ; MVT DstVT = N -> getSimpleValueType ( 0 ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const X86TargetLowering * X86Lowering = static_cast < const X86TargetLowering * > ( getTargetLowering ( ) ) ; bool SrcIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } MVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> bool HexagonInstrInfo :: getIncrementValue ( const MachineInstr & MI , int & Value ) const { if ( isPostIncrement ( MI ) ) { unsigned AccessSize ; return getBaseAndOffset ( MI , Value , AccessSize ) ; } if ( MI . getOpcode ( ) == Hexagon :: A2_addi ) { Value = MI . getOperand ( 2 ) . getImm ( ) ; return true ; } return false ; } </s>

If the instruction is an increment of a constant value , return the amount .


<s> bool HexagonPassConfig :: addInstSelector ( ) { HexagonTargetMachine & TM = getHexagonTargetMachine ( ) ; bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) addPass ( createHexagonOptimizeSZextends ( ) ) ; addPass ( createHexagonISelDag ( TM , getOptLevel ( ) ) ) ; if ( ! NoOpt ) { if ( EnableGenPred ) addPass ( createHexagonGenPredicate ( ) ) ; if ( EnableLoopResched ) addPass ( createHexagonLoopRescheduling ( ) ) ; if ( ! DisableHSDR ) addPass ( createHexagonSplitDoubleRegs ( ) ) ; if ( EnableBitSimplify ) addPass ( createHexagonBitSimplify ( ) ) ; addPass ( createHexagonPeephole ( ) ) ; if ( ! DisableHCP ) { addPass ( createHexagonConstPropagationPass ( ) ) ; addPass ( & UnreachableMachineBlockElimID ) ; } if ( EnableGenInsert ) addPass ( createHexagonGenInsert ( ) ) ; if ( EnableEarlyIf ) addPass ( createHexagonEarlyIfConversion ( ) ) ; } return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .

Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon


<s> bool SIInstrInfo :: isLegalFLATOffset ( int64_t Offset , unsigned AddrSpace , bool Signed ) const { if ( ! ST . hasFlatInstOffsets ( ) ) return false ; if ( ST . hasFlatSegmentOffsetBug ( ) && AddrSpace == AMDGPUAS :: FLAT_ADDRESS ) return false ; unsigned N = AMDGPU :: getNumFlatOffsetBits ( ST , Signed ) ; return Signed ? isIntN ( N , Offset ) : isUIntN ( N , Offset ) ; } </s>

Returns if Offset is legal for the subtarget as the offset to a FLAT encoded instruction .

AMDGPU SI AMDGPU AMDGPU::getNumFlatOffsetBits


<s> unsigned RISCVInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : { if ( MI . getParent ( ) && MI . getParent ( ) -> getParent ( ) ) { const auto MF = MI . getMF ( ) ; const auto & TM = static_cast < const RISCVTargetMachine & > ( MF -> getTarget ( ) ) ; const MCRegisterInfo & MRI = * TM . getMCRegisterInfo ( ) ; const MCSubtargetInfo & STI = * TM . getMCSubtargetInfo ( ) ; const RISCVSubtarget & ST = MF -> getSubtarget < RISCVSubtarget > ( ) ; if ( isCompressibleInst ( MI , & ST , MRI , STI ) ) return 2 ; } return get ( Opcode ) . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return 0 ; case RISCV :: PseudoCALLReg : case RISCV :: PseudoCALL : case RISCV :: PseudoJump : case RISCV :: PseudoTAIL : case RISCV :: PseudoLLA : case RISCV :: PseudoLA : case RISCV :: PseudoLA_TLS_IE : case RISCV :: PseudoLA_TLS_GD : return 8 ; case RISCV :: PseudoAtomicLoadNand32 : case RISCV :: PseudoAtomicLoadNand64 : return 20 ; case RISCV :: PseudoMaskedAtomicSwap32 : case RISCV :: PseudoMaskedAtomicLoadAdd32 : case RISCV :: PseudoMaskedAtomicLoadSub32 : return 28 ; case RISCV :: PseudoMaskedAtomicLoadNand32 : return 32 ; case RISCV :: PseudoMaskedAtomicLoadMax32 : case RISCV :: PseudoMaskedAtomicLoadMin32 : return 44 ; case RISCV :: PseudoMaskedAtomicLoadUMax32 : case RISCV :: PseudoMaskedAtomicLoadUMin32 : return 36 ; case RISCV :: PseudoCmpXchg32 : case RISCV :: PseudoCmpXchg64 : return 16 ; case RISCV :: PseudoMaskedCmpXchg32 : return 32 ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const auto & TM = static_cast < const RISCVTargetMachine & > ( MF . getTarget ( ) ) ; return getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> bool isAllocated ( unsigned Reg ) const { return UsedRegs [ Reg / 32 ] & ( 1 << ( Reg & 31 ) ) ; } </s>

isAllocated - Return true if the specified register ( or an alias ) is allocated .


<s> static rtx tilepro_function_value ( const_tree valtype , const_tree fn_decl_or_type , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode mode ; int unsigned_p ; mode = TYPE_MODE ( valtype ) ; unsigned_p = TYPE_UNSIGNED ( valtype ) ; mode = promote_function_mode ( valtype , mode , & unsigned_p , fn_decl_or_type , 1 ) ; return gen_rtx_REG ( mode , 0 ) ; } </s>


<s>
void
PatmosInstPrinter
::
printInst
(
const
MCInst
*
MI
,
uint64_t
Address
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
,
raw_ostream
&
O
)
{
printInstPrefix
(
MI
,
O
)
;
printInstruction
(
MI
,
Address
,
O
)
;
if
(
!
isBundled
(
MI
)
&&
InBundle
)
{
O
<<
" }"
;
InBundle
=
false
;
}
printAnnotation
(
O
,
Annot
)
;
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s> void emitThumbFunc ( MCSymbol * Func ) override { } </s>

Note in the output that the specified Func is a Thumb mode function ( ARM target only ) .


<s> const JVMInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> static bool rs6000_cannot_substitute_mem_equiv_p ( rtx mem ) { gcc_assert ( MEM_P ( mem ) ) ; if ( GET_CODE ( XEXP ( mem , 0 ) ) == AND ) return true ; return false ; } </s>


<s> static rtx mips_call_tls_get_addr ( rtx sym , enum mips_symbol_type type , rtx v0 ) { rtx insn , loc , a0 ; a0 = gen_rtx_REG ( Pmode , GP_ARG_FIRST ) ; if ( ! mips_tls_symbol ) mips_tls_symbol = init_one_libfunc ( "__tls_get_addr" ) ; loc = mips_unspec_address ( sym , type ) ; start_sequence ( ) ; emit_insn ( gen_rtx_SET ( a0 , gen_rtx_LO_SUM ( Pmode , pic_offset_table_rtx , loc ) ) ) ; insn = mips_expand_call ( MIPS_CALL_NORMAL , v0 , mips_tls_symbol , const0_rtx , NULL_RTX , false ) ; RTL_CONST_CALL_P ( insn ) = 1 ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , a0 ) ; insn = get_insns ( ) ; end_sequence ( ) ; return insn ; } </s>

Return an instruction sequence that calls __tls_get_addr . SYM is the TLS symbol we are referencing and TYPE is the symbol type to use ( either global dynamic or local dynamic ) . V0 is an RTX for the return value location .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"ARM64 Address Type Promotion"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static bool rs6000_must_pass_in_stack ( machine_mode mode , const_tree type ) { if ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT ) return must_pass_in_stack_var_size ( mode , type ) ; else return must_pass_in_stack_var_size_or_pad ( mode , type ) ; } </s>

Return true if TYPE must be passed on the stack and not in registers .


<s> MachineInstrBuilder MipsInstrInfo :: genInstrWithNewOpc ( unsigned NewOpc , MachineBasicBlock :: iterator I ) const { MachineInstrBuilder MIB ; int ZeroOperandPosition = - 1 ; bool BranchWithZeroOperand = false ; if ( I -> isBranch ( ) && ! I -> isPseudo ( ) ) { auto TRI = I -> getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; ZeroOperandPosition = I -> findRegisterUseOperandIdx ( Mips :: ZERO , false , TRI ) ; BranchWithZeroOperand = ZeroOperandPosition != - 1 ; } if ( BranchWithZeroOperand ) { switch ( NewOpc ) { case Mips :: BEQC : NewOpc = Mips :: BEQZC ; break ; case Mips :: BNEC : NewOpc = Mips :: BNEZC ; break ; case Mips :: BGEC : NewOpc = Mips :: BGEZC ; break ; case Mips :: BLTC : NewOpc = Mips :: BLTZC ; break ; case Mips :: BEQC64 : NewOpc = Mips :: BEQZC64 ; break ; case Mips :: BNEC64 : NewOpc = Mips :: BNEZC64 ; break ; } } MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , get ( NewOpc ) ) ; if ( NewOpc == Mips :: JIC || NewOpc == Mips :: JIALC || NewOpc == Mips :: JIC64 || NewOpc == Mips :: JIALC64 ) { if ( NewOpc == Mips :: JIALC || NewOpc == Mips :: JIALC64 ) MIB -> RemoveOperand ( 0 ) ; for ( unsigned J = 0 , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { MIB . add ( I -> getOperand ( J ) ) ; } MIB . addImm ( 0 ) ; for ( unsigned J = I -> getDesc ( ) . getNumOperands ( ) , E = I -> getNumOperands ( ) ; J < E ; ++ J ) { const MachineOperand & MO = I -> getOperand ( J ) ; if ( MO . isMCSymbol ( ) && ( MO . getTargetFlags ( ) & MipsII :: MO_JALR ) ) MIB . addSym ( MO . getMCSymbol ( ) , MipsII :: MO_JALR ) ; } } else { for ( unsigned J = 0 , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { if ( BranchWithZeroOperand && ( unsigned ) ZeroOperandPosition == J ) continue ; MIB . add ( I -> getOperand ( J ) ) ; } } MIB . copyImplicitOps ( * I ) ; MIB . cloneMemRefs ( * I ) ; return MIB ; } </s>

Create an instruction which has the same operands and memory operands as MI but has a new opcode .


<s> static recps_type get_recps_type ( machine_mode mode ) { switch ( mode ) { case E_SFmode : return ( gen_aarch64_frecpssf ) ; case E_V2SFmode : return ( gen_aarch64_frecpsv2sf ) ; case E_V4SFmode : return ( gen_aarch64_frecpsv4sf ) ; case E_DFmode : return ( gen_aarch64_frecpsdf ) ; case E_V2DFmode : return ( gen_aarch64_frecpsv2df ) ; default : gcc_unreachable ( ) ; } } </s>

Select reciprocal series step insn depending on machine mode .


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return createSystemZObjectWriter ( OS , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static int frv_function_contains_far_jump ( void ) { rtx_insn * insn = get_insns ( ) ; while ( insn != NULL && ! ( JUMP_P ( insn ) && get_attr_far_jump ( insn ) == FAR_JUMP_YES ) ) insn = NEXT_INSN ( insn ) ; return ( insn != NULL ) ; } </s>

True if the current function contains a far jump .


<s> void aarch64_init_builtin_rsqrt ( void ) { tree fndecl = NULL ; tree ftype = NULL ; tree V2SF_type_node = build_vector_type ( float_type_node , 2 ) ; tree V2DF_type_node = build_vector_type ( double_type_node , 2 ) ; tree V4SF_type_node = build_vector_type ( float_type_node , 4 ) ; struct builtin_decls_data { tree type_node ; const char * builtin_name ; int function_code ; } ; builtin_decls_data bdda [ ] = { { double_type_node , "__builtin_aarch64_rsqrt_df" , AARCH64_BUILTIN_RSQRT_DF } , { float_type_node , "__builtin_aarch64_rsqrt_sf" , AARCH64_BUILTIN_RSQRT_SF } , { V2DF_type_node , "__builtin_aarch64_rsqrt_v2df" , AARCH64_BUILTIN_RSQRT_V2DF } , { V2SF_type_node , "__builtin_aarch64_rsqrt_v2sf" , AARCH64_BUILTIN_RSQRT_V2SF } , { V4SF_type_node , "__builtin_aarch64_rsqrt_v4sf" , AARCH64_BUILTIN_RSQRT_V4SF } } ; builtin_decls_data * bdd = bdda ; builtin_decls_data * bdd_end = bdd + ( sizeof ( bdda ) / sizeof ( builtin_decls_data ) ) ; for ( ; bdd < bdd_end ; bdd ++ ) { ftype = build_function_type_list ( bdd -> type_node , bdd -> type_node , NULL_TREE ) ; fndecl = add_builtin_function ( bdd -> builtin_name , ftype , bdd -> function_code , BUILT_IN_MD , NULL , NULL_TREE ) ; aarch64_builtin_decls [ bdd -> function_code ] = fndecl ; } } </s>

Add builtins for reciprocal square root .


<s> int rx_initial_elimination_offset ( int from , int to ) { unsigned int low ; unsigned int high ; unsigned int frame_size ; unsigned int stack_size ; unsigned int mask ; rx_get_stack_layout ( & low , & high , & mask , & frame_size , & stack_size ) ; if ( from == ARG_POINTER_REGNUM ) { if ( low ) frame_size += ( ( high - low ) + 1 ) * UNITS_PER_WORD ; else frame_size += bit_count ( mask ) * UNITS_PER_WORD ; frame_size += 1 * UNITS_PER_WORD ; if ( to == FRAME_POINTER_REGNUM ) return frame_size ; gcc_assert ( to == STACK_POINTER_REGNUM ) ; return frame_size + stack_size ; } gcc_assert ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) ; return stack_size ; } </s>

Compute the offset ( in words ) between FROM ( arg pointer or frame pointer ) and TO ( frame pointer or stack pointer ) . See ASCII art comment at the start of rx_expand_prologue for more information .


<s> bool HexagonCopyToCombine :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; if ( IsCombinesDisabled ) return false ; bool HasChanged = false ; ST = & MF . getSubtarget < HexagonSubtarget > ( ) ; TRI = ST -> getRegisterInfo ( ) ; TII = ST -> getInstrInfo ( ) ; const Function * F = MF . getFunction ( ) ; bool OptForSize = F -> hasFnAttribute ( Attribute :: OptimizeForSize ) ; ShouldCombineAggressively = MF . getTarget ( ) . getOptLevel ( ) <= CodeGenOpt :: Default ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( * BI ) ; for ( MachineBasicBlock :: iterator MI = BI -> begin ( ) , End = BI -> end ( ) ; MI != End ; ) { MachineInstr & I1 = * MI ++ ; if ( I1 . isDebugValue ( ) ) continue ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( & I1 ) ) continue ; if ( ! isCombinableInstType ( I1 , TII , ShouldCombineAggressively ) ) continue ; bool DoInsertAtI1 = false ; DbgMItoMove . clear ( ) ; MachineInstr * I2 = findPairable ( I1 , DoInsertAtI1 , OptForSize ) ; if ( I2 ) { HasChanged = true ; combine ( I1 , * I2 , MI , DoInsertAtI1 , OptForSize ) ; } } } return HasChanged ; } </s>

runOnMachineFunction - Emit the function body .


"internal compiler error.  Bad address:"

"internal compiler error.  Unknown mode:"

Use S for SI regsUse B & T for parts of DI regs X - stack pointer name Registers Q - byte sized register name U - high byte of word register V - low byte of word register H - word register name I - next word register name S & B - long register name T - next long register name D - quad register name P - register name in size of pointer Integers O - log two of value P - inverted log two H - bottom 16 bits I - top 16 bits N - negative B - high 32 bits of 32bit number . default : value Memory I - adjusted upwards by two T - adjusted upwards by four default : value Address H - low 16 bits I - high 16 bits A - as long constant S - as A but with # default : error Misc C - conditional name D - reverse conditional name F - clear v flag if necessary

"internal compiler error.  Bad address:"


<s>
void
recordRelocation
(
MCAssembler
&
Asm
,
const
MCAsmLayout
&
Layout
,
const
MCFragment
*
Fragment
,
const
MCFixup
&
Fixup
,
MCValue
Target
,
bool
&
IsPCRel
,
uint64_t
&
FixedValue
)
override
{
assert
(
!
"Not implemented"
)
;
}
</s>


<s> static int csky_arg_partial_bytes ( cumulative_args_t pcum_v , machine_mode mode , tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * pcum = get_cumulative_args ( pcum_v ) ; int param_size = csky_num_arg_regs ( mode , type ) ; if ( * pcum < CSKY_NPARM_REGS && * pcum + param_size > CSKY_NPARM_REGS ) return ( CSKY_NPARM_REGS - * pcum ) * UNITS_PER_WORD ; return 0 ; } </s>

Implement TARGET_ARG_PARTIAL_BYTES . Return the number of bytes at the beginning of an argument that must be put in registers . The value must be zero for arguments that are passed entirely in registers or that are entirely pushed on the stack .


<s> bool rvexPassConfig :: addInstSelector ( ) { addPass ( creatervexISelDag ( getrvexTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void EmitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , bool ) override { EmitA64MappingSymbol ( ) ; MCELFStreamer :: EmitInstruction ( Inst , STI ) ; AArch64BranchTargetAligner BTA ; unsigned Opcode = Inst . getOpcode ( ) ; if ( BTA . needsSpecialAlignment ( STI . getCPU ( ) , Opcode ) ) { unsigned BA = BTA . getBranchTargetAlignment ( Inst ) ; if ( BA ) { EmitA64MappingSymbol ( ) ; MCELFStreamer :: EmitCodeAlignment ( BA ) ; } } } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool LEGRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> void SIFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; SavedRegs . reset ( MFI -> getStackPtrOffsetReg ( ) ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> static unsigned int bfin_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( mode == PDImode && ( regno == REG_A0 || regno == REG_A1 ) ) return 1 ; if ( mode == V2PDImode && ( regno == REG_A0 || regno == REG_A1 ) ) return 2 ; return CLASS_MAX_NREGS ( GENERAL_REGS , mode ) ; } </s>


<s> static rtx iq2000_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( ( ( GET_MODE_CLASS ( mode ) != MODE_INT || GET_MODE_SIZE ( mode ) >= 4 ) ? mode : SImode ) , GP_RETURN ) ; } </s>

Worker function for TARGET_LIBCALL_VALUE .


<s> void ARMPassConfig :: addIRPasses ( ) { if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( SimplifyCFGOptions ( ) . hoistCommonInsts ( true ) . sinkCommonInsts ( true ) , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < ARMSubtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST . isThumb1Only ( ) ; } ) ) ; addPass ( createMVEGatherScatterLoweringPass ( ) ) ; addPass ( createMVELaneInterleavingPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( createARMParallelDSPPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardCheckPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> void GCNPassConfig :: addPreEmitPass ( ) { addPass ( createSIInsertWaitsPass ( ) , false ) ; addPass ( createSILowerControlFlowPass ( ) , false ) ; if ( InsertNops ) { addPass ( createSIInsertNopsPass ( ) , false ) ; } } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static rtx tilepro_text_label_rtx ( void ) { return cfun -> machine -> text_label_rtx ; } </s>

Return the register storing the value of the text label .


<s> void TOYRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { MachineInstr & MI = * II ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineFrameInfo * MFI = & MF . getFrameInfo ( ) ; unsigned FI = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned ImmOpIdx = 0 ; switch ( MI . getOpcode ( ) ) { default : return ; case TOY :: LDR : case TOY :: STR : ImmOpIdx = FIOperandNum + 1 ; break ; } MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ; int Offset = MFI -> getObjectOffset ( FI ) + MFI -> getStackSize ( ) + ImmOp . getImm ( ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( TOY :: SP , false ) ; ImmOp . setImm ( Offset ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


"Unknown regclass in loadRegFromStackSlot!"

Load the specified register of the given register class from the specified stack frame index .


<s> static unsigned int riscv_function_arg_boundary ( machine_mode mode , const_tree type ) { unsigned int alignment ; if ( type && ! AGGREGATE_TYPE_P ( type ) ) alignment = TYPE_ALIGN ( TYPE_MAIN_VARIANT ( type ) ) ; else alignment = type ? TYPE_ALIGN ( type ) : GET_MODE_ALIGNMENT ( mode ) ; return MIN ( PREFERRED_STACK_BOUNDARY , MAX ( PARM_BOUNDARY , alignment ) ) ; } </s>

Implement TARGET_FUNCTION_ARG_BOUNDARY . Every parameter gets at least PARM_BOUNDARY bits of alignment , but will be given anything up to STACK_BOUNDARY bits if the type requires it .


<s> static int is_regular_file ( char * name ) { int ret ; struct stat statbuf ; ret = stat ( name , & statbuf ) ; return ! ret && S_ISREG ( statbuf . st_mode ) ; } </s>

Check to see if NAME is a regular file , i.e . not a directory .


<s> bool MSP430TargetMachine :: addPreEmitPass ( PassManagerBase & PM ) { PM . add ( createMSP430BranchSelectionPass ( ) ) ; return false ; } </s>


<s> void MipsPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; if ( getMipsSubtarget ( ) . os16 ( ) ) addPass ( createMipsOs16 ( getMipsTargetMachine ( ) ) ) ; if ( getMipsSubtarget ( ) . inMips16HardFloat ( ) ) addPass ( createMips16HardFloat ( getMipsTargetMachine ( ) ) ) ; addPass ( createMipsOptimizeMathLibCalls ( getMipsTargetMachine ( ) ) ) ; } </s>

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips


<s> void SparcRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const SparcSubtarget & Subtarget = MF . getSubtarget < SparcSubtarget > ( ) ; const SparcFrameLowering * TFI = getFrameLowering ( MF ) ; Register FrameReg ; int Offset ; Offset = TFI -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) . getFixed ( ) ; Offset += MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ; if ( ! Subtarget . isV9 ( ) || ! Subtarget . hasHardQuad ( ) ) { if ( MI . getOpcode ( ) == SP :: STQFri ) { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; Register SrcReg = MI . getOperand ( 2 ) . getReg ( ) ; Register SrcEvenReg = getSubReg ( SrcReg , SP :: sub_even64 ) ; Register SrcOddReg = getSubReg ( SrcReg , SP :: sub_odd64 ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( SP :: STDFri ) ) . addReg ( FrameReg ) . addImm ( 0 ) . addReg ( SrcEvenReg ) ; replaceFI ( MF , * StMI , * StMI , dl , 0 , Offset , FrameReg ) ; MI . setDesc ( TII . get ( SP :: STDFri ) ) ; MI . getOperand ( 2 ) . setReg ( SrcOddReg ) ; Offset += 8 ; } else if ( MI . getOpcode ( ) == SP :: LDQFri ) { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; Register DestReg = MI . getOperand ( 0 ) . getReg ( ) ; Register DestEvenReg = getSubReg ( DestReg , SP :: sub_even64 ) ; Register DestOddReg = getSubReg ( DestReg , SP :: sub_odd64 ) ; MachineInstr * LdMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( SP :: LDDFri ) , DestEvenReg ) . addReg ( FrameReg ) . addImm ( 0 ) ; replaceFI ( MF , * LdMI , * LdMI , dl , 1 , Offset , FrameReg ) ; MI . setDesc ( TII . get ( SP :: LDDFri ) ) ; MI . getOperand ( 0 ) . setReg ( DestOddReg ) ; Offset += 8 ; } } replaceFI ( MF , II , MI , dl , FIOperandNum , Offset , FrameReg ) ; } </s>


<s> bool AArch64InstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( TargetInstrInfo :: isSchedulingBoundary ( MI , MBB , MF ) ) return true ; return isSEHInstruction ( MI ) ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s>
bool
ARMBaseInstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
TBB
=
nullptr
;
FBB
=
nullptr
;
MachineBasicBlock
::
instr_iterator
I
=
MBB
.
instr_end
(
)
;
if
(
I
==
MBB
.
instr_begin
(
)
)
return
false
;
I
;
while
(
isPredicated
(
*
I
)
||
I
->
isTerminator
(
)
||
I
->
isDebugValue
(
)
)
{
bool
CantAnalyze
=
false
;
while
(
I
->
isDebugInstr
(
)
||
!
I
->
isTerminator
(
)
||
isSpeculationBarrierEndBBOpcode
(
I
->
getOpcode
(
)
)
||
I
->
getOpcode
(
)
==
ARM
::
t2DoLoopStartTP
)
{
if
(
I
==
MBB
.
instr_begin
(
)
)
return
false
;
I
;
}
if
(
isIndirectBranchOpcode
(
I
->
getOpcode
(
)
)
||
isJumpTableBranchOpcode
(
I
->
getOpcode
(
)
)
)
{
CantAnalyze
=
true
;
}
else
if
(
isUncondBranchOpcode
(
I
->
getOpcode
(
)
)
)
{
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
}
else
if
(
isCondBranchOpcode
(
I
->
getOpcode
(
)
)
)
{
if
(
!
Cond
.
empty
(
)
)
return
true
;
assert
(
!
FBB
&&
"FBB should have been null."
)
;
FBB
=
TBB
;
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
Cond
.
push_back
(
I
->
getOperand
(
1
)
)
;
Cond
.
push_back
(
I
->
getOperand
(
2
)
)
;
}
else
if
(
I
->
isReturn
(
)
)
{
CantAnalyze
=
true
;
}
else
{
return
true
;
}
if
(
!
isPredicated
(
*
I
)
&&
(
isUncondBranchOpcode
(
I
->
getOpcode
(
)
)
||
isIndirectBranchOpcode
(
I
->
getOpcode
(
)
)
||
isJumpTableBranchOpcode
(
I
->
getOpcode
(
)
)
||
I
->
isReturn
(
)
)
)
{
Cond
.
clear
(
)
;
FBB
=
nullptr
;
if
(
AllowModify
)
{
MachineBasicBlock
::
iterator
DI
=
std
::
next
(
I
)
;
while
(
DI
!=
MBB
.
instr_end
(
)
)
{
MachineInstr
&
InstToDelete
=
*
DI
;
++
DI
;
if
(
isSpeculationBarrierEndBBOpcode
(
InstToDelete
.
getOpcode
(
)
)
)
continue
;
InstToDelete
.
eraseFromParent
(
)
;
}
}
}
if
(
CantAnalyze
)
{
if
(
AllowModify
&&
!
isPredicated
(
MBB
.
back
(
)
)
&&
isUncondBranchOpcode
(
MBB
.
back
(
)
.
getOpcode
(
)
)
&&
TBB
&&
MBB
.
isLayoutSuccessor
(
TBB
)
)
removeBranch
(
MBB
)
;
return
true
;
}
if
(
I
==
MBB
.
instr_begin
(
)
)
return
false
;
I
;
}
return
false
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


"Cannot store this register to stack slot!"

Store the specified register of the given register class to the specified stack frame index .


<s> bool SystemZInstrInfo :: isPredicable ( MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; return STI . hasLoadStoreOnCond ( ) && getConditionalMove ( Opcode ) ; } </s>

Return true if the specified instruction can be predicated .


<s> bool HexagonAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & OS ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , OS ) ; case 'c' : printOperand ( MI , OpNo , OS ) ; return false ; case 'L' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + 1 == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + 1 ) . isReg ( ) ) return true ; ++ OpNo ; break ; case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) OS << "i" ; return false ; } } printOperand ( MI , OpNo , OS ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


"%qE attribute only applies to functions"

"interrupt handlers cannot have arguments"

"argument of %qE attribute is not a string constant"

"argument of %qE attribute is not %qs, %qs %qs, %qs, %qs, "

Handle an `` interrupt '' attribute ; arguments as in struct attribute_spec.handler .