<s> static bool r10k_uncached_address_p ( unsigned HOST_WIDE_INT address ) { unsigned HOST_WIDE_INT upper ; if ( address + 0x60000000 < 0x20000000 ) return true ; if ( Pmode == DImode ) { upper = ( address >> 40 ) & 0xf9ffff ; if ( upper == 0x900000 || upper == 0xb80000 ) return true ; } return false ; } </s>

Return true if ADDRESS is known to be an uncached address on R10K systems .


<s> void expand_fusion_p9_store ( rtx * operands ) { rtx tmp_reg = operands [ 0 ] ; rtx addis_value = operands [ 1 ] ; rtx orig_mem = operands [ 2 ] ; rtx src = operands [ 3 ] ; rtx new_addr , new_mem , orig_addr , offset , set , clobber , insn , new_src ; enum rtx_code plus_or_lo_sum ; machine_mode target_mode = GET_MODE ( orig_mem ) ; machine_mode ptr_mode = Pmode ; gcc_assert ( MEM_P ( orig_mem ) ) ; orig_addr = XEXP ( orig_mem , 0 ) ; plus_or_lo_sum = GET_CODE ( orig_addr ) ; gcc_assert ( plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM ) ; offset = XEXP ( orig_addr , 1 ) ; new_addr = gen_rtx_fmt_ee ( plus_or_lo_sum , ptr_mode , addis_value , offset ) ; new_mem = replace_equiv_address_nv ( orig_mem , new_addr , false ) ; new_src = gen_rtx_UNSPEC ( target_mode , gen_rtvec ( 1 , src ) , UNSPEC_FUSION_P9 ) ; set = gen_rtx_SET ( new_mem , new_src ) ; clobber = gen_rtx_CLOBBER ( VOIDmode , tmp_reg ) ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set , clobber ) ) ; emit_insn ( insn ) ; return ; } </s>

During the peephole2 pass , adjust and expand the insns for an extended fusion store sequence . The operands are : operands [ 0 ] register set with addis operands [ 1 ] value set via addis operands [ 2 ] target D-form memory being stored to operands [ 3 ] register being stored This is similar to the fusion introduced with power8 , except it scales to both loads/stores and does not require the result register to be the same as the base register . At the moment , we only do this if register set with addis is dead .


<s> const AArch64RegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> int loongarch_load_store_insns ( rtx mem , rtx_insn * insn ) { machine_mode mode ; bool might_split_p ; rtx set ; gcc_assert ( MEM_P ( mem ) ) ; mode = GET_MODE ( mem ) ; might_split_p = GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ; if ( might_split_p ) { set = single_set ( insn ) ; if ( set && ! loongarch_split_move_insn_p ( SET_DEST ( set ) , SET_SRC ( set ) ) ) might_split_p = false ; } return loongarch_address_insns ( XEXP ( mem , 0 ) , mode , might_split_p ) ; } </s>

Return the number of instructions needed to implement INSN , given that it loads from or stores to MEM .


<s> static unsigned rs6000_add_stmt_cost ( void * data , int count , enum vect_cost_for_stmt kind , struct _stmt_vec_info * stmt_info , int misalign , enum vect_cost_model_location where ) { rs6000_cost_data * cost_data = ( rs6000_cost_data * ) data ; unsigned retval = 0 ; if ( flag_vect_cost_model ) { tree vectype = stmt_info ? stmt_vectype ( stmt_info ) : NULL_TREE ; int stmt_cost = rs6000_builtin_vectorization_cost ( kind , vectype , misalign ) ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( stmt_info ) ) count *= 50 ; retval = ( unsigned ) ( count * stmt_cost ) ; cost_data -> cost [ where ] += retval ; } return retval ; } </s>


<s> AArch64GenInstrInfo :: MachineOutlinerInstrType AArch64InstrInfo :: getOutliningType ( MachineInstr & MI ) const { MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; AArch64FunctionInfo * FuncInfo = MF -> getInfo < AArch64FunctionInfo > ( ) ; if ( FuncInfo -> getLOHRelated ( ) . count ( & MI ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . isDebugValue ( ) || MI . isIndirectDebugValue ( ) ) return MachineOutlinerInstrType :: Invisible ; if ( MI . isTerminator ( ) ) { if ( MI . getParent ( ) -> succ_empty ( ) ) return MachineOutlinerInstrType :: Legal ; return MachineOutlinerInstrType :: Illegal ; } if ( MI . isPosition ( ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . readsRegister ( AArch64 :: W30 , & getRegisterInfo ( ) ) || MI . modifiesRegister ( AArch64 :: W30 , & getRegisterInfo ( ) ) ) return MachineOutlinerInstrType :: Illegal ; for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return MachineOutlinerInstrType :: Illegal ; if ( MOP . isReg ( ) && getRegisterInfo ( ) . regsOverlap ( MOP . getReg ( ) , AArch64 :: LR ) ) return MachineOutlinerInstrType :: Illegal ; } if ( MI . modifiesRegister ( AArch64 :: SP , & RI ) || MI . readsRegister ( AArch64 :: SP , & RI ) ) { if ( MI . mayLoadOrStore ( ) ) { unsigned Base ; int64_t Offset ; unsigned DummyWidth ; if ( ! getMemOpBaseRegImmOfsWidth ( MI , Base , Offset , DummyWidth , & RI ) || Base != AArch64 :: SP ) return MachineOutlinerInstrType :: Illegal ; int64_t MinOffset , MaxOffset ; unsigned DummyScale ; getMemOpInfo ( MI . getOpcode ( ) , DummyScale , DummyWidth , MinOffset , MaxOffset ) ; if ( Offset + 16 < MinOffset || Offset + 16 > MaxOffset ) return MachineOutlinerInstrType :: Illegal ; return MachineOutlinerInstrType :: Legal ; } return MachineOutlinerInstrType :: Illegal ; } return MachineOutlinerInstrType :: Legal ; } </s>

Returns how or if MIT should be outlined .


<s> MCSection * DLXTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , unsigned & Align ) const { if ( isConstantInSmallSection ( DL , C ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: getSectionForConstant ( DL , Kind , C , Align ) ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> Function * AMDGPUIntrinsicInfo :: getDeclaration ( Module * M , unsigned IntrID , Type * * Tys , unsigned NumTys ) const { return getDeclaration ( M , IntrID , makeArrayRef ( Tys , NumTys ) ) ; } </s>

Create or insert an LLVM Function declaration for an intrinsic , and return it .


<s> rtx m32c_libcall_value ( enum machine_mode mode ) { if ( mode == DFmode ) { rtx rv ; rv = gen_rtx_PARALLEL ( mode , rtvec_alloc ( 4 ) ) ; XVECEXP ( rv , 0 , 0 ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( HImode , R0_REGNO ) , GEN_INT ( 0 ) ) ; XVECEXP ( rv , 0 , 1 ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( HImode , R1_REGNO ) , GEN_INT ( 2 ) ) ; XVECEXP ( rv , 0 , 2 ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( HImode , R2_REGNO ) , GEN_INT ( 4 ) ) ; XVECEXP ( rv , 0 , 3 ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( HImode , R3_REGNO ) , GEN_INT ( 6 ) ) ; return rv ; } if ( TARGET_A24 && GET_MODE_SIZE ( mode ) > 2 ) { rtx rv ; rv = gen_rtx_PARALLEL ( mode , rtvec_alloc ( 1 ) ) ; XVECEXP ( rv , 0 , 0 ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , R0_REGNO ) , GEN_INT ( 0 ) ) ; return rv ; } if ( GET_MODE_SIZE ( mode ) > 2 ) return gen_rtx_REG ( mode , MEM0_REGNO ) ; return gen_rtx_REG ( mode , R0_REGNO ) ; } </s>

Implements LIBCALL_VALUE . Most values are returned in $ r0 , or some combination of registers starting there ( r2r0 for longs , r3r1r2r0 for long long , r3r2r1r0 for doubles ) , except that that ABI currently does n't work because it ends up using all available general registers and gcc often ca n't compile it . So , instead , we return anything bigger than 16 bits in `` mem0 '' ( effectively , a memory location ) .


<s> const_iterator begin ( ) const { return Seq . begin ( ) ; } </s>


<s> static void bpf_init_builtins ( void ) { tree ullt = long_long_unsigned_type_node ; def_builtin ( "__builtin_bpf_load_byte" , BPF_BUILTIN_LOAD_BYTE , build_function_type_list ( ullt , ullt , 0 ) ) ; def_builtin ( "__builtin_bpf_load_half" , BPF_BUILTIN_LOAD_HALF , build_function_type_list ( ullt , ullt , 0 ) ) ; def_builtin ( "__builtin_bpf_load_word" , BPF_BUILTIN_LOAD_WORD , build_function_type_list ( ullt , ullt , 0 ) ) ; def_builtin ( "__builtin_preserve_access_index" , BPF_BUILTIN_PRESERVE_ACCESS_INDEX , build_function_type_list ( ptr_type_node , ptr_type_node , 0 ) ) ; } </s>

Define machine-specific built-in functions .


<s>
SDValue
MSP430TargetLowering
::
LowerReturn
(
SDValue
Chain
,
unsigned
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_MSP430
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
if
(
RVLocs
[
i
]
.
isRegLoc
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
Outs
[
i
]
.
Val
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
MSP430ISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
return
DAG
.
getNode
(
MSP430ISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s>
SDValue
X86TargetLowering
::
BuildSDIVPow2
(
SDNode
*
N
,
const
APInt
&
Divisor
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDNode
*
>
&
Created
)
const
{
AttributeList
Attr
=
DAG
.
getMachineFunction
(
)
.
getFunction
(
)
.
getAttributes
(
)
;
if
(
isIntDivCheap
(
N
->
getValueType
(
0
)
,
Attr
)
)
return
SDValue
(
N
,
0
)
;
assert
(
(
Divisor
.
isPowerOf2
(
)
||
(
Divisor
)
.
isPowerOf2
(
)
)
&&
"Unexpected divisor!"
)
;
if
(
!
Subtarget
.
hasCMov
(
)
)
return
SDValue
(
)
;
EVT
VT
=
N
->
getValueType
(
0
)
;
if
(
VT
!=
MVT
::
i16
&&
VT
!=
MVT
::
i32
&&
!
(
Subtarget
.
is64Bit
(
)
&&
VT
==
MVT
::
i64
)
)
return
SDValue
(
)
;
unsigned
Lg2
=
Divisor
.
countTrailingZeros
(
)
;
if
(
Lg2
==
1
)
return
SDValue
(
)
;
SDLoc
DL
(
N
)
;
SDValue
N0
=
N
->
getOperand
(
0
)
;
SDValue
Zero
=
DAG
.
getConstant
(
0
,
DL
,
VT
)
;
SDValue
Pow2MinusOne
=
DAG
.
getConstant
(
(
1ULL
<<
Lg2
)
1
,
DL
,
VT
)
;
SDValue
Cmp
=
DAG
.
getSetCC
(
DL
,
MVT
::
i8
,
N0
,
Zero
,
ISD
::
SETLT
)
;
SDValue
Add
=
DAG
.
getNode
(
ISD
::
ADD
,
DL
,
VT
,
N0
,
Pow2MinusOne
)
;
SDValue
CMov
=
DAG
.
getNode
(
ISD
::
SELECT
,
DL
,
VT
,
Cmp
,
Add
,
N0
)
;
Created
.
push_back
(
Cmp
.
getNode
(
)
)
;
Created
.
push_back
(
Add
.
getNode
(
)
)
;
Created
.
push_back
(
CMov
.
getNode
(
)
)
;
SDValue
SRA
=
DAG
.
getNode
(
ISD
::
SRA
,
DL
,
VT
,
CMov
,
DAG
.
getConstant
(
Lg2
,
DL
,
MVT
::
i64
)
)
;
if
(
Divisor
.
isNonNegative
(
)
)
return
SRA
;
Created
.
push_back
(
SRA
.
getNode
(
)
)
;
return
DAG
.
getNode
(
ISD
::
SUB
,
DL
,
VT
,
Zero
,
SRA
)
;
}
</s>

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators .


<s> unsigned SNESMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; if ( MO . isFPImm ( ) ) return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( 32 ) . getLimitedValue ( ) ) ; assert ( MO . isExpr ( ) ) ; return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> static bool rs6000_is_opaque_type ( tree type ) { return ( type == opaque_V2SI_type_node || type == opaque_V2SF_type_node || type == opaque_p_V2SI_type_node || type == opaque_V4SI_type_node ) ; } </s>

Return true if TYPE is a SPE or AltiVec opaque type .


<s> void WebAssemblyPassConfig :: addIRPasses ( ) { addPass ( new CoalesceFeaturesAndStripAtomics ( & getWebAssemblyTargetMachine ( ) ) ) ; addPass ( createAtomicExpandPass ( ) ) ; addPass ( createWebAssemblyAddMissingPrototypes ( ) ) ; addPass ( createWebAssemblyLowerGlobalDtors ( ) ) ; addPass ( createWebAssemblyFixFunctionBitcasts ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createWebAssemblyOptimizeReturned ( ) ) ; if ( ! EnableEmException && TM -> Options . ExceptionModel == ExceptionHandling :: None ) { addPass ( createLowerInvokePass ( ) ) ; addPass ( createUnreachableBlockEliminationPass ( ) ) ; } if ( EnableEmException || EnableEmSjLj ) addPass ( createWebAssemblyLowerEmscriptenEHSjLj ( EnableEmException , EnableEmSjLj ) ) ; addPass ( createIndirectBrExpandPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AsmPrinter :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> rtx frv_find_base_term ( rtx x ) { struct frv_unspec unspec ; if ( frv_const_unspec_p ( x , & unspec ) && frv_small_data_reloc_p ( unspec . symbol , unspec . reloc ) ) return plus_constant ( unspec . symbol , unspec . offset ) ; return x ; } </s>

Implement FIND_BASE_TERM . See whether ORIG_X represents # gprel12 ( foo ) or # gotoff12 ( foo ) for some small data symbol foo . If so , return foo , otherwise return ORIG_X .


<s>
bool
X86InstrInfo
::
preservesZeroValueInReg
(
const
MachineInstr
*
MI
,
const
Register
NullValueReg
,
const
TargetRegisterInfo
*
TRI
)
const
{
if
(
!
MI
->
modifiesRegister
(
NullValueReg
,
TRI
)
)
return
true
;
switch
(
MI
->
getOpcode
(
)
)
{
case
X86
::
SHR64ri
:
case
X86
::
SHR32ri
:
case
X86
::
SHL64ri
:
case
X86
::
SHL32ri
:
assert
(
MI
->
getOperand
(
0
)
.
isDef
(
)
&&
MI
->
getOperand
(
1
)
.
isUse
(
)
&&
"expected for shift opcode!"
)
;
return
MI
->
getOperand
(
0
)
.
getReg
(
)
==
NullValueReg
&&
MI
->
getOperand
(
1
)
.
getReg
(
)
==
NullValueReg
;
case
X86
::
MOV32rr
:
return
llvm
::
all_of
(
MI
->
operands
(
)
,
[
&
]
(
const
MachineOperand
&
MO
)
{
return
TRI
->
isSubRegisterEq
(
NullValueReg
,
MO
.
getReg
(
)
)
;
}
)
;
default
:
return
false
;
}
llvm_unreachable
(
"Should be handled above!"
)
;
}
</s>

Returns true if MI 's Def is NullValueReg , and the MI does not change the Zero value .


<s> Register P2RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return P2 :: PTRA ; } </s>


Return an array that contains the bitmask target flag values and their names .

PowerPC PPC PPC "ppc-plt" "ppc-pic" "ppc-pcrel"


<s> ScheduleHazardRecognizer * PPCInstrInfo :: CreateTargetHazardRecognizer ( const TargetSubtargetInfo * STI , const ScheduleDAG * DAG ) const { unsigned Directive = static_cast < const PPCSubtarget * > ( STI ) -> getMcpu ( ) ; if ( Directive == PPC :: MCPU_440 || Directive == PPC :: MCPU_A2 || Directive == PPC :: MCPU_E500mc || Directive == PPC :: MCPU_E5500 ) { const InstrItineraryData * II = static_cast < const PPCSubtarget * > ( STI ) -> getInstrItineraryData ( ) ; return new ScoreboardHazardRecognizer ( II , DAG ) ; } return TargetInstrInfo :: CreateTargetHazardRecognizer ( STI , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT LHSTy ) const override { return MVT :: i8 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> static enum dispatch_group get_mem_group ( rtx_insn * insn ) { enum attr_memory memory ; if ( INSN_CODE ( insn ) < 0 ) return disp_no_group ; memory = get_attr_memory ( insn ) ; if ( memory == MEMORY_STORE ) return disp_store ; if ( memory == MEMORY_LOAD ) return disp_load ; if ( memory == MEMORY_BOTH ) return disp_load_store ; return disp_no_group ; } </s>


<s> void neon_split_vcombine ( rtx operands [ 3 ] ) { unsigned int dest = REGNO ( operands [ 0 ] ) ; unsigned int src1 = REGNO ( operands [ 1 ] ) ; unsigned int src2 = REGNO ( operands [ 2 ] ) ; machine_mode halfmode = GET_MODE ( operands [ 1 ] ) ; unsigned int halfregs = HARD_REGNO_NREGS ( src1 , halfmode ) ; rtx destlo , desthi ; if ( src1 == dest && src2 == dest + halfregs ) { emit_note ( NOTE_INSN_DELETED ) ; return ; } destlo = gen_rtx_REG_offset ( operands [ 0 ] , halfmode , dest , 0 ) ; desthi = gen_rtx_REG_offset ( operands [ 0 ] , halfmode , dest + halfregs , GET_MODE_SIZE ( halfmode ) ) ; if ( src2 == dest && src1 == dest + halfregs ) { rtx x = gen_rtx_SET ( destlo , operands [ 1 ] ) ; rtx y = gen_rtx_SET ( desthi , operands [ 2 ] ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , x , y ) ) ) ; return ; } if ( ! reg_overlap_mentioned_p ( operands [ 2 ] , destlo ) ) { if ( src1 != dest ) emit_move_insn ( destlo , operands [ 1 ] ) ; if ( src2 != dest + halfregs ) emit_move_insn ( desthi , operands [ 2 ] ) ; } else { if ( src2 != dest + halfregs ) emit_move_insn ( desthi , operands [ 2 ] ) ; if ( src1 != dest ) emit_move_insn ( destlo , operands [ 1 ] ) ; } } </s>

Split operands into moves from op [ 1 ] + op [ 2 ] into op [ 0 ] .


<s> void EmitInstruction ( uint32_t Val , raw_ostream & OS ) const { for ( unsigned i = 0 ; i != 4 ; ++ i ) { EmitByte ( Val & 0xff , OS ) ; Val >>= 8 ; } } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> const char * output_reload_inhi ( rtx * op , rtx clobber_reg , int * plen ) { output_reload_in_const ( op , clobber_reg , plen , false ) ; return "" ; } </s>

Reload the constant OP [ 1 ] into the HI register OP [ 0 ] . CLOBBER_REG is a QI clobber reg needed to move vast majority of consts into a NO_LD_REGS register . If CLOBBER_REG is NULL_RTX we either do n't need a clobber reg or have to cook one up . PLEN == NULL : Output instructions . PLEN ! = NULL : Output nothing . Set * PLEN to number of words occupied by the insns printed . Return `` '' .


<s> void LC3InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( LC3 :: STR ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> MachineInstr * X86InstrInfo :: optimizeLoadInstr ( MachineInstr & MI , const MachineRegisterInfo * MRI , unsigned & FoldAsLoadDefReg , MachineInstr * & DefMI ) const { DefMI = MRI -> getVRegDef ( FoldAsLoadDefReg ) ; assert ( DefMI ) ; bool SawStore = false ; if ( ! DefMI -> isSafeToMove ( nullptr , SawStore ) ) return nullptr ; SmallVector < unsigned , 1 > SrcOperandIds ; for ( unsigned i = 0 , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( Reg != FoldAsLoadDefReg ) continue ; if ( MO . getSubReg ( ) || MO . isDef ( ) ) return nullptr ; SrcOperandIds . push_back ( i ) ; } if ( SrcOperandIds . empty ( ) ) return nullptr ; if ( MachineInstr * FoldMI = foldMemoryOperand ( MI , SrcOperandIds , * DefMI ) ) { FoldAsLoadDefReg = 0 ; return FoldMI ; } return nullptr ; } </s>

optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use .


<s> bool aarch64_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( GET_MODE_CLASS ( mode1 ) == GET_MODE_CLASS ( mode2 ) ) return true ; if ( aarch64_vector_mode_p ( mode1 ) && aarch64_vector_mode_p ( mode2 ) ) return true ; if ( aarch64_vector_mode_supported_p ( mode1 ) || aarch64_vector_mode_supported_p ( mode2 ) ) return true ; return false ; } </s>

Implement MODES_TIEABLE_P . In principle we should always return true . However due to issues with register allocation it is preferable to avoid tieing integer scalar and FP scalar modes . Executing integer operations in general registers is better than treating them as scalar vector operations . This reduces latency and avoids redundant int < - > FP moves . So tie modes if they are either the same class , or vector modes with other vector modes , vector structs or any scalar mode .


<s> bool MOSInsertCopies :: runOnMachineFunction ( MachineFunction & MF ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { MachineBasicBlock :: iterator Next ; for ( auto I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; I = Next ) { Next = std :: next ( I ) ; const TargetRegisterClass * WideRC ; switch ( I -> getOpcode ( ) ) { default : continue ; case MOS :: ASL : case MOS :: LSR : case MOS :: ROL : case MOS :: ROR : WideRC = & MOS :: AImag8RegClass ; break ; case MOS :: IncMB : case MOS :: DecMB : WideRC = & MOS :: Anyi8RegClass ; break ; } for ( unsigned Idx = 0 , EndIdx = I -> getNumExplicitDefs ( ) ; Idx != EndIdx ; ++ Idx ) { MachineOperand & DstOp = I -> getOperand ( Idx ) ; if ( ! DstOp . isReg ( ) || ! DstOp . isTied ( ) || ! DstOp . getReg ( ) . isVirtual ( ) ) continue ; MachineOperand & SrcOp = I -> getOperand ( I -> findTiedOperandIdx ( Idx ) ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( SrcOp . getReg ( ) ) ; const TargetRegisterClass * DstRC = MRI . getRegClass ( DstOp . getReg ( ) ) ; if ( ! SrcRC -> hasSuperClassEq ( WideRC ) || ! DstRC -> hasSuperClassEq ( WideRC ) ) continue ; if ( SrcRC == & MOS :: Imag8RegClass && DstRC == & MOS :: Imag8RegClass ) continue ; if ( SrcRC != WideRC ) { Changed = true ; MachineIRBuilder Builder ( MBB , I ) ; SrcOp . setReg ( Builder . buildCopy ( WideRC , SrcOp ) . getReg ( 0 ) ) ; } if ( DstRC != WideRC ) { Changed = true ; Register NewDst = MRI . createVirtualRegister ( WideRC ) ; MachineIRBuilder Builder ( MBB , Next ) ; Builder . buildCopy ( DstOp , NewDst ) ; DstOp . setReg ( NewDst ) ; } } } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> const MipsFrameLowering * MipsFrameLowering :: create ( const MipsSubtarget & ST ) { if ( ST . inMips16Mode ( ) ) return llvm :: createMips16FrameLowering ( ST ) ; return llvm :: createMipsSEFrameLowering ( ST ) ; } </s>


<s> TargetLowering :: AtomicExpansionKind PPCTargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( EnableQuadwordAtomics && Subtarget . hasQuadwordAtomics ( ) && Size == 128 ) return AtomicExpansionKind :: MaskedIntrinsic ; return TargetLowering :: shouldExpandAtomicRMWInIR ( AI ) ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> void vms_c_register_includes ( const char * sysroot , const char * iprefix ATTRIBUTE_UNUSED , int stdinc ) { static const char dir_separator_str [ ] = { DIR_SEPARATOR , 0 } ; struct cpp_dir * dir ; if ( ! stdinc ) return ; for ( dir = get_added_cpp_dirs ( SYSTEM ) ; dir != NULL ; dir = dir -> next ) { const char * const * lib ; for ( lib = vms_std_modules ; * lib != NULL ; lib ++ ) { char * path ; struct stat st ; if ( sysroot != NULL ) path = concat ( sysroot , dir -> name , dir_separator_str , * lib , NULL ) ; else path = concat ( dir -> name , dir_separator_str , * lib , NULL ) ; if ( stat ( path , & st ) == 0 && S_ISDIR ( st . st_mode ) ) { cpp_dir * p ; p = XNEW ( cpp_dir ) ; p -> next = NULL ; p -> name = path ; p -> sysp = 1 ; p -> construct = vms_construct_include_filename ; p -> user_supplied_p = 0 ; add_cpp_dir_path ( p , SYSTEM ) ; } else free ( path ) ; } } } </s>

Find include modules in the include path .


<s> MachineBasicBlock * SITargetLowering :: EmitInstrWithCustomInserter ( MachineInstr & MI , MachineBasicBlock * BB ) const { switch ( MI . getOpcode ( ) ) { case AMDGPU :: SI_INIT_M0 : { const SIInstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; BuildMI ( * BB , MI . getIterator ( ) , MI . getDebugLoc ( ) , TII -> get ( AMDGPU :: S_MOV_B32 ) , AMDGPU :: M0 ) . addOperand ( MI . getOperand ( 0 ) ) ; MI . eraseFromParent ( ) ; return BB ; } case AMDGPU :: GET_GROUPSTATICSIZE : { const SIInstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; MachineFunction * MF = BB -> getParent ( ) ; SIMachineFunctionInfo * MFI = MF -> getInfo < SIMachineFunctionInfo > ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; BuildMI ( * BB , MI , DL , TII -> get ( AMDGPU :: S_MOVK_I32 ) ) . addOperand ( MI . getOperand ( 0 ) ) . addImm ( MFI -> LDSSize ) ; MI . eraseFromParent ( ) ; return BB ; } case AMDGPU :: SI_INDIRECT_SRC_V1 : case AMDGPU :: SI_INDIRECT_SRC_V2 : case AMDGPU :: SI_INDIRECT_SRC_V4 : case AMDGPU :: SI_INDIRECT_SRC_V8 : case AMDGPU :: SI_INDIRECT_SRC_V16 : return emitIndirectSrc ( MI , * BB , getSubtarget ( ) -> getInstrInfo ( ) ) ; case AMDGPU :: SI_INDIRECT_DST_V1 : case AMDGPU :: SI_INDIRECT_DST_V2 : case AMDGPU :: SI_INDIRECT_DST_V4 : case AMDGPU :: SI_INDIRECT_DST_V8 : case AMDGPU :: SI_INDIRECT_DST_V16 : return emitIndirectDst ( MI , * BB , getSubtarget ( ) -> getInstrInfo ( ) ) ; case AMDGPU :: SI_KILL : return splitKillBlock ( MI , BB ) ; default : return AMDGPUTargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; } } </s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> void sparc_flat_expand_prologue ( void ) { HOST_WIDE_INT size ; rtx_insn * insn ; sparc_leaf_function_p = optimize > 0 && crtl -> is_leaf ; size = sparc_compute_frame_size ( get_frame_size ( ) , sparc_leaf_function_p ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = size ; if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK || flag_stack_clash_protection ) { if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { if ( size > PROBE_INTERVAL && size > get_stack_check_protect ( ) ) sparc_emit_probe_stack_range ( get_stack_check_protect ( ) , size - get_stack_check_protect ( ) ) ; } else if ( size > 0 ) sparc_emit_probe_stack_range ( get_stack_check_protect ( ) , size ) ; } if ( sparc_save_local_in_regs_p ) emit_save_or_restore_local_in_regs ( stack_pointer_rtx , SPARC_STACK_BIAS , SORR_SAVE ) ; if ( size == 0 ) ; else { rtx size_int_rtx , size_rtx ; size_rtx = size_int_rtx = GEN_INT ( - size ) ; if ( size <= 4096 ) insn = emit_insn ( gen_stack_pointer_inc ( size_int_rtx ) ) ; else if ( size <= 8192 && ! frame_pointer_needed ) { insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - 4096 ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( 4096 - size ) ) ) ; } else { size_rtx = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( size_rtx , size_int_rtx ) ; insn = emit_insn ( gen_stack_pointer_inc ( size_rtx ) ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_stack_pointer_inc ( size_int_rtx ) ) ; } RTX_FRAME_RELATED_P ( insn ) = 1 ; emit_insn ( gen_blockage ( ) ) ; if ( frame_pointer_needed ) { insn = emit_insn ( gen_rtx_SET ( hard_frame_pointer_rtx , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , size_rtx ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( hard_frame_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , size ) ) ) ; } if ( return_addr_reg_needed_p ( sparc_leaf_function_p ) ) { rtx o7 = gen_rtx_REG ( Pmode , INCOMING_RETURN_ADDR_REGNUM ) ; rtx i7 = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; insn = emit_move_insn ( i7 , o7 ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_REGISTER , gen_rtx_SET ( i7 , o7 ) ) ; emit_use ( i7 ) ; } } if ( frame_pointer_needed ) { sparc_frame_base_reg = hard_frame_pointer_rtx ; sparc_frame_base_offset = SPARC_STACK_BIAS ; } else { sparc_frame_base_reg = stack_pointer_rtx ; sparc_frame_base_offset = size + SPARC_STACK_BIAS ; } if ( sparc_n_global_fp_regs > 0 ) emit_save_or_restore_global_fp_regs ( sparc_frame_base_reg , sparc_frame_base_offset - sparc_apparent_frame_size , SORR_SAVE ) ; sparc_prologue_data_valid_p = true ; } </s>

Expand the function prologue . The prologue is responsible for reserving storage for the frame , saving the call-saved registers and loading the GOT register if needed .


<s> rtx s390_function_arg ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int named ATTRIBUTE_UNUSED ) { if ( s390_function_arg_float ( mode , type ) ) { if ( cum -> fprs + 1 > FP_ARG_NUM_REG ) return 0 ; else return gen_rtx_REG ( mode , cum -> fprs + 16 ) ; } else if ( s390_function_arg_integer ( mode , type ) ) { int size = s390_function_arg_size ( mode , type ) ; int n_gprs = ( size + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; if ( cum -> gprs + n_gprs > GP_ARG_NUM_REG ) return 0 ; else return gen_rtx_REG ( mode , cum -> gprs + 2 ) ; } else if ( type == void_type_node ) return const0_rtx ; gcc_unreachable ( ) ; } </s>

Define where to put the arguments to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . On S/390 , we use general purpose registers 2 through 6 to pass integer , pointer , and certain structure arguments , and floating point registers 0 and 2 ( 0 , 2 , 4 , and 6 on 64-bit ) to pass floating point arguments . All remaining arguments are pushed to the stack .


<s> static void ix86_option_override ( void ) { opt_pass * pass_insert_vzeroupper = make_pass_insert_vzeroupper ( g ) ; struct register_pass_info insert_vzeroupper_info = { pass_insert_vzeroupper , "reload" , 1 , PASS_POS_INSERT_AFTER } ; ix86_option_override_internal ( true , & global_options , & global_options_set ) ; register_pass ( & insert_vzeroupper_info ) ; } </s>

Implement the TARGET_OPTION_OVERRIDE hook .


<s>
bool
X86InstrInfo
::
expandPostRAPseudo
(
MachineBasicBlock
::
iterator
MI
)
const
{
bool
HasAVX
=
TM
.
getSubtarget
<
X86Subtarget
>
(
)
.
hasAVX
(
)
;
MachineInstrBuilder
MIB
(
*
MI
->
getParent
(
)
->
getParent
(
)
,
MI
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
X86
::
SETB_C8r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB8rr
)
)
;
case
X86
::
SETB_C16r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB16rr
)
)
;
case
X86
::
SETB_C32r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB32rr
)
)
;
case
X86
::
SETB_C64r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB64rr
)
)
;
case
X86
::
V_SET0
:
case
X86
::
FsFLD0SS
:
case
X86
::
FsFLD0SD
:
return
Expand2AddrUndef
(
MIB
,
get
(
HasAVX
X86
::
VXORPSrr
:
X86
::
XORPSrr
)
)
;
case
X86
::
AVX_SET0
:
assert
(
HasAVX
&&
"AVX not supported"
)
;
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VXORPSYrr
)
)
;
case
X86
::
V_SETALLONES
:
return
Expand2AddrUndef
(
MIB
,
get
(
HasAVX
X86
::
VPCMPEQDrr
:
X86
::
PCMPEQDrr
)
)
;
case
X86
::
AVX2_SETALLONES
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VPCMPEQDYrr
)
)
;
case
X86
::
TEST8ri_NOREX
:
MI
->
setDesc
(
get
(
X86
::
TEST8ri
)
)
;
return
true
;
}
return
false
;
}
</s>

This function is called for all pseudo instructions that remain after register allocation .


<s> bool MipsSERegisterInfo :: requiresFrameIndexScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> void WebAssemblyTTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP , OptimizationRemarkEmitter * ORE ) const { for ( BasicBlock * BB : L -> blocks ( ) ) for ( Instruction & I : * BB ) if ( isa < CallInst > ( I ) || isa < InvokeInst > ( I ) ) if ( const Function * F = cast < CallBase > ( I ) . getCalledFunction ( ) ) if ( isLoweredToCall ( F ) ) return ; UP . Partial = UP . Runtime = UP . UpperBound = true ; UP . PartialThreshold = 30 ; UP . OptSizeThreshold = 0 ; UP . PartialOptSizeThreshold = 0 ; UP . BEInsns = 2 ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> bool PPCTTIImpl :: isNumRegsMajorCostOfLSR ( ) { return false ; } </s>

Return true if LSR major cost is number of registers .


<s> TargetLowering :: ConstraintWeight AArch64TargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'x' : case 'w' : case 'y' : if ( type -> isFloatingPointTy ( ) || type -> isVectorTy ( ) ) weight = CW_Register ; break ; case 'z' : weight = CW_Constant ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> const char * XtensaTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { return "unknown" ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static int sh_register_move_cost ( machine_mode mode , reg_class_t srcclass , reg_class_t dstclass ) { if ( dstclass == T_REGS || dstclass == PR_REGS ) return 10 ; if ( dstclass == MAC_REGS && srcclass == MAC_REGS ) return 4 ; if ( mode == SImode && TARGET_FMOVD && REGCLASS_HAS_FP_REG ( srcclass ) && REGCLASS_HAS_FP_REG ( dstclass ) ) return 4 ; if ( REGCLASS_HAS_FP_REG ( dstclass ) && srcclass == T_REGS ) return ( ( TARGET_HARD_SH4 && ! optimize_size ) ? 10 : 7 ) ; if ( ( REGCLASS_HAS_FP_REG ( dstclass ) && srcclass == MAC_REGS ) || ( dstclass == MAC_REGS && REGCLASS_HAS_FP_REG ( srcclass ) ) ) return 9 ; if ( ( REGCLASS_HAS_FP_REG ( dstclass ) && REGCLASS_HAS_GENERAL_REG ( srcclass ) ) || ( REGCLASS_HAS_GENERAL_REG ( dstclass ) && REGCLASS_HAS_FP_REG ( srcclass ) ) ) { int addend = ( mode == Pmode ) ? 40 : 0 ; return ( ( TARGET_FMOVD ? 8 : 12 ) + addend ) * ( ( GET_MODE_SIZE ( mode ) + 7 ) / 8U ) ; } if ( ( dstclass == FPUL_REGS && REGCLASS_HAS_GENERAL_REG ( srcclass ) ) || ( srcclass == FPUL_REGS && REGCLASS_HAS_GENERAL_REG ( dstclass ) ) ) return 5 ; if ( ( dstclass == FPUL_REGS && ( srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS ) ) || ( srcclass == FPUL_REGS && ( dstclass == PR_REGS || dstclass == MAC_REGS ) ) ) return 7 ; if ( ( srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG ( dstclass ) ) || ( dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG ( srcclass ) ) ) return 4 ; if ( TARGET_FMOVD && ! REGCLASS_HAS_GENERAL_REG ( srcclass ) && ! REGCLASS_HAS_GENERAL_REG ( dstclass ) ) return 2 * ( ( GET_MODE_SIZE ( mode ) + 7 ) / 8U ) ; if ( ( ( dstclass == FP_REGS || dstclass == DF_REGS ) && ( srcclass == PR_REGS ) ) || ( ( srcclass == FP_REGS || srcclass == DF_REGS ) && ( dstclass == PR_REGS ) ) ) return 7 ; return 2 * ( ( GET_MODE_SIZE ( mode ) + 3 ) / 4U ) ; } </s>

If SECONDARY * _RELOAD_CLASS says something about the src/dst pair , regclass uses this information . Hence , the general register < - > floating point register information here is not used for SFmode .


<s> bool AMDGPUAnnotateUniformValues :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; DA = & getAnalysis < LegacyDivergenceAnalysis > ( ) ; MSSA = & getAnalysis < MemorySSAWrapperPass > ( ) . getMSSA ( ) ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; isEntryFunc = AMDGPU :: isEntryFunctionCC ( F . getCallingConv ( ) ) ; visit ( F ) ; noClobberClones . clear ( ) ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> unsigned PPCFastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( DL , C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return PPCMaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return PPCMaterializeGV ( GV , VT ) ; else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( C ) ) return PPCMaterializeInt ( CI , VT , VT != MVT :: i1 ) ; return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s> unsigned MBlazeInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == MBlaze :: SWI ) { if ( ( MI -> getOperand ( 1 ) . isFI ( ) ) && ( MI -> getOperand ( 2 ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( 2 ) ) ) ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> const char * i386_pe_strip_name_encoding_full ( const char * str ) { const char * p ; const char * name = default_strip_name_encoding ( str ) ; if ( * name == '@' ) name ++ ; p = strchr ( name , '@' ) ; if ( p ) return ggc_alloc_string ( name , p - name ) ; return name ; } </s>

Also strip the fastcall prefix and stdcall suffix .


<s> bool MipsFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || TRI -> needsStackRealignment ( MF ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> AArch64Subtarget :: AArch64Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasFPARMv8 ( false ) , HasNEON ( false ) , HasCrypto ( false ) , HasCRC ( false ) , HasZeroCycleRegMove ( false ) , HasZeroCycleZeroing ( false ) , CPUString ( CPU ) , TargetTriple ( TT ) , DL ( isTargetMachO ( ) ? "e-m:o-i64:64-i128:128-n32:64-S128" : ( LittleEndian ? "e-m:e-i64:64-i128:128-n32:64-S128" : "E-m:e-i64:64-i128:128-n32:64-S128" ) ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS ) ) , TSInfo ( & DL ) , TLInfo ( TM ) { } </s>

This constructor initializes the data members to match that of the specified triple .


<s> bool SystemZPassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createSystemZElimComparePass ( getSystemZTargetMachine ( ) ) ) ; addPass ( createSystemZLongBranchPass ( getSystemZTargetMachine ( ) ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ


<s> bool ARMConstantPoolSymbol :: hasSameValue ( ARMConstantPoolValue * ACPV ) { const ARMConstantPoolSymbol * ACPS = dyn_cast < ARMConstantPoolSymbol > ( ACPV ) ; return ACPS && CPV_streq ( ACPS -> S , S ) && ARMConstantPoolValue :: hasSameValue ( ACPV ) ; } </s>

hasSameValue - Return true if this ARM constpool value can share the same constantpool entry as another ARM constpool value .


<s> static void sparc_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; tree type = arg . type ; machine_mode mode = arg . mode ; int regno , padding ; function_arg_slotno ( cum , mode , type , arg . named , false , & regno , & padding ) ; cum -> words += padding ; if ( TARGET_ARCH32 ) cum -> words += CEIL_NWORDS ( GET_MODE_SIZE ( mode ) ) ; else { if ( type && ( AGGREGATE_TYPE_P ( type ) || VECTOR_FLOAT_TYPE_P ( type ) ) ) { const int size = int_size_in_bytes ( type ) ; if ( size <= 0 ) cum -> words ++ ; else cum -> words += CEIL_NWORDS ( size ) ; } else cum -> words += CEIL_NWORDS ( GET_MODE_SIZE ( mode ) ) ; } } </s>

Handle the TARGET_FUNCTION_ARG_ADVANCE hook . Update the data in CUM to advance over an argument of mode MODE and data type TYPE . TYPE is null for libcalls where that information may not be available .


<s> static rtx tilepro_legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , machine_mode mode ) { if ( GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD && symbolic_operand ( x , Pmode ) && tilepro_tls_referenced_p ( x ) ) { return tilepro_legitimize_tls_address ( x ) ; } else if ( flag_pic ) { return tilepro_legitimize_pic_address ( x , mode , 0 ) ; } else return x ; } </s>


<s> const TargetRegisterClass * PPCRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; if ( Subtarget . hasVSX ( ) ) { if ( RC == & PPC :: F8RCRegClass ) return & PPC :: VSFRCRegClass ; else if ( RC == & PPC :: VRRCRegClass ) return & PPC :: VSRCRegClass ; } return TargetRegisterInfo :: getLargestLegalSuperClass ( RC , MF ) ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .

PowerPC PPC PPC PPC PPC::F8RCRegClass PPC::VSFRCRegClass PPC::VRRCRegClass PPC::VSRCRegClass


<s> unsigned SystemZTTIImpl :: getIntImmCost ( Intrinsic :: ID IID , unsigned Idx , const APInt & Imm , Type * Ty ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; if ( BitSize > 64 ) return TTI :: TCC_Free ; switch ( IID ) { default : return TTI :: TCC_Free ; case Intrinsic :: sadd_with_overflow : case Intrinsic :: uadd_with_overflow : case Intrinsic :: ssub_with_overflow : case Intrinsic :: usub_with_overflow : if ( Idx == 1 && Imm . getBitWidth ( ) <= 64 ) { if ( isUInt < 32 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( isUInt < 32 > ( - Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; } break ; case Intrinsic :: smul_with_overflow : case Intrinsic :: umul_with_overflow : if ( Idx == 1 && Imm . getBitWidth ( ) <= 64 ) { if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; } break ; case Intrinsic :: experimental_stackmap : if ( ( Idx < 2 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; case Intrinsic :: experimental_patchpoint_void : case Intrinsic :: experimental_patchpoint_i64 : if ( ( Idx < 4 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; } return SystemZTTIImpl :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> void BPFAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel , MCContext & Ctx ) const { if ( Fixup . getKind ( ) == FK_SecRel_4 || Fixup . getKind ( ) == FK_SecRel_8 ) { assert ( Value == 0 ) ; } else if ( Fixup . getKind ( ) == FK_Data_4 || Fixup . getKind ( ) == FK_Data_8 ) { unsigned Size = Fixup . getKind ( ) == FK_Data_4 ? 4 : 8 ; for ( unsigned i = 0 ; i != Size ; ++ i ) { unsigned Idx = IsLittleEndian ? i : Size - i - 1 ; Data [ Fixup . getOffset ( ) + Idx ] = uint8_t ( Value >> ( i * 8 ) ) ; } } else { assert ( Fixup . getKind ( ) == FK_PCRel_2 ) ; Value = ( uint16_t ) ( ( Value - 8 ) / 8 ) ; if ( IsLittleEndian ) { Data [ Fixup . getOffset ( ) + 2 ] = Value & 0xFF ; Data [ Fixup . getOffset ( ) + 3 ] = Value >> 8 ; } else { Data [ Fixup . getOffset ( ) + 2 ] = Value >> 8 ; Data [ Fixup . getOffset ( ) + 3 ] = Value & 0xFF ; } } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> SMLoc getEndLoc ( ) const { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


";;\tatom sched_reorder: put %d insn on top\n"

";;\tslm sched_reorder: swap %d and %d insns\n"

Perform possible reodering of ready list for Atom/Silvermont only . Return issue rate .


<s> static bool unspec_caller_rtx_p ( rtx pat ) { rtx base , offset ; int i ; split_const ( pat , & base , & offset ) ; if ( GET_CODE ( base ) == UNSPEC ) { if ( XINT ( base , 1 ) == UNSPEC_CALLER ) return true ; for ( i = 0 ; i < XVECLEN ( base , 0 ) ; i ++ ) if ( unspec_caller_rtx_p ( XVECEXP ( base , 0 , i ) ) ) return true ; } return false ; } </s>

Check if PAT includes UNSPEC_CALLER unspec pattern .


<s> Register ( ) { ARMTargetMachine :: registerAsmPrinter ( createARMCodePrinterPass ) ; } </s>


"Only integer vectors are supported here"

Return a SCEV for the constant 0 of a specific type .


<s> bool microblaze_expand_block_move ( rtx dest , rtx src , rtx length , rtx align_rtx ) { if ( GET_CODE ( length ) == CONST_INT ) { HOST_WIDE_INT bytes = INTVAL ( length ) ; int align = INTVAL ( align_rtx ) ; if ( align > UNITS_PER_WORD ) { align = UNITS_PER_WORD ; } else if ( align < UNITS_PER_WORD ) { if ( INTVAL ( length ) <= MAX_MOVE_BYTES ) { move_by_pieces ( dest , src , bytes , align , 0 ) ; return true ; } else return false ; } if ( INTVAL ( length ) <= 2 * MAX_MOVE_BYTES ) { microblaze_block_move_straight ( dest , src , INTVAL ( length ) ) ; return true ; } else if ( optimize ) { microblaze_block_move_loop ( dest , src , INTVAL ( length ) ) ; return true ; } } return false ; } </s>


<s> const HexagonRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


"%qE attribute only applies to variables"

Handle a `` shared '' attribute ; arguments as in struct attribute_spec.handler .


<s> static void sparc_add_gc_roots ( ) { ggc_add_rtx_root ( & sparc_compare_op0 , 1 ) ; ggc_add_rtx_root ( & sparc_compare_op1 , 1 ) ; ggc_add_rtx_root ( & global_offset_table , 1 ) ; ggc_add_rtx_root ( & get_pc_symbol , 1 ) ; ggc_add_rtx_root ( & sparc_addr_diff_list , 1 ) ; ggc_add_rtx_root ( & sparc_addr_list , 1 ) ; ggc_add_root ( ultra_pipe_hist , ARRAY_SIZE ( ultra_pipe_hist ) , sizeof ( ultra_pipe_hist [ 0 ] ) , & mark_ultrasparc_pipeline_state ) ; } </s>

Called to register all of our global variables with the garbage collector .


<s> const unsigned * PPCRegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { if ( Subtarget . isDarwinABI ( ) ) return Subtarget . isPPC64 ( ) ? CSR_Darwin64_RegMask : CSR_Darwin32_RegMask ; return Subtarget . isPPC64 ( ) ? CSR_SVR464_RegMask : CSR_SVR432_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool HexagonHazardRecognizer :: ShouldPreferAnother ( SUnit * SU ) { if ( PrefVectorStoreNew != nullptr && PrefVectorStoreNew != SU ) return true ; if ( UsesLoad && SU -> isInstr ( ) && SU -> getInstr ( ) -> mayLoad ( ) ) return true ; return UsesDotCur && ( ( SU == UsesDotCur ) ^ ( DotCurPNum == ( int ) PacketNum ) ) ; } </s>

ShouldPreferAnother - This callback may be invoked if getHazardType returns NoHazard .


<s> const char * HexagonTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case HexagonISD :: CONST32 : return "HexagonISD::CONST32" ; case HexagonISD :: CONST32_GP : return "HexagonISD::CONST32_GP" ; case HexagonISD :: CONST32_Int_Real : return "HexagonISD::CONST32_Int_Real" ; case HexagonISD :: ADJDYNALLOC : return "HexagonISD::ADJDYNALLOC" ; case HexagonISD :: CMPICC : return "HexagonISD::CMPICC" ; case HexagonISD :: CMPFCC : return "HexagonISD::CMPFCC" ; case HexagonISD :: BRICC : return "HexagonISD::BRICC" ; case HexagonISD :: BRFCC : return "HexagonISD::BRFCC" ; case HexagonISD :: SELECT_ICC : return "HexagonISD::SELECT_ICC" ; case HexagonISD :: SELECT_FCC : return "HexagonISD::SELECT_FCC" ; case HexagonISD :: Hi : return "HexagonISD::Hi" ; case HexagonISD :: Lo : return "HexagonISD::Lo" ; case HexagonISD :: FTOI : return "HexagonISD::FTOI" ; case HexagonISD :: ITOF : return "HexagonISD::ITOF" ; case HexagonISD :: CALL : return "HexagonISD::CALL" ; case HexagonISD :: RET_FLAG : return "HexagonISD::RET_FLAG" ; case HexagonISD :: BR_JT : return "HexagonISD::BR_JT" ; case HexagonISD :: TC_RETURN : return "HexagonISD::TC_RETURN" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> bool isReg ( ) const override { return Kind == k_Register ; } </s>


<s> bool PPCPassConfig :: addPreSched2 ( ) { if ( getPPCSubtarget ( ) . hasVSX ( ) ) addPass ( createPPCVSXCopyCleanupPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & IfConverterID ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> bool SIPeepholeSDWA :: runOnMachineFunction ( MachineFunction & MF ) { const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; if ( ! ST . hasSDWA ( ) || ! AMDGPU :: isVI ( ST ) ) { return false ; } MRI = & MF . getRegInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; TII = ST . getInstrInfo ( ) ; matchSDWAOperands ( MF ) ; for ( const auto & OperandPair : SDWAOperands ) { const auto & Operand = OperandPair . second ; MachineInstr * PotentialMI = Operand -> potentialToConvert ( TII ) ; if ( PotentialMI && isConvertibleToSDWA ( * PotentialMI ) ) { PotentialMatches [ PotentialMI ] . push_back ( Operand . get ( ) ) ; } } for ( auto & PotentialPair : PotentialMatches ) { MachineInstr & PotentialMI = * PotentialPair . first ; convertToSDWA ( PotentialMI , PotentialPair . second ) ; } PotentialMatches . clear ( ) ; SDWAOperands . clear ( ) ; bool Ret = ! ConvertedInstructions . empty ( ) ; while ( ! ConvertedInstructions . empty ( ) ) legalizeScalarOperands ( * ConvertedInstructions . pop_back_val ( ) ) ; return Ret ; } </s>

runOnMachineFunction - Emit the function body .


"Can only insert epilog into returning blocks"

"SPURegisterInfo::emitEpilogue: FrameSize not aligned"


<s> bool mips_cprestore_address_p ( rtx x , bool load_p ) { rtx given_base , required_base ; HOST_WIDE_INT given_offset , required_offset ; mips_split_plus ( x , & given_base , & given_offset ) ; mips_get_cprestore_base_and_offset ( & required_base , & required_offset , load_p ) ; return given_base == required_base && given_offset == required_offset ; } </s>

Return true if X is the load or store address of the cprestore slot ; LOAD_P says which .


<s> aarch64_print_operand_address ( STREAM , X ) { \ rtx fun , lr ; \ lr = get_hard_reg_initial_val ( Pmode , LR_REGNUM ) ; \ fun = gen_rtx_SYMBOL_REF ( Pmode , MCOUNT_NAME ) ; \ emit_library_call ( fun , LCT_NORMAL , VOIDmode , 1 , lr , Pmode ) ; \ } </s>

Print address ' x ' of a memory access with mode 'mode ' .


<s> void X86WinCOFFStreamer :: finishImpl ( ) { emitFrames ( nullptr ) ; EmitWindowsUnwindTables ( ) ; MCWinCOFFStreamer :: finishImpl ( ) ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool SIInstrInfo :: findCommutedOpIndices ( MachineInstr * MI , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( ! MCID . isCommutable ( ) ) return false ; unsigned Opc = MI -> getOpcode ( ) ; int Src0Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src0 ) ; if ( Src0Idx == - 1 ) return false ; if ( ! MI -> getOperand ( Src0Idx ) . isReg ( ) ) return false ; int Src1Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src1 ) ; if ( Src1Idx == - 1 ) return false ; if ( ! MI -> getOperand ( Src1Idx ) . isReg ( ) ) return false ; if ( hasModifiersSet ( * MI , AMDGPU :: OpName :: src0_modifiers ) || hasModifiersSet ( * MI , AMDGPU :: OpName :: src1_modifiers ) ) return false ; SrcOpIdx1 = Src0Idx ; SrcOpIdx2 = Src1Idx ; return true ; } </s>

Returns true iff the routine could find two commutable operands in the given machine instruction .


<s> Value * ARMTargetLowering :: emitLoadLinked ( IRBuilderBase & Builder , Type * ValueTy , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsAcquire = isAcquireOrStronger ( Ord ) ; if ( ValueTy -> getPrimitiveSizeInBits ( ) == 64 ) { Intrinsic :: ID Int = IsAcquire ? Intrinsic :: arm_ldaexd : Intrinsic :: arm_ldrexd ; Function * Ldrex = Intrinsic :: getDeclaration ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldrex , Addr , "lohi" ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Lo = Builder . CreateZExt ( Lo , ValueTy , "lo64" ) ; Hi = Builder . CreateZExt ( Hi , ValueTy , "hi64" ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValueTy , 32 ) ) , "val64" ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; Intrinsic :: ID Int = IsAcquire ? Intrinsic :: arm_ldaex : Intrinsic :: arm_ldrex ; Function * Ldrex = Intrinsic :: getDeclaration ( M , Int , Tys ) ; CallInst * CI = Builder . CreateCall ( Ldrex , Addr ) ; CI -> addParamAttr ( 0 , Attribute :: get ( M -> getContext ( ) , Attribute :: ElementType , ValueTy ) ) ; return Builder . CreateTruncOrBitCast ( CI , ValueTy ) ; } </s>

Perform a load-linked operation on Addr , returning a `` Value * '' with the corresponding pointee type .


"Cannot load this register from a stack slot!"

Load the specified register of the given register class from the specified stack frame index .


<s> bool isReg ( ) const { if ( isGPRAsmReg ( ) && RegIdx . Index == 0 ) return true ; return Kind == k_PhysRegister ; } </s>


<s> void SparcRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { MachineInstr & MI = * I ; DebugLoc dl = MI . getDebugLoc ( ) ; int Size = MI . getOperand ( 0 ) . getImm ( ) ; if ( MI . getOpcode ( ) == SP :: ADJCALLSTACKDOWN ) Size = - Size ; if ( Size ) BuildMI ( MBB , I , dl , TII . get ( SP :: ADDri ) , SP :: O6 ) . addReg ( SP :: O6 ) . addImm ( Size ) ; MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool PPCTTIImpl :: useColdCCForColdCall ( Function & F ) { return EnablePPCColdCC ; } </s>

Return true if the input function which is cold at all call sites , should use coldcc calling convention .


<s> void PPCFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const PPCRegisterInfo * RegInfo = static_cast < const PPCRegisterInfo * > ( Subtarget . getRegisterInfo ( ) ) ; PPCFunctionInfo * FI = MF . getInfo < PPCFunctionInfo > ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; SavedRegs . reset ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; bool isPPC64 = Subtarget . isPPC64 ( ) ; bool isDarwinABI = Subtarget . isDarwinABI ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( ) ; FPSI = MFI -> CreateFixedObject ( isPPC64 ? 8 : 4 , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int BPSI = FI -> getBasePointerSaveIndex ( ) ; if ( ! BPSI && RegInfo -> hasBasePointer ( MF ) ) { int BPOffset = getBasePointerSaveOffset ( ) ; BPSI = MFI -> CreateFixedObject ( isPPC64 ? 8 : 4 , BPOffset , true ) ; FI -> setBasePointerSaveIndex ( BPSI ) ; } if ( FI -> usesPICBase ( ) ) { int PBPSI = FI -> getPICBasePointerSaveIndex ( ) ; PBPSI = MFI -> CreateFixedObject ( 4 , - 8 , true ) ; FI -> setPICBasePointerSaveIndex ( PBPSI ) ; } int TCSPDelta = 0 ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < 0 ) { MFI -> CreateFixedObject ( - 1 * TCSPDelta , TCSPDelta , true ) ; } if ( ! isPPC64 && ! isDarwinABI && ( SavedRegs . test ( PPC :: CR2 ) || SavedRegs . test ( PPC :: CR3 ) || SavedRegs . test ( PPC :: CR4 ) ) ) { int FrameIdx = MFI -> CreateFixedObject ( ( uint64_t ) 4 , ( int64_t ) - 4 , true ) ; FI -> setCRSpillFrameIndex ( FrameIdx ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> static void s390_register_info_stdarg_gpr ( ) { int i ; int min_gpr ; int max_gpr ; if ( ! cfun -> stdarg || ! cfun -> va_list_gpr_size || crtl -> args . info . gprs >= GP_ARG_NUM_REG ) return ; min_gpr = crtl -> args . info . gprs ; max_gpr = min_gpr + cfun -> va_list_gpr_size ; if ( max_gpr > GP_ARG_NUM_REG ) max_gpr = GP_ARG_NUM_REG ; for ( i = min_gpr ; i < max_gpr ; i ++ ) cfun_gpr_save_slot ( 2 + i ) = - 1 ; } </s>

Reserve the GPR save slots for GPRs which need to be saved due to stdarg . This is a helper routine for s390_register_info .


<s> void WebAssemblyTargetWasmStreamer :: emitImportModule ( MCSymbolWasm * Sym , StringRef ModuleName ) { Sym -> setModuleName ( ModuleName ) ; } </s>


<s> static rtx_code_label * ix86_expand_aligntest ( rtx variable , int value , bool epilogue ) { rtx_code_label * label = gen_label_rtx ( ) ; rtx tmpcount = gen_reg_rtx ( GET_MODE ( variable ) ) ; if ( GET_MODE ( variable ) == DImode ) emit_insn ( gen_anddi3 ( tmpcount , variable , GEN_INT ( value ) ) ) ; else emit_insn ( gen_andsi3 ( tmpcount , variable , GEN_INT ( value ) ) ) ; emit_cmp_and_jump_insns ( tmpcount , const0_rtx , EQ , 0 , GET_MODE ( variable ) , 1 , label ) ; if ( epilogue ) predict_jump ( REG_BR_PROB_BASE * 50 / 100 ) ; else predict_jump ( REG_BR_PROB_BASE * 90 / 100 ) ; return label ; } </s>

Helper function for the string operations below . Dest VARIABLE whether it is aligned to VALUE bytes . If true , jump to the label .


"stack limit expression is not supported"

Emit the correct code for allocating stack space , as insns . If COPY_R12 , make sure a copy of the old frame is left in r12 . The generated code may use hard register 0 as a temporary .


<s> static HOST_WIDE_INT rs6000_constant_alignment ( const_tree exp , HOST_WIDE_INT align ) { if ( TREE_CODE ( exp ) == STRING_CST && ( STRICT_ALIGNMENT || ! optimize_size ) ) return MAX ( align , BITS_PER_WORD ) ; return align ; } </s>


<s> static rtx aarch64_convert_mult_to_shift ( rtx value , rtx_code & code ) { if ( GET_CODE ( value ) != CONST_VECTOR ) return NULL_RTX ; rtx_vector_builder builder ; if ( ! builder . new_unary_operation ( GET_MODE ( value ) , value , false ) ) return NULL_RTX ; scalar_mode int_mode = GET_MODE_INNER ( GET_MODE ( value ) ) ; int negate = - 1 ; unsigned int encoded_nelts = const_vector_encoded_nelts ( value ) ; for ( unsigned int i = 0 ; i < encoded_nelts ; ++ i ) { rtx elt = CONST_VECTOR_ENCODED_ELT ( value , i ) ; if ( ! CONST_SCALAR_INT_P ( elt ) ) return NULL_RTX ; rtx_mode_t val ( elt , int_mode ) ; wide_int pow2 = wi :: neg ( val ) ; if ( val != pow2 ) { if ( negate == ! wi :: neg_p ( val ) ) return NULL_RTX ; negate = wi :: neg_p ( val ) ; if ( ! negate ) pow2 = val ; } int shift = wi :: exact_log2 ( pow2 ) ; if ( shift < 0 ) return NULL_RTX ; builder . quick_push ( gen_int_mode ( shift , int_mode ) ) ; } if ( negate == - 1 ) code = PLUS ; else if ( negate == 1 ) code = code == PLUS ? MINUS : PLUS ; return builder . build ( ) ; } </s>

Check whether VALUE is a vector constant in which every element is either a power of 2 or a negated power of 2 . If so , return a constant vector of log2s , and flip CODE between PLUS and MINUS if VALUE contains negated powers of 2 . Return NULL_RTX otherwise .


<s>
void
AVRAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
adjustFixupValue
(
Fixup
,
Target
,
Value
,
&
Asm
.
getContext
(
)
)
;
if
(
Value
==
0
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
auto
NumBits
=
Info
.
TargetSize
+
Info
.
TargetOffset
;
auto
NumBytes
=
(
NumBits
/
8
)
+
(
(
NumBits
%
8
)
==
0
0
:
1
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
<
NumBytes
;
++
i
)
{
uint8_t
mask
=
(
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
)
;
Data
[
Offset
+
i
]
|=
mask
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool WebAssemblyDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { switch ( ConstraintID ) { case InlineAsm :: Constraint_i : case InlineAsm :: Constraint_m : OutOps . push_back ( Op ) ; return false ; default : break ; } return true ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s>
static
void
arm_unwind_emit_set
(
FILE
*
out_file
,
rtx
p
)
{
rtx
e0
;
rtx
e1
;
unsigned
reg
;
e0
=
XEXP
(
p
,
0
)
;
e1
=
XEXP
(
p
,
1
)
;
switch
(
GET_CODE
(
e0
)
)
{
case
MEM
:
if
(
GET_CODE
(
XEXP
(
e0
,
0
)
)
!=
PRE_DEC
||
!
REG_P
(
XEXP
(
XEXP
(
e0
,
0
)
,
0
)
)
||
REGNO
(
XEXP
(
XEXP
(
e0
,
0
)
,
0
)
)
!=
SP_REGNUM
)
abort
(
)
;
asm_fprintf
(
out_file
,
"\t.save "
)
;
if
(
IS_VFP_REGNUM
(
REGNO
(
e1
)
)
)
asm_fprintf
(
out_file
,
"{d%d}\n"
,
(
REGNO
(
e1
)
FIRST_VFP_REGNUM
)
/
2
)
;
else
asm_fprintf
(
out_file
,
"{%r}\n"
,
REGNO
(
e1
)
)
;
break
;
case
REG
:
if
(
REGNO
(
e0
)
==
SP_REGNUM
)
{
if
(
GET_CODE
(
e1
)
!=
PLUS
||
!
REG_P
(
XEXP
(
e1
,
0
)
)
||
REGNO
(
XEXP
(
e1
,
0
)
)
!=
SP_REGNUM
||
!
CONST_INT_P
(
XEXP
(
e1
,
1
)
)
)
abort
(
)
;
asm_fprintf
(
out_file
,
"\t.pad #%wd\n"
,
INTVAL
(
XEXP
(
e1
,
1
)
)
)
;
}
else
if
(
REGNO
(
e0
)
==
HARD_FRAME_POINTER_REGNUM
)
{
HOST_WIDE_INT
offset
;
if
(
GET_CODE
(
e1
)
==
PLUS
)
{
if
(
!
REG_P
(
XEXP
(
e1
,
0
)
)
||
!
CONST_INT_P
(
XEXP
(
e1
,
1
)
)
)
abort
(
)
;
reg
=
REGNO
(
XEXP
(
e1
,
0
)
)
;
offset
=
INTVAL
(
XEXP
(
e1
,
1
)
)
;
asm_fprintf
(
out_file
,
"\t.setfp %r, %r, #%wd\n"
,
HARD_FRAME_POINTER_REGNUM
,
reg
,
offset
)
;
}
else
if
(
REG_P
(
e1
)
)
{
reg
=
REGNO
(
e1
)
;
asm_fprintf
(
out_file
,
"\t.setfp %r, %r\n"
,
HARD_FRAME_POINTER_REGNUM
,
reg
)
;
}
else
abort
(
)
;
}
else
if
(
REG_P
(
e1
)
&&
REGNO
(
e1
)
==
SP_REGNUM
)
{
asm_fprintf
(
out_file
,
"\t.movsp %r\n"
,
REGNO
(
e0
)
)
;
}
else
if
(
GET_CODE
(
e1
)
==
PLUS
&&
REG_P
(
XEXP
(
e1
,
0
)
)
&&
REGNO
(
XEXP
(
e1
,
0
)
)
==
SP_REGNUM
&&
CONST_INT_P
(
XEXP
(
e1
,
1
)
)
)
{
asm_fprintf
(
out_file
,
"\t.movsp %r, #%d\n"
,
REGNO
(
e0
)
,
(
int
)
INTVAL
(
XEXP
(
e1
,
1
)
)
)
;
}
else
if
(
REGNO
(
e0
)
==
IP_REGNUM
&&
arm_current_function_pac_enabled_p
(
)
)
{
if
(
cfun
->
machine
->
pacspval_needed
)
asm_fprintf
(
out_file
,
"\t.pacspval\n"
)
;
}
else
abort
(
)
;
break
;
default
:
abort
(
)
;
}
}
</s>


<s> void X86AsmBackend :: emitInstructionBegin ( MCObjectStreamer & OS , const MCInst & Inst , const MCSubtargetInfo & STI ) { CanPadInst = canPadInst ( Inst , OS ) ; if ( ! canPadBranches ( OS ) ) return ; if ( ! isMacroFused ( PrevInst , Inst ) ) PendingBA = nullptr ; if ( ! CanPadInst ) return ; if ( PendingBA && OS . getCurrentFragment ( ) -> getPrevNode ( ) == PendingBA ) { return ; } if ( needAlign ( Inst ) || ( ( AlignBranchType & X86 :: AlignBranchFused ) && isFirstMacroFusibleInst ( Inst , * MCII ) ) ) { OS . insert ( PendingBA = new MCBoundaryAlignFragment ( AlignBoundary , STI ) ) ; } } </s>

Give the target a chance to manipulate state related to instruction alignment ( e.g .


<s> int mmix_register_move_cost ( enum machine_mode mode ATTRIBUTE_UNUSED , enum reg_class from , enum reg_class to ) { return ( from == GENERAL_REGS && from == to ) ? 2 : 3 ; } </s>


<s> unsigned getNumFixupKinds ( ) const override { return MCS51 :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


"Instructions with multiple result values not implemented"

Print the specified MCInst to the specified raw_ostream .


<s> int ix86_match_ccmode ( rtx insn , enum machine_mode req_mode ) { rtx set ; enum machine_mode set_mode ; set = PATTERN ( insn ) ; if ( GET_CODE ( set ) == PARALLEL ) set = XVECEXP ( set , 0 , 0 ) ; gcc_assert ( GET_CODE ( set ) == SET ) ; gcc_assert ( GET_CODE ( SET_SRC ( set ) ) == COMPARE ) ; set_mode = GET_MODE ( SET_DEST ( set ) ) ; switch ( set_mode ) { case CCNOmode : if ( req_mode != CCNOmode && ( req_mode != CCmode || XEXP ( SET_SRC ( set ) , 1 ) != const0_rtx ) ) return 0 ; break ; case CCmode : if ( req_mode == CCGCmode ) return 0 ; case CCGCmode : if ( req_mode == CCGOCmode || req_mode == CCNOmode ) return 0 ; case CCGOCmode : if ( req_mode == CCZmode ) return 0 ; case CCZmode : break ; default : gcc_unreachable ( ) ; } return ( GET_MODE ( SET_SRC ( set ) ) == set_mode ) ; } </s>

Return TRUE or FALSE depending on whether the first SET in INSN has source and destination with matching CC modes , and that the CC mode is at least as constrained as REQ_MODE .


<s> static int m32c_memory_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t rclass ATTRIBUTE_UNUSED , bool in ATTRIBUTE_UNUSED ) { return COSTS_N_INSNS ( 10 ) ; } </s>


<s>
bool
HexagonPassConfig
::
addInstSelector
(
)
{
HexagonTargetMachine
&
TM
=
getHexagonTargetMachine
(
)
;
bool
NoOpt
=
(
getOptLevel
(
)
==
CodeGenOpt
::
)
;
if
(
!
NoOpt
)
addPass
(
createHexagonRemoveExtendArgs
(
TM
)
)
;
addPass
(
createHexagonISelDag
(
TM
,
getOptLevel
(
)
)
)
;
if
(
!
NoOpt
)
{
if
(
EnableGenPred
)
addPass
(
createHexagonGenPredicate
(
)
,
false
)
;
addPass
(
createHexagonPeephole
(
)
)
;
printAndVerify
(
"After hexagon peephole pass"
)
;
if
(
EnableGenInsert
)
addPass
(
createHexagonGenInsert
(
)
,
false
)
;
}
return
false
;
}
</s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .

Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
"After hexagon peephole pass"
Hexagon


<s>
StringRef
R600AsmPrinter
::
getPassName
(
)
const
{
return
"R600 Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void erase_if ( T && container , Pred p ) { llvm :: erase_if ( std :: forward < T > ( container ) , p ) ; } </s>

Erase items from the set vector based on a predicate function .


<s> unsigned SystemZInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { return isSimpleMove ( MI , FrameIndex , SystemZII :: SimpleBDXStore ) ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s>
bool
runOnMachineFunction
(
MachineFunction
&
MF
)
override
{
LLVM_DEBUG
(
dbgs
(
)
<<
"********** ISelDAGToDAG **********\n"
"********** Function: "
<<
MF
.
getName
(
)
<<
'\n'
)
;
Subtarget
=
&
MF
.
getSubtarget
<
WebAssemblySubtarget
>
(
)
;
return
SelectionDAGISel
::
runOnMachineFunction
(
MF
)
;
}
</s>

runOnMachineFunction - Emit the function body .

WebAssembly
"********** ISelDAGToDAG **********\n"
"********** Function: "
WebAssembly


<s> void ECLairInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>


<s>
unsigned
HexagonInstrInfo
::
createVR
(
MachineFunction
*
MF
,
MVT
VT
)
const
{
MachineRegisterInfo
&
RegInfo
=
MF
->
getRegInfo
(
)
;
const
TargetRegisterClass
*
TRC
;
if
(
VT
==
MVT
::
i1
)
{
TRC
=
Hexagon
::
PredRegsRegisterClass
;
}
else
if
(
VT
==
MVT
::
i32
)
{
TRC
=
Hexagon
::
IntRegsRegisterClass
;
}
else
if
(
VT
==
MVT
::
i64
)
{
TRC
=
Hexagon
::
DoubleRegsRegisterClass
;
}
else
{
llvm_unreachable
(
"Cannot handle this register class"
)
;
}
unsigned
NewReg
=
RegInfo
.
createVirtualRegister
(
TRC
)
;
return
NewReg
;
}
</s>

Hexagon
Hexagon
MVT::i1
Hexagon::PredRegsRegisterClass
MVT::i32
Hexagon::IntRegsRegisterClass
MVT::i64
Hexagon::DoubleRegsRegisterClass
"Cannot handle this register class"


"Libcall overhead timing pass for the TMS320C64X target"


<s> static rtx nvptx_function_arg ( cumulative_args_t ARG_UNUSED ( cum_v ) , machine_mode mode , const_tree , bool named ) { if ( mode == VOIDmode || ! named ) return NULL_RTX ; return gen_reg_rtx ( mode ) ; } </s>


<s>
void
HSAILMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
llvm_unreachable
(
"When do we hit this?"
)
;
}
</s>

Encode the given Inst to bytes and append to CB .


<s> static void s390_live_on_entry ( bitmap regs ) { if ( cfun -> machine -> split_stack_varargs_pointer != NULL_RTX ) { gcc_assert ( flag_split_stack ) ; bitmap_set_bit ( regs , 1 ) ; } } </s>

We may have to tell the dataflow pass that the split stack prologue is initializing a register .


<s> const char * RISCVTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { OPCODE ( RET_FLAG ) ; OPCODE ( CALL ) ; OPCODE ( PCREL_WRAPPER ) ; OPCODE ( Hi ) ; OPCODE ( Lo ) ; OPCODE ( FENCE ) ; OPCODE ( SELECT_CC ) ; OPCODE ( SMIN ) ; OPCODE ( UMIN ) ; OPCODE ( SMAX ) ; OPCODE ( UMAX ) ; } return NULL ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> const DataLayout * getDataLayout ( ) const override { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


"  Found lowered global address with one use: "


<s> StringRef getPassName ( ) const override { return AARCH64_COLLECT_LOH_NAME ; } </s>


"VideoCore4 DAG->DAG Pattern Instruction Selection"


<s> void AMDGPUAsmBackend :: relaxInstruction ( MCInst & Inst , const MCSubtargetInfo & STI ) const { MCInst Res ; unsigned RelaxedOpcode = AMDGPU :: getSOPPWithRelaxation ( Inst . getOpcode ( ) ) ; Res . setOpcode ( RelaxedOpcode ) ; Res . addOperand ( Inst . getOperand ( 0 ) ) ; Inst = std :: move ( Res ) ; } </s>

Relax the instruction in the given fragment to the next wider instruction .

AMDGPU AMDGPU AMDGPU::getSOPPWithRelaxation 0


<s> static bool expand_set_cint32_one_inst ( rtx dest_reg , HOST_WIDE_INT val , bool three_wide_only ) { val = trunc_int_for_mode ( val , SImode ) ; if ( val == trunc_int_for_mode ( val , QImode ) ) { emit_move_insn ( dest_reg , GEN_INT ( val ) ) ; return true ; } else if ( ! three_wide_only ) { rtx imm_op = GEN_INT ( val ) ; if ( satisfies_constraint_J ( imm_op ) || satisfies_constraint_K ( imm_op ) || satisfies_constraint_N ( imm_op ) || satisfies_constraint_P ( imm_op ) ) { emit_move_insn ( dest_reg , imm_op ) ; return true ; } } return false ; } </s>

Returns true iff val can be moved into a register in one instruction . And if it can , it emits the code to move the constant . If three_wide_only is true , this insists on an instruction that works in a bundle containing three instructions .


<s> unsigned PPCFastISel :: fastEmitInst_rr ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , bool Op0IsKill , unsigned Op1 , bool Op1IsKill ) { const TargetRegisterClass * UseRC = ( RC == & PPC :: GPRCRegClass ? & PPC :: GPRC_and_GPRC_NOR0RegClass : ( RC == & PPC :: G8RCRegClass ? & PPC :: G8RC_and_G8RC_NOX0RegClass : RC ) ) ; return FastISel :: fastEmitInst_rr ( MachineInstOpcode , UseRC , Op0 , Op0IsKill , Op1 , Op1IsKill ) ; } </s>

Emit a MachineInstr with two register operands and a result register in the given register class .


<s>
unsigned
getReg
(
)
const
{
assert
(
Kind
==
k_Reg
&&
"Invalid access!"
)
;
return
Reg
;
}
</s>

Returns the register associated with this edge .


<s> unsigned X86TargetLowering :: getVectorTypeBreakdownForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT , EVT & IntermediateVT , unsigned & NumIntermediates , MVT & RegisterVT ) const { if ( VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i1 && Subtarget . hasAVX512 ( ) && ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) || ( VT . getVectorNumElements ( ) == 64 && ! Subtarget . hasBWI ( ) ) || VT . getVectorNumElements ( ) > 64 ) ) { RegisterVT = MVT :: i8 ; IntermediateVT = MVT :: i1 ; NumIntermediates = VT . getVectorNumElements ( ) ; return NumIntermediates ; } if ( VT == MVT :: v64i1 && Subtarget . hasBWI ( ) && ! Subtarget . useAVX512Regs ( ) && CC != CallingConv :: X86_RegCall ) { RegisterVT = MVT :: v32i8 ; IntermediateVT = MVT :: v32i1 ; NumIntermediates = 2 ; return 2 ; } return TargetLowering :: getVectorTypeBreakdownForCallingConv ( Context , CC , VT , IntermediateVT , NumIntermediates , RegisterVT ) ; } </s>

Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts .


<s> void split_double_concat ( machine_mode mode , rtx dst , rtx lo , rtx hi ) { rtx dlo , dhi ; int deleted_move_count = 0 ; split_double_mode ( mode , & dst , 1 , & dlo , & dhi ) ; if ( MEM_P ( lo ) && rtx_equal_p ( dlo , hi ) && reg_overlap_mentioned_p ( dhi , lo ) ) { emit_move_insn ( dhi , lo ) ; lo = dhi ; } else if ( MEM_P ( hi ) && ! MEM_P ( lo ) && ! rtx_equal_p ( dlo , lo ) && reg_overlap_mentioned_p ( dlo , hi ) ) { if ( rtx_equal_p ( dhi , lo ) ) { emit_move_insn ( dlo , hi ) ; hi = dlo ; } else { emit_move_insn ( dhi , hi ) ; hi = dhi ; } } if ( ! rtx_equal_p ( dlo , hi ) ) { if ( ! rtx_equal_p ( dlo , lo ) ) emit_move_insn ( dlo , lo ) ; else deleted_move_count ++ ; if ( ! rtx_equal_p ( dhi , hi ) ) emit_move_insn ( dhi , hi ) ; else deleted_move_count ++ ; } else if ( ! rtx_equal_p ( lo , dhi ) ) { if ( ! rtx_equal_p ( dhi , hi ) ) emit_move_insn ( dhi , hi ) ; else deleted_move_count ++ ; if ( ! rtx_equal_p ( dlo , lo ) ) emit_move_insn ( dlo , lo ) ; else deleted_move_count ++ ; } else if ( mode == TImode ) emit_insn ( gen_swapdi ( dlo , dhi ) ) ; else emit_insn ( gen_swapsi ( dlo , dhi ) ) ; if ( deleted_move_count == 2 ) emit_note ( NOTE_INSN_DELETED ) ; } </s>

Emit the double word assignment DST = { LO , HI } .


<s> bool AArch64AsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == ".hword" ) return parseDirectiveWord ( 2 , Loc ) ; if ( IDVal == ".word" ) return parseDirectiveWord ( 4 , Loc ) ; if ( IDVal == ".xword" ) return parseDirectiveWord ( 8 , Loc ) ; if ( IDVal == ".tlsdesccall" ) return parseDirectiveTLSDescCall ( Loc ) ; return parseDirectiveLOH ( IDVal , Loc ) ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> void PPCPassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( & getPPCTargetMachine ( ) ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s>
void
RISCVMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
unsigned
Size
=
Desc
.
getSize
(
)
;
if
(
MI
.
getOpcode
(
)
==
RISCV
::
PseudoCALLReg
||
MI
.
getOpcode
(
)
==
RISCV
::
PseudoCALL
||
MI
.
getOpcode
(
)
==
RISCV
::
PseudoTAIL
||
MI
.
getOpcode
(
)
==
RISCV
::
PseudoJump
)
{
expandFunctionCall
(
MI
,
OS
,
Fixups
,
STI
)
;
MCNumEmitted
+=
2
;
return
;
}
if
(
MI
.
getOpcode
(
)
==
RISCV
::
PseudoAddTPRel
)
{
expandAddTPRel
(
MI
,
OS
,
Fixups
,
STI
)
;
MCNumEmitted
+=
1
;
return
;
}
switch
(
Size
)
{
default
:
llvm_unreachable
(
"Unhandled encodeInstruction length!"
)
;
case
2
:
{
uint16_t
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
support
::
endian
::
write
<
uint16_t
>
(
OS
,
Bits
,
support
::
little
)
;
break
;
}
case
4
:
{
uint32_t
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
support
::
endian
::
write
(
OS
,
Bits
,
support
::
little
)
;
break
;
}
}
++
MCNumEmitted
;
}
</s>

RISCV
RISCV
RISCV::PseudoCALLReg
RISCV::PseudoCALL
RISCV::PseudoTAIL
RISCV::PseudoJump
2
RISCV::PseudoAddTPRel
1
"Unhandled encodeInstruction length!"
2
support::endian
support::little
4
support::endian
support::little


<s> bool ELFAArch64AsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { if ( ( uint32_t ) Fixup . getKind ( ) == AArch64 :: fixup_aarch64_pcrel_adrp_imm21 ) return true ; return false ; } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> bool isReg ( ) const { return Kind == Register ; } </s>


<s>
void
MipsRegisterBankInfo
::
setRegBank
(
MachineInstr
&
MI
,
MachineRegisterInfo
&
MRI
)
const
{
Register
Dest
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
switch
(
MI
.
getOpcode
(
)
)
{
case
TargetOpcode
::
G_STORE
:
break
;
case
TargetOpcode
::
G_CONSTANT
:
case
TargetOpcode
::
G_LOAD
:
case
TargetOpcode
::
G_SELECT
:
case
TargetOpcode
::
G_PHI
:
case
TargetOpcode
::
G_IMPLICIT_DEF
:
{
assert
(
MRI
.
getType
(
Dest
)
==
LLT
::
scalar
(
32
)
&&
"Unexpected operand type."
)
;
MRI
.
setRegBank
(
Dest
,
getRegBank
(
Mips
::
GPRBRegBankID
)
)
;
break
;
}
case
TargetOpcode
::
G_GEP
:
{
assert
(
MRI
.
getType
(
Dest
)
.
isPointer
(
)
&&
"Unexpected operand type."
)
;
MRI
.
setRegBank
(
Dest
,
getRegBank
(
Mips
::
GPRBRegBankID
)
)
;
break
;
}
default
:
llvm_unreachable
(
"Unexpected opcode."
)
;
}
}
</s>

RegBankSelect determined that s64 operand is better to be split into two s32 operands in gprb .

Mips
Mips
0
32
"Unexpected operand type."
Mips::GPRBRegBankID
"Unexpected operand type."
Mips::GPRBRegBankID
"Unexpected opcode."


<s> int shl_and_scr_length ( rtx insn ) { rtx set_src = SET_SRC ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) ) ; int len = shift_insns [ INTVAL ( XEXP ( set_src , 1 ) ) ] ; rtx op = XEXP ( set_src , 0 ) ; len += shift_insns [ INTVAL ( XEXP ( op , 1 ) ) ] + 1 ; op = XEXP ( XEXP ( op , 0 ) , 0 ) ; return len + shift_insns [ INTVAL ( XEXP ( op , 1 ) ) ] ; } </s>

This is used in length attribute of the and_shl_scratch instruction .


<s> static void aarch64_output_mi_thunk ( FILE * file , tree thunk ATTRIBUTE_UNUSED , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { int this_regno = R0_REGNUM ; rtx this_rtx , temp0 , temp1 , addr , funexp ; rtx_insn * insn ; reload_completed = 1 ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; if ( vcall_offset == 0 ) aarch64_add_constant ( this_regno , IP1_REGNUM , delta ) ; else { gcc_assert ( ( vcall_offset & ( POINTER_BYTES - 1 ) ) == 0 ) ; this_rtx = gen_rtx_REG ( Pmode , this_regno ) ; temp0 = gen_rtx_REG ( Pmode , IP0_REGNUM ) ; temp1 = gen_rtx_REG ( Pmode , IP1_REGNUM ) ; addr = this_rtx ; if ( delta != 0 ) { if ( delta >= - 256 && delta < 256 ) addr = gen_rtx_PRE_MODIFY ( Pmode , this_rtx , plus_constant ( Pmode , this_rtx , delta ) ) ; else aarch64_add_constant ( this_regno , IP1_REGNUM , delta ) ; } if ( Pmode == ptr_mode ) aarch64_emit_move ( temp0 , gen_rtx_MEM ( ptr_mode , addr ) ) ; else aarch64_emit_move ( temp0 , gen_rtx_ZERO_EXTEND ( Pmode , gen_rtx_MEM ( ptr_mode , addr ) ) ) ; if ( vcall_offset >= - 256 && vcall_offset < 4096 * POINTER_BYTES ) addr = plus_constant ( Pmode , temp0 , vcall_offset ) ; else { ( void ) aarch64_build_constant ( IP1_REGNUM , vcall_offset , true ) ; addr = gen_rtx_PLUS ( Pmode , temp0 , temp1 ) ; } if ( Pmode == ptr_mode ) aarch64_emit_move ( temp1 , gen_rtx_MEM ( ptr_mode , addr ) ) ; else aarch64_emit_move ( temp1 , gen_rtx_SIGN_EXTEND ( Pmode , gen_rtx_MEM ( ptr_mode , addr ) ) ) ; emit_insn ( gen_add2_insn ( this_rtx , temp1 ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = 1 ; } funexp = XEXP ( DECL_RTL ( function ) , 0 ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx , NULL_RTX ) ) ; SIBLING_CALL_P ( insn ) = 1 ; insn = get_insns ( ) ; shorten_branches ( insn ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; reload_completed = 0 ; } </s>

Output code to add DELTA to the first argument , and then jump to FUNCTION . Used for C++ multiple inheritance .


"failed to spill SGPR to VGPR when allocated"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


"only uninitialized variables can be placed in the "

Implement ` TARGET_SECTION_TYPE_FLAGS ' .


<s> unsigned MBlazeMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO ) const { if ( MO . isReg ( ) ) return getMBlazeRegisterNumbering ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; if ( MO . isExpr ( ) ) return 0 ; errs ( ) << MO ; llvm_unreachable ( 0 ) ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> const char * getPassName ( ) const override { return TLSCLEANUP_PASS_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


getTargetNodeName - This method returns the name of a target specific


<s> bool AMDGPUTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , unsigned Intrinsic ) const { return false ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s>
bool
BPFAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
unsigned
RegNo
=
MatchRegisterName
(
Name
)
;
if
(
RegNo
!=
0
)
{
SMLoc
E
=
SMLoc
::
getFromPointer
(
NameLoc
.
getPointer
(
)
1
)
;
Operands
.
push_back
(
BPFOperand
::
createReg
(
RegNo
,
NameLoc
,
E
)
)
;
}
else
if
(
BPFOperand
::
isValidIdAtStart
(
Name
)
)
Operands
.
push_back
(
BPFOperand
::
createToken
(
Name
,
NameLoc
)
)
;
else
return
true
;
while
(
!
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
{
if
(
parseOperandAsOperator
(
Operands
)
==
MatchOperand_Success
)
continue
;
if
(
parseRegister
(
Operands
)
==
MatchOperand_Success
)
continue
;
if
(
parseImmediate
(
Operands
)
!=
MatchOperand_Success
)
return
true
;
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
getParser
(
)
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
getParser
(
)
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

BPF
BPF
0
1
BPFOperand::createReg
BPFOperand::isValidIdAtStart
BPFOperand::createToken
"unexpected token"


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; AU . addRequired < MachineDominatorTree > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


"cannot return value in vector register because"

" altivec instructions are disabled, use -maltivec"

Handle the INIT_CUMULATIVE_ARGS macro . Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is 0 .


<s> virtual unsigned int execute ( function * fun ) { if ( avr_gasisr_prologues && ! fun -> machine -> is_no_gccisr && ( fun -> machine -> is_interrupt || fun -> machine -> is_signal ) && ! cfun -> machine -> is_naked && ! cfun -> calls_setjmp && ! cfun -> has_nonlocal_label && ! cfun -> has_forced_label_in_static ) { compute_maybe_gasisr ( fun ) ; } return 0 ; } </s>


This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> unsigned getNumFixupKinds ( ) const { return Sparc :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; AU . addRequired < ScalarEvolutionWrapperPass > ( ) ; AU . addPreserved < ScalarEvolutionWrapperPass > ( ) ; } </s>


<s> bool FixAllFDIVSQRT :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < SparcSubtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget -> getInstrInfo ( ) ; DebugLoc DL = DebugLoc ( ) ; bool Modified = false ; for ( auto MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; for ( auto MBBI = MBB . begin ( ) , E = MBB . end ( ) ; MBBI != E ; ++ MBBI ) { MachineInstr & MI = * MBBI ; unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == SP :: FSQRTD || Opcode == SP :: FDIVD ) { for ( int InsertedCount = 0 ; InsertedCount < 5 ; InsertedCount ++ ) BuildMI ( MBB , MBBI , DL , TII . get ( SP :: NOP ) ) ; MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; for ( int InsertedCount = 0 ; InsertedCount < 28 ; InsertedCount ++ ) BuildMI ( MBB , NMBBI , DL , TII . get ( SP :: NOP ) ) ; Modified = true ; } } } return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> static void rs6000_alloc_sdmode_stack_slot ( void ) { tree t ; basic_block bb ; gimple_stmt_iterator gsi ; gcc_assert ( cfun -> machine -> sdmode_stack_slot == NULL_RTX ) ; if ( ira_use_lra_p ) return ; if ( TARGET_NO_SDMODE_STACK ) return ; FOR_EACH_BB_FN ( bb , cfun ) for ( gsi = gsi_start_bb ( bb ) ; ! gsi_end_p ( gsi ) ; gsi_next ( & gsi ) ) { tree ret = walk_gimple_op ( gsi_stmt ( gsi ) , rs6000_check_sdmode , NULL ) ; if ( ret ) { rtx stack = assign_stack_local ( DDmode , GET_MODE_SIZE ( DDmode ) , 0 ) ; cfun -> machine -> sdmode_stack_slot = adjust_address_nv ( stack , SDmode , 0 ) ; return ; } } for ( t = DECL_ARGUMENTS ( cfun -> decl ) ; t ; t = DECL_CHAIN ( t ) ) { if ( TREE_TYPE ( t ) == error_mark_node ) continue ; if ( TYPE_MODE ( TREE_TYPE ( t ) ) == SDmode || TYPE_MODE ( DECL_ARG_TYPE ( t ) ) == SDmode ) { rtx stack = assign_stack_local ( DDmode , GET_MODE_SIZE ( DDmode ) , 0 ) ; cfun -> machine -> sdmode_stack_slot = adjust_address_nv ( stack , SDmode , 0 ) ; return ; } } } </s>

Allocate a 64-bit stack slot to be used for copying SDmode values through if this function has any SDmode references . If we are on a power7 or later , we do n't need the 64-bit stack slot since the LFIWZX and STIFWX instructions can load/store the value .


<s> static bool microblaze_can_eliminate ( const int from , const int to ) { return ( ( from == RETURN_ADDRESS_POINTER_REGNUM && ! leaf_function_p ( ) ) || ( to == MB_ABI_SUB_RETURN_ADDR_REGNUM && leaf_function_p ( ) ) || ( from != RETURN_ADDRESS_POINTER_REGNUM && ( to == HARD_FRAME_POINTER_REGNUM || ( to == STACK_POINTER_REGNUM && ! frame_pointer_needed ) ) ) ) ; } </s>

Make sure that we 're not trying to eliminate to the wrong hard frame pointer .


<s> MCSection * RISCVELFTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , Align & Alignment ) const { if ( isConstantInSmallSection ( DL , C ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: getSectionForConstant ( DL , Kind , C , Alignment ) ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> void RV16KInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static inline built_in_function complex_divide_builtin_code ( machine_mode mode ) { gcc_assert ( IN_RANGE ( mode , MIN_MODE_COMPLEX_FLOAT , MAX_MODE_COMPLEX_FLOAT ) ) ; int func = BUILT_IN_COMPLEX_DIV_MIN + mode - MIN_MODE_COMPLEX_FLOAT ; return ( built_in_function ) func ; } </s>

Internal function to return the built-in function id for the complex divide operation for a given mode .


<s> static int mips_address_cost ( rtx addr , machine_mode mode , addr_space_t as ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { return mips_address_insns ( addr , mode , false ) ; } </s>

Provide the costs of an addressing mode that contains ADDR . If ADDR is not a valid address , its cost is irrelevant .


<s> BitVector SIRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AMDGPU :: EXEC ) ; Reserved . set ( AMDGPU :: INDIRECT_BASE_ADDR ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> MachineInstr * SystemZInstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const { return 0 ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> int tls_symbolic_operand ( rtx op ) { if ( GET_CODE ( op ) != SYMBOL_REF ) return 0 ; return SYMBOL_REF_TLS_MODEL ( op ) ; } </s>

Return the TLS type for TLS symbols , 0 for otherwise .


<s> static inline bool s390_vector_bool_type_p ( const_tree type ) { return TYPE_VECTOR_OPAQUE ( type ) ; } </s>

Return true if TYPE is a vector bool type .


<s> bool PPCInstrInfo :: isPredicated ( const MachineInstr * MI ) const { return false ; } </s>

Returns true if the instruction is already predicated .


<s> bool M680x0FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; M680x0MachineFunctionInfo * M680x0FI = MF . getInfo < M680x0MachineFunctionInfo > ( ) ; int SpillSlotOffset = getOffsetOfLocalArea ( ) + M680x0FI -> getTCReturnAddrDelta ( ) ; if ( hasFP ( MF ) ) { SpillSlotOffset -= SlotSize ; MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; unsigned FPReg = TRI -> getFrameRegister ( MF ) ; for ( unsigned i = 0 ; i < CSI . size ( ) ; ++ i ) { if ( TRI -> regsOverlap ( CSI [ i ] . getReg ( ) , FPReg ) ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } } return false ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> void ARMInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << getRegisterName ( RegNo ) ; } </s>


<s>
SDValue
RISCVTargetLowering
::
getAddr
(
NodeTy
*
N
,
SelectionDAG
&
DAG
)
const
{
SDLoc
DL
(
N
)
;
EVT
Ty
=
getPointerTy
(
DAG
.
getDataLayout
(
)
)
;
switch
(
getTargetMachine
(
)
.
getCodeModel
(
)
)
{
default
:
report_fatal_error
(
"Unsupported code model for lowering"
)
;
case
CodeModel
::
Small
:
{
SDValue
AddrHi
=
getTargetNode
(
N
,
DL
,
Ty
,
DAG
,
RISCVII
::
MO_HI
)
;
SDValue
AddrLo
=
getTargetNode
(
N
,
DL
,
Ty
,
DAG
,
RISCVII
::
MO_LO
)
;
SDValue
MNHi
=
SDValue
(
DAG
.
getMachineNode
(
RISCV
::
LUI
,
DL
,
Ty
,
AddrHi
)
,
0
)
;
return
SDValue
(
DAG
.
getMachineNode
(
RISCV
::
ADDI
,
DL
,
Ty
,
MNHi
,
AddrLo
)
,
0
)
;
}
case
CodeModel
::
Medium
:
{
SDValue
Addr
=
getTargetNode
(
N
,
DL
,
Ty
,
DAG
,
0
)
;
return
SDValue
(
DAG
.
getMachineNode
(
RISCV
::
PseudoLLA
,
DL
,
Ty
,
Addr
)
,
0
)
;
}
}
}
</s>

Return the address accessed by this recipe .


<s> SDValue ARCompactTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_ARCompact32 ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> void initializePass ( ) override { pushTTIStack ( this ) ; } </s>

initializePass - This method may be overriden by immutable passes to allow them to perform various initialization actions they require .


<s> static rtx gen_rx_rtsd_vector ( unsigned int adjust , unsigned int low , unsigned int high ) { unsigned int i ; unsigned int bias = 3 ; unsigned int count = ( high - low ) + bias ; rtx vector ; vector = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; XVECEXP ( vector , 0 , 0 ) = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , adjust ) ) ; for ( i = 0 ; i < count - 2 ; i ++ ) XVECEXP ( vector , 0 , i + 1 ) = gen_rtx_SET ( gen_rtx_REG ( SImode , low + i ) , gen_rtx_MEM ( SImode , i == 0 ? stack_pointer_rtx : plus_constant ( Pmode , stack_pointer_rtx , i * UNITS_PER_WORD ) ) ) ; XVECEXP ( vector , 0 , count - 1 ) = ret_rtx ; return vector ; } </s>

Generate a PARALLEL which will satisfy the rx_rtsd_vector predicate .


<s>
SDValue
SystemZTargetLowering
::
LowerCall
(
SDValue
Chain
,
SDValue
Callee
,
unsigned
CallConv
,
bool
isVarArg
,
bool
isTailCall
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .

SystemZ
SystemZ
ISD::OutputArg
ISD::InputArg
"Unsupported calling convention"


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { if ( isConditionalBranch ( Inst ) ) { int64_t Imm ; if ( Size == 2 ) Imm = Inst . getOperand ( 1 ) . getImm ( ) ; else Imm = Inst . getOperand ( 2 ) . getImm ( ) ; Target = Addr + Imm ; return true ; } if ( Inst . getOpcode ( ) == RISCV :: C_JAL || Inst . getOpcode ( ) == RISCV :: C_J || Inst . getOpcode ( ) == RISCV :: C_CJAL ) { Target = Addr + Inst . getOperand ( 0 ) . getImm ( ) ; return true ; } if ( Inst . getOpcode ( ) == RISCV :: JAL || Inst . getOpcode ( ) == RISCV :: CJAL ) { Target = Addr + Inst . getOperand ( 1 ) . getImm ( ) ; return true ; } return false ; } </s>

Given a branch instruction try to get the address the branch targets .


Store the specified register of the given register class to the specified stack frame index .


<s> bool AMDGPUConvertToISAPass :: runOnMachineFunction ( MachineFunction & MF ) { const AMDGPUInstrInfo * TII = static_cast < const AMDGPUInstrInfo * > ( TM . getInstrInfo ( ) ) ; for ( MachineFunction :: iterator BB = MF . begin ( ) , BB_E = MF . end ( ) ; BB != BB_E ; ++ BB ) { MachineBasicBlock & MBB = * BB ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { MachineInstr & MI = * I ; TII -> convertToISA ( MI , MF , MBB . findDebugLoc ( I ) ) ; } } return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> static rtx move_acc_to_reg ( rtx acc , int regno , rtx_insn * before ) { machine_mode mode = GET_MODE ( acc ) ; rtx reg ; reg = gen_rtx_REG ( mode , regno ) ; return gen_and_emit_move ( reg , acc , before , true ) ; } </s>

Copy accumulator ( A or AX ) to REGNO , placing any generated insns before BEFORE . Returns reg RTX .


"Unhandled instruction encoding format!"

Targets should implement this to emit instructions .


<s>
SDValue
SparcTargetLowering
::
withTargetFlags
(
SDValue
Op
,
unsigned
TF
,
SelectionDAG
&
DAG
)
const
{
if
(
const
GlobalAddressSDNode
*
GA
=
dyn_cast
<
GlobalAddressSDNode
>
(
Op
)
)
return
DAG
.
getTargetGlobalAddress
(
GA
->
getGlobal
(
)
,
SDLoc
(
GA
)
,
GA
->
getValueType
(
0
)
,
GA
->
getOffset
(
)
,
TF
)
;
if
(
const
ConstantPoolSDNode
*
CP
=
dyn_cast
<
ConstantPoolSDNode
>
(
Op
)
)
return
DAG
.
getTargetConstantPool
(
CP
->
getConstVal
(
)
,
CP
->
getValueType
(
0
)
,
CP
->
getAlign
(
)
,
CP
->
getOffset
(
)
,
TF
)
;
if
(
const
BlockAddressSDNode
*
BA
=
dyn_cast
<
BlockAddressSDNode
>
(
Op
)
)
return
DAG
.
getTargetBlockAddress
(
BA
->
getBlockAddress
(
)
,
Op
.
getValueType
(
)
,
0
,
TF
)
;
if
(
const
ExternalSymbolSDNode
*
ES
=
dyn_cast
<
ExternalSymbolSDNode
>
(
Op
)
)
return
DAG
.
getTargetExternalSymbol
(
ES
->
getSymbol
(
)
,
ES
->
getValueType
(
0
)
,
TF
)
;
llvm_unreachable
(
"Unhandled address SDNode"
)
;
}
</s>


<s> TargetLowering :: ConstraintWeight MBlazeTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; const Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'd' : case 'y' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> unsigned MSP430RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? MSP430 :: FPW : MSP430 :: SPW ; } </s>


"Function has local memory argument.  Promoting to "

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


"interrupt and naked attributes are not compatible"

"Only DWARF debug format is supported for interrupt "

Set the func_type field from the function FNDECL .


<s> Align ARMTargetLowering :: getABIAlignmentForCallingConv ( Type * ArgTy , const DataLayout & DL ) const { const Align ABITypeAlign = DL . getABITypeAlign ( ArgTy ) ; if ( ! ArgTy -> isVectorTy ( ) ) return ABITypeAlign ; return std :: min ( ABITypeAlign , DL . getStackAlignment ( ) ) ; } </s>

Return the correct alignment for the current calling convention .