<s> static void nvptx_goacc_reduction_setup ( gcall * call ) { gimple_stmt_iterator gsi = gsi_for_stmt ( call ) ; tree lhs = gimple_call_lhs ( call ) ; tree var = gimple_call_arg ( call , 2 ) ; int level = TREE_INT_CST_LOW ( gimple_call_arg ( call , 3 ) ) ; gimple_seq seq = NULL ; push_gimplify_context ( true ) ; if ( level != GOMP_DIM_GANG ) { tree ref_to_res = gimple_call_arg ( call , 1 ) ; if ( ! integer_zerop ( ref_to_res ) ) var = build_simple_mem_ref ( ref_to_res ) ; } if ( level == GOMP_DIM_WORKER ) { tree offset = gimple_call_arg ( call , 5 ) ; tree call = nvptx_get_worker_red_addr ( TREE_TYPE ( var ) , offset ) ; tree ptr = make_ssa_name ( TREE_TYPE ( call ) ) ; gimplify_assign ( ptr , call , & seq ) ; tree ref = build_simple_mem_ref ( ptr ) ; TREE_THIS_VOLATILE ( ref ) = 1 ; gimplify_assign ( ref , var , & seq ) ; } if ( lhs ) gimplify_assign ( lhs , var , & seq ) ; pop_gimplify_context ( NULL ) ; gsi_replace_with_seq ( & gsi , seq , true ) ; } </s>

NVPTX implementation of GOACC_REDUCTION_SETUP .


<s>
void
HexagonFrameLowering
::
processFunctionBeforeFrameFinalized
(
MachineFunction
&
MF
,
RegScavenger
*
RS
)
const
{
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
bool
HasAlloca
=
MFI
.
hasVarSizedObjects
(
)
;
bool
NeedsAlign
=
(
MFI
.
getMaxAlign
(
)
>
getStackAlign
(
)
)
;
if
(
!
HasAlloca
||
!
NeedsAlign
)
return
;
SmallSet
<
int
,
4
>
DealignSlots
;
unsigned
LFS
=
MFI
.
getLocalFrameSize
(
)
;
for
(
int
i
=
0
,
e
=
MFI
.
getObjectIndexEnd
(
)
;
i
!=
e
;
++
i
)
{
if
(
!
MFI
.
isSpillSlotObjectIndex
(
i
)
||
MFI
.
isDeadObjectIndex
(
i
)
)
continue
;
unsigned
S
=
MFI
.
getObjectSize
(
i
)
;
Align
A
=
std
::
max
(
MFI
.
getObjectAlign
(
i
)
,
Align
(
8
)
)
;
MFI
.
setObjectAlignment
(
i
,
Align
(
8
)
)
;
LFS
=
alignTo
(
LFS
+
S
,
A
)
;
MFI
.
mapLocalFrameObject
(
i
,
static_cast
<
int64_t
>
(
LFS
)
)
;
DealignSlots
.
insert
(
i
)
;
}
MFI
.
setLocalFrameSize
(
LFS
)
;
Align
A
=
MFI
.
getLocalFrameMaxAlign
(
)
;
assert
(
A
<=
8
&&
"Unexpected local frame alignment"
)
;
if
(
A
==
1
)
MFI
.
setLocalFrameMaxAlign
(
Align
(
8
)
)
;
MFI
.
setUseLocalStackAllocationBlock
(
true
)
;
if
(
!
DealignSlots
.
empty
(
)
)
{
for
(
MachineBasicBlock
&
BB
:
MF
)
{
for
(
MachineInstr
&
MI
:
BB
)
{
bool
KeepOld
=
true
;
ArrayRef
<
MachineMemOperand
*
>
memops
=
MI
.
memoperands
(
)
;
SmallVector
<
MachineMemOperand
*
,
1
>
new_memops
;
for
(
MachineMemOperand
*
MMO
:
memops
)
{
auto
*
PV
=
MMO
->
getPseudoValue
(
)
;
if
(
auto
*
FS
=
dyn_cast_or_null
<
FixedStackPseudoSourceValue
>
(
PV
)
)
{
int
FI
=
FS
->
getFrameIndex
(
)
;
if
(
DealignSlots
.
count
(
FI
)
)
{
auto
*
NewMMO
=
MF
.
getMachineMemOperand
(
MMO
->
getPointerInfo
(
)
,
MMO
->
getFlags
(
)
,
MMO
->
getSize
(
)
,
MFI
.
getObjectAlign
(
FI
)
,
MMO
->
getAAInfo
(
)
,
MMO
->
getRanges
(
)
,
MMO
->
getSyncScopeID
(
)
,
MMO
->
getSuccessOrdering
(
)
,
MMO
->
getFailureOrdering
(
)
)
;
new_memops
.
push_back
(
NewMMO
)
;
KeepOld
=
false
;
continue
;
}
}
new_memops
.
push_back
(
MMO
)
;
}
if
(
!
KeepOld
)
MI
.
setMemRefs
(
MF
,
new_memops
)
;
}
}
}
unsigned
AP
=
0
;
if
(
const
MachineInstr
*
AI
=
getAlignaInstr
(
MF
)
)
AP
=
AI
->
getOperand
(
0
)
.
getReg
(
)
;
auto
&
HMFI
=
*
MF
.
getInfo
<
HexagonMachineFunctionInfo
>
(
)
;
HMFI
.
setStackAlignBasePhysReg
(
AP
)
;
}
</s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> SystemZSubtarget & SystemZSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { StringRef CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "generic" ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( HasSoftFloat ) HasVector = false ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool X86InstrInfo :: isHighLatencyDef ( int opc ) const { switch ( opc ) { default : return false ; case X86 :: DIVSDrm : case X86 :: DIVSDrm_Int : case X86 :: DIVSDrr : case X86 :: DIVSDrr_Int : case X86 :: DIVSSrm : case X86 :: DIVSSrm_Int : case X86 :: DIVSSrr : case X86 :: DIVSSrr_Int : case X86 :: SQRTPDm : case X86 :: SQRTPDr : case X86 :: SQRTPSm : case X86 :: SQRTPSr : case X86 :: SQRTSDm : case X86 :: SQRTSDm_Int : case X86 :: SQRTSDr : case X86 :: SQRTSDr_Int : case X86 :: SQRTSSm : case X86 :: SQRTSSm_Int : case X86 :: SQRTSSr : case X86 :: SQRTSSr_Int : case X86 :: VDIVSDrm : case X86 :: VDIVSDrm_Int : case X86 :: VDIVSDrr : case X86 :: VDIVSDrr_Int : case X86 :: VDIVSSrm : case X86 :: VDIVSSrm_Int : case X86 :: VDIVSSrr : case X86 :: VDIVSSrr_Int : case X86 :: VSQRTPDm : case X86 :: VSQRTPDr : case X86 :: VSQRTPSm : case X86 :: VSQRTPSr : case X86 :: VSQRTSDm : case X86 :: VSQRTSDm_Int : case X86 :: VSQRTSDr : case X86 :: VSQRTSSm : case X86 :: VSQRTSSm_Int : case X86 :: VSQRTSSr : return true ; } } </s>

Return true if this opcode has high latency to its result .


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s>
void
MipsInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineMemOperand
*
MMO
=
GetMemOperand
(
MBB
,
FI
,
MachineMemOperand
::
MOStore
)
;
unsigned
Opc
=
0
;
if
(
RC
==
Mips
::
CPURegsRegisterClass
)
Opc
=
IsN64
Mips
::
SW_P8
:
Mips
::
SW
;
else
if
(
RC
==
Mips
::
CPU64RegsRegisterClass
)
Opc
=
IsN64
Mips
::
SD_P8
:
Mips
::
SD
;
else
if
(
RC
==
Mips
::
FGR32RegisterClass
)
Opc
=
IsN64
Mips
::
SWC1_P8
:
Mips
::
SWC1
;
else
if
(
RC
==
Mips
::
AFGR64RegisterClass
)
Opc
=
Mips
::
SDC1
;
else
if
(
RC
==
Mips
::
FGR64RegisterClass
)
Opc
=
IsN64
Mips
::
SDC164_P8
:
Mips
::
SDC164
;
assert
(
Opc
&&
"Register class not handled!"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> static void ia64_output_function_end_prologue ( FILE * file ) { if ( ! flag_unwind_tables && ( ! flag_exceptions || USING_SJLJ_EXCEPTIONS ) ) return ; fputs ( "\t.body\n" , file ) ; } </s>

Emit the .body directive at the scheduled end of the prologue .


<s>
void
ARMHazardRecognizer
::
EmitInstruction
(
SUnit
*
SU
)
{
MachineInstr
*
MI
=
SU
->
getInstr
(
)
;
unsigned
Opcode
=
MI
->
getOpcode
(
)
;
if
(
ITBlockSize
)
{
ITBlockSize
;
}
else
if
(
Opcode
==
ARM
::
t2IT
)
{
unsigned
Mask
=
MI
->
getOperand
(
1
)
.
getImm
(
)
;
unsigned
NumTZ
=
CountTrailingZeros_32
(
Mask
)
;
assert
(
NumTZ
<=
3
&&
"Invalid IT mask!"
)
;
ITBlockSize
=
4
NumTZ
;
MachineBasicBlock
::
iterator
I
=
MI
;
for
(
unsigned
i
=
0
;
i
<
ITBlockSize
;
++
i
)
{
do
{
++
I
;
}
while
(
I
->
isDebugValue
(
)
)
;
ITBlockMIs
[
ITBlockSize
1
i
]
=
&
*
I
;
}
}
if
(
!
MI
->
isDebugValue
(
)
)
{
LastMI
=
MI
;
Stalls
=
0
;
}
ScoreboardHazardRecognizer
::
EmitInstruction
(
SU
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
bool
SystemZXPLINKFrameLowering
::
spillCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MBBI
,
ArrayRef
<
CalleeSavedInfo
>
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
if
(
CSI
.
empty
(
)
)
return
true
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
SystemZMachineFunctionInfo
*
ZFI
=
MF
.
getInfo
<
SystemZMachineFunctionInfo
>
(
)
;
const
SystemZSubtarget
&
Subtarget
=
MF
.
getSubtarget
<
SystemZSubtarget
>
(
)
;
const
TargetInstrInfo
*
TII
=
Subtarget
.
getInstrInfo
(
)
;
auto
&
Regs
=
Subtarget
.
getSpecialRegisters
<
SystemZXPLINK64Registers
>
(
)
;
SystemZ
::
GPRRegs
SpillGPRs
=
ZFI
->
getSpillGPRRegs
(
)
;
DebugLoc
DL
;
if
(
SpillGPRs
.
LowGPR
)
{
assert
(
SpillGPRs
.
LowGPR
!=
SpillGPRs
.
HighGPR
&&
"Should be saving multiple registers"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MBBI
,
DL
,
TII
->
get
(
SystemZ
::
STMG
)
)
;
addSavedGPR
(
MBB
,
MIB
,
SpillGPRs
.
LowGPR
,
false
)
;
addSavedGPR
(
MBB
,
MIB
,
SpillGPRs
.
HighGPR
,
false
)
;
MIB
.
addReg
(
Regs
.
getStackPointerRegister
(
)
)
;
MIB
.
addImm
(
SpillGPRs
.
GPROffset
)
;
auto
&
GRRegClass
=
SystemZ
::
GR64BitRegClass
;
for
(
unsigned
I
=
0
,
E
=
CSI
.
size
(
)
;
I
!=
E
;
++
I
)
{
unsigned
Reg
=
CSI
[
I
]
.
getReg
(
)
;
if
(
GRRegClass
.
contains
(
Reg
)
)
addSavedGPR
(
MBB
,
MIB
,
Reg
,
true
)
;
}
}
for
(
unsigned
I
=
0
,
E
=
CSI
.
size
(
)
;
I
!=
E
;
++
I
)
{
unsigned
Reg
=
CSI
[
I
]
.
getReg
(
)
;
if
(
SystemZ
::
FP64BitRegClass
.
contains
(
Reg
)
)
{
MBB
.
addLiveIn
(
Reg
)
;
TII
->
storeRegToStackSlot
(
MBB
,
MBBI
,
Reg
,
true
,
CSI
[
I
]
.
getFrameIdx
(
)
,
&
SystemZ
::
FP64BitRegClass
,
TRI
)
;
}
if
(
SystemZ
::
VR128BitRegClass
.
contains
(
Reg
)
)
{
MBB
.
addLiveIn
(
Reg
)
;
TII
->
storeRegToStackSlot
(
MBB
,
MBBI
,
Reg
,
true
,
CSI
[
I
]
.
getFrameIdx
(
)
,
&
SystemZ
::
VR128BitRegClass
,
TRI
)
;
}
}
return
true
;
}
</s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s>
bool
SNESInstrInfo
::
reverseBranchCondition
(
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
assert
(
Cond
.
size
(
)
==
1
&&
"Invalid SNES branch condition!"
)
;
SNESCC
::
CondCodes
CC
=
static_cast
<
SNESCC
::
CondCodes
>
(
Cond
[
0
]
.
getImm
(
)
)
;
Cond
[
0
]
.
setImm
(
getOppositeCondition
(
CC
)
)
;
return
false
;
}
</s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> const NVPTXSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> rtx standard_80387_constant_rtx ( int idx ) { int i ; if ( ! ext_80387_constants_init ) init_ext_80387_constants ( ) ; switch ( idx ) { case 3 : case 4 : case 5 : case 6 : case 7 : i = idx - 3 ; break ; default : gcc_unreachable ( ) ; } return const_double_from_real_value ( ext_80387_constants_table [ i ] , XFmode ) ; } </s>

Return the CONST_DOUBLE representing the 80387 constant that is loaded by the specified special instruction . The argument IDX matches the return value from standard_80387_constant_p .


<s> MCDisassembler :: DecodeStatus X86GenericDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & VStream , raw_ostream & CStream ) const { CommentStream = & CStream ; InternalInstruction InternalInstr ; dlog_t LoggerFn = logger ; if ( & VStream == & nulls ( ) ) LoggerFn = nullptr ; Region R ( Bytes , Address ) ; int Ret = decodeInstruction ( & InternalInstr , regionReader , ( const void * ) & R , LoggerFn , ( void * ) & VStream , ( const void * ) MII . get ( ) , Address , fMode ) ; if ( Ret ) { Size = InternalInstr . readerCursor - Address ; return Fail ; } else { Size = InternalInstr . length ; return ( ! translateInstruction ( Instr , InternalInstr , this ) ) ? Success : Fail ; } } </s>

Returns the disassembly of a single instruction .


<s> void ix86_expand_v1ti_shift ( enum rtx_code code , rtx operands [ ] ) { rtx op1 = force_reg ( V1TImode , operands [ 1 ] ) ; if ( ! CONST_INT_P ( operands [ 2 ] ) ) { rtx tmp1 = ix86_expand_v1ti_to_ti ( op1 ) ; rtx tmp2 = gen_reg_rtx ( TImode ) ; rtx ( * shift ) ( rtx , rtx , rtx ) = ( code == ASHIFT ) ? gen_ashlti3 : gen_lshrti3 ; emit_insn ( shift ( tmp2 , tmp1 , operands [ 2 ] ) ) ; rtx tmp3 = ix86_expand_ti_to_v1ti ( tmp2 ) ; emit_move_insn ( operands [ 0 ] , tmp3 ) ; return ; } HOST_WIDE_INT bits = INTVAL ( operands [ 2 ] ) & 127 ; if ( bits == 0 ) { emit_move_insn ( operands [ 0 ] , op1 ) ; return ; } if ( ( bits & 7 ) == 0 ) { rtx tmp = gen_reg_rtx ( V1TImode ) ; if ( code == ASHIFT ) emit_insn ( gen_sse2_ashlv1ti3 ( tmp , op1 , GEN_INT ( bits ) ) ) ; else emit_insn ( gen_sse2_lshrv1ti3 ( tmp , op1 , GEN_INT ( bits ) ) ) ; emit_move_insn ( operands [ 0 ] , tmp ) ; return ; } rtx tmp1 = gen_reg_rtx ( V1TImode ) ; if ( code == ASHIFT ) emit_insn ( gen_sse2_ashlv1ti3 ( tmp1 , op1 , GEN_INT ( 64 ) ) ) ; else emit_insn ( gen_sse2_lshrv1ti3 ( tmp1 , op1 , GEN_INT ( 64 ) ) ) ; rtx tmp2 = force_reg ( V2DImode , gen_lowpart ( V2DImode , tmp1 ) ) ; rtx tmp3 = gen_reg_rtx ( V2DImode ) ; if ( bits > 64 ) { if ( code == ASHIFT ) emit_insn ( gen_ashlv2di3 ( tmp3 , tmp2 , GEN_INT ( bits - 64 ) ) ) ; else emit_insn ( gen_lshrv2di3 ( tmp3 , tmp2 , GEN_INT ( bits - 64 ) ) ) ; } else { rtx tmp4 = force_reg ( V2DImode , gen_lowpart ( V2DImode , op1 ) ) ; rtx tmp5 = gen_reg_rtx ( V2DImode ) ; if ( code == ASHIFT ) emit_insn ( gen_ashlv2di3 ( tmp5 , tmp4 , GEN_INT ( bits ) ) ) ; else emit_insn ( gen_lshrv2di3 ( tmp5 , tmp4 , GEN_INT ( bits ) ) ) ; rtx tmp6 = gen_reg_rtx ( V2DImode ) ; if ( code == ASHIFT ) emit_insn ( gen_lshrv2di3 ( tmp6 , tmp2 , GEN_INT ( 64 - bits ) ) ) ; else emit_insn ( gen_ashlv2di3 ( tmp6 , tmp2 , GEN_INT ( 64 - bits ) ) ) ; emit_insn ( gen_iorv2di3 ( tmp3 , tmp5 , tmp6 ) ) ; } rtx tmp7 = force_reg ( V1TImode , gen_lowpart ( V1TImode , tmp3 ) ) ; emit_move_insn ( operands [ 0 ] , tmp7 ) ; } </s>

Expand V1TI mode shift ( of rtx_code CODE ) by constant .


<s> static bool s390_match_ccmode_set ( rtx set , machine_mode req_mode ) { machine_mode set_mode ; gcc_assert ( GET_CODE ( set ) == SET ) ; if ( GET_CODE ( SET_DEST ( set ) ) != REG || ! CC_REGNO_P ( REGNO ( SET_DEST ( set ) ) ) ) return 1 ; set_mode = GET_MODE ( SET_DEST ( set ) ) ; switch ( set_mode ) { case CCSmode : case CCSRmode : case CCUmode : case CCURmode : case CCLmode : case CCL1mode : case CCL2mode : case CCL3mode : case CCT1mode : case CCT2mode : case CCT3mode : case CCVEQmode : case CCVHmode : case CCVHUmode : case CCVFHmode : case CCVFHEmode : if ( req_mode != set_mode ) return 0 ; break ; case CCZmode : if ( req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode && req_mode != CCSRmode && req_mode != CCURmode ) return 0 ; break ; case CCAPmode : case CCANmode : if ( req_mode != CCAmode ) return 0 ; break ; default : gcc_unreachable ( ) ; } return ( GET_MODE ( SET_SRC ( set ) ) == set_mode ) ; } </s>

Return true if SET either does n't set the CC register , or else the source and destination have matching CC modes and that CC mode is at least as constrained as REQ_MODE .


Enable AARCH64_FL_ * flags EXTRA_FLAGS on top of the base Advanced SIMD set .


<s> const PPCRegisterInfo * getRegisterInfo ( ) const override { return & getInstrInfo ( ) -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


"%qs requires the %qs option and either the %qs or %qs option"

"%qs requires quad-precision floating-point arithmetic"

Raise an error message for a builtin function that is called without the appropriate target options being set .


"64-bit code requested on a subtarget that doesn't support it!"

This constructor initializes the data members to match that of the specified triple .


<s> virtual bool shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) override { ( void ) adjustFixupValue ( Fixup , Target . getConstant ( ) ) ; return false ; } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> void M68kFrameLowering :: emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , int64_t NumBytes , bool InEpilogue ) const { bool IsSub = NumBytes < 0 ; uint64_t Offset = IsSub ? - NumBytes : NumBytes ; uint64_t Chunk = ( 1LL << 31 ) - 1 ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { if ( Offset > Chunk ) { Register Reg ; if ( IsSub && ! isRegLiveIn ( MBB , M68k :: D0 ) ) Reg = M68k :: D0 ; else Reg = findDeadCallerSavedReg ( MBB , MBBI , TRI ) ; if ( Reg ) { unsigned Opc = M68k :: MOV32ri ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , Reg ) . addImm ( Offset ) ; Opc = IsSub ? M68k :: SUB32ar : M68k :: ADD32ar ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addReg ( Reg ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; Offset = 0 ; continue ; } } uint64_t ThisVal = std :: min ( Offset , Chunk ) ; MachineInstrBuilder MI = BuildStackAdjustment ( MBB , MBBI , DL , IsSub ? - ThisVal : ThisVal , InEpilogue ) ; if ( IsSub ) MI . setMIFlag ( MachineInstr :: FrameSetup ) ; else MI . setMIFlag ( MachineInstr :: FrameDestroy ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> bool MBlazeTargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createMBlazeISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool MSP430FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) BuildMI ( MBB , MI , DL , TII . get ( MSP430 :: POP16r ) , CSI [ i ] . getReg ( ) ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


"All AArch64 cmps should have 2 operands"

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Cpu0 Delay Slot Fille"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> rtx frv_split_abs ( rtx operands [ ] ) { rtx dest = operands [ 0 ] ; rtx src = operands [ 1 ] ; rtx cc_reg = operands [ 2 ] ; rtx cr_reg = operands [ 3 ] ; rtx ret ; start_sequence ( ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cc_reg , gen_rtx_COMPARE ( CCmode , src , const0_rtx ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cr_reg , gen_rtx_fmt_ee ( LT , CC_CCRmode , cc_reg , const0_rtx ) ) ) ; emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_NE ( CC_CCRmode , cr_reg , const0_rtx ) , gen_negsi2 ( dest , src ) ) ) ; if ( ! rtx_equal_p ( dest , src ) ) emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_EQ ( CC_CCRmode , cr_reg , const0_rtx ) , gen_rtx_SET ( VOIDmode , dest , src ) ) ) ; ret = get_insns ( ) ; end_sequence ( ) ; return ret ; } </s>

Split an integer abs operation returning a SEQUENCE containing all of the insns .


"lesser than 2 predicate operands are provided"

Convert the instruction into a predicated instruction .


<s> static int arm_tls_operand_p_1 ( rtx * x , void * data ATTRIBUTE_UNUSED ) { if ( GET_CODE ( * x ) == SYMBOL_REF ) return SYMBOL_REF_TLS_MODEL ( * x ) != 0 ; if ( GET_CODE ( * x ) == UNSPEC && XINT ( * x , 1 ) == UNSPEC_TLS ) return - 1 ; return 0 ; } </s>


<s> bool Z80TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * ) const { return true ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> bool X86AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { SMShadowTracker . startFunction ( MF ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Intrn = MF . getFunction ( ) -> hasInternalLinkage ( ) ; OutStreamer . BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer . EmitCOFFSymbolStorageClass ( Intrn ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer . EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer . EndCOFFSymbolDef ( ) ; } EmitFunctionHeader ( ) ; EmitFunctionBody ( ) ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> void AnalyzeFormalArguments ( const SmallVectorImpl < ISD :: InputArg > & Ins , CCAssignFn Fn ) { IsFixed . resize ( Ins . size ( ) , true ) ; CCState :: AnalyzeFormalArguments ( Ins , Fn ) ; } </s>

AnalyzeFormalArguments - Analyze an array of argument values , incorporating info about the formals into this state .


<s> bool HexagonPassConfig :: addInstSelector ( ) { PM . add ( createHexagonRemoveExtendOps ( getHexagonTargetMachine ( ) ) ) ; PM . add ( createHexagonISelDag ( getHexagonTargetMachine ( ) ) ) ; PM . add ( createHexagonPeephole ( ) ) ; return false ; } </s>

Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon


<s> bool X86TargetLowering :: decomposeMulByConstant ( LLVMContext & Context , EVT VT , SDValue C ) const { APInt MulC ; if ( ! ISD :: isConstantSplatVector ( C . getNode ( ) , MulC ) ) return false ; while ( getTypeAction ( Context , VT ) != TypeLegal ) VT = getTypeToTransformTo ( Context , VT ) ; if ( isOperationLegal ( ISD :: MUL , VT ) ) return false ; return ( MulC + 1 ) . isPowerOf2 ( ) || ( MulC - 1 ) . isPowerOf2 ( ) || ( 1 - MulC ) . isPowerOf2 ( ) || ( - ( MulC + 1 ) ) . isPowerOf2 ( ) ; } </s>

Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds .


<s> unsigned RISCVRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return RISCV :: X8 ; } </s>


<s> void print ( raw_ostream & OS , const TargetRegisterInfo * TRI = nullptr ) const { if ( isReg ( ) ) { OS << printReg ( Contents . R . Reg , TRI , Contents . R . Sub ) ; } if ( isImm ( ) ) { OS << Contents . ImmVal ; } } </s>

print - Print a debug representation of the operand to the given stream .


<s> void MipsELFStreamer :: createPendingLabelRelocs ( ) { MipsTargetELFStreamer * ELFTargetStreamer = static_cast < MipsTargetELFStreamer * > ( getTargetStreamer ( ) ) ; if ( ELFTargetStreamer -> isMicroMipsEnabled ( ) ) { for ( auto * L : Labels ) { auto * Label = cast < MCSymbolELF > ( L ) ; getAssembler ( ) . registerSymbol ( * Label ) ; Label -> setOther ( ELF :: STO_MIPS_MICROMIPS ) ; } } Labels . clear ( ) ; } </s>

Mark labels as microMIPS , if necessary for the subtarget .


<s> int avx_vpermilp_parallel ( rtx par , machine_mode mode ) { unsigned i , nelt = GET_MODE_NUNITS ( mode ) ; unsigned mask = 0 ; unsigned char ipar [ 16 ] = { } ; if ( XVECLEN ( par , 0 ) != ( int ) nelt ) return 0 ; for ( i = 0 ; i < nelt ; ++ i ) { rtx er = XVECEXP ( par , 0 , i ) ; unsigned HOST_WIDE_INT ei ; if ( ! CONST_INT_P ( er ) ) return 0 ; ei = INTVAL ( er ) ; if ( ei >= nelt ) return 0 ; ipar [ i ] = ei ; } switch ( mode ) { case E_V8DFmode : for ( i = 4 ; i < 6 ; ++ i ) { if ( ipar [ i ] < 4 || ipar [ i ] >= 6 ) return 0 ; mask |= ( ipar [ i ] - 4 ) << i ; } for ( i = 6 ; i < 8 ; ++ i ) { if ( ipar [ i ] < 6 ) return 0 ; mask |= ( ipar [ i ] - 6 ) << i ; } case E_V4DFmode : for ( i = 0 ; i < 2 ; ++ i ) { if ( ipar [ i ] >= 2 ) return 0 ; mask |= ipar [ i ] << i ; } for ( i = 2 ; i < 4 ; ++ i ) { if ( ipar [ i ] < 2 ) return 0 ; mask |= ( ipar [ i ] - 2 ) << i ; } break ; case E_V16SFmode : for ( i = 0 ; i < 8 ; ++ i ) if ( ipar [ i ] + 8 != ipar [ i + 8 ] ) return 0 ; case E_V8SFmode : for ( i = 0 ; i < 4 ; ++ i ) if ( ipar [ i ] + 4 != ipar [ i + 4 ] ) return 0 ; nelt = 4 ; case E_V2DFmode : case E_V4SFmode : for ( i = 0 ; i < nelt ; ++ i ) mask |= ipar [ i ] << ( i * ( nelt / 2 ) ) ; break ; default : gcc_unreachable ( ) ; } return mask + 1 ; } </s>

Helper for avx_vpermilps256_operand et al . This is also used by the expansion functions to turn the parallel back into a mask . The return value is 0 for no match and the imm8+1 for a match .


<s> unsigned RISCVTargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { switch ( Op . getOpcode ( ) ) { default : break ; case RISCVISD :: SLLW : case RISCVISD :: SRAW : case RISCVISD :: SRLW : case RISCVISD :: DIVW : case RISCVISD :: DIVUW : case RISCVISD :: REMUW : case RISCVISD :: ROLW : case RISCVISD :: RORW : case RISCVISD :: GREVW : case RISCVISD :: GORCW : case RISCVISD :: FSLW : case RISCVISD :: FSRW : case RISCVISD :: SHFLW : case RISCVISD :: UNSHFLW : case RISCVISD :: BCOMPRESSW : case RISCVISD :: BDECOMPRESSW : case RISCVISD :: FCVT_W_RV64 : case RISCVISD :: FCVT_WU_RV64 : return 33 ; case RISCVISD :: SHFL : case RISCVISD :: UNSHFL : { if ( Op . getValueType ( ) == MVT :: i64 && isa < ConstantSDNode > ( Op . getOperand ( 1 ) ) && ( Op . getConstantOperandVal ( 1 ) & 0x10 ) == 0 ) { unsigned Tmp = DAG . ComputeNumSignBits ( Op . getOperand ( 0 ) , Depth + 1 ) ; if ( Tmp > 32 ) return 33 ; } break ; } case RISCVISD :: VMV_X_S : if ( Op . getOperand ( 0 ) . getScalarValueSizeInBits ( ) > Subtarget . getXLen ( ) ) return 1 ; return Subtarget . getXLen ( ) - Op . getOperand ( 0 ) . getScalarValueSizeInBits ( ) + 1 ; } return 1 ; } </s>

Determine the number of bits in the operation that are sign bits .


<s> bool ARMBaseInstrInfo :: isPredicable ( const MachineInstr & MI ) const { if ( ! MI . isPredicable ( ) ) return false ; if ( MI . isBundle ( ) ) return false ; if ( ! isEligibleForITBlock ( & MI ) ) return false ; const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const ARMFunctionInfo * AFI = MF -> getInfo < ARMFunctionInfo > ( ) ; if ( ( MI . getDesc ( ) . TSFlags & ARMII :: DomainMask ) == ARMII :: DomainNEON ) return false ; const ARMSubtarget & ST = MF -> getSubtarget < ARMSubtarget > ( ) ; if ( ST . hardenSlsRetBr ( ) && isIndirectControlFlowNotComingBack ( MI ) ) return false ; if ( ST . hardenSlsBlr ( ) && isIndirectCall ( MI ) ) return false ; if ( AFI -> isThumb2Function ( ) ) { if ( getSubtarget ( ) . restrictIT ( ) ) return isV8EligibleForIT ( & MI ) ; } return true ; } </s>

Return true if the specified instruction can be predicated .

ARM ARM ARM ARM ARMII::DomainMask ARMII::DomainNEON ARM ARM


"Unexpected Kind in getPointerRegClass!"

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> int sh_contains_memref_p ( rtx insn ) { return for_each_rtx ( & PATTERN ( insn ) , & sh_contains_memref_p_1 , NULL ) ; } </s>

Return nonzero iff INSN contains a MEM .


<s> static void mips_output_64bit_xfer ( char direction , unsigned int gpreg , unsigned int fpreg ) { if ( TARGET_64BIT ) fprintf ( asm_out_file , "\tdm%cc1\t%s,%s\n" , direction , reg_names [ gpreg ] , reg_names [ fpreg ] ) ; else if ( ISA_HAS_MXHC1 ) { fprintf ( asm_out_file , "\tm%cc1\t%s,%s\n" , direction , reg_names [ gpreg + TARGET_BIG_ENDIAN ] , reg_names [ fpreg ] ) ; fprintf ( asm_out_file , "\tm%chc1\t%s,%s\n" , direction , reg_names [ gpreg + TARGET_LITTLE_ENDIAN ] , reg_names [ fpreg ] ) ; } else if ( TARGET_FLOATXX && direction == 't' ) { fprintf ( asm_out_file , "\tsw\t%s,0($sp)\n" , reg_names [ gpreg ] ) ; fprintf ( asm_out_file , "\tsw\t%s,4($sp)\n" , reg_names [ gpreg + 1 ] ) ; fprintf ( asm_out_file , "\tldc1\t%s,0($sp)\n" , reg_names [ fpreg ] ) ; } else if ( TARGET_FLOATXX && direction == 'f' ) { fprintf ( asm_out_file , "\tsdc1\t%s,0($sp)\n" , reg_names [ fpreg ] ) ; fprintf ( asm_out_file , "\tlw\t%s,0($sp)\n" , reg_names [ gpreg ] ) ; fprintf ( asm_out_file , "\tlw\t%s,4($sp)\n" , reg_names [ gpreg + 1 ] ) ; } else { fprintf ( asm_out_file , "\tm%cc1\t%s,%s\n" , direction , reg_names [ gpreg + TARGET_BIG_ENDIAN ] , reg_names [ fpreg ] ) ; fprintf ( asm_out_file , "\tm%cc1\t%s,%s\n" , direction , reg_names [ gpreg + TARGET_LITTLE_ENDIAN ] , reg_names [ fpreg + 1 ] ) ; } } </s>


"\tmove\t%s,%s\t\t# save current return address\n"

"\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from  stack\n"


<s> unsigned VEInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . getOpcode ( ) == VE :: STrii || MI . getOpcode ( ) == VE :: STLrii || MI . getOpcode ( ) == VE :: STUrii ) { if ( MI . getOperand ( 0 ) . isFI ( ) && MI . getOperand ( 1 ) . isImm ( ) && MI . getOperand ( 1 ) . getImm ( ) == 0 && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 0 ) . getIndex ( ) ; return MI . getOperand ( 3 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> MCSection * X86WindowsTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , unsigned & Align ) const { if ( Kind . isMergeableConst ( ) && C ) { const unsigned Characteristics = COFF :: IMAGE_SCN_CNT_INITIALIZED_DATA | COFF :: IMAGE_SCN_MEM_READ | COFF :: IMAGE_SCN_LNK_COMDAT ; std :: string COMDATSymName ; if ( Kind . isMergeableConst4 ( ) ) { if ( Align <= 4 ) { COMDATSymName = "__real@" + scalarConstantToHexString ( C ) ; Align = 4 ; } } else if ( Kind . isMergeableConst8 ( ) ) { if ( Align <= 8 ) { COMDATSymName = "__real@" + scalarConstantToHexString ( C ) ; Align = 8 ; } } else if ( Kind . isMergeableConst16 ( ) ) { if ( Align <= 16 ) { COMDATSymName = "__xmm@" + scalarConstantToHexString ( C ) ; Align = 16 ; } } else if ( Kind . isMergeableConst32 ( ) ) { if ( Align <= 32 ) { COMDATSymName = "__ymm@" + scalarConstantToHexString ( C ) ; Align = 32 ; } } if ( ! COMDATSymName . empty ( ) ) return getContext ( ) . getCOFFSection ( ".rdata" , Characteristics , Kind , COMDATSymName , COFF :: IMAGE_COMDAT_SELECT_ANY ) ; } return TargetLoweringObjectFile :: getSectionForConstant ( DL , Kind , C , Align ) ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> static bool loongarch_valid_pointer_mode ( scalar_int_mode mode ) { return mode == SImode || ( TARGET_64BIT && mode == DImode ) ; } </s>


<s> HOST_WIDE_INT arm_compute_initial_elimination_offset ( unsigned int from , unsigned int to ) { arm_stack_offsets * offsets ; offsets = arm_get_frame_offsets ( ) ; switch ( from ) { case ARG_POINTER_REGNUM : switch ( to ) { case THUMB_HARD_FRAME_POINTER_REGNUM : return 0 ; case FRAME_POINTER_REGNUM : return offsets -> soft_frame - offsets -> saved_args ; case ARM_HARD_FRAME_POINTER_REGNUM : if ( offsets -> frame == offsets -> saved_regs ) return 0 ; return ( frame_pointer_needed && cfun -> static_chain_decl != NULL && ! cfun -> machine -> uses_anonymous_args ) ? 4 : 0 ; case STACK_POINTER_REGNUM : return offsets -> outgoing_args - ( offsets -> saved_args + 4 ) ; default : gcc_unreachable ( ) ; } gcc_unreachable ( ) ; case FRAME_POINTER_REGNUM : switch ( to ) { case THUMB_HARD_FRAME_POINTER_REGNUM : return 0 ; case ARM_HARD_FRAME_POINTER_REGNUM : return offsets -> frame - offsets -> soft_frame ; case STACK_POINTER_REGNUM : return offsets -> outgoing_args - offsets -> soft_frame ; default : gcc_unreachable ( ) ; } gcc_unreachable ( ) ; default : gcc_unreachable ( ) ; } } </s>

Compute the distance from register FROM to register TO . These can be the arg pointer ( 26 ) , the soft frame pointer ( 25 ) , the stack pointer ( 13 ) or the hard frame pointer ( 11 ) . Typical stack layout looks like this : old stack pointer - > | | -- -- | | \ | | saved arguments for | | vararg functions | | / -- hard FP & arg pointer - > | | \ | | stack | | frame | | / -- | | \ | | call saved | | registers soft frame pointer - > | | / -- | | \ | | local | | variables | | / -- | | \ | | outgoing | | arguments current stack pointer - > | | / -- For a given funciton some or all of these stack compomnents may not be needed , giving rise to the possibility of eliminating some of the registers . The values returned by this function must reflect the behaviour of arm_expand_prologue ( ) and arm_compute_save_reg_mask ( ) . The sign of the number returned reflects the direction of stack growth , so the values are positive for all eliminations except from the soft frame pointer to the hard frame pointer .


<s> void HexagonPassConfig :: addPreEmitPass ( ) { bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) addPass ( createHexagonNewValueJump ( ) , false ) ; addPass ( createHexagonBranchRelaxation ( ) , false ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( createHexagonFixupHwLoops ( ) , false ) ; if ( EnableGenMux ) addPass ( createHexagonGenMux ( ) , false ) ; addPass ( createHexagonPacketizer ( ) , false ) ; } addPass ( createHexagonCallFrameInformation ( ) , false ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon


<s> rtx loongarch_rewrite_small_data ( rtx pattern ) { pattern = copy_insn ( pattern ) ; loongarch_rewrite_small_data_1 ( & pattern ) ; return pattern ; } </s>

Rewrite instruction pattern PATTERN so that it refers to small data using explicit relocations .


<s> bool SIInstrInfo :: isLegalRegOperand ( const MachineRegisterInfo & MRI , const MCOperandInfo & OpInfo , const MachineOperand & MO ) const { if ( ! MO . isReg ( ) ) return false ; Register Reg = MO . getReg ( ) ; const TargetRegisterClass * RC = Reg . isVirtual ( ) ? MRI . getRegClass ( Reg ) : RI . getPhysRegClass ( Reg ) ; const TargetRegisterClass * DRC = RI . getRegClass ( OpInfo . RegClass ) ; if ( MO . getSubReg ( ) ) { const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const TargetRegisterClass * SuperRC = RI . getLargestLegalSuperClass ( RC , * MF ) ; if ( ! SuperRC ) return false ; DRC = RI . getMatchingSuperRegClass ( SuperRC , DRC , MO . getSubReg ( ) ) ; if ( ! DRC ) return false ; } return RC -> hasSuperClassEq ( DRC ) ; } </s>

Check if MO ( a register operand ) is a legal register for the given operand description .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Cpu0 Emit GP Restore"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> const TargetRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
void
setReg
(
unsigned
Reg
)
{
assert
(
isRegBase
(
)
&&
"Invalid base register access!"
)
;
Base
.
Reg
=
Reg
;
}
</s>

Assigns the associated register for this edge .


<s> static int microblaze_address_insns ( rtx x , machine_mode mode ) { struct microblaze_address_info addr ; if ( microblaze_classify_address ( & addr , x , mode , false ) ) { switch ( addr . type ) { case ADDRESS_REG : if ( SMALL_INT ( addr . offset ) ) return 1 ; else return 2 ; case ADDRESS_CONST_INT : if ( SMALL_INT ( x ) ) return 1 ; else return 2 ; case ADDRESS_REG_INDEX : return 1 ; case ADDRESS_SYMBOLIC : case ADDRESS_SYMBOLIC_TXT_REL : case ADDRESS_GOTOFF : return 2 ; case ADDRESS_TLS : switch ( addr . tls_type ) { case TLS_GD : return 2 ; case TLS_LDM : return 2 ; case TLS_DTPREL : return 1 ; default : gcc_unreachable ( ) ; } default : break ; } } return 0 ; } </s>

Return the number of instructions needed to load or store a value of mode MODE at X . Return 0 if X is n't valid for MODE .


<s> bool Z80RegisterInfo :: requiresVirtualBaseRegisters ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers used for more efficient stack access .


<s> static bool epiphany_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) { if ( tree type = arg . type ) { if ( AGGREGATE_TYPE_P ( type ) && ( arg . mode == BLKmode || TYPE_NEEDS_CONSTRUCTING ( type ) ) ) return true ; } return false ; } </s>

For EPIPHANY , All aggregates and arguments greater than 8 bytes are passed by reference .


<s> static bool aarch64_vectorize_vec_perm_const ( machine_mode vmode , rtx target , rtx op0 , rtx op1 , const vec_perm_indices & sel ) { struct expand_vec_perm_d d ; if ( sel . ninputs ( ) == 1 || ( op0 && rtx_equal_p ( op0 , op1 ) ) ) d . one_vector_p = true ; else if ( sel . all_from_input_p ( 0 ) ) { d . one_vector_p = true ; op1 = op0 ; } else if ( sel . all_from_input_p ( 1 ) ) { d . one_vector_p = true ; op0 = op1 ; } else d . one_vector_p = false ; d . perm . new_vector ( sel . encoding ( ) , d . one_vector_p ? 1 : 2 , sel . nelts_per_input ( ) ) ; d . vmode = vmode ; d . vec_flags = aarch64_classify_vector_mode ( d . vmode ) ; d . target = target ; d . op0 = op0 ? force_reg ( vmode , op0 ) : NULL_RTX ; if ( op0 == op1 ) d . op1 = d . op0 ; else d . op1 = op1 ? force_reg ( vmode , op1 ) : NULL_RTX ; d . testing_p = ! target ; if ( ! d . testing_p ) return aarch64_expand_vec_perm_const_1 ( & d ) ; rtx_insn * last = get_last_insn ( ) ; bool ret = aarch64_expand_vec_perm_const_1 ( & d ) ; gcc_assert ( last == get_last_insn ( ) ) ; return ret ; } </s>


<s> virtual const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> const char * mangle_builtin_type ( const_tree type ) { if ( TYPE_NAME ( type ) && TREE_CODE ( TYPE_NAME ( type ) ) == TYPE_DECL ) type = TREE_TYPE ( TYPE_NAME ( type ) ) ; if ( tree attr = lookup_sve_type_attribute ( type ) ) if ( tree id = TREE_VALUE ( chain_index ( 2 , TREE_VALUE ( attr ) ) ) ) return IDENTIFIER_POINTER ( id ) ; return NULL ; } </s>

If TYPE is a built-in type defined by the RVV ABI , return the mangled name , otherwise return NULL .


<s> bool ARMTargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { if ( ! Subtarget -> supportsTailCall ( ) ) return false ; auto Attr = CI -> getParent ( ) -> getParent ( ) -> getFnAttribute ( "disable-tail-calls" ) ; if ( ! CI -> isTailCall ( ) || Attr . getValueAsString ( ) == "true" ) return false ; return true ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> unsigned MipsSEInstrInfo :: loadImmediate ( int64_t Imm , MachineBasicBlock & MBB , MachineBasicBlock :: iterator II , DebugLoc DL , unsigned * NewImm ) const { MipsAnalyzeImmediate AnalyzeImm ; const MipsSubtarget & STI = TM . getSubtarget < MipsSubtarget > ( ) ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; unsigned Size = STI . isABI_N64 ( ) ? 64 : 32 ; unsigned LUi = STI . isABI_N64 ( ) ? Mips :: LUi64 : Mips :: LUi ; unsigned ZEROReg = STI . isABI_N64 ( ) ? Mips :: ZERO_64 : Mips :: ZERO ; const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & Mips :: CPU64RegsRegClass : & Mips :: CPURegsRegClass ; bool LastInstrIsADDiu = NewImm ; const MipsAnalyzeImmediate :: InstSeq & Seq = AnalyzeImm . Analyze ( Imm , Size , LastInstrIsADDiu ) ; MipsAnalyzeImmediate :: InstSeq :: const_iterator Inst = Seq . begin ( ) ; assert ( Seq . size ( ) && ( ! LastInstrIsADDiu || ( Seq . size ( ) > 1 ) ) ) ; unsigned Reg = RegInfo . createVirtualRegister ( RC ) ; if ( Inst -> Opc == LUi ) BuildMI ( MBB , II , DL , get ( LUi ) , Reg ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; else BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , Reg ) . addReg ( ZEROReg ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; for ( ++ Inst ; Inst != Seq . end ( ) - LastInstrIsADDiu ; ++ Inst ) BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; if ( LastInstrIsADDiu ) * NewImm = Inst -> ImmOpnd ; return Reg ; } </s>

Emit a series of instructions to load an immediate .


<s>
const
char
*
m68k_output_scc_float
(
rtx_code
code
)
{
switch
(
code
)
{
case
EQ
:
return
"fseq %0"
;
case
NE
:
return
"fsne %0"
;
case
GT
:
return
"fsgt %0"
;
case
GTU
:
return
"fshi %0"
;
case
LT
:
return
"fslt %0"
;
case
GE
:
return
"fsge %0"
;
case
LE
:
return
"fsle %0"
;
case
ORDERED
:
return
"fsor %0"
;
case
UNORDERED
:
return
"fsun %0"
;
case
UNEQ
:
return
"fsueq %0"
;
case
UNGE
:
return
"fsuge %0"
;
case
UNGT
:
return
"fsugt %0"
;
case
UNLE
:
return
"fsule %0"
;
case
UNLT
:
return
"fsult %0"
;
case
LTGT
:
return
"fsogl %0"
;
default
:
gcc_unreachable
(
)
;
}
}
</s>

Return an output template for a floating point scc instruction with CODE .

m68k
"fseq %0"
"fsne %0"
"fsgt %0"
"fshi %0"
"fslt %0"
"fsge %0"
"fsle %0"
"fsor %0"
"fsun %0"
"fsueq %0"
"fsuge %0"
"fsugt %0"
"fsule %0"
"fsult %0"
"fsogl %0"


<s>
void
RISCVDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
MVT
XLenVT
=
Subtarget
->
getXLenVT
(
)
;
DEBUG
(
dbgs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
EVT
VT
=
Node
->
getValueType
(
0
)
;
if
(
Opcode
==
ISD
::
Constant
&&
VT
==
XLenVT
)
{
auto
*
ConstNode
=
cast
<
ConstantSDNode
>
(
Node
)
;
if
(
ConstNode
->
isNullValue
(
)
)
{
SDValue
New
=
CurDAG
->
getCopyFromReg
(
CurDAG
->
getEntryNode
(
)
,
SDLoc
(
Node
)
,
RISCV
::
X0
,
XLenVT
)
;
ReplaceNode
(
Node
,
New
.
getNode
(
)
)
;
return
;
}
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

RISCV
RISCV
"Selecting: "
"\n"
"== "
"\n"
1
0
ISD::Constant
RISCV::X0


<s> unsigned RISCVTargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { return RISCV :: X10 ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s>
void
WebAssemblyInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
auto
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
const
TargetRegisterClass
*
RC
=
TargetRegisterInfo
::
isVirtualRegister
(
DestReg
)
MRI
.
getRegClass
(
DestReg
)
:
MRI
.
getTargetRegisterInfo
(
)
->
getMinimalPhysRegClass
(
SrcReg
)
;
unsigned
CopyLocalOpcode
;
if
(
RC
==
&
WebAssembly
::
I32RegClass
)
CopyLocalOpcode
=
WebAssembly
::
COPY_LOCAL_I32
;
else
if
(
RC
==
&
WebAssembly
::
I64RegClass
)
CopyLocalOpcode
=
WebAssembly
::
COPY_LOCAL_I64
;
else
if
(
RC
==
&
WebAssembly
::
F32RegClass
)
CopyLocalOpcode
=
WebAssembly
::
COPY_LOCAL_F32
;
else
if
(
RC
==
&
WebAssembly
::
F64RegClass
)
CopyLocalOpcode
=
WebAssembly
::
COPY_LOCAL_F64
;
else
llvm_unreachable
(
"Unexpected register class"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
CopyLocalOpcode
)
,
DestReg
)
.
addReg
(
SrcReg
,
KillSrc
RegState
::
Kill
:
0
)
;
}
</s>


<s> ScheduleHazardRecognizer * ARMBaseInstrInfo :: CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II , const ScheduleDAG * DAG ) const { if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2Base ( ) ) return new ARMHazardRecognizer ( II , DAG ) ; return TargetInstrInfo :: CreateTargetPostRAHazardRecognizer ( II , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for by non-scheduling passes .


<s> unsigned LC3RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return LC3 :: SP ; } </s>


<s> void override_options ( void ) { if ( TARGET_G_FLOAT ) REAL_MODE_FORMAT ( DFmode ) = & vax_g_format ; } </s>

Set global variables as needed for the options enabled .


"getBranchTargetOpValue expects only expressions or immediates"

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s> void emit_pic_move ( rtx * operands , enum machine_mode mode ATTRIBUTE_UNUSED ) { rtx temp = reload_in_progress ? operands [ 0 ] : gen_reg_rtx ( Pmode ) ; if ( GET_CODE ( operands [ 0 ] ) == MEM && SYMBOLIC_CONST ( operands [ 1 ] ) ) operands [ 1 ] = force_reg ( SImode , operands [ 1 ] ) ; else operands [ 1 ] = legitimize_pic_address ( operands [ 1 ] , temp , pic_offset_table_rtx ) ; } </s>

Emit insns to move operands [ 1 ] into operands [ 0 ] .


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasV8_1aOps ( false ) , HasV8_2aOps ( false ) , HasFPARMv8 ( false ) , HasNEON ( false ) , HasCrypto ( false ) , HasCRC ( false ) , HasPerfMon ( false ) , HasFullFP16 ( false ) , HasZeroCycleRegMove ( false ) , HasZeroCycleZeroing ( false ) , StrictAlign ( false ) , ReserveX18 ( TT . isOSDarwin ( ) ) , IsLittle ( LittleEndian ) , CPUString ( CPU ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS ) ) , TSInfo ( ) , TLInfo ( TM , * this ) , CallLoweringInfo ( nullptr ) { } </s>

This constructor initializes the data members to match that of the specified triple .


"Pseudo opcode found in EmitInstruction()"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> rtx s390_emit_compare ( enum rtx_code code , rtx op0 , rtx op1 ) { enum machine_mode mode = s390_select_ccmode ( code , op0 , op1 ) ; rtx ret = NULL_RTX ; if ( s390_compare_emitted && ( s390_cc_modes_compatible ( GET_MODE ( s390_compare_emitted ) , mode ) == GET_MODE ( s390_compare_emitted ) ) ) ret = gen_rtx_fmt_ee ( code , VOIDmode , s390_compare_emitted , const0_rtx ) ; else { rtx cc = gen_rtx_REG ( mode , CC_REGNUM ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cc , gen_rtx_COMPARE ( mode , op0 , op1 ) ) ) ; ret = gen_rtx_fmt_ee ( code , VOIDmode , cc , const0_rtx ) ; } s390_compare_emitted = NULL_RTX ; return ret ; } </s>

Emit a compare instruction suitable to implement the comparison OP0 CODE OP1 . Return the correct condition RTL to be placed in the IF_THEN_ELSE of the conditional branch testing the result .


<s> void Cpu0FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


"passing %qT to argument %d of %qE, which"

" expects a single SVE vector rather than a tuple"

"passing single vector %qT to argument %d"

" of %qE, which expects a tuple of %d vectors"

Require argument ARGNO to be a single vector or a tuple of NUM_VECTORS vectors ; NUM_VECTORS is 1 for the former . Return the associated type suffix on success , using TYPE_SUFFIX_b for predicates . Report an error and return NUM_TYPE_SUFFIXES on failure .


<s> static void Query ( const MachineInstr & MI , AliasAnalysis & AA , bool & Read , bool & Write , bool & Effects , bool & StackPointer ) { assert ( ! MI . isTerminator ( ) ) ; if ( MI . isDebugInstr ( ) || MI . isPosition ( ) ) return ; if ( MI . mayLoad ( ) && ! MI . isDereferenceableInvariantLoad ( & AA ) ) Read = true ; if ( MI . mayStore ( ) ) { Write = true ; for ( auto MMO : MI . memoperands ( ) ) { const MachinePointerInfo & MPI = MMO -> getPointerInfo ( ) ; if ( MPI . V . is < const PseudoSourceValue * > ( ) ) { auto PSV = MPI . V . get < const PseudoSourceValue * > ( ) ; if ( const ExternalSymbolPseudoSourceValue * EPSV = dyn_cast < ExternalSymbolPseudoSourceValue > ( PSV ) ) if ( StringRef ( EPSV -> getSymbol ( ) ) == "__stack_pointer" ) { StackPointer = true ; } } } } else if ( MI . hasOrderedMemoryRef ( ) ) { switch ( MI . getOpcode ( ) ) { case WebAssembly :: DIV_S_I32 : case WebAssembly :: DIV_S_I64 : case WebAssembly :: REM_S_I32 : case WebAssembly :: REM_S_I64 : case WebAssembly :: DIV_U_I32 : case WebAssembly :: DIV_U_I64 : case WebAssembly :: REM_U_I32 : case WebAssembly :: REM_U_I64 : case WebAssembly :: I32_TRUNC_S_F32 : case WebAssembly :: I64_TRUNC_S_F32 : case WebAssembly :: I32_TRUNC_S_F64 : case WebAssembly :: I64_TRUNC_S_F64 : case WebAssembly :: I32_TRUNC_U_F32 : case WebAssembly :: I64_TRUNC_U_F32 : case WebAssembly :: I32_TRUNC_U_F64 : case WebAssembly :: I64_TRUNC_U_F64 : break ; default : if ( ! MI . isCall ( ) ) { Write = true ; Effects = true ; } break ; } } if ( MI . hasUnmodeledSideEffects ( ) ) { switch ( MI . getOpcode ( ) ) { case WebAssembly :: DIV_S_I32 : case WebAssembly :: DIV_S_I64 : case WebAssembly :: REM_S_I32 : case WebAssembly :: REM_S_I64 : case WebAssembly :: DIV_U_I32 : case WebAssembly :: DIV_U_I64 : case WebAssembly :: REM_U_I32 : case WebAssembly :: REM_U_I64 : case WebAssembly :: I32_TRUNC_S_F32 : case WebAssembly :: I64_TRUNC_S_F32 : case WebAssembly :: I32_TRUNC_S_F64 : case WebAssembly :: I64_TRUNC_S_F64 : case WebAssembly :: I32_TRUNC_U_F32 : case WebAssembly :: I64_TRUNC_U_F32 : case WebAssembly :: I32_TRUNC_U_F64 : case WebAssembly :: I64_TRUNC_U_F64 : break ; default : Effects = true ; break ; } } if ( MI . isCall ( ) ) { unsigned CalleeOpNo = WebAssembly :: getCalleeOpNo ( MI ) ; QueryCallee ( MI , CalleeOpNo , Read , Write , Effects , StackPointer ) ; } } </s>


<s> void AMDGPUPassConfig :: addIRPasses ( ) { disablePass ( & StackMapLivenessID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & PatchableFunctionID ) ; addPass ( createAMDGPUAlwaysInlinePass ( ) ) ; addPass ( createAlwaysInlinerPass ( ) ) ; addPass ( createBarrierNoopPass ( ) ) ; addPass ( createAMDGPUOpenCLImageTypeLoweringPass ( ) ) ; const AMDGPUTargetMachine & TM = getAMDGPUTargetMachine ( ) ; const AMDGPUSubtarget & ST = * TM . getSubtargetImpl ( ) ; if ( TM . getOptLevel ( ) > CodeGenOpt :: None && ST . isPromoteAllocaEnabled ( ) ) { addPass ( createAMDGPUPromoteAlloca ( & TM ) ) ; addPass ( createSROAPass ( ) ) ; } addStraightLineScalarOptimizationPasses ( ) ; TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addEarlyCSEOrGVNPass ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU


<s>
bool
AMDGPUAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Name
=
parseMnemonicSuffix
(
Name
)
;
Operands
.
push_back
(
AMDGPUOperand
::
CreateToken
(
this
,
Name
,
NameLoc
)
)
;
bool
IsMIMG
=
Name
.
startswith
(
"image_"
)
;
while
(
!
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
{
OperandMode
Mode
=
OperandMode_Default
;
if
(
IsMIMG
&&
isGFX10Plus
(
)
&&
Operands
.
size
(
)
==
2
)
Mode
=
OperandMode_NSA
;
OperandMatchResultTy
Res
=
parseOperand
(
Operands
,
Name
,
Mode
)
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
Parser
.
Lex
(
)
;
if
(
Res
!=
MatchOperand_Success
)
{
checkUnsupportedInstruction
(
Name
,
NameLoc
)
;
if
(
!
Parser
.
hasPendingError
(
)
)
{
StringRef
Msg
=
(
Res
==
MatchOperand_ParseFail
)
"failed parsing operand."
:
"not a valid operand."
;
Error
(
getLexer
(
)
.
getLoc
(
)
,
Msg
)
;
}
while
(
!
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
{
Parser
.
Lex
(
)
;
}
Parser
.
Lex
(
)
;
return
true
;
}
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

AMDGPU
AMDGPU
AMDGPU
"image_"
2
"failed parsing operand."
"not a valid operand."


<s> MachineInstrBuilder MipsInstrInfo :: genInstrWithNewOpc ( unsigned NewOpc , MachineBasicBlock :: iterator I ) const { MachineInstrBuilder MIB ; bool BranchWithZeroOperand = ( I -> isBranch ( ) && ! I -> isPseudo ( ) && I -> getOperand ( 1 ) . isReg ( ) && ( I -> getOperand ( 1 ) . getReg ( ) == Mips :: ZERO || I -> getOperand ( 1 ) . getReg ( ) == Mips :: ZERO_64 ) ) ; if ( BranchWithZeroOperand ) { switch ( NewOpc ) { case Mips :: BEQC : NewOpc = Mips :: BEQZC ; break ; case Mips :: BNEC : NewOpc = Mips :: BNEZC ; break ; case Mips :: BGEC : NewOpc = Mips :: BGEZC ; break ; case Mips :: BLTC : NewOpc = Mips :: BLTZC ; break ; case Mips :: BEQC64 : NewOpc = Mips :: BEQZC64 ; break ; case Mips :: BNEC64 : NewOpc = Mips :: BNEZC64 ; break ; } } MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , get ( NewOpc ) ) ; if ( NewOpc == Mips :: JIC || NewOpc == Mips :: JIALC || NewOpc == Mips :: JIC64 || NewOpc == Mips :: JIALC64 ) { if ( NewOpc == Mips :: JIALC || NewOpc == Mips :: JIALC64 ) MIB -> RemoveOperand ( 0 ) ; for ( unsigned J = 0 , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { MIB . addOperand ( I -> getOperand ( J ) ) ; } MIB . addImm ( 0 ) ; } else if ( BranchWithZeroOperand ) { MIB . addOperand ( I -> getOperand ( 0 ) ) ; for ( unsigned J = 2 , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { MIB . addOperand ( I -> getOperand ( J ) ) ; } } else { for ( unsigned J = 0 , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { MIB . addOperand ( I -> getOperand ( J ) ) ; } } MIB . copyImplicitOps ( * I ) ; MIB . setMemRefs ( I -> memoperands_begin ( ) , I -> memoperands_end ( ) ) ; return MIB ; } </s>

Create an instruction which has the same operands and memory operands as MI but has a new opcode .


<s> void NVPTXPassConfig :: addIRPasses ( ) { disablePass ( & PrologEpilogCodeInserterID ) ; disablePass ( & MachineCopyPropagationID ) ; disablePass ( & TailDuplicateID ) ; disablePass ( & StackMapLivenessID ) ; disablePass ( & LiveDebugValuesID ) ; disablePass ( & PostRAMachineSinkingID ) ; disablePass ( & PostRASchedulerID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & PatchableFunctionID ) ; disablePass ( & ShrinkWrapID ) ; const NVPTXSubtarget & ST = * getTM < NVPTXTargetMachine > ( ) . getSubtargetImpl ( ) ; addPass ( createNVVMReflectPass ( ST . getSmVersion ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createNVPTXImageOptimizerPass ( ) ) ; addPass ( createNVPTXAssignValidGlobalNamesPass ( ) ) ; addPass ( createGenericToNVVMPass ( ) ) ; addPass ( createNVPTXLowerArgsPass ( & getNVPTXTargetMachine ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addAddressSpaceInferencePasses ( ) ; addStraightLineScalarOptimizationPasses ( ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addEarlyCSEOrGVNPass ( ) ; if ( ! DisableLoadStoreVectorizer ) addPass ( createLoadStoreVectorizerPass ( ) ) ; addPass ( createSROAPass ( ) ) ; } } </s>

NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX


"-m64 requires PowerPC64 architecture, enabling"

The Darwin version of SUBTARGET_OVERRIDE_OPTIONS .


<s> SDValue KudeyarTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_Kudeyar ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> bool SystemZSubtarget :: enableSubRegLiveness ( ) const { return UseSubRegLiveness ; } </s>

Enable tracking of subregister liveness in register allocator .


<s> void UPTInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << StringRef ( getRegisterName ( RegNo ) ) ; } </s>


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
auto
RegName
=
[
]
(
unsigned
Reg
)
{
if
(
Reg
)
return
RISCVInstPrinter
::
getRegisterName
(
Reg
)
;
else
return
"noreg"
;
}
;
switch
(
Kind
)
{
case
KindTy
::
Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
KindTy
::
Register
:
OS
<<
"<register "
<<
RegName
(
getReg
(
)
)
<<
">"
;
break
;
case
KindTy
::
Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
case
KindTy
::
SystemRegister
:
OS
<<
"<sysreg: "
<<
getSysReg
(
)
<<
'>'
;
break
;
case
KindTy
::
SpecialCapRegister
:
OS
<<
"<specialcapreg: "
<<
getSpecialCapReg
(
)
<<
'>'
;
break
;
case
KindTy
::
VType
:
OS
<<
"<vtype: "
;
RISCVVType
::
printVType
(
getVType
(
)
,
OS
)
;
OS
<<
'>'
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

RISCV
RISCV
"noreg"
"<register "
">"
"'"
"'"
"<sysreg: "
"<specialcapreg: "
"<vtype: "
RISCV


<s> void ARMHazardRecognizer :: AdvanceCycle ( ) { if ( FpMLxStalls && -- FpMLxStalls == 0 ) LastMI = nullptr ; ScoreboardHazardRecognizer :: AdvanceCycle ( ) ; } </s>

AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled can not issue in the current cycle , either because of latency or resource conflicts .


<s> static bool frv_for_each_packet ( void ( * handle_packet ) ( void ) ) { rtx insn , next_insn ; frv_packet . issue_rate = frv_issue_rate ( ) ; if ( ! optimize || ! flag_schedule_insns_after_reload || ! TARGET_VLIW_BRANCH || frv_packet . issue_rate == 1 ) return false ; dfa_start ( ) ; frv_packet . dfa_state = alloca ( state_size ( ) ) ; frv_start_packet_block ( ) ; for ( insn = get_insns ( ) ; insn != 0 ; insn = next_insn ) { enum rtx_code code ; bool eh_insn_p ; code = GET_CODE ( insn ) ; next_insn = NEXT_INSN ( insn ) ; if ( code == CODE_LABEL ) { frv_finish_packet ( handle_packet ) ; frv_start_packet_block ( ) ; } if ( INSN_P ( insn ) ) switch ( GET_CODE ( PATTERN ( insn ) ) ) { case USE : case CLOBBER : case ADDR_VEC : case ADDR_DIFF_VEC : break ; default : if ( GET_CODE ( insn ) == CALL_INSN && frv_cpu_type == FRV_CPU_TOMCAT ) frv_finish_packet ( handle_packet ) ; eh_insn_p = ( find_reg_note ( insn , REG_EH_REGION , NULL ) != NULL ) ; if ( eh_insn_p && ! frv_issues_to_branch_unit_p ( insn ) ) frv_finish_packet ( handle_packet ) ; if ( ! frv_pack_insn_p ( insn ) ) { frv_finish_packet ( handle_packet ) ; while ( ! frv_pack_insn_p ( insn ) ) state_transition ( frv_packet . dfa_state , 0 ) ; } frv_add_insn_to_packet ( insn ) ; if ( code == CALL_INSN || code == JUMP_INSN || eh_insn_p ) frv_finish_packet ( handle_packet ) ; break ; } } frv_finish_packet ( handle_packet ) ; dfa_finish ( ) ; return true ; } </s>

If packing is enabled , divide the instructions into packets and return true . Call HANDLE_PACKET for each complete packet .


<s> static bool call_ABI_of_interest ( tree fndecl ) { if ( symtab -> state == EXPANSION ) { struct cgraph_node * c_node ; if ( fndecl == NULL_TREE ) return true ; if ( DECL_EXTERNAL ( fndecl ) ) return true ; c_node = cgraph_node :: get ( fndecl ) ; c_node = c_node -> ultimate_alias_target ( ) ; return ! c_node -> only_called_directly_p ( ) ; } return false ; } </s>

Return TRUE if a call to function FNDECL may be one that potentially affects the function calling ABI of the object file .


<s> static rtx bfin_expand_binop_builtin ( enum insn_code icode , tree exp , rtx target , int macflag ) { rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , 0 ) ; tree arg1 = CALL_EXPR_ARG ( exp , 1 ) ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; machine_mode op0mode = GET_MODE ( op0 ) ; machine_mode op1mode = GET_MODE ( op1 ) ; machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; machine_mode mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ 2 ] . mode ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ( op0mode == SImode || op0mode == VOIDmode ) && mode0 == HImode ) { op0mode = HImode ; op0 = gen_lowpart ( HImode , op0 ) ; } if ( ( op1mode == SImode || op1mode == VOIDmode ) && mode1 == HImode ) { op1mode = HImode ; op1 = gen_lowpart ( HImode , op1 ) ; } gcc_assert ( ( op0mode == mode0 || op0mode == VOIDmode ) && ( op1mode == mode1 || op1mode == VOIDmode ) ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ 2 ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; if ( macflag == - 1 ) pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; else pat = GEN_FCN ( icode ) ( target , op0 , op1 , GEN_INT ( macflag ) ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>

Subroutine of bfin_expand_builtin to take care of binop insns . MACFLAG is -1 if this is a normal binary op , or one of the MACFLAG_xxx constants .


"Couldn't get MachineMemOperand for store to stack."

"Only support 4-byte stores to stack now."

"Only support GPR32 stores to stack now."

Store the specified register of the given register class to the specified stack frame index .


<s> unsigned SIInstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL , int * BytesAdded ) const { if ( ! FBB && Cond . empty ( ) ) { BuildMI ( & MBB , DL , get ( AMDGPU :: S_BRANCH ) ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded = 4 ; return 1 ; } if ( Cond . size ( ) == 1 && Cond [ 0 ] . isReg ( ) ) { BuildMI ( & MBB , DL , get ( AMDGPU :: SI_NON_UNIFORM_BRCOND_PSEUDO ) ) . add ( Cond [ 0 ] ) . addMBB ( TBB ) ; return 1 ; } assert ( TBB && Cond [ 0 ] . isImm ( ) ) ; unsigned Opcode = getBranchOpcode ( static_cast < BranchPredicate > ( Cond [ 0 ] . getImm ( ) ) ) ; if ( ! FBB ) { Cond [ 1 ] . isUndef ( ) ; MachineInstr * CondBr = BuildMI ( & MBB , DL , get ( Opcode ) ) . addMBB ( TBB ) ; preserveCondRegFlags ( CondBr -> getOperand ( 1 ) , Cond [ 1 ] ) ; if ( BytesAdded ) * BytesAdded = 4 ; return 1 ; } assert ( TBB && FBB ) ; MachineInstr * CondBr = BuildMI ( & MBB , DL , get ( Opcode ) ) . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( AMDGPU :: S_BRANCH ) ) . addMBB ( FBB ) ; MachineOperand & CondReg = CondBr -> getOperand ( 1 ) ; CondReg . setIsUndef ( Cond [ 1 ] . isUndef ( ) ) ; CondReg . setIsKill ( Cond [ 1 ] . isKill ( ) ) ; if ( BytesAdded ) * BytesAdded = 8 ; return 2 ; } </s>

Insert branch code into the end of the specified MachineBasicBlock .


<s> MCSection * getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C ) const override { return ReadOnlySection ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> void WebAssemblyPassConfig :: addPostRegAlloc ( ) { } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> MCInst PPCInstrInfo :: getNop ( ) const { MCInst Nop ; Nop . setOpcode ( PPC :: NOP ) ; return Nop ; } </s>

Return the noop instruction to use for a noop .


<s>
unsigned
MipsInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
reverse_iterator
I
=
MBB
.
rbegin
(
)
,
REnd
=
MBB
.
rend
(
)
;
unsigned
removed
;
while
(
I
!=
REnd
&&
I
->
isDebugValue
(
)
)
++
I
;
if
(
I
==
REnd
)
return
0
;
MachineBasicBlock
::
iterator
FirstBr
=
++
I
.
getReverse
(
)
;
for
(
removed
=
0
;
I
!=
REnd
&&
removed
<
2
;
++
I
,
++
removed
)
if
(
!
getAnalyzableBrOpc
(
I
->
getOpcode
(
)
)
)
break
;
MBB
.
erase
(
(
I
)
.
getReverse
(
)
,
FirstBr
)
;
return
removed
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s> rtx iq2000_function_value ( tree valtype , tree func ATTRIBUTE_UNUSED ) { int reg = GP_RETURN ; enum machine_mode mode = TYPE_MODE ( valtype ) ; int unsignedp = TYPE_UNSIGNED ( valtype ) ; mode = promote_mode ( valtype , mode , & unsignedp , 1 ) ; return gen_rtx_REG ( mode , reg ) ; } </s>

Return register to use for a function return value with VALTYPE for function FUNC .


<s> bool ARMTargetLowering :: isVectorLoadExtDesirable ( SDValue ExtVal ) const { EVT VT = ExtVal . getValueType ( ) ; if ( ! isTypeLegal ( VT ) ) return false ; if ( auto * Ld = dyn_cast < MaskedLoadSDNode > ( ExtVal . getOperand ( 0 ) ) ) { if ( Ld -> isExpandingLoad ( ) ) return false ; } if ( Subtarget -> hasMVEIntegerOps ( ) ) return true ; if ( ExtVal -> use_empty ( ) || ! ExtVal -> use_begin ( ) -> isOnlyUserOf ( ExtVal . getNode ( ) ) ) return true ; SDNode * U = * ExtVal -> use_begin ( ) ; if ( ( U -> getOpcode ( ) == ISD :: ADD || U -> getOpcode ( ) == ISD :: SUB || U -> getOpcode ( ) == ISD :: SHL || U -> getOpcode ( ) == ARMISD :: VSHLIMM ) ) return false ; return true ; } </s>

Return true if folding a vector load into ExtVal ( a sign , zero , or any extend node ) is profitable .

ARM ARM 0 ISD::ADD ISD::SUB ISD::SHL ARMISD::VSHLIMM


<s> const char * name ( ) const noexcept override { return "switch" ; } </s>

Gets the name of the pass we are mixed into .


<s> bool addInstSelector ( ) override { addPass ( new J2DAGToDAGISel ( getJ2TargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s>
bool
WaitInsert
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
!
MF
.
getFunction
(
)
.
hasFnAttribute
(
Attribute
::
StrictFP
)
)
return
false
;
const
X86Subtarget
&
ST
=
MF
.
getSubtarget
<
X86Subtarget
>
(
)
;
const
X86InstrInfo
*
TII
=
ST
.
getInstrInfo
(
)
;
bool
Changed
=
false
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
for
(
MachineBasicBlock
::
iterator
MI
=
MBB
.
begin
(
)
;
MI
!=
MBB
.
end
(
)
;
++
MI
)
{
if
(
!
isX87Instruction
(
*
MI
)
)
continue
;
if
(
!
(
MI
->
mayRaiseFPException
(
)
||
MI
->
mayLoadOrStore
(
)
)
||
isX87ControlInstruction
(
*
MI
)
)
continue
;
MachineBasicBlock
::
iterator
AfterMI
=
std
::
next
(
MI
)
;
if
(
AfterMI
!=
MBB
.
end
(
)
&&
isX87Instruction
(
*
AfterMI
)
&&
!
isX87NonWaitingControlInstruction
(
*
AfterMI
)
)
continue
;
BuildMI
(
MBB
,
AfterMI
,
MI
->
getDebugLoc
(
)
,
TII
->
get
(
X86
::
WAIT
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"\nInsert wait after:\t"
<<
*
MI
)
;
++
MI
;
Changed
=
true
;
}
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool ARMBaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( ! MF . getTarget ( ) . Options . RealignStack ) return false ; if ( AFI -> isThumb1OnlyFunction ( ) ) return false ; if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ; if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) ) return true ; return MRI -> canReserveReg ( BasePtr ) ; } </s>

True if the stack can be realigned for the target .


<s>
const
char
*
pru_output_sign_extend
(
rtx
*
operands
)
{
static
char
buf
[
512
]
;
int
bufi
;
const
int
dst_sz
=
GET_MODE_SIZE
(
GET_MODE
(
operands
[
0
]
)
)
;
const
int
src_sz
=
GET_MODE_SIZE
(
GET_MODE
(
operands
[
1
]
)
)
;
char
ext_start
;
switch
(
src_sz
)
{
case
1
:
ext_start
=
'y'
;
break
;
case
2
:
ext_start
=
'z'
;
break
;
default
:
gcc_unreachable
(
)
;
}
gcc_assert
(
dst_sz
>
src_sz
)
;
bufi
=
snprintf
(
buf
,
sizeof
(
buf
)
,
"mov\t%%0, %%1\n\t"
"qbbc\t.+8, %%0, %d\n\t"
"fill\t%%%c0, %d"
,
sign_bit_position
(
operands
[
1
]
)
,
ext_start
,
dst_sz
src_sz
)
;
gcc_assert
(
bufi
>
0
)
;
gcc_assert
(
(
unsigned
int
)
bufi
<
sizeof
(
buf
)
)
;
return
buf
;
}
</s>

Output asm code for sign_extend operation .


"Cannot store this register to stack slot!"

Load the specified register of the given register class from the specified stack frame index .


<s> virtual const TargetFrameInfo * getFrameInfo ( ) const { return & FrameInfo ; } </s>

getFrameInfo - Return the frame info object for the current function .


<s> static void loongarch_set_frame_expr ( rtx frame_pattern ) { rtx insn ; insn = get_last_insn ( ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = alloc_EXPR_LIST ( REG_FRAME_RELATED_EXPR , frame_pattern , REG_NOTES ( insn ) ) ; } </s>

Make the last instruction frame-related and note that it performs the operation described by FRAME_PATTERN .


<s> static rtx frv_expand_mclracc_builtin ( tree call ) { enum insn_code icode = CODE_FOR_mclracc ; rtx pat ; rtx op0 = frv_read_argument ( call , 0 ) ; op0 = frv_int_to_acc ( icode , 0 , op0 ) ; if ( ! op0 ) return NULL_RTX ; pat = GEN_FCN ( icode ) ( op0 ) ; if ( pat ) emit_insn ( pat ) ; return NULL_RTX ; } </s>

Expand the MCLRACC builtin . This builtin takes a single accumulator number as argument .


<s> static unsigned int rest_of_insert_endbranch ( void ) { timevar_push ( TV_MACH_DEP ) ; rtx cet_eb ; rtx_insn * insn ; basic_block bb ; if ( ! lookup_attribute ( "nocf_check" , TYPE_ATTRIBUTES ( TREE_TYPE ( cfun -> decl ) ) ) && ! cgraph_node :: get ( cfun -> decl ) -> only_called_directly_p ( ) ) { cet_eb = gen_nop_endbr ( ) ; bb = ENTRY_BLOCK_PTR_FOR_FN ( cfun ) -> next_bb ; insn = BB_HEAD ( bb ) ; emit_insn_before ( cet_eb , insn ) ; } bb = 0 ; FOR_EACH_BB_FN ( bb , cfun ) { for ( insn = BB_HEAD ( bb ) ; insn != NEXT_INSN ( BB_END ( bb ) ) ; insn = NEXT_INSN ( insn ) ) { if ( CALL_P ( insn ) ) { if ( find_reg_note ( insn , REG_SETJMP , NULL ) == NULL ) continue ; cet_eb = gen_nop_endbr ( ) ; emit_insn_after_setloc ( cet_eb , insn , INSN_LOCATION ( insn ) ) ; continue ; } if ( JUMP_P ( insn ) && flag_cet_switch ) { rtx target = JUMP_LABEL ( insn ) ; if ( target == NULL_RTX || ANY_RETURN_P ( target ) ) continue ; rtx_insn * label = as_a < rtx_insn * > ( target ) ; rtx_insn * table = next_insn ( label ) ; if ( table == NULL_RTX || ! JUMP_TABLE_DATA_P ( table ) ) continue ; edge_iterator ei ; edge e ; basic_block dest_blk ; FOR_EACH_EDGE ( e , ei , bb -> succs ) { rtx_insn * insn ; dest_blk = e -> dest ; insn = BB_HEAD ( dest_blk ) ; gcc_assert ( LABEL_P ( insn ) ) ; cet_eb = gen_nop_endbr ( ) ; emit_insn_after ( cet_eb , insn ) ; } continue ; } if ( ( LABEL_P ( insn ) && LABEL_PRESERVE_P ( insn ) ) || ( NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_DELETED_LABEL ) ) { cet_eb = gen_nop_endbr ( ) ; emit_insn_after ( cet_eb , insn ) ; continue ; } } } timevar_pop ( TV_MACH_DEP ) ; return 0 ; } </s>


<s> static rtx m68k_get_gp ( void ) { if ( pic_offset_table_rtx == NULL_RTX ) pic_offset_table_rtx = gen_rtx_REG ( Pmode , PIC_REG ) ; crtl -> uses_pic_offset_table = 1 ; return pic_offset_table_rtx ; } </s>


<s> MachineBasicBlock :: iterator CJGFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const CJGInstrInfo & TII = * static_cast < const CJGInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; unsigned StackAlign = getStackAlignment ( ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr & Old = * I ; uint64_t Amount = Old . getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = nullptr ; if ( Old . getOpcode ( ) == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( CJG :: SUBri ) , CJG :: SP ) . addReg ( CJG :: SP ) . addImm ( Amount ) ; } else { assert ( Old . getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) ; uint64_t CalleeAmt = Old . getOperand ( 1 ) . getImm ( ) ; Amount -= CalleeAmt ; if ( Amount ) New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( CJG :: ADDri ) , CJG :: SP ) . addReg ( CJG :: SP ) . addImm ( Amount ) ; } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { MachineInstr & Old = * I ; MachineInstr * New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( CJG :: SUBri ) , CJG :: SP ) . addReg ( CJG :: SP ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"X86 FP Stackifier"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static int c6x_sched_reorder_1 ( rtx_insn * * ready , int * pn_ready , int clock_var ) { int n_ready = * pn_ready ; rtx_insn * * e_ready = ready + n_ready ; rtx_insn * * insnp ; int first_jump ; for ( insnp = ready ; insnp < e_ready ; insnp ++ ) { rtx_insn * insn = * insnp ; int icode = recog_memoized ( insn ) ; bool is_asm = ( icode < 0 && ( GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT || asm_noperands ( PATTERN ( insn ) ) >= 0 ) ) ; bool no_parallel = ( is_asm || icode == CODE_FOR_sploop || ( icode >= 0 && get_attr_type ( insn ) == TYPE_ATOMIC ) ) ; if ( ( no_parallel && ( ss . issued_this_cycle > 0 || clock_var < ss . delays_finished_at ) ) || c6x_registers_update ( insn ) || ( ss . issued_this_cycle > 0 && icode == CODE_FOR_sploop ) ) { memmove ( ready + 1 , ready , ( insnp - ready ) * sizeof ( rtx ) ) ; * ready = insn ; n_ready -- ; ready ++ ; } else if ( shadow_p ( insn ) ) { memmove ( ready + 1 , ready , ( insnp - ready ) * sizeof ( rtx ) ) ; * ready = insn ; } } first_jump = first_jump_index ( clock_var ) ; if ( first_jump != - 1 ) { int first_cycle = get_jump_cycle ( first_jump ) ; rtx first_cond = get_jump_cond ( first_jump ) ; int second_cycle = 0 ; if ( first_jump > 0 ) second_cycle = get_jump_cycle ( first_jump - 1 ) ; for ( insnp = ready ; insnp < e_ready ; insnp ++ ) { rtx_insn * insn = * insnp ; int icode = recog_memoized ( insn ) ; bool is_asm = ( icode < 0 && ( GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT || asm_noperands ( PATTERN ( insn ) ) >= 0 ) ) ; int this_cycles , rsrv_cycles ; enum attr_type type ; gcc_assert ( ! is_asm ) ; if ( icode < 0 ) continue ; this_cycles = get_attr_cycles ( insn ) ; rsrv_cycles = get_attr_reserve_cycles ( insn ) ; type = get_attr_type ( insn ) ; if ( type == TYPE_BRANCH || type == TYPE_CALL ) this_cycles ++ ; if ( clock_var + this_cycles <= first_cycle ) continue ; if ( ( first_jump > 0 && clock_var + this_cycles > second_cycle ) || clock_var + rsrv_cycles > first_cycle || ! predicate_insn ( insn , first_cond , false ) ) { memmove ( ready + 1 , ready , ( insnp - ready ) * sizeof ( rtx ) ) ; * ready = insn ; n_ready -- ; ready ++ ; } } } return n_ready ; } </s>

Helper function for the TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2 hooks . If scheduling an insn would be unsafe in the current cycle , move it down in the ready list and return the number of non-unsafe insns .


<s>
bool
ParseInstruction
(
ParseInstructionInfo
&
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
override
{
Operands
.
push_back
(
make_unique
<
WebAssemblyOperand
>
(
WebAssemblyOperand
::
Token
,
NameLoc
,
SMLoc
::
getFromPointer
(
NameLoc
.
getPointer
(
)
+
Name
.
size
(
)
)
,
WebAssemblyOperand
::
TokOp
{
StringRef
(
NameLoc
.
getPointer
(
)
,
Name
.
size
(
)
)
}
)
)
;
auto
NamePair
=
Name
.
split
(
'.'
)
;
if
(
NamePair
.
second
.
empty
(
)
)
std
::
swap
(
NamePair
.
first
,
NamePair
.
second
)
;
while
(
Lexer
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
auto
&
Tok
=
Lexer
.
getTok
(
)
;
switch
(
Tok
.
getKind
(
)
)
{
case
AsmToken
::
Identifier
:
{
auto
&
Id
=
Lexer
.
getTok
(
)
;
const
MCExpr
*
Val
;
SMLoc
End
;
if
(
Parser
.
parsePrimaryExpr
(
Val
,
End
)
)
return
Error
(
"Cannot parse symbol: "
,
Lexer
.
getTok
(
)
)
;
Operands
.
push_back
(
make_unique
<
WebAssemblyOperand
>
(
WebAssemblyOperand
::
Symbol
,
Id
.
getLoc
(
)
,
Id
.
getEndLoc
(
)
,
WebAssemblyOperand
::
SymOp
{
Val
}
)
)
;
break
;
}
case
AsmToken
::
Minus
:
Parser
.
Lex
(
)
;
if
(
Lexer
.
isNot
(
AsmToken
::
Integer
)
)
return
Error
(
"Expected integer instead got: "
,
Lexer
.
getTok
(
)
)
;
if
(
ParseOperandStartingWithInteger
(
true
,
Operands
,
NamePair
.
second
)
)
return
true
;
break
;
case
AsmToken
::
Integer
:
if
(
ParseOperandStartingWithInteger
(
false
,
Operands
,
NamePair
.
second
)
)
return
true
;
break
;
case
AsmToken
::
Real
:
{
double
Val
;
if
(
Tok
.
getString
(
)
.
getAsDouble
(
Val
,
false
)
)
return
Error
(
"Cannot parse real: "
,
Tok
)
;
Operands
.
push_back
(
make_unique
<
WebAssemblyOperand
>
(
WebAssemblyOperand
::
Float
,
Tok
.
getLoc
(
)
,
Tok
.
getEndLoc
(
)
,
WebAssemblyOperand
::
FltOp
{
Val
}
)
)
;
Parser
.
Lex
(
)
;
break
;
}
default
:
return
Error
(
"Unexpected token in operand: "
,
Tok
)
;
}
if
(
Lexer
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Expect
(
AsmToken
::
Comma
,
","
)
)
return
true
;
}
}
Parser
.
Lex
(
)
;
if
(
NamePair
.
second
==
"block"
||
NamePair
.
second
==
"loop"
)
{
Operands
.
push_back
(
make_unique
<
WebAssemblyOperand
>
(
WebAssemblyOperand
::
Integer
,
NameLoc
,
NameLoc
,
WebAssemblyOperand
::
IntOp
{
1
}
)
)
;
}
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

WebAssembly
WebAssembly
WebAssemblyOperand::Token
WebAssemblyOperand::TokOp
"Cannot parse symbol: "
WebAssembly
WebAssemblyOperand::Symbol
WebAssemblyOperand::SymOp
"Expected integer instead got: "
"Cannot parse real: "
WebAssembly
WebAssemblyOperand::Float
WebAssemblyOperand::FltOp
"Unexpected token in operand: "
","
"block"
"loop"
WebAssembly
WebAssemblyOperand::Integer
WebAssemblyOperand::IntOp
1


<s> unsigned TPCInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { case TPC :: SPILL_ARF_RESTORE : case TPC :: SPILL_DRF_RESTORE : case TPC :: SPILL_VRF_RESTORE : case TPC :: SPILL_VPRF_RESTORE : case TPC :: SPILL_IRF_RESTORE : case TPC :: SPILL_SRF_RESTORE : case TPC :: SPILL_ZRF_RESTORE : case TPC :: SPILL_SPRF_RESTORE : FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> TargetPassConfig * NPEngineTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new NPEnginePassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> bool ix86_fp_jump_nontrivial_p ( enum rtx_code code ) { enum rtx_code bypass_code , first_code , second_code ; if ( ! TARGET_CMOVE ) return true ; ix86_fp_comparison_codes ( code , & bypass_code , & first_code , & second_code ) ; return bypass_code != UNKNOWN || second_code != UNKNOWN ; } </s>

Return true if the CODE will result in nontrivial jump sequence .


<s> unsigned SparcMCCodeEmitter :: getBranchTargetOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , ( MCFixupKind ) Sparc :: fixup_sparc_br22 ) ) ; return 0 ; } </s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s> void X86PassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & LiveRangeShrinkID ) ; addPass ( createX86FixupSetCC ( ) ) ; addPass ( createX86OptimizeLEAs ( ) ) ; addPass ( createX86CallFrameOptimization ( ) ) ; addPass ( createX86AvoidStoreForwardingBlocks ( ) ) ; } addPass ( createX86SpeculativeLoadHardeningPass ( ) ) ; addPass ( createX86FlagsCopyLoweringPass ( ) ) ; addPass ( createX86DynAllocaExpander ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createX86PreTileConfigPass ( ) ) ; else addPass ( createX86FastPreTileConfigPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> TargetLowering :: ConstraintWeight LanaiTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & Info , const char * Constraint ) const { ConstraintWeight Weight = CW_Invalid ; Value * CallOperandVal = Info . CallOperandVal ; if ( CallOperandVal == nullptr ) return CW_Default ; switch ( * Constraint ) { case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'O' : if ( isa < ConstantInt > ( CallOperandVal ) ) Weight = CW_Constant ; break ; default : Weight = TargetLowering :: getSingleConstraintMatchWeight ( Info , Constraint ) ; break ; } return Weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> const char * XNCMTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return NULL ; case XNCMISD :: RET_FLAG : return "XNCMISD::RET_FLAG" ; case XNCMISD :: RETI_FLAG : return "XNCMISD::RETI_FLAG" ; case XNCMISD :: RRA : return "XNCMISD::RRA" ; case XNCMISD :: RLA : return "XNCMISD::RLA" ; case XNCMISD :: RRC : return "XNCMISD::RRC" ; case XNCMISD :: CALL : return "XNCMISD::CALL" ; case XNCMISD :: Wrapper : return "XNCMISD::Wrapper" ; case XNCMISD :: BR_CC : return "XNCMISD::BR_CC" ; case XNCMISD :: CMP : return "XNCMISD::CMP" ; case XNCMISD :: SELECT_CC : return "XNCMISD::SELECT_CC" ; case XNCMISD :: SHL : return "XNCMISD::SHL" ; case XNCMISD :: SRA : return "XNCMISD::SRA" ; } } </s>

getTargetNodeName - This method returns the name of a target specific

XNCM XNCM XNCMISD::RET_FLAG "XNCMISD::RET_FLAG" XNCMISD::RETI_FLAG "XNCMISD::RETI_FLAG" XNCMISD::RRA "XNCMISD::RRA" XNCMISD::RLA "XNCMISD::RLA" XNCMISD::RRC "XNCMISD::RRC" XNCMISD::CALL "XNCMISD::CALL" XNCMISD::Wrapper "XNCMISD::Wrapper" XNCMISD::BR_CC "XNCMISD::BR_CC" XNCMISD::CMP "XNCMISD::CMP" XNCMISD::SELECT_CC "XNCMISD::SELECT_CC" XNCMISD::SHL "XNCMISD::SHL" XNCMISD::SRA "XNCMISD::SRA"


<s> void PPCExpandISEL :: initialize ( MachineFunction & MFParam ) { MF = & MFParam ; TII = MF -> getSubtarget ( ) . getInstrInfo ( ) ; ISELInstructions . clear ( ) ; } </s>

Initialize the strategy after building the DAG for a new region .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createELFObjectWriter ( createELFObjectTargetWriter ( ) , OS , true ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> void GCNPassConfig :: addFastRegAlloc ( FunctionPass * RegAllocPass ) { addPass ( & SIFixSGPRLiveRangesID ) ; TargetPassConfig :: addFastRegAlloc ( RegAllocPass ) ; } </s>

addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast register allocation .


<s>
int
MBlazeRegisterInfo
::
getDwarfRegNum
(
unsigned
RegNum
,
bool
isEH
)
const
{
llvm_unreachable
(
"What is the dwarf register number"
)
;
return
1
;
}
</s>

Map a target register to an equivalent dwarf register number .

MBlaze
MBlaze
"What is the dwarf register number"
1


<s> void func_fma_steering :: analyze_fma_fmul_insn ( fma_forest * ref_forest , du_chain * chain , du_head_p head ) { fma_forest * forest ; fma_node * node = this -> get_fma_node ( chain -> insn ) ; if ( ! node ) { fma_root_node * root_node ; root_node = new fma_root_node ( this , chain , this -> m_next_forest_id ++ ) ; forest = root_node -> get_forest ( ) ; node = root_node ; this -> m_fma_forests . push_back ( forest ) ; } else forest = node -> get_forest ( ) ; node -> set_head ( head ) ; if ( ref_forest ) { ref_forest -> merge_forest ( forest ) ; return ; } for ( chain = head -> first ; chain ; chain = chain -> next_use ) { fma_node * child_fma ; rtx fma_rtx , * accum_rtx_p ; if ( ! is_fmul_fmac_insn ( chain -> insn , false ) ) continue ; fma_rtx = SET_SRC ( PATTERN ( chain -> insn ) ) ; if ( GET_CODE ( fma_rtx ) == NEG ) fma_rtx = XEXP ( fma_rtx , 0 ) ; accum_rtx_p = & XEXP ( fma_rtx , 2 ) ; if ( ! REG_P ( * accum_rtx_p ) ) accum_rtx_p = & XEXP ( * accum_rtx_p , 0 ) ; if ( accum_rtx_p != chain -> loc ) continue ; if ( this -> get_fma_node ( chain -> insn ) ) continue ; child_fma = new fma_node ( node , chain ) ; node -> add_child ( child_fma ) ; } } </s>

Allocate and initialize fma_node objects for the FMUL or FMADD/FMSUB instruction in CHAIN- > insn and its dependent FMADD/FMSUB instructions , all part of FOREST . For the children , the associated head is left untouched ( and thus null ) as this function will be called again when considering the chain where they are def . For the parent , the chain is given in HEAD .


<s> unsigned HexagonTTIImpl :: getScalarizationOverhead ( Type * Ty , const APInt & DemandedElts , bool Insert , bool Extract ) { return BaseT :: getScalarizationOverhead ( Ty , DemandedElts , Insert , Extract ) ; } </s>

Estimate the overhead of scalarizing an instruction .


<s> static rtx emit_add ( rtx dest , rtx src0 , rtx src1 ) { rtx insn ; insn = emit_insn ( gen_addsi3 ( dest , src0 , src1 ) ) ; return insn ; } </s>

Emit insns to set DSTREG to SRCREG + AMOUNT during the prologue or epilogue .


<s> bool AMDGPUCallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < Register > VRegs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; MFI -> setIfReturnsVoid ( ! Val ) ; if ( ! Val ) { MIRBuilder . buildInstr ( AMDGPU :: S_ENDPGM ) . addImm ( 0 ) ; return true ; } Register VReg = VRegs [ 0 ] ; const Function & F = MF . getFunction ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; if ( ! AMDGPU :: isShader ( F . getCallingConv ( ) ) ) return false ; const AMDGPUTargetLowering & TLI = * getTLI < AMDGPUTargetLowering > ( ) ; SmallVector < EVT , 4 > SplitVTs ; SmallVector < uint64_t , 4 > Offsets ; ArgInfo OrigArg { VReg , Val -> getType ( ) } ; setArgFlags ( OrigArg , AttributeList :: ReturnIndex , DL , F ) ; ComputeValueVTs ( TLI , DL , OrigArg . Ty , SplitVTs , & Offsets , 0 ) ; SmallVector < ArgInfo , 8 > SplitArgs ; CCAssignFn * AssignFn = CCAssignFnForReturn ( F . getCallingConv ( ) , false ) ; for ( unsigned i = 0 , e = Offsets . size ( ) ; i != e ; ++ i ) { Type * SplitTy = SplitVTs [ i ] . getTypeForEVT ( F . getContext ( ) ) ; SplitArgs . push_back ( { VRegs [ i ] , SplitTy , OrigArg . Flags , OrigArg . IsFixed } ) ; } auto RetInstr = MIRBuilder . buildInstrNoInsert ( AMDGPU :: SI_RETURN_TO_EPILOG ) ; OutgoingArgHandler Handler ( MIRBuilder , MRI , RetInstr , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . insertInstr ( RetInstr ) ; return true ; } </s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> bool Cpu0LongBranch :: runOnMachineFunction ( MachineFunction & F ) { const Cpu0Subtarget & STI = static_cast < const Cpu0Subtarget & > ( F . getSubtarget ( ) ) ; const Cpu0InstrInfo * TII = static_cast < const Cpu0InstrInfo * > ( STI . getInstrInfo ( ) ) ; LongBranchSeqSize = ! IsPIC ? 2 : 10 ; if ( ! STI . enableLongBranchPass ( ) ) return false ; if ( IsPIC && static_cast < const Cpu0TargetMachine & > ( TM ) . getABI ( ) . IsO32 ( ) && F . getInfo < Cpu0MachineFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; MF = & F ; initMBBInfo ( ) ; SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; int ShVal = 4 ; int64_t Offset = computeOffset ( I -> Br ) / ShVal ; if ( ! ForceLongBranch && isInt < 16 > ( Offset ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * 4 ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( IsPIC ) { uint64_t Address = 0 ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ; } for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) if ( I -> HasLongBranch ) expandToLongBranch ( * I ) ; MF -> RenumberBlocks ( ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> void frv_split_double_load ( rtx dest , rtx source ) { int regno = REGNO ( dest ) ; rtx dest1 = gen_highpart ( SImode , dest ) ; rtx dest2 = gen_lowpart ( SImode , dest ) ; rtx address = XEXP ( source , 0 ) ; if ( GET_CODE ( address ) == PRE_MODIFY || ! refers_to_regno_p ( regno , regno + 1 , address , NULL ) ) { emit_move_insn ( dest1 , change_address ( source , SImode , NULL ) ) ; emit_move_insn ( dest2 , frv_index_memory ( source , SImode , 1 ) ) ; } else { emit_move_insn ( dest2 , frv_index_memory ( source , SImode , 1 ) ) ; emit_move_insn ( dest1 , change_address ( source , SImode , NULL ) ) ; } } </s>

Split ( set DEST SOURCE ) , where DEST is a double register and SOURCE is a memory location that is not known to be dword-aligned .


<s> bool SVEIntrinsicOpts :: runOnModule ( Module & M ) { bool Changed = false ; SmallSetVector < Function * , 4 > Functions ; for ( auto & F : M . getFunctionList ( ) ) { if ( ! F . isDeclaration ( ) ) continue ; switch ( F . getIntrinsicID ( ) ) { case Intrinsic :: aarch64_sve_convert_from_svbool : case Intrinsic :: aarch64_sve_ptest_any : case Intrinsic :: aarch64_sve_ptest_first : case Intrinsic :: aarch64_sve_ptest_last : for ( auto I = F . user_begin ( ) , E = F . user_end ( ) ; I != E ; ) { auto * Inst = dyn_cast < Instruction > ( * I ++ ) ; Functions . insert ( Inst -> getFunction ( ) ) ; } break ; default : break ; } } if ( ! Functions . empty ( ) ) Changed |= optimizeFunctions ( Functions ) ; return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> static inline int startswith ( const char * str , const char * prefix ) { return strncmp ( str , prefix , strlen ( prefix ) ) == 0 ; } </s>

Return 1 if STR string starts with PREFIX .


<s>
bool
SystemZAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
;
MatchResult
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MatchingInlineAsm
)
;
switch
(
MatchResult
)
{
case
Match_Success
:
Inst
.
setLoc
(
IDLoc
)
;
Out
.
EmitInstruction
(
Inst
,
STI
)
;
return
false
;
case
Match_MissingFeature
:
{
assert
(
ErrorInfo
&&
"Unknown missing feature!"
)
;
std
::
string
Msg
=
"instruction requires:"
;
uint64_t
Mask
=
1
;
for
(
unsigned
I
=
0
;
I
<
sizeof
(
ErrorInfo
)
*
8
1
;
++
I
)
{
if
(
ErrorInfo
&
Mask
)
{
Msg
+=
" "
;
Msg
+=
getSubtargetFeatureName
(
ErrorInfo
&
Mask
)
;
}
Mask
<<=
1
;
}
return
Error
(
IDLoc
,
Msg
)
;
}
case
Match_InvalidOperand
:
{
SMLoc
ErrorLoc
=
IDLoc
;
if
(
ErrorInfo
!=
~
0ULL
)
{
if
(
ErrorInfo
>=
Operands
.
size
(
)
)
return
Error
(
IDLoc
,
"too few operands for instruction"
)
;
ErrorLoc
=
(
(
SystemZOperand
&
)
*
Operands
[
ErrorInfo
]
)
.
getStartLoc
(
)
;
if
(
ErrorLoc
==
SMLoc
(
)
)
ErrorLoc
=
IDLoc
;
}
return
Error
(
ErrorLoc
,
"invalid operand for instruction"
)
;
}
case
Match_MnemonicFail
:
return
Error
(
IDLoc
,
"invalid instruction"
)
;
}
llvm_unreachable
(
"Unexpected match type"
)
;
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


"Branch Fix Up pass failed to converge!"


<s> bool isConstant ( const MachineFrameInfo * ) const override { return false ; } </s>

Returns true if we know the value of all bits .


<s>
const
char
*
getPassName
(
)
const
{
return
"R600 Packetizer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> rtx mips_got_load ( rtx temp , rtx addr , enum mips_symbol_type type ) { rtx base , high , lo_sum_symbol ; base = mips_pic_base_register ( temp ) ; if ( temp != NULL && reg_overlap_mentioned_p ( base , temp ) ) temp = NULL ; high = mips_unspec_offset_high ( temp , base , addr , type ) ; lo_sum_symbol = mips_unspec_address ( addr , type ) ; if ( type == SYMBOL_GOTOFF_CALL ) return mips_unspec_call ( high , lo_sum_symbol ) ; else return PMODE_INSN ( gen_unspec_got , ( high , lo_sum_symbol ) ) ; } </s>

Create and return a GOT reference of type TYPE for address ADDR . TEMP , if nonnull , is a scratch Pmode base register .


<s> bool ARMPassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge && ! getARMSubtarget ( ) . isTargetNaCl ( ) ) addPass ( createGlobalMergePass ( TM ) ) ; return false ; } </s>


<s> static void block_move_sequence ( rtx dst_mem , rtx src_mem , int size , int align ) { rtx temp [ 2 ] ; machine_mode mode [ 2 ] ; int amount [ 2 ] ; bool active [ 2 ] ; int phase = 0 ; int next ; int offset_ld = 0 ; int offset_st = 0 ; rtx x ; x = XEXP ( dst_mem , 0 ) ; if ( ! REG_P ( x ) ) { x = force_reg ( Pmode , x ) ; dst_mem = replace_equiv_address ( dst_mem , x ) ; } x = XEXP ( src_mem , 0 ) ; if ( ! REG_P ( x ) ) { x = force_reg ( Pmode , x ) ; src_mem = replace_equiv_address ( src_mem , x ) ; } active [ 0 ] = active [ 1 ] = false ; do { next = phase ; phase ^= 1 ; if ( size > 0 ) { int next_amount ; next_amount = ( size >= 4 ? 4 : ( size >= 2 ? 2 : 1 ) ) ; next_amount = MIN ( next_amount , align ) ; amount [ next ] = next_amount ; mode [ next ] = mode_from_align [ next_amount ] ; temp [ next ] = gen_reg_rtx ( mode [ next ] ) ; x = adjust_address ( src_mem , mode [ next ] , offset_ld ) ; emit_insn ( gen_rtx_SET ( VOIDmode , temp [ next ] , x ) ) ; offset_ld += next_amount ; size -= next_amount ; active [ next ] = true ; } if ( active [ phase ] ) { active [ phase ] = false ; x = adjust_address ( dst_mem , mode [ phase ] , offset_st ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x , temp [ phase ] ) ) ; offset_st += amount [ phase ] ; } } while ( active [ next ] ) ; } </s>

Emit code to perform a block move with an offset sequence of ld/st instructions ( ... , ld 0 , st 1 , ld 1 , st 0 , ... ) . SIZE and ALIGN are known constants . DEST and SRC are registers . OFFSET is the known starting point for the output pattern .


"ARM64 Collect Linker Optimization Hint (LOH)"


<s> bool Thumb2RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> static rtx s390_execute_label ( rtx insn ) { if ( GET_CODE ( insn ) == INSN && GET_CODE ( PATTERN ( insn ) ) == PARALLEL && GET_CODE ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) ) == UNSPEC && XINT ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) , 1 ) == UNSPEC_EXECUTE ) return XVECEXP ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) , 0 , 2 ) ; return NULL_RTX ; } </s>

Check whether INSN is an execute . Return the label_ref to its execute target template if so , NULL_RTX otherwise .


<s> bool ARMBaseTargetMachine :: addPreRegAlloc ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( Subtarget . hasNEON ( ) ) PM . add ( createNEONPreAllocPass ( ) ) ; if ( OptLevel != CodeGenOpt :: None && ! DisableLdStOpti && ! Subtarget . isThumb ( ) ) PM . add ( createARMLoadStoreOptimizationPass ( true ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static std :: unique_ptr < MINA32Operand > CreateMem ( unsigned Base , const MCExpr * Off , SMLoc S , SMLoc E ) { auto Op = std :: make_unique < MINA32Operand > ( k_Memory ) ; Op -> Mem . Base = Base ; Op -> Mem . Off = Off ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>


<s> bool ARMPreAllocLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { if ( AssumeMisalignedLoadStores || skipFunction ( Fn . getFunction ( ) ) ) return false ; TD = & Fn . getDataLayout ( ) ; STI = & static_cast < const ARMSubtarget & > ( Fn . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; DT = & getAnalysis < MachineDominatorTree > ( ) ; MF = & Fn ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; bool Modified = DistributeIncrements ( ) ; for ( MachineBasicBlock & MFI : Fn ) Modified |= RescheduleLoadStoreInstrs ( & MFI ) ; return Modified ; } </s>


<s>
EVT
GBZ80TargetLowering
::
getSetCCResultType
(
const
DataLayout
&
DL
,
LLVMContext
&
,
EVT
VT
)
const
{
assert
(
!
VT
.
isVector
(
)
&&
"No GBZ80 SetCC type for vectors!"
)
;
return
MVT
::
i8
;
}
</s>

Return the value type to use for ISD : :SETCC .


";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n"


<s>
unsigned
TL45InstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
reverse_iterator
I
=
MBB
.
rbegin
(
)
,
REnd
=
MBB
.
rend
(
)
;
unsigned
removed
=
0
;
while
(
I
!=
REnd
&&
removed
<
2
)
{
if
(
I
->
isDebugInstr
(
)
)
{
++
I
;
continue
;
}
if
(
!
getAnalyzableBrOpc
(
I
->
getOpcode
(
)
)
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
rbegin
(
)
;
++
removed
;
}
return
removed
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s> static void assign_fp_registers ( const_tree field , HOST_WIDE_INT bitpos , assign_data_t * data ) { int nregs ; machine_mode mode ; if ( ! compute_fp_layout ( field , bitpos , data , & nregs , & mode ) ) return ; const int this_slotno = data -> slotno + bitpos / BITS_PER_WORD ; int regno = SPARC_FP_ARG_FIRST + this_slotno * 2 ; if ( GET_MODE_SIZE ( mode ) <= 4 && ( bitpos & 32 ) != 0 ) regno ++ ; int pos = bitpos / BITS_PER_UNIT ; do { rtx reg = gen_rtx_REG ( mode , regno ) ; XVECEXP ( data -> ret , 0 , data -> stack + data -> nregs ) = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( pos ) ) ; data -> nregs += 1 ; regno += GET_MODE_SIZE ( mode ) / 4 ; pos += GET_MODE_SIZE ( mode ) ; } while ( -- nregs > 0 ) ; } </s>

A subroutine of function_arg_record_value . Assign FIELD at position BITPOS to FP registers .


<s> static rtx loongarch_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return loongarch_function_value_1 ( NULL_TREE , NULL_TREE , mode ) ; } </s>


Do anything needed before RTL is emitted for each function .


<s>
void
MSP430InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
MCRegister
DestReg
,
MCRegister
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
;
if
(
MSP430
::
GR16RegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
MSP430
::
MOV16rr
;
else
if
(
MSP430
::
GR8RegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
MSP430
::
MOV8rr
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s>
void
CJGMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
if
(
Desc
.
getSize
(
)
!=
4
)
{
llvm_unreachable
(
"Unexpected instruction size!"
)
;
}
const
uint32_t
Binary
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
emitConstant
(
Binary
,
Desc
.
getSize
(
)
,
OS
)
;
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .

CJG
CJG
4
"Unexpected instruction size!"