<s> void expand_epilogue ( void ) { int size ; register int regno ; int return_size ; rtx scratch ; gcc_assert ( reload_completed == 1 ) ; size = get_frame_size ( ) ; if ( current_function_return_rtx == 0 ) return_size = 0 ; else if ( GET_CODE ( current_function_return_rtx ) == MEM ) return_size = HARD_REG_SIZE ; else return_size = GET_MODE_SIZE ( GET_MODE ( current_function_return_rtx ) ) ; if ( return_size > HARD_REG_SIZE && return_size <= 2 * HARD_REG_SIZE ) scratch = iy_reg ; else scratch = ix_reg ; for ( regno = SOFT_REG_LAST ; regno >= SOFT_REG_FIRST ; regno -- ) { if ( regs_ever_live [ regno ] && ! call_used_regs [ regno ] ) { emit_move_after_reload ( gen_rtx_REG ( HImode , regno ) , stack_pop_word , scratch ) ; } } if ( TARGET_M6812 && ( size > 4 || size == 3 ) ) { emit_insn ( gen_addhi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( size ) ) ) ; } else if ( ( ! optimize_size && size > 8 ) || ( optimize_size && size > 10 ) ) { rtx insn ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , gen_rtx_SET ( VOIDmode , stack_pointer_rtx , gen_rtx_PLUS ( HImode , stack_pointer_rtx , GEN_INT ( size ) ) ) , gen_rtx_CLOBBER ( VOIDmode , scratch ) ) ) ; emit_insn ( insn ) ; } else { int i ; for ( i = 2 ; i <= size ; i += 2 ) emit_move_after_reload ( scratch , stack_pop_word , scratch ) ; if ( size & 1 ) emit_insn ( gen_addhi3 ( stack_pointer_rtx , stack_pointer_rtx , const1_rtx ) ) ; } if ( current_function_interrupt ) { emit_move_after_reload ( gen_rtx_REG ( HImode , SOFT_SAVED_XY_REGNUM ) , stack_pop_word , scratch ) ; emit_move_after_reload ( gen_rtx_REG ( HImode , SOFT_Z_REGNUM ) , stack_pop_word , scratch ) ; emit_move_after_reload ( m68hc11_soft_tmp_reg , stack_pop_word , scratch ) ; } if ( frame_pointer_needed ) emit_move_after_reload ( hard_frame_pointer_rtx , stack_pop_word , scratch ) ; else if ( current_function_trap && return_size != 0 ) { rtx addr_reg = stack_pointer_rtx ; if ( ! TARGET_M6812 ) { emit_move_after_reload ( scratch , stack_pointer_rtx , 0 ) ; addr_reg = scratch ; } emit_move_after_reload ( gen_rtx_MEM ( HImode , gen_rtx_PLUS ( HImode , addr_reg , const1_rtx ) ) , d_reg , 0 ) ; if ( return_size > HARD_REG_SIZE ) emit_move_after_reload ( gen_rtx_MEM ( HImode , gen_rtx_PLUS ( HImode , addr_reg , GEN_INT ( 3 ) ) ) , ix_reg , 0 ) ; } emit_jump_insn ( gen_return ( ) ) ; } </s>


<s> bool function_checker :: require_immediate ( unsigned int argno , HOST_WIDE_INT min , HOST_WIDE_INT max ) const { gcc_assert ( argno < m_nargs ) ; tree arg = m_args [ argno ] ; if ( ! tree_fits_uhwi_p ( arg ) ) { report_non_ice ( argno ) ; return false ; } return require_immediate_range ( argno , min , max ) ; } </s>

Check that argument ARGNO is an integer constant expression and store its value in VALUE_OUT if so . The caller should first check that argument ARGNO exists .


Given the pattern ( X & ( C l > > / < < Y ) ) ==/ ! = 0 return true if it should be transformed into : ( ( X < < /l > > Y ) & C ) ==/ ! = 0 WARNING : if ' X ' is a constant , the fold may deadlock ! FIXME : we could avoid passing XC , but we ca n't use isConstOrConstSplat ( ) here because it can end up being not linked in .


<s> bool PPCSubtarget :: enableMachinePipeliner ( ) const { return ( CPUDirective == PPC :: DIR_PWR9 ) && EnableMachinePipeliner ; } </s>

True if the subtarget should run MachinePipeliner .


<s> bool ARMFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; unsigned PushOpc = AFI -> isThumbFunction ( ) ? ARM :: t2STMDB_UPD : ARM :: STMDB_UPD ; unsigned PushOneOpc = AFI -> isThumbFunction ( ) ? ARM :: t2STR_PRE : ARM :: STR_PRE ; unsigned FltOpc = ARM :: VSTMDDB_UPD ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & isARMArea1Register , MachineInstr :: FrameSetup ) ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & isARMArea2Register , MachineInstr :: FrameSetup ) ; emitPushInst ( MBB , MI , CSI , FltOpc , 0 , true , & isARMArea3Register , MachineInstr :: FrameSetup ) ; return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static int frv_string_begins_with ( tree name , const char * prefix ) { int prefix_len = strlen ( prefix ) ; return ( TREE_STRING_LENGTH ( name ) > prefix_len && strncmp ( TREE_STRING_POINTER ( name ) , prefix , prefix_len ) == 0 ) ; } </s>

Return true if NAME ( a STRING_CST node ) begins with PREFIX .


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s>
const
MCFixupKindInfo
&
SystemZMCAsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
SystemZ
::
NumTargetFixupKinds
]
=
{
{
"FK_390_PC12DBL"
,
4
,
12
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"FK_390_PC16DBL"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"FK_390_PC24DBL"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"FK_390_PC32DBL"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"FK_390_TLS_CALL"
,
0
,
0
,
0
}
}
;
if
(
Kind
>=
FirstLiteralRelocationKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
FK_NONE
)
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> static void alpha_conditional_register_usage ( void ) { int i ; if ( ! TARGET_FPREGS ) for ( i = 32 ; i < 63 ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 ; } </s>

On the Alpha , we use this to disable the floating-point registers when they do n't exist .


<s> void alpha_split_tmode_pair ( rtx operands [ 4 ] , machine_mode mode , bool fixup_overlap ) { switch ( GET_CODE ( operands [ 1 ] ) ) { case REG : operands [ 3 ] = gen_rtx_REG ( DImode , REGNO ( operands [ 1 ] ) + 1 ) ; operands [ 2 ] = gen_rtx_REG ( DImode , REGNO ( operands [ 1 ] ) ) ; break ; case MEM : operands [ 3 ] = adjust_address ( operands [ 1 ] , DImode , 8 ) ; operands [ 2 ] = adjust_address ( operands [ 1 ] , DImode , 0 ) ; break ; case CONST_INT : case CONST_DOUBLE : gcc_assert ( operands [ 1 ] == CONST0_RTX ( mode ) ) ; operands [ 2 ] = operands [ 3 ] = const0_rtx ; break ; default : gcc_unreachable ( ) ; } switch ( GET_CODE ( operands [ 0 ] ) ) { case REG : operands [ 1 ] = gen_rtx_REG ( DImode , REGNO ( operands [ 0 ] ) + 1 ) ; operands [ 0 ] = gen_rtx_REG ( DImode , REGNO ( operands [ 0 ] ) ) ; break ; case MEM : operands [ 1 ] = adjust_address ( operands [ 0 ] , DImode , 8 ) ; operands [ 0 ] = adjust_address ( operands [ 0 ] , DImode , 0 ) ; break ; default : gcc_unreachable ( ) ; } if ( fixup_overlap && reg_overlap_mentioned_p ( operands [ 0 ] , operands [ 3 ] ) ) { std :: swap ( operands [ 0 ] , operands [ 1 ] ) ; std :: swap ( operands [ 2 ] , operands [ 3 ] ) ; } } </s>

Split a TImode or TFmode move from OP [ 1 ] to OP [ 0 ] into a pair of DImode moves from OP [ 2,3 ] to OP [ 0,1 ] . If FIXUP_OVERLAP is true , guarantee that the sequence set ( OP [ 0 ] OP [ 2 ] ) set ( OP [ 1 ] OP [ 3 ] ) is valid . Naturally , output operand ordering is little-endian . This is used by * movtf_internal and * movti_internal .


<s> bool HexagonInstrInfo :: isTailCall ( const MachineInstr * MI ) const { if ( ! MI -> isBranch ( ) ) return false ; for ( auto & Op : MI -> operands ( ) ) if ( Op . isGlobal ( ) || Op . isSymbol ( ) ) return true ; return false ; } </s>

Determines whether Inst is a tail call instruction .


<s> bool RISCVTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , Align Alignment , MachineMemOperand :: Flags Flags , bool * Fast ) const { if ( ! VT . isVector ( ) ) return false ; EVT ElemVT = VT . getVectorElementType ( ) ; if ( Alignment >= ElemVT . getStoreSize ( ) ) { if ( Fast ) * Fast = true ; return true ; } return false ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> MachineBasicBlock :: iterator begin ( ) const { return getStart ( ) ; } </s>


<s> bool isStackIdSafeForLocalArea ( unsigned StackId ) const override { return StackId != TargetStackID :: SVEVector ; } </s>

This method returns whether or not it is safe for an object with the given stack id to be bundled into the local area .


"Instruction use requires option to be enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> const TargetRegisterInfo * XtensaSubtarget :: getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
bool
WaitcntBrackets
::
merge
(
const
WaitcntBrackets
&
Other
)
{
bool
StrictDom
=
false
;
VgprUB
=
std
::
max
(
VgprUB
,
Other
.
VgprUB
)
;
SgprUB
=
std
::
max
(
SgprUB
,
Other
.
SgprUB
)
;
for
(
auto
T
:
inst_counter_types
(
)
)
{
const
bool
OldOutOfOrder
=
counterOutOfOrder
(
T
)
;
const
unsigned
OldEvents
=
PendingEvents
&
WaitEventMaskForInst
[
T
]
;
const
unsigned
OtherEvents
=
Other
.
PendingEvents
&
WaitEventMaskForInst
[
T
]
;
if
(
OtherEvents
&
~
OldEvents
)
StrictDom
=
true
;
PendingEvents
|=
OtherEvents
;
const
unsigned
MyPending
=
ScoreUBs
[
T
]
ScoreLBs
[
T
]
;
const
unsigned
OtherPending
=
Other
.
ScoreUBs
[
T
]
Other
.
ScoreLBs
[
T
]
;
const
unsigned
NewUB
=
ScoreLBs
[
T
]
+
std
::
max
(
MyPending
,
OtherPending
)
;
if
(
NewUB
<
ScoreLBs
[
T
]
)
report_fatal_error
(
"waitcnt score overflow"
)
;
MergeInfo
M
;
M
.
OldLB
=
ScoreLBs
[
T
]
;
M
.
OtherLB
=
Other
.
ScoreLBs
[
T
]
;
M
.
MyShift
=
NewUB
ScoreUBs
[
T
]
;
M
.
OtherShift
=
NewUB
Other
.
ScoreUBs
[
T
]
;
ScoreUBs
[
T
]
=
NewUB
;
StrictDom
|=
mergeScore
(
M
,
LastFlat
[
T
]
,
Other
.
LastFlat
[
T
]
)
;
bool
RegStrictDom
=
false
;
for
(
int
J
=
0
;
J
<=
VgprUB
;
J
++
)
{
RegStrictDom
|=
mergeScore
(
M
,
VgprScores
[
T
]
[
J
]
,
Other
.
VgprScores
[
T
]
[
J
]
)
;
}
if
(
T
==
VM_CNT
)
{
for
(
int
J
=
0
;
J
<=
VgprUB
;
J
++
)
{
unsigned
char
NewVmemTypes
=
VgprVmemTypes
[
J
]
|
Other
.
VgprVmemTypes
[
J
]
;
RegStrictDom
|=
NewVmemTypes
!=
VgprVmemTypes
[
J
]
;
VgprVmemTypes
[
J
]
=
NewVmemTypes
;
}
}
if
(
T
==
LGKM_CNT
)
{
for
(
int
J
=
0
;
J
<=
SgprUB
;
J
++
)
{
RegStrictDom
|=
mergeScore
(
M
,
SgprScores
[
J
]
,
Other
.
SgprScores
[
J
]
)
;
}
}
if
(
RegStrictDom
&&
!
OldOutOfOrder
)
StrictDom
=
true
;
}
return
StrictDom
;
}
</s>


<s>
static
void
hwloop_fail
(
hwloop_info
loop
)
{
rtx
insn
,
test
,
testreg
;
if
(
dump_file
)
fprintf
(
dump_file
,
"splitting doloop insn %d\n"
,
INSN_UID
(
loop
->
loop_end
)
)
;
insn
=
gen_addsi3
(
loop
->
iter_reg
,
loop
->
iter_reg
,
constm1_rtx
)
;
if
(
loop
->
head
==
||
loop
->
iter_reg_used_outside
||
loop
->
iter_reg_used
||
TEST_HARD_REG_BIT
(
loop
->
regs_set_in_loop
,
REGNO
(
loop
->
iter_reg
)
)
||
loop
->
incoming_dest
!=
loop
->
head
||
EDGE_COUNT
(
loop
->
head
->
preds
)
!=
2
)
emit_insn_before
(
insn
,
loop
->
loop_end
)
;
else
{
rtx_insn
*
t
=
loop
->
start_label
;
while
(
!
NOTE_P
(
t
)
||
NOTE_KIND
(
t
)
!=
NOTE_INSN_BASIC_BLOCK
)
t
=
NEXT_INSN
(
t
)
;
emit_insn_after
(
insn
,
t
)
;
}
testreg
=
SET_DEST
(
XVECEXP
(
PATTERN
(
loop
->
loop_end
)
,
0
,
2
)
)
;
if
(
GET_CODE
(
testreg
)
==
SCRATCH
)
testreg
=
loop
->
iter_reg
;
else
emit_insn_before
(
gen_movsi
(
testreg
,
loop
->
iter_reg
)
,
loop
->
loop_end
)
;
test
=
gen_rtx_NE
(
VOIDmode
,
testreg
,
const0_rtx
)
;
insn
=
emit_jump_insn_before
(
gen_cbranchsi4
(
test
,
testreg
,
const0_rtx
,
loop
->
start_label
)
,
loop
->
loop_end
)
;
JUMP_LABEL
(
insn
)
=
loop
->
start_label
;
LABEL_NUSES
(
loop
->
start_label
)
++
;
delete_insn
(
loop
->
loop_end
)
;
}
</s>

A callback for the hw-doloop pass . Called when a loop we have discovered turns out not to be optimizable ; we have to split the doloop_end pattern into a subtract and a test .


<s> unsigned getNumFixupKinds ( ) const override { return Z80 :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> void initialize ( MCContext & Context ) { Ctx = & Context ; usesSgprAt ( SgprIndexUnusedMin = - 1 ) ; usesVgprAt ( VgprIndexUnusedMin = - 1 ) ; } </s>

Initialize the strategy after building the DAG for a new region .


<s> std :: pair < unsigned , const TargetRegisterClass * > RISCVTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , & RISCV :: GPRRegClass ) ; default : break ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s>
bool
GBZ80InstrInfo
::
isBranchOffsetInRange
(
unsigned
BranchOp
,
int64_t
BrOffset
)
const
{
switch
(
BranchOp
)
{
default
:
llvm_unreachable
(
"unexpected opcode!"
)
;
case
GB
::
CALL_cc_nn
:
case
GB
::
CALL_nn
:
case
GB
::
JP_cc_nn
:
case
GB
::
JP_nn
:
return
true
;
case
GB
::
JR_cc_e
:
case
GB
::
JR_e
:
return
BrOffset
>=
127
&&
BrOffset
<=
129
;
}
}
</s>

Determine if the branch target is in range .


<s> static tree arm_cxx_guard_type ( void ) { return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node ; } </s>

The generic C++ ABI says 64-bit ( long long ) . The EABI says 32-bit .


<s>
unsigned
SystemZRegisterInfo
::
getFrameRegister
(
const
MachineFunction
&
MF
)
const
{
assert
(
0
&&
"What is the frame register"
)
;
return
0
;
}
</s>


<s> void SIWholeQuadMode :: processBlock ( MachineBasicBlock & MBB , unsigned LiveMaskReg , bool isEntry ) { auto BII = Blocks . find ( & MBB ) ; if ( BII == Blocks . end ( ) ) return ; const BlockInfo & BI = BII -> second ; if ( ! ( BI . InNeeds & StateWQM ) ) return ; if ( ! isEntry && ! ( BI . Needs & StateExact ) && BI . OutNeeds != StateExact ) return ; unsigned SavedWQMReg = 0 ; bool WQMFromExec = isEntry ; char State = isEntry ? StateExact : StateWQM ; auto II = MBB . getFirstNonPHI ( ) , IE = MBB . end ( ) ; while ( II != IE ) { MachineInstr & MI = * II ; ++ II ; if ( TII -> isScalarUnit ( MI ) && ! MI . isTerminator ( ) ) continue ; if ( TargetInstrInfo :: isGenericOpcode ( MI . getOpcode ( ) ) ) { if ( MI . getNumExplicitOperands ( ) >= 1 ) { const MachineOperand & Op = MI . getOperand ( 0 ) ; if ( Op . isReg ( ) ) { if ( TRI -> isSGPRReg ( * MRI , Op . getReg ( ) ) ) { continue ; } } } } char Needs = 0 ; char OutNeeds = 0 ; auto InstrInfoIt = Instructions . find ( & MI ) ; if ( InstrInfoIt != Instructions . end ( ) ) { Needs = InstrInfoIt -> second . Needs ; OutNeeds = InstrInfoIt -> second . OutNeeds ; if ( OutNeeds == StateExact && MI . isTerminator ( ) ) { assert ( Needs == 0 ) ; Needs = StateExact ; } } if ( Needs && State != Needs ) { if ( Needs == StateExact ) { assert ( ! SavedWQMReg ) ; if ( ! WQMFromExec && ( OutNeeds & StateWQM ) ) SavedWQMReg = MRI -> createVirtualRegister ( & AMDGPU :: SReg_64RegClass ) ; toExact ( MBB , & MI , SavedWQMReg , LiveMaskReg ) ; } else { assert ( WQMFromExec == ( SavedWQMReg == 0 ) ) ; toWQM ( MBB , & MI , SavedWQMReg ) ; SavedWQMReg = 0 ; } State = Needs ; } } if ( ( BI . OutNeeds & StateWQM ) && State != StateWQM ) { assert ( WQMFromExec == ( SavedWQMReg == 0 ) ) ; toWQM ( MBB , MBB . end ( ) , SavedWQMReg ) ; } else if ( BI . OutNeeds == StateExact && State != StateExact ) { toExact ( MBB , MBB . end ( ) , 0 , LiveMaskReg ) ; } } </s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


"WebAssembly doesn't support non-C calling conventions"

"WebAssembly hasn't implemented inalloca arguments"

"WebAssembly hasn't implemented nest arguments"

"WebAssembly hasn't implemented cons regs arguments"

"WebAssembly hasn't implemented cons regs last arguments"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> bool AArch64PassConfig :: addPostRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableDeadRegisterElimination ) addPass ( createAArch64DeadRegisterDefinitions ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> static bool mips_interrupt_extra_call_saved_reg_p ( unsigned int regno ) { if ( ( ISA_HAS_HILO || TARGET_DSP ) && MD_REG_P ( regno ) ) return true ; if ( TARGET_DSP && DSP_ACC_REG_P ( regno ) ) return true ; if ( GP_REG_P ( regno ) && cfun -> machine -> use_shadow_register_set == SHADOW_SET_NO ) { if ( regno == GP_REG_FIRST ) return false ; if ( KERNEL_REG_P ( regno ) ) return false ; if ( regno == STACK_POINTER_REGNUM ) return false ; return call_used_regs [ regno ] ; } return false ; } </s>

Return true if REGNO is a register that is ordinarily call-clobbered but must nevertheless be preserved by an interrupt handler .


<s> bool AArch64PassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createAArch64PostSelectOptimize ( ) ) ; return false ; } </s>

This method should install a ( global ) instruction selector pass , which converts possibly generic instructions to fully target-specific instructions , thereby constraining all generic virtual registers to register classes .


<s> bool function_checker :: require_immediate ( unsigned int argno , HOST_WIDE_INT & value_out ) { gcc_assert ( argno < m_nargs ) ; tree arg = m_args [ argno ] ; if ( ! tree_fits_uhwi_p ( arg ) ) { report_non_ice ( location , fndecl , argno ) ; return false ; } value_out = tree_to_uhwi ( arg ) ; return true ; } </s>

Check that argument ARGNO is an integer constant expression and store its value in VALUE_OUT if so . The caller should first check that argument ARGNO exists .


<s> void ix86_expand_copysign ( rtx operands [ ] ) { enum machine_mode mode , vmode ; rtx dest , op0 , op1 , mask , nmask ; dest = operands [ 0 ] ; op0 = operands [ 1 ] ; op1 = operands [ 2 ] ; mode = GET_MODE ( dest ) ; vmode = mode == SFmode ? V4SFmode : V2DFmode ; if ( GET_CODE ( op0 ) == CONST_DOUBLE ) { rtvec v ; if ( real_isneg ( CONST_DOUBLE_REAL_VALUE ( op0 ) ) ) op0 = simplify_unary_operation ( ABS , mode , op0 , mode ) ; if ( op0 == CONST0_RTX ( mode ) ) op0 = CONST0_RTX ( vmode ) ; else { if ( mode == SFmode ) v = gen_rtvec ( 4 , op0 , CONST0_RTX ( SFmode ) , CONST0_RTX ( SFmode ) , CONST0_RTX ( SFmode ) ) ; else v = gen_rtvec ( 2 , op0 , CONST0_RTX ( DFmode ) ) ; op0 = force_reg ( vmode , gen_rtx_CONST_VECTOR ( vmode , v ) ) ; } mask = ix86_build_signbit_mask ( mode , 0 , 0 ) ; if ( mode == SFmode ) emit_insn ( gen_copysignsf3_const ( dest , op0 , op1 , mask ) ) ; else emit_insn ( gen_copysigndf3_const ( dest , op0 , op1 , mask ) ) ; } else { nmask = ix86_build_signbit_mask ( mode , 0 , 1 ) ; mask = ix86_build_signbit_mask ( mode , 0 , 0 ) ; if ( mode == SFmode ) emit_insn ( gen_copysignsf3_var ( dest , NULL , op0 , op1 , nmask , mask ) ) ; else emit_insn ( gen_copysigndf3_var ( dest , NULL , op0 , op1 , nmask , mask ) ) ; } } </s>

Expand a copysign operation . Special case operand 0 being a constant .


<s> void X86PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; addPass ( createX86LowerAMXIntrinsicsPass ( ) ) ; addPass ( createX86LowerAMXTypePass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: None ) addPass ( createX86PreAMXConfigPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedAccessPass ( ) ) ; addPass ( createX86PartialReductionPass ( ) ) ; } addPass ( createIndirectBrExpandPass ( ) ) ; const Triple & TT = TM -> getTargetTriple ( ) ; if ( TT . isOSWindows ( ) ) { if ( TT . getArch ( ) == Triple :: x86_64 ) { addPass ( createCFGuardDispatchPass ( ) ) ; } else { addPass ( createCFGuardCheckPass ( ) ) ; } } if ( TM -> Options . JMCInstrument ) addPass ( createJMCInstrumenterPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static bool aarch64_sve_pred_valid_immediate ( rtx x , simd_immediate_info * info ) { if ( aarch64_sve_ptrue_svpattern_p ( x , info ) ) return true ; if ( x == CONST0_RTX ( GET_MODE ( x ) ) ) { if ( info ) * info = simd_immediate_info ( DImode , 0 ) ; return true ; } rtx_vector_builder builder ; if ( ! aarch64_get_sve_pred_bits ( builder , x ) ) return false ; unsigned int elt_size = aarch64_widest_sve_pred_elt_size ( builder ) ; if ( int vl = aarch64_partial_ptrue_length ( builder , elt_size ) ) { machine_mode mode = aarch64_sve_pred_mode ( elt_size ) . require ( ) ; aarch64_svpattern pattern = aarch64_svpattern_for_vl ( mode , vl ) ; if ( pattern != AARCH64_NUM_SVPATTERNS ) { if ( info ) { scalar_int_mode int_mode = aarch64_sve_element_int_mode ( mode ) ; * info = simd_immediate_info ( int_mode , pattern ) ; } return true ; } } return false ; } </s>

Return true if X is a valid SVE predicate . If INFO is nonnull , use it to describe valid immediates .


<s> bool SIInstrInfo :: hasUnwantedEffectsWhenEXECEmpty ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( MI . mayStore ( ) && isSMRD ( MI ) ) return true ; if ( Opcode == AMDGPU :: S_SENDMSG || Opcode == AMDGPU :: S_SENDMSGHALT || Opcode == AMDGPU :: EXP || Opcode == AMDGPU :: EXP_DONE || Opcode == AMDGPU :: DS_ORDERED_COUNT ) return true ; if ( MI . isInlineAsm ( ) ) return true ; if ( Opcode == AMDGPU :: V_READFIRSTLANE_B32 || Opcode == AMDGPU :: V_READLANE_B32 ) return true ; return false ; } </s>

Whether we must prevent this instruction from executing with EXEC = 0 .


<s> SDValue AMDGPUTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & DL , SelectionDAG & DAG ) const { return DAG . getNode ( AMDGPUISD :: ENDPGM , DL , MVT :: Other , Chain ) ; } </s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .

AMDGPU AMDGPU ISD::OutputArg AMDGPUISD::ENDPGM MVT::Other


"Cannot store this register into a stack slot!"

Store the specified register of the given register class to the specified stack frame index .


<s> static void mips_sim_wait_units ( struct mips_sim * state , rtx insn ) { state_t tmp_state ; tmp_state = alloca ( state_size ( ) ) ; while ( state -> insns_left == 0 || ( memcpy ( tmp_state , state -> dfa_state , state_size ( ) ) , state_transition ( tmp_state , insn ) >= 0 ) ) mips_sim_next_cycle ( state ) ; } </s>

Advance simulation state STATE until the units required by instruction INSN are available .


<s>
static
HOST_WIDE_INT
rs6000_disable_incompatible_switches
(
void
)
{
HOST_WIDE_INT
ignore_masks
=
rs6000_isa_flags_explicit
;
size_t
i
,
j
;
static
const
struct
{
const
HOST_WIDE_INT
no_flag
;
const
HOST_WIDE_INT
dep_flags
;
const
char
*
const
name
;
}
flags
[
]
=
{
{
OPTION_MASK_POWER10
,
OTHER_POWER10_MASKS
,
"power10"
}
,
{
OPTION_MASK_P9_VECTOR
,
OTHER_P9_VECTOR_MASKS
,
"power9-vector"
}
,
{
OPTION_MASK_P8_VECTOR
,
OTHER_P8_VECTOR_MASKS
,
"power8-vector"
}
,
{
OPTION_MASK_VSX
,
OTHER_VSX_VECTOR_MASKS
,
"vsx"
}
,
{
OPTION_MASK_ALTIVEC
,
OTHER_ALTIVEC_MASKS
,
"altivec"
}
,
}
;
for
(
i
=
0
;
i
<
ARRAY_SIZE
(
flags
)
;
i
++
)
{
HOST_WIDE_INT
no_flag
=
flags
[
i
]
.
no_flag
;
if
(
(
rs6000_isa_flags
&
no_flag
)
==
0
&&
(
rs6000_isa_flags_explicit
&
no_flag
)
!=
0
)
{
HOST_WIDE_INT
dep_flags
=
flags
[
i
]
.
dep_flags
;
HOST_WIDE_INT
set_flags
=
(
rs6000_isa_flags_explicit
&
rs6000_isa_flags
&
dep_flags
)
;
if
(
set_flags
)
{
for
(
j
=
0
;
j
<
ARRAY_SIZE
(
rs6000_opt_masks
)
;
j
++
)
if
(
(
set_flags
&
rs6000_opt_masks
[
j
]
.
mask
)
!=
0
)
{
set_flags
&=
~
rs6000_opt_masks
[
j
]
.
mask
;
error
(
"%<-mno-%s%> turns off %<-m%s%>"
,
flags
[
i
]
.
name
,
rs6000_opt_masks
[
j
]
.
name
)
;
}
gcc_assert
(
!
set_flags
)
;
}
rs6000_isa_flags
&=
~
dep_flags
;
ignore_masks
|=
no_flag
|
dep_flags
;
}
}
return
ignore_masks
;
}
</s>

If the user used -mno-vsx , we need turn off all of the implicit ISA 2.06 , 2.07 , and 3.0 options that relate to the vector unit ( -mdirect-move , -mupper-regs-df , etc. ) . If the user used -mno-power8-vector , we need to turn off all of the implicit ISA 2.07 and 3.0 options that relate to the vector unit . If the user used -mno-power9-vector , we need to turn off all of the implicit ISA 3.0 options that relate to the vector unit . This function does not handle explicit options such as the user specifying -mdirect-move . These are handled in rs6000_option_override_internal , and the appropriate error is given if needed . We return a mask of all of the implicit options that should not be enabled by default .


<s> bool TL45TargetLowering :: shouldReduceLoadWidth ( SDNode * Load , ISD :: LoadExtType ExtTy , EVT NewVT ) const { return TargetLoweringBase :: shouldReduceLoadWidth ( Load , ExtTy , NewVT ) ; } </s>

Return true if we believe it is correct and profitable to reduce the load node to a smaller type .


<s> static void ia64_option_override ( void ) { unsigned int i ; cl_deferred_option * opt ; vec < cl_deferred_option > * v = ( vec < cl_deferred_option > * ) ia64_deferred_options ; if ( v ) FOR_EACH_VEC_ELT ( * v , i , opt ) { switch ( opt -> opt_index ) { case OPT_mfixed_range_ : fix_range ( opt -> arg ) ; break ; default : gcc_unreachable ( ) ; } } if ( TARGET_AUTO_PIC ) target_flags |= MASK_CONST_GP ; if ( optimize >= 3 ) flag_ira_loop_pressure = 1 ; ia64_section_threshold = ( OPTION_SET_P ( g_switch_value ) ? g_switch_value : IA64_DEFAULT_GVALUE ) ; init_machine_status = ia64_init_machine_status ; if ( flag_align_functions && ! str_align_functions ) str_align_functions = "64" ; if ( flag_align_loops && ! str_align_loops ) str_align_loops = "32" ; if ( TARGET_ABI_OPEN_VMS ) flag_no_common = 1 ; ia64_override_options_after_change ( ) ; } </s>


<s>
int
ConvergingVLIWScheduler
::
SchedulingCost
(
ReadyQueue
&
Q
,
SUnit
*
SU
,
SchedCandidate
&
Candidate
,
RegPressureDelta
&
Delta
,
bool
verbose
)
{
int
ResCount
=
1
;
if
(
!
SU
||
SU
->
isScheduled
)
return
ResCount
;
if
(
SU
->
isScheduleHigh
)
ResCount
+=
PriorityOne
;
if
(
Q
.
getID
(
)
==
TopQID
)
{
ResCount
+=
(
SU
->
getHeight
(
)
*
ScaleTwo
)
;
if
(
Top
.
ResourceModel
->
isResourceAvailable
(
SU
)
)
ResCount
<<=
FactorOne
;
}
else
{
ResCount
+=
(
SU
->
getDepth
(
)
*
ScaleTwo
)
;
if
(
Bot
.
ResourceModel
->
isResourceAvailable
(
SU
)
)
ResCount
<<=
FactorOne
;
}
unsigned
NumNodesBlocking
=
0
;
if
(
Q
.
getID
(
)
==
TopQID
)
{
for
(
SUnit
::
const_succ_iterator
I
=
SU
->
Succs
.
begin
(
)
,
E
=
SU
->
Succs
.
end
(
)
;
I
!=
E
;
++
I
)
if
(
getSingleUnscheduledPred
(
I
->
getSUnit
(
)
)
==
SU
)
++
NumNodesBlocking
;
}
else
{
for
(
SUnit
::
const_pred_iterator
I
=
SU
->
Preds
.
begin
(
)
,
E
=
SU
->
Preds
.
end
(
)
;
I
!=
E
;
++
I
)
if
(
getSingleUnscheduledSucc
(
I
->
getSUnit
(
)
)
==
SU
)
++
NumNodesBlocking
;
}
ResCount
+=
(
NumNodesBlocking
*
ScaleTwo
)
;
ResCount
-=
(
Delta
.
Excess
.
UnitIncrease
*
PriorityThree
)
;
ResCount
-=
(
Delta
.
CriticalMax
.
UnitIncrease
*
PriorityThree
)
;
DEBUG
(
if
(
verbose
)
dbgs
(
)
<<
" Total("
<<
ResCount
<<
")"
)
;
return
ResCount
;
}
</s>

Single point to compute overall scheduling cost .


<s> static void mips_sim_finish_insn ( struct mips_sim * state , rtx_insn * insn ) { if ( JUMP_P ( insn ) ) mips_sim_issue_nop ( state ) ; switch ( GET_CODE ( SEQ_BEGIN ( insn ) ) ) { case CODE_LABEL : case CALL_INSN : mips_sim_reset ( state ) ; break ; case JUMP_INSN : if ( INSN_ANNULLED_BRANCH_P ( SEQ_BEGIN ( insn ) ) ) mips_sim_reset ( state ) ; break ; default : break ; } } </s>

Update simulation state STATE so that it 's ready to accept the instruction after INSN . INSN should be part of the main rtl chain , not a member of a SEQUENCE .


<s> static bool aarch64_gimple_fold_builtin ( gimple_stmt_iterator * gsi ) { gcall * stmt = as_a < gcall * > ( gsi_stmt ( * gsi ) ) ; tree fndecl = gimple_call_fndecl ( stmt ) ; unsigned int code = DECL_MD_FUNCTION_CODE ( fndecl ) ; unsigned int subcode = code >> AARCH64_BUILTIN_SHIFT ; gimple * new_stmt = NULL ; switch ( code & AARCH64_BUILTIN_CLASS ) { case AARCH64_BUILTIN_GENERAL : new_stmt = aarch64_general_gimple_fold_builtin ( subcode , stmt ) ; break ; case AARCH64_BUILTIN_SVE : new_stmt = aarch64_sve :: gimple_fold_builtin ( subcode , gsi , stmt ) ; break ; } if ( ! new_stmt ) return false ; gsi_replace ( gsi , new_stmt , true ) ; return true ; } </s>


<s>
void
SIInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
Register
SrcReg
,
bool
isKill
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
SIMachineFunctionInfo
*
MFI
=
MF
->
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MachineFrameInfo
&
FrameInfo
=
MF
->
getFrameInfo
(
)
;
const
DebugLoc
&
DL
=
MBB
.
findDebugLoc
(
MI
)
;
MachinePointerInfo
PtrInfo
=
MachinePointerInfo
::
getFixedStack
(
*
MF
,
FrameIndex
)
;
MachineMemOperand
*
MMO
=
MF
->
getMachineMemOperand
(
PtrInfo
,
MachineMemOperand
::
MOStore
,
FrameInfo
.
getObjectSize
(
FrameIndex
)
,
FrameInfo
.
getObjectAlign
(
FrameIndex
)
)
;
unsigned
SpillSize
=
TRI
->
getSpillSize
(
*
RC
)
;
if
(
RI
.
isSGPRClass
(
RC
)
)
{
MFI
->
setHasSpilledSGPRs
(
)
;
assert
(
SrcReg
!=
AMDGPU
::
M0
&&
"m0 should not be spilled"
)
;
assert
(
SrcReg
!=
AMDGPU
::
EXEC_LO
&&
SrcReg
!=
AMDGPU
::
EXEC_HI
&&
SrcReg
!=
AMDGPU
::
EXEC
&&
"exec should not be spilled"
)
;
const
MCInstrDesc
&
OpDesc
=
get
(
getSGPRSpillSaveOpcode
(
SpillSize
)
)
;
if
(
SrcReg
.
isVirtual
(
)
&&
SpillSize
==
4
)
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
MRI
.
constrainRegClass
(
SrcReg
,
&
AMDGPU
::
SReg_32_XM0_XEXECRegClass
)
;
}
BuildMI
(
MBB
,
MI
,
DL
,
OpDesc
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIndex
)
.
addMemOperand
(
MMO
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
,
RegState
::
Implicit
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
,
RegState
::
Implicit
)
;
if
(
RI
.
spillSGPRToVGPR
(
)
)
FrameInfo
.
setStackID
(
FrameIndex
,
TargetStackID
::
SGPRSpill
)
;
return
;
}
unsigned
Opcode
=
RI
.
hasAGPRs
(
RC
)
getAGPRSpillSaveOpcode
(
SpillSize
)
:
getVGPRSpillSaveOpcode
(
SpillSize
)
;
MFI
->
setHasSpilledVGPRs
(
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opcode
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIndex
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>


<s> bool aarch64_simd_check_vect_par_cnst_half ( rtx op , machine_mode mode , bool high ) { int nelts ; if ( ! VECTOR_MODE_P ( mode ) || ! GET_MODE_NUNITS ( mode ) . is_constant ( & nelts ) ) return false ; rtx ideal = aarch64_simd_vect_par_cnst_half ( mode , nelts , high ) ; HOST_WIDE_INT count_op = XVECLEN ( op , 0 ) ; HOST_WIDE_INT count_ideal = XVECLEN ( ideal , 0 ) ; int i = 0 ; if ( count_op != count_ideal ) return false ; for ( i = 0 ; i < count_ideal ; i ++ ) { rtx elt_op = XVECEXP ( op , 0 , i ) ; rtx elt_ideal = XVECEXP ( ideal , 0 , i ) ; if ( ! CONST_INT_P ( elt_op ) || INTVAL ( elt_ideal ) != INTVAL ( elt_op ) ) return false ; } return true ; } </s>

Check OP for validity as a PARALLEL RTX vector with elements numbering the lanes of either the high ( HIGH == TRUE ) or low lanes , from the perspective of the architecture . See the diagram above aarch64_simd_vect_par_cnst_half for more details .


<s> bool MipsAsmBackend :: isMicroMips ( const MCSymbol * Sym ) const { if ( const auto * ElfSym = dyn_cast < const MCSymbolELF > ( Sym ) ) { if ( ElfSym -> getOther ( ) & ELF :: STO_MIPS_MICROMIPS ) return true ; } return false ; } </s>

Check whether a given symbol has been flagged with MICROMIPS flag .


<s> bool isTarget64BitLP64 ( ) const { if ( NaClDontBreakABI ) { return In64BitMode && ( TargetTriple . getEnvironment ( ) != Triple :: GNUX32 ) ; } return In64BitMode && ( TargetTriple . getEnvironment ( ) != Triple :: GNUX32 && ! TargetTriple . isOSNaCl ( ) ) ; } </s>

Is this x86_64 with the LP64 programming model ( standard AMD64 , no x32 ) ?


<s> static bool alpha_scalar_mode_supported_p ( scalar_mode mode ) { switch ( mode ) { case E_QImode : case E_HImode : case E_SImode : case E_DImode : case E_TImode : return true ; case E_SFmode : case E_DFmode : return true ; case E_TFmode : return TARGET_HAS_XFLOATING_LIBS ; default : return false ; } } </s>

The scalar modes supported differs from the default check-what-c-supports version in that sometimes TFmode is available even when long double indicates only DFmode . On unicosmk , we have the situation that HImode does n't map to any C type , but of course we still support that .


"Return instruction can only reference SP relative frame objects"

"Requesting 64-bit offset in 32-bit immediate!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> const char * tilegx_asm_output_opcode ( FILE * stream , const char * code ) { bool pseudo = ! strcmp ( code , "pseudo" ) ; if ( ! tilegx_in_bundle && insn_mode == SImode ) { fprintf ( stream , "{\n\t" ) ; tilegx_in_bundle = true ; } if ( tilegx_in_bundle && insn_mode == QImode ) { static char buf [ 100 ] ; gcc_assert ( strlen ( code ) + 3 + 1 < sizeof ( buf ) ) ; strcpy ( buf , pseudo ? "" : code ) ; strcat ( buf , "\n\t}" ) ; tilegx_in_bundle = false ; return buf ; } else { return pseudo ? "" : code ; } } </s>

Implement ASM_OUTPUT_OPCODE . Prepend/append curly braces as appropriate given the bundling information recorded by tilegx_gen_bundles .


<s>
const
char
*
getPassName
(
)
const
{
return
"PPC CTR Loops"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"Store results: call to builtin function with wrong "

"signature, not consuming reg or frame index"

optimizeCall - Take the given call instruction and return a more optimal value to replace the instruction with or 0 if a more optimal form ca n't be found .


"sret virtual register not created in the entry block"


<s> virtual bool enableMachineScheduler ( ) const { return getGeneration ( ) <= NORTHERN_ISLANDS ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


<s> unsigned BPFRegisterInfo :: getRARegister ( ) const { return BPF :: R0 ; } </s>

This method should return the register where the return address can be found .


<s>
struct
rtx_def
*
c4x_function_arg
(
CUMULATIVE_ARGS
*
cum
,
enum
machine_mode
mode
,
tree
type
,
int
named
)
{
int
reg
=
0
;
if
(
!
cum
->
init
)
{
cum
->
maxfloats
=
(
cum
->
floats
>
2
)
2
:
cum
->
floats
;
cum
->
maxints
=
(
cum
->
ints
>
6
cum
->
maxfloats
)
6
cum
->
maxfloats
:
cum
->
ints
;
if
(
!
cum
->
prototype
)
cum
->
maxints
=
6
;
cum
->
ints
=
cum
->
floats
=
0
;
cum
->
init
=
1
;
}
if
(
type
==
void_type_node
)
return
0
;
if
(
!
TARGET_MEMPARM
&&
named
&&
type
&&
!
targetm
.
calls
.
must_pass_in_stack
(
mode
,
type
)
)
{
if
(
mode
==
QFmode
||
mode
==
HFmode
)
{
if
(
cum
->
floats
<
cum
->
maxfloats
)
reg
=
c4x_fp_reglist
[
cum
->
floats
]
;
}
else
if
(
mode
==
QImode
||
mode
==
Pmode
)
{
if
(
cum
->
ints
<
cum
->
maxints
)
reg
=
c4x_int_reglist
[
cum
->
maxfloats
]
[
cum
->
ints
]
;
}
}
else
if
(
!
TARGET_MEMPARM
&&
!
type
)
{
if
(
mode
==
QFmode
||
mode
==
HFmode
)
reg
=
c4x_fp_reglist
[
cum
->
floats
]
;
else
if
(
mode
==
QImode
||
mode
==
Pmode
)
reg
=
c4x_int_reglist
[
0
]
[
cum
->
ints
]
;
}
if
(
TARGET_DEBUG
)
{
fprintf
(
stderr
,
"c4x_function_arg(mode=%s, named=%d"
,
GET_MODE_NAME
(
mode
)
,
named
)
;
if
(
reg
)
fprintf
(
stderr
,
", reg=%s"
,
reg_names
[
reg
]
)
;
else
fprintf
(
stderr
,
", stack"
)
;
fprintf
(
stderr
,
")\n"
)
;
}
if
(
reg
)
return
gen_rtx_REG
(
mode
,
reg
)
;
else
return
NULL_RTX
;
}
</s>

Define where to put the arguments to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) .


<s> void PPCTTIImpl :: getUnrollingPreferences ( Loop * L , TTI :: UnrollingPreferences & UP ) { if ( ST -> getDarwinDirective ( ) == PPC :: DIR_A2 ) { UP . Partial = UP . Runtime = true ; } BaseT :: getUnrollingPreferences ( L , UP ) ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> static int bfin_comp_type_attributes ( const_tree type1 , const_tree type2 ) { e_funkind kind1 , kind2 ; if ( TREE_CODE ( type1 ) != FUNCTION_TYPE ) return 1 ; kind1 = funkind ( type1 ) ; kind2 = funkind ( type2 ) ; if ( kind1 != kind2 ) return 0 ; if ( ! lookup_attribute ( "nesting" , TYPE_ATTRIBUTES ( type1 ) ) != ! lookup_attribute ( "nesting" , TYPE_ATTRIBUTES ( type2 ) ) ) return 0 ; if ( ! lookup_attribute ( "saveall" , TYPE_ATTRIBUTES ( type1 ) ) != ! lookup_attribute ( "saveall" , TYPE_ATTRIBUTES ( type2 ) ) ) return 0 ; if ( ! lookup_attribute ( "kspisusp" , TYPE_ATTRIBUTES ( type1 ) ) != ! lookup_attribute ( "kspisusp" , TYPE_ATTRIBUTES ( type2 ) ) ) return 0 ; if ( ! lookup_attribute ( "longcall" , TYPE_ATTRIBUTES ( type1 ) ) != ! lookup_attribute ( "longcall" , TYPE_ATTRIBUTES ( type2 ) ) ) return 0 ; return 1 ; } </s>

Return 0 if the attributes for two types are incompatible , 1 if they are compatible , and 2 if they are nearly compatible ( which causes a warning to be generated ) .


<s> static int ix86_avx_u128_mode_needed ( rtx_insn * insn ) { if ( CALL_P ( insn ) ) { rtx link ; for ( link = CALL_INSN_FUNCTION_USAGE ( insn ) ; link ; link = XEXP ( link , 1 ) ) { if ( GET_CODE ( XEXP ( link , 0 ) ) == USE ) { rtx arg = XEXP ( XEXP ( link , 0 ) , 0 ) ; if ( ix86_check_avx_upper_register ( arg ) ) return AVX_U128_DIRTY ; } } return AVX_U128_CLEAN ; } subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , NONCONST ) if ( ix86_check_avx_upper_register ( * iter ) ) return AVX_U128_DIRTY ; return AVX_U128_ANY ; } </s>

Return needed mode for entity in optimize_mode_switching pass .


<s> static bool aarch64_hard_regno_call_part_clobbered ( unsigned int regno , machine_mode mode ) { return FP_REGNUM_P ( regno ) && maybe_gt ( GET_MODE_SIZE ( mode ) , 8 ) ; } </s>

Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED . The callee only saves the lower 64 bits of a 128-bit register . Tell the compiler the callee clobbers the top 64 bits when restoring the bottom 64 bits .


<s> void ix86_expand_unary_operator ( enum rtx_code code , machine_mode mode , rtx operands [ ] ) { bool matching_memory = false ; rtx src , dst , op , clob ; dst = operands [ 0 ] ; src = operands [ 1 ] ; if ( MEM_P ( dst ) ) { if ( rtx_equal_p ( dst , src ) ) matching_memory = true ; else dst = gen_reg_rtx ( mode ) ; } if ( MEM_P ( src ) && ! matching_memory ) src = force_reg ( mode , src ) ; op = gen_rtx_SET ( dst , gen_rtx_fmt_e ( code , mode , src ) ) ; if ( code == NOT ) emit_insn ( op ) ; else { clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , op , clob ) ) ) ; } if ( dst != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , dst ) ; } </s>

Attempt to expand a unary operator . Make the expansion closer to the actual machine , then just general_operand , which will allow 2 separate memory references ( one output , one input ) in a single insn .


<s>
bool
AArch64InstrInfo
::
areMemAccessesTriviallyDisjoint
(
MachineInstr
*
MIa
,
MachineInstr
*
MIb
,
AliasAnalysis
*
AA
)
const
{
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
unsigned
BaseRegA
=
0
,
BaseRegB
=
0
;
int
OffsetA
=
0
,
OffsetB
=
0
;
int
WidthA
=
0
,
WidthB
=
0
;
assert
(
MIa
&&
(
MIa
->
mayLoad
(
)
||
MIa
->
mayStore
(
)
)
&&
"MIa must be a store or a load"
)
;
assert
(
MIb
&&
(
MIb
->
mayLoad
(
)
||
MIb
->
mayStore
(
)
)
&&
"MIb must be a store or a load"
)
;
if
(
MIa
->
hasUnmodeledSideEffects
(
)
||
MIb
->
hasUnmodeledSideEffects
(
)
||
MIa
->
hasOrderedMemoryRef
(
)
||
MIb
->
hasOrderedMemoryRef
(
)
)
return
false
;
if
(
getLdStBaseRegImmOfsWidth
(
MIa
,
BaseRegA
,
OffsetA
,
WidthA
,
TRI
)
&&
getLdStBaseRegImmOfsWidth
(
MIb
,
BaseRegB
,
OffsetB
,
WidthB
,
TRI
)
)
{
if
(
BaseRegA
==
BaseRegB
)
{
int
LowOffset
=
OffsetA
<
OffsetB
OffsetA
:
OffsetB
;
int
HighOffset
=
OffsetA
<
OffsetB
OffsetB
:
OffsetA
;
int
LowWidth
=
(
LowOffset
==
OffsetA
)
WidthA
:
WidthB
;
if
(
LowOffset
+
LowWidth
<=
HighOffset
)
return
true
;
}
}
return
false
;
}
</s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> bool ix86_check_builtin_isa_match ( unsigned int fcode , HOST_WIDE_INT * pbisa , HOST_WIDE_INT * pbisa2 ) { HOST_WIDE_INT isa = ix86_isa_flags ; HOST_WIDE_INT isa2 = ix86_isa_flags2 ; HOST_WIDE_INT bisa = ix86_builtins_isa [ fcode ] . isa ; HOST_WIDE_INT bisa2 = ix86_builtins_isa [ fcode ] . isa2 ; if ( ( ( bisa & ( OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A ) ) == ( OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A ) ) && ( isa & ( OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A ) ) != 0 ) isa |= ( OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A ) ; if ( ( ( bisa & ( OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 ) ) == ( OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 ) ) && ( isa & ( OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 ) ) != 0 ) isa |= ( OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 ) ; if ( ( ( bisa & ( OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4 ) ) == ( OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4 ) ) && ( isa & ( OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4 ) ) != 0 ) isa |= ( OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4 ) ; if ( ( ( ( bisa & ( OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL ) ) == ( OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL ) ) || ( bisa2 & OPTION_MASK_ISA2_AVXVNNI ) != 0 ) && ( ( ( isa & ( OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL ) ) == ( OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL ) ) || ( isa2 & OPTION_MASK_ISA2_AVXVNNI ) != 0 ) ) { isa |= OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL ; isa2 |= OPTION_MASK_ISA2_AVXVNNI ; } if ( ( bisa & OPTION_MASK_ISA_MMX ) && ! TARGET_MMX && TARGET_MMX_WITH_SSE && fcode != IX86_BUILTIN_MASKMOVQ ) { bisa &= ~ OPTION_MASK_ISA_MMX ; bisa |= OPTION_MASK_ISA_SSE2 ; } if ( pbisa ) * pbisa = bisa ; if ( pbisa2 ) * pbisa2 = bisa2 ; return ( bisa & isa ) == bisa && ( bisa2 & isa2 ) == bisa2 ; } </s>

Return true if the necessary isa options for this builtin exist , else false . fcode = DECL_MD_FUNCTION_CODE ( fndecl ) ;


<s> static void rs6000_adjust_vect_cost_per_loop ( rs6000_cost_data * data ) { struct loop * loop = data -> loop_info ; gcc_assert ( loop ) ; loop_vec_info loop_vinfo = loop_vec_info_for_loop ( loop ) ; if ( LOOP_VINFO_FULLY_WITH_LENGTH_P ( loop_vinfo ) ) { rgroup_controls * rgc ; unsigned int num_vectors_m1 ; unsigned int shift_cnt = 0 ; FOR_EACH_VEC_ELT ( LOOP_VINFO_LENS ( loop_vinfo ) , num_vectors_m1 , rgc ) if ( rgc -> type ) shift_cnt += num_vectors_m1 + 1 ; rs6000_add_stmt_cost ( loop_vinfo , ( void * ) data , shift_cnt , scalar_stmt , NULL , NULL_TREE , 0 , vect_body ) ; } } </s>

For some target specific vectorization cost which ca n't be handled per stmt , we check the requisite conditions and adjust the vectorization cost accordingly if satisfied . One typical example is to model shift cost for vector with length by counting number of required lengths under condition LOOP_VINFO_FULLY_WITH_LENGTH_P .


<s> void HexagonTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF :: SHF_HEX_GPREL ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF :: SHF_HEX_GPREL ) ; } </s>

This method must be called before any actual lowering is done .


<s> static bool r10k_safe_mem_expr_p ( tree expr , unsigned HOST_WIDE_INT offset ) { HOST_WIDE_INT bitoffset , bitsize ; tree inner , var_offset ; machine_mode mode ; int unsigned_p , volatile_p ; inner = get_inner_reference ( expr , & bitsize , & bitoffset , & var_offset , & mode , & unsigned_p , & volatile_p , false ) ; if ( ! DECL_P ( inner ) || ! DECL_SIZE_UNIT ( inner ) || var_offset ) return false ; offset += bitoffset / BITS_PER_UNIT ; return offset < tree_to_uhwi ( DECL_SIZE_UNIT ( inner ) ) ; } </s>

Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is an in-range access to an automatic variable , or to an object with a link-time-constant address .


Output indirect call insns . WHICH is 0 for tocsave , 1 for plt16_ha , 2 for plt16_lo , 3 for mtctr .


"LVI load hardening is only supported on 64-bit"

runOnMachineFunction - Emit the function body .


<s> StackOffset VEFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const VERegisterInfo * RegInfo = STI . getRegisterInfo ( ) ; bool isFixed = MFI . isFixedObjectIndex ( FI ) ; int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) ; if ( ! hasFP ( MF ) ) { FrameReg = VE :: SX11 ; return StackOffset :: getFixed ( FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ) ; } if ( RegInfo -> needsStackRealignment ( MF ) && ! isFixed ) { if ( hasBP ( MF ) ) FrameReg = VE :: SX17 ; else FrameReg = VE :: SX11 ; return StackOffset :: getFixed ( FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ) ; } FrameReg = RegInfo -> getFrameRegister ( MF ) ; return StackOffset :: getFixed ( FrameOffset ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s>
void
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
override
{
unsigned
Size
=
getFixupKindSize
(
Fixup
.
getKind
(
)
)
;
assert
(
Fixup
.
getOffset
(
)
+
Size
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
int64_t
SignedValue
=
static_cast
<
int64_t
>
(
Value
)
;
if
(
(
Target
.
isAbsolute
(
)
||
IsResolved
)
&&
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
.
Flags
&
MCFixupKindInfo
::
FKF_IsPCRel
)
{
if
(
Size
>
0
&&
!
isIntN
(
Size
*
8
,
SignedValue
)
)
Asm
.
getContext
(
)
.
reportError
(
Fixup
.
getLoc
(
)
,
"value of "
+
Twine
(
SignedValue
)
+
" is too large for field of "
+
Twine
(
Size
)
+
(
(
Size
==
1
)
" byte."
:
" bytes."
)
)
;
}
else
{
assert
(
(
Size
==
0
||
isIntN
(
Size
*
8
+
1
,
SignedValue
)
)
&&
"Value does not fit in the Fixup field"
)
;
}
for
(
unsigned
i
=
0
;
i
!=
Size
;
++
i
)
Data
[
Fixup
.
getOffset
(
)
+
i
]
=
uint8_t
(
Value
>>
(
i
*
8
)
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < AAResultsWrapperPass > ( ) ; AU . addRequired < LiveIntervals > ( ) ; AU . addPreserved < MachineBlockFrequencyInfo > ( ) ; AU . addPreserved < SlotIndexes > ( ) ; AU . addPreserved < LiveIntervals > ( ) ; AU . addPreservedID ( MachineDominatorsID ) ; AU . addPreservedID ( LiveVariablesID ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , int NumBytes , ARMCC :: CondCodes Pred , unsigned PredReg , bool isThumb , const TargetInstrInfo & TII , const ARMRegisterInfo & MRI , DebugLoc dl ) { if ( isThumb ) emitThumbRegPlusImmediate ( MBB , MBBI , ARM :: SP , ARM :: SP , NumBytes , TII , MRI , dl ) ; else emitARMRegPlusImmediate ( MBB , MBBI , ARM :: SP , ARM :: SP , NumBytes , Pred , PredReg , TII , dl ) ; } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .

ARM ARMCC::CondCodes ARM ARM::SP ARM::SP ARM ARM::SP ARM::SP


"getBranchTargetOpValuePC10 expects only expressions or immediates"

getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS 10-bit branch target operand .


<s> const TriCoreInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> bool AArch64FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; static LoadStoreMethod PossibleClasses [ ] = { { & AArch64 :: GPR64RegClass , AArch64 :: LSPair64_LDR , AArch64 :: LS64_LDR } , { & AArch64 :: FPR64RegClass , AArch64 :: LSFPPair64_LDR , AArch64 :: LSFP64_LDR } , } ; unsigned NumClasses = llvm :: array_lengthof ( PossibleClasses ) ; emitFrameMemOps ( false , MBB , MBBI , CSI , TRI , PossibleClasses , NumClasses ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool ia64_expand_vecint_minmax ( enum rtx_code code , enum machine_mode mode , rtx operands [ ] ) { rtx xops [ 6 ] ; if ( mode == V8QImode && ( code == UMIN || code == UMAX ) ) return false ; if ( mode == V4HImode && ( code == SMIN || code == SMAX ) ) return false ; if ( mode == V4HImode && code == UMAX ) { rtx x , tmp = gen_reg_rtx ( mode ) ; x = gen_rtx_US_MINUS ( mode , operands [ 1 ] , operands [ 2 ] ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , x ) ) ; emit_insn ( gen_addv4hi3 ( operands [ 0 ] , tmp , operands [ 2 ] ) ) ; return true ; } xops [ 0 ] = operands [ 0 ] ; xops [ 4 ] = xops [ 1 ] = operands [ 1 ] ; xops [ 5 ] = xops [ 2 ] = operands [ 2 ] ; switch ( code ) { case UMIN : code = LTU ; break ; case UMAX : code = GTU ; break ; case SMIN : code = LT ; break ; case SMAX : code = GT ; break ; default : gcc_unreachable ( ) ; } xops [ 3 ] = gen_rtx_fmt_ee ( code , VOIDmode , operands [ 1 ] , operands [ 2 ] ) ; ia64_expand_vecint_cmov ( xops ) ; return true ; } </s>

Emit an integral vector min or max operation . Return true if all done .


<s> static const char * reg_name_with_mode ( int regno , machine_mode mode ) { int mlen = GET_MODE_SIZE ( mode ) ; if ( regno == R0_REGNO && mlen == 1 ) return "r0l" ; if ( regno == R0_REGNO && ( mlen == 3 || mlen == 4 ) ) return "r2r0" ; if ( regno == R0_REGNO && mlen == 6 ) return "r2r1r0" ; if ( regno == R0_REGNO && mlen == 8 ) return "r3r1r2r0" ; if ( regno == R1_REGNO && mlen == 1 ) return "r1l" ; if ( regno == R1_REGNO && ( mlen == 3 || mlen == 4 ) ) return "r3r1" ; if ( regno == A0_REGNO && TARGET_A16 && ( mlen == 3 || mlen == 4 ) ) return "a1a0" ; return reg_names [ regno ] ; } </s>

Since register names indicate the mode they 're used in , we need a way to determine which name to refer to the register with . Called by print_operand ( ) .


<s> const MipsRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


"  Skipping pass: no machine model present.\n"


<s> unsigned ARMBaseInstrInfo :: isStoreToStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { SmallVector < const MachineMemOperand * , 1 > Accesses ; if ( MI . mayStore ( ) && hasStoreToStackSlot ( MI , Accesses ) && Accesses . size ( ) == 1 ) { FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) -> getFrameIndex ( ) ; return true ; } return false ; } </s>

isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s> bool SystemZTTIImpl :: isLSRCostLess ( TargetTransformInfo :: LSRCost & C1 , TargetTransformInfo :: LSRCost & C2 ) { return std :: tie ( C1 . Insns , C1 . NumRegs , C1 . AddRecCost , C1 . NumIVMuls , C1 . NumBaseAdds , C1 . ScaleCost , C1 . SetupCost ) < std :: tie ( C2 . Insns , C2 . NumRegs , C2 . AddRecCost , C2 . NumIVMuls , C2 . NumBaseAdds , C2 . ScaleCost , C2 . SetupCost ) ; } </s>

Return true if LSR cost of C1 is lower than C2 .


<s> static void aarch64_pop_regs ( unsigned regno1 , unsigned regno2 , HOST_WIDE_INT adjustment , rtx * cfi_ops ) { machine_mode mode = ( regno1 <= R30_REGNUM ) ? E_DImode : E_DFmode ; rtx reg1 = gen_rtx_REG ( mode , regno1 ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg1 , * cfi_ops ) ; if ( regno2 == INVALID_REGNUM ) { rtx mem = plus_constant ( Pmode , stack_pointer_rtx , adjustment ) ; mem = gen_rtx_POST_MODIFY ( Pmode , stack_pointer_rtx , mem ) ; emit_move_insn ( reg1 , gen_frame_mem ( mode , mem ) ) ; } else { rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg2 , * cfi_ops ) ; emit_insn ( aarch64_gen_loadwb_pair ( mode , stack_pointer_rtx , reg1 , reg2 , adjustment ) ) ; } } </s>

Pop the two registers numbered REGNO1 , REGNO2 from the stack , adjusting it afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes into CFI_OPS .


<s> bool WebAssemblyInstrInfo :: isReallyTriviallyReMaterializable ( const MachineInstr & MI , AliasAnalysis * AA ) const { switch ( MI . getOpcode ( ) ) { case WebAssembly :: CONST_I32 : case WebAssembly :: CONST_I64 : case WebAssembly :: CONST_F32 : case WebAssembly :: CONST_F64 : return true ; default : return false ; } } </s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> bool X86TargetLowering :: IsDesirableToPromoteOp ( SDValue Op , EVT & PVT ) const { EVT VT = Op . getValueType ( ) ; if ( VT != MVT :: i16 ) return false ; bool Promote = false ; bool Commute = false ; switch ( Op . getOpcode ( ) ) { default : break ; case ISD :: SIGN_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: ANY_EXTEND : Promote = true ; break ; case ISD :: SHL : case ISD :: SRL : { SDValue N0 = Op . getOperand ( 0 ) ; if ( MayFoldLoad ( N0 ) && MayFoldIntoStore ( Op ) ) return false ; Promote = true ; break ; } case ISD :: ADD : case ISD :: MUL : case ISD :: AND : case ISD :: OR : case ISD :: XOR : Commute = true ; case ISD :: SUB : { SDValue N0 = Op . getOperand ( 0 ) ; SDValue N1 = Op . getOperand ( 1 ) ; if ( ! Commute && MayFoldLoad ( N1 ) ) return false ; if ( MayFoldLoad ( N0 ) && ( ! isa < ConstantSDNode > ( N1 ) || MayFoldIntoStore ( Op ) ) ) return false ; if ( MayFoldLoad ( N1 ) && ( ! isa < ConstantSDNode > ( N0 ) || MayFoldIntoStore ( Op ) ) ) return false ; Promote = true ; } } PVT = MVT :: i32 ; return Promote ; } </s>

Return true if the target has native support for the specified value type and it is 'desirable ' to use the type .


<s> const HexagonSubtarget * HexagonTargetMachine :: getSubtargetImpl ( const Function & F ) const { AttributeList FnAttrs = F . getAttributes ( ) ; Attribute CPUAttr = FnAttrs . getAttribute ( AttributeList :: FunctionIndex , "target-cpu" ) ; Attribute FSAttr = FnAttrs . getAttribute ( AttributeList :: FunctionIndex , "target-features" ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; if ( FnAttrs . hasFnAttribute ( "unsafe-fp-math" ) && F . getFnAttribute ( "unsafe-fp-math" ) . getValueAsString ( ) == "true" ) FS = FS . empty ( ) ? "+unsafe-fp" : "+unsafe-fp," + FS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < HexagonSubtarget > ( TargetTriple , CPU , FS , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

Hexagon Hexagon Hexagon "target-cpu" "target-features" "unsafe-fp-math" "unsafe-fp-math" "true" "+unsafe-fp" "+unsafe-fp," Hexagon


<s> InstructionCost ARMTTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind , Instruction * Inst ) { if ( ( Opcode == Instruction :: SDiv || Opcode == Instruction :: UDiv || Opcode == Instruction :: SRem || Opcode == Instruction :: URem ) && Idx == 1 ) return 0 ; if ( Opcode == Instruction :: And ) { if ( Imm == 255 || Imm == 65535 ) return 0 ; return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( ~ Imm , Ty , CostKind ) ) ; } if ( Opcode == Instruction :: Add ) return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( - Imm , Ty , CostKind ) ) ; if ( Opcode == Instruction :: ICmp && Imm . isNegative ( ) && Ty -> getIntegerBitWidth ( ) == 32 ) { int64_t NegImm = - Imm . getSExtValue ( ) ; if ( ST -> isThumb2 ( ) && NegImm < 1 << 12 ) return 0 ; if ( ST -> isThumb ( ) && NegImm < 1 << 8 ) return 0 ; } if ( Opcode == Instruction :: Xor && Imm . isAllOnesValue ( ) ) return 0 ; if ( Inst && ( ( ST -> hasV6Ops ( ) && ! ST -> isThumb ( ) ) || ST -> isThumb2 ( ) ) && Ty -> getIntegerBitWidth ( ) <= 32 ) { if ( isSSATMinMaxPattern ( Inst , Imm ) || ( isa < ICmpInst > ( Inst ) && Inst -> hasOneUse ( ) && isSSATMinMaxPattern ( cast < Instruction > ( * Inst -> user_begin ( ) ) , Imm ) ) ) return 0 ; } return getIntImmCost ( Imm , Ty , CostKind ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> bool function_resolver :: check_gp_argument ( unsigned int nops , unsigned int & i , unsigned int & nargs ) { i = 0 ; if ( pred != PRED_none ) { gcc_assert ( nops != 1 || pred != PRED_m ) ; nargs = nops + 1 ; if ( ! check_num_arguments ( nargs ) || ! require_vector_type ( i , VECTOR_TYPE_svbool_t ) ) return false ; i += 1 ; } else { nargs = nops ; if ( ! check_num_arguments ( nargs ) ) return false ; } return true ; } </s>

If the function is predicated , check that the first argument is a suitable governing predicate . Also check that there are NOPS further arguments after any governing predicate , but do n't check what they are . Return true on success , otherwise report a suitable error . When returning true : - set I to the number of the first unchecked argument . - set NARGS to the total number of arguments .


<s> static bool tilegx_scalar_mode_supported_p ( scalar_mode mode ) { switch ( mode ) { case E_QImode : case E_HImode : case E_SImode : case E_DImode : case E_TImode : return true ; case E_SFmode : case E_DFmode : return true ; default : return false ; } } </s>


"Instr doesn't have FrameIndex operand!"

"16-byte alignment violated in eliminateFrameIndex"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Prepare control-flow for ISel"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void * aarch64_init_cost ( class loop * ) { return new aarch64_vector_costs ; } </s>


<s> static void frv_start_packet ( void ) { enum frv_insn_group group ; memset ( frv_packet . regstate , 0 , sizeof ( frv_packet . regstate ) ) ; frv_packet . num_mems = 0 ; frv_packet . num_insns = 0 ; for ( group = GROUP_I ; group < NUM_GROUPS ; group = ( enum frv_insn_group ) ( group + 1 ) ) frv_packet . groups [ group ] . num_insns = 0 ; } </s>

Initialize frv_packet for the start of a new packet .


"The destination address is not aligned to a word"

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static void ft32_compute_frame ( void ) { int stack_alignment = STACK_BOUNDARY / BITS_PER_UNIT ; int padding_locals ; int regno ; cfun -> machine -> local_vars_size = get_frame_size ( ) ; padding_locals = cfun -> machine -> local_vars_size % stack_alignment ; if ( padding_locals ) padding_locals = stack_alignment - padding_locals ; cfun -> machine -> local_vars_size += padding_locals ; cfun -> machine -> callee_saved_reg_size = 0 ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ( ! call_used_regs [ regno ] ) ) cfun -> machine -> callee_saved_reg_size += 4 ; cfun -> machine -> size_for_adjusting_sp = 0 + cfun -> machine -> local_vars_size + ( ACCUMULATE_OUTGOING_ARGS ? crtl -> outgoing_args_size : 0 ) ; } </s>

Compute the size of the local area and the size to be adjusted by the * prologue and epilogue .


Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU R600 AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU


"Only base registers and frame indices are supported."

Returns true if the two given memory operations should be scheduled adjacent .


<s> static bool sparc_legitimate_constant_p ( machine_mode mode , rtx x ) { switch ( GET_CODE ( x ) ) { case CONST : case SYMBOL_REF : if ( sparc_tls_referenced_p ( x ) ) return false ; break ; case CONST_DOUBLE : if ( GET_MODE ( x ) == VOIDmode ) return true ; if ( TARGET_VIS && SCALAR_FLOAT_MODE_P ( mode ) && ( const_zero_operand ( x , mode ) || const_all_ones_operand ( x , mode ) ) ) return true ; return false ; case CONST_VECTOR : if ( TARGET_VIS && ( const_zero_operand ( x , mode ) || const_all_ones_operand ( x , mode ) ) ) return true ; return false ; default : break ; } return true ; } </s>

Determine if a given RTX is a valid constant . We already know this satisfies CONSTANT_P .


<s> static rtx stv_expand_builtin ( insn_code icode , rtx * op , machine_mode tmode , machine_mode smode ) { op [ 2 ] = copy_to_mode_reg ( Pmode , op [ 2 ] ) ; if ( icode == CODE_FOR_altivec_stvx_v2df || icode == CODE_FOR_altivec_stvx_v2di || icode == CODE_FOR_altivec_stvx_v4sf || icode == CODE_FOR_altivec_stvx_v4si || icode == CODE_FOR_altivec_stvx_v8hi || icode == CODE_FOR_altivec_stvx_v16qi ) { rtx rawaddr ; if ( op [ 1 ] == const0_rtx ) rawaddr = op [ 2 ] ; else { op [ 1 ] = copy_to_mode_reg ( Pmode , op [ 1 ] ) ; rawaddr = gen_rtx_PLUS ( Pmode , op [ 2 ] , op [ 1 ] ) ; } rtx addr = gen_rtx_AND ( Pmode , rawaddr , gen_rtx_CONST_INT ( Pmode , - 16 ) ) ; addr = gen_rtx_MEM ( tmode , addr ) ; op [ 0 ] = copy_to_mode_reg ( tmode , op [ 0 ] ) ; emit_insn ( gen_rtx_SET ( addr , op [ 0 ] ) ) ; } else if ( icode == CODE_FOR_vsx_stxvrbx || icode == CODE_FOR_vsx_stxvrhx || icode == CODE_FOR_vsx_stxvrwx || icode == CODE_FOR_vsx_stxvrdx ) { rtx truncrtx = gen_rtx_TRUNCATE ( tmode , op [ 0 ] ) ; op [ 0 ] = copy_to_mode_reg ( E_TImode , truncrtx ) ; rtx addr ; if ( op [ 1 ] == const0_rtx ) addr = gen_rtx_MEM ( Pmode , op [ 2 ] ) ; else { op [ 1 ] = copy_to_mode_reg ( Pmode , op [ 1 ] ) ; addr = gen_rtx_MEM ( tmode , gen_rtx_PLUS ( Pmode , op [ 2 ] , op [ 1 ] ) ) ; } rtx pat = GEN_FCN ( icode ) ( addr , op [ 0 ] ) ; if ( pat ) emit_insn ( pat ) ; } else { if ( ! insn_data [ icode ] . operand [ 1 ] . predicate ( op [ 0 ] , smode ) ) op [ 0 ] = copy_to_mode_reg ( smode , op [ 0 ] ) ; rtx addr ; if ( op [ 1 ] == const0_rtx ) addr = gen_rtx_MEM ( tmode , op [ 2 ] ) ; else { op [ 1 ] = copy_to_mode_reg ( Pmode , op [ 1 ] ) ; addr = gen_rtx_MEM ( tmode , gen_rtx_PLUS ( Pmode , op [ 2 ] , op [ 1 ] ) ) ; } rtx pat = GEN_FCN ( icode ) ( addr , op [ 0 ] ) ; if ( pat ) emit_insn ( pat ) ; } return NULL_RTX ; } </s>

Expand an AltiVec vector store builtin , and return the expanded rtx .


<s>
static
void
initialize_aarch64_code_model
(
struct
gcc_options
*
opts
)
{
if
(
opts
->
x_flag_pic
)
{
switch
(
opts
->
x_aarch64_cmodel_var
)
{
case
AARCH64_CMODEL_TINY
:
aarch64_cmodel
=
AARCH64_CMODEL_TINY_PIC
;
break
;
case
AARCH64_CMODEL_SMALL
:
aarch64_cmodel
=
(
flag_pic
==
2
AARCH64_CMODEL_SMALL_PIC
:
AARCH64_CMODEL_SMALL_SPIC
)
;
aarch64_cmodel
=
AARCH64_CMODEL_SMALL_PIC
;
break
;
case
AARCH64_CMODEL_LARGE
:
sorry
(
"code model %qs with %<-f%s%>"
,
"large"
,
opts
->
x_flag_pic
>
1
"PIC"
:
"pic"
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
else
aarch64_cmodel
=
opts
->
x_aarch64_cmodel_var
;
}
</s>

A checking mechanism for the implementation of the various code models .


<s> static bool avr_address_tiny_pm_p ( rtx x ) { if ( CONST == GET_CODE ( x ) ) x = XEXP ( XEXP ( x , 0 ) , 0 ) ; if ( SYMBOL_REF_P ( x ) ) return SYMBOL_REF_FLAGS ( x ) & AVR_SYMBOL_FLAG_TINY_PM ; return false ; } </s>

Return true if rtx X is a CONST or SYMBOL_REF with progmem . This must be used for AVR_TINY only because on other cores the flash memory is not visible in the RAM address range and can not be read by , say , LD instruction .


<s>
void
SIInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
SIMachineFunctionInfo
*
MFI
=
MF
->
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MachineFrameInfo
&
FrameInfo
=
MF
->
getFrameInfo
(
)
;
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
unsigned
Size
=
FrameInfo
.
getObjectSize
(
FrameIndex
)
;
unsigned
Align
=
FrameInfo
.
getObjectAlignment
(
FrameIndex
)
;
MachinePointerInfo
PtrInfo
=
MachinePointerInfo
::
getFixedStack
(
*
MF
,
FrameIndex
)
;
MachineMemOperand
*
MMO
=
MF
->
getMachineMemOperand
(
PtrInfo
,
MachineMemOperand
::
MOStore
,
Size
,
Align
)
;
unsigned
SpillSize
=
TRI
->
getSpillSize
(
*
RC
)
;
if
(
RI
.
isSGPRClass
(
RC
)
)
{
MFI
->
setHasSpilledSGPRs
(
)
;
const
MCInstrDesc
&
OpDesc
=
get
(
getSGPRSpillSaveOpcode
(
SpillSize
)
)
;
if
(
TargetRegisterInfo
::
isVirtualRegister
(
SrcReg
)
&&
SpillSize
==
4
)
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
MRI
.
constrainRegClass
(
SrcReg
,
&
AMDGPU
::
SReg_32_XM0RegClass
)
;
}
MachineInstrBuilder
Spill
=
BuildMI
(
MBB
,
MI
,
DL
,
OpDesc
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIndex
)
.
addMemOperand
(
MMO
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
,
RegState
::
Implicit
)
.
addReg
(
MFI
->
getFrameOffsetReg
(
)
,
RegState
::
Implicit
)
;
FrameInfo
.
setStackID
(
FrameIndex
,
SIStackID
::
SGPR_SPILL
)
;
if
(
ST
.
hasScalarStores
(
)
)
{
Spill
.
addReg
(
AMDGPU
::
M0
,
RegState
::
ImplicitDefine
|
RegState
::
Dead
)
;
}
return
;
}
assert
(
RI
.
hasVGPRs
(
RC
)
&&
"Only VGPR spilling expected"
)
;
unsigned
Opcode
=
getVGPRSpillSaveOpcode
(
SpillSize
)
;
MFI
->
setHasSpilledVGPRs
(
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opcode
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIndex
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
)
.
addReg
(
MFI
->
getFrameOffsetReg
(
)
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s>
void
print
(
raw_ostream
&
O
)
const
override
{
switch
(
Kind
)
{
case
k_Token
:
O
<<
"Token: \""
<<
getToken
(
)
<<
"\""
;
break
;
case
k_Register
:
O
<<
"Register: "
<<
getReg
(
)
;
break
;
case
k_Immediate
:
O
<<
"Immediate: \""
<<
*
getImm
(
)
<<
"\""
;
break
;
case
k_Memri
:
{
O
<<
"Memri: \""
<<
getReg
(
)
<<
'+'
<<
*
getImm
(
)
<<
"\""
;
break
;
}
}
O
<<
"\n"
;
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> const TargetRegisterClass * SIInstrInfo :: getOpRegClass ( const MachineInstr & MI , unsigned OpNo ) const { const MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const MCInstrDesc & Desc = get ( MI . getOpcode ( ) ) ; if ( MI . isVariadic ( ) || OpNo >= Desc . getNumOperands ( ) || Desc . OpInfo [ OpNo ] . RegClass == - 1 ) { Register Reg = MI . getOperand ( OpNo ) . getReg ( ) ; if ( Reg . isVirtual ( ) ) return MRI . getRegClass ( Reg ) ; return RI . getPhysRegClass ( Reg ) ; } unsigned RCID = Desc . OpInfo [ OpNo ] . RegClass ; RCID = adjustAllocatableRegClass ( ST , MRI , Desc , RCID , true ) ; return RI . getRegClass ( RCID ) ; } </s>

Return the correct register class for OpNo .


<s> unsigned getPrefetchDistance ( ) const { return PrefetchDistance ; } </s>

Return the preferred prefetch distance in terms of instructions .


<s> EVT AArch64TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , const AttributeList & FuncAttributes ) const { bool CanImplicitFloat = ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; bool CanUseNEON = Subtarget -> hasNEON ( ) && CanImplicitFloat ; bool CanUseFP = Subtarget -> hasFPARMv8 ( ) && CanImplicitFloat ; bool IsSmallMemset = IsMemset && Size < 32 ; auto AlignmentIsAcceptable = [ & ] ( EVT VT , unsigned AlignCheck ) { if ( memOpAlign ( SrcAlign , DstAlign , AlignCheck ) ) return true ; bool Fast ; return allowsMisalignedMemoryAccesses ( VT , 0 , 1 , MachineMemOperand :: MONone , & Fast ) && Fast ; } ; if ( CanUseNEON && IsMemset && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: v2i64 , 16 ) ) return MVT :: v2i64 ; if ( CanUseFP && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: f128 , 16 ) ) return MVT :: f128 ; if ( Size >= 8 && AlignmentIsAcceptable ( MVT :: i64 , 8 ) ) return MVT :: i64 ; if ( Size >= 4 && AlignmentIsAcceptable ( MVT :: i32 , 4 ) ) return MVT :: i32 ; return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> bool SIInstrInfo :: usesConstantBus ( const MachineRegisterInfo & MRI , const MachineOperand & MO , unsigned OpSize ) const { if ( isLiteralConstant ( MO , OpSize ) ) return true ; if ( ! MO . isReg ( ) || ! MO . isUse ( ) ) return false ; if ( TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) return RI . isSGPRClass ( MRI . getRegClass ( MO . getReg ( ) ) ) ; if ( ! MO . isImplicit ( ) && ( MO . getReg ( ) == AMDGPU :: FLAT_SCR ) ) return true ; if ( ! MO . isImplicit ( ) && MO . getReg ( ) == AMDGPU :: EXEC ) return true ; if ( MO . getReg ( ) == AMDGPU :: M0 || MO . getReg ( ) == AMDGPU :: VCC || ( ! MO . isImplicit ( ) && ( AMDGPU :: SGPR_32RegClass . contains ( MO . getReg ( ) ) || AMDGPU :: SGPR_64RegClass . contains ( MO . getReg ( ) ) ) ) ) { return true ; } return false ; } </s>

Returns true if this operand uses the constant bus .


<s> bool X86TargetLowering :: shouldScalarizeBinop ( SDValue VecOp ) const { EVT VecVT = VecOp . getValueType ( ) ; if ( ! isOperationLegalOrCustomOrPromote ( VecOp . getOpcode ( ) , VecVT ) ) return true ; EVT ScalarVT = VecVT . getScalarType ( ) ; return isOperationLegalOrCustomOrPromote ( VecOp . getOpcode ( ) , ScalarVT ) ; } </s>

Scalar ops always have equal or better analysis/performance/power than the vector equivalent , so this always makes sense if the scalar op is supported .


<s> static rtx v850_libcall_value ( machine_mode mode , const_rtx func ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( mode , RV_REGNUM ) ; } </s>


<s>
CCAssignFn
*
ARMFastISel
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
Return
,
bool
isVarArg
)
{
switch
(
CC
)
{
default
:
report_fatal_error
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
if
(
Subtarget
->
hasVFP2Base
(
)
&&
!
isVarArg
)
{
if
(
!
Subtarget
->
isAAPCS_ABI
(
)
)
return
(
Return
RetFastCC_ARM_APCS
:
FastCC_ARM_APCS
)
;
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
}
LLVM_FALLTHROUGH
;
case
CallingConv
::
C
:
case
CallingConv
::
CXX_FAST_TLS
:
if
(
Subtarget
->
isAAPCS_ABI
(
)
)
{
if
(
Subtarget
->
hasVFP2Base
(
)
&&
TM
.
Options
.
FloatABIType
==
FloatABI
::
Hard
&&
!
isVarArg
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
else
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
}
else
{
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
}
case
CallingConv
::
ARM_AAPCS_VFP
:
case
CallingConv
::
Swift
:
if
(
!
isVarArg
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
LLVM_FALLTHROUGH
;
case
CallingConv
::
ARM_AAPCS
:
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
case
CallingConv
::
ARM_APCS
:
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
case
CallingConv
::
GHC
:
if
(
Return
)
report_fatal_error
(
"Can't return in GHC call convention"
)
;
else
return
CC_ARM_APCS_GHC
;
case
CallingConv
::
CFGuard_Check
:
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_Win32_CFGuard_Check
)
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .

ARM
ARM
"Unsupported calling convention"
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
"Can't return in GHC call convention"
ARM
ARM
ARM


<s> const TargetRegisterClass * SPURegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & SPU :: R32CRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> static rtx m68k_unwrap_symbol_1 ( rtx orig , bool unwrap_reloc32_p , enum m68k_reloc * reloc_ptr ) { if ( GET_CODE ( orig ) == CONST ) { rtx x ; enum m68k_reloc dummy ; x = XEXP ( orig , 0 ) ; if ( reloc_ptr == NULL ) reloc_ptr = & dummy ; if ( ( GET_CODE ( x ) == PLUS || GET_CODE ( x ) == MINUS ) && CONST_INT_P ( XEXP ( x , 1 ) ) ) x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == UNSPEC ) { switch ( XINT ( x , 1 ) ) { case UNSPEC_RELOC16 : orig = XVECEXP ( x , 0 , 0 ) ; * reloc_ptr = ( enum m68k_reloc ) INTVAL ( XVECEXP ( x , 0 , 1 ) ) ; break ; case UNSPEC_RELOC32 : if ( unwrap_reloc32_p ) { orig = XVECEXP ( x , 0 , 0 ) ; * reloc_ptr = ( enum m68k_reloc ) INTVAL ( XVECEXP ( x , 0 , 1 ) ) ; } break ; default : break ; } } } return orig ; } </s>

Helper for m68k_unwrap_symbol . Also , if unwrapping was successful ( that is if ( ORIG ! = < return value > ) ) , sets * RELOC_PTR to relocation type for the symbol .


<s> static inline tree def_builtin_const2 ( HOST_WIDE_INT mask , const char * name , enum ix86_builtin_func_type tcode , enum ix86_builtins code ) { tree decl = def_builtin2 ( mask , name , tcode , code ) ; if ( decl ) TREE_READONLY ( decl ) = 1 ; else ix86_builtins_isa [ ( int ) code ] . const_p = true ; return decl ; } </s>

Like def_builtin , but also marks the function decl `` const '' .


initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s>
bool
ARMBaseInstrInfo
::
getRegSequenceLikeInputs
(
const
MachineInstr
&
MI
,
unsigned
DefIdx
,
SmallVectorImpl
<
RegSubRegPairAndIdx
>
&
InputRegs
)
const
{
assert
(
DefIdx
<
MI
.
getDesc
(
)
.
getNumDefs
(
)
&&
"Invalid definition index"
)
;
assert
(
MI
.
isRegSequenceLike
(
)
&&
"Invalid kind of instruction"
)
;
switch
(
MI
.
getOpcode
(
)
)
{
case
ARM
::
VMOVDRR
:
const
MachineOperand
*
MOReg
=
&
MI
.
getOperand
(
1
)
;
if
(
!
MOReg
->
isUndef
(
)
)
InputRegs
.
push_back
(
RegSubRegPairAndIdx
(
MOReg
->
getReg
(
)
,
MOReg
->
getSubReg
(
)
,
ARM
::
ssub_0
)
)
;
MOReg
=
&
MI
.
getOperand
(
2
)
;
if
(
!
MOReg
->
isUndef
(
)
)
InputRegs
.
push_back
(
RegSubRegPairAndIdx
(
MOReg
->
getReg
(
)
,
MOReg
->
getSubReg
(
)
,
ARM
::
ssub_1
)
)
;
return
true
;
}
llvm_unreachable
(
"Target dependent opcode missing"
)
;
}
</s>

Target-dependent implementation of getRegSequenceInputs .


<s> void function_expander :: prepare_prefetch_operands ( ) { unsigned int prfop = INTVAL ( args . last ( ) ) ; args . quick_push ( GEN_INT ( ( prfop & 8 ) != 0 ) ) ; args . quick_push ( GEN_INT ( ( ( prfop >> 1 ) & 3 ) + 1 ) ) ; } </s>

The final argument is an immediate svprfop value . Add two fake arguments to represent the rw and locality operands of a PREFETCH rtx .


<s>
static
int
getMemScale
(
MachineInstr
&
MI
)
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Opcode has unknown scale!"
)
;
case
AArch64
::
LDRBBui
:
case
AArch64
::
LDURBBi
:
case
AArch64
::
LDRSBWui
:
case
AArch64
::
LDURSBWi
:
case
AArch64
::
STRBBui
:
case
AArch64
::
STURBBi
:
return
1
;
case
AArch64
::
LDRHHui
:
case
AArch64
::
LDURHHi
:
case
AArch64
::
LDRSHWui
:
case
AArch64
::
LDURSHWi
:
case
AArch64
::
STRHHui
:
case
AArch64
::
STURHHi
:
return
2
;
case
AArch64
::
LDRSui
:
case
AArch64
::
LDURSi
:
case
AArch64
::
LDRSWui
:
case
AArch64
::
LDURSWi
:
case
AArch64
::
LDRWui
:
case
AArch64
::
LDURWi
:
case
AArch64
::
STRSui
:
case
AArch64
::
STURSi
:
case
AArch64
::
STRWui
:
case
AArch64
::
STURWi
:
case
AArch64
::
LDPSi
:
case
AArch64
::
LDPSWi
:
case
AArch64
::
LDPWi
:
case
AArch64
::
STPSi
:
case
AArch64
::
STPWi
:
return
4
;
case
AArch64
::
LDRDui
:
case
AArch64
::
LDURDi
:
case
AArch64
::
LDRXui
:
case
AArch64
::
LDURXi
:
case
AArch64
::
STRDui
:
case
AArch64
::
STURDi
:
case
AArch64
::
STRXui
:
case
AArch64
::
STURXi
:
case
AArch64
::
LDPDi
:
case
AArch64
::
LDPXi
:
case
AArch64
::
STPDi
:
case
AArch64
::
STPXi
:
return
8
;
case
AArch64
::
LDRQui
:
case
AArch64
::
LDURQi
:
case
AArch64
::
STRQui
:
case
AArch64
::
STURQi
:
case
AArch64
::
LDPQi
:
case
AArch64
::
STPQi
:
return
16
;
}
}
</s>

Scaling factor for ( scaled or unscaled ) load or store .


<s>
bool
PPCInstrInfo
::
isReallyTriviallyReMaterializable
(
const
MachineInstr
&
MI
,
AliasAnalysis
*
AA
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown rematerializable operation!"
)
;
break
;
case
PPC
::
LI
:
case
PPC
::
LI8
:
case
PPC
::
LIS
:
case
PPC
::
LIS8
:
case
PPC
::
QVGPCI
:
case
PPC
::
ADDIStocHA8
:
case
PPC
::
ADDItocL
:
case
PPC
::
LOAD_STACK_GUARD
:
case
PPC
::
XXLXORz
:
case
PPC
::
XXLXORspz
:
case
PPC
::
XXLXORdpz
:
case
PPC
::
V_SET0B
:
case
PPC
::
V_SET0H
:
case
PPC
::
V_SET0
:
case
PPC
::
V_SETALLONESB
:
case
PPC
::
V_SETALLONESH
:
case
PPC
::
V_SETALLONES
:
case
PPC
::
CRSET
:
case
PPC
::
CRUNSET
:
return
true
;
}
return
false
;
}
</s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> SMLoc getLoc ( ) const { return Parser . getTok ( ) . getLoc ( ) ; } </s>

Get the source location of the point where the field was defined .


<s> SDValue PIC16TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , DebugLoc dl , SelectionDAG & DAG ) { unsigned NumRet = Outs . size ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function * F = MF . getFunction ( ) ; std :: string FuncName = F -> getName ( ) ; const char * tmpName = createESName ( PAN :: getFrameLabel ( FuncName ) ) ; SDValue ES = DAG . getTargetExternalSymbol ( tmpName , MVT :: i8 ) ; SDValue BS = DAG . getConstant ( 1 , MVT :: i8 ) ; SDValue RetVal ; for ( unsigned i = 0 ; i < NumRet ; ++ i ) { RetVal = Outs [ i ] . Val ; Chain = DAG . getNode ( PIC16ISD :: PIC16Store , dl , MVT :: Other , Chain , RetVal , ES , BS , DAG . getConstant ( i , MVT :: i8 ) ) ; } return DAG . getNode ( PIC16ISD :: RET , dl , MVT :: Other , Chain ) ; } </s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool MipsPassConfig :: addPreEmitPass ( ) { MipsTargetMachine & TM = getMipsTargetMachine ( ) ; addPass ( createMipsDelaySlotFillerPass ( TM ) ) ; if ( TM . getSubtarget < MipsSubtarget > ( ) . hasStandardEncoding ( ) ) addPass ( createMipsLongBranchPass ( TM ) ) ; if ( TM . getSubtarget < MipsSubtarget > ( ) . inMips16Mode ( ) ) addPass ( createMipsConstantIslandPass ( TM ) ) ; if ( getMipsSubtarget ( ) . isTargetNaCl ( ) ) { addPass ( createMipsNaClRewritePass ( ) ) ; } return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips


<s>
SDValue
MSP430TargetLowering
::
LowerCall
(
SDValue
Chain
,
SDValue
Callee
,
unsigned
CallConv
,
bool
isVarArg
,
bool
isTailCall
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void GCNPassConfig :: addPreSched2 ( ) { addPass ( createSIInsertWaits ( * TM ) , false ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s>
bool
scalar_chain
::
add_insn
(
bitmap
candidates
,
unsigned
int
insn_uid
,
bitmap
disallowed
)
{
if
(
!
bitmap_set_bit
(
insns
,
insn_uid
)
)
return
true
;
if
(
dump_file
)
fprintf
(
dump_file
,
"  Adding insn %d to chain #%d\n"
,
insn_uid
,
chain_id
)
;
rtx_insn
*
insn
=
DF_INSN_UID_GET
(
insn_uid
)
->
insn
;
rtx
def_set
=
single_set
(
insn
)
;
if
(
def_set
&&
REG_P
(
SET_DEST
(
def_set
)
)
&&
!
HARD_REGISTER_P
(
SET_DEST
(
def_set
)
)
)
bitmap_set_bit
(
defs
,
REGNO
(
SET_DEST
(
def_set
)
)
)
;
df_ref
ref
;
for
(
ref
=
DF_INSN_UID_DEFS
(
insn_uid
)
;
ref
;
ref
=
DF_REF_NEXT_LOC
(
ref
)
)
if
(
!
HARD_REGISTER_P
(
DF_REF_REG
(
ref
)
)
)
if
(
!
analyze_register_chain
(
candidates
,
ref
,
disallowed
)
)
return
false
;
if
(
def_set
&&
GET_CODE
(
SET_SRC
(
def_set
)
)
==
VEC_SELECT
)
return
true
;
for
(
ref
=
DF_INSN_UID_USES
(
insn_uid
)
;
ref
;
ref
=
DF_REF_NEXT_LOC
(
ref
)
)
if
(
!
DF_REF_REG_MEM_P
(
ref
)
)
if
(
!
analyze_register_chain
(
candidates
,
ref
,
disallowed
)
)
return
false
;
return
true
;
}
</s>

Add instruction into a chain . Return true if OK , false if the search was aborted .


<s> HexagonTargetObjectFile * getObjFileLowering ( ) const override { return static_cast < HexagonTargetObjectFile * > ( TLOF . get ( ) ) ; } </s>

Return information about object file lowering .


<s> static void nvptx_assemble_value ( unsigned HOST_WIDE_INT val , unsigned size ) { bool negative_p = val & ( HOST_WIDE_INT_1U << ( HOST_BITS_PER_WIDE_INT - 1 ) ) ; if ( size * BITS_PER_UNIT < HOST_BITS_PER_WIDE_INT ) val &= ( HOST_WIDE_INT_1U << ( size * BITS_PER_UNIT ) ) - 1 ; for ( unsigned part = 0 ; size ; size -= part ) { if ( part * BITS_PER_UNIT == HOST_BITS_PER_WIDE_INT ) val = negative_p ? - 1 : 0 ; else val >>= ( part * BITS_PER_UNIT ) ; part = init_frag . size - init_frag . offset ; part = MIN ( part , size ) ; unsigned HOST_WIDE_INT partial = val << ( init_frag . offset * BITS_PER_UNIT ) ; init_frag . val |= partial & init_frag . mask ; init_frag . offset += part ; if ( init_frag . offset == init_frag . size ) output_init_frag ( NULL ) ; } } </s>

Add value VAL sized SIZE to the data we 're emitting , and keep writing out chunks as they fill up .


<s> bool aarch64_can_const_movi_rtx_p ( rtx x , machine_mode mode ) { if ( ! TARGET_SIMD ) return false ; machine_mode vmode ; scalar_int_mode imode ; unsigned HOST_WIDE_INT ival ; if ( GET_CODE ( x ) == CONST_DOUBLE && SCALAR_FLOAT_MODE_P ( mode ) ) { if ( ! aarch64_reinterpret_float_as_int ( x , & ival ) ) return false ; if ( aarch64_float_const_zero_rtx_p ( x ) ) return true ; imode = int_mode_for_mode ( mode ) . require ( ) ; } else if ( GET_CODE ( x ) == CONST_INT && is_a < scalar_int_mode > ( mode , & imode ) ) ival = INTVAL ( x ) ; else return false ; int width = GET_MODE_BITSIZE ( imode ) == 64 ? 128 : 64 ; vmode = aarch64_simd_container_mode ( imode , width ) ; rtx v_op = aarch64_simd_gen_const_vector_dup ( vmode , ival ) ; return aarch64_simd_valid_immediate ( v_op , NULL ) ; } </s>

Return TRUE if rtx X is immediate constant that fits in a single MOVI immediate operation .


<s> static const char * elf_platform ( void ) { int fd ; fd = open ( "/proc/self/auxv" , O_RDONLY ) ; if ( fd != - 1 ) { char buf [ 1024 ] ; ElfW ( auxv_t ) * av ; ssize_t n ; n = read ( fd , buf , sizeof ( buf ) ) ; close ( fd ) ; if ( n > 0 ) { for ( av = ( ElfW ( auxv_t ) * ) buf ; av -> a_type != AT_NULL ; ++ av ) switch ( av -> a_type ) { case AT_PLATFORM : return ( const char * ) av -> a_un . a_val ; default : break ; } } } </s>

Returns the canonical AT_PLATFORM if present , otherwise NULL .


<s> Value * AArch64TargetLowering :: emitLoadLinked ( IRBuilder < > & Builder , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Type * ValTy = cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ; bool IsAcquire = isAcquireOrStronger ( Ord ) ; if ( ValTy -> getPrimitiveSizeInBits ( ) == 128 ) { Intrinsic :: ID Int = IsAcquire ? Intrinsic :: aarch64_ldaxp : Intrinsic :: aarch64_ldxp ; Function * Ldxr = Intrinsic :: getDeclaration ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldxr , Addr , "lohi" ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ; Lo = Builder . CreateZExt ( Lo , ValTy , "lo64" ) ; Hi = Builder . CreateZExt ( Hi , ValTy , "hi64" ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , 64 ) ) , "val64" ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; Intrinsic :: ID Int = IsAcquire ? Intrinsic :: aarch64_ldaxr : Intrinsic :: aarch64_ldxr ; Function * Ldxr = Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateTruncOrBitCast ( Builder . CreateCall ( Ldxr , Addr ) , cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ) ; } </s>

Perform a load-linked operation on Addr , returning a `` Value * '' with the corresponding pointee type .


<s> WebAssemblyTargetMachine :: WebAssemblyTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , TT . isArch64Bit ( ) ? "e-m:e-p:64:64-i64:64-n32:64-S128" : "e-m:e-p:32:32-i64:64-n32:64-S128" , TT , CPU , FS , Options , getEffectiveRelocModel ( RM , TT ) , getEffectiveCodeModel ( CM , CodeModel :: Large ) , OL ) , TLOF ( new WebAssemblyTargetObjectFile ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . FunctionSections = true ; this -> Options . DataSections = true ; this -> Options . UniqueSectionNames = true ; initAsmInfo ( ) ; } </s>

Create an WebAssembly architecture model .

WebAssembly WebAssembly WebAssembly "e-m:e-p:64:64-i64:64-n32:64-S128" "e-m:e-p:32:32-i64:64-n32:64-S128" WebAssembly


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> const MCPhysReg * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const ARMSubtarget & STI = MF -> getSubtarget < ARMSubtarget > ( ) ; bool UseSplitPush = STI . splitFramePushPop ( * MF ) ; const MCPhysReg * RegList = STI . isTargetDarwin ( ) ? CSR_iOS_SaveList : ( UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList ) ; const Function * F = MF -> getFunction ( ) ; if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F -> hasFnAttribute ( "interrupt" ) ) { if ( STI . isMClass ( ) ) { return UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList ; } else if ( F -> getFnAttribute ( "interrupt" ) . getValueAsString ( ) == "FIQ" ) { return CSR_FIQ_SaveList ; } else { return CSR_GenericInt_SaveList ; } } if ( STI . isTargetDarwin ( ) && STI . getTargetLowering ( ) -> supportSwiftError ( ) && F -> getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_iOS_SwiftError_SaveList ; if ( STI . isTargetDarwin ( ) && F -> getCallingConv ( ) == CallingConv :: CXX_FAST_TLS ) return MF -> getInfo < ARMFunctionInfo > ( ) -> isSplitCSR ( ) ? CSR_iOS_CXX_TLS_PE_SaveList : CSR_iOS_CXX_TLS_SaveList ; return RegList ; } </s>

ARM ARM ARM ARM "interrupt" "interrupt" "FIQ" ARM


<s> unsigned XCoreInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { int Opcode = MI . getOpcode ( ) ; if ( Opcode == XCore :: STWFI ) { if ( ( MI . getOperand ( 1 ) . isFI ( ) ) && ( MI . getOperand ( 2 ) . isImm ( ) ) && ( isZeroImm ( MI . getOperand ( 2 ) ) ) ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> ArrayRef < std :: pair < int , const char * >> WebAssemblyInstrInfo :: getSerializableTargetIndices ( ) const { static const std :: pair < int , const char * > TargetIndices [ ] = { { WebAssembly :: TI_LOCAL , "wasm-local" } , { WebAssembly :: TI_GLOBAL_FIXED , "wasm-global-fixed" } , { WebAssembly :: TI_OPERAND_STACK , "wasm-operand-stack" } , { WebAssembly :: TI_GLOBAL_RELOC , "wasm-global-reloc" } , { WebAssembly :: TI_LOCAL_INDIRECT , "wasm-local-indirect" } } ; return makeArrayRef ( TargetIndices ) ; } </s>

Return an array that contains the ids of the target indices ( used for the TargetIndex machine operand ) and their names .


<s> const char * Tile64TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case T64ISD :: MOVELO : return "T64ISD::MOVELO" ; case T64ISD :: ADDLO_PIC : return "T64ISD::ADDLO_PIC" ; case T64ISD :: ADDHI : return "T64ISD::ADDHI" ; case T64ISD :: ADDHI_PIC : return "T64ISD::ADDHI_PIC" ; case T64ISD :: ADDLI_GOT : return "T64ISD::ADDLI_GOT" ; case T64ISD :: JAL : return "T64ISD::JAL" ; case T64ISD :: JALR : return "T64ISD::JALR" ; case T64ISD :: JRP : return "T64ISD::JRP" ; case T64ISD :: CALL : return "T64ISD::CALL" ; case T64ISD :: PICCALL : return "T64ISD::PICCALL" ; case T64ISD :: PREFETCH : return "T64ISD::PREFETCH" ; case T64ISD :: FENCE : return "T64ISD::FENCE" ; case T64ISD :: MEMBARRIER : return "T64ISD::MEMBARRIER" ; case T64ISD :: MULHH_SS : return "T64ISD::MULHH_SS" ; case T64ISD :: MULHH_SU : return "T64ISD::MULHH_SU" ; case T64ISD :: MULHH_UU : return "T64IDF::MULHH_UU" ; case T64ISD :: MULHHA_SS : return "T64ISD::MULHHA_SS" ; case T64ISD :: MULHHA_SU : return "T64ISD::MULHHA_SU" ; case T64ISD :: MULHHA_UU : return "T64ISD::MULHHA_UU" ; case T64ISD :: MULHHSA_UU : return "T64ISD::MULHHSA_UU" ; case T64ISD :: MULHL_SS : return "T64ISD::MULHL_SS" ; case T64ISD :: MULHL_SU : return "T64ISD::MULHL_SU" ; case T64ISD :: MULHL_US : return "T64ISD::MULHL_US" ; case T64ISD :: MULHL_UU : return "T64ISD::MULHL_UU" ; case T64ISD :: MULHLA_SS : return "T64ISD::MULHLA_SS" ; case T64ISD :: MULHLA_SU : return "T64ISD::MULHLA_SU" ; case T64ISD :: MULHLA_US : return "T64ISD::MULHLA_US" ; case T64ISD :: MULHLA_UU : return "T64ISD::MULHLA_UU" ; case T64ISD :: MULHLSA_UU : return "T64ISD::MULHLSA_UU" ; case T64ISD :: MULLL_SS : return "T64ISD::MULLL_SS" ; case T64ISD :: MULLL_SU : return "T64ISD::MULLL_SU" ; case T64ISD :: MULLL_UU : return "T64ISD::MULLL_UU" ; case T64ISD :: MULLLA_SS : return "T64ISD::MULLLA_SS" ; case T64ISD :: MULLLA_SU : return "T64ISD::MULLLA_SU" ; case T64ISD :: MULLLA_UU : return "T64ISD::MULLLA_UU" ; case T64ISD :: MULLLSA_UU : return "T64ISD::MULLLSA_UU" ; case T64ISD :: FNOP : return "T64ISD::FNOP" ; case T64ISD :: NOP : return "T64ISD::NOP" ; case T64ISD :: BITX : return "T64ISD::BITX" ; case T64ISD :: CRC32_32 : return "T64ISD::CRC32_32" ; case T64ISD :: CRC32_8 : return "T64ISD::CRC32_8" ; case T64ISD :: MM : return "T64ISD::MM" ; case T64ISD :: GLOBAL_BASE_REG : return "T64ISD::GLOBAL_BASE_REG" ; case T64ISD :: STORE_FP : return "T64ISD::STORE_FP" ; case T64ISD :: NEWSLOT_ADDR : return "T64ISD::NEWSLOT_ADDR" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> bool xtensa_simm8 ( HOST_WIDE_INT v ) { return v >= - 128 && v <= 127 ; } </s>

Functions to test Xtensa immediate operand validity .


<s>
SDValue
ARMTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
assert
(
0
&&
"Don't know how to custom lower this!"
)
;
abort
(
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
Subtarget
->
isTargetDarwin
(
)
LowerGlobalAddressDarwin
(
Op
,
DAG
)
:
LowerGlobalAddressELF
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
CALL
:
return
LowerCALL
(
Op
,
DAG
)
;
case
ISD
::
RET
:
return
LowerRET
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
,
Subtarget
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
,
Subtarget
)
;
case
ISD
::
BR_JT
:
return
LowerBR_JT
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
,
VarArgsFrameIndex
)
;
case
ISD
::
SINT_TO_FP
:
case
ISD
::
UINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
)
;
case
ISD
::
FCOPYSIGN
:
return
LowerFCOPYSIGN
(
Op
,
DAG
)
;
case
ISD
::
FORMAL_ARGUMENTS
:
return
LowerFORMAL_ARGUMENTS
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
break
;
case
ISD
::
FRAMEADDR
:
break
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
return
LowerGLOBAL_OFFSET_TABLE
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
BIT_CONVERT
:
return
ExpandBIT_CONVERT
(
Op
.
getNode
(
)
,
DAG
)
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
return
ExpandSRx
(
Op
.
getNode
(
)
,
DAG
,
Subtarget
)
;
}
return
SDValue
(
)
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


"WebAssembly should not have callee-saved registers"

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


"eliminateFrameIndex currently requires hasFP"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> rtx neon_make_constant ( rtx vals , bool generate ) { machine_mode mode = GET_MODE ( vals ) ; rtx target ; rtx const_vec = NULL_RTX ; int n_elts = GET_MODE_NUNITS ( mode ) ; int n_const = 0 ; int i ; if ( GET_CODE ( vals ) == CONST_VECTOR ) const_vec = vals ; else if ( GET_CODE ( vals ) == PARALLEL ) { for ( i = 0 ; i < n_elts ; ++ i ) { rtx x = XVECEXP ( vals , 0 , i ) ; if ( CONST_INT_P ( x ) || CONST_DOUBLE_P ( x ) ) n_const ++ ; } if ( n_const == n_elts ) const_vec = gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , 0 ) ) ; } else gcc_unreachable ( ) ; if ( const_vec != NULL && simd_immediate_valid_for_move ( const_vec , mode , NULL , NULL ) ) return const_vec ; else if ( TARGET_HAVE_MVE && VALID_MVE_PRED_MODE ( mode ) ) return mve_bool_vec_to_const ( const_vec ) ; else if ( ( target = neon_vdup_constant ( vals , generate ) ) != NULL_RTX ) return target ; else if ( const_vec != NULL_RTX ) return arm_disable_literal_pool ? NULL_RTX : const_vec ; else return NULL_RTX ; } </s>

Generate code to load VALS , which is a PARALLEL containing only constants ( for vec_init ) or CONST_VECTOR , efficiently into a register . Returns an RTX to copy into the register , or NULL_RTX for a PARALLEL that can not be converted into a CONST_VECTOR .


"Byval argument's alignment should be a multiple of RegSizeInBytes."

Target-specific cleanup for formal ByVal parameters .


<s> Register RISCVRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? RISCV :: X8 : RISCV :: X2 ; } </s>


<s> static void mips_output_args_xfer ( int fp_code , char direction ) { unsigned int gparg , fparg , f ; CUMULATIVE_ARGS cum ; gcc_assert ( TARGET_OLDABI ) ; mips_init_cumulative_args ( & cum , NULL ) ; for ( f = ( unsigned int ) fp_code ; f != 0 ; f >>= 2 ) { machine_mode mode ; struct mips_arg_info info ; if ( ( f & 3 ) == 1 ) mode = SFmode ; else if ( ( f & 3 ) == 2 ) mode = DFmode ; else gcc_unreachable ( ) ; mips_get_arg_info ( & info , & cum , mode , NULL , true ) ; gparg = mips_arg_regno ( & info , false ) ; fparg = mips_arg_regno ( & info , true ) ; if ( mode == SFmode ) mips_output_32bit_xfer ( direction , gparg , fparg ) ; else mips_output_64bit_xfer ( direction , gparg , fparg ) ; function_arg_info arg ( mode , true ) ; mips_function_arg_advance ( pack_cumulative_args ( & cum ) , arg ) ; } } </s>

Write out code to move floating-point arguments into or out of general registers . FP_CODE is the code describing which arguments are present ( see the comment above the definition of CUMULATIVE_ARGS in mips.h ) . DIRECTION is as for mips_output_32bit_xfer .


<s> EVT ARMTargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return getPointerTy ( DL ) ; if ( ( Subtarget -> hasMVEIntegerOps ( ) && ( VT == MVT :: v2i64 || VT == MVT :: v4i32 || VT == MVT :: v8i16 || VT == MVT :: v16i8 ) ) || ( Subtarget -> hasMVEFloatOps ( ) && ( VT == MVT :: v2f64 || VT == MVT :: v4f32 || VT == MVT :: v8f16 ) ) ) return MVT :: getVectorVT ( MVT :: i1 , VT . getVectorElementCount ( ) ) ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> bool writeNopData ( raw_ostream & OS , uint64_t Count ) const override { if ( Count == 0 ) { return true ; } return false ; } </s>


<s> SMLoc getEndLoc ( ) const { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


"Instruction should be in a basic block!"

"Generic instruction has unexpected implicit operands\n"

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s> bool enableEarlyIfConversion ( ) const override { return true ; } </s>

Enable the use of the early if conversion pass .