<s> bool CopyGeneration :: processBlock ( MachineBasicBlock & B , const RegisterSet & AVs ) { if ( ! BT . reached ( & B ) ) return false ; RegisterSet AVB ( AVs ) ; bool Changed = false ; RegisterSet Defs ; for ( auto I = B . begin ( ) , E = B . end ( ) , NextI = I ; I != E ; ++ I , AVB . insert ( Defs ) ) { NextI = std :: next ( I ) ; Defs . clear ( ) ; HBS :: getInstrDefs ( * I , Defs ) ; unsigned Opc = I -> getOpcode ( ) ; if ( CopyPropagation :: isCopyReg ( Opc , false ) || ConstGeneration :: isTfrConst ( * I ) ) continue ; DebugLoc DL = I -> getDebugLoc ( ) ; auto At = I -> isPHI ( ) ? B . getFirstNonPHI ( ) : I ; for ( unsigned R = Defs . find_first ( ) ; R ; R = Defs . find_next ( R ) ) { BitTracker :: RegisterRef MR ; auto * FRC = HBS :: getFinalVRegClass ( R , MRI ) ; if ( findMatch ( R , MR , AVB ) ) { unsigned NewR = MRI . createVirtualRegister ( FRC ) ; BuildMI ( B , At , DL , HII . get ( TargetOpcode :: COPY ) , NewR ) . addReg ( MR . Reg , 0 , MR . Sub ) ; BT . put ( BitTracker :: RegisterRef ( NewR ) , BT . get ( MR ) ) ; HBS :: replaceReg ( R , NewR , MRI ) ; Forbidden . insert ( R ) ; continue ; } if ( FRC == & Hexagon :: DoubleRegsRegClass || FRC == & Hexagon :: VecDblRegsRegClass || FRC == & Hexagon :: VecDblRegs128BRegClass ) { BitTracker :: RegisterRef TL = { R , Hexagon :: subreg_loreg } ; BitTracker :: RegisterRef TH = { R , Hexagon :: subreg_hireg } ; BitTracker :: RegisterRef ML , MH ; if ( findMatch ( TL , ML , AVB ) && findMatch ( TH , MH , AVB ) ) { auto * FRC = HBS :: getFinalVRegClass ( R , MRI ) ; unsigned NewR = MRI . createVirtualRegister ( FRC ) ; BuildMI ( B , At , DL , HII . get ( TargetOpcode :: REG_SEQUENCE ) , NewR ) . addReg ( ML . Reg , 0 , ML . Sub ) . addImm ( Hexagon :: subreg_loreg ) . addReg ( MH . Reg , 0 , MH . Sub ) . addImm ( Hexagon :: subreg_hireg ) ; BT . put ( BitTracker :: RegisterRef ( NewR ) , BT . get ( R ) ) ; HBS :: replaceReg ( R , NewR , MRI ) ; Forbidden . insert ( R ) ; } } } } return Changed ; } </s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s> void assignValueToAddress ( const CallLowering :: ArgInfo & Arg , Register Addr , uint64_t MemSize , MachinePointerInfo & MPO , CCValAssign & VA ) override { Register ValVReg = VA . getLocInfo ( ) != CCValAssign :: LocInfo :: FPExt ? extendRegister ( Arg . Regs [ 0 ] , VA ) : Arg . Regs [ 0 ] ; const LLT RegTy = MRI . getType ( ValVReg ) ; MemSize = std :: min ( MemSize , ( uint64_t ) RegTy . getSizeInBytes ( ) ) ; assignValueToAddress ( ValVReg , Addr , MemSize , MPO , VA ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> int SystemZFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { int64_t Offset = TargetFrameLowering :: getFrameIndexReference ( MF , FI , FrameReg ) ; return Offset + SystemZMC :: CallFrameSize ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> static struct machine_function * moxie_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function > ( ) ; } </s>

Zero initialization is OK for all current fields .


<s> bool NVPTXImageOptimizer :: runOnFunction ( Function & F ) { bool Changed = false ; InstrToDelete . clear ( ) ; for ( Function :: iterator BI = F . begin ( ) , BE = F . end ( ) ; BI != BE ; ++ BI ) { for ( BasicBlock :: iterator I = ( * BI ) . begin ( ) , E = ( * BI ) . end ( ) ; I != E ; ++ I ) { Instruction & Instr = * I ; if ( CallInst * CI = dyn_cast < CallInst > ( I ) ) { Function * CalledF = CI -> getCalledFunction ( ) ; if ( CalledF && CalledF -> isIntrinsic ( ) ) { switch ( CalledF -> getIntrinsicID ( ) ) { default : break ; case Intrinsic :: nvvm_istypep_sampler : Changed |= replaceIsTypePSampler ( Instr ) ; break ; case Intrinsic :: nvvm_istypep_surface : Changed |= replaceIsTypePSurface ( Instr ) ; break ; case Intrinsic :: nvvm_istypep_texture : Changed |= replaceIsTypePTexture ( Instr ) ; break ; } } } } } for ( unsigned i = 0 , e = InstrToDelete . size ( ) ; i != e ; ++ i ) InstrToDelete [ i ] -> eraseFromParent ( ) ; return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


Write PATCH_AREA_SIZE NOPs into the asm outfile FILE around a function entry . If RECORD_P is true and the target supports named sections , the location of the NOPs will be recorded in a special object section called `` __patchable_function_entries '' . This routine may be called twice per function to put NOPs before and after the function entry .


<s> bool AArch64PassConfig :: addPreRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAdvSIMDScalar ) { addPass ( createAArch64AdvSIMDScalar ( ) ) ; addPass ( & PeepholeOptimizerID ) ; } return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> void ix86_expand_unary_operator ( enum rtx_code code , enum machine_mode mode , rtx operands [ ] ) { int matching_memory ; rtx src , dst , op , clob ; dst = operands [ 0 ] ; src = operands [ 1 ] ; matching_memory = 0 ; if ( MEM_P ( dst ) ) { if ( rtx_equal_p ( dst , src ) ) matching_memory = 1 ; else dst = gen_reg_rtx ( mode ) ; } if ( MEM_P ( src ) && ! matching_memory ) src = force_reg ( mode , src ) ; op = gen_rtx_SET ( VOIDmode , dst , gen_rtx_fmt_e ( code , mode , src ) ) ; if ( reload_in_progress || code == NOT ) { gcc_assert ( code == NOT ) ; emit_insn ( op ) ; } else { clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , op , clob ) ) ) ; } if ( dst != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , dst ) ; } </s>

Attempt to expand a unary operator . Make the expansion closer to the actual machine , then just general_operand , which will allow 2 separate memory references ( one output , one input ) in a single insn .


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> hasFnAttribute ( Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ! Subtarget -> isTargetNaCl ( ) && ( ( N -> getOpcode ( ) == X86ISD :: CALL && ! Subtarget -> callRegIndirect ( ) ) || ( N -> getOpcode ( ) == X86ISD :: TC_RETURN && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; MVT SrcVT = N -> getOperand ( 0 ) . getSimpleValueType ( ) ; MVT DstVT = N -> getSimpleValueType ( 0 ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const X86TargetLowering * X86Lowering = static_cast < const X86TargetLowering * > ( TLI ) ; bool SrcIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } MVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> bool X86FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; const X86Subtarget & STI = MF . getTarget ( ) . getSubtarget < X86Subtarget > ( ) ; bool hasGPR = false ; unsigned FirstReg = 0 ; unsigned Opc = STI . is64Bit ( ) ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; if ( ! MF . protectCSRs ( ) ) { BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else if ( ! hasGPR ) { FirstReg = Reg ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; hasGPR = true ; } else { BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MI , DL , TII . get ( X86 :: ADD64rr ) , FirstReg ) . addReg ( FirstReg ) . addReg ( Reg , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } } if ( MF . protectCSRs ( ) && hasGPR ) { assert ( FirstReg ) ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( FirstReg , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - 1 ] . getFrameIdx ( ) , RC , TRI ) ; -- MI ; MI -> setFlag ( MachineInstr :: FrameSetup ) ; ++ MI ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static bool ix86_expand_sse_fp_minmax ( rtx dest , enum rtx_code code , rtx cmp_op0 , rtx cmp_op1 , rtx if_true , rtx if_false ) { machine_mode mode ; bool is_min ; rtx tmp ; if ( code == LT ) ; else if ( code == UNGE ) std :: swap ( if_true , if_false ) ; else return false ; if ( rtx_equal_p ( cmp_op0 , if_true ) && rtx_equal_p ( cmp_op1 , if_false ) ) is_min = true ; else if ( rtx_equal_p ( cmp_op1 , if_true ) && rtx_equal_p ( cmp_op0 , if_false ) ) is_min = false ; else return false ; mode = GET_MODE ( dest ) ; if ( ! flag_finite_math_only || ! flag_unsafe_math_optimizations ) { int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX ; rtvec v ; if_true = force_reg ( mode , if_true ) ; v = gen_rtvec ( 2 , if_true , if_false ) ; tmp = gen_rtx_UNSPEC ( mode , v , u ) ; } else { code = is_min ? SMIN : SMAX ; tmp = gen_rtx_fmt_ee ( code , mode , if_true , if_false ) ; } emit_insn ( gen_rtx_SET ( dest , tmp ) ) ; return true ; } </s>

Detect conditional moves that exactly match min/max operational semantics . Note that this is IEEE safe , as long as we do n't interchange the operands . Returns FALSE if this conditional move does n't match a MIN/MAX , and TRUE if the operation is successful and instructions are emitted .


<s> bool empty ( ) const { return size ( ) == 0 ; } </s>

Determine whether this version information is empty ( e.g. , all version components are zero ) .


<s> bool AMDGPUPassConfig :: addPreSched2 ( ) { const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) addPass ( createR600EmitClauseMarkers ( * TM ) ) ; addPass ( & IfConverterID ) ; if ( ST . getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) addPass ( createR600ClauseMergePass ( * TM ) ) ; return false ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> void rl78_expand_epilogue ( void ) { int i , fs ; rtx sp = gen_rtx_REG ( HImode , STACK_POINTER_REGNUM ) ; rtx ax = gen_rtx_REG ( HImode , AX_REG ) ; int rb = 0 ; if ( rl78_is_naked_func ( ) ) return ; if ( frame_pointer_needed ) { emit_move_insn ( ax , gen_rtx_REG ( HImode , FRAME_POINTER_REGNUM ) ) ; emit_move_insn ( sp , ax ) ; } else { fs = cfun -> machine -> framesize_locals + cfun -> machine -> framesize_outgoing ; if ( fs > 254 * 3 ) { emit_move_insn ( ax , sp ) ; emit_insn ( gen_addhi3 ( ax , ax , GEN_INT ( fs ) ) ) ; emit_move_insn ( sp , ax ) ; } else { while ( fs > 0 ) { int fs_byte = ( fs > 254 ) ? 254 : fs ; emit_insn ( gen_addhi3 ( sp , sp , GEN_INT ( fs_byte ) ) ) ; fs -= fs_byte ; } } } if ( is_interrupt_func ( cfun -> decl ) && cfun -> machine -> uses_es ) { emit_insn ( gen_pop ( gen_rtx_REG ( HImode , AX_REG ) ) ) ; emit_insn ( gen_movqi_to_es ( gen_rtx_REG ( QImode , A_REG ) ) ) ; } for ( i = 15 ; i >= 0 ; i -- ) if ( cfun -> machine -> need_to_push [ i ] ) { rtx dest = gen_rtx_REG ( HImode , i * 2 ) ; if ( TARGET_G10 ) { if ( i < 8 ) emit_insn ( gen_pop ( dest ) ) ; else { emit_insn ( gen_pop ( ax ) ) ; emit_move_insn ( dest , ax ) ; emit_insn ( gen_use ( dest ) ) ; } } else { int need_bank = i / 4 ; if ( need_bank != rb ) { emit_insn ( gen_sel_rb ( GEN_INT ( need_bank ) ) ) ; rb = need_bank ; } emit_insn ( gen_pop ( dest ) ) ; } } if ( rb != 0 ) emit_insn ( gen_sel_rb ( GEN_INT ( 0 ) ) ) ; if ( cfun -> machine -> trampolines_used ) emit_insn ( gen_trampoline_uninit ( ) ) ; if ( is_brk_interrupt_func ( cfun -> decl ) ) emit_jump_insn ( gen_brk_interrupt_return ( ) ) ; else if ( is_interrupt_func ( cfun -> decl ) ) emit_jump_insn ( gen_interrupt_return ( ) ) ; else emit_jump_insn ( gen_rl78_return ( ) ) ; } </s>

Expand the function epilogue ( from the epilogue pattern ) .


<s> static bool aarch64_advsimd_ldp_stp_p ( enum vect_cost_for_stmt kind , stmt_vec_info stmt_info ) { switch ( kind ) { case vector_load : case vector_store : case unaligned_load : case unaligned_store : break ; default : return false ; } if ( aarch64_tune_params . extra_tuning_flags & AARCH64_EXTRA_TUNE_NO_LDP_STP_QREGS ) return false ; return is_gimple_assign ( stmt_info -> stmt ) ; } </s>

Return true if creating multiple copies of STMT_INFO for Advanced SIMD vectors would produce a series of LDP or STP operations . KIND is the kind of statement that STMT_INFO represents .


<s> virtual void loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { loadRegFromStack ( MBB , MBBI , DestReg , FrameIndex , RC , TRI , 0 ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> bool RISCVTargetLowering :: hasAndNotCompare ( SDValue Y ) const { EVT VT = Y . getValueType ( ) ; if ( VT . isVector ( ) ) return false ; return ( Subtarget . hasStdExtZbb ( ) || Subtarget . hasStdExtZbp ( ) || Subtarget . hasStdExtZbkb ( ) ) && ! isa < ConstantSDNode > ( Y ) ; } </s>

Return true if the target should transform : ( X & Y ) == Y � ? ( ~X & Y ) == 0 ( X & Y ) ! = Y � ? ( ~X & Y ) ! = 0 .


<s> bool mips16e_save_restore_pattern_p ( rtx pattern , HOST_WIDE_INT adjust , struct mips16e_save_restore_info * info ) { unsigned int i , nargs , mask , extra ; HOST_WIDE_INT top_offset , save_offset , offset ; rtx set , reg , mem , base ; int n ; if ( ! GENERATE_MIPS16E_SAVE_RESTORE ) return false ; top_offset = adjust > 0 ? adjust : 0 ; save_offset = top_offset - UNITS_PER_WORD ; mask = 0 ; nargs = 0 ; i = 0 ; for ( n = 1 ; n < XVECLEN ( pattern , 0 ) ; n ++ ) { set = XVECEXP ( pattern , 0 , n ) ; if ( GET_CODE ( set ) != SET ) return false ; mem = adjust > 0 ? SET_SRC ( set ) : SET_DEST ( set ) ; if ( ! MEM_P ( mem ) ) return false ; mips_split_plus ( XEXP ( mem , 0 ) , & base , & offset ) ; if ( base != stack_pointer_rtx ) return false ; reg = adjust > 0 ? SET_DEST ( set ) : SET_SRC ( set ) ; if ( ! REG_P ( reg ) ) return false ; if ( offset == top_offset + nargs * UNITS_PER_WORD && REGNO ( reg ) == GP_ARG_FIRST + nargs ) nargs ++ ; else if ( offset == save_offset ) { while ( mips16e_save_restore_regs [ i ++ ] != REGNO ( reg ) ) if ( i == ARRAY_SIZE ( mips16e_save_restore_regs ) ) return false ; mask |= 1 << REGNO ( reg ) ; save_offset -= UNITS_PER_WORD ; } else return false ; } extra = 0 ; mips16e_mask_registers ( & mask , mips16e_s2_s8_regs , ARRAY_SIZE ( mips16e_s2_s8_regs ) , & extra ) ; mips16e_mask_registers ( & mask , mips16e_a0_a3_regs , ARRAY_SIZE ( mips16e_a0_a3_regs ) , & extra ) ; if ( extra != 0 ) return false ; if ( nargs > 0 && BITSET_P ( mask , GP_ARG_FIRST + nargs - 1 ) ) return false ; if ( info ) { info -> nargs = nargs ; info -> mask = mask ; info -> size = ( adjust > 0 ? adjust : - adjust ) ; } return true ; } </s>

PATTERN is a PARALLEL whose first element adds ADJUST to the stack pointer . Return true if PATTERN matches the kind of instruction generated by mips16e_build_save_restore . If INFO is nonnull , initialize it when returning true .


<s>
StringRef
getPassName
(
)
const
override
{
return
"WebAssembly Debug Fixup"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void Comet2ELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; } </s>

This method must be called before any actual lowering is done .


"SI insert s_cbranch_execz instructions"


<s> void Warning ( SMLoc L , const Twine & Msg ) { Parser . Warning ( L , Msg ) ; } </s>

Emit a warning at the location L , with the message Msg .


<s> static bool sh_cannot_substitute_mem_equiv_p ( rtx ) { if ( TARGET_SHMEDIA ) return false ; return true ; } </s>

Return true if SUBST ca n't safely replace its equivalent during RA .


<s> SDValue XtensaTargetLowering :: LowerCall ( TargetLowering :: CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const { SDValue ret ; return ret ; } </s>

This hook must be implemented to lower calls into the specified DAG .


<s>
const
MCPhysReg
*
X86RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
bool
HasAVX
=
Subtarget
.
hasAVX
(
)
;
bool
HasAVX512
=
Subtarget
.
hasAVX512
(
)
;
assert
(
MF
&&
"MachineFunction required"
)
;
switch
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
)
{
case
CallingConv
::
GHC
:
case
CallingConv
::
HiPE
:
return
CSR_NoRegs_SaveList
;
case
CallingConv
::
AnyReg
:
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
return
CSR_64_AllRegs_SaveList
;
case
CallingConv
::
PreserveMost
:
return
CSR_64_RT_MostRegs_SaveList
;
case
CallingConv
::
PreserveAll
:
if
(
HasAVX
)
return
CSR_64_RT_AllRegs_AVX_SaveList
;
return
CSR_64_RT_AllRegs_SaveList
;
case
CallingConv
::
Intel_OCL_BI
:
{
if
(
HasAVX512
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX512
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX_SaveList
;
if
(
HasAVX
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX_SaveList
;
if
(
!
HasAVX
&&
!
IsWin64
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_SaveList
;
break
;
}
case
CallingConv
::
Cold
:
if
(
Is64Bit
)
return
CSR_64_MostRegs_SaveList
;
break
;
default
:
break
;
}
bool
CallsEHReturn
=
MF
->
getMMI
(
)
.
callsEHReturn
(
)
;
bool
IsNaCl
=
Subtarget
.
isTargetNaCl
(
)
;
if
(
Is64Bit
)
{
if
(
IsWin64
)
return
CSR_Win64_SaveList
;
if
(
IsNaCl
)
{
if
(
CallsEHReturn
)
return
CSR_NaCl64EHRet_SaveList
;
return
CSR_NaCl64_SaveList
;
}
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
}
if
(
CallsEHReturn
)
return
CSR_32EHRet_SaveList
;
return
CSR_32_SaveList
;
}
</s>


<s> int mcore_arith_S_operand ( rtx op ) { if ( GET_CODE ( op ) == CONST_INT && CONST_OK_FOR_M ( ~ INTVAL ( op ) ) ) return 1 ; return 0 ; } </s>


<s> bool PPCInstrInfo :: ClobbersPredicate ( MachineInstr & MI , std :: vector < MachineOperand > & Pred , bool SkipDead ) const { const TargetRegisterClass * RCs [ ] = { & PPC :: CRRCRegClass , & PPC :: CRBITRCRegClass , & PPC :: CTRRCRegClass , & PPC :: CTRRC8RegClass } ; bool Found = false ; for ( unsigned i = 0 , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; for ( unsigned c = 0 ; c < array_lengthof ( RCs ) && ! Found ; ++ c ) { const TargetRegisterClass * RC = RCs [ c ] ; if ( MO . isReg ( ) ) { if ( MO . isDef ( ) && RC -> contains ( MO . getReg ( ) ) ) { Pred . push_back ( MO ) ; Found = true ; } } else if ( MO . isRegMask ( ) ) { for ( TargetRegisterClass :: iterator I = RC -> begin ( ) , IE = RC -> end ( ) ; I != IE ; ++ I ) if ( MO . clobbersPhysReg ( * I ) ) { Pred . push_back ( MO ) ; Found = true ; } } } } return Found ; } </s>

If the specified instruction defines any predicate or condition code register ( s ) used for predication , returns true as well as the definition predicate ( s ) by reference .


<s> void PPCPassConfig :: addMachineSSAOptimization ( ) { TargetPassConfig :: addMachineSSAOptimization ( ) ; if ( TM -> getTargetTriple ( ) . getArch ( ) == Triple :: ppc64le && ! DisableVSXSwapRemoval ) addPass ( createPPCVSXSwapRemovalPass ( ) ) ; if ( ! DisableMIPeephole ) { addPass ( createPPCMIPeepholePass ( ) ) ; addPass ( & DeadMachineInstructionElimID ) ; } } </s>

Methods with trivial inline returns are convenient points in the common codegen pass pipeline where targets may insert passes .


<s>
static
void
ix86_output_indirect_branch_via_reg
(
rtx
call_op
,
bool
sibcall_p
)
{
char
thunk_name_buf
[
32
]
;
char
*
thunk_name
;
enum
indirect_thunk_prefix
need_prefix
=
indirect_thunk_need_prefix
(
current_output_insn
)
;
int
regno
=
REGNO
(
call_op
)
;
if
(
cfun
->
machine
->
indirect_branch_type
!=
indirect_branch_thunk_inline
)
{
if
(
cfun
->
machine
->
indirect_branch_type
==
indirect_branch_thunk
)
{
int
i
=
regno
;
if
(
i
>=
FIRST_REX_INT_REG
)
i
-=
(
FIRST_REX_INT_REG
LAST_INT_REG
1
)
;
if
(
need_prefix
==
indirect_thunk_prefix_bnd
)
indirect_thunks_bnd_used
|=
1
<<
i
;
else
indirect_thunks_used
|=
1
<<
i
;
}
indirect_thunk_name
(
thunk_name_buf
,
regno
,
need_prefix
,
false
)
;
thunk_name
=
thunk_name_buf
;
}
else
thunk_name
=
;
if
(
sibcall_p
)
{
if
(
thunk_name
!=
)
{
if
(
need_prefix
==
indirect_thunk_prefix_bnd
)
fprintf
(
asm_out_file
,
"\tbnd jmp\t%s\n"
,
thunk_name
)
;
else
fprintf
(
asm_out_file
,
"\tjmp\t%s\n"
,
thunk_name
)
;
}
else
output_indirect_thunk
(
need_prefix
,
regno
)
;
}
else
{
if
(
thunk_name
!=
)
{
if
(
need_prefix
==
indirect_thunk_prefix_bnd
)
fprintf
(
asm_out_file
,
"\tbnd call\t%s\n"
,
thunk_name
)
;
else
fprintf
(
asm_out_file
,
"\tcall\t%s\n"
,
thunk_name
)
;
return
;
}
char
indirectlabel1
[
32
]
;
char
indirectlabel2
[
32
]
;
ASM_GENERATE_INTERNAL_LABEL
(
indirectlabel1
,
INDIRECT_LABEL
,
indirectlabelno
++
)
;
ASM_GENERATE_INTERNAL_LABEL
(
indirectlabel2
,
INDIRECT_LABEL
,
indirectlabelno
++
)
;
if
(
need_prefix
==
indirect_thunk_prefix_bnd
)
fputs
(
"\tbnd jmp\t"
,
asm_out_file
)
;
else
fputs
(
"\tjmp\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
indirectlabel2
)
;
fputc
(
'\n'
,
asm_out_file
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
indirectlabel1
)
;
if
(
thunk_name
!=
)
{
if
(
need_prefix
==
indirect_thunk_prefix_bnd
)
fprintf
(
asm_out_file
,
"\tbnd jmp\t%s\n"
,
thunk_name
)
;
else
fprintf
(
asm_out_file
,
"\tjmp\t%s\n"
,
thunk_name
)
;
}
else
output_indirect_thunk
(
need_prefix
,
regno
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
indirectlabel2
)
;
if
(
need_prefix
==
indirect_thunk_prefix_bnd
)
fputs
(
"\tbnd call\t"
,
asm_out_file
)
;
else
fputs
(
"\tcall\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
indirectlabel1
)
;
fputc
(
'\n'
,
asm_out_file
)
;
}
}
</s>

Output indirect branch via a call and return thunk . CALL_OP is a register which contains the branch target . XASM is the assembly template for CALL_OP . Branch is a tail call if SIBCALL_P is true . A normal call is converted to : call __x86_indirect_thunk_reg and a tail call is converted to : jmp __x86_indirect_thunk_reg


<s>
bool
AArch64TargetLowering
::
lowerInterleavedStore
(
StoreInst
*
SI
,
ShuffleVectorInst
*
SVI
,
unsigned
Factor
)
const
{
assert
(
Factor
>=
2
&&
Factor
<=
getMaxSupportedInterleaveFactor
(
)
&&
"Invalid interleave factor"
)
;
VectorType
*
VecTy
=
SVI
->
getType
(
)
;
assert
(
VecTy
->
getVectorNumElements
(
)
%
Factor
==
0
&&
"Invalid interleaved store"
)
;
if
(
Factor
>
4
)
return
false
;
unsigned
NumSubElts
=
VecTy
->
getVectorNumElements
(
)
/
Factor
;
Type
*
EltTy
=
VecTy
->
getVectorElementType
(
)
;
VectorType
*
SubVecTy
=
VectorType
::
get
(
EltTy
,
NumSubElts
)
;
const
DataLayout
&
DL
=
SI
->
getModule
(
)
->
getDataLayout
(
)
;
unsigned
SubVecSize
=
DL
.
getTypeSizeInBits
(
SubVecTy
)
;
if
(
!
Subtarget
->
hasNEON
(
)
||
(
SubVecSize
!=
64
&&
SubVecSize
!=
128
)
)
return
false
;
Value
*
Op0
=
SVI
->
getOperand
(
0
)
;
Value
*
Op1
=
SVI
->
getOperand
(
1
)
;
IRBuilder
<
>
Builder
(
SI
)
;
if
(
EltTy
->
isPointerTy
(
)
)
{
Type
*
IntTy
=
DL
.
getIntPtrType
(
EltTy
)
;
unsigned
NumOpElts
=
dyn_cast
<
VectorType
>
(
Op0
->
getType
(
)
)
->
getVectorNumElements
(
)
;
Type
*
IntVecTy
=
VectorType
::
get
(
IntTy
,
NumOpElts
)
;
Op0
=
Builder
.
CreatePtrToInt
(
Op0
,
IntVecTy
)
;
Op1
=
Builder
.
CreatePtrToInt
(
Op1
,
IntVecTy
)
;
SubVecTy
=
VectorType
::
get
(
IntTy
,
NumSubElts
)
;
}
Type
*
PtrTy
=
SubVecTy
->
getPointerTo
(
SI
->
getPointerAddressSpace
(
)
)
;
Type
*
Tys
[
2
]
=
{
SubVecTy
,
PtrTy
}
;
static
const
Intrinsic
::
ID
StoreInts
[
3
]
=
{
Intrinsic
::
aarch64_neon_st2
,
Intrinsic
::
aarch64_neon_st3
,
Intrinsic
::
aarch64_neon_st4
}
;
Function
*
StNFunc
=
Intrinsic
::
getDeclaration
(
SI
->
getModule
(
)
,
StoreInts
[
Factor
2
]
,
Tys
)
;
SmallVector
<
Value
*
,
5
>
Ops
;
for
(
unsigned
i
=
0
;
i
<
Factor
;
i
++
)
Ops
.
push_back
(
Builder
.
CreateShuffleVector
(
Op0
,
Op1
,
getSequentialMask
(
Builder
,
NumSubElts
*
i
,
NumSubElts
)
)
)
;
Ops
.
push_back
(
Builder
.
CreateBitCast
(
SI
->
getPointerOperand
(
)
,
PtrTy
)
)
;
Builder
.
CreateCall
(
StNFunc
,
Ops
)
;
return
true
;
}
</s>

Lower interleaved store ( s ) into target specific instructions/intrinsics .


<s> void WebAssemblyPassConfig :: addPreEmitPass ( ) { TargetPassConfig :: addPreEmitPass ( ) ; addPass ( createWebAssemblyCFGStackify ( ) ) ; addPass ( createWebAssemblyLowerBrUnless ( ) ) ; addPass ( createWebAssemblyRegNumbering ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createWebAssemblyPeephole ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly


<s> void arm_split_compare_and_swap ( rtx operands [ ] ) { rtx rval , mem , oldval , newval , scratch ; machine_mode mode ; enum memmodel mod_s , mod_f ; bool is_weak ; rtx_code_label * label1 , * label2 ; rtx x , cond ; rval = operands [ 0 ] ; mem = operands [ 1 ] ; oldval = operands [ 2 ] ; newval = operands [ 3 ] ; is_weak = ( operands [ 4 ] != const0_rtx ) ; mod_s = memmodel_from_int ( INTVAL ( operands [ 5 ] ) ) ; mod_f = memmodel_from_int ( INTVAL ( operands [ 6 ] ) ) ; scratch = operands [ 7 ] ; mode = GET_MODE ( mem ) ; bool is_armv8_sync = arm_arch8 && is_mm_sync ( mod_s ) ; bool use_acquire = TARGET_HAVE_LDACQ && ! ( is_mm_relaxed ( mod_s ) || is_mm_consume ( mod_s ) || is_mm_release ( mod_s ) ) ; bool use_release = TARGET_HAVE_LDACQ && ! ( is_mm_relaxed ( mod_s ) || is_mm_consume ( mod_s ) || is_mm_acquire ( mod_s ) ) ; if ( is_armv8_sync ) use_acquire = false ; if ( ! ( use_acquire || use_release ) ) arm_pre_atomic_barrier ( mod_s ) ; label1 = NULL ; if ( ! is_weak ) { label1 = gen_label_rtx ( ) ; emit_label ( label1 ) ; } label2 = gen_label_rtx ( ) ; arm_emit_load_exclusive ( mode , rval , mem , use_acquire ) ; cond = arm_gen_compare_reg ( NE , rval , oldval , scratch ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; arm_emit_store_exclusive ( mode , scratch , mem , newval , use_release ) ; cond = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_COMPARE ( CCmode , scratch , const0_rtx ) ; emit_insn ( gen_rtx_SET ( cond , x ) ) ; if ( ! is_weak ) { x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label1 ) , pc_rtx ) ; emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } if ( ! is_mm_relaxed ( mod_f ) ) emit_label ( label2 ) ; if ( is_armv8_sync || ! ( use_acquire || use_release ) ) arm_post_atomic_barrier ( mod_s ) ; if ( is_mm_relaxed ( mod_f ) ) emit_label ( label2 ) ; } </s>

Split a compare and swap pattern . It is IMPLEMENTATION DEFINED whether another memory store between the load-exclusive and store-exclusive can reset the monitor from Exclusive to Open state . This means we must wait until after reload to split the pattern , lest we get a register spill in the middle of the atomic sequence .


<s> StringRef getType ( ) { return CurType . Name ; } </s>

Overload to return most specific vector type .


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & ) const override { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> bool HexagonFrameLowering :: hasFP ( const MachineFunction & MF ) const { if ( MF . getFunction ( ) . hasFnAttribute ( Attribute :: Naked ) ) return false ; auto & MFI = MF . getFrameInfo ( ) ; auto & HRI = * MF . getSubtarget < HexagonSubtarget > ( ) . getRegisterInfo ( ) ; bool HasExtraAlign = HRI . hasStackRealignment ( MF ) ; bool HasAlloca = MFI . hasVarSizedObjects ( ) ; if ( MF . getTarget ( ) . getOptLevel ( ) == CodeGenOpt :: None ) return true ; if ( HasAlloca || HasExtraAlign ) return true ; if ( MFI . getStackSize ( ) > 0 ) { const TargetMachine & TM = MF . getTarget ( ) ; if ( TM . Options . DisableFramePointerElim ( MF ) || ! EliminateFramePointer ) return true ; if ( EnableStackOVFSanitizer ) return true ; } const auto & HMFI = * MF . getInfo < HexagonMachineFunctionInfo > ( ) ; if ( ( MFI . hasCalls ( ) && ! enableAllocFrameElim ( MF ) ) || HMFI . hasClobberLR ( ) ) return true ; return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Z80 Expand Pseudo Instructions"
;
}
</s>


<s> static void bfin_reorg ( void ) { compute_bb_for_insn ( ) ; if ( flag_schedule_insns_after_reload ) { splitting_for_sched = 1 ; split_all_insns ( ) ; splitting_for_sched = 0 ; add_sched_insns_for_speculation ( ) ; timevar_push ( TV_SCHED2 ) ; if ( flag_selective_scheduling2 && ! maybe_skip_selective_scheduling ( ) ) run_selective_scheduling ( ) ; else schedule_insns ( ) ; timevar_pop ( TV_SCHED2 ) ; bfin_gen_bundles ( ) ; } df_analyze ( ) ; if ( cfun -> machine -> has_hardware_loops ) bfin_reorg_loops ( ) ; workaround_speculation ( ) ; if ( flag_var_tracking ) { timevar_push ( TV_VAR_TRACKING ) ; variable_tracking_main ( ) ; reorder_var_tracking_notes ( ) ; timevar_pop ( TV_VAR_TRACKING ) ; } df_finish_pass ( false ) ; workaround_rts_anomaly ( ) ; } </s>

We use the machine specific reorg pass for emitting CSYNC instructions after conditional branches as needed . The Blackfin is unusual in that a code sequence like if cc jump label r0 = ( p0 ) may speculatively perform the load even if the condition is n't true . This happens for a branch that is predicted not taken , because the pipeline is n't flushed or stalled , so the early stages of the following instructions , which perform the memory reference , are allowed to execute before the jump condition is evaluated . Therefore , we must insert additional instructions in all places where this could lead to incorrect behavior . The manual recommends CSYNC , while VDSP seems to use NOPs ( even though its corresponding compiler option is named CSYNC ) . When optimizing for speed , we emit NOPs , which seems faster than a CSYNC . When optimizing for size , we turn the branch into a predicted taken one . This may be slower due to mispredicts , but saves code size .


<s> static bool reg_offset_addressing_ok_p ( machine_mode mode ) { switch ( mode ) { case V16QImode : case V8HImode : case V4SFmode : case V4SImode : case V2DFmode : case V2DImode : case V1TImode : case TImode : if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) ) return false ; break ; case V4HImode : case V2SImode : case V1DImode : case V2SFmode : if ( TARGET_PAIRED_FLOAT ) return false ; break ; case SDmode : if ( TARGET_NO_SDMODE_STACK ) return false ; break ; default : break ; } return true ; } </s>

Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Mips Long Branch"
;
}
</s>


<s> void handleAssemblerFlag ( MCAssemblerFlag Flag ) { switch ( Flag ) { default : break ; case MCAF_Code16 : setIsThumb ( true ) ; break ; case MCAF_Code32 : setIsThumb ( false ) ; break ; } } </s>

Handle any target-specific assembler flags . By default , do nothing .


<s> static bool pa_expand_compare_and_swap_loop ( rtx mem , rtx old_reg , rtx new_reg , rtx seq ) { machine_mode mode = GET_MODE ( mem ) ; rtx_code_label * label ; rtx cmp_reg , success , oldval ; label = gen_label_rtx ( ) ; cmp_reg = gen_reg_rtx ( mode ) ; emit_move_insn ( cmp_reg , mem ) ; emit_label ( label ) ; emit_move_insn ( old_reg , cmp_reg ) ; if ( seq ) emit_insn ( seq ) ; success = NULL_RTX ; oldval = cmp_reg ; if ( ! expand_atomic_compare_and_swap ( & success , & oldval , mem , old_reg , new_reg , false , MEMMODEL_SYNC_SEQ_CST , MEMMODEL_RELAXED ) ) return false ; if ( oldval != cmp_reg ) emit_move_insn ( cmp_reg , oldval ) ; emit_cmp_and_jump_insns ( success , const0_rtx , EQ , const0_rtx , GET_MODE ( success ) , 1 , label , profile_probability :: guessed_never ( ) ) ; return true ; } </s>

This is a helper function for the other atomic operations . This function emits a loop that contains SEQ that iterates until a compare-and-swap operation at the end succeeds . MEM is the memory to be modified . SEQ is a set of instructions that takes a value from OLD_REG as an input and produces a value in NEW_REG as an output . Before SEQ , OLD_REG will be set to the current contents of MEM . After SEQ , a compare-and-swap will attempt to update MEM with NEW_REG . The function returns true when the loop was generated successfully .


<s> bool TeakInstrInfo :: PredicateInstruction ( MachineInstr & MI , ArrayRef < MachineOperand > Pred ) const { dbgs ( ) << "PredicateInstruction\n" ; unsigned Opc = MI . getOpcode ( ) ; int PIdx = MI . findFirstPredOperandIdx ( ) ; if ( PIdx != - 1 ) { MachineOperand & PMO = MI . getOperand ( PIdx ) ; PMO . setImm ( Pred [ 0 ] . getImm ( ) ) ; if ( Pred [ 0 ] . getImm ( ) == TeakCC :: True ) MI . getOperand ( PIdx + 1 ) . ChangeToRegister ( 0 , false ) ; else MI . getOperand ( PIdx + 1 ) . ChangeToRegister ( Teak :: ICC , false , true ) ; return true ; } return false ; } </s>

Convert the instruction into a predicated instruction .


<s> bool JVMSubtarget :: enableMachineScheduler ( ) const { return false ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


<s> bool SIAnnotateControlFlow :: doInitialization ( Module & M ) { LLVMContext & Context = M . getContext ( ) ; Void = Type :: getVoidTy ( Context ) ; Boolean = Type :: getInt1Ty ( Context ) ; Int64 = Type :: getInt64Ty ( Context ) ; ReturnStruct = StructType :: get ( Boolean , Int64 ) ; BoolTrue = ConstantInt :: getTrue ( Context ) ; BoolFalse = ConstantInt :: getFalse ( Context ) ; BoolUndef = UndefValue :: get ( Boolean ) ; Int64Zero = ConstantInt :: get ( Int64 , 0 ) ; If = Intrinsic :: getDeclaration ( & M , Intrinsic :: amdgcn_if ) ; Else = Intrinsic :: getDeclaration ( & M , Intrinsic :: amdgcn_else ) ; IfBreak = Intrinsic :: getDeclaration ( & M , Intrinsic :: amdgcn_if_break ) ; Loop = Intrinsic :: getDeclaration ( & M , Intrinsic :: amdgcn_loop ) ; EndCf = Intrinsic :: getDeclaration ( & M , Intrinsic :: amdgcn_end_cf ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> bool prefixed_store_p ( rtx_insn * insn ) { extract_insn_cached ( insn ) ; if ( recog_data . n_operands < 2 ) return false ; rtx mem = recog_data . operand [ 0 ] ; rtx reg = recog_data . operand [ 1 ] ; if ( ! REG_P ( reg ) && ! SUBREG_P ( reg ) ) return false ; if ( ! MEM_P ( mem ) ) return false ; if ( get_attr_indexed ( insn ) == INDEXED_YES || get_attr_update ( insn ) == UPDATE_YES ) return false ; machine_mode mem_mode = GET_MODE ( mem ) ; rtx addr = XEXP ( mem , 0 ) ; enum non_prefixed_form non_prefixed = reg_to_non_prefixed ( reg , mem_mode ) ; if ( non_prefixed == NON_PREFIXED_X && is_lfs_stfs_insn ( insn ) ) return address_is_prefixed ( addr , mem_mode , NON_PREFIXED_DEFAULT ) ; else return address_is_prefixed ( addr , mem_mode , non_prefixed ) ; } </s>

Whether a store instruction is a prefixed instruction . This is called from the prefixed attribute processing .


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const PPCFrameLowering * PPCFI = static_cast < const PPCFrameLowering * > ( Subtarget . getFrameLowering ( ) ) ; Reserved . set ( PPC :: ZERO ) ; Reserved . set ( PPC :: ZERO8 ) ; Reserved . set ( PPC :: FP ) ; Reserved . set ( PPC :: FP8 ) ; Reserved . set ( PPC :: BP ) ; Reserved . set ( PPC :: BP8 ) ; Reserved . set ( PPC :: CTR ) ; Reserved . set ( PPC :: CTR8 ) ; Reserved . set ( PPC :: R1 ) ; Reserved . set ( PPC :: LR ) ; Reserved . set ( PPC :: LR8 ) ; Reserved . set ( PPC :: RM ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) Reserved . set ( PPC :: VRSAVE ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: R2 ) ; Reserved . set ( PPC :: R13 ) ; } if ( TM . isPPC64 ( ) ) { Reserved . set ( PPC :: R13 ) ; Reserved . set ( PPC :: X1 ) ; Reserved . set ( PPC :: X13 ) ; if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: X31 ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( PPC :: X30 ) ; if ( Subtarget . isSVR4ABI ( ) ) { const PPCFunctionInfo * FuncInfo = MF . getInfo < PPCFunctionInfo > ( ) ; if ( FuncInfo -> usesTOCBasePtr ( ) || MF . hasInlineAsm ( ) ) Reserved . set ( PPC :: X2 ) ; else Reserved . reset ( PPC :: R2 ) ; } } if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: R31 ) ; if ( hasBasePointer ( MF ) ) { if ( Subtarget . isSVR4ABI ( ) && ! TM . isPPC64 ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ) Reserved . set ( PPC :: R29 ) ; else Reserved . set ( PPC :: R30 ) ; } if ( Subtarget . isSVR4ABI ( ) && ! TM . isPPC64 ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ) Reserved . set ( PPC :: R30 ) ; if ( ! Subtarget . hasAltivec ( ) ) for ( TargetRegisterClass :: iterator I = PPC :: VRRCRegClass . begin ( ) , IE = PPC :: VRRCRegClass . end ( ) ; I != IE ; ++ I ) Reserved . set ( * I ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool ARMBaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const ARMFrameLowering * TFI = getFrameLowering ( MF ) ; const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; if ( ! MRI -> canReserveReg ( STI . getFramePointerReg ( ) ) ) return false ; if ( TFI -> hasReservedCallFrame ( MF ) ) return true ; return MRI -> canReserveReg ( BasePtr ) ; } </s>

True if the stack can be realigned for the target .


<s> rtx frv_split_cond_move ( rtx operands [ ] ) { rtx dest = operands [ 0 ] ; rtx test = operands [ 1 ] ; rtx cc_reg = operands [ 2 ] ; rtx src1 = operands [ 3 ] ; rtx src2 = operands [ 4 ] ; rtx cr_reg = operands [ 5 ] ; rtx ret ; machine_mode cr_mode = GET_MODE ( cr_reg ) ; start_sequence ( ) ; emit_insn ( gen_rtx_SET ( cr_reg , gen_rtx_fmt_ee ( GET_CODE ( test ) , GET_MODE ( cr_reg ) , cc_reg , const0_rtx ) ) ) ; if ( GET_CODE ( src1 ) == CONST_INT && GET_CODE ( src2 ) == CONST_INT ) { HOST_WIDE_INT value1 = INTVAL ( src1 ) ; HOST_WIDE_INT value2 = INTVAL ( src2 ) ; if ( value1 == 0 ) { emit_move_insn ( dest , src2 ) ; emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_NE ( cr_mode , cr_reg , const0_rtx ) , gen_rtx_SET ( dest , src1 ) ) ) ; } else if ( value2 == 0 ) { emit_move_insn ( dest , src1 ) ; emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_EQ ( cr_mode , cr_reg , const0_rtx ) , gen_rtx_SET ( dest , src2 ) ) ) ; } else if ( IN_RANGE ( value1 , - 2048 , 2047 ) && IN_RANGE ( value2 - value1 , - 2048 , 2047 ) ) { rtx dest_si = ( ( GET_MODE ( dest ) == SImode ) ? dest : gen_rtx_SUBREG ( SImode , dest , 0 ) ) ; emit_move_insn ( dest_si , GEN_INT ( value2 - value1 ) ) ; emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_NE ( cr_mode , cr_reg , const0_rtx ) , gen_rtx_SET ( dest_si , const0_rtx ) ) ) ; emit_insn ( gen_addsi3 ( dest_si , dest_si , src1 ) ) ; } else gcc_unreachable ( ) ; } else { if ( ! rtx_equal_p ( dest , src1 ) ) emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_NE ( cr_mode , cr_reg , const0_rtx ) , gen_rtx_SET ( dest , src1 ) ) ) ; if ( ! rtx_equal_p ( dest , src2 ) ) emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_EQ ( cr_mode , cr_reg , const0_rtx ) , gen_rtx_SET ( dest , src2 ) ) ) ; } ret = get_insns ( ) ; end_sequence ( ) ; return ret ; } </s>

Split a conditional move into constituent parts , returning a SEQUENCE containing all of the insns .


<s> const uint32_t * DLXRegisterInfo :: getCallPreservedMask ( const MachineFunction & , CallingConv :: ID ) const { return nullptr ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static bool aarch64_short_vector_p ( const_tree type , machine_mode mode ) { HOST_WIDE_INT size = - 1 ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) size = int_size_in_bytes ( type ) ; else if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT ) size = GET_MODE_SIZE ( mode ) ; return ( size == 8 || size == 16 ) ; } </s>

Return TRUE if the type , as described by TYPE and MODE , is a short vector type as described in AAPCS64 \S 4.1.2 . See the comment above aarch64_composite_type_p for the notes on MODE .


<s> BitVector HexagonRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( Hexagon :: R29 ) ; Reserved . set ( Hexagon :: R30 ) ; Reserved . set ( Hexagon :: R31 ) ; Reserved . set ( Hexagon :: VTMP ) ; Reserved . set ( Hexagon :: GELR ) ; Reserved . set ( Hexagon :: GSR ) ; Reserved . set ( Hexagon :: GOSP ) ; Reserved . set ( Hexagon :: G3 ) ; Reserved . set ( Hexagon :: SA0 ) ; Reserved . set ( Hexagon :: LC0 ) ; Reserved . set ( Hexagon :: SA1 ) ; Reserved . set ( Hexagon :: LC1 ) ; Reserved . set ( Hexagon :: P3_0 ) ; Reserved . set ( Hexagon :: USR ) ; Reserved . set ( Hexagon :: PC ) ; Reserved . set ( Hexagon :: UGP ) ; Reserved . set ( Hexagon :: GP ) ; Reserved . set ( Hexagon :: CS0 ) ; Reserved . set ( Hexagon :: CS1 ) ; Reserved . set ( Hexagon :: UPCYCLELO ) ; Reserved . set ( Hexagon :: UPCYCLEHI ) ; Reserved . set ( Hexagon :: FRAMELIMIT ) ; Reserved . set ( Hexagon :: FRAMEKEY ) ; Reserved . set ( Hexagon :: PKTCOUNTLO ) ; Reserved . set ( Hexagon :: PKTCOUNTHI ) ; Reserved . set ( Hexagon :: UTIMERLO ) ; Reserved . set ( Hexagon :: UTIMERHI ) ; Reserved . set ( Hexagon :: C8 ) ; Reserved . set ( Hexagon :: USR_OVF ) ; for ( auto Reg : Hexagon_MC :: GetVectRegRev ( ) ) Reserved . set ( Reg ) ; if ( MF . getSubtarget < HexagonSubtarget > ( ) . hasReservedR19 ( ) ) Reserved . set ( Hexagon :: R19 ) ; for ( int x = Reserved . find_first ( ) ; x >= 0 ; x = Reserved . find_next ( x ) ) markSuperRegs ( Reserved , x ) ; return Reserved ; } </s>


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Patmos Single-Path Clone (bitcode)"
;
}
</s>

getPassName - Return a nice clean name for a pass .

Patmos
"Patmos Single-Path Clone (bitcode)"


"Unrecognised AArch64 memory constraint"

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> static void remove_non_convertible_regs ( bitmap candidates ) { if ( TARGET_64BIT ) timode_remove_non_convertible_regs ( candidates ) ; else dimode_remove_non_convertible_regs ( candidates ) ; } </s>

For a given bitmap of insn UIDs scans all instruction and remove insn from CANDIDATES in case it has both convertible and not convertible definitions . All insns in a bitmap are conversion candidates according to scalar_to_vector_candidate_p . Currently it implies all insns are single_set .


<s> const char * MCS51MCExpr :: getName ( ) const { const auto & Modifier = llvm :: find_if ( ModifierNames , [ this ] ( ModifierEntry const & Mod ) { return Mod . VariantKind == Kind ; } ) ; if ( Modifier != std :: end ( ModifierNames ) ) { return Modifier -> Spelling ; } return nullptr ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> static unsigned int ATTRIBUTE_UNUSED x86_64_elf_section_type_flags ( tree decl , const char * name , int reloc ) { unsigned int flags = default_section_type_flags ( decl , name , reloc ) ; if ( ix86_in_large_data_p ( decl ) ) flags |= SECTION_LARGE ; if ( decl == NULL_TREE && ( strcmp ( name , ".ldata.rel.ro" ) == 0 || strcmp ( name , ".ldata.rel.ro.local" ) == 0 ) ) flags |= SECTION_RELRO ; if ( strcmp ( name , ".lbss" ) == 0 || startswith ( name , ".lbss." ) || startswith ( name , ".gnu.linkonce.lb." ) ) flags |= SECTION_BSS ; return flags ; } </s>

Select a set of attributes for section NAME based on the properties of DECL and whether or not RELOC indicates that DECL 's initializer might contain runtime relocations .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


"The Delta should always be zero or negative"

"Slot for EBP register must be last in order to be found!"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


Similarly for the start of the epilogue .


"Tail call for extern symbol not yet supported."

Targets should implement this to emit instructions .


<s> unsigned PatmosInstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { MachineBasicBlock :: iterator I = MBB . end ( ) ; unsigned Count = 0 ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! I -> isBranch ( ) ) break ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++ Count ; } return Count ; } </s>

Remove the branching code at the end of the specific MBB .


<s> static int function_arg_advance_32 ( CUMULATIVE_ARGS * cum , machine_mode mode , const_tree type , HOST_WIDE_INT bytes , HOST_WIDE_INT words ) { int res = 0 ; switch ( mode ) { default : break ; case BLKmode : if ( bytes < 0 ) break ; case DImode : case SImode : case HImode : case QImode : cum -> words += words ; cum -> nregs -= words ; cum -> regno += words ; if ( cum -> nregs >= 0 ) res = words ; if ( cum -> nregs <= 0 ) { cum -> nregs = 0 ; cum -> regno = 0 ; } break ; case OImode : gcc_unreachable ( ) ; case DFmode : if ( cum -> float_in_sse < 2 ) break ; case SFmode : if ( cum -> float_in_sse < 1 ) break ; case V8SFmode : case V8SImode : case V64QImode : case V32HImode : case V16SImode : case V8DImode : case V16SFmode : case V8DFmode : case V32QImode : case V16HImode : case V4DFmode : case V4DImode : case TImode : case V16QImode : case V8HImode : case V4SImode : case V2DImode : case V4SFmode : case V2DFmode : if ( ! type || ! AGGREGATE_TYPE_P ( type ) ) { cum -> sse_words += words ; cum -> sse_nregs -= 1 ; cum -> sse_regno += 1 ; if ( cum -> sse_nregs <= 0 ) { cum -> sse_nregs = 0 ; cum -> sse_regno = 0 ; } } break ; case V8QImode : case V4HImode : case V2SImode : case V2SFmode : case V1TImode : case V1DImode : if ( ! type || ! AGGREGATE_TYPE_P ( type ) ) { cum -> mmx_words += words ; cum -> mmx_nregs -= 1 ; cum -> mmx_regno += 1 ; if ( cum -> mmx_nregs <= 0 ) { cum -> mmx_nregs = 0 ; cum -> mmx_regno = 0 ; } } break ; } return res ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . ) Return a number of integer regsiters advanced over .


<s> static void ix86_override_options_after_change ( void ) { ix86_default_align ( & global_options ) ; } </s>

Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE hook .


<s>
SDValue
MandarinTargetLowering
::
withTargetFlags
(
SDValue
Op
,
unsigned
TF
,
SelectionDAG
&
DAG
)
const
{
if
(
const
GlobalAddressSDNode
*
GA
=
dyn_cast
<
GlobalAddressSDNode
>
(
Op
)
)
return
DAG
.
getTargetGlobalAddress
(
GA
->
getGlobal
(
)
,
SDLoc
(
GA
)
,
GA
->
getValueType
(
0
)
,
GA
->
getOffset
(
)
,
TF
)
;
if
(
const
ConstantPoolSDNode
*
CP
=
dyn_cast
<
ConstantPoolSDNode
>
(
Op
)
)
return
DAG
.
getTargetConstantPool
(
CP
->
getConstVal
(
)
,
CP
->
getValueType
(
0
)
,
CP
->
getAlignment
(
)
,
CP
->
getOffset
(
)
,
TF
)
;
if
(
const
BlockAddressSDNode
*
BA
=
dyn_cast
<
BlockAddressSDNode
>
(
Op
)
)
return
DAG
.
getTargetBlockAddress
(
BA
->
getBlockAddress
(
)
,
Op
.
getValueType
(
)
,
0
,
TF
)
;
if
(
const
ExternalSymbolSDNode
*
ES
=
dyn_cast
<
ExternalSymbolSDNode
>
(
Op
)
)
return
DAG
.
getTargetExternalSymbol
(
ES
->
getSymbol
(
)
,
ES
->
getValueType
(
0
)
,
TF
)
;
llvm_unreachable
(
"Unhandled address SDNode"
)
;
}
</s>


"*** BPF MachineSSA peephole pass ***\n\n"

Initialize the strategy after building the DAG for a new region .


<s> static rtx loongarch_pass_fpr_single ( machine_mode type_mode , unsigned regno , machine_mode value_mode , HOST_WIDE_INT offset ) { rtx x = gen_rtx_REG ( value_mode , regno ) ; if ( type_mode != value_mode ) { x = gen_rtx_EXPR_LIST ( VOIDmode , x , GEN_INT ( offset ) ) ; x = gen_rtx_PARALLEL ( type_mode , gen_rtvec ( 1 , x ) ) ; } return x ; } </s>

Return the representation of an argument passed or returned in an FPR when the value has mode VALUE_MODE and the type has TYPE_MODE . The two modes may be different for structures like : struct __attribute__ ( ( packed ) ) foo { float f ; } where the SFmode value `` f '' is passed in REGNO but the struct itself has mode BLKmode .


<s> MVT :: SimpleValueType AlphaTargetLowering :: getSetCCResultType ( EVT VT ) const { return MVT :: i64 ; } </s>

Return the value type to use for ISD : :SETCC .

Alpha MVT::SimpleValueType Alpha MVT::i64


<s> static bool rs6000_return_in_msb ( const_tree valtype ) { return ( DEFAULT_ABI == ABI_ELFv2 && BYTES_BIG_ENDIAN && AGGREGATE_TYPE_P ( valtype ) && rs6000_function_arg_padding ( TYPE_MODE ( valtype ) , valtype ) == PAD_UPWARD ) ; } </s>

Specify whether values returned in registers should be at the most significant end of a register . We want aggregates returned by value to match the way aggregates are passed to functions .


<s> int ix86_data_alignment ( tree type , int align , bool opt ) { int max_align_compat = MIN ( 256 , MAX_OFILE_ALIGNMENT ) ; int max_align = MIN ( ( unsigned ) ix86_tune_cost -> prefetch_block * 8 , MAX_OFILE_ALIGNMENT ) ; if ( max_align < BITS_PER_WORD ) max_align = BITS_PER_WORD ; switch ( ix86_align_data_type ) { case ix86_align_data_type_abi : opt = false ; break ; case ix86_align_data_type_compat : max_align = BITS_PER_WORD ; break ; case ix86_align_data_type_cacheline : break ; } if ( TARGET_IAMCU ) align = iamcu_alignment ( type , align ) ; if ( opt && AGGREGATE_TYPE_P ( type ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST ) { if ( wi :: geu_p ( wi :: to_wide ( TYPE_SIZE ( type ) ) , max_align_compat ) && align < max_align_compat ) align = max_align_compat ; if ( wi :: geu_p ( wi :: to_wide ( TYPE_SIZE ( type ) ) , max_align ) && align < max_align ) align = max_align ; } if ( TARGET_64BIT ) { if ( ( opt ? AGGREGATE_TYPE_P ( type ) : TREE_CODE ( type ) == ARRAY_TYPE ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && wi :: geu_p ( wi :: to_wide ( TYPE_SIZE ( type ) ) , 128 ) && align < 128 ) return 128 ; } if ( ! opt ) return align ; if ( TREE_CODE ( type ) == ARRAY_TYPE ) { if ( TYPE_MODE ( TREE_TYPE ( type ) ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( type ) ) ) && align < 128 ) return 128 ; } else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) { if ( TYPE_MODE ( type ) == DCmode && align < 64 ) return 64 ; if ( ( TYPE_MODE ( type ) == XCmode || TYPE_MODE ( type ) == TCmode ) && align < 128 ) return 128 ; } else if ( ( TREE_CODE ( type ) == RECORD_TYPE || TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == QUAL_UNION_TYPE ) && TYPE_FIELDS ( type ) ) { if ( DECL_MODE ( TYPE_FIELDS ( type ) ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( DECL_MODE ( TYPE_FIELDS ( type ) ) ) && align < 128 ) return 128 ; } else if ( TREE_CODE ( type ) == REAL_TYPE || TREE_CODE ( type ) == VECTOR_TYPE || TREE_CODE ( type ) == INTEGER_TYPE ) { if ( TYPE_MODE ( type ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( TYPE_MODE ( type ) ) && align < 128 ) return 128 ; } return align ; } </s>

Compute the alignment for a static variable . TYPE is the data type , and ALIGN is the alignment that the object would ordinarily have . The value of this function is used instead of that alignment to align the object .


<s> int memory_address_length ( rtx addr , bool lea ) { struct ix86_address parts ; rtx base , index , disp ; int len ; int ok ; if ( GET_CODE ( addr ) == PRE_DEC || GET_CODE ( addr ) == POST_INC || GET_CODE ( addr ) == PRE_MODIFY || GET_CODE ( addr ) == POST_MODIFY ) return 0 ; ok = ix86_decompose_address ( addr , & parts ) ; gcc_assert ( ok ) ; len = ( parts . seg == ADDR_SPACE_GENERIC ) ? 0 : 1 ; if ( TARGET_64BIT && ! lea && ( SImode_address_operand ( addr , VOIDmode ) || ( parts . base && GET_MODE ( parts . base ) == SImode ) || ( parts . index && GET_MODE ( parts . index ) == SImode ) ) ) len ++ ; base = parts . base ; index = parts . index ; disp = parts . disp ; if ( base && SUBREG_P ( base ) ) base = SUBREG_REG ( base ) ; if ( index && SUBREG_P ( index ) ) index = SUBREG_REG ( index ) ; gcc_assert ( base == NULL_RTX || REG_P ( base ) ) ; gcc_assert ( index == NULL_RTX || REG_P ( index ) ) ; if ( base && ! index && ! disp ) { if ( base == arg_pointer_rtx || base == frame_pointer_rtx || REGNO ( base ) == SP_REG || REGNO ( base ) == BP_REG || REGNO ( base ) == R12_REG || REGNO ( base ) == R13_REG ) len ++ ; } else if ( disp && ! base && ! index ) { len += 4 ; if ( ! ix86_rip_relative_addr_p ( & parts ) ) len ++ ; } else { if ( disp ) { if ( base && satisfies_constraint_K ( disp ) ) len += 1 ; else len += 4 ; } else if ( base && ( REGNO ( base ) == BP_REG || REGNO ( base ) == R13_REG ) ) len ++ ; if ( index || base == arg_pointer_rtx || base == frame_pointer_rtx || ( base && ( REGNO ( base ) == SP_REG || REGNO ( base ) == R12_REG ) ) ) len ++ ; } return len ; } </s>

Calculate the length of the memory address in the instruction encoding . Does not include the one-byte modrm , opcode , or prefix .


<s> int pru_initial_elimination_offset ( int from , int to ) { int offset ; switch ( from ) { case FRAME_POINTER_REGNUM : offset = cfun -> machine -> out_args_size ; break ; case ARG_POINTER_REGNUM : offset = cfun -> machine -> total_size ; offset -= crtl -> args . pretend_args_size ; break ; default : gcc_unreachable ( ) ; } if ( to == HARD_FRAME_POINTER_REGNUM ) offset -= cfun -> machine -> total_size - crtl -> args . pretend_args_size ; return offset ; } </s>

Implement INITIAL_ELIMINATION_OFFSET macro .


<s> const char * out_tstsi ( rtx insn , int * l ) { if ( compare_sign_p ( insn ) ) { if ( l ) * l = 1 ; return AS1 ( tst , % D0 ) ; } if ( test_hard_reg_class ( ADDW_REGS , SET_SRC ( PATTERN ( insn ) ) ) ) { if ( l ) * l = 3 ; return ( AS2 ( sbiw , % A0 , 0 ) CR_TAB AS2 ( cpc , % C0 , __zero_reg__ ) CR_TAB AS2 ( cpc , % D0 , __zero_reg__ ) ) ; } if ( l ) * l = 4 ; return ( AS2 ( cp , % A0 , __zero_reg__ ) CR_TAB AS2 ( cpc , % B0 , __zero_reg__ ) CR_TAB AS2 ( cpc , % C0 , __zero_reg__ ) CR_TAB AS2 ( cpc , % D0 , __zero_reg__ ) ) ; } </s>


<s> bool ix86_operands_ok_for_move_multiple ( rtx * operands , bool load , enum machine_mode mode ) { HOST_WIDE_INT offval_1 , offval_2 , msize ; rtx mem_1 , mem_2 , reg_1 , reg_2 , base_1 , base_2 , offset_1 , offset_2 ; if ( load ) { mem_1 = operands [ 1 ] ; mem_2 = operands [ 3 ] ; reg_1 = operands [ 0 ] ; reg_2 = operands [ 2 ] ; } else { mem_1 = operands [ 0 ] ; mem_2 = operands [ 2 ] ; reg_1 = operands [ 1 ] ; reg_2 = operands [ 3 ] ; } gcc_assert ( REG_P ( reg_1 ) && REG_P ( reg_2 ) ) ; if ( REGNO ( reg_1 ) != REGNO ( reg_2 ) ) return false ; if ( ! extract_base_offset_in_addr ( mem_1 , & base_1 , & offset_1 ) ) return false ; if ( ! extract_base_offset_in_addr ( mem_2 , & base_2 , & offset_2 ) ) return false ; if ( ! rtx_equal_p ( base_1 , base_2 ) ) return false ; offval_1 = INTVAL ( offset_1 ) ; offval_2 = INTVAL ( offset_2 ) ; msize = GET_MODE_SIZE ( mode ) ; if ( offval_1 + msize != offval_2 ) return false ; return true ; } </s>

Given OPERANDS of consecutive load/store , check if we can merge them into move multiple . LOAD is true if they are load instructions . MODE is the mode of memory operands .


<s> static void mep_asm_named_section ( const char * name , unsigned int flags , tree decl ATTRIBUTE_UNUSED ) { char flagchars [ 8 ] , * f = flagchars ; const char * type ; if ( ! ( flags & SECTION_DEBUG ) ) * f ++ = 'a' ; if ( flags & SECTION_WRITE ) * f ++ = 'w' ; if ( flags & SECTION_CODE ) * f ++ = 'x' ; if ( flags & SECTION_SMALL ) * f ++ = 's' ; if ( flags & SECTION_MEP_VLIW ) * f ++ = 'v' ; * f = '\0' ; if ( flags & SECTION_BSS ) type = "nobits" ; else type = "progbits" ; fprintf ( asm_out_file , "\t.section\t%s,\"%s\",@%s\n" , name , flagchars , type ) ; if ( flags & SECTION_CODE ) fputs ( ( flags & SECTION_MEP_VLIW ? "\t.vliw\n" : "\t.core\n" ) , asm_out_file ) ; } </s>

Switch to an arbitrary section NAME with attributes as specified by FLAGS . ALIGN specifies any known alignment requirements for the section ; 0 if the default should be used . Differs from the standard ELF version only in support of VLIW mode .


<s> static int frv_clear_registers_used ( rtx * ptr , void * data ) { if ( GET_CODE ( * ptr ) == REG ) { int regno = REGNO ( * ptr ) ; HARD_REG_SET * p_regs = ( HARD_REG_SET * ) data ; if ( regno < FIRST_PSEUDO_REGISTER ) { int reg_max = regno + HARD_REGNO_NREGS ( regno , GET_MODE ( * ptr ) ) ; while ( regno < reg_max ) { CLEAR_HARD_REG_BIT ( * p_regs , regno ) ; regno ++ ; } } } return 0 ; } </s>

An internal function called by for_each_rtx to clear in a hard_reg set each register used in an insn .


<s> MCObjectWriter * CJGAsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { return createCJGELFObjectWriter ( OS , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> bool mem_operand_ds_form ( rtx op , machine_mode mode ) { unsigned HOST_WIDE_INT offset ; int extra ; rtx addr = XEXP ( op , 0 ) ; if ( address_is_prefixed ( addr , mode , NON_PREFIXED_DS ) ) return true ; if ( ! offsettable_address_p ( false , mode , addr ) ) return false ; op = address_offset ( addr ) ; if ( op == NULL_RTX ) return true ; offset = INTVAL ( op ) ; if ( ( offset & 3 ) != 0 ) return false ; extra = GET_MODE_SIZE ( mode ) - UNITS_PER_WORD ; if ( extra < 0 ) extra = 0 ; if ( GET_CODE ( addr ) == LO_SUM ) offset = sext_hwi ( offset , 16 ) ; return SIGNED_16BIT_OFFSET_EXTRA_P ( offset , extra ) ; } </s>

As above , but for DS-FORM VSX insns . Unlike mem_operand_gpr , enforce an offset divisible by 4 even for 32-bit .


<s> bool PPCFrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return true ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! EnablePEVectorSpills || MFI . hasCalls ( ) || ! Subtarget . hasP9Vector ( ) ) return false ; BitVector BVAllocatable = TRI -> getAllocatableSet ( MF ) ; BitVector BVCalleeSaved ( TRI -> getNumRegs ( ) ) ; const PPCRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( & MF ) ; for ( unsigned i = 0 ; CSRegs [ i ] ; ++ i ) BVCalleeSaved . set ( CSRegs [ i ] ) ; for ( unsigned Reg : BVAllocatable . set_bits ( ) ) { if ( BVCalleeSaved [ Reg ] || ! PPC :: VSRCRegClass . contains ( Reg ) || MF . getRegInfo ( ) . isPhysRegUsed ( Reg ) ) BVAllocatable . reset ( Reg ) ; } bool AllSpilledToReg = true ; unsigned LastVSRUsedForSpill = 0 ; for ( auto & CS : CSI ) { if ( BVAllocatable . none ( ) ) return false ; Register Reg = CS . getReg ( ) ; if ( ! PPC :: G8RCRegClass . contains ( Reg ) ) { AllSpilledToReg = false ; continue ; } if ( LastVSRUsedForSpill != 0 ) { CS . setDstReg ( LastVSRUsedForSpill ) ; BVAllocatable . reset ( LastVSRUsedForSpill ) ; LastVSRUsedForSpill = 0 ; continue ; } unsigned VolatileVFReg = BVAllocatable . find_first ( ) ; if ( VolatileVFReg < BVAllocatable . size ( ) ) { CS . setDstReg ( VolatileVFReg ) ; LastVSRUsedForSpill = VolatileVFReg ; } else { AllSpilledToReg = false ; } } return AllSpilledToReg ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> static void frv_frame_access_multi ( frv_frame_accessor_t * accessor , frv_stack_t * info , int reg_set ) { frv_stack_regs_t * regs_info ; int regno ; regs_info = & info -> regs [ reg_set ] ; for ( regno = regs_info -> first ; regno <= regs_info -> last ; regno ++ ) if ( info -> save_p [ regno ] ) frv_frame_access ( accessor , info -> save_p [ regno ] == REG_SAVE_2WORDS ? gen_rtx_REG ( DImode , regno ) : gen_rtx_REG ( SImode , regno ) , info -> reg_offset [ regno ] ) ; } </s>

A function that uses frv_frame_access to transfer a group of registers to or from the stack . ACCESSOR is passed directly to frv_frame_access , INFO is the stack information generated by frv_stack_info , and REG_SET is the number of the register set to transfer .


<s> static void xtensa_function_arg_advance ( cumulative_args_t cum , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { int words , max ; int * arg_words ; arg_words = & get_cumulative_args ( cum ) -> arg_words ; max = MAX_ARGS_IN_REGISTERS ; words = ( ( ( mode != BLKmode ) ? ( int ) GET_MODE_SIZE ( mode ) : int_size_in_bytes ( type ) ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; if ( * arg_words < max && ( targetm . calls . must_pass_in_stack ( mode , type ) || * arg_words + words > max ) ) * arg_words = max ; * arg_words += words ; } </s>

Advance the argument to the next argument position .


<s> bool ARMPassConfig :: addPreISel ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createARMParallelDSPPass ( ) ) ; if ( ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE ) { bool OnlyOptimizeForSize = ( TM -> getOptLevel ( ) < CodeGenOpt :: Aggressive ) && ( EnableGlobalMerge == cl :: BOU_UNSET ) ; bool MergeExternalByDefault = ! TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ; addPass ( createGlobalMergePass ( TM , 127 , OnlyOptimizeForSize , MergeExternalByDefault ) ) ; } return false ; } </s>


<s> bool processBlock ( MachineFunction & MF , MachineBasicBlock & MBB ) { bool Changed = false ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; I ++ ) { for ( unsigned j = 0 ; j < I -> getNumOperands ( ) ; j ++ ) { const Constant * c ; switch ( I -> getOperand ( j ) . getType ( ) ) { case MachineOperand :: MO_Immediate : c = ConstantInt :: get ( Type :: getInt32Ty ( * LCtx ) , ( int32_t ) I -> getOperand ( j ) . getImm ( ) ) ; break ; case MachineOperand :: MO_FPImmediate : c = I -> getOperand ( j ) . getFPImm ( ) ; break ; default : continue ; } unsigned int idx = MCP -> getConstantPoolIndex ( c , 4 ) ; I -> getOperand ( j ) . ChangeToImmediate ( idx ) ; } } return Changed ; } </s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s> static unsigned findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const X86RegisterInfo * TRI , bool Is64Bit ) { const MachineFunction * MF = MBB . getParent ( ) ; const Function * F = MF -> getFunction ( ) ; if ( ! F || MF -> getMMI ( ) . callsEHReturn ( ) ) return 0 ; const TargetRegisterClass & AvailableRegs = * TRI -> getGPRsForTailCall ( * MF ) ; if ( MBBI == MBB . end ( ) ) return 0 ; switch ( MBBI -> getOpcode ( ) ) { default : return 0 ; case TargetOpcode :: PATCHABLE_RET : case X86 :: RET : case X86 :: RETL : case X86 :: RETQ : case X86 :: RETIL : case X86 :: RETIQ : case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: TCRETURNmi64 : case X86 :: EH_RETURN : case X86 :: EH_RETURN64 : { SmallSet < uint16_t , 8 > Uses ; for ( unsigned i = 0 , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } for ( auto CS : AvailableRegs ) if ( ! Uses . count ( CS ) && CS != X86 :: RIP ) return CS ; } } return 0 ; } </s>

findDeadCallerSavedReg - Return a caller-saved register that is n't live when it reaches the `` return '' instruction .


<s> int pa_fmpysuboperands ( rtx * operands ) { machine_mode mode = GET_MODE ( operands [ 0 ] ) ; if ( mode != SFmode && mode != DFmode ) return 0 ; if ( ! ( mode == GET_MODE ( operands [ 1 ] ) && mode == GET_MODE ( operands [ 2 ] ) && mode == GET_MODE ( operands [ 3 ] ) && mode == GET_MODE ( operands [ 4 ] ) && mode == GET_MODE ( operands [ 5 ] ) ) ) return 0 ; if ( ! ( GET_CODE ( operands [ 1 ] ) == REG && GET_CODE ( operands [ 2 ] ) == REG && GET_CODE ( operands [ 3 ] ) == REG && GET_CODE ( operands [ 4 ] ) == REG && GET_CODE ( operands [ 5 ] ) == REG ) ) return 0 ; if ( ! rtx_equal_p ( operands [ 3 ] , operands [ 4 ] ) ) return 0 ; if ( rtx_equal_p ( operands [ 5 ] , operands [ 0 ] ) ) return 0 ; if ( rtx_equal_p ( operands [ 3 ] , operands [ 0 ] ) || rtx_equal_p ( operands [ 3 ] , operands [ 1 ] ) || rtx_equal_p ( operands [ 3 ] , operands [ 2 ] ) ) return 0 ; if ( mode == SFmode && ( REGNO_REG_CLASS ( REGNO ( operands [ 0 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 1 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 2 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 3 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 4 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 5 ] ) ) != FPUPPER_REGS ) ) return 0 ; return 1 ; } </s>

Returns 1 if the 6 operands specified in OPERANDS are suitable for use in fmpysub instructions .


<s> static int riscv_register_move_cost ( machine_mode mode , reg_class_t from , reg_class_t to ) { return riscv_secondary_memory_needed ( mode , from , to ) ? 8 : 2 ; } </s>


"instruction use requires an option to be enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> static bool riscv_legitimate_constant_p ( enum machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { return riscv_const_insns ( x ) > 0 ; } </s>


<s> static void maybe_make_core_relo ( tree expr , enum btf_core_reloc_kind kind ) { if ( ! TARGET_BPF_CORE ) return ; auto_vec < unsigned int , 16 > accessors ; tree container = bpf_core_compute ( expr , & accessors ) ; if ( accessors . length ( ) < 1 ) return ; accessors . reverse ( ) ; rtx_code_label * label = gen_label_rtx ( ) ; LABEL_PRESERVE_P ( label ) = 1 ; emit_label ( label ) ; const char * section_name ; if ( current_function_decl && DECL_SECTION_NAME ( current_function_decl ) ) section_name = DECL_SECTION_NAME ( current_function_decl ) ; else section_name = ".text" ; bpf_core_reloc_add ( TREE_TYPE ( container ) , section_name , & accessors , label , kind ) ; } </s>

BPF Compile Once - Run Everywhere ( CO-RE ) support . Construct a CO-RE relocation record for EXPR of kind KIND to be emitted in the .BTF.ext section . Does nothing if we are not targetting BPF CO-RE , or if the constructed relocation would be a no-op .


<s>
SDValue
VideoCore4TargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
isVarArg
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> static bool s390_function_arg_float ( machine_mode mode , const_tree type ) { int size = s390_function_arg_size ( mode , type ) ; if ( size > 8 ) return false ; if ( TARGET_SOFT_FLOAT ) return false ; if ( ! type ) return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode ; while ( TREE_CODE ( type ) == RECORD_TYPE ) { tree field , single = NULL_TREE ; for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( single == NULL_TREE ) single = TREE_TYPE ( field ) ; else return false ; } if ( single == NULL_TREE ) return false ; else type = single ; } return TREE_CODE ( type ) == REAL_TYPE ; } </s>

Return true if a function argument of type TYPE and mode MODE is to be passed in a floating-point register , if available .


"Can only put epilog before 'retl' instruction!"


<s> static rtx rs6000_adjust_atomic_subword ( rtx orig_mem , rtx * pshift , rtx * pmask ) { rtx addr , align , shift , mask , mem ; HOST_WIDE_INT shift_mask ; machine_mode mode = GET_MODE ( orig_mem ) ; shift_mask = ( mode == QImode ? 0x18 : 0x10 ) ; addr = XEXP ( orig_mem , 0 ) ; addr = force_reg ( GET_MODE ( addr ) , addr ) ; align = expand_simple_binop ( Pmode , AND , addr , GEN_INT ( - 4 ) , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; mem = gen_rtx_MEM ( SImode , align ) ; MEM_VOLATILE_P ( mem ) = MEM_VOLATILE_P ( orig_mem ) ; if ( MEM_ALIAS_SET ( orig_mem ) == ALIAS_SET_MEMORY_BARRIER ) set_mem_alias_set ( mem , ALIAS_SET_MEMORY_BARRIER ) ; shift = gen_reg_rtx ( SImode ) ; addr = gen_lowpart ( SImode , addr ) ; emit_insn ( gen_rlwinm ( shift , addr , GEN_INT ( 3 ) , GEN_INT ( shift_mask ) ) ) ; if ( BYTES_BIG_ENDIAN ) shift = expand_simple_binop ( SImode , XOR , shift , GEN_INT ( shift_mask ) , shift , 1 , OPTAB_LIB_WIDEN ) ; * pshift = shift ; mask = expand_simple_binop ( SImode , ASHIFT , GEN_INT ( GET_MODE_MASK ( mode ) ) , shift , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; * pmask = mask ; return mem ; } </s>

A subroutine of the various atomic expanders . For sub-word operations , we must adjust things to operate on SImode . Given the original MEM , return a new aligned memory . Also build and return the quantities by which to shift and mask .


<s> static void riscv_legitimize_const_move ( enum machine_mode mode , rtx dest , rtx src ) { rtx base , offset ; if ( splittable_const_int_operand ( src , mode ) ) { riscv_move_integer ( dest , dest , INTVAL ( src ) ) ; return ; } if ( riscv_split_symbol ( dest , src , MAX_MACHINE_MODE , & src ) ) { riscv_emit_set ( dest , src ) ; return ; } if ( riscv_tls_symbol_p ( src ) ) { riscv_emit_move ( dest , riscv_legitimize_tls_address ( src ) ) ; return ; } split_const ( src , & base , & offset ) ; if ( offset != const0_rtx && ( targetm . cannot_force_const_mem ( mode , src ) || can_create_pseudo_p ( ) ) ) { base = riscv_force_temporary ( dest , base ) ; riscv_emit_move ( dest , riscv_add_offset ( NULL , base , INTVAL ( offset ) ) ) ; return ; } src = force_const_mem ( mode , src ) ; riscv_split_symbol ( dest , XEXP ( src , 0 ) , mode , & XEXP ( src , 0 ) ) ; riscv_emit_move ( dest , src ) ; } </s>

Subroutine of riscv_legitimize_move . Move constant SRC into register DEST given that SRC satisfies immediate_operand but does n't satisfy move_operand .


<s> const char * XCoreTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( XCoreISD :: NodeType ) Opcode ) { case XCoreISD :: FIRST_NUMBER : break ; case XCoreISD :: BL : return "XCoreISD::BL" ; case XCoreISD :: PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper" ; case XCoreISD :: DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper" ; case XCoreISD :: CPRelativeWrapper : return "XCoreISD::CPRelativeWrapper" ; case XCoreISD :: LDWSP : return "XCoreISD::LDWSP" ; case XCoreISD :: STWSP : return "XCoreISD::STWSP" ; case XCoreISD :: RETSP : return "XCoreISD::RETSP" ; case XCoreISD :: LADD : return "XCoreISD::LADD" ; case XCoreISD :: LSUB : return "XCoreISD::LSUB" ; case XCoreISD :: LMUL : return "XCoreISD::LMUL" ; case XCoreISD :: MACCU : return "XCoreISD::MACCU" ; case XCoreISD :: MACCS : return "XCoreISD::MACCS" ; case XCoreISD :: CRC8 : return "XCoreISD::CRC8" ; case XCoreISD :: BR_JT : return "XCoreISD::BR_JT" ; case XCoreISD :: BR_JT32 : return "XCoreISD::BR_JT32" ; case XCoreISD :: FRAME_TO_ARGS_OFFSET : return "XCoreISD::FRAME_TO_ARGS_OFFSET" ; case XCoreISD :: EH_RETURN : return "XCoreISD::EH_RETURN" ; case XCoreISD :: MEMBARRIER : return "XCoreISD::MEMBARRIER" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

XCore XCore XCoreISD::NodeType XCoreISD::FIRST_NUMBER XCoreISD::BL "XCoreISD::BL" XCoreISD::PCRelativeWrapper "XCoreISD::PCRelativeWrapper" XCoreISD::DPRelativeWrapper "XCoreISD::DPRelativeWrapper" XCoreISD::CPRelativeWrapper "XCoreISD::CPRelativeWrapper" XCoreISD::LDWSP "XCoreISD::LDWSP" XCoreISD::STWSP "XCoreISD::STWSP" XCoreISD::RETSP "XCoreISD::RETSP" XCoreISD::LADD "XCoreISD::LADD" XCoreISD::LSUB "XCoreISD::LSUB" XCoreISD::LMUL "XCoreISD::LMUL" XCoreISD::MACCU "XCoreISD::MACCU" XCoreISD::MACCS "XCoreISD::MACCS" XCoreISD::CRC8 "XCoreISD::CRC8" XCoreISD::BR_JT "XCoreISD::BR_JT" XCoreISD::BR_JT32 "XCoreISD::BR_JT32" XCoreISD::FRAME_TO_ARGS_OFFSET "XCoreISD::FRAME_TO_ARGS_OFFSET" XCoreISD::EH_RETURN "XCoreISD::EH_RETURN" XCoreISD::MEMBARRIER "XCoreISD::MEMBARRIER"


"********** Exception Info Calculation **********\n"

runOnMachineFunction - Emit the function body .


<s> MachineInstr * Thumb2InstrInfo :: commuteInstructionImpl ( MachineInstr & MI , bool NewMI , unsigned OpIdx1 , unsigned OpIdx2 ) const { switch ( MI . getOpcode ( ) ) { case ARM :: MVE_VMAXNMAf16 : case ARM :: MVE_VMAXNMAf32 : case ARM :: MVE_VMINNMAf16 : case ARM :: MVE_VMINNMAf32 : if ( getVPTInstrPredicate ( MI ) != ARMVCC :: None ) return nullptr ; } return ARMBaseInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1 , OpIdx2 ) ; } </s>

Commutes the operands in the given instruction by changing the operands order and/or changing the instruction 's opcode and/or the immediate value operand .


<s> std :: unique_ptr < Z80Operand > Z80Operand :: CreateReg ( unsigned RegNo , SMLoc Start , SMLoc End ) { auto newOperand = std :: make_unique < Z80Operand > ( k_Register , Start , End ) ; newOperand -> Reg . RegNumber = RegNo ; return newOperand ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s>
static
uint16_t
name
(
struct
InternalInstruction
*
insn
,
\
OperandType
type
,
\
uint8_t
index
,
\
uint8_t
*
valid
)
{
\
*
valid
=
1
;
\
switch
(
type
)
{
\
default
:
\
debug
(
"Unhandled register type"
)
;
\
*
valid
=
0
;
\
return
0
;
\
case
TYPE_Rv
:
\
return
base
+
index
;
\
case
TYPE_R8
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
if
(
insn
->
rexPrefix
&&
\
index
>=
4
&&
index
<=
7
)
{
\
return
prefix
##
_SPL
+
(
index
4
)
;
\
}
else
{
\
return
prefix
##
_AL
+
index
;
\
}
\
case
TYPE_R16
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
return
prefix
##
_AX
+
index
;
\
case
TYPE_R32
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
return
prefix
##
_EAX
+
index
;
\
case
TYPE_R64
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
return
prefix
##
_RAX
+
index
;
\
case
TYPE_ZMM
:
\
return
prefix
##
_ZMM0
+
index
;
\
case
TYPE_YMM
:
\
return
prefix
##
_YMM0
+
index
;
\
case
TYPE_XMM
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_VK
:
\
index
&=
0xf
;
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_K0
+
index
;
\
case
TYPE_VK_PAIR
:
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_K0_K1
+
(
index
/
2
)
;
\
case
TYPE_MM64
:
\
return
prefix
##
_MM0
+
(
index
&
0x7
)
;
\
case
TYPE_SEGMENTREG
:
\
if
(
(
index
&
7
)
>
5
)
\
*
valid
=
0
;
\
return
prefix
##
_ES
+
(
index
&
7
)
;
\
case
TYPE_DEBUGREG
:
\
return
prefix
##
_DR0
+
index
;
\
case
TYPE_CONTROLREG
:
\
return
prefix
##
_CR0
+
index
;
\
case
TYPE_BNDR
:
\
if
(
index
>
3
)
\
*
valid
=
0
;
\
return
prefix
##
_BND0
+
index
;
\
case
TYPE_MVSIBX
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_MVSIBY
:
\
return
prefix
##
_YMM0
+
index
;
\
case
TYPE_MVSIBZ
:
\
return
prefix
##
_ZMM0
+
index
;
\
}
\
}
</s>

Gets the name of the pass we are mixed into .


"%<-fexcess-precision=16%> is not supported on this target"

Implement TARGET_C_EXCESS_PRECISION . Set the value of FLT_EVAL_METHOD in float.h . When using 68040 fp instructions , we get proper intermediate rounding , otherwise we get extended precision results .


<s> void TPCInstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , unsigned SubIdx , const MachineInstr & Orig , const TargetRegisterInfo & TRI ) const { MachineInstr * DefMI = MBB . getParent ( ) -> CloneMachineInstr ( & Orig ) ; DefMI -> substituteRegister ( DefMI -> getOperand ( 0 ) . getReg ( ) , DestReg , SubIdx , TRI ) ; MBB . insert ( MI , DefMI ) ; MachineInstr & Instr = * -- MI ; MachineOperand & MO = Instr . getOperand ( 0 ) ; assert ( MO . isReg ( ) && MO . isDef ( ) ) ; if ( ! MO . getReg ( ) . isVirtual ( ) ) return ; if ( MO . isTied ( ) ) { const MCInstrDesc & MCI = Instr . getDesc ( ) ; if ( MCI . getNumOperands ( ) < 4 ) return ; MachineOperand & IncomeMO = Instr . getOperand ( MCI . getNumOperands ( ) - 3 ) ; if ( ! IncomeMO . isTied ( ) ) return ; if ( IncomeMO . getSubReg ( ) ) { IncomeMO . setSubReg ( SubIdx ) ; } } } </s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s>
virtual
StringRef
getPassName
(
)
const
{
return
StringRef
(
"LEG Assembly Printer"
)
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool AArch64TTIImpl :: getTgtMemIntrinsic ( IntrinsicInst * Inst , MemIntrinsicInfo & Info ) { switch ( Inst -> getIntrinsicID ( ) ) { default : break ; case Intrinsic :: aarch64_neon_ld2 : case Intrinsic :: aarch64_neon_ld3 : case Intrinsic :: aarch64_neon_ld4 : Info . ReadMem = true ; Info . WriteMem = false ; Info . PtrVal = Inst -> getArgOperand ( 0 ) ; break ; case Intrinsic :: aarch64_neon_st2 : case Intrinsic :: aarch64_neon_st3 : case Intrinsic :: aarch64_neon_st4 : Info . ReadMem = false ; Info . WriteMem = true ; Info . PtrVal = Inst -> getArgOperand ( Inst -> getNumArgOperands ( ) - 1 ) ; break ; } switch ( Inst -> getIntrinsicID ( ) ) { default : return false ; case Intrinsic :: aarch64_neon_ld2 : case Intrinsic :: aarch64_neon_st2 : Info . MatchingId = VECTOR_LDST_TWO_ELEMENTS ; break ; case Intrinsic :: aarch64_neon_ld3 : case Intrinsic :: aarch64_neon_st3 : Info . MatchingId = VECTOR_LDST_THREE_ELEMENTS ; break ; case Intrinsic :: aarch64_neon_ld4 : case Intrinsic :: aarch64_neon_st4 : Info . MatchingId = VECTOR_LDST_FOUR_ELEMENTS ; break ; } return true ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> const char * XtensaTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case XtensaISD :: RET_FLAG : return "RET_FLAG" ; case XtensaISD :: ENTRY_FLAG : return "ENTRY_FLAG" ; default : return nullptr ; } } </s>


<s> unsigned RISCVInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : { if ( MI . getParent ( ) && MI . getParent ( ) -> getParent ( ) ) { const auto MF = MI . getMF ( ) ; const auto & TM = static_cast < const RISCVTargetMachine & > ( MF -> getTarget ( ) ) ; const MCRegisterInfo & MRI = * TM . getMCRegisterInfo ( ) ; const MCSubtargetInfo & STI = * TM . getMCSubtargetInfo ( ) ; const RISCVSubtarget & ST = MF -> getSubtarget < RISCVSubtarget > ( ) ; if ( isCompressibleInst ( MI , & ST , MRI , STI ) ) return 2 ; } return get ( Opcode ) . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return 0 ; case RISCV :: PseudoCALLReg : case RISCV :: PseudoCALL : case RISCV :: PseudoTAIL : case RISCV :: PseudoLLA : case RISCV :: PseudoLA : case RISCV :: PseudoLA_TLS_IE : case RISCV :: PseudoLA_TLS_GD : return 8 ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const auto & TM = static_cast < const RISCVTargetMachine & > ( MF . getTarget ( ) ) ; return getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> const UPTRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static int pa_issue_rate ( void ) { switch ( pa_cpu ) { case PROCESSOR_700 : return 1 ; case PROCESSOR_7100 : return 2 ; case PROCESSOR_7100LC : return 2 ; case PROCESSOR_7200 : return 2 ; case PROCESSOR_7300 : return 2 ; case PROCESSOR_8000 : return 4 ; default : gcc_unreachable ( ) ; } } </s>

The 700 can only issue a single insn at a time . The 7XXX processors can issue two insns at a time . The 8000 can issue 4 insns at a time .


<s> bool M88kMCAsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> bool SVEIntrinsicOpts :: runOnModule ( Module & M ) { bool Changed = false ; SmallSetVector < Function * , 4 > Functions ; for ( auto & F : M . getFunctionList ( ) ) { if ( ! F . isDeclaration ( ) ) continue ; switch ( F . getIntrinsicID ( ) ) { case Intrinsic :: aarch64_sve_convert_from_svbool : case Intrinsic :: aarch64_sve_ptest_any : case Intrinsic :: aarch64_sve_ptest_first : case Intrinsic :: aarch64_sve_ptest_last : for ( User * U : F . users ( ) ) Functions . insert ( cast < Instruction > ( U ) -> getFunction ( ) ) ; break ; default : break ; } } if ( ! Functions . empty ( ) ) Changed |= optimizeFunctions ( Functions ) ; return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> static void mips_set_current_function ( tree fndecl ) { mips_set_compression_mode ( mips_get_compress_mode ( fndecl ) ) ; } </s>

Implement TARGET_SET_CURRENT_FUNCTION . Decide whether the current function should use the MIPS16 or microMIPS ISA and switch modes accordingly .


<s> bool isToken ( ) const override { return Kind == k_Token ; } </s>


<s> static void frv_add_insn_to_packet ( rtx_insn * insn ) { struct frv_packet_group * packet_group ; packet_group = & frv_packet . groups [ frv_unit_groups [ frv_insn_unit ( insn ) ] ] ; packet_group -> insns [ packet_group -> num_insns ++ ] = insn ; frv_packet . insns [ frv_packet . num_insns ++ ] = insn ; frv_registers_update ( PATTERN ( insn ) ) ; } </s>

Add instruction INSN to the current packet .


<s>
CCAssignFn
*
ARMFastISel
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
Return
,
bool
isVarArg
)
{
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
if
(
Subtarget
->
hasVFP2
(
)
&&
!
isVarArg
)
{
if
(
!
Subtarget
->
isAAPCS_ABI
(
)
)
return
(
Return
RetFastCC_ARM_APCS
:
FastCC_ARM_APCS
)
;
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
}
case
CallingConv
::
C
:
if
(
Subtarget
->
isAAPCS_ABI
(
)
)
{
if
(
Subtarget
->
hasVFP2
(
)
&&
TM
.
Options
.
FloatABIType
==
FloatABI
::
Hard
&&
!
isVarArg
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
else
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
}
else
{
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
}
case
CallingConv
::
ARM_AAPCS_VFP
:
if
(
!
isVarArg
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
case
CallingConv
::
ARM_AAPCS
:
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
case
CallingConv
::
ARM_APCS
:
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
case
CallingConv
::
GHC
:
if
(
Return
)
llvm_unreachable
(
"Can't return in GHC call convention"
)
;
else
return
CC_ARM_APCS_GHC
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .

ARM
ARM
"Unsupported calling convention"
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
"Can't return in GHC call convention"
ARM


<s> rtx_insn * s390_emit_jump ( rtx target , rtx cond ) { rtx insn ; target = gen_rtx_LABEL_REF ( VOIDmode , target ) ; if ( cond ) target = gen_rtx_IF_THEN_ELSE ( VOIDmode , cond , target , pc_rtx ) ; insn = gen_rtx_SET ( pc_rtx , target ) ; return emit_jump_insn ( insn ) ; } </s>

Emit a jump instruction to TARGET . If COND is NULL_RTX , emit an unconditional jump , else a conditional jump under condition COND .


<s> BitVector R600RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const R600Subtarget & ST = MF . getSubtarget < R600Subtarget > ( ) ; const R600InstrInfo * TII = ST . getInstrInfo ( ) ; Reserved . set ( AMDGPU :: ZERO ) ; Reserved . set ( AMDGPU :: HALF ) ; Reserved . set ( AMDGPU :: ONE ) ; Reserved . set ( AMDGPU :: ONE_INT ) ; Reserved . set ( AMDGPU :: NEG_HALF ) ; Reserved . set ( AMDGPU :: NEG_ONE ) ; Reserved . set ( AMDGPU :: PV_X ) ; Reserved . set ( AMDGPU :: ALU_LITERAL_X ) ; Reserved . set ( AMDGPU :: ALU_CONST ) ; Reserved . set ( AMDGPU :: PREDICATE_BIT ) ; Reserved . set ( AMDGPU :: PRED_SEL_OFF ) ; Reserved . set ( AMDGPU :: PRED_SEL_ZERO ) ; Reserved . set ( AMDGPU :: PRED_SEL_ONE ) ; Reserved . set ( AMDGPU :: INDIRECT_BASE_ADDR ) ; for ( TargetRegisterClass :: iterator I = AMDGPU :: R600_AddrRegClass . begin ( ) , E = AMDGPU :: R600_AddrRegClass . end ( ) ; I != E ; ++ I ) { Reserved . set ( * I ) ; } TII -> reserveIndirectRegisters ( Reserved , MF ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool Mips16InstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock & MBB = * MI -> getParent ( ) ; switch ( MI -> getDesc ( ) . getOpcode ( ) ) { default : return false ; case Mips :: RetRA16 : ExpandRetRA16 ( MBB , MI , Mips :: JrcRa16 ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> void analyze ( MachineBasicBlock & DefBlock , ArrayRef < MachineBasicBlock * > IncomingBlocks ) { assert ( Stack . empty ( ) ) ; ReachableMap . clear ( ) ; ReachableOrdered . clear ( ) ; Predecessors . clear ( ) ; ReachableMap . try_emplace ( & DefBlock , false ) ; ReachableOrdered . push_back ( & DefBlock ) ; for ( MachineBasicBlock * MBB : IncomingBlocks ) { if ( MBB == & DefBlock ) { ReachableMap [ & DefBlock ] = true ; continue ; } ReachableMap . try_emplace ( MBB , false ) ; ReachableOrdered . push_back ( MBB ) ; bool Divergent = false ; for ( MachineInstr & MI : MBB -> terminators ( ) ) { if ( MI . getOpcode ( ) == AMDGPU :: SI_NON_UNIFORM_BRCOND_PSEUDO || MI . getOpcode ( ) == AMDGPU :: SI_IF || MI . getOpcode ( ) == AMDGPU :: SI_ELSE || MI . getOpcode ( ) == AMDGPU :: SI_LOOP ) { Divergent = true ; break ; } } if ( Divergent && PDT . dominates ( & DefBlock , MBB ) ) { for ( MachineBasicBlock * Succ : MBB -> successors ( ) ) Stack . push_back ( Succ ) ; } } while ( ! Stack . empty ( ) ) { MachineBasicBlock * MBB = Stack . pop_back_val ( ) ; if ( ! ReachableMap . try_emplace ( MBB , false ) . second ) continue ; ReachableOrdered . push_back ( MBB ) ; for ( MachineBasicBlock * Succ : MBB -> successors ( ) ) Stack . push_back ( Succ ) ; } for ( MachineBasicBlock * MBB : ReachableOrdered ) { bool HaveReachablePred = false ; for ( MachineBasicBlock * Pred : MBB -> predecessors ( ) ) { if ( ReachableMap . count ( Pred ) ) { HaveReachablePred = true ; } else { Stack . push_back ( Pred ) ; } } if ( ! HaveReachablePred ) ReachableMap [ MBB ] = true ; if ( HaveReachablePred ) { for ( MachineBasicBlock * UnreachablePred : Stack ) { if ( llvm :: find ( Predecessors , UnreachablePred ) == Predecessors . end ( ) ) Predecessors . push_back ( UnreachablePred ) ; } } Stack . clear ( ) ; } } </s>

analyze - set CurLI to the specified interval , and analyze how it may be split .


<s> void SIInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { insertWaitStates ( MBB , MI , 1 ) ; } </s>

Insert a noop into the instruction stream at the specified point .


"Odd number of callee-saved regs to spill!"

"Expected GPR64 callee-saved register pair!"

"Expected FPR64 callee-saved register pair!"

"Offset out of bounds for STP immediate"

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


"Relocation required in an instruction that we cannot encode!"

getMachineOpValue - Return binary encoding of operand .


"  Skipping pass: no machine model present.\n"

runOnMachineFunction - Emit the function body .


<s>
static
char
*
describe_cache
(
struct
cache_desc
level1
,
struct
cache_desc
level2
)
{
char
size
[
100
]
,
line
[
100
]
,
size2
[
100
]
;
snprintf
(
size
,
sizeof
(
size
)
,
"--param l1-cache-size=%u "
,
level1
.
sizekb
)
;
snprintf
(
line
,
sizeof
(
line
)
,
"--param l1-cache-line-size=%u "
,
level1
.
line
)
;
snprintf
(
size2
,
sizeof
(
size2
)
,
"--param l2-cache-size=%u "
,
level2
.
sizekb
)
;
return
concat
(
size
,
line
,
size2
,
)
;
}
</s>

Returns parameters that describe L1_ASSOC associative cache of size L1_SIZEKB with lines of size L1_LINE , and L2_SIZEKB .


<s> static bool classof ( const DiagnosticInfo * DI ) { return DI -> getKind ( ) == getKindID ( ) ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> static void ix86_emit_binop ( enum rtx_code code , machine_mode mode , rtx dst , rtx src ) { rtx op , clob ; op = gen_rtx_SET ( dst , gen_rtx_fmt_ee ( code , mode , dst , src ) ) ; clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , op , clob ) ) ) ; } </s>

Emit x86 binary operand CODE in mode MODE , where the first operand matches destination . RTX includes clobber of FLAGS_REG .


<s> bool RISCVAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { if ( ! AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , OS ) ) return false ; const MachineOperand & MO = MI -> getOperand ( OpNo ) ; if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'z' : if ( MO . isImm ( ) && MO . getImm ( ) == 0 ) { OS << RISCVInstPrinter :: getRegisterName ( RISCV :: X0 ) ; return false ; } break ; case 'i' : if ( ! MO . isReg ( ) ) OS << 'i' ; return false ; } } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate : OS << MO . getImm ( ) ; return false ; case MachineOperand :: MO_Register : OS << RISCVInstPrinter :: getRegisterName ( MO . getReg ( ) ) ; return false ; default : break ; } return true ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < PatmosSPBundling > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> MVT SITargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( CC != CallingConv :: AMDGPU_KERNEL && VT . isVector ( ) ) { EVT ScalarVT = VT . getScalarType ( ) ; unsigned Size = ScalarVT . getSizeInBits ( ) ; if ( Size == 32 ) return ScalarVT . getSimpleVT ( ) ; if ( Size == 64 ) return MVT :: i32 ; if ( Size == 16 && Subtarget -> has16BitInsts ( ) ) return VT . isInteger ( ) ? MVT :: v2i16 : MVT :: v2f16 ; } return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


<s> bool RISCVAsmBackend :: shouldInsertFixupForCodeAlign ( MCAssembler & Asm , const MCAsmLayout & Layout , MCAlignFragment & AF ) { if ( ! STI . getFeatureBits ( ) [ RISCV :: FeatureRelax ] ) return false ; unsigned Count ; shouldInsertExtraNopBytesForCodeAlign ( AF , Count ) ; if ( Count == 0 ) return false ; MCContext & Ctx = Asm . getContext ( ) ; const MCExpr * Dummy = MCConstantExpr :: create ( 0 , Ctx ) ; MCFixup Fixup = MCFixup :: create ( 0 , Dummy , MCFixupKind ( RISCV :: fixup_riscv_align ) , SMLoc ( ) ) ; uint64_t FixedValue = 0 ; MCValue NopBytes = MCValue :: get ( Count ) ; Asm . getWriter ( ) . recordRelocation ( Asm , Layout , & AF , Fixup , NopBytes , FixedValue ) ; return true ; } </s>

Hook which indicates if the target requires a fixup to be generated when handling an align directive in an executable section .


"Blocked load and store instructions: \n"


<s> void setFrameAdjustment ( MachineInstr & I , int64_t V ) const { assert ( isFrameInstr ( I ) ) ; if ( isFrameSetup ( I ) ) I . getOperand ( 2 ) . setImm ( V ) ; else I . getOperand ( 1 ) . setImm ( V ) ; } </s>

Sets the stack pointer adjustment made inside the frame made up by this instruction .


<s>
int
AArch64AsmParser
::
tryParseRegister
(
)
{
const
AsmToken
&
Tok
=
Parser
.
getTok
(
)
;
assert
(
Tok
.
is
(
AsmToken
::
Identifier
)
&&
"Token is not an Identifier"
)
;
std
::
string
lowerCase
=
Tok
.
getString
(
)
.
lower
(
)
;
unsigned
RegNum
=
MatchRegisterName
(
lowerCase
)
;
if
(
RegNum
==
0
)
RegNum
=
StringSwitch
<
unsigned
>
(
lowerCase
)
.
Case
(
"fp"
,
AArch64
::
FP
)
.
Case
(
"lr"
,
AArch64
::
LR
)
.
Case
(
"x31"
,
AArch64
::
XZR
)
.
Case
(
"w31"
,
AArch64
::
WZR
)
.
Default
(
0
)
;
if
(
RegNum
==
0
)
return
1
;
Parser
.
Lex
(
)
;
return
RegNum
;
}
</s>

tryParseRegister - parse one register if possible


<s> bool SparcAsmPrinter :: doInitialization ( Module & M ) { Mang = new Mangler ( M , "" , TAI -> getPrivateGlobalPrefix ( ) ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> void RISCVMCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { uint64_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; unsigned Size = MCII . get ( MI . getOpcode ( ) ) . getSize ( ) ; unsigned ShiftValue = 0 ; for ( unsigned I = 0 ; I != Size ; ++ I ) { OS << uint8_t ( Bits >> ShiftValue ) ; ShiftValue += 8 ; } } </s>

Encode the given Inst to bytes and append to CB .


Do anything needed before RTL is emitted for each function .


<s> void loongarch_split_move ( rtx dest , rtx src , rtx insn_ ) { rtx low_dest ; gcc_checking_assert ( loongarch_split_move_p ( dest , src ) ) ; if ( FP_REG_RTX_P ( dest ) || FP_REG_RTX_P ( src ) ) { if ( ! TARGET_64BIT && GET_MODE ( dest ) == DImode ) emit_insn ( gen_move_doubleword_fprdi ( dest , src ) ) ; else if ( ! TARGET_64BIT && GET_MODE ( dest ) == DFmode ) emit_insn ( gen_move_doubleword_fprdf ( dest , src ) ) ; else if ( TARGET_64BIT && GET_MODE ( dest ) == TFmode ) emit_insn ( gen_move_doubleword_fprtf ( dest , src ) ) ; else gcc_unreachable ( ) ; } else { low_dest = loongarch_subword ( dest , false ) ; if ( REG_P ( low_dest ) && reg_overlap_mentioned_p ( low_dest , src ) ) { loongarch_emit_move ( loongarch_subword ( dest , true ) , loongarch_subword ( src , true ) ) ; loongarch_emit_move ( low_dest , loongarch_subword ( src , false ) ) ; } else { loongarch_emit_move ( low_dest , loongarch_subword ( src , false ) ) ; loongarch_emit_move ( loongarch_subword ( dest , true ) , loongarch_subword ( src , true ) ) ; } } rtx_insn * insn = ( rtx_insn * ) insn_ ; struct loongarch_address_info addr = { } ; if ( insn ) { rtx_insn * next = next_nonnote_nondebug_insn_bb ( insn ) ; if ( next ) { rtx set = single_set ( next ) ; if ( set && SET_SRC ( set ) == dest ) { if ( MEM_P ( src ) ) { rtx tmp = XEXP ( src , 0 ) ; loongarch_classify_address ( & addr , tmp , GET_MODE ( tmp ) , true ) ; if ( addr . reg && ! reg_overlap_mentioned_p ( dest , addr . reg ) ) validate_change ( next , & SET_SRC ( set ) , src , false ) ; } else validate_change ( next , & SET_SRC ( set ) , src , false ) ; } } } } </s>

Split a move from SRC to DEST , given that loongarch_split_move_p holds . SPLIT_TYPE describes the split condition .