<s> static void vax_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; * cum += ( arg . promoted_size_in_bytes ( ) + 3 ) & ~ 3 ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s>
bool
WebAssemblyArgumentMove
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
DEBUG
(
{
dbgs
(
)
<<
"********** Argument Move **********\n"
<<
"********** Function: "
<<
MF
.
getName
(
)
<<
'\n'
;
}
)
;
bool
Changed
=
false
;
MachineBasicBlock
&
EntryMBB
=
MF
.
front
(
)
;
MachineBasicBlock
::
iterator
InsertPt
=
EntryMBB
.
end
(
)
;
for
(
MachineInstr
&
MI
:
EntryMBB
)
{
if
(
!
IsArgument
(
MI
)
)
{
InsertPt
=
MI
;
break
;
}
}
for
(
MachineInstr
&
MI
:
llvm
::
make_range
(
InsertPt
,
EntryMBB
.
end
(
)
)
)
{
if
(
IsArgument
(
MI
)
)
{
EntryMBB
.
insert
(
InsertPt
,
MI
.
removeFromParent
(
)
)
;
Changed
=
true
;
}
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

WebAssembly
WebAssembly
"********** Argument Move **********\n"
"********** Function: "


"Unable to generate load/store offset for fusion"

Emit a D-form load or store instruction that is the second instruction of a fusion sequence .


<s>
void
ARMBaseInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
bool
GPRDest
=
ARM
::
GPRRegClass
.
contains
(
DestReg
)
;
bool
GPRSrc
=
ARM
::
GPRRegClass
.
contains
(
SrcReg
)
;
if
(
GPRDest
&&
GPRSrc
)
{
AddDefaultCC
(
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
MOVr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
)
)
;
return
;
}
bool
SPRDest
=
ARM
::
SPRRegClass
.
contains
(
DestReg
)
;
bool
SPRSrc
=
ARM
::
SPRRegClass
.
contains
(
SrcReg
)
;
unsigned
Opc
;
if
(
SPRDest
&&
SPRSrc
)
Opc
=
ARM
::
VMOVS
;
else
if
(
GPRDest
&&
SPRSrc
)
Opc
=
ARM
::
VMOVRS
;
else
if
(
SPRDest
&&
GPRSrc
)
Opc
=
ARM
::
VMOVSR
;
else
if
(
ARM
::
DPRRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
ARM
::
VMOVD
;
else
if
(
ARM
::
QPRRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
ARM
::
VMOVQ
;
else
if
(
ARM
::
QQPRRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
ARM
::
VMOVQQ
;
else
if
(
ARM
::
QQQQPRRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
ARM
::
VMOVQQQQ
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DestReg
)
;
MIB
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
if
(
Opc
!=
ARM
::
VMOVQQ
&&
Opc
!=
ARM
::
VMOVQQQQ
)
AddDefaultPred
(
MIB
)
;
}
</s>

ARM
ARM
ARM::GPRRegClass
ARM::GPRRegClass
ARM::MOVr
ARM::SPRRegClass
ARM::SPRRegClass
ARM::VMOVS
ARM::VMOVRS
ARM::VMOVSR
ARM::DPRRegClass
ARM::VMOVD
ARM::QPRRegClass
ARM::VMOVQ
ARM::QQPRRegClass
ARM::VMOVQQ
ARM::QQQQPRRegClass
ARM::VMOVQQQQ
"Impossible reg-to-reg copy"
ARM::VMOVQQ
ARM::VMOVQQQQ


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineModuleInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


"Can only insert epilog into returning blocks"


<s> virtual const MipsSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static inline bool reg_ok_for_index_p ( const_rtx x , bool strict ) { return reg_ok_for_base_p ( x , strict ) ; } </s>

Nonzero if X is a hard reg that can be used as an index .


<s> const uint32_t * Cpu0RegisterInfo :: getCallPreservedMask ( CallingConv :: ID ) const { return CSR_O32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


"Cannot store this register to stack slot!"

Store the specified register of the given register class to the specified stack frame index .


<s> bool X86PassConfig :: addGlobalInstructionSelect ( ) { return false ; } </s>

This method should install a ( global ) instruction selector pass , which converts possibly generic instructions to fully target-specific instructions , thereby constraining all generic virtual registers to register classes .


<s> static bool aarch64_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_SIMD && ( mode == V4SImode || mode == V8HImode || mode == V16QImode || mode == V2DImode || mode == V2SImode || mode == V4HImode || mode == V8QImode || mode == V2SFmode || mode == V4SFmode || mode == V2DFmode || mode == V1DFmode ) ) return true ; return false ; } </s>

Implements target hook vector_mode_supported_p .


<s>
EVT
Z80oldTargetLowering
::
getSetCCResultType
(
const
DataLayout
&
DL
,
LLVMContext
&
Context
,
EVT
VT
)
const
{
assert
(
!
VT
.
isVector
(
)
&&
"No default SetCC type for vectors!"
)
;
return
MVT
::
i8
;
}
</s>

Return the value type to use for ISD : :SETCC .


<s> static bool alpha_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { if ( ! decl ) return false ; return decl_has_samegp ( decl ) ; } </s>

We do not allow indirect calls to be optimized into sibling calls , nor can we allow a call to a function with a different GP to be optimized into a sibcall .


<s>
SDValue
OR1KTargetLowering
::
LowerCall
(
TargetLowering
::
CallLoweringInfo
&
CLI
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SelectionDAG
&
DAG
=
CLI
.
DAG
;
DebugLoc
&
dl
=
CLI
.
DL
;
SmallVector
<
ISD
::
OutputArg
,
32
>
&
Outs
=
CLI
.
Outs
;
SmallVector
<
SDValue
,
32
>
&
OutVals
=
CLI
.
OutVals
;
SmallVector
<
ISD
::
InputArg
,
32
>
&
Ins
=
CLI
.
Ins
;
SDValue
Chain
=
CLI
.
Chain
;
SDValue
Callee
=
CLI
.
Callee
;
bool
&
isTailCall
=
CLI
.
IsTailCall
;
CallingConv
::
ID
CallConv
=
CLI
.
CallConv
;
bool
isVarArg
=
CLI
.
IsVarArg
;
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
OutVals
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .


<s> static void add_to_dispatch_window ( rtx_insn * insn ) { int byte_len ; dispatch_windows * window_list ; dispatch_windows * next_list ; dispatch_windows * window0_list ; enum insn_path path ; enum dispatch_group insn_group ; bool insn_fits ; int num_insn ; int num_uops ; int window_num ; int insn_num_uops ; int sum ; if ( INSN_CODE ( insn ) < 0 ) return ; byte_len = min_insn_size ( insn ) ; window_list = dispatch_window_list ; next_list = window_list -> next ; path = get_insn_path ( insn ) ; insn_group = get_insn_group ( insn ) ; if ( next_list ) window_list = dispatch_window_list -> next ; if ( path == path_single ) insn_num_uops = 1 ; else if ( path == path_double ) insn_num_uops = 2 ; else insn_num_uops = ( int ) path ; num_insn = window_list -> num_insn ; num_uops = window_list -> num_uops ; window_num = window_list -> window_num ; insn_fits = fits_dispatch_window ( insn ) ; if ( num_insn >= MAX_INSN || num_uops + insn_num_uops > MAX_INSN || ! ( insn_fits ) ) { window_num = ~ window_num & 1 ; window_list = allocate_next_window ( window_num ) ; } if ( window_num == 0 ) { add_insn_window ( insn , window_list , insn_num_uops ) ; if ( window_list -> num_insn >= MAX_INSN && insn_group == disp_branch ) { process_end_window ( ) ; return ; } } else if ( window_num == 1 ) { window0_list = window_list -> prev ; sum = window0_list -> window_size + window_list -> window_size ; if ( sum == 32 || ( byte_len + sum ) >= 48 ) { process_end_window ( ) ; window_list = dispatch_window_list ; } add_insn_window ( insn , window_list , insn_num_uops ) ; } else gcc_unreachable ( ) ; if ( is_end_basic_block ( insn_group ) ) { process_end_window ( ) ; return ; } } </s>

Adds a scheduled instruction , INSN , to the current dispatch window . If the total bytes of instructions or the number of instructions in the window exceed allowable , it allocates a new window .


<s> bool LanaiAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( ( Count % 4 ) != 0 ) return false ; for ( uint64_t i = 0 ; i < Count ; i += 4 ) OW -> write32 ( 0x15000000 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> static void s390_register_info_stdarg_fpr ( ) { int i ; int min_fpr ; int max_fpr ; if ( ! cfun -> stdarg || ! TARGET_HARD_FLOAT || ! cfun -> va_list_fpr_size || crtl -> args . info . fprs >= FP_ARG_NUM_REG ) return ; min_fpr = crtl -> args . info . fprs ; max_fpr = min_fpr + cfun -> va_list_fpr_size - 1 ; if ( max_fpr >= FP_ARG_NUM_REG ) max_fpr = FP_ARG_NUM_REG - 1 ; min_fpr += FPR0_REGNUM ; max_fpr += FPR0_REGNUM ; for ( i = min_fpr ; i <= max_fpr ; i ++ ) cfun_set_fpr_save ( i ) ; } </s>

Set the bits in fpr_bitmap for FPRs which need to be saved due to stdarg . This is a helper routine for s390_register_info .


<s> static const char * ptrreg_to_str ( int regno ) { switch ( regno ) { case REG_X : return "X" ; case REG_Y : return "Y" ; case REG_Z : return "Z" ; default : gcc_unreachable ( ) ; } return NULL ; } </s>

Return a pointer register name as a string


<s> static rtx cris_struct_value_rtx ( tree fntype ATTRIBUTE_UNUSED , int incoming ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( Pmode , CRIS_STRUCT_VALUE_REGNUM ) ; } </s>

Worker function for TARGET_STRUCT_VALUE_RTX .


<s> TargetLoweringBase :: LegalizeTypeAction X86TargetLowering :: getPreferredVectorAction ( MVT VT ) const { if ( VT == MVT :: v32i1 && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return TypeSplitVector ; if ( ExperimentalVectorWideningLegalization && VT . getVectorNumElements ( ) != 1 && VT . getVectorElementType ( ) != MVT :: i1 ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s> static bool tilegx_cannot_force_const_mem ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ATTRIBUTE_UNUSED ) { return true ; } </s>


<s> static std :: unique_ptr < HexagonOperand > CreateReg ( MCContext & Context , unsigned RegNum , SMLoc S , SMLoc E ) { HexagonOperand * Op = new HexagonOperand ( Register , Context ) ; Op -> Reg . RegNum = RegNum ; Op -> StartLoc = S ; Op -> EndLoc = E ; return std :: unique_ptr < HexagonOperand > ( Op ) ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> bool sh_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( SPECIAL_REGISTER_P ( regno ) ) return mode == SImode ; if ( regno == FPUL_REG ) return ( mode == SImode || mode == SFmode ) ; if ( FP_REGISTER_P ( regno ) && mode == SFmode ) return true ; if ( mode == V2SFmode ) { if ( ( ( FP_REGISTER_P ( regno ) && ( regno - FIRST_FP_REG ) % 2 == 0 ) || GENERAL_REGISTER_P ( regno ) ) ) return true ; else return false ; } if ( mode == V4SFmode ) { if ( ( FP_REGISTER_P ( regno ) && ( regno - FIRST_FP_REG ) % 4 == 0 ) || GENERAL_REGISTER_P ( regno ) ) return true ; else return false ; } if ( mode == V16SFmode ) { if ( TARGET_SHMEDIA ) { if ( FP_REGISTER_P ( regno ) && ( regno - FIRST_FP_REG ) % 16 == 0 ) return true ; else return false ; } else return regno == FIRST_XD_REG ; } if ( FP_REGISTER_P ( regno ) ) { if ( mode == SFmode || mode == SImode || ( ( TARGET_SH2E || TARGET_SHMEDIA ) && mode == SCmode ) || ( ( ( ( TARGET_SH4 || TARGET_SH2A_DOUBLE ) && mode == DFmode ) || mode == DCmode || ( TARGET_SHMEDIA && ( mode == DFmode || mode == DImode || mode == V2SFmode || mode == TImode ) ) ) && ( ( regno - FIRST_FP_REG ) & 1 ) == 0 ) || ( ( TARGET_SH4 || TARGET_SHMEDIA ) && mode == TImode && ( ( regno - FIRST_FP_REG ) & 3 ) == 0 ) ) return true ; else return false ; } if ( XD_REGISTER_P ( regno ) ) return mode == DFmode ; if ( TARGET_REGISTER_P ( regno ) ) return ( mode == DImode || mode == SImode || mode == PDImode ) ; if ( regno == PR_REG ) return mode == SImode ; if ( regno == FPSCR_REG ) return mode == SImode ; if ( ! optimize && TARGET_SHMEDIA32 && GET_MODE_SIZE ( mode ) > 4 ) { unsigned int n = GET_MODE_SIZE ( mode ) / 8 ; if ( regno >= FIRST_GENERAL_REG + 10 - n + 1 && regno <= FIRST_GENERAL_REG + 14 ) return false ; } return true ; } </s>

Return true if hard register REGNO can hold a value of machine-mode MODE . We can allow any mode in any general register . The special registers only allow SImode . Do n't allow any mode in the PR . We can not hold DCmode values in the XD registers because alter_reg handles subregs of them incorrectly . We could work around this by spacing the XD registers like the DR registers , but this would require additional memory in every compilation to hold larger register vectors . We could hold SFmode / SCmode values in XD registers , but that would require a tertiary reload when reloading from / to memory , and a secondary reload to reload from / to general regs ; that seems to be a losing proposition . We want to allow TImode FP regs so that when V4SFmode is loaded as TImode , it wo n't be ferried through GP registers first .


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
READ_REGISTER
:
ExpandREAD_REGISTER
(
N
,
Results
,
DAG
)
;
break
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SREM
:
case
ISD
::
UREM
:
Res
=
LowerREM
(
N
,
DAG
)
;
break
;
case
ISD
::
SDIVREM
:
case
ISD
::
UDIVREM
:
Res
=
LowerDivRem
(
SDValue
(
N
,
0
)
,
DAG
)
;
assert
(
Res
.
getNumOperands
(
)
==
2
&&
"DivRem needs two values"
)
;
Results
.
push_back
(
Res
.
getValue
(
0
)
)
;
Results
.
push_back
(
Res
.
getValue
(
1
)
)
;
return
;
case
ISD
::
READCYCLECOUNTER
:
ReplaceREADCYCLECOUNTER
(
N
,
Results
,
DAG
,
Subtarget
)
;
return
;
case
ISD
::
UDIV
:
case
ISD
::
SDIV
:
assert
(
Subtarget
->
isTargetWindows
(
)
&&
"can only expand DIV on Windows"
)
;
return
ExpandDIV_Windows
(
SDValue
(
N
,
0
)
,
DAG
,
N
->
getOpcode
(
)
==
ISD
::
SDIV
,
Results
)
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

ARM
ARM
"Don't know how to custom expand this!"
ISD::READ_REGISTER
ISD::BITCAST
ISD::SRL
ISD::SRA
ISD::SREM
ISD::UREM
ISD::SDIVREM
ISD::UDIVREM
0
2
"DivRem needs two values"
0
1
ISD::READCYCLECOUNTER
ISD::UDIV
ISD::SDIV
"can only expand DIV on Windows"
0
ISD::SDIV


<s> static bool rs6000_secondary_reload_simple_move ( enum rs6000_reg_type to_type , enum rs6000_reg_type from_type , machine_mode mode ) { int size = GET_MODE_SIZE ( mode ) ; if ( TARGET_DIRECT_MOVE && ( ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) || ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) { if ( TARGET_POWERPC64 ) { if ( size == 8 ) return true ; if ( size == 16 && TARGET_P9_VECTOR && mode != TDmode ) return true ; } if ( TARGET_VSX_SMALL_INTEGER ) { if ( mode == SImode ) return true ; if ( TARGET_P9_VECTOR && ( mode == HImode || mode == QImode ) ) return true ; } if ( mode == SDmode ) return true ; } else if ( TARGET_MFPGPR && TARGET_POWERPC64 && size == 8 && ( ( to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE ) || ( to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; else if ( ( size == 4 || ( TARGET_POWERPC64 && size == 8 ) ) && ( ( to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE ) || ( to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; return false ; } </s>

Helper function for rs6000_secondary_reload to return true if a move to a different register classe is really a simple move .


"Don't know how to custom type legalize this operation!"

"READCYCLECOUNTER only has custom type legalization on riscv32"


<s> static bool isPairedLdSt ( const MachineInstr * MI ) { switch ( MI -> getOpcode ( ) ) { default : return false ; case AArch64 :: LDPSi : case AArch64 :: LDPSWi : case AArch64 :: LDPDi : case AArch64 :: LDPQi : case AArch64 :: LDPWi : case AArch64 :: LDPXi : case AArch64 :: STPSi : case AArch64 :: STPDi : case AArch64 :: STPQi : case AArch64 :: STPWi : case AArch64 :: STPXi : return true ; } } </s>

Returns whether the instruction is a paired load/store .


<s> void HexagonInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ) ; if ( Hexagon :: IntRegsRegisterClass -> hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: STriw ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( Hexagon :: DoubleRegsRegisterClass -> hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: STrid ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( Hexagon :: PredRegsRegisterClass -> hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: STriw_pred ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else { llvm_unreachable ( "Unimplemented" ) ; } } </s>

Store the specified register of the given register class to the specified stack frame index .

Hexagon Hexagon Hexagon::IntRegsRegisterClass Hexagon::STriw 0 Hexagon::DoubleRegsRegisterClass Hexagon::STrid 0 Hexagon::PredRegsRegisterClass Hexagon::STriw_pred 0 "Unimplemented"


<s> static bool aarch64_scalar_mode_supported_p ( scalar_mode mode ) { return ( mode == HFmode ? true : default_scalar_mode_supported_p ( mode ) ) ; } </s>

Implement TARGET_SCALAR_MODE_SUPPORTED_P - return TRUE if MODE is HFmode , and punt to the generic implementation otherwise .


<s>
void
LoongArchDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
SDLoc
DL
(
Node
)
;
switch
(
Opcode
)
{
default
:
break
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> static bool sparc_promote_prototypes ( tree fntype ATTRIBUTE_UNUSED ) { return TARGET_ARCH32 ? true : false ; } </s>

Handle the TARGET_PROMOTE_PROTOTYPES target hook . When a prototype says ` char ' or ` short ' , really pass an ` int ' .


<s> static bool i386_pe_determine_dllexport_p ( tree decl ) { if ( TREE_CODE ( decl ) != VAR_DECL && TREE_CODE ( decl ) != FUNCTION_DECL ) return false ; if ( ! TREE_PUBLIC ( decl ) ) return false ; if ( TREE_CODE ( decl ) == FUNCTION_DECL && DECL_DECLARED_INLINE_P ( decl ) && ! flag_keep_inline_dllexport ) return false ; if ( lookup_attribute ( "dllexport" , DECL_ATTRIBUTES ( decl ) ) ) return true ; return false ; } </s>

Return true if DECL should be a dllexport 'd object .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
AArch64
::
NumTargetFixupKinds
]
=
{
{
"fixup_aarch64_pcrel_adr_imm21"
,
0
,
32
,
PCRelFlagVal
}
,
{
"fixup_aarch64_pcrel_adrp_imm21"
,
0
,
32
,
PCRelFlagVal
}
,
{
"fixup_aarch64_add_imm12"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldst_imm12_scale1"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldst_imm12_scale2"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldst_imm12_scale4"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldst_imm12_scale8"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldst_imm12_scale16"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldr_pcrel_imm19"
,
5
,
19
,
PCRelFlagVal
}
,
{
"fixup_aarch64_movw"
,
5
,
16
,
0
}
,
{
"fixup_aarch64_pcrel_branch14"
,
5
,
14
,
PCRelFlagVal
}
,
{
"fixup_aarch64_pcrel_branch19"
,
5
,
19
,
PCRelFlagVal
}
,
{
"fixup_aarch64_pcrel_branch26"
,
0
,
26
,
PCRelFlagVal
}
,
{
"fixup_aarch64_pcrel_call26"
,
0
,
26
,
PCRelFlagVal
}
,
{
"fixup_aarch64_tlsdesc_call"
,
0
,
0
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> unsigned HexagonMCInst :: getType ( ) const { const uint64_t F = MCID -> TSFlags ; return ( ( F >> HexagonII :: TypePos ) & HexagonII :: TypeMask ) ; } </s>

Overload to return most specific vector type .

Hexagon Hexagon HexagonII::TypePos HexagonII::TypeMask


<s> virtual void * getAdjustedAnalysisPointer ( const void * ID ) override { if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo * ) this ; return this ; } </s>

getAdjustedAnalysisPointer - This method is used when a pass implements an analysis interface through multiple inheritance .


<s> static void avr_asm_named_section ( const char * name , unsigned int flags , tree decl ) { if ( flags & AVR_SECTION_PROGMEM ) { addr_space_t as = ( flags & AVR_SECTION_PROGMEM ) / SECTION_MACH_DEP ; const char * old_prefix = ".rodata" ; const char * new_prefix = avr_addrspace [ as ] . section_name ; if ( STR_PREFIX_P ( name , old_prefix ) ) { const char * sname = ACONCAT ( ( new_prefix , name + strlen ( old_prefix ) , NULL ) ) ; default_elf_asm_named_section ( sname , flags , decl ) ; return ; } default_elf_asm_named_section ( new_prefix , flags , decl ) ; return ; } if ( ! avr_need_copy_data_p ) avr_need_copy_data_p = ( STR_PREFIX_P ( name , ".data" ) || STR_PREFIX_P ( name , ".rodata" ) || STR_PREFIX_P ( name , ".gnu.linkonce.d" ) ) ; if ( ! avr_need_clear_bss_p ) avr_need_clear_bss_p = STR_PREFIX_P ( name , ".bss" ) ; default_elf_asm_named_section ( name , flags , decl ) ; } </s>

Track need of __do_clear_bss , __do_copy_data for named sections .


<s> static void riscv_save_restore_reg ( enum machine_mode mode , int regno , HOST_WIDE_INT offset , riscv_save_restore_fn fn ) { rtx mem ; mem = gen_frame_mem ( mode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; fn ( gen_rtx_REG ( mode , regno ) , mem ) ; } </s>

Use FN to save or restore register REGNO . MODE is the register 's mode and OFFSET is the offset of its save slot from the current stack pointer .


<s> bool SystemZLDCleanup :: runOnMachineFunction ( MachineFunction & F ) { if ( skipFunction ( F . getFunction ( ) ) ) return false ; TII = static_cast < const SystemZInstrInfo * > ( F . getSubtarget ( ) . getInstrInfo ( ) ) ; MF = & F ; SystemZMachineFunctionInfo * MFI = F . getInfo < SystemZMachineFunctionInfo > ( ) ; if ( MFI -> getNumLocalDynamicTLSAccesses ( ) < 2 ) { return false ; } MachineDominatorTree * DT = & getAnalysis < MachineDominatorTree > ( ) ; return VisitNode ( DT -> getRootNode ( ) , 0 ) ; } </s>

runOnMachineFunction - Emit the function body .

SystemZ SystemZ SystemZ SystemZ SystemZ 2 0


<s> void rs6000_emit_sCOND ( machine_mode mode , rtx operands [ ] ) { rtx condition_rtx ; machine_mode op_mode ; enum rtx_code cond_code ; rtx result = operands [ 0 ] ; condition_rtx = rs6000_generate_compare ( operands [ 1 ] , mode ) ; cond_code = GET_CODE ( condition_rtx ) ; if ( cond_code == NE || cond_code == GE || cond_code == LE || cond_code == GEU || cond_code == LEU || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE ) { rtx not_result = gen_reg_rtx ( CCEQmode ) ; rtx not_op , rev_cond_rtx ; machine_mode cc_mode ; cc_mode = GET_MODE ( XEXP ( condition_rtx , 0 ) ) ; rev_cond_rtx = gen_rtx_fmt_ee ( rs6000_reverse_condition ( cc_mode , cond_code ) , SImode , XEXP ( condition_rtx , 0 ) , const0_rtx ) ; not_op = gen_rtx_COMPARE ( CCEQmode , rev_cond_rtx , const0_rtx ) ; emit_insn ( gen_rtx_SET ( not_result , not_op ) ) ; condition_rtx = gen_rtx_EQ ( VOIDmode , not_result , const0_rtx ) ; } op_mode = GET_MODE ( XEXP ( operands [ 1 ] , 0 ) ) ; if ( op_mode == VOIDmode ) op_mode = GET_MODE ( XEXP ( operands [ 1 ] , 1 ) ) ; if ( TARGET_POWERPC64 && ( op_mode == DImode || FLOAT_MODE_P ( mode ) ) ) { PUT_MODE ( condition_rtx , DImode ) ; convert_move ( result , condition_rtx , 0 ) ; } else { PUT_MODE ( condition_rtx , SImode ) ; emit_insn ( gen_rtx_SET ( result , condition_rtx ) ) ; } } </s>


<s> static bool or1k_frame_pointer_required ( ) { return ( crtl -> accesses_prior_frames ) ; } </s>

Worker for TARGET_FRAME_POINTER_REQUIRED . Returns true if the current function must use a frame pointer .


<s> bool XCoreAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { this -> MF = & MF ; SetupMachineFunction ( MF ) ; EmitConstantPool ( MF . getConstantPool ( ) ) ; EmitJumpTableInfo ( MF . getJumpTableInfo ( ) , MF ) ; emitFunctionStart ( MF ) ; DW -> BeginFunction ( & MF ) ; for ( MachineFunction :: const_iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( I != MF . begin ( ) ) { printBasicBlockLabel ( I , true , true ) ; O << '\n' ; } for ( MachineBasicBlock :: const_iterator II = I -> begin ( ) , E = I -> end ( ) ; II != E ; ++ II ) { O << "\t" ; printMachineInstruction ( II ) ; } O << '\n' ; } emitFunctionEnd ( MF ) ; DW -> EndFunction ( & MF ) ; return false ; } </s>


<s>
unsigned
CJGMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
{
return
CTX
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
}
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
if
(
MO
.
isExpr
(
)
)
{
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
MCExpr
::
ExprKind
Kind
=
Expr
->
getKind
(
)
;
if
(
Kind
==
MCExpr
::
Constant
)
{
return
cast
<
MCConstantExpr
>
(
Expr
)
->
getValue
(
)
;
}
if
(
Kind
==
MCExpr
::
Binary
)
{
Expr
=
static_cast
<
const
MCBinaryExpr
*
>
(
Expr
)
->
getLHS
(
)
;
Kind
=
Expr
->
getKind
(
)
;
}
assert
(
Kind
==
MCExpr
::
SymbolRef
&&
"unknown MCExpr kind"
)
;
CJG
::
Fixups
FixupKind
=
CJG
::
Fixups
(
0
)
;
switch
(
cast
<
MCSymbolRefExpr
>
(
Expr
)
->
getKind
(
)
)
{
default
:
llvm_unreachable
(
"Unknown fixup kind!"
)
;
case
MCSymbolRefExpr
::
VK_None
:
FixupKind
=
CJG
::
fixup_CJG_32
;
break
;
}
Fixups
.
push_back
(
MCFixup
::
create
(
0
,
Expr
,
MCFixupKind
(
FixupKind
)
)
)
;
return
0
;
}
llvm_unreachable
(
"Unhandled expression!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> const TargetRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static void mips_avoid_hazard ( rtx_insn * after , rtx_insn * insn , int * hilo_delay , rtx * delayed_reg , rtx lo_reg , bool * fs_delay ) { rtx pattern , set ; int nops , ninsns ; pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) == ASM_INPUT || asm_noperands ( pattern ) >= 0 ) cfun -> machine -> all_noreorder_p = false ; ninsns = get_attr_length ( insn ) / 4 ; if ( ninsns == 0 ) return ; if ( * hilo_delay < 2 && reg_set_p ( lo_reg , pattern ) ) nops = 2 - * hilo_delay ; else if ( * delayed_reg != 0 && reg_referenced_p ( * delayed_reg , pattern ) ) nops = 1 ; else if ( * fs_delay && get_attr_can_delay ( insn ) == CAN_DELAY_NO && GET_CODE ( PATTERN ( after ) ) != SEQUENCE && GET_CODE ( pattern ) != ASM_INPUT && asm_noperands ( pattern ) < 0 ) nops = 1 ; else if ( TUNE_P6600 && TARGET_CB_MAYBE && ! optimize_size && ( ( mips_classify_branch_p6600 ( after ) == UC_BALC && mips_classify_branch_p6600 ( insn ) == UC_OTHER ) || ( mips_classify_branch_p6600 ( insn ) == UC_BALC && mips_classify_branch_p6600 ( after ) == UC_OTHER ) ) ) nops = 1 ; else nops = 0 ; * hilo_delay += nops ; rtx_insn * real_after = after ; if ( real_after && nops && CALL_P ( real_after ) ) while ( real_after && ( NOTE_P ( NEXT_INSN ( real_after ) ) || BARRIER_P ( NEXT_INSN ( real_after ) ) ) ) real_after = NEXT_INSN ( real_after ) ; while ( nops -- > 0 ) emit_insn_after ( gen_hazard_nop ( ) , real_after ) ; * hilo_delay += ninsns ; * delayed_reg = 0 ; * fs_delay = false ; if ( INSN_CODE ( insn ) >= 0 ) switch ( get_attr_hazard ( insn ) ) { case HAZARD_NONE : if ( TUNE_P6600 && ! optimize_size && TARGET_CB_MAYBE && mips_classify_branch_p6600 ( insn ) == UC_OTHER ) * fs_delay = true ; break ; case HAZARD_FORBIDDEN_SLOT : if ( TARGET_CB_MAYBE ) * fs_delay = true ; break ; case HAZARD_HILO : * hilo_delay = 0 ; break ; case HAZARD_DELAY : set = single_set ( insn ) ; gcc_assert ( set ) ; * delayed_reg = SET_DEST ( set ) ; break ; } } </s>

Subroutine of mips_reorg . If there is a hazard between INSN and a previous instruction , avoid it by inserting nops after instruction AFTER . * DELAYED_REG and * HILO_DELAY describe the hazards that apply at this point . If * DELAYED_REG is non-null , INSN must wait a cycle before using the value of that register . * HILO_DELAY counts the number of instructions since the last hilo hazard ( that is , the number of instructions since the last mflo or mfhi ) . After inserting nops for INSN , update * DELAYED_REG and * HILO_DELAY for the next instruction . LO_REG is an rtx for the LO register , used in dependence checking .


<s> bool ProtectSpillSupportPass :: runOnMachineFunction ( MachineFunction & Func ) { const X86InstrInfo * TII = static_cast < const X86InstrInfo * > ( Func . getTarget ( ) . getInstrInfo ( ) ) ; bool modified = false ; SmallVector < CJEItem , 8 > worklist ; for ( auto MBBI = Func . begin ( ) , MBBE = Func . end ( ) ; MBBI != MBBE ; ++ MBBI ) { for ( auto MI = MBBI -> begin ( ) , ME = MBBI -> end ( ) ; MI != ME ; ++ MI ) { CJEItem item ; if ( isCJEOpcode ( MI -> getOpcode ( ) , item . NativeOpcode , item . isFrameSetup ) ) { item . MI = MI ; item . isEFLAGSlive = TII -> isRegLiveAtMI ( X86 :: EFLAGS , MI ) ; item . isRAXlive = isRAXLiveAtMI ( MI ) ; worklist . push_back ( item ) ; } } } modified = ! worklist . empty ( ) ; while ( ! worklist . empty ( ) ) { CJEItem item = worklist . pop_back_val ( ) ; transformCJE ( item . MI , item . NativeOpcode , item . isFrameSetup , item . isEFLAGSlive , item . isRAXlive ) ; } return modified ; } </s>


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Mips OptimizePICCall"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> PPCSubtarget :: PPCSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , bool is64Bit ) : PPCGenSubtargetInfo ( TT , CPU , FS ) , StackAlignment ( 16 ) , DarwinDirective ( PPC :: DIR_NONE ) , IsGigaProcessor ( false ) , Has64BitSupport ( false ) , Use64BitRegs ( false ) , IsPPC64 ( is64Bit ) , HasAltivec ( false ) , HasFSQRT ( false ) , HasSTFIWX ( false ) , HasLazyResolverStubs ( false ) , IsJITCodeModel ( false ) , TargetTriple ( TT ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "generic" ; if ( CPUName == "generic" ) CPUName = GetCurrentPowerPCCPU ( ) ; ParseSubtargetFeatures ( CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( is64Bit ) { Has64BitSupport = true ; Use64BitRegs = true ; } if ( use64BitRegs ( ) && ! has64BitSupport ( ) ) Use64BitRegs = false ; if ( isDarwin ( ) ) HasLazyResolverStubs = true ; } </s>

This constructor initializes the data members to match that of the specified triple .

PowerPC PPC PPC PPC 16 PPC::DIR_NONE PPC "generic" "generic"


"Switch should handle all register classes"


"BPF CO-RE requires BTF debugging information, use %<-gbtf%>"

Override options and do some other initialization .


<s> bool ix86_expand_fp_movcc ( rtx operands [ ] ) { machine_mode mode = GET_MODE ( operands [ 0 ] ) ; enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; rtx tmp , compare_op ; rtx op0 = XEXP ( operands [ 1 ] , 0 ) ; rtx op1 = XEXP ( operands [ 1 ] , 1 ) ; if ( SSE_FLOAT_MODE_SSEMATH_OR_HF_P ( mode ) ) { machine_mode cmode ; cmode = GET_MODE ( op0 ) ; if ( cmode == VOIDmode ) cmode = GET_MODE ( op1 ) ; if ( cmode != mode ) return false ; code = ix86_prepare_sse_fp_compare_args ( operands [ 0 ] , code , & op0 , & op1 ) ; if ( code == UNKNOWN ) return false ; if ( ix86_expand_sse_fp_minmax ( operands [ 0 ] , code , op0 , op1 , operands [ 2 ] , operands [ 3 ] ) ) return true ; tmp = ix86_expand_sse_cmp ( operands [ 0 ] , code , op0 , op1 , operands [ 2 ] , operands [ 3 ] ) ; ix86_expand_sse_movcc ( operands [ 0 ] , tmp , operands [ 2 ] , operands [ 3 ] ) ; return true ; } if ( GET_MODE ( op0 ) == TImode || ( GET_MODE ( op0 ) == DImode && ! TARGET_64BIT ) ) return false ; compare_op = ix86_expand_compare ( code , op0 , op1 ) ; if ( ! fcmov_comparison_operator ( compare_op , VOIDmode ) ) { tmp = gen_reg_rtx ( QImode ) ; ix86_expand_setcc ( tmp , code , op0 , op1 ) ; compare_op = ix86_expand_compare ( NE , tmp , const0_rtx ) ; } emit_insn ( gen_rtx_SET ( operands [ 0 ] , gen_rtx_IF_THEN_ELSE ( mode , compare_op , operands [ 2 ] , operands [ 3 ] ) ) ) ; return true ; } </s>

Expand a floating-point conditional move . Return true if successful .


<s> bool HexagonPassConfig :: addPreEmitPass ( ) { if ( ! DisableHardwareLoops ) { PM -> add ( createHexagonFixupHwLoops ( ) ) ; } PM -> add ( createHexagonExpandPredSpillCode ( getHexagonTargetMachine ( ) ) ) ; PM -> add ( createHexagonSplitTFRCondSets ( getHexagonTargetMachine ( ) ) ) ; return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon


<s>
static
X86Operand
*
CreateMem
(
unsigned
SegReg
,
const
MCExpr
*
Disp
,
unsigned
BaseReg
,
unsigned
IndexReg
,
unsigned
Scale
,
SMLoc
StartLoc
,
SMLoc
EndLoc
)
{
assert
(
(
SegReg
||
BaseReg
||
IndexReg
)
&&
"Invalid memory operand!"
)
;
assert
(
(
(
Scale
==
1
||
Scale
==
2
||
Scale
==
4
||
Scale
==
8
)
)
&&
"Invalid scale!"
)
;
X86Operand
*
Res
=
new
X86Operand
(
Memory
,
StartLoc
,
EndLoc
)
;
Res
->
Mem
.
SegReg
=
SegReg
;
Res
->
Mem
.
Disp
=
Disp
;
Res
->
Mem
.
BaseReg
=
BaseReg
;
Res
->
Mem
.
IndexReg
=
IndexReg
;
Res
->
Mem
.
Scale
=
Scale
;
return
Res
;
}
</s>


<s> std :: vector < std :: string > add ( Px a , Bx b ) { return D ( "add" , R ( a ) , R ( b ) ) ; } </s>


<s> bool ThumbRegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { if ( MF . getSubtarget < ARMSubtarget > ( ) . isThumb1Only ( ) ) { return false ; } return true ; } </s>

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot .


<s>
bool
HexagonPacketizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
const
TargetInstrInfo
*
TII
=
Fn
.
getTarget
(
)
.
getInstrInfo
(
)
;
MachineLoopInfo
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
MachineDominatorTree
&
MDT
=
getAnalysis
<
MachineDominatorTree
>
(
)
;
HexagonPacketizerList
Packetizer
(
Fn
,
MLI
,
MDT
)
;
assert
(
Packetizer
.
getResourceTracker
(
)
&&
"Empty DFA table!"
)
;
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
MachineBasicBlock
::
iterator
End
=
MBB
->
end
(
)
;
MachineBasicBlock
::
iterator
MI
=
MBB
->
begin
(
)
;
while
(
MI
!=
End
)
{
if
(
MI
->
isKill
(
)
)
{
MachineBasicBlock
::
iterator
DeleteMI
=
MI
;
++
MI
;
MBB
->
erase
(
DeleteMI
)
;
End
=
MBB
->
end
(
)
;
continue
;
}
++
MI
;
}
}
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
unsigned
RemainingCount
=
MBB
->
size
(
)
;
for
(
MachineBasicBlock
::
iterator
RegionEnd
=
MBB
->
end
(
)
;
RegionEnd
!=
MBB
->
begin
(
)
;
)
{
MachineBasicBlock
::
iterator
I
=
RegionEnd
;
for
(
;
I
!=
MBB
->
begin
(
)
;
I
,
RemainingCount
)
{
if
(
TII
->
isSchedulingBoundary
(
llvm
::
prior
(
I
)
,
MBB
,
Fn
)
)
break
;
}
I
=
MBB
->
begin
(
)
;
if
(
I
==
RegionEnd
)
{
RegionEnd
=
llvm
::
prior
(
RegionEnd
)
;
RemainingCount
;
continue
;
}
if
(
I
==
llvm
::
prior
(
RegionEnd
)
)
{
RegionEnd
=
llvm
::
prior
(
RegionEnd
)
;
continue
;
}
Packetizer
.
PacketizeMIs
(
MBB
,
I
,
RegionEnd
)
;
RegionEnd
=
I
;
}
}
return
true
;
}
</s>

Hexagon
Hexagon
Hexagon
"Empty DFA table!"


<s> void Warning ( SMLoc L , const Twine & Msg ) { getParser ( ) . Warning ( L , Msg ) ; } </s>

Emit a warning at the location L , with the message Msg .


<s> int move_double_src_operand ( rtx op , enum machine_mode mode ) { switch ( GET_CODE ( op ) ) { case REG : return register_operand ( op , mode ) ; case SUBREG : if ( GET_CODE ( SUBREG_REG ( op ) ) == MEM ) return move_double_src_operand ( SUBREG_REG ( op ) , mode ) ; else return register_operand ( op , mode ) ; case MEM : if ( GET_CODE ( XEXP ( op , 0 ) ) == PRE_DEC || GET_CODE ( XEXP ( op , 0 ) ) == PRE_INC ) return 0 ; return address_operand ( XEXP ( op , 0 ) , mode ) ; case CONST_INT : case CONST_DOUBLE : return 1 ; default : return 0 ; } } </s>

Return true if OP is an acceptable argument for a double word move source .


<s> bool hasTrue16BitInsts ( ) const { return HasTrue16BitInsts ; } </s>

Return true if the subtarget supports True16 instructions .


<s> const SICRegisterInfo & SICInstrInfo :: getRegisterInfo ( ) const { return RI ; } </s>


<s> static rtx nvptx_gen_unpack ( rtx dst0 , rtx dst1 , rtx src ) { rtx res ; switch ( GET_MODE ( src ) ) { case DImode : res = gen_unpackdisi2 ( dst0 , dst1 , src ) ; break ; case DFmode : res = gen_unpackdfsi2 ( dst0 , dst1 , src ) ; break ; default : gcc_unreachable ( ) ; } return res ; } </s>

Generate instruction ( s ) to unpack a 64 bit object into 2 32 bit objects .


<s>
void
PIC16TargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
{
switch
(
N
->
getOpcode
(
)
)
{
case
ISD
::
GlobalAddress
:
Results
.
push_back
(
ExpandGlobalAddress
(
N
,
DAG
)
)
;
return
;
case
ISD
::
ExternalSymbol
:
Results
.
push_back
(
ExpandExternalSymbol
(
N
,
DAG
)
)
;
return
;
case
ISD
::
STORE
:
Results
.
push_back
(
ExpandStore
(
N
,
DAG
)
)
;
return
;
case
ISD
::
LOAD
:
PopulateResults
(
ExpandLoad
(
N
,
DAG
)
,
Results
)
;
return
;
case
ISD
::
ADD
:
return
;
case
ISD
::
FrameIndex
:
Results
.
push_back
(
ExpandFrameIndex
(
N
,
DAG
)
)
;
return
;
default
:
assert
(
0
&&
"not implemented"
)
;
return
;
}
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

PIC16
PIC16
ISD::GlobalAddress
ISD::ExternalSymbol
ISD::STORE
ISD::LOAD
ISD::ADD
ISD::FrameIndex
0
"not implemented"


<s> void AArch64PassConfig :: addPreGlobalInstructionSelect ( ) { if ( TM -> getOptLevel ( ) == CodeGenOpt :: None ) addPass ( new Localizer ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before the ( global ) instruction selection .


<s> bool NVPTXTTI :: hasBranchDivergence ( ) const { return true ; } </s>

Return true if branch divergence exists .


<s> bool ARMPassConfig :: addPreISel ( ) { if ( ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE ) addPass ( createGlobalMergePass ( TM , 127 ) ) ; return false ; } </s>


<s> bool MBlazeTargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> bool ARMPreAllocLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { TD = Fn . getTarget ( ) . getDataLayout ( ) ; STI = & static_cast < const ARMSubtarget & > ( Fn . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; MF = & Fn ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) Modified |= RescheduleLoadStoreInstrs ( MFI ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> const char * arm_gen_far_branch ( rtx * operands , int pos_label , const char * dest , const char * branch_format ) { rtx_code_label * tmp_label = gen_label_rtx ( ) ; char label_buf [ 256 ] ; char buffer [ 128 ] ; ASM_GENERATE_INTERNAL_LABEL ( label_buf , dest , \ CODE_LABEL_NUMBER ( tmp_label ) ) ; const char * label_ptr = arm_strip_name_encoding ( label_buf ) ; rtx dest_label = operands [ pos_label ] ; operands [ pos_label ] = tmp_label ; snprintf ( buffer , sizeof ( buffer ) , "%s%s" , branch_format , label_ptr ) ; output_asm_insn ( buffer , operands ) ; snprintf ( buffer , sizeof ( buffer ) , "b\t%%l0%d\n%s:" , pos_label , label_ptr ) ; operands [ pos_label ] = dest_label ; output_asm_insn ( buffer , operands ) ; return "" ; } </s>

Generate code to enable conditional branches in functions over 1 MiB . Parameters are : operands : is the operands list of the asm insn ( see arm_cond_branch or arm_cond_branch_reversed ) . pos_label : is an index into the operands array where operands [ pos_label ] is the asm label of the final jump destination . dest : is a string which is used to generate the asm label of the intermediate destination branch_format : is a string denoting the intermediate branch format , e.g . `` beq '' , `` bne '' , etc .


<s>
void
ARMTTIImpl
::
getUnrollingPreferences
(
Loop
*
L
,
ScalarEvolution
&
SE
,
TTI
::
UnrollingPreferences
&
UP
)
{
if
(
!
ST
->
isMClass
(
)
)
return
BasicTTIImplBase
::
getUnrollingPreferences
(
L
,
SE
,
UP
)
;
UP
.
OptSizeThreshold
=
0
;
UP
.
PartialOptSizeThreshold
=
0
;
if
(
L
->
getHeader
(
)
->
getParent
(
)
->
hasOptSize
(
)
)
return
;
if
(
!
ST
->
isThumb2
(
)
)
return
;
SmallVector
<
BasicBlock
*
,
4
>
ExitingBlocks
;
L
->
getExitingBlocks
(
ExitingBlocks
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Loop has:\n"
<<
"Blocks: "
<<
L
->
getNumBlocks
(
)
<<
"\n"
<<
"Exit blocks: "
<<
ExitingBlocks
.
size
(
)
<<
"\n"
)
;
if
(
ExitingBlocks
.
size
(
)
>
2
)
return
;
if
(
ST
->
hasBranchPredictor
(
)
&&
L
->
getNumBlocks
(
)
>
4
)
return
;
unsigned
Cost
=
0
;
for
(
auto
*
BB
:
L
->
getBlocks
(
)
)
{
for
(
auto
&
I
:
*
BB
)
{
if
(
I
.
getType
(
)
->
isVectorTy
(
)
)
return
;
if
(
isa
<
CallInst
>
(
I
)
||
isa
<
InvokeInst
>
(
I
)
)
{
ImmutableCallSite
CS
(
&
I
)
;
if
(
const
Function
*
F
=
CS
.
getCalledFunction
(
)
)
{
if
(
!
isLoweredToCall
(
F
)
)
continue
;
}
return
;
}
SmallVector
<
const
Value
*
,
4
>
Operands
(
I
.
value_op_begin
(
)
,
I
.
value_op_end
(
)
)
;
Cost
+=
getUserCost
(
&
I
,
Operands
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Cost of loop: "
<<
Cost
<<
"\n"
)
;
UP
.
Partial
=
true
;
UP
.
Runtime
=
true
;
UP
.
UpperBound
=
true
;
UP
.
UnrollRemainder
=
true
;
UP
.
DefaultUnrollRuntimeCount
=
4
;
UP
.
UnrollAndJam
=
true
;
UP
.
UnrollAndJamInnerLoopThreshold
=
60
;
if
(
Cost
<
12
)
UP
.
Force
=
true
;
}
</s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> BitVector RISCVRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const RISCVFrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; for ( size_t Reg = 0 ; Reg < getNumRegs ( ) ; Reg ++ ) { if ( MF . getSubtarget < RISCVSubtarget > ( ) . isRegisterReservedByUser ( Reg ) ) markSuperRegs ( Reserved , Reg ) ; } markSuperRegs ( Reserved , RISCV :: X0 ) ; markSuperRegs ( Reserved , RISCV :: X2 ) ; markSuperRegs ( Reserved , RISCV :: X3 ) ; markSuperRegs ( Reserved , RISCV :: X4 ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , RISCV :: X8 ) ; if ( TFI -> hasBP ( MF ) ) markSuperRegs ( Reserved , RISCVABI :: getBPReg ( ) ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void AArch64BranchFixup :: verify ( ) { for ( MachineFunction :: iterator MBBI = MF -> begin ( ) , E = MF -> end ( ) ; MBBI != E ; ++ MBBI ) { MachineBasicBlock * MBB = MBBI ; unsigned MBBId = MBB -> getNumber ( ) ; assert ( ! MBBId || BBInfo [ MBBId - 1 ] . postOffset ( ) <= BBInfo [ MBBId ] . Offset ) ; } } </s>


<s> TargetIRAnalysis TGSITargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( const Function & F ) { return TargetTransformInfo ( TGSITTIImpl ( this , F ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


<s> bool ARMBaseInstrInfo :: analyzeCompare ( const MachineInstr * MI , unsigned & SrcReg , unsigned & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case ARM :: CMPri : case ARM :: t2CMPri : SrcReg = MI -> getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = MI -> getOperand ( 1 ) . getImm ( ) ; return true ; case ARM :: CMPrr : case ARM :: t2CMPrr : SrcReg = MI -> getOperand ( 0 ) . getReg ( ) ; SrcReg2 = MI -> getOperand ( 1 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case ARM :: TSTri : case ARM :: t2TSTri : SrcReg = MI -> getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = MI -> getOperand ( 1 ) . getImm ( ) ; CmpValue = 0 ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> static unsigned HOST_WIDE_INT aarch64_asan_shadow_offset ( void ) { return ( HOST_WIDE_INT_1 << 36 ) ; } </s>

Implement the TARGET_ASAN_SHADOW_OFFSET hook .


<s>
void
HSAILInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
DestReg
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
unsigned
int
Opc
=
0
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
DebugLoc
DL
;
unsigned
BT
;
switch
(
RC
->
getID
(
)
)
{
default
:
llvm_unreachable
(
"unrecognized TargetRegisterClass"
)
;
break
;
case
HSAIL
::
GPR32RegClassID
:
Opc
=
HSAIL
::
LD_U32
;
BT
=
BRIG_TYPE_U32
;
break
;
case
HSAIL
::
GPR64RegClassID
:
Opc
=
HSAIL
::
LD_U64
;
BT
=
BRIG_TYPE_U64
;
break
;
case
HSAIL
::
CRRegClassID
:
Opc
=
HSAIL
::
RESTORE_B1
;
BT
=
BRIG_TYPE_B1
;
break
;
}
if
(
MI
!=
MBB
.
end
(
)
)
{
DL
=
MI
->
getDebugLoc
(
)
;
}
switch
(
RC
->
getID
(
)
)
{
default
:
llvm_unreachable
(
"unrecognized TargetRegisterClass"
)
;
break
;
case
HSAIL
::
GPR32RegClassID
:
case
HSAIL
::
GPR64RegClassID
:
case
HSAIL
::
CRRegClassID
:
{
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FrameIndex
)
,
MachineMemOperand
::
MOLoad
,
MFI
.
getObjectSize
(
FrameIndex
)
,
MFI
.
getObjectAlignment
(
FrameIndex
)
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
)
.
addReg
(
DestReg
,
RegState
::
Define
)
.
addFrameIndex
(
FrameIndex
)
.
addReg
(
HSAIL
::
NoRegister
)
.
addImm
(
0
)
.
addImm
(
BT
)
.
addImm
(
HSAILAS
::
SPILL_ADDRESS
)
.
addImm
(
MMO
->
getAlignment
(
)
)
.
addImm
(
BRIG_WIDTH_1
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
break
;
}
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> static void m68k_conditional_register_usage ( void ) { int i ; HARD_REG_SET x ; if ( ! TARGET_HARD_FLOAT ) { x = reg_class_contents [ FP_REGS ] ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( x , i ) ) fixed_regs [ i ] = call_used_regs [ i ] = 1 ; } if ( flag_pic ) fixed_regs [ PIC_REG ] = call_used_regs [ PIC_REG ] = 1 ; } </s>

Make sure everything 's fine if we * do n't * have a given processor . This assumes that putting a register in fixed_regs will keep the compiler 's mitts completely off it . We do n't bother to zero it out of register classes .


<s>
void
NVPTXAsmPrinter
::
emitHeader
(
Module
&
M
,
raw_ostream
&
O
)
{
O
<<
"//\n"
;
O
<<
"// Generated by LLVM NVPTX Back-End\n"
;
O
<<
"//\n"
;
O
<<
"\n"
;
unsigned
PTXVersion
=
nvptxSubtarget
.
getPTXVersion
(
)
;
O
<<
".version "
<<
(
PTXVersion
/
10
)
<<
"."
<<
(
PTXVersion
%
10
)
<<
"\n"
;
O
<<
".target "
;
O
<<
nvptxSubtarget
.
getTargetName
(
)
;
if
(
nvptxSubtarget
.
getDrvInterface
(
)
==
NVPTX
::
NVCL
)
O
<<
", texmode_independent"
;
if
(
nvptxSubtarget
.
getDrvInterface
(
)
==
NVPTX
::
CUDA
)
{
if
(
!
nvptxSubtarget
.
hasDouble
(
)
)
O
<<
", map_f64_to_f32"
;
}
if
(
MAI
->
doesSupportDebugInformation
(
)
)
O
<<
", debug"
;
O
<<
"\n"
;
O
<<
".address_size "
;
if
(
nvptxSubtarget
.
is64Bit
(
)
)
O
<<
"64"
;
else
O
<<
"32"
;
O
<<
"\n"
;
O
<<
"\n"
;
}
</s>

Emit the header for this unit , not including the initial length field .

NVPTX
NVPTX
"//\n"
"// Generated by LLVM NVPTX Back-End\n"
"//\n"
"\n"
".version "
10
"."
10
"\n"
".target "
NVPTX::NVCL
", texmode_independent"
NVPTX::CUDA
", map_f64_to_f32"
", debug"
"\n"
".address_size "
"64"
"32"
"\n"
"\n"


<s> static unsigned HOST_WIDE_INT mips_asan_shadow_offset ( void ) { if ( mips_abi == ABI_N32 ) return ( HOST_WIDE_INT_1 << 29 ) ; if ( POINTER_SIZE == 64 ) return ( HOST_WIDE_INT_1 << 37 ) ; else return HOST_WIDE_INT_C ( 0x0aaa0000 ) ; } </s>


<s> void ARMPassConfig :: addCodeGenPrepare ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createTypePromotionPass ( ) ) ; TargetPassConfig :: addCodeGenPrepare ( ) ; } </s>

Add pass to prepare the LLVM IR for code generation .


<s> int arm_count_output_move_double_insns ( rtx * operands ) { int count ; rtx ops [ 2 ] ; ops [ 0 ] = operands [ 0 ] ; ops [ 1 ] = operands [ 1 ] ; output_move_double ( ops , false , & count ) ; return count ; } </s>

Compute the number of instructions emitted by output_move_double .


<s> BitVector SparcRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const SparcSubtarget & Subtarget = MF . getSubtarget < SparcSubtarget > ( ) ; Reserved . set ( SP :: G1 ) ; if ( ReserveAppRegisters ) { Reserved . set ( SP :: G2 ) ; Reserved . set ( SP :: G3 ) ; Reserved . set ( SP :: G4 ) ; } if ( ! Subtarget . is64Bit ( ) ) Reserved . set ( SP :: G5 ) ; Reserved . set ( SP :: O6 ) ; Reserved . set ( SP :: I6 ) ; Reserved . set ( SP :: I7 ) ; Reserved . set ( SP :: G0 ) ; Reserved . set ( SP :: G6 ) ; Reserved . set ( SP :: G7 ) ; Reserved . set ( SP :: G0_G1 ) ; if ( ReserveAppRegisters ) Reserved . set ( SP :: G2_G3 ) ; if ( ReserveAppRegisters || ! Subtarget . is64Bit ( ) ) Reserved . set ( SP :: G4_G5 ) ; Reserved . set ( SP :: O6_O7 ) ; Reserved . set ( SP :: I6_I7 ) ; Reserved . set ( SP :: G6_G7 ) ; if ( ! Subtarget . isV9 ( ) ) { for ( unsigned n = 0 ; n != 16 ; ++ n ) { for ( MCRegAliasIterator AI ( SP :: D16 + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; } } return Reserved ; } </s>


<s>
int
getRegClass
(
)
const
{
assert
(
Kind
==
OpKind
::
Reg
&&
"Invalid access!"
)
;
return
Reg
.
Class
;
}
</s>

Given a machine instruction descriptor , returns the register class constraint for OpNum , or NULL .


"Couldn't assign to global base register!"

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> bool X86TTIImpl :: isLegalMaskedGather ( Type * DataTy , Align Alignment ) { if ( ! supportsGather ( ) ) return false ; Type * ScalarTy = DataTy -> getScalarType ( ) ; if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == 32 || IntWidth == 64 ; } </s>

Return true if the target supports masked gather .


<s> static unsigned int visium_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( regno == MDB_REGNUM ) return CEIL ( GET_MODE_SIZE ( mode ) , 2 * UNITS_PER_WORD ) ; return CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ; } </s>


<s> int GCNTTIImpl :: getMinMaxReductionCost ( VectorType * Ty , VectorType * CondTy , bool IsPairwise , bool IsUnsigned , TTI :: TargetCostKind CostKind ) { EVT OrigTy = TLI -> getValueType ( DL , Ty ) ; if ( IsPairwise || ! ST -> hasVOP3PInsts ( ) || OrigTy . getScalarSizeInBits ( ) != 16 ) return BaseT :: getMinMaxReductionCost ( Ty , CondTy , IsPairwise , IsUnsigned , CostKind ) ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; return LT . first * getHalfRateInstrCost ( CostKind ) ; } </s>

Try to calculate op costs for min/max reduction operations .


<s> SDValue AMDGPUTargetLowering :: SplitVectorLoad ( const SDValue Op , SelectionDAG & DAG ) const { LoadSDNode * Load = cast < LoadSDNode > ( Op ) ; EVT VT = Op . getValueType ( ) ; SDLoc SL ( Op ) ; if ( VT . getVectorNumElements ( ) == 2 ) { SDValue Ops [ 2 ] ; std :: tie ( Ops [ 0 ] , Ops [ 1 ] ) = scalarizeVectorLoad ( Load , DAG ) ; return DAG . getMergeValues ( Ops , SL ) ; } SDValue BasePtr = Load -> getBasePtr ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; const MachinePointerInfo & SrcValue = Load -> getMemOperand ( ) -> getPointerInfo ( ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = getSplitDestVTs ( VT , DAG ) ; std :: tie ( LoMemVT , HiMemVT ) = getSplitDestVTs ( MemVT , DAG ) ; std :: tie ( Lo , Hi ) = splitVector ( Op , SL , LoVT , HiVT , DAG ) ; unsigned Size = LoMemVT . getStoreSize ( ) ; unsigned BaseAlign = Load -> getAlignment ( ) ; unsigned HiAlign = MinAlign ( BaseAlign , Size ) ; SDValue LoLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , LoVT , Load -> getChain ( ) , BasePtr , SrcValue , LoMemVT , BaseAlign , Load -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue HiPtr = DAG . getObjectPtrOffset ( SL , BasePtr , Size ) ; SDValue HiLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , HiVT , Load -> getChain ( ) , HiPtr , SrcValue . getWithOffset ( LoMemVT . getStoreSize ( ) ) , HiMemVT , HiAlign , Load -> getMemOperand ( ) -> getFlags ( ) ) ; auto IdxTy = getVectorIdxTy ( DAG . getDataLayout ( ) ) ; SDValue Join ; if ( LoVT == HiVT ) { Join = DAG . getNode ( ISD :: CONCAT_VECTORS , SL , VT , LoLoad , HiLoad ) ; } else { Join = DAG . getNode ( ISD :: INSERT_SUBVECTOR , SL , VT , DAG . getUNDEF ( VT ) , LoLoad , DAG . getConstant ( 0 , SL , IdxTy ) ) ; Join = DAG . getNode ( HiVT . isVector ( ) ? ISD :: INSERT_SUBVECTOR : ISD :: INSERT_VECTOR_ELT , SL , VT , Join , HiLoad , DAG . getConstant ( LoVT . getVectorNumElements ( ) , SL , IdxTy ) ) ; } SDValue Ops [ ] = { Join , DAG . getNode ( ISD :: TokenFactor , SL , MVT :: Other , LoLoad . getValue ( 1 ) , HiLoad . getValue ( 1 ) ) } ; return DAG . getMergeValues ( Ops , SL ) ; } </s>

Split a vector load into 2 loads of half the vector .


<s> static int msp430_muldiv_costs ( rtx src , rtx dst , bool speed , rtx outer_rtx , machine_mode outer_mode ) { enum rtx_code outer_code = GET_CODE ( outer_rtx ) ; const struct msp430_multlib_costs * cost_p ; cost_p = ( msp430_use_16bit_hwmult ( ) ? & cycle_cost_multlib_32bit : & cycle_cost_multlib_16bit ) ; int factor = 1 ; int mode_factor = 1 ; if ( outer_mode == SImode ) mode_factor = 2 ; else if ( outer_mode == PSImode ) mode_factor = 3 ; else if ( outer_mode == DImode ) mode_factor = 4 ; if ( ! speed ) { if ( outer_code != MULT ) factor = 7 ; else if ( ( ( msp430_use_16bit_hwmult ( ) && outer_mode != DImode ) || msp430_use_32bit_hwmult ( ) || msp430_use_f5_series_hwmult ( ) ) ) factor = 2 ; else factor = 5 ; return factor * mode_factor * msp430_costs ( src , dst , speed , outer_rtx ) ; } if ( outer_code != MULT || ! msp430_has_hwmult ( ) || ( outer_mode == DImode && msp430_use_16bit_hwmult ( ) ) ) { factor = ( outer_code == MULT ? 50 : 70 ) ; return factor * mode_factor * msp430_costs ( src , dst , speed , outer_rtx ) ; } switch ( outer_mode ) { case E_QImode : case E_HImode : return cost_p -> mulhi + ( 3 * msp430_costs ( src , dst , speed , outer_rtx ) ) ; case E_PSImode : factor = 2 ; case E_SImode : return factor * ( cost_p -> mulsi + ( 6 * msp430_costs ( src , dst , speed , outer_rtx ) ) ) ; case E_DImode : default : return cost_p -> muldi + ( 12 * msp430_costs ( src , dst , speed , outer_rtx ) ) ; } } </s>

Given source operand SRC and destination operand DST from the MULT/DIV/MOD RTX OUTER_RTX , return the cost of performing that operation , assuming optimization for speed when SPEED is true .


<s> void R600InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { unsigned VectorComponents = 0 ; if ( ( AMDGPU :: R600_Reg128RegClass . contains ( DestReg ) || AMDGPU :: R600_Reg128VerticalRegClass . contains ( DestReg ) ) && ( AMDGPU :: R600_Reg128RegClass . contains ( SrcReg ) || AMDGPU :: R600_Reg128VerticalRegClass . contains ( SrcReg ) ) ) { VectorComponents = 4 ; } else if ( ( AMDGPU :: R600_Reg64RegClass . contains ( DestReg ) || AMDGPU :: R600_Reg64VerticalRegClass . contains ( DestReg ) ) && ( AMDGPU :: R600_Reg64RegClass . contains ( SrcReg ) || AMDGPU :: R600_Reg64VerticalRegClass . contains ( SrcReg ) ) ) { VectorComponents = 2 ; } if ( VectorComponents > 0 ) { for ( unsigned I = 0 ; I < VectorComponents ; I ++ ) { unsigned SubRegIndex = AMDGPURegisterInfo :: getSubRegFromChannel ( I ) ; buildDefaultInstruction ( MBB , MI , AMDGPU :: MOV , RI . getSubReg ( DestReg , SubRegIndex ) , RI . getSubReg ( SrcReg , SubRegIndex ) ) . addReg ( DestReg , RegState :: Define | RegState :: Implicit ) ; } } else { MachineInstr * NewMI = buildDefaultInstruction ( MBB , MI , AMDGPU :: MOV , DestReg , SrcReg ) ; NewMI -> getOperand ( getOperandIdx ( * NewMI , AMDGPU :: OpName :: src0 ) ) . setIsKill ( KillSrc ) ; } } </s>


<s>
MCSymbol
*
TLCS900MCInstLower
::
GetBlockAddressSymbol
(
const
MachineOperand
&
MO
)
const
{
switch
(
MO
.
getTargetFlags
(
)
)
{
default
:
llvm_unreachable
(
"Unknown target flag on GV operand"
)
;
case
0
:
break
;
}
return
Printer
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
;
}
</s>

Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block .


<s> bool Thumb1RegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { const TargetInstrInfo & TII = * MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; AddDefaultPred ( BuildMI ( MBB , I , DL , TII . get ( ARM :: tMOVr ) ) . addReg ( ARM :: R12 , RegState :: Define ) . addReg ( Reg , RegState :: Kill ) ) ; bool done = false ; for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { if ( II -> isDebugValue ( ) ) continue ; for ( unsigned i = 0 , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( ARM :: R12 ) ) { UseMI = II ; done = true ; break ; } if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == ARM :: R12 ) { UseMI = II ; done = true ; break ; } } } AddDefaultPred ( BuildMI ( MBB , UseMI , DL , TII . get ( ARM :: tMOVr ) ) . addReg ( Reg , RegState :: Define ) . addReg ( ARM :: R12 , RegState :: Kill ) ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .


<s> static bool msp430_preserve_reg_p ( int regno ) { if ( regno <= 3 ) return false ; if ( crtl -> calls_eh_return ) return true ; if ( fixed_regs [ regno ] ) return false ; if ( msp430_is_interrupt_func ( ) && regno >= 11 && regno <= 15 ) { if ( crtl -> is_leaf && df_regs_ever_live_p ( regno ) ) return true ; else if ( ! crtl -> is_leaf ) return true ; } if ( ! call_used_or_fixed_reg_p ( regno ) && df_regs_ever_live_p ( regno ) ) return true ; return false ; } </s>

This is the one spot that decides if a register is to be saved and restored in the prologue/epilogue .


<s> bool hasSPackHL ( ) const { return GFX11Insts ; } </s>

Return true if the target has the S_PACK_HL_B32_B16 instruction .


This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool AMDGPUPassConfig :: addPreSched2 ( ) { addPass ( & IfConverterID ) ; return false ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> static bool aapcs_vfp_allocate ( CUMULATIVE_ARGS * pcum , machine_mode mode , const_tree type ATTRIBUTE_UNUSED ) { int rmode_size = MAX ( GET_MODE_SIZE ( pcum -> aapcs_vfp_rmode ) , GET_MODE_SIZE ( SFmode ) ) ; int shift = rmode_size / GET_MODE_SIZE ( SFmode ) ; unsigned mask = ( 1 << ( shift * pcum -> aapcs_vfp_rcount ) ) - 1 ; int regno ; for ( regno = 0 ; regno < NUM_VFP_ARG_REGS ; regno += shift ) if ( ( ( pcum -> aapcs_vfp_regs_free >> regno ) & mask ) == mask ) { pcum -> aapcs_vfp_reg_alloc = mask << regno ; if ( mode == BLKmode || ( mode == TImode && ! TARGET_NEON ) || ! arm_hard_regno_mode_ok ( FIRST_VFP_REGNUM + regno , mode ) ) { int i ; int rcount = pcum -> aapcs_vfp_rcount ; int rshift = shift ; machine_mode rmode = pcum -> aapcs_vfp_rmode ; rtx par ; if ( ! TARGET_NEON ) { if ( rmode == V2SImode ) rmode = DImode ; else if ( rmode == V4SImode ) { rmode = DImode ; rcount *= 2 ; rshift /= 2 ; } } par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( rcount ) ) ; for ( i = 0 ; i < rcount ; i ++ ) { rtx tmp = gen_rtx_REG ( rmode , FIRST_VFP_REGNUM + regno + i * rshift ) ; tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , GEN_INT ( i * GET_MODE_SIZE ( rmode ) ) ) ; XVECEXP ( par , 0 , i ) = tmp ; } pcum -> aapcs_reg = par ; } else pcum -> aapcs_reg = gen_rtx_REG ( mode , FIRST_VFP_REGNUM + regno ) ; return true ; } return false ; } </s>

Implement the allocate field in aapcs_cp_arg_layout . See the comment there for the behaviour of this function .


<s> void mips_expand_vector_init ( rtx target , rtx vals ) { machine_mode vmode = GET_MODE ( target ) ; machine_mode imode = GET_MODE_INNER ( vmode ) ; unsigned i , nelt = GET_MODE_NUNITS ( vmode ) ; unsigned nvar = 0 , one_var = - 1u ; bool all_same = true ; rtx x ; for ( i = 0 ; i < nelt ; ++ i ) { x = XVECEXP ( vals , 0 , i ) ; if ( ! mips_constant_elt_p ( x ) ) nvar ++ , one_var = i ; if ( i > 0 && ! rtx_equal_p ( x , XVECEXP ( vals , 0 , 0 ) ) ) all_same = false ; } if ( nvar == 0 ) { emit_move_insn ( target , gen_rtx_CONST_VECTOR ( vmode , XVEC ( vals , 0 ) ) ) ; return ; } if ( nelt == 2 ) { rtx op0 = force_reg ( imode , XVECEXP ( vals , 0 , 0 ) ) ; rtx op1 = force_reg ( imode , XVECEXP ( vals , 0 , 1 ) ) ; x = gen_rtx_VEC_CONCAT ( vmode , op0 , op1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , x ) ) ; return ; } gcc_assert ( TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS ) ; if ( all_same ) { mips_expand_vi_broadcast ( vmode , target , XVECEXP ( vals , 0 , 0 ) ) ; return ; } if ( nvar == 1 && vmode == V4HImode ) { mips_expand_vi_loongson_one_pinsrh ( target , vals , one_var ) ; return ; } mips_expand_vi_general ( vmode , imode , nelt , nvar , target , vals ) ; } </s>


<s> void finishLayout ( MCAssembler const & Asm , MCAsmLayout & Layout ) const override { for ( auto I : Layout . getSectionOrder ( ) ) { auto & Fragments = I -> getFragmentList ( ) ; for ( auto & J : Fragments ) { switch ( J . getKind ( ) ) { default : break ; case MCFragment :: FT_Align : { auto Size = Asm . computeFragmentSize ( Layout , J ) ; for ( auto K = J . getIterator ( ) ; K != Fragments . begin ( ) && Size >= HEXAGON_PACKET_SIZE ; ) { -- K ; switch ( K -> getKind ( ) ) { default : break ; case MCFragment :: FT_Align : { Size = 0 ; break ; } case MCFragment :: FT_Relaxable : { auto & RF = cast < MCRelaxableFragment > ( * K ) ; auto & Inst = const_cast < MCInst & > ( RF . getInst ( ) ) ; while ( Size > 0 && HexagonMCInstrInfo :: bundleSize ( Inst ) < 4 ) { MCInst * Nop = new ( Asm . getContext ( ) ) MCInst ; Nop -> setOpcode ( Hexagon :: A2_nop ) ; Inst . addOperand ( MCOperand :: createInst ( Nop ) ) ; Size -= 4 ; if ( ! HexagonMCChecker ( * MCII , RF . getSubtargetInfo ( ) , Inst , Inst , * Asm . getContext ( ) . getRegisterInfo ( ) ) . check ( ) ) { Inst . erase ( Inst . end ( ) - 1 ) ; Size = 0 ; } } bool Error = HexagonMCShuffle ( true , * MCII , RF . getSubtargetInfo ( ) , Inst ) ; ( void ) Error ; ReplaceInstruction ( Asm . getEmitter ( ) , RF , Inst ) ; Layout . invalidateFragmentsFrom ( & RF ) ; Size = 0 ; break ; } } } } } } } } </s>

Give backend an opportunity to finish layout after relaxation .


<s>
bool
WinEHStatePass
::
runOnFunction
(
Function
&
F
)
{
StringRef
WinEHParentName
=
F
.
getFnAttribute
(
"wineh-parent"
)
.
getValueAsString
(
)
;
if
(
WinEHParentName
!=
F
.
getName
(
)
&&
!
WinEHParentName
.
empty
(
)
)
return
false
;
if
(
!
F
.
hasPersonalityFn
(
)
)
return
false
;
PersonalityFn
=
dyn_cast
<
Function
>
(
F
.
getPersonalityFn
(
)
->
stripPointerCasts
(
)
)
;
if
(
!
PersonalityFn
)
return
false
;
Personality
=
classifyEHPersonality
(
PersonalityFn
)
;
if
(
!
isMSVCEHPersonality
(
Personality
)
)
return
false
;
F
.
addFnAttr
(
"no-frame-pointer-elim"
,
"true"
)
;
emitExceptionRegistrationRecord
(
&
F
)
;
auto
*
MMI
=
getAnalysisIfAvailable
<
MachineModuleInfo
>
(
)
;
std
::
unique_ptr
<
WinEHFuncInfo
>
FuncInfoPtr
;
if
(
!
MMI
)
FuncInfoPtr
.
reset
(
new
WinEHFuncInfo
(
)
)
;
WinEHFuncInfo
&
FuncInfo
=
*
(
MMI
&
MMI
->
getWinEHFuncInfo
(
&
F
)
:
FuncInfoPtr
.
get
(
)
)
;
FuncInfo
.
EHRegNode
=
RegNode
;
switch
(
Personality
)
{
default
:
llvm_unreachable
(
"unexpected personality function"
)
;
case
EHPersonality
::
MSVC_CXX
:
addCXXStateStores
(
F
,
FuncInfo
)
;
break
;
case
EHPersonality
::
MSVC_X86SEH
:
addSEHStateStores
(
F
,
FuncInfo
)
;
break
;
}
PersonalityFn
=
nullptr
;
Personality
=
EHPersonality
::
Unknown
;
return
true
;
}
</s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .

X86
"wineh-parent"
"no-frame-pointer-elim"
"true"
"unexpected personality function"
X86


<s> void HCE :: collect ( MachineFunction & MF ) { Extenders . clear ( ) ; for ( MachineBasicBlock & MBB : MF ) for ( MachineInstr & MI : MBB ) collectInstr ( MI ) ; } </s>

Analyze the given instruction MI and fill in the Uses , Defs and DeadDefs list based on the MachineOperand flags .


<s> void s390_expand_atomic ( machine_mode mode , enum rtx_code code , rtx target , rtx mem , rtx val , bool after ) { struct alignment_context ac ; rtx cmp ; rtx new_rtx = gen_reg_rtx ( SImode ) ; rtx orig = gen_reg_rtx ( SImode ) ; rtx_code_label * csloop = gen_label_rtx ( ) ; gcc_assert ( ! target || register_operand ( target , VOIDmode ) ) ; gcc_assert ( MEM_P ( mem ) ) ; init_alignment_context ( & ac , mem , mode ) ; if ( ! ( ac . aligned && code == SET && MEM_P ( val ) ) ) val = s390_expand_mask_and_shift ( val , mode , ac . shift ) ; if ( code == PLUS || code == MINUS ) emit_move_insn ( orig , val ) ; else if ( code == MULT || code == AND ) val = expand_simple_binop ( SImode , XOR , val , ac . modemaski , NULL_RTX , 1 , OPTAB_DIRECT ) ; cmp = force_reg ( SImode , ac . memsi ) ; emit_label ( csloop ) ; emit_move_insn ( new_rtx , cmp ) ; switch ( code ) { case PLUS : case MINUS : val = expand_simple_binop ( SImode , code , new_rtx , orig , NULL_RTX , 1 , OPTAB_DIRECT ) ; val = expand_simple_binop ( SImode , AND , val , ac . modemask , NULL_RTX , 1 , OPTAB_DIRECT ) ; case SET : if ( ac . aligned && MEM_P ( val ) ) store_bit_field ( new_rtx , GET_MODE_BITSIZE ( mode ) , 0 , 0 , 0 , SImode , val ) ; else { new_rtx = expand_simple_binop ( SImode , AND , new_rtx , ac . modemaski , NULL_RTX , 1 , OPTAB_DIRECT ) ; new_rtx = expand_simple_binop ( SImode , IOR , new_rtx , val , NULL_RTX , 1 , OPTAB_DIRECT ) ; } break ; case AND : case IOR : case XOR : new_rtx = expand_simple_binop ( SImode , code , new_rtx , val , NULL_RTX , 1 , OPTAB_DIRECT ) ; break ; case MULT : new_rtx = expand_simple_binop ( SImode , AND , new_rtx , val , NULL_RTX , 1 , OPTAB_DIRECT ) ; new_rtx = expand_simple_binop ( SImode , XOR , new_rtx , ac . modemask , NULL_RTX , 1 , OPTAB_DIRECT ) ; break ; default : gcc_unreachable ( ) ; } s390_emit_jump ( csloop , s390_emit_compare_and_swap ( NE , cmp , ac . memsi , cmp , new_rtx ) ) ; if ( target ) convert_move ( target , expand_simple_binop ( SImode , LSHIFTRT , after ? new_rtx : cmp , ac . shift , NULL_RTX , 1 , OPTAB_DIRECT ) , 1 ) ; } </s>

Expand an atomic operation CODE of mode MODE . MEM is the memory location and VAL the value to play with . If AFTER is true then store the the value MEM holds after the operation , if AFTER is false then store the value MEM holds before the operation . If TARGET is zero then discard that value , else store it to TARGET .


<s> const DLXRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
unsigned
getTypeID
(
Type
*
T
)
const
{
TypeMapType
::
const_iterator
I
=
TypeMap
.
find
(
T
)
;
assert
(
I
!=
TypeMap
.
end
(
)
&&
"Type not in ValueEnumerator!"
)
;
return
I
->
second
1
;
}
</s>

DirectX
"Type not in ValueEnumerator!"
1


<s>
SDValue
MSP430TargetLowering
::
LowerCall
(
TargetLowering
::
CallLoweringInfo
&
CLI
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SelectionDAG
&
DAG
=
CLI
.
DAG
;
SDLoc
&
dl
=
CLI
.
DL
;
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
=
CLI
.
Outs
;
SmallVectorImpl
<
SDValue
>
&
OutVals
=
CLI
.
OutVals
;
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
=
CLI
.
Ins
;
SDValue
Chain
=
CLI
.
Chain
;
SDValue
Callee
=
CLI
.
Callee
;
bool
&
isTailCall
=
CLI
.
IsTailCall
;
CallingConv
::
ID
CallConv
=
CLI
.
CallConv
;
bool
isVarArg
=
CLI
.
IsVarArg
;
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
report_fatal_error
(
"Unsupported calling convention"
)
;
case
CallingConv
::
MSP430_BUILTIN
:
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
OutVals
,
Ins
,
dl
,
DAG
,
InVals
)
;
case
CallingConv
::
MSP430_INTR
:
report_fatal_error
(
"ISRs cannot be called directly"
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .


<s> unsigned X86TargetLowering :: getVectorTypeBreakdownForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT , EVT & IntermediateVT , unsigned & NumIntermediates , MVT & RegisterVT ) const { if ( VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i1 && Subtarget . hasAVX512 ( ) && ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) || ( VT . getVectorNumElements ( ) > 16 && ! Subtarget . hasBWI ( ) ) || ( VT . getVectorNumElements ( ) > 64 && Subtarget . hasBWI ( ) ) ) ) { RegisterVT = MVT :: i8 ; IntermediateVT = MVT :: i1 ; NumIntermediates = VT . getVectorNumElements ( ) ; return NumIntermediates ; } if ( VT == MVT :: v64i1 && Subtarget . hasBWI ( ) && ! Subtarget . useAVX512Regs ( ) && CC != CallingConv :: X86_RegCall ) { RegisterVT = MVT :: v32i1 ; IntermediateVT = MVT :: v32i1 ; NumIntermediates = 2 ; return 2 ; } return TargetLowering :: getVectorTypeBreakdownForCallingConv ( Context , CC , VT , IntermediateVT , NumIntermediates , RegisterVT ) ; } </s>

Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts .


<s> static bool dimode_scalar_to_vector_candidate_p ( rtx_insn * insn ) { rtx def_set = single_set ( insn ) ; if ( ! def_set ) return false ; if ( has_non_address_hard_reg ( insn ) ) return false ; rtx src = SET_SRC ( def_set ) ; rtx dst = SET_DEST ( def_set ) ; if ( GET_CODE ( src ) == COMPARE ) return convertible_comparison_p ( insn ) ; if ( ( GET_MODE ( src ) != DImode && ! CONST_INT_P ( src ) ) || GET_MODE ( dst ) != DImode ) return false ; if ( ! REG_P ( dst ) && ! MEM_P ( dst ) ) return false ; switch ( GET_CODE ( src ) ) { case ASHIFTRT : if ( ! TARGET_AVX512VL ) return false ; case ASHIFT : case LSHIFTRT : if ( ! CONST_INT_P ( XEXP ( src , 1 ) ) || ! IN_RANGE ( INTVAL ( XEXP ( src , 1 ) ) , 0 , 63 ) ) return false ; break ; case PLUS : case MINUS : case IOR : case XOR : case AND : if ( ! REG_P ( XEXP ( src , 1 ) ) && ! MEM_P ( XEXP ( src , 1 ) ) && ! CONST_INT_P ( XEXP ( src , 1 ) ) ) return false ; if ( GET_MODE ( XEXP ( src , 1 ) ) != DImode && ! CONST_INT_P ( XEXP ( src , 1 ) ) ) return false ; break ; case NEG : case NOT : break ; case REG : return true ; case MEM : case CONST_INT : return REG_P ( dst ) ; default : return false ; } if ( ! REG_P ( XEXP ( src , 0 ) ) && ! MEM_P ( XEXP ( src , 0 ) ) && ! CONST_INT_P ( XEXP ( src , 0 ) ) && ( GET_CODE ( src ) != AND || GET_CODE ( XEXP ( src , 0 ) ) != NOT || ! REG_P ( XEXP ( XEXP ( src , 0 ) , 0 ) ) ) ) return false ; if ( GET_MODE ( XEXP ( src , 0 ) ) != DImode && ! CONST_INT_P ( XEXP ( src , 0 ) ) ) return false ; return true ; } </s>

The DImode version of scalar_to_vector_candidate_p .


<s> bool AAPAsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { Operands . push_back ( AAPOperand :: CreateToken ( Name , NameLoc ) ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( ParseOperand ( Operands ) ) return true ; while ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) && getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( ParseOperand ( Operands ) ) return true ; } return false ; } </s>

ParseInstruction - Parse one assembly instruction .


<s> static machine_mode frv_matching_accg_mode ( machine_mode mode ) { switch ( mode ) { case V4SImode : return V4QImode ; case DImode : return HImode ; case SImode : return QImode ; default : gcc_unreachable ( ) ; } } </s>

If an ACC rtx has mode MODE , return the mode that the matching ACCG should have .


<s> bool SITargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & CI , MachineFunction & MF , unsigned IntrID ) const { if ( const AMDGPU :: RsrcIntrinsic * RsrcIntr = AMDGPU :: lookupRsrcIntrinsic ( IntrID ) ) { AttributeList Attr = Intrinsic :: getAttributes ( CI . getContext ( ) , ( Intrinsic :: ID ) IntrID ) ; if ( Attr . hasFnAttribute ( Attribute :: ReadNone ) ) return false ; SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; if ( RsrcIntr -> IsImage ) { Info . ptrVal = MFI -> getImagePSV ( * MF . getSubtarget < GCNSubtarget > ( ) . getInstrInfo ( ) , CI . getArgOperand ( RsrcIntr -> RsrcArg ) ) ; Info . align = 0 ; } else { Info . ptrVal = MFI -> getBufferPSV ( * MF . getSubtarget < GCNSubtarget > ( ) . getInstrInfo ( ) , CI . getArgOperand ( RsrcIntr -> RsrcArg ) ) ; } Info . flags = MachineMemOperand :: MODereferenceable ; if ( Attr . hasFnAttribute ( Attribute :: ReadOnly ) ) { Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: getVT ( CI . getType ( ) , true ) ; if ( Info . memVT == MVT :: Other ) { Info . memVT = memVTFromAggregate ( CI . getType ( ) ) ; } Info . flags |= MachineMemOperand :: MOLoad ; } else if ( Attr . hasFnAttribute ( Attribute :: WriteOnly ) ) { Info . opc = ISD :: INTRINSIC_VOID ; Info . memVT = MVT :: getVT ( CI . getArgOperand ( 0 ) -> getType ( ) ) ; Info . flags |= MachineMemOperand :: MOStore ; } else { Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: getVT ( CI . getType ( ) ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MODereferenceable ; Info . flags |= MachineMemOperand :: MOVolatile ; } return true ; } switch ( IntrID ) { case Intrinsic :: amdgcn_atomic_inc : case Intrinsic :: amdgcn_atomic_dec : case Intrinsic :: amdgcn_ds_ordered_add : case Intrinsic :: amdgcn_ds_ordered_swap : case Intrinsic :: amdgcn_ds_fadd : case Intrinsic :: amdgcn_ds_fmin : case Intrinsic :: amdgcn_ds_fmax : { Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: getVT ( CI . getType ( ) ) ; Info . ptrVal = CI . getOperand ( 0 ) ; Info . align = 0 ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore ; const ConstantInt * Vol = dyn_cast < ConstantInt > ( CI . getOperand ( 4 ) ) ; if ( ! Vol || ! Vol -> isZero ( ) ) Info . flags |= MachineMemOperand :: MOVolatile ; return true ; } default : return false ; } } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AsmPrinter :: getAnalysisUsage ( AU ) ; AU . setPreservesAll ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void AMDGPUTTI :: getUnrollingPreferences ( Loop * L , UnrollingPreferences & UP ) const { for ( Loop :: block_iterator BI = L -> block_begin ( ) , BE = L -> block_end ( ) ; BI != BE ; ++ BI ) { BasicBlock * BB = * BI ; for ( BasicBlock :: const_iterator I = BB -> begin ( ) , E = BB -> end ( ) ; I != E ; ++ I ) { const GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( I ) ; if ( ! GEP ) continue ; const Value * Ptr = GEP -> getPointerOperand ( ) ; const AllocaInst * Alloca = dyn_cast < AllocaInst > ( GetUnderlyingObject ( Ptr ) ) ; if ( Alloca ) { UP . Threshold = 500 ; } } } } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> bool sh2a_function_vector_p ( tree func ) { if ( TREE_CODE ( func ) != FUNCTION_DECL ) return false ; for ( tree list = SH_ATTRIBUTES ( func ) ; list ; list = TREE_CHAIN ( list ) ) if ( is_attribute_p ( "function_vector" , get_attribute_name ( list ) ) ) return true ; return false ; } </s>

Returns true if FUNC has been assigned the attribute `` function_vector '' .


<s> bool PTXPassConfig :: addInstSelector ( ) { PM -> add ( createPTXISelDag ( getPTXTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static rtx_insn * conditionalize_block ( rtx_insn * first ) { rtx_insn * insn ; rtx br_pat ; rtx_insn * end_blk_1_br = 0 ; rtx_insn * end_blk_2_insn = 0 ; rtx_insn * start_blk_3_lab = 0 ; int cond ; int br_lab_num ; int blk_size = 0 ; if ( ! JUMP_P ( first ) || GET_CODE ( PATTERN ( first ) ) != SET || GET_CODE ( XEXP ( PATTERN ( first ) , 1 ) ) != IF_THEN_ELSE ) return NEXT_INSN ( first ) ; end_blk_1_br = first ; br_pat = PATTERN ( end_blk_1_br ) ; cond = ( GET_CODE ( XEXP ( XEXP ( br_pat , 1 ) , 0 ) ) == EQ ) ; if ( GET_CODE ( XEXP ( XEXP ( br_pat , 1 ) , 1 ) ) == LABEL_REF ) { br_lab_num = CODE_LABEL_NUMBER ( XEXP ( XEXP ( XEXP ( br_pat , 1 ) , 1 ) , 0 ) ) ; } else { cond = ( cond == 0 ) ; br_lab_num = CODE_LABEL_NUMBER ( XEXP ( XEXP ( XEXP ( br_pat , 1 ) , 2 ) , 0 ) ) ; } for ( insn = NEXT_INSN ( first ) ; insn ; insn = NEXT_INSN ( insn ) ) { enum rtx_code code ; code = GET_CODE ( insn ) ; if ( code == CODE_LABEL && CODE_LABEL_NUMBER ( insn ) == br_lab_num ) break ; if ( code != BARRIER && code != NOTE && ! is_cond_candidate ( insn ) ) return NEXT_INSN ( insn ) ; if ( code == JUMP_INSN || code == INSN ) { blk_size ++ ; end_blk_2_insn = insn ; } } if ( ! insn ) return insn ; if ( optimize > 1 && blk_size > 2 ) return insn ; start_blk_3_lab = insn ; for ( insn = NEXT_INSN ( end_blk_1_br ) ; insn != start_blk_3_lab ; insn = NEXT_INSN ( insn ) ) { rtx_insn * newinsn ; if ( insn -> deleted ( ) ) continue ; if ( ( newinsn = emit_new_cond_insn ( insn , cond ) ) ) { if ( end_blk_2_insn == insn ) end_blk_2_insn = newinsn ; insn = newinsn ; } } if ( LABEL_NUSES ( start_blk_3_lab ) == 1 ) { start_blk_3_lab = 0 ; } delete_insn ( end_blk_1_br ) ; if ( ! start_blk_3_lab ) return end_blk_2_insn ; return NEXT_INSN ( start_blk_3_lab ) ; } </s>

Attempt to change a basic block into a series of conditional insns . This works by taking the branch at the end of the 1st block and scanning for the end of the 2nd block . If all instructions in the 2nd block have cond . versions and the label at the start of block 3 is the same as the target from the branch at block 1 , then conditionalize all insn in block 2 using the inverse condition of the branch at block 1 . ( Note I 'm bending the definition of basic block here . ) e.g. , change : bt L2 < -- end of block 1 ( delete ) mov r7 , r8 addu r7,1 br L3 < -- end of block 2 L2 : ... < -- start of block 3 ( NUSES==1 ) L3 : ... to : movf r7 , r8 incf r7 bf L3 L3 : ... we can delete the L2 label if NUSES==1 and re-apply the optimization starting at the last instruction of block 2 . This may allow an entire if-then-else statement to be conditionalized . BRC


<s> static HOST_WIDE_INT spu_static_rtx_alignment ( machine_mode mode ) { return MAX ( GET_MODE_ALIGNMENT ( mode ) , 128 ) ; } </s>

Implement TARGET_STATIC_RTX_ALIGNMENT . Make all static objects 16-byte aligned . This allows us to assume they are also padded to 16 bytes , which means we can use a single load or store instruction to access them .


<s>
int
ConvergingVLIWScheduler
::
SchedulingCost
(
ReadyQueue
&
Q
,
SUnit
*
SU
,
SchedCandidate
&
Candidate
,
RegPressureDelta
&
Delta
,
bool
verbose
)
{
int
ResCount
=
1
;
if
(
!
SU
||
SU
->
isScheduled
)
return
ResCount
;
if
(
SU
->
isScheduleHigh
)
ResCount
+=
PriorityOne
;
if
(
Q
.
getID
(
)
==
TopQID
)
{
ResCount
+=
(
SU
->
getHeight
(
)
*
ScaleTwo
)
;
if
(
Top
.
ResourceModel
->
isResourceAvailable
(
SU
)
)
ResCount
<<=
FactorOne
;
}
else
{
ResCount
+=
(
SU
->
getDepth
(
)
*
ScaleTwo
)
;
if
(
Bot
.
ResourceModel
->
isResourceAvailable
(
SU
)
)
ResCount
<<=
FactorOne
;
}
unsigned
NumNodesBlocking
=
0
;
if
(
Q
.
getID
(
)
==
TopQID
)
{
for
(
SUnit
::
const_succ_iterator
I
=
SU
->
Succs
.
begin
(
)
,
E
=
SU
->
Succs
.
end
(
)
;
I
!=
E
;
++
I
)
if
(
getSingleUnscheduledPred
(
I
->
getSUnit
(
)
)
==
SU
)
++
NumNodesBlocking
;
}
else
{
for
(
SUnit
::
const_pred_iterator
I
=
SU
->
Preds
.
begin
(
)
,
E
=
SU
->
Preds
.
end
(
)
;
I
!=
E
;
++
I
)
if
(
getSingleUnscheduledSucc
(
I
->
getSUnit
(
)
)
==
SU
)
++
NumNodesBlocking
;
}
ResCount
+=
(
NumNodesBlocking
*
ScaleTwo
)
;
ResCount
-=
(
Delta
.
Excess
.
getUnitInc
(
)
*
PriorityTwo
)
;
ResCount
-=
(
Delta
.
CriticalMax
.
getUnitInc
(
)
*
PriorityTwo
)
;
DEBUG
(
if
(
verbose
)
dbgs
(
)
<<
" Total("
<<
ResCount
<<
")"
)
;
return
ResCount
;
}
</s>

Single point to compute overall scheduling cost .


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const X86Subtarget & Subtarget = MF . getSubtarget < X86Subtarget > ( ) ; bool HasSSE = Subtarget . hasSSE1 ( ) ; bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return CSR_64_TLS_Darwin_RegMask ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: X86_64_Win64 : return CSR_Win64_RegMask ; case CallingConv :: X86_64_SysV : return CSR_64_RegMask ; case CallingConv :: X86_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_32_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_32_AllRegs_SSE_RegMask ; return CSR_32_AllRegs_RegMask ; } default : break ; } if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_RegMask ; if ( Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) -> getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_64_SwiftError_RegMask ; return CSR_64_RegMask ; } return CSR_32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool X86FrameInfo :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> static void setup_incoming_varargs ( cumulative_args_t cum , const function_arg_info & , int * pretend_size , int no_rtl ) { rtx mem ; int i ; if ( no_rtl ) return ; for ( i = get_cumulative_args ( cum ) -> words + 1 ; i < max_arg_registers ; i ++ ) { mem = gen_rtx_MEM ( Pmode , plus_constant ( Pmode , arg_pointer_rtx , ( i * UNITS_PER_WORD ) ) ) ; emit_move_insn ( mem , gen_rtx_REG ( Pmode , i ) ) ; } * pretend_size = 0 ; } </s>

Perform any needed actions needed for a function that is receiving a variable number of arguments . CUM is as above . MODE and TYPE are the mode and type of the current parameter . PRETEND_SIZE is a variable that should be set to the amount of stack that must be pushed by the prolog to pretend that our caller pushed it . Normally , this macro will push all remaining incoming registers on the stack and set PRETEND_SIZE to the length of the registers pushed .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < ReachingDefAnalysis > ( ) ; AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> unsigned getNumFixupKinds ( ) const { return OR1K :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> bool AArch64AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , const char * ExtraCode , raw_ostream & O ) { const MachineOperand & MO = MI -> getOperand ( OpNum ) ; if ( ! AsmPrinter :: PrintAsmOperand ( MI , OpNum , ExtraCode , O ) ) return false ; if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'w' : case 'x' : if ( MO . isReg ( ) ) return printAsmMRegister ( MO , ExtraCode [ 0 ] , O ) ; if ( MO . isImm ( ) && MO . getImm ( ) == 0 ) { unsigned Reg = ExtraCode [ 0 ] == 'w' ? AArch64 :: WZR : AArch64 :: XZR ; O << AArch64InstPrinter :: getRegisterName ( Reg ) ; return false ; } printOperand ( MI , OpNum , O ) ; return false ; case 'b' : case 'h' : case 's' : case 'd' : case 'q' : case 'z' : if ( MO . isReg ( ) ) { const TargetRegisterClass * RC ; switch ( ExtraCode [ 0 ] ) { case 'b' : RC = & AArch64 :: FPR8RegClass ; break ; case 'h' : RC = & AArch64 :: FPR16RegClass ; break ; case 's' : RC = & AArch64 :: FPR32RegClass ; break ; case 'd' : RC = & AArch64 :: FPR64RegClass ; break ; case 'q' : RC = & AArch64 :: FPR128RegClass ; break ; case 'z' : RC = & AArch64 :: ZPRRegClass ; break ; default : return true ; } return printAsmRegInClass ( MO , RC , AArch64 :: NoRegAltName , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } } if ( MO . isReg ( ) ) { Register Reg = MO . getReg ( ) ; if ( AArch64 :: GPR32allRegClass . contains ( Reg ) || AArch64 :: GPR64allRegClass . contains ( Reg ) ) return printAsmMRegister ( MO , 'x' , O ) ; unsigned AltName = AArch64 :: NoRegAltName ; const TargetRegisterClass * RegClass ; if ( AArch64 :: ZPRRegClass . contains ( Reg ) ) { RegClass = & AArch64 :: ZPRRegClass ; } else if ( AArch64 :: PPRRegClass . contains ( Reg ) ) { RegClass = & AArch64 :: PPRRegClass ; } else { RegClass = & AArch64 :: FPR128RegClass ; AltName = AArch64 :: vreg ; } return printAsmRegInClass ( MO , RegClass , AltName , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


Initialize register TARGET from the elements in PARALLEL rtx VALS .


<s> bool m68k_legitimate_base_reg_p ( rtx x , bool strict_p ) { if ( ! strict_p && GET_CODE ( x ) == SUBREG ) x = SUBREG_REG ( x ) ; return ( REG_P ( x ) && ( strict_p ? REGNO_OK_FOR_BASE_P ( REGNO ( x ) ) : REGNO_OK_FOR_BASE_NONSTRICT_P ( REGNO ( x ) ) ) ) ; } </s>

Return true if X is a legitimate base register . STRICT_P says whether we need strict checking .


<s> enum machine_mode visium_select_cc_mode ( enum rtx_code code , rtx op0 , rtx op1 ) { if ( GET_MODE_CLASS ( GET_MODE ( op0 ) ) == MODE_FLOAT ) { switch ( code ) { case EQ : case NE : case ORDERED : case UNORDERED : case UNLT : case UNLE : case UNGT : case UNGE : return CCFPmode ; case LT : case LE : case GT : case GE : return CCFPEmode ; case UNEQ : case LTGT : default : gcc_unreachable ( ) ; } } if ( op1 == constm1_rtx ) return CCCmode ; if ( ( code == LTU || code == GEU ) && GET_CODE ( op0 ) == PLUS && rtx_equal_p ( XEXP ( op0 , 0 ) , op1 ) ) return CCCmode ; if ( ( code == EQ || code == NE ) && GET_CODE ( op1 ) == UNSPEC && ( XINT ( op1 , 1 ) == UNSPEC_ADDV || XINT ( op1 , 1 ) == UNSPEC_SUBV || XINT ( op1 , 1 ) == UNSPEC_NEGV ) ) return CCVmode ; if ( op1 != const0_rtx ) return CCmode ; switch ( GET_CODE ( op0 ) ) { case PLUS : case MINUS : case NEG : case ASHIFT : case LTU : case LT : return CCNZmode ; case ZERO_EXTRACT : return CCCmode ; case CONST_INT : gcc_assert ( op0 == constm1_rtx ) ; case REG : case AND : case IOR : case XOR : case NOT : case ASHIFTRT : case LSHIFTRT : case TRUNCATE : case SIGN_EXTEND : return CCmode ; default : gcc_unreachable ( ) ; } } </s>

Given a comparison code ( EQ , NE , etc . ) and the operands of a COMPARE , return the mode to be used for the comparison .


<s>
int
PPCTTIImpl
::
getArithmeticInstrCost
(
unsigned
Opcode
,
Type
*
Ty
,
TTI
::
OperandValueKind
Op1Info
,
TTI
::
OperandValueKind
Op2Info
,
TTI
::
OperandValueProperties
Opd1PropInfo
,
TTI
::
OperandValueProperties
Opd2PropInfo
,
ArrayRef
<
const
Value
*
>
Args
)
{
assert
(
TLI
->
InstructionOpcodeToISD
(
Opcode
)
&&
"Invalid opcode"
)
;
return
BaseT
::
getArithmeticInstrCost
(
Opcode
,
Ty
,
Op1Info
,
Op2Info
,
Opd1PropInfo
,
Opd2PropInfo
)
;
}
</s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> bool ix86_expand_fp_vcond ( rtx operands [ ] ) { enum rtx_code code = GET_CODE ( operands [ 3 ] ) ; rtx cmp ; code = ix86_prepare_sse_fp_compare_args ( operands [ 0 ] , code , & operands [ 4 ] , & operands [ 5 ] ) ; if ( code == UNKNOWN ) return false ; if ( ix86_expand_sse_fp_minmax ( operands [ 0 ] , code , operands [ 4 ] , operands [ 5 ] , operands [ 1 ] , operands [ 2 ] ) ) return true ; cmp = ix86_expand_sse_cmp ( operands [ 0 ] , code , operands [ 4 ] , operands [ 5 ] , operands [ 1 ] , operands [ 2 ] ) ; ix86_expand_sse_movcc ( operands [ 0 ] , cmp , operands [ 1 ] , operands [ 2 ] ) ; return true ; } </s>

Expand a floating-point vector conditional move ; a vcond operation rather than a movcc operation .


<s> void ARMBaseRegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const DebugLoc & dl , unsigned DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , unsigned PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: LDRcp ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( 0 ) . add ( predOps ( Pred , PredReg ) ) . setMIFlags ( MIFlags ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s>
StringRef
getPassName
(
)
const
override
{
return
"SI Optimize VGPR LiveRange"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool X86TargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { auto Attr = CI -> getParent ( ) -> getParent ( ) -> getFnAttribute ( "disable-tail-calls" ) ; if ( ! CI -> isTailCall ( ) || Attr . getValueAsString ( ) == "true" ) return false ; ImmutableCallSite CS ( CI ) ; CallingConv :: ID CalleeCC = CS . getCallingConv ( ) ; if ( ! mayTailCallThisCC ( CalleeCC , Subtarget . isTargetWin64 ( ) ) ) return false ; return true ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> BitVector LoongArchRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const LoongArchFrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , LoongArch :: R0 ) ; markSuperRegs ( Reserved , LoongArch :: R2 ) ; markSuperRegs ( Reserved , LoongArch :: R3 ) ; markSuperRegs ( Reserved , LoongArch :: R21 ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , LoongArch :: R22 ) ; if ( TFI -> hasBP ( MF ) ) markSuperRegs ( Reserved , LoongArchABI :: getBPReg ( ) ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> rtx mips_strip_unspec_address ( rtx op ) { rtx base , offset ; split_const ( op , & base , & offset ) ; if ( UNSPEC_ADDRESS_P ( base ) ) op = plus_constant ( Pmode , UNSPEC_ADDRESS ( base ) , INTVAL ( offset ) ) ; return op ; } </s>

If OP is an UNSPEC address , return the address to which it refers , otherwise return OP itself .


<s> void SSEDomainFixPass :: enterBasicBlock ( ) { for ( MachineBasicBlock :: livein_iterator i = MBB -> livein_begin ( ) , e = MBB -> livein_end ( ) ; i != e ; ++ i ) { int rx = RegIndex ( * i ) ; if ( rx < 0 ) continue ; for ( MachineBasicBlock :: const_pred_iterator pi = MBB -> pred_begin ( ) , pe = MBB -> pred_end ( ) ; pi != pe ; ++ pi ) { LiveOutMap :: const_iterator fi = LiveOuts . find ( * pi ) ; if ( fi == LiveOuts . end ( ) ) continue ; DomainValue * pdv = fi -> second [ rx ] ; if ( ! pdv ) continue ; if ( ! LiveRegs || ! LiveRegs [ rx ] ) { SetLiveReg ( rx , pdv ) ; continue ; } if ( LiveRegs [ rx ] -> isCollapsed ( ) ) { unsigned domain = LiveRegs [ rx ] -> getFirstDomain ( ) ; if ( ! pdv -> isCollapsed ( ) && pdv -> hasDomain ( domain ) ) Collapse ( pdv , domain ) ; continue ; } if ( ! pdv -> isCollapsed ( ) ) Merge ( LiveRegs [ rx ] , pdv ) ; else Force ( rx , pdv -> getFirstDomain ( ) ) ; } } } </s>

Start tracking liveness from the begin of basic block MBB .


"JIT relocation model must be set to static or default!"

runOnMachineFunction - Emit the function body .


<s> rtx ix86_zero_extend_to_Pmode ( rtx exp ) { return force_reg ( Pmode , convert_to_mode ( Pmode , exp , 1 ) ) ; } </s>

Zero extend possibly SImode EXP to Pmode register .


<s> int first_reg_to_save ( void ) { int first_reg ; for ( first_reg = 13 ; first_reg <= 31 ; first_reg ++ ) if ( save_reg_p ( first_reg ) ) break ; return first_reg ; } </s>

Return the first register that is required to be saved . 16 if none .


<s> virtual BitVector getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; return Reserved ; } </s>


<s> virtual const SparcRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


"\nnew fndecl target specific options:\n"

"\nold fndecl target specific options:\n"

Establish appropriate back-end context for processing the function FNDECL . The argument might be NULL to indicate processing at top level , outside of any function scope .


<s> unsigned X86InstrInfo :: isStoreToStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { unsigned Dummy ; if ( isFrameStoreOpcode ( MI . getOpcode ( ) , Dummy ) ) { unsigned Reg ; if ( ( Reg = isStoreToStackSlot ( MI , FrameIndex ) ) ) return Reg ; SmallVector < const MachineMemOperand * , 1 > Accesses ; if ( hasStoreToStackSlot ( MI , Accesses ) ) { FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) -> getFrameIndex ( ) ; return 1 ; } } return 0 ; } </s>

isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s> bool HexagonCopyToCombine :: runOnMachineFunction ( MachineFunction & MF ) { if ( IsCombinesDisabled ) return false ; bool HasChanged = false ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; TII = static_cast < const HexagonInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; ShouldCombineAggressively = MF . getTarget ( ) . getOptLevel ( ) <= CodeGenOpt :: Default ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( * BI ) ; for ( MachineBasicBlock :: iterator MI = BI -> begin ( ) , End = BI -> end ( ) ; MI != End ; ) { MachineInstr * I1 = MI ++ ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( I1 ) ) continue ; if ( ! isCombinableInstType ( I1 , TII , ShouldCombineAggressively ) ) continue ; bool DoInsertAtI1 = false ; MachineInstr * I2 = findPairable ( I1 , DoInsertAtI1 ) ; if ( I2 ) { HasChanged = true ; combine ( I1 , I2 , MI , DoInsertAtI1 ) ; } } } return HasChanged ; } </s>


<s> static bool aarch64_vector_mode_supported_p ( machine_mode mode ) { unsigned int vec_flags = aarch64_classify_vector_mode ( mode ) ; return vec_flags != 0 && ( vec_flags & VEC_STRUCT ) == 0 ; } </s>

Implements target hook vector_mode_supported_p .


"unrecognized interrupt vector argument of %qE attribute"

"numeric argument of %qE attribute must be in range 0..63"

"argument of %qE attribute is not a string constant or number"

"%qE attribute only applies to functions"

"critical attribute has no effect on interrupt functions"

"critical functions cannot be reentrant"

"reentrant functions cannot be critical"


"getBranchTarget21OpValue expects only expressions or immediates"

getBranchTarget21OpValue - Return binary encoding of the branch target operand .


<s> virtual bool addInstSelector ( ) { addPass ( createTGSIISelDag ( getTGSITargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool XCoreAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .