<s> bool aarch64_is_extend_from_extract ( scalar_int_mode mode , rtx mult_imm , rtx extract_imm ) { HOST_WIDE_INT mult_val , extract_val ; if ( ! CONST_INT_P ( mult_imm ) || ! CONST_INT_P ( extract_imm ) ) return false ; mult_val = INTVAL ( mult_imm ) ; extract_val = INTVAL ( extract_imm ) ; if ( extract_val > 8 && extract_val < GET_MODE_BITSIZE ( mode ) && exact_log2 ( extract_val & ~ 7 ) > 0 && ( extract_val & 7 ) <= 4 && mult_val == ( 1 << ( extract_val & 7 ) ) ) return true ; return false ; } </s>

Return true if the offsets to a zero/sign-extract operation represent an expression that matches an extend operation . The operands represent the paramters from ( extract : MODE ( mult ( reg ) ( MULT_IMM ) ) ( EXTRACT_IMM ) ( const_int 0 ) ) .


<s> bool SparcTargetMachine :: addPreEmitPass ( PassManagerBase & PM , bool Fast ) { PM . add ( createSparcFPMoverPass ( * this ) ) ; PM . add ( createSparcDelaySlotFillerPass ( * this ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void emitFill ( const MCExpr & NumBytes , uint64_t FillValue , SMLoc Loc ) override { emitDataMappingSymbol ( ) ; MCObjectStreamer :: emitFill ( NumBytes , FillValue , Loc ) ; } </s>

Emit Size bytes worth of the value specified by FillValue .


<s> void emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const override { } </s>


<s> bool csky_split_xor ( rtx * operands ) { HOST_WIDE_INT mask = INTVAL ( operands [ 2 ] ) ; if ( mask == 0 ) { emit_move_insn ( operands [ 0 ] , operands [ 1 ] ) ; return true ; } if ( mask == - 1 ) { if ( CSKY_ISA_FEATURE ( E2 ) ) emit_insn ( gen_cskyv2_one_cmplsi2 ( operands [ 0 ] , operands [ 1 ] ) ) ; else { emit_move_insn ( operands [ 0 ] , operands [ 1 ] ) ; emit_insn ( gen_ck801_one_cmplsi2 ( operands [ 0 ] , operands [ 0 ] ) ) ; } return true ; } if ( CSKY_ISA_FEATURE ( E2 ) && csky_arith_O_operand ( operands [ 2 ] , SImode ) ) return false ; if ( reload_completed ) { emit_move_insn ( operands [ 0 ] , operands [ 2 ] ) ; operands [ 2 ] = operands [ 1 ] ; operands [ 1 ] = operands [ 0 ] ; } else operands [ 2 ] = copy_to_mode_reg ( SImode , operands [ 2 ] ) ; return false ; } </s>

Split operands for an XOR expression when OPERANDS [ 2 ] is a constant . Note operands [ 0 ] is marked earlyclobber in this case and can be overwritten . Return true if `` DONE '' , false otherwise .


<s> unsigned getMaxSupportedInterleaveFactor ( ) const override { return 6 ; } </s>

Get the maximum supported factor for interleaved memory accesses .


<s> static unsigned int c6x_function_arg_boundary ( machine_mode mode , const_tree type ) { unsigned int boundary = type ? TYPE_ALIGN ( type ) : GET_MODE_BITSIZE ( mode ) ; if ( boundary > BITS_PER_WORD ) return 2 * BITS_PER_WORD ; if ( mode == BLKmode ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; if ( size > 4 ) return 2 * BITS_PER_WORD ; if ( boundary < BITS_PER_WORD ) { if ( size >= 3 ) return BITS_PER_WORD ; if ( size >= 2 ) return 2 * BITS_PER_UNIT ; } } return boundary ; } </s>


<s> static bool arm_default_short_enums ( void ) { return ARM_DEFAULT_SHORT_ENUMS ; } </s>

AAPCS based ABIs use short enums by default .


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { unsigned Offset = Fixup . getOffset ( ) ; MCFixupKind Kind = Fixup . getKind ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { Data [ Offset + i ] = ( uint8_t ) ( ( Value >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( EnableSVEIntrinsicOpts && TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( createSVEIntrinsicOptsPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( SimplifyCFGOptions ( ) . forwardSwitchCondToPhi ( true ) . convertSwitchRangeToICmp ( true ) . convertSwitchToLookupTable ( true ) . needCanonicalLoops ( false ) . hoistCommonInsts ( true ) . sinkCommonInsts ( true ) ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; addPass ( createAArch64StackTaggingPass ( TM -> getOptLevel ( ) == CodeGenOpt :: None ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedLoadCombinePass ( ) ) ; addPass ( createInterleavedAccessPass ( ) ) ; } if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardCheckPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> void VideoCore4InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = * MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; BuildMI ( MBB , I , DL , get ( VideoCore4 :: MEM32_LD_LI ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> SDValue ARMTargetLowering :: PerformCMOVCombine ( SDNode * N , SelectionDAG & DAG ) const { SDValue Cmp = N -> getOperand ( 4 ) ; if ( Cmp . getOpcode ( ) != ARMISD :: CMPZ ) return SDValue ( ) ; EVT VT = N -> getValueType ( 0 ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue LHS = Cmp . getOperand ( 0 ) ; SDValue RHS = Cmp . getOperand ( 1 ) ; SDValue FalseVal = N -> getOperand ( 0 ) ; SDValue TrueVal = N -> getOperand ( 1 ) ; SDValue ARMcc = N -> getOperand ( 2 ) ; ARMCC :: CondCodes CC = ( ARMCC :: CondCodes ) cast < ConstantSDNode > ( ARMcc ) -> getZExtValue ( ) ; SDValue Res ; if ( CC == ARMCC :: NE && FalseVal == RHS && FalseVal != LHS ) { Res = DAG . getNode ( ARMISD :: CMOV , dl , VT , LHS , TrueVal , ARMcc , N -> getOperand ( 3 ) , Cmp ) ; } else if ( CC == ARMCC :: EQ && TrueVal == RHS ) { SDValue ARMcc ; SDValue NewCmp = getARMCmp ( LHS , RHS , ISD :: SETNE , ARMcc , DAG , dl ) ; Res = DAG . getNode ( ARMISD :: CMOV , dl , VT , LHS , FalseVal , ARMcc , N -> getOperand ( 3 ) , NewCmp ) ; } if ( Res . getNode ( ) ) { APInt KnownZero , KnownOne ; DAG . ComputeMaskedBits ( SDValue ( N , 0 ) , KnownZero , KnownOne ) ; if ( KnownZero == 0xfffffffe ) Res = DAG . getNode ( ISD :: AssertZext , dl , MVT :: i32 , Res , DAG . getValueType ( MVT :: i1 ) ) ; else if ( KnownZero == 0xffffff00 ) Res = DAG . getNode ( ISD :: AssertZext , dl , MVT :: i32 , Res , DAG . getValueType ( MVT :: i8 ) ) ; else if ( KnownZero == 0xffff0000 ) Res = DAG . getNode ( ISD :: AssertZext , dl , MVT :: i32 , Res , DAG . getValueType ( MVT :: i16 ) ) ; } return Res ; } </s>

PerformCMOVCombine - Target-specific DAG combining for ARMISD : :CMOV .


<s>
bool
AArch64InstrInfo
::
isLdStPairSuppressed
(
const
MachineInstr
*
MI
)
const
{
static_assert
(
MOSuppressPair
<
(
1
<<
MachineMemOperand
::
MOTargetNumBits
)
,
"Too many target MO flags"
)
;
for
(
auto
*
MM
:
MI
->
memoperands
(
)
)
{
if
(
MM
->
getFlags
(
)
&
(
MOSuppressPair
<<
MachineMemOperand
::
MOTargetStartBit
)
)
{
return
true
;
}
}
return
false
;
}
</s>

Return true if pairing the given load or store is hinted to be unprofitable .


<s> static void ix86_option_override ( void ) { ix86_option_override_internal ( true , & global_options , & global_options_set ) ; } </s>

Implement the TARGET_OPTION_OVERRIDE hook .


<s> bool AAPRegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> void VEInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { unsigned AltIdx = VE :: AsmName ; OS << '%' << getRegisterName ( RegNo , AltIdx ) ; } </s>


<s>
bool
fixupNeedsRelaxation
(
MCFixup
const
&
,
uint64_t
,
MCRelaxableFragment
const
*
,
MCAsmLayout
const
&
)
const
override
{
llvm_unreachable
(
"fixupNeedsRelaxation() unimplemented"
)
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> unsigned char AArch64Subtarget :: ClassifyGlobalReference ( const GlobalValue * GV , const TargetMachine & TM ) const { bool isDecl = GV -> hasAvailableExternallyLinkage ( ) ; if ( GV -> isDeclaration ( ) && ! GV -> isMaterializable ( ) ) isDecl = true ; if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) ) return AArch64II :: MO_GOT ; if ( TM . getCodeModel ( ) == CodeModel :: Small && GV -> isWeakForLinker ( ) && isDecl ) { if ( TM . getRelocationModel ( ) == Reloc :: Static ) return AArch64II :: MO_CONSTPOOL ; else return AArch64II :: MO_GOT ; } if ( TM . getRelocationModel ( ) != Reloc :: Static && GV -> hasDefaultVisibility ( ) ) { if ( isTargetMachO ( ) ) return ( isDecl || GV -> isWeakForLinker ( ) ) ? AArch64II :: MO_GOT : AArch64II :: MO_NO_FLAG ; else return GV -> hasLocalLinkage ( ) ? AArch64II :: MO_NO_FLAG : AArch64II :: MO_GOT ; } return AArch64II :: MO_NO_FLAG ; } </s>

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be referenced for the current subtarget .


<s> unsigned HexagonTTIImpl :: getCacheLineSize ( ) const { return getST ( ) -> getL1CacheLineSize ( ) ; } </s>

Return the target cache line size in bytes .


<s> static HOST_WIDE_INT spu_function_arg_offset ( machine_mode mode , const_tree type ) { if ( type && INTEGRAL_TYPE_P ( type ) && GET_MODE_SIZE ( mode ) < 4 ) return 4 - GET_MODE_SIZE ( mode ) ; return 0 ; } </s>

Implement TARGET_FUNCTION_ARG_OFFSET . The SPU ABI wants 32/64-bit types at offset 0 in the quad-word on the stack . 8/16-bit types should be at offsets 3/2 respectively .


<s> bool RISCVInstrInfo :: isAsCheapAsAMove ( const MachineInstr & MI ) const { const unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : break ; case RISCV :: ADDI : case RISCV :: ORI : case RISCV :: XORI : return ( MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 1 ) . getReg ( ) == RISCV :: X0 ) ; } return MI . isAsCheapAsAMove ( ) ; } </s>

Return true if the instruction is as cheap as a move instruction .


<s> unsigned AArch64TTI :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , OperandValueKind Opd1Info , OperandValueKind Opd2Info , OperandValueProperties Opd1PropInfo , OperandValueProperties Opd2PropInfo ) const { std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Ty ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( ISD == ISD :: SDIV && Opd2Info == TargetTransformInfo :: OK_UniformConstantValue && Opd2PropInfo == TargetTransformInfo :: OP_PowerOf2 ) { unsigned Cost = getArithmeticInstrCost ( Instruction :: Add , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Sub , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Select , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: AShr , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return Cost ; } switch ( ISD ) { default : return TargetTransformInfo :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: ADD : case ISD :: MUL : case ISD :: XOR : case ISD :: OR : case ISD :: AND : return 1 * LT . first ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .

AArch64 AArch64 ISD::SDIV ISD::ADD ISD::MUL ISD::XOR ISD::OR ISD::AND 1


<s> static unsigned int h8300_asm_insn_count ( const char * template ) { unsigned int count = 1 ; for ( ; * template ; template ++ ) if ( * template == '\n' ) count ++ ; return count ; } </s>

Count the number of assembly instructions in a string TEMPLATE .


<s> Register MipsOutgoingValueHandler :: getStackAddress ( const CCValAssign & VA , MachineMemOperand * & MMO ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; const TargetFrameLowering * TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; LLT p0 = LLT :: pointer ( 0 , 32 ) ; LLT s32 = LLT :: scalar ( 32 ) ; auto SPReg = MIRBuilder . buildCopy ( p0 , Register ( Mips :: SP ) ) ; unsigned Offset = VA . getLocMemOffset ( ) ; auto OffsetReg = MIRBuilder . buildConstant ( s32 , Offset ) ; auto AddrReg = MIRBuilder . buildPtrAdd ( p0 , SPReg , OffsetReg ) ; MachinePointerInfo MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ; unsigned Size = alignTo ( VA . getValVT ( ) . getSizeInBits ( ) , 8 ) / 8 ; Align Alignment = commonAlignment ( TFL -> getStackAlign ( ) , Offset ) ; MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , Alignment ) ; return AddrReg . getReg ( 0 ) ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s>
bool
HexagonPacketizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
const
TargetInstrInfo
*
TII
=
Fn
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
MachineLoopInfo
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
const
MachineBranchProbabilityInfo
*
MBPI
=
&
getAnalysis
<
MachineBranchProbabilityInfo
>
(
)
;
HexagonPacketizerList
Packetizer
(
Fn
,
MLI
,
MBPI
)
;
assert
(
Packetizer
.
getResourceTracker
(
)
&&
"Empty DFA table!"
)
;
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
MachineBasicBlock
::
iterator
End
=
MBB
->
end
(
)
;
MachineBasicBlock
::
iterator
MI
=
MBB
->
begin
(
)
;
while
(
MI
!=
End
)
{
if
(
MI
->
isKill
(
)
)
{
MachineBasicBlock
::
iterator
DeleteMI
=
MI
;
++
MI
;
MBB
->
erase
(
DeleteMI
)
;
End
=
MBB
->
end
(
)
;
continue
;
}
++
MI
;
}
}
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
unsigned
RemainingCount
=
MBB
->
size
(
)
;
for
(
MachineBasicBlock
::
iterator
RegionEnd
=
MBB
->
end
(
)
;
RegionEnd
!=
MBB
->
begin
(
)
;
)
{
MachineBasicBlock
::
iterator
I
=
RegionEnd
;
for
(
;
I
!=
MBB
->
begin
(
)
;
I
,
RemainingCount
)
{
if
(
TII
->
isSchedulingBoundary
(
std
::
prev
(
I
)
,
&
*
MBB
,
Fn
)
)
break
;
}
I
=
MBB
->
begin
(
)
;
if
(
I
==
RegionEnd
)
{
RegionEnd
=
std
::
prev
(
RegionEnd
)
;
RemainingCount
;
continue
;
}
if
(
I
==
std
::
prev
(
RegionEnd
)
)
{
RegionEnd
=
std
::
prev
(
RegionEnd
)
;
continue
;
}
Packetizer
.
PacketizeMIs
(
&
*
MBB
,
I
,
RegionEnd
)
;
RegionEnd
=
I
;
}
}
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .

Hexagon
Hexagon
Hexagon
"Empty DFA table!"


<s>
void
assignValueToAddress
(
Register
ValVReg
,
Register
Addr
,
uint64_t
Size
,
MachinePointerInfo
&
MPO
,
CCValAssign
&
VA
)
override
{
assert
(
(
Size
==
1
||
Size
==
2
||
Size
==
4
||
Size
==
8
)
&&
"Unsupported size"
)
;
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
SExt
||
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExt
)
{
Size
=
4
;
assert
(
MRI
.
getType
(
ValVReg
)
.
isScalar
(
)
&&
"Only scalars supported atm"
)
;
auto
LoadVReg
=
buildLoad
(
LLT
::
scalar
(
32
)
,
Addr
,
Size
,
1
,
MPO
)
;
MIRBuilder
.
buildTrunc
(
ValVReg
,
LoadVReg
)
;
}
else
{
buildLoad
(
ValVReg
,
Addr
,
Size
,
1
,
MPO
)
;
}
}
</s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> static bool bfin_assemble_integer ( rtx value , unsigned int size , int aligned_p ) { if ( TARGET_FDPIC && size == UNITS_PER_WORD ) { if ( GET_CODE ( value ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( value ) ) { fputs ( "\t.picptr\tfuncdesc(" , asm_out_file ) ; output_addr_const ( asm_out_file , value ) ; fputs ( ")\n" , asm_out_file ) ; return true ; } if ( ! aligned_p ) { assemble_integer_with_op ( "\t.4byte\t" , value ) ; return true ; } } return default_assemble_integer ( value , size , aligned_p ) ; } </s>

Implementation of TARGET_ASM_INTEGER . When using FD-PIC , we need to tell the assembler to generate pointers to function descriptors in some cases .


<s>
const
char
*
output_move64
(
rtx
dst
,
rtx
src
)
{
if
(
push_operand
(
dst
,
GET_MODE
(
dst
)
)
)
{
if
(
reg_overlap_mentioned_p
(
stack_pointer_rtx
,
src
)
)
{
return
"pushl	@%H0,%T1\n\tpushl	@%H0,%T1"
;
}
return
"pushl	@%H0,%T1\n\tpushl	@%H0,%S1"
;
}
if
(
whichway
(
dst
,
src
)
<
0
)
return
"$ldl	%T0,%T1\n\t$ldl	%S0,%S1 ! di a"
;
else
return
"$ldl	%S0,%S1\n\t$ldl	%T0,%T1 ! di b"
;
}
</s>

Return string to move 64 bit operand without trampling arguments .


<s>
void
ARCTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
LLVM_DEBUG
(
dbgs
(
)
<<
"[ARC-ISEL] ReplaceNodeResults "
)
;
LLVM_DEBUG
(
N
->
dump
(
&
DAG
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"; use_count="
<<
N
->
use_size
(
)
<<
"\n"
)
;
switch
(
N
->
getOpcode
(
)
)
{
case
ISD
::
READCYCLECOUNTER
:
if
(
N
->
getValueType
(
0
)
==
MVT
::
i64
)
{
SDValue
V
=
DAG
.
getNode
(
ISD
::
READCYCLECOUNTER
,
SDLoc
(
N
)
,
DAG
.
getVTList
(
MVT
::
i32
,
MVT
::
Other
)
,
N
->
getOperand
(
0
)
)
;
SDValue
Op
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
SDLoc
(
N
)
,
MVT
::
i64
,
V
)
;
Results
.
push_back
(
Op
)
;
Results
.
push_back
(
V
.
getValue
(
1
)
)
;
}
break
;
default
:
break
;
}
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s>
bool
PPCCallLowering
::
lowerReturn
(
MachineIRBuilder
&
MIRBuilder
,
const
Value
*
Val
,
ArrayRef
<
Register
>
VRegs
,
FunctionLoweringInfo
&
FLI
,
Register
SwiftErrorVReg
)
const
{
assert
(
(
(
Val
&&
!
VRegs
.
empty
(
)
)
||
(
!
Val
&&
VRegs
.
empty
(
)
)
)
&&
"Return value without a vreg"
)
;
if
(
VRegs
.
size
(
)
>
0
)
return
false
;
MIRBuilder
.
buildInstr
(
PPC
::
BLR8
)
;
return
true
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> MachineInstr * front ( ) const { return Uses . top ( ) ; } </s>

front - Get the first character in the string .


<s>
bool
SystemZInstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugInstr
(
)
)
continue
;
if
(
!
isUnpredicatedTerminator
(
*
I
)
)
break
;
if
(
!
I
->
isBranch
(
)
)
return
true
;
SystemZII
::
Branch
Branch
(
getBranchInfo
(
*
I
)
)
;
if
(
!
Branch
.
hasMBBTarget
(
)
)
return
true
;
if
(
Branch
.
Type
!=
SystemZII
::
BranchNormal
)
return
true
;
if
(
Branch
.
CCMask
==
SystemZ
::
CCMASK_ANY
)
{
if
(
!
AllowModify
)
{
TBB
=
Branch
.
getMBBTarget
(
)
;
continue
;
}
while
(
std
::
next
(
I
)
!=
MBB
.
end
(
)
)
std
::
next
(
I
)
->
eraseFromParent
(
)
;
Cond
.
clear
(
)
;
FBB
=
nullptr
;
if
(
MBB
.
isLayoutSuccessor
(
Branch
.
getMBBTarget
(
)
)
)
{
TBB
=
nullptr
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
continue
;
}
TBB
=
Branch
.
getMBBTarget
(
)
;
continue
;
}
if
(
Cond
.
empty
(
)
)
{
FBB
=
TBB
;
TBB
=
Branch
.
getMBBTarget
(
)
;
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
Branch
.
CCValid
)
)
;
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
Branch
.
CCMask
)
)
;
continue
;
}
assert
(
Cond
.
size
(
)
==
2
&&
TBB
&&
"Should have seen a conditional branch"
)
;
if
(
TBB
!=
Branch
.
getMBBTarget
(
)
)
return
true
;
unsigned
OldCCValid
=
Cond
[
0
]
.
getImm
(
)
;
unsigned
OldCCMask
=
Cond
[
1
]
.
getImm
(
)
;
if
(
OldCCValid
==
Branch
.
CCValid
&&
OldCCMask
==
Branch
.
CCMask
)
continue
;
return
false
;
}
return
false
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


"getBranchTargetOpValue expects only expressions or immediates"

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s> bool MipsSubtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = TargetSubtargetInfo :: ANTIDEP_NONE ; CriticalPathRCs . clear ( ) ; CriticalPathRCs . push_back ( hasMips64 ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ) ; return OptLevel >= CodeGenOpt :: Aggressive ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; Reserved . set ( PPC :: R0 ) ; Reserved . set ( PPC :: R1 ) ; Reserved . set ( PPC :: LR ) ; Reserved . set ( PPC :: LR8 ) ; Reserved . set ( PPC :: RM ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: R2 ) ; Reserved . set ( PPC :: R13 ) ; } if ( Subtarget . isDarwinABI ( ) ) { Reserved . set ( PPC :: R2 ) ; } if ( Subtarget . isPPC64 ( ) ) { Reserved . set ( PPC :: R13 ) ; Reserved . set ( PPC :: R31 ) ; if ( ! requiresRegisterScavenging ( MF ) ) Reserved . set ( PPC :: R0 ) ; Reserved . set ( PPC :: X0 ) ; Reserved . set ( PPC :: X1 ) ; Reserved . set ( PPC :: X13 ) ; Reserved . set ( PPC :: X31 ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: X2 ) ; } if ( Subtarget . isDarwinABI ( ) ) { Reserved . set ( PPC :: X2 ) ; } } if ( TFI -> hasFP ( MF ) ) Reserved . set ( PPC :: R31 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static unsigned getBasePtrIndex ( const MemSDNode * N ) { switch ( N -> getOpcode ( ) ) { case ISD :: STORE : case ISD :: INTRINSIC_W_CHAIN : case ISD :: INTRINSIC_VOID : return 2 ; default : return 1 ; } } </s>

The index into the associate statepoint 's argument list which contains the base pointer of the pointer whose relocation this gc.relocate describes .


<s>
SDValue
LanaiTargetLowering
::
LowerCall
(
TargetLowering
::
CallLoweringInfo
&
CLI
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SelectionDAG
&
DAG
=
CLI
.
DAG
;
SDLoc
&
DL
=
CLI
.
DL
;
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
=
CLI
.
Outs
;
SmallVectorImpl
<
SDValue
>
&
OutVals
=
CLI
.
OutVals
;
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
=
CLI
.
Ins
;
SDValue
Chain
=
CLI
.
Chain
;
SDValue
Callee
=
CLI
.
Callee
;
bool
&
IsTailCall
=
CLI
.
IsTailCall
;
CallingConv
::
ID
CallConv
=
CLI
.
CallConv
;
bool
IsVarArg
=
CLI
.
IsVarArg
;
IsTailCall
=
false
;
switch
(
CallConv
)
{
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
IsVarArg
,
IsTailCall
,
Outs
,
OutVals
,
Ins
,
DL
,
DAG
,
InVals
)
;
default
:
report_fatal_error
(
"Unsupported calling convention"
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .

Lanai
Lanai
ISD::OutputArg
ISD::InputArg
"Unsupported calling convention"


<s>
void
GCNUpwardRPTracker
::
recede
(
const
MachineInstr
&
MI
)
{
assert
(
MRI
&&
"call reset first"
)
;
LastTrackedMI
=
&
MI
;
if
(
MI
.
isDebugInstr
(
)
)
return
;
auto
const
RegUses
=
collectVirtualRegUses
(
MI
,
LIS
,
*
MRI
)
;
auto
AtMIPressure
=
CurPressure
;
for
(
const
auto
&
U
:
RegUses
)
{
auto
LiveMask
=
LiveRegs
[
U
.
RegUnit
]
;
AtMIPressure
.
inc
(
U
.
RegUnit
,
LiveMask
,
LiveMask
|
U
.
LaneMask
,
*
MRI
)
;
}
MaxPressure
=
max
(
AtMIPressure
,
MaxPressure
)
;
for
(
const
auto
&
MO
:
MI
.
defs
(
)
)
{
if
(
!
MO
.
isReg
(
)
||
!
Register
::
isVirtualRegister
(
MO
.
getReg
(
)
)
||
MO
.
isDead
(
)
)
continue
;
auto
Reg
=
MO
.
getReg
(
)
;
auto
I
=
LiveRegs
.
find
(
Reg
)
;
if
(
I
==
LiveRegs
.
end
(
)
)
continue
;
auto
&
LiveMask
=
I
->
second
;
auto
PrevMask
=
LiveMask
;
LiveMask
&=
~
getDefRegMask
(
MO
,
*
MRI
)
;
CurPressure
.
inc
(
Reg
,
PrevMask
,
LiveMask
,
*
MRI
)
;
if
(
LiveMask
.
(
)
)
LiveRegs
.
erase
(
I
)
;
}
for
(
const
auto
&
U
:
RegUses
)
{
auto
&
LiveMask
=
LiveRegs
[
U
.
RegUnit
]
;
auto
PrevMask
=
LiveMask
;
LiveMask
|=
U
.
LaneMask
;
CurPressure
.
inc
(
U
.
RegUnit
,
PrevMask
,
LiveMask
,
*
MRI
)
;
}
assert
(
CurPressure
==
getRegPressure
(
*
MRI
,
LiveRegs
)
)
;
}
</s>

Recede across the previous instruction .


<s> void ix86_expand_fp_absneg_operator ( enum rtx_code code , machine_mode mode , rtx operands [ ] ) { rtx mask , set , dst , src ; bool use_sse = false ; bool vector_mode = VECTOR_MODE_P ( mode ) ; machine_mode vmode = mode ; if ( vector_mode ) use_sse = true ; else if ( mode == TFmode ) use_sse = true ; else if ( TARGET_SSE_MATH ) { use_sse = SSE_FLOAT_MODE_P ( mode ) ; if ( mode == SFmode ) vmode = V4SFmode ; else if ( mode == DFmode ) vmode = V2DFmode ; } if ( use_sse ) mask = ix86_build_signbit_mask ( vmode , vector_mode , code == ABS ) ; else mask = NULL_RTX ; dst = operands [ 0 ] ; src = operands [ 1 ] ; set = gen_rtx_fmt_e ( code , mode , src ) ; set = gen_rtx_SET ( VOIDmode , dst , set ) ; if ( mask ) { rtx use , clob ; rtvec par ; use = gen_rtx_USE ( VOIDmode , mask ) ; if ( vector_mode ) par = gen_rtvec ( 2 , set , use ) ; else { clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; par = gen_rtvec ( 3 , set , use , clob ) ; } emit_insn ( gen_rtx_PARALLEL ( VOIDmode , par ) ) ; } else emit_insn ( set ) ; } </s>

Generate code for floating point ABS or NEG .


<s> unsigned BlackfinRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? BF :: FP : BF :: SP ; } </s>


<s> EVT PPCTargetLowering :: getSetCCResultType ( EVT VT ) const { return MVT :: i32 ; } </s>

Return the value type to use for ISD : :SETCC .


<s> unsigned getExceptionPointerRegister ( const Constant * PersonalityFn ) const override { return Hexagon :: R0 ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s> MachineInstr * Thumb1InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , int FI ) const { if ( Ops . size ( ) != 1 ) return NULL ; unsigned OpNum = Ops [ 0 ] ; unsigned Opc = MI -> getOpcode ( ) ; MachineInstr * NewMI = NULL ; switch ( Opc ) { default : break ; case ARM :: tMOVr : case ARM :: tMOVtgpr2gpr : case ARM :: tMOVgpr2tgpr : case ARM :: tMOVgpr2gpr : { if ( OpNum == 0 ) { unsigned SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; bool isKill = MI -> getOperand ( 1 ) . isKill ( ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) && ! isARMLowRegister ( SrcReg ) ) break ; NewMI = AddDefaultPred ( BuildMI ( MF , MI -> getDebugLoc ( ) , get ( ARM :: tSpill ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) ) ; } else { unsigned DstReg = MI -> getOperand ( 0 ) . getReg ( ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DstReg ) && ! isARMLowRegister ( DstReg ) ) break ; bool isDead = MI -> getOperand ( 0 ) . isDead ( ) ; NewMI = AddDefaultPred ( BuildMI ( MF , MI -> getDebugLoc ( ) , get ( ARM :: tRestore ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( isDead ) ) . addFrameIndex ( FI ) . addImm ( 0 ) ) ; } break ; } } return NewMI ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> static bool loongarch_function_ok_for_sibcall ( tree decl ATTRIBUTE_UNUSED , tree exp ATTRIBUTE_UNUSED ) { return true ; } </s>


<s> static void nvptx_print_operand_address ( FILE * file , machine_mode mode , rtx addr ) { nvptx_print_address_operand ( file , addr , mode ) ; } </s>

Write assembly language output for the address ADDR to FILE .


<s> bool X86TargetMachine :: addPostRegAlloc ( PassManagerBase & PM ) { PM . add ( createX86FloatingPointStackifierPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> void RISCVPassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; addPass ( createCheriBoundAllocasPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> bool X86FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; if ( MI != MBB . end ( ) && isFuncletReturnInstr ( * MI ) && STI . isOSWindows ( ) ) { if ( STI . is32Bit ( ) ) return true ; if ( MI -> getOpcode ( ) == X86 :: CATCHRET ) { const Function & F = MBB . getParent ( ) -> getFunction ( ) ; bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( F . getPersonalityFn ( ) ) ) ; if ( IsSEH ) return true ; } } DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; int XMMFrameSlotOrigin ; int SEHFrameOffset = X86FI -> getCalleeSavedXMMFrameInfo ( XMMFrameSlotOrigin ) + MF . getFrameInfo ( ) . getMaxCallFrameSize ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( MBB . isEHFuncletEntry ( ) && STI . is64Bit ( ) ) { if ( X86 :: VR128RegClass . contains ( Reg ) ) { int Offset = ( CSI [ i ] . getFrameIdx ( ) - XMMFrameSlotOrigin - 1 ) * 16 ; addRegOffset ( BuildMI ( MBB , MI , DL , TII . get ( getXMMAlignedLoadStoreOp ( true ) ) , Reg ) , X86 :: RSP , true , SEHFrameOffset + Offset ) ; } } else { if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MVT VT = MVT :: Other ; if ( X86 :: VK16RegClass . contains ( Reg ) ) VT = STI . hasBWI ( ) ? MVT :: v64i1 : MVT :: v16i1 ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg , VT ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } } unsigned Opc = STI . is64Bit ( ) ? X86 :: POP64r : X86 :: POP32r ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> tree arm_resolve_overloaded_builtin ( location_t loc , tree fndecl , void * arglist ) { if ( arm_describe_resolver ( fndecl ) == arm_cde_resolver ) return arm_resolve_cde_builtin ( loc , fndecl , arglist ) ; return NULL_TREE ; } </s>

Implement TARGET_RESOLVE_OVERLOADED_BUILTIN . This is currently only used for the MVE related builtins for the CDE extension . Here we ensure the type of arguments is such that the size is correct , and then return a tree that describes the same function call but with the relevant types cast as necessary .


<s> static short find_insn_regmode_weight ( rtx insn , enum machine_mode mode ) { short reg_weight = 0 ; rtx x ; x = PATTERN ( insn ) ; reg_weight += find_set_regmode_weight ( x , mode ) ; if ( GET_CODE ( x ) == PARALLEL ) { int j ; for ( j = XVECLEN ( x , 0 ) - 1 ; j >= 0 ; j -- ) { x = XVECEXP ( PATTERN ( insn ) , 0 , j ) ; reg_weight += find_set_regmode_weight ( x , mode ) ; } } for ( x = REG_NOTES ( insn ) ; x ; x = XEXP ( x , 1 ) ) { if ( REG_NOTE_KIND ( x ) == REG_DEAD || REG_NOTE_KIND ( x ) == REG_UNUSED ) { rtx note = XEXP ( x , 0 ) ; if ( GET_CODE ( note ) == REG && GET_MODE ( note ) == mode ) reg_weight -- ; } } return reg_weight ; } </s>


<s>
void
AAPDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
SDLoc
dl
(
Node
)
;
LLVM_DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
return
;
}
switch
(
Opcode
)
{
case
ISD
::
FrameIndex
:
{
assert
(
Node
->
getValueType
(
0
)
==
MVT
::
i16
)
;
int
FI
=
cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
MVT
::
i16
)
;
SDNode
*
N
=
CurDAG
->
getMachineNode
(
AAP
::
LEA
,
dl
,
MVT
::
i16
,
TFI
,
CurDAG
->
getTargetConstant
(
0
,
dl
,
MVT
::
i16
)
)
;
ReplaceNode
(
Node
,
N
)
;
return
;
}
default
:
break
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> const std :: string & getAddress ( ) const { return Address ; } </s>

Returns the address of this pointer in this block .


<s> SparcTargetMachine :: SparcTargetMachine ( const Module & M , const std :: string & FS ) : DataLayout ( "E-p:32:32-f128:128:128" ) , Subtarget ( M , FS ) , TLInfo ( * this ) , InstrInfo ( Subtarget ) , FrameInfo ( TargetFrameInfo :: StackGrowsDown , 8 , 0 ) { } </s>


<s>
MachineBasicBlock
::
iterator
AArch64FrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
const
AArch64InstrInfo
*
TII
=
static_cast
<
const
AArch64InstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
DebugLoc
DL
=
I
->
getDebugLoc
(
)
;
unsigned
Opc
=
I
->
getOpcode
(
)
;
bool
IsDestroy
=
Opc
==
TII
->
getCallFrameDestroyOpcode
(
)
;
uint64_t
CalleePopAmount
=
IsDestroy
I
->
getOperand
(
1
)
.
getImm
(
)
:
0
;
if
(
!
hasReservedCallFrame
(
MF
)
)
{
unsigned
Align
=
getStackAlignment
(
)
;
int64_t
Amount
=
I
->
getOperand
(
0
)
.
getImm
(
)
;
Amount
=
alignTo
(
Amount
,
Align
)
;
if
(
!
IsDestroy
)
Amount
=
Amount
;
if
(
CalleePopAmount
==
0
)
{
assert
(
Amount
>
0xffffff
&&
Amount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
{
Amount
,
MVT
::
i8
}
,
TII
)
;
}
}
else
if
(
CalleePopAmount
!=
0
)
{
assert
(
CalleePopAmount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
{
(
int64_t
)
CalleePopAmount
,
MVT
::
i8
}
,
TII
)
;
}
return
MBB
.
erase
(
I
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool ARMCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const { auto & TLI = * getTLI < ARMTargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb1Only ( ) ) return false ; if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; const auto & DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasPassPointeeByValueCopyAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; OutgoingValueAssigner ArgAssigner ( AssignFn ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) ) ; SmallVector < ArgInfo , 8 > SplitArgInfos ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArgInfo ( VRegs [ Idx ] , Arg . getType ( ) , Idx ) ; setArgFlags ( OrigArgInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArgInfo , SplitArgInfos , DL , F . getCallingConv ( ) ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; if ( ! determineAndHandleAssignments ( ArgHandler , ArgAssigner , SplitArgInfos , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> bool ARMAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { const uint16_t Thumb1_16bitNopEncoding = 0x46c0 ; const uint16_t Thumb2_16bitNopEncoding = 0xbf00 ; const uint32_t ARMv4_NopEncoding = 0xe1a00000 ; const uint32_t ARMv6T2_NopEncoding = 0xe320f000 ; if ( isThumb ( ) ) { const uint16_t nopEncoding = hasNOP ( ) ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding ; uint64_t NumNops = Count / 2 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> write16 ( nopEncoding ) ; if ( Count & 1 ) OW -> write8 ( 0 ) ; return true ; } const uint32_t nopEncoding = hasNOP ( ) ? ARMv6T2_NopEncoding : ARMv4_NopEncoding ; uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> write32 ( nopEncoding ) ; switch ( Count % 4 ) { default : break ; case 1 : OW -> write8 ( 0 ) ; break ; case 2 : OW -> write16 ( 0 ) ; break ; case 3 : OW -> write16 ( 0 ) ; OW -> write8 ( 0xa0 ) ; break ; } return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> static bool canonicalize_vector_int_perm ( const struct expand_vec_perm_d * d , struct expand_vec_perm_d * nd ) { int i ; enum machine_mode mode = VOIDmode ; switch ( d -> vmode ) { case V16QImode : mode = V8HImode ; break ; case V32QImode : mode = V16HImode ; break ; case V64QImode : mode = V32HImode ; break ; case V8HImode : mode = V4SImode ; break ; case V16HImode : mode = V8SImode ; break ; case V32HImode : mode = V16SImode ; break ; case V4SImode : mode = V2DImode ; break ; case V8SImode : mode = V4DImode ; break ; case V16SImode : mode = V8DImode ; break ; default : return false ; } for ( i = 0 ; i < d -> nelt ; i += 2 ) if ( ( d -> perm [ i ] & 1 ) || d -> perm [ i + 1 ] != d -> perm [ i ] + 1 ) return false ; nd -> vmode = mode ; nd -> nelt = d -> nelt / 2 ; for ( i = 0 ; i < nd -> nelt ; i ++ ) nd -> perm [ i ] = d -> perm [ 2 * i ] / 2 ; if ( GET_MODE_INNER ( mode ) != DImode ) canonicalize_vector_int_perm ( nd , nd ) ; if ( nd != d ) { nd -> one_operand_p = d -> one_operand_p ; nd -> testing_p = d -> testing_p ; if ( d -> op0 == d -> op1 ) nd -> op0 = nd -> op1 = gen_lowpart ( nd -> vmode , d -> op0 ) ; else { nd -> op0 = gen_lowpart ( nd -> vmode , d -> op0 ) ; nd -> op1 = gen_lowpart ( nd -> vmode , d -> op1 ) ; } if ( d -> testing_p ) nd -> target = gen_raw_REG ( nd -> vmode , LAST_VIRTUAL_REGISTER + 1 ) ; else nd -> target = gen_reg_rtx ( nd -> vmode ) ; } return true ; } </s>

For V * [ QHS ] Imode permutations , check if the same permutation ca n't be performed in a 2x , 4x or 8x wider inner mode .


Control the placement of special register scavenging spill slots when allocating a stack frame .


<s> bool AMDGPUAsmBackend :: mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const { if ( ! STI . getFeatureBits ( ) [ AMDGPU :: FeatureOffset3fBug ] ) return false ; if ( AMDGPU :: getSOPPWithRelaxation ( Inst . getOpcode ( ) ) >= 0 ) return true ; return false ; } </s>

Check whether the given instruction may need relaxation .


"********** ARM MVE VPT Optimisations **********\n"

runOnMachineFunction - Emit the function body .


<s> static void v850_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain_value ) { rtx mem , fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp , SImode , 16 ) ; emit_move_insn ( mem , chain_value ) ; mem = adjust_address ( m_tramp , SImode , 20 ) ; emit_move_insn ( mem , fnaddr ) ; } </s>

Worker function for TARGET_TRAMPOLINE_INIT .


"getBranchTargetOpValueLsl2MMR6 expects only expressions or immediates"

getBranchTargetOpValueLsl2MMR6 - Return binary encoding of the branch target operand .


<s> bool MSP430DAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintID ) { default : return true ; case InlineAsm :: Constraint_m : if ( ! SelectAddr ( Op , Op0 , Op1 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> bool AArch64TargetLowering :: isTruncateFree ( EVT VT1 , EVT VT2 ) const { if ( VT1 . isVector ( ) || VT2 . isVector ( ) || ! VT1 . isInteger ( ) || ! VT2 . isInteger ( ) ) return false ; unsigned NumBits1 = VT1 . getSizeInBits ( ) ; unsigned NumBits2 = VT2 . getSizeInBits ( ) ; return NumBits1 > NumBits2 ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s> BitVector RISCVRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const RISCVFrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; for ( size_t Reg = 0 ; Reg < getNumRegs ( ) ; Reg ++ ) { if ( MF . getSubtarget < RISCVSubtarget > ( ) . isRegisterReservedByUser ( Reg ) ) markSuperRegs ( Reserved , Reg ) ; } markSuperRegs ( Reserved , RISCV :: X0 ) ; markSuperRegs ( Reserved , RISCV :: X2 ) ; markSuperRegs ( Reserved , RISCV :: X3 ) ; markSuperRegs ( Reserved , RISCV :: X4 ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , RISCV :: X8 ) ; if ( TFI -> hasBP ( MF ) ) markSuperRegs ( Reserved , RISCVABI :: getBPReg ( ) ) ; markSuperRegs ( Reserved , RISCV :: VL ) ; markSuperRegs ( Reserved , RISCV :: VTYPE ) ; markSuperRegs ( Reserved , RISCV :: VXSAT ) ; markSuperRegs ( Reserved , RISCV :: VXRM ) ; markSuperRegs ( Reserved , RISCV :: FRM ) ; markSuperRegs ( Reserved , RISCV :: FFLAGS ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


"operation not permitted on type %<bfloat16_t%>"

"cannot combine GNU and SVE vectors in a binary operation"

Return the diagnostic message string if the binary operation OP is not permitted on TYPE1 and TYPE2 , NULL otherwise .


"stack guard value must be an exact power of 2"

"stack size must be an exact power of 2"


<s> void rx_copy_reg_dead_or_unused_notes ( rtx reg , const rtx_insn * src , rtx_insn * dst ) { int regno = REGNO ( SUBREG_P ( reg ) ? SUBREG_REG ( reg ) : reg ) ; if ( rtx note = find_regno_note ( src , REG_DEAD , regno ) ) add_shallow_copy_of_reg_note ( dst , note ) ; if ( rtx note = find_regno_note ( src , REG_UNUSED , regno ) ) add_shallow_copy_of_reg_note ( dst , note ) ; } </s>

Copy dead and unused notes from SRC to DST for the specified REGNO .


<s> bool HexagonEarlyIfConversion :: isValid ( const FlowPattern & FP ) const { if ( hasEHLabel ( FP . SplitB ) ) return false ; if ( FP . TrueB && ! isValidCandidate ( FP . TrueB ) ) return false ; if ( FP . FalseB && ! isValidCandidate ( FP . FalseB ) ) return false ; if ( FP . JoinB ) { const MachineBasicBlock & B = * FP . JoinB ; for ( auto & MI : B ) { if ( ! MI . isPHI ( ) ) break ; if ( usesUndefVReg ( & MI ) ) return false ; unsigned DefR = MI . getOperand ( 0 ) . getReg ( ) ; if ( isPredicate ( DefR ) ) return false ; } } return true ; } </s>

Returns true if this iterator is still pointing at a valid entry .


<s>
static
void
replace_swap_with_copy
(
swap_web_entry
*
insn_entry
,
unsigned
i
)
{
rtx_insn
*
insn
=
insn_entry
[
i
]
.
insn
;
rtx
body
=
PATTERN
(
insn
)
;
rtx
src_reg
=
XEXP
(
SET_SRC
(
body
)
,
0
)
;
rtx
copy
=
gen_rtx_SET
(
VOIDmode
,
SET_DEST
(
body
)
,
src_reg
)
;
rtx_insn
*
new_insn
=
emit_insn_before
(
copy
,
insn
)
;
set_block_for_insn
(
new_insn
,
BLOCK_FOR_INSN
(
insn
)
)
;
df_insn_rescan
(
new_insn
)
;
if
(
dump_file
)
{
unsigned
int
new_uid
=
INSN_UID
(
new_insn
)
;
fprintf
(
dump_file
,
"Replacing swap %d with copy %d\n"
,
i
,
new_uid
)
;
}
df_insn_delete
(
insn
)
;
remove_insn
(
insn
)
;
insn
->
set_deleted
(
)
;
}
</s>

Find the insn from the Ith table entry , which is known to be a register swap Y = SWAP ( X ) . Replace it with a copy Y = X .


<s>
const
char
*
output_jump_label_table
(
void
)
{
int
i
;
if
(
pool_size
)
{
fprintf
(
asm_out_file
,
"\t.align 2\n"
)
;
for
(
i
=
0
;
i
<
pool_size
;
i
++
)
{
pool_node
*
p
=
&
pool_vector
[
i
]
;
(
*
targetm
.
asm_out
.
internal_label
)
(
asm_out_file
,
"L"
,
CODE_LABEL_NUMBER
(
p
->
label
)
)
;
output_asm_insn
(
".long	%O0"
,
&
p
->
value
)
;
}
pool_size
=
0
;
}
return
""
;
}
</s>

Dump out any constants accumulated in the final pass . These will only be labels .


<s> static rtx aarch64_expand_builtin ( tree exp , rtx target , rtx , machine_mode , int ignore ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , 0 ) ; unsigned int code = DECL_MD_FUNCTION_CODE ( fndecl ) ; unsigned int subcode = code >> AARCH64_BUILTIN_SHIFT ; switch ( code & AARCH64_BUILTIN_CLASS ) { case AARCH64_BUILTIN_GENERAL : return aarch64_general_expand_builtin ( subcode , exp , target , ignore ) ; case AARCH64_BUILTIN_SVE : return aarch64_sve :: expand_builtin ( subcode , exp , target ) ; } gcc_unreachable ( ) ; } </s>


<s> static rtx s390_delegitimize_address ( rtx orig_x ) { rtx x = orig_x , y ; if ( GET_CODE ( x ) != MEM ) return orig_x ; x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 1 ) ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == REG && REGNO ( XEXP ( x , 0 ) ) == PIC_OFFSET_TABLE_REGNUM ) { y = XEXP ( XEXP ( x , 1 ) , 0 ) ; if ( GET_CODE ( y ) == UNSPEC && XINT ( y , 1 ) == UNSPEC_GOT ) return XVECEXP ( y , 0 , 0 ) ; return orig_x ; } if ( GET_CODE ( x ) == CONST ) { y = XEXP ( x , 0 ) ; if ( GET_CODE ( y ) == UNSPEC && XINT ( y , 1 ) == UNSPEC_GOTENT ) return XVECEXP ( y , 0 , 0 ) ; return orig_x ; } return orig_x ; } </s>

In the name of slightly smaller debug output , and to cater to general assembler lossage , recognize various UNSPEC sequences and turn them back into a direct symbol reference .


<s> bool MipsAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == ".ent" ) { Parser . Lex ( ) ; return false ; } if ( IDVal == ".end" ) { Parser . Lex ( ) ; return false ; } if ( IDVal == ".frame" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".set" ) { return parseDirectiveSet ( ) ; } if ( IDVal == ".fmask" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".mask" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".gpword" ) { parseDirectiveGpWord ( ) ; return false ; } if ( IDVal == ".word" ) { parseDirectiveWord ( 4 , DirectiveID . getLoc ( ) ) ; return false ; } return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


"Global constants structure not present"


<s> static bool pa_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) { HOST_WIDE_INT size = arg . type_size_in_bytes ( ) ; if ( TARGET_64BIT ) return size <= 0 ; else return size <= 0 || size > 8 ; } </s>

In the 32-bit runtime , arguments larger than eight bytes are passed by invisible reference . As a GCC extension , we also pass anything with a zero or variable size by reference . The 64-bit runtime does not describe passing any types by invisible reference . The internals of GCC ca n't currently handle passing empty structures , and zero or variable length arrays when they are not passed entirely on the stack or by reference . Thus , as a GCC extension , we pass these types by reference . The HP compiler does n't support these types , so hopefully there should n't be any compatibility issues . This may have to be revisited when HP releases a C99 compiler or updates the ABI .


<s> MachineInstr * SIInstrInfo :: convertToThreeAddress ( MachineFunction :: iterator & MBB , MachineInstr & MI , LiveVariables * LV ) const { bool IsF16 = false ; switch ( MI . getOpcode ( ) ) { default : return nullptr ; case AMDGPU :: V_MAC_F16_e64 : IsF16 = true ; case AMDGPU :: V_MAC_F32_e64 : break ; case AMDGPU :: V_MAC_F16_e32 : IsF16 = true ; case AMDGPU :: V_MAC_F32_e32 : { int Src0Idx = AMDGPU :: getNamedOperandIdx ( MI . getOpcode ( ) , AMDGPU :: OpName :: src0 ) ; const MachineOperand * Src0 = & MI . getOperand ( Src0Idx ) ; if ( Src0 -> isImm ( ) && ! isInlineConstant ( MI , Src0Idx , * Src0 ) ) return nullptr ; break ; } } const MachineOperand * Dst = getNamedOperand ( MI , AMDGPU :: OpName :: vdst ) ; const MachineOperand * Src0 = getNamedOperand ( MI , AMDGPU :: OpName :: src0 ) ; const MachineOperand * Src1 = getNamedOperand ( MI , AMDGPU :: OpName :: src1 ) ; const MachineOperand * Src2 = getNamedOperand ( MI , AMDGPU :: OpName :: src2 ) ; return BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( IsF16 ? AMDGPU :: V_MAD_F16 : AMDGPU :: V_MAD_F32 ) ) . add ( * Dst ) . addImm ( 0 ) . add ( * Src0 ) . addImm ( 0 ) . add ( * Src1 ) . addImm ( 0 ) . add ( * Src2 ) . addImm ( 0 ) . addImm ( 0 ) ; } </s>

convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag .


<s>
SDValue
MSP430TargetLowering
::
LowerCall
(
SDValue
Chain
,
SDValue
Callee
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
bool
&
isTailCall
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
Ins
,
dl
,
DAG
,
InVals
)
;
case
CallingConv
::
MSP430_INTR
:
llvm_report_error
(
"ISRs cannot be called directly"
)
;
return
SDValue
(
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .


<s> bool SIWholeQuadMode :: runOnMachineFunction ( MachineFunction & MF ) { Instructions . clear ( ) ; Blocks . clear ( ) ; LiveMaskQueries . clear ( ) ; LowerToCopyInstrs . clear ( ) ; LowerToMovInstrs . clear ( ) ; CallingConv = MF . getFunction ( ) . getCallingConv ( ) ; ST = & MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST -> getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; LIS = & getAnalysis < LiveIntervals > ( ) ; if ( ST -> isWave32 ( ) ) { AndOpc = AMDGPU :: S_AND_B32 ; XorTermrOpc = AMDGPU :: S_XOR_B32_term ; OrSaveExecOpc = AMDGPU :: S_OR_SAVEEXEC_B32 ; Exec = AMDGPU :: EXEC_LO ; } else { AndOpc = AMDGPU :: S_AND_B64 ; XorTermrOpc = AMDGPU :: S_XOR_B64_term ; OrSaveExecOpc = AMDGPU :: S_OR_SAVEEXEC_B64 ; Exec = AMDGPU :: EXEC ; } char GlobalFlags = analyzeFunction ( MF ) ; unsigned LiveMaskReg = 0 ; if ( ! ( GlobalFlags & StateWQM ) ) { lowerLiveMaskQueries ( Exec ) ; if ( ! ( GlobalFlags & StateWWM ) && LowerToCopyInstrs . empty ( ) && LowerToMovInstrs . empty ( ) ) return ! LiveMaskQueries . empty ( ) ; } else { MachineBasicBlock & Entry = MF . front ( ) ; MachineBasicBlock :: iterator EntryMI = Entry . getFirstNonPHI ( ) ; if ( GlobalFlags & StateExact || ! LiveMaskQueries . empty ( ) ) { LiveMaskReg = MRI -> createVirtualRegister ( TRI -> getBoolRC ( ) ) ; MachineInstr * MI = BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( AMDGPU :: COPY ) , LiveMaskReg ) . addReg ( Exec ) ; LIS -> InsertMachineInstrInMaps ( * MI ) ; } lowerLiveMaskQueries ( LiveMaskReg ) ; if ( GlobalFlags == StateWQM ) { auto MI = BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( ST -> isWave32 ( ) ? AMDGPU :: S_WQM_B32 : AMDGPU :: S_WQM_B64 ) , Exec ) . addReg ( Exec ) ; LIS -> InsertMachineInstrInMaps ( * MI ) ; lowerCopyInstrs ( ) ; return true ; } } LLVM_DEBUG ( printInfo ( ) ) ; lowerCopyInstrs ( ) ; for ( auto BII : Blocks ) processBlock ( * BII . first , LiveMaskReg , BII . first == & * MF . begin ( ) ) ; if ( LiveMaskReg ) LIS -> createAndComputeVirtRegInterval ( LiveMaskReg ) ; LIS -> removeRegUnit ( * MCRegUnitIterator ( MCRegister :: from ( AMDGPU :: SCC ) , TRI ) ) ; return true ; } </s>


<s> bool sh_is_logical_t_store_expr ( rtx op , rtx_insn * insn ) { if ( ! logical_operator ( op , SImode ) ) return false ; rtx ops [ 2 ] = { XEXP ( op , 0 ) , XEXP ( op , 1 ) } ; int op_is_t_count = 0 ; for ( int i = 0 ; i < 2 ; ++ i ) { if ( t_reg_operand ( ops [ i ] , VOIDmode ) || negt_reg_operand ( ops [ i ] , VOIDmode ) ) op_is_t_count ++ ; else { set_of_reg op_set = sh_find_set_of_reg ( ops [ i ] , insn , prev_nonnote_insn_bb ) ; if ( op_set . set_src == NULL_RTX ) continue ; if ( t_reg_operand ( op_set . set_src , VOIDmode ) || negt_reg_operand ( op_set . set_src , VOIDmode ) || sh_is_logical_t_store_expr ( op_set . set_src , op_set . insn ) ) op_is_t_count ++ ; } } return op_is_t_count == 2 ; } </s>

Given an op rtx and an insn , try to find out whether the result of the specified op consists only of logical operations on T bit stores .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , computeDefaultCPU ( TT , CPU ) , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveAArch64CodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } if ( getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) { this -> Options . TrapUnreachable = true ; } if ( this -> Options . TLSSize == 0 ) this -> Options . TLSSize = 24 ; if ( ( getCodeModel ( ) == CodeModel :: Small || getCodeModel ( ) == CodeModel :: Kernel ) && this -> Options . TLSSize > 32 ) this -> Options . TLSSize = 32 ; else if ( getCodeModel ( ) == CodeModel :: Tiny && this -> Options . TLSSize > 24 ) this -> Options . TLSSize = 24 ; if ( getOptLevel ( ) <= EnableGlobalISelAtO && TT . getArch ( ) != Triple :: aarch64_32 && TT . getEnvironment ( ) != Triple :: GNUILP32 && ! ( getCodeModel ( ) == CodeModel :: Large && TT . isOSBinFormatMachO ( ) ) ) { setGlobalISel ( true ) ; setGlobalISelAbort ( GlobalISelAbortMode :: Disable ) ; } setMachineOutliner ( true ) ; setSupportsDefaultOutlining ( true ) ; setSupportsDebugEntryValues ( true ) ; } </s>


<s> enum reg_class avr_regno_reg_class ( int r ) { if ( r <= 33 ) return reg_class_tab [ r ] ; return ALL_REGS ; } </s>


<s> void function_expander :: add_vundef_operand ( machine_mode mode ) { add_input_operand ( mode , RVV_VUNDEF ( mode ) ) ; } </s>

Since we may normalize vop/vop_tu/vop_m/vop_tumu .. into a single patter . We add a undef for the intrinsics that do n't need a real merge .


"calling %qD with SSE calling convention without "

"this is a GCC bug that can be worked around by adding "

Define how to find the value returned by a function . VALTYPE is the data type of the value ( as a tree ) . If the precise function being called is known , FUNC is its FUNCTION_DECL ; otherwise , FUNC is 0 .


"internal compiler error.  Incorrect shift:"

8bit arithmetic shift right ( ( signed char ) x > > i )


<s> static rtx visium_function_value_1 ( enum machine_mode mode ) { if ( TARGET_FPU && ( ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && GET_MODE_SIZE ( mode ) <= UNITS_PER_HWFPVALUE ) || ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT && GET_MODE_SIZE ( mode ) <= UNITS_PER_HWFPVALUE * 2 ) ) ) return gen_rtx_REG ( mode , FP_RETURN_REGNUM ) ; return gen_rtx_REG ( mode , RETURN_REGNUM ) ; } </s>


<s> bool AMDGPUTargetLowering :: isTruncateFree ( Type * Source , Type * Dest ) const { unsigned SrcSize = Source -> getScalarSizeInBits ( ) ; unsigned DestSize = Dest -> getScalarSizeInBits ( ) ; if ( DestSize == 16 && Subtarget -> has16BitInsts ( ) ) return SrcSize >= 32 ; return DestSize < SrcSize && DestSize % 32 == 0 ; } </s>


<s> virtual bool doInitialization ( Module & M ) { LLVMContext & Ctx = M . getContext ( ) ; Mod = & M ; FloatType = Type :: getFloatTy ( Ctx ) ; Int32Type = Type :: getInt32Ty ( Ctx ) ; V4f32Type = VectorType :: get ( FloatType , 4 ) ; V4i32Type = VectorType :: get ( Int32Type , 4 ) ; Type * ArgsType [ ] = { V4f32Type , Int32Type , Int32Type , Int32Type , Int32Type , Int32Type , Int32Type , Int32Type , Int32Type , Int32Type , } ; TexSign = FunctionType :: get ( V4f32Type , ArgsType , false ) ; Type * ArgsQType [ ] = { V4i32Type , Int32Type , Int32Type , Int32Type , Int32Type , Int32Type , Int32Type , Int32Type , Int32Type , Int32Type , } ; TexQSign = FunctionType :: get ( V4f32Type , ArgsQType , false ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> void emitGlobalType ( const MCSymbolWasm * ) override { } </s>


<s>
unsigned
char
X86Subtarget
::
ClassifyGlobalReference
(
const
GlobalValue
*
GV
,
const
TargetMachine
&
TM
)
const
{
if
(
GV
->
hasDLLImportLinkage
(
)
)
return
X86II
::
MO_DLLIMPORT
;
bool
isDecl
=
GV
->
isDeclaration
(
)
&&
!
GV
->
isMaterializable
(
)
;
if
(
isPICStyleRIPRel
(
)
)
{
if
(
TM
.
getCodeModel
(
)
==
CodeModel
::
Large
)
return
X86II
::
MO_NO_FLAG
;
if
(
isTargetDarwin
(
)
)
{
if
(
GV
->
hasDefaultVisibility
(
)
&&
(
isDecl
||
GV
->
isWeakForLinker
(
)
)
)
return
X86II
::
MO_GOTPCREL
;
}
else
{
assert
(
isTargetELF
(
)
&&
"Unknown rip-relative target"
)
;
if
(
!
GV
->
hasLocalLinkage
(
)
&&
GV
->
hasDefaultVisibility
(
)
)
return
X86II
::
MO_GOTPCREL
;
}
return
X86II
::
MO_NO_FLAG
;
}
if
(
isPICStyleGOT
(
)
)
{
if
(
GV
->
hasLocalLinkage
(
)
||
GV
->
hasHiddenVisibility
(
)
)
return
X86II
::
MO_GOTOFF
;
return
X86II
::
MO_GOT
;
}
if
(
isPICStyleStubPIC
(
)
)
{
if
(
!
isDecl
&&
!
GV
->
isWeakForLinker
(
)
)
return
X86II
::
MO_PIC_BASE_OFFSET
;
if
(
!
GV
->
hasHiddenVisibility
(
)
)
return
X86II
::
MO_DARWIN_NONLAZY_PIC_BASE
;
if
(
isDecl
||
GV
->
hasCommonLinkage
(
)
)
{
return
X86II
::
MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE
;
}
return
X86II
::
MO_PIC_BASE_OFFSET
;
}
if
(
isPICStyleStubNoDynamic
(
)
)
{
if
(
!
isDecl
&&
!
GV
->
isWeakForLinker
(
)
)
return
X86II
::
MO_NO_FLAG
;
if
(
!
GV
->
hasHiddenVisibility
(
)
)
return
X86II
::
MO_DARWIN_NONLAZY
;
return
X86II
::
MO_NO_FLAG
;
}
return
X86II
::
MO_NO_FLAG
;
}
</s>

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be referenced for the current subtarget .


"ARM Loops: Failed to find all loop components.\n"

Dump the plan to stderr ( for debugging ) .


"execute-only should not generate constant pools"

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> Val ( unsigned int Op , std :: vector < unsigned int > Nums ) : Op ( Op ) , Nums ( Nums ) { } </s>


<s> void HexagonAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst MCB ; MCB . setOpcode ( Hexagon :: BUNDLE ) ; MCB . addOperand ( MCOperand :: createImm ( 0 ) ) ; if ( MI -> isBundle ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI -> getIterator ( ) ; unsigned IgnoreCount = 0 ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) { if ( MII -> getOpcode ( ) == TargetOpcode :: DBG_VALUE || MII -> getOpcode ( ) == TargetOpcode :: IMPLICIT_DEF ) ++ IgnoreCount ; else { HexagonLowerToMC ( & * MII , MCB , * this ) ; } } } else { HexagonLowerToMC ( MI , MCB , * this ) ; HexagonMCInstrInfo :: padEndloop ( MCB ) ; } HexagonMCInstrInfo :: tryCompound ( * Subtarget -> getInstrInfo ( ) , OutStreamer -> getContext ( ) , MCB ) ; SmallVector < DuplexCandidate , 8 > possibleDuplexes ; possibleDuplexes = HexagonMCInstrInfo :: getDuplexPossibilties ( * Subtarget -> getInstrInfo ( ) , MCB ) ; HexagonMCShuffle ( * Subtarget -> getInstrInfo ( ) , * Subtarget , OutStreamer -> getContext ( ) , MCB , possibleDuplexes ) ; EmitToStreamer ( * OutStreamer , MCB ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .

Hexagon Hexagon Hexagon::BUNDLE 0 0 Hexagon Hexagon Hexagon Hexagon 8 Hexagon Hexagon


<s>
bool
ARMBaseInstrInfo
::
expandPostRAPseudo
(
MachineBasicBlock
::
iterator
MI
)
const
{
if
(
!
WidenVMOVS
||
!
MI
->
isCopy
(
)
||
Subtarget
.
isCortexA15
(
)
)
return
false
;
unsigned
DstRegS
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
unsigned
SrcRegS
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
if
(
!
ARM
::
SPRRegClass
.
contains
(
DstRegS
,
SrcRegS
)
)
return
false
;
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
unsigned
DstRegD
=
TRI
->
getMatchingSuperReg
(
DstRegS
,
ARM
::
ssub_0
,
&
ARM
::
DPRRegClass
)
;
unsigned
SrcRegD
=
TRI
->
getMatchingSuperReg
(
SrcRegS
,
ARM
::
ssub_0
,
&
ARM
::
DPRRegClass
)
;
if
(
!
DstRegD
||
!
SrcRegD
)
return
false
;
if
(
!
MI
->
definesRegister
(
DstRegD
,
TRI
)
||
MI
->
readsRegister
(
DstRegD
,
TRI
)
)
return
false
;
if
(
MI
->
getOperand
(
0
)
.
isDead
(
)
)
return
false
;
DEBUG
(
dbgs
(
)
<<
"widening:    "
<<
*
MI
)
;
MachineInstrBuilder
MIB
(
*
MI
->
getParent
(
)
->
getParent
(
)
,
MI
)
;
int
ImpDefIdx
=
MI
->
findRegisterDefOperandIdx
(
DstRegD
)
;
if
(
ImpDefIdx
!=
1
)
MI
->
RemoveOperand
(
ImpDefIdx
)
;
MI
->
setDesc
(
get
(
ARM
::
VMOVD
)
)
;
MI
->
getOperand
(
0
)
.
setReg
(
DstRegD
)
;
MI
->
getOperand
(
1
)
.
setReg
(
SrcRegD
)
;
AddDefaultPred
(
MIB
)
;
MI
->
getOperand
(
1
)
.
setIsUndef
(
)
;
MIB
.
addReg
(
SrcRegS
,
RegState
::
Implicit
)
;
if
(
MI
->
getOperand
(
1
)
.
isKill
(
)
)
{
MI
->
getOperand
(
1
)
.
setIsKill
(
false
)
;
MI
->
addRegisterKilled
(
SrcRegS
,
TRI
,
true
)
;
}
DEBUG
(
dbgs
(
)
<<
"replaced by: "
<<
*
MI
)
;
return
true
;
}
</s>

This function is called for all pseudo instructions that remain after register allocation .


"%q+D has incompatible attributes %qs and %qs"

Implement ` TARGET_ENCODE_SECTION_INFO ' .


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> hasFnAttr ( Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( N -> getOpcode ( ) == X86ISD :: CALL || N -> getOpcode ( ) == X86ISD :: TC_RETURN ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; EVT SrcVT = N -> getOperand ( 0 ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( 0 ) ; bool SrcIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , DstVT , dl , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> void pa_d_register_target_info ( void ) { const struct d_target_info_spec handlers [ ] = { { "floatAbi" , pa_d_handle_target_float_abi } , { "objectFormat" , pa_d_handle_target_object_format } , { NULL , NULL } , } ; d_add_target_info_handlers ( handlers ) ; } </s>


<s> unsigned ARMFastISel :: fastMaterializeAlloca ( const AllocaInst * AI ) { if ( ! FuncInfo . StaticAllocaMap . count ( AI ) ) return 0 ; MVT VT ; if ( ! isLoadTypeLegal ( AI -> getType ( ) , VT ) ) return 0 ; DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( AI ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { unsigned Opc = isThumb2 ? ARM :: t2ADDri : ARM :: ADDri ; const TargetRegisterClass * RC = TLI . getRegClassFor ( VT ) ; unsigned ResultReg = createResultReg ( RC ) ; ResultReg = constrainOperandRegClass ( TII . get ( Opc ) , ResultReg , 0 ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addFrameIndex ( SI -> second ) . addImm ( 0 ) ) ; return ResultReg ; } return 0 ; } </s>

Emit an alloca address in a register using target-specific logic .


<s> bool X86PassConfig :: addPreRegAlloc ( ) { addPass ( createX86ProtectJTSupport ( ) ) ; return false ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> void SparcRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const SparcSubtarget & Subtarget = MF . getSubtarget < SparcSubtarget > ( ) ; const SparcFrameLowering * TFI = getFrameLowering ( MF ) ; unsigned FrameReg ; int Offset ; Offset = TFI -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) ; Offset += MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ; if ( ! Subtarget . isV9 ( ) || ! Subtarget . hasHardQuad ( ) ) { if ( MI . getOpcode ( ) == SP :: STQFri ) { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; unsigned SrcReg = MI . getOperand ( 2 ) . getReg ( ) ; unsigned SrcEvenReg = getSubReg ( SrcReg , SP :: sub_even64 ) ; unsigned SrcOddReg = getSubReg ( SrcReg , SP :: sub_odd64 ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( SP :: STDFri ) ) . addReg ( FrameReg ) . addImm ( 0 ) . addReg ( SrcEvenReg ) ; replaceFI ( MF , * StMI , * StMI , dl , 0 , Offset , FrameReg ) ; MI . setDesc ( TII . get ( SP :: STDFri ) ) ; MI . getOperand ( 2 ) . setReg ( SrcOddReg ) ; Offset += 8 ; } else if ( MI . getOpcode ( ) == SP :: LDQFri ) { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; unsigned DestReg = MI . getOperand ( 0 ) . getReg ( ) ; unsigned DestEvenReg = getSubReg ( DestReg , SP :: sub_even64 ) ; unsigned DestOddReg = getSubReg ( DestReg , SP :: sub_odd64 ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( SP :: LDDFri ) , DestEvenReg ) . addReg ( FrameReg ) . addImm ( 0 ) ; replaceFI ( MF , * StMI , * StMI , dl , 1 , Offset , FrameReg ) ; MI . setDesc ( TII . get ( SP :: LDDFri ) ) ; MI . getOperand ( 0 ) . setReg ( DestOddReg ) ; Offset += 8 ; } } replaceFI ( MF , II , MI , dl , FIOperandNum , Offset , FrameReg ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static void get_scratch_register_on_entry ( struct scratch_reg * sr ) { int regno ; sr -> saved = false ; if ( TARGET_64BIT ) { regno = R11_REG ; } else { tree decl = current_function_decl , fntype = TREE_TYPE ( decl ) ; bool fastcall_p = lookup_attribute ( "fastcall" , TYPE_ATTRIBUTES ( fntype ) ) != NULL_TREE ; bool thiscall_p = lookup_attribute ( "thiscall" , TYPE_ATTRIBUTES ( fntype ) ) != NULL_TREE ; bool static_chain_p = DECL_STATIC_CHAIN ( decl ) ; int regparm = ix86_function_regparm ( fntype , decl ) ; int drap_regno = crtl -> drap_reg ? REGNO ( crtl -> drap_reg ) : INVALID_REGNUM ; if ( ( regparm < 1 || ( fastcall_p && ! static_chain_p ) ) && drap_regno != AX_REG ) regno = AX_REG ; else if ( thiscall_p && ! static_chain_p && drap_regno != AX_REG ) regno = AX_REG ; else if ( regparm < 2 && ! thiscall_p && drap_regno != DX_REG ) regno = DX_REG ; else if ( regparm < 3 && ! fastcall_p && ! thiscall_p && ! static_chain_p && drap_regno != CX_REG ) regno = CX_REG ; else if ( ix86_save_reg ( BX_REG , true ) ) regno = BX_REG ; else if ( ! ( regparm == 3 && static_chain_p ) && ix86_save_reg ( SI_REG , true ) ) regno = SI_REG ; else if ( ix86_save_reg ( DI_REG , true ) ) regno = DI_REG ; else { regno = ( drap_regno == AX_REG ? DX_REG : AX_REG ) ; sr -> saved = true ; } } sr -> reg = gen_rtx_REG ( Pmode , regno ) ; if ( sr -> saved ) { rtx_insn * insn = emit_insn ( gen_push ( sr -> reg ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } </s>

Return a short-lived scratch register for use on function entry . In 32-bit mode , it is valid only after the registers are saved in the prologue . This register must be released by means of release_scratch_register_on_entry once it is dead .


<s> static tree ix86_get_builtin_func_type ( enum ix86_builtin_func_type tcode ) { tree type ; gcc_assert ( ( unsigned ) tcode < ARRAY_SIZE ( ix86_builtin_func_type_tab ) ) ; type = ix86_builtin_func_type_tab [ ( int ) tcode ] ; if ( type != NULL ) return type ; if ( tcode <= IX86_BT_LAST_FUNC ) { unsigned start = ix86_builtin_func_start [ ( int ) tcode ] ; unsigned after = ix86_builtin_func_start [ ( int ) tcode + 1 ] ; tree rtype , atype , args = void_list_node ; unsigned i ; rtype = ix86_get_builtin_type ( ix86_builtin_func_args [ start ] ) ; for ( i = after - 1 ; i > start ; -- i ) { atype = ix86_get_builtin_type ( ix86_builtin_func_args [ i ] ) ; args = tree_cons ( NULL , atype , args ) ; } type = build_function_type ( rtype , args ) ; } else { unsigned index = tcode - IX86_BT_LAST_FUNC - 1 ; enum ix86_builtin_func_type icode ; icode = ix86_builtin_func_alias_base [ index ] ; type = ix86_get_builtin_func_type ( icode ) ; } ix86_builtin_func_type_tab [ ( int ) tcode ] = type ; return type ; } </s>

Retrieve an element from the above table , building some of the types lazily .


<s> const TL45Subtarget * getSubtargetImpl ( const Function & ) const override { return & DefaultSubtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static int get_num_immediates ( rtx_insn * insn , int * imm , int * imm32 , int * imm64 ) { imm_info imm_values = { 0 , 0 , 0 } ; find_constant ( insn , & imm_values ) ; * imm = imm_values . imm ; * imm32 = imm_values . imm32 ; * imm64 = imm_values . imm64 ; return imm_values . imm32 * 4 + imm_values . imm64 * 8 ; } </s>

Return total size of immediate operands of an instruction along with number of corresponding immediate-operands . It initializes its parameters to zero befor calling FIND_CONSTANT . INSN is the input instruction . IMM is the total of immediates . IMM32 is the number of 32 bit immediates . IMM64 is the number of 64 bit immediates .


<s> bool isStackIdSafeForLocalArea ( unsigned StackId ) const override { return StackId != TargetStackID :: ScalableVector ; } </s>

This method returns whether or not it is safe for an object with the given stack id to be bundled into the local area .


<s> void mmix_init_expanders ( void ) { init_machine_status = mmix_init_machine_status ; } </s>


<s> bool NVPTXReplaceImageHandles :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; InstrsToRemove . clear ( ) ; for ( MachineBasicBlock & MBB : MF ) for ( MachineInstr & MI : MBB ) Changed |= processInstr ( MI ) ; for ( MachineInstr * MI : InstrsToRemove ) MI -> eraseFromParent ( ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> const RegisterBankInfo :: InstructionMapping & MipsRegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const RegisterBankInfo :: InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; switch ( Opc ) { case G_ADD : case G_LOAD : case G_STORE : case G_ZEXTLOAD : case G_SEXTLOAD : case G_GEP : case G_AND : case G_OR : case G_XOR : case G_SHL : case G_ASHR : case G_LSHR : case G_SDIV : case G_UDIV : case G_SREM : case G_UREM : OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; break ; case G_CONSTANT : case G_FRAME_INDEX : case G_GLOBAL_VALUE : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr } ) ; break ; case G_ICMP : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] } ) ; break ; case G_SELECT : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] } ) ; break ; default : return getInvalidInstructionMapping ( ) ; } return getInstructionMapping ( DefaultMappingID , 1 , OperandsMapping , NumOperands ) ; } </s>

Get the mapping of the different operands of MI on the register bank .

Mips Mips Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx 1


"cannot return value in vector register because"

" altivec instructions are disabled, use -maltivec"

Handle the INIT_CUMULATIVE_ARGS macro . Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is 0 .


<s> bool X86AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { static const uint8_t Nops [ 10 ] [ 10 ] = { { 0x90 } , { 0x66 , 0x90 } , { 0x0f , 0x1f , 0x00 } , { 0x0f , 0x1f , 0x40 , 0x00 } , { 0x0f , 0x1f , 0x44 , 0x00 , 0x00 } , { 0x66 , 0x0f , 0x1f , 0x44 , 0x00 , 0x00 } , { 0x0f , 0x1f , 0x80 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x66 , 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x66 , 0x2e , 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , } ; if ( ! STI . getFeatureBits ( ) [ X86 :: FeatureNOPL ] ) { for ( uint64_t i = 0 ; i < Count ; ++ i ) OW -> write8 ( 0x90 ) ; return true ; } uint64_t MaxNopLength = STI . getFeatureBits ( ) [ X86 :: ProcIntelSLM ] ? 7 : 15 ; do { const uint8_t ThisNopLength = ( uint8_t ) std :: min ( Count , MaxNopLength ) ; const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10 ; for ( uint8_t i = 0 ; i < Prefixes ; i ++ ) OW -> write8 ( 0x66 ) ; const uint8_t Rest = ThisNopLength - Prefixes ; for ( uint8_t i = 0 ; i < Rest ; i ++ ) OW -> write8 ( Nops [ Rest - 1 ] [ i ] ) ; Count -= ThisNopLength ; } while ( Count != 0 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s>
bool
HexagonPacketizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
const
TargetInstrInfo
*
TII
=
Fn
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
MachineLoopInfo
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
const
MachineBranchProbabilityInfo
*
MBPI
=
&
getAnalysis
<
MachineBranchProbabilityInfo
>
(
)
;
HexagonPacketizerList
Packetizer
(
Fn
,
MLI
,
MBPI
)
;
assert
(
Packetizer
.
getResourceTracker
(
)
&&
"Empty DFA table!"
)
;
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
MachineBasicBlock
::
iterator
End
=
MBB
->
end
(
)
;
MachineBasicBlock
::
iterator
MI
=
MBB
->
begin
(
)
;
while
(
MI
!=
End
)
{
if
(
MI
->
isKill
(
)
)
{
MachineBasicBlock
::
iterator
DeleteMI
=
MI
;
++
MI
;
MBB
->
erase
(
DeleteMI
)
;
End
=
MBB
->
end
(
)
;
continue
;
}
++
MI
;
}
}
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
unsigned
RemainingCount
=
MBB
->
size
(
)
;
for
(
MachineBasicBlock
::
iterator
RegionEnd
=
MBB
->
end
(
)
;
RegionEnd
!=
MBB
->
begin
(
)
;
)
{
MachineBasicBlock
::
iterator
I
=
RegionEnd
;
for
(
;
I
!=
MBB
->
begin
(
)
;
I
,
RemainingCount
)
{
if
(
TII
->
isSchedulingBoundary
(
std
::
prev
(
I
)
,
MBB
,
Fn
)
)
break
;
}
I
=
MBB
->
begin
(
)
;
if
(
I
==
RegionEnd
)
{
RegionEnd
=
std
::
prev
(
RegionEnd
)
;
RemainingCount
;
continue
;
}
if
(
I
==
std
::
prev
(
RegionEnd
)
)
{
RegionEnd
=
std
::
prev
(
RegionEnd
)
;
continue
;
}
Packetizer
.
PacketizeMIs
(
MBB
,
I
,
RegionEnd
)
;
RegionEnd
=
I
;
}
}
return
true
;
}
</s>

Hexagon
Hexagon
Hexagon
"Empty DFA table!"


<s> static tree make_resolver_func ( const tree default_decl , const tree dispatch_decl , basic_block * empty_bb ) { tree decl_name = clone_function_name ( default_decl , "resolver" ) ; const char * resolver_name = IDENTIFIER_POINTER ( decl_name ) ; tree type = build_function_type_list ( ptr_type_node , NULL_TREE ) ; tree decl = build_fn_decl ( resolver_name , type ) ; SET_DECL_ASSEMBLER_NAME ( decl , decl_name ) ; DECL_NAME ( decl ) = decl_name ; TREE_USED ( decl ) = 1 ; DECL_ARTIFICIAL ( decl ) = 1 ; DECL_IGNORED_P ( decl ) = 0 ; TREE_PUBLIC ( decl ) = 0 ; DECL_UNINLINABLE ( decl ) = 1 ; DECL_EXTERNAL ( decl ) = 0 ; DECL_EXTERNAL ( dispatch_decl ) = 0 ; DECL_CONTEXT ( decl ) = NULL_TREE ; DECL_INITIAL ( decl ) = make_node ( BLOCK ) ; DECL_STATIC_CONSTRUCTOR ( decl ) = 0 ; if ( DECL_COMDAT_GROUP ( default_decl ) || TREE_PUBLIC ( default_decl ) ) { DECL_COMDAT ( decl ) = 1 ; make_decl_one_only ( decl , DECL_ASSEMBLER_NAME ( decl ) ) ; } else TREE_PUBLIC ( dispatch_decl ) = 0 ; tree t = build_decl ( UNKNOWN_LOCATION , RESULT_DECL , NULL_TREE , ptr_type_node ) ; DECL_CONTEXT ( t ) = decl ; DECL_ARTIFICIAL ( t ) = 1 ; DECL_IGNORED_P ( t ) = 1 ; DECL_RESULT ( decl ) = t ; gimplify_function_tree ( decl ) ; push_cfun ( DECL_STRUCT_FUNCTION ( decl ) ) ; * empty_bb = init_lowered_empty_function ( decl , false , profile_count :: uninitialized ( ) ) ; cgraph_node :: add_new_function ( decl , true ) ; symtab -> call_cgraph_insertion_hooks ( cgraph_node :: get_create ( decl ) ) ; pop_cfun ( ) ; DECL_ATTRIBUTES ( dispatch_decl ) = make_attribute ( "ifunc" , resolver_name , DECL_ATTRIBUTES ( dispatch_decl ) ) ; cgraph_node :: create_same_body_alias ( dispatch_decl , decl ) ; return decl ; } </s>

Make the resolver function decl to dispatch the versions of a multi- versioned function , DEFAULT_DECL . Create an empty basic block in the resolver and store the pointer in EMPTY_BB . Return the decl of the resolver function .


<s> static bool mips_cannot_force_const_mem ( machine_mode mode , rtx x ) { enum mips_symbol_type type ; rtx base , offset ; if ( GET_CODE ( x ) == HIGH ) return true ; if ( CONST_INT_P ( x ) && mips_legitimate_constant_p ( mode , x ) ) return true ; split_const ( x , & base , & offset ) ; if ( mips_symbolic_constant_p ( base , SYMBOL_CONTEXT_LEA , & type ) ) { if ( mips_use_pcrel_pool_p [ ( int ) type ] ) return false ; if ( SMALL_INT ( offset ) && mips_symbol_insns ( type , MAX_MACHINE_MODE ) > 0 ) return true ; if ( TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p ( type ) ) return true ; } if ( tls_referenced_p ( x ) ) return true ; return false ; } </s>

Return true if X can not be forced into a constant pool .


<s> SDValue R600TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; R600MachineFunctionInfo * MFI = MF . getInfo < R600MachineFunctionInfo > ( ) ; SmallVector < ISD :: InputArg , 8 > LocalIns ; getOriginalFunctionArgs ( DAG , MF . getFunction ( ) , Ins , LocalIns ) ; AnalyzeFormalArguments ( CCInfo , LocalIns ) ; for ( unsigned i = 0 , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const ISD :: InputArg & In = Ins [ i ] ; EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector ( ) ) { MemVT = MemVT . getVectorElementType ( ) ; } if ( AMDGPU :: isShader ( CallConv ) ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & AMDGPU :: R600_Reg128RegClass ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , AMDGPUAS :: CONSTANT_BUFFER_0 ) ; ISD :: LoadExtType Ext = ISD :: NON_EXTLOAD ; if ( MemVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) { Ext = ISD :: SEXTLOAD ; } unsigned ValBase = ArgLocs [ In . getOrigArgIndex ( ) ] . getLocMemOffset ( ) ; unsigned PartOffset = VA . getLocMemOffset ( ) ; unsigned Offset = 36 + VA . getLocMemOffset ( ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) , PartOffset - ValBase ) ; SDValue Arg = DAG . getLoad ( ISD :: UNINDEXED , Ext , VT , DL , Chain , DAG . getConstant ( Offset , DL , MVT :: i32 ) , DAG . getUNDEF ( MVT :: i32 ) , PtrInfo , MemVT , false , true , true , 4 ) ; InVals . push_back ( Arg ) ; MFI -> ABIArgOffset = Offset + MemVT . getStoreSize ( ) ; } return Chain ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


"Instr doesn't have FrameIndex operand!"


<s>
virtual
ScheduleHazardRecognizer
*
CreateTargetHazardRecognizer
(
)
{
const
TargetInstrInfo
*
II
=
TM
.
getInstrInfo
(
)
;
assert
(
II
&&
"No InstrInfo?"
)
;
return
new
PPCHazardRecognizer970
(
*
II
)
;
}
</s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .


<s> unsigned int mn10300_store_multiple_regs ( rtx op ) { int count ; int mask ; int i ; unsigned int last ; rtx elt ; count = XVECLEN ( op , 0 ) ; if ( count < 2 ) return 0 ; elt = XVECEXP ( op , 0 , 0 ) ; if ( GET_CODE ( elt ) != SET || ( ! REG_P ( SET_DEST ( elt ) ) ) || REGNO ( SET_DEST ( elt ) ) != STACK_POINTER_REGNUM || GET_CODE ( SET_SRC ( elt ) ) != PLUS ) return 0 ; elt = SET_SRC ( elt ) ; if ( ( ! REG_P ( XEXP ( elt , 0 ) ) ) || REGNO ( XEXP ( elt , 0 ) ) != STACK_POINTER_REGNUM || ( ! CONST_INT_P ( XEXP ( elt , 1 ) ) ) || INTVAL ( XEXP ( elt , 1 ) ) != - ( count - 1 ) * 4 ) return 0 ; mask = 0 ; for ( i = 1 ; i < count ; i ++ ) { elt = XVECEXP ( op , 0 , i ) ; if ( GET_CODE ( elt ) != SET || ( ! MEM_P ( SET_DEST ( elt ) ) ) || ( ! REG_P ( SET_SRC ( elt ) ) ) ) return 0 ; last = REGNO ( SET_SRC ( elt ) ) ; mask |= ( 1 << last ) ; elt = XEXP ( SET_DEST ( elt ) , 0 ) ; if ( GET_CODE ( elt ) != PLUS || ( ! REG_P ( XEXP ( elt , 0 ) ) ) || REGNO ( XEXP ( elt , 0 ) ) != STACK_POINTER_REGNUM || ( ! CONST_INT_P ( XEXP ( elt , 1 ) ) ) || INTVAL ( XEXP ( elt , 1 ) ) != - i * 4 ) return 0 ; } if ( ( mask & 0x3c000 ) != 0 && ( mask & 0x3c000 ) != 0x3c000 ) return 0 ; return mask ; } </s>

Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store ( ) . This function is for MATCH_PARALLEL and so assumes OP is known to be parallel . If OP is a multiple store , return a mask indicating which registers it saves . Return 0 otherwise .


<s> static void finish_bundle_states ( void ) { struct bundle_state * curr_state , * next_state ; for ( curr_state = allocated_bundle_states_chain ; curr_state != NULL ; curr_state = next_state ) { next_state = curr_state -> allocated_states_chain ; free ( curr_state -> dfa_state ) ; free ( curr_state ) ; } } </s>

Finish work with abstract data ` bundle states ' .


<s> void visium_expand_fp_cstore ( rtx * operands , enum machine_mode mode ATTRIBUTE_UNUSED ) { enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; rtx op0 = operands [ 0 ] , op1 = operands [ 2 ] , op2 = operands [ 3 ] , slt ; bool reverse = false ; switch ( code ) { case UNLE : case UNGE : code = reverse_condition_maybe_unordered ( code ) ; reverse = true ; case LT : case GT : if ( code == GT ) { rtx tmp = op1 ; op1 = op2 ; op2 = tmp ; } break ; default : gcc_unreachable ( ) ; } slt = gen_rtx_LT ( SImode , op1 , op2 ) ; if ( reverse ) { rtx tmp = copy_to_mode_reg ( SImode , gen_rtx_NEG ( SImode , slt ) ) ; emit_insn ( gen_add3_insn ( op0 , tmp , const1_rtx ) ) ; } else emit_insn ( gen_rtx_SET ( op0 , slt ) ) ; } </s>

Expand a cstore of OPERANDS in MODE for LT/GT/UNGE/UNLE . We generate the result in the C flag and use the ADC/SUBC instructions to write it into the destination register .


<s> bool X86TargetLowering :: isExtractSubvectorCheap ( EVT ResVT , EVT SrcVT , unsigned Index ) const { if ( ! isOperationLegalOrCustom ( ISD :: EXTRACT_SUBVECTOR , ResVT ) ) return false ; if ( ResVT . getVectorElementType ( ) == MVT :: i1 ) return Index == 0 || ( ( ResVT . getSizeInBits ( ) == SrcVT . getSizeInBits ( ) * 2 ) && ( Index == ResVT . getVectorNumElements ( ) ) ) ; return ( Index % ResVT . getVectorNumElements ( ) ) == 0 ; } </s>

Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index .


<s> SDValue SITargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; DebugLoc DL = N -> getDebugLoc ( ) ; EVT VT = N -> getValueType ( 0 ) ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: SELECT_CC : { N -> dump ( ) ; ConstantSDNode * True , * False ; if ( ( True = dyn_cast < ConstantSDNode > ( N -> getOperand ( 2 ) ) ) && ( False = dyn_cast < ConstantSDNode > ( N -> getOperand ( 3 ) ) ) && True -> isAllOnesValue ( ) && False -> isNullValue ( ) && VT == MVT :: i1 ) { return DAG . getNode ( ISD :: SETCC , DL , VT , N -> getOperand ( 0 ) , N -> getOperand ( 1 ) , N -> getOperand ( 4 ) ) ; } break ; } case ISD :: SETCC : { SDValue Arg0 = N -> getOperand ( 0 ) ; SDValue Arg1 = N -> getOperand ( 1 ) ; SDValue CC = N -> getOperand ( 2 ) ; ConstantSDNode * C = NULL ; ISD :: CondCode CCOp = dyn_cast < CondCodeSDNode > ( CC ) -> get ( ) ; if ( VT == MVT :: i1 && Arg0 . getOpcode ( ) == ISD :: SIGN_EXTEND && Arg0 . getOperand ( 0 ) . getValueType ( ) == MVT :: i1 && ( C = dyn_cast < ConstantSDNode > ( Arg1 ) ) && C -> isNullValue ( ) && CCOp == ISD :: SETNE ) { return SimplifySetCC ( VT , Arg0 . getOperand ( 0 ) , DAG . getConstant ( 0 , MVT :: i1 ) , CCOp , true , DCI , DL ) ; } break ; } } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> bool MCS51DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < MCS51Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> int RV16KFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; int MinCSFI = 0 ; int MaxCSFI = - 1 ; int Offset = MFI . getObjectOffset ( FI ) - getOffsetOfLocalArea ( ) + MFI . getOffsetAdjustment ( ) ; if ( CSI . size ( ) ) { MinCSFI = CSI [ 0 ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - 1 ] . getFrameIdx ( ) ; } FrameReg = RI -> getFrameRegister ( MF ) ; if ( ( FI >= MinCSFI && FI <= MaxCSFI ) || ! hasFP ( MF ) ) { FrameReg = RV16K :: X1 ; Offset += MF . getFrameInfo ( ) . getStackSize ( ) ; } return Offset ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> bool X86TargetLowering :: hasAndNotCompare ( SDValue Y ) const { EVT VT = Y . getValueType ( ) ; if ( VT . isVector ( ) ) return false ; if ( ! Subtarget . hasBMI ( ) ) return false ; if ( VT != MVT :: i32 && VT != MVT :: i64 ) return false ; return ! isa < ConstantSDNode > ( Y ) ; } </s>

Return true if the target should transform : ( X & Y ) == Y � ? ( ~X & Y ) == 0 ( X & Y ) ! = Y � ? ( ~X & Y ) ! = 0 .


<s>
const
MCPhysReg
*
AArch64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_AArch64_NoRegs_SaveList
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_AArch64_AllRegs_SaveList
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
CXX_FAST_TLS
)
return
MF
->
getInfo
<
AArch64FunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_AArch64_CXX_TLS_Darwin_PE_SaveList
:
CSR_AArch64_CXX_TLS_Darwin_SaveList
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
PreserveMost
)
return
CSR_AArch64_RT_MostRegs_SaveList
;
else
return
CSR_AArch64_AAPCS_SaveList
;
}
</s>


<s> void RISCVAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel , MCContext & Ctx ) const { return ; } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool ix86_epilogue_uses ( int regno ) { return ( epilogue_completed && cfun -> machine -> no_caller_saved_registers && ! fixed_regs [ regno ] && ! STACK_REGNO_P ( regno ) && ! MMX_REGNO_P ( regno ) ) ; } </s>

Return true if REGNO is used by the epilogue .


<s>
SDValue
RISCVTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
report_fatal_error
(
"unimplemented operand"
)
;
case
ISD
::
GlobalAddress
:
return
lowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
lowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
lowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
lowerSELECT
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
lowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
lowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
lowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
SHL_PARTS
:
return
lowerShiftLeftParts
(
Op
,
DAG
)
;
case
ISD
::
SRA_PARTS
:
return
lowerShiftRightParts
(
Op
,
DAG
,
true
)
;
case
ISD
::
SRL_PARTS
:
return
lowerShiftRightParts
(
Op
,
DAG
,
false
)
;
case
ISD
::
BITCAST
:
{
assert
(
Subtarget
.
is64Bit
(
)
&&
Subtarget
.
hasStdExtF
(
)
&&
"Unexpected custom legalisation"
)
;
SDLoc
DL
(
Op
)
;
SDValue
Op0
=
Op
.
getOperand
(
0
)
;
if
(
Op
.
getValueType
(
)
!=
MVT
::
f32
||
Op0
.
getValueType
(
)
!=
MVT
::
i32
)
return
SDValue
(
)
;
SDValue
NewOp0
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
DL
,
MVT
::
i64
,
Op0
)
;
SDValue
FPConv
=
DAG
.
getNode
(
RISCVISD
::
FMV_W_X_RV64
,
DL
,
MVT
::
f32
,
NewOp0
)
;
return
FPConv
;
}
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> Value * AArch64TargetLowering :: emitStoreConditional ( IRBuilder < > & Builder , Value * Val , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = isReleaseOrStronger ( Ord ) ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == 128 ) { Intrinsic :: ID Int = IsRelease ? Intrinsic :: aarch64_stlxp : Intrinsic :: aarch64_stxp ; Function * Stxr = Intrinsic :: getDeclaration ( M , Int ) ; Type * Int64Ty = Type :: getInt64Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int64Ty , "lo" ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , 64 ) , Int64Ty , "hi" ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall ( Stxr , { Lo , Hi , Addr } ) ; } Intrinsic :: ID Int = IsRelease ? Intrinsic :: aarch64_stlxr : Intrinsic :: aarch64_stxr ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Stxr = Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateCall ( Stxr , { Builder . CreateZExtOrBitCast ( Val , Stxr -> getFunctionType ( ) -> getParamType ( 0 ) ) , Addr } ) ; } </s>

Perform a store-conditional operation to Addr .


<s> bool AMDGPUCFGStructurizer :: prepare ( ) { bool Changed = false ; LLVM_DEBUG ( dbgs ( ) << "AMDGPUCFGStructurizer::prepare\n" ; ) ; orderBlocks ( FuncRep ) ; SmallVector < MachineBasicBlock * , DEFAULT_VEC_SLOTS > RetBlks ; for ( MachineLoop * LoopRep : * MLI ) { MBBVector ExitingMBBs ; LoopRep -> getExitingBlocks ( ExitingMBBs ) ; if ( ExitingMBBs . size ( ) == 0 ) { MachineBasicBlock * DummyExitBlk = normalizeInfiniteLoopExit ( LoopRep ) ; if ( DummyExitBlk ) RetBlks . push_back ( DummyExitBlk ) ; } } for ( MachineBasicBlock * MBB : OrderedBlks ) { removeUnconditionalBranch ( MBB ) ; removeRedundantConditionalBranch ( MBB ) ; if ( isReturnBlock ( MBB ) ) { RetBlks . push_back ( MBB ) ; } assert ( MBB -> succ_size ( ) <= 2 ) ; } if ( RetBlks . size ( ) >= 2 ) { addDummyExitBlock ( RetBlks ) ; Changed = true ; } return Changed ; } </s>

prepare - Reset state and prepare for a new spill placement computation .


Return the bytes needed to compute the frame pointer from the current stack pointer . SIZE is the size needed for local variables .


<s> virtual const PPCInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> static bool valid_src_p ( rtx src , rtx_insn * insn , struct loop * loop , bool * pre_post , rtx * base , rtx * offset , bool load_pair ) { subrtx_var_iterator :: array_type array ; rtx x = NULL_RTX ; FOR_EACH_SUBRTX_VAR ( iter , array , src , NONCONST ) if ( MEM_P ( * iter ) ) { x = * iter ; break ; } if ( ! x ) return false ; struct aarch64_address_info addr ; machine_mode mode = GET_MODE ( x ) ; if ( ! aarch64_classify_address ( & addr , XEXP ( x , 0 ) , mode , true ) ) return false ; if ( addr . type != ADDRESS_REG_IMM && addr . type != ADDRESS_REG_WB && addr . type != ADDRESS_REG_REG && addr . type != ADDRESS_REG_UXTW && addr . type != ADDRESS_REG_SXTW ) return false ; unsigned regno = REGNO ( addr . base ) ; if ( global_regs [ regno ] || fixed_regs [ regno ] ) return false ; if ( addr . type == ADDRESS_REG_WB ) { unsigned code = GET_CODE ( XEXP ( x , 0 ) ) ; * pre_post = true ; * base = addr . base ; if ( code == PRE_MODIFY || code == POST_MODIFY ) * offset = addr . offset ; else { unsigned int_offset = GET_MODE_SIZE ( mode ) . to_constant ( ) ; if ( load_pair && ( code == POST_INC || code == POST_DEC ) ) int_offset *= 2 ; * offset = GEN_INT ( int_offset ) ; } return true ; } else if ( addr . type == ADDRESS_REG_IMM || addr . type == ADDRESS_REG_REG ) { if ( ! iv_p ( insn , addr . base , loop ) ) return false ; * base = addr . base ; * offset = addr . offset ; return true ; } return false ; } </s>

Return true if SRC is a strided load in the LOOP , false otherwise . If it is a strided load , set the BASE and OFFSET . Also , if this is a pre/post increment load , set PRE_POST to true .


<s> static void m68k_asm_final_postscan_insn ( FILE * , rtx_insn * insn , rtx [ ] , int ) { enum attr_flags_valid v = get_attr_flags_valid ( insn ) ; if ( v == FLAGS_VALID_SET ) return ; flags_compare_op0 = flags_compare_op1 = NULL_RTX ; if ( v == FLAGS_VALID_NO ) { flags_operand1 = flags_operand2 = NULL_RTX ; return ; } else if ( v == FLAGS_VALID_UNCHANGED ) { if ( flags_operand1 != NULL_RTX && modified_in_p ( flags_operand1 , insn ) ) flags_operand1 = NULL_RTX ; if ( flags_operand2 != NULL_RTX && modified_in_p ( flags_operand2 , insn ) ) flags_operand2 = NULL_RTX ; return ; } flags_valid = v ; rtx set = single_set ( insn ) ; rtx dest = SET_DEST ( set ) ; rtx src = SET_SRC ( set ) ; if ( side_effects_p ( dest ) ) dest = NULL_RTX ; switch ( v ) { case FLAGS_VALID_YES : case FLAGS_VALID_NOOV : flags_operand1 = dest ; flags_operand2 = NULL_RTX ; break ; case FLAGS_VALID_MOVE : if ( dest != NULL_RTX && ! FP_REG_P ( dest ) && ( FP_REG_P ( src ) || GET_CODE ( src ) == FIX || FLOAT_MODE_P ( GET_MODE ( dest ) ) ) ) flags_operand1 = flags_operand2 = NULL_RTX ; else { flags_operand1 = dest ; if ( GET_MODE ( src ) != VOIDmode && ! side_effects_p ( src ) && ! modified_in_p ( src , insn ) ) flags_operand2 = src ; else flags_operand2 = NULL_RTX ; } break ; default : gcc_unreachable ( ) ; } return ; } </s>

Process INSN to remember flag operands if possible .


<s> static rtx moxie_static_chain ( const_tree ARG_UNUSED ( fndecl_or_type ) , bool incoming_p ) { rtx addr , mem ; if ( incoming_p ) addr = plus_constant ( Pmode , arg_pointer_rtx , 2 * UNITS_PER_WORD ) ; else addr = plus_constant ( Pmode , stack_pointer_rtx , - UNITS_PER_WORD ) ; mem = gen_rtx_MEM ( Pmode , addr ) ; MEM_NOTRAP_P ( mem ) = 1 ; return mem ; } </s>

Worker function for TARGET_STATIC_CHAIN .


<s> bool XCoreTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( Ty -> getTypeID ( ) == Type :: VoidTyID ) return AM . Scale == 0 && isImmUs ( AM . BaseOffs ) && isImmUs4 ( AM . BaseOffs ) ; const DataLayout * TD = TM . getDataLayout ( ) ; unsigned Size = TD -> getTypeAllocSize ( Ty ) ; if ( AM . BaseGV ) { return Size >= 4 && ! AM . HasBaseReg && AM . Scale == 0 && AM . BaseOffs % 4 == 0 ; } switch ( Size ) { case 1 : if ( AM . Scale == 0 ) { return isImmUs ( AM . BaseOffs ) ; } return AM . Scale == 1 && AM . BaseOffs == 0 ; case 2 : case 3 : if ( AM . Scale == 0 ) { return isImmUs2 ( AM . BaseOffs ) ; } return AM . Scale == 2 && AM . BaseOffs == 0 ; default : if ( AM . Scale == 0 ) { return isImmUs4 ( AM . BaseOffs ) ; } return AM . Scale == 4 && AM . BaseOffs == 0 ; } } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


"Store results: call to builtin function "

"with wrong signature, from/to mismatch"

"with wrong signature, not consuming reg or "

runOnMachineFunction - Emit the function body .