<s> struct rtx_def * function_arg ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int named ATTRIBUTE_UNUSED ) { int bytes = ( mode == BLKmode ) ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ; if ( mode == VOIDmode ) return GEN_INT ( cum -> call_cookie ) ; if ( bytes == - 1 ) return NULL_RTX ; if ( cum -> nregs ) return gen_rtx_REG ( mode , * ( cum -> arg_regs ) ) ; return NULL_RTX ; } </s>

Return an RTL expression containing the register for the given mode , or 0 if the argument is to be passed on the stack . INCOMING_P is nonzero if this is an incoming argument to the current function .


<s> SMLoc getEndLoc ( ) const { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> virtual const TargetRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


Return the bytes needed to compute the frame pointer from the current stack pointer .


<s> static unsigned int aarch64_call_properties ( unsigned int flags , machine_mode mode ) { if ( ! ( flags & FLAG_AUTO_FP ) && FLOAT_MODE_P ( mode ) ) flags |= FLAG_FP ; if ( ! flag_trapping_math ) flags &= ~ FLAG_RAISE_FP_EXCEPTIONS ; return flags ; } </s>

Return a set of FLAG_ * flags that describe what the function could do , taking the command-line flags into account .


<s> bool AMDGPUInstrInfo :: isPredicable ( MachineInstr * MI ) const { return MI -> getDesc ( ) . isPredicable ( ) ; } </s>

Return true if the specified instruction can be predicated .


<s> void AArch64TargetLowering :: LowerOperationWrapper ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { SDValue Res = LowerOperation ( SDValue ( N , 0 ) , DAG ) ; if ( Res . getNode ( ) ) for ( unsigned I = 0 , E = Res -> getNumValues ( ) ; I != E ; ++ I ) Results . push_back ( Res . getValue ( I ) ) ; } </s>

This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types .


<s> static bool isShift ( MachineInstr * MI , unsigned Opcode , int64_t Imm ) { return ( MI -> getOpcode ( ) == Opcode && ! MI -> getOperand ( 2 ) . getReg ( ) && MI -> getOperand ( 3 ) . getImm ( ) == Imm ) ; } </s>

Determine if the Opcode is one of the shift instructions .


<s> static bool rs6000_secondary_reload_direct_move ( enum rs6000_reg_type to_type , enum rs6000_reg_type from_type , machine_mode mode , secondary_reload_info * sri , bool altivec_p ) { bool ret = false ; enum insn_code icode = CODE_FOR_nothing ; int cost = 0 ; int size = GET_MODE_SIZE ( mode ) ; if ( TARGET_POWERPC64 ) { if ( size == 16 ) { if ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) { cost = 3 ; icode = reg_addr [ mode ] . reload_vsx_gpr ; } else if ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) { cost = 3 ; icode = reg_addr [ mode ] . reload_gpr_vsx ; } } else if ( mode == SFmode ) { if ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) { cost = 3 ; icode = reg_addr [ mode ] . reload_gpr_vsx ; } else if ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) { cost = 2 ; icode = reg_addr [ mode ] . reload_vsx_gpr ; } } } if ( TARGET_POWERPC64 && size == 16 ) { if ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) { cost = 3 ; icode = reg_addr [ mode ] . reload_vsx_gpr ; } else if ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) { cost = 3 ; icode = reg_addr [ mode ] . reload_gpr_vsx ; } } else if ( ! TARGET_POWERPC64 && size == 8 ) { if ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE && ! altivec_p ) { cost = 3 ; icode = reg_addr [ mode ] . reload_fpr_gpr ; } } if ( icode != CODE_FOR_nothing ) { ret = true ; if ( sri ) { sri -> icode = icode ; sri -> extra_cost = cost ; } } return ret ; } </s>

Power8 helper function for rs6000_secondary_reload , handle all of the special direct moves that involve allocating an extra register , return the insn code of the helper function if there is such a function or CODE_FOR_nothing if not .


<s> unsigned X86TTIImpl :: getIntImmCost ( Intrinsic :: ID IID , unsigned Idx , const APInt & Imm , Type * Ty ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; switch ( IID ) { default : return TTI :: TCC_Free ; case Intrinsic :: sadd_with_overflow : case Intrinsic :: uadd_with_overflow : case Intrinsic :: ssub_with_overflow : case Intrinsic :: usub_with_overflow : case Intrinsic :: smul_with_overflow : case Intrinsic :: umul_with_overflow : if ( ( Idx == 1 ) && Imm . getBitWidth ( ) <= 64 && isInt < 32 > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; break ; case Intrinsic :: experimental_stackmap : if ( ( Idx < 2 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; case Intrinsic :: experimental_patchpoint_void : case Intrinsic :: experimental_patchpoint_i64 : if ( ( Idx < 4 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; } return X86TTIImpl :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> static int iq2000_address_cost ( rtx addr ) { switch ( GET_CODE ( addr ) ) { case LO_SUM : return 1 ; case LABEL_REF : return 2 ; case CONST : { rtx offset = const0_rtx ; addr = eliminate_constant_term ( XEXP ( addr , 0 ) , & offset ) ; if ( GET_CODE ( addr ) == LABEL_REF ) return 2 ; if ( GET_CODE ( addr ) != SYMBOL_REF ) return 4 ; if ( ! SMALL_INT ( offset ) ) return 2 ; } case SYMBOL_REF : return SYMBOL_REF_FLAG ( addr ) ? 1 : 2 ; case PLUS : { rtx plus0 = XEXP ( addr , 0 ) ; rtx plus1 = XEXP ( addr , 1 ) ; if ( GET_CODE ( plus0 ) != REG && GET_CODE ( plus1 ) == REG ) plus0 = XEXP ( addr , 1 ) , plus1 = XEXP ( addr , 0 ) ; if ( GET_CODE ( plus0 ) != REG ) break ; switch ( GET_CODE ( plus1 ) ) { case CONST_INT : return SMALL_INT ( plus1 ) ? 1 : 2 ; case CONST : case SYMBOL_REF : case LABEL_REF : case HIGH : case LO_SUM : return iq2000_address_cost ( plus1 ) + 1 ; default : break ; } } default : break ; } return 4 ; } </s>

Provide the costs of an addressing mode that contains ADDR .


<s> static int bfin_arg_partial_bytes ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { int bytes = ( mode == BLKmode ) ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ; int bytes_left = cum -> nregs * UNITS_PER_WORD ; if ( bytes == - 1 ) return 0 ; if ( bytes_left == 0 ) return 0 ; if ( bytes > bytes_left ) return bytes_left ; return 0 ; } </s>

For an arg passed partly in registers and partly in memory , this is the number of bytes passed in registers . For args passed entirely in registers or entirely in memory , zero . Refer VDSP C Compiler manual , our ABI . First 3 words are in registers . So , if a an argument is larger than the registers available , it will span the register and stack .


<s> int avr_starting_frame_offset ( void ) { return 1 + avr_outgoing_args_size ( ) ; } </s>

This is the offset from the frame pointer register to the first stack slot that contains a variable living in the frame .


<s> bool RegDefsUses :: update ( const MachineInstr & MI , unsigned Begin , unsigned End ) { BitVector NewDefs ( TRI . getNumRegs ( ) ) , NewUses ( TRI . getNumRegs ( ) ) ; bool HasHazard = false ; for ( unsigned I = Begin ; I != End ; ++ I ) { const MachineOperand & MO = MI . getOperand ( I ) ; if ( MO . isReg ( ) && MO . getReg ( ) ) HasHazard |= checkRegDefsUses ( NewDefs , NewUses , MO . getReg ( ) , MO . isDef ( ) ) ; } Defs |= NewDefs ; Uses |= NewUses ; return HasHazard ; } </s>


<s> void WebAssemblyPassConfig :: addPostRegAlloc ( ) { disablePass ( & PrologEpilogCodeInserterID ) ; disablePass ( & MachineCopyPropagationID ) ; addPass ( createWebAssemblyRegStackify ( ) ) ; addPass ( createWebAssemblyRegColoring ( ) ) ; TargetPassConfig :: addPostRegAlloc ( ) ; addPass ( createWebAssemblyPEI ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .

WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly


"Only base registers and frame indices are supported."

Returns true if the two given memory operations should be scheduled adjacent .


<s> WebAssemblySubtarget :: WebAssemblySubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : WebAssemblyGenSubtargetInfo ( TT , CPU , FS ) , CPUString ( CPU ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS ) ) , TSInfo ( ) , TLInfo ( TM , * this ) { } </s>

This constructor initializes the data members to match that of the specified triple .

WebAssembly WebAssembly WebAssembly WebAssembly


<s> void P2InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const DebugLoc & DL , MCRegister DestReg , MCRegister SrcReg , bool KillSrc ) const { if ( SrcReg == P2 :: QX ) { BuildMI ( MBB , MI , DL , get ( P2 :: GETQX ) , DestReg ) ; } else if ( SrcReg == P2 :: QY ) { BuildMI ( MBB , MI , DL , get ( P2 :: GETQY ) , DestReg ) ; } else { BuildMI ( MBB , MI , DL , get ( P2 :: MOVrr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } } </s>


<s>
bool
X86AsmParser
::
ParseDirective
(
AsmToken
DirectiveID
)
{
MCAsmParser
&
Parser
=
getParser
(
)
;
StringRef
IDVal
=
DirectiveID
.
getIdentifier
(
)
;
if
(
IDVal
==
".word"
)
return
ParseDirectiveWord
(
2
,
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
.
startswith
(
".code"
)
)
return
ParseDirectiveCode
(
IDVal
,
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
.
startswith
(
".att_syntax"
)
)
{
getParser
(
)
.
setParsingInlineAsm
(
false
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.att_syntax noprefix' is not "
"supported: registers must have a "
"'%' prefix in .att_syntax"
)
;
}
getParser
(
)
.
setAssemblerDialect
(
0
)
;
return
false
;
}
else
if
(
IDVal
.
startswith
(
".intel_syntax"
)
)
{
getParser
(
)
.
setAssemblerDialect
(
1
)
;
getParser
(
)
.
setParsingInlineAsm
(
true
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.intel_syntax prefix' is not "
"supported: registers must not have "
"a '%' prefix in .intel_syntax"
)
;
}
return
false
;
}
else
if
(
IDVal
==
".even"
)
return
parseDirectiveEven
(
DirectiveID
.
getLoc
(
)
)
;
return
true
;
}
</s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool BlackfinAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; O << '[' ; printOperand ( MI , OpNo ) ; O << ']' ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> void ARMBaseInstrInfo :: mergeOutliningCandidateAttributes ( Function & F , std :: vector < outliner :: Candidate > & Candidates ) const { outliner :: Candidate & C = Candidates . front ( ) ; const Function & CFn = C . getMF ( ) -> getFunction ( ) ; if ( CFn . hasFnAttribute ( "branch-target-enforcement" ) ) F . addFnAttr ( CFn . getFnAttribute ( "branch-target-enforcement" ) ) ; ARMGenInstrInfo :: mergeOutliningCandidateAttributes ( F , Candidates ) ; } </s>

Optional target hook to create the LLVM IR attributes for the outlined function .

ARM ARM "branch-target-enforcement" "branch-target-enforcement" ARM


<s> bool PatmosInstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( MI . isDebugValue ( ) ) return false ; if ( MI . getDesc ( ) . isTerminator ( ) || MI . isLabel ( ) ) return true ; return false ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> static void mips_process_load_label ( rtx target ) { rtx base , gp , intop ; HOST_WIDE_INT offset ; mips_multi_start ( ) ; switch ( mips_abi ) { case ABI_N32 : mips_multi_add_insn ( "lw\t%@,%%got_page(%0)(%+)" , target , 0 ) ; mips_multi_add_insn ( "addiu\t%@,%@,%%got_ofst(%0)" , target , 0 ) ; break ; case ABI_64 : mips_multi_add_insn ( "ld\t%@,%%got_page(%0)(%+)" , target , 0 ) ; mips_multi_add_insn ( "daddiu\t%@,%@,%%got_ofst(%0)" , target , 0 ) ; break ; default : gp = pic_offset_table_rtx ; if ( mips_cfun_has_cprestore_slot_p ( ) ) { gp = gen_rtx_REG ( Pmode , AT_REGNUM ) ; mips_get_cprestore_base_and_offset ( & base , & offset , true ) ; if ( ! SMALL_OPERAND ( offset ) ) { intop = GEN_INT ( CONST_HIGH_PART ( offset ) ) ; mips_multi_add_insn ( "lui\t%0,%1" , gp , intop , 0 ) ; mips_multi_add_insn ( "addu\t%0,%0,%1" , gp , base , 0 ) ; base = gp ; offset = CONST_LOW_PART ( offset ) ; } intop = GEN_INT ( offset ) ; if ( ISA_HAS_LOAD_DELAY ) mips_multi_add_insn ( "lw\t%0,%1(%2)%#" , gp , intop , base , 0 ) ; else mips_multi_add_insn ( "lw\t%0,%1(%2)" , gp , intop , base , 0 ) ; } if ( ISA_HAS_LOAD_DELAY ) mips_multi_add_insn ( "lw\t%@,%%got(%0)(%1)%#" , target , gp , 0 ) ; else mips_multi_add_insn ( "lw\t%@,%%got(%0)(%1)" , target , gp , 0 ) ; mips_multi_add_insn ( "addiu\t%@,%@,%%lo(%0)" , target , 0 ) ; break ; } } </s>

Build up a multi-insn sequence that loads label TARGET into $ AT .


<s> static int s390_function_arg_size ( machine_mode mode , const_tree type ) { if ( type ) return int_size_in_bytes ( type ) ; if ( mode != BLKmode ) return GET_MODE_SIZE ( mode ) ; gcc_unreachable ( ) ; } </s>

Return the size in bytes of a function argument of type TYPE and/or mode MODE . At least one of TYPE or MODE must be specified .


<s> static bool s390_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { return ( ( mode1 == SFmode || mode1 == DFmode ) == ( mode2 == SFmode || mode2 == DFmode ) ) ; } </s>


<s> static void arc_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int bytes = ( mode == BLKmode ? int_size_in_bytes ( type ) : ( int ) GET_MODE_SIZE ( mode ) ) ; int words = ( bytes + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; int i ; if ( words ) * cum = ROUND_ADVANCE_CUM ( * cum , mode , type ) ; for ( i = 0 ; i < words ; i ++ ) * cum = ARC_NEXT_ARG_REG ( * cum ) ; } </s>

For the ARC : the cum set here is passed on to function_arg where we look at its value and say which reg to use . Strategy : advance the regnumber here till we run out of arg regs , then set * cum to last reg . In function_arg , since * cum > last arg reg we would return 0 and thus the arg will end up on the stack . For straddling args of course function_arg_partial_nregs will come into play .


<s> void SystemZXPLINKFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; bool HasFP = hasFP ( MF ) ; const SystemZSubtarget & Subtarget = MF . getSubtarget < SystemZSubtarget > ( ) ; auto & Regs = Subtarget . getSpecialRegisters < SystemZXPLINK64Registers > ( ) ; if ( HasFP ) SavedRegs . set ( Regs . getFramePointerRegister ( ) ) ; SavedRegs . set ( Regs . getReturnFunctionAddressRegister ( ) ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Mips Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
const
char
*
vfp_output_vstmd
(
rtx
*
operands
)
{
char
pattern
[
100
]
;
int
p
;
int
base
;
int
i
;
rtx
addr_reg
=
REG_P
(
XEXP
(
operands
[
0
]
,
0
)
)
XEXP
(
operands
[
0
]
,
0
)
:
XEXP
(
XEXP
(
operands
[
0
]
,
0
)
,
0
)
;
bool
push_p
=
REGNO
(
addr_reg
)
==
SP_REGNUM
;
if
(
push_p
)
strcpy
(
pattern
,
"vpush%?.64\t{%P1"
)
;
else
strcpy
(
pattern
,
"vstmdb%?.64\t%m0!, {%P1"
)
;
p
=
strlen
(
pattern
)
;
gcc_assert
(
REG_P
(
operands
[
1
]
)
)
;
base
=
(
REGNO
(
operands
[
1
]
)
FIRST_VFP_REGNUM
)
/
2
;
for
(
i
=
1
;
i
<
XVECLEN
(
operands
[
2
]
,
0
)
;
i
++
)
{
p
+=
sprintf
(
&
pattern
[
p
]
,
", d%d"
,
base
+
i
)
;
}
strcpy
(
&
pattern
[
p
]
,
"}"
)
;
output_asm_insn
(
pattern
,
operands
)
;
return
""
;
}
</s>

Output the assembly for a store multiple .


<s> MachineInstr * SIInstrInfo :: commuteInstruction ( MachineInstr * MI , bool NewMI ) const { if ( MI -> getNumOperands ( ) < 3 || ! MI -> getOperand ( 1 ) . isReg ( ) || ! MI -> getOperand ( 2 ) . isReg ( ) ) return 0 ; return TargetInstrInfo :: commuteInstruction ( MI , NewMI ) ; } </s>

This method commutes the operands of the given machine instruction MI .


<s> LiveRange ( unsigned virtReg ) : LiveRange ( ) { virtRegs . insert ( virtReg ) ; } </s>

Constructs a new LiveRange object by copying segments and valnos from another LiveRange .


<s> SDValue TOYTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InGlue , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { assert ( ! isVarArg && "Unsupported" ) ; SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_TOY ) ; for ( auto & Loc : RVLocs ) { Chain = DAG . getCopyFromReg ( Chain , dl , Loc . getLocReg ( ) , Loc . getValVT ( ) , InGlue ) . getValue ( 1 ) ; InGlue = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


"Fallthrough blocks can have only one predecessor"

"Last operand in a LOOP instruction should be a block"

isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> SDNode * SITargetLowering :: PostISelFolding ( MachineSDNode * Node , SelectionDAG & DAG ) const { Node = AdjustRegClass ( Node , DAG ) ; if ( AMDGPU :: isMIMG ( Node -> getMachineOpcode ( ) ) != - 1 ) adjustWritemask ( Node , DAG ) ; return foldOperands ( Node , DAG ) ; } </s>

Fold the instructions after selecting them .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> unsigned char M680x0Subtarget :: classifyExternalReference ( const Module & M ) const { if ( TM . shouldAssumeDSOLocal ( M , nullptr ) ) return classifyLocalReference ( nullptr ) ; if ( isPositionIndependent ( ) ) { return M680x0II :: MO_GOTPCREL ; } else { return M680x0II :: MO_GOT ; } } </s>

Classify a external variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s>
void
Thumb1InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tMOVr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
)
;
assert
(
ARM
::
GPRRegClass
.
contains
(
DestReg
,
SrcReg
)
&&
"Thumb1 can only copy GPR registers"
)
;
}
</s>

ARM
ARM::tMOVr
ARM::GPRRegClass
"Thumb1 can only copy GPR registers"


<s> static X86Operand * CreateReg ( unsigned RegNo , SMLoc StartLoc , SMLoc EndLoc , bool AddressOf = false , SMLoc OffsetOfLoc = SMLoc ( ) ) { X86Operand * Res = new X86Operand ( Register , StartLoc , EndLoc ) ; Res -> Reg . RegNo = RegNo ; Res -> AddressOf = AddressOf ; Res -> OffsetOfLoc = OffsetOfLoc ; return Res ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> static bool arc_in_small_data_p ( const_tree decl ) { HOST_WIDE_INT size ; if ( TREE_CODE ( decl ) == STRING_CST || TREE_CODE ( decl ) == FUNCTION_DECL ) return false ; if ( TARGET_NO_SDATA_SET ) return false ; if ( TREE_CODE ( decl ) == VAR_DECL && DECL_SECTION_NAME ( decl ) != 0 ) { const char * name ; name = DECL_SECTION_NAME ( decl ) ; if ( strcmp ( name , ".sdata" ) != 0 && strcmp ( name , ".sbss" ) != 0 ) return false ; if ( ! DECL_EXTERNAL ( decl ) ) return true ; } else if ( 1 ) { if ( TREE_CODE ( decl ) != VAR_DECL ) return false ; if ( TREE_READONLY ( decl ) && ! TREE_SIDE_EFFECTS ( decl ) && ( ! DECL_INITIAL ( decl ) || TREE_CONSTANT ( DECL_INITIAL ( decl ) ) ) ) return false ; if ( default_binds_local_p_1 ( decl , 1 ) || arc_decl_anon_ns_mem_p ( decl ) ) return false ; if ( TREE_THIS_VOLATILE ( decl ) ) return false ; } if ( DECL_WEAK ( decl ) ) return false ; size = int_size_in_bytes ( TREE_TYPE ( decl ) ) ; return ( size > 0 && size <= 4 ) ; } </s>

Implement TARGET_IN_SMALL_DATA_P . Return true if it would be safe to access DECL using % gp_rel ( ... ) ( $ gp ) .


<s> bool nds32_n7_load_to_ii_p ( rtx_insn * producer , rtx_insn * consumer ) { if ( post_update_insn_p ( producer ) ) return false ; rtx def_reg = SET_DEST ( PATTERN ( producer ) ) ; return n7_consumed_by_ii_dep_p ( consumer , def_reg ) ; } </s>


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s>
void
ARM64AppleInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
O
,
StringRef
Annot
)
{
unsigned
Opcode
=
MI
->
getOpcode
(
)
;
StringRef
Layout
,
Mnemonic
;
bool
IsTbx
;
if
(
isTblTbxInstruction
(
MI
->
getOpcode
(
)
,
Layout
,
IsTbx
)
)
{
O
<<
"\t"
<<
(
IsTbx
"tbx"
:
"tbl"
)
<<
Layout
<<
'\t'
<<
getRegisterName
(
MI
->
getOperand
(
0
)
.
getReg
(
)
,
ARM64
::
vreg
)
<<
", "
;
unsigned
ListOpNum
=
IsTbx
2
:
1
;
printVectorList
(
MI
,
ListOpNum
,
O
,
""
)
;
O
<<
", "
<<
getRegisterName
(
MI
->
getOperand
(
ListOpNum
+
1
)
.
getReg
(
)
,
ARM64
::
vreg
)
;
printAnnotation
(
O
,
Annot
)
;
return
;
}
if
(
LdStNInstrDesc
*
LdStDesc
=
getLdStNInstrDesc
(
Opcode
)
)
{
O
<<
"\t"
<<
LdStDesc
->
Mnemonic
<<
LdStDesc
->
Layout
<<
'\t'
;
int
OpNum
=
LdStDesc
->
ListOperand
;
printVectorList
(
MI
,
OpNum
++
,
O
,
""
)
;
if
(
LdStDesc
->
HasLane
)
O
<<
'['
<<
MI
->
getOperand
(
OpNum
++
)
.
getImm
(
)
<<
']'
;
unsigned
AddrReg
=
MI
->
getOperand
(
OpNum
++
)
.
getReg
(
)
;
O
<<
", ["
<<
getRegisterName
(
AddrReg
)
<<
']'
;
if
(
LdStDesc
->
NaturalOffset
!=
0
)
{
unsigned
Reg
=
MI
->
getOperand
(
OpNum
++
)
.
getReg
(
)
;
if
(
Reg
!=
ARM64
::
XZR
)
O
<<
", "
<<
getRegisterName
(
Reg
)
;
else
{
assert
(
LdStDesc
->
NaturalOffset
&&
"no offset on post-inc instruction?"
)
;
O
<<
", #"
<<
LdStDesc
->
NaturalOffset
;
}
}
printAnnotation
(
O
,
Annot
)
;
return
;
}
ARM64InstPrinter
::
printInst
(
MI
,
O
,
Annot
)
;
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s> void SITargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { switch ( N -> getOpcode ( ) ) { case ISD :: INSERT_VECTOR_ELT : { if ( SDValue Res = lowerINSERT_VECTOR_ELT ( SDValue ( N , 0 ) , DAG ) ) Results . push_back ( Res ) ; return ; } case ISD :: EXTRACT_VECTOR_ELT : { if ( SDValue Res = lowerEXTRACT_VECTOR_ELT ( SDValue ( N , 0 ) , DAG ) ) Results . push_back ( Res ) ; return ; } case ISD :: INTRINSIC_WO_CHAIN : { unsigned IID = cast < ConstantSDNode > ( N -> getOperand ( 0 ) ) -> getZExtValue ( ) ; if ( IID == Intrinsic :: amdgcn_cvt_pkrtz ) { SDValue Src0 = N -> getOperand ( 1 ) ; SDValue Src1 = N -> getOperand ( 2 ) ; SDLoc SL ( N ) ; SDValue Cvt = DAG . getNode ( AMDGPUISD :: CVT_PKRTZ_F16_F32 , SL , MVT :: i32 , Src0 , Src1 ) ; Results . push_back ( DAG . getNode ( ISD :: BITCAST , SL , MVT :: v2f16 , Cvt ) ) ; return ; } break ; } case ISD :: SELECT : { SDLoc SL ( N ) ; EVT VT = N -> getValueType ( 0 ) ; EVT NewVT = getEquivalentMemType ( * DAG . getContext ( ) , VT ) ; SDValue LHS = DAG . getNode ( ISD :: BITCAST , SL , NewVT , N -> getOperand ( 1 ) ) ; SDValue RHS = DAG . getNode ( ISD :: BITCAST , SL , NewVT , N -> getOperand ( 2 ) ) ; EVT SelectVT = NewVT ; if ( NewVT . bitsLT ( MVT :: i32 ) ) { LHS = DAG . getNode ( ISD :: ANY_EXTEND , SL , MVT :: i32 , LHS ) ; RHS = DAG . getNode ( ISD :: ANY_EXTEND , SL , MVT :: i32 , RHS ) ; SelectVT = MVT :: i32 ; } SDValue NewSelect = DAG . getNode ( ISD :: SELECT , SL , SelectVT , N -> getOperand ( 0 ) , LHS , RHS ) ; if ( NewVT != SelectVT ) NewSelect = DAG . getNode ( ISD :: TRUNCATE , SL , NewVT , NewSelect ) ; Results . push_back ( DAG . getNode ( ISD :: BITCAST , SL , VT , NewSelect ) ) ; return ; } default : break ; } } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"RISCV Assembly Printer"
;
}
</s>


<s> TargetPassConfig * LanaiTargetMachine :: createPassConfig ( PassManagerBase & PassManager ) { return new LanaiPassConfig ( this , & PassManager ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


"SIInstrInfo::storeRegToStackSlot - Do not know how to"

Store the specified register of the given register class to the specified stack frame index .


<s> static rtx_insn * thumb1_emit_multi_reg_push ( unsigned long mask , unsigned long real_regs ) { unsigned long regno ; rtx par [ 10 ] , tmp , reg ; rtx_insn * insn ; int i , j ; for ( i = 0 ; mask ; ++ i , mask &= mask - 1 ) { regno = ctz_hwi ( mask ) ; reg = gen_rtx_REG ( SImode , regno ) ; if ( i == 0 ) tmp = gen_rtx_UNSPEC ( BLKmode , gen_rtvec ( 1 , reg ) , UNSPEC_PUSH_MULT ) ; else tmp = gen_rtx_USE ( VOIDmode , reg ) ; par [ i ] = tmp ; } tmp = plus_constant ( Pmode , stack_pointer_rtx , - 4 * i ) ; tmp = gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , tmp ) ; tmp = gen_frame_mem ( BLKmode , tmp ) ; tmp = gen_rtx_SET ( VOIDmode , tmp , par [ 0 ] ) ; par [ 0 ] = tmp ; tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( i , par ) ) ; insn = emit_insn ( tmp ) ; tmp = plus_constant ( Pmode , stack_pointer_rtx , - 4 * i ) ; tmp = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , tmp ) ; par [ 0 ] = tmp ; for ( j = 0 ; real_regs ; ++ j , real_regs &= real_regs - 1 ) { regno = ctz_hwi ( real_regs ) ; reg = gen_rtx_REG ( SImode , regno ) ; tmp = plus_constant ( Pmode , stack_pointer_rtx , j * 4 ) ; tmp = gen_frame_mem ( SImode , tmp ) ; tmp = gen_rtx_SET ( VOIDmode , tmp , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; par [ j + 1 ] = tmp ; } if ( j == 0 ) tmp = par [ 0 ] ; else { RTX_FRAME_RELATED_P ( par [ 0 ] ) = 1 ; tmp = gen_rtx_SEQUENCE ( VOIDmode , gen_rtvec_v ( j + 1 , par ) ) ; } add_reg_note ( insn , REG_FRAME_RELATED_EXPR , tmp ) ; return insn ; } </s>

Like emit_multi_reg_push , but allowing for a different set of registers to be described as saved . MASK is the set of registers to be saved ; REAL_REGS is the set of registers to be described as saved . If REAL_REGS is 0 , only describe the stack adjustment .


<s>
uint64_t
SystemZMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
)
const
{
if
(
MO
.
isReg
(
)
)
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
if
(
MO
.
isImm
(
)
)
return
static_cast
<
uint64_t
>
(
MO
.
getImm
(
)
)
;
llvm_unreachable
(
"Unexpected operand type!"
)
;
}
</s>

getMachineOpValue - Return binary encoding of operand .

SystemZ
SystemZ
"Unexpected operand type!"


<s> void X86PassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( new X86ExecutionDomainFix ( ) ) ; addPass ( createBreakFalseDeps ( ) ) ; } addPass ( createX86IndirectBranchTrackingPass ( ) ) ; if ( UseVZeroUpper ) addPass ( createX86IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86FixupBWInsts ( ) ) ; addPass ( createX86PadShortFunctions ( ) ) ; addPass ( createX86FixupLEAs ( ) ) ; addPass ( createX86EvexToVexInsts ( ) ) ; } } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
TargetLowering
::
ConstraintWeight
AArch64TargetLowering
::
getSingleConstraintMatchWeight
(
AsmOperandInfo
&
Info
,
const
char
*
Constraint
)
const
{
llvm_unreachable
(
"Constraint weight unimplemented"
)
;
}
</s>

Examine constraint string and operand type and determine a weight value .


<s>
SDValue
MSP430TargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
if
(
CallConv
==
CallingConv
::
MSP430_INTR
&&
!
Outs
.
empty
(
)
)
report_fatal_error
(
"ISRs cannot return any value"
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
AnalyzeReturnValues
(
CCInfo
,
RVLocs
,
Outs
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
unsigned
Opc
=
(
CallConv
==
CallingConv
::
MSP430_INTR
MSP430ISD
::
RETI_FLAG
:
MSP430ISD
::
RET_FLAG
)
;
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
Opc
,
dl
,
MVT
::
Other
,
&
RetOps
[
0
]
,
RetOps
.
size
(
)
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


"X86TargetMachine --->> In the constructor class !! \n"


<s>
static
void
ix86_test_dumping_hard_regs
(
)
{
ASSERT_RTL_DUMP_EQ
(
"(reg:SI ax)"
,
gen_raw_REG
(
SImode
,
0
)
)
;
ASSERT_RTL_DUMP_EQ
(
"(reg:SI dx)"
,
gen_raw_REG
(
SImode
,
1
)
)
;
}
</s>

Verify that hard regs are dumped as expected ( in compact mode ) .


<s> static rtx m68k_get_m68k_read_tp ( void ) { if ( m68k_read_tp == NULL_RTX ) m68k_read_tp = init_one_libfunc ( "__m68k_read_tp" ) ; return m68k_read_tp ; } </s>


"Some operands reg class are incompatible!"

optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare ; remove Compare if possible .


"64-bit code requested on a subtarget that doesn't support it!"

This constructor initializes the data members to match that of the specified triple .


<s> static bool mep_assign_save_slots ( int reg_save_size ) { bool really_need_stack_frame = false ; int di_ofs = 0 ; int i ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( mep_call_saves_register ( i ) ) { int regsize = mep_reg_size ( i ) ; if ( ( i != TP_REGNO && i != GP_REGNO && i != LP_REGNO ) || mep_reg_set_in_function ( i ) ) really_need_stack_frame = true ; if ( cfun -> machine -> reg_save_slot [ i ] ) continue ; if ( regsize < 8 ) { cfun -> machine -> reg_save_size += regsize ; cfun -> machine -> reg_save_slot [ i ] = cfun -> machine -> reg_save_size ; } else { cfun -> machine -> reg_save_slot [ i ] = reg_save_size - di_ofs ; di_ofs += 8 ; } } cfun -> machine -> frame_locked = 1 ; return really_need_stack_frame ; } </s>

Assign save slots for any register not already saved . DImode registers go at the end of the reg save area ; the rest go at the beginning . This is for alignment purposes . Returns true if a frame is really needed .


<s> StringRef getPassName ( ) const override { return "MipsPostLegalizerCombiner" ; } </s>

getPassName - Return a nice clean name for a pass .


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) -> findAssociatedFragment ( ) ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s> TargetLowering :: ConstraintWeight LM32TargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'd' : case 'y' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; } return weight ; } </s>


<s> bool isReg ( ) const override { return false ; } </s>


<s> bool AArch64TargetLowering :: isLegalInterleavedAccessType ( VectorType * VecTy , const DataLayout & DL ) const { unsigned VecSize = DL . getTypeSizeInBits ( VecTy ) ; unsigned ElSize = DL . getTypeSizeInBits ( VecTy -> getElementType ( ) ) ; if ( cast < FixedVectorType > ( VecTy ) -> getNumElements ( ) < 2 ) return false ; if ( ElSize != 8 && ElSize != 16 && ElSize != 32 && ElSize != 64 ) return false ; return VecSize == 64 || VecSize % 128 == 0 ; } </s>

Returns whether or not generating a interleaved load/store intrinsic for this type will be legal .


<s> void AMDGPUFrameLowering :: emitPrologue ( MachineFunction & MF ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> const Triple & getTargetTriple ( ) const { return TargetTriple ; } </s>

Get the target triple which is a string describing the target host .


<s> void ARMPassConfig :: addIRPasses ( ) { if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( - 1 , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < ARMSubtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST . isThumb1Only ( ) ; } ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> void ix86_emit_swsqrtsf ( rtx res , rtx a , machine_mode mode , bool recip ) { rtx x0 , e0 , e1 , e2 , e3 , mthree , mhalf ; REAL_VALUE_TYPE r ; int unspec ; x0 = gen_reg_rtx ( mode ) ; e0 = gen_reg_rtx ( mode ) ; e1 = gen_reg_rtx ( mode ) ; e2 = gen_reg_rtx ( mode ) ; e3 = gen_reg_rtx ( mode ) ; real_from_integer ( & r , VOIDmode , - 3 , SIGNED ) ; mthree = CONST_DOUBLE_FROM_REAL_VALUE ( r , SFmode ) ; real_arithmetic ( & r , NEGATE_EXPR , & dconsthalf , NULL ) ; mhalf = CONST_DOUBLE_FROM_REAL_VALUE ( r , SFmode ) ; unspec = UNSPEC_RSQRT ; if ( VECTOR_MODE_P ( mode ) ) { mthree = ix86_build_const_vector ( mode , true , mthree ) ; mhalf = ix86_build_const_vector ( mode , true , mhalf ) ; if ( GET_MODE_SIZE ( mode ) == 64 ) unspec = UNSPEC_RSQRT14 ; } a = force_reg ( mode , a ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , a ) , unspec ) ) ) ; if ( ! recip ) { rtx zero , mask ; zero = gen_reg_rtx ( mode ) ; mask = gen_reg_rtx ( mode ) ; zero = force_reg ( mode , CONST0_RTX ( mode ) ) ; if ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == 64 ) { mask = gen_reg_rtx ( HImode ) ; emit_insn ( gen_avx512f_cmpv16sf3 ( mask , zero , a , GEN_INT ( 0x4 ) ) ) ; emit_insn ( gen_avx512f_blendmv16sf ( x0 , zero , x0 , mask ) ) ; } else { emit_insn ( gen_rtx_SET ( VOIDmode , mask , gen_rtx_NE ( mode , zero , a ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x0 , gen_rtx_AND ( mode , x0 , mask ) ) ) ; } } emit_insn ( gen_rtx_SET ( VOIDmode , e0 , gen_rtx_MULT ( mode , x0 , a ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , e1 , gen_rtx_MULT ( mode , e0 , x0 ) ) ) ; mthree = force_reg ( mode , mthree ) ; emit_insn ( gen_rtx_SET ( VOIDmode , e2 , gen_rtx_PLUS ( mode , e1 , mthree ) ) ) ; mhalf = force_reg ( mode , mhalf ) ; if ( recip ) emit_insn ( gen_rtx_SET ( VOIDmode , e3 , gen_rtx_MULT ( mode , x0 , mhalf ) ) ) ; else emit_insn ( gen_rtx_SET ( VOIDmode , e3 , gen_rtx_MULT ( mode , e0 , mhalf ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , res , gen_rtx_MULT ( mode , e2 , e3 ) ) ) ; } </s>

Output code to perform a Newton-Rhapson approximation of a single precision floating point [ reciprocal ] square root .


<s> unsigned CSKYAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { CSKYOperand & Op = static_cast < CSKYOperand & > ( AsmOp ) ; if ( ! Op . isReg ( ) ) return Match_InvalidOperand ; MCRegister Reg = Op . getReg ( ) ; if ( CSKYMCRegisterClasses [ CSKY :: FPR32RegClassID ] . contains ( Reg ) ) { if ( Kind == MCK_FPR64 || Kind == MCK_sFPR64_V ) { Op . Reg . RegNum = convertFPR32ToFPR64 ( Reg ) ; if ( Kind == MCK_sFPR64_V && ( Op . Reg . RegNum < CSKY :: F0_64 || Op . Reg . RegNum > CSKY :: F15_64 ) ) return Match_InvalidRegOutOfRange ; if ( Kind == MCK_FPR64 && ( Op . Reg . RegNum < CSKY :: F0_64 || Op . Reg . RegNum > CSKY :: F31_64 ) ) return Match_InvalidRegOutOfRange ; return Match_Success ; } } if ( CSKYMCRegisterClasses [ CSKY :: GPRRegClassID ] . contains ( Reg ) ) { if ( Kind == MCK_GPRPair ) { Op . Reg . RegNum = MRI -> getEncodingValue ( Reg ) + CSKY :: R0_R1 ; return Match_Success ; } } return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> bool AMDGPUAtomicOptimizer :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) { return false ; } DA = & getAnalysis < LegacyDivergenceAnalysis > ( ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; DominatorTreeWrapperPass * const DTW = getAnalysisIfAvailable < DominatorTreeWrapperPass > ( ) ; DT = DTW ? & DTW -> getDomTree ( ) : nullptr ; const TargetPassConfig & TPC = getAnalysis < TargetPassConfig > ( ) ; const TargetMachine & TM = TPC . getTM < TargetMachine > ( ) ; const GCNSubtarget & ST = TM . getSubtarget < GCNSubtarget > ( F ) ; HasDPP = ST . hasDPP ( ) ; IsPixelShader = F . getCallingConv ( ) == CallingConv :: AMDGPU_PS ; visit ( F ) ; const bool Changed = ! ToReplace . empty ( ) ; for ( ReplacementInfo & Info : ToReplace ) { optimizeAtomic ( * Info . I , Info . Op , Info . ValIdx , Info . ValDivergent ) ; } ToReplace . clear ( ) ; return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> unsigned getNumFixupKinds ( ) const override { return Teak :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> Register PatmosRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? Patmos :: RFP : Patmos :: RSP ; } </s>


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , LittleEndian ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , CM , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , Subtarget ( TT , CPU , FS , * this , LittleEndian ) { initReciprocals ( * this , Subtarget ) ; initAsmInfo ( ) ; } </s>


<s> bool VideoCore4FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool X86FrameLowering :: canSimplifyCallFramePseudos ( const MachineFunction & MF ) const { const X86RegisterInfo * TRI = static_cast < const X86RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; return hasReservedCallFrame ( MF ) || ( hasFP ( MF ) && ! TRI -> needsStackRealignment ( MF ) ) || TRI -> hasBasePointer ( MF ) ; } </s>

canSimplifyCallFramePseudos - If there is a reserved call frame , the call frame pseudos can be simplified .


"No idea how to print this kind of operand"

print - Print a debug representation of the operand to the given stream .


<s>
static
void
write_token
(
FILE
*
out
,
Token
const
*
tok
)
{
if
(
tok
->
space
)
fputc
(
' '
,
out
)
;
switch
(
tok
->
kind
)
{
case
K_string
:
{
const
char
*
c
=
tok
->
ptr
+
1
;
size_t
len
=
tok
->
len
2
;
fputs
(
"\\\""
,
out
)
;
while
(
len
)
{
const
char
*
bs
=
(
const
char
*
)
memchr
(
c
,
'\\'
,
len
)
;
size_t
l
=
bs
bs
c
:
len
;
fprintf
(
out
,
"%.*s"
,
(
int
)
l
,
c
)
;
len
-=
l
;
c
+=
l
;
if
(
bs
)
{
fputs
(
"\\\\"
,
out
)
;
len
,
c
++
;
}
}
fputs
(
"\\\""
,
out
)
;
}
break
;
default
:
fprintf
(
out
,
"%.*s"
,
tok
->
len
,
tok
->
ptr
)
;
break
;
}
if
(
tok
->
end
)
fputs
(
"\\n"
,
out
)
;
}
</s>


"Frame indices can only appear as the first "

"operand of a DBG_VALUE machine instruction"

runOnMachineFunction - Emit the function body .


<s> int ix86_issue_rate ( void ) { switch ( ix86_tune ) { case PROCESSOR_PENTIUM : case PROCESSOR_LAKEMONT : case PROCESSOR_BONNELL : case PROCESSOR_SILVERMONT : case PROCESSOR_KNL : case PROCESSOR_KNM : case PROCESSOR_INTEL : case PROCESSOR_K6 : case PROCESSOR_BTVER2 : case PROCESSOR_PENTIUM4 : case PROCESSOR_NOCONA : return 2 ; case PROCESSOR_PENTIUMPRO : case PROCESSOR_ATHLON : case PROCESSOR_K8 : case PROCESSOR_AMDFAM10 : case PROCESSOR_BTVER1 : case PROCESSOR_LUJIAZUI : return 3 ; case PROCESSOR_BDVER1 : case PROCESSOR_BDVER2 : case PROCESSOR_BDVER3 : case PROCESSOR_BDVER4 : case PROCESSOR_ZNVER1 : case PROCESSOR_ZNVER2 : case PROCESSOR_ZNVER3 : case PROCESSOR_ZNVER4 : case PROCESSOR_CORE2 : case PROCESSOR_NEHALEM : case PROCESSOR_SANDYBRIDGE : case PROCESSOR_HASWELL : case PROCESSOR_TREMONT : case PROCESSOR_SKYLAKE : case PROCESSOR_SKYLAKE_AVX512 : case PROCESSOR_CASCADELAKE : case PROCESSOR_CANNONLAKE : case PROCESSOR_ALDERLAKE : case PROCESSOR_GENERIC : return 4 ; case PROCESSOR_ICELAKE_CLIENT : case PROCESSOR_ICELAKE_SERVER : case PROCESSOR_TIGERLAKE : case PROCESSOR_COOPERLAKE : case PROCESSOR_ROCKETLAKE : return 5 ; case PROCESSOR_SAPPHIRERAPIDS : return 6 ; default : return 1 ; } } </s>

Return the maximum number of instructions a cpu can issue .


<s>
void
P2MCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
LLVM_DEBUG
(
errs
(
)
<<
"==== begin encode ====\n"
)
;
LLVM_DEBUG
(
MI
.
dump
(
)
)
;
uint32_t
bin
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
unsigned
op_code
=
MI
.
getOpcode
(
)
;
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
op_code
)
;
LLVM_DEBUG
(
errs
(
)
<<
"emitting instruction binary: "
)
;
for
(
int
i
=
0
;
i
<
32
;
i
++
)
{
LLVM_DEBUG
(
errs
(
)
<<
(
(
bin
>>
(
31
i
)
)
&
1
)
)
;
}
LLVM_DEBUG
(
errs
(
)
<<
"\n"
)
;
emitInstruction
(
bin
,
4
,
OS
)
;
LLVM_DEBUG
(
errs
(
)
<<
"==== end encode ====\n"
)
;
}
</s>

Encode the given Inst to bytes and append to CB .


<s> static void riscv_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; struct riscv_arg_info info ; riscv_get_arg_info ( & info , cum , arg . mode , arg . type , arg . named , false ) ; cum -> num_fprs = info . fpr_offset + info . num_fprs ; cum -> num_gprs = info . gpr_offset + info . num_gprs ; } </s>


<s> PPCSubtarget :: PPCSubtarget ( const std :: string & TT , const std :: string & FS , bool is64Bit ) : StackAlignment ( 16 ) , DarwinDirective ( PPC :: DIR_NONE ) , IsGigaProcessor ( false ) , Has64BitSupport ( false ) , Use64BitRegs ( false ) , IsPPC64 ( is64Bit ) , HasAltivec ( false ) , HasFSQRT ( false ) , HasSTFIWX ( false ) , HasLazyResolverStubs ( false ) , DarwinVers ( 0 ) { std :: string CPU = "generic" ; CPU = GetCurrentPowerPCCPU ( ) ; ParseSubtargetFeatures ( FS , CPU ) ; if ( is64Bit ) { Has64BitSupport = true ; Use64BitRegs = true ; } if ( use64BitRegs ( ) && ! has64BitSupport ( ) ) Use64BitRegs = false ; if ( TT . length ( ) > 7 ) { size_t DarwinPos = TT . find ( "-darwin" ) ; if ( DarwinPos != std :: string :: npos ) { if ( isdigit ( TT [ DarwinPos + 7 ] ) ) DarwinVers = atoi ( & TT [ DarwinPos + 7 ] ) ; else DarwinVers = 8 ; } } if ( isDarwin ( ) ) HasLazyResolverStubs = true ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> bool VZeroUpperInserter :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getTarget ( ) . getInstrInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool EverMadeChange = false ; bool YMMUsed = false ; const TargetRegisterClass * RC = X86 :: VR256RegisterClass ; for ( TargetRegisterClass :: iterator i = RC -> begin ( ) , e = RC -> end ( ) ; i != e ; i ++ ) { if ( MRI . isPhysRegUsed ( * i ) ) { YMMUsed = true ; break ; } } if ( ! YMMUsed ) return EverMadeChange ; FnHasLiveInYmm = checkFnHasLiveInYmm ( MRI ) ; assert ( BBState . empty ( ) ) ; BBState . resize ( MF . getNumBlockIDs ( ) , 0 ) ; BBSolved . resize ( MF . getNumBlockIDs ( ) , 0 ) ; while ( 1 ) { bool MadeChange = false ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) MadeChange |= processBasicBlock ( MF , * I ) ; if ( ! MadeChange ) break ; EverMadeChange = true ; } BBState . clear ( ) ; BBSolved . clear ( ) ; return EverMadeChange ; } </s>


<s> FastISel * PPC :: createFastISel ( FunctionLoweringInfo & FuncInfo , const TargetLibraryInfo * LibInfo ) { const PPCSubtarget & Subtarget = FuncInfo . MF -> getSubtarget < PPCSubtarget > ( ) ; if ( Subtarget . isPPC64 ( ) ) return new PPCFastISel ( FuncInfo , LibInfo ) ; return nullptr ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .

PowerPC PPC::createFastISel PPC PPC PPC PPC


<s> void tilepro_expand_epilogue ( bool sibcall_p ) { rtx reg_save_addr [ ROUND_ROBIN_SIZE ] = { NULL_RTX , NULL_RTX , NULL_RTX , NULL_RTX } ; rtx_insn * last_insn , * insn ; unsigned int which_scratch ; int offset , start_offset , regno ; rtx cfa_restores = NULL_RTX ; int fp_copy_regno = - 1 ; int next_scratch_regno = 29 ; int total_size = compute_total_frame_size ( ) ; last_insn = get_last_insn ( ) ; insn = NULL ; if ( df_regs_ever_live_p ( TILEPRO_LINK_REGNUM ) ) { insn = frame_emit_load ( TILEPRO_LINK_REGNUM , compute_frame_addr ( 0 , & next_scratch_regno ) , & cfa_restores ) ; } if ( total_size == 0 ) { if ( insn ) { RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = cfa_restores ; } goto done ; } start_offset = - crtl -> args . pretend_args_size - UNITS_PER_WORD ; offset = start_offset ; if ( frame_pointer_needed ) fp_copy_regno = next_scratch_regno -- ; which_scratch = 0 ; for ( regno = FIRST_PSEUDO_REGISTER - 1 ; regno >= 0 ; regno -- ) if ( need_to_save_reg ( regno ) ) { rtx r = reg_save_addr [ which_scratch ] ; if ( r == NULL_RTX ) { r = compute_frame_addr ( offset , & next_scratch_regno ) ; reg_save_addr [ which_scratch ] = r ; } else { int stride = ROUND_ROBIN_SIZE * - UNITS_PER_WORD ; rtx p = gen_rtx_PLUS ( Pmode , r , GEN_INT ( stride ) ) ; emit_insn ( gen_rtx_SET ( r , p ) ) ; } if ( fp_copy_regno >= 0 && regno == HARD_FRAME_POINTER_REGNUM ) frame_emit_load ( fp_copy_regno , r , NULL ) ; else frame_emit_load ( regno , r , & cfa_restores ) ; offset -= UNITS_PER_WORD ; which_scratch = ( which_scratch + 1 ) % ROUND_ROBIN_SIZE ; } if ( ! tilepro_current_function_is_leaf ( ) ) cfa_restores = alloc_reg_note ( REG_CFA_RESTORE , stack_pointer_rtx , cfa_restores ) ; emit_insn ( gen_blockage ( ) ) ; if ( frame_pointer_needed ) { insn = emit_insn ( gen_sp_restore ( stack_pointer_rtx , hard_frame_pointer_rtx ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = cfa_restores ; add_reg_note ( insn , REG_CFA_DEF_CFA , stack_pointer_rtx ) ; } else { insn = emit_sp_adjust ( total_size , & next_scratch_regno , true , cfa_restores ) ; } if ( crtl -> calls_eh_return ) emit_insn ( gen_sp_adjust ( stack_pointer_rtx , stack_pointer_rtx , EH_RETURN_STACKADJ_RTX ) ) ; if ( frame_pointer_needed ) { insn = emit_move_insn ( hard_frame_pointer_rtx , gen_rtx_REG ( Pmode , fp_copy_regno ) ) ; add_reg_note ( insn , REG_CFA_RESTORE , hard_frame_pointer_rtx ) ; } if ( flag_pic ) { emit_use ( cfun -> machine -> text_label_rtx ) ; emit_use ( cfun -> machine -> got_rtx ) ; } done : if ( ! sibcall_p ) { emit_jump_insn ( gen__return ( ) ) ; } else { emit_use ( gen_rtx_REG ( Pmode , TILEPRO_LINK_REGNUM ) ) ; } for ( ; last_insn != NULL_RTX ; last_insn = next_insn ( last_insn ) ) RTX_FRAME_RELATED_P ( last_insn ) = 1 ; } </s>

Implement the epilogue and sibcall_epilogue patterns . SIBCALL_P is true for a sibcall_epilogue pattern , and false for an epilogue pattern .


<s> static rtx sparc_function_arg_1 ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named , bool incoming ) { const CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; const int regbase = incoming ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST ; int slotno , regno , padding ; enum mode_class mclass = GET_MODE_CLASS ( mode ) ; slotno = function_arg_slotno ( cum , mode , type , named , incoming , & regno , & padding ) ; if ( slotno == - 1 ) return 0 ; if ( type && VECTOR_INTEGER_TYPE_P ( type ) ) mclass = MODE_FLOAT ; if ( TARGET_ARCH32 ) return gen_rtx_REG ( mode , regno ) ; if ( type && TREE_CODE ( type ) == RECORD_TYPE ) { const int size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; return function_arg_record_value ( type , mode , slotno , named , regbase ) ; } else if ( type && TREE_CODE ( type ) == UNION_TYPE ) { const int size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; return function_arg_union_value ( size , mode , slotno , regno ) ; } else if ( type && VECTOR_TYPE_P ( type ) && mode == BLKmode ) { const int size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; return function_arg_vector_value ( size , slotno , named , regno ) ; } else if ( ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) && SPARC_FP_REG_P ( regno ) ) { rtx reg = gen_rtx_REG ( mode , regno ) ; if ( cum -> prototype_p || cum -> libcall_p ) return reg ; else { rtx v0 , v1 ; if ( ( regno - SPARC_FP_ARG_FIRST ) < SPARC_INT_ARG_MAX * 2 ) { int intreg ; if ( incoming ) return reg ; intreg = ( SPARC_OUTGOING_INT_ARG_FIRST + ( regno - SPARC_FP_ARG_FIRST ) / 2 ) ; v0 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , intreg ) , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , v0 , v1 ) ) ; } else { v0 = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , v0 , v1 ) ) ; } } } else if ( type && AGGREGATE_TYPE_P ( type ) ) { const int size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; mode = int_mode_for_size ( size * BITS_PER_UNIT , 0 ) . else_blk ( ) ; } return gen_rtx_REG ( mode , regno ) ; } </s>

Determine where to put an argument to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . NAMED is true if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . INCOMING_P is false for TARGET_FUNCTION_ARG , true for TARGET_FUNCTION_INCOMING_ARG .


<s> bool isTargetEHABICompatible ( ) const { return ( TargetTriple . getEnvironment ( ) == Triple :: EABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: EABIHF || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || isTargetAndroid ( ) ) && ! isTargetDarwin ( ) && ! isTargetWindows ( ) ; } </s>

Tests whether the target supports the EHABI exception handling standard .


<s> void thumb_expand_movmemqi ( rtx * operands ) { rtx out = copy_to_mode_reg ( SImode , XEXP ( operands [ 0 ] , 0 ) ) ; rtx in = copy_to_mode_reg ( SImode , XEXP ( operands [ 1 ] , 0 ) ) ; HOST_WIDE_INT len = INTVAL ( operands [ 2 ] ) ; HOST_WIDE_INT offset = 0 ; while ( len >= 12 ) { emit_insn ( gen_movmem12b ( out , in , out , in ) ) ; len -= 12 ; } if ( len >= 8 ) { emit_insn ( gen_movmem8b ( out , in , out , in ) ) ; len -= 8 ; } if ( len >= 4 ) { rtx reg = gen_reg_rtx ( SImode ) ; emit_insn ( gen_movsi ( reg , gen_rtx_MEM ( SImode , in ) ) ) ; emit_insn ( gen_movsi ( gen_rtx_MEM ( SImode , out ) , reg ) ) ; len -= 4 ; offset += 4 ; } if ( len >= 2 ) { rtx reg = gen_reg_rtx ( HImode ) ; emit_insn ( gen_movhi ( reg , gen_rtx_MEM ( HImode , plus_constant ( in , offset ) ) ) ) ; emit_insn ( gen_movhi ( gen_rtx_MEM ( HImode , plus_constant ( out , offset ) ) , reg ) ) ; len -= 2 ; offset += 2 ; } if ( len ) { rtx reg = gen_reg_rtx ( QImode ) ; emit_insn ( gen_movqi ( reg , gen_rtx_MEM ( QImode , plus_constant ( in , offset ) ) ) ) ; emit_insn ( gen_movqi ( gen_rtx_MEM ( QImode , plus_constant ( out , offset ) ) , reg ) ) ; } } </s>


<s> void GCNPassConfig :: addMachineSSAOptimization ( ) { TargetPassConfig :: addMachineSSAOptimization ( ) ; addPass ( & SIFoldOperandsID ) ; if ( EnableDPPCombine ) addPass ( & GCNDPPCombineID ) ; addPass ( & SILoadStoreOptimizerID ) ; if ( EnableSDWAPeephole . getNumOccurrences ( ) ? EnableSDWAPeephole : TM -> getOptLevel ( ) > CodeGenOpt :: Less ) { addPass ( & SIPeepholeSDWAID ) ; addPass ( & EarlyMachineLICMID ) ; addPass ( & MachineCSEID ) ; addPass ( & SIFoldOperandsID ) ; } addPass ( & DeadMachineInstructionElimID ) ; addPass ( createSIShrinkInstructionsPass ( ) ) ; } </s>

Methods with trivial inline returns are convenient points in the common codegen pass pipeline where targets may insert passes .


<s>
PIC16Section
*
PIC16Section
::
Create
(
const
StringRef
&
Name
,
PIC16SectionType
Ty
,
const
std
::
string
&
Address
,
int
Color
,
MCContext
&
Ctx
)
{
SectionKind
K
;
switch
(
Ty
)
{
default
:
llvm_unreachable
(
"can not create unknown section type"
)
;
case
UDATA_OVR
:
{
K
=
SectionKind
::
getThreadBSS
(
)
;
break
;
}
case
UDATA_SHR
:
case
UDATA
:
{
K
=
SectionKind
::
getBSS
(
)
;
break
;
}
case
ROMDATA
:
case
IDATA
:
{
K
=
SectionKind
::
getMetadata
(
)
;
break
;
}
case
CODE
:
{
K
=
SectionKind
::
getText
(
)
;
break
;
}
}
PIC16Section
*
S
=
new
(
Ctx
)
PIC16Section
(
Name
,
K
,
Address
,
Color
)
;
S
->
T
=
Ty
;
return
S
;
}
</s>

Construct a unary instruction , given the opcode and an operand .


<s> unsigned ARCInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { int Opcode = MI . getOpcode ( ) ; if ( isStore ( Opcode ) ) { if ( ( MI . getOperand ( 1 ) . isFI ( ) ) && ( MI . getOperand ( 2 ) . isImm ( ) ) && ( isZeroImm ( MI . getOperand ( 2 ) ) ) ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> const uint32_t * M88kRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return CSR_M88k_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"SI Fix CF Live Intervals"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool PPCRegisterInfo :: requiresVirtualBaseRegisters ( const MachineFunction & MF ) const { const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; return ! Subtarget . hasROPProtect ( ) ; } </s>

Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers used for more efficient stack access .


<s> bool AArch64IndirectThunks :: runOnMachineFunction ( MachineFunction & MF ) { LLVM_DEBUG ( dbgs ( ) << getPassName ( ) << '\n' ) ; auto & MMI = getAnalysis < MachineModuleInfoWrapperPass > ( ) . getMMI ( ) ; return runTIs ( MMI , MF , TIs ) ; } </s>


<s> static int find_r0_life_regions ( basic_block b ) { rtx_insn * end , * insn ; rtx pset ; rtx r0_reg ; int live ; int set ; int death = 0 ; if ( REGNO_REG_SET_P ( df_get_live_in ( b ) , R0_REG ) ) { set = 1 ; live = 1 ; } else { set = 0 ; live = 0 ; } insn = BB_HEAD ( b ) ; end = BB_END ( b ) ; r0_reg = gen_rtx_REG ( SImode , R0_REG ) ; while ( 1 ) { if ( INSN_P ( insn ) ) { if ( find_regno_note ( insn , REG_DEAD , R0_REG ) ) { death ++ ; live = 0 ; } if ( ! live && ( pset = single_set ( insn ) ) && reg_overlap_mentioned_p ( r0_reg , SET_DEST ( pset ) ) && ! find_regno_note ( insn , REG_UNUSED , R0_REG ) ) { set ++ ; live = 1 ; } } if ( insn == end ) break ; insn = NEXT_INSN ( insn ) ; } return set - death ; } </s>


<s> const AMDGPUSubtarget * getSubtargetImpl ( ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool can_be_overloaded_p ( enum predication_type_index pred ) const override { return pred == PRED_TYPE_tu || pred == PRED_TYPE_tum || pred == PRED_TYPE_tumu ; } </s>

Since most of intrinsics can be overloaded , we set it true by default .


<s> static bool s390_is_vr128 ( machine_mode m ) { return m == V1TFmode || ( TARGET_VXE && m == TFmode ) ; } </s>

Return nonzero if mode M describes a 128-bit float in a vector register .


"Instr doesn't have FrameIndex operand!"

"Unconditionally using R28 for evil purposes Offset: "

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool contains ( MachineInstr * MI ) { return Insts . count ( MI ) > 0 ; } </s>

contains - Returns true if this trace contains the given basic block .


<s> virtual const DataLayout * getDataLayout ( ) const { return & Layout ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> void X86PassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None && getX86Subtarget ( ) . hasSSE2 ( ) ) addPass ( createExecutionDependencyFixPass ( & X86 :: VR128RegClass ) ) ; if ( UseVZeroUpper ) addPass ( createX86IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86PadShortFunctions ( ) ) ; addPass ( createX86FixupLEAs ( ) ) ; } } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> unsigned getNumFixupKinds ( ) const override { return J2 :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> const char * XCoreTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case XCoreISD :: BL : return "XCoreISD::BL" ; case XCoreISD :: PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper" ; case XCoreISD :: DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper" ; case XCoreISD :: CPRelativeWrapper : return "XCoreISD::CPRelativeWrapper" ; case XCoreISD :: STWSP : return "XCoreISD::STWSP" ; case XCoreISD :: RETSP : return "XCoreISD::RETSP" ; case XCoreISD :: LADD : return "XCoreISD::LADD" ; case XCoreISD :: LSUB : return "XCoreISD::LSUB" ; case XCoreISD :: BR_JT : return "XCoreISD::BR_JT" ; case XCoreISD :: BR_JT32 : return "XCoreISD::BR_JT32" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific

XCore XCore XCoreISD::BL "XCoreISD::BL" XCoreISD::PCRelativeWrapper "XCoreISD::PCRelativeWrapper" XCoreISD::DPRelativeWrapper "XCoreISD::DPRelativeWrapper" XCoreISD::CPRelativeWrapper "XCoreISD::CPRelativeWrapper" XCoreISD::STWSP "XCoreISD::STWSP" XCoreISD::RETSP "XCoreISD::RETSP" XCoreISD::LADD "XCoreISD::LADD" XCoreISD::LSUB "XCoreISD::LSUB" XCoreISD::BR_JT "XCoreISD::BR_JT" XCoreISD::BR_JT32 "XCoreISD::BR_JT32"


<s> PreservedAnalyses AMDGPUPromoteKernelArgumentsPass :: run ( Function & F , FunctionAnalysisManager & AM ) { MemorySSA & MSSA = AM . getResult < MemorySSAAnalysis > ( F ) . getMSSA ( ) ; if ( AMDGPUPromoteKernelArguments ( ) . run ( F , MSSA ) ) { PreservedAnalyses PA ; PA . preserveSet < CFGAnalyses > ( ) ; PA . preserve < MemorySSAAnalysis > ( ) ; return PA ; } return PreservedAnalyses :: all ( ) ; } </s>

Run the analysis pass over a function and produce a dominator tree .


<s> void ARMPassConfig :: addIRPasses ( ) { if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( 1 , false , false , true , true , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < ARMSubtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST . isThumb1Only ( ) ; } ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( createARMParallelDSPPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardCheckPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> enum attr_cc compute_logical_op_cc ( machine_mode mode , rtx * operands ) { enum rtx_code code = GET_CODE ( operands [ 3 ] ) ; const unsigned HOST_WIDE_INT intval = ( unsigned HOST_WIDE_INT ) ( ( GET_CODE ( operands [ 2 ] ) == CONST_INT ) && register_operand ( operands [ 1 ] , VOIDmode ) ? INTVAL ( operands [ 2 ] ) : 0x55555555 ) ; const unsigned HOST_WIDE_INT det = ( code != AND ) ? intval : ~ intval ; const unsigned HOST_WIDE_INT b0 = ( det >> 0 ) & 0xff ; const unsigned HOST_WIDE_INT b1 = ( det >> 8 ) & 0xff ; const unsigned HOST_WIDE_INT w0 = ( det >> 0 ) & 0xffff ; const unsigned HOST_WIDE_INT w1 = ( det >> 16 ) & 0xffff ; int lower_half_easy_p = 0 ; int upper_half_easy_p = 0 ; enum attr_cc cc = CC_CLOBBER ; switch ( mode ) { case E_HImode : if ( ( TARGET_H8300H || TARGET_H8300S ) && b0 != 0 && b1 != 0 ) { cc = CC_SET_ZNV ; } break ; case E_SImode : if ( TARGET_H8300H || TARGET_H8300S ) { lower_half_easy_p = ( b0 == 0 || b1 == 0 || ( code != IOR && w0 == 0xffff ) ) ; upper_half_easy_p = ( ( code != IOR && w1 == 0xffff ) || ( code == AND && w1 == 0xff00 ) ) ; } if ( ( TARGET_H8300H || TARGET_H8300S ) && w0 != 0 && w1 != 0 && ! ( lower_half_easy_p && upper_half_easy_p ) && ! ( code == IOR && w1 == 0xffff && ( w0 & 0x8000 ) != 0 && lower_half_easy_p ) ) { cc = CC_SET_ZNV ; } else { if ( ( TARGET_H8300H || TARGET_H8300S ) && code == IOR && w1 == 0xffff && ( w0 & 0x8000 ) != 0 ) { cc = CC_SET_ZNV ; } } break ; default : gcc_unreachable ( ) ; } return cc ; } </s>

Compute which flag bits are valid after a logical insn .


<s> void aarch64_expand_compare_and_swap ( rtx operands [ ] ) { rtx bval , rval , mem , oldval , newval , is_weak , mod_s , mod_f , x ; machine_mode mode , cmp_mode ; typedef rtx ( * gen_cas_fn ) ( rtx , rtx , rtx , rtx , rtx , rtx , rtx ) ; int idx ; gen_cas_fn gen ; const gen_cas_fn split_cas [ ] = { gen_aarch64_compare_and_swapqi , gen_aarch64_compare_and_swaphi , gen_aarch64_compare_and_swapsi , gen_aarch64_compare_and_swapdi } ; const gen_cas_fn atomic_cas [ ] = { gen_aarch64_compare_and_swapqi_lse , gen_aarch64_compare_and_swaphi_lse , gen_aarch64_compare_and_swapsi_lse , gen_aarch64_compare_and_swapdi_lse } ; bval = operands [ 0 ] ; rval = operands [ 1 ] ; mem = operands [ 2 ] ; oldval = operands [ 3 ] ; newval = operands [ 4 ] ; is_weak = operands [ 5 ] ; mod_s = operands [ 6 ] ; mod_f = operands [ 7 ] ; mode = GET_MODE ( mem ) ; cmp_mode = mode ; if ( is_mm_acquire ( memmodel_from_int ( INTVAL ( mod_f ) ) ) && is_mm_release ( memmodel_from_int ( INTVAL ( mod_s ) ) ) ) mod_s = GEN_INT ( MEMMODEL_ACQ_REL ) ; switch ( mode ) { case QImode : case HImode : cmp_mode = SImode ; rval = gen_reg_rtx ( SImode ) ; oldval = convert_modes ( SImode , mode , oldval , true ) ; case SImode : case DImode : if ( ! aarch64_plus_operand ( oldval , mode ) ) oldval = force_reg ( cmp_mode , oldval ) ; break ; default : gcc_unreachable ( ) ; } switch ( mode ) { case QImode : idx = 0 ; break ; case HImode : idx = 1 ; break ; case SImode : idx = 2 ; break ; case DImode : idx = 3 ; break ; default : gcc_unreachable ( ) ; } if ( TARGET_LSE ) gen = atomic_cas [ idx ] ; else gen = split_cas [ idx ] ; emit_insn ( gen ( rval , mem , oldval , newval , is_weak , mod_s , mod_f ) ) ; if ( mode == QImode || mode == HImode ) emit_move_insn ( operands [ 1 ] , gen_lowpart ( mode , rval ) ) ; x = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_EQ ( SImode , x , const0_rtx ) ; emit_insn ( gen_rtx_SET ( bval , x ) ) ; } </s>


<s> static void rs6000_init_dwarf_reg_sizes_extra ( tree address ) { if ( TARGET_SPE ) { int i ; machine_mode mode = TYPE_MODE ( char_type_node ) ; rtx addr = expand_expr ( address , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; rtx mem = gen_rtx_MEM ( BLKmode , addr ) ; rtx value = gen_int_mode ( 4 , mode ) ; for ( i = FIRST_SPE_HIGH_REGNO ; i < LAST_SPE_HIGH_REGNO + 1 ; i ++ ) { int column = DWARF_REG_TO_UNWIND_COLUMN ( DWARF2_FRAME_REG_OUT ( DWARF_FRAME_REGNUM ( i ) , true ) ) ; HOST_WIDE_INT offset = column * GET_MODE_SIZE ( mode ) ; emit_move_insn ( adjust_address ( mem , mode , offset ) , value ) ; } } if ( TARGET_MACHO && ! TARGET_ALTIVEC ) { int i ; machine_mode mode = TYPE_MODE ( char_type_node ) ; rtx addr = expand_expr ( address , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; rtx mem = gen_rtx_MEM ( BLKmode , addr ) ; rtx value = gen_int_mode ( 16 , mode ) ; for ( i = FIRST_ALTIVEC_REGNO ; i < LAST_ALTIVEC_REGNO + 1 ; i ++ ) { int column = DWARF_REG_TO_UNWIND_COLUMN ( DWARF2_FRAME_REG_OUT ( DWARF_FRAME_REGNUM ( i ) , true ) ) ; HOST_WIDE_INT offset = column * GET_MODE_SIZE ( mode ) ; emit_move_insn ( adjust_address ( mem , mode , offset ) , value ) ; } } } </s>

Fill in sizes of registers used by unwinder .


<s> static bool rs6000_gen_pic_addr_diff_vec ( void ) { return rs6000_relative_jumptables ; } </s>


<s> static bool rs6000_legitimate_constant_p ( machine_mode mode , rtx x ) { if ( TARGET_ELF && tls_referenced_p ( x ) ) return false ; if ( CONST_DOUBLE_P ( x ) ) return easy_fp_constant ( x , mode ) ; if ( GET_CODE ( x ) == CONST_VECTOR ) return easy_vector_constant ( x , mode ) ; return true ; } </s>

Implement TARGET_LEGITIMATE_CONSTANT_P . On the RS/6000 , all integer constants are acceptable , most wo n't be valid for particular insns , though . Only easy FP constants are acceptable .


<s> bool FalkorMarkStridedAccesses :: run ( ) { bool MadeChange = false ; for ( Loop * L : LI ) for ( Loop * LIt : depth_first ( L ) ) MadeChange |= runOnLoop ( * LIt ) ; return MadeChange ; } </s>


<s> bool R600InstrInfo :: fitsConstReadLimitations ( const std :: vector < MachineInstr * > & MIs ) const { std :: vector < unsigned > Consts ; SmallSet < int64_t , 4 > Literals ; for ( unsigned i = 0 , n = MIs . size ( ) ; i < n ; i ++ ) { MachineInstr * MI = MIs [ i ] ; if ( ! isALUInstr ( MI -> getOpcode ( ) ) ) continue ; const SmallVectorImpl < std :: pair < MachineOperand * , int64_t > > & Srcs = getSrcs ( MI ) ; for ( unsigned j = 0 , e = Srcs . size ( ) ; j < e ; j ++ ) { std :: pair < MachineOperand * , unsigned > Src = Srcs [ j ] ; if ( Src . first -> getReg ( ) == AMDGPU :: ALU_LITERAL_X ) Literals . insert ( Src . second ) ; if ( Literals . size ( ) > 4 ) return false ; if ( Src . first -> getReg ( ) == AMDGPU :: ALU_CONST ) Consts . push_back ( Src . second ) ; if ( AMDGPU :: R600_KC0RegClass . contains ( Src . first -> getReg ( ) ) || AMDGPU :: R600_KC1RegClass . contains ( Src . first -> getReg ( ) ) ) { unsigned Index = RI . getEncodingValue ( Src . first -> getReg ( ) ) & 0xff ; unsigned Chan = RI . getHWRegChan ( Src . first -> getReg ( ) ) ; Consts . push_back ( ( Index << 2 ) | Chan ) ; } } } return fitsConstReadLimitations ( Consts ) ; } </s>

Same but using const index set instead of MI set .


<s> void StackPU2TargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { Base :: Initialize ( Ctx , TM ) ; ProgmemDataSection = Ctx . getELFSection ( ".progmem.data" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ; } </s>

This method must be called before any actual lowering is done .


<s> static int get_num_immediates ( rtx insn , int * imm , int * imm32 , int * imm64 ) { imm_info imm_values = { 0 , 0 , 0 } ; find_constant ( insn , & imm_values ) ; * imm = imm_values . imm ; * imm32 = imm_values . imm32 ; * imm64 = imm_values . imm64 ; return imm_values . imm32 * 4 + imm_values . imm64 * 8 ; } </s>

Return total size of immediate operands of an instruction along with number of corresponding immediate-operands . It initializes its parameters to zero befor calling FIND_CONSTANT . INSN is the input instruction . IMM is the total of immediates . IMM32 is the number of 32 bit immediates . IMM64 is the number of 64 bit immediates .


<s> static inline tree rs6000_builtin_type ( int id ) { tree t ; t = rs6000_builtin_types [ id < 0 ? ~ id : id ] ; return id < 0 ? build_pointer_type ( t ) : t ; } </s>

Convert a type stored into a struct altivec_builtin_types as ID , into a tree . The types are in rs6000_builtin_types : negative values create a pointer type for the type associated to ~ID . Note it is a logical NOT , rather than a negation , otherwise you can not represent a pointer type for ID 0 .


<s>
void
AArch64RegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected"
)
;
MachineInstr
&
MI
=
*
II
;
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
AArch64InstrInfo
*
TII
=
MF
.
getSubtarget
<
AArch64Subtarget
>
(
)
.
getInstrInfo
(
)
;
const
AArch64FrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
unsigned
FrameReg
;
int
Offset
;
if
(
MI
.
isDebugValue
(
)
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
STACKMAP
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
PATCHPOINT
)
{
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
,
true
)
;
Offset
+=
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
)
;
return
;
}
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
)
;
if
(
rewriteAArch64FrameIndex
(
MI
,
FIOperandNum
,
FrameReg
,
Offset
,
TII
)
)
return
;
assert
(
(
!
RS
||
!
RS
->
isScavengingFrameIndex
(
FrameIndex
)
)
&&
"Emergency spill slot is out of reach"
)
;
unsigned
ScratchReg
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
&
AArch64
::
GPR64RegClass
)
;
emitFrameOffset
(
MBB
,
II
,
MI
.
getDebugLoc
(
)
,
ScratchReg
,
FrameReg
,
Offset
,
TII
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
ScratchReg
,
false
,
false
,
true
)
;
}
</s>


<s> SDValue XCoreTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_XCore ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


"cannot use va_start in interrupt function"

Implement the stdarg/varargs va_start macro . STDARG_P is non-zero if this is stdarg.h instead of varargs.h . VALIST is the tree of the va_list variable to initialize . NEXTARG is the machine independent notion of the 'next ' argument after the variable arguments .


<s>
const
MCFixupKindInfo
&
SystemZMCAsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
SystemZ
::
NumTargetFixupKinds
]
=
{
{
"FK_390_PC12DBL"
,
4
,
12
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"FK_390_PC16DBL"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"FK_390_PC24DBL"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"FK_390_PC32DBL"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"FK_390_TLS_CALL"
,
0
,
0
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> bool AVRFrameLowering :: canSimplifyCallFramePseudos ( const MachineFunction & MF ) const { return true ; } </s>

canSimplifyCallFramePseudos - If there is a reserved call frame , the call frame pseudos can be simplified .


<s>
void
SystemZPostRASchedStrategy
::
enterMBB
(
MachineBasicBlock
*
NextMBB
)
{
assert
(
(
SchedStates
.
find
(
NextMBB
)
==
SchedStates
.
end
(
)
)
&&
"Entering MBB twice?"
)
;
DEBUG
(
dbgs
(
)
<<
"+++ Entering MBB#"
<<
NextMBB
->
getNumber
(
)
)
;
MBB
=
NextMBB
;
HazardRec
=
SchedStates
[
MBB
]
=
new
SystemZHazardRecognizer
(
TII
,
&
SchedModel
)
;
DEBUG
(
const
MachineLoop
*
Loop
=
MLI
->
getLoopFor
(
MBB
)
;
if
(
Loop
&&
Loop
->
getHeader
(
)
==
MBB
)
dbgs
(
)
<<
" (Loop header)"
;
dbgs
(
)
<<
":\n"
;
)
;
MachineBasicBlock
*
SinglePredMBB
=
getSingleSchedPred
(
MBB
,
MLI
->
getLoopFor
(
MBB
)
)
;
if
(
SinglePredMBB
==
nullptr
||
SchedStates
.
find
(
SinglePredMBB
)
==
SchedStates
.
end
(
)
)
return
;
DEBUG
(
dbgs
(
)
<<
"+++ Continued scheduling from MBB#"
<<
SinglePredMBB
->
getNumber
(
)
<<
"\n"
;
)
;
HazardRec
->
copyState
(
SchedStates
[
SinglePredMBB
]
)
;
for
(
MachineBasicBlock
::
iterator
I
=
SinglePredMBB
->
getFirstTerminator
(
)
;
I
!=
SinglePredMBB
->
end
(
)
;
I
++
)
{
DEBUG
(
dbgs
(
)
<<
"+++ Emitting incoming branch: "
;
I
->
dump
(
)
;
)
;
bool
TakenBranch
=
(
I
->
isBranch
(
)
&&
(
TII
->
getBranchInfo
(
*
I
)
.
Target
->
isReg
(
)
||
TII
->
getBranchInfo
(
*
I
)
.
Target
->
getMBB
(
)
==
MBB
)
)
;
HazardRec
->
emitInstruction
(
&
*
I
,
TakenBranch
)
;
if
(
TakenBranch
)
break
;
}
}
</s>

Tell the strategy that MBB is about to be processed .

SystemZ
SystemZ
"Entering MBB twice?"
"+++ Entering MBB#"
SystemZ
" (Loop header)"
":\n"
"+++ Continued scheduling from MBB#"
"\n"
"+++ Emitting incoming branch: "


<s>
static
void
or1k_print_operand
(
FILE
*
file
,
rtx
x
,
int
code
)
{
rtx
operand
=
x
;
switch
(
code
)
{
case
'#'
:
if
(
final_sequence
==
)
fputs
(
"\n\t l.nop\n"
,
file
)
;
break
;
case
'r'
:
if
(
REG_P
(
x
)
)
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
operand
)
]
)
;
else
if
(
x
==
CONST0_RTX
(
GET_MODE
(
x
)
)
)
fprintf
(
file
,
"r0"
)
;
else
output_operand_lossage
(
"invalid %%r value"
)
;
break
;
case
'H'
:
if
(
REG_P
(
x
)
)
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
operand
)
+
1
]
)
;
else
output_operand_lossage
(
"invalid %%H value"
)
;
break
;
case
'd'
:
if
(
REG_P
(
x
)
)
{
if
(
GET_MODE
(
x
)
==
DFmode
||
GET_MODE
(
x
)
==
DImode
)
fprintf
(
file
,
"%s,%s"
,
reg_names
[
REGNO
(
operand
)
]
,
reg_names
[
REGNO
(
operand
)
+
1
]
)
;
else
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
operand
)
]
)
;
}
else
output_operand_lossage
(
"invalid %%d value"
)
;
break
;
case
'h'
:
print_reloc
(
file
,
x
,
0
,
RKIND_HI
)
;
break
;
case
'L'
:
print_reloc
(
file
,
x
,
0
,
RKIND_LO
)
;
break
;
case
'P'
:
if
(
!
flag_pic
||
SYMBOL_REF_LOCAL_P
(
x
)
)
output_addr_const
(
file
,
x
)
;
else
output_addr_reloc
(
file
,
x
,
0
,
"plt"
)
;
break
;
case
0
:
switch
(
GET_CODE
(
operand
)
)
{
case
REG
:
if
(
REGNO
(
operand
)
>
31
)
internal_error
(
"internal error: bad register: %d"
,
REGNO
(
operand
)
)
;
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
operand
)
]
)
;
break
;
case
MEM
:
output_address
(
GET_MODE
(
XEXP
(
operand
,
0
)
)
,
XEXP
(
operand
,
0
)
)
;
break
;
case
CODE_LABEL
:
case
LABEL_REF
:
output_asm_label
(
operand
)
;
break
;
default
:
if
(
CONSTANT_P
(
operand
)
)
output_addr_const
(
file
,
operand
)
;
else
internal_error
(
"unexpected operand: %d"
,
GET_CODE
(
operand
)
)
;
break
;
}
break
;
default
:
output_operand_lossage
(
"unknown operand letter: '%c'"
,
code
)
;
break
;
}
}
</s>

Worker for TARGET_PRINT_OPERAND . Print operand X , an RTX , to the file FILE . The output is formed as expected by the OpenRISC assember . CODE is the letter following a ' % ' in an instrunction template used to control the RTX output . Example ( s ) : CODE RTX OUTPUT COMMENT 0 ( reg : SI 3 ) r3 output an operand r ( reg : SI 3 ) r3 output a register or const zero H ( reg : SI 3 ) r4 output the high pair register h ( symbol_ref : SI ( `` x '' ) ) ha ( x ) output a signed high relocation L ( symbol_ref : SI ( `` x '' ) ) lo ( x ) output a low relocation Note , ' # ' is a special code used to fill the branch delay slot with an l.nop instruction . The l.nop ( no-op ) instruction is only outputted when the delay slot has not been filled .


Change register usage conditional on target flags .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"OpenRISC Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"loadRegFromStackSlot didn't insert any code!"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static void s390_mainpool_cancel ( struct constant_pool * pool ) { s390_free_pool ( pool ) ; } </s>

POOL holds the main literal pool as collected by s390_mainpool_start . We have decided we can not use this pool , so revert all changes to the current function that were done by s390_mainpool_start .


<s> const LM32Subtarget * getSubtargetImpl ( ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool ThumbRegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { const ARMSubtarget & STI = MBB . getParent ( ) -> getSubtarget < ARMSubtarget > ( ) ; if ( ! STI . isThumb1Only ( ) ) return ARMBaseRegisterInfo :: saveScavengerRegister ( MBB , I , UseMI , RC , Reg ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; DebugLoc DL ; AddDefaultPred ( BuildMI ( MBB , I , DL , TII . get ( ARM :: tMOVr ) ) . addReg ( ARM :: R12 , RegState :: Define ) . addReg ( Reg , RegState :: Kill ) ) ; bool done = false ; for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { if ( II -> isDebugValue ( ) ) continue ; for ( unsigned i = 0 , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( ARM :: R12 ) ) { UseMI = II ; done = true ; break ; } if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == ARM :: R12 ) { UseMI = II ; done = true ; break ; } } } AddDefaultPred ( BuildMI ( MBB , UseMI , DL , TII . get ( ARM :: tMOVr ) ) . addReg ( Reg , RegState :: Define ) . addReg ( ARM :: R12 , RegState :: Kill ) ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .


<s> void GCNPassConfig :: addPreEmitPass ( ) { addPass ( createSILowerControlFlowPass ( * TM ) , false ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
int
PPCTTIImpl
::
getArithmeticInstrCost
(
unsigned
Opcode
,
Type
*
Ty
,
TTI
::
OperandValueKind
Op1Info
,
TTI
::
OperandValueKind
Op2Info
,
TTI
::
OperandValueProperties
Opd1PropInfo
,
TTI
::
OperandValueProperties
Opd2PropInfo
,
ArrayRef
<
const
Value
*
>
Args
,
const
Instruction
*
CxtI
)
{
assert
(
TLI
->
InstructionOpcodeToISD
(
Opcode
)
&&
"Invalid opcode"
)
;
int
Cost
=
BaseT
::
getArithmeticInstrCost
(
Opcode
,
Ty
,
Op1Info
,
Op2Info
,
Opd1PropInfo
,
Opd2PropInfo
)
;
return
vectorCostAdjustment
(
Cost
,
Opcode
,
Ty
,
nullptr
)
;
}
</s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> void MipsFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MipsInstrInfo & TII = * static_cast < const MipsInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; unsigned SP = STI . isABI_N64 ( ) ? Mips :: SP_64 : Mips :: SP ; unsigned FP = STI . isABI_N64 ( ) ? Mips :: FP_64 : Mips :: FP ; unsigned ZERO = STI . isABI_N64 ( ) ? Mips :: ZERO_64 : Mips :: ZERO ; unsigned ADDu = STI . isABI_N64 ( ) ? Mips :: DADDu : Mips :: ADDu ; unsigned ADDiu = STI . isABI_N64 ( ) ? Mips :: DADDiu : Mips :: ADDiu ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( ADDu ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; if ( isInt < 16 > ( StackSize ) ) BuildMI ( MBB , MBBI , dl , TII . get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( StackSize ) ; else expandLargeImm ( SP , StackSize , STI . isABI_N64 ( ) , TII , MBB , MBBI , dl ) ; } </s>

Mips Mips Mips Mips Mips::SP_64 Mips::SP Mips::FP_64 Mips::FP Mips::ZERO_64 Mips::ZERO Mips::DADDu Mips::ADDu Mips::DADDiu Mips::ADDiu 0 16


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < DominatorTreeWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> EVT PPCTargetLowering :: getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const { if ( getTargetMachine ( ) . getOptLevel ( ) != CodeGenOpt :: None ) { if ( Subtarget . hasAltivec ( ) && Op . size ( ) >= 16 && ( Op . isAligned ( Align ( 16 ) ) || ( ( Op . isMemset ( ) && Subtarget . hasVSX ( ) ) || Subtarget . hasP8Vector ( ) ) ) ) return MVT :: v4i32 ; } if ( Subtarget . isPPC64 ( ) ) { return MVT :: i64 ; } return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> const BlackfinInstrInfo & getInstrInfo ( ) { return * static_cast < const BlackfinTargetMachine & > ( TM ) . getInstrInfo ( ) ; } </s>


<s> void FixupLEAPass :: processInstruction ( MachineBasicBlock :: iterator & I , MachineFunction :: iterator MFI ) { MachineInstr * MI = I ; int opcode = MI -> getOpcode ( ) ; const MCInstrDesc & Desc = MI -> getDesc ( ) ; int AddrOffset = X86II :: getMemoryOperandNo ( Desc . TSFlags , opcode ) ; if ( AddrOffset >= 0 ) { AddrOffset += X86II :: getOperandBias ( Desc ) ; MachineOperand & p = MI -> getOperand ( AddrOffset + X86 :: AddrBaseReg ) ; if ( p . isReg ( ) && p . getReg ( ) != X86 :: ESP ) { seekLEAFixup ( p , I , MFI ) ; } MachineOperand & q = MI -> getOperand ( AddrOffset + X86 :: AddrIndexReg ) ; if ( q . isReg ( ) && q . getReg ( ) != X86 :: ESP ) { seekLEAFixup ( q , I , MFI ) ; } } } </s>

Process a single instruction and collect debug info anchors .


<s> void PIC16TargetLowering :: LowerOperationWrapper ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { SDValue Op = SDValue ( N , 0 ) ; SDValue Res ; unsigned i ; switch ( Op . getOpcode ( ) ) { case ISD :: LOAD : Res = ExpandLoad ( Op . getNode ( ) , DAG ) ; break ; default : { Res = LowerOperation ( Op , DAG ) ; if ( Res . getNode ( ) ) Results . push_back ( Res ) ; return ; } } N = Res . getNode ( ) ; unsigned NumValues = N -> getNumValues ( ) ; for ( i = 0 ; i < NumValues ; i ++ ) { Results . push_back ( SDValue ( N , i ) ) ; } } </s>

This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types .


<s> static bool eco32_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { const HOST_WIDE_INT size = int_size_in_bytes ( type ) ; return ( size == - 1 || size > UNITS_PER_WORD ) ; } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


"secondary output reload copy from %s %s to "


<s> static void mips16_lay_out_constants ( void ) { struct mips16_constant_pool pool ; rtx insn , barrier ; barrier = 0 ; memset ( & pool , 0 , sizeof ( pool ) ) ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( INSN_P ( insn ) ) for_each_rtx ( & PATTERN ( insn ) , mips16_rewrite_pool_refs , & pool ) ; pool . insn_address += mips16_insn_length ( insn ) ; if ( pool . first != NULL ) { if ( barrier == 0 && pool . insn_address + 4 > pool . highest_address ) { rtx label , jump ; label = gen_label_rtx ( ) ; jump = emit_jump_insn_before ( gen_jump ( label ) , insn ) ; JUMP_LABEL ( jump ) = label ; LABEL_NUSES ( label ) = 1 ; barrier = emit_barrier_after ( jump ) ; emit_label_after ( label , barrier ) ; pool . insn_address += 4 ; } if ( pool . insn_address > pool . highest_address ) { dump_constants ( pool . first , barrier ) ; pool . first = NULL ; barrier = 0 ; } else if ( BARRIER_P ( insn ) ) barrier = insn ; } } dump_constants ( pool . first , get_last_insn ( ) ) ; } </s>


<s> v850_data_area v850_get_data_area ( tree decl ) { if ( lookup_attribute ( "sda" , DECL_ATTRIBUTES ( decl ) ) != NULL_TREE ) return DATA_AREA_SDA ; if ( lookup_attribute ( "tda" , DECL_ATTRIBUTES ( decl ) ) != NULL_TREE ) return DATA_AREA_TDA ; if ( lookup_attribute ( "zda" , DECL_ATTRIBUTES ( decl ) ) != NULL_TREE ) return DATA_AREA_ZDA ; return DATA_AREA_NORMAL ; } </s>

Retrieve the data area that has been chosen for the given decl .


<s> bool DLXAsmParser :: ParseDirective ( AsmToken ) { return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> unsigned getExplicitKernelArgOffset ( const Function & F ) const { return isAmdCodeObjectV2 ( F ) ? 0 : 36 ; } </s>

Returns the offset in bytes from the start of the input buffer of the first explicit kernel argument .


<s>
void
relaxInstruction
(
const
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
,
MCInst
&
Res
)
const
override
{
assert
(
0
&&
"relaxInstruction() unimplemented"
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .

Nyuzi
0
"relaxInstruction() unimplemented"


<s> void SIInstrInfo :: legalizeOpWithMove ( MachineInstr * MI , unsigned OpIdx ) const { MachineBasicBlock :: iterator I = MI ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineOperand & MO = MI -> getOperand ( OpIdx ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; unsigned RCID = get ( MI -> getOpcode ( ) ) . OpInfo [ OpIdx ] . RegClass ; const TargetRegisterClass * RC = RI . getRegClass ( RCID ) ; unsigned Opcode = AMDGPU :: V_MOV_B32_e32 ; if ( MO . isReg ( ) ) Opcode = AMDGPU :: COPY ; else if ( RI . isSGPRClass ( RC ) ) Opcode = AMDGPU :: S_MOV_B32 ; const TargetRegisterClass * VRC = RI . getEquivalentVGPRClass ( RC ) ; if ( RI . getCommonSubClass ( & AMDGPU :: VReg_64RegClass , VRC ) ) VRC = & AMDGPU :: VReg_64RegClass ; else VRC = & AMDGPU :: VReg_32RegClass ; unsigned Reg = MRI . createVirtualRegister ( VRC ) ; DebugLoc DL = MBB -> findDebugLoc ( I ) ; BuildMI ( * MI -> getParent ( ) , I , DL , get ( Opcode ) , Reg ) . addOperand ( MO ) ; MO . ChangeToRegister ( Reg , false ) ; } </s>

Legalize the OpIndex operand of this instruction by inserting a MOV .


<s> void X86FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( TRI -> hasBasePointer ( MF ) ) SavedRegs . set ( TRI -> getBaseRegister ( ) ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> TargetLowering :: AtomicExpansionKind AArch64TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { unsigned Size = LI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return Size == 128 ? AtomicExpansionKind :: LLSC : AtomicExpansionKind :: None ; } </s>

Returns how the given ( atomic ) load should be expanded by the IR-level AtomicExpand pass .


"instruction requires a CPU feature not currently enabled"

"source and destination must be different"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


"Should use MaskedValueIsZero if you don't know whether Op"

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> static bool aarch64_option_valid_attribute_p ( tree fndecl , tree , tree args , int ) { struct cl_target_option cur_target ; bool ret ; tree old_optimize ; tree new_target , new_optimize ; tree existing_target = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( ! existing_target && args == current_target_pragma ) { DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = target_option_current_node ; return true ; } tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; old_optimize = build_optimization_node ( & global_options ) ; func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( func_optimize && func_optimize != old_optimize ) cl_optimization_restore ( & global_options , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_save ( & cur_target , & global_options ) ; if ( existing_target ) { struct cl_target_option * existing_options = TREE_TARGET_OPTION ( existing_target ) ; if ( existing_options ) cl_target_option_restore ( & global_options , existing_options ) ; } else cl_target_option_restore ( & global_options , TREE_TARGET_OPTION ( target_option_current_node ) ) ; ret = aarch64_process_target_attr ( args , "attribute" ) ; if ( ret ) { aarch64_override_options_internal ( & global_options ) ; if ( TARGET_SIMD ) { tree saved_current_target_pragma = current_target_pragma ; current_target_pragma = NULL ; aarch64_init_simd_builtins ( ) ; current_target_pragma = saved_current_target_pragma ; } new_target = build_target_option_node ( & global_options ) ; } else new_target = NULL ; new_optimize = build_optimization_node ( & global_options ) ; if ( fndecl && ret ) { DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = new_target ; if ( old_optimize != new_optimize ) DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) = new_optimize ; } cl_target_option_restore ( & global_options , & cur_target ) ; if ( old_optimize != new_optimize ) cl_optimization_restore ( & global_options , TREE_OPTIMIZATION ( old_optimize ) ) ; return ret ; } </s>

Implement TARGET_OPTION_VALID_ATTRIBUTE_P . This is used to process attribute ( ( target ( `` ... '' ) ) ) .


<s> bool AVRTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { int64_t Offs = AM . BaseOffs ; if ( AM . BaseGV && ! AM . HasBaseReg && AM . Scale == 0 && Offs == 0 ) { return true ; } if ( isa < PointerType > ( Ty ) && AS == AVR :: ProgramMemory ) { return false ; } if ( Offs < 0 ) Offs = - Offs ; if ( AM . BaseGV == 0 && AM . HasBaseReg && AM . Scale == 0 && isUInt < 6 > ( Offs ) ) { return true ; } return false ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> void ARMTargetAsmStreamer :: emitInst ( uint32_t Inst , char Suffix ) { OS << "\t.inst" ; if ( Suffix ) OS << "." << Suffix ; OS << "\t0x" << utohexstr ( Inst ) << "\n" ; } </s>

Callback used to implement the .inst directive .


<s> Context ( Instruction * Exp ) : Ctx ( Exp -> getParent ( ) -> getParent ( ) -> getContext ( ) ) { initialize ( Exp ) ; } </s>

Pointer to a class instance holding , among other things , the table with the values of live string variables at the start of any given CHECK line .


<s> bool isScalarFPTypeInSSEReg ( EVT VT ) const { return ( VT == MVT :: f64 && Subtarget -> hasSSE2 ( ) ) || ( VT == MVT :: f32 && Subtarget -> hasSSE1 ( ) ) || ( VT == MVT :: f16 && Subtarget -> hasFP16 ( ) ) ; } </s>

Return true if the specified scalar FP type is computed in an SSE register , not on the X87 floating point stack .


<s> bool ARMTargetLowering :: isLegalInterleavedAccessType ( unsigned Factor , FixedVectorType * VecTy , const DataLayout & DL ) const { unsigned VecSize = DL . getTypeSizeInBits ( VecTy ) ; unsigned ElSize = DL . getTypeSizeInBits ( VecTy -> getElementType ( ) ) ; if ( ! Subtarget -> hasNEON ( ) && ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; if ( Subtarget -> hasNEON ( ) && VecTy -> getElementType ( ) -> isHalfTy ( ) ) return false ; if ( Subtarget -> hasMVEIntegerOps ( ) && Factor == 3 ) return false ; if ( VecTy -> getNumElements ( ) < 2 ) return false ; if ( ElSize != 8 && ElSize != 16 && ElSize != 32 ) return false ; if ( Subtarget -> hasNEON ( ) && VecSize == 64 ) return true ; return VecSize % 128 == 0 ; } </s>

Returns whether or not generating a interleaved load/store intrinsic for this type will be legal .


<s> static int mips_small_data_pattern_1 ( rtx x , enum mips_symbol_context context ) { subrtx_var_iterator :: array_type array ; FOR_EACH_SUBRTX_VAR ( iter , array , x , ALL ) { rtx x = * iter ; if ( GET_CODE ( x ) == LO_SUM || GET_CODE ( x ) == ASM_OPERANDS ) iter . skip_subrtxes ( ) ; else if ( MEM_P ( x ) ) { if ( mips_small_data_pattern_1 ( XEXP ( x , 0 ) , SYMBOL_CONTEXT_MEM ) ) return true ; iter . skip_subrtxes ( ) ; } else if ( mips_rewrite_small_data_p ( x , context ) ) return true ; } return false ; } </s>

A for_each_rtx callback for mips_small_data_pattern_p .


<s> static rtx riscv_pass_fpr_single ( machine_mode type_mode , unsigned regno , machine_mode value_mode ) { rtx x = gen_rtx_REG ( value_mode , regno ) ; if ( type_mode != value_mode ) { x = gen_rtx_EXPR_LIST ( VOIDmode , x , const0_rtx ) ; x = gen_rtx_PARALLEL ( type_mode , gen_rtvec ( 1 , x ) ) ; } return x ; } </s>

Return the representation of an argument passed or returned in an FPR when the value has mode VALUE_MODE and the type has TYPE_MODE . The two modes may be different for structures like : struct __attribute__ ( ( packed ) ) foo { float f ; } where the SFmode value `` f '' is passed in REGNO but the struct itself has mode BLKmode .


<s> void SparcTargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( ! Subtarget -> isTargetLinux ( ) ) return TargetLowering :: insertSSPDeclarations ( M ) ; } </s>

Inserts necessary declarations for SSP ( stack protection ) purpose .


<s> virtual const ARMSubtarget * getSubtarget ( ) { return Subtarget ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


<s>
static
void
seh_emit_save
(
FILE
*
f
,
struct
seh_frame_state
*
seh
,
rtx
reg
,
HOST_WIDE_INT
cfa_offset
)
{
unsigned
int
regno
=
REGNO
(
reg
)
;
HOST_WIDE_INT
offset
;
gcc_assert
(
seh
->
sp_offset
>=
cfa_offset
)
;
offset
=
seh
->
sp_offset
cfa_offset
;
fputs
(
(
SSE_REGNO_P
(
regno
)
"\t.seh_savexmm\t"
:
GENERAL_REGNO_P
(
regno
)
"\t.seh_savereg\t"
:
(
gcc_unreachable
(
)
,
""
)
)
,
f
)
;
print_reg
(
reg
,
0
,
f
)
;
fprintf
(
f
,
", "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
offset
)
;
}
</s>

Emit an assembler directive to save REG at CFA - CFA_OFFSET .


<s> static rtx rs6000_mask_atomic_subword ( rtx oldval , rtx newval , rtx mask ) { rtx x ; x = gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( x , gen_rtx_AND ( SImode , gen_rtx_NOT ( SImode , mask ) , oldval ) ) ) ; x = expand_simple_binop ( SImode , IOR , newval , x , x , 1 , OPTAB_LIB_WIDEN ) ; return x ; } </s>

A subroutine of the various atomic expanders . For sub-word operands , combine OLDVAL and NEWVAL via MASK . Returns a new pseduo .


<s> Function * AMDGPULibFunc :: getFunction ( Module * M , const AMDGPULibFunc & fInfo ) { std :: string FuncName = fInfo . mangle ( ) ; Function * F = dyn_cast_or_null < Function > ( M -> getValueSymbolTable ( ) . lookup ( FuncName ) ) ; if ( F && ! F -> isDeclaration ( ) && ! F -> isVarArg ( ) && F -> arg_size ( ) == fInfo . getNumArgs ( ) ) { return F ; } return nullptr ; } </s>

getFunction - Return this trace 's parent function .


<s> static rtx_insn * visium_md_asm_adjust ( vec < rtx > & , vec < rtx > & , vec < machine_mode > & , vec < const char * > & , vec < rtx > & clobbers , HARD_REG_SET & clobbered_regs , location_t ) { clobbers . safe_push ( gen_rtx_REG ( CCmode , FLAGS_REGNUM ) ) ; SET_HARD_REG_BIT ( clobbered_regs , FLAGS_REGNUM ) ; return NULL ; } </s>

Prepend to CLOBBERS hard registers that are automatically clobbered for an asm We do this for the FLAGS to maintain source compatibility with the original cc0-based compiler .


<s> const SPScope * SPScope :: getParent ( ) const { return Priv -> Parent ; } </s>

getParent - Return the last analyzed interval .


<s> bool SITargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Align , bool * IsFast ) const { if ( IsFast ) * IsFast = false ; if ( ! VT . isSimple ( ) || VT == MVT :: Other ) return false ; if ( AddrSpace == AMDGPUAS :: LOCAL_ADDRESS ) { return Align % 4 == 0 ; } if ( IsFast ) * IsFast = true ; return VT . bitsGT ( MVT :: i32 ) ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .