<s> bool PPCFastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { MVT VT ; if ( ! isLoadTypeLegal ( LI -> getType ( ) , VT ) ) return false ; bool IsZExt = false ; switch ( MI -> getOpcode ( ) ) { default : return false ; case PPC :: RLDICL : case PPC :: RLDICL_32_64 : { IsZExt = true ; unsigned MB = MI -> getOperand ( 3 ) . getImm ( ) ; if ( ( VT == MVT :: i8 && MB <= 56 ) || ( VT == MVT :: i16 && MB <= 48 ) || ( VT == MVT :: i32 && MB <= 32 ) ) break ; return false ; } case PPC :: RLWINM : case PPC :: RLWINM8 : { IsZExt = true ; unsigned MB = MI -> getOperand ( 3 ) . getImm ( ) ; if ( ( VT == MVT :: i8 && MB <= 24 ) || ( VT == MVT :: i16 && MB <= 16 ) ) break ; return false ; } case PPC :: EXTSB : case PPC :: EXTSB8 : case PPC :: EXTSB8_32_64 : return false ; case PPC :: EXTSH : case PPC :: EXTSH8 : case PPC :: EXTSH8_32_64 : { if ( VT != MVT :: i16 && VT != MVT :: i8 ) return false ; break ; } case PPC :: EXTSW : case PPC :: EXTSW_32_64 : { if ( VT != MVT :: i32 && VT != MVT :: i16 && VT != MVT :: i8 ) return false ; break ; } } Address Addr ; if ( ! PPCComputeAddress ( LI -> getOperand ( 0 ) , Addr ) ) return false ; unsigned ResultReg = MI -> getOperand ( 0 ) . getReg ( ) ; if ( ! PPCEmitLoad ( VT , ResultReg , Addr , nullptr , IsZExt ) ) return false ; MI -> eraseFromParent ( ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> MachineBasicBlock * SITargetLowering :: EmitInstrWithCustomInserter ( MachineInstr & MI , MachineBasicBlock * BB ) const { switch ( MI . getOpcode ( ) ) { case AMDGPU :: SI_INIT_M0 : { const SIInstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; BuildMI ( * BB , MI . getIterator ( ) , MI . getDebugLoc ( ) , TII -> get ( AMDGPU :: S_MOV_B32 ) , AMDGPU :: M0 ) . addOperand ( MI . getOperand ( 0 ) ) ; MI . eraseFromParent ( ) ; return BB ; } case AMDGPU :: GET_GROUPSTATICSIZE : { const SIInstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; MachineFunction * MF = BB -> getParent ( ) ; SIMachineFunctionInfo * MFI = MF -> getInfo < SIMachineFunctionInfo > ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; BuildMI ( * BB , MI , DL , TII -> get ( AMDGPU :: S_MOV_B32 ) ) . addOperand ( MI . getOperand ( 0 ) ) . addImm ( MFI -> getLDSSize ( ) ) ; MI . eraseFromParent ( ) ; return BB ; } case AMDGPU :: SI_INDIRECT_SRC_V1 : case AMDGPU :: SI_INDIRECT_SRC_V2 : case AMDGPU :: SI_INDIRECT_SRC_V4 : case AMDGPU :: SI_INDIRECT_SRC_V8 : case AMDGPU :: SI_INDIRECT_SRC_V16 : return emitIndirectSrc ( MI , * BB , getSubtarget ( ) -> getInstrInfo ( ) ) ; case AMDGPU :: SI_INDIRECT_DST_V1 : case AMDGPU :: SI_INDIRECT_DST_V2 : case AMDGPU :: SI_INDIRECT_DST_V4 : case AMDGPU :: SI_INDIRECT_DST_V8 : case AMDGPU :: SI_INDIRECT_DST_V16 : return emitIndirectDst ( MI , * BB , getSubtarget ( ) -> getInstrInfo ( ) ) ; case AMDGPU :: SI_KILL : return splitKillBlock ( MI , BB ) ; default : return AMDGPUTargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; } } </s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


";; [Global] Removing membar %d since order of accesses"

See if MEMBAR , the last membar instruction in BB , can be removed . FIRST_IO [ X ] describes the first operation performed by basic block X .


<s> static unsigned addLiveIn ( MachineFunction & MF , unsigned PReg , const TargetRegisterClass * RC ) { unsigned VReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MF . getRegInfo ( ) . addLiveIn ( PReg , VReg ) ; return VReg ; } </s>

addLiveIn - Add the specified register as a live-in .


"Calling %qD with attribute sseregparm without "

"Calling %qT with attribute sseregparm without "

Return 1 or 2 , if we can pass up to SSE_REGPARM_MAX SFmode ( 1 ) and DFmode ( 2 ) arguments in SSE registers for a function with the indicated TYPE and DECL . DECL may be NULL when calling function indirectly or considering a libcall . Otherwise return 0 .


"Suitable Machine Function for outlining must track liveness"

Optional target hook that returns true if MBB is safe to outline from , and returns any target-specific information in Flags .


<s> bool RISCVTargetLowering :: isMulAddWithConstProfitable ( const SDValue & AddNode , const SDValue & ConstNode ) const { EVT VT = AddNode . getValueType ( ) ; if ( VT . isVector ( ) ) return true ; if ( VT . getScalarSizeInBits ( ) > Subtarget . getXLen ( ) ) return true ; ConstantSDNode * C1Node = cast < ConstantSDNode > ( AddNode . getOperand ( 1 ) ) ; ConstantSDNode * C2Node = cast < ConstantSDNode > ( ConstNode ) ; const APInt & C1 = C1Node -> getAPIntValue ( ) ; const APInt & C2 = C2Node -> getAPIntValue ( ) ; if ( C1 . isSignedIntN ( 12 ) && ! ( C1 * C2 ) . isSignedIntN ( 12 ) ) return false ; return true ; } </s>

Return true if it may be profitable to transform ( mul ( add x , c1 ) , c2 ) - > ( add ( mul x , c2 ) , c1 * c2 ) .


<s> bool Thumb1InstrInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( ARM :: tPUSH ) ) ; AddDefaultPred ( MIB ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> rtx mips_msa_vec_parallel_const_half ( machine_mode mode , bool high_p ) { int nunits = GET_MODE_NUNITS ( mode ) ; rtvec v = rtvec_alloc ( nunits / 2 ) ; int base ; int i ; if ( BYTES_BIG_ENDIAN ) base = high_p ? 0 : nunits / 2 ; else base = high_p ? nunits / 2 : 0 ; for ( i = 0 ; i < nunits / 2 ; i ++ ) RTVEC_ELT ( v , i ) = GEN_INT ( base + i ) ; return gen_rtx_PARALLEL ( VOIDmode , v ) ; } </s>

Construct and return PARALLEL RTX with CONST_INTs for HIGH ( high_p == TRUE ) or LOW ( high_p == FALSE ) half of a vector for mode MODE .


<s>
bool
MipsAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
MCAsmParser
&
Parser
=
getParser
(
)
;
DEBUG
(
dbgs
(
)
<<
"ParseInstruction\n"
)
;
getTargetStreamer
(
)
.
forbidModuleDirective
(
)
;
if
(
!
mnemonicIsValid
(
Name
,
0
)
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
NameLoc
,
"unknown instruction"
)
;
}
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Name
,
NameLoc
,
*
this
)
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
parseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
&&
parseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
)
{
if
(
parseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
}
else
if
(
getLexer
(
)
.
is
(
AsmToken
::
LParen
)
&&
parseParenSuffix
(
Name
,
Operands
)
)
return
true
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Mips
Mips
"ParseInstruction\n"
0
"unknown instruction"
MipsOperand::CreateToken
"unexpected token in argument list"
"unexpected token in argument list"
"unexpected token in argument list"


<s> int ix86_unary_operator_ok ( enum rtx_code code ATTRIBUTE_UNUSED , enum machine_mode mode ATTRIBUTE_UNUSED , rtx operands [ 2 ] ATTRIBUTE_UNUSED ) { if ( ( GET_CODE ( operands [ 0 ] ) == MEM || GET_CODE ( operands [ 1 ] ) == MEM ) && ! rtx_equal_p ( operands [ 0 ] , operands [ 1 ] ) ) return FALSE ; return TRUE ; } </s>

Return TRUE or FALSE depending on whether the unary operator meets the appropriate constraints .


<s> RISCVTargetLowering :: ConstraintType RISCVTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'f' : case 'v' : return C_RegisterClass ; case 'I' : case 'J' : case 'K' : return C_Immediate ; case 'A' : return C_Memory ; case 'S' : return C_Other ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> getFnAttributes ( ) . hasOptimizeForSizeAttr ( ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( N -> getOpcode ( ) == X86ISD :: CALL || ( N -> getOpcode ( ) == X86ISD :: TC_RETURN && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; EVT SrcVT = N -> getOperand ( 0 ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( 0 ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; bool SrcIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s>
static
uint32_t
getBranchTargetOpValue
(
const
MCInst
&
MI
,
unsigned
OpIdx
,
unsigned
FixupKind
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
{
const
MCOperand
&
MO
=
MI
.
getOperand
(
OpIdx
)
;
if
(
MO
.
isImm
(
)
)
return
MO
.
getImm
(
)
;
assert
(
MO
.
isExpr
(
)
&&
"Unexpected branch target type!"
)
;
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
MCFixupKind
Kind
=
MCFixupKind
(
FixupKind
)
;
Fixups
.
push_back
(
MCFixup
::
create
(
0
,
Expr
,
Kind
,
MI
.
getLoc
(
)
)
)
;
return
0
;
}
</s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s>
void
arm_output_multireg_pop
(
rtx
*
operands
,
bool
return_pc
,
rtx
cond
,
bool
reverse
,
bool
update
)
{
int
i
;
char
pattern
[
100
]
;
int
offset
;
const
char
*
conditional
;
int
num_saves
=
XVECLEN
(
operands
[
0
]
,
0
)
;
unsigned
int
regno
;
unsigned
int
regno_base
=
REGNO
(
operands
[
1
]
)
;
offset
=
0
;
offset
+=
update
1
:
0
;
offset
+=
return_pc
1
:
0
;
for
(
i
=
offset
;
i
<
num_saves
;
i
++
)
{
regno
=
REGNO
(
XEXP
(
XVECEXP
(
operands
[
0
]
,
0
,
i
)
,
0
)
)
;
gcc_assert
(
(
regno
!=
SP_REGNUM
)
||
(
regno_base
==
SP_REGNUM
)
)
;
if
(
regno
==
regno_base
)
gcc_assert
(
!
update
)
;
}
conditional
=
reverse
"%?%D0"
:
"%?%d0"
;
if
(
(
regno_base
==
SP_REGNUM
)
&&
TARGET_UNIFIED_ASM
)
{
gcc_assert
(
update
)
;
sprintf
(
pattern
,
"pop%s\t{"
,
conditional
)
;
}
else
{
if
(
regno_base
==
SP_REGNUM
)
sprintf
(
pattern
,
"ldm%sfd\t"
,
conditional
)
;
else
if
(
TARGET_UNIFIED_ASM
)
sprintf
(
pattern
,
"ldmia%s\t"
,
conditional
)
;
else
sprintf
(
pattern
,
"ldm%sia\t"
,
conditional
)
;
strcat
(
pattern
,
reg_names
[
regno_base
]
)
;
if
(
update
)
strcat
(
pattern
,
"!, {"
)
;
else
strcat
(
pattern
,
", {"
)
;
}
strcat
(
pattern
,
reg_names
[
REGNO
(
XEXP
(
XVECEXP
(
operands
[
0
]
,
0
,
offset
)
,
0
)
)
]
)
;
for
(
i
=
offset
+
1
;
i
<
num_saves
;
i
++
)
{
strcat
(
pattern
,
", "
)
;
strcat
(
pattern
,
reg_names
[
REGNO
(
XEXP
(
XVECEXP
(
operands
[
0
]
,
0
,
i
)
,
0
)
)
]
)
;
}
strcat
(
pattern
,
"}"
)
;
if
(
IS_INTERRUPT
(
arm_current_func_type
(
)
)
&&
return_pc
)
strcat
(
pattern
,
"^"
)
;
output_asm_insn
(
pattern
,
&
cond
)
;
}
</s>

OPERANDS [ 0 ] is the entire list of insns that constitute pop , OPERANDS [ 1 ] is the base register , RETURN_PC is true iff return insn is in the list , UPDATE is true iff the list contains explicit update of base register .


<s> static tree nvptx_get_shared_red_addr ( tree type , tree offset , bool vector ) { enum nvptx_builtins addr_dim = NVPTX_BUILTIN_WORKER_ADDR ; if ( vector ) addr_dim = NVPTX_BUILTIN_VECTOR_ADDR ; machine_mode mode = TYPE_MODE ( type ) ; tree fndecl = nvptx_builtin_decl ( addr_dim , true ) ; tree size = build_int_cst ( unsigned_type_node , GET_MODE_SIZE ( mode ) ) ; tree align = build_int_cst ( unsigned_type_node , GET_MODE_ALIGNMENT ( mode ) / BITS_PER_UNIT ) ; tree call = build_call_expr ( fndecl , 3 , offset , size , align ) ; return fold_convert ( build_pointer_type ( type ) , call ) ; } </s>

Generate a PTX builtin function call that returns the address in the worker reduction buffer at OFFSET . TYPE is the type of the data at that location .


"should only be seeing stack pointer offset relative FrameIndex"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> unsigned Z80oldRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return getFrameLowering ( MF ) -> hasFP ( MF ) ? Z80old :: IX : Z80old :: SPS ; } </s>


"Missing call preserved mask for calling convention"

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


"getRegForInlineAsmConstraint Unhandled data type"

Given a physical register constraint ( e.g .


<s> static sbitmap rs6000_components_for_bb ( basic_block bb ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; bitmap in = DF_LIVE_IN ( bb ) ; bitmap gen = & DF_LIVE_BB_INFO ( bb ) -> gen ; bitmap kill = & DF_LIVE_BB_INFO ( bb ) -> kill ; sbitmap components = sbitmap_alloc ( cfun -> machine -> n_components ) ; bitmap_clear ( components ) ; for ( unsigned regno = info -> first_gp_reg_save ; regno < 32 ; regno ++ ) if ( bitmap_bit_p ( in , regno ) || bitmap_bit_p ( gen , regno ) || bitmap_bit_p ( kill , regno ) ) bitmap_set_bit ( components , regno ) ; for ( unsigned regno = info -> first_fp_reg_save ; regno < 64 ; regno ++ ) if ( bitmap_bit_p ( in , regno ) || bitmap_bit_p ( gen , regno ) || bitmap_bit_p ( kill , regno ) ) bitmap_set_bit ( components , regno ) ; if ( bitmap_bit_p ( in , LR_REGNO ) || bitmap_bit_p ( gen , LR_REGNO ) || bitmap_bit_p ( kill , LR_REGNO ) ) bitmap_set_bit ( components , 0 ) ; if ( bitmap_bit_p ( in , TOC_REGNUM ) || bitmap_bit_p ( gen , TOC_REGNUM ) || bitmap_bit_p ( kill , TOC_REGNUM ) ) bitmap_set_bit ( components , 2 ) ; return components ; } </s>


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , RM , CM , OL ) , Subtarget ( TT , CPU , FS , is64bit ) , DataLayout ( Subtarget . getDataLayout ( ) ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrInfo ( Subtarget ) , FrameLowering ( Subtarget ) { } </s>


<s> int mmix_function_arg_regno_p ( int regno , int incoming ) { int first_arg_regnum = incoming ? MMIX_FIRST_INCOMING_ARG_REGNUM : MMIX_FIRST_ARG_REGNUM ; return regno >= first_arg_regnum && regno < first_arg_regnum + MMIX_MAX_ARGS_IN_REGS ; } </s>

Return nonzero if regno is a register number where a parameter is passed , and 0 otherwise .


<s> bool SITargetLowering :: requiresUniformRegister ( MachineFunction & MF , const Value * V ) const { if ( const IntrinsicInst * Intrinsic = dyn_cast < IntrinsicInst > ( V ) ) { switch ( Intrinsic -> getIntrinsicID ( ) ) { default : return false ; case Intrinsic :: amdgcn_if_break : return true ; } } if ( const ExtractValueInst * ExtValue = dyn_cast < ExtractValueInst > ( V ) ) { if ( const IntrinsicInst * Intrinsic = dyn_cast < IntrinsicInst > ( ExtValue -> getOperand ( 0 ) ) ) { switch ( Intrinsic -> getIntrinsicID ( ) ) { default : return false ; case Intrinsic :: amdgcn_if : case Intrinsic :: amdgcn_else : { ArrayRef < unsigned > Indices = ExtValue -> getIndices ( ) ; if ( Indices . size ( ) == 1 && Indices [ 0 ] == 1 ) { return true ; } } } } } if ( const CallInst * CI = dyn_cast < CallInst > ( V ) ) { if ( isa < InlineAsm > ( CI -> getCalledValue ( ) ) ) { const SIRegisterInfo * SIRI = Subtarget -> getRegisterInfo ( ) ; ImmutableCallSite CS ( CI ) ; TargetLowering :: AsmOperandInfoVector TargetConstraints = ParseConstraints ( MF . getDataLayout ( ) , Subtarget -> getRegisterInfo ( ) , CS ) ; for ( auto & TC : TargetConstraints ) { if ( TC . Type == InlineAsm :: isOutput ) { ComputeConstraintToUse ( TC , SDValue ( ) ) ; unsigned AssignedReg ; const TargetRegisterClass * RC ; std :: tie ( AssignedReg , RC ) = getRegForInlineAsmConstraint ( SIRI , TC . ConstraintCode , TC . ConstraintVT ) ; if ( RC ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( AssignedReg != 0 && SIRI -> isSGPRReg ( MRI , AssignedReg ) ) return true ; else if ( SIRI -> isSGPRClass ( RC ) ) return true ; } } } } } SmallPtrSet < const Value * , 16 > Visited ; return hasCFUser ( V , Visited , Subtarget -> getWavefrontSize ( ) ) ; } </s>

Allows target to decide about the register class of the specific value that is live outside the defining block .


<s> bool isLegalNTStore ( Type * DataType , Align Alignment ) { if ( auto * DataTypeVTy = dyn_cast < VectorType > ( DataType ) ) { unsigned NumElements = cast < FixedVectorType > ( DataTypeVTy ) -> getNumElements ( ) ; unsigned EltSize = DataTypeVTy -> getElementType ( ) -> getScalarSizeInBits ( ) ; return NumElements > 1 && isPowerOf2_64 ( NumElements ) && EltSize >= 8 && EltSize <= 128 && isPowerOf2_64 ( EltSize ) ; } return BaseT :: isLegalNTStore ( DataType , Alignment ) ; } </s>

Return true if the target supports nontemporal store .


<s>
bool
Z80DAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
SDValue
Op0
,
Op1
;
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_m
:
if
(
!
SelectMem
(
Op
,
Op0
)
)
return
true
;
OutOps
.
push_back
(
Op0
)
;
return
false
;
case
InlineAsm
::
Constraint_o
:
if
(
!
SelectOff
(
Op
,
Op0
,
Op1
)
)
return
true
;
OutOps
.
push_back
(
Op0
)
;
OutOps
.
push_back
(
Op1
)
;
return
false
;
}
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> BPFSubtarget & BPFSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { initializeEnvironment ( ) ; initSubtargetFeatures ( CPU , FS ) ; ParseSubtargetFeatures ( CPU , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> void init_cumulative_args ( CUMULATIVE_ARGS * cum , tree fntype , rtx libname ATTRIBUTE_UNUSED ) { static CUMULATIVE_ARGS zero_cum ; tree param , next_param ; * cum = zero_cum ; cum -> prototype = ( fntype && TYPE_ARG_TYPES ( fntype ) ) ; for ( param = fntype ? TYPE_ARG_TYPES ( fntype ) : 0 ; param != 0 ; param = next_param ) { next_param = TREE_CHAIN ( param ) ; if ( next_param == 0 && TREE_VALUE ( param ) != void_type_node ) cum -> gp_reg_found = 1 ; } } </s>

Handle the INIT_CUMULATIVE_ARGS macro . Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is 0 .


<s> int includes_rldic_lshift_p ( rtx shiftop , rtx andop ) { if ( GET_CODE ( andop ) == CONST_INT ) { HOST_WIDE_INT c , lsb , shift_mask ; c = INTVAL ( andop ) ; if ( c == 0 || c == ~ 0 ) return 0 ; shift_mask = ~ 0 ; shift_mask <<= INTVAL ( shiftop ) ; lsb = c & - c ; if ( - lsb != shift_mask ) return 0 ; c = ~ c ; c &= - lsb ; lsb = c & - c ; return c == - lsb ; } else if ( GET_CODE ( andop ) == CONST_DOUBLE && ( GET_MODE ( andop ) == VOIDmode || GET_MODE ( andop ) == DImode ) ) { HOST_WIDE_INT low , high , lsb ; HOST_WIDE_INT shift_mask_low , shift_mask_high ; low = CONST_DOUBLE_LOW ( andop ) ; if ( HOST_BITS_PER_WIDE_INT < 64 ) high = CONST_DOUBLE_HIGH ( andop ) ; if ( ( low == 0 && ( HOST_BITS_PER_WIDE_INT >= 64 || high == 0 ) ) || ( low == ~ 0 && ( HOST_BITS_PER_WIDE_INT >= 64 || high == ~ 0 ) ) ) return 0 ; if ( HOST_BITS_PER_WIDE_INT < 64 && low == 0 ) { shift_mask_high = ~ 0 ; if ( INTVAL ( shiftop ) > 32 ) shift_mask_high <<= INTVAL ( shiftop ) - 32 ; lsb = high & - high ; if ( - lsb != shift_mask_high || INTVAL ( shiftop ) < 32 ) return 0 ; high = ~ high ; high &= - lsb ; lsb = high & - high ; return high == - lsb ; } shift_mask_low = ~ 0 ; shift_mask_low <<= INTVAL ( shiftop ) ; lsb = low & - low ; if ( - lsb != shift_mask_low ) return 0 ; if ( HOST_BITS_PER_WIDE_INT < 64 ) high = ~ high ; low = ~ low ; low &= - lsb ; if ( HOST_BITS_PER_WIDE_INT < 64 && low == 0 ) { lsb = high & - high ; return high == - lsb ; } lsb = low & - low ; return low == - lsb && ( HOST_BITS_PER_WIDE_INT >= 64 || high == ~ 0 ) ; } else return 0 ; } </s>

Return 1 if ANDOP is a mask suitable for use with an rldic insn to perform a left shift . It must have exactly SHIFTOP least significant 0 's , then one or more 1 's , then zero or more 0 's .


<s> static unsigned getTOCSaveOffset ( bool isELFv2ABI ) { return isELFv2ABI ? 24 : 40 ; } </s>

getTOCSaveOffset - Return the previous frame offset to save the TOC register � ? 64-bit SVR4 ABI only .


<s> unsigned MipsSEInstrInfo :: loadImmediate ( int64_t Imm , MachineBasicBlock & MBB , MachineBasicBlock :: iterator II , DebugLoc DL , unsigned * NewImm ) const { MipsAnalyzeImmediate AnalyzeImm ; const MipsSubtarget & STI = Subtarget ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; unsigned Size = STI . isABI_N64 ( ) ? 64 : 32 ; unsigned LUi = STI . isABI_N64 ( ) ? Mips :: LUi64 : Mips :: LUi ; unsigned ZEROReg = STI . isABI_N64 ( ) ? Mips :: ZERO_64 : Mips :: ZERO ; const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; bool LastInstrIsADDiu = NewImm ; const MipsAnalyzeImmediate :: InstSeq & Seq = AnalyzeImm . Analyze ( Imm , Size , LastInstrIsADDiu ) ; MipsAnalyzeImmediate :: InstSeq :: const_iterator Inst = Seq . begin ( ) ; assert ( Seq . size ( ) && ( ! LastInstrIsADDiu || ( Seq . size ( ) > 1 ) ) ) ; unsigned Reg = RegInfo . createVirtualRegister ( RC ) ; if ( Inst -> Opc == LUi ) BuildMI ( MBB , II , DL , get ( LUi ) , Reg ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; else BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , Reg ) . addReg ( ZEROReg ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; for ( ++ Inst ; Inst != Seq . end ( ) - LastInstrIsADDiu ; ++ Inst ) BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; if ( LastInstrIsADDiu ) * NewImm = Inst -> ImmOpnd ; return Reg ; } </s>

Emit a series of instructions to load an immediate .


<s> void asm_conditional_branch ( rtx_insn * insn , rtx * operands , int n_nops , int predict_taken ) { int offset = branch_dest ( insn ) - INSN_ADDRESSES ( INSN_UID ( insn ) ) ; int len = ( offset >= - 1024 && offset <= 1022 ? 0 : offset >= - 4094 && offset <= 4096 ? 1 : 2 ) ; int bp = predict_taken && len == 0 ? 1 : cbranch_predicted_taken_p ( insn ) ; int idx = ( bp << 1 ) | ( GET_CODE ( operands [ 0 ] ) == EQ ? BRF : BRT ) ; output_asm_insn ( ccbranch_templates [ idx ] [ len ] , operands ) ; gcc_assert ( n_nops == 0 || ! bp ) ; if ( len == 0 ) while ( n_nops -- > 0 ) output_asm_insn ( "nop;" , NULL ) ; } </s>

Output INSN , which is a conditional branch instruction with operands OPERANDS . We deal with the various forms of conditional branches that can be generated by bfin_reorg to prevent the hardware from doing speculative loads , by - emitting a sufficient number of nops , if N_NOPS is nonzero , or - always emitting the branch as predicted taken , if PREDICT_TAKEN is true . Either of these is only necessary if the branch is short , otherwise the template we use ends in an unconditional jump which flushes the pipeline anyway .


<s> inline void function_expander :: add_integer_operand ( rtx x ) { create_integer_operand ( & m_ops [ opno ++ ] , INTVAL ( x ) ) ; } </s>


<s> static bool aarch64_evpc_ext ( struct expand_vec_perm_d * d ) { unsigned int i , nelt = d -> nelt ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; rtx offset ; unsigned int location = d -> perm [ 0 ] ; for ( i = 1 ; i < nelt ; i ++ ) { unsigned int required = location + i ; if ( d -> one_vector_p ) { required &= ( nelt - 1 ) ; } if ( d -> perm [ i ] != required ) return false ; } switch ( d -> vmode ) { case V16QImode : gen = gen_aarch64_extv16qi ; break ; case V8QImode : gen = gen_aarch64_extv8qi ; break ; case V4HImode : gen = gen_aarch64_extv4hi ; break ; case V8HImode : gen = gen_aarch64_extv8hi ; break ; case V2SImode : gen = gen_aarch64_extv2si ; break ; case V4SImode : gen = gen_aarch64_extv4si ; break ; case V2SFmode : gen = gen_aarch64_extv2sf ; break ; case V4SFmode : gen = gen_aarch64_extv4sf ; break ; case V2DImode : gen = gen_aarch64_extv2di ; break ; case V2DFmode : gen = gen_aarch64_extv2df ; break ; default : return false ; } if ( d -> testing_p ) return true ; if ( BYTES_BIG_ENDIAN && ( location != 0 ) ) { std :: swap ( d -> op0 , d -> op1 ) ; location = nelt - location ; } offset = GEN_INT ( location ) ; emit_insn ( gen ( d -> target , d -> op0 , d -> op1 , offset ) ) ; return true ; } </s>


<s>
bool
AMDGPUCallLowering
::
lowerReturn
(
MachineIRBuilder
&
MIRBuilder
,
const
Value
*
Val
,
ArrayRef
<
Register
>
VRegs
)
const
{
MachineFunction
&
MF
=
MIRBuilder
.
getMF
(
)
;
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
SIMachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MFI
->
setIfReturnsVoid
(
!
Val
)
;
assert
(
!
Val
==
VRegs
.
empty
(
)
&&
"Return value without a vreg"
)
;
CallingConv
::
ID
CC
=
MIRBuilder
.
getMF
(
)
.
getFunction
(
)
.
getCallingConv
(
)
;
const
bool
IsShader
=
AMDGPU
::
isShader
(
CC
)
;
const
bool
IsWaveEnd
=
(
IsShader
&&
MFI
->
returnsVoid
(
)
)
||
AMDGPU
::
isKernel
(
CC
)
;
if
(
IsWaveEnd
)
{
MIRBuilder
.
buildInstr
(
AMDGPU
::
S_ENDPGM
)
.
addImm
(
0
)
;
return
true
;
}
auto
const
&
ST
=
MIRBuilder
.
getMF
(
)
.
getSubtarget
<
GCNSubtarget
>
(
)
;
unsigned
ReturnOpc
=
ReturnOpc
=
IsShader
AMDGPU
::
SI_RETURN_TO_EPILOG
:
AMDGPU
::
S_SETPC_B64_return
;
auto
Ret
=
MIRBuilder
.
buildInstrNoInsert
(
ReturnOpc
)
;
Register
ReturnAddrVReg
;
if
(
ReturnOpc
==
AMDGPU
::
S_SETPC_B64_return
)
{
ReturnAddrVReg
=
MRI
.
createVirtualRegister
(
&
AMDGPU
::
CCR_SGPR_64RegClass
)
;
Ret
.
addUse
(
ReturnAddrVReg
)
;
}
if
(
!
lowerReturnVal
(
MIRBuilder
,
Val
,
VRegs
,
Ret
)
)
return
false
;
if
(
ReturnOpc
==
AMDGPU
::
S_SETPC_B64_return
)
{
const
SIRegisterInfo
*
TRI
=
ST
.
getRegisterInfo
(
)
;
Register
LiveInReturn
=
MF
.
addLiveIn
(
TRI
->
getReturnAddressReg
(
MF
)
,
&
AMDGPU
::
SGPR_64RegClass
)
;
MIRBuilder
.
buildCopy
(
ReturnAddrVReg
,
LiveInReturn
)
;
}
MIRBuilder
.
insertInstr
(
Ret
)
;
return
true
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> static int no_previous_def ( tree function_name ) { branch_island * bi ; unsigned ix ; FOR_EACH_VEC_SAFE_ELT ( branch_islands , ix , bi ) if ( function_name == bi -> function_name ) return 0 ; return 1 ; } </s>

NO_PREVIOUS_DEF checks in the link list whether the function name is already there or not .


<s> bool AArch64InstrInfo :: getMemOperandWithOffset ( MachineInstr & LdSt , MachineOperand * & BaseOp , int64_t & Offset , const TargetRegisterInfo * TRI ) const { unsigned Width ; return getMemOperandWithOffsetWidth ( LdSt , BaseOp , Offset , Width , TRI ) ; } </s>

Get the base operand and byte offset of an instruction that reads/writes memory .


"No offset range is defined for this opcode. "

"Please define it in the above switch statement!"


<s> void AMDGPUDAGToDAGISel :: PostprocessISelDAG ( ) { const AMDGPUTargetLowering & Lowering = * static_cast < const AMDGPUTargetLowering * > ( getTargetLowering ( ) ) ; bool IsModified = false ; do { IsModified = false ; for ( SDNode & Node : CurDAG -> allnodes ( ) ) { MachineSDNode * MachineNode = dyn_cast < MachineSDNode > ( & Node ) ; if ( ! MachineNode ) continue ; SDNode * ResNode = Lowering . PostISelFolding ( MachineNode , * CurDAG ) ; if ( ResNode != & Node ) { ReplaceUses ( & Node , ResNode ) ; IsModified = true ; } } CurDAG -> RemoveDeadNodes ( ) ; } while ( IsModified ) ; } </s>

PostprocessISelDAG ( ) - This hook allows the target to hack on the graph right after selection .


<s> std :: pair < unsigned , const TargetRegisterClass * > SITargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI_ , StringRef Constraint , MVT VT ) const { const SIRegisterInfo * TRI = static_cast < const SIRegisterInfo * > ( TRI_ ) ; const TargetRegisterClass * RC = nullptr ; if ( Constraint . size ( ) == 1 ) { const unsigned BitWidth = VT . getSizeInBits ( ) ; switch ( Constraint [ 0 ] ) { default : return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; case 's' : case 'r' : switch ( BitWidth ) { case 16 : RC = & AMDGPU :: SReg_32RegClass ; break ; case 64 : RC = & AMDGPU :: SGPR_64RegClass ; break ; default : RC = SIRegisterInfo :: getSGPRClassForBitWidth ( BitWidth ) ; if ( ! RC ) return std :: make_pair ( 0U , nullptr ) ; break ; } break ; case 'v' : switch ( BitWidth ) { case 16 : RC = & AMDGPU :: VGPR_32RegClass ; break ; default : RC = TRI -> getVGPRClassForBitWidth ( BitWidth ) ; if ( ! RC ) return std :: make_pair ( 0U , nullptr ) ; break ; } break ; case 'a' : if ( ! Subtarget -> hasMAIInsts ( ) ) break ; switch ( BitWidth ) { case 16 : RC = & AMDGPU :: AGPR_32RegClass ; break ; default : RC = TRI -> getAGPRClassForBitWidth ( BitWidth ) ; if ( ! RC ) return std :: make_pair ( 0U , nullptr ) ; break ; } break ; } if ( RC && ( isTypeLegal ( VT ) || VT . SimpleTy == MVT :: i128 || VT . SimpleTy == MVT :: i16 || VT . SimpleTy == MVT :: f16 ) ) return std :: make_pair ( 0U , RC ) ; } if ( Constraint . size ( ) > 1 ) { if ( Constraint [ 1 ] == 'v' ) { RC = & AMDGPU :: VGPR_32RegClass ; } else if ( Constraint [ 1 ] == 's' ) { RC = & AMDGPU :: SGPR_32RegClass ; } else if ( Constraint [ 1 ] == 'a' ) { RC = & AMDGPU :: AGPR_32RegClass ; } if ( RC ) { uint32_t Idx ; bool Failed = Constraint . substr ( 2 ) . getAsInteger ( 10 , Idx ) ; if ( ! Failed && Idx < RC -> getNumRegs ( ) ) return std :: make_pair ( RC -> getRegister ( Idx ) , RC ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>


<s>
SDValue
TriCoreTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
case
ISD
::
SHL
:
case
ISD
::
SRL
:
case
ISD
::
SRA
:
return
LowerShifts
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

TriCore
TriCore
ISD::GlobalAddress
ISD::BR_CC
ISD::SELECT_CC
ISD::SETCC
ISD::SHL
ISD::SRL
ISD::SRA
"unimplemented operand"


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> bool PPCPassConfig :: addPreEmitPass ( ) { PM -> add ( createPPCBranchSelectionPass ( ) ) ; return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool HexagonInstrInfo :: isPostIncrement ( const MachineInstr & MI ) const { return getAddrMode ( MI ) == HexagonII :: PostInc ; } </s>

Return true for post-incremented instructions .


<s> rtx ix86_replace_reg_with_reg ( rtx x , rtx from , rtx to ) { gcc_checking_assert ( REG_P ( from ) && REG_P ( to ) && GET_MODE ( from ) == GET_MODE ( to ) ) ; if ( ! reg_overlap_mentioned_p ( from , x ) ) return x ; rtx ret = copy_rtx ( x ) ; subrtx_ptr_iterator :: array_type array ; FOR_EACH_SUBRTX_PTR ( iter , array , & ret , NONCONST ) { rtx * loc = * iter ; x = * loc ; if ( REG_P ( x ) && REGNO ( x ) == REGNO ( from ) ) { if ( x == from ) * loc = to ; else { gcc_checking_assert ( REG_NREGS ( x ) == 1 ) ; * loc = gen_rtx_REG ( GET_MODE ( x ) , REGNO ( to ) ) ; } } } return ret ; } </s>

Replace all occurrences of REG FROM with REG TO in X , including occurrences with different modes .


<s> bool PPCTTIImpl :: enableAggressiveInterleaving ( bool LoopHasReductions ) { if ( ST -> getCPUDirective ( ) == PPC :: DIR_A2 ) return true ; return LoopHasReductions ; } </s>

Do n't restrict interleaved unrolling to small loops .


<s> static int pad_groups ( FILE * dump , int sched_verbose , rtx_insn * prev_head_insn , rtx_insn * tail ) { rtx_insn * insn , * next_insn ; rtx nop ; int issue_rate ; int can_issue_more ; int group_end ; int group_count = 0 ; issue_rate = rs6000_issue_rate ( ) ; can_issue_more = issue_rate ; insn = get_next_active_insn ( prev_head_insn , tail ) ; next_insn = get_next_active_insn ( insn , tail ) ; while ( insn != NULL_RTX ) { can_issue_more = rs6000_variable_issue ( dump , sched_verbose , insn , can_issue_more ) ; group_end = ( next_insn == NULL_RTX || GET_MODE ( next_insn ) == TImode ) ; if ( next_insn == NULL_RTX ) break ; if ( group_end ) { if ( can_issue_more && ( rs6000_sched_insert_nops == sched_finish_pad_groups ) && ! insn_terminates_group_p ( insn , current_group ) && ! insn_terminates_group_p ( next_insn , previous_group ) ) { if ( ! is_branch_slot_insn ( next_insn ) ) can_issue_more -- ; while ( can_issue_more ) { nop = gen_nop ( ) ; emit_insn_before ( nop , next_insn ) ; can_issue_more -- ; } } can_issue_more = issue_rate ; group_count ++ ; } insn = next_insn ; next_insn = get_next_active_insn ( insn , tail ) ; } return group_count ; } </s>

Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the dispatch group boundaries that the scheduler had marked . Pad with nops any dispatch groups which have vacant issue slots , in order to force the scheduler 's grouping on the processor dispatcher . The function returns the number of dispatch groups found .


<s>
bool
AArch64InstrInfo
::
isGPRCopy
(
const
MachineInstr
*
MI
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
TargetOpcode
::
COPY
:
{
unsigned
DstReg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
return
(
AArch64
::
GPR32RegClass
.
contains
(
DstReg
)
||
AArch64
::
GPR64RegClass
.
contains
(
DstReg
)
)
;
}
case
AArch64
::
ORRXrs
:
if
(
MI
->
getOperand
(
1
)
.
getReg
(
)
==
AArch64
::
XZR
)
{
assert
(
MI
->
getDesc
(
)
.
getNumOperands
(
)
==
4
&&
MI
->
getOperand
(
3
)
.
getImm
(
)
==
0
&&
"invalid ORRrs operands"
)
;
return
true
;
}
case
AArch64
::
ADDXri
:
if
(
MI
->
getOperand
(
2
)
.
getImm
(
)
==
0
)
{
assert
(
MI
->
getDesc
(
)
.
getNumOperands
(
)
==
4
&&
MI
->
getOperand
(
3
)
.
getImm
(
)
==
0
&&
"invalid ADDXri operands"
)
;
return
true
;
}
}
return
false
;
}
</s>

Does this instruction rename a GPR without modifying bits ?


<s> static rtx s390_execute_label ( rtx insn ) { if ( INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == PARALLEL && GET_CODE ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) ) == UNSPEC && ( XINT ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) , 1 ) == UNSPEC_EXECUTE || XINT ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) , 1 ) == UNSPEC_EXECUTE_JUMP ) ) { if ( XINT ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) , 1 ) == UNSPEC_EXECUTE ) return XVECEXP ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) , 0 , 2 ) ; else { gcc_assert ( JUMP_P ( insn ) ) ; return XEXP ( XVECEXP ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) , 0 , 0 ) , 0 ) ; } } return NULL_RTX ; } </s>

Check whether INSN is an execute . Return the label_ref to its execute target template if so , NULL_RTX otherwise .


<s> int X86TTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind , Instruction * Inst ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; unsigned ImmIdx = ~ 0U ; switch ( Opcode ) { default : return TTI :: TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: Store : ImmIdx = 0 ; break ; case Instruction :: ICmp : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 ) { uint64_t ImmVal = Imm . getZExtValue ( ) ; if ( ImmVal == 0x100000000ULL || ImmVal == 0xffffffff ) return TTI :: TCC_Free ; } ImmIdx = 1 ; break ; case Instruction :: And : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 && isUInt < 32 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; ImmIdx = 1 ; break ; case Instruction :: Add : case Instruction :: Sub : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 && Imm . getZExtValue ( ) == 0x80000000 ) return TTI :: TCC_Free ; ImmIdx = 1 ; break ; case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : return TTI :: TCC_Free ; case Instruction :: Mul : case Instruction :: Or : case Instruction :: Xor : ImmIdx = 1 ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == 1 ) return TTI :: TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: IntToPtr : case Instruction :: PtrToInt : case Instruction :: BitCast : case Instruction :: PHI : case Instruction :: Call : case Instruction :: Select : case Instruction :: Ret : case Instruction :: Load : break ; } if ( Idx == ImmIdx ) { int NumConstants = divideCeil ( BitSize , 64 ) ; int Cost = X86TTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ; return ( Cost <= NumConstants * TTI :: TCC_Basic ) ? static_cast < int > ( TTI :: TCC_Free ) : Cost ; } return X86TTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> void PPCPassConfig :: addPreEmitPass2 ( ) { addPass ( createPPCExpandAtomicPseudoPass ( ) ) ; addPass ( createPPCBranchSelectionPass ( ) ) ; } </s>

Targets may add passes immediately before machine code is emitted in this callback .


"boolean registers required for the floating-point option"

"-f%s ignored (all code is position independent)"

Set global variables as needed for the options enabled .


<s> gimple * fold ( gimple_folder & f ) const override { poly_uint64 nelts = TYPE_VECTOR_SUBPARTS ( TREE_TYPE ( f . lhs ) ) ; poly_uint64 base = m_base * exact_div ( nelts , 2 ) ; vec_perm_builder builder ( nelts , 2 , 3 ) ; for ( unsigned int i = 0 ; i < 3 ; ++ i ) { builder . quick_push ( base + i ) ; builder . quick_push ( base + i + nelts ) ; } return fold_permute ( f , builder ) ; } </s>

Try to fold the call . Return the new statement on success and null on failure .


<s> void rs6000_xcoff_asm_globalize_decl_name ( FILE * stream , tree decl ) { const char * name = XSTR ( XEXP ( DECL_RTL ( decl ) , 0 ) , 0 ) ; fputs ( GLOBAL_ASM_OP , stream ) ; RS6000_OUTPUT_BASENAME ( stream , name ) ; fputs ( rs6000_xcoff_visibility ( decl ) , stream ) ; putc ( '\n' , stream ) ; } </s>

Output assembly language to globalize a symbol from a DECL , possibly with visibility .


<s> bool mips_small_data_pattern_p ( rtx op ) { return for_each_rtx ( & op , mips_small_data_pattern_1 , 0 ) ; } </s>

Return true if OP refers to small data symbols directly , not through a LO_SUM .


<s> void aarch64_sls_emit_blr_function_thunks ( FILE * out_file ) { if ( ! aarch64_harden_sls_blr_p ( ) ) return ; bool any_functions_emitted = false ; section * save_text_section = in_section ; switch_to_section ( function_section ( current_function_decl ) ) ; for ( int regnum = 0 ; regnum < 30 ; ++ regnum ) { rtx specu_label = cfun -> machine -> call_via [ regnum ] ; if ( specu_label == NULL ) continue ; targetm . asm_out . print_operand ( out_file , specu_label , 0 ) ; asm_fprintf ( out_file , ":\n" ) ; aarch64_sls_emit_function_stub ( out_file , regnum ) ; any_functions_emitted = true ; } if ( any_functions_emitted ) asm_fprintf ( out_file , "\t%s\n" , aarch64_sls_barrier ( true ) ) ; switch_to_section ( save_text_section ) ; } </s>

Emit all BLR stubs for this particular function . Here we emit all the BLR stubs needed for the current function . Since we emit these stubs in a consecutive block we know there will be no speculation gadgets between each stub , and hence we only emit a speculation barrier at the end of the stub sequences . This is called in the TARGET_ASM_FUNCTION_EPILOGUE hook .


<s> unsigned getStackAlignment ( ) const { return stackAlignment ; } </s>

Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget .


<s> void PPCTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { Known . resetAll ( ) ; switch ( Op . getOpcode ( ) ) { default : break ; case PPCISD :: LBRX : { if ( cast < VTSDNode > ( Op . getOperand ( 2 ) ) -> getVT ( ) == MVT :: i16 ) Known . Zero = 0xFFFF0000 ; break ; } case ISD :: INTRINSIC_WO_CHAIN : { switch ( cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ) { default : break ; case Intrinsic :: ppc_altivec_vcmpbfp_p : case Intrinsic :: ppc_altivec_vcmpeqfp_p : case Intrinsic :: ppc_altivec_vcmpequb_p : case Intrinsic :: ppc_altivec_vcmpequh_p : case Intrinsic :: ppc_altivec_vcmpequw_p : case Intrinsic :: ppc_altivec_vcmpequd_p : case Intrinsic :: ppc_altivec_vcmpequq_p : case Intrinsic :: ppc_altivec_vcmpgefp_p : case Intrinsic :: ppc_altivec_vcmpgtfp_p : case Intrinsic :: ppc_altivec_vcmpgtsb_p : case Intrinsic :: ppc_altivec_vcmpgtsh_p : case Intrinsic :: ppc_altivec_vcmpgtsw_p : case Intrinsic :: ppc_altivec_vcmpgtsd_p : case Intrinsic :: ppc_altivec_vcmpgtsq_p : case Intrinsic :: ppc_altivec_vcmpgtub_p : case Intrinsic :: ppc_altivec_vcmpgtuh_p : case Intrinsic :: ppc_altivec_vcmpgtuw_p : case Intrinsic :: ppc_altivec_vcmpgtud_p : case Intrinsic :: ppc_altivec_vcmpgtuq_p : Known . Zero = ~ 1U ; break ; } break ; } case ISD :: INTRINSIC_W_CHAIN : { switch ( cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) -> getZExtValue ( ) ) { default : break ; case Intrinsic :: ppc_load2r : Known . Zero = 0xFFFF0000 ; break ; } break ; } } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> bool PPCDarwinAsmPrinter :: doFinalization ( Module & M ) { bool isPPC64 = TM . getDataLayout ( ) -> getPointerSizeInBits ( 0 ) == 64 ; const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetFnStubList ( ) ; if ( ! Stubs . empty ( ) ) EmitFunctionStubs ( Stubs ) ; if ( MAI -> doesSupportExceptionHandling ( ) && MMI ) { const std :: vector < const Function * > & Personalities = MMI -> getPersonalities ( ) ; for ( std :: vector < const Function * > :: const_iterator I = Personalities . begin ( ) , E = Personalities . end ( ) ; I != E ; ++ I ) { if ( * I ) { MCSymbol * NLPSym = GetSymbolWithGlobalValueBase ( * I , "$non_lazy_ptr" ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMIMacho . getGVStubEntry ( NLPSym ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( * I ) , true ) ; } } } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue ( 0 , isPPC64 ? 8 : 4 , 0 ) ; else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 , 0 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 , 0 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> bool SITargetLowering :: requiresUniformRegister ( MachineFunction & MF , const Value * V ) const { if ( const CallInst * CI = dyn_cast < CallInst > ( V ) ) { if ( CI -> isInlineAsm ( ) ) { const SIRegisterInfo * SIRI = Subtarget -> getRegisterInfo ( ) ; TargetLowering :: AsmOperandInfoVector TargetConstraints = ParseConstraints ( MF . getDataLayout ( ) , Subtarget -> getRegisterInfo ( ) , * CI ) ; for ( auto & TC : TargetConstraints ) { if ( TC . Type == InlineAsm :: isOutput ) { ComputeConstraintToUse ( TC , SDValue ( ) ) ; unsigned AssignedReg ; const TargetRegisterClass * RC ; std :: tie ( AssignedReg , RC ) = getRegForInlineAsmConstraint ( SIRI , TC . ConstraintCode , TC . ConstraintVT ) ; if ( RC ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( AssignedReg != 0 && SIRI -> isSGPRReg ( MRI , AssignedReg ) ) return true ; else if ( SIRI -> isSGPRClass ( RC ) ) return true ; } } } } } SmallPtrSet < const Value * , 16 > Visited ; return hasCFUser ( V , Visited , Subtarget -> getWavefrontSize ( ) ) ; } </s>

Allows target to decide about the register class of the specific value that is live outside the defining block .


<s> bool X86AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( MI -> getInlineAsmDialect ( ) == InlineAsm :: AD_Intel ) { PrintIntelMemReference ( MI , OpNo , O ) ; return false ; } if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : break ; case 'H' : PrintMemReference ( MI , OpNo , O , "H" ) ; return false ; case 'P' : PrintMemReference ( MI , OpNo , O , "no-rip" ) ; return false ; } } PrintMemReference ( MI , OpNo , O , nullptr ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> unsigned SIInstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL , int * BytesAdded ) const { if ( ! FBB && Cond . empty ( ) ) { BuildMI ( & MBB , DL , get ( AMDGPU :: S_BRANCH ) ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded = 4 ; return 1 ; } assert ( TBB && Cond [ 0 ] . isImm ( ) ) ; unsigned Opcode = getBranchOpcode ( static_cast < BranchPredicate > ( Cond [ 0 ] . getImm ( ) ) ) ; if ( ! FBB ) { Cond [ 1 ] . isUndef ( ) ; MachineInstr * CondBr = BuildMI ( & MBB , DL , get ( Opcode ) ) . addMBB ( TBB ) ; MachineOperand & CondReg = CondBr -> getOperand ( 1 ) ; CondReg . setIsUndef ( Cond [ 1 ] . isUndef ( ) ) ; CondReg . setIsKill ( Cond [ 1 ] . isKill ( ) ) ; if ( BytesAdded ) * BytesAdded = 4 ; return 1 ; } assert ( TBB && FBB ) ; MachineInstr * CondBr = BuildMI ( & MBB , DL , get ( Opcode ) ) . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( AMDGPU :: S_BRANCH ) ) . addMBB ( FBB ) ; MachineOperand & CondReg = CondBr -> getOperand ( 1 ) ; CondReg . setIsUndef ( Cond [ 1 ] . isUndef ( ) ) ; CondReg . setIsKill ( Cond [ 1 ] . isKill ( ) ) ; if ( BytesAdded ) * BytesAdded = 8 ; return 2 ; } </s>

Insert branch code into the end of the specified MachineBasicBlock .


<s> virtual const TargetRegisterClass * getCFGStructurizerRegClass ( MVT VT ) const { assert ( ! "Unimplemented" ) ; return NULL ; } </s>

get the register class of the specified type to use in the CFGStructurizer


<s> static void query ( const MachineInstr & MI , AliasAnalysis & AA , bool & Read , bool & Write , bool & Effects , bool & StackPointer ) { assert ( ! MI . isTerminator ( ) ) ; if ( MI . isDebugInstr ( ) || MI . isPosition ( ) ) return ; if ( MI . mayLoad ( ) && ! MI . isDereferenceableInvariantLoad ( & AA ) ) Read = true ; if ( MI . mayStore ( ) ) { Write = true ; } else if ( MI . hasOrderedMemoryRef ( ) ) { switch ( MI . getOpcode ( ) ) { case WebAssembly :: DIV_S_I32 : case WebAssembly :: DIV_S_I64 : case WebAssembly :: REM_S_I32 : case WebAssembly :: REM_S_I64 : case WebAssembly :: DIV_U_I32 : case WebAssembly :: DIV_U_I64 : case WebAssembly :: REM_U_I32 : case WebAssembly :: REM_U_I64 : case WebAssembly :: I32_TRUNC_S_F32 : case WebAssembly :: I64_TRUNC_S_F32 : case WebAssembly :: I32_TRUNC_S_F64 : case WebAssembly :: I64_TRUNC_S_F64 : case WebAssembly :: I32_TRUNC_U_F32 : case WebAssembly :: I64_TRUNC_U_F32 : case WebAssembly :: I32_TRUNC_U_F64 : case WebAssembly :: I64_TRUNC_U_F64 : break ; default : if ( ! MI . isCall ( ) ) { Write = true ; Effects = true ; } break ; } } if ( MI . hasUnmodeledSideEffects ( ) ) { switch ( MI . getOpcode ( ) ) { case WebAssembly :: DIV_S_I32 : case WebAssembly :: DIV_S_I64 : case WebAssembly :: REM_S_I32 : case WebAssembly :: REM_S_I64 : case WebAssembly :: DIV_U_I32 : case WebAssembly :: DIV_U_I64 : case WebAssembly :: REM_U_I32 : case WebAssembly :: REM_U_I64 : case WebAssembly :: I32_TRUNC_S_F32 : case WebAssembly :: I64_TRUNC_S_F32 : case WebAssembly :: I32_TRUNC_S_F64 : case WebAssembly :: I64_TRUNC_S_F64 : case WebAssembly :: I32_TRUNC_U_F32 : case WebAssembly :: I64_TRUNC_U_F32 : case WebAssembly :: I32_TRUNC_U_F64 : case WebAssembly :: I64_TRUNC_U_F64 : break ; default : Effects = true ; break ; } } if ( MI . getOpcode ( ) == WebAssembly :: GLOBAL_SET_I32 && strcmp ( MI . getOperand ( 0 ) . getSymbolName ( ) , "__stack_pointer" ) == 0 ) StackPointer = true ; if ( MI . isCall ( ) ) { unsigned CalleeOpNo = WebAssembly :: getCalleeOpNo ( MI . getOpcode ( ) ) ; queryCallee ( MI , CalleeOpNo , Read , Write , Effects , StackPointer ) ; } } </s>

Query a line of the assigned virtual register matrix directly .


"Do not know how to custom type legalize this operation!"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> const char * Z80TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( Z80ISD :: NodeType ) Opcode ) { case Z80ISD :: FIRST_NUMBER : break ; case Z80ISD :: RET_FLAG : return "Z80ISD::RET_FLAG" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> const P2TargetMachine & getTargetMachine ( ) { return static_cast < const P2TargetMachine & > ( TM ) ; } </s>

Return the target machine ( if available ) .


<s> bool AMDGPUTargetMachine :: isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const { return AMDGPU :: isFlatGlobalAddrSpace ( SrcAS ) && AMDGPU :: isFlatGlobalAddrSpace ( DestAS ) ; } </s>

Returns true if a cast between SrcAS and DestAS is a noop .

AMDGPU AMDGPU AMDGPU::isFlatGlobalAddrSpace AMDGPU::isFlatGlobalAddrSpace


<s> SDValue Cpu0TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; unsigned opc = N -> getOpcode ( ) ; switch ( opc ) { default : break ; case ISD :: SDIVREM : case ISD :: UDIVREM : return PerformDivRemCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s>
void
TPCDAGToDAGISel
::
Select
(
SDNode
*
N
)
{
LLVM_DEBUG
(
errs
(
)
<<
"Selecting: "
)
;
LLVM_DEBUG
(
N
->
dump
(
CurDAG
)
)
;
LLVM_DEBUG
(
errs
(
)
<<
"\n"
)
;
if
(
N
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
errs
(
)
<<
"== "
;
N
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
N
->
setNodeId
(
1
)
;
return
;
}
SelectCode
(
N
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> virtual bool isProfitableToUnpredicate ( MachineBasicBlock & TMBB , MachineBasicBlock & FMBB ) const { return false ; } </s>

Return true if it 's profitable to unpredicate one side of a 'diamond ' , i.e .


<s> static void arm_option_params_internal ( void ) { if ( TARGET_THUMB1 ) { targetm . min_anchor_offset = 0 ; targetm . max_anchor_offset = 127 ; } else if ( TARGET_THUMB2 ) { targetm . min_anchor_offset = - 248 ; targetm . max_anchor_offset = 4095 ; } else { targetm . min_anchor_offset = TARGET_MIN_ANCHOR_OFFSET ; targetm . max_anchor_offset = TARGET_MAX_ANCHOR_OFFSET ; } max_insns_skipped = optimize_size ? 4 : current_tune -> max_insns_skipped ; if ( TARGET_THUMB2 ) max_insns_skipped = MIN ( max_insns_skipped , MAX_INSN_PER_IT_BLOCK ) ; } </s>

Recompute the global settings depending on target attribute options .


<s> int AArch64TTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args , const Instruction * CxtI ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; int Cost = 0 ; if ( isWideningInstruction ( Ty , Opcode , Args ) ) Cost += ST -> getWideningBaseCost ( ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return Cost + BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: SDIV : if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue && Opd2PropInfo == TargetTransformInfo :: OP_PowerOf2 ) { Cost += getArithmeticInstrCost ( Instruction :: Add , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Sub , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Select , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: AShr , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return Cost ; } LLVM_FALLTHROUGH ; case ISD :: UDIV : if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue ) { auto VT = TLI -> getValueType ( DL , Ty ) ; if ( TLI -> isOperationLegalOrCustom ( ISD :: MULHU , VT ) ) { int MulCost = getArithmeticInstrCost ( Instruction :: Mul , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; int AddCost = getArithmeticInstrCost ( Instruction :: Add , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; int ShrCost = getArithmeticInstrCost ( Instruction :: AShr , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return MulCost * 2 + AddCost * 2 + ShrCost * 2 + 1 ; } } Cost += BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( Ty -> isVectorTy ( ) ) { Cost += getArithmeticInstrCost ( Instruction :: ExtractElement , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += getArithmeticInstrCost ( Instruction :: InsertElement , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += Cost ; } return Cost ; case ISD :: ADD : case ISD :: MUL : case ISD :: XOR : case ISD :: OR : case ISD :: AND : return ( Cost + 1 ) * LT . first ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> bool PPCInstrInfo :: isPredicable ( MachineInstr * MI ) const { unsigned OpC = MI -> getOpcode ( ) ; switch ( OpC ) { default : return false ; case PPC :: B : case PPC :: BLR : case PPC :: BCTR : case PPC :: BCTR8 : case PPC :: BCTRL : case PPC :: BCTRL8 : return true ; } } </s>

Return true if the specified instruction can be predicated .

PowerPC PPC PPC::B PPC::BLR PPC::BCTR PPC::BCTR8 PPC::BCTRL PPC::BCTRL8


<s> static std :: unique_ptr < MipsOperand > CreateReg ( unsigned Index , StringRef Str , RegKind RegKind , const MCRegisterInfo * RegInfo , SMLoc S , SMLoc E , MipsAsmParser & Parser , unsigned RealRegister = Mips :: NoRegister ) { auto Op = std :: make_unique < MipsOperand > ( k_RegisterIndex , Parser ) ; Op -> RegIdx . Index = Index ; Op -> RegIdx . RegInfo = RegInfo ; Op -> RegIdx . Kind = RegKind ; Op -> RegIdx . Tok . Data = Str . data ( ) ; Op -> RegIdx . Tok . Length = Str . size ( ) ; Op -> RegIdx . RealRegister = RealRegister ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> MCELFStreamer & PatmosTargetELFStreamer :: getStreamer ( ) { return static_cast < MCELFStreamer & > ( * Streamer ) ; } </s>

Return the output streamer for the assembler .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createELFObjectWriter ( new X86ELFObjectWriter ( true , OSType , ELF :: EM_X86_64 , true ) , OS , true ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static bool h8300_short_move_mem_p ( rtx op , enum rtx_code inc_code ) { rtx addr ; unsigned int size ; if ( GET_CODE ( op ) != MEM ) return false ; addr = XEXP ( op , 0 ) ; size = GET_MODE_SIZE ( GET_MODE ( op ) ) ; if ( size != 1 && size != 2 ) return false ; return ( GET_CODE ( addr ) == inc_code || ( GET_CODE ( addr ) == PLUS && GET_CODE ( XEXP ( addr , 0 ) ) == REG && h8300_displacement_length ( addr , size ) == 2 ) ) ; } </s>

Subroutine of h8300_move_length . Return true if OP is 1- or 2-byte memory reference and either ( 1 ) it has the form @ ( d:16 , Rn ) or ( 2 ) its address has the code given by INC_CODE .


<s> static bool single_def_chain_p ( rtx reg ) { df_ref ref = DF_REG_DEF_CHAIN ( REGNO ( reg ) ) ; if ( ! ref ) return false ; return DF_REF_NEXT_REG ( ref ) == nullptr ; } </s>

Return true if the register REG is defined in a single DEF chain . If it is defined in more than one DEF chains , we may not be able to convert it in all chains .


<s> int m32c_mode_dependent_address ( rtx addr ) { if ( GET_CODE ( addr ) == POST_INC || GET_CODE ( addr ) == PRE_DEC ) return 1 ; return 0 ; } </s>


<s> enum rtx_code ix86_reverse_condition ( enum rtx_code code , machine_mode mode ) { return ( mode == CCFPmode ? reverse_condition_maybe_unordered ( code ) : reverse_condition ( code ) ) ; } </s>


<s> void ARMPassConfig :: addIRPasses ( ) { if ( getARMSubtarget ( ) . isTargetNaCl ( ) ) { addPass ( createInsertDivideCheckPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> insn_code function_expander :: direct_optab_handler ( optab op , unsigned int suffix_i ) { return :: direct_optab_handler ( op , vector_mode ( suffix_i ) ) ; } </s>

Return the handler of direct optab OP for type suffix SUFFIX_I .


<s> bool AArch64TargetLowering :: useLoadStackGuardNode ( ) const { if ( ! Subtarget -> isTargetAndroid ( ) ) return true ; return TargetLowering :: useLoadStackGuardNode ( ) ; } </s>

If this function returns true , SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic : :stackprotector .


<s> bool SIInstrInfo :: hasUnwantedEffectsWhenEXECEmpty ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( MI . mayStore ( ) && isSMRD ( MI ) ) return true ; if ( Opcode == AMDGPU :: S_SENDMSG || Opcode == AMDGPU :: S_SENDMSGHALT || Opcode == AMDGPU :: EXP || Opcode == AMDGPU :: EXP_DONE || Opcode == AMDGPU :: DS_ORDERED_COUNT ) return true ; if ( MI . isCall ( ) || MI . isInlineAsm ( ) ) return true ; if ( Opcode == AMDGPU :: V_READFIRSTLANE_B32 || Opcode == AMDGPU :: V_READLANE_B32 ) return true ; return false ; } </s>

Whether we must prevent this instruction from executing with EXEC = 0 .


<s> virtual const NVPTXRegisterInfo * getRegisterInfo ( ) const { return & ( InstrInfo . getRegisterInfo ( ) ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
unsigned
AArch64TTIImpl
::
getGatherScatterOpCost
(
unsigned
Opcode
,
Type
*
DataTy
,
const
Value
*
Ptr
,
bool
VariableMask
,
Align
Alignment
,
TTI
::
TargetCostKind
CostKind
,
const
Instruction
*
I
)
{
if
(
!
isa
<
ScalableVectorType
>
(
DataTy
)
)
return
BaseT
::
getGatherScatterOpCost
(
Opcode
,
DataTy
,
Ptr
,
VariableMask
,
Alignment
,
CostKind
,
I
)
;
auto
*
VT
=
cast
<
VectorType
>
(
DataTy
)
;
auto
LT
=
TLI
->
getTypeLegalizationCost
(
DL
,
DataTy
)
;
ElementCount
LegalVF
=
LT
.
second
.
getVectorElementCount
(
)
;
Optional
<
unsigned
>
MaxNumVScale
=
getMaxVScale
(
)
;
assert
(
MaxNumVScale
&&
"Expected valid max vscale value"
)
;
unsigned
MemOpCost
=
getMemoryOpCost
(
Opcode
,
VT
->
getElementType
(
)
,
Alignment
,
0
,
CostKind
,
I
)
;
unsigned
MaxNumElementsPerGather
=
MaxNumVScale
.
getValue
(
)
*
LegalVF
.
getKnownMinValue
(
)
;
return
LT
.
first
*
MaxNumElementsPerGather
*
MemOpCost
;
}
</s>

Calculate the cost of Gather / Scatter operation .


<s>
MachineInstr
*
PPCInstrInfo
::
commuteInstruction
(
MachineInstr
*
MI
,
bool
NewMI
)
const
{
MachineFunction
&
MF
=
*
MI
->
getParent
(
)
->
getParent
(
)
;
if
(
MI
->
getOpcode
(
)
!=
PPC
::
RLWIMI
&&
MI
->
getOpcode
(
)
!=
PPC
::
RLWIMIo
)
return
TargetInstrInfo
::
commuteInstruction
(
MI
,
NewMI
)
;
if
(
MI
->
getOperand
(
3
)
.
getImm
(
)
!=
0
)
return
0
;
unsigned
Reg0
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
unsigned
Reg1
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
unsigned
Reg2
=
MI
->
getOperand
(
2
)
.
getReg
(
)
;
bool
Reg1IsKill
=
MI
->
getOperand
(
1
)
.
isKill
(
)
;
bool
Reg2IsKill
=
MI
->
getOperand
(
2
)
.
isKill
(
)
;
bool
ChangeReg0
=
false
;
if
(
Reg0
==
Reg1
)
{
assert
(
MI
->
getDesc
(
)
.
getOperandConstraint
(
0
,
MCOI
::
TIED_TO
)
&&
"Expecting a two-address instruction!"
)
;
Reg2IsKill
=
false
;
ChangeReg0
=
true
;
}
unsigned
MB
=
MI
->
getOperand
(
4
)
.
getImm
(
)
;
unsigned
ME
=
MI
->
getOperand
(
5
)
.
getImm
(
)
;
if
(
NewMI
)
{
unsigned
Reg0
=
ChangeReg0
Reg2
:
MI
->
getOperand
(
0
)
.
getReg
(
)
;
bool
Reg0IsDead
=
MI
->
getOperand
(
0
)
.
isDead
(
)
;
return
BuildMI
(
MF
,
MI
->
getDebugLoc
(
)
,
MI
->
getDesc
(
)
)
.
addReg
(
Reg0
,
RegState
::
Define
|
getDeadRegState
(
Reg0IsDead
)
)
.
addReg
(
Reg2
,
getKillRegState
(
Reg2IsKill
)
)
.
addReg
(
Reg1
,
getKillRegState
(
Reg1IsKill
)
)
.
addImm
(
(
ME
+
1
)
&
31
)
.
addImm
(
(
MB
1
)
&
31
)
;
}
if
(
ChangeReg0
)
MI
->
getOperand
(
0
)
.
setReg
(
Reg2
)
;
MI
->
getOperand
(
2
)
.
setReg
(
Reg1
)
;
MI
->
getOperand
(
1
)
.
setReg
(
Reg2
)
;
MI
->
getOperand
(
2
)
.
setIsKill
(
Reg1IsKill
)
;
MI
->
getOperand
(
1
)
.
setIsKill
(
Reg2IsKill
)
;
MI
->
getOperand
(
4
)
.
setImm
(
(
ME
+
1
)
&
31
)
;
MI
->
getOperand
(
5
)
.
setImm
(
(
MB
1
)
&
31
)
;
return
MI
;
}
</s>

This method commutes the operands of the given machine instruction MI .


<s> inline bool function_call_info :: function_returns_void_p ( ) { return TREE_TYPE ( TREE_TYPE ( fndecl ) ) == void_type_node ; } </s>

Return true if the function has no return value .


"Unexpected instruction for custom inserter!"

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> bool AMDGPULowerKernelCalls :: runOnModule ( Module & M ) { bool Changed = false ; for ( auto & F : M ) { if ( CallingConv :: AMDGPU_KERNEL != F . getCallingConv ( ) ) continue ; Function * FBody = NULL ; for ( Function :: user_iterator UI = F . user_begin ( ) , UE = F . user_end ( ) ; UI != UE ; ) { CallInst * CI = dyn_cast < CallInst > ( * UI ++ ) ; if ( ! CI ) continue ; if ( ! FBody ) FBody = cloneKernel ( F ) ; CI -> setCalledFunction ( FBody ) ; CI -> setCallingConv ( CallingConv :: C ) ; Changed = true ; } } return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> void X86InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , Register DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Alignment = std :: max < uint32_t > ( TRI -> getSpillSize ( * RC ) , 16 ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlign ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , Subtarget ) ; auto mi = BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , get ( Opc ) , DestReg ) ; addFrameReference ( mi , FrameIdx ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s>
void
XCoreRegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected"
)
;
MachineInstr
&
MI
=
*
II
;
MachineOperand
&
FrameOp
=
MI
.
getOperand
(
FIOperandNum
)
;
int
FrameIndex
=
FrameOp
.
getIndex
(
)
;
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
const
XCoreInstrInfo
&
TII
=
*
static_cast
<
const
XCoreInstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
const
XCoreFrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
int
Offset
=
MF
.
getFrameInfo
(
)
.
getObjectOffset
(
FrameIndex
)
;
int
StackSize
=
MF
.
getFrameInfo
(
)
.
getStackSize
(
)
;
DEBUG
(
errs
(
)
<<
"\nFunction         : "
<<
MF
.
getName
(
)
<<
"\n"
)
;
DEBUG
(
errs
(
)
<<
"<--------->\n"
)
;
DEBUG
(
MI
.
print
(
errs
(
)
)
)
;
DEBUG
(
errs
(
)
<<
"FrameIndex         : "
<<
FrameIndex
<<
"\n"
)
;
DEBUG
(
errs
(
)
<<
"FrameOffset        : "
<<
Offset
<<
"\n"
)
;
DEBUG
(
errs
(
)
<<
"StackSize          : "
<<
StackSize
<<
"\n"
)
;
Offset
+=
StackSize
;
unsigned
FrameReg
=
getFrameRegister
(
MF
)
;
if
(
MI
.
isDebugValue
(
)
)
{
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
)
;
return
;
}
Offset
+=
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
0
)
;
assert
(
Offset
%
4
==
0
&&
"Misaligned stack offset"
)
;
DEBUG
(
errs
(
)
<<
"Offset             : "
<<
Offset
<<
"\n"
<<
"<--------->\n"
)
;
Offset
/=
4
;
unsigned
Reg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
assert
(
XCore
::
GRRegsRegClass
.
contains
(
Reg
)
&&
"Unexpected register operand"
)
;
if
(
TFI
->
hasFP
(
MF
)
)
{
if
(
isImmUs
(
Offset
)
)
InsertFPImmInst
(
II
,
TII
,
Reg
,
FrameReg
,
Offset
)
;
else
InsertFPConstInst
(
II
,
TII
,
Reg
,
FrameReg
,
Offset
,
RS
)
;
}
else
{
if
(
isImmU16
(
Offset
)
)
InsertSPImmInst
(
II
,
TII
,
Reg
,
Offset
)
;
else
InsertSPConstInst
(
II
,
TII
,
Reg
,
Offset
,
RS
)
;
}
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
MBB
.
erase
(
II
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .

XCore
XCore
0
"Unexpected"
XCore
XCore
XCore
"\nFunction         : "
"\n"
"<--------->\n"
"FrameIndex         : "
"\n"
"FrameOffset        : "
"\n"
"StackSize          : "
"\n"
1
1
1
0
4
0
"Misaligned stack offset"
"Offset             : "
"\n"
"<--------->\n"
4
0
XCore::GRRegsRegClass
"Unexpected register operand"


<s> bool MipsDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & TM . getSubtarget < MipsSubtarget > ( ) ; bool Ret = SelectionDAGISel :: runOnMachineFunction ( MF ) ; processFunctionAfterISel ( MF ) ; return Ret ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool AArch64FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( MF . hasEHFunclets ( ) ) return true ; if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) return true ; if ( MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || RegInfo -> hasStackRealignment ( MF ) ) return true ; if ( ! MFI . isMaxCallFrameSizeComputed ( ) || MFI . getMaxCallFrameSize ( ) > DefaultSafeSPDisplacement ) return true ; return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void aarch64_split_128bit_move ( rtx dst , rtx src ) { rtx dst_lo , dst_hi ; rtx src_lo , src_hi ; machine_mode mode = GET_MODE ( dst ) ; gcc_assert ( mode == TImode || mode == TFmode ) ; gcc_assert ( ! ( side_effects_p ( src ) || side_effects_p ( dst ) ) ) ; gcc_assert ( mode == GET_MODE ( src ) || GET_MODE ( src ) == VOIDmode ) ; if ( REG_P ( dst ) && REG_P ( src ) ) { int src_regno = REGNO ( src ) ; int dst_regno = REGNO ( dst ) ; if ( FP_REGNUM_P ( dst_regno ) && GP_REGNUM_P ( src_regno ) ) { src_lo = gen_lowpart ( word_mode , src ) ; src_hi = gen_highpart ( word_mode , src ) ; emit_insn ( gen_aarch64_movlow_di ( mode , dst , src_lo ) ) ; emit_insn ( gen_aarch64_movhigh_di ( mode , dst , src_hi ) ) ; return ; } else if ( GP_REGNUM_P ( dst_regno ) && FP_REGNUM_P ( src_regno ) ) { dst_lo = gen_lowpart ( word_mode , dst ) ; dst_hi = gen_highpart ( word_mode , dst ) ; emit_insn ( gen_aarch64_movdi_low ( mode , dst_lo , src ) ) ; emit_insn ( gen_aarch64_movdi_high ( mode , dst_hi , src ) ) ; return ; } } dst_lo = gen_lowpart ( word_mode , dst ) ; dst_hi = gen_highpart ( word_mode , dst ) ; src_lo = gen_lowpart ( word_mode , src ) ; src_hi = gen_highpart_mode ( word_mode , mode , src ) ; if ( reg_overlap_mentioned_p ( dst_lo , src_hi ) ) { aarch64_emit_move ( dst_hi , src_hi ) ; aarch64_emit_move ( dst_lo , src_lo ) ; } else { aarch64_emit_move ( dst_lo , src_lo ) ; aarch64_emit_move ( dst_hi , src_hi ) ; } } </s>

Split a 128-bit move operation into two 64-bit move operations , taking care to handle partial overlap of register to register copies . Special cases are needed when moving between GP regs and FP regs . SRC can be a register , constant or memory ; DST a register or memory . If either operand is memory it must not have any side effects .


"accessing thread-local storage is not currently supported "

Return TRUE if X contains any TLS symbol references .


<s>
bool
AMDGPULegalizerInfo
::
legalizeCustom
(
LegalizerHelper
&
Helper
,
MachineInstr
&
MI
)
const
{
MachineIRBuilder
&
B
=
Helper
.
MIRBuilder
;
MachineRegisterInfo
&
MRI
=
*
B
.
getMRI
(
)
;
GISelChangeObserver
&
Observer
=
Helper
.
Observer
;
switch
(
MI
.
getOpcode
(
)
)
{
case
TargetOpcode
::
G_ADDRSPACE_CAST
:
return
legalizeAddrSpaceCast
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FRINT
:
return
legalizeFrint
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FCEIL
:
return
legalizeFceil
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_INTRINSIC_TRUNC
:
return
legalizeIntrinsicTrunc
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_SITOFP
:
return
legalizeITOFP
(
MI
,
MRI
,
B
,
true
)
;
case
TargetOpcode
::
G_UITOFP
:
return
legalizeITOFP
(
MI
,
MRI
,
B
,
false
)
;
case
TargetOpcode
::
G_FPTOSI
:
return
legalizeFPTOI
(
MI
,
MRI
,
B
,
true
)
;
case
TargetOpcode
::
G_FPTOUI
:
return
legalizeFPTOI
(
MI
,
MRI
,
B
,
false
)
;
case
TargetOpcode
::
G_FMINNUM
:
case
TargetOpcode
::
G_FMAXNUM
:
case
TargetOpcode
::
G_FMINNUM_IEEE
:
case
TargetOpcode
::
G_FMAXNUM_IEEE
:
return
legalizeMinNumMaxNum
(
Helper
,
MI
)
;
case
TargetOpcode
::
G_EXTRACT_VECTOR_ELT
:
return
legalizeExtractVectorElt
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_INSERT_VECTOR_ELT
:
return
legalizeInsertVectorElt
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_SHUFFLE_VECTOR
:
return
legalizeShuffleVector
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FSIN
:
case
TargetOpcode
::
G_FCOS
:
return
legalizeSinCos
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_GLOBAL_VALUE
:
return
legalizeGlobalValue
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_LOAD
:
return
legalizeLoad
(
MI
,
MRI
,
B
,
Observer
)
;
case
TargetOpcode
::
G_FMAD
:
return
legalizeFMad
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FDIV
:
return
legalizeFDIV
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_UDIV
:
case
TargetOpcode
::
G_UREM
:
return
legalizeUDIV_UREM
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_SDIV
:
case
TargetOpcode
::
G_SREM
:
return
legalizeSDIV_SREM
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_ATOMIC_CMPXCHG
:
return
legalizeAtomicCmpXChg
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FLOG
:
return
legalizeFlog
(
MI
,
B
,
numbers
::
ln2f
)
;
case
TargetOpcode
::
G_FLOG10
:
return
legalizeFlog
(
MI
,
B
,
numbers
::
ln2f
/
numbers
::
ln10f
)
;
case
TargetOpcode
::
G_FEXP
:
return
legalizeFExp
(
MI
,
B
)
;
case
TargetOpcode
::
G_FPOW
:
return
legalizeFPow
(
MI
,
B
)
;
case
TargetOpcode
::
G_FFLOOR
:
return
legalizeFFloor
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_BUILD_VECTOR
:
return
legalizeBuildVector
(
MI
,
MRI
,
B
)
;
default
:
return
false
;
}
llvm_unreachable
(
"expected switch to return"
)
;
}
</s>

Called for instructions with the Custom LegalizationAction .

AMDGPU
AMDGPU
SI
SI
SI
SI
"expected switch to return"


<s> bool ARMBaseInstrInfo :: isPredicable ( const MachineInstr & MI ) const { if ( ! MI . isPredicable ( ) ) return false ; if ( MI . isBundle ( ) ) return false ; if ( ! isEligibleForITBlock ( & MI ) ) return false ; const ARMFunctionInfo * AFI = MI . getParent ( ) -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; if ( AFI -> isThumb2Function ( ) ) { if ( getSubtarget ( ) . restrictIT ( ) ) return isV8EligibleForIT ( & MI ) ; } else { if ( ( MI . getDesc ( ) . TSFlags & ARMII :: DomainMask ) == ARMII :: DomainNEON ) return false ; } return true ; } </s>

Return true if the specified instruction can be predicated .

ARM ARM ARM ARM ARMII::DomainMask ARMII::DomainNEON


<s> MachineBasicBlock * SITargetLowering :: EmitInstrWithCustomInserter ( MachineInstr & MI , MachineBasicBlock * BB ) const { switch ( MI . getOpcode ( ) ) { case AMDGPU :: SI_INIT_M0 : { const SIInstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; BuildMI ( * BB , MI . getIterator ( ) , MI . getDebugLoc ( ) , TII -> get ( AMDGPU :: S_MOV_B32 ) , AMDGPU :: M0 ) . addOperand ( MI . getOperand ( 0 ) ) ; MI . eraseFromParent ( ) ; break ; } case AMDGPU :: BRANCH : return BB ; case AMDGPU :: GET_GROUPSTATICSIZE : { const SIInstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; MachineFunction * MF = BB -> getParent ( ) ; SIMachineFunctionInfo * MFI = MF -> getInfo < SIMachineFunctionInfo > ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; BuildMI ( * BB , MI , DL , TII -> get ( AMDGPU :: S_MOVK_I32 ) ) . addOperand ( MI . getOperand ( 0 ) ) . addImm ( MFI -> LDSSize ) ; MI . eraseFromParent ( ) ; return BB ; } default : return AMDGPUTargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; } return BB ; } </s>


<s> void rs6000_output_function_entry ( FILE * file , const char * fname ) { if ( fname [ 0 ] != '.' ) { switch ( DEFAULT_ABI ) { default : gcc_unreachable ( ) ; case ABI_AIX : if ( DOT_SYMBOLS ) putc ( '.' , file ) ; else ASM_OUTPUT_INTERNAL_LABEL_PREFIX ( file , "L." ) ; break ; case ABI_V4 : case ABI_DARWIN : break ; } } if ( TARGET_AIX ) RS6000_OUTPUT_BASENAME ( file , fname ) ; else assemble_name ( file , fname ) ; } </s>


Targets may add passes immediately before machine code is emitted in this callback .


<s>
MachineInstr
*
LanaiInstrInfo
::
optimizeSelect
(
MachineInstr
&
MI
,
SmallPtrSetImpl
<
MachineInstr
*
>
&
SeenMIs
,
bool
)
const
{
assert
(
MI
.
getOpcode
(
)
==
Lanai
::
SELECT
&&
"unknown select instruction"
)
;
MachineRegisterInfo
&
MRI
=
MI
.
getParent
(
)
->
getParent
(
)
->
getRegInfo
(
)
;
MachineInstr
*
DefMI
=
canFoldIntoSelect
(
MI
.
getOperand
(
1
)
.
getReg
(
)
,
MRI
)
;
bool
Invert
=
!
DefMI
;
if
(
!
DefMI
)
DefMI
=
canFoldIntoSelect
(
MI
.
getOperand
(
2
)
.
getReg
(
)
,
MRI
)
;
if
(
!
DefMI
)
return
nullptr
;
MachineOperand
FalseReg
=
MI
.
getOperand
(
Invert
1
:
2
)
;
Register
DestReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
const
TargetRegisterClass
*
PreviousClass
=
MRI
.
getRegClass
(
FalseReg
.
getReg
(
)
)
;
if
(
!
MRI
.
constrainRegClass
(
DestReg
,
PreviousClass
)
)
return
nullptr
;
MachineInstrBuilder
NewMI
=
BuildMI
(
*
MI
.
getParent
(
)
,
MI
,
MI
.
getDebugLoc
(
)
,
DefMI
->
getDesc
(
)
,
DestReg
)
;
const
MCInstrDesc
&
DefDesc
=
DefMI
->
getDesc
(
)
;
for
(
unsigned
i
=
1
,
e
=
DefDesc
.
getNumOperands
(
)
;
i
!=
e
&&
!
DefDesc
.
OpInfo
[
i
]
.
isPredicate
(
)
;
++
i
)
NewMI
.
add
(
DefMI
->
getOperand
(
i
)
)
;
unsigned
CondCode
=
MI
.
getOperand
(
3
)
.
getImm
(
)
;
if
(
Invert
)
NewMI
.
addImm
(
getOppositeCondition
(
LPCC
::
CondCode
(
CondCode
)
)
)
;
else
NewMI
.
addImm
(
CondCode
)
;
NewMI
.
copyImplicitOps
(
MI
)
;
FalseReg
.
setImplicit
(
)
;
NewMI
.
add
(
FalseReg
)
;
NewMI
->
tieOperands
(
0
,
NewMI
->
getNumOperands
(
)
1
)
;
SeenMIs
.
insert
(
NewMI
)
;
SeenMIs
.
erase
(
DefMI
)
;
if
(
DefMI
->
getParent
(
)
!=
MI
.
getParent
(
)
)
NewMI
->
clearKillInfo
(
)
;
DefMI
->
eraseFromParent
(
)
;
return
NewMI
;
}
</s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


<s> static opt_scalar_float_mode riscv_floatn_mode ( int n , bool extended ) { if ( ! extended && n == 16 ) return HFmode ; return default_floatn_mode ( n , extended ) ; } </s>


<s> static void winnt_d_os_builtins ( void ) { d_add_builtin_version ( "Windows" ) ; d_add_builtin_version ( "MinGW" ) ; if ( TARGET_64BIT && ix86_abi == MS_ABI ) d_add_builtin_version ( "Win64" ) ; else if ( ! TARGET_64BIT ) d_add_builtin_version ( "Win32" ) ; d_add_builtin_version ( "CRuntime_Microsoft" ) ; } </s>

Implement TARGET_D_OS_VERSIONS for Windows targets .


<s> int X86TTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; unsigned ImmIdx = ~ 0U ; switch ( Opcode ) { default : return TTI :: TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: Store : ImmIdx = 0 ; break ; case Instruction :: ICmp : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 ) { uint64_t ImmVal = Imm . getZExtValue ( ) ; if ( ImmVal == 0x100000000ULL || ImmVal == 0xffffffff ) return TTI :: TCC_Free ; } ImmIdx = 1 ; break ; case Instruction :: And : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 && isUInt < 32 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; ImmIdx = 1 ; break ; case Instruction :: Add : case Instruction :: Sub : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 && Imm . getZExtValue ( ) == 0x80000000 ) return TTI :: TCC_Free ; ImmIdx = 1 ; break ; case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : return TTI :: TCC_Free ; case Instruction :: Mul : case Instruction :: Or : case Instruction :: Xor : ImmIdx = 1 ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == 1 ) return TTI :: TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: IntToPtr : case Instruction :: PtrToInt : case Instruction :: BitCast : case Instruction :: PHI : case Instruction :: Call : case Instruction :: Select : case Instruction :: Ret : case Instruction :: Load : break ; } if ( Idx == ImmIdx ) { int NumConstants = divideCeil ( BitSize , 64 ) ; int Cost = X86TTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ; return ( Cost <= NumConstants * TTI :: TCC_Basic ) ? static_cast < int > ( TTI :: TCC_Free ) : Cost ; } return X86TTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> static rtx sparc_builtin_saveregs ( void ) { int first_reg = crtl -> args . info . words ; rtx address ; int regno ; for ( regno = first_reg ; regno < SPARC_INT_ARG_MAX ; regno ++ ) emit_move_insn ( gen_rtx_MEM ( word_mode , gen_rtx_PLUS ( Pmode , frame_pointer_rtx , GEN_INT ( FIRST_PARM_OFFSET ( 0 ) + ( UNITS_PER_WORD * regno ) ) ) ) , gen_rtx_REG ( word_mode , SPARC_INCOMING_INT_ARG_FIRST + regno ) ) ; address = gen_rtx_PLUS ( Pmode , frame_pointer_rtx , GEN_INT ( FIRST_PARM_OFFSET ( 0 ) + UNITS_PER_WORD * first_reg ) ) ; return address ; } </s>

Do what is necessary for ` va_start ' . We look at the current function to determine if stdarg or varargs is used and return the address of the first unnamed parameter .


<s> void MipsInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << '$' << StringRef ( getRegisterName ( RegNo ) ) . lower ( ) ; } </s>


<s> rtx maybe_get_pool_constant ( rtx x ) { x = ix86_delegitimize_address ( XEXP ( x , 0 ) ) ; if ( GET_CODE ( x ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) ) return get_pool_constant ( x ) ; return NULL_RTX ; } </s>

X is an unchanging MEM . If it is a constant pool reference , return the constant pool rtx , else NULL .


<s>
virtual
const
char
*
getPassName
(
)
const
LLVM_OVERRIDE
{
return
"X86 Assembly / Object Emitter"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void HexagonMCELFStreamer :: EmitInstruction ( const MCInst & MCB , const MCSubtargetInfo & STI , bool ) { assert ( MCB . getOpcode ( ) == Hexagon :: BUNDLE ) ; assert ( HexagonMCInstrInfo :: bundleSize ( MCB ) <= HEXAGON_PACKET_SIZE ) ; assert ( HexagonMCInstrInfo :: bundleSize ( MCB ) > 0 ) ; bool Extended = false ; for ( auto & I : HexagonMCInstrInfo :: bundleInstructions ( MCB ) ) { MCInst * MCI = const_cast < MCInst * > ( I . getInst ( ) ) ; if ( Extended ) { if ( HexagonMCInstrInfo :: isDuplex ( * MCII , * MCI ) ) { MCInst * SubInst = const_cast < MCInst * > ( MCI -> getOperand ( 1 ) . getInst ( ) ) ; HexagonMCInstrInfo :: clampExtended ( * MCII , getContext ( ) , * SubInst ) ; } else { HexagonMCInstrInfo :: clampExtended ( * MCII , getContext ( ) , * MCI ) ; } Extended = false ; } else { Extended = HexagonMCInstrInfo :: isImmext ( * MCI ) ; } } for ( auto const & I : HexagonMCInstrInfo :: bundleInstructions ( MCB ) ) { MCInst * MCI = const_cast < MCInst * > ( I . getInst ( ) ) ; EmitSymbol ( * MCI ) ; } MCObjectStreamer :: EmitInstruction ( MCB , STI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .

Hexagon Hexagon Hexagon::BUNDLE Hexagon Hexagon 0 Hexagon Hexagon 1 Hexagon Hexagon Hexagon Hexagon


<s> void HexagonPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; addPass ( createAtomicExpandPass ( TM ) ) ; if ( ! NoOpt ) { if ( EnableCommGEP ) addPass ( createHexagonCommonGEP ( ) ) ; if ( EnableGenExtract ) addPass ( createHexagonGenExtract ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> BitVector X86RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( X86 :: RSP ) ; Reserved . set ( X86 :: ESP ) ; Reserved . set ( X86 :: SP ) ; Reserved . set ( X86 :: SPL ) ; Reserved . set ( X86 :: RIP ) ; Reserved . set ( X86 :: EIP ) ; Reserved . set ( X86 :: IP ) ; if ( hasFP ( MF ) ) { Reserved . set ( X86 :: RBP ) ; Reserved . set ( X86 :: EBP ) ; Reserved . set ( X86 :: BP ) ; Reserved . set ( X86 :: BPL ) ; } Reserved . set ( X86 :: ST0 ) ; Reserved . set ( X86 :: ST1 ) ; Reserved . set ( X86 :: ST2 ) ; Reserved . set ( X86 :: ST3 ) ; Reserved . set ( X86 :: ST4 ) ; Reserved . set ( X86 :: ST5 ) ; Reserved . set ( X86 :: ST6 ) ; Reserved . set ( X86 :: ST7 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void MipsRegisterInfo :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = ( MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc :: getUnknownLoc ( ) ) ; bool isPIC = ( MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ; adjustMipsStackFrame ( MF ) ; unsigned StackSize = MFI -> getStackSize ( ) ; if ( StackSize == 0 && ! MFI -> hasCalls ( ) ) return ; int FPOffset = MipsFI -> getFPStackOffset ( ) ; int RAOffset = MipsFI -> getRAStackOffset ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: NOREORDER ) ) ; if ( isPIC && Subtarget . isABI_O32 ( ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: CPLOAD ) ) . addReg ( getPICCallReg ( ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: NOMACRO ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDiu ) , Mips :: SP ) . addReg ( Mips :: SP ) . addImm ( - StackSize ) ; if ( MFI -> hasCalls ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: SW ) ) . addReg ( Mips :: RA ) . addImm ( RAOffset ) . addReg ( Mips :: SP ) ; } if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: SW ) ) . addReg ( Mips :: FP ) . addImm ( FPOffset ) . addReg ( Mips :: SP ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDu ) , Mips :: FP ) . addReg ( Mips :: SP ) . addReg ( Mips :: ZERO ) ; } if ( ( isPIC ) && ( MFI -> hasCalls ( ) ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: CPRESTORE ) ) . addImm ( MipsFI -> getGPStackOffset ( ) ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Mips Mips Mips Mips Mips Mips 0 Mips Mips Mips::NOREORDER Mips::CPLOAD Mips::NOMACRO Mips::ADDiu Mips::SP Mips::SP Mips::SW Mips::RA Mips::SP Mips::SW Mips::FP Mips::SP Mips::ADDu Mips::FP Mips::SP Mips::ZERO Mips::CPRESTORE Mips


<s> bool NVVMIntrRange :: runOnFunction ( Function & F ) { return runNVVMIntrRange ( F , SmVersion ) ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> SMLoc getStartLoc ( ) const { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> bool MipsTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; MipsCCState CCInfo ( CallConv , IsVarArg , MF , getTargetMachine ( ) , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_Mips ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s>
DecodeStatus
AMDGPUDisassembler
::
getInstruction
(
MCInst
&
MI
,
uint64_t
&
Size
,
ArrayRef
<
uint8_t
>
Bytes_
,
uint64_t
Address
,
raw_ostream
&
WS
,
raw_ostream
&
CS
)
const
{
CommentStream
=
&
CS
;
assert
(
AMDGPU
::
isVI
(
STI
)
&&
"Can disassemble only VI ISA."
)
;
const
unsigned
MaxInstBytesNum
=
(
std
::
min
)
(
(
size_t
)
8
,
Bytes_
.
size
(
)
)
;
Bytes
=
Bytes_
.
slice
(
0
,
MaxInstBytesNum
)
;
DecodeStatus
Res
=
MCDisassembler
::
Fail
;
do
{
if
(
Bytes
.
size
(
)
>=
8
)
{
const
uint64_t
QW
=
eatBytes
<
uint64_t
>
(
Bytes
)
;
Res
=
tryDecodeInst
(
DecoderTableDPP64
,
MI
,
QW
,
Address
)
;
if
(
Res
)
break
;
}
Bytes
=
Bytes_
.
slice
(
0
,
MaxInstBytesNum
)
;
if
(
Bytes
.
size
(
)
<
4
)
break
;
const
uint32_t
DW
=
eatBytes
<
uint32_t
>
(
Bytes
)
;
Res
=
tryDecodeInst
(
DecoderTableVI32
,
MI
,
DW
,
Address
)
;
if
(
Res
)
break
;
Res
=
tryDecodeInst
(
DecoderTableAMDGPU32
,
MI
,
DW
,
Address
)
;
if
(
Res
)
break
;
if
(
Bytes
.
size
(
)
<
4
)
break
;
const
uint64_t
QW
=
(
(
uint64_t
)
eatBytes
<
uint32_t
>
(
Bytes
)
<<
32
)
|
DW
;
Res
=
tryDecodeInst
(
DecoderTableVI64
,
MI
,
QW
,
Address
)
;
if
(
Res
)
break
;
Res
=
tryDecodeInst
(
DecoderTableAMDGPU64
,
MI
,
QW
,
Address
)
;
}
while
(
false
)
;
Size
=
Res
(
MaxInstBytesNum
Bytes
.
size
(
)
)
:
0
;
return
Res
;
}
</s>

Returns the disassembly of a single instruction .


<s>
bool
MipsAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
SmallVectorImpl
<
MCParsedAsmOperand
*
>
&
Operands
)
{
if
(
!
mnemonicIsValid
(
Name
,
0
)
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
NameLoc
,
"Unknown instruction"
)
;
}
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Name
,
NameLoc
)
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Mips
Mips
0
"Unknown instruction"
MipsOperand::CreateToken
"unexpected token in argument list"
"unexpected token in argument list"
"unexpected token in argument list"


"Slot for FPW register must be last in order to be found!"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> bool runOnMachineFunction ( MachineFunction & F ) { bool Changed = false ; if ( EnableDelJmp ) { MachineFunction :: iterator FJ = F . begin ( ) ; if ( FJ != F . end ( ) ) FJ ++ ; if ( FJ == F . end ( ) ) return Changed ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FJ != FE ; ++ FI , ++ FJ ) Changed |= runOnMachineBasicBlock ( * FI , * FJ ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool X86FrameInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; const TargetRegisterInfo * RI = TM . getRegisterInfo ( ) ; return ( DisableFramePointerElim ( MF ) || RI -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


"calling %qD with SSE calling convention without "

"this is a GCC bug that can be worked around by adding "

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . ) Return a number of integer regsiters advanced over .


<s>
void
RISCVAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
)
const
{
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
if
(
!
Value
)
return
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
Ctx
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
unsigned
FullSize
=
getSize
(
Fixup
.
getKind
(
)
)
;
unsigned
NumBytes
=
(
Info
.
TargetSize
+
7
)
/
8
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
FullSize
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> const DataLayout * getDataLayout ( ) const override { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> void HexagonRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOp , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; MachineBasicBlock & MB = * MI . getParent ( ) ; MachineFunction & MF = * MB . getParent ( ) ; auto & HST = MF . getSubtarget < HexagonSubtarget > ( ) ; auto & HII = * HST . getInstrInfo ( ) ; auto & HFI = * HST . getFrameLowering ( ) ; unsigned BP = 0 ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; int Offset = HFI . getFrameIndexReference ( MF , FI , BP ) ; int RealOffset = Offset + MI . getOperand ( FIOp + 1 ) . getImm ( ) ; bool IsKill = false ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case Hexagon :: PS_fia : MI . setDesc ( HII . get ( Hexagon :: A2_addi ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + 1 ) ; return ; case Hexagon :: PS_fi : MI . setDesc ( HII . get ( Hexagon :: A2_addi ) ) ; break ; } if ( ! HII . isValidOffset ( Opc , RealOffset , this ) ) { auto & MRI = MF . getRegInfo ( ) ; unsigned TmpR = MRI . createVirtualRegister ( & Hexagon :: IntRegsRegClass ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( MB , II , DL , HII . get ( Hexagon :: A2_addi ) , TmpR ) . addReg ( BP ) . addImm ( RealOffset ) ; BP = TmpR ; RealOffset = 0 ; IsKill = true ; } MI . getOperand ( FIOp ) . ChangeToRegister ( BP , false , false , IsKill ) ; MI . getOperand ( FIOp + 1 ) . ChangeToImmediate ( RealOffset ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool ok_for_simple_move_strict_operands ( rtx * operands , machine_mode mode ) { if ( visium_flags_exposed && gpc_reg_operand ( operands [ 0 ] , mode ) && ( gpc_reg_operand ( operands [ 1 ] , mode ) || ( mode == QImode && operands [ 1 ] == const0_rtx ) ) ) return false ; return true ; } </s>

Return true if the operands are valid for a simple move strict insn .


<s> BitVector SNESRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( SNES :: DB ) ; Reserved . set ( SNES :: DP ) ; Reserved . set ( SNES :: P ) ; Reserved . set ( SNES :: PC ) ; Reserved . set ( SNES :: PB ) ; Reserved . set ( SNES :: SP ) ; return Reserved ; } </s>

SNES SNES SNES::DB SNES::DP SNES::P SNES::PC SNES::PB SNES::SP


"SIInstrInfo::loadRegToStackSlot - Can't retrieve spilled VGPR!"

Load the specified register of the given register class from the specified stack frame index .


<s> unsigned XCoreInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { int Opcode = MI -> getOpcode ( ) ; if ( Opcode == XCore :: LDWFI ) { if ( ( MI -> getOperand ( 1 ) . isFI ( ) ) && ( MI -> getOperand ( 2 ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( 2 ) ) ) ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s>
StringRef
getPassName
(
)
const
override
{
return
"JVM Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static void v850_setup_incoming_varargs ( CUMULATIVE_ARGS * ca , enum machine_mode mode ATTRIBUTE_UNUSED , tree type ATTRIBUTE_UNUSED , int * pretend_arg_size ATTRIBUTE_UNUSED , int second_time ATTRIBUTE_UNUSED ) { ca -> anonymous_args = ( ! TARGET_GHS ? 1 : 0 ) ; } </s>

Worker function for TARGET_SETUP_INCOMING_VARARGS .


<s> unsigned SIInstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL , int * BytesAdded ) const { if ( ! FBB && Cond . empty ( ) ) { BuildMI ( & MBB , DL , get ( AMDGPU :: S_BRANCH ) ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded = 4 ; return 1 ; } assert ( TBB && Cond [ 0 ] . isImm ( ) ) ; unsigned Opcode = getBranchOpcode ( static_cast < BranchPredicate > ( Cond [ 0 ] . getImm ( ) ) ) ; if ( ! FBB ) { Cond [ 1 ] . isUndef ( ) ; MachineInstr * CondBr = BuildMI ( & MBB , DL , get ( Opcode ) ) . addMBB ( TBB ) ; preserveCondRegFlags ( CondBr -> getOperand ( 1 ) , Cond [ 1 ] ) ; if ( BytesAdded ) * BytesAdded = 4 ; return 1 ; } assert ( TBB && FBB ) ; MachineInstr * CondBr = BuildMI ( & MBB , DL , get ( Opcode ) ) . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( AMDGPU :: S_BRANCH ) ) . addMBB ( FBB ) ; MachineOperand & CondReg = CondBr -> getOperand ( 1 ) ; CondReg . setIsUndef ( Cond [ 1 ] . isUndef ( ) ) ; CondReg . setIsKill ( Cond [ 1 ] . isKill ( ) ) ; if ( BytesAdded ) * BytesAdded = 8 ; return 2 ; } </s>

Insert branch code into the end of the specified MachineBasicBlock .