<s>
void
HexagonAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
if
(
MI
->
isBundle
(
)
)
{
std
::
vector
<
MachineInstr
const
*
>
BundleMIs
;
const
MachineBasicBlock
*
MBB
=
MI
->
getParent
(
)
;
MachineBasicBlock
::
const_instr_iterator
MII
=
MI
;
++
MII
;
unsigned
int
IgnoreCount
=
0
;
while
(
MII
!=
MBB
->
end
(
)
&&
MII
->
isInsideBundle
(
)
)
{
const
MachineInstr
*
MInst
=
MII
;
if
(
MInst
->
getOpcode
(
)
==
TargetOpcode
::
DBG_VALUE
||
MInst
->
getOpcode
(
)
==
TargetOpcode
::
IMPLICIT_DEF
)
{
IgnoreCount
++
;
++
MII
;
continue
;
}
BundleMIs
.
push_back
(
MInst
)
;
++
MII
;
}
unsigned
Size
=
BundleMIs
.
size
(
)
;
assert
(
(
Size
+
IgnoreCount
)
==
MI
->
getBundleSize
(
)
&&
"Corrupt Bundle!"
)
;
for
(
unsigned
Index
=
0
;
Index
<
Size
;
Index
++
)
{
MCInst
MCI
;
HexagonLowerToMC
(
BundleMIs
[
Index
]
,
MCI
,
*
this
)
;
HexagonMCInstrInfo
::
AppendImplicitOperands
(
MCI
)
;
HexagonMCInstrInfo
::
setPacketBegin
(
MCI
,
Index
==
0
)
;
HexagonMCInstrInfo
::
setPacketEnd
(
MCI
,
Index
==
(
Size
1
)
)
;
EmitToStreamer
(
OutStreamer
,
MCI
)
;
}
}
else
{
MCInst
MCI
;
HexagonLowerToMC
(
MI
,
MCI
,
*
this
)
;
HexagonMCInstrInfo
::
AppendImplicitOperands
(
MCI
)
;
if
(
MI
->
getOpcode
(
)
==
Hexagon
::
ENDLOOP0
)
{
HexagonMCInstrInfo
::
setPacketBegin
(
MCI
,
true
)
;
HexagonMCInstrInfo
::
setPacketEnd
(
MCI
,
true
)
;
}
EmitToStreamer
(
OutStreamer
,
MCI
)
;
}
return
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .

Hexagon
Hexagon
0
"Corrupt Bundle!"
0
Hexagon
Hexagon
Hexagon
0
Hexagon
1
Hexagon
Hexagon
Hexagon::ENDLOOP0
Hexagon
Hexagon


<s> static rtx ix86_get_drap_rtx ( void ) { if ( ix86_force_drap || ( ( cfun -> machine -> outgoing_args_on_stack || crtl -> sp_is_clobbered_by_asm ) && ! ACCUMULATE_OUTGOING_ARGS ) ) crtl -> need_drap = true ; if ( stack_realign_drap ) { unsigned int regno = find_drap_reg ( ) ; rtx drap_vreg ; rtx arg_ptr ; rtx_insn * seq , * insn ; arg_ptr = gen_rtx_REG ( Pmode , regno ) ; crtl -> drap_reg = arg_ptr ; start_sequence ( ) ; drap_vreg = copy_to_reg ( arg_ptr ) ; seq = get_insns ( ) ; end_sequence ( ) ; insn = emit_insn_before ( seq , NEXT_INSN ( entry_of_function ( ) ) ) ; if ( ! optimize ) { add_reg_note ( insn , REG_CFA_SET_VDRAP , drap_vreg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } return drap_vreg ; } else return NULL ; } </s>

Handle the TARGET_GET_DRAP_RTX hook . Return NULL if no DRAP is needed or an rtx for DRAP otherwise .


<s> TargetTransformInfo PPCTargetMachine :: getTargetTransformInfo ( const Function & F ) const { return TargetTransformInfo ( PPCTTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> static void mips_select_rtx_section ( enum machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ) { if ( TARGET_MIPS16 ) { function_section ( current_function_decl ) ; } else if ( TARGET_EMBEDDED_DATA ) { mergeable_constant_section ( mode , align , 0 ) ; } else { if ( GET_MODE_SIZE ( mode ) <= ( unsigned ) mips_section_threshold && mips_section_threshold > 0 ) named_section ( 0 , ".sdata" , 0 ) ; else if ( flag_pic && symbolic_expression_p ( x ) ) named_section ( 0 , ".data.rel.ro" , 3 ) ; else mergeable_constant_section ( mode , align , 0 ) ; } } </s>

Choose the section to use for the constant rtx expression X that has mode MODE .


<s>
void
ARCRegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected"
)
;
MachineInstr
&
MI
=
*
II
;
MachineOperand
&
FrameOp
=
MI
.
getOperand
(
FIOperandNum
)
;
int
FrameIndex
=
FrameOp
.
getIndex
(
)
;
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
const
ARCInstrInfo
&
TII
=
*
MF
.
getSubtarget
<
ARCSubtarget
>
(
)
.
getInstrInfo
(
)
;
const
ARCFrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
int
Offset
=
MF
.
getFrameInfo
(
)
.
getObjectOffset
(
FrameIndex
)
;
int
ObjSize
=
MF
.
getFrameInfo
(
)
.
getObjectSize
(
FrameIndex
)
;
int
StackSize
=
MF
.
getFrameInfo
(
)
.
getStackSize
(
)
;
int
LocalFrameSize
=
MF
.
getFrameInfo
(
)
.
getLocalFrameSize
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"\nFunction         : "
<<
MF
.
getName
(
)
<<
"\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"<--------->\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
MI
<<
"\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"FrameIndex         : "
<<
FrameIndex
<<
"\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ObjSize            : "
<<
ObjSize
<<
"\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"FrameOffset        : "
<<
Offset
<<
"\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"StackSize          : "
<<
StackSize
<<
"\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"LocalFrameSize     : "
<<
LocalFrameSize
<<
"\n"
)
;
(
void
)
LocalFrameSize
;
if
(
MI
.
isDebugValue
(
)
)
{
Register
FrameReg
=
getFrameRegister
(
MF
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
)
;
return
;
}
Offset
+=
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Offset             : "
<<
Offset
<<
"\n"
<<
"<--------->\n"
)
;
unsigned
Reg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
assert
(
ARC
::
GPR32RegClass
.
contains
(
Reg
)
&&
"Unexpected register operand"
)
;
if
(
!
TFI
->
hasFP
(
MF
)
)
{
Offset
=
StackSize
+
Offset
;
if
(
FrameIndex
>=
0
)
assert
(
(
Offset
>=
0
&&
Offset
<
StackSize
)
&&
"SP Offset not in bounds."
)
;
}
else
{
if
(
FrameIndex
>=
0
)
{
assert
(
(
Offset
<
0
&&
Offset
<=
StackSize
)
&&
"FP Offset not in bounds."
)
;
}
}
ReplaceFrameIndex
(
II
,
TII
,
Reg
,
getFrameRegister
(
MF
)
,
Offset
,
StackSize
,
ObjSize
,
RS
,
SPAdj
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .

ARC
ARC
0
"Unexpected"
ARC
ARC
ARC
"\nFunction         : "
"\n"
"<--------->\n"
"\n"
"FrameIndex         : "
"\n"
"ObjSize            : "
"\n"
"FrameOffset        : "
"\n"
"StackSize          : "
"\n"
"LocalFrameSize     : "
"\n"
1
1
"Offset             : "
"\n"
"<--------->\n"
0
ARC::GPR32RegClass
"Unexpected register operand"
0
0
"SP Offset not in bounds."
0
0
"FP Offset not in bounds."


<s> bool ARMTargetLowering :: shouldSinkOperands ( Instruction * I , SmallVectorImpl < Use * > & Ops ) const { if ( ! I -> getType ( ) -> isVectorTy ( ) ) return false ; if ( Subtarget -> hasNEON ( ) ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Sub : case Instruction :: Add : { if ( ! areExtractExts ( I -> getOperand ( 0 ) , I -> getOperand ( 1 ) ) ) return false ; Ops . push_back ( & I -> getOperandUse ( 0 ) ) ; Ops . push_back ( & I -> getOperandUse ( 1 ) ) ; return true ; } default : return false ; } } if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; auto IsSinker = [ ] ( Instruction * I , int Operand ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Add : case Instruction :: Mul : case Instruction :: ICmp : return true ; case Instruction :: Sub : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return Operand == 1 ; default : return false ; } } ; int Op = 0 ; if ( ! isa < ShuffleVectorInst > ( I -> getOperand ( Op ) ) ) Op = 1 ; if ( ! IsSinker ( I , Op ) ) return false ; if ( ! match ( I -> getOperand ( Op ) , m_ShuffleVector ( m_InsertElement ( m_Undef ( ) , m_Value ( ) , m_ZeroInt ( ) ) , m_Undef ( ) , m_Zero ( ) ) ) ) { return false ; } Instruction * Shuffle = cast < Instruction > ( I -> getOperand ( Op ) ) ; for ( Use & U : Shuffle -> uses ( ) ) { Instruction * Insn = cast < Instruction > ( U . getUser ( ) ) ; if ( ! IsSinker ( Insn , U . getOperandNo ( ) ) ) return false ; } Ops . push_back ( & Shuffle -> getOperandUse ( 0 ) ) ; Ops . push_back ( & I -> getOperandUse ( Op ) ) ; return true ; } </s>

Return true if sinking I 's operands to the same basic block as I is profitable , e.g .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> bool MBlazeIntrinsicInfo :: isOverloaded ( unsigned IntrID ) const { if ( IntrID == 0 ) return false ; unsigned id = IntrID - Intrinsic :: num_intrinsics + 1 ; } </s>

Returns true if the intrinsic can be overloaded .


<s> void HexagonSubtarget :: adjustSchedDependency ( SUnit * Src , SUnit * Dst , SDep & Dep ) const { MachineInstr * SrcInst = Src -> getInstr ( ) ; MachineInstr * DstInst = Dst -> getInstr ( ) ; if ( ! Src -> isInstr ( ) || ! Dst -> isInstr ( ) ) return ; const HexagonInstrInfo * QII = static_cast < const HexagonInstrInfo * > ( getInstrInfo ( ) ) ; if ( QII -> canExecuteInBundle ( * SrcInst , * DstInst ) && isBestZeroLatency ( Src , Dst , QII ) ) { Dep . setLatency ( 0 ) ; return ; } if ( ! hasV60TOps ( ) ) return ; if ( QII -> isPostIncrement ( * SrcInst ) && Dep . isAssignedRegDep ( ) ) { if ( SrcInst -> mayStore ( ) ) return ; if ( Dep . getReg ( ) != SrcInst -> getOperand ( 0 ) . getReg ( ) ) return ; } else if ( QII -> isPostIncrement ( * DstInst ) && Dep . getKind ( ) == SDep :: Anti ) { if ( DstInst -> mayStore ( ) ) return ; if ( Dep . getReg ( ) != DstInst -> getOperand ( 0 ) . getReg ( ) ) return ; } else if ( QII -> isPostIncrement ( * DstInst ) && DstInst -> mayStore ( ) && Dep . isAssignedRegDep ( ) ) { MachineOperand & Op = DstInst -> getOperand ( DstInst -> getNumOperands ( ) - 1 ) ; if ( Op . isReg ( ) && Dep . getReg ( ) != Op . getReg ( ) ) return ; } if ( useBSBScheduling ( ) && SrcInst -> isPHI ( ) ) { changePhiLatency ( * SrcInst , Dst , Dep ) ; return ; } if ( DstInst -> isRegSequence ( ) && Dst -> NumSuccs == 1 ) DstInst = Dst -> Succs [ 0 ] . getSUnit ( ) -> getInstr ( ) ; if ( EnableDotCurSched && QII -> isToBeScheduledASAP ( * SrcInst , * DstInst ) && isBestZeroLatency ( Src , Dst , QII ) ) { Dep . setLatency ( 0 ) ; return ; } updateLatency ( * SrcInst , * DstInst , Dep ) ; } </s>

Perform target specific adjustments to the latency of a schedule dependency .


<s>
enum
cris_symbol_type
cris_symbol_type_of
(
const_rtx
x
)
{
switch
(
GET_CODE
(
x
)
)
{
case
SYMBOL_REF
:
return
flag_pic
(
SYMBOL_REF_LOCAL_P
(
x
)
cris_rel_symbol
:
cris_got_symbol
)
:
cris_offsettable_symbol
;
case
LABEL_REF
:
return
flag_pic
cris_rel_symbol
:
cris_offsettable_symbol
;
case
CONST
:
return
cris_symbol_type_of
(
XEXP
(
x
,
0
)
)
;
case
PLUS
:
case
MINUS
:
{
enum
cris_symbol_type
t1
=
cris_symbol_type_of
(
XEXP
(
x
,
0
)
)
;
enum
cris_symbol_type
t2
=
cris_symbol_type_of
(
XEXP
(
x
,
1
)
)
;
gcc_assert
(
t1
==
cris_no_symbol
||
t2
==
cris_no_symbol
)
;
if
(
t1
==
cris_got_symbol
||
t2
==
cris_got_symbol
)
return
cris_got_symbol_needing_fixup
;
return
t1
!=
cris_no_symbol
t1
:
t2
;
}
case
CONST_INT
:
case
CONST_DOUBLE
:
return
cris_no_symbol
;
case
UNSPEC
:
return
cris_unspec
;
default
:
fatal_insn
(
"unrecognized supposed constant"
,
x
)
;
}
gcc_unreachable
(
)
;
}
</s>

Helper function to find the right symbol-type to generate , given the original ( non-PIC ) representation .


<s> static const char * getName ( ) { return DEBUG_TYPE ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> void SPUHazardRecognizer :: AdvanceCycle ( ) { DEBUG ( errs ( ) << "SPUHazardRecognizer::AdvanceCycle\n" ) ; } </s>

AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled can not issue in the current cycle , either because of latency or resource conflicts .


<s> int includes_rldic_lshift_p ( rtx shiftop , rtx andop ) { if ( GET_CODE ( andop ) == CONST_INT ) { unsigned HOST_WIDE_INT c , lsb , shift_mask ; c = INTVAL ( andop ) ; if ( c == 0 || c == HOST_WIDE_INT_M1U ) return 0 ; shift_mask = HOST_WIDE_INT_M1U ; shift_mask <<= INTVAL ( shiftop ) ; lsb = c & - c ; if ( - lsb != shift_mask ) return 0 ; c = ~ c ; c &= - lsb ; lsb = c & - c ; return c == - lsb ; } else return 0 ; } </s>

Return 1 if ANDOP is a mask suitable for use with an rldic insn to perform a left shift . It must have exactly SHIFTOP least significant 0 's , then one or more 1 's , then zero or more 0 's .


<s> unsigned PPCTTIImpl :: getCacheLineSize ( ) const { if ( CacheLineSize . getNumOccurrences ( ) > 0 ) return CacheLineSize ; unsigned Directive = ST -> getCPUDirective ( ) ; if ( Directive == PPC :: DIR_PWR7 || Directive == PPC :: DIR_PWR8 || Directive == PPC :: DIR_PWR9 || Directive == PPC :: DIR_PWR_FUTURE ) return 128 ; return 64 ; } </s>

Return the target cache line size in bytes .


<s> unsigned AlphaRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; return TFI -> hasFP ( MF ) ? Alpha :: R15 : Alpha :: R30 ; } </s>


<s> enum reg_class pdp11_regno_reg_class ( int regno ) { if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return GENERAL_REGS ; else if ( regno > AC3_REGNUM ) return NO_LOAD_FPU_REGS ; else if ( regno >= AC0_REGNUM ) return LOAD_FPU_REGS ; else if ( regno & 1 ) return MUL_REGS ; else return GENERAL_REGS ; } </s>

Return the class number of the smallest class containing reg number REGNO .


<s> static inline bool m32r_store_preinc_predec_p ( machine_mode mode , const_rtx x , bool strict ) { if ( ( mode == SImode || mode == SFmode ) && ( GET_CODE ( x ) == PRE_INC || GET_CODE ( x ) == PRE_DEC ) && REG_P ( XEXP ( x , 0 ) ) \ && m32r_rtx_ok_for_base_p ( XEXP ( x , 0 ) , strict ) ) return true ; return false ; } </s>

Is this an increment/decrement and store operation .


<s> virtual const TLCS900InstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


"AIX's linkage directives take a visibility setting."

"InternalLinkage should not have other visibility setting."

"CommonLinkage of XCOFF should not come to this path"

This emits linkage information about GVSym based on GV , if this is supported by the target .


<s> void emitImportModule ( const MCSymbolWasm * , StringRef ) override { } </s>


<s> static ArrayRef < MCPhysReg > getAllSGPR128 ( ) { return makeArrayRef ( AMDGPU :: SReg_128RegClass . begin ( ) , AMDGPU :: SReg_128RegClass . getNumRegs ( ) ) ; } </s>

Return all SGPR128 which satisfy the waves per execution unit requirement of the subtarget .


<s> bool isMem ( ) const { return Kind == k_Memri ; } </s>


<s> int use_return_insn ( int iscond , rtx sibling ) { int regno ; unsigned int func_type ; unsigned long saved_int_regs ; unsigned HOST_WIDE_INT stack_adjust ; arm_stack_offsets * offsets ; if ( ! reload_completed ) return 0 ; if ( arm_current_function_pac_enabled_p ( ) ) return 0 ; func_type = arm_current_func_type ( ) ; if ( func_type & ( ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN ) ) return 0 ; if ( IS_INTERRUPT ( func_type ) && ( frame_pointer_needed || TARGET_THUMB ) ) return 0 ; if ( TARGET_LDRD && current_tune -> prefer_ldrd_strd && ! optimize_function_for_size_p ( cfun ) ) return 0 ; offsets = arm_get_frame_offsets ( ) ; stack_adjust = offsets -> outgoing_args - offsets -> saved_regs ; if ( crtl -> args . pretend_args_size || cfun -> machine -> uses_anonymous_args || crtl -> calls_eh_return || cfun -> calls_alloca || ! ( stack_adjust == 0 || ( TARGET_APCS_FRAME && frame_pointer_needed && stack_adjust == 4 ) ) || ( ! ( TARGET_APCS_FRAME && frame_pointer_needed ) && arm_compute_static_chain_stack_bytes ( ) != 0 ) ) return 0 ; saved_int_regs = offsets -> saved_regs_mask ; if ( stack_adjust == 4 && ! arm_arch5t && TARGET_ARM ) { if ( ! call_used_or_fixed_reg_p ( 3 ) ) return 0 ; if ( arm_size_return_regs ( ) >= ( 4 * UNITS_PER_WORD ) ) return 0 ; if ( sibling ) { gcc_assert ( CALL_P ( sibling ) ) ; if ( find_regno_fusage ( sibling , USE , 3 ) ) return 0 ; } if ( saved_int_regs & 0x7 ) return 0 ; } if ( TARGET_INTERWORK && saved_int_regs != 0 && ! IS_INTERRUPT ( func_type ) ) return 0 ; if ( iscond && arm_tune_strongarm ) { if ( saved_int_regs != 0 && saved_int_regs != ( 1 << LR_REGNUM ) ) return 0 ; if ( flag_pic && arm_pic_register != INVALID_REGNUM && df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) ) return 0 ; } if ( IS_CMSE_ENTRY ( func_type ) && ( saved_int_regs || TARGET_HAVE_FPCXT_CMSE ) ) return 0 ; if ( saved_int_regs && ! ( saved_int_regs & ( 1 << LR_REGNUM ) ) ) return 0 ; if ( TARGET_VFP_BASE ) for ( regno = FIRST_VFP_REGNUM ; regno <= LAST_VFP_REGNUM ; regno ++ ) if ( reg_needs_saving_p ( regno ) ) return 0 ; if ( TARGET_REALLY_IWMMXT ) for ( regno = FIRST_IWMMXT_REGNUM ; regno <= LAST_IWMMXT_REGNUM ; regno ++ ) if ( reg_needs_saving_p ( regno ) ) return 0 ; return 1 ; } </s>

Return true if this function 's epilogue can be output as RTL .


<s>
bool
SystemZRegisterInfo
::
shouldCoalesce
(
MachineInstr
*
MI
,
const
TargetRegisterClass
*
SrcRC
,
unsigned
SubReg
,
const
TargetRegisterClass
*
DstRC
,
unsigned
DstSubReg
,
const
TargetRegisterClass
*
NewRC
,
LiveIntervals
&
LIS
)
const
{
assert
(
MI
->
isCopy
(
)
&&
"Only expecting COPY instructions"
)
;
if
(
!
(
NewRC
->
hasSuperClassEq
(
&
SystemZ
::
GR128BitRegClass
)
&&
(
getRegSizeInBits
(
*
SrcRC
)
<=
64
||
getRegSizeInBits
(
*
DstRC
)
<=
64
)
)
)
return
true
;
unsigned
WideOpNo
=
(
getRegSizeInBits
(
*
SrcRC
)
==
128
1
:
0
)
;
unsigned
GR128Reg
=
MI
->
getOperand
(
WideOpNo
)
.
getReg
(
)
;
unsigned
GRNarReg
=
MI
->
getOperand
(
(
WideOpNo
==
1
)
0
:
1
)
.
getReg
(
)
;
LiveInterval
&
IntGR128
=
LIS
.
getInterval
(
GR128Reg
)
;
LiveInterval
&
IntGRNar
=
LIS
.
getInterval
(
GRNarReg
)
;
MachineBasicBlock
*
MBB
=
MI
->
getParent
(
)
;
if
(
LIS
.
isLiveInToMBB
(
IntGR128
,
MBB
)
||
LIS
.
isLiveOutOfMBB
(
IntGR128
,
MBB
)
||
LIS
.
isLiveInToMBB
(
IntGRNar
,
MBB
)
||
LIS
.
isLiveOutOfMBB
(
IntGRNar
,
MBB
)
)
return
false
;
MachineInstr
*
FirstMI
=
nullptr
,
*
LastMI
=
nullptr
;
if
(
WideOpNo
==
1
)
{
FirstMI
=
LIS
.
getInstructionFromIndex
(
IntGR128
.
beginIndex
(
)
)
;
LastMI
=
LIS
.
getInstructionFromIndex
(
IntGRNar
.
endIndex
(
)
)
;
}
else
{
FirstMI
=
LIS
.
getInstructionFromIndex
(
IntGRNar
.
beginIndex
(
)
)
;
LastMI
=
LIS
.
getInstructionFromIndex
(
IntGR128
.
endIndex
(
)
)
;
}
assert
(
FirstMI
&&
LastMI
&&
"No instruction from index?"
)
;
BitVector
PhysClobbered
(
getNumRegs
(
)
)
;
MachineBasicBlock
::
iterator
MII
=
FirstMI
,
MEE
=
LastMI
;
MEE
++
;
for
(
;
MII
!=
MEE
;
++
MII
)
{
for
(
const
MachineOperand
&
MO
:
MII
->
operands
(
)
)
if
(
MO
.
isReg
(
)
&&
isPhysicalRegister
(
MO
.
getReg
(
)
)
)
{
for
(
MCSuperRegIterator
SI
(
MO
.
getReg
(
)
,
this
,
true
)
;
SI
.
isValid
(
)
;
++
SI
)
if
(
NewRC
->
contains
(
*
SI
)
)
{
PhysClobbered
.
set
(
*
SI
)
;
break
;
}
}
}
unsigned
const
DemandedFreeGR128
=
3
;
if
(
PhysClobbered
.
count
(
)
>
(
NewRC
->
getNumRegs
(
)
DemandedFreeGR128
)
)
return
false
;
return
true
;
}
</s>


<s>
bool
TL45InstrInfo
::
expandPostRAPseudo
(
MachineInstr
&
MI
)
const
{
const
DebugLoc
DL
=
MI
.
getDebugLoc
(
)
;
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
return
false
;
case
TL45
::
CMP_JMP
:
{
auto
ConditionCode
=
ISD
::
CondCode
(
MI
.
getOperand
(
0
)
.
getImm
(
)
)
;
unsigned
int
JmpOpcode
;
resolveComparison
(
MBB
,
MI
,
DL
,
ConditionCode
,
MI
.
getOperand
(
1
)
,
MI
.
getOperand
(
2
)
,
JmpOpcode
,
false
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
JmpOpcode
)
)
.
add
(
MI
.
getOperand
(
3
)
)
;
break
;
}
case
TL45
::
CMPI_JMP
:
{
auto
ConditionCode
=
ISD
::
CondCode
(
MI
.
getOperand
(
0
)
.
getImm
(
)
)
;
unsigned
int
JmpOpcode
;
resolveComparison
(
MBB
,
MI
,
DL
,
ConditionCode
,
MI
.
getOperand
(
1
)
,
MI
.
getOperand
(
2
)
,
JmpOpcode
,
true
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
JmpOpcode
)
)
.
add
(
MI
.
getOperand
(
3
)
)
;
break
;
}
case
TL45
::
ADD32
:
{
MachineOperand
&
dst
=
MI
.
getOperand
(
0
)
;
MachineOperand
&
src
=
MI
.
getOperand
(
1
)
;
MachineOperand
&
imm
=
MI
.
getOperand
(
2
)
;
assert
(
imm
.
isImm
(
)
&&
"imm must be immediate"
)
;
uint64_t
val
=
(
uint32_t
)
imm
.
getImm
(
)
;
uint64_t
low
=
val
&
0xffffu
;
uint64_t
high
=
(
val
>>
16u
)
&
0xffffu
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
TL45
::
ADDIZ
)
)
.
add
(
dst
)
.
add
(
src
)
.
addImm
(
low
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
TL45
::
ADDHI
)
)
.
add
(
dst
)
.
add
(
dst
)
.
addImm
(
high
)
;
break
;
}
}
MBB
.
erase
(
MI
)
;
return
true
;
}
</s>

This function is called for all pseudo instructions that remain after register allocation .


<s> void NVPTXPassConfig :: addIRPasses ( ) { disablePass ( & PrologEpilogCodeInserterID ) ; disablePass ( & MachineCopyPropagationID ) ; disablePass ( & TailDuplicateID ) ; disablePass ( & StackMapLivenessID ) ; disablePass ( & LiveDebugValuesID ) ; disablePass ( & PostRAMachineSinkingID ) ; disablePass ( & PostRASchedulerID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & PatchableFunctionID ) ; disablePass ( & ShrinkWrapID ) ; const NVPTXSubtarget & ST = * getTM < NVPTXTargetMachine > ( ) . getSubtargetImpl ( ) ; addPass ( createNVVMReflectPass ( ST . getSmVersion ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createNVPTXImageOptimizerPass ( ) ) ; addPass ( createNVPTXAssignValidGlobalNamesPass ( ) ) ; addPass ( createGenericToNVVMPass ( ) ) ; addPass ( createNVPTXLowerArgsPass ( & getNVPTXTargetMachine ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addAddressSpaceInferencePasses ( ) ; addStraightLineScalarOptimizationPasses ( ) ; } addPass ( createAtomicExpandPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addEarlyCSEOrGVNPass ( ) ; if ( ! DisableLoadStoreVectorizer ) addPass ( createLoadStoreVectorizerPass ( ) ) ; addPass ( createSROAPass ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX


<s> unsigned SIRegisterInfo :: reservedPrivateSegmentBufferReg ( const MachineFunction & MF ) const { const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; unsigned BaseIdx = alignDown ( ST . getMaxNumSGPRs ( MF ) , 4 ) - 4 ; unsigned BaseReg ( AMDGPU :: SGPR_32RegClass . getRegister ( BaseIdx ) ) ; return getMatchingSuperReg ( BaseReg , AMDGPU :: sub0 , & AMDGPU :: SReg_128RegClass ) ; } </s>

Return the end register initially reserved for the scratch buffer in case spilling is needed .


<s>
int
AArch64TTIImpl
::
getArithmeticReductionCost
(
unsigned
Opcode
,
VectorType
*
ValTy
,
bool
IsPairwiseForm
)
{
if
(
IsPairwiseForm
)
return
BaseT
::
getArithmeticReductionCost
(
Opcode
,
ValTy
,
IsPairwiseForm
)
;
std
::
pair
<
int
,
MVT
>
LT
=
TLI
->
getTypeLegalizationCost
(
DL
,
ValTy
)
;
MVT
MTy
=
LT
.
second
;
int
ISD
=
TLI
->
InstructionOpcodeToISD
(
Opcode
)
;
assert
(
ISD
&&
"Invalid opcode"
)
;
static
const
CostTblEntry
CostTblNoPairwise
[
]
{
{
ISD
::
ADD
,
MVT
::
v8i8
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v16i8
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v4i16
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v8i16
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v4i32
,
1
}
,
}
;
if
(
const
auto
*
Entry
=
CostTableLookup
(
CostTblNoPairwise
,
ISD
,
MTy
)
)
return
LT
.
first
*
Entry
->
Cost
;
return
BaseT
::
getArithmeticReductionCost
(
Opcode
,
ValTy
,
IsPairwiseForm
)
;
}
</s>

Calculate the cost of vector reduction intrinsics .


<s> bool doInitialization ( Module & ) override { if ( ! StatsFile . empty ( ) && ! AppendStatsFile && sys :: fs :: exists ( StatsFile ) ) { sys :: fs :: remove ( StatsFile . c_str ( ) ) ; } return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
void
SIScheduleBlock
::
addPred
(
SIScheduleBlock
*
Pred
)
{
unsigned
PredID
=
Pred
->
getID
(
)
;
for
(
SIScheduleBlock
*
P
:
Preds
)
{
if
(
PredID
==
P
->
getID
(
)
)
return
;
}
Preds
.
push_back
(
Pred
)
;
assert
(
none_of
(
Succs
,
[
=
]
(
SIScheduleBlock
*
S
)
{
return
PredID
==
S
->
getID
(
)
;
}
)
&&
"Loop in the Block Graph!"
)
;
}
</s>

Adds the specified edge as a pred of the current node if not already .

AMDGPU
SI
SI
SI
SI
"Loop in the Block Graph!"


<s>
void
assignValueToReg
(
Register
ValVReg
,
Register
PhysReg
,
CCValAssign
VA
)
override
{
switch
(
VA
.
getLocVT
(
)
.
getSizeInBits
(
)
)
{
default
:
report_fatal_error
(
"Not yet implemented."
)
;
case
8
:
case
16
:
break
;
}
makeLive
(
PhysReg
)
;
MIRBuilder
.
buildCopy
(
ValVReg
,
PhysReg
)
;
}
</s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


"expression value must be representable in 32 bits"

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> void CSKYAsmPrinter :: emitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; if ( InConstantPool && MI -> getOpcode ( ) != CSKY :: CONSTPOOL_ENTRY ) { InConstantPool = false ; } if ( MI -> getOpcode ( ) == CSKY :: PseudoTLSLA32 ) return expandTLSLA ( MI ) ; if ( MI -> getOpcode ( ) == CSKY :: CONSTPOOL_ENTRY ) return emitCustomConstantPool ( MI ) ; MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

Targets should implement this to emit instructions .


<s> machine_mode arc_select_cc_mode ( enum rtx_code op , rtx x , rtx y ) { machine_mode mode = GET_MODE ( x ) ; rtx x1 ; if ( GET_MODE_CLASS ( mode ) == MODE_INT && y == const0_rtx && ( op == EQ || op == NE || ( ( op == LT || op == GE ) && GET_MODE_SIZE ( GET_MODE ( x ) ) <= 4 ) ) ) return CC_ZNmode ; if ( mode == SImode && GET_CODE ( y ) == NEG && ( op == EQ || op == NE ) ) return CC_ZNmode ; if ( mode == SImode && ( op == EQ || op == NE ) && CONST_INT_P ( y ) && ( ( INTVAL ( y ) - 1 ) & INTVAL ( y ) ) == 0 && INTVAL ( y ) ) return CC_Zmode ; if ( mode == SImode && ( op == EQ || op == NE ) && CONST_INT_P ( y ) && GET_CODE ( x ) == AND && CONST_INT_P ( ( x1 = XEXP ( x , 1 ) ) ) && ( ( INTVAL ( x1 ) + 1 ) & INTVAL ( x1 ) ) == 0 && ( ~ INTVAL ( x1 ) | INTVAL ( y ) ) < 0 && ( ~ INTVAL ( x1 ) | INTVAL ( y ) ) > - 0x800 ) return CC_Zmode ; if ( GET_MODE ( x ) == SImode && ( op == LTU || op == GEU ) && GET_CODE ( x ) == PLUS && ( rtx_equal_p ( XEXP ( x , 0 ) , y ) || rtx_equal_p ( XEXP ( x , 1 ) , y ) ) ) return CC_Cmode ; if ( TARGET_ARGONAUT_SET && ( ( mode == SFmode && TARGET_SPFP ) || ( mode == DFmode && TARGET_DPFP ) ) ) switch ( op ) { case EQ : case NE : case UNEQ : case LTGT : case ORDERED : case UNORDERED : return CC_FPXmode ; case LT : case UNGE : case GT : case UNLE : return CC_FP_GTmode ; case LE : case UNGT : case GE : case UNLT : return CC_FP_GEmode ; default : gcc_unreachable ( ) ; } else if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && TARGET_OPTFPE ) switch ( op ) { case EQ : case NE : return CC_Zmode ; case LT : case UNGE : case GT : case UNLE : return CC_FP_GTmode ; case LE : case UNGT : case GE : case UNLT : return CC_FP_GEmode ; case UNEQ : case LTGT : return CC_FP_UNEQmode ; case ORDERED : case UNORDERED : return CC_FP_ORDmode ; default : gcc_unreachable ( ) ; } return CCmode ; } </s>

Given a comparison code ( EQ , NE , etc . ) and the first operand of a COMPARE , return the mode to be used for the comparison .


<s> bool FISCTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( ! AM . HasBaseReg ) break ; return false ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> void GCNPassConfig :: addPreGlobalInstructionSelect ( ) { bool IsOptNone = getOptLevel ( ) == CodeGenOpt :: None ; addPass ( createAMDGPURegBankCombiner ( IsOptNone ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before the ( global ) instruction selection .


<s> void X86InstrInfo :: breakPartialRegDependency ( MachineBasicBlock :: iterator MI , unsigned OpNum , const TargetRegisterInfo * TRI ) const { unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; if ( X86 :: VR128RegClass . contains ( Reg ) ) { bool HasAVX = TM . getSubtarget < X86Subtarget > ( ) . hasAVX ( ) ; unsigned Opc = HasAVX ? X86 :: VXORPSrr : X86 :: XORPSrr ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , get ( Opc ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; } else if ( X86 :: VR256RegClass . contains ( Reg ) ) { unsigned XReg = TRI -> getSubReg ( Reg , X86 :: sub_xmm ) ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , get ( X86 :: VXORPSrr ) , XReg ) . addReg ( XReg , RegState :: Undef ) . addReg ( XReg , RegState :: Undef ) . addReg ( Reg , RegState :: ImplicitDefine ) ; } else return ; MI -> addRegisterKilled ( Reg , TRI , true ) ; } </s>

Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum .


<s> static void expand_small_cpymem_or_setmem ( rtx destmem , rtx srcmem , rtx destptr , rtx srcptr , rtx value , rtx vec_value , rtx count , int size , rtx done_label , bool issetmem ) { rtx_code_label * label = ix86_expand_aligntest ( count , size , false ) ; machine_mode mode = int_mode_for_size ( size * BITS_PER_UNIT , 1 ) . else_blk ( ) ; rtx modesize ; int n ; if ( issetmem ) { if ( ! vec_value ) { if ( GET_MODE ( value ) == VOIDmode && size > 8 ) mode = Pmode ; else if ( GET_MODE_SIZE ( mode ) > GET_MODE_SIZE ( GET_MODE ( value ) ) ) mode = GET_MODE ( value ) ; } else mode = GET_MODE ( vec_value ) , value = vec_value ; } else { if ( size >= 32 ) mode = TARGET_AVX ? V32QImode : TARGET_SSE ? V16QImode : DImode ; else if ( size >= 16 ) mode = TARGET_SSE ? V16QImode : DImode ; srcmem = change_address ( srcmem , mode , srcptr ) ; } destmem = change_address ( destmem , mode , destptr ) ; modesize = GEN_INT ( GET_MODE_SIZE ( mode ) ) ; gcc_assert ( GET_MODE_SIZE ( mode ) <= size ) ; for ( n = 0 ; n * GET_MODE_SIZE ( mode ) < size ; n ++ ) { if ( issetmem ) emit_move_insn ( destmem , gen_lowpart ( mode , value ) ) ; else { emit_move_insn ( destmem , srcmem ) ; srcmem = offset_address ( srcmem , modesize , GET_MODE_SIZE ( mode ) ) ; } destmem = offset_address ( destmem , modesize , GET_MODE_SIZE ( mode ) ) ; } destmem = offset_address ( destmem , count , 1 ) ; destmem = offset_address ( destmem , GEN_INT ( - 2 * size ) , GET_MODE_SIZE ( mode ) ) ; if ( ! issetmem ) { srcmem = offset_address ( srcmem , count , 1 ) ; srcmem = offset_address ( srcmem , GEN_INT ( - 2 * size ) , GET_MODE_SIZE ( mode ) ) ; } for ( n = 0 ; n * GET_MODE_SIZE ( mode ) < size ; n ++ ) { if ( issetmem ) emit_move_insn ( destmem , gen_lowpart ( mode , value ) ) ; else { emit_move_insn ( destmem , srcmem ) ; srcmem = offset_address ( srcmem , modesize , GET_MODE_SIZE ( mode ) ) ; } destmem = offset_address ( destmem , modesize , GET_MODE_SIZE ( mode ) ) ; } emit_jump_insn ( gen_jump ( done_label ) ) ; emit_barrier ( ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; } </s>

Test if COUNT & SIZE is nonzero and if so , expand movme or setmem sequence that is valid for SIZE .. 2 * SIZE-1 bytes and jump to DONE_LABEL .


"Not expecting modifiers with immediates"

This method commutes the operands of the given machine instruction MI .


Clear caller saved registers not used to pass return values and leaked condition flags before exiting a cmse_nonsecure_entry function .


<s> void AArch64BranchTargets :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> bool HexagonFixupHwLoops :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = fixupLoopInstrs ( MF ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s>
const
char
*
PTXTargetLowering
::
getTargetNodeName
(
unsigned
Opcode
)
const
{
switch
(
Opcode
)
{
default
:
llvm_unreachable
(
"Unknown opcode"
)
;
case
PTXISD
::
READ_PARAM
:
return
"PTXISD::READ_PARAM"
;
case
PTXISD
::
EXIT
:
return
"PTXISD::EXIT"
;
case
PTXISD
::
RET
:
return
"PTXISD::RET"
;
}
}
</s>

getTargetNodeName - This method returns the name of a target specific

PTX
PTX
"Unknown opcode"
PTXISD::READ_PARAM
"PTXISD::READ_PARAM"
PTXISD::EXIT
"PTXISD::EXIT"
PTXISD::RET
"PTXISD::RET"


<s> static void output_short_suffix ( FILE * file ) { rtx_insn * insn = current_output_insn ; if ( arc_verify_short ( insn , cfun -> machine -> unalign , 1 ) ) { fprintf ( file , "_s" ) ; cfun -> machine -> unalign ^= 2 ; } extract_insn_cached ( insn ) ; } </s>

When outputting an instruction ( alternative ) that can potentially be short , output the short suffix if the insn is in fact short , and update cfun- > machine- > unalign accordingly .


"JIT relocation model must be set to static or default!"


<s> static bool chkp_type_has_function_pointer ( const_tree type ) { bool res = false ; if ( POINTER_TYPE_P ( type ) && FUNC_OR_METHOD_TYPE_P ( TREE_TYPE ( type ) ) ) res = true ; else if ( RECORD_OR_UNION_TYPE_P ( type ) ) { tree field ; for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) if ( TREE_CODE ( field ) == FIELD_DECL ) res = res || chkp_type_has_function_pointer ( TREE_TYPE ( field ) ) ; } else if ( TREE_CODE ( type ) == ARRAY_TYPE ) res = chkp_type_has_function_pointer ( TREE_TYPE ( type ) ) ; return res ; } </s>

Return 1 if type TYPE is a pointer to function type or a structure having a pointer to function type as one of its fields . Otherwise return 0 .


<s> static void mips_avoid_hazard ( rtx_insn * after , rtx_insn * insn , int * hilo_delay , rtx * delayed_reg , rtx lo_reg ) { rtx pattern , set ; int nops , ninsns ; pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) == ASM_INPUT || asm_noperands ( pattern ) >= 0 ) cfun -> machine -> all_noreorder_p = false ; ninsns = get_attr_length ( insn ) / 4 ; if ( ninsns == 0 ) return ; if ( * hilo_delay < 2 && reg_set_p ( lo_reg , pattern ) ) nops = 2 - * hilo_delay ; else if ( * delayed_reg != 0 && reg_referenced_p ( * delayed_reg , pattern ) ) nops = 1 ; else nops = 0 ; * hilo_delay += nops ; while ( nops -- > 0 ) emit_insn_after ( gen_hazard_nop ( ) , after ) ; * hilo_delay += ninsns ; * delayed_reg = 0 ; if ( INSN_CODE ( insn ) >= 0 ) switch ( get_attr_hazard ( insn ) ) { case HAZARD_NONE : break ; case HAZARD_HILO : * hilo_delay = 0 ; break ; case HAZARD_DELAY : set = single_set ( insn ) ; gcc_assert ( set ) ; * delayed_reg = SET_DEST ( set ) ; break ; } } </s>

Subroutine of mips_reorg . If there is a hazard between INSN and a previous instruction , avoid it by inserting nops after instruction AFTER . * DELAYED_REG and * HILO_DELAY describe the hazards that apply at this point . If * DELAYED_REG is non-null , INSN must wait a cycle before using the value of that register . * HILO_DELAY counts the number of instructions since the last hilo hazard ( that is , the number of instructions since the last mflo or mfhi ) . After inserting nops for INSN , update * DELAYED_REG and * HILO_DELAY for the next instruction . LO_REG is an rtx for the LO register , used in dependence checking .


<s> void PPCRegisterInfo :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned TargetAlign = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - 1 ; if ( ! DisableRedZone && FrameSize <= 224 && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> hasCalls ( ) && ( ! ALIGN_STACK || MaxAlign <= TargetAlign ) ) { MFI -> setStackSize ( 0 ) ; return ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = PPCFrameInfo :: getMinCallFrameSize ( Subtarget . isPPC64 ( ) , Subtarget . isMachoABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; MFI -> setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s> void SystemZRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU


<s> static rtx address_offset ( rtx op ) { if ( GET_CODE ( op ) == PRE_INC || GET_CODE ( op ) == PRE_DEC ) op = XEXP ( op , 0 ) ; else if ( GET_CODE ( op ) == PRE_MODIFY || GET_CODE ( op ) == LO_SUM ) op = XEXP ( op , 1 ) ; if ( GET_CODE ( op ) == CONST ) op = XEXP ( op , 0 ) ; if ( GET_CODE ( op ) == PLUS ) op = XEXP ( op , 1 ) ; if ( CONST_INT_P ( op ) ) return op ; return NULL_RTX ; } </s>

Given an address , return a constant offset term if one exists .


<s> static bool rs6000_legitimate_combined_insn ( rtx_insn * insn ) { int icode = INSN_CODE ( insn ) ; if ( icode != CODE_FOR_nothing && ( icode == CODE_FOR_ctrsi_internal1 || icode == CODE_FOR_ctrdi_internal1 || icode == CODE_FOR_ctrsi_internal2 || icode == CODE_FOR_ctrdi_internal2 || icode == CODE_FOR_ctrsi_internal3 || icode == CODE_FOR_ctrdi_internal3 || icode == CODE_FOR_ctrsi_internal4 || icode == CODE_FOR_ctrdi_internal4 ) ) return false ; return true ; } </s>

Implement the TARGET_LEGITIMATE_COMBINED_INSN hook .


<s> bool ARMFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; unsigned PushOpc = AFI -> isThumbFunction ( ) ? ARM :: t2STMDB_UPD : ARM :: STMDB_UPD ; unsigned PushOneOpc = AFI -> isThumbFunction ( ) ? ARM :: t2STR_PRE : ARM :: STR_PRE_IMM ; unsigned FltOpc = ARM :: VSTMDDB_UPD ; unsigned NumAlignedDPRCS2Regs = AFI -> getNumAlignedDPRCS2Regs ( ) ; if ( AFI -> shouldSignReturnAddress ( ) ) { BuildMI ( MBB , MI , DebugLoc ( ) , STI . getInstrInfo ( ) -> get ( ARM :: t2PAC ) ) . setMIFlags ( MachineInstr :: FrameSetup ) ; } if ( llvm :: any_of ( CSI , [ ] ( const CalleeSavedInfo & C ) { return C . getReg ( ) == ARM :: FPCXTNS ; } ) ) { BuildMI ( MBB , MI , DebugLoc ( ) , STI . getInstrInfo ( ) -> get ( ARM :: VSTR_FPCXTNS_pre ) , ARM :: SP ) . addReg ( ARM :: SP ) . addImm ( - 4 ) . add ( predOps ( ARMCC :: AL ) ) ; } emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & isARMArea1Register , 0 , MachineInstr :: FrameSetup ) ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & isARMArea2Register , 0 , MachineInstr :: FrameSetup ) ; emitPushInst ( MBB , MI , CSI , FltOpc , 0 , true , & isARMArea3Register , NumAlignedDPRCS2Regs , MachineInstr :: FrameSetup ) ; if ( NumAlignedDPRCS2Regs ) emitAlignedDPRCS2Spills ( MBB , MI , NumAlignedDPRCS2Regs , CSI , TRI ) ; return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s>
static
void
hsa_fatal
(
const
char
*
str
,
hsa_status_t
status
)
{
const
char
*
hsa_error_msg
;
hsa_fns
.
hsa_status_string_fn
(
status
,
&
hsa_error_msg
)
;
fprintf
(
stderr
,
"%s: FAILED\nHSA Runtime message: %s\n"
,
str
,
hsa_error_msg
)
;
exit
(
1
)
;
}
</s>

Report a fatal error STR together with the HSA error corresponding to STATUS and terminate execution of the current process .

gcn
"%s: FAILED\nHSA Runtime message: %s\n"
1


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { GlobalBaseReg = 0 ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; return true ; } </s>


<s> static bool s390_match_ccmode_set ( rtx set , machine_mode req_mode ) { machine_mode set_mode ; gcc_assert ( GET_CODE ( set ) == SET ) ; gcc_assert ( req_mode != CCVIALLmode && req_mode != CCVIANYmode && req_mode != CCVFALLmode && req_mode != CCVFANYmode ) ; if ( GET_CODE ( SET_DEST ( set ) ) != REG || ! CC_REGNO_P ( REGNO ( SET_DEST ( set ) ) ) ) return 1 ; set_mode = GET_MODE ( SET_DEST ( set ) ) ; switch ( set_mode ) { case E_CCZ1mode : case E_CCSmode : case E_CCSRmode : case E_CCUmode : case E_CCURmode : case E_CCLmode : case E_CCL1mode : case E_CCL2mode : case E_CCL3mode : case E_CCT1mode : case E_CCT2mode : case E_CCT3mode : case E_CCVEQmode : case E_CCVIHmode : case E_CCVIHUmode : case E_CCVFHmode : case E_CCVFHEmode : if ( req_mode != set_mode ) return 0 ; break ; case E_CCZmode : if ( req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode && req_mode != CCSRmode && req_mode != CCURmode && req_mode != CCZ1mode ) return 0 ; break ; case E_CCAPmode : case E_CCANmode : if ( req_mode != CCAmode ) return 0 ; break ; default : gcc_unreachable ( ) ; } return ( GET_MODE ( SET_SRC ( set ) ) == set_mode ) ; } </s>

Return true if SET either does n't set the CC register , or else the source and destination have matching CC modes and that CC mode is at least as constrained as REQ_MODE .


<s> ARMTargetLowering :: ConstraintType ARMTargetLowering :: getConstraintType ( StringRef Constraint ) const { unsigned S = Constraint . size ( ) ; if ( S == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'l' : return C_RegisterClass ; case 'w' : return C_RegisterClass ; case 'h' : return C_RegisterClass ; case 'x' : return C_RegisterClass ; case 't' : return C_RegisterClass ; case 'j' : return C_Immediate ; case 'Q' : return C_Memory ; } } else if ( S == 2 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'T' : return C_RegisterClass ; case 'U' : return C_Memory ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> bool FalkorHWPFFix :: runOnMachineFunction ( MachineFunction & Fn ) { auto & ST = static_cast < const AArch64Subtarget & > ( Fn . getSubtarget ( ) ) ; if ( ST . getProcFamily ( ) != AArch64Subtarget :: Falkor ) return false ; if ( skipFunction ( Fn . getFunction ( ) ) ) return false ; TII = static_cast < const AArch64InstrInfo * > ( ST . getInstrInfo ( ) ) ; TRI = ST . getRegisterInfo ( ) ; MachineLoopInfo & LI = getAnalysis < MachineLoopInfo > ( ) ; Modified = false ; for ( MachineLoop * I : LI ) for ( auto L = df_begin ( I ) , LE = df_end ( I ) ; L != LE ; ++ L ) if ( L -> isInnermost ( ) ) runOnLoop ( * * L , Fn ) ; return Modified ; } </s>


<s> const uint32_t * ARMBaseRegisterInfo :: getNoPreservedMask ( ) const { return CSR_NoRegs_RegMask ; } </s>

Return a register mask that clobbers everything .


<s> static bool isPairedLdSt ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { default : return false ; case AArch64 :: LDPSi : case AArch64 :: LDPSWi : case AArch64 :: LDPDi : case AArch64 :: LDPQi : case AArch64 :: LDPWi : case AArch64 :: LDPXi : case AArch64 :: STPSi : case AArch64 :: STPDi : case AArch64 :: STPQi : case AArch64 :: STPWi : case AArch64 :: STPXi : case AArch64 :: STGPi : return true ; } } </s>

Returns whether the instruction is a paired load/store .


<s> void OrderedRegisterList :: insert ( unsigned VR ) { iterator L = llvm :: lower_bound ( Seq , VR , Ord ) ; if ( L == Seq . end ( ) ) Seq . push_back ( VR ) ; else Seq . insert ( L , VR ) ; unsigned S = Seq . size ( ) ; if ( S > MaxSize ) Seq . resize ( MaxSize ) ; assert ( Seq . size ( ) <= MaxSize ) ; } </s>

insert - Append entry to the vector if it does n't already exist .


<s>
void
NyuziInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
bool
destIsScalar
=
Nyuzi
::
GPR32RegClass
.
contains
(
DestReg
)
;
bool
srcIsScalar
=
Nyuzi
::
GPR32RegClass
.
contains
(
SrcReg
)
;
unsigned
operation
;
if
(
destIsScalar
&&
srcIsScalar
)
operation
=
Nyuzi
::
MOVESS
;
else
if
(
!
destIsScalar
&&
srcIsScalar
)
operation
=
Nyuzi
::
MOVEVSI
;
else
if
(
!
destIsScalar
&&
!
srcIsScalar
)
operation
=
Nyuzi
::
MOVEVV
;
else
llvm_unreachable
(
"unsupported physical reg copy type"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
operation
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>

Nyuzi
Nyuzi
Nyuzi::GPR32RegClass
Nyuzi::GPR32RegClass
Nyuzi::MOVESS
Nyuzi::MOVEVSI
Nyuzi::MOVEVV
"unsupported physical reg copy type"


aarch64
"%*sselected tune = %s\n"
""
"%*sselected arch = %s%s\n"
""


<s> void xstormy16_expand_call ( rtx retval , rtx dest , rtx counter ) { rtx call , temp ; machine_mode mode ; gcc_assert ( MEM_P ( dest ) ) ; dest = XEXP ( dest , 0 ) ; if ( ! CONSTANT_P ( dest ) && ! REG_P ( dest ) ) dest = force_reg ( Pmode , dest ) ; if ( retval == NULL ) mode = VOIDmode ; else mode = GET_MODE ( retval ) ; call = gen_rtx_CALL ( mode , gen_rtx_MEM ( FUNCTION_MODE , dest ) , counter ) ; if ( retval ) call = gen_rtx_SET ( retval , call ) ; if ( ! CONSTANT_P ( dest ) ) { temp = gen_reg_rtx ( HImode ) ; emit_move_insn ( temp , const0_rtx ) ; } else temp = const0_rtx ; call = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , call , gen_rtx_USE ( VOIDmode , temp ) ) ) ; emit_call_insn ( call ) ; } </s>

Expander for the ` call ' patterns . INDEX is the index of the switch statement . LOWER_BOUND is a CONST_INT that is the value of INDEX corresponding to the first table entry . RANGE is the number of table entries . TABLE is an ADDR_VEC that is the jump table . DEFAULT_LABEL is the address to branch to if INDEX is outside the range LOWER_BOUND to LOWER_BOUND+RANGE-1 .


<s> bool HexagonInstrInfo :: isComplex ( const MachineInstr * MI ) const { const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const TargetInstrInfo * TII = MF -> getSubtarget ( ) . getInstrInfo ( ) ; const HexagonInstrInfo * QII = ( const HexagonInstrInfo * ) TII ; if ( ! ( isTC1 ( MI ) ) && ! ( QII -> isTC2Early ( MI ) ) && ! ( MI -> getDesc ( ) . mayLoad ( ) ) && ! ( MI -> getDesc ( ) . mayStore ( ) ) && ( MI -> getDesc ( ) . getOpcode ( ) != Hexagon :: S2_allocframe ) && ( MI -> getDesc ( ) . getOpcode ( ) != Hexagon :: L2_deallocframe ) && ! ( QII -> isMemOp ( MI ) ) && ! ( MI -> isBranch ( ) ) && ! ( MI -> isReturn ( ) ) && ! MI -> isCall ( ) ) return true ; return false ; } </s>

Return whether the location is computed on the expression stack , meaning it can not be a simple register location .

Hexagon Hexagon Hexagon Hexagon Hexagon::S2_allocframe Hexagon::L2_deallocframe


<s> const MCInstrDesc & getDesc ( void ) const { return * MCID ; } </s>

Returns the target instruction descriptor of this MachineInstr .


"loadRegFromStackSlot didn't insert any code!"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s>
bool
X86ATTAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
const
Function
*
F
=
MF
.
getFunction
(
)
;
this
->
MF
=
&
MF
;
unsigned
CC
=
F
->
getCallingConv
(
)
;
SetupMachineFunction
(
MF
)
;
O
<<
"\n\n"
;
if
(
CC
==
CallingConv
::
X86_StdCall
||
CC
==
CallingConv
::
X86_FastCall
)
FunctionInfoMap
[
F
]
=
*
MF
.
getInfo
<
X86MachineFunctionInfo
>
(
)
;
EmitConstantPool
(
MF
.
getConstantPool
(
)
)
;
if
(
F
->
hasDLLExportLinkage
(
)
)
DLLExportedFns
.
insert
(
Mang
->
makeNameProper
(
F
->
getName
(
)
,
""
)
)
;
emitFunctionHeader
(
MF
)
;
if
(
TAI
->
doesSupportDebugInformation
(
)
||
TAI
->
doesSupportExceptionHandling
(
)
)
DW
->
BeginFunction
(
&
MF
)
;
bool
hasAnyRealCode
=
false
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
!
VerboseAsm
&&
(
I
->
pred_empty
(
)
||
I
->
isOnlyReachableByFallthrough
(
)
)
)
{
}
else
{
printBasicBlockLabel
(
I
,
true
,
true
,
VerboseAsm
)
;
O
<<
'\n'
;
}
for
(
MachineBasicBlock
::
const_iterator
II
=
I
->
begin
(
)
,
IE
=
I
->
end
(
)
;
II
!=
IE
;
++
II
)
{
if
(
!
II
->
isLabel
(
)
)
hasAnyRealCode
=
true
;
printMachineInstruction
(
II
)
;
}
}
if
(
Subtarget
->
isTargetDarwin
(
)
&&
!
hasAnyRealCode
)
{
O
<<
"\tnop\n"
;
}
if
(
TAI
->
hasDotTypeDotSizeDirective
(
)
)
O
<<
"\t.size\t"
<<
CurrentFnName
<<
", .-"
<<
CurrentFnName
<<
'\n'
;
if
(
TAI
->
doesSupportDebugInformation
(
)
)
DW
->
EndFunction
(
&
MF
)
;
EmitJumpTableInfo
(
MF
.
getJumpTableInfo
(
)
,
MF
)
;
O
.
flush
(
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> void EmitInstruction ( const MachineInstr * MI ) { printInstruction ( MI ) ; OutStreamer . AddBlankLine ( ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


"pointer offset from symbol maybe incorrect"


<s>
bool
MemSelOpt
::
processInstruction
(
MachineInstr
*
MI
)
{
bool
Changed
=
false
;
unsigned
NumOperands
=
MI
->
getNumOperands
(
)
;
if
(
NumOperands
==
0
)
return
false
;
const
TargetInstrDesc
&
TID
=
TII
->
get
(
MI
->
getOpcode
(
)
)
;
if
(
!
(
TID
.
isBranch
(
)
||
TID
.
isCall
(
)
||
TID
.
mayLoad
(
)
||
TID
.
mayStore
(
)
)
)
return
false
;
if
(
TID
.
isCall
(
)
)
{
PageChanged
=
1
;
CurBank
=
""
;
}
int
MemOpPos
=
1
;
int
BBOpPos
=
1
;
for
(
unsigned
i
=
0
;
i
<
NumOperands
;
i
++
)
{
MachineOperand
Op
=
MI
->
getOperand
(
i
)
;
if
(
Op
.
getType
(
)
==
MachineOperand
::
MO_GlobalAddress
||
Op
.
getType
(
)
==
MachineOperand
::
MO_ExternalSymbol
)
{
MemOpPos
=
i
;
}
if
(
Op
.
getType
(
)
==
MachineOperand
::
MO_MachineBasicBlock
)
{
BBOpPos
=
i
;
}
}
if
(
(
MemOpPos
==
1
)
&&
(
BBOpPos
==
1
)
)
return
false
;
assert
(
(
BBOpPos
!=
MemOpPos
)
&&
"operand can only be of one type"
)
;
if
(
(
MI
->
getOpcode
(
)
==
PIC16
::
CALL
)
)
{
MachineOperand
&
MemOp
=
MI
->
getOperand
(
MemOpPos
)
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
BuildMI
(
*
MBB
,
MI
,
dl
,
TII
->
get
(
PIC16
::
pagesel
)
)
.
addOperand
(
MemOp
)
;
return
true
;
}
if
(
MemOpPos
==
1
)
return
Changed
;
MachineOperand
&
Op
=
MI
->
getOperand
(
MemOpPos
)
;
std
::
string
NewBank
=
CurBank
;
bool
hasExternalLinkage
=
false
;
if
(
Op
.
getType
(
)
==
MachineOperand
::
MO_GlobalAddress
&&
Op
.
getGlobal
(
)
->
getType
(
)
->
getAddressSpace
(
)
==
PIC16ISD
::
RAM_SPACE
)
{
if
(
Op
.
getGlobal
(
)
->
hasExternalLinkage
(
)
)
hasExternalLinkage
=
true
;
NewBank
=
Op
.
getGlobal
(
)
->
getSection
(
)
;
}
else
if
(
Op
.
getType
(
)
==
MachineOperand
::
MO_ExternalSymbol
)
{
std
::
string
Sym
=
Op
.
getSymbolName
(
)
;
NewBank
=
PAN
::
getSectionNameForSym
(
Sym
)
;
}
if
(
NewBank
==
PAN
::
getSharedUDataSectionName
(
)
)
return
Changed
;
if
(
NewBank
.
compare
(
CurBank
)
!=
0
||
hasExternalLinkage
)
{
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
BuildMI
(
*
MBB
,
MI
,
dl
,
TII
->
get
(
PIC16
::
banksel
)
)
.
addOperand
(
Op
)
;
Changed
=
true
;
CurBank
=
NewBank
;
}
return
Changed
;
}
</s>

Process a single instruction and collect debug info anchors .


<s> BitVector MCS51RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( MCS51 :: R0 ) ; Reserved . set ( MCS51 :: R1 ) ; Reserved . set ( MCS51 :: R1R0 ) ; Reserved . set ( MCS51 :: SPL ) ; Reserved . set ( MCS51 :: SPH ) ; Reserved . set ( MCS51 :: SP ) ; Reserved . set ( MCS51 :: R28 ) ; Reserved . set ( MCS51 :: R29 ) ; Reserved . set ( MCS51 :: R29R28 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool rs6000_overloaded_builtin_p ( enum rs6000_builtins fncode ) { return ( rs6000_builtin_info [ ( int ) fncode ] . attr & RS6000_BTC_OVERLOADED ) != 0 ; } </s>

Return true if a builtin function is overloaded .


<s>
void
SystemZPostRASchedStrategy
::
leaveMBB
(
)
{
DEBUG
(
dbgs
(
)
<<
"+++ Leaving MBB#"
<<
MBB
->
getNumber
(
)
<<
"\n"
;
)
;
advanceTo
(
MBB
->
getFirstTerminator
(
)
)
;
}
</s>

Tell the strategy that current MBB is done .


<s> unsigned LM32RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getSubtargetImpl ( ) -> getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? LM32 :: RFP : LM32 :: RSP ; } </s>


<s> static void s390_register_info_set_ranges ( ) { int i , j ; for ( i = 0 ; i < 16 && cfun_gpr_save_slot ( i ) != SAVE_SLOT_STACK ; i ++ ) ; for ( j = 15 ; j > i && cfun_gpr_save_slot ( j ) != SAVE_SLOT_STACK ; j -- ) ; cfun_frame_layout . first_restore_gpr = ( i == 16 ) ? - 1 : i ; cfun_frame_layout . last_restore_gpr = ( i == 16 ) ? - 1 : j ; cfun_frame_layout . first_save_gpr = ( i == 16 ) ? - 1 : i ; cfun_frame_layout . last_save_gpr = ( i == 16 ) ? - 1 : j ; } </s>

Calculate the save and restore ranges for stm ( g ) and lm ( g ) in the prologue and epilogue .


<s> int getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { assert ( Ty -> isIntegerTy ( ) ) ; if ( Imm == 0 ) return TTI :: TCC_Free ; if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Basic ; if ( isInt < 21 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Basic ; if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) { if ( ( Imm . getSExtValue ( ) & 0xFFFF ) == 0 ) return TTI :: TCC_Basic ; return 2 * TTI :: TCC_Basic ; } return 4 * TTI :: TCC_Basic ; } </s>

Calculate the cost of materializing a 64-bit value .


"getImmOpValue expects only expressions or immediates"

getJumpTargetOpValue - Return binary encoding of the jump target operand .


"\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "


<s>
MCSection
*
XCoreTargetObjectFile
::
getSectionForConstant
(
const
DataLayout
&
DL
,
SectionKind
Kind
,
const
Constant
*
C
,
unsigned
&
Align
)
const
{
if
(
Kind
.
isMergeableConst4
(
)
)
return
MergeableConst4Section
;
if
(
Kind
.
isMergeableConst8
(
)
)
return
MergeableConst8Section
;
if
(
Kind
.
isMergeableConst16
(
)
)
return
MergeableConst16Section
;
assert
(
(
Kind
.
isReadOnly
(
)
||
Kind
.
isReadOnlyWithRel
(
)
)
&&
"Unknown section kind"
)
;
return
ReadOnlySection
;
}
</s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> void X86AsmParser :: EmitInstruction ( MCInst & Inst , OperandVector & Operands , MCStreamer & Out ) { Instrumentation -> InstrumentAndEmitInstruction ( Inst , Operands , getContext ( ) , MII , Out , getParser ( ) . shouldPrintSchedInfo ( ) ) ; } </s>


<s> char * function_builder :: finish_name ( ) { obstack_1grow ( & m_string_obstack , 0 ) ; return ( char * ) obstack_finish ( & m_string_obstack ) ; } </s>

Zero-terminate and complete the function name being built .


"Unknown opcode to check as cheap as a move!"

Return true if the instruction is as cheap as a move instruction .


"Recognize Hexagon-specific loop idioms"

getPassName - Return a nice clean name for a pass .


<s> bool AMDGPULowerKernelAttributes :: runOnModule ( Module & M ) { StringRef DispatchPtrName = Intrinsic :: getName ( Intrinsic :: amdgcn_dispatch_ptr ) ; Function * DispatchPtr = Mod -> getFunction ( DispatchPtrName ) ; if ( ! DispatchPtr ) return false ; bool MadeChange = false ; SmallPtrSet < Instruction * , 4 > HandledUses ; for ( auto * U : DispatchPtr -> users ( ) ) { CallInst * CI = cast < CallInst > ( U ) ; if ( HandledUses . insert ( CI ) . second ) { if ( processUse ( CI ) ) MadeChange = true ; } } return MadeChange ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> MachineBasicBlock :: iterator M68kFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { bool ReserveCallFrame = hasReservedCallFrame ( MF ) ; unsigned Opcode = I -> getOpcode ( ) ; bool IsDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! ReserveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t InternalAmt = ( IsDestroy && Amount ) ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! ReserveCallFrame ) { unsigned StackAlign = getStackAlignment ( ) ; Amount = alignTo ( Amount , StackAlign ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const auto & Fn = MF . getFunction ( ) ; bool DwarfCFI = MMI . hasDebugInfo ( ) || Fn . needsUnwindTableEntry ( ) ; bool HasDwarfEHHandlers = ! MF . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! IsDestroy && MF . getInfo < M68kMachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) { BuildCFI ( MBB , I , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; } if ( Amount == 0 ) return I ; Amount -= InternalAmt ; if ( IsDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) ) BuildCFI ( MBB , I , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ; int64_t StackAdjustment = IsDestroy ? Amount : - Amount ; int64_t CfaAdjustment = - StackAdjustment ; if ( StackAdjustment ) { StackAdjustment += mergeSPUpdates ( MBB , I , true ) ; StackAdjustment += mergeSPUpdates ( MBB , I , false ) ; if ( StackAdjustment ) { BuildStackAdjustment ( MBB , I , DL , StackAdjustment , false ) ; } } if ( DwarfCFI && ! hasFP ( MF ) ) { if ( CfaAdjustment ) { BuildCFI ( MBB , I , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , CfaAdjustment ) ) ; } } return I ; } if ( IsDestroy && InternalAmt ) { MachineBasicBlock :: iterator CI = I ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( CI != B && ! std :: prev ( CI ) -> isCall ( ) ) -- CI ; BuildStackAdjustment ( MBB , CI , DL , - InternalAmt , false ) ; } return I ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> void LC3RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { MachineInstr & MI = * II ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ; unsigned FI = FIOp . getIndex ( ) ; unsigned ImmOpIdx = 0 ; switch ( MI . getOpcode ( ) ) { default : return ; case LC3 :: LDR : case LC3 :: STR : ImmOpIdx = FIOperandNum + 1 ; break ; } MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ; int Offset = MFI -> getObjectOffset ( FI ) + MFI -> getStackSize ( ) + ImmOp . getImm ( ) ; FIOp . ChangeToRegister ( LC3 :: SP , false ) ; ImmOp . setImm ( Offset ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static rtx create_temp_reg_if_possible ( machine_mode mode , rtx default_reg ) { return can_create_pseudo_p ( ) ? gen_reg_rtx ( mode ) : default_reg ; } </s>

Create a temporary variable to hold a partial result , to enable CSE .


<s> virtual bool addInstSelector ( ) { addPass ( createPatmosISelDag ( getPatmosTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s>
static
void
recombine_lvx_pattern
(
rtx_insn
*
insn
,
del_info
*
to_delete
)
{
rtx
body
=
PATTERN
(
insn
)
;
gcc_assert
(
GET_CODE
(
body
)
==
SET
&&
GET_CODE
(
SET_SRC
(
body
)
)
==
VEC_SELECT
&&
GET_CODE
(
XEXP
(
SET_SRC
(
body
)
,
0
)
)
==
MEM
)
;
rtx
mem
=
XEXP
(
SET_SRC
(
body
)
,
0
)
;
rtx
base_reg
=
XEXP
(
mem
,
0
)
;
rtx
and_operation
=
find_alignment_op
(
insn
,
base_reg
)
;
if
(
and_operation
!=
0
)
{
df_ref
def
;
struct
df_insn_info
*
insn_info
=
DF_INSN_INFO_GET
(
insn
)
;
FOR_EACH_INSN_INFO_DEF
(
def
,
insn_info
)
{
struct
df_link
*
link
=
DF_REF_CHAIN
(
def
)
;
if
(
!
link
||
link
->
next
)
break
;
rtx_insn
*
swap_insn
=
DF_REF_INSN
(
link
->
ref
)
;
if
(
!
insn_is_swap_p
(
swap_insn
)
||
insn_is_load_p
(
swap_insn
)
||
insn_is_store_p
(
swap_insn
)
)
break
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace
=
true
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace_insn
=
swap_insn
;
XEXP
(
mem
,
0
)
=
and_operation
;
SET_SRC
(
body
)
=
mem
;
INSN_CODE
(
insn
)
=
1
;
df_insn_rescan
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"lvx opportunity found at %d\n"
,
INSN_UID
(
insn
)
)
;
}
}
}
</s>

If INSN is the load for an lvx pattern , put it in canonical form .


<s> int size ( ) const { return Chain . size ( ) ; } </s>

The number of name/type pairs is returned .


<s>
unsigned
getReg
(
)
const
{
assert
(
isRegBase
(
)
&&
"Invalid base register access!"
)
;
return
Base
.
Reg
;
}
</s>

Returns the register associated with this edge .


<s> static int rs6000_loop_align_max_skip ( rtx_insn * label ) { return ( 1 << rs6000_loop_align ( label ) ) - 1 ; } </s>


<s> MachineBasicBlock :: iterator eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const override { return MBB . erase ( MI ) ; } </s>


<s> bool XCoreInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return false ; if ( ! isUnpredicatedTerminator ( * I ) ) return false ; MachineInstr * LastInst = & * I ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { if ( IsBRU ( LastInst -> getOpcode ( ) ) ) { TBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } XCore :: CondCode BranchCode = GetCondFromBranchOpc ( LastInst -> getOpcode ( ) ) ; if ( BranchCode == XCore :: COND_INVALID ) return true ; TBB = LastInst -> getOperand ( 1 ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; Cond . push_back ( LastInst -> getOperand ( 0 ) ) ; return false ; } MachineInstr * SecondLastInst = & * I ; if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( * -- I ) ) return true ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; XCore :: CondCode BranchCode = GetCondFromBranchOpc ( SecondLastOpc ) ; if ( BranchCode != XCore :: COND_INVALID && IsBRU ( LastInst -> getOpcode ( ) ) ) { TBB = SecondLastInst -> getOperand ( 1 ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( 0 ) ) ; FBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } if ( IsBRU ( SecondLastInst -> getOpcode ( ) ) && IsBRU ( LastInst -> getOpcode ( ) ) ) { TBB = SecondLastInst -> getOperand ( 0 ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } if ( IsBR_JT ( SecondLastInst -> getOpcode ( ) ) && IsBRU ( LastInst -> getOpcode ( ) ) ) { I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return true ; } return true ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> static bool aarch_macro_fusion_pair_p ( rtx_insn * prev , rtx_insn * curr ) { rtx set_dest ; rtx prev_set = single_set ( prev ) ; rtx curr_set = single_set ( curr ) ; if ( ! prev_set || ! curr_set ) return false ; if ( any_condjump_p ( curr ) ) return false ; if ( ! arm_macro_fusion_p ( ) ) return false ; if ( current_tune -> fuseable_ops & ARM_FUSE_MOVW_MOVT ) { set_dest = SET_DEST ( curr_set ) ; if ( GET_MODE ( set_dest ) != SImode ) return false ; if ( GET_CODE ( set_dest ) == ZERO_EXTRACT ) { if ( CONST_INT_P ( SET_SRC ( curr_set ) ) && CONST_INT_P ( SET_SRC ( prev_set ) ) && REG_P ( XEXP ( set_dest , 0 ) ) && REG_P ( SET_DEST ( prev_set ) ) && REGNO ( XEXP ( set_dest , 0 ) ) == REGNO ( SET_DEST ( prev_set ) ) ) return true ; } else if ( GET_CODE ( SET_SRC ( curr_set ) ) == LO_SUM && REG_P ( SET_DEST ( curr_set ) ) && REG_P ( SET_DEST ( prev_set ) ) && GET_CODE ( SET_SRC ( prev_set ) ) == HIGH && REGNO ( SET_DEST ( curr_set ) ) == REGNO ( SET_DEST ( prev_set ) ) ) return true ; } return false ; } </s>

Implement TARGET_SCHED_MACRO_FUSION_PAIR_P . Return true if PREV and CURR should be kept together during scheduling .


<s> unsigned char AArch64Subtarget :: ClassifyGlobalReference ( const GlobalValue * GV , const TargetMachine & TM ) const { bool isDef = GV -> isStrongDefinitionForLinker ( ) ; if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) ) return AArch64II :: MO_GOT ; if ( TM . getCodeModel ( ) == CodeModel :: Small && GV -> hasExternalWeakLinkage ( ) ) { if ( TM . getRelocationModel ( ) == Reloc :: Static ) return AArch64II :: MO_CONSTPOOL ; else return AArch64II :: MO_GOT ; } if ( TM . getRelocationModel ( ) != Reloc :: Static && GV -> hasDefaultVisibility ( ) ) { if ( isTargetMachO ( ) ) return isDef ? AArch64II :: MO_NO_FLAG : AArch64II :: MO_GOT ; else return GV -> hasLocalLinkage ( ) ? AArch64II :: MO_NO_FLAG : AArch64II :: MO_GOT ; } return AArch64II :: MO_NO_FLAG ; } </s>

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be referenced for the current subtarget .


<s> unsigned SIInstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL , int * BytesAdded ) const { if ( ! FBB && Cond . empty ( ) ) { BuildMI ( & MBB , DL , get ( AMDGPU :: S_BRANCH ) ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded = ST . hasOffset3fBug ( ) ? 8 : 4 ; return 1 ; } if ( Cond . size ( ) == 1 && Cond [ 0 ] . isReg ( ) ) { BuildMI ( & MBB , DL , get ( AMDGPU :: SI_NON_UNIFORM_BRCOND_PSEUDO ) ) . add ( Cond [ 0 ] ) . addMBB ( TBB ) ; return 1 ; } assert ( TBB && Cond [ 0 ] . isImm ( ) ) ; unsigned Opcode = getBranchOpcode ( static_cast < BranchPredicate > ( Cond [ 0 ] . getImm ( ) ) ) ; if ( ! FBB ) { Cond [ 1 ] . isUndef ( ) ; MachineInstr * CondBr = BuildMI ( & MBB , DL , get ( Opcode ) ) . addMBB ( TBB ) ; preserveCondRegFlags ( CondBr -> getOperand ( 1 ) , Cond [ 1 ] ) ; fixImplicitOperands ( * CondBr ) ; if ( BytesAdded ) * BytesAdded = ST . hasOffset3fBug ( ) ? 8 : 4 ; return 1 ; } assert ( TBB && FBB ) ; MachineInstr * CondBr = BuildMI ( & MBB , DL , get ( Opcode ) ) . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( AMDGPU :: S_BRANCH ) ) . addMBB ( FBB ) ; MachineOperand & CondReg = CondBr -> getOperand ( 1 ) ; CondReg . setIsUndef ( Cond [ 1 ] . isUndef ( ) ) ; CondReg . setIsKill ( Cond [ 1 ] . isKill ( ) ) ; if ( BytesAdded ) * BytesAdded = ST . hasOffset3fBug ( ) ? 16 : 8 ; return 2 ; } </s>

Insert branch code into the end of the specified MachineBasicBlock .


<s>
bool
MipsAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNum
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
return
true
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNum
)
;
assert
(
MO
.
isReg
(
)
&&
"unexpected inline asm memory operand"
)
;
O
<<
"0($"
<<
MipsInstPrinter
::
getRegisterName
(
MO
.
getReg
(
)
)
<<
")"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .

Mips
Mips
0
"unexpected inline asm memory operand"
"0($"
Mips
")"


<s> bool AArch64FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s>
static
void
output_indirect_thunk
(
unsigned
int
regno
)
{
char
indirectlabel1
[
32
]
;
char
indirectlabel2
[
32
]
;
ASM_GENERATE_INTERNAL_LABEL
(
indirectlabel1
,
INDIRECT_LABEL
,
indirectlabelno
++
)
;
ASM_GENERATE_INTERNAL_LABEL
(
indirectlabel2
,
INDIRECT_LABEL
,
indirectlabelno
++
)
;
fputs
(
"\tcall\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
indirectlabel2
)
;
fputc
(
'\n'
,
asm_out_file
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
indirectlabel1
)
;
fprintf
(
asm_out_file
,
"\tpause\n\tlfence\n"
)
;
fputs
(
"\tjmp\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
indirectlabel1
)
;
fputc
(
'\n'
,
asm_out_file
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
indirectlabel2
)
;
if
(
flag_asynchronous_unwind_tables
&&
dwarf2out_do_frame
(
)
)
{
if
(
!
dwarf2out_do_cfi_asm
(
)
)
{
dw_cfi_ref
xcfi
=
ggc_cleared_alloc
<
dw_cfi_node
>
(
)
;
xcfi
->
dw_cfi_opc
=
DW_CFA_advance_loc4
;
xcfi
->
dw_cfi_oprnd1
.
dw_cfi_addr
=
ggc_strdup
(
indirectlabel2
)
;
vec_safe_push
(
cfun
->
fde
->
dw_fde_cfi
,
xcfi
)
;
}
dw_cfi_ref
xcfi
=
ggc_cleared_alloc
<
dw_cfi_node
>
(
)
;
xcfi
->
dw_cfi_opc
=
DW_CFA_def_cfa_offset
;
xcfi
->
dw_cfi_oprnd1
.
dw_cfi_offset
=
2
*
UNITS_PER_WORD
;
vec_safe_push
(
cfun
->
fde
->
dw_fde_cfi
,
xcfi
)
;
dwarf2out_emit_cfi
(
xcfi
)
;
}
if
(
regno
!=
INVALID_REGNUM
)
{
rtx
xops
[
2
]
;
xops
[
0
]
=
gen_rtx_MEM
(
word_mode
,
stack_pointer_rtx
)
;
xops
[
1
]
=
gen_rtx_REG
(
word_mode
,
regno
)
;
output_asm_insn
(
"mov\t{%1, %0|%0, %1}"
,
xops
)
;
}
else
{
rtx
xops
[
2
]
;
xops
[
0
]
=
stack_pointer_rtx
;
xops
[
1
]
=
plus_constant
(
Pmode
,
stack_pointer_rtx
,
UNITS_PER_WORD
)
;
output_asm_insn
(
"lea\t{%E1, %0|%0, %E1}"
,
xops
)
;
}
fputs
(
"\tret\n"
,
asm_out_file
)
;
if
(
(
ix86_harden_sls
&
harden_sls_return
)
)
fputs
(
"\tint3\n"
,
asm_out_file
)
;
}
</s>

Output a call and return thunk for indirect branch . If BND_P is true , the BND prefix is needed . If REGNO ! = -1 , the function address is in REGNO and the call and return thunk looks like : call L2 L1 : pause lfence jmp L1 L2 : mov % REG , ( % sp ) ret Otherwise , the function address is on the top of stack and the call and return thunk looks like : call L2 L1 : pause lfence jmp L1 L2 : lea WORD_SIZE ( % sp ) , % sp ret


<s> void P2TargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; } </s>

Lower the specified operand into the Ops vector .


"constant halfword load operand out of range"

Detect and error out on out-of-range constants for movhi .


<s>
static
bool
aarch64_rtx_costs_wrapper
(
rtx
x
,
int
code
,
int
outer
,
int
param
,
int
*
cost
,
bool
speed
)
{
bool
result
=
aarch64_rtx_costs
(
x
,
code
,
outer
,
param
,
cost
,
speed
)
;
if
(
dump_file
&&
(
dump_flags
&
TDF_DETAILS
)
)
{
print_rtl_single
(
dump_file
,
x
)
;
fprintf
(
dump_file
,
"\n%s cost: %d (%s)\n"
,
speed
"Hot"
:
"Cold"
,
*
cost
,
result
"final"
:
"partial"
)
;
}
return
result
;
}
</s>

Wrapper around aarch64_rtx_costs , dumps the partial , or total cost calculated for X . This cost is stored in * COST . Returns true if the total cost of X was calculated .

aarch64
"\n%s cost: %d (%s)\n"
"Hot"
"Cold"
"final"
"partial"


<s> void ARMHazardRecognizer :: AdvanceCycle ( ) { if ( FpMLxStalls && -- FpMLxStalls == 0 ) LastMI = 0 ; ScoreboardHazardRecognizer :: AdvanceCycle ( ) ; } </s>

AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled can not issue in the current cycle , either because of latency or resource conflicts .


"FPDelta isn't aligned per the Win64 ABI!"

"VLAs and dynamic stack realign, but no FP?!"

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> static void expand_small_movmem_or_setmem ( rtx destmem , rtx srcmem , rtx destptr , rtx srcptr , rtx value , rtx vec_value , rtx count , int size , rtx done_label , bool issetmem ) { rtx_code_label * label = ix86_expand_aligntest ( count , size , false ) ; machine_mode mode = mode_for_size ( size * BITS_PER_UNIT , MODE_INT , 1 ) ; rtx modesize ; int n ; if ( issetmem ) { if ( ! vec_value ) { if ( GET_MODE ( value ) == VOIDmode && size > 8 ) mode = Pmode ; else if ( GET_MODE_SIZE ( mode ) > GET_MODE_SIZE ( GET_MODE ( value ) ) ) mode = GET_MODE ( value ) ; } else mode = GET_MODE ( vec_value ) , value = vec_value ; } else { if ( size >= 32 ) mode = TARGET_AVX ? V32QImode : TARGET_SSE ? V16QImode : DImode ; else if ( size >= 16 ) mode = TARGET_SSE ? V16QImode : DImode ; srcmem = change_address ( srcmem , mode , srcptr ) ; } destmem = change_address ( destmem , mode , destptr ) ; modesize = GEN_INT ( GET_MODE_SIZE ( mode ) ) ; gcc_assert ( GET_MODE_SIZE ( mode ) <= size ) ; for ( n = 0 ; n * GET_MODE_SIZE ( mode ) < size ; n ++ ) { if ( issetmem ) emit_move_insn ( destmem , gen_lowpart ( mode , value ) ) ; else { emit_move_insn ( destmem , srcmem ) ; srcmem = offset_address ( srcmem , modesize , GET_MODE_SIZE ( mode ) ) ; } destmem = offset_address ( destmem , modesize , GET_MODE_SIZE ( mode ) ) ; } destmem = offset_address ( destmem , count , 1 ) ; destmem = offset_address ( destmem , GEN_INT ( - 2 * size ) , GET_MODE_SIZE ( mode ) ) ; if ( ! issetmem ) { srcmem = offset_address ( srcmem , count , 1 ) ; srcmem = offset_address ( srcmem , GEN_INT ( - 2 * size ) , GET_MODE_SIZE ( mode ) ) ; } for ( n = 0 ; n * GET_MODE_SIZE ( mode ) < size ; n ++ ) { if ( issetmem ) emit_move_insn ( destmem , gen_lowpart ( mode , value ) ) ; else { emit_move_insn ( destmem , srcmem ) ; srcmem = offset_address ( srcmem , modesize , GET_MODE_SIZE ( mode ) ) ; } destmem = offset_address ( destmem , modesize , GET_MODE_SIZE ( mode ) ) ; } emit_jump_insn ( gen_jump ( done_label ) ) ; emit_barrier ( ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; } </s>

Test if COUNT & SIZE is nonzero and if so , expand movme or setmem sequence that is valid for SIZE .. 2 * SIZE-1 bytes and jump to DONE_LABEL .


<s> bool MINA32AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { return false ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> static bool sh_cannot_copy_insn_p ( rtx_insn * insn ) { rtx pat ; if ( ! reload_completed || ! flag_pic ) return false ; if ( ! NONJUMP_INSN_P ( insn ) ) return false ; if ( asm_noperands ( insn ) >= 0 ) return false ; pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == CLOBBER || GET_CODE ( pat ) == USE ) return false ; if ( TARGET_FDPIC && GET_CODE ( pat ) == PARALLEL ) { rtx t = XVECEXP ( pat , 0 , XVECLEN ( pat , 0 ) - 1 ) ; if ( GET_CODE ( t ) == USE && unspec_caller_rtx_p ( XEXP ( t , 0 ) ) ) return true ; } if ( GET_CODE ( pat ) != SET ) return false ; pat = SET_SRC ( pat ) ; if ( unspec_caller_rtx_p ( pat ) ) return true ; return false ; } </s>

Indicate that INSN can not be duplicated . This is true for insn that generates a unique label .


<s> const char * AlphaTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case AlphaISD :: CVTQT_ : return "Alpha::CVTQT_" ; case AlphaISD :: CVTQS_ : return "Alpha::CVTQS_" ; case AlphaISD :: CVTTQ_ : return "Alpha::CVTTQ_" ; case AlphaISD :: GPRelHi : return "Alpha::GPRelHi" ; case AlphaISD :: GPRelLo : return "Alpha::GPRelLo" ; case AlphaISD :: RelLit : return "Alpha::RelLit" ; case AlphaISD :: GlobalRetAddr : return "Alpha::GlobalRetAddr" ; case AlphaISD :: CALL : return "Alpha::CALL" ; case AlphaISD :: DivCall : return "Alpha::DivCall" ; case AlphaISD :: RET_FLAG : return "Alpha::RET_FLAG" ; case AlphaISD :: COND_BRANCH_I : return "Alpha::COND_BRANCH_I" ; case AlphaISD :: COND_BRANCH_F : return "Alpha::COND_BRANCH_F" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> unsigned X86TTI :: getIntImmCost ( Intrinsic :: ID IID , unsigned Idx , const APInt & Imm , Type * Ty ) const { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return ~ 0U ; switch ( IID ) { default : return TCC_Free ; case Intrinsic :: sadd_with_overflow : case Intrinsic :: uadd_with_overflow : case Intrinsic :: ssub_with_overflow : case Intrinsic :: usub_with_overflow : case Intrinsic :: smul_with_overflow : case Intrinsic :: umul_with_overflow : if ( ( Idx == 1 ) && Imm . getBitWidth ( ) <= 64 && isInt < 32 > ( Imm . getSExtValue ( ) ) ) return TCC_Free ; break ; case Intrinsic :: experimental_stackmap : if ( ( Idx < 2 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TCC_Free ; break ; case Intrinsic :: experimental_patchpoint_void : case Intrinsic :: experimental_patchpoint_i64 : if ( ( Idx < 4 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TCC_Free ; break ; } return X86TTI :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> bool X86CallFrameOptimization :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; MRI = & MF . getRegInfo ( ) ; if ( ! isLegal ( MF ) ) return false ; unsigned FrameSetupOpcode = TII -> getCallFrameSetupOpcode ( ) ; bool Changed = false ; ContextMap CallSeqMap ; for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ++ I ) if ( I -> getOpcode ( ) == FrameSetupOpcode ) { CallContext & Context = CallSeqMap [ I ] ; collectCallInfo ( MF , * BB , I , Context ) ; } if ( ! isProfitable ( MF , CallSeqMap ) ) return false ; for ( auto CC : CallSeqMap ) if ( CC . second . UsePush ) Changed |= adjustCallSequence ( MF , CC . first , CC . second ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> static HOST_WIDE_INT nds32_constant_alignment ( const_tree constant , HOST_WIDE_INT basic_align ) { if ( ( ( TREE_CODE ( constant ) == STRING_CST || TREE_CODE ( constant ) == CONSTRUCTOR || TREE_CODE ( constant ) == UNION_TYPE || TREE_CODE ( constant ) == RECORD_TYPE || TREE_CODE ( constant ) == ARRAY_TYPE ) && basic_align < BITS_PER_WORD ) ) return BITS_PER_WORD ; else return basic_align ; } </s>


<s> unsigned PPCInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case PPC :: STD : case PPC :: STW : case PPC :: STFS : case PPC :: STFD : case PPC :: SPILL_CR : case PPC :: SPILL_CRBIT : case PPC :: STVX : case PPC :: SPILL_VRSAVE : if ( MI -> getOperand ( 1 ) . isImm ( ) && ! MI -> getOperand ( 1 ) . getImm ( ) && MI -> getOperand ( 2 ) . isFI ( ) ) { FrameIndex = MI -> getOperand ( 2 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( TM ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableSVEPostVec ) addPass ( createSVEPostVectorizePass ( ) ) ; if ( TM -> getTargetFeatureString ( ) . count ( "sve" ) ) addPass ( createSVEExpandLibCallPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( TM ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && LowerGatherScatterToInterleaved ) { addPass ( createEarlyCSEPass ( ) ) ; addPass ( createInterleavedGatherScatterPass ( TM ) ) ; addPass ( createInstructionCombiningPass ( ) ) ; } if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> const TargetRegisterClass * Thumb1RegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC ) const { if ( ARM :: tGPRRegClass . hasSubClassEq ( RC ) ) return & ARM :: tGPRRegClass ; return ARMBaseRegisterInfo :: getLargestLegalSuperClass ( RC ) ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .

ARM ARM::tGPRRegClass ARM::tGPRRegClass ARM


Generate a sequence of instructions to sign-extend an HI value into an SI value . Handles the tricky case where we are overwriting the destination . Return the number of bytes used by the emitted instructions . If RETURN_LENGTH is true then do not emit the assembly instruction sequence .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"ARM64 Instruction Selection"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool AMDGPUPassConfig :: addInstSelector ( ) { addPass ( createAMDGPUISelDag ( getAMDGPUTargetMachine ( ) ) ) ; const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . device ( ) -> getGeneration ( ) <= AMDGPUDeviceInfo :: HD6XXX ) { addPass ( createAMDGPUIndirectAddressingPass ( * TM ) ) ; } return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> const Cpu0InstrInfo * getInstrInfo ( ) { return getTargetMachine ( ) . getInstrInfo ( ) ; } </s>


<s> EVT SparcTargetLowering :: getSetCCResultType ( const DataLayout & , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


"CFGuard check mechanism only used on 32-bit X86"

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void frv_optimization_options ( int level , int size ATTRIBUTE_UNUSED ) { if ( level >= 2 ) { flag_schedule_insns_after_reload = 0 ; flag_rcsp = 1 ; } } </s>

On the FRV , possibly disable VLIW packing which is done by the 2nd scheduling pass at the current time .


"instruction requires a WASM feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> void sh_init_cumulative_args ( CUMULATIVE_ARGS * pcum , tree fntype , rtx libname ATTRIBUTE_UNUSED , tree fndecl , signed int n_named_args , enum machine_mode mode ) { pcum -> arg_count [ ( int ) SH_ARG_FLOAT ] = 0 ; pcum -> free_single_fp_reg = 0 ; pcum -> stack_regs = 0 ; pcum -> byref_regs = 0 ; pcum -> byref = 0 ; pcum -> outgoing = ( n_named_args == - 1 ) ? 0 : 1 ; pcum -> renesas_abi = sh_attr_renesas_p ( fntype ) ? 1 : 0 ; if ( fntype ) { pcum -> force_mem = ( ( TARGET_HITACHI || pcum -> renesas_abi ) && aggregate_value_p ( TREE_TYPE ( fntype ) , fndecl ) ) ; pcum -> prototype_p = TYPE_ARG_TYPES ( fntype ) ? TRUE : FALSE ; pcum -> arg_count [ ( int ) SH_ARG_INT ] = TARGET_SH5 && aggregate_value_p ( TREE_TYPE ( fntype ) , fndecl ) ; pcum -> call_cookie = CALL_COOKIE_RET_TRAMP ( TARGET_SHCOMPACT && pcum -> arg_count [ ( int ) SH_ARG_INT ] == 0 && ( TYPE_MODE ( TREE_TYPE ( fntype ) ) == BLKmode ? int_size_in_bytes ( TREE_TYPE ( fntype ) ) : GET_MODE_SIZE ( TYPE_MODE ( TREE_TYPE ( fntype ) ) ) ) > 4 && ( BASE_RETURN_VALUE_REG ( TYPE_MODE ( TREE_TYPE ( fntype ) ) ) == FIRST_RET_REG ) ) ; } else { pcum -> arg_count [ ( int ) SH_ARG_INT ] = 0 ; pcum -> prototype_p = FALSE ; if ( mode != VOIDmode ) { pcum -> call_cookie = CALL_COOKIE_RET_TRAMP ( TARGET_SHCOMPACT && GET_MODE_SIZE ( mode ) > 4 && BASE_RETURN_VALUE_REG ( mode ) == FIRST_RET_REG ) ; pcum -> force_mem = ( TARGET_DEFAULT & MASK_HITACHI ) && ( mode == BLKmode || ( GET_MODE_SIZE ( mode ) > 4 && ! ( mode == DFmode && TARGET_FPU_DOUBLE ) ) ) ; } else { pcum -> call_cookie = 0 ; pcum -> force_mem = FALSE ; } } } </s>

Initialize the CUMULATIVE_ARGS structure .


<s> int legitimate_pic_operand_p ( rtx x ) { if ( CONSTANT_P ( x ) && flag_pic && ( GET_CODE ( x ) == SYMBOL_REF || ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == SYMBOL_REF ) ) ) return 0 ; return 1 ; } </s>

Return true if OP is a legitimate general operand when generating PIC code . It is given that flag_pic is on and that OP satisfies CONSTANT_P or is a CONST_DOUBLE .


"Expecting an ACC register for BUILD_UACC."

Get a list of 'hint ' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg .


<s>
void
BPFDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
DEBUG
(
dbgs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;
return
;
}
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
SDIV
:
{
DebugLoc
Empty
;
const
DebugLoc
&
DL
=
Node
->
getDebugLoc
(
)
;
if
(
DL
!=
Empty
)
errs
(
)
<<
"Error at line "
<<
DL
.
getLine
(
)
<<
": "
;
else
errs
(
)
<<
"Error: "
;
errs
(
)
<<
"Unsupport signed division for DAG: "
;
Node
->
print
(
errs
(
)
,
CurDAG
)
;
errs
(
)
<<
"Please convert to unsigned div/mod.\n"
;
break
;
}
case
ISD
::
INTRINSIC_W_CHAIN
:
{
unsigned
IntNo
=
cast
<
ConstantSDNode
>
(
Node
->
getOperand
(
1
)
)
->
getZExtValue
(
)
;
switch
(
IntNo
)
{
case
Intrinsic
::
bpf_load_byte
:
case
Intrinsic
::
bpf_load_half
:
case
Intrinsic
::
bpf_load_word
:
{
SDLoc
DL
(
Node
)
;
SDValue
Chain
=
Node
->
getOperand
(
0
)
;
SDValue
N1
=
Node
->
getOperand
(
1
)
;
SDValue
Skb
=
Node
->
getOperand
(
2
)
;
SDValue
N3
=
Node
->
getOperand
(
3
)
;
SDValue
R6Reg
=
CurDAG
->
getRegister
(
BPF
::
R6
,
MVT
::
i64
)
;
Chain
=
CurDAG
->
getCopyToReg
(
Chain
,
DL
,
R6Reg
,
Skb
,
SDValue
(
)
)
;
Node
=
CurDAG
->
UpdateNodeOperands
(
Node
,
Chain
,
N1
,
R6Reg
,
N3
)
;
break
;
}
}
break
;
}
case
ISD
::
FrameIndex
:
{
int
FI
=
cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
EVT
VT
=
Node
->
getValueType
(
0
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
VT
)
;
unsigned
Opc
=
BPF
::
MOV_rr
;
if
(
Node
->
hasOneUse
(
)
)
{
CurDAG
->
SelectNodeTo
(
Node
,
Opc
,
VT
,
TFI
)
;
return
;
}
ReplaceNode
(
Node
,
CurDAG
->
getMachineNode
(
Opc
,
SDLoc
(
Node
)
,
VT
,
TFI
)
)
;
return
;
}
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> SDValue AMDGPUTargetLowering :: SplitVectorLoad ( const SDValue Op , SelectionDAG & DAG ) const { LoadSDNode * Load = cast < LoadSDNode > ( Op ) ; EVT VT = Op . getValueType ( ) ; if ( VT . getVectorNumElements ( ) == 2 ) return scalarizeVectorLoad ( Load , DAG ) ; SDValue BasePtr = Load -> getBasePtr ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; SDLoc SL ( Op ) ; const MachinePointerInfo & SrcValue = Load -> getMemOperand ( ) -> getPointerInfo ( ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Op , SL , LoVT , HiVT ) ; unsigned Size = LoMemVT . getStoreSize ( ) ; unsigned BaseAlign = Load -> getAlignment ( ) ; unsigned HiAlign = MinAlign ( BaseAlign , Size ) ; SDValue LoLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , LoVT , Load -> getChain ( ) , BasePtr , SrcValue , LoMemVT , BaseAlign , Load -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue HiPtr = DAG . getObjectPtrOffset ( SL , BasePtr , Size ) ; SDValue HiLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , HiVT , Load -> getChain ( ) , HiPtr , SrcValue . getWithOffset ( LoMemVT . getStoreSize ( ) ) , HiMemVT , HiAlign , Load -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Ops [ ] = { DAG . getNode ( ISD :: CONCAT_VECTORS , SL , VT , LoLoad , HiLoad ) , DAG . getNode ( ISD :: TokenFactor , SL , MVT :: Other , LoLoad . getValue ( 1 ) , HiLoad . getValue ( 1 ) ) } ; return DAG . getMergeValues ( Ops , SL ) ; } </s>

Split a vector load into 2 loads of half the vector .


<s> bool MipsBranchExpansion :: runOnMachineFunction ( MachineFunction & MF ) { const TargetMachine & TM = MF . getTarget ( ) ; IsPIC = TM . isPositionIndependent ( ) ; ABI = static_cast < const MipsTargetMachine & > ( TM ) . getABI ( ) ; STI = & static_cast < const MipsSubtarget & > ( MF . getSubtarget ( ) ) ; TII = static_cast < const MipsInstrInfo * > ( STI -> getInstrInfo ( ) ) ; if ( IsPIC && ABI . IsO32 ( ) && MF . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( MF , TII ) ; MFp = & MF ; ForceLongBranchFirstPass = ForceLongBranch ; bool longBranchChanged = handlePossibleLongBranch ( ) ; bool forbiddenSlotChanged = handleForbiddenSlot ( ) ; bool Changed = longBranchChanged || forbiddenSlotChanged ; while ( forbiddenSlotChanged ) { longBranchChanged = handlePossibleLongBranch ( ) ; if ( ! longBranchChanged ) break ; forbiddenSlotChanged = handleForbiddenSlot ( ) ; } return Changed ; } </s>


<s> unsigned getNumFixupKinds ( ) const override { return ARM :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> bool HexagonInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & MBB , unsigned NumCyles , unsigned ExtraPredCycles , const BranchProbability & Probability ) const { return true ; } </s>


<s> void R600TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { switch ( N -> getOpcode ( ) ) { default : AMDGPUTargetLowering :: ReplaceNodeResults ( N , Results , DAG ) ; return ; case ISD :: FP_TO_UINT : if ( N -> getValueType ( 0 ) == MVT :: i1 ) { Results . push_back ( lowerFP_TO_UINT ( N -> getOperand ( 0 ) , DAG ) ) ; return ; } LLVM_FALLTHROUGH ; case ISD :: FP_TO_SINT : { if ( N -> getValueType ( 0 ) == MVT :: i1 ) { Results . push_back ( lowerFP_TO_SINT ( N -> getOperand ( 0 ) , DAG ) ) ; return ; } SDValue Result ; if ( expandFP_TO_SINT ( N , Result , DAG ) ) Results . push_back ( Result ) ; return ; } case ISD :: SDIVREM : { SDValue Op = SDValue ( N , 1 ) ; SDValue RES = LowerSDIVREM ( Op , DAG ) ; Results . push_back ( RES ) ; Results . push_back ( RES . getValue ( 1 ) ) ; break ; } case ISD :: UDIVREM : { SDValue Op = SDValue ( N , 0 ) ; LowerUDIVREM64 ( Op , DAG , Results ) ; break ; } } } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


"Code generation for MIPS-I is not implemented"

"Code generation for MIPS-V is not implemented"

"MSA requires a 64-bit FPU register file (FR=1 mode). "

"-mattr=+nooddspreg requires the O32 ABI."

"FPXX is not permitted for the N32/N64 ABI's."

"position-independent code requires '-mabicalls'"

"warning: cannot use small-data accesses for '-mabicalls'"

This constructor initializes the data members to match that of the specified triple .


<s>
void
SIInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
SIMachineFunctionInfo
*
MFI
=
MF
->
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MachineFrameInfo
&
FrameInfo
=
MF
->
getFrameInfo
(
)
;
const
DebugLoc
&
DL
=
MBB
.
findDebugLoc
(
MI
)
;
unsigned
Size
=
FrameInfo
.
getObjectSize
(
FrameIndex
)
;
unsigned
Align
=
FrameInfo
.
getObjectAlignment
(
FrameIndex
)
;
MachinePointerInfo
PtrInfo
=
MachinePointerInfo
::
getFixedStack
(
*
MF
,
FrameIndex
)
;
MachineMemOperand
*
MMO
=
MF
->
getMachineMemOperand
(
PtrInfo
,
MachineMemOperand
::
MOStore
,
Size
,
Align
)
;
unsigned
SpillSize
=
TRI
->
getSpillSize
(
*
RC
)
;
if
(
RI
.
isSGPRClass
(
RC
)
)
{
MFI
->
setHasSpilledSGPRs
(
)
;
const
MCInstrDesc
&
OpDesc
=
get
(
getSGPRSpillSaveOpcode
(
SpillSize
)
)
;
if
(
TargetRegisterInfo
::
isVirtualRegister
(
SrcReg
)
&&
SpillSize
==
4
)
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
MRI
.
constrainRegClass
(
SrcReg
,
&
AMDGPU
::
SReg_32_XM0RegClass
)
;
}
MachineInstrBuilder
Spill
=
BuildMI
(
MBB
,
MI
,
DL
,
OpDesc
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIndex
)
.
addMemOperand
(
MMO
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
,
RegState
::
Implicit
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
,
RegState
::
Implicit
)
;
if
(
RI
.
spillSGPRToVGPR
(
)
)
FrameInfo
.
setStackID
(
FrameIndex
,
TargetStackID
::
SGPRSpill
)
;
if
(
ST
.
hasScalarStores
(
)
)
{
Spill
.
addReg
(
AMDGPU
::
M0
,
RegState
::
ImplicitDefine
|
RegState
::
Dead
)
;
}
return
;
}
assert
(
RI
.
hasVGPRs
(
RC
)
&&
"Only VGPR spilling expected"
)
;
unsigned
Opcode
=
getVGPRSpillSaveOpcode
(
SpillSize
)
;
MFI
->
setHasSpilledVGPRs
(
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opcode
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIndex
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> const MCPhysReg * MMIXRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_SaveList ; } </s>


"Module has aliases, which NVPTX does not support."

"Module has a nontrivial global ctor, which NVPTX does not support."

"Module has a nontrivial global dtor, which NVPTX does not support."

Set up the AsmPrinter when we are working on a new module .


<s> bool SystemZElimCompare :: processBlock ( MachineBasicBlock & MBB ) { bool Changed = false ; LivePhysRegs LiveRegs ( * TRI ) ; LiveRegs . addLiveOuts ( MBB ) ; bool CompleteCCUsers = ! LiveRegs . contains ( SystemZ :: CC ) ; SmallVector < MachineInstr * , 4 > CCUsers ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; while ( MBBI != MBB . begin ( ) ) { MachineInstr & MI = * -- MBBI ; if ( CompleteCCUsers && ( MI . isCompare ( ) || isLoadAndTestAsCmp ( MI ) ) && ( optimizeCompareZero ( MI , CCUsers ) || fuseCompareOperations ( MI , CCUsers ) ) ) { ++ MBBI ; MI . eraseFromParent ( ) ; Changed = true ; CCUsers . clear ( ) ; continue ; } if ( MI . definesRegister ( SystemZ :: CC ) ) { CCUsers . clear ( ) ; CompleteCCUsers = true ; } if ( MI . readsRegister ( SystemZ :: CC ) && CompleteCCUsers ) CCUsers . push_back ( & MI ) ; } return Changed ; } </s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .

SystemZ SystemZ SystemZ::CC 4 SystemZ::CC SystemZ::CC


<s> bool TeakPassConfig :: addPreISel ( ) { addPass ( createHardwareLoopsPass ( ) ) ; return false ; } </s>


"  Found lowered global address with one use: "

runOnMachineFunction - Emit the function body .


<s> unsigned getCSRFirstUseCost ( ) const { return 5 ; } </s>

Allow the target to override the cost of using a callee-saved register for the first time .


<s> BitVector RV16KRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , RV16K :: X0 ) ; markSuperRegs ( Reserved , RV16K :: X1 ) ; markSuperRegs ( Reserved , RV16K :: X2 ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> size_t addString ( StringRef S ) { return StringTable . addString ( S ) ; } </s>


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { if ( Inst . getNumOperands ( ) == 0 ) return false ; if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ 0 ] . OperandType == MCOI :: OPERAND_PCREL ) { int64_t Imm = Inst . getOperand ( 0 ) . getImm ( ) ; Target = Addr + Size + Imm ; return true ; } else { int64_t Imm = Inst . getOperand ( 0 ) . getImm ( ) ; if ( Imm == 0 ) return false ; Target = Imm ; return true ; } } </s>

Given a branch instruction try to get the address the branch targets .


<s> static machine_mode spu_addr_space_pointer_mode ( addr_space_t addrspace ) { switch ( addrspace ) { case ADDR_SPACE_GENERIC : return ptr_mode ; case ADDR_SPACE_EA : return EAmode ; default : gcc_unreachable ( ) ; } } </s>

Return the appropriate mode for a named address pointer .


<s> bool runOnModule ( Module & M ) override { SetVector < Function * > Functions ; AnalysisGetter AG ; for ( Function & F : M ) { if ( ! F . isIntrinsic ( ) ) Functions . insert ( & F ) ; } CallGraphUpdater CGUpdater ; BumpPtrAllocator Allocator ; AMDGPUInformationCache InfoCache ( M , AG , Allocator , nullptr , * TM ) ; Attributor A ( Functions , InfoCache , CGUpdater ) ; for ( Function & F : M ) { if ( ! F . isIntrinsic ( ) ) { A . getOrCreateAAFor < AAAMDAttributes > ( IRPosition :: function ( F ) ) ; A . getOrCreateAAFor < AAAMDWorkGroupSize > ( IRPosition :: function ( F ) ) ; } } ChangeStatus Change = A . run ( ) ; return Change == ChangeStatus :: CHANGED ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .