<s>
void
PPCAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
if
(
MI
->
getOpcode
(
)
==
PPC
::
RLWINM
)
{
unsigned
char
SH
=
MI
->
getOperand
(
2
)
.
getImm
(
)
;
unsigned
char
MB
=
MI
->
getOperand
(
3
)
.
getImm
(
)
;
unsigned
char
ME
=
MI
->
getOperand
(
4
)
.
getImm
(
)
;
bool
useSubstituteMnemonic
=
false
;
if
(
SH
<=
31
&&
MB
==
0
&&
ME
==
(
31
SH
)
)
{
O
<<
"\tslwi "
;
useSubstituteMnemonic
=
true
;
}
if
(
SH
<=
31
&&
MB
==
(
32
SH
)
&&
ME
==
31
)
{
O
<<
"\tsrwi "
;
useSubstituteMnemonic
=
true
;
SH
=
32
SH
;
}
if
(
useSubstituteMnemonic
)
{
printOperand
(
MI
,
0
)
;
O
<<
", "
;
printOperand
(
MI
,
1
)
;
O
<<
", "
<<
(
unsigned
int
)
SH
;
OutStreamer
.
AddBlankLine
(
)
;
return
;
}
}
if
(
(
MI
->
getOpcode
(
)
==
PPC
::
OR
||
MI
->
getOpcode
(
)
==
PPC
::
OR8
)
&&
MI
->
getOperand
(
1
)
.
getReg
(
)
==
MI
->
getOperand
(
2
)
.
getReg
(
)
)
{
O
<<
"\tmr "
;
printOperand
(
MI
,
0
)
;
O
<<
", "
;
printOperand
(
MI
,
1
)
;
OutStreamer
.
AddBlankLine
(
)
;
return
;
}
if
(
MI
->
getOpcode
(
)
==
PPC
::
RLDICR
)
{
unsigned
char
SH
=
MI
->
getOperand
(
2
)
.
getImm
(
)
;
unsigned
char
ME
=
MI
->
getOperand
(
3
)
.
getImm
(
)
;
if
(
63
SH
==
ME
)
{
O
<<
"\tsldi "
;
printOperand
(
MI
,
0
)
;
O
<<
", "
;
printOperand
(
MI
,
1
)
;
O
<<
", "
<<
(
unsigned
int
)
SH
;
OutStreamer
.
AddBlankLine
(
)
;
return
;
}
}
printInstruction
(
MI
)
;
OutStreamer
.
AddBlankLine
(
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> virtual bool isFMAFasterThanFMulAndFAdd ( EVT VT ) const { return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> static int ix86_function_regparm ( const_tree type , const_tree decl ) { tree attr ; int regparm ; unsigned int ccvt ; if ( TARGET_64BIT ) return ( ix86_function_type_abi ( type ) == SYSV_ABI ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX ) ; ccvt = ix86_get_callcvt ( type ) ; regparm = ix86_regparm ; if ( ( ccvt & IX86_CALLCVT_REGPARM ) != 0 ) { attr = lookup_attribute ( "regparm" , TYPE_ATTRIBUTES ( type ) ) ; if ( attr ) { regparm = TREE_INT_CST_LOW ( TREE_VALUE ( TREE_VALUE ( attr ) ) ) ; return regparm ; } } else if ( ( ccvt & IX86_CALLCVT_FASTCALL ) != 0 ) return 2 ; else if ( ( ccvt & IX86_CALLCVT_THISCALL ) != 0 ) return 1 ; if ( decl && TREE_CODE ( decl ) == FUNCTION_DECL ) { cgraph_node * target = cgraph_node :: get ( decl ) ; if ( target ) target = target -> function_symbol ( ) ; if ( target && opt_for_fn ( target -> decl , optimize ) && ! ( profile_flag && ! flag_fentry ) ) { if ( target -> local && target -> can_change_signature ) { int local_regparm , globals = 0 , regno ; for ( local_regparm = 0 ; local_regparm < REGPARM_MAX ; local_regparm ++ ) if ( fixed_regs [ local_regparm ] ) break ; if ( local_regparm == 3 && DECL_STATIC_CHAIN ( target -> decl ) ) local_regparm = 2 ; if ( flag_split_stack ) { if ( local_regparm == 3 ) local_regparm = 2 ; else if ( local_regparm == 2 && DECL_STATIC_CHAIN ( target -> decl ) ) local_regparm = 1 ; } for ( regno = AX_REG ; regno <= DI_REG ; regno ++ ) if ( fixed_regs [ regno ] ) globals ++ ; local_regparm = globals < local_regparm ? local_regparm - globals : 0 ; if ( local_regparm > regparm ) regparm = local_regparm ; } } } return regparm ; } </s>

Return the regparm value for a function with the indicated TYPE and DECL . DECL may be NULL when calling function indirectly or considering a libcall .


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , DebugLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { if ( Subtarget -> isTargetNaCl ( ) || ! Subtarget -> isAAPCS_ABI ( ) || Subtarget -> isTargetDarwin ( ) ) return SDValue ( ) ; const ARMTargetLowering & TLI = * static_cast < const ARMTargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Type * IntPtrTy = TLI . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( MVT :: i32 ) ) Src = DAG . getNode ( ISD :: TRUNCATE , dl , MVT :: i32 , Src ) ; else Src = DAG . getNode ( ISD :: ZERO_EXTEND , dl , MVT :: i32 , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , 0 , TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , false , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } </s>

Emit target-specific code that performs a memset .


<s> bool RV16KTargetLowering :: IsEligibleForTailCallOptimization ( CCState & CCInfo , CallLoweringInfo & CLI , MachineFunction & MF , const SmallVector < CCValAssign , 16 > & ArgLocs ) const { auto & Callee = CLI . Callee ; auto CalleeCC = CLI . CallConv ; auto IsVarArg = CLI . IsVarArg ; auto & Outs = CLI . Outs ; auto & Caller = MF . getFunction ( ) ; auto CallerCC = Caller . getCallingConv ( ) ; if ( Caller . getFnAttribute ( "disable-tail-calls" ) . getValueAsString ( ) == "true" ) return false ; if ( IsVarArg ) return false ; if ( CCInfo . getNextStackOffset ( ) != 0 ) return false ; auto IsCallerStructRet = Caller . hasStructRetAttr ( ) ; auto IsCalleeStructRet = Outs . empty ( ) ? false : Outs [ 0 ] . Flags . isSRet ( ) ; if ( IsCallerStructRet || IsCalleeStructRet ) return false ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; if ( GV -> hasExternalWeakLinkage ( ) ) return false ; } const RV16KRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( CalleeCC != CallerCC ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } for ( auto & Arg : Outs ) if ( Arg . Flags . isByVal ( ) ) return false ; return true ; } </s>

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization .


<s>
void
X86AsmBackend
::
relaxInstruction
(
const
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
,
MCInst
&
Res
)
const
{
bool
is16BitMode
=
STI
.
getFeatureBits
(
)
[
X86
::
Mode16Bit
]
;
unsigned
RelaxedOp
=
getRelaxedOpcode
(
Inst
,
is16BitMode
)
;
if
(
RelaxedOp
==
Inst
.
getOpcode
(
)
)
{
SmallString
<
256
>
Tmp
;
raw_svector_ostream
OS
(
Tmp
)
;
Inst
.
dump_pretty
(
OS
)
;
OS
<<
"\n"
;
report_fatal_error
(
"unexpected instruction to relax: "
+
OS
.
str
(
)
)
;
}
Res
=
Inst
;
Res
.
setOpcode
(
RelaxedOp
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> int getLength ( ) { return length ; } </s>

Return the number of bytes of data in this stream .


<s> bool n9_2r1w_consumed_by_ex_dep_p ( rtx_insn * consumer , rtx def_reg ) { rtx use_rtx ; switch ( get_attr_type ( consumer ) ) { case TYPE_ALU : if ( movd44_even_dep_p ( consumer , def_reg ) ) return true ; use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_PBSAD : case TYPE_MUL : use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_ALU_SHIFT : use_rtx = extract_shift_reg ( consumer ) ; break ; case TYPE_PBSADA : return pbsada_insn_ra_rb_dep_reg_p ( consumer , def_reg ) ; case TYPE_MAC : use_rtx = PATTERN ( consumer ) ; break ; case TYPE_DIV : if ( INSN_CODE ( consumer ) == CODE_FOR_divmodsi4 || INSN_CODE ( consumer ) == CODE_FOR_udivmodsi4 ) use_rtx = SET_SRC ( parallel_element ( consumer , 0 ) ) ; else use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_MMU : if ( GET_CODE ( PATTERN ( consumer ) ) == SET ) use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; else return true ; break ; case TYPE_LOAD : if ( post_update_insn_p ( consumer ) ) use_rtx = extract_base_reg ( consumer ) ; else use_rtx = extract_mem_rtx ( consumer ) ; break ; case TYPE_STORE : if ( post_update_insn_p ( consumer ) ) use_rtx = extract_base_reg ( consumer ) ; else use_rtx = extract_mem_rtx ( consumer ) ; if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; if ( ! post_update_insn_p ( consumer ) && ! immed_offset_p ( extract_mem_rtx ( consumer ) ) ) return false ; use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_LOAD_MULTIPLE : use_rtx = extract_base_reg ( consumer ) ; break ; case TYPE_STORE_MULTIPLE : use_rtx = extract_base_reg ( consumer ) ; if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; use_rtx = extract_nth_access_rtx ( consumer , 0 ) ; break ; case TYPE_BRANCH : use_rtx = PATTERN ( consumer ) ; break ; default : gcc_unreachable ( ) ; } if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; return false ; } </s>

Check the dependency between the producer defining DEF_REG and CONSUMER requiring input operand at EX .


"Copy one register into another with a different width"


<s> void X86PassConfig :: addPreEmitPass2 ( ) { addPass ( createX86RetpolineThunksPass ( ) ) ; const Triple & TT = TM -> getTargetTriple ( ) ; if ( ! TT . isOSDarwin ( ) && ! TT . isOSWindows ( ) ) addPass ( createCFIInstrInserter ( ) ) ; } </s>

Targets may add passes immediately before machine code is emitted in this callback .


<s> rtx mips_pic_base_register ( rtx temp ) { if ( ! TARGET_MIPS16 ) return pic_offset_table_rtx ; if ( currently_expanding_to_rtl ) return mips16_gp_pseudo_reg ( ) ; if ( can_create_pseudo_p ( ) ) temp = gen_reg_rtx ( Pmode ) ; if ( TARGET_USE_GOT ) mips_emit_move ( temp , pic_offset_table_rtx ) ; else emit_insn ( gen_load_const_gp ( temp ) ) ; return temp ; } </s>

Return a base register that holds pic_offset_table_rtx . TEMP , if nonnull , is a scratch Pmode base register .


<s> DecodeStatus BPFDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & VStream , raw_ostream & CStream ) const { bool IsLittleEndian = getContext ( ) . getAsmInfo ( ) -> isLittleEndian ( ) ; uint64_t Insn , Hi ; DecodeStatus Result ; Result = readInstruction64 ( Bytes , Address , Size , Insn , IsLittleEndian ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTableBPF64 , Instr , Insn , Address , this , STI ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; switch ( Instr . getOpcode ( ) ) { case BPF :: LD_imm64 : { if ( Bytes . size ( ) < 16 ) { Size = 0 ; return MCDisassembler :: Fail ; } Size = 16 ; if ( IsLittleEndian ) Hi = ( Bytes [ 12 ] << 0 ) | ( Bytes [ 13 ] << 8 ) | ( Bytes [ 14 ] << 16 ) | ( Bytes [ 15 ] << 24 ) ; else Hi = ( Bytes [ 12 ] << 24 ) | ( Bytes [ 13 ] << 16 ) | ( Bytes [ 14 ] << 8 ) | ( Bytes [ 15 ] << 0 ) ; auto & Op = Instr . getOperand ( 1 ) ; Op . setImm ( Make_64 ( Hi , Op . getImm ( ) ) ) ; break ; } case BPF :: LD_ABS_B : case BPF :: LD_ABS_H : case BPF :: LD_ABS_W : case BPF :: LD_IND_B : case BPF :: LD_IND_H : case BPF :: LD_IND_W : { auto Op = Instr . getOperand ( 0 ) ; Instr . clear ( ) ; Instr . addOperand ( MCOperand :: createReg ( BPF :: R6 ) ) ; Instr . addOperand ( Op ) ; break ; } } return Result ; } </s>

Returns the disassembly of a single instruction .


<s> rtx rs6000_gen_le_vsx_permute ( rtx source , machine_mode mode ) { if ( FLOAT128_VECTOR_P ( mode ) || mode == TImode ) return gen_rtx_ROTATE ( mode , source , GEN_INT ( 64 ) ) ; else { rtx par = gen_rtx_PARALLEL ( VOIDmode , rs6000_const_vec ( mode ) ) ; return gen_rtx_VEC_SELECT ( mode , source , par ) ; } } </s>

Generate a permute rtx that represents an lxvd2x , stxvd2x , or xxpermdi for a VSX load or store operation .


<s> void ARMPassConfig :: addIRPasses ( ) { if ( getARMSubtarget ( ) . isTargetNaCl ( ) ) addPass ( createInsertDivideCheckPass ( ) ) ; addPass ( createAtomicExpandLoadLinkedPass ( TM ) ) ; const ARMSubtarget * Subtarget = & getARMSubtarget ( ) ; if ( Subtarget -> hasAnyDataBarrier ( ) && ! Subtarget -> isThumb1Only ( ) ) if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> bool HexagonTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , Align Alignment , MachineMemOperand :: Flags Flags , bool * Fast ) const { MVT SVT = VT . getSimpleVT ( ) ; if ( Subtarget . isHVXVectorType ( SVT , true ) ) return allowsHvxMisalignedMemoryAccesses ( SVT , Flags , Fast ) ; if ( Fast ) * Fast = false ; return false ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> const TargetRegisterClass * SNESRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & SNES :: MainRegsRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> static void print_csky_value ( FILE * f , rtx x ) { switch ( GET_CODE ( x ) ) { case CONST_INT : fprintf ( f , HOST_WIDE_INT_PRINT_HEX , INTVAL ( x ) ) ; return ; case CONST_DOUBLE : fprintf ( f , "<0x%lx,0x%lx>" , ( long ) XWINT ( x , 2 ) , ( long ) XWINT ( x , 3 ) ) ; return ; case CONST_VECTOR : { int i ; fprintf ( f , "<" ) ; for ( i = 0 ; i < CONST_VECTOR_NUNITS ( x ) ; i ++ ) { fprintf ( f , HOST_WIDE_INT_PRINT_HEX , INTVAL ( CONST_VECTOR_ELT ( x , i ) ) ) ; if ( i < ( CONST_VECTOR_NUNITS ( x ) - 1 ) ) fputc ( ',' , f ) ; } fprintf ( f , ">" ) ; } return ; case CONST_STRING : fprintf ( f , "\"%s\"" , XSTR ( x , 0 ) ) ; return ; case SYMBOL_REF : fprintf ( f , "`%s'" , XSTR ( x , 0 ) ) ; return ; case LABEL_REF : fprintf ( f , "L%d" , INSN_UID ( XEXP ( x , 0 ) ) ) ; return ; case CONST : print_csky_value ( f , XEXP ( x , 0 ) ) ; return ; case PLUS : print_csky_value ( f , XEXP ( x , 0 ) ) ; fprintf ( f , "+" ) ; print_csky_value ( f , XEXP ( x , 1 ) ) ; return ; case PC : fprintf ( f , "pc" ) ; return ; default : fprintf ( f , "????" ) ; return ; } } </s>

Print a symbolic form of the constant X to the dump file F. This is used for dump output for -mconstpool in the target-dependent reorg pass .


<s>
unsigned
getSubReg
(
)
const
{
assert
(
isReg
(
)
&&
"Wrong CountValue accessor"
)
;
return
Contents
.
R
.
Sub
;
}
</s>

Returns the physical register number of sub-register `` Index '' for physical register RegNo .


<s>
void
AVRAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
)
const
{
if
(
Value
==
0
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
auto
NumBits
=
Info
.
TargetSize
+
Info
.
TargetOffset
;
auto
NumBytes
=
(
NumBits
/
8
)
+
(
(
NumBits
%
8
)
==
0
0
:
1
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
<
NumBytes
;
++
i
)
{
uint8_t
mask
=
(
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
)
;
Data
[
Offset
+
i
]
|=
mask
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> unsigned encode ( unsigned Val ) const { return ( Val & Mask ) << Shift ; } </s>

Utility function to encode a Dwarf pair of LineDelta and AddrDeltas .


<s> void erase ( ) { while ( ! Items . empty ( ) ) { TransformItem * TI = Items . pop_back_val ( ) ; TI -> erase ( ) ; } } </s>

erase - Erases an element identified by Key , if it exists .


<s> unsigned Cpu0SEInstrInfo :: loadImmediate ( int64_t Imm , MachineBasicBlock & MBB , MachineBasicBlock :: iterator II , const DebugLoc & DL , unsigned * NewImm ) const { Cpu0AnalyzeImmediate AnalyzeImm ; unsigned Size = 32 ; unsigned LUi = Cpu0 :: LUi ; unsigned ZEROReg = Cpu0 :: ZERO ; unsigned ATReg = Cpu0 :: AT ; bool LastInstrIsADDiu = NewImm ; const Cpu0AnalyzeImmediate :: InstSeq & Seq = AnalyzeImm . Analyze ( Imm , Size , LastInstrIsADDiu ) ; Cpu0AnalyzeImmediate :: InstSeq :: const_iterator Inst = Seq . begin ( ) ; assert ( Seq . size ( ) && ( ! LastInstrIsADDiu || ( Seq . size ( ) > 1 ) ) ) ; if ( Inst -> Opc == LUi ) BuildMI ( MBB , II , DL , get ( LUi ) , ATReg ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; else BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , ATReg ) . addReg ( ZEROReg ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; for ( ++ Inst ; Inst != Seq . end ( ) - LastInstrIsADDiu ; ++ Inst ) BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , ATReg ) . addReg ( ATReg ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; if ( LastInstrIsADDiu ) * NewImm = Inst -> ImmOpnd ; return ATReg ; } </s>

Emit a series of instructions to load an immediate .


<s> bool AMDGPUPrintfRuntimeBindingImpl :: run ( Module & M ) { Triple TT ( M . getTargetTriple ( ) ) ; if ( TT . getArch ( ) == Triple :: r600 ) return false ; auto PrintfFunction = M . getFunction ( "printf" ) ; if ( ! PrintfFunction ) return false ; for ( auto & U : PrintfFunction -> uses ( ) ) { if ( auto * CI = dyn_cast < CallInst > ( U . getUser ( ) ) ) { if ( CI -> isCallee ( & U ) ) Printfs . push_back ( CI ) ; } } if ( Printfs . empty ( ) ) return false ; TD = & M . getDataLayout ( ) ; return lowerPrintfForGpu ( M ) ; } </s>

Run the analysis pass over a function and produce a dominator tree .


<s> bool MipsTargetMachine :: addPostRegAlloc ( PassManagerBase & PM ) { PM . add ( createMipsExpandPseudoPass ( * this ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> SDNode * AlphaDAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI . getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static AMDGPUOperand :: Ptr CreateReg ( const AMDGPUAsmParser * AsmParser , unsigned RegNo , SMLoc S , SMLoc E ) { auto Op = std :: make_unique < AMDGPUOperand > ( Register , AsmParser ) ; Op -> Reg . RegNo = RegNo ; Op -> Reg . Mods = Modifiers ( ) ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> void SystemZCopyPhysRegs :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> SDValue AMDGPUTargetLowering :: CreateLiveInRegister ( SelectionDAG & DAG , const TargetRegisterClass * RC , unsigned Reg , EVT VT ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned VirtualRegister ; if ( ! MRI . isLiveIn ( Reg ) ) { VirtualRegister = MRI . createVirtualRegister ( RC ) ; MRI . addLiveIn ( Reg , VirtualRegister ) ; } else { VirtualRegister = MRI . getLiveInVirtReg ( Reg ) ; } return DAG . getRegister ( VirtualRegister , VT ) ; } </s>

Helper function that adds Reg to the LiveIn list of the DAG 's MachineFunction .


<s> std :: pair < unsigned , unsigned > M68kInstrInfo :: decomposeMachineOperandsTargetFlags ( unsigned TF ) const { return std :: make_pair ( TF , 0u ) ; } </s>

Decompose the machine operand 's target flags into two values - the direct target flag value and any of bit flags that are applied .


<s> opt_machine_mode arm_mode_to_pred_mode ( machine_mode mode ) { switch ( GET_MODE_NUNITS ( mode ) ) { case 16 : return V16BImode ; case 8 : return V8BImode ; case 4 : return V4BImode ; } return opt_machine_mode ( ) ; } </s>

Return the mode for the MVE vector of predicates corresponding to MODE .


<s> const M88kInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> void PPCScoreboardHazardRecognizer :: AdvanceCycle ( ) { ScoreboardHazardRecognizer :: AdvanceCycle ( ) ; } </s>

AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled can not issue in the current cycle , either because of latency or resource conflicts .


<s> static int sh_address_cost ( rtx x , machine_mode mode , addr_space_t as ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { if ( REG_P ( x ) && REGNO ( x ) == GBR_REG ) return 2 ; if ( REG_P ( x ) || GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == PRE_DEC ) return 1 ; if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , 0 ) ) && CONST_INT_P ( XEXP ( x , 1 ) ) ) { if ( REGNO ( XEXP ( x , 0 ) ) == GBR_REG && gbr_displacement ( XEXP ( x , 1 ) , mode ) ) return 2 ; const HOST_WIDE_INT offset = INTVAL ( XEXP ( x , 1 ) ) ; if ( offset == 0 ) return 1 ; if ( offset > 0 && offset <= sh_max_mov_insn_displacement ( mode , false ) ) return ( mode == HImode || mode == QImode ) ? 2 : 1 ; if ( TARGET_SH2A && offset > 0 && offset <= sh_max_mov_insn_displacement ( mode , true ) ) return 2 ; return 3 ; } if ( GET_CODE ( x ) == PLUS && ! CONSTANT_P ( XEXP ( x , 1 ) ) ) return 3 ; return 10 ; } </s>

Compute the cost of an address . For the SH , all valid addresses are the same cost . Use a slightly higher cost for reg + reg addressing , since it increases pressure on r0 .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Set wave priority"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> int SparcRegisterInfo :: getDwarfRegNum ( unsigned RegNum , bool isEH ) const { return SparcGenRegisterInfo :: getDwarfRegNumFull ( RegNum , 0 ) ; } </s>

Map a target register to an equivalent dwarf register number .


<s> MCInst X86InstrInfo :: getNop ( ) const { MCInst Nop ; Nop . setOpcode ( X86 :: NOOP ) ; return Nop ; } </s>

Return the noop instruction to use for a noop .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Hexagon Constant Propagation"
;
}
</s>


<s> void HexagonRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOp , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; MachineBasicBlock & MB = * MI . getParent ( ) ; MachineFunction & MF = * MB . getParent ( ) ; auto & HST = MF . getSubtarget < HexagonSubtarget > ( ) ; auto & HII = * HST . getInstrInfo ( ) ; auto & HFI = * HST . getFrameLowering ( ) ; unsigned BP = 0 ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; int Offset = HFI . getFrameIndexReference ( MF , FI , BP ) ; int RealOffset = Offset + MI . getOperand ( FIOp + 1 ) . getImm ( ) ; bool IsKill = false ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case Hexagon :: PS_fia : MI . setDesc ( HII . get ( Hexagon :: A2_addi ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + 1 ) ; return ; case Hexagon :: PS_fi : MI . setDesc ( HII . get ( Hexagon :: A2_addi ) ) ; break ; } if ( ! HII . isValidOffset ( Opc , RealOffset , this ) ) { auto & MRI = MF . getRegInfo ( ) ; Register TmpR = MRI . createVirtualRegister ( & Hexagon :: IntRegsRegClass ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( MB , II , DL , HII . get ( Hexagon :: A2_addi ) , TmpR ) . addReg ( BP ) . addImm ( RealOffset ) ; BP = TmpR ; RealOffset = 0 ; IsKill = true ; } MI . getOperand ( FIOp ) . ChangeToRegister ( BP , false , false , IsKill ) ; MI . getOperand ( FIOp + 1 ) . ChangeToImmediate ( RealOffset ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> std :: unique_ptr < SICacheControl > SICacheControl :: create ( const GCNSubtarget & ST ) { GCNSubtarget :: Generation Generation = ST . getGeneration ( ) ; if ( ST . hasGFX940Insts ( ) ) return std :: make_unique < SIGfx940CacheControl > ( ST ) ; if ( ST . hasGFX90AInsts ( ) ) return std :: make_unique < SIGfx90ACacheControl > ( ST ) ; if ( Generation <= AMDGPUSubtarget :: SOUTHERN_ISLANDS ) return std :: make_unique < SIGfx6CacheControl > ( ST ) ; if ( Generation < AMDGPUSubtarget :: GFX10 ) return std :: make_unique < SIGfx7CacheControl > ( ST ) ; return std :: make_unique < SIGfx10CacheControl > ( ST ) ; } </s>

AMDGPU SI SI SI SI AMDGPU SI AMDGPU SI SI


<s> bool RISCVTargetLowering :: hasAndNot ( SDValue Y ) const { EVT VT = Y . getValueType ( ) ; if ( VT . isVector ( ) ) return false ; return Subtarget . hasStdExtZbb ( ) && ! isa < ConstantSDNode > ( Y ) ; } </s>

Return true if the target has a bitwise and-not operation : X = ~A & B This can be used to simplify select or other instructions .


<s>
SDValue
RISCVTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
report_fatal_error
(
"unimplemented operand"
)
;
case
ISD
::
GlobalAddress
:
return
lowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
lowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
lowerSELECT
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
lowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

RISCV
RISCV
"unimplemented operand"
ISD::GlobalAddress
ISD::BlockAddress
ISD::SELECT
ISD::VASTART
ISD::FRAMEADDR
ISD::RETURNADDR


<s> static bool ia64_libgcc_floating_mode_supported_p ( machine_mode mode ) { switch ( mode ) { case SFmode : case DFmode : return true ; case XFmode : return false ; return true ; case TFmode : return false ; return true ; default : return false ; } } </s>


<s> TargetTransformInfo NVPTXTargetMachine :: getTargetTransformInfo ( const Function & F ) const { return TargetTransformInfo ( NVPTXTTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> bool OptimizeLEAPass :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; if ( DisableX86LEAOpt || ! MF . getFunction ( ) -> optForSize ( ) ) return false ; MRI = & MF . getRegInfo ( ) ; TII = MF . getSubtarget < X86Subtarget > ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget < X86Subtarget > ( ) . getRegisterInfo ( ) ; for ( auto & MBB : MF ) { MemOpMap LEAs ; InstrPos . clear ( ) ; findLEAs ( MBB , LEAs ) ; if ( LEAs . empty ( ) ) continue ; if ( MF . getFunction ( ) -> optForMinSize ( ) ) Changed |= removeRedundantLEAs ( LEAs ) ; Changed |= removeRedundantAddrCalc ( LEAs ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool hppa_rtx_costs ( rtx x , int code , int outer_code , int opno ATTRIBUTE_UNUSED , int * total , bool speed ATTRIBUTE_UNUSED ) { int factor ; switch ( code ) { case CONST_INT : if ( INTVAL ( x ) == 0 ) * total = 0 ; else if ( INT_14_BITS ( x ) ) * total = 1 ; else * total = 2 ; return true ; case HIGH : * total = 2 ; return true ; case CONST : case LABEL_REF : case SYMBOL_REF : * total = 4 ; return true ; case CONST_DOUBLE : if ( ( x == CONST0_RTX ( DFmode ) || x == CONST0_RTX ( SFmode ) ) && outer_code != SET ) * total = 0 ; else * total = 8 ; return true ; case MULT : if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) { * total = COSTS_N_INSNS ( 3 ) ; return true ; } factor = GET_MODE_SIZE ( GET_MODE ( x ) ) / 4 ; if ( factor == 0 ) factor = 1 ; if ( TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT ) * total = factor * factor * COSTS_N_INSNS ( 8 ) ; else * total = factor * factor * COSTS_N_INSNS ( 20 ) ; return true ; case DIV : if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) { * total = COSTS_N_INSNS ( 14 ) ; return true ; } case UDIV : case MOD : case UMOD : factor = GET_MODE_SIZE ( GET_MODE ( x ) ) / 4 ; if ( factor == 0 ) factor = 1 ; * total = factor * factor * COSTS_N_INSNS ( 60 ) ; return true ; case PLUS : case MINUS : if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) { * total = COSTS_N_INSNS ( 3 ) ; return true ; } factor = GET_MODE_SIZE ( GET_MODE ( x ) ) / UNITS_PER_WORD ; if ( factor == 0 ) factor = 1 ; * total = factor * COSTS_N_INSNS ( 1 ) ; return true ; case ASHIFT : case ASHIFTRT : case LSHIFTRT : * total = COSTS_N_INSNS ( 1 ) ; return true ; default : return false ; } } </s>

Compute a ( partial ) cost for rtx X . Return true if the complete cost has been computed , and false if subexpressions should be scanned . In either case , * TOTAL contains the cost result .


<s> void mcore_print_operand_address ( FILE * stream , rtx x ) { switch ( GET_CODE ( x ) ) { case REG : fprintf ( stream , "(%s)" , reg_names [ REGNO ( x ) ] ) ; break ; case PLUS : { rtx base = XEXP ( x , 0 ) ; rtx index = XEXP ( x , 1 ) ; if ( GET_CODE ( base ) != REG ) { rtx temp = base ; base = index ; index = temp ; } switch ( GET_CODE ( index ) ) { case CONST_INT : fprintf ( stream , "(%s," HOST_WIDE_INT_PRINT_DEC ")" , reg_names [ REGNO ( base ) ] , INTVAL ( index ) ) ; break ; default : gcc_unreachable ( ) ; } } break ; default : output_addr_const ( stream , x ) ; break ; } } </s>

Print the operand address in x to the stream .


<s> const uint32_t * ARMBaseRegisterInfo :: getThisReturnPreservedMask ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return nullptr ; return ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ? CSR_iOS_ThisReturn_RegMask : CSR_AAPCS_ThisReturn_RegMask ; } </s>

getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned ' is on an i32 first argument if the calling convention is one that can ( partially ) model this attribute with a preserved mask ( i.e .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Mips VR4300 mulmul bugfix"
;
}
</s>


<s> void HexagonTargetLowering :: LowerOperationWrapper ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { if ( isHvxOperation ( N ) ) { LowerHvxOperationWrapper ( N , Results , DAG ) ; if ( ! Results . empty ( ) ) return ; } if ( N -> getOpcode ( ) != ISD :: STORE ) return TargetLowering :: LowerOperationWrapper ( N , Results , DAG ) ; } </s>

This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types .


<s> void initializePass ( ) override { pushTTIStack ( this ) ; } </s>

initializePass - This method may be overriden by immutable passes to allow them to perform various initialization actions they require .


<s>
void
HexagonEarlyIfConversion
::
removeBlock
(
MachineBasicBlock
*
B
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Removing block "
<<
PrintMB
(
B
)
<<
"\n"
)
;
MachineDomTreeNode
*
N
=
MDT
->
getNode
(
B
)
;
MachineDomTreeNode
*
IDN
=
N
->
getIDom
(
)
;
if
(
IDN
)
{
MachineBasicBlock
*
IDB
=
IDN
->
getBlock
(
)
;
using
GTN
=
GraphTraits
<
MachineDomTreeNode
*
>
;
using
DTNodeVectType
=
SmallVector
<
MachineDomTreeNode
*
,
4
>
;
DTNodeVectType
Cn
(
GTN
::
child_begin
(
N
)
,
GTN
::
child_end
(
N
)
)
;
for
(
DTNodeVectType
::
iterator
I
=
Cn
.
begin
(
)
,
E
=
Cn
.
end
(
)
;
I
!=
E
;
++
I
)
{
MachineBasicBlock
*
SB
=
(
*
I
)
->
getBlock
(
)
;
MDT
->
changeImmediateDominator
(
SB
,
IDB
)
;
}
}
while
(
B
->
succ_size
(
)
>
0
)
B
->
removeSuccessor
(
B
->
succ_begin
(
)
)
;
for
(
auto
I
=
B
->
pred_begin
(
)
,
E
=
B
->
pred_end
(
)
;
I
!=
E
;
++
I
)
(
*
I
)
->
removeSuccessor
(
B
,
true
)
;
Deleted
.
insert
(
B
)
;
MDT
->
eraseNode
(
B
)
;
MFN
->
erase
(
B
->
getIterator
(
)
)
;
}
</s>

This method completely removes BB from all data structures , including all of the Loop objects it is nested in and our mapping from MachineBasicBlocks to loops .

Hexagon
Hexagon
"Removing block "
"\n"
4
0


<s>
bool
SystemZInstrInfo
::
PredicateInstruction
(
MachineInstr
&
MI
,
ArrayRef
<
MachineOperand
>
Pred
)
const
{
assert
(
Pred
.
size
(
)
==
2
&&
"Invalid condition"
)
;
unsigned
CCValid
=
Pred
[
0
]
.
getImm
(
)
;
unsigned
CCMask
=
Pred
[
1
]
.
getImm
(
)
;
assert
(
CCMask
>
0
&&
CCMask
<
15
&&
"Invalid predicate"
)
;
unsigned
Opcode
=
MI
.
getOpcode
(
)
;
if
(
Opcode
==
SystemZ
::
Trap
)
{
MI
.
setDesc
(
get
(
SystemZ
::
CondTrap
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
Return
)
{
MI
.
setDesc
(
get
(
SystemZ
::
CondReturn
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
CallJG
)
{
MachineOperand
FirstOp
=
MI
.
getOperand
(
0
)
;
const
uint32_t
*
RegMask
=
MI
.
getOperand
(
1
)
.
getRegMask
(
)
;
MI
.
RemoveOperand
(
1
)
;
MI
.
RemoveOperand
(
0
)
;
MI
.
setDesc
(
get
(
SystemZ
::
CallBRCL
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
add
(
FirstOp
)
.
addRegMask
(
RegMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
CallBR
)
{
MachineOperand
Target
=
MI
.
getOperand
(
0
)
;
const
uint32_t
*
RegMask
=
MI
.
getOperand
(
1
)
.
getRegMask
(
)
;
MI
.
RemoveOperand
(
1
)
;
MI
.
RemoveOperand
(
0
)
;
MI
.
setDesc
(
get
(
SystemZ
::
CallBCR
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
add
(
Target
)
.
addRegMask
(
RegMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
return
false
;
}
</s>

Convert the instruction into a predicated instruction .


<s>
SDValue
Nios2TargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
MF
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
CheckReturn
(
Outs
,
RetCC_Nios2EABI
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
SDValue
Val
=
OutVals
[
i
]
;
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
if
(
RVLocs
[
i
]
.
getValVT
(
)
!=
RVLocs
[
i
]
.
getLocVT
(
)
)
Val
=
DAG
.
getNode
(
ISD
::
BITCAST
,
DL
,
RVLocs
[
i
]
.
getLocVT
(
)
,
Val
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
Val
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
Nios2ISD
::
Ret
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> int SIInstrInfo :: pseudoToMCOpcode ( int Opcode ) const { SIEncodingFamily Gen = subtargetEncodingFamily ( ST ) ; if ( ( get ( Opcode ) . TSFlags & SIInstrFlags :: renamedInGFX9 ) != 0 && ST . getGeneration ( ) >= AMDGPUSubtarget :: GFX9 ) Gen = SIEncodingFamily :: GFX9 ; if ( get ( Opcode ) . TSFlags & SIInstrFlags :: SDWA ) Gen = ST . getGeneration ( ) == AMDGPUSubtarget :: GFX9 ? SIEncodingFamily :: SDWA9 : SIEncodingFamily :: SDWA ; if ( ST . hasUnpackedD16VMem ( ) && ( get ( Opcode ) . TSFlags & SIInstrFlags :: D16Buf ) ) Gen = SIEncodingFamily :: GFX80 ; int MCOp = AMDGPU :: getMCOpcode ( Opcode , Gen ) ; if ( MCOp == - 1 ) return Opcode ; if ( MCOp == ( uint16_t ) - 1 ) return - 1 ; return MCOp ; } </s>

Return a target-specific opcode if Opcode is a pseudo instruction .


<s> bool HexagonSplitConst32AndConst64 :: runOnMachineFunction ( MachineFunction & Fn ) { const HexagonTargetObjectFile & TLOF = * static_cast < const HexagonTargetObjectFile * > ( Fn . getTarget ( ) . getObjFileLowering ( ) ) ; if ( TLOF . isSmallDataEnabled ( ) ) return true ; const TargetInstrInfo * TII = Fn . getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * TRI = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; for ( MachineBasicBlock & B : Fn ) { for ( auto I = B . begin ( ) , E = B . end ( ) ; I != E ; ) { MachineInstr & MI = * I ; ++ I ; unsigned Opc = MI . getOpcode ( ) ; if ( Opc == Hexagon :: CONST32 ) { unsigned DestReg = MI . getOperand ( 0 ) . getReg ( ) ; uint64_t ImmValue = MI . getOperand ( 1 ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( B , MI , DL , TII -> get ( Hexagon :: A2_tfrsi ) , DestReg ) . addImm ( ImmValue ) ; B . erase ( & MI ) ; } else if ( Opc == Hexagon :: CONST64 ) { unsigned DestReg = MI . getOperand ( 0 ) . getReg ( ) ; int64_t ImmValue = MI . getOperand ( 1 ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; unsigned DestLo = TRI -> getSubReg ( DestReg , Hexagon :: isub_lo ) ; unsigned DestHi = TRI -> getSubReg ( DestReg , Hexagon :: isub_hi ) ; int32_t LowWord = ( ImmValue & 0xFFFFFFFF ) ; int32_t HighWord = ( ImmValue >> 32 ) & 0xFFFFFFFF ; BuildMI ( B , MI , DL , TII -> get ( Hexagon :: A2_tfrsi ) , DestLo ) . addImm ( LowWord ) ; BuildMI ( B , MI , DL , TII -> get ( Hexagon :: A2_tfrsi ) , DestHi ) . addImm ( HighWord ) ; B . erase ( & MI ) ; } } } return true ; } </s>


<s>
MachineBasicBlock
*
MSP430TargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
unsigned
Opc
=
MI
->
getOpcode
(
)
;
if
(
Opc
==
MSP430
::
Shl8
||
Opc
==
MSP430
::
Shl16
||
Opc
==
MSP430
::
Sra8
||
Opc
==
MSP430
::
Sra16
||
Opc
==
MSP430
::
Srl8
||
Opc
==
MSP430
::
Srl16
)
return
EmitShiftInstr
(
MI
,
BB
)
;
const
TargetInstrInfo
&
TII
=
*
getTargetMachine
(
)
.
getInstrInfo
(
)
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
assert
(
(
Opc
==
MSP430
::
Select16
||
Opc
==
MSP430
::
Select8
)
&&
"Unexpected instr type to insert"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
I
=
BB
;
++
I
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
copy1MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
F
->
insert
(
I
,
copy0MBB
)
;
F
->
insert
(
I
,
copy1MBB
)
;
copy1MBB
->
splice
(
copy1MBB
->
begin
(
)
,
BB
,
std
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
BB
->
end
(
)
)
;
copy1MBB
->
transferSuccessorsAndUpdatePHIs
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
copy1MBB
)
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
MSP430
::
JCC
)
)
.
addMBB
(
copy1MBB
)
.
addImm
(
MI
->
getOperand
(
3
)
.
getImm
(
)
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
copy1MBB
)
;
BB
=
copy1MBB
;
BuildMI
(
*
BB
,
BB
->
begin
(
)
,
dl
,
TII
.
get
(
MSP430
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
MI
->
eraseFromParent
(
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


"********** Memory Intrinsic Results **********\n"

"MemIntrinsicResults expects liveness tracking"


"mnop-mcount only supported with fentry-call"


<s> static int rs6000_emit_int_cmove ( rtx dest , rtx op , rtx true_cond , rtx false_cond ) { rtx condition_rtx , cr ; if ( GET_MODE ( rs6000_compare_op0 ) != SImode ) return 0 ; condition_rtx = rs6000_generate_compare ( GET_CODE ( op ) ) ; cr = XEXP ( condition_rtx , 0 ) ; if ( GET_MODE ( cr ) == CCmode ) emit_insn ( gen_isel_signed ( dest , condition_rtx , true_cond , false_cond , cr ) ) ; else emit_insn ( gen_isel_unsigned ( dest , condition_rtx , true_cond , false_cond , cr ) ) ; return 1 ; } </s>


<s>
void
A57PBQPConstraints
::
apply
(
PBQPRAGraph
&
G
)
{
MachineFunction
&
MF
=
G
.
getMetadata
(
)
.
MF
;
const
TargetRegisterInfo
&
TRI
=
*
MF
.
getTarget
(
)
.
getSubtargetImpl
(
)
->
getRegisterInfo
(
)
;
(
void
)
TRI
;
DEBUG
(
MF
.
dump
(
)
)
;
for
(
MachineFunction
::
const_iterator
mbbItr
=
MF
.
begin
(
)
,
mbbEnd
=
MF
.
end
(
)
;
mbbItr
!=
mbbEnd
;
++
mbbItr
)
{
const
MachineBasicBlock
*
MBB
=
&
*
mbbItr
;
Chains
.
clear
(
)
;
for
(
MachineBasicBlock
::
const_iterator
miItr
=
MBB
->
begin
(
)
,
miEnd
=
MBB
->
end
(
)
;
miItr
!=
miEnd
;
++
miItr
)
{
const
MachineInstr
*
MI
=
&
*
miItr
;
switch
(
MI
->
getOpcode
(
)
)
{
case
AArch64
::
FMSUBSrrr
:
case
AArch64
::
FMADDSrrr
:
case
AArch64
::
FNMSUBSrrr
:
case
AArch64
::
FNMADDSrrr
:
case
AArch64
::
FMSUBDrrr
:
case
AArch64
::
FMADDDrrr
:
case
AArch64
::
FNMSUBDrrr
:
case
AArch64
::
FNMADDDrrr
:
{
unsigned
Rd
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
unsigned
Ra
=
MI
->
getOperand
(
3
)
.
getReg
(
)
;
if
(
addIntraChainConstraint
(
G
,
Rd
,
Ra
)
)
addInterChainConstraint
(
G
,
Rd
,
Ra
)
;
break
;
}
case
AArch64
::
FMLAv2f32
:
case
AArch64
::
FMLSv2f32
:
{
unsigned
Rd
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
addInterChainConstraint
(
G
,
Rd
,
Rd
)
;
break
;
}
default
:
for
(
auto
r
:
Chains
)
{
SmallVector
<
unsigned
,
8
>
toDel
;
if
(
MI
->
killsRegister
(
r
)
)
{
DEBUG
(
dbgs
(
)
<<
"Killing chain "
<<
PrintReg
(
r
,
&
TRI
)
<<
" at "
;
MI
->
print
(
dbgs
(
)
)
;
)
;
toDel
.
push_back
(
r
)
;
}
while
(
!
toDel
.
empty
(
)
)
{
Chains
.
remove
(
toDel
.
back
(
)
)
;
toDel
.
pop_back
(
)
;
}
}
}
}
}
}
</s>

Apply the profile inference algorithm for a given function .


<s> bool aarch64_bitmask_imm ( HOST_WIDE_INT val_in , machine_mode mode ) { unsigned HOST_WIDE_INT val , tmp , mask , first_one , next_one ; int bits ; val = aarch64_replicate_bitmask_imm ( val_in , mode ) ; tmp = val + ( val & - val ) ; if ( tmp == ( tmp & - tmp ) ) return ( val + 1 ) > 1 ; if ( mode == SImode ) val = ( val << 32 ) | ( val & 0xffffffff ) ; if ( val & 1 ) val = ~ val ; first_one = val & - val ; tmp = val & ( val + first_one ) ; if ( tmp == 0 ) return true ; next_one = tmp & - tmp ; bits = clz_hwi ( first_one ) - clz_hwi ( next_one ) ; mask = val ^ tmp ; if ( ( mask >> bits ) != 0 || bits != ( bits & - bits ) ) return false ; return val == mask * bitmask_imm_mul [ __builtin_clz ( bits ) - 26 ] ; } </s>

Return true if val is a valid bitmask immediate .


<s> int first_reg_to_save ( void ) { int first_reg ; for ( first_reg = 13 ; first_reg <= 31 ; first_reg ++ ) if ( regs_ever_live [ first_reg ] && ( ! call_used_regs [ first_reg ] || ( first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ( ( DEFAULT_ABI == ABI_V4 && flag_pic != 0 ) || ( DEFAULT_ABI == ABI_DARWIN && flag_pic ) || ( TARGET_TOC && TARGET_MINIMAL_TOC ) ) ) ) ) break ; if ( flag_pic && current_function_uses_pic_offset_table && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM ) return RS6000_PIC_OFFSET_TABLE_REGNUM ; return first_reg ; } </s>

Return the first register that is required to be saved . 16 if none .


<s> unsigned WebAssemblyFastISel :: fastMaterializeConstant ( const Constant * C ) { if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) { if ( TLI . isPositionIndependent ( ) ) return 0 ; if ( GV -> isThreadLocal ( ) ) return 0 ; unsigned ResultReg = createResultReg ( Subtarget -> hasAddr64 ( ) ? & WebAssembly :: I64RegClass : & WebAssembly :: I32RegClass ) ; unsigned Opc = Subtarget -> hasAddr64 ( ) ? WebAssembly :: CONST_I64 : WebAssembly :: CONST_I32 ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addGlobalAddress ( GV ) ; return ResultReg ; } return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s> static sbitmap rs6000_get_separate_components ( void ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; if ( WORLD_SAVE_P ( info ) ) return NULL ; gcc_assert ( ! ( info -> savres_strategy & SAVE_MULTIPLE ) && ! ( info -> savres_strategy & REST_MULTIPLE ) ) ; cfun -> machine -> n_components = 64 ; sbitmap components = sbitmap_alloc ( cfun -> machine -> n_components ) ; bitmap_clear ( components ) ; int reg_size = TARGET_32BIT ? 4 : 8 ; int fp_reg_size = 8 ; if ( ( info -> savres_strategy & SAVE_INLINE_GPRS ) && ( info -> savres_strategy & REST_INLINE_GPRS ) ) { int offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( unsigned regno = info -> first_gp_reg_save ; regno < 32 ; regno ++ ) { if ( IN_RANGE ( offset , - 0x8000 , 0x7fff ) && save_reg_p ( regno ) ) bitmap_set_bit ( components , regno ) ; offset += reg_size ; } } if ( frame_pointer_needed ) bitmap_clear_bit ( components , HARD_FRAME_POINTER_REGNUM ) ; if ( ( TARGET_TOC && TARGET_MINIMAL_TOC ) || ( flag_pic == 1 && DEFAULT_ABI == ABI_V4 ) || ( flag_pic && DEFAULT_ABI == ABI_DARWIN ) ) bitmap_clear_bit ( components , RS6000_PIC_OFFSET_TABLE_REGNUM ) ; if ( ( info -> savres_strategy & SAVE_INLINE_FPRS ) && ( info -> savres_strategy & REST_INLINE_FPRS ) ) { int offset = info -> fp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( unsigned regno = info -> first_fp_reg_save ; regno < 64 ; regno ++ ) { if ( IN_RANGE ( offset , - 0x8000 , 0x7fff ) && save_reg_p ( regno ) ) bitmap_set_bit ( components , regno ) ; offset += fp_reg_size ; } } if ( info -> lr_save_p && ! ( flag_pic && ( DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN ) ) && ( info -> savres_strategy & SAVE_INLINE_GPRS ) && ( info -> savres_strategy & REST_INLINE_GPRS ) && ( info -> savres_strategy & SAVE_INLINE_FPRS ) && ( info -> savres_strategy & REST_INLINE_FPRS ) && ( info -> savres_strategy & SAVE_INLINE_VRS ) && ( info -> savres_strategy & REST_INLINE_VRS ) ) { int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; if ( IN_RANGE ( offset , - 0x8000 , 0x7fff ) ) bitmap_set_bit ( components , 0 ) ; } if ( cfun -> machine -> save_toc_in_prologue ) bitmap_set_bit ( components , 2 ) ; return components ; } </s>


<s> static void workaround_arc_anomaly ( void ) { rtx_insn * insn , * succ0 ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { succ0 = next_real_insn ( insn ) ; if ( arc_hazard ( insn , succ0 ) ) { emit_insn_before ( gen_nopv ( ) , succ0 ) ; } } if ( TARGET_ARC700 ) { rtx_insn * succ1 ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { succ0 = next_real_insn ( insn ) ; if ( arc_store_addr_hazard_p ( insn , succ0 ) ) { emit_insn_after ( gen_nopv ( ) , insn ) ; emit_insn_after ( gen_nopv ( ) , insn ) ; continue ; } succ1 = next_real_insn ( succ0 ) ; if ( succ0 && ! JUMP_P ( succ0 ) && ! CALL_P ( succ0 ) && arc_store_addr_hazard_p ( insn , succ1 ) ) emit_insn_after ( gen_nopv ( ) , insn ) ; } } } </s>

The same functionality as arc_hazard . It is called in machine reorg before any other optimization . Hence , the NOP size is taken into account when doing branch shortening .


<s> static bool avr_cannot_modify_jumps_p ( void ) { if ( reload_completed && cfun -> machine && cfun -> machine -> is_naked ) { return true ; } return false ; } </s>

Implement ` TARGET_CANNOT_MODITY_JUMPS_P ' .


<s> void LC3InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( LC3 :: LDR ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> rtx function_value ( tree valtype , tree func ATTRIBUTE_UNUSED , enum machine_mode mode ) { unsigned int regnum , dummy ; enum mode_class class ; gcc_assert ( ! valtype || ! alpha_return_in_memory ( valtype , func ) ) ; if ( valtype ) mode = TYPE_MODE ( valtype ) ; class = GET_MODE_CLASS ( mode ) ; switch ( class ) { case MODE_INT : PROMOTE_MODE ( mode , dummy , valtype ) ; case MODE_COMPLEX_INT : case MODE_VECTOR_INT : regnum = 0 ; break ; case MODE_FLOAT : regnum = 32 ; break ; case MODE_COMPLEX_FLOAT : { enum machine_mode cmode = GET_MODE_INNER ( mode ) ; return gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( cmode , 32 ) , const0_rtx ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( cmode , 33 ) , GEN_INT ( GET_MODE_SIZE ( cmode ) ) ) ) ) ; } default : gcc_unreachable ( ) ; } return gen_rtx_REG ( mode , regnum ) ; } </s>

Handle FUNCTION_VALUE , FUNCTION_OUTGOING_VALUE , and LIBCALL_VALUE macros . For v9 , function return values are subject to the same rules as arguments , except that up to 32 bytes may be returned in registers .


"selector must be an integer constant in the range 0..%wi"

Return the integer constant in ARG . Constrain it to be in the range of the subparts of VEC_TYPE ; issue an error if not .


<s>
StringRef
getPassName
(
)
const
override
{
return
"SI optimize exec mask operations"
;
}
</s>

getPassName - Return a nice clean name for a pass .

AMDGPU
"SI optimize exec mask operations"


<s> static void aarch64_asm_output_variant_pcs ( FILE * stream , const tree decl , const char * name ) { if ( TREE_CODE ( decl ) == FUNCTION_DECL ) { arm_pcs pcs = ( arm_pcs ) fndecl_abi ( decl ) . id ( ) ; if ( pcs == ARM_PCS_SIMD || pcs == ARM_PCS_SVE ) { fprintf ( stream , "\t.variant_pcs\t" ) ; assemble_name ( stream , name ) ; fprintf ( stream , "\n" ) ; } } } </s>

Output .variant_pcs for aarch64_vector_pcs function symbols .


"Only register-returns should be created by PCS"


<s> bool RISCVRegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , Register Reg , int & FrameIdx ) const { const auto * RVFI = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; if ( ! RVFI -> useSaveRestoreLibCalls ( ) ) return false ; auto FII = FixedCSRFIMap . find ( Reg ) ; if ( FII == FixedCSRFIMap . end ( ) ) return false ; FrameIdx = FII -> second ; return true ; } </s>

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register .


<s> enum rtx_code s390_reverse_condition ( machine_mode mode , enum rtx_code code ) { if ( mode == CCVFALLmode || mode == CCVFANYmode || mode == CCSFPSmode ) return reverse_condition_maybe_unordered ( code ) ; else if ( mode == CCVIALLmode || mode == CCVIANYmode ) return reverse_condition ( code ) ; else gcc_unreachable ( ) ; } </s>

Invert the comparison CODE applied to a CC mode . This is only safe if we know whether there result was created by a floating point compare or not . For the CCV modes this is encoded as part of the mode .


<s> void thumb1_gen_const_int ( rtx op0 , HOST_WIDE_INT op1 ) { bool mov_done_p = false ; int i ; for ( i = 0 ; i < 3 ; i ++ ) { int byte = ( op1 >> ( 8 * ( 3 - i ) ) ) & 0xff ; if ( byte ) { emit_set_insn ( op0 , mov_done_p ? gen_rtx_PLUS ( SImode , op0 , GEN_INT ( byte ) ) : GEN_INT ( byte ) ) ; mov_done_p = true ; } if ( mov_done_p ) emit_set_insn ( op0 , gen_rtx_ASHIFT ( SImode , op0 , GEN_INT ( 8 ) ) ) ; } if ( ! mov_done_p ) emit_set_insn ( op0 , GEN_INT ( op1 & 0xff ) ) ; else if ( op1 & 0xff ) emit_set_insn ( op0 , gen_rtx_PLUS ( SImode , op0 , GEN_INT ( op1 & 0xff ) ) ) ; } </s>

Emit a sequence of movs/adds/shift to produce a 32-bit constant . Avoid generating useless code when one of the bytes is zero .


<s> static void s390_asm_file_start ( void ) { s390_asm_output_machine_for_arch ( asm_out_file ) ; } </s>


<s> int AMDGPUFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const AMDGPURegisterInfo * RI = MF . getSubtarget < AMDGPUSubtarget > ( ) . getRegisterInfo ( ) ; FrameReg = RI -> getFrameRegister ( MF ) ; unsigned OffsetBytes = 2 * ( getStackWidth ( MF ) * 4 ) ; int UpperBound = FI == - 1 ? MFI . getNumObjects ( ) : FI ; for ( int i = MFI . getObjectIndexBegin ( ) ; i < UpperBound ; ++ i ) { OffsetBytes = alignTo ( OffsetBytes , MFI . getObjectAlignment ( i ) ) ; OffsetBytes += MFI . getObjectSize ( i ) ; OffsetBytes = alignTo ( OffsetBytes , 4 ) ; } if ( FI != - 1 ) OffsetBytes = alignTo ( OffsetBytes , MFI . getObjectAlignment ( FI ) ) ; return OffsetBytes / ( getStackWidth ( MF ) * 4 ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


"storeRegToStackSlot should not be called for PTX"

Store the specified register of the given register class to the specified stack frame index .


<s> bool MipsTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( ! AM . HasBaseReg ) break ; return false ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> static bool rs6000_hard_regno_call_part_clobbered ( unsigned int regno , machine_mode mode ) { if ( TARGET_32BIT && TARGET_POWERPC64 && GET_MODE_SIZE ( mode ) > 4 && INT_REGNO_P ( regno ) ) return true ; if ( TARGET_VSX && FP_REGNO_P ( regno ) && GET_MODE_SIZE ( mode ) > 8 && ! FLOAT128_2REG_P ( mode ) ) return true ; return false ; } </s>


<s> void AArch64TTIImpl :: getPeelingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: PeelingPreferences & PP ) { BaseT :: getPeelingPreferences ( L , SE , PP ) ; } </s>

Get target-customized preferences for the generic loop peeling transformation .


<s> const MCExpr * PPCAIXAsmPrinter :: lowerConstant ( const Constant * CV ) { if ( const Function * F = dyn_cast < Function > ( CV ) ) { MCSymbolXCOFF * FSym = cast < MCSymbolXCOFF > ( getSymbol ( F ) ) ; if ( ! FSym -> hasContainingCsect ( ) ) { MCSectionXCOFF * Csect = cast < MCSectionXCOFF > ( F -> isDeclaration ( ) ? getObjFileLowering ( ) . getSectionForExternalReference ( F , TM ) : getObjFileLowering ( ) . getSectionForFunctionDescriptor ( FSym ) ) ; FSym -> setContainingCsect ( Csect ) ; } return MCSymbolRefExpr :: create ( FSym -> getContainingCsect ( ) -> getQualNameSymbol ( ) , OutContext ) ; } return PPCAsmPrinter :: lowerConstant ( CV ) ; } </s>

Lower the specified LLVM Constant to an MCExpr .


<s> static rtx move_to_de ( int opno , rtx_insn * before ) { rtx src = OP ( opno ) ; machine_mode mode = GET_MODE ( src ) ; rtx reg ; if ( mode == VOIDmode ) mode = recog_data . operand_mode [ opno ] ; reg = ( mode == QImode ) ? E : DE ; if ( mode == QImode || ! is_virtual_register ( OP ( opno ) ) ) { OP ( opno ) = move_to_acc ( opno , before ) ; OP ( opno ) = move_acc_to_reg ( OP ( opno ) , E_REG , before ) ; } else { gen_and_emit_move ( reg , src , before , true ) ; } return reg ; } </s>

Copy OP ( opno ) to E or DE , placing any generated insns before BEFORE . Returns E/DE RTX .


"Size in memset call must be a compile time constant"

"Cannot memcpy between different address spaces"

"memcpy may be called only for local memory"

"Size in memcpy must be a multiple of space unit"

Emit target-specific code that performs a memcpy .


<s> rtx frv_dynamic_chain_address ( rtx frame ) { cfun -> machine -> frame_needed = 1 ; return frame ; } </s>

The default is correct , but we need to make sure the frame gets created .


<s>
CCAssignFn
*
AMDGPUCallLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
{
switch
(
CC
)
{
case
CallingConv
::
AMDGPU_KERNEL
:
case
CallingConv
::
SPIR_KERNEL
:
return
CC_AMDGPU_Kernel
;
case
CallingConv
::
AMDGPU_VS
:
case
CallingConv
::
AMDGPU_GS
:
case
CallingConv
::
AMDGPU_PS
:
case
CallingConv
::
AMDGPU_CS
:
case
CallingConv
::
AMDGPU_HS
:
return
CC_AMDGPU
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
CC_AMDGPU_Func
;
default
:
report_fatal_error
(
"Unsupported calling convention."
)
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .

AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
"Unsupported calling convention."


<s> static void create_bif_order ( void ) { bif_order = ( int * ) malloc ( ( curr_bif + 1 ) * sizeof ( int ) ) ; rbt_inorder_callback ( & bifo_rbt , bifo_rbt . rbt_root , set_bif_order ) ; } </s>

Create a mapping from function IDs in their final order to the order they appear in the built-in function file .


<s> void arc_print_operand_address ( FILE * file , rtx addr ) { register rtx base , index = 0 ; switch ( GET_CODE ( addr ) ) { case REG : fputs ( reg_names [ REGNO ( addr ) ] , file ) ; break ; case SYMBOL_REF : output_addr_const ( file , addr ) ; if ( SYMBOL_REF_SMALL_P ( addr ) ) fprintf ( file , "@sda" ) ; break ; case PLUS : if ( GET_CODE ( XEXP ( addr , 0 ) ) == MULT ) index = XEXP ( XEXP ( addr , 0 ) , 0 ) , base = XEXP ( addr , 1 ) ; else if ( CONST_INT_P ( XEXP ( addr , 0 ) ) ) index = XEXP ( addr , 0 ) , base = XEXP ( addr , 1 ) ; else base = XEXP ( addr , 0 ) , index = XEXP ( addr , 1 ) ; gcc_assert ( OBJECT_P ( base ) ) ; arc_print_operand_address ( file , base ) ; if ( CONSTANT_P ( base ) && CONST_INT_P ( index ) ) fputc ( '+' , file ) ; else fputc ( ',' , file ) ; gcc_assert ( OBJECT_P ( index ) ) ; arc_print_operand_address ( file , index ) ; break ; case CONST : { rtx c = XEXP ( addr , 0 ) ; if ( ( GET_CODE ( c ) == UNSPEC && ( XINT ( c , 1 ) == UNSPEC_TLS_OFF || XINT ( c , 1 ) == UNSPEC_TLS_IE ) ) || ( GET_CODE ( c ) == PLUS && GET_CODE ( XEXP ( c , 0 ) ) == UNSPEC && ( XINT ( XEXP ( c , 0 ) , 1 ) == UNSPEC_TLS_OFF || XINT ( XEXP ( c , 0 ) , 1 ) == ARC_UNSPEC_GOTOFFPC ) ) ) { arc_output_pic_addr_const ( file , c , 0 ) ; break ; } gcc_assert ( GET_CODE ( c ) == PLUS ) ; gcc_assert ( GET_CODE ( XEXP ( c , 0 ) ) == SYMBOL_REF ) ; gcc_assert ( GET_CODE ( XEXP ( c , 1 ) ) == CONST_INT ) ; output_address ( VOIDmode , XEXP ( addr , 0 ) ) ; break ; } case PRE_INC : case PRE_DEC : gcc_unreachable ( ) ; break ; default : if ( flag_pic ) arc_output_pic_addr_const ( file , addr , 0 ) ; else output_addr_const ( file , addr ) ; break ; } } </s>

Print a memory address as an operand to reference that memory location .


<s> void ARMTargetELFStreamer :: emitLabel ( MCSymbol * Symbol ) { ARMELFStreamer & Streamer = getStreamer ( ) ; if ( ! Streamer . IsThumb ) return ; Streamer . getAssembler ( ) . registerSymbol ( * Symbol ) ; unsigned Type = cast < MCSymbolELF > ( Symbol ) -> getType ( ) ; if ( Type == ELF :: STT_FUNC || Type == ELF :: STT_GNU_IFUNC ) Streamer . EmitThumbFunc ( Symbol ) ; } </s>

Emit a label for Symbol into the current section .


<s>
static
int
frv_arg_partial_bytes
(
cumulative_args_t
cum
,
const
function_arg_info
&
arg
)
{
machine_mode
xmode
=
(
arg
.
mode
==
BLKmode
)
SImode
:
arg
.
mode
;
int
bytes
=
GET_MODE_SIZE
(
xmode
)
;
int
words
=
(
bytes
+
UNITS_PER_WORD
1
)
/
UNITS_PER_WORD
;
int
arg_num
=
*
get_cumulative_args
(
cum
)
;
int
ret
;
ret
=
(
(
arg_num
<=
LAST_ARG_REGNUM
&&
arg_num
+
words
>
LAST_ARG_REGNUM
+
1
)
LAST_ARG_REGNUM
arg_num
+
1
:
0
)
;
ret
*=
UNITS_PER_WORD
;
if
(
TARGET_DEBUG_ARG
&&
ret
)
fprintf
(
stderr
,
"frv_arg_partial_bytes: %d\n"
,
ret
)
;
return
ret
;
}
</s>

A C expression for the number of words , at the beginning of an argument , must be put in registers . The value must be zero for arguments that are passed entirely in registers or that are entirely pushed on the stack . On some machines , certain arguments must be passed partially in registers and partially in memory . On these machines , typically the first N words of arguments are passed in registers , and the rest on the stack . If a multi-word argument ( a ` double ' or a structure ) crosses that boundary , its first few words must be passed in registers and the rest must be pushed . This macro tells the compiler when this occurs , and how many of the words should go in registers . ` FUNCTION_ARG ' for these arguments should return the first register to be used by the caller for this argument ; likewise ` FUNCTION_INCOMING_ARG ' , for the called function .


<s> void alpha_expand_movmisalign ( enum machine_mode mode , rtx * operands ) { if ( MEM_P ( operands [ 1 ] ) ) { rtx tmp ; if ( register_operand ( operands [ 0 ] , mode ) ) tmp = operands [ 0 ] ; else tmp = gen_reg_rtx ( mode ) ; alpha_expand_unaligned_load ( tmp , operands [ 1 ] , 8 , 0 , 0 ) ; if ( tmp != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , tmp ) ; } else if ( MEM_P ( operands [ 0 ] ) ) { if ( ! reg_or_0_operand ( operands [ 1 ] , mode ) ) operands [ 1 ] = force_reg ( mode , operands [ 1 ] ) ; alpha_expand_unaligned_store ( operands [ 0 ] , operands [ 1 ] , 8 , 0 ) ; } else gcc_unreachable ( ) ; } </s>

Implement the movmisalign patterns . One of the operands is a memory that is not naturally aligned . Emit instructions to load it .


<s> static bool expand_vec_perm_pblendv ( struct expand_vec_perm_d * d ) { unsigned i , which , nelt = d -> nelt ; struct expand_vec_perm_d dcopy , dcopy1 ; machine_mode vmode = d -> vmode ; bool ok ; if ( d -> one_operand_p ) return false ; if ( TARGET_AVX2 && GET_MODE_SIZE ( vmode ) == 32 ) ; else if ( TARGET_AVX && ( vmode == V4DFmode || vmode == V8SFmode ) ) ; else if ( TARGET_SSE4_1 && ( GET_MODE_SIZE ( vmode ) == 16 || ( TARGET_MMX_WITH_SSE && GET_MODE_SIZE ( vmode ) == 8 ) || GET_MODE_SIZE ( vmode ) == 4 ) ) ; else return false ; for ( i = 0 , which = 0 ; i < nelt ; ++ i ) { unsigned e = d -> perm [ i ] ; if ( e != i ) which |= ( e < nelt ? 1 : 2 ) ; } if ( which != 1 && which != 2 ) return false ; if ( d -> testing_p && GET_MODE_SIZE ( vmode ) == 16 ) return true ; dcopy = * d ; if ( which == 2 ) dcopy . op0 = dcopy . op1 = d -> op1 ; else dcopy . op0 = dcopy . op1 = d -> op0 ; if ( ! d -> testing_p ) dcopy . target = gen_reg_rtx ( vmode ) ; dcopy . one_operand_p = true ; for ( i = 0 ; i < nelt ; ++ i ) dcopy . perm [ i ] = d -> perm [ i ] & ( nelt - 1 ) ; ok = expand_vec_perm_1 ( & dcopy ) ; if ( GET_MODE_SIZE ( vmode ) != 16 && ! ok ) return false ; else gcc_assert ( ok ) ; if ( d -> testing_p ) return true ; dcopy1 = * d ; if ( which == 2 ) dcopy1 . op1 = dcopy . target ; else dcopy1 . op0 = dcopy . target ; for ( i = 0 ; i < nelt ; ++ i ) dcopy1 . perm [ i ] = ( ( d -> perm [ i ] >= nelt ) ? ( nelt + i ) : i ) ; ok = expand_vec_perm_blend ( & dcopy1 ) ; gcc_assert ( ok ) ; return true ; } </s>

A subroutine of ix86_expand_vec_perm_const_1 . Try to simplify the permutation using the SSE4_1 pblendv instruction . Potentially reduces permutation from 2 pshufb and or to 1 pshufb and pblendv .


<s> unsigned getNumFixupKinds ( ) const override { return OR1K :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> unsigned X86InstrInfo :: isStoreToStackSlotPostFE ( const MachineInstr * MI , int & FrameIndex ) const { if ( isFrameStoreOpcode ( MI -> getOpcode ( ) ) ) { unsigned Reg ; if ( ( Reg = isStoreToStackSlot ( MI , FrameIndex ) ) ) return Reg ; const MachineMemOperand * Dummy ; return hasStoreToStackSlot ( MI , Dummy , FrameIndex ) ; } return 0 ; } </s>

isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s> DFAPacketizer * HexagonInstrInfo :: CreateTargetScheduleState ( const TargetMachine * TM , const ScheduleDAG * DAG ) const { const InstrItineraryData * II = TM -> getSubtargetImpl ( ) -> getInstrItineraryData ( ) ; return TM -> getSubtarget < HexagonGenSubtargetInfo > ( ) . createDFAPacketizer ( II ) ; } </s>

Create machine specific model for scheduling .


<s> static bool mips_mult_move_p ( rtx dest , rtx src , enum mips_split_type split_type ) { return ( ( split_type != SPLIT_FOR_SPEED || mips_tuning_info . fast_mult_zero_zero_p ) && src == const0_rtx && REG_P ( dest ) && GET_MODE_SIZE ( GET_MODE ( dest ) ) == 2 * UNITS_PER_WORD && ( ISA_HAS_DSP_MULT ? ACC_REG_P ( REGNO ( dest ) ) : MD_REG_P ( REGNO ( dest ) ) ) ) ; } </s>

Return true if SRC should be moved into DEST using `` MULT $ 0 , $ 0 '' . SPLIT_TYPE is the condition under which moves should be split .


<s> bool AArch64TargetLowering :: isProfitableToHoist ( Instruction * I ) const { if ( I -> getOpcode ( ) != Instruction :: FMul ) return true ; if ( I -> getNumUses ( ) != 1 ) return true ; Instruction * User = I -> user_back ( ) ; if ( User && ! ( User -> getOpcode ( ) == Instruction :: FSub || User -> getOpcode ( ) == Instruction :: FAdd ) ) return true ; const TargetOptions & Options = getTargetMachine ( ) . Options ; const DataLayout & DL = I -> getModule ( ) -> getDataLayout ( ) ; EVT VT = getValueType ( DL , User -> getOperand ( 0 ) -> getType ( ) ) ; return ! ( isFMAFasterThanFMulAndFAdd ( VT ) && isOperationLegalOrCustom ( ISD :: FMA , VT ) && ( Options . AllowFPOpFusion == FPOpFusion :: Fast || Options . UnsafeFPMath ) ) ; } </s>

Return true if it is profitable to hoist instruction in the then/else to before if .


<s> static rtx ft32_function_arg ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( * cum < 8 ) return gen_rtx_REG ( arg . mode , * cum ) ; else return NULL_RTX ; } </s>

Return the next register to be used to hold a function argument or NULL_RTX if there 's no more space .


<s> void AMDGPUTargetELFStreamer :: finish ( ) { std :: string Blob ; const char * Vendor = getPALMetadata ( ) -> getVendor ( ) ; unsigned Type = getPALMetadata ( ) -> getType ( ) ; getPALMetadata ( ) -> toBlob ( Type , Blob ) ; if ( Blob . empty ( ) ) return ; EmitNote ( Vendor , MCConstantExpr :: create ( Blob . size ( ) , getContext ( ) ) , Type , [ & ] ( MCELFStreamer & OS ) { OS . emitBytes ( Blob ) ; } ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> MachinePointerInfo MipsFunctionInfo :: callPtrInfo ( const GlobalValue * Val ) { std :: unique_ptr < const MipsCallEntry > & E = GlobalCallEntries [ Val ] ; if ( ! E ) E = llvm :: make_unique < MipsCallEntry > ( Val ) ; return MachinePointerInfo ( E . get ( ) ) ; } </s>

Create a MachinePointerInfo that has a GlobalValuePseudoSourceValue object representing a GOT entry for a global function .


<s> void SparcRegisterInfo :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; NumBytes += 92 ; NumBytes = ( NumBytes + 7 ) & ~ 7 ; NumBytes = - NumBytes ; if ( NumBytes >= - 4096 ) { BuildMI ( MBB , MBBI , dl , TII . get ( SP :: SAVEri ) , SP :: O6 ) . addReg ( SP :: O6 ) . addImm ( NumBytes ) ; } else { unsigned OffHi = ( unsigned ) NumBytes >> 10U ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: SETHIi ) , SP :: G1 ) . addImm ( OffHi ) ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: ORri ) , SP :: G1 ) . addReg ( SP :: G1 ) . addImm ( NumBytes & ( ( 1 << 10 ) - 1 ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: SAVErr ) , SP :: O6 ) . addReg ( SP :: O6 ) . addReg ( SP :: G1 ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static bool needs_frame_header_p ( function * fn ) { tree t ; if ( fn -> decl == NULL ) return true ; if ( fn -> stdarg ) return true ; for ( t = DECL_ARGUMENTS ( fn -> decl ) ; t ; t = TREE_CHAIN ( t ) ) { if ( ! use_register_for_decl ( t ) ) return true ; if ( DECL_MODE ( t ) != SImode ) return true ; } return false ; } </s>

Return true if this function will use the stack space allocated by its caller or if we can not determine for certain that it does not .


<s>
bool
HexagonAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
return
true
;
const
MachineOperand
&
Base
=
MI
->
getOperand
(
OpNo
)
;
const
MachineOperand
&
Offset
=
MI
->
getOperand
(
OpNo
+
1
)
;
if
(
Base
.
isReg
(
)
)
printOperand
(
MI
,
OpNo
,
O
)
;
else
llvm_unreachable
(
"Unimplemented"
)
;
if
(
Offset
.
isImm
(
)
)
{
if
(
Offset
.
getImm
(
)
)
O
<<
" + #"
<<
Offset
.
getImm
(
)
;
}
else
llvm_unreachable
(
"Unimplemented"
)
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .

Hexagon
Hexagon
0
1
"Unimplemented"
" + #"
"Unimplemented"


<s> const char * mcore_output_cmov ( rtx operands [ ] , int cmp_t , const char * test ) { int load_value ; int adjust_value ; rtx out_operands [ 4 ] ; out_operands [ 0 ] = operands [ 0 ] ; if ( const_ok_for_mcore ( INTVAL ( operands [ 1 ] ) ) ) { out_operands [ 1 ] = operands [ 1 ] ; out_operands [ 2 ] = operands [ 2 ] ; } else if ( const_ok_for_mcore ( INTVAL ( operands [ 2 ] ) ) ) { out_operands [ 1 ] = operands [ 2 ] ; out_operands [ 2 ] = operands [ 1 ] ; cmp_t = ( cmp_t == 0 ) ; } load_value = INTVAL ( out_operands [ 1 ] ) ; adjust_value = INTVAL ( out_operands [ 2 ] ) ; if ( test ) output_asm_insn ( test , operands ) ; if ( load_value >= 0 && load_value <= 127 ) output_asm_insn ( "movi\t%0,%1" , out_operands ) ; else if ( ( load_value & ( load_value - 1 ) ) == 0 ) output_asm_insn ( "bgeni\t%0,%P1" , out_operands ) ; else if ( ( load_value & ( load_value + 1 ) ) == 0 ) output_asm_insn ( "bmaski\t%0,%N1" , out_operands ) ; if ( load_value > adjust_value ) { if ( cmp_t ) output_asm_insn ( "decf\t%0" , out_operands ) ; else output_asm_insn ( "dect\t%0" , out_operands ) ; } else { if ( cmp_t ) output_asm_insn ( "incf\t%0" , out_operands ) ; else output_asm_insn ( "inct\t%0" , out_operands ) ; } return "" ; } </s>

Output a conditional move of two constants that are +/- 1 within each other . See the `` movtK '' patterns in mcore.md . I 'm not sure this is really worth the effort .


<s> SDNode * SITargetLowering :: PostISelFolding ( MachineSDNode * Node , SelectionDAG & DAG ) const { const SIInstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; unsigned Opcode = Node -> getMachineOpcode ( ) ; if ( TII -> isMIMG ( Opcode ) && ! TII -> get ( Opcode ) . mayStore ( ) && ! TII -> isGather4 ( Opcode ) ) { return adjustWritemask ( Node , DAG ) ; } if ( Opcode == AMDGPU :: INSERT_SUBREG || Opcode == AMDGPU :: REG_SEQUENCE ) { legalizeTargetIndependentNode ( Node , DAG ) ; return Node ; } switch ( Opcode ) { case AMDGPU :: V_DIV_SCALE_F32 : case AMDGPU :: V_DIV_SCALE_F64 : { SDValue Src0 = Node -> getOperand ( 0 ) ; SDValue Src1 = Node -> getOperand ( 1 ) ; SDValue Src2 = Node -> getOperand ( 2 ) ; if ( ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) != AMDGPU :: IMPLICIT_DEF ) && ( Src0 == Src1 || Src0 == Src2 ) ) break ; MVT VT = Src0 . getValueType ( ) . getSimpleVT ( ) ; const TargetRegisterClass * RC = getRegClassFor ( VT , Src0 . getNode ( ) -> isDivergent ( ) ) ; MachineRegisterInfo & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue UndefReg = DAG . getRegister ( MRI . createVirtualRegister ( RC ) , VT ) ; SDValue ImpDef = DAG . getCopyToReg ( DAG . getEntryNode ( ) , SDLoc ( Node ) , UndefReg , Src0 , SDValue ( ) ) ; if ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) == AMDGPU :: IMPLICIT_DEF ) { if ( Src1 . isMachineOpcode ( ) && Src1 . getMachineOpcode ( ) != AMDGPU :: IMPLICIT_DEF ) Src0 = Src1 ; else if ( Src2 . isMachineOpcode ( ) && Src2 . getMachineOpcode ( ) != AMDGPU :: IMPLICIT_DEF ) Src0 = Src2 ; else { assert ( Src1 . getMachineOpcode ( ) == AMDGPU :: IMPLICIT_DEF ) ; Src0 = UndefReg ; Src1 = UndefReg ; } } else break ; SmallVector < SDValue , 4 > Ops = { Src0 , Src1 , Src2 } ; for ( unsigned I = 3 , N = Node -> getNumOperands ( ) ; I != N ; ++ I ) Ops . push_back ( Node -> getOperand ( I ) ) ; Ops . push_back ( ImpDef . getValue ( 1 ) ) ; return DAG . getMachineNode ( Opcode , SDLoc ( Node ) , Node -> getVTList ( ) , Ops ) ; } default : break ; } return Node ; } </s>

Fold the instructions after selecting them .


"Missing call preserved mask for calling convention"

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


<s> FastISel * ARM64TargetLowering :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) const { return ARM64 :: createFastISel ( funcInfo , libInfo ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


Register to register moves are cheap if both are general registers .


<s> std :: pair < SDValue , SDValue > SystemZSelectionDAGInfo :: EmitTargetCodeForStrcmp ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Src1 , SDValue Src2 , MachinePointerInfo Op1PtrInfo , MachinePointerInfo Op2PtrInfo ) const { SDVTList VTs = DAG . getVTList ( Src1 . getValueType ( ) , MVT :: i32 , MVT :: Other ) ; SDValue Unused = DAG . getNode ( SystemZISD :: STRCMP , DL , VTs , Chain , Src1 , Src2 , DAG . getConstant ( 0 , DL , MVT :: i32 ) ) ; SDValue CCReg = Unused . getValue ( 1 ) ; Chain = Unused . getValue ( 2 ) ; return std :: make_pair ( addIPMSequence ( DL , CCReg , DAG ) , Chain ) ; } </s>

Emit target-specific code that performs a strcmp , in cases where that is faster than a libcall .


<s> bool isImm ( ) const override { return Kind == k_Immediate ; } </s>


<s> SITargetLowering :: ConstraintType SITargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 's' : case 'v' : case 'a' : return C_RegisterClass ; } } if ( isImmConstraint ( Constraint ) ) { return C_Other ; } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> bool WebAssembly :: isCatch ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { case WebAssembly :: CATCH_I32 : case WebAssembly :: CATCH_I32_S : case WebAssembly :: CATCH_I64 : case WebAssembly :: CATCH_I64_S : case WebAssembly :: CATCH_ALL : case WebAssembly :: CATCH_ALL_S : return true ; default : return false ; } } </s>

Return 'true ' if the clause and index Idx is a catch clause .


<s> const DenseSet < StringRef > & getAttributes ( ) const override { return Attributes ; } </s>

Return the attribute set for this global .


<s> void or1k_expand_compare ( rtx * operands ) { rtx sr_f = gen_rtx_REG ( BImode , SR_F_REGNUM ) ; rtx righthand_op = XEXP ( operands [ 0 ] , 1 ) ; rtx_code cmp_code = GET_CODE ( operands [ 0 ] ) ; bool flag_check_ne = true ; if ( ! TARGET_SFIMM && CONST_INT_P ( righthand_op ) ) XEXP ( operands [ 0 ] , 1 ) = force_reg ( SImode , righthand_op ) ; switch ( cmp_code ) { case LTGT : cmp_code = UNEQ ; flag_check_ne = false ; break ; case ORDERED : cmp_code = UNORDERED ; flag_check_ne = false ; break ; default : break ; } PUT_MODE ( operands [ 0 ] , BImode ) ; PUT_CODE ( operands [ 0 ] , cmp_code ) ; emit_insn ( gen_rtx_SET ( sr_f , operands [ 0 ] ) ) ; operands [ 0 ] = flag_check_ne ? gen_rtx_NE ( VOIDmode , sr_f , const0_rtx ) : gen_rtx_EQ ( VOIDmode , sr_f , const0_rtx ) ; operands [ 1 ] = sr_f ; operands [ 2 ] = const0_rtx ; } </s>

Used to expand patterns `` movsicc '' , `` movqicc '' , `` movhicc '' , `` cstoresi4 '' and `` cbranchsi4 '' . Expands a comparison where OPERANDS is an array of RTX describing the comparison . The first argument OPERANDS [ 0 ] is the operator and OPERANDS [ 1 ] and OPERANDS [ 2 ] are the operands . Split out the compare into SR [ F ] and return a new operation in OPERANDS [ 0 ] . The inputs OPERANDS [ 1 ] and OPERANDS [ 2 ] are not directly used , only overridden .


<s> static machine_mode rs6000_c_mode_for_suffix ( char suffix ) { if ( TARGET_FLOAT128 ) { if ( suffix == 'q' || suffix == 'Q' ) return ( FLOAT128_IEEE_P ( TFmode ) ) ? TFmode : KFmode ; } return VOIDmode ; } </s>


<s>
static
void
mmix_output_octa
(
FILE
*
stream
,
HOST_WIDEST_INT
value
,
int
do_begin_end
)
{
char
hex_format
[
sizeof
(
HOST_WIDEST_INT_PRINT_HEX
)
]
;
if
(
do_begin_end
)
fprintf
(
stream
,
"\tOCTA "
)
;
strcpy
(
hex_format
,
HOST_WIDEST_INT_PRINT_HEX
)
;
hex_format
[
0
]
=
'#'
;
hex_format
[
1
]
=
'0'
;
if
(
(
value
<
(
HOST_WIDEST_INT
)
0
&&
value
>
(
HOST_WIDEST_INT
)
10000
)
||
(
value
>=
(
HOST_WIDEST_INT
)
0
&&
value
<=
(
HOST_WIDEST_INT
)
16384
)
)
fprintf
(
stream
,
"%d"
,
(
int
)
value
)
;
else
if
(
value
>
(
HOST_WIDEST_INT
)
0
&&
value
<
(
(
HOST_WIDEST_INT
)
1
<<
31
)
*
2
)
fprintf
(
stream
,
"#%x"
,
(
unsigned
int
)
value
)
;
else
fprintf
(
stream
,
hex_format
,
value
)
;
if
(
do_begin_end
)
fprintf
(
stream
,
"\n"
)
;
}
</s>

Print a 64-bit value , optionally prefixed by assembly pseudo .


<s> void KudeyarInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIdx ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; BuildMI ( MBB , MI , DL , get ( Kudeyar :: MOV_RM32 ) ) . addReg ( DestReg ) . addFrameIndex ( FrameIdx ) . addImm ( 0 ) . addMemOperand ( MMO ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> ARMTargetLowering :: ConstraintType ARMTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'l' : return C_RegisterClass ; case 'w' : return C_RegisterClass ; case 'h' : return C_RegisterClass ; case 'x' : return C_RegisterClass ; case 't' : return C_RegisterClass ; case 'j' : return C_Other ; case 'Q' : return C_Memory ; } } else if ( Constraint . size ( ) == 2 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'U' : return C_Memory ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>


<s> void TGSIDAGToDAGISel :: Select ( SDNode * n ) { SDLoc dl ( n ) ; switch ( n -> getOpcode ( ) ) { case ISD :: FrameIndex : { int fi = cast < FrameIndexSDNode > ( n ) -> getIndex ( ) ; SDValue tfi = CurDAG -> getTargetFrameIndex ( fi , MVT :: i32 ) ; ReplaceNode ( n , tfi . getNode ( ) ) ; return ; } case ISD :: GlobalAddress : { const GlobalValue * gv = cast < GlobalAddressSDNode > ( n ) -> getGlobal ( ) ; SDValue tga = CurDAG -> getTargetGlobalAddress ( gv , dl , MVT :: i32 ) ; ReplaceNode ( n , tga . getNode ( ) ) ; return ; } } SelectCode ( n ) ; } </s>

Main hook for targets to transform nodes into machine nodes .

TGSI TGSI ISD::FrameIndex MVT::i32 ISD::GlobalAddress MVT::i32


"Instr doesn't have FrameIndex operand!"

"Unconditionally using R28 for evil purposes Offset: "

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static unsigned HOST_WIDE_INT tilegx_shift_truncation_mask ( machine_mode mode ) { return mode == DImode ? 63 : 0 ; } </s>

Implement TARGET_SHIFT_TRUNCATION_MASK . DImode shifts use the mode matching insns and therefore guarantee that the shift count is modulo 64 . SImode shifts sometimes use the 64 bit version so do not hold such guarantee .


<s> const MCFixupKindInfo & AMDGPUAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ AMDGPU :: NumTargetFixupKinds ] = { { "fixup_si_sopp_br" , 0 , 16 , MCFixupKindInfo :: FKF_IsPCRel } , { "fixup_si_rodata" , 0 , 32 , MCFixupKindInfo :: FKF_IsPCRel } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } </s>


<s> void ARMELFStreamer :: Reset ( ) { ExTab = NULL ; FnStart = NULL ; Personality = NULL ; PersonalityIndex = ARM :: EHABI :: NUM_PERSONALITY_INDEX ; FPReg = ARM :: SP ; FPOffset = 0 ; SPOffset = 0 ; PendingOffset = 0 ; UsedFP = false ; CantUnwind = false ; Opcodes . clear ( ) ; UnwindOpAsm . Reset ( ) ; } </s>


<s> static rtx adjust_operand ( rtx op , HOST_WIDE_INT * start ) { machine_mode mode ; int op_size ; if ( GET_CODE ( op ) == SUBREG && ( GET_MODE_BITSIZE ( GET_MODE ( op ) ) > GET_MODE_BITSIZE ( GET_MODE ( SUBREG_REG ( op ) ) ) ) ) { if ( start ) * start -= GET_MODE_BITSIZE ( GET_MODE ( op ) ) - GET_MODE_BITSIZE ( GET_MODE ( SUBREG_REG ( op ) ) ) ; op = SUBREG_REG ( op ) ; } op_size = GET_MODE_BITSIZE ( GET_MODE ( op ) ) ; if ( op_size < 32 ) { if ( start ) * start += 32 - op_size ; op_size = 32 ; } mode = int_mode_for_size ( op_size , 0 ) . require ( ) ; if ( mode != GET_MODE ( op ) ) op = gen_rtx_SUBREG ( mode , op , 0 ) ; return op ; } </s>

When insv and ext [ sz ] v ar passed a TI SUBREG , we want to strip it off and adjust the start offset .


"ARM constant island placement and branch shortening pass"

getPassName - Return a nice clean name for a pass .


<s> MachineBasicBlock :: iterator LEGFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( I -> getOpcode ( ) == LEG :: ADJCALLSTACKUP || I -> getOpcode ( ) == LEG :: ADJCALLSTACKDOWN ) { return MBB . erase ( I ) ; } return I ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

LEG LEG LEG::ADJCALLSTACKUP LEG::ADJCALLSTACKDOWN


<s> virtual const LC3bInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> RegisterBankInfo :: InstructionMappings AMDGPURegisterBankInfo :: getInstrAlternativeMappings ( const MachineInstr & MI ) const { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned Size = getSizeInBits ( MI . getOperand ( 0 ) . getReg ( ) , MRI , * TRI ) ; InstructionMappings AltMappings ; switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_LOAD : { const InstructionMapping & SSMapping = getInstructionMapping ( 1 , 1 , getOperandsMapping ( { AMDGPU :: getValueMapping ( AMDGPU :: SGPRRegBankID , Size ) , AMDGPU :: getValueMapping ( AMDGPU :: SGPRRegBankID , 64 ) } ) , 2 ) ; AltMappings . push_back ( & SSMapping ) ; const InstructionMapping & VVMapping = getInstructionMapping ( 2 , 1 , getOperandsMapping ( { AMDGPU :: getValueMapping ( AMDGPU :: VGPRRegBankID , Size ) , AMDGPU :: getValueMapping ( AMDGPU :: VGPRRegBankID , 64 ) } ) , 2 ) ; AltMappings . push_back ( & VVMapping ) ; const InstructionMapping & VSMapping = getInstructionMapping ( 3 , 1 , getOperandsMapping ( { AMDGPU :: getValueMapping ( AMDGPU :: VGPRRegBankID , Size ) , AMDGPU :: getValueMapping ( AMDGPU :: SGPRRegBankID , 64 ) } ) , 2 ) ; AltMappings . push_back ( & VSMapping ) ; return AltMappings ; } default : break ; } return RegisterBankInfo :: getInstrAlternativeMappings ( MI ) ; } </s>


<s> void nds32_expand_prologue_v3push ( void ) { int fp_adjust ; int sp_adjust ; rtx Rb , Re ; rtx fp_adjust_insn , sp_adjust_insn ; nds32_compute_stack_frame ( ) ; if ( cfun -> machine -> naked_p ) return ; Rb = gen_rtx_REG ( SImode , cfun -> machine -> callee_saved_first_gpr_regno ) ; Re = gen_rtx_REG ( SImode , cfun -> machine -> callee_saved_last_gpr_regno ) ; sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes ; if ( satisfies_constraint_Iu08 ( GEN_INT ( sp_adjust ) ) && NDS32_DOUBLE_WORD_ALIGN_P ( sp_adjust ) ) { nds32_emit_stack_v3push ( Rb , Re , GEN_INT ( 14 ) , GEN_INT ( sp_adjust ) ) ; if ( frame_pointer_needed ) { fp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size + sp_adjust ; fp_adjust_insn = gen_addsi3 ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( fp_adjust ) ) ; fp_adjust_insn = emit_insn ( fp_adjust_insn ) ; } } else { nds32_emit_stack_v3push ( Rb , Re , GEN_INT ( 14 ) , GEN_INT ( 0 ) ) ; if ( frame_pointer_needed ) { fp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size ; fp_adjust_insn = gen_addsi3 ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( fp_adjust ) ) ; fp_adjust_insn = emit_insn ( fp_adjust_insn ) ; } sp_adjust = nds32_force_addi_stack_int ( ( - 1 ) * sp_adjust ) ; if ( sp_adjust ) { sp_adjust_insn = gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - 1 * sp_adjust ) ) ; sp_adjust_insn = emit_insn ( sp_adjust_insn ) ; RTX_FRAME_RELATED_P ( sp_adjust_insn ) = 1 ; } } emit_insn ( gen_blockage ( ) ) ; } </s>


<s> bool Mips16FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == Mips :: RA ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) MBB . addLiveIn ( Reg ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> bool SIInstrInfo :: shouldClusterMemOps ( MachineInstr & FirstLdSt , MachineInstr & SecondLdSt , unsigned NumLoads ) const { const MachineOperand * FirstDst = nullptr ; const MachineOperand * SecondDst = nullptr ; if ( ( isMUBUF ( FirstLdSt ) && isMUBUF ( SecondLdSt ) ) || ( isMTBUF ( FirstLdSt ) && isMTBUF ( SecondLdSt ) ) ) { FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: vdata ) ; SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: vdata ) ; } else if ( isSMRD ( FirstLdSt ) && isSMRD ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: sdst ) ; SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: sdst ) ; } else if ( isDS ( FirstLdSt ) && isDS ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: vdst ) ; SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: vdst ) ; } if ( ! FirstDst || ! SecondDst ) return false ; unsigned LoadClusterThreshold = 16 ; const MachineRegisterInfo & MRI = FirstLdSt . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * DstRC = MRI . getRegClass ( FirstDst -> getReg ( ) ) ; return ( NumLoads * DstRC -> getSize ( ) ) <= LoadClusterThreshold ; } </s>

Returns true if the two given memory operations should be scheduled adjacent .

AMDGPU SI AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName 16


<s> static inline bool equal ( tree_map * a , tree_map * b ) { return a -> base . from == b -> base . from ; } </s>


<s>
bool
RISCVAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
if
(
getSTI
(
)
.
getFeatureBits
(
)
[
RISCV
::
FeatureRelax
]
)
{
auto
*
Assembler
=
getTargetStreamer
(
)
.
getStreamer
(
)
.
getAssemblerPtr
(
)
;
if
(
Assembler
!=
nullptr
)
{
RISCVAsmBackend
&
MAB
=
static_cast
<
RISCVAsmBackend
&
>
(
Assembler
->
getBackend
(
)
)
;
MAB
.
setForceRelocs
(
)
;
}
}
Operands
.
push_back
(
RISCVOperand
::
createToken
(
Name
,
NameLoc
,
isRV64
(
)
)
)
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
return
false
;
if
(
parseOperand
(
Operands
,
Name
)
)
return
true
;
unsigned
OperandIdx
=
1
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
getLexer
(
)
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
)
return
true
;
++
OperandIdx
;
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
getParser
(
)
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
getParser
(
)
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

RISCV
RISCV
RISCV::FeatureRelax
RISCV
RISCV
RISCV
1
"unexpected token"


<s>
int
AArch64AsmParser
::
tryParseRegister
(
)
{
MCAsmParser
&
Parser
=
getParser
(
)
;
const
AsmToken
&
Tok
=
Parser
.
getTok
(
)
;
assert
(
Tok
.
is
(
AsmToken
::
Identifier
)
&&
"Token is not an Identifier"
)
;
std
::
string
lowerCase
=
Tok
.
getString
(
)
.
lower
(
)
;
unsigned
RegNum
=
matchRegisterNameAlias
(
lowerCase
,
false
)
;
if
(
RegNum
==
0
)
RegNum
=
StringSwitch
<
unsigned
>
(
lowerCase
)
.
Case
(
"fp"
,
AArch64
::
FP
)
.
Case
(
"lr"
,
AArch64
::
LR
)
.
Case
(
"x31"
,
AArch64
::
XZR
)
.
Case
(
"w31"
,
AArch64
::
WZR
)
.
Default
(
0
)
;
if
(
RegNum
==
0
)
return
1
;
Parser
.
Lex
(
)
;
return
RegNum
;
}
</s>

tryParseRegister - parse one register if possible


<s> static void frv_registers_update ( rtx x ) { regstate_t flags ; flags = REGSTATE_MODIFIED ; if ( GET_CODE ( x ) == COND_EXEC ) { flags |= frv_cond_flags ( XEXP ( x , 0 ) ) ; x = XEXP ( x , 1 ) ; } note_pattern_stores ( x , frv_registers_update_1 , & flags ) ; } </s>

Update the register state information for an instruction whose body is X .


<s> bool sh_cfun_trap_exit_p ( void ) { return ( lookup_attribute ( "trap_exit" , DECL_ATTRIBUTES ( current_function_decl ) ) == NULL_TREE ) ; } </s>

Returns true if the current function has a `` trap_exit '' attribute set .


<s>
bool
PPCCTRLoops
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
DEBUG
(
dbgs
(
)
<<
"********* PPC CTR Loops *********\n"
)
;
bool
Changed
=
false
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
TII
=
MF
.
getTarget
(
)
.
getInstrInfo
(
)
;
for
(
MachineLoopInfo
::
iterator
I
=
MLI
->
begin
(
)
,
E
=
MLI
->
end
(
)
;
I
!=
E
;
++
I
)
{
MachineLoop
*
L
=
*
I
;
if
(
!
L
->
getParentLoop
(
)
)
{
Changed
|=
convertToCTRLoop
(
L
)
;
}
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

PowerPC
PPC
"********* PPC CTR Loops *********\n"


<s> StringRef getPassName ( ) const override { return SNES_RELAX_MEM_OPS_NAME ; } </s>


<s> static rtx arm_gen_load_multiple_1 ( int count , int * regs , rtx * mems , rtx basereg , HOST_WIDE_INT wback_offset ) { int i = 0 , j ; rtx result ; if ( ! multiple_operation_profitable_p ( false , count , 0 ) ) { rtx seq ; start_sequence ( ) ; for ( i = 0 ; i < count ; i ++ ) emit_move_insn ( gen_rtx_REG ( SImode , regs [ i ] ) , mems [ i ] ) ; if ( wback_offset != 0 ) emit_move_insn ( basereg , plus_constant ( Pmode , basereg , wback_offset ) ) ; seq = get_insns ( ) ; end_sequence ( ) ; return seq ; } result = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count + ( wback_offset != 0 ? 1 : 0 ) ) ) ; if ( wback_offset != 0 ) { XVECEXP ( result , 0 , 0 ) = gen_rtx_SET ( VOIDmode , basereg , plus_constant ( Pmode , basereg , wback_offset ) ) ; i = 1 ; count ++ ; } for ( j = 0 ; i < count ; i ++ , j ++ ) XVECEXP ( result , 0 , i ) = gen_rtx_SET ( VOIDmode , gen_rtx_REG ( SImode , regs [ j ] ) , mems [ j ] ) ; return result ; } </s>

Generate a load-multiple instruction . COUNT is the number of loads in the instruction ; REGS and MEMS are arrays containing the operands . BASEREG is the base register to be used in addressing the memory operands . WBACK_OFFSET is nonzero if the instruction should update the base register .


"stack re-alignment, but LLVM couldn't handle it "

"(probably because it has a dynamic alloca)."

"SP has to be saved in order to align variable sized stack object!"

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> void ScheduleDAGPostRA :: initQueues ( ArrayRef < SUnit * > TopRoots , ArrayRef < SUnit * > BotRoots ) { for ( SmallVectorImpl < SUnit * > :: const_iterator I = TopRoots . begin ( ) , E = TopRoots . end ( ) ; I != E ; ++ I ) { SchedImpl -> releaseTopNode ( * I ) ; } for ( SmallVectorImpl < SUnit * > :: const_reverse_iterator I = BotRoots . rbegin ( ) , E = BotRoots . rend ( ) ; I != E ; ++ I ) { SchedImpl -> releaseBottomNode ( * I ) ; } releaseSuccessors ( & EntrySU ) ; releasePredecessors ( & ExitSU ) ; SchedImpl -> registerRoots ( ) ; CurrentTop = nextIfDebug ( RegionBegin , RegionEnd ) ; CurrentBottom = RegionEnd ; TopBundleMIs . clear ( ) ; BottomBundleMIs . clear ( ) ; } </s>

Release ExitSU predecessors and setup scheduler queues .


<s> SMLoc getEndLoc ( ) const { return End ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> bool cris_return_address_on_stack ( void ) { return regs_ever_live [ CRIS_SRP_REGNUM ] || cfun -> machine -> needs_return_address_on_stack ; } </s>

Accessor used in cris.md : return because cfun- > machine is n't available there .


<s>
bool
SNESInstrInfo
::
isBranchOffsetInRange
(
unsigned
BranchOp
,
int64_t
BrOffset
)
const
{
switch
(
BranchOp
)
{
default
:
llvm_unreachable
(
"unexpected opcode!"
)
;
case
SNES
::
JMPk
:
case
SNES
::
CALLk
:
assert
(
BrOffset
>=
0
&&
"offset must be absolute address"
)
;
return
isUIntN
(
16
,
BrOffset
)
;
case
SNES
::
RCALLk
:
case
SNES
::
RJMPk
:
return
isIntN
(
13
,
BrOffset
)
;
case
SNES
::
BRBSsk
:
case
SNES
::
BRBCsk
:
case
SNES
::
BREQk
:
case
SNES
::
BRNEk
:
case
SNES
::
BRSHk
:
case
SNES
::
BRLOk
:
case
SNES
::
BRMIk
:
case
SNES
::
BRPLk
:
case
SNES
::
BRGEk
:
case
SNES
::
BRLTk
:
return
isIntN
(
7
,
BrOffset
)
;
}
}
</s>

Determine if the branch target is in range .

SNES
SNES
"unexpected opcode!"
SNES::JMPk
SNES::CALLk
0
"offset must be absolute address"
16
SNES::RCALLk
SNES::RJMPk
13
SNES::BRBSsk
SNES::BRBCsk
SNES::BREQk
SNES::BRNEk
SNES::BRSHk
SNES::BRLOk
SNES::BRMIk
SNES::BRPLk
SNES::BRGEk
SNES::BRLTk
7


<s>
unsigned
ARMBaseInstrInfo
::
getPartialRegUpdateClearance
(
const
MachineInstr
*
MI
,
unsigned
OpNum
,
const
TargetRegisterInfo
*
TRI
)
const
{
if
(
!
SwiftPartialUpdateClearance
||
!
(
Subtarget
.
isSwift
(
)
||
Subtarget
.
isCortexA15
(
)
)
)
return
0
;
assert
(
TRI
&&
"Need TRI instance"
)
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNum
)
;
if
(
MO
.
readsReg
(
)
)
return
0
;
unsigned
Reg
=
MO
.
getReg
(
)
;
int
UseOp
=
1
;
switch
(
MI
->
getOpcode
(
)
)
{
case
ARM
::
VLDRS
:
case
ARM
::
FCONSTS
:
case
ARM
::
VMOVSR
:
case
ARM
::
VMOVv8i8
:
case
ARM
::
VMOVv4i16
:
case
ARM
::
VMOVv2i32
:
case
ARM
::
VMOVv2f32
:
case
ARM
::
VMOVv1i64
:
UseOp
=
MI
->
findRegisterUseOperandIdx
(
Reg
,
false
,
TRI
)
;
break
;
case
ARM
::
VLD1LNd32
:
UseOp
=
3
;
break
;
default
:
return
0
;
}
if
(
UseOp
!=
1
&&
MI
->
getOperand
(
UseOp
)
.
readsReg
(
)
)
return
0
;
if
(
TargetRegisterInfo
::
isVirtualRegister
(
Reg
)
)
{
if
(
!
MO
.
getSubReg
(
)
||
MI
->
readsVirtualRegister
(
Reg
)
)
return
0
;
}
else
if
(
ARM
::
SPRRegClass
.
contains
(
Reg
)
)
{
unsigned
DReg
=
TRI
->
getMatchingSuperReg
(
Reg
,
ARM
::
ssub_0
,
&
ARM
::
DPRRegClass
)
;
if
(
!
DReg
||
!
MI
->
definesRegister
(
DReg
,
TRI
)
)
return
0
;
}
return
SwiftPartialUpdateClearance
;
}
</s>

Inform the BreakFalseDeps pass how many idle instructions we would like before a partial register update .


<s> static inline bool ia64_reg_ok_for_base_p ( const_rtx reg , bool strict ) { if ( strict && REGNO_OK_FOR_BASE_P ( REGNO ( reg ) ) ) return true ; else if ( ! strict && ( GENERAL_REGNO_P ( REGNO ( reg ) ) || ! HARD_REGISTER_P ( reg ) ) ) return true ; else return false ; } </s>

Returns true if REG ( assumed to be a ` reg ' RTX ) is valid for use as a base register .


<s> void Warning ( SMLoc L , const Twine & Msg ) { Parser . Warning ( L , Msg ) ; } </s>

Emit a warning at the location L , with the message Msg .


<s> bool Cpu0PassConfig :: addPreRegAlloc ( ) { addPass ( createCpu0EmitGPRestorePass ( getCpu0TargetMachine ( ) ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


Register the Visium-specific libfuncs with the middle-end .


<s> int loongarch_idiv_insns ( machine_mode mode ATTRIBUTE_UNUSED ) { int count ; count = 1 ; if ( loongarch_check_zero_div_p ( ) ) count += 2 ; return count ; } </s>

Return the number of instructions needed for an integer division .


<s> SDValue PPCTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { if ( Subtarget . isSVR4ABI ( ) ) { if ( Subtarget . isPPC64 ( ) ) return LowerFormalArguments_64SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; else return LowerFormalArguments_32SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } else { return LowerFormalArguments_Darwin ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


"unexpected token in argument list (first)"

ParseInstruction - Parse one assembly instruction .


<s> static rtx aarch64_struct_value_rtx ( tree fndecl ATTRIBUTE_UNUSED , int incoming ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( Pmode , AARCH64_STRUCT_VALUE_REGNUM ) ; } </s>


<s> std :: unique_ptr < MCObjectWriter > J2AsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { auto MOTW = llvm :: make_unique < J2ELFObjectWriter > ( MCELFObjectTargetWriter :: getOSABI ( OSType ) , ELF :: EM_J2 ) ; return createELFObjectWriter ( std :: move ( MOTW ) , OS , true ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> void MipsSETargetLowering :: getOpndList ( SmallVectorImpl < SDValue > & Ops , std :: deque < std :: pair < unsigned , SDValue > > & RegsToPass , bool IsPICCall , bool GlobalOrExternal , bool InternalLinkage , CallLoweringInfo & CLI , SDValue Callee , SDValue Chain ) const { Ops . push_back ( Callee ) ; MipsTargetLowering :: getOpndList ( Ops , RegsToPass , IsPICCall , GlobalOrExternal , InternalLinkage , CLI , Callee , Chain ) ; } </s>

This function fills Ops , which is the list of operands that will later be used when a function call node is created .