<s> bool SIInstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Cond , unsigned TrueReg , unsigned FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { switch ( Cond [ 0 ] . getImm ( ) ) { case VCCNZ : case VCCZ : { const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = MRI . getRegClass ( TrueReg ) ; assert ( MRI . getRegClass ( FalseReg ) == RC ) ; int NumInsts = AMDGPU :: getRegBitWidth ( RC -> getID ( ) ) / 32 ; CondCycles = TrueCycles = FalseCycles = NumInsts ; return RI . hasVGPRs ( RC ) && NumInsts <= 6 ; } case SCC_TRUE : case SCC_FALSE : { const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = MRI . getRegClass ( TrueReg ) ; assert ( MRI . getRegClass ( FalseReg ) == RC ) ; int NumInsts = AMDGPU :: getRegBitWidth ( RC -> getID ( ) ) / 32 ; if ( NumInsts % 2 == 0 ) NumInsts /= 2 ; CondCycles = TrueCycles = FalseCycles = NumInsts ; return RI . isSGPRClass ( RC ) ; } default : return false ; } } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


"Can only insert epilog into returning blocks"


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static insn_info * extract_single_source ( set_info * set ) { if ( ! set ) return nullptr ; if ( set -> insn ( ) -> is_real ( ) ) return set -> insn ( ) ; if ( ! set -> insn ( ) -> is_phi ( ) ) return nullptr ; hash_set < set_info * > sets = get_all_sets ( set , true , false , true ) ; insn_info * first_insn = ( * sets . begin ( ) ) -> insn ( ) ; if ( first_insn -> is_artificial ( ) ) return nullptr ; for ( const set_info * set : sets ) { if ( set -> insn ( ) -> is_artificial ( ) ) return nullptr ; if ( ! source_equal_p ( set -> insn ( ) , first_insn ) ) return nullptr ; } return first_insn ; } </s>

Helper function to get single same real RTL source . return NULL if it is not a single real RTL source .


<s> virtual const MCSection * getSectionForConstant ( SectionKind Kind ) const { return ReadOnlySection ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> void Z80FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setMaxCallFrameSize ( 0 ) ; if ( MFI . estimateStackSize ( MF ) > 0x80 ) RS -> addScavengingFrameIndex ( MFI . CreateStackObject ( SlotSize , 1 , false ) ) ; } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> std :: pair < unsigned , const TargetRegisterClass * > ARM64TargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & ARM64 :: GPR64commonRegClass ) ; return std :: make_pair ( 0U , & ARM64 :: GPR32commonRegClass ) ; case 'w' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , & ARM64 :: FPR32RegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & ARM64 :: FPR64RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & ARM64 :: FPR128RegClass ) ; break ; case 'x' : if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & ARM64 :: FPR128_loRegClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( ARM64 :: NZCV ) , & ARM64 :: CCRRegClass ) ; std :: pair < unsigned , const TargetRegisterClass * > Res ; Res = TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; if ( ! Res . second ) { unsigned Size = Constraint . size ( ) ; if ( ( Size == 4 || Size == 5 ) && Constraint [ 0 ] == '{' && tolower ( Constraint [ 1 ] ) == 'v' && Constraint [ Size - 1 ] == '}' ) { const std :: string Reg = std :: string ( & Constraint [ 2 ] , & Constraint [ Size - 1 ] ) ; int RegNo = atoi ( Reg . c_str ( ) ) ; if ( RegNo >= 0 && RegNo <= 31 ) { Res . first = ARM64 :: FPR128RegClass . getRegister ( RegNo ) ; Res . second = & ARM64 :: FPR128RegClass ; } } } return Res ; } </s>

Given a physical register constraint ( e.g .


<s> static int ix86_simd_clone_usable ( struct cgraph_node * node ) { switch ( node -> simdclone -> vecsize_mangle ) { case 'b' : if ( ! TARGET_SSE2 ) return - 1 ; if ( ! TARGET_AVX ) return 0 ; return TARGET_AVX2 ? 2 : 1 ; case 'c' : if ( ! TARGET_AVX ) return - 1 ; return TARGET_AVX2 ? 1 : 0 ; break ; case 'd' : if ( ! TARGET_AVX2 ) return - 1 ; return 0 ; case 'e' : if ( ! TARGET_AVX512F ) return - 1 ; return 0 ; default : gcc_unreachable ( ) ; } } </s>

If SIMD clone NODE ca n't be used in a vectorized loop in current function , return -1 , otherwise return a badness of using it ( 0 if it is most desirable from vecsize_mangle point of view , 1 slightly less desirable , etc . ) .


<s> bool HexagonAsmPrinter :: isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { if ( MBB -> hasAddressTaken ( ) ) { return false ; } return AsmPrinter :: isBlockOnlyReachableByFallthrough ( MBB ) ; } </s>

isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


<s> ChangeStatus manifest ( Attributor & A ) override { SmallVector < Attribute , 8 > AttrList ; Function * F = getAssociatedFunction ( ) ; LLVMContext & Ctx = F -> getContext ( ) ; auto & InfoCache = static_cast < AMDGPUInformationCache & > ( A . getInfoCache ( ) ) ; unsigned Min , Max ; std :: tie ( Min , Max ) = InfoCache . getMaximumFlatWorkGroupRange ( * F ) ; if ( getAssumed ( ) . getLower ( ) == Min && getAssumed ( ) . getUpper ( ) - 1 == Max ) return ChangeStatus :: UNCHANGED ; SmallString < 10 > Buffer ; raw_svector_ostream OS ( Buffer ) ; OS << getAssumed ( ) . getLower ( ) << ',' << getAssumed ( ) . getUpper ( ) - 1 ; AttrList . push_back ( Attribute :: get ( Ctx , "amdgpu-flat-work-group-size" , OS . str ( ) ) ) ; return IRAttributeManifest :: manifestAttrs ( A , getIRPosition ( ) , AttrList , true ) ; } </s>

See AbstractAttribute : :manifest ( ... ) .


<s> static unsigned findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const TargetRegisterInfo & TRI , bool Is64Bit ) { const MachineFunction * MF = MBB . getParent ( ) ; const Function * F = MF -> getFunction ( ) ; if ( ! F || MF -> getMMI ( ) . callsEHReturn ( ) ) return 0 ; static const uint16_t CallerSavedRegs32Bit [ ] = { X86 :: EAX , X86 :: EDX , X86 :: ECX , 0 } ; static const uint16_t CallerSavedRegs64Bit [ ] = { X86 :: RAX , X86 :: RDX , X86 :: RCX , X86 :: RSI , X86 :: RDI , X86 :: R8 , X86 :: R9 , X86 :: R10 , X86 :: R11 , 0 } ; unsigned Opc = MBBI -> getOpcode ( ) ; switch ( Opc ) { default : return 0 ; case X86 :: RETL : case X86 :: RETQ : case X86 :: RETIL : case X86 :: RETIQ : case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: TCRETURNmi64 : case X86 :: EH_RETURN : case X86 :: EH_RETURN64 : { SmallSet < uint16_t , 8 > Uses ; for ( unsigned i = 0 , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , & TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } const uint16_t * CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit ; for ( ; * CS ; ++ CS ) if ( ! Uses . count ( * CS ) ) return * CS ; } } return 0 ; } </s>

findDeadCallerSavedReg - Return a caller-saved register that is n't live when it reaches the `` return '' instruction .


<s> unsigned getNumFixupKinds ( ) const override { return RISCV :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s>
void
BPFDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
DEBUG
(
dbgs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;
return
;
}
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
SDIV
:
{
DebugLoc
Empty
;
const
DebugLoc
&
DL
=
Node
->
getDebugLoc
(
)
;
if
(
DL
!=
Empty
)
errs
(
)
<<
"Error at line "
<<
DL
.
getLine
(
)
<<
": "
;
else
errs
(
)
<<
"Error: "
;
errs
(
)
<<
"Unsupport signed division for DAG: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"Please convert to unsigned div/mod.\n"
;
break
;
}
case
ISD
::
INTRINSIC_W_CHAIN
:
{
unsigned
IntNo
=
cast
<
ConstantSDNode
>
(
Node
->
getOperand
(
1
)
)
->
getZExtValue
(
)
;
switch
(
IntNo
)
{
case
Intrinsic
::
bpf_load_byte
:
case
Intrinsic
::
bpf_load_half
:
case
Intrinsic
::
bpf_load_word
:
{
SDLoc
DL
(
Node
)
;
SDValue
Chain
=
Node
->
getOperand
(
0
)
;
SDValue
N1
=
Node
->
getOperand
(
1
)
;
SDValue
Skb
=
Node
->
getOperand
(
2
)
;
SDValue
N3
=
Node
->
getOperand
(
3
)
;
SDValue
R6Reg
=
CurDAG
->
getRegister
(
BPF
::
R6
,
MVT
::
i64
)
;
Chain
=
CurDAG
->
getCopyToReg
(
Chain
,
DL
,
R6Reg
,
Skb
,
SDValue
(
)
)
;
Node
=
CurDAG
->
UpdateNodeOperands
(
Node
,
Chain
,
N1
,
R6Reg
,
N3
)
;
break
;
}
}
break
;
}
case
ISD
::
FrameIndex
:
{
int
FI
=
cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
EVT
VT
=
Node
->
getValueType
(
0
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
VT
)
;
unsigned
Opc
=
BPF
::
MOV_rr
;
if
(
Node
->
hasOneUse
(
)
)
{
CurDAG
->
SelectNodeTo
(
Node
,
Opc
,
VT
,
TFI
)
;
return
;
}
ReplaceNode
(
Node
,
CurDAG
->
getMachineNode
(
Opc
,
SDLoc
(
Node
)
,
VT
,
TFI
)
)
;
return
;
}
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> const char * HexagonTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( HexagonISD :: NodeType ) Opcode ) { case HexagonISD :: ALLOCA : return "HexagonISD::ALLOCA" ; case HexagonISD :: AT_GOT : return "HexagonISD::AT_GOT" ; case HexagonISD :: AT_PCREL : return "HexagonISD::AT_PCREL" ; case HexagonISD :: BARRIER : return "HexagonISD::BARRIER" ; case HexagonISD :: CALL : return "HexagonISD::CALL" ; case HexagonISD :: CALLnr : return "HexagonISD::CALLnr" ; case HexagonISD :: CALLR : return "HexagonISD::CALLR" ; case HexagonISD :: COMBINE : return "HexagonISD::COMBINE" ; case HexagonISD :: CONST32_GP : return "HexagonISD::CONST32_GP" ; case HexagonISD :: CONST32 : return "HexagonISD::CONST32" ; case HexagonISD :: CP : return "HexagonISD::CP" ; case HexagonISD :: DCFETCH : return "HexagonISD::DCFETCH" ; case HexagonISD :: EH_RETURN : return "HexagonISD::EH_RETURN" ; case HexagonISD :: TSTBIT : return "HexagonISD::TSTBIT" ; case HexagonISD :: EXTRACTU : return "HexagonISD::EXTRACTU" ; case HexagonISD :: INSERT : return "HexagonISD::INSERT" ; case HexagonISD :: JT : return "HexagonISD::JT" ; case HexagonISD :: RET_FLAG : return "HexagonISD::RET_FLAG" ; case HexagonISD :: TC_RETURN : return "HexagonISD::TC_RETURN" ; case HexagonISD :: VASL : return "HexagonISD::VASL" ; case HexagonISD :: VASR : return "HexagonISD::VASR" ; case HexagonISD :: VLSR : return "HexagonISD::VLSR" ; case HexagonISD :: VSPLAT : return "HexagonISD::VSPLAT" ; case HexagonISD :: VEXTRACTW : return "HexagonISD::VEXTRACTW" ; case HexagonISD :: VINSERTW0 : return "HexagonISD::VINSERTW0" ; case HexagonISD :: VROR : return "HexagonISD::VROR" ; case HexagonISD :: READCYCLE : return "HexagonISD::READCYCLE" ; case HexagonISD :: VZERO : return "HexagonISD::VZERO" ; case HexagonISD :: D2P : return "HexagonISD::D2P" ; case HexagonISD :: P2D : return "HexagonISD::P2D" ; case HexagonISD :: V2Q : return "HexagonISD::V2Q" ; case HexagonISD :: Q2V : return "HexagonISD::Q2V" ; case HexagonISD :: QCAT : return "HexagonISD::QCAT" ; case HexagonISD :: QTRUE : return "HexagonISD::QTRUE" ; case HexagonISD :: QFALSE : return "HexagonISD::QFALSE" ; case HexagonISD :: TYPECAST : return "HexagonISD::TYPECAST" ; case HexagonISD :: VALIGN : return "HexagonISD::VALIGN" ; case HexagonISD :: VALIGNADDR : return "HexagonISD::VALIGNADDR" ; case HexagonISD :: OP_END : break ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

Hexagon Hexagon HexagonISD::NodeType HexagonISD::ALLOCA "HexagonISD::ALLOCA" HexagonISD::AT_GOT "HexagonISD::AT_GOT" HexagonISD::AT_PCREL "HexagonISD::AT_PCREL" HexagonISD::BARRIER "HexagonISD::BARRIER" HexagonISD::CALL "HexagonISD::CALL" HexagonISD::CALLnr "HexagonISD::CALLnr" HexagonISD::CALLR "HexagonISD::CALLR" HexagonISD::COMBINE "HexagonISD::COMBINE" HexagonISD::CONST32_GP "HexagonISD::CONST32_GP" HexagonISD::CONST32 "HexagonISD::CONST32" HexagonISD::CP "HexagonISD::CP" HexagonISD::DCFETCH "HexagonISD::DCFETCH" HexagonISD::EH_RETURN "HexagonISD::EH_RETURN" HexagonISD::TSTBIT "HexagonISD::TSTBIT" HexagonISD::EXTRACTU "HexagonISD::EXTRACTU" HexagonISD::INSERT "HexagonISD::INSERT" HexagonISD::JT "HexagonISD::JT" HexagonISD::RET_FLAG "HexagonISD::RET_FLAG" HexagonISD::TC_RETURN "HexagonISD::TC_RETURN" HexagonISD::VASL "HexagonISD::VASL" HexagonISD::VASR "HexagonISD::VASR" HexagonISD::VLSR "HexagonISD::VLSR" HexagonISD::VSPLAT "HexagonISD::VSPLAT" HexagonISD::VEXTRACTW "HexagonISD::VEXTRACTW" HexagonISD::VINSERTW0 "HexagonISD::VINSERTW0" HexagonISD::VROR "HexagonISD::VROR" HexagonISD::READCYCLE "HexagonISD::READCYCLE" HexagonISD::VZERO "HexagonISD::VZERO" HexagonISD::D2P "HexagonISD::D2P" HexagonISD::P2D "HexagonISD::P2D" HexagonISD::V2Q "HexagonISD::V2Q" HexagonISD::Q2V "HexagonISD::Q2V" HexagonISD::QCAT "HexagonISD::QCAT" HexagonISD::QTRUE "HexagonISD::QTRUE" HexagonISD::QFALSE "HexagonISD::QFALSE" HexagonISD::TYPECAST "HexagonISD::TYPECAST" HexagonISD::VALIGN "HexagonISD::VALIGN" HexagonISD::VALIGNADDR "HexagonISD::VALIGNADDR" HexagonISD::OP_END


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> bool msp430_is_interrupt_func ( void ) { if ( current_function_decl == NULL ) return false ; return is_attr_func ( "interrupt" ) ; } </s>

Returns true if the current function has the `` interrupt '' attribute .


<s> static enum rtx_code ix86_prepare_sse_fp_compare_args ( rtx dest , enum rtx_code code , rtx * pop0 , rtx * pop1 ) { switch ( code ) { case LTGT : case UNEQ : if ( TARGET_AVX ) break ; return UNKNOWN ; case LT : case LE : case UNGT : case UNGE : break ; case EQ : case NE : case UNORDERED : case ORDERED : if ( TARGET_AVX ) break ; if ( ! dest || ! rtx_equal_p ( dest , * pop1 ) ) break ; case GE : case GT : case UNLE : case UNLT : std :: swap ( * pop0 , * pop1 ) ; code = swap_condition ( code ) ; break ; default : gcc_unreachable ( ) ; } return code ; } </s>

Swap , force into registers , or otherwise massage the two operands to an sse comparison with a mask result . Thus we differ a bit from ix86_prepare_fp_compare_args which expects to produce a flags result . The DEST operand exists to help determine whether to commute commutative operators . The POP0/POP1 operands are updated in place . The new comparison code is returned , or UNKNOWN if not implementable .


<s> void X86SolarisTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; } </s>

This method must be called before any actual lowering is done .


<s> static const struct mips_cpu_info * mips_cpu_info_from_isa ( int isa ) { unsigned int i ; for ( i = 0 ; i < ARRAY_SIZE ( mips_cpu_info_table ) ; i ++ ) if ( mips_cpu_info_table [ i ] . isa == isa ) return mips_cpu_info_table + i ; return NULL ; } </s>

Return the processor associated with the given ISA level , or null if the ISA is n't valid .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachinePostDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> void HexagonMCELFStreamer :: EmitInstruction ( const MCInst & MCB , const MCSubtargetInfo & STI ) { assert ( MCB . getOpcode ( ) == Hexagon :: BUNDLE ) ; assert ( HexagonMCInstrInfo :: bundleSize ( MCB ) <= HEXAGON_PACKET_SIZE ) ; assert ( HexagonMCInstrInfo :: bundleSize ( MCB ) > 0 ) ; for ( auto const & I : HexagonMCInstrInfo :: bundleInstructions ( MCB ) ) { MCInst * MCI = const_cast < MCInst * > ( I . getInst ( ) ) ; EmitSymbol ( * MCI ) ; } MCObjectStreamer :: EmitInstruction ( MCB , STI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .

Hexagon Hexagon Hexagon::BUNDLE Hexagon Hexagon 0 Hexagon


<s> EVT Cpu0TargetLowering :: getSetCCResultType ( const DataLayout & , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> static bool cr16_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { const HOST_WIDE_INT size = int_size_in_bytes ( type ) ; return ( ( size == - 1 ) || ( size > 8 ) ) ; } </s>

Implements hook TARGET_RETURN_IN_MEMORY .


<s> static const char * s390_mangle_fundamental_type ( tree type ) { if ( TYPE_MAIN_VARIANT ( type ) == long_double_type_node && TARGET_LONG_DOUBLE_128 ) return "g" ; return NULL ; } </s>


"Cannot store this register into a stack slot!"

Store the specified register of the given register class to the specified stack frame index .


<s> static bool mips_function_has_gp_insn ( void ) { if ( ! cfun -> machine -> has_gp_insn_p ) { rtx insn ; push_topmost_sequence ( ) ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER && ( get_attr_got ( insn ) != GOT_UNSET || small_data_pattern ( PATTERN ( insn ) , VOIDmode ) ) ) break ; pop_topmost_sequence ( ) ; cfun -> machine -> has_gp_insn_p = ( insn != 0 ) ; } return cfun -> machine -> has_gp_insn_p ; } </s>

Return true if the current function has an insn that implicitly refers to $ gp .


<s>
void
WaitcntBrackets
::
print
(
raw_ostream
&
OS
)
{
OS
<<
'\n'
;
for
(
auto
T
:
inst_counter_types
(
)
)
{
uint32_t
LB
=
getScoreLB
(
T
)
;
uint32_t
UB
=
getScoreUB
(
T
)
;
switch
(
T
)
{
case
VM_CNT
:
OS
<<
"    VM_CNT("
<<
UB
LB
<<
"): "
;
break
;
case
LGKM_CNT
:
OS
<<
"    LGKM_CNT("
<<
UB
LB
<<
"): "
;
break
;
case
EXP_CNT
:
OS
<<
"    EXP_CNT("
<<
UB
LB
<<
"): "
;
break
;
case
VS_CNT
:
OS
<<
"    VS_CNT("
<<
UB
LB
<<
"): "
;
break
;
default
:
OS
<<
"    UNKNOWN("
<<
UB
LB
<<
"): "
;
break
;
}
if
(
LB
<
UB
)
{
for
(
int
J
=
0
;
J
<=
getMaxVGPR
(
)
;
J
++
)
{
uint32_t
RegScore
=
getRegScore
(
J
,
T
)
;
if
(
RegScore
<=
LB
)
continue
;
uint32_t
RelScore
=
RegScore
LB
1
;
if
(
J
<
SQ_MAX_PGM_VGPRS
+
EXTRA_VGPR_LDS
)
{
OS
<<
RelScore
<<
":v"
<<
J
<<
" "
;
}
else
{
OS
<<
RelScore
<<
":ds "
;
}
}
if
(
T
==
LGKM_CNT
)
{
for
(
int
J
=
0
;
J
<=
getMaxSGPR
(
)
;
J
++
)
{
uint32_t
RegScore
=
getRegScore
(
J
+
NUM_ALL_VGPRS
,
LGKM_CNT
)
;
if
(
RegScore
<=
LB
)
continue
;
uint32_t
RelScore
=
RegScore
LB
1
;
OS
<<
RelScore
<<
":s"
<<
J
<<
" "
;
}
}
}
OS
<<
'\n'
;
}
OS
<<
'\n'
;
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> unsigned getImageHandleSymbolIndex ( const char * Symbol ) { for ( unsigned i = 0 , e = ImageHandleList . size ( ) ; i != e ; ++ i ) if ( ImageHandleList [ i ] == std :: string ( Symbol ) ) return i ; ImageHandleList . push_back ( Symbol ) ; return ImageHandleList . size ( ) - 1 ; } </s>

Returns the index for the symbol Symbol .


<s>
const
RegisterBankInfo
::
InstructionMapping
&
MipsRegisterBankInfo
::
getInstrMapping
(
const
MachineInstr
&
MI
)
const
{
unsigned
Opc
=
MI
.
getOpcode
(
)
;
const
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
const
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
const
RegisterBankInfo
::
InstructionMapping
&
Mapping
=
getInstrMappingImpl
(
MI
)
;
if
(
Mapping
.
isValid
(
)
)
return
Mapping
;
using
namespace
TargetOpcode
;
unsigned
NumOperands
=
MI
.
getNumOperands
(
)
;
const
ValueMapping
*
OperandsMapping
=
&
Mips
::
ValueMappings
[
Mips
::
GPRIdx
]
;
switch
(
Opc
)
{
case
G_TRUNC
:
case
G_ADD
:
case
G_SUB
:
case
G_MUL
:
case
G_UMULH
:
case
G_LOAD
:
case
G_STORE
:
case
G_ZEXTLOAD
:
case
G_SEXTLOAD
:
case
G_GEP
:
case
G_AND
:
case
G_OR
:
case
G_XOR
:
case
G_SHL
:
case
G_ASHR
:
case
G_LSHR
:
case
G_SDIV
:
case
G_UDIV
:
case
G_SREM
:
case
G_UREM
:
OperandsMapping
=
&
Mips
::
ValueMappings
[
Mips
::
GPRIdx
]
;
break
;
case
G_FADD
:
case
G_FSUB
:
case
G_FMUL
:
case
G_FDIV
:
{
unsigned
Size
=
MRI
.
getType
(
MI
.
getOperand
(
0
)
.
getReg
(
)
)
.
getSizeInBits
(
)
;
assert
(
(
Size
==
32
||
Size
==
64
)
&&
"Unsupported floating point size"
)
;
OperandsMapping
=
Size
==
32
&
Mips
::
ValueMappings
[
Mips
::
SPRIdx
]
:
&
Mips
::
ValueMappings
[
Mips
::
DPRIdx
]
;
break
;
}
case
G_FCONSTANT
:
{
unsigned
Size
=
MRI
.
getType
(
MI
.
getOperand
(
0
)
.
getReg
(
)
)
.
getSizeInBits
(
)
;
assert
(
(
Size
==
32
||
Size
==
64
)
&&
"Unsupported floating point size"
)
;
const
RegisterBankInfo
::
ValueMapping
*
FPRValueMapping
=
Size
==
32
&
Mips
::
ValueMappings
[
Mips
::
SPRIdx
]
:
&
Mips
::
ValueMappings
[
Mips
::
DPRIdx
]
;
OperandsMapping
=
getOperandsMapping
(
{
FPRValueMapping
,
nullptr
}
)
;
break
;
}
case
G_CONSTANT
:
case
G_FRAME_INDEX
:
case
G_GLOBAL_VALUE
:
case
G_BRCOND
:
OperandsMapping
=
getOperandsMapping
(
{
&
Mips
::
ValueMappings
[
Mips
::
GPRIdx
]
,
nullptr
}
)
;
break
;
case
G_ICMP
:
OperandsMapping
=
getOperandsMapping
(
{
&
Mips
::
ValueMappings
[
Mips
::
GPRIdx
]
,
nullptr
,
&
Mips
::
ValueMappings
[
Mips
::
GPRIdx
]
,
&
Mips
::
ValueMappings
[
Mips
::
GPRIdx
]
}
)
;
break
;
case
G_SELECT
:
OperandsMapping
=
getOperandsMapping
(
{
&
Mips
::
ValueMappings
[
Mips
::
GPRIdx
]
,
&
Mips
::
ValueMappings
[
Mips
::
GPRIdx
]
,
&
Mips
::
ValueMappings
[
Mips
::
GPRIdx
]
,
&
Mips
::
ValueMappings
[
Mips
::
GPRIdx
]
}
)
;
break
;
default
:
return
getInvalidInstructionMapping
(
)
;
}
return
getInstructionMapping
(
DefaultMappingID
,
1
,
OperandsMapping
,
NumOperands
)
;
}
</s>

Get the mapping of the different operands of MI on the register bank .

Mips
Mips
Mips::ValueMappings
Mips::GPRIdx
Mips::ValueMappings
Mips::GPRIdx
0
32
64
"Unsupported floating point size"
32
Mips::ValueMappings
Mips::SPRIdx
Mips::ValueMappings
Mips::DPRIdx
0
32
64
"Unsupported floating point size"
32
Mips::ValueMappings
Mips::SPRIdx
Mips::ValueMappings
Mips::DPRIdx
Mips::ValueMappings
Mips::GPRIdx
Mips::ValueMappings
Mips::GPRIdx
Mips::ValueMappings
Mips::GPRIdx
Mips::ValueMappings
Mips::GPRIdx
Mips::ValueMappings
Mips::GPRIdx
Mips::ValueMappings
Mips::GPRIdx
Mips::ValueMappings
Mips::GPRIdx
Mips::ValueMappings
Mips::GPRIdx
1


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ; AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
void
TeakInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
MCRegister
DestReg
,
MCRegister
SrcReg
,
bool
KillSrc
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
TeakSubtarget
&
st
=
MF
.
getSubtarget
<
TeakSubtarget
>
(
)
;
const
TargetRegisterInfo
*
RegInfo
=
st
.
getRegisterInfo
(
)
;
bool
keepFlags
=
MBB
.
computeRegisterLiveness
(
RegInfo
,
Teak
::
ICC
,
I
)
!=
MachineBasicBlock
::
LQR_Dead
;
dbgs
(
)
<<
"copyPhysReg("
<<
SrcReg
.
id
(
)
<<
", "
<<
DestReg
.
id
(
)
<<
")\n"
;
unsigned
op
;
if
(
Teak
::
ARegsRegClass
.
contains
(
SrcReg
)
&&
Teak
::
ARegsRegClass
.
contains
(
DestReg
)
)
op
=
Teak
::
COPY_a
;
else
if
(
Teak
::
ABRegsRegClass
.
contains
(
SrcReg
)
&&
Teak
::
ABRegsRegClass
.
contains
(
DestReg
)
)
op
=
Teak
::
MOV_ab_ab
;
else
if
(
Teak
::
RegNoBRegs16RegClass
.
contains
(
SrcReg
)
&&
Teak
::
RegNoBRegs40RegClass
.
contains
(
DestReg
)
)
op
=
Teak
::
MOV_regnobp016_abl
;
else
if
(
Teak
::
RegNoBRegs16RegClass
.
contains
(
SrcReg
)
&&
Teak
::
RegNoBRegs16RegClass
.
contains
(
DestReg
)
)
op
=
Teak
::
MOV_regnobp016_regnob16
;
else
assert
(
0
&&
"Unimplemented copyPhysReg"
)
;
if
(
!
keepFlags
)
{
if
(
op
==
Teak
::
COPY_a
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
op
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
TeakCC
::
True
)
->
addRegisterDead
(
Teak
::
ICC
,
RegInfo
)
;
else
BuildMI
(
MBB
,
I
,
DL
,
get
(
op
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
->
addRegisterDead
(
Teak
::
ICC
,
RegInfo
)
;
}
else
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
Teak
::
PUSH_ararpsttmod
)
,
Teak
::
STT0
)
;
if
(
op
==
Teak
::
COPY_a
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
op
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
TeakCC
::
True
)
;
else
BuildMI
(
MBB
,
I
,
DL
,
get
(
op
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Teak
::
POP_ararpsttmod
)
,
Teak
::
STT0
)
;
}
}
</s>


<s>
const
char
*
getPassName
(
)
const
override
{
return
"X86 LEA Optimize"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static int ft32_arg_partial_bytes ( cumulative_args_t cum_v , enum machine_mode mode , tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int bytes_left , size ; if ( * cum >= 8 ) return 0 ; if ( ft32_pass_by_reference ( cum_v , mode , type , named ) ) size = 4 ; else if ( type ) { if ( AGGREGATE_TYPE_P ( type ) ) return 0 ; size = int_size_in_bytes ( type ) ; } else size = GET_MODE_SIZE ( mode ) ; bytes_left = ( 4 * 6 ) - ( ( * cum - 2 ) * 4 ) ; if ( size > bytes_left ) return bytes_left ; else return 0 ; } </s>

Some function arguments will only partially fit in the registers that hold arguments . Given a new arg , return the number of bytes that fit in argument passing registers .


<s> bool AArch64InstrInfo :: getMachineCombinerPatterns ( MachineInstr & Root , SmallVectorImpl < MachineCombinerPattern > & Patterns ) const { if ( getMaddPatterns ( Root , Patterns ) ) return true ; return TargetInstrInfo :: getMachineCombinerPatterns ( Root , Patterns ) ; } </s>

Return true when there is potentially a faster code sequence for an instruction chain ending in Root .


<s> bool BPFAdjustOptImpl :: insertPassThrough ( ) { for ( auto & Info : PassThroughs ) { auto * CI = BPFCoreSharedInfo :: insertPassThrough ( M , Info . UsedInst -> getParent ( ) , Info . Input , Info . UsedInst ) ; Info . UsedInst -> setOperand ( Info . OpIdx , CI ) ; } return ! PassThroughs . empty ( ) ; } </s>

Insert a bpf passthrough builtin function .


<s> bool RISCVAsmBackend :: fixupNeedsRelaxationAdvanced ( const MCFixup & Fixup , bool Resolved , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout , const bool WasForced ) const { if ( ! Resolved && ! WasForced ) return true ; int64_t Offset = int64_t ( Value ) ; switch ( Fixup . getTargetKind ( ) ) { default : return false ; case RISCV :: fixup_riscv_rvc_branch : return Offset > 254 || Offset < - 256 ; case RISCV :: fixup_riscv_rvc_jump : case RISCV :: fixup_riscv_rvc_cjump : return Offset > 2046 || Offset < - 2048 ; } } </s>

Target specific predicate for whether a given fixup requires the associated instruction to be relaxed .


<s> bool ARMSubtarget :: enableAtomicExpand ( ) const { return hasAnyDataBarrier ( ) && ( ! isThumb ( ) || hasV8MBaselineOps ( ) ) ; } </s>

True if the subtarget should run the atomic expansion pass .


"Can't store this register to stack slot"


<s> const uint32_t * MOSRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CallingConv ) const { return MOS_CSR_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool isIntDivCheap ( EVT VT , AttributeList Attr ) const override { return true ; } </s>

Return true if integer divide is usually cheaper than a sequence of several shifts , adds , and multiplies for this target .


<s> bool convertSetCCLogicToBitwiseLogic ( EVT VT ) const override { return VT . isScalarInteger ( ) ; } </s>

Use bitwise logic to make pairs of compares more efficient .


<s>
SDValue
VETargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
unsigned
Opcode
=
Op
.
getOpcode
(
)
;
if
(
ISD
::
isVPOpcode
(
Opcode
)
)
return
lowerToVVP
(
Op
,
DAG
)
;
switch
(
Opcode
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
ATOMIC_FENCE
:
return
lowerATOMIC_FENCE
(
Op
,
DAG
)
;
case
ISD
::
ATOMIC_SWAP
:
return
lowerATOMIC_SWAP
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
lowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
lowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
lowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
EH_SJLJ_LONGJMP
:
return
lowerEH_SJLJ_LONGJMP
(
Op
,
DAG
)
;
case
ISD
::
EH_SJLJ_SETJMP
:
return
lowerEH_SJLJ_SETJMP
(
Op
,
DAG
)
;
case
ISD
::
EH_SJLJ_SETUP_DISPATCH
:
return
lowerEH_SJLJ_SETUP_DISPATCH
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
lowerFRAMEADDR
(
Op
,
DAG
,
*
this
,
Subtarget
)
;
case
ISD
::
GlobalAddress
:
return
lowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
lowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
lowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
lowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
LOAD
:
return
lowerLOAD
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
lowerRETURNADDR
(
Op
,
DAG
,
*
this
,
Subtarget
)
;
case
ISD
::
BUILD_VECTOR
:
return
lowerBUILD_VECTOR
(
Op
,
DAG
)
;
case
ISD
::
STORE
:
return
lowerSTORE
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
lowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
VAARG
:
return
lowerVAARG
(
Op
,
DAG
)
;
case
ISD
::
INSERT_VECTOR_ELT
:
return
lowerINSERT_VECTOR_ELT
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_VECTOR_ELT
:
return
lowerEXTRACT_VECTOR_ELT
(
Op
,
DAG
)
;
return
lowerToVVP
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> static bool get_default_ma ( ) { return ( bool ) ( get_prefer_mask_policy ( ) & 0x1 || ( get_prefer_mask_policy ( ) >> 1 & 0x1 ) ) ; } </s>


<s>
void
AMDGPURegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
MI
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
llvm_unreachable
(
"Subroutines not supported yet"
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .

AMDGPU
AMDGPU
"Subroutines not supported yet"


<s> static void alpha_compute_frame_layout ( void ) { unsigned HOST_WIDE_INT sa_mask = 0 ; HOST_WIDE_INT frame_size ; int sa_size ; if ( ! cfun -> is_thunk ) { if ( TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK ) sa_mask |= HOST_WIDE_INT_1U << HARD_FRAME_POINTER_REGNUM ; for ( unsigned i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( ! call_used_or_fixed_reg_p ( i ) && df_regs_ever_live_p ( i ) && i != REG_RA ) sa_mask |= HOST_WIDE_INT_1U << i ; if ( crtl -> calls_eh_return ) { for ( unsigned i = 0 ; ; ++ i ) { unsigned regno = EH_RETURN_DATA_REGNO ( i ) ; if ( regno == INVALID_REGNUM ) break ; sa_mask |= HOST_WIDE_INT_1U << regno ; } } if ( sa_mask || alpha_ra_ever_killed ( ) ) sa_mask |= HOST_WIDE_INT_1U << REG_RA ; } sa_size = popcount_hwi ( sa_mask ) ; frame_size = get_frame_size ( ) ; if ( TARGET_ABI_OPEN_VMS ) { if ( ( sa_mask >> REG_RA ) & 1 || frame_pointer_needed ) alpha_procedure_type = PT_STACK ; else if ( frame_size != 0 ) alpha_procedure_type = PT_REGISTER ; else alpha_procedure_type = PT_NULL ; if ( alpha_procedure_type == PT_STACK ) sa_size -= 2 ; vms_base_regno = ( frame_pointer_needed || cfun -> has_nonlocal_label || alpha_procedure_type == PT_STACK || crtl -> outgoing_args_size ) ? REG_PV : HARD_FRAME_POINTER_REGNUM ; vms_save_fp_regno = - 1 ; if ( vms_base_regno == HARD_FRAME_POINTER_REGNUM ) for ( unsigned i = 0 ; i < 32 ; i ++ ) if ( ! fixed_regs [ i ] && call_used_or_fixed_reg_p ( i ) && ! df_regs_ever_live_p ( i ) ) { vms_save_fp_regno = i ; break ; } if ( ( vms_save_fp_regno == - 1 && alpha_procedure_type == PT_REGISTER ) || cfun -> machine -> uses_condition_handler ) vms_base_regno = REG_PV , alpha_procedure_type = PT_STACK ; else if ( alpha_procedure_type == PT_NULL ) vms_base_regno = REG_PV ; vms_unwind_regno = ( vms_base_regno == REG_PV ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ) ; if ( alpha_procedure_type == PT_STACK ) sa_size += 2 + cfun -> machine -> uses_condition_handler ; } else { if ( sa_size & 1 ) sa_size ++ ; } sa_size *= 8 ; if ( TARGET_ABI_OPEN_VMS ) frame_size = ALPHA_ROUND ( sa_size + ( alpha_procedure_type == PT_STACK ? 8 : 0 ) + frame_size + crtl -> args . pretend_args_size ) ; else frame_size = ( ALPHA_ROUND ( crtl -> outgoing_args_size ) + sa_size + ALPHA_ROUND ( frame_size + crtl -> args . pretend_args_size ) ) ; cfun -> machine -> sa_mask = sa_mask ; cfun -> machine -> sa_size = sa_size ; cfun -> machine -> frame_size = frame_size ; } </s>

Compute register masks for saved registers , register save area size , and total frame size .


<s> void print_operand_address ( FILE * file , rtx x ) { struct mips_address_info addr ; if ( mips_classify_address ( & addr , x , word_mode , true ) ) switch ( addr . type ) { case ADDRESS_REG : print_operand ( file , addr . offset , 0 ) ; fprintf ( file , "(%s)" , reg_names [ REGNO ( addr . reg ) ] ) ; return ; case ADDRESS_LO_SUM : print_operand ( file , addr . offset , 'R' ) ; fprintf ( file , "(%s)" , reg_names [ REGNO ( addr . reg ) ] ) ; return ; case ADDRESS_CONST_INT : output_addr_const ( file , x ) ; fprintf ( file , "(%s)" , reg_names [ 0 ] ) ; return ; case ADDRESS_SYMBOLIC : output_addr_const ( file , x ) ; return ; } gcc_unreachable ( ) ; } </s>

Print the operand address represented by the rtx addr


"Intrinsic instructions can't commute operand 1"

Returns an adjusted FMA opcode that must be used in FMA instruction that performs the same computations as the given MI but which has the operands SrcOpIdx1 and SrcOpIdx2 commuted .


<s> void changedInstr ( MachineInstr & MI ) override { } </s>

This instruction was mutated in some way .


<s> TargetLowering :: AtomicExpansionKind ARMTargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { unsigned Size = AI -> getOperand ( 1 ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; bool HasAtomicCmpXchg = ! Subtarget -> isThumb ( ) || Subtarget -> hasV8MBaselineOps ( ) ; if ( getTargetMachine ( ) . getOptLevel ( ) != 0 && HasAtomicCmpXchg && Size <= ( Subtarget -> isMClass ( ) ? 32U : 64U ) ) return AtomicExpansionKind :: LLSC ; return AtomicExpansionKind :: None ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


"Callee should be an llvm::Function object."

"failed to perform tail call elimination on a call "

This hook must be implemented to lower calls into the specified DAG .


<s> void sparc_emit_set_const32 ( rtx op0 , rtx op1 ) { enum machine_mode mode = GET_MODE ( op0 ) ; rtx temp ; if ( reload_in_progress || reload_completed ) temp = op0 ; else temp = gen_reg_rtx ( mode ) ; if ( GET_CODE ( op1 ) == CONST_INT ) { gcc_assert ( ! small_int_operand ( op1 , mode ) && ! const_high_operand ( op1 , mode ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , temp , GEN_INT ( INTVAL ( op1 ) & ~ ( HOST_WIDE_INT ) 0x3ff ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_IOR ( mode , temp , GEN_INT ( INTVAL ( op1 ) & 0x3ff ) ) ) ) ; } else { emit_insn ( gen_rtx_SET ( VOIDmode , temp , gen_rtx_HIGH ( mode , op1 ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_LO_SUM ( mode , temp , op1 ) ) ) ; } } </s>

We know it ca n't be done in one insn when we get here , the movsi expander guarentees this .


<s> MachineFunction * getMF ( ) const { return MF ; } </s>

Return the function that contains the basic block that this instruction belongs to .


<s> bool ARMAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AFI = MF . getInfo < ARMFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; Subtarget = & MF . getSubtarget < ARMSubtarget > ( ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = MF . getFunction ( ) -> hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer . BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer . EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer . EmitCOFFSymbolType ( Type ) ; OutStreamer . EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; if ( ! ThumbIndirectPads . empty ( ) ) { OutStreamer . EmitAssemblerFlag ( MCAF_Code16 ) ; EmitAlignment ( 1 ) ; for ( unsigned i = 0 , e = ThumbIndirectPads . size ( ) ; i < e ; i ++ ) { OutStreamer . EmitLabel ( ThumbIndirectPads [ i ] . second ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( ARM :: tBX ) . addReg ( ThumbIndirectPads [ i ] . first ) . addImm ( ARMCC :: AL ) . addReg ( 0 ) ) ; } ThumbIndirectPads . clear ( ) ; } return false ; } </s>

runOnMachineFunction - Emit the function body .

ARM ARM ARM ARM 1 0 ARM::tBX ARMCC::AL 0


"A single use instruction with no uses."

Return true if it is profitable to hoist instruction in the then/else to before if .


<s> RegionMRT * getParent ( ) { return Parent ; } </s>

getParent - Return the last analyzed interval .


<s> bool ix86_expand_strlen ( rtx out , rtx src , rtx eoschar , rtx align ) { rtx addr , scratch1 , scratch2 , scratch3 , scratch4 ; if ( TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1 && ! TARGET_INLINE_ALL_STRINGOPS && ! optimize_insn_for_size_p ( ) && ( ! CONST_INT_P ( align ) || INTVAL ( align ) < 4 ) ) return false ; addr = force_reg ( Pmode , XEXP ( src , 0 ) ) ; scratch1 = gen_reg_rtx ( Pmode ) ; if ( TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1 && ! optimize_insn_for_size_p ( ) ) { emit_move_insn ( out , addr ) ; ix86_expand_strlensi_unroll_1 ( out , src , align ) ; emit_insn ( ix86_gen_sub3 ( out , out , addr ) ) ; } else { rtx unspec ; if ( fixed_regs [ AX_REG ] || fixed_regs [ CX_REG ] || fixed_regs [ DI_REG ] ) return false ; scratch2 = gen_reg_rtx ( Pmode ) ; scratch3 = gen_reg_rtx ( Pmode ) ; scratch4 = force_reg ( Pmode , constm1_rtx ) ; emit_move_insn ( scratch3 , addr ) ; eoschar = force_reg ( QImode , eoschar ) ; src = replace_equiv_address_nv ( src , scratch3 ) ; unspec = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 4 , src , eoschar , align , scratch4 ) , UNSPEC_SCAS ) ; emit_insn ( gen_strlenqi_1 ( scratch1 , scratch3 , unspec ) ) ; emit_insn ( ix86_gen_one_cmpl2 ( scratch2 , scratch1 ) ) ; emit_insn ( ix86_gen_add3 ( out , scratch2 , constm1_rtx ) ) ; } return true ; } </s>


<s> void mips_emit_fcc_reload ( rtx dest , rtx src , rtx scratch ) { rtx fp1 , fp2 ; if ( MEM_P ( src ) ) src = adjust_address ( src , SFmode , 0 ) ; else if ( REG_P ( src ) || GET_CODE ( src ) == SUBREG ) src = gen_rtx_REG ( SFmode , true_regnum ( src ) ) ; fp1 = gen_rtx_REG ( SFmode , REGNO ( scratch ) ) ; fp2 = gen_rtx_REG ( SFmode , REGNO ( scratch ) + FP_INC ) ; emit_move_insn ( copy_rtx ( fp1 ) , src ) ; emit_move_insn ( copy_rtx ( fp2 ) , CONST0_RTX ( SFmode ) ) ; emit_insn ( gen_slt_sf ( dest , fp2 , fp1 ) ) ; } </s>

Emit code to move general operand SRC into condition-code register DEST . SCRATCH is a scratch TFmode float register . The sequence is : FP1 = SRC FP2 = 0.0f DEST = FP2 < FP1 where FP1 and FP2 are single-precision float registers taken from SCRATCH .


<s> bool ix86_expand_cmpstrn_or_cmpmem ( rtx result , rtx src1 , rtx src2 , rtx length , rtx align , bool is_cmpstrn ) { if ( ! TARGET_INLINE_ALL_STRINGOPS ) return false ; if ( fixed_regs [ CX_REG ] || fixed_regs [ SI_REG ] || fixed_regs [ DI_REG ] ) return false ; if ( is_cmpstrn ) { tree t1 = MEM_EXPR ( src1 ) ; tree t2 = MEM_EXPR ( src2 ) ; if ( ! ( ( t1 && TREE_CODE ( t1 ) == MEM_REF && TREE_CODE ( TREE_OPERAND ( t1 , 0 ) ) == ADDR_EXPR && ( TREE_CODE ( TREE_OPERAND ( TREE_OPERAND ( t1 , 0 ) , 0 ) ) == STRING_CST ) ) || ( t2 && TREE_CODE ( t2 ) == MEM_REF && TREE_CODE ( TREE_OPERAND ( t2 , 0 ) ) == ADDR_EXPR && ( TREE_CODE ( TREE_OPERAND ( TREE_OPERAND ( t2 , 0 ) , 0 ) ) == STRING_CST ) ) ) ) return false ; } rtx addr1 = copy_addr_to_reg ( XEXP ( src1 , 0 ) ) ; rtx addr2 = copy_addr_to_reg ( XEXP ( src2 , 0 ) ) ; if ( addr1 != XEXP ( src1 , 0 ) ) src1 = replace_equiv_address_nv ( src1 , addr1 ) ; if ( addr2 != XEXP ( src2 , 0 ) ) src2 = replace_equiv_address_nv ( src2 , addr2 ) ; length = ix86_zero_extend_to_Pmode ( length ) ; rtx lengthreg = gen_reg_rtx ( Pmode ) ; emit_move_insn ( lengthreg , length ) ; if ( CONST_INT_P ( length ) ) { if ( length == const0_rtx ) { emit_move_insn ( result , const0_rtx ) ; return true ; } emit_insn ( gen_cmpstrnqi_nz_1 ( addr1 , addr2 , lengthreg , align , src1 , src2 ) ) ; } else { emit_insn ( gen_cmp_1 ( Pmode , lengthreg , lengthreg ) ) ; emit_insn ( gen_cmpstrnqi_1 ( addr1 , addr2 , lengthreg , align , src1 , src2 ) ) ; } rtx out = gen_lowpart ( QImode , result ) ; emit_insn ( gen_cmpintqi ( out ) ) ; emit_move_insn ( result , gen_rtx_SIGN_EXTEND ( SImode , out ) ) ; return true ; } </s>


<s>
const
MCFixupKindInfo
&
Cpu0AsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
Cpu0
::
NumTargetFixupKinds
]
=
{
{
"fixup_Cpu0_32"
,
0
,
32
,
0
}
,
{
"fixup_Cpu0_HI16"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_LO16"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_GPREL16"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_GOT"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_GOT_HI16"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_GOT_LO16"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_PC16"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_Cpu0_PC24"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> bool TeakRegisterInfo :: isFrameOffsetLegal ( const MachineInstr * MI , unsigned BaseReg , int64_t Offset ) const { dbgs ( ) << "isFrameOffsetLegal\n" ; return true ; } </s>

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


"Function has local memory argument. Promoting to "

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> unsigned SITargetLowering :: getVectorTypeBreakdownForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT , EVT & IntermediateVT , unsigned & NumIntermediates , MVT & RegisterVT ) const { if ( CC != CallingConv :: AMDGPU_KERNEL && VT . getVectorNumElements ( ) == 3 ) { EVT ScalarVT = VT . getScalarType ( ) ; if ( ScalarVT . getSizeInBits ( ) == 32 || ScalarVT . getSizeInBits ( ) == 64 ) { RegisterVT = ScalarVT . getSimpleVT ( ) ; IntermediateVT = RegisterVT ; NumIntermediates = 3 ; return NumIntermediates ; } } return TargetLowering :: getVectorTypeBreakdownForCallingConv ( Context , CC , VT , IntermediateVT , NumIntermediates , RegisterVT ) ; } </s>

Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , CM , OL ) , TargetABI ( computeTargetABI ( TT , CPU , Options ) ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , Subtarget ( TT , CPU , FS , * this , isLittle ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = Subtarget . isTargetHardFloat ( ) ? FloatABI :: Hard : FloatABI :: Soft ; if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( Subtarget . isTargetGNUAEABI ( ) || Subtarget . isTargetMuslAEABI ( ) ) this -> Options . EABIVersion = EABI :: GNU ; else this -> Options . EABIVersion = EABI :: EABI5 ; } } </s>


"-mno-power9-vector turns off -mpower9-dform"

If the user used -mno-vsx , we need turn off all of the implicit ISA 2.06 , 2.07 , and 3.0 options that relate to the vector unit ( -mdirect-move , -mupper-regs-df , etc. ) . If the user used -mno-power8-vector , we need to turn off all of the implicit ISA 2.07 and 3.0 options that relate to the vector unit . If the user used -mno-power9-vector , we need to turn off all of the implicit ISA 3.0 options that relate to the vector unit . This function does not handle explicit options such as the user specifying -mdirect-move . These are handled in rs6000_option_override_internal , and the appropriate error is given if needed . We return a mask of all of the implicit options that should not be enabled by default .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
void
SystemZOperand
::
print
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
KindToken
:
OS
<<
"Token:"
<<
getToken
(
)
;
break
;
case
KindReg
:
OS
<<
"Reg:"
<<
SystemZInstPrinter
::
getRegisterName
(
getReg
(
)
)
;
break
;
case
KindImm
:
OS
<<
"Imm:"
;
printMCExpr
(
getImm
(
)
,
OS
)
;
break
;
case
KindImmTLS
:
OS
<<
"ImmTLS:"
;
printMCExpr
(
getImmTLS
(
)
.
Imm
,
OS
)
;
if
(
getImmTLS
(
)
.
Sym
)
{
OS
<<
", "
;
printMCExpr
(
getImmTLS
(
)
.
Sym
,
OS
)
;
}
break
;
case
KindMem
:
{
const
MemOp
&
Op
=
getMem
(
)
;
OS
<<
"Mem:"
<<
*
cast
<
MCConstantExpr
>
(
Op
.
Disp
)
;
if
(
Op
.
Base
)
{
OS
<<
"("
;
if
(
Op
.
MemKind
==
BDLMem
)
OS
<<
*
cast
<
MCConstantExpr
>
(
Op
.
Length
.
Imm
)
<<
","
;
else
if
(
Op
.
MemKind
==
BDRMem
)
OS
<<
SystemZInstPrinter
::
getRegisterName
(
Op
.
Length
.
Reg
)
<<
","
;
if
(
Op
.
Index
)
OS
<<
SystemZInstPrinter
::
getRegisterName
(
Op
.
Index
)
<<
","
;
OS
<<
SystemZInstPrinter
::
getRegisterName
(
Op
.
Base
)
;
OS
<<
")"
;
}
break
;
}
case
KindInvalid
:
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

SystemZ
SystemZ
"Token:"
"Reg:"
SystemZ
"Imm:"
"ImmTLS:"
", "
"Mem:"
"("
","
SystemZ
","
SystemZ
","
SystemZ
")"


"stack limit expression is not supported"

Emit the correct code for allocating stack space , as insns . If COPY_R12 , make sure a copy of the old frame is left in r12 . The generated code may use hard register 0 as a temporary .


<s> const MSP430Subtarget * getSubtargetImpl ( const Function & F ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> void MipsTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; SmallDataSection = getELFSection ( ".sdata" , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_WRITE | MCSectionELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getELFSection ( ".sbss" , MCSectionELF :: SHT_NOBITS , MCSectionELF :: SHF_WRITE | MCSectionELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s> bool OptimizeLEAPass :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; if ( DisableX86LEAOpt || skipFunction ( * MF . getFunction ( ) ) ) return false ; MRI = & MF . getRegInfo ( ) ; TII = MF . getSubtarget < X86Subtarget > ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget < X86Subtarget > ( ) . getRegisterInfo ( ) ; for ( auto & MBB : MF ) { MemOpMap LEAs ; InstrPos . clear ( ) ; findLEAs ( MBB , LEAs ) ; if ( LEAs . empty ( ) ) continue ; Changed |= removeRedundantLEAs ( LEAs ) ; if ( MF . getFunction ( ) -> optForSize ( ) ) Changed |= removeRedundantAddrCalc ( LEAs ) ; } return Changed ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 Fixup SetCC"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool isValid ( ) const { return Valid ; } </s>

Returns true if this iterator is still pointing at a valid entry .


"Instr doesn't have FrameIndex operand!"

"16-byte alignment violated in eliminateFrameIndex"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> const MipsInstrInfo * MipsInstrInfo :: create ( MipsSubtarget & STI ) { if ( STI . inMips16Mode ( ) ) return llvm :: createMips16InstrInfo ( STI ) ; return llvm :: createMipsSEInstrInfo ( STI ) ; } </s>


"insertBranch must not be told to insert a fallthrough"

"GBZ80 branch conditions must have a multiple of two components!"

"Unconditional branch with multiple successors!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> bool AMDGPUTargetLowering :: isKnownNeverNaNForTargetNode ( SDValue Op , const SelectionDAG & DAG , bool SNaN , unsigned Depth ) const { unsigned Opcode = Op . getOpcode ( ) ; switch ( Opcode ) { case AMDGPUISD :: FMIN_LEGACY : case AMDGPUISD :: FMAX_LEGACY : { if ( SNaN ) return true ; return false ; } case AMDGPUISD :: FMUL_LEGACY : case AMDGPUISD :: CVT_PKRTZ_F16_F32 : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( 0 ) , SNaN , Depth + 1 ) && DAG . isKnownNeverNaN ( Op . getOperand ( 1 ) , SNaN , Depth + 1 ) ; } case AMDGPUISD :: FMED3 : case AMDGPUISD :: FMIN3 : case AMDGPUISD :: FMAX3 : case AMDGPUISD :: FMAD_FTZ : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( 0 ) , SNaN , Depth + 1 ) && DAG . isKnownNeverNaN ( Op . getOperand ( 1 ) , SNaN , Depth + 1 ) && DAG . isKnownNeverNaN ( Op . getOperand ( 2 ) , SNaN , Depth + 1 ) ; } case AMDGPUISD :: CVT_F32_UBYTE0 : case AMDGPUISD :: CVT_F32_UBYTE1 : case AMDGPUISD :: CVT_F32_UBYTE2 : case AMDGPUISD :: CVT_F32_UBYTE3 : return true ; case AMDGPUISD :: RCP : case AMDGPUISD :: RSQ : case AMDGPUISD :: RCP_LEGACY : case AMDGPUISD :: RSQ_CLAMP : { if ( SNaN ) return true ; return false ; } case AMDGPUISD :: LDEXP : case AMDGPUISD :: FRACT : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( 0 ) , SNaN , Depth + 1 ) ; } case AMDGPUISD :: DIV_SCALE : case AMDGPUISD :: DIV_FMAS : case AMDGPUISD :: DIV_FIXUP : return SNaN ; case AMDGPUISD :: SIN_HW : case AMDGPUISD :: COS_HW : { return SNaN ; } case ISD :: INTRINSIC_WO_CHAIN : { unsigned IntrinsicID = cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ; switch ( IntrinsicID ) { case Intrinsic :: amdgcn_cubeid : return true ; case Intrinsic :: amdgcn_frexp_mant : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( 1 ) , SNaN , Depth + 1 ) ; } case Intrinsic :: amdgcn_cvt_pkrtz : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( 1 ) , SNaN , Depth + 1 ) && DAG . isKnownNeverNaN ( Op . getOperand ( 2 ) , SNaN , Depth + 1 ) ; } case Intrinsic :: amdgcn_rcp : case Intrinsic :: amdgcn_rsq : case Intrinsic :: amdgcn_rcp_legacy : case Intrinsic :: amdgcn_rsq_legacy : case Intrinsic :: amdgcn_rsq_clamp : { if ( SNaN ) return true ; return false ; } case Intrinsic :: amdgcn_trig_preop : case Intrinsic :: amdgcn_fdot2 : return SNaN ; default : return false ; } } default : return false ; } } </s>


<s> rtx xstormy16_function_value ( tree valtype , tree func ATTRIBUTE_UNUSED ) { enum machine_mode mode ; mode = TYPE_MODE ( valtype ) ; PROMOTE_MODE ( mode , 0 , valtype ) ; return gen_rtx_REG ( mode , RETURN_VALUE_REGNUM ) ; } </s>


<s> void setupMF ( MachineFunction & MF , GISelKnownBits & KB , CodeGenCoverage & CoverageInfo ) override { InstructionSelector :: setupMF ( MF , KB , CoverageInfo ) ; ProduceNonFlagSettingCondBr = ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: SpeculativeLoadHardening ) ; } </s>


"64-bit code requested on a subtarget that doesn't "

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> SDNode * MipsDAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = MF -> getInfo < MipsFunctionInfo > ( ) -> getGlobalBaseReg ( ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI . getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> FunctionPass * NVPTXPassConfig :: createTargetRegisterAllocator ( bool ) { return nullptr ; } </s>

createTargetRegisterAllocator - Create the register allocator pass for this target at the current optimization level .


<s> void assignValueToReg ( Register ValVReg , Register PhysReg , CCValAssign & VA ) override { markPhysRegUsed ( PhysReg ) ; IncomingValueHandler :: assignValueToReg ( ValVReg , PhysReg , VA ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Z80 Assembly / Object Emitter"
;
}
</s>


<s> static unsigned int cris_postdbr_cmpelim ( ) { rtx_insn * insn ; rtx_insn * next ; rtx_insn * prev_cc_setter = 0 ; rtx_insn * prev_cc_outer = 0 ; rtx dccr = gen_rtx_REG ( CCmode , CRIS_CC0_REGNUM ) ; for ( insn = get_insns ( ) ; insn ; insn = next ) { rtx_insn * outer_insn = insn ; rtx pat = PATTERN ( insn ) ; next = NEXT_INSN ( outer_insn ) ; if ( LABEL_P ( insn ) ) { prev_cc_setter = 0 ; continue ; } if ( ! NONDEBUG_INSN_P ( insn ) ) continue ; if ( GET_CODE ( pat ) == SEQUENCE ) insn = as_a < rtx_insn * > ( XVECEXP ( pat , 0 , 1 ) ) ; else if ( prev_cc_setter != 0 && GET_CODE ( pat ) == SET ) { rtx dest = SET_DEST ( pat ) ; rtx src = SET_SRC ( pat ) ; rtx prev_set ; if ( REG_P ( dest ) && REGNO ( dest ) == CRIS_CC0_REGNUM && GET_CODE ( src ) == COMPARE && REG_P ( XEXP ( src , 0 ) ) && XEXP ( src , 1 ) == const0_rtx && ( prev_set = single_set ( prev_cc_setter ) ) != 0 ) { rtx reg = XEXP ( src , 0 ) ; rtx prev_dest = SET_DEST ( prev_set ) ; rtx prev_src = SET_SRC ( prev_set ) ; bool src_same = rtx_equal_p ( prev_src , reg ) ; if ( REG_P ( prev_dest ) && ! reg_set_p ( reg , prev_src ) && ! reg_set_between_p ( reg , prev_cc_outer , outer_insn ) && ( src_same || rtx_equal_p ( prev_dest , reg ) ) ) { machine_mode ccmode = GET_MODE ( src ) ; rtx modeadjusted_dccr = ( ccmode == CCmode ? dccr : gen_rtx_REG ( CCmode , CRIS_CC0_REGNUM ) ) ; rtx compare = ( src_same ? pat : gen_rtx_SET ( modeadjusted_dccr , gen_rtx_COMPARE ( ccmode , copy_rtx ( prev_src ) , const0_rtx ) ) ) ; validate_change ( prev_cc_setter , & XVECEXP ( PATTERN ( prev_cc_setter ) , 0 , 0 ) , compare , true ) ; validate_change ( prev_cc_setter , & XVECEXP ( PATTERN ( prev_cc_setter ) , 0 , 1 ) , prev_set , true ) ; if ( apply_change_group ( ) ) { delete_insn ( insn ) ; prev_cc_setter = 0 ; continue ; } } } } if ( reg_set_p ( dccr , insn ) ) { rtx pat = PATTERN ( insn ) ; prev_cc_setter = 0 ; if ( GET_CODE ( pat ) == PARALLEL && XVECLEN ( pat , 0 ) == 2 && GET_CODE ( XVECEXP ( pat , 0 , 1 ) ) == CLOBBER ) { prev_cc_setter = insn ; prev_cc_outer = outer_insn ; } } } return 0 ; } </s>

`` Cheap version '' of cmpelim , making use of the opportunities opened up by reorg . Go through the insns of a function and look at each actual compare insn ; considering only those that compare a register to 0 . If the previous CC-affecting insn sets the compared register or if a move reads from it , try to change that into a CC-setting move and try to have it recognized . Bail at labels or non-matching insns that clobber the compared register . If successful , delete the compare . Also , reorg is n't up to date regarding data-flow handling , so we ca n't go beyond classic RTL scanning .


<s>
void
print
(
)
{
if
(
numSymbols
==
0
)
{
for
(
unsigned
i
=
0
;
i
<
size
;
i
++
)
{
if
(
i
)
O
<<
", "
;
O
<<
(
unsigned
int
)
buffer
[
i
]
;
}
}
else
{
unsigned
int
pos
=
0
;
unsigned
int
nSym
=
0
;
unsigned
int
nextSymbolPos
=
symbolPosInBuffer
[
nSym
]
;
unsigned
int
nBytes
=
4
;
if
(
static_cast
<
const
NVPTXTargetMachine
&
>
(
AP
.
TM
)
.
is64Bit
(
)
)
nBytes
=
8
;
for
(
pos
=
0
;
pos
<
size
;
pos
+=
nBytes
)
{
if
(
pos
)
O
<<
", "
;
if
(
pos
==
nextSymbolPos
)
{
const
Value
*
v
=
Symbols
[
nSym
]
;
const
Value
*
v0
=
SymbolsBeforeStripping
[
nSym
]
;
if
(
const
GlobalValue
*
GVar
=
dyn_cast
<
GlobalValue
>
(
v
)
)
{
MCSymbol
*
Name
=
AP
.
getSymbol
(
GVar
)
;
PointerType
*
PTy
=
dyn_cast
<
PointerType
>
(
v0
->
getType
(
)
)
;
bool
IsNonGenericPointer
=
false
;
if
(
PTy
&&
PTy
->
getAddressSpace
(
)
!=
0
)
{
IsNonGenericPointer
=
true
;
}
if
(
EmitGeneric
&&
!
isa
<
Function
>
(
v
)
&&
!
IsNonGenericPointer
)
{
O
<<
"generic("
;
O
<<
*
Name
;
O
<<
")"
;
}
else
{
O
<<
*
Name
;
}
}
else
if
(
const
ConstantExpr
*
CExpr
=
dyn_cast
<
ConstantExpr
>
(
v0
)
)
{
const
MCExpr
*
Expr
=
AP
.
lowerConstantForGV
(
cast
<
Constant
>
(
CExpr
)
,
false
)
;
AP
.
printMCExpr
(
*
Expr
,
O
)
;
}
else
llvm_unreachable
(
"symbol type unknown"
)
;
nSym
++
;
if
(
nSym
>=
numSymbols
)
nextSymbolPos
=
size
+
1
;
else
nextSymbolPos
=
symbolPosInBuffer
[
nSym
]
;
}
else
if
(
nBytes
==
4
)
O
<<
*
(
unsigned
int
*
)
(
&
buffer
[
pos
]
)
;
else
O
<<
*
(
unsigned
long
long
*
)
(
&
buffer
[
pos
]
)
;
}
}
}
</s>


<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < 512 > Key ; Key . reserve ( CPU . size ( ) + FS . size ( ) ) ; Key += CPU ; Key += FS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) Key += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; FS = Key . substr ( CPU . size ( ) ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < X86Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; X86GISelActualAccessor * GISel = new X86GISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new X86CallLowering ( * I -> getTargetLowering ( ) ) ) ; GISel -> Legalizer . reset ( new X86LegalizerInfo ( * I ) ) ; auto * RBI = new X86RegisterBankInfo ( * I -> getRegisterInfo ( ) ) ; GISel -> RegBankInfo . reset ( RBI ) ; GISel -> InstSelector . reset ( new X86InstructionSelector ( * I , * RBI ) ) ; I -> setGISelAccessor ( * GISel ) ; } return I . get ( ) ; } </s>


<s> EVT X86TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( ( ! IsMemset || ZeroMemset ) && ! F -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { if ( Size >= 16 && ( Subtarget -> isUnalignedMemAccessFast ( ) || ( ( DstAlign == 0 || DstAlign >= 16 ) && ( SrcAlign == 0 || SrcAlign >= 16 ) ) ) ) { if ( Size >= 32 ) { if ( Subtarget -> hasInt256 ( ) ) return MVT :: v8i32 ; if ( Subtarget -> hasFp256 ( ) ) return MVT :: v8f32 ; } if ( Subtarget -> hasSSE2 ( ) ) return MVT :: v4i32 ; if ( Subtarget -> hasSSE1 ( ) ) return MVT :: v4f32 ; } else if ( ! MemcpyStrSrc && Size >= 8 && ! Subtarget -> is64Bit ( ) && Subtarget -> hasSSE2 ( ) ) { return MVT :: f64 ; } } if ( Subtarget -> is64Bit ( ) && Size >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> bool X86ATTAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : break ; case 'P' : printMemReference ( MI , OpNo , "mem" , true ) ; return false ; } } printMemReference ( MI , OpNo ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> int same_cmp_following_p ( rtx i1 ) { rtx i2 , i3 ; i2 = next_nonnote_insn ( i1 ) ; if ( i2 == NULL_RTX ) return 0 ; i3 = next_nonnote_insn ( i2 ) ; if ( i3 == NULL_RTX ) return 0 ; return ( INSN_P ( i3 ) && rtx_equal_p ( PATTERN ( i1 ) , PATTERN ( i3 ) ) && any_condjump_p ( i2 ) && onlyjump_p ( i2 ) ) ; } </s>

Return nonzero if we have the same comparison insn as I1 two insns after I1 . I1 is assumed to be a comparison insn .


<s> static int rs6000_darwin64_struct_check_p ( machine_mode mode , const_tree type ) { return rs6000_darwin64_abi && ( ( mode == BLKmode && TREE_CODE ( type ) == RECORD_TYPE && int_size_in_bytes ( type ) > 0 ) || ( type && TREE_CODE ( type ) == RECORD_TYPE && int_size_in_bytes ( type ) == 8 ) ) ? 1 : 0 ; } </s>

Check for an item that needs to be considered specially under the darwin 64 bit ABI . These are record types where the mode is BLK or the structure is 8 bytes in size .


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const PPCFrameLowering * PPCFI = static_cast < const PPCFrameLowering * > ( MF . getTarget ( ) . getFrameLowering ( ) ) ; Reserved . set ( PPC :: ZERO ) ; Reserved . set ( PPC :: ZERO8 ) ; Reserved . set ( PPC :: FP ) ; Reserved . set ( PPC :: FP8 ) ; Reserved . set ( PPC :: BP ) ; Reserved . set ( PPC :: BP8 ) ; Reserved . set ( PPC :: CTR ) ; Reserved . set ( PPC :: CTR8 ) ; Reserved . set ( PPC :: R1 ) ; Reserved . set ( PPC :: LR ) ; Reserved . set ( PPC :: LR8 ) ; Reserved . set ( PPC :: RM ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) Reserved . set ( PPC :: VRSAVE ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: R2 ) ; Reserved . set ( PPC :: R13 ) ; } if ( Subtarget . isPPC64 ( ) ) { Reserved . set ( PPC :: R13 ) ; Reserved . set ( PPC :: X1 ) ; Reserved . set ( PPC :: X13 ) ; if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: X31 ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( PPC :: X30 ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: X2 ) ; } } if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: R31 ) ; if ( hasBasePointer ( MF ) ) { if ( Subtarget . isSVR4ABI ( ) && ! Subtarget . isPPC64 ( ) && MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) Reserved . set ( PPC :: R29 ) ; else Reserved . set ( PPC :: R30 ) ; } if ( Subtarget . isSVR4ABI ( ) && ! Subtarget . isPPC64 ( ) && MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) Reserved . set ( PPC :: R30 ) ; if ( ! Subtarget . hasAltivec ( ) ) for ( TargetRegisterClass :: iterator I = PPC :: VRRCRegClass . begin ( ) , IE = PPC :: VRRCRegClass . end ( ) ; I != IE ; ++ I ) Reserved . set ( * I ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly


<s> static bool spu_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { if ( ( GET_CODE ( x ) == SYMBOL_REF ) || GET_CODE ( x ) == LABEL_REF || GET_CODE ( x ) == CONST ) reloc_diagnostic ( x ) ; return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Hook into assemble_integer so we can generate an error for run-time relocations . The SPU ABI disallows them .


<s> SDNode * NVPTXDAGToDAGISel :: Select ( SDNode * N ) { if ( N -> isMachineOpcode ( ) ) return NULL ; SDNode * ResNode = NULL ; switch ( N -> getOpcode ( ) ) { case ISD :: LOAD : ResNode = SelectLoad ( N ) ; break ; case ISD :: STORE : ResNode = SelectStore ( N ) ; break ; case NVPTXISD :: LoadV2 : case NVPTXISD :: LoadV4 : ResNode = SelectLoadVector ( N ) ; break ; case NVPTXISD :: LDGV2 : case NVPTXISD :: LDGV4 : case NVPTXISD :: LDUV2 : case NVPTXISD :: LDUV4 : ResNode = SelectLDGLDUVector ( N ) ; break ; case NVPTXISD :: StoreV2 : case NVPTXISD :: StoreV4 : ResNode = SelectStoreVector ( N ) ; break ; case NVPTXISD :: LoadParam : case NVPTXISD :: LoadParamV2 : case NVPTXISD :: LoadParamV4 : ResNode = SelectLoadParam ( N ) ; break ; case NVPTXISD :: StoreRetval : case NVPTXISD :: StoreRetvalV2 : case NVPTXISD :: StoreRetvalV4 : ResNode = SelectStoreRetval ( N ) ; break ; case NVPTXISD :: StoreParam : case NVPTXISD :: StoreParamV2 : case NVPTXISD :: StoreParamV4 : case NVPTXISD :: StoreParamS32 : case NVPTXISD :: StoreParamU32 : ResNode = SelectStoreParam ( N ) ; break ; default : break ; } if ( ResNode ) return ResNode ; return SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> MachineInstr * ARMBaseInstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const { return 0 ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> enum direction function_arg_padding ( enum machine_mode mode , tree type ) { if ( ! AGGREGATE_PADDING_FIXED ) { if ( BYTES_BIG_ENDIAN ) { HOST_WIDE_INT size = 0 ; if ( mode == BLKmode ) { if ( type && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST ) size = int_size_in_bytes ( type ) ; } else size = GET_MODE_SIZE ( mode ) ; if ( size == 1 || size == 2 || size == 4 ) return downward ; } return upward ; } if ( AGGREGATES_PAD_UPWARD_ALWAYS ) { if ( type != 0 && AGGREGATE_TYPE_P ( type ) ) return upward ; } return DEFAULT_FUNCTION_ARG_PADDING ( mode , type ) ; } </s>

Handle the FUNCTION_ARG_PADDING macro . For the 64 bit ABI structs are always stored left shifted in their argument slot .


<s>
bool
Mips16HardFloat
::
runOnModule
(
Module
&
M
)
{
auto
&
TM
=
static_cast
<
const
MipsTargetMachine
&
>
(
getAnalysis
<
TargetPassConfig
>
(
)
.
getTM
<
TargetMachine
>
(
)
)
;
LLVM_DEBUG
(
errs
(
)
<<
"Run on Module Mips16HardFloat\n"
)
;
bool
Modified
=
false
;
for
(
Module
::
iterator
F
=
M
.
begin
(
)
,
E
=
M
.
end
(
)
;
F
!=
E
;
++
F
)
{
if
(
F
->
hasFnAttribute
(
"nomips16"
)
&&
F
->
hasFnAttribute
(
"use-soft-float"
)
)
{
removeUseSoftFloat
(
*
F
)
;
continue
;
}
if
(
F
->
isDeclaration
(
)
||
F
->
hasFnAttribute
(
"mips16_fp_stub"
)
||
F
->
hasFnAttribute
(
"nomips16"
)
)
continue
;
Modified
|=
fixupFPReturnAndCall
(
*
F
,
&
M
,
TM
)
;
FPParamVariant
V
=
whichFPParamVariantNeeded
(
*
F
)
;
if
(
V
!=
NoSig
)
{
Modified
=
true
;
createFPFnStub
(
&
*
F
,
&
M
,
V
,
TM
)
;
}
}
return
Modified
;
}
</s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s>
const
MCPhysReg
*
AArch64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_AArch64_NoRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_AArch64_AllRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_VectorCall
)
return
CSR_AArch64_AAVPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
CXX_FAST_TLS
)
return
MF
->
getInfo
<
AArch64FunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_AArch64_CXX_TLS_Darwin_PE_SaveList
:
CSR_AArch64_CXX_TLS_Darwin_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
.
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_AArch64_AAPCS_SwiftError_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
PreserveMost
)
return
CSR_AArch64_RT_MostRegs_SaveList
;
else
return
CSR_AArch64_AAPCS_SaveList
;
}
</s>


Define the ` __builtin_va_list ' type for the ABI .


<s> static char * avr_tolower ( char * lo , const char * up ) { char * lo0 = lo ; for ( ; * up ; up ++ , lo ++ ) * lo = TOLOWER ( * up ) ; * lo = '\0' ; return lo0 ; } </s>

Transform UP into lowercase and write the result to LO . You must provide enough space for LO . Return LO .


<s> bool X86InstrInfo :: analyzeCompare ( const MachineInstr * MI , unsigned & SrcReg , unsigned & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case X86 :: CMP64ri32 : case X86 :: CMP64ri8 : case X86 :: CMP32ri : case X86 :: CMP32ri8 : case X86 :: CMP16ri : case X86 :: CMP16ri8 : case X86 :: CMP8ri : SrcReg = MI -> getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = MI -> getOperand ( 1 ) . getImm ( ) ; return true ; case X86 :: CMP64rr : case X86 :: CMP32rr : case X86 :: CMP16rr : case X86 :: CMP8rr : SrcReg = MI -> getOperand ( 0 ) . getReg ( ) ; SrcReg2 = MI -> getOperand ( 1 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


"Didn't find MI in its own basic block?"

getOffsetOf - Return the current offset of the specified machine instruction from the start of the function .


runOnMachineFunction - Emit the function body .


<s> unsigned postKnownBits ( Align Align = llvm :: Align ( 1 ) ) const { return std :: max ( Log2 ( std :: max ( PostAlign , Align ) ) , internalKnownBits ( ) ) ; } </s>

Compute the number of known low bits of postOffset .


<s> void assignValueToAddress ( Register ValVReg , Register Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { if ( VA . getLocInfo ( ) == CCValAssign :: LocInfo :: AExt ) { Size = VA . getLocVT ( ) . getSizeInBits ( ) / 8 ; ValVReg = MIRBuilder . buildAnyExt ( LLT :: scalar ( Size * 8 ) , ValVReg ) . getReg ( 0 ) ; } auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , 1 ) ; MIRBuilder . buildStore ( ValVReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> bool Cpu0SEFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return isInt < 16 > ( MFI . getMaxCallFrameSize ( ) + getStackAlignment ( ) ) && ! MFI . hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> void TVMPassConfig :: addPreEmitPass ( ) { TargetPassConfig :: addPreEmitPass ( ) ; addPass ( createTVMContinuationsHoist ( ) ) ; addPass ( createTVMReplacePhysRegs ( ) ) ; addPass ( createTVMPrepareForLiveIntervals ( ) ) ; addPass ( createTVMRematerialize ( ) ) ; addPass ( createTVMRegStackify ( ) ) ; addPass ( createTVMLoopInstructions ( ) ) ; addPass ( createTVMMoveMaterializable ( ) ) ; addPass ( createTVMStackModel ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createTVMPeephole ( ) ) ; addPass ( createTVMRegNumbering ( ) ) ; } </s>

TVM TVM TVM TVM TVM TVM TVM TVM TVM TVM TVM TVM


<s> bool aarch64_float_const_rtx_p ( rtx x ) { machine_mode mode = GET_MODE ( x ) ; if ( mode == VOIDmode ) return false ; unsigned HOST_WIDE_INT ival ; if ( CONST_DOUBLE_P ( x ) && SCALAR_FLOAT_MODE_P ( mode ) && aarch64_reinterpret_float_as_int ( x , & ival ) ) { scalar_int_mode imode = ( mode == HFmode ? SImode : int_mode_for_mode ( mode ) . require ( ) ) ; int num_instr = aarch64_internal_mov_immediate ( NULL_RTX , gen_int_mode ( ival , imode ) , false , imode ) ; return num_instr < 3 ; } return false ; } </s>

Return TRUE if rtx X is an immediate constant that can be moved using a single MOV ( +MOVK ) followed by an FMOV .


<s>
unsigned
char
X86Subtarget
::
ClassifyGlobalReference
(
const
GlobalValue
*
GV
,
const
TargetMachine
&
TM
)
const
{
if
(
GV
->
hasDLLImportStorageClass
(
)
)
return
X86II
::
MO_DLLIMPORT
;
bool
isDecl
=
GV
->
hasAvailableExternallyLinkage
(
)
;
if
(
GV
->
isDeclaration
(
)
&&
!
GV
->
isMaterializable
(
)
)
isDecl
=
true
;
if
(
isPICStyleRIPRel
(
)
)
{
if
(
TM
.
getCodeModel
(
)
==
CodeModel
::
Large
)
return
X86II
::
MO_NO_FLAG
;
if
(
isTargetDarwin
(
)
)
{
if
(
GV
->
hasDefaultVisibility
(
)
&&
(
isDecl
||
GV
->
isWeakForLinker
(
)
)
)
return
X86II
::
MO_GOTPCREL
;
}
else
if
(
!
isTargetWin64
(
)
)
{
assert
(
isTargetELF
(
)
&&
"Unknown rip-relative target"
)
;
if
(
!
GV
->
hasLocalLinkage
(
)
&&
GV
->
hasDefaultVisibility
(
)
)
return
X86II
::
MO_GOTPCREL
;
}
return
X86II
::
MO_NO_FLAG
;
}
if
(
isPICStyleGOT
(
)
)
{
if
(
GV
->
hasLocalLinkage
(
)
||
GV
->
hasHiddenVisibility
(
)
)
return
X86II
::
MO_GOTOFF
;
return
X86II
::
MO_GOT
;
}
if
(
isPICStyleStubPIC
(
)
)
{
if
(
!
isDecl
&&
!
GV
->
isWeakForLinker
(
)
)
return
X86II
::
MO_PIC_BASE_OFFSET
;
if
(
!
GV
->
hasHiddenVisibility
(
)
)
return
X86II
::
MO_DARWIN_NONLAZY_PIC_BASE
;
if
(
isDecl
||
GV
->
hasCommonLinkage
(
)
)
{
return
X86II
::
MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE
;
}
return
X86II
::
MO_PIC_BASE_OFFSET
;
}
if
(
isPICStyleStubNoDynamic
(
)
)
{
if
(
!
isDecl
&&
!
GV
->
isWeakForLinker
(
)
)
return
X86II
::
MO_NO_FLAG
;
if
(
!
GV
->
hasHiddenVisibility
(
)
)
return
X86II
::
MO_DARWIN_NONLAZY
;
return
X86II
::
MO_NO_FLAG
;
}
return
X86II
::
MO_NO_FLAG
;
}
</s>

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be referenced for the current subtarget .


<s> static bool valid_perm_using_mode_p ( machine_mode vmode , struct expand_vec_perm_d * d ) { unsigned int i , j , chunk ; if ( GET_MODE_CLASS ( vmode ) != MODE_VECTOR_INT || GET_MODE_CLASS ( d -> vmode ) != MODE_VECTOR_INT || GET_MODE_SIZE ( vmode ) != GET_MODE_SIZE ( d -> vmode ) ) return false ; if ( GET_MODE_NUNITS ( vmode ) >= d -> nelt ) return true ; chunk = d -> nelt / GET_MODE_NUNITS ( vmode ) ; for ( i = 0 ; i < d -> nelt ; i += chunk ) if ( d -> perm [ i ] & ( chunk - 1 ) ) return false ; else for ( j = 1 ; j < chunk ; ++ j ) if ( d -> perm [ i ] + j != d -> perm [ i + j ] ) return false ; return true ; } </s>

Return true if permutation D can be performed as VMODE permutation instead .


<s> bool ARMBaseInstrInfo :: analyzeCompare ( const MachineInstr & MI , unsigned & SrcReg , unsigned & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI . getOpcode ( ) ) { default : break ; case ARM :: CMPri : case ARM :: t2CMPri : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 1 ) . getImm ( ) ; return true ; case ARM :: CMPrr : case ARM :: t2CMPrr : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 1 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case ARM :: TSTri : case ARM :: t2TSTri : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = MI . getOperand ( 1 ) . getImm ( ) ; CmpValue = 0 ; return true ; } return false ; } </s>


<s> bool runOnMachineFunction ( MachineFunction & F ) override { bool Changed = false ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; return Changed ; } </s>


<s>
int
legitimate_address_p
(
enum
machine_mode
mode
,
rtx
x
,
int
strict
)
{
enum
reg_class
r
=
NO_REGS
;
if
(
TARGET_ALL_DEBUG
)
{
fprintf
(
stderr
,
"mode: (%s) %s %s %s %s:"
,
GET_MODE_NAME
(
mode
)
,
strict
"(strict)"
:
""
,
reload_completed
"(reload_completed)"
:
""
,
reload_in_progress
"(reload_in_progress)"
:
""
,
reg_renumber
"(reg_renumber)"
:
""
)
;
if
(
GET_CODE
(
x
)
==
PLUS
&&
REG_P
(
XEXP
(
x
,
0
)
)
&&
GET_CODE
(
XEXP
(
x
,
1
)
)
==
CONST_INT
&&
INTVAL
(
XEXP
(
x
,
1
)
)
>=
0
&&
INTVAL
(
XEXP
(
x
,
1
)
)
<=
MAX_LD_OFFSET
(
mode
)
&&
reg_renumber
)
fprintf
(
stderr
,
"(r%d ---> r%d)"
,
REGNO
(
XEXP
(
x
,
0
)
)
,
true_regnum
(
XEXP
(
x
,
0
)
)
)
;
debug_rtx
(
x
)
;
}
if
(
REG_P
(
x
)
&&
(
strict
REG_OK_FOR_BASE_STRICT_P
(
x
)
:
REG_OK_FOR_BASE_NOSTRICT_P
(
x
)
)
)
r
=
POINTER_REGS
;
else
if
(
CONSTANT_ADDRESS_P
(
x
)
)
r
=
ALL_REGS
;
else
if
(
GET_CODE
(
x
)
==
PLUS
&&
REG_P
(
XEXP
(
x
,
0
)
)
&&
GET_CODE
(
XEXP
(
x
,
1
)
)
==
CONST_INT
&&
INTVAL
(
XEXP
(
x
,
1
)
)
>=
0
)
{
int
fit
=
INTVAL
(
XEXP
(
x
,
1
)
)
<=
MAX_LD_OFFSET
(
mode
)
;
if
(
fit
)
{
if
(
!
strict
||
REGNO
(
XEXP
(
x
,
0
)
)
==
REG_Y
||
REGNO
(
XEXP
(
x
,
0
)
)
==
REG_Z
)
r
=
BASE_POINTER_REGS
;
if
(
XEXP
(
x
,
0
)
==
frame_pointer_rtx
||
XEXP
(
x
,
0
)
==
arg_pointer_rtx
)
r
=
BASE_POINTER_REGS
;
}
else
if
(
frame_pointer_needed
&&
XEXP
(
x
,
0
)
==
frame_pointer_rtx
)
r
=
POINTER_Y_REGS
;
}
else
if
(
(
GET_CODE
(
x
)
==
PRE_DEC
||
GET_CODE
(
x
)
==
POST_INC
)
&&
REG_P
(
XEXP
(
x
,
0
)
)
&&
(
strict
REG_OK_FOR_BASE_STRICT_P
(
XEXP
(
x
,
0
)
)
:
REG_OK_FOR_BASE_NOSTRICT_P
(
XEXP
(
x
,
0
)
)
)
)
{
r
=
POINTER_REGS
;
}
if
(
TARGET_ALL_DEBUG
)
{
fprintf
(
stderr
,
"   ret = %c\n"
,
r
+
'0'
)
;
}
return
r
==
NO_REGS
0
:
(
int
)
r
;
}
</s>

legitimate_address_p returns 1 if it recognizes an RTL expression `` x '' that is a valid memory address for an instruction . The MODE argument is the machine mode for the MEM expression that wants to use this address .


<s> VariantKind getKind ( ) const { return Kind ; } </s>


<s> const AArch64InstrInfo * getInstrInfo ( ) const override { return getSubtargetImpl ( ) -> getInstrInfo ( ) ; } </s>


<s> const SNESRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> unsigned ARMTargetLowering :: getMaxSupportedInterleaveFactor ( ) const { if ( Subtarget -> hasNEON ( ) ) return 4 ; if ( Subtarget -> hasMVEIntegerOps ( ) ) return 4 ; return TargetLoweringBase :: getMaxSupportedInterleaveFactor ( ) ; } </s>

Get the maximum supported factor for interleaved memory accesses .


<s> void s390_initialize_trampoline ( rtx addr , rtx fnaddr , rtx cxt ) { emit_move_insn ( gen_rtx_MEM ( Pmode , memory_address ( Pmode , plus_constant ( addr , ( TARGET_64BIT ? 16 : 8 ) ) ) ) , cxt ) ; emit_move_insn ( gen_rtx_MEM ( Pmode , memory_address ( Pmode , plus_constant ( addr , ( TARGET_64BIT ? 24 : 12 ) ) ) ) , fnaddr ) ; } </s>

Emit RTL insns to initialize the variable parts of a trampoline . FNADDR is an RTX for the address of the function 's pure code . CXT is an RTX for the static chain value for the function .


<s> const TargetRegisterClass * ThumbRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { if ( ! MF . getSubtarget < ARMSubtarget > ( ) . isThumb1Only ( ) ) return ARMBaseRegisterInfo :: getLargestLegalSuperClass ( RC , MF ) ; if ( ARM :: tGPRRegClass . hasSubClassEq ( RC ) ) return & ARM :: tGPRRegClass ; return ARMBaseRegisterInfo :: getLargestLegalSuperClass ( RC , MF ) ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .

ARM ARM ARM ARM::tGPRRegClass ARM::tGPRRegClass ARM


<s> const XtensaRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>


"No offset range is defined for this opcode. "

"Please define it in the above switch statement!"


<s> bool PPCInstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Cond , unsigned TrueReg , unsigned FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( Cond . size ( ) != 2 ) return false ; if ( Cond [ 1 ] . getReg ( ) == PPC :: CTR || Cond [ 1 ] . getReg ( ) == PPC :: CTR8 ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( ! PPC :: GPRCRegClass . hasSubClassEq ( RC ) && ! PPC :: GPRC_NOR0RegClass . hasSubClassEq ( RC ) && ! PPC :: G8RCRegClass . hasSubClassEq ( RC ) && ! PPC :: G8RC_NOX0RegClass . hasSubClassEq ( RC ) ) return false ; CondCycles = 1 ; TrueCycles = 1 ; FalseCycles = 1 ; return true ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> int uses_TOC ( ) { rtx insn ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) ) { rtx pat = PATTERN ( insn ) ; int i ; if ( GET_CODE ( pat ) == PARALLEL ) for ( i = 0 ; i < XVECLEN ( PATTERN ( insn ) , 0 ) ; i ++ ) if ( GET_CODE ( XVECEXP ( PATTERN ( insn ) , 0 , i ) ) == UNSPEC && XINT ( XVECEXP ( PATTERN ( insn ) , 0 , i ) , 1 ) == 7 ) return 1 ; } return 0 ; } </s>

This retuns nonzero if the current function uses the TOC . This is determined by the presence of ( unspec ... 7 ) , which is generated by the various load_toc_ * patterns .


<s> bool SystemZInstrInfo :: FoldImmediate ( MachineInstr & UseMI , MachineInstr & DefMI , Register Reg , MachineRegisterInfo * MRI ) const { unsigned DefOpc = DefMI . getOpcode ( ) ; if ( DefOpc != SystemZ :: LHIMux && DefOpc != SystemZ :: LHI && DefOpc != SystemZ :: LGHI ) return false ; if ( DefMI . getOperand ( 0 ) . getReg ( ) != Reg ) return false ; int32_t ImmVal = ( int32_t ) DefMI . getOperand ( 1 ) . getImm ( ) ; unsigned UseOpc = UseMI . getOpcode ( ) ; unsigned NewUseOpc ; unsigned UseIdx ; int CommuteIdx = - 1 ; bool TieOps = false ; switch ( UseOpc ) { case SystemZ :: SELRMux : TieOps = true ; LLVM_FALLTHROUGH ; case SystemZ :: LOCRMux : if ( ! STI . hasLoadStoreOnCond2 ( ) ) return false ; NewUseOpc = SystemZ :: LOCHIMux ; if ( UseMI . getOperand ( 2 ) . getReg ( ) == Reg ) UseIdx = 2 ; else if ( UseMI . getOperand ( 1 ) . getReg ( ) == Reg ) UseIdx = 2 , CommuteIdx = 1 ; else return false ; break ; case SystemZ :: SELGR : TieOps = true ; LLVM_FALLTHROUGH ; case SystemZ :: LOCGR : if ( ! STI . hasLoadStoreOnCond2 ( ) ) return false ; NewUseOpc = SystemZ :: LOCGHI ; if ( UseMI . getOperand ( 2 ) . getReg ( ) == Reg ) UseIdx = 2 ; else if ( UseMI . getOperand ( 1 ) . getReg ( ) == Reg ) UseIdx = 2 , CommuteIdx = 1 ; else return false ; break ; default : return false ; } if ( CommuteIdx != - 1 ) if ( ! commuteInstruction ( UseMI , false , CommuteIdx , UseIdx ) ) return false ; bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ; UseMI . setDesc ( get ( NewUseOpc ) ) ; if ( TieOps ) UseMI . tieOperands ( 0 , 1 ) ; UseMI . getOperand ( UseIdx ) . ChangeToImmediate ( ImmVal ) ; if ( DeleteDef ) DefMI . eraseFromParent ( ) ; return true ; } </s>

Reg is known to be defined by a move immediate instruction , try to fold the immediate into the use instruction .


<s> OperandMatchResultTy RISCVAsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { const AsmToken & Tok = getParser ( ) . getTok ( ) ; StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; RegNo = 0 ; StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( matchRegisterNameHelper ( isRV32E ( ) , ( MCRegister & ) RegNo , Name ) ) return MatchOperand_NoMatch ; getParser ( ) . Lex ( ) ; return MatchOperand_Success ; } </s>

tryParseRegister - parse one register if possible


<s> std :: pair < unsigned , unsigned > M88kInstrInfo :: decomposeMachineOperandsTargetFlags ( unsigned TF ) const { return std :: make_pair ( TF , 0u ) ; } </s>

Decompose the machine operand 's target flags into two values - the direct target flag value and any of bit flags that are applied .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; initialize ( MF ) ; return simplifyCode ( ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool isConditionalBranch ( const MCInst & Inst ) const override { if ( Inst . getOpcode ( ) == ARM :: Bcc && Inst . getOperand ( 1 ) . getImm ( ) == ARMCC :: AL ) return false ; return MCInstrAnalysis :: isConditionalBranch ( Inst ) ; } </s>

Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static tree mips_build_cvpointer_type ( void ) { static tree cache ; if ( cache == NULL_TREE ) cache = build_pointer_type ( build_qualified_type ( void_type_node , TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE ) ) ; return cache ; } </s>

Return a type for 'const volatile void * ' .


<s> static bool mips_get_unaligned_mem ( rtx op , HOST_WIDE_INT width , HOST_WIDE_INT bitpos , rtx * left , rtx * right ) { rtx first , last ; if ( width != 32 && ( ! TARGET_64BIT || width != 64 ) ) return false ; if ( bitpos % BITS_PER_UNIT != 0 ) return false ; if ( MEM_ALIGN ( op ) >= width ) return false ; first = adjust_address ( op , QImode , 0 ) ; last = adjust_address ( op , QImode , width / BITS_PER_UNIT - 1 ) ; if ( TARGET_BIG_ENDIAN ) * left = first , * right = last ; else * left = last , * right = first ; return true ; } </s>

Return true if it is possible to use left/right accesses for a bitfield of WIDTH bits starting BITPOS bits into * OP . When returning true , update * OP , * LEFT and * RIGHT as follows : * OP is a BLKmode reference to the whole field . * LEFT is a QImode reference to the first byte if big endian or the last byte if little endian . This address can be used in the left-side instructions ( lwl , swl , ldl , sdl ) . * RIGHT is a QImode reference to the opposite end of the field and can be used in the patterning right-side instruction .


<s> bool AMDGPURegisterBankInfo :: executeInWaterfallLoop ( MachineInstr & MI , MachineRegisterInfo & MRI , ArrayRef < unsigned > OpIndices ) const { MachineIRBuilder B ( MI ) ; return executeInWaterfallLoop ( B , MI , MRI , OpIndices ) ; } </s>

Legalize instruction MI where operands in OpIndices must be SGPRs .


<s> void XCorePassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static rtx mips_legitimize_tls_address ( rtx loc ) { rtx dest , insn , v0 , tp , tmp1 , tmp2 , eqv , offset ; enum tls_model model ; model = SYMBOL_REF_TLS_MODEL ( loc ) ; if ( ! TARGET_ABICALLS ) model = TLS_MODEL_LOCAL_EXEC ; switch ( model ) { case TLS_MODEL_GLOBAL_DYNAMIC : v0 = gen_rtx_REG ( Pmode , GP_RETURN ) ; insn = mips_call_tls_get_addr ( loc , SYMBOL_TLSGD , v0 ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insn , dest , v0 , loc ) ; break ; case TLS_MODEL_LOCAL_DYNAMIC : v0 = gen_rtx_REG ( Pmode , GP_RETURN ) ; insn = mips_call_tls_get_addr ( loc , SYMBOL_TLSLDM , v0 ) ; tmp1 = gen_reg_rtx ( Pmode ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , const0_rtx ) , UNSPEC_TLS_LDM ) ; emit_libcall_block ( insn , tmp1 , v0 , eqv ) ; offset = mips_unspec_address ( loc , SYMBOL_DTPREL ) ; if ( mips_split_p [ SYMBOL_DTPREL ] ) { tmp2 = mips_unspec_offset_high ( NULL , tmp1 , loc , SYMBOL_DTPREL ) ; dest = gen_rtx_LO_SUM ( Pmode , tmp2 , offset ) ; } else dest = expand_binop ( Pmode , add_optab , tmp1 , offset , 0 , 0 , OPTAB_DIRECT ) ; break ; case TLS_MODEL_INITIAL_EXEC : tp = mips_get_tp ( ) ; tmp1 = gen_reg_rtx ( Pmode ) ; tmp2 = mips_unspec_address ( loc , SYMBOL_GOTTPREL ) ; if ( Pmode == DImode ) emit_insn ( gen_load_gotdi ( tmp1 , pic_offset_table_rtx , tmp2 ) ) ; else emit_insn ( gen_load_gotsi ( tmp1 , pic_offset_table_rtx , tmp2 ) ) ; dest = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_add3_insn ( dest , tmp1 , tp ) ) ; break ; case TLS_MODEL_LOCAL_EXEC : tmp1 = mips_get_tp ( ) ; offset = mips_unspec_address ( loc , SYMBOL_TPREL ) ; if ( mips_split_p [ SYMBOL_TPREL ] ) { tmp2 = mips_unspec_offset_high ( NULL , tmp1 , loc , SYMBOL_TPREL ) ; dest = gen_rtx_LO_SUM ( Pmode , tmp2 , offset ) ; } else dest = expand_binop ( Pmode , add_optab , tmp1 , offset , 0 , 0 , OPTAB_DIRECT ) ; break ; default : gcc_unreachable ( ) ; } return dest ; } </s>

Generate the code to access LOC , a thread local SYMBOL_REF . The return value will be a valid address and move_operand ( either a REG or a LO_SUM ) .


<s> static int thumb2_legitimate_index_p ( machine_mode mode , rtx index , int strict_p ) { enum rtx_code code = GET_CODE ( index ) ; if ( TARGET_VFP_BASE && ( mode == SFmode || mode == DFmode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 256 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE ( mode ) ) { if ( ! TARGET_LDRD || mode != DImode ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; } if ( TARGET_NEON && VALID_NEON_QREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1016 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( TARGET_NEON && VALID_NEON_DREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( arm_address_register_rtx_p ( index , strict_p ) && ( GET_MODE_SIZE ( mode ) <= 4 ) ) return 1 ; if ( mode == DImode || mode == DFmode ) { if ( code == CONST_INT ) { HOST_WIDE_INT val = INTVAL ( index ) ; if ( TARGET_LDRD ) return IN_RANGE ( val , - 1020 , 1020 ) && ( val & 3 ) == 0 ; else return IN_RANGE ( val , - 255 , 4095 - 4 ) ; } else return 0 ; } if ( code == MULT ) { rtx xiop0 = XEXP ( index , 0 ) ; rtx xiop1 = XEXP ( index , 1 ) ; return ( ( arm_address_register_rtx_p ( xiop0 , strict_p ) && thumb2_index_mul_operand ( xiop1 ) ) || ( arm_address_register_rtx_p ( xiop1 , strict_p ) && thumb2_index_mul_operand ( xiop0 ) ) ) ; } else if ( code == ASHIFT ) { rtx op = XEXP ( index , 1 ) ; return ( arm_address_register_rtx_p ( XEXP ( index , 0 ) , strict_p ) && CONST_INT_P ( op ) && INTVAL ( op ) > 0 && INTVAL ( op ) <= 3 ) ; } return ( code == CONST_INT && INTVAL ( index ) < 4096 && INTVAL ( index ) > - 256 ) ; } </s>

Return nonzero if INDEX is a valid Thumb-2 address index operand .


<s>
SDValue
SparcTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getTarget
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_Sparc32
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
if
(
RVLocs
[
i
]
.
isRegLoc
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
SPISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
return
DAG
.
getNode
(
SPISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool isReg ( ) const { return Kind == Register ; } </s>


<s>
void
alpha_output_filename
(
FILE
*
stream
,
const
char
*
name
)
{
static
int
first_time
=
TRUE
;
if
(
first_time
)
{
first_time
=
FALSE
;
++
num_source_filenames
;
current_function_file
=
name
;
fprintf
(
stream
,
"\t.file\t%d "
,
num_source_filenames
)
;
output_quoted_string
(
stream
,
name
)
;
fprintf
(
stream
,
"\n"
)
;
if
(
!
TARGET_GAS
&&
write_symbols
==
DBX_DEBUG
)
fprintf
(
stream
,
"\t#@stabs\n"
)
;
}
else
if
(
write_symbols
==
DBX_DEBUG
)
return
;
else
if
(
name
!=
current_function_file
&&
strcmp
(
name
,
current_function_file
)
!=
0
)
{
if
(
inside_function
&&
!
TARGET_GAS
)
fprintf
(
stream
,
"\t#.file\t%d "
,
num_source_filenames
)
;
else
{
++
num_source_filenames
;
current_function_file
=
name
;
fprintf
(
stream
,
"\t.file\t%d "
,
num_source_filenames
)
;
}
output_quoted_string
(
stream
,
name
)
;
fprintf
(
stream
,
"\n"
)
;
}
}
</s>

alpha
"\t.file\t%d "
"\n"
"\t#@stabs\n"
0
"\t#.file\t%d "
"\t.file\t%d "
"\n"


<s>
void
machopic_output_stub
(
FILE
*
file
,
const
char
*
symb
,
const
char
*
stub
)
{
unsigned
int
length
;
char
*
symbol_name
,
*
lazy_ptr_name
;
char
*
local_label_0
;
static
int
label
=
0
;
symb
=
(
*
targetm
.
strip_name_encoding
)
(
symb
)
;
length
=
strlen
(
symb
)
;
symbol_name
=
XALLOCAVEC
(
char
,
length
+
32
)
;
GEN_SYMBOL_NAME_FOR_SYMBOL
(
symbol_name
,
symb
,
length
)
;
lazy_ptr_name
=
XALLOCAVEC
(
char
,
length
+
32
)
;
GEN_LAZY_PTR_NAME_FOR_SYMBOL
(
lazy_ptr_name
,
symb
,
length
)
;
if
(
flag_pic
==
2
)
switch_to_section
(
darwin_sections
[
machopic_picsymbol_stub1_section
]
)
;
else
switch_to_section
(
darwin_sections
[
machopic_symbol_stub1_section
]
)
;
if
(
flag_pic
==
2
)
{
fprintf
(
file
,
"\t.align 5\n"
)
;
fprintf
(
file
,
"%s:\n"
,
stub
)
;
fprintf
(
file
,
"\t.indirect_symbol %s\n"
,
symbol_name
)
;
label
++
;
local_label_0
=
XALLOCAVEC
(
char
,
sizeof
(
"\"L00000000000$spb\""
)
)
;
sprintf
(
local_label_0
,
"\"L%011d$spb\""
,
label
)
;
fprintf
(
file
,
"\tmflr r0\n"
)
;
if
(
TARGET_LINK_STACK
)
{
char
name
[
32
]
;
get_ppc476_thunk_name
(
name
)
;
fprintf
(
file
,
"\tbl %s\n"
,
name
)
;
fprintf
(
file
,
"%s:\n\tmflr r11\n"
,
local_label_0
)
;
}
else
{
fprintf
(
file
,
"\tbcl 20,31,%s\n"
,
local_label_0
)
;
fprintf
(
file
,
"%s:\n\tmflr r11\n"
,
local_label_0
)
;
}
fprintf
(
file
,
"\taddis r11,r11,ha16(%s-%s)\n"
,
lazy_ptr_name
,
local_label_0
)
;
fprintf
(
file
,
"\tmtlr r0\n"
)
;
fprintf
(
file
,
"\t%s r12,lo16(%s-%s)(r11)\n"
,
(
TARGET_64BIT
"ldu"
:
"lwzu"
)
,
lazy_ptr_name
,
local_label_0
)
;
fprintf
(
file
,
"\tmtctr r12\n"
)
;
fprintf
(
file
,
"\tbctr\n"
)
;
}
else
{
fprintf
(
file
,
"\t.align 4\n"
)
;
fprintf
(
file
,
"%s:\n"
,
stub
)
;
fprintf
(
file
,
"\t.indirect_symbol %s\n"
,
symbol_name
)
;
fprintf
(
file
,
"\tlis r11,ha16(%s)\n"
,
lazy_ptr_name
)
;
fprintf
(
file
,
"\t%s r12,lo16(%s)(r11)\n"
,
(
TARGET_64BIT
"ldu"
:
"lwzu"
)
,
lazy_ptr_name
)
;
fprintf
(
file
,
"\tmtctr r12\n"
)
;
fprintf
(
file
,
"\tbctr\n"
)
;
}
switch_to_section
(
darwin_sections
[
machopic_lazy_symbol_ptr_section
]
)
;
fprintf
(
file
,
"%s:\n"
,
lazy_ptr_name
)
;
fprintf
(
file
,
"\t.indirect_symbol %s\n"
,
symbol_name
)
;
fprintf
(
file
,
"%sdyld_stub_binding_helper\n"
,
(
TARGET_64BIT
DOUBLE_INT_ASM_OP
:
"\t.long\t"
)
)
;
}
</s>

Generate external symbol indirection stubs ( PIC and non-PIC ) .

powerpcspe
0
32
32
2
2
"\t.align 5\n"
"%s:\n"
"\t.indirect_symbol %s\n"
"\"L00000000000$spb\""
"\"L%011d$spb\""
"\tmflr r0\n"
32
"\tbl %s\n"
"%s:\n\tmflr r11\n"
"\tbcl 20,31,%s\n"
"%s:\n\tmflr r11\n"
"\taddis r11,r11,ha16(%s-%s)\n"
"\tmtlr r0\n"
"\t%s r12,lo16(%s-%s)(r11)\n"
"ldu"
"lwzu"
"\tmtctr r12\n"
"\tbctr\n"
"\t.align 4\n"
"%s:\n"
"\t.indirect_symbol %s\n"
"\tlis r11,ha16(%s)\n"
"\t%s r12,lo16(%s)(r11)\n"
"ldu"
"lwzu"
"\tmtctr r12\n"
"\tbctr\n"
"%s:\n"
"\t.indirect_symbol %s\n"
"%sdyld_stub_binding_helper\n"
"\t.long\t"


<s> static unsigned rs6000_loop_unroll_adjust ( unsigned nunroll , struct loop * loop ) { if ( unroll_only_small_loops ) { if ( loop -> ninsns <= 6 ) return MIN ( 4 , nunroll ) ; if ( loop -> ninsns <= 10 ) return MIN ( 2 , nunroll ) ; return 0 ; } return nunroll ; } </s>


<s> int m32c_modes_tieable_p ( machine_mode m1 , machine_mode m2 ) { if ( GET_MODE_SIZE ( m1 ) == GET_MODE_SIZE ( m2 ) ) return 1 ; if ( m1 == QImode || m2 == QImode ) return 0 ; return 1 ; } </s>

Implements MODES_TIEABLE_P . In general , modes are n't tieable since registers are all different sizes . However , since most modes are bigger than our registers anyway , it 's easier to implement this function that way , leaving QImode as the only unique case .


<s> static int ia32_multipass_dfa_lookahead ( void ) { switch ( ix86_tune ) { case PROCESSOR_PENTIUM : return 2 ; case PROCESSOR_PENTIUMPRO : case PROCESSOR_K6 : return 1 ; case PROCESSOR_BDVER1 : case PROCESSOR_BDVER2 : case PROCESSOR_BDVER3 : case PROCESSOR_BDVER4 : return 4 ; case PROCESSOR_CORE2 : case PROCESSOR_NEHALEM : case PROCESSOR_SANDYBRIDGE : case PROCESSOR_HASWELL : case PROCESSOR_BONNELL : case PROCESSOR_SILVERMONT : case PROCESSOR_KNL : case PROCESSOR_INTEL : if ( reload_completed ) return ix86_issue_rate ( ) ; return 0 ; default : return 0 ; } } </s>

How many alternative schedules to try . This should be as wide as the scheduling freedom in the DFA , but no wider . Making this value too large results extra work for the scheduler .


"Callee should be an llvm::Function object."

"failed to perform tail call elimination on a call "

This hook must be implemented to lower calls into the specified DAG .


"Some operands reg class are incompatible!"

optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare ; remove Compare if possible .