<s> bool PPCDarwinAsmPrinter :: doFinalization ( Module & M ) { bool isPPC64 = TM . getTargetData ( ) -> getPointerSizeInBits ( ) == 64 ; TargetLoweringObjectFileMachO & TLOFMacho = static_cast < TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetFnStubList ( ) ; if ( ! Stubs . empty ( ) ) EmitFunctionStubs ( Stubs ) ; if ( MAI -> doesSupportExceptionHandling ( ) && MMI ) { const std :: vector < Function * > & Personalities = MMI -> getPersonalities ( ) ; for ( std :: vector < Function * > :: const_iterator I = Personalities . begin ( ) , E = Personalities . end ( ) ; I != E ; ++ I ) { if ( * I ) { MCSymbol * NLPSym = GetSymbolWithGlobalValueBase ( * I , "$non_lazy_ptr" ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMIMacho . getGVStubEntry ( NLPSym ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( * I ) , true ) ; } } } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue ( 0 , isPPC64 ? 8 : 4 , 0 ) ; else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 , 0 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 , 0 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


"flag setting instruction only valid outside IT block"

"instruction only valid inside IT block"

"instruction variant requires ARMv6 or later"

"immediate operand must be in the range [0,15]"

"immediate operand must be in the range [0,239]"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s>
bool
ARMLowOverheadLoops
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
!
static_cast
<
const
ARMSubtarget
&
>
(
MF
.
getSubtarget
(
)
)
.
hasLOB
(
)
)
return
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM Loops on "
<<
MF
.
getName
(
)
<<
" ------------- \n"
)
;
auto
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
TII
=
static_cast
<
const
ARMBaseInstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
BBUtils
=
std
::
unique_ptr
<
ARMBasicBlockUtils
>
(
new
ARMBasicBlockUtils
(
MF
)
)
;
BBUtils
->
computeAllBlockSizes
(
)
;
bool
Changed
=
false
;
for
(
auto
ML
:
MLI
)
{
if
(
!
ML
->
getParentLoop
(
)
)
Changed
|=
ProcessLoop
(
ML
)
;
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

ARM
ARM
ARM
"ARM Loops on "
" ------------- \n"
ARM
ARM
ARM


<s> SMLoc getEndLoc ( ) const { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> bool mips_pad_reg_upward ( machine_mode mode , tree type ) { if ( type != 0 ? FLOAT_TYPE_P ( type ) : GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return ! BYTES_BIG_ENDIAN ; return mips_function_arg_padding ( mode , type ) == PAD_UPWARD ; } </s>

Likewise BLOCK_REG_PADDING ( MODE , TYPE , ... ) . Return ! BYTES_BIG_ENDIAN if the least significant byte of the register has useful data . Return the opposite if the most significant byte does .


<s> static bool fault_first_load_p ( rtx_insn * rinsn ) { return recog_memoized ( rinsn ) >= 0 && get_attr_type ( rinsn ) == TYPE_VLDFF ; } </s>

Return true if the instruction is fault first load instruction .


<s> void BPFFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


<s> static bool z8k_legitimate_address_p ( enum machine_mode mode , rtx operand , bool strict ) { if ( REG_P ( operand ) && z8k_reg_ok_for_base_p ( operand ) ) return true ; if ( data_ref_p ( operand ) ) return true ; if ( inside_ba_p ( operand , strict ) ) return true ; if ( GET_CODE ( operand ) == PRE_DEC && mode == HImode && REGNO ( XEXP ( operand , 0 ) ) == STACK_POINTER_REGNUM ) return true ; if ( GET_CODE ( operand ) == PRE_DEC && mode == HImode && z8k_reg_ok_for_base_p ( XEXP ( operand , 0 ) ) ) return true ; if ( inside_x_p ( operand , strict ) ) return true ; if ( GET_MODE_SIZE ( mode ) <= 4 && inside_bx_p ( operand , strict ) ) return true ; return false ; } </s>

in any mode the z8k allows * ( reg ) eg ld r0 , ( r0 ) * ( da ) eg ld r0 , foo * ( reg+disp ) eg ld r0 , rr2 ( # 8 ) * ( pre-dec of the sp ) eg push sp , # 9 * * in non huge mode we can also * ( pre-dec of any reg ) eg push r0 , # 9 * ( address+reg ) eg ld r0 , address ( r0 ) * in small mode * ( reg+reg ) eg ld r0 , r1 ( r0 ) * *


<s> ARMTargetLowering :: ConstraintType ARMTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'l' : return C_RegisterClass ; case 'w' : return C_RegisterClass ; case 'h' : return C_RegisterClass ; case 'x' : return C_RegisterClass ; case 't' : return C_RegisterClass ; case 'j' : return C_Other ; case 'Q' : return C_Memory ; } } else if ( Constraint . size ( ) == 2 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'U' : return C_Memory ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> unsigned X86TargetLowering :: getByValTypeAlignment ( const Type * Ty ) const { if ( Subtarget -> is64Bit ( ) ) { unsigned TyAlign = TD -> getABITypeAlignment ( Ty ) ; if ( TyAlign > 8 ) return TyAlign ; return 8 ; } unsigned Align = 4 ; if ( Subtarget -> hasSSE1 ( ) ) getMaxByValAlign ( Ty , Align ) ; return Align ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


<s>
void
CSKYInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
Register
SrcReg
,
bool
IsKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
CSKYMachineFunctionInfo
*
CFI
=
MF
.
getInfo
<
CSKYMachineFunctionInfo
>
(
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
unsigned
Opcode
=
0
;
if
(
CSKY
::
GPRRegClass
.
hasSubClassEq
(
RC
)
)
{
Opcode
=
CSKY
::
ST32W
;
}
else
if
(
CSKY
::
CARRYRegClass
.
hasSubClassEq
(
RC
)
)
{
Opcode
=
CSKY
::
SPILL_CARRY
;
CFI
->
setSpillsCR
(
)
;
}
else
if
(
v2sf
&&
CSKY
::
sFPR32RegClass
.
hasSubClassEq
(
RC
)
)
Opcode
=
CSKY
::
FST_S
;
else
if
(
v2df
&&
CSKY
::
sFPR64RegClass
.
hasSubClassEq
(
RC
)
)
Opcode
=
CSKY
::
FST_D
;
else
if
(
v3sf
&&
CSKY
::
FPR32RegClass
.
hasSubClassEq
(
RC
)
)
Opcode
=
CSKY
::
f2FST_S
;
else
if
(
v3df
&&
CSKY
::
FPR64RegClass
.
hasSubClassEq
(
RC
)
)
Opcode
=
CSKY
::
f2FST_D
;
else
{
llvm_unreachable
(
"Unknown RegisterClass"
)
;
}
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
,
MachineMemOperand
::
MOStore
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlign
(
FI
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opcode
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
IsKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s>
void
SystemZTargetLowering
::
LowerOperationWrapper
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
switch
(
N
->
getOpcode
(
)
)
{
case
ISD
::
ATOMIC_LOAD
:
{
SDLoc
DL
(
N
)
;
SDVTList
Tys
=
DAG
.
getVTList
(
MVT
::
Untyped
,
MVT
::
Other
)
;
SDValue
Ops
[
]
=
{
N
->
getOperand
(
0
)
,
N
->
getOperand
(
1
)
}
;
MachineMemOperand
*
MMO
=
cast
<
AtomicSDNode
>
(
N
)
->
getMemOperand
(
)
;
SDValue
Res
=
DAG
.
getMemIntrinsicNode
(
SystemZISD
::
ATOMIC_LOAD_128
,
DL
,
Tys
,
Ops
,
MVT
::
i128
,
MMO
)
;
Results
.
push_back
(
lowerGR128ToI128
(
DAG
,
Res
)
)
;
Results
.
push_back
(
Res
.
getValue
(
1
)
)
;
break
;
}
case
ISD
::
ATOMIC_STORE
:
{
SDLoc
DL
(
N
)
;
SDVTList
Tys
=
DAG
.
getVTList
(
MVT
::
Other
)
;
SDValue
Ops
[
]
=
{
N
->
getOperand
(
0
)
,
lowerI128ToGR128
(
DAG
,
N
->
getOperand
(
2
)
)
,
N
->
getOperand
(
1
)
}
;
MachineMemOperand
*
MMO
=
cast
<
AtomicSDNode
>
(
N
)
->
getMemOperand
(
)
;
SDValue
Res
=
DAG
.
getMemIntrinsicNode
(
SystemZISD
::
ATOMIC_STORE_128
,
DL
,
Tys
,
Ops
,
MVT
::
i128
,
MMO
)
;
if
(
cast
<
AtomicSDNode
>
(
N
)
->
getSuccessOrdering
(
)
==
AtomicOrdering
::
SequentiallyConsistent
)
Res
=
SDValue
(
DAG
.
getMachineNode
(
SystemZ
::
Serialize
,
DL
,
MVT
::
Other
,
Res
)
,
0
)
;
Results
.
push_back
(
Res
)
;
break
;
}
case
ISD
::
ATOMIC_CMP_SWAP_WITH_SUCCESS
:
{
SDLoc
DL
(
N
)
;
SDVTList
Tys
=
DAG
.
getVTList
(
MVT
::
Untyped
,
MVT
::
i32
,
MVT
::
Other
)
;
SDValue
Ops
[
]
=
{
N
->
getOperand
(
0
)
,
N
->
getOperand
(
1
)
,
lowerI128ToGR128
(
DAG
,
N
->
getOperand
(
2
)
)
,
lowerI128ToGR128
(
DAG
,
N
->
getOperand
(
3
)
)
}
;
MachineMemOperand
*
MMO
=
cast
<
AtomicSDNode
>
(
N
)
->
getMemOperand
(
)
;
SDValue
Res
=
DAG
.
getMemIntrinsicNode
(
SystemZISD
::
ATOMIC_CMP_SWAP_128
,
DL
,
Tys
,
Ops
,
MVT
::
i128
,
MMO
)
;
SDValue
Success
=
emitSETCC
(
DAG
,
DL
,
Res
.
getValue
(
1
)
,
SystemZ
::
CCMASK_CS
,
SystemZ
::
CCMASK_CS_EQ
)
;
Success
=
DAG
.
getZExtOrTrunc
(
Success
,
DL
,
N
->
getValueType
(
1
)
)
;
Results
.
push_back
(
lowerGR128ToI128
(
DAG
,
Res
)
)
;
Results
.
push_back
(
Success
)
;
Results
.
push_back
(
Res
.
getValue
(
2
)
)
;
break
;
}
default
:
llvm_unreachable
(
"Unexpected node to lower"
)
;
}
}
</s>

This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types .


"instruction use requires an option to be enabled"


<s> bool HexagonCopyToCombine :: runOnMachineFunction ( MachineFunction & MF ) { if ( IsCombinesDisabled ) return false ; bool HasChanged = false ; ST = & MF . getSubtarget < HexagonSubtarget > ( ) ; TRI = ST -> getRegisterInfo ( ) ; TII = ST -> getInstrInfo ( ) ; const Function * F = MF . getFunction ( ) ; bool OptForSize = F -> hasFnAttribute ( Attribute :: OptimizeForSize ) ; ShouldCombineAggressively = MF . getTarget ( ) . getOptLevel ( ) <= CodeGenOpt :: Default ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( * BI ) ; for ( MachineBasicBlock :: iterator MI = BI -> begin ( ) , End = BI -> end ( ) ; MI != End ; ) { MachineInstr & I1 = * MI ++ ; if ( I1 . isDebugValue ( ) ) continue ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( & I1 ) ) continue ; if ( ! isCombinableInstType ( I1 , TII , ShouldCombineAggressively ) ) continue ; bool DoInsertAtI1 = false ; DbgMItoMove . clear ( ) ; MachineInstr * I2 = findPairable ( I1 , DoInsertAtI1 , OptForSize ) ; if ( I2 ) { HasChanged = true ; combine ( I1 , * I2 , MI , DoInsertAtI1 , OptForSize ) ; } } } return HasChanged ; } </s>


<s>
MachineBasicBlock
*
SIWholeQuadMode
::
splitBlock
(
MachineBasicBlock
*
BB
,
MachineInstr
*
TermMI
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Split block "
<<
printMBBReference
(
*
BB
)
<<
" @ "
<<
*
TermMI
<<
"\n"
)
;
MachineBasicBlock
*
SplitBB
=
BB
->
splitAt
(
*
TermMI
,
true
,
LIS
)
;
unsigned
NewOpcode
=
0
;
switch
(
TermMI
->
getOpcode
(
)
)
{
case
AMDGPU
::
S_AND_B32
:
NewOpcode
=
AMDGPU
::
S_AND_B32_term
;
break
;
case
AMDGPU
::
S_AND_B64
:
NewOpcode
=
AMDGPU
::
S_AND_B64_term
;
break
;
case
AMDGPU
::
S_MOV_B32
:
NewOpcode
=
AMDGPU
::
S_MOV_B32_term
;
break
;
case
AMDGPU
::
S_MOV_B64
:
NewOpcode
=
AMDGPU
::
S_MOV_B64_term
;
break
;
default
:
break
;
}
if
(
NewOpcode
)
TermMI
->
setDesc
(
TII
->
get
(
NewOpcode
)
)
;
if
(
SplitBB
!=
BB
)
{
using
DomTreeT
=
DomTreeBase
<
MachineBasicBlock
>
;
SmallVector
<
DomTreeT
::
UpdateType
,
16
>
DTUpdates
;
for
(
MachineBasicBlock
*
Succ
:
SplitBB
->
successors
(
)
)
{
DTUpdates
.
push_back
(
{
DomTreeT
::
Insert
,
SplitBB
,
Succ
}
)
;
DTUpdates
.
push_back
(
{
DomTreeT
::
Delete
,
BB
,
Succ
}
)
;
}
DTUpdates
.
push_back
(
{
DomTreeT
::
Insert
,
BB
,
SplitBB
}
)
;
if
(
MDT
)
MDT
->
getBase
(
)
.
applyUpdates
(
DTUpdates
)
;
if
(
PDT
)
PDT
->
getBase
(
)
.
applyUpdates
(
DTUpdates
)
;
MachineInstr
*
MI
=
BuildMI
(
*
BB
,
BB
->
end
(
)
,
DebugLoc
(
)
,
TII
->
get
(
AMDGPU
::
S_BRANCH
)
)
.
addMBB
(
SplitBB
)
;
LIS
->
InsertMachineInstrInMaps
(
*
MI
)
;
}
return
SplitBB
;
}
</s>

splitBlock - BB is split and now it has one successor .


<s> static rtx altivec_expand_st_builtin ( tree exp , rtx target ATTRIBUTE_UNUSED , bool * expandedp ) { tree fndecl = TREE_OPERAND ( TREE_OPERAND ( exp , 0 ) , 0 ) ; tree arglist = TREE_OPERAND ( exp , 1 ) ; unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; tree arg0 , arg1 ; enum machine_mode mode0 , mode1 ; rtx pat , op0 , op1 ; enum insn_code icode ; switch ( fcode ) { case ALTIVEC_BUILTIN_ST_INTERNAL_16qi : icode = CODE_FOR_altivec_stvx_v16qi ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_8hi : icode = CODE_FOR_altivec_stvx_v8hi ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_4si : icode = CODE_FOR_altivec_stvx_v4si ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_4sf : icode = CODE_FOR_altivec_stvx_v4sf ; break ; default : * expandedp = false ; return NULL_RTX ; } arg0 = TREE_VALUE ( arglist ) ; arg1 = TREE_VALUE ( TREE_CHAIN ( arglist ) ) ; op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , 0 ) ; op1 = expand_expr ( arg1 , NULL_RTX , VOIDmode , 0 ) ; mode0 = insn_data [ icode ] . operand [ 0 ] . mode ; mode1 = insn_data [ icode ] . operand [ 1 ] . mode ; if ( ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( op0 , mode0 ) ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( pat ) emit_insn ( pat ) ; * expandedp = true ; return NULL_RTX ; } </s>


<s> static bool isEqual ( const GCNRPTracker :: LiveRegSet & S1 , const GCNRPTracker :: LiveRegSet & S2 ) { if ( S1 . size ( ) != S2 . size ( ) ) return false ; for ( const auto & P : S1 ) { auto I = S2 . find ( P . first ) ; if ( I == S2 . end ( ) || I -> second != P . second ) return false ; } return true ; } </s>

isEqual - Compares two trees for structural equality and returns true if they are equal .


<s>
void
AArch64TargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this"
)
;
case
ISD
::
BITCAST
:
ReplaceBITCASTResults
(
N
,
Results
,
DAG
)
;
return
;
case
AArch64ISD
::
SADDV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
ADD
,
AArch64ISD
::
SADDV
)
;
return
;
case
AArch64ISD
::
UADDV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
ADD
,
AArch64ISD
::
UADDV
)
;
return
;
case
AArch64ISD
::
SMINV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
SMIN
,
AArch64ISD
::
SMINV
)
;
return
;
case
AArch64ISD
::
UMINV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
UMIN
,
AArch64ISD
::
UMINV
)
;
return
;
case
AArch64ISD
::
SMAXV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
SMAX
,
AArch64ISD
::
SMAXV
)
;
return
;
case
AArch64ISD
::
UMAXV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
UMAX
,
AArch64ISD
::
UMAXV
)
;
return
;
case
ISD
::
FP_TO_UINT
:
case
ISD
::
FP_TO_SINT
:
assert
(
N
->
getValueType
(
0
)
==
MVT
::
i128
&&
"unexpected illegal conversion"
)
;
return
;
}
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> bool isImm ( ) const override { return Kind == KindTy :: Immediate ; } </s>


<s> bool AArch64InstrInfo :: isThroughputPattern ( MachineCombinerPattern Pattern ) const { switch ( Pattern ) { default : break ; case MachineCombinerPattern :: FMULADDS_OP1 : case MachineCombinerPattern :: FMULADDS_OP2 : case MachineCombinerPattern :: FMULSUBS_OP1 : case MachineCombinerPattern :: FMULSUBS_OP2 : case MachineCombinerPattern :: FMULADDD_OP1 : case MachineCombinerPattern :: FMULADDD_OP2 : case MachineCombinerPattern :: FMULSUBD_OP1 : case MachineCombinerPattern :: FMULSUBD_OP2 : case MachineCombinerPattern :: FNMULSUBS_OP1 : case MachineCombinerPattern :: FNMULSUBD_OP1 : case MachineCombinerPattern :: FMLAv1i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv1i32_indexed_OP2 : case MachineCombinerPattern :: FMLAv1i64_indexed_OP1 : case MachineCombinerPattern :: FMLAv1i64_indexed_OP2 : case MachineCombinerPattern :: FMLAv2f32_OP2 : case MachineCombinerPattern :: FMLAv2f32_OP1 : case MachineCombinerPattern :: FMLAv2f64_OP1 : case MachineCombinerPattern :: FMLAv2f64_OP2 : case MachineCombinerPattern :: FMLAv2i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv2i32_indexed_OP2 : case MachineCombinerPattern :: FMLAv2i64_indexed_OP1 : case MachineCombinerPattern :: FMLAv2i64_indexed_OP2 : case MachineCombinerPattern :: FMLAv4f32_OP1 : case MachineCombinerPattern :: FMLAv4f32_OP2 : case MachineCombinerPattern :: FMLAv4i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv4i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv1i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv1i64_indexed_OP2 : case MachineCombinerPattern :: FMLSv2i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv2i64_indexed_OP2 : case MachineCombinerPattern :: FMLSv2f32_OP2 : case MachineCombinerPattern :: FMLSv2f64_OP2 : case MachineCombinerPattern :: FMLSv4i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv4f32_OP2 : return true ; } return false ; } </s>

Return true when a code sequence can improve throughput .


<s> bool MipsTargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { return ( IsGlobalInSmallSectionImpl ( GV , TM ) && ( Kind . isData ( ) || Kind . isBSS ( ) || Kind . isCommon ( ) ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> const char * RISCVTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { OPCODE ( RET_FLAG ) ; OPCODE ( CALL ) ; OPCODE ( PCREL_WRAPPER ) ; OPCODE ( Hi ) ; OPCODE ( Lo ) ; OPCODE ( FENCE ) ; OPCODE ( SELECT_CC ) ; } return NULL ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> void insert ( const GepNode * N ) { insert ( std :: make_pair ( N , ++ LastNum ) ) ; } </s>

insert - Append entry to the vector if it does n't already exist .


<s>
StringRef
getPassName
(
)
const
override
{
return
"If-convert TVM terminators"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static unsigned int nvptx_hard_regno_nregs ( unsigned int , machine_mode ) { return 1 ; } </s>


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"ARM64 load / store optimization pass"
;
}
</s>


<s> void ARMElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { bool isAAPCS_ABI = TM . getSubtarget < ARMSubtarget > ( ) . isAAPCS_ABI ( ) ; TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( isAAPCS_ABI ) ; if ( isAAPCS_ABI && ! TM . getSubtarget < ARMSubtarget > ( ) . isTargetNaCl ( ) ) { LSDASection = NULL ; } AttributesSection = getContext ( ) . getELFSection ( ".ARM.attributes" , ELF :: SHT_ARM_ATTRIBUTES , 0 , SectionKind :: getMetadata ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s> bool s390_contiguous_bitmask_p ( unsigned HOST_WIDE_INT in , int size , int * pos , int * length ) { int tmp_pos = 0 ; int tmp_length = 0 ; int i ; unsigned HOST_WIDE_INT mask = 1ULL ; bool contiguous = false ; for ( i = 0 ; i < size ; mask <<= 1 , i ++ ) { if ( contiguous ) { if ( mask & in ) tmp_length ++ ; else break ; } else { if ( mask & in ) { contiguous = true ; tmp_length ++ ; } else tmp_pos ++ ; } } if ( ! tmp_length ) return false ; mask = ( - 1LL & ~ ( ( ( 1ULL << ( tmp_length + tmp_pos - 1 ) ) << 1 ) - 1 ) ) ; if ( ( unsigned ) size < sizeof ( HOST_WIDE_INT ) * BITS_PER_UNIT ) mask &= ( HOST_WIDE_INT_1U << size ) - 1 ; if ( mask & in ) return false ; if ( tmp_length + tmp_pos - 1 > size ) return false ; if ( length ) * length = tmp_length ; if ( pos ) * pos = tmp_pos ; return true ; } </s>

Return true if IN contains a contiguous bitfield in the lower SIZE bits and no other bits are set in IN . POS and LENGTH can be used to obtain the start position and the length of the bitfield . POS gives the position of the first bit of the bitfield counting from the lowest order bit starting with zero . In order to use this value for S/390 instructions this has to be converted to `` bits big endian '' style .


<s>
SDValue
BlackfinTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getTarget
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_Blackfin
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Opi
=
Outs
[
i
]
.
Val
;
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
SExt
:
Opi
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Opi
)
;
break
;
case
CCValAssign
::
ZExt
:
Opi
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Opi
)
;
break
;
case
CCValAssign
::
AExt
:
Opi
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Opi
)
;
break
;
}
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
Opi
,
SDValue
(
)
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
{
return
DAG
.
getNode
(
BFISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
}
else
{
return
DAG
.
getNode
(
BFISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static bool riscv_pass_by_reference ( cumulative_args_t cum_v , enum machine_mode mode , const_tree type , bool named ) { HOST_WIDE_INT size = type ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ; struct riscv_arg_info info ; CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( cum != NULL ) { riscv_get_arg_info ( & info , cum , mode , type , named , false ) ; if ( info . num_fprs ) return false ; } return ! IN_RANGE ( size , 0 , 2 * UNITS_PER_WORD ) ; } </s>


runOnMachineFunction - Emit the function body .


<s> const char * riscv_output_move ( rtx dest , rtx src ) { enum rtx_code dest_code , src_code ; machine_mode mode ; bool dbl_p ; dest_code = GET_CODE ( dest ) ; src_code = GET_CODE ( src ) ; mode = GET_MODE ( dest ) ; dbl_p = ( GET_MODE_SIZE ( mode ) == 8 ) ; if ( dbl_p && riscv_split_64bit_move_p ( dest , src ) ) return "#" ; if ( dest_code == REG && GP_REG_P ( REGNO ( dest ) ) ) { if ( src_code == REG && FP_REG_P ( REGNO ( src ) ) ) return dbl_p ? "fmv.x.d\t%0,%1" : "fmv.x.w\t%0,%1" ; if ( src_code == MEM ) switch ( GET_MODE_SIZE ( mode ) ) { case 1 : return "lbu\t%0,%1" ; case 2 : return "lhu\t%0,%1" ; case 4 : return "lw\t%0,%1" ; case 8 : return "ld\t%0,%1" ; } if ( src_code == CONST_INT ) { if ( SMALL_OPERAND ( INTVAL ( src ) ) || LUI_OPERAND ( INTVAL ( src ) ) ) return "li\t%0,%1" ; if ( TARGET_ZBS && SINGLE_BIT_MASK_OPERAND ( INTVAL ( src ) ) ) return "bseti\t%0,zero,%S1" ; abort ( ) ; } if ( src_code == HIGH ) return "lui\t%0,%h1" ; if ( symbolic_operand ( src , VOIDmode ) ) switch ( riscv_classify_symbolic_expression ( src ) ) { case SYMBOL_GOT_DISP : return "la\t%0,%1" ; case SYMBOL_ABSOLUTE : return "lla\t%0,%1" ; case SYMBOL_PCREL : return "lla\t%0,%1" ; default : gcc_unreachable ( ) ; } } if ( ( src_code == REG && GP_REG_P ( REGNO ( src ) ) ) || ( src == CONST0_RTX ( mode ) ) ) { if ( dest_code == REG ) { if ( GP_REG_P ( REGNO ( dest ) ) ) return "mv\t%0,%z1" ; if ( FP_REG_P ( REGNO ( dest ) ) ) { if ( ! dbl_p ) return "fmv.w.x\t%0,%z1" ; if ( TARGET_64BIT ) return "fmv.d.x\t%0,%z1" ; gcc_assert ( src == CONST0_RTX ( mode ) ) ; return "fcvt.d.w\t%0,x0" ; } } if ( dest_code == MEM ) switch ( GET_MODE_SIZE ( mode ) ) { case 1 : return "sb\t%z1,%0" ; case 2 : return "sh\t%z1,%0" ; case 4 : return "sw\t%z1,%0" ; case 8 : return "sd\t%z1,%0" ; } } if ( src_code == REG && FP_REG_P ( REGNO ( src ) ) ) { if ( dest_code == REG && FP_REG_P ( REGNO ( dest ) ) ) return dbl_p ? "fmv.d\t%0,%1" : "fmv.s\t%0,%1" ; if ( dest_code == MEM ) return dbl_p ? "fsd\t%1,%0" : "fsw\t%1,%0" ; } if ( dest_code == REG && FP_REG_P ( REGNO ( dest ) ) ) { if ( src_code == MEM ) return dbl_p ? "fld\t%0,%1" : "flw\t%0,%1" ; } gcc_unreachable ( ) ; } </s>

Return the appropriate instructions to move SRC into DEST . Assume that SRC is operand 1 and DEST is operand 0 .


<s> static void riscv_save_reg ( rtx reg , rtx mem ) { riscv_emit_move ( mem , reg ) ; riscv_set_frame_expr ( riscv_frame_set ( mem , reg ) ) ; } </s>

Save register REG to MEM . Make the instruction frame-related .


<s>
StringRef
getPassName
(
)
const
override
{
return
"PowerPC Branch Selector"
;
}
</s>


<s>
void
ARCFrameLowering
::
determineCalleeSaves
(
MachineFunction
&
MF
,
BitVector
&
SavedRegs
,
RegScavenger
*
RS
)
const
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Determine Callee Saves: "
<<
MF
.
getName
(
)
<<
"\n"
)
;
TargetFrameLowering
::
determineCalleeSaves
(
MF
,
SavedRegs
,
RS
)
;
SavedRegs
.
set
(
ARC
::
BLINK
)
;
}
</s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .

ARC
ARC
"Determine Callee Saves: "
"\n"
ARC::BLINK


<s> static int address_needs_split ( rtx mem ) { if ( GET_MODE_SIZE ( GET_MODE ( mem ) ) < 16 && ( GET_MODE_SIZE ( GET_MODE ( mem ) ) < 4 || ! ( store_with_one_insn_p ( mem ) || mem_is_padded_component_ref ( mem ) ) ) ) return 1 ; return 0 ; } </s>

Return 1 when the address is not valid for a simple load and store as required by the '_mov * ' patterns . We could make this less strict for loads , but we prefer mem 's to look the same so they are more likely to be merged .


<s> bool SIInstrInfo :: shouldClusterMemOps ( MachineInstr * FirstLdSt , MachineInstr * SecondLdSt , unsigned NumLoads ) const { const MachineOperand * FirstDst = nullptr ; const MachineOperand * SecondDst = nullptr ; if ( isDS ( * FirstLdSt ) && isDS ( * SecondLdSt ) ) { FirstDst = getNamedOperand ( * FirstLdSt , AMDGPU :: OpName :: vdst ) ; SecondDst = getNamedOperand ( * SecondLdSt , AMDGPU :: OpName :: vdst ) ; } if ( isSMRD ( * FirstLdSt ) && isSMRD ( * SecondLdSt ) ) { FirstDst = getNamedOperand ( * FirstLdSt , AMDGPU :: OpName :: sdst ) ; SecondDst = getNamedOperand ( * SecondLdSt , AMDGPU :: OpName :: sdst ) ; } if ( ( isMUBUF ( * FirstLdSt ) && isMUBUF ( * SecondLdSt ) ) || ( isMTBUF ( * FirstLdSt ) && isMTBUF ( * SecondLdSt ) ) ) { FirstDst = getNamedOperand ( * FirstLdSt , AMDGPU :: OpName :: vdata ) ; SecondDst = getNamedOperand ( * SecondLdSt , AMDGPU :: OpName :: vdata ) ; } if ( ! FirstDst || ! SecondDst ) return false ; unsigned LoadClusterThreshold = 16 ; const MachineRegisterInfo & MRI = FirstLdSt -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * DstRC = MRI . getRegClass ( FirstDst -> getReg ( ) ) ; return ( NumLoads * DstRC -> getSize ( ) ) <= LoadClusterThreshold ; } </s>

Returns true if the two given memory operations should be scheduled adjacent .

AMDGPU SI AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName 16


<s>
void
gen_conditional_branch
(
rtx
operands
[
]
,
enum
rtx_code
test_code
)
{
enum
cmp_type
type
=
branch_type
;
rtx
cmp0
=
branch_cmp
[
0
]
;
rtx
cmp1
=
branch_cmp
[
1
]
;
enum
machine_mode
mode
;
rtx
reg
;
int
invert
;
rtx
label1
,
label2
;
switch
(
type
)
{
case
CMP_SI
:
case
CMP_DI
:
mode
=
type
==
CMP_SI
SImode
:
DImode
;
invert
=
0
;
reg
=
gen_int_relational
(
test_code
,
NULL_RTX
,
cmp0
,
cmp1
,
&
invert
)
;
if
(
reg
)
{
cmp0
=
reg
;
cmp1
=
const0_rtx
;
test_code
=
NE
;
}
else
if
(
GET_CODE
(
cmp1
)
==
CONST_INT
&&
INTVAL
(
cmp1
)
!=
0
)
cmp1
=
force_reg
(
mode
,
cmp1
)
;
break
;
case
CMP_SF
:
case
CMP_DF
:
reg
=
gen_reg_rtx
(
CCmode
)
;
emit_insn
(
gen_rtx_SET
(
VOIDmode
,
reg
,
gen_rtx_fmt_ee
(
test_code
==
NE
EQ
:
test_code
,
CCmode
,
cmp0
,
cmp1
)
)
)
;
test_code
=
test_code
==
NE
EQ
:
NE
;
mode
=
CCmode
;
cmp0
=
reg
;
cmp1
=
const0_rtx
;
invert
=
0
;
break
;
default
:
abort_with_insn
(
gen_rtx_fmt_ee
(
test_code
,
VOIDmode
,
cmp0
,
cmp1
)
,
"bad test"
)
;
}
label1
=
gen_rtx_LABEL_REF
(
VOIDmode
,
operands
[
0
]
)
;
label2
=
pc_rtx
;
if
(
invert
)
{
label2
=
label1
;
label1
=
pc_rtx
;
}
emit_jump_insn
(
gen_rtx_SET
(
VOIDmode
,
pc_rtx
,
gen_rtx_IF_THEN_ELSE
(
VOIDmode
,
gen_rtx_fmt_ee
(
test_code
,
mode
,
cmp0
,
cmp1
)
,
label1
,
label2
)
)
)
;
}
</s>

Emit the common code for doing conditional branches . operand [ 0 ] is the label to jump to . The comparison operands are saved away by cmp { si , di , sf , df } .


Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calling convention CallConv .


<s> static rtx ix86_function_arg ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; machine_mode mode = arg . mode ; HOST_WIDE_INT bytes , words ; rtx reg ; if ( ! cum -> caller && cfun -> machine -> func_type != TYPE_NORMAL ) { gcc_assert ( arg . type != NULL_TREE ) ; if ( POINTER_TYPE_P ( arg . type ) ) { gcc_assert ( TYPE_MODE ( arg . type ) == ptr_mode ) ; reg = plus_constant ( Pmode , arg_pointer_rtx , - UNITS_PER_WORD ) ; } else { gcc_assert ( cfun -> machine -> func_type == TYPE_EXCEPTION && TREE_CODE ( arg . type ) == INTEGER_TYPE && TYPE_MODE ( arg . type ) == word_mode ) ; reg = gen_rtx_MEM ( word_mode , plus_constant ( Pmode , arg_pointer_rtx , - 2 * UNITS_PER_WORD ) ) ; } return reg ; } bytes = arg . promoted_size_in_bytes ( ) ; words = CEIL ( bytes , UNITS_PER_WORD ) ; if ( arg . type && TREE_CODE ( arg . type ) == VECTOR_TYPE ) mode = type_natural_mode ( arg . type , cum , false ) ; if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) reg = function_arg_ms_64 ( cum , mode , arg . mode , arg . named , arg . type , bytes ) ; else reg = function_arg_64 ( cum , mode , arg . mode , arg . type , arg . named ) ; } else reg = function_arg_32 ( cum , mode , arg . mode , arg . type , bytes , words ) ; if ( reg == NULL_RTX && cum -> caller ) cfun -> machine -> outgoing_args_on_stack = true ; return reg ; } </s>

Return where to put the arguments to a function . Return zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument . It is null for libcalls where that information may not be available . CUM gives information about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) .


<s> static bool arm_const_not_ok_for_debug_p ( rtx p ) { tree decl_op0 = NULL ; tree decl_op1 = NULL ; if ( GET_CODE ( p ) == MINUS ) { if ( GET_CODE ( XEXP ( p , 1 ) ) == SYMBOL_REF ) { decl_op1 = SYMBOL_REF_DECL ( XEXP ( p , 1 ) ) ; if ( decl_op1 && GET_CODE ( XEXP ( p , 0 ) ) == SYMBOL_REF && ( decl_op0 = SYMBOL_REF_DECL ( XEXP ( p , 0 ) ) ) ) { if ( ( TREE_CODE ( decl_op1 ) == VAR_DECL || TREE_CODE ( decl_op1 ) == CONST_DECL ) && ( TREE_CODE ( decl_op0 ) == VAR_DECL || TREE_CODE ( decl_op0 ) == CONST_DECL ) ) return ( get_variable_section ( decl_op1 , false ) != get_variable_section ( decl_op0 , false ) ) ; if ( TREE_CODE ( decl_op1 ) == LABEL_DECL && TREE_CODE ( decl_op0 ) == LABEL_DECL ) return ( DECL_CONTEXT ( decl_op1 ) != DECL_CONTEXT ( decl_op0 ) ) ; } return true ; } } return false ; } </s>

This is a temporary fix for PR60655 . Ideally we need to handle most of these cases in the generic part but currently we reject minus ( .. ) ( sym_ref ) . We try to ameliorate the case with minus ( sym_ref1 ) ( sym_ref2 ) where they are in the same section .


"\033[41;30m Unrecognized *virtual* insn \033[0m\n"

Rescans an insn to see if it 's recognized again . This is done carefully to ensure that all the constraint information is accurate for the newly matched insn .


<s> virtual const LEGSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> void Mips16FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( STI . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: Move32R16 ) , Mips :: SP ) . addReg ( Mips :: S0 ) ; TII . restoreFrame ( Mips :: SP , StackSize , MBB , MBBI ) ; } </s>

Mips Mips Mips Mips Mips::Move32R16 Mips::SP Mips::S0 Mips::SP


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesAll ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool m68k_legitimate_index_reg_p ( rtx x , bool strict_p ) { if ( ! strict_p && GET_CODE ( x ) == SUBREG ) x = SUBREG_REG ( x ) ; return ( REG_P ( x ) && ( strict_p ? REGNO_OK_FOR_INDEX_P ( REGNO ( x ) ) : REGNO_OK_FOR_INDEX_NONSTRICT_P ( REGNO ( x ) ) ) ) ; } </s>

Return true if X is a legitimate index register . STRICT_P says whether we need strict checking .


<s> static reg_class_t loongarch_secondary_reload ( bool in_p ATTRIBUTE_UNUSED , rtx x , reg_class_t rclass , machine_mode mode , secondary_reload_info * sri ATTRIBUTE_UNUSED ) { int regno ; regno = true_regnum ( x ) ; if ( reg_class_subset_p ( rclass , FP_REGS ) ) { if ( regno < 0 || ( MEM_P ( x ) && ( GET_MODE_SIZE ( mode ) == 4 || GET_MODE_SIZE ( mode ) == 8 ) ) ) return NO_REGS ; if ( GP_REG_P ( regno ) || x == CONST0_RTX ( mode ) ) return NO_REGS ; if ( CONSTANT_P ( x ) && ! targetm . cannot_force_const_mem ( mode , x ) ) return NO_REGS ; if ( FP_REG_P ( regno ) && loongarch_mode_ok_for_mov_fmt_p ( mode ) ) return NO_REGS ; return GR_REGS ; } if ( FP_REG_P ( regno ) ) return reg_class_subset_p ( rclass , GR_REGS ) ? NO_REGS : GR_REGS ; return NO_REGS ; } </s>

Return the register class required for a secondary register when copying between one of the registers in RCLASS and value X , which has mode MODE . X is the source of the move if IN_P , otherwise it is the destination . Return NO_REGS if no secondary register is needed .


<s> static void do_load_for_compare ( rtx reg , rtx mem , machine_mode mode ) { switch ( GET_MODE ( reg ) ) { case E_DImode : switch ( mode ) { case E_QImode : emit_insn ( gen_zero_extendqidi2 ( reg , mem ) ) ; break ; case E_HImode : { rtx src = mem ; if ( ! BYTES_BIG_ENDIAN ) { src = gen_reg_rtx ( HImode ) ; emit_insn ( gen_bswaphi2 ( src , mem ) ) ; } emit_insn ( gen_zero_extendhidi2 ( reg , src ) ) ; break ; } case E_SImode : { rtx src = mem ; if ( ! BYTES_BIG_ENDIAN ) { src = gen_reg_rtx ( SImode ) ; emit_insn ( gen_bswapsi2 ( src , mem ) ) ; } emit_insn ( gen_zero_extendsidi2 ( reg , src ) ) ; } break ; case E_DImode : if ( ! BYTES_BIG_ENDIAN ) emit_insn ( gen_bswapdi2 ( reg , mem ) ) ; else emit_insn ( gen_movdi ( reg , mem ) ) ; break ; default : gcc_unreachable ( ) ; } break ; case E_SImode : switch ( mode ) { case E_QImode : emit_insn ( gen_zero_extendqisi2 ( reg , mem ) ) ; break ; case E_HImode : { rtx src = mem ; if ( ! BYTES_BIG_ENDIAN ) { src = gen_reg_rtx ( HImode ) ; emit_insn ( gen_bswaphi2 ( src , mem ) ) ; } emit_insn ( gen_zero_extendhisi2 ( reg , src ) ) ; break ; } case E_SImode : if ( ! BYTES_BIG_ENDIAN ) emit_insn ( gen_bswapsi2 ( reg , mem ) ) ; else emit_insn ( gen_movsi ( reg , mem ) ) ; break ; case E_DImode : gcc_unreachable ( ) ; break ; default : gcc_unreachable ( ) ; } break ; default : gcc_unreachable ( ) ; break ; } } </s>

Figure out the correct instructions to generate to load data for block compare . MODE is used for the read from memory , and data is zero extended if REG is wider than MODE . If LE code is being generated , bswap loads are used . REG is the destination register to move the data into . MEM is the memory block being read . MODE is the mode of memory to use for the read .


<s>
bool
AMDGPULegalizerInfo
::
legalizeCustom
(
MachineInstr
&
MI
,
MachineRegisterInfo
&
MRI
,
MachineIRBuilder
&
B
,
GISelChangeObserver
&
Observer
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
case
TargetOpcode
::
G_ADDRSPACE_CAST
:
return
legalizeAddrSpaceCast
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FRINT
:
return
legalizeFrint
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FCEIL
:
return
legalizeFceil
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_INTRINSIC_TRUNC
:
return
legalizeIntrinsicTrunc
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_SITOFP
:
return
legalizeITOFP
(
MI
,
MRI
,
B
,
true
)
;
case
TargetOpcode
::
G_UITOFP
:
return
legalizeITOFP
(
MI
,
MRI
,
B
,
false
)
;
case
TargetOpcode
::
G_FMINNUM
:
case
TargetOpcode
::
G_FMAXNUM
:
case
TargetOpcode
::
G_FMINNUM_IEEE
:
case
TargetOpcode
::
G_FMAXNUM_IEEE
:
return
legalizeMinNumMaxNum
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_EXTRACT_VECTOR_ELT
:
return
legalizeExtractVectorElt
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_INSERT_VECTOR_ELT
:
return
legalizeInsertVectorElt
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FSIN
:
case
TargetOpcode
::
G_FCOS
:
return
legalizeSinCos
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_GLOBAL_VALUE
:
return
legalizeGlobalValue
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_LOAD
:
return
legalizeLoad
(
MI
,
MRI
,
B
,
Observer
)
;
case
TargetOpcode
::
G_FMAD
:
return
legalizeFMad
(
MI
,
MRI
,
B
)
;
default
:
return
false
;
}
llvm_unreachable
(
"expected switch to return"
)
;
}
</s>

Called for instructions with the Custom LegalizationAction .

AMDGPU
AMDGPU
SI
SI
SI
"expected switch to return"


<s> int get_dest_uid ( rtx_insn * label , int max_uid ) { rtx_insn * dest = next_real_insn ( label ) ; if ( ! dest ) return 0 ; int dest_uid = INSN_UID ( dest ) ; while ( dest_uid >= max_uid ) { dest = NEXT_INSN ( dest ) ; dest_uid = INSN_UID ( dest ) ; } if ( JUMP_P ( dest ) && GET_CODE ( PATTERN ( dest ) ) == RETURN ) return 0 ; return dest_uid ; } </s>

Return the UID of the insn that follows the specified label .


<s> static void mips_extra_live_on_entry ( bitmap regs ) { if ( TARGET_USE_GOT ) { if ( ! TARGET_ABSOLUTE_ABICALLS ) bitmap_set_bit ( regs , PIC_FUNCTION_ADDR_REGNUM ) ; if ( TARGET_MIPS16 ) bitmap_set_bit ( regs , MIPS16_PIC_TEMP_REGNUM ) ; bitmap_set_bit ( regs , GOT_VERSION_REGNUM ) ; } } </s>


runOnMachineFunction - Emit the function body .


<s> virtual llvm :: StringRef getPassName ( ) const { return "localaccessortosharedmemory" ; } </s>

getPassName - Return a nice clean name for a pass .


<s>
virtual
void
print
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
k_Token
:
OS
<<
"Token: "
<<
getToken
(
)
<<
"\n"
;
break
;
case
k_Register
:
OS
<<
"Reg: #"
<<
getReg
(
)
<<
"\n"
;
break
;
case
k_Immediate
:
OS
<<
"Imm: "
<<
getImm
(
)
<<
"\n"
;
break
;
case
k_MemoryReg
:
OS
<<
"Mem: "
<<
getMemBase
(
)
<<
"+"
<<
getMemOffsetReg
(
)
<<
"\n"
;
break
;
case
k_MemoryImm
:
assert
(
getMemOff
(
)
!=
0
)
;
OS
<<
"Mem: "
<<
getMemBase
(
)
<<
"+"
<<
*
getMemOff
(
)
<<
"\n"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> int c4x_T_constraint ( rtx op ) { if ( GET_CODE ( op ) != MEM ) return 0 ; op = XEXP ( op , 0 ) ; if ( GET_CODE ( op ) != LO_SUM ) { return GET_CODE ( op ) == SYMBOL_REF && GET_MODE ( op ) == Pmode && SYMBOL_REF_FUNCTION_P ( op ) ; } if ( GET_MODE ( op ) == HImode || GET_CODE ( op ) == HFmode ) return 0 ; if ( ( GET_CODE ( XEXP ( op , 0 ) ) == REG ) && ( REGNO ( XEXP ( op , 0 ) ) == DP_REGNO ) ) return c4x_U_constraint ( XEXP ( op , 1 ) ) ; return 0 ; } </s>


<s> bool mep_mul_hilo_bypass_p ( rtx_insn * prev , rtx_insn * insn ) { rtx pat ; pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , 0 , 0 ) ; if ( GET_CODE ( pat ) != SET ) return false ; subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , SET_SRC ( pat ) , NONCONST ) { const_rtx x = * iter ; if ( REG_P ( x ) && REGNO ( x ) != LO_REGNO && REGNO ( x ) != HI_REGNO && reg_set_p ( x , prev ) ) return false ; } return true ; } </s>

Return true if , apart from HI/LO , there are no true dependencies between multiplication instructions PREV and INSN .


<s> static void mips_start_unique_function ( const char * name ) { tree decl ; decl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , build_function_type_list ( void_type_node , NULL_TREE ) ) ; DECL_RESULT ( decl ) = build_decl ( BUILTINS_LOCATION , RESULT_DECL , NULL_TREE , void_type_node ) ; TREE_PUBLIC ( decl ) = 1 ; TREE_STATIC ( decl ) = 1 ; cgraph_node :: create ( decl ) -> set_comdat_group ( DECL_ASSEMBLER_NAME ( decl ) ) ; targetm . asm_out . unique_section ( decl , 0 ) ; switch_to_section ( get_named_section ( decl , NULL , 0 ) ) ; targetm . asm_out . globalize_label ( asm_out_file , name ) ; fputs ( "\t.hidden\t" , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; putc ( '\n' , asm_out_file ) ; } </s>

Declare a unique , locally-binding function called NAME , then start its definition .


<s> void BPFFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


<s> void constant_to_array ( machine_mode mode , rtx x , unsigned char arr [ 16 ] ) { HOST_WIDE_INT val ; int i , j , first ; memset ( arr , 0 , 16 ) ; mode = GET_MODE ( x ) != VOIDmode ? GET_MODE ( x ) : mode ; if ( GET_CODE ( x ) == CONST_INT || ( GET_CODE ( x ) == CONST_DOUBLE && ( mode == SFmode || mode == DFmode ) ) ) { gcc_assert ( mode != VOIDmode && mode != BLKmode ) ; if ( GET_CODE ( x ) == CONST_DOUBLE ) val = const_double_to_hwint ( x ) ; else val = INTVAL ( x ) ; first = GET_MODE_SIZE ( mode ) - 1 ; for ( i = first ; i >= 0 ; i -- ) { arr [ i ] = val & 0xff ; val >>= 8 ; } for ( j = 0 , i = first + 1 ; i < 16 ; i ++ ) { arr [ i ] = arr [ j ] ; j = ( j == first ) ? 0 : j + 1 ; } } else if ( GET_CODE ( x ) == CONST_DOUBLE ) { val = CONST_DOUBLE_LOW ( x ) ; for ( i = 15 ; i >= 8 ; i -- ) { arr [ i ] = val & 0xff ; val >>= 8 ; } val = CONST_DOUBLE_HIGH ( x ) ; for ( i = 7 ; i >= 0 ; i -- ) { arr [ i ] = val & 0xff ; val >>= 8 ; } } else if ( GET_CODE ( x ) == CONST_VECTOR ) { int units ; rtx elt ; mode = GET_MODE_INNER ( mode ) ; units = CONST_VECTOR_NUNITS ( x ) ; for ( i = 0 ; i < units ; i ++ ) { elt = CONST_VECTOR_ELT ( x , i ) ; if ( GET_CODE ( elt ) == CONST_INT || GET_CODE ( elt ) == CONST_DOUBLE ) { if ( GET_CODE ( elt ) == CONST_DOUBLE ) val = const_double_to_hwint ( elt ) ; else val = INTVAL ( elt ) ; first = GET_MODE_SIZE ( mode ) - 1 ; if ( first + i * GET_MODE_SIZE ( mode ) > 16 ) abort ( ) ; for ( j = first ; j >= 0 ; j -- ) { arr [ j + i * GET_MODE_SIZE ( mode ) ] = val & 0xff ; val >>= 8 ; } } } } else gcc_unreachable ( ) ; } </s>

Convert a CONST_INT , CONST_DOUBLE , or CONST_VECTOR into a 16 byte array . Use MODE for CONST_INT 's . When the constant 's mode is smaller than 16 bytes , the value is repeated across the rest of the array .


<s> static void rs6000_output_dwarf_dtprel ( FILE * file , int size , rtx x ) { switch ( size ) { case 4 : fputs ( "\t.long\t" , file ) ; break ; case 8 : fputs ( DOUBLE_INT_ASM_OP , file ) ; break ; default : gcc_unreachable ( ) ; } output_addr_const ( file , x ) ; if ( TARGET_ELF ) fputs ( "@dtprel+0x8000" , file ) ; else if ( TARGET_XCOFF && GET_CODE ( x ) == SYMBOL_REF ) { switch ( SYMBOL_REF_TLS_MODEL ( x ) ) { case 0 : break ; case TLS_MODEL_LOCAL_EXEC : fputs ( "@le" , file ) ; break ; case TLS_MODEL_INITIAL_EXEC : fputs ( "@ie" , file ) ; break ; case TLS_MODEL_GLOBAL_DYNAMIC : case TLS_MODEL_LOCAL_DYNAMIC : fputs ( "@m" , file ) ; break ; default : gcc_unreachable ( ) ; } } } </s>

This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL . We need to emit DTP-relative relocations .


<s> static rtx get_vl_x2_rtx ( rtx avl , machine_mode mode , machine_mode demote_mode ) { rtx i32vl = NULL_RTX ; if ( CONST_INT_P ( avl ) ) { unsigned elt_size = GET_MODE_BITSIZE ( GET_MODE_INNER ( mode ) ) ; unsigned min_size = get_unknown_min_value ( mode ) ; unsigned vlen_max = RVV_65536 ; unsigned vlmax_max = compute_vlmax ( vlen_max , elt_size , min_size ) ; unsigned vlen_min = TARGET_MIN_VLEN ; unsigned vlmax_min = compute_vlmax ( vlen_min , elt_size , min_size ) ; unsigned HOST_WIDE_INT avl_int = INTVAL ( avl ) ; if ( avl_int <= vlmax_min ) i32vl = gen_int_mode ( 2 * avl_int , Pmode ) ; else if ( avl_int >= 2 * vlmax_max ) { i32vl = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_no_side_effects_vsetvl_rtx ( demote_mode , i32vl , RVV_VLMAX ) ) ; } else { } } if ( ! i32vl ) { rtx i64vl = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_no_side_effects_vsetvl_rtx ( mode , i64vl , force_reg ( Pmode , avl ) ) ) ; i32vl = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( i32vl , gen_rtx_ASHIFT ( Pmode , i64vl , const1_rtx ) ) ) ; } return force_vector_length_operand ( i32vl ) ; } </s>


<s> bool doInitialization ( Module & Mod ) override { M = & Mod ; TD = std :: make_unique < DataLayout > ( M ) ; SizeTy = IntegerType :: get ( M -> getContext ( ) , TD -> getIndexSizeInBits ( 200 ) ) ; CapPtrTy = PointerType :: get ( IntegerType :: get ( M -> getContext ( ) , 8 ) , 200 ) ; return true ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> void gen_shifty_op ( int code , rtx * operands ) { int value = INTVAL ( operands [ 2 ] ) ; int max , i ; value = value & 31 ; if ( value == 31 ) { if ( code == LSHIFTRT ) { emit_insn ( gen_rotlsi3_1 ( operands [ 0 ] , operands [ 0 ] ) ) ; emit_insn ( gen_movt ( operands [ 0 ] , get_t_reg_rtx ( ) ) ) ; return ; } else if ( code == ASHIFT ) { if ( REG_P ( operands [ 0 ] ) && REGNO ( operands [ 0 ] ) == 0 ) { emit_insn ( gen_andsi3 ( operands [ 0 ] , operands [ 0 ] , const1_rtx ) ) ; emit_insn ( gen_rotlsi3_31 ( operands [ 0 ] , operands [ 0 ] ) ) ; return ; } } } else if ( value == 0 ) { emit_insn ( gen_rtx_SET ( operands [ 0 ] , operands [ 0 ] ) ) ; return ; } max = ashl_lshr_seq [ value ] . insn_count ; for ( i = 0 ; i < max ; i ++ ) gen_ashift ( code , ashl_lshr_seq [ value ] . amount [ i ] , operands [ 0 ] ) ; } </s>

Output RTL to split a constant shift into its component SH constant shift instructions .


<s> static int c6x_adjust_cost ( rtx_insn * insn , int dep_type , rtx_insn * dep_insn , int cost , unsigned int ) { enum attr_type insn_type = TYPE_UNKNOWN , dep_insn_type = TYPE_UNKNOWN ; int dep_insn_code_number , insn_code_number ; int shadow_bonus = 0 ; enum reg_note kind ; dep_insn_code_number = recog_memoized ( dep_insn ) ; insn_code_number = recog_memoized ( insn ) ; if ( dep_insn_code_number >= 0 ) dep_insn_type = get_attr_type ( dep_insn ) ; if ( insn_code_number >= 0 ) insn_type = get_attr_type ( insn ) ; kind = ( reg_note ) dep_type ; if ( kind == 0 ) { if ( dep_insn_type == TYPE_LOAD ) { rtx set = PATTERN ( dep_insn ) ; if ( GET_CODE ( set ) == COND_EXEC ) set = COND_EXEC_CODE ( set ) ; if ( GET_CODE ( set ) == UNSPEC ) cost = 1 ; else { gcc_assert ( GET_CODE ( set ) == SET ) ; if ( ! reg_overlap_mentioned_p ( SET_DEST ( set ) , PATTERN ( insn ) ) ) cost = 1 ; } } } if ( shadow_type_p ( insn_type ) ) shadow_bonus = 1 ; if ( kind != 0 ) { if ( kind == REG_DEP_ANTI && insn_type == TYPE_SHADOW ) kind = REG_DEP_OUTPUT ; switch ( dep_insn_type ) { case TYPE_CALLP : return 1 ; case TYPE_BRANCH : case TYPE_CALL : if ( get_attr_has_shadow ( dep_insn ) == HAS_SHADOW_Y ) return 0 ; return 6 ; case TYPE_LOAD : case TYPE_LOADN : case TYPE_INTDP : if ( kind == REG_DEP_OUTPUT ) return 5 - shadow_bonus ; return 0 ; case TYPE_MPY4 : case TYPE_FP4 : if ( kind == REG_DEP_OUTPUT ) return 4 - shadow_bonus ; return 0 ; case TYPE_MPY2 : if ( kind == REG_DEP_OUTPUT ) return 2 - shadow_bonus ; return 0 ; case TYPE_CMPDP : if ( kind == REG_DEP_OUTPUT ) return 2 - shadow_bonus ; return 2 ; case TYPE_ADDDP : case TYPE_MPYSPDP : if ( kind == REG_DEP_OUTPUT ) return 7 - shadow_bonus ; return 2 ; case TYPE_MPYSP2DP : if ( kind == REG_DEP_OUTPUT ) return 5 - shadow_bonus ; return 2 ; case TYPE_MPYI : if ( kind == REG_DEP_OUTPUT ) return 9 - shadow_bonus ; return 4 ; case TYPE_MPYID : case TYPE_MPYDP : if ( kind == REG_DEP_OUTPUT ) return 10 - shadow_bonus ; return 4 ; default : if ( insn_type == TYPE_SPKERNEL ) return 0 ; if ( kind == REG_DEP_OUTPUT ) return 1 - shadow_bonus ; return 0 ; } } return cost - shadow_bonus ; } </s>

Implement the TARGET_SCHED_ADJUST_COST hook . We need special handling for anti- and output dependencies .


<s> bool lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) const { return LowerZ80MachineOperandToMCOperand ( MO , MCOp , * this ) ; } </s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> void v850_output_aligned_bss ( FILE * file , tree decl , const char * name , unsigned HOST_WIDE_INT size , int align ) { switch ( v850_get_data_area ( decl ) ) { case DATA_AREA_ZDA : switch_to_section ( zbss_section ) ; break ; case DATA_AREA_SDA : switch_to_section ( sbss_section ) ; break ; case DATA_AREA_TDA : switch_to_section ( tdata_section ) ; break ; default : switch_to_section ( bss_section ) ; break ; } ASM_OUTPUT_ALIGN ( file , floor_log2 ( align / BITS_PER_UNIT ) ) ; last_assemble_variable_decl = decl ; ASM_DECLARE_OBJECT_NAME ( file , name , decl ) ; ASM_OUTPUT_LABEL ( file , name ) ; ASM_OUTPUT_SKIP ( file , size ? size : 1 ) ; } </s>

A version of asm_output_aligned_bss ( ) that copes with the special data areas of the v850 .


"Only optimizing constant comparisons so far"

optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare ; remove Compare if possible .


<s> bool swiftAsyncContextIsDynamicallySet ( ) const { const Triple & TT = getTargetTriple ( ) ; unsigned Major = TT . getOSVersion ( ) . getMajor ( ) ; switch ( TT . getOS ( ) ) { default : return false ; case Triple :: IOS : case Triple :: TvOS : return Major < 15 ; case Triple :: WatchOS : return Major < 8 ; case Triple :: MacOSX : case Triple :: Darwin : return Major < 12 ; } } </s>

Return whether FrameLowering should always set the `` extended frame present '' bit in FP , or set it based on a symbol in the runtime .


"Module has aliases, which NVPTX does not support."

"Module has a nontrivial global ctor, which NVPTX does not support."

"Module has a nontrivial global dtor, which NVPTX does not support."


<s> void WebAssemblyDebugValueManager :: clone ( MachineInstr * Insert , unsigned NewReg ) { MachineBasicBlock * MBB = Insert -> getParent ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; for ( MachineInstr * DBI : reverse ( DbgValues ) ) { MachineInstr * Clone = MF -> CloneMachineInstr ( DBI ) ; Clone -> getOperand ( 0 ) . setReg ( NewReg ) ; MBB -> insert ( Insert , Clone ) ; } } </s>

Make a functionally equivalent copy of this MachineFunctionInfo in MF .


<s> static tree def_builtin_const ( const char * name , enum insn_code icode , enum sparc_builtins code , tree type ) { tree t = def_builtin ( name , icode , code , type ) ; if ( t ) TREE_READONLY ( t ) = 1 ; return t ; } </s>

Likewise , but also marks the function as `` const '' .


<s> bool PPCDarwinAsmPrinter :: doFinalization ( Module & M ) { bool isPPC64 = TM . getTargetData ( ) -> getPointerSizeInBits ( ) == 64 ; const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetFnStubList ( ) ; if ( ! Stubs . empty ( ) ) EmitFunctionStubs ( Stubs ) ; if ( MAI -> doesSupportExceptionHandling ( ) && MMI ) { const std :: vector < const Function * > & Personalities = MMI -> getPersonalities ( ) ; for ( std :: vector < const Function * > :: const_iterator I = Personalities . begin ( ) , E = Personalities . end ( ) ; I != E ; ++ I ) { if ( * I ) { MCSymbol * NLPSym = GetSymbolWithGlobalValueBase ( * I , "$non_lazy_ptr" ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMIMacho . getGVStubEntry ( NLPSym ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( * I ) , true ) ; } } } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue ( 0 , isPPC64 ? 8 : 4 , 0 ) ; else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 , 0 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 , 0 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s>
void
RISCVMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
unsigned
Size
=
Desc
.
getSize
(
)
;
if
(
MI
.
getOpcode
(
)
==
RISCV
::
PseudoCALL
||
MI
.
getOpcode
(
)
==
RISCV
::
PseudoTAIL
)
{
expandFunctionCall
(
MI
,
OS
,
Fixups
,
STI
)
;
MCNumEmitted
+=
2
;
return
;
}
switch
(
Size
)
{
default
:
llvm_unreachable
(
"Unhandled encodeInstruction length!"
)
;
case
2
:
{
uint16_t
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
support
::
endian
::
write
<
uint16_t
>
(
OS
,
Bits
,
support
::
little
)
;
break
;
}
case
4
:
{
uint32_t
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
support
::
endian
::
write
(
OS
,
Bits
,
support
::
little
)
;
break
;
}
}
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .

RISCV
RISCV
RISCV::PseudoCALL
RISCV::PseudoTAIL
2
"Unhandled encodeInstruction length!"
2
support::endian
support::little
4
support::endian
support::little


<s> void DCPU16RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( ! TFI -> hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; uint64_t Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = 0 ; if ( Old -> getOpcode ( ) == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( DCPU16 :: SUB16ri ) , DCPU16 :: SP ) . addReg ( DCPU16 :: SP ) . addImm ( Amount ) ; } else { assert ( Old -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) ; uint64_t CalleeAmt = Old -> getOperand ( 1 ) . getImm ( ) ; Amount -= CalleeAmt ; if ( Amount ) New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( DCPU16 :: ADD16ri ) , DCPU16 :: SP ) . addReg ( DCPU16 :: SP ) . addImm ( Amount ) ; } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { MachineInstr * Old = I ; MachineInstr * New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( DCPU16 :: SUB16ri ) , DCPU16 :: SP ) . addReg ( DCPU16 :: SP ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> unsigned HSAILInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { const MCInstrDesc & MCID = get ( MI -> getOpcode ( ) ) ; if ( ! MCID . mayStore ( ) || ! MI -> hasOneMemOperand ( ) ) return 0 ; const MachineOperand * Segment = getNamedOperand ( * MI , HSAIL :: OpName :: segment ) ; if ( ! Segment || Segment -> getImm ( ) != HSAILAS :: SPILL_ADDRESS ) return HSAIL :: NoRegister ; int AddressIdx = HSAIL :: getNamedOperandIdx ( MI -> getOpcode ( ) , HSAIL :: OpName :: address ) ; const MachineOperand & Base = MI -> getOperand ( AddressIdx + HSAILADDRESS :: BASE ) ; if ( Base . isFI ( ) ) { FrameIndex = Base . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } return HSAIL :: NoRegister ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .

HSAIL HSAIL 0 HSAIL::OpName HSAILAS::SPILL_ADDRESS HSAIL::NoRegister HSAIL::getNamedOperandIdx HSAIL::OpName HSAILADDRESS::BASE 0 HSAIL::NoRegister


<s> void GCNPassConfig :: addPreRegAlloc ( ) { const AMDGPUSubtarget & ST = * getAMDGPUTargetMachine ( ) . getSubtargetImpl ( ) ; if ( getOptLevel ( ) > CodeGenOpt :: None && ST . loadStoreOptEnabled ( ) ) { initializeSILoadStoreOptimizerPass ( * PassRegistry :: getPassRegistry ( ) ) ; insertPass ( & MachineSchedulerID , & SILoadStoreOptimizerID ) ; } addPass ( createSIShrinkInstructionsPass ( ) , false ) ; addPass ( createSIFixSGPRLiveRangesPass ( ) , false ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> int sparc_check_64 ( rtx x , rtx insn ) { int set_once = 0 ; rtx y = x ; gcc_assert ( GET_CODE ( x ) == REG ) ; if ( GET_MODE ( x ) == DImode ) y = gen_rtx_REG ( SImode , REGNO ( x ) + WORDS_BIG_ENDIAN ) ; if ( flag_expensive_optimizations && REG_N_SETS ( REGNO ( y ) ) == 1 ) set_once = 1 ; if ( insn == 0 ) { if ( set_once ) insn = get_last_insn_anywhere ( ) ; else return 0 ; } while ( ( insn = PREV_INSN ( insn ) ) ) { switch ( GET_CODE ( insn ) ) { case JUMP_INSN : case NOTE : break ; case CODE_LABEL : case CALL_INSN : default : if ( ! set_once ) return 0 ; break ; case INSN : { rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) != SET ) return 0 ; if ( rtx_equal_p ( x , SET_DEST ( pat ) ) ) return set_extends ( insn ) ; if ( y && rtx_equal_p ( y , SET_DEST ( pat ) ) ) return set_extends ( insn ) ; if ( reg_overlap_mentioned_p ( SET_DEST ( pat ) , y ) ) return 0 ; } } } return 0 ; } </s>

Return 0 if the high 32 bits of X ( the low word of X , if DImode ) are unknown . Return 1 if the high bits are zero , -1 if the register is sign extended .


<s> const uint32_t * VERegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { switch ( CC ) { case CallingConv :: Fast : default : return CSR_RegMask ; case CallingConv :: PreserveAll : return CSR_preserve_all_RegMask ; } } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool HexagonFrameLowering :: hasFP ( const MachineFunction & MF ) const { auto & MFI = * MF . getFrameInfo ( ) ; auto & HRI = * MF . getSubtarget < HexagonSubtarget > ( ) . getRegisterInfo ( ) ; bool HasFixed = MFI . getNumFixedObjects ( ) ; bool HasPrealloc = const_cast < MachineFrameInfo & > ( MFI ) . getLocalFrameObjectCount ( ) ; bool HasExtraAlign = HRI . needsStackRealignment ( MF ) ; bool HasAlloca = MFI . hasVarSizedObjects ( ) ; if ( MF . getTarget ( ) . getOptLevel ( ) == CodeGenOpt :: None ) return true ; if ( ( HasFixed || HasPrealloc ) && ( HasAlloca || HasExtraAlign ) ) return true ; if ( MFI . getStackSize ( ) > 0 ) { if ( UseAllocframe ) return true ; } if ( MFI . hasCalls ( ) || MF . getInfo < HexagonMachineFunctionInfo > ( ) -> hasClobberLR ( ) ) return true ; return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void LoongArchAsmPrinter :: emitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; MCInst TmpInst ; if ( ! lowerLoongArchMachineInstrToMCInst ( MI , TmpInst , * this ) ) EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

Targets should implement this to emit instructions .


"Unconditional branch with multiple successors!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> const RegisterBank & AMDGPURegisterBankInfo :: getRegBankFromRegClass ( const TargetRegisterClass & RC ) const { if ( TRI -> isSGPRClass ( & RC ) ) return getRegBank ( AMDGPU :: SGPRRegBankID ) ; return getRegBank ( AMDGPU :: VGPRRegBankID ) ; } </s>

AMDGPU AMDGPU AMDGPU::SGPRRegBankID AMDGPU::VGPRRegBankID


<s> bool arc_profile_call ( rtx callee ) { rtx from = XEXP ( DECL_RTL ( current_function_decl ) , 0 ) ; if ( TARGET_UCB_MCOUNT ) return false ; if ( CONSTANT_P ( callee ) ) { rtx count_ptr = gen_rtx_CONST ( Pmode , gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 3 , from , callee , CONST0_RTX ( Pmode ) ) , UNSPEC_PROF ) ) ; rtx counter = gen_rtx_MEM ( SImode , count_ptr ) ; emit_move_insn ( counter , force_reg ( SImode , plus_constant ( SImode , counter , 1 ) ) ) ; return false ; } else { rtx count_list_ptr = gen_rtx_CONST ( Pmode , gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 3 , from , CONST0_RTX ( Pmode ) , CONST0_RTX ( Pmode ) ) , UNSPEC_PROF ) ) ; emit_move_insn ( gen_rtx_REG ( Pmode , 8 ) , count_list_ptr ) ; emit_move_insn ( gen_rtx_REG ( Pmode , 9 ) , callee ) ; return true ; } } </s>

Emit profiling code for calling CALLEE . Return true if a special call pattern needs to be generated .


"NVPTX DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> int arm_eliminable_register ( rtx x ) { return REG_P ( x ) && ( REGNO ( x ) == FRAME_POINTER_REGNUM || REGNO ( x ) == ARG_POINTER_REGNUM || ( REGNO ( x ) >= FIRST_VIRTUAL_REGISTER && REGNO ( x ) <= LAST_VIRTUAL_REGISTER ) ) ; } </s>

Return true if X is a register that will be eliminated later on .


<s>
unsigned
getReg
(
)
const
{
assert
(
isReg
(
)
&&
"Wrong CountValue accessor"
)
;
return
Contents
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s> bool ARMAsmBackend :: mayNeedRelaxation ( const MCInst & Inst ) const { if ( getRelaxedOpcode ( Inst . getOpcode ( ) ) != Inst . getOpcode ( ) ) return true ; return false ; } </s>

Check whether the given instruction may need relaxation .


"function_adv({gp reg found = %d, arg # = %2d, words = %2d}, %4s, "

Advance the argument of type TYPE and mode MODE to the next argument position in CUM .


<s> void AMDGPUPassConfig :: addIRPasses ( ) { addPass ( createAMDGPUAlwaysInlinePass ( ) ) ; addPass ( createAlwaysInlinerPass ( ) ) ; addPass ( createBarrierNoopPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> void altivec_expand_vec_perm_le ( rtx operands [ 4 ] ) { rtx notx , iorx , unspec ; rtx target = operands [ 0 ] ; rtx op0 = operands [ 1 ] ; rtx op1 = operands [ 2 ] ; rtx sel = operands [ 3 ] ; rtx tmp = target ; rtx norreg = gen_reg_rtx ( V16QImode ) ; machine_mode mode = GET_MODE ( target ) ; if ( ! REG_P ( op0 ) ) op0 = force_reg ( mode , op0 ) ; if ( ! REG_P ( op1 ) ) op1 = force_reg ( mode , op1 ) ; if ( ! REG_P ( sel ) ) sel = force_reg ( V16QImode , sel ) ; if ( ! REG_P ( target ) ) tmp = gen_reg_rtx ( mode ) ; notx = gen_rtx_NOT ( V16QImode , sel ) ; iorx = ( TARGET_P8_VECTOR ? gen_rtx_IOR ( V16QImode , notx , notx ) : gen_rtx_AND ( V16QImode , notx , notx ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , norreg , iorx ) ) ; unspec = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , op1 , op0 , norreg ) , UNSPEC_VPERM ) ; if ( ! REG_P ( target ) ) { emit_move_insn ( tmp , unspec ) ; unspec = tmp ; } emit_move_insn ( target , unspec ) ; } </s>

Similarly to altivec_expand_vec_perm_const_le , we must adjust the permute control vector . But here it 's not a constant , so we must generate a vector NAND or NOR to do the adjustment .


<s> bool isCheapToSpeculateCtlz ( ) const override { return true ; } </s>

Return true if it is cheap to speculate a call to intrinsic ctlz .


<s>
void
TPCRegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
MachineInstr
&
MI
=
*
II
;
const
TargetRegisterClass
*
RC
=
nullptr
;
bool
IsSpill
=
false
;
bool
IsFill
=
false
;
switch
(
MI
.
getOpcode
(
)
)
{
case
TPC
::
SPILL_ARF_RESTORE
:
RC
=
&
TPC
::
ARFRegClass
;
IsFill
=
true
;
break
;
case
TPC
::
SPILL_DRF_RESTORE
:
RC
=
&
TPC
::
DRFRegClass
;
IsFill
=
true
;
break
;
case
TPC
::
SPILL_ZRF_RESTORE
:
RC
=
&
TPC
::
ZRFRegClass
;
IsFill
=
true
;
break
;
case
TPC
::
SPILL_VRF_RESTORE
:
RC
=
&
TPC
::
VRFRegClass
;
IsFill
=
true
;
break
;
case
TPC
::
SPILL_VPRF_RESTORE
:
RC
=
&
TPC
::
VPRFRegClass
;
IsFill
=
true
;
break
;
case
TPC
::
SPILL_IRF_RESTORE
:
RC
=
&
TPC
::
IRFRegClass
;
IsFill
=
true
;
break
;
case
TPC
::
SPILL_SRF_RESTORE
:
RC
=
&
TPC
::
SRFRegClass
;
IsFill
=
true
;
break
;
case
TPC
::
SPILL_SPRF_RESTORE
:
RC
=
&
TPC
::
SPRFRegClass
;
IsFill
=
true
;
break
;
case
TPC
::
SPILL_ARF_SAVE
:
RC
=
&
TPC
::
ARFRegClass
;
IsSpill
=
true
;
break
;
case
TPC
::
SPILL_DRF_SAVE
:
RC
=
&
TPC
::
DRFRegClass
;
IsSpill
=
true
;
break
;
case
TPC
::
SPILL_ZRF_SAVE
:
RC
=
&
TPC
::
ZRFRegClass
;
IsSpill
=
true
;
break
;
case
TPC
::
SPILL_VRF_SAVE
:
RC
=
&
TPC
::
VRFRegClass
;
IsSpill
=
true
;
break
;
case
TPC
::
SPILL_VPRF_SAVE
:
RC
=
&
TPC
::
VPRFRegClass
;
IsSpill
=
true
;
break
;
case
TPC
::
SPILL_IRF_SAVE
:
RC
=
&
TPC
::
IRFRegClass
;
IsSpill
=
true
;
break
;
case
TPC
::
SPILL_SRF_SAVE
:
RC
=
&
TPC
::
SRFRegClass
;
IsSpill
=
true
;
break
;
case
TPC
::
SPILL_SPRF_SAVE
:
RC
=
&
TPC
::
SPRFRegClass
;
IsSpill
=
true
;
break
;
default
:
llvm_unreachable
(
"Unexpected frame index"
)
;
}
if
(
IsSpill
||
IsFill
)
{
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
TPCFrameLowering
&
FL
=
*
const_cast
<
TPCFrameLowering
*
>
(
MF
.
getSubtarget
<
TPCSubtarget
>
(
)
.
getFrameLowering
(
)
)
;
int
FI
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
unsigned
Offset
;
Offset
=
FL
.
getSpillObject
(
FI
,
RC
,
MF
,
MFI
.
getObjectSize
(
FI
)
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToImmediate
(
Offset
)
;
}
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static void rs6000_emit_stack_tie ( ) { rtx mem = gen_rtx_MEM ( BLKmode , gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ) ; set_mem_alias_set ( mem , rs6000_sr_alias_set ) ; emit_insn ( gen_stack_tie ( mem ) ) ; } </s>

This ties together stack memory ( MEM with an alias set of rs6000_sr_alias_set ) and the change to the stack pointer .


<s> void applyFixup ( const MCFixup & Fixup , MutableArrayRef < char > Data , uint64_t Value , bool IsPCRel , MCContext & Ctx ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { unsigned Idx = IsLittleEndian ? i : 3 - i ; Data [ Offset + Idx ] |= uint8_t ( ( Value >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool Z80AsmParser :: MatchAndEmitInstruction ( SMLoc IDLoc , unsigned & Opcode , OperandVector & Operands , MCStreamer & Out , uint64_t & ErrorInfo , bool MatchingInlineAsm ) { llvm_unreachable ( "Unimplemented" ) ; } </s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> unsigned TVMInstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return 0 ; if ( I -> getOpcode ( ) != TVM :: JMPX && I -> getOpcode ( ) != TVM :: IFELSE && I -> getOpcode ( ) != TVM :: IFJMP && I -> getOpcode ( ) != TVM :: IFNOTJMP ) return 0 ; if ( I -> getOpcode ( ) == TVM :: JMPX ) { if ( BytesRemoved ) * BytesRemoved = 8 ; I -> eraseFromParent ( ) ; return 1 ; } if ( I -> getOpcode ( ) == TVM :: IFELSE ) { if ( BytesRemoved ) * BytesRemoved = 8 ; I -> eraseFromParent ( ) ; return 1 ; } if ( I -> getOpcode ( ) == TVM :: IFJMP || I -> getOpcode ( ) == TVM :: IFNOTJMP ) { if ( BytesRemoved ) * BytesRemoved = 8 ; I -> eraseFromParent ( ) ; return 1 ; } return 0 ; } </s>

Remove the branching code at the end of the specific MBB .


<s> unsigned getWeight ( ) const { return ( Weight ) ; } </s>

Provide a weight to bias towards choosing this strategy for a mutation .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < EdgeBundles > ( ) ; AU . addPreservedID ( MachineLoopInfoID ) ; AU . addPreservedID ( MachineDominatorsID ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


"Pseudo instructions must not be bundled!"

Targets should implement this to emit instructions .


<s> static int mips_multipass_dfa_lookahead ( void ) { if ( TUNE_SB1 ) return 4 ; if ( TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A ) return 4 ; if ( TUNE_OCTEON ) return 2 ; if ( TUNE_P5600 ) return 4 ; return 0 ; } </s>


<s> static bool mcore_return_in_memory ( tree type , tree fntype ATTRIBUTE_UNUSED ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; return ( size == - 1 || size > 2 * UNITS_PER_WORD ) ; } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


"ARM64 pseudo instruction expansion pass"

getPassName - Return a nice clean name for a pass .


<s> static rtx arm_find_shift_sub_rtx ( rtx pattern ) { return arm_find_sub_rtx_with_code ( pattern , ASHIFT , true ) ; } </s>

Traverse PATTERN looking for any sub-rtx which looks like a shift .


<s> unsigned getNumFixupKinds ( ) const override { return AMDGPU :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> static tree gen_regparm_prefix ( tree decl , unsigned nregs ) { unsigned total = 0 ; const char * asmname = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; char * newsym ; tree formal_type = TYPE_ARG_TYPES ( TREE_TYPE ( decl ) ) ; if ( formal_type != NULL_TREE ) { if ( TREE_VALUE ( tree_last ( formal_type ) ) != void_type_node ) return NULL_TREE ; while ( TREE_VALUE ( formal_type ) != void_type_node && COMPLETE_TYPE_P ( TREE_VALUE ( formal_type ) ) ) { unsigned parm_size = TREE_INT_CST_LOW ( TYPE_SIZE ( TREE_VALUE ( formal_type ) ) ) ; parm_size = ( ( parm_size + PARM_BOUNDARY - 1 ) / PARM_BOUNDARY * PARM_BOUNDARY ) ; total += parm_size ; formal_type = TREE_CHAIN ( formal_type ) ; } } if ( nregs > total / BITS_PER_WORD ) nregs = total / BITS_PER_WORD ; gcc_assert ( nregs <= 9 ) ; newsym = alloca ( 3 + strlen ( asmname ) + 1 ) ; return get_identifier_with_length ( newsym , sprintf ( newsym , "_%u@%s" , nregs , asmname ) ) ; } </s>

Return string which is the former assembler name modified with an _n @ prefix where n represents the number of arguments passed in registers


<s>
unsigned
getReg
(
)
const
override
{
llvm_unreachable
(
"Assembly inspects a register operand"
)
;
return
0
;
}
</s>

Returns the register associated with this edge .

WebAssembly
"Assembly inspects a register operand"
0


<s> void reset ( ) { FnStartLocs = Locs ( ) ; CantUnwindLocs = Locs ( ) ; PersonalityLocs = Locs ( ) ; HandlerDataLocs = Locs ( ) ; PersonalityIndexLocs = Locs ( ) ; FPReg = ARM :: SP ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s> TargetPassConfig * MandarinTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new MandarinPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> SDValue DCPU16TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_DCPU16 ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s>
static
const
char
*
get_content_name
(
unsigned
char
index
,
machine_mode
mode
)
{
static
char
buffer
[
128
]
;
if
(
index
==
NOT_KNOWN
)
return
"Unknown"
;
if
(
index
>
31
)
sprintf
(
buffer
,
"stack slot %d"
,
index
32
)
;
else
if
(
mode
==
HImode
)
sprintf
(
buffer
,
"%s%s"
,
reg_names
[
index
+
1
]
,
reg_names
[
index
]
)
;
else
return
reg_names
[
index
]
;
return
buffer
;
}
</s>

Return a string describing content INDEX in mode MODE . WARNING : Can return a pointer to a static buffer .


<s> ScheduleHazardRecognizer :: HazardType GCNHazardRecognizer :: getHazardType ( SUnit * SU , int Stalls ) { MachineInstr * MI = SU -> getInstr ( ) ; auto HazardType = IsHazardRecognizerMode ? NoopHazard : Hazard ; if ( MI -> isBundle ( ) ) return NoHazard ; if ( SIInstrInfo :: isSMRD ( * MI ) && checkSMRDHazards ( MI ) > 0 ) return HazardType ; if ( ST . hasNSAtoVMEMBug ( ) && checkNSAtoVMEMHazard ( MI ) > 0 ) return HazardType ; if ( checkFPAtomicToDenormModeHazard ( MI ) > 0 ) return HazardType ; if ( ST . hasNoDataDepHazard ( ) ) return NoHazard ; if ( ( SIInstrInfo :: isVMEM ( * MI ) || SIInstrInfo :: isFLAT ( * MI ) ) && checkVMEMHazards ( MI ) > 0 ) return HazardType ; if ( SIInstrInfo :: isVALU ( * MI ) && checkVALUHazards ( MI ) > 0 ) return HazardType ; if ( SIInstrInfo :: isDPP ( * MI ) && checkDPPHazards ( MI ) > 0 ) return HazardType ; if ( isDivFMas ( MI -> getOpcode ( ) ) && checkDivFMasHazards ( MI ) > 0 ) return HazardType ; if ( isRWLane ( MI -> getOpcode ( ) ) && checkRWLaneHazards ( MI ) > 0 ) return HazardType ; if ( ( SIInstrInfo :: isVALU ( * MI ) || SIInstrInfo :: isVMEM ( * MI ) || SIInstrInfo :: isFLAT ( * MI ) || SIInstrInfo :: isDS ( * MI ) || SIInstrInfo :: isEXP ( * MI ) ) && checkMAIVALUHazards ( MI ) > 0 ) return HazardType ; if ( isSGetReg ( MI -> getOpcode ( ) ) && checkGetRegHazards ( MI ) > 0 ) return HazardType ; if ( isSSetReg ( MI -> getOpcode ( ) ) && checkSetRegHazards ( MI ) > 0 ) return HazardType ; if ( isRFE ( MI -> getOpcode ( ) ) && checkRFEHazards ( MI ) > 0 ) return HazardType ; if ( ST . hasReadM0MovRelInterpHazard ( ) && ( TII . isVINTRP ( * MI ) || isSMovRel ( MI -> getOpcode ( ) ) ) && checkReadM0Hazards ( MI ) > 0 ) return HazardType ; if ( ST . hasReadM0SendMsgHazard ( ) && isSendMsgTraceDataOrGDS ( TII , * MI ) && checkReadM0Hazards ( MI ) > 0 ) return HazardType ; if ( SIInstrInfo :: isMAI ( * MI ) && checkMAIHazards ( MI ) > 0 ) return HazardType ; if ( ( SIInstrInfo :: isVMEM ( * MI ) || SIInstrInfo :: isFLAT ( * MI ) || SIInstrInfo :: isDS ( * MI ) ) && checkMAILdStHazards ( MI ) > 0 ) return HazardType ; if ( MI -> isInlineAsm ( ) && checkInlineAsmHazards ( MI ) > 0 ) return HazardType ; return NoHazard ; } </s>

getHazardType - Return the hazard type of emitting this node .


<s> bool AArch64AsmParser :: parsePrimaryExpr ( const MCExpr * & Res , SMLoc & EndLoc ) { if ( ! parseAuthExpr ( Res , EndLoc ) ) return false ; return getParser ( ) . parsePrimaryExpr ( Res , EndLoc , nullptr ) ; } </s>


runOnMachineFunction - Emit the function body .


<s> static unsigned int cr16_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( regno >= CR16_FIRST_DWORD_REGISTER ) return CEIL ( GET_MODE_SIZE ( mode ) , CR16_UNITS_PER_DWORD ) ; return CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ; } </s>


<s> TargetLowering :: AtomicExpansionKind AArch64TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { if ( Subtarget -> hasLSE ( ) || Subtarget -> outlineAtomics ( ) ) return AtomicExpansionKind :: None ; if ( getTargetMachine ( ) . getOptLevel ( ) == CodeGenOpt :: None ) return AtomicExpansionKind :: None ; return AtomicExpansionKind :: LLSC ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> bool HexagonHardwareLoops :: isDead ( const MachineInstr * MI , SmallVectorImpl < MachineInstr * > & DeadPhis ) const { for ( const MachineOperand & MO : MI -> operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( MRI -> use_nodbg_empty ( Reg ) ) continue ; using use_nodbg_iterator = MachineRegisterInfo :: use_nodbg_iterator ; use_nodbg_iterator I = MRI -> use_nodbg_begin ( Reg ) ; use_nodbg_iterator End = MRI -> use_nodbg_end ( ) ; if ( std :: next ( I ) != End || ! I -> getParent ( ) -> isPHI ( ) ) return false ; MachineInstr * OnePhi = I -> getParent ( ) ; for ( unsigned j = 0 , f = OnePhi -> getNumOperands ( ) ; j != f ; ++ j ) { const MachineOperand & OPO = OnePhi -> getOperand ( j ) ; if ( ! OPO . isReg ( ) || ! OPO . isDef ( ) ) continue ; Register OPReg = OPO . getReg ( ) ; use_nodbg_iterator nextJ ; for ( use_nodbg_iterator J = MRI -> use_nodbg_begin ( OPReg ) ; J != End ; J = nextJ ) { nextJ = std :: next ( J ) ; MachineOperand & Use = * J ; MachineInstr * UseMI = Use . getParent ( ) ; if ( MI != UseMI ) return false ; } } DeadPhis . push_back ( OnePhi ) ; } return true ; } </s>

isDead - Returns true if this is a dead def kill slot .


<s> void xtensa_split_operand_pair ( rtx operands [ 4 ] , enum machine_mode mode ) { switch ( GET_CODE ( operands [ 1 ] ) ) { case REG : operands [ 3 ] = gen_rtx_REG ( mode , REGNO ( operands [ 1 ] ) + 1 ) ; operands [ 2 ] = gen_rtx_REG ( mode , REGNO ( operands [ 1 ] ) ) ; break ; case MEM : operands [ 3 ] = adjust_address ( operands [ 1 ] , mode , GET_MODE_SIZE ( mode ) ) ; operands [ 2 ] = adjust_address ( operands [ 1 ] , mode , 0 ) ; break ; case CONST_INT : case CONST_DOUBLE : split_double ( operands [ 1 ] , & operands [ 2 ] , & operands [ 3 ] ) ; break ; default : gcc_unreachable ( ) ; } switch ( GET_CODE ( operands [ 0 ] ) ) { case REG : operands [ 1 ] = gen_rtx_REG ( mode , REGNO ( operands [ 0 ] ) + 1 ) ; operands [ 0 ] = gen_rtx_REG ( mode , REGNO ( operands [ 0 ] ) ) ; break ; case MEM : operands [ 1 ] = adjust_address ( operands [ 0 ] , mode , GET_MODE_SIZE ( mode ) ) ; operands [ 0 ] = adjust_address ( operands [ 0 ] , mode , 0 ) ; break ; default : gcc_unreachable ( ) ; } } </s>

Split OP [ 1 ] into OP [ 2,3 ] and likewise for OP [ 0 ] into OP [ 0,1 ] . MODE is for the output , i.e. , the input operands are twice as big as MODE .


<s> MachineBasicBlock :: iterator RISCVFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const RISCVInstrInfo & TII = * static_cast < const RISCVInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; const RISCVSubtarget & STI = MF . getSubtarget < RISCVSubtarget > ( ) ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( 0 ) . getImm ( ) ; if ( I -> getOpcode ( ) == RISCV :: ADJCALLSTACKDOWN ) Amount = - Amount ; unsigned SP = STI . isRV64 ( ) ? RISCV :: sp_64 : RISCV :: sp ; TII . adjustStackPtr ( SP , Amount , MBB , I ) ; } return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

RISCV RISCV RISCV RISCV RISCV RISCV 0 RISCV::ADJCALLSTACKDOWN RISCV::sp_64 RISCV::sp


<s> static void frv_align_label ( void ) { unsigned int alignment , target , nop ; rtx_insn * x , * last , * barrier , * label ; last = frv_packet . insns [ frv_packet . num_insns - 1 ] ; label = barrier = 0 ; alignment = 4 ; for ( x = NEXT_INSN ( last ) ; x != 0 && ! INSN_P ( x ) ; x = NEXT_INSN ( x ) ) { if ( LABEL_P ( x ) ) { unsigned int subalign = 1 << label_to_alignment ( x ) . levels [ 0 ] . log ; alignment = MAX ( alignment , subalign ) ; label = x ; } if ( BARRIER_P ( x ) ) barrier = x ; } if ( TARGET_ALIGN_LABELS && label != 0 && barrier == 0 && frv_packet . num_insns < frv_packet . issue_rate ) alignment = MAX ( alignment , 8 ) ; frv_packet_address += frv_packet . num_insns * 4 ; target = ( frv_packet_address + alignment - 1 ) & - alignment ; if ( barrier == 0 ) { for ( nop = 0 ; nop < frv_num_nops ; nop ++ ) while ( frv_packet_address < target && frv_pack_insn_p ( frv_nops [ nop ] ) ) { frv_insert_nop_in_packet ( frv_nops [ nop ] ) ; frv_packet_address += 4 ; } last = frv_packet . insns [ frv_packet . num_insns - 1 ] ; nop = 0 ; while ( frv_packet_address < target ) { last = emit_insn_after ( PATTERN ( frv_nops [ nop ] ) , last ) ; frv_packet_address += 4 ; if ( frv_num_nops > 1 ) nop ^= 1 ; } } frv_packet_address = target ; } </s>

If the current packet falls through to a label , try to pad the packet with nops in order to fit the label 's alignment requirements .


<s> void EmitInstruction ( uint64_t Val , unsigned Size , raw_ostream & OS ) const { for ( unsigned i = 0 ; i != Size ; ++ i ) { EmitByte ( Val & 255 , OS ) ; Val >>= 8 ; } } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static bool insn_terminates_group_p ( rtx insn , enum group_termination which_group ) { enum attr_type type ; if ( ! insn ) return false ; type = get_attr_type ( insn ) ; if ( is_microcoded_insn ( insn ) ) return true ; if ( which_group == current_group ) { if ( is_branch_slot_insn ( insn ) ) return true ; return false ; } else if ( which_group == previous_group ) { if ( is_dispatch_slot_restricted ( insn ) ) return true ; return false ; } return false ; } </s>

Return whether the presence of INSN causes a dispatch group termination of group WHICH_GROUP . If WHICH_GROUP == current_group , this function will return true if INSN causes the termination of the current group ( i.e , the dispatch group to which INSN belongs ) . This means that INSN will be the last insn in the group it belongs to . If WHICH_GROUP == previous_group , this function will return true if INSN causes the termination of the previous group ( i.e , the dispatch group that precedes the group to which INSN belongs ) . This means that INSN will be the first insn in the group it belongs to ) .


<s> const unsigned * SparcRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const unsigned CalleeSavedRegs [ ] = { 0 } ; return CalleeSavedRegs ; } </s>


<s> static SDNode * getInt64 ( SelectionDAG * CurDAG , SDNode * N ) { SDLoc dl ( N ) ; int64_t Imm = cast < ConstantSDNode > ( N ) -> getZExtValue ( ) ; return getInt64 ( CurDAG , dl , Imm ) ; } </s>


<s> const SHUXIRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> int pa_is_function_label_plus_const ( rtx op ) { if ( GET_CODE ( op ) == CONST ) op = XEXP ( op , 0 ) ; return ( GET_CODE ( op ) == PLUS && function_label_operand ( XEXP ( op , 0 ) , VOIDmode ) && GET_CODE ( XEXP ( op , 1 ) ) == CONST_INT ) ; } </s>

Returns 1 if OP is a function label involved in a simple addition with a constant . Used to keep certain patterns from matching during instruction combination .


<s> static rtx_code_label * ix86_expand_sse_compare_and_jump ( enum rtx_code code , rtx op0 , rtx op1 , bool swap_operands ) { machine_mode fpcmp_mode = ix86_fp_compare_mode ( code ) ; rtx_code_label * label ; rtx tmp ; if ( swap_operands ) std :: swap ( op0 , op1 ) ; label = gen_label_rtx ( ) ; tmp = gen_rtx_REG ( fpcmp_mode , FLAGS_REG ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , gen_rtx_COMPARE ( fpcmp_mode , op0 , op1 ) ) ) ; tmp = gen_rtx_fmt_ee ( code , VOIDmode , tmp , const0_rtx ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; tmp = emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , tmp ) ) ; JUMP_LABEL ( tmp ) = label ; return label ; } </s>

Expands a comparison of OP0 with OP1 using comparison code CODE , swapping the operands if SWAP_OPERANDS is true . The expanded code is a forward jump to a newly created label in case the comparison is true . The generated label rtx is returned .


"Cannot relax the instruction, value does not fit"

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> static bool cris_handle_option ( size_t code , const char * arg ATTRIBUTE_UNUSED , int value ATTRIBUTE_UNUSED ) { switch ( code ) { case OPT_metrax100 : target_flags |= ( MASK_SVINTO + MASK_ETRAX4_ADD + MASK_ALIGN_BY_32 ) ; break ; case OPT_mno_etrax100 : target_flags &= ~ ( MASK_SVINTO + MASK_ETRAX4_ADD + MASK_ALIGN_BY_32 ) ; break ; case OPT_m32_bit : case OPT_m32bit : target_flags |= ( MASK_STACK_ALIGN + MASK_CONST_ALIGN + MASK_DATA_ALIGN + MASK_ALIGN_BY_32 ) ; break ; case OPT_m16_bit : case OPT_m16bit : target_flags |= ( MASK_STACK_ALIGN + MASK_CONST_ALIGN + MASK_DATA_ALIGN ) ; break ; case OPT_m8_bit : case OPT_m8bit : target_flags &= ~ ( MASK_STACK_ALIGN + MASK_CONST_ALIGN + MASK_DATA_ALIGN ) ; break ; default : break ; } CRIS_SUBTARGET_HANDLE_OPTION ( code , arg , value ) ; return true ; } </s>

TARGET_HANDLE_OPTION worker . We just store the values into local variables here . Checks for correct semantics are in cris_override_options .


<s> void X86IntelInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( TSFlags & X86II :: LOCK ) OS << "\tlock\n" ; printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAnyX86InstComments ( MI , * CommentStream , getRegisterName ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> void WebAssemblyPassConfig :: addPreEmitPass ( ) { TargetPassConfig :: addPreEmitPass ( ) ; addPass ( createWebAssemblyCFGStackify ( ) ) ; addPass ( createWebAssemblyLowerBrUnless ( ) ) ; addPass ( createWebAssemblyRegNumbering ( ) ) ; addPass ( createWebAssemblyPeephole ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly


<s> static void pop ( struct unw_state_record * sr ) { struct unw_reg_state * rs = sr -> curr . next ; if ( ! rs ) abort ( ) ; memcpy ( & sr -> curr , rs , sizeof ( * rs ) ) ; free_reg_state ( rs ) ; } </s>

Output RTL to pop register RN from the stack .


<s> int vspltis_shifted ( rtx op ) { machine_mode mode = GET_MODE ( op ) ; machine_mode inner = GET_MODE_INNER ( mode ) ; unsigned i , j ; unsigned nunits ; unsigned mask ; HOST_WIDE_INT val ; if ( mode != V16QImode && mode != V8HImode && mode != V4SImode ) return false ; if ( ! can_create_pseudo_p ( ) ) return false ; nunits = GET_MODE_NUNITS ( mode ) ; mask = GET_MODE_MASK ( inner ) ; val = const_vector_elt_as_int ( op , BYTES_BIG_ENDIAN ? 0 : nunits - 1 ) ; if ( EASY_VECTOR_15 ( val ) ) ; else if ( EASY_VECTOR_MSB ( val , inner ) ) ; else return 0 ; for ( i = 1 ; i < nunits ; ++ i ) { unsigned elt = BYTES_BIG_ENDIAN ? i : nunits - 1 - i ; HOST_WIDE_INT elt_val = const_vector_elt_as_int ( op , elt ) ; if ( val != elt_val ) { if ( elt_val == 0 ) { for ( j = i + 1 ; j < nunits ; ++ j ) { unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j ; if ( const_vector_elt_as_int ( op , elt2 ) != 0 ) return 0 ; } return ( nunits - i ) * GET_MODE_SIZE ( inner ) ; } else if ( ( elt_val & mask ) == mask ) { for ( j = i + 1 ; j < nunits ; ++ j ) { unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j ; if ( ( const_vector_elt_as_int ( op , elt2 ) & mask ) != mask ) return 0 ; } return - ( ( nunits - i ) * GET_MODE_SIZE ( inner ) ) ; } else return 0 ; } } return 0 ; } </s>

Like vsplitis_constant , but allow the value to be shifted left with a VSLDOI instruction , filling in the bottom elements with 0 or -1 . Return 0 if the constant can not be generated with VSLDOI . Return positive for the number of zeroes to shift in , or negative for the number of 0xff bytes to shift in . OP is a CONST_VECTOR .


"Blocked load and store instructions: \n"

runOnMachineFunction - Emit the function body .


<s> static bool mips_return_mode_in_fpr_p ( machine_mode mode ) { gcc_assert ( TARGET_PAIRED_SINGLE_FLOAT || mode != V2SFmode ) ; return ( ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || mode == V2SFmode || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) && GET_MODE_UNIT_SIZE ( mode ) <= UNITS_PER_HWFPVALUE ) ; } </s>

Return true if the function return value MODE will get returned in a floating-point register .


<s>
unsigned
X86InstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugInstr
(
)
)
continue
;
if
(
I
->
getOpcode
(
)
!=
X86
::
JMP_1
&&
X86
::
getCondFromBranch
(
*
I
)
==
X86
::
COND_INVALID
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s> static unsigned size ( const GraphType & G ) { return G . Nodes . size ( ) ; } </s>

The number of name/type pairs is returned .


<s> WebAssemblySubtarget :: WebAssemblySubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : WebAssemblyGenSubtargetInfo ( TT , CPU , FS ) , HasSIMD128 ( false ) , HasAtomics ( false ) , CPUString ( CPU ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS ) ) , TSInfo ( ) , TLInfo ( TM , * this ) { } </s>

This constructor initializes the data members to match that of the specified triple .

WebAssembly WebAssembly WebAssembly WebAssembly


<s>
SDValue
BPFTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

BPF
BPF
ISD::BR_CC
ISD::GlobalAddress
ISD::SELECT_CC
"unimplemented operand"


<s> bool MipsAsmBackend :: getFixupKind ( StringRef Name , MCFixupKind & MappedKind ) const { if ( Name == "R_MIPS_NONE" ) { MappedKind = ( MCFixupKind ) Mips :: fixup_Mips_NONE ; return true ; } if ( Name == "R_MIPS_32" ) { MappedKind = FK_Data_4 ; return true ; } return MCAsmBackend :: getFixupKind ( Name , MappedKind ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> inline hashval_t bundle_state_hasher :: hash ( const value_type * state ) { unsigned result , i ; for ( result = i = 0 ; i < dfa_state_size ; i ++ ) result += ( ( ( unsigned char * ) state -> dfa_state ) [ i ] << ( ( i % CHAR_BIT ) * 3 + CHAR_BIT ) ) ; return result + state -> insn_num ; } </s>

Hash function for builtin functions with up to 3 arguments and a return type .


<s> virtual MVT getScalarShiftAmountTy ( EVT LHSTy ) const { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> uint64_t flags ( ) const { return 0x0 ; } </s>

Get the flags for this GlobalValue ( see struct GVFlags ) .


<s> static bool s390_use_by_pieces_infrastructure_p ( unsigned HOST_WIDE_INT size , unsigned int align ATTRIBUTE_UNUSED , enum by_pieces_operation op ATTRIBUTE_UNUSED , bool speed_p ATTRIBUTE_UNUSED ) { return ( size == 1 || size == 2 || size == 4 || ( TARGET_ZARCH && size == 8 ) ) ; } </s>


<s>
void
ArgDescriptor
::
print
(
raw_ostream
&
OS
,
const
TargetRegisterInfo
*
TRI
)
const
{
if
(
!
isSet
(
)
)
{
OS
<<
"<not set>\n"
;
return
;
}
if
(
isRegister
(
)
)
OS
<<
"Reg "
<<
printReg
(
getRegister
(
)
,
TRI
)
<<
'\n'
;
else
OS
<<
"Stack offset "
<<
getStackOffset
(
)
<<
'\n'
;
}
</s>

print - Print a debug representation of the operand to the given stream .

AMDGPU
"<not set>\n"
"Reg "
"Stack offset "


<s> bool SILowerI1Copies :: runOnMachineFunction ( MachineFunction & TheMF ) { if ( TheMF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: Selected ) ) return false ; MF = & TheMF ; MRI = & MF -> getRegInfo ( ) ; DT = & getAnalysis < MachineDominatorTree > ( ) ; PDT = & getAnalysis < MachinePostDominatorTree > ( ) ; ST = & MF -> getSubtarget < GCNSubtarget > ( ) ; TII = ST -> getInstrInfo ( ) ; IsWave32 = ST -> isWave32 ( ) ; if ( IsWave32 ) { ExecReg = AMDGPU :: EXEC_LO ; MovOp = AMDGPU :: S_MOV_B32 ; AndOp = AMDGPU :: S_AND_B32 ; OrOp = AMDGPU :: S_OR_B32 ; XorOp = AMDGPU :: S_XOR_B32 ; AndN2Op = AMDGPU :: S_ANDN2_B32 ; OrN2Op = AMDGPU :: S_ORN2_B32 ; } else { ExecReg = AMDGPU :: EXEC ; MovOp = AMDGPU :: S_MOV_B64 ; AndOp = AMDGPU :: S_AND_B64 ; OrOp = AMDGPU :: S_OR_B64 ; XorOp = AMDGPU :: S_XOR_B64 ; AndN2Op = AMDGPU :: S_ANDN2_B64 ; OrN2Op = AMDGPU :: S_ORN2_B64 ; } bool Changed = false ; Changed |= lowerCopiesFromI1 ( ) ; Changed |= lowerPhis ( ) ; Changed |= lowerCopiesToI1 ( ) ; assert ( Changed || ConstrainRegs . empty ( ) ) ; for ( unsigned Reg : ConstrainRegs ) MRI -> constrainRegClass ( Reg , & AMDGPU :: SReg_1_XEXECRegClass ) ; ConstrainRegs . clear ( ) ; return Changed ; } </s>


<s> void rs6000_conditional_register_usage ( void ) { int i ; if ( ! TARGET_POWER ) fixed_regs [ 64 ] = 1 ; if ( TARGET_64BIT ) fixed_regs [ 13 ] = call_used_regs [ 13 ] = call_really_used_regs [ 13 ] = 1 ; if ( TARGET_SOFT_FLOAT || ! TARGET_FPRS ) for ( i = 32 ; i < 64 ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = call_really_used_regs [ i ] = 1 ; if ( DEFAULT_ABI == ABI_AIX ) call_really_used_regs [ 2 ] = 0 ; if ( DEFAULT_ABI == ABI_V4 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM && flag_pic == 2 ) fixed_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = 1 ; if ( DEFAULT_ABI == ABI_V4 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM && flag_pic == 1 ) fixed_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = call_used_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = call_really_used_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = 1 ; if ( DEFAULT_ABI == ABI_DARWIN && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM ) fixed_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = call_used_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = call_really_used_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = 1 ; if ( TARGET_TOC && TARGET_MINIMAL_TOC ) fixed_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = call_used_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = 1 ; if ( TARGET_ALTIVEC ) global_regs [ VSCR_REGNO ] = 1 ; if ( TARGET_SPE ) { global_regs [ SPEFSCR_REGNO ] = 1 ; fixed_regs [ FIXED_SCRATCH ] = call_used_regs [ FIXED_SCRATCH ] = call_really_used_regs [ FIXED_SCRATCH ] = 1 ; } if ( ! TARGET_ALTIVEC ) { for ( i = FIRST_ALTIVEC_REGNO ; i <= LAST_ALTIVEC_REGNO ; ++ i ) fixed_regs [ i ] = call_used_regs [ i ] = call_really_used_regs [ i ] = 1 ; call_really_used_regs [ VRSAVE_REGNO ] = 1 ; } if ( TARGET_ALTIVEC_ABI ) for ( i = FIRST_ALTIVEC_REGNO ; i < FIRST_ALTIVEC_REGNO + 20 ; ++ i ) call_used_regs [ i ] = call_really_used_regs [ i ] = 1 ; } </s>

Change register usage conditional on target flags .


<s> const LegalizerInfo * getLegalizerInfo ( ) const override { return & Legalizer ; } </s>

Expose LegalizerInfo so the clients can re-use .


<s> bool isTarget64BitLP64 ( ) const { return In64BitMode && ( TargetTriple . getEnvironment ( ) != Triple :: GNUX32 && TargetTriple . getOS ( ) != Triple :: NaCl ) ; } </s>

Is this x86_64 with the LP64 programming model ( standard AMD64 , no x32 ) ?


<s> void HexagonInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << getRegisterName ( RegNo ) ; } </s>


<s> scalar_chain :: ~ scalar_chain ( ) { BITMAP_FREE ( insns ) ; BITMAP_FREE ( defs ) ; BITMAP_FREE ( defs_conv ) ; bitmap_obstack_release ( NULL ) ; } </s>


<s> MachinePointerInfo SICFunctionInfo :: callPtrInfo ( const GlobalValue * GV ) { return MachinePointerInfo ( MF . getPSVManager ( ) . getGlobalValueCallEntry ( GV ) ) ; } </s>

Create a MachinePointerInfo that has a GlobalValuePseudoSourceValue object representing a GOT entry for a global function .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { if ( ! FastEstimation ) AU . addRequired < MachineProfileAnalysis > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .