<s> static void update_set_flags ( rtx x , struct reg_flags * pflags ) { rtx src = SET_SRC ( x ) ; switch ( GET_CODE ( src ) ) { case CALL : return ; case IF_THEN_ELSE : return ; default : if ( COMPARISON_P ( src ) && SCALAR_FLOAT_MODE_P ( GET_MODE ( XEXP ( src , 0 ) ) ) ) pflags -> is_fp = 1 ; else if ( GET_CODE ( src ) == AND ) pflags -> is_and = 1 ; else if ( GET_CODE ( src ) == IOR ) pflags -> is_or = 1 ; break ; } } </s>

Examine X , which is a SET rtx , and update the flags , the predicate , and the condition , stored in * PFLAGS , * PPRED and * PCOND .


<s> static void frv_io_check_address ( rtx x , rtx pat ATTRIBUTE_UNUSED , void * data ) { rtx * other = data ; if ( REG_P ( x ) && * other != 0 && reg_overlap_mentioned_p ( x , * other ) ) * other = 0 ; } </s>

A note_stores callback for which DATA points to an rtx . Nullify * DATA if X is a register and * DATA depends on X .


<s> bool X86FastTileConfig :: runOnMachineFunction ( MachineFunction & MFunc ) { MF = & MFunc ; MRI = & MFunc . getRegInfo ( ) ; ST = & MFunc . getSubtarget < X86Subtarget > ( ) ; TRI = ST -> getRegisterInfo ( ) ; TII = MFunc . getSubtarget ( ) . getInstrInfo ( ) ; return fastTileConfig ( ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool sh_cannot_copy_insn_p ( rtx insn ) { rtx pat ; if ( ! reload_completed || ! flag_pic ) return false ; if ( GET_CODE ( insn ) != INSN ) return false ; if ( asm_noperands ( insn ) >= 0 ) return false ; pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) != SET ) return false ; pat = SET_SRC ( pat ) ; if ( unspec_caller_rtx_p ( pat ) ) return true ; return false ; } </s>

Indicate that INSN can not be duplicated . This is true for insn that generates a unique label .


<s> bool WebAssemblyLateEHPrepare :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getTarget ( ) . getMCAsmInfo ( ) -> getExceptionHandlingType ( ) != ExceptionHandling :: Wasm ) return false ; bool Changed = false ; Changed |= removeUnnecessaryUnreachables ( MF ) ; Changed |= addRethrows ( MF ) ; if ( ! MF . getFunction ( ) . hasPersonalityFn ( ) ) return Changed ; Changed |= replaceFuncletReturns ( MF ) ; Changed |= hoistCatches ( MF ) ; Changed |= addCatchAlls ( MF ) ; Changed |= ensureSingleBBTermPads ( MF ) ; Changed |= mergeTerminatePads ( MF ) ; Changed |= addCatchAllTerminatePads ( MF ) ; return Changed ; } </s>


<s> SDValue Cpu0TargetLowering :: LowerCall ( TargetLowering :: CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const { return CLI . Chain ; } </s>

This hook must be implemented to lower calls into the specified DAG .


<s> unsigned RISCVInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : { return get ( Opcode ) . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return 0 ; case RISCV :: PseudoCALL : case RISCV :: PseudoTAIL : return 8 ; case TargetOpcode :: INLINEASM : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const auto & TM = static_cast < const RISCVTargetMachine & > ( MF . getTarget ( ) ) ; return getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> opt_machine_mode arm_get_mask_mode ( machine_mode mode ) { if ( TARGET_HAVE_MVE ) return arm_mode_to_pred_mode ( mode ) ; return default_get_mask_mode ( mode ) ; } </s>


<s> static int arm_address_register_rtx_p ( rtx x , int strict_p ) { int regno ; if ( ! REG_P ( x ) ) return 0 ; regno = REGNO ( x ) ; if ( strict_p ) return ARM_REGNO_OK_FOR_BASE_P ( regno ) ; return ( regno <= LAST_ARM_REGNUM || regno >= FIRST_PSEUDO_REGISTER || regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) ; } </s>

Return nonzero if X is valid as an ARM state addressing register .


<s> static inline VConstraintType getConstraint ( uint64_t TSFlags ) { return static_cast < VConstraintType > ( ( TSFlags & ConstraintMask ) >> ConstraintShift ) ; } </s>

Fetch condition in the form of PredicateConstraint , if possible .


<s> bool X86TargetLowering :: isLegalAddImmediate ( int64_t Imm ) const { return Imm == ( int32_t ) Imm ; } </s>

Return true if the specified immediate is legal add immediate , that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register .


<s> int iq2000_adjust_insn_length ( rtx_insn * insn , int length ) { if ( simplejump_p ( insn ) || ( ( JUMP_P ( insn ) || CALL_P ( insn ) ) ) ) length += 4 ; return length ; } </s>

Return the length of INSN . LENGTH is the initial length computed by attributes in the machine-description file .


<s> const TargetRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static sbitmap aarch64_components_for_bb ( basic_block bb ) { bitmap in = DF_LIVE_IN ( bb ) ; bitmap gen = & DF_LIVE_BB_INFO ( bb ) -> gen ; bitmap kill = & DF_LIVE_BB_INFO ( bb ) -> kill ; sbitmap components = sbitmap_alloc ( LAST_SAVED_REGNUM + 1 ) ; bitmap_clear ( components ) ; function_abi_aggregator callee_abis ; rtx_insn * insn ; FOR_BB_INSNS ( bb , insn ) if ( CALL_P ( insn ) ) callee_abis . note_callee_abi ( insn_callee_abi ( insn ) ) ; HARD_REG_SET extra_caller_saves = callee_abis . caller_save_regs ( * crtl -> abi ) ; for ( unsigned regno = 0 ; regno <= LAST_SAVED_REGNUM ; regno ++ ) if ( ! fixed_regs [ regno ] && ! crtl -> abi -> clobbers_full_reg_p ( regno ) && ( TEST_HARD_REG_BIT ( extra_caller_saves , regno ) || bitmap_bit_p ( in , regno ) || bitmap_bit_p ( gen , regno ) || bitmap_bit_p ( kill , regno ) ) ) { bitmap_set_bit ( components , regno ) ; poly_int64 offset = cfun -> machine -> frame . reg_offset [ regno ] ; unsigned regno2 = multiple_p ( offset , 16 ) ? regno + 1 : regno - 1 ; if ( regno2 <= LAST_SAVED_REGNUM ) { poly_int64 offset2 = cfun -> machine -> frame . reg_offset [ regno2 ] ; if ( regno < regno2 ? known_eq ( offset + 8 , offset2 ) : multiple_p ( offset2 , 16 ) && known_eq ( offset2 + 8 , offset ) ) bitmap_set_bit ( components , regno2 ) ; } } return components ; } </s>


<s>
bool
X86InstrInfo
::
expandPostRAPseudo
(
MachineBasicBlock
::
iterator
MI
)
const
{
bool
HasAVX
=
TM
.
getSubtarget
<
X86Subtarget
>
(
)
.
hasAVX
(
)
;
MachineInstrBuilder
MIB
(
*
MI
->
getParent
(
)
->
getParent
(
)
,
MI
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
X86
::
SETB_C8r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB8rr
)
)
;
case
X86
::
SETB_C16r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB16rr
)
)
;
case
X86
::
SETB_C32r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB32rr
)
)
;
case
X86
::
SETB_C64r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB64rr
)
)
;
case
X86
::
V_SET0
:
case
X86
::
FsFLD0SS
:
case
X86
::
FsFLD0SD
:
return
Expand2AddrUndef
(
MIB
,
get
(
HasAVX
X86
::
VXORPSrr
:
X86
::
XORPSrr
)
)
;
case
X86
::
AVX_SET0
:
assert
(
HasAVX
&&
"AVX not supported"
)
;
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VXORPSYrr
)
)
;
case
X86
::
AVX512_512_SET0
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VPXORDZrr
)
)
;
case
X86
::
V_SETALLONES
:
return
Expand2AddrUndef
(
MIB
,
get
(
HasAVX
X86
::
VPCMPEQDrr
:
X86
::
PCMPEQDrr
)
)
;
case
X86
::
AVX2_SETALLONES
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VPCMPEQDYrr
)
)
;
case
X86
::
TEST8ri_NOREX
:
MI
->
setDesc
(
get
(
X86
::
TEST8ri
)
)
;
return
true
;
case
X86
::
KSET0W
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
KXORWrr
)
)
;
case
X86
::
KSET1B
:
case
X86
::
KSET1W
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
KXNORWrr
)
)
;
}
return
false
;
}
</s>

This function is called for all pseudo instructions that remain after register allocation .


<s> enum machine_mode arc_select_cc_mode ( enum rtx_code op , rtx x ATTRIBUTE_UNUSED , rtx y ATTRIBUTE_UNUSED ) { switch ( op ) { case EQ : case NE : return CCZNmode ; default : switch ( GET_CODE ( x ) ) { case AND : case IOR : case XOR : case SIGN_EXTEND : case ZERO_EXTEND : return CCZNmode ; case ASHIFT : case ASHIFTRT : case LSHIFTRT : return CCZNCmode ; default : break ; } } return CCmode ; } </s>

Given a comparison code ( EQ , NE , etc . ) and the first operand of a COMPARE , return the mode to be used for the comparison .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"TMS320C64X Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> machine_mode cris_promote_function_mode ( const_tree type ATTRIBUTE_UNUSED , machine_mode mode , int * punsignedp ATTRIBUTE_UNUSED , const_tree fntype ATTRIBUTE_UNUSED , int for_return ) { if ( for_return == 1 ) return mode ; return CRIS_PROMOTED_MODE ( mode , * punsignedp , type ) ; } </s>

A combination of defining TARGET_PROMOTE_FUNCTION_MODE , promoting arguments and * not * defining TARGET_PROMOTE_PROTOTYPES or PROMOTE_MODE gives the best code size and speed for gcc , ipps and products in gcc-2.7.2 .


<s> static void csky_conditional_register_usage ( void ) { if ( TARGET_MINI_REGISTERS ) { int i ; for ( i = ( CSKY_LAST_MINI_REGNUM + 1 ) ; i < 32 ; i ++ ) { fixed_regs [ i ] = 1 ; call_used_regs [ i ] = 1 ; } } else if ( CSKY_TARGET_ARCH ( CK802 ) || CSKY_TARGET_ARCH ( CK803 ) || ! TARGET_HIGH_REGISTERS ) { int i ; for ( i = CSKY_FIRST_HIGH_REGNUM ; i <= CSKY_LAST_HIGH_REGNUM ; i ++ ) { fixed_regs [ i ] = 1 ; call_used_regs [ i ] = 1 ; } } if ( CSKY_TARGET_ARCH ( CK801 ) || CSKY_TARGET_ARCH ( CK802 ) ) { fixed_regs [ CSKY_LR_REGNUM ] = 1 ; call_used_regs [ CSKY_LR_REGNUM ] = 0 ; } if ( ! TARGET_DSP ) { fixed_regs [ CSKY_HI_REGNUM ] = 1 ; call_used_regs [ CSKY_HI_REGNUM ] = 1 ; fixed_regs [ CSKY_LO_REGNUM ] = 1 ; call_used_regs [ CSKY_LO_REGNUM ] = 1 ; } if ( ! TARGET_HARD_FLOAT ) { int regno ; for ( regno = CSKY_FIRST_VFP_REGNUM ; regno <= CSKY_LAST_VFP3_REGNUM ; regno ++ ) { fixed_regs [ regno ] = 1 ; call_used_regs [ regno ] = 1 ; } } if ( ! TARGET_SUPPORT_FPV3 ) { int regno ; for ( regno = CSKY_FIRST_VFP3_REGNUM ; regno <= CSKY_LAST_VFP3_REGNUM ; regno ++ ) { fixed_regs [ regno ] = 1 ; call_used_regs [ regno ] = 1 ; } } if ( flag_pic ) { fixed_regs [ PIC_OFFSET_TABLE_REGNUM ] = 1 ; call_used_regs [ PIC_OFFSET_TABLE_REGNUM ] = 0 ; } } </s>

Implement TARGET_CONDITIONAL_REGISTER_USAGE . Conditionally modify five variables fixed_regs , call_used_regs , global_regs , reg_names , and reg_class_contents , to take into account any dependence of these register sets on target flags . CK801 has registers r0-r8 and r13-r15 . CK802 and CK803 have registers r0-r15 ( the `` low '' registers ) . Other cpus use registers r0-r31 with -mhigh-registers , otherwise also only r0-r15 . CK801 only has 16-bit instructions , most of which can only reference r0-r7 ( the `` mini '' registers ) . So we mark regs outside that range as fixed . -msmart can be used on other arch variants to force the same behavior because it results in smaller code size . TODO : investigate whether it 's beneficial to use r8-r13 as a spill class when TARGET_MINI_REGISTERS instead of making them unusable by the register allocator .


<s> bool PPCLoopPreIncPrep :: runOnFunction ( Function & F ) { LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolution > ( ) ; DataLayoutPass * DLP = getAnalysisIfAvailable < DataLayoutPass > ( ) ; DL = DLP ? & DLP -> getDataLayout ( ) : 0 ; bool MadeChange = false ; for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) { Loop * L = * I ; MadeChange |= runOnLoop ( L ) ; } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static rtx v850_function_value ( const_tree valtype , const_tree fn_decl_or_type ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( TYPE_MODE ( valtype ) , 10 ) ; } </s>

Worker function for TARGET_FUNCTION_VALUE .


<s> void AArch64CallLowering :: splitToValueTypes ( const ArgInfo & OrigArg , SmallVectorImpl < ArgInfo > & SplitArgs , const DataLayout & DL , MachineRegisterInfo & MRI , const SplitArgTy & PerformArgSplit ) const { const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; LLVMContext & Ctx = OrigArg . Ty -> getContext ( ) ; SmallVector < EVT , 4 > SplitVTs ; SmallVector < uint64_t , 4 > Offsets ; ComputeValueVTs ( TLI , DL , OrigArg . Ty , SplitVTs , & Offsets , 0 ) ; if ( SplitVTs . size ( ) == 1 ) { SplitArgs . emplace_back ( OrigArg . Reg , SplitVTs [ 0 ] . getTypeForEVT ( Ctx ) , OrigArg . Flags , OrigArg . IsFixed ) ; return ; } unsigned FirstRegIdx = SplitArgs . size ( ) ; for ( auto SplitVT : SplitVTs ) { Type * SplitTy = SplitVT . getTypeForEVT ( Ctx ) ; SplitArgs . push_back ( ArgInfo { MRI . createGenericVirtualRegister ( getLLTForType ( * SplitTy , DL ) ) , SplitTy , OrigArg . Flags , OrigArg . IsFixed } ) ; } for ( unsigned i = 0 ; i < Offsets . size ( ) ; ++ i ) PerformArgSplit ( SplitArgs [ FirstRegIdx + i ] . Reg , Offsets [ i ] * 8 ) ; } </s>

Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> unsigned R600RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return AMDGPU :: NoRegister ; } </s>


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ; } </s>


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { MachineFunction & MF = MIRBuilder . getMF ( ) ; LLT p0 = LLT :: pointer ( 0 , 64 ) ; LLT s64 = LLT :: scalar ( 64 ) ; if ( IsTailCall ) { Offset += FPDiff ; int FI = MF . getFrameInfo ( ) . CreateFixedObject ( Size , Offset , true ) ; Register FIReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildFrameIndex ( FIReg , FI ) ; MPO = MachinePointerInfo :: getFixedStack ( MF , FI ) ; return FIReg ; } if ( ! SPReg ) SPReg = MIRBuilder . buildCopy ( p0 , Register ( AArch64 :: SP ) ) . getReg ( 0 ) ; Register OffsetReg = MRI . createGenericVirtualRegister ( s64 ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; Register AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildPtrAdd ( AddrReg , SPReg , OffsetReg ) ; MPO = MachinePointerInfo :: getStack ( MF , Offset ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> static void lm32_block_move_inline ( rtx dest , rtx src , HOST_WIDE_INT length , HOST_WIDE_INT alignment ) { HOST_WIDE_INT offset , delta ; unsigned HOST_WIDE_INT bits ; int i ; machine_mode mode ; rtx * regs ; switch ( alignment ) { case 1 : bits = 8 ; break ; case 2 : bits = 16 ; break ; default : bits = 32 ; break ; } mode = int_mode_for_size ( bits , 0 ) . require ( ) ; delta = bits / BITS_PER_UNIT ; regs = XALLOCAVEC ( rtx , length / delta ) ; for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) { regs [ i ] = gen_reg_rtx ( mode ) ; emit_move_insn ( regs [ i ] , adjust_address ( src , mode , offset ) ) ; } for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) emit_move_insn ( adjust_address ( dest , mode , offset ) , regs [ i ] ) ; if ( offset < length ) { src = adjust_address ( src , BLKmode , offset ) ; dest = adjust_address ( dest , BLKmode , offset ) ; move_by_pieces ( dest , src , length - offset , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) , 0 ) ; } } </s>

Emit straight-line code to move LENGTH bytes from SRC to DEST . Assume that the areas do not overlap .


<s> static int getRegClass ( bool IsVgpr , unsigned RegWidth ) { if ( IsVgpr ) { switch ( RegWidth ) { default : return - 1 ; case 1 : return AMDGPU :: VGPR_32RegClassID ; case 2 : return AMDGPU :: VReg_64RegClassID ; case 3 : return AMDGPU :: VReg_96RegClassID ; case 4 : return AMDGPU :: VReg_128RegClassID ; case 8 : return AMDGPU :: VReg_256RegClassID ; case 16 : return AMDGPU :: VReg_512RegClassID ; } } switch ( RegWidth ) { default : return - 1 ; case 1 : return AMDGPU :: SGPR_32RegClassID ; case 2 : return AMDGPU :: SGPR_64RegClassID ; case 4 : return AMDGPU :: SReg_128RegClassID ; case 8 : return AMDGPU :: SReg_256RegClassID ; case 16 : return AMDGPU :: SReg_512RegClassID ; } } </s>

Given a machine instruction descriptor , returns the register class constraint for OpNum , or NULL .


"  Copied r%d to a vector register r%d for insn %d\n"

Make vector copies for all register REGNO definitions and replace its uses in a chain .


<s>
unsigned
getReg
(
)
const
{
assert
(
isRegNumber
(
)
&&
"Invalid access!"
)
;
return
(
unsigned
)
Imm
.
Val
;
}
</s>

Returns the register associated with this edge .


<s> static void fold_compare_helper ( gimple_stmt_iterator * gsi , tree_code code , gimple * stmt ) { tree arg0 = gimple_call_arg ( stmt , 0 ) ; tree arg1 = gimple_call_arg ( stmt , 1 ) ; tree lhs = gimple_call_lhs ( stmt ) ; tree cmp = fold_build_vec_cmp ( code , TREE_TYPE ( lhs ) , arg0 , arg1 , gsi ) ; gimple * g = gimple_build_assign ( lhs , cmp ) ; gimple_set_location ( g , gimple_location ( stmt ) ) ; gsi_replace ( gsi , g , true ) ; } </s>

Helper function to handle the in-between steps for the vector compare built-ins .


<s> bool SystemZAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { if ( ExtraCode ) return AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , OS ) ; SystemZMCInstLower Lower ( MF -> getContext ( ) , * this ) ; MCOperand MO ( Lower . lowerOperand ( MI -> getOperand ( OpNo ) ) ) ; SystemZInstPrinter :: printOperand ( MO , MAI , OS ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


"Cannot store this register to stack slot!"

Load the specified register of the given register class from the specified stack frame index .


<s> int mmix_initial_elimination_offset ( int fromreg , int toreg ) { int regno ; int fp_sp_offset = ( get_frame_size ( ) + crtl -> outgoing_args_size + 7 ) & ~ 7 ; if ( fromreg == MMIX_ARG_POINTER_REGNUM && toreg == MMIX_FRAME_POINTER_REGNUM ) return 0 ; for ( regno = MMIX_FIRST_GLOBAL_REGNUM ; regno <= 255 ; regno ++ ) if ( ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) || IS_MMIX_EH_RETURN_DATA_REG ( regno ) ) fp_sp_offset += 8 ; return fp_sp_offset + ( MMIX_CFUN_HAS_LANDING_PAD ? 16 : ( MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS ? 8 : 0 ) ) + ( fromreg == MMIX_ARG_POINTER_REGNUM ? 0 : 8 ) ; } </s>

The difference between the ( imaginary ) frame pointer and the stack pointer . Used to eliminate the frame pointer .


<s> void split_addsi ( rtx * operands ) { int val = INTVAL ( operands [ 2 ] ) ; if ( val > 127 && val <= 255 && satisfies_constraint_Rcq ( operands [ 0 ] ) ) { operands [ 3 ] = operands [ 2 ] ; operands [ 4 ] = gen_rtx_PLUS ( SImode , operands [ 0 ] , operands [ 1 ] ) ; } else { operands [ 3 ] = operands [ 1 ] ; operands [ 4 ] = gen_rtx_PLUS ( SImode , operands [ 0 ] , operands [ 2 ] ) ; } } </s>

Operands 0 .. 2 are the operands of a addsi which uses a 12 bit constant in operand 2 , but which would require a LIMM because of operand mismatch . operands 3 and 4 are new SET_SRCs for operands 0 .


<s> static void ix86_dwarf_handle_frame_unspec ( const char * label , rtx pattern , int index ) { rtx unspec = SET_SRC ( pattern ) ; gcc_assert ( GET_CODE ( unspec ) == UNSPEC ) ; switch ( index ) { case UNSPEC_REG_SAVE : dwarf2out_reg_save_reg ( label , XVECEXP ( unspec , 0 , 0 ) , SET_DEST ( pattern ) ) ; break ; case UNSPEC_DEF_CFA : dwarf2out_def_cfa ( label , REGNO ( SET_DEST ( pattern ) ) , INTVAL ( XVECEXP ( unspec , 0 , 0 ) ) ) ; break ; default : gcc_unreachable ( ) ; } } </s>

Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook . This is called from dwarf2out.c to emit call frame instructions for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs .


<s>
void
relaxInstruction
(
const
MCInst
&
Inst
,
MCInst
&
Res
)
const
{
assert
(
0
&&
"relaxInstruction() unimplemented"
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .

PowerPC
0
"relaxInstruction() unimplemented"


<s> bool ARMTTIImpl :: isLegalMaskedLoad ( Type * DataTy ) { if ( ! EnableMaskedLoadStores || ! ST -> hasMVEIntegerOps ( ) ) return false ; if ( DataTy -> isVectorTy ( ) ) { unsigned VecWidth = DataTy -> getPrimitiveSizeInBits ( ) ; if ( VecWidth != 128 ) return false ; } unsigned EltWidth = DataTy -> getScalarSizeInBits ( ) ; return EltWidth == 32 || EltWidth == 16 || EltWidth == 8 ; } </s>

Return true if the target supports masked load .


<s> X86TargetLowering :: ConstraintType X86TargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'A' : return C_Register ; case 'f' : case 'r' : case 'R' : case 'l' : case 'q' : case 'Q' : case 'x' : case 'y' : case 'Y' : return C_RegisterClass ; case 'e' : case 'Z' : return C_Other ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> static rtx rs6000_emit_vector_compare_inner ( enum rtx_code code , rtx op0 , rtx op1 ) { rtx mask ; machine_mode mode = GET_MODE ( op0 ) ; switch ( code ) { default : break ; case GE : if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) return NULL_RTX ; case EQ : case GT : case GTU : case ORDERED : case UNORDERED : case UNEQ : case LTGT : mask = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( mask , gen_rtx_fmt_ee ( code , mode , op0 , op1 ) ) ) ; return mask ; } return NULL_RTX ; } </s>

Return insn for VSX or Altivec comparisons .


<s> DecodeStatus HexagonDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & os , raw_ostream & cs ) const { DecodeStatus Result = DecodeStatus :: Success ; bool Complete = false ; Size = 0 ; * CurrentBundle = & MI ; MI = HexagonMCInstrInfo :: createBundle ( ) ; while ( Result == Success && ! Complete ) { if ( Bytes . size ( ) < HEXAGON_INSTR_SIZE ) return MCDisassembler :: Fail ; MCInst * Inst = new ( getContext ( ) ) MCInst ; Result = getSingleInstruction ( * Inst , MI , Bytes , Address , os , cs , Complete ) ; MI . addOperand ( MCOperand :: createInst ( Inst ) ) ; Size += HEXAGON_INSTR_SIZE ; Bytes = Bytes . slice ( HEXAGON_INSTR_SIZE ) ; } if ( Result == MCDisassembler :: Fail ) return Result ; if ( Size > HEXAGON_MAX_PACKET_SIZE ) return MCDisassembler :: Fail ; HexagonMCChecker Checker ( getContext ( ) , * MCII , STI , MI , * getContext ( ) . getRegisterInfo ( ) , false ) ; if ( ! Checker . check ( ) ) return MCDisassembler :: Fail ; return MCDisassembler :: Success ; } </s>

Returns the disassembly of a single instruction .


<s> bool XCoreRegisterInfo :: needsFrameMoves ( const MachineFunction & MF ) { return MF . getMMI ( ) . hasDebugInfo ( ) || ! MF . getFunction ( ) -> doesNotThrow ( ) || UnwindTablesMandatory ; } </s>


<s> const uint32_t * RISCVRegisterInfo :: getNoPreservedMask ( ) const { return CSR_NoRegs_RegMask ; } </s>

Return a register mask that clobbers everything .


<s> VariantKind getKind ( ) const { return static_cast < VariantKind > ( Kind ) ; } </s>


<s>
const
uint32_t
*
RISCVRegisterInfo
::
getCallPreservedMask
(
const
MachineFunction
&
MF
,
CallingConv
::
ID
)
const
{
auto
&
Subtarget
=
MF
.
getSubtarget
<
RISCVSubtarget
>
(
)
;
if
(
MF
.
getFunction
(
)
.
hasFnAttribute
(
"interrupt"
)
)
{
if
(
Subtarget
.
hasStdExtD
(
)
)
return
CSR_XLEN_F64_Interrupt_RegMask
;
if
(
Subtarget
.
hasStdExtF
(
)
)
return
CSR_XLEN_F32_Interrupt_RegMask
;
if
(
Subtarget
.
hasStdExtV
(
)
)
return
CSR_XLEN_F32_VEC_Interrupt_RegMask
;
return
CSR_Interrupt_RegMask
;
}
if
(
MF
.
getSubtarget
<
RISCVSubtarget
>
(
)
.
hasStdExtV
(
)
)
return
CSR_ILP32F_LP64F_VEC_RegMask
;
if
(
MF
.
getSubtarget
<
RISCVSubtarget
>
(
)
.
hasStdExtF
(
)
)
return
CSR_ILP32F_LP64F_RegMask
;
switch
(
Subtarget
.
getTargetABI
(
)
)
{
default
:
llvm_unreachable
(
"Unrecognized ABI"
)
;
case
RISCVABI
::
ABI_ILP32
:
case
RISCVABI
::
ABI_LP64
:
return
CSR_ILP32_LP64_RegMask
;
case
RISCVABI
::
ABI_ILP32F
:
case
RISCVABI
::
ABI_LP64F
:
return
CSR_ILP32F_LP64F_RegMask
;
case
RISCVABI
::
ABI_ILP32D
:
case
RISCVABI
::
ABI_LP64D
:
return
CSR_ILP32D_LP64D_RegMask
;
}
}
</s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static inline bool offset_9bit_signed_unscaled_p ( machine_mode mode ATTRIBUTE_UNUSED , poly_int64 offset ) { HOST_WIDE_INT const_offset ; return ( offset . is_constant ( & const_offset ) && IN_RANGE ( const_offset , - 256 , 255 ) ) ; } </s>

Return true if OFFSET is a signed 9-bit value .


"Encountered a global variable kind that is "

Emit the specified global variable to the .s file .


<s> static unsigned int mips_get_compress_mode ( tree decl ) { unsigned int flags , force_on ; flags = mips_base_compression_flags ; if ( decl ) { tree parent = decl_function_context ( decl ) ; if ( parent ) decl = parent ; force_on = mips_get_compress_on_flags ( DECL_ATTRIBUTES ( decl ) ) ; if ( force_on ) return force_on ; flags &= ~ mips_get_compress_off_flags ( DECL_ATTRIBUTES ( decl ) ) ; } return flags ; } </s>

Return the compression mode that should be used for function DECL . Return the ambient setting if DECL is null .


Output a pattern for a move instruction .


<s> static bool loongarch_can_change_mode_class ( machine_mode , machine_mode , reg_class_t rclass ) { return ! reg_classes_intersect_p ( FP_REGS , rclass ) ; } </s>


<s> static machine_mode promote_arg ( machine_mode mode , bool prototyped ) { if ( ! prototyped && mode == SFmode ) mode = DFmode ; else if ( GET_MODE_SIZE ( mode ) < GET_MODE_SIZE ( SImode ) ) mode = SImode ; return mode ; } </s>

A non-memory argument of mode MODE is being passed , determine the mode it should be promoted to . This is also used for determining return type promotion .


<s> static unsigned int rest_of_insert_bti ( void ) { timevar_push ( TV_MACH_DEP ) ; rtx bti_insn ; rtx_insn * insn ; basic_block bb ; if ( ! cgraph_node :: get ( cfun -> decl ) -> only_called_directly_p ( ) ) { bb = ENTRY_BLOCK_PTR_FOR_FN ( cfun ) -> next_bb ; insn = BB_HEAD ( bb ) ; if ( ! aarch64_pac_insn_p ( get_first_nonnote_insn ( ) ) ) { bti_insn = gen_bti_c ( ) ; emit_insn_before ( bti_insn , insn ) ; } } bb = 0 ; FOR_EACH_BB_FN ( bb , cfun ) { for ( insn = BB_HEAD ( bb ) ; insn != NEXT_INSN ( BB_END ( bb ) ) ; insn = NEXT_INSN ( insn ) ) { if ( ( LABEL_P ( insn ) && ( LABEL_PRESERVE_P ( insn ) || bb -> flags & BB_NON_LOCAL_GOTO_TARGET ) ) || ( NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_DELETED_LABEL ) ) { bti_insn = gen_bti_j ( ) ; emit_insn_after ( bti_insn , insn ) ; continue ; } if ( JUMP_P ( insn ) ) { rtx_jump_table_data * table ; if ( tablejump_p ( insn , NULL , & table ) ) { rtvec vec = table -> get_labels ( ) ; int j ; rtx_insn * label ; for ( j = GET_NUM_ELEM ( vec ) - 1 ; j >= 0 ; -- j ) { label = as_a < rtx_insn * > ( XEXP ( RTVEC_ELT ( vec , j ) , 0 ) ) ; bti_insn = gen_bti_j ( ) ; emit_insn_after ( bti_insn , label ) ; } } } if ( CALL_P ( insn ) && ( find_reg_note ( insn , REG_SETJMP , NULL ) ) ) { bti_insn = gen_bti_j ( ) ; emit_insn_after ( bti_insn , insn ) ; continue ; } } } timevar_pop ( TV_MACH_DEP ) ; return 0 ; } </s>

This is implemented as a late RTL pass that runs before branch shortening and does the following .


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , int64_t NumBytes , bool Is64Bit , const TargetInstrInfo & TII , const TargetRegisterInfo & TRI ) { bool isSub = NumBytes < 0 ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; unsigned Opc = isSub ? getSUBriOpcode ( Is64Bit , Offset ) : getADDriOpcode ( Is64Bit , Offset ) ; uint64_t Chunk = ( 1LL << 31 ) - 1 ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; if ( ThisVal == ( Is64Bit ? 8 : 4 ) ) { unsigned Reg = isSub ? ( unsigned ) ( Is64Bit ? X86 :: RAX : X86 :: EAX ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { Opc = isSub ? ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) : ( Is64Bit ? X86 :: POP64r : X86 :: POP32r ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ; Offset -= ThisVal ; continue ; } } MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( ThisVal ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


"AMD IL Control Flow Graph structurizer Pass"

getPassName - Return a nice clean name for a pass .


"internal error: builtin function %qs already processed"

Add a SPARC builtin function with NAME , ICODE , CODE and TYPE . Return the function decl or NULL_TREE if the builtin was not added .


<s> void AMDGPUPassConfig :: addIRPasses ( ) { const AMDGPUTargetMachine & TM = getAMDGPUTargetMachine ( ) ; disablePass ( & StackMapLivenessID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & PatchableFunctionID ) ; addPass ( createAMDGPULowerIntrinsicsPass ( & TM ) ) ; addPass ( createAMDGPUAlwaysInlinePass ( ) ) ; addPass ( createAlwaysInlinerLegacyPass ( ) ) ; addPass ( createBarrierNoopPass ( ) ) ; if ( TM . getTargetTriple ( ) . getArch ( ) == Triple :: amdgcn ) { addPass ( createAMDGPUCodeGenPreparePass ( static_cast < const GCNTargetMachine * > ( & TM ) ) ) ; } addPass ( createAMDGPUOpenCLImageTypeLoweringPass ( ) ) ; if ( TM . getOptLevel ( ) > CodeGenOpt :: None ) { addPass ( createInferAddressSpacesPass ( ) ) ; addPass ( createAMDGPUPromoteAlloca ( & TM ) ) ; if ( EnableSROA ) addPass ( createSROAPass ( ) ) ; addStraightLineScalarOptimizationPasses ( ) ; if ( EnableAMDGPUAliasAnalysis ) { addPass ( createAMDGPUAAWrapperPass ( ) ) ; addPass ( createExternalAAWrapperPass ( [ ] ( Pass & P , Function & , AAResults & AAR ) { if ( auto * WrapperPass = P . getAnalysisIfAvailable < AMDGPUAAWrapperPass > ( ) ) AAR . addAAResult ( WrapperPass -> getResult ( ) ) ; } ) ) ; } } TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addEarlyCSEOrGVNPass ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU


<s> void sparc_emit_fixunsdi ( rtx * operands , machine_mode mode ) { rtx i0 , i1 , f0 , in , out , limit ; out = operands [ 0 ] ; in = force_reg ( mode , operands [ 1 ] ) ; rtx_code_label * neglab = gen_label_rtx ( ) ; rtx_code_label * donelab = gen_label_rtx ( ) ; i0 = gen_reg_rtx ( DImode ) ; i1 = gen_reg_rtx ( DImode ) ; limit = gen_reg_rtx ( mode ) ; f0 = gen_reg_rtx ( mode ) ; emit_move_insn ( limit , const_double_from_real_value ( REAL_VALUE_ATOF ( "9223372036854775808.0" , mode ) , mode ) ) ; emit_cmp_and_jump_insns ( in , limit , GE , NULL_RTX , mode , 0 , neglab ) ; emit_insn ( gen_rtx_SET ( out , gen_rtx_FIX ( DImode , gen_rtx_FIX ( mode , in ) ) ) ) ; emit_jump_insn ( gen_jump ( donelab ) ) ; emit_barrier ( ) ; emit_label ( neglab ) ; emit_insn ( gen_rtx_SET ( f0 , gen_rtx_MINUS ( mode , in , limit ) ) ) ; emit_insn ( gen_rtx_SET ( i0 , gen_rtx_FIX ( DImode , gen_rtx_FIX ( mode , f0 ) ) ) ) ; emit_insn ( gen_movdi ( i1 , const1_rtx ) ) ; emit_insn ( gen_ashldi3 ( i1 , i1 , GEN_INT ( 63 ) ) ) ; emit_insn ( gen_xordi3 ( out , i0 , i1 ) ) ; emit_label ( donelab ) ; } </s>

Generate an FP to unsigned DImode conversion . This is the same code optabs would emit if we did n't have TFmode patterns .


<s> static int frv_compare_insns ( const void * first , const void * second ) { const rtx * insn1 = first , * insn2 = second ; return frv_insn_unit ( * insn1 ) - frv_insn_unit ( * insn2 ) ; } </s>

Compare two instructions by their frv_insn_unit .


<s> int ix86_use_fcomi_compare ( enum rtx_code code ATTRIBUTE_UNUSED ) { enum rtx_code swapped_code = swap_condition ( code ) ; return ( ( ix86_fp_comparison_cost ( code ) == ix86_fp_comparison_fcomi_cost ( code ) ) || ( ix86_fp_comparison_cost ( swapped_code ) == ix86_fp_comparison_fcomi_cost ( swapped_code ) ) ) ; } </s>

Return true if we should use an FCOMI instruction for this fp comparison .


<s> static int mergeSPUpdates ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , bool doMergeWithPrevious ) { if ( ( doMergeWithPrevious && MBBI == MBB . begin ( ) ) || ( ! doMergeWithPrevious && MBBI == MBB . end ( ) ) ) return 0 ; MachineBasicBlock :: iterator PI = doMergeWithPrevious ? prior ( MBBI ) : MBBI ; MachineBasicBlock :: iterator NI = doMergeWithPrevious ? 0 : llvm :: next ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = 0 ; if ( ( Opc == X86 :: ADD64ri32 || Opc == X86 :: ADD64ri8 || Opc == X86 :: ADD32ri || Opc == X86 :: ADD32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { Offset += PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == X86 :: SUB64ri32 || Opc == X86 :: SUB64ri8 || Opc == X86 :: SUB32ri || Opc == X86 :: SUB32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { Offset -= PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } return Offset ; } </s>

Check the instruction before/after the passed instruction .


"%Jdata area attributes cannot be specified for "

"data area of %q+D conflicts with previous declaration"

Handle a `` sda '' , `` tda '' or `` zda '' attribute ; arguments as in struct attribute_spec.handler .


"@c Copyright (C) 2012-2018 Free Software Foundation, Inc.\n"

"@c For copying conditions, see the file "

"@c This file is generated automatically using\n"

Main program to convert flat files into built-in initialization code .


<s> bool RISCVTargetLowering :: isDesirableToCommuteWithShift ( const SDNode * N , CombineLevel Level ) const { SDValue N0 = N -> getOperand ( 0 ) ; MVT Ty = N0 . getSimpleValueType ( ) ; if ( Ty . isScalarInteger ( ) && ( N0 . getOpcode ( ) == ISD :: ADD || N0 . getOpcode ( ) == ISD :: OR ) ) { auto * C1 = dyn_cast < ConstantSDNode > ( N0 -> getOperand ( 1 ) ) ; auto * C2 = dyn_cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) ; if ( C1 && C2 ) { APInt C1Int = C1 -> getAPIntValue ( ) ; APInt ShiftedC1Int = C1Int << C2 -> getAPIntValue ( ) ; if ( isLegalAddImmediate ( ShiftedC1Int . getSExtValue ( ) ) ) return true ; if ( isLegalAddImmediate ( C1Int . getSExtValue ( ) ) ) return false ; int C1Cost = RISCVMatInt :: getIntMatCost ( C1Int , Ty . getSizeInBits ( ) , Subtarget . is64Bit ( ) ) ; int ShiftedC1Cost = RISCVMatInt :: getIntMatCost ( ShiftedC1Int , Ty . getSizeInBits ( ) , Subtarget . is64Bit ( ) ) ; if ( C1Cost < ShiftedC1Cost ) return false ; } } return true ; } </s>

Return true if it is profitable to move this shift by a constant amount through its operand , adjusting any immediate operands as necessary to preserve semantics .

RISCV RISCV 0 ISD::ADD ISD::OR 1 1 RISCVMatInt::getIntMatCost RISCVMatInt::getIntMatCost


<s> unsigned stackAlignment ( ) const { return 8 ; } </s>

The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function .


<s> CCAssignFn * MipsTargetLowering :: CCAssignFnForCall ( ) const { return CC_Mips ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> const LanaiRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool PPCAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , O ) ; case 'c' : break ; case 'L' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + 1 == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + 1 ) . isReg ( ) ) return true ; ++ OpNo ; break ; case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << "i" ; return false ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> SDValue MipsSETargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; SDValue Val ; switch ( N -> getOpcode ( ) ) { case ISD :: ADDE : return performADDECombine ( N , DAG , DCI , Subtarget ) ; case ISD :: AND : Val = performANDCombine ( N , DAG , DCI , Subtarget ) ; break ; case ISD :: SUBE : return performSUBECombine ( N , DAG , DCI , Subtarget ) ; case ISD :: MUL : return performMULCombine ( N , DAG , DCI , this ) ; case ISD :: SHL : return performSHLCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SRA : return performSRACombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SRL : return performSRLCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: VSELECT : return performVSELECTCombine ( N , DAG ) ; case ISD :: XOR : Val = performXORCombine ( N , DAG , Subtarget ) ; break ; case ISD :: SETCC : Val = performSETCCCombine ( N , DAG ) ; break ; } if ( Val . getNode ( ) ) return Val ; return MipsTargetLowering :: PerformDAGCombine ( N , DCI ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips Mips ISD::ADDE ISD::AND ISD::SUBE ISD::MUL ISD::SHL ISD::SRA ISD::SRL ISD::VSELECT ISD::XOR ISD::SETCC Mips


<s> static bool microblaze_valid_base_register_p ( rtx x , machine_mode mode ATTRIBUTE_UNUSED , int strict ) { if ( ! strict && GET_CODE ( x ) == SUBREG ) x = SUBREG_REG ( x ) ; return ( GET_CODE ( x ) == REG && microblaze_regno_ok_for_base_p ( REGNO ( x ) , strict ) ) ; } </s>

Return true if X is a valid base register for the given mode . Allow only hard registers if STRICT .


<s>
static
void
segv_crash_handler
(
int
sig
ATTRIBUTE_UNUSED
)
{
internal_error
(
"Segmentation Fault (code)"
)
;
}
</s>

On Darwin/powerpc , hitting the stack limit turns into a SIGSEGV . This code detects the difference between hitting the stack limit and a true wild pointer dereference by looking at the instruction that faulted ; only a few kinds of instruction are used to access below the previous bottom of the stack .


<s> unsigned HexagonTTIImpl :: getPrefetchDistance ( ) const { return ST . getL1PrefetchDistance ( ) ; } </s>

Return the preferred prefetch distance in terms of instructions .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
Kind
==
Register
&&
"Invalid type access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s> bool X86AsmBackend :: mayNeedRelaxation ( const MCInst & Inst ) const { if ( getRelaxedOpcodeBranch ( Inst . getOpcode ( ) ) != Inst . getOpcode ( ) ) return true ; if ( getRelaxedOpcodeArith ( Inst . getOpcode ( ) ) == Inst . getOpcode ( ) ) return false ; unsigned RelaxableOp = Inst . getNumOperands ( ) - 1 ; if ( Inst . getOperand ( RelaxableOp ) . isExpr ( ) ) return true ; return false ; } </s>

Check whether the given instruction may need relaxation .


<s> void Z80oldRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { MachineFunction & MF = * MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock :: iterator II = MBB -> begin ( ) ; DebugLoc DL = MBB -> findDebugLoc ( II ) ; MRI . setRegClass ( BaseReg , & Z80old :: IR16RegClass ) ; BuildMI ( * MBB , II , DL , TII . get ( Z80old :: LD88ro ) , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ; return ; unsigned CopyReg = MRI . createVirtualRegister ( & Z80old :: IR16RegClass ) ; unsigned OffsetReg = MRI . createVirtualRegister ( & Z80old :: OR16RegClass ) ; BuildMI ( * MBB , II , DL , TII . get ( TargetOpcode :: COPY ) , CopyReg ) . addReg ( getFrameRegister ( MF ) ) ; BuildMI ( * MBB , II , DL , TII . get ( Z80old :: LD16ri ) , OffsetReg ) . addImm ( Offset ) ; BuildMI ( * MBB , II , DL , TII . get ( Z80old :: ADD16ao ) , BaseReg ) . addReg ( CopyReg ) . addReg ( OffsetReg ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .


<s> bool AMDGPUInstructionSelector :: select ( MachineInstr & I , CodeGenCoverage & CoverageInfo ) const { if ( I . isPHI ( ) ) return selectPHI ( I ) ; if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) { if ( I . isCopy ( ) ) return selectCOPY ( I ) ; return true ; } switch ( I . getOpcode ( ) ) { case TargetOpcode :: G_AND : case TargetOpcode :: G_OR : case TargetOpcode :: G_XOR : if ( selectG_AND_OR_XOR ( I ) ) return true ; return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_ADD : case TargetOpcode :: G_SUB : if ( selectG_ADD_SUB ( I ) ) return true ; LLVM_FALLTHROUGH ; default : return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_INTTOPTR : case TargetOpcode :: G_BITCAST : return selectCOPY ( I ) ; case TargetOpcode :: G_CONSTANT : case TargetOpcode :: G_FCONSTANT : return selectG_CONSTANT ( I ) ; case TargetOpcode :: G_EXTRACT : return selectG_EXTRACT ( I ) ; case TargetOpcode :: G_MERGE_VALUES : case TargetOpcode :: G_BUILD_VECTOR : case TargetOpcode :: G_CONCAT_VECTORS : return selectG_MERGE_VALUES ( I ) ; case TargetOpcode :: G_UNMERGE_VALUES : return selectG_UNMERGE_VALUES ( I ) ; case TargetOpcode :: G_GEP : return selectG_GEP ( I ) ; case TargetOpcode :: G_IMPLICIT_DEF : return selectG_IMPLICIT_DEF ( I ) ; case TargetOpcode :: G_INSERT : return selectG_INSERT ( I ) ; case TargetOpcode :: G_INTRINSIC : return selectG_INTRINSIC ( I , CoverageInfo ) ; case TargetOpcode :: G_INTRINSIC_W_SIDE_EFFECTS : return selectG_INTRINSIC_W_SIDE_EFFECTS ( I , CoverageInfo ) ; case TargetOpcode :: G_ICMP : if ( selectG_ICMP ( I ) ) return true ; return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_LOAD : return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_SELECT : return selectG_SELECT ( I ) ; case TargetOpcode :: G_STORE : if ( selectImpl ( I , CoverageInfo ) ) return true ; return selectG_STORE ( I ) ; case TargetOpcode :: G_TRUNC : return selectG_TRUNC ( I ) ; case TargetOpcode :: G_SEXT : case TargetOpcode :: G_ZEXT : case TargetOpcode :: G_ANYEXT : if ( selectG_SZA_EXT ( I ) ) { I . eraseFromParent ( ) ; return true ; } return false ; case TargetOpcode :: G_BRCOND : return selectG_BRCOND ( I ) ; case TargetOpcode :: G_FRAME_INDEX : return selectG_FRAME_INDEX ( I ) ; case TargetOpcode :: G_FENCE : I . setDesc ( TII . get ( AMDGPU :: ATOMIC_FENCE ) ) ; return true ; } return false ; } </s>

Select the ( possibly generic ) instruction I to only use target-specific opcodes .

AMDGPU AMDGPU SI SI SI SI AMDGPU::ATOMIC_FENCE


<s>
bool
AArch64InstrInfo
::
isGPRZero
(
const
MachineInstr
*
MI
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
AArch64
::
MOVZWi
:
case
AArch64
::
MOVZXi
:
if
(
MI
->
getOperand
(
1
)
.
isImm
(
)
&&
MI
->
getOperand
(
1
)
.
getImm
(
)
==
0
)
{
assert
(
MI
->
getDesc
(
)
.
getNumOperands
(
)
==
3
&&
MI
->
getOperand
(
2
)
.
getImm
(
)
==
0
&&
"invalid MOVZi operands"
)
;
return
true
;
}
break
;
case
AArch64
::
ANDWri
:
return
MI
->
getOperand
(
1
)
.
getReg
(
)
==
AArch64
::
WZR
;
case
AArch64
::
ANDXri
:
return
MI
->
getOperand
(
1
)
.
getReg
(
)
==
AArch64
::
XZR
;
case
TargetOpcode
::
COPY
:
return
MI
->
getOperand
(
1
)
.
getReg
(
)
==
AArch64
::
WZR
;
}
return
false
;
}
</s>

Does this instruction set its full destination register to zero ?


Implement TARGET_SECONDARY_MEMORY_NEEDED . If we are copying between general and FP registers , we need a memory location unless the FIX extension is available .


<s> BitVector R600RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const R600InstrInfo * TII = static_cast < const R600InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; Reserved . set ( AMDGPU :: ZERO ) ; Reserved . set ( AMDGPU :: HALF ) ; Reserved . set ( AMDGPU :: ONE ) ; Reserved . set ( AMDGPU :: ONE_INT ) ; Reserved . set ( AMDGPU :: NEG_HALF ) ; Reserved . set ( AMDGPU :: NEG_ONE ) ; Reserved . set ( AMDGPU :: PV_X ) ; Reserved . set ( AMDGPU :: ALU_LITERAL_X ) ; Reserved . set ( AMDGPU :: ALU_CONST ) ; Reserved . set ( AMDGPU :: PREDICATE_BIT ) ; Reserved . set ( AMDGPU :: PRED_SEL_OFF ) ; Reserved . set ( AMDGPU :: PRED_SEL_ZERO ) ; Reserved . set ( AMDGPU :: PRED_SEL_ONE ) ; Reserved . set ( AMDGPU :: INDIRECT_BASE_ADDR ) ; for ( TargetRegisterClass :: iterator I = AMDGPU :: R600_AddrRegClass . begin ( ) , E = AMDGPU :: R600_AddrRegClass . end ( ) ; I != E ; ++ I ) { Reserved . set ( * I ) ; } TII -> reserveIndirectRegisters ( Reserved , MF ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool AArch64TargetLowering :: isExtractSubvectorCheap ( EVT ResVT , EVT SrcVT , unsigned Index ) const { if ( ! isOperationLegalOrCustom ( ISD :: EXTRACT_SUBVECTOR , ResVT ) ) return false ; return ( Index == 0 || Index == ResVT . getVectorMinNumElements ( ) ) ; } </s>

Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index .


<s> static HOST_WIDE_INT ix86_static_rtx_alignment ( machine_mode mode ) { if ( mode == DFmode ) return 64 ; if ( ALIGN_MODE_128 ( mode ) ) return MAX ( 128 , GET_MODE_ALIGNMENT ( mode ) ) ; return GET_MODE_ALIGNMENT ( mode ) ; } </s>


<s> int sparc_flat_epilogue_delay_slots ( ) { if ( ! current_frame_info . initialized ) ( void ) sparc_flat_compute_frame_size ( get_frame_size ( ) ) ; if ( current_frame_info . total_size == 0 ) return 1 ; return 0 ; } </s>

Define the number of delay slots needed for the function epilogue . On the sparc , we need a slot if either no stack has been allocated , or the only register saved is the return register .


<s> std :: unique_ptr < MCObjectWriter > createObjectWriter ( raw_pwrite_stream & OS ) const override { return createSystemZObjectWriter ( OS , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> bool AVRAsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : return false ; case AVR :: fixup_7_pcrel : case AVR :: fixup_13_pcrel : case AVR :: fixup_call : return true ; } } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> static rtx nvptx_libcall_value ( machine_mode mode , const_rtx ) { if ( ! cfun -> machine -> doing_call ) return gen_rtx_REG ( mode , NVPTX_RETURN_REGNUM ) ; return gen_reg_rtx ( mode ) ; } </s>


<s> static rtx_insn * nds32_md_asm_adjust ( vec < rtx > & outputs ATTRIBUTE_UNUSED , vec < rtx > & inputs ATTRIBUTE_UNUSED , vec < const char * > & constraints ATTRIBUTE_UNUSED , vec < rtx > & clobbers , HARD_REG_SET & clobbered_regs ) { clobbers . safe_push ( gen_rtx_REG ( SImode , TA_REGNUM ) ) ; SET_HARD_REG_BIT ( clobbered_regs , TA_REGNUM ) ; return NULL ; } </s>


<s> bool AMDGPUAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { OW -> WriteZeros ( Count % 4 ) ; Count /= 4 ; const uint32_t Encoded_S_NOP_0 = 0xbf800000 ; for ( uint64_t I = 0 ; I != Count ; ++ I ) OW -> write32 ( Encoded_S_NOP_0 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> bool PPCFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( ! Subtarget . isSVR4ABI ( ) ) return false ; MachineFunction * MF = MBB . getParent ( ) ; const PPCInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc DL ; bool CRSpilled = false ; MachineInstrBuilder CRMIB ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg == PPC :: VRSAVE && ! Subtarget . isDarwinABI ( ) ) continue ; bool IsCRField = PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ; const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; bool IsLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! IsLiveIn ) MBB . addLiveIn ( Reg ) ; if ( CRSpilled && IsCRField ) { CRMIB . addReg ( Reg , RegState :: ImplicitKill ) ; continue ; } if ( IsCRField ) { PPCFunctionInfo * FuncInfo = MF -> getInfo < PPCFunctionInfo > ( ) ; if ( Subtarget . isPPC64 ( ) ) { FuncInfo -> addMustSaveCR ( Reg ) ; } else { CRSpilled = true ; FuncInfo -> setSpillsCR ( ) ; CRMIB = BuildMI ( * MF , DL , TII . get ( PPC :: MFCR ) , PPC :: R12 ) . addReg ( Reg , RegState :: ImplicitKill ) ; MBB . insert ( MI , CRMIB ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( PPC :: STW ) ) . addReg ( PPC :: R12 , getKillRegState ( true ) ) , CSI [ i ] . getFrameIdx ( ) ) ) ; } } else { if ( CSI [ i ] . isSpilledToReg ( ) ) { NumPESpillVSR ++ ; BuildMI ( MBB , MI , DL , TII . get ( PPC :: MTVSRD ) , CSI [ i ] . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , ! IsLiveIn , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .

PowerPC PPC PPC 0 PPC::VRSAVE PPC::CR2 PPC::CR4 PPC PPC PPC PPC::MFCR PPC::R12 PPC::STW PPC::R12 PPC::MTVSRD


<s> void MipsInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << '$' << LowercaseString ( getRegisterName ( RegNo ) ) ; } </s>


<s> void HexagonPassConfig :: addPreEmitPass ( ) { bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) addPass ( createHexagonNewValueJump ( ) ) ; addPass ( createHexagonBranchRelaxation ( ) ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( createHexagonFixupHwLoops ( ) ) ; if ( EnableGenMux ) addPass ( createHexagonGenMux ( ) ) ; addPass ( createHexagonPacketizer ( ) , false ) ; } if ( EnableVectorPrint ) addPass ( createHexagonVectorPrint ( ) , false ) ; addPass ( createHexagonCallFrameInformation ( ) , false ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon


<s> SDValue NyuziTargetLowering :: getAddr ( const NodeTy * N , SelectionDAG & DAG ) const { SDLoc DL ( N ) ; EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; if ( isPositionIndependent ( ) ) { SDValue GPReg = DAG . getRegister ( Nyuzi :: GP_REG , MVT :: i32 ) ; SDValue Wrapper = DAG . getNode ( NyuziISD :: GOT_ADDR , DL , Ty , GPReg , getTargetNode ( N , Ty , DAG , Nyuzi :: MO_GOT ) ) ; return DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , Wrapper , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; } else { SDValue Hi = getTargetNode ( N , Ty , DAG , Nyuzi :: MO_ABS_HI ) ; SDValue Lo = getTargetNode ( N , Ty , DAG , Nyuzi :: MO_ABS_LO ) ; SDValue MoveHi = DAG . getNode ( NyuziISD :: MOVEHI , DL , MVT :: i32 , Hi ) ; return DAG . getNode ( NyuziISD :: ORLO , DL , MVT :: i32 , MoveHi , Lo ) ; } } </s>

Return the address accessed by this recipe .


<s>
SDValue
LanaiTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
switch
(
CallConv
)
{
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
IsVarArg
,
Ins
,
DL
,
DAG
,
InVals
)
;
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .

Lanai
Lanai
ISD::InputArg
"Unsupported calling convention"


<s> SDValue MipsTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; unsigned opc = N -> getOpcode ( ) ; switch ( opc ) { default : break ; case ISD :: ADDE : return PerformADDECombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SUBE : return PerformSUBECombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SDIVREM : case ISD :: UDIVREM : return PerformDivRemCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips Mips ISD::ADDE ISD::SUBE ISD::SDIVREM ISD::UDIVREM


<s> void rs6000_emit_le_vsx_load ( rtx dest , rtx source , machine_mode mode ) { if ( mode == TImode || mode == V1TImode ) { mode = V2DImode ; dest = gen_lowpart ( V2DImode , dest ) ; source = adjust_address ( source , V2DImode , 0 ) ; } rtx tmp = can_create_pseudo_p ( ) ? gen_reg_rtx_and_attrs ( dest ) : dest ; rs6000_emit_le_vsx_permute ( tmp , source , mode ) ; rs6000_emit_le_vsx_permute ( dest , tmp , mode ) ; } </s>

Emit a little-endian load from vector memory location SOURCE to VSX register DEST in mode MODE . The load is done with two permuting insn 's that represent an lxvd2x and xxpermdi .


<s> bool AArch64InstrInfo :: analyzeCompare ( const MachineInstr * MI , unsigned & SrcReg , unsigned & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case AArch64 :: SUBSWrr : case AArch64 :: SUBSWrs : case AArch64 :: SUBSWrx : case AArch64 :: SUBSXrr : case AArch64 :: SUBSXrs : case AArch64 :: SUBSXrx : case AArch64 :: ADDSWrr : case AArch64 :: ADDSWrs : case AArch64 :: ADDSWrx : case AArch64 :: ADDSXrr : case AArch64 :: ADDSXrs : case AArch64 :: ADDSXrx : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; SrcReg2 = MI -> getOperand ( 2 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case AArch64 :: SUBSWri : case AArch64 :: ADDSWri : case AArch64 :: SUBSXri : case AArch64 :: ADDSXri : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = ( MI -> getOperand ( 2 ) . getImm ( ) != 0 ) ; return true ; case AArch64 :: ANDSWri : case AArch64 :: ANDSXri : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = ( AArch64_AM :: decodeLogicalImmediate ( MI -> getOperand ( 2 ) . getImm ( ) , MI -> getOpcode ( ) == AArch64 :: ANDSWri ? 32 : 64 ) != 0 ) ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> void LanaiFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const LanaiRegisterInfo * LRI = STI . getRegisterInfo ( ) ; unsigned FrameSize = MFI . getStackSize ( ) ; Align StackAlign = LRI -> needsStackRealignment ( MF ) ? MFI . getMaxAlign ( ) : getStackAlign ( ) ; unsigned MaxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; if ( MFI . hasVarSizedObjects ( ) ) MaxCallFrameSize = alignTo ( MaxCallFrameSize , StackAlign ) ; MFI . setMaxCallFrameSize ( MaxCallFrameSize ) ; if ( ! ( hasReservedCallFrame ( MF ) && MFI . adjustsStack ( ) ) ) FrameSize += MaxCallFrameSize ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI . setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s> void VEAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { switch ( MI -> getOpcode ( ) ) { default : break ; case TargetOpcode :: DBG_VALUE : return ; } MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { MCInst TmpInst ; LowerVEMachineInstrToMCInst ( & * I , TmpInst , * this ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } while ( ( ++ I != E ) && I -> isInsideBundle ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> unsigned PIC16InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == PIC16 :: movf && MI -> getOperand ( 0 ) . isReg ( ) && MI -> getOperand ( 1 ) . isSymbol ( ) ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> static unsigned HOST_WIDE_INT compute_current_alignment ( unsigned HOST_WIDE_INT base_align , unsigned HOST_WIDE_INT offset ) { if ( offset == 0 ) return base_align ; return MIN ( base_align , offset & - offset ) ; } </s>

Compute the alignment of pointer+OFFSET where the original alignment of pointer was BASE_ALIGN .


<s>
bool
AArch64DAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_o
:
case
InlineAsm
::
Constraint_Q
:
const
TargetRegisterInfo
*
TRI
=
Subtarget
->
getRegisterInfo
(
)
;
const
TargetRegisterClass
*
TRC
=
TRI
->
getPointerRegClass
(
*
MF
)
;
SDLoc
dl
(
Op
)
;
SDValue
RC
=
CurDAG
->
getTargetConstant
(
TRC
->
getID
(
)
,
dl
,
MVT
::
i64
)
;
SDValue
NewOp
=
SDValue
(
CurDAG
->
getMachineNode
(
TargetOpcode
::
COPY_TO_REGCLASS
,
dl
,
Op
.
getValueType
(
)
,
Op
,
RC
)
,
0
)
;
OutOps
.
push_back
(
NewOp
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> void SITargetLowering :: AdjustInstrPostInstrSelection ( MachineInstr & MI , SDNode * Node ) const { const SIInstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; if ( TII -> isVOP3 ( MI . getOpcode ( ) ) ) { TII -> legalizeOperandsVOP3 ( MRI , MI ) ; if ( const MCOperandInfo * OpInfo = MI . getDesc ( ) . OpInfo ) { unsigned Opc = MI . getOpcode ( ) ; const SIRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; for ( auto I : { AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src0 ) , AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src1 ) } ) { if ( I == - 1 ) break ; MachineOperand & Op = MI . getOperand ( I ) ; if ( ( OpInfo [ I ] . RegClass != llvm :: AMDGPU :: AV_64RegClassID && OpInfo [ I ] . RegClass != llvm :: AMDGPU :: AV_32RegClassID ) || ! TargetRegisterInfo :: isVirtualRegister ( Op . getReg ( ) ) || ! TRI -> isAGPR ( MRI , Op . getReg ( ) ) ) continue ; auto * Src = MRI . getUniqueVRegDef ( Op . getReg ( ) ) ; if ( ! Src || ! Src -> isCopy ( ) || ! TRI -> isSGPRReg ( MRI , Src -> getOperand ( 1 ) . getReg ( ) ) ) continue ; auto * RC = TRI -> getRegClassForReg ( MRI , Op . getReg ( ) ) ; auto * NewRC = TRI -> getEquivalentVGPRClass ( RC ) ; MRI . setRegClass ( Op . getReg ( ) , NewRC ) ; } } return ; } int NoRetAtomicOp = AMDGPU :: getAtomicNoRetOp ( MI . getOpcode ( ) ) ; if ( NoRetAtomicOp != - 1 ) { if ( ! Node -> hasAnyUseOfValue ( 0 ) ) { MI . setDesc ( TII -> get ( NoRetAtomicOp ) ) ; MI . RemoveOperand ( 0 ) ; return ; } if ( ( Node -> hasNUsesOfValue ( 1 , 0 ) && Node -> use_begin ( ) -> isMachineOpcode ( ) && Node -> use_begin ( ) -> getMachineOpcode ( ) == AMDGPU :: EXTRACT_SUBREG && ! Node -> use_begin ( ) -> hasAnyUseOfValue ( 0 ) ) ) { unsigned Def = MI . getOperand ( 0 ) . getReg ( ) ; MI . setDesc ( TII -> get ( NoRetAtomicOp ) ) ; MI . RemoveOperand ( 0 ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , TII -> get ( AMDGPU :: IMPLICIT_DEF ) , Def ) ; } return ; } } </s>

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


<s> static bool rs6000_slow_unaligned_access ( machine_mode mode , unsigned int align ) { return ( STRICT_ALIGNMENT || ( ! TARGET_EFFICIENT_UNALIGNED_VSX && ( ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( mode ) && align < 32 ) || ( ( VECTOR_MODE_P ( mode ) || VECTOR_ALIGNMENT_P ( mode ) ) && ( int ) align < VECTOR_ALIGN ( mode ) ) ) ) ) ; } </s>

Implement TARGET_SLOW_UNALIGNED_ACCESS . Altivec vector memory instructions simply ignore the low bits ; VSX memory instructions are aligned to 4 or 8 bytes .


<s> bool PPCRegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , unsigned Reg , int & FrameIdx ) const { const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; if ( Subtarget . isSVR4ABI ( ) && PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ) { FrameIdx = MF . getInfo < PPCFunctionInfo > ( ) -> getCRSpillFrameIndex ( ) ; return true ; } return false ; } </s>

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register .

PowerPC PPC PPC PPC PPC::CR2 PPC::CR4 PPC


<s> static rtx legitimize_pic_address ( rtx orig , rtx reg , rtx picreg ) { rtx addr = orig ; rtx new_rtx = orig ; if ( GET_CODE ( addr ) == SYMBOL_REF || GET_CODE ( addr ) == LABEL_REF ) { int unspec = UNSPEC_LOAD_GOT ; rtx tmp ; if ( reg == 0 ) { gcc_assert ( can_create_pseudo_p ( ) ) ; reg = gen_reg_rtx ( Pmode ) ; } if ( flag_pic == 2 ) { if ( can_create_pseudo_p ( ) ) tmp = gen_reg_rtx ( Pmode ) ; else tmp = reg ; emit_insn ( gen_movsi_gotoff_high ( tmp , addr ) ) ; emit_insn ( gen_movsi_gotoff_lo_sum ( tmp , tmp , addr ) ) ; emit_insn ( gen_load_got_gotoff ( reg , picreg , tmp ) ) ; } else { tmp = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , addr ) , unspec ) ; new_rtx = gen_const_mem ( Pmode , gen_rtx_PLUS ( Pmode , picreg , tmp ) ) ; emit_move_insn ( reg , new_rtx ) ; } if ( picreg == pic_offset_table_rtx ) crtl -> uses_pic_offset_table = 1 ; return reg ; } else if ( GET_CODE ( addr ) == CONST || GET_CODE ( addr ) == PLUS ) { rtx base ; if ( GET_CODE ( addr ) == CONST ) { addr = XEXP ( addr , 0 ) ; gcc_assert ( GET_CODE ( addr ) == PLUS ) ; } if ( XEXP ( addr , 0 ) == picreg ) return orig ; if ( reg == 0 ) { gcc_assert ( can_create_pseudo_p ( ) ) ; reg = gen_reg_rtx ( Pmode ) ; } base = legitimize_pic_address ( XEXP ( addr , 0 ) , reg , picreg ) ; addr = legitimize_pic_address ( XEXP ( addr , 1 ) , base == reg ? NULL_RTX : reg , picreg ) ; if ( GET_CODE ( addr ) == CONST_INT ) { gcc_assert ( ! reload_in_progress && ! reload_completed ) ; addr = force_reg ( Pmode , addr ) ; } if ( GET_CODE ( addr ) == PLUS && CONSTANT_P ( XEXP ( addr , 1 ) ) ) { base = gen_rtx_PLUS ( Pmode , base , XEXP ( addr , 0 ) ) ; addr = XEXP ( addr , 1 ) ; } return gen_rtx_PLUS ( Pmode , base , addr ) ; } return new_rtx ; } </s>

Legitimize PIC addresses . If the address is already position-independent , we return ORIG . Newly generated position-independent addresses go into a reg . This is REG if nonzero , otherwise we allocate register ( s ) as necessary .


<s> bool arc_can_use_return_insn ( void ) { return ( reload_completed && cfun -> machine -> frame_info . total_size == 0 && ! ARC_INTERRUPT_P ( arc_compute_function_type ( cfun ) ) ) ; } </s>

Return nonzero if this function is known to have a null epilogue . This allows the optimizer to omit jumps to jumps if no stack was created .


<s> Value * AArch64TargetLowering :: getSafeStackPointerLocation ( IRBuilder < > & IRB ) const { if ( ! Subtarget -> isTargetAndroid ( ) ) return TargetLowering :: getSafeStackPointerLocation ( IRB ) ; const unsigned TlsOffset = 0x48 ; Module * M = IRB . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Function * ThreadPointerFunc = Intrinsic :: getDeclaration ( M , Intrinsic :: thread_pointer ) ; return IRB . CreatePointerCast ( IRB . CreateConstGEP1_32 ( IRB . CreateCall ( ThreadPointerFunc ) , TlsOffset ) , Type :: getInt8PtrTy ( IRB . getContext ( ) ) -> getPointerTo ( 0 ) ) ; } </s>

Return true if the target stores SafeStack pointer at a fixed offset in some non-standard address space , and populates the address space and offset as appropriate .


<s> static bool branch_needs_nop_p ( rtx_insn * insn ) { rtx_insn * jump_insn ; if ( dbr_sequence_length ( ) ) return FALSE ; jump_insn = next_active_insn ( JUMP_LABEL_AS_INSN ( insn ) ) ; while ( insn ) { insn = next_active_insn ( insn ) ; if ( ! insn || jump_insn == insn ) return TRUE ; if ( ! ( GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT || asm_noperands ( PATTERN ( insn ) ) >= 0 ) && get_attr_length ( insn ) > 0 ) break ; } return FALSE ; } </s>

Return TRUE if INSN , a forward jump insn , needs a nop in its delay slot . This occurs when INSN has an unfilled delay slot and is followed by an asm . Disaster can occur if the asm is empty and the jump branches into the delay slot . So , we add a nop in the delay slot when this occurs .


<s> EVT X86TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , const AttributeList & FuncAttributes ) const { if ( ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { if ( Size >= 16 && ( ! Subtarget . isUnalignedMem16Slow ( ) || ( ( DstAlign == 0 || DstAlign >= 16 ) && ( SrcAlign == 0 || SrcAlign >= 16 ) ) ) ) { if ( Size >= 32 && Subtarget . hasAVX ( ) && ( Subtarget . getPreferVectorWidth ( ) >= 256 ) ) { return MVT :: v32i8 ; } if ( Subtarget . hasSSE2 ( ) && ( Subtarget . getPreferVectorWidth ( ) >= 128 ) ) return MVT :: v16i8 ; if ( Subtarget . hasSSE1 ( ) && ( Subtarget . is64Bit ( ) || Subtarget . hasX87 ( ) ) && ( Subtarget . getPreferVectorWidth ( ) >= 128 ) ) return MVT :: v4f32 ; } else if ( ( ! IsMemset || ZeroMemset ) && ! MemcpyStrSrc && Size >= 8 && ! Subtarget . is64Bit ( ) && Subtarget . hasSSE2 ( ) ) { return MVT :: f64 ; } } if ( Subtarget . is64Bit ( ) && Size >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AsmPrinter :: getAnalysisUsage ( AU ) ; AU . setPreservesAll ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


"Can only insert epilog into returning blocks"


<s> bool AMDGPUSymbolizer :: tryAddingSymbolicOperand ( MCInst & Inst , raw_ostream & , int64_t Value , uint64_t , bool IsBranch , uint64_t , uint64_t ) { using SymbolInfoTy = std :: tuple < uint64_t , StringRef , uint8_t > ; using SectionSymbolsTy = std :: vector < SymbolInfoTy > ; if ( ! IsBranch ) { return false ; } auto * Symbols = static_cast < SectionSymbolsTy * > ( DisInfo ) ; auto Result = std :: find_if ( Symbols -> begin ( ) , Symbols -> end ( ) , [ Value ] ( const SymbolInfoTy & Val ) { return std :: get < 0 > ( Val ) == static_cast < uint64_t > ( Value ) && std :: get < 2 > ( Val ) == ELF :: STT_NOTYPE ; } ) ; if ( Result != Symbols -> end ( ) ) { auto * Sym = Ctx . getOrCreateSymbol ( std :: get < 1 > ( * Result ) ) ; const auto * Add = MCSymbolRefExpr :: create ( Sym , Ctx ) ; Inst . addOperand ( MCOperand :: createExpr ( Add ) ) ; return true ; } return false ; } </s>

Try to add a symbolic operand instead of Value to the MCInst .


<s> bool runOnModule ( Module & M ) override { SetVector < Function * > Functions ; AnalysisGetter AG ; for ( Function & F : M ) { if ( ! F . isIntrinsic ( ) ) Functions . insert ( & F ) ; } CallGraphUpdater CGUpdater ; BumpPtrAllocator Allocator ; AMDGPUInformationCache InfoCache ( M , AG , Allocator , nullptr , * TM ) ; DenseSet < const char * > Allowed ( { & AAAMDAttributes :: ID , & AAUniformWorkGroupSize :: ID , & AAAMDFlatWorkGroupSize :: ID , & AACallEdges :: ID , & AAPointerInfo :: ID } ) ; Attributor A ( Functions , InfoCache , CGUpdater , & Allowed ) ; for ( Function & F : M ) { if ( ! F . isIntrinsic ( ) ) { A . getOrCreateAAFor < AAAMDAttributes > ( IRPosition :: function ( F ) ) ; A . getOrCreateAAFor < AAUniformWorkGroupSize > ( IRPosition :: function ( F ) ) ; if ( ! AMDGPU :: isEntryFunctionCC ( F . getCallingConv ( ) ) ) { A . getOrCreateAAFor < AAAMDFlatWorkGroupSize > ( IRPosition :: function ( F ) ) ; } } } ChangeStatus Change = A . run ( ) ; return Change == ChangeStatus :: CHANGED ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


"\n========== quad_load_store, return %s\n"

Return true if this is a load or store quad operation . This function does not handle the atomic quad memory instructions .


<s> const char * RISCVTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( RISCVISD :: NodeType ) Opcode ) { case RISCVISD :: FIRST_NUMBER : break ; case RISCVISD :: RET_FLAG : return "RISCVISD::RET_FLAG" ; case RISCVISD :: URET_FLAG : return "RISCVISD::URET_FLAG" ; case RISCVISD :: SRET_FLAG : return "RISCVISD::SRET_FLAG" ; case RISCVISD :: MRET_FLAG : return "RISCVISD::MRET_FLAG" ; case RISCVISD :: CALL : return "RISCVISD::CALL" ; case RISCVISD :: SELECT_CC : return "RISCVISD::SELECT_CC" ; case RISCVISD :: BuildPairF64 : return "RISCVISD::BuildPairF64" ; case RISCVISD :: SplitF64 : return "RISCVISD::SplitF64" ; case RISCVISD :: TAIL : return "RISCVISD::TAIL" ; case RISCVISD :: SLLW : return "RISCVISD::SLLW" ; case RISCVISD :: SRAW : return "RISCVISD::SRAW" ; case RISCVISD :: SRLW : return "RISCVISD::SRLW" ; case RISCVISD :: DIVW : return "RISCVISD::DIVW" ; case RISCVISD :: DIVUW : return "RISCVISD::DIVUW" ; case RISCVISD :: REMUW : return "RISCVISD::REMUW" ; case RISCVISD :: FMV_W_X_RV64 : return "RISCVISD::FMV_W_X_RV64" ; case RISCVISD :: FMV_X_ANYEXTW_RV64 : return "RISCVISD::FMV_X_ANYEXTW_RV64" ; case RISCVISD :: READ_CYCLE_WIDE : return "RISCVISD::READ_CYCLE_WIDE" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> void visium_split_cbranch ( enum rtx_code code , rtx op0 , rtx op1 , rtx label ) { machine_mode cc_mode = visium_select_cc_mode ( code , op0 , op1 ) ; rtx flags = gen_rtx_REG ( cc_mode , FLAGS_REGNUM ) ; rtx x = gen_rtx_COMPARE ( cc_mode , op0 , op1 ) ; x = gen_rtx_SET ( flags , x ) ; emit_insn ( x ) ; x = gen_rtx_fmt_ee ( code , VOIDmode , flags , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label ) , pc_rtx ) ; x = gen_rtx_SET ( pc_rtx , x ) ; emit_jump_insn ( x ) ; visium_flags_exposed = true ; } </s>

Split a compare-and-branch with CODE , operands OP0 and OP1 , and LABEL .


<s> static rtx aarch64_gen_load_pair ( machine_mode mode , rtx reg1 , rtx mem1 , rtx reg2 , rtx mem2 ) { switch ( mode ) { case E_DImode : return gen_load_pair_dw_didi ( reg1 , mem1 , reg2 , mem2 ) ; case E_DFmode : return gen_load_pair_dw_dfdf ( reg1 , mem1 , reg2 , mem2 ) ; case E_TFmode : return gen_load_pair_dw_tftf ( reg1 , mem1 , reg2 , mem2 ) ; case E_V4SImode : return gen_load_pairv4siv4si ( reg1 , mem1 , reg2 , mem2 ) ; default : gcc_unreachable ( ) ; } } </s>

Generate and regurn a load pair isntruction of mode MODE to load register REG1 from MEM1 and register REG2 from MEM2 .


<s> static rtx tilepro_tls_got ( void ) { rtx temp ; if ( flag_pic ) { crtl -> uses_pic_offset_table = 1 ; return tilepro_got_rtx ( ) ; } temp = gen_reg_rtx ( Pmode ) ; emit_move_insn ( temp , tilepro_got_symbol ( ) ) ; return temp ; } </s>

Return a reference to the got to be used by tls references .


<s> virtual const OR1KSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static void swap_const_vector_halves ( rtx * op_ptr ) { int i ; rtx op = * op_ptr ; enum rtx_code code = GET_CODE ( op ) ; if ( GET_CODE ( op ) == CONST_VECTOR ) { int units = GET_MODE_NUNITS ( GET_MODE ( op ) ) ; rtx_vector_builder builder ( GET_MODE ( op ) , units , 1 ) ; for ( i = 0 ; i < units / 2 ; ++ i ) builder . quick_push ( CONST_VECTOR_ELT ( op , i + units / 2 ) ) ; for ( i = 0 ; i < units / 2 ; ++ i ) builder . quick_push ( CONST_VECTOR_ELT ( op , i ) ) ; * op_ptr = builder . build ( ) ; } else { int j ; const char * fmt = GET_RTX_FORMAT ( code ) ; for ( i = 0 ; i < GET_RTX_LENGTH ( code ) ; ++ i ) if ( fmt [ i ] == 'e' || fmt [ i ] == 'u' ) swap_const_vector_halves ( & XEXP ( op , i ) ) ; else if ( fmt [ i ] == 'E' ) for ( j = 0 ; j < XVECLEN ( op , i ) ; ++ j ) swap_const_vector_halves ( & XVECEXP ( op , i , j ) ) ; } } </s>

OP is either a CONST_VECTOR or an expression containing one . Swap the first half of the vector with the second in the first case . Recurse to find it in the second .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> const InstrItineraryData & getInstrItineraryData ( ) const { return InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s>
unsigned
M88kMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
if
(
MO
.
isImm
(
)
)
return
static_cast
<
uint64_t
>
(
MO
.
getImm
(
)
)
;
assert
(
MO
.
isExpr
(
)
&&
"Expected MCExpr"
)
;
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
assert
(
isa
<
M88kMCExpr
>
(
Expr
)
&&
"Expected M88kMCExpr"
)
;
const
uint32_t
Offset
=
2
;
Fixups
.
push_back
(
MCFixup
::
create
(
Offset
,
Expr
,
MCFixupKind
(
FixupKind
(
Expr
)
)
)
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static int mips_arg_partial_bytes ( cumulative_args_t cum , machine_mode mode , tree type , bool named ) { struct mips_arg_info info ; mips_get_arg_info ( & info , get_cumulative_args ( cum ) , mode , type , named ) ; return info . stack_words > 0 ? info . reg_words * UNITS_PER_WORD : 0 ; } </s>


"WebAssembly doesn't support non-C calling conventions"

"WebAssembly hasn't implemented inalloca arguments"

"WebAssembly hasn't implemented nest arguments"

"WebAssembly hasn't implemented cons regs arguments"

"WebAssembly hasn't implemented cons regs last arguments"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


"Not all fixup kinds added to Infos array"


<s>
void
BlackfinInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
BF
::
ALLRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
MOVE
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
return
;
}
if
(
BF
::
D16RegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
SLL16i
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
0
)
;
return
;
}
if
(
BF
::
DRegClass
.
contains
(
DestReg
)
)
{
if
(
SrcReg
==
BF
::
NCC
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
MOVENCC_z
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
BITTGL
)
,
DestReg
)
.
addReg
(
DestReg
)
.
addImm
(
0
)
;
return
;
}
if
(
SrcReg
==
BF
::
CC
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
MOVECC_zext
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
return
;
}
}
if
(
BF
::
DRegClass
.
contains
(
SrcReg
)
)
{
if
(
DestReg
==
BF
::
NCC
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
SETEQri_not
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
0
)
;
return
;
}
if
(
DestReg
==
BF
::
CC
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
MOVECC_nz
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
return
;
}
}
if
(
DestReg
==
BF
::
NCC
&&
SrcReg
==
BF
::
CC
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
MOVE_ncccc
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
return
;
}
if
(
DestReg
==
BF
::
CC
&&
SrcReg
==
BF
::
NCC
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
MOVE_ccncc
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
return
;
}
llvm_unreachable
(
"Bad reg-to-reg copy"
)
;
}
</s>


"instruction requires a WASM feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> void HSAILPassConfig :: addPostRegAlloc ( ) { } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> void ix86_expand_floorceildf_32 ( rtx operand0 , rtx operand1 , bool do_floor ) { machine_mode mode = GET_MODE ( operand0 ) ; rtx xa , TWO52 , tmp , one , res , mask ; rtx_code_label * label ; TWO52 = ix86_gen_TWO52 ( mode ) ; res = gen_reg_rtx ( mode ) ; emit_move_insn ( res , operand1 ) ; xa = ix86_expand_sse_fabs ( res , & mask ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; xa = expand_simple_binop ( mode , PLUS , xa , TWO52 , NULL_RTX , 0 , OPTAB_DIRECT ) ; xa = expand_simple_binop ( mode , MINUS , xa , TWO52 , xa , 0 , OPTAB_DIRECT ) ; ix86_sse_copysign_to_positive ( xa , xa , res , mask ) ; one = force_reg ( mode , const_double_from_real_value ( do_floor ? dconst1 : dconstm1 , mode ) ) ; tmp = ix86_expand_sse_compare_mask ( UNGT , xa , res , ! do_floor ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_AND ( mode , one , tmp ) ) ) ; tmp = expand_simple_binop ( mode , MINUS , xa , tmp , NULL_RTX , 0 , OPTAB_DIRECT ) ; emit_move_insn ( res , tmp ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; emit_move_insn ( operand0 , res ) ; } </s>

Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing into OPERAND0 .


<s> void Thumb1RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; DebugLoc dl = Old -> getDebugLoc ( ) ; unsigned Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { unsigned Align = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; Amount = ( Amount + Align - 1 ) / Align * Align ; unsigned Opc = Old -> getOpcode ( ) ; if ( Opc == ARM :: ADJCALLSTACKDOWN || Opc == ARM :: tADJCALLSTACKDOWN ) { emitSPUpdate ( MBB , I , TII , dl , * this , - Amount ) ; } else { assert ( Opc == ARM :: ADJCALLSTACKUP || Opc == ARM :: tADJCALLSTACKUP ) ; emitSPUpdate ( MBB , I , TII , dl , * this , Amount ) ; } } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static void ia64_output_function_end_prologue ( FILE * file ) { if ( ia64_except_unwind_info ( & global_options ) != UI_TARGET ) return ; fputs ( "\t.body\n" , file ) ; } </s>

Emit the .body directive at the scheduled end of the prologue .


"Invalid number of NOP bytes requested!"

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> static rtx riscv_add_offset ( rtx temp , rtx reg , HOST_WIDE_INT offset ) { if ( ! SMALL_OPERAND ( offset ) ) { rtx high ; high = gen_int_mode ( CONST_HIGH_PART ( offset ) , Pmode ) ; offset = CONST_LOW_PART ( offset ) ; high = riscv_force_temporary ( temp , high ) ; reg = riscv_force_temporary ( temp , gen_rtx_PLUS ( Pmode , high , reg ) ) ; } return plus_constant ( Pmode , reg , offset ) ; } </s>

Return a legitimate address for REG + OFFSET . TEMP is as for riscv_force_temporary ; it is only needed when OFFSET is not a SMALL_OPERAND .


<s> MSP430Subtarget :: MSP430Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : MSP430GenSubtargetInfo ( TT , CPU , FS ) , DL ( "e-m:e-p:16:16-i32:16:32-a:16-n8:16" ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM ) , TSInfo ( DL ) { } </s>

This constructor initializes the data members to match that of the specified triple .


<s> void PatmosFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const TargetInstrInfo * TII = STC . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned stackSize = assignFrameObjects ( MF , ! DisableStackCache ) ; if ( ! DisableStackCache ) { MachineInstr * MI = emitSTC ( MF , MBB , MBBI , Patmos :: SRESi ) ; if ( MI ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; patchCallSites ( MF ) ; } if ( stackSize ) { if ( stackSize <= 0xFFF ) { MachineInstr * MI = AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII -> get ( Patmos :: SUBi ) , Patmos :: RSP ) ) . addReg ( Patmos :: RSP ) . addImm ( stackSize ) ; MI -> setFlag ( MachineInstr :: FrameSetup ) ; } else { MachineInstr * MI = AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII -> get ( Patmos :: SUBl ) , Patmos :: RSP ) ) . addReg ( Patmos :: RSP ) . addImm ( stackSize ) ; MI -> setFlag ( MachineInstr :: FrameSetup ) ; } } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Patmos Patmos Patmos::SRESi 0xFFF Patmos::SUBi Patmos::RSP Patmos::RSP Patmos::SUBl Patmos::RSP Patmos::RSP


<s> static std :: unique_ptr < ARMOperand > CreateReg ( unsigned RegNum , SMLoc S , SMLoc E ) { auto Op = std :: make_unique < ARMOperand > ( k_Register ) ; Op -> Reg . RegNum = RegNum ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < TargetTransformInfoWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const X86Subtarget & Subtarget = MF . getSubtarget < X86Subtarget > ( ) ; bool HasSSE = Subtarget . hasSSE1 ( ) ; bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return CSR_64_TLS_Darwin_RegMask ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: X86_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_RegMask : CSR_Win64_RegCall_NoSSE_RegMask ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_RegMask : CSR_SysV64_RegCall_NoSSE_RegMask ) ; } } else { return ( HasSSE ? CSR_32_RegCall_RegMask : CSR_32_RegCall_NoSSE_RegMask ) ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: X86_64_Win64 : return CSR_Win64_RegMask ; case CallingConv :: X86_64_SysV : return CSR_64_RegMask ; case CallingConv :: X86_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_32_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_32_AllRegs_SSE_RegMask ; return CSR_32_AllRegs_RegMask ; } default : break ; } if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_RegMask ; if ( Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) -> getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_64_SwiftError_RegMask ; return CSR_64_RegMask ; } return CSR_32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
static
void
vax_output_function_prologue
(
FILE
*
file
,
HOST_WIDE_INT
size
)
{
int
regno
;
int
mask
=
0
;
for
(
regno
=
0
;
regno
<
FIRST_PSEUDO_REGISTER
;
regno
++
)
if
(
regs_ever_live
[
regno
]
&&
!
call_used_regs
[
regno
]
)
mask
|=
1
<<
regno
;
fprintf
(
file
,
"\t.word 0x%x\n"
,
mask
)
;
if
(
dwarf2out_do_frame
(
)
)
{
const
char
*
label
=
dwarf2out_cfi_label
(
)
;
int
offset
=
0
;
for
(
regno
=
FIRST_PSEUDO_REGISTER
1
;
regno
>=
0
;
regno
)
if
(
regs_ever_live
[
regno
]
&&
!
call_used_regs
[
regno
]
)
dwarf2out_reg_save
(
label
,
regno
,
offset
-=
4
)
;
dwarf2out_reg_save
(
label
,
PC_REGNUM
,
offset
-=
4
)
;
dwarf2out_reg_save
(
label
,
FRAME_POINTER_REGNUM
,
offset
-=
4
)
;
dwarf2out_reg_save
(
label
,
ARG_POINTER_REGNUM
,
offset
-=
4
)
;
dwarf2out_def_cfa
(
label
,
FRAME_POINTER_REGNUM
,
(
offset
4
)
)
;
}
size
-=
STARTING_FRAME_OFFSET
;
if
(
size
>=
64
)
asm_fprintf
(
file
,
"\tmovab %wd(%Rsp),%Rsp\n"
,
size
)
;
else
if
(
size
)
asm_fprintf
(
file
,
"\tsubl2 $%wd,%Rsp\n"
,
size
)
;
}
</s>

Generate the assembly code for function entry . FILE is a stdio stream to output the code to . SIZE is an int : how many units of temporary storage to allocate . Refer to the array ` regs_ever_live ' to determine which registers to save ; ` regs_ever_live [ I ] ' is nonzero if register number I is ever used in the function . This function is responsible for knowing which registers should not be saved even if used .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"ARM64 Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> SDValue AMDGPUTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { for ( unsigned i = 0 , e = Ins . size ( ) ; i < e ; ++ i ) { InVals . push_back ( SDValue ( ) ) ; } return Chain ; } </s>


"failed to spill SGPR to VGPR when allocated"

runOnMachineFunction - Emit the function body .


<s>
bool
Emitter
<
CodeEmitter
>
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MCE
.
setModuleInfo
(
&
getAnalysis
<
MachineModuleInfo
>
(
)
)
;
II
=
TM
.
getInstrInfo
(
)
;
TD
=
TM
.
getTargetData
(
)
;
Is64BitMode
=
TM
.
getSubtarget
<
X86Subtarget
>
(
)
.
is64Bit
(
)
;
IsPIC
=
TM
.
getRelocationModel
(
)
==
Reloc
::
PIC_
;
do
{
DOUT
<<
"JITTing function '"
<<
MF
.
getFunction
(
)
->
getName
(
)
<<
"'\n"
;
MCE
.
startFunction
(
MF
)
;
for
(
MachineFunction
::
iterator
MBB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBB
!=
E
;
++
MBB
)
{
MCE
.
StartMachineBasicBlock
(
MBB
)
;
for
(
MachineBasicBlock
::
const_iterator
I
=
MBB
->
begin
(
)
,
E
=
MBB
->
end
(
)
;
I
!=
E
;
++
I
)
{
const
TargetInstrDesc
&
Desc
=
I
->
getDesc
(
)
;
emitInstruction
(
*
I
,
&
Desc
)
;
if
(
Desc
.
getOpcode
(
)
==
X86
::
MOVPC32r
)
emitInstruction
(
*
I
,
&
II
->
get
(
X86
::
POP32r
)
)
;
NumEmitted
++
;
}
}
}
while
(
MCE
.
finishFunction
(
MF
)
)
;
return
false
;
}
</s>


<s>
Register
LanaiTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
,
const
MachineFunction
&
)
const
{
Register
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"pc"
,
Lanai
::
PC
)
.
Case
(
"sp"
,
Lanai
::
SP
)
.
Case
(
"fp"
,
Lanai
::
FP
)
.
Case
(
"rr1"
,
Lanai
::
RR1
)
.
Case
(
"r10"
,
Lanai
::
R10
)
.
Case
(
"rr2"
,
Lanai
::
RR2
)
.
Case
(
"r11"
,
Lanai
::
R11
)
.
Case
(
"rca"
,
Lanai
::
RCA
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s>
bool
SystemZInstrInfo
::
reverseBranchCondition
(
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
assert
(
Cond
.
size
(
)
==
2
&&
"Invalid condition"
)
;
Cond
[
1
]
.
setImm
(
Cond
[
1
]
.
getImm
(
)
^
Cond
[
0
]
.
getImm
(
)
)
;
return
false
;
}
</s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> enum calling_abi ix86_cfun_abi ( void ) { return cfun ? cfun -> machine -> call_abi : ix86_abi ; } </s>

Returns value SYSV_ABI , MS_ABI dependent on cfun , specifying the call abi used .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"mproc Assembly Printer"
;
}
</s>


<s>
void
AMDGPUMCInstLower
::
lower
(
const
MachineInstr
*
MI
,
MCInst
&
OutMI
)
const
{
OutMI
.
setOpcode
(
getMCOpcode
(
MI
->
getOpcode
(
)
)
)
;
for
(
const
MachineOperand
&
MO
:
MI
->
explicit_operands
(
)
)
{
MCOperand
MCOp
;
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
CreateImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_Register
:
MCOp
=
MCOperand
::
CreateReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
CreateExpr
(
MCSymbolRefExpr
::
Create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
Ctx
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
MCSymbol
*
Sym
=
Ctx
.
GetOrCreateSymbol
(
StringRef
(
GV
->
getName
(
)
)
)
;
MCOp
=
MCOperand
::
CreateExpr
(
MCSymbolRefExpr
::
Create
(
Sym
,
Ctx
)
)
;
break
;
}
case
MachineOperand
::
MO_TargetIndex
:
{
assert
(
MO
.
getIndex
(
)
==
AMDGPU
::
TI_CONSTDATA_START
)
;
MCSymbol
*
Sym
=
Ctx
.
GetOrCreateSymbol
(
StringRef
(
END_OF_TEXT_LABEL_NAME
)
)
;
const
MCSymbolRefExpr
*
Expr
=
MCSymbolRefExpr
::
Create
(
Sym
,
Ctx
)
;
MCOp
=
MCOperand
::
CreateExpr
(
Expr
)
;
break
;
}
}
OutMI
.
addOperand
(
MCOp
)
;
}
}
</s>


<s> unsigned int call_properties ( const function_instance & ) const OVERRIDE { return CP_WRITE_MEMORY ; } </s>

Default implementation of function_base : :call_properties , with conservatively correct behavior for floating-point instructions .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < PatmosSPReduce > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> SDNode * TMS320C64XInstSelectorPass :: Select ( SDNode * op ) { if ( op -> isMachineOpcode ( ) ) return op ; return SelectCode ( op ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> unsigned X86TTI :: getIntImmCost ( Intrinsic :: ID IID , unsigned Idx , const APInt & Imm , Type * Ty ) const { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TCC_Free ; switch ( IID ) { default : return TCC_Free ; case Intrinsic :: sadd_with_overflow : case Intrinsic :: uadd_with_overflow : case Intrinsic :: ssub_with_overflow : case Intrinsic :: usub_with_overflow : case Intrinsic :: smul_with_overflow : case Intrinsic :: umul_with_overflow : if ( ( Idx == 1 ) && Imm . getBitWidth ( ) <= 64 && isInt < 32 > ( Imm . getSExtValue ( ) ) ) return TCC_Free ; break ; case Intrinsic :: experimental_stackmap : if ( ( Idx < 2 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TCC_Free ; break ; case Intrinsic :: experimental_patchpoint_void : case Intrinsic :: experimental_patchpoint_i64 : if ( ( Idx < 4 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TCC_Free ; break ; } return X86TTI :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> void PPCFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && I -> getOpcode ( ) == PPC :: ADJCALLSTACKUP ) { if ( int CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { bool is64Bit = Subtarget . isPPC64 ( ) ; CalleeAmt *= - 1 ; unsigned StackReg = is64Bit ? PPC :: X1 : PPC :: R1 ; unsigned TmpReg = is64Bit ? PPC :: X0 : PPC :: R0 ; unsigned ADDIInstr = is64Bit ? PPC :: ADDI8 : PPC :: ADDI ; unsigned ADDInstr = is64Bit ? PPC :: ADD8 : PPC :: ADD4 ; unsigned LISInstr = is64Bit ? PPC :: LIS8 : PPC :: LIS ; unsigned ORIInstr = is64Bit ? PPC :: ORI8 : PPC :: ORI ; MachineInstr * MI = I ; DebugLoc dl = MI -> getDebugLoc ( ) ; if ( isInt < 16 > ( CalleeAmt ) ) { BuildMI ( MBB , I , dl , TII . get ( ADDIInstr ) , StackReg ) . addReg ( StackReg , RegState :: Kill ) . addImm ( CalleeAmt ) ; } else { MachineBasicBlock :: iterator MBBI = I ; BuildMI ( MBB , MBBI , dl , TII . get ( LISInstr ) , TmpReg ) . addImm ( CalleeAmt >> 16 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ORIInstr ) , TmpReg ) . addReg ( TmpReg , RegState :: Kill ) . addImm ( CalleeAmt & 0xFFFF ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ADDInstr ) , StackReg ) . addReg ( StackReg , RegState :: Kill ) . addReg ( TmpReg ) ; } } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"AMDGPU Annotate Kernel Features"
;
}
</s>

AMDGPU
"AMDGPU Annotate Kernel Features"


<s> Value * X86TargetLowering :: getSafeStackPointerLocation ( IRBuilder < > & IRB ) const { if ( ! Subtarget -> isTargetAndroid ( ) ) return TargetLowering :: getSafeStackPointerLocation ( IRB ) ; unsigned AddressSpace , Offset ; if ( Subtarget -> is64Bit ( ) ) { Offset = 0x48 ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Kernel ) AddressSpace = 256 ; else AddressSpace = 257 ; } else { Offset = 0x24 ; AddressSpace = 256 ; } return ConstantExpr :: getIntToPtr ( ConstantInt :: get ( Type :: getInt32Ty ( IRB . getContext ( ) ) , Offset ) , Type :: getInt8PtrTy ( IRB . getContext ( ) ) -> getPointerTo ( AddressSpace ) ) ; } </s>

Return true if the target stores SafeStack pointer at a fixed offset in some non-standard address space , and populates the address space and offset as appropriate .


<s> static int extended_reg_mentioned_1 ( rtx * p , void * data ATTRIBUTE_UNUSED ) { unsigned int regno ; if ( ! REG_P ( * p ) ) return 0 ; regno = REGNO ( * p ) ; return REX_INT_REGNO_P ( regno ) || REX_SSE_REGNO_P ( regno ) ; } </s>

Return nonzero when P points to register encoded via REX prefix . Called via for_each_rtx .


"Pseudo opcode found in EmitInstruction()"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool nds32_rtx_costs_impl ( rtx x , machine_mode mode ATTRIBUTE_UNUSED , int outer_code , int opno , int * total , bool speed ) { int code = GET_CODE ( x ) ; if ( speed ) return rtx_cost_model . speed_prefer ( x , code , outer_code , opno , total ) ; else return rtx_cost_model . size_prefer ( x , code , outer_code , opno , total ) ; } </s>

This target hook describes the relative costs of RTL expressions . Return 'true ' when all subexpressions of x have been processed . Return 'false ' to sum the costs of sub-rtx , plus cost of this operation . Refer to gcc/rtlanal.cc for more information .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { TargetTransformInfo :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> SDValue AArch64SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; ConstantSDNode * SizeValue = dyn_cast < ConstantSDNode > ( Size ) ; const char * bzeroEntry = ( V && V -> isNullValue ( ) ) ? DAG . getTarget ( ) . getSubtarget < AArch64Subtarget > ( ) . getBZeroEntry ( ) : nullptr ; if ( bzeroEntry && ( ! SizeValue || SizeValue -> getZExtValue ( ) > 256 ) ) { const AArch64TargetLowering & TLI = * DAG . getTarget ( ) . getSubtarget < AArch64Subtarget > ( ) . getTargetLowering ( ) ; EVT IntPtr = TLI . getPointerTy ( ) ; Type * IntPtrTy = getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroEntry , IntPtr ) , std :: move ( Args ) , 0 ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memset .


<s> bool HexagonTTIImpl :: isLegalMaskedLoad ( Type * DataType , Align ) { return HexagonMaskedVMem && isTypeForHVX ( DataType ) ; } </s>

Return true if the target supports masked load .


<s> HOST_WIDE_INT bpf_initial_elimination_offset ( int from , int to ) { HOST_WIDE_INT ret ; if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) ret = ( cfun -> machine -> local_vars_size + cfun -> machine -> callee_saved_reg_size ) ; else if ( from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM ) ret = 0 ; else gcc_unreachable ( ) ; return ret ; } </s>

Return the initial difference between the specified pair of registers . The registers that can figure in FROM , and TO , are specified by ELIMINABLE_REGS in bpf.h . This function is used in the definition of INITIAL_ELIMINATION_OFFSET in bpf.h


<s> bool isToken ( ) const override { return Kind == k_Token ; } </s>


"Frame offsets outside of the signed 16-bit range not supported"