<s> bool ARMFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; unsigned PushOpc = AFI -> isThumbFunction ( ) ? ARM :: t2STMDB_UPD : ARM :: STMDB_UPD ; unsigned PushOneOpc = AFI -> isThumbFunction ( ) ? ARM :: t2STR_PRE : ARM :: STR_PRE_IMM ; unsigned FltOpc = ARM :: VSTMDDB_UPD ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & isARMArea1Register , MachineInstr :: FrameSetup ) ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & isARMArea2Register , MachineInstr :: FrameSetup ) ; emitPushInst ( MBB , MI , CSI , FltOpc , 0 , true , & isARMArea3Register , MachineInstr :: FrameSetup ) ; return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> bool X86AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < X86Subtarget > ( ) ; SMShadowTracker . startFunction ( MF ) ; CodeEmitter . reset ( TM . getTarget ( ) . createMCCodeEmitter ( * Subtarget -> getInstrInfo ( ) , * Subtarget -> getRegisterInfo ( ) , MF . getContext ( ) ) ) ; EmitFPOData = Subtarget -> isTargetWin32 ( ) && MF . getMMI ( ) . getModule ( ) -> getCodeViewFlag ( ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Local = MF . getFunction ( ) -> hasLocalLinkage ( ) ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Local ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; emitXRayTable ( ) ; EmitFPOData = false ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> void MipsSEFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned BP = ABI . IsN64 ( ) ? Mips :: S7_64 : Mips :: S7 ; if ( hasFP ( MF ) ) setAliasRegs ( MF , SavedRegs , FP ) ; if ( hasBP ( MF ) ) setAliasRegs ( MF , SavedRegs , BP ) ; if ( MipsFI -> callsEhReturn ( ) ) MipsFI -> createEhDataRegsFI ( ) ; if ( MipsFI -> isISR ( ) ) MipsFI -> createISRRegFI ( ) ; if ( ExpandPseudo ( MF ) . expand ( ) ) { const TargetRegisterClass & RC = STI . isGP64bit ( ) ? Mips :: GPR64RegClass : Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlignment ( RC ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } uint64_t MaxSPOffset = estimateStackSize ( MF ) ; if ( isIntN ( STI . hasMSA ( ) ? 10 : 16 , MaxSPOffset ) && ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ) return ; const TargetRegisterClass & RC = ABI . ArePtrs64bit ( ) ? Mips :: GPR64RegClass : Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlignment ( RC ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> const BPFTargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


<s> bool R600InstrInfo :: fitsReadPortLimitations ( const std :: vector < MachineInstr * > & IG , const DenseMap < unsigned , unsigned > & PV , std :: vector < BankSwizzle > & ValidSwizzle ) const { std :: vector < std :: vector < std :: pair < int , unsigned > > > IGSrcs ; ValidSwizzle . clear ( ) ; for ( unsigned i = 0 , e = IG . size ( ) ; i < e ; ++ i ) { IGSrcs . push_back ( ExtractSrcs ( IG [ i ] , PV ) ) ; unsigned Op = getOperandIdx ( IG [ i ] -> getOpcode ( ) , AMDGPU :: OpName :: bank_swizzle ) ; ValidSwizzle . push_back ( ( R600InstrInfo :: BankSwizzle ) IG [ i ] -> getOperand ( Op ) . getImm ( ) ) ; } bool Result = recursiveFitsFPLimitation ( IGSrcs , ValidSwizzle ) ; if ( ! Result ) return false ; return true ; } </s>

Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first ( in lexical order ) BankSwizzle affectation starting from the one already provided in the Instruction Group MIs that fits Read Port limitations in BS if available .


<s> bool SICFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || TRI -> needsStackRealignment ( MF ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool MipsAsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { const unsigned FixupKind = Fixup . getKind ( ) ; switch ( FixupKind ) { default : return false ; case Mips :: fixup_Mips_CALL_HI16 : case Mips :: fixup_Mips_CALL_LO16 : case Mips :: fixup_Mips_CALL16 : case Mips :: fixup_Mips_GOT : case Mips :: fixup_Mips_GOT_PAGE : case Mips :: fixup_Mips_GOT_OFST : case Mips :: fixup_Mips_GOT_DISP : case Mips :: fixup_Mips_GOT_HI16 : case Mips :: fixup_Mips_GOT_LO16 : case Mips :: fixup_Mips_GOTTPREL : case Mips :: fixup_Mips_DTPREL_HI : case Mips :: fixup_Mips_DTPREL_LO : case Mips :: fixup_Mips_TLSGD : case Mips :: fixup_Mips_TLSLDM : case Mips :: fixup_Mips_TPREL_HI : case Mips :: fixup_Mips_TPREL_LO : case Mips :: fixup_MICROMIPS_CALL16 : case Mips :: fixup_MICROMIPS_GOT_DISP : case Mips :: fixup_MICROMIPS_GOT_PAGE : case Mips :: fixup_MICROMIPS_GOT_OFST : case Mips :: fixup_MICROMIPS_GOT16 : case Mips :: fixup_MICROMIPS_GOTTPREL : case Mips :: fixup_MICROMIPS_TLS_DTPREL_HI16 : case Mips :: fixup_MICROMIPS_TLS_DTPREL_LO16 : case Mips :: fixup_MICROMIPS_TLS_GD : case Mips :: fixup_MICROMIPS_TLS_LDM : case Mips :: fixup_MICROMIPS_TLS_TPREL_HI16 : case Mips :: fixup_MICROMIPS_TLS_TPREL_LO16 : return true ; } } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> void WebAssemblyTargetELFStreamer :: emitLocal ( ArrayRef < MVT > Types ) { Streamer . EmitIntValue ( WebAssembly :: DotLocal , sizeof ( uint64_t ) ) ; EncodeTypes ( Streamer , Types ) ; } </s>


"J2 DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> bool LC3FrameLowering :: hasFP ( const MachineFunction & MF ) const { return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>


<s> static rtx riscv_function_arg ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; struct riscv_arg_info info ; if ( mode == VOIDmode ) return NULL ; return riscv_get_arg_info ( & info , cum , mode , type , named , false ) ; } </s>


<s> void Thumb2InstrInfo :: ReplaceTailWithBranchTo ( MachineBasicBlock :: iterator Tail , MachineBasicBlock * NewDest ) const { MachineBasicBlock * MBB = Tail -> getParent ( ) ; ARMFunctionInfo * AFI = MBB -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; if ( ! AFI -> hasITBlocks ( ) || Tail -> isBranch ( ) ) { TargetInstrInfo :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; return ; } Register PredReg ; ARMCC :: CondCodes CC = getInstrPredicate ( * Tail , PredReg ) ; MachineBasicBlock :: iterator MBBI = Tail ; if ( CC != ARMCC :: AL ) -- MBBI ; TargetInstrInfo :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; if ( CC != ARMCC :: AL ) { MachineBasicBlock :: iterator E = MBB -> begin ( ) ; unsigned Count = 4 ; while ( Count && MBBI != E ) { if ( MBBI -> isDebugInstr ( ) ) { -- MBBI ; continue ; } if ( MBBI -> getOpcode ( ) == ARM :: t2IT ) { unsigned Mask = MBBI -> getOperand ( 1 ) . getImm ( ) ; if ( Count == 4 ) MBBI -> eraseFromParent ( ) ; else { unsigned MaskOn = 1 << Count ; unsigned MaskOff = ~ ( MaskOn - 1 ) ; MBBI -> getOperand ( 1 ) . setImm ( ( Mask & MaskOff ) | MaskOn ) ; } return ; } -- MBBI ; -- Count ; } } } </s>

Delete the instruction OldInst and everything after it , replacing it with an unconditional branch to NewDest .


<s> unsigned getFramePointerSaveOffset ( ) const { return FramePointerSaveOffset ; } </s>

getFramePointerSaveOffset - Return the previous frame offset to save the frame pointer .


<s>
void
xstormy16_print_operand
(
FILE
*
file
,
rtx
x
,
int
code
)
{
switch
(
code
)
{
case
'B'
:
{
static
int
bits_set
[
8
]
=
{
0
,
1
,
1
,
2
,
1
,
2
,
2
,
3
}
;
HOST_WIDE_INT
xx
=
1
;
HOST_WIDE_INT
l
;
if
(
GET_CODE
(
x
)
==
CONST_INT
)
xx
=
INTVAL
(
x
)
;
else
output_operand_lossage
(
"'B' operand is not constant"
)
;
if
(
bits_set
[
xx
&
7
]
<=
1
)
{
if
(
(
~
xx
&
~
(
HOST_WIDE_INT
)
0xff
)
==
0
)
xx
&=
0xff
;
else
if
(
(
~
xx
&
~
(
HOST_WIDE_INT
)
0xffff
)
==
0
)
xx
&=
0xffff
;
l
=
exact_log2
(
xx
)
;
}
else
{
if
(
(
xx
&
~
(
HOST_WIDE_INT
)
0xff
)
==
0
)
xx
|=
~
(
HOST_WIDE_INT
)
0xff
;
else
if
(
(
xx
&
~
(
HOST_WIDE_INT
)
0xffff
)
==
0
)
xx
|=
~
(
HOST_WIDE_INT
)
0xffff
;
l
=
exact_log2
(
~
xx
)
;
}
if
(
l
==
1
)
output_operand_lossage
(
"'B' operand has multiple bits set"
)
;
fprintf
(
file
,
IMMEDIATE_PREFIX
HOST_WIDE_INT_PRINT_DEC
,
l
)
;
return
;
}
case
'C'
:
if
(
GET_CODE
(
x
)
==
SYMBOL_REF
)
assemble_name
(
file
,
XSTR
(
x
,
0
)
)
;
else
if
(
GET_CODE
(
x
)
==
LABEL_REF
)
output_asm_label
(
x
)
;
else
xstormy16_print_operand_address
(
file
,
x
)
;
return
;
case
'o'
:
case
'O'
:
{
HOST_WIDE_INT
xx
=
0
;
if
(
GET_CODE
(
x
)
==
CONST_INT
)
xx
=
INTVAL
(
x
)
;
else
output_operand_lossage
(
"'o' operand is not constant"
)
;
if
(
code
==
'O'
)
xx
=
xx
;
fprintf
(
file
,
IMMEDIATE_PREFIX
HOST_WIDE_INT_PRINT_DEC
,
xx
1
)
;
return
;
}
case
'b'
:
{
HOST_WIDE_INT
xx
=
1
;
HOST_WIDE_INT
l
;
if
(
GET_CODE
(
x
)
==
CONST_INT
)
xx
=
INTVAL
(
x
)
;
else
output_operand_lossage
(
"'B' operand is not constant"
)
;
l
=
7
xx
;
fputs
(
IMMEDIATE_PREFIX
,
file
)
;
fprintf
(
file
,
HOST_WIDE_INT_PRINT_DEC
,
l
)
;
return
;
}
case
0
:
break
;
default
:
output_operand_lossage
(
"xstormy16_print_operand: unknown code"
)
;
return
;
}
switch
(
GET_CODE
(
x
)
)
{
case
REG
:
fputs
(
reg_names
[
REGNO
(
x
)
]
,
file
)
;
break
;
case
MEM
:
xstormy16_print_operand_address
(
file
,
XEXP
(
x
,
0
)
)
;
break
;
default
:
fputs
(
IMMEDIATE_PREFIX
,
file
)
;
output_addr_const
(
file
,
x
)
;
break
;
}
return
;
}
</s>

Print an operand to an assembler instruction .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { MachineFunctionPass :: getAnalysisUsage ( AU ) ; AU . addRequired < MachineModuleInfoWrapperPass > ( ) ; AU . addPreserved < MachineModuleInfoWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static inline SlotWithTag getTombstoneKey ( ) { return { - 3 , - 3 ; } </s>

Difference in tombstone is that the Optional is meaningful .


<s> TargetLowering :: ConstraintWeight MipsTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'd' : case 'y' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; case 'c' : case 'l' : case 'x' : if ( type -> isIntegerTy ( ) ) weight = CW_SpecificReg ; break ; case 'I' : case 'J' : case 'K' : case 'L' : case 'N' : case 'O' : case 'P' : if ( isa < ConstantInt > ( CallOperandVal ) ) weight = CW_Constant ; break ; case 'R' : weight = CW_Memory ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> static int bpf_core_get_index ( const tree node ) { enum tree_code code = TREE_CODE ( node ) ; if ( code == FIELD_DECL ) { int idx = bpf_core_get_sou_member_index ( ctf_get_tu_ctfc ( ) , node ) ; if ( idx >= 0 ) return idx ; } else if ( code == ARRAY_REF || code == ARRAY_RANGE_REF || code == MEM_REF ) { tree index = TREE_OPERAND ( node , 1 ) ; if ( TREE_CODE ( index ) == INTEGER_CST && tree_fits_shwi_p ( index ) ) return tree_to_shwi ( index ) ; } return - 1 ; } </s>

Compute the index of the NODE in its immediate container . NODE should be a FIELD_DECL ( i.e . of struct or union ) , or an ARRAY_REF .


<s> bool MipsSEFrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { if ( CHERICFI && STI . isCheri ( ) && ! STI . getABI ( ) . IsCheriPureCap ( ) ) for ( auto & I : CSI ) if ( I . getReg ( ) == Mips :: RA_64 ) { CSI . push_back ( CalleeSavedInfo ( Mips :: C16 , 0 ) ) ; break ; } return false ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s>
static
int
s390_fn_types_compatible
(
enum
s390_builtin_ov_type_index
typeindex
,
vec
<
tree
,
va_gc
>
*
arglist
)
{
unsigned
int
i
;
int
match_type
=
0
;
for
(
i
=
0
;
i
<
vec_safe_length
(
arglist
)
;
i
++
)
{
tree
b_arg_type
=
s390_builtin_types
[
s390_builtin_ov_types
[
typeindex
]
[
i
+
1
]
]
;
tree
in_arg
=
(
*
arglist
)
[
i
]
;
tree
in_type
=
TREE_TYPE
(
in_arg
)
;
if
(
TREE_CODE
(
b_arg_type
)
==
VECTOR_TYPE
)
{
if
(
b_arg_type
!=
in_type
&&
TYPE_MAIN_VARIANT
(
b_arg_type
)
!=
TYPE_MAIN_VARIANT
(
in_type
)
)
goto
mismatch
;
}
if
(
lang_hooks
.
types_compatible_p
(
in_type
,
b_arg_type
)
)
continue
;
if
(
lang_hooks
.
types_compatible_p
(
lang_hooks
.
types
.
type_promotes_to
(
in_type
)
,
lang_hooks
.
types
.
type_promotes_to
(
b_arg_type
)
)
)
{
match_type
++
;
continue
;
}
if
(
TREE_CODE
(
b_arg_type
)
==
INTEGER_TYPE
&&
TREE_CODE
(
in_type
)
==
INTEGER_TYPE
)
{
match_type
++
;
continue
;
}
if
(
POINTER_TYPE_P
(
b_arg_type
)
&&
POINTER_TYPE_P
(
in_type
)
&&
!
(
TYPE_QUALS
(
TREE_TYPE
(
in_type
)
)
&
~
TYPE_QUALS
(
TREE_TYPE
(
b_arg_type
)
)
)
&&
(
TYPE_QUALS
(
TREE_TYPE
(
b_arg_type
)
)
&
~
TYPE_QUALS
(
TREE_TYPE
(
in_type
)
)
)
)
{
tree
qual_in_type
=
build_qualified_type
(
TREE_TYPE
(
in_type
)
,
TYPE_QUALS
(
TREE_TYPE
(
b_arg_type
)
)
)
;
if
(
lang_hooks
.
types_compatible_p
(
qual_in_type
,
TREE_TYPE
(
b_arg_type
)
)
)
{
match_type
++
;
continue
;
}
}
mismatch
:
if
(
TARGET_DEBUG_ARG
)
fprintf
(
stderr
,
" mismatch in operand: %d\n"
,
i
+
1
)
;
return
INT_MAX
;
}
return
match_type
;
}
</s>

Check whether the arguments in ARGLIST match the function type DEF_TYPE . Return the number of argument types which required conversion/promotion in order to make it match . 0 stands for a perfect match - all operand types match without changes INT_MAX stands for a mismatch .


<s> static bool microblaze_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { return microblaze_hard_regno_mode_ok_p [ mode ] [ regno ] ; } </s>

Implement TARGET_HARD_REGNO_MODE_OK . In 32 bit mode , require that DImode and DFmode be in even registers . For DImode , this makes some of the insns easier to write , since you do n't have to worry about a DImode value in registers 3 & 4 , producing a result in 4 & 5 . To make the code simpler , the hook now just references an array built in override_options .


<s>
void
mprocInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
;
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>

mproc
mproc
"Impossible reg-to-reg copy"


<s>
SDValue
MSP430TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
SHL
:
case
ISD
::
SRL
:
case
ISD
::
SRA
:
return
LowerShifts
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ExternalSymbol
:
return
LowerExternalSymbol
(
Op
,
DAG
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SIGN_EXTEND
:
return
LowerSIGN_EXTEND
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

MSP430
MSP430
ISD::SHL
ISD::SRL
ISD::SRA
ISD::GlobalAddress
ISD::BlockAddress
ISD::ExternalSymbol
ISD::SETCC
ISD::BR_CC
ISD::SELECT_CC
ISD::SIGN_EXTEND
ISD::RETURNADDR
ISD::FRAMEADDR
ISD::VASTART
ISD::JumpTable
"unimplemented operand"


<s>
char
*
aarch64_output_sve_prefetch
(
const
char
*
mnemonic
,
rtx
prfop_rtx
,
const
char
*
suffix
)
{
static
char
buffer
[
128
]
;
aarch64_svprfop
prfop
=
(
aarch64_svprfop
)
INTVAL
(
prfop_rtx
)
;
unsigned
int
written
=
snprintf
(
buffer
,
sizeof
(
buffer
)
,
"%s\t%s, %s"
,
mnemonic
,
svprfop_token
(
prfop
)
,
suffix
)
;
gcc_assert
(
written
<
sizeof
(
buffer
)
)
;
return
buffer
;
}
</s>

Return the assembly string for an SVE prefetch operation with mnemonic MNEMONIC , given that PRFOP_RTX is the prefetch operation and that SUFFIX is the format for the remaining operands .


<s> void assignValueToReg ( Register ValVReg , Register PhysReg , CCValAssign & VA ) override { markPhysRegUsed ( PhysReg ) ; if ( VA . getLocVT ( ) . getSizeInBits ( ) < 32 ) { auto Copy = MIRBuilder . buildCopy ( LLT :: scalar ( 32 ) , PhysReg ) ; MIRBuilder . buildTrunc ( ValVReg , Copy ) ; return ; } switch ( VA . getLocInfo ( ) ) { case CCValAssign :: LocInfo :: SExt : case CCValAssign :: LocInfo :: ZExt : case CCValAssign :: LocInfo :: AExt : { auto Copy = MIRBuilder . buildCopy ( LLT { VA . getLocVT ( ) } , PhysReg ) ; MIRBuilder . buildTrunc ( ValVReg , Copy ) ; break ; } default : MIRBuilder . buildCopy ( ValVReg , PhysReg ) ; break ; } } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> static const char * unicosmk_ssib_name ( ) { static char name [ 256 ] ; rtx x ; const char * fnname ; int len ; x = DECL_RTL ( cfun -> decl ) ; if ( GET_CODE ( x ) != MEM ) abort ( ) ; x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) != SYMBOL_REF ) abort ( ) ; fnname = XSTR ( x , 0 ) ; STRIP_NAME_ENCODING ( fnname , fnname ) ; len = strlen ( fnname ) ; if ( len + SSIB_PREFIX_LEN > 255 ) len = 255 - SSIB_PREFIX_LEN ; strcpy ( name , SSIB_PREFIX ) ; strncpy ( name + SSIB_PREFIX_LEN , fnname , len ) ; name [ len + SSIB_PREFIX_LEN ] = 0 ; return name ; } </s>

Generate the name of the SSIB section for the current function .


<s> unsigned AArch64RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case AArch64 :: GPR32RegClassID : case AArch64 :: GPR32spRegClassID : case AArch64 :: GPR32allRegClassID : case AArch64 :: GPR64spRegClassID : case AArch64 :: GPR64allRegClassID : case AArch64 :: GPR64RegClassID : case AArch64 :: GPR32commonRegClassID : case AArch64 :: GPR64commonRegClassID : return 32 - 1 - ( TFI -> hasFP ( MF ) || STI -> isTargetDarwin ( ) ) - STI -> isTargetDarwin ( ) - hasBasePointer ( MF ) ; case AArch64 :: FPR8RegClassID : case AArch64 :: FPR16RegClassID : case AArch64 :: FPR32RegClassID : case AArch64 :: FPR64RegClassID : case AArch64 :: FPR128RegClassID : return 32 ; case AArch64 :: DDRegClassID : case AArch64 :: DDDRegClassID : case AArch64 :: DDDDRegClassID : case AArch64 :: QQRegClassID : case AArch64 :: QQQRegClassID : case AArch64 :: QQQQRegClassID : return 32 ; case AArch64 :: FPR128_loRegClassID : return 16 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> static unsigned loongarch_save_libcall_count ( unsigned mask ) { for ( unsigned n = GP_REG_LAST ; n > GP_REG_FIRST ; n -- ) if ( BITSET_P ( mask , n ) ) return CALLEE_SAVED_REG_NUMBER ( n ) + 1 ; abort ( ) ; } </s>

Determine which GPR save/restore routine to call .


<s> static const char * getName ( ) { return DEBUG_TYPE ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> void LM32InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> void M88kInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , Register DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; MachineMemOperand * MMO = getMachineMemOperand ( MBB , FrameIndex , MachineMemOperand :: MOLoad ) ; BuildMI ( MBB , MBBI , DL , get ( M88k :: LDriw ) ) . addReg ( DestReg , RegState :: Define ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) . addMemOperand ( MMO ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> static rtx mips16_stub_call_address ( mips_one_only_stub * stub ) { rtx fn = mips16_stub_function ( stub -> get_name ( ) ) ; SYMBOL_REF_FLAGS ( fn ) |= SYMBOL_FLAG_LOCAL ; if ( ! call_insn_operand ( fn , VOIDmode ) ) fn = force_reg ( Pmode , fn ) ; return fn ; } </s>

Return a legitimate call address for STUB , given that STUB is a MIPS16 support function .


<s> MachineBasicBlock * LinearizedRegion :: getExit ( ) { return Exit ; } </s>


<s> bool LinearizedRegion :: contains ( MachineBasicBlock * MBB ) { return MBBs . count ( MBB ) == 1 ; } </s>

contains - Returns true if this trace contains the given basic block .


<s> int const_uint32_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { return ( GET_CODE ( op ) == CONST_INT && ( INTVAL ( op ) >= 0 && INTVAL ( op ) <= 0xffffffffL ) ) ; return ( ( GET_CODE ( op ) == CONST_INT && INTVAL ( op ) >= 0 ) || ( GET_CODE ( op ) == CONST_DOUBLE && CONST_DOUBLE_HIGH ( op ) == 0 ) ) ; } </s>

Accept integer operands in the range 0 .. 0xffffffff . We have to check the range carefully since this predicate is used in DImode contexts . Also , we need some extra crud to make it work when hosted on 64-bit machines .


<s> static bool aarch64_expand_sve_ld1rq ( rtx dest , rtx src ) { src = force_const_mem ( GET_MODE ( src ) , src ) ; if ( ! src ) return false ; if ( ! aarch64_sve_ld1rq_operand_p ( src ) ) { rtx addr = force_reg ( Pmode , XEXP ( src , 0 ) ) ; src = replace_equiv_address ( src , addr ) ; } machine_mode mode = GET_MODE ( dest ) ; machine_mode pred_mode = aarch64_sve_pred_mode ( mode ) ; rtx ptrue = aarch64_ptrue_reg ( pred_mode ) ; emit_insn ( gen_aarch64_sve_ld1rq ( mode , dest , src , ptrue ) ) ; return true ; } </s>

Try to force 128-bit vector value SRC into memory and use LD1RQ to fetch the memory image into DEST . Return true on success .


<s> unsigned SystemZInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { if ( MI . isInlineAsm ( ) ) { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } else if ( MI . getOpcode ( ) == SystemZ :: PATCHPOINT ) return PatchPointOpers ( & MI ) . getNumPatchBytes ( ) ; else if ( MI . getOpcode ( ) == SystemZ :: STACKMAP ) return MI . getOperand ( 1 ) . getImm ( ) ; else if ( MI . getOpcode ( ) == SystemZ :: FENTRY_CALL ) return 6 ; return MI . getDesc ( ) . getSize ( ) ; } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> static reg_class_t cris_preferred_reload_class ( rtx x ATTRIBUTE_UNUSED , reg_class_t rclass ) { if ( rclass != ACR_REGS && rclass != MOF_REGS && rclass != MOF_SRP_REGS && rclass != SRP_REGS && rclass != CC0_REGS && rclass != SPECIAL_REGS ) return GENERAL_REGS ; return rclass ; } </s>

Worker function for TARGET_PREFERRED_RELOAD_CLASS . It seems like gcc ( 2.7.2 and 2.9x of 2000-03-22 ) may send `` NO_REGS '' as the class for a constant ( testcase : __Mul in arit.c ) . To avoid forcing out a constant into the constant pool , we will trap this case and return something a bit more sane . FIXME : Check if this is a bug . Beware that we must not `` override '' classes that can be specified as constraint letters , or else asm operands using them will fail when they need to be reloaded . FIXME : Investigate whether that constitutes a bug .


<s> bool R600InstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumTCycles , unsigned ExtraTCycles , MachineBasicBlock & FMBB , unsigned NumFCycles , unsigned ExtraFCycles , const BranchProbability & Probability ) const { return true ; } </s>


<s> static rtx aarch64_gen_store_pair ( machine_mode mode , rtx mem1 , rtx reg1 , rtx mem2 , rtx reg2 ) { switch ( mode ) { case E_DImode : return gen_store_pair_dw_didi ( mem1 , reg1 , mem2 , reg2 ) ; case E_DFmode : return gen_store_pair_dw_dfdf ( mem1 , reg1 , mem2 , reg2 ) ; case E_TFmode : return gen_store_pair_dw_tftf ( mem1 , reg1 , mem2 , reg2 ) ; default : gcc_unreachable ( ) ; } } </s>

Generate and return a store pair instruction of mode MODE to store register REG1 to MEM1 and register REG2 to MEM2 .


<s> static void arm_block_arith_comp_libfuncs_for_mode ( machine_mode mode ) { set_optab_libfunc ( add_optab , mode , NULL ) ; set_optab_libfunc ( sdiv_optab , mode , NULL ) ; set_optab_libfunc ( smul_optab , mode , NULL ) ; set_optab_libfunc ( neg_optab , mode , NULL ) ; set_optab_libfunc ( sub_optab , mode , NULL ) ; set_optab_libfunc ( eq_optab , mode , NULL ) ; set_optab_libfunc ( ne_optab , mode , NULL ) ; set_optab_libfunc ( lt_optab , mode , NULL ) ; set_optab_libfunc ( le_optab , mode , NULL ) ; set_optab_libfunc ( ge_optab , mode , NULL ) ; set_optab_libfunc ( gt_optab , mode , NULL ) ; set_optab_libfunc ( unord_optab , mode , NULL ) ; } </s>

Record that we have no arithmetic or comparison libfuncs for machine mode MODE .


<s>
void
NVPTXTargetStreamer
::
changeSection
(
const
MCSection
*
CurSection
,
MCSection
*
Section
,
const
MCExpr
*
SubSection
,
raw_ostream
&
OS
)
{
assert
(
!
SubSection
&&
"SubSection is not null!"
)
;
const
MCObjectFileInfo
*
FI
=
getStreamer
(
)
.
getContext
(
)
.
getObjectFileInfo
(
)
;
if
(
isDwarfSection
(
FI
,
CurSection
)
)
OS
<<
"\t}\n"
;
if
(
isDwarfSection
(
FI
,
Section
)
)
{
outputDwarfFileDirectives
(
)
;
OS
<<
"\t.section"
;
Section
->
printSwitchToSection
(
*
getStreamer
(
)
.
getContext
(
)
.
getAsmInfo
(
)
,
getStreamer
(
)
.
getContext
(
)
.
getTargetTriple
(
)
,
OS
,
SubSection
)
;
OS
<<
"\t{\n"
;
HasSections
=
true
;
}
}
</s>

Update streamer for a new active section .

NVPTX
NVPTX
"SubSection is not null!"
"\t}\n"
"\t.section"
"\t{\n"


"SIInstrInfo::loadRegFromStackSlot - Do not know how to"


"Instr doesn't have FrameIndex operand!"

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s>
void
MSP430InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
;
if
(
MSP430
::
GR16RegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
MSP430
::
MOV16rr
;
else
if
(
MSP430
::
GR8RegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
MSP430
::
MOV8rr
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> static unsigned long arm_compute_save_reg0_reg12_mask ( void ) { unsigned long func_type = arm_current_func_type ( ) ; unsigned long save_reg_mask = 0 ; unsigned int reg ; if ( IS_INTERRUPT ( func_type ) ) { unsigned int max_reg ; if ( ARM_FUNC_TYPE ( func_type ) == ARM_FT_FIQ ) max_reg = 7 ; else max_reg = 12 ; for ( reg = 0 ; reg <= max_reg ; reg ++ ) if ( df_regs_ever_live_p ( reg ) || ( ! crtl -> is_leaf && call_used_regs [ reg ] ) ) save_reg_mask |= ( 1 << reg ) ; if ( flag_pic && ! TARGET_SINGLE_PIC_BASE && arm_pic_register != INVALID_REGNUM && crtl -> uses_pic_offset_table ) save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM ; } else if ( IS_VOLATILE ( func_type ) ) { if ( frame_pointer_needed ) save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM ; if ( df_regs_ever_live_p ( ARM_HARD_FRAME_POINTER_REGNUM ) ) save_reg_mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM ; if ( df_regs_ever_live_p ( THUMB_HARD_FRAME_POINTER_REGNUM ) ) save_reg_mask |= 1 << THUMB_HARD_FRAME_POINTER_REGNUM ; } else { for ( reg = 0 ; reg <= 11 ; reg ++ ) if ( df_regs_ever_live_p ( reg ) && callee_saved_reg_p ( reg ) ) save_reg_mask |= ( 1 << reg ) ; if ( frame_pointer_needed ) save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM ; if ( flag_pic && ! TARGET_SINGLE_PIC_BASE && arm_pic_register != INVALID_REGNUM && ( df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) || crtl -> uses_pic_offset_table ) ) save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM ; if ( IS_STACKALIGN ( func_type ) ) save_reg_mask |= 1 ; } if ( crtl -> calls_eh_return ) { unsigned int i ; for ( i = 0 ; ; i ++ ) { reg = EH_RETURN_DATA_REGNO ( i ) ; if ( reg == INVALID_REGNUM ) break ; save_reg_mask |= 1 << reg ; } } return save_reg_mask ; } </s>

Compute the register save mask for registers 0 through 12 inclusive . This code is used by arm_compute_save_reg_mask .


<s> virtual const TGSIRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> int mems_ok_for_quad_peep ( rtx mem1 , rtx mem2 ) { rtx addr1 , addr2 ; unsigned int reg1 , reg2 ; int offset1 , offset2 ; if ( MEM_VOLATILE_P ( mem1 ) || MEM_VOLATILE_P ( mem2 ) ) return 0 ; addr1 = XEXP ( mem1 , 0 ) ; addr2 = XEXP ( mem2 , 0 ) ; if ( GET_CODE ( addr1 ) == PLUS ) { if ( GET_CODE ( XEXP ( addr1 , 0 ) ) != REG ) return 0 ; else { reg1 = REGNO ( XEXP ( addr1 , 0 ) ) ; if ( GET_CODE ( XEXP ( addr1 , 1 ) ) != CONST_INT ) return 0 ; offset1 = INTVAL ( XEXP ( addr1 , 1 ) ) ; } } else if ( GET_CODE ( addr1 ) != REG ) return 0 ; else { reg1 = REGNO ( addr1 ) ; offset1 = 0 ; } if ( GET_CODE ( addr2 ) == PLUS ) { if ( GET_CODE ( XEXP ( addr2 , 0 ) ) != REG ) return 0 ; else { reg2 = REGNO ( XEXP ( addr2 , 0 ) ) ; if ( GET_CODE ( XEXP ( addr2 , 1 ) ) != CONST_INT ) return 0 ; offset2 = INTVAL ( XEXP ( addr2 , 1 ) ) ; } } else if ( GET_CODE ( addr2 ) != REG ) return 0 ; else { reg2 = REGNO ( addr2 ) ; offset2 = 0 ; } if ( reg1 != reg2 ) return 0 ; if ( offset2 != offset1 + 8 ) return 0 ; return 1 ; } </s>

Return 1 if addr1 and addr2 are suitable for lfq or stfq insn . addr1 and addr2 must be in consecutive memory locations ( addr2 == addr1 + 8 ) .


<s> MCDisassembler :: DecodeStatus X86GenericDisassembler :: getInstruction ( MCInst & instr , uint64_t & size , const MemoryObject & region , uint64_t address , raw_ostream & vStream , raw_ostream & cStream ) const { CommentStream = & cStream ; InternalInstruction internalInstr ; dlog_t loggerFn = logger ; if ( & vStream == & nulls ( ) ) loggerFn = 0 ; int ret = decodeInstruction ( & internalInstr , regionReader , ( void * ) & region , loggerFn , ( void * ) & vStream , ( void * ) MII , address , fMode ) ; if ( ret ) { size = internalInstr . readerCursor - address ; return Fail ; } else { size = internalInstr . length ; return ( ! translateInstruction ( instr , internalInstr , this ) ) ? Success : Fail ; } } </s>

Returns the disassembly of a single instruction .


<s> unsigned R600RegisterInfo :: getHWRegChan ( unsigned reg ) const { return this -> getEncodingValue ( reg ) >> HW_CHAN_SHIFT ; } </s>

get the HW encoding for a register 's channel .


<s>
void
PPCDispatchGroupSBHazardRecognizer
::
EmitInstruction
(
SUnit
*
SU
)
{
const
MCInstrDesc
*
MCID
=
DAG
->
getInstrDesc
(
SU
)
;
if
(
MCID
)
{
if
(
CurSlots
==
5
||
(
MCID
->
isBranch
(
)
&&
CurBranches
==
1
)
)
{
CurGroup
.
clear
(
)
;
CurSlots
=
CurBranches
=
0
;
}
else
{
LLVM_DEBUG
(
dbgs
(
)
<<
"**** Adding to dispatch group: "
)
;
LLVM_DEBUG
(
DAG
->
dumpNode
(
*
SU
)
)
;
unsigned
NSlots
;
bool
MustBeFirst
=
mustComeFirst
(
MCID
,
NSlots
)
;
if
(
MustBeFirst
&&
CurSlots
)
{
CurSlots
=
CurBranches
=
0
;
CurGroup
.
clear
(
)
;
}
CurSlots
+=
NSlots
;
CurGroup
.
push_back
(
SU
)
;
if
(
MCID
->
isBranch
(
)
)
++
CurBranches
;
}
}
return
ScoreboardHazardRecognizer
::
EmitInstruction
(
SU
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool enableMachineScheduler ( ) const override { return true ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


<s> static bool spu_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t ) { return ( GET_MODE_SIZE ( from ) == GET_MODE_SIZE ( to ) || ( GET_MODE_SIZE ( from ) <= 4 && GET_MODE_SIZE ( to ) <= 4 ) || ( GET_MODE_SIZE ( from ) >= 16 && GET_MODE_SIZE ( to ) >= 16 ) ) ; } </s>

Implement TARGET_CAN_CHANGE_MODE_CLASS . GCC assumes that modes are in the lowpart of a register , which is only true for SPU .


<s> void rs6000_expand_extract_even ( rtx target , rtx op0 , rtx op1 ) { machine_mode vmode = GET_MODE ( target ) ; unsigned i , nelt = GET_MODE_NUNITS ( vmode ) ; vec_perm_builder perm ( nelt , nelt , 1 ) ; for ( i = 0 ; i < nelt ; i ++ ) perm . quick_push ( i * 2 ) ; rs6000_do_expand_vec_perm ( target , op0 , op1 , vmode , perm ) ; } </s>


<s>
void
WebAssemblyMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
support
::
endian
::
Writer
<
support
::
little
>
(
OS
)
.
write
<
uint64_t
>
(
MI
.
getOpcode
(
)
)
;
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
if
(
Desc
.
isVariadic
(
)
)
support
::
endian
::
Writer
<
support
::
little
>
(
OS
)
.
write
<
uint64_t
>
(
MI
.
getNumOperands
(
)
Desc
.
NumOperands
)
;
for
(
unsigned
i
=
0
,
e
=
MI
.
getNumOperands
(
)
;
i
<
e
;
++
i
)
{
const
MCOperand
&
MO
=
MI
.
getOperand
(
i
)
;
if
(
MO
.
isReg
(
)
)
{
support
::
endian
::
Writer
<
support
::
little
>
(
OS
)
.
write
<
uint64_t
>
(
MO
.
getReg
(
)
)
;
}
else
if
(
MO
.
isImm
(
)
)
{
support
::
endian
::
Writer
<
support
::
little
>
(
OS
)
.
write
<
uint64_t
>
(
MO
.
getImm
(
)
)
;
}
else
if
(
MO
.
isFPImm
(
)
)
{
support
::
endian
::
Writer
<
support
::
little
>
(
OS
)
.
write
<
double
>
(
MO
.
getFPImm
(
)
)
;
}
else
if
(
MO
.
isExpr
(
)
)
{
support
::
endian
::
Writer
<
support
::
little
>
(
OS
)
.
write
<
uint64_t
>
(
0
)
;
Fixups
.
push_back
(
MCFixup
::
create
(
(
1
+
MCII
.
get
(
MI
.
getOpcode
(
)
)
.
isVariadic
(
)
+
i
)
*
sizeof
(
uint64_t
)
,
MO
.
getExpr
(
)
,
STI
.
getTargetTriple
(
)
.
isArch64Bit
(
)
FK_Data_8
:
FK_Data_4
,
MI
.
getLoc
(
)
)
)
;
++
MCNumFixups
;
}
else
{
llvm_unreachable
(
"unexpected operand kind"
)
;
}
}
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .

WebAssembly
WebAssembly
support::endian
support::little
support::endian
support::little
0
support::endian
support::little
support::endian
support::little
support::endian
support::little
support::endian
support::little
0
1
"unexpected operand kind"


"unexpected argument to msp430_select_hwmult_lib: %s"

"unrecognised hwpy field in msp430_mcu_data[%d]: %d"

"unexpected first argument to msp430_select_hwmult_lib: %s"

"msp430_select_hwmult_lib needs one or more arguments"

Implement spec function ` msp430_hwmult_lib麓 .


<s> unsigned XtensaRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return 0 ; } </s>


<s> static bool rs6000_emit_move_si_sf_subreg ( rtx dest , rtx source , machine_mode mode ) { if ( TARGET_DIRECT_MOVE_64BIT && ! reload_in_progress && ! reload_completed && ! lra_in_progress && ( ! SUBREG_P ( dest ) || ! sf_subreg_operand ( dest , mode ) ) && SUBREG_P ( source ) && sf_subreg_operand ( source , mode ) ) { rtx inner_source = SUBREG_REG ( source ) ; machine_mode inner_mode = GET_MODE ( inner_source ) ; if ( mode == SImode && inner_mode == SFmode ) { emit_insn ( gen_movsi_from_sf ( dest , inner_source ) ) ; return true ; } if ( mode == SFmode && inner_mode == SImode ) { emit_insn ( gen_movsf_from_si ( dest , inner_source ) ) ; return true ; } } return false ; } </s>

Helper function to change moves with : ( SUBREG : SF ( REG : SI ) ) and ( SUBREG : SI ( REG : SF ) ) into separate UNSPEC insns . In the PowerPC architecture , scalar SFmode values are stored as DFmode values in the VSX registers . We need to convert the bits before we can use a direct move or operate on the bits in the vector register as an integer type . Skip things like ( set ( SUBREG : SI ( ... ) ( SUBREG : SI ( ... ) ) .


<s> bool hasBranchDivergence ( ) { return true ; } </s>

Return true if branch divergence exists .


<s> void bfin_expand_epilogue ( int need_return , int eh_return ) { rtx spreg = gen_rtx_REG ( Pmode , REG_SP ) ; e_funkind fkind = funkind ( TREE_TYPE ( current_function_decl ) ) ; if ( fkind != SUBROUTINE ) { expand_interrupt_handler_epilogue ( spreg , fkind ) ; return ; } do_unlink ( spreg , get_frame_size ( ) , false ) ; expand_epilogue_reg_restore ( spreg , false , false ) ; if ( ! need_return ) return ; if ( eh_return ) emit_insn ( gen_addsi3 ( spreg , spreg , gen_rtx_REG ( Pmode , REG_P2 ) ) ) ; emit_jump_insn ( gen_return_internal ( GEN_INT ( SUBROUTINE ) ) ) ; } </s>

Generate RTL for the epilogue of the current function . NEED_RETURN is zero if this is for a sibcall . EH_RETURN is nonzero if we 're expanding an eh_return pattern .


<s> bool isTarget64BitILP32 ( ) const { return In64BitMode && ( TargetTriple . getEnvironment ( ) == Triple :: GNUX32 || TargetTriple . isOSNaCl ( ) ) ; } </s>

Is this x86_64 with the ILP32 programming model ( x32 ABI ) ?


<s> enum reg_class preferred_reload_class ( rtx x ATTRIBUTE_UNUSED , enum reg_class class ) { return class ; } </s>

Given an rtx X being reloaded into a reg required to be in class CLASS , return the class of reg to actually use . In general this is just CLASS ; but on some machines in some cases it is preferable to use a more restrictive class . Also , we must ensure that a PLUS is reloaded either into an accumulator or an address register .


"Replace '%s' with __builtin_gcn_dim_pos.\n"

{ { { OMP GCN pass . This pass is intended to make any GCN-specfic transformations to OpenMP target regions . At present , its only purpose is to convert some `` omp '' built-in functions to use closer-to-the-metal `` gcn '' built-in functions .


<s> static int branch_dest ( rtx branch ) { rtx dest ; int dest_uid ; rtx pat = PATTERN ( branch ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , 0 , 0 ) ; dest = SET_SRC ( pat ) ; if ( GET_CODE ( dest ) == IF_THEN_ELSE ) dest = XEXP ( dest , 1 ) ; dest = XEXP ( dest , 0 ) ; dest_uid = INSN_UID ( dest ) ; return INSN_ADDRESSES ( dest_uid ) ; } </s>

Return the destination address of BRANCH . We need to use this instead of get_attr_length , because the cbranch_with_nops pattern conservatively sets its length to 6 , and we still prefer to use shorter sequences .


Return nonzero if the current function is an interrupt function .


<s> DiagnosticInfoUnsupported :: DiagnosticInfoUnsupported ( const Function & Fn , const Twine & Desc , DiagnosticSeverity Severity ) : DiagnosticInfo ( getKindID ( ) , Severity ) , Description ( Desc ) , Fn ( Fn ) { } </s>

Fn is the function where the diagnostic is being emitted .


<s> bool CJGAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( Count == 0 ) { return true ; } return false ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s>
static
rtx
alpha_expand_builtin
(
tree
exp
,
rtx
target
,
rtx
subtarget
ATTRIBUTE_UNUSED
,
machine_mode
mode
ATTRIBUTE_UNUSED
,
int
ignore
ATTRIBUTE_UNUSED
)
{
tree
fndecl
=
TREE_OPERAND
(
CALL_EXPR_FN
(
exp
)
,
0
)
;
unsigned
int
fcode
=
DECL_FUNCTION_CODE
(
fndecl
)
;
tree
arg
;
call_expr_arg_iterator
iter
;
enum
insn_code
icode
;
rtx
op
[
MAX_ARGS
]
,
pat
;
int
arity
;
bool
nonvoid
;
if
(
fcode
>=
ALPHA_BUILTIN_max
)
internal_error
(
"bad builtin fcode"
)
;
icode
=
code_for_builtin
[
fcode
]
;
if
(
icode
==
0
)
internal_error
(
"bad builtin fcode"
)
;
nonvoid
=
TREE_TYPE
(
TREE_TYPE
(
fndecl
)
)
!=
void_type_node
;
arity
=
0
;
FOR_EACH_CALL_EXPR_ARG
(
arg
,
iter
,
exp
)
{
const
struct
insn_operand_data
*
insn_op
;
if
(
arg
==
error_mark_node
)
return
NULL_RTX
;
if
(
arity
>
MAX_ARGS
)
return
NULL_RTX
;
insn_op
=
&
insn_data
[
icode
]
.
operand
[
arity
+
nonvoid
]
;
op
[
arity
]
=
expand_expr
(
arg
,
NULL_RTX
,
insn_op
->
mode
,
EXPAND_NORMAL
)
;
if
(
!
(
*
insn_op
->
predicate
)
(
op
[
arity
]
,
insn_op
->
mode
)
)
op
[
arity
]
=
copy_to_mode_reg
(
insn_op
->
mode
,
op
[
arity
]
)
;
arity
++
;
}
if
(
nonvoid
)
{
machine_mode
tmode
=
insn_data
[
icode
]
.
operand
[
0
]
.
mode
;
if
(
!
target
||
GET_MODE
(
target
)
!=
tmode
||
!
(
*
insn_data
[
icode
]
.
operand
[
0
]
.
predicate
)
(
target
,
tmode
)
)
target
=
gen_reg_rtx
(
tmode
)
;
}
switch
(
arity
)
{
case
0
:
pat
=
GEN_FCN
(
icode
)
(
target
)
;
break
;
case
1
:
if
(
nonvoid
)
pat
=
GEN_FCN
(
icode
)
(
target
,
op
[
0
]
)
;
else
pat
=
GEN_FCN
(
icode
)
(
op
[
0
]
)
;
break
;
case
2
:
pat
=
GEN_FCN
(
icode
)
(
target
,
op
[
0
]
,
op
[
1
]
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
if
(
!
pat
)
return
NULL_RTX
;
emit_insn
(
pat
)
;
if
(
nonvoid
)
return
target
;
else
return
const0_rtx
;
}
</s>

Expand an expression EXP that calls a built-in function , with result going to TARGET if that 's convenient ( and in mode MODE if that 's convenient ) . SUBTARGET may be used as the target for computing one of EXP 's operands . IGNORE is nonzero if the value is to be ignored .


<s>
static
int
s390_sched_variable_issue
(
FILE
*
file
,
int
verbose
,
rtx_insn
*
insn
,
int
more
)
{
last_scheduled_insn
=
insn
;
if
(
s390_tune
>=
PROCESSOR_2827_ZEC12
&&
reload_completed
&&
recog_memoized
(
insn
)
>=
0
)
{
unsigned
int
mask
=
s390_get_sched_attrmask
(
insn
)
;
if
(
(
mask
&
S390_SCHED_ATTR_MASK_CRACKED
)
!=
0
||
(
mask
&
S390_SCHED_ATTR_MASK_EXPANDED
)
!=
0
)
s390_sched_state
=
S390_SCHED_STATE_CRACKED
;
else
if
(
(
mask
&
S390_SCHED_ATTR_MASK_ENDGROUP
)
!=
0
||
(
mask
&
S390_SCHED_ATTR_MASK_GROUPALONE
)
!=
0
)
s390_sched_state
=
S390_SCHED_STATE_NORMAL
;
else
{
switch
(
s390_sched_state
)
{
case
0
:
case
1
:
case
2
:
case
S390_SCHED_STATE_NORMAL
:
if
(
s390_sched_state
==
S390_SCHED_STATE_NORMAL
)
s390_sched_state
=
1
;
else
s390_sched_state
++
;
break
;
case
S390_SCHED_STATE_CRACKED
:
s390_sched_state
=
S390_SCHED_STATE_NORMAL
;
break
;
}
}
if
(
s390_tune
==
PROCESSOR_2964_Z13
)
{
int
units
,
i
;
unsigned
unit_mask
,
m
=
1
;
unit_mask
=
s390_get_unit_mask
(
insn
,
&
units
)
;
gcc_assert
(
units
<=
MAX_SCHED_UNITS
)
;
for
(
i
=
0
;
i
<
units
;
i
++
,
m
<<=
1
)
if
(
m
&
unit_mask
)
last_scheduled_unit_distance
[
i
]
=
0
;
else
if
(
last_scheduled_unit_distance
[
i
]
<
MAX_SCHED_MIX_DISTANCE
)
last_scheduled_unit_distance
[
i
]
++
;
}
if
(
verbose
>
5
)
{
unsigned
int
sched_mask
;
sched_mask
=
s390_get_sched_attrmask
(
insn
)
;
fprintf
(
file
,
";;\t\tBACKEND: insn %d: "
,
INSN_UID
(
insn
)
)
;
PRINT_SCHED_ATTR
(
S390_SCHED_ATTR_MASK_CRACKED
,
cracked
)
;
PRINT_SCHED_ATTR
(
S390_SCHED_ATTR_MASK_EXPANDED
,
expanded
)
;
PRINT_SCHED_ATTR
(
S390_SCHED_ATTR_MASK_ENDGROUP
,
endgroup
)
;
PRINT_SCHED_ATTR
(
S390_SCHED_ATTR_MASK_GROUPALONE
,
groupalone
)
;
if
(
s390_tune
==
PROCESSOR_2964_Z13
)
{
unsigned
int
unit_mask
,
m
=
1
;
int
units
,
j
;
unit_mask
=
s390_get_unit_mask
(
insn
,
&
units
)
;
fprintf
(
file
,
"(units:"
)
;
for
(
j
=
0
;
j
<
units
;
j
++
,
m
<<=
1
)
if
(
m
&
unit_mask
)
fprintf
(
file
,
" %d"
,
j
)
;
fprintf
(
file
,
")"
)
;
}
fprintf
(
file
,
" sched state: %d\n"
,
s390_sched_state
)
;
if
(
s390_tune
==
PROCESSOR_2964_Z13
)
{
int
units
,
j
;
s390_get_unit_mask
(
insn
,
&
units
)
;
fprintf
(
file
,
";;\t\tBACKEND: units unused for: "
)
;
for
(
j
=
0
;
j
<
units
;
j
++
)
fprintf
(
file
,
"%d:%d "
,
j
,
last_scheduled_unit_distance
[
j
]
)
;
fprintf
(
file
,
"\n"
)
;
}
}
}
if
(
GET_CODE
(
PATTERN
(
insn
)
)
!=
USE
&&
GET_CODE
(
PATTERN
(
insn
)
)
!=
CLOBBER
)
return
more
1
;
else
return
more
;
}
</s>

This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after the scheduler has issued INSN . It stores the last issued insn into last_scheduled_insn in order to make it available for s390_sched_reorder .


<s> TargetPassConfig * XNCMTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new XNCMPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s>
bool
WaitInsert
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
!
MF
.
getFunction
(
)
.
hasFnAttribute
(
Attribute
::
StrictFP
)
)
return
false
;
const
X86Subtarget
&
ST
=
MF
.
getSubtarget
<
X86Subtarget
>
(
)
;
TII
=
ST
.
getInstrInfo
(
)
;
bool
Changed
=
false
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
for
(
MachineBasicBlock
::
iterator
MI
=
MBB
.
begin
(
)
;
MI
!=
MBB
.
end
(
)
;
++
MI
)
{
if
(
!
isX87Instruction
(
*
MI
)
)
continue
;
if
(
!
(
MI
->
mayRaiseFPException
(
)
||
MI
->
mayLoadOrStore
(
)
)
||
isX87ControlInstruction
(
*
MI
)
)
continue
;
MachineBasicBlock
::
iterator
AfterMI
=
std
::
next
(
MI
)
;
if
(
AfterMI
!=
MBB
.
end
(
)
&&
isX87Instruction
(
*
AfterMI
)
&&
!
isX87NonWaitingControlInstruction
(
*
AfterMI
)
)
continue
;
BuildMI
(
MBB
,
AfterMI
,
MI
->
getDebugLoc
(
)
,
TII
->
get
(
X86
::
WAIT
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"\nInsert wait after:\t"
<<
*
MI
)
;
++
MI
;
Changed
=
true
;
}
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> SDNode * SparcDAGToDAGISel :: getGlobalBaseReg ( ) { Register GlobalBaseReg = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static void iq2000_annotate_frame_insn ( rtx_insn * insn , rtx dwarf_pattern ) { RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = alloc_EXPR_LIST ( REG_FRAME_RELATED_EXPR , dwarf_pattern , REG_NOTES ( insn ) ) ; } </s>

Make INSN frame related and note that it performs the frame-related operation DWARF_PATTERN .


<s> bool ix86_valid_target_attribute_p ( tree fndecl , tree ARG_UNUSED ( name ) , tree args , int flags ) { struct gcc_options func_options , func_options_set ; tree new_target , new_optimize ; bool ret = true ; if ( TREE_VALUE ( args ) && TREE_CODE ( TREE_VALUE ( args ) ) == STRING_CST && TREE_CHAIN ( args ) == NULL_TREE && strcmp ( TREE_STRING_POINTER ( TREE_VALUE ( args ) ) , "default" ) == 0 ) return true ; if ( ( DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) == target_attribute_cache [ 1 ] || DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) == NULL_TREE ) && ( DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) == target_attribute_cache [ 2 ] || DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) == NULL_TREE ) && simple_cst_list_equal ( args , target_attribute_cache [ 0 ] ) ) { DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = target_attribute_cache [ 1 ] ; DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) = target_attribute_cache [ 2 ] ; return true ; } tree old_optimize = build_optimization_node ( & global_options , & global_options_set ) ; tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( ! func_optimize ) func_optimize = old_optimize ; memset ( & func_options , 0 , sizeof ( func_options ) ) ; init_options_struct ( & func_options , NULL ) ; lang_hooks . init_options_struct ( & func_options ) ; memset ( & func_options_set , 0 , sizeof ( func_options_set ) ) ; cl_optimization_restore ( & func_options , & func_options_set , TREE_OPTIMIZATION ( func_optimize ) ) ; tree old_target = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( old_target == NULL_TREE ) old_target = target_option_default_node ; cl_target_option_restore ( & func_options , & func_options_set , TREE_TARGET_OPTION ( old_target ) ) ; new_target = ix86_valid_target_attribute_tree ( fndecl , args , & func_options , & func_options_set , flags == 1 ) ; new_optimize = build_optimization_node ( & func_options , & func_options_set ) ; if ( new_target == error_mark_node ) ret = false ; else if ( new_target ) { if ( DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) == NULL_TREE && DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) == NULL_TREE ) { target_attribute_cache [ 0 ] = copy_list ( args ) ; target_attribute_cache [ 1 ] = new_target ; target_attribute_cache [ 2 ] = old_optimize != new_optimize ? new_optimize : NULL_TREE ; } DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = new_target ; if ( old_optimize != new_optimize ) DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) = new_optimize ; } return ret ; } </s>

Hook to validate attribute ( ( target ( `` string '' ) ) ) .


<s>
int
R600InstrInfo
::
getOperandIdx
(
unsigned
Opcode
,
R600Operands
::
Ops
Op
)
const
{
unsigned
TargetFlags
=
get
(
Opcode
)
.
TSFlags
;
unsigned
OpTableIdx
;
if
(
!
HAS_NATIVE_OPERANDS
(
TargetFlags
)
)
{
switch
(
Op
)
{
case
R600Operands
::
DST
:
return
0
;
case
R600Operands
::
SRC0
:
return
1
;
case
R600Operands
::
SRC1
:
return
2
;
case
R600Operands
::
SRC2
:
return
3
;
default
:
assert
(
!
"Unknown operand type for instruction"
)
;
return
1
;
}
}
if
(
TargetFlags
&
R600_InstFlag
::
OP1
)
{
OpTableIdx
=
0
;
}
else
if
(
TargetFlags
&
R600_InstFlag
::
OP2
)
{
OpTableIdx
=
1
;
}
else
{
assert
(
(
TargetFlags
&
R600_InstFlag
::
OP3
)
&&
"OP1, OP2, or OP3 not defined "
"for this instruction"
)
;
OpTableIdx
=
2
;
}
return
R600Operands
::
ALUOpTable
[
OpTableIdx
]
[
Op
]
;
}
</s>

Get the index of Op for the given Opcode .


<s>
MachineBasicBlock
::
iterator
SIFrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
int64_t
Amount
=
I
->
getOperand
(
0
)
.
getImm
(
)
;
if
(
Amount
==
0
)
return
MBB
.
erase
(
I
)
;
const
GCNSubtarget
&
ST
=
MF
.
getSubtarget
<
GCNSubtarget
>
(
)
;
const
SIInstrInfo
*
TII
=
ST
.
getInstrInfo
(
)
;
const
DebugLoc
&
DL
=
I
->
getDebugLoc
(
)
;
unsigned
Opc
=
I
->
getOpcode
(
)
;
bool
IsDestroy
=
Opc
==
TII
->
getCallFrameDestroyOpcode
(
)
;
uint64_t
CalleePopAmount
=
IsDestroy
I
->
getOperand
(
1
)
.
getImm
(
)
:
0
;
if
(
!
hasReservedCallFrame
(
MF
)
)
{
Amount
=
alignTo
(
Amount
,
getStackAlign
(
)
)
;
assert
(
isUInt
<
32
>
(
Amount
)
&&
"exceeded stack address space size"
)
;
const
SIMachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
SIMachineFunctionInfo
>
(
)
;
Register
SPReg
=
MFI
->
getStackPtrOffsetReg
(
)
;
unsigned
Op
=
IsDestroy
AMDGPU
::
S_SUB_U32
:
AMDGPU
::
S_ADD_U32
;
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
Op
)
,
SPReg
)
.
addReg
(
SPReg
)
.
addImm
(
Amount
*
ST
.
getWavefrontSize
(
)
)
;
}
else
if
(
CalleePopAmount
!=
0
)
{
llvm_unreachable
(
"is this used?"
)
;
}
return
MBB
.
erase
(
I
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


"ERROR: Unknown type of MachineOperand: "

getMachineOpValue - Return binary encoding of operand .


<s> const char * getSymbol ( ) const { return S . c_str ( ) ; } </s>

Get the target address and flags for the named symbol .


<s> unsigned getScratchRSrcReg ( ) const { return ScratchRSrcReg ; } </s>

Returns the physical register reserved for use as the resource descriptor for scratch accesses .


<s> const RISCVInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> void TPCFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> void NyuziDAGToDAGISel :: Select ( SDNode * N ) { if ( N -> isMachineOpcode ( ) ) return ; SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> NVPTXSubtarget :: NVPTXSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool is64Bit ) : NVPTXGenSubtargetInfo ( TT , CPU , FS ) , Is64Bit ( is64Bit ) , PTXVersion ( 0 ) , SmVersion ( 20 ) , DL ( computeDataLayout ( is64Bit ) ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( ( const NVPTXTargetMachine & ) TM ) , TSInfo ( & DL ) , FrameLowering ( * this ) { Triple T ( TT ) ; if ( T . getOS ( ) == Triple :: NVCL ) drvInterface = NVPTX :: NVCL ; else drvInterface = NVPTX :: CUDA ; } </s>

This constructor initializes the data members to match that of the specified module .

NVPTX NVPTX NVPTX NVPTX 0 20 NVPTX NVPTX::NVCL NVPTX::CUDA


<s> int attr_length_indirect_call ( rtx insn ) { unsigned long distance = - 1 ; unsigned long total = IN_NAMED_SECTION_P ( cfun -> decl ) ? 0 : total_code_bytes ; if ( INSN_ADDRESSES_SET_P ( ) ) { distance = ( total + insn_current_reference_address ( insn ) ) ; if ( distance < total ) distance = - 1 ; } if ( TARGET_64BIT ) return 12 ; if ( TARGET_FAST_INDIRECT_CALLS || ( ! TARGET_PORTABLE_RUNTIME && ( ( TARGET_PA_20 && ! TARGET_SOM && distance < 7600000 ) || distance < 240000 ) ) ) return 8 ; if ( flag_pic ) return 24 ; if ( TARGET_PORTABLE_RUNTIME ) return 20 ; return 12 ; } </s>

Return the attribute length of the indirect call instruction INSN . The length must match the code generated by output_indirect call . The returned length includes the delay slot . Currently , the delay slot of an indirect call sequence is not exposed and it is used by the sequence itself .


<s> const uint32_t * VERegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { switch ( CC ) { default : return CSR_RegMask ; case CallingConv :: PreserveAll : return CSR_preserve_all_RegMask ; } } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> StringRef getPassName ( ) const override { return RISCV_VECTOR_REMOVE_REDUNDANCY_VSETVL ; } </s>

getPassName - Return a nice clean name for a pass .


<s> void print ( raw_ostream & OS , const TargetMachine * TM = 0 ) const { const TargetRegisterInfo * TRI = TM ? TM -> getRegisterInfo ( ) : 0 ; if ( isReg ( ) ) { OS << PrintReg ( Contents . R . Reg , TRI , Contents . R . Sub ) ; } if ( isImm ( ) ) { OS << Contents . ImmVal ; } } </s>

print - Print a debug representation of the operand to the given stream .


<s> int pic_address_needs_scratch ( rtx x ) { if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS ) { rtx p0 , p1 ; p0 = XEXP ( XEXP ( x , 0 ) , 0 ) ; p1 = XEXP ( XEXP ( x , 0 ) , 1 ) ; if ( ( GET_CODE ( p0 ) == SYMBOL_REF || GET_CODE ( p0 ) == LABEL_REF ) && ( GET_CODE ( p1 ) == CONST_INT ) && ( flag_pic == 2 || microblaze_tls_symbol_p ( p0 ) || ! SMALL_INT ( p1 ) ) ) return 1 ; } return 0 ; } </s>

Return true if X is an address which needs a temporary register when reloaded while generating PIC code .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 Discriminate Memory Operands"
;
}
</s>


<s> bool X86FixupSetCCPass :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; MRI = & MF . getRegInfo ( ) ; TII = MF . getSubtarget < X86Subtarget > ( ) . getInstrInfo ( ) ; SmallVector < MachineInstr * , 4 > ToErase ; for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( ! isSetCCr ( MI . getOpcode ( ) ) ) continue ; MachineInstr * ZExt = nullptr ; for ( auto & Use : MRI -> use_instructions ( MI . getOperand ( 0 ) . getReg ( ) ) ) if ( Use . getOpcode ( ) == X86 :: MOVZX32rr8 ) ZExt = & Use ; if ( ! ZExt ) continue ; MachineInstr * FlagsDefMI = findFlagsImpDef ( MI . getParent ( ) , MachineBasicBlock :: reverse_iterator ( & MI ) ) ; if ( ! FlagsDefMI ) continue ; if ( impUsesFlags ( FlagsDefMI ) ) continue ; ++ NumSubstZexts ; Changed = true ; const TargetRegisterClass * RC = MF . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ? & X86 :: GR32RegClass : & X86 :: GR32_ABCDRegClass ; unsigned ZeroReg = MRI -> createVirtualRegister ( RC ) ; unsigned InsertReg = MRI -> createVirtualRegister ( RC ) ; BuildMI ( MBB , FlagsDefMI , MI . getDebugLoc ( ) , TII -> get ( X86 :: MOV32r0 ) , ZeroReg ) ; BuildMI ( * ZExt -> getParent ( ) , ZExt , ZExt -> getDebugLoc ( ) , TII -> get ( X86 :: INSERT_SUBREG ) , InsertReg ) . addReg ( ZeroReg ) . addReg ( MI . getOperand ( 0 ) . getReg ( ) ) . addImm ( X86 :: sub_8bit ) ; MRI -> replaceRegWith ( ZExt -> getOperand ( 0 ) . getReg ( ) , InsertReg ) ; ToErase . push_back ( ZExt ) ; } } for ( auto & I : ToErase ) I -> eraseFromParent ( ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s>
bool
JVMInstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
MachineInstr
*
UBR
=
nullptr
;
MachineInstr
*
CBR
=
nullptr
;
for
(
auto
ritr
=
MBB
.
instr_rbegin
(
)
;
ritr
!=
MBB
.
instr_rend
(
)
;
ritr
++
)
{
MachineInstr
&
MI
=
*
ritr
;
if
(
!
MI
.
isBranch
(
)
)
break
;
if
(
!
IsConditionalBranch
(
MI
)
)
{
assert
(
!
UBR
&&
"Multiple-unconditional branches"
)
;
UBR
=
&
MI
;
}
else
{
assert
(
!
CBR
&&
"Multiple-conditional branches"
)
;
CBR
=
&
MI
;
}
}
if
(
nullptr
==
CBR
&&
nullptr
==
UBR
)
return
true
;
else
if
(
UBR
&&
!
CBR
)
{
TBB
=
UBR
->
getOperand
(
0
)
.
getMBB
(
)
;
}
else
if
(
CBR
)
{
TBB
=
CBR
->
getOperand
(
CBR
->
getNumOperands
(
)
1
)
.
getMBB
(
)
;
for
(
unsigned
i
=
0
;
i
<
CBR
->
getNumOperands
(
)
2
;
i
++
)
Cond
.
push_back
(
CBR
->
getOperand
(
i
)
)
;
FBB
=
UBR
UBR
->
getOperand
(
0
)
.
getMBB
(
)
:
nullptr
;
}
else
{
llvm_unreachable
(
"Unhandled banching"
)
;
}
return
false
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> void umips_output_load_store_pair ( bool load_p , rtx * operands ) { rtx reg1 , reg2 , mem1 , mem2 ; if ( load_p ) { reg1 = operands [ 0 ] ; reg2 = operands [ 2 ] ; mem1 = operands [ 1 ] ; mem2 = operands [ 3 ] ; } else { reg1 = operands [ 1 ] ; reg2 = operands [ 3 ] ; mem1 = operands [ 0 ] ; mem2 = operands [ 2 ] ; } if ( REGNO ( reg2 ) == REGNO ( reg1 ) + 1 ) { umips_output_load_store_pair_1 ( load_p , reg1 , mem1 ) ; return ; } gcc_assert ( REGNO ( reg1 ) == REGNO ( reg2 ) + 1 ) ; umips_output_load_store_pair_1 ( load_p , reg2 , mem2 ) ; } </s>

Output the assembly instruction for a microMIPS LWP or SWP instruction . LOAD_P and OPERANDS are as for umips_load_store_pair_p .


<s> DecodeStatus LanaiDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & VStream , raw_ostream & CStream ) const { uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Bytes , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTableLanai32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { PostOperandDecodeAdjust ( Instr , Insn ) ; Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s> InstructionCost AArch64TTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * DataTy , const Value * Ptr , bool VariableMask , Align Alignment , TTI :: TargetCostKind CostKind , const Instruction * I ) { if ( useNeonVector ( DataTy ) ) return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , CostKind , I ) ; auto * VT = cast < VectorType > ( DataTy ) ; auto LT = TLI -> getTypeLegalizationCost ( DL , DataTy ) ; if ( ! LT . first . isValid ( ) ) return InstructionCost :: getInvalid ( ) ; if ( cast < VectorType > ( DataTy ) -> getElementCount ( ) == ElementCount :: getScalable ( 1 ) ) return InstructionCost :: getInvalid ( ) ; ElementCount LegalVF = LT . second . getVectorElementCount ( ) ; InstructionCost MemOpCost = getMemoryOpCost ( Opcode , VT -> getElementType ( ) , Alignment , 0 , CostKind , I ) ; MemOpCost *= getSVEGatherScatterOverhead ( Opcode ) ; return LT . first * MemOpCost * getMaxNumElements ( LegalVF ) ; } </s>

Calculate the cost of Gather / Scatter operation .


<s> const char * output_plussi ( rtx * operands , bool need_flags ) { machine_mode mode = GET_MODE ( operands [ 0 ] ) ; gcc_assert ( mode == SImode ) ; if ( GET_CODE ( operands [ 2 ] ) == CONST_INT && register_operand ( operands [ 1 ] , VOIDmode ) ) { HOST_WIDE_INT intval = INTVAL ( operands [ 2 ] ) ; if ( TARGET_H8300SX && ( intval >= 1 && intval <= 7 ) ) return "add.l\t%S2,%S0" ; if ( TARGET_H8300SX && ( intval >= - 7 && intval <= - 1 ) ) return "sub.l\t%G2,%S0" ; switch ( ( unsigned int ) intval & 0xffffffff ) { case 0x00000001 : if ( need_flags ) return "inc.l\t#1,%S0" ; else return "adds\t%2,%S0" ; case 0x00000002 : if ( need_flags ) return "inc.l\t#2,%S0" ; else return "adds\t%2,%S0" ; case 0xffffffff : if ( need_flags ) return "dec.l\t#1,%S0" ; else return "subs\t%G2,%S0" ; case 0xfffffffe : if ( need_flags ) return "dec.l\t#2,%S0" ; else return "subs\t%G2,%S0" ; case 0x00000004 : if ( ! need_flags ) return "adds\t%2,%S0" ; case 0xfffffffc : if ( ! need_flags ) return "subs\t%G2,%S0" ; case 0x00010000 : case 0x00020000 : if ( ! need_flags ) { operands [ 2 ] = GEN_INT ( intval >> 16 ) ; return "inc.w\t%2,%e0" ; } case 0xffff0000 : case 0xfffe0000 : if ( ! need_flags ) { operands [ 2 ] = GEN_INT ( intval >> 16 ) ; return "dec.w\t%G2,%e0" ; } } if ( ( intval & 0xffff ) == 0 ) { operands [ 2 ] = GEN_INT ( intval >> 16 ) ; return "add.w\t%2,%e0" ; } } if ( GET_CODE ( operands [ 2 ] ) == CONST_INT && INTVAL ( operands [ 2 ] ) < 0 ) { operands [ 2 ] = GEN_INT ( - INTVAL ( operands [ 2 ] ) ) ; return "sub.l\t%S2,%S0" ; } return "add.l\t%S2,%S0" ; } </s>


<s> int mmix_legitimate_address ( enum machine_mode mode ATTRIBUTE_UNUSED , rtx x , int strict_checking ) { ( ( strict_checking \ && ( REGNO ( X ) <= MMIX_LAST_GENERAL_REGISTER \ || ( reg_renumber [ REGNO ( X ) ] > 0 \ && reg_renumber [ REGNO ( X ) ] <= MMIX_LAST_GENERAL_REGISTER ) ) ) \ || ( ! strict_checking \ && ( REGNO ( X ) <= MMIX_LAST_GENERAL_REGISTER \ || REGNO ( X ) >= FIRST_PSEUDO_REGISTER \ || REGNO ( X ) == ARG_POINTER_REGNUM ) ) ) if ( REG_P ( x ) && MMIX_REG_OK ( x ) ) return 1 ; if ( GET_CODE ( x ) == PLUS ) { rtx x1 = XEXP ( x , 0 ) ; rtx x2 = XEXP ( x , 1 ) ; if ( ! REG_P ( x1 ) ) { rtx tem = x1 ; x1 = x2 ; x2 = tem ; } if ( ! REG_P ( x1 ) || ! MMIX_REG_OK ( x1 ) ) return TARGET_BASE_ADDRESSES && mmix_constant_address_p ( x ) ; if ( REG_P ( x2 ) && MMIX_REG_OK ( x2 ) ) return 1 ; if ( GET_CODE ( x2 ) == CONST_INT && CONST_OK_FOR_LETTER_P ( INTVAL ( x2 ) , 'I' ) ) return 1 ; return 0 ; } return TARGET_BASE_ADDRESSES && mmix_constant_address_p ( x ) ; } </s>

Return 1 if the address is OK , otherwise 0 . Used by GO_IF_LEGITIMATE_ADDRESS .


<s> bool writeNopData ( raw_ostream & OS , uint64_t Count ) const override { return false ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> static unsigned int aarch64_estimated_sve_vq ( ) { return estimated_poly_value ( BITS_PER_SVE_VECTOR ) / 128 ; } </s>

Return an estimate for the number of quadwords in an SVE vector . This is equivalent to the number of Advanced SIMD vectors in an SVE vector .


<s> bool SystemZInstrInfo :: areMemAccessesTriviallyDisjoint ( const MachineInstr & MIa , const MachineInstr & MIb ) const { if ( ! MIa . hasOneMemOperand ( ) || ! MIb . hasOneMemOperand ( ) ) return false ; MachineMemOperand * MMOa = * MIa . memoperands_begin ( ) ; MachineMemOperand * MMOb = * MIb . memoperands_begin ( ) ; const Value * VALa = MMOa -> getValue ( ) ; const Value * VALb = MMOb -> getValue ( ) ; bool SameVal = ( VALa && VALb && ( VALa == VALb ) ) ; if ( ! SameVal ) { const PseudoSourceValue * PSVa = MMOa -> getPseudoValue ( ) ; const PseudoSourceValue * PSVb = MMOb -> getPseudoValue ( ) ; if ( PSVa && PSVb && ( PSVa == PSVb ) ) SameVal = true ; } if ( SameVal ) { int OffsetA = MMOa -> getOffset ( ) , OffsetB = MMOb -> getOffset ( ) ; int WidthA = MMOa -> getSize ( ) , WidthB = MMOb -> getSize ( ) ; int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB ; int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA ; int LowWidth = ( LowOffset == OffsetA ) ? WidthA : WidthB ; if ( LowOffset + LowWidth <= HighOffset ) return true ; } return false ; } </s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> static const MachineOperand & getLdStBaseOp ( const MachineInstr & MI ) { unsigned Idx = isPairedLdSt ( MI ) || AArch64InstrInfo :: isPreLdSt ( MI ) ? 2 : 1 ; return MI . getOperand ( Idx ) ; } </s>

Returns the base register operator of a load/store .


<s> std :: vector < std :: string > sub ( Px a , Bx b ) { return D ( "sub" , R ( a ) , R ( b ) ) ; } </s>

sub - Return the result of replacing the first match of the regex in String with the Repl string .


<s> void AMDGPUPassConfig :: addPostRegAlloc ( ) { const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . getGeneration ( ) > AMDGPUSubtarget :: NORTHERN_ISLANDS ) { addPass ( createSIPrepareScratchRegs ( ) , false ) ; addPass ( createSIShrinkInstructionsPass ( ) , false ) ; } } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool tls_symbolic_reference_mentioned_p ( rtx op ) { const char * fmt ; int i ; if ( GET_CODE ( op ) == SYMBOL_REF ) return tls_symbolic_operand ( op ) ; fmt = GET_RTX_FORMAT ( GET_CODE ( op ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( op ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( op , i ) - 1 ; j >= 0 ; j -- ) if ( tls_symbolic_reference_mentioned_p ( XVECEXP ( op , i , j ) ) ) return true ; } else if ( fmt [ i ] == 'e' && tls_symbolic_reference_mentioned_p ( XEXP ( op , i ) ) ) return true ; } return false ; } </s>

Return true if OP contains a reference to a thread-local symbol .


<s> bool M68kFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { auto & MRI = * static_cast < const M68kRegisterInfo * > ( TRI ) ; auto DL = MBB . findDebugLoc ( MI ) ; int FI = 0 ; unsigned Mask = 0 ; for ( const auto & Info : CSI ) { FI = std :: max ( FI , Info . getFrameIdx ( ) ) ; Register Reg = Info . getReg ( ) ; unsigned Shift = MRI . getSpillRegisterOrder ( Reg ) ; Mask |= 1 << Shift ; } auto I = M68k :: addFrameReference ( BuildMI ( MBB , MI , DL , TII . get ( M68k :: MOVM32pm ) ) , FI ) . addImm ( Mask ) . setMIFlag ( MachineInstr :: FrameSetup ) ; const MachineFunction & MF = * MBB . getParent ( ) ; const MachineRegisterInfo & RI = MF . getRegInfo ( ) ; for ( const auto & Info : CSI ) { Register Reg = Info . getReg ( ) ; bool IsLiveIn = RI . isLiveIn ( Reg ) ; if ( ! IsLiveIn ) MBB . addLiveIn ( Reg ) ; I . addReg ( Reg , IsLiveIn ? RegState :: Implicit : RegState :: ImplicitKill ) ; M68k :: addMemOperand ( I , Info . getFrameIdx ( ) , 0 ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


Remove - Removes a function pass from the registration list .


<s>
static
void
conditionalize_after_sched
(
void
)
{
basic_block
bb
;
rtx_insn
*
insn
;
FOR_EACH_BB_FN
(
bb
,
cfun
)
FOR_BB_INSNS
(
bb
,
insn
)
{
unsigned
uid
=
INSN_UID
(
insn
)
;
rtx
cond
;
if
(
!
NONDEBUG_INSN_P
(
insn
)
||
uid
>=
INSN_INFO_LENGTH
)
continue
;
cond
=
INSN_INFO_ENTRY
(
uid
)
.
new_cond
;
if
(
cond
==
NULL_RTX
)
continue
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Conditionalizing insn %d\n"
,
uid
)
;
predicate_insn
(
insn
,
cond
,
true
)
;
}
}
</s>

For every insn that has an entry in the new_conditions vector , give it the appropriate predicate .


<s>
void
ARM64AsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
Value
=
adjustFixupValue
(
Fixup
.
getKind
(
)
,
Value
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool ARMBaseInstrInfo :: isPredicable ( MachineInstr * MI ) const { const TargetInstrDesc & TID = MI -> getDesc ( ) ; if ( ! TID . isPredicable ( ) ) return false ; if ( ( TID . TSFlags & ARMII :: DomainMask ) == ARMII :: DomainNEON ) { ARMFunctionInfo * AFI = MI -> getParent ( ) -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; return AFI -> isThumb2Function ( ) ; } return true ; } </s>

Return true if the specified instruction can be predicated .

ARM ARM ARMII::DomainMask ARMII::DomainNEON ARM ARM


<s> static rtx mips_expand_builtin_direct ( enum insn_code icode , rtx target , tree arglist , bool has_target ) { rtx ops [ MAX_RECOG_OPERANDS ] ; int i = 0 ; if ( has_target ) { ops [ 0 ] = mips_prepare_builtin_target ( icode , 0 , target ) ; i = 1 ; } for ( ; i < insn_data [ icode ] . n_operands && arglist != 0 ; i ++ ) ops [ i ] = mips_prepare_builtin_arg ( icode , i , & arglist ) ; switch ( i ) { case 2 : emit_insn ( GEN_FCN ( icode ) ( ops [ 0 ] , ops [ 1 ] ) ) ; break ; case 3 : emit_insn ( GEN_FCN ( icode ) ( ops [ 0 ] , ops [ 1 ] , ops [ 2 ] ) ) ; break ; case 4 : emit_insn ( GEN_FCN ( icode ) ( ops [ 0 ] , ops [ 1 ] , ops [ 2 ] , ops [ 3 ] ) ) ; break ; default : gcc_unreachable ( ) ; } return target ; } </s>

Expand a MIPS_BUILTIN_DIRECT function . ICODE is the code of the .md pattern and ARGLIST is the list of function arguments . TARGET , if nonnull , suggests a good place to put the result . HAS_TARGET indicates the function must return something .


<s> virtual const Dcpu16RegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static inline HOST_WIDE_INT htm_spr_num ( enum rs6000_builtins code ) { if ( code == HTM_BUILTIN_GET_TFHAR || code == HTM_BUILTIN_SET_TFHAR ) return TFHAR_SPR ; else if ( code == HTM_BUILTIN_GET_TFIAR || code == HTM_BUILTIN_SET_TFIAR ) return TFIAR_SPR ; else if ( code == HTM_BUILTIN_GET_TEXASR || code == HTM_BUILTIN_SET_TEXASR ) return TEXASR_SPR ; gcc_assert ( code == HTM_BUILTIN_GET_TEXASRU || code == HTM_BUILTIN_SET_TEXASRU ) ; return TEXASRU_SPR ; } </s>

Return the appropriate SPR number associated with the given builtin .


<s> static void build_vs_offset ( function_builder & b , const char * signature , const function_group_info & group , bool force_direct_overloads = false ) { build_32_64 ( b , signature , group , MODE_u32base_offset , MODE_u64base_offset , force_direct_overloads ) ; } </s>

Like build_v_base , but for functions that also take a scalar byte offset .


<s> bool isValid ( ) { return isValidModel ; } </s>

Returns true if this iterator is still pointing at a valid entry .


<s>
SDValue
MSP430TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
SHL
:
case
ISD
::
SRL
:
case
ISD
::
SRA
:
return
LowerShifts
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ExternalSymbol
:
return
LowerExternalSymbol
(
Op
,
DAG
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SIGN_EXTEND
:
return
LowerSIGN_EXTEND
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
return
SDValue
(
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

MSP430
MSP430
ISD::SHL
ISD::SRL
ISD::SRA
ISD::GlobalAddress
ISD::BlockAddress
ISD::ExternalSymbol
ISD::SETCC
ISD::BR_CC
ISD::SELECT_CC
ISD::SIGN_EXTEND
ISD::RETURNADDR
ISD::FRAMEADDR
"unimplemented operand"


<s> bool ARMPassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge ) addPass ( createGlobalMergePass ( TM ) ) ; return false ; } </s>


<s> int msp430_hard_regno_nregs_with_padding ( int regno ATTRIBUTE_UNUSED , machine_mode mode ) { if ( mode == PSImode ) return 2 ; return msp430_hard_regno_nregs ( regno , mode ) ; } </s>


<s> outliner :: OutlinedFunction ARMBaseInstrInfo :: getOutliningCandidateInfo ( std :: vector < outliner :: Candidate > & RepeatedSequenceLocs ) const { outliner :: Candidate & FirstCand = RepeatedSequenceLocs [ 0 ] ; unsigned SequenceSize = std :: accumulate ( FirstCand . front ( ) , std :: next ( FirstCand . back ( ) ) , 0 , [ this ] ( unsigned Sum , const MachineInstr & MI ) { return Sum + getInstSizeInBytes ( MI ) ; } ) ; unsigned FlagsSetInAll = 0xF ; const TargetRegisterInfo & TRI = getRegisterInfo ( ) ; std :: for_each ( RepeatedSequenceLocs . begin ( ) , RepeatedSequenceLocs . end ( ) , [ & FlagsSetInAll ] ( outliner :: Candidate & C ) { FlagsSetInAll &= C . Flags ; } ) ; auto CantGuaranteeValueAcrossCall = [ & TRI ] ( outliner :: Candidate & C ) { if ( C . Flags & UnsafeRegsDead ) return false ; C . initLRU ( TRI ) ; LiveRegUnits LRU = C . LRU ; return ( ! LRU . available ( ARM :: R12 ) || ! LRU . available ( ARM :: CPSR ) ) ; } ; if ( ! ( FlagsSetInAll & UnsafeRegsDead ) ) { RepeatedSequenceLocs . erase ( std :: remove_if ( RepeatedSequenceLocs . begin ( ) , RepeatedSequenceLocs . end ( ) , CantGuaranteeValueAcrossCall ) , RepeatedSequenceLocs . end ( ) ) ; if ( RepeatedSequenceLocs . size ( ) < 2 ) return outliner :: OutlinedFunction ( ) ; } unsigned LastInstrOpcode = RepeatedSequenceLocs [ 0 ] . back ( ) -> getOpcode ( ) ; auto SetCandidateCallInfo = [ & RepeatedSequenceLocs ] ( unsigned CallID , unsigned NumBytesForCall ) { for ( outliner :: Candidate & C : RepeatedSequenceLocs ) C . setCallInfo ( CallID , NumBytesForCall ) ; } ; auto Costs = std :: make_unique < OutlinerCosts > ( Subtarget ) ; unsigned FrameID = 0 ; unsigned NumBytesToCreateFrame = 0 ; if ( RepeatedSequenceLocs [ 0 ] . back ( ) -> isTerminator ( ) ) { FrameID = MachineOutlinerTailCall ; NumBytesToCreateFrame = Costs -> FrameTailCall ; SetCandidateCallInfo ( MachineOutlinerTailCall , Costs -> CallTailCall ) ; } else if ( LastInstrOpcode == ARM :: BL || LastInstrOpcode == ARM :: BLX || LastInstrOpcode == ARM :: tBL || LastInstrOpcode == ARM :: tBLXr || LastInstrOpcode == ARM :: tBLXi ) { FrameID = MachineOutlinerThunk ; NumBytesToCreateFrame = Costs -> FrameThunk ; SetCandidateCallInfo ( MachineOutlinerThunk , Costs -> CallThunk ) ; } else return outliner :: OutlinedFunction ( ) ; return outliner :: OutlinedFunction ( RepeatedSequenceLocs , SequenceSize , NumBytesToCreateFrame , FrameID ) ; } </s>

Returns a outliner : :OutlinedFunction struct containing target-specific information for a set of outlining candidates .


<s> bool addPreISel ( ) override { if ( PatmosSinglePathInfo :: isEnabled ( ) ) { addPass ( createUnifyFunctionExitNodesPass ( ) ) ; addPass ( createLowerSwitchPass ( ) ) ; addPass ( createPatmosSPClonePass ( ) ) ; } addPass ( createPatmosIntrinsicEliminationPass ( ) ) ; return PatmosSinglePathInfo :: isEnabled ( ) ; } </s>


<s> void MipsTargetStreamer :: emitStoreWithImmOffset ( unsigned Opcode , unsigned SrcReg , unsigned BaseReg , int64_t Offset , function_ref < unsigned ( ) > GetATReg , SMLoc IDLoc , const MCSubtargetInfo * STI ) { if ( isInt < 16 > ( Offset ) ) { emitRRI ( Opcode , SrcReg , BaseReg , Offset , IDLoc , STI ) ; return ; } unsigned ATReg = GetATReg ( ) ; if ( ! ATReg ) return ; unsigned LoOffset = Offset & 0x0000ffff ; unsigned HiOffset = ( Offset & 0xffff0000 ) >> 16 ; if ( LoOffset & 0x8000 ) HiOffset ++ ; emitRI ( Mips :: LUi , ATReg , HiOffset , IDLoc , STI ) ; if ( BaseReg != Mips :: ZERO ) emitRRR ( Mips :: ADDu , ATReg , ATReg , BaseReg , IDLoc , STI ) ; emitRRI ( Opcode , SrcReg , ATReg , LoOffset , IDLoc , STI ) ; } </s>

Emit a store instruction with an offset .


<s> void function_arg_advance ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int named ATTRIBUTE_UNUSED ) { int count , bytes , words ; bytes = ( mode == BLKmode ) ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ; words = ( bytes + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; cum -> words += words ; cum -> nregs -= words ; if ( cum -> nregs <= 0 ) { cum -> nregs = 0 ; cum -> arg_regs = NULL ; } else { for ( count = 1 ; count <= words ; count ++ ) cum -> arg_regs ++ ; } return ; } </s>

Handle the FUNCTION_ARG_ADVANCE macro . Update the data in CUM to advance over an argument of mode MODE and data type TYPE . TYPE is null for libcalls where that information may not be available .


<s> FastISel * MipsTargetLowering :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) const { const MipsTargetMachine & TM = static_cast < const MipsTargetMachine & > ( funcInfo . MF -> getTarget ( ) ) ; bool UseFastISel = TM . Options . EnableFastISel && Subtarget . hasMips32 ( ) && ! Subtarget . hasMips32r6 ( ) && ! Subtarget . inMips16Mode ( ) && ! Subtarget . inMicroMipsMode ( ) ; if ( ! TM . isPositionIndependent ( ) || ! TM . getABI ( ) . IsO32 ( ) ) UseFastISel = false ; return UseFastISel ? Mips :: createFastISel ( funcInfo , libInfo ) : nullptr ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .

Mips Mips Mips Mips Mips Mips Mips Mips Mips::createFastISel


<s> void MBlazeFrameInfo :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MBlazeInstrInfo & TII = * static_cast < const MBlazeInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MBlazeFunctionInfo * MBlazeFI = MF . getInfo < MBlazeFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; MBlazeFI -> adjustLoadArgsFI ( MFI ) ; MBlazeFI -> adjustStoreVarArgsFI ( MFI ) ; unsigned StackSize = MFI -> getStackSize ( ) ; if ( StackSize == 0 && ! MFI -> adjustsStack ( ) ) return ; int FPOffset = MBlazeFI -> getFPStackOffset ( ) ; int RAOffset = MBlazeFI -> getRAStackOffset ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( MBlaze :: ADDI ) , MBlaze :: R1 ) . addReg ( MBlaze :: R1 ) . addImm ( - StackSize ) ; if ( MFI -> adjustsStack ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( MBlaze :: SWI ) ) . addReg ( MBlaze :: R15 ) . addReg ( MBlaze :: R1 ) . addImm ( RAOffset ) ; } if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( MBlaze :: SWI ) ) . addReg ( MBlaze :: R19 ) . addReg ( MBlaze :: R1 ) . addImm ( FPOffset ) ; BuildMI ( MBB , MBBI , DL , TII . get ( MBlaze :: ADD ) , MBlaze :: R19 ) . addReg ( MBlaze :: R1 ) . addReg ( MBlaze :: R0 ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static void arc_dwarf_emit_irq_save_regs ( void ) { rtx tmp , par , insn , reg ; int i , offset , j ; par = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( irq_ctrl_saved . irq_save_last_reg + 1 + irq_ctrl_saved . irq_save_blink + irq_ctrl_saved . irq_save_lpcount + 1 ) ) ; j = 0 ; offset = UNITS_PER_WORD * ( irq_ctrl_saved . irq_save_last_reg + 1 + irq_ctrl_saved . irq_save_blink + irq_ctrl_saved . irq_save_lpcount ) ; tmp = plus_constant ( Pmode , stack_pointer_rtx , - 1 * offset ) ; tmp = gen_rtx_SET ( stack_pointer_rtx , tmp ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , j ++ ) = tmp ; offset -= UNITS_PER_WORD ; if ( irq_ctrl_saved . irq_save_lpcount ) { reg = gen_rtx_REG ( SImode , 60 ) ; tmp = plus_constant ( Pmode , stack_pointer_rtx , offset ) ; tmp = gen_frame_mem ( SImode , tmp ) ; tmp = gen_rtx_SET ( tmp , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , j ++ ) = tmp ; offset -= UNITS_PER_WORD ; } if ( irq_ctrl_saved . irq_save_blink ) { reg = gen_rtx_REG ( SImode , 31 ) ; tmp = plus_constant ( Pmode , stack_pointer_rtx , offset ) ; tmp = gen_frame_mem ( SImode , tmp ) ; tmp = gen_rtx_SET ( tmp , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , j ++ ) = tmp ; offset -= UNITS_PER_WORD ; } for ( i = irq_ctrl_saved . irq_save_last_reg ; i >= 0 ; i -- ) { reg = gen_rtx_REG ( SImode , i ) ; tmp = plus_constant ( Pmode , stack_pointer_rtx , offset ) ; tmp = gen_frame_mem ( SImode , tmp ) ; tmp = gen_rtx_SET ( tmp , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , j ++ ) = tmp ; offset -= UNITS_PER_WORD ; } insn = emit_insn ( gen_stack_irq_dwarf ( ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , par ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Build dwarf information when the context is saved via AUX_IRQ_CTRL mechanism .


<s> std :: pair < unsigned , const TargetRegisterClass * > ARMTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return std :: make_pair ( 0U , ARM :: tGPRRegisterClass ) ; else return std :: make_pair ( 0U , ARM :: GPRRegisterClass ) ; case 'r' : return std :: make_pair ( 0U , ARM :: GPRRegisterClass ) ; case 'w' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , ARM :: SPRRegisterClass ) ; if ( VT == MVT :: f64 ) return std :: make_pair ( 0U , ARM :: DPRRegisterClass ) ; break ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> unsigned char AArch64Subtarget :: ClassifyGlobalReference ( const GlobalValue * GV , const TargetMachine & TM ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) ) return AArch64II :: MO_GOT ; if ( ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return AArch64II :: MO_GOT ; if ( useSmallAddressing ( ) && GV -> hasExternalWeakLinkage ( ) ) return AArch64II :: MO_GOT ; return AArch64II :: MO_NO_FLAG ; } </s>

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be referenced for the current subtarget .


<s> static void riscv_emit_int_order_test ( enum rtx_code code , bool * invert_ptr , rtx target , rtx cmp0 , rtx cmp1 ) { machine_mode mode ; mode = GET_MODE ( cmp0 ) ; if ( riscv_canonicalize_int_order_test ( & code , & cmp1 , mode ) ) riscv_emit_binary ( code , target , cmp0 , cmp1 ) ; else { enum rtx_code inv_code = reverse_condition ( code ) ; if ( ! riscv_canonicalize_int_order_test ( & inv_code , & cmp1 , mode ) ) { cmp1 = force_reg ( mode , cmp1 ) ; riscv_emit_int_order_test ( code , invert_ptr , target , cmp0 , cmp1 ) ; } else if ( invert_ptr == 0 ) { rtx inv_target = riscv_force_binary ( GET_MODE ( target ) , inv_code , cmp0 , cmp1 ) ; riscv_emit_binary ( XOR , target , inv_target , const1_rtx ) ; } else { * invert_ptr = ! * invert_ptr ; riscv_emit_binary ( inv_code , target , cmp0 , cmp1 ) ; } } } </s>

Compare CMP0 and CMP1 using ordering test CODE and store the result in TARGET . CMP0 and TARGET are register_operands . If INVERT_PTR is nonnull , it 's OK to set TARGET to the inverse of the result and flip * INVERT_PTR instead .


<s>
bool
BPFAsmPrinter
::
doInitialization
(
Module
&
M
)
{
AsmPrinter
::
doInitialization
(
M
)
;
if
(
MAI
->
doesSupportDebugInformation
(
)
&&
!
empty
(
M
.
debug_compile_units
(
)
)
)
{
BTF
=
new
BTFDebug
(
this
)
;
Handlers
.
push_back
(
HandlerInfo
(
std
::
unique_ptr
<
BTFDebug
>
(
BTF
)
,
"emit"
,
"Debug Info Emission"
,
"BTF"
,
"BTF Emission"
)
)
;
}
return
false
;
}
</s>

Set up the AsmPrinter when we are working on a new module .

BPF
BPF
"emit"
"Debug Info Emission"
"BTF"
"BTF Emission"


<s>
bool
A15SDOptimizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
if
(
skipFunction
(
Fn
.
getFunction
(
)
)
)
return
false
;
const
ARMSubtarget
&
STI
=
Fn
.
getSubtarget
<
ARMSubtarget
>
(
)
;
if
(
!
(
STI
.
isCortexA15
(
)
&&
STI
.
hasNEON
(
)
)
)
return
false
;
TII
=
STI
.
getInstrInfo
(
)
;
TRI
=
STI
.
getRegisterInfo
(
)
;
MRI
=
&
Fn
.
getRegInfo
(
)
;
bool
Modified
=
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Running on function "
<<
Fn
.
getName
(
)
<<
"\n"
)
;
DeadInstr
.
clear
(
)
;
Replacements
.
clear
(
)
;
for
(
MachineBasicBlock
&
MBB
:
Fn
)
{
for
(
MachineInstr
&
MI
:
MBB
)
{
Modified
|=
runOnInstruction
(
&
MI
)
;
}
}
for
(
MachineInstr
*
MI
:
DeadInstr
)
{
MI
->
eraseFromParent
(
)
;
}
return
Modified
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < TargetPassConfig > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
void
gomp_print_output
(
struct
kernargs
*
kernargs
,
bool
final
)
{
unsigned
int
limit
=
(
sizeof
(
kernargs
->
output_data
.
queue
)
/
sizeof
(
kernargs
->
output_data
.
queue
[
0
]
)
)
;
unsigned
int
from
=
__atomic_load_n
(
&
kernargs
->
output_data
.
consumed
,
__ATOMIC_ACQUIRE
)
;
unsigned
int
to
=
kernargs
->
output_data
.
next_output
;
if
(
from
>
to
)
{
if
(
final
)
printf
(
"GCN print buffer overflowed.\n"
)
;
return
;
}
unsigned
int
i
;
for
(
i
=
from
;
i
<
to
;
i
++
)
{
struct
printf_data
*
data
=
&
kernargs
->
output_data
.
queue
[
i
%
limit
]
;
if
(
!
data
->
written
&&
!
final
)
break
;
switch
(
data
->
type
)
{
case
0
:
printf
(
"%.128s%ld\n"
,
data
->
msg
,
data
->
ivalue
)
;
break
;
case
1
:
printf
(
"%.128s%f\n"
,
data
->
msg
,
data
->
dvalue
)
;
break
;
case
2
:
printf
(
"%.128s%.128s\n"
,
data
->
msg
,
data
->
text
)
;
break
;
case
3
:
printf
(
"%.128s%.128s"
,
data
->
msg
,
data
->
text
)
;
break
;
default
:
printf
(
"GCN print buffer error!\n"
)
;
break
;
}
data
->
written
=
0
;
__atomic_store_n
(
&
kernargs
->
output_data
.
consumed
,
i
+
1
,
__ATOMIC_RELEASE
)
;
}
fflush
(
stdout
)
;
}
</s>

Print any console output from the kernel . We print all entries from `` consumed '' to the next entry without a `` written '' flag , or `` next_output '' is reached . The buffer is circular , but the indices are absolute . It is assumed the kernel will stop writing data if `` next_output '' wraps ( becomes smaller than `` consumed '' ) .


<s> unsigned SISubtarget :: getOccupancyWithNumVGPRs ( unsigned VGPRs ) const { if ( VGPRs <= 24 ) return 10 ; if ( VGPRs <= 28 ) return 9 ; if ( VGPRs <= 32 ) return 8 ; if ( VGPRs <= 36 ) return 7 ; if ( VGPRs <= 40 ) return 6 ; if ( VGPRs <= 48 ) return 5 ; if ( VGPRs <= 64 ) return 4 ; if ( VGPRs <= 84 ) return 3 ; if ( VGPRs <= 128 ) return 2 ; return 1 ; } </s>

Return the maximum number of waves per SIMD for kernels using VGPRs VGPRs .


<s> virtual bool runOnFunction ( Function & Fn ) { GlobalBaseReg = 0 ; SelectionDAGISel :: runOnFunction ( Fn ) ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool LanaiTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_Lanai32 ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> bool arc_ccfsm_branch_deleted_p ( void ) { return ARC_CCFSM_BRANCH_DELETED_P ( & arc_ccfsm_current ) ; } </s>

See if the current insn , which is a conditional branch , is to be deleted .


<s> static bool arm_scalar_mode_supported_p ( scalar_mode mode ) { if ( mode == HFmode ) return ( arm_fp16_format != ARM_FP16_FORMAT_NONE ) ; else if ( ALL_FIXED_POINT_MODE_P ( mode ) ) return true ; else return default_scalar_mode_supported_p ( mode ) ; } </s>

Implement TARGET_SCALAR_MODE_SUPPORTED_P . This simply adds HFmode as a supported mode ; even though we do n't implement arithmetic on this type directly , it 's supported by optabs conversions , much the way the double-word arithmetic is special-cased in the default hook .


Return true if the function body might clobber register REGNO . We know that REGNO is call-saved .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addPreserved < DominatorTreeWrapperPass > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> bool LC2200InstrInfo :: isAsCheapAsAMove ( const MachineInstr & MI ) const { const unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : break ; case LC2200 :: ADDI : return ( MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 1 ) . getReg ( ) == LC2200 :: zero ) ; } return MI . isAsCheapAsAMove ( ) ; } </s>

Return true if the instruction is as cheap as a move instruction .


"Object file emission is not supported with PTX"

Add passes to the specified pass manager to get the specified file emitted .


<s> const TargetRegisterClass * mprocRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & mproc :: GR8RegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s>
void
WebAssemblyInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
MCRegister
DestReg
,
MCRegister
SrcReg
,
bool
KillSrc
)
const
{
auto
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
const
TargetRegisterClass
*
RC
=
Register
::
isVirtualRegister
(
DestReg
)
MRI
.
getRegClass
(
DestReg
)
:
MRI
.
getTargetRegisterInfo
(
)
->
getMinimalPhysRegClass
(
DestReg
)
;
unsigned
CopyOpcode
;
if
(
RC
==
&
WebAssembly
::
I32RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_I32
;
else
if
(
RC
==
&
WebAssembly
::
I64RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_I64
;
else
if
(
RC
==
&
WebAssembly
::
F32RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_F32
;
else
if
(
RC
==
&
WebAssembly
::
F64RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_F64
;
else
if
(
RC
==
&
WebAssembly
::
V128RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_V128
;
else
if
(
RC
==
&
WebAssembly
::
FUNCREFRegClass
)
CopyOpcode
=
WebAssembly
::
COPY_FUNCREF
;
else
if
(
RC
==
&
WebAssembly
::
EXTERNREFRegClass
)
CopyOpcode
=
WebAssembly
::
COPY_EXTERNREF
;
else
llvm_unreachable
(
"Unexpected register class"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
CopyOpcode
)
,
DestReg
)
.
addReg
(
SrcReg
,
KillSrc
RegState
::
Kill
:
0
)
;
}
</s>


"@c Copyright (C) 2012-2017 Free Software Foundation, Inc.\n"

"@c For copying conditions, see the file "

"@c This file is generated automatically using\n"

Main program to convert flat files into built-in initialization code .


<s> static rtx rs6000_expand_zeroop_builtin ( enum insn_code icode , rtx target ) { rtx pat ; machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; if ( icode == CODE_FOR_nothing ) return 0 ; if ( target == 0 || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; pat = GEN_FCN ( icode ) ( target ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>

Expand an expression EXP that calls a builtin without arguments .


<s> bool ARMPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None && ! getARMSubtarget ( ) . isThumb1Only ( ) ) addPass ( createARMLoadStoreOptimizationPass ( true ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None && getARMSubtarget ( ) . isCortexA9 ( ) ) addPass ( createMLxExpansionPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Mips PseudoInstrs Expansion"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> MCS51TargetLowering :: ConstraintType MCS51TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'a' : case 'b' : case 'd' : case 'l' : case 'e' : case 'q' : case 'r' : case 'w' : return C_RegisterClass ; case 't' : case 'x' : case 'X' : case 'y' : case 'Y' : case 'z' : case 'Z' : return C_Register ; case 'Q' : return C_Memory ; case 'G' : case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'O' : case 'P' : case 'R' : return C_Immediate ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> void SystemZFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo * MFFrame = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; bool HasFP = hasFP ( MF ) ; SystemZMachineFunctionInfo * MFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; bool IsVarArg = MF . getFunction ( ) -> isVarArg ( ) ; if ( IsVarArg ) for ( unsigned I = MFI -> getVarArgsFirstGPR ( ) ; I < SystemZ :: NumArgGPRs ; ++ I ) SavedRegs . set ( SystemZ :: ArgGPRs [ I ] ) ; if ( ! MF . getMMI ( ) . getLandingPads ( ) . empty ( ) ) { SavedRegs . set ( SystemZ :: R6D ) ; SavedRegs . set ( SystemZ :: R7D ) ; } if ( HasFP ) SavedRegs . set ( SystemZ :: R11D ) ; if ( MFFrame -> hasCalls ( ) ) SavedRegs . set ( SystemZ :: R14D ) ; const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ; for ( unsigned I = 0 ; CSRegs [ I ] ; ++ I ) { unsigned Reg = CSRegs [ I ] ; if ( SystemZ :: GR64BitRegClass . contains ( Reg ) && SavedRegs . test ( Reg ) ) { SavedRegs . set ( SystemZ :: R15D ) ; break ; } } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> bool AArch64PassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnablePromoteConstant ) addPass ( createAArch64PromoteConstantPass ( ) ) ; if ( ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE ) { bool OnlyOptimizeForSize = ( TM -> getOptLevel ( ) < CodeGenOpt :: Aggressive ) && ( EnableGlobalMerge == cl :: BOU_UNSET ) ; bool MergeExternalByDefault = ! TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ; if ( ! OnlyOptimizeForSize ) MergeExternalByDefault = false ; addPass ( createGlobalMergePass ( TM , 4095 , OnlyOptimizeForSize , MergeExternalByDefault ) ) ; } return false ; } </s>


<s> unsigned OpenRISCRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? OpenRISC :: FP : OpenRISC :: SP ; } </s>

OpenRISC OpenRISC OpenRISC::FP OpenRISC::SP


<s> TargetPassConfig * MSP430TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new MSP430PassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> static rtx m68hc11_expand_compare ( enum rtx_code code , rtx op0 , rtx op1 ) { rtx ret = 0 ; gcc_assert ( GET_MODE_CLASS ( GET_MODE ( op0 ) ) != MODE_FLOAT ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cc0_rtx , gen_rtx_COMPARE ( VOIDmode , op0 , op1 ) ) ) ; ret = gen_rtx_fmt_ee ( code , VOIDmode , cc0_rtx , const0_rtx ) ; return ret ; } </s>


<s> static void rs6000_eliminate_indexed_memrefs ( rtx operands [ 2 ] ) { if ( GET_CODE ( operands [ 0 ] ) == MEM && GET_CODE ( XEXP ( operands [ 0 ] , 0 ) ) != REG && ! legitimate_constant_pool_address_p ( XEXP ( operands [ 0 ] , 0 ) ) && ! reload_in_progress ) operands [ 0 ] = replace_equiv_address ( operands [ 0 ] , copy_addr_to_reg ( XEXP ( operands [ 0 ] , 0 ) ) ) ; if ( GET_CODE ( operands [ 1 ] ) == MEM && GET_CODE ( XEXP ( operands [ 1 ] , 0 ) ) != REG && ! legitimate_constant_pool_address_p ( XEXP ( operands [ 1 ] , 0 ) ) && ! reload_in_progress ) operands [ 1 ] = replace_equiv_address ( operands [ 1 ] , copy_addr_to_reg ( XEXP ( operands [ 1 ] , 0 ) ) ) ; } </s>

Helper for the following . Get rid of [ r+r ] memory refs in cases where it wo n't work ( TImode , TFmode ) .


<s> bool ARMTargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( VT . getVectorNumElements ( ) == 4 && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ 4 ] ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { if ( M [ i ] < 0 ) PFIndexes [ i ] = 8 ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ 0 ] * 9 * 9 * 9 + PFIndexes [ 1 ] * 9 * 9 + PFIndexes [ 2 ] * 9 + PFIndexes [ 3 ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> 30 ) ; if ( Cost <= 4 ) return true ; } bool ReverseVEXT ; unsigned Imm , WhichResult ; return ( ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isVREVMask ( M , VT , 64 ) || isVREVMask ( M , VT , 32 ) || isVREVMask ( M , VT , 16 ) || isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTRNMask ( M , VT , WhichResult ) || isVUZPMask ( M , VT , WhichResult ) || isVZIPMask ( M , VT , WhichResult ) || isVTRN_v_undef_Mask ( M , VT , WhichResult ) || isVUZP_v_undef_Mask ( M , VT , WhichResult ) || isVZIP_v_undef_Mask ( M , VT , WhichResult ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .