<s> bool ix86_avoid_lea_for_addr ( rtx_insn * insn , rtx operands [ ] ) { unsigned int regno0 , regno1 , regno2 ; int split_cost ; struct ix86_address parts ; int ok ; if ( REG_P ( operands [ 1 ] ) || ( SImode_address_operand ( operands [ 1 ] , VOIDmode ) && REG_P ( XEXP ( operands [ 1 ] , 0 ) ) ) ) return false ; ok = ix86_decompose_address ( operands [ 1 ] , & parts ) ; gcc_assert ( ok ) ; if ( ( parts . base != NULL_RTX ) + ( parts . index != NULL_RTX ) + ( parts . disp != NULL_RTX ) + ( parts . scale > 1 ) < 2 ) return false ; if ( parts . disp && flag_pic && ! LEGITIMATE_PIC_OPERAND_P ( parts . disp ) ) return false ; regno0 = true_regnum ( operands [ 0 ] ) ; regno1 = INVALID_REGNUM ; regno2 = INVALID_REGNUM ; if ( parts . base ) regno1 = true_regnum ( parts . base ) ; if ( parts . index ) regno2 = true_regnum ( parts . index ) ; if ( ! TARGET_CPU_P ( BONNELL ) && parts . scale == 1 && ( ! parts . disp || parts . disp == const0_rtx ) && ( regno0 == regno1 || regno0 == regno2 ) ) return true ; if ( ! TARGET_AVOID_LEA_FOR_ADDR || optimize_function_for_size_p ( cfun ) ) return false ; split_cost = 0 ; if ( parts . base || parts . index ) { if ( regno1 != regno0 && regno2 != regno0 ) split_cost += 1 ; if ( parts . base && parts . index ) split_cost += 1 ; if ( parts . scale > 1 ) { if ( regno0 != regno1 ) split_cost += 1 ; else if ( regno2 == regno0 ) split_cost += 4 ; else split_cost += parts . scale ; } if ( parts . disp && parts . disp != const0_rtx ) split_cost += 1 ; split_cost -= 1 ; } return ! ix86_lea_outperforms ( insn , regno0 , regno1 , regno2 , split_cost , parts . scale > 1 ) ; } </s>

Return true if we need to split lea into a sequence of instructions to avoid AGU stalls during peephole2 .


<s>
SDValue
X86TargetLowering
::
BuildSDIVPow2
(
SDNode
*
N
,
const
APInt
&
Divisor
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDNode
*
>
&
Created
)
const
{
AttributeList
Attr
=
DAG
.
getMachineFunction
(
)
.
getFunction
(
)
.
getAttributes
(
)
;
if
(
isIntDivCheap
(
N
->
getValueType
(
0
)
,
Attr
)
)
return
SDValue
(
N
,
0
)
;
assert
(
(
Divisor
.
isPowerOf2
(
)
||
(
Divisor
)
.
isPowerOf2
(
)
)
&&
"Unexpected divisor!"
)
;
if
(
!
Subtarget
.
hasCMov
(
)
)
return
SDValue
(
)
;
EVT
VT
=
N
->
getValueType
(
0
)
;
if
(
VT
!=
MVT
::
i16
&&
VT
!=
MVT
::
i32
&&
!
(
Subtarget
.
is64Bit
(
)
&&
VT
==
MVT
::
i64
)
)
return
SDValue
(
)
;
unsigned
Lg2
=
Divisor
.
countTrailingZeros
(
)
;
if
(
Lg2
==
1
)
return
SDValue
(
)
;
SDLoc
DL
(
N
)
;
SDValue
N0
=
N
->
getOperand
(
0
)
;
SDValue
Zero
=
DAG
.
getConstant
(
0
,
DL
,
VT
)
;
APInt
Lg2Mask
=
APInt
::
getLowBitsSet
(
VT
.
getSizeInBits
(
)
,
Lg2
)
;
SDValue
Pow2MinusOne
=
DAG
.
getConstant
(
Lg2Mask
,
DL
,
VT
)
;
SDValue
Cmp
=
DAG
.
getSetCC
(
DL
,
MVT
::
i8
,
N0
,
Zero
,
ISD
::
SETLT
)
;
SDValue
Add
=
DAG
.
getNode
(
ISD
::
ADD
,
DL
,
VT
,
N0
,
Pow2MinusOne
)
;
SDValue
CMov
=
DAG
.
getNode
(
ISD
::
SELECT
,
DL
,
VT
,
Cmp
,
Add
,
N0
)
;
Created
.
push_back
(
Cmp
.
getNode
(
)
)
;
Created
.
push_back
(
Add
.
getNode
(
)
)
;
Created
.
push_back
(
CMov
.
getNode
(
)
)
;
SDValue
SRA
=
DAG
.
getNode
(
ISD
::
SRA
,
DL
,
VT
,
CMov
,
DAG
.
getConstant
(
Lg2
,
DL
,
MVT
::
i8
)
)
;
if
(
Divisor
.
isNonNegative
(
)
)
return
SRA
;
Created
.
push_back
(
SRA
.
getNode
(
)
)
;
return
DAG
.
getNode
(
ISD
::
SUB
,
DL
,
VT
,
Zero
,
SRA
)
;
}
</s>

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators .


<s> unsigned SystemZInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { return isSimpleMove ( MI , FrameIndex , SystemZII :: SimpleBDXStore ) ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> bool SIWholeQuadMode :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getFunction ( ) -> getCallingConv ( ) != CallingConv :: AMDGPU_PS ) return false ; Instructions . clear ( ) ; Blocks . clear ( ) ; ExecExports . clear ( ) ; LiveMaskQueries . clear ( ) ; const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; char GlobalFlags = analyzeFunction ( MF ) ; if ( ! ( GlobalFlags & StateWQM ) ) { lowerLiveMaskQueries ( AMDGPU :: EXEC ) ; return ! LiveMaskQueries . empty ( ) ; } unsigned LiveMaskReg = 0 ; { MachineBasicBlock & Entry = MF . front ( ) ; MachineBasicBlock :: iterator EntryMI = Entry . getFirstNonPHI ( ) ; if ( GlobalFlags & StateExact || ! LiveMaskQueries . empty ( ) ) { LiveMaskReg = MRI -> createVirtualRegister ( & AMDGPU :: SReg_64RegClass ) ; BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( AMDGPU :: COPY ) , LiveMaskReg ) . addReg ( AMDGPU :: EXEC ) ; } if ( GlobalFlags == StateWQM ) { BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( AMDGPU :: S_WQM_B64 ) , AMDGPU :: EXEC ) . addReg ( AMDGPU :: EXEC ) ; lowerLiveMaskQueries ( LiveMaskReg ) ; return true ; } } lowerLiveMaskQueries ( LiveMaskReg ) ; for ( auto BII : Blocks ) processBlock ( * BII . first , LiveMaskReg , BII . first == & * MF . begin ( ) ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .

AMDGPU SI AMDGPU SI SI AMDGPU::EXEC 0 AMDGPU::SReg_64RegClass AMDGPU::COPY AMDGPU::EXEC AMDGPU::S_WQM_B64 AMDGPU::EXEC AMDGPU::EXEC


"Frame indices can only appear as the first "

"operand of a DBG_VALUE machine instruction"


<s> static void mips_legitimize_const_move ( machine_mode mode , rtx dest , rtx src ) { rtx base , offset ; if ( splittable_const_int_operand ( src , mode ) ) { mips_move_integer ( dest , dest , INTVAL ( src ) ) ; return ; } if ( mips_split_symbol ( dest , src , MAX_MACHINE_MODE , & src ) ) { emit_insn ( gen_rtx_SET ( VOIDmode , dest , src ) ) ; return ; } if ( mips_tls_symbol_p ( src ) ) { mips_emit_move ( dest , mips_legitimize_tls_address ( src ) ) ; return ; } split_const ( src , & base , & offset ) ; if ( offset != const0_rtx && ( targetm . cannot_force_const_mem ( mode , src ) || ( ! TARGET_MIPS16 && can_create_pseudo_p ( ) ) ) ) { base = mips_force_temporary ( dest , base ) ; mips_emit_move ( dest , mips_add_offset ( NULL , base , INTVAL ( offset ) ) ) ; return ; } src = force_const_mem ( mode , src ) ; mips_split_symbol ( dest , XEXP ( src , 0 ) , mode , & XEXP ( src , 0 ) ) ; mips_emit_move ( dest , src ) ; } </s>

Subroutine of mips_legitimize_move . Move constant SRC into register DEST given that SRC satisfies immediate_operand but does n't satisfy move_operand .


<s> bool X86FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; if ( isFuncletReturnInstr ( * MI ) && STI . isOSWindows ( ) ) { if ( STI . is32Bit ( ) ) return true ; if ( MI -> getOpcode ( ) == X86 :: CATCHRET ) { const Function * Func = MBB . getParent ( ) -> getFunction ( ) ; bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( Func -> getPersonalityFn ( ) ) ) ; if ( IsSEH ) return true ; } } DebugLoc DL = MBB . findDebugLoc ( MI ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; -- MI ; MI -> setFlag ( MachineInstr :: FrameDestroy ) ; ++ MI ; } unsigned Opc = STI . is64Bit ( ) ? X86 :: POP64r : X86 :: POP32r ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool usesFunctionDescriptors ( ) const { return isAIXABI ( ) || ( is64BitELFABI ( ) && ! isELFv2ABI ( ) ) ; } </s>


<s>
SDValue
MSP430TargetLowering
::
LowerCall
(
TargetLowering
::
CallLoweringInfo
&
CLI
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SelectionDAG
&
DAG
=
CLI
.
DAG
;
SDLoc
&
dl
=
CLI
.
DL
;
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
=
CLI
.
Outs
;
SmallVectorImpl
<
SDValue
>
&
OutVals
=
CLI
.
OutVals
;
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
=
CLI
.
Ins
;
SDValue
Chain
=
CLI
.
Chain
;
SDValue
Callee
=
CLI
.
Callee
;
bool
&
isTailCall
=
CLI
.
IsTailCall
;
CallingConv
::
ID
CallConv
=
CLI
.
CallConv
;
bool
isVarArg
=
CLI
.
IsVarArg
;
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
MSP430_BUILTIN
:
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
OutVals
,
Ins
,
dl
,
DAG
,
InVals
)
;
case
CallingConv
::
MSP430_INTR
:
report_fatal_error
(
"ISRs cannot be called directly"
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .


<s> void MBlazeInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s>
void
ARMAsmBackend
::
relaxInstruction
(
const
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
,
MCInst
&
Res
)
const
{
unsigned
RelaxedOp
=
getRelaxedOpcode
(
Inst
.
getOpcode
(
)
)
;
if
(
RelaxedOp
==
Inst
.
getOpcode
(
)
)
{
SmallString
<
256
>
Tmp
;
raw_svector_ostream
OS
(
Tmp
)
;
Inst
.
dump_pretty
(
OS
)
;
OS
<<
"\n"
;
report_fatal_error
(
"unexpected instruction to relax: "
+
OS
.
str
(
)
)
;
}
if
(
(
Inst
.
getOpcode
(
)
==
ARM
::
tCBZ
||
Inst
.
getOpcode
(
)
==
ARM
::
tCBNZ
)
&&
RelaxedOp
==
ARM
::
tHINT
)
{
Res
.
setOpcode
(
RelaxedOp
)
;
Res
.
addOperand
(
MCOperand
::
createImm
(
0
)
)
;
Res
.
addOperand
(
MCOperand
::
createImm
(
14
)
)
;
Res
.
addOperand
(
MCOperand
::
createReg
(
0
)
)
;
return
;
}
Res
=
Inst
;
Res
.
setOpcode
(
RelaxedOp
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> SDValue SystemZTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ZERO_EXTEND : return combineZERO_EXTEND ( N , DCI ) ; case ISD :: SIGN_EXTEND : return combineSIGN_EXTEND ( N , DCI ) ; case ISD :: SIGN_EXTEND_INREG : return combineSIGN_EXTEND_INREG ( N , DCI ) ; case SystemZISD :: MERGE_HIGH : case SystemZISD :: MERGE_LOW : return combineMERGE ( N , DCI ) ; case ISD :: STORE : return combineSTORE ( N , DCI ) ; case ISD :: EXTRACT_VECTOR_ELT : return combineEXTRACT_VECTOR_ELT ( N , DCI ) ; case SystemZISD :: JOIN_DWORDS : return combineJOIN_DWORDS ( N , DCI ) ; case ISD :: FP_ROUND : return combineFP_ROUND ( N , DCI ) ; case ISD :: BSWAP : return combineBSWAP ( N , DCI ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : case ISD :: ROTL : return combineSHIFTROT ( N , DCI ) ; case SystemZISD :: BR_CCMASK : return combineBR_CCMASK ( N , DCI ) ; case SystemZISD :: SELECT_CCMASK : return combineSELECT_CCMASK ( N , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s>
static
int
rs6000_arg_partial_bytes
(
cumulative_args_t
cum_v
,
machine_mode
mode
,
tree
type
,
bool
named
)
{
CUMULATIVE_ARGS
*
cum
=
get_cumulative_args
(
cum_v
)
;
bool
passed_in_gprs
=
true
;
int
ret
=
0
;
int
align_words
;
machine_mode
elt_mode
;
int
n_elts
;
rs6000_discover_homogeneous_aggregate
(
mode
,
type
,
&
elt_mode
,
&
n_elts
)
;
if
(
DEFAULT_ABI
==
ABI_V4
)
return
0
;
if
(
USE_ALTIVEC_FOR_ARG_P
(
cum
,
elt_mode
,
named
)
)
{
if
(
TARGET_64BIT
&&
!
cum
->
prototype
)
return
0
;
passed_in_gprs
=
false
;
if
(
cum
->
vregno
+
n_elts
>
ALTIVEC_ARG_MAX_REG
+
1
)
ret
=
(
ALTIVEC_ARG_MAX_REG
+
1
cum
->
vregno
)
*
16
;
}
if
(
TARGET_MACHO
&&
rs6000_darwin64_struct_check_p
(
mode
,
type
)
)
return
0
;
align_words
=
rs6000_parm_start
(
mode
,
type
,
cum
->
words
)
;
if
(
USE_FP_FOR_ARG_P
(
cum
,
elt_mode
)
)
{
unsigned
long
n_fpreg
=
(
GET_MODE_SIZE
(
elt_mode
)
+
7
)
>>
3
;
if
(
type
&&
(
cum
->
nargs_prototype
<=
0
||
(
(
DEFAULT_ABI
==
ABI_AIX
||
DEFAULT_ABI
==
ABI_ELFv2
)
&&
TARGET_XL_COMPAT
&&
align_words
>=
GP_ARG_NUM_REG
)
)
)
return
0
;
passed_in_gprs
=
false
;
if
(
cum
->
fregno
+
n_elts
*
n_fpreg
>
FP_ARG_MAX_REG
+
1
)
{
int
fpr
=
(
(
FP_ARG_MAX_REG
+
1
cum
->
fregno
)
*
MIN
(
8
,
GET_MODE_SIZE
(
elt_mode
)
)
)
;
int
fpr_words
=
fpr
/
(
TARGET_32BIT
4
:
8
)
;
if
(
align_words
+
fpr_words
<
GP_ARG_NUM_REG
)
passed_in_gprs
=
true
;
else
ret
=
fpr
;
}
}
if
(
passed_in_gprs
&&
align_words
<
GP_ARG_NUM_REG
&&
GP_ARG_NUM_REG
<
align_words
+
rs6000_arg_size
(
mode
,
type
)
)
ret
=
(
GP_ARG_NUM_REG
align_words
)
*
(
TARGET_32BIT
4
:
8
)
;
if
(
ret
!=
0
&&
TARGET_DEBUG_ARG
)
fprintf
(
stderr
,
"rs6000_arg_partial_bytes: %d\n"
,
ret
)
;
return
ret
;
}
</s>

For an arg passed partly in registers and partly in memory , this is the number of bytes passed in registers . For args passed entirely in registers or entirely in memory , zero . When an arg is described by a PARALLEL , perhaps using more than one register type , this function returns the number of bytes used by the first element of the PARALLEL .


"********** Prepare For LiveIntervals **********\n"

"LiveIntervals shouldn't be active yet!"


<s> void MBlazeRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool ba_p ( rtx op , bool strict ) { return ( GET_CODE ( op ) == MEM && inside_ba_p ( XEXP ( op , 0 ) , strict ) ) || ( reload_in_progress && GET_CODE ( op ) == REG && REGNO ( op ) >= FIRST_PSEUDO_REGISTER ) || ( reload_in_progress && GET_CODE ( op ) == MEM && GET_CODE ( XEXP ( op , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( op , 0 ) , 0 ) ) == REG && REGNO ( op ) >= FIRST_PSEUDO_REGISTER && GET_CODE ( XEXP ( XEXP ( op , 0 ) , 1 ) ) == CONST_INT && ( INTVAL ( XEXP ( XEXP ( op , 0 ) , 1 ) ) & 0x1 ) == 0 ) ; } </s>

Also accept ( MEM ( PLUS ( pseudo ) CONST_INT ) ) , since the pseudo will always be allocated to a PTR reg .


<s> void NVPTXFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


<s>
static
bool
matchBitfieldExtractFromSExtInReg
(
MachineInstr
&
MI
,
MachineRegisterInfo
&
MRI
,
std
::
function
<
void
(
MachineIRBuilder
&
)
>
&
MatchInfo
)
{
assert
(
MI
.
getOpcode
(
)
==
TargetOpcode
::
G_SEXT_INREG
)
;
Register
Dst
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
Register
Src
=
MI
.
getOperand
(
1
)
.
getReg
(
)
;
int64_t
Width
=
MI
.
getOperand
(
2
)
.
getImm
(
)
;
LLT
Ty
=
MRI
.
getType
(
Src
)
;
assert
(
(
Ty
==
LLT
::
scalar
(
32
)
||
Ty
==
LLT
::
scalar
(
64
)
)
&&
"Unexpected type for G_SEXT_INREG?"
)
;
Register
ShiftSrc
;
int64_t
ShiftImm
;
if
(
!
mi_match
(
Src
,
MRI
,
m_OneNonDBGUse
(
m_any_of
(
m_GAShr
(
m_Reg
(
ShiftSrc
)
,
m_ICst
(
ShiftImm
)
)
,
m_GLShr
(
m_Reg
(
ShiftSrc
)
,
m_ICst
(
ShiftImm
)
)
)
)
)
)
return
false
;
if
(
ShiftImm
<
0
||
ShiftImm
+
Width
>
Ty
.
getSizeInBits
(
)
)
return
false
;
MatchInfo
=
[
=
]
(
MachineIRBuilder
&
B
)
{
auto
Cst1
=
B
.
buildConstant
(
Ty
,
ShiftImm
)
;
auto
Cst2
=
B
.
buildConstant
(
Ty
,
Width
)
;
B
.
buildInstr
(
TargetOpcode
::
G_SBFX
,
{
Dst
}
,
{
ShiftSrc
,
Cst1
,
Cst2
}
)
;
}
;
return
true
;
}
</s>

Form a G_SBFX from a G_SEXT_INREG fed by a right shift .


<s> static bool is_branch ( rtx insn ) { return ( CALL_P ( insn ) || JUMP_P ( insn ) ) ; } </s>

Return true if insn is a branch instruction .


<s>
void
AArch64AsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
Ctx
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
unsigned
FulleSizeInBytes
=
getFixupKindContainereSizeInBytes
(
Fixup
.
getKind
(
)
)
;
if
(
FulleSizeInBytes
==
0
)
{
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
else
{
assert
(
(
Offset
+
FulleSizeInBytes
)
<=
Data
.
size
(
)
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FulleSizeInBytes
&&
"Invalid fixup size!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
FulleSizeInBytes
1
i
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> rtx sparc_legitimize_reload_address ( rtx x , machine_mode mode , int opnum , int type , int ind_levels ATTRIBUTE_UNUSED , int * win ) { if ( CONSTANT_P ( x ) && ( mode != TFmode || TARGET_ARCH64 ) && GET_MODE ( x ) == SImode && GET_CODE ( x ) != LO_SUM && GET_CODE ( x ) != HIGH && sparc_code_model <= CM_MEDLOW && ! ( flag_pic && ( symbolic_operand ( x , Pmode ) || pic_address_needs_scratch ( x ) ) ) ) { x = gen_rtx_LO_SUM ( GET_MODE ( x ) , gen_rtx_HIGH ( GET_MODE ( x ) , x ) , x ) ; push_reload ( XEXP ( x , 0 ) , NULL_RTX , & XEXP ( x , 0 ) , NULL , BASE_REG_CLASS , GET_MODE ( x ) , VOIDmode , 0 , 0 , opnum , ( enum reload_type ) type ) ; * win = 1 ; return x ; } if ( GET_CODE ( x ) == LO_SUM && GET_CODE ( XEXP ( x , 0 ) ) == HIGH ) { push_reload ( XEXP ( x , 0 ) , NULL_RTX , & XEXP ( x , 0 ) , NULL , BASE_REG_CLASS , GET_MODE ( x ) , VOIDmode , 0 , 0 , opnum , ( enum reload_type ) type ) ; * win = 1 ; return x ; } * win = 0 ; return x ; } </s>

SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS . Returns a value to replace the input X , or the original X if no replacement is called for . The output parameter * WIN is 1 if the calling macro should goto WIN , 0 if it should not . For SPARC , we wish to handle addresses by splitting them into HIGH+LO_SUM pairs , retaining the LO_SUM in the memory reference . This cuts the number of extra insns by one . Do nothing when generating PIC code and the address is a symbolic operand or requires a scratch register .


<s> bool mep_vliw_jmp_match ( rtx tgt ) { bool src_vliw = mep_vliw_function_p ( cfun -> decl ) ; bool tgt_vliw = INTVAL ( tgt ) ; if ( mep_section_tag ( DECL_RTL ( cfun -> decl ) ) == 'f' ) return false ; return src_vliw == tgt_vliw ; } </s>

Like the above , but also test for near/far mismatches .


<s> bool TOYPassConfig :: addInstSelector ( ) { addPass ( createTOYISelDag ( getTOYTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool SparcAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'r' : break ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> SDValue NVPTXTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { CodeGenOpt :: Level OptLevel = getTargetMachine ( ) . getOptLevel ( ) ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : case ISD :: FADD : return PerformADDCombine ( N , DCI , STI , OptLevel ) ; case ISD :: MUL : return PerformMULCombine ( N , DCI , OptLevel ) ; case ISD :: SHL : return PerformSHLCombine ( N , DCI , OptLevel ) ; case ISD :: AND : return PerformANDCombine ( N , DCI ) ; case ISD :: SELECT : return PerformSELECTCombine ( N , DCI ) ; case ISD :: UREM : case ISD :: SREM : return PerformREMCombine ( N , DCI , OptLevel ) ; } return SDValue ( ) ; } </s>

NVPTX NVPTX ISD::ADD ISD::FADD ISD::MUL ISD::SHL ISD::AND ISD::SELECT ISD::UREM ISD::SREM


<s> void WebAssemblyFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { uint64_t StackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ; if ( ! StackSize ) return ; const auto * TII = MF . getSubtarget < WebAssemblySubtarget > ( ) . getInstrInfo ( ) ; auto & MRI = MF . getRegInfo ( ) ; unsigned OffsetReg = MRI . createVirtualRegister ( & WebAssembly :: I32RegClass ) ; auto InsertPt = MBB . getFirstTerminator ( ) ; DebugLoc DL ; if ( InsertPt != MBB . end ( ) ) { DL = InsertPt -> getDebugLoc ( ) ; } BuildMI ( MBB , InsertPt , DL , TII -> get ( WebAssembly :: CONST_I32 ) , OffsetReg ) . addImm ( StackSize ) ; auto * SPSymbol = MF . createExternalSymbolName ( "__stack_pointer" ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( WebAssembly :: ADD_I32 ) , WebAssembly :: SP32 ) . addReg ( WebAssembly :: SP32 ) . addReg ( OffsetReg ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( WebAssembly :: CONST_I32 ) , OffsetReg ) . addExternalSymbol ( SPSymbol ) ; auto * MMO = new MachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOStore , 4 , 4 ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( WebAssembly :: STORE_I32 ) , WebAssembly :: SP32 ) . addImm ( 0 ) . addReg ( OffsetReg ) . addImm ( 2 ) . addReg ( WebAssembly :: SP32 ) . addMemOperand ( MMO ) ; } </s>


<s> unsigned getRsaSize ( void ) const { return 176 ; } </s>

Get the size of RSA , return address , and frame pointer as described in VEFrameLowering.cpp .


<s> void function_builder :: append_name ( const char * name ) { obstack_grow ( & m_string_obstack , name , strlen ( name ) ) ; } </s>

Add NAME to the end of the function name being built .


"Some operands reg class are incompatible!"

optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare ; remove Compare if possible .


<s>
void
X86IntelInstPrinter
::
printPCRelImm
(
const
MCInst
*
MI
,
unsigned
OpNo
,
raw_ostream
&
O
)
{
const
MCOperand
&
Op
=
MI
->
getOperand
(
OpNo
)
;
if
(
Op
.
isImm
(
)
)
O
<<
formatImm
(
Op
.
getImm
(
)
)
;
else
{
assert
(
Op
.
isExpr
(
)
&&
"unknown pcrel immediate operand"
)
;
const
MCConstantExpr
*
BranchTarget
=
dyn_cast
<
MCConstantExpr
>
(
Op
.
getExpr
(
)
)
;
int64_t
Address
;
if
(
BranchTarget
&&
BranchTarget
->
EvaluateAsAbsolute
(
Address
)
)
{
O
<<
formatHex
(
(
uint64_t
)
Address
)
;
}
else
{
O
<<
*
Op
.
getExpr
(
)
;
}
}
}
</s>


<s> static struct machine_function * arc_init_machine_status ( void ) { struct machine_function * machine ; machine = ggc_cleared_alloc < machine_function > ( ) ; machine -> fn_type = ARC_FUNCTION_UNKNOWN ; return machine ; } </s>

The usual ; we set up our machine_function data .


<s> void SIInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; SIMachineFunctionInfo * MFI = MBB . getParent ( ) -> getInfo < SIMachineFunctionInfo > ( ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; unsigned KillFlag = isKill ? RegState :: Kill : 0 ; if ( TRI -> getCommonSubClass ( RC , & AMDGPU :: SGPR_32RegClass ) ) { unsigned Lane = MFI -> SpillTracker . getNextLane ( MRI ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: V_WRITELANE_B32 ) , MFI -> SpillTracker . LaneVGPR ) . addReg ( SrcReg , KillFlag ) . addImm ( Lane ) ; MFI -> SpillTracker . addSpilledReg ( FrameIndex , MFI -> SpillTracker . LaneVGPR , Lane ) ; } else { for ( unsigned i = 0 , e = RC -> getSize ( ) / 4 ; i != e ; ++ i ) { unsigned SubReg = MRI . createVirtualRegister ( & AMDGPU :: SReg_32RegClass ) ; BuildMI ( MBB , MI , MBB . findDebugLoc ( MI ) , get ( AMDGPU :: COPY ) , SubReg ) . addReg ( SrcReg , 0 , RI . getSubRegFromChannel ( i ) ) ; storeRegToStackSlot ( MBB , MI , SubReg , isKill , FrameIndex + i , & AMDGPU :: SReg_32RegClass , TRI ) ; } } } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> void PatmosAsmPrinter :: emitBasicBlockEnd ( const MachineBasicBlock & MBB ) { if ( & MBB . getParent ( ) -> back ( ) == & MBB ) return ; const MachineBasicBlock * Next = MBB . getNextNode ( ) ; bool followedByFStart = isFStart ( Next ) ; if ( followedByFStart ) { OutStreamer -> emitLabel ( CurrCodeEnd ) ; } } </s>

Targets can override this to emit stuff at the end of a basic block .


<s>
int
scalar_chain
::
convert
(
)
{
bitmap_iterator
bi
;
unsigned
id
;
int
converted_insns
=
0
;
if
(
!
dbg_cnt
(
stv_conversion
)
)
return
0
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Converting chain #%d...\n"
,
chain_id
)
;
convert_registers
(
)
;
EXECUTE_IF_SET_IN_BITMAP
(
insns
,
0
,
id
,
bi
)
{
rtx_insn
*
insn
=
DF_INSN_UID_GET
(
id
)
->
insn
;
convert_insn_common
(
insn
)
;
convert_insn
(
insn
)
;
converted_insns
++
;
}
return
converted_insns
;
}
</s>

Convert whole chain creating required register conversions and copies .


<s> bool SIInstrInfo :: isLegalFLATOffset ( int64_t Offset , unsigned AddrSpace , bool Signed ) const { if ( ! ST . hasFlatInstOffsets ( ) ) return false ; if ( ST . hasFlatSegmentOffsetBug ( ) && AddrSpace == AMDGPUAS :: FLAT_ADDRESS ) return false ; if ( ST . getGeneration ( ) >= AMDGPUSubtarget :: GFX10 ) return Signed ? isInt < 12 > ( Offset ) : isUInt < 11 > ( Offset ) ; return Signed ? isInt < 13 > ( Offset ) : isUInt < 12 > ( Offset ) ; } </s>

Returns if Offset is legal for the subtarget as the offset to a FLAT encoded instruction .


<s> bool PPCTargetLowering :: decomposeMulByConstant ( LLVMContext & Context , EVT VT , SDValue C ) const { if ( ! VT . isScalarInteger ( ) ) return false ; if ( auto * ConstNode = dyn_cast < ConstantSDNode > ( C . getNode ( ) ) ) { if ( ! ConstNode -> getAPIntValue ( ) . isSignedIntN ( 64 ) ) return false ; int64_t Imm = ConstNode -> getSExtValue ( ) ; unsigned Shift = countTrailingZeros < uint64_t > ( Imm ) ; Imm >>= Shift ; if ( isInt < 16 > ( Imm ) ) return false ; uint64_t UImm = static_cast < uint64_t > ( Imm ) ; if ( isPowerOf2_64 ( UImm + 1 ) || isPowerOf2_64 ( UImm - 1 ) || isPowerOf2_64 ( 1 - UImm ) || isPowerOf2_64 ( - 1 - UImm ) ) return true ; } return false ; } </s>

Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds .


"invalid number in -mrgf-banked-regs=%s "

Parse -mrgf-banked-regs=NUM option string . Valid values for NUM are 4 , 8 , 16 , or 32 .


<s> bool match ( MachineInstr * & Instr , unsigned int Opcode , ArgsT ... Args ) { Instr = match ( Opcode , Args ... ) ; return Instr != nullptr ; } </s>

matches - Match the regex against a given String .


<s> void emitThumbFunc ( MCSymbol * Func ) override { getAssembler ( ) . setIsThumbFunc ( Func ) ; emitSymbolAttribute ( Func , MCSA_ELF_TypeFunction ) ; } </s>

Note in the output that the specified Func is a Thumb mode function ( ARM target only ) .


<s>
CCAssignFn
*
AArch64TargetLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
const
{
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention."
)
;
case
CallingConv
::
WebKit_JS
:
return
CC_AArch64_WebKit_JS
;
case
CallingConv
::
GHC
:
return
CC_AArch64_GHC
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
case
CallingConv
::
PreserveMost
:
if
(
!
Subtarget
->
isTargetDarwin
(
)
)
return
CC_AArch64_AAPCS
;
return
IsVarArg
CC_AArch64_DarwinPCS_VarArg
:
CC_AArch64_DarwinPCS
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> void NVPTXRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> const char * output_fix_trunc ( rtx_insn * insn , rtx * operands , bool fisttp ) { bool stack_top_dies = find_regno_note ( insn , REG_DEAD , FIRST_STACK_REG ) ; bool dimode_p = GET_MODE ( operands [ 0 ] ) == DImode ; int round_mode = get_attr_i387_cw ( insn ) ; static char buf [ 40 ] ; const char * p ; if ( ( dimode_p || fisttp ) && ! stack_top_dies ) output_asm_insn ( "fld\t%y1" , operands ) ; gcc_assert ( STACK_TOP_P ( operands [ 1 ] ) ) ; gcc_assert ( MEM_P ( operands [ 0 ] ) ) ; gcc_assert ( GET_MODE ( operands [ 1 ] ) != TFmode ) ; if ( fisttp ) return "fisttp%Z0\t%0" ; strcpy ( buf , "fist" ) ; if ( round_mode != I387_CW_ANY ) output_asm_insn ( "fldcw\t%3" , operands ) ; p = "p%Z0\t%0" ; strcat ( buf , p + ! ( stack_top_dies || dimode_p ) ) ; output_asm_insn ( buf , operands ) ; if ( round_mode != I387_CW_ANY ) output_asm_insn ( "fldcw\t%2" , operands ) ; return "" ; } </s>

Output code for INSN to convert a float to a signed int . OPERANDS are the insn operands . The output may be [ HSD ] Imode and the input operand may be [ SDX ] Fmode .


<s> static void mips_move_integer ( rtx dest , unsigned HOST_WIDE_INT value ) { struct mips_integer_op codes [ MIPS_MAX_INTEGER_OPS ] ; enum machine_mode mode ; unsigned int i , cost ; rtx x ; mode = GET_MODE ( dest ) ; cost = mips_build_integer ( codes , value ) ; x = GEN_INT ( codes [ 0 ] . value ) ; for ( i = 1 ; i < cost ; i ++ ) { if ( no_new_pseudos ) emit_move_insn ( dest , x ) , x = dest ; else x = force_reg ( mode , x ) ; x = gen_rtx_fmt_ee ( codes [ i ] . code , mode , x , GEN_INT ( codes [ i ] . value ) ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , dest , x ) ) ; } </s>


<s> void SIWholeQuadMode :: processBlock ( MachineBasicBlock & MBB , unsigned LiveMaskReg , bool isEntry ) { auto BII = Blocks . find ( & MBB ) ; if ( BII == Blocks . end ( ) ) return ; const BlockInfo & BI = BII -> second ; if ( ! ( BI . InNeeds & StateWQM ) ) return ; if ( ! isEntry && ! ( BI . Needs & StateExact ) && BI . OutNeeds != StateExact ) return ; unsigned SavedWQMReg = 0 ; bool WQMFromExec = isEntry ; char State = isEntry ? StateExact : StateWQM ; auto II = MBB . getFirstNonPHI ( ) , IE = MBB . end ( ) ; while ( II != IE ) { MachineInstr & MI = * II ; ++ II ; if ( TII -> isScalarUnit ( MI ) && ! MI . isTerminator ( ) ) continue ; if ( TargetInstrInfo :: isGenericOpcode ( MI . getOpcode ( ) ) ) { if ( MI . getNumExplicitOperands ( ) >= 1 ) { const MachineOperand & Op = MI . getOperand ( 0 ) ; if ( Op . isReg ( ) ) { if ( TRI -> isSGPRReg ( * MRI , Op . getReg ( ) ) ) { continue ; } } } } char Needs = 0 ; char OutNeeds = 0 ; auto InstrInfoIt = Instructions . find ( & MI ) ; if ( InstrInfoIt != Instructions . end ( ) ) { Needs = InstrInfoIt -> second . Needs ; OutNeeds = InstrInfoIt -> second . OutNeeds ; if ( OutNeeds == StateExact && MI . isTerminator ( ) ) { assert ( Needs == 0 ) ; Needs = StateExact ; } } if ( Needs && State != Needs ) { if ( Needs == StateExact ) { assert ( ! SavedWQMReg ) ; if ( ! WQMFromExec && ( OutNeeds & StateWQM ) ) SavedWQMReg = MRI -> createVirtualRegister ( & AMDGPU :: SReg_64RegClass ) ; toExact ( MBB , & MI , SavedWQMReg , LiveMaskReg ) ; } else { assert ( WQMFromExec == ( SavedWQMReg == 0 ) ) ; toWQM ( MBB , & MI , SavedWQMReg ) ; SavedWQMReg = 0 ; } State = Needs ; } if ( MI . getOpcode ( ) == AMDGPU :: SI_ELSE && State == StateExact ) MI . getOperand ( 3 ) . setImm ( 1 ) ; } if ( ( BI . OutNeeds & StateWQM ) && State != StateWQM ) { assert ( WQMFromExec == ( SavedWQMReg == 0 ) ) ; toWQM ( MBB , MBB . end ( ) , SavedWQMReg ) ; } else if ( BI . OutNeeds == StateExact && State != StateExact ) { toExact ( MBB , MBB . end ( ) , 0 , LiveMaskReg ) ; } } </s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s> bool HexagonCopyToCombine :: runOnMachineFunction ( MachineFunction & MF ) { if ( IsCombinesDisabled ) return false ; bool HasChanged = false ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; TII = MF . getSubtarget < HexagonSubtarget > ( ) . getInstrInfo ( ) ; const Function * F = MF . getFunction ( ) ; bool OptForSize = F -> hasFnAttribute ( Attribute :: OptimizeForSize ) ; ShouldCombineAggressively = MF . getTarget ( ) . getOptLevel ( ) <= CodeGenOpt :: Default ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( * BI ) ; for ( MachineBasicBlock :: iterator MI = BI -> begin ( ) , End = BI -> end ( ) ; MI != End ; ) { MachineInstr & I1 = * MI ++ ; if ( I1 . isDebugValue ( ) ) continue ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( & I1 ) ) continue ; if ( ! isCombinableInstType ( I1 , TII , ShouldCombineAggressively ) ) continue ; bool DoInsertAtI1 = false ; DbgMItoMove . clear ( ) ; MachineInstr * I2 = findPairable ( I1 , DoInsertAtI1 , OptForSize ) ; if ( I2 ) { HasChanged = true ; combine ( I1 , * I2 , MI , DoInsertAtI1 , OptForSize ) ; } } } return HasChanged ; } </s>

runOnMachineFunction - Emit the function body .


"You cannot use the same Regs with MOVSX_RR"

"You cannot use the same Reg Classes with MOVSX_RR"


<s> static enum loongarch_symbol_type loongarch_classify_symbol ( const_rtx x ) { if ( LABEL_REF_P ( x ) ) return SYMBOL_GOT_DISP ; gcc_assert ( SYMBOL_REF_P ( x ) ) ; if ( SYMBOL_REF_TLS_MODEL ( x ) ) return SYMBOL_TLS ; if ( SYMBOL_REF_P ( x ) ) return SYMBOL_GOT_DISP ; return SYMBOL_GOT_DISP ; } </s>

Return the method that should be used to access SYMBOL_REF or LABEL_REF X .


<s> bool isSubregFoldable ( ) const override { return true ; } </s>

Check whether the target can fold a load that feeds a subreg operand ( or a subreg operand that feeds a store ) .


<s> bool aarch64_sve_dup_immediate_p ( rtx x ) { rtx elt ; if ( ! const_vec_duplicate_p ( x , & elt ) || ! CONST_INT_P ( elt ) ) return false ; HOST_WIDE_INT val = INTVAL ( elt ) ; if ( val & 0xff ) return IN_RANGE ( val , - 0x80 , 0x7f ) ; return IN_RANGE ( val , - 0x8000 , 0x7f00 ) ; } </s>

Return true if X is a valid immediate for the SVE DUP and CPY instructions .


<s> static rtx gen_load_pcrel_sym ( rtx op0 , rtx op1 , rtx op2 ) { int orig_flag_pic = flag_pic ; rtx insn ; flag_pic = 0 ; if ( TARGET_ARCH64 ) insn = gen_load_pcrel_symdi ( op0 , op1 , op2 , GEN_INT ( REGNO ( op0 ) ) ) ; else insn = gen_load_pcrel_symsi ( op0 , op1 , op2 , GEN_INT ( REGNO ( op0 ) ) ) ; flag_pic = orig_flag_pic ; return insn ; } </s>

Wrapper around the load_pcrel_sym { si , di } patterns .


<s> void SystemZAsmPrinter :: emitEndOfAsmFile ( Module & M ) { emitStackMaps ( SM ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> const SPIRVSubtarget * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
const
char
*
rvexAsmPrinter
::
getCurrentABIString
(
)
const
{
switch
(
Subtarget
->
getTargetABI
(
)
)
{
case
rvexSubtarget
::
O32
:
return
"abi32"
;
default
:
llvm_unreachable
(
"Unknown rvex ABI"
)
;
;
}
}
</s>

rvex
rvex
rvex
"abi32"
"Unknown rvex ABI"


<s> static void output_short_suffix ( FILE * file ) { rtx_insn * insn = current_output_insn ; if ( ! insn ) return ; if ( arc_verify_short ( insn , cfun -> machine -> unalign , 1 ) ) { fprintf ( file , "_s" ) ; cfun -> machine -> unalign ^= 2 ; } extract_insn_cached ( insn ) ; } </s>

When outputting an instruction ( alternative ) that can potentially be short , output the short suffix if the insn is in fact short , and update cfun- > machine- > unalign accordingly .


<s> unsigned HexagonInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case Hexagon :: L2_loadri_io : case Hexagon :: L2_loadrd_io : case Hexagon :: V6_vL32b_ai : case Hexagon :: V6_vL32b_nt_ai : case Hexagon :: V6_vL32b_ai_128B : case Hexagon :: V6_vL32b_nt_ai_128B : case Hexagon :: V6_vL32Ub_ai : case Hexagon :: V6_vL32Ub_ai_128B : case Hexagon :: LDriw_pred : case Hexagon :: LDriw_mod : case Hexagon :: PS_vloadrq_ai : case Hexagon :: PS_vloadrw_ai : case Hexagon :: PS_vloadrw_nt_ai : case Hexagon :: PS_vloadrq_ai_128B : case Hexagon :: PS_vloadrw_ai_128B : case Hexagon :: PS_vloadrw_nt_ai_128B : { const MachineOperand OpFI = MI . getOperand ( 1 ) ; if ( ! OpFI . isFI ( ) ) return 0 ; const MachineOperand OpOff = MI . getOperand ( 2 ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != 0 ) return 0 ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } case Hexagon :: L2_ploadrit_io : case Hexagon :: L2_ploadrif_io : case Hexagon :: L2_ploadrdt_io : case Hexagon :: L2_ploadrdf_io : { const MachineOperand OpFI = MI . getOperand ( 2 ) ; if ( ! OpFI . isFI ( ) ) return 0 ; const MachineOperand OpOff = MI . getOperand ( 3 ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != 0 ) return 0 ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> bool arc_legitimate_pic_operand_p ( rtx x ) { return ! arc_raw_symbolic_reference_mentioned_p ( x , true ) ; } </s>

Nonzero if the constant value X is a legitimate general operand when generating PIC code . It is given that flag_pic is on and that X satisfies CONSTANT_P or is a CONST_DOUBLE .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { bool is64 = getPointerSize ( ) == 8 ; return createMachObjectWriter ( OS , is64 , ( is64 ? object :: mach :: CTM_PowerPC64 : object :: mach :: CTM_PowerPC ) , object :: mach :: CSPPC_ALL , false ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> rtx nds32_expand_load_multiple ( int base_regno , int count , rtx base_addr , rtx basemem ) { int par_index ; int offset ; rtx result ; rtx new_addr , mem , reg ; result = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; for ( par_index = 0 ; par_index < count ; par_index ++ ) { offset = par_index * 4 ; new_addr = plus_constant ( Pmode , base_addr , offset ) ; mem = adjust_automodify_address_nv ( basemem , SImode , new_addr , offset ) ; reg = gen_rtx_REG ( SImode , base_regno + par_index ) ; XVECEXP ( result , 0 , par_index ) = gen_rtx_SET ( reg , mem ) ; } return result ; } </s>

Functions to expand load_multiple and store_multiple . They are auxiliary extern functions to help create rtx template . Check nds32-multiple.md file for the patterns .


<s> bool RISCVFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return true ; MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) DL = MI -> getDebugLoc ( ) ; const char * SpillLibCall = getSpillLibCallName ( * MF , CSI ) ; if ( SpillLibCall ) { BuildMI ( MBB , MI , DL , TII . get ( RISCV :: PseudoCALLReg ) , RISCV :: X5 ) . addExternalSymbol ( SpillLibCall , RISCVII :: MO_CALL ) . setMIFlag ( MachineInstr :: FrameSetup ) ; for ( auto & CS : CSI ) MBB . addLiveIn ( CS . getReg ( ) ) ; } const auto & NonLibcallCSI = getNonLibcallCSI ( CSI ) ; for ( auto & CS : NonLibcallCSI ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


"%<-mno-mpy%> supported only for ARC700 or ARCv2"

"%<-mno-dpfp-lrsr%> supported only with %<-mdpfp%>"

"FPX fast and compact options cannot be specified together"

"%<-mspfp_fast%> not available on ARC600 or ARC601"

Called by OVERRIDE_OPTIONS to initialize various things .


<s> bool Tile64InstrInfo :: isSchedulingBoundary ( const MachineInstr * MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( MI -> isDebugValue ( ) ) return false ; if ( MI -> getDesc ( ) . isTerminator ( ) || MI -> isLabel ( ) || MI -> isInlineAsm ( ) ) { return true ; } return false ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> bool SITargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & CI , MachineFunction & MF , unsigned IntrID ) const { if ( const AMDGPU :: RsrcIntrinsic * RsrcIntr = AMDGPU :: lookupRsrcIntrinsic ( IntrID ) ) { AttributeList Attr = Intrinsic :: getAttributes ( CI . getContext ( ) , ( Intrinsic :: ID ) IntrID ) ; if ( Attr . hasFnAttribute ( Attribute :: ReadNone ) ) return false ; SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; if ( RsrcIntr -> IsImage ) { Info . ptrVal = MFI -> getImagePSV ( * MF . getSubtarget < SISubtarget > ( ) . getInstrInfo ( ) , CI . getArgOperand ( RsrcIntr -> RsrcArg ) ) ; Info . align = 0 ; } else { Info . ptrVal = MFI -> getBufferPSV ( * MF . getSubtarget < SISubtarget > ( ) . getInstrInfo ( ) , CI . getArgOperand ( RsrcIntr -> RsrcArg ) ) ; } Info . flags = MachineMemOperand :: MODereferenceable ; if ( Attr . hasFnAttribute ( Attribute :: ReadOnly ) ) { Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: getVT ( CI . getType ( ) ) ; Info . flags |= MachineMemOperand :: MOLoad ; } else if ( Attr . hasFnAttribute ( Attribute :: WriteOnly ) ) { Info . opc = ISD :: INTRINSIC_VOID ; Info . memVT = MVT :: getVT ( CI . getArgOperand ( 0 ) -> getType ( ) ) ; Info . flags |= MachineMemOperand :: MOStore ; } else { Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: getVT ( CI . getType ( ) ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MODereferenceable ; Info . flags |= MachineMemOperand :: MOVolatile ; } return true ; } switch ( IntrID ) { case Intrinsic :: amdgcn_atomic_inc : case Intrinsic :: amdgcn_atomic_dec : case Intrinsic :: amdgcn_ds_fadd : case Intrinsic :: amdgcn_ds_fmin : case Intrinsic :: amdgcn_ds_fmax : { Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: getVT ( CI . getType ( ) ) ; Info . ptrVal = CI . getOperand ( 0 ) ; Info . align = 0 ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore ; const ConstantInt * Vol = dyn_cast < ConstantInt > ( CI . getOperand ( 4 ) ) ; if ( ! Vol || ! Vol -> isZero ( ) ) Info . flags |= MachineMemOperand :: MOVolatile ; return true ; } default : return false ; } } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> std :: unique_ptr < SICacheControl > SICacheControl :: create ( const GCNSubtarget & ST ) { GCNSubtarget :: Generation Generation = ST . getGeneration ( ) ; if ( Generation <= AMDGPUSubtarget :: SOUTHERN_ISLANDS ) return make_unique < SIGfx6CacheControl > ( ST ) ; return make_unique < SIGfx7CacheControl > ( ST ) ; } </s>


Allocate SIZE bytes of stack space , using TEMP_REG as a temporary if necessary . LAST_PROBE_OFFSET contains the offset of the closest probe relative to the stack pointer . Note that SIZE is negative . The return value is true if TEMP_REG has been clobbered .


<s>
SDValue
BlackfinTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
SmallVector
<
CCValAssign
,
16
>
ArgLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
ArgLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AllocateStack
(
12
,
4
)
;
CCInfo
.
AnalyzeFormalArguments
(
Ins
,
CC_Blackfin
)
;
for
(
unsigned
i
=
0
,
e
=
ArgLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
ArgLocs
[
i
]
;
if
(
VA
.
isRegLoc
(
)
)
{
EVT
RegVT
=
VA
.
getLocVT
(
)
;
TargetRegisterClass
*
RC
=
VA
.
getLocReg
(
)
==
BF
::
P0
BF
::
PRegisterClass
:
BF
::
DRegisterClass
;
assert
(
RC
->
contains
(
VA
.
getLocReg
(
)
)
&&
"Unexpected regclass in CCState"
)
;
assert
(
RC
->
hasType
(
RegVT
)
&&
"Unexpected regclass in CCState"
)
;
unsigned
Reg
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
RC
)
;
MF
.
getRegInfo
(
)
.
addLiveIn
(
VA
.
getLocReg
(
)
,
Reg
)
;
SDValue
ArgValue
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
Reg
,
RegVT
)
;
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
SExt
)
ArgValue
=
DAG
.
getNode
(
ISD
::
AssertSext
,
dl
,
RegVT
,
ArgValue
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
else
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExt
)
ArgValue
=
DAG
.
getNode
(
ISD
::
AssertZext
,
dl
,
RegVT
,
ArgValue
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
if
(
VA
.
getLocInfo
(
)
!=
CCValAssign
::
Full
)
ArgValue
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
ArgValue
)
;
InVals
.
push_back
(
ArgValue
)
;
}
else
{
assert
(
VA
.
isMemLoc
(
)
&&
"CCValAssign must be RegLoc or MemLoc"
)
;
unsigned
ObjSize
=
VA
.
getLocVT
(
)
.
getStoreSize
(
)
;
int
FI
=
MFI
->
CreateFixedObject
(
ObjSize
,
VA
.
getLocMemOffset
(
)
,
true
,
false
)
;
SDValue
FIN
=
DAG
.
getFrameIndex
(
FI
,
MVT
::
i32
)
;
InVals
.
push_back
(
DAG
.
getLoad
(
VA
.
getValVT
(
)
,
dl
,
Chain
,
FIN
,
,
0
,
false
,
false
,
0
)
)
;
}
}
return
Chain
;
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> rtx spu_legitimize_reload_address ( rtx ad , machine_mode mode ATTRIBUTE_UNUSED , int opnum , int type ) { bool removed_and = false ; if ( GET_CODE ( ad ) == AND && CONST_INT_P ( XEXP ( ad , 1 ) ) && INTVAL ( XEXP ( ad , 1 ) ) == ( HOST_WIDE_INT ) - 16 ) { ad = XEXP ( ad , 0 ) ; removed_and = true ; } if ( GET_CODE ( ad ) == PLUS && REG_P ( XEXP ( ad , 0 ) ) && CONST_INT_P ( XEXP ( ad , 1 ) ) && ! ( INTVAL ( XEXP ( ad , 1 ) ) >= - 0x2000 && INTVAL ( XEXP ( ad , 1 ) ) <= 0x1fff ) ) { ad = copy_rtx ( ad ) ; push_reload ( XEXP ( ad , 1 ) , NULL_RTX , & XEXP ( ad , 1 ) , NULL , BASE_REG_CLASS , GET_MODE ( ad ) , VOIDmode , 0 , 0 , opnum , ( enum reload_type ) type ) ; if ( removed_and ) ad = gen_rtx_AND ( GET_MODE ( ad ) , ad , GEN_INT ( - 16 ) ) ; return ad ; } return NULL_RTX ; } </s>

Reload reg + const_int for out-of-range displacements .


<s> std :: pair < unsigned , const TargetRegisterClass * > PPCTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'b' : case 'r' : if ( VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RCRegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRCRegClass ) ; case 'f' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , & PPC :: F4RCRegClass ) ; if ( VT == MVT :: f64 ) return std :: make_pair ( 0U , & PPC :: F8RCRegClass ) ; break ; case 'v' : return std :: make_pair ( 0U , & PPC :: VRRCRegClass ) ; case 'y' : return std :: make_pair ( 0U , & PPC :: CRRCRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


"switch -mcpu=%s conflicts with -march=%s switch"

"Assembler does not support -mabi=ilp32"

"Return address signing is only supported for -mabi=lp64"


<s> bool GCNPassConfig :: addRegAssignAndRewriteFast ( ) { if ( ! usingDefaultRegAlloc ( ) ) report_fatal_error ( RegAllocOptNotSupportedMessage ) ; addPass ( createSGPRAllocPass ( false ) ) ; addPass ( & SILowerSGPRSpillsID ) ; addPass ( createVGPRAllocPass ( false ) ) ; return true ; } </s>

Add core register allocator passes which do the actual register assignment and rewriting .


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { if ( ! Subtarget -> isAAPCS_ABI ( ) || Subtarget -> isTargetMachO ( ) || Subtarget -> isTargetWindows ( ) ) return SDValue ( ) ; const ARMTargetLowering & TLI = * static_cast < const ARMTargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Type * IntPtrTy = TLI . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( MVT :: i32 ) ) Src = DAG . getNode ( ISD :: TRUNCATE , dl , MVT :: i32 , Src ) ; else Src = DAG . getNode ( ISD :: ZERO_EXTEND , dl , MVT :: i32 , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , 0 , TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , false , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } </s>

Emit target-specific code that performs a memset .


<s> bool LC2200AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { if ( Count == 0 ) { return true ; } return false ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> bool TL45PassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( ) ) ; return false ; } </s>

This method should install a ( global ) instruction selector pass , which converts possibly generic instructions to fully target-specific instructions , thereby constraining all generic virtual registers to register classes .


<s> void ia64_emit_cond_move ( rtx op0 , rtx op1 , rtx cond ) { rtx_insn * insn , * first = get_last_insn ( ) ; emit_move_insn ( op0 , op1 ) ; for ( insn = get_last_insn ( ) ; insn != first ; insn = PREV_INSN ( insn ) ) if ( INSN_P ( insn ) ) PATTERN ( insn ) = gen_rtx_COND_EXEC ( VOIDmode , copy_rtx ( cond ) , PATTERN ( insn ) ) ; } </s>

Split a move from OP1 to OP0 conditional on COND .


<s> static bool rs6000_save_toc_in_prologue_p ( void ) { return ( cfun && cfun -> machine && cfun -> machine -> save_toc_in_prologue ) ; } </s>

Return whether we need to always update the saved TOC pointer when we update the stack pointer .


<s> void AMDGPUPassConfig :: addCodeGenPrepare ( ) { if ( TM -> getTargetTriple ( ) . getArch ( ) == Triple :: amdgcn ) { addPass ( createAMDGPUAttributorPass ( ) ) ; addPass ( createAMDGPUAnnotateKernelFeaturesPass ( ) ) ; } if ( TM -> getTargetTriple ( ) . getArch ( ) == Triple :: amdgcn && EnableLowerKernelArguments ) addPass ( createAMDGPULowerKernelArgumentsPass ( ) ) ; TargetPassConfig :: addCodeGenPrepare ( ) ; if ( isPassEnabled ( EnableLoadStoreVectorizer ) ) addPass ( createLoadStoreVectorizerPass ( ) ) ; addPass ( createLowerSwitchPass ( ) ) ; } </s>

Add pass to prepare the LLVM IR for code generation .


"Should be saving %r15 and something else"


<s> bool HexagonEvaluator :: evaluate ( const MachineInstr * BI , const CellMapType & Inputs , BranchTargetList & Targets , bool & FallsThru ) const { unsigned Opc = BI -> getOpcode ( ) ; bool SimpleBranch = false ; bool Negated = false ; switch ( Opc ) { case Hexagon :: J2_jumpf : case Hexagon :: J2_jumpfnew : case Hexagon :: J2_jumpfnewpt : Negated = true ; case Hexagon :: J2_jumpt : case Hexagon :: J2_jumptnew : case Hexagon :: J2_jumptnewpt : SimpleBranch = true ; break ; case Hexagon :: J2_jump : Targets . insert ( BI -> getOperand ( 0 ) . getMBB ( ) ) ; FallsThru = false ; return true ; default : return false ; } if ( ! SimpleBranch ) return false ; RegisterRef PR = BI -> getOperand ( 0 ) ; RegisterCell PC = getCell ( PR , Inputs ) ; const BT :: BitValue & Test = PC [ 0 ] ; if ( ! Test . is ( 0 ) && ! Test . is ( 1 ) ) return false ; if ( ! Test . is ( ! Negated ) ) { FallsThru = true ; return true ; } Targets . insert ( BI -> getOperand ( 1 ) . getMBB ( ) ) ; FallsThru = false ; return true ; } </s>

evaluate - Evaluate Expr and append the resulting set to Elts .


<s> bool SPUAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; printMemRegReg ( MI , OpNo , O ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s>
SUnit
*
R600SchedStrategy
::
pickNode
(
bool
&
IsTopNode
)
{
SUnit
*
SU
=
nullptr
;
NextInstKind
=
IDOther
;
IsTopNode
=
false
;
bool
AllowSwitchToAlu
=
(
CurEmitted
>=
InstKindLimit
[
CurInstKind
]
)
||
(
Available
[
CurInstKind
]
.
empty
(
)
)
;
bool
AllowSwitchFromAlu
=
(
CurEmitted
>=
InstKindLimit
[
CurInstKind
]
)
&&
(
!
Available
[
IDFetch
]
.
empty
(
)
||
!
Available
[
IDOther
]
.
empty
(
)
)
;
if
(
CurInstKind
==
IDAlu
&&
!
Available
[
IDFetch
]
.
empty
(
)
)
{
float
ALUFetchRationEstimate
=
(
AluInstCount
+
AvailablesAluCount
(
)
+
Pending
[
IDAlu
]
.
size
(
)
)
/
(
FetchInstCount
+
Available
[
IDFetch
]
.
size
(
)
)
;
if
(
ALUFetchRationEstimate
==
0
)
{
AllowSwitchFromAlu
=
true
;
}
else
{
unsigned
NeededWF
=
62.5f
/
ALUFetchRationEstimate
;
DEBUG
(
dbgs
(
)
<<
NeededWF
<<
" approx. Wavefronts Required\n"
)
;
unsigned
NearRegisterRequirement
=
2
*
Available
[
IDFetch
]
.
size
(
)
;
if
(
NeededWF
>
getWFCountLimitedByGPR
(
NearRegisterRequirement
)
)
AllowSwitchFromAlu
=
true
;
}
}
if
(
!
SU
&&
(
(
AllowSwitchToAlu
&&
CurInstKind
!=
IDAlu
)
||
(
!
AllowSwitchFromAlu
&&
CurInstKind
==
IDAlu
)
)
)
{
SU
=
pickAlu
(
)
;
if
(
!
SU
&&
!
PhysicalRegCopy
.
empty
(
)
)
{
SU
=
PhysicalRegCopy
.
front
(
)
;
PhysicalRegCopy
.
erase
(
PhysicalRegCopy
.
begin
(
)
)
;
}
if
(
SU
)
{
if
(
CurEmitted
>=
InstKindLimit
[
IDAlu
]
)
CurEmitted
=
0
;
NextInstKind
=
IDAlu
;
}
}
if
(
!
SU
)
{
SU
=
pickOther
(
IDFetch
)
;
if
(
SU
)
NextInstKind
=
IDFetch
;
}
if
(
!
SU
)
{
SU
=
pickOther
(
IDOther
)
;
if
(
SU
)
NextInstKind
=
IDOther
;
}
DEBUG
(
if
(
SU
)
{
dbgs
(
)
<<
" ** Pick node **\n"
;
SU
->
dump
(
DAG
)
;
}
else
{
dbgs
(
)
<<
"NO NODE \n"
;
for
(
unsigned
i
=
0
;
i
<
DAG
->
SUnits
.
size
(
)
;
i
++
)
{
const
SUnit
&
S
=
DAG
->
SUnits
[
i
]
;
if
(
!
S
.
isScheduled
)
S
.
dump
(
DAG
)
;
}
}
</s>

Pick the next node to schedule , or return NULL .


<s>
char
*
xstormy16_output_cbranch_si
(
rtx
op
,
const
char
*
label
,
int
reversed
,
rtx_insn
*
insn
)
{
static
char
string
[
64
]
;
int
need_longbranch
=
get_attr_length
(
insn
)
>=
8
;
int
really_reversed
=
reversed
^
need_longbranch
;
const
char
*
ccode
;
const
char
*
templ
;
char
prevop
[
16
]
;
enum
rtx_code
code
;
code
=
GET_CODE
(
op
)
;
if
(
really_reversed
)
code
=
reverse_condition
(
code
)
;
switch
(
code
)
{
case
EQ
:
ccode
=
"z"
;
break
;
case
NE
:
ccode
=
"nz"
;
break
;
case
GE
:
ccode
=
"ge"
;
break
;
case
LT
:
ccode
=
"lt"
;
break
;
case
GEU
:
ccode
=
"nc"
;
break
;
case
LTU
:
ccode
=
"c"
;
break
;
default
:
gcc_unreachable
(
)
;
}
switch
(
code
)
{
case
EQ
:
case
NE
:
{
int
regnum
;
gcc_assert
(
REG_P
(
XEXP
(
op
,
0
)
)
)
;
regnum
=
REGNO
(
XEXP
(
op
,
0
)
)
;
sprintf
(
prevop
,
"or %s,%s"
,
reg_names
[
regnum
]
,
reg_names
[
regnum
+
1
]
)
;
}
break
;
case
GE
:
case
LT
:
case
GEU
:
case
LTU
:
strcpy
(
prevop
,
"sbc %2,%3"
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
if
(
need_longbranch
)
templ
=
"%s | b%s .+6 | jmpf %s"
;
else
templ
=
"%s | b%s %s"
;
sprintf
(
string
,
templ
,
prevop
,
ccode
,
label
)
;
return
string
;
}
</s>

Return the string to output a conditional branch to LABEL , which is the operand number of the label , but suitable for the tail of a SImode branch . OP is the conditional expression ( OP is never NULL_RTX ) . REVERSED is non-zero if we should reverse the sense of the comparison . INSN is the insn .


"use_as_extended_reg: converting non-extending mem load in "

"use_as_extended_reg: dest reg %d of extending insn %d is "

Given a reg that is known to be sign or zero extended at some insn , take the appropriate measures so that the extended value can be used as a reg at the specified insn and return the resulting reg rtx .


<s> StringRef getName ( ) const { return StringRef ( reinterpret_cast < const char * > ( this ) + sizeof ( * this ) , namesz ) ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this , Options . StackAlignmentOverride ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = FloatABI :: Hard ; if ( Subtarget . isTargetWin64 ( ) ) this -> Options . TrapUnreachable = true ; initAsmInfo ( ) ; } </s>


<s> bool HexagonFrameLowering :: hasFP ( const MachineFunction & MF ) const { auto & MFI = MF . getFrameInfo ( ) ; auto & HRI = * MF . getSubtarget < HexagonSubtarget > ( ) . getRegisterInfo ( ) ; bool HasFixed = MFI . getNumFixedObjects ( ) ; bool HasPrealloc = const_cast < MachineFrameInfo & > ( MFI ) . getLocalFrameObjectCount ( ) ; bool HasExtraAlign = HRI . needsStackRealignment ( MF ) ; bool HasAlloca = MFI . hasVarSizedObjects ( ) ; if ( MF . getTarget ( ) . getOptLevel ( ) == CodeGenOpt :: None ) return true ; if ( ( HasFixed || HasPrealloc ) && ( HasAlloca || HasExtraAlign ) ) return true ; if ( MFI . getStackSize ( ) > 0 ) { if ( EnableStackOVFSanitizer || UseAllocframe ) return true ; } if ( MFI . hasCalls ( ) || MF . getInfo < HexagonMachineFunctionInfo > ( ) -> hasClobberLR ( ) ) return true ; return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


"Can only insert epilog into returning blocks"


<s> bool CAHPAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { if ( ! ExtraCode ) { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; if ( ! MO . isReg ( ) ) return true ; OS << "0(" << CAHPInstPrinter :: getRegisterName ( MO . getReg ( ) ) << ")" ; return false ; } return AsmPrinter :: PrintAsmMemoryOperand ( MI , OpNo , ExtraCode , OS ) ; } </s>


<s> EVT SITargetLowering :: getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const { if ( Op . size ( ) >= 16 && Op . isDstAligned ( Align ( 4 ) ) ) return MVT :: v4i32 ; if ( Op . size ( ) >= 8 && Op . isDstAligned ( Align ( 4 ) ) ) return MVT :: v2i32 ; return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> void OpenRISCAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { OpenRISCMCInstLower MCInstLowering ( OutContext , * Mang , * this ) ; MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; OutStreamer . EmitInstruction ( TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> MCRegister SIRegisterInfo :: findUnusedRegister ( const MachineRegisterInfo & MRI , const TargetRegisterClass * RC , const MachineFunction & MF , bool ReserveHighestVGPR ) const { if ( ReserveHighestVGPR ) { for ( MCRegister Reg : reverse ( * RC ) ) if ( MRI . isAllocatable ( Reg ) && ! MRI . isPhysRegUsed ( Reg ) ) return Reg ; } else { for ( MCRegister Reg : * RC ) if ( MRI . isAllocatable ( Reg ) && ! MRI . isPhysRegUsed ( Reg ) ) return Reg ; } return MCRegister ( ) ; } </s>

Returns a lowest register that is not used at any point in the function .


<s>
bool
FixupBWInstPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
!
FixupBWInsts
||
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
this
->
MF
=
&
MF
;
TII
=
MF
.
getSubtarget
<
X86Subtarget
>
(
)
.
getInstrInfo
(
)
;
OptForSize
=
MF
.
getFunction
(
)
.
optForSize
(
)
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
LiveRegs
.
init
(
TII
->
getRegisterInfo
(
)
)
;
DEBUG
(
dbgs
(
)
<<
"Start X86FixupBWInsts\n"
;
)
;
for
(
auto
&
MBB
:
MF
)
processBasicBlock
(
MF
,
MBB
)
;
DEBUG
(
dbgs
(
)
<<
"End X86FixupBWInsts\n"
;
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static int thumb_find_work_register ( unsigned long pushed_regs_mask ) { int reg ; for ( reg = LAST_ARG_REGNUM ; reg >= 0 ; reg -- ) if ( ! regs_ever_live [ reg ] ) return reg ; if ( cfun -> machine -> uses_anonymous_args && current_function_pretend_args_size > 0 ) return LAST_ARG_REGNUM ; if ( ! cfun -> machine -> uses_anonymous_args && current_function_args_size >= 0 && current_function_args_size <= ( LAST_ARG_REGNUM * UNITS_PER_WORD ) && cfun -> args_info . nregs < 4 ) return LAST_ARG_REGNUM ; for ( reg = LAST_LO_REGNUM ; reg > LAST_ARG_REGNUM ; reg -- ) if ( pushed_regs_mask & ( 1 << reg ) ) return reg ; gcc_unreachable ( ) ; } </s>

Find a spare low register to use during the prolog of a function .


<s> unsigned getCSRFirstUseCost ( ) const override { return 100 ; } </s>

Allow the target to override the cost of using a callee-saved register for the first time .


<s> machine_mode select_cc_mode ( enum rtx_code op , rtx x , rtx y ATTRIBUTE_UNUSED ) { if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) { switch ( op ) { case EQ : case NE : case UNORDERED : case ORDERED : case UNLT : case UNLE : case UNGT : case UNGE : case UNEQ : case LTGT : return CCFPmode ; case LT : case LE : case GT : case GE : return CCFPEmode ; default : gcc_unreachable ( ) ; } } else if ( GET_CODE ( x ) == PLUS || GET_CODE ( x ) == MINUS || GET_CODE ( x ) == NEG || GET_CODE ( x ) == ASHIFT ) { if ( TARGET_ARCH64 && GET_MODE ( x ) == DImode ) return CCX_NOOVmode ; else return CC_NOOVmode ; } else { if ( TARGET_ARCH64 && GET_MODE ( x ) == DImode ) return CCXmode ; else return CCmode ; } } </s>

Given a comparison code ( EQ , NE , etc . ) and the first operand of a COMPARE , return the mode to be used for the comparison . For floating-point , CCFP [ E ] mode is used . CC_NOOVmode should be used when the first operand is a PLUS , MINUS , NEG , or ASHIFT . CCmode should be used when no special processing is needed .


<s> static bool m32c_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { return m32c_hard_regno_nregs_1 ( regno , mode ) != 0 ; } </s>

Implement TARGET_HARD_REGNO_MODE_OK . The above function does the work already ; just test its return value .


"unrecognised interrupt vector argument of %qE attribute"

"numeric argument of %qE attribute must be in range 0..63"

"argument of %qE attribute is not a string constant or number"

"%qE attribute only applies to functions"

"critical functions cannot be reentrant"

"reentrant functions cannot be critical"


<s> int simple_memory_operand ( rtx op , machine_mode mode ATTRIBUTE_UNUSED ) { rtx addr ; if ( GET_CODE ( op ) != MEM ) return FALSE ; indirection : addr = XEXP ( op , 0 ) ; switch ( GET_CODE ( addr ) ) { case REG : return 1 ; case PRE_DEC : case POST_INC : case PRE_MODIFY : case POST_MODIFY : return 1 ; case MEM : if ( GET_CODE ( XEXP ( addr , 0 ) ) == REG ) return 0 ; op = addr ; goto indirection ; case CONST_INT : case LABEL_REF : case CONST : case SYMBOL_REF : return 0 ; case PLUS : return 0 ; default : break ; } return FALSE ; } </s>

Return truth value if a memory operand fits in a single instruction ( ie , register + small offset ) .


<s> static void emit_push_byte ( unsigned regno , bool frame_related_p ) { rtx mem , reg ; rtx_insn * insn ; mem = gen_rtx_POST_DEC ( HImode , stack_pointer_rtx ) ; mem = gen_frame_mem ( QImode , mem ) ; reg = gen_rtx_REG ( QImode , regno ) ; insn = emit_insn ( gen_rtx_SET ( VOIDmode , mem , reg ) ) ; if ( frame_related_p ) RTX_FRAME_RELATED_P ( insn ) = 1 ; cfun -> machine -> stack_usage ++ ; } </s>

Helper for expand_prologue . Emit a push of a byte register .


"Pseudo opcode found in EmitInstruction()"


<s>
void
ARMInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
DebugLoc
::
getUnknownLoc
(
)
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
if
(
RC
==
ARM
::
GPRRegisterClass
)
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
ARMFunctionInfo
*
AFI
=
MF
.
getInfo
<
ARMFunctionInfo
>
(
)
;
assert
(
!
AFI
->
isThumbFunction
(
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
STR
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addReg
(
0
)
.
addImm
(
0
)
)
;
}
else
if
(
RC
==
ARM
::
tGPRRegisterClass
)
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
ARMFunctionInfo
*
AFI
=
MF
.
getInfo
<
ARMFunctionInfo
>
(
)
;
assert
(
AFI
->
isThumbFunction
(
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tSpill
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
}
else
if
(
RC
==
ARM
::
DPRRegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
FSTD
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
)
;
}
else
{
assert
(
RC
==
ARM
::
SPRRegisterClass
&&
"Unknown regclass!"
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
FSTS
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .

ARM
ARM
ARM::GPRRegisterClass
ARM
ARM
ARM::STR
0
0
ARM::tGPRRegisterClass
ARM
ARM
ARM::tSpill
0
ARM::DPRRegisterClass
ARM::FSTD
0
ARM::SPRRegisterClass
"Unknown regclass!"
ARM::FSTS
0


<s>
static
const
char
*
ia64_invalid_binary_op
(
int
op
ATTRIBUTE_UNUSED
,
const_tree
type1
,
const_tree
type2
)
{
if
(
TYPE_MODE
(
type1
)
==
RFmode
||
TYPE_MODE
(
type2
)
==
RFmode
)
return
N_
(
"invalid operation on %<__fpreg%>"
)
;
return
;
}
</s>

Return the diagnostic message string if the binary operation OP is not permitted on TYPE1 and TYPE2 , NULL otherwise .


"Cannot store this register to stack slot!"

Load the specified register of the given register class from the specified stack frame index .


<s> void MCS51FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( hasFP ( MF ) ) { SavedRegs . set ( MCS51 :: R29 ) ; SavedRegs . set ( MCS51 :: R28 ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> static int ix86_mode_needed ( int entity , rtx_insn * insn ) { switch ( entity ) { case X86_DIRFLAG : return ix86_dirflag_mode_needed ( insn ) ; case AVX_U128 : return ix86_avx_u128_mode_needed ( insn ) ; case I387_ROUNDEVEN : case I387_TRUNC : case I387_FLOOR : case I387_CEIL : return ix86_i387_mode_needed ( entity , insn ) ; default : gcc_unreachable ( ) ; } return 0 ; } </s>

Return needed mode for entity in optimize_mode_switching pass .


<s> bool SIFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MFI . hasCalls ( ) ) { if ( MFI . getStackSize ( ) != 0 ) return true ; if ( MF . getInfo < SIMachineFunctionInfo > ( ) -> isEntryFunction ( ) ) return true ; } return MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || MF . getSubtarget < GCNSubtarget > ( ) . getRegisterInfo ( ) -> needsStackRealignment ( MF ) || MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool XtensaPassConfig :: addInstSelector ( ) { addPass ( createXtensaISelDag ( getXtensaTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s>
const
RegisterBank
&
SPIRVRegisterBankInfo
::
getRegBankFromRegClass
(
const
TargetRegisterClass
&
RC
,
LLT
Ty
)
const
{
switch
(
RC
.
getID
(
)
)
{
case
SPIRV
::
TYPERegClassID
:
return
SPIRV
::
TYPERegBank
;
case
SPIRV
::
pIDRegClassID
:
case
SPIRV
::
IDRegClassID
:
return
SPIRV
::
IDRegBank
;
case
SPIRV
::
fIDRegClassID
:
return
SPIRV
::
fIDRegBank
;
case
SPIRV
::
vIDRegClassID
:
return
SPIRV
::
vIDRegBank
;
case
SPIRV
::
vfIDRegClassID
:
return
SPIRV
::
vfIDRegBank
;
case
SPIRV
::
ANYIDRegClassID
:
case
SPIRV
::
ANYRegClassID
:
return
SPIRV
::
IDRegBank
;
}
llvm_unreachable
(
"Unknown register class"
)
;
}
</s>

SPIRV
SPIRV
SPIRV::TYPERegClassID
SPIRV::TYPERegBank
SPIRV::pIDRegClassID
SPIRV::IDRegClassID
SPIRV::IDRegBank
SPIRV::fIDRegClassID
SPIRV::fIDRegBank
SPIRV::vIDRegClassID
SPIRV::vIDRegBank
SPIRV::vfIDRegClassID
SPIRV::vfIDRegBank
SPIRV::ANYIDRegClassID
SPIRV::ANYRegClassID
SPIRV::IDRegBank
"Unknown register class"


<s> int RISCVFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const auto * RVFI = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; bool HasRISCVVector = RVFI -> hasSpillVRs ( ) ; const auto & CSI = getNonLibcallCSI ( MFI . getCalleeSavedInfo ( ) ) ; int MinCSFI = 0 ; int MaxCSFI = - 1 ; int Offset = MFI . getObjectOffset ( FI ) - getOffsetOfLocalArea ( ) + MFI . getOffsetAdjustment ( ) ; uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( CSI . size ( ) ) { MinCSFI = CSI [ 0 ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - 1 ] . getFrameIdx ( ) ; } if ( FI >= MinCSFI && FI <= MaxCSFI ) { FrameReg = RISCV :: X2 ; if ( FirstSPAdjustAmount ) Offset += FirstSPAdjustAmount ; else Offset += MFI . getStackSize ( ) ; } else if ( RI -> needsStackRealignment ( MF ) && ! MFI . isFixedObjectIndex ( FI ) ) { if ( hasBP ( MF ) ) FrameReg = RISCVABI :: getBPReg ( ) ; else FrameReg = RISCV :: X2 ; Offset += MFI . getStackSize ( ) ; if ( FI < 0 ) Offset += RVFI -> getLibCallStackSize ( ) ; } else { FrameReg = RI -> getFrameRegister ( MF ) ; if ( hasFP ( MF ) ) { Offset += RVFI -> getVarArgsSaveSize ( ) ; if ( FI >= 0 ) Offset -= RVFI -> getLibCallStackSize ( ) ; } else { Offset += MFI . getStackSize ( ) ; if ( FI < 0 ) Offset += RVFI -> getLibCallStackSize ( ) ; } } return Offset ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


"loadRegFromStackSlot didn't insert any code!"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static bool aarch64_evpc_sve_tbl ( struct expand_vec_perm_d * d ) { unsigned HOST_WIDE_INT nelt ; if ( ! d -> one_vector_p && ! d -> perm . length ( ) . is_constant ( & nelt ) ) return false ; if ( d -> testing_p ) return true ; machine_mode sel_mode = mode_for_int_vector ( d -> vmode ) . require ( ) ; rtx sel = vec_perm_indices_to_rtx ( sel_mode , d -> perm ) ; if ( d -> one_vector_p ) emit_unspec2 ( d -> target , UNSPEC_TBL , d -> op0 , force_reg ( sel_mode , sel ) ) ; else aarch64_expand_sve_vec_perm ( d -> target , d -> op0 , d -> op1 , sel ) ; return true ; } </s>

Try to implement D using an SVE TBL instruction .


<s>
const
char
*
output_move_vfp
(
rtx
*
operands
)
{
rtx
reg
,
mem
,
addr
,
ops
[
2
]
;
int
load
=
REG_P
(
operands
[
0
]
)
;
int
dp
=
GET_MODE_SIZE
(
GET_MODE
(
operands
[
0
]
)
)
==
8
;
int
sp
=
(
!
TARGET_VFP_FP16INST
||
GET_MODE_SIZE
(
GET_MODE
(
operands
[
0
]
)
)
==
4
)
;
int
integer_p
=
GET_MODE_CLASS
(
GET_MODE
(
operands
[
0
]
)
)
==
MODE_INT
;
const
char
*
templ
;
char
buff
[
50
]
;
machine_mode
mode
;
reg
=
operands
[
!
load
]
;
mem
=
operands
[
load
]
;
mode
=
GET_MODE
(
reg
)
;
gcc_assert
(
REG_P
(
reg
)
)
;
gcc_assert
(
IS_VFP_REGNUM
(
REGNO
(
reg
)
)
)
;
gcc_assert
(
(
mode
==
HFmode
&&
TARGET_HARD_FLOAT
)
||
mode
==
SFmode
||
mode
==
DFmode
||
mode
==
HImode
||
mode
==
SImode
||
mode
==
DImode
||
(
TARGET_NEON
&&
VALID_NEON_DREG_MODE
(
mode
)
)
)
;
gcc_assert
(
MEM_P
(
mem
)
)
;
addr
=
XEXP
(
mem
,
0
)
;
switch
(
GET_CODE
(
addr
)
)
{
case
PRE_DEC
:
templ
=
"v%smdb%%?.%s\t%%0!, {%%%s1}%s"
;
ops
[
0
]
=
XEXP
(
addr
,
0
)
;
ops
[
1
]
=
reg
;
break
;
case
POST_INC
:
templ
=
"v%smia%%?.%s\t%%0!, {%%%s1}%s"
;
ops
[
0
]
=
XEXP
(
addr
,
0
)
;
ops
[
1
]
=
reg
;
break
;
default
:
templ
=
"v%sr%%?.%s\t%%%s0, %%1%s"
;
ops
[
0
]
=
reg
;
ops
[
1
]
=
mem
;
break
;
}
sprintf
(
buff
,
templ
,
load
"ld"
:
"st"
,
dp
"64"
:
sp
"32"
:
"16"
,
dp
"P"
:
""
,
integer_p
"\t%@ int"
:
""
)
;
output_asm_insn
(
buff
,
ops
)
;
return
""
;
}
</s>

Output a VFP load or store instruction .


<s> bool isLegalMaskedStore ( Type * DataType , MaybeAlign Alignment ) { return isLegalMaskedLoadStore ( DataType , Alignment ) ; } </s>

Return true if the target supports masked store .


runOnMachineFunction - Emit the function body .


<s> void rs6000_output_function_entry ( FILE * file , const char * fname ) { if ( fname [ 0 ] != '.' ) { switch ( DEFAULT_ABI ) { default : gcc_unreachable ( ) ; case ABI_AIX : if ( DOT_SYMBOLS ) putc ( '.' , file ) ; else ASM_OUTPUT_INTERNAL_LABEL_PREFIX ( file , "L." ) ; break ; case ABI_ELFv2 : case ABI_V4 : case ABI_DARWIN : break ; } } RS6000_OUTPUT_BASENAME ( file , fname ) ; } </s>


<s> bool SystemZTDCPass :: runOnFunction ( Function & F ) { auto & TPC = getAnalysis < TargetPassConfig > ( ) ; if ( TPC . getTM < TargetMachine > ( ) . getSubtarget < SystemZSubtarget > ( F ) . hasSoftFloat ( ) ) return false ; ConvertedInsts . clear ( ) ; LogicOpsWorklist . clear ( ) ; PossibleJunk . clear ( ) ; for ( auto & I : instructions ( F ) ) { if ( I . getOpcode ( ) == Instruction :: FCmp ) convertFCmp ( cast < CmpInst > ( I ) ) ; else if ( I . getOpcode ( ) == Instruction :: ICmp ) convertICmp ( cast < CmpInst > ( I ) ) ; } if ( ConvertedInsts . empty ( ) ) return false ; while ( ! LogicOpsWorklist . empty ( ) ) { BinaryOperator * Op = LogicOpsWorklist . back ( ) ; LogicOpsWorklist . pop_back ( ) ; if ( ConvertedInsts . count ( dyn_cast < Instruction > ( Op -> getOperand ( 0 ) ) ) && ConvertedInsts . count ( dyn_cast < Instruction > ( Op -> getOperand ( 1 ) ) ) && ! ConvertedInsts . count ( Op ) ) convertLogicOp ( * Op ) ; } Module & M = * F . getParent ( ) ; auto & Ctx = M . getContext ( ) ; Value * Zero32 = ConstantInt :: get ( Type :: getInt32Ty ( Ctx ) , 0 ) ; bool MadeChange = false ; for ( auto & It : reverse ( ConvertedInsts ) ) { Instruction * I = It . first ; Value * V ; int Mask ; bool Worthy ; std :: tie ( V , Mask , Worthy ) = It . second ; if ( ! I -> user_empty ( ) ) { if ( ! Worthy ) continue ; Function * TDCFunc = Intrinsic :: getDeclaration ( & M , Intrinsic :: s390_tdc , V -> getType ( ) ) ; IRBuilder < > IRB ( I ) ; Value * MaskVal = ConstantInt :: get ( Type :: getInt64Ty ( Ctx ) , Mask ) ; Instruction * TDC = IRB . CreateCall ( TDCFunc , { V , MaskVal } ) ; Value * ICmp = IRB . CreateICmp ( CmpInst :: ICMP_NE , TDC , Zero32 ) ; I -> replaceAllUsesWith ( ICmp ) ; } I -> eraseFromParent ( ) ; MadeChange = true ; } if ( ! MadeChange ) return false ; for ( auto * I : PossibleJunk ) if ( I -> user_empty ( ) ) I -> eraseFromParent ( ) ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool AMDGPUCodeGenPrepare :: runOnFunction ( Function & F ) { if ( ! TM || skipFunction ( F ) ) return false ; DA = & getAnalysis < DivergenceAnalysis > ( ) ; visit ( F ) ; return true ; } </s>


<s>
MachineBasicBlock
*
XCoreTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
const
TargetInstrInfo
&
TII
=
*
getTargetMachine
(
)
.
getInstrInfo
(
)
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
assert
(
(
MI
->
getOpcode
(
)
==
XCore
::
SELECT_CC
)
&&
"Unexpected instr type to insert"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
It
=
BB
;
++
It
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
sinkMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
F
->
insert
(
It
,
copy0MBB
)
;
F
->
insert
(
It
,
sinkMBB
)
;
sinkMBB
->
splice
(
sinkMBB
->
begin
(
)
,
BB
,
llvm
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
BB
->
end
(
)
)
;
sinkMBB
->
transferSuccessorsAndUpdatePHIs
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
sinkMBB
)
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
XCore
::
BRFT_lru6
)
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
sinkMBB
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
sinkMBB
;
BuildMI
(
*
BB
,
BB
->
begin
(
)
,
dl
,
TII
.
get
(
XCore
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
3
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
MI
->
eraseFromParent
(
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static rtx ix86_expand_sse_cmp ( rtx dest , enum rtx_code code , rtx cmp_op0 , rtx cmp_op1 , rtx op_true , rtx op_false ) { machine_mode mode = GET_MODE ( dest ) ; machine_mode cmp_ops_mode = GET_MODE ( cmp_op0 ) ; machine_mode cmp_mode ; bool maskcmp = false ; rtx x ; if ( GET_MODE_SIZE ( cmp_ops_mode ) == 64 ) { cmp_mode = mode_for_size ( GET_MODE_NUNITS ( cmp_ops_mode ) , MODE_INT , 0 ) ; gcc_assert ( cmp_mode != BLKmode ) ; maskcmp = true ; } else cmp_mode = cmp_ops_mode ; cmp_op0 = force_reg ( cmp_ops_mode , cmp_op0 ) ; if ( ! nonimmediate_operand ( cmp_op1 , cmp_ops_mode ) ) cmp_op1 = force_reg ( cmp_ops_mode , cmp_op1 ) ; if ( optimize || ( maskcmp && cmp_mode != mode ) || ( op_true && reg_overlap_mentioned_p ( dest , op_true ) ) || ( op_false && reg_overlap_mentioned_p ( dest , op_false ) ) ) dest = gen_reg_rtx ( maskcmp ? cmp_mode : mode ) ; if ( maskcmp && ( code == GT || code == EQ ) ) { rtx ( * gen ) ( rtx , rtx , rtx ) ; switch ( cmp_ops_mode ) { case V64QImode : gcc_assert ( TARGET_AVX512BW ) ; gen = code == GT ? gen_avx512bw_gtv64qi3 : gen_avx512bw_eqv64qi3_1 ; break ; case V32HImode : gcc_assert ( TARGET_AVX512BW ) ; gen = code == GT ? gen_avx512bw_gtv32hi3 : gen_avx512bw_eqv32hi3_1 ; break ; case V16SImode : gen = code == GT ? gen_avx512f_gtv16si3 : gen_avx512f_eqv16si3_1 ; break ; case V8DImode : gen = code == GT ? gen_avx512f_gtv8di3 : gen_avx512f_eqv8di3_1 ; break ; default : gen = NULL ; } if ( gen ) { emit_insn ( gen ( dest , cmp_op0 , cmp_op1 ) ) ; return dest ; } } x = gen_rtx_fmt_ee ( code , cmp_mode , cmp_op0 , cmp_op1 ) ; if ( cmp_mode != mode && ! maskcmp ) { x = force_reg ( cmp_ops_mode , x ) ; convert_move ( dest , x , false ) ; } else emit_insn ( gen_rtx_SET ( dest , x ) ) ; return dest ; } </s>

Expand an sse vector comparison . Return the register with the result .


<s> bool nvptx_libc_has_function ( enum function_class fn_class , tree type ) { if ( fn_class == function_sincos ) { if ( type != NULL_TREE ) return type == float_type_node || type == double_type_node ; else return true ; } return default_libc_has_function ( fn_class , type ) ; } </s>


<s> SMLoc getLoc ( ) const { return getParser ( ) . getTok ( ) . getLoc ( ) ; } </s>

Get the source location of the point where the field was defined .


<s> void LM32InstPrinter :: printRegName ( raw_ostream & O , unsigned RegNo ) const { O << '%' << getRegisterName ( RegNo ) ; } </s>


<s> static bool fusion_load_store ( rtx_insn * insn , rtx * base , rtx * offset , bool * is_load ) { rtx x , dest , src ; gcc_assert ( INSN_P ( insn ) ) ; x = PATTERN ( insn ) ; if ( GET_CODE ( x ) != SET ) return false ; src = SET_SRC ( x ) ; dest = SET_DEST ( x ) ; if ( REG_P ( src ) && MEM_P ( dest ) ) { * is_load = false ; extract_base_offset_in_addr ( dest , base , offset ) ; } else if ( MEM_P ( src ) && REG_P ( dest ) ) { * is_load = true ; extract_base_offset_in_addr ( src , base , offset ) ; } else return false ; return ( * base != NULL_RTX && * offset != NULL_RTX ) ; } </s>

If INSN is a load or store of address in the form of [ base+offset ] , extract the two parts and set to BASE and OFFSET . IS_LOAD is set to TRUE if it 's a load . Return TRUE if INSN is such an instruction , otherwise return FALSE .


<s> static int get_vec_cmp_insn ( enum rtx_code code , enum machine_mode dest_mode , enum machine_mode op_mode ) { if ( ! TARGET_ALTIVEC ) return INSN_NOT_AVAILABLE ; switch ( code ) { case EQ : if ( dest_mode == V16QImode && op_mode == V16QImode ) return UNSPEC_VCMPEQUB ; if ( dest_mode == V8HImode && op_mode == V8HImode ) return UNSPEC_VCMPEQUH ; if ( dest_mode == V4SImode && op_mode == V4SImode ) return UNSPEC_VCMPEQUW ; if ( dest_mode == V4SImode && op_mode == V4SFmode ) return UNSPEC_VCMPEQFP ; break ; case GE : if ( dest_mode == V4SImode && op_mode == V4SFmode ) return UNSPEC_VCMPGEFP ; case GT : if ( dest_mode == V16QImode && op_mode == V16QImode ) return UNSPEC_VCMPGTSB ; if ( dest_mode == V8HImode && op_mode == V8HImode ) return UNSPEC_VCMPGTSH ; if ( dest_mode == V4SImode && op_mode == V4SImode ) return UNSPEC_VCMPGTSW ; if ( dest_mode == V4SImode && op_mode == V4SFmode ) return UNSPEC_VCMPGTFP ; break ; case GTU : if ( dest_mode == V16QImode && op_mode == V16QImode ) return UNSPEC_VCMPGTUB ; if ( dest_mode == V8HImode && op_mode == V8HImode ) return UNSPEC_VCMPGTUH ; if ( dest_mode == V4SImode && op_mode == V4SImode ) return UNSPEC_VCMPGTUW ; break ; default : break ; } return INSN_NOT_AVAILABLE ; } </s>

Return insn index for the vector compare instruction for given CODE , and DEST_MODE , OP_MODE . Return -1 if valid insn is not available .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Mips Delay Slot Filler"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static bool pru_addr_space_legitimate_address_p ( machine_mode mode , rtx operand , bool strict_p , addr_space_t as ) { if ( as == ADDR_SPACE_REGIO ) { return true ; } else if ( as != ADDR_SPACE_GENERIC ) { gcc_unreachable ( ) ; } switch ( GET_CODE ( operand ) ) { case SYMBOL_REF : case LABEL_REF : case CONST : case CONST_WIDE_INT : return false ; case CONST_INT : return ctable_addr_operand ( operand , VOIDmode ) ; case REG : return pru_regno_ok_for_base_p ( REGNO ( operand ) , strict_p ) ; case PLUS : { rtx op0 = XEXP ( operand , 0 ) ; rtx op1 = XEXP ( operand , 1 ) ; return pru_valid_addr_expr_p ( mode , op0 , op1 , strict_p ) ; } default : break ; } return false ; } </s>


<s> unsigned X86FrameLowering :: getWinEHFuncletFrameSize ( const MachineFunction & MF ) const { unsigned CSSize = MF . getInfo < X86MachineFunctionInfo > ( ) -> getCalleeSavedFrameSize ( ) ; unsigned UsedSize ; EHPersonality Personality = classifyEHPersonality ( MF . getFunction ( ) -> getPersonalityFn ( ) ) ; if ( Personality == EHPersonality :: CoreCLR ) { UsedSize = getPSPSlotOffsetFromSP ( MF ) + SlotSize ; } else { UsedSize = MF . getFrameInfo ( ) -> getMaxCallFrameSize ( ) ; } unsigned FrameSizeMinusRBP = alignTo ( CSSize + UsedSize , getStackAlignment ( ) ) ; return FrameSizeMinusRBP - CSSize ; } </s>

Funclets only need to account for space for the callee saved registers , as the locals are accounted for in the parent 's stack frame .


<s> bool mips_use_pic_fn_addr_reg_p ( const_rtx x ) { if ( ! TARGET_USE_PIC_FN_ADDR_REG ) return false ; if ( mips16_stub_function_p ( x ) ) return false ; if ( GET_CODE ( x ) == SYMBOL_REF ) { if ( TARGET_ABICALLS_PIC0 ) return false ; if ( TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p ( x ) && ! SYMBOL_REF_EXTERNAL_P ( x ) ) return false ; } return true ; } </s>

Return true if calls to X might need $ 25 to be valid on entry .


<s> bool PPCInstrInfo :: isAssociativeAndCommutative ( const MachineInstr & Inst ) const { switch ( Inst . getOpcode ( ) ) { case PPC :: FADD : case PPC :: FADDS : case PPC :: FMUL : case PPC :: FMULS : case PPC :: VADDFP : case PPC :: XSADDDP : case PPC :: XVADDDP : case PPC :: XVADDSP : case PPC :: XSADDSP : case PPC :: XSMULDP : case PPC :: XVMULDP : case PPC :: XVMULSP : case PPC :: XSMULSP : return Inst . getFlag ( MachineInstr :: MIFlag :: FmReassoc ) && Inst . getFlag ( MachineInstr :: MIFlag :: FmNsz ) ; case PPC :: MULHD : case PPC :: MULLD : case PPC :: MULHW : case PPC :: MULLW : return true ; default : return false ; } } </s>

Return true when \P Inst is both associative and commutative .

PowerPC PPC PPC::FADD PPC::FADDS PPC::FMUL PPC::FMULS PPC::VADDFP PPC::XSADDDP PPC::XVADDDP PPC::XVADDSP PPC::XSADDSP PPC::XSMULDP PPC::XVMULDP PPC::XVMULSP PPC::XSMULSP PPC::MULHD PPC::MULLD PPC::MULHW PPC::MULLW


<s> const char * VETargetLowering :: getTargetNodeName ( unsigned Opcode ) const { case VEISD :: NAME : \ return "VEISD::" # NAME ; switch ( ( VEISD :: NodeType ) Opcode ) { case VEISD :: FIRST_NUMBER : break ; TARGET_NODE_CASE ( Lo ) TARGET_NODE_CASE ( Hi ) TARGET_NODE_CASE ( GETFUNPLT ) TARGET_NODE_CASE ( CALL ) TARGET_NODE_CASE ( RET_FLAG ) TARGET_NODE_CASE ( GLOBAL_BASE_REG ) } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

VE VE VEISD::NAME "VEISD::" VEISD::NodeType VEISD::FIRST_NUMBER


<s> int pa_adjust_insn_length ( rtx_insn * insn , int length ) { rtx pat = PATTERN ( insn ) ; if ( ( unsigned int ) length >= INT_MAX ) { if ( GET_CODE ( pat ) == SEQUENCE ) insn = as_a < rtx_insn * > ( XVECEXP ( pat , 0 , 0 ) ) ; switch ( get_attr_type ( insn ) ) { case TYPE_MILLI : length = pa_attr_length_millicode_call ( insn ) ; break ; case TYPE_CALL : length = pa_attr_length_call ( insn , 0 ) ; break ; case TYPE_SIBCALL : length = pa_attr_length_call ( insn , 1 ) ; break ; case TYPE_DYNCALL : length = pa_attr_length_indirect_call ( insn ) ; break ; case TYPE_SH_FUNC_ADRS : length = pa_attr_length_millicode_call ( insn ) + 20 ; break ; default : gcc_unreachable ( ) ; } } if ( NONJUMP_INSN_P ( insn ) && GET_CODE ( pat ) == PARALLEL && GET_CODE ( XVECEXP ( pat , 0 , 0 ) ) == SET && GET_CODE ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 0 ) ) == MEM && GET_CODE ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 1 ) ) == MEM && GET_MODE ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 0 ) ) == BLKmode && GET_MODE ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 1 ) ) == BLKmode ) length += compute_movmem_length ( insn ) - 4 ; else if ( NONJUMP_INSN_P ( insn ) && GET_CODE ( pat ) == PARALLEL && GET_CODE ( XVECEXP ( pat , 0 , 0 ) ) == SET && GET_CODE ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 0 ) ) == MEM && XEXP ( XVECEXP ( pat , 0 , 0 ) , 1 ) == const0_rtx && GET_MODE ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 0 ) ) == BLKmode ) length += compute_clrmem_length ( insn ) - 4 ; else if ( JUMP_P ( insn ) && ! simplejump_p ( insn ) ) { if ( GET_CODE ( pat ) == SET && length == 4 && JUMP_LABEL ( insn ) != NULL_RTX && ! forward_branch_p ( insn ) ) length += 4 ; else if ( GET_CODE ( pat ) == PARALLEL && get_attr_type ( insn ) == TYPE_PARALLEL_BRANCH && length == 4 ) length += 4 ; else if ( GET_CODE ( pat ) == PARALLEL && GET_CODE ( XVECEXP ( pat , 0 , 1 ) ) == SET && GET_CODE ( XEXP ( XVECEXP ( pat , 0 , 1 ) , 0 ) ) == REG && ! FP_REG_P ( XEXP ( XVECEXP ( pat , 0 , 1 ) , 0 ) ) && length == 4 && ! forward_branch_p ( insn ) ) length += 4 ; } return length ; } </s>

Return any length adjustment needed by INSN which already has its length computed as LENGTH . Return zero if no adjustment is necessary . For the PA : function calls , millicode calls , and backwards short conditional branches with unfilled delay slots need an adjustment by +1 ( to account for the NOP which will be inserted into the instruction stream ) . Also compute the length of an inline block move here as it is too complicated to express as a length attribute in pa.md .


<s> static void assign_int_registers ( HOST_WIDE_INT bitpos , assign_data_t * data ) { int intoffset = data -> intoffset ; machine_mode mode ; int nregs ; if ( ! compute_int_layout ( bitpos , data , & nregs ) ) return ; if ( intoffset % BITS_PER_WORD != 0 ) mode = smallest_mode_for_size ( BITS_PER_WORD - intoffset % BITS_PER_WORD , MODE_INT ) ; else mode = word_mode ; const int this_slotno = data -> slotno + intoffset / BITS_PER_WORD ; unsigned int regno = data -> regbase + this_slotno ; intoffset /= BITS_PER_UNIT ; do { rtx reg = gen_rtx_REG ( mode , regno ) ; XVECEXP ( data -> ret , 0 , data -> stack + data -> nregs ) = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( intoffset ) ) ; data -> nregs += 1 ; mode = word_mode ; regno += 1 ; intoffset = ( intoffset | ( UNITS_PER_WORD - 1 ) ) + 1 ; } while ( -- nregs > 0 ) ; } </s>

A subroutine of function_arg_record_value . Assign the bits of the structure between PARMS- > intoffset and BITPOS to integer registers .


<s> static void ix86_emit_mode_set ( int entity , int mode , int prev_mode ATTRIBUTE_UNUSED , HARD_REG_SET regs_live ATTRIBUTE_UNUSED ) { switch ( entity ) { case X86_DIRFLAG : if ( mode == X86_DIRFLAG_RESET ) emit_insn ( gen_cld ( ) ) ; break ; case AVX_U128 : if ( mode == AVX_U128_CLEAN ) ix86_expand_avx_vzeroupper ( ) ; break ; case I387_ROUNDEVEN : case I387_TRUNC : case I387_FLOOR : case I387_CEIL : if ( mode != I387_CW_ANY && mode != I387_CW_UNINITIALIZED ) emit_i387_cw_initialization ( mode ) ; break ; default : gcc_unreachable ( ) ; } } </s>

Generate one or more insns to set ENTITY to MODE . HARD_REG_LIVE is the set of hard registers live at the point where the insn ( s ) are to be inserted .


<s> static rtx moxie_function_arg ( cumulative_args_t cum_v , machine_mode mode , const_tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( * cum < 8 ) return gen_rtx_REG ( mode , * cum ) ; else return NULL_RTX ; } </s>

Return the next register to be used to hold a function argument or NULL_RTX if there 's no more space .


"All regions recorded, starting actual scheduling.\n"

"Retrying function scheduling with lowest recorded occupancy "

After the schedule has been formed , call this function to combine the instructions from the different stages/cycles .


<s> const MOSInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


"MSA requires a 64-bit FPU register file (FR=1 mode). "

This constructor initializes the data members to match that of the specified triple .


<s> void s390_expand_vcond ( rtx target , rtx then , rtx els , enum rtx_code cond , rtx cmp_op1 , rtx cmp_op2 ) { rtx tmp ; machine_mode result_mode ; rtx result_target ; machine_mode target_mode = GET_MODE ( target ) ; machine_mode cmp_mode = GET_MODE ( cmp_op1 ) ; rtx op = ( cond == LT ) ? els : then ; if ( ( cond == LT || cond == GE ) && target_mode == cmp_mode && cmp_op2 == CONST0_RTX ( cmp_mode ) && op == CONST0_RTX ( target_mode ) && s390_vector_mode_supported_p ( target_mode ) && GET_MODE_CLASS ( target_mode ) == MODE_VECTOR_INT ) { rtx negop = ( cond == LT ) ? then : els ; int shift = GET_MODE_BITSIZE ( GET_MODE_INNER ( target_mode ) ) - 1 ; if ( negop == CONST1_RTX ( target_mode ) ) { rtx res = expand_simple_binop ( cmp_mode , LSHIFTRT , cmp_op1 , GEN_INT ( shift ) , target , 1 , OPTAB_DIRECT ) ; if ( res != target ) emit_move_insn ( target , res ) ; return ; } else if ( all_ones_operand ( negop , target_mode ) ) { rtx res = expand_simple_binop ( cmp_mode , ASHIFTRT , cmp_op1 , GEN_INT ( shift ) , target , 0 , OPTAB_DIRECT ) ; if ( res != target ) emit_move_insn ( target , res ) ; return ; } } result_mode = mode_for_vector ( int_mode_for_mode ( GET_MODE_INNER ( cmp_mode ) ) , GET_MODE_NUNITS ( cmp_mode ) ) ; result_target = gen_reg_rtx ( result_mode ) ; if ( ! REG_P ( cmp_op1 ) ) cmp_op1 = force_reg ( GET_MODE ( cmp_op1 ) , cmp_op1 ) ; if ( ! REG_P ( cmp_op2 ) ) cmp_op2 = force_reg ( GET_MODE ( cmp_op2 ) , cmp_op2 ) ; s390_expand_vec_compare ( result_target , cond , cmp_op1 , cmp_op2 ) ; if ( all_ones_operand ( then , GET_MODE ( then ) ) && const0_operand ( els , GET_MODE ( els ) ) ) { emit_move_insn ( target , gen_rtx_SUBREG ( target_mode , result_target , 0 ) ) ; return ; } if ( ! REG_P ( then ) ) then = force_reg ( target_mode , then ) ; if ( ! REG_P ( els ) ) els = force_reg ( target_mode , els ) ; tmp = gen_rtx_fmt_ee ( EQ , VOIDmode , result_target , CONST0_RTX ( result_mode ) ) ; tmp = gen_rtx_IF_THEN_ELSE ( target_mode , tmp , els , then ) ; gcc_assert ( target_mode == GET_MODE ( then ) ) ; emit_insn ( gen_rtx_SET ( target , tmp ) ) ; } </s>

Generate a vector comparison expression loading either elements of THEN or ELS into TARGET depending on the comparison COND of CMP_OP1 and CMP_OP2 .


<s> static bool quad_aligned_store_p ( swap_web_entry * insn_entry , rtx_insn * insn ) { unsigned uid = INSN_UID ( insn ) ; if ( ! insn_entry [ uid ] . is_swap || ! insn_entry [ uid ] . is_store ) return false ; rtx body = PATTERN ( insn ) ; rtx dest_address = XEXP ( SET_DEST ( body ) , 0 ) ; rtx swap_reg = XEXP ( SET_SRC ( body ) , 0 ) ; if ( ! REG_P ( dest_address ) && ! rs6000_sum_of_two_registers_p ( dest_address ) ) return false ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref use ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( ! rtx_equal_p ( DF_REF_REG ( use ) , swap_reg ) ) continue ; if ( ! def_link || ! def_link -> ref || DF_REF_IS_ARTIFICIAL ( def_link -> ref ) || def_link -> next ) return false ; rtx def_insn = DF_REF_INSN ( def_link -> ref ) ; unsigned uid2 = INSN_UID ( def_insn ) ; if ( ! insn_entry [ uid2 ] . is_swap || insn_entry [ uid2 ] . is_load || insn_entry [ uid2 ] . is_store ) return false ; break ; } rtx set = single_set ( insn ) ; if ( set ) { rtx dest = SET_DEST ( set ) ; if ( MEM_P ( dest ) ) return ( MEM_ALIGN ( dest ) >= 128 ) ; } return false ; } </s>

Return TRUE if INSN represents a store-with-swap of a swapped value and the memory address is quad-word aligned .


<s> static rtx frame_subreg_note ( rtx set , int offset ) { rtx src = simplify_gen_subreg ( SImode , SET_SRC ( set ) , DImode , offset ) ; rtx dst = simplify_gen_subreg ( SImode , SET_DEST ( set ) , DImode , offset ) ; set = gen_rtx_SET ( VOIDmode , dst , src ) ; RTX_FRAME_RELATED_P ( set ) = 1 ; return set ; } </s>

For a DImode load / store SET , make a SImode set for a REG_FRAME_RELATED_EXPR note , using OFFSET to create a high or lowpart subreg .


<s> static rtx_insn * frame_emit_load ( int regno , rtx addr , HOST_WIDE_INT offset ) { rtx reg = gen_rtx_REG ( V4SImode , regno ) ; rtx mem = gen_frame_mem ( V4SImode , gen_rtx_PLUS ( Pmode , addr , GEN_INT ( offset ) ) ) ; return emit_insn ( gen_movv4si ( reg , mem ) ) ; } </s>

Emit a load in the stack frame to load REGNO from address ADDR . Add a REG_CFA_RESTORE note to CFA_RESTORES if CFA_RESTORES is non-null . Return the emitted insn .


<s> static rtx ix86_expand_sse_cmp ( rtx dest , enum rtx_code code , rtx cmp_op0 , rtx cmp_op1 , rtx op_true , rtx op_false ) { machine_mode mode = GET_MODE ( dest ) ; machine_mode cmp_ops_mode = GET_MODE ( cmp_op0 ) ; machine_mode cmp_mode ; bool maskcmp = false ; rtx x ; if ( GET_MODE_SIZE ( cmp_ops_mode ) == 64 ) { cmp_mode = mode_for_size ( GET_MODE_NUNITS ( cmp_ops_mode ) , MODE_INT , 0 ) ; gcc_assert ( cmp_mode != BLKmode ) ; maskcmp = true ; } else cmp_mode = cmp_ops_mode ; cmp_op0 = force_reg ( cmp_ops_mode , cmp_op0 ) ; if ( ! nonimmediate_operand ( cmp_op1 , cmp_ops_mode ) ) cmp_op1 = force_reg ( cmp_ops_mode , cmp_op1 ) ; if ( optimize || reg_overlap_mentioned_p ( dest , op_true ) || reg_overlap_mentioned_p ( dest , op_false ) ) dest = gen_reg_rtx ( maskcmp ? cmp_mode : mode ) ; if ( maskcmp && ( code == GT || code == EQ ) ) { rtx ( * gen ) ( rtx , rtx , rtx ) ; switch ( cmp_ops_mode ) { case V64QImode : gcc_assert ( TARGET_AVX512BW ) ; gen = code == GT ? gen_avx512bw_gtv64qi3 : gen_avx512bw_eqv64qi3_1 ; break ; case V32HImode : gcc_assert ( TARGET_AVX512BW ) ; gen = code == GT ? gen_avx512bw_gtv32hi3 : gen_avx512bw_eqv32hi3_1 ; break ; case V16SImode : gen = code == GT ? gen_avx512f_gtv16si3 : gen_avx512f_eqv16si3_1 ; break ; case V8DImode : gen = code == GT ? gen_avx512f_gtv8di3 : gen_avx512f_eqv8di3_1 ; break ; default : gen = NULL ; } if ( gen ) { emit_insn ( gen ( dest , cmp_op0 , cmp_op1 ) ) ; return dest ; } } x = gen_rtx_fmt_ee ( code , cmp_mode , cmp_op0 , cmp_op1 ) ; if ( cmp_mode != mode && ! maskcmp ) { x = force_reg ( cmp_ops_mode , x ) ; convert_move ( dest , x , false ) ; } else emit_insn ( gen_rtx_SET ( VOIDmode , dest , x ) ) ; return dest ; } </s>

Expand an sse vector comparison . Return the register with the result .