<s>
const
char
*
getPassName
(
)
const
{
return
"C64x+ specific post RA scheduler"
;
}
</s>


<s>
LLVM_DUMP_METHOD
void
dump
(
const
MachineRegisterInfo
*
MRI
)
const
{
dbgs
(
)
<<
"Registers: "
;
bool
First
=
true
;
for
(
Register
Reg
:
Edges
)
{
if
(
!
First
)
dbgs
(
)
<<
", "
;
First
=
false
;
dbgs
(
)
<<
printReg
(
Reg
,
MRI
->
getTargetRegisterInfo
(
)
,
0
,
MRI
)
;
}
dbgs
(
)
<<
"\n"
<<
"Instructions:"
;
for
(
MachineInstr
*
MI
:
Instrs
)
{
dbgs
(
)
<<
"\n  "
;
MI
->
print
(
dbgs
(
)
)
;
}
dbgs
(
)
<<
"\n"
;
}
</s>

Dump the plan to stderr ( for debugging ) .

X86
"Registers: "
", "
0
"\n"
"Instructions:"
"\n  "
"\n"


<s> static int aarch64_builtin_vectorization_cost ( enum vect_cost_for_stmt type_of_cost , tree vectype , int misalign ATTRIBUTE_UNUSED ) { unsigned elements ; const cpu_vector_cost * costs = aarch64_tune_params . vec_costs ; bool fp = false ; if ( vectype != NULL ) fp = FLOAT_TYPE_P ( vectype ) ; const simd_vec_cost * simd_costs = aarch64_simd_vec_costs ( vectype ) ; switch ( type_of_cost ) { case scalar_stmt : return fp ? costs -> scalar_fp_stmt_cost : costs -> scalar_int_stmt_cost ; case scalar_load : return costs -> scalar_load_cost ; case scalar_store : return costs -> scalar_store_cost ; case vector_stmt : return fp ? simd_costs -> fp_stmt_cost : simd_costs -> int_stmt_cost ; case vector_load : return simd_costs -> align_load_cost ; case vector_store : return simd_costs -> store_cost ; case vec_to_scalar : return simd_costs -> vec_to_scalar_cost ; case scalar_to_vec : return simd_costs -> scalar_to_vec_cost ; case unaligned_load : case vector_gather_load : return simd_costs -> unalign_load_cost ; case unaligned_store : case vector_scatter_store : return simd_costs -> unalign_store_cost ; case cond_branch_taken : return costs -> cond_taken_branch_cost ; case cond_branch_not_taken : return costs -> cond_not_taken_branch_cost ; case vec_perm : return simd_costs -> permute_cost ; case vec_promote_demote : return fp ? simd_costs -> fp_stmt_cost : simd_costs -> int_stmt_cost ; case vec_construct : elements = estimated_poly_value ( TYPE_VECTOR_SUBPARTS ( vectype ) ) ; return elements / 2 + 1 ; default : gcc_unreachable ( ) ; } } </s>


<s> const MCSection * AMDGPUMCAsmInfo :: getNonexecutableStackSection ( MCContext & CTX ) const { return nullptr ; } </s>

Targets can implement this method to specify a section to switch to if the translation unit does n't have any trampolines that require an executable stack .


<s> void HexagonAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst MCB ; MCB . setOpcode ( Hexagon :: BUNDLE ) ; MCB . addOperand ( MCOperand :: createImm ( 0 ) ) ; if ( MI -> isBundle ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI ; unsigned IgnoreCount = 0 ; for ( ++ MII ; MII != MBB -> end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) { if ( MII -> getOpcode ( ) == TargetOpcode :: DBG_VALUE || MII -> getOpcode ( ) == TargetOpcode :: IMPLICIT_DEF ) ++ IgnoreCount ; else { HexagonLowerToMC ( MII , MCB , * this ) ; } } } else { HexagonLowerToMC ( MI , MCB , * this ) ; HexagonMCInstrInfo :: padEndloop ( MCB ) ; } HexagonMCInstrInfo :: tryCompound ( * Subtarget -> getInstrInfo ( ) , OutStreamer -> getContext ( ) , MCB ) ; SmallVector < DuplexCandidate , 8 > possibleDuplexes ; possibleDuplexes = HexagonMCInstrInfo :: getDuplexPossibilties ( * Subtarget -> getInstrInfo ( ) , MCB ) ; HexagonMCShuffle ( * Subtarget -> getInstrInfo ( ) , * Subtarget , OutStreamer -> getContext ( ) , MCB , possibleDuplexes ) ; EmitToStreamer ( * OutStreamer , MCB ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .

Hexagon Hexagon Hexagon::BUNDLE 0 0 Hexagon Hexagon Hexagon Hexagon 8 Hexagon Hexagon


<s> bool aarch64_madd_needs_nop ( rtx_insn * insn ) { enum attr_type attr_type ; rtx_insn * prev ; rtx body ; if ( ! TARGET_FIX_ERR_A53_835769 ) return false ; if ( ! INSN_P ( insn ) || recog_memoized ( insn ) < 0 ) return false ; attr_type = get_attr_type ( insn ) ; if ( ! is_madd_op ( attr_type ) ) return false ; prev = aarch64_prev_real_insn ( insn ) ; extract_constrain_insn_cached ( insn ) ; if ( ! prev || ! contains_mem_rtx_p ( PATTERN ( prev ) ) ) return false ; body = single_set ( prev ) ; if ( GET_MODE ( recog_data . operand [ 0 ] ) == DImode && ( ! body || ! dep_between_memop_and_curr ( body ) ) ) return true ; return false ; } </s>

When working around the Cortex-A53 erratum 835769 , given rtx_insn INSN , return true if it is a 64-bit multiply-accumulate instruction and has a preceding memory instruction such that a NOP should be inserted between them .


<s> X86TargetLowering :: ConstraintType X86TargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'R' : case 'q' : case 'Q' : case 'f' : case 't' : case 'u' : case 'y' : case 'x' : case 'Y' : return C_RegisterClass ; case 'a' : case 'b' : case 'c' : case 'd' : case 'S' : case 'D' : case 'A' : return C_Register ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'G' : case 'C' : case 'e' : case 'Z' : return C_Other ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> unsigned MipsSEInstrInfo :: loadImmediate ( int64_t Imm , MachineBasicBlock & MBB , MachineBasicBlock :: iterator II , DebugLoc DL , unsigned * NewImm ) const { MipsAnalyzeImmediate AnalyzeImm ; const MipsSubtarget & STI = TM . getSubtarget < MipsSubtarget > ( ) ; unsigned Size = STI . isABI_N64 ( ) ? 64 : 32 ; unsigned LUi = STI . isABI_N64 ( ) ? Mips :: LUi64 : Mips :: LUi ; unsigned ZEROReg = STI . isABI_N64 ( ) ? Mips :: ZERO_64 : Mips :: ZERO ; unsigned ATReg = STI . isABI_N64 ( ) ? Mips :: AT_64 : Mips :: AT ; bool LastInstrIsADDiu = NewImm ; const MipsAnalyzeImmediate :: InstSeq & Seq = AnalyzeImm . Analyze ( Imm , Size , LastInstrIsADDiu ) ; MipsAnalyzeImmediate :: InstSeq :: const_iterator Inst = Seq . begin ( ) ; assert ( Seq . size ( ) && ( ! LastInstrIsADDiu || ( Seq . size ( ) > 1 ) ) ) ; if ( Inst -> Opc == LUi ) BuildMI ( MBB , II , DL , get ( LUi ) , ATReg ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; else BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , ATReg ) . addReg ( ZEROReg ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; for ( ++ Inst ; Inst != Seq . end ( ) - LastInstrIsADDiu ; ++ Inst ) BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , ATReg ) . addReg ( ATReg ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; if ( LastInstrIsADDiu ) * NewImm = Inst -> ImmOpnd ; return ATReg ; } </s>

Emit a series of instructions to load an immediate .


<s> bool AMDGPUAsmPrinter :: doFinalization ( Module & M ) { CallGraphResourceInfo . clear ( ) ; const MCSubtargetInfo & STI = * getGlobalSTI ( ) ; if ( AMDGPU :: isGFX10 ( STI ) && ( STI . getTargetTriple ( ) . getOS ( ) == Triple :: AMDHSA || STI . getTargetTriple ( ) . getOS ( ) == Triple :: AMDPAL ) ) { OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; getTargetStreamer ( ) -> EmitCodeEnd ( ) ; } return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> std :: vector < std :: pair < uint64_t , uint64_t >> X86MCInstrAnalysis :: findPltEntries ( uint64_t PltSectionVA , ArrayRef < uint8_t > PltContents , uint64_t GotPltSectionVA , const Triple & TargetTriple ) const { switch ( TargetTriple . getArch ( ) ) { case Triple :: x86 : return findX86PltEntries ( PltSectionVA , PltContents , GotPltSectionVA ) ; case Triple :: x86_64 : return findX86_64PltEntries ( PltSectionVA , PltContents ) ; default : return { } ; } } </s>

Returns ( PLT virtual address , GOT virtual address ) pairs for PLT entries .


<s> static pad_direction arm_function_arg_padding ( machine_mode mode , const_tree type ) { if ( ! TARGET_AAPCS_BASED ) return default_function_arg_padding ( mode , type ) ; if ( type && BYTES_BIG_ENDIAN && INTEGRAL_TYPE_P ( type ) ) return PAD_DOWNWARD ; return PAD_UPWARD ; } </s>

Implement TARGET_FUNCTION_ARG_PADDING ; return PAD_UPWARD if the lowest byte of a stack argument has useful data . For legacy APCS ABIs we use the default . For AAPCS based ABIs small aggregate types are placed in the lowest memory address .


<s> static rtx v850_all_frame_related ( rtx par ) { int len = XVECLEN ( par , 0 ) ; int i ; gcc_assert ( GET_CODE ( par ) == PARALLEL ) ; for ( i = 0 ; i < len ; i ++ ) F ( XVECEXP ( par , 0 , i ) ) ; return par ; } </s>

Mark all the subexpressions of the PARALLEL rtx PAR as frame-related . Return PAR . dwarf2out.cc : dwarf2out_frame_debug_expr ignores sub-expressions of a PARALLEL rtx other than the first if they do not have the FRAME_RELATED flag set on them .


<s> bool MSP430PassConfig :: addInstSelector ( ) { PM -> add ( createMSP430ISelDag ( getMSP430TargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool AArch64CallLowering :: lowerCall ( MachineIRBuilder & MIRBuilder , const CallInst & CI , unsigned CalleeReg , unsigned ResReg , ArrayRef < unsigned > ArgRegs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = * MF . getFunction ( ) ; SmallVector < MVT , 8 > ArgTys ; for ( auto & Arg : CI . arg_operands ( ) ) ArgTys . push_back ( MVT :: getVT ( Arg -> getType ( ) ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * CallAssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; SmallVector < unsigned , 8 > PhysRegs ; handleAssignments ( MIRBuilder , CallAssignFn , ArgTys , ArgRegs , [ & ] ( MachineIRBuilder & MIRBuilder , unsigned ValReg , unsigned PhysReg ) { MIRBuilder . buildCopy ( PhysReg , ValReg ) ; PhysRegs . push_back ( PhysReg ) ; } ) ; MachineInstrBuilder MIB ; if ( CalleeReg ) MIB = MIRBuilder . buildInstr ( AArch64 :: BLR ) . addUse ( CalleeReg ) ; else MIB = MIRBuilder . buildInstr ( AArch64 :: BL ) . addGlobalAddress ( CI . getCalledFunction ( ) ) ; auto TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , F . getCallingConv ( ) ) ) ; for ( auto Reg : PhysRegs ) MIB . addUse ( Reg , RegState :: Implicit ) ; CCAssignFn * RetAssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) ) ; if ( ! CI . getType ( ) -> isVoidTy ( ) ) handleAssignments ( MIRBuilder , RetAssignFn , MVT :: getVT ( CI . getType ( ) ) , ResReg , [ & ] ( MachineIRBuilder & MIRBuilder , unsigned ValReg , unsigned PhysReg ) { MIRBuilder . buildCopy ( ValReg , PhysReg ) ; MIB . addDef ( PhysReg , RegState :: Implicit ) ; } ) ; return true ; } </s>

This hook must be implemented to lower the given call instruction , including argument and return value marshalling .


<s> bool ARMOptimizeBarriersPass :: runOnMachineFunction ( MachineFunction & MF ) { std :: vector < MachineInstr * > ToRemove ; int64_t DMBType = - 1 ; for ( auto & MBB : MF ) { bool IsRemovableNextDMB = false ; for ( auto & MI : MBB ) { if ( MI . getOpcode ( ) == ARM :: DMB ) { if ( IsRemovableNextDMB ) { if ( MI . getOperand ( 0 ) . getImm ( ) == DMBType ) { ToRemove . push_back ( & MI ) ; } else { DMBType = MI . getOperand ( 0 ) . getImm ( ) ; } } else { IsRemovableNextDMB = true ; DMBType = MI . getOperand ( 0 ) . getImm ( ) ; } } else if ( ! CanMovePastDMB ( & MI ) ) { IsRemovableNextDMB = false ; } } } for ( auto MI : ToRemove ) { MI -> eraseFromParent ( ) ; ++ NumDMBsRemoved ; } return NumDMBsRemoved > 0 ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool visitInstruction ( Instruction & ) { return false ; } </s>

Specify what to return for unhandled instructions .


<s>
SDValue
ARCTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCallArguments
(
Chain
,
CallConv
,
IsVarArg
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .

ARC
ARC
ISD::InputArg
"Unsupported calling convention"


"internal compiler error.  Incorrect shift:"


<s> SDValue PPCTargetLowering :: getSqrtEstimate ( SDValue Operand , SelectionDAG & DAG , int Enabled , int & RefinementSteps , bool & UseOneConstNR , bool Reciprocal ) const { EVT VT = Operand . getValueType ( ) ; if ( ( VT == MVT :: f32 && Subtarget . hasFRSQRTES ( ) ) || ( VT == MVT :: f64 && Subtarget . hasFRSQRTE ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasAltivec ( ) ) || ( VT == MVT :: v2f64 && Subtarget . hasVSX ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasQPX ( ) ) || ( VT == MVT :: v4f64 && Subtarget . hasQPX ( ) ) ) { if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = getEstimateRefinementSteps ( VT , Subtarget ) ; UseOneConstNR = true ; return DAG . getNode ( PPCISD :: FRSQRTE , SDLoc ( Operand ) , VT , Operand ) ; } return SDValue ( ) ; } </s>

Hooks for building estimates in place of slower divisions and square roots .


<s> bool rs6000_function_pcrel_p ( struct function * fn ) { if ( DEFAULT_ABI != ABI_ELFv2 ) return false ; if ( fn == cfun ) return ( ( rs6000_isa_flags & OPTION_MASK_PCREL ) != 0 && TARGET_CMODEL == CMODEL_MEDIUM ) ; return rs6000_fndecl_pcrel_p ( fn -> decl ) ; } </s>

Return whether we should generate PC-relative code for * FN .


<s> bool SIFixWWMLiveness :: runOnMachineFunction ( MachineFunction & MF ) { bool Modified = false ; LIS = getAnalysisIfAvailable < LiveIntervals > ( ) ; const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; const SIInstrInfo * TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) { if ( MI . getOpcode ( ) == AMDGPU :: EXIT_WWM ) { Modified |= runOnWWMInstruction ( MI ) ; } } } return Modified ; } </s>


<s> static bool classof ( const MCStreamer * S ) { return S -> getKind ( ) == SK_MipsELFStreamer ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> unsigned PatmosSubtarget :: getIssueWidth ( unsigned SchedClass ) const { return InstrItins . getNumMicroOps ( SchedClass ) ; } </s>

Maximum number of micro-ops that may be scheduled per cycle .


<s>
void
AMDGPUArgumentUsageInfo
::
print
(
raw_ostream
&
OS
,
const
Module
*
M
)
const
{
for
(
const
auto
&
FI
:
ArgInfoMap
)
{
OS
<<
"Arguments for "
<<
FI
.
first
->
getName
(
)
<<
'\n'
<<
"  PrivateSegmentBuffer: "
<<
FI
.
second
.
PrivateSegmentBuffer
<<
"  DispatchPtr: "
<<
FI
.
second
.
DispatchPtr
<<
"  QueuePtr: "
<<
FI
.
second
.
QueuePtr
<<
"  KernargSegmentPtr: "
<<
FI
.
second
.
KernargSegmentPtr
<<
"  DispatchID: "
<<
FI
.
second
.
DispatchID
<<
"  FlatScratchInit: "
<<
FI
.
second
.
FlatScratchInit
<<
"  PrivateSegmentSize: "
<<
FI
.
second
.
PrivateSegmentSize
<<
"  WorkGroupIDX: "
<<
FI
.
second
.
WorkGroupIDX
<<
"  WorkGroupIDY: "
<<
FI
.
second
.
WorkGroupIDY
<<
"  WorkGroupIDZ: "
<<
FI
.
second
.
WorkGroupIDZ
<<
"  WorkGroupInfo: "
<<
FI
.
second
.
WorkGroupInfo
<<
"  PrivateSegmentWaveByteOffset: "
<<
FI
.
second
.
PrivateSegmentWaveByteOffset
<<
"  ImplicitBufferPtr: "
<<
FI
.
second
.
ImplicitBufferPtr
<<
"  ImplicitArgPtr: "
<<
FI
.
second
.
ImplicitArgPtr
<<
"  WorkItemIDX "
<<
FI
.
second
.
WorkItemIDX
<<
"  WorkItemIDY "
<<
FI
.
second
.
WorkItemIDY
<<
"  WorkItemIDZ "
<<
FI
.
second
.
WorkItemIDZ
<<
'\n'
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

AMDGPU
AMDGPU
"Arguments for "
"  PrivateSegmentBuffer: "
"  DispatchPtr: "
"  QueuePtr: "
"  KernargSegmentPtr: "
"  DispatchID: "
"  FlatScratchInit: "
"  PrivateSegmentSize: "
"  WorkGroupIDX: "
"  WorkGroupIDY: "
"  WorkGroupIDZ: "
"  WorkGroupInfo: "
"  PrivateSegmentWaveByteOffset: "
"  ImplicitBufferPtr: "
"  ImplicitArgPtr: "
"  WorkItemIDX "
"  WorkItemIDY "
"  WorkItemIDZ "


<s>
void
tilepro_function_profiler
(
FILE
*
file
,
int
labelno
ATTRIBUTE_UNUSED
)
{
if
(
tilepro_in_bundle
)
{
fprintf
(
file
,
"\t}\n"
)
;
}
if
(
flag_pic
)
{
fprintf
(
file
,
"\t{\n"
"\tmove\tr10, lr\n"
"\tjal\tplt(%s)\n"
"\t}\n"
,
MCOUNT_NAME
)
;
}
else
{
fprintf
(
file
,
"\t{\n"
"\tmove\tr10, lr\n"
"\tjal\t%s\n"
"\t}\n"
,
MCOUNT_NAME
)
;
}
tilepro_in_bundle
=
false
;
}
</s>

Output assembler code to FILE to increment profiler label # LABELNO for profiling a function entry .


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override { return false ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> SDValue AVRTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; auto CCFunction = CCAssignFnForReturn ( CallConv ) ; CCInfo . AnalyzeCallResult ( Ins , CCFunction ) ; if ( CallConv != CallingConv :: AVR_BUILTIN && RVLocs . size ( ) > 1 ) { std :: reverse ( RVLocs . begin ( ) , RVLocs . end ( ) ) ; } for ( CCValAssign const & RVLoc : RVLocs ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLoc . getLocReg ( ) , RVLoc . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static tree ix86_builtin_tm_load ( tree type ) { if ( TREE_CODE ( type ) == VECTOR_TYPE ) { switch ( tree_to_uhwi ( TYPE_SIZE ( type ) ) ) { case 64 : return builtin_decl_explicit ( BUILT_IN_TM_LOAD_M64 ) ; case 128 : return builtin_decl_explicit ( BUILT_IN_TM_LOAD_M128 ) ; case 256 : return builtin_decl_explicit ( BUILT_IN_TM_LOAD_M256 ) ; } } return NULL_TREE ; } </s>

Return the builtin decl needed to load a vector of TYPE .


<s>
static
void
consume_whitespace
(
void
)
{
while
(
pos
<
LINELEN
&&
isspace
(
linebuf
[
pos
]
)
&&
linebuf
[
pos
]
!=
'\n'
)
pos
++
;
if
(
pos
>=
LINELEN
)
{
diag
(
pos
,
"line length overrun.\n"
)
;
exit
(
1
)
;
}
return
;
}
</s>

Pass over whitespace ( other than a newline , which terminates the scan ) .


<s>
static
void
copy_fp_args
(
rtx_insn
*
insn
)
{
rtx
link
;
rtx
xoperands
[
2
]
;
for
(
link
=
CALL_INSN_FUNCTION_USAGE
(
insn
)
;
link
;
link
=
XEXP
(
link
,
1
)
)
{
int
arg_mode
,
regno
;
rtx
use
=
XEXP
(
link
,
0
)
;
if
(
!
(
GET_CODE
(
use
)
==
USE
&&
GET_CODE
(
XEXP
(
use
,
0
)
)
==
REG
&&
FUNCTION_ARG_REGNO_P
(
REGNO
(
XEXP
(
use
,
0
)
)
)
)
)
continue
;
arg_mode
=
GET_MODE
(
XEXP
(
use
,
0
)
)
;
regno
=
REGNO
(
XEXP
(
use
,
0
)
)
;
if
(
regno
>=
32
&&
regno
<=
39
)
{
if
(
arg_mode
==
SFmode
)
{
xoperands
[
0
]
=
XEXP
(
use
,
0
)
;
xoperands
[
1
]
=
gen_rtx_REG
(
SImode
,
26
(
regno
32
)
/
2
)
;
output_asm_insn
(
"{fstws|fstw} %0,-16(%%sr0,%%r30)"
,
xoperands
)
;
output_asm_insn
(
"ldw -16(%%sr0,%%r30),%1"
,
xoperands
)
;
}
else
{
xoperands
[
0
]
=
XEXP
(
use
,
0
)
;
xoperands
[
1
]
=
gen_rtx_REG
(
DImode
,
25
(
regno
34
)
/
2
)
;
output_asm_insn
(
"{fstds|fstd} %0,-16(%%sr0,%%r30)"
,
xoperands
)
;
output_asm_insn
(
"ldw -12(%%sr0,%%r30),%R1"
,
xoperands
)
;
output_asm_insn
(
"ldw -16(%%sr0,%%r30),%1"
,
xoperands
)
;
}
}
}
}
</s>

Copy any FP arguments in INSN into integer registers .


<s>
bool
ThumbDisassembler
::
getInstruction
(
MCInst
&
MI
,
uint64_t
&
Size
,
const
MemoryObject
&
Region
,
uint64_t
Address
,
raw_ostream
&
os
)
const
{
unsigned
insn
=
0
;
uint16_t
insn1
=
0
;
uint8_t
bytes
[
2
]
;
if
(
Region
.
readBytes
(
Address
,
2
,
(
uint8_t
*
)
bytes
,
)
==
1
)
return
false
;
insn
=
(
bytes
[
1
]
<<
8
)
|
bytes
[
0
]
;
unsigned
bits15_11
=
slice
(
insn
,
15
,
11
)
;
bool
IsThumb2
=
false
;
if
(
bits15_11
==
0x1D
||
bits15_11
==
0x1E
||
bits15_11
==
0x1F
)
{
IsThumb2
=
true
;
if
(
Region
.
readBytes
(
Address
+
2
,
2
,
(
uint8_t
*
)
bytes
,
)
==
1
)
return
false
;
insn1
=
(
bytes
[
1
]
<<
8
)
|
bytes
[
0
]
;
insn
=
(
insn
<<
16
|
insn1
)
;
}
unsigned
Opcode
=
decodeThumbSideEffect
(
IsThumb2
,
insn
)
;
ARMFormat
Format
=
ARMFormats
[
Opcode
]
;
Size
=
IsThumb2
4
:
2
;
DEBUG
(
{
errs
(
)
<<
"Opcode="
<<
Opcode
<<
" Name="
<<
ARMUtils
::
OpcodeName
(
Opcode
)
<<
" Format="
<<
stringForARMFormat
(
Format
)
<<
'('
<<
(
int
)
Format
<<
")\n"
;
showBitVector
(
errs
(
)
,
insn
)
;
}
)
;
ARMBasicMCBuilder
*
Builder
=
CreateMCBuilder
(
Opcode
,
Format
)
;
if
(
!
Builder
)
return
false
;
Builder
->
SetSession
(
const_cast
<
Session
*
>
(
&
SO
)
)
;
if
(
!
Builder
->
Build
(
MI
,
insn
)
)
return
false
;
delete
Builder
;
return
true
;
}
</s>

Returns the disassembly of a single instruction .


<s> static HOST_WIDE_INT sparc_constant_alignment ( const_tree exp , HOST_WIDE_INT align ) { if ( TREE_CODE ( exp ) == STRING_CST ) return MAX ( align , FASTEST_ALIGNMENT ) ; return align ; } </s>


<s>
bool
R600VectorRegMerger
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
if
(
skipFunction
(
Fn
.
getFunction
(
)
)
)
return
false
;
const
R600Subtarget
&
ST
=
Fn
.
getSubtarget
<
R600Subtarget
>
(
)
;
TII
=
ST
.
getInstrInfo
(
)
;
MRI
=
&
Fn
.
getRegInfo
(
)
;
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
MachineBasicBlock
*
MB
=
&
*
MBB
;
PreviousRegSeq
.
clear
(
)
;
PreviousRegSeqByReg
.
clear
(
)
;
PreviousRegSeqByUndefCount
.
clear
(
)
;
for
(
MachineBasicBlock
::
iterator
MII
=
MB
->
begin
(
)
,
MIIE
=
MB
->
end
(
)
;
MII
!=
MIIE
;
++
MII
)
{
MachineInstr
&
MI
=
*
MII
;
if
(
MI
.
getOpcode
(
)
!=
R600
::
REG_SEQUENCE
)
{
if
(
TII
->
get
(
MI
.
getOpcode
(
)
)
.
TSFlags
&
R600_InstFlag
::
TEX_INST
)
{
Register
Reg
=
MI
.
getOperand
(
1
)
.
getReg
(
)
;
for
(
MachineRegisterInfo
::
def_instr_iterator
It
=
MRI
->
def_instr_begin
(
Reg
)
,
E
=
MRI
->
def_instr_end
(
)
;
It
!=
E
;
++
It
)
{
RemoveMI
(
&
(
*
It
)
)
;
}
}
continue
;
}
RegSeqInfo
RSI
(
*
MRI
,
&
MI
)
;
Register
Reg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
if
(
!
areAllUsesSwizzeable
(
Reg
)
)
continue
;
LLVM_DEBUG
(
{
dbgs
(
)
<<
"Trying to optimize "
;
MI
.
dump
(
)
;
}
)
;
RegSeqInfo
CandidateRSI
;
std
::
vector
<
std
::
pair
<
unsigned
,
unsigned
>>
RemapChan
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Using common slots...\n"
;
)
;
if
(
tryMergeUsingCommonSlot
(
RSI
,
CandidateRSI
,
RemapChan
)
)
{
RemoveMI
(
CandidateRSI
.
Instr
)
;
MII
=
RebuildVector
(
&
RSI
,
&
CandidateRSI
,
RemapChan
)
;
trackRSI
(
RSI
)
;
continue
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Using free slots...\n"
;
)
;
RemapChan
.
clear
(
)
;
if
(
tryMergeUsingFreeSlot
(
RSI
,
CandidateRSI
,
RemapChan
)
)
{
RemoveMI
(
CandidateRSI
.
Instr
)
;
MII
=
RebuildVector
(
&
RSI
,
&
CandidateRSI
,
RemapChan
)
;
trackRSI
(
RSI
)
;
continue
;
}
trackRSI
(
RSI
)
;
}
}
</s>

AMDGPU
R600
R600
R600
R600::REG_SEQUENCE
R600_InstFlag::TEX_INST
1
SI
0
"Trying to optimize "
SI
"Using common slots...\n"
SI
SI
SI
SI
SI
SI
SI
"Using free slots...\n"
SI
SI
SI
SI
SI
SI
SI
SI
SI


<s>
bool
ARMBaseInstrInfo
::
getExtractSubregLikeInputs
(
const
MachineInstr
&
MI
,
unsigned
DefIdx
,
RegSubRegPairAndIdx
&
InputReg
)
const
{
assert
(
DefIdx
<
MI
.
getDesc
(
)
.
getNumDefs
(
)
&&
"Invalid definition index"
)
;
assert
(
MI
.
isExtractSubregLike
(
)
&&
"Invalid kind of instruction"
)
;
switch
(
MI
.
getOpcode
(
)
)
{
case
ARM
::
VMOVRRD
:
const
MachineOperand
&
MOReg
=
MI
.
getOperand
(
2
)
;
InputReg
.
Reg
=
MOReg
.
getReg
(
)
;
InputReg
.
SubReg
=
MOReg
.
getSubReg
(
)
;
InputReg
.
SubIdx
=
DefIdx
==
0
ARM
::
ssub_0
:
ARM
::
ssub_1
;
return
true
;
}
llvm_unreachable
(
"Target dependent opcode missing"
)
;
}
</s>

Target-dependent implementation of getExtractSubregInputs .


<s> static void rs6000_emit_move_from_cr ( rtx reg ) { if ( DEFAULT_ABI == ABI_ELFv2 && TARGET_MFCRF ) { int i , cr_reg [ 8 ] , count = 0 ; for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) cr_reg [ count ++ ] = i ; if ( count == 1 ) { rtvec p = rtvec_alloc ( 1 ) ; rtvec r = rtvec_alloc ( 2 ) ; RTVEC_ELT ( r , 0 ) = gen_rtx_REG ( CCmode , CR0_REGNO + cr_reg [ 0 ] ) ; RTVEC_ELT ( r , 1 ) = GEN_INT ( 1 << ( 7 - cr_reg [ 0 ] ) ) ; RTVEC_ELT ( p , 0 ) = gen_rtx_SET ( reg , gen_rtx_UNSPEC ( SImode , r , UNSPEC_MOVESI_FROM_CR ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , p ) ) ; return ; } } emit_insn ( gen_movesi_from_cr ( reg ) ) ; } </s>

Emit code to store CR fields that need to be saved into REG .


<s> bool aarch64_emit_approx_sqrt ( rtx dst , rtx src , bool recp ) { machine_mode mode = GET_MODE ( dst ) ; if ( GET_MODE_INNER ( mode ) == HFmode ) { gcc_assert ( ! recp ) ; return false ; } machine_mode mmsk = mode_for_vector ( int_mode_for_mode ( GET_MODE_INNER ( mode ) ) , GET_MODE_NUNITS ( mode ) ) ; if ( ! recp ) { if ( ! ( flag_mlow_precision_sqrt || ( aarch64_tune_params . approx_modes -> sqrt & AARCH64_APPROX_MODE ( mode ) ) ) ) return false ; if ( flag_finite_math_only || flag_trapping_math || ! flag_unsafe_math_optimizations || optimize_function_for_size_p ( cfun ) ) return false ; } else gcc_assert ( use_rsqrt_p ( mode ) ) ; rtx xmsk = gen_reg_rtx ( mmsk ) ; if ( ! recp ) emit_insn ( gen_rtx_SET ( xmsk , gen_rtx_NEG ( mmsk , gen_rtx_EQ ( mmsk , src , CONST0_RTX ( mode ) ) ) ) ) ; rtx xdst = gen_reg_rtx ( mode ) ; emit_insn ( ( * get_rsqrte_type ( mode ) ) ( xdst , src ) ) ; int iterations = ( GET_MODE_INNER ( mode ) == DFmode ) ? 3 : 2 ; if ( ( recp && flag_mrecip_low_precision_sqrt ) || ( ! recp && flag_mlow_precision_sqrt ) ) iterations -- ; rtx x1 = gen_reg_rtx ( mode ) ; while ( iterations -- ) { rtx x2 = gen_reg_rtx ( mode ) ; emit_set_insn ( x2 , gen_rtx_MULT ( mode , xdst , xdst ) ) ; emit_insn ( ( * get_rsqrts_type ( mode ) ) ( x1 , src , x2 ) ) ; if ( iterations > 0 ) emit_set_insn ( xdst , gen_rtx_MULT ( mode , xdst , x1 ) ) ; } if ( ! recp ) { rtx xtmp = gen_reg_rtx ( mmsk ) ; emit_set_insn ( xtmp , gen_rtx_AND ( mmsk , gen_rtx_NOT ( mmsk , xmsk ) , gen_rtx_SUBREG ( mmsk , xdst , 0 ) ) ) ; emit_move_insn ( xdst , gen_rtx_SUBREG ( mode , xtmp , 0 ) ) ; emit_set_insn ( xdst , gen_rtx_MULT ( mode , xdst , src ) ) ; } emit_set_insn ( dst , gen_rtx_MULT ( mode , xdst , x1 ) ) ; return true ; } </s>

Emit instruction sequence to compute either the approximate square root or its approximate reciprocal , depending on the flag RECP , and return whether the sequence was emitted or not .


<s>
void
Thumb1InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
&
ARM
::
tGPRRegClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
&
ARM
::
tGPRRegClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
FI
)
,
MachineMemOperand
::
MOStore
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tSTRspi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .

ARM
ARM::tGPRRegClass
ARM
"Unknown regclass!"
ARM::tGPRRegClass
ARM
ARM::tSTRspi
0


"calling %qD with SSE calling convention without "

"this is a GCC bug that can be worked around by adding "

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . ) Return a number of integer regsiters advanced over .


<s> bool CSKYAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < CSKYSubtarget > ( ) ; return AsmPrinter :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s>
void
WebAssemblyInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
auto
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
const
TargetRegisterClass
*
RC
=
TargetRegisterInfo
::
isVirtualRegister
(
DestReg
)
MRI
.
getRegClass
(
DestReg
)
:
MRI
.
getTargetRegisterInfo
(
)
->
getMinimalPhysRegClass
(
DestReg
)
;
unsigned
CopyLocalOpcode
;
if
(
RC
==
&
WebAssembly
::
I32RegClass
)
CopyLocalOpcode
=
WebAssembly
::
COPY_LOCAL_I32
;
else
if
(
RC
==
&
WebAssembly
::
I64RegClass
)
CopyLocalOpcode
=
WebAssembly
::
COPY_LOCAL_I64
;
else
if
(
RC
==
&
WebAssembly
::
F32RegClass
)
CopyLocalOpcode
=
WebAssembly
::
COPY_LOCAL_F32
;
else
if
(
RC
==
&
WebAssembly
::
F64RegClass
)
CopyLocalOpcode
=
WebAssembly
::
COPY_LOCAL_F64
;
else
llvm_unreachable
(
"Unexpected register class"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
CopyLocalOpcode
)
,
DestReg
)
.
addReg
(
SrcReg
,
KillSrc
RegState
::
Kill
:
0
)
;
}
</s>


<s> bool AArch64AsmParser :: ParseDirective ( AsmToken DirectiveID ) { const MCObjectFileInfo :: Environment Format = getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ; bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; StringRef IDVal = DirectiveID . getIdentifier ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == ".arch" ) parseDirectiveArch ( Loc ) ; else if ( IDVal == ".cpu" ) parseDirectiveCPU ( Loc ) ; else if ( IDVal == ".tlsdesccall" ) parseDirectiveTLSDescCall ( Loc ) ; else if ( IDVal == ".ltorg" || IDVal == ".pool" ) parseDirectiveLtorg ( Loc ) ; else if ( IDVal == ".unreq" ) parseDirectiveUnreq ( Loc ) ; else if ( IDVal == ".inst" ) parseDirectiveInst ( Loc ) ; else if ( IDVal == ".cfi_negate_ra_state" ) parseDirectiveCFINegateRAState ( ) ; else if ( IDVal == ".cfi_b_key_frame" ) parseDirectiveCFIBKeyFrame ( ) ; else if ( IsMachO ) { if ( IDVal == MCLOHDirectiveName ( ) ) parseDirectiveLOH ( IDVal , Loc ) ; else return true ; } else return true ; return false ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> RCPair ARMTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: tGPRRegClass ) ; return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'h' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: hGPRRegClass ) ; break ; case 'r' : return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'w' : if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPRRegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPRRegClass ) ; break ; case 'x' : if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPR_8RegClass ) ; break ; case 't' : if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( ARM :: CPSR ) , & ARM :: CCRRegClass ) ; return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> void AArch64PassConfig :: addPreSched2 ( ) { addPass ( createAArch64ExpandPseudoPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoadStoreOpt ) addPass ( createAArch64LoadStoreOptimizationPass ( ) ) ; } addPass ( createAArch64SpeculationHardeningPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableFalkorHWPFFix ) addPass ( createFalkorHWPFFixPass ( ) ) ; } } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> static bool aarch64_base_register_rtx_p ( rtx x , bool strict_p ) { if ( ! strict_p && GET_CODE ( x ) == SUBREG && contains_reg_of_mode [ GENERAL_REGS ] [ GET_MODE ( SUBREG_REG ( x ) ) ] ) x = SUBREG_REG ( x ) ; return ( REG_P ( x ) && aarch64_regno_ok_for_base_p ( REGNO ( x ) , strict_p ) ) ; } </s>

Return true if X is a valid base register for mode MODE . STRICT_P is true if REG_OK_STRICT is in effect .


<s> bool Mips16RegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { DebugLoc DL ; TII . copyPhysReg ( MBB , I , DL , Mips :: T0 , Reg , true ) ; TII . copyPhysReg ( MBB , UseMI , DL , Reg , Mips :: T0 , true ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .


<s> ScheduleHazardRecognizer * PPCInstrInfo :: CreateTargetHazardRecognizer ( const TargetSubtargetInfo * STI , const ScheduleDAG * DAG ) const { unsigned Directive = static_cast < const PPCSubtarget * > ( STI ) -> getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_440 || Directive == PPC :: DIR_A2 || Directive == PPC :: DIR_E500mc || Directive == PPC :: DIR_E5500 ) { const InstrItineraryData * II = & static_cast < const PPCSubtarget * > ( STI ) -> getInstrItineraryData ( ) ; return new ScoreboardHazardRecognizer ( II , DAG ) ; } return TargetInstrInfo :: CreateTargetHazardRecognizer ( STI , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .


"malformed %<target()%> pragma or attribute"

"pragma or attribute %<target(\"%s\")%> does not accept an argument"

"pragma or attribute %<target(\"%s\")%> does not allow a negated form"

"pragma or attribute %<target(\"%s=%s\")%> is not valid"

Parse ARG_STR which contains the definition of one target attribute . Show appropriate errors if any or return true if the attribute is valid . PRAGMA_OR_ATTR holds the string to use in error messages about whether we 're processing a target attribute or pragma .


<s> bool isIncomingArgumentHandler ( ) const override { return false ; } </s>

Returns true if the handler is dealing with incoming arguments , i.e .


<s> static bool bpf_legitimate_address_p ( machine_mode mode , rtx x , bool strict ) { switch ( GET_CODE ( x ) ) { case CONST_INT : return ( mode == FUNCTION_MODE ) ; case REG : return bpf_address_base_p ( x , strict ) ; case PLUS : { rtx x0 = XEXP ( x , 0 ) ; rtx x1 = XEXP ( x , 1 ) ; if ( bpf_address_base_p ( x0 , strict ) && GET_CODE ( x1 ) == CONST_INT ) return IN_RANGE ( INTVAL ( x1 ) , - 1 - 0x7fff , 0x7fff ) ; break ; } default : break ; } return false ; } </s>

Return true if X ( a RTX ) is a legitimate memory address on the target machine for a memory operand of mode MODE .


"Unrecognized Hexagon processor version"

"Behavior is undefined for simultaneous qfloat and ieee hvx codegen..."

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool AMDGPUAnnotateUniformValues :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; DA = & getAnalysis < LegacyDivergenceAnalysis > ( ) ; MDR = & getAnalysis < MemoryDependenceWrapperPass > ( ) . getMemDep ( ) ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; isKernelFunc = F . getCallingConv ( ) == CallingConv :: AMDGPU_KERNEL ; visit ( F ) ; noClobberClones . clear ( ) ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { if ( Inst . getNumOperands ( ) == 0 || ! Inst . getOperand ( 0 ) . isImm ( ) || Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ 0 ] . OperandType != MCOI :: OPERAND_PCREL ) return false ; int64_t Imm = Inst . getOperand ( 0 ) . getImm ( ) ; APInt SignedOffset ( 18 , Imm * 4 , true ) ; Target = ( SignedOffset . sext ( 64 ) + Addr + Size ) . getZExtValue ( ) ; return true ; } </s>

Given a branch instruction try to get the address the branch targets .


<s> MachineInstr * ARMBaseInstrInfo :: commuteInstruction ( MachineInstr * MI , bool NewMI ) const { switch ( MI -> getOpcode ( ) ) { case ARM :: MOVCCr : case ARM :: t2MOVCCr : { unsigned PredReg = 0 ; ARMCC :: CondCodes CC = getInstrPredicate ( MI , PredReg ) ; if ( CC == ARMCC :: AL || PredReg != ARM :: CPSR ) return NULL ; MI = TargetInstrInfo :: commuteInstruction ( MI , NewMI ) ; if ( ! MI ) return NULL ; MI -> getOperand ( MI -> findFirstPredOperandIdx ( ) ) . setImm ( ARMCC :: getOppositeCondition ( CC ) ) ; return MI ; } } return TargetInstrInfo :: commuteInstruction ( MI , NewMI ) ; } </s>

This method commutes the operands of the given machine instruction MI .

ARM ARM ARM::MOVCCr ARM::t2MOVCCr 0 ARMCC::CondCodes ARMCC::AL ARM::CPSR ARMCC::getOppositeCondition


<s> bool ARMInstrInfo :: PredicateInstruction ( MachineInstr * MI , const SmallVectorImpl < MachineOperand > & Pred ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == ARM :: B || Opc == ARM :: tB ) { MI -> setDesc ( get ( Opc == ARM :: B ? ARM :: Bcc : ARM :: tBcc ) ) ; MI -> addOperand ( MachineOperand :: CreateImm ( Pred [ 0 ] . getImm ( ) ) ) ; MI -> addOperand ( MachineOperand :: CreateReg ( Pred [ 1 ] . getReg ( ) , false ) ) ; return true ; } int PIdx = MI -> findFirstPredOperandIdx ( ) ; if ( PIdx != - 1 ) { MachineOperand & PMO = MI -> getOperand ( PIdx ) ; PMO . setImm ( Pred [ 0 ] . getImm ( ) ) ; MI -> getOperand ( PIdx + 1 ) . setReg ( Pred [ 1 ] . getReg ( ) ) ; return true ; } return false ; } </s>

Convert the instruction into a predicated instruction .


<s> void i386_pe_declare_function_type ( FILE * file , const char * name , int public ) { fprintf ( file , "\t.def\t" ) ; assemble_name ( file , name ) ; fprintf ( file , ";\t.scl\t%d;\t.type\t%d;\t.endef\n" , public ? ( int ) C_EXT : ( int ) C_STAT , ( int ) DT_FCN << N_BTSHFT ) ; } </s>

Mark a function appropriately . This should only be called for functions for which we are not emitting COFF debugging information . FILE is the assembler output file , NAME is the name of the function , and PUBLIC is nonzero if the function is globally visible .


"passing %qT to argument %d of %qE, which"

" expects a single SVE vector rather than a tuple"

"passing single vector %qT to argument %d"

" of %qE, which expects a tuple of %d vectors"

Require argument ARGNO to be a single vector or a tuple of NUM_VECTORS vectors ; NUM_VECTORS is 1 for the former . Return the associated type suffix on success , using TYPE_SUFFIX_b for predicates . Report an error and return NUM_TYPE_SUFFIXES on failure .


<s> Optional < Instruction * > AArch64TTIImpl :: instCombineIntrinsic ( InstCombiner & IC , IntrinsicInst & II ) const { Intrinsic :: ID IID = II . getIntrinsicID ( ) ; switch ( IID ) { default : break ; case Intrinsic :: aarch64_sve_convert_from_svbool : return instCombineConvertFromSVBool ( IC , II ) ; case Intrinsic :: aarch64_sve_dup : return instCombineSVEDup ( IC , II ) ; case Intrinsic :: aarch64_sve_dup_x : return instCombineSVEDupX ( IC , II ) ; case Intrinsic :: aarch64_sve_cmpne : case Intrinsic :: aarch64_sve_cmpne_wide : return instCombineSVECmpNE ( IC , II ) ; case Intrinsic :: aarch64_sve_rdffr : return instCombineRDFFR ( IC , II ) ; case Intrinsic :: aarch64_sve_lasta : case Intrinsic :: aarch64_sve_lastb : return instCombineSVELast ( IC , II ) ; case Intrinsic :: aarch64_sve_cntd : return instCombineSVECntElts ( IC , II , 2 ) ; case Intrinsic :: aarch64_sve_cntw : return instCombineSVECntElts ( IC , II , 4 ) ; case Intrinsic :: aarch64_sve_cnth : return instCombineSVECntElts ( IC , II , 8 ) ; case Intrinsic :: aarch64_sve_cntb : return instCombineSVECntElts ( IC , II , 16 ) ; case Intrinsic :: aarch64_sve_ptest_any : case Intrinsic :: aarch64_sve_ptest_first : case Intrinsic :: aarch64_sve_ptest_last : return instCombineSVEPTest ( IC , II ) ; case Intrinsic :: aarch64_sve_mul : case Intrinsic :: aarch64_sve_fmul : return instCombineSVEVectorMul ( IC , II ) ; case Intrinsic :: aarch64_sve_fadd : case Intrinsic :: aarch64_sve_fsub : return instCombineSVEVectorBinOp ( IC , II ) ; case Intrinsic :: aarch64_sve_tbl : return instCombineSVETBL ( IC , II ) ; case Intrinsic :: aarch64_sve_uunpkhi : case Intrinsic :: aarch64_sve_uunpklo : case Intrinsic :: aarch64_sve_sunpkhi : case Intrinsic :: aarch64_sve_sunpklo : return instCombineSVEUnpack ( IC , II ) ; case Intrinsic :: aarch64_sve_tuple_get : return instCombineSVETupleGet ( IC , II ) ; case Intrinsic :: aarch64_sve_zip1 : case Intrinsic :: aarch64_sve_zip2 : return instCombineSVEZip ( IC , II ) ; } return None ; } </s>

Targets can implement their own combinations for target-specific intrinsics .


<s>
bool
HexagonExpandCondsets
::
split
(
MachineInstr
&
MI
,
std
::
set
<
unsigned
>
&
UpdRegs
)
{
if
(
TfrLimitActive
)
{
if
(
TfrCounter
>=
TfrLimit
)
return
false
;
TfrCounter
++
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"\nsplitting "
<<
printMBBReference
(
*
MI
.
getParent
(
)
)
<<
": "
<<
MI
)
;
MachineOperand
&
MD
=
MI
.
getOperand
(
0
)
;
MachineOperand
&
MP
=
MI
.
getOperand
(
1
)
;
assert
(
MD
.
isDef
(
)
)
;
Register
DR
=
MD
.
getReg
(
)
,
DSR
=
MD
.
getSubReg
(
)
;
bool
ReadUndef
=
MD
.
isUndef
(
)
;
MachineBasicBlock
::
iterator
At
=
MI
;
auto
updateRegs
=
[
&
UpdRegs
]
(
const
MachineInstr
&
MI
)
->
void
{
for
(
auto
&
Op
:
MI
.
operands
(
)
)
if
(
Op
.
isReg
(
)
)
UpdRegs
.
insert
(
Op
.
getReg
(
)
)
;
}
;
MachineOperand
&
ST
=
MI
.
getOperand
(
2
)
;
MachineOperand
&
SF
=
MI
.
getOperand
(
3
)
;
if
(
ST
.
isReg
(
)
&&
SF
.
isReg
(
)
)
{
RegisterRef
RT
(
ST
)
;
if
(
RT
==
RegisterRef
(
SF
)
)
{
updateRegs
(
MI
)
;
MI
.
setDesc
(
HII
->
get
(
TargetOpcode
::
COPY
)
)
;
unsigned
S
=
getRegState
(
ST
)
;
while
(
MI
.
getNumOperands
(
)
>
1
)
MI
.
RemoveOperand
(
MI
.
getNumOperands
(
)
1
)
;
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
MachineInstrBuilder
(
MF
,
MI
)
.
addReg
(
RT
.
Reg
,
S
,
RT
.
Sub
)
;
return
true
;
}
}
MachineInstr
*
TfrT
=
genCondTfrFor
(
ST
,
At
,
DR
,
DSR
,
MP
,
true
,
ReadUndef
,
false
)
;
MachineInstr
*
TfrF
=
genCondTfrFor
(
SF
,
At
,
DR
,
DSR
,
MP
,
false
,
ReadUndef
,
true
)
;
LIS
->
InsertMachineInstrInMaps
(
*
TfrT
)
;
LIS
->
InsertMachineInstrInMaps
(
*
TfrF
)
;
updateRegs
(
MI
)
;
removeInstr
(
MI
)
;
return
true
;
}
</s>

Split into substrings around the occurrences of a separator character .


<s> unsigned ARMBaseInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case ARM :: LDRrs : case ARM :: t2LDRs : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isReg ( ) && MI -> getOperand ( 3 ) . isImm ( ) && MI -> getOperand ( 2 ) . getReg ( ) == 0 && MI -> getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: LDRi12 : case ARM :: t2LDRi12 : case ARM :: tLDRspi : case ARM :: VLDRD : case ARM :: VLDRS : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VLD1q64 : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VLDMQIA : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> SMLoc getEndLoc ( ) const override { return End ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> bool PPCAsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { std :: string NewOpcode ; if ( getLexer ( ) . is ( AsmToken :: Plus ) ) { getLexer ( ) . Lex ( ) ; NewOpcode = Name ; NewOpcode += '+' ; Name = NewOpcode ; } if ( getLexer ( ) . is ( AsmToken :: Minus ) ) { getLexer ( ) . Lex ( ) ; NewOpcode = Name ; NewOpcode += '-' ; Name = NewOpcode ; } size_t Dot = Name . find ( '.' ) ; StringRef Mnemonic = Name . slice ( 0 , Dot ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( PPCOperand :: CreateTokenWithStringCopy ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; else Operands . push_back ( PPCOperand :: CreateToken ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; if ( Dot != StringRef :: npos ) { SMLoc DotLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Dot ) ; StringRef DotStr = Name . slice ( Dot , StringRef :: npos ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( PPCOperand :: CreateTokenWithStringCopy ( DotStr , DotLoc , isPPC64 ( ) ) ) ; else Operands . push_back ( PPCOperand :: CreateToken ( DotStr , DotLoc , isPPC64 ( ) ) ) ; } if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( ParseOperand ( Operands ) ) return true ; while ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) && getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( ParseOperand ( Operands ) ) return true ; } return false ; } </s>

ParseInstruction - Parse one assembly instruction .

PowerPC PPC 0 PPC PPC PPC PPC PPC PPC PPC PPC


<s> bool FISCInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { switch ( MI -> getOpcode ( ) ) { default : return false ; case FISC :: MOVi64 : { DebugLoc DL = MI -> getDebugLoc ( ) ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; const unsigned DstReg = MI -> getOperand ( 0 ) . getReg ( ) ; const bool DstIsDead = MI -> getOperand ( 0 ) . isDead ( ) ; const MachineOperand & MO = MI -> getOperand ( 1 ) ; auto Q1 = BuildMI ( MBB , MI , DL , get ( FISC :: MOVZ ) , DstReg ) ; auto Q2 = BuildMI ( MBB , MI , DL , get ( FISC :: MOVK ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; auto Q3 = BuildMI ( MBB , MI , DL , get ( FISC :: MOVK ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; auto Q4 = BuildMI ( MBB , MI , DL , get ( FISC :: MOVK ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; if ( MO . isImm ( ) ) { const uint64_t Imm = MO . getImm ( ) ; Q1 = Q1 . addImm ( Imm & 0xffff ) . addImm ( 0 ) ; Q2 = Q2 . addImm ( ( Imm >> 16 ) & 0xffff ) . addImm ( 1 ) ; Q3 = Q3 . addImm ( ( Imm >> 32 ) & 0xffff ) . addImm ( 2 ) ; Q4 = Q4 . addImm ( ( Imm >> 48 ) & 0xffff ) . addImm ( 3 ) ; } else { const GlobalValue * GV = MO . getGlobal ( ) ; const unsigned TF = MO . getTargetFlags ( ) ; Q1 = Q1 . addGlobalAddress ( GV , MO . getOffset ( ) , FISCII :: MO_Q1 ) . addImm ( 0 ) ; Q2 = Q2 . addGlobalAddress ( GV , MO . getOffset ( ) , FISCII :: MO_Q2 ) . addImm ( 1 ) ; Q3 = Q3 . addGlobalAddress ( GV , MO . getOffset ( ) , FISCII :: MO_Q3 ) . addImm ( 2 ) ; Q4 = Q4 . addGlobalAddress ( GV , MO . getOffset ( ) , FISCII :: MO_Q4 ) . addImm ( 3 ) ; } MBB . erase ( MI ) ; return true ; } } } </s>

This function is called for all pseudo instructions that remain after register allocation .


"Unrecognized Hexagon processor version"


<s> MachineInstr * ARMBaseInstrInfo :: commuteInstructionImpl ( MachineInstr & MI , bool NewMI , unsigned OpIdx1 , unsigned OpIdx2 ) const { switch ( MI . getOpcode ( ) ) { case ARM :: MOVCCr : case ARM :: t2MOVCCr : { unsigned PredReg = 0 ; ARMCC :: CondCodes CC = getInstrPredicate ( MI , PredReg ) ; if ( CC == ARMCC :: AL || PredReg != ARM :: CPSR ) return nullptr ; MachineInstr * CommutedMI = TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1 , OpIdx2 ) ; if ( ! CommutedMI ) return nullptr ; CommutedMI -> getOperand ( CommutedMI -> findFirstPredOperandIdx ( ) ) . setImm ( ARMCC :: getOppositeCondition ( CC ) ) ; return CommutedMI ; } } return TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1 , OpIdx2 ) ; } </s>

Commutes the operands in the given instruction by changing the operands order and/or changing the instruction 's opcode and/or the immediate value operand .


<s> bool nios2_legitimate_pic_operand_p ( rtx x ) { if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == UNSPEC && nios2_large_offset_p ( XINT ( XEXP ( x , 0 ) , 1 ) ) ) return true ; return ! ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF || GET_CODE ( x ) == CONST ) ; } </s>

Nonzero if the constant value X is a legitimate general operand when generating PIC code . It is given that flag_pic is on and that X satisfies CONSTANT_P or is a CONST_DOUBLE .


"Cannot get the value of a constant bit"


<s> rtx function_expander :: use_contiguous_load_insn ( insn_code icode ) { machine_mode mem_mode = memory_vector_mode ( ) ; add_output_operand ( icode ) ; add_mem_operand ( mem_mode , get_contiguous_base ( mem_mode ) ) ; add_input_operand ( icode , args [ 0 ] ) ; if ( GET_MODE_UNIT_BITSIZE ( mem_mode ) < type_suffix ( 0 ) . element_bits ) add_input_operand ( icode , CONSTM1_RTX ( VNx16BImode ) ) ; return generate_insn ( icode ) ; } </s>


<s>
static
void
rs6000_print_options_internal
(
FILE
*
file
,
int
indent
,
const
char
*
string
,
HOST_WIDE_INT
flags
,
const
char
*
prefix
,
const
struct
rs6000_opt_mask
*
opts
,
size_t
num_elements
)
{
size_t
i
;
size_t
start_column
=
0
;
size_t
cur_column
;
size_t
max_column
=
120
;
size_t
prefix_len
=
strlen
(
prefix
)
;
size_t
comma_len
=
0
;
const
char
*
comma
=
""
;
if
(
indent
)
start_column
+=
fprintf
(
file
,
"%*s"
,
indent
,
""
)
;
if
(
!
flags
)
{
fprintf
(
stderr
,
DEBUG_FMT_S
,
string
,
"<none>"
)
;
return
;
}
start_column
+=
fprintf
(
stderr
,
DEBUG_FMT_WX
,
string
,
flags
)
;
cur_column
=
start_column
;
for
(
i
=
0
;
i
<
num_elements
;
i
++
)
{
bool
invert
=
opts
[
i
]
.
invert
;
const
char
*
name
=
opts
[
i
]
.
name
;
const
char
*
no_str
=
""
;
HOST_WIDE_INT
mask
=
opts
[
i
]
.
mask
;
size_t
len
=
comma_len
+
prefix_len
+
strlen
(
name
)
;
if
(
!
invert
)
{
if
(
(
flags
&
mask
)
==
0
)
{
no_str
=
"no-"
;
len
+=
strlen
(
"no-"
)
;
}
flags
&=
~
mask
;
}
else
{
if
(
(
flags
&
mask
)
!=
0
)
{
no_str
=
"no-"
;
len
+=
strlen
(
"no-"
)
;
}
flags
|=
mask
;
}
cur_column
+=
len
;
if
(
cur_column
>
max_column
)
{
fprintf
(
stderr
,
", \\\n%*s"
,
(
int
)
start_column
,
""
)
;
cur_column
=
start_column
+
len
;
comma
=
""
;
}
fprintf
(
file
,
"%s%s%s%s"
,
comma
,
prefix
,
no_str
,
name
)
;
comma
=
", "
;
comma_len
=
strlen
(
", "
)
;
}
fputs
(
"\n"
,
file
)
;
}
</s>

Helper function to print the current isa or misc options on a line .


<s> void emitAssignment ( MCSymbol * S , const MCExpr * Value ) override { auto * Symbol = cast < MCSymbolELF > ( S ) ; if ( copyLocalEntry ( Symbol , Value ) ) UpdateOther . insert ( Symbol ) ; else UpdateOther . erase ( Symbol ) ; } </s>


<s> unsigned MBlazeMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO ) const { if ( MO . isReg ( ) ) return getMBlazeRegisterNumbering ( MO . getReg ( ) ) ; else if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; else if ( MO . isExpr ( ) ) return 0 ; else { errs ( ) << MO ; llvm_unreachable ( 0 ) ; } return 0 ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> bool call_operand ( rtx op , machine_mode mode ) { if ( ! MEM_P ( op ) ) return 0 ; op = XEXP ( op , 0 ) ; return call_address_operand ( op , mode ) ; } </s>

Call insn on SPARC can take a PC-relative constant address , or any regular memory address .


<s> bool AMDGPUTargetLowering :: isFNegFree ( EVT VT ) const { assert ( VT . isFloatingPoint ( ) ) ; return VT == MVT :: f32 || VT == MVT :: f64 ; } </s>

Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation .


<s> static void ia64_output_function_epilogue ( FILE * ) { int i ; if ( current_frame_info . r [ reg_fp ] ) { const char * tmp = reg_names [ HARD_FRAME_POINTER_REGNUM ] ; reg_names [ HARD_FRAME_POINTER_REGNUM ] = reg_names [ current_frame_info . r [ reg_fp ] ] ; reg_names [ current_frame_info . r [ reg_fp ] ] = tmp ; reg_emitted ( reg_fp ) ; } if ( ! TARGET_REG_NAMES ) { for ( i = 0 ; i < current_frame_info . n_input_regs ; i ++ ) reg_names [ IN_REG ( i ) ] = ia64_input_reg_names [ i ] ; for ( i = 0 ; i < current_frame_info . n_local_regs ; i ++ ) reg_names [ LOC_REG ( i ) ] = ia64_local_reg_names [ i ] ; for ( i = 0 ; i < current_frame_info . n_output_regs ; i ++ ) reg_names [ OUT_REG ( i ) ] = ia64_output_reg_names [ i ] ; } current_frame_info . initialized = 0 ; } </s>


<s> bool R600InstrInfo :: fitsConstReadLimitations ( const std :: vector < MachineInstr * > & MIs ) const { std :: vector < unsigned > Consts ; SmallSet < int64_t , 4 > Literals ; for ( unsigned i = 0 , n = MIs . size ( ) ; i < n ; i ++ ) { MachineInstr & MI = * MIs [ i ] ; if ( ! isALUInstr ( MI . getOpcode ( ) ) ) continue ; ArrayRef < std :: pair < MachineOperand * , int64_t >> Srcs = getSrcs ( MI ) ; for ( const auto & Src : Srcs ) { if ( Src . first -> getReg ( ) == AMDGPU :: ALU_LITERAL_X ) Literals . insert ( Src . second ) ; if ( Literals . size ( ) > 4 ) return false ; if ( Src . first -> getReg ( ) == AMDGPU :: ALU_CONST ) Consts . push_back ( Src . second ) ; if ( AMDGPU :: R600_KC0RegClass . contains ( Src . first -> getReg ( ) ) || AMDGPU :: R600_KC1RegClass . contains ( Src . first -> getReg ( ) ) ) { unsigned Index = RI . getEncodingValue ( Src . first -> getReg ( ) ) & 0xff ; unsigned Chan = RI . getHWRegChan ( Src . first -> getReg ( ) ) ; Consts . push_back ( ( Index << 2 ) | Chan ) ; } } } return fitsConstReadLimitations ( Consts ) ; } </s>

Same but using const index set instead of MI set .


<s> static void flow_dependent_p_1 ( rtx x , rtx pat ATTRIBUTE_UNUSED , void * data ) { rtx * pinsn = ( rtx * ) data ; if ( * pinsn && reg_referenced_p ( x , * pinsn ) ) * pinsn = NULL_RTX ; } </s>

A helper function for flow_dependent_p called through note_stores .


<s> aarch64_feature_flags get_flags_off ( aarch64_feature_flags mask ) { return ( 0 | ( feature_deps :: IDENT ( ) . enable & mask ? AARCH64_FL_ ## IDENT : 0 ) ) ; } </s>

Return the set of all features that would need to be disabled if the features in MASK are disabled . Note that the size of the expression varies linearly with the number of features , which means that invoking this function once per feature is quadratic in the number of features . However , collecting the same information at compiler start-up is likely to be quadratic too , so we 're better off paying the cost once per compiler build rather than once per compiler run .


<s> bool GCNTTIImpl :: isAlwaysUniform ( const Value * V ) const { if ( const IntrinsicInst * Intrinsic = dyn_cast < IntrinsicInst > ( V ) ) { switch ( Intrinsic -> getIntrinsicID ( ) ) { default : return false ; case Intrinsic :: amdgcn_readfirstlane : case Intrinsic :: amdgcn_readlane : case Intrinsic :: amdgcn_icmp : case Intrinsic :: amdgcn_fcmp : case Intrinsic :: amdgcn_if_break : return true ; } } if ( const CallInst * CI = dyn_cast < CallInst > ( V ) ) { if ( isa < InlineAsm > ( CI -> getCalledValue ( ) ) ) return ! isInlineAsmSourceOfDivergence ( CI ) ; return false ; } const ExtractValueInst * ExtValue = dyn_cast < ExtractValueInst > ( V ) ; if ( ! ExtValue ) return false ; const CallInst * CI = dyn_cast < CallInst > ( ExtValue -> getOperand ( 0 ) ) ; if ( ! CI ) return false ; if ( const IntrinsicInst * Intrinsic = dyn_cast < IntrinsicInst > ( CI ) ) { switch ( Intrinsic -> getIntrinsicID ( ) ) { default : return false ; case Intrinsic :: amdgcn_if : case Intrinsic :: amdgcn_else : { ArrayRef < unsigned > Indices = ExtValue -> getIndices ( ) ; return Indices . size ( ) == 1 && Indices [ 0 ] == 1 ; } } } if ( isa < InlineAsm > ( CI -> getCalledValue ( ) ) ) return ! isInlineAsmSourceOfDivergence ( CI , ExtValue -> getIndices ( ) ) ; return false ; } </s>

Whether Val will always return a uniform value regardless of its operands .


<s> int getIntImmCost ( Intrinsic :: ID IID , unsigned Idx , const APInt & Imm , Type * Ty ) { return getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> bool SPUTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * ) const { if ( AM . BaseGV && ! AM . HasBaseReg && AM . Scale == 0 && AM . BaseOffs == 0 ) return true ; if ( AM . BaseGV == 0 && AM . HasBaseReg && AM . Scale == 0 && isInt < 14 > ( AM . BaseOffs ) ) return true ; if ( AM . BaseGV == 0 && AM . HasBaseReg && AM . Scale == 1 && AM . BaseOffs == 0 ) return true ; return false ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s>
SDValue
RISCVTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
report_fatal_error
(
"unimplemented operand"
)
;
case
ISD
::
GlobalAddress
:
return
lowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
lowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
lowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
lowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
lowerSELECT
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
lowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
lowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
lowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
SHL_PARTS
:
return
lowerShiftLeftParts
(
Op
,
DAG
)
;
case
ISD
::
SRA_PARTS
:
return
lowerShiftRightParts
(
Op
,
DAG
,
true
)
;
case
ISD
::
SRL_PARTS
:
return
lowerShiftRightParts
(
Op
,
DAG
,
false
)
;
case
ISD
::
BITCAST
:
{
assert
(
Subtarget
.
is64Bit
(
)
&&
Subtarget
.
hasStdExtF
(
)
&&
"Unexpected custom legalisation"
)
;
SDLoc
DL
(
Op
)
;
SDValue
Op0
=
Op
.
getOperand
(
0
)
;
if
(
Op
.
getValueType
(
)
!=
MVT
::
f32
||
Op0
.
getValueType
(
)
!=
MVT
::
i32
)
return
SDValue
(
)
;
SDValue
NewOp0
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
DL
,
MVT
::
i64
,
Op0
)
;
SDValue
FPConv
=
DAG
.
getNode
(
RISCVISD
::
FMV_W_X_RV64
,
DL
,
MVT
::
f32
,
NewOp0
)
;
return
FPConv
;
}
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_W_CHAIN
:
return
SDValue
(
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> int getSEHRegNum ( unsigned i ) const { return getEncodingValue ( i ) ; } </s>

Map a target register to an equivalent SEH register number .


<s> bool AArch64FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; static LoadStoreMethod PossibleClasses [ ] = { { & AArch64 :: GPR64RegClass , AArch64 :: LSPair64_STR , AArch64 :: LS64_STR } , { & AArch64 :: FPR64RegClass , AArch64 :: LSFPPair64_STR , AArch64 :: LSFP64_STR } , } ; unsigned NumClasses = llvm :: array_lengthof ( PossibleClasses ) ; emitFrameMemOps ( true , MBB , MBBI , CSI , TRI , PossibleClasses , NumClasses ) ; return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


"Callee saved registers requested for unknown architecture "


"Couldn't get MachineMemOperand for store to stack."

"Only support 4-byte loads from stack now."

"Only support GPR32 stores to stack now."

Load the specified register of the given register class from the specified stack frame index .


<s> int legitimate_constant_p ( rtx x ATTRIBUTE_UNUSED ) { return 1 ; } </s>

Nonzero if the constant value X is a legitimate general operand . It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE .


<s> unsigned DCPU16InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == DCPU16 :: MOV16mr ) { if ( MI -> getOperand ( 0 ) . isFI ( ) ) { FrameIndex = MI -> getOperand ( 0 ) . getIndex ( ) ; return MI -> getOperand ( 2 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s>
const
RegisterBank
&
X86RegisterBankInfo
::
getRegBankFromRegClass
(
const
TargetRegisterClass
&
RC
)
const
{
if
(
X86
::
GR8RegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
GR16RegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
GR32RegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
GR64RegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
LOW32_ADDR_ACCESSRegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
LOW32_ADDR_ACCESS_RBPRegClass
.
hasSubClassEq
(
&
RC
)
)
return
getRegBank
(
X86
::
GPRRegBankID
)
;
if
(
X86
::
FR32XRegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
FR64XRegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
VR128XRegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
VR256XRegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
VR512RegClass
.
hasSubClassEq
(
&
RC
)
)
return
getRegBank
(
X86
::
VECRRegBankID
)
;
llvm_unreachable
(
"Unsupported register kind yet."
)
;
}
</s>


<s> bool GBZ80InstrInfo :: isConditionalBranch ( const MachineInstr & I ) const { return I . getOpcode ( ) == GB :: JP_cc_nn || I . getOpcode ( ) == GB :: JR_cc_e ; } </s>

Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block .


"  Mark r%d def in insn %d as requiring both modes in chain #%d\n"

For DImode conversion , mark register defined by DEF as requiring conversion .


<s> bool PPCLoopPreIncPrep :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; auto * DTWP = getAnalysisIfAvailable < DominatorTreeWrapperPass > ( ) ; DT = DTWP ? & DTWP -> getDomTree ( ) : nullptr ; PreserveLCSSA = mustPreserveAnalysisID ( LCSSAID ) ; bool MadeChange = false ; for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L = df_begin ( * I ) , LE = df_end ( * I ) ; L != LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ; return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static rtx avr_libcall_value ( machine_mode mode , const_rtx func ATTRIBUTE_UNUSED ) { int offs = GET_MODE_SIZE ( mode ) ; if ( offs <= 4 ) offs = ( offs + 1 ) & ~ 1 ; return gen_rtx_REG ( mode , avr_ret_register ( ) + 2 - offs ) ; } </s>

Ceate an RTX representing the place where a library function returns a value of mode MODE .


<s>
bool
TPCPacketizer
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
DisablePacketizer
||
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
HII
=
MF
.
getSubtarget
<
TPCSubtarget
>
(
)
.
getInstrInfo
(
)
;
HRI
=
MF
.
getSubtarget
<
TPCSubtarget
>
(
)
.
getRegisterInfo
(
)
;
auto
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
auto
*
AA
=
&
getAnalysis
<
AAResultsWrapperPass
>
(
)
.
getAAResults
(
)
;
auto
*
MBPI
=
&
getAnalysis
<
MachineBranchProbabilityInfo
>
(
)
;
TPCPacketizerList
Packetizer
(
MF
,
MLI
,
AA
,
MBPI
)
;
assert
(
Packetizer
.
getResourceTracker
(
)
&&
"Empty DFA table!"
)
;
if
(
Packetizer
.
getResourceTracker
(
)
->
getInstrItins
(
)
->
isEmpty
(
)
)
{
return
false
;
}
for
(
auto
&
MB
:
MF
)
{
auto
End
=
MB
.
end
(
)
;
auto
MI
=
MB
.
begin
(
)
;
while
(
MI
!=
End
)
{
auto
NextI
=
std
::
next
(
MI
)
;
if
(
MI
->
isKill
(
)
||
MI
->
getOpcode
(
)
==
TPC
::
IMPLICIT_DEF
)
{
MB
.
erase
(
MI
)
;
End
=
MB
.
end
(
)
;
}
MI
=
NextI
;
}
}
for
(
auto
&
MB
:
MF
)
{
Packetizer
.
PacketNum
=
0
;
Packetizer
.
PacketizeMIs
(
&
MB
,
MB
.
begin
(
)
,
MB
.
end
(
)
)
;
}
Packetizer
.
unpacketizeSoloInstrs
(
MF
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .

TPC
TPC
TPC
TPC
TPC
"Empty DFA table!"
TPC::IMPLICIT_DEF
0


<s> uint32_t BTFStringTable :: addString ( StringRef S ) { for ( auto & OffsetM : OffsetToIdMap ) { if ( Table [ OffsetM . second ] == S ) return OffsetM . first ; } uint32_t Offset = Size ; OffsetToIdMap [ Offset ] = Table . size ( ) ; Table . push_back ( S ) ; Size += S . size ( ) + 1 ; return Offset ; } </s>


<s> bool AMDGPUPromoteAlloca :: doInitialization ( Module & M ) { Mod = & M ; DL = & Mod -> getDataLayout ( ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> static bool compare_diff_p ( rtx_insn * insn ) { RTX_CODE cond = compare_condition ( insn ) ; return ( cond == GT || cond == GTU || cond == LE || cond == LEU ) ? cond : 0 ; } </s>

Returns nonzero if the next insn is a JUMP_INSN with a condition that needs to be swapped ( GT , GTU , LE , LEU ) .


<s> const MipsSubtarget * getSubtargetImpl ( ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> unsigned getGlobalBaseReg ( ) const { return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> EVT ARCompactTargetLowering :: getSetCCResultType ( EVT VT ) const { return MVT :: i32 ; } </s>

Return the value type to use for ISD : :SETCC .


<s> const UPTSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>


<s>
const
char
*
ashlsi3_out
(
rtx_insn
*
insn
,
rtx
operands
[
]
,
int
*
len
)
{
if
(
GET_CODE
(
operands
[
2
]
)
==
CONST_INT
)
{
int
k
;
int
*
t
=
len
;
if
(
!
len
)
len
=
&
k
;
switch
(
INTVAL
(
operands
[
2
]
)
)
{
default
:
if
(
INTVAL
(
operands
[
2
]
)
<
32
)
break
;
if
(
AVR_HAVE_MOVW
)
return
*
len
=
3
,
(
"clr %D0"
CR_TAB
"clr %C0"
CR_TAB
"movw %A0,%C0"
)
;
*
len
=
4
;
return
(
"clr %D0"
CR_TAB
"clr %C0"
CR_TAB
"clr %B0"
CR_TAB
"clr %A0"
)
;
case
8
:
{
int
reg0
=
true_regnum
(
operands
[
0
]
)
;
int
reg1
=
true_regnum
(
operands
[
1
]
)
;
*
len
=
4
;
if
(
reg0
>=
reg1
)
return
(
"mov %D0,%C1"
CR_TAB
"mov %C0,%B1"
CR_TAB
"mov %B0,%A1"
CR_TAB
"clr %A0"
)
;
else
return
(
"clr %A0"
CR_TAB
"mov %B0,%A1"
CR_TAB
"mov %C0,%B1"
CR_TAB
"mov %D0,%C1"
)
;
}
case
16
:
{
int
reg0
=
true_regnum
(
operands
[
0
]
)
;
int
reg1
=
true_regnum
(
operands
[
1
]
)
;
if
(
reg0
+
2
==
reg1
)
return
*
len
=
2
,
(
"clr %B0"
CR_TAB
"clr %A0"
)
;
if
(
AVR_HAVE_MOVW
)
return
*
len
=
3
,
(
"movw %C0,%A1"
CR_TAB
"clr %B0"
CR_TAB
"clr %A0"
)
;
else
return
*
len
=
4
,
(
"mov %C0,%A1"
CR_TAB
"mov %D0,%B1"
CR_TAB
"clr %B0"
CR_TAB
"clr %A0"
)
;
}
case
24
:
*
len
=
4
;
return
(
"mov %D0,%A1"
CR_TAB
"clr %C0"
CR_TAB
"clr %B0"
CR_TAB
"clr %A0"
)
;
case
31
:
*
len
=
6
;
return
(
"clr %D0"
CR_TAB
"lsr %A0"
CR_TAB
"ror %D0"
CR_TAB
"clr %C0"
CR_TAB
"clr %B0"
CR_TAB
"clr %A0"
)
;
}
len
=
t
;
}
out_shift_with_cnt
(
"lsl %A0"
CR_TAB
"rol %B0"
CR_TAB
"rol %C0"
CR_TAB
"rol %D0"
,
insn
,
operands
,
len
,
4
)
;
return
""
;
}
</s>


<s>
const
ArrayRef
<
MCPhysReg
>
SICABIInfo
::
GetVarArgRegs
(
)
const
{
if
(
IsO32
(
)
)
return
makeArrayRef
(
O32IntRegs
)
;
if
(
IsS32
(
)
)
return
makeArrayRef
(
S32IntRegs
)
;
llvm_unreachable
(
"Unhandled ABI"
)
;
}
</s>

The registers to use for the variable argument list .


<s> SDValue rvexTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , DebugLoc dl , SelectionDAG & DAG ) const { return DAG . getNode ( rvexISD :: Ret , dl , MVT :: Other , Chain , DAG . getRegister ( rvex :: LR , MVT :: i32 ) ) ; } </s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .

rvex rvex ISD::OutputArg rvexISD::Ret MVT::Other rvex::LR MVT::i32


<s> Instruction * PPCTargetLowering :: emitLeadingFence ( IRBuilder < > & Builder , AtomicOrdering Ord , bool IsStore , bool IsLoad ) const { if ( Ord == AtomicOrdering :: SequentiallyConsistent ) return callIntrinsic ( Builder , Intrinsic :: ppc_sync ) ; if ( isReleaseOrStronger ( Ord ) ) return callIntrinsic ( Builder , Intrinsic :: ppc_lwsync ) ; return nullptr ; } </s>


<s> unsigned X86InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( isFrameStoreOpcode ( MI -> getOpcode ( ) ) ) { if ( MI -> getOperand ( X86 :: AddrNumOperands ) . getSubReg ( ) == 0 && isFrameOperand ( MI , 0 , FrameIndex ) ) return MI -> getOperand ( X86 :: AddrNumOperands ) . getReg ( ) ; } return 0 ; } </s>


<s>
void
MipsInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
if
(
RC
==
Mips
::
CPURegsRegisterClass
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
LW
)
,
DestReg
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
else
if
(
RC
==
Mips
::
FGR32RegisterClass
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
LWC1
)
,
DestReg
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
else
if
(
RC
==
Mips
::
AFGR64RegisterClass
)
{
if
(
!
TM
.
getSubtarget
<
MipsSubtarget
>
(
)
.
isMips1
(
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
LDC1
)
,
DestReg
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
}
else
{
const
TargetRegisterInfo
*
TRI
=
MBB
.
getParent
(
)
->
getTarget
(
)
.
getRegisterInfo
(
)
;
const
unsigned
*
SubSet
=
TRI
->
getSubRegisters
(
DestReg
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
LWC1
)
,
SubSet
[
0
]
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
LWC1
)
,
SubSet
[
1
]
)
.
addImm
(
4
)
.
addFrameIndex
(
FI
)
;
}
}
else
llvm_unreachable
(
"Register class not handled!"
)
;
}
</s>


<s> static void m32r_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; * cum = ( ROUND_ADVANCE_CUM ( * cum , mode , type ) + ROUND_ADVANCE_ARG ( mode , type ) ) ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> SDValue Z80TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { if ( N -> isMachineOpcode ( ) ) switch ( N -> getMachineOpcode ( ) ) { default : return SDValue ( ) ; case TargetOpcode :: EXTRACT_SUBREG : return combineExtractSubreg ( N , DCI . DAG , Subtarget ) ; } switch ( N -> getOpcode ( ) ) { default : return SDValue ( ) ; case ISD :: MUL : return combineMul ( N , DCI . DAG , Subtarget ) ; case ISD :: AND : return combineAnd ( N , DCI . DAG ) ; case ISD :: ZERO_EXTEND : return combineZeroExtend ( N , DCI ) ; case ISD :: TRUNCATE : return combineTruncate ( N , DCI . DAG ) ; case Z80ISD :: SUB : return combineSub ( N , DCI ) ; case Z80ISD :: SEXT : return combineSExt ( N , DCI . DAG , Subtarget ) ; } switch ( N -> getOpcode ( ) ) { } } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> static bool nds32_fp_as_gp_check_available ( void ) { basic_block bb ; basic_block exit_bb ; edge_iterator ei ; edge e ; bool first_exit_blocks_p ; if ( TARGET_FORBID_FP_AS_GP || nds32_naked_function_p ( current_function_decl ) || ! optimize_size || frame_pointer_needed || NDS32_REQUIRED_CALLEE_SAVED_P ( FP_REGNUM ) || ( cfun -> stdarg == 1 ) || ( find_fallthru_edge ( EXIT_BLOCK_PTR_FOR_FN ( cfun ) -> preds ) == NULL ) ) return false ; first_exit_blocks_p = true ; exit_bb = NULL ; FOR_EACH_EDGE ( e , ei , EXIT_BLOCK_PTR_FOR_FN ( cfun ) -> preds ) { if ( ! first_exit_blocks_p ) return false ; exit_bb = e -> src ; first_exit_blocks_p = false ; } if ( ! exit_bb ) return false ; FOR_EACH_BB_FN ( bb , cfun ) { if ( ! dominated_by_p ( CDI_POST_DOMINATORS , bb , exit_bb ) ) return false ; } if ( TARGET_FORCE_FP_AS_GP ) { return true ; } else { bool good_gain = false ; int symbol_count ; int threshold ; if ( flag_pic || nds32_have_prologue_p ( ) ) { threshold = 3 ; } else { threshold = 5 + ( TARGET_V3PUSH ? 0 : 2 ) ; } symbol_count = nds32_get_symbol_count ( ) ; if ( symbol_count >= threshold ) good_gain = true ; return good_gain ; } } </s>

Function to determine whether it is worth to do fp_as_gp optimization . Return 0 : It is NOT worth to do fp_as_gp optimization . Return 1 : It is APPROXIMATELY worth to do fp_as_gp optimization . Note that if it is worth to do fp_as_gp optimization , we MUST set FP_REGNUM ever live in this function .


<s>
bool
HexagonOptAddrMode
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
bool
Changed
=
false
;
auto
&
HST
=
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
;
auto
&
MRI
=
MF
.
getRegInfo
(
)
;
HII
=
HST
.
getInstrInfo
(
)
;
const
auto
&
MDF
=
getAnalysis
<
MachineDominanceFrontier
>
(
)
;
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
const
auto
&
TRI
=
*
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
const
TargetOperandInfo
TOI
(
*
HII
)
;
DataFlowGraph
G
(
MF
,
*
HII
,
TRI
,
*
MDT
,
MDF
,
TOI
)
;
G
.
build
(
BuildOptions
::
KeepDeadPhis
)
;
DFG
=
&
G
;
Liveness
L
(
MRI
,
*
DFG
)
;
L
.
computePhiInfo
(
)
;
LV
=
&
L
;
Deleted
.
clear
(
)
;
NodeAddr
<
FuncNode
*
>
FA
=
DFG
->
getFunc
(
)
;
DEBUG
(
dbgs
(
)
<<
"==== [RefMap#]=====:\n "
<<
Print
<
NodeAddr
<
FuncNode
*
>>
(
FA
,
*
DFG
)
<<
"\n"
)
;
for
(
NodeAddr
<
BlockNode
*
>
BA
:
FA
.
Addr
->
members
(
*
DFG
)
)
Changed
|=
processBlock
(
BA
)
;
for
(
auto
MI
:
Deleted
)
MI
->
eraseFromParent
(
)
;
if
(
Changed
)
{
G
.
build
(
)
;
L
.
computeLiveIns
(
)
;
L
.
resetLiveIns
(
)
;
L
.
resetKills
(
)
;
}
return
Changed
;
}
</s>

Hexagon
Hexagon
Hexagon
"==== [RefMap#]=====:\n "
"\n"


<s> machine_mode mips_hard_regno_caller_save_mode ( unsigned int regno , unsigned int nregs , machine_mode mode ) { if ( mode == VOIDmode ) return choose_hard_reg_mode ( regno , nregs , false ) ; else return mode ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < PMLImport > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < MachinePostDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addPreserved < MachinePostDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> unsigned RISCVInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : return 0 ; case RISCV :: LB : case RISCV :: LBU : case RISCV :: LH : case RISCV :: LHU : case RISCV :: FLH : case RISCV :: LW : case RISCV :: FLW : case RISCV :: LWU : case RISCV :: LD : case RISCV :: FLD : break ; } if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < DataLayoutPass > ( ) ; AU . addPreserved ( "stack-protector" ) ; AU . addPreserved < MachineFunctionAnalysis > ( ) ; } </s>


<s> const DigitalSubtarget * getSubtargetImpl ( ) const { return & DefaultSubtarget ; } </s>


<s> const char * getPassName ( ) const override { return AARCH64_EXPAND_PSEUDO_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> MVT MipsTargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , EVT VT ) const { if ( VT . isVector ( ) ) { if ( Subtarget . isABI_O32 ( ) ) { return MVT :: i32 ; } else { return ( VT . getSizeInBits ( ) == 32 ) ? MVT :: i32 : MVT :: i64 ; } } return MipsTargetLowering :: getRegisterType ( Context , VT ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


"********** Replace Physical Registers **********\n"

"LiveIntervals shouldn't be active yet!"


<s> void v850_output_common ( FILE * file , tree decl , const char * name , int size , int align ) { if ( decl == NULL_TREE ) { fprintf ( file , "%s" , COMMON_ASM_OP ) ; } else { switch ( v850_get_data_area ( decl ) ) { case DATA_AREA_ZDA : fprintf ( file , "%s" , ZCOMMON_ASM_OP ) ; break ; case DATA_AREA_SDA : fprintf ( file , "%s" , SCOMMON_ASM_OP ) ; break ; case DATA_AREA_TDA : fprintf ( file , "%s" , TCOMMON_ASM_OP ) ; break ; default : fprintf ( file , "%s" , COMMON_ASM_OP ) ; break ; } } assemble_name ( file , name ) ; fprintf ( file , ",%u,%u\n" , size , align / BITS_PER_UNIT ) ; } </s>

Called via the macro ASM_OUTPUT_DECL_COMMON


<s> bool MCS51AsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : return false ; case MCS51 :: fixup_7_pcrel : case MCS51 :: fixup_13_pcrel : case MCS51 :: fixup_call : return true ; } } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> static machine_mode nvptx_preferred_simd_mode ( scalar_mode mode ) { switch ( mode ) { case E_DImode : return V2DImode ; case E_SImode : return V2SImode ; default : return default_preferred_simd_mode ( mode ) ; } } </s>

Return the preferred mode for vectorizing scalar MODE .


<s> bool PatmosSinglePathInfo :: doFinalization ( Module & M ) { if ( Root ) { delete Root ; Root = NULL ; } return false ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> function_symbol_result function_symbol ( rtx target , const char * name , sh_function_kind kind ) { if ( kind != FUNCTION_ORDINARY ) name = IDENTIFIER_POINTER ( get_identifier ( name ) ) ; rtx sym = gen_rtx_SYMBOL_REF ( Pmode , name ) ; rtx lab = const0_rtx ; SYMBOL_REF_FLAGS ( sym ) = SYMBOL_FLAG_FUNCTION ; if ( flag_pic ) switch ( kind ) { case FUNCTION_ORDINARY : break ; case SFUNC_GOT : { rtx reg = target ? target : gen_reg_rtx ( Pmode ) ; emit_insn ( gen_symGOT2reg ( reg , sym ) ) ; sym = reg ; break ; } case SFUNC_STATIC : { rtx reg = target ? target : gen_reg_rtx ( Pmode ) ; if ( TARGET_FDPIC ) { lab = PATTERN ( gen_call_site ( ) ) ; emit_insn ( gen_sym_label2reg ( reg , sym , lab ) ) ; } else { emit_insn ( gen_symGOTOFF2reg ( reg , sym ) ) ; } sym = reg ; break ; } } if ( target && sym != target ) { emit_move_insn ( target , sym ) ; return function_symbol_result ( target , lab ) ; } return function_symbol_result ( sym , lab ) ; } </s>

Return an RTX pair for the address and call site label of a function NAME of kind KIND , placing the result in TARGET if not NULL . For SFUNC_STATIC , if FDPIC , the LAB member of result will be set to ( const_int 0 ) if jsr should be used , or a label_ref if bsrf should be used . For FDPIC , both SFUNC_GOT and SFUNC_STATIC will return the address of the function itself , not a function descriptor , so they can only be used with functions not using the FDPIC register that are known to be called directory without a PLT entry .


<s> unsigned int rs6000_special_round_type_align ( tree type , unsigned int computed , unsigned int specified ) { unsigned int align = MAX ( computed , specified ) ; tree field = TYPE_FIELDS ( type ) ; while ( field != NULL && TREE_CODE ( field ) != FIELD_DECL ) field = DECL_CHAIN ( field ) ; if ( field != NULL && field != type ) { type = TREE_TYPE ( field ) ; while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; if ( type != error_mark_node && TYPE_MODE ( type ) == DFmode ) align = MAX ( align , 64 ) ; } return align ; } </s>

Darwin , AIX increases natural record alignment to doubleword if the first field is an FP double while the FP fields remain word aligned .


<s> void RISCVAsmPrinter :: emitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; MCInst TmpInst ; if ( ! lowerRISCVMachineInstrToMCInst ( MI , TmpInst , * this ) ) EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

Targets should implement this to emit instructions .


<s> TargetLoweringBase :: LegalizeTypeAction getPreferredVectorAction ( EVT VT ) const override { if ( VT . getScalarSizeInBits ( ) % 8 == 0 ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s> bool runOnFunction ( Function & F ) override { if ( skipFunction ( F ) ) return false ; PHINodeSet PromotablePHINodes = getPromotablePHINodes ( F ) ; B2IMap Bool2IntMap ; bool Changed = false ; for ( auto & BB : F ) { for ( auto & I : BB ) { if ( auto * R = dyn_cast < ReturnInst > ( & I ) ) if ( F . getReturnType ( ) -> isIntegerTy ( 1 ) ) Changed |= runOnUse ( R -> getOperandUse ( 0 ) , PromotablePHINodes , Bool2IntMap ) ; if ( auto * CI = dyn_cast < CallInst > ( & I ) ) for ( auto & U : CI -> operands ( ) ) if ( U -> getType ( ) -> isIntegerTy ( 1 ) ) Changed |= runOnUse ( U , PromotablePHINodes , Bool2IntMap ) ; } } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


Return true if the vector misalignment factor is supported by the target .


<s>
bool
Z80AsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
if
(
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MatchingInlineAsm
)
)
{
Out
.
EmitInstruction
(
Inst
,
this
->
STI
)
;
return
false
;
}
return
Error
(
IDLoc
,
"Failed to parse instruction"
)
;
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"X86 Byte/Word Instruction Fixup"
;
}
</s>


<s>
const
char
*
getPassName
(
)
const
{
return
"Hexagon Copy-To-Combine Pass"
;
}
</s>


<s> bool MipsFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * EntryBlock = MF -> begin ( ) ; const TargetInstrInfo & TII = * MF -> getTarget ( ) . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == Mips :: RA || Reg == Mips :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


"too large function value type, needs %d registers,\ have only %d registers for this"


<s> static rtx arm_gen_multiple_op ( bool is_load , int * regs , int count , rtx basereg , bool write_back , rtx basemem , HOST_WIDE_INT * offsetp ) { rtx mems [ MAX_LDM_STM_OPS ] ; HOST_WIDE_INT offset = * offsetp ; int i ; gcc_assert ( count <= MAX_LDM_STM_OPS ) ; if ( GET_CODE ( basereg ) == PLUS ) basereg = XEXP ( basereg , 0 ) ; for ( i = 0 ; i < count ; i ++ ) { rtx addr = plus_constant ( Pmode , basereg , i * 4 ) ; mems [ i ] = adjust_automodify_address_nv ( basemem , SImode , addr , offset ) ; offset += 4 ; } if ( write_back ) * offsetp = offset ; if ( is_load ) return arm_gen_load_multiple_1 ( count , regs , mems , basereg , write_back ? 4 * count : 0 ) ; else return arm_gen_store_multiple_1 ( count , regs , mems , basereg , write_back ? 4 * count : 0 ) ; } </s>

Generate either a load-multiple or a store-multiple instruction . This function can be used in situations where we can start with a single MEM rtx and adjust its address upwards . COUNT is the number of operations in the instruction , not counting a possible update of the base register . REGS is an array containing the register operands . BASEREG is the base register to be used in addressing the memory operands , which are constructed from BASEMEM . WRITE_BACK specifies whether the generated instruction should include an update of the base register . OFFSETP is used to pass an offset to and from this function ; this offset is not used when constructing the address ( instead BASEMEM should have an appropriate offset in its address ) , it is used only for setting MEM_OFFSET . It is updated only if WRITE_BACK is true .


<s> bool MSP430FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MSP430MachineFunctionInfo * MFI = MF . getInfo < MSP430MachineFunctionInfo > ( ) ; MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( MSP430 :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ; } return true ; } </s>


<s> bool exp2_immediate_p ( rtx op , machine_mode mode , int low , int high ) { machine_mode int_mode ; HOST_WIDE_INT val ; unsigned char arr [ 16 ] ; int bytes , i , j ; gcc_assert ( GET_CODE ( op ) == CONST_INT || GET_CODE ( op ) == CONST_DOUBLE || GET_CODE ( op ) == CONST_VECTOR ) ; if ( GET_CODE ( op ) == CONST_VECTOR && ! const_vector_immediate_p ( op ) ) return 0 ; if ( GET_MODE ( op ) != VOIDmode ) mode = GET_MODE ( op ) ; constant_to_array ( mode , op , arr ) ; mode = GET_MODE_INNER ( mode ) ; bytes = GET_MODE_SIZE ( mode ) ; int_mode = mode_for_size ( GET_MODE_BITSIZE ( mode ) , MODE_INT , 0 ) ; for ( i = bytes ; i < 16 ; i += bytes ) for ( j = 0 ; j < bytes ; j ++ ) if ( arr [ j ] != arr [ i + j ] ) return 0 ; val = arr [ 0 ] ; for ( j = 1 ; j < bytes ; j ++ ) val = ( val << 8 ) | arr [ j ] ; val = trunc_int_for_mode ( val , int_mode ) ; gcc_assert ( mode == SFmode ) ; if ( mode == SFmode ) { int exp = ( val >> 23 ) - 127 ; return val > 0 && ( val & 0x007fffff ) == 0 && exp >= low && exp <= high ; } return FALSE ; } </s>

TRUE when op is an immediate and an exact power of 2 , and given that OP is 2^scale , scale > = LOW & & scale < = HIGH . When OP is a vector , all entries must be the same .


<s> bool HexagonVectorLoopCarriedReuse :: run ( ) { if ( ! CurLoop -> getLoopPreheader ( ) ) return false ; if ( ! CurLoop -> getSubLoops ( ) . empty ( ) ) return false ; if ( CurLoop -> getNumBlocks ( ) != 1 ) return false ; return doVLCR ( ) ; } </s>

Run the analysis pass over a function and produce a dominator tree .


<s> void LanaiAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned , uint64_t Value , bool ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( static_cast < unsigned > ( Kind ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize = 4 ; uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; CurVal |= static_cast < uint64_t > ( static_cast < uint8_t > ( Data [ Offset + Idx ] ) ) << ( i * 8 ) ; } uint64_t Mask = ( static_cast < uint64_t > ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = static_cast < uint8_t > ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void GBZ80TargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { Base :: Initialize ( Ctx , TM ) ; TextSection = getSection ( SectionKind :: getText ( ) , StringRef ( ".text" ) , GBSectionType :: ST_ROM0 , 0 , ~ 0U , 1 , nullptr ) ; DataSection = getSection ( SectionKind :: getText ( ) , StringRef ( ".data" ) , GBSectionType :: ST_WRAM0 , 0 , ~ 0U , 1 , nullptr ) ; BSSSection = getSection ( SectionKind :: getText ( ) , StringRef ( ".bss" ) , GBSectionType :: ST_WRAM0 , 0 , ~ 0U , 1 , nullptr ) ; ReadOnlySection = getSection ( SectionKind :: getText ( ) , StringRef ( ".readonly" ) , GBSectionType :: ST_ROM0 , 0 , ~ 0U , 1 , nullptr ) ; } </s>

This method must be called before any actual lowering is done .


<s>
void
AArch64AppleInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
O
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
)
{
unsigned
Opcode
=
MI
->
getOpcode
(
)
;
StringRef
Layout
;
bool
IsTbx
;
if
(
isTblTbxInstruction
(
MI
->
getOpcode
(
)
,
Layout
,
IsTbx
)
)
{
O
<<
"\t"
<<
(
IsTbx
"tbx"
:
"tbl"
)
<<
Layout
<<
'\t'
<<
getRegisterName
(
MI
->
getOperand
(
0
)
.
getReg
(
)
,
AArch64
::
vreg
)
<<
", "
;
unsigned
ListOpNum
=
IsTbx
2
:
1
;
printVectorList
(
MI
,
ListOpNum
,
STI
,
O
,
""
)
;
O
<<
", "
<<
getRegisterName
(
MI
->
getOperand
(
ListOpNum
+
1
)
.
getReg
(
)
,
AArch64
::
vreg
)
;
printAnnotation
(
O
,
Annot
)
;
return
;
}
if
(
const
LdStNInstrDesc
*
LdStDesc
=
getLdStNInstrDesc
(
Opcode
)
)
{
O
<<
"\t"
<<
LdStDesc
->
Mnemonic
<<
LdStDesc
->
Layout
<<
'\t'
;
int
OpNum
=
LdStDesc
->
ListOperand
;
printVectorList
(
MI
,
OpNum
++
,
STI
,
O
,
""
)
;
if
(
LdStDesc
->
HasLane
)
O
<<
'['
<<
MI
->
getOperand
(
OpNum
++
)
.
getImm
(
)
<<
']'
;
unsigned
AddrReg
=
MI
->
getOperand
(
OpNum
++
)
.
getReg
(
)
;
O
<<
", ["
<<
getRegisterName
(
AddrReg
)
<<
']'
;
if
(
LdStDesc
->
NaturalOffset
!=
0
)
{
unsigned
Reg
=
MI
->
getOperand
(
OpNum
++
)
.
getReg
(
)
;
if
(
Reg
!=
AArch64
::
XZR
)
O
<<
", "
<<
getRegisterName
(
Reg
)
;
else
{
assert
(
LdStDesc
->
NaturalOffset
&&
"no offset on post-inc instruction?"
)
;
O
<<
", #"
<<
LdStDesc
->
NaturalOffset
;
}
}
printAnnotation
(
O
,
Annot
)
;
return
;
}
AArch64InstPrinter
::
printInst
(
MI
,
O
,
Annot
,
STI
)
;
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s> void M680x0ELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; this -> TM = & static_cast < const M680x0TargetMachine & > ( TM ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; } </s>


<s> bool M68kAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { if ( ! ExtraCode || ! ExtraCode [ 0 ] ) { printOperand ( MI , OpNo , OS ) ; return false ; } return AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , OS ) ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


"Atomic inst not expanded when it should be?"


<s> static bool cdx_add_immed ( rtx op ) { if ( CONST_INT_P ( op ) ) { HOST_WIDE_INT ival = INTVAL ( op ) ; return ival <= 128 && ival > 0 && ( ival & ( ival - 1 ) ) == 0 ; } return false ; } </s>

Returns true if OP is within range of CDX addi.n immediates .


<s> Relocator :: Size AArch64Relocator :: getSize ( Relocation :: Type pType ) const { return ApplyFunctions [ pType ] . size ; } </s>

Return the number of bytes in the encoding of this instruction , or zero if the encoding size can not be known from the opcode .


<s> void F2003fMCAsmStreamer :: AddComment ( const Twine & T , bool EOL ) { if ( ! IsVerboseAsm ) return ; T . toVector ( CommentToEmit ) ; if ( EOL ) CommentToEmit . push_back ( '\n' ) ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < TargetPassConfig > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> ScheduleHazardRecognizer :: HazardType ARMBankConflictHazardRecognizer :: getHazardType ( SUnit * SU , int Stalls ) { MachineInstr & L0 = * SU -> getInstr ( ) ; if ( ! L0 . mayLoad ( ) || L0 . mayStore ( ) || L0 . getNumMemOperands ( ) != 1 ) return NoHazard ; auto MO0 = * L0 . memoperands ( ) . begin ( ) ; auto BaseVal0 = MO0 -> getValue ( ) ; auto BasePseudoVal0 = MO0 -> getPseudoValue ( ) ; int64_t Offset0 = 0 ; if ( MO0 -> getSize ( ) > 4 ) return NoHazard ; bool SPvalid = false ; const MachineOperand * SP = nullptr ; int64_t SPOffset0 = 0 ; for ( auto L1 : Accesses ) { auto MO1 = * L1 -> memoperands ( ) . begin ( ) ; auto BaseVal1 = MO1 -> getValue ( ) ; auto BasePseudoVal1 = MO1 -> getPseudoValue ( ) ; int64_t Offset1 = 0 ; if ( BaseVal0 && BaseVal1 ) { const Value * Ptr0 , * Ptr1 ; Ptr0 = GetPointerBaseWithConstantOffset ( BaseVal0 , Offset0 , DL , true ) ; Ptr1 = GetPointerBaseWithConstantOffset ( BaseVal1 , Offset1 , DL , true ) ; if ( Ptr0 == Ptr1 && Ptr0 ) return CheckOffsets ( Offset0 , Offset1 ) ; } if ( BasePseudoVal0 && BasePseudoVal1 && BasePseudoVal0 -> kind ( ) == BasePseudoVal1 -> kind ( ) && BasePseudoVal0 -> kind ( ) == PseudoSourceValue :: FixedStack ) { auto FS0 = cast < FixedStackPseudoSourceValue > ( BasePseudoVal0 ) ; auto FS1 = cast < FixedStackPseudoSourceValue > ( BasePseudoVal1 ) ; Offset0 = MF . getFrameInfo ( ) . getObjectOffset ( FS0 -> getFrameIndex ( ) ) ; Offset1 = MF . getFrameInfo ( ) . getObjectOffset ( FS1 -> getFrameIndex ( ) ) ; return CheckOffsets ( Offset0 , Offset1 ) ; } if ( BasePseudoVal0 && BasePseudoVal1 && BasePseudoVal0 -> kind ( ) == BasePseudoVal1 -> kind ( ) && BasePseudoVal0 -> isConstantPool ( ) && AssumeITCMBankConflict ) return Hazard ; if ( ! SPvalid ) { if ( ! getBaseOffset ( L0 , SP , SPOffset0 ) || SP -> getReg ( ) . id ( ) != ARM :: SP ) SP = nullptr ; SPvalid = true ; } if ( SP ) { int64_t SPOffset1 ; const MachineOperand * SP1 ; if ( getBaseOffset ( * L1 , SP1 , SPOffset1 ) && SP1 -> getReg ( ) . id ( ) == ARM :: SP ) return CheckOffsets ( SPOffset0 , SPOffset1 ) ; } } return NoHazard ; } </s>

getHazardType - Return the hazard type of emitting this node .


<s> void SystemZInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned LoadOpcode , StoreOpcode ; getLoadStoreOpcodes ( RC , LoadOpcode , StoreOpcode ) ; addFrameReference ( BuildMI ( MBB , MBBI , DL , get ( StoreOpcode ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> virtual MachineInstr * foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const { return 0 ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> void HexagonInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { if ( Hexagon :: IntRegsRegClass . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: TFR ) , DestReg ) . addReg ( SrcReg ) ; return ; } if ( Hexagon :: DoubleRegsRegClass . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: TFR_64 ) , DestReg ) . addReg ( SrcReg ) ; return ; } if ( Hexagon :: PredRegsRegClass . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: OR_pp ) , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg ) ; return ; } if ( Hexagon :: DoubleRegsRegClass . contains ( DestReg , SrcReg ) ) { if ( SrcReg == RI . getSubReg ( DestReg , Hexagon :: subreg_loreg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: TFRI ) , ( RI . getSubReg ( DestReg , Hexagon :: subreg_hireg ) ) ) . addImm ( 0 ) ; } else { BuildMI ( MBB , I , DL , get ( Hexagon :: TFR ) , ( RI . getSubReg ( DestReg , Hexagon :: subreg_loreg ) ) ) . addReg ( SrcReg ) ; BuildMI ( MBB , I , DL , get ( Hexagon :: TFRI ) , ( RI . getSubReg ( DestReg , Hexagon :: subreg_hireg ) ) ) . addImm ( 0 ) ; } return ; } if ( Hexagon :: CRRegsRegClass . contains ( DestReg , SrcReg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: TFCR ) , DestReg ) . addReg ( SrcReg ) ; return ; } assert ( 0 && "Unimplemented" ) ; } </s>


<s> unsigned int pass_bpf_core_attr :: execute ( function * fn ) { handle_attr_preserve ( fn ) ; return 0 ; } </s>


<s> void EmitInstruction ( uint64_t Val , unsigned Size , raw_ostream & OS ) const { if ( IsLittleEndian && Size == 4 && IsMicroMips ) { EmitInstruction ( Val >> 16 , 2 , OS ) ; EmitInstruction ( Val , 2 , OS ) ; } else { for ( unsigned i = 0 ; i < Size ; ++ i ) { unsigned Shift = IsLittleEndian ? i * 8 : ( Size - 1 - i ) * 8 ; EmitByte ( ( Val >> Shift ) & 0xff , OS ) ; } } } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .