<s> SDValue HexagonTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SmallVectorImpl < SDValue > & OutVals , SDValue Callee ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_Hexagon ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( ARM :: GPRRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( ARM :: t2LDRi12 ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; return ; } if ( ARM :: GPRPairRegClass . hasSubClassEq ( RC ) ) { if ( Register :: isVirtualRegister ( DestReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( DestReg , & ARM :: GPRPairnospRegClass ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( ARM :: t2LDRDi8 ) ) ; AddDReg ( MIB , DestReg , ARM :: gsub_0 , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , ARM :: gsub_1 , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; if ( Register :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; } ARMBaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC , TRI ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> void HexagonCommonGEP :: removeDeadCode ( ) { ValueVect BO ; BO . push_back ( & Fn -> front ( ) ) ; for ( unsigned i = 0 ; i < BO . size ( ) ; ++ i ) { BasicBlock * B = cast < BasicBlock > ( BO [ i ] ) ; for ( auto DTN : children < DomTreeNode * > ( DT -> getNode ( B ) ) ) BO . push_back ( DTN -> getBlock ( ) ) ; } for ( Value * V : llvm :: reverse ( BO ) ) { BasicBlock * B = cast < BasicBlock > ( V ) ; ValueVect Ins ; for ( Instruction & I : llvm :: reverse ( * B ) ) Ins . push_back ( & I ) ; for ( ValueVect :: iterator I = Ins . begin ( ) , E = Ins . end ( ) ; I != E ; ++ I ) { Instruction * In = cast < Instruction > ( * I ) ; if ( isInstructionTriviallyDead ( In ) ) In -> eraseFromParent ( ) ; } } } </s>

Remove all dead instructions between the I and E .


<s> void rs6000_output_function_entry ( FILE * file , const char * fname ) { if ( fname [ 0 ] != '.' ) { switch ( DEFAULT_ABI ) { default : gcc_unreachable ( ) ; case ABI_AIX : if ( DOT_SYMBOLS ) putc ( '.' , file ) ; else ASM_OUTPUT_INTERNAL_LABEL_PREFIX ( file , "L." ) ; break ; case ABI_ELFv2 : case ABI_V4 : case ABI_DARWIN : break ; } } RS6000_OUTPUT_BASENAME ( file , fname ) ; } </s>


<s> bool ThumbRegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { const ARMSubtarget & STI = MBB . getParent ( ) -> getSubtarget < ARMSubtarget > ( ) ; if ( ! STI . isThumb1Only ( ) ) return ARMBaseRegisterInfo :: saveScavengerRegister ( MBB , I , UseMI , RC , Reg ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; DebugLoc DL ; BuildMI ( MBB , I , DL , TII . get ( ARM :: tMOVr ) ) . addReg ( ARM :: R12 , RegState :: Define ) . addReg ( Reg , RegState :: Kill ) . add ( predOps ( ARMCC :: AL ) ) ; bool done = false ; for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { if ( II -> isDebugValue ( ) ) continue ; for ( unsigned i = 0 , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( ARM :: R12 ) ) { UseMI = II ; done = true ; break ; } if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == ARM :: R12 ) { UseMI = II ; done = true ; break ; } } } BuildMI ( MBB , UseMI , DL , TII . get ( ARM :: tMOVr ) ) . addReg ( Reg , RegState :: Define ) . addReg ( ARM :: R12 , RegState :: Kill ) . add ( predOps ( ARMCC :: AL ) ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .


<s> void SIInstrInfo :: legalizeOpWithMove ( MachineInstr & MI , unsigned OpIdx ) const { MachineBasicBlock :: iterator I = MI ; MachineBasicBlock * MBB = MI . getParent ( ) ; MachineOperand & MO = MI . getOperand ( OpIdx ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; unsigned RCID = get ( MI . getOpcode ( ) ) . OpInfo [ OpIdx ] . RegClass ; const TargetRegisterClass * RC = RI . getRegClass ( RCID ) ; unsigned Size = RI . getRegSizeInBits ( * RC ) ; unsigned Opcode = ( Size == 64 ) ? AMDGPU :: V_MOV_B64_PSEUDO : AMDGPU :: V_MOV_B32_e32 ; if ( MO . isReg ( ) ) Opcode = AMDGPU :: COPY ; else if ( RI . isSGPRClass ( RC ) ) Opcode = ( Size == 64 ) ? AMDGPU :: S_MOV_B64 : AMDGPU :: S_MOV_B32 ; const TargetRegisterClass * VRC = RI . getEquivalentVGPRClass ( RC ) ; const TargetRegisterClass * VRC64 = RI . getVGPR64Class ( ) ; if ( RI . getCommonSubClass ( VRC64 , VRC ) ) VRC = VRC64 ; else VRC = & AMDGPU :: VGPR_32RegClass ; Register Reg = MRI . createVirtualRegister ( VRC ) ; DebugLoc DL = MBB -> findDebugLoc ( I ) ; BuildMI ( * MI . getParent ( ) , I , DL , get ( Opcode ) , Reg ) . add ( MO ) ; MO . ChangeToRegister ( Reg , false ) ; } </s>

Legalize the OpIndex operand of this instruction by inserting a MOV .


"accessing thread-local storage is not currently supported "

"with %<-mpure-code%> or %<-mslow-flash-data%>"

Return TRUE if X contains any TLS symbol references .


<s> SDValue AMDGPUTargetLowering :: SplitVectorLoad ( const SDValue Op , SelectionDAG & DAG ) const { LoadSDNode * Load = cast < LoadSDNode > ( Op ) ; EVT VT = Op . getValueType ( ) ; SDLoc SL ( Op ) ; if ( VT . getVectorNumElements ( ) == 2 ) { SDValue Ops [ 2 ] ; std :: tie ( Ops [ 0 ] , Ops [ 1 ] ) = scalarizeVectorLoad ( Load , DAG ) ; return DAG . getMergeValues ( Ops , SL ) ; } SDValue BasePtr = Load -> getBasePtr ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; const MachinePointerInfo & SrcValue = Load -> getMemOperand ( ) -> getPointerInfo ( ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = getSplitDestVTs ( VT , DAG ) ; std :: tie ( LoMemVT , HiMemVT ) = getSplitDestVTs ( MemVT , DAG ) ; std :: tie ( Lo , Hi ) = splitVector ( Op , SL , LoVT , HiVT , DAG ) ; unsigned Size = LoMemVT . getStoreSize ( ) ; unsigned BaseAlign = Load -> getAlignment ( ) ; unsigned HiAlign = MinAlign ( BaseAlign , Size ) ; SDValue LoLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , LoVT , Load -> getChain ( ) , BasePtr , SrcValue , LoMemVT , BaseAlign , Load -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue HiPtr = DAG . getObjectPtrOffset ( SL , BasePtr , TypeSize :: Fixed ( Size ) ) ; SDValue HiLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , HiVT , Load -> getChain ( ) , HiPtr , SrcValue . getWithOffset ( LoMemVT . getStoreSize ( ) ) , HiMemVT , HiAlign , Load -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Join ; if ( LoVT == HiVT ) { Join = DAG . getNode ( ISD :: CONCAT_VECTORS , SL , VT , LoLoad , HiLoad ) ; } else { Join = DAG . getNode ( ISD :: INSERT_SUBVECTOR , SL , VT , DAG . getUNDEF ( VT ) , LoLoad , DAG . getVectorIdxConstant ( 0 , SL ) ) ; Join = DAG . getNode ( HiVT . isVector ( ) ? ISD :: INSERT_SUBVECTOR : ISD :: INSERT_VECTOR_ELT , SL , VT , Join , HiLoad , DAG . getVectorIdxConstant ( LoVT . getVectorNumElements ( ) , SL ) ) ; } SDValue Ops [ ] = { Join , DAG . getNode ( ISD :: TokenFactor , SL , MVT :: Other , LoLoad . getValue ( 1 ) , HiLoad . getValue ( 1 ) ) } ; return DAG . getMergeValues ( Ops , SL ) ; } </s>

Split a vector load into 2 loads of half the vector .


<s> static int nios2_arg_partial_bytes ( cumulative_args_t cum_v , machine_mode mode , tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; HOST_WIDE_INT param_size ; if ( mode == BLKmode ) { param_size = int_size_in_bytes ( type ) ; gcc_assert ( param_size >= 0 ) ; } else param_size = GET_MODE_SIZE ( mode ) ; param_size = ( UNITS_PER_WORD - 1 + param_size ) / UNITS_PER_WORD ; if ( cum -> regs_used < NUM_ARG_REGS && cum -> regs_used + param_size > NUM_ARG_REGS ) return ( NUM_ARG_REGS - cum -> regs_used ) * UNITS_PER_WORD ; return 0 ; } </s>

Return number of bytes , at the beginning of the argument , that must be put in registers . 0 is the argument is entirely in registers or entirely in memory .


<s> const char * mangle_builtin_type ( const_tree type ) { if ( TYPE_NAME ( type ) && TREE_CODE ( TYPE_NAME ( type ) ) == TYPE_DECL ) type = TREE_TYPE ( TYPE_NAME ( type ) ) ; if ( tree attr = lookup_vector_type_attribute ( type ) ) if ( tree id = TREE_VALUE ( chain_index ( 0 , TREE_VALUE ( attr ) ) ) ) return IDENTIFIER_POINTER ( id ) ; return NULL ; } </s>

If TYPE is a built-in type defined by the RVV ABI , return the mangled name , otherwise return NULL .


<s>
bool
GBZ80FrameLowering
::
restoreCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
if
(
CSI
.
empty
(
)
)
{
return
false
;
}
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
GBZ80Subtarget
&
STI
=
MF
.
getSubtarget
<
GBZ80Subtarget
>
(
)
;
const
TargetInstrInfo
&
TII
=
*
STI
.
getInstrInfo
(
)
;
for
(
const
CalleeSavedInfo
&
CCSI
:
CSI
)
{
unsigned
Reg
=
CCSI
.
getReg
(
)
;
assert
(
TRI
->
getRegSizeInBits
(
*
TRI
->
getMinimalPhysRegClass
(
Reg
)
)
==
16
&&
"Invalid register size"
)
;
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
GB
::
POP
)
,
Reg
)
.
setMIFlag
(
MachineInstr
::
FrameDestroy
)
;
}
return
true
;
}
</s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .

GBZ80
GB
GB
GB
16
"Invalid register size"
GB::POP


<s> const char * PPCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case PPCISD :: FSEL : return "PPCISD::FSEL" ; case PPCISD :: FCFID : return "PPCISD::FCFID" ; case PPCISD :: FCTIDZ : return "PPCISD::FCTIDZ" ; case PPCISD :: FCTIWZ : return "PPCISD::FCTIWZ" ; case PPCISD :: FRE : return "PPCISD::FRE" ; case PPCISD :: FRSQRTE : return "PPCISD::FRSQRTE" ; case PPCISD :: STFIWX : return "PPCISD::STFIWX" ; case PPCISD :: VMADDFP : return "PPCISD::VMADDFP" ; case PPCISD :: VNMSUBFP : return "PPCISD::VNMSUBFP" ; case PPCISD :: VPERM : return "PPCISD::VPERM" ; case PPCISD :: Hi : return "PPCISD::Hi" ; case PPCISD :: Lo : return "PPCISD::Lo" ; case PPCISD :: TOC_ENTRY : return "PPCISD::TOC_ENTRY" ; case PPCISD :: TOC_RESTORE : return "PPCISD::TOC_RESTORE" ; case PPCISD :: LOAD : return "PPCISD::LOAD" ; case PPCISD :: LOAD_TOC : return "PPCISD::LOAD_TOC" ; case PPCISD :: DYNALLOC : return "PPCISD::DYNALLOC" ; case PPCISD :: GlobalBaseReg : return "PPCISD::GlobalBaseReg" ; case PPCISD :: SRL : return "PPCISD::SRL" ; case PPCISD :: SRA : return "PPCISD::SRA" ; case PPCISD :: SHL : return "PPCISD::SHL" ; case PPCISD :: CALL : return "PPCISD::CALL" ; case PPCISD :: CALL_NOP : return "PPCISD::CALL_NOP" ; case PPCISD :: MTCTR : return "PPCISD::MTCTR" ; case PPCISD :: BCTRL : return "PPCISD::BCTRL" ; case PPCISD :: RET_FLAG : return "PPCISD::RET_FLAG" ; case PPCISD :: EH_SJLJ_SETJMP : return "PPCISD::EH_SJLJ_SETJMP" ; case PPCISD :: EH_SJLJ_LONGJMP : return "PPCISD::EH_SJLJ_LONGJMP" ; case PPCISD :: MFCR : return "PPCISD::MFCR" ; case PPCISD :: VCMP : return "PPCISD::VCMP" ; case PPCISD :: VCMPo : return "PPCISD::VCMPo" ; case PPCISD :: LBRX : return "PPCISD::LBRX" ; case PPCISD :: STBRX : return "PPCISD::STBRX" ; case PPCISD :: LARX : return "PPCISD::LARX" ; case PPCISD :: STCX : return "PPCISD::STCX" ; case PPCISD :: COND_BRANCH : return "PPCISD::COND_BRANCH" ; case PPCISD :: BDNZ : return "PPCISD::BDNZ" ; case PPCISD :: BDZ : return "PPCISD::BDZ" ; case PPCISD :: MFFS : return "PPCISD::MFFS" ; case PPCISD :: FADDRTZ : return "PPCISD::FADDRTZ" ; case PPCISD :: TC_RETURN : return "PPCISD::TC_RETURN" ; case PPCISD :: CR6SET : return "PPCISD::CR6SET" ; case PPCISD :: CR6UNSET : return "PPCISD::CR6UNSET" ; case PPCISD :: ADDIS_TOC_HA : return "PPCISD::ADDIS_TOC_HA" ; case PPCISD :: LD_TOC_L : return "PPCISD::LD_TOC_L" ; case PPCISD :: ADDI_TOC_L : return "PPCISD::ADDI_TOC_L" ; case PPCISD :: ADDIS_GOT_TPREL_HA : return "PPCISD::ADDIS_GOT_TPREL_HA" ; case PPCISD :: LD_GOT_TPREL_L : return "PPCISD::LD_GOT_TPREL_L" ; case PPCISD :: ADD_TLS : return "PPCISD::ADD_TLS" ; case PPCISD :: ADDIS_TLSGD_HA : return "PPCISD::ADDIS_TLSGD_HA" ; case PPCISD :: ADDI_TLSGD_L : return "PPCISD::ADDI_TLSGD_L" ; case PPCISD :: GET_TLS_ADDR : return "PPCISD::GET_TLS_ADDR" ; case PPCISD :: ADDIS_TLSLD_HA : return "PPCISD::ADDIS_TLSLD_HA" ; case PPCISD :: ADDI_TLSLD_L : return "PPCISD::ADDI_TLSLD_L" ; case PPCISD :: GET_TLSLD_ADDR : return "PPCISD::GET_TLSLD_ADDR" ; case PPCISD :: ADDIS_DTPREL_HA : return "PPCISD::ADDIS_DTPREL_HA" ; case PPCISD :: ADDI_DTPREL_L : return "PPCISD::ADDI_DTPREL_L" ; case PPCISD :: VADD_SPLAT : return "PPCISD::VADD_SPLAT" ; case PPCISD :: SC : return "PPCISD::SC" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> const char * mips_output_tls_reloc_directive ( rtx * addr ) { enum mips_symbol_type type ; type = mips_classify_symbolic_expression ( * addr , SYMBOL_CONTEXT_LEA ) ; * addr = mips_strip_unspec_address ( * addr ) ; switch ( type ) { case SYMBOL_DTPREL : return Pmode == SImode ? ".dtprelword\t%0" : ".dtpreldword\t%0" ; case SYMBOL_TPREL : return Pmode == SImode ? ".tprelword\t%0" : ".tpreldword\t%0" ; default : gcc_unreachable ( ) ; } } </s>

Return the pseudo-op for full SYMBOL_ ( D ) TPREL address * ADDR . Update * ADDR with the operand that should be printed .


<s> MachineBasicBlock :: iterator Thumb1FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const Thumb1InstrInfo & TII = * static_cast < const Thumb1InstrInfo * > ( STI . getInstrInfo ( ) ) ; const ThumbRegisterInfo * RegInfo = static_cast < const ThumbRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr & Old = * I ; DebugLoc dl = Old . getDebugLoc ( ) ; unsigned Amount = TII . getFrameSize ( Old ) ; if ( Amount != 0 ) { Amount = alignTo ( Amount , getStackAlign ( ) ) ; unsigned Opc = Old . getOpcode ( ) ; if ( Opc == ARM :: ADJCALLSTACKDOWN || Opc == ARM :: tADJCALLSTACKDOWN ) { emitCallSPUpdate ( MBB , I , TII , dl , * RegInfo , - Amount ) ; } else { assert ( Opc == ARM :: ADJCALLSTACKUP || Opc == ARM :: tADJCALLSTACKUP ) ; emitCallSPUpdate ( MBB , I , TII , dl , * RegInfo , Amount ) ; } } } return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

ARM 0 ARM::ADJCALLSTACKDOWN ARM::tADJCALLSTACKDOWN ARM::ADJCALLSTACKUP ARM::tADJCALLSTACKUP


<s> static void s390_split_branches ( void ) { rtx temp_reg = gen_rtx_REG ( Pmode , RETURN_REGNUM ) ; rtx insn , pat , label , target , jump , tmp ; if ( TARGET_64BIT ) return ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( GET_CODE ( insn ) != JUMP_INSN ) continue ; pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) != SET ) continue ; if ( GET_CODE ( SET_SRC ( pat ) ) == LABEL_REF ) { label = SET_SRC ( pat ) ; } else if ( GET_CODE ( SET_SRC ( pat ) ) == IF_THEN_ELSE ) { if ( GET_CODE ( XEXP ( SET_SRC ( pat ) , 1 ) ) == LABEL_REF ) label = XEXP ( SET_SRC ( pat ) , 1 ) ; else if ( GET_CODE ( XEXP ( SET_SRC ( pat ) , 2 ) ) == LABEL_REF ) label = XEXP ( SET_SRC ( pat ) , 2 ) ; else continue ; } else continue ; if ( get_attr_length ( insn ) == 4 ) continue ; if ( flag_pic ) { target = gen_rtx_UNSPEC ( SImode , gen_rtvec ( 1 , label ) , 100 ) ; target = gen_rtx_CONST ( SImode , target ) ; target = force_const_mem ( SImode , target ) ; jump = gen_rtx_REG ( Pmode , BASE_REGISTER ) ; jump = gen_rtx_PLUS ( Pmode , jump , temp_reg ) ; } else { target = force_const_mem ( Pmode , label ) ; jump = temp_reg ; } if ( GET_CODE ( SET_SRC ( pat ) ) == IF_THEN_ELSE ) { if ( GET_CODE ( XEXP ( SET_SRC ( pat ) , 1 ) ) == LABEL_REF ) jump = gen_rtx_IF_THEN_ELSE ( VOIDmode , XEXP ( SET_SRC ( pat ) , 0 ) , jump , pc_rtx ) ; else jump = gen_rtx_IF_THEN_ELSE ( VOIDmode , XEXP ( SET_SRC ( pat ) , 0 ) , pc_rtx , jump ) ; } tmp = emit_insn_before ( gen_rtx_SET ( Pmode , temp_reg , target ) , insn ) ; INSN_ADDRESSES_NEW ( tmp , - 1 ) ; tmp = emit_jump_insn_before ( gen_rtx_SET ( VOIDmode , pc_rtx , jump ) , insn ) ; INSN_ADDRESSES_NEW ( tmp , - 1 ) ; remove_insn ( insn ) ; insn = tmp ; } } </s>

Split all branches that exceed the maximum distance . Returns true if this created a new literal pool entry .


<s> static bool ix86_rop_should_change_byte_p ( int t ) { return t == 0xc2 || t == 0xc3 || t == 0xca || t == 0xcb ; } </s>

Return true if T is one of the bytes we should avoid with -mmitigate-rop .


"Function has local memory argument.  Promoting to "

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static rtx c6x_dwarf_register_span ( rtx rtl ) { unsigned regno ; unsigned real_regno ; int nregs ; int i ; rtx p ; regno = REGNO ( rtl ) ; nregs = HARD_REGNO_NREGS ( regno , GET_MODE ( rtl ) ) ; if ( nregs == 1 ) return NULL_RTX ; p = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nregs ) ) ; for ( i = 0 ; i < nregs ; i ++ ) { if ( TARGET_BIG_ENDIAN ) real_regno = regno + nregs - ( i + 1 ) ; else real_regno = regno + i ; XVECEXP ( p , 0 , i ) = gen_rtx_REG ( SImode , real_regno ) ; } return p ; } </s>

We save pairs of registers using a DImode store . Describe the component registers for DWARF generation code .


";; [Global] Removing membar %d since order of accesses"

See if MEMBAR , the last membar instruction in BB , can be removed . FIRST_IO [ X ] describes the first operation performed by basic block X .


Return the assembly code for INSN , which branches to OPERANDS [ 0 ] if some equality condition is true . The condition is given by OPERANDS [ 1 ] if ! INVERTED_P , otherwise it is the inverse of OPERANDS [ 1 ] . OPERANDS [ 2 ] is the comparison 's first operand ; OPERANDS [ 3 ] is the second operand and may be zero or a register .


<s> void MipsInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { switch ( MI -> getOpcode ( ) ) { default : break ; case Mips :: RDHWR : case Mips :: RDHWR64 : O << "\t.set\tpush\n" ; O << "\t.set\tmips32r2\n" ; } if ( ! printAliasInstr ( MI , O ) && ! printAlias ( * MI , O ) ) printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; switch ( MI -> getOpcode ( ) ) { default : break ; case Mips :: RDHWR : case Mips :: RDHWR64 : O << "\n\t.set\tpop" ; } } </s>

Print the specified MCInst to the specified raw_ostream .


<s> void AAPMCCodeEmitter :: encodeInstruction ( MCInst const & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , MCSubtargetInfo const & STI ) const { const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; uint64_t Binary = getBinaryCodeForInstr ( MI , Fixups , STI ) ; emitLittleEndian ( Binary , OS , Desc . getSize ( ) ) ; ++ MCNumEmitted ; } </s>

Encode the given Inst to bytes and append to CB .


"Expected integer or floating type for store"

Store the specified register of the given register class to the specified stack frame index .


<s> static bool loongarch_frame_pointer_required ( void ) { if ( cfun -> calls_alloca ) return true ; return false ; } </s>


<s> void rs6000_emit_sCOND ( enum rtx_code code , rtx result ) { rtx condition_rtx ; enum machine_mode op_mode ; enum rtx_code cond_code ; condition_rtx = rs6000_generate_compare ( code ) ; cond_code = GET_CODE ( condition_rtx ) ; if ( TARGET_E500 && rs6000_compare_fp_p && ! TARGET_FPRS && TARGET_HARD_FLOAT ) { rtx t ; PUT_MODE ( condition_rtx , SImode ) ; t = XEXP ( condition_rtx , 0 ) ; gcc_assert ( cond_code == NE || cond_code == EQ ) ; if ( cond_code == NE ) emit_insn ( gen_e500_flip_gt_bit ( t , t ) ) ; emit_insn ( gen_move_from_CR_gt_bit ( result , t ) ) ; return ; } if ( cond_code == NE || cond_code == GE || cond_code == LE || cond_code == GEU || cond_code == LEU || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE ) { rtx not_result = gen_reg_rtx ( CCEQmode ) ; rtx not_op , rev_cond_rtx ; enum machine_mode cc_mode ; cc_mode = GET_MODE ( XEXP ( condition_rtx , 0 ) ) ; rev_cond_rtx = gen_rtx_fmt_ee ( rs6000_reverse_condition ( cc_mode , cond_code ) , SImode , XEXP ( condition_rtx , 0 ) , const0_rtx ) ; not_op = gen_rtx_COMPARE ( CCEQmode , rev_cond_rtx , const0_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , not_result , not_op ) ) ; condition_rtx = gen_rtx_EQ ( VOIDmode , not_result , const0_rtx ) ; } op_mode = GET_MODE ( rs6000_compare_op0 ) ; if ( op_mode == VOIDmode ) op_mode = GET_MODE ( rs6000_compare_op1 ) ; if ( TARGET_POWERPC64 && ( op_mode == DImode || rs6000_compare_fp_p ) ) { PUT_MODE ( condition_rtx , DImode ) ; convert_move ( result , condition_rtx , 0 ) ; } else { PUT_MODE ( condition_rtx , SImode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , result , condition_rtx ) ) ; } } </s>


<s> MachineInstr * X86InstrInfo :: optimizeLoadInstr ( MachineInstr * MI , const MachineRegisterInfo * MRI , unsigned & FoldAsLoadDefReg , MachineInstr * & DefMI ) const { if ( FoldAsLoadDefReg == 0 ) return nullptr ; if ( MI -> mayLoad ( ) ) { FoldAsLoadDefReg = 0 ; return nullptr ; } DefMI = MRI -> getVRegDef ( FoldAsLoadDefReg ) ; assert ( DefMI ) ; bool SawStore = false ; if ( ! DefMI -> isSafeToMove ( this , nullptr , SawStore ) ) return nullptr ; unsigned SrcOperandId = 0 ; bool FoundSrcOperand = false ; for ( unsigned i = 0 , e = MI -> getDesc ( ) . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg != FoldAsLoadDefReg ) continue ; if ( MO . getSubReg ( ) || MO . isDef ( ) || FoundSrcOperand ) return nullptr ; SrcOperandId = i ; FoundSrcOperand = true ; } if ( ! FoundSrcOperand ) return nullptr ; MachineInstr * FoldMI = foldMemoryOperand ( MI , SrcOperandId , DefMI ) ; if ( FoldMI ) { FoldAsLoadDefReg = 0 ; return FoldMI ; } return nullptr ; } </s>

optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use .


<s>
static
GlobalVariable
*
getGlobalVariable
(
Module
&
M
,
Type
*
Ty
,
WebAssemblyTargetMachine
&
TM
,
const
char
*
Name
)
{
auto
*
GV
=
dyn_cast
<
GlobalVariable
>
(
M
.
getOrInsertGlobal
(
Name
,
Ty
)
)
;
if
(
!
GV
)
report_fatal_error
(
Twine
(
"unable to create global: "
)
+
Name
)
;
auto
*
Subtarget
=
TM
.
getSubtargetImpl
(
)
;
auto
TLS
=
Subtarget
->
hasAtomics
(
)
&&
Subtarget
->
hasBulkMemory
(
)
GlobalValue
::
LocalExecTLSModel
:
GlobalValue
::
NotThreadLocal
;
GV
->
setThreadLocalMode
(
TLS
)
;
return
GV
;
}
</s>

getGlobalVariable - Look up the specified global variable in the module symbol table .

WebAssembly
WebAssembly
"unable to create global: "


"fixup_CHERI_CAPABILITY shouldn't happen here!"

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
StringRef
getPassName
(
)
const
override
{
return
"PPC Generate Scalar MASS Entries"
;
}
</s>

getPassName - Return a nice clean name for a pass .

PowerPC
"PPC Generate Scalar MASS Entries"


<s> unsigned X86InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( isFrameStoreOpcode ( MI -> getOpcode ( ) ) ) if ( isFrameOperand ( MI , 0 , FrameIndex ) ) return MI -> getOperand ( X86AddrNumOperands ) . getReg ( ) ; return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> unsigned WebAssemblyTTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: TargetCostKind CostKind , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args , const Instruction * CxtI ) { unsigned Cost = BasicTTIImplBase < WebAssemblyTTIImpl > :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( auto * VTy = dyn_cast < VectorType > ( Ty ) ) { switch ( Opcode ) { case Instruction :: LShr : case Instruction :: AShr : case Instruction :: Shl : if ( Opd2Info != TTI :: OK_UniformValue && Opd2Info != TTI :: OK_UniformConstantValue ) Cost = VTy -> getNumElements ( ) * ( TargetTransformInfo :: TCC_Basic + getArithmeticInstrCost ( Opcode , VTy -> getElementType ( ) , CostKind ) + TargetTransformInfo :: TCC_Basic ) ; break ; } } return Cost ; } </s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> void RISCVPassConfig :: addPreEmitPass2 ( ) { addPass ( createRISCVExpandPseudoPass ( ) ) ; addPass ( createRISCVExpandAtomicPseudoPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createRISCVExpandCoreVHwlpPseudoPass ( ) ) ; } } </s>

Targets may add passes immediately before machine code is emitted in this callback .


<s> bool X86FastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { const Value * Ptr = LI -> getPointerOperand ( ) ; X86AddressMode AM ; if ( ! X86SelectAddress ( Ptr , AM ) ) return false ; const X86InstrInfo & XII = ( const X86InstrInfo & ) TII ; unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; unsigned Alignment = LI -> getAlignment ( ) ; if ( Alignment == 0 ) Alignment = DL . getABITypeAlignment ( LI -> getType ( ) ) ; SmallVector < MachineOperand , 8 > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , * MI , OpNo , AddrOps , FuncInfo . InsertPt , Size , Alignment , true ) ; if ( ! Result ) return false ; unsigned OperandNo = 0 ; for ( MachineInstr :: mop_iterator I = Result -> operands_begin ( ) , E = Result -> operands_end ( ) ; I != E ; ++ I , ++ OperandNo ) { MachineOperand & MO = * I ; if ( ! MO . isReg ( ) || MO . isDef ( ) || MO . getReg ( ) != AM . IndexReg ) continue ; unsigned IndexReg = constrainOperandRegClass ( Result -> getDesc ( ) , MO . getReg ( ) , OperandNo ) ; if ( IndexReg == MO . getReg ( ) ) continue ; MO . setReg ( IndexReg ) ; } Result -> addMemOperand ( * FuncInfo . MF , createMachineMemOperandFor ( LI ) ) ; MachineBasicBlock :: iterator I ( MI ) ; removeDeadCode ( I , std :: next ( I ) ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> std :: pair < unsigned , const TargetRegisterClass * > PPCTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'b' : if ( VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RC_NOX0RegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRC_NOR0RegClass ) ; case 'r' : if ( VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RCRegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRCRegClass ) ; case 'f' : if ( VT == MVT :: f32 || VT == MVT :: i32 ) return std :: make_pair ( 0U , & PPC :: F4RCRegClass ) ; if ( VT == MVT :: f64 || VT == MVT :: i64 ) return std :: make_pair ( 0U , & PPC :: F8RCRegClass ) ; break ; case 'v' : return std :: make_pair ( 0U , & PPC :: VRRCRegClass ) ; case 'y' : return std :: make_pair ( 0U , & PPC :: CRRCRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> ix86_dependencies_evaluation_hook static int ix86_reassociation_width ( unsigned int op , machine_mode mode ) { int width = 1 ; if ( VECTOR_MODE_P ( mode ) ) { int div = 1 ; if ( INTEGRAL_MODE_P ( mode ) ) width = ix86_cost -> reassoc_vec_int ; else if ( FLOAT_MODE_P ( mode ) ) width = ix86_cost -> reassoc_vec_fp ; if ( width == 1 ) return 1 ; if ( ( ix86_tune == PROCESSOR_ZNVER1 || ix86_tune == PROCESSOR_ZNVER2 || ix86_tune == PROCESSOR_ZNVER3 || ix86_tune == PROCESSOR_ZNVER4 ) && INTEGRAL_MODE_P ( mode ) && op != PLUS && op != MINUS ) return 1 ; if ( TARGET_AVX512_SPLIT_REGS && GET_MODE_BITSIZE ( mode ) > 256 ) div = GET_MODE_BITSIZE ( mode ) / 256 ; else if ( TARGET_AVX256_SPLIT_REGS && GET_MODE_BITSIZE ( mode ) > 128 ) div = GET_MODE_BITSIZE ( mode ) / 128 ; else if ( TARGET_SSE_SPLIT_REGS && GET_MODE_BITSIZE ( mode ) > 64 ) div = GET_MODE_BITSIZE ( mode ) / 64 ; width = ( width + div - 1 ) / div ; } else if ( INTEGRAL_MODE_P ( mode ) ) width = ix86_cost -> reassoc_int ; else if ( FLOAT_MODE_P ( mode ) ) width = ix86_cost -> reassoc_fp ; if ( ! TARGET_64BIT && width > 2 ) width = 2 ; return width ; } </s>

Implementation of reassociation_width target hook used by reassoc phase to identify parallelism level in reassociated tree . Statements tree_code is passed in OPC . Arguments type is passed in MODE . Currently parallel reassociation is enabled for Atom processors only and we set reassociation width to be 2 because Atom may issue up to 2 instructions per cycle . Return value should be fixed if parallel reassociation is enabled for other processors .


<s> unsigned AVRInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { case AVR :: LDDRdPtrQ : case AVR :: LDDWRdYQ : { if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } default : break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> bool check_builtin_call ( location_t location , vec < location_t > , unsigned int code , tree fndecl , unsigned int nargs , tree * args ) { const registered_function & rfn = * ( * registered_functions ) [ code ] ; return function_checker ( location , rfn . instance , fndecl , TREE_TYPE ( rfn . decl ) , nargs , args ) . check ( ) ; } </s>

Perform any semantic checks needed for a call to the SVE function with subcode CODE , such as testing for integer constant expressions . The call occurs at location LOCATION and has NARGS arguments , given by ARGS . FNDECL is the original function decl , before overload resolution . Return true if the call is valid , otherwise report a suitable error .


<s> const SparcRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static void rs6000_override_options_after_change ( void ) { if ( ( OPTION_SET_P ( flag_unroll_loops ) && flag_unroll_loops ) || ( OPTION_SET_P ( flag_unroll_all_loops ) && flag_unroll_all_loops ) ) { if ( ! OPTION_SET_P ( unroll_only_small_loops ) ) unroll_only_small_loops = 0 ; if ( ! OPTION_SET_P ( flag_rename_registers ) ) flag_rename_registers = 1 ; if ( ! OPTION_SET_P ( flag_cunroll_grow_size ) ) flag_cunroll_grow_size = 1 ; } else if ( ! OPTION_SET_P ( flag_cunroll_grow_size ) ) flag_cunroll_grow_size = flag_peel_loops || optimize >= 3 ; if ( rs6000_rop_protect ) flag_shrink_wrap = 0 ; } </s>

This target function is similar to the hook TARGET_OPTION_OVERRIDE but is called when the optimize level is changed via an attribute or pragma or when it is reset at the end of the code affected by the attribute or pragma . It is not called at the beginning of compilation when TARGET_OPTION_OVERRIDE is called so if you want to perform these actions then , you should have TARGET_OPTION_OVERRIDE call TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE .


<s>
SDValue
BlackfinTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
Op
.
getNode
(
)
->
dump
(
)
;
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
llvm_unreachable
(
"TLS not implemented for Blackfin."
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
SDValue
(
)
;
case
ISD
::
RETURNADDR
:
return
SDValue
(
)
;
case
ISD
::
ADDE
:
case
ISD
::
SUBE
:
return
LowerADDE
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

Blackfin
"Should not custom lower this!"
ISD::GlobalAddress
ISD::GlobalTLSAddress
"TLS not implemented for Blackfin."
ISD::JumpTable
ISD::FRAMEADDR
ISD::RETURNADDR
ISD::ADDE
ISD::SUBE


<s>
void
pa_output_function_label
(
FILE
*
file
)
{
ASM_OUTPUT_LABEL
(
file
,
XSTR
(
XEXP
(
DECL_RTL
(
current_function_decl
)
,
0
)
,
0
)
)
;
fputs
(
"\t.PROC\n"
,
file
)
;
fprintf
(
file
,
"\t.CALLINFO FRAME="
HOST_WIDE_INT_PRINT_DEC
,
actual_fsize
)
;
if
(
crtl
->
is_leaf
)
fputs
(
",NO_CALLS"
,
file
)
;
else
fputs
(
",CALLS"
,
file
)
;
if
(
rp_saved
)
fputs
(
",SAVE_RP"
,
file
)
;
if
(
frame_pointer_needed
)
fputs
(
",SAVE_SP"
,
file
)
;
if
(
gr_saved
)
fprintf
(
file
,
",ENTRY_GR=%d"
,
gr_saved
+
2
)
;
if
(
fr_saved
)
fprintf
(
file
,
",ENTRY_FR=%d"
,
fr_saved
+
11
)
;
fputs
(
"\n\t.ENTRY\n"
,
file
)
;
}
</s>

Output function label , and associated .PROC and .CALLINFO statements .


<s>
DecodeStatus
RV16KDisassembler
::
getInstruction
(
MCInst
&
MI
,
uint64_t
&
Size
,
ArrayRef
<
uint8_t
>
Bytes
,
uint64_t
Address
,
raw_ostream
&
OS
,
raw_ostream
&
CS
)
const
{
if
(
Bytes
.
size
(
)
<
2
)
{
Size
=
0
;
return
MCDisassembler
::
Fail
;
}
uint32_t
Inst
;
DecodeStatus
Result
;
uint8_t
bit15
=
Bytes
[
1
]
>>
7
,
bit14
=
(
Bytes
[
1
]
>>
6
)
&
1
,
bit12
=
(
Bytes
[
1
]
>>
4
)
&
1
;
uint8_t
isNIAI
=
(
bit15
^
bit14
)
&
bit12
;
if
(
isNIAI
)
{
if
(
Bytes
.
size
(
)
<
4
)
{
Size
=
0
;
return
MCDisassembler
::
Fail
;
}
Inst
=
support
::
endian
::
read32le
(
Bytes
.
data
(
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Trying RV16K 32bit table :\n"
)
;
Result
=
decodeInstruction
(
DecoderTable32
,
MI
,
Inst
,
Address
,
this
,
STI
)
;
Size
=
4
;
}
else
{
if
(
Bytes
.
size
(
)
<
2
)
{
Size
=
0
;
return
MCDisassembler
::
Fail
;
}
Inst
=
support
::
endian
::
read16le
(
Bytes
.
data
(
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Trying RV16K 16bit table :\n"
)
;
Result
=
decodeInstruction
(
DecoderTable16
,
MI
,
Inst
,
Address
,
this
,
STI
)
;
Size
=
2
;
}
return
Result
;
}
</s>

Returns the disassembly of a single instruction .


<s> const MachineBasicBlock * getMBB ( ) const { return MBB ; } </s>

Return a reference to the basic block containing this bundle .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"AArch64 Redundant Copy Elimination"
;
}
</s>


<s>
void
MipsCodeEmitter
::
emitInstruction
(
const
MachineInstr
&
MI
)
{
DEBUG
(
errs
(
)
<<
"JIT: "
<<
(
void
*
)
MCE
.
getCurrentPCValue
(
)
<<
":\t"
<<
MI
)
;
MCE
.
processDebugLoc
(
MI
.
getDebugLoc
(
)
,
true
)
;
if
(
(
MI
.
getDesc
(
)
.
TSFlags
&
MipsII
::
FormMask
)
==
MipsII
::
Pseudo
)
return
;
++
NumEmitted
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
emitWordLE
(
getBinaryCodeForInstr
(
MI
)
)
;
break
;
}
MCE
.
processDebugLoc
(
MI
.
getDebugLoc
(
)
,
false
)
;
}
</s>

Targets should implement this to emit instructions .

Mips
Mips
"JIT: "
":\t"
MipsII::FormMask
MipsII::Pseudo


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( 1 , true , true , false , true ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedLoadCombinePass ( ) ) ; addPass ( createInterleavedAccessPass ( ) ) ; } if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } addPass ( createAArch64StackTaggingPass ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static HOST_WIDE_INT visium_constant_alignment ( const_tree exp , HOST_WIDE_INT align ) { return visium_data_alignment ( TREE_TYPE ( exp ) , align ) ; } </s>


<s>
void
PPCInstrInfo
::
genAlternativeCodeSequence
(
MachineInstr
&
Root
,
MachineCombinerPattern
::
MC_PATTERN
Pattern
,
SmallVectorImpl
<
MachineInstr
*
>
&
InsInstrs
,
SmallVectorImpl
<
MachineInstr
*
>
&
DelInstrs
,
DenseMap
<
unsigned
,
unsigned
>
&
InstIdxForVirtReg
)
const
{
MachineRegisterInfo
&
MRI
=
Root
.
getParent
(
)
->
getParent
(
)
->
getRegInfo
(
)
;
MachineInstr
*
Prev
=
nullptr
;
switch
(
Pattern
)
{
case
MachineCombinerPattern
::
MC_REASSOC_AX_BY
:
case
MachineCombinerPattern
::
MC_REASSOC_XA_BY
:
Prev
=
MRI
.
getUniqueVRegDef
(
Root
.
getOperand
(
1
)
.
getReg
(
)
)
;
break
;
case
MachineCombinerPattern
::
MC_REASSOC_AX_YB
:
case
MachineCombinerPattern
::
MC_REASSOC_XA_YB
:
Prev
=
MRI
.
getUniqueVRegDef
(
Root
.
getOperand
(
2
)
.
getReg
(
)
)
;
}
assert
(
Prev
&&
"Unknown pattern for machine combiner"
)
;
reassociateOps
(
Root
,
*
Prev
,
Pattern
,
InsInstrs
,
DelInstrs
,
InstIdxForVirtReg
)
;
return
;
}
</s>

When getMachineCombinerPatterns ( ) finds potential patterns , this function generates the instructions that could replace the original code sequence .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> BitVector SystemZRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( SystemZ :: R11D ) ; Reserved . set ( SystemZ :: R14D ) ; Reserved . set ( SystemZ :: R15D ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> rtx legitimize_tls_address ( rtx x , rtx reg ) { rtx dest , tp , label , labelno , sum , insns , ret , eqv , addend ; unsigned int model = SYMBOL_REF_TLS_MODEL ( x ) ; switch ( model ) { case TLS_MODEL_GLOBAL_DYNAMIC : insns = arm_call_tls_get_addr ( x , reg , & ret , TLS_GD32 ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , x ) ; return dest ; case TLS_MODEL_LOCAL_DYNAMIC : insns = arm_call_tls_get_addr ( x , reg , & ret , TLS_LDM32 ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , const1_rtx ) , UNSPEC_TLS ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , eqv ) ; addend = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 2 , x , GEN_INT ( TLS_LDO32 ) ) , UNSPEC_TLS ) ; addend = force_reg ( SImode , gen_rtx_CONST ( SImode , addend ) ) ; return gen_rtx_PLUS ( Pmode , dest , addend ) ; case TLS_MODEL_INITIAL_EXEC : labelno = GEN_INT ( pic_labelno ++ ) ; label = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , labelno ) , UNSPEC_PIC_LABEL ) ; label = gen_rtx_CONST ( VOIDmode , label ) ; sum = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 4 , x , GEN_INT ( TLS_IE32 ) , label , GEN_INT ( TARGET_ARM ? 8 : 4 ) ) , UNSPEC_TLS ) ; reg = load_tls_operand ( sum , reg ) ; if ( TARGET_ARM ) emit_insn ( gen_tls_load_dot_plus_eight ( reg , reg , labelno ) ) ; else { emit_insn ( gen_pic_add_dot_plus_four ( reg , reg , labelno ) ) ; emit_move_insn ( reg , gen_const_mem ( SImode , reg ) ) ; } tp = arm_load_tp ( NULL_RTX ) ; return gen_rtx_PLUS ( Pmode , tp , reg ) ; case TLS_MODEL_LOCAL_EXEC : tp = arm_load_tp ( NULL_RTX ) ; reg = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 2 , x , GEN_INT ( TLS_LE32 ) ) , UNSPEC_TLS ) ; reg = force_reg ( SImode , gen_rtx_CONST ( SImode , reg ) ) ; return gen_rtx_PLUS ( Pmode , tp , reg ) ; default : abort ( ) ; } } </s>

ADDR contains a thread-local SYMBOL_REF . Generate code to compute this ( thread-local ) address .


<s> static tree mips_builtin_vector_type ( tree type , machine_mode mode ) { static tree types [ 2 * ( int ) MAX_MACHINE_MODE ] ; int mode_index ; mode_index = ( int ) mode ; if ( TREE_CODE ( type ) == INTEGER_TYPE && TYPE_UNSIGNED ( type ) ) mode_index += MAX_MACHINE_MODE ; if ( types [ mode_index ] == NULL_TREE ) types [ mode_index ] = build_vector_type_for_mode ( type , mode ) ; return types [ mode_index ] ; } </s>

MODE is a vector mode whose elements have type TYPE . Return the type of the vector itself .


<s> const XCoreInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


"instruction requires a CPU feature not currently enabled"

"source and destination must be different"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> bool AArch64TargetLowering :: combineRepeatedFPDivisors ( unsigned NumUsers ) const { return NumUsers > 2 ; } </s>

Indicate whether this target prefers to combine FDIVs with the same divisor .


<s> virtual bool doFinalization ( Module & M ) { return false ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; if ( ! ST . hasHardClauses ( ) ) return false ; const SIInstrInfo * SII = ST . getInstrInfo ( ) ; const TargetRegisterInfo * TRI = ST . getRegisterInfo ( ) ; bool Changed = false ; for ( auto & MBB : MF ) { ClauseInfo CI ; for ( auto & MI : MBB ) { HardClauseType Type = getHardClauseType ( MI ) ; int64_t Dummy1 ; bool Dummy2 ; unsigned Dummy3 ; SmallVector < const MachineOperand * , 4 > BaseOps ; if ( Type <= LAST_REAL_HARDCLAUSE_TYPE ) { if ( ! SII -> getMemOperandsWithOffsetWidth ( MI , BaseOps , Dummy1 , Dummy2 , Dummy3 , TRI ) ) { Type = HARDCLAUSE_ILLEGAL ; } } if ( CI . Length == 64 || ( CI . Length && Type != HARDCLAUSE_INTERNAL && ( Type != CI . Type || ! SII -> shouldClusterMemOps ( CI . BaseOps , BaseOps , 2 , 2 ) ) ) ) { Changed |= emitClause ( CI , SII ) ; CI = ClauseInfo ( ) ; } if ( CI . Length ) { ++ CI . Length ; if ( Type != HARDCLAUSE_INTERNAL ) { CI . Last = & MI ; CI . BaseOps = std :: move ( BaseOps ) ; } } else if ( Type <= LAST_REAL_HARDCLAUSE_TYPE ) { CI = ClauseInfo { Type , & MI , & MI , 1 , std :: move ( BaseOps ) } ; } } if ( CI . Length ) Changed |= emitClause ( CI , SII ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> const uint32_t * SIRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { switch ( CC ) { case CallingConv :: C : case CallingConv :: Fast : case CallingConv :: Cold : case CallingConv :: AMDGPU_Gfx : return CSR_AMDGPU_HighRegs_RegMask ; default : return nullptr ; } } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
void
WebAssemblyDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> std :: string getNodeLabel ( const MCGNode * N , const MCallSubGraph & G ) { if ( N -> isUnknown ( ) ) { std :: string tmp ; raw_string_ostream s ( tmp ) ; s << "<UNKNOWN-" << * N -> getType ( ) << ">" ; return s . str ( ) ; } else return N -> getMF ( ) -> getFunction ( ) -> getName ( ) ; } </s>

Print a DDG node either in concise form ( -ddg-dot-only ) or verbose mode ( -ddg-dot ) .


<s> StringRef getPassName ( ) const override { return "CheriLoopPointerDecanonicalize" ; } </s>

getPassName - Return a nice clean name for a pass .


<s> Value * AArch64TargetLowering :: emitStoreConditional ( IRBuilder < > & Builder , Value * Val , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = isReleaseOrStronger ( Ord ) ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == 128 ) { Intrinsic :: ID Int = IsRelease ? Intrinsic :: aarch64_stlxp : Intrinsic :: aarch64_stxp ; Function * Stxr = Intrinsic :: getDeclaration ( M , Int ) ; Type * Int64Ty = Type :: getInt64Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int64Ty , "lo" ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , 64 ) , Int64Ty , "hi" ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall ( Stxr , { Lo , Hi , Addr } ) ; } Intrinsic :: ID Int = IsRelease ? Intrinsic :: aarch64_stlxr : Intrinsic :: aarch64_stxr ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Stxr = Intrinsic :: getDeclaration ( M , Int , Tys ) ; const DataLayout & DL = M -> getDataLayout ( ) ; IntegerType * IntValTy = Builder . getIntNTy ( DL . getTypeSizeInBits ( Val -> getType ( ) ) ) ; Val = Builder . CreateBitCast ( Val , IntValTy ) ; return Builder . CreateCall ( Stxr , { Builder . CreateZExtOrBitCast ( Val , Stxr -> getFunctionType ( ) -> getParamType ( 0 ) ) , Addr } ) ; } </s>

Perform a store-conditional operation to Addr .


<s>
void
pa_asm_output_aligned_bss
(
FILE
*
stream
,
const
char
*
name
,
unsigned
HOST_WIDE_INT
size
,
unsigned
int
align
)
{
switch_to_section
(
bss_section
)
;
fprintf
(
stream
,
"\t.align %u\n"
,
align
/
BITS_PER_UNIT
)
;
ASM_OUTPUT_TYPE_DIRECTIVE
(
stream
,
name
,
"object"
)
;
ASM_OUTPUT_SIZE_DIRECTIVE
(
stream
,
name
,
size
)
;
fprintf
(
stream
,
"\t.align %u\n"
,
align
/
BITS_PER_UNIT
)
;
ASM_OUTPUT_LABEL
(
stream
,
name
)
;
fprintf
(
stream
,
"\t.block "
HOST_WIDE_INT_PRINT_UNSIGNED
"\n"
,
size
)
;
}
</s>

This function places uninitialized global data in the bss section . The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this function on the SOM port to prevent uninitialized global data from being placed in the data section .

pa
"\t.align %u\n"
"object"
"\t.align %u\n"
"\t.block "
"\n"


<s>
const
char
*
nds32_output_32bit_load
(
rtx
*
operands
,
int
byte
)
{
char
pattern
[
100
]
;
unsigned
char
size
;
rtx
code
;
code
=
XEXP
(
operands
[
1
]
,
0
)
;
size
=
nds32_byte_to_size
(
byte
)
;
switch
(
GET_CODE
(
code
)
)
{
case
REG
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%ci\t%%0, %%1"
,
size
)
;
break
;
case
SYMBOL_REF
:
case
CONST
:
operands
[
1
]
=
XEXP
(
operands
[
1
]
,
0
)
;
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%ci.gp\t%%0, [ + %%1]"
,
size
)
;
break
;
case
POST_INC
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%ci.bi\t%%0, %%1, %d"
,
size
,
byte
)
;
break
;
case
POST_DEC
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%ci.bi\t%%0, %%1, -%d"
,
size
,
byte
)
;
break
;
case
POST_MODIFY
:
switch
(
GET_CODE
(
XEXP
(
XEXP
(
code
,
1
)
,
1
)
)
)
{
case
REG
:
case
SUBREG
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%c.bi\t%%0, %%1"
,
size
)
;
break
;
case
CONST_INT
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%ci.bi\t%%0, %%1"
,
size
)
;
break
;
default
:
abort
(
)
;
}
break
;
case
PLUS
:
switch
(
GET_CODE
(
XEXP
(
code
,
1
)
)
)
{
case
REG
:
case
SUBREG
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%c\t%%0, %%1"
,
size
)
;
break
;
case
CONST_INT
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%ci\t%%0, %%1"
,
size
)
;
break
;
default
:
abort
(
)
;
}
break
;
case
LO_SUM
:
operands
[
2
]
=
XEXP
(
code
,
1
)
;
operands
[
1
]
=
XEXP
(
code
,
0
)
;
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%ci\t%%0, [%%1 + lo12(%%2)]"
,
size
)
;
break
;
default
:
abort
(
)
;
}
output_asm_insn
(
pattern
,
operands
)
;
return
""
;
}
</s>


<s> SDValue AArch64TargetLowering :: getRecipEstimate ( SDValue Operand , DAGCombinerInfo & DCI , unsigned & ExtraSteps ) const { return getEstimate ( * Subtarget , DCI , AArch64ISD :: FRECPE , Operand , ExtraSteps ) ; } </s>

Return a reciprocal estimate value for the input operand .


<s>
MachineInstr
*
ARMBaseInstrInfo
::
optimizeSelect
(
MachineInstr
*
MI
,
bool
PreferFalse
)
const
{
assert
(
(
MI
->
getOpcode
(
)
==
ARM
::
MOVCCr
||
MI
->
getOpcode
(
)
==
ARM
::
t2MOVCCr
)
&&
"Unknown select instruction"
)
;
const
MachineRegisterInfo
&
MRI
=
MI
->
getParent
(
)
->
getParent
(
)
->
getRegInfo
(
)
;
MachineInstr
*
DefMI
=
canFoldIntoMOVCC
(
MI
->
getOperand
(
2
)
.
getReg
(
)
,
MRI
,
this
)
;
bool
Invert
=
!
DefMI
;
if
(
!
DefMI
)
DefMI
=
canFoldIntoMOVCC
(
MI
->
getOperand
(
1
)
.
getReg
(
)
,
MRI
,
this
)
;
if
(
!
DefMI
)
return
0
;
MachineInstrBuilder
NewMI
=
BuildMI
(
*
MI
->
getParent
(
)
,
MI
,
MI
->
getDebugLoc
(
)
,
DefMI
->
getDesc
(
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
;
const
MCInstrDesc
&
DefDesc
=
DefMI
->
getDesc
(
)
;
for
(
unsigned
i
=
1
,
e
=
DefDesc
.
getNumOperands
(
)
;
i
!=
e
&&
!
DefDesc
.
OpInfo
[
i
]
.
isPredicate
(
)
;
++
i
)
NewMI
.
addOperand
(
DefMI
->
getOperand
(
i
)
)
;
unsigned
CondCode
=
MI
->
getOperand
(
3
)
.
getImm
(
)
;
if
(
Invert
)
NewMI
.
addImm
(
ARMCC
::
getOppositeCondition
(
ARMCC
::
CondCodes
(
CondCode
)
)
)
;
else
NewMI
.
addImm
(
CondCode
)
;
NewMI
.
addOperand
(
MI
->
getOperand
(
4
)
)
;
if
(
NewMI
->
hasOptionalDef
(
)
)
AddDefaultCC
(
NewMI
)
;
MachineOperand
FalseReg
=
MI
->
getOperand
(
Invert
2
:
1
)
;
FalseReg
.
setImplicit
(
)
;
NewMI
.
addOperand
(
FalseReg
)
;
NewMI
->
tieOperands
(
0
,
NewMI
->
getNumOperands
(
)
1
)
;
DefMI
->
eraseFromParent
(
)
;
return
NewMI
;
}
</s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


<s> static parse_codes parse_bif ( void ) { parse_codes result ; diag = & bif_diag ; if ( ! advance_line ( bif_file ) ) return PC_OK ; do result = parse_bif_stanza ( ) ; while ( result == PC_OK ) ; if ( result == PC_EOFILE ) return PC_OK ; return result ; } </s>


<s> static bool arc_mode_dependent_address_p ( const_rtx addr , addr_space_t ) { if ( GET_CODE ( addr ) == PLUS && GET_CODE ( XEXP ( ( addr ) , 0 ) ) == MULT ) return true ; return false ; } </s>

Return true iff ADDR ( a legitimate address expression ) has an effect that depends on the machine mode it is used for .


<s> int arm_no_early_alu_shift_dep ( rtx producer , rtx consumer ) { rtx value , op ; rtx early_op ; if ( ! arm_get_set_operands ( producer , consumer , & value , & op ) ) return 0 ; if ( ( early_op = arm_find_shift_sub_rtx ( op ) ) ) { if ( REG_P ( early_op ) ) early_op = op ; return ! reg_overlap_mentioned_p ( value , early_op ) ; } return 0 ; } </s>

Return nonzero if the CONSUMER instruction ( an ALU op ) does not have an early register shift value or amount dependency on the result of PRODUCER .


<s> static bool contains_core_p ( unsigned * arr , unsigned core ) { if ( arr [ 0 ] != INVALID_CORE ) { if ( arr [ 0 ] == core ) return true ; if ( arr [ 1 ] != INVALID_CORE ) return arr [ 1 ] == core ; } return false ; } </s>

Return true iff ARR contains CORE , in either of the two elements .


<s> static void expand_small_movmem_or_setmem ( rtx destmem , rtx srcmem , rtx destptr , rtx srcptr , rtx value , rtx vec_value , rtx count , int size , rtx done_label , bool issetmem ) { rtx_code_label * label = ix86_expand_aligntest ( count , size , false ) ; machine_mode mode = int_mode_for_size ( size * BITS_PER_UNIT , 1 ) . else_blk ( ) ; rtx modesize ; int n ; if ( issetmem ) { if ( ! vec_value ) { if ( GET_MODE ( value ) == VOIDmode && size > 8 ) mode = Pmode ; else if ( GET_MODE_SIZE ( mode ) > GET_MODE_SIZE ( GET_MODE ( value ) ) ) mode = GET_MODE ( value ) ; } else mode = GET_MODE ( vec_value ) , value = vec_value ; } else { if ( size >= 32 ) mode = TARGET_AVX ? V32QImode : TARGET_SSE ? V16QImode : DImode ; else if ( size >= 16 ) mode = TARGET_SSE ? V16QImode : DImode ; srcmem = change_address ( srcmem , mode , srcptr ) ; } destmem = change_address ( destmem , mode , destptr ) ; modesize = GEN_INT ( GET_MODE_SIZE ( mode ) ) ; gcc_assert ( GET_MODE_SIZE ( mode ) <= size ) ; for ( n = 0 ; n * GET_MODE_SIZE ( mode ) < size ; n ++ ) { if ( issetmem ) emit_move_insn ( destmem , gen_lowpart ( mode , value ) ) ; else { emit_move_insn ( destmem , srcmem ) ; srcmem = offset_address ( srcmem , modesize , GET_MODE_SIZE ( mode ) ) ; } destmem = offset_address ( destmem , modesize , GET_MODE_SIZE ( mode ) ) ; } destmem = offset_address ( destmem , count , 1 ) ; destmem = offset_address ( destmem , GEN_INT ( - 2 * size ) , GET_MODE_SIZE ( mode ) ) ; if ( ! issetmem ) { srcmem = offset_address ( srcmem , count , 1 ) ; srcmem = offset_address ( srcmem , GEN_INT ( - 2 * size ) , GET_MODE_SIZE ( mode ) ) ; } for ( n = 0 ; n * GET_MODE_SIZE ( mode ) < size ; n ++ ) { if ( issetmem ) emit_move_insn ( destmem , gen_lowpart ( mode , value ) ) ; else { emit_move_insn ( destmem , srcmem ) ; srcmem = offset_address ( srcmem , modesize , GET_MODE_SIZE ( mode ) ) ; } destmem = offset_address ( destmem , modesize , GET_MODE_SIZE ( mode ) ) ; } emit_jump_insn ( gen_jump ( done_label ) ) ; emit_barrier ( ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; } </s>

Test if COUNT & SIZE is nonzero and if so , expand movme or setmem sequence that is valid for SIZE .. 2 * SIZE-1 bytes and jump to DONE_LABEL .


<s> static rtx save_fpr ( rtx base , int offset , int regnum ) { rtx addr ; rtx insn ; addr = gen_rtx_MEM ( DFmode , plus_constant ( Pmode , base , offset ) ) ; if ( regnum >= FPR0_REGNUM && regnum <= ( FPR0_REGNUM + FP_ARG_NUM_REG ) ) set_mem_alias_set ( addr , get_varargs_alias_set ( ) ) ; else set_mem_alias_set ( addr , get_frame_alias_set ( ) ) ; insn = emit_move_insn ( addr , gen_rtx_REG ( DFmode , regnum ) ) ; if ( ! call_used_regs [ regnum ] || s390_preserve_fpr_arg_p ( regnum ) ) RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( s390_preserve_fpr_arg_p ( regnum ) && ! cfun_fpr_save_p ( regnum ) ) { rtx reg = gen_rtx_REG ( DFmode , regnum ) ; add_reg_note ( insn , REG_CFA_NO_RESTORE , reg ) ; add_reg_note ( insn , REG_CFA_OFFSET , gen_rtx_SET ( addr , reg ) ) ; } return insn ; } </s>

Emit insn to save fpr REGNUM at offset OFFSET relative to register BASE . Return generated insn .


<s>
bool
X86AsmPrinter
::
PrintAsmOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
{
if
(
ExtraCode
[
1
]
!=
0
)
return
true
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNo
)
;
switch
(
ExtraCode
[
0
]
)
{
default
:
return
AsmPrinter
::
PrintAsmOperand
(
MI
,
OpNo
,
AsmVariant
,
ExtraCode
,
O
)
;
case
'a'
:
switch
(
MO
.
getType
(
)
)
{
default
:
return
true
;
case
MachineOperand
::
MO_Immediate
:
O
<<
MO
.
getImm
(
)
;
return
false
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
case
MachineOperand
::
MO_JumpTableIndex
:
case
MachineOperand
::
MO_ExternalSymbol
:
llvm_unreachable
(
"unexpected operand type!"
)
;
case
MachineOperand
::
MO_GlobalAddress
:
printSymbolOperand
(
*
this
,
MO
,
O
)
;
if
(
Subtarget
->
isPICStyleRIPRel
(
)
)
O
<<
"(%rip)"
;
return
false
;
case
MachineOperand
::
MO_Register
:
O
<<
'('
;
printOperand
(
*
this
,
MI
,
OpNo
,
O
)
;
O
<<
')'
;
return
false
;
}
case
'c'
:
switch
(
MO
.
getType
(
)
)
{
default
:
printOperand
(
*
this
,
MI
,
OpNo
,
O
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
O
<<
MO
.
getImm
(
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
case
MachineOperand
::
MO_JumpTableIndex
:
case
MachineOperand
::
MO_ExternalSymbol
:
llvm_unreachable
(
"unexpected operand type!"
)
;
case
MachineOperand
::
MO_GlobalAddress
:
printSymbolOperand
(
*
this
,
MO
,
O
)
;
break
;
}
return
false
;
case
'A'
:
if
(
MO
.
isReg
(
)
)
{
O
<<
'*'
;
printOperand
(
*
this
,
MI
,
OpNo
,
O
)
;
return
false
;
}
return
true
;
case
'b'
:
case
'h'
:
case
'w'
:
case
'k'
:
case
'q'
:
case
'V'
:
if
(
MO
.
isReg
(
)
)
return
printAsmMRegister
(
*
this
,
MO
,
ExtraCode
[
0
]
,
O
)
;
printOperand
(
*
this
,
MI
,
OpNo
,
O
)
;
return
false
;
case
'P'
:
printPCRelImm
(
*
this
,
MI
,
OpNo
,
O
)
;
return
false
;
case
'n'
:
if
(
MO
.
isImm
(
)
)
{
O
<<
MO
.
getImm
(
)
;
return
false
;
}
O
<<
'-'
;
}
}
printOperand
(
*
this
,
MI
,
OpNo
,
O
,
nullptr
,
AsmVariant
)
;
return
false
;
}
</s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static bool lm32_in_small_data_p ( const_tree exp ) { if ( TREE_CODE ( exp ) == STRING_CST ) return false ; if ( TREE_CODE ( exp ) == FUNCTION_DECL ) return false ; if ( TREE_CODE ( exp ) == VAR_DECL && DECL_SECTION_NAME ( exp ) ) { const char * section = DECL_SECTION_NAME ( exp ) ; if ( strcmp ( section , ".sdata" ) == 0 || strcmp ( section , ".sbss" ) == 0 ) return true ; } else { HOST_WIDE_INT size = int_size_in_bytes ( TREE_TYPE ( exp ) ) ; if ( size > 0 && size <= g_switch_value ) return true ; } return false ; } </s>

Return true if EXP should be placed in the small data section .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < AAResultsWrapperPass > ( ) ; AU . addPreserved < AAResultsWrapperPass > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
void
GCNUpwardRPTracker
::
recede
(
const
MachineInstr
&
MI
)
{
assert
(
MRI
&&
"call reset first"
)
;
LastTrackedMI
=
&
MI
;
if
(
MI
.
isDebugInstr
(
)
)
return
;
auto
const
RegUses
=
collectVirtualRegUses
(
MI
,
LIS
,
*
MRI
)
;
auto
AtMIPressure
=
CurPressure
;
for
(
const
auto
&
U
:
RegUses
)
{
auto
LiveMask
=
LiveRegs
[
U
.
RegUnit
]
;
AtMIPressure
.
inc
(
U
.
RegUnit
,
LiveMask
,
LiveMask
|
U
.
LaneMask
,
*
MRI
)
;
}
MaxPressure
=
max
(
AtMIPressure
,
MaxPressure
)
;
for
(
const
auto
&
MO
:
MI
.
operands
(
)
)
{
if
(
!
MO
.
isReg
(
)
||
!
MO
.
isDef
(
)
||
!
Register
::
isVirtualRegister
(
MO
.
getReg
(
)
)
||
MO
.
isDead
(
)
)
continue
;
auto
Reg
=
MO
.
getReg
(
)
;
auto
I
=
LiveRegs
.
find
(
Reg
)
;
if
(
I
==
LiveRegs
.
end
(
)
)
continue
;
auto
&
LiveMask
=
I
->
second
;
auto
PrevMask
=
LiveMask
;
LiveMask
&=
~
getDefRegMask
(
MO
,
*
MRI
)
;
CurPressure
.
inc
(
Reg
,
PrevMask
,
LiveMask
,
*
MRI
)
;
if
(
LiveMask
.
(
)
)
LiveRegs
.
erase
(
I
)
;
}
for
(
const
auto
&
U
:
RegUses
)
{
auto
&
LiveMask
=
LiveRegs
[
U
.
RegUnit
]
;
auto
PrevMask
=
LiveMask
;
LiveMask
|=
U
.
LaneMask
;
CurPressure
.
inc
(
U
.
RegUnit
,
PrevMask
,
LiveMask
,
*
MRI
)
;
}
assert
(
CurPressure
==
getRegPressure
(
*
MRI
,
LiveRegs
)
)
;
}
</s>

Recede across the previous instruction .


<s> static rtx sh_function_arg ( cumulative_args_t ca_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * ca = get_cumulative_args ( ca_v ) ; if ( ! TARGET_SH5 && mode == VOIDmode ) return GEN_INT ( ca -> renesas_abi ? 1 : 0 ) ; if ( ! TARGET_SH5 && sh_pass_in_reg_p ( * ca , mode , type ) && ( named || ! ( TARGET_HITACHI || ca -> renesas_abi ) ) ) { int regno ; if ( mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN && ( ! FUNCTION_ARG_SCmode_WART || ( sh_round_reg ( * ca , mode ) & 1 ) ) ) { rtx r1 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SFmode , BASE_ARG_REG ( mode ) + ( sh_round_reg ( * ca , mode ) ^ 1 ) ) , const0_rtx ) ; rtx r2 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SFmode , BASE_ARG_REG ( mode ) + ( ( sh_round_reg ( * ca , mode ) + 1 ) ^ 1 ) ) , GEN_INT ( 4 ) ) ; return gen_rtx_PARALLEL ( SCmode , gen_rtvec ( 2 , r1 , r2 ) ) ; } if ( ( TARGET_HITACHI || ca -> renesas_abi ) && ca -> free_single_fp_reg && mode == SFmode ) return gen_rtx_REG ( mode , ca -> free_single_fp_reg ) ; regno = ( BASE_ARG_REG ( mode ) + sh_round_reg ( * ca , mode ) ) ^ ( mode == SFmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN && ! TARGET_HITACHI && ! ca -> renesas_abi ) ; return gen_rtx_REG ( mode , regno ) ; } if ( TARGET_SH5 ) { if ( mode == VOIDmode && TARGET_SHCOMPACT ) return GEN_INT ( ca -> call_cookie ) ; if ( mode == SFmode && ca -> free_single_fp_reg ) return SH5_PROTOTYPED_FLOAT_ARG ( * ca , mode , ca -> free_single_fp_reg ) ; if ( ( GET_SH_ARG_CLASS ( mode ) == SH_ARG_FLOAT ) && ( named || ! ca -> prototype_p ) && ca -> arg_count [ ( int ) SH_ARG_FLOAT ] < NPARM_REGS ( SFmode ) ) { if ( ! ca -> prototype_p && TARGET_SHMEDIA ) return SH5_PROTOTYPELESS_FLOAT_ARG ( * ca , mode ) ; return SH5_PROTOTYPED_FLOAT_ARG ( * ca , mode , FIRST_FP_PARM_REG + ca -> arg_count [ ( int ) SH_ARG_FLOAT ] ) ; } if ( ca -> arg_count [ ( int ) SH_ARG_INT ] < NPARM_REGS ( SImode ) && ( ! TARGET_SHCOMPACT || ( ! SHCOMPACT_FORCE_ON_STACK ( mode , type ) && ! SH5_WOULD_BE_PARTIAL_NREGS ( * ca , mode , type , named ) ) ) ) { return gen_rtx_REG ( mode , ( FIRST_PARM_REG + ca -> arg_count [ ( int ) SH_ARG_INT ] ) ) ; } return NULL_RTX ; } return NULL_RTX ; } </s>

Define where to put the arguments to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . On SH the first args are normally in registers and the rest are pushed . Any arg that starts within the first NPARM_REGS words is at least partially passed in a register unless its data type forbids .


<s> static rtx gen_gpr_to_xmm_move_src ( enum machine_mode vmode , rtx gpr ) { switch ( GET_MODE_NUNITS ( vmode ) ) { case 1 : return gen_rtx_SUBREG ( vmode , gpr , 0 ) ; case 2 : return gen_rtx_VEC_CONCAT ( vmode , gpr , CONST0_RTX ( GET_MODE_INNER ( vmode ) ) ) ; default : return gen_rtx_VEC_MERGE ( vmode , gen_rtx_VEC_DUPLICATE ( vmode , gpr ) , CONST0_RTX ( vmode ) , GEN_INT ( HOST_WIDE_INT_1U ) ) ; } } </s>

Generate the canonical SET_SRC to move GPR to a VMODE vector register , zeroing the upper parts .


"\t.word\t0x00000000\t\t# <static chain value>\n"


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> bool LoongArchAsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { return false ; } </s>

Hook to check if a relocation is needed for some target specific reason .


"All regions recorded, starting actual scheduling.\n"

"Retrying function scheduling with lowest recorded occupancy "

After the schedule has been formed , call this function to combine the instructions from the different stages/cycles .


<s> int crx_function_arg_regno_p ( int n ) { return ( n <= MAX_REG_FOR_PASSING_ARGS && n >= MIN_REG_FOR_PASSING_ARGS ) ; } </s>

Implements the macro FUNCTION_ARG_REGNO_P defined in crx.h . Return nonzero * if N is a register used for passing parameters .


<s> static rtx hwloop_pattern_reg ( rtx_insn * insn ) { rtx reg ; if ( ! JUMP_P ( insn ) || recog_memoized ( insn ) != CODE_FOR_loop_end ) return NULL_RTX ; reg = SET_DEST ( XVECEXP ( PATTERN ( insn ) , 0 , 1 ) ) ; if ( ! REG_P ( reg ) ) return NULL_RTX ; return reg ; } </s>

A callback for the hw-doloop pass . This function examines INSN ; if it is a doloop_end pattern we recognize , return the reg rtx for the loop counter . Otherwise , return NULL_RTX .


<s> unsigned AArch64FastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( DL , C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const auto * CI = dyn_cast < ConstantInt > ( C ) ) return materializeInt ( CI , VT ) ; else if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return materializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return materializeGV ( GV ) ; return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s> void X86IntelInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; unsigned Flags = MI -> getFlags ( ) ; if ( ( TSFlags & X86II :: LOCK ) || ( Flags & X86 :: IP_HAS_LOCK ) ) OS << "\tlock\t" ; if ( Flags & X86 :: IP_HAS_REPEAT_NE ) OS << "\trepne\t" ; else if ( Flags & X86 :: IP_HAS_REPEAT ) OS << "\trep\t" ; if ( ( TSFlags & X86II :: NOTRACK ) || ( Flags & X86 :: IP_HAS_NOTRACK ) ) OS << "\tnotrack\t" ; if ( MI -> getOpcode ( ) == X86 :: DATA16_PREFIX && STI . getFeatureBits ( ) [ X86 :: Mode16Bit ] ) { OS << "\tdata32" ; } else printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAnyX86InstComments ( MI , * CommentStream , MII ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> void Mips16FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( STI . getInstrInfo ( ) ) ; const MipsRegisterInfo & RI = TII . getRegisterInfo ( ) ; const BitVector Reserved = RI . getReservedRegs ( MF ) ; bool SaveS2 = Reserved [ Mips :: S2 ] ; if ( SaveS2 ) SavedRegs . set ( Mips :: S2 ) ; if ( hasFP ( MF ) ) SavedRegs . set ( Mips :: S0 ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> CCAssignFn * MipsFastISel :: CCAssignFnForCall ( CallingConv :: ID CC ) const { return CC_MipsO32 ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s>
SDValue
MSP430TargetLowering
::
LowerCall
(
SDValue
Chain
,
SDValue
Callee
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
bool
&
isTailCall
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
Ins
,
dl
,
DAG
,
InVals
)
;
case
CallingConv
::
MSP430_INTR
:
report_fatal_error
(
"ISRs cannot be called directly"
)
;
return
SDValue
(
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .


<s>
SDValue
X86TargetLowering
::
BuildSDIVPow2
(
SDNode
*
N
,
const
APInt
&
Divisor
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDNode
*
>
&
Created
)
const
{
AttributeList
Attr
=
DAG
.
getMachineFunction
(
)
.
getFunction
(
)
.
getAttributes
(
)
;
if
(
isIntDivCheap
(
N
->
getValueType
(
0
)
,
Attr
)
)
return
SDValue
(
N
,
0
)
;
assert
(
(
Divisor
.
isPowerOf2
(
)
||
Divisor
.
isNegatedPowerOf2
(
)
)
&&
"Unexpected divisor!"
)
;
if
(
!
Subtarget
.
canUseCMOV
(
)
)
return
SDValue
(
)
;
EVT
VT
=
N
->
getValueType
(
0
)
;
if
(
VT
!=
MVT
::
i16
&&
VT
!=
MVT
::
i32
&&
!
(
Subtarget
.
is64Bit
(
)
&&
VT
==
MVT
::
i64
)
)
return
SDValue
(
)
;
unsigned
Lg2
=
Divisor
.
countTrailingZeros
(
)
;
if
(
Lg2
==
1
)
return
SDValue
(
)
;
SDLoc
DL
(
N
)
;
SDValue
N0
=
N
->
getOperand
(
0
)
;
SDValue
Zero
=
DAG
.
getConstant
(
0
,
DL
,
VT
)
;
APInt
Lg2Mask
=
APInt
::
getLowBitsSet
(
VT
.
getSizeInBits
(
)
,
Lg2
)
;
SDValue
Pow2MinusOne
=
DAG
.
getConstant
(
Lg2Mask
,
DL
,
VT
)
;
SDValue
Cmp
=
DAG
.
getSetCC
(
DL
,
MVT
::
i8
,
N0
,
Zero
,
ISD
::
SETLT
)
;
SDValue
Add
=
DAG
.
getNode
(
ISD
::
ADD
,
DL
,
VT
,
N0
,
Pow2MinusOne
)
;
SDValue
CMov
=
DAG
.
getNode
(
ISD
::
SELECT
,
DL
,
VT
,
Cmp
,
Add
,
N0
)
;
Created
.
push_back
(
Cmp
.
getNode
(
)
)
;
Created
.
push_back
(
Add
.
getNode
(
)
)
;
Created
.
push_back
(
CMov
.
getNode
(
)
)
;
SDValue
SRA
=
DAG
.
getNode
(
ISD
::
SRA
,
DL
,
VT
,
CMov
,
DAG
.
getConstant
(
Lg2
,
DL
,
MVT
::
i8
)
)
;
if
(
Divisor
.
isNonNegative
(
)
)
return
SRA
;
Created
.
push_back
(
SRA
.
getNode
(
)
)
;
return
DAG
.
getNode
(
ISD
::
SUB
,
DL
,
VT
,
Zero
,
SRA
)
;
}
</s>

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators .


<s> const char * output_387_reg_move ( rtx insn , rtx * operands ) { if ( REG_P ( operands [ 1 ] ) && find_regno_note ( insn , REG_DEAD , REGNO ( operands [ 1 ] ) ) ) { if ( REGNO ( operands [ 0 ] ) == FIRST_STACK_REG && TARGET_USE_FFREEP ) return "ffreep\t%y0" ; return "fstp\t%y0" ; } if ( STACK_TOP_P ( operands [ 0 ] ) ) return "fld%z1\t%y1" ; return "fst\t%y0" ; } </s>

Output code to perform an x87 FP register move , from OPERANDS [ 1 ] to OPERANDS [ 0 ] .


<s> void AMDGPUDAGToDAGISel :: PreprocessISelDAG ( ) { bool Modified = false ; SmallVector < LoadSDNode * , 8 > LoadsToReplace ; SmallVector < StoreSDNode * , 8 > StoresToReplace ; for ( SDNode & Node : CurDAG -> allnodes ( ) ) { if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( & Node ) ) { EVT VT = LD -> getValueType ( 0 ) ; if ( VT != MVT :: i64 || LD -> getExtensionType ( ) != ISD :: NON_EXTLOAD ) continue ; LoadsToReplace . push_back ( LD ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( & Node ) ) { SDValue Value = ST -> getValue ( ) ; if ( Value . getValueType ( ) != MVT :: i64 || ST -> isTruncatingStore ( ) ) continue ; StoresToReplace . push_back ( ST ) ; } } for ( LoadSDNode * LD : LoadsToReplace ) { SDLoc SL ( LD ) ; SDValue NewLoad = CurDAG -> getLoad ( MVT :: v2i32 , SL , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getMemOperand ( ) ) ; SDValue BitCast = CurDAG -> getNode ( ISD :: BITCAST , SL , MVT :: i64 , NewLoad ) ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( LD , 1 ) , NewLoad . getValue ( 1 ) ) ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( LD , 0 ) , BitCast ) ; Modified = true ; } for ( StoreSDNode * ST : StoresToReplace ) { SDValue NewValue = CurDAG -> getNode ( ISD :: BITCAST , SDLoc ( ST ) , MVT :: v2i32 , ST -> getValue ( ) ) ; const SDValue StoreOps [ ] = { ST -> getChain ( ) , NewValue , ST -> getBasePtr ( ) , ST -> getOffset ( ) } ; CurDAG -> UpdateNodeOperands ( ST , StoreOps ) ; Modified = true ; } if ( Modified ) CurDAG -> RemoveDeadNodes ( ) ; } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> void fr30_setup_incoming_varargs ( cumulative_args_t arg_regs_used_so_far_v , const function_arg_info & arg , int * pretend_size , int second_time ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * arg_regs_used_so_far = get_cumulative_args ( arg_regs_used_so_far_v ) ; int size ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) ) { gcc_assert ( arg . mode != BLKmode ) ; if ( targetm . calls . strict_argument_naming ( arg_regs_used_so_far_v ) ) arg_regs_used_so_far += fr30_num_arg_regs ( arg ) ; } size = FR30_NUM_ARG_REGS - ( * arg_regs_used_so_far ) ; if ( size <= 0 ) return ; * pretend_size = ( size * UNITS_PER_WORD ) ; } </s>

Do any needed setup for a variadic function . We must create a register parameter block , and then copy any anonymous arguments , plus the last named argument , from registers into memory . * copying actually done in fr30_expand_prologue ( ) . ARG_REGS_USED_SO_FAR has * not * been updated for the last named argument which has type TYPE and mode MODE , and we rely on this fact .


<s> static int xtensa_memory_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t rclass ATTRIBUTE_UNUSED , bool in ATTRIBUTE_UNUSED ) { return 4 ; } </s>

Worker function for TARGET_MEMORY_MOVE_COST .


<s> unsigned X86RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; unsigned FPDiff = TFI -> hasFP ( MF ) ? 1 : 0 ; switch ( RC -> getID ( ) ) { default : return 0 ; case X86 :: GR32RegClassID : return 4 - FPDiff ; case X86 :: GR64RegClassID : return 12 - FPDiff ; case X86 :: VR128RegClassID : return Subtarget . is64Bit ( ) ? 10 : 4 ; case X86 :: VR64RegClassID : return 4 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s>
const
MCPhysReg
*
AArch64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_AArch64_NoRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_AArch64_AllRegs_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetDarwin
(
)
)
return
getDarwinCalleeSavedRegs
(
MF
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
CFGuard_Check
)
return
CSR_Win_AArch64_CFGuard_Check_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetWindows
(
)
)
return
CSR_Win_AArch64_AAPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_VectorCall
)
return
CSR_AArch64_AAVPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_SVE_VectorCall
)
return
CSR_AArch64_SVE_AAPCS_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
.
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_AArch64_AAPCS_SwiftError_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
SwiftTail
)
return
CSR_AArch64_AAPCS_SwiftTail_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
PreserveMost
)
return
CSR_AArch64_RT_MostRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
Win64
)
return
CSR_AArch64_AAPCS_X18_SaveList
;
if
(
hasSVEArgsOrReturn
(
MF
)
)
return
CSR_AArch64_SVE_AAPCS_SaveList
;
return
CSR_AArch64_AAPCS_SaveList
;
}
</s>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { GlobalBaseReg = 0 ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; if ( ! PPCSubTarget . isSVR4ABI ( ) ) InsertVRSaveCode ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> auto AlignVectors :: getMask ( Value * Val ) const -> Value * { if ( auto * II = dyn_cast < IntrinsicInst > ( Val ) ) { switch ( II -> getIntrinsicID ( ) ) { case Intrinsic :: masked_load : return II -> getArgOperand ( 2 ) ; case Intrinsic :: masked_store : return II -> getArgOperand ( 3 ) ; } } Type * ValTy = getPayload ( Val ) -> getType ( ) ; if ( auto * VecTy = dyn_cast < VectorType > ( ValTy ) ) { int ElemCount = VecTy -> getElementCount ( ) . getFixedValue ( ) ; return HVC . getFullValue ( HVC . getBoolTy ( ElemCount ) ) ; } return HVC . getFullValue ( HVC . getBoolTy ( ) ) ; } </s>


<s> int vspltis_shifted ( rtx op ) { machine_mode mode = GET_MODE ( op ) ; machine_mode inner = GET_MODE_INNER ( mode ) ; unsigned i , j ; unsigned nunits ; unsigned mask ; HOST_WIDE_INT val ; if ( mode != V16QImode && mode != V8HImode && mode != V4SImode ) return false ; if ( ! can_create_pseudo_p ( ) || ( cfun -> curr_properties & PROP_rtl_split_insns ) ) return false ; nunits = GET_MODE_NUNITS ( mode ) ; mask = GET_MODE_MASK ( inner ) ; val = const_vector_elt_as_int ( op , BYTES_BIG_ENDIAN ? 0 : nunits - 1 ) ; if ( EASY_VECTOR_15 ( val ) ) ; else if ( EASY_VECTOR_MSB ( val , inner ) ) ; else return 0 ; for ( i = 1 ; i < nunits ; ++ i ) { unsigned elt = BYTES_BIG_ENDIAN ? i : nunits - 1 - i ; HOST_WIDE_INT elt_val = const_vector_elt_as_int ( op , elt ) ; if ( val != elt_val ) { if ( elt_val == 0 ) { for ( j = i + 1 ; j < nunits ; ++ j ) { unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j ; if ( const_vector_elt_as_int ( op , elt2 ) != 0 ) return 0 ; } return ( nunits - i ) * GET_MODE_SIZE ( inner ) ; } else if ( ( elt_val & mask ) == mask ) { for ( j = i + 1 ; j < nunits ; ++ j ) { unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j ; if ( ( const_vector_elt_as_int ( op , elt2 ) & mask ) != mask ) return 0 ; } return - ( ( nunits - i ) * GET_MODE_SIZE ( inner ) ) ; } else return 0 ; } } return 0 ; } </s>

Like vsplitis_constant , but allow the value to be shifted left with a VSLDOI instruction , filling in the bottom elements with 0 or -1 . Return 0 if the constant can not be generated with VSLDOI . Return positive for the number of zeroes to shift in , or negative for the number of 0xff bytes to shift in . OP is a CONST_VECTOR .


<s> void print_operand_address ( FILE * stream , rtx x ) { switch ( GET_CODE ( x ) ) { case REG : case SUBREG : fprintf ( stream , "@%s" , reg_names [ true_regnum ( x ) ] ) ; break ; case PLUS : { rtx base = XEXP ( x , 0 ) ; rtx index = XEXP ( x , 1 ) ; switch ( GET_CODE ( index ) ) { case CONST_INT : fprintf ( stream , "@(%d,%s)" , ( int ) INTVAL ( index ) , reg_names [ true_regnum ( base ) ] ) ; break ; case REG : case SUBREG : { int base_num = true_regnum ( base ) ; int index_num = true_regnum ( index ) ; fprintf ( stream , "@(r0,%s)" , reg_names [ MAX ( base_num , index_num ) ] ) ; break ; } default : gcc_unreachable ( ) ; } } break ; case PRE_DEC : fprintf ( stream , "@-%s" , reg_names [ true_regnum ( XEXP ( x , 0 ) ) ] ) ; break ; case POST_INC : fprintf ( stream , "@%s+" , reg_names [ true_regnum ( XEXP ( x , 0 ) ) ] ) ; break ; default : x = mark_constant_pool_use ( x ) ; output_addr_const ( stream , x ) ; break ; } } </s>

Print the operand address represented by the rtx addr


<s> bool PPCTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , bool * Fast ) const { if ( DisablePPCUnaligned ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( VT . getSimpleVT ( ) . isVector ( ) ) { if ( Subtarget . hasVSX ( ) ) { if ( VT != MVT :: v2f64 && VT != MVT :: v2i64 && VT != MVT :: v4f32 && VT != MVT :: v4i32 ) return false ; } else { return false ; } } if ( VT == MVT :: ppcf128 ) return false ; if ( Fast ) * Fast = true ; return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> void neon_const_bounds ( rtx operand , HOST_WIDE_INT low , HOST_WIDE_INT high ) { bounds_check ( operand , low , high , NULL_TREE , "constant" ) ; } </s>


<s> int frv_hard_regno_nregs ( int regno , machine_mode mode ) { if ( ACCG_P ( regno ) ) return GET_MODE_SIZE ( mode ) ; else return ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } </s>

On the FRV , make the CC_FP mode take 3 words in the integer registers , so that we can build the appropriate instructions to properly reload the values . Also , make the byte-sized accumulator guards use one guard for each byte .


<s>
bool
HexagonInstrInfo
::
PredicateInstruction
(
MachineInstr
*
MI
,
ArrayRef
<
MachineOperand
>
Cond
)
const
{
if
(
Cond
.
empty
(
)
||
isNewValueJump
(
Cond
[
0
]
.
getImm
(
)
)
||
isEndLoopN
(
Cond
[
0
]
.
getImm
(
)
)
)
{
DEBUG
(
dbgs
(
)
<<
"\nCannot predicate:"
;
MI
->
dump
(
)
;
)
;
return
false
;
}
int
Opc
=
MI
->
getOpcode
(
)
;
assert
(
isPredicable
(
MI
)
&&
"Expected predicable instruction"
)
;
bool
invertJump
=
predOpcodeHasNot
(
Cond
)
;
MachineBasicBlock
&
B
=
*
MI
->
getParent
(
)
;
DebugLoc
DL
=
MI
->
getDebugLoc
(
)
;
unsigned
PredOpc
=
getCondOpcode
(
Opc
,
invertJump
)
;
MachineInstrBuilder
T
=
BuildMI
(
B
,
MI
,
DL
,
get
(
PredOpc
)
)
;
unsigned
NOp
=
0
,
NumOps
=
MI
->
getNumOperands
(
)
;
while
(
NOp
<
NumOps
)
{
MachineOperand
&
Op
=
MI
->
getOperand
(
NOp
)
;
if
(
!
Op
.
isReg
(
)
||
!
Op
.
isDef
(
)
||
Op
.
isImplicit
(
)
)
break
;
T
.
addOperand
(
Op
)
;
NOp
++
;
}
unsigned
PredReg
,
PredRegPos
,
PredRegFlags
;
bool
GotPredReg
=
getPredReg
(
Cond
,
PredReg
,
PredRegPos
,
PredRegFlags
)
;
(
void
)
GotPredReg
;
assert
(
GotPredReg
)
;
T
.
addReg
(
PredReg
,
PredRegFlags
)
;
while
(
NOp
<
NumOps
)
T
.
addOperand
(
MI
->
getOperand
(
NOp
++
)
)
;
MI
->
setDesc
(
get
(
PredOpc
)
)
;
while
(
unsigned
n
=
MI
->
getNumOperands
(
)
)
MI
->
RemoveOperand
(
n
1
)
;
for
(
unsigned
i
=
0
,
n
=
T
->
getNumOperands
(
)
;
i
<
n
;
++
i
)
MI
->
addOperand
(
T
->
getOperand
(
i
)
)
;
MachineBasicBlock
::
instr_iterator
TI
=
T
->
getIterator
(
)
;
B
.
erase
(
TI
)
;
MachineRegisterInfo
&
MRI
=
B
.
getParent
(
)
->
getRegInfo
(
)
;
MRI
.
clearKillFlags
(
PredReg
)
;
return
true
;
}
</s>

Convert the instruction into a predicated instruction .


"calling %qD with SSE calling convention without "

"this is a GCC bug that can be worked around by adding "

Define where to put the arguments to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) .


<s>
static
bool
Check
(
DecodeStatus
&
Out
,
DecodeStatus
In
)
{
switch
(
In
)
{
case
MCDisassembler
::
Success
:
return
true
;
case
MCDisassembler
::
SoftFail
:
Out
=
In
;
return
true
;
case
MCDisassembler
::
Fail
:
Out
=
In
;
return
false
;
}
llvm_unreachable
(
"Invalid DecodeStatus!"
)
;
}
</s>

Matches check string and its `` not strings '' and/or `` dag strings '' .


<s> void sparc_emit_floatunsdi ( rtx * operands , enum machine_mode mode ) { rtx neglab , donelab , i0 , i1 , f0 , in , out ; out = operands [ 0 ] ; in = force_reg ( DImode , operands [ 1 ] ) ; neglab = gen_label_rtx ( ) ; donelab = gen_label_rtx ( ) ; i0 = gen_reg_rtx ( DImode ) ; i1 = gen_reg_rtx ( DImode ) ; f0 = gen_reg_rtx ( mode ) ; emit_cmp_and_jump_insns ( in , const0_rtx , LT , const0_rtx , DImode , 0 , neglab ) ; emit_insn ( gen_rtx_SET ( VOIDmode , out , gen_rtx_FLOAT ( mode , in ) ) ) ; emit_jump_insn ( gen_jump ( donelab ) ) ; emit_barrier ( ) ; emit_label ( neglab ) ; emit_insn ( gen_lshrdi3 ( i0 , in , const1_rtx ) ) ; emit_insn ( gen_anddi3 ( i1 , in , const1_rtx ) ) ; emit_insn ( gen_iordi3 ( i0 , i0 , i1 ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , f0 , gen_rtx_FLOAT ( mode , i0 ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , out , gen_rtx_PLUS ( mode , f0 , f0 ) ) ) ; emit_label ( donelab ) ; } </s>

Generate an unsigned DImode to FP conversion . This is the same code optabs would emit if we did n't have TFmode patterns .


<s>
void
TriCoreMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
if
(
Desc
.
getSize
(
)
!=
2
&&
Desc
.
getSize
(
)
!=
4
)
{
llvm_unreachable
(
"Unexpected instruction size!"
)
;
}
uint32_t
Binary
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
if
(
Desc
.
getSize
(
)
==
4
)
{
EmitConstant
(
Binary
&
0xffff
,
2
,
OS
)
;
EmitConstant
(
Binary
>>
16
,
2
,
OS
)
;
}
else
EmitConstant
(
Binary
,
2
,
OS
)
;
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .


<s> bool GCNPassConfig :: addGlobalInstructionSelect ( ) { return false ; } </s>

This method should install a ( global ) instruction selector pass , which converts possibly generic instructions to fully target-specific instructions , thereby constraining all generic virtual registers to register classes .


<s> void xstormy16_expand_prologue ( ) { struct xstormy16_stack_layout layout ; int regno ; rtx insn ; rtx mem_push_rtx ; rtx mem_fake_push_rtx ; const int ifun = xstormy16_interrupt_function_p ( ) ; mem_push_rtx = gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ; mem_push_rtx = gen_rtx_MEM ( HImode , mem_push_rtx ) ; mem_fake_push_rtx = gen_rtx_PRE_INC ( Pmode , stack_pointer_rtx ) ; mem_fake_push_rtx = gen_rtx_MEM ( HImode , mem_fake_push_rtx ) ; layout = xstormy16_compute_stack_layout ( ) ; if ( layout . stdarg_save_size ) for ( regno = FIRST_ARGUMENT_REGISTER ; regno < FIRST_ARGUMENT_REGISTER + NUM_ARGUMENT_REGISTERS ; regno ++ ) { rtx reg = gen_rtx_REG ( HImode , regno ) ; insn = emit_move_insn ( mem_push_rtx , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , mem_fake_push_rtx , reg ) , REG_NOTES ( insn ) ) ; } for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( REG_NEEDS_SAVE ( regno , ifun ) ) { rtx reg = gen_rtx_REG ( HImode , regno ) ; insn = emit_move_insn ( mem_push_rtx , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , mem_fake_push_rtx , reg ) , REG_NOTES ( insn ) ) ; } if ( frame_pointer_needed && layout . sp_minus_fp == layout . locals_size ) { insn = emit_move_insn ( hard_frame_pointer_rtx , stack_pointer_rtx ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } if ( layout . locals_size ) { insn = emit_addhi3_postreload ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( layout . locals_size ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } if ( frame_pointer_needed && layout . sp_minus_fp != layout . locals_size ) { insn = emit_move_insn ( hard_frame_pointer_rtx , stack_pointer_rtx ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( layout . sp_minus_fp ) { insn = emit_addhi3_postreload ( hard_frame_pointer_rtx , hard_frame_pointer_rtx , GEN_INT ( - layout . sp_minus_fp ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } } </s>

Called after register allocation to add any instructions needed for the prologue . Using a prologue insn is favored compared to putting all of the instructions in the TARGET_ASM_FUNCTION_PROLOGUE macro , since it allows the scheduler to intermix instructions with the saves of the caller saved registers . In some cases , it might be necessary to emit a barrier instruction as the last insn to prevent such scheduling . Also any insns generated here should have RTX_FRAME_RELATED_P ( insn ) = 1 so that the debug info generation code can handle them properly .


<s> void visitCallInst ( CallInst & I ) { StringRef Name = I . getCalledFunction ( ) -> getName ( ) ; if ( Name == "llvm.AMDGPU.tex" ) { ReplaceTexIntrinsic ( I , false , TexSign , "llvm.R600.tex" , "llvm.R600.texc" ) ; return ; } if ( Name == "llvm.AMDGPU.txl" ) { ReplaceTexIntrinsic ( I , true , TexSign , "llvm.R600.txl" , "llvm.R600.txlc" ) ; return ; } if ( Name == "llvm.AMDGPU.txb" ) { ReplaceTexIntrinsic ( I , true , TexSign , "llvm.R600.txb" , "llvm.R600.txbc" ) ; return ; } if ( Name == "llvm.AMDGPU.txf" ) { ReplaceTXF ( I ) ; return ; } if ( Name == "llvm.AMDGPU.txq" ) { ReplaceTexIntrinsic ( I , false , TexQSign , "llvm.R600.txq" , "llvm.R600.txq" ) ; return ; } if ( Name == "llvm.AMDGPU.ddx" ) { ReplaceTexIntrinsic ( I , false , TexSign , "llvm.R600.ddx" , "llvm.R600.ddx" ) ; return ; } if ( Name == "llvm.AMDGPU.ddy" ) { ReplaceTexIntrinsic ( I , false , TexSign , "llvm.R600.ddy" , "llvm.R600.ddy" ) ; return ; } } </s>


<s>
bool
X86TargetLowering
::
lowerInterleavedStore
(
StoreInst
*
SI
,
ShuffleVectorInst
*
SVI
,
unsigned
Factor
)
const
{
assert
(
Factor
>=
2
&&
Factor
<=
getMaxSupportedInterleaveFactor
(
)
&&
"Invalid interleave factor"
)
;
assert
(
cast
<
FixedVectorType
>
(
SVI
->
getType
(
)
)
->
getNumElements
(
)
%
Factor
==
0
&&
"Invalid interleaved store"
)
;
SmallVector
<
unsigned
,
4
>
Indices
;
auto
Mask
=
SVI
->
getShuffleMask
(
)
;
for
(
unsigned
i
=
0
;
i
<
Factor
;
i
++
)
Indices
.
push_back
(
Mask
[
i
]
)
;
ArrayRef
<
ShuffleVectorInst
*
>
Shuffles
=
makeArrayRef
(
SVI
)
;
IRBuilder
<
>
Builder
(
SI
)
;
X86InterleavedAccessGroup
Grp
(
SI
,
Shuffles
,
Indices
,
Factor
,
Subtarget
,
Builder
)
;
return
Grp
.
isSupported
(
)
&&
Grp
.
lowerIntoOptimizedSequence
(
)
;
}
</s>

Lower interleaved store ( s ) into target specific instructions/intrinsics .


<s> unsigned X86TargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { unsigned VTBits = Op . getScalarValueSizeInBits ( ) ; unsigned Opcode = Op . getOpcode ( ) ; switch ( Opcode ) { case X86ISD :: SETCC_CARRY : return VTBits ; case X86ISD :: VSEXT : { SDValue Src = Op . getOperand ( 0 ) ; unsigned Tmp = DAG . ComputeNumSignBits ( Src , Depth + 1 ) ; Tmp += VTBits - Src . getScalarValueSizeInBits ( ) ; return Tmp ; } case X86ISD :: VSRAI : { SDValue Src = Op . getOperand ( 0 ) ; unsigned Tmp = DAG . ComputeNumSignBits ( Src , Depth + 1 ) ; APInt ShiftVal = cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) -> getAPIntValue ( ) ; ShiftVal += Tmp ; return ShiftVal . uge ( VTBits ) ? VTBits : ShiftVal . getZExtValue ( ) ; } case X86ISD :: PCMPGT : case X86ISD :: PCMPEQ : case X86ISD :: CMPP : case X86ISD :: VPCOM : case X86ISD :: VPCOMU : return VTBits ; } return 1 ; } </s>

Determine the number of bits in the operation that are sign bits .


<s> void HexagonPassConfig :: addPostRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) if ( ! DisableHexagonCFGOpt ) addPass ( createHexagonCFGOptimizer ( ) , false ) ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> const AArch64Subtarget * getSubtargetImpl ( ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


Hook to validate the current # pragma GCC target and set the state , and update the macros based on what was changed . If ARGS is NULL , then POP_TARGET is used to reset the options .


<s>
static
rtx
frv_read_iacc_argument
(
machine_mode
mode
,
tree
call
,
unsigned
int
index
)
{
int
i
,
regno
;
rtx
op
;
op
=
frv_read_argument
(
call
,
index
)
;
if
(
GET_CODE
(
op
)
!=
CONST_INT
||
INTVAL
(
op
)
<
0
||
INTVAL
(
op
)
>
IACC_LAST
IACC_FIRST
||
(
(
INTVAL
(
op
)
*
4
)
&
(
GET_MODE_SIZE
(
mode
)
1
)
)
!=
0
)
{
error
(
"invalid IACC argument"
)
;
op
=
const0_rtx
;
}
regno
=
INTVAL
(
op
)
+
IACC_FIRST
;
for
(
i
=
0
;
i
<
hard_regno_nregs
(
regno
,
mode
)
;
i
++
)
global_regs
[
regno
+
i
]
=
1
;
return
gen_rtx_REG
(
mode
,
regno
)
;
}
</s>

Like frv_read_argument , but interpret the argument as the number of an IACC register and return a ( reg : MODE ... ) rtx for it .


<s> MachineInstrBuilder MipsInstrInfo :: genInstrWithNewOpc ( unsigned NewOpc , MachineBasicBlock :: iterator I ) const { MachineInstrBuilder MIB ; int ZeroOperandPosition = - 1 ; bool BranchWithZeroOperand = false ; if ( I -> isBranch ( ) && ! I -> isPseudo ( ) ) { auto TRI = I -> getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; ZeroOperandPosition = I -> findRegisterUseOperandIdx ( Mips :: ZERO , false , TRI ) ; BranchWithZeroOperand = ZeroOperandPosition != - 1 ; } if ( BranchWithZeroOperand ) { switch ( NewOpc ) { case Mips :: BEQC : NewOpc = Mips :: BEQZC ; break ; case Mips :: BNEC : NewOpc = Mips :: BNEZC ; break ; case Mips :: BGEC : NewOpc = Mips :: BGEZC ; break ; case Mips :: BLTC : NewOpc = Mips :: BLTZC ; break ; case Mips :: BEQC64 : NewOpc = Mips :: BEQZC64 ; break ; case Mips :: BNEC64 : NewOpc = Mips :: BNEZC64 ; break ; } } MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , get ( NewOpc ) ) ; if ( NewOpc == Mips :: JIC || NewOpc == Mips :: JIALC || NewOpc == Mips :: JIC64 || NewOpc == Mips :: JIALC64 ) { if ( NewOpc == Mips :: JIALC || NewOpc == Mips :: JIALC64 ) MIB -> RemoveOperand ( 0 ) ; for ( unsigned J = 0 , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { MIB . addOperand ( I -> getOperand ( J ) ) ; } MIB . addImm ( 0 ) ; } else { for ( unsigned J = 0 , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { if ( BranchWithZeroOperand && ( unsigned ) ZeroOperandPosition == J ) continue ; MIB . addOperand ( I -> getOperand ( J ) ) ; } } MIB . copyImplicitOps ( * I ) ; MIB . setMemRefs ( I -> memoperands_begin ( ) , I -> memoperands_end ( ) ) ; return MIB ; } </s>

Create an instruction which has the same operands and memory operands as MI but has a new opcode .


<s> SDValue XCoreSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { unsigned SizeBitWidth = Size . getValueType ( ) . getSizeInBits ( ) ; if ( ! AlwaysInline && ( Align & 3 ) == 0 && DAG . MaskedValueIsZero ( Size , APInt ( SizeBitWidth , 3 ) ) ) { const TargetLowering & TLI = * DAG . getSubtarget ( ) . getTargetLowering ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; Entry . Node = Src ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMCPY ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( "__memcpy_4" , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) , std :: move ( Args ) ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .


<s> const MipsSubtarget * MipsTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool hasMips16Attr = F . getFnAttribute ( "mips16" ) . isValid ( ) ; bool hasNoMips16Attr = F . getFnAttribute ( "nomips16" ) . isValid ( ) ; bool HasMicroMipsAttr = F . getFnAttribute ( "micromips" ) . isValid ( ) ; bool HasNoMicroMipsAttr = F . getFnAttribute ( "nomicromips" ) . isValid ( ) ; bool softFloat = F . hasFnAttribute ( "use-soft-float" ) && F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( hasMips16Attr ) FS += FS . empty ( ) ? "+mips16" : ",+mips16" ; else if ( hasNoMips16Attr ) FS += FS . empty ( ) ? "-mips16" : ",-mips16" ; if ( HasMicroMipsAttr ) FS += FS . empty ( ) ? "+micromips" : ",+micromips" ; else if ( HasNoMicroMipsAttr ) FS += FS . empty ( ) ? "-micromips" : ",-micromips" ; if ( softFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < MipsSubtarget > ( TargetTriple , CPU , FS , isLittle , * this , MaybeAlign ( Options . StackAlignmentOverride ) ) ; } return I . get ( ) ; } </s>

Mips Mips Mips "target-cpu" "target-features" Mips "mips16" Mips "nomips16" Mips "micromips" Mips "nomicromips" "use-soft-float" "use-soft-float" "true" Mips "+mips16" ",+mips16" Mips "-mips16" ",-mips16" Mips "+micromips" ",+micromips" Mips "-micromips" ",-micromips" "+soft-float" ",+soft-float" Mips


<s>
LLVM_DUMP_METHOD
void
GCNRegPressure
::
print
(
raw_ostream
&
OS
,
const
SISubtarget
*
ST
)
const
{
OS
<<
"VGPRs: "
<<
getVGPRNum
(
)
;
if
(
ST
)
OS
<<
"(O"
<<
ST
->
getOccupancyWithNumVGPRs
(
getVGPRNum
(
)
)
<<
')'
;
OS
<<
", SGPRs: "
<<
getSGPRNum
(
)
;
if
(
ST
)
OS
<<
"(O"
<<
ST
->
getOccupancyWithNumSGPRs
(
getSGPRNum
(
)
)
<<
')'
;
OS
<<
", LVGPR WT: "
<<
getVGPRTuplesWeight
(
)
<<
", LSGPR WT: "
<<
getSGPRTuplesWeight
(
)
;
if
(
ST
)
OS
<<
" -> Occ: "
<<
getOccupancy
(
*
ST
)
;
OS
<<
'\n'
;
}
</s>

print - Print a debug representation of the operand to the given stream .

AMDGPU
SI
"VGPRs: "
"(O"
", SGPRs: "
"(O"
", LVGPR WT: "
", LSGPR WT: "
" -> Occ: "


<s>
void
AMDGPUPropagateAttributes
::
setAttributes
(
Function
&
F
,
const
ArrayRef
<
Optional
<
Attribute
>>
NewAttrs
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Set attributes on "
<<
F
.
getName
(
)
<<
":\n"
)
;
for
(
unsigned
I
=
0
;
I
<
NumAttr
;
++
I
)
{
F
.
removeFnAttr
(
AttributeNames
[
I
]
)
;
if
(
NewAttrs
[
I
]
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
'\t'
<<
NewAttrs
[
I
]
->
getAsString
(
)
<<
'\n'
)
;
F
.
addFnAttr
(
*
NewAttrs
[
I
]
)
;
}
}
}
</s>

AMDGPU
AMDGPU
"Set attributes on "
":\n"
0


<s> ScheduleHazardRecognizer * PPCInstrInfo :: CreateTargetHazardRecognizer ( const TargetMachine * TM , const ScheduleDAG * DAG ) const { unsigned Directive = TM -> getSubtarget < PPCSubtarget > ( ) . getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_440 ) { const InstrItineraryData * II = TM -> getInstrItineraryData ( ) ; return new PPCHazardRecognizer440 ( II , DAG ) ; } return TargetInstrInfoImpl :: CreateTargetHazardRecognizer ( TM , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .