<s> static bool frv_sort_insn_group_1 ( enum frv_insn_group group , unsigned int lower_slot , unsigned int upper_slot , unsigned int issued , unsigned int num_insns , state_t state ) { struct frv_packet_group * packet_group ; unsigned int i ; state_t test_state ; size_t dfa_size ; rtx insn ; if ( lower_slot == upper_slot ) return true ; packet_group = & frv_packet . groups [ group ] ; dfa_size = state_size ( ) ; test_state = alloca ( dfa_size ) ; for ( i = num_insns - 1 ; i + 1 != 0 ; i -- ) if ( ~ issued & ( 1 << i ) ) { insn = packet_group -> sorted [ i ] ; memcpy ( test_state , state , dfa_size ) ; if ( state_transition ( test_state , insn ) < 0 && cpu_unit_reservation_p ( test_state , NTH_UNIT ( group , upper_slot - 1 ) ) && frv_sort_insn_group_1 ( group , lower_slot , upper_slot - 1 , issued | ( 1 << i ) , num_insns , test_state ) ) { packet_group -> sorted [ upper_slot - 1 ] = insn ; return true ; } } return false ; } </s>

Subroutine of frv_sort_insn_group . We are trying to sort frv_packet.groups [ GROUP ] .sorted [ 0 ... NUM_INSNS-1 ] into assembly language order . We have already picked a new position for frv_packet.groups [ GROUP ] .sorted [ X ] if bit X of ISSUED is set . These instructions will occupy elements [ 0 , LOWER_SLOT ) and [ UPPER_SLOT , NUM_INSNS ) of the final ( sorted ) array . STATE is the DFA state after issuing these instructions . Try filling elements [ LOWER_SLOT , UPPER_SLOT ) with every permutation of the unused instructions . Return true if one such permutation gives a valid ordering , leaving the successful permutation in sorted [ ] . Do not modify sorted [ ] until a valid permutation is found .


<s> SMLoc getEndLoc ( ) const { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> enum machine_mode arm_select_dominance_cc_mode ( rtx x , rtx y , HOST_WIDE_INT cond_or ) { enum rtx_code cond1 , cond2 ; int swapped = 0 ; if ( ( arm_select_cc_mode ( cond1 = GET_CODE ( x ) , XEXP ( x , 0 ) , XEXP ( x , 1 ) ) != CCmode ) || ( arm_select_cc_mode ( cond2 = GET_CODE ( y ) , XEXP ( y , 0 ) , XEXP ( y , 1 ) ) != CCmode ) ) return CCmode ; if ( cond_or == DOM_CC_NX_OR_Y ) cond1 = reverse_condition ( cond1 ) ; if ( cond1 != cond2 && ! comparison_dominates_p ( cond1 , cond2 ) && ( swapped = 1 , ! comparison_dominates_p ( cond2 , cond1 ) ) ) return CCmode ; if ( swapped ) { enum rtx_code temp = cond1 ; cond1 = cond2 ; cond2 = temp ; } switch ( cond1 ) { case EQ : if ( cond_or == DOM_CC_X_AND_Y ) return CC_DEQmode ; switch ( cond2 ) { case EQ : return CC_DEQmode ; case LE : return CC_DLEmode ; case LEU : return CC_DLEUmode ; case GE : return CC_DGEmode ; case GEU : return CC_DGEUmode ; default : gcc_unreachable ( ) ; } case LT : if ( cond_or == DOM_CC_X_AND_Y ) return CC_DLTmode ; switch ( cond2 ) { case LT : return CC_DLTmode ; case LE : return CC_DLEmode ; case NE : return CC_DNEmode ; default : gcc_unreachable ( ) ; } case GT : if ( cond_or == DOM_CC_X_AND_Y ) return CC_DGTmode ; switch ( cond2 ) { case GT : return CC_DGTmode ; case GE : return CC_DGEmode ; case NE : return CC_DNEmode ; default : gcc_unreachable ( ) ; } case LTU : if ( cond_or == DOM_CC_X_AND_Y ) return CC_DLTUmode ; switch ( cond2 ) { case LTU : return CC_DLTUmode ; case LEU : return CC_DLEUmode ; case NE : return CC_DNEmode ; default : gcc_unreachable ( ) ; } case GTU : if ( cond_or == DOM_CC_X_AND_Y ) return CC_DGTUmode ; switch ( cond2 ) { case GTU : return CC_DGTUmode ; case GEU : return CC_DGEUmode ; case NE : return CC_DNEmode ; default : gcc_unreachable ( ) ; } case NE : gcc_assert ( cond1 == cond2 ) ; return CC_DNEmode ; case LE : gcc_assert ( cond1 == cond2 ) ; return CC_DLEmode ; case GE : gcc_assert ( cond1 == cond2 ) ; return CC_DGEmode ; case LEU : gcc_assert ( cond1 == cond2 ) ; return CC_DLEUmode ; case GEU : gcc_assert ( cond1 == cond2 ) ; return CC_DGEUmode ; default : gcc_unreachable ( ) ; } } </s>

Select a dominance comparison mode if possible for a test of the general form ( OP ( COND_OR ( X ) ( Y ) ) ( const_int 0 ) ) . We support three forms . COND_OR == DOM_CC_X_AND_Y = > ( X & & Y ) COND_OR == DOM_CC_NX_OR_Y = > ( ( ! X ) || Y ) COND_OR == DOM_CC_X_OR_Y = > ( X || Y ) In all cases OP will be either EQ or NE , but we do n't need to know which here . If we are unable to support a dominance comparison we return CC mode . This will then fail to match for the RTL expressions that generate this call .


<s> inline static rtx emit_set_insn ( rtx x , rtx y ) { return emit_insn ( gen_rtx_SET ( VOIDmode , x , y ) ) ; } </s>

Emit an insn that 's a simple single-set . Both the operands must be known to be valid .


<s> bool MipsTargetLowering :: isCheapToSpeculateCttz ( ) const { return Subtarget . hasMips32 ( ) ; } </s>

Return true if it is cheap to speculate a call to intrinsic cttz .


"loadRegFromStackSlot didn't insert any code!"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static rtx_insn * find_cond_jump ( rtx_insn * insn ) { for ( ; insn ; insn = NEXT_INSN ( insn ) ) { rtx ite , cc ; if ( LABEL_P ( insn ) ) break ; if ( ! JUMP_P ( insn ) ) { if ( reg_mentioned_p ( gen_rtx_REG ( CCmode , CC_REGNUM ) , insn ) ) break ; continue ; } if ( GET_CODE ( PATTERN ( insn ) ) != SET ) break ; gcc_assert ( SET_DEST ( PATTERN ( insn ) ) == pc_rtx ) ; ite = SET_SRC ( PATTERN ( insn ) ) ; if ( GET_CODE ( ite ) != IF_THEN_ELSE ) break ; cc = XEXP ( XEXP ( ite , 0 ) , 0 ) ; if ( ! REG_P ( cc ) || ! CC_REGNO_P ( REGNO ( cc ) ) ) break ; if ( find_reg_note ( insn , REG_DEAD , cc ) ) return insn ; break ; } return NULL ; } </s>

Starting from INSN find_cond_jump looks downwards in the insn stream for a single jump insn which is the last user of the condition code set in INSN .


<s> static bool arm_promote_prototypes ( tree t ATTRIBUTE_UNUSED ) { return ! TARGET_AAPCS_BASED ; } </s>

We ca n't rely on the caller doing the proper promotion when using APCS or ATPCS .


"SPARC DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> TargetPassConfig * UPTTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new UPTPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> FuncInfo ( ) : MemInstCount ( 0 ) , InstCount ( 0 ) , IAMInstCount ( 0 ) , LSMInstCount ( 0 ) { } </s>

Information about the function as a whole .


<s> Candidate ( MachineInstr * mi , Register reg , unsigned subreg , unsigned freebanks ) : MI ( mi ) , Reg ( reg ) , SubReg ( subreg ) , FreeBanks ( freebanks ) { } </s>


<s> unsigned F2003fRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return F2003f :: F5 ; } </s>


<s> unsigned ARMBaseRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case ARM :: tGPRRegClassID : return TFI -> hasFP ( MF ) ? 4 : 5 ; case ARM :: GPRRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 10 - FP - ( STI . isR9Reserved ( ) ? 1 : 0 ) ; } case ARM :: SPRRegClassID : case ARM :: DPRRegClassID : return 32 - 10 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> bool PPCTargetLowering :: SelectAddressRegReg ( SDValue N , SDValue & Base , SDValue & Index , SelectionDAG & DAG ) const { short imm = 0 ; if ( N . getOpcode ( ) == ISD :: ADD ) { if ( isIntS16Immediate ( N . getOperand ( 1 ) , imm ) ) return false ; if ( N . getOperand ( 1 ) . getOpcode ( ) == PPCISD :: Lo ) return false ; Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } else if ( N . getOpcode ( ) == ISD :: OR ) { if ( isIntS16Immediate ( N . getOperand ( 1 ) , imm ) ) return false ; APInt LHSKnownZero , LHSKnownOne ; APInt RHSKnownZero , RHSKnownOne ; DAG . computeKnownBits ( N . getOperand ( 0 ) , LHSKnownZero , LHSKnownOne ) ; if ( LHSKnownZero . getBoolValue ( ) ) { DAG . computeKnownBits ( N . getOperand ( 1 ) , RHSKnownZero , RHSKnownOne ) ; if ( ~ ( LHSKnownZero | RHSKnownZero ) == 0 ) { Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } } } return false ; } </s>

SelectAddressRegReg - Given the specified addressed , check to see if it can be more efficiently represented as [ r+imm ] .


<s> static enum mips_ucbranch_type mips_classify_branch_p6600 ( rtx_insn * insn ) { if ( ! insn || ! USEFUL_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == SEQUENCE ) return UC_UNDEFINED ; if ( get_attr_jal ( insn ) == JAL_INDIRECT || get_attr_type ( insn ) == TYPE_JUMP ) return UC_OTHER ; if ( CALL_P ( insn ) && get_attr_jal ( insn ) == JAL_DIRECT ) return UC_BALC ; return UC_UNDEFINED ; } </s>

Subroutine of mips_avoid_hazard . We classify unconditional branches of interest for the P6600 for performance reasons . We 're interested in differentiating BALC from JIC , JIALC and BC .


<s> bool enableMachineScheduler ( ) const override { return isCheri ( ) || isBeri ( ) ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


"multiple save register attributes to function %qD"

"multiple nested types attributes to function %qD"

"multiple interrupt attributes to function %qD"

"cannot use interrupt attributes to function %qD "

"cannot use exception attributes to function %qD "

"cannot use reset attributes to function %qD "

Function for nds32_merge_decl_attributes ( ) and nds32_insert_attributes ( ) to check if there are any conflict isr-specific attributes being set . We need to check : 1 . Only 'save_all ' or 'partial_save ' in the attributes . 2 . Only 'nested ' , 'not_nested ' , or 'nested_ready ' in the attributes . 3 . Only 'interrupt ' , 'exception ' , or 'reset ' in the attributes .


This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
static
MCSymbol
*
GetSymbolFromOperand
(
const
MachineOperand
&
MO
,
AsmPrinter
&
AP
)
{
const
TargetMachine
&
TM
=
AP
.
TM
;
Mangler
*
Mang
=
AP
.
Mang
;
const
DataLayout
*
DL
=
TM
.
getDataLayout
(
)
;
MCContext
&
Ctx
=
AP
.
OutContext
;
bool
isDarwin
=
Triple
(
TM
.
getTargetTriple
(
)
)
.
isOSDarwin
(
)
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
)
{
if
(
isDarwin
)
Suffix
=
"$stub"
;
}
else
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
Suffix
=
"$non_lazy_ptr"
;
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
->
getPrivateGlobalPrefix
(
)
;
unsigned
PrefixLen
=
Name
.
size
(
)
;
if
(
!
MO
.
isGlobal
(
)
)
{
assert
(
MO
.
isSymbol
(
)
&&
"Isn't a symbol reference"
)
;
Mang
->
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
)
;
}
else
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
TM
.
getNameWithPrefix
(
Name
,
GV
,
*
Mang
)
;
}
unsigned
OrigLen
=
Name
.
size
(
)
PrefixLen
;
Name
+=
Suffix
;
MCSymbol
*
Sym
=
Ctx
.
GetOrCreateSymbol
(
Name
)
;
StringRef
OrigName
=
StringRef
(
Name
)
.
substr
(
PrefixLen
,
OrigLen
)
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
&&
isDarwin
)
{
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
getMachOMMI
(
AP
)
.
getFnStubEntry
(
Sym
)
;
if
(
StubSym
.
getPointer
(
)
)
return
Sym
;
if
(
MO
.
isGlobal
(
)
)
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
else
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
Ctx
.
GetOrCreateSymbol
(
OrigName
)
,
false
)
;
}
return
Sym
;
}
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
{
MachineModuleInfoMachO
&
MachO
=
getMachOMMI
(
AP
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_HIDDEN_FLAG
)
MachO
.
getHiddenGVStubEntry
(
Sym
)
:
MachO
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
return
Sym
;
}
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


<s> void X86FrameLowering :: emitCalleeSavedFrameMovesFullCFA ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) const { MachineFunction & MF = * MBB . getParent ( ) ; if ( ! hasFP ( MF ) ) { emitCalleeSavedFrameMoves ( MBB , MBBI , DebugLoc { } , true ) ; return ; } const MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; const Register FramePtr = TRI -> getFrameRegister ( MF ) ; const Register MachineFramePtr = STI . isTarget64BitILP32 ( ) ? Register ( getX86SubSuperRegister ( FramePtr , 64 ) ) : FramePtr ; unsigned DwarfReg = MRI -> getDwarfRegNum ( MachineFramePtr , true ) ; unsigned Offset = ( Is64Bit ? 8 : 4 ) + ( Uses64BitFramePtr ? 8 : 4 ) ; BuildCFI ( MBB , MBBI , DebugLoc { } , MCCFIInstruction :: createOffset ( nullptr , DwarfReg , - Offset ) ) ; emitCalleeSavedFrameMoves ( MBB , MBBI , DebugLoc { } , true ) ; } </s>

Emits Dwarf Info specifying offsets of callee saved registers and frame pointer .


<s> void R600InstrInfo :: reserveIndirectRegisters ( BitVector & Reserved , const MachineFunction & MF ) const { const AMDGPUFrameLowering * TFL = static_cast < const AMDGPUFrameLowering * > ( TM . getFrameLowering ( ) ) ; unsigned StackWidth = TFL -> getStackWidth ( MF ) ; int End = getIndirectIndexEnd ( MF ) ; if ( End == - 1 ) return ; for ( int Index = getIndirectIndexBegin ( MF ) ; Index <= End ; ++ Index ) { unsigned SuperReg = AMDGPU :: R600_Reg128RegClass . getRegister ( Index ) ; Reserved . set ( SuperReg ) ; for ( unsigned Chan = 0 ; Chan < StackWidth ; ++ Chan ) { unsigned Reg = AMDGPU :: R600_TReg32RegClass . getRegister ( ( 4 * Index ) + Chan ) ; Reserved . set ( Reg ) ; } } } </s>

Reserve the registers that may be accessed using indirect addressing .


<s> bool isReg ( ) const override { return Kind == KindTy :: Register ; } </s>


<s> bool RISCVInstructionSelector :: select ( MachineInstr & I ) { if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) { return true ; } if ( selectImpl ( I , * CoverageInfo ) ) return true ; return false ; } </s>

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s> static void rs6000_set_sched_context ( void * _sc ) { rs6000_sched_context_t sc = ( rs6000_sched_context_t ) _sc ; gcc_assert ( sc != NULL ) ; cached_can_issue_more = sc -> cached_can_issue_more ; last_scheduled_insn = sc -> last_scheduled_insn ; load_store_pendulum = sc -> load_store_pendulum ; divide_cnt = sc -> divide_cnt ; vec_pairing = sc -> vec_pairing ; } </s>

Sets the global scheduling context to the one pointed to by _SC .


<s> static bool m32r_in_small_data_p ( const_tree decl ) { const char * section ; if ( TREE_CODE ( decl ) != VAR_DECL ) return false ; if ( lookup_attribute ( "model" , DECL_ATTRIBUTES ( decl ) ) ) return false ; section = DECL_SECTION_NAME ( decl ) ; if ( section ) { if ( strcmp ( section , ".sdata" ) == 0 || strcmp ( section , ".sbss" ) == 0 ) return true ; } else { if ( ! TREE_READONLY ( decl ) && ! TARGET_SDATA_NONE ) { int size = int_size_in_bytes ( TREE_TYPE ( decl ) ) ; if ( size > 0 && size <= g_switch_value ) return true ; } } return false ; } </s>

Only mark the object as being small data area addressable if it has n't been explicitly marked with a code model . The user can explicitly put an object in the small data area with the section attribute . If the object is in sdata/sbss and marked with a code model do both [ put the object in .sdata and mark it as being addressed with a specific code model - do n't mark it as being addressed with an SDA reloc though ] . This is ok and might be useful at times . If the object does n't fit the linker will give an error .


<s> void AMDGPUTTIImpl :: getUnrollingPreferences ( Loop * L , TTI :: UnrollingPreferences & UP ) { UP . Threshold = 300 ; UP . MaxCount = UINT_MAX ; UP . Partial = true ; for ( const BasicBlock * BB : L -> getBlocks ( ) ) { const DataLayout & DL = BB -> getModule ( ) -> getDataLayout ( ) ; for ( const Instruction & I : * BB ) { const GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( & I ) ; if ( ! GEP || GEP -> getAddressSpace ( ) != AMDGPUAS :: PRIVATE_ADDRESS ) continue ; const Value * Ptr = GEP -> getPointerOperand ( ) ; const AllocaInst * Alloca = dyn_cast < AllocaInst > ( GetUnderlyingObject ( Ptr , DL ) ) ; if ( Alloca ) { UP . Threshold = 800 ; } } } } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s>
unsigned
LanaiTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
SelectionDAG
&
DAG
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"pc"
,
Lanai
::
PC
)
.
Case
(
"sp"
,
Lanai
::
SP
)
.
Case
(
"fp"
,
Lanai
::
FP
)
.
Case
(
"rr1"
,
Lanai
::
RR1
)
.
Case
(
"r10"
,
Lanai
::
R10
)
.
Case
(
"rr2"
,
Lanai
::
RR2
)
.
Case
(
"r11"
,
Lanai
::
R11
)
.
Case
(
"rca"
,
Lanai
::
RCA
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> static bool m68k_legitimate_constant_address_p ( rtx x , unsigned int reach , bool strict_p ) { rtx base , offset ; if ( ! CONSTANT_ADDRESS_P ( x ) ) return false ; if ( flag_pic && ! ( strict_p && TARGET_PCREL ) && symbolic_operand ( x , VOIDmode ) ) return false ; if ( M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P && reach > 1 ) { split_const ( x , & base , & offset ) ; if ( GET_CODE ( base ) == SYMBOL_REF && ! offset_within_block_p ( base , INTVAL ( offset ) + reach - 1 ) ) return false ; } return ! m68k_tls_reference_p ( x , false ) ; } </s>

Return true if X is a legitimate constant address that can reach bytes in the range [ X , X + REACH ) . STRICT_P says whether we need strict checking .


<s> const MCPhysReg * XCoreRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const MCPhysReg CalleeSavedRegs [ ] = { XCore :: R4 , XCore :: R5 , XCore :: R6 , XCore :: R7 , XCore :: R8 , XCore :: R9 , XCore :: R10 , 0 } ; static const MCPhysReg CalleeSavedRegsFP [ ] = { XCore :: R4 , XCore :: R5 , XCore :: R6 , XCore :: R7 , XCore :: R8 , XCore :: R9 , 0 } ; const TargetFrameLowering * TFI = MF -> getTarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( * MF ) ) return CalleeSavedRegsFP ; return CalleeSavedRegs ; } </s>


<s> bool WebAssemblySubtarget :: enableMachineScheduler ( ) const { return false ; } </s>


<s> static const char * reg_name_with_mode ( int regno , enum machine_mode mode ) { int mlen = GET_MODE_SIZE ( mode ) ; if ( regno == R0_REGNO && mlen == 1 ) return "r0l" ; if ( regno == R0_REGNO && ( mlen == 3 || mlen == 4 ) ) return "r2r0" ; if ( regno == R0_REGNO && mlen == 6 ) return "r2r1r0" ; if ( regno == R0_REGNO && mlen == 8 ) return "r3r1r2r0" ; if ( regno == R1_REGNO && mlen == 1 ) return "r1l" ; if ( regno == R1_REGNO && ( mlen == 3 || mlen == 4 ) ) return "r3r1" ; if ( regno == A0_REGNO && TARGET_A16 && ( mlen == 3 || mlen == 4 ) ) return "a1a0" ; return reg_names [ regno ] ; } </s>

Since register names indicate the mode they 're used in , we need a way to determine which name to refer to the register with . Called by print_operand ( ) .


<s>
void
AlphaFrameLowering
::
emitPrologue
(
MachineFunction
&
MF
)
const
{
MachineBasicBlock
&
MBB
=
MF
.
front
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getTarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
dl
=
(
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
(
)
)
;
bool
FP
=
hasFP
(
MF
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
LDAHg
)
,
Alpha
::
R29
)
.
addGlobalAddress
(
MF
.
getFunction
(
)
)
.
addReg
(
Alpha
::
R27
)
.
addImm
(
++
curgpdist
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
LDAg
)
,
Alpha
::
R29
)
.
addGlobalAddress
(
MF
.
getFunction
(
)
)
.
addReg
(
Alpha
::
R29
)
.
addImm
(
curgpdist
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
ALTENT
)
)
.
addGlobalAddress
(
MF
.
getFunction
(
)
)
;
long
NumBytes
=
MFI
->
getStackSize
(
)
;
if
(
FP
)
NumBytes
+=
8
;
if
(
NumBytes
==
0
)
return
;
unsigned
Align
=
getStackAlignment
(
)
;
NumBytes
=
(
NumBytes
+
Align
1
)
/
Align
*
Align
;
MFI
->
setStackSize
(
NumBytes
)
;
NumBytes
=
NumBytes
;
if
(
NumBytes
>=
Alpha
::
IMM_LOW
)
{
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
LDA
)
,
Alpha
::
R30
)
.
addImm
(
NumBytes
)
.
addReg
(
Alpha
::
R30
)
;
}
else
if
(
getUpper16
(
NumBytes
)
>=
Alpha
::
IMM_LOW
)
{
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
LDAH
)
,
Alpha
::
R30
)
.
addImm
(
getUpper16
(
NumBytes
)
)
.
addReg
(
Alpha
::
R30
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
LDA
)
,
Alpha
::
R30
)
.
addImm
(
getLower16
(
NumBytes
)
)
.
addReg
(
Alpha
::
R30
)
;
}
else
{
report_fatal_error
(
"Too big a stack frame at "
+
Twine
(
NumBytes
)
)
;
}
if
(
FP
)
{
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
STQ
)
)
.
addReg
(
Alpha
::
R15
)
.
addImm
(
0
)
.
addReg
(
Alpha
::
R30
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
BISr
)
,
Alpha
::
R15
)
.
addReg
(
Alpha
::
R30
)
.
addReg
(
Alpha
::
R30
)
;
}
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool canCauseFpMLxStall ( unsigned Opcode ) const { return MLxHazardOpcodes . count ( Opcode ) ; } </s>

canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when scheduled after ( within 4-cycle window ) a fp MLA / MLS instruction .


<s> const char * arm_strip_name_encoding ( const char * name ) { int skip ; while ( ( skip = arm_get_strip_length ( * name ) ) ) name += skip ; return name ; } </s>

Return a pointer to a function 's name with any and all prefix encodings stripped from it .


<s>
void
ATTRIBUTE_UNUSED
ix86_debug_options
(
void
)
{
char
*
opts
=
ix86_target_string
(
ix86_isa_flags
,
target_flags
,
ix86_arch_string
,
ix86_tune_string
,
ix86_fpmath
,
true
)
;
if
(
opts
)
{
fprintf
(
stderr
,
"%s\n\n"
,
opts
)
;
free
(
opts
)
;
}
else
fputs
(
"<no options>\n\n"
,
stderr
)
;
return
;
}
</s>

Function that is callable from the debugger to print the current options .


<s> void print ( raw_ostream & OS ) const override { } </s>

print - Print a debug representation of the operand to the given stream .


<s> unsigned char PPCSubtarget :: classifyGlobalReference ( const GlobalValue * GV ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return PPCII :: MO_PIC_FLAG | PPCII :: MO_NLP_FLAG ; if ( TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return PPCII :: MO_PIC_FLAG ; return PPCII :: MO_PIC_FLAG | PPCII :: MO_NLP_FLAG ; } </s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s> void AArch64ConditionOptimizer :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < LiveIntervals > ( ) ; AU . addPreserved < LiveIntervals > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static bool xtensa_cannot_force_const_mem ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { return xtensa_tls_referenced_p ( x ) ; } </s>


<s> void ix86_split_fp_branch ( enum rtx_code code , rtx op1 , rtx op2 , rtx target1 , rtx target2 , rtx tmp ) { rtx condition ; rtx_insn * i ; if ( target2 != pc_rtx ) { std :: swap ( target1 , target2 ) ; code = reverse_condition_maybe_unordered ( code ) ; } condition = ix86_expand_fp_compare ( code , op1 , op2 , tmp ) ; i = emit_jump_insn ( gen_rtx_SET ( pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , condition , target1 , target2 ) ) ) ; if ( split_branch_probability >= 0 ) add_int_reg_note ( i , REG_BR_PROB , split_branch_probability ) ; } </s>

Split branch based on floating point condition .


<s> void GCNPassConfig :: addPreEmitPass ( ) { addPass ( & PostRAHazardRecognizerID ) ; addPass ( createSIInsertWaitsPass ( ) ) ; addPass ( createSIShrinkInstructionsPass ( ) ) ; addPass ( createSILowerControlFlowPass ( ) ) ; addPass ( createSIDebuggerInsertNopsPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static rtx pru_function_value ( const_tree ret_type , const_tree fn ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( TYPE_MODE ( ret_type ) , FIRST_RETVAL_REGNUM ) ; } </s>


<s> bool ARMTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , MachineMemOperand :: Flags , bool * Fast ) const { if ( ! VT . isSimple ( ) ) return false ; bool AllowsUnaligned = Subtarget -> allowsUnalignedMem ( ) ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : { if ( AllowsUnaligned ) { if ( Fast ) * Fast = Subtarget -> hasV7Ops ( ) ; return true ; } return false ; } case MVT :: f64 : case MVT :: v2f64 : { if ( Subtarget -> hasNEON ( ) && ( AllowsUnaligned || Subtarget -> isLittle ( ) ) ) { if ( Fast ) * Fast = true ; return true ; } return false ; } } } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> MachineMemOperand :: Flags SystemZTargetLowering :: getTargetMMOFlags ( const Instruction & I ) const { if ( auto * SI = dyn_cast < StoreInst > ( & I ) ) if ( SI -> isAtomic ( ) ) return MachineMemOperand :: MOVolatile ; if ( auto * LI = dyn_cast < LoadInst > ( & I ) ) if ( LI -> isAtomic ( ) ) return MachineMemOperand :: MOVolatile ; if ( auto * AI = dyn_cast < AtomicRMWInst > ( & I ) ) if ( AI -> isAtomic ( ) ) return MachineMemOperand :: MOVolatile ; if ( auto * AI = dyn_cast < AtomicCmpXchgInst > ( & I ) ) if ( AI -> isAtomic ( ) ) return MachineMemOperand :: MOVolatile ; return MachineMemOperand :: MONone ; } </s>

This callback is used to inspect load/store instructions and add target-specific MachineMemOperand flags to them .


<s> static int avr_naked_function_p ( tree func ) { tree a ; gcc_assert ( TREE_CODE ( func ) == FUNCTION_DECL ) ; a = lookup_attribute ( "naked" , DECL_ATTRIBUTES ( func ) ) ; return a != NULL_TREE ; } </s>

Return non-zero if FUNC is a naked function .


<s> bool HexagonOptAddrMode :: isValidOffset ( MachineInstr * MI , int Offset ) { unsigned AlignMask = 0 ; switch ( HII -> getMemAccessSize ( * MI ) ) { case HexagonII :: MemAccessSize :: DoubleWordAccess : AlignMask = 0x7 ; break ; case HexagonII :: MemAccessSize :: WordAccess : AlignMask = 0x3 ; break ; case HexagonII :: MemAccessSize :: HalfWordAccess : AlignMask = 0x1 ; break ; case HexagonII :: MemAccessSize :: ByteAccess : AlignMask = 0x0 ; break ; default : return false ; } if ( ( AlignMask & Offset ) != 0 ) return false ; return HII -> isValidOffset ( MI -> getOpcode ( ) , Offset , HRI , false ) ; } </s>


";; loop %d start_label not before loop_end\n"

A callback for the hw-doloop pass . Called to optimize LOOP in a machine-specific fashion ; returns true if successful and false if the hwloop_fail function should be called .


<s> void MipsGOT :: reserve ( size_t pNum ) { for ( size_t i = 0 ; i < pNum ; ++ i ) createEntry ( 0 , m_SectionData ) ; } </s>

Grow the map so that it has at least Size buckets . Does not shrink .


"Callee saved registers requested for unknown architecture "


<s> bool isSubregFoldable ( ) const override { return true ; } </s>

Check whether the target can fold a load that feeds a subreg operand ( or a subreg operand that feeds a store ) .


<s>
StringRef
getPassName
(
)
const
override
{
return
"LoongArch Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
const
char
*
output_probe_stack_range
(
rtx
reg1
,
rtx
reg2
)
{
static
int
labelno
=
0
;
char
loop_lab
[
32
]
,
end_lab
[
32
]
;
rtx
xops
[
2
]
;
ASM_GENERATE_INTERNAL_LABEL
(
loop_lab
,
"LPSRL"
,
labelno
)
;
ASM_GENERATE_INTERNAL_LABEL
(
end_lab
,
"LPSRE"
,
labelno
++
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
loop_lab
)
;
xops
[
0
]
=
reg1
;
xops
[
1
]
=
reg2
;
if
(
TARGET_64BIT
)
output_asm_insn
(
"cmpd 0,%0,%1"
,
xops
)
;
else
output_asm_insn
(
"cmpw 0,%0,%1"
,
xops
)
;
fputs
(
"\tbeq 0,"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
end_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
xops
[
1
]
=
GEN_INT
(
PROBE_INTERVAL
)
;
output_asm_insn
(
"addi %0,%0,%1"
,
xops
)
;
xops
[
1
]
=
gen_rtx_REG
(
Pmode
,
0
)
;
output_asm_insn
(
"stw %1,0(%0)"
,
xops
)
;
fprintf
(
asm_out_file
,
"\tb "
)
;
assemble_name_raw
(
asm_out_file
,
loop_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
end_lab
)
;
return
""
;
}
</s>

Wrapper around the output_probe_stack_range routines .


<s>
StackOffset
AArch64FrameLowering
::
getFrameIndexReferencePreferSP
(
const
MachineFunction
&
MF
,
int
FI
,
Register
&
FrameReg
,
bool
IgnoreSPUpdates
)
const
{
const
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
if
(
IgnoreSPUpdates
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Offset from the SP for "
<<
FI
<<
" is "
<<
MFI
.
getObjectOffset
(
FI
)
<<
"\n"
)
;
FrameReg
=
AArch64
::
SP
;
return
StackOffset
::
getFixed
(
MFI
.
getObjectOffset
(
FI
)
)
;
}
if
(
MFI
.
hasVarSizedObjects
(
)
||
MF
.
getInfo
<
AArch64FunctionInfo
>
(
)
->
getStackSizeSVE
(
)
||
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
->
hasStackRealignment
(
MF
)
)
return
getFrameIndexReference
(
MF
,
FI
,
FrameReg
)
;
FrameReg
=
AArch64
::
SP
;
return
getStackOffset
(
MF
,
MFI
.
getObjectOffset
(
FI
)
)
;
}
</s>

Same as getFrameIndexReference , except that the stack pointer ( as opposed to the frame pointer ) will be the preferred value for FrameReg .


<s> unsigned getFlatAddressSpace ( ) const { if ( IsGraphicsShader ) return - 1 ; return ST -> hasFlatAddressSpace ( ) ? ST -> getAMDGPUAS ( ) . FLAT_ADDRESS : ST -> getAMDGPUAS ( ) . UNKNOWN_ADDRESS_SPACE ; } </s>

Returns the address space ID for a target 's 'flat ' address space .


<s>
MachineBasicBlock
*
GBZ80TargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
MBB
)
const
{
llvm_unreachable
(
"Custom inserters are disabled."
)
;
return
nullptr
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .

GBZ80
GB
"Custom inserters are disabled."


<s> void AMDGPUAsmPrinter :: emitStartOfAsmFile ( Module & M ) { if ( getTargetStreamer ( ) && ! getTargetStreamer ( ) -> getTargetID ( ) ) initializeTargetID ( M ) ; if ( TM . getTargetTriple ( ) . getOS ( ) != Triple :: AMDHSA && TM . getTargetTriple ( ) . getOS ( ) != Triple :: AMDPAL ) return ; if ( isHsaAbiVersion3AndAbove ( getGlobalSTI ( ) ) ) getTargetStreamer ( ) -> EmitDirectiveAMDGCNTarget ( ) ; if ( TM . getTargetTriple ( ) . getOS ( ) == Triple :: AMDHSA ) HSAMetadataStream -> begin ( M , * getTargetStreamer ( ) -> getTargetID ( ) ) ; if ( TM . getTargetTriple ( ) . getOS ( ) == Triple :: AMDPAL ) getTargetStreamer ( ) -> getPALMetadata ( ) -> readFromIR ( M ) ; if ( isHsaAbiVersion3AndAbove ( getGlobalSTI ( ) ) ) return ; if ( TM . getTargetTriple ( ) . getOS ( ) == Triple :: AMDHSA ) getTargetStreamer ( ) -> EmitDirectiveHSACodeObjectVersion ( 2 , 1 ) ; IsaVersion Version = getIsaVersion ( getGlobalSTI ( ) -> getCPU ( ) ) ; getTargetStreamer ( ) -> EmitDirectiveHSACodeObjectISAV2 ( Version . Major , Version . Minor , Version . Stepping , "AMD" , "AMDGPU" ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the start of their file .


<s> InstructionCost AArch64TTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * DataTy , const Value * Ptr , bool VariableMask , Align Alignment , TTI :: TargetCostKind CostKind , const Instruction * I ) { if ( useNeonVector ( DataTy ) ) return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , CostKind , I ) ; auto * VT = cast < VectorType > ( DataTy ) ; auto LT = TLI -> getTypeLegalizationCost ( DL , DataTy ) ; if ( ! LT . first . isValid ( ) ) return InstructionCost :: getInvalid ( ) ; if ( cast < VectorType > ( DataTy ) -> getElementCount ( ) == ElementCount :: getScalable ( 1 ) ) return InstructionCost :: getInvalid ( ) ; ElementCount LegalVF = LT . second . getVectorElementCount ( ) ; InstructionCost MemOpCost = getMemoryOpCost ( Opcode , VT -> getElementType ( ) , Alignment , 0 , CostKind , I ) ; return LT . first * MemOpCost * getMaxNumElements ( LegalVF , I -> getFunction ( ) ) ; } </s>

Calculate the cost of Gather / Scatter operation .


<s> void AMDGPUCFGStructurizer :: removeSuccessor ( MachineBasicBlock * MBB ) { while ( MBB -> succ_size ( ) ) MBB -> removeSuccessor ( * MBB -> succ_begin ( ) ) ; } </s>

Remove specified successor from the successors list of this MachineBasicBlock .


<s> bool HexagonBitSimplify :: isZero ( const BitTracker :: RegisterCell & RC , uint16_t B , uint16_t W ) { assert ( B < RC . width ( ) && B + W <= RC . width ( ) ) ; for ( uint16_t i = B ; i < B + W ; ++ i ) if ( ! RC [ i ] . is ( 0 ) ) return false ; return true ; } </s>

Return true if the expression is a constant zero .


<s> bool X86AsmBackend :: shouldForceRelocation ( const MCAssembler & , const MCFixup & Fixup , const MCValue & ) { return Fixup . getKind ( ) == FK_NONE ; } </s>

Hook to check if a relocation is needed for some target specific reason .


<s>
const
MCPhysReg
*
AArch64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
CFGuard_Check
)
return
CSR_Win_AArch64_CFGuard_Check_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetWindows
(
)
)
return
CSR_Win_AArch64_AAPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_AArch64_NoRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_AArch64_AllRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_VectorCall
)
return
CSR_AArch64_AAVPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_SVE_VectorCall
)
return
CSR_AArch64_SVE_AAPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
CXX_FAST_TLS
)
return
MF
->
getInfo
<
AArch64FunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_AArch64_CXX_TLS_Darwin_PE_SaveList
:
CSR_AArch64_CXX_TLS_Darwin_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
.
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_AArch64_AAPCS_SwiftError_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
PreserveMost
)
return
CSR_AArch64_RT_MostRegs_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetDarwin
(
)
)
return
CSR_Darwin_AArch64_AAPCS_SaveList
;
return
CSR_AArch64_AAPCS_SaveList
;
}
</s>


<s> static tree ix86_vectorize_builtin_scatter ( const_tree vectype , const_tree index_type , int scale ) { bool si ; enum ix86_builtins code ; if ( ! TARGET_AVX512F ) return NULL_TREE ; if ( ( TREE_CODE ( index_type ) != INTEGER_TYPE && ! POINTER_TYPE_P ( index_type ) ) || ( TYPE_MODE ( index_type ) != SImode && TYPE_MODE ( index_type ) != DImode ) ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) > POINTER_SIZE ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) < POINTER_SIZE && TYPE_UNSIGNED ( index_type ) ) return NULL_TREE ; if ( scale <= 0 || scale > 8 || ( scale & ( scale - 1 ) ) != 0 ) return NULL_TREE ; si = TYPE_MODE ( index_type ) == SImode ; switch ( TYPE_MODE ( vectype ) ) { case E_V8DFmode : code = si ? IX86_BUILTIN_SCATTERALTSIV8DF : IX86_BUILTIN_SCATTERDIV8DF ; break ; case E_V8DImode : code = si ? IX86_BUILTIN_SCATTERALTSIV8DI : IX86_BUILTIN_SCATTERDIV8DI ; break ; case E_V16SFmode : code = si ? IX86_BUILTIN_SCATTERSIV16SF : IX86_BUILTIN_SCATTERALTDIV16SF ; break ; case E_V16SImode : code = si ? IX86_BUILTIN_SCATTERSIV16SI : IX86_BUILTIN_SCATTERALTDIV16SI ; break ; case E_V4DFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERALTSIV4DF : IX86_BUILTIN_SCATTERDIV4DF ; else return NULL_TREE ; break ; case E_V4DImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERALTSIV4DI : IX86_BUILTIN_SCATTERDIV4DI ; else return NULL_TREE ; break ; case E_V8SFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERSIV8SF : IX86_BUILTIN_SCATTERALTDIV8SF ; else return NULL_TREE ; break ; case E_V8SImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERSIV8SI : IX86_BUILTIN_SCATTERALTDIV8SI ; else return NULL_TREE ; break ; case E_V2DFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERALTSIV2DF : IX86_BUILTIN_SCATTERDIV2DF ; else return NULL_TREE ; break ; case E_V2DImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERALTSIV2DI : IX86_BUILTIN_SCATTERDIV2DI ; else return NULL_TREE ; break ; case E_V4SFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERSIV4SF : IX86_BUILTIN_SCATTERALTDIV4SF ; else return NULL_TREE ; break ; case E_V4SImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERSIV4SI : IX86_BUILTIN_SCATTERALTDIV4SI ; else return NULL_TREE ; break ; default : return NULL_TREE ; } return get_ix86_builtin ( code ) ; } </s>

Returns a decl of a function that implements scatter store with register type VECTYPE and index type INDEX_TYPE and SCALE . Return NULL_TREE if it is not available .


<s> MachineBasicBlock :: iterator Thumb1FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const Thumb1InstrInfo & TII = * static_cast < const Thumb1InstrInfo * > ( STI . getInstrInfo ( ) ) ; const ThumbRegisterInfo * RegInfo = static_cast < const ThumbRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr & Old = * I ; DebugLoc dl = Old . getDebugLoc ( ) ; unsigned Amount = Old . getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { unsigned Align = getStackAlignment ( ) ; Amount = ( Amount + Align - 1 ) / Align * Align ; unsigned Opc = Old . getOpcode ( ) ; if ( Opc == ARM :: ADJCALLSTACKDOWN || Opc == ARM :: tADJCALLSTACKDOWN ) { emitSPUpdate ( MBB , I , TII , dl , * RegInfo , - Amount ) ; } else { assert ( Opc == ARM :: ADJCALLSTACKUP || Opc == ARM :: tADJCALLSTACKUP ) ; emitSPUpdate ( MBB , I , TII , dl , * RegInfo , Amount ) ; } } } return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static rtx get_thread_pointer ( machine_mode tp_mode , bool to_reg ) { rtx tp = gen_rtx_UNSPEC ( ptr_mode , gen_rtvec ( 1 , const0_rtx ) , UNSPEC_TP ) ; if ( GET_MODE ( tp ) != tp_mode ) { gcc_assert ( GET_MODE ( tp ) == SImode ) ; gcc_assert ( tp_mode == DImode ) ; tp = gen_rtx_ZERO_EXTEND ( tp_mode , tp ) ; } if ( to_reg ) tp = copy_to_mode_reg ( tp_mode , tp ) ; return tp ; } </s>

Load the thread pointer . If TO_REG is true , force it into a register .


"Do not know how to custom type legalize this operation!"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> bool Thumb1InstrInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( ARM :: tPUSH ) ) ; AddDefaultPred ( MIB ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


"Encountered a global variable kind that is "

Emit the specified global variable to the .s file .


"Trying RISCV32Only_16 table (16-bit Instruction):\n"

"Trying RVBC32 table (BitManip 16-bit Instruction):\n"

"Trying RISCV_C table (16-bit Instruction):\n"

Returns the disassembly of a single instruction .


<s> tree aarch64_general_builtin_rsqrt ( unsigned int fn ) { if ( fn == AARCH64_SIMD_BUILTIN_UNOP_sqrtv2df ) return aarch64_builtin_decls [ AARCH64_BUILTIN_RSQRT_V2DF ] ; if ( fn == AARCH64_SIMD_BUILTIN_UNOP_sqrtv2sf ) return aarch64_builtin_decls [ AARCH64_BUILTIN_RSQRT_V2SF ] ; if ( fn == AARCH64_SIMD_BUILTIN_UNOP_sqrtv4sf ) return aarch64_builtin_decls [ AARCH64_BUILTIN_RSQRT_V4SF ] ; return NULL_TREE ; } </s>

Return builtin for reciprocal square root .


<s> static void s390_register_info ( ) { int i ; char clobbered_regs [ 32 ] ; gcc_assert ( ! epilogue_completed ) ; if ( reload_completed ) s390_regs_ever_clobbered ( clobbered_regs ) ; else for ( i = 0 ; i < 32 ; i ++ ) clobbered_regs [ i ] = df_regs_ever_live_p ( i ) ; for ( i = 0 ; i < 32 ; i ++ ) clobbered_regs [ i ] = clobbered_regs [ i ] && ! global_regs [ i ] ; cfun_frame_layout . fpr_bitmap = 0 ; cfun_frame_layout . high_fprs = 0 ; for ( i = FPR0_REGNUM ; i <= FPR15_REGNUM ; i ++ ) if ( clobbered_regs [ i ] && ! call_really_used_regs [ i ] ) { cfun_set_fpr_save ( i ) ; if ( i >= FPR8_REGNUM ) cfun_frame_layout . high_fprs ++ ; } clobbered_regs [ 12 ] |= ( ( flag_pic && df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) ) || ( flag_split_stack && cfun -> stdarg && ( crtl -> is_leaf || TARGET_TPF_PROFILING || has_hard_reg_initial_val ( Pmode , RETURN_REGNUM ) ) ) ) ; clobbered_regs [ BASE_REGNUM ] |= ( cfun -> machine -> base_reg && REGNO ( cfun -> machine -> base_reg ) == BASE_REGNUM ) ; clobbered_regs [ HARD_FRAME_POINTER_REGNUM ] |= ! ! frame_pointer_needed ; clobbered_regs [ RETURN_REGNUM ] |= ( ! crtl -> is_leaf || TARGET_TPF_PROFILING || cfun_frame_layout . save_return_addr_p || crtl -> calls_eh_return ) ; clobbered_regs [ STACK_POINTER_REGNUM ] |= ( ! crtl -> is_leaf || TARGET_TPF_PROFILING || cfun_save_high_fprs_p || get_frame_size ( ) > 0 || ( reload_completed && cfun_frame_layout . frame_size > 0 ) || cfun -> calls_alloca ) ; memset ( cfun_frame_layout . gpr_save_slots , SAVE_SLOT_NONE , 16 ) ; for ( i = 6 ; i < 16 ; i ++ ) if ( clobbered_regs [ i ] ) cfun_gpr_save_slot ( i ) = SAVE_SLOT_STACK ; s390_register_info_stdarg_fpr ( ) ; s390_register_info_gprtofpr ( ) ; s390_register_info_set_ranges ( ) ; s390_register_info_stdarg_gpr ( ) ; } </s>

Fill cfun- > machine with info about register usage of current function . Return in CLOBBERED_REGS which GPRs are currently considered set .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
(
Kind
==
k_Register
||
Kind
==
k_Memri
)
&&
"Invalid access!"
)
;
return
RegImm
.
Reg
;
}
</s>

Returns the register associated with this edge .


<s>
bool
X86TargetLowering
::
shouldReduceLoadWidth
(
SDNode
*
Load
,
ISD
::
LoadExtType
ExtTy
,
EVT
NewVT
)
const
{
assert
(
cast
<
LoadSDNode
>
(
Load
)
->
isSimple
(
)
&&
"illegal to narrow"
)
;
SDValue
BasePtr
=
cast
<
LoadSDNode
>
(
Load
)
->
getBasePtr
(
)
;
if
(
BasePtr
.
getOpcode
(
)
==
X86ISD
::
WrapperRIP
)
if
(
const
auto
*
GA
=
dyn_cast
<
GlobalAddressSDNode
>
(
BasePtr
.
getOperand
(
0
)
)
)
return
GA
->
getTargetFlags
(
)
!=
X86II
::
MO_GOTTPOFF
;
EVT
VT
=
Load
->
getValueType
(
0
)
;
if
(
(
VT
.
is256BitVector
(
)
||
VT
.
is512BitVector
(
)
)
&&
!
Load
->
hasOneUse
(
)
)
{
for
(
auto
UI
=
Load
->
use_begin
(
)
,
UE
=
Load
->
use_end
(
)
;
UI
!=
UE
;
++
UI
)
{
if
(
UI
.
getUse
(
)
.
getResNo
(
)
!=
0
)
continue
;
if
(
UI
->
getOpcode
(
)
!=
ISD
::
EXTRACT_SUBVECTOR
||
!
UI
->
hasOneUse
(
)
||
UI
->
use_begin
(
)
->
getOpcode
(
)
!=
ISD
::
STORE
)
return
true
;
}
return
false
;
}
return
true
;
}
</s>

Return true if we believe it is correct and profitable to reduce the load node to a smaller type .


<s> void StackPU2AsmPrinter :: emitInstruction ( const MachineInstr * MI ) { StackPU2MCInstLower MCInstLowering ( OutContext , * this ) ; MCInst I ; MCInstLowering . lowerInstruction ( * MI , I ) ; EmitToStreamer ( * OutStreamer , I ) ; } </s>

Targets should implement this to emit instructions .


<s> unsigned VEInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . getOpcode ( ) == VE :: STSri || MI . getOpcode ( ) == VE :: STLri || MI . getOpcode ( ) == VE :: STUri ) { if ( MI . getOperand ( 0 ) . isFI ( ) && MI . getOperand ( 1 ) . isImm ( ) && MI . getOperand ( 1 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 0 ) . getIndex ( ) ; return MI . getOperand ( 2 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> static bool riscv_valid_lo_sum_p ( enum riscv_symbol_type sym_type , enum machine_mode mode ) { if ( riscv_symbol_insns ( sym_type ) == 0 ) return false ; if ( ! riscv_split_symbol_type ( sym_type ) ) return false ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && GET_MODE_BITSIZE ( mode ) > GET_MODE_ALIGNMENT ( mode ) ) return false ; return true ; } </s>

Return true if a LO_SUM can address a value of mode MODE when the LO_SUM symbol has type SYM_TYPE .


<s> MachineBasicBlock :: iterator RISCVFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { unsigned SPReg = RISCV :: X2 ; DebugLoc DL = MI -> getDebugLoc ( ) ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = MI -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { Amount = alignSPAdjust ( Amount ) ; if ( MI -> getOpcode ( ) == RISCV :: ADJCALLSTACKDOWN ) Amount = - Amount ; adjustReg ( MBB , MI , DL , SPReg , SPReg , Amount , MachineInstr :: NoFlags ) ; } } return MBB . erase ( MI ) ; } </s>


<s> rtx riscv_return_addr ( int count , rtx frame ATTRIBUTE_UNUSED ) { if ( count != 0 ) return const0_rtx ; return get_hard_reg_initial_val ( Pmode , RETURN_ADDR_REGNUM ) ; } </s>

Implement RETURN_ADDR_RTX . We do not support moving back to a previous frame .


<s> static int stackSlotSize ( ) { return 2 ; } </s>


<s>
bool
ARCFrameLowering
::
restoreCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
DEBUG
(
dbgs
(
)
<<
"Restore callee saved registers: "
<<
MBB
.
getParent
(
)
->
getFunction
(
)
->
getName
(
)
<<
"\n"
)
;
unsigned
Last
=
determineLastCalleeSave
(
CSI
)
;
if
(
UseSaveRestoreFunclet
&&
Last
>
ARC
::
R14
)
{
return
true
;
}
return
false
;
}
</s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .

ARC
ARC
"Restore callee saved registers: "
"\n"
ARC::R14


<s> void SystemZFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; bool HasFP = hasFP ( MF ) ; SystemZMachineFunctionInfo * MFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; bool IsVarArg = MF . getFunction ( ) -> isVarArg ( ) ; if ( IsVarArg ) for ( unsigned I = MFI -> getVarArgsFirstGPR ( ) ; I < SystemZ :: NumArgGPRs ; ++ I ) SavedRegs . set ( SystemZ :: ArgGPRs [ I ] ) ; if ( ! MF . getLandingPads ( ) . empty ( ) ) { SavedRegs . set ( SystemZ :: R6D ) ; SavedRegs . set ( SystemZ :: R7D ) ; } if ( HasFP ) SavedRegs . set ( SystemZ :: R11D ) ; if ( MFFrame . hasCalls ( ) ) SavedRegs . set ( SystemZ :: R14D ) ; const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ; for ( unsigned I = 0 ; CSRegs [ I ] ; ++ I ) { unsigned Reg = CSRegs [ I ] ; if ( SystemZ :: GR64BitRegClass . contains ( Reg ) && SavedRegs . test ( Reg ) ) { SavedRegs . set ( SystemZ :: R15D ) ; break ; } } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s>
SDValue
VETargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
lowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
VAARG
:
return
LowerVAARG
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

VE
VE
"Should not custom lower this!"
ISD::BlockAddress
ISD::DYNAMIC_STACKALLOC
ISD::GlobalAddress
ISD::GlobalTLSAddress
ISD::VASTART
ISD::VAARG


<s> void AArch64PassConfig :: addPreRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && TM -> isPagerando ( ) ) { addPass ( createAArch64PagerandoOptimizerPass ( ) ) ; addPass ( & DeadMachineInstructionElimID ) ; } if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableDeadRegisterElimination ) addPass ( createAArch64DeadRegisterDefinitions ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAdvSIMDScalar ) { addPass ( createAArch64AdvSIMDScalar ( ) ) ; addPass ( & PeepholeOptimizerID ) ; } } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> bool MSP430FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; MSP430MachineFunctionInfo * MFI = MF . getInfo < MSP430MachineFunctionInfo > ( ) ; MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( MSP430 :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ; } return true ; } </s>


<s> Align PPCTargetLowering :: getPrefLoopAlignment ( MachineLoop * ML ) const { switch ( Subtarget . getCPUDirective ( ) ) { default : break ; case PPC :: DIR_970 : case PPC :: DIR_PWR4 : case PPC :: DIR_PWR5 : case PPC :: DIR_PWR5X : case PPC :: DIR_PWR6 : case PPC :: DIR_PWR6X : case PPC :: DIR_PWR7 : case PPC :: DIR_PWR8 : case PPC :: DIR_PWR9 : case PPC :: DIR_PWR10 : case PPC :: DIR_PWR_FUTURE : { if ( ! ML ) break ; if ( ! DisableInnermostLoopAlign32 ) { if ( ML -> getLoopDepth ( ) > 1 && ML -> getSubLoops ( ) . empty ( ) ) return Align ( 32 ) ; } const PPCInstrInfo * TII = Subtarget . getInstrInfo ( ) ; uint64_t LoopSize = 0 ; for ( auto I = ML -> block_begin ( ) , IE = ML -> block_end ( ) ; I != IE ; ++ I ) for ( auto J = ( * I ) -> begin ( ) , JE = ( * I ) -> end ( ) ; J != JE ; ++ J ) { LoopSize += TII -> getInstSizeInBytes ( * J ) ; if ( LoopSize > 32 ) break ; } if ( LoopSize > 16 && LoopSize <= 32 ) return Align ( 32 ) ; break ; } } return TargetLowering :: getPrefLoopAlignment ( ML ) ; } </s>


<s> static inline bool offset_9bit_signed_scaled_p ( machine_mode mode , poly_int64 offset ) { HOST_WIDE_INT multiple ; return ( constant_multiple_p ( offset , GET_MODE_SIZE ( mode ) , & multiple ) && IN_RANGE ( multiple , - 256 , 255 ) ) ; } </s>

Return true if OFFSET is a signed 9-bit value multiplied by the size of MODE .


"variable %q+D located in address space %qs beyond flash "

"variable %q+D located in address space %qs"

" which is not supported for architecture %qs"

"variable %q+D must be const in order to be put into"

Add the section attribute if the variable is in progmem .


<s> void MipsSERegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( ! TFI -> hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( 0 ) . getImm ( ) ; if ( I -> getOpcode ( ) == Mips :: ADJCALLSTACKDOWN ) Amount = - Amount ; const MipsSEInstrInfo * II = static_cast < const MipsSEInstrInfo * > ( & TII ) ; unsigned SP = Subtarget . isABI_N64 ( ) ? Mips :: SP_64 : Mips :: SP ; II -> adjustStackPtr ( SP , Amount , MBB , I ) ; } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

Mips Mips 0 Mips::ADJCALLSTACKDOWN Mips Mips Mips::SP_64 Mips::SP


Returns the calling convention specific va_list date type . The argument ABI can be DEFAULT_ABI , MS_ABI , or SYSV_ABI .


<s> TargetPassConfig * GCNTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new GCNPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> TargetIRAnalysis HexagonTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( const Function & F ) { return TargetTransformInfo ( HexagonTTIImpl ( this , F ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


<s> virtual const NVPTXInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> SDValue PPCTargetLowering :: LowerCall ( TargetLowering :: CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const { SelectionDAG & DAG = CLI . DAG ; DebugLoc & dl = CLI . DL ; SmallVector < ISD :: OutputArg , 32 > & Outs = CLI . Outs ; SmallVector < SDValue , 32 > & OutVals = CLI . OutVals ; SmallVector < ISD :: InputArg , 32 > & Ins = CLI . Ins ; SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; bool & isTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool isVarArg = CLI . IsVarArg ; if ( isTailCall ) isTailCall = IsEligibleForTailCallOptimization ( Callee , CallConv , isVarArg , Ins , DAG ) ; if ( PPCSubTarget . isSVR4ABI ( ) && ! PPCSubTarget . isPPC64 ( ) ) return LowerCall_32SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; return LowerCall_Darwin_Or_64SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; } </s>

This hook must be implemented to lower calls into the specified DAG .

PowerPC PPC ISD::OutputArg 32 32 ISD::InputArg 32 PPC PPC PPC


<s> unsigned XCoreRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? XCore :: R10 : XCore :: SP ; } </s>


<s> bool ARMBaseTargetMachine :: addPreRegAlloc ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( Subtarget . hasNEON ( ) ) PM . add ( createNEONPreAllocPass ( ) ) ; if ( OptLevel != CodeGenOpt :: None && ! Subtarget . isThumb1Only ( ) ) PM . add ( createARMLoadStoreOptimizationPass ( true ) ) ; return true ; } </s>


<s> int romp_makes_calls ( ) { rtx insn ; for ( insn = get_insns ( ) ; insn ; insn = next_insn ( insn ) ) { if ( GET_CODE ( insn ) == CALL_INSN ) return 1 ; else if ( GET_CODE ( insn ) == INSN ) { rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) != USE && GET_CODE ( body ) != CLOBBER && GET_CODE ( body ) != ADDR_VEC && GET_CODE ( body ) != ADDR_DIFF_VEC && get_attr_type ( insn ) == TYPE_FP ) return 1 ; } } return 0 ; } </s>

Return non-zero if this function makes calls or has fp operations ( which are really calls ) .


<s>
void
RISCVInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MBBI
,
const
DebugLoc
&
DL
,
unsigned
DstReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
RISCV
::
GPRRegClass
.
contains
(
DstReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
RISCV
::
ADDI
)
,
DstReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
0
)
;
return
;
}
unsigned
Opc
;
if
(
RISCV
::
FPR32RegClass
.
contains
(
DstReg
,
SrcReg
)
)
Opc
=
RISCV
::
FSGNJ_S
;
else
if
(
RISCV
::
FPR64RegClass
.
contains
(
DstReg
,
SrcReg
)
)
Opc
=
RISCV
::
FSGNJ_D
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
Opc
)
,
DstReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LiveIntervals > ( ) ; AU . addPreserved < LiveIntervals > ( ) ; AU . addRequired < VirtRegMap > ( ) ; AU . addRequired < LiveRegMatrix > ( ) ; AU . addPreserved < SlotIndexes > ( ) ; AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool M68kOperand :: isImm ( ) const { return Kind == KindTy :: Imm ; } </s>


<s> bool MSP430FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) BuildMI ( MBB , MI , DL , TII . get ( MSP430 :: POP16r ) , CSI [ i ] . getReg ( ) ) ; return true ; } </s>


<s> static void riscv_expand_conditional_move_onesided ( rtx dest , rtx cons , rtx alt , rtx_code code , rtx op0 , rtx op1 ) { machine_mode mode = GET_MODE ( dest ) ; gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_INT ) ; gcc_assert ( reg_or_0_operand ( cons , mode ) ) ; gcc_assert ( reg_or_0_operand ( alt , mode ) ) ; riscv_emit_int_compare ( & code , & op0 , & op1 , true ) ; rtx cond = gen_rtx_fmt_ee ( code , mode , op0 , op1 ) ; rtx tmp1 = gen_reg_rtx ( mode ) ; rtx tmp2 = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( tmp1 , gen_rtx_IF_THEN_ELSE ( mode , cond , cons , const0_rtx ) ) ) ; cond = gen_rtx_fmt_ee ( ( code == EQ ) ? NE : EQ , mode , op0 , op1 ) ; emit_insn ( gen_rtx_SET ( tmp2 , gen_rtx_IF_THEN_ELSE ( mode , cond , alt , const0_rtx ) ) ) ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_IOR ( mode , tmp1 , tmp2 ) ) ) ; } </s>

Helper to emit two one-sided conditional moves for the movecc .


<s> static rtx altivec_expand_vec_ext_builtin ( tree exp , rtx target ) { machine_mode tmode , mode0 ; tree arg0 , arg1 ; int elt ; rtx op0 ; arg0 = CALL_EXPR_ARG ( exp , 0 ) ; arg1 = CALL_EXPR_ARG ( exp , 1 ) ; op0 = expand_normal ( arg0 ) ; elt = get_element_number ( TREE_TYPE ( arg0 ) , arg1 ) ; tmode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( arg0 ) ) ) ; mode0 = TYPE_MODE ( TREE_TYPE ( arg0 ) ) ; gcc_assert ( VECTOR_MODE_P ( mode0 ) ) ; op0 = force_reg ( mode0 , op0 ) ; if ( optimize || ! target || ! register_operand ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; rs6000_expand_vector_extract ( target , op0 , elt ) ; return target ; } </s>


<s> int HexagonMCInstrInfo :: getMaxValue ( MCInstrInfo const & MCII , MCInst const & MCI ) { assert ( HexagonMCInstrInfo :: isExtendable ( MCII , MCI ) || HexagonMCInstrInfo :: isExtended ( MCII , MCI ) ) ; if ( HexagonMCInstrInfo :: isExtentSigned ( MCII , MCI ) ) return ( 1 << ( HexagonMCInstrInfo :: getExtentBits ( MCII , MCI ) - 1 ) ) - 1 ; return ( 1 << HexagonMCInstrInfo :: getExtentBits ( MCII , MCI ) ) - 1 ; } </s>

Return the maximal unsigned value possible given these KnownBits .


<s> static bool const_load_sequence_p ( swap_web_entry * insn_entry , rtx insn ) { unsigned uid = INSN_UID ( insn ) ; if ( ! insn_entry [ uid ] . is_swap || insn_entry [ uid ] . is_load ) return false ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref use ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( ! def_link || def_link -> next ) return false ; rtx def_insn = DF_REF_INSN ( def_link -> ref ) ; unsigned uid2 = INSN_UID ( def_insn ) ; if ( ! insn_entry [ uid2 ] . is_load || ! insn_entry [ uid2 ] . is_swap ) return false ; rtx body = PATTERN ( def_insn ) ; if ( GET_CODE ( body ) != SET || GET_CODE ( SET_SRC ( body ) ) != VEC_SELECT || GET_CODE ( XEXP ( SET_SRC ( body ) , 0 ) ) != MEM ) return false ; rtx mem = XEXP ( SET_SRC ( body ) , 0 ) ; rtx base_reg = XEXP ( mem , 0 ) ; df_ref base_use ; insn_info = DF_INSN_INFO_GET ( def_insn ) ; FOR_EACH_INSN_INFO_USE ( base_use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( base_use ) , base_reg ) ) continue ; struct df_link * base_def_link = DF_REF_CHAIN ( base_use ) ; if ( ! base_def_link || base_def_link -> next ) return false ; rtx tocrel_insn = DF_REF_INSN ( base_def_link -> ref ) ; rtx tocrel_body = PATTERN ( tocrel_insn ) ; rtx base , offset ; if ( GET_CODE ( tocrel_body ) != SET ) return false ; rtx tocrel_expr = SET_SRC ( tocrel_body ) ; if ( GET_CODE ( tocrel_expr ) == MEM ) tocrel_expr = XEXP ( tocrel_expr , 0 ) ; if ( ! toc_relative_expr_p ( tocrel_expr , false ) ) return false ; split_const ( XVECEXP ( tocrel_base , 0 , 0 ) , & base , & offset ) ; if ( GET_CODE ( base ) != SYMBOL_REF || ! CONSTANT_POOL_ADDRESS_P ( base ) ) return false ; } } return true ; } </s>

Return TRUE if insn is a swap fed by a load from the constant pool .


<s> EVT WebAssemblyTargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & C , EVT VT ) const { if ( VT . isVector ( ) ) return VT . changeVectorElementTypeToInteger ( ) ; return TargetLowering :: getSetCCResultType ( DL , C , VT ) ; } </s>

Return the value type to use for ISD : :SETCC .


Define the offset between two registers , one to be eliminated , and the other its replacement , at the start of a routine .


<s> void RISCVTargetStreamer :: reset ( ) { } </s>

Reset an existing scalar value for Def and a given Instance .


<s> MCObjectStreamer & getStreamer ( ) { return static_cast < MCObjectStreamer & > ( Streamer ) ; } </s>

Return the output streamer for the assembler .


<s> void Mips16FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: Move32R16 ) , Mips :: SP ) . addReg ( Mips :: S0 ) ; TII . restoreFrame ( Mips :: SP , StackSize , MBB , MBBI ) ; } </s>

Mips Mips Mips Mips Mips::Move32R16 Mips::SP Mips::S0 Mips::SP


<s> static rtx set_frame_related_p ( void ) { rtx_insn * seq = get_insns ( ) ; rtx_insn * insn ; end_sequence ( ) ; if ( ! seq ) return NULL_RTX ; if ( INSN_P ( seq ) ) { insn = seq ; while ( insn != NULL_RTX ) { RTX_FRAME_RELATED_P ( insn ) = 1 ; insn = NEXT_INSN ( insn ) ; } seq = emit_insn ( seq ) ; } else { seq = emit_insn ( seq ) ; RTX_FRAME_RELATED_P ( seq ) = 1 ; } return seq ; } </s>

Helper function to set RTX_FRAME_RELATED_P on instructions , including sequences .


<s> static inline void xtensa_reorg_loops ( void ) { } </s>

Run from machine_dependent_reorg , this pass looks for doloop_end insns and tries to rewrite the RTL of these loops so that proper Xtensa hardware loops are generated .


<s> opt_machine_mode aarch64_sve_data_mode ( scalar_mode inner_mode , poly_uint64 nunits ) { enum mode_class mclass = ( is_a < scalar_float_mode > ( inner_mode ) ? MODE_VECTOR_FLOAT : MODE_VECTOR_INT ) ; machine_mode mode ; FOR_EACH_MODE_IN_CLASS ( mode , mclass ) if ( inner_mode == GET_MODE_INNER ( mode ) && known_eq ( nunits , GET_MODE_NUNITS ( mode ) ) && aarch64_sve_data_mode_p ( mode ) ) return mode ; return opt_machine_mode ( ) ; } </s>

Return the SVE vector mode that has NUNITS elements of mode INNER_MODE .


<s>
static
void
mmix_asm_output_mi_thunk
(
FILE
*
stream
,
tree
thunk_fndecl
ATTRIBUTE_UNUSED
,
HOST_WIDE_INT
delta
,
HOST_WIDE_INT
vcall_offset
ATTRIBUTE_UNUSED
,
tree
func
)
{
const
char
*
regname
=
reg_names
[
MMIX_FIRST_INCOMING_ARG_REGNUM
]
;
const
char
*
fnname
=
IDENTIFIER_POINTER
(
DECL_ASSEMBLER_NAME
(
thunk_fndecl
)
)
;
assemble_start_function
(
thunk_fndecl
,
fnname
)
;
if
(
delta
>=
0
&&
delta
<
65536
)
fprintf
(
stream
,
"\tINCL %s,%d\n"
,
regname
,
(
int
)
delta
)
;
else
if
(
delta
<
0
&&
delta
>=
255
)
fprintf
(
stream
,
"\tSUBU %s,%s,%d\n"
,
regname
,
regname
,
(
int
)
delta
)
;
else
{
mmix_output_register_setting
(
stream
,
255
,
delta
,
1
)
;
fprintf
(
stream
,
"\tADDU %s,%s,$255\n"
,
regname
,
regname
)
;
}
fprintf
(
stream
,
"\tJMP "
)
;
assemble_name
(
stream
,
XSTR
(
XEXP
(
DECL_RTL
(
func
)
,
0
)
,
0
)
)
;
fprintf
(
stream
,
"\n"
)
;
assemble_end_function
(
thunk_fndecl
,
fnname
)
;
}
</s>


<s> void MOSNoRecurse :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < CallGraphWrapperPass > ( ) ; AU . addPreserved < CallGraphWrapperPass > ( ) ; } </s>


<s>
void
XCoreRegisterInfo
::
emitEpilogue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
prior
(
MBB
.
end
(
)
)
;
DebugLoc
dl
=
MBBI
->
getDebugLoc
(
)
;
bool
FP
=
hasFP
(
MF
)
;
if
(
FP
)
{
unsigned
FramePtr
=
XCore
::
R10
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
XCore
::
SETSP_1r
)
)
.
addReg
(
FramePtr
)
;
}
int
FrameSize
=
MFI
->
getStackSize
(
)
;
assert
(
FrameSize
%
4
==
0
&&
"Misaligned frame size"
)
;
FrameSize
/=
4
;
bool
isU6
=
isImmU6
(
FrameSize
)
;
if
(
!
isU6
&&
!
isImmU16
(
FrameSize
)
)
{
cerr
<<
"emitEpilogue Frame size too big: "
<<
FrameSize
<<
"\n"
;
abort
(
)
;
}
if
(
FrameSize
)
{
XCoreFunctionInfo
*
XFI
=
MF
.
getInfo
<
XCoreFunctionInfo
>
(
)
;
if
(
FP
)
{
int
FPSpillOffset
=
MFI
->
getObjectOffset
(
XFI
->
getFPSpillSlot
(
)
)
;
FPSpillOffset
+=
FrameSize
*
4
;
loadFromStack
(
MBB
,
MBBI
,
XCore
::
R10
,
FPSpillOffset
,
dl
)
;
}
bool
restoreLR
=
XFI
->
getUsesLR
(
)
;
if
(
restoreLR
&&
MFI
->
getObjectOffset
(
XFI
->
getLRSpillSlot
(
)
)
!=
0
)
{
int
LRSpillOffset
=
MFI
->
getObjectOffset
(
XFI
->
getLRSpillSlot
(
)
)
;
LRSpillOffset
+=
FrameSize
*
4
;
loadFromStack
(
MBB
,
MBBI
,
XCore
::
LR
,
LRSpillOffset
,
dl
)
;
restoreLR
=
false
;
}
if
(
restoreLR
)
{
assert
(
MBBI
->
getOpcode
(
)
==
XCore
::
RETSP_u6
||
MBBI
->
getOpcode
(
)
==
XCore
::
RETSP_lu6
)
;
int
Opcode
=
(
isU6
)
XCore
::
RETSP_u6
:
XCore
::
RETSP_lu6
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Opcode
)
)
.
addImm
(
FrameSize
)
;
MBB
.
erase
(
MBBI
)
;
}
else
{
int
Opcode
=
(
isU6
)
XCore
::
LDAWSP_ru6_RRegs
:
XCore
::
LDAWSP_lru6_RRegs
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Opcode
)
,
XCore
::
SP
)
.
addImm
(
FrameSize
)
;
}
}
}
</s>


<s> unsigned AMDGPUAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & Op , unsigned Kind ) { AMDGPUOperand & Operand = ( AMDGPUOperand & ) Op ; switch ( Kind ) { case MCK_addr64 : return Operand . isAddr64 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_gds : return Operand . isGDS ( ) ? Match_Success : Match_InvalidOperand ; case MCK_lds : return Operand . isLDS ( ) ? Match_Success : Match_InvalidOperand ; case MCK_glc : return Operand . isGLC ( ) ? Match_Success : Match_InvalidOperand ; case MCK_idxen : return Operand . isIdxen ( ) ? Match_Success : Match_InvalidOperand ; case MCK_offen : return Operand . isOffen ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SSrcB32 : return Operand . isSSrcB32 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SSrcF32 : return Operand . isSSrcF32 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SoppBrTarget : return Operand . isSoppBrTarget ( ) ? Match_Success : Match_InvalidOperand ; case MCK_VReg32OrOff : return Operand . isVReg32OrOff ( ) ? Match_Success : Match_InvalidOperand ; case MCK_InterpSlot : return Operand . isInterpSlot ( ) ? Match_Success : Match_InvalidOperand ; case MCK_Attr : return Operand . isInterpAttr ( ) ? Match_Success : Match_InvalidOperand ; case MCK_AttrChan : return Operand . isAttrChan ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SReg_64 : case MCK_SReg_64_XEXEC : return Operand . isNull ( ) ? Match_Success : Match_InvalidOperand ; default : return Match_InvalidOperand ; } } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


"Unexpected number of bits in the mask!"

Returns true if at least one of the register writes performed by .


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s>
static
void
aarch64_print_hint_for_core_or_arch
(
const
char
*
str
,
bool
arch
)
{
auto_vec
<
const
char
*
>
candidates
;
const
struct
processor
*
entry
=
arch
all_architectures
:
all_cores
;
for
(
;
entry
->
name
!=
;
entry
++
)
candidates
.
safe_push
(
entry
->
name
)
;
char
*
s
;
const
char
*
hint
=
candidates_list_and_hint
(
str
,
s
,
candidates
)
;
if
(
hint
)
inform
(
input_location
,
"valid arguments are: %s;"
" did you mean %qs?"
,
s
,
hint
)
;
XDELETEVEC
(
s
)
;
}
</s>

Print a hint with a suggestion for a core or architecture name that most closely resembles what the user passed in STR . ARCH is true if the user is asking for an architecture name . ARCH is false if the user is asking for a core name .

aarch64
"valid arguments are: %s;"
" did you mean %qs?"


initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool ARMBaseInstrInfo :: areLoadsFromSameBasePtr ( SDNode * Load1 , SDNode * Load2 , int64_t & Offset1 , int64_t & Offset2 ) const { if ( Subtarget . isThumb1Only ( ) ) return false ; if ( ! Load1 -> isMachineOpcode ( ) || ! Load2 -> isMachineOpcode ( ) ) return false ; switch ( Load1 -> getMachineOpcode ( ) ) { default : return false ; case ARM :: LDR : case ARM :: LDRB : case ARM :: LDRD : case ARM :: LDRH : case ARM :: LDRSB : case ARM :: LDRSH : case ARM :: VLDRD : case ARM :: VLDRS : case ARM :: t2LDRi8 : case ARM :: t2LDRDi8 : case ARM :: t2LDRSHi8 : case ARM :: t2LDRi12 : case ARM :: t2LDRSHi12 : break ; } switch ( Load2 -> getMachineOpcode ( ) ) { default : return false ; case ARM :: LDR : case ARM :: LDRB : case ARM :: LDRD : case ARM :: LDRH : case ARM :: LDRSB : case ARM :: LDRSH : case ARM :: VLDRD : case ARM :: VLDRS : case ARM :: t2LDRi8 : case ARM :: t2LDRDi8 : case ARM :: t2LDRSHi8 : case ARM :: t2LDRi12 : case ARM :: t2LDRSHi12 : break ; } if ( Load1 -> getOperand ( 0 ) != Load2 -> getOperand ( 0 ) || Load1 -> getOperand ( 4 ) != Load2 -> getOperand ( 4 ) ) return false ; if ( Load1 -> getOperand ( 3 ) != Load2 -> getOperand ( 3 ) ) return false ; if ( isa < ConstantSDNode > ( Load1 -> getOperand ( 1 ) ) && isa < ConstantSDNode > ( Load2 -> getOperand ( 1 ) ) ) { Offset1 = cast < ConstantSDNode > ( Load1 -> getOperand ( 1 ) ) -> getSExtValue ( ) ; Offset2 = cast < ConstantSDNode > ( Load2 -> getOperand ( 1 ) ) -> getSExtValue ( ) ; return true ; } return false ; } </s>

areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address .


<s> inline hashval_t mips_lo_sum_offset_hasher :: hash ( const mips_lo_sum_offset * entry ) { return mips_hash_base ( entry -> base ) ; } </s>

Hash function for builtin functions with up to 3 arguments and a return type .


<s> bool WebAssemblyTargetLowering :: CanLowerReturn ( CallingConv :: ID , MachineFunction & , bool , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & ) const { return Outs . size ( ) <= 1 ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .

WebAssembly WebAssembly ISD::OutputArg 1


<s> SDValue ARMTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : return PerformADDCombine ( N , DCI ) ; case ISD :: SUB : return PerformSUBCombine ( N , DCI ) ; case ISD :: MUL : return PerformMULCombine ( N , DCI , Subtarget ) ; case ISD :: OR : return PerformORCombine ( N , DCI , Subtarget ) ; case ISD :: AND : return PerformANDCombine ( N , DCI ) ; case ARMISD :: VMOVRRD : return PerformVMOVRRDCombine ( N , DCI ) ; case ARMISD :: VMOVDRR : return PerformVMOVDRRCombine ( N , DCI . DAG ) ; case ISD :: BUILD_VECTOR : return PerformBUILD_VECTORCombine ( N , DCI . DAG ) ; case ISD :: VECTOR_SHUFFLE : return PerformVECTOR_SHUFFLECombine ( N , DCI . DAG ) ; case ARMISD :: VDUPLANE : return PerformVDUPLANECombine ( N , DCI ) ; case ISD :: INTRINSIC_WO_CHAIN : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DCI . DAG , Subtarget ) ; case ISD :: SIGN_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: ANY_EXTEND : return PerformExtendCombine ( N , DCI . DAG , Subtarget ) ; case ISD :: SELECT_CC : return PerformSELECT_CCCombine ( N , DCI . DAG , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> static bool mips_handle_option ( size_t code , const char * arg , int value ATTRIBUTE_UNUSED ) { switch ( code ) { case OPT_mabi_ : if ( strcmp ( arg , "32" ) == 0 ) mips_abi = ABI_32 ; else if ( strcmp ( arg , "o64" ) == 0 ) mips_abi = ABI_O64 ; else if ( strcmp ( arg , "n32" ) == 0 ) mips_abi = ABI_N32 ; else if ( strcmp ( arg , "64" ) == 0 ) mips_abi = ABI_64 ; else if ( strcmp ( arg , "eabi" ) == 0 ) mips_abi = ABI_EABI ; else return false ; return true ; case OPT_march_ : case OPT_mtune_ : return mips_parse_cpu ( arg ) != 0 ; case OPT_mips : mips_isa_info = mips_parse_cpu ( ACONCAT ( ( "mips" , arg , NULL ) ) ) ; return mips_isa_info != 0 ; case OPT_mno_flush_func : mips_cache_flush_func = NULL ; return true ; default : return true ; } } </s>


<s>
void
HexagonHazardRecognizer
::
EmitInstruction
(
SUnit
*
SU
)
{
MachineInstr
*
MI
=
SU
->
getInstr
(
)
;
if
(
!
MI
)
return
;
for
(
const
MachineOperand
&
MO
:
MI
->
operands
(
)
)
if
(
MO
.
isReg
(
)
&&
MO
.
isDef
(
)
&&
!
MO
.
isImplicit
(
)
)
RegDefs
.
insert
(
MO
.
getReg
(
)
)
;
if
(
TII
->
isZeroCost
(
MI
->
getOpcode
(
)
)
)
return
;
if
(
!
Resources
->
canReserveResources
(
*
MI
)
||
isNewStore
(
*
MI
)
)
{
assert
(
TII
->
mayBeNewStore
(
*
MI
)
&&
"Expecting .new store"
)
;
MachineFunction
*
MF
=
MI
->
getParent
(
)
->
getParent
(
)
;
MachineInstr
*
NewMI
=
MF
->
CreateMachineInstr
(
TII
->
get
(
TII
->
getDotNewOp
(
*
MI
)
)
,
MI
->
getDebugLoc
(
)
)
;
if
(
Resources
->
canReserveResources
(
*
NewMI
)
)
Resources
->
reserveResources
(
*
NewMI
)
;
else
Resources
->
reserveResources
(
*
MI
)
;
MF
->
deleteMachineInstr
(
NewMI
)
;
}
else
Resources
->
reserveResources
(
*
MI
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
" Add instruction "
<<
*
MI
)
;
if
(
TII
->
mayBeCurLoad
(
*
MI
)
)
for
(
auto
&
S
:
SU
->
Succs
)
if
(
S
.
isAssignedRegDep
(
)
&&
S
.
getLatency
(
)
==
0
&&
S
.
getSUnit
(
)
->
NumPredsLeft
==
1
)
{
UsesDotCur
=
S
.
getSUnit
(
)
;
DotCurPNum
=
PacketNum
;
break
;
}
if
(
SU
==
UsesDotCur
)
{
UsesDotCur
=
nullptr
;
DotCurPNum
=
1
;
}
UsesLoad
=
MI
->
mayLoad
(
)
;
if
(
TII
->
isHVXVec
(
*
MI
)
&&
!
MI
->
mayLoad
(
)
&&
!
MI
->
mayStore
(
)
)
for
(
auto
&
S
:
SU
->
Succs
)
if
(
S
.
isAssignedRegDep
(
)
&&
S
.
getLatency
(
)
==
0
&&
TII
->
mayBeNewStore
(
*
S
.
getSUnit
(
)
->
getInstr
(
)
)
&&
Resources
->
canReserveResources
(
*
S
.
getSUnit
(
)
->
getInstr
(
)
)
)
{
PrefVectorStoreNew
=
S
.
getSUnit
(
)
;
break
;
}
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


"SIInstrInfo::storeRegToStackSlot - Do not know how to"

Store the specified register of the given register class to the specified stack frame index .


<s> bool ShouldShrinkFPConstant ( EVT VT ) const override { return VT != MVT :: f64 ; } </s>

If true , then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime .


<s> const SPIRVRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool RISCVAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { if ( ! ExtraCode ) { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; if ( ! MO . isReg ( ) ) return true ; OS << "0(" << RISCVInstPrinter :: getRegisterName ( MO . getReg ( ) ) << ")" ; return false ; } return AsmPrinter :: PrintAsmMemoryOperand ( MI , OpNo , ExtraCode , OS ) ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


"Byval argument's alignment should be a multiple of"

Target-specific cleanup for formal ByVal parameters .


<s> void M88kPassConfig :: addPreEmitPass ( ) { if ( BranchRelaxation ) addPass ( & BranchRelaxationPassID ) ; if ( ! DisableDelaySlotFiller ) addPass ( createM88kDelaySlotFiller ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> unsigned getStackAlignment ( ) const { return StackAlignment ; } </s>

Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget .


<s> static M68kRelType getType ( unsigned Kind , MCSymbolRefExpr :: VariantKind & Modifier , bool & IsPCRel ) { switch ( Kind ) { case FK_Data_4 : case FK_PCRel_4 : return RT_32 ; case FK_PCRel_2 : case FK_Data_2 : return RT_16 ; case FK_PCRel_1 : case FK_Data_1 : return RT_8 ; } llvm_unreachable ( "Unimplemented" ) ; } </s>

Overload to return most specific vector type .


<s> static bool mep_expand_setcc_1 ( enum rtx_code code , rtx dest , rtx op1 , rtx op2 ) { rtx tmp ; switch ( code ) { case GT : case GTU : tmp = op1 , op1 = op2 , op2 = tmp ; code = swap_condition ( code ) ; case LT : case LTU : op1 = force_reg ( SImode , op1 ) ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_fmt_ee ( code , SImode , op1 , op2 ) ) ) ; return true ; case EQ : if ( op2 != const0_rtx ) op1 = expand_binop ( SImode , sub_optab , op1 , op2 , NULL , 1 , OPTAB_WIDEN ) ; mep_expand_setcc_1 ( LTU , dest , op1 , const1_rtx ) ; return true ; case NE : if ( optimize_size && op2 != const0_rtx ) return false ; if ( op2 != const0_rtx ) op1 = expand_binop ( SImode , sub_optab , op1 , op2 , NULL , 1 , OPTAB_WIDEN ) ; op2 = gen_reg_rtx ( SImode ) ; mep_expand_setcc_1 ( LTU , op2 , op1 , const1_rtx ) ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_XOR ( SImode , op2 , const1_rtx ) ) ) ; return true ; case LE : if ( GET_CODE ( op2 ) != CONST_INT || INTVAL ( op2 ) == 0x7ffffff ) return false ; op2 = GEN_INT ( INTVAL ( op2 ) + 1 ) ; return mep_expand_setcc_1 ( LT , dest , op1 , op2 ) ; case LEU : if ( GET_CODE ( op2 ) != CONST_INT || INTVAL ( op2 ) == - 1 ) return false ; op2 = GEN_INT ( trunc_int_for_mode ( INTVAL ( op2 ) + 1 , SImode ) ) ; return mep_expand_setcc_1 ( LTU , dest , op1 , op2 ) ; case GE : if ( GET_CODE ( op2 ) != CONST_INT || INTVAL ( op2 ) == trunc_int_for_mode ( 0x80000000 , SImode ) ) return false ; op2 = GEN_INT ( INTVAL ( op2 ) - 1 ) ; return mep_expand_setcc_1 ( GT , dest , op1 , op2 ) ; case GEU : if ( GET_CODE ( op2 ) != CONST_INT || op2 == const0_rtx ) return false ; op2 = GEN_INT ( trunc_int_for_mode ( INTVAL ( op2 ) - 1 , SImode ) ) ; return mep_expand_setcc_1 ( GTU , dest , op1 , op2 ) ; default : gcc_unreachable ( ) ; } } </s>

Emit a setcc instruction in its entirity .


<s> static rtx frv_alloc_temp_reg ( frv_tmp_reg_t * info , enum reg_class rclass , machine_mode mode , int mark_as_used , int no_abort ) { int regno = info -> next_reg [ ( int ) rclass ] ; int orig_regno = regno ; HARD_REG_SET * reg_in_class = & reg_class_contents [ ( int ) rclass ] ; int i , nr ; for ( ; ; ) { if ( TEST_HARD_REG_BIT ( * reg_in_class , regno ) && TEST_HARD_REG_BIT ( info -> regs , regno ) ) break ; if ( ++ regno >= FIRST_PSEUDO_REGISTER ) regno = 0 ; if ( regno == orig_regno ) { gcc_assert ( no_abort ) ; return NULL_RTX ; } } nr = HARD_REGNO_NREGS ( regno , mode ) ; info -> next_reg [ ( int ) rclass ] = regno + nr ; if ( mark_as_used ) for ( i = 0 ; i < nr ; i ++ ) CLEAR_HARD_REG_BIT ( info -> regs , regno + i ) ; return gen_rtx_REG ( mode , regno ) ; } </s>

Return the next available temporary register in a given class .


<s> unsigned getMaxInlineSizeThreshold ( ) const { return isThumb ( ) ? 0 : 64 ; } </s>

Returns the maximum memset / memcpy size that still makes it profitable to inline the call .


"CPU0 DAG to DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


"Floating-point constant is not a positive zero."

Emit the floating-point constant +0.0 in a register using target- specific logic .


<s> static bool is_branch_slot_insn ( rtx insn ) { if ( ! insn || ! INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; if ( rs6000_sched_groups ) { enum attr_type type = get_attr_type ( insn ) ; if ( type == TYPE_BRANCH || type == TYPE_JMPREG ) return true ; return false ; } return false ; } </s>

The function returns true if INSN can be issued only from the branch slot .


<s> void ix86_expand_round_sse4 ( rtx op0 , rtx op1 ) { machine_mode mode = GET_MODE ( op0 ) ; rtx e1 , e2 , res , half ; const struct real_format * fmt ; REAL_VALUE_TYPE pred_half , half_minus_pred_half ; rtx ( * gen_copysign ) ( rtx , rtx , rtx ) ; rtx ( * gen_round ) ( rtx , rtx , rtx ) ; switch ( mode ) { case SFmode : gen_copysign = gen_copysignsf3 ; gen_round = gen_sse4_1_roundsf2 ; break ; case DFmode : gen_copysign = gen_copysigndf3 ; gen_round = gen_sse4_1_rounddf2 ; break ; default : gcc_unreachable ( ) ; } fmt = REAL_MODE_FORMAT ( mode ) ; real_2expN ( & half_minus_pred_half , - ( fmt -> p ) - 1 , mode ) ; real_arithmetic ( & pred_half , MINUS_EXPR , & dconsthalf , & half_minus_pred_half ) ; half = const_double_from_real_value ( pred_half , mode ) ; e1 = gen_reg_rtx ( mode ) ; emit_insn ( gen_copysign ( e1 , half , op1 ) ) ; e2 = expand_simple_binop ( mode , PLUS , op1 , e1 , NULL_RTX , 0 , OPTAB_DIRECT ) ; res = gen_reg_rtx ( mode ) ; emit_insn ( gen_round ( res , e2 , GEN_INT ( ROUND_TRUNC ) ) ) ; emit_move_insn ( op0 , res ) ; } </s>

Expand SSE sequence for computing round from OP1 storing into OP0 using sse4 round insn .


<s> bool ARMBlockPlacement :: processPostOrderLoops ( MachineLoop * ML ) { bool Changed = false ; for ( auto * InnerML : * ML ) Changed |= processPostOrderLoops ( InnerML ) ; return Changed | fixBackwardsWLS ( ML ) ; } </s>

Updates ordering ( of WLS BB and their loopExits ) in inner loops first Returns true if any change was made in any of the loops .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
const
char
*
avr_out_tsthi
(
rtx_insn
*
insn
,
rtx
*
op
,
int
*
plen
)
{
if
(
compare_sign_p
(
insn
)
)
{
avr_asm_len
(
"tst %B0"
,
op
,
plen
,
1
)
;
}
else
if
(
reg_unused_after
(
insn
,
op
[
0
]
)
&&
compare_eq_p
(
insn
)
)
{
avr_asm_len
(
"or %A0,%B0"
,
op
,
plen
,
1
)
;
}
else
{
avr_out_compare
(
insn
,
op
,
plen
)
;
}
return
""
;
}
</s>


<s> int nds32_can_use_bclr_p ( int ival ) { int one_bit_count ; one_bit_count = popcount_hwi ( ( unsigned HOST_WIDE_INT ) ( ~ ival ) ) ; return ( TARGET_EXT_PERF && ( one_bit_count == 1 ) ) ; } </s>

Function to check if 'bclr ' instruction can be used with IVAL .


<s> static rtx alpha_libcall_value ( machine_mode mode , const_rtx ) { return alpha_function_value_1 ( NULL_TREE , NULL_TREE , mode ) ; } </s>


<s>
bool
FixupLEAPass
::
runOnMachineFunction
(
MachineFunction
&
Func
)
{
MF
=
&
Func
;
const
X86Subtarget
&
ST
=
Func
.
getSubtarget
<
X86Subtarget
>
(
)
;
OptIncDec
=
!
ST
.
slowIncDec
(
)
||
Func
.
getFunction
(
)
->
optForMinSize
(
)
;
OptLEA
=
ST
.
LEAusesAG
(
)
||
ST
.
slowLEA
(
)
;
if
(
!
OptLEA
&&
!
OptIncDec
)
return
false
;
TII
=
ST
.
getInstrInfo
(
)
;
DEBUG
(
dbgs
(
)
<<
"Start X86FixupLEAs\n"
;
)
;
for
(
MachineFunction
::
iterator
I
=
Func
.
begin
(
)
,
E
=
Func
.
end
(
)
;
I
!=
E
;
++
I
)
processBasicBlock
(
Func
,
I
)
;
DEBUG
(
dbgs
(
)
<<
"End X86FixupLEAs\n"
;
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> void aarch64_init_builtin_rsqrt ( void ) { tree fndecl = NULL ; tree ftype = NULL ; tree V2SF_type_node = build_vector_type ( float_type_node , 2 ) ; tree V2DF_type_node = build_vector_type ( double_type_node , 2 ) ; tree V4SF_type_node = build_vector_type ( float_type_node , 4 ) ; struct builtin_decls_data { tree type_node ; const char * builtin_name ; int function_code ; } ; builtin_decls_data bdda [ ] = { { double_type_node , "__builtin_aarch64_rsqrt_df" , AARCH64_BUILTIN_RSQRT_DF } , { float_type_node , "__builtin_aarch64_rsqrt_sf" , AARCH64_BUILTIN_RSQRT_SF } , { V2DF_type_node , "__builtin_aarch64_rsqrt_v2df" , AARCH64_BUILTIN_RSQRT_V2DF } , { V2SF_type_node , "__builtin_aarch64_rsqrt_v2sf" , AARCH64_BUILTIN_RSQRT_V2SF } , { V4SF_type_node , "__builtin_aarch64_rsqrt_v4sf" , AARCH64_BUILTIN_RSQRT_V4SF } } ; builtin_decls_data * bdd = bdda ; builtin_decls_data * bdd_end = bdd + ( ARRAY_SIZE ( bdda ) ) ; for ( ; bdd < bdd_end ; bdd ++ ) { ftype = build_function_type_list ( bdd -> type_node , bdd -> type_node , NULL_TREE ) ; tree attrs = aarch64_get_attributes ( FLAG_FP , TYPE_MODE ( bdd -> type_node ) ) ; fndecl = aarch64_general_add_builtin ( bdd -> builtin_name , ftype , bdd -> function_code , attrs ) ; aarch64_builtin_decls [ bdd -> function_code ] = fndecl ; } } </s>

Add builtins for reciprocal square root .


<s> bool ARM64TargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { EVT VT ; SDValue Ptr ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; } else return false ; bool IsInc ; if ( ! getIndexedAddressParts ( Op , Base , Offset , AM , IsInc , DAG ) ) return false ; if ( Ptr != Base ) return false ; AM = IsInc ? ISD :: POST_INC : ISD :: POST_DEC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .


<s>
StringRef
getPassName
(
)
const
override
{
return
"RISCV Redundant Copy Elimination"
;
}
</s>

RISCV
"RISCV Redundant Copy Elimination"


<s> static void get_pc_thunk_name ( char name [ 32 ] , unsigned int regno ) { if ( USE_HIDDEN_LINKONCE ) sprintf ( name , "__i686.get_pc_thunk.%s" , reg_names [ regno ] ) ; else ASM_GENERATE_INTERNAL_LABEL ( name , "LPR" , regno ) ; } </s>

Fills in the label name that should be used for a pc thunk for the given register .


<s> static tree arm_convert_to_type ( tree type , tree expr ) { tree fromtype = TREE_TYPE ( expr ) ; if ( ! SCALAR_FLOAT_TYPE_P ( fromtype ) || ! SCALAR_FLOAT_TYPE_P ( type ) ) return NULL_TREE ; if ( ( TYPE_PRECISION ( fromtype ) == 16 && TYPE_PRECISION ( type ) > 32 ) || ( TYPE_PRECISION ( type ) == 16 && TYPE_PRECISION ( fromtype ) > 32 ) ) return convert ( type , convert ( float_type_node , expr ) ) ; return NULL_TREE ; } </s>

Implement TARGET_CONVERT_TO_TYPE . Specifically , this hook implements the peculiarity of the ARM half-precision floating-point C semantics that requires conversions between __fp16 to or from double to do an intermediate conversion to float .


"This resolveFrameIndex does not support Thumb1!"

"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> TargetPassConfig * AArch64TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new AArch64PassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> unsigned getCSRFirstUseCost ( ) const { return 5 ; } </s>

Allow the target to override the cost of using a callee-saved register for the first time .


<s>
void
LoongArchDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
MVT
GRLenVT
=
Subtarget
->
getGRLenVT
(
)
;
SDLoc
DL
(
Node
)
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
Constant
:
{
int64_t
Imm
=
cast
<
ConstantSDNode
>
(
Node
)
->
getSExtValue
(
)
;
SDNode
*
Result
=
nullptr
;
SDValue
SrcReg
=
CurDAG
->
getRegister
(
LoongArch
::
R0
,
GRLenVT
)
;
for
(
LoongArchMatInt
::
Inst
&
Inst
:
LoongArchMatInt
::
generateInstSeq
(
Imm
)
)
{
SDValue
SDImm
=
CurDAG
->
getTargetConstant
(
Inst
.
Imm
,
DL
,
GRLenVT
)
;
if
(
Inst
.
Opc
==
LoongArch
::
LU12I_W
)
Result
=
CurDAG
->
getMachineNode
(
LoongArch
::
LU12I_W
,
DL
,
GRLenVT
,
SDImm
)
;
else
Result
=
CurDAG
->
getMachineNode
(
Inst
.
Opc
,
DL
,
GRLenVT
,
SrcReg
,
SDImm
)
;
SrcReg
=
SDValue
(
Result
,
0
)
;
}
ReplaceNode
(
Node
,
Result
)
;
return
;
}
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> const MachineOperand * SIInstrInfo :: getNamedOperand ( const MachineInstr & MI , unsigned OperandName ) const { int Idx = AMDGPU :: getNamedOperandIdx ( MI . getOpcode ( ) , OperandName ) ; if ( Idx == - 1 ) return nullptr ; return & MI . getOperand ( Idx ) ; } </s>


<s> static rtx get_next_active_insn ( rtx insn , rtx tail ) { if ( insn == NULL_RTX || insn == tail ) return NULL_RTX ; while ( 1 ) { insn = NEXT_INSN ( insn ) ; if ( insn == NULL_RTX || insn == tail ) return NULL_RTX ; if ( CALL_P ( insn ) || JUMP_P ( insn ) || ( NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER && INSN_CODE ( insn ) != CODE_FOR_stack_tie ) ) break ; } return insn ; } </s>

Return the next insn after INSN that is found before TAIL is reached , skipping any `` non-active '' insns - insns that will not actually occupy an issue slot . Return NULL_RTX if such an insn is not found .


<s> MachineBasicBlock :: iterator RISCVInstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , outliner :: Candidate & C ) const { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( RISCV :: PseudoCALLReg ) , RISCV :: X5 ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) , 0 , RISCVII :: MO_CALL ) ) ; return It ; } </s>

Insert a call to an outlined function into the program .


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCRelaxableFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
override
{
llvm_unreachable
(
"RelaxInstruction() unimplemented"
)
;
return
false
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> bool isReg ( ) const override { return Kind == Register ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> bool AMDGPUAnnotateKernelFeatures :: runOnModule ( Module & M ) { Triple TT ( M . getTargetTriple ( ) ) ; static const StringRef IntrinsicToAttr [ ] [ 2 ] = { { "llvm.r600.read.tgid.y" , "amdgpu-work-group-id-y" } , { "llvm.r600.read.tgid.z" , "amdgpu-work-group-id-z" } , { "llvm.r600.read.tidig.y" , "amdgpu-work-item-id-y" } , { "llvm.r600.read.tidig.z" , "amdgpu-work-item-id-z" } } ; static const StringRef HSAIntrinsicToAttr [ ] [ 2 ] = { { "llvm.r600.read.local.size.x" , "amdgpu-dispatch-ptr" } , { "llvm.r600.read.local.size.y" , "amdgpu-dispatch-ptr" } , { "llvm.r600.read.local.size.z" , "amdgpu-dispatch-ptr" } , { "llvm.r600.read.global.size.x" , "amdgpu-dispatch-ptr" } , { "llvm.r600.read.global.size.y" , "amdgpu-dispatch-ptr" } , { "llvm.r600.read.global.size.z" , "amdgpu-dispatch-ptr" } } ; bool Changed = addAttrsForIntrinsics ( M , IntrinsicToAttr ) ; if ( TT . getOS ( ) == Triple :: AMDHSA ) Changed |= addAttrsForIntrinsics ( M , HSAIntrinsicToAttr ) ; return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s>
static
void
write_func_decl_from_insn
(
std
::
stringstream
&
s
,
rtx
result
,
rtx
pat
,
rtx
callee
)
{
bool
callprototype
=
register_operand
(
callee
,
Pmode
)
;
const
char
*
name
=
"_"
;
if
(
!
callprototype
)
{
name
=
XSTR
(
callee
,
0
)
;
name
=
nvptx_name_replacement
(
name
)
;
s
<<
"// BEGIN GLOBAL FUNCTION DECL: "
<<
name
<<
"\n"
;
}
s
<<
(
callprototype
"\t.callprototype\t"
:
"\t.extern .func "
)
;
if
(
result
!=
NULL_RTX
)
{
s
<<
"(.param"
;
s
<<
nvptx_ptx_type_from_mode
(
arg_promotion
(
GET_MODE
(
result
)
)
,
false
)
;
s
<<
" "
;
if
(
callprototype
)
s
<<
"_"
;
else
s
<<
"%out_retval"
;
s
<<
")"
;
}
s
<<
name
;
int
nargs
=
XVECLEN
(
pat
,
0
)
1
;
if
(
nargs
>
0
)
{
s
<<
" ("
;
for
(
int
i
=
0
;
i
<
nargs
;
i
++
)
{
rtx
t
=
XEXP
(
XVECEXP
(
pat
,
0
,
i
+
1
)
,
0
)
;
machine_mode
mode
=
GET_MODE
(
t
)
;
int
count
=
maybe_split_mode
(
&
mode
)
;
while
(
count
>
0
)
{
s
<<
".param"
;
s
<<
nvptx_ptx_type_from_mode
(
mode
,
false
)
;
s
<<
" "
;
if
(
callprototype
)
s
<<
"_"
;
else
s
<<
"%arg"
<<
i
;
if
(
mode
==
QImode
||
mode
==
HImode
)
s
<<
"[1]"
;
if
(
i
+
1
<
nargs
||
count
>
0
)
s
<<
", "
;
}
}
s
<<
")"
;
}
s
<<
";\n"
;
}
</s>

Construct a function declaration from a call insn . This can be necessary for two reasons - either we have an indirect call which requires a .callprototype declaration , or we have a libcall generated by emit_library_call for which no decl exists .


<s>
static
void
write_type_node
(
char
*
tok
,
bool
indent
)
{
if
(
indent
)
fprintf
(
init_file
,
"  "
)
;
typemap
*
entry
=
(
typemap
*
)
bsearch
(
tok
,
type_map
,
sizeof
type_map
/
sizeof
type_map
[
0
]
,
sizeof
(
typemap
)
,
typemap_cmp
)
;
if
(
!
entry
)
fatal
(
"Type map is inconsistent."
)
;
fprintf
(
init_file
,
"%s_type_node"
,
entry
->
value
)
;
}
</s>

Write the type node corresponding to TOK .


Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s> static void conditionalize_optimization ( void ) { rtx insn ; for ( insn = get_insns ( ) ; insn ; insn = conditionalize_block ( insn ) ) continue ; } </s>

Apply the conditionalization of blocks optimization . This is the outer loop that traverses through the insns scanning for a branch that signifies an opportunity to apply the optimization . Note that this optimization is applied late . If we could apply it earlier , say before cse 2 , it may expose more optimization opportunities . but , the pay back probably is n't really worth the effort ( we 'd have to update all reg/flow/notes/links/etc to make it work - and stick it in before cse 2 ) .


"getIntImmCost can only estimate cost of materialising integers"

Calculate the cost of materializing a 64-bit value .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
ARM
::
NumTargetFixupKinds
]
=
{
{
"fixup_arm_ldst_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_ldst_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_pcrel_10_unscaled"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_pcrel_10"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_pcrel_10"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_thumb_adr_pcrel_10"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_adr_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_adr_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_condbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_uncondbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_condbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_uncondbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_br"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_uncondbl"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_condbl"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_blx"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_bl"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_blx"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cb"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cp"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_thumb_bcc"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>