<s>
void
HSAILInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
HSAIL
::
GPR32RegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
MI
,
DL
,
get
(
HSAIL
::
MOV_B32
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
BRIG_TYPE_B32
)
;
return
;
}
if
(
HSAIL
::
GPR64RegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
MI
,
DL
,
get
(
HSAIL
::
MOV_B64
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
BRIG_TYPE_B64
)
;
return
;
}
if
(
HSAIL
::
CRRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
MI
,
DL
,
get
(
HSAIL
::
MOV_B1
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
BRIG_TYPE_B1
)
;
return
;
}
unsigned
SrcBT
=
1
;
unsigned
DestBT
=
1
;
unsigned
CvtOpc
=
1
;
if
(
HSAIL
::
GPR32RegClass
.
contains
(
DestReg
)
&&
HSAIL
::
CRRegClass
.
contains
(
SrcReg
)
)
{
DestBT
=
BRIG_TYPE_B1
;
SrcBT
=
BRIG_TYPE_U32
;
CvtOpc
=
HSAIL
::
CVT_B1_U32
;
}
else
if
(
HSAIL
::
CRRegClass
.
contains
(
DestReg
)
&&
HSAIL
::
GPR32RegClass
.
contains
(
SrcReg
)
)
{
DestBT
=
BRIG_TYPE_U32
;
SrcBT
=
BRIG_TYPE_B1
;
CvtOpc
=
HSAIL
::
CVT_U32_B1
;
}
else
if
(
HSAIL
::
GPR64RegClass
.
contains
(
DestReg
)
&&
HSAIL
::
GPR32RegClass
.
contains
(
SrcReg
)
)
{
DestBT
=
BRIG_TYPE_U32
;
SrcBT
=
BRIG_TYPE_U64
;
CvtOpc
=
HSAIL
::
CVT_U32_U64
;
}
else
if
(
HSAIL
::
GPR32RegClass
.
contains
(
DestReg
)
&&
HSAIL
::
GPR64RegClass
.
contains
(
SrcReg
)
)
{
DestBT
=
BRIG_TYPE_U64
;
SrcBT
=
BRIG_TYPE_U32
;
CvtOpc
=
HSAIL
::
CVT_U64_U32
;
}
else
{
assert
(
!
"When do we hit this?"
)
;
return
TargetInstrInfo
::
copyPhysReg
(
MBB
,
MI
,
DL
,
DestReg
,
SrcReg
,
KillSrc
)
;
}
BuildMI
(
MBB
,
MI
,
DL
,
get
(
CvtOpc
)
,
DestReg
)
.
addImm
(
0
)
.
addImm
(
0
)
.
addImm
(
DestBT
)
.
addImm
(
SrcBT
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


"getBranchTargetOpValue expects only expressions or immediates"

getBranchTargetOpValue1SImm16 - Return binary encoding of the branch target operand .


<s> bool X86TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_X86 ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> static rtx frv_expand_unop_builtin ( enum insn_code icode , tree call , rtx target ) { rtx pat ; rtx op0 = frv_read_argument ( call , 0 ) ; target = frv_legitimize_target ( icode , target ) ; op0 = frv_legitimize_argument ( icode , 1 , op0 ) ; pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return target ; } </s>


<s>
void
SNESAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsPCRel
)
const
{
adjustFixupValue
(
Fixup
,
Target
,
Value
,
&
Asm
.
getContext
(
)
)
;
if
(
Value
==
0
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
auto
NumBits
=
Info
.
TargetSize
+
Info
.
TargetOffset
;
auto
NumBytes
=
(
NumBits
/
8
)
+
(
(
NumBits
%
8
)
==
0
0
:
1
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
<
NumBytes
;
++
i
)
{
uint8_t
mask
=
(
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
)
;
Data
[
Offset
+
i
]
|=
mask
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static rtx loongarch_unspec_address_offset ( rtx base , rtx offset , enum loongarch_symbol_type symbol_type ) { base = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , base ) , UNSPEC_ADDRESS_FIRST + symbol_type ) ; if ( offset != const0_rtx ) base = gen_rtx_PLUS ( Pmode , base , offset ) ; return gen_rtx_CONST ( Pmode , base ) ; } </s>

Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE , then add CONST_INT OFFSET to the result .


<s> virtual const NVPTXRegisterInfo & getRegisterInfo ( ) const { return RegInfo ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool isImm ( ) const override { return Kind == k_Immediate ; } </s>


"eliminateCallFramePseudoInstr size too big: "

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BR_JT : return lowerBR_JT ( Op , DAG ) ; case ISD :: BRCOND : return lowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return lowerConstantPool ( Op , DAG ) ; case ISD :: GlobalAddress : return lowerGlobalAddress ( Op , DAG ) ; case ISD :: BlockAddress : return lowerBlockAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return lowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return lowerJumpTable ( Op , DAG ) ; case ISD :: SELECT : return lowerSELECT ( Op , DAG ) ; case ISD :: SELECT_CC : return lowerSELECT_CC ( Op , DAG ) ; case ISD :: SETCC : return lowerSETCC ( Op , DAG ) ; case ISD :: VASTART : return lowerVASTART ( Op , DAG ) ; case ISD :: FCOPYSIGN : return lowerFCOPYSIGN ( Op , DAG ) ; case ISD :: FABS : return lowerFABS ( Op , DAG ) ; case ISD :: FRAMEADDR : return lowerFRAMEADDR ( Op , DAG ) ; case ISD :: RETURNADDR : return lowerRETURNADDR ( Op , DAG ) ; case ISD :: EH_RETURN : return lowerEH_RETURN ( Op , DAG ) ; case ISD :: ATOMIC_FENCE : return lowerATOMIC_FENCE ( Op , DAG ) ; case ISD :: SHL_PARTS : return lowerShiftLeftParts ( Op , DAG ) ; case ISD :: SRA_PARTS : return lowerShiftRightParts ( Op , DAG , true ) ; case ISD :: SRL_PARTS : return lowerShiftRightParts ( Op , DAG , false ) ; case ISD :: LOAD : return lowerLOAD ( Op , DAG ) ; case ISD :: STORE : return lowerSTORE ( Op , DAG ) ; case ISD :: ADD : return lowerADD ( Op , DAG ) ; case ISD :: FP_TO_SINT : return lowerFP_TO_SINT ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::BR_JT ISD::BRCOND ISD::ConstantPool ISD::GlobalAddress ISD::BlockAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::SELECT ISD::SELECT_CC ISD::SETCC ISD::VASTART ISD::FCOPYSIGN ISD::FABS ISD::FRAMEADDR ISD::RETURNADDR ISD::EH_RETURN ISD::ATOMIC_FENCE ISD::SHL_PARTS ISD::SRA_PARTS ISD::SRL_PARTS ISD::LOAD ISD::STORE ISD::ADD ISD::FP_TO_SINT


<s> void MipsSEFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const MipsSEInstrInfo & TII = * static_cast < const MipsSEInstrInfo * > ( STI . getInstrInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( 0 ) . getImm ( ) ; if ( I -> getOpcode ( ) == Mips :: ADJCALLSTACKDOWN ) Amount = - Amount ; unsigned SP = STI . isABI_N64 ( ) ? Mips :: SP_64 : Mips :: SP ; TII . adjustStackPtr ( SP , Amount , MBB , I ) ; } MBB . erase ( I ) ; } </s>

Mips Mips Mips Mips 0 Mips::ADJCALLSTACKDOWN Mips::SP_64 Mips::SP


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> static void mips_annotate_pic_call_expr ( rtx call , rtx symbol ) { rtx args_size ; args_size = XEXP ( call , 1 ) ; XEXP ( call , 1 ) = gen_rtx_UNSPEC ( GET_MODE ( args_size ) , gen_rtvec ( 2 , args_size , symbol ) , UNSPEC_CALL_ATTR ) ; } </s>

Replace the args_size operand of the call expression CALL with the call-attribute UNSPEC and fill in SYMBOL as the function symbol .


<s>
void
init_cumulative_args
(
CUMULATIVE_ARGS
*
cum
,
tree
fntype
,
rtx
libname
,
tree
fndecl
)
{
static
CUMULATIVE_ARGS
zero_cum
;
tree
param
,
next_param
;
if
(
TARGET_DEBUG_ARG
)
{
fprintf
(
stderr
,
"\ninit_cumulative_args ("
)
;
if
(
fntype
)
fprintf
(
stderr
,
"fntype code = %s, ret code = %s"
,
tree_code_name
[
(
int
)
TREE_CODE
(
fntype
)
]
,
tree_code_name
[
(
int
)
TREE_CODE
(
TREE_TYPE
(
fntype
)
)
]
)
;
else
fprintf
(
stderr
,
"no fntype"
)
;
if
(
libname
)
fprintf
(
stderr
,
", libname = %s"
,
XSTR
(
libname
,
0
)
)
;
}
*
cum
=
zero_cum
;
cum
->
nregs
=
ix86_regparm
;
if
(
TARGET_SSE
)
cum
->
sse_nregs
=
SSE_REGPARM_MAX
;
if
(
TARGET_MMX
)
cum
->
mmx_nregs
=
MMX_REGPARM_MAX
;
cum
->
warn_sse
=
true
;
cum
->
warn_mmx
=
true
;
cum
->
maybe_vaarg
=
false
;
if
(
fntype
&&
!
TARGET_64BIT
)
{
if
(
lookup_attribute
(
"fastcall"
,
TYPE_ATTRIBUTES
(
fntype
)
)
)
{
cum
->
nregs
=
2
;
cum
->
fastcall
=
1
;
}
else
cum
->
nregs
=
ix86_function_regparm
(
fntype
,
fndecl
)
;
}
cum
->
float_in_sse
=
ix86_function_sseregparm
(
fntype
,
fndecl
)
;
if
(
cum
->
nregs
||
cum
->
mmx_nregs
||
cum
->
sse_nregs
)
{
for
(
param
=
(
fntype
)
TYPE_ARG_TYPES
(
fntype
)
:
0
;
param
!=
0
;
param
=
next_param
)
{
next_param
=
TREE_CHAIN
(
param
)
;
if
(
next_param
==
0
&&
TREE_VALUE
(
param
)
!=
void_type_node
)
{
if
(
!
TARGET_64BIT
)
{
cum
->
nregs
=
0
;
cum
->
sse_nregs
=
0
;
cum
->
mmx_nregs
=
0
;
cum
->
warn_sse
=
0
;
cum
->
warn_mmx
=
0
;
cum
->
fastcall
=
0
;
cum
->
float_in_sse
=
0
;
}
cum
->
maybe_vaarg
=
true
;
}
}
}
if
(
(
!
fntype
&&
!
libname
)
||
(
fntype
&&
!
TYPE_ARG_TYPES
(
fntype
)
)
)
cum
->
maybe_vaarg
=
true
;
if
(
TARGET_DEBUG_ARG
)
fprintf
(
stderr
,
", nregs=%d )\n"
,
cum
->
nregs
)
;
return
;
}
</s>

Handle the INIT_CUMULATIVE_ARGS macro . Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is 0 .


<s>
void
print
(
raw_ostream
&
Out
)
const
{
R
.
print
(
Out
)
;
Out
<<
", Matched="
<<
Matched
;
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> static bool classof ( const PseudoSourceValue * V ) { return V -> kind ( ) == GWSResource ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> bool MipsCallEntry :: isConstant ( const MachineFrameInfo * ) const { return false ; } </s>

Returns true if we know the value of all bits .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> rtx alpha_use_linkage ( rtx func , bool lflag , bool rflag ) { struct alpha_links * al = NULL ; const char * name = XSTR ( func , 0 ) ; if ( cfun -> machine -> links ) { alpha_links * * slot = cfun -> machine -> links -> get ( name ) ; if ( slot ) al = * slot ; } else cfun -> machine -> links = hash_map < const char * , alpha_links * , string_traits > :: create_ggc ( 64 ) ; if ( al == NULL ) { size_t buf_len ; char * linksym ; tree id ; if ( name [ 0 ] == '*' ) name ++ ; id = maybe_get_identifier ( name ) ; if ( id ) { while ( IDENTIFIER_TRANSPARENT_ALIAS ( id ) ) id = TREE_CHAIN ( id ) ; name = IDENTIFIER_POINTER ( id ) ; } buf_len = strlen ( name ) + 8 + 9 ; linksym = ( char * ) alloca ( buf_len ) ; snprintf ( linksym , buf_len , "$%d..%s..lk" , cfun -> funcdef_no , name ) ; al = ggc_alloc < alpha_links > ( ) ; al -> func = func ; al -> linkage = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( linksym ) ) ; cfun -> machine -> links -> put ( ggc_strdup ( name ) , al ) ; } al -> rkind = rflag ? KIND_CODEADDR : KIND_LINKAGE ; if ( lflag ) return gen_rtx_MEM ( Pmode , plus_constant ( Pmode , al -> linkage , 8 ) ) ; else return al -> linkage ; } </s>

Return a SYMBOL_REF representing the reference to the .linkage entry of function FUNC built for calls made from CFUNDECL . LFLAG is 1 if this is the reference to the linkage pointer value , 0 if this is the reference to the function entry value . RFLAG is 1 if this a reduced reference ( code address only ) , 0 if this is a full reference .


<s>
bool
SIInstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
MachineBasicBlock
::
iterator
I
=
MBB
.
getFirstTerminator
(
)
;
auto
E
=
MBB
.
end
(
)
;
if
(
I
==
E
)
return
false
;
while
(
I
!=
E
&&
!
I
->
isBranch
(
)
&&
!
I
->
isReturn
(
)
&&
I
->
getOpcode
(
)
!=
AMDGPU
::
SI_MASK_BRANCH
)
{
switch
(
I
->
getOpcode
(
)
)
{
case
AMDGPU
::
SI_MASK_BRANCH
:
case
AMDGPU
::
S_MOV_B64_term
:
case
AMDGPU
::
S_XOR_B64_term
:
case
AMDGPU
::
S_OR_B64_term
:
case
AMDGPU
::
S_ANDN2_B64_term
:
case
AMDGPU
::
S_MOV_B32_term
:
case
AMDGPU
::
S_XOR_B32_term
:
case
AMDGPU
::
S_OR_B32_term
:
case
AMDGPU
::
S_ANDN2_B32_term
:
break
;
case
AMDGPU
::
SI_IF
:
case
AMDGPU
::
SI_ELSE
:
case
AMDGPU
::
SI_KILL_I1_TERMINATOR
:
case
AMDGPU
::
SI_KILL_F32_COND_IMM_TERMINATOR
:
return
true
;
default
:
llvm_unreachable
(
"unexpected non-branch terminator inst"
)
;
}
++
I
;
}
if
(
I
==
E
)
return
false
;
if
(
I
->
getOpcode
(
)
!=
AMDGPU
::
SI_MASK_BRANCH
)
return
analyzeBranchImpl
(
MBB
,
I
,
TBB
,
FBB
,
Cond
,
AllowModify
)
;
++
I
;
if
(
I
==
MBB
.
end
(
)
)
return
true
;
if
(
analyzeBranchImpl
(
MBB
,
I
,
TBB
,
FBB
,
Cond
,
AllowModify
)
)
return
true
;
MachineBasicBlock
*
MaskBrDest
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
if
(
TBB
!=
MaskBrDest
||
Cond
.
empty
(
)
)
return
true
;
auto
Pred
=
Cond
[
0
]
.
getImm
(
)
;
return
(
Pred
!=
EXECZ
&&
Pred
!=
EXECNZ
)
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static bool avr_warn_func_return ( tree decl ) { return ! avr_naked_function_p ( decl ) ; } </s>


<s> bool SIInstrInfo :: shouldClusterMemOps ( ArrayRef < const MachineOperand * > BaseOps1 , ArrayRef < const MachineOperand * > BaseOps2 , unsigned NumLoads ) const { assert ( ! BaseOps1 . empty ( ) && ! BaseOps2 . empty ( ) ) ; const MachineInstr & FirstLdSt = * BaseOps1 . front ( ) -> getParent ( ) ; const MachineInstr & SecondLdSt = * BaseOps2 . front ( ) -> getParent ( ) ; if ( ! memOpsHaveSameBasePtr ( FirstLdSt , BaseOps1 , SecondLdSt , BaseOps2 ) ) return false ; const MachineOperand * FirstDst = nullptr ; const MachineOperand * SecondDst = nullptr ; if ( ( isMUBUF ( FirstLdSt ) && isMUBUF ( SecondLdSt ) ) || ( isMTBUF ( FirstLdSt ) && isMTBUF ( SecondLdSt ) ) || ( isFLAT ( FirstLdSt ) && isFLAT ( SecondLdSt ) ) ) { const unsigned MaxGlobalLoadCluster = 7 ; if ( NumLoads > MaxGlobalLoadCluster ) return false ; FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: vdata ) ; if ( ! FirstDst ) FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: vdst ) ; SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: vdata ) ; if ( ! SecondDst ) SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: vdst ) ; } else if ( isSMRD ( FirstLdSt ) && isSMRD ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: sdst ) ; SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: sdst ) ; } else if ( isDS ( FirstLdSt ) && isDS ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: vdst ) ; SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: vdst ) ; } if ( ! FirstDst || ! SecondDst ) return false ; unsigned LoadClusterThreshold = 16 ; const MachineRegisterInfo & MRI = FirstLdSt . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const Register Reg = FirstDst -> getReg ( ) ; const TargetRegisterClass * DstRC = Register :: isVirtualRegister ( Reg ) ? MRI . getRegClass ( Reg ) : RI . getPhysRegClass ( Reg ) ; return ( ( NumLoads - 1 ) * ( RI . getRegSizeInBits ( * DstRC ) / 8 ) ) <= LoadClusterThreshold ; } </s>

Returns true if the two given memory operations should be scheduled adjacent .

AMDGPU SI 7 AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName 16 1 8


<s>
void
SIInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
Register
DestReg
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
SIMachineFunctionInfo
*
MFI
=
MF
->
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MachineFrameInfo
&
FrameInfo
=
MF
->
getFrameInfo
(
)
;
const
DebugLoc
&
DL
=
MBB
.
findDebugLoc
(
MI
)
;
unsigned
SpillSize
=
TRI
->
getSpillSize
(
*
RC
)
;
MachinePointerInfo
PtrInfo
=
MachinePointerInfo
::
getFixedStack
(
*
MF
,
FrameIndex
)
;
MachineMemOperand
*
MMO
=
MF
->
getMachineMemOperand
(
PtrInfo
,
MachineMemOperand
::
MOLoad
,
FrameInfo
.
getObjectSize
(
FrameIndex
)
,
FrameInfo
.
getObjectAlign
(
FrameIndex
)
)
;
if
(
RI
.
isSGPRClass
(
RC
)
)
{
MFI
->
setHasSpilledSGPRs
(
)
;
assert
(
DestReg
!=
AMDGPU
::
M0
&&
"m0 should not be reloaded into"
)
;
assert
(
DestReg
!=
AMDGPU
::
EXEC_LO
&&
DestReg
!=
AMDGPU
::
EXEC_HI
&&
DestReg
!=
AMDGPU
::
EXEC
&&
"exec should not be spilled"
)
;
const
MCInstrDesc
&
OpDesc
=
get
(
getSGPRSpillRestoreOpcode
(
SpillSize
)
)
;
if
(
DestReg
.
isVirtual
(
)
&&
SpillSize
==
4
)
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
MRI
.
constrainRegClass
(
DestReg
,
&
AMDGPU
::
SReg_32_XM0_XEXECRegClass
)
;
}
if
(
RI
.
spillSGPRToVGPR
(
)
)
FrameInfo
.
setStackID
(
FrameIndex
,
TargetStackID
::
SGPRSpill
)
;
BuildMI
(
MBB
,
MI
,
DL
,
OpDesc
,
DestReg
)
.
addFrameIndex
(
FrameIndex
)
.
addMemOperand
(
MMO
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
,
RegState
::
Implicit
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
,
RegState
::
Implicit
)
;
return
;
}
unsigned
Opcode
=
RI
.
hasAGPRs
(
RC
)
getAGPRSpillRestoreOpcode
(
SpillSize
)
:
getVGPRSpillRestoreOpcode
(
SpillSize
)
;
auto
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opcode
)
,
DestReg
)
;
if
(
RI
.
hasAGPRs
(
RC
)
)
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
Register
Tmp
=
MRI
.
createVirtualRegister
(
&
AMDGPU
::
VGPR_32RegClass
)
;
MIB
.
addReg
(
Tmp
,
RegState
::
Define
)
;
}
MIB
.
addFrameIndex
(
FrameIndex
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> unsigned RISCVTargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) const { return RISCV :: X11 ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .


<s> static void emit_final_compare_vec ( rtx str1 , rtx str2 , rtx result , rtx s1addr , rtx s2addr , rtx orig_src1 , rtx orig_src2 , rtx off_reg , rtx vec_result ) { if ( TARGET_P9_VECTOR ) { rtx diffix = gen_reg_rtx ( SImode ) ; rtx chr1 = gen_reg_rtx ( SImode ) ; rtx chr2 = gen_reg_rtx ( SImode ) ; rtx chr1_di = simplify_gen_subreg ( DImode , chr1 , SImode , 0 ) ; rtx chr2_di = simplify_gen_subreg ( DImode , chr2 , SImode , 0 ) ; emit_insn ( gen_vclzlsbb_v16qi ( diffix , vec_result ) ) ; emit_insn ( gen_vextublx ( chr1 , diffix , str1 ) ) ; emit_insn ( gen_vextublx ( chr2 , diffix , str2 ) ) ; do_sub3 ( result , chr1_di , chr2_di ) ; } else { gcc_assert ( TARGET_P8_VECTOR ) ; rtx diffix = gen_reg_rtx ( DImode ) ; rtx result_gbbd = gen_reg_rtx ( V16QImode ) ; emit_insn ( gen_p8v_vgbbd ( result_gbbd , vec_result ) ) ; rtx result_shifted = gen_reg_rtx ( V16QImode ) ; int shift_amt = ( BYTES_BIG_ENDIAN ) ? 7 : 9 ; emit_insn ( gen_altivec_vsldoi_v16qi ( result_shifted , result_gbbd , result_gbbd , GEN_INT ( shift_amt ) ) ) ; rtx diffix_df = simplify_gen_subreg ( DFmode , diffix , DImode , 0 ) ; emit_insn ( gen_p8_mfvsrd_3_v16qi ( diffix_df , result_shifted ) ) ; rtx count = gen_reg_rtx ( DImode ) ; if ( BYTES_BIG_ENDIAN ) emit_insn ( gen_clzdi2 ( count , diffix ) ) ; else emit_insn ( gen_ctzdi2 ( count , diffix ) ) ; do_add3 ( off_reg , off_reg , count ) ; rtx chr1 = gen_reg_rtx ( QImode ) ; rtx chr2 = gen_reg_rtx ( QImode ) ; rtx addr1 = gen_rtx_PLUS ( Pmode , s1addr , off_reg ) ; do_load_for_compare_from_addr ( QImode , chr1 , addr1 , orig_src1 ) ; rtx addr2 = gen_rtx_PLUS ( Pmode , s2addr , off_reg ) ; do_load_for_compare_from_addr ( QImode , chr2 , addr2 , orig_src2 ) ; machine_mode rmode = GET_MODE ( result ) ; rtx chr1_rm = simplify_gen_subreg ( rmode , chr1 , QImode , 0 ) ; rtx chr2_rm = simplify_gen_subreg ( rmode , chr2 , QImode , 0 ) ; do_sub3 ( result , chr1_rm , chr2_rm ) ; } return ; } </s>

Generate the final sequence that identifies the differing byte and generates the final result , taking into account zero bytes : P8 : vgbbd 0,0 vsldoi 0,0,0,9 mfvsrd 9,32 addi 10,9 , -1 # count trailing zero bits andc 9,10,9 popcntd 9,9 lbzx 10,28,9 # use that offset to load differing byte lbzx 3,29,9 subf 3,3,10 # subtract for final result P9 : vclzlsbb # counts trailing bytes with lsb=0 vextublx # extract differing byte STR1 is the reg rtx for data from string 1 . STR2 is the reg rtx for data from string 2 . RESULT is the reg rtx for the comparison result . S1ADDR is the register to use for the base address of the first string . S2ADDR is the register to use for the base address of the second string . ORIG_SRC1 is the unmodified rtx for the first string . ORIG_SRC2 is the unmodified rtx for the second string . OFF_REG is the register to use for the string offset for loads . VEC_RESULT is the rtx for the vector result indicating the byte difference .


<s> static void rbt_right_rotate ( struct rbt_strings * t , struct rbt_string_node * node ) { struct rbt_string_node * left = node -> left ; assert ( left ) ; node -> left = left -> right ; if ( left -> right != t -> rbt_nil ) left -> right -> par = node ; left -> par = node -> par ; if ( node -> par == t -> rbt_nil ) t -> rbt_root = left ; else if ( node == node -> par -> right ) node -> par -> right = left ; else node -> par -> left = left ; left -> right = node ; node -> par = left ; } </s>

Perform a right-rotate operation on NODE in the red-black tree .


<s> static enum machine_mode s390_cc_modes_compatible ( enum machine_mode m1 , enum machine_mode m2 ) { if ( m1 == m2 ) return m1 ; switch ( m1 ) { case CCZmode : if ( m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode ) return m2 ; return VOIDmode ; case CCSmode : case CCUmode : case CCTmode : case CCSRmode : case CCURmode : case CCZ1mode : if ( m2 == CCZmode ) return m1 ; return VOIDmode ; default : return VOIDmode ; } return VOIDmode ; } </s>

If two condition code modes are compatible , return a condition code mode which is compatible with both . Otherwise , return VOIDmode .


<s> bool AArch64InstrInfo :: analyzeBranchPredicate ( MachineBasicBlock & MBB , MachineBranchPredicate & MBP , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return true ; if ( I -> getOpcode ( ) == AArch64 :: SpeculationBarrierISBDSBEndBB || I -> getOpcode ( ) == AArch64 :: SpeculationBarrierSBEndBB ) { -- I ; } if ( ! isUnpredicatedTerminator ( * I ) ) return true ; MachineInstr * LastInst = & * I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; if ( ! isCondBranchOpcode ( LastOpc ) ) return true ; switch ( LastOpc ) { default : return true ; case AArch64 :: CBZW : case AArch64 :: CBZX : case AArch64 :: CBNZW : case AArch64 :: CBNZX : break ; } ; MBP . TrueDest = LastInst -> getOperand ( 1 ) . getMBB ( ) ; assert ( MBP . TrueDest && "expected!" ) ; MBP . FalseDest = MBB . getNextNode ( ) ; MBP . ConditionDef = nullptr ; MBP . SingleUseCondition = false ; MBP . LHS = LastInst -> getOperand ( 0 ) ; MBP . RHS = MachineOperand :: CreateImm ( 0 ) ; MBP . Predicate = LastOpc == AArch64 :: CBNZX ? MachineBranchPredicate :: PRED_NE : MachineBranchPredicate :: PRED_EQ ; return false ; } </s>

Analyze the branching code at the end of MBB and parse it into the MachineBranchPredicate structure if possible .


<s> unsigned AVRInstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { if ( BytesRemoved ) * BytesRemoved = 0 ; MachineBasicBlock :: iterator I = MBB . end ( ) ; unsigned Count = 0 ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugInstr ( ) ) { continue ; } if ( I -> getOpcode ( ) != AVR :: RJMPk && getCondFromBranchOpc ( I -> getOpcode ( ) ) == AVRCC :: COND_INVALID ) { break ; } if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++ Count ; } return Count ; } </s>

Remove the branching code at the end of the specific MBB .


"Can't return value from vararg function in memory"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> auto size ( ) const { return Data . size ( ) ; } </s>

The number of name/type pairs is returned .


<s> static bool frv_must_pass_in_stack ( const function_arg_info & arg ) { return arg . mode == BLKmode || arg . aggregate_type_p ( ) ; } </s>

Return true if we should pass an argument on the stack rather than in registers .


<s> void LC2200MCCodeEmitter :: encodeInstruction ( const MCInst & Inst , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { uint32_t CurByte = 0 ; unsigned Value = getBinaryCodeForInstr ( Inst , Fixups , STI ) ; EmitBEConstant ( Value , 4 , CurByte , OS ) ; } </s>

Encode the given Inst to bytes and append to CB .


<s> unsigned AArch64TTIImpl :: getIntrinsicInstrCost ( const IntrinsicCostAttributes & ICA , TTI :: TargetCostKind CostKind ) { auto * RetTy = ICA . getReturnType ( ) ; switch ( ICA . getID ( ) ) { case Intrinsic :: smin : case Intrinsic :: umin : case Intrinsic :: smax : case Intrinsic :: umax : { static const auto ValidMinMaxTys = { MVT :: v8i8 , MVT :: v16i8 , MVT :: v4i16 , MVT :: v8i16 , MVT :: v2i32 , MVT :: v4i32 } ; auto LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; if ( any_of ( ValidMinMaxTys , [ & LT ] ( MVT M ) { return M == LT . second ; } ) ) return LT . first ; break ; } default : break ; } return BaseT :: getIntrinsicInstrCost ( ICA , CostKind ) ; } </s>


"Instr doesn't have FrameIndex operand!"

"16-byte alignment violated in eliminateFrameIndex"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static void arc_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int bytes = arg . promoted_size_in_bytes ( ) ; int words = ( bytes + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; int i ; if ( words ) * cum = ROUND_ADVANCE_CUM ( * cum , arg . mode , arg . type ) ; for ( i = 0 ; i < words ; i ++ ) * cum = ARC_NEXT_ARG_REG ( * cum ) ; } </s>

For the ARC : the cum set here is passed on to function_arg where we look at its value and say which reg to use . Strategy : advance the regnumber here till we run out of arg regs , then set * cum to last reg . In function_arg , since * cum > last arg reg we would return 0 and thus the arg will end up on the stack . For straddling args of course function_arg_partial_nregs will come into play .


"getBranchTargetOpValue expects only expressions or immediates"

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s> static void mips_asm_file_end ( void ) { if ( NEED_INDICATE_EXEC_STACK ) file_end_indicate_exec_stack ( ) ; } </s>

If we are optimizing the global pointer , emit the text section now and any small externs which did not have .comm , etc that are needed . Also , give a warning if the data area is more than 32K and -pic because 3 instructions are needed to reference the data pointers .


<s> static void mips_set_tune ( const struct mips_cpu_info * info ) { if ( info != 0 ) { mips_tune_info = info ; mips_tune = info -> cpu ; } } </s>


"Custom lowering not defined for operation"

LowerOperation - Provide custom lowering hooks for some operations .


"Return from a call instruction in the loop."

NULL if INSN insn is valid within a low-overhead loop . Otherwise return why doloop can not be applied .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
ARM
::
NumTargetFixupKinds
]
=
{
{
"fixup_arm_ldst_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_ldst_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_pcrel_10_unscaled"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_pcrel_10"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_pcrel_10"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_thumb_adr_pcrel_10"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_adr_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_adr_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_condbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_uncondbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_condbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_uncondbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_br"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_uncondbl"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_condbl"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_blx"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_bl"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_blx"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cb"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cp"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_thumb_bcc"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> void emitGPRel32Value ( const MCExpr * Value ) override { } </s>

Emit the expression Value into the output as a gprel32 ( 32-bit GP relative ) value .


<s> static bool expand_vec_perm_shrp ( struct expand_vec_perm_d * d ) { unsigned i , nelt = d -> nelt , shift , mask ; rtx tmp , hi , lo ; if ( d -> vmode == V2SFmode ) return false ; mask = ( d -> one_operand_p ? nelt - 1 : 2 * nelt - 1 ) ; shift = d -> perm [ 0 ] ; if ( BYTES_BIG_ENDIAN && shift > nelt ) return false ; for ( i = 1 ; i < nelt ; ++ i ) if ( d -> perm [ i ] != ( ( shift + i ) & mask ) ) return false ; if ( d -> testing_p ) return true ; hi = shift < nelt ? d -> op1 : d -> op0 ; lo = shift < nelt ? d -> op0 : d -> op1 ; shift %= nelt ; shift *= GET_MODE_UNIT_SIZE ( d -> vmode ) * BITS_PER_UNIT ; gcc_assert ( IN_RANGE ( shift , 1 , 63 ) ) ; if ( BYTES_BIG_ENDIAN ) shift = 64 - shift ; tmp = gen_reg_rtx ( DImode ) ; hi = gen_lowpart ( DImode , hi ) ; lo = gen_lowpart ( DImode , lo ) ; emit_insn ( gen_shrp ( tmp , hi , lo , GEN_INT ( shift ) ) ) ; emit_move_insn ( d -> target , gen_lowpart ( d -> vmode , tmp ) ) ; return true ; } </s>

Try to expand D via a shrp instruction .


"  group = %s, path = %d, byte_len = %d\n"

"  num_imm = %d, num_imm_32 = %d, num_imm_64 = %d, imm_size = %d\n"

Print INSN dispatch information to FILE .


<s> bool enablePostRAScheduler ( ) const override { return isGeneric ( ) || isCortexA53 ( ) || isCortexA57 ( ) ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s> static void sparc_init_pic_reg ( void ) { edge entry_edge ; rtx_insn * seq ; if ( ! crtl -> uses_pic_offset_table ) return ; start_sequence ( ) ; load_got_register ( ) ; if ( ! TARGET_VXWORKS_RTP ) emit_move_insn ( pic_offset_table_rtx , got_register_rtx ) ; seq = get_insns ( ) ; end_sequence ( ) ; entry_edge = single_succ_edge ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) ; insert_insn_on_edge ( seq , entry_edge ) ; commit_one_edge_insertion ( entry_edge ) ; } </s>


<s> void VideocoreFrameLowering :: emitPrologue ( MachineFunction & MF ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> void TriCoreFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( I -> getOpcode ( ) == TriCore :: ADJCALLSTACKUP || I -> getOpcode ( ) == TriCore :: ADJCALLSTACKDOWN ) { MBB . erase ( I ) ; } return ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

TriCore TriCore TriCore::ADJCALLSTACKUP TriCore::ADJCALLSTACKDOWN


<s> void BPFFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; SavedRegs . reset ( BPF :: R6 ) ; SavedRegs . reset ( BPF :: R7 ) ; SavedRegs . reset ( BPF :: R8 ) ; SavedRegs . reset ( BPF :: R9 ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> bool Thumb2SizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { const TargetMachine & TM = MF . getTarget ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( TM . getInstrInfo ( ) ) ; STI = & TM . getSubtarget < ARMSubtarget > ( ) ; AttributeSet FnAttrs = MF . getFunction ( ) -> getAttributes ( ) ; OptimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; MinimizeSize = STI -> isMinSize ( ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; ReversePostOrderTraversal < MachineFunction * > RPOT ( & MF ) ; bool Modified = false ; for ( ReversePostOrderTraversal < MachineFunction * > :: rpo_iterator I = RPOT . begin ( ) , E = RPOT . end ( ) ; I != E ; ++ I ) Modified |= ReduceMBB ( * * I ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s>
const
char
*
thumb1_output_interwork
(
void
)
{
const
char
*
name
;
FILE
*
f
=
asm_out_file
;
gcc_assert
(
MEM_P
(
DECL_RTL
(
current_function_decl
)
)
)
;
gcc_assert
(
GET_CODE
(
XEXP
(
DECL_RTL
(
current_function_decl
)
,
0
)
)
==
SYMBOL_REF
)
;
name
=
XSTR
(
XEXP
(
DECL_RTL
(
current_function_decl
)
,
0
)
,
0
)
;
asm_fprintf
(
f
,
"\torr\t%r, %r, #1\n"
,
IP_REGNUM
,
PC_REGNUM
)
;
asm_fprintf
(
f
,
"\tbx\t%r\n"
,
IP_REGNUM
)
;
fprintf
(
f
,
"\t.code\t16\n"
)
;
if
(
arm_dllexport_name_p
(
name
)
)
name
=
arm_strip_name_encoding
(
name
)
;
asm_fprintf
(
f
,
"\t.globl %s%U%s\n"
,
STUB_NAME
,
name
)
;
fprintf
(
f
,
"\t.thumb_func\n"
)
;
asm_fprintf
(
f
,
"%s%U%s:\n"
,
STUB_NAME
,
name
)
;
return
""
;
}
</s>

Implementation of insn prologue_thumb1_interwork . This is the first `` instruction '' of a function called in ARM mode . Swap to thumb mode .


<s> bool PPCFrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return true ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! EnablePEVectorSpills || MFI . hasCalls ( ) || ! Subtarget . hasP9Vector ( ) ) return false ; BitVector BVAllocatable = TRI -> getAllocatableSet ( MF ) ; BitVector BVCalleeSaved ( TRI -> getNumRegs ( ) ) ; const PPCRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( & MF ) ; for ( unsigned i = 0 ; CSRegs [ i ] ; ++ i ) BVCalleeSaved . set ( CSRegs [ i ] ) ; for ( unsigned Reg : BVAllocatable . set_bits ( ) ) { if ( BVCalleeSaved [ Reg ] || ! PPC :: VSRCRegClass . contains ( Reg ) || MF . getRegInfo ( ) . isPhysRegUsed ( Reg ) ) BVAllocatable . reset ( Reg ) ; } bool AllSpilledToReg = true ; unsigned LastVSRUsedForSpill = 0 ; for ( auto & CS : CSI ) { if ( BVAllocatable . none ( ) ) return false ; unsigned Reg = CS . getReg ( ) ; if ( ! PPC :: G8RCRegClass . contains ( Reg ) ) { AllSpilledToReg = false ; continue ; } if ( LastVSRUsedForSpill != 0 ) { CS . setDstReg ( LastVSRUsedForSpill ) ; BVAllocatable . reset ( LastVSRUsedForSpill ) ; LastVSRUsedForSpill = 0 ; continue ; } unsigned VolatileVFReg = BVAllocatable . find_first ( ) ; if ( VolatileVFReg < BVAllocatable . size ( ) ) { CS . setDstReg ( VolatileVFReg ) ; LastVSRUsedForSpill = VolatileVFReg ; } else { AllSpilledToReg = false ; } } return AllSpilledToReg ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> void prepare_move_operands ( rtx * operands , machine_mode mode ) { if ( GET_CODE ( operands [ 0 ] ) == MEM && ! reg_or_0_operand ( operands [ 1 ] , mode ) ) operands [ 1 ] = force_reg ( mode , operands [ 1 ] ) ; } </s>

Prepare operands for a move define_expand in MODE .


<s> int arc_register_move_cost ( machine_mode , enum reg_class from_class , enum reg_class to_class ) { if ( TARGET_ARC600 ) { if ( to_class == MPY_WRITABLE_CORE_REGS ) return 3 ; else if ( to_class == LPCOUNT_REG ) return 6 ; else if ( to_class == WRITABLE_CORE_REGS ) return 6 ; } if ( from_class == LPCOUNT_REG ) return 1000 ; if ( to_class == LPCOUNT_REG ) return 6 ; if ( ( TARGET_ARC700 || TARGET_EM ) && TARGET_DPFP && from_class == DOUBLE_REGS && to_class == DOUBLE_REGS ) return 100 ; return 2 ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"AArch64 Conditional Compares"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"Module has aliases, which NVPTX does not support."

Set up the AsmPrinter when we are working on a new module .


<s> static bool nds32_expand_movmemsi_loop_unknown_size ( rtx dstmem , rtx srcmem , rtx size , rtx alignment ) { rtx dst_base_reg , src_base_reg ; rtx dst_itr , src_itr ; rtx dstmem_m , srcmem_m , dst_itr_m , src_itr_m ; rtx dst_end ; rtx size_least_3_bit ; rtx double_word_end ; rtx double_word_mode_loop , byte_mode_entry , byte_mode_loop , end_label ; rtx tmp ; rtx mask_least_3_bit ; int start_regno ; bool align_to_4_bytes = ( INTVAL ( alignment ) & 3 ) == 0 ; if ( TARGET_ISA_V3M && ! align_to_4_bytes ) return 0 ; if ( TARGET_REDUCED_REGS ) start_regno = 2 ; else start_regno = 16 ; dst_itr = gen_reg_rtx ( Pmode ) ; src_itr = gen_reg_rtx ( Pmode ) ; dst_end = gen_reg_rtx ( Pmode ) ; tmp = gen_reg_rtx ( QImode ) ; mask_least_3_bit = GEN_INT ( ~ 7 ) ; double_word_mode_loop = gen_label_rtx ( ) ; byte_mode_entry = gen_label_rtx ( ) ; byte_mode_loop = gen_label_rtx ( ) ; end_label = gen_label_rtx ( ) ; dst_base_reg = copy_to_mode_reg ( Pmode , XEXP ( dstmem , 0 ) ) ; src_base_reg = copy_to_mode_reg ( Pmode , XEXP ( srcmem , 0 ) ) ; size_least_3_bit = expand_binop ( SImode , and_optab , size , mask_least_3_bit , NULL_RTX , 0 , OPTAB_WIDEN ) ; dst_end = expand_binop ( Pmode , add_optab , dst_base_reg , size , NULL_RTX , 0 , OPTAB_WIDEN ) ; emit_move_insn ( dst_itr , dst_base_reg ) ; emit_move_insn ( src_itr , src_base_reg ) ; emit_cmp_and_jump_insns ( size_least_3_bit , const0_rtx , EQ , NULL , SImode , 1 , byte_mode_entry ) ; double_word_end = expand_binop ( Pmode , add_optab , dst_base_reg , size_least_3_bit , NULL_RTX , 0 , OPTAB_WIDEN ) ; emit_label ( double_word_mode_loop ) ; src_itr_m = src_itr ; dst_itr_m = dst_itr ; srcmem_m = srcmem ; dstmem_m = dstmem ; nds32_emit_mem_move_block ( start_regno , 2 , & dst_itr_m , & dstmem_m , & src_itr_m , & srcmem_m , true ) ; emit_move_insn ( dst_itr , dst_itr_m ) ; emit_move_insn ( src_itr , src_itr_m ) ; emit_cmp_and_jump_insns ( double_word_end , dst_itr , NE , NULL , Pmode , 1 , double_word_mode_loop ) ; emit_label ( byte_mode_entry ) ; emit_cmp_and_jump_insns ( dst_itr , dst_end , EQ , NULL , Pmode , 1 , end_label ) ; emit_label ( byte_mode_loop ) ; nds32_emit_post_inc_load_store ( tmp , src_itr , QImode , true ) ; nds32_emit_post_inc_load_store ( tmp , dst_itr , QImode , false ) ; emit_cmp_and_jump_insns ( dst_itr , dst_end , NE , NULL , SImode , 1 , byte_mode_loop ) ; emit_label ( end_label ) ; return true ; } </s>

Auxiliary function for expand movmem pattern .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < PatmosSinglePathInfo > ( ) ; AU . addRequired < MachinePostDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"AdvSIMD Scalar Operation Optimization"
;
}
</s>


<s> DecodeStatus PPCDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CS ) const { auto * ReadFunc = IsLittleEndian ? support :: endian :: read32le : support :: endian :: read32be ; if ( STI . getFeatureBits ( ) [ PPC :: FeaturePrefixInstrs ] && Bytes . size ( ) >= 8 ) { uint32_t Prefix = ReadFunc ( Bytes . data ( ) ) ; uint32_t BaseInst = ReadFunc ( Bytes . data ( ) + 4 ) ; uint64_t Inst = BaseInst | ( uint64_t ) Prefix << 32 ; DecodeStatus result = decodeInstruction ( DecoderTable64 , MI , Inst , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = 8 ; return result ; } } Size = 4 ; if ( Bytes . size ( ) < 4 ) { Size = 0 ; return MCDisassembler :: Fail ; } uint64_t Inst = ReadFunc ( Bytes . data ( ) ) ; if ( STI . getFeatureBits ( ) [ PPC :: FeatureSPE ] ) { DecodeStatus result = decodeInstruction ( DecoderTableSPE32 , MI , Inst , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) return result ; } return decodeInstruction ( DecoderTable32 , MI , Inst , Address , this , STI ) ; } </s>

Returns the disassembly of a single instruction .


"Unexpected instruction for custom inserter!"

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCInstFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
{
assert
(
0
&&
"RelaxInstruction() unimplemented"
)
;
return
false
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .

Mips
0
"RelaxInstruction() unimplemented"


"eliminateFrameIndex currently requires hasFP"

"Frame offsets outside of the signed 12-bit range not supported"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> rtx sh_try_omit_signzero_extend ( rtx extended_op , rtx_insn * insn ) { if ( REG_P ( extended_op ) ) extended_op = extended_op ; else if ( GET_CODE ( extended_op ) == SUBREG && REG_P ( SUBREG_REG ( extended_op ) ) ) extended_op = SUBREG_REG ( extended_op ) ; else return NULL_RTX ; if ( GET_MODE ( extended_op ) != SImode ) return NULL_RTX ; set_of_reg s = sh_find_set_of_reg ( extended_op , insn , prev_nonnote_insn_bb ) ; if ( s . set_src == NULL_RTX ) return NULL_RTX ; if ( t_reg_operand ( s . set_src , VOIDmode ) || negt_reg_operand ( s . set_src , VOIDmode ) ) return extended_op ; else if ( sh_is_logical_t_store_expr ( s . set_src , s . insn ) ) return extended_op ; return NULL_RTX ; } </s>

Given the operand that is extended in a sign/zero extend insn , and the insn , try to figure out whether the sign/zero extension can be replaced by a simple reg-reg copy . If so , the replacement reg rtx is returned , NULL_RTX otherwise .


<s> static bool m68k_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { return ( ! TARGET_HARD_FLOAT || ( ( GET_MODE_CLASS ( mode1 ) == MODE_FLOAT || GET_MODE_CLASS ( mode1 ) == MODE_COMPLEX_FLOAT ) == ( GET_MODE_CLASS ( mode2 ) == MODE_FLOAT || GET_MODE_CLASS ( mode2 ) == MODE_COMPLEX_FLOAT ) ) ) ; } </s>


<s>
std
::
vector
<
const
SUnit
*
>
GCNILPScheduler
::
schedule
(
ArrayRef
<
const
SUnit
*
>
BotRoots
,
const
ScheduleDAG
&
DAG
)
{
auto
&
SUnits
=
const_cast
<
ScheduleDAG
&
>
(
DAG
)
.
SUnits
;
std
::
vector
<
SUnit
>
SUSavedCopy
;
SUSavedCopy
.
resize
(
SUnits
.
size
(
)
)
;
for
(
const
SUnit
&
SU
:
SUnits
)
SUSavedCopy
[
SU
.
NodeNum
]
=
SU
;
SUNumbers
.
assign
(
SUnits
.
size
(
)
,
0
)
;
for
(
const
SUnit
&
SU
:
SUnits
)
CalcNodeSethiUllmanNumber
(
&
SU
,
SUNumbers
)
;
for
(
auto
SU
:
BotRoots
)
{
AvailQueue
.
push_back
(
*
new
(
Alloc
.
Allocate
(
)
)
Candidate
(
const_cast
<
SUnit
*
>
(
SU
)
)
)
;
}
releasePredecessors
(
&
DAG
.
ExitSU
)
;
std
::
vector
<
const
SUnit
*
>
Schedule
;
Schedule
.
reserve
(
SUnits
.
size
(
)
)
;
while
(
true
)
{
if
(
AvailQueue
.
empty
(
)
&&
!
PendingQueue
.
empty
(
)
)
{
auto
EarliestSU
=
std
::
min_element
(
PendingQueue
.
begin
(
)
,
PendingQueue
.
end
(
)
,
[
=
]
(
const
Candidate
&
C1
,
const
Candidate
&
C2
)
{
return
C1
.
SU
->
getHeight
(
)
<
C2
.
SU
->
getHeight
(
)
;
}
)
->
SU
;
advanceToCycle
(
std
::
max
(
CurCycle
+
1
,
EarliestSU
->
getHeight
(
)
)
)
;
}
if
(
AvailQueue
.
empty
(
)
)
break
;
DEBUG
(
dbgs
(
)
<<
"\n=== Picking candidate\n"
"Ready queue:"
;
for
(
auto
&
C
:
AvailQueue
)
dbgs
(
)
<<
' '
<<
C
.
SU
->
NodeNum
;
dbgs
(
)
<<
'\n'
;
)
;
auto
C
=
pickCandidate
(
)
;
assert
(
C
)
;
AvailQueue
.
remove
(
*
C
)
;
auto
SU
=
C
->
SU
;
DEBUG
(
dbgs
(
)
<<
"Selected "
;
SU
->
dump
(
&
DAG
)
)
;
advanceToCycle
(
SU
->
getHeight
(
)
)
;
releasePredecessors
(
SU
)
;
Schedule
.
push_back
(
SU
)
;
SU
->
isScheduled
=
true
;
}
assert
(
SUnits
.
size
(
)
==
Schedule
.
size
(
)
)
;
std
::
reverse
(
Schedule
.
begin
(
)
,
Schedule
.
end
(
)
)
;
for
(
auto
&
SU
:
SUnits
)
SU
=
SUSavedCopy
[
SU
.
NodeNum
]
;
return
Schedule
;
}
</s>

Schedule - This is called back from ScheduleDAGInstrs : :Run ( ) when it 's time to do some work .

AMDGPU
0
1
"\n=== Picking candidate\n"
"Ready queue:"
"Selected "


"variable %q+D located in address space %qs beyond flash "

"variable %q+D located in address space %qs"

" which is not supported for architecture %qs"

"variable %q+D must be const in order to be put into"

Add the section attribute if the variable is in progmem .


<s>
bool
ARMAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
;
bool
PendConditionalInstruction
=
false
;
SmallVector
<
NearMissInfo
,
4
>
NearMisses
;
MatchResult
=
MatchInstruction
(
Operands
,
Inst
,
NearMisses
,
MatchingInlineAsm
,
PendConditionalInstruction
,
Out
)
;
switch
(
MatchResult
)
{
case
Match_Success
:
LLVM_DEBUG
(
dbgs
(
)
<<
"Parsed as: "
;
Inst
.
dump_pretty
(
dbgs
(
)
,
MII
.
getName
(
Inst
.
getOpcode
(
)
)
)
;
dbgs
(
)
<<
"\n"
)
;
if
(
validateInstruction
(
Inst
,
Operands
)
)
{
forwardITPosition
(
)
;
forwardVPTPosition
(
)
;
return
true
;
}
{
while
(
processInstruction
(
Inst
,
Operands
,
Out
)
)
LLVM_DEBUG
(
dbgs
(
)
<<
"Changed to: "
;
Inst
.
dump_pretty
(
dbgs
(
)
,
MII
.
getName
(
Inst
.
getOpcode
(
)
)
)
;
dbgs
(
)
<<
"\n"
)
;
}
forwardITPosition
(
)
;
forwardVPTPosition
(
)
;
if
(
Inst
.
getOpcode
(
)
==
ARM
::
ITasm
)
return
false
;
Inst
.
setLoc
(
IDLoc
)
;
if
(
PendConditionalInstruction
)
{
PendingConditionalInsts
.
push_back
(
Inst
)
;
if
(
isITBlockFull
(
)
||
isITBlockTerminator
(
Inst
)
)
flushPendingInstructions
(
Out
)
;
}
else
{
Out
.
emitInstruction
(
Inst
,
getSTI
(
)
)
;
}
return
false
;
case
Match_NearMisses
:
ReportNearMisses
(
NearMisses
,
IDLoc
,
Operands
)
;
return
true
;
case
Match_MnemonicFail
:
{
FeatureBitset
FBS
=
ComputeAvailableFeatures
(
getSTI
(
)
.
getFeatureBits
(
)
)
;
std
::
string
Suggestion
=
ARMMnemonicSpellCheck
(
(
(
ARMOperand
&
)
*
Operands
[
0
]
)
.
getToken
(
)
,
FBS
)
;
return
Error
(
IDLoc
,
"invalid instruction"
+
Suggestion
,
(
(
ARMOperand
&
)
*
Operands
[
0
]
)
.
getLocRange
(
)
)
;
}
}
llvm_unreachable
(
"Implement any new match types added!"
)
;
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .

ARM
ARM
4
"Parsed as: "
"\n"
"Changed to: "
"\n"
ARM::ITasm
ARM
ARM
0
"invalid instruction"
ARM
0
"Implement any new match types added!"


<s> bool AMDGPUTargetLowering :: isFPExtFoldable ( unsigned Opcode , EVT DestVT , EVT SrcVT ) const { return Opcode == ISD :: FMAD && Subtarget -> hasMadMixInsts ( ) && DestVT . getScalarType ( ) == MVT :: f32 && ! Subtarget -> hasFP32Denormals ( ) && SrcVT . getScalarType ( ) == MVT :: f16 ; } </s>

Return true if an fpext operation input to an Opcode operation is free ( for instance , because half-precision floating-point numbers are implicitly extended to float-precision ) for an FMA instruction .


<s> int AArch64TTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( ISD == ISD :: SDIV && Opd2Info == TargetTransformInfo :: OK_UniformConstantValue && Opd2PropInfo == TargetTransformInfo :: OP_PowerOf2 ) { int Cost = getArithmeticInstrCost ( Instruction :: Add , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Sub , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Select , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: AShr , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return Cost ; } switch ( ISD ) { default : return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: ADD : case ISD :: MUL : case ISD :: XOR : case ISD :: OR : case ISD :: AND : return 1 * LT . first ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .

AArch64 AArch64 ISD::SDIV ISD::ADD ISD::MUL ISD::XOR ISD::OR ISD::AND 1


<s> bool AMDGPULateCodeGenPrepare :: doInitialization ( Module & M ) { Mod = & M ; DL = & Mod -> getDataLayout ( ) ; return false ; } </s>


<s> static bool riscv_leaf_function_p ( void ) { if ( cfun -> machine -> is_leaf == 0 ) cfun -> machine -> is_leaf = leaf_function_p ( ) ? 1 : - 1 ; return cfun -> machine -> is_leaf > 0 ; } </s>

Return leaf_function_p ( ) and memoize the result .


"PrintAsmMemoryOperand not implemented yet!\n"

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> static const char * getName ( ) { return DEBUG_TYPE ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> void GCNMaxOccupancySchedStrategy :: pickNodeFromQueue ( SchedBoundary & Zone , const CandPolicy & ZonePolicy , const RegPressureTracker & RPTracker , SchedCandidate & Cand ) { const SIRegisterInfo * SRI = static_cast < const SIRegisterInfo * > ( TRI ) ; ArrayRef < unsigned > Pressure = RPTracker . getRegSetPressureAtPos ( ) ; unsigned SGPRPressure = Pressure [ SRI -> getSGPRPressureSet ( ) ] ; unsigned VGPRPressure = Pressure [ SRI -> getVGPRPressureSet ( ) ] ; ReadyQueue & Q = Zone . Available ; for ( SUnit * SU : Q ) { SchedCandidate TryCand ( ZonePolicy ) ; initCandidate ( TryCand , SU , Zone . isTop ( ) , RPTracker , SRI , SGPRPressure , VGPRPressure ) ; SchedBoundary * ZoneArg = Cand . AtTop == TryCand . AtTop ? & Zone : nullptr ; GenericScheduler :: tryCandidate ( Cand , TryCand , ZoneArg ) ; if ( TryCand . Reason != NoCand ) { if ( TryCand . ResDelta == SchedResourceDelta ( ) ) TryCand . initResourceDelta ( Zone . DAG , SchedModel ) ; Cand . setBest ( TryCand ) ; LLVM_DEBUG ( traceCandidate ( Cand ) ) ; } } } </s>

Pick the best candidate from the queue .


<s> static void riscv_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; struct riscv_arg_info info ; riscv_get_arg_info ( & info , cum , mode , type , named , false ) ; cum -> num_fprs = info . fpr_offset + info . num_fprs ; cum -> num_gprs = info . gpr_offset + info . num_gprs ; } </s>


<s> NVPTXTargetLowering :: ConstraintType NVPTXTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'b' : case 'r' : case 'h' : case 'c' : case 'l' : case 'f' : case 'd' : case '0' : case 'N' : return C_RegisterClass ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s>
void
RISCVInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MBBI
,
const
DebugLoc
&
DL
,
MCRegister
DstReg
,
MCRegister
SrcReg
,
bool
KillSrc
)
const
{
if
(
RISCV
::
GPRRegClass
.
contains
(
DstReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
RISCV
::
ADDI
)
,
DstReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
0
)
;
return
;
}
unsigned
Opc
;
bool
IsScalableVector
=
false
;
if
(
RISCV
::
FPR16RegClass
.
contains
(
DstReg
,
SrcReg
)
)
Opc
=
RISCV
::
FSGNJ_H
;
else
if
(
RISCV
::
FPR32RegClass
.
contains
(
DstReg
,
SrcReg
)
)
Opc
=
RISCV
::
FSGNJ_S
;
else
if
(
RISCV
::
FPR64RegClass
.
contains
(
DstReg
,
SrcReg
)
)
Opc
=
RISCV
::
FSGNJ_D
;
else
if
(
RISCV
::
VRRegClass
.
contains
(
DstReg
,
SrcReg
)
)
{
Opc
=
RISCV
::
PseudoVMV1R_V
;
IsScalableVector
=
true
;
}
else
if
(
RISCV
::
VRM2RegClass
.
contains
(
DstReg
,
SrcReg
)
)
{
Opc
=
RISCV
::
PseudoVMV2R_V
;
IsScalableVector
=
true
;
}
else
if
(
RISCV
::
VRM4RegClass
.
contains
(
DstReg
,
SrcReg
)
)
{
Opc
=
RISCV
::
PseudoVMV4R_V
;
IsScalableVector
=
true
;
}
else
if
(
RISCV
::
VRM8RegClass
.
contains
(
DstReg
,
SrcReg
)
)
{
Opc
=
RISCV
::
PseudoVMV8R_V
;
IsScalableVector
=
true
;
}
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
if
(
IsScalableVector
)
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
Opc
)
,
DstReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
Opc
)
,
DstReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> static bool riscv_legitimate_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { return riscv_const_insns ( x ) > 0 ; } </s>


<s> void ARM64ConditionalCompares :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineBranchProbabilityInfo > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; AU . addRequired < MachineTraceMetrics > ( ) ; AU . addPreserved < MachineTraceMetrics > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


"ARMHWLoops: Trip count does not fit into 32bits\n"

Query the target whether it would be profitable to convert the given loop into a hardware loop .


<s> CSKYTargetLowering :: ConstraintType CSKYTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'a' : case 'b' : case 'v' : case 'w' : case 'y' : return C_RegisterClass ; case 'c' : case 'l' : case 'h' : case 'z' : return C_Register ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>


<s> unsigned X86FastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( DL , C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const auto * CI = dyn_cast < ConstantInt > ( C ) ) return X86MaterializeInt ( CI , VT ) ; if ( const auto * CFP = dyn_cast < ConstantFP > ( C ) ) return X86MaterializeFP ( CFP , VT ) ; if ( const auto * GV = dyn_cast < GlobalValue > ( C ) ) return X86MaterializeGV ( GV , VT ) ; if ( isa < UndefValue > ( C ) ) { unsigned Opc = 0 ; switch ( VT . SimpleTy ) { default : break ; case MVT :: f32 : if ( ! X86ScalarSSEf32 ) Opc = X86 :: LD_Fp032 ; break ; case MVT :: f64 : if ( ! X86ScalarSSEf64 ) Opc = X86 :: LD_Fp064 ; break ; case MVT :: f80 : Opc = X86 :: LD_Fp080 ; break ; } if ( Opc ) { Register ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; return ResultReg ; } } return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


"Invalid number of NOP bytes requested!"

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> unsigned HexagonTTIImpl :: getCallInstrCost ( Function * F , Type * RetTy , ArrayRef < Type * > Tys , TTI :: TargetCostKind CostKind ) { return BaseT :: getCallInstrCost ( F , RetTy , Tys , CostKind ) ; } </s>

Compute a cost of the given call instruction .


<s> bool ia64_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { return ( to == BR_REG ( 0 ) ? crtl -> is_leaf : true ) ; } </s>

Worker function for TARGET_CAN_ELIMINATE .


"instruction requires a CPU feature not currently enabled"


<s> static rtx altivec_expand_ld_builtin ( tree exp , rtx target , bool * expandedp ) { tree fndecl = TREE_OPERAND ( TREE_OPERAND ( exp , 0 ) , 0 ) ; tree arglist = TREE_OPERAND ( exp , 1 ) ; unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; tree arg0 ; enum machine_mode tmode , mode0 ; rtx pat , op0 ; enum insn_code icode ; switch ( fcode ) { case ALTIVEC_BUILTIN_LD_INTERNAL_16qi : icode = CODE_FOR_altivec_lvx_v16qi ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_8hi : icode = CODE_FOR_altivec_lvx_v8hi ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_4si : icode = CODE_FOR_altivec_lvx_v4si ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_4sf : icode = CODE_FOR_altivec_lvx_v4sf ; break ; default : * expandedp = false ; return NULL_RTX ; } * expandedp = true ; arg0 = TREE_VALUE ( arglist ) ; op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , 0 ) ; tmode = insn_data [ icode ] . operand [ 0 ] . mode ; mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; if ( target == 0 || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>


<s> bool ix86_force_load_from_GOT_p ( rtx x , bool call_p ) { return ( ( TARGET_64BIT || ( ! flag_pic && HAVE_AS_IX86_GOT32X ) ) && ! TARGET_PECOFF && ! TARGET_MACHO && ( ! flag_pic || this_is_asm_operands ) && ix86_cmodel != CM_LARGE && ix86_cmodel != CM_LARGE_PIC && GET_CODE ( x ) == SYMBOL_REF && ( ( ! call_p && ( ! ix86_direct_extern_access || ( SYMBOL_REF_DECL ( x ) && lookup_attribute ( "nodirect_extern_access" , DECL_ATTRIBUTES ( SYMBOL_REF_DECL ( x ) ) ) ) ) ) || ( SYMBOL_REF_FUNCTION_P ( x ) && ( ! flag_plt || ( SYMBOL_REF_DECL ( x ) && lookup_attribute ( "noplt" , DECL_ATTRIBUTES ( SYMBOL_REF_DECL ( x ) ) ) ) ) ) ) && ! SYMBOL_REF_LOCAL_P ( x ) ) ; } </s>

True if the function symbol operand X should be loaded from GOT . NB : In 32-bit mode , only non-PIC is allowed in inline assembly statements , since a PIC register could not be available at the call site .


<s> static section * iq2000_select_section ( tree decl , int reloc ATTRIBUTE_UNUSED , unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED ) { if ( TARGET_EMBEDDED_DATA ) { if ( ( TREE_CODE ( decl ) == VAR_DECL && TREE_READONLY ( decl ) && ! TREE_SIDE_EFFECTS ( decl ) && DECL_INITIAL ( decl ) && ( DECL_INITIAL ( decl ) == error_mark_node || TREE_CONSTANT ( DECL_INITIAL ( decl ) ) ) ) || TREE_CODE ( decl ) != VAR_DECL ) return readonly_data_section ; else return data_section ; } else { if ( ( TREE_CODE ( decl ) == VAR_DECL && TREE_READONLY ( decl ) && ! TREE_SIDE_EFFECTS ( decl ) && DECL_INITIAL ( decl ) && ( DECL_INITIAL ( decl ) == error_mark_node || TREE_CONSTANT ( DECL_INITIAL ( decl ) ) ) ) || TREE_CODE ( decl ) != VAR_DECL ) return readonly_data_section ; else return data_section ; } } </s>

Choose the section to use for DECL . RELOC is true if its value contains any relocatable expression . Some of the logic used here needs to be replicated in ENCODE_SECTION_INFO in iq2000.h so that references to these symbols are done correctly .


<s> static int arm_size_return_regs ( void ) { enum machine_mode mode ; if ( current_function_return_rtx != 0 ) mode = GET_MODE ( current_function_return_rtx ) ; else mode = DECL_MODE ( DECL_RESULT ( current_function_decl ) ) ; return GET_MODE_SIZE ( mode ) ; } </s>

Calculate the size of the return value that is passed in registers .


<s> static void dump_tree_node_info ( fma_forest * forest , fma_node * node ) { node -> dump_info ( forest ) ; } </s>

Wrapper around fma_node : :dump_info for use as parameter of function pointer type in func_fma_steering : :dfs .


<s> bool SIInstrInfo :: shouldClusterMemOps ( ArrayRef < const MachineOperand * > BaseOps1 , ArrayRef < const MachineOperand * > BaseOps2 , unsigned NumLoads , unsigned NumBytes ) const { assert ( ! BaseOps1 . empty ( ) && ! BaseOps2 . empty ( ) ) ; const MachineInstr & FirstLdSt = * BaseOps1 . front ( ) -> getParent ( ) ; const MachineInstr & SecondLdSt = * BaseOps2 . front ( ) -> getParent ( ) ; if ( ! memOpsHaveSameBasePtr ( FirstLdSt , BaseOps1 , SecondLdSt , BaseOps2 ) ) return false ; const MachineOperand * FirstDst = nullptr ; const MachineOperand * SecondDst = nullptr ; if ( ( isMUBUF ( FirstLdSt ) && isMUBUF ( SecondLdSt ) ) || ( isMTBUF ( FirstLdSt ) && isMTBUF ( SecondLdSt ) ) || ( isFLAT ( FirstLdSt ) && isFLAT ( SecondLdSt ) ) ) { const unsigned MaxGlobalLoadCluster = 7 ; if ( NumLoads > MaxGlobalLoadCluster ) return false ; FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: vdata ) ; if ( ! FirstDst ) FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: vdst ) ; SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: vdata ) ; if ( ! SecondDst ) SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: vdst ) ; } else if ( isSMRD ( FirstLdSt ) && isSMRD ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: sdst ) ; SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: sdst ) ; } else if ( isDS ( FirstLdSt ) && isDS ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: vdst ) ; SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: vdst ) ; } if ( ! FirstDst || ! SecondDst ) return false ; unsigned LoadClusterThreshold = 16 ; const MachineRegisterInfo & MRI = FirstLdSt . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const Register Reg = FirstDst -> getReg ( ) ; const TargetRegisterClass * DstRC = Register :: isVirtualRegister ( Reg ) ? MRI . getRegClass ( Reg ) : RI . getPhysRegClass ( Reg ) ; return ( ( NumLoads - 1 ) * ( RI . getRegSizeInBits ( * DstRC ) / 8 ) ) <= LoadClusterThreshold ; } </s>

Returns true if the two given memory operations should be scheduled adjacent .

AMDGPU SI 7 AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName 16 1 8


<s> static bool s390_vector_mode_supported_p ( machine_mode mode ) { machine_mode inner ; if ( ! VECTOR_MODE_P ( mode ) || ! TARGET_VX || GET_MODE_SIZE ( mode ) > 16 ) return false ; inner = GET_MODE_INNER ( mode ) ; switch ( inner ) { case E_QImode : case E_HImode : case E_SImode : case E_DImode : case E_TImode : case E_SFmode : case E_DFmode : case E_TFmode : return true ; default : return false ; } } </s>

Return true if the back end supports vector mode MODE .


<s> bool mprocFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> hashval_t builtin_hasher :: hash ( builtin_hash_struct * bh ) { unsigned ret = 0 ; int i ; for ( i = 0 ; i < 4 ; i ++ ) { ret = ( ret * ( unsigned ) MAX_MACHINE_MODE ) + ( ( unsigned ) bh -> mode [ i ] ) ; ret = ( ret * 2 ) + bh -> uns_p [ i ] ; } return ret ; } </s>

Hash function for builtin functions with up to 3 arguments and a return type .


<s> void MipsAsmPrinter :: emitInlineAsmEnd ( const MCSubtargetInfo & StartInfo , const MCSubtargetInfo * EndInfo ) const { OutStreamer . AddBlankLine ( ) ; getTargetStreamer ( ) . emitDirectiveSetPop ( ) ; } </s>

Let the target do anything it needs to do after emitting inlineasm .


<s> MVT RISCVTargetLowering :: getScalarShiftAmountTy ( const DataLayout & DL , EVT ) const { return Subtarget . getXLenVT ( ) ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> unsigned MipsMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups ) const { if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; unsigned RegNo = getMipsRegisterNumbering ( Reg ) ; return RegNo ; } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isFPImm ( ) ) { return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( 32 ) . getLimitedValue ( ) ) ; } assert ( MO . isExpr ( ) ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; if ( Kind == MCExpr :: Binary ) { Expr = static_cast < const MCBinaryExpr * > ( Expr ) -> getLHS ( ) ; Kind = Expr -> getKind ( ) ; } assert ( Kind == MCExpr :: SymbolRef ) ; Mips :: Fixups FixupKind ; switch ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) ) { case MCSymbolRefExpr :: VK_Mips_GPREL : FixupKind = Mips :: fixup_Mips_GPREL16 ; break ; case MCSymbolRefExpr :: VK_Mips_GOT_CALL : FixupKind = Mips :: fixup_Mips_CALL16 ; break ; case MCSymbolRefExpr :: VK_Mips_GOT16 : FixupKind = Mips :: fixup_Mips_GOT_Global ; break ; case MCSymbolRefExpr :: VK_Mips_GOT : FixupKind = Mips :: fixup_Mips_GOT_Local ; break ; case MCSymbolRefExpr :: VK_Mips_ABS_HI : FixupKind = Mips :: fixup_Mips_HI16 ; break ; case MCSymbolRefExpr :: VK_Mips_ABS_LO : FixupKind = Mips :: fixup_Mips_LO16 ; break ; case MCSymbolRefExpr :: VK_Mips_TLSGD : FixupKind = Mips :: fixup_Mips_TLSGD ; break ; case MCSymbolRefExpr :: VK_Mips_TLSLDM : FixupKind = Mips :: fixup_Mips_TLSLDM ; break ; case MCSymbolRefExpr :: VK_Mips_DTPREL_HI : FixupKind = Mips :: fixup_Mips_DTPREL_HI ; break ; case MCSymbolRefExpr :: VK_Mips_DTPREL_LO : FixupKind = Mips :: fixup_Mips_DTPREL_LO ; break ; case MCSymbolRefExpr :: VK_Mips_GOTTPREL : FixupKind = Mips :: fixup_Mips_GOTTPREL ; break ; case MCSymbolRefExpr :: VK_Mips_TPREL_HI : FixupKind = Mips :: fixup_Mips_TPREL_HI ; break ; case MCSymbolRefExpr :: VK_Mips_TPREL_LO : FixupKind = Mips :: fixup_Mips_TPREL_LO ; break ; default : break ; } Fixups . push_back ( MCFixup :: Create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) ) ) ; return 0 ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> void XCoreInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , get ( XCore :: STWFI ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool mips_legitimize_address ( rtx * xloc , enum machine_mode mode ) { enum mips_symbol_type symbol_type ; if ( mips_tls_operand_p ( * xloc ) ) { * xloc = mips_legitimize_tls_address ( * xloc ) ; return true ; } if ( mips_symbolic_constant_p ( * xloc , & symbol_type ) && mips_symbolic_address_p ( symbol_type , mode ) && mips_split_p [ symbol_type ] ) { * xloc = mips_split_symbol ( 0 , * xloc ) ; return true ; } if ( GET_CODE ( * xloc ) == PLUS && GET_CODE ( XEXP ( * xloc , 1 ) ) == CONST_INT ) { rtx reg ; reg = XEXP ( * xloc , 0 ) ; if ( ! mips_valid_base_register_p ( reg , mode , 0 ) ) reg = copy_to_mode_reg ( Pmode , reg ) ; * xloc = mips_add_offset ( 0 , reg , INTVAL ( XEXP ( * xloc , 1 ) ) ) ; return true ; } return false ; } </s>

This function is used to implement LEGITIMIZE_ADDRESS . If * XLOC can be legitimized in a way that the generic machinery might not expect , put the new address in * XLOC and return true . MODE is the mode of the memory being accessed .


<s> int arm_early_store_addr_dep_ptr ( rtx producer , rtx consumer ) { rtx value = arm_find_sub_rtx_with_code ( PATTERN ( producer ) , SET , false ) ; rtx addr = arm_find_sub_rtx_with_code ( PATTERN ( consumer ) , SET , false ) ; if ( ! value || ! addr || ! MEM_P ( SET_SRC ( value ) ) ) return 0 ; value = SET_DEST ( value ) ; addr = SET_DEST ( addr ) ; return GET_MODE ( value ) == Pmode && reg_overlap_mentioned_p ( value , addr ) ; } </s>

Return nonzero if the CONSUMER instruction ( a store ) does need a Pmode PRODUCER 's value to calculate the address .


<s> const MCExpr * AVRAsmPrinter :: lowerConstant ( const Constant * CV ) { MCContext & Ctx = OutContext ; if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( CV ) ) { bool IsProgMem = GV -> getAddressSpace ( ) == AVR :: ProgramMemory ; if ( IsProgMem ) { const MCExpr * Expr = MCSymbolRefExpr :: create ( getSymbol ( GV ) , Ctx ) ; return AVRMCExpr :: create ( AVRMCExpr :: VK_AVR_PM , Expr , false , Ctx ) ; } } return AsmPrinter :: lowerConstant ( CV ) ; } </s>

Lower the specified LLVM Constant to an MCExpr .


<s> int ARMTTIImpl :: getArithmeticReductionCost ( unsigned Opcode , VectorType * ValTy , bool IsPairwiseForm , TTI :: TargetCostKind CostKind ) { EVT ValVT = TLI -> getValueType ( DL , ValTy ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( ! ST -> hasMVEIntegerOps ( ) || ! ValVT . isSimple ( ) || ISD != ISD :: ADD ) return BaseT :: getArithmeticReductionCost ( Opcode , ValTy , IsPairwiseForm , CostKind ) ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; static const CostTblEntry CostTblAdd [ ] { { ISD :: ADD , MVT :: v16i8 , 1 } , { ISD :: ADD , MVT :: v8i16 , 1 } , { ISD :: ADD , MVT :: v4i32 , 1 } , } ; if ( const auto * Entry = CostTableLookup ( CostTblAdd , ISD , LT . second ) ) return Entry -> Cost * ST -> getMVEVectorCostFactor ( ) * LT . first ; return BaseT :: getArithmeticReductionCost ( Opcode , ValTy , IsPairwiseForm , CostKind ) ; } </s>

Calculate the cost of vector reduction intrinsics .


<s> bool AMDGPUTargetLowering :: shouldReduceLoadWidth ( SDNode * N , ISD :: LoadExtType ExtTy , EVT NewVT ) const { if ( ! TargetLoweringBase :: shouldReduceLoadWidth ( N , ExtTy , NewVT ) ) return false ; unsigned NewSize = NewVT . getStoreSizeInBits ( ) ; if ( NewSize == 32 ) return true ; EVT OldVT = N -> getValueType ( 0 ) ; unsigned OldSize = OldVT . getStoreSizeInBits ( ) ; MemSDNode * MN = cast < MemSDNode > ( N ) ; unsigned AS = MN -> getAddressSpace ( ) ; if ( OldSize >= 32 && NewSize < 32 && MN -> getAlignment ( ) >= 4 && ( AS == AMDGPUAS :: CONSTANT_ADDRESS || AS == AMDGPUAS :: CONSTANT_ADDRESS_32BIT || ( isa < LoadSDNode > ( N ) && AS == AMDGPUAS :: GLOBAL_ADDRESS && MN -> isInvariant ( ) ) ) && AMDGPUInstrInfo :: isUniformMMO ( MN -> getMemOperand ( ) ) ) return false ; return ( OldSize < 32 ) ; } </s>

Return true if we believe it is correct and profitable to reduce the load node to a smaller type .


<s> std :: pair < unsigned , const TargetRegisterClass * > MBlazeTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , & MBlaze :: GPRRegClass ) ; case 'd' : case 'y' : case 'f' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , & MBlaze :: GPRRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> inline bool isPseudo ( uint64_t TSFlags ) { return ( TSFlags & X86II :: FormMask ) == Pseudo ; } </s>

Return true if this is a pseudo instruction that does n't correspond to a real machine instruction .


<s> static bool avr_mode_dependent_address_p ( const_rtx addr ATTRIBUTE_UNUSED , addr_space_t as ) { return ! ADDR_SPACE_GENERIC_P ( as ) ; } </s>

Implement ` TARGET_MODE_DEPENDENT_ADDRESS_P ' .


<s> bool MBlazeAsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCInstFragment * DF , const MCAsmLayout & Layout ) const { return int64_t ( Value ) != int64_t ( int8_t ( Value ) ) ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> bool n13_consumed_by_e2_dep_p ( rtx_insn * consumer , rtx def_reg ) { rtx use_rtx ; switch ( get_attr_type ( consumer ) ) { case TYPE_ALU : case TYPE_STORE : use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_ALU_SHIFT : use_rtx = extract_shift_reg ( consumer ) ; break ; case TYPE_PBSADA : return pbsada_insn_rt_dep_reg_p ( consumer , def_reg ) ; case TYPE_STORE_MULTIPLE : use_rtx = extract_nth_access_rtx ( consumer , 0 ) ; break ; case TYPE_BRANCH : use_rtx = extract_branch_condition_rtx ( consumer ) ; break ; default : gcc_unreachable ( ) ; } if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; return false ; } </s>

Check the dependency between the producer defining DEF_REG and CONSUMER requiring input operand at E2 .


<s> void MipsSubtarget :: overrideSchedPolicy ( MachineSchedPolicy & Policy , unsigned NumRegionInstrs ) const { } </s>

Override generic scheduling policy within a region .


<s>
bool
PPCRegisterInfo
::
needsFrameBaseReg
(
MachineInstr
*
MI
,
int64_t
Offset
)
const
{
assert
(
Offset
<
0
&&
"Local offset must be negative"
)
;
unsigned
OpC
=
MI
->
getOpcode
(
)
;
if
(
!
ImmToIdxMap
.
count
(
OpC
)
)
return
false
;
if
(
(
OpC
==
PPC
::
ADDI
||
OpC
==
PPC
::
ADDI8
)
&&
MI
->
getOperand
(
2
)
.
getImm
(
)
==
0
)
return
false
;
MachineBasicBlock
&
MBB
=
*
MI
->
getParent
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
PPCFrameLowering
*
PPCFI
=
static_cast
<
const
PPCFrameLowering
*
>
(
MF
.
getTarget
(
)
.
getFrameLowering
(
)
)
;
unsigned
StackEst
=
PPCFI
->
determineFrameLayout
(
MF
,
false
,
true
)
;
if
(
!
StackEst
)
return
false
;
Offset
+=
StackEst
;
return
!
isFrameOffsetLegal
(
MI
,
Offset
)
;
}
</s>

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .

PowerPC
PPC
0
"Local offset must be negative"
PPC::ADDI
PPC::ADDI8
2
0
PPC
PPC
PPC
PPC


<s> bool AArch64FastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Add : case Instruction :: Sub : return selectAddSub ( I ) ; case Instruction :: Mul : return selectMul ( I ) ; case Instruction :: SDiv : return selectSDiv ( I ) ; case Instruction :: SRem : if ( ! selectBinaryOp ( I , ISD :: SREM ) ) return selectRem ( I , ISD :: SREM ) ; return true ; case Instruction :: URem : if ( ! selectBinaryOp ( I , ISD :: UREM ) ) return selectRem ( I , ISD :: UREM ) ; return true ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return selectShift ( I ) ; case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : return selectLogicalOp ( I ) ; case Instruction :: Br : return selectBranch ( I ) ; case Instruction :: IndirectBr : return selectIndirectBr ( I ) ; case Instruction :: BitCast : if ( ! FastISel :: selectBitCast ( I ) ) return selectBitCast ( I ) ; return true ; case Instruction :: FPToSI : if ( ! selectCast ( I , ISD :: FP_TO_SINT ) ) return selectFPToInt ( I , true ) ; return true ; case Instruction :: FPToUI : return selectFPToInt ( I , false ) ; case Instruction :: ZExt : case Instruction :: SExt : return selectIntExt ( I ) ; case Instruction :: Trunc : if ( ! selectCast ( I , ISD :: TRUNCATE ) ) return selectTrunc ( I ) ; return true ; case Instruction :: FPExt : return selectFPExt ( I ) ; case Instruction :: FPTrunc : return selectFPTrunc ( I ) ; case Instruction :: SIToFP : if ( ! selectCast ( I , ISD :: SINT_TO_FP ) ) return selectIntToFP ( I , true ) ; return true ; case Instruction :: UIToFP : return selectIntToFP ( I , false ) ; case Instruction :: Load : return selectLoad ( I ) ; case Instruction :: Store : return selectStore ( I ) ; case Instruction :: FCmp : case Instruction :: ICmp : return selectCmp ( I ) ; case Instruction :: Select : return selectSelect ( I ) ; case Instruction :: Ret : return selectRet ( I ) ; case Instruction :: FRem : return selectFRem ( I ) ; case Instruction :: GetElementPtr : return selectGetElementPtr ( I ) ; case Instruction :: AtomicCmpXchg : return selectAtomicCmpXchg ( cast < AtomicCmpXchgInst > ( I ) ) ; } return selectOperator ( I , I -> getOpcode ( ) ) ; ( void ) & CC_AArch64_DarwinPCS_VarArg ; ( void ) & CC_AArch64_Win64_VarArg ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> static void fixup_mova ( rtx_insn * mova ) { PUT_MODE ( XEXP ( MOVA_LABELREF ( mova ) , 0 ) , QImode ) ; if ( ! flag_pic ) { SET_SRC ( PATTERN ( mova ) ) = MOVA_LABELREF ( mova ) ; INSN_CODE ( mova ) = - 1 ; } else { rtx_insn * worker = mova ; rtx_code_label * lab = gen_label_rtx ( ) ; rtx wpat , wpat0 , wpat1 , wsrc , target , base , diff ; do { worker = NEXT_INSN ( worker ) ; gcc_assert ( worker && ! LABEL_P ( worker ) && ! JUMP_P ( worker ) ) ; } while ( NOTE_P ( worker ) || recog_memoized ( worker ) != CODE_FOR_casesi_worker_1 ) ; wpat = PATTERN ( worker ) ; wpat0 = XVECEXP ( wpat , 0 , 0 ) ; wpat1 = XVECEXP ( wpat , 0 , 1 ) ; wsrc = SET_SRC ( wpat0 ) ; PATTERN ( worker ) = ( gen_casesi_worker_2 ( SET_DEST ( wpat0 ) , XVECEXP ( wsrc , 0 , 1 ) , XEXP ( XVECEXP ( wsrc , 0 , 2 ) , 0 ) , lab , XEXP ( wpat1 , 0 ) ) ) ; INSN_CODE ( worker ) = - 1 ; target = XVECEXP ( SET_SRC ( PATTERN ( mova ) ) , 0 , 0 ) ; base = gen_rtx_LABEL_REF ( Pmode , lab ) ; diff = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 2 , target , base ) , UNSPEC_SYMOFF ) ; SET_SRC ( PATTERN ( mova ) ) = gen_rtx_CONST ( Pmode , diff ) ; INSN_CODE ( mova ) = - 1 ; } } </s>

Fix up a mova from a switch that went out of range .


<s> virtual bool isPredicable ( MachineInstr * MI ) const { return true ; } </s>

Return true if the specified instruction can be predicated .


<s> void Initialize ( MCContext & ctx , const TargetMachine & TM ) override { TargetLoweringObjectFile :: Initialize ( ctx , TM ) ; } </s>

This method must be called before any actual lowering is done .


<s> static bool extract_bundle ( rtx_insn * insn , struct liw_data * pdata ) { bool allow_consts = true ; rtx p ; gcc_assert ( pdata != NULL ) ; if ( insn == NULL ) return false ; p = single_set ( insn ) ; if ( p == NULL_RTX ) return false ; pdata -> slot = get_attr_liw ( insn ) ; if ( pdata -> slot == LIW_BOTH ) return false ; pdata -> op = get_attr_liw_op ( insn ) ; switch ( pdata -> op ) { case LIW_OP_MOV : pdata -> dest = SET_DEST ( p ) ; pdata -> src = SET_SRC ( p ) ; break ; case LIW_OP_CMP : pdata -> dest = XEXP ( SET_SRC ( p ) , 0 ) ; pdata -> src = XEXP ( SET_SRC ( p ) , 1 ) ; break ; case LIW_OP_NONE : return false ; case LIW_OP_AND : case LIW_OP_OR : case LIW_OP_XOR : allow_consts = false ; default : pdata -> dest = SET_DEST ( p ) ; pdata -> src = XEXP ( SET_SRC ( p ) , 1 ) ; break ; } if ( ! REG_P ( pdata -> dest ) ) return false ; if ( REG_P ( pdata -> src ) ) return true ; return allow_consts && satisfies_constraint_O ( pdata -> src ) ; } </s>

Decide if the given insn is a candidate for LIW bundling . If it is then extract the operands and LIW attributes from the insn and use them to fill in the liw_data structure . Return true upon success or false if the insn can not be bundled .


<s> void ARMDAGToDAGISel :: PreprocessISelDAG ( ) { if ( ! Subtarget -> hasV6T2Ops ( ) ) return ; bool isThumb2 = Subtarget -> isThumb ( ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = & * I ++ ; if ( N -> getOpcode ( ) != ISD :: ADD ) continue ; SDValue N0 = N -> getOperand ( 0 ) ; SDValue N1 = N -> getOperand ( 1 ) ; unsigned And_imm = 0 ; if ( ! isOpcWithIntImmediate ( N1 . getNode ( ) , ISD :: AND , And_imm ) ) { if ( isOpcWithIntImmediate ( N0 . getNode ( ) , ISD :: AND , And_imm ) ) std :: swap ( N0 , N1 ) ; } if ( ! And_imm ) continue ; unsigned TZ = countTrailingZeros ( And_imm ) ; if ( TZ != 1 && TZ != 2 ) continue ; And_imm >>= TZ ; if ( And_imm & ( And_imm + 1 ) ) continue ; SDValue Srl = N1 . getOperand ( 0 ) ; unsigned Srl_imm = 0 ; if ( ! isOpcWithIntImmediate ( Srl . getNode ( ) , ISD :: SRL , Srl_imm ) || ( Srl_imm <= 2 ) ) continue ; SDValue CPTmp0 ; SDValue CPTmp1 ; SDValue CPTmp2 ; if ( isThumb2 ) { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) ) continue ; } else { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) || SelectRegShifterOperand ( N0 , CPTmp0 , CPTmp1 , CPTmp2 ) ) continue ; } Srl = CurDAG -> getNode ( ISD :: SRL , SDLoc ( Srl ) , MVT :: i32 , Srl . getOperand ( 0 ) , CurDAG -> getConstant ( Srl_imm + TZ , SDLoc ( Srl ) , MVT :: i32 ) ) ; N1 = CurDAG -> getNode ( ISD :: AND , SDLoc ( N1 ) , MVT :: i32 , Srl , CurDAG -> getConstant ( And_imm , SDLoc ( Srl ) , MVT :: i32 ) ) ; N1 = CurDAG -> getNode ( ISD :: SHL , SDLoc ( N1 ) , MVT :: i32 , N1 , CurDAG -> getConstant ( TZ , SDLoc ( Srl ) , MVT :: i32 ) ) ; CurDAG -> UpdateNodeOperands ( N , N0 , N1 ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> bool SystemZShortenInst :: processBlock ( MachineBasicBlock & MBB ) { bool Changed = false ; LiveRegs . clear ( ) ; LiveRegs . addLiveOuts ( & MBB ) ; for ( auto MBBI = MBB . rbegin ( ) , MBBE = MBB . rend ( ) ; MBBI != MBBE ; ++ MBBI ) { MachineInstr & MI = * MBBI ; switch ( MI . getOpcode ( ) ) { case SystemZ :: IILF : Changed |= shortenIIF ( MI , SystemZ :: LLILL , SystemZ :: LLILH ) ; break ; case SystemZ :: IIHF : Changed |= shortenIIF ( MI , SystemZ :: LLIHL , SystemZ :: LLIHH ) ; break ; case SystemZ :: WFADB : Changed |= shortenOn001AddCC ( MI , SystemZ :: ADBR ) ; break ; case SystemZ :: WFDDB : Changed |= shortenOn001 ( MI , SystemZ :: DDBR ) ; break ; case SystemZ :: WFIDB : Changed |= shortenFPConv ( MI , SystemZ :: FIDBRA ) ; break ; case SystemZ :: WLDEB : Changed |= shortenOn01 ( MI , SystemZ :: LDEBR ) ; break ; case SystemZ :: WLEDB : Changed |= shortenFPConv ( MI , SystemZ :: LEDBRA ) ; break ; case SystemZ :: WFMDB : Changed |= shortenOn001 ( MI , SystemZ :: MDBR ) ; break ; case SystemZ :: WFLCDB : Changed |= shortenOn01 ( MI , SystemZ :: LCDFR ) ; break ; case SystemZ :: WFLNDB : Changed |= shortenOn01 ( MI , SystemZ :: LNDFR ) ; break ; case SystemZ :: WFLPDB : Changed |= shortenOn01 ( MI , SystemZ :: LPDFR ) ; break ; case SystemZ :: WFSQDB : Changed |= shortenOn01 ( MI , SystemZ :: SQDBR ) ; break ; case SystemZ :: WFSDB : Changed |= shortenOn001AddCC ( MI , SystemZ :: SDBR ) ; break ; case SystemZ :: WFCDB : Changed |= shortenOn01 ( MI , SystemZ :: CDBR ) ; break ; case SystemZ :: VL32 : Changed |= shortenOn0 ( MI , SystemZ :: LDE32 ) ; break ; case SystemZ :: VST32 : Changed |= shortenOn0 ( MI , SystemZ :: STE ) ; break ; case SystemZ :: VL64 : Changed |= shortenOn0 ( MI , SystemZ :: LD ) ; break ; case SystemZ :: VST64 : Changed |= shortenOn0 ( MI , SystemZ :: STD ) ; break ; } LiveRegs . stepBackward ( MI ) ; } return Changed ; } </s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .

SystemZ SystemZ SystemZ::IILF SystemZ::LLILL SystemZ::LLILH SystemZ::IIHF SystemZ::LLIHL SystemZ::LLIHH SystemZ::WFADB SystemZ::ADBR SystemZ::WFDDB SystemZ::DDBR SystemZ::WFIDB SystemZ::FIDBRA SystemZ::WLDEB SystemZ::LDEBR SystemZ::WLEDB SystemZ::LEDBRA SystemZ::WFMDB SystemZ::MDBR SystemZ::WFLCDB SystemZ::LCDFR SystemZ::WFLNDB SystemZ::LNDFR SystemZ::WFLPDB SystemZ::LPDFR SystemZ::WFSQDB SystemZ::SQDBR SystemZ::WFSDB SystemZ::SDBR SystemZ::WFCDB SystemZ::CDBR SystemZ::VL32 SystemZ::LDE32 SystemZ::VST32 SystemZ::STE SystemZ::VL64 SystemZ::LD SystemZ::VST64 SystemZ::STD


<s> bool tilegx_emit_setcc ( rtx operands [ ] , machine_mode cmp_mode ) { return tilegx_emit_setcc_internal ( operands [ 0 ] , GET_CODE ( operands [ 1 ] ) , operands [ 2 ] , operands [ 3 ] , cmp_mode ) ; } </s>


<s> static void tilegx_init_builtins ( void ) { size_t i ; for ( i = 0 ; i < ARRAY_SIZE ( tilegx_builtins ) ; i ++ ) { const struct tilegx_builtin_def * p = & tilegx_builtins [ i ] ; tree ftype , ret_type , arg_type_list = void_list_node ; tree decl ; int j ; for ( j = strlen ( p -> type ) - 1 ; j > 0 ; j -- ) { arg_type_list = tree_cons ( NULL_TREE , char_to_type ( p -> type [ j ] ) , arg_type_list ) ; } ret_type = char_to_type ( p -> type [ 0 ] ) ; ftype = build_function_type ( ret_type , arg_type_list ) ; decl = add_builtin_function ( p -> name , ftype , p -> code , BUILT_IN_MD , NULL , NULL ) ; if ( p -> is_const ) TREE_READONLY ( decl ) = 1 ; TREE_NOTHROW ( decl ) = 1 ; if ( tilegx_builtin_info [ p -> code ] . fndecl == NULL ) tilegx_builtin_info [ p -> code ] . fndecl = decl ; } } </s>


<s> bool WebAssemblyPassConfig :: addILPOpts ( ) { return true ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .


<s> static rtx_insn * arm_pic_static_addr ( rtx orig , rtx reg ) { rtx l1 , labelno , offset_rtx ; gcc_assert ( flag_pic ) ; labelno = GEN_INT ( pic_labelno ++ ) ; l1 = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , labelno ) , UNSPEC_PIC_LABEL ) ; l1 = gen_rtx_CONST ( VOIDmode , l1 ) ; offset_rtx = plus_constant ( Pmode , l1 , TARGET_ARM ? 8 : 4 ) ; offset_rtx = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 2 , orig , offset_rtx ) , UNSPEC_SYMBOL_OFFSET ) ; offset_rtx = gen_rtx_CONST ( Pmode , offset_rtx ) ; return emit_insn ( gen_pic_load_addr_unified ( reg , offset_rtx , labelno ) ) ; } </s>

Generate code to load the address of a static var when flag_pic is set .


<s> MachineInstr * PPCInstrInfo :: findLoopInstr ( MachineBasicBlock & PreHeader , SmallPtrSet < MachineBasicBlock * , 8 > & Visited ) const { unsigned LOOPi = ( Subtarget . isPPC64 ( ) ? PPC :: MTCTR8loop : PPC :: MTCTRloop ) ; for ( auto & I : PreHeader . instrs ( ) ) if ( I . getOpcode ( ) == LOOPi ) return & I ; return nullptr ; } </s>

Find the hardware loop instruction used to set-up the specified loop .

PowerPC PPC 8 PPC PPC::MTCTR8loop PPC::MTCTRloop


<s> unsigned getID ( ) const { return ID ; } </s>


<s> void Note ( SMLoc L , const Twine & Msg , ArrayRef < SMRange > Ranges = None ) { return Parser . Note ( L , Msg , Ranges ) ; } </s>

Emit a note at the location L , with the message Msg .


<s> void ARMHazardRecognizer :: EmitInstruction ( SUnit * SU ) { MachineInstr * MI = SU -> getInstr ( ) ; if ( ! MI -> isDebugValue ( ) ) { LastMI = MI ; FpMLxStalls = 0 ; } ScoreboardHazardRecognizer :: EmitInstruction ( SU ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


"rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n"

A C expressions returning the cost of moving data of MODE from a register to or from memory .


<s> Optional < ExtAddrMode > AArch64InstrInfo :: getAddrModeFromMemoryOp ( const MachineInstr & MemI , const TargetRegisterInfo * TRI ) const { const MachineOperand * Base ; int64_t Offset ; bool OffsetIsScalable ; if ( ! getMemOperandWithOffset ( MemI , Base , Offset , OffsetIsScalable , TRI ) ) return None ; if ( ! Base -> isReg ( ) ) return None ; ExtAddrMode AM ; AM . BaseReg = Base -> getReg ( ) ; AM . Displacement = Offset ; AM . ScaledReg = 0 ; AM . Scale = 0 ; return AM ; } </s>

Target dependent implementation to get the values constituting the address MachineInstr that is accessing memory .


<s> std :: pair < unsigned , const TargetRegisterClass * > SparcTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , SP :: IntRegsRegisterClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> bool PPCInstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Cond , Register DstReg , Register TrueReg , Register FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( Cond . size ( ) != 2 ) return false ; if ( Cond [ 1 ] . getReg ( ) == PPC :: CTR || Cond [ 1 ] . getReg ( ) == PPC :: CTR8 ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( ! PPC :: GPRCRegClass . hasSubClassEq ( RC ) && ! PPC :: GPRC_NOR0RegClass . hasSubClassEq ( RC ) && ! PPC :: G8RCRegClass . hasSubClassEq ( RC ) && ! PPC :: G8RC_NOX0RegClass . hasSubClassEq ( RC ) ) return false ; CondCycles = 1 ; TrueCycles = 1 ; FalseCycles = 1 ; return true ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> void MipsAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( MI -> isDebugValue ( ) ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; PrintDebugValueComment ( MI , OS ) ; return ; } MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { MCInst TmpInst0 ; MCInstLowering . Lower ( I ++ , TmpInst0 ) ; OutStreamer . EmitInstruction ( TmpInst0 ) ; } while ( ( I != E ) && I -> isInsideBundle ( ) ) ; } </s>


<s> static int arm_get_set_operands ( rtx producer , rtx consumer , rtx * set_source , rtx * set_destination ) { rtx set_producer = arm_find_sub_rtx_with_code ( PATTERN ( producer ) , SET , false ) ; rtx set_consumer = arm_find_sub_rtx_with_code ( PATTERN ( consumer ) , SET , false ) ; if ( set_producer && set_consumer ) { * set_source = SET_DEST ( set_producer ) ; * set_destination = SET_SRC ( set_consumer ) ; return 1 ; } return 0 ; } </s>

PRODUCER and CONSUMER are two potentially dependant RTX . PRODUCER ( possibly ) contains a SET which will provide a result we can access using the SET_DEST macro . We will place the RTX which would be written by PRODUCER in SET_SOURCE . Similarly , CONSUMER ( possibly ) contains a SET which has an operand we can access using SET_SRC . We place this operand in SET_DESTINATION . Return nonzero if we found the SET RTX we expected .


<s> bool AMDGPUPassConfig :: addPreISel ( ) { const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . getGeneration ( ) > AMDGPUSubtarget :: NORTHERN_ISLANDS ) { addPass ( createAMDGPUStructurizeCFGPass ( ) ) ; addPass ( createSIAnnotateControlFlowPass ( ) ) ; } else { addPass ( createR600TextureIntrinsicsReplacer ( ) ) ; } return false ; } </s>


"********** AArch64 Conditional Branch Tuning  **********\n"

runOnMachineFunction - Emit the function body .


<s> bool HexagonCommonGEP :: runOnFunction ( Function & F ) { for ( Function :: iterator A = F . begin ( ) , Z = F . end ( ) ; A != Z ; ++ A ) for ( BasicBlock :: iterator I = A -> begin ( ) , E = A -> end ( ) ; I != E ; ++ I ) if ( isa < InvokeInst > ( I ) || isa < LandingPadInst > ( I ) ) return false ; Fn = & F ; DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; PDT = & getAnalysis < PostDominatorTreeWrapperPass > ( ) . getPostDomTree ( ) ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; Ctx = & F . getContext ( ) ; Nodes . clear ( ) ; Uses . clear ( ) ; NodeOrder . clear ( ) ; SpecificBumpPtrAllocator < GepNode > Allocator ; Mem = & Allocator ; collect ( ) ; common ( ) ; NodeToValueMap Loc ; computeNodePlacement ( Loc ) ; materialize ( Loc ) ; removeDeadCode ( ) ; verifyFunction ( F ) ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static tree aarch64_add_attribute ( const char * name , tree attrs ) { return tree_cons ( get_identifier ( name ) , NULL_TREE , attrs ) ; } </s>


<s> static void riscv_legitimize_const_move ( machine_mode mode , rtx dest , rtx src ) { rtx base , offset ; if ( splittable_const_int_operand ( src , mode ) ) { riscv_move_integer ( dest , dest , INTVAL ( src ) , mode , FALSE ) ; return ; } if ( riscv_split_symbol ( dest , src , MAX_MACHINE_MODE , & src , FALSE ) ) { riscv_emit_set ( dest , src ) ; return ; } if ( riscv_tls_symbol_p ( src ) ) { riscv_emit_move ( dest , riscv_legitimize_tls_address ( src ) ) ; return ; } split_const ( src , & base , & offset ) ; if ( offset != const0_rtx && ( targetm . cannot_force_const_mem ( mode , src ) || can_create_pseudo_p ( ) ) ) { base = riscv_force_temporary ( dest , base , FALSE ) ; riscv_emit_move ( dest , riscv_add_offset ( NULL , base , INTVAL ( offset ) ) ) ; return ; } src = force_const_mem ( mode , src ) ; riscv_split_symbol ( dest , XEXP ( src , 0 ) , mode , & XEXP ( src , 0 ) , FALSE ) ; riscv_emit_move ( dest , src ) ; } </s>

Subroutine of riscv_legitimize_move . Move constant SRC into register DEST given that SRC satisfies immediate_operand but does n't satisfy move_operand .


<s> static rtx cr16_function_value ( const_tree type , const_tree fn_decl_or_type ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( TYPE_MODE ( type ) , cr16_ret_register ( ) ) ; } </s>

Create an RTX representing the place where a function returns a value of data type VALTYPE .


<s> static void mmix_encode_section_info ( tree decl , rtx rtl , int first ) { if ( ( TREE_CODE ( decl ) == VAR_DECL && ( DECL_EXTERNAL ( decl ) || TREE_PUBLIC ( decl ) ) ) || ( TREE_CODE ( decl ) == FUNCTION_DECL && TREE_PUBLIC ( decl ) ) ) ; else if ( first && DECL_P ( decl ) ) { const char * str = XSTR ( XEXP ( rtl , 0 ) , 0 ) ; int len = strlen ( str ) ; char * newstr = XALLOCAVEC ( char , len + 2 ) ; newstr [ 0 ] = '@' ; strcpy ( newstr + 1 , str ) ; XSTR ( XEXP ( rtl , 0 ) , 0 ) = ggc_alloc_string ( newstr , len + 1 ) ; } if ( TREE_CODE ( decl ) == FUNCTION_DECL || TREE_CONSTANT ( decl ) || ( TREE_CODE ( decl ) == VAR_DECL && TREE_READONLY ( decl ) && ! TREE_SIDE_EFFECTS ( decl ) && ( ! DECL_INITIAL ( decl ) || TREE_CONSTANT ( DECL_INITIAL ( decl ) ) ) ) ) SYMBOL_REF_FLAG ( XEXP ( rtl , 0 ) ) = 1 ; } </s>


"instruction use requires option to be enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> static bool mips_expand_vpc_loongson_even_odd ( struct expand_vec_perm_d * d ) { unsigned i , odd , nelt = d -> nelt ; rtx t0 , t1 , t2 , t3 ; if ( ! ( TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS ) ) return false ; if ( nelt < 4 ) return false ; odd = d -> perm [ 0 ] ; if ( odd > 1 ) return false ; for ( i = 1 ; i < nelt ; ++ i ) if ( d -> perm [ i ] != i * 2 + odd ) return false ; if ( d -> testing_p ) return true ; t0 = gen_reg_rtx ( d -> vmode ) ; t1 = gen_reg_rtx ( d -> vmode ) ; switch ( d -> vmode ) { case E_V4HImode : emit_insn ( gen_loongson_punpckhhw ( t0 , d -> op0 , d -> op1 ) ) ; emit_insn ( gen_loongson_punpcklhw ( t1 , d -> op0 , d -> op1 ) ) ; if ( odd ) emit_insn ( gen_loongson_punpckhhw ( d -> target , t1 , t0 ) ) ; else emit_insn ( gen_loongson_punpcklhw ( d -> target , t1 , t0 ) ) ; break ; case E_V8QImode : t2 = gen_reg_rtx ( d -> vmode ) ; t3 = gen_reg_rtx ( d -> vmode ) ; emit_insn ( gen_loongson_punpckhbh ( t0 , d -> op0 , d -> op1 ) ) ; emit_insn ( gen_loongson_punpcklbh ( t1 , d -> op0 , d -> op1 ) ) ; emit_insn ( gen_loongson_punpckhbh ( t2 , t1 , t0 ) ) ; emit_insn ( gen_loongson_punpcklbh ( t3 , t1 , t0 ) ) ; if ( odd ) emit_insn ( gen_loongson_punpckhbh ( d -> target , t3 , t2 ) ) ; else emit_insn ( gen_loongson_punpcklbh ( d -> target , t3 , t2 ) ) ; break ; default : gcc_unreachable ( ) ; } return true ; } </s>

Recognize patterns for even-odd extraction .


<s> void gcn_goacc_reduction ( gcall * call ) { int level = TREE_INT_CST_LOW ( gimple_call_arg ( call , 3 ) ) ; if ( level == GOMP_DIM_VECTOR ) { default_goacc_reduction ( call ) ; return ; } unsigned code = ( unsigned ) TREE_INT_CST_LOW ( gimple_call_arg ( call , 0 ) ) ; switch ( code ) { case IFN_GOACC_REDUCTION_SETUP : gcn_goacc_reduction_setup ( call ) ; break ; case IFN_GOACC_REDUCTION_INIT : gcn_goacc_reduction_init ( call ) ; break ; case IFN_GOACC_REDUCTION_FINI : gcn_goacc_reduction_fini ( call ) ; break ; case IFN_GOACC_REDUCTION_TEARDOWN : gcn_goacc_reduction_teardown ( call ) ; break ; default : gcc_unreachable ( ) ; } } </s>

Implement TARGET_GOACC_REDUCTION . Expand calls to the GOACC REDUCTION internal function , into a sequence of gimple instructions .


<s> bool runOnModule ( Module & M ) override { UsedList = AMDGPU :: getUsedList ( M ) ; bool Changed = processUsedLDS ( M ) ; for ( Function & F : M . functions ( ) ) { if ( ! AMDGPU :: isKernelCC ( & F ) ) continue ; Changed |= processUsedLDS ( M , & F ) ; } UsedList . clear ( ) ; return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> bool X86TargetLowering :: useStackGuardXorFP ( ) const { return Subtarget . getTargetTriple ( ) . isOSMSVCRT ( ) && ! Subtarget . isTargetMachO ( ) ; } </s>

If this function returns true , stack protection checks should XOR the frame pointer ( or whichever pointer is used to address locals ) into the stack guard value before checking it .