<s> bool PPCLoopPreIncPrep :: runOnFunction ( Function & F ) { LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; auto * DTWP = getAnalysisIfAvailable < DominatorTreeWrapperPass > ( ) ; DT = DTWP ? & DTWP -> getDomTree ( ) : nullptr ; PreserveLCSSA = mustPreserveAnalysisID ( LCSSAID ) ; bool MadeChange = false ; for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L = df_begin ( * I ) , LE = df_end ( * I ) ; L != LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ; return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


";; [Local] Removing membar %d since order"

";; [Local] Removing membar %d since the target"

" of %d is used before the I/O operation\n"

Go through block BB looking for membars to remove . There are two cases where intra-block analysis is enough : - a membar is redundant if it occurs between two consecutive I/O operations and if those operations are guaranteed to complete in order . - a membar for a __builtin_read is redundant if the result is used before the next I/O operation is issued . If the last membar in the block could not be removed , and there are guaranteed to be no I/O operations between that membar and the end of the block , store the membar in * LAST_MEMBAR , otherwise store null . Describe the block 's first I/O operation in * NEXT_IO . Describe an unknown operation if the block does n't do any I/O .


<s> bool TeakRegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { return false ; } </s>

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot .


<s> MCInstrDesc const & TPCMCInstrInfo :: getDesc ( MCInstrInfo const & MCII , MCInst const & MCI ) { return ( MCII . get ( MCI . getOpcode ( ) ) ) ; } </s>

Returns the target instruction descriptor of this MachineInstr .


<s> static rtx mips_get_sync_operand ( rtx * operands , int index , rtx default_value ) { if ( index > 0 ) default_value = operands [ index - 1 ] ; return default_value ; } </s>

OPERANDS are the operands to a sync loop instruction and INDEX is the value of the one of the sync_ * attributes . Return the operand referred to by the attribute , or DEFAULT_VALUE if the insn does n't have the associated attribute .


<s> bool ShouldShrinkFPConstant ( EVT VT ) const override { return ! X86ScalarSSEf64 || VT == MVT :: f80 ; } </s>

If true , then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime .


<s> int nds32_fp_as_gp_check_available ( void ) { return 0 ; } </s>

Function to determine whether it is worth to do fp_as_gp optimization . Return 0 : It is NOT worth to do fp_as_gp optimization . Return 1 : It is APPROXIMATELY worth to do fp_as_gp optimization . Note that if it is worth to do fp_as_gp optimization , we MUST set FP_REGNUM ever live in this function .


<s> bool PTXInstrInfo :: SubsumesPredicate ( const SmallVectorImpl < MachineOperand > & Pred1 , const SmallVectorImpl < MachineOperand > & Pred2 ) const { const MachineOperand & PredReg1 = Pred1 [ 0 ] ; const MachineOperand & PredReg2 = Pred2 [ 0 ] ; if ( PredReg1 . getReg ( ) != PredReg2 . getReg ( ) ) return false ; const MachineOperand & PredOp1 = Pred1 [ 1 ] ; const MachineOperand & PredOp2 = Pred2 [ 1 ] ; if ( PredOp1 . getImm ( ) != PredOp2 . getImm ( ) ) return false ; return true ; } </s>

Returns true if the first specified predicate subsumes the second , e.g .


<s> bool gpr_or_gpr_p ( rtx op0 , rtx op1 ) { return ( ( REG_P ( op0 ) && INT_REGNO_P ( REGNO ( op0 ) ) ) || ( REG_P ( op1 ) && INT_REGNO_P ( REGNO ( op1 ) ) ) ) ; } </s>

Return true if either operand is a general purpose register .


<s> void X86PassConfig :: addPreSched2 ( ) { addPass ( createX86ExpandPseudoPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> bool Thumb2InstrInfo :: isLegalToSplitMBBAt ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) const { while ( MBBI -> isDebugInstr ( ) ) { ++ MBBI ; if ( MBBI == MBB . end ( ) ) return false ; } unsigned PredReg = 0 ; return getITInstrPredicate ( * MBBI , PredReg ) == ARMCC :: AL ; } </s>

Return true if it 's legal to split the given basic block at the specified instruction ( i.e .


<s> bool AArch64InstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF , bool OutlineFromLinkOnceODRs ) const { const Function * F = MF . getFunction ( ) ; if ( ! F -> hasFnAttribute ( Attribute :: NoRedZone ) ) return false ; if ( F -> hasAddressTaken ( ) ) return false ; if ( ! OutlineFromLinkOnceODRs && F -> hasLinkOnceODRLinkage ( ) ) return false ; return true ; } </s>

Return true if the function can safely be outlined from .


<s>
bool
PPCLinuxAsmPrinter
::
doFinalization
(
Module
&
M
)
{
const
TargetData
*
TD
=
TM
.
getTargetData
(
)
;
bool
isPPC64
=
TD
->
getPointerSizeInBits
(
)
==
64
;
if
(
isPPC64
&&
!
TOC
.
empty
(
)
)
{
const
MCSectionELF
*
Section
=
OutStreamer
.
getContext
(
)
.
getELFSection
(
".toc"
,
ELF
::
SHT_PROGBITS
,
ELF
::
SHF_WRITE
|
ELF
::
SHF_ALLOC
,
SectionKind
::
getReadOnly
(
)
)
;
OutStreamer
.
SwitchSection
(
Section
)
;
for
(
DenseMap
<
MCSymbol
*
,
MCSymbol
*
>
::
iterator
I
=
TOC
.
begin
(
)
,
E
=
TOC
.
end
(
)
;
I
!=
E
;
++
I
)
{
OutStreamer
.
EmitLabel
(
I
->
second
)
;
OutStreamer
.
EmitRawText
(
"\t.tc "
+
Twine
(
I
->
first
->
getName
(
)
)
+
"[TC],"
+
I
->
first
->
getName
(
)
)
;
}
}
return
AsmPrinter
::
doFinalization
(
M
)
;
}
</s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .

PowerPC
PPC
PPC
64
PPC
".toc"
"\t.tc "
"[TC],"


<s> static unsigned long arm_isr_value ( tree argument ) { const isr_attribute_arg * ptr ; const char * arg ; if ( ! arm_arch_notm ) return ARM_FT_NORMAL | ARM_FT_STACKALIGN ; if ( argument == NULL_TREE ) return ARM_FT_ISR ; if ( TREE_VALUE ( argument ) == NULL_TREE || TREE_CODE ( TREE_VALUE ( argument ) ) != STRING_CST ) return ARM_FT_UNKNOWN ; arg = TREE_STRING_POINTER ( TREE_VALUE ( argument ) ) ; for ( ptr = isr_attribute_args ; ptr -> arg != NULL ; ptr ++ ) if ( streq ( arg , ptr -> arg ) ) return ptr -> return_value ; return ARM_FT_UNKNOWN ; } </s>

Returns the ( interrupt ) function type of the current function , or ARM_FT_UNKNOWN if the type can not be determined .


<s> SDValue SITargetLowering :: CreateLiveInRegister ( SelectionDAG & DAG , const TargetRegisterClass * RC , unsigned Reg , EVT VT ) const { SDValue VReg = AMDGPUTargetLowering :: CreateLiveInRegister ( DAG , RC , Reg , VT ) ; return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , SDLoc ( DAG . getEntryNode ( ) ) , cast < RegisterSDNode > ( VReg ) -> getReg ( ) , VT ) ; } </s>

Helper function that adds Reg to the LiveIn list of the DAG 's MachineFunction .


<s> static bool arc_can_use_doloop_p ( const widest_int & , const widest_int & iterations_max , unsigned int loop_depth , bool entered_at_top ) { if ( loop_depth > 1 || ! entered_at_top ) return false ; if ( arc_lpcwidth != 32 && ( wi :: gtu_p ( iterations_max , ( ( 1 << arc_lpcwidth ) - 1 ) ) || wi :: eq_p ( iterations_max , 0 ) ) ) return false ; return true ; } </s>


<s> const char * AArch64TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case AArch64ISD :: BR_CC : return "AArch64ISD::BR_CC" ; case AArch64ISD :: Call : return "AArch64ISD::Call" ; case AArch64ISD :: FPMOV : return "AArch64ISD::FPMOV" ; case AArch64ISD :: GOTLoad : return "AArch64ISD::GOTLoad" ; case AArch64ISD :: BFI : return "AArch64ISD::BFI" ; case AArch64ISD :: EXTR : return "AArch64ISD::EXTR" ; case AArch64ISD :: Ret : return "AArch64ISD::Ret" ; case AArch64ISD :: SBFX : return "AArch64ISD::SBFX" ; case AArch64ISD :: SELECT_CC : return "AArch64ISD::SELECT_CC" ; case AArch64ISD :: SETCC : return "AArch64ISD::SETCC" ; case AArch64ISD :: TC_RETURN : return "AArch64ISD::TC_RETURN" ; case AArch64ISD :: THREAD_POINTER : return "AArch64ISD::THREAD_POINTER" ; case AArch64ISD :: TLSDESCCALL : return "AArch64ISD::TLSDESCCALL" ; case AArch64ISD :: WrapperLarge : return "AArch64ISD::WrapperLarge" ; case AArch64ISD :: WrapperSmall : return "AArch64ISD::WrapperSmall" ; case AArch64ISD :: NEON_BSL : return "AArch64ISD::NEON_BSL" ; case AArch64ISD :: NEON_MOVIMM : return "AArch64ISD::NEON_MOVIMM" ; case AArch64ISD :: NEON_MVNIMM : return "AArch64ISD::NEON_MVNIMM" ; case AArch64ISD :: NEON_FMOVIMM : return "AArch64ISD::NEON_FMOVIMM" ; case AArch64ISD :: NEON_CMP : return "AArch64ISD::NEON_CMP" ; case AArch64ISD :: NEON_CMPZ : return "AArch64ISD::NEON_CMPZ" ; case AArch64ISD :: NEON_TST : return "AArch64ISD::NEON_TST" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> bool ARMBaseInstrInfo :: shouldSink ( const MachineInstr & MI ) const { if ( isPredicated ( MI ) ) return true ; MachineBasicBlock :: const_iterator Next = & MI ; ++ Next ; Register SrcReg , SrcReg2 ; int CmpMask , CmpValue ; bool IsThumb1 ; if ( Next != MI . getParent ( ) -> end ( ) && analyzeCompare ( * Next , SrcReg , SrcReg2 , CmpMask , CmpValue ) && isRedundantFlagInstr ( & * Next , SrcReg , SrcReg2 , CmpValue , & MI , IsThumb1 ) ) return false ; return true ; } </s>

Return true if the instruction should be sunk by MachineSink .


<s> virtual const X86InstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> static bool in_same_chain ( rtx_insn * insn , rtx_insn * cand , unsigned regno ) { struct du_chain * chain = NULL ; du_head_p head = NULL ; int i ; operand_rr_info * op_info = insn_rr [ INSN_UID ( insn ) ] . op_info ; for ( i = 0 ; i < op_info -> n_chains ; i ++ ) { if ( op_info -> heads [ i ] -> regno != regno ) continue ; head = op_info -> heads [ i ] ; if ( ! head -> first ) head = regrename_chain_from_id ( head -> id ) ; bool found_insn = false , found_cand = false ; for ( chain = head -> first ; chain ; chain = chain -> next_use ) { rtx * loc = & SET_DEST ( PATTERN ( chain -> insn ) ) ; if ( chain -> loc != loc ) continue ; if ( chain -> insn == insn ) found_insn = true ; if ( chain -> insn == cand ) found_cand = true ; if ( found_insn && found_cand ) return true ; } } return false ; } </s>

Return whether INSN and CAND are in the same def/use chain .


<s> void HSAILMachineFunctionInfo :: addMetadata ( std :: string md , bool kernelOnly ) { if ( kernelOnly ) { mMetadataKernel . push_back ( md ) ; } else { mMetadataFunc . insert ( md ) ; } } </s>

Similar to the previous function but it adds the metadata to a vector of instructions .


<s> static void alpha_output_mi_thunk_osf ( FILE * file , tree thunk_fndecl ATTRIBUTE_UNUSED , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { HOST_WIDE_INT hi , lo ; rtx this_rtx , funexp ; rtx_insn * insn ; emit_insn ( gen_prologue_ldgp ( ) ) ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , 17 ) ; else this_rtx = gen_rtx_REG ( Pmode , 16 ) ; lo = ( ( delta & 0xffff ) ^ 0x8000 ) - 0x8000 ; hi = ( ( ( delta - lo ) & 0xffffffff ) ^ 0x80000000 ) - 0x80000000 ; if ( hi + lo == delta ) { if ( hi ) emit_insn ( gen_adddi3 ( this_rtx , this_rtx , GEN_INT ( hi ) ) ) ; if ( lo ) emit_insn ( gen_adddi3 ( this_rtx , this_rtx , GEN_INT ( lo ) ) ) ; } else { rtx tmp = alpha_emit_set_long_const ( gen_rtx_REG ( Pmode , 0 ) , delta ) ; emit_insn ( gen_adddi3 ( this_rtx , this_rtx , tmp ) ) ; } if ( vcall_offset ) { rtx tmp , tmp2 ; tmp = gen_rtx_REG ( Pmode , 0 ) ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , this_rtx ) ) ; lo = ( ( vcall_offset & 0xffff ) ^ 0x8000 ) - 0x8000 ; hi = ( ( ( vcall_offset - lo ) & 0xffffffff ) ^ 0x80000000 ) - 0x80000000 ; if ( hi + lo == vcall_offset ) { if ( hi ) emit_insn ( gen_adddi3 ( tmp , tmp , GEN_INT ( hi ) ) ) ; } else { tmp2 = alpha_emit_set_long_const ( gen_rtx_REG ( Pmode , 1 ) , vcall_offset ) ; emit_insn ( gen_adddi3 ( tmp , tmp , tmp2 ) ) ; lo = 0 ; } if ( lo ) tmp2 = gen_rtx_PLUS ( Pmode , tmp , GEN_INT ( lo ) ) ; else tmp2 = tmp ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , tmp2 ) ) ; emit_insn ( gen_adddi3 ( this_rtx , this_rtx , tmp ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = 1 ; } funexp = XEXP ( DECL_RTL ( function ) , 0 ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx ) ) ; SIBLING_CALL_P ( insn ) = 1 ; insn = get_insns ( ) ; shorten_branches ( insn ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; } </s>

Emit a tail call to FUNCTION after adjusting THIS by DELTA . In order to avoid the hordes of differences between generated code with and without TARGET_EXPLICIT_RELOCS , and to avoid duplicating lots of code loading up large constants , generate rtl and emit it instead of going straight to text . Not sure why this idea has n't been explored before ...


Return true if accesses IO1 and IO2 refer to the same doubleword .


<s> void altivec_expand_stvex_be ( rtx op0 , rtx op1 , machine_mode mode , unsigned unspec ) { machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx tmp = gen_reg_rtx ( mode ) ; rtx stvx = gen_rtx_UNSPEC ( inner_mode , gen_rtvec ( 1 , tmp ) , unspec ) ; rtx sel = swap_selector_for_mode ( mode ) ; rtx vperm ; gcc_assert ( REG_P ( op1 ) ) ; vperm = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , op1 , op1 , sel ) , UNSPEC_VPERM ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , vperm ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , op0 , stvx ) ) ; } </s>

Generate code for a `` stve * x '' built-in for a little endian target with -maltivec=be specified . Issue the store preceded by an element-reversing permute .


<s> void AVRFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> static const char * rs6000_xcoff_visibility ( tree decl ) { static const char * const visibility_types [ ] = { "" , ",protected" , ",hidden" , ",internal" } ; enum symbol_visibility vis = DECL_VISIBILITY ( decl ) ; return visibility_types [ vis ] ; } </s>

Helper function to calculate visibility of a DECL and return the value as a const string .

rs6000 "" ",protected" ",hidden" ",internal"


<s> tree gimple_folder :: fold_contiguous_base ( gimple_seq & stmts , tree vectype ) { tree base = gimple_call_arg ( call , 1 ) ; if ( mode_suffix_id == MODE_vnum ) { tree offset = gimple_call_arg ( call , 2 ) ; offset = gimple_convert ( & stmts , sizetype , offset ) ; offset = gimple_build ( & stmts , MULT_EXPR , sizetype , offset , TYPE_SIZE_UNIT ( vectype ) ) ; base = gimple_build ( & stmts , POINTER_PLUS_EXPR , TREE_TYPE ( base ) , base , offset ) ; } return base ; } </s>

Return a pointer to the address in a contiguous load or store , given that each memory vector has type VECTYPE . Add any new statements to STMTS .


<s> int xstormy16_below100_symbol ( rtx x , enum machine_mode mode ATTRIBUTE_UNUSED ) { if ( GET_CODE ( x ) == CONST ) x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == SYMBOL_REF ) return ( SYMBOL_REF_FLAGS ( x ) & SYMBOL_FLAG_XSTORMY16_BELOW100 ) != 0 ; if ( GET_CODE ( x ) == CONST_INT ) { HOST_WIDE_INT i = INTVAL ( x ) ; if ( ( i >= 0x0000 && i <= 0x00ff ) || ( i >= 0x7f00 && i <= 0x7fff ) ) return 1 ; } return 0 ; } </s>

Predicate for symbols and addresses that reflect special 8-bit addressing .


<s>
void
StackFixup
::
print
(
raw_ostream
&
OS
)
const
{
llvm
::
for_each
(
Changes
,
[
&
]
(
const
std
::
pair
<
Change
,
std
::
string
>
&
v
)
{
printElem
(
OS
,
v
.
first
)
;
OS
<<
"; "
<<
v
.
second
<<
"\n"
;
}
)
;
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> static rtx ix86_expand_int_compare ( enum rtx_code code , rtx op0 , rtx op1 ) { machine_mode cmpmode ; rtx tmp , flags ; if ( ( code == GTU || code == LEU ) && nonimmediate_operand ( op1 , VOIDmode ) ) { std :: swap ( op0 , op1 ) ; code = swap_condition ( code ) ; } cmpmode = SELECT_CC_MODE ( code , op0 , op1 ) ; flags = gen_rtx_REG ( cmpmode , FLAGS_REG ) ; tmp = gen_rtx_COMPARE ( cmpmode , op0 , op1 ) ; emit_insn ( gen_rtx_SET ( flags , tmp ) ) ; return gen_rtx_fmt_ee ( code , VOIDmode , flags , const0_rtx ) ; } </s>

Generate insn patterns to do an integer compare of OPERANDS .


<s> bool XCoreTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , getTargetMachine ( ) , RVLocs , Context ) ; if ( ! CCInfo . CheckReturn ( Outs , RetCC_XCore ) ) return false ; if ( CCInfo . getNextStackOffset ( ) != 0 && isVarArg ) return false ; return true ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> void HexagonDAGToDAGISel :: Select ( SDNode * N ) { if ( N -> isMachineOpcode ( ) ) return N -> setNodeId ( - 1 ) ; switch ( N -> getOpcode ( ) ) { case ISD :: Constant : return SelectConstant ( N ) ; case ISD :: ConstantFP : return SelectConstantFP ( N ) ; case ISD :: FrameIndex : return SelectFrameIndex ( N ) ; case ISD :: BITCAST : return SelectBitcast ( N ) ; case ISD :: SHL : return SelectSHL ( N ) ; case ISD :: LOAD : return SelectLoad ( N ) ; case ISD :: STORE : return SelectStore ( N ) ; case ISD :: INTRINSIC_W_CHAIN : return SelectIntrinsicWChain ( N ) ; case ISD :: INTRINSIC_WO_CHAIN : return SelectIntrinsicWOChain ( N ) ; case HexagonISD :: TYPECAST : return SelectTypecast ( N ) ; case HexagonISD :: P2D : return SelectP2D ( N ) ; case HexagonISD :: D2P : return SelectD2P ( N ) ; case HexagonISD :: Q2V : return SelectQ2V ( N ) ; case HexagonISD :: V2Q : return SelectV2Q ( N ) ; } if ( HST -> useHVXOps ( ) ) { switch ( N -> getOpcode ( ) ) { case ISD :: VECTOR_SHUFFLE : return SelectHvxShuffle ( N ) ; case HexagonISD :: VROR : return SelectHvxRor ( N ) ; } } SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> size_type count ( ) const { return V . count ( ) ; } </s>

Return 1 if the specified key is in the map , 0 otherwise .


<s> static void m68k_output_dwarf_dtprel ( FILE * file , int size , rtx x ) { gcc_assert ( size == 4 ) ; fputs ( "\t.long\t" , file ) ; output_addr_const ( file , x ) ; fputs ( "@TLSLDO+0x8000" , file ) ; } </s>


<s> static bool abi_v4_pass_in_fpr ( machine_mode mode , bool named ) { if ( ! TARGET_HARD_FLOAT ) return false ; if ( mode == DFmode ) return true ; if ( mode == SFmode && named ) return true ; if ( is_complex_IBM_long_double ( mode ) ) return false ; if ( FLOAT128_2REG_P ( mode ) ) return true ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) return true ; return false ; } </s>

Whether ABI_V4 passes MODE args to a function in floating point registers .


<s> rtx aarch64_replace_reg_mode ( rtx x , machine_mode mode ) { if ( GET_MODE ( x ) == mode ) return x ; x = shallow_copy_rtx ( x ) ; set_mode_and_regno ( x , mode , REGNO ( x ) ) ; return x ; } </s>

Return a copy of X with mode MODE , without changing its other attributes . Unlike gen_lowpart , this does n't care whether the mode change is valid .


<s> bool SPUPassConfig :: addInstSelector ( ) { PM . add ( createSPUISelDag ( getSPUTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s>
void
PTXInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DstReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
for
(
int
i
=
0
,
e
=
sizeof
(
map
)
/
sizeof
(
map
[
0
]
)
;
i
!=
e
;
++
i
)
{
if
(
map
[
i
]
.
cls
->
contains
(
DstReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
map
[
i
]
.
opcode
)
,
DstReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
return
;
}
}
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
</s>


<s> bool XCoreRegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { return false ; } </s>

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot .


<s>
bool
MSP430AsmParser
::
MatchAndEmitInstruction
(
SMLoc
Loc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MatchingInlineAsm
)
;
switch
(
MatchResult
)
{
case
Match_Success
:
Inst
.
setLoc
(
Loc
)
;
Out
.
emitInstruction
(
Inst
,
STI
)
;
return
false
;
case
Match_MnemonicFail
:
return
Error
(
Loc
,
"invalid instruction mnemonic"
)
;
case
Match_InvalidOperand
:
{
SMLoc
ErrorLoc
=
Loc
;
if
(
ErrorInfo
!=
~
0U
)
{
if
(
ErrorInfo
>=
Operands
.
size
(
)
)
return
Error
(
ErrorLoc
,
"too few operands for instruction"
)
;
ErrorLoc
=
(
(
MSP430Operand
&
)
*
Operands
[
ErrorInfo
]
)
.
getStartLoc
(
)
;
if
(
ErrorLoc
==
SMLoc
(
)
)
ErrorLoc
=
Loc
;
}
return
Error
(
ErrorLoc
,
"invalid operand for instruction"
)
;
}
default
:
return
true
;
}
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> static void aarch64_expand_vec_series ( rtx dest , rtx base , rtx step ) { machine_mode mode = GET_MODE ( dest ) ; scalar_mode inner = GET_MODE_INNER ( mode ) ; if ( ! aarch64_sve_index_immediate_p ( base ) ) base = force_reg ( inner , base ) ; if ( ! aarch64_sve_index_immediate_p ( step ) ) step = force_reg ( inner , step ) ; emit_set_insn ( dest , gen_rtx_VEC_SERIES ( mode , base , step ) ) ; } </s>


Initialize fpsr fpcr getters and setters .


<s> SDValue XCoreSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { unsigned SizeBitWidth = Size . getValueType ( ) . getSizeInBits ( ) ; if ( ! AlwaysInline && ( Align & 3 ) == 0 && DAG . MaskedValueIsZero ( Size , APInt ( SizeBitWidth , 3 ) ) ) { const TargetLowering & TLI = * DAG . getSubtarget ( ) . getTargetLowering ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; Entry . Node = Src ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMCPY ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( "__memcpy_4" , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) , std :: move ( Args ) , 0 ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .


<s> void ARCExpandPseudos :: expandCTTZ ( MachineFunction & MF , MachineBasicBlock :: iterator MII ) { MachineInstr & MI = * MII ; const MachineOperand & Dest = MI . getOperand ( 0 ) ; const MachineOperand & Src = MI . getOperand ( 1 ) ; Register R = MF . getRegInfo ( ) . createVirtualRegister ( & ARC :: GPR32RegClass ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , TII -> get ( ARC :: FFS_f_rr ) , R ) . add ( Src ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , TII -> get ( ARC :: MOV_cc_ru6 ) ) . add ( Dest ) . addImm ( 32 ) . addImm ( ARCCC :: EQ ) . addReg ( R ) ; MI . eraseFromParent ( ) ; } </s>


<s> static bool sp_valid_at ( HOST_WIDE_INT cfa_offset ) { const struct machine_frame_state & fs = cfun -> machine -> fs ; if ( fs . sp_realigned && cfa_offset <= fs . sp_realigned_offset ) { gcc_assert ( cfa_offset <= fs . sp_realigned_fp_last ) ; return false ; } return fs . sp_valid ; } </s>

Determine if the stack pointer is valid for accessing the CFA_OFFSET in the frame save area . The register is saved at CFA - CFA_OFFSET .


<s> static bool arc_rtx_costs ( rtx x , int code , int outer_code ATTRIBUTE_UNUSED , int * total ) { switch ( code ) { case CONST_INT : if ( SMALL_INT ( INTVAL ( x ) ) ) { * total = 0 ; return true ; } case CONST : case LABEL_REF : case SYMBOL_REF : * total = COSTS_N_INSNS ( 1 ) ; return true ; case CONST_DOUBLE : { rtx high , low ; split_double ( x , & high , & low ) ; * total = COSTS_N_INSNS ( ! SMALL_INT ( INTVAL ( high ) ) + ! SMALL_INT ( INTVAL ( low ) ) ) ; return true ; } case ASHIFT : case ASHIFTRT : case LSHIFTRT : if ( TARGET_SHIFTER ) * total = COSTS_N_INSNS ( 1 ) ; else if ( GET_CODE ( XEXP ( x , 1 ) ) != CONST_INT ) * total = COSTS_N_INSNS ( 16 ) ; else * total = COSTS_N_INSNS ( INTVAL ( XEXP ( ( x ) , 1 ) ) ) ; return false ; default : return false ; } } </s>

Compute a ( partial ) cost for rtx X . Return true if the complete cost has been computed , and false if subexpressions should be scanned . In either case , * TOTAL contains the cost result .


<s> bool aarch_mm_needs_release ( rtx const_int ) { enum memmodel model = memmodel_from_int ( INTVAL ( const_int ) ) ; return ! ( is_mm_relaxed ( model ) || is_mm_consume ( model ) || is_mm_acquire ( model ) ) ; } </s>

Return non-zero if the RTX representing a memory model is a memory model that needs release semantics .


<s> virtual MachineInstr * foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const { return 0 ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < AMDGPUArgumentUsageInfo > ( ) ; AU . addRequired < LegacyDivergenceAnalysis > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; SelectionDAGISel :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static void alpha_emit_xfloating_libcall ( rtx func , rtx target , rtx operands [ ] , int noperands , rtx equiv ) { rtx usage = NULL_RTX , tmp , reg ; int regno = 16 , i ; start_sequence ( ) ; for ( i = 0 ; i < noperands ; ++ i ) { switch ( GET_MODE ( operands [ i ] ) ) { case TFmode : reg = gen_rtx_REG ( TFmode , regno ) ; regno += 2 ; break ; case DFmode : reg = gen_rtx_REG ( DFmode , regno + 32 ) ; regno += 1 ; break ; case VOIDmode : gcc_assert ( GET_CODE ( operands [ i ] ) == CONST_INT ) ; case DImode : reg = gen_rtx_REG ( DImode , regno ) ; regno += 1 ; break ; default : gcc_unreachable ( ) ; } emit_move_insn ( reg , operands [ i ] ) ; usage = alloc_EXPR_LIST ( 0 , gen_rtx_USE ( VOIDmode , reg ) , usage ) ; } switch ( GET_MODE ( target ) ) { case TFmode : reg = gen_rtx_REG ( TFmode , 16 ) ; break ; case DFmode : reg = gen_rtx_REG ( DFmode , 32 ) ; break ; case DImode : reg = gen_rtx_REG ( DImode , 0 ) ; break ; default : gcc_unreachable ( ) ; } tmp = gen_rtx_MEM ( QImode , func ) ; tmp = emit_call_insn ( GEN_CALL_VALUE ( reg , tmp , const0_rtx , const0_rtx , const0_rtx ) ) ; CALL_INSN_FUNCTION_USAGE ( tmp ) = usage ; CONST_OR_PURE_CALL_P ( tmp ) = 1 ; tmp = get_insns ( ) ; end_sequence ( ) ; emit_libcall_block ( tmp , target , reg , equiv ) ; } </s>

Emit an X_floating library function call . Note that these functions do not follow normal calling conventions : TFmode arguments are passed in two integer registers ( as opposed to indirect ) ; TFmode return values appear in R16+R17 . FUNC is the function name to call . TARGET is where the output belongs . OPERANDS are the inputs . NOPERANDS is the count of inputs . EQUIV is the expression equivalent for the function .


<s>
bool
MipsAsmParser
::
ParseDirective
(
AsmToken
DirectiveID
)
{
StringRef
IDVal
=
DirectiveID
.
getString
(
)
;
if
(
IDVal
==
".dword"
)
{
parseDataDirective
(
8
,
DirectiveID
.
getLoc
(
)
)
;
return
false
;
}
if
(
IDVal
==
".ent"
)
{
Parser
.
Lex
(
)
;
return
false
;
}
if
(
IDVal
==
".end"
)
{
Parser
.
Lex
(
)
;
return
false
;
}
if
(
IDVal
==
".frame"
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
false
;
}
if
(
IDVal
==
".set"
)
{
return
parseDirectiveSet
(
)
;
}
if
(
IDVal
==
".fmask"
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
false
;
}
if
(
IDVal
==
".mask"
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
false
;
}
if
(
IDVal
==
".nan"
)
return
parseDirectiveNaN
(
)
;
if
(
IDVal
==
".gpword"
)
{
parseDirectiveGpWord
(
)
;
return
false
;
}
if
(
IDVal
==
".gpdword"
)
{
parseDirectiveGpDWord
(
)
;
return
false
;
}
if
(
IDVal
==
".word"
)
{
parseDataDirective
(
4
,
DirectiveID
.
getLoc
(
)
)
;
return
false
;
}
if
(
IDVal
==
".option"
)
return
parseDirectiveOption
(
)
;
if
(
IDVal
==
".abicalls"
)
{
getTargetStreamer
(
)
.
emitDirectiveAbiCalls
(
)
;
if
(
Parser
.
getTok
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
Error
(
Parser
.
getTok
(
)
.
getLoc
(
)
,
"unexpected token in directive"
)
;
Parser
.
eatToEndOfStatement
(
)
;
}
return
false
;
}
if
(
IDVal
==
".cpsetup"
)
return
parseDirectiveCPSetup
(
)
;
return
true
;
}
</s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


EXP is a pointer argument to a vector scatter store intrinsics . Consider the following example : VSTRW < v > . < dt > Qd , [ Qm { , # +/- < imm > } ] ! When < Qm > used as the base register for the target address , this function is used to derive and return an expression for the accessed memory . The intrinsic function operates on a block of registers that has mode REG_MODE . This block contains vectors of type TYPE_MODE . The function references the memory at EXP of type TYPE and in mode MEM_MODE . This mode may be BLKmode if no more suitable mode is available .


<s> static int microblaze_address_insns ( rtx x , machine_mode mode ) { struct microblaze_address_info addr ; if ( microblaze_classify_address ( & addr , x , mode , false ) ) { switch ( addr . type ) { case ADDRESS_REG : if ( SMALL_INT ( addr . offset ) ) return 1 ; else return 2 ; case ADDRESS_CONST_INT : if ( SMALL_INT ( x ) ) return 1 ; else return 2 ; case ADDRESS_REG_INDEX : return 1 ; case ADDRESS_SYMBOLIC : case ADDRESS_GOTOFF : return 2 ; case ADDRESS_TLS : switch ( addr . tls_type ) { case TLS_GD : return 2 ; case TLS_LDM : return 2 ; case TLS_DTPREL : return 1 ; default : abort ( ) ; } default : break ; } } return 0 ; } </s>

Return the number of instructions needed to load or store a value of mode MODE at X . Return 0 if X is n't valid for MODE .


<s> static unsigned getLinkageSize ( bool LP64 , bool isMacho ) { if ( isMacho ) return 6 * ( LP64 ? 8 : 4 ) ; return 8 ; } </s>

getLinkageSize - Return the size of the PowerPC ABI linkage area .


<s> void arc_print_operand_address ( FILE * file , rtx addr ) { register rtx base , index = 0 ; switch ( GET_CODE ( addr ) ) { case REG : fputs ( reg_names [ REGNO ( addr ) ] , file ) ; break ; case SYMBOL_REF : output_addr_const ( file , addr ) ; if ( SYMBOL_REF_SMALL_P ( addr ) ) fprintf ( file , "@sda" ) ; break ; case PLUS : if ( GET_CODE ( XEXP ( addr , 0 ) ) == MULT ) index = XEXP ( XEXP ( addr , 0 ) , 0 ) , base = XEXP ( addr , 1 ) ; else if ( CONST_INT_P ( XEXP ( addr , 0 ) ) ) index = XEXP ( addr , 0 ) , base = XEXP ( addr , 1 ) ; else base = XEXP ( addr , 0 ) , index = XEXP ( addr , 1 ) ; gcc_assert ( OBJECT_P ( base ) ) ; arc_print_operand_address ( file , base ) ; if ( CONSTANT_P ( base ) && CONST_INT_P ( index ) ) fputc ( '+' , file ) ; else fputc ( ',' , file ) ; gcc_assert ( OBJECT_P ( index ) ) ; arc_print_operand_address ( file , index ) ; break ; case CONST : { rtx c = XEXP ( addr , 0 ) ; gcc_assert ( GET_CODE ( XEXP ( c , 0 ) ) == SYMBOL_REF ) ; gcc_assert ( GET_CODE ( XEXP ( c , 1 ) ) == CONST_INT ) ; output_address ( VOIDmode , XEXP ( addr , 0 ) ) ; break ; } case PRE_INC : case PRE_DEC : gcc_unreachable ( ) ; break ; default : if ( flag_pic ) arc_output_pic_addr_const ( file , addr , 0 ) ; else output_addr_const ( file , addr ) ; break ; } } </s>

Print a memory address as an operand to reference that memory location .


<s> bool ARMBaseInstrInfo :: analyzeCompare ( const MachineInstr & MI , Register & SrcReg , Register & SrcReg2 , int64_t & CmpMask , int64_t & CmpValue ) const { switch ( MI . getOpcode ( ) ) { default : break ; case ARM :: CMPri : case ARM :: t2CMPri : case ARM :: tCMPi8 : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 1 ) . getImm ( ) ; return true ; case ARM :: CMPrr : case ARM :: t2CMPrr : case ARM :: tCMPr : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 1 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case ARM :: TSTri : case ARM :: t2TSTri : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = MI . getOperand ( 1 ) . getImm ( ) ; CmpValue = 0 ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> bool SIFoldOperands :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; MRI = & MF . getRegInfo ( ) ; TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ; MachineBasicBlock :: iterator I , Next ; for ( I = MBB . begin ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; if ( ! isSafeToFold ( MI ) ) continue ; MachineOperand & OpToFold = MI . getOperand ( 1 ) ; bool FoldingImm = OpToFold . isImm ( ) || OpToFold . isFI ( ) ; if ( ! FoldingImm && ! OpToFold . isReg ( ) ) continue ; if ( OpToFold . isReg ( ) && ! TargetRegisterInfo :: isVirtualRegister ( OpToFold . getReg ( ) ) ) continue ; MachineOperand & Dst = MI . getOperand ( 0 ) ; if ( Dst . isReg ( ) && ! TargetRegisterInfo :: isVirtualRegister ( Dst . getReg ( ) ) ) continue ; foldInstOperand ( MI , OpToFold ) ; } } return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> RegisterRef PhysicalRegisterInfo :: normalize ( RegisterRef RR ) const { return RR ; } </s>


<s> int mn10300_get_live_callee_saved_regs ( ) { int mask ; int i ; mask = 0 ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( regs_ever_live [ i ] && ! call_used_regs [ i ] ) mask |= ( 1 << i ) ; if ( ( mask & 0x3c000 ) != 0 ) mask |= 0x3c000 ; return mask ; } </s>

Returns the set of live , callee-saved registers as a bitmask . The callee-saved extended registers can not be stored individually , so all of them will be included in the mask if any one of them is used .


<s>
void
CSKYDAGToDAGISel
::
Select
(
SDNode
*
N
)
{
if
(
N
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
N
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;
N
->
setNodeId
(
1
)
;
return
;
}
SDLoc
Dl
(
N
)
;
unsigned
Opcode
=
N
->
getOpcode
(
)
;
bool
IsSelected
=
false
;
switch
(
Opcode
)
{
default
:
break
;
}
if
(
IsSelected
)
return
;
SelectCode
(
N
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> static void nios2_init_builtins ( void ) { unsigned int i ; for ( i = 0 ; i < ARRAY_SIZE ( nios2_builtins ) ; i ++ ) { const struct nios2_builtin_desc * d = & nios2_builtins [ i ] ; tree fndecl = add_builtin_function ( d -> name , nios2_ftype ( d -> ftype ) , i , BUILT_IN_MD , NULL , NULL ) ; nios2_register_builtin_fndecl ( i , fndecl ) ; } nios2_fpu_builtin_base = ARRAY_SIZE ( nios2_builtins ) ; nios2_init_fpu_builtins ( nios2_fpu_builtin_base ) ; nios2_custom_builtin_base = nios2_fpu_builtin_base + ARRAY_SIZE ( nios2_fpu_insn ) ; nios2_custom_builtin_end = nios2_custom_builtin_base + NUM_CUSTOM_BUILTINS ; nios2_init_custom_builtins ( nios2_custom_builtin_base ) ; } </s>


<s> void aarch64_split_atomic_op ( enum rtx_code code , rtx old_out , rtx new_out , rtx mem , rtx value , rtx model_rtx , rtx cond ) { machine_mode mode = GET_MODE ( mem ) ; machine_mode wmode = ( mode == DImode ? DImode : SImode ) ; const enum memmodel model = memmodel_from_int ( INTVAL ( model_rtx ) ) ; const bool is_sync = is_mm_sync ( model ) ; rtx_code_label * label ; rtx x ; label = gen_label_rtx ( ) ; emit_label ( label ) ; if ( new_out ) new_out = gen_lowpart ( wmode , new_out ) ; if ( old_out ) old_out = gen_lowpart ( wmode , old_out ) ; else old_out = new_out ; value = simplify_gen_subreg ( wmode , value , mode , 0 ) ; if ( is_sync ) aarch64_emit_load_exclusive ( mode , old_out , mem , GEN_INT ( MEMMODEL_RELAXED ) ) ; else aarch64_emit_load_exclusive ( mode , old_out , mem , model_rtx ) ; switch ( code ) { case SET : new_out = value ; break ; case NOT : x = gen_rtx_AND ( wmode , old_out , value ) ; emit_insn ( gen_rtx_SET ( new_out , x ) ) ; x = gen_rtx_NOT ( wmode , new_out ) ; emit_insn ( gen_rtx_SET ( new_out , x ) ) ; break ; case MINUS : if ( CONST_INT_P ( value ) ) { value = GEN_INT ( - INTVAL ( value ) ) ; code = PLUS ; } default : x = gen_rtx_fmt_ee ( code , wmode , old_out , value ) ; emit_insn ( gen_rtx_SET ( new_out , x ) ) ; break ; } aarch64_emit_store_exclusive ( mode , cond , mem , gen_lowpart ( mode , new_out ) , model_rtx ) ; if ( aarch64_track_speculation ) { rtx cc_reg = aarch64_gen_compare_reg ( NE , cond , const0_rtx ) ; x = gen_rtx_NE ( GET_MODE ( cc_reg ) , cc_reg , const0_rtx ) ; } else x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; if ( is_sync ) aarch64_emit_post_barrier ( model ) ; } </s>


<s> void ARMElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; isAAPCS_ABI = TM . getSubtarget < ARMSubtarget > ( ) . isAAPCS_ABI ( ) ; if ( isAAPCS_ABI ) { StaticCtorSection = getContext ( ) . getELFSection ( ".init_array" , ELF :: SHT_INIT_ARRAY , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; StaticDtorSection = getContext ( ) . getELFSection ( ".fini_array" , ELF :: SHT_FINI_ARRAY , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; LSDASection = NULL ; } AttributesSection = getContext ( ) . getELFSection ( ".ARM.attributes" , ELF :: SHT_ARM_ATTRIBUTES , 0 , SectionKind :: getMetadata ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s> static int ix86_function_regparm ( tree type , tree decl ) { tree attr ; int regparm = ix86_regparm ; bool user_convention = false ; if ( ! TARGET_64BIT ) { attr = lookup_attribute ( "regparm" , TYPE_ATTRIBUTES ( type ) ) ; if ( attr ) { regparm = TREE_INT_CST_LOW ( TREE_VALUE ( TREE_VALUE ( attr ) ) ) ; user_convention = true ; } if ( lookup_attribute ( "fastcall" , TYPE_ATTRIBUTES ( type ) ) ) { regparm = 2 ; user_convention = true ; } if ( ! TARGET_64BIT && ! user_convention && decl && flag_unit_at_a_time && ! profile_flag ) { struct cgraph_local_info * i = cgraph_local_info ( decl ) ; if ( i && i -> local ) { int local_regparm , globals = 0 , regno ; for ( local_regparm = 0 ; local_regparm < 3 ; local_regparm ++ ) if ( global_regs [ local_regparm ] ) break ; if ( local_regparm == 3 && decl_function_context ( decl ) && ! DECL_NO_STATIC_CHAIN ( decl ) ) local_regparm = 2 ; for ( regno = 0 ; regno < 6 ; regno ++ ) if ( global_regs [ regno ] ) globals ++ ; local_regparm = globals < local_regparm ? local_regparm - globals : 0 ; if ( local_regparm > regparm ) regparm = local_regparm ; } } } return regparm ; } </s>

Return the regparm value for a function with the indicated TYPE and DECL . DECL may be NULL when calling function indirectly or considering a libcall .


<s> static bool arm_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { if ( size == UNITS_PER_WORD && aligned_p ) { fputs ( "\t.word\t" , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; if ( NEED_GOT_RELOC && flag_pic && making_const_table && ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF ) ) { if ( GET_CODE ( x ) == SYMBOL_REF && ( CONSTANT_POOL_ADDRESS_P ( x ) || SYMBOL_REF_LOCAL_P ( x ) ) ) fputs ( "(GOTOFF)" , asm_out_file ) ; else if ( GET_CODE ( x ) == LABEL_REF ) fputs ( "(GOTOFF)" , asm_out_file ) ; else fputs ( "(GOT)" , asm_out_file ) ; } fputc ( '\n' , asm_out_file ) ; return true ; } if ( arm_vector_mode_supported_p ( GET_MODE ( x ) ) ) { int i , units ; gcc_assert ( GET_CODE ( x ) == CONST_VECTOR ) ; units = CONST_VECTOR_NUNITS ( x ) ; switch ( GET_MODE ( x ) ) { case V2SImode : size = 4 ; break ; case V4HImode : size = 2 ; break ; case V8QImode : size = 1 ; break ; default : gcc_unreachable ( ) ; } for ( i = 0 ; i < units ; i ++ ) { rtx elt ; elt = CONST_VECTOR_ELT ( x , i ) ; assemble_integer ( elt , size , i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT , 1 ) ; } return true ; } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . The ARM version needs to handle word-sized values specially .


<s> const NVPTXRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void SystemZPassConfig :: addPostRegAlloc ( ) { if ( getOptLevel ( ) == CodeGenOpt :: None ) addPass ( createSystemZPostRewritePass ( getSystemZTargetMachine ( ) ) ) ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> unsigned X86FrameLowering :: getWinEHFuncletFrameSize ( const MachineFunction & MF ) const { unsigned CSSize = MF . getInfo < X86MachineFunctionInfo > ( ) -> getCalleeSavedFrameSize ( ) ; unsigned UsedSize ; EHPersonality Personality = classifyEHPersonality ( MF . getFunction ( ) -> getPersonalityFn ( ) ) ; if ( Personality == EHPersonality :: CoreCLR ) { UsedSize = getPSPSlotOffsetFromSP ( MF ) + SlotSize ; } else { UsedSize = MF . getFrameInfo ( ) . getMaxCallFrameSize ( ) ; } unsigned FrameSizeMinusRBP = alignTo ( CSSize + UsedSize , getStackAlignment ( ) ) ; return FrameSizeMinusRBP - CSSize ; } </s>

Funclets only need to account for space for the callee saved registers , as the locals are accounted for in the parent 's stack frame .


<s> const FPGASubtarget * FPGATargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute FPGAAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; StringRef FPGA = ! FPGAAttr . hasAttribute ( Attribute :: None ) ? FPGAAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < 512 > Key ; Key . reserve ( FPGA . size ( ) + FS . size ( ) ) ; Key += FPGA ; Key += FS ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < FPGASubtarget > ( TargetTriple , FPGA , FS , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

FPGA FPGA FPGA FPGA "target-cpu" "target-features" FPGA FPGA FPGA 512 FPGA FPGA FPGA FPGA


<s>
SDValue
SystemZTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
DL
,
SelectionDAG
&
DAG
)
const
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
SmallVector
<
CCValAssign
,
16
>
RetLocs
;
CCState
RetCCInfo
(
CallConv
,
IsVarArg
,
MF
,
RetLocs
,
*
DAG
.
getContext
(
)
)
;
RetCCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_SystemZ
)
;
if
(
RetLocs
.
empty
(
)
)
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
Chain
)
;
SDValue
Glue
;
SmallVector
<
SDValue
,
4
>
RetOps
;
RetOps
.
push_back
(
Chain
)
;
for
(
unsigned
I
=
0
,
E
=
RetLocs
.
size
(
)
;
I
!=
E
;
++
I
)
{
CCValAssign
&
VA
=
RetLocs
[
I
]
;
SDValue
RetValue
=
OutVals
[
I
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
RetValue
=
convertValVTToLocVT
(
DAG
,
DL
,
VA
,
RetValue
)
;
unsigned
Reg
=
VA
.
getLocReg
(
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
Reg
,
RetValue
,
Glue
)
;
Glue
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
Reg
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Glue
.
getNode
(
)
)
RetOps
.
push_back
(
Glue
)
;
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void HexagonCommonGEP :: removeDeadCode ( ) { ValueVect BO ; BO . push_back ( & Fn -> front ( ) ) ; for ( unsigned i = 0 ; i < BO . size ( ) ; ++ i ) { BasicBlock * B = cast < BasicBlock > ( BO [ i ] ) ; DomTreeNode * N = DT -> getNode ( B ) ; typedef GraphTraits < DomTreeNode * > GTN ; typedef GTN :: ChildIteratorType Iter ; for ( Iter I = GTN :: child_begin ( N ) , E = GTN :: child_end ( N ) ; I != E ; ++ I ) BO . push_back ( ( * I ) -> getBlock ( ) ) ; } for ( unsigned i = BO . size ( ) ; i > 0 ; -- i ) { BasicBlock * B = cast < BasicBlock > ( BO [ i - 1 ] ) ; BasicBlock :: InstListType & IL = B -> getInstList ( ) ; typedef BasicBlock :: InstListType :: reverse_iterator reverse_iterator ; ValueVect Ins ; for ( reverse_iterator I = IL . rbegin ( ) , E = IL . rend ( ) ; I != E ; ++ I ) Ins . push_back ( & * I ) ; for ( ValueVect :: iterator I = Ins . begin ( ) , E = Ins . end ( ) ; I != E ; ++ I ) { Instruction * In = cast < Instruction > ( * I ) ; if ( isInstructionTriviallyDead ( In ) ) In -> eraseFromParent ( ) ; } } } </s>

Remove all dead instructions between the I and E .


<s> static rtx conditionalize_nonjump ( rtx pat , rtx cond , rtx insn , bool annulled ) { if ( GET_CODE ( pat ) == SET ) { rtx src = SET_SRC ( pat ) ; if ( COMMUTATIVE_P ( src ) ) { rtx src0 = XEXP ( src , 0 ) ; rtx src1 = XEXP ( src , 1 ) ; rtx dst = SET_DEST ( pat ) ; if ( rtx_equal_p ( src1 , dst ) && ! rtx_equal_p ( src0 , dst ) && REG_P ( src0 ) ) pat = gen_rtx_SET ( dst , gen_rtx_fmt_ee ( GET_CODE ( src ) , GET_MODE ( src ) , src1 , src0 ) ) ; } } if ( RTX_FRAME_RELATED_P ( insn ) ) { gcc_assert ( annulled ) ; rtx note = alloc_reg_note ( REG_FRAME_RELATED_EXPR , pat , REG_NOTES ( insn ) ) ; validate_change ( insn , & REG_NOTES ( insn ) , note , 1 ) ; } pat = gen_rtx_COND_EXEC ( VOIDmode , cond , pat ) ; return pat ; } </s>

Return version of PAT conditionalized with COND , which is part of INSN . ANNULLED indicates if INSN is an annulled delay-slot insn . Register further changes if necessary .


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , int64_t NumBytes , const TargetInstrInfo & TII ) { unsigned Opc ; uint64_t Chunk ; bool isSub = NumBytes < 0 ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; if ( Offset >= ( 1LL << 15 ) - 1 ) { Opc = SystemZ :: ADD64ri32 ; Chunk = ( 1LL << 31 ) - 1 ; } else { Opc = SystemZ :: ADD64ri16 ; Chunk = ( 1LL << 15 ) - 1 ; } DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; while ( Offset ) { uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , SystemZ :: R15D ) . addReg ( SystemZ :: R15D ) . addImm ( isSub ? - ThisVal : ThisVal ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> Instruction * PPCTargetLowering :: emitLeadingFence ( IRBuilder < > & Builder , Instruction * Inst , AtomicOrdering Ord ) const { if ( Ord == AtomicOrdering :: SequentiallyConsistent ) return callIntrinsic ( Builder , Intrinsic :: ppc_sync ) ; if ( isReleaseOrStronger ( Ord ) ) return callIntrinsic ( Builder , Intrinsic :: ppc_lwsync ) ; return nullptr ; } </s>


<s> static bool mt_pass_in_stack ( enum machine_mode mode ATTRIBUTE_UNUSED , tree type ) { return ( ( ( type ) != 0 && ( TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST || TREE_ADDRESSABLE ( type ) ) ) ) ; } </s>

Implement TARGET_MUST_PASS_IN_STACK hook .


<s> static int rid_int128 ( void ) { int i ; for ( i = 0 ; i < NUM_INT_N_ENTS ; i ++ ) if ( int_n_enabled_p [ i ] && int_n_data [ i ] . bitsize == 128 ) return RID_INT_N_0 + i ; return RID_MAX + 1 ; } </s>

Helper function to find out which RID_INT_N_ * code is the one for __int128 , if any . Returns RID_MAX+1 if none apply , which is safe ( for our purposes , since we always expect to have __int128 ) to compare against .


<s>
bool
AArch64FrameLowering
::
hasFP
(
const
MachineFunction
&
MF
)
const
{
const
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
const
TargetRegisterInfo
*
RegInfo
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
assert
(
!
RegInfo
->
needsStackRealignment
(
MF
)
&&
"No stack realignment on AArch64!"
)
;
return
(
MFI
->
hasCalls
(
)
||
MFI
->
hasVarSizedObjects
(
)
||
MFI
->
isFrameAddressTaken
(
)
)
;
}
</s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static rtx arc_dwarf_register_span ( rtx rtl ) { enum machine_mode mode = GET_MODE ( rtl ) ; unsigned regno ; rtx p ; if ( GET_MODE_SIZE ( mode ) != 8 ) return NULL_RTX ; p = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( 2 ) ) ; regno = REGNO ( rtl ) ; XVECEXP ( p , 0 , 0 ) = gen_rtx_REG ( SImode , regno ) ; XVECEXP ( p , 0 , 1 ) = gen_rtx_REG ( SImode , regno + 1 ) ; return p ; } </s>

Return a parallel of registers to represent where to find the register pieces if required , otherwise NULL_RTX .


<s> rtx mmix_gen_compare_reg ( RTX_CODE code , rtx x , rtx y ) { enum machine_mode ccmode = SELECT_CC_MODE ( code , x , y ) ; rtx cc_reg ; enum machine_mode mode = GET_MODE ( x ) == VOIDmode ? GET_MODE ( y ) : GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ? DFmode : DImode ; if ( ! mmix_valid_comparison ( code , mode , x ) ) return NULL_RTX ; cc_reg = gen_reg_rtx ( ccmode ) ; if ( ! REG_P ( x ) && ! REG_P ( y ) ) x = force_reg ( mode , x ) ; if ( ! REG_P ( y ) && ( GET_CODE ( y ) != CONST_INT || ! CONST_OK_FOR_LETTER_P ( INTVAL ( y ) , 'I' ) ) ) y = force_reg ( mode , y ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cc_reg , gen_rtx_COMPARE ( ccmode , x , y ) ) ) ; return cc_reg ; } </s>

X and Y are two things to compare using CODE . Emit a compare insn if possible and return the rtx for the cc-reg in the proper mode , or NULL_RTX if this is not a valid comparison .


<s> void arc_expand_epilogue ( int sibcall_p ) { int size ; unsigned int fn_type = arc_compute_function_type ( cfun ) ; unsigned int size_to_deallocate ; int restored ; int can_trust_sp_p = ! cfun -> calls_alloca ; int first_offset ; bool restore_fp = arc_frame_pointer_needed ( ) && ! ARC_AUTOFP_IRQ_P ( fn_type ) ; bool restore_blink = arc_must_save_return_addr ( cfun ) && ! ARC_AUTOBLINK_IRQ_P ( fn_type ) ; unsigned int gmask = cfun -> machine -> frame_info . gmask ; bool return_p = ! sibcall_p && fn_type == ARC_FUNCTION_NORMAL && ! cfun -> machine -> frame_info . pretend_size ; struct arc_frame_info * frame = & cfun -> machine -> frame_info ; if ( ARC_NAKED_P ( fn_type ) ) return ; size = arc_compute_frame_size ( ) ; size_to_deallocate = size ; first_offset = size - ( frame -> pretend_size + frame -> reg_size + frame -> extra_size ) ; if ( ! can_trust_sp_p ) gcc_assert ( arc_frame_pointer_needed ( ) ) ; if ( size ) emit_insn ( gen_blockage ( ) ) ; if ( TARGET_CODE_DENSITY && TARGET_CODE_DENSITY_FRAME && ! ARC_AUTOFP_IRQ_P ( fn_type ) && ! ARC_AUTOBLINK_IRQ_P ( fn_type ) && ! ARC_INTERRUPT_P ( fn_type ) && arc_enter_leave_p ( gmask ) ) { size_to_deallocate -= arc_restore_callee_leave ( gmask , restore_blink , restore_fp , return_p , first_offset ) ; if ( return_p ) { gcc_assert ( size_to_deallocate == 0 ) ; return ; } } else if ( frame -> millicode_end_reg > 14 ) { size_to_deallocate -= arc_restore_callee_milli ( gmask , restore_blink , restore_fp , return_p , first_offset ) ; if ( return_p ) { gcc_assert ( size_to_deallocate == 0 ) ; return ; } } else size_to_deallocate -= arc_restore_callee_saves ( gmask , restore_blink , restore_fp , first_offset , size_to_deallocate ) ; restored = size - size_to_deallocate ; if ( size > restored ) frame_stack_add ( size - restored ) ; if ( crtl -> calls_eh_return ) emit_insn ( gen_add2_insn ( stack_pointer_rtx , EH_RETURN_STACKADJ_RTX ) ) ; if ( sibcall_p == FALSE ) emit_jump_insn ( gen_simple_return ( ) ) ; } </s>

Do any necessary cleanup after a function to restore stack , frame , and regs .


<s> void reset ( ) override { MappingSymbolCounter = 0 ; MCELFStreamer :: reset ( ) ; LastMappingSymbols . clear ( ) ; LastEMS = EMS_None ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s> unsigned SIInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const MCInstrDesc & Desc = getMCOpcodeFromPseudo ( Opc ) ; unsigned DescSize = Desc . getSize ( ) ; if ( isFixedSize ( MI ) ) return DescSize ; if ( isVALU ( MI ) || isSALU ( MI ) ) { int Src0Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src0 ) ; if ( Src0Idx == - 1 ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src0Idx ) , Desc . OpInfo [ Src0Idx ] ) ) return isVOP3 ( MI ) ? 12 : ( DescSize + 4 ) ; int Src1Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src1 ) ; if ( Src1Idx == - 1 ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src1Idx ) , Desc . OpInfo [ Src1Idx ] ) ) return isVOP3 ( MI ) ? 12 : ( DescSize + 4 ) ; int Src2Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src2 ) ; if ( Src2Idx == - 1 ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src2Idx ) , Desc . OpInfo [ Src2Idx ] ) ) return isVOP3 ( MI ) ? 12 : ( DescSize + 4 ) ; return DescSize ; } if ( isMIMG ( MI ) ) { int VAddr0Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: vaddr0 ) ; if ( VAddr0Idx < 0 ) return 8 ; int RSrcIdx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: srsrc ) ; return 8 + 4 * ( ( RSrcIdx - VAddr0Idx + 2 ) / 4 ) ; } switch ( Opc ) { case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : case TargetOpcode :: EH_LABEL : return 0 ; case TargetOpcode :: BUNDLE : return getInstBundleSize ( MI ) ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) , & MF -> getSubtarget ( ) ) ; } default : return DescSize ; } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> unsigned HexagonTTIImpl :: getIntrinsicInstrCost ( const IntrinsicCostAttributes & ICA , TTI :: TargetCostKind CostKind ) { if ( ICA . getID ( ) == Intrinsic :: bswap ) { std :: pair < int , MVT > LT = TLI . getTypeLegalizationCost ( DL , ICA . getReturnType ( ) ) ; return LT . first + 2 ; } return BaseT :: getIntrinsicInstrCost ( ICA , CostKind ) ; } </s>


"calling %qD with SSE calling convention without "

"this is a GCC bug that can be worked around by adding "

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . ) Return a number of integer regsiters advanced over .


<s> static int get_spec_unspec_code ( const_rtx x ) { if ( GET_CODE ( x ) != UNSPEC ) return - 1 ; { int code ; code = XINT ( x , 1 ) ; switch ( code ) { case UNSPEC_LDA : case UNSPEC_LDS : case UNSPEC_LDS_A : case UNSPEC_LDSA : return code ; default : return - 1 ; } } } </s>

If X is an unspec part of a speculative load , return its code . Return -1 otherwise .


<s> int rs6000_legitimate_address ( enum machine_mode mode , rtx x , int reg_ok_strict ) { if ( TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE ( mode ) && GET_CODE ( x ) == AND && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT && INTVAL ( XEXP ( x , 1 ) ) == - 16 ) x = XEXP ( x , 0 ) ; if ( RS6000_SYMBOL_REF_TLS_P ( x ) ) return 0 ; if ( legitimate_indirect_address_p ( x , reg_ok_strict ) ) return 1 ; if ( ( GET_CODE ( x ) == PRE_INC || GET_CODE ( x ) == PRE_DEC ) && ! ALTIVEC_VECTOR_MODE ( mode ) && ! SPE_VECTOR_MODE ( mode ) && ! ( TARGET_E500_DOUBLE && ( mode == DFmode || mode == DImode ) ) && TARGET_UPDATE && legitimate_indirect_address_p ( XEXP ( x , 0 ) , reg_ok_strict ) ) return 1 ; if ( rs6000_legitimate_small_data_p ( mode , x ) ) return 1 ; if ( legitimate_constant_pool_address_p ( x ) ) return 1 ; if ( ! reg_ok_strict && GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 0 ) ) == REG && ( XEXP ( x , 0 ) == virtual_stack_vars_rtx || XEXP ( x , 0 ) == arg_pointer_rtx ) && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) return 1 ; if ( rs6000_legitimate_offset_address_p ( mode , x , reg_ok_strict ) ) return 1 ; if ( mode != TImode && mode != TFmode && ( ( TARGET_HARD_FLOAT && TARGET_FPRS ) || TARGET_POWERPC64 || ( ( mode != DFmode || TARGET_E500_DOUBLE ) && mode != TFmode ) ) && ( TARGET_POWERPC64 || mode != DImode ) && legitimate_indexed_address_p ( x , reg_ok_strict ) ) return 1 ; if ( legitimate_lo_sum_address_p ( mode , x , reg_ok_strict ) ) return 1 ; return 0 ; } </s>

GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid memory address for an instruction . The MODE argument is the machine mode for the MEM expression that wants to use this address . On the RS/6000 , there are four valid address : a SYMBOL_REF that refers to a constant pool entry of an address ( or the sum of it plus a constant ) , a short ( 16-bit signed ) constant plus a register , the sum of two registers , or a register indirect , possibly with an auto-increment . For DFmode and DImode with a constant plus register , we must ensure that both words are addressable or PowerPC64 with offset word aligned . For modes spanning multiple registers ( DFmode in 32-bit GPRs , 32-bit DImode , TImode , TFmode ) , indexed addressing can not be used because adjacent memory cells are accessed by adding word-sized offsets during assembly output .


<s>
bool
VETargetLowering
::
CanLowerReturn
(
CallingConv
::
ID
CallConv
,
MachineFunction
&
MF
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
LLVMContext
&
Context
)
const
{
assert
(
!
IsVarArg
&&
"TODO implement var args"
)
;
assert
(
Outs
.
empty
(
)
&&
"TODO implement return values"
)
;
return
true
;
}
</s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .

VE
VE
ISD::OutputArg
"TODO implement var args"
"TODO implement return values"


<s> static void ix86_run_selftests ( void ) { ix86_test_dumping_hard_regs ( ) ; ix86_test_dumping_memory_blockage ( ) ; ix86_test_loading_dump_fragment_1 ( ) ; ix86_test_loading_call_insn ( ) ; ix86_test_loading_full_dump ( ) ; ix86_test_loading_unspec ( ) ; } </s>


<s> bool s390_vectorize_vec_perm_const ( machine_mode vmode , rtx target , rtx op0 , rtx op1 , const vec_perm_indices & sel ) { struct expand_vec_perm_d d ; unsigned int i , nelt ; if ( ! s390_vector_mode_supported_p ( vmode ) || GET_MODE_SIZE ( vmode ) != 16 ) return false ; d . target = target ; d . op0 = op0 ; d . op1 = op1 ; d . vmode = vmode ; gcc_assert ( VECTOR_MODE_P ( d . vmode ) ) ; d . nelt = nelt = GET_MODE_NUNITS ( d . vmode ) ; d . testing_p = target == NULL_RTX ; gcc_assert ( target == NULL_RTX || REG_P ( target ) ) ; gcc_assert ( sel . length ( ) == nelt ) ; for ( i = 0 ; i < nelt ; i ++ ) { unsigned char e = sel [ i ] ; gcc_assert ( e < 2 * nelt ) ; d . perm [ i ] = e ; } return vectorize_vec_perm_const_1 ( d ) ; } </s>

Return true if we can emit instructions for the constant permutation vector in SEL . If OUTPUT , IN0 , IN1 are non-null the hook is supposed to emit the required INSNs .


<s> static enum rs6000_reg_type register_to_reg_type ( rtx reg , bool * is_altivec ) { HOST_WIDE_INT regno ; enum reg_class rclass ; if ( SUBREG_P ( reg ) ) reg = SUBREG_REG ( reg ) ; if ( ! REG_P ( reg ) ) return NO_REG_TYPE ; regno = REGNO ( reg ) ; if ( ! HARD_REGISTER_NUM_P ( regno ) ) { if ( ! lra_in_progress && ! reload_completed ) return PSEUDO_REG_TYPE ; regno = true_regnum ( reg ) ; if ( regno < 0 || ! HARD_REGISTER_NUM_P ( regno ) ) return PSEUDO_REG_TYPE ; } gcc_assert ( regno >= 0 ) ; if ( is_altivec && ALTIVEC_REGNO_P ( regno ) ) * is_altivec = true ; rclass = rs6000_regno_regclass [ regno ] ; return reg_class_to_reg_type [ ( int ) rclass ] ; } </s>

Classify a register type . Because the FMRGOW/FMRGEW instructions only work on traditional floating point registers , and the VMRGOW/VMRGEW instructions only work on the traditional altivec registers , note if an altivec register was chosen .


<s> bool s390_hard_regno_rename_ok ( unsigned int old_reg , unsigned int new_reg ) { if ( cfun -> machine -> base_reg ) if ( REGNO ( cfun -> machine -> base_reg ) == old_reg || REGNO ( cfun -> machine -> base_reg ) == new_reg ) return false ; if ( GENERAL_REGNO_P ( new_reg ) && ! call_really_used_regs [ new_reg ] && cfun_gpr_save_slot ( new_reg ) == 0 ) return false ; return true ; } </s>

Return nonzero if register OLD_REG can be renamed to register NEW_REG .


<s> bool mips_const_vector_same_val_p ( rtx op , machine_mode mode ) { int i , nunits = GET_MODE_NUNITS ( mode ) ; rtx first ; if ( GET_CODE ( op ) != CONST_VECTOR || GET_MODE ( op ) != mode ) return false ; first = CONST_VECTOR_ELT ( op , 0 ) ; for ( i = 1 ; i < nunits ; i ++ ) if ( ! rtx_equal_p ( first , CONST_VECTOR_ELT ( op , i ) ) ) return false ; return true ; } </s>

Return true if OP is a constant vector with the number of units in MODE , and each unit has the same value .


<s> const MCPhysReg * SystemZRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const SystemZSubtarget & Subtarget = MF -> getSubtarget < SystemZSubtarget > ( ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: AnyReg ) return Subtarget . hasVector ( ) ? CSR_SystemZ_AllRegs_Vector_SaveList : CSR_SystemZ_AllRegs_SaveList ; if ( MF -> getSubtarget ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF -> getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_SystemZ_SwiftError_SaveList ; return CSR_SystemZ_SaveList ; } </s>

SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ


<s> static void tilepro_trampoline_init ( rtx m_tramp , tree fndecl , rtx static_chain ) { rtx fnaddr , chaddr ; rtx mem ; rtx begin_addr , end_addr ; int ptr_mode_size = GET_MODE_SIZE ( ptr_mode ) ; fnaddr = copy_to_reg ( XEXP ( DECL_RTL ( fndecl ) , 0 ) ) ; chaddr = copy_to_reg ( static_chain ) ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp , ptr_mode , TRAMPOLINE_SIZE - 2 * ptr_mode_size ) ; emit_move_insn ( mem , fnaddr ) ; mem = adjust_address ( m_tramp , ptr_mode , TRAMPOLINE_SIZE - ptr_mode_size ) ; emit_move_insn ( mem , chaddr ) ; begin_addr = force_reg ( Pmode , XEXP ( m_tramp , 0 ) ) ; end_addr = force_reg ( Pmode , plus_constant ( Pmode , XEXP ( m_tramp , 0 ) , TRAMPOLINE_SIZE ) ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , "__clear_cache" ) , LCT_NORMAL , VOIDmode , 2 , begin_addr , Pmode , end_addr , Pmode ) ; } </s>


"Function versions cannot be marked as gnu_inline,"

"Virtual function multiversioning not supported"

This function changes the assembler name for functions that are versions . If DECL is a function version and has a `` target '' attribute , it appends the attribute string to its assembler name .


<s> bool X86InstrInfo :: hasHighOperandLatency ( const TargetSchedModel & SchedModel , const MachineRegisterInfo * MRI , const MachineInstr & DefMI , unsigned DefIdx , const MachineInstr & UseMI , unsigned UseIdx ) const { return isHighLatencyDef ( DefMI . getOpcode ( ) ) ; } </s>

Compute operand latency between a def of 'Reg ' and a use in the current loop .


<s> bool RISCVExpandSSR :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const RISCVInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; this -> MF = & MF ; this -> RVFI = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; Enabled = false ; bool Modified = false ; for ( auto & MBB : MF ) Modified |= expandMBB ( MBB ) ; RISCVExpandSSR :: RegisterMergingPreferences RMP = gatherRegisterMergingPreferences ( ) ; if ( RMP . Enable && RVFI -> getUsedSSR ( ) ) for ( auto & MBB : MF ) mergePushPop ( MBB ) ; if ( Modified ) { for ( auto & MBB : MF ) { for ( unsigned ssr_no = 0 ; ssr_no < NUM_SSR ; ++ ssr_no ) MBB . addLiveIn ( getSSRFtReg ( ssr_no ) ) ; MBB . sortUniqueLiveIns ( ) ; } } return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s>
SDValue
MBlazeTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_MBlaze
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
if
(
RVLocs
[
i
]
.
isRegLoc
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
MBlazeISD
::
Ret
,
dl
,
MVT
::
Other
,
Chain
,
DAG
.
getRegister
(
MBlaze
::
R15
,
MVT
::
i32
)
,
Flag
)
;
else
return
DAG
.
getNode
(
MBlazeISD
::
Ret
,
dl
,
MVT
::
Other
,
Chain
,
DAG
.
getRegister
(
MBlaze
::
R15
,
MVT
::
i32
)
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool doInitialization ( Module & M ) override { LLVMContext & Ctx = M . getContext ( ) ; Mod = & M ; FloatType = Type :: getFloatTy ( Ctx ) ; Int32Type = Type :: getInt32Ty ( Ctx ) ; V4f32Type = VectorType :: get ( FloatType , 4 ) ; V4i32Type = VectorType :: get ( Int32Type , 4 ) ; Type * ArgsType [ ] = { V4f32Type , Int32Type , Int32Type , Int32Type , Int32Type , Int32Type , Int32Type , Int32Type , Int32Type , Int32Type , } ; TexSign = FunctionType :: get ( V4f32Type , ArgsType , false ) ; Type * ArgsQType [ ] = { V4i32Type , Int32Type , Int32Type , Int32Type , Int32Type , Int32Type , Int32Type , Int32Type , Int32Type , Int32Type , } ; TexQSign = FunctionType :: get ( V4f32Type , ArgsQType , false ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> X86Subtarget :: X86Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const X86TargetMachine & TM , unsigned StackAlignOverride ) : X86GenSubtargetInfo ( TT , CPU , FS ) , X86ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TM ( TM ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( * this , getStackAlignment ( ) ) { if ( ! isPositionIndependent ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( is64Bit ( ) ) setPICStyle ( PICStyles :: RIPRel ) ; else if ( isTargetCOFF ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( isTargetDarwin ( ) ) setPICStyle ( PICStyles :: StubPIC ) ; else if ( isTargetELF ( ) ) setPICStyle ( PICStyles :: GOT ) ; CallLoweringInfo . reset ( new X86CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new X86LegalizerInfo ( * this , TM ) ) ; auto * RBI = new X86RegisterBankInfo ( * getRegisterInfo ( ) ) ; RegBankInfo . reset ( RBI ) ; InstSelector . reset ( createX86InstructionSelector ( TM , * this , * RBI ) ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> static tree rs6000_d_handle_target_float_abi ( void ) { const char * abi ; if ( TARGET_HARD_FLOAT ) abi = "hard" ; else if ( TARGET_SOFT_FLOAT ) abi = "soft" ; else abi = "" ; return build_string_literal ( strlen ( abi ) + 1 , abi ) ; } </s>

Handle a call to ` __traits ( getTargetInfo , `` floatAbi '' ) ' .


<s> void print ( raw_ostream & OS ) const override { switch ( Kind ) { case k_Register : OS << "Reg<" << Reg . Num << ">" ; break ; case k_Immediate : OS << "Imm<" << ( ( const MCConstantExpr * ) Imm . Val ) -> getValue ( ) << ">" ; break ; case k_Token : OS << Tok . Data ; break ; } } </s>

print - Print a debug representation of the operand to the given stream .


<s> bool PatmosFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * TM . getInstrInfo ( ) ; PatmosMachineFunctionInfo & PMFI = * MF . getInfo < PatmosMachineFunctionInfo > ( ) ; unsigned spilledSize = 0 ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; if ( Patmos :: PRegsRegClass . contains ( Reg ) ) continue ; if ( Reg == Patmos :: S0 && PMFI . getS0SpillReg ( ) ) { TII . copyPhysReg ( MBB , MI , DL , PMFI . getS0SpillReg ( ) , Reg , true ) ; prior ( MI ) -> setFlag ( MachineInstr :: FrameSetup ) ; continue ; } if ( Patmos :: SRegsRegClass . contains ( Reg ) ) { TII . copyPhysReg ( MBB , MI , DL , Patmos :: R9 , Reg , true ) ; prior ( MI ) -> setFlag ( MachineInstr :: FrameSetup ) ; Reg = Patmos :: R9 ; } const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - 1 ] . getFrameIdx ( ) , RC , TRI ) ; prior ( MI ) -> setFlag ( MachineInstr :: FrameSetup ) ; spilledSize += 4 ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> bool ARMTargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


"unimplemented opcode in encodeInstruction()"

Encode the given Inst to bytes and append to CB .


<s> bool RISCVTargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const { return isInt < 12 > ( Imm ) ; } </s>

Return true if the specified immediate is legal icmp immediate , that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register .


<s>
SDValue
MSP430TargetLowering
::
LowerCall
(
SDValue
Chain
,
SDValue
Callee
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
bool
&
isTailCall
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
OutVals
,
Ins
,
dl
,
DAG
,
InVals
)
;
case
CallingConv
::
MSP430_INTR
:
report_fatal_error
(
"ISRs cannot be called directly"
)
;
return
SDValue
(
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .


<s> void mprocFrameLowering :: emitPrologue ( MachineFunction & MF ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static void mips_pop_asm_switch_1 ( struct mips_asm_switch * asm_switch , const char * prefix , const char * suffix ) { gcc_assert ( asm_switch -> nesting_level ) ; asm_switch -> nesting_level -- ; if ( asm_switch -> nesting_level == 0 ) fprintf ( asm_out_file , "%s.set\t%s%s" , prefix , asm_switch -> name , suffix ) ; } </s>


"FP elimination on a non-leaf function is not supported"


<s> static unsigned rs6000_adjust_vect_cost_per_stmt ( enum vect_cost_for_stmt kind , struct _stmt_vec_info * stmt_info ) { if ( kind == scalar_stmt && stmt_info && stmt_info -> stmt && gimple_code ( stmt_info -> stmt ) == GIMPLE_ASSIGN ) { tree_code subcode = gimple_assign_rhs_code ( stmt_info -> stmt ) ; if ( subcode == COND_EXPR ) return 2 ; } return 0 ; } </s>

Adjust vectorization cost after calling rs6000_builtin_vectorization_cost . For some statement , we would like to further fine-grain tweak the cost on top of rs6000_builtin_vectorization_cost handling which does n't have any information on statement operation codes etc . One typical case here is COND_EXPR , it takes the same cost to simple FXU instruction when evaluating for scalar cost , but it should be priced more whatever transformed to either compare + branch or compare + isel instructions .


<s> const Z80oldSubtarget & getSubtarget ( ) const { return * Subtarget ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


<s> bool AArch64RegisterInfo :: isAsmClobberable ( const MachineFunction & MF , unsigned PhysReg ) const { return ! isReservedReg ( MF , PhysReg ) ; } </s>

Returns false if we ca n't guarantee that Physreg , specified as an IR asm clobber constraint , will be preserved across the statement .


"********** AArch64 Conditional Compares **********\n"


<s> static rtx get_branch_target ( rtx branch ) { if ( CALL_P ( branch ) ) { rtx call ; call = XVECEXP ( PATTERN ( branch ) , 0 , 0 ) ; if ( GET_CODE ( call ) == SET ) call = SET_SRC ( call ) ; if ( GET_CODE ( call ) != CALL ) abort ( ) ; return XEXP ( XEXP ( call , 0 ) , 0 ) ; } } </s>

Returns 0 if we do n't want a hint for this branch . Otherwise return the rtx for the branch target .


<s> int vfp3_const_double_rtx ( rtx x ) { if ( ! TARGET_VFP3 ) return 0 ; return vfp3_const_double_index ( x ) != - 1 ; } </s>

Return TRUE if rtx X is a valid immediate VFPv3 constant .


<s> const TargetRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
MachineInstrBuilder
R600InstrInfo
::
buildIndirectRead
(
MachineBasicBlock
*
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
ValueReg
,
unsigned
Address
,
unsigned
OffsetReg
,
unsigned
AddrChan
)
const
{
unsigned
AddrReg
;
switch
(
AddrChan
)
{
default
:
llvm_unreachable
(
"Invalid Channel"
)
;
case
0
:
AddrReg
=
AMDGPU
::
R600_AddrRegClass
.
getRegister
(
Address
)
;
break
;
case
1
:
AddrReg
=
AMDGPU
::
R600_Addr_YRegClass
.
getRegister
(
Address
)
;
break
;
case
2
:
AddrReg
=
AMDGPU
::
R600_Addr_ZRegClass
.
getRegister
(
Address
)
;
break
;
case
3
:
AddrReg
=
AMDGPU
::
R600_Addr_WRegClass
.
getRegister
(
Address
)
;
break
;
}
MachineInstr
*
MOVA
=
buildDefaultInstruction
(
*
MBB
,
I
,
AMDGPU
::
MOVA_INT_eg
,
AMDGPU
::
AR_X
,
OffsetReg
)
;
setImmOperand
(
*
MOVA
,
AMDGPU
::
OpName
::
write
,
0
)
;
MachineInstrBuilder
Mov
=
buildDefaultInstruction
(
*
MBB
,
I
,
AMDGPU
::
MOV
,
ValueReg
,
AddrReg
)
.
addReg
(
AMDGPU
::
AR_X
,
RegState
::
Implicit
|
RegState
::
Kill
)
;
setImmOperand
(
*
Mov
,
AMDGPU
::
OpName
::
src0_rel
,
1
)
;
return
Mov
;
}
</s>

Build instruction ( s ) for an indirect register read .


<s> static int ix86_mode_entry ( int entity ) { switch ( entity ) { case X86_DIRFLAG : return ix86_dirflag_mode_entry ( ) ; case AVX_U128 : return ix86_avx_u128_mode_entry ( ) ; case I387_ROUNDEVEN : case I387_TRUNC : case I387_FLOOR : case I387_CEIL : return I387_CW_ANY ; default : gcc_unreachable ( ) ; } } </s>

Return a mode that ENTITY is assumed to be switched to at function entry .


<s> static rtx avr_function_arg ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int bytes = avr_num_arg_regs ( arg . mode , arg . type ) ; if ( cum -> nregs && bytes <= cum -> nregs ) return gen_rtx_REG ( arg . mode , cum -> regno - bytes ) ; return NULL_RTX ; } </s>

Controls whether a function argument is passed in a register , and which register .


<s> const SIRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>


<s> outliner :: TargetCostInfo X86InstrInfo :: getOutliningCandidateInfo ( std :: vector < outliner :: Candidate > & RepeatedSequenceLocs ) const { unsigned SequenceSize = std :: accumulate ( RepeatedSequenceLocs [ 0 ] . front ( ) , std :: next ( RepeatedSequenceLocs [ 0 ] . back ( ) ) , 0 , [ ] ( unsigned Sum , const MachineInstr & MI ) { if ( MI . isDebugInstr ( ) || MI . isKill ( ) ) return Sum ; return Sum + 1 ; } ) ; if ( RepeatedSequenceLocs [ 0 ] . back ( ) -> isTerminator ( ) ) return outliner :: TargetCostInfo ( SequenceSize , 1 , 0 , MachineOutlinerTailCall , MachineOutlinerTailCall ) ; return outliner :: TargetCostInfo ( SequenceSize , 1 , 1 , MachineOutlinerDefault , MachineOutlinerDefault ) ; } </s>

Returns a outliner : :OutlinedFunction struct containing target-specific information for a set of outlining candidates .


"Block %d(%d), parent (%d), orientation %+d\n"

DFS walk creating SESE data structures . Only cover nodes with BB_VISITED set . Append discovered blocks to LIST . We number in increments of 3 so that the above and below pseudo nodes can be implicitly numbered too .


<s> void RISCVPassConfig :: addPreEmitPass ( ) { addPass ( createRISCVBranchSelectionPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> bool X86AsmParser :: parsePrimaryExpr ( const MCExpr * & Res , SMLoc & EndLoc ) { MCAsmParser & Parser = getParser ( ) ; if ( getTok ( ) . is ( AsmToken :: Percent ) || ( isParsingIntelSyntax ( ) && getTok ( ) . is ( AsmToken :: Identifier ) && MatchRegisterName ( Parser . getTok ( ) . getString ( ) ) ) ) { SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; unsigned RegNo ; if ( ParseRegister ( RegNo , StartLoc , EndLoc ) ) return true ; Res = X86MCExpr :: create ( RegNo , Parser . getContext ( ) ) ; return false ; } return Parser . parsePrimaryExpr ( Res , EndLoc , nullptr ) ; } </s>


<s> void MipsELFStreamer :: emitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) { MCELFStreamer :: emitInstruction ( Inst , STI ) ; MCContext & Context = getContext ( ) ; const MCRegisterInfo * MCRegInfo = Context . getRegisterInfo ( ) ; for ( unsigned OpIndex = 0 ; OpIndex < Inst . getNumOperands ( ) ; ++ OpIndex ) { const MCOperand & Op = Inst . getOperand ( OpIndex ) ; if ( ! Op . isReg ( ) ) continue ; unsigned Reg = Op . getReg ( ) ; RegInfoRecord -> SetPhysRegUsed ( Reg , MCRegInfo ) ; } createPendingLabelRelocs ( ) ; } </s>

Targets should implement this to emit instructions .


<s> bool ix86_using_red_zone ( void ) { return ( TARGET_RED_ZONE && ! TARGET_64BIT_MS_ABI && ( ! cfun -> machine -> has_local_indirect_jump || cfun -> machine -> indirect_branch_type == indirect_branch_keep ) ) ; } </s>


<s> SDValue X86TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: EXTRACT_VECTOR_ELT : return PerformEXTRACT_VECTOR_ELTCombine ( N , DAG , * this ) ; case ISD :: SELECT : return PerformSELECTCombine ( N , DAG , Subtarget ) ; case X86ISD :: CMOV : return PerformCMOVCombine ( N , DAG , DCI ) ; case ISD :: MUL : return PerformMulCombine ( N , DAG , DCI ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DAG , Subtarget ) ; case ISD :: OR : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: STORE : return PerformSTORECombine ( N , DAG , Subtarget ) ; case X86ISD :: FXOR : case X86ISD :: FOR : return PerformFORCombine ( N , DAG ) ; case X86ISD :: FAND : return PerformFANDCombine ( N , DAG ) ; case X86ISD :: BT : return PerformBTCombine ( N , DAG , DCI ) ; case X86ISD :: VZEXT_MOVL : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case ISD :: ZERO_EXTEND : return PerformZExtCombine ( N , DAG ) ; case X86ISD :: SHUFPS : case X86ISD :: SHUFPD : case X86ISD :: PALIGN : case X86ISD :: PUNPCKHBW : case X86ISD :: PUNPCKHWD : case X86ISD :: PUNPCKHDQ : case X86ISD :: PUNPCKHQDQ : case X86ISD :: UNPCKHPS : case X86ISD :: UNPCKHPD : case X86ISD :: PUNPCKLBW : case X86ISD :: PUNPCKLWD : case X86ISD :: PUNPCKLDQ : case X86ISD :: PUNPCKLQDQ : case X86ISD :: UNPCKLPS : case X86ISD :: UNPCKLPD : case X86ISD :: MOVHLPS : case X86ISD :: MOVLHPS : case X86ISD :: PSHUFD : case X86ISD :: PSHUFHW : case X86ISD :: PSHUFLW : case X86ISD :: MOVSS : case X86ISD :: MOVSD : case ISD :: VECTOR_SHUFFLE : return PerformShuffleCombine ( N , DAG , * this ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> bool PPCLinuxAsmPrinter :: doFinalization ( Module & M ) { const DataLayout * TD = TM . getDataLayout ( ) ; bool isPPC64 = TD -> getPointerSizeInBits ( ) == 64 ; PPCTargetStreamer & TS = static_cast < PPCTargetStreamer & > ( * OutStreamer . getTargetStreamer ( ) ) ; if ( ! TOC . empty ( ) ) { const MCSectionELF * Section ; if ( isPPC64 ) Section = OutStreamer . getContext ( ) . getELFSection ( ".toc" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; else Section = OutStreamer . getContext ( ) . getELFSection ( ".got2" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; OutStreamer . SwitchSection ( Section ) ; for ( MapVector < MCSymbol * , MCSymbol * > :: iterator I = TOC . begin ( ) , E = TOC . end ( ) ; I != E ; ++ I ) { OutStreamer . EmitLabel ( I -> second ) ; MCSymbol * S = I -> first ; if ( isPPC64 ) TS . emitTCEntry ( * S ) ; else OutStreamer . EmitSymbolValue ( S , 4 ) ; } } MachineModuleInfoELF & MMIELF = MMI -> getObjFileInfo < MachineModuleInfoELF > ( ) ; MachineModuleInfoELF :: SymbolListTy Stubs = MMIELF . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> static void ix86_emit_save_reg_using_mov ( machine_mode mode , unsigned int regno , HOST_WIDE_INT cfa_offset ) { struct machine_function * m = cfun -> machine ; rtx reg = gen_rtx_REG ( mode , regno ) ; rtx mem , addr , base , insn ; unsigned int align = GET_MODE_ALIGNMENT ( mode ) ; addr = choose_baseaddr ( cfa_offset , & align ) ; mem = gen_frame_mem ( mode , addr ) ; align = MIN ( GET_MODE_ALIGNMENT ( mode ) , align ) ; gcc_assert ( ! ( cfa_offset & ( align / BITS_PER_UNIT - 1 ) ) ) ; set_mem_align ( mem , align ) ; insn = emit_insn ( gen_rtx_SET ( mem , reg ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; base = addr ; if ( GET_CODE ( base ) == PLUS ) base = XEXP ( base , 0 ) ; gcc_checking_assert ( REG_P ( base ) ) ; if ( m -> fs . realigned ) { gcc_checking_assert ( stack_realign_drap ) ; if ( regno == REGNO ( crtl -> drap_reg ) ) { gcc_checking_assert ( cfun -> machine -> fs . fp_valid ) ; addr = plus_constant ( Pmode , hard_frame_pointer_rtx , cfun -> machine -> fs . fp_offset - cfa_offset ) ; mem = gen_rtx_MEM ( mode , addr ) ; add_reg_note ( insn , REG_CFA_DEF_CFA , mem ) ; } else { gcc_checking_assert ( cfun -> machine -> fs . fp_valid ) ; addr = plus_constant ( Pmode , hard_frame_pointer_rtx , cfun -> machine -> fs . fp_offset - cfa_offset ) ; mem = gen_rtx_MEM ( mode , addr ) ; add_reg_note ( insn , REG_CFA_EXPRESSION , gen_rtx_SET ( mem , reg ) ) ; } } else if ( base == stack_pointer_rtx && m -> fs . sp_realigned && cfa_offset >= m -> fs . sp_realigned_offset ) { gcc_checking_assert ( stack_realign_fp ) ; add_reg_note ( insn , REG_CFA_EXPRESSION , gen_rtx_SET ( mem , reg ) ) ; } else if ( base != m -> fs . cfa_reg ) { addr = plus_constant ( Pmode , m -> fs . cfa_reg , m -> fs . cfa_offset - cfa_offset ) ; mem = gen_rtx_MEM ( mode , addr ) ; add_reg_note ( insn , REG_CFA_OFFSET , gen_rtx_SET ( mem , reg ) ) ; } } </s>

Emit a single register save at CFA - CFA_OFFSET .


<s> bool AMDGPUAsmParser :: usesConstantBus ( const MCInst & Inst , unsigned OpIdx ) { const MCOperand & MO = Inst . getOperand ( OpIdx ) ; if ( MO . isImm ( ) ) { return ! isInlineConstant ( Inst , OpIdx ) ; } else if ( MO . isReg ( ) ) { auto Reg = MO . getReg ( ) ; const MCRegisterInfo * TRI = getContext ( ) . getRegisterInfo ( ) ; return isSGPR ( mc2PseudoReg ( Reg ) , TRI ) && Reg != SGPR_NULL ; } else { return true ; } } </s>

Returns true if this operand uses the constant bus .


<s> void microblaze_declare_object ( FILE * stream , const char * name , const char * section , const char * fmt , int size ) { fputs ( section , stream ) ; assemble_name ( stream , name ) ; fprintf ( stream , fmt , size ) ; } </s>

Emit either a label , .comm , or .lcomm directive , and mark that the symbol is used , so that we do n't emit an .extern for it in microblaze_asm_file_end .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"SI annotate control flow"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static bool mayAlias ( MachineInstr & MIa , SmallVectorImpl < MachineInstr * > & MemInsns , const AArch64InstrInfo * TII ) { for ( MachineInstr * MIb : MemInsns ) if ( mayAlias ( MIa , * MIb , TII ) ) return true ; return false ; } </s>

Returns true if this instruction 's memory access aliases the memory access of Other .


<s> static bool index_term_p ( rtx prod , machine_mode mode , bool strict ) { rtx xfoo0 , xfoo1 ; bool log_p ; if ( GET_MODE_SIZE ( mode ) == 1 ) return BASE_REGISTER_P ( prod , strict ) ; if ( ( GET_CODE ( prod ) != MULT && GET_CODE ( prod ) != ASHIFT ) || GET_MODE_SIZE ( mode ) > 8 ) return false ; log_p = GET_CODE ( prod ) == ASHIFT ; xfoo0 = XEXP ( prod , 0 ) ; xfoo1 = XEXP ( prod , 1 ) ; if ( CONST_INT_P ( xfoo0 ) && GET_MODE_SIZE ( mode ) == ( log_p ? 1 << INTVAL ( xfoo0 ) : INTVAL ( xfoo0 ) ) && INDEX_REGISTER_P ( xfoo1 , strict ) ) return true ; if ( CONST_INT_P ( xfoo1 ) && GET_MODE_SIZE ( mode ) == ( log_p ? 1 << INTVAL ( xfoo1 ) : INTVAL ( xfoo1 ) ) && INDEX_REGISTER_P ( xfoo0 , strict ) ) return true ; return false ; } </s>

1 if PROD is either a reg times size of mode MODE and MODE is less than or equal 8 bytes , or just a reg if MODE is one byte .


<s>
const
ArrayRef
<
MCPhysReg
>
Cpu0ABIInfo
::
GetByValArgRegs
(
)
const
{
if
(
IsO32
(
)
)
return
makeArrayRef
(
O32IntRegs
)
;
if
(
IsS32
(
)
)
return
makeArrayRef
(
S32IntRegs
)
;
llvm_unreachable
(
"Unhandled ABI"
)
;
}
</s>

The registers to use for byval arguments .


"Constant Island pass failed to converge!"

"Branch Fix Up pass failed to converge!"

runOnMachineFunction - Emit the function body .


<s> static bool rs6000_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { if ( RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p ) { static int recurse = 0 ; if ( DEFAULT_ABI == ABI_V4 && ( TARGET_RELOCATABLE || flag_pic > 1 ) && in_section != toc_section && ! recurse && ! CONST_SCALAR_INT_P ( x ) && CONSTANT_P ( x ) ) { char buf [ 256 ] ; recurse = 1 ; ASM_GENERATE_INTERNAL_LABEL ( buf , "LCP" , fixuplabelno ) ; fixuplabelno ++ ; ASM_OUTPUT_LABEL ( asm_out_file , buf ) ; fprintf ( asm_out_file , "\t.long\t(" ) ; output_addr_const ( asm_out_file , x ) ; fprintf ( asm_out_file , ")@fixup\n" ) ; fprintf ( asm_out_file , "\t.section\t\".fixup\",\"aw\"\n" ) ; ASM_OUTPUT_ALIGN ( asm_out_file , 2 ) ; fprintf ( asm_out_file , "\t.long\t" ) ; assemble_name ( asm_out_file , buf ) ; fprintf ( asm_out_file , "\n\t.previous\n" ) ; recurse = 0 ; return true ; } else if ( GET_CODE ( x ) == SYMBOL_REF && XSTR ( x , 0 ) [ 0 ] == '.' && DEFAULT_ABI == ABI_AIX ) { const char * name = XSTR ( x , 0 ) ; while ( * name == '.' ) name ++ ; fprintf ( asm_out_file , "\t.long\t%s\n" , name ) ; return true ; } } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . The powerpc version has to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP is defined . It also needs to handle DI-mode objects on 64-bit targets .


<s> bool MBlazeTargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ; if ( Kind . isMergeable1ByteCString ( ) ) return false ; Type * Ty = GV -> getType ( ) -> getElementType ( ) ; return IsInSmallSection ( TM . getDataLayout ( ) -> getTypeAllocSize ( Ty ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> static rtx aarch64_simd_dup_constant ( rtx vals ) { machine_mode mode = GET_MODE ( vals ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx x ; if ( ! const_vec_duplicate_p ( vals , & x ) ) return NULL_RTX ; x = copy_to_mode_reg ( inner_mode , x ) ; return gen_rtx_VEC_DUPLICATE ( mode , x ) ; } </s>

If VALS is a vector constant that can be loaded into a register using DUP , generate instructions to do so and return an RTX to assign to the register . Otherwise return NULL_RTX .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
TOY
::
NumTargetFixupKinds
]
=
{
{
"fixup_TOY_CALL"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_TOY_BR"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> bool AArch64FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; return ( MFI -> hasCalls ( ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MFI -> hasStackMap ( ) || MFI -> hasPatchPoint ( ) || RegInfo -> needsStackRealignment ( MF ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> virtual gimple * fold ( gimple_folder & ) const { return NULL ; } </s>

Try to fold the call . Return the new statement on success and null on failure .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineBranchProbabilityInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> std :: pair < uint16_t , uint16_t > X86InstrInfo :: getExecutionDomain ( const MachineInstr & MI ) const { uint16_t domain = ( MI . getDesc ( ) . TSFlags >> X86II :: SSEDomainShift ) & 3 ; unsigned opcode = MI . getOpcode ( ) ; uint16_t validDomains = 0 ; if ( domain ) { if ( lookup ( MI . getOpcode ( ) , domain , ReplaceableInstrs ) ) { validDomains = 0xe ; } else if ( lookup ( opcode , domain , ReplaceableInstrsAVX2 ) ) { validDomains = Subtarget . hasAVX2 ( ) ? 0xe : 0x6 ; } else if ( lookup ( opcode , domain , ReplaceableInstrsAVX2InsertExtract ) ) { if ( ! Subtarget . hasAVX2 ( ) ) return std :: make_pair ( 0 , 0 ) ; validDomains = 0xe ; } else if ( lookupAVX512 ( opcode , domain , ReplaceableInstrsAVX512 ) ) { validDomains = 0xe ; } else if ( Subtarget . hasDQI ( ) && lookupAVX512 ( opcode , domain , ReplaceableInstrsAVX512DQ ) ) { validDomains = 0xe ; } else if ( Subtarget . hasDQI ( ) ) { if ( const uint16_t * table = lookupAVX512 ( opcode , domain , ReplaceableInstrsAVX512DQMasked ) ) { if ( domain == 1 || ( domain == 3 && table [ 3 ] == opcode ) ) validDomains = 0xa ; else validDomains = 0xc ; } } } return std :: make_pair ( domain , validDomains ) ; } </s>

Return the current execution domain and bit mask of possible domains for instruction .


<s>
void
HexagonFrameLowering
::
processFunctionBeforeFrameFinalized
(
MachineFunction
&
MF
,
RegScavenger
*
RS
)
const
{
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
bool
HasAlloca
=
MFI
.
hasVarSizedObjects
(
)
;
bool
NeedsAlign
=
(
MFI
.
getMaxAlign
(
)
>
getStackAlign
(
)
)
;
if
(
!
HasAlloca
||
!
NeedsAlign
)
return
;
SmallSet
<
int
,
4
>
DealignSlots
;
unsigned
LFS
=
MFI
.
getLocalFrameSize
(
)
;
for
(
int
i
=
0
,
e
=
MFI
.
getObjectIndexEnd
(
)
;
i
!=
e
;
++
i
)
{
if
(
!
MFI
.
isSpillSlotObjectIndex
(
i
)
||
MFI
.
isDeadObjectIndex
(
i
)
)
continue
;
unsigned
S
=
MFI
.
getObjectSize
(
i
)
;
Align
A
=
std
::
max
(
MFI
.
getObjectAlign
(
i
)
,
Align
(
8
)
)
;
MFI
.
setObjectAlignment
(
i
,
Align
(
8
)
)
;
LFS
=
alignTo
(
LFS
+
S
,
A
)
;
MFI
.
mapLocalFrameObject
(
i
,
static_cast
<
int64_t
>
(
LFS
)
)
;
DealignSlots
.
insert
(
i
)
;
}
MFI
.
setLocalFrameSize
(
LFS
)
;
Align
A
=
MFI
.
getLocalFrameMaxAlign
(
)
;
assert
(
A
<=
8
&&
"Unexpected local frame alignment"
)
;
if
(
A
==
1
)
MFI
.
setLocalFrameMaxAlign
(
Align
(
8
)
)
;
MFI
.
setUseLocalStackAllocationBlock
(
true
)
;
if
(
!
DealignSlots
.
empty
(
)
)
{
for
(
MachineBasicBlock
&
BB
:
MF
)
{
for
(
MachineInstr
&
MI
:
BB
)
{
bool
KeepOld
=
true
;
ArrayRef
<
MachineMemOperand
*
>
memops
=
MI
.
memoperands
(
)
;
SmallVector
<
MachineMemOperand
*
,
1
>
new_memops
;
for
(
MachineMemOperand
*
MMO
:
memops
)
{
auto
*
PV
=
MMO
->
getPseudoValue
(
)
;
if
(
auto
*
FS
=
dyn_cast_or_null
<
FixedStackPseudoSourceValue
>
(
PV
)
)
{
int
FI
=
FS
->
getFrameIndex
(
)
;
if
(
DealignSlots
.
count
(
FI
)
)
{
auto
*
NewMMO
=
MF
.
getMachineMemOperand
(
MMO
->
getPointerInfo
(
)
,
MMO
->
getFlags
(
)
,
MMO
->
getSize
(
)
,
MFI
.
getObjectAlign
(
FI
)
,
MMO
->
getAAInfo
(
)
,
MMO
->
getRanges
(
)
,
MMO
->
getSyncScopeID
(
)
,
MMO
->
getOrdering
(
)
,
MMO
->
getFailureOrdering
(
)
)
;
new_memops
.
push_back
(
NewMMO
)
;
KeepOld
=
false
;
continue
;
}
}
new_memops
.
push_back
(
MMO
)
;
}
if
(
!
KeepOld
)
MI
.
setMemRefs
(
MF
,
new_memops
)
;
}
}
}
unsigned
AP
=
0
;
if
(
const
MachineInstr
*
AI
=
getAlignaInstr
(
MF
)
)
AP
=
AI
->
getOperand
(
0
)
.
getReg
(
)
;
auto
&
HMFI
=
*
MF
.
getInfo
<
HexagonMachineFunctionInfo
>
(
)
;
HMFI
.
setStackAlignBasePhysReg
(
AP
)
;
}
</s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> bool DCPU16FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ; } </s>


<s> bool mprocPassConfig :: addInstSelector ( ) { addPass ( createmprocISelDag ( getmprocTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> MCSymbol * X86AsmPrinter :: GetCPISymbol ( unsigned CPID ) const { if ( Subtarget -> isTargetKnownWindowsMSVC ( ) ) { const MachineConstantPoolEntry & CPE = MF -> getConstantPool ( ) -> getConstants ( ) [ CPID ] ; if ( ! CPE . isMachineConstantPoolEntry ( ) ) { SectionKind Kind = CPE . getSectionKind ( TM . getDataLayout ( ) ) ; const Constant * C = CPE . Val . ConstVal ; const MCSectionCOFF * S = cast < MCSectionCOFF > ( getObjFileLowering ( ) . getSectionForConstant ( Kind , C ) ) ; if ( MCSymbol * Sym = S -> getCOMDATSymbol ( ) ) { if ( Sym -> isUndefined ( ) ) OutStreamer . EmitSymbolAttribute ( Sym , MCSA_Global ) ; return Sym ; } } } return AsmPrinter :: GetCPISymbol ( CPID ) ; } </s>

Return the symbol for the specified constant pool entry .


<s> void PPCDAGToDAGISel :: PostprocessISelDAG ( ) { if ( TM . getOptLevel ( ) == CodeGenOpt :: None ) return ; PeepholePPC64 ( ) ; PeepholeCROps ( ) ; PeepholePPC64ZExt ( ) ; } </s>

PostprocessISelDAG ( ) - This hook allows the target to hack on the graph right after selection .


<s> unsigned Cpu0MachineFunctionInfo :: getGlobalBaseReg ( ) { return GlobalBaseReg = Cpu0 :: GP ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> void M68kIncomingValueHandler :: assignValueToReg ( Register ValVReg , Register PhysReg , CCValAssign & VA ) { MIRBuilder . getMRI ( ) -> addLiveIn ( PhysReg ) ; MIRBuilder . getMBB ( ) . addLiveIn ( PhysReg ) ; IncomingValueHandler :: assignValueToReg ( ValVReg , PhysReg , VA ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> void MINA32MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; uint64_t Binary = getBinaryCodeForInstr ( MI , Fixups , STI ) ; support :: endian :: write < uint32_t > ( OS , Binary , support :: little ) ; ++ MCNumEmitted ; } </s>

Encode the given Inst to bytes and append to CB .