<s> const char * PPCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case PPCISD :: FSEL : return "PPCISD::FSEL" ; case PPCISD :: FCFID : return "PPCISD::FCFID" ; case PPCISD :: FCTIDZ : return "PPCISD::FCTIDZ" ; case PPCISD :: FCTIWZ : return "PPCISD::FCTIWZ" ; case PPCISD :: STFIWX : return "PPCISD::STFIWX" ; case PPCISD :: VMADDFP : return "PPCISD::VMADDFP" ; case PPCISD :: VNMSUBFP : return "PPCISD::VNMSUBFP" ; case PPCISD :: VPERM : return "PPCISD::VPERM" ; case PPCISD :: Hi : return "PPCISD::Hi" ; case PPCISD :: Lo : return "PPCISD::Lo" ; case PPCISD :: TOC_ENTRY : return "PPCISD::TOC_ENTRY" ; case PPCISD :: TOC_RESTORE : return "PPCISD::TOC_RESTORE" ; case PPCISD :: LOAD : return "PPCISD::LOAD" ; case PPCISD :: LOAD_TOC : return "PPCISD::LOAD_TOC" ; case PPCISD :: DYNALLOC : return "PPCISD::DYNALLOC" ; case PPCISD :: GlobalBaseReg : return "PPCISD::GlobalBaseReg" ; case PPCISD :: SRL : return "PPCISD::SRL" ; case PPCISD :: SRA : return "PPCISD::SRA" ; case PPCISD :: SHL : return "PPCISD::SHL" ; case PPCISD :: EXTSW_32 : return "PPCISD::EXTSW_32" ; case PPCISD :: STD_32 : return "PPCISD::STD_32" ; case PPCISD :: CALL_SVR4 : return "PPCISD::CALL_SVR4" ; case PPCISD :: CALL_NOP_SVR4 : return "PPCISD::CALL_NOP_SVR4" ; case PPCISD :: CALL_Darwin : return "PPCISD::CALL_Darwin" ; case PPCISD :: NOP : return "PPCISD::NOP" ; case PPCISD :: MTCTR : return "PPCISD::MTCTR" ; case PPCISD :: BCTRL_Darwin : return "PPCISD::BCTRL_Darwin" ; case PPCISD :: BCTRL_SVR4 : return "PPCISD::BCTRL_SVR4" ; case PPCISD :: RET_FLAG : return "PPCISD::RET_FLAG" ; case PPCISD :: MFCR : return "PPCISD::MFCR" ; case PPCISD :: VCMP : return "PPCISD::VCMP" ; case PPCISD :: VCMPo : return "PPCISD::VCMPo" ; case PPCISD :: LBRX : return "PPCISD::LBRX" ; case PPCISD :: STBRX : return "PPCISD::STBRX" ; case PPCISD :: LARX : return "PPCISD::LARX" ; case PPCISD :: STCX : return "PPCISD::STCX" ; case PPCISD :: COND_BRANCH : return "PPCISD::COND_BRANCH" ; case PPCISD :: MFFS : return "PPCISD::MFFS" ; case PPCISD :: MTFSB0 : return "PPCISD::MTFSB0" ; case PPCISD :: MTFSB1 : return "PPCISD::MTFSB1" ; case PPCISD :: FADDRTZ : return "PPCISD::FADDRTZ" ; case PPCISD :: MTFSF : return "PPCISD::MTFSF" ; case PPCISD :: TC_RETURN : return "PPCISD::TC_RETURN" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s>
bool
AMDGPUOpenCLEnqueuedBlockLowering
::
runOnModule
(
Module
&
M
)
{
DenseSet
<
Function
*
>
Callers
;
auto
&
C
=
M
.
getContext
(
)
;
bool
Changed
=
false
;
for
(
auto
&
F
:
M
.
functions
(
)
)
{
if
(
F
.
hasFnAttribute
(
"enqueued-block"
)
)
{
if
(
!
F
.
hasName
(
)
)
{
SmallString
<
64
>
Name
;
Mangler
::
getNameWithPrefix
(
Name
,
"__amdgpu_enqueued_kernel"
,
M
.
getDataLayout
(
)
)
;
F
.
setName
(
Name
)
;
}
DEBUG
(
dbgs
(
)
<<
"found enqueued kernel: "
<<
F
.
getName
(
)
<<
'\n'
)
;
auto
RuntimeHandle
=
(
F
.
getName
(
)
+
".runtime_handle"
)
.
str
(
)
;
auto
T
=
Type
::
getInt8Ty
(
C
)
->
getPointerTo
(
AMDGPUAS
::
GLOBAL_ADDRESS
)
;
auto
*
GV
=
new
GlobalVariable
(
M
,
T
,
false
,
GlobalValue
::
ExternalLinkage
,
Constant
::
getNullValue
(
T
)
,
RuntimeHandle
,
nullptr
,
GlobalValue
::
NotThreadLocal
,
AMDGPUAS
::
GLOBAL_ADDRESS
,
false
)
;
DEBUG
(
dbgs
(
)
<<
"runtime handle created: "
<<
*
GV
<<
'\n'
)
;
for
(
auto
U
:
F
.
users
(
)
)
{
auto
*
UU
=
&
*
U
;
if
(
!
isa
<
ConstantExpr
>
(
UU
)
)
continue
;
collectFunctionUsers
(
UU
,
Callers
)
;
auto
*
BitCast
=
cast
<
ConstantExpr
>
(
UU
)
;
auto
*
NewPtr
=
ConstantExpr
::
getPointerCast
(
GV
,
BitCast
->
getType
(
)
)
;
BitCast
->
replaceAllUsesWith
(
NewPtr
)
;
F
.
addFnAttr
(
"runtime-handle"
,
RuntimeHandle
)
;
F
.
setLinkage
(
GlobalValue
::
ExternalLinkage
)
;
Changed
=
true
;
}
}
}
for
(
auto
F
:
Callers
)
{
if
(
F
->
getCallingConv
(
)
!=
CallingConv
::
AMDGPU_KERNEL
)
continue
;
F
->
addFnAttr
(
"calls-enqueue-kernel"
)
;
DEBUG
(
dbgs
(
)
<<
"mark enqueue_kernel caller:"
<<
F
->
getName
(
)
<<
'\n'
)
;
}
return
Changed
;
}
</s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .

AMDGPU
AMDGPU
"enqueued-block"
64
"__amdgpu_enqueued_kernel"
"found enqueued kernel: "
".runtime_handle"
AMDGPU
AMDGPU
"runtime handle created: "
"runtime-handle"
AMDGPU
"calls-enqueue-kernel"
"mark enqueue_kernel caller:"


<s>
SDValue
M68kTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
SADDO
:
case
ISD
::
UADDO
:
case
ISD
::
SSUBO
:
case
ISD
::
USUBO
:
case
ISD
::
SMULO
:
case
ISD
::
UMULO
:
return
LowerXALUO
(
Op
,
DAG
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
case
ISD
::
SETCCCARRY
:
return
LowerSETCCCARRY
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
LowerSELECT
(
Op
,
DAG
)
;
case
ISD
::
BRCOND
:
return
LowerBRCOND
(
Op
,
DAG
)
;
case
ISD
::
ADDC
:
case
ISD
::
ADDE
:
case
ISD
::
SUBC
:
case
ISD
::
SUBE
:
return
LowerADDC_ADDE_SUBC_SUBE
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
ExternalSymbol
:
return
LowerExternalSymbol
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
SHL_PARTS
:
return
LowerShiftLeftParts
(
Op
,
DAG
)
;
case
ISD
::
SRA_PARTS
:
return
LowerShiftRightParts
(
Op
,
DAG
,
true
)
;
case
ISD
::
SRL_PARTS
:
return
LowerShiftRightParts
(
Op
,
DAG
,
false
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

M68k
M68k
"Should not custom lower this!"
ISD::SADDO
ISD::UADDO
ISD::SSUBO
ISD::USUBO
ISD::SMULO
ISD::UMULO
ISD::SETCC
ISD::SETCCCARRY
ISD::SELECT
ISD::BRCOND
ISD::ADDC
ISD::ADDE
ISD::SUBC
ISD::SUBE
ISD::ConstantPool
ISD::GlobalAddress
ISD::ExternalSymbol
ISD::BlockAddress
ISD::JumpTable
ISD::VASTART
ISD::DYNAMIC_STACKALLOC
ISD::SHL_PARTS
ISD::SRA_PARTS
ISD::SRL_PARTS


<s> void Z80oldInstPrinterBase :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << markup ( "<reg:" ) << getRegName ( RegNo ) << markup ( ">" ) ; } </s>


<s> unsigned VEInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . getOpcode ( ) == VE :: LDrii || MI . getOpcode ( ) == VE :: LDLSXrii || MI . getOpcode ( ) == VE :: LDUrii ) { if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 && MI . getOperand ( 3 ) . isImm ( ) && MI . getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> unsigned getNumFixupKinds ( ) const override { return AMDGPU :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> static const char * rs6000_mangle_fundamental_type ( tree type ) { if ( type == bool_char_type_node ) return "U6__boolc" ; if ( type == bool_short_type_node ) return "U6__bools" ; if ( type == pixel_type_node ) return "u7__pixel" ; if ( type == bool_int_type_node ) return "U6__booli" ; if ( TYPE_MAIN_VARIANT ( type ) == long_double_type_node && TARGET_ELF && TARGET_LONG_DOUBLE_128 && ! TARGET_IEEEQUAD ) return "g" ; return NULL ; } </s>

AltiVec defines four built-in scalar types that serve as vector elements ; we must teach the compiler how to mangle them .


<s> static void or1k_tls_call ( rtx dest , rtx arg ) { emit_library_call_value ( gen_tls_get_addr ( ) , dest , LCT_CONST , Pmode , arg , Pmode ) ; } </s>


<s> bool sh_can_use_simple_return_p ( void ) { HARD_REG_SET live_regs_mask ; int d ; if ( TARGET_SHMEDIA || ( TARGET_SHCOMPACT && ( crtl -> args . info . call_cookie & CALL_COOKIE_RET_TRAMP ( 1 ) ) ) ) return false ; if ( ! reload_completed || frame_pointer_needed ) return false ; if ( optimize_function_for_size_p ( cfun ) ) return false ; d = calc_live_regs ( & live_regs_mask ) ; if ( rounded_frame_size ( d ) > 4 ) return false ; return true ; } </s>

Return true if it is appropriate to emit ` ret ' instructions in the body of a function .


<s> void RISCVFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> void MINA32InstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & O ) { if ( ! printAliasInstr ( MI , Address , O ) ) printInstruction ( MI , Address , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool fp_one_operand ( rtx op ) { REAL_VALUE_TYPE r ; if ( GET_MODE ( op ) != SFmode ) return false ; REAL_VALUE_FROM_CONST_DOUBLE ( r , op ) ; return REAL_VALUES_EQUAL ( r , dconst1 ) ; } </s>

Nonzero if OP is a floating point value with value 1.0 .


<s>
bool
ARMBlockPlacement
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
const
ARMSubtarget
&
ST
=
static_cast
<
const
ARMSubtarget
&
>
(
MF
.
getSubtarget
(
)
)
;
if
(
!
ST
.
hasLOB
(
)
)
return
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
DEBUG_PREFIX
<<
"Running on "
<<
MF
.
getName
(
)
<<
"\n"
)
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
TII
=
static_cast
<
const
ARMBaseInstrInfo
*
>
(
ST
.
getInstrInfo
(
)
)
;
BBUtils
=
std
::
unique_ptr
<
ARMBasicBlockUtils
>
(
new
ARMBasicBlockUtils
(
MF
)
)
;
MF
.
RenumberBlocks
(
)
;
BBUtils
->
computeAllBlockSizes
(
)
;
BBUtils
->
adjustBBOffsetsAfter
(
&
MF
.
front
(
)
)
;
bool
Changed
=
false
;
for
(
auto
*
ML
:
*
MLI
)
Changed
|=
processPostOrderLoops
(
ML
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

ARM
ARM
ARM
ARM
"Running on "
"\n"
ARM
ARM
ARM


<s> static const __EIT_entry * search_EIT_table ( const __EIT_entry * table , int nrec , _uw return_address ) { _uw next_fn ; _uw this_fn ; int n , left , right ; if ( nrec == 0 ) return ( __EIT_entry * ) 0 ; left = 0 ; right = nrec - 1 ; while ( 1 ) { n = ( left + right ) / 2 ; this_fn = selfrel_offset31 ( & table [ n ] . fnoffset ) ; if ( n != nrec - 1 ) next_fn = selfrel_offset31 ( & table [ n + 1 ] . fnoffset ) - 1 ; else next_fn = ( _uw ) 0 - 1 ; if ( return_address < this_fn ) { if ( n == left ) return ( __EIT_entry * ) 0 ; right = n - 1 ; } else if ( return_address <= next_fn ) return & table [ n ] ; else left = n + 1 ; } } </s>

Perform a binary search for RETURN_ADDRESS in TABLE . The table contains NREC entries .


"SystemZ DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> bool PatmosInstrInfo :: isPredicated ( const MachineInstr * MI ) const { if ( MI -> isBundle ( ) ) { MachineBasicBlock :: const_instr_iterator II = MI ; while ( II -> isBundledWithSucc ( ) ) { ++ II ; if ( isPredicated ( & * II ) ) return true ; } return false ; } int i = MI -> findFirstPredOperandIdx ( ) ; if ( i != - 1 ) { unsigned preg = MI -> getOperand ( i ) . getReg ( ) ; int flag = MI -> getOperand ( ++ i ) . getImm ( ) ; return ( preg != Patmos :: NoRegister && preg != Patmos :: P0 ) || flag ; } return false ; } </s>

Returns true if the instruction is already predicated .


<s> static rtx c6x_struct_value_rtx ( tree type ATTRIBUTE_UNUSED , int incoming ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( Pmode , REG_A3 ) ; } </s>


<s> MVT AArch64TargetLowering :: getScalarShiftAmountTy ( EVT LHSTy ) const { return MVT :: i64 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> MCObjectWriter * WebAssemblyAsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { return createWebAssemblyWasmObjectWriter ( OS , Is64Bit ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> EVT PPCTargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


"failed to allocated VGPR for implicit arguments"

Allocate implicit function VGPR arguments in fixed registers .


<s> bool rs6000_emit_set_const ( rtx dest , rtx source ) { machine_mode mode = GET_MODE ( dest ) ; rtx temp , set ; rtx_insn * insn ; HOST_WIDE_INT c ; gcc_checking_assert ( CONST_INT_P ( source ) ) ; c = INTVAL ( source ) ; switch ( mode ) { case E_QImode : case E_HImode : emit_insn ( gen_rtx_SET ( dest , source ) ) ; return true ; case E_SImode : temp = ! can_create_pseudo_p ( ) ? dest : gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( copy_rtx ( temp ) , GEN_INT ( c & ~ ( HOST_WIDE_INT ) 0xffff ) ) ) ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_IOR ( SImode , copy_rtx ( temp ) , GEN_INT ( c & 0xffff ) ) ) ) ; break ; case E_DImode : if ( ! TARGET_POWERPC64 ) { rtx hi , lo ; hi = operand_subword_force ( copy_rtx ( dest ) , WORDS_BIG_ENDIAN == 0 , DImode ) ; lo = operand_subword_force ( dest , WORDS_BIG_ENDIAN != 0 , DImode ) ; emit_move_insn ( hi , GEN_INT ( c >> 32 ) ) ; c = ( ( c & 0xffffffff ) ^ 0x80000000 ) - 0x80000000 ; emit_move_insn ( lo , GEN_INT ( c ) ) ; } else rs6000_emit_set_long_const ( dest , c ) ; break ; default : gcc_unreachable ( ) ; } insn = get_last_insn ( ) ; set = single_set ( insn ) ; if ( ! CONSTANT_P ( SET_SRC ( set ) ) ) set_unique_reg_note ( insn , REG_EQUAL , GEN_INT ( c ) ) ; return true ; } </s>

Try to output insns to set TARGET equal to the constant C if it can be done in less than N insns . Do all computations in MODE . Returns the place where the output has been placed if it can be done and the insns have been emitted . If it would take more than N insns , zero is returned and no insns and emitted .


<s> void crx_function_arg_advance ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int named ATTRIBUTE_UNUSED ) { int l = GET_MODE_BITSIZE ( mode ) / BITS_PER_WORD ; if ( ! last_parm_in_reg ) return ; if ( targetm . calls . must_pass_in_stack ( mode , type ) || ( cum -> ints < 0 ) ) return ; if ( mode == SImode || mode == HImode || mode == QImode || mode == DImode ) { if ( l <= 1 ) cum -> ints += 1 ; else cum -> ints += l ; } else if ( mode == SFmode || mode == DFmode ) cum -> ints += l ; else if ( ( mode ) == BLKmode ) { if ( ( l = enough_regs_for_param ( cum , type , mode ) ) != 0 ) cum -> ints += l ; } } </s>

Implements the macro FUNCTION_ARG_ADVANCE defined in crx.h .


"WebAssembly Lower Emscripten Exceptions"


<s> static void union_defs ( swap_web_entry * insn_entry , rtx insn , df_ref use ) { struct df_link * link = DF_REF_CHAIN ( use ) ; if ( ! link ) insn_entry [ INSN_UID ( insn ) ] . is_live_in = 1 ; while ( link ) { if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) insn_entry [ INSN_UID ( insn ) ] . is_live_in = 1 ; if ( DF_REF_INSN_INFO ( link -> ref ) ) { rtx def_insn = DF_REF_INSN ( link -> ref ) ; ( void ) unionfind_union ( insn_entry + INSN_UID ( insn ) , insn_entry + INSN_UID ( def_insn ) ) ; } link = link -> next ; } } </s>

Union INSN with all insns containing definitions that reach USE . Detect whether USE is live-in to the current function .


<s>
SDValue
RISCVTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
if
(
IsVarArg
)
{
report_fatal_error
(
"VarArg not supported"
)
;
}
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
analyzeOutputArgs
(
DAG
.
getMachineFunction
(
)
,
CCInfo
,
Outs
,
true
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
<
e
;
++
i
)
{
SDValue
Val
=
OutVals
[
i
]
;
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
assert
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
Full
&&
"Unexpected CCValAssign::LocInfo"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
Val
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
{
RetOps
.
push_back
(
Flag
)
;
}
return
DAG
.
getNode
(
RISCVISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool SystemZMCAsmBackend :: shouldForceRelocation ( const MCAssembler & , const MCFixup & Fixup , const MCValue & ) { return Fixup . getKind ( ) >= FirstLiteralRelocationKind ; } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> BTFTypeStruct :: BTFTypeStruct ( const DICompositeType * STy , bool IsStruct , bool HasBitField , uint32_t Vlen ) : STy ( STy ) , HasBitField ( HasBitField ) { Kind = IsStruct ? BTF :: BTF_KIND_STRUCT : BTF :: BTF_KIND_UNION ; BTFType . Size = roundupToBytes ( STy -> getSizeInBits ( ) ) ; BTFType . Info = ( HasBitField << 31 ) | ( Kind << 24 ) | Vlen ; } </s>


<s> static unsigned long arm_compute_save_reg0_reg12_mask ( ) { unsigned long func_type = arm_current_func_type ( ) ; unsigned int save_reg_mask = 0 ; unsigned int reg ; if ( IS_INTERRUPT ( func_type ) ) { unsigned int max_reg ; if ( ARM_FUNC_TYPE ( func_type ) == ARM_FT_FIQ ) max_reg = 7 ; else max_reg = 12 ; for ( reg = 0 ; reg <= max_reg ; reg ++ ) if ( regs_ever_live [ reg ] || ( ! current_function_is_leaf && call_used_regs [ reg ] ) ) save_reg_mask |= ( 1 << reg ) ; } else { for ( reg = 0 ; reg <= 10 ; reg ++ ) if ( regs_ever_live [ reg ] && ! call_used_regs [ reg ] ) save_reg_mask |= ( 1 << reg ) ; if ( ! TARGET_APCS_FRAME && ! frame_pointer_needed && regs_ever_live [ HARD_FRAME_POINTER_REGNUM ] && ! call_used_regs [ HARD_FRAME_POINTER_REGNUM ] ) save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM ; if ( flag_pic && ! TARGET_SINGLE_PIC_BASE && regs_ever_live [ PIC_OFFSET_TABLE_REGNUM ] ) save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM ; } return save_reg_mask ; } </s>

Compute the register save mask for registers 0 through 12 inclusive . This code is used by arm_compute_save_reg_mask .


<s> static void rs6000_elf_asm_init_sections ( void ) { toc_section = get_unnamed_section ( 0 , rs6000_elf_output_toc_section_asm_op , NULL ) ; sdata2_section = get_unnamed_section ( SECTION_WRITE , output_section_asm_op , SDATA2_SECTION_ASM_OP ) ; } </s>


<s> static inline void aarch64_sub_sp ( int scratchreg , HOST_WIDE_INT delta , bool frame_related_p ) { aarch64_add_constant_internal ( Pmode , SP_REGNUM , scratchreg , - delta , frame_related_p , true ) ; } </s>

Subtract DELTA from the stack pointer , marking the instructions frame-related if FRAME_RELATED_P . TEMP1 is available as a temporary if nonnull .


<s> bool ARM64RegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MFI -> hasVarSizedObjects ( ) && ! hasBasePointer ( MF ) ; } </s>

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 WinAlloca Expander"
;
}
</s>


<s> static const char * csky_mangle_type ( const_tree type ) { if ( TREE_CODE ( type ) == REAL_TYPE && TYPE_PRECISION ( type ) == 16 && TYPE_MAIN_VARIANT ( type ) != float16_type_node ) return "Dh" ; return NULL ; } </s>


<s>
void
NVPTXAsmPrinter
::
emitImplicitDef
(
const
MachineInstr
*
MI
)
const
{
unsigned
RegNo
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
const
TargetRegisterInfo
*
TRI
=
TM
.
getRegisterInfo
(
)
;
if
(
TRI
->
isVirtualRegister
(
RegNo
)
)
{
OutStreamer
.
AddComment
(
Twine
(
"implicit-def: "
)
+
getVirtualRegisterName
(
RegNo
)
)
;
}
else
{
OutStreamer
.
AddComment
(
Twine
(
"implicit-def: "
)
+
TM
.
getRegisterInfo
(
)
->
getName
(
RegNo
)
)
;
}
OutStreamer
.
AddBlankLine
(
)
;
}
</s>

Targets can override this to customize the output of IMPLICIT_DEF instructions in verbose mode .

NVPTX
NVPTX
0
"implicit-def: "
"implicit-def: "


"CFProtection used on invalid architecture!"

This virtual method can be overridden by targets that want to emit something at the start of their file .


<s> unsigned TeeRISCInstrInfo :: getGlobalBaseReg ( MachineFunction * MF ) const { TeeRISCMachineFunctionInfo * TeeRISCFI = MF -> getInfo < TeeRISCMachineFunctionInfo > ( ) ; unsigned GlobalBaseReg = TeeRISCFI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg != 0 ) return GlobalBaseReg ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; GlobalBaseReg = RegInfo . createVirtualRegister ( & TeeRISC :: IntRegsRegClass ) ; DebugLoc dl ; BuildMI ( FirstMBB , MBBI , dl , get ( TeeRISC :: ADD ) , GlobalBaseReg ) . addReg ( TeeRISC :: R10 ) ; RegInfo . addLiveIn ( TeeRISC :: R10 ) ; TeeRISCFI -> setGlobalBaseReg ( GlobalBaseReg ) ; return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

TeeRISC TeeRISC TeeRISC TeeRISC TeeRISC TeeRISC 0 TeeRISC::IntRegsRegClass TeeRISC::ADD TeeRISC::R10 TeeRISC::R10 TeeRISC


<s> void HexagonFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { auto & HST = MF . getSubtarget < HexagonSubtarget > ( ) ; auto & HRI = * HST . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; MachineBasicBlock * PrologB = & MF . front ( ) , * EpilogB = nullptr ; if ( EnableShrinkWrapping ) findShrunkPrologEpilog ( MF , PrologB , EpilogB ) ; bool PrologueStubs = false ; insertCSRSpillsInBlock ( * PrologB , CSI , HRI , PrologueStubs ) ; insertPrologueInBlock ( * PrologB , PrologueStubs ) ; updateEntryPaths ( MF , * PrologB ) ; if ( EpilogB ) { insertCSRRestoresInBlock ( * EpilogB , CSI , HRI ) ; insertEpilogueInBlock ( * EpilogB ) ; } else { for ( auto & B : MF ) if ( B . isReturnBlock ( ) ) insertCSRRestoresInBlock ( B , CSI , HRI ) ; for ( auto & B : MF ) if ( B . isReturnBlock ( ) ) insertEpilogueInBlock ( B ) ; for ( auto & B : MF ) { if ( B . empty ( ) ) continue ; MachineInstr * RetI = getReturn ( B ) ; if ( ! RetI || isRestoreCall ( RetI -> getOpcode ( ) ) ) continue ; for ( auto & R : CSI ) RetI -> addOperand ( MachineOperand :: CreateReg ( R . getReg ( ) , false , true ) ) ; } } if ( EpilogB ) { unsigned MaxBN = MF . getNumBlockIDs ( ) ; BitVector DoneT ( MaxBN + 1 ) , DoneF ( MaxBN + 1 ) , Path ( MaxBN + 1 ) ; updateExitPaths ( * EpilogB , * EpilogB , DoneT , DoneF , Path ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> void MSP430InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O ) { printInstruction ( MI , O ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> rtx nds32_legitimize_ict_address ( rtx x ) { rtx symbol = x ; rtx addr = x ; rtx reg = gen_reg_rtx ( Pmode ) ; gcc_assert ( GET_CODE ( x ) == SYMBOL_REF && nds32_indirect_call_referenced_p ( x ) ) ; addr = gen_rtx_UNSPEC ( SImode , gen_rtvec ( 1 , symbol ) , UNSPEC_ICT ) ; addr = gen_rtx_CONST ( SImode , addr ) ; emit_insn ( gen_sethi ( reg , addr ) ) ; x = gen_const_mem ( SImode , gen_rtx_LO_SUM ( Pmode , reg , addr ) ) ; return x ; } </s>

Expand ICT symbol . Example for @ ICT and ICT model=large : la $ r0 , symbol @ ICT - > sethi $ rt , hi20 ( symbol @ ICT ) lwi $ r0 , [ $ rt + lo12 ( symbol @ ICT ) ]


"MIa must load from or modify a memory location"

"MIb must load from or modify a memory location"

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCRelaxableFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
override
{
assert
(
0
&&
"RelaxInstruction() unimplemented"
)
;
return
false
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .

Mips
0
"RelaxInstruction() unimplemented"


<s> static bool ix86_function_value_regno_p ( const unsigned int regno ) { switch ( regno ) { case AX_REG : return true ; case DX_REG : return ( ! TARGET_64BIT || ix86_abi != MS_ABI ) ; case DI_REG : case SI_REG : return TARGET_64BIT && ix86_abi != MS_ABI ; case FIRST_BND_REG : return chkp_function_instrumented_p ( current_function_decl ) ; case ST0_REG : case ST1_REG : if ( TARGET_64BIT && ix86_abi == MS_ABI ) return false ; return TARGET_FLOAT_RETURNS_IN_80387 ; case XMM0_REG : case XMM1_REG : return TARGET_SSE ; case MM0_REG : if ( TARGET_MACHO || TARGET_64BIT ) return false ; return TARGET_MMX ; } return false ; } </s>

Return true if N is a possible register number of function value .


<s> Register getExceptionPointerRegister ( const Constant * PersonalityFn ) const override { return AArch64 :: X0 ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s> static unsigned int h8300_asm_insn_count ( const char * templ ) { unsigned int count = 1 ; for ( ; * templ ; templ ++ ) if ( * templ == '\n' ) count ++ ; return count ; } </s>

Count the number of assembly instructions in a string TEMPLATE .


"inserting int3 after trailing call instruction:\n"

runOnMachineFunction - Emit the function body .


<s> static void nds32_conditional_register_usage ( void ) { int regno ; if ( TARGET_HARD_FLOAT ) { for ( regno = NDS32_FIRST_FPR_REGNUM ; regno <= NDS32_LAST_FPR_REGNUM ; regno ++ ) { fixed_regs [ regno ] = 0 ; if ( regno < NDS32_FIRST_FPR_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS ) call_used_regs [ regno ] = 1 ; else if ( regno >= NDS32_FIRST_FPR_REGNUM + 22 && regno < NDS32_FIRST_FPR_REGNUM + 48 ) call_used_regs [ regno ] = 1 ; else call_used_regs [ regno ] = 0 ; } } else if ( TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE ) { for ( regno = NDS32_FIRST_FPR_REGNUM ; regno <= NDS32_LAST_FPR_REGNUM ; regno ++ ) fixed_regs [ regno ] = 0 ; } } </s>


<s> TargetIRAnalysis X86TargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( Function & F ) { return TargetTransformInfo ( X86TTIImpl ( this , F ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


<s> static bool is_fmul_op ( enum attr_type t ) { return ( t == TYPE_FMULS ) || ( t == TYPE_FMULD ) || ( t == TYPE_NEON_FP_MUL_S ) ; } </s>

Return whether T is the attribute of a FMUL instruction .


<s>
void
M68kTargetLowering
::
LowerAsmOperandForConstraint
(
SDValue
Op
,
std
::
string
&
Constraint
,
std
::
vector
<
SDValue
>
&
Ops
,
SelectionDAG
&
DAG
)
const
{
SDValue
Result
;
if
(
Constraint
.
size
(
)
==
1
)
{
switch
(
Constraint
[
0
]
)
{
case
'I'
:
case
'J'
:
case
'K'
:
case
'L'
:
case
'M'
:
case
'N'
:
case
'O'
:
case
'P'
:
{
auto
*
C
=
dyn_cast
<
ConstantSDNode
>
(
Op
)
;
if
(
!
C
)
return
;
int64_t
Val
=
C
->
getSExtValue
(
)
;
switch
(
Constraint
[
0
]
)
{
case
'I'
:
if
(
Val
>
0
&&
Val
<=
8
)
break
;
return
;
case
'J'
:
if
(
isInt
<
16
>
(
Val
)
)
break
;
return
;
case
'K'
:
if
(
Val
<
0x80
||
Val
>=
0x80
)
break
;
return
;
case
'L'
:
if
(
Val
<
0
&&
Val
>=
8
)
break
;
return
;
case
'M'
:
if
(
Val
<
0x100
||
Val
>=
0x100
)
break
;
return
;
case
'N'
:
if
(
Val
>=
24
&&
Val
<=
31
)
break
;
return
;
case
'O'
:
if
(
Val
==
16
)
break
;
return
;
case
'P'
:
if
(
Val
>=
8
&&
Val
<=
15
)
break
;
return
;
default
:
llvm_unreachable
(
"Unhandled constant constraint"
)
;
}
Result
=
DAG
.
getTargetConstant
(
Val
,
SDLoc
(
Op
)
,
Op
.
getValueType
(
)
)
;
break
;
}
default
:
break
;
}
}
if
(
Constraint
.
size
(
)
==
2
)
{
switch
(
Constraint
[
0
]
)
{
case
'C'
:
switch
(
Constraint
[
1
]
)
{
case
'0'
:
case
'i'
:
case
'j'
:
{
auto
*
C
=
dyn_cast
<
ConstantSDNode
>
(
Op
)
;
if
(
!
C
)
break
;
int64_t
Val
=
C
->
getSExtValue
(
)
;
switch
(
Constraint
[
1
]
)
{
case
'0'
:
if
(
!
Val
)
break
;
return
;
case
'i'
:
break
;
case
'j'
:
if
(
!
isInt
<
16
>
(
C
->
getSExtValue
(
)
)
)
break
;
return
;
default
:
llvm_unreachable
(
"Unhandled constant constraint"
)
;
}
Result
=
DAG
.
getTargetConstant
(
Val
,
SDLoc
(
Op
)
,
Op
.
getValueType
(
)
)
;
break
;
}
default
:
break
;
}
break
;
default
:
break
;
}
}
if
(
Result
.
getNode
(
)
)
{
Ops
.
push_back
(
Result
)
;
return
;
}
TargetLowering
::
LowerAsmOperandForConstraint
(
Op
,
Constraint
,
Ops
,
DAG
)
;
}
</s>

Lower the specified operand into the Ops vector .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( createTLOF ( Triple ( getTargetTriple ( ) ) ) ) , Subtarget ( TT , CPU , FS , * this , LittleEndian ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; } </s>


<s>
rtx_code
m68k_output_compare_fp
(
rtx
op0
,
rtx
op1
,
rtx_code
code
)
{
rtx_code
tmp
=
m68k_find_flags_value
(
op0
,
op1
,
code
)
;
if
(
tmp
!=
UNKNOWN
)
return
tmp
;
rtx
ops
[
2
]
;
ops
[
0
]
=
op0
;
ops
[
1
]
=
op1
;
remember_compare_flags
(
op0
,
op1
)
;
machine_mode
mode
=
GET_MODE
(
op0
)
;
std
::
string
prec
=
mode
==
SFmode
"s"
:
mode
==
DFmode
"d"
:
"x"
;
if
(
op1
==
CONST0_RTX
(
GET_MODE
(
op0
)
)
)
{
if
(
FP_REG_P
(
op0
)
)
{
if
(
TARGET_COLDFIRE_FPU
)
output_asm_insn
(
"ftst%.d %0"
,
ops
)
;
else
output_asm_insn
(
"ftst%.x %0"
,
ops
)
;
}
else
output_asm_insn
(
(
"ftst%."
+
prec
+
" %0"
)
.
c_str
(
)
,
ops
)
;
return
code
;
}
switch
(
which_alternative
)
{
case
0
:
if
(
TARGET_COLDFIRE_FPU
)
output_asm_insn
(
"fcmp%.d %1,%0"
,
ops
)
;
else
output_asm_insn
(
"fcmp%.x %1,%0"
,
ops
)
;
break
;
case
1
:
output_asm_insn
(
(
"fcmp%."
+
prec
+
" %f1,%0"
)
.
c_str
(
)
,
ops
)
;
break
;
case
2
:
output_asm_insn
(
(
"fcmp%."
+
prec
+
" %0,%f1"
)
.
c_str
(
)
,
ops
)
;
std
::
swap
(
flags_compare_op0
,
flags_compare_op1
)
;
return
swap_condition
(
code
)
;
case
3
:
gcc_unreachable
(
)
;
}
return
code
;
}
</s>

Emit a comparison between OP0 and OP1 . CODE is the code of the comparison . It is returned , potentially modified if necessary .


<s> void add ( const SPIRV :: SpecialTypeDescriptor & TD , const MachineFunction * MF , Register R ) { ST . add ( TD , MF , R ) ; } </s>


<s> void AMDGPUPassConfig :: addCodeGenPrepare ( ) { const AMDGPUSubtarget & ST = * getAMDGPUTargetMachine ( ) . getSubtargetImpl ( ) ; if ( ST . isPromoteAllocaEnabled ( ) ) { addPass ( createAMDGPUPromoteAlloca ( ST ) ) ; addPass ( createSROAPass ( ) ) ; } TargetPassConfig :: addCodeGenPrepare ( ) ; } </s>

Add pass to prepare the LLVM IR for code generation .


<s> bool cris_biap_index_p ( const_rtx x , bool strict ) { return ( cris_index_p ( x , strict ) || ( GET_CODE ( x ) == MULT && cris_index_p ( XEXP ( x , 0 ) , strict ) && cris_scale_int_operand ( XEXP ( x , 1 ) , VOIDmode ) ) ) ; } </s>

True if X is a valid ( register ) index for BIAP , i.e . Rd.m .


<s> bool X86TargetLowering :: isFsqrtCheap ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; if ( VT . getScalarType ( ) == MVT :: f16 ) return true ; if ( DAG . getNodeIfExists ( X86ISD :: FRSQRT , DAG . getVTList ( VT ) , Op ) ) return false ; if ( VT . isVector ( ) ) return Subtarget . hasFastVectorFSQRT ( ) ; return Subtarget . hasFastScalarFSQRT ( ) ; } </s>

Return true if SQRT ( X ) should n't be replaced with X * RSQRT ( X ) .


<s> static bool mips_find_gp_ref ( bool * cache , bool ( * pred ) ( rtx_insn * ) ) { rtx_insn * insn ; if ( ! * cache ) { push_topmost_sequence ( ) ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( USEFUL_INSN_P ( insn ) && pred ( insn ) ) { * cache = true ; break ; } pop_topmost_sequence ( ) ; } return * cache ; } </s>

Return true if predicate PRED is true for at least one instruction . Cache the result in * CACHE , and assume that the result is true if * CACHE is already true .


<s> bool doInitialization ( Module & M ) override { CallGraphResourceInfo . clear ( ) ; return ModulePass :: doInitialization ( M ) ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s>
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
Cpu0TargetLowering
::
getRegForInlineAsmConstraint
(
const
TargetRegisterInfo
*
TRI
,
StringRef
Constraint
,
MVT
VT
)
const
{
if
(
Constraint
.
size
(
)
==
1
)
{
switch
(
Constraint
[
0
]
)
{
case
'r'
:
if
(
VT
==
MVT
::
i32
||
VT
==
MVT
::
i16
||
VT
==
MVT
::
i8
)
{
return
std
::
make_pair
(
0U
,
&
Cpu0
::
CPURegsRegClass
)
;
}
if
(
VT
==
MVT
::
i64
)
return
std
::
make_pair
(
0U
,
&
Cpu0
::
CPURegsRegClass
)
;
return
std
::
make_pair
(
0u
,
static_cast
<
const
TargetRegisterClass
*
>
(
0
)
)
;
case
'c'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
(
unsigned
)
Cpu0
::
T9
,
&
Cpu0
::
CPURegsRegClass
)
;
assert
(
"Unexpected type."
)
;
}
}
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
R
;
R
=
parseRegForInlineAsmConstraint
(
Constraint
,
VT
)
;
if
(
R
.
second
)
return
R
;
return
TargetLowering
::
getRegForInlineAsmConstraint
(
TRI
,
Constraint
,
VT
)
;
}
</s>

Given a physical register constraint ( e.g .


"module has aliases, which LLVM does not yet support for AIX"


<s> virtual const InstrItineraryData * getInstrItineraryData ( ) const { return InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> bool ARM64RegisterInfo :: requiresVirtualBaseRegisters ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers used for more efficient stack access .


<s>
void
SystemZInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MBBI
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
SystemZ
::
GR128BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
copyPhysReg
(
MBB
,
MBBI
,
DL
,
RI
.
getSubReg
(
DestReg
,
SystemZ
::
subreg_h64
)
,
RI
.
getSubReg
(
SrcReg
,
SystemZ
::
subreg_h64
)
,
KillSrc
)
;
copyPhysReg
(
MBB
,
MBBI
,
DL
,
RI
.
getSubReg
(
DestReg
,
SystemZ
::
subreg_l64
)
,
RI
.
getSubReg
(
SrcReg
,
SystemZ
::
subreg_l64
)
,
KillSrc
)
;
return
;
}
if
(
SystemZ
::
GRX32BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
emitGRX32Move
(
MBB
,
MBBI
,
DL
,
DestReg
,
SrcReg
,
SystemZ
::
LR
,
32
,
KillSrc
)
;
return
;
}
unsigned
Opcode
;
if
(
SystemZ
::
GR64BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LGR
;
else
if
(
SystemZ
::
FP32BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LER
;
else
if
(
SystemZ
::
FP64BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LDR
;
else
if
(
SystemZ
::
FP128BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LXR
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
Opcode
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> void X86TileConfig :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < LiveIntervals > ( ) ; AU . addPreserved < SlotIndexes > ( ) ; AU . addRequired < VirtRegMap > ( ) ; AU . setPreservesAll ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool RISCVTargetLowering :: shouldSignExtendTypeInLibCall ( EVT Type , bool IsSigned ) const { if ( Subtarget . is64Bit ( ) && Type == MVT :: i32 ) return true ; return IsSigned ; } </s>

Returns true if arguments should be sign-extended in lib calls .


Like arm_compute_initial_elimination offset . Simpler because there is n't an ABI specified frame pointer for Thumb . Instead , we set it to point at the base of the local variables after static stack space for a function has been allocated .


<s> void Thumb2InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { if ( ! ARM :: GPRRegClass . contains ( DestReg , SrcReg ) ) return ARMBaseInstrInfo :: copyPhysReg ( MBB , I , DL , DestReg , SrcReg , KillSrc ) ; BuildMI ( MBB , I , DL , get ( ARM :: tMOVr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . add ( predOps ( ARMCC :: AL ) ) ; } </s>

ARM ARM::GPRRegClass ARM ARM::tMOVr ARMCC::AL


<s> MVT :: SimpleValueType PIC16TargetLowering :: getCmpLibcallReturnType ( ) const { return MVT :: i8 ; } </s>

Return the ValueType for comparison libcalls .


<s> rtx rs6000_libcall_value ( machine_mode mode ) { unsigned int regno ; if ( TARGET_32BIT && TARGET_POWERPC64 && mode == DImode ) return rs6000_parallel_return ( mode , 2 , SImode , GP_ARG_RETURN , 1 ) ; if ( DECIMAL_FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT ) regno = ( mode == TDmode ) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN ; else if ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( mode ) && TARGET_HARD_FLOAT && ( ( TARGET_SINGLE_FLOAT && mode == SFmode ) || TARGET_DOUBLE_FLOAT ) ) regno = FP_ARG_RETURN ; else if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI ) regno = ALTIVEC_ARG_RETURN ; else if ( COMPLEX_MODE_P ( mode ) && targetm . calls . split_complex_arg ) return rs6000_complex_function_value ( mode ) ; else regno = GP_ARG_RETURN ; return gen_rtx_REG ( mode , regno ) ; } </s>

Define how to find the value returned by a library function assuming the value has mode MODE .


<s> void VEFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( isLeafProc ( MF ) ) { VEMachineFunctionInfo * MFI = MF . getInfo < VEMachineFunctionInfo > ( ) ; MFI -> setLeafProc ( true ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> void HexagonPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) { if ( EnableInstSimplify ) addPass ( createInstSimplifyLegacyPass ( ) ) ; addPass ( createDeadCodeEliminationPass ( ) ) ; } addPass ( createAtomicExpandPass ( ) ) ; if ( ! NoOpt ) { if ( EnableInitialCFGCleanup ) addPass ( createCFGSimplificationPass ( SimplifyCFGOptions ( ) . forwardSwitchCondToPhi ( true ) . convertSwitchToLookupTable ( true ) . needCanonicalLoops ( false ) . hoistCommonInsts ( true ) . sinkCommonInsts ( true ) ) ) ; if ( EnableLoopPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableVectorCombine ) addPass ( createHexagonVectorCombineLegacyPass ( ) ) ; if ( EnableCommGEP ) addPass ( createHexagonCommonGEP ( ) ) ; if ( EnableGenExtract ) addPass ( createHexagonGenExtract ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return createTriCoreELFObjectWriter ( OS , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


"builtin %qs can only be used on vector types"

Expand builtins which can directly be mapped to tree expressions . LOC - location information FCODE - function code of the builtin ARGLIST - value supposed to be passed as arguments RETURN-TYPE - expected return type of the builtin


"binary operator does not support two vector bool operands"

"binary operator does not support vector bool operand"

"binary operator does not support mixing vector "

"bool with floating point vector operands"

Return the diagnostic message string if the binary operation OP is not permitted on TYPE1 and TYPE2 , NULL otherwise .


<s> static void m68k_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain_value ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx mem ; gcc_assert ( ADDRESS_REGNO_P ( STATIC_CHAIN_REGNUM ) ) ; mem = adjust_address ( m_tramp , HImode , 0 ) ; emit_move_insn ( mem , GEN_INT ( 0x207C + ( ( STATIC_CHAIN_REGNUM - 8 ) << 9 ) ) ) ; mem = adjust_address ( m_tramp , SImode , 2 ) ; emit_move_insn ( mem , chain_value ) ; mem = adjust_address ( m_tramp , HImode , 6 ) ; emit_move_insn ( mem , GEN_INT ( 0x4EF9 ) ) ; mem = adjust_address ( m_tramp , SImode , 8 ) ; emit_move_insn ( mem , fnaddr ) ; FINALIZE_TRAMPOLINE ( XEXP ( m_tramp , 0 ) ) ; } </s>

We generate a two-instructions program at M_TRAMP : movea.l & CHAIN_VALUE , % a0 jmp FNADDR where % a0 can be modified by changing STATIC_CHAIN_REGNUM .


<s>
bool
HCE
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
LLVM_DEBUG
(
MF
.
print
(
dbgs
(
)
<<
"Before "
<<
getPassName
(
)
<<
'\n'
,
nullptr
)
)
;
HII
=
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getInstrInfo
(
)
;
HRI
=
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getRegisterInfo
(
)
;
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
AssignmentMap
IMap
;
collect
(
MF
)
;
llvm
::
sort
(
Extenders
.
begin
(
)
,
Extenders
.
end
(
)
,
[
]
(
const
ExtDesc
&
A
,
const
ExtDesc
&
B
)
{
return
ExtValue
(
A
)
<
ExtValue
(
B
)
;
}
)
;
bool
Changed
=
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Collected "
<<
Extenders
.
size
(
)
<<
" extenders\n"
)
;
for
(
unsigned
I
=
0
,
E
=
Extenders
.
size
(
)
;
I
!=
E
;
)
{
unsigned
B
=
I
;
const
ExtRoot
&
T
=
Extenders
[
B
]
.
getOp
(
)
;
while
(
I
!=
E
&&
ExtRoot
(
Extenders
[
I
]
.
getOp
(
)
)
==
T
)
++
I
;
IMap
.
clear
(
)
;
assignInits
(
T
,
B
,
I
,
IMap
)
;
Changed
|=
replaceExtenders
(
IMap
)
;
}
LLVM_DEBUG
(
{
if
(
Changed
)
MF
.
print
(
dbgs
(
)
<<
"After "
<<
getPassName
(
)
<<
'\n'
,
nullptr
)
;
else
dbgs
(
)
<<
"No changes\n"
;
}
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

Hexagon
"Before "
Hexagon
Hexagon
"Collected "
" extenders\n"
0
"After "
"No changes\n"


"optionally flag setting instruction missing optional def operand"

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


<s> static rtx ix86_expand_sse_compare_mask ( enum rtx_code code , rtx op0 , rtx op1 , bool swap_operands ) { rtx ( * insn ) ( rtx , rtx , rtx , rtx ) ; machine_mode mode = GET_MODE ( op0 ) ; rtx mask = gen_reg_rtx ( mode ) ; if ( swap_operands ) std :: swap ( op0 , op1 ) ; insn = mode == DFmode ? gen_setcc_df_sse : gen_setcc_sf_sse ; emit_insn ( insn ( mask , op0 , op1 , gen_rtx_fmt_ee ( code , mode , op0 , op1 ) ) ) ; return mask ; } </s>

Expand a mask generating SSE comparison instruction comparing OP0 with OP1 using comparison code CODE . Operands are swapped for the comparison if SWAP_OPERANDS is true . Returns a rtx for the generated mask .


<s> SDNode * PTXDAGToDAGISel :: Select ( SDNode * Node ) { switch ( Node -> getOpcode ( ) ) { case ISD :: BRCOND : return SelectBRCOND ( Node ) ; case PTXISD :: READ_PARAM : return SelectREADPARAM ( Node ) ; case PTXISD :: WRITE_PARAM : return SelectWRITEPARAM ( Node ) ; case ISD :: FrameIndex : return SelectFrameIndex ( Node ) ; default : return SelectCode ( Node ) ; } } </s>

Main hook for targets to transform nodes into machine nodes .

PTX PTX ISD::BRCOND PTXISD::READ_PARAM PTXISD::WRITE_PARAM ISD::FrameIndex


<s>
MCSymbol
*
AAPMCInstLower
::
GetExternalSymbolSymbol
(
const
MachineOperand
&
MO
)
const
{
switch
(
MO
.
getTargetFlags
(
)
)
{
default
:
llvm_unreachable
(
"Unknown target flag on GV operand"
)
;
case
0
:
break
;
}
return
Printer
.
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
;
}
</s>

Return the MCSymbol for the specified ExternalSymbol .

AAP
AAP
"Unknown target flag on GV operand"
0


"Caller should have handled 0-size case"

Emit target-specific code that performs a memcmp/bcmp , in cases where that is faster than a libcall .


<s> static const char * getName ( ) { return DEBUG_TYPE ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


Implement ADJUST_REG_ALLOC_ORDER . We use the default ordering for R1 and non-CDX R2 code ; for CDX we tweak thing to prefer the registers that can be used as operands to instructions that have 3-bit register fields .


<s> bool GCNPassConfig :: addPreRewrite ( ) { if ( EnableRegReassign ) addPass ( & GCNNSAReassignID ) ; return true ; } </s>

addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is complete , but before virtual registers are rewritten to physical registers .


<s> StringRef getPassName ( ) const override { return PASS_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { ForCodeSize = MF . getFunction ( ) . optForSize ( ) ; Subtarget = & MF . getSubtarget < AArch64Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>


<s> unsigned GBZ80InstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { case GB :: LD8_FI : { if ( MI . getOperand ( 1 ) . isFI ( ) ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } default : break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> bool ARMConstantIslands :: runOnMachineFunction ( MachineFunction & Fn ) { MachineConstantPool & MCP = * Fn . getConstantPool ( ) ; TII = Fn . getTarget ( ) . getInstrInfo ( ) ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; isThumb = AFI -> isThumbFunction ( ) ; HasFarJump = false ; Fn . RenumberBlocks ( ) ; AFI -> setAlign ( isThumb ? 1U : 2U ) ; std :: vector < MachineInstr * > CPEMIs ; if ( ! MCP . isEmpty ( ) ) { DoInitialPlacement ( Fn , CPEMIs ) ; if ( isThumb ) AFI -> setAlign ( 2U ) ; } AFI -> initConstPoolEntryUId ( CPEMIs . size ( ) ) ; InitialFunctionScan ( Fn , CPEMIs ) ; CPEMIs . clear ( ) ; RemoveUnusedCPEntries ( ) ; bool MadeChange = false ; while ( true ) { bool Change = false ; for ( unsigned i = 0 , e = CPUsers . size ( ) ; i != e ; ++ i ) Change |= HandleConstantPoolUser ( Fn , i ) ; DEBUG ( dumpBBs ( ) ) ; for ( unsigned i = 0 , e = ImmBranches . size ( ) ; i != e ; ++ i ) Change |= FixUpImmediateBr ( Fn , ImmBranches [ i ] ) ; DEBUG ( dumpBBs ( ) ) ; if ( ! Change ) break ; MadeChange = true ; } verify ( Fn ) ; if ( ! HasFarJump && AFI -> isLRSpilledForFarJump ( ) && isThumb ) MadeChange |= UndoLRSpillRestore ( ) ; BBSizes . clear ( ) ; BBOffsets . clear ( ) ; WaterList . clear ( ) ; CPUsers . clear ( ) ; CPEntries . clear ( ) ; ImmBranches . clear ( ) ; PushPopMIs . clear ( ) ; return MadeChange ; } </s>


<s> void AArch64InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << getRegisterName ( RegNo ) ; } </s>


<s> static rtx nios2_legitimize_constant_address ( rtx addr ) { rtx base , offset ; split_const ( addr , & base , & offset ) ; if ( nios2_tls_symbol_p ( base ) ) base = nios2_legitimize_tls_address ( base ) ; else if ( flag_pic ) base = nios2_load_pic_address ( base , UNSPEC_PIC_SYM , NULL_RTX ) ; else if ( ! nios2_large_constant_allowed ( ) && nios2_symbolic_constant_p ( addr ) ) return nios2_split_large_constant ( addr , gen_reg_rtx ( Pmode ) ) ; else if ( CONST_INT_P ( addr ) ) { HOST_WIDE_INT val = INTVAL ( addr ) ; if ( SMALL_INT ( val ) ) return addr ; else if ( ! nios2_large_constant_allowed ( ) ) return nios2_split_large_constant ( addr , gen_reg_rtx ( Pmode ) ) ; } else return addr ; if ( offset != const0_rtx ) { gcc_assert ( can_create_pseudo_p ( ) ) ; return gen_rtx_PLUS ( Pmode , force_reg ( Pmode , base ) , ( CONST_INT_P ( offset ) ? ( SMALL_INT ( INTVAL ( offset ) ) ? offset : force_reg ( Pmode , offset ) ) : offset ) ) ; } return base ; } </s>

Legitimize addresses that are CONSTANT_P expressions .


<s> static unsigned getReg ( const void * D , unsigned RC , unsigned RegNo ) { const NyuziDisassembler * Dis = static_cast < const NyuziDisassembler * > ( D ) ; return * ( Dis -> getRegInfo ( ) -> getRegClass ( RC ) . begin ( ) + RegNo ) ; } </s>

Returns the register associated with this edge .


<s> void MipsSETargetLowering :: getOpndList ( SmallVectorImpl < SDValue > & Ops , std :: deque < std :: pair < unsigned , SDValue >> & RegsToPass , bool IsPICCall , bool GlobalOrExternal , bool InternalLinkage , bool IsCallReloc , CallLoweringInfo & CLI , SDValue Callee , SDValue Chain ) const { Ops . push_back ( Callee ) ; MipsTargetLowering :: getOpndList ( Ops , RegsToPass , IsPICCall , GlobalOrExternal , InternalLinkage , IsCallReloc , CLI , Callee , Chain ) ; } </s>

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


<s> void BitcodeWriter :: writeSymtab ( ) { assert ( ! WroteStrtab && ! WroteSymtab ) ; for ( Module * M : Mods ) { if ( M -> getModuleInlineAsm ( ) . empty ( ) ) continue ; } WroteSymtab = true ; SmallVector < char , 0 > Symtab ; if ( Error E = irsymtab :: build ( Mods , Symtab , StrtabBuilder , Alloc ) ) { consumeError ( std :: move ( E ) ) ; return ; } writeBlob ( bitc :: SYMTAB_BLOCK_ID , bitc :: SYMTAB_BLOB , { Symtab . data ( ) , Symtab . size ( ) } ) ; } </s>

Attempt to write a symbol table to the bitcode file .


<s> bool MipsAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == ".ent" ) { Parser . Lex ( ) ; return false ; } if ( IDVal == ".end" ) { Parser . Lex ( ) ; return false ; } if ( IDVal == ".frame" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".set" ) { return parseDirectiveSet ( ) ; } if ( IDVal == ".fmask" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".mask" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".gpword" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".word" ) { parseDirectiveWord ( 4 , DirectiveID . getLoc ( ) ) ; return false ; } if ( IDVal == ".mips_hack_stocg" ) return parseDirectiveMipsHackStocg ( ) ; if ( IDVal == ".mips_hack_elf_flags" ) return parseDirectiveMipsHackELFFlags ( ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> const MCExpr * getSubExpr ( ) const { return Expr ; } </s>

getSubExpr - Get the child of this expression .


<s> SDValue PPCTargetLowering :: LowerCall ( SDValue Chain , SDValue Callee , CallingConv :: ID CallConv , bool isVarArg , bool & isTailCall , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { if ( isTailCall ) isTailCall = IsEligibleForTailCallOptimization ( Callee , CallConv , isVarArg , Ins , DAG ) ; if ( PPCSubTarget . isSVR4ABI ( ) && ! PPCSubTarget . isPPC64 ( ) ) { return LowerCall_SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; } else { return LowerCall_Darwin ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; } } </s>

This hook must be implemented to lower calls into the specified DAG .

PowerPC PPC ISD::OutputArg ISD::InputArg PPC PPC PPC


<s> void finish ( ) override { for ( auto * Sym : UpdateOther ) if ( Sym -> isVariable ( ) ) copyLocalEntry ( Sym , Sym -> getVariableValue ( ) ) ; UpdateOther . clear ( ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> bool LC2200AsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> bool AArch64FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( MF . hasEHFunclets ( ) ) return true ; if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) return true ; if ( MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || RegInfo -> needsStackRealignment ( MF ) ) return true ; if ( ! MFI . isMaxCallFrameSizeComputed ( ) || MFI . getMaxCallFrameSize ( ) > DefaultSafeSPDisplacement ) return true ; return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> static bool v850_function_value_regno_p ( const unsigned int regno ) { return ( regno == 10 ) ; } </s>

Worker function for TARGET_FUNCTION_VALUE_REGNO_P .


<s> TargetLowering :: ConstraintType MOSTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'a' : case 'x' : case 'y' : case 'd' : return C_Register ; case 'R' : return C_RegisterClass ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> static void mips_expand_to_rtl_hook ( void ) { mips_set_tuning_info ( ) ; } </s>


<s> bool MipsFastISel :: fastSelectInstruction ( const Instruction * I ) { if ( ! TargetSupported ) return false ; switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Load : return selectLoad ( I ) ; case Instruction :: Store : return selectStore ( I ) ; case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : return selectLogicalOp ( I ) ; case Instruction :: Br : return selectBranch ( I ) ; case Instruction :: Ret : return selectRet ( I ) ; case Instruction :: Trunc : return selectTrunc ( I ) ; case Instruction :: ZExt : case Instruction :: SExt : return selectIntExt ( I ) ; case Instruction :: FPTrunc : return selectFPTrunc ( I ) ; case Instruction :: FPExt : return selectFPExt ( I ) ; case Instruction :: FPToSI : return selectFPToInt ( I , true ) ; case Instruction :: FPToUI : return selectFPToInt ( I , false ) ; case Instruction :: ICmp : case Instruction :: FCmp : return selectCmp ( I ) ; } return false ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> const MCExpr * X86_64MachoTargetObjectFile :: getTTypeGlobalReference ( const GlobalValue * GV , Mangler * Mang , MachineModuleInfo * MMI , unsigned Encoding , MCStreamer & Streamer ) const { if ( Encoding & ( DW_EH_PE_indirect | DW_EH_PE_pcrel ) ) { const MCSymbol * Sym = Mang -> getSymbol ( GV ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_GOTPCREL , getContext ( ) ) ; const MCExpr * Four = MCConstantExpr :: Create ( 4 , getContext ( ) ) ; return MCBinaryExpr :: CreateAdd ( Res , Four , getContext ( ) ) ; } return TargetLoweringObjectFileMachO :: getTTypeGlobalReference ( GV , Mang , MMI , Encoding , Streamer ) ; } </s>

The mach-o version of this method defaults to returning a stub reference .


<s> int getOffset ( ) const { return Offset ; } </s>

Get the offest of a string in the string table .


"expression value must be representable in 32 bits"

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> bool enableMachineScheduler ( ) const override { return true ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


"insertBranch must not be told to insert a fallthrough"

"Cond. cannot be empty when multiple branchings are required"

Insert branch code into the end of the specified MachineBasicBlock .


<s> unsigned GCNHazardRecognizer :: PreEmitNoops ( MachineInstr * MI ) { IsHazardRecognizerMode = true ; CurrCycleInstr = MI ; unsigned W = PreEmitNoopsCommon ( MI ) ; fixHazards ( MI ) ; CurrCycleInstr = nullptr ; return W ; } </s>

PreEmitNoops - This callback is invoked prior to emitting an instruction .


<s> static void ia64_init_libfuncs ( void ) { set_optab_libfunc ( sdiv_optab , SImode , "__divsi3" ) ; set_optab_libfunc ( udiv_optab , SImode , "__udivsi3" ) ; set_optab_libfunc ( smod_optab , SImode , "__modsi3" ) ; set_optab_libfunc ( umod_optab , SImode , "__umodsi3" ) ; set_optab_libfunc ( add_optab , TFmode , "_U_Qfadd" ) ; set_optab_libfunc ( sub_optab , TFmode , "_U_Qfsub" ) ; set_optab_libfunc ( smul_optab , TFmode , "_U_Qfmpy" ) ; set_optab_libfunc ( sdiv_optab , TFmode , "_U_Qfdiv" ) ; set_optab_libfunc ( neg_optab , TFmode , "_U_Qfneg" ) ; set_conv_libfunc ( sext_optab , TFmode , SFmode , "_U_Qfcnvff_sgl_to_quad" ) ; set_conv_libfunc ( sext_optab , TFmode , DFmode , "_U_Qfcnvff_dbl_to_quad" ) ; set_conv_libfunc ( sext_optab , TFmode , XFmode , "_U_Qfcnvff_f80_to_quad" ) ; set_conv_libfunc ( trunc_optab , SFmode , TFmode , "_U_Qfcnvff_quad_to_sgl" ) ; set_conv_libfunc ( trunc_optab , DFmode , TFmode , "_U_Qfcnvff_quad_to_dbl" ) ; set_conv_libfunc ( trunc_optab , XFmode , TFmode , "_U_Qfcnvff_quad_to_f80" ) ; set_conv_libfunc ( sfix_optab , SImode , TFmode , "_U_Qfcnvfxt_quad_to_sgl" ) ; set_conv_libfunc ( sfix_optab , DImode , TFmode , "_U_Qfcnvfxt_quad_to_dbl" ) ; set_conv_libfunc ( sfix_optab , TImode , TFmode , "_U_Qfcnvfxt_quad_to_quad" ) ; set_conv_libfunc ( ufix_optab , SImode , TFmode , "_U_Qfcnvfxut_quad_to_sgl" ) ; set_conv_libfunc ( ufix_optab , DImode , TFmode , "_U_Qfcnvfxut_quad_to_dbl" ) ; set_conv_libfunc ( sfloat_optab , TFmode , SImode , "_U_Qfcnvxf_sgl_to_quad" ) ; set_conv_libfunc ( sfloat_optab , TFmode , DImode , "_U_Qfcnvxf_dbl_to_quad" ) ; set_conv_libfunc ( sfloat_optab , TFmode , TImode , "_U_Qfcnvxf_quad_to_quad" ) ; set_conv_libfunc ( ufloat_optab , TFmode , DImode , "_U_Qfcnvxuf_dbl_to_quad" ) ; } </s>

Set SImode div/mod functions , init_integral_libfuncs only initializes modes of word_mode and larger . Rename the TFmode libfuncs using the HPUX conventions . __divtf3 is used for XFmode . We need to keep it for backward compatibility .


<s> StringRef HexagonMCInstrInfo :: getName ( MCInstrInfo const & MCII , MCInst const & MCI ) { return MCII . getName ( MCI . getOpcode ( ) ) ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s>
bool
ARMDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_Q
:
case
InlineAsm
::
Constraint_Um
:
case
InlineAsm
::
Constraint_Un
:
case
InlineAsm
::
Constraint_Uq
:
case
InlineAsm
::
Constraint_Us
:
case
InlineAsm
::
Constraint_Ut
:
case
InlineAsm
::
Constraint_Uv
:
case
InlineAsm
::
Constraint_Uy
:
OutOps
.
push_back
(
Op
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .

ARM
ARM
"Unexpected asm memory constraint"


<s>
bool
AMDGPULegalizerInfo
::
legalizeCustom
(
MachineInstr
&
MI
,
MachineRegisterInfo
&
MRI
,
MachineIRBuilder
&
B
,
GISelChangeObserver
&
Observer
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
case
TargetOpcode
::
G_ADDRSPACE_CAST
:
return
legalizeAddrSpaceCast
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FRINT
:
return
legalizeFrint
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FCEIL
:
return
legalizeFceil
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_INTRINSIC_TRUNC
:
return
legalizeIntrinsicTrunc
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_SITOFP
:
return
legalizeITOFP
(
MI
,
MRI
,
B
,
true
)
;
case
TargetOpcode
::
G_UITOFP
:
return
legalizeITOFP
(
MI
,
MRI
,
B
,
false
)
;
case
TargetOpcode
::
G_FPTOSI
:
return
legalizeFPTOI
(
MI
,
MRI
,
B
,
true
)
;
case
TargetOpcode
::
G_FPTOUI
:
return
legalizeFPTOI
(
MI
,
MRI
,
B
,
false
)
;
case
TargetOpcode
::
G_FMINNUM
:
case
TargetOpcode
::
G_FMAXNUM
:
case
TargetOpcode
::
G_FMINNUM_IEEE
:
case
TargetOpcode
::
G_FMAXNUM_IEEE
:
return
legalizeMinNumMaxNum
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_EXTRACT_VECTOR_ELT
:
return
legalizeExtractVectorElt
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_INSERT_VECTOR_ELT
:
return
legalizeInsertVectorElt
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_SHUFFLE_VECTOR
:
return
legalizeShuffleVector
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FSIN
:
case
TargetOpcode
::
G_FCOS
:
return
legalizeSinCos
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_GLOBAL_VALUE
:
return
legalizeGlobalValue
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_LOAD
:
return
legalizeLoad
(
MI
,
MRI
,
B
,
Observer
)
;
case
TargetOpcode
::
G_FMAD
:
return
legalizeFMad
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FDIV
:
return
legalizeFDIV
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_ATOMIC_CMPXCHG
:
return
legalizeAtomicCmpXChg
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FLOG
:
return
legalizeFlog
(
MI
,
B
,
1.0f
/
numbers
::
log2ef
)
;
case
TargetOpcode
::
G_FLOG10
:
return
legalizeFlog
(
MI
,
B
,
numbers
::
ln2f
/
numbers
::
ln10f
)
;
case
TargetOpcode
::
G_FEXP
:
return
legalizeFExp
(
MI
,
B
)
;
case
TargetOpcode
::
G_FFLOOR
:
return
legalizeFFloor
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_BUILD_VECTOR
:
return
legalizeBuildVector
(
MI
,
MRI
,
B
)
;
default
:
return
false
;
}
llvm_unreachable
(
"expected switch to return"
)
;
}
</s>

Called for instructions with the Custom LegalizationAction .

AMDGPU
AMDGPU
SI
SI
SI
SI
1.0f
"expected switch to return"


<s> bool ix86_expand_pinsr ( rtx * operands ) { rtx dst = operands [ 0 ] ; rtx src = operands [ 3 ] ; unsigned int size = INTVAL ( operands [ 1 ] ) ; unsigned int pos = INTVAL ( operands [ 2 ] ) ; if ( GET_CODE ( dst ) == SUBREG ) { pos += SUBREG_BYTE ( dst ) * BITS_PER_UNIT ; dst = SUBREG_REG ( dst ) ; } if ( GET_CODE ( src ) == SUBREG ) src = SUBREG_REG ( src ) ; switch ( GET_MODE ( dst ) ) { case V16QImode : case V8HImode : case V4SImode : case V2DImode : { machine_mode srcmode , dstmode ; rtx ( * pinsr ) ( rtx , rtx , rtx , rtx ) ; srcmode = mode_for_size ( size , MODE_INT , 0 ) ; switch ( srcmode ) { case QImode : if ( ! TARGET_SSE4_1 ) return false ; dstmode = V16QImode ; pinsr = gen_sse4_1_pinsrb ; break ; case HImode : if ( ! TARGET_SSE2 ) return false ; dstmode = V8HImode ; pinsr = gen_sse2_pinsrw ; break ; case SImode : if ( ! TARGET_SSE4_1 ) return false ; dstmode = V4SImode ; pinsr = gen_sse4_1_pinsrd ; break ; case DImode : gcc_assert ( TARGET_64BIT ) ; if ( ! TARGET_SSE4_1 ) return false ; dstmode = V2DImode ; pinsr = gen_sse4_1_pinsrq ; break ; default : return false ; } rtx d = dst ; if ( GET_MODE ( dst ) != dstmode ) d = gen_reg_rtx ( dstmode ) ; src = gen_lowpart ( srcmode , src ) ; pos /= size ; emit_insn ( pinsr ( d , gen_lowpart ( dstmode , dst ) , src , GEN_INT ( 1 << pos ) ) ) ; if ( d != dst ) emit_move_insn ( dst , gen_lowpart ( GET_MODE ( dst ) , d ) ) ; return true ; } default : return false ; } } </s>

Expand an insert into a vector register through pinsr insn . Return true if successful .


"%qE attribute not available to functions with arguments "

"%qE attribute not available to functions with variable number "

"%qE attribute not available to functions that return value on "

This function returns true if a function with declaration FNDECL and type FNTYPE uses the stack to pass arguments or return variables and false otherwise . This is used for functions with the attributes 'cmse_nonsecure_call ' or 'cmse_nonsecure_entry ' and this function will issue diagnostic messages if the stack is used . NAME is the name of the attribute used .


"Disassembly not yet supported for subtarget"

Returns the disassembly of a single instruction .


<s> static int frv_registers_conflict_p_1 ( rtx * x , void * data ) { unsigned int regno , i ; regstate_t cond ; cond = * ( regstate_t * ) data ; if ( GET_CODE ( * x ) == REG ) FOR_EACH_REGNO ( regno , * x ) if ( ( frv_packet . regstate [ regno ] & REGSTATE_MODIFIED ) != 0 ) if ( frv_regstate_conflict_p ( frv_packet . regstate [ regno ] , cond ) ) return 1 ; if ( GET_CODE ( * x ) == MEM ) { if ( frv_packet . num_mems > ARRAY_SIZE ( frv_packet . mems ) ) return 1 ; for ( i = 0 ; i < frv_packet . num_mems ; i ++ ) if ( frv_regstate_conflict_p ( frv_packet . mems [ i ] . cond , cond ) ) { if ( true_dependence ( frv_packet . mems [ i ] . mem , VOIDmode , * x , rtx_varies_p ) ) return 1 ; if ( output_dependence ( frv_packet . mems [ i ] . mem , * x ) ) return 1 ; } } if ( GET_CODE ( * x ) == SET && GET_CODE ( SET_SRC ( * x ) ) == CALL ) { if ( for_each_rtx ( & SET_SRC ( * x ) , frv_registers_conflict_p_1 , data ) ) return 1 ; return - 1 ; } return 0 ; } </s>

A for_each_rtx callback . Return 1 if * X depends on an instruction in the current packet . DATA points to a regstate_t that describes the condition under which * X might be set or used .


"RISCV branch conditions have two components!"


<s> InstructionCost RISCVTTIImpl :: getIntrinsicInstrCost ( const IntrinsicCostAttributes & ICA , TTI :: TargetCostKind CostKind ) { auto * RetTy = ICA . getReturnType ( ) ; switch ( ICA . getID ( ) ) { case Intrinsic :: experimental_stepvector : { unsigned Cost = 1 ; auto LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; return Cost + ( LT . first - 1 ) ; } default : break ; } return BaseT :: getIntrinsicInstrCost ( ICA , CostKind ) ; } </s>


"X86-64 PIC uses RIP relative addressing"

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static tree rs6000_builtin_decl ( unsigned code , bool initialize_p ATTRIBUTE_UNUSED ) { HOST_WIDE_INT fnmask ; if ( code >= RS6000_BUILTIN_COUNT ) return error_mark_node ; fnmask = rs6000_builtin_info [ code ] . mask ; if ( ( fnmask & rs6000_builtin_mask ) != fnmask ) { rs6000_invalid_builtin ( ( enum rs6000_builtins ) code ) ; return error_mark_node ; } return rs6000_builtin_decls [ code ] ; } </s>

Returns the rs6000 builtin decl for CODE .


"Second offset should be larger than first offset!"

shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine ( in conjunction with areLoadsFromSameBasePtr ) if two loads should be scheduled togther .


<s> AliasResult AMDGPUAAResult :: alias ( const MemoryLocation & LocA , const MemoryLocation & LocB , AAQueryInfo & AAQI ) { unsigned asA = LocA . Ptr -> getType ( ) -> getPointerAddressSpace ( ) ; unsigned asB = LocB . Ptr -> getType ( ) -> getPointerAddressSpace ( ) ; AliasResult Result = getAliasResult ( asA , asB ) ; if ( Result == NoAlias ) return Result ; MemoryLocation A = LocA ; MemoryLocation B = LocB ; if ( asA != AMDGPUAS :: FLAT_ADDRESS ) { std :: swap ( asA , asB ) ; std :: swap ( A , B ) ; } if ( asA == AMDGPUAS :: FLAT_ADDRESS && ( asB == AMDGPUAS :: LOCAL_ADDRESS || asB == AMDGPUAS :: PRIVATE_ADDRESS ) ) { const auto * ObjA = getUnderlyingObject ( A . Ptr -> stripPointerCastsAndInvariantGroups ( ) ) ; if ( const LoadInst * LI = dyn_cast < LoadInst > ( ObjA ) ) { if ( LI -> getPointerAddressSpace ( ) == AMDGPUAS :: CONSTANT_ADDRESS ) return NoAlias ; } else if ( const Argument * Arg = dyn_cast < Argument > ( ObjA ) ) { const Function * F = Arg -> getParent ( ) ; switch ( F -> getCallingConv ( ) ) { case CallingConv :: AMDGPU_KERNEL : return NoAlias ; default : break ; } } } return AAResultBase :: alias ( LocA , LocB , AAQI ) ; } </s>

alias - If one of the pointers is to a global that we are tracking , and the other is some random pointer , we know there can not be an alias , because the address of the global is n't taken .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU


<s> void SNESFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


<s> void BPFRegisterInfo :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const { } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s>
void
arm_emit_eabi_attribute
(
const
char
*
name
,
int
num
,
int
val
)
{
asm_fprintf
(
asm_out_file
,
"\t.eabi_attribute %d, %d"
,
num
,
val
)
;
if
(
flag_verbose_asm
||
flag_debug_asm
)
asm_fprintf
(
asm_out_file
,
"\t%s %s"
,
ASM_COMMENT_START
,
name
)
;
asm_fprintf
(
asm_out_file
,
"\n"
)
;
}
</s>

This function is used to emit an EABI tag and its associated value . We emit the numerical value of the tag in case the assembler does not support textual tags . ( Eg gas prior to 2.20 ) . If requested we include the tag name in a comment so that anyone reading the assembler output will know which tag is being set . This function is not static because arm-c.cc needs it too .

arm
"\t.eabi_attribute %d, %d"
"\t%s %s"
"\n"


<s> int xtensa_expand_block_move ( rtx * operands ) { static const machine_mode mode_from_align [ ] = { VOIDmode , QImode , HImode , VOIDmode , SImode , } ; rtx dst_mem = operands [ 0 ] ; rtx src_mem = operands [ 1 ] ; HOST_WIDE_INT bytes , align ; int num_pieces , move_ratio ; rtx temp [ 2 ] ; machine_mode mode [ 2 ] ; int amount [ 2 ] ; bool active [ 2 ] ; int phase = 0 ; int next ; int offset_ld = 0 ; int offset_st = 0 ; rtx x ; if ( ! optimize || ( GET_CODE ( operands [ 2 ] ) != CONST_INT ) ) return 0 ; bytes = INTVAL ( operands [ 2 ] ) ; align = INTVAL ( operands [ 3 ] ) ; if ( bytes <= 0 ) return 0 ; if ( align > MOVE_MAX ) align = MOVE_MAX ; move_ratio = 4 ; if ( optimize > 2 ) move_ratio = LARGEST_MOVE_RATIO ; num_pieces = ( bytes / align ) + ( ( bytes % align + 1 ) / 2 ) ; if ( num_pieces > move_ratio ) return 0 ; x = XEXP ( dst_mem , 0 ) ; if ( ! REG_P ( x ) ) { x = force_reg ( Pmode , x ) ; dst_mem = replace_equiv_address ( dst_mem , x ) ; } x = XEXP ( src_mem , 0 ) ; if ( ! REG_P ( x ) ) { x = force_reg ( Pmode , x ) ; src_mem = replace_equiv_address ( src_mem , x ) ; } active [ 0 ] = active [ 1 ] = false ; do { next = phase ; phase ^= 1 ; if ( bytes > 0 ) { int next_amount ; next_amount = ( bytes >= 4 ? 4 : ( bytes >= 2 ? 2 : 1 ) ) ; next_amount = MIN ( next_amount , align ) ; amount [ next ] = next_amount ; mode [ next ] = mode_from_align [ next_amount ] ; temp [ next ] = gen_reg_rtx ( mode [ next ] ) ; x = adjust_address ( src_mem , mode [ next ] , offset_ld ) ; emit_move_insn ( temp [ next ] , x ) ; offset_ld += next_amount ; bytes -= next_amount ; active [ next ] = true ; } if ( active [ phase ] ) { active [ phase ] = false ; x = adjust_address ( dst_mem , mode [ phase ] , offset_st ) ; emit_move_insn ( x , temp [ phase ] ) ; offset_st += amount [ phase ] ; } } while ( active [ next ] ) ; return 1 ; } </s>

Try to expand a block move operation to an RTL block move instruction . If not optimizing or if the block size is not a constant or if the block is small , the expansion fails and GCC falls back to calling memcpy ( ) . operands [ 0 ] is the destination operands [ 1 ] is the source operands [ 2 ] is the length operands [ 3 ] is the alignment


<s> int ARMBaseInstrInfo :: getInstrLatency ( const InstrItineraryData * ItinData , SDNode * Node ) const { if ( ! Node -> isMachineOpcode ( ) ) return 1 ; if ( ! ItinData || ItinData -> isEmpty ( ) ) return 1 ; unsigned Opcode = Node -> getMachineOpcode ( ) ; switch ( Opcode ) { default : return ItinData -> getStageLatency ( get ( Opcode ) . getSchedClass ( ) ) ; case ARM :: VLDMQIA : case ARM :: VSTMQIA : return 2 ; } } </s>

Compute the instruction latency of a given instruction .


<s> MachineBasicBlock :: iterator M680x0FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { bool reserveCallFrame = hasReservedCallFrame ( MF ) ; unsigned Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t InternalAmt = ( isDestroy && Amount ) ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { unsigned StackAlign = getStackAlignment ( ) ; Amount = alignTo ( Amount , StackAlign ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const auto & Fn = MF . getFunction ( ) ; bool DwarfCFI = MMI . hasDebugInfo ( ) || Fn . needsUnwindTableEntry ( ) ; bool HasDwarfEHHandlers = ! MF . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < M680x0MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) { BuildCFI ( MBB , I , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; } if ( Amount == 0 ) return I ; Amount -= InternalAmt ; if ( isDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) ) BuildCFI ( MBB , I , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ; int64_t StackAdjustment = isDestroy ? Amount : - Amount ; int64_t CfaAdjustment = - StackAdjustment ; if ( StackAdjustment ) { StackAdjustment += mergeSPUpdates ( MBB , I , true ) ; StackAdjustment += mergeSPUpdates ( MBB , I , false ) ; if ( StackAdjustment ) { BuildStackAdjustment ( MBB , I , DL , StackAdjustment , false ) ; } } if ( DwarfCFI && ! hasFP ( MF ) ) { if ( CfaAdjustment ) { BuildCFI ( MBB , I , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , CfaAdjustment ) ) ; } } return I ; } if ( isDestroy && InternalAmt ) { MachineBasicBlock :: iterator CI = I ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( CI != B && ! std :: prev ( CI ) -> isCall ( ) ) -- CI ; BuildStackAdjustment ( MBB , CI , DL , - InternalAmt , false ) ; } return I ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static bool sparc_mode_dependent_address_p ( const_rtx addr , addr_space_t as ATTRIBUTE_UNUSED ) { if ( GET_CODE ( addr ) == PLUS && sparc_pic_register_p ( XEXP ( addr , 0 ) ) && symbolic_operand ( XEXP ( addr , 1 ) , VOIDmode ) ) return true ; return false ; } </s>

Return true if ADDR ( a legitimate address expression ) has an effect that depends on the machine mode it is used for . In PIC mode , ( mem : HI [ % l7+a ] ) is not equivalent to ( mem : QI [ % l7+a ] ) ( mem : QI [ % l7+a+1 ] ) because [ % l7+a+1 ] is interpreted as the address of ( a+1 ) .


"Unrecognized Hexagon processor version"

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> const char * getName ( unsigned RegNo ) const { std :: stringstream O ; O << "reg" << RegNo ; return getStrPool ( ) -> getManagedString ( O . str ( ) . c_str ( ) ) -> c_str ( ) ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> static void mips16_split_long_branches ( void ) { bool something_changed ; if ( ! TARGET_MIPS16 ) return ; do { rtx_insn * insn ; shorten_branches ( get_insns ( ) ) ; something_changed = false ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( JUMP_P ( insn ) && get_attr_length ( insn ) > 4 && ( any_condjump_p ( insn ) || any_uncondjump_p ( insn ) ) ) { rtx old_label , temp , saved_temp ; rtx_code_label * new_label ; rtx target ; rtx_insn * jump , * jump_sequence ; start_sequence ( ) ; saved_temp = gen_rtx_REG ( Pmode , AT_REGNUM ) ; temp = gen_rtx_REG ( Pmode , GP_REG_FIRST + 2 ) ; emit_move_insn ( saved_temp , temp ) ; old_label = JUMP_LABEL ( insn ) ; target = gen_rtx_LABEL_REF ( Pmode , old_label ) ; mips16_load_branch_target ( temp , target ) ; jump = emit_jump_insn ( PMODE_INSN ( gen_indirect_jump_and_restore , ( temp , temp , saved_temp ) ) ) ; JUMP_LABEL ( jump ) = old_label ; LABEL_NUSES ( old_label ) ++ ; mips16_lay_out_constants ( false ) ; if ( simplejump_p ( insn ) ) new_label = NULL ; else { new_label = gen_label_rtx ( ) ; emit_label ( new_label ) ; } jump_sequence = get_insns ( ) ; end_sequence ( ) ; emit_insn_after ( jump_sequence , insn ) ; if ( new_label ) invert_jump ( insn , new_label , false ) ; else delete_insn ( insn ) ; something_changed = true ; } } while ( something_changed ) ; } </s>

If we 're compiling a MIPS16 function , look for and split any long branches . This must be called after all other instruction modifications in mips_reorg .


<s> void ix86_option_override ( void ) { ix86_option_override_internal ( true , & global_options , & global_options_set ) ; } </s>

Implement the TARGET_OPTION_OVERRIDE hook .


<s> bool SICAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> int avr_hard_regno_call_part_clobbered ( unsigned regno , machine_mode mode ) { if ( ! avr_hard_regno_mode_ok ( regno , mode ) ) return 0 ; return ( ( regno <= LAST_CALLEE_SAVED_REG && regno + GET_MODE_SIZE ( mode ) > ( LAST_CALLEE_SAVED_REG + 1 ) ) || ( regno < REG_Y && regno + GET_MODE_SIZE ( mode ) > REG_Y ) || ( regno < REG_Z && regno + GET_MODE_SIZE ( mode ) > REG_Z ) ) ; } </s>

Implement ` HARD_REGNO_CALL_PART_CLOBBERED ' .


"Requesting 64-bit offset in 32-bit immediate!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static section * avr_asm_select_section ( tree decl , int reloc , unsigned HOST_WIDE_INT align ) { section * sect = default_elf_select_section ( decl , reloc , align ) ; if ( decl && DECL_P ( decl ) && avr_progmem_p ( decl , DECL_ATTRIBUTES ( decl ) ) ) { addr_space_t as = TYPE_ADDR_SPACE ( TREE_TYPE ( decl ) ) ; if ( ADDR_SPACE_GENERIC_P ( as ) ) as = ADDR_SPACE_FLASH ; if ( sect -> common . flags & SECTION_NAMED ) { const char * name = sect -> named . name ; const char * old_prefix = ".rodata" ; const char * new_prefix = avr_addrspace [ as ] . section_name ; if ( STR_PREFIX_P ( name , old_prefix ) ) { const char * sname = ACONCAT ( ( new_prefix , name + strlen ( old_prefix ) , NULL ) ) ; return get_section ( sname , sect -> common . flags , sect -> named . decl ) ; } } if ( ! progmem_section [ as ] ) { progmem_section [ as ] = get_unnamed_section ( 0 , avr_output_progmem_section_asm_op , avr_addrspace [ as ] . section_name ) ; } return progmem_section [ as ] ; } return sect ; } </s>


<s>
const
char
*
getPassName
(
)
const
override
{
return
"NVPTX Replace Image Handles"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool MipsPassConfig :: addPreEmitPass ( ) { MipsTargetMachine & TM = getMipsTargetMachine ( ) ; addPass ( createMipsDelaySlotFillerPass ( TM ) ) ; if ( TM . getSubtarget < MipsSubtarget > ( ) . hasStandardEncoding ( ) ) addPass ( createMipsLongBranchPass ( TM ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static void expand_block_set_4 ( rtx dst , rtx dst_reg , rtx value_rtx , rtx bytes_rtx ) { unsigned HOST_WIDE_INT bytes = UINTVAL ( bytes_rtx ) ; unsigned int rem = bytes % 4 ; value_rtx = convert_to_mode ( Pmode , value_rtx , 1 ) ; emit_library_call ( long_int_memset_libfunc , LCT_NORMAL , VOIDmode , 3 , dst_reg , Pmode , value_rtx , Pmode , convert_to_mode ( TYPE_MODE ( sizetype ) , GEN_INT ( bytes >> 2 ) , TYPE_UNSIGNED ( sizetype ) ) , TYPE_MODE ( sizetype ) ) ; if ( rem == 0 ) return ; dst = replace_equiv_address_nv ( dst , dst_reg ) ; bytes -= rem ; if ( rem > 1 ) { if ( CONST_INT_P ( value_rtx ) ) { const unsigned HOST_WIDE_INT value = UINTVAL ( value_rtx ) & 0xff ; emit_move_insn ( adjust_address_nv ( dst , HImode , bytes ) , gen_int_mode ( ( value << 8 ) | value , HImode ) ) ; } else { rtx temp = convert_to_mode ( QImode , value_rtx , 1 ) ; emit_move_insn ( adjust_address_nv ( dst , QImode , bytes ) , temp ) ; emit_move_insn ( adjust_address_nv ( dst , QImode , bytes + 1 ) , temp ) ; } bytes += 2 ; rem -= 2 ; } if ( rem > 0 ) emit_move_insn ( adjust_address_nv ( dst , QImode , bytes ) , convert_to_mode ( QImode , value_rtx , 1 ) ) ; } </s>

Generate a call to a library function to set BYTES_RTX bytes of DST with address DST_REG to VALUE_RTX in 4-byte chunks .


<s> unsigned PPCFrameLowering :: determineFrameLayoutAndUpdate ( MachineFunction & MF , bool UseEstimate ) const { unsigned NewMaxCallFrameSize = 0 ; unsigned FrameSize = determineFrameLayout ( MF , UseEstimate , & NewMaxCallFrameSize ) ; MF . getFrameInfo ( ) . setStackSize ( FrameSize ) ; MF . getFrameInfo ( ) . setMaxCallFrameSize ( NewMaxCallFrameSize ) ; return FrameSize ; } </s>

Determine the frame layout and update the machine function .


<s> bool arm_frame_pointer_required ( void ) { if ( SUBTARGET_FRAME_POINTER_REQUIRED ) return true ; if ( cfun -> has_nonlocal_label ) return true ; if ( TARGET_ARM && TARGET_APCS_FRAME && ! crtl -> is_leaf ) return true ; if ( ! IS_INTERRUPT ( arm_current_func_type ( ) ) && flag_stack_check == STATIC_BUILTIN_STACK_CHECK && arm_except_unwind_info ( & global_options ) == UI_TARGET && cfun -> can_throw_non_call_exceptions ) { HOST_WIDE_INT size = get_frame_size ( ) ; if ( size <= 0 ) return false ; if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { size += 32 * UNITS_PER_WORD ; if ( size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT ) return true ; } else return true ; } return false ; } </s>


"RISC-V backend can't currently handle functions that need stack "

"realignment and have variable sized objects"

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s>
void
Mips16FrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
const
Mips16InstrInfo
&
TII
=
*
static_cast
<
const
Mips16InstrInfo
*
>
(
STI
.
getInstrInfo
(
)
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
dl
;
uint64_t
StackSize
=
MFI
.
getStackSize
(
)
;
if
(
StackSize
==
0
&&
!
MFI
.
adjustsStack
(
)
)
return
;
MachineModuleInfo
&
MMI
=
MF
.
getMMI
(
)
;
const
MCRegisterInfo
*
MRI
=
MMI
.
getContext
(
)
.
getRegisterInfo
(
)
;
MachineLocation
DstML
,
SrcML
;
TII
.
makeFrame
(
Mips
::
SP
,
StackSize
,
MBB
,
MBBI
)
;
unsigned
CFIIndex
=
MF
.
addFrameInst
(
MCCFIInstruction
::
createDefCfaOffset
(
nullptr
,
StackSize
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
TargetOpcode
::
CFI_INSTRUCTION
)
)
.
addCFIIndex
(
CFIIndex
)
;
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
.
getCalleeSavedInfo
(
)
;
if
(
CSI
.
size
(
)
)
{
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
.
getCalleeSavedInfo
(
)
;
for
(
std
::
vector
<
CalleeSavedInfo
>
::
const_iterator
I
=
CSI
.
begin
(
)
,
E
=
CSI
.
end
(
)
;
I
!=
E
;
++
I
)
{
int64_t
Offset
=
MFI
.
getObjectOffset
(
I
->
getFrameIdx
(
)
)
;
unsigned
Reg
=
I
->
getReg
(
)
;
unsigned
DReg
=
MRI
->
getDwarfRegNum
(
Reg
,
true
)
;
unsigned
CFIIndex
=
MF
.
addFrameInst
(
MCCFIInstruction
::
createOffset
(
nullptr
,
DReg
,
Offset
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
TargetOpcode
::
CFI_INSTRUCTION
)
)
.
addCFIIndex
(
CFIIndex
)
;
}
}
if
(
hasFP
(
MF
)
)
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Mips
::
MoveR3216
)
,
Mips
::
S0
)
.
addReg
(
Mips
::
SP
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
}
</s>

Mips
Mips
"Shrink-wrapping not yet supported"
Mips
Mips
0
Mips::SP
Mips::MoveR3216
Mips::S0
Mips::SP


<s> bool PPCInstrInfo :: getMachineCombinerPatterns ( MachineInstr & Root , SmallVectorImpl < MachineCombinerPattern > & Patterns , bool DoRegPressureReduce ) const { if ( Subtarget . getTargetMachine ( ) . getOptLevel ( ) != CodeGenOpt :: Aggressive ) return false ; if ( getFMAPatterns ( Root , Patterns ) ) return true ; return TargetInstrInfo :: getMachineCombinerPatterns ( Root , Patterns , DoRegPressureReduce ) ; } </s>

Return true when there is potentially a faster code sequence for an instruction chain ending in Root .


<s> unsigned getBase ( ) const { assert ( Base ) ; return Base ; } </s>


<s> const NVPTXRegisterInfo & getRegisterInfo ( ) const { return RegInfo ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool TPCHazardRecognizer :: canReserveResources ( SUnit * SU ) { MachineInstr * MI = SU -> getInstr ( ) ; if ( MI -> isPseudo ( ) ) { return ( CurrentPacket . size ( ) < 2 ) ; } if ( ! Resources -> canReserveResources ( * MI ) ) { return false ; } for ( auto SUJ : CurrentPacket ) { if ( ! isLegalToPacketizeTogether ( SU , SUJ ) ) { return false ; } } return true ; } </s>

Check if the resources occupied by a machine instruction are available in the current state .


<s> unsigned X86InstrInfo :: getOpcodeAfterMemoryUnfold ( unsigned Opc , bool UnfoldLoad , bool UnfoldStore , unsigned * LoadRegIndex ) const { const X86MemoryFoldTableEntry * I = lookupUnfoldTable ( Opc ) ; if ( I == nullptr ) return 0 ; bool FoldedLoad = I -> Flags & TB_FOLDED_LOAD ; bool FoldedStore = I -> Flags & TB_FOLDED_STORE ; if ( UnfoldLoad && ! FoldedLoad ) return 0 ; if ( UnfoldStore && ! FoldedStore ) return 0 ; if ( LoadRegIndex ) * LoadRegIndex = I -> Flags & TB_INDEX_MASK ; return I -> DstOp ; } </s>

getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode .


<s> static rtx tilegx_delegitimize_address ( rtx x ) { x = delegitimize_mem_from_attrs ( x ) ; if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == UNSPEC ) { switch ( XINT ( XEXP ( x , 0 ) , 1 ) ) { case UNSPEC_HW0 : case UNSPEC_HW1 : case UNSPEC_HW2 : case UNSPEC_HW3 : case UNSPEC_HW0_LAST : case UNSPEC_HW1_LAST : case UNSPEC_HW2_LAST : case UNSPEC_HW0_PCREL : case UNSPEC_HW1_PCREL : case UNSPEC_HW1_LAST_PCREL : case UNSPEC_HW2_LAST_PCREL : case UNSPEC_HW0_PLT_PCREL : case UNSPEC_HW1_PLT_PCREL : case UNSPEC_HW1_LAST_PLT_PCREL : case UNSPEC_HW2_LAST_PLT_PCREL : case UNSPEC_HW0_GOT : case UNSPEC_HW0_LAST_GOT : case UNSPEC_HW1_LAST_GOT : case UNSPEC_HW0_TLS_GD : case UNSPEC_HW1_LAST_TLS_GD : case UNSPEC_HW0_TLS_IE : case UNSPEC_HW1_LAST_TLS_IE : case UNSPEC_HW0_TLS_LE : case UNSPEC_HW1_LAST_TLS_LE : x = XVECEXP ( XEXP ( x , 0 ) , 0 , 0 ) ; break ; } } return x ; } </s>


<s>
void
PatmosFrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
const
TargetInstrInfo
&
TII
=
*
TM
.
getInstrInfo
(
)
;
if
(
TM
.
getFrameLowering
(
)
->
hasFP
(
MF
)
)
{
MachineInstr
&
MI
=
*
I
;
DebugLoc
dl
=
MI
.
getDebugLoc
(
)
;
int
Size
=
MI
.
getOperand
(
0
)
.
getImm
(
)
;
unsigned
Opcode
;
if
(
MI
.
getOpcode
(
)
==
Patmos
::
ADJCALLSTACKDOWN
)
{
Opcode
=
(
Size
<=
0xFFF
)
Patmos
::
SUBi
:
Patmos
::
SUBl
;
}
else
if
(
MI
.
getOpcode
(
)
==
Patmos
::
ADJCALLSTACKUP
)
{
Opcode
=
(
Size
<=
0xFFF
)
Patmos
::
ADDi
:
Patmos
::
ADDl
;
}
else
{
llvm_unreachable
(
"Unsupported pseudo instruction."
)
;
}
if
(
Size
)
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
dl
,
TII
.
get
(
Opcode
)
,
Patmos
::
RSP
)
)
.
addReg
(
Patmos
::
RSP
)
.
addImm
(
Size
)
;
}
MBB
.
erase
(
I
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

Patmos
Patmos
0
Patmos::ADJCALLSTACKDOWN
0xFFF
Patmos::SUBi
Patmos::SUBl
Patmos::ADJCALLSTACKUP
0xFFF
Patmos::ADDi
Patmos::ADDl
"Unsupported pseudo instruction."
Patmos::RSP
Patmos::RSP


<s> static machine_mode ix86_promote_function_mode ( const_tree type , machine_mode mode , int * punsignedp , const_tree fntype , int for_return ) { if ( cfun -> machine -> func_type == TYPE_NORMAL && type != NULL_TREE && POINTER_TYPE_P ( type ) ) { * punsignedp = POINTERS_EXTEND_UNSIGNED ; return word_mode ; } return default_promote_function_mode ( type , mode , punsignedp , fntype , for_return ) ; } </s>

Pointer function arguments and return values are promoted to word_mode .


<s> static bool ix86_pass_by_reference ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( ( type && POINTER_BOUNDS_TYPE_P ( type ) ) || POINTER_BOUNDS_MODE_P ( mode ) ) return false ; if ( TARGET_64BIT && ( cum ? cum -> call_abi : ix86_abi ) == MS_ABI ) { int msize = ( int ) GET_MODE_SIZE ( mode ) ; if ( type ) { if ( TREE_CODE ( type ) == ARRAY_TYPE ) return true ; if ( AGGREGATE_TYPE_P ( type ) ) { msize = int_size_in_bytes ( type ) ; } } switch ( msize ) { case 1 : case 2 : case 4 : case 8 : break ; default : return true ; } } else if ( TARGET_64BIT && type && int_size_in_bytes ( type ) == - 1 ) return 1 ; return 0 ; } </s>

A C expression that indicates when an argument must be passed by reference . If nonzero for an argument , a copy of that argument is made in memory and a pointer to the argument is passed instead of the argument itself . The pointer is passed in whatever way is appropriate for passing a pointer to that type .


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> const MCPhysReg * SIRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { CallingConv :: ID CC = MF -> getFunction ( ) . getCallingConv ( ) ; switch ( CC ) { case CallingConv :: C : case CallingConv :: Fast : case CallingConv :: Cold : case CallingConv :: AMDGPU_Gfx : return MF -> getSubtarget < GCNSubtarget > ( ) . hasGFX90AInsts ( ) ? CSR_AMDGPU_HighRegs_With_AGPRs_SaveList : CSR_AMDGPU_HighRegs_SaveList ; default : { static const MCPhysReg NoCalleeSavedReg = AMDGPU :: NoRegister ; return & NoCalleeSavedReg ; } } } </s>

AMDGPU SI AMDGPU AMDGPU AMDGPU AMDGPU::NoRegister


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s>
MachineBasicBlock
*
WebAssemblyTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
const
TargetInstrInfo
&
TII
=
*
Subtarget
->
getInstrInfo
(
)
;
DebugLoc
DL
=
MI
.
getDebugLoc
(
)
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unexpected instr type to insert"
)
;
case
WebAssembly
::
FP_TO_SINT_I32_F32
:
return
LowerFPToInt
(
MI
,
DL
,
BB
,
TII
,
false
,
false
,
false
,
WebAssembly
::
I32_TRUNC_S_F32
)
;
case
WebAssembly
::
FP_TO_UINT_I32_F32
:
return
LowerFPToInt
(
MI
,
DL
,
BB
,
TII
,
true
,
false
,
false
,
WebAssembly
::
I32_TRUNC_U_F32
)
;
case
WebAssembly
::
FP_TO_SINT_I64_F32
:
return
LowerFPToInt
(
MI
,
DL
,
BB
,
TII
,
false
,
true
,
false
,
WebAssembly
::
I64_TRUNC_S_F32
)
;
case
WebAssembly
::
FP_TO_UINT_I64_F32
:
return
LowerFPToInt
(
MI
,
DL
,
BB
,
TII
,
true
,
true
,
false
,
WebAssembly
::
I64_TRUNC_U_F32
)
;
case
WebAssembly
::
FP_TO_SINT_I32_F64
:
return
LowerFPToInt
(
MI
,
DL
,
BB
,
TII
,
false
,
false
,
true
,
WebAssembly
::
I32_TRUNC_S_F64
)
;
case
WebAssembly
::
FP_TO_UINT_I32_F64
:
return
LowerFPToInt
(
MI
,
DL
,
BB
,
TII
,
true
,
false
,
true
,
WebAssembly
::
I32_TRUNC_U_F64
)
;
case
WebAssembly
::
FP_TO_SINT_I64_F64
:
return
LowerFPToInt
(
MI
,
DL
,
BB
,
TII
,
false
,
true
,
true
,
WebAssembly
::
I64_TRUNC_S_F64
)
;
case
WebAssembly
::
FP_TO_UINT_I64_F64
:
return
LowerFPToInt
(
MI
,
DL
,
BB
,
TII
,
true
,
true
,
true
,
WebAssembly
::
I64_TRUNC_U_F64
)
;
case
WebAssembly
::
CALL_RESULTS
:
return
LowerCallResults
(
MI
,
DL
,
BB
,
TII
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> bool ResourceAssignment :: isPseudo ( SUnit * SU ) const { return ( ! SU -> getInstr ( ) ) ; } </s>

Return true if this is a pseudo instruction that does n't correspond to a real machine instruction .


<s> bool X86FastISel :: isTypeLegal ( const Type * Ty , EVT & VT , bool AllowI1 ) { VT = TLI . getValueType ( Ty , true ) ; if ( VT == MVT :: Other || ! VT . isSimple ( ) ) return false ; if ( VT == MVT :: f64 && ! X86ScalarSSEf64 ) return false ; if ( VT == MVT :: f32 && ! X86ScalarSSEf32 ) return false ; if ( VT == MVT :: f80 ) return false ; return ( AllowI1 && VT == MVT :: i1 ) || TLI . isTypeLegal ( VT ) ; } </s>


<s> const AArch64Subtarget * AArch64TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < AArch64Subtarget > ( TargetTriple , CPU , FS , * this , isLittle ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static machine_mode sparc_preferred_simd_mode ( machine_mode mode ) { if ( TARGET_VIS ) switch ( mode ) { case SImode : return V2SImode ; case HImode : return V4HImode ; case QImode : return V8QImode ; default : ; } return word_mode ; } </s>

Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook .


<s> const HexagonSubtarget * HexagonTargetMachine :: getSubtargetImpl ( const Function & F ) const { AttributeSet FnAttrs = F . getAttributes ( ) ; Attribute CPUAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "target-cpu" ) ; Attribute FSAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < HexagonSubtarget > ( TargetTriple , CPU , FS , * this ) ; } return I . get ( ) ; } </s>

Hexagon Hexagon Hexagon "target-cpu" "target-features" Hexagon


<s> inline static rtx next_consecutive_mem ( rtx mem ) { machine_mode mode = GET_MODE ( mem ) ; HOST_WIDE_INT offset = GET_MODE_SIZE ( mode ) ; rtx addr = plus_constant ( Pmode , XEXP ( mem , 0 ) , offset ) ; return adjust_automodify_address ( mem , mode , addr , offset ) ; } </s>

Helper for gen_movmem_ldrd_strd . Increase the address of memory rtxby mode size .


<s> void SICFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; SICFunctionInfo * SICFI = MF . getInfo < SICFunctionInfo > ( ) ; const SICInstrInfo & TII = * static_cast < const SICInstrInfo * > ( STI . getInstrInfo ( ) ) ; const SICRegisterInfo & RegInfo = * static_cast < const SICRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; SICABIInfo ABI = STI . getABI ( ) ; unsigned SP = SIC :: X ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize , MBB , MBBI ) ; } </s>

SIC SIC SIC SIC SIC SIC SIC SIC SIC SIC SIC::X


<s> const MCPhysReg * SPIRVRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const MCPhysReg CalleeSavedReg = { 0 } ; return & CalleeSavedReg ; } </s>


<s> rtx_insn * s390_load_got ( void ) { rtx_insn * insns ; rtx got_rtx = gen_rtx_REG ( Pmode , 12 ) ; start_sequence ( ) ; emit_move_insn ( got_rtx , s390_got_symbol ( ) ) ; insns = get_insns ( ) ; end_sequence ( ) ; return insns ; } </s>

Return insn sequence to load the GOT register .


<s>
bool
HexagonDCE
::
run
(
)
{
bool
Collected
=
collect
(
)
;
if
(
!
Collected
)
return
false
;
const
SetVector
<
NodeId
>
&
DeadNodes
=
getDeadNodes
(
)
;
const
SetVector
<
NodeId
>
&
DeadInstrs
=
getDeadInstrs
(
)
;
typedef
DenseMap
<
NodeId
,
NodeId
>
RefToInstrMap
;
RefToInstrMap
R2I
;
SetVector
<
NodeId
>
PartlyDead
;
DataFlowGraph
&
DFG
=
getDFG
(
)
;
for
(
NodeAddr
<
BlockNode
*
>
BA
:
DFG
.
getFunc
(
)
.
Addr
->
members
(
DFG
)
)
{
for
(
auto
TA
:
BA
.
Addr
->
members_if
(
DFG
.
IsCode
<
NodeAttrs
::
Stmt
>
,
DFG
)
)
{
NodeAddr
<
StmtNode
*
>
SA
=
TA
;
for
(
NodeAddr
<
RefNode
*
>
RA
:
SA
.
Addr
->
members
(
DFG
)
)
{
R2I
.
insert
(
std
::
make_pair
(
RA
.
Id
,
SA
.
Id
)
)
;
if
(
DFG
.
IsDef
(
RA
)
&&
DeadNodes
.
count
(
RA
.
Id
)
)
if
(
!
DeadInstrs
.
count
(
SA
.
Id
)
)
PartlyDead
.
insert
(
SA
.
Id
)
;
}
}
}
SetVector
<
NodeId
>
Remove
=
DeadInstrs
;
bool
Changed
=
false
;
for
(
NodeId
N
:
PartlyDead
)
{
auto
SA
=
DFG
.
addr
<
StmtNode
*
>
(
N
)
;
if
(
trace
(
)
)
dbgs
(
)
<<
"Partly dead: "
<<
*
SA
.
Addr
->
getCode
(
)
;
Changed
|=
rewrite
(
SA
,
Remove
)
;
}
return
erase
(
Remove
)
||
Changed
;
}
</s>

Run the analysis pass over a function and produce a dominator tree .


<s> unsigned SPUTargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , unsigned Depth ) const { switch ( Op . getOpcode ( ) ) { default : return 1 ; case ISD :: SETCC : { EVT VT = Op . getValueType ( ) ; if ( VT != MVT :: i8 && VT != MVT :: i16 && VT != MVT :: i32 ) { VT = MVT :: i32 ; } return VT . getSizeInBits ( ) ; } } } </s>

Determine the number of bits in the operation that are sign bits .


<s>
bool
ARMLowOverheadLoops
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
const
ARMSubtarget
&
ST
=
static_cast
<
const
ARMSubtarget
&
>
(
mf
.
getSubtarget
(
)
)
;
if
(
!
ST
.
hasLOB
(
)
)
return
false
;
MF
=
&
mf
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM Loops on "
<<
MF
->
getName
(
)
<<
" ------------- \n"
)
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
RDA
=
&
getAnalysis
<
ReachingDefAnalysis
>
(
)
;
MF
->
getProperties
(
)
.
set
(
MachineFunctionProperties
::
Property
::
TracksLiveness
)
;
MRI
=
&
MF
->
getRegInfo
(
)
;
TII
=
static_cast
<
const
ARMBaseInstrInfo
*
>
(
ST
.
getInstrInfo
(
)
)
;
TRI
=
ST
.
getRegisterInfo
(
)
;
BBUtils
=
std
::
unique_ptr
<
ARMBasicBlockUtils
>
(
new
ARMBasicBlockUtils
(
*
MF
)
)
;
BBUtils
->
computeAllBlockSizes
(
)
;
BBUtils
->
adjustBBOffsetsAfter
(
&
MF
->
front
(
)
)
;
bool
Changed
=
false
;
for
(
auto
ML
:
*
MLI
)
{
if
(
ML
->
isOutermost
(
)
)
Changed
|=
ProcessLoop
(
ML
)
;
}
Changed
|=
RevertNonLoops
(
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

ARM
ARM
ARM
ARM
"ARM Loops on "
" ------------- \n"
ARM
ARM
ARM