<s> void s390_expand_vec_init ( rtx target , rtx vals ) { machine_mode mode = GET_MODE ( target ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; int n_elts = GET_MODE_NUNITS ( mode ) ; bool all_same = true , all_regs = true , all_const_int = true ; rtx x ; int i ; for ( i = 0 ; i < n_elts ; ++ i ) { x = XVECEXP ( vals , 0 , i ) ; if ( ! CONST_INT_P ( x ) ) all_const_int = false ; if ( i > 0 && ! rtx_equal_p ( x , XVECEXP ( vals , 0 , 0 ) ) ) all_same = false ; if ( ! REG_P ( x ) ) all_regs = false ; } if ( all_same && all_const_int && ( XVECEXP ( vals , 0 , 0 ) == const0_rtx || s390_contiguous_bitmask_vector_p ( XVECEXP ( vals , 0 , 0 ) , NULL , NULL ) || s390_bytemask_vector_p ( XVECEXP ( vals , 0 , 0 ) , NULL ) ) ) { emit_insn ( gen_rtx_SET ( target , gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , 0 ) ) ) ) ; return ; } if ( all_same ) { emit_insn ( gen_rtx_SET ( target , gen_rtx_VEC_DUPLICATE ( mode , XVECEXP ( vals , 0 , 0 ) ) ) ) ; return ; } if ( all_regs && REG_P ( target ) && n_elts == 2 && inner_mode == DImode ) { emit_insn ( gen_rtx_SET ( target , gen_rtx_VEC_CONCAT ( mode , XVECEXP ( vals , 0 , 0 ) , XVECEXP ( vals , 0 , 1 ) ) ) ) ; return ; } emit_insn ( gen_rtx_SET ( target , CONST0_RTX ( mode ) ) ) ; for ( i = 0 ; i < n_elts ; i ++ ) emit_insn ( gen_rtx_SET ( target , gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , XVECEXP ( vals , 0 , i ) , GEN_INT ( i ) , target ) , UNSPEC_VEC_SET ) ) ) ; } </s>

Emit the RTX necessary to initialize the vector TARGET with values in VALS .


<s> const uint32_t * ARMBaseRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; if ( CC == CallingConv :: GHC ) return CSR_NoRegs_RegMask ; if ( STI . isTargetDarwin ( ) && CC == CallingConv :: CXX_FAST_TLS ) return CSR_iOS_CXX_TLS_RegMask ; return STI . isTargetDarwin ( ) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static void vax_trampoline_init ( rtx m_tramp , tree fndecl , rtx cxt ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx mem ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp , HImode , 0 ) ; emit_move_insn ( mem , gen_const_mem ( HImode , fnaddr ) ) ; mem = adjust_address ( m_tramp , SImode , 4 ) ; emit_move_insn ( mem , cxt ) ; mem = adjust_address ( m_tramp , SImode , 11 ) ; emit_move_insn ( mem , plus_constant ( Pmode , fnaddr , 2 ) ) ; emit_insn ( gen_sync_istream ( ) ) ; } </s>

We copy the register-mask from the function 's pure code to the start of the trampoline .


<s> void mep_save_register_info ( void ) { save_register_info ( ) ; } </s>

These three functions provide a bridge between the pramgas that affect register classes , and the functions that maintain them . We ca n't call those functions directly as pragma handling is part of the front end and does n't have direct access to them .


<s> void ARCPassConfig :: addPreRegAlloc ( ) { addPass ( createARCExpandPseudosPass ( ) ) ; addPass ( createARCOptAddrMode ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> bool PPCSubtarget :: useDFAforSMS ( ) const { return false ; } </s>

Default to DFA for resource management , return false when target will use ProcResource in InstrSchedModel instead .


<s> static rtx extract_sfunc_addr ( rtx insn ) { rtx pattern , part = NULL_RTX ; int len , i ; pattern = PATTERN ( insn ) ; len = XVECLEN ( pattern , 0 ) ; for ( i = 0 ; i < len ; i ++ ) { part = XVECEXP ( pattern , 0 , i ) ; if ( GET_CODE ( part ) == USE && GET_MODE ( XEXP ( part , 0 ) ) == Pmode && GENERAL_REGISTER_P ( true_regnum ( XEXP ( part , 0 ) ) ) ) return XEXP ( part , 0 ) ; } gcc_assert ( GET_CODE ( XVECEXP ( pattern , 0 , 0 ) ) == UNSPEC_VOLATILE ) ; return XVECEXP ( XVECEXP ( pattern , 0 , 0 ) , 0 , 1 ) ; } </s>

INSN is an sfunc ; return the rtx that describes the address used .


<s> void emitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) override { emitA64MappingSymbol ( ) ; MCELFStreamer :: emitInstruction ( Inst , STI ) ; } </s>

Targets should implement this to emit instructions .


<s> static void nds32_init_builtins ( void ) { nds32_init_builtins_impl ( ) ; } </s>


"profiling %<-mcmodel=large%> with PIC is not supported"

Output assembler code to FILE to increment profiler label # LABELNO for profiling a function entry .


<s> bool ARMBaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( MF . getFunction ( ) -> hasFnAttribute ( "no-realign-stack" ) ) return false ; if ( AFI -> isThumb1OnlyFunction ( ) ) return false ; if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ; if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) ) return true ; return MRI -> canReserveReg ( BasePtr ) ; } </s>

True if the stack can be realigned for the target .


<s> static int cris_reg_overlap_mentioned_p ( rtx x , rtx in ) { if ( GET_CODE ( in ) == STRICT_LOW_PART ) in = XEXP ( in , 0 ) ; return reg_overlap_mentioned_p ( x , in ) ; } </s>

The function reg_overlap_mentioned_p in CVS ( still as of 2001-05-16 ) does not handle the case where the IN operand is strict_low_part ; it does handle it for X. Test-case in Axis-20010516 . This function takes care of that for THIS port . FIXME : strict_low_part is going away anyway .


<s> void CAHPAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; MCInst TmpInst , CInst ; LowerCAHPMachineInstrToMCInst ( MI , TmpInst , * this ) ; bool Res = compressInst ( CInst , TmpInst , * TM . getMCSubtargetInfo ( ) , OutStreamer -> getContext ( ) ) ; EmitToStreamer ( * OutStreamer , Res ? CInst : TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> Reloc :: Model MipsSubtarget :: getRelocationModel ( ) const { return TM . getRelocationModel ( ) ; } </s>

Returns the code generation relocation model .


<s> static void arc_init_reg_tables ( void ) { int i ; for ( i = 0 ; i < NUM_MACHINE_MODES ; i ++ ) { machine_mode m = ( machine_mode ) i ; switch ( GET_MODE_CLASS ( m ) ) { case MODE_INT : case MODE_PARTIAL_INT : case MODE_COMPLEX_INT : if ( GET_MODE_SIZE ( m ) <= 4 ) arc_mode_class [ i ] = 1 << ( int ) S_MODE ; else if ( GET_MODE_SIZE ( m ) == 8 ) arc_mode_class [ i ] = 1 << ( int ) D_MODE ; else if ( GET_MODE_SIZE ( m ) == 16 ) arc_mode_class [ i ] = 1 << ( int ) T_MODE ; else if ( GET_MODE_SIZE ( m ) == 32 ) arc_mode_class [ i ] = 1 << ( int ) O_MODE ; else arc_mode_class [ i ] = 0 ; break ; case MODE_FLOAT : case MODE_COMPLEX_FLOAT : if ( GET_MODE_SIZE ( m ) <= 4 ) arc_mode_class [ i ] = 1 << ( int ) SF_MODE ; else if ( GET_MODE_SIZE ( m ) == 8 ) arc_mode_class [ i ] = 1 << ( int ) DF_MODE ; else if ( GET_MODE_SIZE ( m ) == 16 ) arc_mode_class [ i ] = 1 << ( int ) TF_MODE ; else if ( GET_MODE_SIZE ( m ) == 32 ) arc_mode_class [ i ] = 1 << ( int ) OF_MODE ; else arc_mode_class [ i ] = 0 ; break ; case MODE_VECTOR_INT : arc_mode_class [ i ] = ( 1 << ( int ) V_MODE ) ; break ; case MODE_CC : default : if ( i == ( int ) CCmode || i == ( int ) CC_ZNmode || i == ( int ) CC_Zmode || i == ( int ) CC_Cmode || i == CC_FP_GTmode || i == CC_FP_GEmode || i == CC_FP_ORDmode ) arc_mode_class [ i ] = 1 << ( int ) C_MODE ; else arc_mode_class [ i ] = 0 ; break ; } } } </s>


<s> static int sparc_vis_mul8x16 ( int e8 , int e16 ) { return ( e8 * e16 + 128 ) / 256 ; } </s>

Return the upper 16 bits of the 8x16 multiplication .


<s> bool ARMSubtarget :: enableSubRegLiveness ( ) const { if ( EnableSubRegLiveness . getNumOccurrences ( ) ) return EnableSubRegLiveness ; return hasMVEIntegerOps ( ) ; } </s>

Enable tracking of subregister liveness in register allocator .


<s> void AMDGPUAsmPrinter :: emitFunctionBodyEnd ( ) { const SIMachineFunctionInfo & MFI = * MF -> getInfo < SIMachineFunctionInfo > ( ) ; if ( ! MFI . isEntryFunction ( ) ) return ; if ( ! IsaInfo :: hasCodeObjectV3 ( getGlobalSTI ( ) ) || TM . getTargetTriple ( ) . getOS ( ) != Triple :: AMDHSA ) return ; auto & Streamer = getTargetStreamer ( ) -> getStreamer ( ) ; auto & Context = Streamer . getContext ( ) ; auto & ObjectFileInfo = * Context . getObjectFileInfo ( ) ; auto & ReadOnlySection = * ObjectFileInfo . getReadOnlySection ( ) ; Streamer . PushSection ( ) ; Streamer . SwitchSection ( & ReadOnlySection ) ; Streamer . emitValueToAlignment ( 64 , 0 , 1 , 0 ) ; if ( ReadOnlySection . getAlignment ( ) < 64 ) ReadOnlySection . setAlignment ( Align ( 64 ) ) ; const MCSubtargetInfo & STI = MF -> getSubtarget ( ) ; SmallString < 128 > KernelName ; getNameWithPrefix ( KernelName , & MF -> getFunction ( ) ) ; getTargetStreamer ( ) -> EmitAmdhsaKernelDescriptor ( STI , KernelName , getAmdhsaKernelDescriptor ( * MF , CurrentProgramInfo ) , CurrentProgramInfo . NumVGPRsForWavesPerEU , CurrentProgramInfo . NumSGPRsForWavesPerEU - IsaInfo :: getNumExtraSGPRs ( & STI , CurrentProgramInfo . VCCUsed , CurrentProgramInfo . FlatUsed ) , CurrentProgramInfo . VCCUsed , CurrentProgramInfo . FlatUsed , hasXNACK ( STI ) ) ; Streamer . PopSection ( ) ; } </s>

Targets can override this to emit stuff after the last basic block in the function .


runOnMachineFunction - Emit the function body .


<s> int mcore_dllexport_name_p ( const char * symbol ) { return symbol [ 0 ] == '@' && symbol [ 1 ] == 'e' && symbol [ 2 ] == '.' ; } </s>

Return non-zero if SYMBOL is marked as being dllexport 'd .


<s> const XCoreTargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


<s> virtual EVT getSetCCResultType ( EVT VT ) const { return MVT :: i1 ; } </s>

Return the value type to use for ISD : :SETCC .


<s> void WebAssemblyFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { uint64_t StackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ; if ( ! StackSize ) return ; const auto * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; auto & MRI = MF . getRegInfo ( ) ; unsigned OffsetReg = MRI . createVirtualRegister ( & WebAssembly :: I32RegClass ) ; auto InsertPt = MBB . getFirstTerminator ( ) ; DebugLoc DL ; if ( InsertPt != MBB . end ( ) ) { DL = InsertPt -> getDebugLoc ( ) ; } BuildMI ( MBB , InsertPt , DL , TII -> get ( WebAssembly :: CONST_I32 ) , OffsetReg ) . addImm ( StackSize ) ; auto * SPSymbol = MF . createExternalSymbolName ( "__stack_pointer" ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( WebAssembly :: ADD_I32 ) , WebAssembly :: SP32 ) . addReg ( WebAssembly :: SP32 ) . addReg ( OffsetReg ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( WebAssembly :: CONST_I32 ) , OffsetReg ) . addExternalSymbol ( SPSymbol ) ; auto * MMO = new MachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOStore , 4 , 4 ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( WebAssembly :: STORE_I32 ) , WebAssembly :: SP32 ) . addImm ( 0 ) . addReg ( OffsetReg ) . addReg ( WebAssembly :: SP32 ) . addMemOperand ( MMO ) ; } </s>


<s> void X86PassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createX86OptimizeLEAs ( ) ) ; addPass ( createX86CallFrameOptimization ( ) ) ; } </s>


<s> BitVector HexagonRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( HEXAGON_RESERVED_REG_1 ) ; Reserved . set ( HEXAGON_RESERVED_REG_2 ) ; Reserved . set ( Hexagon :: R29 ) ; Reserved . set ( Hexagon :: R30 ) ; Reserved . set ( Hexagon :: R31 ) ; Reserved . set ( Hexagon :: PC ) ; Reserved . set ( Hexagon :: D15 ) ; Reserved . set ( Hexagon :: LC0 ) ; Reserved . set ( Hexagon :: LC1 ) ; Reserved . set ( Hexagon :: SA0 ) ; Reserved . set ( Hexagon :: SA1 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s>
SDNode
*
MBlazeDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
DebugLoc
dl
=
Node
->
getDebugLoc
(
)
;
if
(
Node
->
isMachineOpcode
(
)
)
return
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
return
getGlobalBaseReg
(
)
;
case
ISD
::
FrameIndex
:
{
SDValue
imm
=
CurDAG
->
getTargetConstant
(
0
,
MVT
::
i32
)
;
int
FI
=
dyn_cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
EVT
VT
=
Node
->
getValueType
(
0
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
VT
)
;
unsigned
Opc
=
MBlaze
::
ADDI
;
if
(
Node
->
hasOneUse
(
)
)
return
CurDAG
->
SelectNodeTo
(
Node
,
Opc
,
VT
,
TFI
,
imm
)
;
return
CurDAG
->
getMachineNode
(
Opc
,
dl
,
VT
,
TFI
,
imm
)
;
}
case
MBlazeISD
::
JmpLink
:
{
if
(
TM
.
getRelocationModel
(
)
==
Reloc
::
PIC_
)
{
SDValue
Chain
=
Node
->
getOperand
(
0
)
;
SDValue
Callee
=
Node
->
getOperand
(
1
)
;
SDValue
R20Reg
=
CurDAG
->
getRegister
(
MBlaze
::
R20
,
MVT
::
i32
)
;
SDValue
InFlag
(
0
,
0
)
;
if
(
(
isa
<
GlobalAddressSDNode
>
(
Callee
)
)
||
(
isa
<
ExternalSymbolSDNode
>
(
Callee
)
)
)
{
SDValue
GPReg
=
CurDAG
->
getRegister
(
MBlaze
::
R15
,
MVT
::
i32
)
;
SDValue
Ops
[
]
=
{
Callee
,
GPReg
,
Chain
}
;
SDValue
Load
=
SDValue
(
CurDAG
->
getMachineNode
(
MBlaze
::
LW
,
dl
,
MVT
::
i32
,
MVT
::
Other
,
Ops
,
3
)
,
0
)
;
Chain
=
Load
.
getValue
(
1
)
;
Chain
=
CurDAG
->
getCopyToReg
(
Chain
,
dl
,
R20Reg
,
Load
,
InFlag
)
;
}
else
Chain
=
CurDAG
->
getCopyToReg
(
Chain
,
dl
,
R20Reg
,
Callee
,
InFlag
)
;
SDNode
*
ResNode
=
CurDAG
->
getMachineNode
(
MBlaze
::
BRLID
,
dl
,
MVT
::
Other
,
MVT
::
Flag
,
R20Reg
,
Chain
)
;
Chain
=
SDValue
(
ResNode
,
0
)
;
InFlag
=
SDValue
(
ResNode
,
1
)
;
ReplaceUses
(
SDValue
(
Node
,
0
)
,
Chain
)
;
ReplaceUses
(
SDValue
(
Node
,
1
)
,
InFlag
)
;
return
ResNode
;
}
}
}
SDNode
*
ResNode
=
SelectCode
(
Node
)
;
DEBUG
(
errs
(
)
<<
"=> "
)
;
if
(
ResNode
==
||
ResNode
==
Node
)
DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
else
DEBUG
(
ResNode
->
dump
(
CurDAG
)
)
;
DEBUG
(
errs
(
)
<<
"\n"
)
;
return
ResNode
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> bool nds32_n13_e2_to_e1_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx def_reg ; switch ( get_attr_type ( producer ) ) { case TYPE_LOAD : case TYPE_STORE : case TYPE_LOAD_MULTIPLE : case TYPE_STORE_MULTIPLE : if ( ! post_update_insn_p ( producer ) ) return false ; def_reg = extract_base_reg ( producer ) ; break ; case TYPE_ALU : case TYPE_ALU_SHIFT : case TYPE_PBSAD : case TYPE_PBSADA : case TYPE_MUL : case TYPE_MAC : def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; case TYPE_BRANCH : return true ; case TYPE_DIV : if ( divmod_p ( producer ) ) { rtx def_reg1 = SET_DEST ( parallel_element ( producer , 0 ) ) ; rtx def_reg2 = SET_DEST ( parallel_element ( producer , 1 ) ) ; return ( n13_consumed_by_e1_dep_p ( consumer , def_reg1 ) || n13_consumed_by_e1_dep_p ( consumer , def_reg2 ) ) ; } def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; default : gcc_unreachable ( ) ; } return n13_consumed_by_e1_dep_p ( consumer , def_reg ) ; } </s>


"Only support MVT::i32 register passing"

"Can only pass arguments as either registers or via the stack"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> const Cpu0InstrInfo * getInstrInfo ( ) const override { return InstrInfo . get ( ) ; } </s>


<s> bool isUnconditionalBranch ( const MCInst & Inst ) const override { if ( Inst . getOpcode ( ) == AArch64 :: Bcc && Inst . getOperand ( 0 ) . getImm ( ) == A64CC :: AL ) return true ; return MCInstrAnalysis :: isUnconditionalBranch ( Inst ) ; } </s>

Return true if this is a branch which always transfers control flow to some other block .


<s>
bool
AMDGPUAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
setForcedEncodingSize
(
0
)
;
if
(
Name
.
endswith
(
"_e64"
)
)
setForcedEncodingSize
(
64
)
;
else
if
(
Name
.
endswith
(
"_e32"
)
)
setForcedEncodingSize
(
32
)
;
Operands
.
push_back
(
AMDGPUOperand
::
CreateToken
(
Name
,
NameLoc
)
)
;
if
(
Name
.
endswith
(
"_e64"
)
)
{
Name
=
Name
.
substr
(
0
,
Name
.
size
(
)
4
)
;
}
if
(
Name
.
endswith
(
"_e32"
)
)
{
Name
=
Name
.
substr
(
0
,
Name
.
size
(
)
4
)
;
}
while
(
!
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
{
AMDGPUAsmParser
::
OperandMatchResultTy
Res
=
parseOperand
(
Operands
,
Name
)
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
Parser
.
Lex
(
)
;
switch
(
Res
)
{
case
MatchOperand_Success
:
break
;
case
MatchOperand_ParseFail
:
Error
(
getLexer
(
)
.
getLoc
(
)
,
"failed parsing operand."
)
;
while
(
!
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
{
Parser
.
Lex
(
)
;
}
return
true
;
case
MatchOperand_NoMatch
:
Error
(
getLexer
(
)
.
getLoc
(
)
,
"not a valid operand."
)
;
while
(
!
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
{
Parser
.
Lex
(
)
;
}
return
true
;
}
}
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .


<s> void nvptx_output_skip ( FILE * , unsigned HOST_WIDE_INT size ) { if ( decl_offset + size >= object_size ) { if ( decl_offset % decl_chunk_size != 0 ) nvptx_assemble_value ( 0 , decl_chunk_size ) ; object_finished = true ; return ; } while ( size > decl_chunk_size ) { nvptx_assemble_value ( 0 , decl_chunk_size ) ; size -= decl_chunk_size ; } while ( size -- > 0 ) nvptx_assemble_value ( 0 , 1 ) ; } </s>

Output SIZE zero bytes . We ignore the FILE argument since the functions we 're calling to perform the output just use asm_out_file .


<s> bool SIInsertNops :: runOnMachineFunction ( MachineFunction & MF ) { const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; DenseMap < unsigned , MachineBasicBlock :: iterator > LineToInst ; for ( auto MBB = MF . begin ( ) ; MBB != MF . end ( ) ; ++ MBB ) { for ( auto MI = MBB -> begin ( ) ; MI != MBB -> end ( ) ; ++ MI ) { if ( MI -> isDebugValue ( ) || ! MI -> getDebugLoc ( ) ) { continue ; } auto DL = MI -> getDebugLoc ( ) ; auto CL = DL . getLine ( ) ; auto LineToInstEntry = LineToInst . find ( CL ) ; if ( LineToInstEntry == LineToInst . end ( ) ) { BuildMI ( * MBB , * MI , DL , TII -> get ( AMDGPU :: S_NOP ) ) . addImm ( 0 ) ; LineToInst . insert ( std :: make_pair ( CL , MI ) ) ; } else { LineToInstEntry -> second = MI ; } } } for ( auto LineToInstEntry = LineToInst . begin ( ) ; LineToInstEntry != LineToInst . end ( ) ; ++ LineToInstEntry ) { auto MBB = LineToInstEntry -> second -> getParent ( ) ; auto DL = LineToInstEntry -> second -> getDebugLoc ( ) ; MachineBasicBlock :: iterator MI = LineToInstEntry -> second ; ++ MI ; if ( MI != MBB -> end ( ) ) { BuildMI ( * MBB , * MI , DL , TII -> get ( AMDGPU :: S_NOP ) ) . addImm ( 0 ) ; } } MachineBasicBlock & MBB = MF . front ( ) ; MachineInstr & MI = MBB . front ( ) ; BuildMI ( MBB , MI , DebugLoc ( ) , TII -> get ( AMDGPU :: S_NOP ) ) . addImm ( 0 ) ; return true ; } </s>


<s> Register getGlobalBaseReg ( ) const { return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s>
void
ARMBaseInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
DebugLoc
::
getUnknownLoc
(
)
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
unsigned
Align
=
MFI
.
getObjectAlignment
(
FI
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
PseudoSourceValue
::
getFixedStack
(
FI
)
,
MachineMemOperand
::
MOStore
,
0
,
MFI
.
getObjectSize
(
FI
)
,
Align
)
;
if
(
RC
==
ARM
::
tGPRRegisterClass
)
RC
=
ARM
::
GPRRegisterClass
;
if
(
RC
==
ARM
::
GPRRegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
STR
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addReg
(
0
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
else
if
(
RC
==
ARM
::
DPRRegisterClass
||
RC
==
ARM
::
DPR_VFP2RegisterClass
||
RC
==
ARM
::
DPR_8RegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
VSTRD
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
else
if
(
RC
==
ARM
::
SPRRegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
VSTRS
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
else
{
assert
(
(
RC
==
ARM
::
QPRRegisterClass
||
RC
==
ARM
::
QPR_VFP2RegisterClass
)
&&
"Unknown regclass!"
)
;
if
(
Align
>=
16
&&
(
getRegisterInfo
(
)
.
canRealignStack
(
MF
)
)
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
VST1q64
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addImm
(
0
)
.
addImm
(
128
)
.
addMemOperand
(
MMO
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
)
;
}
else
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
VSTRQ
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> static void * rs6000_alloc_sched_context ( void ) { return xmalloc ( sizeof ( rs6000_sched_context_def ) ) ; } </s>

Allocate store for new scheduling context .


"ReadCycleWrite is only to be used on riscv32"

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( 1 , true , true , false , true ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedLoadCombinePass ( ) ) ; addPass ( createInterleavedAccessPass ( ) ) ; } if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } addPass ( createAArch64StackTaggingPass ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardCheckPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static void mcore_print_operand ( FILE * stream , rtx x , int code ) { switch ( code ) { case 'N' : if ( INTVAL ( x ) == - 1 ) fprintf ( asm_out_file , "32" ) ; else fprintf ( asm_out_file , "%d" , exact_log2 ( INTVAL ( x ) + 1 ) ) ; break ; case 'P' : fprintf ( asm_out_file , "%d" , exact_log2 ( INTVAL ( x ) & 0xffffffff ) ) ; break ; case 'Q' : fprintf ( asm_out_file , "%d" , exact_log2 ( ~ INTVAL ( x ) ) ) ; break ; case 'O' : fprintf ( asm_out_file , HOST_WIDE_INT_PRINT_DEC , INTVAL ( x ) ) ; break ; case 'M' : fprintf ( asm_out_file , HOST_WIDE_INT_PRINT_DEC , - INTVAL ( x ) ) ; break ; case 'R' : switch ( GET_CODE ( x ) ) { case REG : fputs ( reg_names [ REGNO ( x ) + 1 ] , ( stream ) ) ; break ; case MEM : mcore_print_operand_address ( stream , GET_MODE ( x ) , XEXP ( adjust_address ( x , SImode , 4 ) , 0 ) ) ; break ; default : gcc_unreachable ( ) ; } break ; case 'U' : fprintf ( asm_out_file , "%s-%s" , reg_names [ REGNO ( x ) ] , reg_names [ REGNO ( x ) + 3 ] ) ; break ; case 'x' : fprintf ( asm_out_file , HOST_WIDE_INT_PRINT_HEX , INTVAL ( x ) ) ; break ; case 'X' : fprintf ( asm_out_file , HOST_WIDE_INT_PRINT_DEC , 3 - INTVAL ( x ) / 8 ) ; break ; default : switch ( GET_CODE ( x ) ) { case REG : fputs ( reg_names [ REGNO ( x ) ] , ( stream ) ) ; break ; case MEM : output_address ( GET_MODE ( x ) , XEXP ( x , 0 ) ) ; break ; default : output_addr_const ( stream , x ) ; break ; } break ; } } </s>

Print operand x ( an rtx ) in assembler syntax to file stream according to modifier code . ' R ' print the next register or memory location along , ie the lsw in a double word value ' O ' print a constant without the # 'M ' print a constant as its negative ' P ' print log2 of a power of two ' Q ' print log2 of an inverse of a power of two ' U ' print register for ldm/stm instruction ' X ' print byte number for xtrbN instruction .


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( CommentStream ) HasCustomInstComment = EmitAnyX86InstComments ( MI , * CommentStream , getRegisterName ) ; if ( TSFlags & X86II :: LOCK ) OS << "\tlock\t" ; if ( MI -> getOpcode ( ) == X86 :: CALLpcrel32 && ( STI . getFeatureBits ( ) [ X86 :: Mode64Bit ] ) ) { OS << "\tcallq\t" ; printPCRelImm ( MI , 0 , OS ) ; } else if ( MI -> getOpcode ( ) == X86 :: DATA16_PREFIX && ( STI . getFeatureBits ( ) [ X86 :: Mode16Bit ] ) ) { MCInst Data32MI ( * MI ) ; Data32MI . setOpcode ( X86 :: DATA32_PREFIX ) ; printInstruction ( & Data32MI , OS ) ; } else if ( ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static bool riscv_valid_lo_sum_p ( enum riscv_symbol_type sym_type , machine_mode mode ) { if ( riscv_symbol_insns ( sym_type ) == 0 ) return false ; if ( ! riscv_split_symbol_type ( sym_type ) ) return false ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && ( ! TARGET_STRICT_ALIGN || GET_MODE_BITSIZE ( mode ) > GET_MODE_ALIGNMENT ( mode ) ) ) return false ; return true ; } </s>

Return true if a LO_SUM can address a value of mode MODE when the LO_SUM symbol has type SYM_TYPE .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Local Dynamic TLS Access Clean-up"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Patmos Function Splitter"
;
}
</s>


"instruction requires a CPU feature not currently enabled"

"source and destination must be different"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> static void tilegx_trampoline_init ( rtx m_tramp , tree fndecl , rtx static_chain ) { rtx fnaddr , chaddr ; rtx mem ; rtx begin_addr , end_addr ; int ptr_mode_size = GET_MODE_SIZE ( ptr_mode ) ; fnaddr = copy_to_reg ( XEXP ( DECL_RTL ( fndecl ) , 0 ) ) ; chaddr = copy_to_reg ( static_chain ) ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp , ptr_mode , TRAMPOLINE_SIZE - 2 * ptr_mode_size ) ; emit_move_insn ( mem , fnaddr ) ; mem = adjust_address ( m_tramp , ptr_mode , TRAMPOLINE_SIZE - ptr_mode_size ) ; emit_move_insn ( mem , chaddr ) ; begin_addr = force_reg ( Pmode , XEXP ( m_tramp , 0 ) ) ; end_addr = force_reg ( Pmode , plus_constant ( Pmode , XEXP ( m_tramp , 0 ) , TRAMPOLINE_SIZE ) ) ; maybe_emit_call_builtin___clear_cache ( begin_addr , end_addr ) ; } </s>


<s> void BTFKindDataSec :: emitType ( MCStreamer & OS ) { BTFTypeBase :: emitType ( OS ) ; for ( const auto & V : Vars ) { OS . emitIntValue ( std :: get < 0 > ( V ) , 4 ) ; Asm -> emitLabelReference ( std :: get < 1 > ( V ) , 4 ) ; OS . emitIntValue ( std :: get < 2 > ( V ) , 4 ) ; } } </s>


<s> unsigned MipsCodeEmitter :: getJumpTargetOpValue ( const MachineInstr & MI , unsigned OpNo ) const { return 0 ; } </s>

getJumpTargetOpValue - Return binary encoding of the jump target operand .


<s>
const
char
*
nds32_output_16bit_load
(
rtx
*
operands
,
int
byte
)
{
char
pattern
[
100
]
;
unsigned
char
size
;
rtx
code
=
XEXP
(
operands
[
1
]
,
0
)
;
size
=
nds32_byte_to_size
(
byte
)
;
switch
(
nds32_mem_format
(
operands
[
1
]
)
)
{
case
ADDRESS_REG
:
operands
[
1
]
=
code
;
output_asm_insn
(
"lwi450\t%0, [%1]"
,
operands
)
;
break
;
case
ADDRESS_LO_REG_IMM3U
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%ci333\t%%0, %%1"
,
size
)
;
output_asm_insn
(
pattern
,
operands
)
;
break
;
case
ADDRESS_POST_INC_LO_REG_IMM3U
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"lwi333.bi\t%%0, %%1, 4"
)
;
output_asm_insn
(
pattern
,
operands
)
;
break
;
case
ADDRESS_POST_MODIFY_LO_REG_IMM3U
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"lwi333.bi\t%%0, %%1"
)
;
output_asm_insn
(
pattern
,
operands
)
;
break
;
case
ADDRESS_R8_IMM7U
:
output_asm_insn
(
"lwi45.fe\t%0, %e1"
,
operands
)
;
break
;
case
ADDRESS_FP_IMM7U
:
output_asm_insn
(
"lwi37\t%0, %1"
,
operands
)
;
break
;
case
ADDRESS_SP_IMM7U
:
operands
[
1
]
=
XEXP
(
code
,
1
)
;
output_asm_insn
(
"lwi37.sp\t%0, [ + (%1)]"
,
operands
)
;
break
;
default
:
break
;
}
return
""
;
}
</s>


<s> static unsigned bitmap_popcount ( const sbitmap bmap ) { unsigned int count = 0 ; unsigned int n = 0 ; sbitmap_iterator sbi ; EXECUTE_IF_SET_IN_BITMAP ( bmap , 0 , n , sbi ) count ++ ; return count ; } </s>


<s> bool M68kFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , MutableArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { auto & MRI = * static_cast < const M68kRegisterInfo * > ( TRI ) ; auto DL = MBB . findDebugLoc ( MI ) ; int FI = 0 ; unsigned Mask = 0 ; for ( const auto & Info : CSI ) { FI = std :: max ( FI , Info . getFrameIdx ( ) ) ; unsigned Reg = Info . getReg ( ) ; unsigned Shift = MRI . getSpillRegisterOrder ( Reg ) ; Mask |= 1 << Shift ; } auto I = M68k :: addFrameReference ( BuildMI ( MBB , MI , DL , TII . get ( M68k :: MOVM32mp ) ) . addImm ( Mask ) , FI ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; for ( const auto & Info : CSI ) { I . addReg ( Info . getReg ( ) , RegState :: ImplicitDefine ) ; M68k :: addMemOperand ( I , Info . getFrameIdx ( ) , 0 ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static int ix86_register_move_cost ( machine_mode mode , reg_class_t class1_i , reg_class_t class2_i ) { enum reg_class class1 = ( enum reg_class ) class1_i ; enum reg_class class2 = ( enum reg_class ) class2_i ; if ( inline_secondary_memory_needed ( mode , class1 , class2 , false ) ) { int cost = 1 ; cost += inline_memory_move_cost ( mode , class1 , 2 ) ; cost += inline_memory_move_cost ( mode , class2 , 2 ) ; if ( GET_MODE_BITSIZE ( mode ) > BITS_PER_WORD && TARGET_MEMORY_MISMATCH_STALL && targetm . class_max_nregs ( class1 , mode ) > targetm . class_max_nregs ( class2 , mode ) ) cost += 20 ; if ( ( MMX_CLASS_P ( class1 ) && MAYBE_FLOAT_CLASS_P ( class2 ) ) || ( MMX_CLASS_P ( class2 ) && MAYBE_FLOAT_CLASS_P ( class1 ) ) ) cost += 20 ; return cost ; } if ( MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class2 ) || SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class2 ) ) return MAX ( 8 , MMX_CLASS_P ( class1 ) || MMX_CLASS_P ( class2 ) ? ix86_cost -> mmxsse_to_integer : ix86_cost -> ssemmx_to_integer ) ; if ( MAYBE_FLOAT_CLASS_P ( class1 ) ) return ix86_cost -> fp_move ; if ( MAYBE_SSE_CLASS_P ( class1 ) ) { if ( GET_MODE_BITSIZE ( mode ) <= 128 ) return ix86_cost -> xmm_move ; if ( GET_MODE_BITSIZE ( mode ) <= 256 ) return ix86_cost -> ymm_move ; return ix86_cost -> zmm_move ; } if ( MAYBE_MMX_CLASS_P ( class1 ) ) return ix86_cost -> mmx_move ; return 2 ; } </s>

Return the cost of moving data from a register in class CLASS1 to one in class CLASS2 . It is not required that the cost always equal 2 when FROM is the same as TO ; on some machines it is expensive to move between registers if they are not general registers .


<s>
bool
AMDGPUAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Name
=
parseMnemonicSuffix
(
Name
)
;
Operands
.
push_back
(
AMDGPUOperand
::
CreateToken
(
this
,
Name
,
NameLoc
)
)
;
bool
IsMIMG
=
Name
.
startswith
(
"image_"
)
;
while
(
!
trySkipToken
(
AsmToken
::
EndOfStatement
)
)
{
OperandMode
Mode
=
OperandMode_Default
;
if
(
IsMIMG
&&
isGFX10Plus
(
)
&&
Operands
.
size
(
)
==
2
)
Mode
=
OperandMode_NSA
;
OperandMatchResultTy
Res
=
parseOperand
(
Operands
,
Name
,
Mode
)
;
trySkipToken
(
AsmToken
::
Comma
)
;
if
(
Res
!=
MatchOperand_Success
)
{
checkUnsupportedInstruction
(
Name
,
NameLoc
)
;
if
(
!
Parser
.
hasPendingError
(
)
)
{
StringRef
Msg
=
(
Res
==
MatchOperand_ParseFail
)
"failed parsing operand."
:
"not a valid operand."
;
Error
(
getLoc
(
)
,
Msg
)
;
}
while
(
!
trySkipToken
(
AsmToken
::
EndOfStatement
)
)
{
lex
(
)
;
}
return
true
;
}
}
return
false
;
}
</s>

AMDGPU
AMDGPU
AMDGPU
"image_"
2
"failed parsing operand."
"not a valid operand."


<s> unsigned TOYInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case TOY :: LOADrr : if ( MI -> getOperand ( 1 ) . isFI ( ) ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> static bool isIdentity ( ArrayRef < int > Mask ) { for ( int I = 0 , E = Mask . size ( ) ; I != E ; ++ I ) { int M = Mask [ I ] ; if ( M >= 0 && M != I ) return false ; } return true ; } </s>

Return true if this shuffle chooses elements from exactly one source vector without lane crossings and does not change the number of elements from its input vectors .


<s> bool HexagonFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; if ( CSI . empty ( ) ) { return false ; } bool ContiguousRegs = true ; for ( unsigned i = 0 ; i < CSI . size ( ) ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; unsigned SuperReg = uniqueSuperReg ( Reg , TRI ) ; bool CanUseDblStore = false ; const TargetRegisterClass * SuperRegClass = nullptr ; if ( ContiguousRegs && ( i < CSI . size ( ) - 1 ) ) { unsigned SuperRegNext = uniqueSuperReg ( CSI [ i + 1 ] . getReg ( ) , TRI ) ; SuperRegClass = TRI -> getMinimalPhysRegClass ( SuperReg ) ; CanUseDblStore = ( SuperRegNext == SuperReg ) ; } if ( CanUseDblStore ) { TII . storeRegToStackSlot ( MBB , MI , SuperReg , true , CSI [ i + 1 ] . getFrameIdx ( ) , SuperRegClass , TRI ) ; MBB . addLiveIn ( SuperReg ) ; ++ i ; } else { ContiguousRegs = false ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; MBB . addLiveIn ( Reg ) ; } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> bool PPCTargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const { return isInt < 16 > ( Imm ) || isUInt < 16 > ( Imm ) ; } </s>

Return true if the specified immediate is legal icmp immediate , that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register .


<s> static int visium_save_reg_p ( int interrupt , int regno ) { switch ( regno ) { case HARD_FRAME_POINTER_REGNUM : return 0 ; case MDC_REGNUM : break ; case 29 : case 30 : return ( interrupt != 0 ) ; default : if ( fixed_regs [ regno ] ) return 0 ; break ; } if ( interrupt ) { if ( crtl -> is_leaf ) { if ( df_regs_ever_live_p ( regno ) ) return 1 ; } else if ( call_used_regs [ regno ] ) return 1 ; if ( regno == PROLOGUE_TMP_REGNUM ) { if ( df_regs_ever_live_p ( MDB_REGNUM ) || df_regs_ever_live_p ( MDC_REGNUM ) ) return 1 ; for ( int i = FP_FIRST_REGNUM ; i <= FP_LAST_REGNUM ; i ++ ) if ( df_regs_ever_live_p ( i ) ) return 1 ; } else if ( regno == PROLOGUE_TMP_REGNUM + 1 ) { if ( df_regs_ever_live_p ( MDB_REGNUM ) ) return 1 ; } } return df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ; } </s>

Return non-zero if register REGNO needs to be saved in the frame .


<s> bool SystemZInstrInfo :: FoldImmediate ( MachineInstr & UseMI , MachineInstr & DefMI , unsigned Reg , MachineRegisterInfo * MRI ) const { unsigned DefOpc = DefMI . getOpcode ( ) ; if ( DefOpc != SystemZ :: LHIMux && DefOpc != SystemZ :: LHI && DefOpc != SystemZ :: LGHI ) return false ; if ( DefMI . getOperand ( 0 ) . getReg ( ) != Reg ) return false ; int32_t ImmVal = ( int32_t ) DefMI . getOperand ( 1 ) . getImm ( ) ; unsigned UseOpc = UseMI . getOpcode ( ) ; unsigned NewUseOpc ; unsigned UseIdx ; int CommuteIdx = - 1 ; bool TieOps = false ; switch ( UseOpc ) { case SystemZ :: SELRMux : TieOps = true ; LLVM_FALLTHROUGH ; case SystemZ :: LOCRMux : if ( ! STI . hasLoadStoreOnCond2 ( ) ) return false ; NewUseOpc = SystemZ :: LOCHIMux ; if ( UseMI . getOperand ( 2 ) . getReg ( ) == Reg ) UseIdx = 2 ; else if ( UseMI . getOperand ( 1 ) . getReg ( ) == Reg ) UseIdx = 2 , CommuteIdx = 1 ; else return false ; break ; case SystemZ :: SELGR : TieOps = true ; LLVM_FALLTHROUGH ; case SystemZ :: LOCGR : if ( ! STI . hasLoadStoreOnCond2 ( ) ) return false ; NewUseOpc = SystemZ :: LOCGHI ; if ( UseMI . getOperand ( 2 ) . getReg ( ) == Reg ) UseIdx = 2 ; else if ( UseMI . getOperand ( 1 ) . getReg ( ) == Reg ) UseIdx = 2 , CommuteIdx = 1 ; else return false ; break ; default : return false ; } if ( CommuteIdx != - 1 ) if ( ! commuteInstruction ( UseMI , false , CommuteIdx , UseIdx ) ) return false ; bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ; UseMI . setDesc ( get ( NewUseOpc ) ) ; if ( TieOps ) UseMI . tieOperands ( 0 , 1 ) ; UseMI . getOperand ( UseIdx ) . ChangeToImmediate ( ImmVal ) ; if ( DeleteDef ) DefMI . eraseFromParent ( ) ; return true ; } </s>

Reg is known to be defined by a move immediate instruction , try to fold the immediate into the use instruction .


<s> static void ia64_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int words = ia64_function_arg_words ( arg . type , arg . mode ) ; int offset = ia64_function_arg_offset ( cum , arg . type , words ) ; machine_mode hfa_mode = VOIDmode ; if ( cum -> words >= MAX_ARGUMENT_SLOTS ) { cum -> words += words + offset ; return ; } cum -> atypes [ cum -> words ] = ia64_arg_type ( arg . mode ) ; cum -> words += words + offset ; if ( TARGET_ABI_OPEN_VMS ) { cum -> int_regs = cum -> words ; cum -> fp_regs = cum -> words ; return ; } if ( arg . type ) hfa_mode = hfa_element_mode ( arg . type , 0 ) ; if ( hfa_mode != VOIDmode && ( ! cum -> prototype || arg . named ) ) { int fp_regs = cum -> fp_regs ; int int_regs = cum -> words - words ; int hfa_size = GET_MODE_SIZE ( hfa_mode ) ; int byte_size ; int args_byte_size ; byte_size = arg . promoted_size_in_bytes ( ) ; args_byte_size = int_regs * UNITS_PER_WORD ; offset = 0 ; for ( ; ( offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS && args_byte_size < ( MAX_ARGUMENT_SLOTS * UNITS_PER_WORD ) ) ; ) { offset += hfa_size ; args_byte_size += hfa_size ; fp_regs ++ ; } cum -> fp_regs = fp_regs ; } else if ( arg . mode == TFmode || arg . mode == TCmode || ! FLOAT_MODE_P ( arg . mode ) || cum -> fp_regs == MAX_ARGUMENT_SLOTS ) cum -> int_regs = cum -> words ; else if ( cum -> prototype ) { if ( ! arg . named ) cum -> int_regs = cum -> words ; else cum -> fp_regs += ( GET_MODE_CLASS ( arg . mode ) == MODE_COMPLEX_FLOAT ? 2 : 1 ) ; } else { cum -> fp_regs += ( GET_MODE_CLASS ( arg . mode ) == MODE_COMPLEX_FLOAT ? 2 : 1 ) ; cum -> int_regs = cum -> words ; } } </s>

Update CUM to point after this argument . This is patterned after ia64_function_arg .


<s> bool isLegalBroadcastLoad ( Type * ElementTy , ElementCount NumElements ) const { if ( ! ST -> hasNEON ( ) || NumElements . isScalable ( ) ) return false ; switch ( unsigned ElementBits = ElementTy -> getScalarSizeInBits ( ) ) { case 8 : case 16 : case 32 : case 64 : { unsigned VectorBits = NumElements . getFixedValue ( ) * ElementBits ; return VectorBits >= 64 ; } } return false ; } </s>

\Returns true if the target supports broadcasting a load to a vector of type < NumElements x ElementTy > .


<s> unsigned PPCTargetLowering :: getPrefLoopAlignment ( MachineLoop * ML ) const { switch ( Subtarget . getDarwinDirective ( ) ) { default : break ; case PPC :: DIR_970 : case PPC :: DIR_PWR4 : case PPC :: DIR_PWR5 : case PPC :: DIR_PWR5X : case PPC :: DIR_PWR6 : case PPC :: DIR_PWR6X : case PPC :: DIR_PWR7 : case PPC :: DIR_PWR8 : case PPC :: DIR_PWR9 : { if ( ! ML ) break ; if ( ! DisableInnermostLoopAlign32 ) { if ( ML -> getLoopDepth ( ) > 1 && ML -> getSubLoops ( ) . empty ( ) ) return 5 ; } const PPCInstrInfo * TII = Subtarget . getInstrInfo ( ) ; uint64_t LoopSize = 0 ; for ( auto I = ML -> block_begin ( ) , IE = ML -> block_end ( ) ; I != IE ; ++ I ) for ( auto J = ( * I ) -> begin ( ) , JE = ( * I ) -> end ( ) ; J != JE ; ++ J ) { LoopSize += TII -> getInstSizeInBytes ( * J ) ; if ( LoopSize > 32 ) break ; } if ( LoopSize > 16 && LoopSize <= 32 ) return 5 ; break ; } } return TargetLowering :: getPrefLoopAlignment ( ML ) ; } </s>


<s> static void aarch64_push_regs ( unsigned regno1 , unsigned regno2 , HOST_WIDE_INT adjustment ) { rtx_insn * insn ; machine_mode mode = aarch64_reg_save_mode ( cfun -> decl , regno1 ) ; if ( regno2 == INVALID_REGNUM ) return aarch64_pushwb_single_reg ( mode , regno1 , adjustment ) ; rtx reg1 = gen_rtx_REG ( mode , regno1 ) ; rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; insn = emit_insn ( aarch64_gen_storewb_pair ( mode , stack_pointer_rtx , reg1 , reg2 , adjustment ) ) ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , 0 , 2 ) ) = 1 ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , 0 , 1 ) ) = 1 ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Push registers numbered REGNO1 and REGNO2 to the stack , adjusting the stack pointer by ADJUSTMENT .


<s> MCSection * X86WindowsTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C ) const { if ( Kind . isMergeableConst ( ) && C ) { const unsigned Characteristics = COFF :: IMAGE_SCN_CNT_INITIALIZED_DATA | COFF :: IMAGE_SCN_MEM_READ | COFF :: IMAGE_SCN_LNK_COMDAT ; std :: string COMDATSymName ; if ( Kind . isMergeableConst4 ( ) || Kind . isMergeableConst8 ( ) ) COMDATSymName = "__real@" + scalarConstantToHexString ( C ) ; else if ( Kind . isMergeableConst16 ( ) ) COMDATSymName = "__xmm@" + scalarConstantToHexString ( C ) ; if ( ! COMDATSymName . empty ( ) ) return getContext ( ) . getCOFFSection ( ".rdata" , Characteristics , Kind , COMDATSymName , COFF :: IMAGE_COMDAT_SELECT_ANY ) ; } return TargetLoweringObjectFile :: getSectionForConstant ( DL , Kind , C ) ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> static rtx or1k_libcall_value ( machine_mode mode , const_rtx ) { return gen_rtx_REG ( mode , RV_REGNUM ) ; } </s>

Worker for TARGET_LIBCALL_VALUE . Returns an RTX representing the location where function return values to external libraries will be stored . On OpenRISC this the same as local function calls .


<s> void PPCLinuxAsmPrinter :: emitFunctionBodyStart ( ) { if ( Subtarget -> isELFv2ABI ( ) && ! MF -> getRegInfo ( ) . use_empty ( PPC :: X2 ) ) { const PPCFunctionInfo * PPCFI = MF -> getInfo < PPCFunctionInfo > ( ) ; MCSymbol * GlobalEntryLabel = PPCFI -> getGlobalEPSymbol ( ) ; OutStreamer -> emitLabel ( GlobalEntryLabel ) ; const MCSymbolRefExpr * GlobalEntryLabelExp = MCSymbolRefExpr :: create ( GlobalEntryLabel , OutContext ) ; if ( TM . getCodeModel ( ) != CodeModel :: Large ) { MCSymbol * TOCSymbol = OutContext . getOrCreateSymbol ( StringRef ( ".TOC." ) ) ; const MCExpr * TOCDeltaExpr = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( TOCSymbol , OutContext ) , GlobalEntryLabelExp , OutContext ) ; const MCExpr * TOCDeltaHi = PPCMCExpr :: createHa ( TOCDeltaExpr , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( PPC :: ADDIS ) . addReg ( PPC :: X2 ) . addReg ( PPC :: X12 ) . addExpr ( TOCDeltaHi ) ) ; const MCExpr * TOCDeltaLo = PPCMCExpr :: createLo ( TOCDeltaExpr , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( PPC :: ADDI ) . addReg ( PPC :: X2 ) . addReg ( PPC :: X2 ) . addExpr ( TOCDeltaLo ) ) ; } else { MCSymbol * TOCOffset = PPCFI -> getTOCOffsetSymbol ( ) ; const MCExpr * TOCOffsetDeltaExpr = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( TOCOffset , OutContext ) , GlobalEntryLabelExp , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( PPC :: LD ) . addReg ( PPC :: X2 ) . addExpr ( TOCOffsetDeltaExpr ) . addReg ( PPC :: X12 ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( PPC :: ADD8 ) . addReg ( PPC :: X2 ) . addReg ( PPC :: X2 ) . addReg ( PPC :: X12 ) ) ; } MCSymbol * LocalEntryLabel = PPCFI -> getLocalEPSymbol ( ) ; OutStreamer -> emitLabel ( LocalEntryLabel ) ; const MCSymbolRefExpr * LocalEntryLabelExp = MCSymbolRefExpr :: create ( LocalEntryLabel , OutContext ) ; const MCExpr * LocalOffsetExp = MCBinaryExpr :: createSub ( LocalEntryLabelExp , GlobalEntryLabelExp , OutContext ) ; PPCTargetStreamer * TS = static_cast < PPCTargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; if ( TS ) TS -> emitLocalEntry ( cast < MCSymbolELF > ( CurrentFnSym ) , LocalOffsetExp ) ; } } </s>

Targets can override this to emit stuff before the first basic block in the function .


<s> void reverseBlock ( unsigned From = 0 ) { std :: reverse ( Blocks . begin ( ) + From , Blocks . end ( ) ) ; } </s>

interface to reverse Blocks [ from , end of loop ] in this loop


<s> static rsqrte_type get_rsqrte_type ( machine_mode mode ) { switch ( mode ) { case DFmode : return gen_aarch64_rsqrtedf ; case SFmode : return gen_aarch64_rsqrtesf ; case V2DFmode : return gen_aarch64_rsqrtev2df ; case V2SFmode : return gen_aarch64_rsqrtev2sf ; case V4SFmode : return gen_aarch64_rsqrtev4sf ; default : gcc_unreachable ( ) ; } } </s>

Select reciprocal square root initial estimate insn depending on machine mode .


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> bool ARMAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == ".word" ) return parseDirectiveWord ( 4 , DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".thumb" ) return parseDirectiveThumb ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".arm" ) return parseDirectiveARM ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".thumb_func" ) return parseDirectiveThumbFunc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".code" ) return parseDirectiveCode ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".syntax" ) return parseDirectiveSyntax ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".unreq" ) return parseDirectiveUnreq ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".arch" ) return parseDirectiveArch ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".eabi_attribute" ) return parseDirectiveEabiAttr ( DirectiveID . getLoc ( ) ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> static void rs6000_free_sched_context ( void * _sc ) { gcc_assert ( _sc != NULL ) ; free ( _sc ) ; } </s>


<s> static rtx h8300_function_arg ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; static const char * const hand_list [ ] = { "__main" , "__cmpsi2" , "__divhi3" , "__modhi3" , "__udivhi3" , "__umodhi3" , "__divsi3" , "__modsi3" , "__udivsi3" , "__umodsi3" , "__mulhi3" , "__mulsi3" , "__reg_memcpy" , "__reg_memset" , "__ucmpsi2" , 0 , } ; rtx result = NULL_RTX ; const char * fname ; int regpass = 0 ; if ( ! arg . named ) return NULL_RTX ; if ( TARGET_QUICKCALL ) regpass = 3 ; if ( cum -> libcall ) { const char * const * p ; fname = XSTR ( cum -> libcall , 0 ) ; for ( p = hand_list ; * p && strcmp ( * p , fname ) != 0 ; p ++ ) ; if ( * p ) regpass = 4 ; } if ( regpass ) { int size = arg . promoted_size_in_bytes ( ) ; if ( size + cum -> nbytes <= regpass * UNITS_PER_WORD && cum -> nbytes / UNITS_PER_WORD <= 3 ) result = gen_rtx_REG ( arg . mode , cum -> nbytes / UNITS_PER_WORD ) ; } return result ; } </s>

If the next function argument with MODE and TYPE is to be passed in a register , return a reg RTX for the hard register in which to pass the argument . CUM represents the state after the last argument . If the argument is to be pushed , NULL_RTX is returned . On the H8/300 all normal args are pushed , unless -mquickcall in which case the first 3 arguments are passed in registers .


"function_arg_pass_by_reference: V4 IEEE 128-bit\n"

"non-standard ABI extension with no compatibility "

A C expression that indicates when an argument must be passed by reference . If nonzero for an argument , a copy of that argument is made in memory and a pointer to the argument is passed instead of the argument itself . The pointer is passed in whatever way is appropriate for passing a pointer to that type . Under V.4 , aggregates and long double are passed by reference . As an extension to all 32-bit ABIs , AltiVec vectors are passed by reference unless the AltiVec vector extension ABI is in force . As an extension to all ABIs , variable sized types are passed by reference .


<s> void i386_pe_seh_unwind_emit ( FILE * asm_out_file , rtx_insn * insn ) { rtx note , pat ; bool handled_one = false ; struct seh_frame_state * seh ; if ( ! TARGET_SEH ) return ; seh = cfun -> machine -> seh ; if ( NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_SWITCH_TEXT_SECTIONS ) { rtx_insn * prev = prev_active_insn ( insn ) ; if ( prev && ! insn_nothrow_p ( prev ) ) fputs ( "\tnop\n" , asm_out_file ) ; fputs ( "\t.seh_endproc\n" , asm_out_file ) ; seh -> in_cold_section = true ; return ; } if ( NOTE_P ( insn ) || ! RTX_FRAME_RELATED_P ( insn ) ) return ; if ( seh -> after_prologue ) return ; for ( note = REG_NOTES ( insn ) ; note ; note = XEXP ( note , 1 ) ) { switch ( REG_NOTE_KIND ( note ) ) { case REG_FRAME_RELATED_EXPR : pat = XEXP ( note , 0 ) ; goto found ; case REG_CFA_DEF_CFA : case REG_CFA_EXPRESSION : gcc_unreachable ( ) ; break ; case REG_CFA_REGISTER : gcc_unreachable ( ) ; case REG_CFA_ADJUST_CFA : pat = XEXP ( note , 0 ) ; if ( pat == NULL ) { pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , 0 , 0 ) ; } seh_cfa_adjust_cfa ( asm_out_file , seh , pat ) ; handled_one = true ; break ; case REG_CFA_OFFSET : pat = XEXP ( note , 0 ) ; if ( pat == NULL ) pat = single_set ( insn ) ; seh_cfa_offset ( asm_out_file , seh , pat ) ; handled_one = true ; break ; default : break ; } } if ( handled_one ) return ; pat = PATTERN ( insn ) ; found : seh_frame_related_expr ( asm_out_file , seh , pat ) ; } </s>

This function looks at a single insn and emits any SEH directives required for unwind of this insn .


<s> unsigned Nios2RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return 0 ; } </s>


<s> static bool global_reg_mentioned_p ( rtx x ) { if ( INSN_P ( x ) ) { if ( CALL_P ( x ) ) { if ( ! RTL_CONST_OR_PURE_CALL_P ( x ) ) return true ; x = CALL_INSN_FUNCTION_USAGE ( x ) ; if ( x == 0 ) return false ; } else x = PATTERN ( x ) ; } subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , x , NONCONST ) if ( global_reg_mentioned_p_1 ( * iter ) ) return true ; return false ; } </s>

Returns nonzero if X mentions a global register .


<s> static void emit_unlikely_jump ( rtx cond , rtx label ) { int very_unlikely = REG_BR_PROB_BASE / 100 - 1 ; rtx x ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , cond , label , pc_rtx ) ; x = emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , x ) ) ; add_int_reg_note ( x , REG_BR_PROB , very_unlikely ) ; } </s>

Mark the previous jump instruction as unlikely .


<s> bool ARMAsmParser :: ParseInstruction ( StringRef Name , SMLoc NameLoc , SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { OwningPtr < ARMOperand > Op ; size_t Start = 0 , Next = Name . find ( '.' ) ; StringRef Head = Name . slice ( Start , Next ) ; unsigned CC = StringSwitch < unsigned > ( Head . substr ( Head . size ( ) - 2 ) ) . Case ( "eq" , ARMCC :: EQ ) . Case ( "ne" , ARMCC :: NE ) . Case ( "hs" , ARMCC :: HS ) . Case ( "lo" , ARMCC :: LO ) . Case ( "mi" , ARMCC :: MI ) . Case ( "pl" , ARMCC :: PL ) . Case ( "vs" , ARMCC :: VS ) . Case ( "vc" , ARMCC :: VC ) . Case ( "hi" , ARMCC :: HI ) . Case ( "ls" , ARMCC :: LS ) . Case ( "ge" , ARMCC :: GE ) . Case ( "lt" , ARMCC :: LT ) . Case ( "gt" , ARMCC :: GT ) . Case ( "le" , ARMCC :: LE ) . Case ( "al" , ARMCC :: AL ) . Default ( ~ 0U ) ; if ( CC != ~ 0U ) { Head = Head . slice ( 0 , Head . size ( ) - 2 ) ; } else CC = ARMCC :: AL ; ARMOperand :: CreateToken ( Op , Head , NameLoc ) ; Operands . push_back ( Op . take ( ) ) ; ARMOperand :: CreateCondCode ( Op , ARMCC :: CondCodes ( CC ) , NameLoc ) ; Operands . push_back ( Op . take ( ) ) ; while ( Next != StringRef :: npos ) { Start = Next ; Next = Name . find ( '.' , Start + 1 ) ; Head = Name . slice ( Start , Next ) ; ARMOperand :: CreateToken ( Op , Head , NameLoc ) ; Operands . push_back ( Op . take ( ) ) ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { OwningPtr < ARMOperand > Op ; if ( ParseOperand ( Op ) ) return true ; Operands . push_back ( Op . take ( ) ) ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( ParseOperand ( Op ) ) return true ; Operands . push_back ( Op . take ( ) ) ; } } return false ; } </s>

ParseInstruction - Parse one assembly instruction .

ARM ARM ARM 0 2 "eq" ARMCC::EQ "ne" ARMCC::NE "hs" ARMCC::HS "lo" ARMCC::LO "mi" ARMCC::MI "pl" ARMCC::PL "vs" ARMCC::VS "vc" ARMCC::VC "hi" ARMCC::HI "ls" ARMCC::LS "ge" ARMCC::GE "lt" ARMCC::LT "gt" ARMCC::GT "le" ARMCC::LE "al" ARMCC::AL 0U 0U 0 2 ARMCC::AL ARM ARM ARMCC::CondCodes 1 ARM ARM


<s> BitVector BlackfinRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; using namespace BF ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AZ ) ; Reserved . set ( AN ) ; Reserved . set ( AQ ) ; Reserved . set ( AC0 ) ; Reserved . set ( AC1 ) ; Reserved . set ( AV0 ) ; Reserved . set ( AV0S ) ; Reserved . set ( AV1 ) ; Reserved . set ( AV1S ) ; Reserved . set ( V ) ; Reserved . set ( VS ) ; Reserved . set ( CYCLES ) . set ( CYCLES2 ) ; Reserved . set ( L0 ) ; Reserved . set ( L1 ) ; Reserved . set ( L2 ) ; Reserved . set ( L3 ) ; Reserved . set ( SP ) ; Reserved . set ( RETS ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( FP ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
bool
X86DAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
SDValue
Op0
,
Op1
,
Op2
,
Op3
,
Op4
;
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
case
InlineAsm
::
Constraint_o
:
case
InlineAsm
::
Constraint_v
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_X
:
if
(
!
SelectAddr
(
nullptr
,
Op
,
Op0
,
Op1
,
Op2
,
Op3
,
Op4
)
)
return
true
;
break
;
}
OutOps
.
push_back
(
Op0
)
;
OutOps
.
push_back
(
Op1
)
;
OutOps
.
push_back
(
Op2
)
;
OutOps
.
push_back
(
Op3
)
;
OutOps
.
push_back
(
Op4
)
;
return
false
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


"builtin function %qs is only valid for the cell processor"

"builtin function %qs requires the %qs option"

"builtin function %qs requires the %qs and %qs options"

"builtin function %qs requires ISA 3.0 IEEE 128-bit floating point"

"builtin function %qs requires the %qs (or newer), and "

"builtin function %qs is not supported with the current options"

Raise an error message for a builtin function that is called without the appropriate target options being set .


<s> void NVPTXPassConfig :: addPostRegAlloc ( ) { addPass ( createNVPTXPrologEpilogPass ( ) , false ) ; addPass ( createNVPTXPeephole ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> unsigned SystemZTTIImpl :: getMinPrefetchStride ( unsigned NumMemAccesses , unsigned NumStridedMemAccesses , unsigned NumPrefetches , bool HasCall ) const { if ( NumPrefetches > 16 ) return UINT_MAX ; if ( NumStridedMemAccesses > 32 && ! HasCall && ( NumMemAccesses - NumStridedMemAccesses ) * 32 <= NumStridedMemAccesses ) return 1 ; return ST -> hasMiscellaneousExtensions3 ( ) ? 8192 : 2048 ; } </s>

Some HW prefetchers can handle accesses up to a certain constant stride .


<s>
int
m32c_limit_reload_class
(
machine_mode
mode
,
int
rclass
)
{
fprintf
(
stderr
,
"limit_reload_class for %s: %s ->"
,
mode_name
[
mode
]
,
class_names
[
rclass
]
)
;
if
(
mode
==
QImode
)
rclass
=
reduce_class
(
rclass
,
HL_REGS
,
rclass
)
;
else
if
(
mode
==
HImode
)
rclass
=
reduce_class
(
rclass
,
HI_REGS
,
rclass
)
;
else
if
(
mode
==
SImode
)
rclass
=
reduce_class
(
rclass
,
SI_REGS
,
rclass
)
;
if
(
rclass
!=
A_REGS
)
rclass
=
reduce_class
(
rclass
,
DI_REGS
,
rclass
)
;
fprintf
(
stderr
,
" %s\n"
,
class_names
[
rclass
]
)
;
return
rclass
;
}
</s>

Implements LIMIT_RELOAD_CLASS . We basically want to avoid using address registers for reloads since they 're needed for address reloads .

m32c
"limit_reload_class for %s: %s ->"
" %s\n"


<s> bool ARMAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; printAddrMode2Operand ( MI , OpNo ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> const uint32_t * CSKYRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID Id ) const { const CSKYSubtarget & STI = MF . getSubtarget < CSKYSubtarget > ( ) ; if ( STI . hasFPUv2DoubleFloat ( ) || STI . hasFPUv3DoubleFloat ( ) ) return CSR_GPR_FPR64_RegMask ; if ( STI . hasFPUv2SingleFloat ( ) || STI . hasFPUv3SingleFloat ( ) ) return CSR_GPR_FPR32_RegMask ; return CSR_I32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> const HexagonTargetLowering * getTLI ( ) const { return & TLI ; } </s>

Getter for generic TargetLowering class .


<s> void ARMConstantIslands :: verify ( MachineFunction & MF ) { assert ( BBOffsets . size ( ) == BBSizes . size ( ) ) ; for ( unsigned i = 1 , e = BBOffsets . size ( ) ; i != e ; ++ i ) assert ( BBOffsets [ i - 1 ] + BBSizes [ i - 1 ] == BBOffsets [ i ] ) ; if ( ! isThumb ) return ; for ( MachineFunction :: iterator MBBI = MF . begin ( ) , E = MF . end ( ) ; MBBI != E ; ++ MBBI ) { MachineBasicBlock * MBB = MBBI ; if ( ! MBB -> empty ( ) && MBB -> begin ( ) -> getOpcode ( ) == ARM :: CONSTPOOL_ENTRY ) { unsigned MBBId = MBB -> getNumber ( ) ; assert ( ( BBOffsets [ MBBId ] % 4 == 0 && BBSizes [ MBBId ] % 4 == 0 ) || ( BBOffsets [ MBBId ] % 4 != 0 && BBSizes [ MBBId ] % 4 != 0 ) ) ; } } } </s>


<s>
bool
AVRFrameLowering
::
restoreCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
MutableArrayRef
<
CalleeSavedInfo
>
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
if
(
CSI
.
empty
(
)
)
{
return
false
;
}
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
AVRSubtarget
&
STI
=
MF
.
getSubtarget
<
AVRSubtarget
>
(
)
;
const
TargetInstrInfo
&
TII
=
*
STI
.
getInstrInfo
(
)
;
for
(
const
CalleeSavedInfo
&
CCSI
:
CSI
)
{
unsigned
Reg
=
CCSI
.
getReg
(
)
;
assert
(
TRI
->
getRegSizeInBits
(
*
TRI
->
getMinimalPhysRegClass
(
Reg
)
)
==
8
&&
"Invalid register size"
)
;
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
POPRd
)
,
Reg
)
;
}
return
true
;
}
</s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .

AVR
AVR
AVR
AVR
8
"Invalid register size"
AVR::POPRd


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Hexagon Split Const32s and Const64s"
;
}
</s>

getPassName - Return a nice clean name for a pass .

Hexagon
"Hexagon Split Const32s and Const64s"


<s> int aarch64_ldrstr_offset_compare ( const void * x , const void * y ) { const rtx * operands_1 = ( const rtx * ) x ; const rtx * operands_2 = ( const rtx * ) y ; rtx mem_1 , mem_2 , base , offset_1 , offset_2 ; if ( MEM_P ( operands_1 [ 0 ] ) ) mem_1 = operands_1 [ 0 ] ; else mem_1 = operands_1 [ 1 ] ; if ( MEM_P ( operands_2 [ 0 ] ) ) mem_2 = operands_2 [ 0 ] ; else mem_2 = operands_2 [ 1 ] ; extract_base_offset_in_addr ( mem_1 , & base , & offset_1 ) ; extract_base_offset_in_addr ( mem_2 , & base , & offset_2 ) ; gcc_assert ( offset_1 != NULL_RTX && offset_2 != NULL_RTX ) ; return wi :: cmps ( INTVAL ( offset_1 ) , INTVAL ( offset_2 ) ) ; } </s>

Taking X and Y to be pairs of RTX , one pointing to a MEM rtx and the other pointing to a REG rtx containing an offset , compare the offsets of the two pairs . Return : 1 iff offset ( X ) > offset ( Y ) 0 iff offset ( X ) == offset ( Y ) -1 iff offset ( X ) < offset ( Y )


"Operand must be a register when you're"

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> bool TPCMovCoalescer :: runOnMachineFunction ( MachineFunction & MF ) { if ( ! EnableCoalescer ) { return false ; } MLI = & getAnalysis < MachineLoopInfo > ( ) ; MRI = & MF . getRegInfo ( ) ; TII = MF . getSubtarget < TPCSubtarget > ( ) . getInstrInfo ( ) ; for ( unsigned i = 0 ; i < TPCII :: OpType :: Max + 1 ; ++ i ) { ConstMap [ i ] = MovMap ( ) ; } bool Changed = false ; for ( auto & L : * MLI ) { Changed |= findInnermostLoop ( L ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> void AnalyzeCallOperands ( const SmallVectorImpl < ISD :: OutputArg > & Outs , CCAssignFn Fn ) { IsFixed . resize ( Outs . size ( ) , false ) ; for ( unsigned ValNo = 0 , E = Outs . size ( ) ; ValNo != E ; ++ ValNo ) if ( Outs [ ValNo ] . IsFixed ) IsFixed . set ( ValNo ) ; CCState :: AnalyzeCallOperands ( Outs , Fn ) ; } </s>

AnalyzeCallOperands - Same as above except it takes vectors of types and argument flags .


<s> void PPCInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; SmallVector < MachineInstr * , 4 > NewMIs ; PPCFunctionInfo * FuncInfo = MF . getInfo < PPCFunctionInfo > ( ) ; FuncInfo -> setHasSpills ( ) ; bool NonRI = false , SpillsVRS = false ; if ( StoreRegToStackSlot ( MF , SrcReg , isKill , FrameIdx , RC , NewMIs , NonRI , SpillsVRS ) ) FuncInfo -> setSpillsCR ( ) ; if ( SpillsVRS ) FuncInfo -> setSpillsVRSAVE ( ) ; if ( NonRI ) FuncInfo -> setHasNonRISpills ( ) ; for ( unsigned i = 0 , e = NewMIs . size ( ) ; i != e ; ++ i ) MBB . insert ( MI , NewMIs [ i ] ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdx ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; NewMIs . back ( ) -> addMemOperand ( MF , MMO ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool AMDGPUTargetLowering :: isTruncateFree ( Type * Source , Type * Dest ) const { return Dest -> getPrimitiveSizeInBits ( ) < Source -> getPrimitiveSizeInBits ( ) && ( Dest -> getPrimitiveSizeInBits ( ) % 32 == 0 ) ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s> const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> static void function_arg_record_value_2 ( const_tree type , HOST_WIDE_INT startbitpos , struct function_arg_record_value_parms * parms , bool packed_p ) { tree field ; if ( ! packed_p ) for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) == FIELD_DECL && DECL_PACKED ( field ) ) { packed_p = true ; break ; } } for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) == FIELD_DECL ) { HOST_WIDE_INT bitpos = startbitpos ; if ( DECL_SIZE ( field ) != 0 ) { if ( integer_zerop ( DECL_SIZE ( field ) ) ) continue ; if ( tree_fits_uhwi_p ( bit_position ( field ) ) ) bitpos += int_bit_position ( field ) ; } if ( TREE_CODE ( TREE_TYPE ( field ) ) == RECORD_TYPE ) function_arg_record_value_2 ( TREE_TYPE ( field ) , bitpos , parms , packed_p ) ; else if ( ( FLOAT_TYPE_P ( TREE_TYPE ( field ) ) || TREE_CODE ( TREE_TYPE ( field ) ) == VECTOR_TYPE ) && TARGET_FPU && parms -> named && ! packed_p ) { int this_slotno = parms -> slotno + bitpos / BITS_PER_WORD ; int regno , nregs , pos ; machine_mode mode = DECL_MODE ( field ) ; rtx reg ; function_arg_record_value_3 ( bitpos , parms ) ; if ( TREE_CODE ( TREE_TYPE ( field ) ) == VECTOR_TYPE && mode == BLKmode ) { mode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( field ) ) ) ; nregs = TYPE_VECTOR_SUBPARTS ( TREE_TYPE ( field ) ) ; } else if ( TREE_CODE ( TREE_TYPE ( field ) ) == COMPLEX_TYPE ) { mode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( field ) ) ) ; nregs = 2 ; } else nregs = 1 ; regno = SPARC_FP_ARG_FIRST + this_slotno * 2 ; if ( GET_MODE_SIZE ( mode ) <= 4 && ( bitpos & 32 ) != 0 ) regno ++ ; reg = gen_rtx_REG ( mode , regno ) ; pos = bitpos / BITS_PER_UNIT ; XVECEXP ( parms -> ret , 0 , parms -> stack + parms -> nregs ) = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( pos ) ) ; parms -> nregs += 1 ; while ( -- nregs > 0 ) { regno += GET_MODE_SIZE ( mode ) / 4 ; reg = gen_rtx_REG ( mode , regno ) ; pos += GET_MODE_SIZE ( mode ) ; XVECEXP ( parms -> ret , 0 , parms -> stack + parms -> nregs ) = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( pos ) ) ; parms -> nregs += 1 ; } } else { if ( parms -> intoffset == - 1 ) parms -> intoffset = bitpos ; } } } } </s>

A subroutine of function_arg_record_value . Traverse the structure recursively and assign bits to floating point registers . Track which bits in between need integer registers ; invoke function_arg_record_value_3 to make that happen .


"%qE attribute only applies to variables"

Handle aux attribute . The auxiliary registers are addressed using special instructions lr and sr . The attribute 'aux ' indicates if a variable refers to the aux-regs and what is the register number desired .


<s> void MipsTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF :: SHF_MIPS_GPREL ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF :: SHF_MIPS_GPREL ) ; this -> TM = & static_cast < const MipsTargetMachine & > ( TM ) ; } </s>

This method must be called before any actual lowering is done .


<s> bool X86InstrInfo :: isSafeToMoveRegClassDefs ( const TargetRegisterClass * RC ) const { return ! ( RC == & X86 :: CCRRegClass || RC == & X86 :: DFCCRRegClass || RC == & X86 :: RFP32RegClass || RC == & X86 :: RFP64RegClass || RC == & X86 :: RFP80RegClass ) ; } </s>

isSafeToMoveRegClassDefs - Return true if it 's safe to move a machine instruction that defines the specified register class .


<s> const MCExpr * X86TargetLowering :: getPICJumpTableRelocBaseExpr ( const MachineFunction * MF , unsigned JTI , MCContext & Ctx ) const { if ( Subtarget -> isPICStyleRIPRel ( ) ) return TargetLowering :: getPICJumpTableRelocBaseExpr ( MF , JTI , Ctx ) ; return MCSymbolRefExpr :: create ( MF -> getPICBaseSymbol ( ) , Ctx ) ; } </s>

This returns the relocation base for the given PIC jumptable , the same as getPICJumpTableRelocBase , but as an MCExpr .


<s>
MachineBasicBlock
*
SparcTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown SELECT_CC!"
)
;
case
SP
::
SELECT_CC_Int_ICC
:
case
SP
::
SELECT_CC_FP_ICC
:
case
SP
::
SELECT_CC_DFP_ICC
:
case
SP
::
SELECT_CC_QFP_ICC
:
return
expandSelectCC
(
MI
,
BB
,
SP
::
BCOND
)
;
case
SP
::
SELECT_CC_Int_XCC
:
case
SP
::
SELECT_CC_FP_XCC
:
case
SP
::
SELECT_CC_DFP_XCC
:
case
SP
::
SELECT_CC_QFP_XCC
:
return
expandSelectCC
(
MI
,
BB
,
SP
::
BPXCC
)
;
case
SP
::
SELECT_CC_Int_FCC
:
case
SP
::
SELECT_CC_FP_FCC
:
case
SP
::
SELECT_CC_DFP_FCC
:
case
SP
::
SELECT_CC_QFP_FCC
:
return
expandSelectCC
(
MI
,
BB
,
SP
::
FBCOND
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> SDValue AArch64TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : case ISD :: SUB : return performAddSubLongCombine ( N , DCI , DAG ) ; case ISD :: XOR : return performXorCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: MUL : return performMulCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SINT_TO_FP : case ISD :: UINT_TO_FP : return performIntToFpCombine ( N , DAG , Subtarget ) ; case ISD :: OR : return performORCombine ( N , DCI , Subtarget ) ; case ISD :: INTRINSIC_WO_CHAIN : return performIntrinsicCombine ( N , DCI , Subtarget ) ; case ISD :: ANY_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: SIGN_EXTEND : return performExtendCombine ( N , DCI , DAG ) ; case ISD :: BITCAST : return performBitcastCombine ( N , DCI , DAG ) ; case ISD :: CONCAT_VECTORS : return performConcatVectorsCombine ( N , DCI , DAG ) ; case ISD :: SELECT : return performSelectCombine ( N , DCI ) ; case ISD :: VSELECT : return performVSelectCombine ( N , DCI . DAG ) ; case ISD :: SELECT_CC : return performSelectCCCombine ( N , DCI . DAG ) ; case ISD :: STORE : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case AArch64ISD :: BRCOND : return performBRCONDCombine ( N , DCI , DAG ) ; case AArch64ISD :: CSEL : return performCONDCombine ( N , DCI , DAG , 2 , 3 ) ; case AArch64ISD :: DUP : return performPostLD1Combine ( N , DCI , false ) ; case AArch64ISD :: NVCAST : return performNVCASTCombine ( N ) ; case ISD :: INSERT_VECTOR_ELT : return performPostLD1Combine ( N , DCI , true ) ; case ISD :: INTRINSIC_VOID : case ISD :: INTRINSIC_W_CHAIN : switch ( cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) -> getZExtValue ( ) ) { case Intrinsic :: aarch64_neon_ld2 : case Intrinsic :: aarch64_neon_ld3 : case Intrinsic :: aarch64_neon_ld4 : case Intrinsic :: aarch64_neon_ld1x2 : case Intrinsic :: aarch64_neon_ld1x3 : case Intrinsic :: aarch64_neon_ld1x4 : case Intrinsic :: aarch64_neon_ld2lane : case Intrinsic :: aarch64_neon_ld3lane : case Intrinsic :: aarch64_neon_ld4lane : case Intrinsic :: aarch64_neon_ld2r : case Intrinsic :: aarch64_neon_ld3r : case Intrinsic :: aarch64_neon_ld4r : case Intrinsic :: aarch64_neon_st2 : case Intrinsic :: aarch64_neon_st3 : case Intrinsic :: aarch64_neon_st4 : case Intrinsic :: aarch64_neon_st1x2 : case Intrinsic :: aarch64_neon_st1x3 : case Intrinsic :: aarch64_neon_st1x4 : case Intrinsic :: aarch64_neon_st2lane : case Intrinsic :: aarch64_neon_st3lane : case Intrinsic :: aarch64_neon_st4lane : return performNEONPostLDSTCombine ( N , DCI , DAG ) ; default : break ; } } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> void X86PassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & LiveRangeShrinkID ) ; addPass ( createX86FixupSetCC ( ) ) ; addPass ( createX86OptimizeLEAs ( ) ) ; addPass ( createX86CallFrameOptimization ( ) ) ; } addPass ( createX86FlagsCopyLoweringPass ( ) ) ; addPass ( createX86WinAllocaExpander ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static rtx or1k_function_arg ( cumulative_args_t cum_v , const function_arg_info & arg ) { if ( arg . end_marker_p ( ) ) return NULL_RTX ; CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int nreg = CEIL ( GET_MODE_SIZE ( arg . mode ) , UNITS_PER_WORD ) ; gcc_assert ( nreg <= 2 ) ; if ( arg . named && * cum + nreg <= 6 ) return gen_rtx_REG ( arg . mode , * cum + 3 ) ; else return NULL_RTX ; } </s>

Worker for TARGET_FUNCTION_ARG . Return the next register to be used to hold a function argument or NULL_RTX if there 's no more space . Arugment CUM_V represents the current argument offset , zero for the first function argument . OpenRISC function arguments maybe be passed in registers r3 to r8 .


<s>
Register
Comet2RegisterInfo
::
getFrameRegister
(
const
MachineFunction
&
MF
)
const
{
report_fatal_error
(
"Comet2 cannot read or overwrite SP"
)
;
}
</s>


<s> static machine_mode alpha_secondary_memory_needed_mode ( machine_mode mode ) { if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return mode ; if ( GET_MODE_SIZE ( mode ) >= 4 ) return mode ; return mode_for_size ( BITS_PER_WORD , GET_MODE_CLASS ( mode ) , 0 ) . require ( ) ; } </s>

Implement TARGET_SECONDARY_MEMORY_NEEDED_MODE . If MODE is floating-point , use it . Otherwise , widen to a word like the default . This is needed because we always store integers in FP registers in quadword format . This whole area is very tricky !


<s> void MipsTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ; this -> TM = & TM ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"WebAssembly CFG Sort"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool AMDGPUPassConfig :: addInstSelector ( ) { const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; addPass ( createAMDGPUISelDag ( getAMDGPUTargetMachine ( ) ) ) ; if ( ST . getGeneration ( ) >= AMDGPUSubtarget :: SOUTHERN_ISLANDS ) { addPass ( createSILowerI1CopiesPass ( ) ) ; addPass ( createSIFixSGPRCopiesPass ( * TM ) ) ; addPass ( createSIFoldOperandsPass ( ) ) ; } return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void ARCInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << StringRef ( getRegisterName ( RegNo ) ) . lower ( ) ; } </s>


<s> impl_ptr clone ( ) const { return impl_ptr ( ptr_ ? copier_ ( ptr_ . get ( ) ) : nullptr , ptr_ . get_deleter ( ) , copier_ ) ; } </s>

Make a functionally equivalent copy of this MachineFunctionInfo in MF .


<s> bool SITargetLowering :: isFPExtFoldable ( const MachineInstr & MI , unsigned Opcode , LLT DestTy , LLT SrcTy ) const { return ( ( Opcode == TargetOpcode :: G_FMAD && Subtarget -> hasMadMixInsts ( ) ) || ( Opcode == TargetOpcode :: G_FMA && Subtarget -> hasFmaMixInsts ( ) ) ) && DestTy . getScalarSizeInBits ( ) == 32 && SrcTy . getScalarSizeInBits ( ) == 16 && ! hasFP32Denormals ( * MI . getMF ( ) ) ; } </s>

Return true if an fpext operation input to an Opcode operation is free ( for instance , because half-precision floating-point numbers are implicitly extended to float-precision ) for an FMA instruction .


<s> bool exp2_immediate_p ( rtx op , machine_mode mode , int low , int high ) { machine_mode int_mode ; HOST_WIDE_INT val ; unsigned char arr [ 16 ] ; int bytes , i , j ; gcc_assert ( GET_CODE ( op ) == CONST_INT || GET_CODE ( op ) == CONST_DOUBLE || GET_CODE ( op ) == CONST_VECTOR ) ; if ( GET_CODE ( op ) == CONST_VECTOR && ! const_vector_immediate_p ( op ) ) return 0 ; if ( GET_MODE ( op ) != VOIDmode ) mode = GET_MODE ( op ) ; constant_to_array ( mode , op , arr ) ; mode = GET_MODE_INNER ( mode ) ; bytes = GET_MODE_SIZE ( mode ) ; int_mode = int_mode_for_mode ( mode ) . require ( ) ; for ( i = bytes ; i < 16 ; i += bytes ) for ( j = 0 ; j < bytes ; j ++ ) if ( arr [ j ] != arr [ i + j ] ) return 0 ; val = arr [ 0 ] ; for ( j = 1 ; j < bytes ; j ++ ) val = ( val << 8 ) | arr [ j ] ; val = trunc_int_for_mode ( val , int_mode ) ; gcc_assert ( mode == SFmode ) ; if ( mode == SFmode ) { int exp = ( val >> 23 ) - 127 ; return val > 0 && ( val & 0x007fffff ) == 0 && exp >= low && exp <= high ; } return FALSE ; } </s>

TRUE when op is an immediate and an exact power of 2 , and given that OP is 2^scale , scale > = LOW & & scale < = HIGH . When OP is a vector , all entries must be the same .


<s> DecodeStatus ARM64Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , const MemoryObject & Region , uint64_t Address , raw_ostream & os , raw_ostream & cs ) const { CommentStream = & cs ; uint8_t bytes [ 4 ] ; Size = 0 ; if ( Region . readBytes ( Address , 4 , ( uint8_t * ) bytes ) == - 1 ) return Fail ; Size = 4 ; uint32_t insn = ( bytes [ 3 ] << 24 ) | ( bytes [ 2 ] << 16 ) | ( bytes [ 1 ] << 8 ) | ( bytes [ 0 ] << 0 ) ; return decodeInstruction ( DecoderTable32 , MI , insn , Address , this , STI ) ; } </s>

Returns the disassembly of a single instruction .


<s> bool GCNTTIImpl :: isInlineAsmSourceOfDivergence ( const CallInst * CI , ArrayRef < unsigned > Indices ) const { if ( Indices . size ( ) > 1 ) return true ; const DataLayout & DL = CI -> getModule ( ) -> getDataLayout ( ) ; const SIRegisterInfo * TRI = ST -> getRegisterInfo ( ) ; ImmutableCallSite CS ( CI ) ; TargetLowering :: AsmOperandInfoVector TargetConstraints = TLI -> ParseConstraints ( DL , ST -> getRegisterInfo ( ) , CS ) ; const int TargetOutputIdx = Indices . empty ( ) ? - 1 : Indices [ 0 ] ; int OutputIdx = 0 ; for ( auto & TC : TargetConstraints ) { if ( TC . Type != InlineAsm :: isOutput ) continue ; if ( TargetOutputIdx != - 1 && TargetOutputIdx != OutputIdx ++ ) continue ; TLI -> ComputeConstraintToUse ( TC , SDValue ( ) ) ; Register AssignedReg ; const TargetRegisterClass * RC ; std :: tie ( AssignedReg , RC ) = TLI -> getRegForInlineAsmConstraint ( TRI , TC . ConstraintCode , TC . ConstraintVT ) ; if ( AssignedReg ) { RC = TRI -> getPhysRegClass ( AssignedReg ) ; } if ( ! RC || ! TRI -> isSGPRClass ( RC ) ) return true ; } return false ; } </s>

Analyze if the results of inline asm are divergent .


<s> void thumb_expand_cpymemqi ( rtx * operands ) { rtx out = copy_to_mode_reg ( SImode , XEXP ( operands [ 0 ] , 0 ) ) ; rtx in = copy_to_mode_reg ( SImode , XEXP ( operands [ 1 ] , 0 ) ) ; HOST_WIDE_INT len = INTVAL ( operands [ 2 ] ) ; HOST_WIDE_INT offset = 0 ; while ( len >= 12 ) { emit_insn ( gen_cpymem12b ( out , in , out , in ) ) ; len -= 12 ; } if ( len >= 8 ) { emit_insn ( gen_cpymem8b ( out , in , out , in ) ) ; len -= 8 ; } if ( len >= 4 ) { rtx reg = gen_reg_rtx ( SImode ) ; emit_insn ( gen_movsi ( reg , gen_rtx_MEM ( SImode , in ) ) ) ; emit_insn ( gen_movsi ( gen_rtx_MEM ( SImode , out ) , reg ) ) ; len -= 4 ; offset += 4 ; } if ( len >= 2 ) { rtx reg = gen_reg_rtx ( HImode ) ; emit_insn ( gen_movhi ( reg , gen_rtx_MEM ( HImode , plus_constant ( Pmode , in , offset ) ) ) ) ; emit_insn ( gen_movhi ( gen_rtx_MEM ( HImode , plus_constant ( Pmode , out , offset ) ) , reg ) ) ; len -= 2 ; offset += 2 ; } if ( len ) { rtx reg = gen_reg_rtx ( QImode ) ; emit_insn ( gen_movqi ( reg , gen_rtx_MEM ( QImode , plus_constant ( Pmode , in , offset ) ) ) ) ; emit_insn ( gen_movqi ( gen_rtx_MEM ( QImode , plus_constant ( Pmode , out , offset ) ) , reg ) ) ; } } </s>


<s> static void mep_init_intrinsics ( void ) { size_t i ; mep_selected_isa = mep_configs [ 0 ] . isa ; if ( mep_config_string != 0 ) for ( i = 0 ; mep_configs [ i ] . config_name ; i ++ ) if ( strcmp ( mep_config_string , mep_configs [ i ] . config_name ) == 0 ) { mep_selected_isa = mep_configs [ i ] . isa ; break ; } for ( i = 0 ; i < ARRAY_SIZE ( mep_intrinsic_insn ) ; i ++ ) mep_intrinsic_insn [ i ] = - 1 ; for ( i = 0 ; i < ARRAY_SIZE ( cgen_insns ) ; i ++ ) if ( ( cgen_insns [ i ] . isas & mep_selected_isa ) != 0 ) { mep_intrinsic_chain [ i ] = mep_intrinsic_insn [ cgen_insns [ i ] . intrinsic ] ; mep_intrinsic_insn [ cgen_insns [ i ] . intrinsic ] = i ; } for ( i = 0 ; i < ARRAY_SIZE ( mep_cmov_insns ) ; i ++ ) if ( MEP_INTRINSIC_AVAILABLE_P ( mep_cmov_insns [ i ] ) ) mep_have_copro_copro_moves_p = true ; mep_have_core_copro_moves_p = ( MEP_INTRINSIC_AVAILABLE_P ( mep_cmov1 ) && MEP_INTRINSIC_AVAILABLE_P ( mep_cmov2 ) ) ; mep_have_core_copro_moves_p = 1 ; } </s>

Initialize the global intrinsics variables above .


<s> void WebAssemblyPassConfig :: addIRPasses ( ) { addPass ( createWebAssemblyAddMissingPrototypes ( ) ) ; addPass ( createLowerGlobalDtorsLegacyPass ( ) ) ; addPass ( createWebAssemblyFixFunctionBitcasts ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createWebAssemblyOptimizeReturned ( ) ) ; basicCheckForEHAndSjLj ( TM ) ; if ( ! WasmEnableEmEH && ! WasmEnableEH ) { addPass ( createLowerInvokePass ( ) ) ; addPass ( createUnreachableBlockEliminationPass ( ) ) ; } if ( WasmEnableEmEH || WasmEnableEmSjLj || WasmEnableSjLj ) addPass ( createWebAssemblyLowerEmscriptenEHSjLj ( ) ) ; addPass ( createIndirectBrExpandPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly


"Unexpected base pointer for inline asm memory operand."

"Unexpected offset for inline asm memory operand."

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> BitVector MipsRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t ReservedCPURegs [ ] = { Mips :: ZERO , Mips :: AT , Mips :: K0 , Mips :: K1 , Mips :: SP , Mips :: RA } ; static const uint16_t ReservedCPU64Regs [ ] = { Mips :: ZERO_64 , Mips :: AT_64 , Mips :: K0_64 , Mips :: K1_64 , Mips :: SP_64 , Mips :: RA_64 } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: const_iterator RegIter ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; if ( Subtarget . hasMips64 ( ) ) { for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPU64Regs ) ; ++ I ) Reserved . set ( ReservedCPU64Regs [ I ] ) ; for ( RegIter Reg = Mips :: AFGR64RegClass . begin ( ) , EReg = Mips :: AFGR64RegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } else { for ( RegIter Reg = Mips :: CPU64RegsRegClass . begin ( ) , EReg = Mips :: CPU64RegsRegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; for ( RegIter Reg = Mips :: FGR64RegClass . begin ( ) , EReg = Mips :: FGR64RegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) ) { Reserved . set ( Mips :: FP ) ; Reserved . set ( Mips :: FP_64 ) ; } Reserved . set ( Mips :: HWR29 ) ; Reserved . set ( Mips :: HWR29_64 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static sbitmap rs6000_components_for_bb ( basic_block bb ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; bitmap in = DF_LIVE_IN ( bb ) ; bitmap gen = & DF_LIVE_BB_INFO ( bb ) -> gen ; bitmap kill = & DF_LIVE_BB_INFO ( bb ) -> kill ; sbitmap components = sbitmap_alloc ( 32 ) ; bitmap_clear ( components ) ; for ( unsigned regno = info -> first_gp_reg_save ; regno < 32 ; regno ++ ) if ( bitmap_bit_p ( in , regno ) || bitmap_bit_p ( gen , regno ) || bitmap_bit_p ( kill , regno ) ) bitmap_set_bit ( components , regno ) ; if ( bitmap_bit_p ( in , LR_REGNO ) || bitmap_bit_p ( gen , LR_REGNO ) || bitmap_bit_p ( kill , LR_REGNO ) ) bitmap_set_bit ( components , 0 ) ; return components ; } </s>


<s> bool ARMPassConfig :: addPreISel ( ) { if ( ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE ) { bool OnlyOptimizeForSize = ( TM -> getOptLevel ( ) < CodeGenOpt :: Aggressive ) && ( EnableGlobalMerge == cl :: BOU_UNSET ) ; addPass ( createGlobalMergePass ( TM , 127 , OnlyOptimizeForSize ) ) ; } return false ; } </s>


<s> static bool m32c_class_likely_spilled_p ( reg_class_t regclass ) { if ( regclass == A_REGS ) return true ; return ( reg_class_size [ ( int ) regclass ] == 1 ) ; } </s>

Implements CLASS_LIKELY_SPILLED_P . A_REGS is needed for address reloads .


<s> static bool ix86_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( CC_REGNO_P ( regno ) ) return GET_MODE_CLASS ( mode ) == MODE_CC ; if ( GET_MODE_CLASS ( mode ) == MODE_CC || GET_MODE_CLASS ( mode ) == MODE_RANDOM ) return false ; if ( STACK_REGNO_P ( regno ) ) return VALID_FP_MODE_P ( mode ) ; if ( MASK_REGNO_P ( regno ) ) { if ( ( mode == P2QImode || mode == P2HImode ) ) return MASK_PAIR_REGNO_P ( regno ) ; return ( ( TARGET_AVX512F && VALID_MASK_REG_MODE ( mode ) ) || ( TARGET_AVX512BW && VALID_MASK_AVX512BW_MODE ( mode ) ) ) ; } if ( GET_MODE_CLASS ( mode ) == MODE_PARTIAL_INT ) return false ; if ( SSE_REGNO_P ( regno ) ) { if ( TARGET_AVX512F && ( VALID_AVX512F_REG_OR_XI_MODE ( mode ) || VALID_AVX512F_SCALAR_MODE ( mode ) ) ) return true ; if ( ( TARGET_AVX5124FMAPS || TARGET_AVX5124VNNIW ) && ( mode == V64SFmode || mode == V64SImode ) && MOD4_SSE_REGNO_P ( regno ) ) return true ; if ( TARGET_AVX512VL && ( VALID_AVX256_REG_OR_OI_MODE ( mode ) || VALID_AVX512VL_128_REG_MODE ( mode ) ) ) return true ; if ( EXT_REX_SSE_REGNO_P ( regno ) ) return false ; if ( TARGET_SSE2 && mode == HImode ) return true ; return ( ( TARGET_AVX && VALID_AVX256_REG_OR_OI_MODE ( mode ) ) || VALID_SSE_REG_MODE ( mode ) || VALID_SSE2_REG_MODE ( mode ) || VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( MMX_REGNO_P ( regno ) ) { return ( VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( mode == QImode ) { if ( ANY_QI_REGNO_P ( regno ) ) return true ; if ( ! TARGET_PARTIAL_REG_STALL ) return true ; if ( lra_in_progress ) return true ; return ! can_create_pseudo_p ( ) ; } else if ( VALID_INT_MODE_P ( mode ) || VALID_FP_MODE_P ( mode ) ) return true ; else if ( VALID_MMX_REG_MODE_3DNOW ( mode ) || VALID_MMX_REG_MODE ( mode ) ) return true ; return false ; } </s>

Return TRUE if hard register REGNO can hold a value of machine-mode MODE .


"%qE attribute only applies to functions"


<s> static bool insn_uses_reg_mem ( unsigned int regno , rtx insn ) { df_ref use ; FOR_EACH_INSN_USE ( use , insn ) if ( DF_REF_REG_MEM_P ( use ) && regno == DF_REF_REGNO ( use ) ) return true ; return false ; } </s>

Function checks if instruction INSN uses register number REGNO as a part of address expression .


<s> bool AArch64TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( AM . BaseGV ) return false ; if ( AM . HasBaseReg && AM . BaseOffs && AM . Scale ) return false ; uint64_t NumBytes = 0 ; if ( Ty -> isSized ( ) ) { uint64_t NumBits = DL . getTypeSizeInBits ( Ty ) ; NumBytes = NumBits / 8 ; if ( ! isPowerOf2_64 ( NumBits ) ) NumBytes = 0 ; } if ( ! AM . Scale ) { int64_t Offset = AM . BaseOffs ; if ( Offset >= - ( 1LL << 9 ) && Offset <= ( 1LL << 9 ) - 1 ) return true ; unsigned shift = Log2_64 ( NumBytes ) ; if ( NumBytes && Offset > 0 && ( Offset / NumBytes ) <= ( 1LL << 12 ) - 1 && ( Offset >> shift ) << shift == Offset ) return true ; return false ; } return ! AM . Scale || AM . Scale == 1 || ( AM . Scale > 0 && ( uint64_t ) AM . Scale == NumBytes ) ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> bool isToken ( ) const override { return Kind == k_Token ; } </s>


<s>
void
SNESInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
const
SNESSubtarget
&
STI
=
MBB
.
getParent
(
)
->
getSubtarget
<
SNESSubtarget
>
(
)
;
const
SNESRegisterInfo
&
TRI
=
*
STI
.
getRegisterInfo
(
)
;
unsigned
Opc
;
if
(
SNES
::
MainRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
unsigned
DestLo
,
DestHi
,
SrcLo
,
SrcHi
;
TRI
.
splitReg
(
DestReg
,
DestLo
,
DestHi
)
;
TRI
.
splitReg
(
SrcReg
,
SrcLo
,
SrcHi
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
SNES
::
MOVRdRr
)
,
DestLo
)
.
addReg
(
SrcLo
,
getKillRegState
(
KillSrc
)
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
SNES
::
MOVRdRr
)
,
DestHi
)
.
addReg
(
SrcHi
,
getKillRegState
(
KillSrc
)
)
;
}
else
{
if
(
SNES
::
MainRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
Opc
=
SNES
::
MOVRdRr
;
}
else
if
(
SrcReg
==
SNES
::
SP
&&
SNES
::
MainRegsRegClass
.
contains
(
DestReg
)
)
{
Opc
=
SNES
::
SPREAD
;
}
else
if
(
DestReg
==
SNES
::
SP
&&
SNES
::
MainRegsRegClass
.
contains
(
SrcReg
)
)
{
Opc
=
SNES
::
SPWRITE
;
}
else
{
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
}
</s>

SNES
SNES
SNES
SNES
SNES
SNES::MainRegsRegClass
SNES::MOVRdRr
SNES::MOVRdRr
SNES::MainRegsRegClass
SNES::MOVRdRr
SNES::SP
SNES::MainRegsRegClass
SNES::SPREAD
SNES::SP
SNES::MainRegsRegClass
SNES::SPWRITE
"Impossible reg-to-reg copy"


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCRelaxableFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
override
{
llvm_unreachable
(
"RelaxInstruction() unimplemented"
)
;
return
false
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s>
const
char
*
getPassName
(
)
const
{
return
"AdvSIMD scalar operation optimization"
;
}
</s>


"XtensaInstrInfo::removeBranch not yet implemented"

Remove the branching code at the end of the specific MBB .


<s> machine_mode visium_select_cc_mode ( enum rtx_code code , rtx op0 , rtx op1 ) { if ( GET_MODE_CLASS ( GET_MODE ( op0 ) ) == MODE_FLOAT ) { switch ( code ) { case EQ : case NE : case ORDERED : case UNORDERED : case UNLT : case UNLE : case UNGT : case UNGE : return CCFPmode ; case LT : case LE : case GT : case GE : return CCFPEmode ; case UNEQ : case LTGT : default : gcc_unreachable ( ) ; } } if ( op1 == constm1_rtx ) return CCCmode ; if ( ( code == LTU || code == GEU ) && GET_CODE ( op0 ) == PLUS && rtx_equal_p ( XEXP ( op0 , 0 ) , op1 ) ) return CCCmode ; if ( ( code == EQ || code == NE ) && GET_CODE ( op1 ) == UNSPEC && ( XINT ( op1 , 1 ) == UNSPEC_ADDV || XINT ( op1 , 1 ) == UNSPEC_SUBV || XINT ( op1 , 1 ) == UNSPEC_NEGV ) ) return CCVmode ; if ( op1 != const0_rtx ) return CCmode ; switch ( GET_CODE ( op0 ) ) { case PLUS : case MINUS : case NEG : case ASHIFT : case LTU : case LT : return CCNZmode ; case ZERO_EXTRACT : return CCCmode ; case REG : case AND : case IOR : case XOR : case NOT : case ASHIFTRT : case LSHIFTRT : case TRUNCATE : case SIGN_EXTEND : return CCmode ; case ASM_OPERANDS : case CALL : case CONST_INT : case LO_SUM : case HIGH : case MEM : case UNSPEC : case ZERO_EXTEND : return CCmode ; default : gcc_unreachable ( ) ; } } </s>

Given a comparison code ( EQ , NE , etc . ) and the operands of a COMPARE , return the mode to be used for the comparison .


<s> inline machine_mode function_instance :: gp_mode ( unsigned int i ) const { return aarch64_sve_pred_mode ( type_suffix ( i ) . element_bytes ) . require ( ) ; } </s>

Return the mode of the governing predicate to use when operating on type suffix I .


<s> bool SystemZInstrInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; SystemZMachineFunctionInfo * MFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; unsigned CalleeFrameSize = 0 ; unsigned LowReg = 0 , HighReg = 0 , StartOffset = - 1U , EndOffset = 0 ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; const TargetRegisterClass * RegClass = CSI [ i ] . getRegClass ( ) ; if ( RegClass != & SystemZ :: FP64RegClass ) { unsigned Offset = RegSpillOffsets [ Reg ] ; CalleeFrameSize += 8 ; if ( StartOffset > Offset ) { LowReg = Reg ; StartOffset = Offset ; } if ( EndOffset < Offset ) { HighReg = Reg ; EndOffset = RegSpillOffsets [ Reg ] ; } } } MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ; MFI -> setLowReg ( LowReg ) ; MFI -> setHighReg ( HighReg ) ; if ( StartOffset ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( ( LowReg == HighReg ? SystemZ :: MOV64mr : SystemZ :: MOV64mrm ) ) ) ; MIB . addReg ( SystemZ :: R15D ) . addImm ( StartOffset ) ; if ( LowReg == HighReg ) MIB . addReg ( 0 ) ; MIB . addReg ( LowReg , RegState :: Kill ) ; if ( LowReg != HighReg ) MIB . addReg ( HighReg , RegState :: Kill ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; if ( Reg != LowReg && Reg != HighReg ) MIB . addReg ( Reg , RegState :: ImplicitKill ) ; } } for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; const TargetRegisterClass * RegClass = CSI [ i ] . getRegClass ( ) ; if ( RegClass == & SystemZ :: FP64RegClass ) { MBB . addLiveIn ( Reg ) ; storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i ] . getFrameIdx ( ) , RegClass ) ; } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Blackfin Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static tree make_resolver_func ( const tree default_decl , const tree ifunc_alias_decl , basic_block * empty_bb ) { char * resolver_name ; tree decl , type , decl_name , t ; if ( TREE_PUBLIC ( default_decl ) == 0 ) { char * ifunc_name = make_unique_name ( default_decl , "ifunc" , true ) ; symtab -> change_decl_assembler_name ( ifunc_alias_decl , get_identifier ( ifunc_name ) ) ; XDELETEVEC ( ifunc_name ) ; } resolver_name = make_unique_name ( default_decl , "resolver" , false ) ; type = build_function_type_list ( ptr_type_node , NULL_TREE ) ; decl = build_fn_decl ( resolver_name , type ) ; decl_name = get_identifier ( resolver_name ) ; SET_DECL_ASSEMBLER_NAME ( decl , decl_name ) ; DECL_NAME ( decl ) = decl_name ; TREE_USED ( decl ) = 1 ; DECL_ARTIFICIAL ( decl ) = 1 ; DECL_IGNORED_P ( decl ) = 1 ; TREE_PUBLIC ( decl ) = 0 ; DECL_UNINLINABLE ( decl ) = 1 ; DECL_EXTERNAL ( decl ) = 0 ; DECL_EXTERNAL ( ifunc_alias_decl ) = 0 ; DECL_CONTEXT ( decl ) = NULL_TREE ; DECL_INITIAL ( decl ) = make_node ( BLOCK ) ; DECL_STATIC_CONSTRUCTOR ( decl ) = 0 ; if ( DECL_COMDAT_GROUP ( default_decl ) || TREE_PUBLIC ( default_decl ) ) { DECL_COMDAT ( decl ) = 1 ; make_decl_one_only ( decl , DECL_ASSEMBLER_NAME ( decl ) ) ; } t = build_decl ( UNKNOWN_LOCATION , RESULT_DECL , NULL_TREE , ptr_type_node ) ; DECL_CONTEXT ( t ) = decl ; DECL_ARTIFICIAL ( t ) = 1 ; DECL_IGNORED_P ( t ) = 1 ; DECL_RESULT ( decl ) = t ; gimplify_function_tree ( decl ) ; push_cfun ( DECL_STRUCT_FUNCTION ( decl ) ) ; * empty_bb = init_lowered_empty_function ( decl , false , profile_count :: uninitialized ( ) ) ; cgraph_node :: add_new_function ( decl , true ) ; symtab -> call_cgraph_insertion_hooks ( cgraph_node :: get_create ( decl ) ) ; pop_cfun ( ) ; gcc_assert ( ifunc_alias_decl != NULL ) ; DECL_ATTRIBUTES ( ifunc_alias_decl ) = make_attribute ( "ifunc" , resolver_name , DECL_ATTRIBUTES ( ifunc_alias_decl ) ) ; cgraph_node :: create_same_body_alias ( ifunc_alias_decl , decl ) ; XDELETEVEC ( resolver_name ) ; return decl ; } </s>

Make the resolver function decl to dispatch the versions of a multi- versioned function , DEFAULT_DECL . Create an empty basic block in the resolver and store the pointer in EMPTY_BB . Return the decl of the resolver function .


"SystemZ does do not have assembler relaxation"

Relax the instruction in the given fragment to the next wider instruction .