<s> void h8300_swap_into_er6 ( rtx addr ) { rtx insn = push ( HARD_FRAME_POINTER_REGNUM , false ) ; if ( frame_pointer_needed ) add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , gen_rtx_MEM ( Pmode , stack_pointer_rtx ) , 2 * UNITS_PER_WORD ) ) ; else add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , 4 ) ) ) ; emit_move_insn ( hard_frame_pointer_rtx , addr ) ; if ( REGNO ( addr ) == SP_REG ) emit_move_insn ( hard_frame_pointer_rtx , plus_constant ( Pmode , hard_frame_pointer_rtx , GET_MODE_SIZE ( word_mode ) ) ) ; } </s>

Move ADDR into er6 after pushing its old value onto the stack .


<s> bool isLegalMaskedStore ( Type * DataType ) { return ST -> hasSVE ( ) ; } </s>

Return true if the target supports masked store .


<s> bool SIInstrInfo :: isInlineConstant ( const MachineOperand & MO , unsigned OpSize ) const { if ( MO . isImm ( ) ) { unsigned BitSize = 8 * OpSize ; return isInlineConstant ( APInt ( BitSize , MO . getImm ( ) , true ) ) ; } return false ; } </s>

returns true if the operand OpIdx in MI is a valid inline immediate .


<s> static int avr_OS_task_function_p ( tree func ) { return avr_lookup_function_attribute1 ( func , "OS_task" ) ; } </s>

Return nonzero if FUNC is an OS_task function .


<s> static struct machine_function * frv_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function > ( ) ; } </s>

Function to set up the backend function structure .


<s> bool PPCTargetLowering :: isMaskAndCmp0FoldingBeneficial ( const Instruction & AndI ) const { const Value * Mask = AndI . getOperand ( 1 ) ; if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Mask ) ) { if ( CI -> getBitWidth ( ) > 64 ) return false ; int64_t ConstVal = CI -> getZExtValue ( ) ; return isUInt < 16 > ( ConstVal ) || ( isUInt < 16 > ( ConstVal >> 16 ) && ! ( ConstVal & 0xFFFF ) ) ; } return true ; } </s>

Return if the target supports combining a chain like :


<s> X86Subtarget :: X86Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const X86TargetMachine & TM , unsigned StackAlignOverride , unsigned PreferVectorWidthOverride , unsigned RequiredVectorWidth ) : X86GenSubtargetInfo ( TT , CPU , FS ) , PICStyle ( PICStyles :: None ) , TM ( TM ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , PreferVectorWidthOverride ( PreferVectorWidthOverride ) , RequiredVectorWidth ( RequiredVectorWidth ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( * this , getStackAlignment ( ) ) { if ( ! isPositionIndependent ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( is64Bit ( ) ) setPICStyle ( PICStyles :: RIPRel ) ; else if ( isTargetCOFF ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( isTargetDarwin ( ) ) setPICStyle ( PICStyles :: StubPIC ) ; else if ( isTargetELF ( ) ) setPICStyle ( PICStyles :: GOT ) ; CallLoweringInfo . reset ( new X86CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new X86LegalizerInfo ( * this , TM ) ) ; auto * RBI = new X86RegisterBankInfo ( * getRegisterInfo ( ) ) ; RegBankInfo . reset ( RBI ) ; InstSelector . reset ( createX86InstructionSelector ( TM , * this , * RBI ) ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> static void nds32_relax_group ( void ) { rtx_insn * insn ; compute_bb_for_insn ( ) ; df_chain_add_problem ( DF_DU_CHAIN | DF_UD_CHAIN ) ; df_insn_rescan_all ( ) ; df_analyze ( ) ; df_set_flags ( DF_DEFER_INSN_RESCAN ) ; calculate_dominance_info ( CDI_DOMINATORS ) ; insn = get_insns ( ) ; gcc_assert ( NOTE_P ( insn ) ) ; for ( insn = next_active_insn ( insn ) ; insn ; insn = next_active_insn ( insn ) ) { if ( NONJUMP_INSN_P ( insn ) ) { if ( recog_memoized ( insn ) == CODE_FOR_sethi && nds32_symbolic_operand ( XEXP ( SET_SRC ( PATTERN ( insn ) ) , 0 ) , SImode ) && ! nds32_ict_const_p ( XEXP ( SET_SRC ( PATTERN ( insn ) ) , 0 ) ) ) nds32_group_insns ( insn ) ; else if ( recog_memoized ( insn ) == CODE_FOR_tls_ie ) nds32_group_tls_insn ( insn ) ; else if ( TARGET_FPU_SINGLE && recog_memoized ( insn ) == CODE_FOR_move_addr && ! nds32_ict_const_p ( XEXP ( SET_SRC ( PATTERN ( insn ) ) , 0 ) ) ) { nds32_group_float_insns ( insn ) ; } } else if ( CALL_P ( insn ) && recog_memoized ( insn ) == CODE_FOR_tls_desc ) { nds32_group_tls_insn ( insn ) ; } } df_insn_rescan_all ( ) ; df_finish_pass ( false ) ; free_dominance_info ( CDI_DOMINATORS ) ; } </s>

Group the relax candidate instructions for linker .


<s> bool Z80oldTargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * ) const { return true ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> bool PPCInstrInfo :: isPredicable ( MachineInstr * MI ) const { unsigned OpC = MI -> getOpcode ( ) ; switch ( OpC ) { default : return false ; case PPC :: B : case PPC :: BLR : case PPC :: BLR8 : case PPC :: BCTR : case PPC :: BCTR8 : case PPC :: BCTRL : case PPC :: BCTRL8 : return true ; } } </s>

Return true if the specified instruction can be predicated .

PowerPC PPC PPC::B PPC::BLR PPC::BLR8 PPC::BCTR PPC::BCTR8 PPC::BCTRL PPC::BCTRL8


<s>
bool
AMDGPUMachineCFGStructurizer
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
const
SISubtarget
&
ST
=
MF
.
getSubtarget
<
SISubtarget
>
(
)
;
const
SIInstrInfo
*
TII
=
ST
.
getInstrInfo
(
)
;
TRI
=
ST
.
getRegisterInfo
(
)
;
MRI
=
&
(
MF
.
getRegInfo
(
)
)
;
initFallthroughMap
(
MF
)
;
checkRegOnlyPHIInputs
(
MF
)
;
DEBUG
(
dbgs
(
)
<<
"----STRUCTURIZER START----\n"
)
;
DEBUG
(
MF
.
dump
(
)
)
;
Regions
=
&
(
getAnalysis
<
MachineRegionInfoPass
>
(
)
.
getRegionInfo
(
)
)
;
DEBUG
(
Regions
->
dump
(
)
)
;
RegionMRT
*
RTree
=
MRT
::
buildMRT
(
MF
,
Regions
,
TII
,
MRI
)
;
setRegionMRT
(
RTree
)
;
initializeSelectRegisters
(
RTree
,
0
,
MRI
,
TII
)
;
DEBUG
(
RTree
->
dump
(
TRI
)
)
;
bool
result
=
structurizeRegions
(
RTree
,
true
)
;
delete
RTree
;
DEBUG
(
dbgs
(
)
<<
"----STRUCTURIZER END----\n"
)
;
initFallthroughMap
(
MF
)
;
return
result
;
}
</s>

runOnMachineFunction - Emit the function body .

AMDGPU
AMDGPU
SI
SI
SI
"----STRUCTURIZER START----\n"
0
"----STRUCTURIZER END----\n"


<s> const MipsMCSymbolRefExpr * MipsMCSymbolRefExpr :: Create ( VariantKind Kind , const MCSymbol * Symbol , int Offset , MCContext & Ctx ) { return new ( Ctx ) MipsMCSymbolRefExpr ( Kind , Symbol , Offset ) ; } </s>

Construct a unary instruction , given the opcode and an operand .


<s> const char * SystemZTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { OPCODE ( RET_FLAG ) ; OPCODE ( CALL ) ; OPCODE ( SIBCALL ) ; OPCODE ( PCREL_WRAPPER ) ; OPCODE ( PCREL_OFFSET ) ; OPCODE ( IABS ) ; OPCODE ( ICMP ) ; OPCODE ( FCMP ) ; OPCODE ( TM ) ; OPCODE ( BR_CCMASK ) ; OPCODE ( SELECT_CCMASK ) ; OPCODE ( ADJDYNALLOC ) ; OPCODE ( EXTRACT_ACCESS ) ; OPCODE ( UMUL_LOHI64 ) ; OPCODE ( SDIVREM64 ) ; OPCODE ( UDIVREM32 ) ; OPCODE ( UDIVREM64 ) ; OPCODE ( MVC ) ; OPCODE ( MVC_LOOP ) ; OPCODE ( NC ) ; OPCODE ( NC_LOOP ) ; OPCODE ( OC ) ; OPCODE ( OC_LOOP ) ; OPCODE ( XC ) ; OPCODE ( XC_LOOP ) ; OPCODE ( CLC ) ; OPCODE ( CLC_LOOP ) ; OPCODE ( STRCMP ) ; OPCODE ( STPCPY ) ; OPCODE ( SEARCH_STRING ) ; OPCODE ( IPM ) ; OPCODE ( SERIALIZE ) ; OPCODE ( TBEGIN ) ; OPCODE ( TBEGIN_NOFLOAT ) ; OPCODE ( TEND ) ; OPCODE ( ATOMIC_SWAPW ) ; OPCODE ( ATOMIC_LOADW_ADD ) ; OPCODE ( ATOMIC_LOADW_SUB ) ; OPCODE ( ATOMIC_LOADW_AND ) ; OPCODE ( ATOMIC_LOADW_OR ) ; OPCODE ( ATOMIC_LOADW_XOR ) ; OPCODE ( ATOMIC_LOADW_NAND ) ; OPCODE ( ATOMIC_LOADW_MIN ) ; OPCODE ( ATOMIC_LOADW_MAX ) ; OPCODE ( ATOMIC_LOADW_UMIN ) ; OPCODE ( ATOMIC_LOADW_UMAX ) ; OPCODE ( ATOMIC_CMP_SWAPW ) ; OPCODE ( PREFETCH ) ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> int vfp3_const_double_for_bits ( rtx operand ) { REAL_VALUE_TYPE r0 ; if ( ! CONST_DOUBLE_P ( operand ) ) return 0 ; REAL_VALUE_FROM_CONST_DOUBLE ( r0 , operand ) ; if ( exact_real_truncate ( DFmode , & r0 ) ) { HOST_WIDE_INT value = real_to_integer ( & r0 ) ; value = value & 0xffffffff ; if ( ( value != 0 ) && ( ( value & ( value - 1 ) ) == 0 ) ) return int_log2 ( value ) ; } return 0 ; } </s>

If X is a CONST_DOUBLE with a value that is a power of 2 whose log2 is in [ 1 , 32 ] , return that log2 . Otherwise return -1 . This is used in the patterns for vcvt.s32.f32 floating-point to fixed-point conversions .


<s> static unsigned feature_count ( const arm_feature_set * set ) { return ( bit_count ( ARM_FSET_CPU1 ( * set ) ) + bit_count ( ARM_FSET_CPU2 ( * set ) ) ) ; } </s>

Return the number of features in feature-set SET .


<s> void mt_expand_prologue ( void ) { rtx size_rtx , insn ; unsigned int frame_size ; if ( mt_interrupt_function_p ( current_function_decl ) ) { interrupt_handler = 1 ; if ( cfun -> machine ) cfun -> machine -> interrupt_handler = 1 ; } mt_compute_frame_size ( get_frame_size ( ) ) ; if ( TARGET_DEBUG_STACK ) mt_debug_stack ( & current_frame_info ) ; frame_size = current_frame_info . total_size ; if ( CONST_OK_FOR_LETTER_P ( frame_size , 'O' ) ) size_rtx = GEN_INT ( frame_size ) ; else { gcc_assert ( ! interrupt_handler ) ; size_rtx = gen_rtx_REG ( SImode , GPR_R9 ) ; insn = emit_move_insn ( size_rtx , GEN_INT ( frame_size & 0xffff0000 ) ) ; insn = emit_insn ( gen_iorsi3 ( size_rtx , size_rtx , GEN_INT ( frame_size & 0x0000ffff ) ) ) ; } if ( frame_size ) { insn = emit_insn ( gen_subsi3 ( stack_pointer_rtx , stack_pointer_rtx , size_rtx ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , stack_pointer_rtx , gen_rtx_MINUS ( SImode , stack_pointer_rtx , GEN_INT ( frame_size ) ) ) , REG_NOTES ( insn ) ) ; } if ( current_frame_info . reg_size != 0 && ! CONST_OK_FOR_LETTER_P ( frame_size , 'O' ) ) emit_insn ( gen_addsi3 ( size_rtx , size_rtx , stack_pointer_rtx ) ) ; mt_emit_save_fp ( FROM_PROCESSOR_TO_MEM , current_frame_info ) ; if ( frame_pointer_needed ) { insn = emit_move_insn ( frame_pointer_rtx , stack_pointer_rtx ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } mt_emit_save_regs ( FROM_PROCESSOR_TO_MEM , current_frame_info ) ; if ( profile_flag ) emit_insn ( gen_blockage ( ) ) ; } </s>


<s> bool HexagonInstrInfo :: isBranch ( const MachineInstr * MI ) const { return MI -> getDesc ( ) . isBranch ( ) ; } </s>

Returns true if this is a conditional , unconditional , or indirect branch .


<s>
bool
Mips16HardFloat
::
runOnModule
(
Module
&
M
)
{
DEBUG
(
errs
(
)
<<
"Run on Module Mips16HardFloat\n"
)
;
bool
Modified
=
false
;
for
(
Module
::
iterator
F
=
M
.
begin
(
)
,
E
=
M
.
end
(
)
;
F
!=
E
;
++
F
)
{
if
(
F
->
hasFnAttribute
(
"nomips16"
)
&&
F
->
hasFnAttribute
(
"use-soft-float"
)
)
{
removeUseSoftFloat
(
*
F
)
;
continue
;
}
if
(
F
->
isDeclaration
(
)
||
F
->
hasFnAttribute
(
"mips16_fp_stub"
)
||
F
->
hasFnAttribute
(
"nomips16"
)
)
continue
;
Modified
|=
fixupFPReturnAndCall
(
*
F
,
&
M
,
TM
)
;
FPParamVariant
V
=
whichFPParamVariantNeeded
(
*
F
)
;
if
(
V
!=
NoSig
)
{
Modified
=
true
;
createFPFnStub
(
F
,
&
M
,
V
,
TM
)
;
}
}
return
Modified
;
}
</s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> bool DLXInstrInfo :: optimizeCompareInstr ( MachineInstr & CmpInstr , unsigned SrcReg , unsigned SrcReg2 , int CmpMask , int CmpValue , const MachineRegisterInfo * MRI ) const { return false ; } </s>

optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare ; remove Compare if possible .


<s> int frv_emit_scc ( enum rtx_code test , rtx target ) { rtx set ; rtx test_rtx ; rtx clobber ; rtx cr_reg ; rtx cc_reg = frv_emit_comparison ( test , frv_compare_op0 , frv_compare_op1 ) ; test_rtx = gen_rtx_fmt_ee ( test , SImode , cc_reg , const0_rtx ) ; set = gen_rtx_SET ( VOIDmode , target , test_rtx ) ; cr_reg = ( ( TARGET_ALLOC_CC ) ? gen_reg_rtx ( CC_CCRmode ) : gen_rtx_REG ( CC_CCRmode , ( ( GET_MODE ( cc_reg ) == CC_FPmode ) ? FCR_FIRST : ICR_FIRST ) ) ) ; clobber = gen_rtx_CLOBBER ( VOIDmode , cr_reg ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set , clobber ) ) ) ; return TRUE ; } </s>

Emit code to set a gpr to 1/0 based on a comparison . The comparison operands were previously stored in frv_compare_op0 and frv_compare_op1 .


<s> bool canReach ( MachineBasicBlock * From , MachineBasicBlock * To ) const { assert ( inRegion ( From ) && inRegion ( To ) ) ; auto I = Reachable . find ( From ) ; if ( I == Reachable . end ( ) ) return false ; return I -> second . count ( To ) ; } </s>

If the function represented by this possition can reach Fn .


<s> void OrderedRegisterList :: remove ( unsigned VR ) { iterator L = std :: lower_bound ( Seq . begin ( ) , Seq . end ( ) , VR , Ord ) ; assert ( L != Seq . end ( ) ) ; Seq . erase ( L ) ; } </s>

remove - Remove the specified key/value pair from the map , but do not erase it .


<s> static int tilegx_compare_multipliers ( const void * key , const void * t ) { long long delta = ( * ( const long long * ) key - ( ( const struct tilegx_multiply_insn_seq * ) t ) -> multiplier ) ; return ( delta < 0 ) ? - 1 : ( delta > 0 ) ; } </s>


<s> bool SystemZElimCompare :: processBlock ( MachineBasicBlock & MBB ) { bool Changed = false ; bool CompleteCCUsers = ! isCCLiveOut ( MBB ) ; SmallVector < MachineInstr * , 4 > CCUsers ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; while ( MBBI != MBB . begin ( ) ) { MachineInstr * MI = -- MBBI ; if ( CompleteCCUsers && ( MI -> isCompare ( ) || isLoadAndTestAsCmp ( MI ) ) && ( optimizeCompareZero ( MI , CCUsers ) || fuseCompareAndBranch ( MI , CCUsers ) ) ) { ++ MBBI ; MI -> eraseFromParent ( ) ; Changed = true ; CCUsers . clear ( ) ; continue ; } Reference CCRefs ( getRegReferences ( MI , SystemZ :: CC ) ) ; if ( CCRefs . Def ) { CCUsers . clear ( ) ; CompleteCCUsers = true ; } if ( CompleteCCUsers && CCRefs . Use ) CCUsers . push_back ( MI ) ; } return Changed ; } </s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> bool HexagonCallFrameInformation :: runOnMachineFunction ( MachineFunction & MF ) { auto & HFI = * MF . getSubtarget < HexagonSubtarget > ( ) . getFrameLowering ( ) ; bool NeedCFI = MF . getMMI ( ) . hasDebugInfo ( ) || MF . getFunction ( ) -> needsUnwindTableEntry ( ) ; if ( ! NeedCFI ) return false ; HFI . insertCFIInstructions ( MF ) ; return true ; } </s>


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == nullptr ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( const auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s> static int ix86_count_insn_bb ( basic_block bb ) { rtx_insn * insn ; int insn_count = 0 ; FOR_BB_INSNS ( bb , insn ) { if ( JUMP_P ( insn ) && ANY_RETURN_P ( PATTERN ( insn ) ) ) break ; if ( NONDEBUG_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER ) { insn_count ++ ; if ( insn_count >= 4 ) return insn_count ; } } return insn_count ; } </s>

Count the minimum number of instructions in BB . Return 4 if the number of instructions > = 4 .


<s> bool RISCVDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { switch ( ConstraintID ) { case InlineAsm :: Constraint_m : OutOps . push_back ( Op ) ; return false ; case InlineAsm :: Constraint_A : OutOps . push_back ( Op ) ; return false ; default : break ; } return true ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s>
bool
MipsAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
SmallVectorImpl
<
MCParsedAsmOperand
*
>
&
Operands
)
{
if
(
requestsDoubleOperand
(
Name
)
)
{
setFpFormat
(
FP_FORMAT_D
)
;
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Name
,
NameLoc
)
)
;
}
else
{
setDefaultFpFormat
(
)
;
size_t
Start
=
0
,
Next
=
Name
.
find
(
'.'
)
;
StringRef
Mnemonic
=
Name
.
slice
(
Start
,
Next
)
;
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Mnemonic
,
NameLoc
)
)
;
if
(
Next
!=
StringRef
::
npos
)
{
size_t
Dot
=
Name
.
find
(
'.'
,
Next
+
1
)
;
StringRef
Format
=
Name
.
slice
(
Next
,
Dot
)
;
if
(
Dot
==
StringRef
::
npos
)
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Format
,
NameLoc
)
)
;
else
{
if
(
Name
.
startswith
(
"c."
)
)
{
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
"."
,
NameLoc
)
)
;
int
Cc
=
ConvertCcString
(
Format
)
;
if
(
Cc
==
1
)
{
return
Error
(
NameLoc
,
"Invalid conditional code"
)
;
}
SMLoc
E
=
Parser
.
getTok
(
)
.
getLoc
(
)
;
Operands
.
push_back
(
MipsOperand
::
CreateImm
(
MCConstantExpr
::
Create
(
Cc
,
getContext
(
)
)
,
NameLoc
,
E
)
)
;
}
else
{
return
parseMathOperation
(
Name
,
NameLoc
,
Operands
)
;
}
Format
=
Name
.
slice
(
Dot
,
StringRef
::
npos
)
;
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Format
,
NameLoc
)
)
;
}
setFpFormat
(
Format
)
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
EatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
EatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
EatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Mips
Mips
MipsOperand::CreateToken
0
MipsOperand::CreateToken
1
MipsOperand::CreateToken
"c."
MipsOperand::CreateToken
"."
1
"Invalid conditional code"
MipsOperand::CreateImm
MipsOperand::CreateToken
"unexpected token in argument list"
"unexpected token in argument list"
"unexpected token in argument list"


<s> static bool mips_get_unaligned_mem ( rtx * op , unsigned int width , int bitpos , rtx * left , rtx * right ) { rtx first , last ; if ( ! MEM_P ( * op ) ) return false ; if ( width != 32 && ( ! TARGET_64BIT || width != 64 ) ) return false ; if ( bitpos % BITS_PER_UNIT != 0 ) return false ; if ( MEM_ALIGN ( * op ) >= width ) return false ; * op = adjust_address ( * op , BLKmode , 0 ) ; set_mem_size ( * op , GEN_INT ( width / BITS_PER_UNIT ) ) ; first = adjust_address ( * op , QImode , 0 ) ; last = adjust_address ( * op , QImode , width / BITS_PER_UNIT - 1 ) ; if ( TARGET_BIG_ENDIAN ) * left = first , * right = last ; else * left = last , * right = first ; return true ; } </s>

Return true if it is possible to use left/right accesses for a bitfield of WIDTH bits starting BITPOS bits into * OP . When returning true , update * OP , * LEFT and * RIGHT as follows : * OP is a BLKmode reference to the whole field . * LEFT is a QImode reference to the first byte if big endian or the last byte if little endian . This address can be used in the left-side instructions ( lwl , swl , ldl , sdl ) . * RIGHT is a QImode reference to the opposite end of the field and can be used in the patterning right-side instruction .


<s> unsigned HexagonTTIImpl :: getOperandsScalarizationOverhead ( ArrayRef < const Value * > Args , unsigned VF ) { return BaseT :: getOperandsScalarizationOverhead ( Args , VF ) ; } </s>

Estimate the overhead of scalarizing an instructions unique non-constant operands .


<s> bool ARMBaseTargetMachine :: addPreISel ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt :: None && EnableGlobalMerge ) PM . add ( createGlobalMergePass ( getTargetLowering ( ) ) ) ; return false ; } </s>


<s> static int add_sp_insn_p ( rtx_insn * insn ) { rtx pat ; if ( ! single_set ( insn ) ) return 0 ; pat = PATTERN ( insn ) ; if ( GET_CODE ( SET_DEST ( pat ) ) != REG ) return 0 ; if ( REGNO ( SET_DEST ( pat ) ) != SP_REGNO ) return 0 ; if ( GET_CODE ( SET_SRC ( pat ) ) != PLUS ) return 0 ; if ( GET_CODE ( XEXP ( SET_SRC ( pat ) , 0 ) ) != REG ) return 0 ; if ( REGNO ( XEXP ( SET_SRC ( pat ) , 0 ) ) != SP_REGNO ) return 0 ; if ( GET_CODE ( XEXP ( SET_SRC ( pat ) , 1 ) ) != CONST_INT ) return 0 ; return INTVAL ( XEXP ( SET_SRC ( pat ) , 1 ) ) ; } </s>

If this insn adjusts the stack , return the adjustment , else return zero .


<s> TargetLoweringObjectFile * Z80TargetMachine :: getObjFileLowering ( ) const { return this -> TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s>
unsigned
ValueEnumerator
::
getValueID
(
const
Value
*
V
)
const
{
if
(
auto
*
MD
=
dyn_cast
<
MetadataAsValue
>
(
V
)
)
return
getMetadataID
(
MD
->
getMetadata
(
)
)
;
ValueMapType
::
const_iterator
I
=
ValueMap
.
find
(
V
)
;
assert
(
I
!=
ValueMap
.
end
(
)
&&
"Value not in slotcalculator!"
)
;
return
I
->
second
1
;
}
</s>

Return an ID for the concrete type of this object .

DirectX
"Value not in slotcalculator!"
1


<s> bool isMem ( ) const override { return Kind == k_Memory ; } </s>


<s> static bool aarch64_register_saved_on_entry ( int regno ) { return cfun -> machine -> frame . reg_offset [ regno ] >= 0 ; } </s>

Return true if the register REGNO is saved on entry to the current function .


Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

WebAssembly WebAssembly WebAssembly WebAssembly


<s> void PIC16RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , RegScavenger * RS ) const { } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> TargetTransformInfo SPIRVTargetMachine :: getTargetTransformInfo ( const Function & F ) { return TargetTransformInfo ( SPIRVTTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> std :: pair < unsigned , const TargetRegisterClass * > ARMTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return std :: make_pair ( 0U , ARM :: tGPRRegisterClass ) ; else return std :: make_pair ( 0U , ARM :: GPRRegisterClass ) ; case 'r' : return std :: make_pair ( 0U , ARM :: GPRRegisterClass ) ; case 'w' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , ARM :: SPRRegisterClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , ARM :: DPRRegisterClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , ARM :: QPRRegisterClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( ARM :: CPSR ) , ARM :: CCRRegisterClass ) ; return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> void MipsAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( MI -> isDebugValue ( ) ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; PrintDebugValueComment ( MI , OS ) ; return ; } if ( InConstantPool && MI -> getOpcode ( ) != Mips :: CONSTPOOL_ENTRY ) { OutStreamer . EmitDataRegion ( MCDR_DataRegionEnd ) ; InConstantPool = false ; } if ( MI -> getOpcode ( ) == Mips :: CONSTPOOL_ENTRY ) { unsigned LabelId = ( unsigned ) MI -> getOperand ( 0 ) . getImm ( ) ; unsigned CPIdx = ( unsigned ) MI -> getOperand ( 1 ) . getIndex ( ) ; if ( ! InConstantPool ) { OutStreamer . EmitDataRegion ( MCDR_DataRegion ) ; InConstantPool = true ; } OutStreamer . EmitLabel ( GetCPISymbol ( LabelId ) ) ; const MachineConstantPoolEntry & MCPE = MCP -> getConstants ( ) [ CPIdx ] ; if ( MCPE . isMachineConstantPoolEntry ( ) ) EmitMachineConstantPoolValue ( MCPE . Val . MachineCPVal ) ; else EmitGlobalConstant ( MCPE . Val . ConstVal ) ; return ; } MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { if ( emitPseudoExpansionLowering ( OutStreamer , & * I ) ) continue ; MCInst TmpInst0 ; MCInstLowering . Lower ( I , TmpInst0 ) ; OutStreamer . EmitInstruction ( TmpInst0 ) ; } while ( ( ++ I != E ) && I -> isInsideBundle ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool R600InstrInfo :: isLegalToSplitMBBAt ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) const { for ( MachineInstr :: const_mop_iterator I = MBBI -> operands_begin ( ) , E = MBBI -> operands_end ( ) ; I != E ; ++ I ) { if ( I -> isReg ( ) && ! Register :: isVirtualRegister ( I -> getReg ( ) ) && I -> isUse ( ) && RI . isPhysRegLiveAcrossClauses ( I -> getReg ( ) ) ) return false ; } return true ; } </s>

Return true if it 's legal to split the given basic block at the specified instruction ( i.e .


<s> static bool ix86_flags_dependent ( rtx_insn * insn , rtx_insn * dep_insn , enum attr_type insn_type ) { rtx set , set2 ; if ( insn_type != TYPE_SETCC && insn_type != TYPE_ICMOV && insn_type != TYPE_FCMOV && insn_type != TYPE_IBR ) return false ; if ( ( set = single_set ( dep_insn ) ) != 0 ) { set = SET_DEST ( set ) ; set2 = NULL_RTX ; } else if ( GET_CODE ( PATTERN ( dep_insn ) ) == PARALLEL && XVECLEN ( PATTERN ( dep_insn ) , 0 ) == 2 && GET_CODE ( XVECEXP ( PATTERN ( dep_insn ) , 0 , 0 ) ) == SET && GET_CODE ( XVECEXP ( PATTERN ( dep_insn ) , 0 , 1 ) ) == SET ) { set = SET_DEST ( XVECEXP ( PATTERN ( dep_insn ) , 0 , 0 ) ) ; set2 = SET_DEST ( XVECEXP ( PATTERN ( dep_insn ) , 0 , 0 ) ) ; } else return false ; if ( ! REG_P ( set ) || REGNO ( set ) != FLAGS_REG ) return false ; if ( ! reg_overlap_mentioned_p ( set , PATTERN ( insn ) ) ) return false ; if ( set2 && reg_overlap_mentioned_p ( set2 , PATTERN ( insn ) ) ) return false ; return true ; } </s>

A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set by DEP_INSN and nothing set by DEP_INSN .


<s> TargetLowering :: AtomicExpansionKind RISCVTargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * CI ) const { unsigned Size = CI -> getCompareOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size == 8 || Size == 16 ) return AtomicExpansionKind :: MaskedIntrinsic ; return AtomicExpansionKind :: None ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> Register Z80RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return Z80 :: SP ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineModuleInfo > ( ) ; AU . addPreserved < MachineModuleInfo > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
void
m32c_output_reg_push
(
FILE
*
s
,
int
regno
)
{
if
(
regno
==
FLG_REGNO
)
fprintf
(
s
,
"\tpushc\tflg\n"
)
;
else
fprintf
(
s
,
"\tpush.%c\t%s"
,
" bwll"
[
reg_push_size
(
regno
)
]
,
reg_names
[
regno
]
)
;
}
</s>

Implements ASM_OUTPUT_REG_PUSH . Control registers are pushed differently than general registers .


<s> rtx riscv_expand_builtin ( tree exp , rtx target , rtx subtarget ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , int ignore ATTRIBUTE_UNUSED ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , 0 ) ; unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; const struct riscv_builtin_description * d = & riscv_builtins [ fcode ] ; switch ( d -> builtin_type ) { case RISCV_BUILTIN_DIRECT : return riscv_expand_builtin_direct ( d -> icode , target , exp , true ) ; case RISCV_BUILTIN_DIRECT_NO_TARGET : return riscv_expand_builtin_direct ( d -> icode , target , exp , false ) ; } gcc_unreachable ( ) ; } </s>


<s>
void
output_push_multiple
(
rtx
insn
,
rtx
*
operands
)
{
char
buf
[
80
]
;
int
ok
;
ok
=
push_multiple_operation
(
PATTERN
(
insn
)
,
VOIDmode
)
;
gcc_assert
(
ok
)
;
if
(
first_dreg_to_save
==
8
)
sprintf
(
buf
,
"[--sp] = ( p5:%d );\n"
,
first_preg_to_save
)
;
else
if
(
first_preg_to_save
==
6
)
sprintf
(
buf
,
"[--sp] = ( r7:%d );\n"
,
first_dreg_to_save
)
;
else
sprintf
(
buf
,
"[--sp] = ( r7:%d, p5:%d );\n"
,
first_dreg_to_save
,
first_preg_to_save
)
;
output_asm_insn
(
buf
,
operands
)
;
}
</s>

Emit assembly code for one multi-register push described by INSN , with operands in OPERANDS .


"Not adding R_MIPS_JALR against data symbol "

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


<s> static bool mn10300_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { return ( int_size_in_bytes ( type ) > 8 || int_size_in_bytes ( type ) == 0 || TYPE_MODE ( type ) == BLKmode ) ; } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


<s> unsigned size ( ) const { return Size ; } </s>

The number of name/type pairs is returned .


<s> const MipsInstrInfo * MipsInstrInfo :: create ( MipsSubtarget & STI ) { return llvm :: createMipsSEInstrInfo ( STI ) ; } </s>


<s>
MachineBasicBlock
*
HexagonTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
case
Hexagon
::
ALLOCA
:
{
MachineFunction
*
MF
=
BB
->
getParent
(
)
;
auto
*
FuncInfo
=
MF
->
getInfo
<
HexagonMachineFunctionInfo
>
(
)
;
FuncInfo
->
addAllocaAdjustInst
(
&
MI
)
;
return
BB
;
}
default
:
llvm_unreachable
(
"Unexpected instr type to insert"
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .

Hexagon
Hexagon
Hexagon::ALLOCA
Hexagon
"Unexpected instr type to insert"


<s> MVT MOSTargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT , const ISD :: ArgFlagsTy & Flags ) const { if ( Flags . isPointer ( ) ) return MVT :: i16 ; return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT , Flags ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


"ARMHWLoops: Trip count does not fit into 32bits\n"

Query the target whether it would be profitable to convert the given loop into a hardware loop .


<s> int VEFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const VESubtarget & Subtarget = MF . getSubtarget < VESubtarget > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const VERegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; const VEMachineFunctionInfo * FuncInfo = MF . getInfo < VEMachineFunctionInfo > ( ) ; bool isFixed = MFI . isFixedObjectIndex ( FI ) ; bool UseFP = true ; if ( FuncInfo -> isLeafProc ( ) ) { UseFP = false ; } else if ( isFixed ) { UseFP = true ; } else if ( RegInfo -> needsStackRealignment ( MF ) ) { UseFP = false ; } int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) ; if ( UseFP ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FrameOffset ; } FrameReg = VE :: SX11 ; return FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { if ( CommentStream ) HasCustomInstComment = EmitAnyX86InstComments ( MI , * CommentStream , MII ) ; printInstFlags ( MI , OS ) ; if ( MI -> getOpcode ( ) == X86 :: CALLpcrel32 && ( STI . getFeatureBits ( ) [ X86 :: Mode64Bit ] ) ) { OS << "\tcallq\t" ; printPCRelImm ( MI , 0 , OS ) ; } else if ( MI -> getOpcode ( ) == X86 :: DATA16_PREFIX && STI . getFeatureBits ( ) [ X86 :: Mode16Bit ] ) { OS << "\tdata32" ; } else if ( ! printAliasInstr ( MI , OS ) && ! printVecCompareInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> VariantKind getKind ( ) const { return Kind ; } </s>


<s> bool SIInstrInfo :: shouldClusterMemOps ( const MachineOperand & BaseOp1 , const MachineOperand & BaseOp2 , unsigned NumLoads ) const { const MachineInstr & FirstLdSt = * BaseOp1 . getParent ( ) ; const MachineInstr & SecondLdSt = * BaseOp2 . getParent ( ) ; if ( ! memOpsHaveSameBasePtr ( FirstLdSt , BaseOp1 , SecondLdSt , BaseOp2 ) ) return false ; const MachineOperand * FirstDst = nullptr ; const MachineOperand * SecondDst = nullptr ; if ( ( isMUBUF ( FirstLdSt ) && isMUBUF ( SecondLdSt ) ) || ( isMTBUF ( FirstLdSt ) && isMTBUF ( SecondLdSt ) ) || ( isFLAT ( FirstLdSt ) && isFLAT ( SecondLdSt ) ) ) { const unsigned MaxGlobalLoadCluster = 6 ; if ( NumLoads > MaxGlobalLoadCluster ) return false ; FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: vdata ) ; if ( ! FirstDst ) FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: vdst ) ; SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: vdata ) ; if ( ! SecondDst ) SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: vdst ) ; } else if ( isSMRD ( FirstLdSt ) && isSMRD ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: sdst ) ; SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: sdst ) ; } else if ( isDS ( FirstLdSt ) && isDS ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: vdst ) ; SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: vdst ) ; } if ( ! FirstDst || ! SecondDst ) return false ; unsigned LoadClusterThreshold = 16 ; const MachineRegisterInfo & MRI = FirstLdSt . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const Register Reg = FirstDst -> getReg ( ) ; const TargetRegisterClass * DstRC = Register :: isVirtualRegister ( Reg ) ? MRI . getRegClass ( Reg ) : RI . getPhysRegClass ( Reg ) ; return ( NumLoads * ( RI . getRegSizeInBits ( * DstRC ) / 8 ) ) <= LoadClusterThreshold ; } </s>

Returns true if the two given memory operations should be scheduled adjacent .

AMDGPU SI 6 AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName 16 8


<s> static void maybe_clobber_cond ( rtx insn , int clock_var ) { int n , idx ; idx = ss . jump_cycle_index ; for ( n = 0 ; n < 12 ; n ++ , idx ++ ) { rtx cond , link ; int cycle ; if ( idx >= 12 ) idx -= 12 ; cycle = ss . jump_cycles [ idx ] ; if ( cycle <= clock_var ) return ; cond = ss . jump_cond [ idx ] ; if ( cond == NULL_RTX ) continue ; if ( CALL_P ( insn ) ) { ss . jump_cond [ idx ] = NULL_RTX ; continue ; } note_stores ( PATTERN ( insn ) , clobber_cond_1 , ss . jump_cond + idx ) ; for ( link = REG_NOTES ( insn ) ; link ; link = XEXP ( link , 1 ) ) if ( REG_NOTE_KIND ( link ) == REG_INC ) clobber_cond_1 ( XEXP ( link , 0 ) , NULL_RTX , ss . jump_cond + idx ) ; } } </s>

Examine INSN , and if it destroys the conditions have recorded for any of the jumps in flight , clear that condition so that we do n't predicate any more insns . CLOCK_VAR helps us limit the search to only those jumps which are still in flight .


<s> const char * HexagonTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( HexagonISD :: NodeType ) Opcode ) { case HexagonISD :: ALLOCA : return "HexagonISD::ALLOCA" ; case HexagonISD :: AT_GOT : return "HexagonISD::AT_GOT" ; case HexagonISD :: AT_PCREL : return "HexagonISD::AT_PCREL" ; case HexagonISD :: BARRIER : return "HexagonISD::BARRIER" ; case HexagonISD :: CALL : return "HexagonISD::CALL" ; case HexagonISD :: CALLnr : return "HexagonISD::CALLnr" ; case HexagonISD :: CALLR : return "HexagonISD::CALLR" ; case HexagonISD :: COMBINE : return "HexagonISD::COMBINE" ; case HexagonISD :: CONST32_GP : return "HexagonISD::CONST32_GP" ; case HexagonISD :: CONST32 : return "HexagonISD::CONST32" ; case HexagonISD :: CP : return "HexagonISD::CP" ; case HexagonISD :: DCFETCH : return "HexagonISD::DCFETCH" ; case HexagonISD :: EH_RETURN : return "HexagonISD::EH_RETURN" ; case HexagonISD :: EXTRACTU : return "HexagonISD::EXTRACTU" ; case HexagonISD :: EXTRACTURP : return "HexagonISD::EXTRACTURP" ; case HexagonISD :: INSERT : return "HexagonISD::INSERT" ; case HexagonISD :: INSERTRP : return "HexagonISD::INSERTRP" ; case HexagonISD :: JT : return "HexagonISD::JT" ; case HexagonISD :: RET_FLAG : return "HexagonISD::RET_FLAG" ; case HexagonISD :: TC_RETURN : return "HexagonISD::TC_RETURN" ; case HexagonISD :: VCOMBINE : return "HexagonISD::VCOMBINE" ; case HexagonISD :: VPACKE : return "HexagonISD::VPACKE" ; case HexagonISD :: VPACKO : return "HexagonISD::VPACKO" ; case HexagonISD :: VASL : return "HexagonISD::VASL" ; case HexagonISD :: VASR : return "HexagonISD::VASR" ; case HexagonISD :: VLSR : return "HexagonISD::VLSR" ; case HexagonISD :: VSPLAT : return "HexagonISD::VSPLAT" ; case HexagonISD :: VEXTRACTW : return "HexagonISD::VEXTRACTW" ; case HexagonISD :: VINSERTW0 : return "HexagonISD::VINSERTW0" ; case HexagonISD :: VROR : return "HexagonISD::VROR" ; case HexagonISD :: READCYCLE : return "HexagonISD::READCYCLE" ; case HexagonISD :: VZERO : return "HexagonISD::VZERO" ; case HexagonISD :: OP_END : break ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

Hexagon Hexagon HexagonISD::NodeType HexagonISD::ALLOCA "HexagonISD::ALLOCA" HexagonISD::AT_GOT "HexagonISD::AT_GOT" HexagonISD::AT_PCREL "HexagonISD::AT_PCREL" HexagonISD::BARRIER "HexagonISD::BARRIER" HexagonISD::CALL "HexagonISD::CALL" HexagonISD::CALLnr "HexagonISD::CALLnr" HexagonISD::CALLR "HexagonISD::CALLR" HexagonISD::COMBINE "HexagonISD::COMBINE" HexagonISD::CONST32_GP "HexagonISD::CONST32_GP" HexagonISD::CONST32 "HexagonISD::CONST32" HexagonISD::CP "HexagonISD::CP" HexagonISD::DCFETCH "HexagonISD::DCFETCH" HexagonISD::EH_RETURN "HexagonISD::EH_RETURN" HexagonISD::EXTRACTU "HexagonISD::EXTRACTU" HexagonISD::EXTRACTURP "HexagonISD::EXTRACTURP" HexagonISD::INSERT "HexagonISD::INSERT" HexagonISD::INSERTRP "HexagonISD::INSERTRP" HexagonISD::JT "HexagonISD::JT" HexagonISD::RET_FLAG "HexagonISD::RET_FLAG" HexagonISD::TC_RETURN "HexagonISD::TC_RETURN" HexagonISD::VCOMBINE "HexagonISD::VCOMBINE" HexagonISD::VPACKE "HexagonISD::VPACKE" HexagonISD::VPACKO "HexagonISD::VPACKO" HexagonISD::VASL "HexagonISD::VASL" HexagonISD::VASR "HexagonISD::VASR" HexagonISD::VLSR "HexagonISD::VLSR" HexagonISD::VSPLAT "HexagonISD::VSPLAT" HexagonISD::VEXTRACTW "HexagonISD::VEXTRACTW" HexagonISD::VINSERTW0 "HexagonISD::VINSERTW0" HexagonISD::VROR "HexagonISD::VROR" HexagonISD::READCYCLE "HexagonISD::READCYCLE" HexagonISD::VZERO "HexagonISD::VZERO" HexagonISD::OP_END


<s> const Cpu0Subtarget * getSubtargetImpl ( ) const { return & DefaultSubtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool ix86_expand_int_vcond ( rtx operands [ ] ) { enum machine_mode mode = GET_MODE ( operands [ 0 ] ) ; enum rtx_code code = GET_CODE ( operands [ 3 ] ) ; bool negate = false ; rtx x , cop0 , cop1 ; cop0 = operands [ 4 ] ; cop1 = operands [ 5 ] ; switch ( code ) { case EQ : case GT : case GTU : break ; case NE : case LE : case LEU : code = reverse_condition ( code ) ; negate = true ; break ; case GE : case GEU : code = reverse_condition ( code ) ; negate = true ; case LT : case LTU : code = swap_condition ( code ) ; x = cop0 , cop0 = cop1 , cop1 = x ; break ; default : gcc_unreachable ( ) ; } if ( code == GTU ) { switch ( mode ) { case V4SImode : { rtx t1 , t2 , mask ; t1 = gen_reg_rtx ( mode ) ; emit_insn ( gen_subv4si3 ( t1 , cop0 , cop1 ) ) ; mask = GEN_INT ( - 0x80000000 ) ; mask = gen_rtx_CONST_VECTOR ( mode , gen_rtvec ( 4 , mask , mask , mask , mask ) ) ; mask = force_reg ( mode , mask ) ; t2 = gen_reg_rtx ( mode ) ; emit_insn ( gen_andv4si3 ( t2 , cop0 , mask ) ) ; x = gen_reg_rtx ( mode ) ; emit_insn ( gen_xorv4si3 ( x , t1 , t2 ) ) ; code = GT ; } break ; case V16QImode : case V8HImode : x = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x , gen_rtx_US_MINUS ( mode , cop0 , cop1 ) ) ) ; code = EQ ; negate = ! negate ; break ; default : gcc_unreachable ( ) ; } cop0 = x ; cop1 = CONST0_RTX ( mode ) ; } x = ix86_expand_sse_cmp ( operands [ 0 ] , code , cop0 , cop1 , operands [ 1 + negate ] , operands [ 2 - negate ] ) ; ix86_expand_sse_movcc ( operands [ 0 ] , x , operands [ 1 + negate ] , operands [ 2 - negate ] ) ; return true ; } </s>

Expand a signed integral vector conditional move .


<s> bool fixupNeedsRelaxation ( const MCFixup & , uint64_t , const MCRelaxableFragment * , const MCAsmLayout & ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> OperandMatchResultTy M88kAsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { bool Result = parseRegister ( RegNo , StartLoc , EndLoc , true ) ; bool PendingErrors = getParser ( ) . hasPendingError ( ) ; getParser ( ) . clearPendingErrors ( ) ; if ( PendingErrors ) return MatchOperand_ParseFail ; if ( Result ) return MatchOperand_NoMatch ; return MatchOperand_Success ; } </s>

tryParseRegister - parse one register if possible


<s> static void sparc_init_pic_reg ( void ) { edge entry_edge ; rtx_insn * seq ; if ( ! crtl -> uses_pic_offset_table ) return ; start_sequence ( ) ; load_got_register ( ) ; if ( ! TARGET_VXWORKS_RTP ) emit_move_insn ( pic_offset_table_rtx , global_offset_table_rtx ) ; seq = get_insns ( ) ; end_sequence ( ) ; entry_edge = single_succ_edge ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) ; insert_insn_on_edge ( seq , entry_edge ) ; commit_one_edge_insertion ( entry_edge ) ; } </s>


<s>
const
char
*
getPassName
(
)
const
{
return
"SI insert wait  instructions"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static rtx sparc_tls_got ( void ) { if ( flag_pic ) { crtl -> uses_pic_offset_table = 1 ; return pic_offset_table_rtx ; } if ( TARGET_SUN_TLS && TARGET_ARCH32 ) { load_got_register ( ) ; return got_register_rtx ; } return copy_to_reg ( sparc_got ( ) ) ; } </s>

Return the Global Offset Table to be used in TLS mode .


<s>
SDValue
AMDGPUTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
Op
.
getNode
(
)
->
dump
(
)
;
llvm_unreachable
(
"Custom lowering code for this"
"instruction is not implemented yet!"
)
;
break
;
case
ISD
::
SIGN_EXTEND_INREG
:
return
LowerSIGN_EXTEND_INREG
(
Op
,
DAG
)
;
case
ISD
::
CONCAT_VECTORS
:
return
LowerCONCAT_VECTORS
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_SUBVECTOR
:
return
LowerEXTRACT_SUBVECTOR
(
Op
,
DAG
)
;
case
ISD
::
FrameIndex
:
return
LowerFrameIndex
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
UDIVREM
:
return
LowerUDIVREM
(
Op
,
DAG
)
;
case
ISD
::
SDIVREM
:
return
LowerSDIVREM
(
Op
,
DAG
)
;
case
ISD
::
FREM
:
return
LowerFREM
(
Op
,
DAG
)
;
case
ISD
::
FCEIL
:
return
LowerFCEIL
(
Op
,
DAG
)
;
case
ISD
::
FTRUNC
:
return
LowerFTRUNC
(
Op
,
DAG
)
;
case
ISD
::
FRINT
:
return
LowerFRINT
(
Op
,
DAG
)
;
case
ISD
::
FNEARBYINT
:
return
LowerFNEARBYINT
(
Op
,
DAG
)
;
case
ISD
::
FROUND
:
return
LowerFROUND
(
Op
,
DAG
)
;
case
ISD
::
FFLOOR
:
return
LowerFFLOOR
(
Op
,
DAG
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerSINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
UINT_TO_FP
:
return
LowerUINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_SINT
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_UINT
(
Op
,
DAG
)
;
case
ISD
::
CTLZ
:
case
ISD
::
CTLZ_ZERO_UNDEF
:
return
LowerCTLZ
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
}
return
Op
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool MipsTargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const MipsSubtarget & Subtarget = TM . getSubtarget < MipsSubtarget > ( ) ; if ( ! Subtarget . useSmallSection ( ) ) return false ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ; if ( Kind . isMergeable1ByteCString ( ) ) return false ; Type * Ty = GV -> getType ( ) -> getElementType ( ) ; return IsInSmallSection ( TM . getTargetData ( ) -> getTypeAllocSize ( Ty ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> static enum attr_op_type sched_attr_op_type ( rtx_insn * insn , bool opx_p , bool address_p ) { rtx op ; op = sched_get_operand ( insn , opx_p ) ; if ( op == NULL ) { gcc_assert ( ! reload_completed ) ; return OP_TYPE_RN ; } if ( address_p ) return sched_address_type ( QImode , op ) ; if ( memory_operand ( op , VOIDmode ) ) return sched_address_type ( GET_MODE ( op ) , XEXP ( op , 0 ) ) ; if ( register_operand ( op , VOIDmode ) ) { if ( ( ! reload_completed && FLOAT_MODE_P ( GET_MODE ( op ) ) ) || ( reload_completed && FP_REG_P ( op ) ) ) return OP_TYPE_FPN ; return OP_TYPE_RN ; } if ( GET_CODE ( op ) == CONST_INT ) { int ival ; ival = INTVAL ( op ) ; switch ( get_attr_type ( insn ) ) { case TYPE_ALUQ_L : if ( IN_RANGE ( ival , 1 , 8 ) || IN_RANGE ( ival , - 8 , - 1 ) ) return OP_TYPE_IMM_Q ; gcc_assert ( ! reload_completed ) ; break ; case TYPE_MOVEQ_L : if ( USE_MOVQ ( ival ) ) return OP_TYPE_IMM_Q ; gcc_assert ( ! reload_completed ) ; break ; case TYPE_MOV3Q_L : if ( valid_mov3q_const ( ival ) ) return OP_TYPE_IMM_Q ; gcc_assert ( ! reload_completed ) ; break ; default : break ; } if ( IN_RANGE ( ival , - 0x8000 , 0x7fff ) ) return OP_TYPE_IMM_W ; return OP_TYPE_IMM_L ; } if ( GET_CODE ( op ) == CONST_DOUBLE ) { switch ( GET_MODE ( op ) ) { case E_SFmode : return OP_TYPE_IMM_W ; case E_VOIDmode : case E_DFmode : return OP_TYPE_IMM_L ; default : gcc_unreachable ( ) ; } } if ( GET_CODE ( op ) == CONST || symbolic_operand ( op , VOIDmode ) || LABEL_P ( op ) ) { switch ( GET_MODE ( op ) ) { case E_QImode : return OP_TYPE_IMM_Q ; case E_HImode : return OP_TYPE_IMM_W ; case E_SImode : return OP_TYPE_IMM_L ; default : if ( symbolic_operand ( m68k_unwrap_symbol ( op , false ) , VOIDmode ) ) return OP_TYPE_IMM_W ; return OP_TYPE_IMM_L ; } } gcc_assert ( ! reload_completed ) ; if ( FLOAT_MODE_P ( GET_MODE ( op ) ) ) return OP_TYPE_FPN ; return OP_TYPE_RN ; } </s>

Return type of INSN 's operand X ( if OPX_P ) or operand Y ( if ! OPX_P ) . If ADDRESS_P is true , return type of memory location operand refers to .


<s> static void require_pic_register ( rtx pic_reg , bool compute_now ) { gcc_assert ( compute_now == ( pic_reg != NULL_RTX ) ) ; if ( ! crtl -> uses_pic_offset_table || compute_now ) { gcc_assert ( can_create_pseudo_p ( ) || ( pic_reg != NULL_RTX && REG_P ( pic_reg ) && GET_MODE ( pic_reg ) == Pmode ) ) ; if ( arm_pic_register != INVALID_REGNUM && ! compute_now && ! ( TARGET_THUMB1 && arm_pic_register > LAST_LO_REGNUM ) ) { if ( ! cfun -> machine -> pic_reg ) cfun -> machine -> pic_reg = gen_rtx_REG ( Pmode , arm_pic_register ) ; if ( current_ir_type ( ) != IR_GIMPLE || currently_expanding_to_rtl ) crtl -> uses_pic_offset_table = 1 ; } else { rtx_insn * seq , * insn ; if ( pic_reg == NULL_RTX ) pic_reg = gen_reg_rtx ( Pmode ) ; if ( ! cfun -> machine -> pic_reg ) cfun -> machine -> pic_reg = pic_reg ; if ( current_ir_type ( ) != IR_GIMPLE || currently_expanding_to_rtl ) { crtl -> uses_pic_offset_table = 1 ; start_sequence ( ) ; if ( TARGET_THUMB1 && arm_pic_register != INVALID_REGNUM && arm_pic_register > LAST_LO_REGNUM && ! compute_now ) emit_move_insn ( cfun -> machine -> pic_reg , gen_rtx_REG ( Pmode , arm_pic_register ) ) ; else arm_load_pic_register ( 0UL , pic_reg ) ; seq = get_insns ( ) ; end_sequence ( ) ; for ( insn = seq ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) ) INSN_LOCATION ( insn ) = prologue_location ; if ( currently_expanding_to_rtl ) insert_insn_on_edge ( seq , single_succ_edge ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) ) ; else emit_insn ( seq ) ; } } } } </s>

Record that the current function needs a PIC register . Initialize cfun- > machine- > pic_reg if we have not already done so .


<s>
void
AMDGPUPALMetadata
::
toString
(
std
::
string
&
String
)
{
String
.
clear
(
)
;
if
(
!
BlobType
)
return
;
raw_string_ostream
Stream
(
String
)
;
if
(
isLegacy
(
)
)
{
if
(
MsgPackDoc
.
getRoot
(
)
.
getKind
(
)
==
msgpack
::
Type
::
)
return
;
Stream
<<
'\t'
<<
AMDGPU
::
PALMD
::
AssemblerDirective
<<
' '
;
auto
Regs
=
getRegisters
(
)
;
for
(
auto
I
=
Regs
.
begin
(
)
,
E
=
Regs
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
I
!=
Regs
.
begin
(
)
)
Stream
<<
','
;
unsigned
Reg
=
I
->
first
.
getUInt
(
)
;
unsigned
Val
=
I
->
second
.
getUInt
(
)
;
Stream
<<
"0x"
<<
Twine
::
utohexstr
(
Reg
)
<<
",0x"
<<
Twine
::
utohexstr
(
Val
)
;
}
Stream
<<
'\n'
;
return
;
}
MsgPackDoc
.
setHexMode
(
)
;
auto
&
RegsObj
=
refRegisters
(
)
;
auto
OrigRegs
=
RegsObj
.
getMap
(
)
;
RegsObj
=
MsgPackDoc
.
getMapNode
(
)
;
for
(
auto
I
:
OrigRegs
)
{
auto
Key
=
I
.
first
;
if
(
const
char
*
RegName
=
getRegisterName
(
Key
.
getUInt
(
)
)
)
{
std
::
string
KeyName
=
Key
.
toString
(
)
;
KeyName
+=
" ("
;
KeyName
+=
RegName
;
KeyName
+=
')'
;
Key
=
MsgPackDoc
.
getNode
(
KeyName
,
true
)
;
}
RegsObj
.
getMap
(
)
[
Key
]
=
I
.
second
;
}
Stream
<<
'\t'
<<
AMDGPU
::
PALMD
::
AssemblerDirectiveBegin
<<
'\n'
;
MsgPackDoc
.
toYAML
(
Stream
)
;
Stream
<<
'\t'
<<
AMDGPU
::
PALMD
::
AssemblerDirectiveEnd
<<
'\n'
;
RegsObj
=
OrigRegs
;
}
</s>

Convert to a decimal representation in a string .

AMDGPU
AMDGPU
AMDGPU::PALMD
"0x"
",0x"
" ("
AMDGPU::PALMD
AMDGPU::PALMD


<s> TargetLowering :: AtomicExpansionKind HexagonTargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { return AtomicExpansionKind :: LLSC ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> void s390_expand_logical_operator ( enum rtx_code code , machine_mode mode , rtx * operands ) { machine_mode wmode = mode ; rtx dst = operands [ 0 ] ; rtx src1 = operands [ 1 ] ; rtx src2 = operands [ 2 ] ; rtx op , clob , tem ; if ( ! s390_logical_operator_ok_p ( operands ) ) dst = gen_reg_rtx ( mode ) ; if ( ( mode == QImode || mode == HImode ) && GET_CODE ( dst ) != MEM ) wmode = SImode ; if ( mode != wmode ) { if ( GET_CODE ( dst ) == SUBREG && ( tem = simplify_subreg ( wmode , dst , mode , 0 ) ) != 0 ) dst = tem ; else if ( REG_P ( dst ) ) dst = gen_rtx_SUBREG ( wmode , dst , 0 ) ; else dst = gen_reg_rtx ( wmode ) ; if ( GET_CODE ( src1 ) == SUBREG && ( tem = simplify_subreg ( wmode , src1 , mode , 0 ) ) != 0 ) src1 = tem ; else if ( GET_MODE ( src1 ) != VOIDmode ) src1 = gen_rtx_SUBREG ( wmode , force_reg ( mode , src1 ) , 0 ) ; if ( GET_CODE ( src2 ) == SUBREG && ( tem = simplify_subreg ( wmode , src2 , mode , 0 ) ) != 0 ) src2 = tem ; else if ( GET_MODE ( src2 ) != VOIDmode ) src2 = gen_rtx_SUBREG ( wmode , force_reg ( mode , src2 ) , 0 ) ; } op = gen_rtx_SET ( dst , gen_rtx_fmt_ee ( code , wmode , src1 , src2 ) ) ; clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , CC_REGNUM ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , op , clob ) ) ) ; if ( dst != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , gen_lowpart ( mode , dst ) ) ; } </s>

Expand logical operator CODE in mode MODE with operands OPERANDS .


<s>
MachineBasicBlock
::
iterator
AArch64InstrInfo
::
insertOutlinedCall
(
Module
&
M
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
&
It
,
MachineFunction
&
MF
,
const
outliner
::
Candidate
&
C
)
const
{
if
(
C
.
CallConstructionID
==
MachineOutlinerTailCall
)
{
It
=
MBB
.
insert
(
It
,
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
TCRETURNdi
)
)
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
.
addImm
(
0
)
)
;
return
It
;
}
if
(
C
.
CallConstructionID
==
MachineOutlinerNoLRSave
||
C
.
CallConstructionID
==
MachineOutlinerThunk
)
{
It
=
MBB
.
insert
(
It
,
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
BL
)
)
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
)
;
return
It
;
}
MachineBasicBlock
::
iterator
CallPt
;
MachineInstr
*
Save
;
MachineInstr
*
Restore
;
if
(
C
.
CallConstructionID
==
MachineOutlinerRegSave
)
{
unsigned
Reg
=
findRegisterToSaveLRTo
(
C
)
;
assert
(
Reg
!=
0
&&
"No callee-saved register available?"
)
;
if
(
!
MBB
.
isLiveIn
(
AArch64
::
LR
)
)
MBB
.
addLiveIn
(
AArch64
::
LR
)
;
Save
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
ORRXrs
)
,
Reg
)
.
addReg
(
AArch64
::
XZR
)
.
addReg
(
AArch64
::
LR
)
.
addImm
(
0
)
;
Restore
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
ORRXrs
)
,
AArch64
::
LR
)
.
addReg
(
AArch64
::
XZR
)
.
addReg
(
Reg
)
.
addImm
(
0
)
;
}
else
{
Save
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
STRXpre
)
)
.
addReg
(
AArch64
::
SP
,
RegState
::
Define
)
.
addReg
(
AArch64
::
LR
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
16
)
;
Restore
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
LDRXpost
)
)
.
addReg
(
AArch64
::
SP
,
RegState
::
Define
)
.
addReg
(
AArch64
::
LR
,
RegState
::
Define
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
16
)
;
}
It
=
MBB
.
insert
(
It
,
Save
)
;
It
++
;
It
=
MBB
.
insert
(
It
,
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
BL
)
)
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
)
;
CallPt
=
It
;
It
++
;
It
=
MBB
.
insert
(
It
,
Restore
)
;
return
CallPt
;
}
</s>

Insert a call to an outlined function into the program .


<s> unsigned MBlazeRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return hasFP ( MF ) ? MBlaze :: R19 : MBlaze :: R1 ; } </s>


<s> static unsigned int loongarch_function_arg_boundary ( machine_mode mode , const_tree type ) { unsigned int alignment ; if ( type && ! AGGREGATE_TYPE_P ( type ) ) alignment = TYPE_ALIGN ( TYPE_MAIN_VARIANT ( type ) ) ; else alignment = type ? TYPE_ALIGN ( type ) : GET_MODE_ALIGNMENT ( mode ) ; return MIN ( PREFERRED_STACK_BOUNDARY , MAX ( PARM_BOUNDARY , alignment ) ) ; } </s>

Implement TARGET_FUNCTION_ARG_BOUNDARY . Every parameter gets at least PARM_BOUNDARY bits of alignment , but will be given anything up to PREFERRED_STACK_BOUNDARY bits if the type requires it .


"Occupancy lowered for the function to "

Schedule - This is called back from ScheduleDAGInstrs : :Run ( ) when it 's time to do some work .


<s> void TeakPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & IfConverterID ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> void visium_split_cstore ( enum rtx_code op_code , rtx op0 , rtx op1 , enum rtx_code code , rtx op2 , rtx op3 ) { enum machine_mode cc_mode = visium_select_cc_mode ( code , op2 , op3 ) ; if ( cc_mode == CCFPEmode && ( op_code == NEG || op_code == MINUS ) ) cc_mode = CCFPmode ; rtx flags = gen_rtx_REG ( cc_mode , FLAGS_REGNUM ) ; rtx x = gen_rtx_COMPARE ( cc_mode , op2 , op3 ) ; x = gen_rtx_SET ( VOIDmode , flags , x ) ; emit_insn ( x ) ; x = gen_rtx_fmt_ee ( code , SImode , flags , const0_rtx ) ; switch ( op_code ) { case SET : break ; case NEG : x = gen_rtx_NEG ( SImode , x ) ; break ; case PLUS : case MINUS : x = gen_rtx_fmt_ee ( op_code , SImode , op1 , x ) ; break ; default : gcc_unreachable ( ) ; } rtx pat = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( 2 ) ) ; XVECEXP ( pat , 0 , 0 ) = gen_rtx_SET ( VOIDmode , op0 , x ) ; flags = gen_rtx_REG ( CCmode , FLAGS_REGNUM ) ; XVECEXP ( pat , 0 , 1 ) = gen_rtx_CLOBBER ( VOIDmode , flags ) ; emit_insn ( pat ) ; visium_flags_exposed = true ; } </s>

Split a compare-and-store with CODE , operands OP2 and OP3 , combined with operation with OP_CODE , operands OP0 and OP1 .


"Can only insert epilog into returning blocks"


<s>
static
void
rs6000_print_options_internal
(
FILE
*
file
,
int
indent
,
const
char
*
string
,
HOST_WIDE_INT
flags
,
const
char
*
prefix
,
const
struct
rs6000_opt_mask
*
opts
,
size_t
num_elements
)
{
size_t
i
;
size_t
start_column
=
0
;
size_t
cur_column
;
size_t
max_column
=
76
;
const
char
*
comma
=
""
;
if
(
indent
)
start_column
+=
fprintf
(
file
,
"%*s"
,
indent
,
""
)
;
if
(
!
flags
)
{
fprintf
(
stderr
,
DEBUG_FMT_S
,
string
,
"<none>"
)
;
return
;
}
start_column
+=
fprintf
(
stderr
,
DEBUG_FMT_WX
,
string
,
flags
)
;
cur_column
=
start_column
;
for
(
i
=
0
;
i
<
num_elements
;
i
++
)
{
if
(
(
flags
&
opts
[
i
]
.
mask
)
!=
0
)
{
const
char
*
no_str
=
rs6000_opt_masks
[
i
]
.
invert
"no-"
:
""
;
size_t
len
=
(
strlen
(
comma
)
+
strlen
(
prefix
)
+
strlen
(
no_str
)
+
strlen
(
rs6000_opt_masks
[
i
]
.
name
)
)
;
cur_column
+=
len
;
if
(
cur_column
>
max_column
)
{
fprintf
(
stderr
,
", \\\n%*s"
,
(
int
)
start_column
,
""
)
;
cur_column
=
start_column
+
len
;
comma
=
""
;
}
fprintf
(
file
,
"%s%s%s%s"
,
comma
,
prefix
,
no_str
,
rs6000_opt_masks
[
i
]
.
name
)
;
flags
&=
~
opts
[
i
]
.
mask
;
comma
=
", "
;
}
}
fputs
(
"\n"
,
file
)
;
}
</s>

Helper function to print the current isa or misc options on a line .


getTargetNodeName - This method returns the name of a target specific


<s> static bool is_mem_ref ( rtx pat ) { const char * fmt ; int i , j ; bool ret = false ; if ( GET_CODE ( pat ) == MEM ) return true ; fmt = GET_RTX_FORMAT ( GET_CODE ( pat ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( pat ) ) - 1 ; i >= 0 && ! ret ; i -- ) { if ( fmt [ i ] == 'e' ) ret |= is_mem_ref ( XEXP ( pat , i ) ) ; else if ( fmt [ i ] == 'E' ) for ( j = XVECLEN ( pat , i ) - 1 ; j >= 0 ; j -- ) ret |= is_mem_ref ( XVECEXP ( pat , i , j ) ) ; } return ret ; } </s>


<s> static rtx_insn * vax_md_asm_adjust ( vec < rtx > & outputs ATTRIBUTE_UNUSED , vec < rtx > & inputs ATTRIBUTE_UNUSED , vec < machine_mode > & input_modes ATTRIBUTE_UNUSED , vec < const char * > & constraints ATTRIBUTE_UNUSED , vec < rtx > & clobbers , HARD_REG_SET & clobbered_regs ) { clobbers . safe_push ( gen_rtx_REG ( CCmode , VAX_PSL_REGNUM ) ) ; SET_HARD_REG_BIT ( clobbered_regs , VAX_PSL_REGNUM ) ; return NULL ; } </s>

Mark PSL as clobbered for compatibility with the CC0 representation .


<s> static const char * s390_mangle_type ( const_tree type ) { type = TYPE_MAIN_VARIANT ( type ) ; if ( TREE_CODE ( type ) != VOID_TYPE && TREE_CODE ( type ) != BOOLEAN_TYPE && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE ) return NULL ; if ( type == s390_builtin_types [ BT_BV16QI ] ) return "U6__boolc" ; if ( type == s390_builtin_types [ BT_BV8HI ] ) return "U6__bools" ; if ( type == s390_builtin_types [ BT_BV4SI ] ) return "U6__booli" ; if ( type == s390_builtin_types [ BT_BV2DI ] ) return "U6__booll" ; if ( TYPE_MAIN_VARIANT ( type ) == long_double_type_node && TARGET_LONG_DOUBLE_128 ) return "g" ; return NULL ; } </s>


"WebAssembly does not use MCFixupKindInfo flags"

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void Cpu0FrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { } </s>

Determine the frame layout but do not update the machine function .


<s> bool SITargetLowering :: isFPExtFoldable ( const SelectionDAG & DAG , unsigned Opcode , EVT DestVT , EVT SrcVT ) const { return ( ( Opcode == ISD :: FMAD && Subtarget -> hasMadMixInsts ( ) ) || ( Opcode == ISD :: FMA && Subtarget -> hasFmaMixInsts ( ) ) ) && DestVT . getScalarType ( ) == MVT :: f32 && ! Subtarget -> hasFP32Denormals ( ) && SrcVT . getScalarType ( ) == MVT :: f16 ; } </s>

Return true if an fpext operation input to an Opcode operation is free ( for instance , because half-precision floating-point numbers are implicitly extended to float-precision ) for an FMA instruction .

AMDGPU SI ISD::FMAD ISD::FMA MVT::f32 MVT::f16


<s> static void s390_save_gprs_to_fprs ( void ) { int i ; if ( ! TARGET_Z10 || ! TARGET_HARD_FLOAT || ! crtl -> is_leaf ) return ; for ( i = 6 ; i < 16 ; i ++ ) { if ( FP_REGNO_P ( cfun_gpr_save_slot ( i ) ) ) { rtx_insn * insn = emit_move_insn ( gen_rtx_REG ( DImode , cfun_gpr_save_slot ( i ) ) , gen_rtx_REG ( DImode , i ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_REGISTER , copy_rtx ( PATTERN ( insn ) ) ) ; } } } </s>


<s> void Thumb2InstrInfo :: ReplaceTailWithBranchTo ( MachineBasicBlock :: iterator Tail , MachineBasicBlock * NewDest ) const { MachineBasicBlock * MBB = Tail -> getParent ( ) ; ARMFunctionInfo * AFI = MBB -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; if ( ! AFI -> hasITBlocks ( ) ) { TargetInstrInfo :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; return ; } unsigned PredReg = 0 ; ARMCC :: CondCodes CC = getInstrPredicate ( * Tail , PredReg ) ; MachineBasicBlock :: iterator MBBI = Tail ; if ( CC != ARMCC :: AL ) -- MBBI ; TargetInstrInfo :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; if ( CC != ARMCC :: AL ) { MachineBasicBlock :: iterator E = MBB -> begin ( ) ; unsigned Count = 4 ; while ( Count && MBBI != E ) { if ( MBBI -> isDebugValue ( ) ) { -- MBBI ; continue ; } if ( MBBI -> getOpcode ( ) == ARM :: t2IT ) { unsigned Mask = MBBI -> getOperand ( 1 ) . getImm ( ) ; if ( Count == 4 ) MBBI -> eraseFromParent ( ) ; else { unsigned MaskOn = 1 << Count ; unsigned MaskOff = ~ ( MaskOn - 1 ) ; MBBI -> getOperand ( 1 ) . setImm ( ( Mask & MaskOff ) | MaskOn ) ; } return ; } -- MBBI ; -- Count ; } } } </s>

Delete the instruction OldInst and everything after it , replacing it with an unconditional branch to NewDest .


<s> void sparc_split_mem_reg ( rtx dest , rtx src , machine_mode mode ) { rtx word0 = adjust_address ( dest , mode , 0 ) ; rtx word1 = adjust_address ( dest , mode , 4 ) ; rtx high_part = gen_highpart ( mode , src ) ; rtx low_part = gen_lowpart ( mode , src ) ; emit_move_insn_1 ( word0 , high_part ) ; emit_move_insn_1 ( word1 , low_part ) ; } </s>

Split a MEM < -- REG move into a pair of moves in MODE .


<s> static int mips_arg_partial_bytes ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , bool named ) { struct mips_arg_info info ; mips_arg_info ( cum , mode , type , named , & info ) ; return info . stack_words > 0 ? info . reg_words * UNITS_PER_WORD : 0 ; } </s>


<s> PreservedAnalyses AMDGPUPrintfRuntimeBindingPass :: run ( Module & M , ModuleAnalysisManager & AM ) { FunctionAnalysisManager & FAM = AM . getResult < FunctionAnalysisManagerModuleProxy > ( M ) . getManager ( ) ; auto GetDT = [ & FAM ] ( Function & F ) -> DominatorTree & { return FAM . getResult < DominatorTreeAnalysis > ( F ) ; } ; auto GetTLI = [ & FAM ] ( Function & F ) -> TargetLibraryInfo & { return FAM . getResult < TargetLibraryAnalysis > ( F ) ; } ; bool Changed = AMDGPUPrintfRuntimeBindingImpl ( GetDT , GetTLI ) . run ( M ) ; return Changed ? PreservedAnalyses :: none ( ) : PreservedAnalyses :: all ( ) ; } </s>

Run the analysis pass over a function and produce a dominator tree .


<s> bool GBZ80RegisterInfo :: shouldCoalesce ( MachineInstr * MI , const TargetRegisterClass * SrcRC , unsigned SubReg , const TargetRegisterClass * DstRC , unsigned DstSubReg , const TargetRegisterClass * NewRC , LiveIntervals & LIS ) const { return true ; } </s>


<s> virtual const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> void SystemZFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo * MFFrame = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; bool HasFP = hasFP ( MF ) ; SystemZMachineFunctionInfo * MFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; bool IsVarArg = MF . getFunction ( ) -> isVarArg ( ) ; if ( IsVarArg ) for ( unsigned I = MFI -> getVarArgsFirstGPR ( ) ; I < SystemZ :: NumArgGPRs ; ++ I ) SavedRegs . set ( SystemZ :: ArgGPRs [ I ] ) ; if ( HasFP ) SavedRegs . set ( SystemZ :: R11D ) ; if ( MFFrame -> hasCalls ( ) ) SavedRegs . set ( SystemZ :: R14D ) ; const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ; for ( unsigned I = 0 ; CSRegs [ I ] ; ++ I ) { unsigned Reg = CSRegs [ I ] ; if ( SystemZ :: GR64BitRegClass . contains ( Reg ) && SavedRegs . test ( Reg ) ) { SavedRegs . set ( SystemZ :: R15D ) ; break ; } } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s>
void
X86AsmBackend
::
relaxInstruction
(
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
)
const
{
bool
Is16BitMode
=
STI
.
getFeatureBits
(
)
[
X86
::
Mode16Bit
]
;
unsigned
RelaxedOp
=
getRelaxedOpcode
(
Inst
,
Is16BitMode
)
;
if
(
RelaxedOp
==
Inst
.
getOpcode
(
)
)
{
SmallString
<
256
>
Tmp
;
raw_svector_ostream
OS
(
Tmp
)
;
Inst
.
dump_pretty
(
OS
)
;
OS
<<
"\n"
;
report_fatal_error
(
"unexpected instruction to relax: "
+
OS
.
str
(
)
)
;
}
Inst
.
setOpcode
(
RelaxedOp
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> bool aarch64_mask_and_shift_for_ubfiz_p ( scalar_int_mode mode , rtx mask , rtx shft_amnt ) { return CONST_INT_P ( mask ) && CONST_INT_P ( shft_amnt ) && INTVAL ( shft_amnt ) < GET_MODE_BITSIZE ( mode ) && exact_log2 ( ( INTVAL ( mask ) >> INTVAL ( shft_amnt ) ) + 1 ) >= 0 && ( INTVAL ( mask ) & ( ( HOST_WIDE_INT_1U << INTVAL ( shft_amnt ) ) - 1 ) ) == 0 ; } </s>

Return true if the mask and a shift amount from an RTX of the form ( x < < SHFT_AMNT ) & MASK are valid to combine into a UBFIZ instruction of mode MODE . See the * andim_ashift < mode > _bfiz pattern .


<s> static std :: unique_ptr < ARMOperand > CreateReg ( unsigned RegNum , SMLoc S , SMLoc E ) { auto Op = make_unique < ARMOperand > ( k_Register ) ; Op -> Reg . RegNum = RegNum ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> void PPCTTIImpl :: getPeelingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: PeelingPreferences & PP ) { BaseT :: getPeelingPreferences ( L , SE , PP ) ; } </s>

Get target-customized preferences for the generic loop peeling transformation .


<s> bool HexagonRemoveExtendArgs :: runOnFunction ( Function & F ) { unsigned Idx = 1 ; for ( Function :: arg_iterator AI = F . arg_begin ( ) , AE = F . arg_end ( ) ; AI != AE ; ++ AI , ++ Idx ) { if ( F . getAttributes ( ) . hasAttribute ( Idx , Attribute :: SExt ) ) { Argument * Arg = AI ; if ( ! isa < PointerType > ( Arg -> getType ( ) ) ) { for ( Instruction :: use_iterator UI = Arg -> use_begin ( ) ; UI != Arg -> use_end ( ) ; ) { if ( isa < SExtInst > ( * UI ) ) { Instruction * Use = cast < Instruction > ( * UI ) ; SExtInst * SI = new SExtInst ( Arg , Use -> getType ( ) ) ; assert ( EVT :: getEVT ( SI -> getType ( ) ) == ( EVT :: getEVT ( Use -> getType ( ) ) ) ) ; ++ UI ; Use -> replaceAllUsesWith ( SI ) ; Instruction * First = F . getEntryBlock ( ) . begin ( ) ; SI -> insertBefore ( First ) ; Use -> eraseFromParent ( ) ; } else { ++ UI ; } } } } } return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> machine_mode rs6000_promote_function_mode ( const_tree type ATTRIBUTE_UNUSED , machine_mode mode , int * punsignedp ATTRIBUTE_UNUSED , const_tree , int for_return ATTRIBUTE_UNUSED ) { if ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) < ( TARGET_32BIT ? 4 : 8 ) ) mode = TARGET_32BIT ? SImode : DImode ; return mode ; } </s>

On rs6000 , function arguments are promoted , as are function return values .


<s> bool PatmosInstrInfo :: ClobbersPredicate ( MachineInstr & MI , std :: vector < MachineOperand > & Pred , bool SkipDead ) const { bool flag = false ; for ( unsigned i = 0 ; i < MI . getNumOperands ( ) ; i ++ ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDef ( ) && Patmos :: PRegsRegClass . contains ( MO . getReg ( ) ) ) { Pred . push_back ( MO ) ; flag = true ; } } return flag ; } </s>

If the specified instruction defines any predicate or condition code register ( s ) used for predication , returns true as well as the definition predicate ( s ) by reference .


<s> static bool dominates ( MachineBasicBlock & MBB , MachineBasicBlock :: const_iterator A , MachineBasicBlock :: const_iterator B ) { auto MBBEnd = MBB . end ( ) ; if ( B == MBBEnd ) return true ; MachineBasicBlock :: const_iterator I = MBB . begin ( ) ; for ( ; & * I != A && & * I != B ; ++ I ) ; return & * I == A ; } </s>

Returns true if B1 occurs before B2 in the trace , or if it is the same block as B2 .


<s> static NewSense Def ( unsigned PR , bool True , bool Float ) { NewSense NS = { PR , Float , false , True } ; return NS ; } </s>

Pointer to the VPDef that defines this VPValue .


<s> bool ARMFrameInfo :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getTarget ( ) . getRegisterInfo ( ) ; if ( STI . isTargetDarwin ( ) ) return true ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( ( DisableFramePointerElim ( MF ) && MFI -> hasCalls ( ) ) || RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static bool aarch64_advsimd_struct_mode_p ( machine_mode mode ) { return ( TARGET_SIMD && ( mode == OImode || mode == CImode || mode == XImode ) ) ; } </s>

Return true if MODE is any of the Advanced SIMD structure modes .


<s> ISD :: NodeType getExtendForAtomicCmpSwapArg ( ) const override { return ISD :: SIGN_EXTEND ; } </s>

Returns how the platform 's atomic compare and swap expects its comparison value to be extended ( ZERO_EXTEND , SIGN_EXTEND , or ANY_EXTEND ) .


<s> bool XNCMAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> std :: pair < unsigned , const TargetRegisterClass * > MBlazeTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , MBlaze :: GPRRegisterClass ) ; case 'd' : case 'y' : case 'f' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , MBlaze :: GPRRegisterClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> MCSymbol * WebAssemblyMCInstLower :: GetExternalSymbolSymbol ( const MachineOperand & MO ) const { const char * Name = MO . getSymbolName ( ) ; auto * WasmSym = cast < MCSymbolWasm > ( Printer . GetExternalSymbolSymbol ( Name ) ) ; const WebAssemblySubtarget & Subtarget = Printer . getSubtarget ( ) ; if ( strcmp ( Name , "__stack_pointer" ) == 0 || strcmp ( Name , "__tls_base" ) == 0 || strcmp ( Name , "__memory_base" ) == 0 || strcmp ( Name , "__table_base" ) == 0 || strcmp ( Name , "__tls_size" ) == 0 || strcmp ( Name , "__tls_align" ) == 0 ) { bool Mutable = strcmp ( Name , "__stack_pointer" ) == 0 || strcmp ( Name , "__tls_base" ) == 0 ; WasmSym -> setType ( wasm :: WASM_SYMBOL_TYPE_GLOBAL ) ; WasmSym -> setGlobalType ( wasm :: WasmGlobalType { uint8_t ( Subtarget . hasAddr64 ( ) && strcmp ( Name , "__table_base" ) != 0 ? wasm :: WASM_TYPE_I64 : wasm :: WASM_TYPE_I32 ) , Mutable } ) ; return WasmSym ; } SmallVector < wasm :: ValType , 4 > Returns ; SmallVector < wasm :: ValType , 4 > Params ; if ( strcmp ( Name , "__cpp_exception" ) == 0 ) { WasmSym -> setType ( wasm :: WASM_SYMBOL_TYPE_EVENT ) ; WasmSym -> setEventType ( { wasm :: WASM_EVENT_ATTRIBUTE_EXCEPTION , 0 } ) ; WasmSym -> setWeak ( true ) ; WasmSym -> setExternal ( true ) ; Params . push_back ( Subtarget . hasAddr64 ( ) ? wasm :: ValType :: I64 : wasm :: ValType :: I32 ) ; } else { WasmSym -> setType ( wasm :: WASM_SYMBOL_TYPE_FUNCTION ) ; getLibcallSignature ( Subtarget , Name , Returns , Params ) ; } auto Signature = std :: make_unique < wasm :: WasmSignature > ( std :: move ( Returns ) , std :: move ( Params ) ) ; WasmSym -> setSignature ( Signature . get ( ) ) ; Printer . addSignature ( std :: move ( Signature ) ) ; return WasmSym ; } </s>

Return the MCSymbol for the specified ExternalSymbol .


<s> void split_di ( rtx operands [ ] , int num , rtx lo_half [ ] , rtx hi_half [ ] ) { while ( num -- ) { rtx op = operands [ num ] ; lo_half [ num ] = c6x_subword ( op , false ) ; hi_half [ num ] = c6x_subword ( op , true ) ; } } </s>

Split one or more DImode RTL references into pairs of SImode references . The RTL can be REG , offsettable MEM , integer constant , or CONST_DOUBLE . `` operands '' is a pointer to an array of DImode RTL to split and `` num '' is its length . lo_half and hi_half are output arrays that parallel `` operands '' .


<s> virtual void completeType ( BTFDebug & BDebug ) { } </s>

Complete BTF type generation after all related DebugInfo types have been visited so their BTF type id 's are available for cross referece .


<s>
MCSymbol
*
TeeRISCMCInstLower
::
GetBlockAddressSymbol
(
const
MachineOperand
&
MO
)
const
{
switch
(
MO
.
getTargetFlags
(
)
)
{
default
:
llvm_unreachable
(
"Unknown target flag on GV operand"
)
;
case
0
:
break
;
}
return
Printer
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
;
}
</s>

Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block .

TeeRISC
TeeRISC
"Unknown target flag on GV operand"
0


<s>
bool
PPCAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
{
if
(
ExtraCode
[
1
]
!=
0
)
return
true
;
switch
(
ExtraCode
[
0
]
)
{
default
:
return
true
;
case
'y'
:
{
const
char
*
RegName
=
"r0"
;
if
(
!
Subtarget
->
isDarwin
(
)
)
RegName
=
PPCRegisterInfo
::
stripRegisterPrefix
(
RegName
)
;
O
<<
RegName
<<
", "
;
printOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
}
case
'U'
:
case
'X'
:
{
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
return
false
;
}
}
}
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
O
<<
"0("
;
printOperand
(
MI
,
OpNo
,
O
)
;
O
<<
")"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> static const MachineOperand & getLdStOffsetOp ( const MachineInstr & MI ) { unsigned Idx = isPairedLdSt ( MI ) || AArch64InstrInfo :: isPreLdSt ( MI ) ? 3 : 2 ; return MI . getOperand ( Idx ) ; } </s>

Returns the immediate offset operator of a load/store .


<s> int SystemZTTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; if ( BitSize > 64 ) return TTI :: TCC_Free ; if ( Imm == 0 ) return TTI :: TCC_Free ; if ( Imm . getBitWidth ( ) <= 64 ) { if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Basic ; if ( isUInt < 32 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Basic ; if ( ( Imm . getZExtValue ( ) & 0xffffffff ) == 0 ) return TTI :: TCC_Basic ; return 2 * TTI :: TCC_Basic ; } return 4 * TTI :: TCC_Basic ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> static void replace_addli_pcrel ( rtx_insn * insn ) { rtx pattern = PATTERN ( insn ) ; rtx set_src ; rtx unspec ; rtx opnds [ 4 ] ; bool first_insn_p ; gcc_assert ( GET_CODE ( pattern ) == SET ) ; opnds [ 0 ] = SET_DEST ( pattern ) ; set_src = SET_SRC ( pattern ) ; gcc_assert ( GET_CODE ( set_src ) == LO_SUM ) ; gcc_assert ( GET_CODE ( XEXP ( set_src , 1 ) ) == CONST ) ; opnds [ 1 ] = XEXP ( set_src , 0 ) ; unspec = XEXP ( XEXP ( set_src , 1 ) , 0 ) ; gcc_assert ( GET_CODE ( unspec ) == UNSPEC ) ; gcc_assert ( XINT ( unspec , 1 ) == UNSPEC_PCREL_SYM ) ; opnds [ 2 ] = XVECEXP ( unspec , 0 , 0 ) ; opnds [ 3 ] = XVECEXP ( unspec , 0 , 1 ) ; if ( GET_CODE ( opnds [ 2 ] ) != SYMBOL_REF ) return ; first_insn_p = ( opnds [ 1 ] == tilepro_text_label_rtx ( ) ) ; replace_pc_relative_symbol_ref ( insn , opnds , first_insn_p ) ; } </s>

Helper function for tilepro_fixup_pcrel_references .


<s> static rtx pdp11_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( mode , BASE_RETURN_VALUE_REG ( mode ) ) ; } </s>

Worker function for TARGET_LIBCALL_VALUE .


<s> bool ARMTargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt :: None && ! DisableLdStOpti && ! Subtarget . isThumb ( ) ) PM . add ( createARMLoadStoreOptimizationPass ( ) ) ; if ( OptLevel != CodeGenOpt :: None && ! DisableIfConversion && ! Subtarget . isThumb ( ) ) PM . add ( createIfConverterPass ( ) ) ; PM . add ( createARMConstantIslandPass ( ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> const uint32_t * ARMBaseRegisterInfo :: getThisReturnPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; if ( CC == CallingConv :: GHC ) return nullptr ; return STI . isTargetDarwin ( ) ? CSR_iOS_ThisReturn_RegMask : CSR_AAPCS_ThisReturn_RegMask ; } </s>

getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned ' is on an i32 first argument if the calling convention is one that can ( partially ) model this attribute with a preserved mask ( i.e .


<s> int eq_neq_comparison_operator ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { return ( GET_CODE ( op ) == EQ || GET_CODE ( op ) == NE ) ; } </s>

Return 1 if OP is an equality comparison , else return 0 .


<s> bool TL45AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { if ( Count == 0 ) { return true ; } return false ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> void MOSAsmPrinter :: emitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; MCInst Inst ; InstLowering . lower ( MI , Inst ) ; EmitToStreamer ( * OutStreamer , Inst ) ; } </s>

Targets should implement this to emit instructions .


"Blackfin intrinsics are not overloaded"

Return a string with the name of the plan and the applicable VFs and UFs .


<s> bool HexagonInstrInfo :: analyzeCompare ( const MachineInstr & MI , Register & SrcReg , Register & SrcReg2 , int64_t & Mask , int64_t & Value ) const { unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case Hexagon :: C2_cmpeq : case Hexagon :: C2_cmpeqp : case Hexagon :: C2_cmpgt : case Hexagon :: C2_cmpgtp : case Hexagon :: C2_cmpgtu : case Hexagon :: C2_cmpgtup : case Hexagon :: C4_cmpneq : case Hexagon :: C4_cmplte : case Hexagon :: C4_cmplteu : case Hexagon :: C2_cmpeqi : case Hexagon :: C2_cmpgti : case Hexagon :: C2_cmpgtui : case Hexagon :: C4_cmpneqi : case Hexagon :: C4_cmplteui : case Hexagon :: C4_cmpltei : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; Mask = ~ 0 ; break ; case Hexagon :: A4_cmpbeq : case Hexagon :: A4_cmpbgt : case Hexagon :: A4_cmpbgtu : case Hexagon :: A4_cmpbeqi : case Hexagon :: A4_cmpbgti : case Hexagon :: A4_cmpbgtui : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; Mask = 0xFF ; break ; case Hexagon :: A4_cmpheq : case Hexagon :: A4_cmphgt : case Hexagon :: A4_cmphgtu : case Hexagon :: A4_cmpheqi : case Hexagon :: A4_cmphgti : case Hexagon :: A4_cmphgtui : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; Mask = 0xFFFF ; break ; } switch ( Opc ) { case Hexagon :: C2_cmpeq : case Hexagon :: C2_cmpeqp : case Hexagon :: C2_cmpgt : case Hexagon :: C2_cmpgtp : case Hexagon :: C2_cmpgtu : case Hexagon :: C2_cmpgtup : case Hexagon :: A4_cmpbeq : case Hexagon :: A4_cmpbgt : case Hexagon :: A4_cmpbgtu : case Hexagon :: A4_cmpheq : case Hexagon :: A4_cmphgt : case Hexagon :: A4_cmphgtu : case Hexagon :: C4_cmpneq : case Hexagon :: C4_cmplte : case Hexagon :: C4_cmplteu : SrcReg2 = MI . getOperand ( 2 ) . getReg ( ) ; return true ; case Hexagon :: C2_cmpeqi : case Hexagon :: C2_cmpgtui : case Hexagon :: C2_cmpgti : case Hexagon :: C4_cmpneqi : case Hexagon :: C4_cmplteui : case Hexagon :: C4_cmpltei : case Hexagon :: A4_cmpbeqi : case Hexagon :: A4_cmpbgti : case Hexagon :: A4_cmpbgtui : case Hexagon :: A4_cmpheqi : case Hexagon :: A4_cmphgti : case Hexagon :: A4_cmphgtui : { SrcReg2 = 0 ; const MachineOperand & Op2 = MI . getOperand ( 2 ) ; if ( ! Op2 . isImm ( ) ) return false ; Value = MI . getOperand ( 2 ) . getImm ( ) ; return true ; } } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> static void h8300_emit_stack_adjustment ( int sign , HOST_WIDE_INT size , bool in_prologue ) { if ( size == 0 ) return ; if ( Pmode == HImode ) { rtx_insn * x = emit_insn ( gen_addhi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( sign * size ) ) ) ; if ( size < 4 ) F ( x , 0 ) ; } else F ( emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( sign * size ) ) ) , 0 ) ; } </s>

Output assembly language to FILE for the operation OP with operand size SIZE to adjust the stack pointer .


<s> bool SparcAsmPrinter :: isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { if ( MBB -> isLandingPad ( ) || MBB -> pred_empty ( ) ) return false ; MachineBasicBlock :: const_pred_iterator PI = MBB -> pred_begin ( ) , PI2 = PI ; ++ PI2 ; if ( PI2 != MBB -> pred_end ( ) ) return false ; const MachineBasicBlock * Pred = * PI ; if ( ! Pred -> isLayoutSuccessor ( MBB ) ) return false ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> getDesc ( ) . isTerminator ( ) ) ; return I == Pred -> end ( ) || ! I -> getDesc ( ) . isBarrier ( ) ; } </s>

isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


<s> bool SITargetLowering :: isFMADLegal ( const SelectionDAG & DAG , const SDNode * N ) const { EVT VT = N -> getValueType ( 0 ) ; if ( VT == MVT :: f32 ) return ! hasFP32Denormals ( DAG . getMachineFunction ( ) ) ; if ( VT == MVT :: f16 ) { return Subtarget -> hasMadF16 ( ) && ! hasFP64FP16Denormals ( DAG . getMachineFunction ( ) ) ; } return false ; } </s>

Returns true if MI can be combined with another instruction to form TargetOpcode : :G_FMAD .


<s> bool reg_overlap_p ( rtx x , rtx in ) { if ( x == NULL_RTX || in == NULL_RTX ) return false ; return static_cast < bool > ( reg_overlap_mentioned_p ( x , in ) ) ; } </s>

A safe wrapper to the function reg_overlap_mentioned_p ( ) .


<s>
bool
R600Packetizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
const
TargetInstrInfo
*
TII
=
Fn
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
MachineLoopInfo
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
R600PacketizerList
Packetizer
(
Fn
,
MLI
)
;
assert
(
Packetizer
.
getResourceTracker
(
)
&&
"Empty DFA table!"
)
;
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
MachineBasicBlock
::
iterator
End
=
MBB
->
end
(
)
;
MachineBasicBlock
::
iterator
MI
=
MBB
->
begin
(
)
;
while
(
MI
!=
End
)
{
if
(
MI
->
isKill
(
)
||
MI
->
getOpcode
(
)
==
AMDGPU
::
IMPLICIT_DEF
||
(
MI
->
getOpcode
(
)
==
AMDGPU
::
CF_ALU
&&
!
MI
->
getOperand
(
8
)
.
getImm
(
)
)
)
{
MachineBasicBlock
::
iterator
DeleteMI
=
MI
;
++
MI
;
MBB
->
erase
(
DeleteMI
)
;
End
=
MBB
->
end
(
)
;
continue
;
}
++
MI
;
}
}
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
unsigned
RemainingCount
=
MBB
->
size
(
)
;
for
(
MachineBasicBlock
::
iterator
RegionEnd
=
MBB
->
end
(
)
;
RegionEnd
!=
MBB
->
begin
(
)
;
)
{
MachineBasicBlock
::
iterator
I
=
RegionEnd
;
for
(
;
I
!=
MBB
->
begin
(
)
;
I
,
RemainingCount
)
{
if
(
TII
->
isSchedulingBoundary
(
&
*
std
::
prev
(
I
)
,
&
*
MBB
,
Fn
)
)
break
;
}
I
=
MBB
->
begin
(
)
;
if
(
I
==
RegionEnd
)
{
RegionEnd
=
std
::
prev
(
RegionEnd
)
;
RemainingCount
;
continue
;
}
if
(
I
==
std
::
prev
(
RegionEnd
)
)
{
RegionEnd
=
std
::
prev
(
RegionEnd
)
;
continue
;
}
Packetizer
.
PacketizeMIs
(
&
*
MBB
,
&
*
I
,
RegionEnd
)
;
RegionEnd
=
I
;
}
}
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool SIFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; const SIInstrInfo * TII = MF . getSubtarget < GCNSubtarget > ( ) . getInstrInfo ( ) ; for ( const CalleeSavedInfo & CS : CSI ) { unsigned Reg = CS . getReg ( ) ; if ( CS . isSpilledToReg ( ) ) { BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const bool IsLiveIn = MRI . isLiveIn ( Reg ) ; TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ; } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static int fr30_arg_partial_bytes ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( ! arg . named || * cum >= FR30_NUM_ARG_REGS ) return 0 ; if ( * cum + fr30_num_arg_regs ( arg ) <= FR30_NUM_ARG_REGS ) return 0 ; return ( FR30_NUM_ARG_REGS - * cum ) * UNITS_PER_WORD ; } </s>

Returns the number of bytes in which * part * of a parameter of machine mode MODE and tree type TYPE ( which may be NULL if the type is not known ) . If the argument fits entirely in the argument registers , or entirely on the stack , then 0 is returned . CUM is the number of argument registers already used by earlier parameters to the function .


<s>
StringRef
getPassName
(
)
const
override
{
return
"SI Final Branch Preparation"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
void
ARMBaseInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
bool
GPRDest
=
ARM
::
GPRRegClass
.
contains
(
DestReg
)
;
bool
GPRSrc
=
ARM
::
GPRRegClass
.
contains
(
SrcReg
)
;
if
(
GPRDest
&&
GPRSrc
)
{
AddDefaultCC
(
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
MOVr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
)
)
;
return
;
}
bool
SPRDest
=
ARM
::
SPRRegClass
.
contains
(
DestReg
)
;
bool
SPRSrc
=
ARM
::
SPRRegClass
.
contains
(
SrcReg
)
;
unsigned
Opc
=
0
;
if
(
SPRDest
&&
SPRSrc
)
Opc
=
ARM
::
VMOVS
;
else
if
(
GPRDest
&&
SPRSrc
)
Opc
=
ARM
::
VMOVRS
;
else
if
(
SPRDest
&&
GPRSrc
)
Opc
=
ARM
::
VMOVSR
;
else
if
(
ARM
::
DPRRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
ARM
::
VMOVD
;
else
if
(
ARM
::
QPRRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
ARM
::
VORRq
;
if
(
Opc
)
{
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DestReg
)
;
MIB
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
if
(
Opc
==
ARM
::
VORRq
)
MIB
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
AddDefaultPred
(
MIB
)
;
return
;
}
if
(
ARM
::
QQPRRegClass
.
contains
(
DestReg
,
SrcReg
)
||
ARM
::
QQQQPRRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
assert
(
ARM
::
qsub_0
+
3
==
ARM
::
qsub_3
&&
"Expected contiguous enum."
)
;
unsigned
EndSubReg
=
ARM
::
QQPRRegClass
.
contains
(
DestReg
,
SrcReg
)
ARM
::
qsub_1
:
ARM
::
qsub_3
;
for
(
unsigned
i
=
ARM
::
qsub_0
,
e
=
EndSubReg
+
1
;
i
!=
e
;
++
i
)
{
unsigned
Dst
=
TRI
->
getSubReg
(
DestReg
,
i
)
;
unsigned
Src
=
TRI
->
getSubReg
(
SrcReg
,
i
)
;
MachineInstrBuilder
Mov
=
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
I
->
getDebugLoc
(
)
,
get
(
ARM
::
VORRq
)
)
.
addReg
(
Dst
,
RegState
::
Define
)
.
addReg
(
Src
,
getKillRegState
(
KillSrc
)
)
.
addReg
(
Src
,
getKillRegState
(
KillSrc
)
)
)
;
if
(
i
==
EndSubReg
)
{
Mov
->
addRegisterDefined
(
DestReg
,
TRI
)
;
if
(
KillSrc
)
Mov
->
addRegisterKilled
(
SrcReg
,
TRI
)
;
}
}
return
;
}
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
</s>

ARM
ARM
ARM::GPRRegClass
ARM::GPRRegClass
ARM::MOVr
ARM::SPRRegClass
ARM::SPRRegClass
0
ARM::VMOVS
ARM::VMOVRS
ARM::VMOVSR
ARM::DPRRegClass
ARM::VMOVD
ARM::QPRRegClass
ARM::VORRq
ARM::VORRq
ARM::QQPRRegClass
ARM::QQQQPRRegClass
ARM::qsub_0
3
ARM::qsub_3
"Expected contiguous enum."
ARM::QQPRRegClass
ARM::qsub_1
ARM::qsub_3
ARM::qsub_0
1
ARM::VORRq
"Impossible reg-to-reg copy"


<s> void MSP430FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const MSP430InstrInfo & TII = * static_cast < const MSP430InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; unsigned StackAlign = getStackAlignment ( ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; uint64_t Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = nullptr ; if ( Old -> getOpcode ( ) == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( MSP430 :: SUB16ri ) , MSP430 :: SPW ) . addReg ( MSP430 :: SPW ) . addImm ( Amount ) ; } else { assert ( Old -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) ; uint64_t CalleeAmt = Old -> getOperand ( 1 ) . getImm ( ) ; Amount -= CalleeAmt ; if ( Amount ) New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( MSP430 :: ADD16ri ) , MSP430 :: SPW ) . addReg ( MSP430 :: SPW ) . addImm ( Amount ) ; } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { MachineInstr * Old = I ; MachineInstr * New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( MSP430 :: SUB16ri ) , MSP430 :: SPW ) . addReg ( MSP430 :: SPW ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> int rs6000_emit_vector_cond_expr ( rtx dest , rtx op_true , rtx op_false , rtx cond , rtx cc_op0 , rtx cc_op1 ) { machine_mode dest_mode = GET_MODE ( dest ) ; machine_mode mask_mode = GET_MODE ( cc_op0 ) ; enum rtx_code rcode = GET_CODE ( cond ) ; machine_mode cc_mode = CCmode ; rtx mask ; rtx cond2 ; bool invert_move = false ; if ( VECTOR_UNIT_NONE_P ( dest_mode ) ) return 0 ; gcc_assert ( GET_MODE_SIZE ( dest_mode ) == GET_MODE_SIZE ( mask_mode ) && GET_MODE_NUNITS ( dest_mode ) == GET_MODE_NUNITS ( mask_mode ) ) ; switch ( rcode ) { case NE : case UNLE : case UNLT : case UNGE : case UNGT : invert_move = true ; rcode = reverse_condition_maybe_unordered ( rcode ) ; if ( rcode == UNKNOWN ) return 0 ; break ; case GE : case LE : if ( GET_MODE_CLASS ( mask_mode ) == MODE_VECTOR_INT ) { invert_move = true ; rcode = reverse_condition ( rcode ) ; } break ; case GTU : case GEU : case LTU : case LEU : cc_mode = CCUNSmode ; if ( rcode == GEU || rcode == LEU ) { invert_move = true ; rcode = reverse_condition ( rcode ) ; } break ; default : break ; } mask = rs6000_emit_vector_compare ( rcode , cc_op0 , cc_op1 , mask_mode ) ; if ( ! mask ) return 0 ; if ( invert_move ) std :: swap ( op_true , op_false ) ; if ( GET_MODE_CLASS ( dest_mode ) == MODE_VECTOR_INT && ( GET_CODE ( op_true ) == CONST_VECTOR || GET_CODE ( op_false ) == CONST_VECTOR ) ) { rtx constant_0 = CONST0_RTX ( dest_mode ) ; rtx constant_m1 = CONSTM1_RTX ( dest_mode ) ; if ( op_true == constant_m1 && op_false == constant_0 ) { emit_move_insn ( dest , mask ) ; return 1 ; } else if ( op_true == constant_0 && op_false == constant_m1 ) { emit_insn ( gen_rtx_SET ( dest , gen_rtx_NOT ( dest_mode , mask ) ) ) ; return 1 ; } if ( op_true == constant_m1 ) op_true = mask ; if ( op_false == constant_0 ) op_false = mask ; } if ( ! REG_P ( op_true ) && ! SUBREG_P ( op_true ) ) op_true = force_reg ( dest_mode , op_true ) ; if ( ! REG_P ( op_false ) && ! SUBREG_P ( op_false ) ) op_false = force_reg ( dest_mode , op_false ) ; cond2 = gen_rtx_fmt_ee ( NE , cc_mode , gen_lowpart ( dest_mode , mask ) , CONST0_RTX ( dest_mode ) ) ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_IF_THEN_ELSE ( dest_mode , cond2 , op_true , op_false ) ) ) ; return 1 ; } </s>

Emit vector conditional expression . DEST is destination . OP1 and OP2 are two VEC_COND_EXPR operands . CC_OP0 and CC_OP1 are the two operands for the relation operation COND .


"********** AArch64 Conditional Compares **********\n"


<s> int R600InstrInfo :: getSrcIdx ( unsigned Opcode , unsigned SrcNum ) const { static const unsigned OpTable [ ] = { AMDGPU :: OpName :: src0 , AMDGPU :: OpName :: src1 , AMDGPU :: OpName :: src2 } ; assert ( SrcNum < 3 ) ; return getOperandIdx ( Opcode , OpTable [ SrcNum ] ) ; } </s>

Return the subregister index that SrcReg will be coalesced into , or 0 .

AMDGPU R600 AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName 3


<s> MCSymbol * X86TargetLowering :: getPICBaseSymbol ( const MachineFunction * MF , MCContext & Ctx ) const { const MCAsmInfo & MAI = * getTargetMachine ( ) . getMCAsmInfo ( ) ; return Ctx . GetOrCreateTemporarySymbol ( Twine ( MAI . getPrivateGlobalPrefix ( ) ) + Twine ( MF -> getFunctionNumber ( ) ) + "$pb" ) ; } </s>

getPICBaseSymbol - Return a function-local symbol to represent the PIC base .


"For each split Type there should be exactly one VReg."

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s>
void
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
override
{
verifyInstructionPredicates
(
MI
,
computeAvailableFeatures
(
STI
.
getFeatureBits
(
)
)
)
;
unsigned
Opcode
=
MI
.
getOpcode
(
)
;
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
Opcode
)
;
uint64_t
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
unsigned
Size
=
Desc
.
getSize
(
)
;
switch
(
Size
)
{
case
0
:
break
;
case
4
:
if
(
IsLittleEndian
)
{
support
::
endian
::
Writer
<
support
::
little
>
(
OS
)
.
write
<
uint32_t
>
(
Bits
)
;
}
else
{
support
::
endian
::
Writer
<
support
::
big
>
(
OS
)
.
write
<
uint32_t
>
(
Bits
)
;
}
break
;
case
8
:
if
(
IsLittleEndian
)
{
uint64_t
Swapped
=
(
Bits
<<
32
)
|
(
Bits
>>
32
)
;
support
::
endian
::
Writer
<
support
::
little
>
(
OS
)
.
write
<
uint64_t
>
(
Swapped
)
;
}
else
{
support
::
endian
::
Writer
<
support
::
big
>
(
OS
)
.
write
<
uint64_t
>
(
Bits
)
;
}
break
;
default
:
llvm_unreachable
(
"Invalid instruction size"
)
;
}
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .

PowerPC
0
4
support::endian
support::little
support::endian
support::big
8
32
32
support::endian
support::little
support::endian
support::big
"Invalid instruction size"


<s> bool HexagonCallFrameInformation :: runOnMachineFunction ( MachineFunction & MF ) { auto & HFI = * MF . getSubtarget < HexagonSubtarget > ( ) . getFrameLowering ( ) ; bool NeedCFI = MF . getMMI ( ) . hasDebugInfo ( ) || MF . getFunction ( ) . needsUnwindTableEntry ( ) ; if ( ! NeedCFI ) return false ; HFI . insertCFIInstructions ( MF ) ; return true ; } </s>


<s> bool RISCVInstrInfo :: isMBBSafeToOutlineFrom ( MachineBasicBlock & MBB , unsigned & Flags ) const { return true ; } </s>

Optional target hook that returns true if MBB is safe to outline from , and returns any target-specific information in Flags .


<s> static int mips_register_move_cost ( machine_mode mode , reg_class_t from , reg_class_t to ) { reg_class_t dregs ; int cost1 , cost2 ; from = mips_canonicalize_move_class ( from ) ; to = mips_canonicalize_move_class ( to ) ; if ( from == FP_REGS ) { if ( to == FP_REGS && mips_mode_ok_for_mov_fmt_p ( mode ) ) return 4 ; } dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS ; if ( from == dregs ) return mips_move_from_gpr_cost ( to ) ; if ( to == dregs ) return mips_move_to_gpr_cost ( from ) ; cost1 = mips_move_to_gpr_cost ( from ) ; if ( cost1 != 0 ) { cost2 = mips_move_from_gpr_cost ( to ) ; if ( cost2 != 0 ) return cost1 + cost2 ; } return 0 ; } </s>

Implement TARGET_REGISTER_MOVE_COST . Return 0 for classes that are the maximum of the move costs for subclasses ; regclass will work out the maximum for us .


<s>
SDValue
PTXTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unimplemented operand"
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

PTX
PTX
"Unimplemented operand"
ISD::GlobalAddress


<s> const AArch64InstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>