<s> static int constant_pool_expr_1 ( rtx op , int * have_sym , int * have_toc ) { switch ( GET_CODE ( op ) ) { case SYMBOL_REF : if ( RS6000_SYMBOL_REF_TLS_P ( op ) ) return 0 ; else if ( CONSTANT_POOL_ADDRESS_P ( op ) ) { if ( ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( get_pool_constant ( op ) , Pmode ) ) { * have_sym = 1 ; return 1 ; } else return 0 ; } else if ( ! strcmp ( XSTR ( op , 0 ) , toc_label_name ) ) { * have_toc = 1 ; return 1 ; } else return 0 ; case PLUS : case MINUS : return ( constant_pool_expr_1 ( XEXP ( op , 0 ) , have_sym , have_toc ) && constant_pool_expr_1 ( XEXP ( op , 1 ) , have_sym , have_toc ) ) ; case CONST : return constant_pool_expr_1 ( XEXP ( op , 0 ) , have_sym , have_toc ) ; case CONST_INT : return 1 ; default : return 0 ; } } </s>

Subroutines of rs6000_legitimize_address and rs6000_legitimate_address .


<s> void AArch64_ELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; } </s>

This method must be called before any actual lowering is done .


<s> bool mem_operand_ds_form ( rtx op , machine_mode mode ) { unsigned HOST_WIDE_INT offset ; int extra ; rtx addr = XEXP ( op , 0 ) ; if ( ! offsettable_address_p ( false , mode , addr ) ) return false ; op = address_offset ( addr ) ; if ( op == NULL_RTX ) return true ; offset = INTVAL ( op ) ; if ( ( offset & 3 ) != 0 ) return false ; extra = GET_MODE_SIZE ( mode ) - UNITS_PER_WORD ; if ( extra < 0 ) extra = 0 ; if ( GET_CODE ( addr ) == LO_SUM ) offset = ( ( offset & 0xffff ) ^ 0x8000 ) - 0x8000 ; return offset + 0x8000 < 0x10000u - extra ; } </s>

As above , but for DS-FORM VSX insns . Unlike mem_operand_gpr , enforce an offset divisible by 4 even for 32-bit .


<s> void AAPFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> int s390_cannot_change_mode_class ( machine_mode from_mode , machine_mode to_mode , enum reg_class rclass ) { machine_mode small_mode ; machine_mode big_mode ; if ( reg_classes_intersect_p ( VEC_REGS , rclass ) && ( ( from_mode == V1TFmode && to_mode == TFmode ) || ( from_mode == TFmode && to_mode == V1TFmode ) ) ) return 1 ; if ( GET_MODE_SIZE ( from_mode ) == GET_MODE_SIZE ( to_mode ) ) return 0 ; if ( GET_MODE_SIZE ( from_mode ) < GET_MODE_SIZE ( to_mode ) ) { small_mode = from_mode ; big_mode = to_mode ; } else { small_mode = to_mode ; big_mode = from_mode ; } if ( reg_classes_intersect_p ( VEC_REGS , rclass ) && ( GET_MODE_SIZE ( small_mode ) < 8 || s390_class_max_nregs ( VEC_REGS , big_mode ) == 1 ) ) return 1 ; if ( reg_classes_intersect_p ( ACCESS_REGS , rclass ) ) return 1 ; return 0 ; } </s>

Return TRUE if changing mode from FROM to TO should not be allowed for register class CLASS .


<s> static struct machine_function * ix86_init_machine_status ( void ) { struct machine_function * f ; f = ggc_cleared_alloc < machine_function > ( ) ; f -> use_fast_prologue_epilogue_nregs = - 1 ; f -> call_abi = ix86_abi ; return f ; } </s>

Clear stack slot assignments remembered from previous functions . This is called from INIT_EXPANDERS once before RTL is emitted for each function .


<s> void arc_split_ior ( rtx * operands ) { unsigned HOST_WIDE_INT mask , maskx ; rtx op1 = operands [ 1 ] ; gcc_assert ( CONST_INT_P ( operands [ 2 ] ) ) ; mask = INTVAL ( operands [ 2 ] ) & 0xffffffff ; if ( __builtin_popcount ( mask ) > 3 || ( mask & 0x3f ) ) { maskx = mask & 0x3f ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , gen_rtx_IOR ( SImode , op1 , GEN_INT ( maskx ) ) ) ) ; op1 = operands [ 0 ] ; mask &= ~ maskx ; } switch ( __builtin_popcount ( mask ) ) { case 3 : maskx = 1 << ( __builtin_ffs ( mask ) - 1 ) ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , gen_rtx_IOR ( SImode , op1 , GEN_INT ( maskx ) ) ) ) ; mask &= ~ maskx ; op1 = operands [ 0 ] ; case 2 : maskx = 1 << ( __builtin_ffs ( mask ) - 1 ) ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , gen_rtx_IOR ( SImode , op1 , GEN_INT ( maskx ) ) ) ) ; mask &= ~ maskx ; op1 = operands [ 0 ] ; case 1 : maskx = 1 << ( __builtin_ffs ( mask ) - 1 ) ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , gen_rtx_IOR ( SImode , op1 , GEN_INT ( maskx ) ) ) ) ; break ; case 0 : break ; default : gcc_unreachable ( ) ; } } </s>

Split an OR instruction into multiple BSET/OR instructions in a attempt to avoid long immediate constants . The next strategies are employed when destination is ' q ' reg . 1. if there are up to three bits set in the mask , a succession of three bset instruction will be emitted : OR rA , rB , mask - > BSET ( _S ) rA , rB , mask1/BSET_S rA , rA , mask2/BSET_S rA , rA , mask3 2. if the lower 6 bits of the mask is set and there is only one bit set in the upper remaining bits then we will emit one bset and one OR instruction : OR rA , rB , mask - > OR rA , rB , mask1/BSET_S rA , mask2 3. otherwise an OR with limm will be emmitted .


<s> unsigned SparcAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand * GOp , unsigned Kind ) { SparcOperand * Op = ( SparcOperand * ) GOp ; if ( Op -> isFloatOrDoubleReg ( ) ) { switch ( Kind ) { default : break ; case MCK_DFPRegs : if ( ! Op -> isFloatReg ( ) || SparcOperand :: MorphToDoubleReg ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; case MCK_QFPRegs : if ( SparcOperand :: MorphToQuadReg ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; } } return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .

Sparc Sparc Sparc Sparc SparcOperand::MorphToDoubleReg SparcOperand::MorphToQuadReg


<s> bool MipsInstrInfo :: HasForbiddenSlot ( const MachineInstr & MI ) const { return ( MI . getDesc ( ) . TSFlags & MipsII :: HasForbiddenSlot ) != 0 ; } </s>

Predicate to determine if an instruction has a forbidden slot .


<s> bool SystemZInstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Pred , unsigned TrueReg , unsigned FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( ! STI . hasLoadStoreOnCond ( ) ) return false ; if ( Pred . size ( ) != 2 ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( ( STI . hasLoadStoreOnCond2 ( ) && SystemZ :: GRX32BitRegClass . hasSubClassEq ( RC ) ) || SystemZ :: GR32BitRegClass . hasSubClassEq ( RC ) || SystemZ :: GR64BitRegClass . hasSubClassEq ( RC ) ) { CondCycles = 2 ; TrueCycles = 2 ; FalseCycles = 2 ; return true ; } return false ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s>
void
Z80DAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
SDLoc
DL
(
Node
)
;
DEBUG
(
dbgs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


"Pseudo opcode found in EmitInstruction()"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


"No MachineFunctionInfo for this function!"

runOnMachineFunction - Emit the function body .


<s> void NVPTXRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) + MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( NVPTX :: VRFrame , false ) ; MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s>
void
ARMConstantIslands
::
verify
(
)
{
for
(
MachineFunction
::
iterator
MBBI
=
MF
->
begin
(
)
,
E
=
MF
->
end
(
)
;
MBBI
!=
E
;
++
MBBI
)
{
MachineBasicBlock
*
MBB
=
MBBI
;
unsigned
Align
=
MBB
->
getAlignment
(
)
;
unsigned
MBBId
=
MBB
->
getNumber
(
)
;
assert
(
BBInfo
[
MBBId
]
.
Offset
%
(
1u
<<
Align
)
==
0
)
;
assert
(
!
MBBId
||
BBInfo
[
MBBId
1
]
.
postOffset
(
)
<=
BBInfo
[
MBBId
]
.
Offset
)
;
}
DEBUG
(
dbgs
(
)
<<
"Verifying "
<<
CPUsers
.
size
(
)
<<
" CP users.\n"
)
;
for
(
unsigned
i
=
0
,
e
=
CPUsers
.
size
(
)
;
i
!=
e
;
++
i
)
{
CPUser
&
U
=
CPUsers
[
i
]
;
unsigned
UserOffset
=
getUserOffset
(
U
)
;
if
(
isCPEntryInRange
(
U
.
MI
,
UserOffset
,
U
.
CPEMI
,
U
.
getMaxDisp
(
)
+
2
,
U
.
NegOk
,
true
)
)
{
DEBUG
(
dbgs
(
)
<<
"OK\n"
)
;
continue
;
}
DEBUG
(
dbgs
(
)
<<
"Out of range.\n"
)
;
dumpBBs
(
)
;
DEBUG
(
MF
->
dump
(
)
)
;
llvm_unreachable
(
"Constant pool entry out of range!"
)
;
}
}
</s>


<s> BitVector VERegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const Register ReservedRegs [ ] = { VE :: SX8 , VE :: SX9 , VE :: SX10 , VE :: SX11 , VE :: SX12 , VE :: SX13 , VE :: SX14 , VE :: SX15 , VE :: SX16 , VE :: SX17 , } ; for ( auto R : ReservedRegs ) for ( MCRegAliasIterator ItAlias ( R , this , true ) ; ItAlias . isValid ( ) ; ++ ItAlias ) Reserved . set ( * ItAlias ) ; Reserved . set ( VE :: VM0 ) ; Reserved . set ( VE :: VMP0 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool dominates ( const Waitcnt & Other ) const { return VmCnt <= Other . VmCnt && ExpCnt <= Other . ExpCnt && LgkmCnt <= Other . LgkmCnt ; } </s>

Returns true if B1 occurs before B2 in the trace , or if it is the same block as B2 .


<s> void FixupSFBPass :: buildCopy ( MachineInstr * LoadInst , unsigned NLoadOpcode , int64_t LoadDisp , MachineInstr * StoreInst , unsigned NStoreOpcode , int64_t StoreDisp , unsigned Size , int64_t LMMOffset , int64_t SMMOffset ) { MachineOperand & LoadBase = getBaseOperand ( LoadInst ) ; MachineOperand & StoreBase = getBaseOperand ( StoreInst ) ; MachineBasicBlock * MBB = LoadInst -> getParent ( ) ; MachineMemOperand * LMMO = * LoadInst -> memoperands_begin ( ) ; MachineMemOperand * SMMO = * StoreInst -> memoperands_begin ( ) ; unsigned Reg1 = MRI -> createVirtualRegister ( TII -> getRegClass ( TII -> get ( NLoadOpcode ) , 0 , TRI , * ( MBB -> getParent ( ) ) ) ) ; BuildMI ( * MBB , LoadInst , LoadInst -> getDebugLoc ( ) , TII -> get ( NLoadOpcode ) , Reg1 ) . add ( LoadBase ) . addImm ( 1 ) . addReg ( X86 :: NoRegister ) . addImm ( LoadDisp ) . addReg ( X86 :: NoRegister ) . addMemOperand ( MBB -> getParent ( ) -> getMachineMemOperand ( LMMO , LMMOffset , Size ) ) ; DEBUG ( LoadInst -> getPrevNode ( ) -> dump ( ) ) ; MachineInstr * StInst = StoreInst ; if ( StoreInst -> getPrevNode ( ) == LoadInst ) StInst = LoadInst ; BuildMI ( * MBB , StInst , StInst -> getDebugLoc ( ) , TII -> get ( NStoreOpcode ) ) . add ( StoreBase ) . addImm ( 1 ) . addReg ( X86 :: NoRegister ) . addImm ( StoreDisp ) . addReg ( X86 :: NoRegister ) . addReg ( Reg1 ) . addMemOperand ( MBB -> getParent ( ) -> getMachineMemOperand ( SMMO , SMMOffset , Size ) ) ; DEBUG ( StInst -> getPrevNode ( ) -> dump ( ) ) ; } </s>


<s> static inline bool is_float128_p ( tree t ) { return ( t == float128_type_node || ( t && t == float128t_type_node ) || ( TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 && t == long_double_type_node ) ) ; } </s>

Check whether the type of an argument , T , is compatible with a type ID stored into a struct altivec_builtin_types . Integer types are considered compatible ; otherwise , the language hook lang_hooks.types_compatible_p makes the decision . Also allow long double and _Float128 to be compatible if -mabi=ieeelongdouble .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> const char * X86TargetLowering :: LowerXConstraint ( EVT ConstraintVT ) const { if ( ConstraintVT . isFloatingPoint ( ) ) { if ( Subtarget . hasSSE2 ( ) ) return "Y" ; if ( Subtarget . hasSSE1 ( ) ) return "x" ; } return TargetLowering :: LowerXConstraint ( ConstraintVT ) ; } </s>

Try to replace an X constraint , which matches anything , with another that has more specific requirements based on the type of the corresponding operand .


<s> bool sh_insn_operands_modified_between_p ( rtx_insn * operands_insn , const rtx_insn * from , const rtx_insn * to ) { rtx s = single_set ( operands_insn ) ; if ( s == NULL_RTX ) return true ; subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( i , array , SET_SRC ( s ) , ALL ) if ( * i != NULL && ( ( REG_P ( * i ) || SUBREG_P ( * i ) ) && reg_set_between_p ( * i , from , to ) ) ) return true ; return false ; } </s>

Return true if the register operands of the specified insn are modified between the specified from and to insns ( exclusive of those two ) .


<s> static void visium_function_arg_advance ( cumulative_args_t pcum_v , enum machine_mode mode , const_tree type ATTRIBUTE_UNUSED , bool named ) { int size = ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; int stack_size = 0 ; CUMULATIVE_ARGS * ca = get_cumulative_args ( pcum_v ) ; if ( TARGET_FPU && ( ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && GET_MODE_SIZE ( mode ) <= UNITS_PER_HWFPVALUE ) || ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT && GET_MODE_SIZE ( mode ) <= UNITS_PER_HWFPVALUE * 2 ) ) ) { if ( ca -> frcount + size <= MAX_ARGS_IN_FP_REGISTERS ) ca -> frcount += size ; else { stack_size = size ; ca -> frcount = MAX_ARGS_IN_FP_REGISTERS ; } } else { if ( ca -> grcount + size <= MAX_ARGS_IN_GP_REGISTERS ) ca -> grcount += size ; else { stack_size = size ; ca -> grcount = MAX_ARGS_IN_GP_REGISTERS ; } } if ( named ) ca -> stack_words += stack_size ; } </s>

Update the summarizer variable pointed to by PCUM_V to advance past an argument in the argument list . The values MODE , TYPE and NAMED describe that argument . Once this is done , the variable CUM is suitable for analyzing the _following_ argument with visium_function_arg .


<s> bool PPCCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const { return VRegs . empty ( ) ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


"  Copied r%d to a scalar register r%d for insn %d\n"

Convert all definitions of register REGNO and fix its uses . Scalar copies may be created in case register is used in not convertible insn .


<s> std :: vector < std :: pair < uint64_t , uint64_t >> findPltEntries ( uint64_t PltSectionVA , ArrayRef < uint8_t > PltContents , uint64_t GotPltSectionVA , const Triple & TargetTriple ) const override { std :: vector < std :: pair < uint64_t , uint64_t >> Result ; for ( uint64_t Byte = 0 , End = PltContents . size ( ) ; Byte + 7 < End ; Byte += 4 ) { uint32_t Insn = support :: endian :: read32le ( PltContents . data ( ) + Byte ) ; uint64_t Off = 0 ; if ( Insn == 0xd503245f ) { Off = 4 ; Insn = support :: endian :: read32le ( PltContents . data ( ) + Byte + Off ) ; } if ( ( Insn & 0x9f000000 ) != 0x90000000 ) continue ; Off += 4 ; uint64_t Imm = ( ( ( PltSectionVA + Byte ) >> 12 ) << 12 ) + ( ( ( Insn >> 29 ) & 3 ) << 12 ) + ( ( ( Insn >> 5 ) & 0x3ffff ) << 14 ) ; uint32_t Insn2 = support :: endian :: read32le ( PltContents . data ( ) + Byte + Off ) ; if ( Insn2 >> 22 == 0x3e5 ) { Imm += ( ( Insn2 >> 10 ) & 0xfff ) << 3 ; Result . push_back ( std :: make_pair ( PltSectionVA + Byte , Imm ) ) ; Byte += 4 ; } } return Result ; } </s>

Returns ( PLT virtual address , GOT virtual address ) pairs for PLT entries .


<s> void Z80InstPrinterBase :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << markup ( "<reg:" ) << getRegName ( RegNo ) << markup ( ">" ) ; } </s>


<s> void pdp11_expand_epilogue ( void ) { HOST_WIDE_INT fsize = get_frame_size ( ) ; unsigned regno ; rtx x , reg , via_ac = NULL ; if ( pdp11_saved_regno ( AC4_REGNUM ) || pdp11_saved_regno ( AC5_REGNUM ) ) { for ( regno = AC0_REGNUM ; regno <= AC3_REGNUM ; regno ++ ) if ( pdp11_saved_regno ( regno ) ) { via_ac = gen_rtx_REG ( DFmode , regno ) ; break ; } } if ( ! frame_pointer_needed || crtl -> sp_is_unchanging ) { for ( regno = AC5_REGNUM ; regno >= AC0_REGNUM ; regno -- ) if ( pdp11_saved_regno ( regno ) ) { x = gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ; x = gen_frame_mem ( DFmode , x ) ; reg = gen_rtx_REG ( DFmode , regno ) ; if ( LOAD_FPU_REG_P ( regno ) ) emit_move_insn ( reg , x ) ; else { emit_move_insn ( via_ac , x ) ; emit_move_insn ( reg , via_ac ) ; } } for ( regno = PC_REGNUM ; regno >= R0_REGNUM + 2 ; regno -- ) if ( pdp11_saved_regno ( regno ) && ( regno != HARD_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) ) { x = gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ; x = gen_frame_mem ( Pmode , x ) ; emit_move_insn ( gen_rtx_REG ( Pmode , regno ) , x ) ; } } else { HOST_WIDE_INT ofs = - pdp11_sp_frame_offset ( ) ; for ( regno = AC5_REGNUM ; regno >= AC0_REGNUM ; regno -- ) if ( pdp11_saved_regno ( regno ) ) { x = plus_constant ( Pmode , hard_frame_pointer_rtx , ofs ) ; x = gen_frame_mem ( DFmode , x ) ; reg = gen_rtx_REG ( DFmode , regno ) ; if ( LOAD_FPU_REG_P ( regno ) ) emit_move_insn ( reg , x ) ; else { emit_move_insn ( via_ac , x ) ; emit_move_insn ( reg , via_ac ) ; } ofs += 8 ; } for ( regno = PC_REGNUM ; regno >= R0_REGNUM + 2 ; regno -- ) if ( pdp11_saved_regno ( regno ) && ( regno != HARD_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) ) { x = plus_constant ( Pmode , hard_frame_pointer_rtx , ofs ) ; x = gen_frame_mem ( Pmode , x ) ; emit_move_insn ( gen_rtx_REG ( Pmode , regno ) , x ) ; ofs += 2 ; } } if ( fsize ) { emit_insn ( gen_blockage ( ) ) ; if ( frame_pointer_needed ) { emit_move_insn ( stack_pointer_rtx , hard_frame_pointer_rtx ) ; } else emit_insn ( gen_addhi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( fsize ) ) ) ; } if ( frame_pointer_needed ) { x = gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ; x = gen_frame_mem ( Pmode , x ) ; emit_move_insn ( hard_frame_pointer_rtx , x ) ; } emit_jump_insn ( gen_return ( ) ) ; } </s>

Generate epilogue . This uses the frame pointer to pop the local variables and any alloca data off the stack . If there is no alloca and frame pointer elimination has n't been disabled , there is no frame pointer and the local variables are popped by adjusting the stack pointer instead .


<s> void TGSIMCInstPrinter :: printInst ( const MCInst * mi , raw_ostream & os , StringRef annot , const MCSubtargetInfo & STI ) { printInstruction ( mi , os ) ; printAnnotation ( os , annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


Define the macros that we always expect to have on AArch64 .


"insertBranch must not be told to insert a fallthrough"

"ARC branch conditions have two components!"

Insert branch code into the end of the specified MachineBasicBlock .


<s>
SDValue
PPCTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_PPC
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Arg
=
OutVals
[
i
]
;
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
AExt
:
Arg
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Arg
)
;
break
;
case
CCValAssign
::
ZExt
:
Arg
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Arg
)
;
break
;
case
CCValAssign
::
SExt
:
Arg
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Arg
)
;
break
;
}
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
Arg
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
PPCISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool AArch64PassConfig :: addILPOpts ( ) { if ( EnableCondOpt ) addPass ( createAArch64ConditionOptimizerPass ( ) ) ; if ( EnableCCMP ) addPass ( createAArch64ConditionalCompares ( ) ) ; if ( EnableMCR ) addPass ( & MachineCombinerID ) ; if ( EnableCondBrTuning ) addPass ( createAArch64CondBrTuning ( ) ) ; if ( EnableEarlyIfConversion ) addPass ( & EarlyIfConverterID ) ; if ( EnableStPairSuppress ) addPass ( createAArch64StorePairSuppressPass ( ) ) ; addPass ( createAArch64SIMDInstrOptPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createAArch64StackTaggingPreRAPass ( ) ) ; return true ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .


<s> void WebAssemblyAsmPrinter :: emitLinkage ( const GlobalValue * GV , MCSymbol * Sym ) const { AsmPrinter :: emitLinkage ( GV , Sym ) ; const_cast < WebAssemblyAsmPrinter * > ( this ) -> emitExternalDecls ( * MMI -> getModule ( ) ) ; } </s>

This emits linkage information about GVSym based on GV , if this is supported by the target .


<s> static bool tilegx_legitimate_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { switch ( GET_CODE ( x ) ) { case CONST : case SYMBOL_REF : return ! tilegx_tls_referenced_p ( x ) ; default : return true ; } } </s>

Implement TARGET_LEGITIMATE_CONSTANT_P . This is all constants for which we are willing to load the value into a register via a move pattern . TLS can not be treated as a constant because it can include a function call .


<s> static bool ix86_cannot_force_const_mem ( rtx x ) { return ! legitimate_constant_p ( x ) ; } </s>

Determine if it 's legal to put X into the constant pool . This is not possible for the address of thread-local symbols , which is checked above .


<s>
static
void
nios2_print_operand_address
(
FILE
*
file
,
rtx
op
)
{
switch
(
GET_CODE
(
op
)
)
{
case
CONST
:
case
CONST_INT
:
case
LABEL_REF
:
case
CONST_DOUBLE
:
case
SYMBOL_REF
:
if
(
gprel_constant_p
(
op
)
)
{
fprintf
(
file
,
"%%gprel("
)
;
output_addr_const
(
file
,
op
)
;
fprintf
(
file
,
")(%s)"
,
reg_names
[
GP_REGNO
]
)
;
return
;
}
break
;
case
PLUS
:
{
rtx
op0
=
XEXP
(
op
,
0
)
;
rtx
op1
=
XEXP
(
op
,
1
)
;
if
(
REG_P
(
op0
)
&&
CONSTANT_P
(
op1
)
)
{
output_addr_const
(
file
,
op1
)
;
fprintf
(
file
,
"(%s)"
,
reg_names
[
REGNO
(
op0
)
]
)
;
return
;
}
else
if
(
REG_P
(
op1
)
&&
CONSTANT_P
(
op0
)
)
{
output_addr_const
(
file
,
op0
)
;
fprintf
(
file
,
"(%s)"
,
reg_names
[
REGNO
(
op1
)
]
)
;
return
;
}
}
break
;
case
REG
:
fprintf
(
file
,
"0(%s)"
,
reg_names
[
REGNO
(
op
)
]
)
;
return
;
case
MEM
:
{
rtx
base
=
XEXP
(
op
,
0
)
;
nios2_print_operand_address
(
file
,
base
)
;
return
;
}
default
:
break
;
}
fprintf
(
stderr
,
"Missing way to print address\n"
)
;
debug_rtx
(
op
)
;
gcc_unreachable
(
)
;
}
</s>


<s> void WebAssemblyPassConfig :: addIRPasses ( ) { if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( ) ) ; addPass ( createWebAssemblyLowerGlobalDtors ( ) ) ; addPass ( createWebAssemblyFixFunctionBitcasts ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createWebAssemblyOptimizeReturned ( ) ) ; if ( ! EnableEmException ) { addPass ( createLowerInvokePass ( ) ) ; addPass ( createUnreachableBlockEliminationPass ( ) ) ; } if ( EnableEmException || EnableEmSjLj ) addPass ( createWebAssemblyLowerEmscriptenEHSjLj ( EnableEmException , EnableEmSjLj ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly


"InsertBranch must not be told to insert a fallthrough"

"Z80 branch conditions have one component!"

"Unconditional branch with multiple successors!"


<s>
bool
X86CondBrFolding
::
optimize
(
)
{
bool
Changed
=
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"***** X86CondBr Folding on Function: "
<<
MF
.
getName
(
)
<<
" *****\n"
)
;
MBBInfos
.
resize
(
MF
.
getNumBlockIDs
(
)
)
;
for
(
auto
&
MBB
:
MF
)
MBBInfos
[
MBB
.
getNumber
(
)
]
=
analyzeMBB
(
MBB
)
;
for
(
auto
&
MBB
:
MF
)
{
TargetMBBInfo
*
MBBInfo
=
getMBBInfo
(
&
MBB
)
;
if
(
!
MBBInfo
||
!
MBBInfo
->
CmpBrOnly
)
continue
;
if
(
MBB
.
pred_size
(
)
!=
1
)
continue
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Work on MBB."
<<
MBB
.
getNumber
(
)
<<
" CmpValue: "
<<
MBBInfo
->
CmpValue
<<
"\n"
)
;
SmallVector
<
MachineBasicBlock
*
,
4
>
BranchPath
;
if
(
!
findPath
(
&
MBB
,
BranchPath
)
)
continue
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Found one path (len="
<<
BranchPath
.
size
(
)
<<
"):\n"
)
;
int
Index
=
1
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Target MBB is: "
<<
MBB
<<
"\n"
)
;
for
(
auto
I
=
BranchPath
.
rbegin
(
)
;
I
!=
BranchPath
.
rend
(
)
;
++
I
,
++
Index
)
{
MachineBasicBlock
*
PMBB
=
*
I
;
TargetMBBInfo
*
PMBBInfo
=
getMBBInfo
(
PMBB
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Path MBB ("
<<
Index
<<
" of "
<<
BranchPath
.
size
(
)
<<
") is "
<<
*
PMBB
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"CC="
<<
PMBBInfo
->
BranchCode
<<
"  Val="
<<
PMBBInfo
->
CmpValue
<<
"  CmpBrOnly="
<<
PMBBInfo
->
CmpBrOnly
<<
"\n\n"
)
;
}
optimizeCondBr
(
MBB
,
BranchPath
)
;
Changed
=
true
;
}
NumFixedCondBrs
+=
RemoveList
.
size
(
)
;
for
(
auto
MBBI
:
RemoveList
)
{
while
(
!
MBBI
->
succ_empty
(
)
)
MBBI
->
removeSuccessor
(
MBBI
->
succ_end
(
)
1
)
;
MBBI
->
eraseFromParent
(
)
;
}
return
Changed
;
}
</s>

Apply VPlan-to-VPlan optimizations to Plan , including induction recipe optimizations , dead recipe removal , replicate region optimizations and block merging .

X86
X86
"***** X86CondBr Folding on Function: "
" *****\n"
1
"Work on MBB."
" CmpValue: "
"\n"
4
"Found one path (len="
"):\n"
1
"Target MBB is: "
"\n"
"Path MBB ("
" of "
") is "
"CC="
"  Val="
"  CmpBrOnly="
"\n\n"
1


<s> static inline int and_xor_ior_costs ( rtx x , int code ) { const int cost_scale = ! TARGET_SHMEDIA && GET_MODE_SIZE ( GET_MODE ( x ) ) > UNITS_PER_WORD ? 2 : 1 ; if ( ! CONST_INT_P ( XEXP ( x , 1 ) ) ) return 1 * cost_scale ; int i = INTVAL ( XEXP ( x , 1 ) ) ; if ( TARGET_SHMEDIA ) { if ( satisfies_constraint_I10 ( XEXP ( x , 1 ) ) || satisfies_constraint_J16 ( XEXP ( x , 1 ) ) ) return 1 ; else return 1 + rtx_cost ( XEXP ( x , 1 ) , AND , 1 , ! optimize_size ) ; } if ( ( i == 0xff || i == 0xffff ) && code == AND ) return 1 * cost_scale ; if ( CONST_OK_FOR_K08 ( i ) ) return 2 * cost_scale ; if ( CONST_OK_FOR_I08 ( i ) ) return 2 * cost_scale ; return 3 * cost_scale ; } </s>

Return the cost of an AND/XOR/IOR operation .


<s>
MachineBasicBlock
*
AVRTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
MBB
)
const
{
int
Opc
=
MI
.
getOpcode
(
)
;
switch
(
Opc
)
{
case
AVR
::
Lsl8
:
case
AVR
::
Lsl16
:
case
AVR
::
Lsr8
:
case
AVR
::
Lsr16
:
case
AVR
::
Rol8
:
case
AVR
::
Rol16
:
case
AVR
::
Ror8
:
case
AVR
::
Ror16
:
case
AVR
::
Asr8
:
case
AVR
::
Asr16
:
return
insertShift
(
MI
,
MBB
)
;
case
AVR
::
MULRdRr
:
case
AVR
::
MULSRdRr
:
return
insertMul
(
MI
,
MBB
)
;
}
assert
(
(
Opc
==
AVR
::
Select16
||
Opc
==
AVR
::
Select8
)
&&
"Unexpected instr type to insert"
)
;
const
AVRInstrInfo
&
TII
=
(
const
AVRInstrInfo
&
)
*
MI
.
getParent
(
)
->
getParent
(
)
->
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
dl
=
MI
.
getDebugLoc
(
)
;
MachineFunction
*
MF
=
MBB
->
getParent
(
)
;
const
BasicBlock
*
LLVM_BB
=
MBB
->
getBasicBlock
(
)
;
MachineBasicBlock
*
trueMBB
=
MF
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
falseMBB
=
MF
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineFunction
::
iterator
I
;
for
(
I
=
MF
->
begin
(
)
;
I
!=
MF
->
end
(
)
&&
&
(
*
I
)
!=
MBB
;
++
I
)
;
if
(
I
!=
MF
->
end
(
)
)
++
I
;
MF
->
insert
(
I
,
trueMBB
)
;
MF
->
insert
(
I
,
falseMBB
)
;
trueMBB
->
splice
(
trueMBB
->
begin
(
)
,
MBB
,
std
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
MBB
->
end
(
)
)
;
trueMBB
->
transferSuccessorsAndUpdatePHIs
(
MBB
)
;
AVRCC
::
CondCodes
CC
=
(
AVRCC
::
CondCodes
)
MI
.
getOperand
(
3
)
.
getImm
(
)
;
BuildMI
(
MBB
,
dl
,
TII
.
getBrCond
(
CC
)
)
.
addMBB
(
trueMBB
)
;
BuildMI
(
MBB
,
dl
,
TII
.
get
(
AVR
::
RJMPk
)
)
.
addMBB
(
falseMBB
)
;
MBB
->
addSuccessor
(
falseMBB
)
;
MBB
->
addSuccessor
(
trueMBB
)
;
BuildMI
(
falseMBB
,
dl
,
TII
.
get
(
AVR
::
RJMPk
)
)
.
addMBB
(
trueMBB
)
;
falseMBB
->
addSuccessor
(
trueMBB
)
;
BuildMI
(
*
trueMBB
,
trueMBB
->
begin
(
)
,
dl
,
TII
.
get
(
AVR
::
PHI
)
,
MI
.
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
.
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
MBB
)
.
addReg
(
MI
.
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
falseMBB
)
;
MI
.
eraseFromParent
(
)
;
return
trueMBB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> bool arc_short_comparison_p ( rtx comparison , int offset ) { gcc_assert ( ARC_CC_NC == ARC_CC_HS ) ; gcc_assert ( ARC_CC_C == ARC_CC_LO ) ; switch ( get_arc_condition_code ( comparison ) ) { case ARC_CC_EQ : case ARC_CC_NE : return offset >= - 512 && offset <= 506 ; case ARC_CC_GT : case ARC_CC_LE : case ARC_CC_GE : case ARC_CC_LT : case ARC_CC_HI : case ARC_CC_LS : case ARC_CC_LO : case ARC_CC_HS : return offset >= - 64 && offset <= 58 ; default : return false ; } } </s>

Return true if COMPARISON has a short form that can accomodate OFFSET .


<s> static scalar_int_mode aarch64_sve_element_int_mode ( machine_mode mode ) { poly_uint64 vector_bits = ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL ? BITS_PER_SVE_VECTOR : GET_MODE_BITSIZE ( mode ) ) ; unsigned int elt_bits = vector_element_size ( vector_bits , GET_MODE_NUNITS ( mode ) ) ; return int_mode_for_size ( elt_bits , 0 ) . require ( ) ; } </s>

Return the integer element mode associated with SVE mode MODE .


<s> MCFixupKindInfo const & MOSAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { if ( Kind < FirstTargetFixupKind ) { return MCAsmBackend :: getFixupKindInfo ( Kind ) ; } return MOSFixupKinds :: getFixupKindInfo ( static_cast < MOS :: Fixups > ( Kind ) , this ) ; } </s>

MOS MOS MOSFixupKinds::getFixupKindInfo MOS::Fixups


Return a string to perform a load_multiple operation . operands [ 0 ] is the vector . operands [ 1 ] is the source address . operands [ 2 ] is the first destination register .


<s>
const
char
*
getPassName
(
)
const
{
return
"Hexagon NewValueJump"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void XNCMRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { llvm_unreachable ( 0 ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> void SITargetLowering :: legalizeTargetIndependentNode ( SDNode * Node , SelectionDAG & DAG ) const { SmallVector < SDValue , 8 > Ops ; for ( unsigned i = 0 ; i < Node -> getNumOperands ( ) ; ++ i ) { if ( ! isFrameIndexOp ( Node -> getOperand ( i ) ) ) { Ops . push_back ( Node -> getOperand ( i ) ) ; continue ; } SDLoc DL ( Node ) ; Ops . push_back ( SDValue ( DAG . getMachineNode ( AMDGPU :: S_MOV_B32 , DL , Node -> getOperand ( i ) . getValueType ( ) , Node -> getOperand ( i ) ) , 0 ) ) ; } DAG . UpdateNodeOperands ( Node , Ops ) ; } </s>

Legalize target independent instructions ( e.g .


<s> bool SIFixupVectorISel :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const SIInstrInfo * TII = ST . getInstrInfo ( ) ; const SIRegisterInfo * TRI = ST . getRegisterInfo ( ) ; bool FuncModified = false ; for ( MachineBasicBlock & MBB : MF ) { FuncModified |= fixupGlobalSaddr ( MBB , MF , MRI , ST , TII , TRI ) ; } return FuncModified ; } </s>

runOnMachineFunction - Emit the function body .


<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < 512 > Key ; Key . reserve ( CPU . size ( ) + FS . size ( ) ) ; Key += CPU ; Key += FS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) Key += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; FS = Key . substr ( CPU . size ( ) ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < X86Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; X86GISelActualAccessor * GISel = new X86GISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new X86CallLowering ( * I -> getTargetLowering ( ) ) ) ; GISel -> Legalizer . reset ( new X86LegalizerInfo ( * I , * this ) ) ; auto * RBI = new X86RegisterBankInfo ( * I -> getRegisterInfo ( ) ) ; GISel -> RegBankInfo . reset ( RBI ) ; GISel -> InstSelector . reset ( createX86InstructionSelector ( * this , * I , * RBI ) ) ; I -> setGISelAccessor ( * GISel ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static tree parse_type ( const function_instance & instance , const char * & format ) { int ch = * format ++ ; if ( ch == '_' ) return void_type_node ; if ( ch == 'a' ) { ch = * format ++ ; if ( ch == 'l' ) return build_const_pointer ( instance . memory_scalar_type ( ) ) ; if ( ch == 'p' ) return const_ptr_type_node ; if ( ch == 's' ) return build_pointer_type ( instance . memory_scalar_type ( ) ) ; gcc_unreachable ( ) ; } if ( ch == 'b' ) return instance . base_vector_type ( ) ; if ( ch == 'd' ) return instance . displacement_vector_type ( ) ; if ( ch == 'e' ) { if ( startswith ( format , "pattern" ) ) { format += 7 ; return acle_svpattern ; } if ( startswith ( format , "prfop" ) ) { format += 5 ; return acle_svprfop ; } gcc_unreachable ( ) ; } if ( ch == 's' ) { type_suffix_index suffix = parse_element_type ( instance , format ) ; return scalar_types [ type_suffixes [ suffix ] . vector_type ] ; } if ( ch == 't' ) { type_suffix_index suffix = parse_element_type ( instance , format ) ; vector_type_index vector_type = type_suffixes [ suffix ] . vector_type ; unsigned int num_vectors = instance . vectors_per_tuple ( ) ; return acle_vector_types [ num_vectors - 1 ] [ vector_type ] ; } if ( ch == 'v' ) { type_suffix_index suffix = parse_element_type ( instance , format ) ; return acle_vector_types [ 0 ] [ type_suffixes [ suffix ] . vector_type ] ; } gcc_unreachable ( ) ; } </s>

Read and return a type from FORMAT for function INSTANCE . Advance FORMAT beyond the type string . The format is : _ - void al - array pointer for loads ap - array pointer for prefetches as - array pointer for stores b - base vector type ( from a _ < m0 > base suffix ) d - displacement vector type ( from a _ < m1 > index or _ < m1 > offset suffix ) e < name > - an enum with the given name s < elt > - a scalar type with the given element suffix t < elt > - a vector or tuple type with given element suffix [ * 1 ] v < elt > - a vector with the given element suffix where < elt > has the format described above parse_element_type [ * 1 ] the vectors_per_tuple function indicates whether the type should be a tuple , and if so , how many vectors it should contain .


<s>
void
Thumb1InstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
->
hasSuperClassEq
(
&
ARM
::
tGPRRegClass
)
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
->
hasSuperClassEq
(
&
ARM
::
tGPRRegClass
)
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
,
MachineMemOperand
::
MOLoad
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tLDRspi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .

ARM
ARM::tGPRRegClass
ARM
"Unknown regclass!"
ARM::tGPRRegClass
ARM
ARM::tLDRspi
0
ARMCC::AL


<s> void MINA32FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


<s> unsigned getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { LLT p0 = LLT :: pointer ( 0 , 64 ) ; LLT s64 = LLT :: scalar ( 64 ) ; unsigned SPReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildCopy ( SPReg , AArch64 :: SP ) ; unsigned OffsetReg = MRI . createGenericVirtualRegister ( s64 ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildGEP ( AddrReg , SPReg , OffsetReg ) ; MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> bool ARMAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AFI = MF . getInfo < ARMFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; Subtarget = & MF . getSubtarget < ARMSubtarget > ( ) ; SetupMachineFunction ( MF ) ; const Function & F = MF . getFunction ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; for ( auto * GV : AFI -> getGlobalsPromotedToConstantPool ( ) ) PromotedGlobals . insert ( GV ) ; unsigned OptimizationGoal ; if ( F . hasOptNone ( ) ) OptimizationGoal = 6 ; else if ( F . hasMinSize ( ) ) OptimizationGoal = 4 ; else if ( F . hasOptSize ( ) ) OptimizationGoal = 3 ; else if ( TM . getOptLevel ( ) == CodeGenOpt :: Aggressive ) OptimizationGoal = 2 ; else if ( TM . getOptLevel ( ) > CodeGenOpt :: None ) OptimizationGoal = 1 ; else OptimizationGoal = 5 ; if ( OptimizationGoals == - 1 ) OptimizationGoals = OptimizationGoal ; else if ( OptimizationGoals != ( int ) OptimizationGoal ) OptimizationGoals = 0 ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = F . hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer -> EmitCOFFSymbolType ( Type ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } emitFunctionBody ( ) ; emitXRayTable ( ) ; if ( ! ThumbIndirectPads . empty ( ) ) { OutStreamer -> emitAssemblerFlag ( MCAF_Code16 ) ; emitAlignment ( Align ( 2 ) ) ; for ( std :: pair < unsigned , MCSymbol * > & TIP : ThumbIndirectPads ) { OutStreamer -> emitLabel ( TIP . second ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( ARM :: tBX ) . addReg ( TIP . first ) . addImm ( ARMCC :: AL ) . addReg ( 0 ) ) ; } ThumbIndirectPads . clear ( ) ; } return false ; } </s>


<s> bool useMachineCombiner ( ) const override { return true ; } </s>

Return true when a target supports MachineCombiner .


<s> static enum mips_symbol_type mips_classify_symbolic_expression ( rtx x , enum mips_symbol_context context ) { rtx offset ; split_const ( x , & x , & offset ) ; if ( UNSPEC_ADDRESS_P ( x ) ) return UNSPEC_ADDRESS_TYPE ( x ) ; return mips_classify_symbol ( x , context ) ; } </s>

Classify the base of symbolic expression X , given that X appears in context CONTEXT .


<s> const SystemZTargetMachine & getTargetMachine ( ) const { return static_cast < const SystemZTargetMachine & > ( TM ) ; } </s>

Return the target machine ( if available ) .


<s> unsigned GCNSubtarget :: computeOccupancy ( const Function & F , unsigned LDSSize , unsigned NumSGPRs , unsigned NumVGPRs ) const { unsigned Occupancy = std :: min ( getMaxWavesPerEU ( ) , getOccupancyWithLocalMemSize ( LDSSize , F ) ) ; if ( NumSGPRs ) Occupancy = std :: min ( Occupancy , getOccupancyWithNumSGPRs ( NumSGPRs ) ) ; if ( NumVGPRs ) Occupancy = std :: min ( Occupancy , getOccupancyWithNumVGPRs ( NumVGPRs ) ) ; return Occupancy ; } </s>

Return occupancy for the given function .


<s>
ScheduleHazardRecognizer
::
HazardType
PPCHazardRecognizer970
::
getHazardType
(
SUnit
*
SU
)
{
const
SDNode
*
Node
=
SU
->
getNode
(
)
->
getFlaggedMachineNode
(
)
;
bool
isFirst
,
isSingle
,
isCracked
,
isLoad
,
isStore
;
PPCII
::
PPC970_Unit
InstrType
=
GetInstrType
(
Node
->
getOpcode
(
)
,
isFirst
,
isSingle
,
isCracked
,
isLoad
,
isStore
)
;
if
(
InstrType
==
PPCII
::
PPC970_Pseudo
)
return
NoHazard
;
unsigned
Opcode
=
Node
->
getMachineOpcode
(
)
;
if
(
NumIssued
!=
0
&&
(
isFirst
||
isSingle
)
)
return
Hazard
;
if
(
isCracked
&&
NumIssued
>
2
)
return
Hazard
;
switch
(
InstrType
)
{
default
:
llvm_unreachable
(
"Unknown instruction type!"
)
;
case
PPCII
::
PPC970_FXU
:
case
PPCII
::
PPC970_LSU
:
case
PPCII
::
PPC970_FPU
:
case
PPCII
::
PPC970_VALU
:
case
PPCII
::
PPC970_VPERM
:
if
(
NumIssued
==
4
)
return
Hazard
;
break
;
case
PPCII
::
PPC970_CRU
:
if
(
NumIssued
>=
2
)
return
Hazard
;
break
;
case
PPCII
::
PPC970_BRU
:
break
;
}
if
(
HasCTRSet
&&
(
Opcode
==
PPC
::
BCTRL_Darwin
||
Opcode
==
PPC
::
BCTRL_SVR4
)
)
return
NoopHazard
;
if
(
isLoad
&&
NumStores
)
{
unsigned
LoadSize
;
switch
(
Opcode
)
{
default
:
llvm_unreachable
(
"Unknown load!"
)
;
case
PPC
::
LBZ
:
case
PPC
::
LBZU
:
case
PPC
::
LBZX
:
case
PPC
::
LBZ8
:
case
PPC
::
LBZU8
:
case
PPC
::
LBZX8
:
case
PPC
::
LVEBX
:
LoadSize
=
1
;
break
;
case
PPC
::
LHA
:
case
PPC
::
LHAU
:
case
PPC
::
LHAX
:
case
PPC
::
LHZ
:
case
PPC
::
LHZU
:
case
PPC
::
LHZX
:
case
PPC
::
LVEHX
:
case
PPC
::
LHBRX
:
case
PPC
::
LHA8
:
case
PPC
::
LHAU8
:
case
PPC
::
LHAX8
:
case
PPC
::
LHZ8
:
case
PPC
::
LHZU8
:
case
PPC
::
LHZX8
:
LoadSize
=
2
;
break
;
case
PPC
::
LFS
:
case
PPC
::
LFSU
:
case
PPC
::
LFSX
:
case
PPC
::
LWZ
:
case
PPC
::
LWZU
:
case
PPC
::
LWZX
:
case
PPC
::
LWA
:
case
PPC
::
LWAX
:
case
PPC
::
LVEWX
:
case
PPC
::
LWBRX
:
case
PPC
::
LWZ8
:
case
PPC
::
LWZX8
:
LoadSize
=
4
;
break
;
case
PPC
::
LFD
:
case
PPC
::
LFDU
:
case
PPC
::
LFDX
:
case
PPC
::
LD
:
case
PPC
::
LDU
:
case
PPC
::
LDX
:
LoadSize
=
8
;
break
;
case
PPC
::
LVX
:
case
PPC
::
LVXL
:
LoadSize
=
16
;
break
;
}
if
(
isLoadOfStoredAddress
(
LoadSize
,
Node
->
getOperand
(
0
)
,
Node
->
getOperand
(
1
)
)
)
return
NoopHazard
;
}
return
NoHazard
;
}
</s>

getHazardType - Return the hazard type of emitting this node .


<s> bool isLegalNTStore ( Type * DataType , Align Alignment ) { if ( isa < VectorType > ( DataType ) ) { unsigned NumElements = DataType -> getVectorNumElements ( ) ; unsigned EltSize = DataType -> getVectorElementType ( ) -> getScalarSizeInBits ( ) ; return NumElements > 1 && isPowerOf2_64 ( NumElements ) && EltSize >= 8 && EltSize <= 128 && isPowerOf2_64 ( EltSize ) ; } return BaseT :: isLegalNTStore ( DataType , Alignment ) ; } </s>

Return true if the target supports nontemporal store .


<s> static void mips_save_restore_reg ( machine_mode mode , int regno , HOST_WIDE_INT offset , mips_save_restore_fn fn ) { rtx mem ; mem = gen_frame_mem ( mode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; fn ( gen_rtx_REG ( mode , regno ) , mem ) ; } </s>

Use FN to save or restore register REGNO . MODE is the register 's mode and OFFSET is the offset of its save slot from the current stack pointer .


<s> void ARMDAGToDAGISel :: PreprocessISelDAG ( ) { if ( ! Subtarget -> hasV6T2Ops ( ) ) return ; bool isThumb2 = Subtarget -> isThumb ( ) ; for ( SDNode & N : llvm :: make_early_inc_range ( CurDAG -> allnodes ( ) ) ) { if ( N . getOpcode ( ) != ISD :: ADD ) continue ; SDValue N0 = N . getOperand ( 0 ) ; SDValue N1 = N . getOperand ( 1 ) ; unsigned And_imm = 0 ; if ( ! isOpcWithIntImmediate ( N1 . getNode ( ) , ISD :: AND , And_imm ) ) { if ( isOpcWithIntImmediate ( N0 . getNode ( ) , ISD :: AND , And_imm ) ) std :: swap ( N0 , N1 ) ; } if ( ! And_imm ) continue ; unsigned TZ = countTrailingZeros ( And_imm ) ; if ( TZ != 1 && TZ != 2 ) continue ; And_imm >>= TZ ; if ( And_imm & ( And_imm + 1 ) ) continue ; SDValue Srl = N1 . getOperand ( 0 ) ; unsigned Srl_imm = 0 ; if ( ! isOpcWithIntImmediate ( Srl . getNode ( ) , ISD :: SRL , Srl_imm ) || ( Srl_imm <= 2 ) ) continue ; SDValue CPTmp0 ; SDValue CPTmp1 ; SDValue CPTmp2 ; if ( isThumb2 ) { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) ) continue ; } else { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) || SelectRegShifterOperand ( N0 , CPTmp0 , CPTmp1 , CPTmp2 ) ) continue ; } Srl = CurDAG -> getNode ( ISD :: SRL , SDLoc ( Srl ) , MVT :: i32 , Srl . getOperand ( 0 ) , CurDAG -> getConstant ( Srl_imm + TZ , SDLoc ( Srl ) , MVT :: i32 ) ) ; N1 = CurDAG -> getNode ( ISD :: AND , SDLoc ( N1 ) , MVT :: i32 , Srl , CurDAG -> getConstant ( And_imm , SDLoc ( Srl ) , MVT :: i32 ) ) ; N1 = CurDAG -> getNode ( ISD :: SHL , SDLoc ( N1 ) , MVT :: i32 , N1 , CurDAG -> getConstant ( TZ , SDLoc ( Srl ) , MVT :: i32 ) ) ; CurDAG -> UpdateNodeOperands ( & N , N0 , N1 ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s>
void
arm_declare_function_name
(
FILE
*
stream
,
const
char
*
name
,
tree
decl
)
{
tree
target_parts
=
DECL_FUNCTION_SPECIFIC_TARGET
(
decl
)
;
struct
cl_target_option
*
targ_options
;
if
(
target_parts
)
targ_options
=
TREE_TARGET_OPTION
(
target_parts
)
;
else
targ_options
=
TREE_TARGET_OPTION
(
target_option_current_node
)
;
gcc_assert
(
targ_options
)
;
std
::
string
arch_to_print
;
if
(
targ_options
->
x_arm_arch_string
)
arch_to_print
=
targ_options
->
x_arm_arch_string
;
if
(
arch_to_print
!=
arm_last_printed_arch_string
)
{
std
::
string
arch_name
=
arch_to_print
.
substr
(
0
,
arch_to_print
.
find
(
"+"
)
)
;
asm_fprintf
(
asm_out_file
,
"\t.arch %s\n"
,
arch_name
.
c_str
(
)
)
;
const
arch_option
*
arch
=
arm_parse_arch_option_name
(
all_architectures
,
"-march"
,
targ_options
->
x_arm_arch_string
)
;
auto_sbitmap
opt_bits
(
isa_num_bits
)
;
gcc_assert
(
arch
)
;
if
(
arch
->
common
.
extensions
)
{
for
(
const
struct
cpu_arch_extension
*
opt
=
arch
->
common
.
extensions
;
opt
->
name
!=
;
opt
++
)
{
if
(
!
opt
->
remove
)
{
arm_initialize_isa
(
opt_bits
,
opt
->
isa_bits
)
;
if
(
bitmap_subset_p
(
opt_bits
,
arm_active_target
.
isa
)
&&
!
bitmap_subset_p
(
opt_bits
,
isa_all_fpubits
)
)
asm_fprintf
(
asm_out_file
,
"\t.arch_extension %s\n"
,
opt
->
name
)
;
}
}
}
arm_last_printed_arch_string
=
arch_to_print
;
}
fprintf
(
stream
,
"\t.syntax unified\n"
)
;
if
(
TARGET_THUMB
)
{
if
(
is_called_in_ARM_mode
(
decl
)
||
(
TARGET_THUMB1
&&
!
TARGET_THUMB1_ONLY
&&
cfun
->
is_thunk
)
)
fprintf
(
stream
,
"\t.code 32\n"
)
;
else
if
(
TARGET_THUMB1
)
fprintf
(
stream
,
"\t.code\t16\n\t.thumb_func\n"
)
;
else
fprintf
(
stream
,
"\t.thumb\n\t.thumb_func\n"
)
;
}
else
fprintf
(
stream
,
"\t.arm\n"
)
;
std
::
string
fpu_to_print
=
TARGET_SOFT_FLOAT
"softvfp"
:
arm_identify_fpu_from_isa
(
arm_active_target
.
isa
)
;
if
(
fpu_to_print
!=
arm_last_printed_arch_string
)
{
asm_fprintf
(
asm_out_file
,
"\t.fpu %s\n"
,
fpu_to_print
.
c_str
(
)
)
;
arm_last_printed_fpu_string
=
fpu_to_print
;
}
if
(
TARGET_POKE_FUNCTION_NAME
)
arm_poke_function_name
(
stream
,
(
const
char
*
)
name
)
;
}
</s>

Implement ASM_DECLARE_FUNCTION_NAME . Output the ISA features used by the function fndecl .

arm
0
"+"
"\t.arch %s\n"
"-march"
"\t.arch_extension %s\n"
"\t.syntax unified\n"
"\t.code 32\n"
"\t.code\t16\n\t.thumb_func\n"
"\t.thumb\n\t.thumb_func\n"
"\t.arm\n"
"softvfp"
"\t.fpu %s\n"


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineLoopInfo > ( ) ; AU . addRequired < ProfileSummaryInfoWrapperPass > ( ) ; AU . addRequired < LazyMachineBlockFrequencyInfoPass > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool R600InstrInfo :: fitsReadPortLimitations ( const std :: vector < MachineInstr * > & IG , const DenseMap < unsigned , unsigned > & PV , std :: vector < BankSwizzle > & ValidSwizzle ) const { std :: vector < std :: vector < std :: pair < int , unsigned > > > IGSrcs ; ValidSwizzle . clear ( ) ; for ( unsigned i = 0 , e = IG . size ( ) ; i < e ; ++ i ) { IGSrcs . push_back ( ExtractSrcs ( IG [ i ] , PV ) ) ; unsigned Op = getOperandIdx ( IG [ i ] -> getOpcode ( ) , R600Operands :: BANK_SWIZZLE ) ; ValidSwizzle . push_back ( ( R600InstrInfo :: BankSwizzle ) IG [ i ] -> getOperand ( Op ) . getImm ( ) ) ; } bool Result = recursiveFitsFPLimitation ( IGSrcs , ValidSwizzle ) ; if ( ! Result ) return false ; return true ; } </s>

Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first ( in lexical order ) BankSwizzle affectation starting from the one already provided in the Instruction Group MIs that fits Read Port limitations in BS if available .


<s> bool SITargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return GA -> getAddressSpace ( ) == AMDGPUAS :: GLOBAL_ADDRESS && ! shouldEmitGOTReloc ( GA -> getGlobal ( ) , getTargetMachine ( ) ) ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> static bool riscv_canonicalize_int_order_test ( enum rtx_code * code , rtx * cmp1 , enum machine_mode mode ) { HOST_WIDE_INT plus_one ; if ( riscv_int_order_operand_ok_p ( * code , * cmp1 ) ) return true ; if ( CONST_INT_P ( * cmp1 ) ) switch ( * code ) { case LE : plus_one = trunc_int_for_mode ( UINTVAL ( * cmp1 ) + 1 , mode ) ; if ( INTVAL ( * cmp1 ) < plus_one ) { * code = LT ; * cmp1 = force_reg ( mode , GEN_INT ( plus_one ) ) ; return true ; } break ; case LEU : plus_one = trunc_int_for_mode ( UINTVAL ( * cmp1 ) + 1 , mode ) ; if ( plus_one != 0 ) { * code = LTU ; * cmp1 = force_reg ( mode , GEN_INT ( plus_one ) ) ; return true ; } break ; default : break ; } return false ; } </s>

Return true if * CMP1 ( of mode MODE ) is a valid second operand for integer ordering test * CODE , or if an equivalent combination can be formed by adjusting * CODE and * CMP1 . When returning true , update * CODE and * CMP1 with the chosen code and operand , otherwise leave them alone .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this , LittleEndian ) { initAsmInfo ( ) ; } </s>


<s> static void sparc_emit_probe_stack_range ( HOST_WIDE_INT first , HOST_WIDE_INT size ) { rtx g1 = gen_rtx_REG ( Pmode , 1 ) ; if ( size <= PROBE_INTERVAL ) { emit_move_insn ( g1 , GEN_INT ( first ) ) ; emit_insn ( gen_rtx_SET ( g1 , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , g1 ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , g1 , - size ) ) ; } else if ( size <= 4 * PROBE_INTERVAL ) { HOST_WIDE_INT i ; emit_move_insn ( g1 , GEN_INT ( first + PROBE_INTERVAL ) ) ; emit_insn ( gen_rtx_SET ( g1 , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , g1 ) ) ) ; emit_stack_probe ( g1 ) ; for ( i = 2 * PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) { emit_insn ( gen_rtx_SET ( g1 , plus_constant ( Pmode , g1 , - PROBE_INTERVAL ) ) ) ; emit_stack_probe ( g1 ) ; } emit_stack_probe ( plus_constant ( Pmode , g1 , ( i - PROBE_INTERVAL ) - size ) ) ; } else { HOST_WIDE_INT rounded_size ; rtx g4 = gen_rtx_REG ( Pmode , 4 ) ; emit_move_insn ( g1 , GEN_INT ( first ) ) ; rounded_size = ROUND_DOWN ( size , PROBE_INTERVAL ) ; emit_move_insn ( g4 , GEN_INT ( rounded_size ) ) ; emit_insn ( gen_rtx_SET ( g1 , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , g1 ) ) ) ; emit_insn ( gen_rtx_SET ( g4 , gen_rtx_MINUS ( Pmode , g1 , g4 ) ) ) ; emit_insn ( gen_probe_stack_range ( Pmode , g1 , g1 , g4 ) ) ; if ( size != rounded_size ) emit_stack_probe ( plus_constant ( Pmode , g4 , rounded_size - size ) ) ; } emit_insn ( gen_blockage ( ) ) ; } </s>

Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE , inclusive . These are offsets from the current stack pointer . Note that we do n't use the REG+REG addressing mode for the probes because of the stack bias in 64-bit mode . And it does n't really buy us anything so the advantages of having a single code win here .


Function to check whether the OP is a valid load/store operation . This is a helper function for the predicates : 'nds32_load_multiple_operation ' and 'nds32_store_multiple_operation ' in predicates.md file . The OP is supposed to be a parallel rtx . For each element within this parallel rtx : ( set ( reg ) ( mem addr ) ) is the form for load operation . ( set ( mem addr ) ( reg ) ) is the form for store operation . We have to extract reg and mem of every element and check if the information is valid for multiple load/store operation .


"const void *const __offload_funcs_end[0]\n"

"__attribute__ ((__used__, visibility (\"hidden\"),\n"

"section (\".gnu.offload_funcs\"))) = { };\n\n"

"const void *const __offload_vars_end[0]\n"

"section (\".gnu.offload_vars\"))) = { };\n"

Generates object file with __offload_ * _end symbols for the target library .


<s> const GCNSubtarget * GCNTargetMachine :: getSubtargetImpl ( const Function & F ) const { StringRef GPU = getGPUName ( F ) ; StringRef FS = getFeatureString ( F ) ; SmallString < 128 > SubtargetKey ( GPU ) ; SubtargetKey . append ( FS ) ; auto & I = SubtargetMap [ SubtargetKey ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < GCNSubtarget > ( TargetTriple , GPU , FS , * this ) ; } I -> setScalarizeGlobalBehavior ( ScalarizeGlobal ) ; return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool PatmosSinglePathInfo :: isReachable ( const MachineFunction & MF ) { return MF . getFunction ( ) -> hasFnAttribute ( "sp-reachable" ) ; } </s>

Returns true if instruction is reachable from entry .


<s> bool X86TargetLowering :: isZExtFree ( const Type * Ty1 , const Type * Ty2 ) const { return Ty1 -> isIntegerTy ( 32 ) && Ty2 -> isIntegerTy ( 64 ) && Subtarget -> is64Bit ( ) ; } </s>

Return true if zero-extending the specific node Val to type VT2 is free ( either because it 's implicitly zero-extended such as ARM ldrb / ldrh or because it 's folded such as X86 zero-extending loads ) .


"failed to spill SGPR to VGPR when allocated"

runOnMachineFunction - Emit the function body .


<s> bool MipsNaClRewritePass :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const MipsInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; if ( FlagSfiLoad ) Modified |= SandboxLoadsInBlock ( MBB ) ; if ( FlagSfiStore ) Modified |= SandboxStoresInBlock ( MBB ) ; if ( FlagSfiBranch ) Modified |= SandboxBranchesInBlock ( MBB ) ; if ( FlagSfiStack ) Modified |= SandboxStackChangesInBlock ( MBB ) ; } if ( FlagSfiBranch ) AlignAllJumpTargets ( MF ) ; return Modified ; } </s>


<s> ScheduleHazardRecognizer :: HazardType GCNHazardRecognizer :: getHazardType ( SUnit * SU , int Stalls ) { MachineInstr * MI = SU -> getInstr ( ) ; if ( MI -> isBundle ( ) ) return NoHazard ; if ( SIInstrInfo :: isSMRD ( * MI ) && checkSMRDHazards ( MI ) > 0 ) return NoopHazard ; if ( ( SIInstrInfo :: isVMEM ( * MI ) || SIInstrInfo :: isFLAT ( * MI ) ) && checkVMEMHazards ( MI ) > 0 ) return NoopHazard ; if ( ST . hasNSAtoVMEMBug ( ) && checkNSAtoVMEMHazard ( MI ) > 0 ) return NoopHazard ; if ( ST . hasNoDataDepHazard ( ) ) return NoHazard ; if ( SIInstrInfo :: isVALU ( * MI ) && checkVALUHazards ( MI ) > 0 ) return NoopHazard ; if ( SIInstrInfo :: isDPP ( * MI ) && checkDPPHazards ( MI ) > 0 ) return NoopHazard ; if ( isDivFMas ( MI -> getOpcode ( ) ) && checkDivFMasHazards ( MI ) > 0 ) return NoopHazard ; if ( isRWLane ( MI -> getOpcode ( ) ) && checkRWLaneHazards ( MI ) > 0 ) return NoopHazard ; if ( isSGetReg ( MI -> getOpcode ( ) ) && checkGetRegHazards ( MI ) > 0 ) return NoopHazard ; if ( isSSetReg ( MI -> getOpcode ( ) ) && checkSetRegHazards ( MI ) > 0 ) return NoopHazard ; if ( isRFE ( MI -> getOpcode ( ) ) && checkRFEHazards ( MI ) > 0 ) return NoopHazard ; if ( ST . hasReadM0MovRelInterpHazard ( ) && ( TII . isVINTRP ( * MI ) || isSMovRel ( MI -> getOpcode ( ) ) ) && checkReadM0Hazards ( MI ) > 0 ) return NoopHazard ; if ( ST . hasReadM0SendMsgHazard ( ) && isSendMsgTraceDataOrGDS ( TII , * MI ) && checkReadM0Hazards ( MI ) > 0 ) return NoopHazard ; if ( MI -> isInlineAsm ( ) && checkInlineAsmHazards ( MI ) > 0 ) return NoopHazard ; if ( checkAnyInstHazards ( MI ) > 0 ) return NoopHazard ; return NoHazard ; } </s>


<s> const char * Cpu0TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case Cpu0ISD :: JmpLink : return "Cpu0ISD::JmpLink" ; case Cpu0ISD :: Hi : return "Cpu0ISD::Hi" ; case Cpu0ISD :: Lo : return "Cpu0ISD::Lo" ; case Cpu0ISD :: GPRel : return "Cpu0ISD::GPRel" ; case Cpu0ISD :: Ret : return "Cpu0ISD::Ret" ; case Cpu0ISD :: RetValue : return "Cpu0ISD::RetValue" ; case Cpu0ISD :: DivRem : return "Cpu0ISD::DivRem" ; case Cpu0ISD :: DivRemU : return "Cpu0ISD::DivRemU" ; case Cpu0ISD :: Wrapper : return "Cpu0ISD::Wrapper" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static void ia64_file_start ( void ) { default_file_start ( ) ; emit_safe_across_calls ( ) ; } </s>


<s> const uint32_t * MipsRegisterInfo :: getCallPreservedMask ( CallingConv :: ID ) const { if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_RegMask ; if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_RegMask ; if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_RegMask ; if ( Subtarget . isFP64bit ( ) ) return CSR_O32_FP64_RegMask ; if ( Subtarget . isFPXX ( ) ) return CSR_O32_FPXX_RegMask ; return CSR_O32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static bool sparc_fixed_condition_code_regs ( unsigned int * p1 , unsigned int * p2 ) { * p1 = SPARC_ICC_REG ; * p2 = SPARC_FCC_REG ; return true ; } </s>


<s>
static
bool
rename_single_chain
(
du_head_p
head
,
HARD_REG_SET
*
unavailable
)
{
int
best_new_reg
;
int
n_uses
=
0
;
struct
du_chain
*
tmp
;
int
reg
=
head
->
regno
;
enum
reg_class
super_class
=
NO_REGS
;
if
(
head
->
cannot_rename
)
return
false
;
if
(
fixed_regs
[
reg
]
||
global_regs
[
reg
]
||
(
frame_pointer_needed
&&
reg
==
HARD_FRAME_POINTER_REGNUM
)
)
return
false
;
for
(
tmp
=
head
->
first
;
tmp
;
tmp
=
tmp
->
next_use
)
{
if
(
DEBUG_INSN_P
(
tmp
->
insn
)
)
continue
;
n_uses
++
;
*
unavailable
|=
~
reg_class_contents
[
tmp
->
cl
]
;
super_class
=
reg_class_superunion
[
(
int
)
super_class
]
[
(
int
)
tmp
->
cl
]
;
}
if
(
n_uses
<
1
)
return
false
;
best_new_reg
=
find_rename_reg
(
head
,
super_class
,
unavailable
,
reg
,
false
)
;
if
(
dump_file
)
{
fprintf
(
dump_file
,
"Register %s in insn %d"
,
reg_names
[
reg
]
,
INSN_UID
(
head
->
first
->
insn
)
)
;
if
(
head
->
call_abis
)
fprintf
(
dump_file
,
" crosses a call"
)
;
}
if
(
best_new_reg
==
reg
)
{
if
(
dump_file
)
fprintf
(
dump_file
,
"; no available better choice\n"
)
;
return
false
;
}
if
(
regrename_do_replace
(
head
,
best_new_reg
)
)
{
if
(
dump_file
)
fprintf
(
dump_file
,
", renamed as %s\n"
,
reg_names
[
best_new_reg
]
)
;
df_set_regs_ever_live
(
best_new_reg
,
true
)
;
}
else
{
if
(
dump_file
)
fprintf
(
dump_file
,
", renaming as %s failed\n"
,
reg_names
[
best_new_reg
]
)
;
return
false
;
}
return
true
;
}
</s>

Rename the register HEAD- > regno in all the insns in the chain HEAD to any register not in the set UNAVAILABLE . Adapted from rename_chains in regrename.c .


<s>
bool
AArch64InstrInfo
::
isGPRCopy
(
const
MachineInstr
&
MI
)
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
TargetOpcode
::
COPY
:
{
unsigned
DstReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
return
(
AArch64
::
GPR32RegClass
.
contains
(
DstReg
)
||
AArch64
::
GPR64RegClass
.
contains
(
DstReg
)
)
;
}
case
AArch64
::
ORRXrs
:
if
(
MI
.
getOperand
(
1
)
.
getReg
(
)
==
AArch64
::
XZR
)
{
assert
(
MI
.
getDesc
(
)
.
getNumOperands
(
)
==
4
&&
MI
.
getOperand
(
3
)
.
getImm
(
)
==
0
&&
"invalid ORRrs operands"
)
;
return
true
;
}
break
;
case
AArch64
::
ADDXri
:
if
(
MI
.
getOperand
(
2
)
.
getImm
(
)
==
0
)
{
assert
(
MI
.
getDesc
(
)
.
getNumOperands
(
)
==
4
&&
MI
.
getOperand
(
3
)
.
getImm
(
)
==
0
&&
"invalid ADDXri operands"
)
;
return
true
;
}
break
;
}
return
false
;
}
</s>

Does this instruction rename a GPR without modifying bits ?


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasV8_1aOps ( false ) , HasFPARMv8 ( false ) , HasNEON ( false ) , HasCrypto ( false ) , HasCRC ( false ) , HasPerfMon ( false ) , HasZeroCycleRegMove ( false ) , HasZeroCycleZeroing ( false ) , StrictAlign ( false ) , ReserveX18 ( false ) , IsLittle ( LittleEndian ) , CPUString ( CPU ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS ) ) , TSInfo ( ) , TLInfo ( TM , * this ) { } </s>

This constructor initializes the data members to match that of the specified triple .


<s> const char * getPassName ( ) const override { return FIXUPBW_DESC ; } </s>

getPassName - Return a nice clean name for a pass .


<s>
void
AMDGPUAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
)
const
{
switch
(
(
unsigned
)
Fixup
.
getKind
(
)
)
{
case
AMDGPU
::
fixup_si_sopp_br
:
{
int64_t
BrImm
=
(
(
int64_t
)
Value
4
)
/
4
;
if
(
!
isInt
<
16
>
(
BrImm
)
)
report_fatal_error
(
"branch size exceeds simm16"
)
;
uint16_t
*
Dst
=
(
uint16_t
*
)
(
Data
+
Fixup
.
getOffset
(
)
)
;
*
Dst
=
BrImm
;
break
;
}
case
AMDGPU
::
fixup_si_rodata
:
{
uint32_t
*
Dst
=
(
uint32_t
*
)
(
Data
+
Fixup
.
getOffset
(
)
)
;
*
Dst
=
Value
+
4
;
break
;
}
default
:
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static unsigned int rs6000_parm_start ( machine_mode mode , const_tree type , unsigned int nwords ) { unsigned int align ; align = rs6000_function_arg_boundary ( mode , type ) / PARM_BOUNDARY - 1 ; return nwords + ( - ( rs6000_parm_offset ( ) + nwords ) & align ) ; } </s>

For a function parm of MODE and TYPE , return the starting word in the parameter area . NWORDS of the parameter area are already used .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static unsigned int aarch64_function_arg_alignment ( machine_mode mode , const_tree type , bool * abi_break ) { * abi_break = false ; if ( ! type ) return GET_MODE_ALIGNMENT ( mode ) ; if ( integer_zerop ( TYPE_SIZE ( type ) ) ) return 0 ; gcc_assert ( TYPE_MODE ( type ) == mode ) ; if ( ! AGGREGATE_TYPE_P ( type ) ) return TYPE_ALIGN ( TYPE_MAIN_VARIANT ( type ) ) ; if ( TREE_CODE ( type ) == ARRAY_TYPE ) return TYPE_ALIGN ( TREE_TYPE ( type ) ) ; unsigned int alignment = 0 ; unsigned int bitfield_alignment = 0 ; for ( tree field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) if ( TREE_CODE ( field ) == FIELD_DECL ) { alignment = std :: max ( alignment , DECL_ALIGN ( field ) ) ; if ( DECL_BIT_FIELD_TYPE ( field ) ) bitfield_alignment = std :: max ( bitfield_alignment , TYPE_ALIGN ( DECL_BIT_FIELD_TYPE ( field ) ) ) ; } if ( bitfield_alignment > alignment ) { * abi_break = true ; return bitfield_alignment ; } return alignment ; } </s>

Given MODE and TYPE of a function argument , return the alignment in bits . The idea is to suppress any stronger alignment requested by the user and opt for the natural alignment ( specified in AAPCS64 \S 4.1 ) . This is a helper function for local use only .


"Function has local memory argument.  Promoting to "

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> MVT getVectorIdxTy ( const DataLayout & DL ) const override { return MVT :: getIntegerVT ( 32 ) ; } </s>

Returns the type to be used for the index operand of : ISD : :INSERT_VECTOR_ELT , ISD : :EXTRACT_VECTOR_ELT , ISD : :INSERT_SUBVECTOR , and ISD : :EXTRACT_SUBVECTOR .


<s>
void
dump
(
)
{
dbgs
(
)
<<
"X86ISelAddressMode "
<<
this
<<
'\n'
;
dbgs
(
)
<<
"Base_Reg "
;
if
(
Base_Reg
.
getNode
(
)
)
Base_Reg
.
getNode
(
)
->
dump
(
)
;
else
dbgs
(
)
<<
"nul\n"
;
if
(
BaseType
==
FrameIndexBase
)
dbgs
(
)
<<
" Base.FrameIndex "
<<
Base_FrameIndex
<<
'\n'
;
dbgs
(
)
<<
" Scale "
<<
Scale
<<
'\n'
<<
"IndexReg "
;
if
(
IndexReg
.
getNode
(
)
)
IndexReg
.
getNode
(
)
->
dump
(
)
;
else
dbgs
(
)
<<
"nul\n"
;
dbgs
(
)
<<
" Disp "
<<
Disp
<<
'\n'
<<
"GV "
;
if
(
GV
)
GV
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" CP "
;
if
(
CP
)
CP
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
'\n'
<<
"ES "
;
if
(
ES
)
dbgs
(
)
<<
ES
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" MCSym "
;
if
(
MCSym
)
dbgs
(
)
<<
MCSym
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" JT"
<<
JT
<<
" Align"
<<
Align
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

X86
"X86ISelAddressMode "
"Base_Reg "
"nul\n"
" Base.FrameIndex "
" Scale "
"IndexReg "
"nul\n"
" Disp "
"GV "
"nul"
" CP "
"nul"
"ES "
"nul"
" MCSym "
"nul"
" JT"
" Align"


<s> virtual MVT getShiftAmountTy ( EVT LHSTy ) const { return MVT :: i32 ; } </s>

Returns the type for the shift amount of a shift opcode .


<s> void OutgoingValueHandler :: assignValueToReg ( unsigned ValVReg , const CCValAssign & VA ) { unsigned PhysReg = VA . getLocReg ( ) ; unsigned ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildCopy ( PhysReg , ExtReg ) ; MIB . addUse ( PhysReg , RegState :: Implicit ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> void FISCAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static unsigned int loongarch_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( FCC_REG_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + 3 ) / 4 ; if ( FP_REG_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + UNITS_PER_FPREG - 1 ) / UNITS_PER_FPREG ; return ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } </s>


"rs6000_secondary_memory_needed, return: %s, from_class = %s, "

Debug version of rs6000_secondary_memory_needed .


<s> SDValue PIC16TargetLowering :: LowerFormalArguments ( SDValue Chain , unsigned CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { unsigned NumArgVals = Ins . size ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function * F = MF . getFunction ( ) ; std :: string FuncName = F -> getName ( ) ; ResetTmpOffsetMap ( ) ; InitReservedFrameCount ( F ) ; const char * tmpName = createESName ( PAN :: getArgsLabel ( FuncName ) ) ; SDValue ES = DAG . getTargetExternalSymbol ( tmpName , MVT :: i8 ) ; SDVTList VTs = DAG . getVTList ( MVT :: i8 , MVT :: Other ) ; SDValue BS = DAG . getConstant ( 1 , MVT :: i8 ) ; for ( unsigned i = 0 ; i < NumArgVals ; ++ i ) { SDValue Offset = DAG . getConstant ( i , MVT :: i8 ) ; SDValue PICLoad = DAG . getNode ( PIC16ISD :: PIC16LdArg , dl , VTs , Chain , ES , BS , Offset ) ; Chain = getChain ( PICLoad ) ; InVals . push_back ( PICLoad ) ; } return Chain ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> static unsigned findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const TargetRegisterInfo * TRI , bool Is64Bit ) { const MachineFunction * MF = MBB . getParent ( ) ; const Function * F = MF -> getFunction ( ) ; if ( ! F || MF -> getMMI ( ) . callsEHReturn ( ) ) return 0 ; static const uint16_t CallerSavedRegs32Bit [ ] = { X86 :: EAX , X86 :: EDX , X86 :: ECX , 0 } ; static const uint16_t CallerSavedRegs64Bit [ ] = { X86 :: RAX , X86 :: RDX , X86 :: RCX , X86 :: RSI , X86 :: RDI , X86 :: R8 , X86 :: R9 , X86 :: R10 , X86 :: R11 , 0 } ; unsigned Opc = MBBI -> getOpcode ( ) ; switch ( Opc ) { default : return 0 ; case X86 :: RETL : case X86 :: RETQ : case X86 :: RETIL : case X86 :: RETIQ : case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: TCRETURNmi64 : case X86 :: EH_RETURN : case X86 :: EH_RETURN64 : { SmallSet < uint16_t , 8 > Uses ; for ( unsigned i = 0 , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } const uint16_t * CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit ; for ( ; * CS ; ++ CS ) if ( ! Uses . count ( * CS ) ) return * CS ; } } return 0 ; } </s>

findDeadCallerSavedReg - Return a caller-saved register that is n't live when it reaches the `` return '' instruction .


<s>
void
SIMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
verifyInstructionPredicates
(
MI
,
computeAvailableFeatures
(
STI
.
getFeatureBits
(
)
)
)
;
uint64_t
Encoding
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
unsigned
bytes
=
Desc
.
getSize
(
)
;
for
(
unsigned
i
=
0
;
i
<
bytes
;
i
++
)
{
OS
.
write
(
(
uint8_t
)
(
(
Encoding
>>
(
8
*
i
)
)
&
0xff
)
)
;
}
if
(
AMDGPU
::
isGFX10Plus
(
STI
)
&&
Desc
.
TSFlags
&
SIInstrFlags
::
MIMG
)
{
int
vaddr0
=
AMDGPU
::
getNamedOperandIdx
(
MI
.
getOpcode
(
)
,
AMDGPU
::
OpName
::
vaddr0
)
;
int
srsrc
=
AMDGPU
::
getNamedOperandIdx
(
MI
.
getOpcode
(
)
,
AMDGPU
::
OpName
::
srsrc
)
;
assert
(
vaddr0
>=
0
&&
srsrc
>
vaddr0
)
;
unsigned
NumExtraAddrs
=
srsrc
vaddr0
1
;
unsigned
NumPadding
=
(
NumExtraAddrs
)
&
3
;
for
(
unsigned
i
=
0
;
i
<
NumExtraAddrs
;
++
i
)
OS
.
write
(
(
uint8_t
)
getMachineOpValue
(
MI
,
MI
.
getOperand
(
vaddr0
+
1
+
i
)
,
Fixups
,
STI
)
)
;
for
(
unsigned
i
=
0
;
i
<
NumPadding
;
++
i
)
OS
.
write
(
0
)
;
}
if
(
(
bytes
>
8
&&
STI
.
getFeatureBits
(
)
[
AMDGPU
::
FeatureVOP3Literal
]
)
||
(
bytes
>
4
&&
!
STI
.
getFeatureBits
(
)
[
AMDGPU
::
FeatureVOP3Literal
]
)
)
return
;
for
(
unsigned
i
=
0
,
e
=
Desc
.
getNumOperands
(
)
;
i
<
e
;
++
i
)
{
if
(
!
AMDGPU
::
isSISrcOperand
(
Desc
,
i
)
)
continue
;
const
MCOperand
&
Op
=
MI
.
getOperand
(
i
)
;
if
(
getLitEncoding
(
Op
,
Desc
.
OpInfo
[
i
]
,
STI
)
!=
255
)
continue
;
int64_t
Imm
=
0
;
if
(
Op
.
isImm
(
)
)
Imm
=
Op
.
getImm
(
)
;
else
if
(
Op
.
isExpr
(
)
)
{
if
(
const
auto
*
C
=
dyn_cast
<
MCConstantExpr
>
(
Op
.
getExpr
(
)
)
)
Imm
=
C
->
getValue
(
)
;
}
else
if
(
!
Op
.
isExpr
(
)
)
llvm_unreachable
(
"Must be immediate or expr"
)
;
for
(
unsigned
j
=
0
;
j
<
4
;
j
++
)
{
OS
.
write
(
(
uint8_t
)
(
(
Imm
>>
(
8
*
j
)
)
&
0xff
)
)
;
}
break
;
}
}
</s>

Encode the given Inst to bytes and append to CB .


<s> void Tile64InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { BuildMI ( MBB , I , DL , get ( T64 :: MOVE ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } </s>


"could not find corresponding %pcrel_hi"

Hook to check if a relocation is needed for some target specific reason .


<s>
VE
::
Fixups
VEMCExpr
::
getFixupKind
(
VEMCExpr
::
VariantKind
Kind
)
{
switch
(
Kind
)
{
default
:
llvm_unreachable
(
"Unhandled VEMCExpr::VariantKind"
)
;
case
VK_VE_HI32
:
return
VE
::
fixup_ve_hi32
;
case
VK_VE_LO32
:
return
VE
::
fixup_ve_lo32
;
case
VK_VE_PC_HI32
:
return
VE
::
fixup_ve_pc_hi32
;
case
VK_VE_PC_LO32
:
return
VE
::
fixup_ve_pc_lo32
;
case
VK_VE_GOT_HI32
:
return
VE
::
fixup_ve_got_hi32
;
case
VK_VE_GOT_LO32
:
return
VE
::
fixup_ve_got_lo32
;
case
VK_VE_GOTOFF_HI32
:
return
VE
::
fixup_ve_gotoff_hi32
;
case
VK_VE_GOTOFF_LO32
:
return
VE
::
fixup_ve_gotoff_lo32
;
case
VK_VE_PLT_HI32
:
return
VE
::
fixup_ve_plt_hi32
;
case
VK_VE_PLT_LO32
:
return
VE
::
fixup_ve_plt_lo32
;
case
VK_VE_TLS_GD_HI32
:
return
VE
::
fixup_ve_tls_gd_hi32
;
case
VK_VE_TLS_GD_LO32
:
return
VE
::
fixup_ve_tls_gd_lo32
;
}
}
</s>

getFixupKind - Get the fixup kind of this expression .


<s> void HexagonMCELFStreamer :: EmitInstruction ( const MCInst & MCB , const MCSubtargetInfo & STI ) { assert ( MCB . getOpcode ( ) == Hexagon :: BUNDLE ) ; assert ( HexagonMCInstrInfo :: bundleSize ( MCB ) <= HEXAGON_PACKET_SIZE ) ; assert ( HexagonMCInstrInfo :: bundleSize ( MCB ) > 0 ) ; bool Extended = false ; for ( auto & I : HexagonMCInstrInfo :: bundleInstructions ( MCB ) ) { MCInst * MCI = const_cast < MCInst * > ( I . getInst ( ) ) ; if ( Extended ) { if ( HexagonMCInstrInfo :: isDuplex ( * MCII , * MCI ) ) { MCInst * SubInst = const_cast < MCInst * > ( MCI -> getOperand ( 1 ) . getInst ( ) ) ; HexagonMCInstrInfo :: clampExtended ( * MCII , getContext ( ) , * SubInst ) ; } else { HexagonMCInstrInfo :: clampExtended ( * MCII , getContext ( ) , * MCI ) ; } Extended = false ; } else { Extended = HexagonMCInstrInfo :: isImmext ( * MCI ) ; } } for ( auto const & I : HexagonMCInstrInfo :: bundleInstructions ( MCB ) ) { MCInst * MCI = const_cast < MCInst * > ( I . getInst ( ) ) ; EmitSymbol ( * MCI ) ; } MCObjectStreamer :: EmitInstruction ( MCB , STI ) ; } </s>

Hexagon Hexagon Hexagon::BUNDLE Hexagon Hexagon 0 Hexagon Hexagon 1 Hexagon Hexagon Hexagon Hexagon


<s> void d30v_expand_epilogue ( ) { rtx sp = stack_pointer_rtx ; d30v_stack_t * info = d30v_stack_info ( ) ; int i ; rtx mem_di = NULL_RTX ; rtx mem_si = NULL_RTX ; rtx post_inc ; int extra_stack ; emit_insn ( gen_blockage ( ) ) ; if ( frame_pointer_needed ) emit_move_insn ( sp , frame_pointer_rtx ) ; if ( info -> save_offset ) emit_insn ( gen_addsi3 ( sp , sp , GEN_INT ( info -> save_offset ) ) ) ; post_inc = gen_rtx ( POST_INC , Pmode , sp ) ; mem_di = gen_rtx ( MEM , DImode , post_inc ) ; mem_si = gen_rtx ( MEM , SImode , post_inc ) ; for ( i = ACCUM_FIRST ; i <= ACCUM_LAST ; i ++ ) if ( info -> save_p [ i ] ) { rtx acc_tmp = gen_rtx ( REG , DImode , GPR_ATMP_FIRST ) ; emit_insn ( gen_movdi ( acc_tmp , mem_di ) ) ; emit_insn ( gen_movdi ( gen_rtx ( REG , DImode , i ) , acc_tmp ) ) ; } for ( i = GPR_FIRST ; i <= GPR_LAST ; i += 2 ) if ( info -> save_p [ i ] == 2 ) emit_insn ( gen_movdi ( gen_rtx ( REG , DImode , i ) , mem_di ) ) ; extra_stack = 0 ; for ( i = GPR_FIRST ; i <= GPR_LAST ; i ++ ) if ( info -> save_p [ i ] == 1 ) { if ( cfun -> machine -> eh_epilogue_sp_ofs && i == GPR_LINK ) extra_stack = 4 ; else { if ( extra_stack ) { emit_insn ( gen_addsi3 ( sp , sp , GEN_INT ( extra_stack ) ) ) ; extra_stack = 0 ; } emit_insn ( gen_movsi ( gen_rtx ( REG , SImode , i ) , mem_si ) ) ; } } if ( ( info -> memrefs_1word & 1 ) != 0 ) extra_stack += UNITS_PER_WORD ; extra_stack += current_function_pretend_args_size + info -> varargs_size ; if ( extra_stack ) { if ( cfun -> machine -> eh_epilogue_sp_ofs ) emit_insn ( gen_addsi3 ( cfun -> machine -> eh_epilogue_sp_ofs , cfun -> machine -> eh_epilogue_sp_ofs , GEN_INT ( extra_stack ) ) ) ; else emit_insn ( gen_addsi3 ( sp , sp , GEN_INT ( extra_stack ) ) ) ; } if ( cfun -> machine -> eh_epilogue_sp_ofs ) emit_insn ( gen_addsi3 ( sp , sp , cfun -> machine -> eh_epilogue_sp_ofs ) ) ; emit_jump_insn ( gen_rtx_RETURN ( VOIDmode ) ) ; } </s>

Called after register allocation to add any instructions needed for the epilogue . Using an epilogue insn is favored compared to putting all of the instructions in output_function_prologue ( ) , since it allows the scheduler to intermix instructions with the saves of the caller saved registers . In some cases , it might be necessary to emit a barrier instruction as the last insn to prevent such scheduling .


<s> bool X86PassConfig :: addPreISel ( ) { const Triple & TT = TM -> getTargetTriple ( ) ; if ( TT . isOSWindows ( ) && TT . getArch ( ) == Triple :: x86 ) addPass ( createX86WinEHStatePass ( ) ) ; return true ; } </s>


<s> void Z80oldTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; this -> TM = & static_cast < const Z80oldTargetMachine & > ( TM ) ; } </s>

This method must be called before any actual lowering is done .


<s> bool ARMAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AFI = MF . getInfo < ARMFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = MF . getFunction ( ) -> hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer . BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer . EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer . EmitCOFFSymbolType ( Type ) ; OutStreamer . EndCOFFSymbolDef ( ) ; } EmitFunctionHeader ( ) ; EmitFunctionBody ( ) ; if ( ! ThumbIndirectPads . empty ( ) ) { OutStreamer . EmitAssemblerFlag ( MCAF_Code16 ) ; EmitAlignment ( 1 ) ; for ( unsigned i = 0 , e = ThumbIndirectPads . size ( ) ; i < e ; i ++ ) { OutStreamer . EmitLabel ( ThumbIndirectPads [ i ] . second ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( ARM :: tBX ) . addReg ( ThumbIndirectPads [ i ] . first ) . addImm ( ARMCC :: AL ) . addReg ( 0 ) ) ; } ThumbIndirectPads . clear ( ) ; } return false ; } </s>

runOnMachineFunction - Emit the function body .


<s>
static
X86Operand
*
CreateMem
(
unsigned
SegReg
,
const
MCExpr
*
Disp
,
unsigned
BaseReg
,
unsigned
IndexReg
,
unsigned
Scale
,
SMLoc
StartLoc
,
SMLoc
EndLoc
,
unsigned
Size
=
0
,
StringRef
SymName
=
StringRef
(
)
,
void
*
OpDecl
=
0
)
{
assert
(
(
SegReg
||
BaseReg
||
IndexReg
)
&&
"Invalid memory operand!"
)
;
assert
(
(
(
Scale
==
1
||
Scale
==
2
||
Scale
==
4
||
Scale
==
8
)
)
&&
"Invalid scale!"
)
;
X86Operand
*
Res
=
new
X86Operand
(
Memory
,
StartLoc
,
EndLoc
)
;
Res
->
Mem
.
SegReg
=
SegReg
;
Res
->
Mem
.
Disp
=
Disp
;
Res
->
Mem
.
BaseReg
=
BaseReg
;
Res
->
Mem
.
IndexReg
=
IndexReg
;
Res
->
Mem
.
Scale
=
Scale
;
Res
->
Mem
.
Size
=
Size
;
Res
->
SymName
=
SymName
;
Res
->
OpDecl
=
OpDecl
;
Res
->
AddressOf
=
false
;
return
Res
;
}
</s>


<s> rtx aarch64_endian_lane_rtx ( machine_mode mode , unsigned int n ) { return gen_int_mode ( ENDIAN_LANE_N ( GET_MODE_NUNITS ( mode ) , n ) , SImode ) ; } </s>

Peform endian correction on lane number N , which indexes a vector of mode MODE , and return the result as an SImode rtx .


<s> bool X86InstrInfo :: isCopyInstr ( const MachineInstr & MI , MachineOperand & Src , MachineOperand & Dest ) const { if ( MI . isMoveReg ( ) ) { Dest = MI . getOperand ( 0 ) ; Src = MI . getOperand ( 1 ) ; return true ; } return false ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


<s>
unsigned
SparcRegisterInfo
::
getFrameRegister
(
MachineFunction
&
MF
)
const
{
llvm_unreachable
(
"What is the frame register"
)
;
return
SP
::
G1
;
}
</s>

Sparc
Sparc
"What is the frame register"
SP::G1


<s> MCSection * getExplicitSectionGlobal ( const GlobalObject * GO , SectionKind Kind , const TargetMachine & TM ) const override { return DataSection ; } </s>

Targets should implement this method to assign a section to globals with an explicit section specfied .


<s> bool X86RegisterInfo :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> bool HexagonInstrInfo :: isPostIncrement ( const MachineInstr * MI ) const { return getAddrMode ( MI ) == HexagonII :: PostInc ; } </s>

Return true for post-incremented instructions .


<s> class LLVM_LIBRARY_VISIBILITY SystemZMCInstLower { Mangler * Mang ; MCContext & Ctx ; SystemZAsmPrinter & AsmPrinter ; public : SystemZMCInstLower ( Mangler * mang , MCContext & ctx , SystemZAsmPrinter & asmPrinter ) ; void lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCOperand lowerOperand ( const MachineOperand & MO ) const ; const MCExpr * getExpr ( const MachineOperand & MO , MCSymbolRefExpr :: VariantKind Kind ) const ; } </s>

Implementation of the SCEVPredicate interface .


<s>
SDValue
XCoreTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
BR_JT
:
return
LowerBR_JT
(
Op
,
DAG
)
;
case
ISD
::
LOAD
:
return
LowerLOAD
(
Op
,
DAG
)
;
case
ISD
::
STORE
:
return
LowerSTORE
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
VAARG
:
return
LowerVAARG
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
SMUL_LOHI
:
return
LowerSMUL_LOHI
(
Op
,
DAG
)
;
case
ISD
::
UMUL_LOHI
:
return
LowerUMUL_LOHI
(
Op
,
DAG
)
;
case
ISD
::
ADD
:
case
ISD
::
SUB
:
return
ExpandADDSUB
(
Op
.
getNode
(
)
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
TRAMPOLINE
:
return
LowerTRAMPOLINE
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
return
SDValue
(
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

XCore
XCore
ISD::GlobalAddress
ISD::GlobalTLSAddress
ISD::BlockAddress
ISD::ConstantPool
ISD::BR_JT
ISD::LOAD
ISD::STORE
ISD::SELECT_CC
ISD::VAARG
ISD::VASTART
ISD::SMUL_LOHI
ISD::UMUL_LOHI
ISD::ADD
ISD::SUB
ISD::FRAMEADDR
ISD::TRAMPOLINE
"unimplemented operand"


<s> unsigned AArch64InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case AArch64 :: LDRWui : case AArch64 :: LDRXui : case AArch64 :: LDRBui : case AArch64 :: LDRHui : case AArch64 :: LDRSui : case AArch64 :: LDRDui : case AArch64 :: LDRQui : if ( MI -> getOperand ( 0 ) . getSubReg ( ) == 0 && MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> machine_mode aarch64_hard_regno_caller_save_mode ( unsigned regno , unsigned , machine_mode mode ) { if ( PR_REGNUM_P ( regno ) ) return mode ; if ( known_ge ( GET_MODE_SIZE ( mode ) , 4 ) ) return mode ; else return SImode ; } </s>


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesAll ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void OR1KFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned StackAlign = TRI -> needsStackRealignment ( MF ) ? MFI -> getMaxAlignment ( ) : MF . getSubtarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = alignTo ( maxCallFrameSize , StackAlign ) ; MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; if ( ! ( hasReservedCallFrame ( MF ) && MFI -> adjustsStack ( ) ) ) FrameSize += maxCallFrameSize ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI -> setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
Kind
==
KindReg
&&
"Not a register"
)
;
return
Reg
.
Num
;
}
</s>

Returns the register associated with this edge .


<s> EVT ARMTargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return getPointerTy ( DL ) ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> static rtx xtensa_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) < UNITS_PER_WORD ) ? SImode : mode , GP_RETURN ) ; } </s>

Worker function for TARGET_LIBCALL_VALUE .


<s> static bool nds32_plus_reg_load_store_p ( rtx_insn * insn ) { rtx mem_src = NULL_RTX ; switch ( get_attr_type ( insn ) ) { case TYPE_LOAD : mem_src = SET_SRC ( PATTERN ( insn ) ) ; break ; case TYPE_STORE : mem_src = SET_DEST ( PATTERN ( insn ) ) ; break ; default : break ; } if ( mem_src != NULL_RTX ) { if ( ( GET_CODE ( mem_src ) == ZERO_EXTEND ) || ( GET_CODE ( mem_src ) == SIGN_EXTEND ) ) mem_src = XEXP ( mem_src , 0 ) ; if ( ( GET_CODE ( XEXP ( mem_src , 0 ) ) == PLUS ) ) mem_src = XEXP ( mem_src , 0 ) ; else return false ; if ( GET_CODE ( XEXP ( mem_src , 0 ) ) == REG ) return true ; } return false ; } </s>

Return true if is load with [ REG + REG/CONST_INT ] addressing mode .


<s> static int uses_arg_area_p ( ) { register tree parm ; if ( current_function_decl == 0 || current_function_varargs || variable_args_p ) return 1 ; for ( parm = DECL_ARGUMENTS ( current_function_decl ) ; parm ; parm = TREE_CHAIN ( parm ) ) { if ( DECL_RTL ( parm ) == 0 || GET_CODE ( DECL_RTL ( parm ) ) == MEM ) return 1 ; if ( DECL_INCOMING_RTL ( parm ) == 0 || GET_CODE ( DECL_INCOMING_RTL ( parm ) ) == MEM ) return 1 ; } return 0 ; } </s>

Determine if the current function has any references to the arg pointer . This is done indirectly by examining the DECL_ARGUMENTS ' DECL_RTL . It is OK to return TRUE if there are no references , but FALSE must be correct .


<s> MachineInstr * AMDGPUInstrInfo :: convertToThreeAddress ( MachineFunction :: iterator & MFI , MachineBasicBlock :: iterator & MBBI , LiveVariables * LV ) const { return nullptr ; } </s>

convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag .


<s> void msp430_expand_helper ( rtx * operands , const char * helper_name , bool const_variants ) { rtx c , f ; char * helper_const = NULL ; int arg2 = 13 ; int arg1sz = 1 ; machine_mode arg0mode = GET_MODE ( operands [ 0 ] ) ; machine_mode arg1mode = GET_MODE ( operands [ 1 ] ) ; machine_mode arg2mode = GET_MODE ( operands [ 2 ] ) ; int have_430x = msp430x ? 1 : 0 ; if ( CONST_INT_P ( operands [ 2 ] ) ) { int i ; for ( i = 0 ; const_shift_helpers [ i ] . name ; i ++ ) { if ( const_shift_helpers [ i ] . need_430x <= have_430x && strcmp ( helper_name , const_shift_helpers [ i ] . name ) == 0 && INTVAL ( operands [ 2 ] ) == const_shift_helpers [ i ] . count ) { emit_insn ( const_shift_helpers [ i ] . genfunc ( operands [ 0 ] , operands [ 1 ] ) ) ; return ; } } } if ( arg1mode == VOIDmode ) arg1mode = arg0mode ; if ( arg2mode == VOIDmode ) arg2mode = arg0mode ; if ( arg1mode == SImode ) { arg2 = 14 ; arg1sz = 2 ; } if ( const_variants && CONST_INT_P ( operands [ 2 ] ) && INTVAL ( operands [ 2 ] ) >= 1 && INTVAL ( operands [ 2 ] ) <= 15 ) { int len = strlen ( helper_name ) + 4 ; helper_const = ( char * ) xmalloc ( len ) ; snprintf ( helper_const , len , "%s_%d" , helper_name , ( int ) INTVAL ( operands [ 2 ] ) ) ; } emit_move_insn ( gen_rtx_REG ( arg1mode , 12 ) , operands [ 1 ] ) ; if ( ! helper_const ) emit_move_insn ( gen_rtx_REG ( arg2mode , arg2 ) , operands [ 2 ] ) ; c = gen_call_value_internal ( gen_rtx_REG ( arg0mode , 12 ) , gen_rtx_SYMBOL_REF ( VOIDmode , helper_const ? helper_const : helper_name ) , GEN_INT ( 0 ) ) ; c = emit_call_insn ( c ) ; RTL_CONST_CALL_P ( c ) = 1 ; f = 0 ; use_regs ( & f , 12 , arg1sz ) ; if ( ! helper_const ) use_regs ( & f , arg2 , 1 ) ; add_function_usage_to ( c , f ) ; emit_move_insn ( operands [ 0 ] , gen_rtx_REG ( arg0mode , 12 ) ) ; } </s>

The MSP430 ABI defines a number of helper functions that should be used for , for example , 32-bit shifts . This function is called to emit such a function , using the table above to optimize some cases .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s> bool RISCVFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; auto * RVFI = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || RVFI -> hasSpillVRs ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void DataFlowGraph :: reset ( ) { Memory . clear ( ) ; BlockNodes . clear ( ) ; Func = NodeAddr < FuncNode * > ( ) ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s> static bool sparc_pass_by_reference ( cumulative_args_t cum ATTRIBUTE_UNUSED , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { if ( TARGET_ARCH32 ) return ( ( type && ( AGGREGATE_TYPE_P ( type ) || VECTOR_FLOAT_TYPE_P ( type ) ) ) || mode == SCmode || GET_MODE_SIZE ( mode ) > 8 || ( type && VECTOR_TYPE_P ( type ) && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > 8 ) ) ; else return ( ( type && ( AGGREGATE_TYPE_P ( type ) || VECTOR_TYPE_P ( type ) ) && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > 16 ) || GET_MODE_SIZE ( mode ) > 16 ) ; } </s>

Handle the TARGET_PASS_BY_REFERENCE target hook . Specify whether to pass the argument by reference .


<s> static void mips16_lay_out_constants ( bool split_p ) { struct mips16_constant_pool pool ; rtx_insn * insn , * barrier ; if ( ! TARGET_MIPS16_PCREL_LOADS ) return ; if ( split_p ) { if ( mips_cfg_in_reorg ( ) ) split_all_insns ( ) ; else split_all_insns_noflow ( ) ; } barrier = 0 ; memset ( & pool , 0 , sizeof ( pool ) ) ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( USEFUL_INSN_P ( insn ) ) mips16_rewrite_pool_refs ( insn , & pool ) ; pool . insn_address += mips16_insn_length ( insn ) ; if ( pool . first != NULL ) { if ( barrier == 0 && pool . insn_address + 4 > pool . highest_address ) { rtx_code_label * label ; rtx_insn * jump ; label = gen_label_rtx ( ) ; jump = emit_jump_insn_before ( gen_jump ( label ) , insn ) ; JUMP_LABEL ( jump ) = label ; LABEL_NUSES ( label ) = 1 ; barrier = emit_barrier_after ( jump ) ; emit_label_after ( label , barrier ) ; pool . insn_address += 4 ; } if ( pool . insn_address > pool . highest_address ) { mips16_emit_constants ( pool . first , barrier ) ; pool . first = NULL ; barrier = 0 ; } else if ( BARRIER_P ( insn ) ) barrier = insn ; } } mips16_emit_constants ( pool . first , get_last_insn ( ) ) ; } </s>


"FP elimination on a non-leaf function is not supported"

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s>
void
SIFrameLowering
::
determineCalleeSaves
(
MachineFunction
&
MF
,
BitVector
&
SavedVGPRs
,
RegScavenger
*
RS
)
const
{
TargetFrameLowering
::
determineCalleeSaves
(
MF
,
SavedVGPRs
,
RS
)
;
SIMachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
SIMachineFunctionInfo
>
(
)
;
if
(
MFI
->
isEntryFunction
(
)
)
return
;
MachineFrameInfo
&
FrameInfo
=
MF
.
getFrameInfo
(
)
;
const
GCNSubtarget
&
ST
=
MF
.
getSubtarget
<
GCNSubtarget
>
(
)
;
const
SIRegisterInfo
*
TRI
=
ST
.
getRegisterInfo
(
)
;
SavedVGPRs
.
clearBitsNotInMask
(
TRI
->
getAllVGPRRegMask
(
)
)
;
const
bool
WillHaveFP
=
FrameInfo
.
hasCalls
(
)
&&
(
SavedVGPRs
.
any
(
)
||
!
allStackObjectsAreDead
(
FrameInfo
)
)
;
for
(
auto
SSpill
:
MFI
->
getSGPRSpillVGPRs
(
)
)
SavedVGPRs
.
reset
(
SSpill
.
VGPR
)
;
LivePhysRegs
LiveRegs
;
LiveRegs
.
init
(
*
TRI
)
;
if
(
WillHaveFP
||
hasFP
(
MF
)
)
{
assert
(
!
MFI
->
SGPRForFPSaveRestoreCopy
&&
!
MFI
->
FramePointerSaveIndex
&&
"Re-reserving spill slot for FP"
)
;
getVGPRSpillLaneOrTempRegister
(
MF
,
LiveRegs
,
MFI
->
SGPRForFPSaveRestoreCopy
,
MFI
->
FramePointerSaveIndex
,
true
)
;
}
if
(
TRI
->
hasBasePointer
(
MF
)
)
{
if
(
MFI
->
SGPRForFPSaveRestoreCopy
)
LiveRegs
.
addReg
(
MFI
->
SGPRForFPSaveRestoreCopy
)
;
assert
(
!
MFI
->
SGPRForBPSaveRestoreCopy
&&
!
MFI
->
BasePointerSaveIndex
&&
"Re-reserving spill slot for BP"
)
;
getVGPRSpillLaneOrTempRegister
(
MF
,
LiveRegs
,
MFI
->
SGPRForBPSaveRestoreCopy
,
MFI
->
BasePointerSaveIndex
,
false
)
;
}
}
</s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .

AMDGPU
SI
SI
SI
SI
"Re-reserving spill slot for FP"
"Re-reserving spill slot for BP"


<s> rtx ix86_force_to_memory ( enum machine_mode mode , rtx operand ) { rtx result ; gcc_assert ( reload_completed ) ; if ( TARGET_RED_ZONE ) { result = gen_rtx_MEM ( mode , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( - RED_ZONE_SIZE ) ) ) ; emit_move_insn ( result , operand ) ; } else if ( ! TARGET_RED_ZONE && TARGET_64BIT ) { switch ( mode ) { case HImode : case SImode : operand = gen_lowpart ( DImode , operand ) ; case DImode : emit_insn ( gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( DImode , gen_rtx_PRE_DEC ( DImode , stack_pointer_rtx ) ) , operand ) ) ; break ; default : gcc_unreachable ( ) ; } result = gen_rtx_MEM ( mode , stack_pointer_rtx ) ; } else { switch ( mode ) { case DImode : { rtx operands [ 2 ] ; split_di ( & operand , 1 , operands , operands + 1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( SImode , gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ) , operands [ 1 ] ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( SImode , gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ) , operands [ 0 ] ) ) ; } break ; case HImode : operand = gen_lowpart ( SImode , operand ) ; case SImode : emit_insn ( gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( GET_MODE ( operand ) , gen_rtx_PRE_DEC ( SImode , stack_pointer_rtx ) ) , operand ) ) ; break ; default : gcc_unreachable ( ) ; } result = gen_rtx_MEM ( mode , stack_pointer_rtx ) ; } return result ; } </s>

Store OPERAND to the memory after reload is completed . This means that we ca n't easily use assign_stack_local .


<s> void WebAssemblyInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << getRegisterName ( RegNo ) ; } </s>