<s>
const
MCPhysReg
*
RISCVRegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
auto
&
Subtarget
=
MF
->
getSubtarget
<
RISCVSubtarget
>
(
)
;
if
(
MF
->
getFunction
(
)
.
hasFnAttribute
(
"interrupt"
)
)
{
if
(
Subtarget
.
hasStdExtD
(
)
)
return
CSR_XLEN_F64_Interrupt_SaveList
;
if
(
Subtarget
.
hasStdExtF
(
)
)
return
CSR_XLEN_F32_Interrupt_SaveList
;
return
CSR_Interrupt_SaveList
;
}
switch
(
Subtarget
.
getTargetABI
(
)
)
{
default
:
llvm_unreachable
(
"Unrecognized ABI"
)
;
case
RISCVABI
::
ABI_ILP32
:
case
RISCVABI
::
ABI_LP64
:
return
CSR_ILP32_LP64_SaveList
;
case
RISCVABI
::
ABI_ILP32F
:
case
RISCVABI
::
ABI_LP64F
:
return
CSR_ILP32F_LP64F_SaveList
;
case
RISCVABI
::
ABI_ILP32D
:
case
RISCVABI
::
ABI_LP64D
:
return
CSR_ILP32D_LP64D_SaveList
;
}
}
</s>


<s> bool BlackfinFrameInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return DisableFramePointerElim ( MF ) || MFI -> adjustsStack ( ) || MFI -> hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> MCELFStreamer & VETargetELFStreamer :: getStreamer ( ) { return static_cast < MCELFStreamer & > ( Streamer ) ; } </s>

Return the output streamer for the assembler .


<s> static bool arm_cannot_force_const_mem ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { rtx base , offset ; if ( ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P ) { split_const ( x , & base , & offset ) ; if ( GET_CODE ( base ) == SYMBOL_REF && ! offset_within_block_p ( base , INTVAL ( offset ) ) ) return true ; } return arm_tls_referenced_p ( x ) ; } </s>


<s> void AGCAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const { return ; } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> const BPFInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> bool WinEHStatePass :: runOnFunction ( Function & F ) { if ( F . hasAvailableExternallyLinkage ( ) ) return false ; if ( ! F . hasPersonalityFn ( ) ) return false ; PersonalityFn = dyn_cast < Function > ( F . getPersonalityFn ( ) -> stripPointerCastsSafe ( ) ) ; if ( ! PersonalityFn ) return false ; Personality = classifyEHPersonality ( PersonalityFn ) ; if ( ! isFuncletEHPersonality ( Personality ) ) return false ; bool HasPads = false ; for ( BasicBlock & BB : F ) { if ( BB . isEHPad ( ) ) { HasPads = true ; break ; } } if ( ! HasPads ) return false ; Type * Int8PtrType = Type :: getInt8PtrTy ( TheModule -> getContext ( ) ) ; SetJmp3 = TheModule -> getOrInsertFunction ( "_setjmp3" , FunctionType :: get ( Type :: getInt32Ty ( TheModule -> getContext ( ) ) , { Int8PtrType , Type :: getInt32Ty ( TheModule -> getContext ( ) ) } , true ) ) ; emitExceptionRegistrationRecord ( & F ) ; WinEHFuncInfo FuncInfo ; addStateStores ( F , FuncInfo ) ; PersonalityFn = nullptr ; Personality = EHPersonality :: Unknown ; UseStackGuard = false ; RegNode = nullptr ; EHGuardNode = nullptr ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static bool ix86_member_type_forces_blk ( const_tree field , machine_mode mode ) { return ( mode == XFmode && ( TREE_CODE ( DECL_FIELD_CONTEXT ( field ) ) == UNION_TYPE || TREE_CODE ( DECL_FIELD_CONTEXT ( field ) ) == QUAL_UNION_TYPE ) ) ; } </s>

Return true if a structure , union or array with MODE containing FIELD should be accessed using BLKmode .


<s> unsigned SparcInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == SP :: STri || MI -> getOpcode ( ) == SP :: STFri || MI -> getOpcode ( ) == SP :: STDFri ) { if ( MI -> getOperand ( 0 ) . isFI ( ) && MI -> getOperand ( 1 ) . isImm ( ) && MI -> getOperand ( 1 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 0 ) . getIndex ( ) ; return MI -> getOperand ( 2 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


"Only base registers and frame indices are supported."

"getMemOperandWithOffsetWidth return incorrect base op"

Returns true if the two given memory operations should be scheduled adjacent .


<s> InstructionCost HexagonTTIImpl :: getOperandsScalarizationOverhead ( ArrayRef < const Value * > Args , ArrayRef < Type * > Tys ) { return BaseT :: getOperandsScalarizationOverhead ( Args , Tys ) ; } </s>

Estimate the overhead of scalarizing an instructions unique non-constant operands .


<s> SMLoc getEndLoc ( ) const { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s>
std
::
unique_ptr
<
DLXOperand
>
DLXAsmParser
::
parseIdentifier
(
)
{
SMLoc
Start
=
Parser
.
getTok
(
)
.
getLoc
(
)
;
SMLoc
End
=
SMLoc
::
getFromPointer
(
Parser
.
getTok
(
)
.
getLoc
(
)
.
getPointer
(
)
1
)
;
const
MCExpr
*
Res
,
*
RHS
=
nullptr
;
DLXMCExpr
::
VariantKind
Kind
=
DLXMCExpr
::
VK_DLX_None
;
if
(
Lexer
.
getKind
(
)
!=
AsmToken
::
Identifier
)
return
nullptr
;
StringRef
Identifier
;
if
(
Parser
.
parseIdentifier
(
Identifier
)
)
return
nullptr
;
if
(
Identifier
.
equals_lower
(
"hi"
)
)
Kind
=
DLXMCExpr
::
VK_DLX_ABS_HI
;
else
if
(
Identifier
.
equals_lower
(
"lo"
)
)
Kind
=
DLXMCExpr
::
VK_DLX_ABS_LO
;
if
(
Kind
!=
DLXMCExpr
::
VK_DLX_None
)
{
if
(
Lexer
.
getKind
(
)
!=
AsmToken
::
LParen
)
{
Error
(
Lexer
.
getLoc
(
)
,
"Expected '('"
)
;
return
nullptr
;
}
Lexer
.
Lex
(
)
;
if
(
Parser
.
parseIdentifier
(
Identifier
)
)
return
nullptr
;
}
if
(
Lexer
.
getKind
(
)
==
AsmToken
::
Plus
&&
Parser
.
parseExpression
(
RHS
)
)
return
nullptr
;
if
(
Kind
!=
DLXMCExpr
::
VK_DLX_None
)
{
if
(
Lexer
.
getKind
(
)
!=
AsmToken
::
RParen
)
{
Error
(
Lexer
.
getLoc
(
)
,
"Expected ')'"
)
;
return
nullptr
;
}
Lexer
.
Lex
(
)
;
}
End
=
SMLoc
::
getFromPointer
(
Parser
.
getTok
(
)
.
getLoc
(
)
.
getPointer
(
)
1
)
;
MCSymbol
*
Sym
=
getContext
(
)
.
getOrCreateSymbol
(
Identifier
)
;
const
MCExpr
*
Expr
=
MCSymbolRefExpr
::
create
(
Sym
,
getContext
(
)
)
;
Res
=
DLXMCExpr
::
create
(
Kind
,
Expr
,
getContext
(
)
)
;
if
(
RHS
)
Res
=
MCBinaryExpr
::
createAdd
(
Res
,
RHS
,
getContext
(
)
)
;
return
DLXOperand
::
createImm
(
Res
,
Start
,
End
)
;
}
</s>

Parse an identifier or string ( as a quoted identifier ) and set Res to the identifier contents .

DLX
DLX
DLX
1
DLX
DLX
DLX
"hi"
DLX
DLX
"lo"
DLX
DLX
DLX
DLX
"Expected '('"
DLX
DLX
"Expected ')'"
1
DLX
DLXOperand::createImm


"Cannot store this register to stack slot!"

Store the specified register of the given register class to the specified stack frame index .


<s> bool RISCVCallLowering :: lowerCall ( MachineIRBuilder & MIRBuilder , CallLoweringInfo & Info ) const { return false ; } </s>

This hook must be implemented to lower the given call instruction , including argument and return value marshalling .


<s> StringRef getPassName ( ) const override { return RISCV_OPTIMIZE_VSETVL_USES_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> Relocator :: Result none ( Relocation & pReloc , X86_64Relocator & pParent ) { return Relocator :: OK ; } </s>

Returns true if none of the bits are set .


<s> const RegisterBankInfo * RISCVSubtarget :: getRegBankInfo ( ) const { return RegBankInfo . get ( ) ; } </s>

If the information for the register banks is available , return it .


<s>
void
M68kOperand
::
print
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
Kind
::
Invalid
:
OS
<<
"invalid"
;
break
;
case
Kind
::
Token
:
OS
<<
"token '"
<<
Token
<<
"'"
;
break
;
case
Kind
::
Imm
:
OS
<<
"immediate "
<<
Imm
;
break
;
case
Kind
::
MemOp
:
MemOp
.
print
(
OS
)
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

M68k
M68k
"invalid"
"token '"
"'"
"immediate "


<s> static void ix86_add_new_builtins ( HOST_WIDE_INT isa , HOST_WIDE_INT isa2 ) { isa &= ~ OPTION_MASK_ISA_64BIT ; if ( ( isa & deferred_isa_values ) == 0 && ( isa2 & deferred_isa_values2 ) == 0 ) return ; deferred_isa_values &= ~ isa ; deferred_isa_values2 &= ~ isa2 ; int i ; tree saved_current_target_pragma = current_target_pragma ; current_target_pragma = NULL_TREE ; for ( i = 0 ; i < ( int ) IX86_BUILTIN_MAX ; i ++ ) { if ( ( ( ix86_builtins_isa [ i ] . isa & isa ) != 0 || ( ix86_builtins_isa [ i ] . isa2 & isa2 ) != 0 ) && ix86_builtins_isa [ i ] . set_and_not_built_p ) { tree decl , type ; ix86_builtins_isa [ i ] . set_and_not_built_p = false ; type = ix86_get_builtin_func_type ( ix86_builtins_isa [ i ] . tcode ) ; decl = add_builtin_function_ext_scope ( ix86_builtins_isa [ i ] . name , type , i , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ i ] = decl ; if ( ix86_builtins_isa [ i ] . const_p ) TREE_READONLY ( decl ) = 1 ; } } current_target_pragma = saved_current_target_pragma ; } </s>

Add any new builtin functions for a given ISA that may not have been declared . This saves a bit of space compared to adding all of the declarations to the tree , even if we did n't use them .


<s> enum attr_opx_type m68k_sched_attr_opx_type ( rtx_insn * insn , int address_p ) { switch ( sched_attr_op_type ( insn , true , address_p != 0 ) ) { case OP_TYPE_RN : return OPX_TYPE_RN ; case OP_TYPE_FPN : return OPX_TYPE_FPN ; case OP_TYPE_MEM1 : return OPX_TYPE_MEM1 ; case OP_TYPE_MEM234 : return OPX_TYPE_MEM234 ; case OP_TYPE_MEM5 : return OPX_TYPE_MEM5 ; case OP_TYPE_MEM6 : return OPX_TYPE_MEM6 ; case OP_TYPE_MEM7 : return OPX_TYPE_MEM7 ; case OP_TYPE_IMM_Q : return OPX_TYPE_IMM_Q ; case OP_TYPE_IMM_W : return OPX_TYPE_IMM_W ; case OP_TYPE_IMM_L : return OPX_TYPE_IMM_L ; default : gcc_unreachable ( ) ; } } </s>

Implement opx_type attribute . Return type of INSN 's operand X . If ADDRESS_P is true , return type of memory location operand refers to .


<s> rtx xtensa_function_value ( const_tree valtype , const_tree func ATTRIBUTE_UNUSED , bool outgoing ) { return gen_rtx_REG ( ( INTEGRAL_TYPE_P ( valtype ) && TYPE_PRECISION ( valtype ) < BITS_PER_WORD ) ? SImode : TYPE_MODE ( valtype ) , outgoing ? GP_OUTGOING_RETURN : GP_RETURN_FIRST ) ; } </s>

Worker function for TARGET_FUNCTION_VALUE .


<s> AMDGPUSubtarget & AMDGPUSubtarget :: initializeSubtargetDependencies ( StringRef TT , StringRef GPU , StringRef FS ) { SmallString < 256 > FullFS ( "+promote-alloca,+fp64-denormals," ) ; FullFS += FS ; if ( GPU == "" && Triple ( TT ) . getArch ( ) == Triple :: amdgcn ) GPU = "SI" ; ParseSubtargetFeatures ( GPU , FullFS ) ; if ( getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) { FP32Denormals = false ; FP64Denormals = false ; } return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> static rtx aapcs_vfp_allocate_return_reg ( enum arm_pcs pcs_variant ATTRIBUTE_UNUSED , machine_mode mode , const_tree type ATTRIBUTE_UNUSED ) { if ( ! use_vfp_abi ( pcs_variant , false ) ) return NULL ; if ( mode == BLKmode || ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) >= GET_MODE_SIZE ( TImode ) && ! ( TARGET_NEON || TARGET_HAVE_MVE ) ) ) { int count ; machine_mode ag_mode ; int i ; rtx par ; int shift ; aapcs_vfp_is_call_or_return_candidate ( pcs_variant , mode , type , & ag_mode , & count ) ; if ( ! ( TARGET_NEON || TARGET_HAVE_MVE ) ) { if ( ag_mode == V2SImode ) ag_mode = DImode ; else if ( ag_mode == V4SImode ) { ag_mode = DImode ; count *= 2 ; } } shift = GET_MODE_SIZE ( ag_mode ) / GET_MODE_SIZE ( SFmode ) ; par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( count ) ) ; for ( i = 0 ; i < count ; i ++ ) { rtx tmp = gen_rtx_REG ( ag_mode , FIRST_VFP_REGNUM + i * shift ) ; tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , GEN_INT ( i * GET_MODE_SIZE ( ag_mode ) ) ) ; XVECEXP ( par , 0 , i ) = tmp ; } return par ; } return gen_rtx_REG ( mode , FIRST_VFP_REGNUM ) ; } </s>

Implement the allocate_return_reg field in aapcs_cp_arg_layout . See the comment there for the behaviour of this function .


<s>
bool
AAPAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
matchingInlineAsm
)
{
MCInst
Inst
;
SMLoc
ErrorLoc
;
switch
(
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
matchingInlineAsm
)
)
{
default
:
break
;
case
Match_Success
:
Out
.
EmitInstruction
(
Inst
,
getSTI
(
)
)
;
return
false
;
case
Match_MissingFeature
:
{
assert
(
ErrorInfo
&&
"Unknown missing feature!"
)
;
std
::
string
Msg
=
"Use of this instruction requires:"
;
unsigned
Mask
=
1
;
for
(
unsigned
i
=
0
;
i
<
(
sizeof
(
ErrorInfo
)
*
8
1
)
;
++
i
)
{
if
(
ErrorInfo
&
Mask
)
{
Msg
+=
" "
;
Msg
+=
getSubtargetFeatureName
(
ErrorInfo
&
Mask
)
;
}
Mask
<<=
1
;
}
return
Error
(
IDLoc
,
Msg
)
;
}
case
Match_MnemonicFail
:
return
Error
(
IDLoc
,
"Unrecognized instruction mnemonic"
)
;
case
Match_InvalidOperand
:
ErrorLoc
=
IDLoc
;
if
(
ErrorInfo
!=
~
0U
)
{
if
(
ErrorInfo
>=
Operands
.
size
(
)
)
return
Error
(
IDLoc
,
"Too few operands for instruction"
)
;
ErrorLoc
=
(
(
AAPOperand
&
)
*
Operands
[
ErrorInfo
]
)
.
getStartLoc
(
)
;
if
(
ErrorLoc
==
SMLoc
(
)
)
ErrorLoc
=
IDLoc
;
}
return
Error
(
IDLoc
,
"Invalid operand for instruction"
)
;
}
llvm_unreachable
(
"Unknown match type detected!"
)
;
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittleEndian ? i : ( NumBytes - 1 - i ) ; Data [ Offset + i ] |= uint8_t ( ( Value >> ( Idx * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static rtx m68k_call_tls_get_addr ( rtx x , rtx eqv , enum m68k_reloc reloc ) { rtx a0 ; rtx_insn * insns ; rtx dest ; start_sequence ( ) ; x = m68k_wrap_symbol ( x , reloc , m68k_get_gp ( ) , NULL_RTX ) ; m68k_libcall_value_in_a0_p = true ; a0 = emit_library_call_value ( m68k_get_tls_get_addr ( ) , NULL_RTX , LCT_PURE , Pmode , x , Pmode ) ; m68k_libcall_value_in_a0_p = false ; insns = get_insns ( ) ; end_sequence ( ) ; gcc_assert ( can_create_pseudo_p ( ) ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , a0 , eqv ) ; return dest ; } </s>

Emit instruction sequence that calls __tls_get_addr . X is the TLS symbol we are referencing and RELOC is the symbol type to use ( either TLSGD or TLSLDM ) . EQV is the REG_EQUAL note for the sequence emitted . A pseudo register with result of __tls_get_addr call is returned .


<s> bool SIInstrInfo :: hasUnwantedEffectsWhenEXECEmpty ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( MI . mayStore ( ) && isSMRD ( MI ) ) return true ; if ( Opcode == AMDGPU :: S_SENDMSG || Opcode == AMDGPU :: S_SENDMSGHALT || Opcode == AMDGPU :: EXP || Opcode == AMDGPU :: EXP_DONE ) return true ; if ( MI . isInlineAsm ( ) ) return true ; if ( Opcode == AMDGPU :: V_READFIRSTLANE_B32 || Opcode == AMDGPU :: V_READLANE_B32 ) return true ; return false ; } </s>

Whether we must prevent this instruction from executing with EXEC = 0 .


<s> const uint32_t * MipsRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { const MipsSubtarget & Subtarget = MF . getSubtarget < MipsSubtarget > ( ) ; if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_RegMask ; if ( Subtarget . isABI_CheriPureCap ( ) ) return CSR_Cheri_Purecap_RegMask ; if ( Subtarget . isCheri ( ) ) return CSR_N64_Cheri_RegMask ; if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_RegMask ; if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_RegMask ; if ( Subtarget . isFP64bit ( ) ) return CSR_O32_FP64_RegMask ; if ( Subtarget . isFPXX ( ) ) return CSR_O32_FPXX_RegMask ; return CSR_O32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> struct xstormy16_stack_layout xstormy16_compute_stack_layout ( ) { struct xstormy16_stack_layout layout ; int regno ; const int ifun = xstormy16_interrupt_function_p ( ) ; layout . locals_size = get_frame_size ( ) ; layout . register_save_size = 0 ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( REG_NEEDS_SAVE ( regno , ifun ) ) layout . register_save_size += UNITS_PER_WORD ; if ( current_function_varargs || current_function_stdarg ) layout . stdarg_save_size = NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD ; else layout . stdarg_save_size = 0 ; layout . frame_size = ( layout . locals_size + layout . register_save_size + layout . stdarg_save_size ) ; if ( current_function_args_size <= 2048 && current_function_args_size != - 1 ) { if ( layout . frame_size + INCOMING_FRAME_SP_OFFSET + current_function_args_size <= 2048 ) layout . fp_minus_ap = layout . frame_size + INCOMING_FRAME_SP_OFFSET ; else layout . fp_minus_ap = 2048 - current_function_args_size ; } else layout . fp_minus_ap = ( layout . stdarg_save_size + layout . register_save_size + INCOMING_FRAME_SP_OFFSET ) ; layout . sp_minus_fp = ( layout . frame_size + INCOMING_FRAME_SP_OFFSET - layout . fp_minus_ap ) ; layout . first_local_minus_ap = layout . sp_minus_fp - layout . locals_size ; return layout ; } </s>


<s> static bool sparc_legitimate_constant_p ( machine_mode mode , rtx x ) { switch ( GET_CODE ( x ) ) { case CONST : case SYMBOL_REF : if ( sparc_tls_referenced_p ( x ) ) return false ; break ; case CONST_DOUBLE : if ( TARGET_VIS && SCALAR_FLOAT_MODE_P ( mode ) && ( const_zero_operand ( x , mode ) || const_all_ones_operand ( x , mode ) ) ) return true ; return false ; case CONST_VECTOR : if ( TARGET_VIS && ( const_zero_operand ( x , mode ) || const_all_ones_operand ( x , mode ) ) ) return true ; return false ; default : break ; } return true ; } </s>

Determine if a given RTX is a valid constant . We already know this satisfies CONSTANT_P .


<s> void SIInstrInfo :: legalizeOpWithMove ( MachineInstr * MI , unsigned OpIdx ) const { MachineBasicBlock :: iterator I = MI ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineOperand & MO = MI -> getOperand ( OpIdx ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; unsigned RCID = get ( MI -> getOpcode ( ) ) . OpInfo [ OpIdx ] . RegClass ; const TargetRegisterClass * RC = RI . getRegClass ( RCID ) ; unsigned Opcode = AMDGPU :: V_MOV_B32_e32 ; if ( MO . isReg ( ) ) Opcode = AMDGPU :: COPY ; else if ( RI . isSGPRClass ( RC ) ) Opcode = AMDGPU :: S_MOV_B32 ; const TargetRegisterClass * VRC = RI . getEquivalentVGPRClass ( RC ) ; if ( RI . getCommonSubClass ( & AMDGPU :: VReg_64RegClass , VRC ) ) VRC = & AMDGPU :: VReg_64RegClass ; else VRC = & AMDGPU :: VGPR_32RegClass ; unsigned Reg = MRI . createVirtualRegister ( VRC ) ; DebugLoc DL = MBB -> findDebugLoc ( I ) ; BuildMI ( * MI -> getParent ( ) , I , DL , get ( Opcode ) , Reg ) . addOperand ( MO ) ; MO . ChangeToRegister ( Reg , false ) ; } </s>

Legalize the OpIndex operand of this instruction by inserting a MOV .


<s> MachineInstr * SIInstrInfo :: convertToThreeAddress ( MachineFunction :: iterator & MBB , MachineBasicBlock :: iterator & MI , LiveVariables * LV ) const { switch ( MI -> getOpcode ( ) ) { default : return nullptr ; case AMDGPU :: V_MAC_F32_e64 : break ; case AMDGPU :: V_MAC_F32_e32 : { const MachineOperand * Src0 = getNamedOperand ( * MI , AMDGPU :: OpName :: src0 ) ; if ( Src0 -> isImm ( ) && ! isInlineConstant ( * Src0 , 4 ) ) return nullptr ; break ; } } const MachineOperand * Dst = getNamedOperand ( * MI , AMDGPU :: OpName :: vdst ) ; const MachineOperand * Src0 = getNamedOperand ( * MI , AMDGPU :: OpName :: src0 ) ; const MachineOperand * Src1 = getNamedOperand ( * MI , AMDGPU :: OpName :: src1 ) ; const MachineOperand * Src2 = getNamedOperand ( * MI , AMDGPU :: OpName :: src2 ) ; return BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( AMDGPU :: V_MAD_F32 ) ) . addOperand ( * Dst ) . addImm ( 0 ) . addOperand ( * Src0 ) . addImm ( 0 ) . addOperand ( * Src1 ) . addImm ( 0 ) . addOperand ( * Src2 ) . addImm ( 0 ) . addImm ( 0 ) ; } </s>

convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag .


<s> void WebAssemblyPassConfig :: addPostRegAlloc ( ) { disablePass ( & PrologEpilogCodeInserterID ) ; disablePass ( & MachineCopyPropagationID ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createWebAssemblyRegStackify ( ) ) ; addPass ( createWebAssemblyRegColoring ( ) ) ; } TargetPassConfig :: addPostRegAlloc ( ) ; addPass ( createWebAssemblyPEI ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .

WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly


<s> bool M68kInstrInfo :: ExpandCCR ( MachineInstrBuilder & MIB , bool IsToCCR ) const { if ( IsToCCR ) MIB -> setDesc ( get ( M68k :: MOV16cd ) ) ; else MIB -> setDesc ( get ( M68k :: MOV16dc ) ) ; auto & Opd = MIB -> getOperand ( 1 ) ; Opd . setReg ( getRegisterInfo ( ) . getMatchingSuperReg ( Opd . getReg ( ) , M68k :: MxSubRegIndex8Lo , & M68k :: DR16RegClass ) ) ; return true ; } </s>


"unsupported cpu name returned from kernel "

Returns the canonical AT_PLATFORM if present , otherwise NULL .


"insertBranch must not be told to insert a fallthrough"

Insert branch code into the end of the specified MachineBasicBlock .


<s> const char * LEGTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return NULL ; case LEGISD :: RET_FLAG : return "RetFlag" ; case LEGISD :: LOAD_SYM : return "LOAD_SYM" ; case LEGISD :: MOVEi32 : return "MOVEi32" ; case LEGISD :: CALL : return "CALL" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s>
bool
MipsAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
DEBUG
(
dbgs
(
)
<<
"ParseInstruction\n"
)
;
getTargetStreamer
(
)
.
forbidModuleDirective
(
)
;
if
(
!
mnemonicIsValid
(
Name
,
0
)
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
NameLoc
,
"Unknown instruction"
)
;
}
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Name
,
NameLoc
,
*
this
)
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
&&
ParseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
)
{
if
(
ParseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
}
else
if
(
getLexer
(
)
.
is
(
AsmToken
::
LParen
)
&&
ParseParenSuffix
(
Name
,
Operands
)
)
return
true
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Mips
Mips
"ParseInstruction\n"
0
"Unknown instruction"
MipsOperand::CreateToken
"unexpected token in argument list"
"unexpected token in argument list"
"unexpected token in argument list"


<s> bool RISCVTargetLowering :: signExtendConstant ( const ConstantInt * CI ) const { return Subtarget . is64Bit ( ) && CI -> getType ( ) -> isIntegerTy ( 32 ) ; } </s>

Return true if this constant should be sign extended when promoting to a larger type .


<s> bool MLxExpansion :: runOnMachineFunction ( MachineFunction & Fn ) { TII = static_cast < const ARMBaseInstrInfo * > ( Fn . getTarget ( ) . getInstrInfo ( ) ) ; TRI = Fn . getTarget ( ) . getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= ExpandFPMLxInstructions ( MBB ) ; } return Modified ; } </s>

runOnMachineFunction - Emit the function body .


Define the offset between two registers , one to be eliminated , and the other its replacement , at the start of a routine .


<s> rtx sh_remove_overlapping_post_inc ( rtx dst , rtx src ) { if ( ! MEM_P ( src ) ) return src ; rtx addr = XEXP ( src , 0 ) ; if ( GET_CODE ( addr ) == POST_INC && reg_overlap_mentioned_p ( XEXP ( addr , 0 ) , dst ) ) return replace_equiv_address ( src , XEXP ( addr , 0 ) ) ; gcc_assert ( GET_CODE ( addr ) != POST_MODIFY ) ; return src ; } </s>

Given a move insn destiation and a source , make sure that the move source operand is not a post-inc mem load with the same address reg as the destination . Returns the modified source operand with the post-inc removed if necessary .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < TargetLibraryInfoWrapperPass > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool isMem ( ) const override { return false ; } </s>


<s> bool s390_decompose_shift_count ( rtx op , rtx * base , HOST_WIDE_INT * offset ) { HOST_WIDE_INT off = 0 ; if ( GET_CODE ( op ) == CONST_INT ) { off = INTVAL ( op ) ; op = NULL_RTX ; } if ( op && GET_CODE ( op ) == PLUS && GET_CODE ( XEXP ( op , 1 ) ) == CONST_INT ) { off = INTVAL ( XEXP ( op , 1 ) ) ; op = XEXP ( op , 0 ) ; } while ( op && GET_CODE ( op ) == SUBREG ) op = SUBREG_REG ( op ) ; if ( op && GET_CODE ( op ) != REG ) return false ; if ( offset ) * offset = off ; if ( base ) * base = op ; return true ; } </s>

Decompose a RTL expression OP for a shift count into its components , and return the base register in BASE and the offset in OFFSET . Return true if OP is a valid shift count , false if not .


"Instr doesn't have FrameIndex operand!"

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s> void replace_arg_pushes ( ) { } </s>

Here during RTL generation of return . If we are at the final return in a function , go through the function and replace pushes with stores into a frame arg block . This is similar to what ACCUMULATE_OUTGOING_ARGS does , but we must index off the frame pointer , not the stack pointer , and the calling sequence does not require the arg block to be at the top of the stack .


<s> bool ARMBaseRegisterInfo :: requiresFrameIndexScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s>
void
BT
::
run
(
)
{
reset
(
)
;
assert
(
FlowQ
.
empty
(
)
)
;
using
MachineFlowGraphTraits
=
GraphTraits
<
const
MachineFunction
*
>
;
const
MachineBasicBlock
*
Entry
=
MachineFlowGraphTraits
::
getEntryNode
(
&
MF
)
;
unsigned
MaxBN
=
0
;
for
(
const
MachineBasicBlock
&
B
:
MF
)
{
assert
(
B
.
getNumber
(
)
>=
0
&&
"Disconnected block"
)
;
unsigned
BN
=
B
.
getNumber
(
)
;
if
(
BN
>
MaxBN
)
MaxBN
=
BN
;
}
BitVector
BlockScanned
(
MaxBN
+
1
)
;
int
EntryN
=
Entry
->
getNumber
(
)
;
FlowQ
.
push
(
CFGEdge
(
1
,
EntryN
)
)
;
while
(
!
FlowQ
.
empty
(
)
)
{
CFGEdge
Edge
=
FlowQ
.
front
(
)
;
FlowQ
.
pop
(
)
;
if
(
EdgeExec
.
count
(
Edge
)
)
continue
;
EdgeExec
.
insert
(
Edge
)
;
ReachedBB
.
insert
(
Edge
.
second
)
;
const
MachineBasicBlock
&
B
=
*
MF
.
getBlockNumbered
(
Edge
.
second
)
;
MachineBasicBlock
::
const_iterator
It
=
B
.
begin
(
)
,
End
=
B
.
end
(
)
;
while
(
It
!=
End
&&
It
->
isPHI
(
)
)
{
const
MachineInstr
&
PI
=
*
It
++
;
InstrExec
.
insert
(
&
PI
)
;
visitPHI
(
PI
)
;
}
if
(
BlockScanned
[
Edge
.
second
]
)
continue
;
BlockScanned
[
Edge
.
second
]
=
true
;
while
(
It
!=
End
&&
!
It
->
isBranch
(
)
)
{
const
MachineInstr
&
MI
=
*
It
++
;
InstrExec
.
insert
(
&
MI
)
;
visitNonBranch
(
MI
)
;
}
if
(
It
==
End
)
{
MachineFunction
::
const_iterator
BIt
=
B
.
getIterator
(
)
;
MachineFunction
::
const_iterator
Next
=
std
::
next
(
BIt
)
;
if
(
Next
!=
MF
.
end
(
)
&&
B
.
isSuccessor
(
&
*
Next
)
)
{
int
ThisN
=
B
.
getNumber
(
)
;
int
NextN
=
Next
->
getNumber
(
)
;
FlowQ
.
push
(
CFGEdge
(
ThisN
,
NextN
)
)
;
}
}
else
{
visitBranchesFrom
(
*
It
)
;
}
}
if
(
Trace
)
print_cells
(
dbgs
(
)
<<
"Cells after propagation:\n"
)
;
}
</s>

Run the analysis pass over a function and produce a dominator tree .


<s> virtual const TargetRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> gimple * gimple_fold_builtin ( unsigned int code , gimple_stmt_iterator * gsi , gcall * stmt ) { registered_function & rfn = * ( * registered_functions ) [ code ] ; return gimple_folder ( rfn . instance , rfn . decl , gsi , stmt ) . fold ( ) ; } </s>

Attempt to fold STMT , given that it 's a call to the SVE function with subcode CODE . Return the new statement on success and null on failure . Insert any other new statements at GSI .


<s> static void csky_print_operand ( FILE * stream , rtx x , int code ) { switch ( code ) { case 'N' : if ( ( INTVAL ( x ) & 0xffffffff ) == 0xffffffff ) fprintf ( stream , "0" ) ; else fprintf ( stream , "%d" , ( int ) exact_log2 ( ( INTVAL ( x ) & 0xffffffff ) + 1 ) % 32 ) ; break ; case 'P' : fprintf ( stream , "%d" , ( int ) exact_log2 ( INTVAL ( x ) & 0xffffffff ) ) ; break ; case 'Q' : fprintf ( stream , "%d" , ( int ) exact_log2 ( ~ INTVAL ( x ) & 0xffffffff ) ) ; break ; case 'O' : fprintf ( stream , "%d" , ( int ) INTVAL ( x ) ) ; break ; case 'M' : fprintf ( stream , "%d" , ( int ) ( - INTVAL ( x ) ) ) ; break ; case 'R' : switch ( GET_CODE ( x ) ) { case REG : fputs ( reg_names [ REGNO ( x ) + 1 ] , stream ) ; break ; case MEM : csky_print_operand_address ( stream , GET_MODE ( x ) , XEXP ( adjust_address ( x , SImode , 4 ) , 0 ) ) ; break ; default : gcc_unreachable ( ) ; } break ; case 'H' : fprintf ( stream , "%ld" , ( long ) ( ( INTVAL ( x ) & 0xFFFF0000 ) >> 16 ) ) ; break ; default : switch ( GET_CODE ( x ) ) { case REG : fputs ( reg_names [ REGNO ( x ) ] , stream ) ; break ; case MEM : output_address ( GET_MODE ( x ) , XEXP ( x , 0 ) ) ; break ; case UNSPEC : csky_output_pic_addr_const ( stream , x , code ) ; break ; case CONST_DOUBLE : { char fpstr [ 20 ] ; real_to_decimal ( fpstr , CONST_DOUBLE_REAL_VALUE ( x ) , sizeof ( fpstr ) , 0 , 1 ) ; fprintf ( stream , "%s" , fpstr ) ; } break ; default : output_addr_const ( stream , x ) ; break ; } break ; } } </s>

Implement TARGET_PRINT_OPERAND . Print operand X ( an rtx ) in assembler syntax to file STREAM according to modifier CODE . 'N' print the log2 ( X+1 ) , mainly used for bmaski ' P' print the log2 ( X ) ' Q' print the log2 ( ~X ) ' O' print a decimal number 'M' print a decimal number as its negative ' R' print the next register or memory location along , i.e . the lsw in a double word value ' H' print the high 16 bits of a constant .


<s> bool SIInstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( MI . isTerminator ( ) || MI . isPosition ( ) ) return true ; return MI . modifiesRegister ( AMDGPU :: EXEC , & RI ) || MI . getOpcode ( ) == AMDGPU :: S_SETREG_IMM32_B32 || MI . getOpcode ( ) == AMDGPU :: S_SETREG_B32 || changesVGPRIndexingMode ( MI ) ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override { TargetTransformInfo :: getAnalysisUsage ( AU ) ; } </s>


"... Calling convention cannot be tail called.\n"

"... Cannot tail call from callers with byval "

"... Caller and callee have incompatible calling conventions.\n"

"... Call is eligible for tail call optimization.\n"

Returns true if the call can be lowered as a tail call .


<s> rtx m68k_libcall_value ( machine_mode mode ) { switch ( mode ) { case E_SFmode : case E_DFmode : case E_XFmode : if ( TARGET_68881 ) return gen_rtx_REG ( mode , FP0_REG ) ; break ; default : break ; } return gen_rtx_REG ( mode , m68k_libcall_value_in_a0_p ? A0_REG : D0_REG ) ; } </s>

Return floating point values in a 68881 register . This makes 68881 code a little bit faster . It also makes -msoft-float code incompatible with hard-float code , so people have to be careful not to mix the two . For ColdFire it was decided the ABI incompatibility is undesirable . If there is need for a hard-float ABI it is probably worth doing it properly and also passing function arguments in FP registers .


<s> unsigned RISCVInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : { if ( MI . getParent ( ) && MI . getParent ( ) -> getParent ( ) ) { const auto MF = MI . getMF ( ) ; const auto & TM = static_cast < const RISCVTargetMachine & > ( MF -> getTarget ( ) ) ; const MCRegisterInfo & MRI = * TM . getMCRegisterInfo ( ) ; const MCSubtargetInfo & STI = * TM . getMCSubtargetInfo ( ) ; const RISCVSubtarget & ST = MF -> getSubtarget < RISCVSubtarget > ( ) ; if ( isCompressibleInst ( MI , & ST , MRI , STI ) ) return 2 ; } return get ( Opcode ) . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return 0 ; case RISCV :: PseudoCALLReg : case RISCV :: PseudoCALL : case RISCV :: PseudoJump : case RISCV :: PseudoTAIL : case RISCV :: PseudoLLA : case RISCV :: PseudoLA : case RISCV :: PseudoLA_TLS_IE : case RISCV :: PseudoLA_TLS_GD : return 8 ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const auto & TM = static_cast < const RISCVTargetMachine & > ( MF . getTarget ( ) ) ; return getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .

RISCV RISCV RISCV RISCV RISCV 2 0 RISCV::PseudoCALLReg RISCV::PseudoCALL RISCV::PseudoJump RISCV::PseudoTAIL RISCV::PseudoLLA RISCV::PseudoLA RISCV::PseudoLA_TLS_IE RISCV::PseudoLA_TLS_GD 8 RISCV 0


<s> rtx prepare_scc_operands ( enum rtx_code code ) { rtx t_reg = gen_rtx_REG ( SImode , T_REG ) ; enum rtx_code oldcode = code ; enum machine_mode mode ; switch ( code ) { case NE : gcc_unreachable ( ) ; case LT : code = GT ; break ; case LE : code = GE ; break ; case LTU : code = GTU ; break ; case LEU : code = GEU ; break ; default : break ; } if ( code != oldcode ) { rtx tmp = sh_compare_op0 ; sh_compare_op0 = sh_compare_op1 ; sh_compare_op1 = tmp ; } mode = GET_MODE ( sh_compare_op0 ) ; if ( mode == VOIDmode ) mode = GET_MODE ( sh_compare_op1 ) ; sh_compare_op0 = force_reg ( mode , sh_compare_op0 ) ; if ( ( code != EQ && code != NE && ( sh_compare_op1 != const0_rtx || code == GTU || code == GEU || code == LTU || code == LEU ) ) || ( mode == DImode && sh_compare_op1 != const0_rtx ) || ( TARGET_SH2E && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) ) sh_compare_op1 = force_reg ( mode , sh_compare_op1 ) ; if ( ( TARGET_SH4 || TARGET_SH2A ) && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) ( mode == SFmode ? emit_sf_insn : emit_df_insn ) ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , gen_rtx_SET ( VOIDmode , t_reg , gen_rtx_fmt_ee ( code , SImode , sh_compare_op0 , sh_compare_op1 ) ) , gen_rtx_USE ( VOIDmode , get_fpscr_rtx ( ) ) ) ) ) ; else emit_insn ( gen_rtx_SET ( VOIDmode , t_reg , gen_rtx_fmt_ee ( code , SImode , sh_compare_op0 , sh_compare_op1 ) ) ) ; return t_reg ; } </s>

Prepare the operands for an scc instruction ; make sure that the compare has been done .


<s> bool X86TargetLowering :: IsEligibleForTailCallOptimization ( CallSDNode * TheCall , SDValue Ret , SelectionDAG & DAG ) const { if ( ! PerformTailCallOpt ) return false ; if ( CheckTailCallReturnConstraints ( TheCall , Ret ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned CallerCC = MF . getFunction ( ) -> getCallingConv ( ) ; unsigned CalleeCC = TheCall -> getCallingConv ( ) ; if ( CalleeCC == CallingConv :: Fast && CallerCC == CalleeCC ) { SDValue Callee = TheCall -> getCallee ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ || ! Subtarget -> isPICStyleGOT ( ) || ! Subtarget -> is64Bit ( ) ) return true ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) return G -> getGlobal ( ) -> hasHiddenVisibility ( ) || G -> getGlobal ( ) -> hasProtectedVisibility ( ) ; } } return false ; } </s>

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization .


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , stackAlignment ( 4 ) , CPUString ( CPU ) , TargetTriple ( TT ) , TargetABI ( ARM_ABI_APCS ) { initializeEnvironment ( ) ; resetSubtargetFeatures ( CPU , FS ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> bool ARMBaseTargetMachine :: addPreISel ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt :: None && EnableGlobalMerge ) PM . add ( createARMGlobalMergePass ( getTargetLowering ( ) ) ) ; return false ; } </s>


<s> void ARMBaseInstrInfo :: buildOutlinedFrame ( MachineBasicBlock & MBB , MachineFunction & MF , const outliner :: OutlinedFunction & OF ) const { if ( OF . FrameConstructionID == MachineOutlinerThunk ) { MachineInstr * Call = & * -- MBB . instr_end ( ) ; bool isThumb = Subtarget . isThumb ( ) ; unsigned FuncOp = isThumb ? 2 : 0 ; unsigned Opc = Call -> getOperand ( FuncOp ) . isReg ( ) ? isThumb ? ARM :: tTAILJMPr : ARM :: TAILJMPr : isThumb ? Subtarget . isTargetMachO ( ) ? ARM :: tTAILJMPd : ARM :: tTAILJMPdND : ARM :: TAILJMPd ; MachineInstrBuilder MIB = BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Opc ) ) . add ( Call -> getOperand ( FuncOp ) ) ; if ( isThumb && ! Call -> getOperand ( FuncOp ) . isReg ( ) ) MIB . add ( predOps ( ARMCC :: AL ) ) ; Call -> eraseFromParent ( ) ; } auto IsNonTailCall = [ ] ( MachineInstr & MI ) { return MI . isCall ( ) && ! MI . isReturn ( ) ; } ; if ( std :: any_of ( MBB . instr_begin ( ) , MBB . instr_end ( ) , IsNonTailCall ) ) { MachineBasicBlock :: iterator It = MBB . begin ( ) ; MachineBasicBlock :: iterator Et = MBB . end ( ) ; if ( OF . FrameConstructionID == MachineOutlinerTailCall || OF . FrameConstructionID == MachineOutlinerThunk ) Et = std :: prev ( MBB . end ( ) ) ; if ( ! MBB . isLiveIn ( ARM :: LR ) ) MBB . addLiveIn ( ARM :: LR ) ; saveLROnStack ( MBB , It ) ; emitCFIForLRSaveOnStack ( MBB , It ) ; restoreLRFromStack ( MBB , Et ) ; emitCFIForLRRestoreFromStack ( MBB , Et ) ; } if ( OF . FrameConstructionID == MachineOutlinerTailCall || OF . FrameConstructionID == MachineOutlinerThunk ) return ; BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Subtarget . getReturnOpcode ( ) ) ) . add ( predOps ( ARMCC :: AL ) ) ; } </s>

Insert a custom frame for outlined functions .

ARM ARM 2 0 ARM::tTAILJMPr ARM::TAILJMPr ARM::tTAILJMPd ARM::tTAILJMPdND ARM::TAILJMPd ARMCC::AL ARM::LR ARM::LR ARMCC::AL


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Hexagon VectorPrint pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
const
char
*
output_ubranch
(
rtx
dest
,
rtx_insn
*
insn
)
{
static
char
string
[
64
]
;
bool
v9_form
=
false
;
int
delta
;
char
*
p
;
delta
=
5000000
;
if
(
INSN_ADDRESSES_SET_P
(
)
)
delta
=
(
INSN_ADDRESSES
(
INSN_UID
(
dest
)
)
INSN_ADDRESSES
(
INSN_UID
(
insn
)
)
)
;
if
(
TARGET_V9
&&
delta
>=
260000
&&
delta
<
260000
)
v9_form
=
true
;
if
(
TARGET_CBCOND
)
{
bool
emit_nop
=
emit_cbcond_nop
(
insn
)
;
bool
far
=
false
;
const
char
*
rval
;
if
(
delta
<
500
||
delta
>
500
)
far
=
true
;
if
(
far
)
{
if
(
v9_form
)
rval
=
"ba,a,pt\t%%xcc, %l0"
;
else
rval
=
"b,a\t%l0"
;
}
else
{
if
(
emit_nop
)
rval
=
"cwbe\t%%g0, %%g0, %l0\n\tnop"
;
else
rval
=
"cwbe\t%%g0, %%g0, %l0"
;
}
return
rval
;
}
if
(
v9_form
)
strcpy
(
string
,
"ba%*,pt\t%%xcc, "
)
;
else
strcpy
(
string
,
"b%*\t"
)
;
p
=
strchr
(
string
,
'\0'
)
;
*
p
++
=
'%'
;
*
p
++
=
'l'
;
*
p
++
=
'0'
;
*
p
++
=
'%'
;
*
p
++
=
'('
;
*
p
=
'\0'
;
return
string
;
}
</s>

Output an unconditional branch to LABEL . INSN is the instruction .


<s> enum reg_class m32c_regno_reg_class ( int regno ) { switch ( regno ) { case R0_REGNO : return R0_REGS ; case R1_REGNO : return R1_REGS ; case R2_REGNO : return R2_REGS ; case R3_REGNO : return R3_REGS ; case A0_REGNO : return A0_REGS ; case A1_REGNO : return A1_REGS ; case SB_REGNO : return SB_REGS ; case FB_REGNO : return FB_REGS ; case SP_REGNO : return SP_REGS ; case FLG_REGNO : return FLG_REGS ; default : if ( IS_MEM_REGNO ( regno ) ) return MEM_REGS ; return ALL_REGS ; } } </s>


<s> unsigned R600InstrInfo :: calculateIndirectAddress ( unsigned RegIndex , unsigned Channel ) const { assert ( Channel == 0 ) ; return RegIndex ; } </s>

Calculate the `` Indirect Address '' for the given RegIndex and Channel .


<s>
SDValue
JVMTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
SDLoc
DL
(
Op
)
;
auto
PtrVT
=
getPointerTy
(
DAG
.
getDataLayout
(
)
)
;
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"unimplemented operation lowering"
)
;
return
SDValue
(
)
;
case
ISD
::
ARRAY_REF
:
return
LowerARRAY_REF
(
Op
,
DAG
)
;
case
ISD
::
STRUCT_REF
:
return
LowerSTRUCT_REF
(
Op
,
DAG
)
;
case
ISD
::
BRCOND
:
return
LowerBRCOND
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
SHL
:
case
ISD
::
SRA
:
case
ISD
::
SRL
:
case
ISD
::
OR
:
case
ISD
::
AND
:
case
ISD
::
XOR
:
case
ISD
::
ADD
:
case
ISD
::
SUB
:
case
ISD
::
MUL
:
case
ISD
::
UDIV
:
case
ISD
::
SDIV
:
case
ISD
::
UREM
:
case
ISD
::
SREM
:
return
LowerBinaryOp
(
Op
,
DAG
)
;
case
ISD
::
LOAD
:
return
LowerLOAD
(
Op
,
DAG
)
;
case
ISD
::
STORE
:
return
LowerSTORE
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
,
PtrVT
)
;
case
ISD
::
ZERO_EXTEND
:
case
ISD
::
SIGN_EXTEND
:
case
ISD
::
ANY_EXTEND
:
case
ISD
::
SIGN_EXTEND_INREG
:
return
LowerEXTEND
(
Op
,
DAG
)
;
case
ISD
::
TRUNCATE
:
return
LowerTRUNCATE
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

JVM
JVM
"unimplemented operation lowering"
ISD::ARRAY_REF
ISD::STRUCT_REF
ISD::BRCOND
ISD::BR_CC
ISD::DYNAMIC_STACKALLOC
ISD::SHL
ISD::SRA
ISD::SRL
ISD::OR
ISD::AND
ISD::XOR
ISD::ADD
ISD::SUB
ISD::MUL
ISD::UDIV
ISD::SDIV
ISD::UREM
ISD::SREM
ISD::LOAD
ISD::STORE
ISD::GlobalAddress
ISD::ZERO_EXTEND
ISD::SIGN_EXTEND
ISD::ANY_EXTEND
ISD::SIGN_EXTEND_INREG
ISD::TRUNCATE


<s> static void rx_get_stack_layout ( unsigned int * lowest , unsigned int * highest , unsigned int * register_mask , unsigned int * frame_size , unsigned int * stack_size ) { unsigned int reg ; unsigned int low ; unsigned int high ; unsigned int fixed_reg = 0 ; unsigned int save_mask ; unsigned int pushed_mask ; unsigned int unneeded_pushes ; if ( is_naked_func ( NULL_TREE ) ) { * lowest = 0 ; * highest = 0 ; * register_mask = 0 ; * frame_size = 0 ; * stack_size = 0 ; return ; } for ( save_mask = high = low = 0 , reg = 1 ; reg < CC_REGNUM ; reg ++ ) { if ( ( df_regs_ever_live_p ( reg ) || ( call_used_regs [ reg ] && is_interrupt_func ( NULL_TREE ) && ! crtl -> is_leaf ) ) && ( ! call_used_regs [ reg ] || is_interrupt_func ( NULL_TREE ) || ( is_fast_interrupt_func ( NULL_TREE ) && ! IN_RANGE ( reg , 10 , 13 ) ) ) ) { if ( low == 0 ) low = reg ; high = reg ; save_mask |= 1 << reg ; } if ( low != 0 && fixed_reg == 0 && fixed_regs [ reg ] ) fixed_reg = reg ; } if ( MUST_SAVE_ACC_REGISTER && bit_count ( save_mask ) < 2 ) { save_mask |= ( 1 << 13 ) | ( 1 << 14 ) ; if ( low == 0 ) low = 13 ; if ( high == 0 || low == high ) high = low + 1 ; } pushed_mask = ( - 1 << low ) & ~ ( - 1 << ( high + 1 ) ) ; unneeded_pushes = ( pushed_mask & ( ~ save_mask ) ) & pushed_mask ; if ( ( fixed_reg && fixed_reg <= high ) || ( optimize_function_for_speed_p ( cfun ) && bit_count ( save_mask ) < bit_count ( unneeded_pushes ) ) ) { * lowest = 0 ; * highest = 0 ; * register_mask = save_mask ; } else { * lowest = low ; * highest = high ; * register_mask = 0 ; } * frame_size = rx_round_up ( get_frame_size ( ) , STACK_BOUNDARY / BITS_PER_UNIT ) ; if ( crtl -> args . size > 0 ) * frame_size += rx_round_up ( crtl -> args . size , STACK_BOUNDARY / BITS_PER_UNIT ) ; * stack_size = rx_round_up ( crtl -> outgoing_args_size , STACK_BOUNDARY / BITS_PER_UNIT ) ; } </s>

Returns either the lowest numbered and highest numbered registers that occupy the call-saved area of the stack frame , if the registers are stored as a contiguous block , or else a bitmask of the individual registers if they are stored piecemeal . Also computes the size of the frame and the size of the outgoing arguments block ( in bytes ) .


<s> bool SystemZTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( AM . BaseGV ) return false ; if ( ! isInt < 20 > ( AM . BaseOffs ) ) return false ; bool RequireD12 = Subtarget . hasVector ( ) && Ty -> isVectorTy ( ) ; AddressingMode SupportedAM ( ! RequireD12 , true ) ; if ( I != nullptr ) SupportedAM = supportedAddressingMode ( I , Subtarget . hasVector ( ) ) ; if ( ! SupportedAM . LongDisplacement && ! isUInt < 12 > ( AM . BaseOffs ) ) return false ; if ( ! SupportedAM . IndexReg ) return AM . Scale == 0 ; else return AM . Scale == 0 || AM . Scale == 1 ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM ) , OL ) , TargetABI ( computeTargetABI ( TT , CPU , Options ) ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) { if ( isTargetHardFloat ( ) ) this -> Options . FloatABIType = FloatABI :: Hard ; else this -> Options . FloatABIType = FloatABI :: Soft ; } if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( ( TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABI || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF ) && ! ( TargetTriple . isOSWindows ( ) || TargetTriple . isOSDarwin ( ) ) ) this -> Options . EABIVersion = EABI :: GNU ; else this -> Options . EABIVersion = EABI :: EABI5 ; } if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } initAsmInfo ( ) ; } </s>


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
Teak
::
NumTargetFixupKinds
]
=
{
{
"fixup_teak_call_imm18"
,
0
,
18
,
0
}
,
{
"fixup_teak_rel7"
,
0
,
7
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_teak_ptr_imm16"
,
0
,
16
,
0
}
,
{
"fixup_teak_bkrep_reg"
,
0
,
18
,
0
}
,
{
"fixup_teak_bkrep_r6"
,
0
,
18
,
0
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> void AVRAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { AVRMCInstLower MCInstLowering ( OutContext , * this ) ; MCInst I ; MCInstLowering . lowerInstruction ( * MI , I ) ; EmitToStreamer ( * OutStreamer , I ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


"frame pointer should not have been eliminated"


<s> bool Warning ( SMLoc L , const Twine & Msg , ArrayRef < SMRange > Ranges = None ) { return getParser ( ) . Warning ( L , Msg , Ranges ) ; } </s>

Emit a warning at the location L , with the message Msg .


"LOAD_STACK_GUARD currently supported only for MachO."

This function is called for all pseudo instructions that remain after register allocation .


"CFProtection used on invalid architecture!"

This virtual method can be overridden by targets that want to emit something at the start of their file .


<s> void arc_print_operand_address ( FILE * file , rtx addr ) { register rtx base , index = 0 ; int offset = 0 ; switch ( GET_CODE ( addr ) ) { case REG : fputs ( reg_names [ REGNO ( addr ) ] , file ) ; break ; case SYMBOL_REF : if ( 0 && SYMBOL_REF_FUNCTION_P ( addr ) ) { fprintf ( file , "%%st(" ) ; output_addr_const ( file , addr ) ; fprintf ( file , ")" ) ; } else output_addr_const ( file , addr ) ; break ; case PLUS : if ( GET_CODE ( XEXP ( addr , 0 ) ) == CONST_INT ) offset = INTVAL ( XEXP ( addr , 0 ) ) , base = XEXP ( addr , 1 ) ; else if ( GET_CODE ( XEXP ( addr , 1 ) ) == CONST_INT ) offset = INTVAL ( XEXP ( addr , 1 ) ) , base = XEXP ( addr , 0 ) ; else base = XEXP ( addr , 0 ) , index = XEXP ( addr , 1 ) ; gcc_assert ( GET_CODE ( base ) == REG ) ; fputs ( reg_names [ REGNO ( base ) ] , file ) ; if ( index == 0 ) { if ( offset != 0 ) fprintf ( file , ",%d" , offset ) ; } else { switch ( GET_CODE ( index ) ) { case REG : fprintf ( file , ",%s" , reg_names [ REGNO ( index ) ] ) ; break ; case SYMBOL_REF : fputc ( ',' , file ) , output_addr_const ( file , index ) ; break ; default : gcc_unreachable ( ) ; } } break ; case PRE_INC : case PRE_DEC : gcc_unreachable ( ) ; break ; default : output_addr_const ( file , addr ) ; break ; } } </s>

Print a memory address as an operand to reference that memory location .


<s>
bool
SIInstrInfo
::
isInlineConstant
(
const
MachineOperand
&
MO
,
uint8_t
OperandType
)
const
{
if
(
!
MO
.
isImm
(
)
||
OperandType
<
AMDGPU
::
OPERAND_SRC_FIRST
||
OperandType
>
AMDGPU
::
OPERAND_SRC_LAST
)
return
false
;
int64_t
Imm
=
MO
.
getImm
(
)
;
switch
(
OperandType
)
{
case
AMDGPU
::
OPERAND_REG_IMM_INT32
:
case
AMDGPU
::
OPERAND_REG_IMM_FP32
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_INT32
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_FP32
:
{
int32_t
Trunc
=
static_cast
<
int32_t
>
(
Imm
)
;
return
AMDGPU
::
isInlinableLiteral32
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
case
AMDGPU
::
OPERAND_REG_IMM_INT64
:
case
AMDGPU
::
OPERAND_REG_IMM_FP64
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_INT64
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_FP64
:
return
AMDGPU
::
isInlinableLiteral64
(
MO
.
getImm
(
)
,
ST
.
hasInv2PiInlineImm
(
)
)
;
case
AMDGPU
::
OPERAND_REG_IMM_INT16
:
case
AMDGPU
::
OPERAND_REG_IMM_FP16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_INT16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_FP16
:
{
if
(
isInt
<
16
>
(
Imm
)
||
isUInt
<
16
>
(
Imm
)
)
{
int16_t
Trunc
=
static_cast
<
int16_t
>
(
Imm
)
;
return
ST
.
has16BitInsts
(
)
&&
AMDGPU
::
isInlinableLiteral16
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
return
false
;
}
case
AMDGPU
::
OPERAND_REG_IMM_V2INT16
:
case
AMDGPU
::
OPERAND_REG_IMM_V2FP16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_V2INT16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_V2FP16
:
{
uint32_t
Trunc
=
static_cast
<
uint32_t
>
(
Imm
)
;
return
AMDGPU
::
isInlinableLiteralV216
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
default
:
llvm_unreachable
(
"invalid bitwidth"
)
;
}
}
</s>

returns true if the operand OpIdx in MI is a valid inline immediate .


<s> const DataLayout * getDataLayout ( ) const override { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> static int h8300_rtx_ok_for_base_p ( rtx x , int strict ) { if ( GET_CODE ( x ) == SUBREG ) x = SUBREG_REG ( x ) ; return ( REG_P ( x ) && ( strict ? REG_OK_FOR_BASE_STRICT_P ( x ) : REG_OK_FOR_BASE_NONSTRICT_P ( x ) ) ) ; } </s>

Return nonzero if X is a REG or SUBREG suitable as a base register .


<s> void arc_clear_unalign ( void ) { if ( cfun ) cfun -> machine -> unalign = 0 ; } </s>

Accessor functions for cfun- > machine- > unalign .


<s> bool X86TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( VT . getSizeInBits ( ) == 64 ) return false ; return ( VT . getVectorNumElements ( ) == 2 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isMOVLMask ( M , VT ) || isSHUFPMask ( M , VT , Subtarget -> hasFp256 ( ) ) || isPSHUFDMask ( M , VT ) || isPSHUFHWMask ( M , VT , Subtarget -> hasInt256 ( ) ) || isPSHUFLWMask ( M , VT , Subtarget -> hasInt256 ( ) ) || isPALIGNRMask ( M , VT , Subtarget ) || isUNPCKLMask ( M , VT , Subtarget -> hasInt256 ( ) ) || isUNPCKHMask ( M , VT , Subtarget -> hasInt256 ( ) ) || isUNPCKL_v_undef_Mask ( M , VT , Subtarget -> hasInt256 ( ) ) || isUNPCKH_v_undef_Mask ( M , VT , Subtarget -> hasInt256 ( ) ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> static rtx ix86_expand_sse_fabs ( rtx op0 , rtx * smask ) { machine_mode vmode , mode = GET_MODE ( op0 ) ; rtx xa , mask ; xa = gen_reg_rtx ( mode ) ; if ( mode == SFmode ) vmode = V4SFmode ; else if ( mode == DFmode ) vmode = V2DFmode ; else vmode = mode ; mask = ix86_build_signbit_mask ( vmode , VECTOR_MODE_P ( mode ) , true ) ; if ( ! VECTOR_MODE_P ( mode ) ) { rtx tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 1 , const0_rtx ) ) ; tmp = gen_rtx_VEC_SELECT ( mode , mask , tmp ) ; mask = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , mask , tmp ) ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , xa , gen_rtx_AND ( mode , op0 , mask ) ) ) ; if ( smask ) * smask = mask ; return xa ; } </s>

Expand fabs ( OP0 ) and return a new rtx that holds the result . The mask for masking out the sign-bit is stored in * SMASK , if that is non-null .


<s> const SystemZSubtarget * SystemZTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool softFloat = F . hasFnAttribute ( "use-soft-float" ) && F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( softFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < SystemZSubtarget > ( TargetTriple , CPU , FS , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

SystemZ SystemZ SystemZ "target-cpu" "target-features" "use-soft-float" "use-soft-float" "true" "+soft-float" ",+soft-float" SystemZ


<s> unsigned xlogue_layout :: count_stub_managed_regs ( ) { bool hfp = frame_pointer_needed || stack_realign_fp ; unsigned i , count ; unsigned regno ; for ( count = i = MIN_REGS ; i < MAX_REGS ; ++ i ) { regno = REG_ORDER [ i ] ; if ( regno == BP_REG && hfp ) continue ; if ( ! ix86_save_reg ( regno , false , false ) ) break ; ++ count ; } return count ; } </s>

Determine how many clobbered registers can be saved by the stub . Returns the count of registers the stub will save and restore .


<s> SDValue AArch64SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; ConstantSDNode * SizeValue = dyn_cast < ConstantSDNode > ( Size ) ; const AArch64Subtarget & STI = DAG . getMachineFunction ( ) . getSubtarget < AArch64Subtarget > ( ) ; const char * bzeroName = ( V && V -> isNullValue ( ) ) ? DAG . getTargetLoweringInfo ( ) . getLibcallName ( RTLIB :: BZERO ) : nullptr ; if ( bzeroName && ( ! SizeValue || SizeValue -> getZExtValue ( ) > 256 ) ) { const AArch64TargetLowering & TLI = * STI . getTargetLowering ( ) ; Type * IntPtrTy = Type :: getInt8PtrTy ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalFunctionSymbol ( bzeroName ) , std :: move ( Args ) ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memset .


<s> avr_regno_mode_code_ok_for_base_p ( num , mode , as , outer_code , index_code ) { ARG_POINTER_REGNUM , STACK_POINTER_REGNUM } , \ { ARG_POINTER_REGNUM , FRAME_POINTER_REGNUM } , \ { FRAME_POINTER_REGNUM , STACK_POINTER_REGNUM } , \ { FRAME_POINTER_REGNUM + 1 , STACK_POINTER_REGNUM + 1 } </s>

Implement ` REGNO_MODE_CODE_OK_FOR_BASE_P ' .


<s> unsigned HexagonTTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * DataTy , Value * Ptr , bool VariableMask , unsigned Alignment , TTI :: TargetCostKind CostKind , const Instruction * I ) { return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , CostKind , I ) ; } </s>

Calculate the cost of Gather / Scatter operation .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s> void Mips16TargetLowering :: getOpndList ( SmallVectorImpl < SDValue > & Ops , std :: deque < std :: pair < unsigned , SDValue > > & RegsToPass , bool IsPICCall , bool GlobalOrExternal , bool InternalLinkage , CallLoweringInfo & CLI , SDValue Callee , SDValue Chain ) const { SelectionDAG & DAG = CLI . DAG ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MipsFunctionInfo * FuncInfo = MF . getInfo < MipsFunctionInfo > ( ) ; const char * Mips16HelperFunction = 0 ; bool NeedMips16Helper = false ; if ( getTargetMachine ( ) . Options . UseSoftFloat && Subtarget -> inMips16HardFloat ( ) ) { bool LookupHelper = true ; if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( CLI . Callee ) ) { Mips16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , S -> getSymbol ( ) } ; if ( std :: binary_search ( HardFloatLibCalls , array_endof ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; else { Mips16IntrinsicHelperType IntrinsicFind = { S -> getSymbol ( ) , "" } ; if ( std :: binary_search ( Mips16IntrinsicHelper , array_endof ( Mips16IntrinsicHelper ) , IntrinsicFind ) ) { const Mips16IntrinsicHelperType * h = ( std :: find ( Mips16IntrinsicHelper , array_endof ( Mips16IntrinsicHelper ) , IntrinsicFind ) ) ; Mips16HelperFunction = h -> Helper ; NeedMips16Helper = true ; LookupHelper = false ; } } } else if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( CLI . Callee ) ) { Mips16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , G -> getGlobal ( ) -> getName ( ) . data ( ) } ; if ( std :: binary_search ( HardFloatLibCalls , array_endof ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; } if ( LookupHelper ) Mips16HelperFunction = getMips16HelperFunction ( CLI . RetTy , CLI . Args , NeedMips16Helper ) ; } SDValue JumpTarget = Callee ; if ( IsPICCall || ! GlobalOrExternal ) { unsigned V0Reg = Mips :: V0 ; if ( NeedMips16Helper ) { RegsToPass . push_front ( std :: make_pair ( V0Reg , Callee ) ) ; JumpTarget = DAG . getExternalSymbol ( Mips16HelperFunction , getPointerTy ( ) ) ; ExternalSymbolSDNode * S = cast < ExternalSymbolSDNode > ( JumpTarget ) ; JumpTarget = getAddrGlobal ( S , JumpTarget . getValueType ( ) , DAG , MipsII :: MO_GOT , Chain , FuncInfo -> callPtrInfo ( S -> getSymbol ( ) ) ) ; } else RegsToPass . push_front ( std :: make_pair ( ( unsigned ) Mips :: T9 , Callee ) ) ; } Ops . push_back ( JumpTarget ) ; MipsTargetLowering :: getOpndList ( Ops , RegsToPass , IsPICCall , GlobalOrExternal , InternalLinkage , CLI , Callee , Chain ) ; } </s>

This function fills Ops , which is the list of operands that will later be used when a function call node is created .

Mips Mips Mips Mips Mips 0 Mips Mips Mips Mips "" Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips::V0 Mips Mips MipsII::MO_GOT Mips::T9 Mips


Provide a fast substitute to std : :swap < Use > that also works with less standard-compliant compilers .


<s> virtual void initializePass ( ) override { pushTTIStack ( this ) ; } </s>

initializePass - This method may be overriden by immutable passes to allow them to perform various initialization actions they require .


<s> static void nios2_set_current_function ( tree fndecl ) { tree old_tree = ( nios2_previous_fndecl ? DECL_FUNCTION_SPECIFIC_TARGET ( nios2_previous_fndecl ) : NULL_TREE ) ; tree new_tree = ( fndecl ? DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) : NULL_TREE ) ; if ( fndecl && fndecl != nios2_previous_fndecl ) { nios2_previous_fndecl = fndecl ; if ( old_tree == new_tree ) ; else if ( new_tree ) { cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( new_tree ) ) ; target_reinit ( ) ; } else if ( old_tree ) { struct cl_target_option * def = TREE_TARGET_OPTION ( target_option_current_node ) ; cl_target_option_restore ( & global_options , & global_options_set , def ) ; target_reinit ( ) ; } } } </s>

Establish appropriate back-end context for processing the function FNDECL . The argument might be NULL to indicate processing at top level , outside of any function scope .


"SGPR spill should have been removed in SILowerSGPRSpills"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> static rtx rs6000_emit_stack_reset ( rtx frame_reg_rtx , HOST_WIDE_INT frame_off , unsigned updt_regno ) { if ( frame_off == 0 && REGNO ( frame_reg_rtx ) == updt_regno ) return NULL_RTX ; rtx updt_reg_rtx = gen_rtx_REG ( Pmode , updt_regno ) ; if ( DEFAULT_ABI == ABI_V4 ) return emit_insn ( gen_stack_restore_tie ( updt_reg_rtx , frame_reg_rtx , GEN_INT ( frame_off ) ) ) ; if ( frame_off != 0 ) return emit_insn ( gen_add3_insn ( updt_reg_rtx , frame_reg_rtx , GEN_INT ( frame_off ) ) ) ; else return emit_move_insn ( updt_reg_rtx , frame_reg_rtx ) ; return NULL_RTX ; } </s>

Emit a sequence of insns , including a stack tie if needed , for resetting the stack pointer . If UPDT_REGNO is not 1 , then do n't reset the stack pointer , but move the base of the frame into reg UPDT_REGNO for use by out-of-line register restore routines .


Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineFunctionAnalysis > ( ) ; AU . addPreserved < MachineFunctionAnalysis > ( ) ; AU . addPreserved < StackProtector > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> rtx rs6000_allocate_stack_temp ( machine_mode mode , bool offsettable_p , bool reg_reg_p ) { rtx stack = assign_stack_temp ( mode , GET_MODE_SIZE ( mode ) ) ; rtx addr = XEXP ( stack , 0 ) ; int strict_p = reload_completed ; if ( ! legitimate_indirect_address_p ( addr , strict_p ) ) { if ( offsettable_p && ! rs6000_legitimate_offset_address_p ( mode , addr , strict_p , true ) ) stack = replace_equiv_address ( stack , copy_addr_to_reg ( addr ) ) ; else if ( reg_reg_p && ! legitimate_indexed_address_p ( addr , strict_p ) ) stack = replace_equiv_address ( stack , copy_addr_to_reg ( addr ) ) ; } return stack ; } </s>

Allocate a stack temp and fixup the address so it meets the particular memory requirements ( either offetable or REG+REG addressing ) .


<s> void tilegx_expand_builtin_vector_binop ( rtx ( * gen ) ( rtx , rtx , rtx ) , machine_mode dest_mode , rtx dest , machine_mode src_mode , rtx src0 , rtx src1 , bool do_src1 ) { dest = gen_lowpart ( dest_mode , dest ) ; if ( src0 == const0_rtx ) src0 = CONST0_RTX ( src_mode ) ; else src0 = gen_lowpart ( src_mode , src0 ) ; if ( do_src1 ) { if ( src1 == const0_rtx ) src1 = CONST0_RTX ( src_mode ) ; else src1 = gen_lowpart ( src_mode , src1 ) ; } emit_insn ( ( * gen ) ( dest , src0 , src1 ) ) ; } </s>

Expand a builtin vector binary op , by calling gen function GEN with operands in the proper modes . DEST is converted to DEST_MODE , and src0 and src1 ( if DO_SRC1 is true ) is converted to SRC_MODE .


<s> bool ARMTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty ) const { EVT VT = getValueType ( Ty , true ) ; if ( ! isLegalAddressImmediate ( AM . BaseOffs , VT , Subtarget ) ) return false ; if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( Subtarget -> isThumb1Only ( ) ) return false ; default : if ( AM . BaseOffs ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( Subtarget -> isThumb2 ( ) ) return isLegalT2ScaledAddressingMode ( AM , VT ) ; int Scale = AM . Scale ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case MVT :: i1 : case MVT :: i8 : case MVT :: i32 : if ( Scale < 0 ) Scale = - Scale ; if ( Scale == 1 ) return true ; return isPowerOf2_32 ( Scale & ~ 1 ) ; case MVT :: i16 : case MVT :: i64 : if ( ( ( unsigned ) AM . HasBaseReg + Scale ) <= 2 ) return true ; return false ; case MVT :: isVoid : if ( Scale & 1 ) return false ; return isPowerOf2_32 ( Scale ) ; } break ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> bool RISCVInstrInfo :: getMemOperandWithOffsetWidth ( const MachineInstr & LdSt , const MachineOperand * & BaseReg , int64_t & Offset , unsigned & Width , const TargetRegisterInfo * TRI ) const { if ( ! LdSt . mayLoadOrStore ( ) ) return false ; if ( LdSt . getNumExplicitOperands ( ) != 3 ) return false ; if ( ! LdSt . getOperand ( 1 ) . isReg ( ) || ! LdSt . getOperand ( 2 ) . isImm ( ) ) return false ; if ( ! LdSt . hasOneMemOperand ( ) ) return false ; Width = ( * LdSt . memoperands_begin ( ) ) -> getSize ( ) ; BaseReg = & LdSt . getOperand ( 1 ) ; Offset = LdSt . getOperand ( 2 ) . getImm ( ) ; return true ; } </s>

Return true if get the base operand , byte offset of an instruction and the memory width .


"SIInstrInfo::storeRegToStackSlot - Do not know how to"

Store the specified register of the given register class to the specified stack frame index .


<s> unsigned HexagonInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case Hexagon :: S2_storerb_io : case Hexagon :: S2_storerh_io : case Hexagon :: S2_storeri_io : case Hexagon :: S2_storerd_io : case Hexagon :: V6_vS32b_ai : case Hexagon :: V6_vS32b_ai_128B : case Hexagon :: V6_vS32Ub_ai : case Hexagon :: V6_vS32Ub_ai_128B : case Hexagon :: STriw_pred : case Hexagon :: STriw_mod : case Hexagon :: PS_vstorerq_ai : case Hexagon :: PS_vstorerw_ai : case Hexagon :: PS_vstorerq_ai_128B : case Hexagon :: PS_vstorerw_ai_128B : { const MachineOperand & OpFI = MI . getOperand ( 0 ) ; if ( ! OpFI . isFI ( ) ) return 0 ; const MachineOperand & OpOff = MI . getOperand ( 1 ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != 0 ) return 0 ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( 2 ) . getReg ( ) ; } case Hexagon :: S2_pstorerbt_io : case Hexagon :: S2_pstorerbf_io : case Hexagon :: S2_pstorerht_io : case Hexagon :: S2_pstorerhf_io : case Hexagon :: S2_pstorerit_io : case Hexagon :: S2_pstorerif_io : case Hexagon :: S2_pstorerdt_io : case Hexagon :: S2_pstorerdf_io : { const MachineOperand & OpFI = MI . getOperand ( 1 ) ; if ( ! OpFI . isFI ( ) ) return 0 ; const MachineOperand & OpOff = MI . getOperand ( 2 ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != 0 ) return 0 ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( 3 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> BPFSubtarget & BPFSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { initializeEnvironment ( ) ; initSubtargetFeatures ( CPU , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> static Register buildLoad ( SPIRVType * BaseType , Register PtrVReg , MachineIRBuilder & MIRBuilder , SPIRVGlobalRegistry * GR , LLT llt , Register dstReg = Register ( 0 ) ) { const auto MRI = MIRBuilder . getMRI ( ) ; if ( ! dstReg . isValid ( ) ) { dstReg = MRI -> createVirtualRegister ( & SPIRV :: IDRegClass ) ; MRI -> setType ( dstReg , LLT :: scalar ( 32 ) ) ; GR -> assignSPIRVTypeToVReg ( BaseType , dstReg , MIRBuilder . getMF ( ) ) ; } auto PtrInfo = MachinePointerInfo ( ) ; MIRBuilder . buildLoad ( dstReg , PtrVReg , PtrInfo , Align ( ) ) ; return dstReg ; } </s>

Build and insert a G_LOAD instruction , while constructing the MachineMemOperand .

SPIRV SPIRV SPIRV 0 SPIRV::IDRegClass 32 SPIRV


<s>
ScheduleHazardRecognizer
::
HazardType
PPCHazardRecognizer970
::
getHazardType
(
SUnit
*
SU
)
{
const
SDNode
*
Node
=
SU
->
getNode
(
)
->
getFlaggedMachineNode
(
)
;
bool
isFirst
,
isSingle
,
isCracked
,
isLoad
,
isStore
;
PPCII
::
PPC970_Unit
InstrType
=
GetInstrType
(
Node
->
getOpcode
(
)
,
isFirst
,
isSingle
,
isCracked
,
isLoad
,
isStore
)
;
if
(
InstrType
==
PPCII
::
PPC970_Pseudo
)
return
NoHazard
;
unsigned
Opcode
=
Node
->
getMachineOpcode
(
)
;
if
(
NumIssued
!=
0
&&
(
isFirst
||
isSingle
)
)
return
Hazard
;
if
(
isCracked
&&
NumIssued
>
2
)
return
Hazard
;
switch
(
InstrType
)
{
default
:
assert
(
0
&&
"Unknown instruction type!"
)
;
case
PPCII
::
PPC970_FXU
:
case
PPCII
::
PPC970_LSU
:
case
PPCII
::
PPC970_FPU
:
case
PPCII
::
PPC970_VALU
:
case
PPCII
::
PPC970_VPERM
:
if
(
NumIssued
==
4
)
return
Hazard
;
break
;
case
PPCII
::
PPC970_CRU
:
if
(
NumIssued
>=
2
)
return
Hazard
;
break
;
case
PPCII
::
PPC970_BRU
:
break
;
}
if
(
HasCTRSet
&&
(
Opcode
==
PPC
::
BCTRL_Macho
||
Opcode
==
PPC
::
BCTRL_ELF
)
)
return
NoopHazard
;
if
(
isLoad
&&
NumStores
)
{
unsigned
LoadSize
;
switch
(
Opcode
)
{
default
:
assert
(
0
&&
"Unknown load!"
)
;
case
PPC
::
LBZ
:
case
PPC
::
LBZU
:
case
PPC
::
LBZX
:
case
PPC
::
LBZ8
:
case
PPC
::
LBZU8
:
case
PPC
::
LBZX8
:
case
PPC
::
LVEBX
:
LoadSize
=
1
;
break
;
case
PPC
::
LHA
:
case
PPC
::
LHAU
:
case
PPC
::
LHAX
:
case
PPC
::
LHZ
:
case
PPC
::
LHZU
:
case
PPC
::
LHZX
:
case
PPC
::
LVEHX
:
case
PPC
::
LHBRX
:
case
PPC
::
LHA8
:
case
PPC
::
LHAU8
:
case
PPC
::
LHAX8
:
case
PPC
::
LHZ8
:
case
PPC
::
LHZU8
:
case
PPC
::
LHZX8
:
LoadSize
=
2
;
break
;
case
PPC
::
LFS
:
case
PPC
::
LFSU
:
case
PPC
::
LFSX
:
case
PPC
::
LWZ
:
case
PPC
::
LWZU
:
case
PPC
::
LWZX
:
case
PPC
::
LWA
:
case
PPC
::
LWAX
:
case
PPC
::
LVEWX
:
case
PPC
::
LWBRX
:
case
PPC
::
LWZ8
:
case
PPC
::
LWZX8
:
LoadSize
=
4
;
break
;
case
PPC
::
LFD
:
case
PPC
::
LFDU
:
case
PPC
::
LFDX
:
case
PPC
::
LD
:
case
PPC
::
LDU
:
case
PPC
::
LDX
:
LoadSize
=
8
;
break
;
case
PPC
::
LVX
:
case
PPC
::
LVXL
:
LoadSize
=
16
;
break
;
}
if
(
isLoadOfStoredAddress
(
LoadSize
,
Node
->
getOperand
(
0
)
,
Node
->
getOperand
(
1
)
)
)
return
NoopHazard
;
}
return
NoHazard
;
}
</s>

getHazardType - Return the hazard type of emitting this node .


<s> bool RISCVMCExpr :: evaluateAsConstant ( int64_t & Res ) const { MCValue Value ; if ( Kind == VK_RISCV_PCREL_HI || Kind == VK_RISCV_PCREL_LO || Kind == VK_RISCV_CALL ) return false ; if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ) return false ; if ( ! Value . isAbsolute ( ) ) return false ; Res = evaluateAsInt64 ( Value . getConstant ( ) ) ; return true ; } </s>

Evaluates the fixup as a constant value .


<s> bool SIInstrInfo :: isLegalRegOperand ( const MachineRegisterInfo & MRI , const MCOperandInfo & OpInfo , const MachineOperand & MO ) const { if ( ! MO . isReg ( ) ) return false ; Register Reg = MO . getReg ( ) ; const TargetRegisterClass * RC = Register :: isVirtualRegister ( Reg ) ? MRI . getRegClass ( Reg ) : RI . getPhysRegClass ( Reg ) ; const SIRegisterInfo * TRI = static_cast < const SIRegisterInfo * > ( MRI . getTargetRegisterInfo ( ) ) ; RC = TRI -> getSubRegClass ( RC , MO . getSubReg ( ) ) ; return RI . getCommonSubClass ( RC , RI . getRegClass ( OpInfo . RegClass ) ) == RC ; } </s>

Check if MO ( a register operand ) is a legal register for the given operand description .


<s> void ELFAArch64AsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { if ( ! IsLittleEndian && Fixup . getKind ( ) == FK_Data_4 ) { const MCSection * Sec = Fixup . getValue ( ) -> FindAssociatedSection ( ) ; const MCSectionELF * SecELF = dyn_cast_or_null < const MCSectionELF > ( Sec ) ; if ( SecELF && SecELF -> getSectionName ( ) == ".eh_frame" ) Value = ByteSwap_32 ( unsigned ( Value ) ) ; } AArch64AsmBackend :: applyFixup ( Fixup , Data , DataSize , Value , IsPCRel ) ; } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> int mcore_expand_insv ( rtx operands [ ] ) { int width = INTVAL ( operands [ 1 ] ) ; int posn = INTVAL ( operands [ 2 ] ) ; int mask ; rtx mreg , sreg , ereg ; if ( width == 1 && GET_CODE ( operands [ 3 ] ) == CONST_INT ) { if ( ( INTVAL ( operands [ 3 ] ) & 1 ) == 0 ) { mask = ~ ( 1 << posn ) ; emit_insn ( gen_rtx_SET ( SImode , operands [ 0 ] , gen_rtx_AND ( SImode , operands [ 0 ] , GEN_INT ( mask ) ) ) ) ; } else { mask = 1 << posn ; emit_insn ( gen_rtx_SET ( SImode , operands [ 0 ] , gen_rtx_IOR ( SImode , operands [ 0 ] , GEN_INT ( mask ) ) ) ) ; } return 1 ; } if ( ! TARGET_W_FIELD ) return 0 ; if ( width == 8 && posn % 8 == 0 ) return 0 ; if ( width == 16 && posn % 16 == 0 ) return 0 ; if ( GET_CODE ( operands [ 3 ] ) == CONST_INT && INTVAL ( operands [ 3 ] ) == ( ( 1 << width ) - 1 ) ) { mreg = force_reg ( SImode , GEN_INT ( INTVAL ( operands [ 3 ] ) << posn ) ) ; emit_insn ( gen_rtx_SET ( SImode , operands [ 0 ] , gen_rtx_IOR ( SImode , operands [ 0 ] , mreg ) ) ) ; return 1 ; } mreg = force_reg ( SImode , GEN_INT ( ~ ( ( ( 1 << width ) - 1 ) << posn ) ) ) ; emit_insn ( gen_rtx_SET ( SImode , operands [ 0 ] , gen_rtx_AND ( SImode , operands [ 0 ] , mreg ) ) ) ; if ( GET_CODE ( operands [ 3 ] ) == CONST_INT && INTVAL ( operands [ 3 ] ) == 0 ) return 1 ; sreg = copy_to_mode_reg ( SImode , operands [ 3 ] ) ; if ( width + posn != ( int ) GET_MODE_SIZE ( SImode ) ) { ereg = force_reg ( SImode , GEN_INT ( ( 1 << width ) - 1 ) ) ; emit_insn ( gen_rtx_SET ( SImode , sreg , gen_rtx_AND ( SImode , sreg , ereg ) ) ) ; } if ( posn != 0 ) emit_insn ( gen_rtx_SET ( SImode , sreg , gen_rtx_ASHIFT ( SImode , sreg , GEN_INT ( posn ) ) ) ) ; emit_insn ( gen_rtx_SET ( SImode , operands [ 0 ] , gen_rtx_IOR ( SImode , operands [ 0 ] , sreg ) ) ) ; return 1 ; } </s>


<s>
const
char
*
getPassName
(
)
const
override
{
return
"AMDGPU Promote Alloca"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool MSP430AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) return AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , O ) ; printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s>
const
MCPhysReg
*
X86RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"MachineFunction required"
)
;
const
X86Subtarget
&
Subtarget
=
MF
->
getSubtarget
<
X86Subtarget
>
(
)
;
const
Function
&
F
=
MF
->
getFunction
(
)
;
bool
HasSSE
=
Subtarget
.
hasSSE1
(
)
;
bool
HasAVX
=
Subtarget
.
hasAVX
(
)
;
bool
HasAVX512
=
Subtarget
.
hasAVX512
(
)
;
bool
CallsEHReturn
=
MF
->
callsEHReturn
(
)
;
CallingConv
::
ID
CC
=
F
.
getCallingConv
(
)
;
if
(
MF
->
getFunction
(
)
.
hasFnAttribute
(
"no_caller_saved_registers"
)
)
CC
=
CallingConv
::
X86_INTR
;
switch
(
CC
)
{
case
CallingConv
::
GHC
:
case
CallingConv
::
HiPE
:
return
CSR_NoRegs_SaveList
;
case
CallingConv
::
AnyReg
:
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
return
CSR_64_AllRegs_SaveList
;
case
CallingConv
::
PreserveMost
:
return
CSR_64_RT_MostRegs_SaveList
;
case
CallingConv
::
PreserveAll
:
if
(
HasAVX
)
return
CSR_64_RT_AllRegs_AVX_SaveList
;
return
CSR_64_RT_AllRegs_SaveList
;
case
CallingConv
::
CXX_FAST_TLS
:
if
(
Is64Bit
)
return
MF
->
getInfo
<
X86MachineFunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_64_CXX_TLS_Darwin_PE_SaveList
:
CSR_64_TLS_Darwin_SaveList
;
break
;
case
CallingConv
::
Intel_OCL_BI
:
{
if
(
HasAVX512
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX512
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX_SaveList
;
if
(
HasAVX
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX_SaveList
;
if
(
!
HasAVX
&&
!
IsWin64
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_SaveList
;
break
;
}
case
CallingConv
::
HHVM
:
return
CSR_64_HHVM_SaveList
;
case
CallingConv
::
X86_RegCall
:
if
(
Is64Bit
)
{
if
(
IsWin64
)
{
return
(
HasSSE
CSR_Win64_RegCall_SaveList
:
CSR_Win64_RegCall_NoSSE_SaveList
)
;
}
else
{
return
(
HasSSE
CSR_SysV64_RegCall_SaveList
:
CSR_SysV64_RegCall_NoSSE_SaveList
)
;
}
}
else
{
return
(
HasSSE
CSR_32_RegCall_SaveList
:
CSR_32_RegCall_NoSSE_SaveList
)
;
}
case
CallingConv
::
Cold
:
if
(
Is64Bit
)
return
CSR_64_MostRegs_SaveList
;
break
;
case
CallingConv
::
Win64
:
if
(
!
HasSSE
)
return
CSR_Win64_NoSSE_SaveList
;
return
CSR_Win64_SaveList
;
case
CallingConv
::
X86_64_SysV
:
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
case
CallingConv
::
X86_INTR
:
if
(
Is64Bit
)
{
if
(
HasAVX512
)
return
CSR_64_AllRegs_AVX512_SaveList
;
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
if
(
HasSSE
)
return
CSR_64_AllRegs_SaveList
;
return
CSR_64_AllRegs_NoSSE_SaveList
;
}
else
{
if
(
HasAVX512
)
return
CSR_32_AllRegs_AVX512_SaveList
;
if
(
HasAVX
)
return
CSR_32_AllRegs_AVX_SaveList
;
if
(
HasSSE
)
return
CSR_32_AllRegs_SSE_SaveList
;
return
CSR_32_AllRegs_SaveList
;
}
default
:
break
;
}
if
(
Is64Bit
)
{
bool
IsSwiftCC
=
Subtarget
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
F
.
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
;
if
(
IsSwiftCC
)
return
IsWin64
CSR_Win64_SwiftError_SaveList
:
CSR_64_SwiftError_SaveList
;
if
(
IsWin64
)
return
HasSSE
CSR_Win64_SaveList
:
CSR_Win64_NoSSE_SaveList
;
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
}
return
CallsEHReturn
CSR_32EHRet_SaveList
:
CSR_32_SaveList
;
}
</s>


<s> static void c6x_mark_reg_written ( rtx reg , int cycles ) { unsigned regno = REGNO ( reg ) ; unsigned nregs = hard_regno_nregs [ regno ] [ GET_MODE ( reg ) ] ; while ( nregs -- > 0 ) ss . reg_set_in_cycle [ regno + nregs ] = cycles ; } </s>

Note that register REG is written in cycle CYCLES .


"Frame indices can only appear as the first "

"operand of a DBG_VALUE machine instruction"

runOnMachineFunction - Emit the function body .


<s> bool evaluateBranch ( MCInst const & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { if ( ! ( isCall ( Inst ) || isUnconditionalBranch ( Inst ) || isConditionalBranch ( Inst ) ) ) return false ; if ( ! HexagonMCInstrInfo :: isExtendable ( * Info , Inst ) ) return false ; auto const & Extended ( HexagonMCInstrInfo :: getExtendableOperand ( * Info , Inst ) ) ; assert ( Extended . isExpr ( ) ) ; int64_t Value ; if ( ! Extended . getExpr ( ) -> evaluateAsAbsolute ( Value ) ) return false ; Target = Value ; return true ; } </s>

Given a branch instruction try to get the address the branch targets .


<s>
bool
MipsCodeEmitter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MipsTargetMachine
&
Target
=
static_cast
<
MipsTargetMachine
&
>
(
const_cast
<
TargetMachine
&
>
(
MF
.
getTarget
(
)
)
)
;
JTI
=
Target
.
getJITInfo
(
)
;
II
=
Target
.
getInstrInfo
(
)
;
TD
=
Target
.
getDataLayout
(
)
;
Subtarget
=
&
TM
.
getSubtarget
<
MipsSubtarget
>
(
)
;
MCPEs
=
&
MF
.
getConstantPool
(
)
->
getConstants
(
)
;
MJTEs
=
0
;
if
(
MF
.
getJumpTableInfo
(
)
)
MJTEs
=
&
MF
.
getJumpTableInfo
(
)
->
getJumpTables
(
)
;
JTI
->
Initialize
(
MF
,
IsPIC
,
Subtarget
->
isLittle
(
)
)
;
MCE
.
setModuleInfo
(
&
getAnalysis
<
MachineModuleInfo
>
(
)
)
;
do
{
DEBUG
(
errs
(
)
<<
"JITTing function '"
<<
MF
.
getName
(
)
<<
"'\n"
)
;
MCE
.
startFunction
(
MF
)
;
for
(
MachineFunction
::
iterator
MBB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBB
!=
E
;
++
MBB
)
{
MCE
.
StartMachineBasicBlock
(
MBB
)
;
for
(
MachineBasicBlock
::
instr_iterator
I
=
MBB
->
instr_begin
(
)
,
E
=
MBB
->
instr_end
(
)
;
I
!=
E
;
)
emitInstruction
(
*
I
++
,
*
MBB
)
;
}
}
while
(
MCE
.
finishFunction
(
MF
)
)
;
return
false
;
}
</s>

Mips
Mips
Mips
Mips
Mips
0
"JITTing function '"
"'\n"


<s>
void
PPCTargetLowering
::
LowerAsmOperandForConstraint
(
SDValue
Op
,
std
::
string
&
Constraint
,
std
::
vector
<
SDValue
>
&
Ops
,
SelectionDAG
&
DAG
)
const
{
SDValue
Result
;
if
(
Constraint
.
length
(
)
>
1
)
return
;
char
Letter
=
Constraint
[
0
]
;
switch
(
Letter
)
{
default
:
break
;
case
'I'
:
case
'J'
:
case
'K'
:
case
'L'
:
case
'M'
:
case
'N'
:
case
'O'
:
case
'P'
:
{
ConstantSDNode
*
CST
=
dyn_cast
<
ConstantSDNode
>
(
Op
)
;
if
(
!
CST
)
return
;
int64_t
Value
=
CST
->
getSExtValue
(
)
;
EVT
TCVT
=
MVT
::
i64
;
switch
(
Letter
)
{
default
:
llvm_unreachable
(
"Unknown constraint letter!"
)
;
case
'I'
:
if
(
isInt
<
16
>
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
TCVT
)
;
break
;
case
'J'
:
if
(
isShiftedUInt
<
16
,
16
>
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
TCVT
)
;
break
;
case
'L'
:
if
(
isShiftedInt
<
16
,
16
>
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
TCVT
)
;
break
;
case
'K'
:
if
(
isUInt
<
16
>
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
TCVT
)
;
break
;
case
'M'
:
if
(
Value
>
31
)
Result
=
DAG
.
getTargetConstant
(
Value
,
TCVT
)
;
break
;
case
'N'
:
if
(
Value
>
0
&&
isPowerOf2_64
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
TCVT
)
;
break
;
case
'O'
:
if
(
Value
==
0
)
Result
=
DAG
.
getTargetConstant
(
Value
,
TCVT
)
;
break
;
case
'P'
:
if
(
isInt
<
16
>
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
TCVT
)
;
break
;
}
break
;
}
}
if
(
Result
.
getNode
(
)
)
{
Ops
.
push_back
(
Result
)
;
return
;
}
TargetLowering
::
LowerAsmOperandForConstraint
(
Op
,
Constraint
,
Ops
,
DAG
)
;
}
</s>

Lower the specified operand into the Ops vector .


<s> void XtensaPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> const MipsRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> std :: string MCGNode :: getLabel ( ) const { std :: string tmps ; raw_string_ostream tmp ( tmps ) ; if ( isUnknown ( ) ) tmp << "<UNKNOWN-" << * T << ">" ; else tmp << MF -> getFunction ( ) . getName ( ) ; return tmps ; } </s>

Returns the MDNode pointer for the label .


<s> bool X86InstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Cond , unsigned TrueReg , unsigned FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( ! Subtarget . hasCMov ( ) ) return false ; if ( Cond . size ( ) != 1 ) return false ; if ( ( X86 :: CondCode ) Cond [ 0 ] . getImm ( ) > X86 :: COND_S ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( X86 :: GR16RegClass . hasSubClassEq ( RC ) || X86 :: GR32RegClass . hasSubClassEq ( RC ) || X86 :: GR64RegClass . hasSubClassEq ( RC ) ) { CondCycles = 2 ; TrueCycles = 2 ; FalseCycles = 2 ; return true ; } return false ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> static int ix86_mode_exit ( int entity ) { switch ( entity ) { case AVX_U128 : return ix86_avx_u128_mode_exit ( ) ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : case I387_MASK_PM : return I387_CW_ANY ; default : gcc_unreachable ( ) ; } } </s>

Return a mode that ENTITY is assumed to be switched to at function exit .


<s> bool MicroMipsSizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < MipsSubtarget > ( ) ; if ( ! Subtarget -> inMicroMipsMode ( ) || ! Subtarget -> hasMips32r2 ( ) || Subtarget -> hasMips32r6 ( ) ) return false ; MipsII = static_cast < const MipsInstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; bool Modified = false ; MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; for ( ; I != E ; ++ I ) Modified |= ReduceMBB ( * I ) ; return Modified ; } </s>


<s> bool MOSPassConfig :: addPreISel ( ) { return false ; } </s>


<s> void SIMachineFunctionInfo :: removeDeadFrameIndices ( MachineFrameInfo & MFI ) { for ( auto & R : make_early_inc_range ( SGPRToVGPRSpills ) ) { if ( R . first != FramePointerSaveIndex && R . first != BasePointerSaveIndex ) { MFI . RemoveStackObject ( R . first ) ; SGPRToVGPRSpills . erase ( R . first ) ; } } for ( int i = MFI . getObjectIndexBegin ( ) , e = MFI . getObjectIndexEnd ( ) ; i != e ; ++ i ) if ( i != FramePointerSaveIndex && i != BasePointerSaveIndex ) MFI . setStackID ( i , TargetStackID :: Default ) ; for ( auto & R : VGPRToAGPRSpills ) { if ( R . second . IsDead ) MFI . RemoveStackObject ( R . first ) ; } } </s>

If ResetSGPRSpillStackIDs is true , reset the stack ID from sgpr-spill to the default stack .


<s>
void
SIInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
Register
SrcReg
,
bool
isKill
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
SIMachineFunctionInfo
*
MFI
=
MF
->
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MachineFrameInfo
&
FrameInfo
=
MF
->
getFrameInfo
(
)
;
const
DebugLoc
&
DL
=
MBB
.
findDebugLoc
(
MI
)
;
MachinePointerInfo
PtrInfo
=
MachinePointerInfo
::
getFixedStack
(
*
MF
,
FrameIndex
)
;
MachineMemOperand
*
MMO
=
MF
->
getMachineMemOperand
(
PtrInfo
,
MachineMemOperand
::
MOStore
,
FrameInfo
.
getObjectSize
(
FrameIndex
)
,
FrameInfo
.
getObjectAlign
(
FrameIndex
)
)
;
unsigned
SpillSize
=
TRI
->
getSpillSize
(
*
RC
)
;
if
(
RI
.
isSGPRClass
(
RC
)
)
{
MFI
->
setHasSpilledSGPRs
(
)
;
assert
(
SrcReg
!=
AMDGPU
::
M0
&&
"m0 should not be spilled"
)
;
assert
(
SrcReg
!=
AMDGPU
::
EXEC_LO
&&
SrcReg
!=
AMDGPU
::
EXEC_HI
&&
SrcReg
!=
AMDGPU
::
EXEC
&&
"exec should not be spilled"
)
;
const
MCInstrDesc
&
OpDesc
=
get
(
getSGPRSpillSaveOpcode
(
SpillSize
)
)
;
if
(
Register
::
isVirtualRegister
(
SrcReg
)
&&
SpillSize
==
4
)
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
MRI
.
constrainRegClass
(
SrcReg
,
&
AMDGPU
::
SReg_32_XM0_XEXECRegClass
)
;
}
BuildMI
(
MBB
,
MI
,
DL
,
OpDesc
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIndex
)
.
addMemOperand
(
MMO
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
,
RegState
::
Implicit
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
,
RegState
::
Implicit
)
;
if
(
RI
.
spillSGPRToVGPR
(
)
)
FrameInfo
.
setStackID
(
FrameIndex
,
TargetStackID
::
SGPRSpill
)
;
return
;
}
unsigned
Opcode
=
RI
.
hasAGPRs
(
RC
)
getAGPRSpillSaveOpcode
(
SpillSize
)
:
getVGPRSpillSaveOpcode
(
SpillSize
)
;
MFI
->
setHasSpilledVGPRs
(
)
;
auto
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opcode
)
)
;
if
(
RI
.
hasAGPRs
(
RC
)
)
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
Register
Tmp
=
MRI
.
createVirtualRegister
(
&
AMDGPU
::
VGPR_32RegClass
)
;
MIB
.
addReg
(
Tmp
,
RegState
::
Define
)
;
}
MIB
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIndex
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> static int loongarch_sign_extend_cost ( rtx op ) { if ( MEM_P ( op ) ) return 0 ; return COSTS_N_INSNS ( 1 ) ; } </s>

Return the cost of sign-extending OP to mode MODE , not including the cost of OP itself .


<s>
void
Thumb1InstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
&
ARM
::
tGPRRegClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
&
ARM
::
tGPRRegClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
,
MachineMemOperand
::
MOLoad
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tLDRspi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .

ARM
ARM::tGPRRegClass
ARM
"Unknown regclass!"
ARM::tGPRRegClass
ARM
ARM::tLDRspi
0


<s> bool writeNopData ( raw_ostream & OS , uint64_t Count ) const override { if ( ( Count % 8 ) != 0 ) return false ; for ( uint64_t i = 0 ; i < Count ; i += 8 ) support :: endian :: write < uint64_t > ( OS , 0x7900000000000000ULL , support :: little ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> bool AArch64TargetLowering :: isFMAFasterThanFMulAndFAdd ( EVT VT ) const { VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f16 : case MVT :: f32 : case MVT :: f64 : return true ; case MVT :: f128 : return false ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s>
StringRef
getPassName
(
)
const
override
{
return
"SNES DAG->DAG Instruction Selection"
;
}
</s>

getPassName - Return a nice clean name for a pass .

SNES
"SNES DAG->DAG Instruction Selection"


<s>
void
SIInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
SIMachineFunctionInfo
*
MFI
=
MF
->
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MachineFrameInfo
&
FrameInfo
=
MF
->
getFrameInfo
(
)
;
const
DebugLoc
&
DL
=
MBB
.
findDebugLoc
(
MI
)
;
unsigned
Size
=
FrameInfo
.
getObjectSize
(
FrameIndex
)
;
unsigned
Align
=
FrameInfo
.
getObjectAlignment
(
FrameIndex
)
;
MachinePointerInfo
PtrInfo
=
MachinePointerInfo
::
getFixedStack
(
*
MF
,
FrameIndex
)
;
MachineMemOperand
*
MMO
=
MF
->
getMachineMemOperand
(
PtrInfo
,
MachineMemOperand
::
MOStore
,
Size
,
Align
)
;
unsigned
SpillSize
=
TRI
->
getSpillSize
(
*
RC
)
;
if
(
RI
.
isSGPRClass
(
RC
)
)
{
MFI
->
setHasSpilledSGPRs
(
)
;
const
MCInstrDesc
&
OpDesc
=
get
(
getSGPRSpillSaveOpcode
(
SpillSize
)
)
;
if
(
TargetRegisterInfo
::
isVirtualRegister
(
SrcReg
)
&&
SpillSize
==
4
)
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
MRI
.
constrainRegClass
(
SrcReg
,
&
AMDGPU
::
SReg_32_XM0RegClass
)
;
}
MachineInstrBuilder
Spill
=
BuildMI
(
MBB
,
MI
,
DL
,
OpDesc
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIndex
)
.
addMemOperand
(
MMO
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
,
RegState
::
Implicit
)
.
addReg
(
MFI
->
getFrameOffsetReg
(
)
,
RegState
::
Implicit
)
;
FrameInfo
.
setStackID
(
FrameIndex
,
SIStackID
::
SGPR_SPILL
)
;
if
(
ST
.
hasScalarStores
(
)
)
{
Spill
.
addReg
(
AMDGPU
::
M0
,
RegState
::
ImplicitDefine
|
RegState
::
Dead
)
;
}
return
;
}
assert
(
RI
.
hasVGPRs
(
RC
)
&&
"Only VGPR spilling expected"
)
;
unsigned
Opcode
=
getVGPRSpillSaveOpcode
(
SpillSize
)
;
MFI
->
setHasSpilledVGPRs
(
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opcode
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIndex
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
)
.
addReg
(
MFI
->
getFrameOffsetReg
(
)
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>


<s> void AArch64MacroFusion :: apply ( ScheduleDAGInstrs * DAGInstrs ) { ScheduleDAGMI * DAG = static_cast < ScheduleDAGMI * > ( DAGInstrs ) ; for ( SUnit & ISU : DAG -> SUnits ) scheduleAdjacentImpl ( DAG , ISU ) ; scheduleAdjacentImpl ( DAG , DAG -> ExitSU ) ; } </s>

Apply the profile inference algorithm for a given function .


<s> void finishImpl ( ) override { } </s>


<s>
MachineBasicBlock
::
iterator
TPCFrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
llvm_unreachable
(
"No stack frame pseudos"
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool HexagonTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { return true ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> bool AArch64FastISel :: optimizeSelect ( const SelectInst * SI ) { if ( ! SI -> getType ( ) -> isIntegerTy ( 1 ) ) return false ; const Value * Src1Val , * Src2Val ; unsigned Opc = 0 ; bool NeedExtraOp = false ; if ( auto * CI = dyn_cast < ConstantInt > ( SI -> getTrueValue ( ) ) ) { if ( CI -> isOne ( ) ) { Src1Val = SI -> getCondition ( ) ; Src2Val = SI -> getFalseValue ( ) ; Opc = AArch64 :: ORRWrr ; } else { assert ( CI -> isZero ( ) ) ; Src1Val = SI -> getFalseValue ( ) ; Src2Val = SI -> getCondition ( ) ; Opc = AArch64 :: BICWrr ; } } else if ( auto * CI = dyn_cast < ConstantInt > ( SI -> getFalseValue ( ) ) ) { if ( CI -> isOne ( ) ) { Src1Val = SI -> getCondition ( ) ; Src2Val = SI -> getTrueValue ( ) ; Opc = AArch64 :: ORRWrr ; NeedExtraOp = true ; } else { assert ( CI -> isZero ( ) ) ; Src1Val = SI -> getCondition ( ) ; Src2Val = SI -> getTrueValue ( ) ; Opc = AArch64 :: ANDWrr ; } } if ( ! Opc ) return false ; unsigned Src1Reg = getRegForValue ( Src1Val ) ; if ( ! Src1Reg ) return false ; unsigned Src2Reg = getRegForValue ( Src2Val ) ; if ( ! Src2Reg ) return false ; if ( NeedExtraOp ) Src1Reg = emitLogicalOp_ri ( ISD :: XOR , MVT :: i32 , Src1Reg , 1 ) ; unsigned ResultReg = fastEmitInst_rr ( Opc , & AArch64 :: GPR32RegClass , Src1Reg , Src2Reg ) ; updateValueMap ( SI , ResultReg ) ; return true ; } </s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


<s> bool AMDGPUDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & static_cast < const AMDGPUSubtarget & > ( MF . getSubtarget ( ) ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s>
const
char
*
output_adjust_stack_and_probe
(
rtx
reg
)
{
static
int
labelno
=
0
;
char
loop_lab
[
32
]
;
rtx
xops
[
2
]
;
ASM_GENERATE_INTERNAL_LABEL
(
loop_lab
,
"LPSRL"
,
labelno
++
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
loop_lab
)
;
xops
[
0
]
=
stack_pointer_rtx
;
xops
[
1
]
=
GEN_INT
(
get_probe_interval
(
)
)
;
output_asm_insn
(
"sub%z0\t{%1, %0|%0, %1}"
,
xops
)
;
xops
[
1
]
=
const0_rtx
;
output_asm_insn
(
"or%z0\t{%1, (%0)|DWORD PTR [%0], %1}"
,
xops
)
;
xops
[
0
]
=
stack_pointer_rtx
;
xops
[
1
]
=
reg
;
output_asm_insn
(
"cmp%z0\t{%1, %0|%0, %1}"
,
xops
)
;
fputs
(
"\tjne\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
loop_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
return
""
;
}
</s>

Adjust the stack pointer up to REG while probing it .


<s>
void
ScheduleDAGPostRA
::
viewGraph
(
)
{
viewGraph
(
getDAGName
(
)
,
"Scheduling-Units Graph for "
+
getDAGName
(
)
)
;
}
</s>

Pop up a GraphViz/gv window with the DAG rendered using 'dot ' .


<s> void SystemZTTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP ) { bool HasCall = false ; unsigned NumStores = 0 ; for ( auto & BB : L -> blocks ( ) ) for ( auto & I : * BB ) { if ( isa < CallInst > ( & I ) || isa < InvokeInst > ( & I ) ) { ImmutableCallSite CS ( & I ) ; if ( const Function * F = CS . getCalledFunction ( ) ) { if ( isLoweredToCall ( F ) ) HasCall = true ; if ( F -> getIntrinsicID ( ) == Intrinsic :: memcpy || F -> getIntrinsicID ( ) == Intrinsic :: memset ) NumStores ++ ; } else { HasCall = true ; } } if ( isa < StoreInst > ( & I ) ) { Type * MemAccessTy = I . getOperand ( 0 ) -> getType ( ) ; NumStores += getMemoryOpCost ( Instruction :: Store , MemAccessTy , None , 0 ) ; } } unsigned const Max = ( NumStores ? ( 12 / NumStores ) : UINT_MAX ) ; if ( HasCall ) { UP . FullUnrollMaxCount = Max ; UP . MaxCount = 1 ; return ; } UP . MaxCount = Max ; if ( UP . MaxCount <= 1 ) return ; UP . Partial = UP . Runtime = true ; UP . PartialThreshold = 75 ; UP . DefaultUnrollRuntimeCount = 4 ; UP . AllowExpensiveTripCount = true ; UP . Force = true ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .