<s> static void aarch64_setup_incoming_varargs ( cumulative_args_t cum_v , const function_arg_info & arg , int * pretend_size ATTRIBUTE_UNUSED , int no_rtl ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; CUMULATIVE_ARGS local_cum ; int gr_saved = cfun -> va_list_gpr_size ; int vr_saved = cfun -> va_list_fpr_size ; local_cum = * cum ; aarch64_function_arg_advance ( pack_cumulative_args ( & local_cum ) , arg ) ; if ( cfun -> va_list_gpr_size ) gr_saved = MIN ( NUM_ARG_REGS - local_cum . aapcs_ncrn , cfun -> va_list_gpr_size / UNITS_PER_WORD ) ; if ( cfun -> va_list_fpr_size ) vr_saved = MIN ( NUM_FP_ARG_REGS - local_cum . aapcs_nvrn , cfun -> va_list_fpr_size / UNITS_PER_VREG ) ; if ( ! TARGET_FLOAT ) { gcc_assert ( local_cum . aapcs_nvrn == 0 ) ; vr_saved = 0 ; } if ( ! no_rtl ) { if ( gr_saved > 0 ) { rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , - gr_saved * UNITS_PER_WORD ) ; mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . aapcs_ncrn + R0_REGNUM , mem , gr_saved ) ; } if ( vr_saved > 0 ) { machine_mode mode = TImode ; int off , i , vr_start ; off = - ROUND_UP ( gr_saved * UNITS_PER_WORD , STACK_BOUNDARY / BITS_PER_UNIT ) ; off -= vr_saved * UNITS_PER_VREG ; vr_start = V0_REGNUM + local_cum . aapcs_nvrn ; for ( i = 0 ; i < vr_saved ; ++ i ) { rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , off ) ; mem = gen_frame_mem ( mode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; aarch64_emit_move ( mem , gen_rtx_REG ( mode , vr_start + i ) ) ; off += UNITS_PER_VREG ; } } } cfun -> machine -> frame . saved_varargs_size = ( ROUND_UP ( gr_saved * UNITS_PER_WORD , STACK_BOUNDARY / BITS_PER_UNIT ) + vr_saved * UNITS_PER_VREG ) ; } </s>


<s> rtx aarch64_convert_sve_data_to_pred ( rtx target , machine_mode mode , rtx src ) { machine_mode src_mode = GET_MODE ( src ) ; return aarch64_sve_emit_int_cmp ( target , mode , NE , src_mode , src , CONST0_RTX ( src_mode ) ) ; } </s>

Use a comparison to convert integer vector SRC into MODE , which is the corresponding SVE predicate mode . Use TARGET for the result if it 's nonnull and convenient .


<s> bool HSAILRegisterInfo :: requiresFrameIndexScavenging ( const MachineFunction & MF ) const { const HSAILMachineFunctionInfo * Info = MF . getInfo < HSAILMachineFunctionInfo > ( ) ; return Info -> hasSpilledCRs ( ) ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


"Unrecognized Hexagon processor version"

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool function_expander :: try_negating_argument ( unsigned int argno , machine_mode mode ) { rtx x = args [ argno ] ; if ( ! VECTOR_MODE_P ( GET_MODE ( x ) ) ) mode = GET_MODE_INNER ( mode ) ; x = simplify_unary_operation ( NEG , mode , x , mode ) ; if ( ! x ) return false ; args [ argno ] = x ; return true ; } </s>

Return true if the negation of argument ARGNO can be folded away , replacing it with the negated value if so . MODE is the associated vector mode , but the argument could be a single element . The main case this handles is constant arguments .


<s>
const
MCPhysReg
*
X86RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
const
X86Subtarget
&
Subtarget
=
MF
->
getSubtarget
<
X86Subtarget
>
(
)
;
bool
HasAVX
=
Subtarget
.
hasAVX
(
)
;
bool
HasAVX512
=
Subtarget
.
hasAVX512
(
)
;
bool
CallsEHReturn
=
MF
->
getMMI
(
)
.
callsEHReturn
(
)
;
assert
(
MF
&&
"MachineFunction required"
)
;
switch
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
)
{
case
CallingConv
::
GHC
:
case
CallingConv
::
HiPE
:
return
CSR_NoRegs_SaveList
;
case
CallingConv
::
AnyReg
:
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
return
CSR_64_AllRegs_SaveList
;
case
CallingConv
::
PreserveMost
:
return
CSR_64_RT_MostRegs_SaveList
;
case
CallingConv
::
PreserveAll
:
if
(
HasAVX
)
return
CSR_64_RT_AllRegs_AVX_SaveList
;
return
CSR_64_RT_AllRegs_SaveList
;
case
CallingConv
::
Intel_OCL_BI
:
{
if
(
HasAVX512
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX512
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX_SaveList
;
if
(
HasAVX
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX_SaveList
;
if
(
!
HasAVX
&&
!
IsWin64
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_SaveList
;
break
;
}
case
CallingConv
::
Cold
:
if
(
Is64Bit
)
return
CSR_64_MostRegs_SaveList
;
break
;
case
CallingConv
::
X86_64_Win64
:
return
CSR_Win64_SaveList
;
case
CallingConv
::
X86_64_SysV
:
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
default
:
break
;
}
bool
IsNaCl
=
Subtarget
.
isTargetNaCl
(
)
;
if
(
Is64Bit
)
{
if
(
IsWin64
)
return
CSR_Win64_SaveList
;
if
(
IsNaCl
)
{
if
(
CallsEHReturn
)
return
CSR_NaCl64EHRet_SaveList
;
return
CSR_NaCl64_SaveList
;
}
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
}
if
(
CallsEHReturn
)
return
CSR_32EHRet_SaveList
;
return
CSR_32_SaveList
;
}
</s>


<s> void AGCFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


<s> machine_mode select_cc_mode ( enum rtx_code op , rtx x , rtx y ) { if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) { switch ( op ) { case EQ : case NE : case UNORDERED : case ORDERED : case UNLT : case UNLE : case UNGT : case UNGE : case UNEQ : case LTGT : return CCFPmode ; case LT : case LE : case GT : case GE : return CCFPEmode ; default : gcc_unreachable ( ) ; } } else if ( ( GET_CODE ( x ) == PLUS || GET_CODE ( x ) == MINUS || GET_CODE ( x ) == NEG || GET_CODE ( x ) == ASHIFT ) && y == const0_rtx ) { if ( TARGET_ARCH64 && GET_MODE ( x ) == DImode ) return CCXNZmode ; else return CCNZmode ; } else { if ( GET_CODE ( x ) == NOT && y == constm1_rtx ) { if ( TARGET_ARCH64 && GET_MODE ( x ) == DImode ) return CCXCmode ; else return CCCmode ; } if ( ! TARGET_ARCH64 && GET_MODE ( x ) == DImode ) { if ( GET_CODE ( y ) == UNSPEC && ( XINT ( y , 1 ) == UNSPEC_ADDV || XINT ( y , 1 ) == UNSPEC_SUBV || XINT ( y , 1 ) == UNSPEC_NEGV ) ) return CCVmode ; else return CCCmode ; } if ( TARGET_ARCH64 && GET_MODE ( x ) == DImode ) return CCXmode ; else return CCmode ; } } </s>

Given a comparison code ( EQ , NE , etc . ) and the first operand of a COMPARE , return the mode to be used for the comparison . For floating-point , CCFP [ E ] mode is used . CC_NOOVmode should be used when the first operand is a PLUS , MINUS , NEG , or ASHIFT . CCmode should be used when no special processing is needed .


runOnMachineFunction - Emit the function body .


<s> const AMDGPUAAResult & getResult ( ) const { return * Result ; } </s>

Get the result of an analysis pass for a given IR unit .


<s> static JVMAssemblerImpl * getInst ( ) { if ( ! inst ) { inst = new JVMAssemblerImpl ( ) ; } return inst ; } </s>

If this is a normal dependency , returns the instruction that is depended on .


"Can only insert epilog into returning blocks"

"SPURegisterInfo::emitEpilogue: FrameSize not aligned"


<s> bool X86TargetLowering :: isFsqrtCheap ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; if ( DAG . getNodeIfExists ( X86ISD :: FRSQRT , DAG . getVTList ( VT ) , Op ) ) return false ; if ( VT . isVector ( ) ) return Subtarget . hasFastVectorFSQRT ( ) ; return Subtarget . hasFastScalarFSQRT ( ) ; } </s>

Return true if SQRT ( X ) should n't be replaced with X * RSQRT ( X ) .


<s> static bool ix86_expand_vecop_qihi2 ( enum rtx_code code , rtx dest , rtx op1 , rtx op2 ) { machine_mode himode , qimode = GET_MODE ( dest ) ; rtx hop1 , hop2 , hdest ; rtx ( * gen_extend ) ( rtx , rtx ) ; rtx ( * gen_truncate ) ( rtx , rtx ) ; bool uns_p = ( code == ASHIFTRT ) ? false : true ; if ( qimode == E_V64QImode ) return false ; if ( ! TARGET_AVX512BW ) return false ; if ( ( qimode == V8QImode || qimode == V16QImode ) && ! TARGET_AVX512VL ) return false ; if ( qimode == V32QImode && ( TARGET_PREFER_AVX128 || TARGET_PREFER_AVX256 ) ) return false ; switch ( qimode ) { case E_V8QImode : himode = V8HImode ; gen_extend = uns_p ? gen_zero_extendv8qiv8hi2 : gen_extendv8qiv8hi2 ; gen_truncate = gen_truncv8hiv8qi2 ; break ; case E_V16QImode : himode = V16HImode ; gen_extend = uns_p ? gen_zero_extendv16qiv16hi2 : gen_extendv16qiv16hi2 ; gen_truncate = gen_truncv16hiv16qi2 ; break ; case E_V32QImode : himode = V32HImode ; gen_extend = uns_p ? gen_zero_extendv32qiv32hi2 : gen_extendv32qiv32hi2 ; gen_truncate = gen_truncv32hiv32qi2 ; break ; default : gcc_unreachable ( ) ; } hop1 = gen_reg_rtx ( himode ) ; hop2 = gen_reg_rtx ( himode ) ; hdest = gen_reg_rtx ( himode ) ; emit_insn ( gen_extend ( hop1 , op1 ) ) ; emit_insn ( gen_extend ( hop2 , op2 ) ) ; emit_insn ( gen_rtx_SET ( hdest , simplify_gen_binary ( code , himode , hop1 , hop2 ) ) ) ; emit_insn ( gen_truncate ( dest , hdest ) ) ; return true ; } </s>

This function is similar as ix86_expand_vecop_qihi , but optimized under AVX512BW by using vpmovwb . For example , optimize vector MUL generation like vpmovzxbw ymm2 , xmm0 vpmovzxbw ymm3 , xmm1 vpmullw ymm4 , ymm2 , ymm3 vpmovwb xmm0 , ymm4 it would take less instructions than ix86_expand_vecop_qihi . Return true if success .


<s>
void
mmix_asm_output_reg_pop
(
FILE
*
stream
,
int
regno
)
{
fprintf
(
stream
,
"\tLDOU %s,%s,0\n\tINCL %s,8\n"
,
reg_names
[
MMIX_OUTPUT_REGNO
(
regno
)
]
,
reg_names
[
MMIX_STACK_POINTER_REGNUM
]
,
reg_names
[
MMIX_STACK_POINTER_REGNUM
]
)
;
}
</s>


<s> static unsigned int avr_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( regno == REG_CC && mode == CCmode ) return 1 ; return CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ; } </s>

Implement TARGET_HARD_REGNO_NREGS . CCmode is four units for historical reasons . If this hook is not defined , TARGET_HARD_REGNO_NREGS reports that CCmode requires four registers . Define this hook to allow CCmode to fit in a single REG_CC . For other modes and regs , return the number of words in mode ( i.e whatever the default implementation of the hook returned ) .


<s> static void vr4130_align_insns ( void ) { struct mips_sim state ; rtx_insn * insn , * subinsn , * last , * last2 , * next ; bool aligned_p ; dfa_start ( ) ; last = 0 ; last2 = 0 ; aligned_p = true ; mips_sim_init ( & state , alloca ( state_size ( ) ) ) ; for ( insn = get_insns ( ) ; insn != 0 ; insn = next ) { unsigned int length ; next = NEXT_INSN ( insn ) ; vr4130_avoid_branch_rt_conflict ( insn ) ; length = get_attr_length ( insn ) ; if ( length > 0 && USEFUL_INSN_P ( insn ) ) FOR_EACH_SUBINSN ( subinsn , insn ) { mips_sim_wait_insn ( & state , subinsn ) ; if ( state . insns_left != state . issue_rate && ! CALL_P ( subinsn ) ) { if ( subinsn == SEQ_BEGIN ( insn ) && aligned_p ) { gcc_assert ( last2 ) ; emit_insn_after ( gen_nop ( ) , last2 ) ; aligned_p = false ; } else if ( subinsn != SEQ_BEGIN ( insn ) && ! aligned_p ) { gcc_assert ( last ) ; emit_insn_after ( gen_nop ( ) , last ) ; aligned_p = true ; } } mips_sim_issue_insn ( & state , subinsn ) ; } mips_sim_finish_insn ( & state , insn ) ; length = get_attr_length ( insn ) ; if ( length > 0 ) { if ( NONJUMP_INSN_P ( SEQ_BEGIN ( insn ) ) && ( recog_memoized ( insn ) < 0 || length >= 8 ) ) { next = emit_insn_after ( gen_align ( GEN_INT ( 3 ) ) , insn ) ; next = NEXT_INSN ( next ) ; mips_sim_next_cycle ( & state ) ; aligned_p = true ; } else if ( length & 4 ) aligned_p = ! aligned_p ; last2 = last ; last = insn ; } if ( LABEL_P ( insn ) && label_to_alignment ( insn ) . levels [ 0 ] . log >= 3 ) aligned_p = true ; } dfa_finish ( ) ; } </s>

Implement -mvr4130-align . Go through each basic block and simulate the processor pipeline . If we find that a pair of instructions could execute in parallel , and the first of those instruction is not 8-byte aligned , insert a nop to make it aligned .


<s> static bool must_save_rets_p ( void ) { return df_regs_ever_live_p ( REG_RETS ) ; } </s>

Determine if we are going to save the RETS register .


<s> TargetPassConfig * AMDGPUTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new AMDGPUPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> bool R600TargetLowering :: canMergeStoresTo ( unsigned AS , EVT MemVT , const SelectionDAG & DAG ) const { if ( ( AS == AMDGPUASI . LOCAL_ADDRESS || AS == AMDGPUASI . PRIVATE_ADDRESS ) ) { return ( MemVT . getSizeInBits ( ) <= 32 ) ; } return true ; } </s>

Returns if it 's reasonable to merge stores to MemVT size .


<s> static void rs6000_emit_prologue_components ( sbitmap components ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; rtx ptr_reg = gen_rtx_REG ( Pmode , frame_pointer_needed ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ) ; machine_mode reg_mode = Pmode ; int reg_size = TARGET_32BIT ? 4 : 8 ; machine_mode fp_reg_mode = ( TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT ) ? DFmode : SFmode ; int fp_reg_size = 8 ; if ( bitmap_bit_p ( components , 0 ) ) { rtx reg = gen_rtx_REG ( reg_mode , 0 ) ; rtx_insn * insn = emit_move_insn ( reg , gen_rtx_REG ( reg_mode , LR_REGNO ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_REGISTER , NULL ) ; int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; rtx lr = gen_rtx_REG ( reg_mode , LR_REGNO ) ; rtx mem = copy_rtx ( SET_DEST ( single_set ( insn ) ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , gen_rtx_SET ( mem , lr ) ) ; } if ( bitmap_bit_p ( components , 2 ) ) { rtx reg = gen_rtx_REG ( reg_mode , TOC_REGNUM ) ; rtx sp_reg = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; emit_insn ( gen_frame_store ( reg , sp_reg , RS6000_TOC_SAVE_SLOT ) ) ; } int offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_gp_reg_save ; i < 32 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; rtx set = copy_rtx ( single_set ( insn ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , set ) ; } offset += reg_size ; } offset = info -> fp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_fp_reg_save ; i < 64 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( fp_reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; rtx set = copy_rtx ( single_set ( insn ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , set ) ; } offset += fp_reg_size ; } } </s>


<s> bool Cpu0PassConfig :: addInstSelector ( ) { addPass ( createCpu0SEISelDag ( getCpu0TargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static bool isZero ( SDValue V ) { ConstantSDNode * C = dyn_cast < ConstantSDNode > ( V ) ; return C && C -> isNullValue ( ) ; } </s>

Return true if the expression is a constant zero .


<s> static rtx mips_expand_builtin_compare_1 ( enum insn_code icode , enum mips_fp_condition cond , tree exp , int nargs ) { struct expand_operand ops [ MAX_RECOG_OPERANDS ] ; rtx output ; int opno , argno ; gcc_assert ( nargs + 2 == insn_data [ ( int ) icode ] . n_generator_args ) ; output = mips_allocate_fcc ( insn_data [ ( int ) icode ] . operand [ 0 ] . mode ) ; opno = 0 ; create_fixed_operand ( & ops [ opno ++ ] , output ) ; for ( argno = 0 ; argno < nargs ; argno ++ ) mips_prepare_builtin_arg ( & ops [ opno ++ ] , exp , argno ) ; create_integer_operand ( & ops [ opno ++ ] , ( int ) cond ) ; return mips_expand_builtin_insn ( icode , opno , ops , true ) ; } </s>

Expand a floating-point comparison for built-in function call EXP . The first NARGS arguments are the values to be compared . ICODE is the .md pattern that does the comparison and COND is the condition that is being tested . Return an rtx for the result .


"passing %qT to argument %d of %qE, which"

Require argument ARGNO to be a vector base in a gather-style address . Return its type on success , otherwise return NUM_VECTOR_TYPES .


<s> void addFastRegAlloc ( ) override { } </s>

addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast register allocation .


<s> static void aarch64_emit_unlikely_jump ( rtx insn ) { int very_unlikely = REG_BR_PROB_BASE / 100 - 1 ; rtx_insn * jump = emit_jump_insn ( insn ) ; add_int_reg_note ( jump , REG_BR_PROB , very_unlikely ) ; } </s>

Mark the previous jump instruction as unlikely .


<s> bool isMem ( MemoryKind MemKind , RegisterKind RegKind ) const { return isMem ( MemKind ) && Mem . RegKind == RegKind ; } </s>


<s>
void
WebAssemblyRegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
)
const
{
assert
(
SPAdj
==
0
)
;
MachineInstr
&
MI
=
*
II
;
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
const
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
int64_t
FrameOffset
=
MFI
.
getStackSize
(
)
+
MFI
.
getObjectOffset
(
FrameIndex
)
;
if
(
MI
.
mayLoadOrStore
(
)
&&
FIOperandNum
==
WebAssembly
::
MemOpAddressOperandNo
)
{
assert
(
FrameOffset
>=
0
&&
MI
.
getOperand
(
1
)
.
getImm
(
)
>=
0
)
;
int64_t
Offset
=
MI
.
getOperand
(
1
)
.
getImm
(
)
+
FrameOffset
;
if
(
static_cast
<
uint64_t
>
(
Offset
)
>
std
::
numeric_limits
<
uint32_t
>
::
max
(
)
)
{
report_fatal_error
(
"Memory offset field overflow"
)
;
}
MI
.
getOperand
(
FIOperandNum
1
)
.
setImm
(
Offset
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
WebAssembly
::
SP32
,
false
)
;
}
else
{
auto
&
MRI
=
MF
.
getRegInfo
(
)
;
const
auto
*
TII
=
MF
.
getSubtarget
<
WebAssemblySubtarget
>
(
)
.
getInstrInfo
(
)
;
unsigned
FIRegOperand
=
WebAssembly
::
SP32
;
if
(
FrameOffset
)
{
FIRegOperand
=
MRI
.
createVirtualRegister
(
&
WebAssembly
::
I32RegClass
)
;
BuildMI
(
MBB
,
MI
,
MI
.
getDebugLoc
(
)
,
TII
->
get
(
WebAssembly
::
CONST_I32
)
,
FIRegOperand
)
.
addImm
(
FrameOffset
)
;
BuildMI
(
MBB
,
MI
,
MI
.
getDebugLoc
(
)
,
TII
->
get
(
WebAssembly
::
ADD_I32
)
,
FIRegOperand
)
.
addReg
(
WebAssembly
::
SP32
)
.
addReg
(
FIRegOperand
)
;
}
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FIRegOperand
,
false
)
;
}
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool Nios2AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { printOperand ( MI , OpNum , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> const char * NyuziTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case NyuziISD :: CALL : return "NyuziISD::CALL" ; case NyuziISD :: RET_FLAG : return "NyuziISD::RET_FLAG" ; case NyuziISD :: SPLAT : return "NyuziISD::SPLAT" ; case NyuziISD :: SEL_COND_RESULT : return "NyuziISD::SEL_COND_RESULT" ; case NyuziISD :: RECIPROCAL_EST : return "NyuziISD::RECIPROCAL_EST" ; case NyuziISD :: MASK_TO_INT : return "NyuziISD::MASK_TO_INT" ; case NyuziISD :: MASK_FROM_INT : return "NyuziISD::MASK_FROM_INT" ; case NyuziISD :: MOVEHI : return "NyuziISD::MOVEHI" ; case NyuziISD :: ORLO : return "NyuziISD::ORLO" ; case NyuziISD :: GOT_ADDR : return "NyuziISD::GOT_ADDR" ; case NyuziISD :: FGT : return "NyuziISD::FGT" ; case NyuziISD :: FGE : return "NyuziISD::FGE" ; case NyuziISD :: FLT : return "NyuziISD::FLT" ; case NyuziISD :: FLE : return "NyuziISD::FLE" ; case NyuziISD :: FEQ : return "NyuziISD::FEQ" ; case NyuziISD :: FNE : return "NyuziISD::FNE" ; default : return nullptr ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> unsigned int mn10300_get_live_callee_saved_regs ( unsigned int * bytes_saved ) { int mask ; int i ; unsigned int count ; count = mask = 0 ; for ( i = 0 ; i <= LAST_EXTENDED_REGNUM ; i ++ ) if ( df_regs_ever_live_p ( i ) && ! call_really_used_regs [ i ] ) { mask |= ( 1 << i ) ; ++ count ; } if ( ( mask & 0x3c000 ) != 0 ) { for ( i = 0x04000 ; i < 0x40000 ; i <<= 1 ) if ( ( mask & i ) == 0 ) ++ count ; mask |= 0x3c000 ; } if ( bytes_saved ) * bytes_saved = count * UNITS_PER_WORD ; return mask ; } </s>

Returns the set of live , callee-saved registers as a bitmask . The callee-saved extended registers can not be stored individually , so all of them will be included in the mask if any one of them is used .


<s> unsigned ARMFastISel :: fastEmitInst_r ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , bool Op0IsKill ) { Register ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , 1 ) ; if ( II . getNumDefs ( ) >= 1 ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ 0 ] ) ) ; } return ResultReg ; } </s>

Emit a MachineInstr with one register operand and a result register in the given register class .


<s> void or1k_expand_call ( rtx retval , rtx fnaddr , rtx callarg1 , bool sibcall ) { rtx call , use = NULL ; if ( flag_pic && GET_CODE ( XEXP ( fnaddr , 0 ) ) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P ( XEXP ( fnaddr , 0 ) ) ) { crtl -> uses_pic_offset_table = 1 ; rtx hard_pic = gen_rtx_REG ( Pmode , REAL_PIC_OFFSET_TABLE_REGNUM ) ; emit_move_insn ( hard_pic , pic_offset_table_rtx ) ; use_reg ( & use , hard_pic ) ; } if ( ! call_insn_operand ( XEXP ( fnaddr , 0 ) , Pmode ) ) { fnaddr = copy_to_mode_reg ( Pmode , XEXP ( fnaddr , 0 ) ) ; fnaddr = gen_rtx_MEM ( SImode , fnaddr ) ; } call = gen_rtx_CALL ( VOIDmode , fnaddr , callarg1 ) ; if ( retval ) call = gen_rtx_SET ( retval , call ) ; if ( ! sibcall ) { rtx clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , LR_REGNUM ) ) ; call = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , call , clob ) ) ; } call = emit_call_insn ( call ) ; CALL_INSN_FUNCTION_USAGE ( call ) = use ; } </s>

Expand the patterns `` call '' , `` sibcall '' , `` call_value '' and `` sibcall_value '' . Expands a function call where argument RETVAL is an optional RTX providing return value storage , the argument FNADDR is and RTX describing the function to call , the argument CALLARG1 is the number or registers used as operands and the argument SIBCALL should be true if this is a nested function call . If FNADDR is a non local symbol and FLAG_PIC is enabled this will generate a PLT call .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineFunctionAnalysis > ( ) ; AU . addPreserved < MachineFunctionAnalysis > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> const ARMSubtarget & ARMMCInstLower :: getSubtarget ( ) const { return AsmPrinter . getSubtarget ( ) ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


<s> void aarch64_expand_mov_immediate ( rtx dest , rtx imm ) { machine_mode mode = GET_MODE ( dest ) ; gcc_assert ( mode == SImode || mode == DImode ) ; if ( GET_CODE ( imm ) == SYMBOL_REF || GET_CODE ( imm ) == LABEL_REF || GET_CODE ( imm ) == CONST ) { rtx mem , base , offset ; enum aarch64_symbol_type sty ; split_const ( imm , & base , & offset ) ; sty = aarch64_classify_symbol ( base , offset ) ; switch ( sty ) { case SYMBOL_FORCE_TO_MEM : if ( offset != const0_rtx && targetm . cannot_force_const_mem ( mode , imm ) ) { gcc_assert ( can_create_pseudo_p ( ) ) ; base = aarch64_force_temporary ( mode , dest , base ) ; base = aarch64_add_offset ( mode , NULL , base , INTVAL ( offset ) ) ; aarch64_emit_move ( dest , base ) ; return ; } mem = force_const_mem ( ptr_mode , imm ) ; gcc_assert ( mem ) ; if ( aarch64_nopcrelative_literal_loads ) { gcc_assert ( can_create_pseudo_p ( ) ) ; base = gen_reg_rtx ( ptr_mode ) ; aarch64_expand_mov_immediate ( base , XEXP ( mem , 0 ) ) ; mem = gen_rtx_MEM ( ptr_mode , base ) ; } if ( mode != ptr_mode ) mem = gen_rtx_ZERO_EXTEND ( mode , mem ) ; emit_insn ( gen_rtx_SET ( dest , mem ) ) ; return ; case SYMBOL_SMALL_TLSGD : case SYMBOL_SMALL_TLSDESC : case SYMBOL_SMALL_TLSIE : case SYMBOL_SMALL_GOT_28K : case SYMBOL_SMALL_GOT_4G : case SYMBOL_TINY_GOT : case SYMBOL_TINY_TLSIE : if ( offset != const0_rtx ) { gcc_assert ( can_create_pseudo_p ( ) ) ; base = aarch64_force_temporary ( mode , dest , base ) ; base = aarch64_add_offset ( mode , NULL , base , INTVAL ( offset ) ) ; aarch64_emit_move ( dest , base ) ; return ; } case SYMBOL_SMALL_ABSOLUTE : case SYMBOL_TINY_ABSOLUTE : case SYMBOL_TLSLE12 : case SYMBOL_TLSLE24 : case SYMBOL_TLSLE32 : case SYMBOL_TLSLE48 : aarch64_load_symref_appropriately ( dest , imm , sty ) ; return ; default : gcc_unreachable ( ) ; } } if ( ! CONST_INT_P ( imm ) ) { if ( GET_CODE ( imm ) == HIGH ) emit_insn ( gen_rtx_SET ( dest , imm ) ) ; else { rtx mem = force_const_mem ( mode , imm ) ; gcc_assert ( mem ) ; emit_insn ( gen_rtx_SET ( dest , mem ) ) ; } return ; } aarch64_internal_mov_immediate ( dest , imm , true , GET_MODE ( dest ) ) ; } </s>

Set DEST to immediate IMM . For SVE vector modes , GEN_VEC_DUPLICATE is a pattern that can be used to set DEST to a replicated scalar element .


<s> void arm_split_atomic_op ( enum rtx_code code , rtx old_out , rtx new_out , rtx mem , rtx value , rtx model_rtx , rtx cond ) { enum memmodel model = memmodel_from_int ( INTVAL ( model_rtx ) ) ; machine_mode mode = GET_MODE ( mem ) ; machine_mode wmode = ( mode == DImode ? DImode : SImode ) ; rtx_code_label * label ; rtx x ; bool is_armv8_sync = arm_arch8 && is_mm_sync ( model ) ; bool use_acquire = TARGET_HAVE_LDACQ && ! ( is_mm_relaxed ( model ) || is_mm_consume ( model ) || is_mm_release ( model ) ) ; bool use_release = TARGET_HAVE_LDACQ && ! ( is_mm_relaxed ( model ) || is_mm_consume ( model ) || is_mm_acquire ( model ) ) ; if ( is_armv8_sync ) use_acquire = false ; if ( ! ( use_acquire || use_release ) ) arm_pre_atomic_barrier ( model ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; if ( new_out ) new_out = gen_lowpart ( wmode , new_out ) ; if ( old_out ) old_out = gen_lowpart ( wmode , old_out ) ; else old_out = new_out ; value = simplify_gen_subreg ( wmode , value , mode , 0 ) ; arm_emit_load_exclusive ( mode , old_out , mem , use_acquire ) ; switch ( code ) { case SET : new_out = value ; break ; case NOT : x = gen_rtx_AND ( wmode , old_out , value ) ; emit_insn ( gen_rtx_SET ( new_out , x ) ) ; x = gen_rtx_NOT ( wmode , new_out ) ; emit_insn ( gen_rtx_SET ( new_out , x ) ) ; break ; case MINUS : if ( CONST_INT_P ( value ) ) { value = GEN_INT ( - INTVAL ( value ) ) ; code = PLUS ; } case PLUS : if ( mode == DImode ) { emit_move_insn ( new_out , old_out ) ; if ( code == PLUS ) x = gen_adddi3 ( new_out , new_out , value ) ; else x = gen_subdi3 ( new_out , new_out , value ) ; emit_insn ( x ) ; break ; } default : x = gen_rtx_fmt_ee ( code , wmode , old_out , value ) ; emit_insn ( gen_rtx_SET ( new_out , x ) ) ; break ; } arm_emit_store_exclusive ( mode , cond , mem , gen_lowpart ( mode , new_out ) , use_release ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; emit_unlikely_jump ( gen_cbranchsi4 ( x , cond , const0_rtx , label ) ) ; if ( is_armv8_sync || ! ( use_acquire || use_release ) ) arm_post_atomic_barrier ( model ) ; } </s>

Split an atomic operation pattern . Operation is given by CODE and is one of PLUS , MINUS , IOR , XOR , SET ( for an exchange operation ) or NOT ( for a nand operation ) . Operation is performed on the content at MEM and on VALUE following the memory model MODEL_RTX . The content at MEM before and after the operation is returned in OLD_OUT and NEW_OUT respectively while the success of the operation is returned in COND . Using a scratch register or an operand register for these determines what result is returned for that pattern .


runOnMachineFunction - Emit the function body .


<s> void Warning ( SMLoc L , const Twine & Msg ) { Parser . Warning ( L , Msg ) ; } </s>

Emit a warning at the location L , with the message Msg .


<s> bool hasRawTextSupport ( ) const override { return true ; } </s>

Return true if this asm streamer supports emitting unformatted text to the .s file with EmitRawText .


<s> static bool arm_evpc_neon_vuzp ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> nelt ; rtx out0 , out1 , in0 , in1 ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; int first_elem ; int swap_nelt ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; swap_nelt = BYTES_BIG_ENDIAN && ! d -> one_vector_p && GET_MODE_SIZE ( d -> vmode ) == 8 ? d -> nelt : 0 ; first_elem = d -> perm [ neon_endian_lane_map ( d -> vmode , 0 ) ] ^ swap_nelt ; if ( first_elem == neon_endian_lane_map ( d -> vmode , 0 ) ) odd = 0 ; else if ( first_elem == neon_endian_lane_map ( d -> vmode , 1 ) ) odd = 1 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt ; i ++ ) { unsigned elt = ( neon_pair_endian_lane_map ( d -> vmode , i ) * 2 + odd ) & mask ; if ( ( d -> perm [ i ] ^ swap_nelt ) != neon_pair_endian_lane_map ( d -> vmode , elt ) ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vuzpv16qi_internal ; break ; case V8QImode : gen = gen_neon_vuzpv8qi_internal ; break ; case V8HImode : gen = gen_neon_vuzpv8hi_internal ; break ; case V4HImode : gen = gen_neon_vuzpv4hi_internal ; break ; case V4SImode : gen = gen_neon_vuzpv4si_internal ; break ; case V2SImode : gen = gen_neon_vuzpv2si_internal ; break ; case V2SFmode : gen = gen_neon_vuzpv2sf_internal ; break ; case V4SFmode : gen = gen_neon_vuzpv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d -> op1 ; if ( swap_nelt != 0 ) std :: swap ( in0 , in1 ) ; out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( odd ) std :: swap ( out0 , out1 ) ; emit_insn ( gen ( out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s> bool X86FastTileConfig :: runOnMachineFunction ( MachineFunction & MFunc ) { MF = & MFunc ; MRI = & MFunc . getRegInfo ( ) ; const TargetSubtargetInfo * ST = & MFunc . getSubtarget < X86Subtarget > ( ) ; TRI = ST -> getRegisterInfo ( ) ; TII = MFunc . getSubtarget ( ) . getInstrInfo ( ) ; X86FI = MFunc . getInfo < X86MachineFunctionInfo > ( ) ; bool Change = false ; for ( MachineBasicBlock & MBB : MFunc ) Change |= configBasicBlock ( MBB ) ; return Change ; } </s>


<s>
void
Thumb1InstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
&
ARM
::
tGPRRegClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
&
ARM
::
tGPRRegClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
,
MachineMemOperand
::
MOLoad
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tLDRspi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .

ARM
ARM::tGPRRegClass
ARM
"Unknown regclass!"
ARM::tGPRRegClass
ARM
ARM::tLDRspi
0
ARMCC::AL


<s> const MCPhysReg * VERegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { switch ( MF -> getFunction ( ) . getCallingConv ( ) ) { case CallingConv :: Fast : default : return CSR_SaveList ; case CallingConv :: PreserveAll : return CSR_preserve_all_SaveList ; } } </s>


<s> static void emit_unlikely_jump ( rtx cond , rtx label ) { int very_unlikely = REG_BR_PROB_BASE / 100 - 1 ; rtx x ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , cond , label , pc_rtx ) ; x = emit_jump_insn ( gen_rtx_SET ( pc_rtx , x ) ) ; add_int_reg_note ( x , REG_BR_PROB , very_unlikely ) ; } </s>


<s> static bool ix86_can_inline_p ( tree caller , tree callee ) { bool ret = false ; tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET ( caller ) ; tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET ( callee ) ; if ( ! callee_tree ) ret = true ; else if ( ! caller_tree ) ret = false ; else { struct cl_target_option * caller_opts = TREE_TARGET_OPTION ( caller_tree ) ; struct cl_target_option * callee_opts = TREE_TARGET_OPTION ( callee_tree ) ; if ( ( ( caller_opts -> x_ix86_isa_flags & callee_opts -> x_ix86_isa_flags ) != callee_opts -> x_ix86_isa_flags ) || ( ( caller_opts -> x_ix86_isa_flags2 & callee_opts -> x_ix86_isa_flags2 ) != callee_opts -> x_ix86_isa_flags2 ) ) ret = false ; else if ( caller_opts -> x_target_flags != callee_opts -> x_target_flags ) ret = false ; else if ( caller_opts -> arch != callee_opts -> arch ) ret = false ; else if ( caller_opts -> tune != callee_opts -> tune ) ret = false ; else if ( caller_opts -> x_ix86_fpmath != callee_opts -> x_ix86_fpmath ) ret = false ; else if ( caller_opts -> branch_cost != callee_opts -> branch_cost ) ret = false ; else ret = true ; } return ret ; } </s>

Hook to determine if one function can safely inline another .


<s> void load_got_register ( void ) { if ( ! global_offset_table_rtx ) global_offset_table_rtx = gen_rtx_REG ( Pmode , GLOBAL_OFFSET_TABLE_REGNUM ) ; if ( TARGET_VXWORKS_RTP ) emit_insn ( gen_vxworks_load_got ( ) ) ; else { if ( ! got_helper_rtx ) { char name [ 32 ] ; get_pc_thunk_name ( name , GLOBAL_OFFSET_TABLE_REGNUM ) ; got_helper_rtx = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( name ) ) ; } emit_insn ( gen_load_pcrel_sym ( global_offset_table_rtx , sparc_got ( ) , got_helper_rtx , GEN_INT ( GLOBAL_OFFSET_TABLE_REGNUM ) ) ) ; } emit_use ( global_offset_table_rtx ) ; } </s>


<s> static void mips_finish_stub ( mips_one_only_stub * * stub_ptr ) { mips_one_only_stub * stub = * stub_ptr ; if ( ! stub ) return ; const char * name = stub -> get_name ( ) ; mips_start_unique_function ( name ) ; mips_start_function_definition ( name , false ) ; stub -> output_body ( ) ; mips_end_function_definition ( name ) ; delete stub ; * stub_ptr = 0 ; } </s>

If * STUB_PTR points to a stub , output a comdat-style definition for it , then free * STUB_PTR .


<s> const InstrItineraryData & getInstrItineraryData ( ) const { return InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> uint16_t getFlags ( ) const { return NodeAttrs :: flags ( Attrs ) ; } </s>


<s> bool c6x_long_call_p ( rtx op ) { tree decl ; if ( ! TARGET_LONG_CALLS ) return false ; decl = SYMBOL_REF_DECL ( op ) ; if ( decl != NULL_TREE && ! flag_reorder_blocks_and_partition && TREE_CODE ( decl ) == FUNCTION_DECL && c6x_function_in_section_p ( decl , current_function_section ( ) ) ) return false ; return true ; } </s>

Return true if a call to OP , which is a SYMBOL_REF , must be expanded as a long call .


"Invalid number of NOP bytes requested!"

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


"insertBranch must not be told to insert a fallthrough"

"AVR branch conditions have one component!"

"Unconditional branch with multiple successors!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { TII = static_cast < const R600InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; for ( MachineFunction :: iterator BB = MF . begin ( ) , BB_E = MF . end ( ) ; BB != BB_E ; ++ BB ) { MachineBasicBlock & MBB = * BB ; MachineBasicBlock :: iterator I = MBB . begin ( ) ; if ( I -> getOpcode ( ) == AMDGPU :: CF_ALU ) continue ; for ( MachineBasicBlock :: iterator E = MBB . end ( ) ; I != E ; ) { if ( isALU ( I ) ) I = MakeALUClause ( MBB , I ) ; else ++ I ; } } return false ; } </s>


<s>
SDValue
PPCTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCRetInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCRetInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_PPC
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Val
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
,
InFlag
)
;
Chain
=
Val
.
getValue
(
1
)
;
InFlag
=
Val
.
getValue
(
2
)
;
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
AExt
:
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
ZExt
:
Val
=
DAG
.
getNode
(
ISD
::
AssertZext
,
dl
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
SExt
:
Val
=
DAG
.
getNode
(
ISD
::
AssertSext
,
dl
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
}
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .

PowerPC
PPC
ISD::InputArg
16
PPC
0
"Can only return in registers!"
1
2
"Unknown loc info!"
ISD::TRUNCATE
ISD::AssertZext
ISD::TRUNCATE
ISD::AssertSext
ISD::TRUNCATE


<s> rtx mmix_gen_compare_reg ( RTX_CODE code , rtx x , rtx y ) { machine_mode ccmode = SELECT_CC_MODE ( code , x , y ) ; return gen_reg_rtx ( ccmode ) ; } </s>

X and Y are two things to compare using CODE . Emit a compare insn if possible and return the rtx for the cc-reg in the proper mode , or NULL_RTX if this is not a valid comparison .


<s> static bool m32r_handle_option ( size_t code , const char * arg , int value ) { switch ( code ) { case OPT_m32r : target_flags &= ~ ( MASK_M32R2 | MASK_M32RX ) ; return true ; case OPT_mmodel_ : if ( strcmp ( arg , "small" ) == 0 ) m32r_model = M32R_MODEL_SMALL ; else if ( strcmp ( arg , "medium" ) == 0 ) m32r_model = M32R_MODEL_MEDIUM ; else if ( strcmp ( arg , "large" ) == 0 ) m32r_model = M32R_MODEL_LARGE ; else return false ; return true ; case OPT_msdata_ : if ( strcmp ( arg , "none" ) == 0 ) m32r_sdata = M32R_SDATA_NONE ; else if ( strcmp ( arg , "sdata" ) == 0 ) m32r_sdata = M32R_SDATA_SDATA ; else if ( strcmp ( arg , "use" ) == 0 ) m32r_sdata = M32R_SDATA_USE ; else return false ; return true ; case OPT_mno_flush_func : m32r_cache_flush_func = NULL ; return true ; case OPT_mflush_trap_ : return value <= 15 ; case OPT_mno_flush_trap : m32r_cache_flush_trap = - 1 ; return true ; default : return true ; } } </s>


"should only be seeing frame offset relative FrameIndex"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> static void ia64_emit_nops ( ) { rtx insn ; const struct bundle * b = 0 ; int bundle_pos = 0 ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { rtx pat ; enum attr_type t ; pat = INSN_P ( insn ) ? PATTERN ( insn ) : const0_rtx ; if ( GET_CODE ( pat ) == USE || GET_CODE ( pat ) == CLOBBER ) continue ; if ( ( GET_CODE ( pat ) == UNSPEC && XINT ( pat , 1 ) == 22 ) || GET_CODE ( insn ) == CODE_LABEL ) { if ( b ) while ( bundle_pos < 3 ) { emit_insn_before ( gen_nop_type ( b -> t [ bundle_pos ] ) , insn ) ; bundle_pos ++ ; } if ( GET_CODE ( insn ) != CODE_LABEL ) b = bundle + INTVAL ( XVECEXP ( pat , 0 , 0 ) ) ; else b = 0 ; bundle_pos = 0 ; continue ; } else if ( GET_CODE ( pat ) == UNSPEC_VOLATILE && XINT ( pat , 1 ) == 2 ) { int t = INTVAL ( XVECEXP ( pat , 0 , 0 ) ) ; if ( b ) while ( bundle_pos < t ) { emit_insn_before ( gen_nop_type ( b -> t [ bundle_pos ] ) , insn ) ; bundle_pos ++ ; } continue ; } if ( bundle_pos == 3 ) b = 0 ; if ( b && INSN_P ( insn ) ) { t = ia64_safe_type ( insn ) ; if ( asm_noperands ( PATTERN ( insn ) ) >= 0 || GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT ) { while ( bundle_pos < 3 ) { emit_insn_before ( gen_nop_type ( b -> t [ bundle_pos ] ) , insn ) ; bundle_pos ++ ; } continue ; } if ( t == TYPE_UNKNOWN ) continue ; while ( bundle_pos < 3 ) { if ( t == b -> t [ bundle_pos ] || ( t == TYPE_A && ( b -> t [ bundle_pos ] == TYPE_M || b -> t [ bundle_pos ] == TYPE_I ) ) ) break ; emit_insn_before ( gen_nop_type ( b -> t [ bundle_pos ] ) , insn ) ; bundle_pos ++ ; } if ( bundle_pos < 3 ) bundle_pos ++ ; } } } </s>

After the last scheduling pass , fill in NOPs . It 's easier to do this here than while scheduling .


<s> static void xstormy16_asm_out_destructor ( rtx symbol , int priority ) { const char * section = ".dtors" ; char buf [ 16 ] ; if ( priority != DEFAULT_INIT_PRIORITY ) { sprintf ( buf , ".dtors.%.5u" , MAX_INIT_PRIORITY - priority ) ; section = buf ; } named_section_flags ( section , 0 ) ; assemble_align ( POINTER_SIZE ) ; assemble_integer ( symbol , POINTER_SIZE / BITS_PER_UNIT , POINTER_SIZE , 1 ) ; } </s>

Output constructors and destructors . Just like default_named_section_asm_out_ * but do n't set the sections writable .


<s> bool runOnMachineFunction ( MachineFunction & F ) override { bool Changed = false ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; if ( Changed ) F . getRegInfo ( ) . invalidateLiveness ( ) ; return Changed ; } </s>


<s> void HexagonShuffler :: reset ( ) { Packet . clear ( ) ; BundleFlags = 0 ; CheckFailure = false ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s> bool ARMBaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; return ( RealignStack && ! AFI -> isThumb1OnlyFunction ( ) && ( ! MFI -> hasVarSizedObjects ( ) || EnableBasePointer ) ) ; } </s>

True if the stack can be realigned for the target .


"A single use instruction with no uses."

Return true if it is profitable to hoist instruction in the then/else to before if .


<s> const MCSection * SystemZMCAsmInfo :: getNonexecutableStackSection ( MCContext & Ctx ) const { return Ctx . getELFSection ( ".note.GNU-stack" , MCSectionELF :: SHT_PROGBITS , 0 , SectionKind :: getMetadata ( ) , false ) ; } </s>

Targets can implement this method to specify a section to switch to if the translation unit does n't have any trampolines that require an executable stack .


<s> MachineInstr * X86InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , int FrameIndex ) const { if ( NoFusing ) return nullptr ; if ( ! MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) && hasPartialRegUpdate ( MI -> getOpcode ( ) ) ) return nullptr ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned Size = MFI -> getObjectSize ( FrameIndex ) ; unsigned Alignment = MFI -> getObjectAlignment ( FrameIndex ) ; if ( ! RI . needsStackRealignment ( MF ) ) Alignment = std :: min ( Alignment , Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) ) ; if ( Ops . size ( ) == 2 && Ops [ 0 ] == 0 && Ops [ 1 ] == 1 ) { unsigned NewOpc = 0 ; unsigned RCSize = 0 ; switch ( MI -> getOpcode ( ) ) { default : return nullptr ; case X86 :: TEST8rr : NewOpc = X86 :: CMP8ri ; RCSize = 1 ; break ; case X86 :: TEST16rr : NewOpc = X86 :: CMP16ri8 ; RCSize = 2 ; break ; case X86 :: TEST32rr : NewOpc = X86 :: CMP32ri8 ; RCSize = 4 ; break ; case X86 :: TEST64rr : NewOpc = X86 :: CMP64ri8 ; RCSize = 8 ; break ; } if ( Size < RCSize ) return nullptr ; MI -> setDesc ( get ( NewOpc ) ) ; MI -> getOperand ( 1 ) . ChangeToImmediate ( 0 ) ; } else if ( Ops . size ( ) != 1 ) return nullptr ; SmallVector < MachineOperand , 4 > MOs ; MOs . push_back ( MachineOperand :: CreateFI ( FrameIndex ) ) ; return foldMemoryOperandImpl ( MF , MI , Ops [ 0 ] , MOs , Size , Alignment , true ) ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s>
void
AMDGPUInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
DestReg
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
llvm_unreachable
(
"Not Implemented"
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> void Mips16FrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MipsInstrInfo & TII = * static_cast < const MipsInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( StackSize == 0 && ! MFI -> adjustsStack ( ) ) return ; if ( isInt < 16 > ( - StackSize ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: SaveRaF16 ) ) . addImm ( StackSize ) ; if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: MoveR3216 ) , Mips :: S0 ) . addReg ( Mips :: SP ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static void frv_io_handle_use ( rtx * x , void * data ) { for_each_rtx ( x , frv_io_handle_use_1 , data ) ; } </s>

A note_stores callback that applies frv_io_handle_use_1 to an entire rhs value .


<s> bool X86TargetLowering :: isZExtFree ( EVT VT1 , EVT VT2 ) const { return VT1 == MVT :: i32 && VT2 == MVT :: i64 && Subtarget . is64Bit ( ) ; } </s>

Return true if zero-extending the specific node Val to type VT2 is free ( either because it 's implicitly zero-extended such as ARM ldrb / ldrh or because it 's folded such as X86 zero-extending loads ) .


<s> void Cpu0SEFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; Cpu0MachineFunctionInfo * Cpu0FI = MF . getInfo < Cpu0MachineFunctionInfo > ( ) ; const Cpu0SEInstrInfo & TII = * static_cast < const Cpu0SEInstrInfo * > ( STI . getInstrInfo ( ) ) ; const Cpu0RegisterInfo & RegInfo = * static_cast < const Cpu0SERegisterInfo * > ( STI . getRegisterInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; Cpu0ABIInfo ABI = STI . getABI ( ) ; unsigned SP = Cpu0 :: SP ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize , MBB , MBBI ) ; } </s>


"pointer targeting address space %qs must be const in %qT"

"pointer targeting address space %qs must be const"

Sanity check NODE so that all pointers targeting non-generic address spaces go along with CONST qualifier . Writing to these address spaces should be detected and complained about as early as possible .


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
READ_REGISTER
:
ExpandREAD_REGISTER
(
N
,
Results
,
DAG
)
;
break
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
READCYCLECOUNTER
:
ReplaceREADCYCLECOUNTER
(
N
,
Results
,
DAG
,
Subtarget
)
;
return
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

ARM
ARM
"Don't know how to custom expand this!"
ISD::READ_REGISTER
ISD::BITCAST
ISD::SRL
ISD::SRA
ISD::READCYCLECOUNTER


<s> static void nds32_register_passes ( void ) { nds32_register_pass ( make_pass_nds32_fp_as_gp , PASS_POS_INSERT_BEFORE , "ira" ) ; nds32_register_pass ( make_pass_nds32_relax_opt , PASS_POS_INSERT_AFTER , "mach" ) ; } </s>

This function is called from nds32_option_override ( ) . All new passes should be registered here .


"stack frame not a multiple of octabyte: %wd"

Expands the function epilogue into RTX .


<s> static bool sh_scalar_mode_supported_p ( machine_mode mode ) { if ( TARGET_SHMEDIA32 && mode == TImode ) return false ; return default_scalar_mode_supported_p ( mode ) ; } </s>

The scalar modes supported differs from the default version in TImode for 32-bit SHMEDIA .


<s> MachineBasicBlock :: iterator eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const override { return MBB . erase ( MI ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> WebAssemblyTargetMachine :: WebAssemblyTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , TT . isArch64Bit ( ) ? ( TT . isOSEmscripten ( ) ? "e-m:e-p:64:64-p10:8:8-p20:8:8-i64:64-" "f128:64-n32:64-S128-ni:1:10:20" : "e-m:e-p:64:64-p10:8:8-p20:8:8-i64:64-" "n32:64-S128-ni:1:10:20" ) : ( TT . isOSEmscripten ( ) ? "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-" "f128:64-n32:64-S128-ni:1:10:20" : "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-" "n32:64-S128-ni:1:10:20" ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM , TT ) , getEffectiveCodeModel ( CM , CodeModel :: Large ) , OL ) , TLOF ( new WebAssemblyTargetObjectFile ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . FunctionSections = true ; this -> Options . DataSections = true ; this -> Options . UniqueSectionNames = true ; initAsmInfo ( ) ; } </s>

Create an WebAssembly architecture model .


<s> BitVector AVRRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const AVRTargetMachine & TM = static_cast < const AVRTargetMachine & > ( MF . getTarget ( ) ) ; const TargetFrameLowering * TFI = TM . getSubtargetImpl ( ) -> getFrameLowering ( ) ; Reserved . set ( AVR :: R0 ) ; Reserved . set ( AVR :: R1 ) ; Reserved . set ( AVR :: R1R0 ) ; Reserved . set ( AVR :: SPL ) ; Reserved . set ( AVR :: SPH ) ; Reserved . set ( AVR :: SP ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( AVR :: R28 ) ; Reserved . set ( AVR :: R29 ) ; Reserved . set ( AVR :: R29R28 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static const char * cond_string ( enum rtx_code code ) { bool cc_overflow_unusable = false ; switch ( code ) { case NE : return "ne" ; case EQ : return "eq" ; case GE : if ( cc_overflow_unusable ) return "pl" ; else return "ge" ; case LT : if ( cc_overflow_unusable ) return "mi" ; else return "lt" ; case GEU : return "sh" ; case LTU : return "lo" ; default : gcc_unreachable ( ) ; } return "" ; } </s>

Return assembly language string which identifies a comparison type .

avr "ne" "eq" "pl" "ge" "mi" "lt" "sh" "lo" ""


<s> unsigned int rs6000_dbx_register_number ( unsigned int regno , unsigned int format ) { if ( SPE_HIGH_REGNO_P ( regno ) ) return regno - FIRST_SPE_HIGH_REGNO + 1200 ; if ( ( format == 0 && write_symbols != DWARF2_DEBUG ) || format == 2 ) return regno ; if ( regno <= 63 ) return regno ; if ( regno == LR_REGNO ) return 108 ; if ( regno == CTR_REGNO ) return 109 ; if ( format == 1 && regno == CR2_REGNO ) return 64 ; if ( CR_REGNO_P ( regno ) ) return regno - CR0_REGNO + 86 ; if ( regno == CA_REGNO ) return 101 ; if ( ALTIVEC_REGNO_P ( regno ) ) return regno - FIRST_ALTIVEC_REGNO + 1124 ; if ( regno == VRSAVE_REGNO ) return 356 ; if ( regno == VSCR_REGNO ) return 67 ; if ( regno == SPE_ACC_REGNO ) return 99 ; if ( regno == SPEFSCR_REGNO ) return 612 ; return regno ; } </s>

Map internal gcc register numbers to DWARF2 register numbers .


<s> static int getRegClass ( RegisterKind Is , unsigned RegWidth ) { if ( Is == IS_VGPR ) { switch ( RegWidth ) { default : return - 1 ; case 1 : return AMDGPU :: VGPR_32RegClassID ; case 2 : return AMDGPU :: VReg_64RegClassID ; case 3 : return AMDGPU :: VReg_96RegClassID ; case 4 : return AMDGPU :: VReg_128RegClassID ; case 8 : return AMDGPU :: VReg_256RegClassID ; case 16 : return AMDGPU :: VReg_512RegClassID ; } } else if ( Is == IS_TTMP ) { switch ( RegWidth ) { default : return - 1 ; case 1 : return AMDGPU :: TTMP_32RegClassID ; case 2 : return AMDGPU :: TTMP_64RegClassID ; case 4 : return AMDGPU :: TTMP_128RegClassID ; case 8 : return AMDGPU :: TTMP_256RegClassID ; case 16 : return AMDGPU :: TTMP_512RegClassID ; } } else if ( Is == IS_SGPR ) { switch ( RegWidth ) { default : return - 1 ; case 1 : return AMDGPU :: SGPR_32RegClassID ; case 2 : return AMDGPU :: SGPR_64RegClassID ; case 4 : return AMDGPU :: SGPR_128RegClassID ; case 8 : return AMDGPU :: SGPR_256RegClassID ; case 16 : return AMDGPU :: SGPR_512RegClassID ; } } else if ( Is == IS_AGPR ) { switch ( RegWidth ) { default : return - 1 ; case 1 : return AMDGPU :: AGPR_32RegClassID ; case 2 : return AMDGPU :: AReg_64RegClassID ; case 4 : return AMDGPU :: AReg_128RegClassID ; case 16 : return AMDGPU :: AReg_512RegClassID ; case 32 : return AMDGPU :: AReg_1024RegClassID ; } } return - 1 ; } </s>

Given a machine instruction descriptor , returns the register class constraint for OpNum , or NULL .


"Only 32/64-bit atomic stores supported"

Perform a store-conditional operation to Addr .


<s> bool AArch64AsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { unsigned Kind = Fixup . getKind ( ) ; if ( Kind >= FirstLiteralRelocationKind ) return true ; if ( Kind == AArch64 :: fixup_aarch64_pcrel_adrp_imm21 ) return true ; AArch64MCExpr :: VariantKind RefKind = static_cast < AArch64MCExpr :: VariantKind > ( Target . getRefKind ( ) ) ; AArch64MCExpr :: VariantKind SymLoc = AArch64MCExpr :: getSymbolLoc ( RefKind ) ; if ( Kind == AArch64 :: fixup_aarch64_ldr_pcrel_imm19 && SymLoc == AArch64MCExpr :: VK_GOT ) return true ; return false ; } </s>

Hook to check if a relocation is needed for some target specific reason .


<s>
void
LinearizedRegion
::
print
(
raw_ostream
&
OS
,
const
TargetRegisterInfo
*
TRI
)
{
OS
<<
"Linearized Region {"
;
bool
IsFirst
=
true
;
for
(
const
auto
&
MBB
:
MBBs
)
{
if
(
IsFirst
)
{
IsFirst
=
false
;
}
else
{
OS
<<
" ,"
;
}
OS
<<
MBB
->
getNumber
(
)
;
}
OS
<<
"} ("
<<
Entry
->
getNumber
(
)
<<
", "
<<
(
Exit
==
nullptr
1
:
Exit
->
getNumber
(
)
)
<<
"): In:"
<<
printReg
(
getBBSelectRegIn
(
)
,
TRI
)
<<
" Out:"
<<
printReg
(
getBBSelectRegOut
(
)
,
TRI
)
<<
" {"
;
for
(
auto
&
LI
:
LiveOuts
)
{
OS
<<
printReg
(
LI
,
TRI
)
<<
" "
;
}
OS
<<
"} \n"
;
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> int AArch64TTIImpl :: getIntImmCost ( Intrinsic :: ID IID , unsigned Idx , const APInt & Imm , Type * Ty ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; switch ( IID ) { default : return TTI :: TCC_Free ; case Intrinsic :: sadd_with_overflow : case Intrinsic :: uadd_with_overflow : case Intrinsic :: ssub_with_overflow : case Intrinsic :: usub_with_overflow : case Intrinsic :: smul_with_overflow : case Intrinsic :: umul_with_overflow : if ( Idx == 1 ) { int NumConstants = ( BitSize + 63 ) / 64 ; int Cost = AArch64TTIImpl :: getIntImmCost ( Imm , Ty ) ; return ( Cost <= NumConstants * TTI :: TCC_Basic ) ? static_cast < int > ( TTI :: TCC_Free ) : Cost ; } break ; case Intrinsic :: experimental_stackmap : if ( ( Idx < 2 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; case Intrinsic :: experimental_patchpoint_void : case Intrinsic :: experimental_patchpoint_i64 : if ( ( Idx < 4 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; } return AArch64TTIImpl :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> bool RISCVTargetMachine :: isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DstAS ) const { return true ; } </s>

Returns true if a cast between SrcAS and DestAS is a noop .


<s> bool e8_consumed_by_ex_p ( rtx_insn * consumer , rtx def_reg ) { rtx use_rtx ; switch ( get_attr_type ( consumer ) ) { case TYPE_ALU : case TYPE_STORE : use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_MUL : case TYPE_MAC : case TYPE_DIV : case TYPE_BRANCH : case TYPE_STORE_MULTIPLE : return n8_consumed_by_ex_p ( consumer , def_reg ) ; default : gcc_unreachable ( ) ; } return reg_overlap_p ( def_reg , use_rtx ) ; } </s>

Check the dependency between the producer defining DEF_REG and CONSUMER requiring input operand at EX .


<s> const char * MSP430TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return NULL ; case MSP430ISD :: RET_FLAG : return "MSP430ISD::RET_FLAG" ; case MSP430ISD :: RETI_FLAG : return "MSP430ISD::RETI_FLAG" ; case MSP430ISD :: RRA : return "MSP430ISD::RRA" ; case MSP430ISD :: RLA : return "MSP430ISD::RLA" ; case MSP430ISD :: RRC : return "MSP430ISD::RRC" ; case MSP430ISD :: CALL : return "MSP430ISD::CALL" ; case MSP430ISD :: Wrapper : return "MSP430ISD::Wrapper" ; case MSP430ISD :: BR_CC : return "MSP430ISD::BR_CC" ; case MSP430ISD :: CMP : return "MSP430ISD::CMP" ; case MSP430ISD :: SELECT_CC : return "MSP430ISD::SELECT_CC" ; case MSP430ISD :: SHL : return "MSP430ISD::SHL" ; case MSP430ISD :: SRA : return "MSP430ISD::SRA" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s>
bool
AArch64BranchRelaxation
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
MF
=
&
mf
;
DEBUG
(
dbgs
(
)
<<
"***** AArch64BranchRelaxation *****\n"
)
;
TII
=
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
getInstrInfo
(
)
;
MF
->
RenumberBlocks
(
)
;
scanFunction
(
)
;
DEBUG
(
dbgs
(
)
<<
"  Basic blocks before relaxation\n"
;
dumpBBs
(
)
;
)
;
bool
MadeChange
=
false
;
while
(
relaxBranchInstructions
(
)
)
MadeChange
=
true
;
verify
(
)
;
DEBUG
(
dbgs
(
)
<<
"  Basic blocks after relaxation\n\n"
;
dumpBBs
(
)
)
;
BlockInfo
.
clear
(
)
;
return
MadeChange
;
}
</s>

runOnMachineFunction - Emit the function body .


<s>
int
LC2200FrameLowering
::
getFrameIndexReference
(
const
MachineFunction
&
MF
,
int
FI
,
unsigned
&
FrameReg
)
const
{
int
offset
=
TargetFrameLowering
::
getFrameIndexReference
(
MF
,
FI
,
FrameReg
)
;
assert
(
offset
%
4
==
0
&&
"4-byte addressibility"
)
;
return
offset
/
4
;
}
</s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> bool arm_is_long_call_p ( tree decl ) { tree attrs ; if ( ! decl ) return TARGET_LONG_CALLS ; attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; if ( lookup_attribute ( "short_call" , attrs ) ) return false ; if ( ! flag_reorder_blocks_and_partition && TREE_CODE ( decl ) == FUNCTION_DECL && arm_function_in_section_p ( decl , current_function_section ( ) ) ) return false ; if ( lookup_attribute ( "long_call" , attrs ) ) return true ; return TARGET_LONG_CALLS ; } </s>

Return nonzero if a 32-bit `` long_call '' should be generated for a call from the current function to DECL . We generate a long_call if the function : a. has an __attribute__ ( ( long call ) ) or b. is within the scope of a # pragma long_calls or c. the -mlong-calls command line switch has been specified However we do not generate a long call if the function : d. has an __attribute__ ( ( short_call ) ) or e. is inside the scope of a # pragma no_long_calls or f. is defined in the same section as the current function .


This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly


<s> bool isFsqrtCheap ( SDValue Operand , SelectionDAG & DAG ) const override { return true ; } </s>

Return true if SQRT ( X ) should n't be replaced with X * RSQRT ( X ) .


Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> void ix86_emit_fp_unordered_jump ( rtx label ) { rtx reg = gen_reg_rtx ( HImode ) ; rtx temp ; emit_insn ( gen_x86_fnstsw_1 ( reg ) ) ; if ( TARGET_SAHF && ( TARGET_USE_SAHF || optimize_insn_for_size_p ( ) ) ) { emit_insn ( gen_x86_sahf_1 ( reg ) ) ; temp = gen_rtx_REG ( CCmode , FLAGS_REG ) ; temp = gen_rtx_UNORDERED ( VOIDmode , temp , const0_rtx ) ; } else { emit_insn ( gen_testqi_ext_ccno_0 ( reg , GEN_INT ( 0x04 ) ) ) ; temp = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; temp = gen_rtx_NE ( VOIDmode , temp , const0_rtx ) ; } temp = gen_rtx_IF_THEN_ELSE ( VOIDmode , temp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; temp = gen_rtx_SET ( VOIDmode , pc_rtx , temp ) ; emit_jump_insn ( temp ) ; predict_jump ( REG_BR_PROB_BASE * 10 / 100 ) ; } </s>

Output code to perform a conditional jump to LABEL , if C2 flag in FP status register is set .


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> void arc_cpu_cpp_builtins ( cpp_reader * pfile ) { builtin_assert ( "cpu=arc" ) ; builtin_assert ( "machine=arc" ) ; builtin_define ( "__arc__" ) ; def_or_undef_macro ( pfile , NAME , CONDITION ) ; builtin_define_with_int_value ( "__ARC_TLS_REGNO__" , arc_tp_regno ) ; builtin_define_with_int_value ( "__ARC_LPC_WIDTH__" , arc_lpcwidth ) ; builtin_define ( TARGET_BIG_ENDIAN ? "__BIG_ENDIAN__" : "__LITTLE_ENDIAN__" ) ; if ( TARGET_BIG_ENDIAN ) builtin_define ( "__big_endian__" ) ; if ( TARGET_HARD_FLOAT ) { builtin_define ( "__arc_hard_float__" ) ; builtin_define ( "__ARC_HARD_FLOAT__" ) ; } else { builtin_define ( "__arc_soft_float__" ) ; builtin_define ( "__ARC_SOFT_FLOAT__" ) ; } } </s>

Helper for TARGET_CPU_CPP_BUILTINS hook .


<s> SDValue X86TargetLowering :: getPICJumpTableRelocBase ( SDValue Table , SelectionDAG & DAG ) const { if ( ! Subtarget -> is64Bit ( ) ) return DAG . getNode ( X86ISD :: GlobalBaseReg , SDLoc ( ) , getPointerTy ( ) ) ; return Table ; } </s>

Returns relocation base for the given PIC jumptable .


"%qs attribute only applies to variables"

Handle a `` shared '' attribute ; arguments as in struct attribute_spec.handler .


<s> bool PPCPostRASchedStrategy :: tryCandidate ( SchedCandidate & Cand , SchedCandidate & TryCand ) { if ( ! Cand . isValid ( ) ) { TryCand . Reason = NodeOrder ; return true ; } if ( tryLess ( Top . getLatencyStallCycles ( TryCand . SU ) , Top . getLatencyStallCycles ( Cand . SU ) , TryCand , Cand , Stall ) ) return TryCand . Reason != NoCand ; if ( tryGreater ( TryCand . SU == DAG -> getNextClusterSucc ( ) , Cand . SU == DAG -> getNextClusterSucc ( ) , TryCand , Cand , Cluster ) ) return TryCand . Reason != NoCand ; if ( tryLess ( TryCand . ResDelta . CritResources , Cand . ResDelta . CritResources , TryCand , Cand , ResourceReduce ) ) return TryCand . Reason != NoCand ; if ( tryGreater ( TryCand . ResDelta . DemandedResources , Cand . ResDelta . DemandedResources , TryCand , Cand , ResourceDemand ) ) return TryCand . Reason != NoCand ; if ( Cand . Policy . ReduceLatency && tryLatency ( TryCand , Cand , Top ) ) { return TryCand . Reason != NoCand ; } if ( TryCand . SU -> NodeNum < Cand . SU -> NodeNum ) TryCand . Reason = NodeOrder ; if ( TryCand . Reason != NodeOrder && TryCand . Reason != NoCand ) return true ; if ( biasAddiCandidate ( Cand , TryCand ) ) return TryCand . Reason != NoCand ; return TryCand . Reason != NoCand ; } </s>

Apply a set of heuristics to a new candidate .


<s> bool isToken ( ) const override { if ( Kind == Token ) return true ; if ( Kind != Expression || ! Expr ) return false ; return isa < MCSymbolRefExpr > ( Expr ) ; } </s>


<s> bool MipsPassConfig :: addPreSched2 ( ) { PM -> add ( createMipsExpandPseudoPass ( getMipsTargetMachine ( ) ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> void MipsAsmPrinter :: emitFunctionBodyEnd ( ) { MipsTargetStreamer & TS = getTargetStreamer ( ) ; if ( ! Subtarget -> inMips16Mode ( ) ) { TS . emitDirectiveSetAt ( ) ; TS . emitDirectiveSetMacro ( ) ; TS . emitDirectiveSetReorder ( ) ; } TS . emitDirectiveEnd ( CurrentFnSym -> getName ( ) ) ; if ( ! InConstantPool ) return ; InConstantPool = false ; OutStreamer -> emitDataRegion ( MCDR_DataRegionEnd ) ; } </s>

Targets can override this to emit stuff after the last basic block in the function .


<s> uint64_t MipsAbiFlags :: emit ( const MipsAbiFlags & pInfo , MemoryRegion & pRegion ) { auto * buf = reinterpret_cast < ElfMipsAbiFlags * > ( pRegion . begin ( ) ) ; buf -> version = 0 ; buf -> isa_level = pInfo . m_IsaLevel ; buf -> isa_rev = pInfo . m_IsaRev ; buf -> gpr_size = pInfo . m_GprSize ; buf -> cpr1_size = pInfo . m_Cpr1Size ; buf -> cpr2_size = pInfo . m_Cpr2Size ; buf -> fp_abi = pInfo . m_FpAbi ; buf -> isa_ext = pInfo . m_IsaExt ; buf -> ases = pInfo . m_Ases ; buf -> flags1 = pInfo . m_Flags1 ; buf -> flags2 = 0 ; return size ( ) ; } </s>

Output the remark via the diagnostic handler and to the optimization record file .


<s> bool MipsPassConfig :: addPreSched2 ( ) { PM . add ( createMipsExpandPseudoPass ( getMipsTargetMachine ( ) ) ) ; return true ; } </s>


<s> static ArgDescriptor createRegister ( Register Reg , unsigned Mask = ~ 0u ) { return ArgDescriptor ( Reg , Mask , false , true ) ; } </s>

.cfi_register Previous value of Register1 is saved in register Register2 .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createMachObjectWriter ( OS , true , object :: mach :: CTM_x86_64 , object :: mach :: CSX86_ALL , true ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static void riscv_legitimize_poly_move ( machine_mode mode , rtx dest , rtx tmp , rtx src ) { poly_int64 value = rtx_to_poly_int64 ( src ) ; int offset = value . coeffs [ 0 ] ; int factor = value . coeffs [ 1 ] ; int vlenb = BYTES_PER_RISCV_VECTOR . coeffs [ 1 ] ; int div_factor = 0 ; emit_move_insn ( tmp , gen_int_mode ( BYTES_PER_RISCV_VECTOR , mode ) ) ; if ( BYTES_PER_RISCV_VECTOR . is_constant ( ) ) { gcc_assert ( value . is_constant ( ) ) ; riscv_emit_move ( dest , GEN_INT ( value . to_constant ( ) ) ) ; return ; } else if ( ( factor % vlenb ) == 0 ) div_factor = 1 ; else if ( ( factor % ( vlenb / 2 ) ) == 0 ) div_factor = 2 ; else if ( ( factor % ( vlenb / 4 ) ) == 0 ) div_factor = 4 ; else if ( ( factor % ( vlenb / 8 ) ) == 0 ) div_factor = 8 ; else gcc_unreachable ( ) ; if ( div_factor != 1 ) riscv_expand_op ( LSHIFTRT , mode , tmp , tmp , gen_int_mode ( exact_log2 ( div_factor ) , QImode ) ) ; riscv_expand_mult_with_const_int ( mode , dest , tmp , factor / ( vlenb / div_factor ) ) ; HOST_WIDE_INT constant = offset - factor ; if ( constant == 0 ) return ; else if ( SMALL_OPERAND ( constant ) ) riscv_expand_op ( PLUS , mode , dest , dest , gen_int_mode ( constant , mode ) ) ; else { rtx high ; high = gen_int_mode ( CONST_HIGH_PART ( constant ) , mode ) ; constant = CONST_LOW_PART ( constant ) ; riscv_emit_move ( tmp , high ) ; riscv_expand_op ( PLUS , mode , dest , tmp , dest ) ; riscv_expand_op ( PLUS , mode , dest , dest , gen_int_mode ( constant , mode ) ) ; } } </s>

Analyze src and emit const_poly_int mov sequence .


<s> void Cpu0FrameLowering :: emitEpilogue ( MachineFunction & , MachineBasicBlock & MBB ) const { } </s>


<s> bool X86PassConfig :: addPreEmitPass ( ) { bool ShouldPrint = false ; if ( getOptLevel ( ) != CodeGenOpt :: None && getX86Subtarget ( ) . hasSSE2 ( ) ) { addPass ( createExecutionDependencyFixPass ( & X86 :: VR128RegClass ) ) ; ShouldPrint = true ; } if ( getX86Subtarget ( ) . hasAVX ( ) && UseVZeroUpper ) { addPass ( createX86IssueVZeroUpperPass ( ) ) ; ShouldPrint = true ; } if ( getOptLevel ( ) != CodeGenOpt :: None && getX86Subtarget ( ) . padShortFunctions ( ) ) { addPass ( createX86PadShortFunctions ( ) ) ; ShouldPrint = true ; } return ShouldPrint ; } </s>


<s> registered_function & function_builder :: add_function ( const function_instance & instance , const char * name , tree fntype , tree attrs , uint64_t required_extensions , bool overloaded_p ) { unsigned int code = vec_safe_length ( registered_functions ) ; code = ( code << AARCH64_BUILTIN_SHIFT ) | AARCH64_BUILTIN_SVE ; tree decl = simulate_builtin_function_decl ( input_location , name , fntype , code , NULL , attrs ) ; registered_function & rfn = * ggc_alloc < registered_function > ( ) ; rfn . instance = instance ; rfn . decl = decl ; rfn . required_extensions = required_extensions ; rfn . overloaded_p = overloaded_p ; vec_safe_push ( registered_functions , & rfn ) ; return rfn ; } </s>

Add a function called NAME with type FNTYPE and attributes ATTRS . INSTANCE describes what the function does .


<s> void tilepro_expand_umulsi3_highpart ( rtx op0 , rtx op1 , rtx op2 ) { tilepro_expand_high_multiply ( op0 , op1 , op2 , false ) ; } </s>


<s> virtual const ARCompactSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> int rs6000_trampoline_size ( void ) { int ret = 0 ; switch ( DEFAULT_ABI ) { default : gcc_unreachable ( ) ; case ABI_AIX : ret = ( TARGET_32BIT ) ? 12 : 24 ; break ; case ABI_ELFv2 : gcc_assert ( ! TARGET_32BIT ) ; ret = 32 ; break ; case ABI_DARWIN : case ABI_V4 : ret = ( TARGET_32BIT ) ? 40 : 48 ; break ; } return ret ; } </s>

Length in units of the trampoline for entering a nested function .


<s> void mprocRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


"getRegForInlineAsmConstraint Unhandled data type"

Given a physical register constraint ( e.g .


<s> bool enablePostRAScheduler ( ) const override { return true ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s> void AArch64PreLegalizerCombiner :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < TargetPassConfig > ( ) ; AU . setPreservesCFG ( ) ; getSelectionDAGFallbackAnalysisUsage ( AU ) ; AU . addRequired < GISelKnownBitsAnalysis > ( ) ; AU . addPreserved < GISelKnownBitsAnalysis > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < GISelCSEAnalysisWrapperPass > ( ) ; AU . addPreserved < GISelCSEAnalysisWrapperPass > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static void xtensa_reorg ( void ) { compute_bb_for_insn ( ) ; df_analyze ( ) ; xtensa_reorg_loops ( ) ; } </s>

Implement the TARGET_MACHINE_DEPENDENT_REORG pass .


<s> const char * PPCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return nullptr ; case PPCISD :: FSEL : return "PPCISD::FSEL" ; case PPCISD :: FCFID : return "PPCISD::FCFID" ; case PPCISD :: FCTIDZ : return "PPCISD::FCTIDZ" ; case PPCISD :: FCTIWZ : return "PPCISD::FCTIWZ" ; case PPCISD :: FRE : return "PPCISD::FRE" ; case PPCISD :: FRSQRTE : return "PPCISD::FRSQRTE" ; case PPCISD :: STFIWX : return "PPCISD::STFIWX" ; case PPCISD :: VMADDFP : return "PPCISD::VMADDFP" ; case PPCISD :: VNMSUBFP : return "PPCISD::VNMSUBFP" ; case PPCISD :: VPERM : return "PPCISD::VPERM" ; case PPCISD :: Hi : return "PPCISD::Hi" ; case PPCISD :: Lo : return "PPCISD::Lo" ; case PPCISD :: TOC_ENTRY : return "PPCISD::TOC_ENTRY" ; case PPCISD :: LOAD : return "PPCISD::LOAD" ; case PPCISD :: LOAD_TOC : return "PPCISD::LOAD_TOC" ; case PPCISD :: DYNALLOC : return "PPCISD::DYNALLOC" ; case PPCISD :: GlobalBaseReg : return "PPCISD::GlobalBaseReg" ; case PPCISD :: SRL : return "PPCISD::SRL" ; case PPCISD :: SRA : return "PPCISD::SRA" ; case PPCISD :: SHL : return "PPCISD::SHL" ; case PPCISD :: CALL : return "PPCISD::CALL" ; case PPCISD :: CALL_NOP : return "PPCISD::CALL_NOP" ; case PPCISD :: MTCTR : return "PPCISD::MTCTR" ; case PPCISD :: BCTRL : return "PPCISD::BCTRL" ; case PPCISD :: RET_FLAG : return "PPCISD::RET_FLAG" ; case PPCISD :: EH_SJLJ_SETJMP : return "PPCISD::EH_SJLJ_SETJMP" ; case PPCISD :: EH_SJLJ_LONGJMP : return "PPCISD::EH_SJLJ_LONGJMP" ; case PPCISD :: MFOCRF : return "PPCISD::MFOCRF" ; case PPCISD :: VCMP : return "PPCISD::VCMP" ; case PPCISD :: VCMPo : return "PPCISD::VCMPo" ; case PPCISD :: LBRX : return "PPCISD::LBRX" ; case PPCISD :: STBRX : return "PPCISD::STBRX" ; case PPCISD :: LARX : return "PPCISD::LARX" ; case PPCISD :: STCX : return "PPCISD::STCX" ; case PPCISD :: COND_BRANCH : return "PPCISD::COND_BRANCH" ; case PPCISD :: BDNZ : return "PPCISD::BDNZ" ; case PPCISD :: BDZ : return "PPCISD::BDZ" ; case PPCISD :: MFFS : return "PPCISD::MFFS" ; case PPCISD :: FADDRTZ : return "PPCISD::FADDRTZ" ; case PPCISD :: TC_RETURN : return "PPCISD::TC_RETURN" ; case PPCISD :: CR6SET : return "PPCISD::CR6SET" ; case PPCISD :: CR6UNSET : return "PPCISD::CR6UNSET" ; case PPCISD :: ADDIS_TOC_HA : return "PPCISD::ADDIS_TOC_HA" ; case PPCISD :: LD_TOC_L : return "PPCISD::LD_TOC_L" ; case PPCISD :: ADDI_TOC_L : return "PPCISD::ADDI_TOC_L" ; case PPCISD :: PPC32_GOT : return "PPCISD::PPC32_GOT" ; case PPCISD :: ADDIS_GOT_TPREL_HA : return "PPCISD::ADDIS_GOT_TPREL_HA" ; case PPCISD :: LD_GOT_TPREL_L : return "PPCISD::LD_GOT_TPREL_L" ; case PPCISD :: ADD_TLS : return "PPCISD::ADD_TLS" ; case PPCISD :: ADDIS_TLSGD_HA : return "PPCISD::ADDIS_TLSGD_HA" ; case PPCISD :: ADDI_TLSGD_L : return "PPCISD::ADDI_TLSGD_L" ; case PPCISD :: GET_TLS_ADDR : return "PPCISD::GET_TLS_ADDR" ; case PPCISD :: ADDIS_TLSLD_HA : return "PPCISD::ADDIS_TLSLD_HA" ; case PPCISD :: ADDI_TLSLD_L : return "PPCISD::ADDI_TLSLD_L" ; case PPCISD :: GET_TLSLD_ADDR : return "PPCISD::GET_TLSLD_ADDR" ; case PPCISD :: ADDIS_DTPREL_HA : return "PPCISD::ADDIS_DTPREL_HA" ; case PPCISD :: ADDI_DTPREL_L : return "PPCISD::ADDI_DTPREL_L" ; case PPCISD :: VADD_SPLAT : return "PPCISD::VADD_SPLAT" ; case PPCISD :: SC : return "PPCISD::SC" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static rtx ix86_expand_aligntest ( rtx variable , int value ) { rtx label = gen_label_rtx ( ) ; rtx tmpcount = gen_reg_rtx ( GET_MODE ( variable ) ) ; if ( GET_MODE ( variable ) == DImode ) emit_insn ( gen_anddi3 ( tmpcount , variable , GEN_INT ( value ) ) ) ; else emit_insn ( gen_andsi3 ( tmpcount , variable , GEN_INT ( value ) ) ) ; emit_cmp_and_jump_insns ( tmpcount , const0_rtx , EQ , 0 , GET_MODE ( variable ) , 1 , label ) ; return label ; } </s>

Helper function for the string operations below . Dest VARIABLE whether it is aligned to VALUE bytes . If true , jump to the label .


<s> const TargetSchedModel & getSchedModel ( ) const { return SchedModel ; } </s>

Get the machine model for this subtarget 's CPU .


"NVPTX DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


"invalid id value for interrupt/exception attribute"

"invalid nmi function for reset attribute"

"invalid warm function for reset attribute"

Add some checking when inserting attributes .


<s>
static
void
mn10300_asm_output_mi_thunk
(
FILE
*
file
,
tree
thunk_fndecl
ATTRIBUTE_UNUSED
,
HOST_WIDE_INT
delta
,
HOST_WIDE_INT
vcall_offset
,
tree
function
)
{
const
char
*
_this
;
if
(
aggregate_value_p
(
TREE_TYPE
(
TREE_TYPE
(
function
)
)
,
function
)
)
_this
=
reg_names
[
FIRST_ARGUMENT_REGNUM
+
1
]
;
else
_this
=
reg_names
[
FIRST_ARGUMENT_REGNUM
]
;
fprintf
(
file
,
"\t%s Thunk Entry Point:\n"
,
ASM_COMMENT_START
)
;
if
(
delta
)
fprintf
(
file
,
"\tadd %d, %s\n"
,
(
int
)
delta
,
_this
)
;
if
(
vcall_offset
)
{
const
char
*
scratch
=
reg_names
[
FIRST_ADDRESS_REGNUM
+
1
]
;
fprintf
(
file
,
"\tmov %s, %s\n"
,
_this
,
scratch
)
;
fprintf
(
file
,
"\tmov (%s), %s\n"
,
scratch
,
scratch
)
;
fprintf
(
file
,
"\tadd %d, %s\n"
,
(
int
)
vcall_offset
,
scratch
)
;
fprintf
(
file
,
"\tmov (%s), %s\n"
,
scratch
,
scratch
)
;
fprintf
(
file
,
"\tadd %s, %s\n"
,
scratch
,
_this
)
;
}
fputs
(
"\tjmp "
,
file
)
;
assemble_name
(
file
,
XSTR
(
XEXP
(
DECL_RTL
(
function
)
,
0
)
,
0
)
)
;
putc
(
'\n'
,
file
)
;
}
</s>

Output the assembler code for a C++ thunk function . THUNK_DECL is the declaration for the thunk function itself , FUNCTION is the decl for the target function . DELTA is an immediate constant offset to be added to the THIS parameter . If VCALL_OFFSET is nonzero the word at the adjusted address * ( * THIS ' + VCALL_OFFSET ) should be additionally added to THIS . Finally jump to the entry point of FUNCTION .


<s> void WebAssemblyExceptionInfo :: recalculate ( MachineDominatorTree & MDT , const MachineDominanceFrontier & MDF ) { SmallVector < WebAssemblyException * , 8 > Exceptions ; for ( auto DomNode : post_order ( & MDT ) ) { MachineBasicBlock * EHPad = DomNode -> getBlock ( ) ; if ( ! EHPad -> isEHPad ( ) ) continue ; if ( WebAssembly :: isCatchAllTerminatePad ( * EHPad ) ) continue ; auto * WE = new WebAssemblyException ( EHPad ) ; discoverAndMapException ( WE , MDT , MDF ) ; Exceptions . push_back ( WE ) ; } for ( auto DomNode : post_order ( & MDT ) ) { MachineBasicBlock * MBB = DomNode -> getBlock ( ) ; WebAssemblyException * WE = getExceptionFor ( MBB ) ; for ( ; WE ; WE = WE -> getParentException ( ) ) WE -> addBlock ( MBB ) ; } for ( auto * WE : Exceptions ) { if ( WE -> getParentException ( ) ) WE -> getParentException ( ) -> getSubExceptions ( ) . push_back ( WE ) ; else addTopLevelException ( WE ) ; } for ( auto * WE : Exceptions ) { WE -> reverseBlock ( ) ; std :: reverse ( WE -> getSubExceptions ( ) . begin ( ) , WE -> getSubExceptions ( ) . end ( ) ) ; } } </s>

Notify DTU that the entry block was replaced .

WebAssembly WebAssembly WebAssembly 8 WebAssembly::isCatchAllTerminatePad WebAssembly WebAssembly


<s>
static
const
char
*
rs6000_call_template_1
(
rtx
*
operands
,
unsigned
int
funop
,
bool
sibcall
)
{
gcc_assert
(
funop
<=
MAX_RECOG_OPERANDS
)
;
char
arg
[
12
]
;
arg
[
0
]
=
0
;
if
(
GET_CODE
(
operands
[
funop
+
1
]
)
==
UNSPEC
)
{
if
(
XINT
(
operands
[
funop
+
1
]
,
1
)
==
UNSPEC_TLSGD
)
sprintf
(
arg
,
"(%%%u@tlsgd)"
,
funop
+
1
)
;
else
if
(
XINT
(
operands
[
funop
+
1
]
,
1
)
==
UNSPEC_TLSLD
)
sprintf
(
arg
,
"(%%&@tlsld)"
)
;
}
char
z
[
11
]
;
sprintf
(
z
,
"%%z%u%s"
,
funop
,
(
DEFAULT_ABI
==
ABI_V4
&&
TARGET_SECURE_PLT
&&
flag_pic
==
2
"+32768"
:
""
)
)
;
static
char
str
[
32
]
;
if
(
rs6000_pcrel_p
(
)
)
sprintf
(
str
,
"b%s %s@notoc%s"
,
sibcall
""
:
"l"
,
z
,
arg
)
;
else
if
(
DEFAULT_ABI
==
ABI_AIX
||
DEFAULT_ABI
==
ABI_ELFv2
)
sprintf
(
str
,
"b%s %s%s%s"
,
sibcall
""
:
"l"
,
z
,
arg
,
sibcall
""
:
"\n\tnop"
)
;
else
if
(
DEFAULT_ABI
==
ABI_V4
)
sprintf
(
str
,
"b%s %s%s%s"
,
sibcall
""
:
"l"
,
z
,
arg
,
flag_pic
"@plt"
:
""
)
;
else
if
(
DEFAULT_ABI
==
ABI_DARWIN
)
{
gcc_checking_assert
(
GET_CODE
(
operands
[
funop
+
2
]
)
==
CONST_INT
)
;
int
cookie
=
INTVAL
(
operands
[
funop
+
2
]
)
;
if
(
cookie
&
CALL_LONG
)
{
tree
funname
=
get_identifier
(
XSTR
(
operands
[
funop
]
,
0
)
)
;
tree
labelname
=
get_prev_label
(
funname
)
;
gcc_checking_assert
(
labelname
&&
!
sibcall
)
;
sprintf
(
str
,
"jbsr %%z%u,%.10s"
,
funop
,
IDENTIFIER_POINTER
(
labelname
)
)
;
}
else
sprintf
(
str
,
"b%s %s%s"
,
sibcall
""
:
"l"
,
z
,
arg
)
;
}
else
gcc_unreachable
(
)
;
return
str
;
}
</s>

Return a template string for assembly to emit when making an external call . FUNOP is the call mem argument operand number .


<s> static void winnt_d_register_target_info ( void ) { const struct d_target_info_spec handlers [ ] = { { "objectFormat" , winnt_d_handle_target_object_format } , { NULL , NULL } , } ; d_add_target_info_handlers ( handlers ) ; } </s>

Implement TARGET_D_REGISTER_OS_TARGET_INFO for Windows targets .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return this -> TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> bool GCNHazardRecognizer :: ShouldPreferAnother ( SUnit * SU ) { if ( ! SU -> isInstr ( ) ) return false ; const MachineInstr * MAI = nullptr ; auto IsMFMAFn = [ & MAI ] ( const MachineInstr & MI ) { MAI = nullptr ; if ( SIInstrInfo :: isMAI ( MI ) && MI . getOpcode ( ) != AMDGPU :: V_ACCVGPR_WRITE_B32_e64 && MI . getOpcode ( ) != AMDGPU :: V_ACCVGPR_READ_B32_e64 ) MAI = & MI ; return MAI != nullptr ; } ; MachineInstr * MI = SU -> getInstr ( ) ; if ( IsMFMAFn ( * MI ) ) { int W = getWaitStatesSince ( IsMFMAFn , 16 ) ; if ( MAI ) return W < ( int ) TSchedModel . computeInstrLatency ( MAI ) ; } return false ; } </s>

ShouldPreferAnother - This callback may be invoked if getHazardType returns NoHazard .


<s> bool DLXMemAluCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( DisableMemAluCombiner ) return false ; TII = MF . getSubtarget < DLXSubtarget > ( ) . getInstrInfo ( ) ; bool Modified = false ; for ( MfIterator MFI = MF . begin ( ) ; MFI != MF . end ( ) ; ++ MFI ) { Modified |= combineMemAluInBasicBlock ( & * MFI ) ; } return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> void X86PassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & LiveRangeShrinkID ) ; addPass ( createX86FixupSetCC ( ) ) ; addPass ( createX86OptimizeLEAs ( ) ) ; addPass ( createX86CallFrameOptimization ( ) ) ; addPass ( createX86AvoidStoreForwardingBlocks ( ) ) ; } addPass ( createX86SpeculativeLoadHardeningPass ( ) ) ; addPass ( createX86FlagsCopyLoweringPass ( ) ) ; addPass ( createX86WinAllocaExpander ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86PreTileConfigPass ( ) ) ; } } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> SDValue PPCTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { if ( PPCSubTarget . isSVR4ABI ( ) && ! PPCSubTarget . isPPC64 ( ) ) { return LowerFormalArguments_SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } else { return LowerFormalArguments_Darwin ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> bool CSKYAsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> pass_shorten_memrefs :: regno_map * pass_shorten_memrefs :: analyze ( basic_block bb ) { regno_map * m = hash_map < regno_hash , int > :: create_ggc ( 10 ) ; rtx_insn * insn ; regstat_init_n_sets_and_refs ( ) ; FOR_BB_INSNS ( bb , insn ) { if ( ! NONJUMP_INSN_P ( insn ) ) continue ; rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) != SET ) continue ; for ( int i = 0 ; i < 2 ; i ++ ) { rtx mem = XEXP ( pat , i ) ; rtx addr ; bool extend = false ; if ( get_si_mem_base_reg ( mem , & addr , & extend ) ) { HOST_WIDE_INT regno = REGNO ( XEXP ( addr , 0 ) ) ; if ( i == 0 ) { if ( XEXP ( pat , 1 ) == CONST0_RTX ( GET_MODE ( XEXP ( pat , 1 ) ) ) ) continue ; } if ( REG_N_REFS ( regno ) < 4 ) continue ; m -> get_or_insert ( regno ) ++ ; } } } regstat_free_n_sets_and_refs ( ) ; return m ; } </s>

Count how many times each regno is referenced as base address for a memory access .


<s> int nios2_label_align ( rtx label ) { int n = CODE_LABEL_NUMBER ( label ) ; if ( label_align && n >= min_labelno && n <= max_labelno ) return MAX ( label_align [ n - min_labelno ] , align_labels_log ) ; return align_labels_log ; } </s>

Implement LABEL_ALIGN , using the information gathered in nios2_reorg .


<s> const TargetRegisterClass * ARMBaseRegisterInfo :: getCrossCopyRegClass ( const TargetRegisterClass * RC ) const { if ( RC == & ARM :: CCRRegClass ) return 0 ; return RC ; } </s>

getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or from .


<s>
bool
RISCVDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_m
:
SDValue
Base
,
Offset
;
selectMemRegAddr
(
Op
,
Base
,
Offset
)
;
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
return
false
;
}
return
false
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .

RISCV
RISCV
"Unexpected asm memory constraint"


"unimplemented opcode in encodeInstruction()"

Encode the given Inst to bytes and append to CB .


<s> static bool rs6000_secondary_reload_simple_move ( enum rs6000_reg_type to_type , enum rs6000_reg_type from_type , machine_mode mode ) { int size ; size = GET_MODE_SIZE ( mode ) ; if ( TARGET_DIRECT_MOVE && ( ( mode == SDmode ) || ( TARGET_POWERPC64 && size == 8 ) ) && ( ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) || ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; else if ( TARGET_MFPGPR && TARGET_POWERPC64 && size == 8 && ( ( to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE ) || ( to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; else if ( ( size == 4 || ( TARGET_POWERPC64 && size == 8 ) ) && ( ( to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE ) || ( to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; return false ; } </s>

Helper function for rs6000_secondary_reload to return true if a move to a different register classe is really a simple move .


<s> const MCPhysReg * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const ARMSubtarget & STI = MF -> getSubtarget < ARMSubtarget > ( ) ; if ( STI . isTargetNaCl ( ) ) return CSR_NaCl_SaveList ; const MCPhysReg * RegList = STI . isTargetDarwin ( ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ; const Function * F = MF -> getFunction ( ) ; if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F -> hasFnAttribute ( "interrupt" ) ) { if ( STI . isMClass ( ) ) { return CSR_AAPCS_SaveList ; } else if ( F -> getFnAttribute ( "interrupt" ) . getValueAsString ( ) == "FIQ" ) { return CSR_FIQ_SaveList ; } else { return CSR_GenericInt_SaveList ; } } return RegList ; } </s>

ARM ARM ARM ARM "interrupt" "interrupt" "FIQ"


<s> bool addPassesToEmitMC ( PassManagerBase & , MCContext * & , raw_ostream & , bool = true ) override { return true ; } </s>

Add passes to the specified pass manager to get machine code emitted with the MCJIT .


<s> void rs6000_emit_le_vsx_move ( rtx dest , rtx source , machine_mode mode ) { gcc_assert ( ! BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P ( mode ) && ! TARGET_P9_VECTOR && ! gpr_or_gpr_p ( dest , source ) && ( MEM_P ( source ) ^ MEM_P ( dest ) ) ) ; if ( MEM_P ( source ) ) { gcc_assert ( REG_P ( dest ) || GET_CODE ( dest ) == SUBREG ) ; rs6000_emit_le_vsx_load ( dest , source , mode ) ; } else { if ( ! REG_P ( source ) ) source = force_reg ( mode , source ) ; rs6000_emit_le_vsx_store ( dest , source , mode ) ; } } </s>

Emit a sequence representing a little-endian VSX load or store , moving data from SOURCE to DEST in mode MODE . This is done separately from rs6000_emit_move to ensure it is called only during expand . LE VSX loads and stores introduced later are handled with a split . The expand-time RTL generation allows us to optimize away redundant pairs of register-permutes .


<s>
unsigned
ARM64MCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
else
{
assert
(
MO
.
isImm
(
)
&&
"did not expect relocated expression"
)
;
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
assert
(
0
&&
"Unable to encode MCOperand!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> bool MipsCCState :: originalTypeIsF128 ( const Type * Ty , const char * Func ) { if ( Ty -> isFP128Ty ( ) ) return true ; if ( Ty -> isStructTy ( ) && Ty -> getStructNumElements ( ) == 1 && Ty -> getStructElementType ( 0 ) -> isFP128Ty ( ) ) return true ; return ( Func && Ty -> isIntegerTy ( 128 ) && isF128SoftLibCall ( Func ) ) ; } </s>

This function returns true if Ty is fp128 , { f128 } or i128 which was originally a fp128 .


<s> static void set_pic_reg_ever_live ( ) { if ( reload_in_progress ) df_set_regs_ever_live ( REGNO ( pic_offset_table_rtx ) , true ) ; } </s>

Set regs_ever_live for PIC base address register to true if required .


<s> OperandMatchResultTy SystemZAsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { bool Result = ParseRegister ( RegNo , StartLoc , EndLoc , true ) ; bool PendingErrors = getParser ( ) . hasPendingError ( ) ; getParser ( ) . clearPendingErrors ( ) ; if ( PendingErrors ) return MatchOperand_ParseFail ; if ( Result ) return MatchOperand_NoMatch ; return MatchOperand_Success ; } </s>

tryParseRegister - parse one register if possible


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , TargetMachine & TM , bool IsLittle , const TargetOptions & Options ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , ARMProcClass ( None ) , stackAlignment ( 4 ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( Options ) , TargetABI ( ARM_ABI_UNKNOWN ) , DL ( computeDataLayout ( initializeSubtargetDependencies ( CPU , FS ) ) ) , TSInfo ( DL ) , JITInfo ( ) , InstrInfo ( isThumb1Only ( ) ? ( ARMBaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( ARMBaseInstrInfo * ) new ARMInstrInfo ( * this ) : ( ARMBaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM ) , FrameLowering ( ! isThumb1Only ( ) ? new ARMFrameLowering ( * this ) : ( ARMFrameLowering * ) new Thumb1FrameLowering ( * this ) ) { } </s>

This constructor initializes the data members to match that of the specified triple .

ARM ARM ARM ARM ARM ARM 4 ARM ARM ARM ARM ARM ARM ARM


<s> bool HexagonBitSimplify :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; auto & HST = MF . getSubtarget < HexagonSubtarget > ( ) ; auto & HRI = * HST . getRegisterInfo ( ) ; auto & HII = * HST . getInstrInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool Changed ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) ; const HexagonEvaluator HE ( HRI , MRI , HII , MF ) ; BitTracker BT ( HE , MF ) ; DEBUG ( BT . trace ( true ) ) ; BT . run ( ) ; MachineBasicBlock & Entry = MF . front ( ) ; RegisterSet AIG ; ConstGeneration ImmG ( BT , HII , MRI ) ; Changed |= visitBlock ( Entry , ImmG , AIG ) ; RegisterSet ARE ; RedundantInstrElimination RIE ( BT , HII , MRI ) ; bool Ried = visitBlock ( Entry , RIE , ARE ) ; if ( Ried ) { Changed = true ; BT . run ( ) ; } RegisterSet ACG ; CopyGeneration CopyG ( BT , HII , HRI , MRI ) ; Changed |= visitBlock ( Entry , CopyG , ACG ) ; RegisterSet ACP ; CopyPropagation CopyP ( HRI , MRI ) ; Changed |= visitBlock ( Entry , CopyP , ACP ) ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) || Changed ; BT . run ( ) ; RegisterSet ABS ; BitSimplification BitS ( BT , * MDT , HII , HRI , MRI , MF ) ; Changed |= visitBlock ( Entry , BitS , ABS ) ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) || Changed ; if ( Changed ) { for ( auto & B : MF ) for ( auto & I : B ) I . clearKillInfo ( ) ; DeadCodeElimination ( MF , * MDT ) . run ( ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool NVPTXAsmPrinter :: doFinalization ( Module & M ) { bool HasDebugInfo = MMI && MMI -> hasDebugInfo ( ) ; if ( ! GlobalsEmitted ) { emitGlobals ( M ) ; GlobalsEmitted = true ; } Module :: GlobalListType & global_list = M . getGlobalList ( ) ; int i , n = global_list . size ( ) ; GlobalVariable * * gv_array = new GlobalVariable * [ n ] ; i = 0 ; for ( Module :: global_iterator I = global_list . begin ( ) , E = global_list . end ( ) ; I != E ; ++ I ) gv_array [ i ++ ] = & * I ; while ( ! global_list . empty ( ) ) global_list . remove ( global_list . begin ( ) ) ; bool ret = AsmPrinter :: doFinalization ( M ) ; for ( i = 0 ; i < n ; i ++ ) global_list . insert ( global_list . end ( ) , gv_array [ i ] ) ; clearAnnotationCache ( & M ) ; delete [ ] gv_array ; if ( HasDebugInfo ) OutStreamer -> EmitRawText ( "//\t}" ) ; static_cast < NVPTXTargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) -> outputDwarfFileDirectives ( ) ; return ret ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> bool VESubtarget :: enableMachineScheduler ( ) const { return true ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


<s> bool AMDGPUCodeGenPrepare :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; const AMDGPUTargetMachine & TM = TPC -> getTM < AMDGPUTargetMachine > ( ) ; ST = & TM . getSubtarget < GCNSubtarget > ( F ) ; AC = & getAnalysis < AssumptionCacheTracker > ( ) . getAssumptionCache ( F ) ; DA = & getAnalysis < DivergenceAnalysis > ( ) ; HasUnsafeFPMath = hasUnsafeFPMath ( F ) ; AMDGPUASI = TM . getAMDGPUAS ( ) ; bool MadeChange = false ; for ( BasicBlock & BB : F ) { BasicBlock :: iterator Next ; for ( BasicBlock :: iterator I = BB . begin ( ) , E = BB . end ( ) ; I != E ; I = Next ) { Next = std :: next ( I ) ; MadeChange |= visit ( * I ) ; } } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


"Couldn't get MachineMemOperand for store to stack."

"Only support 4-byte stores to stack now."

"Only support GPR32 stores to stack now."

Store the specified register of the given register class to the specified stack frame index .


<s> bool AMDGPUTargetLowering :: ShouldShrinkFPConstant ( EVT VT ) const { EVT ScalarVT = VT . getScalarType ( ) ; return ( ScalarVT != MVT :: f32 && ScalarVT != MVT :: f64 ) ; } </s>

If true , then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime .


<s>
int
HexagonFrameLowering
::
getFrameIndexReference
(
const
MachineFunction
&
MF
,
int
FI
,
unsigned
&
FrameReg
)
const
{
auto
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
auto
&
HRI
=
*
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getRegisterInfo
(
)
;
int
Offset
=
MFI
.
getObjectOffset
(
FI
)
;
bool
HasAlloca
=
MFI
.
hasVarSizedObjects
(
)
;
bool
HasExtraAlign
=
HRI
.
needsStackRealignment
(
MF
)
;
bool
NoOpt
=
MF
.
getTarget
(
)
.
getOptLevel
(
)
==
CodeGenOpt
::
;
unsigned
SP
=
HRI
.
getStackRegister
(
)
,
FP
=
HRI
.
getFrameRegister
(
)
;
auto
&
HMFI
=
*
MF
.
getInfo
<
HexagonMachineFunctionInfo
>
(
)
;
unsigned
AP
=
HMFI
.
getStackAlignBasePhysReg
(
)
;
unsigned
FrameSize
=
MFI
.
getStackSize
(
)
;
bool
UseFP
=
false
,
UseAP
=
false
;
if
(
NoOpt
&&
!
HasExtraAlign
)
UseFP
=
true
;
if
(
MFI
.
isFixedObjectIndex
(
FI
)
||
MFI
.
isObjectPreAllocated
(
FI
)
)
{
UseFP
|=
(
HasAlloca
||
HasExtraAlign
)
;
}
else
{
if
(
HasAlloca
)
{
if
(
HasExtraAlign
)
UseAP
=
true
;
else
UseFP
=
true
;
}
}
bool
HasFP
=
hasFP
(
MF
)
;
assert
(
(
HasFP
||
!
UseFP
)
&&
"This function must have frame pointer"
)
;
if
(
Offset
>
0
&&
!
HasFP
)
Offset
-=
8
;
if
(
UseFP
)
FrameReg
=
FP
;
else
if
(
UseAP
)
FrameReg
=
AP
;
else
FrameReg
=
SP
;
int
RealOffset
=
Offset
;
if
(
!
UseFP
&&
!
UseAP
&&
HasFP
)
RealOffset
=
FrameSize
+
Offset
;
return
RealOffset
;
}
</s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .

Hexagon
Hexagon
Hexagon
Hexagon
"This function must have frame pointer"
0
8


<s>
void
TriCoreMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
if
(
Desc
.
getSize
(
)
!=
4
)
{
llvm_unreachable
(
"Unexpected instruction size!"
)
;
}
const
uint32_t
Binary
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
EmitConstant
(
Binary
,
Desc
.
getSize
(
)
,
OS
)
;
++
MCNumEmitted
;
}
</s>

TriCore
TriCore
4
"Unexpected instruction size!"