<s> static unsigned findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const TargetRegisterInfo & TRI , bool Is64Bit ) { const MachineFunction * MF = MBB . getParent ( ) ; const Function * F = MF -> getFunction ( ) ; if ( ! F || MF -> getMMI ( ) . callsEHReturn ( ) ) return 0 ; static const uint16_t CallerSavedRegs32Bit [ ] = { X86 :: EAX , X86 :: EDX , X86 :: ECX , 0 } ; static const uint16_t CallerSavedRegs64Bit [ ] = { X86 :: RAX , X86 :: RDX , X86 :: RCX , X86 :: RSI , X86 :: RDI , X86 :: R8 , X86 :: R9 , X86 :: R10 , X86 :: R11 , 0 } ; unsigned Opc = MBBI -> getOpcode ( ) ; switch ( Opc ) { default : return 0 ; case X86 :: RETL : case X86 :: RETQ : case X86 :: RETIL : case X86 :: RETIQ : case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: NACL_CG_TCRETURNdi64 : case X86 :: TCRETURNmi64 : case X86 :: EH_RETURN : case X86 :: EH_RETURN64 : { SmallSet < uint16_t , 8 > Uses ; for ( unsigned i = 0 , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , & TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } const uint16_t * CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit ; for ( ; * CS ; ++ CS ) if ( ! Uses . count ( * CS ) ) return * CS ; } } return 0 ; } </s>

findDeadCallerSavedReg - Return a caller-saved register that is n't live when it reaches the `` return '' instruction .


<s> static AMDGPUOperand :: Ptr CreateReg ( unsigned RegNo , SMLoc S , SMLoc E , const MCRegisterInfo * TRI , const MCSubtargetInfo * STI , bool ForceVOP3 ) { auto Op = llvm :: make_unique < AMDGPUOperand > ( Register ) ; Op -> Reg . RegNo = RegNo ; Op -> Reg . TRI = TRI ; Op -> Reg . STI = STI ; Op -> Reg . Mods = { false , false , false } ; Op -> Reg . IsForcedVOP3 = ForceVOP3 ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s>
SDValue
MSP430TargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
if
(
CallConv
==
CallingConv
::
MSP430_INTR
&&
!
Outs
.
empty
(
)
)
{
report_fatal_error
(
"ISRs cannot return any value"
)
;
return
SDValue
(
)
;
}
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_MSP430
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
if
(
RVLocs
[
i
]
.
isRegLoc
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
unsigned
Opc
=
(
CallConv
==
CallingConv
::
MSP430_INTR
MSP430ISD
::
RETI_FLAG
:
MSP430ISD
::
RET_FLAG
)
;
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
Opc
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
return
DAG
.
getNode
(
Opc
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> TargetLowering :: AtomicExpansionKind AArch64TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { if ( Subtarget -> hasLSE ( ) ) return AtomicExpansionKind :: None ; if ( getTargetMachine ( ) . getOptLevel ( ) == CodeGenOpt :: None ) return AtomicExpansionKind :: None ; return AtomicExpansionKind :: LLSC ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> bool ARMCallLowering :: lowerCall ( MachineIRBuilder & MIRBuilder , const MachineOperand & Callee , const ArgInfo & OrigRet , ArrayRef < ArgInfo > OrigArgs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; const auto & TLI = * getTLI < ARMTargetLowering > ( ) ; const auto & DL = MF . getDataLayout ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( MF . getSubtarget < ARMSubtarget > ( ) . genLongCalls ( ) ) return false ; MIRBuilder . buildInstr ( ARM :: ADJCALLSTACKDOWN ) . addImm ( 0 ) . add ( predOps ( ARMCC :: AL ) ) ; auto CallConv = MF . getFunction ( ) -> getCallingConv ( ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( ARM :: BLX ) . add ( Callee ) . addRegMask ( TRI -> getCallPreservedMask ( MF , CallConv ) ) ; SmallVector < ArgInfo , 8 > ArgInfos ; for ( auto Arg : OrigArgs ) { if ( ! isSupportedType ( DL , TLI , Arg . Ty ) ) return false ; if ( ! Arg . IsFixed ) return false ; splitToValueTypes ( Arg , ArgInfos , DL , MRI ) ; } auto ArgAssignFn = TLI . CCAssignFnForCall ( CallConv , false ) ; OutgoingValueHandler ArgHandler ( MIRBuilder , MRI , MIB , ArgAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( ! OrigRet . Ty -> isVoidTy ( ) ) { if ( ! isSupportedType ( DL , TLI , OrigRet . Ty ) ) return false ; ArgInfos . clear ( ) ; splitToValueTypes ( OrigRet , ArgInfos , DL , MRI ) ; auto RetAssignFn = TLI . CCAssignFnForReturn ( CallConv , false ) ; CallReturnHandler RetHandler ( MIRBuilder , MRI , MIB , RetAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , RetHandler ) ) return false ; } MIRBuilder . buildInstr ( ARM :: ADJCALLSTACKUP ) . addImm ( 0 ) . addImm ( 0 ) . add ( predOps ( ARMCC :: AL ) ) ; return true ; } </s>

This hook must be implemented to lower the given call instruction , including argument and return value marshalling .

ARM ARM ARM ARM ARM::ADJCALLSTACKDOWN 0 ARMCC::AL ARM::BLX 8 ARM::ADJCALLSTACKUP 0 0 ARMCC::AL


<s> static bool is_branch_slot_insn ( rtx_insn * insn ) { if ( ! insn || ! NONDEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; if ( rs6000_sched_groups ) { enum attr_type type = get_attr_type ( insn ) ; if ( type == TYPE_BRANCH || type == TYPE_JMPREG ) return true ; return false ; } return false ; } </s>

The function returns true if INSN can be issued only from the branch slot .


<s> MachineSDNode * SITargetLowering :: buildRSRC ( SelectionDAG & DAG , const SDLoc & DL , SDValue Ptr , uint32_t RsrcDword1 , uint64_t RsrcDword2And3 ) const { SDValue PtrLo = DAG . getTargetExtractSubreg ( AMDGPU :: sub0 , DL , MVT :: i32 , Ptr ) ; SDValue PtrHi = DAG . getTargetExtractSubreg ( AMDGPU :: sub1 , DL , MVT :: i32 , Ptr ) ; if ( RsrcDword1 ) { PtrHi = SDValue ( DAG . getMachineNode ( AMDGPU :: S_OR_B32 , DL , MVT :: i32 , PtrHi , DAG . getConstant ( RsrcDword1 , DL , MVT :: i32 ) ) , 0 ) ; } SDValue DataLo = buildSMovImm32 ( DAG , DL , RsrcDword2And3 & UINT64_C ( 0xFFFFFFFF ) ) ; SDValue DataHi = buildSMovImm32 ( DAG , DL , RsrcDword2And3 >> 32 ) ; const SDValue Ops [ ] = { DAG . getTargetConstant ( AMDGPU :: SReg_128RegClassID , DL , MVT :: i32 ) , PtrLo , DAG . getTargetConstant ( AMDGPU :: sub0 , DL , MVT :: i32 ) , PtrHi , DAG . getTargetConstant ( AMDGPU :: sub1 , DL , MVT :: i32 ) , DataLo , DAG . getTargetConstant ( AMDGPU :: sub2 , DL , MVT :: i32 ) , DataHi , DAG . getTargetConstant ( AMDGPU :: sub3 , DL , MVT :: i32 ) } ; return DAG . getMachineNode ( AMDGPU :: REG_SEQUENCE , DL , MVT :: v4i32 , Ops ) ; } </s>

Return a resource descriptor with the 'Add TID ' bit enabled The TID ( Thread ID ) is multiplied by the stride value ( bits [ 61:48 ] of the resource descriptor ) to create an offset , which is added to the resource pointer .


<s> unsigned RISCVInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : return 0 ; case RISCV :: SB : case RISCV :: SH : case RISCV :: SW : case RISCV :: FSW : case RISCV :: SD : case RISCV :: FSD : break ; } if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s>
void
cris_asm_output_symbol_ref
(
FILE
*
file
,
rtx
x
)
{
gcc_assert
(
GET_CODE
(
x
)
==
SYMBOL_REF
)
;
if
(
flag_pic
&&
in_code
>
0
)
{
const
char
*
origstr
=
XSTR
(
x
,
0
)
;
const
char
*
str
;
str
=
(
*
targetm
.
strip_name_encoding
)
(
origstr
)
;
assemble_name
(
file
,
str
)
;
if
(
!
current_function_uses_pic_offset_table
)
output_operand_lossage
(
"PIC register isn't set up"
)
;
}
else
assemble_name
(
file
,
XSTR
(
x
,
0
)
)
;
}
</s>

Worker function for ASM_OUTPUT_SYMBOL_REF .


Before rtl epilogue has been expanded , this function is used .


"\nStack information for function %s:\n"

Print debugging information for a frame .


A subroutine of expand_vec_perm_even_odd_1 . Implement extract-even and extract-odd permutations of two V32QImode and V16QImode operand with two vpshufb insns , vpor and vpermq . We should have already failed all two or three instruction sequences .


<s> static void aapcs_layout_arg ( CUMULATIVE_ARGS * pcum , machine_mode mode , const_tree type , bool named ) { int nregs , nregs2 ; int ncrn ; if ( pcum -> aapcs_arg_processed ) return ; pcum -> aapcs_arg_processed = true ; if ( ! named ) return ; if ( pcum -> pcs_variant != ARM_PCS_AAPCS ) { int slot = aapcs_select_call_coproc ( pcum , mode , type ) ; pcum -> aapcs_cprc_slot = slot ; if ( slot >= 0 ) { if ( ! pcum -> aapcs_cprc_failed [ slot ] ) { if ( aapcs_cp_arg_layout [ slot ] . allocate ( pcum , mode , type ) ) return ; pcum -> aapcs_cprc_failed [ slot ] = true ; pcum -> can_split = false ; } gcc_assert ( pcum -> can_split == false ) ; return ; } } ncrn = pcum -> aapcs_ncrn ; if ( ( ncrn & 1 ) && arm_needs_doubleword_align ( mode , type ) ) ncrn ++ ; nregs = ARM_NUM_REGS2 ( mode , type ) ; gcc_assert ( nregs >= 0 ) ; nregs2 = nregs ? nregs : 1 ; if ( ncrn + nregs2 <= NUM_ARG_REGS ) { pcum -> aapcs_reg = gen_rtx_REG ( mode , ncrn ) ; pcum -> aapcs_next_ncrn = ncrn + nregs ; return ; } if ( ncrn < NUM_ARG_REGS && pcum -> can_split ) { pcum -> aapcs_reg = gen_rtx_REG ( mode , ncrn ) ; pcum -> aapcs_next_ncrn = NUM_ARG_REGS ; pcum -> aapcs_partial = ( NUM_ARG_REGS - ncrn ) * UNITS_PER_WORD ; return ; } pcum -> aapcs_next_ncrn = NUM_ARG_REGS ; return ; } </s>

Lay out a function argument using the AAPCS rules . The rule numbers referred to here are those in the AAPCS .


"********** Prepare For LiveIntervals **********\n"

"LiveIntervals shouldn't be active yet!"

runOnMachineFunction - Emit the function body .


<s> unsigned getOpSize ( const MachineInstr & MI , unsigned OpNo ) const { return RI . getRegSizeInBits ( * getOpRegClass ( MI , OpNo ) ) / 8 ; } </s>

This form should usually be preferred since it handles operands with unknown register classes .


<s> void NyuziMCInstLower :: Initialize ( MCContext * C ) { Ctx = C ; } </s>

This method must be called before any actual lowering is done .


<s>
void
Z80RegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
MII
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
MachineInstr
&
MI
=
*
MII
;
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"\nFunction : "
<<
MF
.
getName
(
)
<<
"\n"
;
dbgs
(
)
<<
"<--------->\n"
<<
MI
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
uint64_t
StackSize
=
MF
.
getFrameInfo
(
)
.
getStackSize
(
)
;
int64_t
SPOffset
=
MF
.
getFrameInfo
(
)
.
getObjectOffset
(
FrameIndex
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"FrameIndex : "
<<
FrameIndex
<<
"\n"
<<
"spOffset   : "
<<
SPOffset
<<
"\n"
<<
"stackSize  : "
<<
StackSize
<<
"\n"
<<
"alignment  : "
<<
MF
.
getFrameInfo
(
)
.
getObjectAlignment
(
FrameIndex
)
<<
"\n"
)
;
unsigned
OpNo
=
FIOperandNum
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
.
getCalleeSavedInfo
(
)
;
int
MinCSFI
=
0
;
int
MaxCSFI
=
1
;
if
(
CSI
.
size
(
)
)
{
MinCSFI
=
CSI
[
0
]
.
getFrameIdx
(
)
;
MaxCSFI
=
CSI
[
CSI
.
size
(
)
1
]
.
getFrameIdx
(
)
;
}
unsigned
FrameReg
;
FrameReg
=
Z80
::
SP
;
int64_t
Offset
;
bool
IsKill
=
false
;
Offset
=
SPOffset
+
(
int64_t
)
StackSize
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Offset     : "
<<
Offset
<<
"\n"
<<
"<--------->\n"
)
;
const
Z80InstrInfo
&
TII
=
*
static_cast
<
const
Z80InstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
MI
.
getOperand
(
OpNo
)
.
ChangeToImmediate
(
Offset
)
;
assert
(
MI
.
getOpcode
(
)
==
Z80
::
LD16ri
&&
MI
.
getOperand
(
0
)
.
isReg
(
)
&&
MI
.
getOperand
(
0
)
.
getReg
(
)
==
Z80
::
HL
&&
"Constraints: EliminateFI"
)
;
std
::
advance
(
MII
,
1
)
;
BuildMI
(
MBB
,
MII
,
MI
.
getDebugLoc
(
)
,
TII
.
get
(
Z80
::
ADD16HLr
)
,
MI
.
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
.
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
FrameReg
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s>
void
NVPTXAsmPrinter
::
emitImplicitDef
(
const
MachineInstr
*
MI
)
const
{
unsigned
RegNo
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
const
TargetRegisterInfo
*
TRI
=
TM
.
getSubtargetImpl
(
)
->
getRegisterInfo
(
)
;
if
(
TRI
->
isVirtualRegister
(
RegNo
)
)
{
OutStreamer
.
AddComment
(
Twine
(
"implicit-def: "
)
+
getVirtualRegisterName
(
RegNo
)
)
;
}
else
{
OutStreamer
.
AddComment
(
Twine
(
"implicit-def: "
)
+
TM
.
getSubtargetImpl
(
)
->
getRegisterInfo
(
)
->
getName
(
RegNo
)
)
;
}
OutStreamer
.
AddBlankLine
(
)
;
}
</s>

Targets can override this to customize the output of IMPLICIT_DEF instructions in verbose mode .

NVPTX
NVPTX
0
"implicit-def: "
"implicit-def: "


<s> bool WinEHStatePass :: runOnFunction ( Function & F ) { if ( ! F . hasPersonalityFn ( ) ) return false ; PersonalityFn = dyn_cast < Function > ( F . getPersonalityFn ( ) -> stripPointerCasts ( ) ) ; if ( ! PersonalityFn ) return false ; Personality = classifyEHPersonality ( PersonalityFn ) ; if ( ! isFuncletEHPersonality ( Personality ) ) return false ; bool HasPads = false ; for ( BasicBlock & BB : F ) { if ( BB . isEHPad ( ) ) { HasPads = true ; break ; } } if ( ! HasPads ) return false ; F . addFnAttr ( "no-frame-pointer-elim" , "true" ) ; emitExceptionRegistrationRecord ( & F ) ; WinEHFuncInfo FuncInfo ; addStateStores ( F , FuncInfo ) ; PersonalityFn = nullptr ; Personality = EHPersonality :: Unknown ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> unsigned getElementSize ( ) const { assert ( Predicated ) ; return ElementSize ; } </s>

Return the size of an element read or written by Inst .


"attribute %<target%> argument not a string"

"invalid fpu for attribute(target(\"%s\"))"

"auto fpu selection not currently permitted here"

Inner function to process the attribute ( ( target ( ... ) ) ) , take an argument and set the current options from the argument . If we have a list , recursively go over the list .


<s> bool MipsAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> llvm :: FastISel * X86 :: createFastISel ( FunctionLoweringInfo & funcInfo ) { return new X86FastISel ( funcInfo ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> static rtx frv_expand_cut_builtin ( enum insn_code icode , tree arglist , rtx target ) { rtx pat ; rtx op0 = frv_read_argument ( & arglist ) ; rtx op1 = frv_read_argument ( & arglist ) ; rtx op2 ; target = frv_legitimize_target ( icode , target ) ; op0 = frv_int_to_acc ( icode , 1 , op0 ) ; if ( ! op0 ) return NULL_RTX ; if ( icode == CODE_FOR_mdcutssi || GET_CODE ( op1 ) == CONST_INT ) { if ( ! frv_check_constant_argument ( icode , 2 , op1 ) ) return NULL_RTX ; } else op1 = frv_legitimize_argument ( icode , 2 , op1 ) ; op2 = frv_matching_accg_for_acc ( op0 ) ; pat = GEN_FCN ( icode ) ( target , op0 , op1 , op2 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return target ; } </s>

Expand cut-style builtins , which take two operands and an implicit ACCG one .


<s> SparcSubtarget & SparcSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { UseSoftMulDiv = false ; IsV9 = false ; IsLeon = false ; V8DeprecatedInsts = false ; IsVIS = false ; IsVIS2 = false ; IsVIS3 = false ; HasHardQuad = false ; UsePopc = false ; UseSoftFloat = false ; HasNoFSMULD = false ; HasNoFMULS = false ; HasLeonCasa = false ; HasUmacSmac = false ; HasPWRPSR = false ; InsertNOPLoad = false ; FixAllFDIVSQRT = false ; DetectRoundChange = false ; HasLeonCycleCounter = false ; std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? "v9" : "v8" ; ParseSubtargetFeatures ( CPUName , CPUName , FS ) ; if ( ! IsV9 ) UsePopc = false ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> unsigned SIRegisterInfo :: getRegPressureSetLimit ( const MachineFunction & MF , unsigned Idx ) const { if ( Idx == getVGPRPressureSet ( ) || Idx == getAGPRPressureSet ( ) ) return getRegPressureLimit ( & AMDGPU :: VGPR_32RegClass , const_cast < MachineFunction & > ( MF ) ) ; if ( Idx == getSGPRPressureSet ( ) ) return getRegPressureLimit ( & AMDGPU :: SGPR_32RegClass , const_cast < MachineFunction & > ( MF ) ) ; return AMDGPUGenRegisterInfo :: getRegPressureSetLimit ( MF , Idx ) ; } </s>

Get the register unit pressure limit for this dimension .


<s> bool arm_output_addr_const_extra ( FILE * fp , rtx x ) { if ( GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNSPEC_TLS ) return arm_emit_tls_decoration ( fp , x ) ; else if ( GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNSPEC_PIC_LABEL ) { char label [ 256 ] ; int labelno = INTVAL ( XVECEXP ( x , 0 , 0 ) ) ; ASM_GENERATE_INTERNAL_LABEL ( label , "LPIC" , labelno ) ; assemble_name_raw ( fp , label ) ; return TRUE ; } else if ( GET_CODE ( x ) == CONST_VECTOR ) return arm_emit_vector_const ( fp , x ) ; return FALSE ; } </s>


<s> bool SystemZShortenInst :: processBlock ( MachineBasicBlock & MBB ) { bool Changed = false ; LiveRegs . clear ( ) ; LiveRegs . addLiveOuts ( MBB ) ; for ( auto MBBI = MBB . rbegin ( ) , MBBE = MBB . rend ( ) ; MBBI != MBBE ; ++ MBBI ) { MachineInstr & MI = * MBBI ; switch ( MI . getOpcode ( ) ) { case SystemZ :: IILF : Changed |= shortenIIF ( MI , SystemZ :: LLILL , SystemZ :: LLILH ) ; break ; case SystemZ :: IIHF : Changed |= shortenIIF ( MI , SystemZ :: LLIHL , SystemZ :: LLIHH ) ; break ; case SystemZ :: WFADB : Changed |= shortenOn001AddCC ( MI , SystemZ :: ADBR ) ; break ; case SystemZ :: WFDDB : Changed |= shortenOn001 ( MI , SystemZ :: DDBR ) ; break ; case SystemZ :: WFIDB : Changed |= shortenFPConv ( MI , SystemZ :: FIDBRA ) ; break ; case SystemZ :: WLDEB : Changed |= shortenOn01 ( MI , SystemZ :: LDEBR ) ; break ; case SystemZ :: WLEDB : Changed |= shortenFPConv ( MI , SystemZ :: LEDBRA ) ; break ; case SystemZ :: WFMDB : Changed |= shortenOn001 ( MI , SystemZ :: MDBR ) ; break ; case SystemZ :: WFLCDB : Changed |= shortenOn01 ( MI , SystemZ :: LCDFR ) ; break ; case SystemZ :: WFLNDB : Changed |= shortenOn01 ( MI , SystemZ :: LNDFR ) ; break ; case SystemZ :: WFLPDB : Changed |= shortenOn01 ( MI , SystemZ :: LPDFR ) ; break ; case SystemZ :: WFSQDB : Changed |= shortenOn01 ( MI , SystemZ :: SQDBR ) ; break ; case SystemZ :: WFSDB : Changed |= shortenOn001AddCC ( MI , SystemZ :: SDBR ) ; break ; case SystemZ :: WFCDB : Changed |= shortenOn01 ( MI , SystemZ :: CDBR ) ; break ; case SystemZ :: VL32 : Changed |= shortenOn0 ( MI , SystemZ :: LDE32 ) ; break ; case SystemZ :: VST32 : Changed |= shortenOn0 ( MI , SystemZ :: STE ) ; break ; case SystemZ :: VL64 : Changed |= shortenOn0 ( MI , SystemZ :: LD ) ; break ; case SystemZ :: VST64 : Changed |= shortenOn0 ( MI , SystemZ :: STD ) ; break ; } LiveRegs . stepBackward ( MI ) ; } return Changed ; } </s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .

SystemZ SystemZ SystemZ::IILF SystemZ::LLILL SystemZ::LLILH SystemZ::IIHF SystemZ::LLIHL SystemZ::LLIHH SystemZ::WFADB SystemZ::ADBR SystemZ::WFDDB SystemZ::DDBR SystemZ::WFIDB SystemZ::FIDBRA SystemZ::WLDEB SystemZ::LDEBR SystemZ::WLEDB SystemZ::LEDBRA SystemZ::WFMDB SystemZ::MDBR SystemZ::WFLCDB SystemZ::LCDFR SystemZ::WFLNDB SystemZ::LNDFR SystemZ::WFLPDB SystemZ::LPDFR SystemZ::WFSQDB SystemZ::SQDBR SystemZ::WFSDB SystemZ::SDBR SystemZ::WFCDB SystemZ::CDBR SystemZ::VL32 SystemZ::LDE32 SystemZ::VST32 SystemZ::STE SystemZ::VL64 SystemZ::LD SystemZ::VST64 SystemZ::STD


<s>
const
char
*
nds32_output_return
(
void
)
{
char
pattern
[
100
]
;
rtx
operands
[
2
]
;
int
re_callee_saved
=
cfun
->
machine
->
callee_saved_last_gpr_regno
;
int
sp_adjust
;
operands
[
0
]
=
gen_rtx_REG
(
SImode
,
re_callee_saved
)
;
sp_adjust
=
cfun
->
machine
->
local_size
+
cfun
->
machine
->
out_args_size
+
cfun
->
machine
->
callee_saved_area_gpr_padding_bytes
+
cfun
->
machine
->
callee_saved_fpr_regs_size
;
if
(
satisfies_constraint_Iu08
(
GEN_INT
(
sp_adjust
)
)
&&
NDS32_DOUBLE_WORD_ALIGN_P
(
sp_adjust
)
&&
!
cfun
->
calls_alloca
)
operands
[
1
]
=
GEN_INT
(
sp_adjust
)
;
else
operands
[
1
]
=
GEN_INT
(
0
)
;
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"pop25\t%%0, %%1"
)
;
output_asm_insn
(
pattern
,
operands
)
;
return
""
;
}
</s>


<s> static bool use_rsqrt_p ( machine_mode mode ) { return ( ! flag_trapping_math && flag_unsafe_math_optimizations && ( ( aarch64_tune_params . approx_modes -> recip_sqrt & AARCH64_APPROX_MODE ( mode ) ) || flag_mrecip_low_precision_sqrt ) ) ; } </s>

Return true if it is safe to use the rsqrt optabs to optimize 1.0/sqrt .


<s> static rtx_insn * find_last_same_clock ( rtx_insn * insn ) { rtx_insn * retval = insn ; rtx_insn * t = next_real_insn ( insn ) ; while ( t && GET_MODE ( t ) != TImode ) { if ( ! DEBUG_INSN_P ( t ) && recog_memoized ( t ) >= 0 ) retval = t ; t = next_real_insn ( t ) ; } return retval ; } </s>

Walk forward from INSN to find the last insn that issues in the same clock cycle .


<s> void AMDGPUTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , APInt & KnownZero , APInt & KnownOne , const SelectionDAG & DAG , unsigned Depth ) const { KnownZero = KnownOne = APInt ( KnownOne . getBitWidth ( ) , 0 ) ; APInt KnownZero2 ; APInt KnownOne2 ; unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { default : break ; case ISD :: INTRINSIC_WO_CHAIN : { switch ( cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ) { case AMDGPUIntrinsic :: AMDGPU_imax : case AMDGPUIntrinsic :: AMDGPU_umax : case AMDGPUIntrinsic :: AMDGPU_imin : case AMDGPUIntrinsic :: AMDGPU_umin : computeKnownBitsForMinMax ( Op . getOperand ( 1 ) , Op . getOperand ( 2 ) , KnownZero , KnownOne , DAG , Depth ) ; break ; default : break ; } break ; } case AMDGPUISD :: CARRY : case AMDGPUISD :: BORROW : { KnownZero = APInt :: getHighBitsSet ( 32 , 31 ) ; break ; } case AMDGPUISD :: BFE_I32 : case AMDGPUISD :: BFE_U32 : { ConstantSDNode * CWidth = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ; if ( ! CWidth ) return ; unsigned BitWidth = 32 ; uint32_t Width = CWidth -> getZExtValue ( ) & 0x1f ; if ( Opc == AMDGPUISD :: BFE_U32 ) KnownZero = APInt :: getHighBitsSet ( BitWidth , BitWidth - Width ) ; break ; } } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> machine_mode aarch64_hard_regno_caller_save_mode ( unsigned regno , unsigned nregs , machine_mode mode ) { if ( nregs == 1 && GET_MODE_SIZE ( mode ) <= 16 ) { if ( GET_MODE_SIZE ( mode ) >= 4 ) return mode ; else return SImode ; } else return choose_hard_reg_mode ( regno , nregs , false ) ; } </s>


<s> bool isVirtualSection ( ) const override { return false ; } </s>

Check whether this section is `` virtual '' , that is has no actual object file contents .


<s> bool CSKYAsmBackend :: fixupNeedsRelaxationAdvanced ( const MCFixup & Fixup , bool Resolved , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout , const bool WasForced ) const { if ( ! Resolved && ! WasForced ) return true ; int64_t Offset = int64_t ( Value ) ; switch ( Fixup . getTargetKind ( ) ) { default : return false ; case CSKY :: fixup_csky_pcrel_imm10_scale2 : return ! isShiftedInt < 10 , 1 > ( Offset ) ; case CSKY :: fixup_csky_pcrel_imm16_scale2 : return ! isShiftedInt < 16 , 1 > ( Offset ) ; case CSKY :: fixup_csky_pcrel_imm26_scale2 : return ! isShiftedInt < 26 , 1 > ( Offset ) ; case CSKY :: fixup_csky_pcrel_uimm7_scale4 : return ! isShiftedUInt < 8 , 2 > ( Offset ) ; } } </s>

Target specific predicate for whether a given fixup requires the associated instruction to be relaxed .


<s> void mips_split_move_insn ( rtx dest , rtx src , rtx insn ) { mips_split_move ( dest , src , mips_insn_split_type ( insn ) , insn ) ; } </s>

Split a move from SRC to DEST in INSN , given that mips_split_move_insn_p holds .


<s> const SNESSubtarget * SNESTargetMachine :: getSubtargetImpl ( const Function & ) const { return & SubTarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
unsigned
getReg
(
)
const
{
if
(
Kind
==
k_RegisterIndex
&&
RegIdx
.
Index
==
0
&&
RegIdx
.
Kind
&
RegKind_GPR
)
return
getGPR32Reg
(
)
;
assert
(
Kind
==
k_PhysRegister
&&
"Invalid access!"
)
;
return
PhysReg
.
Num
;
}
</s>

Returns the register associated with this edge .


<s> static void h8300_encode_section_info ( tree decl , rtx rtl , int first ) { int extra_flags = 0 ; default_encode_section_info ( decl , rtl , first ) ; if ( TREE_CODE ( decl ) == FUNCTION_DECL && h8300_funcvec_function_p ( decl ) ) extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION ; else if ( TREE_CODE ( decl ) == VAR_DECL && ( TREE_STATIC ( decl ) || DECL_EXTERNAL ( decl ) ) ) { if ( h8300_eightbit_data_p ( decl ) ) extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA ; else if ( first && h8300_tiny_data_p ( decl ) ) extra_flags = SYMBOL_FLAG_TINY_DATA ; } if ( extra_flags ) SYMBOL_REF_FLAGS ( XEXP ( rtl , 0 ) ) |= extra_flags ; } </s>

Mark function vectors , and various small data objects .


<s> SDValue AMDGPUTargetLowering :: getRecipEstimate ( SDValue Operand , DAGCombinerInfo & DCI , unsigned & RefinementSteps ) const { SelectionDAG & DAG = DCI . DAG ; EVT VT = Operand . getValueType ( ) ; if ( VT == MVT :: f32 ) { RefinementSteps = 0 ; return DAG . getNode ( AMDGPUISD :: RCP , SDLoc ( Operand ) , VT , Operand ) ; } return SDValue ( ) ; } </s>

Return a reciprocal estimate value for the input operand .


<s> static void mips_ls2_init_dfa_post_cycle_insn ( void ) { start_sequence ( ) ; emit_insn ( gen_ls2_alu1_turn_enabled_insn ( ) ) ; mips_ls2 . alu1_turn_enabled_insn = get_insns ( ) ; end_sequence ( ) ; start_sequence ( ) ; emit_insn ( gen_ls2_alu2_turn_enabled_insn ( ) ) ; mips_ls2 . alu2_turn_enabled_insn = get_insns ( ) ; end_sequence ( ) ; start_sequence ( ) ; emit_insn ( gen_ls2_falu1_turn_enabled_insn ( ) ) ; mips_ls2 . falu1_turn_enabled_insn = get_insns ( ) ; end_sequence ( ) ; start_sequence ( ) ; emit_insn ( gen_ls2_falu2_turn_enabled_insn ( ) ) ; mips_ls2 . falu2_turn_enabled_insn = get_insns ( ) ; end_sequence ( ) ; mips_ls2 . alu1_core_unit_code = get_cpu_unit_code ( "ls2_alu1_core" ) ; mips_ls2 . alu2_core_unit_code = get_cpu_unit_code ( "ls2_alu2_core" ) ; mips_ls2 . falu1_core_unit_code = get_cpu_unit_code ( "ls2_falu1_core" ) ; mips_ls2 . falu2_core_unit_code = get_cpu_unit_code ( "ls2_falu2_core" ) ; } </s>

Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2 .


<s> bool X86TargetLowering :: isVectorShiftByScalarCheap ( Type * Ty ) const { unsigned Bits = Ty -> getScalarSizeInBits ( ) ; if ( Bits == 8 ) return false ; if ( Subtarget -> hasInt256 ( ) && ( Bits == 32 || Bits == 64 ) ) return false ; return true ; } </s>

This is used to enable splatted operand transforms for vector shifts and vector funnel shifts .


<s> static enum unwind_info_type c6x_debug_unwind_info ( void ) { if ( flag_unwind_tables || flag_exceptions ) return UI_DWARF2 ; return default_debug_unwind_info ( ) ; } </s>

Target unwind frame info is generated from dwarf CFI directives , so always output dwarf2 unwind info .


"function_arg_pass_by_reference: V4 IEEE 128-bit\n"

"non-standard ABI extension with no compatibility "

A C expression that indicates when an argument must be passed by reference . If nonzero for an argument , a copy of that argument is made in memory and a pointer to the argument is passed instead of the argument itself . The pointer is passed in whatever way is appropriate for passing a pointer to that type . Under V.4 , aggregates and long double are passed by reference . As an extension to all 32-bit ABIs , AltiVec vectors are passed by reference unless the AltiVec vector extension ABI is in force . As an extension to all ABIs , variable sized types are passed by reference .


<s> TargetLowering :: AtomicExpansionKind AArch64TargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { if ( AI -> isFloatingPointOperation ( ) ) return AtomicExpansionKind :: CmpXChg ; unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size > 128 ) return AtomicExpansionKind :: None ; if ( AI -> getOperation ( ) == AtomicRMWInst :: Nand ) return AtomicExpansionKind :: LLSC ; return ( Subtarget -> hasLSE ( ) && Size < 128 ) ? AtomicExpansionKind :: None : AtomicExpansionKind :: LLSC ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ 0 ] . OperandType != MCOI :: OPERAND_PCREL ) return false ; int64_t Imm = Inst . getOperand ( 0 ) . getImm ( ) ; Target = Addr + Imm + 4 ; return true ; } </s>

Given a branch instruction try to get the address the branch targets .


<s> void SITypeRewriter :: visitCallInst ( CallInst & I ) { IRBuilder < > Builder ( & I ) ; SmallVector < Value * , 8 > Args ; SmallVector < Type * , 8 > Types ; bool NeedToReplace = false ; Function * F = I . getCalledFunction ( ) ; std :: string Name = F -> getName ( ) . str ( ) ; for ( unsigned i = 0 , e = I . getNumArgOperands ( ) ; i != e ; ++ i ) { Value * Arg = I . getArgOperand ( i ) ; if ( Arg -> getType ( ) == v16i8 ) { Args . push_back ( Builder . CreateBitCast ( Arg , i128 ) ) ; Types . push_back ( i128 ) ; NeedToReplace = true ; Name = Name + ".i128" ; } else if ( Arg -> getType ( ) -> isVectorTy ( ) && Arg -> getType ( ) -> getVectorNumElements ( ) == 1 && Arg -> getType ( ) -> getVectorElementType ( ) == Type :: getInt32Ty ( I . getContext ( ) ) ) { Type * ElementTy = Arg -> getType ( ) -> getVectorElementType ( ) ; std :: string TypeName = "i32" ; InsertElementInst * Def = dyn_cast < InsertElementInst > ( Arg ) ; assert ( Def ) ; Args . push_back ( Def -> getOperand ( 1 ) ) ; Types . push_back ( ElementTy ) ; std :: string VecTypeName = "v1" + TypeName ; Name = Name . replace ( Name . find ( VecTypeName ) , VecTypeName . length ( ) , TypeName ) ; NeedToReplace = true ; } else { Args . push_back ( Arg ) ; Types . push_back ( Arg -> getType ( ) ) ; } } if ( ! NeedToReplace ) { return ; } Function * NewF = Mod -> getFunction ( Name ) ; if ( ! NewF ) { NewF = Function :: Create ( FunctionType :: get ( F -> getReturnType ( ) , Types , false ) , GlobalValue :: ExternalLinkage , Name , Mod ) ; NewF -> setAttributes ( F -> getAttributes ( ) ) ; } I . replaceAllUsesWith ( Builder . CreateCall ( NewF , Args ) ) ; I . eraseFromParent ( ) ; } </s>


<s> bool MOSTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AddrSpace , Instruction * I ) const { if ( AM . Scale > 1 || AM . Scale < 0 ) return false ; if ( AM . Scale ) { assert ( AM . Scale == 1 ) ; if ( ! AM . HasBaseReg ) { if ( is8BitIndex ( AM . ScaleType ) ) return true ; return ! AM . BaseGV && 0 <= AM . BaseOffs && AM . BaseOffs < 256 ; } return ! AM . BaseGV && ! AM . BaseOffs && ( is8BitIndex ( AM . BaseType ) || is8BitIndex ( AM . ScaleType ) ) ; } if ( AM . HasBaseReg ) { if ( is8BitIndex ( AM . BaseType ) ) return true ; return ! AM . BaseGV && 0 <= AM . BaseOffs && AM . BaseOffs < 256 ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> static unsigned aarch64_add_stmt_cost ( void * data , int count , enum vect_cost_for_stmt kind , struct _stmt_vec_info * stmt_info , int misalign , enum vect_cost_model_location where ) { unsigned * cost = ( unsigned * ) data ; unsigned retval = 0 ; if ( flag_vect_cost_model ) { tree vectype = stmt_info ? stmt_vectype ( stmt_info ) : NULL_TREE ; int stmt_cost = aarch64_builtin_vectorization_cost ( kind , vectype , misalign ) ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( stmt_info ) ) { loop_vec_info loop_info = STMT_VINFO_LOOP_VINFO ( stmt_info ) ; struct loop * loop = LOOP_VINFO_LOOP ( loop_info ) ; unsigned nest_level = loop_depth ( loop ) ; count *= nest_level ; } retval = ( unsigned ) ( count * stmt_cost ) ; cost [ where ] += retval ; } return retval ; } </s>


<s>
void
ECLairMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
unsigned
Size
=
Desc
.
getSize
(
)
;
switch
(
Size
)
{
default
:
llvm_unreachable
(
"Unhandled encodeInstruction length!"
)
;
case
1
:
{
uint8_t
ByteBits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
support
::
endian
::
write
(
OS
,
ByteBits
,
support
::
big
)
;
break
;
}
case
2
:
{
uint16_t
WordBits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
support
::
endian
::
write
(
OS
,
WordBits
,
support
::
big
)
;
break
;
}
case
3
:
{
uint32_t
ByteWordBits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
uint8_t
OpcodeBits
=
(
ByteWordBits
>>
16
)
&
0xFF
;
uint16_t
ArgBits
=
ByteWordBits
&
0xFFFF
;
support
::
endian
::
write
(
OS
,
OpcodeBits
,
support
::
big
)
;
support
::
endian
::
write
(
OS
,
ArgBits
,
support
::
big
)
;
break
;
}
}
}
</s>

Encode the given Inst to bytes and append to CB .


<s> void SPUHazardRecognizer :: EmitInstruction ( SUnit * SU ) { } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> unsigned getJumpTableEncoding ( ) const override { return MachineJumpTableInfo :: EK_Custom32 ; } </s>

Return the entry encoding for a jump table in the current function .


<s> static rtx ia64_single_set ( rtx_insn * insn ) { rtx x = PATTERN ( insn ) , ret ; if ( GET_CODE ( x ) == COND_EXEC ) x = COND_EXEC_CODE ( x ) ; if ( GET_CODE ( x ) == SET ) return x ; switch ( recog_memoized ( insn ) ) { case CODE_FOR_prologue_allocate_stack : case CODE_FOR_prologue_allocate_stack_pr : case CODE_FOR_epilogue_deallocate_stack : case CODE_FOR_epilogue_deallocate_stack_pr : ret = XVECEXP ( x , 0 , 0 ) ; break ; default : ret = single_set_2 ( insn , x ) ; break ; } return ret ; } </s>

Helper function - like single_set , but look inside COND_EXEC .


<s> bool ARMAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AFI = MF . getInfo < ARMFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; Subtarget = & MF . getSubtarget < ARMSubtarget > ( ) ; SetupMachineFunction ( MF ) ; const Function * F = MF . getFunction ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; for ( auto * GV : AFI -> getGlobalsPromotedToConstantPool ( ) ) PromotedGlobals . insert ( GV ) ; unsigned OptimizationGoal ; if ( F -> hasFnAttribute ( Attribute :: OptimizeNone ) ) OptimizationGoal = 6 ; else if ( F -> optForMinSize ( ) ) OptimizationGoal = 4 ; else if ( F -> optForSize ( ) ) OptimizationGoal = 3 ; else if ( TM . getOptLevel ( ) == CodeGenOpt :: Aggressive ) OptimizationGoal = 2 ; else if ( TM . getOptLevel ( ) > CodeGenOpt :: None ) OptimizationGoal = 1 ; else OptimizationGoal = 5 ; if ( OptimizationGoals == - 1 ) OptimizationGoals = OptimizationGoal ; else if ( OptimizationGoals != ( int ) OptimizationGoal ) OptimizationGoals = 0 ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = F -> hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer -> EmitCOFFSymbolType ( Type ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; emitXRayTable ( ) ; if ( ! ThumbIndirectPads . empty ( ) ) { OutStreamer -> EmitAssemblerFlag ( MCAF_Code16 ) ; EmitAlignment ( 1 ) ; for ( std :: pair < unsigned , MCSymbol * > & TIP : ThumbIndirectPads ) { OutStreamer -> EmitLabel ( TIP . second ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( ARM :: tBX ) . addReg ( TIP . first ) . addImm ( ARMCC :: AL ) . addReg ( 0 ) ) ; } ThumbIndirectPads . clear ( ) ; } return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> static void normalize_bitfield_mem ( rtx * x , int * pos ) { rtx y ; if ( GET_CODE ( * x ) != MEM ) return ; y = XEXP ( * x , 0 ) ; if ( GET_CODE ( y ) == CONST ) y = XEXP ( y , 0 ) ; if ( GET_CODE ( y ) == PLUS ) { HOST_WIDE_INT i = INTVAL ( XEXP ( y , 1 ) ) ; HOST_WIDE_INT j = i % UNITS_PER_WORD ; if ( j != 0 ) { if ( j < 0 ) j += UNITS_PER_WORD ; * x = gen_rtx_MEM ( GET_MODE ( * x ) , plus_constant ( XEXP ( y , 0 ) , i - j ) ) ; * pos += BITS_PER_UNIT * j ; } } } </s>

* X is a ( 9-bit ) byte in memory and * POS is the first bit of a bitfield starting in * X . Modify * X and * POS such that * X is word aligned and * POS specifies the first bit , in the word that starts at * X , of the bitfield .


<s> WebAssemblyTargetMachine :: WebAssemblyTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT . isArch64Bit ( ) ? "e-p:64:64-i64:64-n32:64-S128" : "e-p:32:32-i64:64-n32:64-S128" , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < WebAssemblyTargetObjectFile > ( ) ) { initAsmInfo ( ) ; setRequiresStructuredCFG ( true ) ; } </s>

Create an WebAssembly architecture model .

WebAssembly WebAssembly WebAssembly "e-p:64:64-i64:64-n32:64-S128" "e-p:32:32-i64:64-n32:64-S128" WebAssembly


<s> bool MipsInstrInfo :: verifyInstruction ( const MachineInstr & MI , StringRef & ErrInfo ) const { switch ( MI . getOpcode ( ) ) { case Mips :: EXT : case Mips :: EXT_MM : case Mips :: INS : case Mips :: INS_MM : case Mips :: DINS : return verifyInsExtInstruction ( MI , ErrInfo , 0 , 32 , 0 , 32 , 0 , 32 ) ; case Mips :: DINSM : return verifyInsExtInstruction ( MI , ErrInfo , 0 , 32 , 1 , 64 , 32 , 64 ) ; case Mips :: DINSU : return verifyInsExtInstruction ( MI , ErrInfo , 32 , 64 , 0 , 32 , 32 , 64 ) ; case Mips :: DEXT : return verifyInsExtInstruction ( MI , ErrInfo , 0 , 32 , 0 , 32 , 0 , 63 ) ; case Mips :: DEXTM : return verifyInsExtInstruction ( MI , ErrInfo , 0 , 32 , 32 , 64 , 32 , 64 ) ; case Mips :: DEXTU : return verifyInsExtInstruction ( MI , ErrInfo , 32 , 64 , 0 , 32 , 32 , 64 ) ; default : return true ; } return true ; } </s>

Perform target-specific instruction verification .


<s>
const
MCSection
*
XCoreTargetObjectFile
::
getSectionForConstant
(
SectionKind
Kind
)
const
{
if
(
Kind
.
isMergeableConst4
(
)
)
return
MergeableConst4Section
;
if
(
Kind
.
isMergeableConst8
(
)
)
return
MergeableConst8Section
;
if
(
Kind
.
isMergeableConst16
(
)
)
return
MergeableConst16Section
;
assert
(
(
Kind
.
isReadOnly
(
)
||
Kind
.
isReadOnlyWithRel
(
)
)
&&
"Unknown section kind"
)
;
return
ReadOnlySection
;
}
</s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> static void th_mempair_save_regs ( rtx operands [ 4 ] ) { rtx set1 = gen_rtx_SET ( operands [ 0 ] , operands [ 1 ] ) ; rtx set2 = gen_rtx_SET ( operands [ 2 ] , operands [ 3 ] ) ; rtx insn = emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set1 , set2 ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_OFFSET , copy_rtx ( set1 ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , copy_rtx ( set2 ) ) ; } </s>

Similar like riscv_save_reg , but saves two registers to memory and marks the resulting instruction as frame-related .


<s> size_t size ( ) { switch ( type ( ) ) { case Scalar16 : return 2 ; case Scalar32 : return 4 ; case Scalar48 : case Vector48 : return 6 ; case Vector80 : return 10 ; default : return 2 ; } } </s>

The number of name/type pairs is returned .


<s> bool TPCResourceModel :: isResourceAvailable ( SUnit * SU ) { if ( ! SU || ! SU -> getInstr ( ) ) return false ; if ( ! SU -> getInstr ( ) -> isPseudo ( ) ) { if ( ! ResourcesModel -> canReserveResources ( * SU -> getInstr ( ) ) ) return false ; } for ( unsigned i = 0 , e = Packet . size ( ) ; i != e ; ++ i ) { if ( Packet [ i ] -> Succs . size ( ) == 0 ) continue ; for ( SUnit :: const_succ_iterator I = Packet [ i ] -> Succs . begin ( ) , E = Packet [ i ] -> Succs . end ( ) ; I != E ; ++ I ) { if ( I -> isCtrl ( ) ) continue ; if ( I -> getSUnit ( ) == SU ) return false ; } } return true ; } </s>

Check if scheduling of this SU is possible in the current packet .


"frame pointer should not have been eliminated"

"SecondSPAdjustAmount should be greater than zero"


<s>
static
void
output_restore
(
rtx
pat
)
{
rtx
operands
[
3
]
;
if
(
!
pat
)
{
fputs
(
"\t restore\n"
,
asm_out_file
)
;
return
;
}
gcc_assert
(
GET_CODE
(
pat
)
==
SET
)
;
operands
[
0
]
=
SET_DEST
(
pat
)
;
pat
=
SET_SRC
(
pat
)
;
switch
(
GET_CODE
(
pat
)
)
{
case
PLUS
:
operands
[
1
]
=
XEXP
(
pat
,
0
)
;
operands
[
2
]
=
XEXP
(
pat
,
1
)
;
output_asm_insn
(
" restore %r1, %2, %Y0"
,
operands
)
;
break
;
case
LO_SUM
:
operands
[
1
]
=
XEXP
(
pat
,
0
)
;
operands
[
2
]
=
XEXP
(
pat
,
1
)
;
output_asm_insn
(
" restore %r1, %%lo(%a2), %Y0"
,
operands
)
;
break
;
case
ASHIFT
:
operands
[
1
]
=
XEXP
(
pat
,
0
)
;
gcc_assert
(
XEXP
(
pat
,
1
)
==
const1_rtx
)
;
output_asm_insn
(
" restore %r1, %r1, %Y0"
,
operands
)
;
break
;
default
:
operands
[
1
]
=
pat
;
output_asm_insn
(
" restore %%g0, %1, %Y0"
,
operands
)
;
break
;
}
}
</s>


<s>
bool
RISCVSExtWRemoval
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
||
DisableSExtWRemoval
)
return
false
;
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
const
RISCVSubtarget
&
ST
=
MF
.
getSubtarget
<
RISCVSubtarget
>
(
)
;
if
(
!
ST
.
is64Bit
(
)
)
return
false
;
bool
MadeChange
=
false
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
for
(
auto
I
=
MBB
.
begin
(
)
,
IE
=
MBB
.
end
(
)
;
I
!=
IE
;
)
{
MachineInstr
*
MI
=
&
*
I
++
;
if
(
MI
->
getOpcode
(
)
!=
RISCV
::
ADDIW
||
!
MI
->
getOperand
(
2
)
.
isImm
(
)
||
MI
->
getOperand
(
2
)
.
getImm
(
)
!=
0
||
!
MI
->
getOperand
(
1
)
.
isReg
(
)
)
continue
;
Register
SrcReg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
if
(
!
SrcReg
.
isVirtual
(
)
)
continue
;
const
MachineInstr
&
SrcMI
=
*
MRI
.
getVRegDef
(
SrcReg
)
;
if
(
!
isSignExtendedW
(
SrcMI
,
MRI
)
)
continue
;
Register
DstReg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
if
(
!
MRI
.
constrainRegClass
(
SrcReg
,
MRI
.
getRegClass
(
DstReg
)
)
)
continue
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Removing redundant sign-extension\n"
)
;
MRI
.
replaceRegWith
(
DstReg
,
SrcReg
)
;
MRI
.
clearKillFlags
(
SrcReg
)
;
MI
->
eraseFromParent
(
)
;
++
NumRemovedSExtW
;
MadeChange
=
true
;
}
}
return
MadeChange
;
}
</s>


<s> void AMDGPUAsmPrinter :: emitFunctionBodyStart ( ) { const SIMachineFunctionInfo & MFI = * MF -> getInfo < SIMachineFunctionInfo > ( ) ; if ( ! MFI . isEntryFunction ( ) ) return ; const GCNSubtarget & STM = MF -> getSubtarget < GCNSubtarget > ( ) ; const Function & F = MF -> getFunction ( ) ; if ( ! STM . hasCodeObjectV3 ( ) && STM . isAmdHsaOrMesa ( F ) && ( F . getCallingConv ( ) == CallingConv :: AMDGPU_KERNEL || F . getCallingConv ( ) == CallingConv :: SPIR_KERNEL ) ) { amd_kernel_code_t KernelCode ; getAmdKernelCode ( KernelCode , CurrentProgramInfo , * MF ) ; getTargetStreamer ( ) -> EmitAMDKernelCodeT ( KernelCode ) ; } if ( STM . isAmdHsaOS ( ) ) HSAMetadataStream -> emitKernel ( * MF , CurrentProgramInfo ) ; } </s>

Targets can override this to emit stuff before the first basic block in the function .


<s> bool ARMBaseInstrInfo :: isSchedulingBoundary ( const MachineInstr * MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( MI -> isDebugValue ( ) ) return false ; if ( MI -> getDesc ( ) . isTerminator ( ) || MI -> isLabel ( ) ) return true ; MachineBasicBlock :: const_iterator I = MI ; while ( ++ I != MBB -> end ( ) && I -> isDebugValue ( ) ) ; if ( I != MBB -> end ( ) && I -> getOpcode ( ) == ARM :: t2IT ) return true ; if ( MI -> definesRegister ( ARM :: SP ) ) return true ; return false ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> void ix86_expand_lround ( rtx op0 , rtx op1 ) { machine_mode mode = GET_MODE ( op1 ) ; const struct real_format * fmt ; REAL_VALUE_TYPE pred_half , half_minus_pred_half ; rtx adj ; fmt = REAL_MODE_FORMAT ( mode ) ; real_2expN ( & half_minus_pred_half , - ( fmt -> p ) - 1 , mode ) ; REAL_ARITHMETIC ( pred_half , MINUS_EXPR , dconsthalf , half_minus_pred_half ) ; adj = force_reg ( mode , const_double_from_real_value ( pred_half , mode ) ) ; ix86_sse_copysign_to_positive ( adj , adj , force_reg ( mode , op1 ) , NULL_RTX ) ; adj = expand_simple_binop ( mode , PLUS , adj , op1 , NULL_RTX , 0 , OPTAB_DIRECT ) ; expand_fix ( op0 , adj , 0 ) ; } </s>

Expand SSE sequence for computing lround from OP1 storing into OP0 .


<s> const std :: string & AArch64CA53ErratumStub :: name ( ) const { return m_Name ; } </s>

Gets the name of the pass we are mixed into .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < Z80Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>


<s> static rtx arm_expand_ternop_builtin ( enum insn_code icode , tree exp , rtx target ) { rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , 0 ) ; tree arg1 = CALL_EXPR_ARG ( exp , 1 ) ; tree arg2 = CALL_EXPR_ARG ( exp , 2 ) ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; rtx op2 = expand_normal ( arg2 ) ; rtx op3 = NULL_RTX ; bool builtin_sha1cpm_p = false ; if ( insn_data [ icode ] . n_operands == 5 ) { gcc_assert ( icode == CODE_FOR_crypto_sha1c || icode == CODE_FOR_crypto_sha1p || icode == CODE_FOR_crypto_sha1m ) ; builtin_sha1cpm_p = true ; } machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; machine_mode mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ 2 ] . mode ; machine_mode mode2 = insn_data [ icode ] . operand [ 3 ] . mode ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( VECTOR_MODE_P ( mode2 ) ) op2 = safe_vector_operand ( op2 , mode2 ) ; if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; gcc_assert ( ( GET_MODE ( op0 ) == mode0 || GET_MODE ( op0 ) == VOIDmode ) && ( GET_MODE ( op1 ) == mode1 || GET_MODE ( op1 ) == VOIDmode ) && ( GET_MODE ( op2 ) == mode2 || GET_MODE ( op2 ) == VOIDmode ) ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ 2 ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; if ( ! ( * insn_data [ icode ] . operand [ 3 ] . predicate ) ( op2 , mode2 ) ) op2 = copy_to_mode_reg ( mode2 , op2 ) ; if ( builtin_sha1cpm_p ) op3 = GEN_INT ( TARGET_BIG_END ? 1 : 0 ) ; if ( builtin_sha1cpm_p ) pat = GEN_FCN ( icode ) ( target , op0 , op1 , op2 , op3 ) ; else pat = GEN_FCN ( icode ) ( target , op0 , op1 , op2 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>


<s> void LEGFrameLowering :: emitPrologue ( MachineFunction & MF ) const { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock & MBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = computeStackSize ( MF ) ; if ( ! StackSize ) { return ; } unsigned StackReg = LEG :: SP ; unsigned OffsetReg = materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ; if ( OffsetReg ) { BuildMI ( MBB , MBBI , dl , TII . get ( LEG :: SUBrr ) , StackReg ) . addReg ( StackReg ) . addReg ( OffsetReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( LEG :: SUBri ) , StackReg ) . addReg ( StackReg ) . addImm ( StackSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


"Following single-path roots were not found:\n"

"Single-path code generation failed due to "

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> WebAssemblyTargetMachine :: WebAssemblyTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT . isArch64Bit ( ) ? "e-m:e-p:64:64-i64:64-n32:64-S128" : "e-m:e-p:32:32-i64:64-n32:64-S128" , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < WebAssemblyTargetObjectFile > ( ) ) { this -> Options . TrapUnreachable = true ; initAsmInfo ( ) ; setRequiresStructuredCFG ( true ) ; } </s>

WebAssembly WebAssembly WebAssembly "e-m:e-p:64:64-i64:64-n32:64-S128" "e-m:e-p:32:32-i64:64-n32:64-S128" WebAssembly


<s> bool c6x_force_op_for_comparison_p ( enum rtx_code code , rtx op ) { if ( ! CONST_INT_P ( op ) || satisfies_constraint_Iu4 ( op ) ) return false ; if ( ( code == EQ || code == LT || code == GT ) && ! satisfies_constraint_Is5 ( op ) ) return true ; if ( ( code == GTU || code == LTU ) && ( ! TARGET_INSNS_64 || ! satisfies_constraint_Iu5 ( op ) ) ) return true ; return false ; } </s>

This function is called when we 're about to expand an integer compare operation which performs COMPARISON . It examines the second operand , and if it is an integer constant that can not be used directly on the current machine in a comparison insn , it returns true .


"Unable to find base and offset operands."


<s> bool CSKYAsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { if ( Fixup . getKind ( ) >= FirstLiteralRelocationKind ) return true ; switch ( Fixup . getTargetKind ( ) ) { default : break ; case CSKY :: fixup_csky_got32 : case CSKY :: fixup_csky_got_imm18_scale4 : case CSKY :: fixup_csky_gotoff : case CSKY :: fixup_csky_gotpc : case CSKY :: fixup_csky_plt32 : case CSKY :: fixup_csky_plt_imm18_scale4 : case CSKY :: fixup_csky_doffset_imm18 : case CSKY :: fixup_csky_doffset_imm18_scale2 : case CSKY :: fixup_csky_doffset_imm18_scale4 : return true ; } return false ; } </s>

Hook to check if a relocation is needed for some target specific reason .


<s>
bool
FISCDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_m
:
OutOps
.
push_back
(
Op
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .

FISC
FISC
"Unexpected asm memory constraint"


"Error: found feature bits in the ALL_FPU_INTERAL"

" group that are not defined by any FPU.\n"

Scan the static data tables generated by parsecpu.awk looking for potential issues with the data . Here we check for consistency between the fpu bits , in particular we check that ISA_ALL_FPU_INTERNAL does not contain a feature bit that is not defined by any FPU flag .


"MVP WebAssembly can only return up to one value"

"WebAssembly doesn't support non-C calling conventions"

"WebAssembly hasn't implemented inalloca results"

"WebAssembly hasn't implemented cons regs results"

"WebAssembly hasn't implemented cons regs last results"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s>
bool
AMDGPULegalizerInfo
::
legalizeCustom
(
MachineInstr
&
MI
,
MachineRegisterInfo
&
MRI
,
MachineIRBuilder
&
B
,
GISelChangeObserver
&
Observer
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
case
TargetOpcode
::
G_ADDRSPACE_CAST
:
return
legalizeAddrSpaceCast
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FRINT
:
return
legalizeFrint
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FCEIL
:
return
legalizeFceil
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_INTRINSIC_TRUNC
:
return
legalizeIntrinsicTrunc
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_SITOFP
:
return
legalizeITOFP
(
MI
,
MRI
,
B
,
true
)
;
case
TargetOpcode
::
G_UITOFP
:
return
legalizeITOFP
(
MI
,
MRI
,
B
,
false
)
;
case
TargetOpcode
::
G_FPTOSI
:
return
legalizeFPTOI
(
MI
,
MRI
,
B
,
true
)
;
case
TargetOpcode
::
G_FPTOUI
:
return
legalizeFPTOI
(
MI
,
MRI
,
B
,
false
)
;
case
TargetOpcode
::
G_FMINNUM
:
case
TargetOpcode
::
G_FMAXNUM
:
case
TargetOpcode
::
G_FMINNUM_IEEE
:
case
TargetOpcode
::
G_FMAXNUM_IEEE
:
return
legalizeMinNumMaxNum
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_EXTRACT_VECTOR_ELT
:
return
legalizeExtractVectorElt
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_INSERT_VECTOR_ELT
:
return
legalizeInsertVectorElt
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_SHUFFLE_VECTOR
:
return
legalizeShuffleVector
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FSIN
:
case
TargetOpcode
::
G_FCOS
:
return
legalizeSinCos
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_GLOBAL_VALUE
:
return
legalizeGlobalValue
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_LOAD
:
return
legalizeLoad
(
MI
,
MRI
,
B
,
Observer
)
;
case
TargetOpcode
::
G_FMAD
:
return
legalizeFMad
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FDIV
:
return
legalizeFDIV
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_UDIV
:
case
TargetOpcode
::
G_UREM
:
return
legalizeUDIV_UREM
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_SDIV
:
case
TargetOpcode
::
G_SREM
:
return
legalizeSDIV_SREM
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_ATOMIC_CMPXCHG
:
return
legalizeAtomicCmpXChg
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FLOG
:
return
legalizeFlog
(
MI
,
B
,
1.0f
/
numbers
::
log2ef
)
;
case
TargetOpcode
::
G_FLOG10
:
return
legalizeFlog
(
MI
,
B
,
numbers
::
ln2f
/
numbers
::
ln10f
)
;
case
TargetOpcode
::
G_FEXP
:
return
legalizeFExp
(
MI
,
B
)
;
case
TargetOpcode
::
G_FPOW
:
return
legalizeFPow
(
MI
,
B
)
;
case
TargetOpcode
::
G_FFLOOR
:
return
legalizeFFloor
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_BUILD_VECTOR
:
return
legalizeBuildVector
(
MI
,
MRI
,
B
)
;
default
:
return
false
;
}
llvm_unreachable
(
"expected switch to return"
)
;
}
</s>

Called for instructions with the Custom LegalizationAction .

AMDGPU
AMDGPU
SI
SI
SI
SI
1.0f
"expected switch to return"


"lowerToVVP called for unexpected SDNode."


"********** Replace Physical Registers **********\n"

"LiveIntervals shouldn't be active yet!"

runOnMachineFunction - Emit the function body .


<s> static struct machine_function * nds32_init_machine_status ( void ) { struct machine_function * machine ; machine = ggc_cleared_alloc < machine_function > ( ) ; machine -> use_eh_return_p = 0 ; machine -> naked_p = 0 ; machine -> fp_as_gp_p = 0 ; machine -> strict_aligned_p = 0 ; return machine ; } </s>

Function to save and restore machine-specific function data .


<s> static bool sh_cannot_substitute_mem_equiv_p ( rtx ) { return true ; } </s>

Return true if SUBST ca n't safely replace its equivalent during RA .


<s> void rs6000_xcoff_declare_object_name ( FILE * file , const char * name , tree decl ) { struct declare_alias_data data = { file , false } ; RS6000_OUTPUT_BASENAME ( file , name ) ; fputs ( ":\n" , file ) ; symtab_node :: get_create ( decl ) -> call_for_symbol_and_aliases ( rs6000_declare_alias , & data , true ) ; } </s>

This macro produces the initial definition of a object ( variable ) name . Because AIX assembler 's .set command has unexpected semantics , we output all aliases as alternative labels in front of the definition .


<s> static void loongarch_save_restore_reg ( machine_mode mode , int regno , HOST_WIDE_INT offset , loongarch_save_restore_fn fn ) { rtx mem ; mem = gen_frame_mem ( mode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; fn ( gen_rtx_REG ( mode , regno ) , mem ) ; } </s>

Use FN to save or restore register REGNO . MODE is the register 's mode and OFFSET is the offset of its save slot from the current stack pointer .


<s>
void
X86InstrInfo
::
genAlternativeCodeSequence
(
MachineInstr
&
Root
,
MachineCombinerPattern
::
MC_PATTERN
Pattern
,
SmallVectorImpl
<
MachineInstr
*
>
&
InsInstrs
,
SmallVectorImpl
<
MachineInstr
*
>
&
DelInstrs
,
DenseMap
<
unsigned
,
unsigned
>
&
InstIdxForVirtReg
)
const
{
MachineRegisterInfo
&
MRI
=
Root
.
getParent
(
)
->
getParent
(
)
->
getRegInfo
(
)
;
MachineInstr
*
Prev
=
nullptr
;
switch
(
Pattern
)
{
case
MachineCombinerPattern
::
MC_REASSOC_AX_BY
:
case
MachineCombinerPattern
::
MC_REASSOC_XA_BY
:
Prev
=
MRI
.
getUniqueVRegDef
(
Root
.
getOperand
(
1
)
.
getReg
(
)
)
;
break
;
case
MachineCombinerPattern
::
MC_REASSOC_AX_YB
:
case
MachineCombinerPattern
::
MC_REASSOC_XA_YB
:
Prev
=
MRI
.
getUniqueVRegDef
(
Root
.
getOperand
(
2
)
.
getReg
(
)
)
;
}
assert
(
Prev
&&
"Unknown pattern for machine combiner"
)
;
reassociateOps
(
Root
,
*
Prev
,
Pattern
,
InsInstrs
,
DelInstrs
,
InstIdxForVirtReg
)
;
return
;
}
</s>

When getMachineCombinerPatterns ( ) finds potential patterns , this function generates the instructions that could replace the original code sequence .


<s> static int ix86_value_regno ( enum machine_mode mode , tree func , tree fntype ) { gcc_assert ( ! TARGET_64BIT ) ; if ( ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == 8 ) ) return FIRST_MMX_REG ; if ( mode == TImode || ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == 16 ) ) return FIRST_SSE_REG ; if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT || ! TARGET_FLOAT_RETURNS_IN_80387 ) return 0 ; if ( ( func || fntype ) && ( mode == SFmode || mode == DFmode ) ) { int sse_level = ix86_function_sseregparm ( fntype , func ) ; if ( ( sse_level >= 1 && mode == SFmode ) || ( sse_level == 2 && mode == DFmode ) ) return FIRST_SSE_REG ; } return FIRST_FLOAT_REG ; } </s>

Given a mode , return the register to use for a return value .


"Operand must be a register when you're"

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static int c_number ( const char * a ) { int val = 0 ; if ( digit ( * a ) && ! digit ( * ( a - 1 ) ) ) { while ( digit ( * a ) ) val = 10 * val + ( * a ++ ) - '0' ; } return val ; } </s>

If A starts a group of digits , return their value as a number .


<s> bool canMergeStoresTo ( unsigned AddressSpace , EVT MemVT , const SelectionDAG & DAG ) const override { bool NoFloat = DAG . getMachineFunction ( ) . getFunction ( ) . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; if ( NoFloat ) return ( MemVT . getSizeInBits ( ) <= 64 ) ; return true ; } </s>

Returns if it 's reasonable to merge stores to MemVT size .


<s> static void split_delayed_insns ( void ) { rtx_insn * insn ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( JUMP_P ( insn ) || CALL_P ( insn ) ) split_delayed_branch ( insn ) ; } } </s>

Split every insn ( i.e . jumps and calls ) which can have delay slots into two parts : the first one is scheduled normally and emits the instruction , while the second one is a shadow insn which shows the side effect taking place . The second one is placed in the right cycle by the scheduler , but not emitted as an assembly instruction .


<s> BitVector RISCVRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , RISCV :: X0 ) ; markSuperRegs ( Reserved , RISCV :: X1 ) ; markSuperRegs ( Reserved , RISCV :: X2 ) ; markSuperRegs ( Reserved , RISCV :: X3 ) ; markSuperRegs ( Reserved , RISCV :: X4 ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , RISCV :: X8 ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void SystemZLDCleanup :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool X86TargetLowering :: isVectorShiftByScalarCheap ( Type * Ty ) const { unsigned Bits = Ty -> getScalarSizeInBits ( ) ; if ( Subtarget . hasXOP ( ) && ( Bits == 8 || Bits == 16 || Bits == 32 || Bits == 64 ) ) return false ; if ( Subtarget . hasAVX2 ( ) && ( Bits == 32 || Bits == 64 ) ) return false ; if ( Subtarget . hasBWI ( ) && Bits == 16 ) return false ; return true ; } </s>

This is used to enable splatted operand transforms for vector shifts and vector funnel shifts .


<s> const SISubtarget * GCNTargetMachine :: getSubtargetImpl ( const Function & F ) const { StringRef GPU = getGPUName ( F ) ; StringRef FS = getFeatureString ( F ) ; SmallString < 128 > SubtargetKey ( GPU ) ; SubtargetKey . append ( FS ) ; auto & I = SubtargetMap [ SubtargetKey ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < SISubtarget > ( TargetTriple , GPU , FS , * this ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; SIGISelActualAccessor * GISel = new SIGISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new AMDGPUCallLowering ( * I -> getTargetLowering ( ) ) ) ; I -> setGISelAccessor ( * GISel ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> void HexagonShuffler :: reset ( ) { Packet . clear ( ) ; BundleFlags = 0 ; Error = SHUFFLE_SUCCESS ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s> virtual const rvexSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>


<s> unsigned X86TargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { unsigned VTBits = Op . getScalarValueSizeInBits ( ) ; unsigned Opcode = Op . getOpcode ( ) ; switch ( Opcode ) { case X86ISD :: SETCC_CARRY : return VTBits ; case X86ISD :: VSEXT : { SDValue Src = Op . getOperand ( 0 ) ; unsigned Tmp = DAG . ComputeNumSignBits ( Src , Depth + 1 ) ; Tmp += VTBits - Src . getScalarValueSizeInBits ( ) ; return Tmp ; } case X86ISD :: VSHLI : { SDValue Src = Op . getOperand ( 0 ) ; unsigned Tmp = DAG . ComputeNumSignBits ( Src , Depth + 1 ) ; APInt ShiftVal = cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) -> getAPIntValue ( ) ; if ( ShiftVal . uge ( VTBits ) ) return VTBits ; if ( ShiftVal . uge ( Tmp ) ) return 1 ; return Tmp - ShiftVal . getZExtValue ( ) ; } case X86ISD :: VSRAI : { SDValue Src = Op . getOperand ( 0 ) ; unsigned Tmp = DAG . ComputeNumSignBits ( Src , Depth + 1 ) ; APInt ShiftVal = cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) -> getAPIntValue ( ) ; ShiftVal += Tmp ; return ShiftVal . uge ( VTBits ) ? VTBits : ShiftVal . getZExtValue ( ) ; } case X86ISD :: PCMPGT : case X86ISD :: PCMPEQ : case X86ISD :: CMPP : case X86ISD :: VPCOM : case X86ISD :: VPCOMU : return VTBits ; } return 1 ; } </s>

Determine the number of bits in the operation that are sign bits .


<s> bool BPFAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; printOperand ( MI , OpNo , O ) ; return false ; } </s>


<s> void handle_arm_neon_h ( void ) { aarch64_simd_switcher simd ; for ( unsigned int i = 0 ; i < ARM_NEON_H_TYPES_LAST ; i ++ ) for ( unsigned int count = 2 ; count <= 4 ; ++ count ) if ( ! aarch64_scalar_builtin_type_p ( aarch64_simd_types [ i ] . type ) ) register_tuple_type ( count , i ) ; aarch64_init_simd_builtin_functions ( true ) ; aarch64_init_simd_intrinsics ( ) ; } </s>

Implement # pragma GCC aarch64 `` arm_neon.h '' . The types and functions defined here need to be available internally during LTO as well .


Write the extra assembler code needed to declare a function properly .


<s> bool SIRegisterInfo :: requiresFrameIndexReplacementScavenging ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MFI . hasStackObjects ( ) ; } </s>

Returns true if the target requires using the RegScavenger directly for frame elimination despite using requiresFrameIndexScavenging .


"Cannot load this register from stack slot!"

Load the specified register of the given register class from the specified stack frame index .


<s> void HexagonAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst MCB = HexagonMCInstrInfo :: createBundle ( ) ; const MCInstrInfo & MCII = * Subtarget -> getInstrInfo ( ) ; if ( MI -> isBundle ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI -> getIterator ( ) ; unsigned IgnoreCount = 0 ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( MII -> getOpcode ( ) == TargetOpcode :: DBG_VALUE || MII -> getOpcode ( ) == TargetOpcode :: IMPLICIT_DEF ) ++ IgnoreCount ; else HexagonLowerToMC ( MCII , & * MII , MCB , * this ) ; } else HexagonLowerToMC ( MCII , MI , MCB , * this ) ; bool Ok = HexagonMCInstrInfo :: canonicalizePacket ( MCII , * Subtarget , OutStreamer -> getContext ( ) , MCB , nullptr ) ; assert ( Ok ) ; ( void ) Ok ; if ( HexagonMCInstrInfo :: bundleSize ( MCB ) == 0 ) return ; OutStreamer -> EmitInstruction ( MCB , getSubtargetInfo ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .

Hexagon Hexagon Hexagon 0 Hexagon Hexagon Hexagon Hexagon 0


<s> bool DataFlowGraph :: alias ( RegisterRef RA , RegisterRef RB ) const { assert ( TargetRegisterInfo :: isPhysicalRegister ( RA . Reg ) ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( RB . Reg ) ) ; MCRegUnitMaskIterator UMA ( RA . Reg , & TRI ) ; MCRegUnitMaskIterator UMB ( RB . Reg , & TRI ) ; while ( UMA . isValid ( ) && UMB . isValid ( ) ) { std :: pair < uint32_t , LaneBitmask > PA = * UMA ; std :: pair < uint32_t , LaneBitmask > PB = * UMB ; if ( PA . first == PB . first ) { if ( PA . second . none ( ) || PB . second . none ( ) ) return true ; LaneBitmask LA = PA . second & RA . Mask ; LaneBitmask LB = PB . second & RB . Mask ; if ( LA . any ( ) && LB . any ( ) ) { unsigned Root = * MCRegUnitRootIterator ( PA . first , & TRI ) ; uint32_t SubA = TRI . getSubRegIndex ( RA . Reg , Root ) ; uint32_t SubB = TRI . getSubRegIndex ( RB . Reg , Root ) ; const TargetRegisterClass & RC = * TRI . getMinimalPhysRegClass ( Root ) ; LaneBitmask MaskA = TRI . reverseComposeSubRegIndexLaneMask ( SubA , LA ) ; LaneBitmask MaskB = TRI . reverseComposeSubRegIndexLaneMask ( SubB , LB ) ; if ( ( MaskA & MaskB & RC . LaneMask ) . any ( ) ) return true ; } ++ UMA ; ++ UMB ; continue ; } if ( PA . first < PB . first ) ++ UMA ; else if ( PB . first < PA . first ) ++ UMB ; } return false ; } </s>

alias - If one of the pointers is to a global that we are tracking , and the other is some random pointer , we know there can not be an alias , because the address of the global is n't taken .


<s> bool rs6000_is_valid_insert_mask ( rtx mask , rtx shift , machine_mode mode ) { int nb , ne ; if ( ! rs6000_is_valid_mask ( mask , & nb , & ne , mode ) ) return false ; int n = GET_MODE_PRECISION ( mode ) ; int sh = INTVAL ( XEXP ( shift , 1 ) ) ; if ( sh < 0 || sh >= n ) return false ; rtx_code code = GET_CODE ( shift ) ; if ( sh == 0 ) code = ROTATE ; if ( code == ROTATE && sh >= 0 && nb >= ne && ne >= sh ) code = ASHIFT ; if ( code == ROTATE && sh >= 0 && nb >= ne && nb < sh ) { code = LSHIFTRT ; sh = n - sh ; } if ( mode == DImode && code == ROTATE ) return ( ne == sh ) ; if ( mode == SImode && code == ROTATE ) return ( nb < 32 && ne < 32 && sh < 32 ) ; if ( ne > nb ) return false ; if ( code == ASHIFT && ne < sh ) return false ; if ( nb < 32 && ne < 32 && sh < 32 && ! ( code == LSHIFTRT && nb >= 32 - sh ) ) return true ; if ( code == LSHIFTRT ) sh = 64 - sh ; if ( ne == sh ) return ! ( code == LSHIFTRT && nb >= sh ) ; return false ; } </s>

Return whether MASK ( a CONST_INT ) is a valid mask for any rlwimi or rldimi instruction , to implement an insert with shift SHIFT ( a ROTATE , ASHIFT , or LSHIFTRT ) in mode MODE .


<s> void pass_vsetvl :: emit_local_forward_vsetvls ( const bb_info * bb ) { auto & block_info = m_vector_manager -> vector_block_infos [ bb -> index ( ) ] ; if ( block_info . local_dem . empty_p ( ) ) return ; vector_insn_info curr_info ; for ( insn_info * insn : bb -> real_nondebug_insns ( ) ) { const vector_insn_info prev_info = curr_info ; enum vsetvl_type type = NUM_VSETVL_TYPE ; transfer_before ( curr_info , insn ) ; if ( has_vtype_op ( insn -> rtl ( ) ) ) { if ( static_cast < const vl_vtype_info & > ( prev_info ) != static_cast < const vl_vtype_info & > ( curr_info ) ) { const auto require = m_vector_manager -> vector_insn_infos [ insn -> uid ( ) ] ; if ( ! require . compatible_p ( static_cast < const vl_vtype_info & > ( prev_info ) ) ) type = insert_vsetvl ( EMIT_BEFORE , insn -> rtl ( ) , require , prev_info ) ; } } if ( type == VSETVL_VTYPE_CHANGE_ONLY ) { curr_info . set_avl_info ( prev_info . get_avl_info ( ) ) ; } transfer_after ( curr_info , insn ) ; } block_info . reaching_out = curr_info ; } </s>

Emit vsetvl within each block by forward data-flow analysis .


<s>
void
assignValueToReg
(
unsigned
ValVReg
,
unsigned
PhysReg
,
CCValAssign
&
VA
)
override
{
assert
(
VA
.
isRegLoc
(
)
&&
"Value shouldn't be assigned to reg"
)
;
assert
(
VA
.
getLocReg
(
)
==
PhysReg
&&
"Assigning to the wrong reg?"
)
;
assert
(
VA
.
getValVT
(
)
.
getSizeInBits
(
)
<=
64
&&
"Unsupported value size"
)
;
assert
(
VA
.
getLocVT
(
)
.
getSizeInBits
(
)
<=
64
&&
"Unsupported location size"
)
;
markPhysRegUsed
(
PhysReg
)
;
MIRBuilder
.
buildCopy
(
ValVReg
,
PhysReg
)
;
}
</s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .

ARM
"Value shouldn't be assigned to reg"
"Assigning to the wrong reg?"
64
"Unsupported value size"
64
"Unsupported location size"


<s>
unsigned
ARMBaseInstrInfo
::
getNumMicroOps
(
const
InstrItineraryData
*
ItinData
,
const
MachineInstr
*
MI
)
const
{
if
(
!
ItinData
||
ItinData
->
isEmpty
(
)
)
return
1
;
const
MCInstrDesc
&
Desc
=
MI
->
getDesc
(
)
;
unsigned
Class
=
Desc
.
getSchedClass
(
)
;
unsigned
UOps
=
ItinData
->
Itineraries
[
Class
]
.
NumMicroOps
;
if
(
UOps
)
return
UOps
;
unsigned
Opc
=
MI
->
getOpcode
(
)
;
switch
(
Opc
)
{
default
:
llvm_unreachable
(
"Unexpected multi-uops instruction!"
)
;
break
;
case
ARM
::
VLDMQIA
:
case
ARM
::
VSTMQIA
:
return
2
;
case
ARM
::
VLDMDIA
:
case
ARM
::
VLDMDIA_UPD
:
case
ARM
::
VLDMDDB_UPD
:
case
ARM
::
VLDMSIA
:
case
ARM
::
VLDMSIA_UPD
:
case
ARM
::
VLDMSDB_UPD
:
case
ARM
::
VSTMDIA
:
case
ARM
::
VSTMDIA_UPD
:
case
ARM
::
VSTMDDB_UPD
:
case
ARM
::
VSTMSIA
:
case
ARM
::
VSTMSIA_UPD
:
case
ARM
::
VSTMSDB_UPD
:
{
unsigned
NumRegs
=
MI
->
getNumOperands
(
)
Desc
.
getNumOperands
(
)
;
return
(
NumRegs
/
2
)
+
(
NumRegs
%
2
)
+
1
;
}
case
ARM
::
LDMIA_RET
:
case
ARM
::
LDMIA
:
case
ARM
::
LDMDA
:
case
ARM
::
LDMDB
:
case
ARM
::
LDMIB
:
case
ARM
::
LDMIA_UPD
:
case
ARM
::
LDMDA_UPD
:
case
ARM
::
LDMDB_UPD
:
case
ARM
::
LDMIB_UPD
:
case
ARM
::
STMIA
:
case
ARM
::
STMDA
:
case
ARM
::
STMDB
:
case
ARM
::
STMIB
:
case
ARM
::
STMIA_UPD
:
case
ARM
::
STMDA_UPD
:
case
ARM
::
STMDB_UPD
:
case
ARM
::
STMIB_UPD
:
case
ARM
::
tLDMIA
:
case
ARM
::
tLDMIA_UPD
:
case
ARM
::
tSTMIA_UPD
:
case
ARM
::
tPOP_RET
:
case
ARM
::
tPOP
:
case
ARM
::
tPUSH
:
case
ARM
::
t2LDMIA_RET
:
case
ARM
::
t2LDMIA
:
case
ARM
::
t2LDMDB
:
case
ARM
::
t2LDMIA_UPD
:
case
ARM
::
t2LDMDB_UPD
:
case
ARM
::
t2STMIA
:
case
ARM
::
t2STMDB
:
case
ARM
::
t2STMIA_UPD
:
case
ARM
::
t2STMDB_UPD
:
{
unsigned
NumRegs
=
MI
->
getNumOperands
(
)
Desc
.
getNumOperands
(
)
+
1
;
if
(
Subtarget
.
isCortexA8
(
)
)
{
if
(
NumRegs
<
4
)
return
2
;
UOps
=
(
NumRegs
/
2
)
;
if
(
NumRegs
%
2
)
++
UOps
;
return
UOps
;
}
else
if
(
Subtarget
.
isCortexA9
(
)
)
{
UOps
=
(
NumRegs
/
2
)
;
if
(
(
NumRegs
%
2
)
||
!
MI
->
hasOneMemOperand
(
)
||
(
*
MI
->
memoperands_begin
(
)
)
->
getAlignment
(
)
<
8
)
++
UOps
;
return
UOps
;
}
else
{
return
NumRegs
;
}
}
}
}
</s>

Return the number of issue slots required for this MI .


<s> int small_data_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { if ( ! TARGET_SDATA_USE ) return 0 ; if ( GET_CODE ( op ) == SYMBOL_REF ) return SYMBOL_REF_SMALL_P ( op ) ; if ( GET_CODE ( op ) == CONST && GET_CODE ( XEXP ( op , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( op , 0 ) , 0 ) ) == SYMBOL_REF && GET_CODE ( XEXP ( XEXP ( op , 0 ) , 1 ) ) == CONST_INT && INT16_P ( INTVAL ( XEXP ( XEXP ( op , 0 ) , 1 ) ) ) ) return SYMBOL_REF_SMALL_P ( XEXP ( XEXP ( op , 0 ) , 0 ) ) ; return 0 ; } </s>

Return 1 for an operand in small memory on V.4/eabi .


<s> bool MipsAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( Count % 4 ) return false ; uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> Write32 ( 0 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> bool supportSplitCSR ( MachineFunction * MF ) const override { return MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: CXX_FAST_TLS && MF -> getFunction ( ) -> hasFnAttribute ( Attribute :: NoUnwind ) ; } </s>

Return true if the target supports that a subset of CSRs for the given machine function is handled explicitly via copies .


<s> static bool aarch64_modifies_global_state_p ( aarch64_simd_builtin_datum * d ) { unsigned int flags = aarch64_call_properties ( d ) ; if ( flags & FLAG_RAISE_FP_EXCEPTIONS ) return true ; if ( flags & FLAG_PREFETCH_MEMORY ) return true ; return flags & FLAG_WRITE_MEMORY ; } </s>

Return true if calls to the function could modify some form of global state .


<s> SDValue SITargetLowering :: handleD16VData ( SDValue VData , SelectionDAG & DAG , bool ImageStore ) const { EVT StoreVT = VData . getValueType ( ) ; if ( ! StoreVT . isVector ( ) ) return VData ; SDLoc DL ( VData ) ; unsigned NumElements = StoreVT . getVectorNumElements ( ) ; if ( Subtarget -> hasUnpackedD16VMem ( ) ) { EVT IntStoreVT = StoreVT . changeTypeToInteger ( ) ; SDValue IntVData = DAG . getNode ( ISD :: BITCAST , DL , IntStoreVT , VData ) ; EVT EquivStoreVT = EVT :: getVectorVT ( * DAG . getContext ( ) , MVT :: i32 , NumElements ) ; SDValue ZExt = DAG . getNode ( ISD :: ZERO_EXTEND , DL , EquivStoreVT , IntVData ) ; return DAG . UnrollVectorOp ( ZExt . getNode ( ) ) ; } else if ( NumElements == 3 ) { EVT IntStoreVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , StoreVT . getStoreSizeInBits ( ) ) ; SDValue IntVData = DAG . getNode ( ISD :: BITCAST , DL , IntStoreVT , VData ) ; EVT WidenedStoreVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StoreVT . getVectorElementType ( ) , NumElements + 1 ) ; EVT WidenedIntVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , WidenedStoreVT . getStoreSizeInBits ( ) ) ; SDValue ZExt = DAG . getNode ( ISD :: ZERO_EXTEND , DL , WidenedIntVT , IntVData ) ; return DAG . getNode ( ISD :: BITCAST , DL , WidenedStoreVT , ZExt ) ; } if ( ImageStore && Subtarget -> hasImageStoreD16Bug ( ) ) { EVT IntStoreVT = StoreVT . changeTypeToInteger ( ) ; SDValue IntVData = DAG . getNode ( ISD :: BITCAST , DL , IntStoreVT , VData ) ; SmallVector < SDValue , 4 > Elts ; DAG . ExtractVectorElements ( IntVData , Elts ) ; SmallVector < SDValue , 4 > PackedElts ; for ( unsigned I = 0 ; I < Elts . size ( ) / 2 ; I += 1 ) { SDValue Pair = DAG . getBuildVector ( MVT :: v2i16 , DL , { Elts [ I * 2 ] , Elts [ I * 2 + 1 ] } ) ; SDValue IntPair = DAG . getNode ( ISD :: BITCAST , DL , MVT :: i32 , Pair ) ; PackedElts . push_back ( IntPair ) ; } PackedElts . resize ( PackedElts . size ( ) * 2 , DAG . getUNDEF ( MVT :: i32 ) ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , MVT :: i32 , PackedElts . size ( ) ) ; return DAG . getBuildVector ( VecVT , DL , PackedElts ) ; } assert ( isTypeLegal ( StoreVT ) ) ; return VData ; } </s>

Handle register layout difference for f16 images for some subtargets .


<s> void PPCELFStreamer :: emitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) { PPCMCCodeEmitter * Emitter = static_cast < PPCMCCodeEmitter * > ( getAssembler ( ) . getEmitterPtr ( ) ) ; if ( ! Emitter -> isPrefixedInstruction ( Inst ) ) { MCELFStreamer :: emitInstruction ( Inst , STI ) ; return ; } emitPrefixedInstruction ( Inst , STI ) ; } </s>

Targets should implement this to emit instructions .


<s>
static
void
rl78_start_function
(
FILE
*
file
)
{
int
i
;
add_vector_labels
(
file
,
"interrupt"
)
;
add_vector_labels
(
file
,
"vector"
)
;
if
(
cfun
->
machine
->
framesize
==
0
)
return
;
fprintf
(
file
,
"\t; start of function\n"
)
;
if
(
cfun
->
machine
->
framesize_regs
)
{
fprintf
(
file
,
"\t; push %d:"
,
cfun
->
machine
->
framesize_regs
)
;
for
(
i
=
0
;
i
<
16
;
i
++
)
if
(
cfun
->
machine
->
need_to_push
[
i
]
)
fprintf
(
file
,
" %s"
,
word_regnames
[
i
*
2
]
)
;
fprintf
(
file
,
"\n"
)
;
}
if
(
frame_pointer_needed
)
fprintf
(
file
,
"\t; $fp points here (r22)\n"
)
;
if
(
cfun
->
machine
->
framesize_locals
)
fprintf
(
file
,
"\t; locals: %d byte%s\n"
,
cfun
->
machine
->
framesize_locals
,
cfun
->
machine
->
framesize_locals
==
1
""
:
"s"
)
;
if
(
cfun
->
machine
->
framesize_outgoing
)
fprintf
(
file
,
"\t; outgoing: %d byte%s\n"
,
cfun
->
machine
->
framesize_outgoing
,
cfun
->
machine
->
framesize_outgoing
==
1
""
:
"s"
)
;
if
(
cfun
->
machine
->
uses_es
)
fprintf
(
file
,
"\t; uses ES register\n"
)
;
if
(
MUST_SAVE_MDUC_REGISTERS
)
fprintf
(
file
,
"\t; preserves MDUC registers\n"
)
;
}
</s>

We do n't use this to actually emit the function prologue . We use this to insert a comment in the asm file describing the function .

rl78
"interrupt"
"vector"
0
"\t; start of function\n"
"\t; push %d:"
0
16
" %s"
2
"\n"
"\t; $fp points here (r22)\n"
"\t; locals: %d byte%s\n"
1
""
"s"
"\t; outgoing: %d byte%s\n"
1
""
"s"
"\t; uses ES register\n"
"\t; preserves MDUC registers\n"


<s> bool RISCVAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == ".option" ) return parseDirectiveOption ( ) ; else if ( IDVal == ".attribute" ) return parseDirectiveAttribute ( ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool ARMTTIImpl :: areInlineCompatible ( const Function * Caller , const Function * Callee ) const { const TargetMachine & TM = getTLI ( ) -> getTargetMachine ( ) ; const FeatureBitset & CallerBits = TM . getSubtargetImpl ( * Caller ) -> getFeatureBits ( ) ; const FeatureBitset & CalleeBits = TM . getSubtargetImpl ( * Callee ) -> getFeatureBits ( ) ; bool MatchExact = ( CallerBits & ~ InlineFeatureWhitelist ) == ( CalleeBits & ~ InlineFeatureWhitelist ) ; bool MatchSubset = ( ( CallerBits & CalleeBits ) & InlineFeatureWhitelist ) == ( CalleeBits & InlineFeatureWhitelist ) ; return MatchExact && MatchSubset ; } </s>

Determine whether a callee with the given TLI can be inlined into caller with this TLI , based on 'nobuiltin ' attributes .


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT LHSTy ) const override { return MVT :: i8 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> unsigned getStackAlignment ( ) const { return StackAlignment ; } </s>

Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget .


<s>
MachineInstr
*
ARMBaseInstrInfo
::
optimizeSelect
(
MachineInstr
&
MI
,
SmallPtrSetImpl
<
MachineInstr
*
>
&
SeenMIs
,
bool
PreferFalse
)
const
{
assert
(
(
MI
.
getOpcode
(
)
==
ARM
::
MOVCCr
||
MI
.
getOpcode
(
)
==
ARM
::
t2MOVCCr
)
&&
"Unknown select instruction"
)
;
MachineRegisterInfo
&
MRI
=
MI
.
getParent
(
)
->
getParent
(
)
->
getRegInfo
(
)
;
MachineInstr
*
DefMI
=
canFoldIntoMOVCC
(
MI
.
getOperand
(
2
)
.
getReg
(
)
,
MRI
,
this
)
;
bool
Invert
=
!
DefMI
;
if
(
!
DefMI
)
DefMI
=
canFoldIntoMOVCC
(
MI
.
getOperand
(
1
)
.
getReg
(
)
,
MRI
,
this
)
;
if
(
!
DefMI
)
return
nullptr
;
MachineOperand
FalseReg
=
MI
.
getOperand
(
Invert
2
:
1
)
;
unsigned
DestReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
const
TargetRegisterClass
*
PreviousClass
=
MRI
.
getRegClass
(
FalseReg
.
getReg
(
)
)
;
if
(
!
MRI
.
constrainRegClass
(
DestReg
,
PreviousClass
)
)
return
nullptr
;
MachineInstrBuilder
NewMI
=
BuildMI
(
*
MI
.
getParent
(
)
,
MI
,
MI
.
getDebugLoc
(
)
,
DefMI
->
getDesc
(
)
,
DestReg
)
;
const
MCInstrDesc
&
DefDesc
=
DefMI
->
getDesc
(
)
;
for
(
unsigned
i
=
1
,
e
=
DefDesc
.
getNumOperands
(
)
;
i
!=
e
&&
!
DefDesc
.
OpInfo
[
i
]
.
isPredicate
(
)
;
++
i
)
NewMI
.
addOperand
(
DefMI
->
getOperand
(
i
)
)
;
unsigned
CondCode
=
MI
.
getOperand
(
3
)
.
getImm
(
)
;
if
(
Invert
)
NewMI
.
addImm
(
ARMCC
::
getOppositeCondition
(
ARMCC
::
CondCodes
(
CondCode
)
)
)
;
else
NewMI
.
addImm
(
CondCode
)
;
NewMI
.
addOperand
(
MI
.
getOperand
(
4
)
)
;
if
(
NewMI
->
hasOptionalDef
(
)
)
AddDefaultCC
(
NewMI
)
;
FalseReg
.
setImplicit
(
)
;
NewMI
.
addOperand
(
FalseReg
)
;
NewMI
->
tieOperands
(
0
,
NewMI
->
getNumOperands
(
)
1
)
;
SeenMIs
.
insert
(
NewMI
)
;
SeenMIs
.
erase
(
DefMI
)
;
if
(
DefMI
->
getParent
(
)
!=
MI
.
getParent
(
)
)
NewMI
->
clearKillInfo
(
)
;
DefMI
->
eraseFromParent
(
)
;
return
NewMI
;
}
</s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


<s> static void ia64_soft_fp_init_libfuncs ( void ) { } </s>


Try to a expand constant multiply in DImode by looking it up in a precompiled table . OP0 is the result operand , OP1 is the source operand , and MULTIPLIER is the value of the constant . Return true if it succeeds .


<s> const MCSection * MipsTargetObjectFile :: getSectionForConstant ( SectionKind Kind , const Constant * C ) const { if ( IsConstantInSmallSection ( C , * TM ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: getSectionForConstant ( Kind , C ) ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


runOnMachineFunction - Emit the function body .

NVPTX NVPTX NVPTX::VRFrame NVPTX::VRFrame


<s>
bool
SIFixVGPRCopies
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
const
SISubtarget
&
ST
=
MF
.
getSubtarget
<
SISubtarget
>
(
)
;
const
SIRegisterInfo
*
TRI
=
ST
.
getRegisterInfo
(
)
;
const
SIInstrInfo
*
TII
=
ST
.
getInstrInfo
(
)
;
bool
Changed
=
false
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
for
(
MachineInstr
&
MI
:
MBB
)
{
switch
(
MI
.
getOpcode
(
)
)
{
case
AMDGPU
::
COPY
:
if
(
TII
->
isVGPRCopy
(
MI
)
&&
!
MI
.
readsRegister
(
AMDGPU
::
EXEC
,
TRI
)
)
{
MI
.
addOperand
(
MF
,
MachineOperand
::
CreateReg
(
AMDGPU
::
EXEC
,
false
,
true
)
)
;
DEBUG
(
dbgs
(
)
<<
"Add exec use to "
<<
MI
)
;
Changed
=
true
;
}
break
;
default
:
break
;
}
}
}
return
Changed
;
}
</s>

AMDGPU
SI
SI
SI
SI
SI
AMDGPU::COPY
AMDGPU::EXEC
AMDGPU::EXEC
"Add exec use to "


<s> static rtx tilegx_function_arg ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS cum = * get_cumulative_args ( cum_v ) ; int byte_size = ( ( mode == BLKmode ) ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ) ; bool doubleword_aligned_p ; if ( cum >= TILEGX_NUM_ARG_REGS ) return NULL_RTX ; doubleword_aligned_p = tilegx_function_arg_boundary ( mode , type ) > BITS_PER_WORD ; if ( doubleword_aligned_p ) cum += cum & 1 ; if ( ( cum + ( byte_size + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ) > TILEGX_NUM_ARG_REGS ) return NULL_RTX ; return gen_rtx_REG ( mode , cum ) ; } </s>


<s> unsigned PTXTargetLowering :: getNumRegisters ( LLVMContext & Context , EVT VT ) { return 1 ; } </s>

Return the number of registers that this ValueType will eventually require .


<s> bool RISCVAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { if ( ! AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , OS ) ) return false ; const MachineOperand & MO = MI -> getOperand ( OpNo ) ; if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'z' : if ( MO . isImm ( ) && MO . getImm ( ) == 0 ) { OS << RISCVInstPrinter :: getRegisterName ( RISCV :: X0 ) ; return false ; } break ; case 'i' : if ( ! MO . isReg ( ) ) OS << 'i' ; return false ; } } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate : OS << MO . getImm ( ) ; return false ; case MachineOperand :: MO_Register : OS << RISCVInstPrinter :: getRegisterName ( MO . getReg ( ) ) ; return false ; case MachineOperand :: MO_GlobalAddress : PrintSymbolOperand ( MO , OS ) ; return false ; case MachineOperand :: MO_BlockAddress : { MCSymbol * Sym = GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; Sym -> print ( OS , MAI ) ; return false ; } default : break ; } return true ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { ForCodeSize = MF . getFunction ( ) -> hasFnAttribute ( Attribute :: OptimizeForSize ) || MF . getFunction ( ) -> hasFnAttribute ( Attribute :: MinSize ) ; Subtarget = & MF . getSubtarget < AArch64Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>


<s> bool MBBInfo :: isVisited ( ) const { return HTScope ; } </s>

Returns true if this node been visited by the DFS traversal .


<s> static void loongarch_save_reg ( rtx reg , rtx mem ) { loongarch_emit_move ( mem , reg ) ; loongarch_set_frame_expr ( loongarch_frame_set ( mem , reg ) ) ; } </s>

Save register REG to MEM . Make the instruction frame-related .


<s> bool isIntDivCheap ( EVT VT , AttributeList Attr ) const override { return true ; } </s>

Return true if integer divide is usually cheaper than a sequence of several shifts , adds , and multiplies for this target .


<s> std :: pair < SDValue , SDValue > SystemZSelectionDAGInfo :: EmitTargetCodeForStrcpy ( SelectionDAG & DAG , SDLoc DL , SDValue Chain , SDValue Dest , SDValue Src , MachinePointerInfo DestPtrInfo , MachinePointerInfo SrcPtrInfo , bool isStpcpy ) const { SDVTList VTs = DAG . getVTList ( Dest . getValueType ( ) , MVT :: Other ) ; SDValue EndDest = DAG . getNode ( SystemZISD :: STPCPY , DL , VTs , Chain , Dest , Src , DAG . getConstant ( 0 , MVT :: i32 ) ) ; return std :: make_pair ( isStpcpy ? EndDest : Dest , EndDest . getValue ( 1 ) ) ; } </s>

Emit target-specific code that performs a strcpy or stpcpy , in cases where that is faster than a libcall .


<s> bool targetSchedulesPostRAScheduling ( ) const override { return true ; } </s>

True if subtarget inserts the final scheduling pass on its own .


<s> static void alpha_extract_integer ( rtx x , HOST_WIDE_INT * p0 , HOST_WIDE_INT * p1 ) { HOST_WIDE_INT i0 , i1 ; if ( GET_CODE ( x ) == CONST_VECTOR ) x = simplify_subreg ( DImode , x , GET_MODE ( x ) , 0 ) ; if ( GET_CODE ( x ) == CONST_INT ) { i0 = INTVAL ( x ) ; i1 = - ( i0 < 0 ) ; } else if ( HOST_BITS_PER_WIDE_INT >= 64 ) { i0 = CONST_DOUBLE_LOW ( x ) ; i1 = - ( i0 < 0 ) ; } else { i0 = CONST_DOUBLE_LOW ( x ) ; i1 = CONST_DOUBLE_HIGH ( x ) ; } * p0 = i0 ; * p1 = i1 ; } </s>

Given an integral CONST_INT , CONST_DOUBLE , or CONST_VECTOR , return the low 64 bits .


<s> InstructionCost HexagonTTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * DataTy , const Value * Ptr , bool VariableMask , Align Alignment , TTI :: TargetCostKind CostKind , const Instruction * I ) { return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , CostKind , I ) ; } </s>

Calculate the cost of Gather / Scatter operation .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == 0 ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s> void fr30_setup_incoming_varargs ( cumulative_args_t arg_regs_used_so_far_v , const function_arg_info & arg , int * pretend_size , int second_time ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * arg_regs_used_so_far = get_cumulative_args ( arg_regs_used_so_far_v ) ; int size ; gcc_assert ( arg . mode != BLKmode ) ; if ( targetm . calls . strict_argument_naming ( arg_regs_used_so_far_v ) ) arg_regs_used_so_far += fr30_num_arg_regs ( arg ) ; size = FR30_NUM_ARG_REGS - ( * arg_regs_used_so_far ) ; if ( size <= 0 ) return ; * pretend_size = ( size * UNITS_PER_WORD ) ; } </s>

Do any needed setup for a variadic function . We must create a register parameter block , and then copy any anonymous arguments , plus the last named argument , from registers into memory . * copying actually done in fr30_expand_prologue ( ) . ARG_REGS_USED_SO_FAR has * not * been updated for the last named argument which has type TYPE and mode MODE , and we rely on this fact .


<s> virtual bool isReg ( ) const LLVM_OVERRIDE { return Kind == KindReg ; } </s>


<s>
SDValue
AMDGPUTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
Op
.
getNode
(
)
->
dump
(
)
;
llvm_unreachable
(
"Custom lowering code for this"
"instruction is not implemented yet!"
)
;
break
;
case
ISD
::
SIGN_EXTEND_INREG
:
return
LowerSIGN_EXTEND_INREG
(
Op
,
DAG
)
;
case
ISD
::
CONCAT_VECTORS
:
return
LowerCONCAT_VECTORS
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_SUBVECTOR
:
return
LowerEXTRACT_SUBVECTOR
(
Op
,
DAG
)
;
case
ISD
::
FrameIndex
:
return
LowerFrameIndex
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
UDIVREM
:
return
LowerUDIVREM
(
Op
,
DAG
)
;
case
ISD
::
SDIVREM
:
return
LowerSDIVREM
(
Op
,
DAG
)
;
case
ISD
::
FREM
:
return
LowerFREM
(
Op
,
DAG
)
;
case
ISD
::
FCEIL
:
return
LowerFCEIL
(
Op
,
DAG
)
;
case
ISD
::
FTRUNC
:
return
LowerFTRUNC
(
Op
,
DAG
)
;
case
ISD
::
FRINT
:
return
LowerFRINT
(
Op
,
DAG
)
;
case
ISD
::
FNEARBYINT
:
return
LowerFNEARBYINT
(
Op
,
DAG
)
;
case
ISD
::
FFLOOR
:
return
LowerFFLOOR
(
Op
,
DAG
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerSINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
UINT_TO_FP
:
return
LowerUINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_SINT
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_UINT
(
Op
,
DAG
)
;
}
return
Op
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s>
static
tree
nvptx_goacc_adjust_private_decl
(
location_t
loc
,
tree
decl
,
int
level
)
{
gcc_checking_assert
(
!
lookup_attribute
(
"oacc gang-private"
,
DECL_ATTRIBUTES
(
decl
)
)
)
;
if
(
level
==
GOMP_DIM_GANG
)
{
tree
id
=
get_identifier
(
"oacc gang-private"
)
;
tree
loc_tree
=
build_empty_stmt
(
loc
)
;
DECL_ATTRIBUTES
(
decl
)
=
tree_cons
(
id
,
loc_tree
,
DECL_ATTRIBUTES
(
decl
)
)
;
}
return
decl
;
}
</s>

nvptx
"oacc gang-private"
"oacc gang-private"


<s>
void
XtensaFrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
dl
=
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
uint64_t
StackSize
=
computeStackSize
(
MF
)
;
if
(
!
StackSize
)
{
return
;
}
llvm_unreachable
(
"Couldn't reach here"
)
;
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool Z80CallFrameOptimization :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) || NoZ80CFOpt . getValue ( ) ) return false ; return false ; } </s>


<s>
SDValue
RISCVTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
report_fatal_error
(
"unimplemented operand"
)
;
case
ISD
::
GlobalAddress
:
return
lowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
lowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
lowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
lowerSELECT
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
lowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
}
}
</s>

RISCV
RISCV
"unimplemented operand"
ISD::GlobalAddress
ISD::BlockAddress
ISD::ConstantPool
ISD::SELECT
ISD::VASTART
ISD::FRAMEADDR
ISD::RETURNADDR


<s> uint32_t find ( T Val ) const { auto F = llvm :: find ( Map , Val ) ; assert ( F != Map . end ( ) ) ; return F - Map . begin ( ) ; } </s>

Search for the first string Str in the string .


<s> ScheduleHazardRecognizer * ARMBaseInstrInfo :: CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II , const ScheduleDAG * DAG ) const { MultiHazardRecognizer * MHR = new MultiHazardRecognizer ( ) ; if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2Base ( ) ) MHR -> AddHazardRecognizer ( std :: make_unique < ARMHazardRecognizerFPMLx > ( ) ) ; auto BHR = TargetInstrInfo :: CreateTargetPostRAHazardRecognizer ( II , DAG ) ; if ( BHR ) MHR -> AddHazardRecognizer ( std :: unique_ptr < ScheduleHazardRecognizer > ( BHR ) ) ; return MHR ; } </s>

Allocate and return a hazard recognizer to use for by non-scheduling passes .


<s> void PPCInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { unsigned Directive = Subtarget . getDarwinDirective ( ) ; unsigned Opcode ; switch ( Directive ) { default : Opcode = PPC :: NOP ; break ; case PPC :: DIR_PWR6 : Opcode = PPC :: NOP_GT_PWR6 ; break ; case PPC :: DIR_PWR7 : Opcode = PPC :: NOP_GT_PWR7 ; break ; case PPC :: DIR_PWR8 : Opcode = PPC :: NOP_GT_PWR7 ; break ; } DebugLoc DL ; BuildMI ( MBB , MI , DL , get ( Opcode ) ) ; } </s>

Insert a noop into the instruction stream at the specified point .


<s>
void
ARMTTIImpl
::
getUnrollingPreferences
(
Loop
*
L
,
ScalarEvolution
&
SE
,
TTI
::
UnrollingPreferences
&
UP
,
OptimizationRemarkEmitter
*
ORE
)
{
UP
.
UpperBound
=
true
;
if
(
!
ST
->
isMClass
(
)
)
return
BasicTTIImplBase
::
getUnrollingPreferences
(
L
,
SE
,
UP
,
ORE
)
;
UP
.
OptSizeThreshold
=
0
;
UP
.
PartialOptSizeThreshold
=
0
;
if
(
L
->
getHeader
(
)
->
getParent
(
)
->
hasOptSize
(
)
)
return
;
SmallVector
<
BasicBlock
*
,
4
>
ExitingBlocks
;
L
->
getExitingBlocks
(
ExitingBlocks
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Loop has:\n"
<<
"Blocks: "
<<
L
->
getNumBlocks
(
)
<<
"\n"
<<
"Exit blocks: "
<<
ExitingBlocks
.
size
(
)
<<
"\n"
)
;
if
(
ExitingBlocks
.
size
(
)
>
2
)
return
;
if
(
ST
->
hasBranchPredictor
(
)
&&
L
->
getNumBlocks
(
)
>
4
)
return
;
if
(
getBooleanLoopAttribute
(
L
,
"llvm.loop.isvectorized"
)
)
return
;
InstructionCost
Cost
=
0
;
for
(
auto
*
BB
:
L
->
getBlocks
(
)
)
{
for
(
auto
&
I
:
*
BB
)
{
if
(
I
.
getType
(
)
->
isVectorTy
(
)
)
return
;
if
(
isa
<
CallInst
>
(
I
)
||
isa
<
InvokeInst
>
(
I
)
)
{
if
(
const
Function
*
F
=
cast
<
CallBase
>
(
I
)
.
getCalledFunction
(
)
)
{
if
(
!
isLoweredToCall
(
F
)
)
continue
;
}
return
;
}
SmallVector
<
const
Value
*
,
4
>
Operands
(
I
.
operand_values
(
)
)
;
Cost
+=
getUserCost
(
&
I
,
Operands
,
TargetTransformInfo
::
TCK_SizeAndLatency
)
;
}
}
unsigned
UnrollCount
=
4
;
if
(
ST
->
isThumb1Only
(
)
)
{
unsigned
ExitingValues
=
0
;
SmallVector
<
BasicBlock
*
,
4
>
ExitBlocks
;
L
->
getExitBlocks
(
ExitBlocks
)
;
for
(
auto
*
Exit
:
ExitBlocks
)
{
unsigned
LiveOuts
=
count_if
(
Exit
->
phis
(
)
,
[
]
(
auto
&
PH
)
{
return
PH
.
getNumOperands
(
)
!=
1
||
!
isa
<
GetElementPtrInst
>
(
PH
.
getOperand
(
0
)
)
;
}
)
;
ExitingValues
=
ExitingValues
<
LiveOuts
LiveOuts
:
ExitingValues
;
}
if
(
ExitingValues
)
UnrollCount
/=
ExitingValues
;
if
(
UnrollCount
<=
1
)
return
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Cost of loop: "
<<
Cost
<<
"\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Default Runtime Unroll Count: "
<<
UnrollCount
<<
"\n"
)
;
UP
.
Partial
=
true
;
UP
.
Runtime
=
true
;
UP
.
UnrollRemainder
=
true
;
UP
.
DefaultUnrollRuntimeCount
=
UnrollCount
;
UP
.
UnrollAndJam
=
true
;
UP
.
UnrollAndJamInnerLoopThreshold
=
60
;
if
(
Cost
<
12
)
UP
.
Force
=
true
;
}
</s>

Get target-customized preferences for the generic loop unrolling transformation .