<s> static void restore_saved_cr ( rtx reg , int using_mfcr_multiple , bool exit_func ) { int count = 0 ; int i ; if ( using_mfcr_multiple ) { for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) count ++ ; gcc_assert ( count ) ; } if ( using_mfcr_multiple && count > 1 ) { rtx_insn * insn ; rtvec p ; int ndx ; p = rtvec_alloc ( count ) ; ndx = 0 ; for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) { rtvec r = rtvec_alloc ( 2 ) ; RTVEC_ELT ( r , 0 ) = reg ; RTVEC_ELT ( r , 1 ) = GEN_INT ( 1 << ( 7 - i ) ) ; RTVEC_ELT ( p , ndx ) = gen_rtx_SET ( gen_rtx_REG ( CCmode , CR0_REGNO + i ) , gen_rtx_UNSPEC ( CCmode , r , UNSPEC_MOVESI_TO_CR ) ) ; ndx ++ ; } insn = emit_insn ( gen_rtx_PARALLEL ( VOIDmode , p ) ) ; gcc_assert ( ndx == count ) ; if ( ! exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap ) { for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) add_reg_note ( insn , REG_CFA_RESTORE , gen_rtx_REG ( SImode , CR0_REGNO + i ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } else for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) { rtx insn = emit_insn ( gen_movsi_to_cr_one ( gen_rtx_REG ( CCmode , CR0_REGNO + i ) , reg ) ) ; if ( ! exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap ) { add_reg_note ( insn , REG_CFA_RESTORE , gen_rtx_REG ( SImode , CR0_REGNO + i ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } if ( ! exit_func && DEFAULT_ABI != ABI_ELFv2 && ( DEFAULT_ABI == ABI_V4 || flag_shrink_wrap ) ) { rtx_insn * insn = get_last_insn ( ) ; rtx cr = gen_rtx_REG ( SImode , CR2_REGNO ) ; add_reg_note ( insn , REG_CFA_RESTORE , cr ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } </s>


"allocate SGPR spill should have worked"

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> void add_vundef_operand ( machine_mode mode ) { add_input_operand ( RVV_VUNDEF ( mode ) , mode ) ; } </s>

Since we may normalize vop/vop_tu/vop_m/vop_tumu .. into a single patter . We add a undef for the intrinsics that do n't need a real merge .


<s>
bool
AVRFrameLowering
::
restoreCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
if
(
CSI
.
empty
(
)
)
{
return
false
;
}
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
AVRSubtarget
&
STI
=
MF
.
getSubtarget
<
AVRSubtarget
>
(
)
;
const
TargetInstrInfo
&
TII
=
*
STI
.
getInstrInfo
(
)
;
for
(
const
CalleeSavedInfo
&
CCSI
:
CSI
)
{
unsigned
Reg
=
CCSI
.
getReg
(
)
;
assert
(
TRI
->
getRegSizeInBits
(
*
TRI
->
getMinimalPhysRegClass
(
Reg
)
)
==
8
&&
"Invalid register size"
)
;
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
POPRd
)
,
Reg
)
;
}
return
true
;
}
</s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .

AVR
AVR
AVR
AVR
8
"Invalid register size"
AVR::POPRd


<s> bool MipsNaClRewritePass :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const MipsInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= SandboxLoadsInBlock ( MBB ) ; Modified |= SandboxStoresInBlock ( MBB ) ; Modified |= SandboxBranchesInBlock ( MBB ) ; Modified |= SandboxStackChangesInBlock ( MBB ) ; } AlignAllJumpTargets ( MF ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> HOST_WIDE_INT mips_debugger_offset ( rtx addr , HOST_WIDE_INT offset ) { rtx offset2 = const0_rtx ; rtx reg = eliminate_constant_term ( addr , & offset2 ) ; if ( offset == 0 ) offset = INTVAL ( offset2 ) ; if ( reg == stack_pointer_rtx || reg == frame_pointer_rtx || reg == hard_frame_pointer_rtx ) { offset -= cfun -> machine -> frame . total_size ; if ( reg == hard_frame_pointer_rtx ) offset += cfun -> machine -> frame . hard_frame_pointer_offset ; } return offset ; } </s>

The MIPS debug format wants all automatic variables and arguments to be in terms of the virtual frame pointer ( stack pointer before any adjustment in the function ) , while the MIPS 3.0 linker wants the frame pointer to be the stack pointer after the initial adjustment . So , we do the adjustment here . The arg pointer ( which is eliminated ) points to the virtual frame pointer , while the frame pointer ( which may be eliminated ) points to the stack pointer after the initial adjustments .


<s> bool X86FastISel :: isTypeLegal ( Type * Ty , MVT & VT , bool AllowI1 ) { EVT evt = TLI . getValueType ( DL , Ty , true ) ; if ( evt == MVT :: Other || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; if ( VT == MVT :: f64 && ! X86ScalarSSEf64 ) return false ; if ( VT == MVT :: f32 && ! X86ScalarSSEf32 ) return false ; if ( VT == MVT :: f80 ) return false ; return ( AllowI1 && VT == MVT :: i1 ) || TLI . isTypeLegal ( VT ) ; } </s>


"expression value must be representable in 32 bits"

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> EVT PPCTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { if ( getTargetMachine ( ) . getOptLevel ( ) != CodeGenOpt :: None ) { const Function & F = MF . getFunction ( ) ; if ( Subtarget . hasQPX ( ) && Size >= 32 && ( ! IsMemset || Size >= 64 ) && ( ! SrcAlign || SrcAlign >= 32 ) && ( ! DstAlign || DstAlign >= 32 ) && ! F . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { return MVT :: v4f64 ; } if ( Subtarget . hasAltivec ( ) && Size >= 16 && ( ( ( ! SrcAlign || SrcAlign >= 16 ) && ( ! DstAlign || DstAlign >= 16 ) ) || ( ( IsMemset && Subtarget . hasVSX ( ) ) || Subtarget . hasP8Vector ( ) ) ) ) return MVT :: v4i32 ; } if ( Subtarget . isPPC64 ( ) ) { return MVT :: i64 ; } return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> bool MipsTargetLowering :: isCheapToSpeculateCtlz ( ) const { return Subtarget . hasMips32 ( ) ; } </s>

Return true if it is cheap to speculate a call to intrinsic ctlz .


<s> void AMDGPUAsmPrinter :: emitStartOfAsmFile ( Module & M ) { if ( IsaInfo :: hasCodeObjectV3 ( getGlobalSTI ( ) ) ) { std :: string ExpectedTarget ; raw_string_ostream ExpectedTargetOS ( ExpectedTarget ) ; IsaInfo :: streamIsaVersion ( getGlobalSTI ( ) , ExpectedTargetOS ) ; getTargetStreamer ( ) -> EmitDirectiveAMDGCNTarget ( ExpectedTarget ) ; } if ( TM . getTargetTriple ( ) . getOS ( ) != Triple :: AMDHSA && TM . getTargetTriple ( ) . getOS ( ) != Triple :: AMDPAL ) return ; if ( TM . getTargetTriple ( ) . getOS ( ) == Triple :: AMDHSA ) HSAMetadataStream -> begin ( M ) ; if ( TM . getTargetTriple ( ) . getOS ( ) == Triple :: AMDPAL ) getTargetStreamer ( ) -> getPALMetadata ( ) -> readFromIR ( M ) ; if ( IsaInfo :: hasCodeObjectV3 ( getGlobalSTI ( ) ) ) return ; if ( TM . getTargetTriple ( ) . getOS ( ) == Triple :: AMDHSA ) getTargetStreamer ( ) -> EmitDirectiveHSACodeObjectVersion ( 2 , 1 ) ; IsaVersion Version = getIsaVersion ( getGlobalSTI ( ) -> getCPU ( ) ) ; getTargetStreamer ( ) -> EmitDirectiveHSACodeObjectISA ( Version . Major , Version . Minor , Version . Stepping , "AMD" , "AMDGPU" ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the start of their file .


<s> static bool reg_used_in_mem_p ( int regno , rtx x ) { enum rtx_code code = GET_CODE ( x ) ; int i , j ; const char * fmt ; if ( code == MEM ) { if ( refers_to_regno_p ( regno , XEXP ( x , 0 ) ) ) return true ; } else if ( code == SET && GET_CODE ( SET_DEST ( x ) ) == PC ) { if ( refers_to_regno_p ( regno , SET_SRC ( x ) ) ) return true ; } fmt = GET_RTX_FORMAT ( code ) ; for ( i = GET_RTX_LENGTH ( code ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'e' && reg_used_in_mem_p ( regno , XEXP ( x , i ) ) ) return true ; else if ( fmt [ i ] == 'E' ) for ( j = 0 ; j < XVECLEN ( x , i ) ; j ++ ) if ( reg_used_in_mem_p ( regno , XVECEXP ( x , i , j ) ) ) return true ; } return false ; } </s>

Returns true if register REGNO is used for forming a memory address in expression X .


<s> bool mips_dangerous_for_la25_p ( rtx x ) { HOST_WIDE_INT offset ; if ( TARGET_EXPLICIT_RELOCS ) return false ; mips_split_const ( x , & x , & offset ) ; return global_got_operand ( x , VOIDmode ) ; } </s>

Return true if X should not be moved directly into register $ 25 . We need this because many versions of GAS will treat `` la $ 25 , foo '' as part of a call sequence and so allow a global `` foo '' to be lazily bound .


<s>
void
AVRInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
;
if
(
AVR
::
GPR8RegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
Opc
=
AVR
::
MOVRdRr
;
}
else
if
(
AVR
::
DREGSRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
Opc
=
AVR
::
MOVWRdRr
;
}
else
if
(
SrcReg
==
AVR
::
SP
&&
AVR
::
DREGSRegClass
.
contains
(
DestReg
)
)
{
Opc
=
AVR
::
SPREAD
;
}
else
if
(
DestReg
==
AVR
::
SP
&&
AVR
::
DREGSRegClass
.
contains
(
SrcReg
)
)
{
Opc
=
AVR
::
SPWRITE
;
}
else
{
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>

AVR
AVR
AVR::GPR8RegClass
AVR::MOVRdRr
AVR::DREGSRegClass
AVR::MOVWRdRr
AVR::SP
AVR::DREGSRegClass
AVR::SPREAD
AVR::SP
AVR::DREGSRegClass
AVR::SPWRITE
"Impossible reg-to-reg copy"


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , int64_t NumBytes , const TargetInstrInfo & TII ) { unsigned Opc ; uint64_t Chunk ; bool isSub = NumBytes < 0 ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; if ( Offset >= ( 1LL << 15 ) - 1 ) { Opc = SystemZ :: ADD64ri32 ; Chunk = ( 1LL << 31 ) - 1 ; } else { Opc = SystemZ :: ADD64ri16 ; Chunk = ( 1LL << 15 ) - 1 ; } DebugLoc DL = ( MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc :: getUnknownLoc ( ) ) ; while ( Offset ) { uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , SystemZ :: R15D ) . addReg ( SystemZ :: R15D ) . addImm ( ( isSub ? - ( int64_t ) ThisVal : ThisVal ) ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> void SystemZTTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP , OptimizationRemarkEmitter * ORE ) { bool HasCall = false ; InstructionCost NumStores = 0 ; for ( auto & BB : L -> blocks ( ) ) for ( auto & I : * BB ) { if ( isa < CallInst > ( & I ) || isa < InvokeInst > ( & I ) ) { if ( const Function * F = cast < CallBase > ( I ) . getCalledFunction ( ) ) { if ( isLoweredToCall ( F ) ) HasCall = true ; if ( F -> getIntrinsicID ( ) == Intrinsic :: memcpy || F -> getIntrinsicID ( ) == Intrinsic :: memset ) NumStores ++ ; } else { HasCall = true ; } } if ( isa < StoreInst > ( & I ) ) { Type * MemAccessTy = I . getOperand ( 0 ) -> getType ( ) ; NumStores += getMemoryOpCost ( Instruction :: Store , MemAccessTy , None , 0 , TTI :: TCK_RecipThroughput ) ; } } unsigned const NumStoresVal = * NumStores . getValue ( ) ; unsigned const Max = ( NumStoresVal ? ( 12 / NumStoresVal ) : UINT_MAX ) ; if ( HasCall ) { UP . FullUnrollMaxCount = Max ; UP . MaxCount = 1 ; return ; } UP . MaxCount = Max ; if ( UP . MaxCount <= 1 ) return ; UP . Partial = UP . Runtime = true ; UP . PartialThreshold = 75 ; UP . DefaultUnrollRuntimeCount = 4 ; UP . AllowExpensiveTripCount = true ; UP . Force = true ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> MachineBasicBlock :: iterator LanaiFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < TargetPassConfig > ( ) ; AU . addRequired < TargetLibraryInfoWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool sparc_can_use_return_insn_p ( void ) { return sparc_prologue_data_valid_p && sparc_n_global_fp_regs == 0 && TARGET_FLAT ? ( sparc_frame_size == 0 && ! sparc_save_local_in_regs_p ) : ( sparc_frame_size == 0 || ! sparc_leaf_function_p ) ; } </s>

Return true if it is appropriate to emit ` return ' instructions in the body of a function .


<s> MachineInstrBuilder R600InstrInfo :: buildDefaultInstruction ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned Opcode , unsigned DstReg , unsigned Src0Reg , unsigned Src1Reg ) const { MachineInstrBuilder MIB = BuildMI ( MBB , I , MBB . findDebugLoc ( I ) , get ( Opcode ) , DstReg ) ; if ( Src1Reg ) { MIB . addImm ( 0 ) . addImm ( 0 ) ; } MIB . addImm ( 1 ) . addImm ( 0 ) . addImm ( 0 ) . addImm ( 0 ) . addReg ( Src0Reg ) . addImm ( 0 ) . addImm ( 0 ) . addImm ( 0 ) . addImm ( - 1 ) ; if ( Src1Reg ) { MIB . addReg ( Src1Reg ) . addImm ( 0 ) . addImm ( 0 ) . addImm ( 0 ) . addImm ( - 1 ) ; } MIB . addImm ( 1 ) . addReg ( AMDGPU :: PRED_SEL_OFF ) . addImm ( 0 ) . addImm ( 0 ) ; return MIB ; } </s>

buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers initialized to their default values .


<s> void WebAssemblyFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const auto * TII = MF . getSubtarget < WebAssemblySubtarget > ( ) . getInstrInfo ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; unsigned Opc = I -> getOpcode ( ) ; bool IsDestroy = Opc == TII -> getCallFrameDestroyOpcode ( ) ; unsigned Amount = I -> getOperand ( 0 ) . getImm ( ) ; if ( Amount ) adjustStackPointer ( Amount , IsDestroy , MF , MBB , TII , I , DL ) ; MBB . erase ( I ) ; } </s>


<s> static tree rs6000_builtin_mask_for_load ( void ) { if ( ( TARGET_ALTIVEC && ! TARGET_VSX ) || ( TARGET_VSX && ! TARGET_EFFICIENT_UNALIGNED_VSX ) ) return altivec_builtin_mask_for_load ; else return 0 ; } </s>


<s>
static
Value
*
getNumElements
(
BasicBlock
*
Preheader
,
Value
*
BTC
)
{
for
(
auto
&
I
:
*
Preheader
)
{
if
(
I
.
getOpcode
(
)
!=
Instruction
::
Add
||
&
I
!=
BTC
)
continue
;
ConstantInt
*
MinusOne
=
nullptr
;
if
(
!
(
MinusOne
=
dyn_cast
<
ConstantInt
>
(
I
.
getOperand
(
1
)
)
)
)
continue
;
if
(
MinusOne
->
getSExtValue
(
)
==
1
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM TP: Found num elems: "
<<
I
<<
"\n"
)
;
return
I
.
getOperand
(
0
)
;
}
}
IRBuilder
<
>
Builder
(
Preheader
->
getTerminator
(
)
)
;
Value
*
NumElements
=
Builder
.
CreateAdd
(
BTC
,
ConstantInt
::
get
(
BTC
->
getType
(
)
,
1
)
,
"num.elements"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM TP: Created num elems: "
<<
*
NumElements
<<
"\n"
)
;
return
NumElements
;
}
</s>


<s> IndexType start ( ) const { return first ; } </s>

start - Beginning of the overlapping interval .


<s> static void ix86_setup_incoming_varargs ( cumulative_args_t cum_v , machine_mode mode , tree type , int * , int no_rtl ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; CUMULATIVE_ARGS next_cum ; tree fntype ; gcc_assert ( ! no_rtl ) ; if ( ! TARGET_64BIT ) return ; fntype = TREE_TYPE ( current_function_decl ) ; next_cum = * cum ; if ( stdarg_p ( fntype ) ) ix86_function_arg_advance ( pack_cumulative_args ( & next_cum ) , mode , type , true ) ; if ( cum -> call_abi == MS_ABI ) setup_incoming_varargs_ms_64 ( & next_cum ) ; else setup_incoming_varargs_64 ( & next_cum ) ; } </s>

Worker function for TARGET_SETUP_INCOMING_VARARGS .


<s> bool arc_is_uncached_mem_p ( rtx pat ) { tree attrs = NULL_TREE ; tree addr ; if ( ! MEM_P ( pat ) ) return false ; addr = MEM_EXPR ( pat ) ; if ( ! addr ) return false ; if ( TREE_CODE ( addr ) == MEM_REF || TREE_CODE ( addr ) == VAR_DECL ) { attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( addr ) ) ; if ( lookup_attribute ( "uncached" , attrs ) ) return true ; } if ( TREE_CODE ( addr ) == MEM_REF ) { attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( TREE_OPERAND ( addr , 0 ) ) ) ; if ( lookup_attribute ( "uncached" , attrs ) ) return true ; attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( TREE_OPERAND ( addr , 1 ) ) ) ; if ( lookup_attribute ( "uncached" , attrs ) ) return true ; } while ( handled_component_p ( addr ) ) { if ( TREE_CODE ( addr ) == COMPONENT_REF ) { attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( addr ) ) ; if ( lookup_attribute ( "uncached" , attrs ) ) return true ; attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( TREE_OPERAND ( addr , 0 ) ) ) ; if ( lookup_attribute ( "uncached" , attrs ) ) return true ; attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( TREE_OPERAND ( addr , 1 ) ) ) ; if ( lookup_attribute ( "uncached" , attrs ) ) return true ; } addr = TREE_OPERAND ( addr , 0 ) ; } return false ; } </s>

Return TRUE if PAT is a memory addressing an uncached data .


<s> SDValue ARMTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : return PerformADDCombine ( N , DCI ) ; case ISD :: SUB : return PerformSUBCombine ( N , DCI ) ; case ISD :: MUL : return PerformMULCombine ( N , DCI , Subtarget ) ; case ISD :: OR : return PerformORCombine ( N , DCI , Subtarget ) ; case ISD :: AND : return PerformANDCombine ( N , DCI ) ; case ARMISD :: BFI : return PerformBFICombine ( N , DCI ) ; case ARMISD :: VMOVRRD : return PerformVMOVRRDCombine ( N , DCI ) ; case ARMISD :: VMOVDRR : return PerformVMOVDRRCombine ( N , DCI . DAG ) ; case ISD :: STORE : return PerformSTORECombine ( N , DCI ) ; case ISD :: BUILD_VECTOR : return PerformBUILD_VECTORCombine ( N , DCI ) ; case ISD :: INSERT_VECTOR_ELT : return PerformInsertEltCombine ( N , DCI ) ; case ISD :: VECTOR_SHUFFLE : return PerformVECTOR_SHUFFLECombine ( N , DCI . DAG ) ; case ARMISD :: VDUPLANE : return PerformVDUPLANECombine ( N , DCI ) ; case ISD :: INTRINSIC_WO_CHAIN : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DCI . DAG , Subtarget ) ; case ISD :: SIGN_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: ANY_EXTEND : return PerformExtendCombine ( N , DCI . DAG , Subtarget ) ; case ISD :: SELECT_CC : return PerformSELECT_CCCombine ( N , DCI . DAG , Subtarget ) ; case ARMISD :: VLD2DUP : case ARMISD :: VLD3DUP : case ARMISD :: VLD4DUP : return CombineBaseUpdate ( N , DCI ) ; case ISD :: INTRINSIC_VOID : case ISD :: INTRINSIC_W_CHAIN : switch ( cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) -> getZExtValue ( ) ) { case Intrinsic :: arm_neon_vld1 : case Intrinsic :: arm_neon_vld2 : case Intrinsic :: arm_neon_vld3 : case Intrinsic :: arm_neon_vld4 : case Intrinsic :: arm_neon_vld2lane : case Intrinsic :: arm_neon_vld3lane : case Intrinsic :: arm_neon_vld4lane : case Intrinsic :: arm_neon_vst1 : case Intrinsic :: arm_neon_vst2 : case Intrinsic :: arm_neon_vst3 : case Intrinsic :: arm_neon_vst4 : case Intrinsic :: arm_neon_vst2lane : case Intrinsic :: arm_neon_vst3lane : case Intrinsic :: arm_neon_vst4lane : return CombineBaseUpdate ( N , DCI ) ; default : break ; } break ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


Allocate SIZE bytes of stack space , using TEMP_REG as a temporary if necessary . LAST_PROBE_OFFSET contains the offset of the closest probe relative to the stack pointer . Note that SIZE is negative . The return value is true if TEMP_REG has been clobbered .


<s> int Cpu0AsmParser :: tryParseRegister ( StringRef Mnemonic ) { const AsmToken & Tok = Parser . getTok ( ) ; int RegNum = - 1 ; if ( Tok . is ( AsmToken :: Identifier ) ) { std :: string lowerCase = Tok . getString ( ) . lower ( ) ; RegNum = matchRegisterName ( lowerCase ) ; } else if ( Tok . is ( AsmToken :: Integer ) ) { RegNum = matchRegisterByNumber ( static_cast < unsigned > ( Tok . getIntVal ( ) ) , Mnemonic . lower ( ) ) ; } else { return RegNum ; } return RegNum ; } </s>

tryParseRegister - parse one register if possible


<s> unsigned getMinPrefetchStride ( unsigned NumMemAccesses , unsigned NumStridedMemAccesses , unsigned NumPrefetches , bool HasCall ) const override { return MinPrefetchStride ; } </s>

Some HW prefetchers can handle accesses up to a certain constant stride .


<s> static inline bool inline_secondary_memory_needed ( machine_mode mode , reg_class_t class1 , reg_class_t class2 , int strict ) { if ( lra_in_progress && ( class1 == NO_REGS || class2 == NO_REGS ) ) return false ; if ( MAYBE_FLOAT_CLASS_P ( class1 ) != FLOAT_CLASS_P ( class1 ) || MAYBE_FLOAT_CLASS_P ( class2 ) != FLOAT_CLASS_P ( class2 ) || MAYBE_SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class1 ) || MAYBE_SSE_CLASS_P ( class2 ) != SSE_CLASS_P ( class2 ) || MAYBE_MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class1 ) || MAYBE_MMX_CLASS_P ( class2 ) != MMX_CLASS_P ( class2 ) || MAYBE_MASK_CLASS_P ( class1 ) != MASK_CLASS_P ( class1 ) || MAYBE_MASK_CLASS_P ( class2 ) != MASK_CLASS_P ( class2 ) ) { gcc_assert ( ! strict || lra_in_progress ) ; return true ; } if ( FLOAT_CLASS_P ( class1 ) != FLOAT_CLASS_P ( class2 ) ) return true ; if ( ( MASK_CLASS_P ( class1 ) != MASK_CLASS_P ( class2 ) ) && ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) ) return true ; if ( MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class2 ) ) return true ; if ( SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class2 ) ) { if ( ! TARGET_SSE2 ) return true ; if ( ( SSE_CLASS_P ( class1 ) && ! TARGET_INTER_UNIT_MOVES_FROM_VEC ) || ( SSE_CLASS_P ( class2 ) && ! TARGET_INTER_UNIT_MOVES_TO_VEC ) ) return true ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) return true ; } return false ; } </s>

If we are copying between general and FP registers , we need a memory location . The same is true for SSE and MMX registers . To optimize register_move_cost performance , allow inline variant . The macro ca n't work reliably when one of the CLASSES is class containing registers from multiple units ( SSE , MMX , integer ) . We avoid this by never combining those units in single alternative in the machine description . Ensure that this constraint holds to avoid unexpected surprises . When STRICT is false , we are being called from REGISTER_MOVE_COST , so do not enforce these sanity checks .


<s> bool MBlazeAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; printOperand ( MI , OpNo ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> int compute_convert_gain ( ) { return 1 ; } </s>


<s> bool MipsBranchExpansion :: runOnMachineFunction ( MachineFunction & MF ) { const TargetMachine & TM = MF . getTarget ( ) ; IsPIC = TM . isPositionIndependent ( ) ; ABI = static_cast < const MipsTargetMachine & > ( TM ) . getABI ( ) ; STI = & static_cast < const MipsSubtarget & > ( MF . getSubtarget ( ) ) ; TII = static_cast < const MipsInstrInfo * > ( STI -> getInstrInfo ( ) ) ; if ( IsPIC && ABI . IsO32 ( ) && MF . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( MF , TII ) ; MFp = & MF ; ForceLongBranchFirstPass = ForceLongBranch ; bool longBranchChanged = handlePossibleLongBranch ( ) ; bool forbiddenSlotChanged = handleForbiddenSlot ( ) ; bool fpuDelaySlotChanged = handleFPUDelaySlot ( ) ; bool loadDelaySlotChanged = handleLoadDelaySlot ( ) ; bool Changed = longBranchChanged || forbiddenSlotChanged || fpuDelaySlotChanged || loadDelaySlotChanged ; while ( forbiddenSlotChanged ) { longBranchChanged = handlePossibleLongBranch ( ) ; fpuDelaySlotChanged = handleFPUDelaySlot ( ) ; loadDelaySlotChanged = handleLoadDelaySlot ( ) ; if ( ! longBranchChanged && ! fpuDelaySlotChanged && ! loadDelaySlotChanged ) break ; forbiddenSlotChanged = handleForbiddenSlot ( ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> static void ia64_setup_incoming_varargs ( cumulative_args_t cum , const function_arg_info & arg , int * pretend_size , int second_time ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS next_cum = * get_cumulative_args ( cum ) ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) ) ia64_function_arg_advance ( pack_cumulative_args ( & next_cum ) , arg ) ; if ( next_cum . words < MAX_ARGUMENT_SLOTS ) { int n = MAX_ARGUMENT_SLOTS - next_cum . words ; * pretend_size = n * UNITS_PER_WORD ; cfun -> machine -> n_varargs = n ; } } </s>

Do any needed setup for a variadic function . CUM has not been updated for the last named argument which has type TYPE and mode MODE . We generate the actual spill instructions during prologue generation .


<s> static bool any_sibcall_could_use_r3 ( void ) { edge_iterator ei ; edge e ; if ( ! crtl -> tail_call_emit ) return false ; FOR_EACH_EDGE ( e , ei , EXIT_BLOCK_PTR_FOR_FN ( cfun ) -> preds ) if ( e -> flags & EDGE_SIBCALL ) { rtx call = BB_END ( e -> src ) ; if ( ! CALL_P ( call ) ) call = prev_nonnote_nondebug_insn ( call ) ; gcc_assert ( CALL_P ( call ) && SIBLING_CALL_P ( call ) ) ; if ( find_regno_fusage ( call , USE , 3 ) || is_indirect_tailcall_p ( call ) ) return true ; } return false ; } </s>

Return true if r3 is used by any of the tail call insns in the current function .


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = Endian == support :: little ? i : ( NumBytes - 1 - i ) ; Data [ Offset + i ] |= uint8_t ( ( Value >> ( Idx * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool PPCTargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createPPCISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> unsigned AGCAsmParser :: checkEarlyTargetMatchPredicate ( MCInst & Inst , const OperandVector & Operands ) { unsigned Opcode = Inst . getOpcode ( ) ; if ( Opcode == AGC :: EXTEND ) { ParsedExtend = true ; return Match_IgnoredExtend ; } bool InstIsExtracode = MII . get ( Opcode ) . TSFlags & AGCII :: IsExtracode ; if ( ! ParsingExtracode ) return InstIsExtracode ? Match_ExtracodeFail : Match_Success ; return InstIsExtracode ? Match_Success : Match_NonExtracodeFail ; return Match_Success ; } </s>

Validate the instruction match against any complex target predicates before rendering any operands to it .


<s> void AArch64MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; if ( MI . getOpcode ( ) == AArch64 :: TLSDESCCALL ) { MCFixupKind Fixup = MCFixupKind ( AArch64 :: fixup_aarch64_tlsdesc_call ) ; Fixups . push_back ( MCFixup :: create ( 0 , MI . getOperand ( 0 ) . getExpr ( ) , Fixup ) ) ; return ; } else if ( MI . getOpcode ( ) == AArch64 :: CompilerBarrier ) { return ; } uint64_t Binary = getBinaryCodeForInstr ( MI , Fixups , STI ) ; support :: endian :: Writer < support :: little > ( OS ) . write < uint32_t > ( Binary ) ; ++ MCNumEmitted ; } </s>

Encode the given Inst to bytes and append to CB .


<s> static bool arm_evpc_neon_vext ( struct expand_vec_perm_d * d ) { unsigned int i , nelt = d -> perm . length ( ) ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; rtx offset ; unsigned int location ; unsigned int next = d -> perm [ 0 ] + 1 ; if ( BYTES_BIG_ENDIAN ) return false ; for ( i = 1 ; i < nelt ; next ++ , i ++ ) { if ( next == 2 * nelt ) return false ; if ( d -> one_vector_p && ( next == nelt ) ) { if ( ( nelt == 2 ) && ( d -> vmode != V2DImode ) ) return false ; else next = 0 ; } if ( d -> perm [ i ] != next ) return false ; } location = d -> perm [ 0 ] ; switch ( d -> vmode ) { case E_V16QImode : gen = gen_neon_vextv16qi ; break ; case E_V8QImode : gen = gen_neon_vextv8qi ; break ; case E_V4HImode : gen = gen_neon_vextv4hi ; break ; case E_V8HImode : gen = gen_neon_vextv8hi ; break ; case E_V2SImode : gen = gen_neon_vextv2si ; break ; case E_V4SImode : gen = gen_neon_vextv4si ; break ; case E_V4HFmode : gen = gen_neon_vextv4hf ; break ; case E_V8HFmode : gen = gen_neon_vextv8hf ; break ; case E_V2SFmode : gen = gen_neon_vextv2sf ; break ; case E_V4SFmode : gen = gen_neon_vextv4sf ; break ; case E_V2DImode : gen = gen_neon_vextv2di ; break ; default : return false ; } if ( d -> testing_p ) return true ; offset = GEN_INT ( location ) ; emit_insn ( gen ( d -> target , d -> op0 , d -> op1 , offset ) ) ; return true ; } </s>


<s> bool isZero ( ) const { return K == ConstZero || K == VariableKnownToBeZero ; } </s>

Return true if the expression is a constant zero .


<s> SPUTargetLowering :: ConstraintType SPUTargetLowering :: getConstraintType ( const std :: string & ConstraintLetter ) const { if ( ConstraintLetter . size ( ) == 1 ) { switch ( ConstraintLetter [ 0 ] ) { default : break ; case 'b' : case 'r' : case 'f' : case 'v' : case 'y' : return C_RegisterClass ; } } return TargetLowering :: getConstraintType ( ConstraintLetter ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> const MipsSubtarget * MipsTargetMachine :: getSubtargetImpl ( const Function & F ) const { AttributeSet FnAttrs = F . getAttributes ( ) ; Attribute CPUAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "target-cpu" ) ; Attribute FSAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool hasMips16Attr = ! FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "mips16" ) . hasAttribute ( Attribute :: None ) ; bool hasNoMips16Attr = ! FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "nomips16" ) . hasAttribute ( Attribute :: None ) ; Attribute SFAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "use-soft-float" ) ; bool softFloat = ! SFAttr . hasAttribute ( Attribute :: None ) ? SFAttr . getValueAsString ( ) == "true" : Options . UseSoftFloat ; if ( hasMips16Attr ) FS += FS . empty ( ) ? "+mips16" : ",+mips16" ; else if ( hasNoMips16Attr ) FS += FS . empty ( ) ? "-mips16" : ",-mips16" ; auto & I = SubtargetMap [ CPU + FS + ( softFloat ? "use-soft-float=true" : "use-soft-float=false" ) ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < MipsSubtarget > ( TargetTriple , CPU , FS , isLittle , this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

Mips Mips Mips "target-cpu" "target-features" Mips "mips16" Mips "nomips16" "use-soft-float" "true" Mips "+mips16" ",+mips16" Mips "-mips16" ",-mips16" "use-soft-float=true" "use-soft-float=false" Mips


<s>
void
HexagonDAGToDAGISel
::
PreprocessISelDAG
(
)
{
auto
getNodes
=
[
this
]
(
)
->
std
::
vector
<
SDNode
*
>
{
std
::
vector
<
SDNode
*
>
T
;
T
.
reserve
(
CurDAG
->
allnodes_size
(
)
)
;
for
(
SDNode
&
N
:
CurDAG
->
allnodes
(
)
)
T
.
push_back
(
&
N
)
;
return
T
;
}
;
ppSimplifyOrSelect0
(
getNodes
(
)
)
;
ppAddrReorderAddShl
(
getNodes
(
)
)
;
ppAddrRewriteAndSrl
(
getNodes
(
)
)
;
ppHoistZextI1
(
getNodes
(
)
)
;
DEBUG_WITH_TYPE
(
"isel"
,
{
dbgs
(
)
<<
"Preprocessed (Hexagon) selection DAG:"
;
CurDAG
->
dump
(
)
;
}
)
;
if
(
EnableAddressRebalancing
)
{
rebalanceAddressTrees
(
)
;
DEBUG_WITH_TYPE
(
"isel"
,
{
dbgs
(
)
<<
"Address tree balanced selection DAG:"
;
CurDAG
->
dump
(
)
;
}
)
;
}
}
</s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .

Hexagon
Hexagon
"isel"
"Preprocessed (Hexagon) selection DAG:"
"isel"
"Address tree balanced selection DAG:"


<s> static bool arm_class_likely_spilled_p ( reg_class_t rclass ) { if ( ( TARGET_THUMB1 && rclass == LO_REGS ) || rclass == CC_REG ) return true ; return default_class_likely_spilled_p ( rclass ) ; } </s>

Implement TARGET_CLASS_LIKELY_SPILLED_P . We need to define this for LO_REGS on Thumb-1 . Otherwise we can end up using r0-r4 for function arguments , r7 for the stack frame and do n't have enough left over to do doubleword arithmetic . For Thumb-2 all the potentially problematic instructions accept high registers so this is not necessary . Care needs to be taken to avoid adding new Thumb-2 patterns that require many low registers .


<s> static void bfin_reorg_loops ( void ) { reorg_loops ( true , & bfin_doloop_hooks ) ; } </s>

Run from machine_dependent_reorg , this pass looks for doloop_end insns and tries to rewrite the RTL of these loops so that proper Blackfin hardware loops are generated .


<s> bool s390_contiguous_bitmask_vector_p ( rtx op , int * start , int * end ) { unsigned HOST_WIDE_INT mask ; int length , size ; rtx elt ; if ( ! const_vec_duplicate_p ( op , & elt ) || ! CONST_INT_P ( elt ) ) return false ; size = GET_MODE_UNIT_BITSIZE ( GET_MODE ( op ) ) ; if ( size > 64 ) return false ; mask = UINTVAL ( elt ) ; if ( s390_contiguous_bitmask_p ( mask , size , start , end != NULL ? & length : NULL ) ) { if ( end != NULL ) * end = * start + length - 1 ; return true ; } if ( s390_contiguous_bitmask_p ( ~ mask , size , start , end != NULL ? & length : NULL ) ) { if ( end != NULL ) * end = * start - 1 ; if ( start != NULL ) * start = * start + length ; return true ; } return false ; } </s>

Return true if OP contains the same contiguous bitfield in * all * its elements . START and END can be used to obtain the start and end position of the bitfield . START/STOP give the position of the first/last bit of the bitfield counting from the lowest order bit starting with zero . In order to use these values for S/390 instructions this has to be converted to `` bits big endian '' style .


<s> static SDValue PerformIntrinsicCombine ( SDNode * N , SelectionDAG & DAG ) { unsigned IntNo = cast < ConstantSDNode > ( N -> getOperand ( 0 ) ) -> getZExtValue ( ) ; switch ( IntNo ) { default : break ; case Intrinsic :: arm_neon_vqshifts : case Intrinsic :: arm_neon_vqshiftu : EVT VT = N -> getOperand ( 1 ) . getValueType ( ) ; int64_t Cnt ; if ( ! isVShiftLImm ( N -> getOperand ( 2 ) , VT , Cnt ) ) break ; unsigned VShiftOpc = ( IntNo == Intrinsic :: arm_neon_vqshifts ) ? AArch64ISD :: NEON_QSHLs : AArch64ISD :: NEON_QSHLu ; return DAG . getNode ( VShiftOpc , SDLoc ( N ) , N -> getValueType ( 0 ) , N -> getOperand ( 1 ) , DAG . getConstant ( Cnt , MVT :: i32 ) ) ; } return SDValue ( ) ; } </s>

PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics .


<s> void ARMPassConfig :: addPreEmitPass ( ) { addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( createUnpackMachineBundles ( [ ] ( const MachineFunction & MF ) { return MF . getSubtarget < ARMSubtarget > ( ) . isThumb2 ( ) ; } ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createARMOptimizeBarriersPass ( ) ) ; addPass ( createARMConstantIslandPass ( ) ) ; addPass ( createARMALFWriterPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> int paired_emit_vector_cond_expr ( rtx dest , rtx op1 , rtx op2 , rtx cond , rtx cc_op0 , rtx cc_op1 ) { enum rtx_code rcode = GET_CODE ( cond ) ; if ( ! TARGET_PAIRED_FLOAT ) return 0 ; paired_emit_vector_compare ( rcode , dest , op1 , op2 , cc_op0 , cc_op1 ) ; return 1 ; } </s>

Emit vector conditional expression . DEST is destination . OP1 and OP2 are two VEC_COND_EXPR operands . CC_OP0 and CC_OP1 are the two operands for the relation operation COND .


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override { ScheduleDAGMI * DAG = createGenericSchedPostRA ( C ) ; DAG -> addMutation ( createX86MacroFusionDAGMutation ( ) ) ; return DAG ; } </s>

Similar to createMachineScheduler but used when postRA machine scheduling is enabled .


<s> PPCSubtarget :: PPCSubtarget ( const std :: string & TT , const std :: string & FS , bool is64Bit ) : StackAlignment ( 16 ) , DarwinDirective ( PPC :: DIR_NONE ) , IsGigaProcessor ( false ) , Has64BitSupport ( false ) , Use64BitRegs ( false ) , IsPPC64 ( is64Bit ) , HasAltivec ( false ) , HasFSQRT ( false ) , HasSTFIWX ( false ) , HasLazyResolverStubs ( false ) , IsJITCodeModel ( false ) , DarwinVers ( 0 ) { std :: string CPU = "generic" ; CPU = GetCurrentPowerPCCPU ( ) ; ParseSubtargetFeatures ( FS , CPU ) ; if ( is64Bit ) { Has64BitSupport = true ; Use64BitRegs = true ; } if ( use64BitRegs ( ) && ! has64BitSupport ( ) ) Use64BitRegs = false ; if ( TT . length ( ) > 7 ) { size_t DarwinPos = TT . find ( "-darwin" ) ; if ( DarwinPos != std :: string :: npos ) { if ( isdigit ( TT [ DarwinPos + 7 ] ) ) DarwinVers = atoi ( & TT [ DarwinPos + 7 ] ) ; else DarwinVers = 8 ; } } if ( isDarwin ( ) ) HasLazyResolverStubs = true ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s>
void
ARCFrameLowering
::
determineCalleeSaves
(
MachineFunction
&
MF
,
BitVector
&
SavedRegs
,
RegScavenger
*
RS
)
const
{
DEBUG
(
dbgs
(
)
<<
"Determine Callee Saves: "
<<
MF
.
getFunction
(
)
->
getName
(
)
<<
"\n"
)
;
TargetFrameLowering
::
determineCalleeSaves
(
MF
,
SavedRegs
,
RS
)
;
SavedRegs
.
set
(
ARC
::
BLINK
)
;
}
</s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .

ARC
ARC
"Determine Callee Saves: "
"\n"
ARC::BLINK


<s>
Sparc
::
Fixups
SparcMCExpr
::
getFixupKind
(
SparcMCExpr
::
VariantKind
Kind
)
{
switch
(
Kind
)
{
default
:
llvm_unreachable
(
"Unhandled SparcMCExpr::VariantKind"
)
;
case
VK_Sparc_LO
:
return
Sparc
::
fixup_sparc_lo10
;
case
VK_Sparc_HI
:
return
Sparc
::
fixup_sparc_hi22
;
case
VK_Sparc_H44
:
return
Sparc
::
fixup_sparc_h44
;
case
VK_Sparc_M44
:
return
Sparc
::
fixup_sparc_m44
;
case
VK_Sparc_L44
:
return
Sparc
::
fixup_sparc_l44
;
case
VK_Sparc_HH
:
return
Sparc
::
fixup_sparc_hh
;
case
VK_Sparc_HM
:
return
Sparc
::
fixup_sparc_hm
;
case
VK_Sparc_PC22
:
return
Sparc
::
fixup_sparc_pc22
;
case
VK_Sparc_PC10
:
return
Sparc
::
fixup_sparc_pc10
;
case
VK_Sparc_GOT22
:
return
Sparc
::
fixup_sparc_got22
;
case
VK_Sparc_GOT10
:
return
Sparc
::
fixup_sparc_got10
;
case
VK_Sparc_GOT13
:
return
Sparc
::
fixup_sparc_got13
;
case
VK_Sparc_13
:
return
Sparc
::
fixup_sparc_13
;
case
VK_Sparc_WPLT30
:
return
Sparc
::
fixup_sparc_wplt30
;
case
VK_Sparc_WDISP30
:
return
Sparc
::
fixup_sparc_call30
;
case
VK_Sparc_TLS_GD_HI22
:
return
Sparc
::
fixup_sparc_tls_gd_hi22
;
case
VK_Sparc_TLS_GD_LO10
:
return
Sparc
::
fixup_sparc_tls_gd_lo10
;
case
VK_Sparc_TLS_GD_ADD
:
return
Sparc
::
fixup_sparc_tls_gd_add
;
case
VK_Sparc_TLS_GD_CALL
:
return
Sparc
::
fixup_sparc_tls_gd_call
;
case
VK_Sparc_TLS_LDM_HI22
:
return
Sparc
::
fixup_sparc_tls_ldm_hi22
;
case
VK_Sparc_TLS_LDM_LO10
:
return
Sparc
::
fixup_sparc_tls_ldm_lo10
;
case
VK_Sparc_TLS_LDM_ADD
:
return
Sparc
::
fixup_sparc_tls_ldm_add
;
case
VK_Sparc_TLS_LDM_CALL
:
return
Sparc
::
fixup_sparc_tls_ldm_call
;
case
VK_Sparc_TLS_LDO_HIX22
:
return
Sparc
::
fixup_sparc_tls_ldo_hix22
;
case
VK_Sparc_TLS_LDO_LOX10
:
return
Sparc
::
fixup_sparc_tls_ldo_lox10
;
case
VK_Sparc_TLS_LDO_ADD
:
return
Sparc
::
fixup_sparc_tls_ldo_add
;
case
VK_Sparc_TLS_IE_HI22
:
return
Sparc
::
fixup_sparc_tls_ie_hi22
;
case
VK_Sparc_TLS_IE_LO10
:
return
Sparc
::
fixup_sparc_tls_ie_lo10
;
case
VK_Sparc_TLS_IE_LD
:
return
Sparc
::
fixup_sparc_tls_ie_ld
;
case
VK_Sparc_TLS_IE_LDX
:
return
Sparc
::
fixup_sparc_tls_ie_ldx
;
case
VK_Sparc_TLS_IE_ADD
:
return
Sparc
::
fixup_sparc_tls_ie_add
;
case
VK_Sparc_TLS_LE_HIX22
:
return
Sparc
::
fixup_sparc_tls_le_hix22
;
case
VK_Sparc_TLS_LE_LOX10
:
return
Sparc
::
fixup_sparc_tls_le_lox10
;
}
}
</s>

getFixupKind - Get the fixup kind of this expression .


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { const ARMSubtarget & Subtarget = DAG . getTarget ( ) . getSubtarget < ARMSubtarget > ( ) ; if ( ! Subtarget . isAAPCS_ABI ( ) || Subtarget . isTargetMachO ( ) || Subtarget . isTargetWindows ( ) ) return SDValue ( ) ; const ARMTargetLowering & TLI = * static_cast < const ARMTargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Type * IntPtrTy = TLI . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( MVT :: i32 ) ) Src = DAG . getNode ( ISD :: TRUNCATE , dl , MVT :: i32 , Src ) ; else Src = DAG . getNode ( ISD :: ZERO_EXTEND , dl , MVT :: i32 , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , std :: move ( Args ) , 0 ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } </s>

Emit target-specific code that performs a memset .


"Process function before frame finalized: "

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> unsigned getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( Size , Offset , true ) ; MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( LLT :: pointer ( 0 , DL . getPointerSizeInBits ( 0 ) ) ) ; MIRBuilder . buildFrameIndex ( AddrReg , FI ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


"Splitting double registers in function: "

"Register partitioning: (partition #0 is fixed)\n"

runOnMachineFunction - Emit the function body .


<s> void m32c_conditional_register_usage ( void ) { int i ; if ( target_memregs >= 0 && target_memregs <= 16 ) { for ( i = ( target_memregs + 1 ) / 2 ; i < 8 ; i ++ ) { fixed_regs [ MEM0_REGNO + i ] = 1 ; CLEAR_HARD_REG_BIT ( reg_class_contents [ MEM_REGS ] , MEM0_REGNO + i ) ; } } if ( TARGET_A24 ) { call_used_regs [ R1_REGNO ] = 0 ; call_used_regs [ R2_REGNO ] = 0 ; call_used_regs [ R3_REGNO ] = 0 ; call_used_regs [ A0_REGNO ] = 0 ; call_used_regs [ A1_REGNO ] = 0 ; } } </s>

Implements CONDITIONAL_REGISTER_USAGE . We adjust the number of available memregs , and select which registers need to be preserved across calls based on the chip family .


<s> static rtx generate_set_vrsave ( rtx reg , rs6000_stack_t * info , int epiloguep ) { int nclobs , i ; rtx insn , clobs [ TOTAL_ALTIVEC_REGS + 1 ] ; rtx vrsave = gen_rtx_REG ( SImode , VRSAVE_REGNO ) ; clobs [ 0 ] = gen_rtx_SET ( VOIDmode , vrsave , gen_rtx_UNSPEC_VOLATILE ( SImode , gen_rtvec ( 2 , reg , vrsave ) , UNSPECV_SET_VRSAVE ) ) ; nclobs = 1 ; for ( i = FIRST_ALTIVEC_REGNO ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( info -> vrsave_mask & ALTIVEC_REG_BIT ( i ) ) { if ( ! epiloguep || call_used_regs [ i ] ) clobs [ nclobs ++ ] = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( V4SImode , i ) ) ; else { rtx reg = gen_rtx_REG ( V4SImode , i ) ; clobs [ nclobs ++ ] = gen_rtx_SET ( VOIDmode , reg , gen_rtx_UNSPEC ( V4SImode , gen_rtvec ( 1 , reg ) , 27 ) ) ; } } insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nclobs ) ) ; for ( i = 0 ; i < nclobs ; ++ i ) XVECEXP ( insn , 0 , i ) = clobs [ i ] ; return insn ; } </s>

Returns an insn that has a vrsave set operation with the appropriate CLOBBERs .


<s> enum reg_class m68k_secondary_reload_class ( enum reg_class rclass , machine_mode mode , rtx x ) { int regno ; regno = true_regnum ( x ) ; if ( GET_MODE_SIZE ( mode ) == 1 && reg_classes_intersect_p ( rclass , ADDR_REGS ) && ! ( INT_REGNO_P ( regno ) || CONSTANT_P ( x ) ) ) return DATA_REGS ; if ( TARGET_PCREL && ! reg_class_subset_p ( rclass , ADDR_REGS ) && symbolic_operand ( x , VOIDmode ) ) return ADDR_REGS ; return NO_REGS ; } </s>


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addRequired < PostDominatorTree > ( ) ; AU . addPreserved < PostDominatorTree > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static bool sparc_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { if ( TARGET_ARCH64 && GET_MODE_SIZE ( from ) == 4 && GET_MODE_SIZE ( to ) != 4 ) return ! reg_classes_intersect_p ( rclass , FP_REGS ) ; return true ; } </s>

Implement TARGET_CAN_CHANGE_MODE_CLASS . Borrowed from the PA port . SImode loads to floating-point registers are not zero-extended . The definition for LOAD_EXTEND_OP specifies that integer loads narrower than BITS_PER_WORD will be zero-extended . As a result , we inhibit changes from SImode unless they are to a mode that is identical in size . Likewise for SFmode , since word-mode paradoxical subregs are problematic on big-endian architectures .


<s> const uint32_t * getNoPreservedMask ( ) const override { return nullptr ; } </s>

Return a register mask that clobbers everything .


<s> tree ix86_veclibabi_acml ( combined_fn fn , tree type_out , tree type_in ) { char name [ 20 ] = "__vr.._" ; tree fntype , new_fndecl , args ; unsigned arity ; const char * bname ; machine_mode el_mode , in_mode ; int n , in_n ; if ( ! TARGET_64BIT || ! flag_unsafe_math_optimizations ) return NULL_TREE ; el_mode = TYPE_MODE ( TREE_TYPE ( type_out ) ) ; n = TYPE_VECTOR_SUBPARTS ( type_out ) ; in_mode = TYPE_MODE ( TREE_TYPE ( type_in ) ) ; in_n = TYPE_VECTOR_SUBPARTS ( type_in ) ; if ( el_mode != in_mode || n != in_n ) return NULL_TREE ; switch ( fn ) { CASE_CFN_SIN : CASE_CFN_COS : CASE_CFN_EXP : CASE_CFN_LOG : CASE_CFN_LOG2 : CASE_CFN_LOG10 : if ( el_mode == DFmode && n == 2 ) { name [ 4 ] = 'd' ; name [ 5 ] = '2' ; } else if ( el_mode == SFmode && n == 4 ) { name [ 4 ] = 's' ; name [ 5 ] = '4' ; } else return NULL_TREE ; break ; default : return NULL_TREE ; } tree fndecl = mathfn_built_in ( el_mode == DFmode ? double_type_node : float_type_node , fn ) ; bname = IDENTIFIER_POINTER ( DECL_NAME ( fndecl ) ) ; sprintf ( name + 7 , "%s" , bname + 10 ) ; arity = 0 ; for ( args = DECL_ARGUMENTS ( fndecl ) ; args ; args = TREE_CHAIN ( args ) ) arity ++ ; if ( arity == 1 ) fntype = build_function_type_list ( type_out , type_in , NULL ) ; else fntype = build_function_type_list ( type_out , type_in , type_in , NULL ) ; new_fndecl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , fntype ) ; TREE_PUBLIC ( new_fndecl ) = 1 ; DECL_EXTERNAL ( new_fndecl ) = 1 ; DECL_IS_NOVOPS ( new_fndecl ) = 1 ; TREE_READONLY ( new_fndecl ) = 1 ; return new_fndecl ; } </s>

Handler for an ACML-style interface to a library with vectorized intrinsics .


<s>
void
NVPTXFrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
if
(
MF
.
getFrameInfo
(
)
.
hasStackObjects
(
)
)
{
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineInstr
*
MI
=
&
MBB
.
front
(
)
;
MachineRegisterInfo
&
MR
=
MF
.
getRegInfo
(
)
;
const
NVPTXRegisterInfo
*
NRI
=
MF
.
getSubtarget
<
NVPTXSubtarget
>
(
)
.
getRegisterInfo
(
)
;
DebugLoc
dl
=
DebugLoc
(
)
;
bool
Is64Bit
=
static_cast
<
const
NVPTXTargetMachine
&
>
(
MF
.
getTarget
(
)
)
.
is64Bit
(
)
;
unsigned
CvtaLocalOpcode
=
(
Is64Bit
NVPTX
::
cvta_local_yes_64
:
NVPTX
::
cvta_local_yes
)
;
unsigned
MovDepotOpcode
=
(
Is64Bit
NVPTX
::
MOV_DEPOT_ADDR_64
:
NVPTX
::
MOV_DEPOT_ADDR
)
;
if
(
!
MR
.
use_empty
(
NRI
->
getFrameRegister
(
MF
)
)
)
{
MI
=
BuildMI
(
MBB
,
MI
,
dl
,
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
->
get
(
CvtaLocalOpcode
)
,
NRI
->
getFrameRegister
(
MF
)
)
.
addReg
(
NRI
->
getFrameLocalRegister
(
MF
)
)
;
}
BuildMI
(
MBB
,
MI
,
dl
,
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
->
get
(
MovDepotOpcode
)
,
NRI
->
getFrameLocalRegister
(
MF
)
)
.
addImm
(
MF
.
getFunctionNumber
(
)
)
;
}
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ; } </s>


<s>
void
WebAssemblyAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
DEBUG
(
dbgs
(
)
<<
"EmitInstruction: "
<<
*
MI
<<
'\n'
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
WebAssembly
::
ARGUMENT_I32
:
case
WebAssembly
::
ARGUMENT_I64
:
case
WebAssembly
::
ARGUMENT_F32
:
case
WebAssembly
::
ARGUMENT_F64
:
break
;
default
:
{
WebAssemblyMCInstLower
MCInstLowering
(
OutContext
,
*
this
)
;
MCInst
TmpInst
;
MCInstLowering
.
Lower
(
MI
,
TmpInst
)
;
EmitToStreamer
(
*
OutStreamer
,
TmpInst
)
;
break
;
}
}
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static char * ix86_offload_options ( void ) { if ( TARGET_LP64 ) return xstrdup ( "-foffload-abi=lp64" ) ; return xstrdup ( "-foffload-abi=ilp32" ) ; } </s>

Implement the TARGET_OFFLOAD_OPTIONS hook .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"R600 Expand special instructions pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .

AMDGPU
"R600 Expand special instructions pass"


<s> static void sh_trampoline_init ( rtx tramp_mem , tree fndecl , rtx cxt ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx tramp = force_reg ( Pmode , XEXP ( tramp_mem , 0 ) ) ; if ( TARGET_FDPIC ) { rtx a = force_reg ( Pmode , plus_constant ( Pmode , XEXP ( tramp_mem , 0 ) , 8 ) ) ; sh_emit_storesi ( tramp_mem , 0 , a ) ; sh_emit_storesi ( tramp_mem , 4 , sh_get_fdpic_reg_initial_val ( ) ) ; sh_emit_storehi ( tramp_mem , 8 , 0xd302 , 0xd203 ) ; sh_emit_storehi ( tramp_mem , 12 , 0x6122 , 0x5c21 ) ; sh_emit_storehi ( tramp_mem , 16 , 0x412b , 0x0009 ) ; sh_emit_storesi ( tramp_mem , 20 , cxt ) ; sh_emit_storesi ( tramp_mem , 24 , fnaddr ) ; } else { sh_emit_storehi ( tramp_mem , 0 , 0xd202 , 0xd301 ) ; sh_emit_storehi ( tramp_mem , 4 , 0x422b , 0x0009 ) ; sh_emit_storesi ( tramp_mem , 8 , cxt ) ; sh_emit_storesi ( tramp_mem , 12 , fnaddr ) ; } if ( TARGET_HARD_SH4 ) { if ( ! TARGET_INLINE_IC_INVALIDATE || ( ! ( TARGET_SH4A || TARGET_SH4_300 ) && TARGET_USERMODE ) ) emit_library_call ( function_symbol ( NULL , "__ic_invalidate" , FUNCTION_ORDINARY ) . sym , LCT_NORMAL , VOIDmode , tramp , SImode ) ; else emit_insn ( gen_ic_invalidate_line ( tramp ) ) ; } } </s>

Emit RTL insns to initialize the variable parts of a trampoline . FNADDR is an RTX for the address of the function 's pure code . CXT is an RTX for the static chain value for the function .


<s> MachinePointerInfo MipsFunctionInfo :: callPtrInfo ( const GlobalValue * GV ) { return MachinePointerInfo ( MF . getPSVManager ( ) . getGlobalValueCallEntry ( GV ) ) ; } </s>

Create a MachinePointerInfo that has a GlobalValuePseudoSourceValue object representing a GOT entry for a global function .


<s> LoadInst * X86TargetLowering :: lowerIdempotentRMWIntoFencedLoad ( AtomicRMWInst * AI ) const { unsigned NativeWidth = Subtarget . is64Bit ( ) ? 64 : 32 ; Type * MemType = AI -> getType ( ) ; if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) return nullptr ; if ( auto * C = dyn_cast < ConstantInt > ( AI -> getValOperand ( ) ) ) if ( AI -> getOperation ( ) == AtomicRMWInst :: Or && C -> isZero ( ) && AI -> use_empty ( ) ) return nullptr ; IRBuilder < > Builder ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SSID = AI -> getSyncScopeID ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; if ( SSID == SyncScope :: SingleThread ) return nullptr ; if ( ! Subtarget . hasMFence ( ) ) return nullptr ; Function * MFence = llvm :: Intrinsic :: getDeclaration ( M , Intrinsic :: x86_sse2_mfence ) ; Builder . CreateCall ( MFence , { } ) ; LoadInst * Loaded = Builder . CreateAlignedLoad ( AI -> getType ( ) , AI -> getPointerOperand ( ) , AI -> getAlign ( ) ) ; Loaded -> setAtomic ( Order , SSID ) ; AI -> replaceAllUsesWith ( Loaded ) ; AI -> eraseFromParent ( ) ; return Loaded ; } </s>

On some platforms , an AtomicRMW that never actually modifies the value ( such as fetch_add of 0 ) can be turned into a fence followed by an atomic load .


<s> void SIRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const SISubtarget & Subtarget = MF -> getSubtarget < SISubtarget > ( ) ; const SIInstrInfo * TII = Subtarget . getInstrInfo ( ) ; if ( Offset == 0 ) { BuildMI ( * MBB , Ins , DL , TII -> get ( AMDGPU :: V_MOV_B32_e32 ) , BaseReg ) . addFrameIndex ( FrameIdx ) ; return ; } MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; unsigned UnusedCarry = MRI . createVirtualRegister ( & AMDGPU :: SReg_64RegClass ) ; unsigned OffsetReg = MRI . createVirtualRegister ( & AMDGPU :: SReg_32_XM0RegClass ) ; unsigned FIReg = MRI . createVirtualRegister ( & AMDGPU :: VGPR_32RegClass ) ; BuildMI ( * MBB , Ins , DL , TII -> get ( AMDGPU :: S_MOV_B32 ) , OffsetReg ) . addImm ( Offset ) ; BuildMI ( * MBB , Ins , DL , TII -> get ( AMDGPU :: V_MOV_B32_e32 ) , FIReg ) . addFrameIndex ( FrameIdx ) ; BuildMI ( * MBB , Ins , DL , TII -> get ( AMDGPU :: V_ADD_I32_e64 ) , BaseReg ) . addReg ( UnusedCarry , RegState :: Define | RegState :: Dead ) . addReg ( OffsetReg , RegState :: Kill ) . addReg ( FIReg ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .


<s> bool AArch64FrameLowering :: canUseRedZone ( const MachineFunction & MF ) const { if ( ! EnableRedZone ) return false ; if ( MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoRedZone ) ) return false ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const AArch64FunctionInfo * AFI = MF . getInfo < AArch64FunctionInfo > ( ) ; unsigned NumBytes = AFI -> getLocalStackSize ( ) ; return ! ( MFI . hasCalls ( ) || hasFP ( MF ) || NumBytes > 128 || getSVEStackSize ( MF ) ) ; } </s>

Can this function use the red zone for local allocations .


<s> void sh_mark_label ( rtx address , int nuses ) { if ( GOTOFF_P ( address ) ) { address = XEXP ( address , 0 ) ; if ( GET_CODE ( address ) == PLUS ) address = XEXP ( address , 0 ) ; address = XVECEXP ( address , 0 , 0 ) ; } if ( GET_CODE ( address ) == LABEL_REF && GET_CODE ( XEXP ( address , 0 ) ) == CODE_LABEL ) LABEL_NUSES ( XEXP ( address , 0 ) ) += nuses ; } </s>

If ADDRESS refers to a CODE_LABEL , add NUSES to the number of times that label is used .


<s> const TargetRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> int includes_rldicr_lshift_p ( rtx shiftop , rtx andop ) { if ( GET_CODE ( andop ) == CONST_INT ) { HOST_WIDE_INT c , lsb , shift_mask ; shift_mask = ~ 0 ; shift_mask <<= INTVAL ( shiftop ) ; c = INTVAL ( andop ) ; lsb = c & - c ; if ( ( lsb & shift_mask ) == 0 ) return 0 ; return c == - lsb && lsb != 1 ; } else if ( GET_CODE ( andop ) == CONST_DOUBLE && ( GET_MODE ( andop ) == VOIDmode || GET_MODE ( andop ) == DImode ) ) { HOST_WIDE_INT low , lsb , shift_mask_low ; low = CONST_DOUBLE_LOW ( andop ) ; if ( HOST_BITS_PER_WIDE_INT < 64 ) { HOST_WIDE_INT high , shift_mask_high ; high = CONST_DOUBLE_HIGH ( andop ) ; if ( low == 0 ) { shift_mask_high = ~ 0 ; if ( INTVAL ( shiftop ) > 32 ) shift_mask_high <<= INTVAL ( shiftop ) - 32 ; lsb = high & - high ; if ( ( lsb & shift_mask_high ) == 0 ) return 0 ; return high == - lsb ; } if ( high != ~ 0 ) return 0 ; } shift_mask_low = ~ 0 ; shift_mask_low <<= INTVAL ( shiftop ) ; lsb = low & - low ; if ( ( lsb & shift_mask_low ) == 0 ) return 0 ; return low == - lsb && lsb != 1 ; } else return 0 ; } </s>

Return 1 if ANDOP is a mask suitable for use with an rldicr insn to perform a left shift . It must have SHIFTOP or more least significant 0 's , with the remainder of the word 1 's .


<s> static bool pa_callee_copies ( cumulative_args_t cum ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , const_tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { return ! TARGET_CALLER_COPIES ; } </s>

Implement TARGET_CALLEE_COPIES . The callee is responsible for copying arguments passed by hidden reference in the 32-bit HP runtime . Users can override this behavior for better compatibility with openmp at the risk of library incompatibilities . Arguments are always passed by value in the 64-bit HP runtime .


"=== RegBanks reassign analysis on function "

"RegBank reassign stall cycles verification failed."

runOnMachineFunction - Emit the function body .


"SIInstrInfo::storeRegToStackSlot - Do not know how to"

Store the specified register of the given register class to the specified stack frame index .


<s>
bool
RISCVInstrInfo
::
isBranchOffsetInRange
(
unsigned
BranchOp
,
int64_t
BrOffset
)
const
{
switch
(
BranchOp
)
{
default
:
llvm_unreachable
(
"Unexpected opcode!"
)
;
case
RISCV
::
BEQ
:
case
RISCV
::
BNE
:
case
RISCV
::
BLT
:
case
RISCV
::
BGE
:
case
RISCV
::
BLTU
:
case
RISCV
::
BGEU
:
return
isIntN
(
13
,
BrOffset
)
;
case
RISCV
::
JAL
:
case
RISCV
::
PseudoBR
:
return
isIntN
(
21
,
BrOffset
)
;
}
}
</s>

Determine if the branch target is in range .

RISCV
RISCV
"Unexpected opcode!"
RISCV::BEQ
RISCV::BNE
RISCV::BLT
RISCV::BGE
RISCV::BLTU
RISCV::BGEU
13
RISCV::JAL
RISCV::PseudoBR
21


<s> static int s390_split_branches ( void ) { rtx temp_reg = gen_rtx_REG ( Pmode , RETURN_REGNUM ) ; int new_literal = 0 , ret ; rtx_insn * insn ; rtx pat , target ; rtx * label ; shorten_branches ( get_insns ( ) ) ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( ! JUMP_P ( insn ) || tablejump_p ( insn , NULL , NULL ) ) continue ; pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , 0 , 0 ) ; if ( GET_CODE ( pat ) != SET || SET_DEST ( pat ) != pc_rtx ) continue ; if ( GET_CODE ( SET_SRC ( pat ) ) == LABEL_REF ) { label = & SET_SRC ( pat ) ; } else if ( GET_CODE ( SET_SRC ( pat ) ) == IF_THEN_ELSE ) { if ( GET_CODE ( XEXP ( SET_SRC ( pat ) , 1 ) ) == LABEL_REF ) label = & XEXP ( SET_SRC ( pat ) , 1 ) ; else if ( GET_CODE ( XEXP ( SET_SRC ( pat ) , 2 ) ) == LABEL_REF ) label = & XEXP ( SET_SRC ( pat ) , 2 ) ; else continue ; } else continue ; if ( get_attr_length ( insn ) <= 4 ) continue ; cfun_frame_layout . save_return_addr_p = 1 ; if ( ! flag_pic ) { new_literal = 1 ; rtx mem = force_const_mem ( Pmode , * label ) ; rtx_insn * set_insn = emit_insn_before ( gen_rtx_SET ( temp_reg , mem ) , insn ) ; INSN_ADDRESSES_NEW ( set_insn , - 1 ) ; annotate_constant_pool_refs ( & PATTERN ( set_insn ) ) ; target = temp_reg ; } else { new_literal = 1 ; target = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , * label ) , UNSPEC_LTREL_OFFSET ) ; target = gen_rtx_CONST ( Pmode , target ) ; target = force_const_mem ( Pmode , target ) ; rtx_insn * set_insn = emit_insn_before ( gen_rtx_SET ( temp_reg , target ) , insn ) ; INSN_ADDRESSES_NEW ( set_insn , - 1 ) ; annotate_constant_pool_refs ( & PATTERN ( set_insn ) ) ; target = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 2 , XEXP ( target , 0 ) , cfun -> machine -> base_reg ) , UNSPEC_LTREL_BASE ) ; target = gen_rtx_PLUS ( Pmode , temp_reg , target ) ; } ret = validate_change ( insn , label , target , 0 ) ; gcc_assert ( ret ) ; } return new_literal ; } </s>

Split all branches that exceed the maximum distance . Returns true if this created a new literal pool entry .


<s> SDValue XCoreSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { unsigned SizeBitWidth = Size . getValueType ( ) . getSizeInBits ( ) ; if ( ! AlwaysInline && ( Align & 3 ) == 0 && DAG . MaskedValueIsZero ( Size , APInt ( SizeBitWidth , 3 ) ) ) { const TargetLowering & TLI = * DAG . getSubtarget ( ) . getTargetLowering ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; Entry . Node = Src ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMCPY ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( "__memcpy_4" , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) , std :: move ( Args ) , 0 ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .


<s> AArch64Subtarget & AArch64Subtarget :: initializeSubtargetDependencies ( StringRef FS ) { if ( CPUString . empty ( ) ) CPUString = "generic" ; ParseSubtargetFeatures ( CPUString , FS ) ; initializeProperties ( ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> int m32c_expand_movmemhi ( rtx * operands ) { rtx desta , srca , count ; rtx desto , srco , counto ; desta = XEXP ( operands [ 0 ] , 0 ) ; srca = XEXP ( operands [ 1 ] , 0 ) ; count = operands [ 2 ] ; desto = gen_reg_rtx ( Pmode ) ; srco = gen_reg_rtx ( Pmode ) ; counto = gen_reg_rtx ( HImode ) ; if ( GET_CODE ( desta ) != REG || REGNO ( desta ) < FIRST_PSEUDO_REGISTER ) desta = copy_to_mode_reg ( Pmode , desta ) ; if ( GET_CODE ( srca ) != REG || REGNO ( srca ) < FIRST_PSEUDO_REGISTER ) srca = copy_to_mode_reg ( Pmode , srca ) ; if ( GET_CODE ( count ) == CONST_INT && ! ( INTVAL ( count ) & 1 ) && ( INTVAL ( count ) > 1 ) ) { count = copy_to_mode_reg ( HImode , GEN_INT ( INTVAL ( count ) / 2 ) ) ; if ( TARGET_A16 ) emit_insn ( gen_movmemhi_whi_op ( desto , srco , counto , desta , srca , count ) ) ; else emit_insn ( gen_movmemhi_wpsi_op ( desto , srco , counto , desta , srca , count ) ) ; return 1 ; } if ( GET_CODE ( count ) != REG || REGNO ( count ) < FIRST_PSEUDO_REGISTER ) count = copy_to_mode_reg ( HImode , count ) ; if ( TARGET_A16 ) emit_insn ( gen_movmemhi_bhi_op ( desto , srco , counto , desta , srca , count ) ) ; else emit_insn ( gen_movmemhi_bpsi_op ( desto , srco , counto , desta , srca , count ) ) ; return 1 ; } </s>

This is a memcpy ( ) opcode . All operands are implied , so we need to arrange for them to be in the right registers . The opcode wants addresses , not [ mem ] syntax . $ 0 is the destination ( MEM : BLK ) , $ 1 is the source ( MEM : BLK ) , and $ 2 the count ( HI ) .


<s> const HexagonInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> int HexagonInstrInfo :: getMaxValue ( const MachineInstr * MI ) const { const uint64_t F = MI -> getDesc ( ) . TSFlags ; unsigned isSigned = ( F >> HexagonII :: ExtentSignedPos ) & HexagonII :: ExtentSignedMask ; unsigned bits = ( F >> HexagonII :: ExtentBitsPos ) & HexagonII :: ExtentBitsMask ; if ( isSigned ) return ~ ( - 1U << ( bits - 1 ) ) ; else return ~ ( - 1U << bits ) ; } </s>

Return the maximal unsigned value possible given these KnownBits .

Hexagon Hexagon HexagonII::ExtentSignedPos HexagonII::ExtentSignedMask HexagonII::ExtentBitsPos HexagonII::ExtentBitsMask 1U 1 1U


<s> static bool ix86_function_value_regno_p ( const unsigned int regno ) { switch ( regno ) { case AX_REG : return true ; case DX_REG : return ( ! TARGET_64BIT || ix86_cfun_abi ( ) != MS_ABI ) ; case DI_REG : case SI_REG : return TARGET_64BIT && ix86_cfun_abi ( ) != MS_ABI ; case ST0_REG : case ST1_REG : if ( TARGET_64BIT && ix86_cfun_abi ( ) == MS_ABI ) return false ; return TARGET_FLOAT_RETURNS_IN_80387 ; case XMM0_REG : case XMM1_REG : return TARGET_SSE ; case MM0_REG : if ( TARGET_MACHO || TARGET_64BIT ) return false ; return TARGET_MMX ; } return false ; } </s>

Return true if N is a possible register number of function value .


"SIInstrInfo::loadRegFromStackSlot - Do not know how to"

Load the specified register of the given register class from the specified stack frame index .


<s> void rbt_inorder_callback ( struct rbt_strings * t , struct rbt_string_node * subtree , void ( * fn ) ( char * ) ) { if ( subtree != t -> rbt_nil ) { rbt_inorder_callback ( t , subtree -> left , fn ) ; ( * fn ) ( subtree -> str ) ; rbt_inorder_callback ( t , subtree -> right , fn ) ; } } </s>

Inorder call-back for iteration over the tree .


<s> int avr_hard_regno_call_part_clobbered ( unsigned regno , machine_mode mode ) { if ( ! avr_hard_regno_mode_ok ( regno , mode ) ) return 0 ; return ( ( regno <= LAST_CALLEE_SAVED_REG && regno + GET_MODE_SIZE ( mode ) > 1 + LAST_CALLEE_SAVED_REG ) || ( regno < REG_Y && regno + GET_MODE_SIZE ( mode ) > REG_Y ) || ( regno < REG_Z && regno + GET_MODE_SIZE ( mode ) > REG_Z ) ) ; } </s>

Implement ` HARD_REGNO_CALL_PART_CLOBBERED ' .


<s>
void
TVMInstrInfo
::
ReplaceUsesOfBlockWith
(
MachineBasicBlock
*
Pred
,
MachineBasicBlock
*
Old
,
MachineBasicBlock
*
New
)
const
{
MachineRegisterInfo
&
MRI
=
Pred
->
getParent
(
)
->
getRegInfo
(
)
;
for
(
MachineInstr
&
Term
:
Pred
->
terminators
(
)
)
{
enumMBBoperands
(
Term
,
[
&
]
(
MachineOperand
&
Op
)
{
if
(
!
Op
.
isReg
(
)
)
return
;
unsigned
MbbReg
=
Op
.
getReg
(
)
;
auto
*
PushMI
=
MRI
.
getVRegDef
(
MbbReg
)
;
if
(
PushMI
->
getOpcode
(
)
!=
TVM
::
PUSHCONT_MBB
)
return
;
assert
(
PushMI
->
getOperand
(
1
)
.
isMBB
(
)
&&
"PUSHCONT_MBB op is not MBB"
)
;
if
(
PushMI
->
getOperand
(
1
)
.
getMBB
(
)
==
Old
)
{
if
(
MRI
.
hasOneNonDBGUse
(
MbbReg
)
)
{
PushMI
->
getOperand
(
1
)
.
setMBB
(
New
)
;
}
else
{
auto
it
=
Pred
->
getFirstTerminator
(
)
;
auto
DL
=
it
->
getDebugLoc
(
)
;
MbbReg
=
MRI
.
createVirtualRegister
(
&
TVM
::
I257RegClass
)
;
BuildMI
(
*
Pred
,
it
,
DL
,
get
(
TVM
::
PUSHCONT_MBB
)
,
MbbReg
)
.
addMBB
(
New
)
.
addImm
(
0
)
;
Op
.
setReg
(
MbbReg
)
;
}
}
}
)
;
}
Pred
->
replaceSuccessor
(
Old
,
New
)
;
}
</s>

Given a machine basic block that branched to 'Old ' , change the code and CFG so that it branches to 'New ' instead .


<s> void xstormy16_expand_iorqi3 ( rtx * operands ) { rtx in , out , outsub , val ; out = operands [ 0 ] ; in = operands [ 1 ] ; val = operands [ 2 ] ; if ( xstormy16_onebit_set_operand ( val , QImode ) ) { if ( ! xstormy16_below100_or_register ( in , QImode ) ) in = copy_to_mode_reg ( QImode , in ) ; if ( ! xstormy16_below100_or_register ( out , QImode ) ) out = gen_reg_rtx ( QImode ) ; emit_insn ( gen_iorqi3_internal ( out , in , val ) ) ; if ( out != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , out ) ; return ; } if ( ! REG_P ( in ) ) in = copy_to_mode_reg ( QImode , in ) ; if ( ! REG_P ( val ) && ! CONST_INT_P ( val ) ) val = copy_to_mode_reg ( QImode , val ) ; if ( ! REG_P ( out ) ) out = gen_reg_rtx ( QImode ) ; in = simplify_gen_subreg ( HImode , in , QImode , 0 ) ; outsub = simplify_gen_subreg ( HImode , out , QImode , 0 ) ; if ( ! CONST_INT_P ( val ) ) val = simplify_gen_subreg ( HImode , val , QImode , 0 ) ; emit_insn ( gen_iorhi3 ( outsub , in , val ) ) ; if ( out != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , out ) ; } </s>

Expand an 8-bit IOR . This either detects the one case we can actually do , or uses a 16-bit IOR .


<s> Value * X86TargetLowering :: getIRStackGuard ( IRBuilder < > & IRB ) const { if ( ! Subtarget . isTargetGlibc ( ) ) return TargetLowering :: getIRStackGuard ( IRB ) ; unsigned Offset = ( Subtarget . is64Bit ( ) ) ? 0x28 : 0x14 ; unsigned AddressSpace = getAddressSpace ( ) ; return ConstantExpr :: getIntToPtr ( ConstantInt :: get ( Type :: getInt32Ty ( IRB . getContext ( ) ) , Offset ) , Type :: getInt8PtrTy ( IRB . getContext ( ) ) -> getPointerTo ( AddressSpace ) ) ; } </s>

If the target has a standard location for the stack protector cookie , returns the address of that location .


<s> bool CJGFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; CJGMachineFunctionInfo * MFI = MF . getInfo < CJGMachineFunctionInfo > ( ) ; MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( CJG :: PUSH ) ) . addReg ( Reg , RegState :: Kill ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


"Function has local memory argument. Promoting to "

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s>
bool
X86DAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
SDValue
Op0
,
Op1
,
Op2
,
Op3
,
Op4
;
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_o
:
case
InlineAsm
::
Constraint_v
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_X
:
if
(
!
selectAddr
(
nullptr
,
Op
,
Op0
,
Op1
,
Op2
,
Op3
,
Op4
)
)
return
true
;
break
;
}
OutOps
.
push_back
(
Op0
)
;
OutOps
.
push_back
(
Op1
)
;
OutOps
.
push_back
(
Op2
)
;
OutOps
.
push_back
(
Op3
)
;
OutOps
.
push_back
(
Op4
)
;
return
false
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> static bool tilepro_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) { return ( arg . type && TYPE_SIZE ( arg . type ) && TREE_CODE ( TYPE_SIZE ( arg . type ) ) != INTEGER_CST ) ; } </s>

Implement TARGET_PASS_BY_REFERENCE . Variable sized types are passed by reference .


<s> bool AArch64FrameLowering :: canUseAsPrologue ( const MachineBasicBlock & MBB ) const { const MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ; const AArch64Subtarget & Subtarget = MF -> getSubtarget < AArch64Subtarget > ( ) ; const AArch64RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; if ( ! RegInfo -> hasStackRealignment ( * MF ) ) return true ; return findScratchNonCalleeSaveRegister ( TmpMBB ) != AArch64 :: NoRegister ; } </s>

Check whether or not the given MBB can be used as a prologue for the target .


<s> TargetLowering :: AtomicExpansionKind RISCVTargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * CI ) const { unsigned Size = CI -> getCompareOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size == 8 || Size == 16 ) return AtomicExpansionKind :: MaskedIntrinsic ; return AtomicExpansionKind :: None ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> int nios2_initial_elimination_offset ( int from , int to ) { int offset ; nios2_compute_frame_layout ( ) ; switch ( from ) { case FRAME_POINTER_REGNUM : offset = cfun -> machine -> args_size ; break ; case ARG_POINTER_REGNUM : offset = cfun -> machine -> total_size ; offset -= crtl -> args . pretend_args_size ; break ; default : gcc_unreachable ( ) ; } if ( to == HARD_FRAME_POINTER_REGNUM ) offset -= ( cfun -> machine -> save_regs_offset + cfun -> machine -> fp_save_offset ) ; return offset ; } </s>

Implement INITIAL_ELIMINATION_OFFSET macro .


<s> virtual void EmitInstruction ( const MachineInstr * MI ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; printInstruction ( MI , OS ) ; OutStreamer . EmitRawText ( OS . str ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static const MachineOperand & getLdStOffsetOp ( const MachineInstr * MI ) { return MI -> getOperand ( 2 ) ; } </s>

Returns the immediate offset operator of a load/store .


<s>
SDValue
MSP430TargetLowering
::
LowerCall
(
TargetLowering
::
CallLoweringInfo
&
CLI
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SelectionDAG
&
DAG
=
CLI
.
DAG
;
SDLoc
&
dl
=
CLI
.
DL
;
SmallVector
<
ISD
::
OutputArg
,
32
>
&
Outs
=
CLI
.
Outs
;
SmallVector
<
SDValue
,
32
>
&
OutVals
=
CLI
.
OutVals
;
SmallVector
<
ISD
::
InputArg
,
32
>
&
Ins
=
CLI
.
Ins
;
SDValue
Chain
=
CLI
.
Chain
;
SDValue
Callee
=
CLI
.
Callee
;
bool
&
isTailCall
=
CLI
.
IsTailCall
;
CallingConv
::
ID
CallConv
=
CLI
.
CallConv
;
bool
isVarArg
=
CLI
.
IsVarArg
;
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
OutVals
,
Ins
,
dl
,
DAG
,
InVals
)
;
case
CallingConv
::
MSP430_INTR
:
report_fatal_error
(
"ISRs cannot be called directly"
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .


<s> static bool nds32_warn_func_return ( tree decl ) { return ! nds32_naked_function_p ( decl ) ; } </s>

Determine whether we need to enable warning for function return check .


"Load should return a value and a chain"

LowerOperation - Provide custom lowering hooks for some operations .


<s> int nds32_can_use_return_insn ( void ) { int sp_adjust ; if ( ! reload_completed ) return 0 ; sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; if ( ! cfun -> machine -> fp_as_gp_p && satisfies_constraint_Iu08 ( GEN_INT ( sp_adjust ) ) && NDS32_DOUBLE_WORD_ALIGN_P ( sp_adjust ) && ! cfun -> calls_alloca && NDS32_V3PUSH_AVAILABLE_P && ! ( TARGET_HARD_FLOAT && ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) ) ) return 1 ; return ( cfun -> machine -> naked_p && ( cfun -> machine -> va_args_size == 0 ) ) ; } </s>

Return nonzero if this function is known to have a null epilogue . This allows the optimizer to omit jumps to jumps if no stack was created .


<s> void rs6000_gen_section_name ( char * * buf , const char * filename , const char * section_desc ) { const char * q , * after_last_slash , * last_period = 0 ; char * p ; int len ; after_last_slash = filename ; for ( q = filename ; * q ; q ++ ) { if ( * q == '/' ) after_last_slash = q + 1 ; else if ( * q == '.' ) last_period = q ; } len = strlen ( after_last_slash ) + strlen ( section_desc ) + 2 ; * buf = ( char * ) xmalloc ( len ) ; p = * buf ; * p ++ = '_' ; for ( q = after_last_slash ; * q ; q ++ ) { if ( q == last_period ) { strcpy ( p , section_desc ) ; p += strlen ( section_desc ) ; break ; } else if ( ISALNUM ( * q ) ) * p ++ = * q ; } if ( last_period == 0 ) strcpy ( p , section_desc ) ; else * p = '\0' ; } </s>

Generate a unique section name for FILENAME for a section type represented by SECTION_DESC . Output goes into BUF . SECTION_DESC can be any string , as long as it is different for each possible section type . We name the section in the same manner as xlc . The name begins with an underscore followed by the filename ( after stripping any leading directory names ) with the last period replaced by the string SECTION_DESC . If FILENAME does not contain a period , SECTION_DESC is appended to the end of the name .


<s> static inline unsigned slice ( uint32_t Bits , unsigned From , unsigned To ) { assert ( From < 32 && To < 32 && From >= To ) ; return ( Bits >> To ) & ( ( 1 << ( From - To + 1 ) ) - 1 ) ; } </s>

Return a reference to the substring from [ Start , End ) .


<s> SDValue ARMTargetLowering :: BuildSDIVPow2 ( SDNode * N , const APInt & Divisor , SelectionDAG & DAG , SmallVectorImpl < SDNode * > & Created ) const { if ( N -> getOpcode ( ) != ISD :: SDIV ) return SDValue ( ) ; const auto & ST = static_cast < const ARMSubtarget & > ( DAG . getSubtarget ( ) ) ; const bool MinSize = ST . optForMinSize ( ) ; const bool HasDivide = ST . isThumb ( ) ? ST . hasDivideInThumbMode ( ) : ST . hasDivideInARMMode ( ) ; if ( N -> getOperand ( 0 ) . getValueType ( ) . isVector ( ) ) return SDValue ( ) ; if ( ! ( MinSize && HasDivide ) ) return SDValue ( ) ; if ( ! ST . isThumb ( ) ) return SDValue ( N , 0 ) ; if ( Divisor . sgt ( 128 ) ) return SDValue ( ) ; return SDValue ( N , 0 ) ; } </s>

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators .


<s> void alpha_split_tfmode_pair ( rtx operands [ 4 ] ) { switch ( GET_CODE ( operands [ 1 ] ) ) { case REG : operands [ 3 ] = gen_rtx_REG ( DImode , REGNO ( operands [ 1 ] ) + 1 ) ; operands [ 2 ] = gen_rtx_REG ( DImode , REGNO ( operands [ 1 ] ) ) ; break ; case MEM : operands [ 3 ] = adjust_address ( operands [ 1 ] , DImode , 8 ) ; operands [ 2 ] = adjust_address ( operands [ 1 ] , DImode , 0 ) ; break ; case CONST_DOUBLE : gcc_assert ( operands [ 1 ] == CONST0_RTX ( TFmode ) ) ; operands [ 2 ] = operands [ 3 ] = const0_rtx ; break ; default : gcc_unreachable ( ) ; } switch ( GET_CODE ( operands [ 0 ] ) ) { case REG : operands [ 1 ] = gen_rtx_REG ( DImode , REGNO ( operands [ 0 ] ) + 1 ) ; operands [ 0 ] = gen_rtx_REG ( DImode , REGNO ( operands [ 0 ] ) ) ; break ; case MEM : operands [ 1 ] = adjust_address ( operands [ 0 ] , DImode , 8 ) ; operands [ 0 ] = adjust_address ( operands [ 0 ] , DImode , 0 ) ; break ; default : gcc_unreachable ( ) ; } } </s>

Split a TFmode OP [ 1 ] into DImode OP [ 2,3 ] and likewise for OP [ 0 ] into OP [ 0,1 ] . Naturally , output operand ordering is little-endian .


runOnMachineFunction - Emit the function body .


<s>
static
unsigned
getOpcode_EXTEND
(
unsigned
Opcode
)
{
switch
(
Opcode
)
{
case
ISD
::
ANY_EXTEND
:
case
ISD
::
ANY_EXTEND_VECTOR_INREG
:
return
ISD
::
ANY_EXTEND
;
case
ISD
::
ZERO_EXTEND
:
case
ISD
::
ZERO_EXTEND_VECTOR_INREG
:
return
ISD
::
ZERO_EXTEND
;
case
ISD
::
SIGN_EXTEND
:
case
ISD
::
SIGN_EXTEND_VECTOR_INREG
:
return
ISD
::
SIGN_EXTEND
;
}
llvm_unreachable
(
"Unknown opcode"
)
;
}
</s>

Convert * _EXTEND_VECTOR_INREG to * _EXTEND opcode .


"Cannot store this register to stack slot!"

Load the specified register of the given register class from the specified stack frame index .


<s>
static
void
rs6000_elf_output_toc_section_asm_op
(
const
void
*
data
ATTRIBUTE_UNUSED
)
{
if
(
(
DEFAULT_ABI
==
ABI_AIX
||
DEFAULT_ABI
==
ABI_ELFv2
)
&&
TARGET_MINIMAL_TOC
)
{
if
(
!
toc_initialized
)
{
fprintf
(
asm_out_file
,
"%s\n"
,
TOC_SECTION_ASM_OP
)
;
ASM_OUTPUT_ALIGN
(
asm_out_file
,
TARGET_64BIT
3
:
2
)
;
(
*
targetm
.
asm_out
.
internal_label
)
(
asm_out_file
,
"LCTOC"
,
0
)
;
fprintf
(
asm_out_file
,
"\t.tc "
)
;
ASM_OUTPUT_INTERNAL_LABEL_PREFIX
(
asm_out_file
,
"LCTOC1[TC],"
)
;
ASM_OUTPUT_INTERNAL_LABEL_PREFIX
(
asm_out_file
,
"LCTOC1"
)
;
fprintf
(
asm_out_file
,
"\n"
)
;
fprintf
(
asm_out_file
,
"%s\n"
,
MINIMAL_TOC_SECTION_ASM_OP
)
;
ASM_OUTPUT_ALIGN
(
asm_out_file
,
TARGET_64BIT
3
:
2
)
;
ASM_OUTPUT_INTERNAL_LABEL_PREFIX
(
asm_out_file
,
"LCTOC1"
)
;
fprintf
(
asm_out_file
,
" = .+32768\n"
)
;
toc_initialized
=
1
;
}
else
fprintf
(
asm_out_file
,
"%s\n"
,
MINIMAL_TOC_SECTION_ASM_OP
)
;
}
else
if
(
DEFAULT_ABI
==
ABI_AIX
||
DEFAULT_ABI
==
ABI_ELFv2
)
{
fprintf
(
asm_out_file
,
"%s\n"
,
TOC_SECTION_ASM_OP
)
;
if
(
!
toc_initialized
)
{
ASM_OUTPUT_ALIGN
(
asm_out_file
,
TARGET_64BIT
3
:
2
)
;
toc_initialized
=
1
;
}
}
else
{
fprintf
(
asm_out_file
,
"%s\n"
,
MINIMAL_TOC_SECTION_ASM_OP
)
;
if
(
!
toc_initialized
)
{
ASM_OUTPUT_ALIGN
(
asm_out_file
,
TARGET_64BIT
3
:
2
)
;
ASM_OUTPUT_INTERNAL_LABEL_PREFIX
(
asm_out_file
,
"LCTOC1"
)
;
fprintf
(
asm_out_file
,
" = .+32768\n"
)
;
toc_initialized
=
1
;
}
}
}
</s>

A get_unnamed_section callback , used for switching to toc_section .


<s> rtx spu_const ( machine_mode mode , HOST_WIDE_INT val ) { rtx inner ; gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_INT || GET_MODE_CLASS ( mode ) == MODE_FLOAT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT ) ; if ( GET_MODE_CLASS ( mode ) == MODE_INT ) return immed_double_const ( val , 0 , mode ) ; if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return hwint_to_const_double ( mode , val ) ; if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) inner = immed_double_const ( val , 0 , GET_MODE_INNER ( mode ) ) ; else inner = hwint_to_const_double ( GET_MODE_INNER ( mode ) , val ) ; return gen_const_vec_duplicate ( mode , inner ) ; } </s>

Given VAL , generate a constant appropriate for MODE . If MODE is a vector mode , every element will be VAL . For TImode , VAL will be zero extended to 128 bits .


<s> void SystemZXPLINKFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; const SystemZSubtarget & Subtarget = MF . getSubtarget < SystemZSubtarget > ( ) ; auto & Regs = Subtarget . getSpecialRegisters < SystemZXPLINK64Registers > ( ) ; MFFrame . setOffsetAdjustment ( Regs . getStackPointerBias ( ) ) ; } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> void rs6000_emit_prologue_components ( sbitmap components ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; rtx ptr_reg = gen_rtx_REG ( Pmode , frame_pointer_needed_indeed ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ) ; machine_mode reg_mode = Pmode ; int reg_size = TARGET_32BIT ? 4 : 8 ; machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode ; int fp_reg_size = 8 ; if ( bitmap_bit_p ( components , 0 ) ) { rtx lr = gen_rtx_REG ( reg_mode , LR_REGNO ) ; rtx reg = gen_rtx_REG ( reg_mode , 0 ) ; rtx_insn * insn = emit_move_insn ( reg , lr ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_REGISTER , gen_rtx_SET ( reg , lr ) ) ; int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; rtx mem = copy_rtx ( SET_DEST ( single_set ( insn ) ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , gen_rtx_SET ( mem , lr ) ) ; } if ( bitmap_bit_p ( components , 2 ) ) { rtx reg = gen_rtx_REG ( reg_mode , TOC_REGNUM ) ; rtx sp_reg = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; emit_insn ( gen_frame_store ( reg , sp_reg , RS6000_TOC_SAVE_SLOT ) ) ; } int offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_gp_reg_save ; i < 32 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; rtx set = copy_rtx ( single_set ( insn ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , set ) ; } offset += reg_size ; } offset = info -> fp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_fp_reg_save ; i < 64 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( fp_reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; rtx set = copy_rtx ( single_set ( insn ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , set ) ; } offset += fp_reg_size ; } } </s>


"Handling of TOC entry displacement larger than 32767 "

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> unsigned PPCDispatchGroupSBHazardRecognizer :: PreEmitNoops ( SUnit * SU ) { if ( isLoadAfterStore ( SU ) && CurSlots < 6 ) { unsigned Directive = DAG -> MF . getSubtarget < PPCSubtarget > ( ) . getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_PWR6 || Directive == PPC :: DIR_PWR7 || Directive == PPC :: DIR_PWR8 ) return 1 ; return 5 - CurSlots ; } return ScoreboardHazardRecognizer :: PreEmitNoops ( SU ) ; } </s>

PreEmitNoops - This callback is invoked prior to emitting an instruction .


<s> bool ARMBaseInstrInfo :: isPredicable ( const MachineInstr & MI ) const { if ( ! MI . isPredicable ( ) ) return false ; if ( MI . isBundle ( ) ) return false ; if ( ! isEligibleForITBlock ( & MI ) ) return false ; const ARMFunctionInfo * AFI = MI . getParent ( ) -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; if ( ( MI . getDesc ( ) . TSFlags & ARMII :: DomainMask ) == ARMII :: DomainNEON ) return false ; if ( AFI -> isThumb2Function ( ) ) { if ( getSubtarget ( ) . restrictIT ( ) ) return isV8EligibleForIT ( & MI ) ; } return true ; } </s>

Return true if the specified instruction can be predicated .

ARM ARM ARM ARM ARMII::DomainMask ARMII::DomainNEON


<s> void ARMAsmPrinter :: emitFunctionEntryLabel ( ) { if ( AFI -> isThumbFunction ( ) ) { OutStreamer -> emitAssemblerFlag ( MCAF_Code16 ) ; OutStreamer -> emitThumbFunc ( CurrentFnSym ) ; } else { OutStreamer -> emitAssemblerFlag ( MCAF_Code32 ) ; } if ( AFI -> isCmseNSEntryFunction ( ) ) { MCSymbol * S = OutContext . getOrCreateSymbol ( "__acle_se_" + CurrentFnSym -> getName ( ) ) ; emitLinkage ( & MF -> getFunction ( ) , S ) ; OutStreamer -> emitSymbolAttribute ( S , MCSA_ELF_TypeFunction ) ; OutStreamer -> emitLabel ( S ) ; } OutStreamer -> emitLabel ( CurrentFnSym ) ; } </s>

EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function .


<s> static unsigned findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const TargetRegisterInfo & TRI , bool Is64Bit ) { const MachineFunction * MF = MBB . getParent ( ) ; const Function * F = MF -> getFunction ( ) ; if ( ! F || MF -> getMMI ( ) . callsEHReturn ( ) ) return 0 ; static const uint16_t CallerSavedRegs32Bit [ ] = { X86 :: EAX , X86 :: EDX , X86 :: ECX , 0 } ; static const uint16_t CallerSavedRegs64Bit [ ] = { X86 :: RAX , X86 :: RDX , X86 :: RCX , X86 :: RSI , X86 :: RDI , X86 :: R8 , X86 :: R9 , X86 :: R10 , X86 :: R11 , 0 } ; unsigned Opc = MBBI -> getOpcode ( ) ; switch ( Opc ) { default : return 0 ; case X86 :: RET : case X86 :: RETI : case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: TCRETURNmi64 : case X86 :: EH_RETURN : case X86 :: EH_RETURN64 : { SmallSet < uint16_t , 8 > Uses ; for ( unsigned i = 0 , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( const uint16_t * AsI = TRI . getOverlaps ( Reg ) ; * AsI ; ++ AsI ) Uses . insert ( * AsI ) ; } const uint16_t * CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit ; for ( ; * CS ; ++ CS ) if ( ! Uses . count ( * CS ) ) return * CS ; } } return 0 ; } </s>

findDeadCallerSavedReg - Return a caller-saved register that is n't live when it reaches the `` return '' instruction .


<s> void MipsSEFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned BP = ABI . IsN64 ( ) ? Mips :: S7_64 : Mips :: S7 ; if ( hasFP ( MF ) ) setAliasRegs ( MF , SavedRegs , FP ) ; if ( hasBP ( MF ) ) setAliasRegs ( MF , SavedRegs , BP ) ; if ( MipsFI -> callsEhReturn ( ) ) MipsFI -> createEhDataRegsFI ( ) ; if ( MipsFI -> isISR ( ) ) MipsFI -> createISRRegFI ( ) ; if ( ExpandPseudo ( MF ) . expand ( ) ) { const TargetRegisterClass * RC = STI . hasMips64 ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } uint64_t MaxSPOffset = MF . getInfo < MipsFunctionInfo > ( ) -> getIncomingArgSize ( ) + estimateStackSize ( MF ) ; if ( isInt < 16 > ( MaxSPOffset ) ) return ; const TargetRegisterClass * RC = ABI . ArePtrs64bit ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> static void nios2_create_cfa_notes ( rtx_insn * insn , bool epilogue_p ) { int i = 0 ; rtx base_reg , offset , elt , pat = PATTERN ( insn ) ; if ( epilogue_p ) { elt = XVECEXP ( pat , 0 , 0 ) ; if ( GET_CODE ( elt ) == RETURN ) i ++ ; elt = XVECEXP ( pat , 0 , i ) ; if ( base_reg_adjustment_p ( elt , & base_reg , & offset ) ) { add_reg_note ( insn , REG_CFA_ADJUST_CFA , copy_rtx ( elt ) ) ; i ++ ; } for ( ; i < XVECLEN ( pat , 0 ) ; i ++ ) { elt = SET_DEST ( XVECEXP ( pat , 0 , i ) ) ; gcc_assert ( REG_P ( elt ) ) ; add_reg_note ( insn , REG_CFA_RESTORE , elt ) ; } } else { for ( i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) RTX_FRAME_RELATED_P ( XVECEXP ( pat , 0 , i ) ) = 1 ; } } </s>

Does the CFA note work for push/pop prologue/epilogue instructions .


<s> unsigned epiphany_special_round_type_align ( tree type , unsigned computed , unsigned specified ) { unsigned align = MAX ( computed , specified ) ; tree field ; HOST_WIDE_INT total , max ; unsigned try_align = FASTEST_ALIGNMENT ; if ( maximum_field_alignment && try_align > maximum_field_alignment ) try_align = maximum_field_alignment ; if ( align >= try_align ) return align ; for ( max = 0 , field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { tree offset , size ; if ( TREE_CODE ( field ) != FIELD_DECL || TREE_TYPE ( field ) == error_mark_node ) continue ; offset = bit_position ( field ) ; size = DECL_SIZE ( field ) ; if ( ! tree_fits_uhwi_p ( offset ) || ! tree_fits_uhwi_p ( size ) || tree_to_uhwi ( offset ) >= try_align || tree_to_uhwi ( size ) >= try_align ) return try_align ; total = tree_to_uhwi ( offset ) + tree_to_uhwi ( size ) ; if ( total > max ) max = total ; } if ( max >= ( HOST_WIDE_INT ) try_align ) align = try_align ; else if ( try_align > 32 && max >= 32 ) align = max > 32 ? 64 : 32 ; return align ; } </s>

STRUCTURE_SIZE_BOUNDARY seems a bit crude in how it enlarges small structs . Make structs double-word-aligned it they are a double word or ( potentially ) larger ; failing that , do the same for a size of 32 bits .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM ) : LLVMTargetMachine ( T , TT , CPU , FS , RM , CM ) , Subtarget ( TT , CPU , FS ) , JITInfo ( ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) { if ( FloatABIType == FloatABI :: Default ) FloatABIType = FloatABI :: Soft ; } </s>


<s>
unsigned
Mips16InstrInfo
::
getOppositeBranchOpc
(
unsigned
Opc
)
const
{
switch
(
Opc
)
{
default
:
llvm_unreachable
(
"Illegal opcode!"
)
;
case
Mips
::
BeqzRxImmX16
:
return
Mips
::
BnezRxImmX16
;
case
Mips
::
BnezRxImmX16
:
return
Mips
::
BeqzRxImmX16
;
case
Mips
::
BteqzT8CmpX16
:
return
Mips
::
BtnezT8CmpX16
;
case
Mips
::
BteqzT8SltX16
:
return
Mips
::
BtnezT8SltX16
;
case
Mips
::
BteqzT8SltiX16
:
return
Mips
::
BtnezT8SltiX16
;
case
Mips
::
BtnezX16
:
return
Mips
::
BteqzX16
;
case
Mips
::
BtnezT8CmpiX16
:
return
Mips
::
BteqzT8CmpiX16
;
case
Mips
::
BtnezT8SltuX16
:
return
Mips
::
BteqzT8SltuX16
;
case
Mips
::
BtnezT8SltiuX16
:
return
Mips
::
BteqzT8SltiuX16
;
case
Mips
::
BteqzX16
:
return
Mips
::
BtnezX16
;
case
Mips
::
BteqzT8CmpiX16
:
return
Mips
::
BtnezT8CmpiX16
;
case
Mips
::
BteqzT8SltuX16
:
return
Mips
::
BtnezT8SltuX16
;
case
Mips
::
BteqzT8SltiuX16
:
return
Mips
::
BtnezT8SltiuX16
;
case
Mips
::
BtnezT8CmpX16
:
return
Mips
::
BteqzT8CmpX16
;
case
Mips
::
BtnezT8SltX16
:
return
Mips
::
BteqzT8SltX16
;
case
Mips
::
BtnezT8SltiX16
:
return
Mips
::
BteqzT8SltiX16
;
}
assert
(
false
&&
"Implement this function."
)
;
return
0
;
}
</s>

getOppositeBranchOpc - Return the inverse of the specified opcode , e.g .


<s> virtual const Dcpu16InstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> bool ix86_expand_pextr ( rtx * operands ) { rtx dst = operands [ 0 ] ; rtx src = operands [ 1 ] ; unsigned int size = INTVAL ( operands [ 2 ] ) ; unsigned int pos = INTVAL ( operands [ 3 ] ) ; if ( SUBREG_P ( dst ) ) { if ( SUBREG_BYTE ( dst ) > 0 ) return false ; dst = SUBREG_REG ( dst ) ; } if ( SUBREG_P ( src ) ) { pos += SUBREG_BYTE ( src ) * BITS_PER_UNIT ; src = SUBREG_REG ( src ) ; } switch ( GET_MODE ( src ) ) { case E_V16QImode : case E_V8HImode : case E_V4SImode : case E_V2DImode : case E_V1TImode : { machine_mode srcmode , dstmode ; rtx d , pat ; if ( ! int_mode_for_size ( size , 0 ) . exists ( & dstmode ) ) return false ; switch ( dstmode ) { case E_QImode : if ( ! TARGET_SSE4_1 ) return false ; srcmode = V16QImode ; break ; case E_HImode : if ( ! TARGET_SSE2 ) return false ; srcmode = V8HImode ; break ; case E_SImode : if ( ! TARGET_SSE4_1 ) return false ; srcmode = V4SImode ; break ; case E_DImode : gcc_assert ( TARGET_64BIT ) ; if ( ! TARGET_SSE4_1 ) return false ; srcmode = V2DImode ; break ; default : return false ; } if ( pos & ( size - 1 ) ) return false ; if ( GET_MODE ( dst ) == dstmode ) d = dst ; else d = gen_reg_rtx ( dstmode ) ; pat = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 1 , GEN_INT ( pos / size ) ) ) ; pat = gen_rtx_VEC_SELECT ( dstmode , gen_lowpart ( srcmode , src ) , pat ) ; if ( dstmode == QImode || dstmode == HImode ) { pat = gen_rtx_ZERO_EXTEND ( SImode , pat ) ; d = gen_lowpart ( SImode , d ) ; } emit_insn ( gen_rtx_SET ( d , pat ) ) ; if ( d != dst ) emit_move_insn ( dst , gen_lowpart ( GET_MODE ( dst ) , d ) ) ; return true ; } default : return false ; } } </s>

Expand an extract from a vector register through pextr insn . Return true if successful .


<s> void neon_reinterpret ( rtx dest , rtx src ) { emit_move_insn ( dest , gen_lowpart ( GET_MODE ( dest ) , src ) ) ; } </s>

Emit code to reinterpret one Neon type as another , without altering bits .


<s> static rtx aapcs_vfp_allocate_return_reg ( enum arm_pcs pcs_variant ATTRIBUTE_UNUSED , machine_mode mode , const_tree type ATTRIBUTE_UNUSED ) { if ( ! use_vfp_abi ( pcs_variant , false ) ) return NULL ; if ( mode == BLKmode || ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) >= GET_MODE_SIZE ( TImode ) && ! TARGET_NEON ) ) { int count ; machine_mode ag_mode ; int i ; rtx par ; int shift ; aapcs_vfp_is_call_or_return_candidate ( pcs_variant , mode , type , & ag_mode , & count ) ; if ( ! TARGET_NEON ) { if ( ag_mode == V2SImode ) ag_mode = DImode ; else if ( ag_mode == V4SImode ) { ag_mode = DImode ; count *= 2 ; } } shift = GET_MODE_SIZE ( ag_mode ) / GET_MODE_SIZE ( SFmode ) ; par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( count ) ) ; for ( i = 0 ; i < count ; i ++ ) { rtx tmp = gen_rtx_REG ( ag_mode , FIRST_VFP_REGNUM + i * shift ) ; tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , GEN_INT ( i * GET_MODE_SIZE ( ag_mode ) ) ) ; XVECEXP ( par , 0 , i ) = tmp ; } return par ; } return gen_rtx_REG ( mode , FIRST_VFP_REGNUM ) ; } </s>

Implement the allocate_return_reg field in aapcs_cp_arg_layout . See the comment there for the behaviour of this function .


<s> static bool use_rsqrt_p ( void ) { return ( ! flag_trapping_math && flag_unsafe_math_optimizations && ( ( aarch64_tune_params . extra_tuning_flags & AARCH64_EXTRA_TUNE_APPROX_RSQRT ) || flag_mrecip_low_precision_sqrt ) ) ; } </s>

Return true if it is safe to use the rsqrt optabs to optimize 1.0/sqrt .


<s> void nvptx_function_end ( FILE * file ) { fprintf ( file , "}\n" ) ; } </s>

Terminate a function by writing a closing brace to FILE .