<s> static void sparc_emit_set_const64_longway ( rtx op0 , rtx temp , unsigned HOST_WIDE_INT high_bits , unsigned HOST_WIDE_INT low_bits ) { rtx sub_temp = op0 ; if ( can_create_pseudo_p ( ) ) sub_temp = gen_reg_rtx ( DImode ) ; if ( ( high_bits & 0xfffffc00 ) != 0 ) { emit_insn ( gen_safe_HIGH64 ( temp , high_bits ) ) ; if ( ( high_bits & ~ 0xfffffc00 ) != 0 ) emit_insn ( gen_rtx_SET ( sub_temp , gen_safe_OR64 ( temp , ( high_bits & 0x3ff ) ) ) ) ; else sub_temp = temp ; } else { emit_insn ( gen_safe_SET64 ( temp , high_bits ) ) ; sub_temp = temp ; } if ( can_create_pseudo_p ( ) ) { rtx temp2 = gen_reg_rtx ( DImode ) ; rtx temp3 = gen_reg_rtx ( DImode ) ; rtx temp4 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_rtx_SET ( temp4 , gen_rtx_ASHIFT ( DImode , sub_temp , GEN_INT ( 32 ) ) ) ) ; emit_insn ( gen_safe_HIGH64 ( temp2 , low_bits ) ) ; if ( ( low_bits & ~ 0xfffffc00 ) != 0 ) { emit_insn ( gen_rtx_SET ( temp3 , gen_safe_OR64 ( temp2 , ( low_bits & 0x3ff ) ) ) ) ; emit_insn ( gen_rtx_SET ( op0 , gen_rtx_PLUS ( DImode , temp4 , temp3 ) ) ) ; } else { emit_insn ( gen_rtx_SET ( op0 , gen_rtx_PLUS ( DImode , temp4 , temp2 ) ) ) ; } } else { rtx low1 = GEN_INT ( ( low_bits >> ( 32 - 12 ) ) & 0xfff ) ; rtx low2 = GEN_INT ( ( low_bits >> ( 32 - 12 - 12 ) ) & 0xfff ) ; rtx low3 = GEN_INT ( ( low_bits >> ( 32 - 12 - 12 - 8 ) ) & 0x0ff ) ; int to_shift = 12 ; if ( low1 != const0_rtx ) { emit_insn ( gen_rtx_SET ( op0 , gen_rtx_ASHIFT ( DImode , sub_temp , GEN_INT ( to_shift ) ) ) ) ; emit_insn ( gen_rtx_SET ( op0 , gen_rtx_IOR ( DImode , op0 , low1 ) ) ) ; sub_temp = op0 ; to_shift = 12 ; } else { to_shift += 12 ; } if ( low2 != const0_rtx ) { emit_insn ( gen_rtx_SET ( op0 , gen_rtx_ASHIFT ( DImode , sub_temp , GEN_INT ( to_shift ) ) ) ) ; emit_insn ( gen_rtx_SET ( op0 , gen_rtx_IOR ( DImode , op0 , low2 ) ) ) ; sub_temp = op0 ; to_shift = 8 ; } else { to_shift += 8 ; } emit_insn ( gen_rtx_SET ( op0 , gen_rtx_ASHIFT ( DImode , sub_temp , GEN_INT ( to_shift ) ) ) ) ; if ( low3 != const0_rtx ) emit_insn ( gen_rtx_SET ( op0 , gen_rtx_IOR ( DImode , op0 , low3 ) ) ) ; } } </s>

Full 64-bit constant decomposition . Even though this is the 'worst ' case , we still optimize a few things away .


<s> const MCPhysReg * Comet2RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_SaveList ; } </s>


<s>
void
set
(
size_t
Slot
,
const
StackVreg
&
Elem
)
{
assert
(
Slot
<
Data
.
size
(
)
&&
"Out of range access"
)
;
Data
[
Slot
]
=
Elem
;
}
</s>

Set the generated scalar V for Def and the given Instance .


<s> static pad_direction iq2000_function_arg_padding ( machine_mode mode , const_tree type ) { return ( ! BYTES_BIG_ENDIAN ? PAD_UPWARD : ( ( mode == BLKmode ? ( type && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && int_size_in_bytes ( type ) < ( PARM_BOUNDARY / BITS_PER_UNIT ) ) : ( GET_MODE_BITSIZE ( mode ) < PARM_BOUNDARY && GET_MODE_CLASS ( mode ) == MODE_INT ) ) ? PAD_DOWNWARD : PAD_UPWARD ) ) ; } </s>


<s> void pdp11_expand_epilogue ( void ) { HOST_WIDE_INT fsize = get_frame_size ( ) ; unsigned regno ; rtx x , reg , via_ac = NULL ; if ( fsize ) { if ( frame_pointer_needed ) { emit_move_insn ( stack_pointer_rtx , frame_pointer_rtx ) ; } else emit_insn ( gen_addhi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( fsize ) ) ) ; } if ( pdp11_saved_regno ( AC4_REGNUM ) || pdp11_saved_regno ( AC5_REGNUM ) ) { for ( regno = AC0_REGNUM ; regno <= AC3_REGNUM ; regno ++ ) if ( pdp11_saved_regno ( regno ) ) { via_ac = gen_rtx_REG ( DFmode , regno ) ; break ; } } for ( regno = AC5_REGNUM ; regno >= AC0_REGNUM ; regno -- ) if ( pdp11_saved_regno ( regno ) ) { x = gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ; x = gen_frame_mem ( DFmode , x ) ; reg = gen_rtx_REG ( DFmode , regno ) ; if ( LOAD_FPU_REG_P ( regno ) ) emit_move_insn ( reg , x ) ; else { emit_move_insn ( via_ac , x ) ; emit_move_insn ( reg , via_ac ) ; } } for ( regno = PC_REGNUM ; regno >= R0_REGNUM + 2 ; regno -- ) if ( pdp11_saved_regno ( regno ) ) { x = gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ; x = gen_frame_mem ( Pmode , x ) ; emit_move_insn ( gen_rtx_REG ( Pmode , regno ) , x ) ; } emit_jump_insn ( gen_rtspc ( ) ) ; } </s>

Generate epilogue . This uses the frame pointer to pop the local variables and any alloca data off the stack . If there is no alloca and frame pointer elimination has n't been disabled , there is no frame pointer and the local variables are popped by adjusting the stack pointer instead .


<s> const MCPhysReg * SIRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { CallingConv :: ID CC = MF -> getFunction ( ) -> getCallingConv ( ) ; switch ( CC ) { case CallingConv :: C : case CallingConv :: Fast : case CallingConv :: Cold : return CSR_AMDGPU_HighRegs_SaveList ; default : { static const MCPhysReg NoCalleeSavedReg = AMDGPU :: NoRegister ; return & NoCalleeSavedReg ; } } } </s>


<s> unsigned getLength ( ) { return CurType . Length ; } </s>

Return the number of bytes of data in this stream .


<s> const uint16_t * FISCRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { FISC :: LR , FISC :: X19 , FISC :: X20 , FISC :: X21 , FISC :: X22 , FISC :: X23 , FISC :: X24 , FISC :: X25 , FISC :: X26 , FISC :: X27 , 0 } ; return CalleeSavedRegs ; } </s>


<s> static rtx aarch64_function_value ( const_tree type , const_tree func , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode mode ; int unsignedp ; int count ; machine_mode ag_mode ; mode = TYPE_MODE ( type ) ; if ( INTEGRAL_TYPE_P ( type ) ) mode = promote_function_mode ( type , mode , & unsignedp , func , 1 ) ; if ( aarch64_return_in_msb ( type ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; if ( size % UNITS_PER_WORD != 0 ) { size += UNITS_PER_WORD - size % UNITS_PER_WORD ; mode = int_mode_for_size ( size * BITS_PER_UNIT , 0 ) . require ( ) ; } } if ( aarch64_vfp_is_call_or_return_candidate ( mode , type , & ag_mode , & count , NULL ) ) { if ( ! aarch64_composite_type_p ( type , mode ) ) { gcc_assert ( count == 1 && mode == ag_mode ) ; return gen_rtx_REG ( mode , V0_REGNUM ) ; } else { int i ; rtx par ; par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( count ) ) ; for ( i = 0 ; i < count ; i ++ ) { rtx tmp = gen_rtx_REG ( ag_mode , V0_REGNUM + i ) ; rtx offset = gen_int_mode ( i * GET_MODE_SIZE ( ag_mode ) , Pmode ) ; tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , offset ) ; XVECEXP ( par , 0 , i ) = tmp ; } return par ; } } else return gen_rtx_REG ( mode , R0_REGNUM ) ; } </s>

Implement TARGET_FUNCTION_VALUE . Define how to find the value returned by a function .


<s> bool PPCRegisterInfo :: isAsmClobberable ( const MachineFunction & MF , MCRegister PhysReg ) const { return PhysReg != PPC :: R1 && PhysReg != PPC :: X1 ; } </s>

Returns false if we ca n't guarantee that Physreg , specified as an IR asm clobber constraint , will be preserved across the statement .


<s> bool SITypeRewriter :: runOnFunction ( Function & F ) { if ( AMDGPU :: getShaderType ( F ) == ShaderType :: COMPUTE ) return false ; visit ( F ) ; visit ( F ) ; return false ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> unsigned getError ( ) const { return ( Error ) ; } </s>


<s> static void riscv_unique_section ( tree decl , int reloc ) { const char * prefix = NULL ; bool one_only = DECL_ONE_ONLY ( decl ) && ! HAVE_COMDAT_GROUP ; switch ( categorize_decl_for_section ( decl , reloc ) ) { case SECCAT_SRODATA : prefix = one_only ? ".sr" : ".srodata" ; break ; default : break ; } if ( prefix ) { const char * name , * linkonce ; char * string ; name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; name = targetm . strip_name_encoding ( name ) ; linkonce = one_only ? ".gnu.linkonce" : "" ; string = ACONCAT ( ( linkonce , prefix , "." , name , NULL ) ) ; set_decl_section_name ( decl , string ) ; return ; } default_unique_section ( decl , reloc ) ; } </s>

Switch to the appropriate section for output of DECL .


<s> void AArch64PassConfig :: addPreEmitPass ( ) { if ( EnableA53Fix835769 ) addPass ( createAArch64A53Fix835769 ( ) ) ; addPass ( createAArch64BranchRelaxation ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
InstructionCost
AArch64TTIImpl
::
getArithmeticReductionCost
(
unsigned
Opcode
,
VectorType
*
ValTy
,
bool
IsPairwiseForm
,
TTI
::
TargetCostKind
CostKind
)
{
if
(
isa
<
ScalableVectorType
>
(
ValTy
)
)
return
getArithmeticReductionCostSVE
(
Opcode
,
ValTy
,
IsPairwiseForm
,
CostKind
)
;
if
(
IsPairwiseForm
)
return
BaseT
::
getArithmeticReductionCost
(
Opcode
,
ValTy
,
IsPairwiseForm
,
CostKind
)
;
std
::
pair
<
InstructionCost
,
MVT
>
LT
=
TLI
->
getTypeLegalizationCost
(
DL
,
ValTy
)
;
MVT
MTy
=
LT
.
second
;
int
ISD
=
TLI
->
InstructionOpcodeToISD
(
Opcode
)
;
assert
(
ISD
&&
"Invalid opcode"
)
;
static
const
CostTblEntry
CostTblNoPairwise
[
]
{
{
ISD
::
ADD
,
MVT
::
v8i8
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v16i8
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v4i16
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v8i16
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v4i32
,
1
}
,
}
;
if
(
const
auto
*
Entry
=
CostTableLookup
(
CostTblNoPairwise
,
ISD
,
MTy
)
)
return
LT
.
first
*
Entry
->
Cost
;
return
BaseT
::
getArithmeticReductionCost
(
Opcode
,
ValTy
,
IsPairwiseForm
,
CostKind
)
;
}
</s>

Calculate the cost of vector reduction intrinsics .


<s>
StringRef
getPassName
(
)
const
override
{
return
"SI insert wait instructions"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> const DataLayout * getDataLayout ( ) const override { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> int symbolic_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { switch ( GET_CODE ( op ) ) { case SYMBOL_REF : case LABEL_REF : case CONST : return 1 ; default : return 0 ; } } </s>

Return 1 if X contains a symbolic expression . We know these expressions will have one of a few well defined forms , so we need only check those forms .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesAll ( ) ; AU . addRequired < MachineModuleInfoWrapperPass > ( ) ; ModulePass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO , ISD :: ArgFlagsTy Flags ) override { MachineFunction & MF = MIRBuilder . getMF ( ) ; const LLT PtrTy = LLT :: pointer ( AMDGPUAS :: PRIVATE_ADDRESS , 32 ) ; const LLT S32 = LLT :: scalar ( 32 ) ; if ( IsTailCall ) { Offset += FPDiff ; int FI = MF . getFrameInfo ( ) . CreateFixedObject ( Size , Offset , true ) ; auto FIReg = MIRBuilder . buildFrameIndex ( PtrTy , FI ) ; MPO = MachinePointerInfo :: getFixedStack ( MF , FI ) ; return FIReg . getReg ( 0 ) ; } const SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; if ( ! SPReg ) SPReg = MIRBuilder . buildCopy ( PtrTy , MFI -> getStackPtrOffsetReg ( ) ) . getReg ( 0 ) ; auto OffsetReg = MIRBuilder . buildConstant ( S32 , Offset ) ; auto AddrReg = MIRBuilder . buildPtrAdd ( PtrTy , SPReg , OffsetReg ) ; MPO = MachinePointerInfo :: getStack ( MF , Offset ) ; return AddrReg . getReg ( 0 ) ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> bool R600TargetLowering :: isZero ( SDValue Op ) const { if ( ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Op ) ) { return Cst -> isNullValue ( ) ; } else if ( ConstantFPSDNode * CstFP = dyn_cast < ConstantFPSDNode > ( Op ) ) { return CstFP -> isZero ( ) ; } else { return false ; } } </s>

Return true if the expression is a constant zero .


"sorry, I don't know how to load this sort of reg from the stack\n"

Load the specified register of the given register class from the specified stack frame index .


<s> bool SystemZAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & OS ) { SystemZInstPrinter :: printAddress ( MI -> getOperand ( OpNo ) . getReg ( ) , MI -> getOperand ( OpNo + 1 ) . getImm ( ) , MI -> getOperand ( OpNo + 2 ) . getReg ( ) , OS ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> Align SITargetLowering :: getPrefLoopAlignment ( MachineLoop * ML ) const { const Align PrefAlign = TargetLowering :: getPrefLoopAlignment ( ML ) ; const Align CacheLineAlign = Align ( 64 ) ; if ( ! ML || DisableLoopAlignment || ( getSubtarget ( ) -> getGeneration ( ) < AMDGPUSubtarget :: GFX10 ) || getSubtarget ( ) -> hasInstFwdPrefetchBug ( ) ) return PrefAlign ; const SIInstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; const MachineBasicBlock * Header = ML -> getHeader ( ) ; if ( Header -> getAlignment ( ) != PrefAlign ) return Header -> getAlignment ( ) ; unsigned LoopSize = 0 ; for ( const MachineBasicBlock * MBB : ML -> blocks ( ) ) { if ( MBB != Header ) LoopSize += MBB -> getAlignment ( ) . value ( ) / 2 ; for ( const MachineInstr & MI : * MBB ) { LoopSize += TII -> getInstSizeInBytes ( MI ) ; if ( LoopSize > 192 ) return PrefAlign ; } } if ( LoopSize <= 64 ) return PrefAlign ; if ( LoopSize <= 128 ) return CacheLineAlign ; for ( MachineLoop * P = ML -> getParentLoop ( ) ; P ; P = P -> getParentLoop ( ) ) { if ( MachineBasicBlock * Exit = P -> getExitBlock ( ) ) { auto I = Exit -> getFirstNonDebugInstr ( ) ; if ( I != Exit -> end ( ) && I -> getOpcode ( ) == AMDGPU :: S_INST_PREFETCH ) return CacheLineAlign ; } } MachineBasicBlock * Pre = ML -> getLoopPreheader ( ) ; MachineBasicBlock * Exit = ML -> getExitBlock ( ) ; if ( Pre && Exit ) { BuildMI ( * Pre , Pre -> getFirstTerminator ( ) , DebugLoc ( ) , TII -> get ( AMDGPU :: S_INST_PREFETCH ) ) . addImm ( 1 ) ; BuildMI ( * Exit , Exit -> getFirstNonDebugInstr ( ) , DebugLoc ( ) , TII -> get ( AMDGPU :: S_INST_PREFETCH ) ) . addImm ( 2 ) ; } return CacheLineAlign ; } </s>


<s> static const char * fp_const_from_val ( REAL_VALUE_TYPE * r ) { if ( ! fp_consts_inited ) init_fp_table ( ) ; gcc_assert ( REAL_VALUES_EQUAL ( * r , value_fp0 ) ) ; return "0" ; } </s>

As for fp_immediate_constant , but value is passed directly , not in rtx .


<s> unsigned AArch64FastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const auto * CI = dyn_cast < ConstantInt > ( C ) ) return materializeInt ( CI , VT ) ; else if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return materializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return materializeGV ( GV ) ; return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


"Unexpected operand for inline assembly"

PrintAsmOperand - Print out an operand for an inline asm expression .


<s>
bool
PPCInstrInfo
::
isReallyTriviallyReMaterializable
(
const
MachineInstr
&
MI
,
AliasAnalysis
*
AA
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown rematerializable operation!"
)
;
break
;
case
PPC
::
LI
:
case
PPC
::
LI8
:
case
PPC
::
LIS
:
case
PPC
::
LIS8
:
case
PPC
::
QVGPCI
:
case
PPC
::
ADDIStocHA
:
case
PPC
::
ADDItocL
:
case
PPC
::
LOAD_STACK_GUARD
:
case
PPC
::
XXLXORz
:
case
PPC
::
XXLXORspz
:
case
PPC
::
XXLXORdpz
:
case
PPC
::
V_SET0B
:
case
PPC
::
V_SET0H
:
case
PPC
::
V_SET0
:
case
PPC
::
V_SETALLONESB
:
case
PPC
::
V_SETALLONESH
:
case
PPC
::
V_SETALLONES
:
return
true
;
}
return
false
;
}
</s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> const Triple & getTargetTriple ( ) const { return TargetTriple ; } </s>

Get the target triple which is a string describing the target host .


"%qE attribute only applies to functions"

"%qE attribute requires a void return type"

Handle a `` kernel '' attribute ; arguments as in struct attribute_spec.handler .


<s>
static
const
char
*
avr_out_movhi_mr_r_xmega
(
rtx_insn
*
insn
,
rtx
op
[
]
,
int
*
plen
)
{
rtx
dest
=
op
[
0
]
;
rtx
src
=
op
[
1
]
;
rtx
base
=
XEXP
(
dest
,
0
)
;
int
reg_base
=
true_regnum
(
base
)
;
int
reg_src
=
true_regnum
(
src
)
;
int
mem_volatile_p
=
MEM_VOLATILE_P
(
dest
)
;
if
(
CONSTANT_ADDRESS_P
(
base
)
)
{
return
io_address_operand
(
base
,
HImode
)
avr_asm_len
(
"out %i0,%A1"
CR_TAB
"out %i0+1,%B1"
,
op
,
plen
,
2
)
:
avr_asm_len
(
"sts %m0,%A1"
CR_TAB
"sts %m0+1,%B1"
,
op
,
plen
,
4
)
;
}
if
(
reg_base
>
0
)
{
if
(
reg_base
!=
REG_X
)
return
avr_asm_len
(
"st %0,%A1"
CR_TAB
"std %0+1,%B1"
,
op
,
plen
,
2
)
;
if
(
reg_src
==
REG_X
)
avr_asm_len
(
"mov __tmp_reg__,r27"
CR_TAB
"st X,r26"
CR_TAB
"adiw r26,1"
CR_TAB
"st X,__tmp_reg__"
,
op
,
plen
,
4
)
;
else
avr_asm_len
(
"st X+,%A1"
CR_TAB
"st X,%B1"
,
op
,
plen
,
2
)
;
return
reg_unused_after
(
insn
,
base
)
""
:
avr_asm_len
(
"sbiw r26,1"
,
op
,
plen
,
1
)
;
}
else
if
(
GET_CODE
(
base
)
==
PLUS
)
{
int
disp
=
INTVAL
(
XEXP
(
base
,
1
)
)
;
reg_base
=
REGNO
(
XEXP
(
base
,
0
)
)
;
if
(
disp
>
MAX_LD_OFFSET
(
GET_MODE
(
dest
)
)
)
{
if
(
reg_base
!=
REG_Y
)
fatal_insn
(
"incorrect insn:"
,
insn
)
;
return
disp
<=
63
+
MAX_LD_OFFSET
(
GET_MODE
(
dest
)
)
avr_asm_len
(
"adiw r28,%o0-62"
CR_TAB
"std Y+62,%A1"
CR_TAB
"std Y+63,%B1"
CR_TAB
"sbiw r28,%o0-62"
,
op
,
plen
,
4
)
:
avr_asm_len
(
"subi r28,lo8(-%o0)"
CR_TAB
"sbci r29,hi8(-%o0)"
CR_TAB
"st Y,%A1"
CR_TAB
"std Y+1,%B1"
CR_TAB
"subi r28,lo8(%o0)"
CR_TAB
"sbci r29,hi8(%o0)"
,
op
,
plen
,
6
)
;
}
if
(
reg_base
!=
REG_X
)
return
avr_asm_len
(
"std %A0,%A1"
CR_TAB
"std %B0,%B1"
,
op
,
plen
,
2
)
;
return
reg_src
==
REG_X
avr_asm_len
(
"mov __tmp_reg__,r26"
CR_TAB
"mov __zero_reg__,r27"
CR_TAB
"adiw r26,%o0"
CR_TAB
"st X+,__tmp_reg__"
CR_TAB
"st X,__zero_reg__"
CR_TAB
"clr __zero_reg__"
CR_TAB
"sbiw r26,%o0+1"
,
op
,
plen
,
7
)
:
avr_asm_len
(
"adiw r26,%o0"
CR_TAB
"st X+,%A1"
CR_TAB
"st X,%B1"
CR_TAB
"sbiw r26,%o0+1"
,
op
,
plen
,
4
)
;
}
else
if
(
GET_CODE
(
base
)
==
PRE_DEC
)
{
if
(
!
mem_volatile_p
)
return
avr_asm_len
(
"st %0,%B1"
CR_TAB
"st %0,%A1"
,
op
,
plen
,
2
)
;
return
REGNO
(
XEXP
(
base
,
0
)
)
==
REG_X
avr_asm_len
(
"sbiw r26,2"
CR_TAB
"st X+,%A1"
CR_TAB
"st X,%B1"
CR_TAB
"sbiw r26,1"
,
op
,
plen
,
4
)
:
avr_asm_len
(
"sbiw %r0,2"
CR_TAB
"st %p0,%A1"
CR_TAB
"std %p0+1,%B1"
,
op
,
plen
,
3
)
;
}
else
if
(
GET_CODE
(
base
)
==
POST_INC
)
{
return
avr_asm_len
(
"st %0,%A1"
CR_TAB
"st %0,%B1"
,
op
,
plen
,
2
)
;
}
fatal_insn
(
"unknown move insn:"
,
insn
)
;
return
""
;
}
</s>

Helper for the next function for XMEGA . It does the same but with low byte first .


<s> static rtx find_addr_reg ( rtx addr ) { while ( GET_CODE ( addr ) == PLUS ) { if ( GET_CODE ( XEXP ( addr , 0 ) ) == REG ) addr = XEXP ( addr , 0 ) ; if ( GET_CODE ( XEXP ( addr , 1 ) ) == REG ) addr = XEXP ( addr , 1 ) ; if ( CONSTANT_P ( XEXP ( addr , 0 ) ) ) addr = XEXP ( addr , 1 ) ; if ( CONSTANT_P ( XEXP ( addr , 1 ) ) ) addr = XEXP ( addr , 0 ) ; } if ( GET_CODE ( addr ) == REG ) return addr ; return 0 ; } </s>

Return a REG that occurs in ADDR with coefficient 1 . ADDR can be effectively incremented by incrementing REG . r0 is special and we must not select it as an address register by this routine since our caller will try to increment the returned register via an `` la '' instruction .


"%qE attribute applies only to initialized variables"

Handle a `` selectany '' attribute ; arguments as in struct attribute_spec.handler .


<s> static rtx_insn * set_frame_related_p ( void ) { rtx_insn * seq = get_insns ( ) ; rtx_insn * insn ; end_sequence ( ) ; if ( ! seq ) return NULL ; if ( INSN_P ( seq ) ) { insn = seq ; while ( insn != NULL_RTX ) { RTX_FRAME_RELATED_P ( insn ) = 1 ; insn = NEXT_INSN ( insn ) ; } seq = emit_insn ( seq ) ; } else { seq = emit_insn ( seq ) ; RTX_FRAME_RELATED_P ( seq ) = 1 ; } return seq ; } </s>

Helper function to set RTX_FRAME_RELATED_P on instructions , including sequences .


<s> void StackFixup :: dump ( ) const { print ( dbgs ( ) ) ; } </s>

Dump the plan to stderr ( for debugging ) .


<s> static void expand_block_move_1 ( rtx dst_reg , rtx src_reg , rtx bytes_rtx ) { const rtx sym = gen_rtx_SYMBOL_REF ( Pmode , "__byt_memcpy" ) ; emit_library_call ( sym , LCT_NORMAL , VOIDmode , 3 , dst_reg , Pmode , src_reg , Pmode , convert_to_mode ( TYPE_MODE ( sizetype ) , bytes_rtx , TYPE_UNSIGNED ( sizetype ) ) , TYPE_MODE ( sizetype ) ) ; } </s>

Generate a call to a library function to move BYTES_RTX bytes from address SRC_REG to address DST_REG in 1-byte chunks .


<s> static bool nios2_legitimate_address_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx operand , bool strict_p ) { switch ( GET_CODE ( operand ) ) { case SYMBOL_REF : if ( SYMBOL_REF_TLS_MODEL ( operand ) ) return false ; case CONST : if ( gprel_constant_p ( operand ) || r0rel_constant_p ( operand ) ) return true ; case LABEL_REF : if ( nios2_large_constant_allowed ( ) && nios2_symbolic_constant_p ( operand ) ) return true ; return false ; case CONST_INT : if ( r0rel_constant_p ( operand ) ) return true ; return nios2_large_constant_allowed ( ) ; case CONST_DOUBLE : return false ; case REG : return nios2_regno_ok_for_base_p ( REGNO ( operand ) , strict_p ) ; case PLUS : { rtx op0 = XEXP ( operand , 0 ) ; rtx op1 = XEXP ( operand , 1 ) ; if ( nios2_valid_addr_expr_p ( op0 , op1 , strict_p ) || nios2_valid_addr_expr_p ( op1 , op0 , strict_p ) ) return true ; } break ; case LO_SUM : if ( TARGET_ARCH_R2 && ( TARGET_BYPASS_CACHE || TARGET_BYPASS_CACHE_VOLATILE ) ) return false ; else { rtx op0 = XEXP ( operand , 0 ) ; rtx op1 = XEXP ( operand , 1 ) ; return ( REG_P ( op0 ) && nios2_regno_ok_for_base_p ( REGNO ( op0 ) , strict_p ) && nios2_large_constant_p ( op1 ) ) ; } default : break ; } return false ; } </s>


<s> static bool ix86_broadcast ( HOST_WIDE_INT v , unsigned int width , HOST_WIDE_INT & val_broadcast ) { wide_int val = wi :: uhwi ( v , HOST_BITS_PER_WIDE_INT ) ; val_broadcast = wi :: extract_uhwi ( val , 0 , width ) ; for ( unsigned int i = width ; i < HOST_BITS_PER_WIDE_INT ; i += width ) { HOST_WIDE_INT each = wi :: extract_uhwi ( val , i , width ) ; if ( val_broadcast != each ) return false ; } val_broadcast = sext_hwi ( val_broadcast , width ) ; return true ; } </s>

Return true if V can be broadcasted from an integer of WIDTH bits which is returned in VAL_BROADCAST . Otherwise , return false .


<s>
void
HexagonFrameLowering
::
emitEpilogue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
MachineBasicBlock
::
iterator
MBBI
=
std
::
prev
(
MBB
.
end
(
)
)
;
DebugLoc
dl
=
MBBI
->
getDebugLoc
(
)
;
if
(
hasFP
(
MF
)
||
MF
.
getTarget
(
)
.
getOptLevel
(
)
==
CodeGenOpt
::
)
{
MachineBasicBlock
::
iterator
MBBI
=
std
::
prev
(
MBB
.
end
(
)
)
;
MachineBasicBlock
::
iterator
MBBI_end
=
MBB
.
end
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getTarget
(
)
.
getInstrInfo
(
)
;
if
(
MBBI
->
getOpcode
(
)
==
Hexagon
::
EH_RETURN_JMPR
)
{
assert
(
MBBI
->
getOperand
(
0
)
.
isReg
(
)
&&
"Offset should be in register!"
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Hexagon
::
DEALLOCFRAME
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Hexagon
::
ADD_rr
)
,
Hexagon
::
R29
)
.
addReg
(
Hexagon
::
R29
)
.
addReg
(
Hexagon
::
R28
)
;
return
;
}
if
(
MF
.
getTarget
(
)
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
hasV4TOps
(
)
&&
MBBI
->
getOpcode
(
)
==
Hexagon
::
JMPret
&&
!
DisableDeallocRet
)
{
MachineBasicBlock
::
iterator
BeforeJMPR
=
MBB
.
begin
(
)
==
MBBI
MBBI
:
std
::
prev
(
MBBI
)
;
if
(
BeforeJMPR
!=
MBBI
&&
BeforeJMPR
->
getOpcode
(
)
==
Hexagon
::
RESTORE_DEALLOC_RET_JMP_V4
)
{
MBB
.
erase
(
MBBI
)
;
return
;
}
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MBBI_end
,
dl
,
TII
.
get
(
Hexagon
::
DEALLOC_RET_V4
)
)
;
MIB
->
copyImplicitOps
(
*
MBB
.
getParent
(
)
,
&
*
MBBI
)
;
MBB
.
erase
(
MBBI
)
;
}
else
{
MachineBasicBlock
::
iterator
Term
=
MBB
.
getFirstTerminator
(
)
;
MachineBasicBlock
::
iterator
I
=
Term
==
MBB
.
begin
(
)
MBB
.
end
(
)
:
std
::
prev
(
Term
)
;
if
(
I
!=
MBB
.
end
(
)
&&
I
->
getOpcode
(
)
==
Hexagon
::
RESTORE_DEALLOC_BEFORE_TAILCALL_V4
)
return
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Hexagon
::
DEALLOCFRAME
)
)
;
}
}
}
</s>


<s> static const char * s390_branch_condition_mnemonic ( rtx code , int inv ) { static const char * const mnemonic [ 16 ] = { NULL , "o" , "h" , "nle" , "l" , "nhe" , "lh" , "ne" , "e" , "nlh" , "he" , "nl" , "le" , "nh" , "no" , NULL } ; int mask = s390_branch_condition_mask ( code ) ; gcc_assert ( mask >= 0 ) ; if ( inv ) mask ^= 15 ; gcc_assert ( mask >= 1 && mask <= 14 ) ; return mnemonic [ mask ] ; } </s>

If INV is false , return assembler mnemonic string to implement a branch specified by CODE . If INV is true , return mnemonic for the corresponding inverted branch .


<s> static unsigned long arm_compute_func_type ( void ) { unsigned long type = ARM_FT_UNKNOWN ; tree a ; tree attr ; gcc_assert ( TREE_CODE ( current_function_decl ) == FUNCTION_DECL ) ; if ( optimize > 0 && ( TREE_NOTHROW ( current_function_decl ) || ! ( flag_unwind_tables || ( flag_exceptions && ! USING_SJLJ_EXCEPTIONS ) ) ) && TREE_THIS_VOLATILE ( current_function_decl ) ) type |= ARM_FT_VOLATILE ; if ( cfun -> static_chain_decl != NULL ) type |= ARM_FT_NESTED ; attr = DECL_ATTRIBUTES ( current_function_decl ) ; a = lookup_attribute ( "naked" , attr ) ; if ( a != NULL_TREE ) type |= ARM_FT_NAKED ; a = lookup_attribute ( "isr" , attr ) ; if ( a == NULL_TREE ) a = lookup_attribute ( "interrupt" , attr ) ; if ( a == NULL_TREE ) type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL ; else type |= arm_isr_value ( TREE_VALUE ( a ) ) ; return type ; } </s>

Computes the type of the current function .


<s> bool NVPTXLowerKernelArgs :: runOnFunction ( Function & F ) { if ( ! isKernelFunction ( F ) ) return false ; if ( TM && TM -> getDrvInterface ( ) == NVPTX :: CUDA ) { for ( auto & B : F ) { for ( auto & I : B ) { if ( LoadInst * LI = dyn_cast < LoadInst > ( & I ) ) { if ( LI -> getType ( ) -> isPointerTy ( ) ) { Value * UO = GetUnderlyingObject ( LI -> getPointerOperand ( ) , F . getParent ( ) -> getDataLayout ( ) ) ; if ( Argument * Arg = dyn_cast < Argument > ( UO ) ) { if ( Arg -> hasByValAttr ( ) ) { markPointerAsGlobal ( LI ) ; } } } } } } } for ( Argument & Arg : F . args ( ) ) { if ( Arg . getType ( ) -> isPointerTy ( ) ) { if ( Arg . hasByValAttr ( ) ) handleByValParam ( & Arg ) ; else if ( TM && TM -> getDrvInterface ( ) == NVPTX :: CUDA ) markPointerAsGlobal ( & Arg ) ; } } return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> const LegalizerInfo * RISCVSubtarget :: getLegalizerInfo ( ) const { return Legalizer . get ( ) ; } </s>

Expose LegalizerInfo so the clients can re-use .


<s> static bool alpha_split_complex_arg ( const_tree type ) { return TYPE_MODE ( type ) != TCmode ; } </s>

TCmode complex values are passed by invisible reference . We should not split these values .


<s> SDValue SystemZTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_SystemZ ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) . getValue ( 1 ) ; SDValue RetValue = Chain . getValue ( 0 ) ; InFlag = Chain . getValue ( 2 ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) RetValue = DAG . getNode ( ISD :: AssertSext , dl , VA . getLocVT ( ) , RetValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) RetValue = DAG . getNode ( ISD :: AssertZext , dl , VA . getLocVT ( ) , RetValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) RetValue = DAG . getNode ( ISD :: TRUNCATE , dl , VA . getValVT ( ) , RetValue ) ; InVals . push_back ( RetValue ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> void xstormy16_initialize_trampoline ( rtx addr , rtx fnaddr , rtx static_chain ) { rtx reg_addr = gen_reg_rtx ( Pmode ) ; rtx temp = gen_reg_rtx ( HImode ) ; rtx reg_fnaddr = gen_reg_rtx ( HImode ) ; rtx reg_addr_mem ; reg_addr_mem = gen_rtx_MEM ( HImode , reg_addr ) ; emit_move_insn ( reg_addr , addr ) ; emit_move_insn ( temp , GEN_INT ( 0x3130 | STATIC_CHAIN_REGNUM ) ) ; emit_move_insn ( reg_addr_mem , temp ) ; emit_insn ( gen_addhi3 ( reg_addr , reg_addr , const2_rtx ) ) ; emit_move_insn ( temp , static_chain ) ; emit_move_insn ( reg_addr_mem , temp ) ; emit_insn ( gen_addhi3 ( reg_addr , reg_addr , const2_rtx ) ) ; emit_move_insn ( reg_fnaddr , fnaddr ) ; emit_move_insn ( temp , reg_fnaddr ) ; emit_insn ( gen_andhi3 ( temp , temp , GEN_INT ( 0xFF ) ) ) ; emit_insn ( gen_iorhi3 ( temp , temp , GEN_INT ( 0x0200 ) ) ) ; emit_move_insn ( reg_addr_mem , temp ) ; emit_insn ( gen_addhi3 ( reg_addr , reg_addr , const2_rtx ) ) ; emit_insn ( gen_lshrhi3 ( reg_fnaddr , reg_fnaddr , GEN_INT ( 8 ) ) ) ; emit_move_insn ( reg_addr_mem , reg_fnaddr ) ; } </s>

Initialize the variable parts of a trampoline . ADDR is an RTX for the address of the trampoline ; FNADDR is an RTX for the address of the nested function ; STATIC_CHAIN is an RTX for the static chain value that should be passed to the function when it is called .


<s> bool FalkorMarkStridedAccesses :: run ( ) { bool MadeChange = false ; for ( Loop * I : LI ) for ( auto L = df_begin ( I ) , LE = df_end ( I ) ; L != LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ; return MadeChange ; } </s>

Run the analysis pass over a function and produce a dominator tree .


"insertBranch must not be told to insert a fallthrough"

Insert branch code into the end of the specified MachineBasicBlock .


<s> static void do_load_mask_compare ( const machine_mode load_mode , rtx diff , rtx cmp_rem , rtx dcond , rtx src1_addr , rtx src2_addr , rtx orig_src1 , rtx orig_src2 ) { HOST_WIDE_INT load_mode_size = GET_MODE_SIZE ( load_mode ) ; rtx shift_amount = gen_reg_rtx ( word_mode ) ; rtx d1 = gen_reg_rtx ( word_mode ) ; rtx d2 = gen_reg_rtx ( word_mode ) ; do_load_for_compare_from_addr ( load_mode , d1 , src1_addr , orig_src1 ) ; do_load_for_compare_from_addr ( load_mode , d2 , src2_addr , orig_src2 ) ; do_sub3 ( shift_amount , GEN_INT ( load_mode_size ) , cmp_rem ) ; if ( word_mode == DImode ) { emit_insn ( gen_ashldi3 ( shift_amount , shift_amount , GEN_INT ( LOG2_BITS_PER_UNIT ) ) ) ; emit_insn ( gen_lshrdi3 ( d1 , d1 , gen_lowpart ( SImode , shift_amount ) ) ) ; emit_insn ( gen_lshrdi3 ( d2 , d2 , gen_lowpart ( SImode , shift_amount ) ) ) ; } else { emit_insn ( gen_ashlsi3 ( shift_amount , shift_amount , GEN_INT ( LOG2_BITS_PER_UNIT ) ) ) ; emit_insn ( gen_lshrsi3 ( d1 , d1 , shift_amount ) ) ; emit_insn ( gen_lshrsi3 ( d2 , d2 , shift_amount ) ) ; } if ( TARGET_P9_MISC ) { rtx cmp = gen_rtx_COMPARE ( CCUNSmode , d1 , d2 ) ; emit_insn ( gen_rtx_SET ( dcond , cmp ) ) ; } else { if ( word_mode == DImode ) emit_insn ( gen_subfdi3_carry ( diff , d2 , d1 ) ) ; else emit_insn ( gen_subfsi3_carry ( diff , d2 , d1 ) ) ; } } </s>

Generate rtl for a load , shift , and compare of less than a full word . LOAD_MODE is the machine mode for the loads . DIFF is the reg for the difference . CMP_REM is the reg containing the remaining bytes to compare . DCOND is the CCUNS reg for the compare if we are doing P9 code with setb . SRC1_ADDR is the first source address . SRC2_ADDR is the second source address . ORIG_SRC1 is the original first source block 's address rtx . ORIG_SRC2 is the original second source block 's address rtx .


<s> bool SIPeepholeSDWA :: runOnMachineFunction ( MachineFunction & MF ) { const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; if ( ! ST . hasSDWA ( ) || skipFunction ( MF . getFunction ( ) ) ) return false ; MRI = & MF . getRegInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; TII = ST . getInstrInfo ( ) ; bool Changed = false ; bool Ret = false ; do { matchSDWAOperands ( MF ) ; for ( const auto & OperandPair : SDWAOperands ) { const auto & Operand = OperandPair . second ; MachineInstr * PotentialMI = Operand -> potentialToConvert ( TII ) ; if ( PotentialMI && isConvertibleToSDWA ( * PotentialMI , ST ) ) { PotentialMatches [ PotentialMI ] . push_back ( Operand . get ( ) ) ; } } for ( auto & PotentialPair : PotentialMatches ) { MachineInstr & PotentialMI = * PotentialPair . first ; convertToSDWA ( PotentialMI , PotentialPair . second ) ; } PotentialMatches . clear ( ) ; SDWAOperands . clear ( ) ; Changed = ! ConvertedInstructions . empty ( ) ; if ( Changed ) Ret = true ; while ( ! ConvertedInstructions . empty ( ) ) legalizeScalarOperands ( * ConvertedInstructions . pop_back_val ( ) , ST ) ; } while ( Changed ) ; return Ret ; } </s>

runOnMachineFunction - Emit the function body .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineModuleInfo > ( ) ; AU . setPreservesAll ( ) ; MachineModulePass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void PPCPreRASchedStrategy :: tryCandidate ( SchedCandidate & Cand , SchedCandidate & TryCand , SchedBoundary * Zone ) const { GenericScheduler :: tryCandidate ( Cand , TryCand , Zone ) ; if ( ! Cand . isValid ( ) || ! Zone ) return ; if ( TryCand . Reason != NodeOrder && TryCand . Reason != NoCand ) return ; if ( biasAddiLoadCandidate ( Cand , TryCand , * Zone ) ) return ; } </s>

Apply a set of heuristics to a new candidate .


<s> void avr_cpu_cpp_builtins ( struct cpp_reader * pfile ) { int i ; builtin_define_std ( "AVR" ) ; if ( avr_arch -> macro ) cpp_define_formatted ( pfile , "__AVR_ARCH__=%s" , avr_arch -> macro ) ; if ( AVR_HAVE_RAMPD ) cpp_define ( pfile , "__AVR_HAVE_RAMPD__" ) ; if ( AVR_HAVE_RAMPX ) cpp_define ( pfile , "__AVR_HAVE_RAMPX__" ) ; if ( AVR_HAVE_RAMPY ) cpp_define ( pfile , "__AVR_HAVE_RAMPY__" ) ; if ( AVR_HAVE_RAMPZ ) cpp_define ( pfile , "__AVR_HAVE_RAMPZ__" ) ; if ( AVR_HAVE_ELPM ) cpp_define ( pfile , "__AVR_HAVE_ELPM__" ) ; if ( AVR_HAVE_ELPMX ) cpp_define ( pfile , "__AVR_HAVE_ELPMX__" ) ; if ( AVR_HAVE_MOVW ) cpp_define ( pfile , "__AVR_HAVE_MOVW__" ) ; if ( AVR_HAVE_LPMX ) cpp_define ( pfile , "__AVR_HAVE_LPMX__" ) ; if ( avr_arch -> asm_only ) cpp_define ( pfile , "__AVR_ASM_ONLY__" ) ; if ( AVR_HAVE_MUL ) { cpp_define ( pfile , "__AVR_ENHANCED__" ) ; cpp_define ( pfile , "__AVR_HAVE_MUL__" ) ; } if ( avr_arch -> have_jmp_call ) { cpp_define ( pfile , "__AVR_MEGA__" ) ; cpp_define ( pfile , "__AVR_HAVE_JMP_CALL__" ) ; } if ( AVR_XMEGA ) cpp_define ( pfile , "__AVR_XMEGA__" ) ; if ( AVR_TINY ) { cpp_define ( pfile , "__AVR_TINY__" ) ; cpp_define ( pfile , "__AVR_TINY_PM_BASE_ADDRESS__=0x4000" ) ; } if ( AVR_HAVE_EIJMP_EICALL ) { cpp_define ( pfile , "__AVR_HAVE_EIJMP_EICALL__" ) ; cpp_define ( pfile , "__AVR_3_BYTE_PC__" ) ; } else { cpp_define ( pfile , "__AVR_2_BYTE_PC__" ) ; } if ( AVR_HAVE_8BIT_SP ) cpp_define ( pfile , "__AVR_HAVE_8BIT_SP__" ) ; else cpp_define ( pfile , "__AVR_HAVE_16BIT_SP__" ) ; if ( AVR_HAVE_SPH ) cpp_define ( pfile , "__AVR_HAVE_SPH__" ) ; else cpp_define ( pfile , "__AVR_SP8__" ) ; if ( TARGET_NO_INTERRUPTS ) cpp_define ( pfile , "__NO_INTERRUPTS__" ) ; if ( TARGET_SKIP_BUG ) { cpp_define ( pfile , "__AVR_ERRATA_SKIP__" ) ; if ( AVR_HAVE_JMP_CALL ) cpp_define ( pfile , "__AVR_ERRATA_SKIP_JMP_CALL__" ) ; } if ( TARGET_RMW ) cpp_define ( pfile , "__AVR_ISA_RMW__" ) ; cpp_define_formatted ( pfile , "__AVR_SFR_OFFSET__=0x%x" , avr_arch -> sfr_offset ) ; cpp_define ( pfile , "__WITH_AVRLIBC__" ) ; if ( lang_GNU_C ( ) ) { for ( i = 0 ; i < ADDR_SPACE_COUNT ; i ++ ) if ( ! ADDR_SPACE_GENERIC_P ( i ) && avr_addrspace [ i ] . segment < avr_n_flash && ( AVR_HAVE_LPM || avr_addrspace [ i ] . pointer_size <= 2 ) ) { const char * name = avr_addrspace [ i ] . name ; char * Name = ( char * ) alloca ( 1 + strlen ( name ) ) ; cpp_define ( pfile , avr_toupper ( Name , name ) ) ; } } cpp_define ( pfile , "__BUILTIN_AVR_" # NAME ) ; cpp_define_formatted ( pfile , "__INT24_MAX__=8388607%s" , INT_TYPE_SIZE == 8 ? "LL" : "L" ) ; cpp_define ( pfile , "__INT24_MIN__=(-__INT24_MAX__-1)" ) ; cpp_define_formatted ( pfile , "__UINT24_MAX__=16777215%s" , INT_TYPE_SIZE == 8 ? "ULL" : "UL" ) ; } </s>

Worker function for TARGET_CPU_CPP_BUILTINS .


<s> void TGSICFGStructurizer :: removeSuccessor ( MachineBasicBlock * MBB ) { while ( MBB -> succ_size ( ) ) MBB -> removeSuccessor ( * MBB -> succ_begin ( ) ) ; } </s>

Remove specified successor from the successors list of this MachineBasicBlock .


<s> static poly_uint16 riscv_convert_vector_bits ( void ) { if ( TARGET_MIN_VLEN > 32 ) { riscv_bytes_per_vector_chunk = 8 ; } else { riscv_bytes_per_vector_chunk = 4 ; } return TARGET_VECTOR ? poly_uint16 ( 1 , 1 ) : 1 ; } </s>

Return the VLEN value associated with -march . TODO : So far we only support length-agnostic value .


<s> void MipsTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; this -> TM = & static_cast < const MipsTargetMachine & > ( TM ) ; } </s>

This method must be called before any actual lowering is done .


<s> bool NVPTXAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; O << '[' ; printMemOperand ( MI , OpNo , O ) ; O << ']' ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> void GCNPassConfig :: addPostRegAlloc ( ) { addPass ( createSIPrepareScratchRegs ( ) , false ) ; addPass ( createSIShrinkInstructionsPass ( ) , false ) ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> Register MipsFunctionInfo :: getGlobalBaseReg ( MachineFunction & MF ) { if ( ! GlobalBaseReg ) GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( & getGlobalBaseRegClass ( MF ) ) ; return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s>
void
Thumb2HazardRecognizer
::
EmitInstruction
(
SUnit
*
SU
)
{
MachineInstr
*
MI
=
SU
->
getInstr
(
)
;
unsigned
Opcode
=
MI
->
getOpcode
(
)
;
if
(
ITBlockSize
)
{
ITBlockSize
;
}
else
if
(
Opcode
==
ARM
::
t2IT
)
{
unsigned
Mask
=
MI
->
getOperand
(
1
)
.
getImm
(
)
;
unsigned
NumTZ
=
CountTrailingZeros_32
(
Mask
)
;
assert
(
NumTZ
<=
3
&&
"Invalid IT mask!"
)
;
ITBlockSize
=
4
NumTZ
;
MachineBasicBlock
::
iterator
I
=
MI
;
for
(
unsigned
i
=
0
;
i
<
ITBlockSize
;
++
i
)
{
do
{
++
I
;
}
while
(
I
->
isDebugValue
(
)
)
;
ITBlockMIs
[
ITBlockSize
1
i
]
=
&
*
I
;
}
}
PostRAHazardRecognizer
::
EmitInstruction
(
SU
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool M680x0PassConfig :: addInstSelector ( ) { addPass ( createM680x0ISelDag ( getM680x0TargetMachine ( ) ) ) ; addPass ( createM680x0GlobalBaseRegPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static int arc_attr_type ( rtx_insn * insn ) { if ( NONJUMP_INSN_P ( insn ) ? ( GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) : JUMP_P ( insn ) ? ( GET_CODE ( PATTERN ( insn ) ) == ADDR_VEC || GET_CODE ( PATTERN ( insn ) ) == ADDR_DIFF_VEC ) : ! CALL_P ( insn ) ) return - 1 ; return get_attr_type ( insn ) ; } </s>

Return the integer value of the `` type '' attribute for INSN , or -1 if INSN ca n't have attributes .


<s> std :: pair < unsigned , const TargetRegisterClass * > RISCVTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'd' : case 'r' : if ( Subtarget . isRV64 ( ) ) return std :: make_pair ( 0U , & RISCV :: GR64BitRegClass ) ; return std :: make_pair ( 0U , & RISCV :: GR32BitRegClass ) ; case 'f' : if ( Subtarget . hasD ( ) ) return std :: make_pair ( 0U , & RISCV :: FP64BitRegClass ) ; else if ( Subtarget . hasF ( ) ) return std :: make_pair ( 0U , & RISCV :: FP32BitRegClass ) ; else if ( Subtarget . isRV64 ( ) ) return std :: make_pair ( 0U , & RISCV :: GR64BitRegClass ) ; return std :: make_pair ( 0U , & RISCV :: GR32BitRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


"frame pointer should not have been eliminated"


<s>
void
SIMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
uint64_t
Encoding
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
unsigned
bytes
=
Desc
.
getSize
(
)
;
for
(
unsigned
i
=
0
;
i
<
bytes
;
i
++
)
{
OS
.
write
(
(
uint8_t
)
(
(
Encoding
>>
(
8
*
i
)
)
&
0xff
)
)
;
}
if
(
bytes
>
4
)
return
;
for
(
unsigned
i
=
0
,
e
=
MI
.
getNumOperands
(
)
;
i
<
e
;
++
i
)
{
if
(
!
isSrcOperand
(
Desc
,
i
)
)
continue
;
int
RCID
=
Desc
.
OpInfo
[
i
]
.
RegClass
;
const
MCRegisterClass
&
RC
=
MRI
.
getRegClass
(
RCID
)
;
const
MCOperand
&
Op
=
MI
.
getOperand
(
i
)
;
if
(
getLitEncoding
(
Op
,
RC
.
getSize
(
)
)
!=
255
)
continue
;
int64_t
Imm
=
0
;
if
(
Op
.
isImm
(
)
)
Imm
=
Op
.
getImm
(
)
;
else
if
(
Op
.
isExpr
(
)
)
{
if
(
const
MCConstantExpr
*
C
=
dyn_cast
<
MCConstantExpr
>
(
Op
.
getExpr
(
)
)
)
Imm
=
C
->
getValue
(
)
;
}
else
if
(
!
Op
.
isExpr
(
)
)
llvm_unreachable
(
"Must be immediate or expr"
)
;
for
(
unsigned
j
=
0
;
j
<
4
;
j
++
)
{
OS
.
write
(
(
uint8_t
)
(
(
Imm
>>
(
8
*
j
)
)
&
0xff
)
)
;
}
break
;
}
}
</s>

Encode the given Inst to bytes and append to CB .


<s> bool ix86_gpr_tls_address_pattern_p ( rtx mem ) { gcc_assert ( MEM_P ( mem ) ) ; rtx addr = XEXP ( mem , 0 ) ; subrtx_var_iterator :: array_type array ; FOR_EACH_SUBRTX_VAR ( iter , array , addr , ALL ) { rtx op = * iter ; if ( GET_CODE ( op ) == UNSPEC ) switch ( XINT ( op , 1 ) ) { case UNSPEC_GOTNTPOFF : return true ; case UNSPEC_TPOFF : if ( ! TARGET_64BIT ) return true ; break ; default : break ; } } return false ; } </s>

Return true if the TLS address requires insn using integer registers . It 's used to prevent KMOV/VMOV in TLS code sequences which require integer MOV instructions , refer to PR103275 .


<s> void PPCRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( GuaranteedTailCallOpt && I -> getOpcode ( ) == PPC :: ADJCALLSTACKUP ) { if ( int CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { bool is64Bit = Subtarget . isPPC64 ( ) ; CalleeAmt *= - 1 ; unsigned StackReg = is64Bit ? PPC :: X1 : PPC :: R1 ; unsigned TmpReg = is64Bit ? PPC :: X0 : PPC :: R0 ; unsigned ADDIInstr = is64Bit ? PPC :: ADDI8 : PPC :: ADDI ; unsigned ADDInstr = is64Bit ? PPC :: ADD8 : PPC :: ADD4 ; unsigned LISInstr = is64Bit ? PPC :: LIS8 : PPC :: LIS ; unsigned ORIInstr = is64Bit ? PPC :: ORI8 : PPC :: ORI ; MachineInstr * MI = I ; DebugLoc dl = MI -> getDebugLoc ( ) ; if ( isInt < 16 > ( CalleeAmt ) ) { BuildMI ( MBB , I , dl , TII . get ( ADDIInstr ) , StackReg ) . addReg ( StackReg ) . addImm ( CalleeAmt ) ; } else { MachineBasicBlock :: iterator MBBI = I ; BuildMI ( MBB , MBBI , dl , TII . get ( LISInstr ) , TmpReg ) . addImm ( CalleeAmt >> 16 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ORIInstr ) , TmpReg ) . addReg ( TmpReg , RegState :: Kill ) . addImm ( CalleeAmt & 0xFFFF ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ADDInstr ) ) . addReg ( StackReg ) . addReg ( StackReg ) . addReg ( TmpReg ) ; } } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> const TargetRegisterClass * X86RegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { if ( RC == & X86 :: GR8_NOREXRegClass ) return RC ; const X86Subtarget & Subtarget = MF . getSubtarget < X86Subtarget > ( ) ; const TargetRegisterClass * Super = RC ; TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case X86 :: FR32RegClassID : case X86 :: FR64RegClassID : if ( ! Subtarget . hasAVX512 ( ) && getRegSizeInBits ( * Super ) == getRegSizeInBits ( * RC ) ) return Super ; break ; case X86 :: VR128RegClassID : case X86 :: VR256RegClassID : if ( ! Subtarget . hasVLX ( ) && getRegSizeInBits ( * Super ) == getRegSizeInBits ( * RC ) ) return Super ; break ; case X86 :: VR128XRegClassID : case X86 :: VR256XRegClassID : if ( Subtarget . hasVLX ( ) && getRegSizeInBits ( * Super ) == getRegSizeInBits ( * RC ) ) return Super ; break ; case X86 :: FR32XRegClassID : case X86 :: FR64XRegClassID : if ( Subtarget . hasAVX512 ( ) && getRegSizeInBits ( * Super ) == getRegSizeInBits ( * RC ) ) return Super ; break ; case X86 :: GR8RegClassID : case X86 :: GR16RegClassID : case X86 :: GR32RegClassID : case X86 :: GR64RegClassID : case X86 :: RFP32RegClassID : case X86 :: RFP64RegClassID : case X86 :: RFP80RegClassID : case X86 :: VR512RegClassID : if ( getRegSizeInBits ( * Super ) == getRegSizeInBits ( * RC ) ) return Super ; } Super = * I ++ ; } while ( Super ) ; return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .


"%qs attribute only applies to functions"

"fastcall and regparm attributes are not compatible"

"%qs attribute requires an integer constant argument"

"argument to %qs attribute larger than %d"

"fastcall and cdecl attributes are not compatible"

"fastcall and stdcall attributes are not compatible"

"stdcall and cdecl attributes are not compatible"

"stdcall and fastcall attributes are not compatible"

Handle `` cdecl '' , `` stdcall '' , `` fastcall '' , `` regparm '' and `` sseregparm '' calling convention attributes ; arguments as in struct attribute_spec.handler .


<s> void split_double_mode ( machine_mode mode , rtx operands [ ] , int num , rtx lo_half [ ] , rtx hi_half [ ] ) { machine_mode half_mode ; unsigned int byte ; rtx mem_op = NULL_RTX ; int mem_num = 0 ; switch ( mode ) { case E_TImode : half_mode = DImode ; break ; case E_DImode : half_mode = SImode ; break ; case E_P2HImode : half_mode = HImode ; break ; case E_P2QImode : half_mode = QImode ; break ; default : gcc_unreachable ( ) ; } byte = GET_MODE_SIZE ( half_mode ) ; while ( num -- ) { rtx op = operands [ num ] ; if ( MEM_P ( op ) ) { if ( mem_op && rtx_equal_p ( op , mem_op ) ) { lo_half [ num ] = lo_half [ mem_num ] ; hi_half [ num ] = hi_half [ mem_num ] ; } else { mem_op = op ; mem_num = num ; lo_half [ num ] = adjust_address ( op , half_mode , 0 ) ; hi_half [ num ] = adjust_address ( op , half_mode , byte ) ; } } else { lo_half [ num ] = simplify_gen_subreg ( half_mode , op , GET_MODE ( op ) == VOIDmode ? mode : GET_MODE ( op ) , 0 ) ; hi_half [ num ] = simplify_gen_subreg ( half_mode , op , GET_MODE ( op ) == VOIDmode ? mode : GET_MODE ( op ) , byte ) ; } } } </s>

Split one or more double-mode RTL references into pairs of half-mode references . The RTL can be REG , offsettable MEM , integer constant , or CONST_DOUBLE . `` operands '' is a pointer to an array of double-mode RTLs to split and `` num '' is its length . lo_half and hi_half are output arrays that parallel `` operands '' .


<s> bool isToken ( ) const override { return is ( k_Token ) ; } </s>


"\t>> Failed to rename destination in insn %d\n\t>>"

The actual reallocation logic . For each vector of collisions V , try to resolve the collision by attempting to rename the destination register of all but one of the loads . This is a callback that is invoked for each name-value pair ( T , V ) in TAG_MAP . The function returns true whenever it returns unchanged and false otherwise to halt traversal .


<s> virtual bool doInitialization ( Module & M ) { return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> static int mips_sched_reassociation_width ( unsigned int opc ATTRIBUTE_UNUSED , machine_mode mode ) { if ( MSA_SUPPORTED_MODE_P ( mode ) ) return 2 ; return 1 ; } </s>


<s> bool MipsPassConfig :: addPreEmitPass ( ) { MipsTargetMachine & TM = getMipsTargetMachine ( ) ; const MipsSubtarget & Subtarget = TM . getSubtarget < MipsSubtarget > ( ) ; addPass ( createMipsDelaySlotFillerPass ( TM ) ) ; if ( Subtarget . enableLongBranchPass ( ) ) addPass ( createMipsLongBranchPass ( TM ) ) ; if ( Subtarget . inMips16Mode ( ) || Subtarget . allowMixed16_32 ( ) ) addPass ( createMipsConstantIslandPass ( TM ) ) ; if ( getMipsSubtarget ( ) . isTargetNaCl ( ) ) { addPass ( createMipsNaClRewritePass ( ) ) ; } return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips


<s> void aarch64_split_simd_combine ( rtx dst , rtx src1 , rtx src2 ) { machine_mode src_mode = GET_MODE ( src1 ) ; machine_mode dst_mode = GET_MODE ( dst ) ; gcc_assert ( VECTOR_MODE_P ( dst_mode ) ) ; gcc_assert ( register_operand ( dst , dst_mode ) && register_operand ( src1 , src_mode ) && register_operand ( src2 , src_mode ) ) ; rtx ( * gen ) ( rtx , rtx , rtx ) ; switch ( src_mode ) { case E_V8QImode : gen = gen_aarch64_simd_combinev8qi ; break ; case E_V4HImode : gen = gen_aarch64_simd_combinev4hi ; break ; case E_V2SImode : gen = gen_aarch64_simd_combinev2si ; break ; case E_V4HFmode : gen = gen_aarch64_simd_combinev4hf ; break ; case E_V2SFmode : gen = gen_aarch64_simd_combinev2sf ; break ; case E_DImode : gen = gen_aarch64_simd_combinedi ; break ; case E_DFmode : gen = gen_aarch64_simd_combinedf ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( dst , src1 , src2 ) ) ; return ; } </s>


<s> static bool s390_pass_by_reference ( cumulative_args_t ca ATTRIBUTE_UNUSED , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { int size = s390_function_arg_size ( mode , type ) ; if ( size > 8 ) return true ; if ( type ) { if ( AGGREGATE_TYPE_P ( type ) && exact_log2 ( size ) < 0 ) return 1 ; if ( TREE_CODE ( type ) == COMPLEX_TYPE || TREE_CODE ( type ) == VECTOR_TYPE ) return 1 ; } return 0 ; } </s>

Return 1 if a function argument of type TYPE and mode MODE is to be passed by reference . The ABI specifies that only structures of size 1 , 2 , 4 , or 8 bytes are passed by value , all other structures ( and complex numbers ) are passed by reference .


<s> static void push_minipool_barrier ( rtx_insn * insn , HOST_WIDE_INT address ) { Mfix * fix = ( Mfix * ) obstack_alloc ( & minipool_obstack , sizeof ( * fix ) ) ; fix -> insn = insn ; fix -> address = address ; fix -> next = NULL ; if ( minipool_fix_head != NULL ) minipool_fix_tail -> next = fix ; else minipool_fix_head = fix ; minipool_fix_tail = fix ; } </s>

Record that there is a natural barrier in the insn stream at ADDRESS .


<s> const MCS51RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
bool
AVRFrameLowering
::
restoreCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
if
(
CSI
.
empty
(
)
)
{
return
false
;
}
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
AVRSubtarget
&
STI
=
MF
.
getSubtarget
<
AVRSubtarget
>
(
)
;
const
TargetInstrInfo
&
TII
=
*
STI
.
getInstrInfo
(
)
;
for
(
const
CalleeSavedInfo
&
CCSI
:
CSI
)
{
unsigned
Reg
=
CCSI
.
getReg
(
)
;
assert
(
TRI
->
getMinimalPhysRegClass
(
Reg
)
->
getSize
(
)
==
1
&&
"Invalid register size"
)
;
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
POPRd
)
,
Reg
)
;
}
return
true
;
}
</s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .

AVR
AVR
AVR
AVR
1
"Invalid register size"
AVR::POPRd


<s> void SITargetLowering :: finalizeLowering ( MachineFunction & MF ) const { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; SIMachineFunctionInfo * Info = MF . getInfo < SIMachineFunctionInfo > ( ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const SIRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; if ( Info -> isEntryFunction ( ) ) { reservePrivateMemoryRegs ( getTargetMachine ( ) , MF , * TRI , * Info ) ; } assert ( ! TRI -> isSubRegister ( Info -> getScratchRSrcReg ( ) , Info -> getStackPtrOffsetReg ( ) ) ) ; if ( Info -> getStackPtrOffsetReg ( ) != AMDGPU :: SP_REG ) MRI . replaceRegWith ( AMDGPU :: SP_REG , Info -> getStackPtrOffsetReg ( ) ) ; if ( Info -> getScratchRSrcReg ( ) != AMDGPU :: PRIVATE_RSRC_REG ) MRI . replaceRegWith ( AMDGPU :: PRIVATE_RSRC_REG , Info -> getScratchRSrcReg ( ) ) ; if ( Info -> getFrameOffsetReg ( ) != AMDGPU :: FP_REG ) MRI . replaceRegWith ( AMDGPU :: FP_REG , Info -> getFrameOffsetReg ( ) ) ; if ( Info -> getScratchWaveOffsetReg ( ) != AMDGPU :: SCRATCH_WAVE_OFFSET_REG ) { MRI . replaceRegWith ( AMDGPU :: SCRATCH_WAVE_OFFSET_REG , Info -> getScratchWaveOffsetReg ( ) ) ; } Info -> limitOccupancy ( MF ) ; if ( ST . isWave32 ( ) && ! MF . empty ( ) ) { const SIInstrInfo * TII = ST . getInstrInfo ( ) ; DebugLoc DL ; MachineBasicBlock & MBB = MF . front ( ) ; MachineBasicBlock :: iterator I = MBB . getFirstNonDebugInstr ( ) ; BuildMI ( MBB , I , DL , TII -> get ( TargetOpcode :: IMPLICIT_DEF ) , AMDGPU :: VCC_HI ) ; for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { TII -> fixImplicitOperands ( MI ) ; } } } TargetLoweringBase :: finalizeLowering ( MF ) ; } </s>

Execute target specific actions to finalize target lowering .


<s> void pdp10_init_builtins ( ) { builtin_function ( "__builtin_fsc" , FUNTYPE2 ( FLOAT , FLOAT , INT ) , PDP10_BUILTIN_FSC , BUILT_IN_MD , 0 ) ; builtin_function ( "__builtin_dfsc" , FUNTYPE2 ( DOUBLE , DOUBLE , INT ) , PDP10_BUILTIN_DFSC , BUILT_IN_MD , 0 ) ; if ( HAVE_JFFO ) { builtin_function ( "__builtin_jffo" , FUNTYPE2 ( VOID , LONGLONG , VOIDP ) , PDP10_BUILTIN_JFFO , BUILT_IN_MD , 0 ) ; } } </s>

Called by the MD_INIT_BUILTINS macro . Performs the necessary setup for machine-specific builtin functions .


<s> void XCoreFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; XCoreFunctionInfo * XFI = MF . getInfo < XCoreFunctionInfo > ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool LRUsed = MRI . isPhysRegModified ( XCore :: LR ) ; if ( ! LRUsed && ! MF . getFunction ( ) -> isVarArg ( ) && MF . getFrameInfo ( ) -> estimateStackSize ( MF ) ) LRUsed = true ; if ( MF . getMMI ( ) . callsUnwindInit ( ) || MF . getMMI ( ) . callsEHReturn ( ) ) { XFI -> createEHSpillSlot ( MF ) ; LRUsed = true ; } if ( LRUsed ) { SavedRegs . reset ( XCore :: LR ) ; XFI -> createLRSpillSlot ( MF ) ; } if ( hasFP ( MF ) ) XFI -> createFPSpillSlot ( MF ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .

XCore XCore XCore XCore XCore::LR XCore::LR


<s>
void
SICFrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
SICFunctionInfo
*
SICFI
=
MF
.
getInfo
<
SICFunctionInfo
>
(
)
;
const
SICInstrInfo
&
TII
=
*
static_cast
<
const
SICInstrInfo
*
>
(
STI
.
getInstrInfo
(
)
)
;
const
SICRegisterInfo
&
RegInfo
=
*
static_cast
<
const
SICRegisterInfo
*
>
(
STI
.
getRegisterInfo
(
)
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
dl
=
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
SICABIInfo
ABI
=
STI
.
getABI
(
)
;
unsigned
SP
=
SIC
::
X
;
const
TargetRegisterClass
*
RC
=
&
SIC
::
GPROutRegClass
;
uint64_t
StackSize
=
MFI
->
getStackSize
(
)
;
if
(
StackSize
==
0
&&
!
MFI
->
adjustsStack
(
)
)
return
;
MachineModuleInfo
&
MMI
=
MF
.
getMMI
(
)
;
const
MCRegisterInfo
*
MRI
=
MMI
.
getContext
(
)
.
getRegisterInfo
(
)
;
MachineLocation
DstML
,
SrcML
;
TII
.
adjustStackPtr
(
SP
,
StackSize
,
MBB
,
MBBI
)
;
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

SIC
SIC
"Shrink-wrapping not yet supported"
SIC
SIC
SIC
SIC
SIC
SIC
SIC
SIC
SIC::X
SIC::GPROutRegClass
0


<s> TargetLowering :: ConstraintType AAPTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'r' : return C_RegisterClass ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> static int ia64_adjust_cost_2 ( rtx_insn * insn , int dep_type1 , rtx_insn * dep_insn , int cost , dw_t dw ) { enum reg_note dep_type = ( enum reg_note ) dep_type1 ; enum attr_itanium_class dep_class ; enum attr_itanium_class insn_class ; insn_class = ia64_safe_itanium_class ( insn ) ; dep_class = ia64_safe_itanium_class ( dep_insn ) ; if ( dep_type == REG_DEP_TRUE && ( dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF ) && ( insn_class == ITANIUM_CLASS_BR || insn_class == ITANIUM_CLASS_SCALL ) ) return 0 ; if ( dw == MIN_DEP_WEAK ) return PARAM_VALUE ( PARAM_SCHED_MEM_TRUE_DEP_COST ) ; else if ( dw > MIN_DEP_WEAK ) { if ( mflag_sched_fp_mem_deps_zero_cost && dep_class == ITANIUM_CLASS_STF ) return 0 ; else return cost ; } if ( dep_type != REG_DEP_OUTPUT ) return cost ; if ( dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF || insn_class == ITANIUM_CLASS_ST || insn_class == ITANIUM_CLASS_STF ) return 0 ; return cost ; } </s>

Adjust the cost of a scheduling dependency . Return the new cost of a dependency of type DEP_TYPE or INSN on DEP_INSN . COST is the current cost , DW is dependency weakness .


<s>
bool
ARMLowOverheadLoops
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
const
ARMSubtarget
&
ST
=
mf
.
getSubtarget
<
ARMSubtarget
>
(
)
;
if
(
!
ST
.
hasLOB
(
)
)
return
false
;
MF
=
&
mf
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM Loops on "
<<
MF
->
getName
(
)
<<
" ------------- \n"
)
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
RDA
=
&
getAnalysis
<
ReachingDefAnalysis
>
(
)
;
MF
->
getProperties
(
)
.
set
(
MachineFunctionProperties
::
Property
::
TracksLiveness
)
;
MRI
=
&
MF
->
getRegInfo
(
)
;
TII
=
static_cast
<
const
ARMBaseInstrInfo
*
>
(
ST
.
getInstrInfo
(
)
)
;
TRI
=
ST
.
getRegisterInfo
(
)
;
BBUtils
=
std
::
unique_ptr
<
ARMBasicBlockUtils
>
(
new
ARMBasicBlockUtils
(
*
MF
)
)
;
BBUtils
->
computeAllBlockSizes
(
)
;
BBUtils
->
adjustBBOffsetsAfter
(
&
MF
->
front
(
)
)
;
bool
Changed
=
false
;
for
(
auto
ML
:
*
MLI
)
{
if
(
ML
->
isOutermost
(
)
)
Changed
|=
ProcessLoop
(
ML
)
;
}
Changed
|=
RevertNonLoops
(
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

ARM
ARM
ARM
ARM
"ARM Loops on "
" ------------- \n"
ARM
ARM
ARM


"Should never see frame index on non-address operand"

Get the offset from the referenced frame index in the instruction , if there is one .


<s>
bool
VLIWResourceModel
::
reserveResources
(
SUnit
*
SU
,
bool
IsTop
)
{
bool
startNewCycle
=
false
;
if
(
!
SU
)
{
ResourcesModel
->
clearResources
(
)
;
Packet
.
clear
(
)
;
TotalPackets
++
;
return
false
;
}
if
(
!
isResourceAvailable
(
SU
,
IsTop
)
||
Packet
.
size
(
)
>=
SchedModel
->
getIssueWidth
(
)
)
{
ResourcesModel
->
clearResources
(
)
;
Packet
.
clear
(
)
;
TotalPackets
++
;
startNewCycle
=
true
;
}
switch
(
SU
->
getInstr
(
)
->
getOpcode
(
)
)
{
default
:
ResourcesModel
->
reserveResources
(
*
SU
->
getInstr
(
)
)
;
break
;
case
TargetOpcode
::
EXTRACT_SUBREG
:
case
TargetOpcode
::
INSERT_SUBREG
:
case
TargetOpcode
::
SUBREG_TO_REG
:
case
TargetOpcode
::
REG_SEQUENCE
:
case
TargetOpcode
::
IMPLICIT_DEF
:
case
TargetOpcode
::
KILL
:
case
TargetOpcode
::
CFI_INSTRUCTION
:
case
TargetOpcode
::
EH_LABEL
:
case
TargetOpcode
::
COPY
:
case
TargetOpcode
::
INLINEASM
:
break
;
}
Packet
.
push_back
(
SU
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Packet["
<<
TotalPackets
<<
"]:\n"
)
;
for
(
unsigned
i
=
0
,
e
=
Packet
.
size
(
)
;
i
!=
e
;
++
i
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"\t["
<<
i
<<
"] SU("
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
Packet
[
i
]
->
NodeNum
<<
")\t"
)
;
LLVM_DEBUG
(
Packet
[
i
]
->
getInstr
(
)
->
dump
(
)
)
;
}
return
startNewCycle
;
}
</s>


<s> bool MSP430FrameInfo :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


"Load should return a value and a chain"

LowerOperation - Provide custom lowering hooks for some operations .


"microMIPS instruction size reduction pass"

getPassName - Return a nice clean name for a pass .


<s> bool AArch64TargetLowering :: isTruncateFree ( EVT VT1 , EVT VT2 ) const { if ( VT1 . isVector ( ) || VT2 . isVector ( ) || ! VT1 . isInteger ( ) || ! VT2 . isInteger ( ) ) return false ; uint64_t NumBits1 = VT1 . getFixedSizeInBits ( ) ; uint64_t NumBits2 = VT2 . getFixedSizeInBits ( ) ; return NumBits1 > NumBits2 ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s> bool X86RetpolineThunks :: doInitialization ( Module & M ) { InsertedThunks = false ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> void NVPTXTargetStreamer :: closeLastSection ( ) { if ( HasSections ) getStreamer ( ) . EmitRawText ( "\t}" ) ; } </s>


<s> DecodeStatus PPCDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & OS , raw_ostream & CS ) const { Size = 4 ; if ( Bytes . size ( ) < 4 ) { Size = 0 ; return MCDisassembler :: Fail ; } uint32_t Inst = IsLittleEndian ? support :: endian :: read32le ( Bytes . data ( ) ) : support :: endian :: read32be ( Bytes . data ( ) ) ; if ( STI . getFeatureBits ( ) [ PPC :: FeatureQPX ] ) { DecodeStatus result = decodeInstruction ( DecoderTableQPX32 , MI , Inst , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) return result ; } return decodeInstruction ( DecoderTable32 , MI , Inst , Address , this , STI ) ; } </s>

Returns the disassembly of a single instruction .


<s>
const
MCFixupKindInfo
&
SICAsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
SIC
::
NumTargetFixupKinds
]
=
{
{
"fixup_SIC_32"
,
0
,
32
,
0
}
,
{
"fixup_SIC_HI16"
,
0
,
16
,
0
}
,
{
"fixup_SIC_LO16"
,
0
,
16
,
0
}
,
{
"fixup_SIC_GPREL16"
,
0
,
16
,
0
}
,
{
"fixup_SIC_GOT"
,
0
,
16
,
0
}
,
{
"fixup_SIC_PC16"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_SIC_PC24"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_SIC_CALL16"
,
0
,
16
,
0
}
,
{
"fixup_SIC_GOT_HI16"
,
0
,
16
,
0
}
,
{
"fixup_SIC_GOT_LO16"
,
0
,
16
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> static bool isF128SoftLibCall ( const char * CallSym ) { const char * const LibCalls [ ] = { "__addtf3" , "__divtf3" , "__eqtf2" , "__extenddftf2" , "__extendsftf2" , "__fixtfdi" , "__fixtfsi" , "__fixtfti" , "__fixunstfdi" , "__fixunstfsi" , "__fixunstfti" , "__floatditf" , "__floatsitf" , "__floattitf" , "__floatunditf" , "__floatunsitf" , "__floatuntitf" , "__getf2" , "__gttf2" , "__letf2" , "__lttf2" , "__multf3" , "__netf2" , "__powitf2" , "__subtf3" , "__trunctfdf2" , "__trunctfsf2" , "__unordtf2" , "ceill" , "copysignl" , "cosl" , "exp2l" , "expl" , "floorl" , "fmal" , "fmodl" , "log10l" , "log2l" , "logl" , "nearbyintl" , "powl" , "rintl" , "sinl" , "sqrtl" , "truncl" } ; const char * const * End = LibCalls + array_lengthof ( LibCalls ) ; MipsTargetLowering :: LTStr Comp ; for ( const char * const * I = LibCalls ; I < End - 1 ; ++ I ) assert ( Comp ( * I , * ( I + 1 ) ) ) ; return std :: binary_search ( LibCalls , End , CallSym , Comp ) ; } </s>

This function returns true if CallSym is a long double emulation routine .


<s> static bool ck803_rtx_costs ( rtx x , int code , int outer_code ATTRIBUTE_UNUSED , int * total , bool speed ATTRIBUTE_UNUSED ) { switch ( code ) { case SET : if ( MEM_P ( XEXP ( x , 1 ) ) ) { struct csky_address op1 ; bool address_valid = decompose_csky_address ( XEXP ( XEXP ( x , 1 ) , 0 ) , & op1 ) ; if ( op1 . index ) { * total = COSTS_N_INSNS ( 3 ) ; return true ; } else if ( address_valid ) { * total = COSTS_N_INSNS ( 1 ) ; return true ; } } if ( REG_P ( XEXP ( x , 0 ) ) && ( GET_CODE ( XEXP ( x , 1 ) ) == PLUS ) ) { rtx sub_exp = XEXP ( x , 1 ) ; if ( REG_P ( XEXP ( sub_exp , 0 ) ) && REG_P ( XEXP ( sub_exp , 1 ) ) ) { * total = COSTS_N_INSNS ( 1 ) ; return true ; } } return false ; case MULT : if ( REG_P ( XEXP ( x , 0 ) ) && CONST_INT_P ( XEXP ( x , 1 ) ) ) { HOST_WIDE_INT val = INTVAL ( XEXP ( x , 1 ) ) ; if ( val % 2 == 0 && val < 0xffffffff && val > 0 ) { * total = COSTS_N_INSNS ( 1 ) ; return true ; } } return false ; case CONST : case LABEL_REF : case SYMBOL_REF : * total = COSTS_N_INSNS ( 3 ) ; return true ; default : return false ; } } </s>


"rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n"

A C expression returning the cost of moving data from a register of class CLASS1 to one of CLASS2 .


"********** MI Converging Scheduling VLIW BB#"

Schedule - This is called back from ScheduleDAGInstrs : :Run ( ) when it 's time to do some work .


<s>
uint64_t
SystemZMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
if
(
MO
.
isImm
(
)
)
return
static_cast
<
uint64_t
>
(
MO
.
getImm
(
)
)
;
llvm_unreachable
(
"Unexpected operand type!"
)
;
}
</s>

getMachineOpValue - Return binary encoding of operand .

SystemZ
SystemZ
"Unexpected operand type!"


<s> static rtx_insn * bb_first_real_insn ( basic_block bb ) { rtx_insn * insn ; FOR_BB_INSNS ( bb , insn ) if ( INSN_P ( insn ) ) return insn ; return 0 ; } </s>

Return first real insn in BB , or return NULL_RTX if BB does not contain real insns .


<s> bool isAtomic ( ) const { return Ordering != AtomicOrdering :: NotAtomic ; } </s>

Returns true if this operation has an atomic ordering requirement of unordered or higher , false otherwise .


<s> BitVector SPIRVRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { return BitVector ( getNumRegs ( ) ) ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
const
char
*
nds32_output_stack_pop
(
rtx
par_rtx
ATTRIBUTE_UNUSED
)
{
char
pattern
[
100
]
;
rtx
operands
[
3
]
;
int
rb_eh_data
=
cfun
->
machine
->
eh_return_data_first_regno
;
int
re_eh_data
=
cfun
->
machine
->
eh_return_data_last_regno
;
int
first_eh_data_regno
=
EH_RETURN_DATA_REGNO
(
0
)
;
int
rb_callee_saved
=
cfun
->
machine
->
callee_saved_first_gpr_regno
;
int
re_callee_saved
=
cfun
->
machine
->
callee_saved_last_gpr_regno
;
if
(
reg_mentioned_p
(
gen_rtx_REG
(
SImode
,
first_eh_data_regno
)
,
par_rtx
)
)
{
operands
[
0
]
=
gen_rtx_REG
(
SImode
,
rb_eh_data
)
;
operands
[
1
]
=
gen_rtx_REG
(
SImode
,
re_eh_data
)
;
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"pop.s\t%s"
,
"%0, %1, { }"
)
;
output_asm_insn
(
pattern
,
operands
)
;
return
""
;
}
if
(
NDS32_V3PUSH_AVAILABLE_P
)
{
int
sp_adjust
;
operands
[
0
]
=
gen_rtx_REG
(
SImode
,
re_callee_saved
)
;
sp_adjust
=
cfun
->
machine
->
local_size
+
cfun
->
machine
->
out_args_size
+
cfun
->
machine
->
callee_saved_area_gpr_padding_bytes
+
cfun
->
machine
->
callee_saved_fpr_regs_size
;
if
(
satisfies_constraint_Iu08
(
GEN_INT
(
sp_adjust
)
)
&&
NDS32_DOUBLE_WORD_ALIGN_P
(
sp_adjust
)
&&
!
cfun
->
calls_alloca
)
operands
[
1
]
=
GEN_INT
(
sp_adjust
)
;
else
{
if
(
cfun
->
machine
->
callee_saved_first_fpr_regno
!=
SP_REGNUM
)
{
sp_adjust
=
cfun
->
machine
->
callee_saved_area_gpr_padding_bytes
+
cfun
->
machine
->
callee_saved_fpr_regs_size
;
operands
[
1
]
=
GEN_INT
(
sp_adjust
)
;
}
else
{
operands
[
1
]
=
GEN_INT
(
0
)
;
}
}
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"pop25\t%%0, %%1"
)
;
}
else
{
int
pop_en4_only_p
=
0
;
operands
[
0
]
=
gen_rtx_REG
(
SImode
,
rb_callee_saved
)
;
operands
[
1
]
=
gen_rtx_REG
(
SImode
,
re_callee_saved
)
;
if
(
!
cfun
->
machine
->
fp_size
&&
!
cfun
->
machine
->
gp_size
&&
!
cfun
->
machine
->
lp_size
&&
REGNO
(
operands
[
0
]
)
==
SP_REGNUM
&&
REGNO
(
operands
[
1
]
)
==
SP_REGNUM
)
{
return
""
;
}
else
{
if
(
REGNO
(
operands
[
0
]
)
==
SP_REGNUM
&&
REGNO
(
operands
[
1
]
)
==
SP_REGNUM
)
pop_en4_only_p
=
1
;
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"pop.s\t%s{%s%s%s }"
,
pop_en4_only_p
""
:
"%0, %1, "
,
cfun
->
machine
->
fp_size
" $fp"
:
""
,
cfun
->
machine
->
gp_size
" $gp"
:
""
,
cfun
->
machine
->
lp_size
" $lp"
:
""
)
;
}
}
output_asm_insn
(
pattern
,
operands
)
;
return
""
;
}
</s>

Function to output stack pop operation . We need to deal with normal stack pop multiple or stack v3pop .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"BPF Assembly Printer"
;
}
</s>


<s> void SparcFrameLowering :: emitPrologue ( MachineFunction & MF ) const { SparcMachineFunctionInfo * FuncInfo = MF . getInfo < SparcMachineFunctionInfo > ( ) ; MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const SparcInstrInfo & TII = * static_cast < const SparcInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; unsigned SAVEri = SP :: SAVEri ; unsigned SAVErr = SP :: SAVErr ; if ( FuncInfo -> isLeafProc ( ) ) { if ( NumBytes == 0 ) return ; SAVEri = SP :: ADDri ; SAVErr = SP :: ADDrr ; } NumBytes = - SubTarget . getAdjustedFrameSize ( NumBytes ) ; emitSPAdjustment ( MF , MBB , MBBI , NumBytes , SAVErr , SAVEri ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; unsigned regFP = MRI -> getDwarfRegNum ( SP :: I6 , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , regFP ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createWindowSave ( nullptr ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; unsigned regInRA = MRI -> getDwarfRegNum ( SP :: I7 , true ) ; unsigned regOutRA = MRI -> getDwarfRegNum ( SP :: O7 , true ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createRegister ( nullptr , regOutRA , regInRA ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool doInitialization ( Module & M ) override { Result . reset ( new AMDGPUAAResult ( M . getDataLayout ( ) ) ) ; return false ; } </s>


<s> unsigned PPCTTIImpl :: getNumberOfRegisters ( unsigned ClassID ) const { assert ( ClassID == GPRRC || ClassID == FPRRC || ClassID == VRRC || ClassID == VSXRC ) ; if ( ST -> hasVSX ( ) ) { assert ( ClassID == GPRRC || ClassID == VSXRC || ClassID == VRRC ) ; return ClassID == VSXRC ? 64 : 32 ; } assert ( ClassID == GPRRC || ClassID == FPRRC || ClassID == VRRC ) ; return 32 ; } </s>


<s> bool AMDGPUPassConfig :: addPreEmitPass ( ) { const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) { addPass ( createAMDGPUCFGStructurizerPass ( ) ) ; addPass ( createR600ExpandSpecialInstrsPass ( * TM ) ) ; addPass ( & FinalizeMachineBundlesID ) ; addPass ( createR600Packetizer ( * TM ) ) ; addPass ( createR600ControlFlowFinalizer ( * TM ) ) ; } else { addPass ( createSILowerControlFlowPass ( * TM ) ) ; } return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void AArch64PostLegalizerCombiner :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < TargetPassConfig > ( ) ; AU . setPreservesCFG ( ) ; getSelectionDAGFallbackAnalysisUsage ( AU ) ; AU . addRequired < GISelKnownBitsAnalysis > ( ) ; AU . addPreserved < GISelKnownBitsAnalysis > ( ) ; if ( ! IsOptNone ) { AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < GISelCSEAnalysisWrapperPass > ( ) ; AU . addPreserved < GISelCSEAnalysisWrapperPass > ( ) ; } MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static rtx frv_expand_voidaccop_builtin ( enum insn_code icode , tree arglist ) { rtx pat ; rtx op0 = frv_read_argument ( & arglist ) ; rtx op1 = frv_read_argument ( & arglist ) ; rtx op2 ; rtx op3 ; op0 = frv_int_to_acc ( icode , 0 , op0 ) ; if ( ! op0 ) return NULL_RTX ; op1 = frv_int_to_acc ( icode , 1 , op1 ) ; if ( ! op1 ) return NULL_RTX ; op2 = frv_matching_accg_for_acc ( op0 ) ; op3 = frv_matching_accg_for_acc ( op1 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 , op2 , op3 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return NULL_RTX ; } </s>

Expand builtins that perform accumulator-to-accumulator operations . These builtins take two accumulator numbers as argument and return void .


<s> void HexagonInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { DebugLoc DL ; BuildMI ( MBB , MI , DL , get ( Hexagon :: A2_nop ) ) ; } </s>

Insert a noop into the instruction stream at the specified point .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Hexagon Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> unsigned HexagonTTIImpl :: getPrefetchDistance ( ) const { return getST ( ) -> getL1PrefetchDistance ( ) ; } </s>

Return the preferred prefetch distance in terms of instructions .


<s> machine_mode s390_tm_ccmode ( rtx op1 , rtx op2 , bool mixed ) { int bit0 , bit1 ; if ( GET_CODE ( op1 ) != CONST_INT || GET_CODE ( op2 ) != CONST_INT ) return VOIDmode ; if ( INTVAL ( op2 ) == 0 ) return CCTmode ; if ( INTVAL ( op2 ) == INTVAL ( op1 ) ) return CCT3mode ; if ( mixed ) { bit1 = exact_log2 ( INTVAL ( op2 ) ) ; bit0 = exact_log2 ( INTVAL ( op1 ) ^ INTVAL ( op2 ) ) ; if ( bit0 != - 1 && bit1 != - 1 ) return bit0 > bit1 ? CCT1mode : CCT2mode ; } return VOIDmode ; } </s>

If a test-under-mask instruction can be used to implement ( compare ( and ... OP1 ) OP2 ) , return the CC mode required to do that . Otherwise , return VOIDmode . MIXED is true if the instruction can distinguish between CC1 and CC2 for mixed selected bits ( TMxx ) , it is false if the instruction can not ( TM ) .


<s> bool isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const override { return false ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> const Z80RegisterInfo * getRegisterInfo ( ) const override { return & RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool ARM64PassConfig :: addPreEmitPass ( ) { addPass ( createARM64BranchRelaxation ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getSubtarget < ARM64Subtarget > ( ) . isTargetMachO ( ) ) addPass ( createARM64CollectLOHPass ( ) ) ; return true ; } </s>


<s> static int rs6000_variable_issue_1 ( rtx_insn * insn , int more ) { last_scheduled_insn = insn ; if ( GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) { cached_can_issue_more = more ; return cached_can_issue_more ; } if ( insn_terminates_group_p ( insn , current_group ) ) { cached_can_issue_more = 0 ; return cached_can_issue_more ; } if ( recog_memoized ( insn ) < 0 ) return more ; if ( rs6000_sched_groups ) { if ( is_microcoded_insn ( insn ) ) cached_can_issue_more = 0 ; else if ( is_cracked_insn ( insn ) ) cached_can_issue_more = more > 2 ? more - 2 : 0 ; else cached_can_issue_more = more - 1 ; return cached_can_issue_more ; } if ( rs6000_cpu_attr == CPU_CELL && is_nonpipeline_insn ( insn ) ) return 0 ; cached_can_issue_more = more - 1 ; return cached_can_issue_more ; } </s>

Power4 load update and store update instructions are cracked into a load or store and an integer insn which are executed in the same cycle . Branches have their own dispatch slot which does not count against the GCC issue rate , but it changes the program flow so there are no other instructions to issue in this cycle .


<s> unsigned ARMBaseInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case ARM :: STR : case ARM :: t2STRs : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isReg ( ) && MI -> getOperand ( 3 ) . isImm ( ) && MI -> getOperand ( 2 ) . getReg ( ) == 0 && MI -> getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: t2STRi12 : case ARM :: tSpill : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VSTRD : case ARM :: VSTRS : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> MCObjectWriter * SNESAsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { return createSNESELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI ( OSType ) ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static MachineInstr * findLoopInstr ( MachineBasicBlock * BB , int EndLoopOp , SmallPtrSet < MachineBasicBlock * , 8 > & Visited ) { int LOOPi ; int LOOPr ; if ( EndLoopOp == Hexagon :: ENDLOOP0 ) { LOOPi = Hexagon :: J2_loop0i ; LOOPr = Hexagon :: J2_loop0r ; } else { LOOPi = Hexagon :: J2_loop1i ; LOOPr = Hexagon :: J2_loop1r ; } for ( MachineBasicBlock :: pred_iterator PB = BB -> pred_begin ( ) , PE = BB -> pred_end ( ) ; PB != PE ; ++ PB ) { if ( ! Visited . insert ( * PB ) . second ) continue ; if ( * PB == BB ) continue ; for ( MachineBasicBlock :: reverse_instr_iterator I = ( * PB ) -> instr_rbegin ( ) , E = ( * PB ) -> instr_rend ( ) ; I != E ; ++ I ) { int Opc = I -> getOpcode ( ) ; if ( Opc == LOOPi || Opc == LOOPr ) return & * I ; if ( Opc == EndLoopOp ) return 0 ; } MachineInstr * loop = findLoopInstr ( * PB , EndLoopOp , Visited ) ; if ( loop ) return loop ; } return 0 ; } </s>

Find the hardware loop instruction used to set-up the specified loop .


"@c Copyright (C) 2012-2022 Free Software Foundation, Inc.\n"

"@c For copying conditions, see the file "

"@c This file is generated automatically using\n"

Main program to convert flat files into built-in initialization code .


"Can only insert epilog into returning blocks"

"Expected to see callee-save register restore code"


<s> unsigned LanaiInstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . getOpcode ( ) == Lanai :: LDW_RI ) { unsigned Reg ; if ( ( Reg = isLoadFromStackSlot ( MI , FrameIndex ) ) ) return Reg ; const MachineMemOperand * Dummy ; return hasLoadFromStackSlot ( MI , Dummy , FrameIndex ) ; } return 0 ; } </s>

isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s> void SITargetLowering :: AdjustInstrPostInstrSelection ( MachineInstr * MI , SDNode * Node ) const { const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; TII -> legalizeOperands ( MI ) ; if ( TII -> isMIMG ( MI -> getOpcode ( ) ) ) { unsigned VReg = MI -> getOperand ( 0 ) . getReg ( ) ; unsigned Writemask = MI -> getOperand ( 1 ) . getImm ( ) ; unsigned BitsSet = 0 ; for ( unsigned i = 0 ; i < 4 ; ++ i ) BitsSet += Writemask & ( 1 << i ) ? 1 : 0 ; const TargetRegisterClass * RC ; switch ( BitsSet ) { default : return ; case 1 : RC = & AMDGPU :: VReg_32RegClass ; break ; case 2 : RC = & AMDGPU :: VReg_64RegClass ; break ; case 3 : RC = & AMDGPU :: VReg_96RegClass ; break ; } unsigned NewOpcode = TII -> getMaskedMIMGOp ( MI -> getOpcode ( ) , BitsSet ) ; MI -> setDesc ( TII -> get ( NewOpcode ) ) ; MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; MRI . setRegClass ( VReg , RC ) ; return ; } int NoRetAtomicOp = AMDGPU :: getAtomicNoRetOp ( MI -> getOpcode ( ) ) ; if ( NoRetAtomicOp != - 1 ) { if ( ! Node -> hasAnyUseOfValue ( 0 ) ) { MI -> setDesc ( TII -> get ( NoRetAtomicOp ) ) ; MI -> RemoveOperand ( 0 ) ; } return ; } } </s>

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


"getJumpTargetOpValue expects only expressions"

"unexpect opcode in getJumpAbsoluteTargetOpValue()"

getJumpTargetOpValue - Return binary encoding of the jump target operand .


<s> BitVector AlphaRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( Alpha :: R15 ) ; Reserved . set ( Alpha :: R29 ) ; Reserved . set ( Alpha :: R30 ) ; Reserved . set ( Alpha :: R31 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
SDNode
*
WebAssemblyDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
llvm_unreachable
(
"TODO: implement Select"
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

WebAssembly
WebAssembly
"TODO: implement Select"


<s> void c6x_expand_call ( rtx retval , rtx address , bool sibcall ) { rtx callee = XEXP ( address , 0 ) ; rtx call_insn ; if ( ! c6x_call_operand ( callee , Pmode ) ) { callee = force_reg ( Pmode , callee ) ; address = change_address ( address , Pmode , callee ) ; } call_insn = gen_rtx_CALL ( VOIDmode , address , const0_rtx ) ; if ( sibcall ) { call_insn = emit_call_insn ( call_insn ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( call_insn ) , gen_rtx_REG ( Pmode , REG_B3 ) ) ; } else { if ( retval == NULL_RTX ) call_insn = emit_call_insn ( call_insn ) ; else call_insn = emit_call_insn ( gen_rtx_SET ( retval , call_insn ) ) ; } if ( flag_pic ) use_reg ( & CALL_INSN_FUNCTION_USAGE ( call_insn ) , pic_offset_table_rtx ) ; } </s>


"SIInstrInfo::loadRegToStackSlot - Can't retrieve spilled VGPR!"

Load the specified register of the given register class from the specified stack frame index .


<s> static bool loop_basic_block_p ( const basic_block cfg_bb ) { if ( JUMP_P ( BB_END ( cfg_bb ) ) && any_condjump_p ( BB_END ( cfg_bb ) ) ) { edge e ; edge_iterator ei ; FOR_EACH_EDGE ( e , ei , cfg_bb -> succs ) if ( e -> dest -> index == cfg_bb -> index ) return true ; } return false ; } </s>

Return true if the block is a loop itself : local_dem __________ ____|____ | | | | |________| | |_________| reaching_out


<s> static bool sparc_strict_argument_naming ( cumulative_args_t ca ATTRIBUTE_UNUSED ) { return TARGET_ARCH64 ? true : false ; } </s>

Handle the TARGET_STRICT_ARGUMENT_NAMING target hook .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < WebAssemblySubtarget > ( ) ; MRI = & MF . getRegInfo ( ) ; MFI = MF . getInfo < WebAssemblyFunctionInfo > ( ) ; return AsmPrinter :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


"insertBranch must not be told to insert a fallthrough"

"NVPTX branch conditions have two components!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> int nds32_can_use_btgl_p ( int ival ) { int one_bit_count ; one_bit_count = popcount_hwi ( ( unsigned HOST_WIDE_INT ) ( ival ) ) ; return ( TARGET_PERF_EXT && ( one_bit_count == 1 ) ) ; } </s>

Function to check if 'btgl ' instruction can be used with IVAL .


"Unknown regclass in loadRegFromStackSlot!"


<s> static char * detect_caches_freebsd ( void ) { unsigned l1_sizekb , l1_line , l1_assoc , l2_sizekb ; size_t len = 4 ; sysctlbyname ( "machdep.cacheline_size" , & l1_line , & len , NULL , 0 ) ; l1_sizekb = 32 ; l1_assoc = 0 ; l2_sizekb = 512 ; return describe_cache ( l1_sizekb , l1_line , l1_assoc , l2_sizekb ) ; } </s>

Returns the description of caches on FreeBSD PPC .


<s> static bool arm_evpc_neon_vrev ( struct expand_vec_perm_d * d ) { unsigned int i , j , diff , nelt = d -> perm . length ( ) ; rtx ( * gen ) ( machine_mode , rtx , rtx ) ; if ( ! d -> one_vector_p ) return false ; diff = d -> perm [ 0 ] ; switch ( diff ) { case 7 : switch ( d -> vmode ) { case E_V16QImode : case E_V8QImode : gen = gen_neon_vrev64 ; break ; default : return false ; } break ; case 3 : switch ( d -> vmode ) { case E_V16QImode : case E_V8QImode : gen = gen_neon_vrev32 ; break ; case E_V8HImode : case E_V4HImode : case E_V8HFmode : case E_V4HFmode : gen = gen_neon_vrev64 ; break ; default : return false ; } break ; case 1 : switch ( d -> vmode ) { case E_V16QImode : case E_V8QImode : gen = gen_neon_vrev16 ; break ; case E_V8HImode : case E_V4HImode : gen = gen_neon_vrev32 ; break ; case E_V4SImode : case E_V2SImode : case E_V4SFmode : case E_V2SFmode : gen = gen_neon_vrev64 ; break ; default : return false ; } break ; default : return false ; } for ( i = 0 ; i < nelt ; i += diff + 1 ) for ( j = 0 ; j <= diff ; j += 1 ) { gcc_assert ( i + j < nelt ) ; if ( d -> perm [ i + j ] != i + diff - j ) return false ; } if ( d -> testing_p ) return true ; emit_insn ( gen ( d -> vmode , d -> target , d -> op0 ) ) ; return true ; } </s>


<s> bool mem_operand_ds_form ( rtx op , machine_mode mode ) { unsigned HOST_WIDE_INT offset ; int extra ; rtx addr = XEXP ( op , 0 ) ; if ( ! offsettable_address_p ( false , mode , addr ) ) return false ; op = address_offset ( addr ) ; if ( op == NULL_RTX ) return true ; offset = INTVAL ( op ) ; if ( ( offset & 3 ) != 0 ) return false ; extra = GET_MODE_SIZE ( mode ) - UNITS_PER_WORD ; if ( extra < 0 ) extra = 0 ; if ( GET_CODE ( addr ) == LO_SUM ) offset = ( ( offset & 0xffff ) ^ 0x8000 ) - 0x8000 ; return offset + 0x8000 < 0x10000u - extra ; } </s>

As above , but for DS-FORM VSX insns . Unlike mem_operand_gpr , enforce an offset divisible by 4 even for 32-bit .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createMipsELFObjectWriter ( OS , OSType , IsLittle ) ; } </s>


<s>
bool
PatmosBypassFromPML
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
!
EnableBypassFromPML
)
return
false
;
PMLImport
&
PI
=
getAnalysis
<
PMLImport
>
(
)
;
PMLMCQuery
*
Query
=
PI
.
createMCQuery
(
*
this
,
MF
)
;
bool
Changed
=
false
;
PMLQuery
::
ValueFactsMap
LoadFacts
;
if
(
Query
&&
Query
->
getMemFacts
(
MF
,
LoadFacts
)
)
{
DEBUG
(
dbgs
(
)
<<
"[BypassFromPML] "
<<
MF
.
getFunction
(
)
->
getName
(
)
<<
"\n"
)
;
for
(
MachineFunction
::
iterator
FI
=
MF
.
begin
(
)
,
FE
=
MF
.
end
(
)
;
FI
!=
FE
;
++
FI
)
{
PMLQuery
::
ValueFactList
&
VFL
=
Query
->
getBBMemFacts
(
LoadFacts
,
*
FI
)
;
if
(
!
VFL
.
empty
(
)
)
{
DEBUG
(
dbgs
(
)
<<
"  MBB#"
<<
FI
->
getNumber
(
)
<<
"\n"
)
;
Changed
|=
bypassCacheLoads
(
*
FI
,
Query
,
VFL
)
;
}
}
delete
Query
;
}
return
Changed
;
}
</s>

Patmos
Patmos
"[BypassFromPML] "
"\n"
"  MBB#"
"\n"


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , Subtarget ( TT , CPU , FS , * this , Options . StackAlignmentOverride ) { if ( Subtarget . isTargetWin64 ( ) ) this -> Options . TrapUnreachable = true ; this -> Options . Reciprocals . setDefaults ( "sqrtf" , true , 1 ) ; this -> Options . Reciprocals . setDefaults ( "divf" , false , 1 ) ; this -> Options . Reciprocals . setDefaults ( "vec-sqrtf" , true , 1 ) ; this -> Options . Reciprocals . setDefaults ( "vec-divf" , true , 1 ) ; initAsmInfo ( ) ; } </s>


Expand a builtin . These builtins are `` special '' because they do n't have symbolic constants defined per-instruction or per instruction-variant . Instead , the required info is looked up in the ARM_BUILTIN_DATA record that is passed into the function .


<s> const char * LM32TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case LM32ISD :: JmpLink : return "LM32ISD::JmpLink" ; case LM32ISD :: GPRel : return "LM32ISD::GPRel" ; case LM32ISD :: ICmp : return "LM32ISD::ICmp" ; case LM32ISD :: RetFlag : return "LM32ISD::RetFlag" ; case LM32ISD :: LM32Select_CC : return "LM32ISD::LM32Select_CC" ; case LM32ISD :: Hi : return "LM32ISD::Hi" ; case LM32ISD :: Lo : return "LM32ISD::Lo" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific


"SystemZ DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"SPARC Delay Slot Filler"
;
}
</s>


<s> bool HexagonBitSimplify :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; auto & HST = MF . getSubtarget < HexagonSubtarget > ( ) ; auto & HRI = * HST . getRegisterInfo ( ) ; auto & HII = * HST . getInstrInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool Changed ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) ; const HexagonEvaluator HE ( HRI , MRI , HII , MF ) ; BitTracker BT ( HE , MF ) ; DEBUG ( BT . trace ( true ) ) ; BT . run ( ) ; MachineBasicBlock & Entry = MF . front ( ) ; RegisterSet AIG ; ConstGeneration ImmG ( BT , HII , MRI ) ; Changed |= visitBlock ( Entry , ImmG , AIG ) ; RegisterSet ARE ; RedundantInstrElimination RIE ( BT , HII , MRI ) ; bool Ried = visitBlock ( Entry , RIE , ARE ) ; if ( Ried ) { Changed = true ; BT . run ( ) ; } RegisterSet ACG ; CopyGeneration CopyG ( BT , HII , MRI ) ; Changed |= visitBlock ( Entry , CopyG , ACG ) ; RegisterSet ACP ; CopyPropagation CopyP ( HRI , MRI ) ; Changed |= visitBlock ( Entry , CopyP , ACP ) ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) || Changed ; BT . run ( ) ; RegisterSet ABS ; BitSimplification BitS ( BT , HII , HRI , MRI , MF ) ; Changed |= visitBlock ( Entry , BitS , ABS ) ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) || Changed ; if ( Changed ) { for ( auto & B : MF ) for ( auto & I : B ) I . clearKillInfo ( ) ; DeadCodeElimination ( MF , * MDT ) . run ( ) ; } return Changed ; } </s>


<s> unsigned SIRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { return RC -> getNumRegs ( ) ; } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> rtx riscv_unspec_address ( rtx address , enum riscv_symbol_type symbol_type ) { rtx base , offset ; split_const ( address , & base , & offset ) ; return riscv_unspec_address_offset ( base , offset , symbol_type ) ; } </s>

Return an UNSPEC address with underlying address ADDRESS and symbol type SYMBOL_TYPE .


<s> bool AMDGPUPerfHintAnalysis :: runOnSCC ( CallGraphSCC & SCC ) { auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; const TargetMachine & TM = TPC -> getTM < TargetMachine > ( ) ; bool Changed = false ; for ( CallGraphNode * I : SCC ) { Function * F = I -> getFunction ( ) ; if ( ! F || F -> isDeclaration ( ) ) continue ; const TargetSubtargetInfo * ST = TM . getSubtargetImpl ( * F ) ; AMDGPUPerfHint Analyzer ( FIM , ST -> getTargetLowering ( ) ) ; if ( Analyzer . runOnFunction ( * F ) ) Changed = true ; } return Changed ; } </s>

runOnSCC - This method should be implemented by the subclass to perform whatever action is necessary for the specified SCC .


<s>
SDValue
SystemZTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
DL
,
SelectionDAG
&
DAG
)
const
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
SmallVector
<
CCValAssign
,
16
>
RetLocs
;
CCState
RetCCInfo
(
CallConv
,
IsVarArg
,
MF
,
TM
,
RetLocs
,
*
DAG
.
getContext
(
)
)
;
RetCCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_SystemZ
)
;
if
(
RetLocs
.
empty
(
)
)
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
Chain
)
;
SDValue
Glue
;
SmallVector
<
SDValue
,
4
>
RetOps
;
RetOps
.
push_back
(
Chain
)
;
for
(
unsigned
I
=
0
,
E
=
RetLocs
.
size
(
)
;
I
!=
E
;
++
I
)
{
CCValAssign
&
VA
=
RetLocs
[
I
]
;
SDValue
RetValue
=
OutVals
[
I
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
RetValue
=
convertValVTToLocVT
(
DAG
,
DL
,
VA
,
RetValue
)
;
unsigned
Reg
=
VA
.
getLocReg
(
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
Reg
,
RetValue
,
Glue
)
;
Glue
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
Reg
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Glue
.
getNode
(
)
)
RetOps
.
push_back
(
Glue
)
;
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
.
data
(
)
,
RetOps
.
size
(
)
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> virtual const TargetFrameInfo * getFrameInfo ( ) const { return & FrameInfo ; } </s>

getFrameInfo - Return the frame info object for the current function .


<s> static rtx move_from_acc ( unsigned int opno , rtx_insn * after ) { rtx dest = OP ( opno ) ; machine_mode mode = GET_MODE ( dest ) ; if ( REG_P ( dest ) && REGNO ( dest ) < 2 ) return dest ; return gen_and_emit_move ( dest , mode == QImode ? A : AX , after , false ) ; } </s>

Copy accumulator ( A or AX ) to DEST , placing any generated insns after AFTER . Returns accumulator RTX .


<s> void Thumb2InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { if ( RC == ARM :: GPRRegisterClass || RC == ARM :: tGPRRegisterClass || RC == ARM :: tcGPRRegisterClass || RC == ARM :: rGPRRegisterClass || RC == ARM :: GPRnopcRegisterClass ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2STRi12 ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } ARMBaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg , isKill , FI , RC , TRI ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .

ARM ARM::GPRRegisterClass ARM::tGPRRegisterClass ARM::tcGPRRegisterClass ARM::rGPRRegisterClass ARM::GPRnopcRegisterClass ARM::t2STRi12 0 ARM


<s> bool AArch64TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( AM . BaseGV ) return false ; if ( AM . HasBaseReg && AM . BaseOffs && AM . Scale ) return false ; uint64_t NumBytes = 0 ; if ( Ty -> isSized ( ) ) { uint64_t NumBits = DL . getTypeSizeInBits ( Ty ) ; NumBytes = NumBits / 8 ; if ( ! isPowerOf2_64 ( NumBits ) ) NumBytes = 0 ; } if ( ! AM . Scale ) { int64_t Offset = AM . BaseOffs ; if ( Offset >= - ( 1LL << 9 ) && Offset <= ( 1LL << 9 ) - 1 ) return true ; unsigned shift = Log2_64 ( NumBytes ) ; if ( NumBytes && Offset > 0 && ( Offset / NumBytes ) <= ( 1LL << 12 ) - 1 && ( Offset >> shift ) << shift == Offset ) return true ; return false ; } if ( ! AM . Scale || AM . Scale == 1 || ( AM . Scale > 0 && ( uint64_t ) AM . Scale == NumBytes ) ) return true ; return false ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> static void aarch64_select_early_remat_modes ( sbitmap modes ) { for ( int i = 0 ; i < NUM_MACHINE_MODES ; ++ i ) { machine_mode mode = ( machine_mode ) i ; unsigned int vec_flags = aarch64_classify_vector_mode ( mode ) ; if ( vec_flags & VEC_ANY_SVE ) bitmap_set_bit ( modes , i ) ; } } </s>