<s>
void
HexagonAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
if
(
MI
->
isBundle
(
)
)
{
std
::
vector
<
const
MachineInstr
*
>
BundleMIs
;
const
MachineBasicBlock
*
MBB
=
MI
->
getParent
(
)
;
MachineBasicBlock
::
const_instr_iterator
MII
=
MI
;
++
MII
;
unsigned
int
IgnoreCount
=
0
;
while
(
MII
!=
MBB
->
end
(
)
&&
MII
->
isInsideBundle
(
)
)
{
const
MachineInstr
*
MInst
=
MII
;
if
(
MInst
->
getOpcode
(
)
==
TargetOpcode
::
DBG_VALUE
||
MInst
->
getOpcode
(
)
==
TargetOpcode
::
IMPLICIT_DEF
)
{
IgnoreCount
++
;
++
MII
;
continue
;
}
BundleMIs
.
push_back
(
MInst
)
;
++
MII
;
}
unsigned
Size
=
BundleMIs
.
size
(
)
;
assert
(
(
Size
+
IgnoreCount
)
==
MI
->
getBundleSize
(
)
&&
"Corrupt Bundle!"
)
;
for
(
unsigned
Index
=
0
;
Index
<
Size
;
Index
++
)
{
HexagonMCInst
MCI
;
MCI
.
setPacketStart
(
Index
==
0
)
;
MCI
.
setPacketEnd
(
Index
==
(
Size
1
)
)
;
HexagonLowerToMC
(
BundleMIs
[
Index
]
,
MCI
,
*
this
)
;
EmitToStreamer
(
OutStreamer
,
MCI
)
;
}
}
else
{
HexagonMCInst
MCI
;
if
(
MI
->
getOpcode
(
)
==
Hexagon
::
ENDLOOP0
)
{
MCI
.
setPacketStart
(
true
)
;
MCI
.
setPacketEnd
(
true
)
;
}
HexagonLowerToMC
(
MI
,
MCI
,
*
this
)
;
EmitToStreamer
(
OutStreamer
,
MCI
)
;
}
return
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> unsigned ARCInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { if ( MI . getOpcode ( ) == TargetOpcode :: INLINEASM ) { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } return MI . getDesc ( ) . getSize ( ) ; } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> static bool arm_needs_doubleword_align ( machine_mode mode , const_tree type ) { if ( ! type ) return PARM_BOUNDARY < GET_MODE_ALIGNMENT ( mode ) ; if ( ! AGGREGATE_TYPE_P ( type ) ) return TYPE_ALIGN ( TYPE_MAIN_VARIANT ( type ) ) > PARM_BOUNDARY ; if ( TREE_CODE ( type ) == ARRAY_TYPE ) return TYPE_ALIGN ( TREE_TYPE ( type ) ) > PARM_BOUNDARY ; for ( tree field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) if ( DECL_ALIGN ( field ) > PARM_BOUNDARY ) return true ; return false ; } </s>

Return 1 if double word alignment is required for argument passing . Return -1 if double word alignment used to be required for argument passing before PR77728 ABI fix , but is not required anymore . Return 0 if double word alignment is not required and was n't requried before either .


<s>
static
bool
aarch64_validate_mcpu
(
const
char
*
str
,
const
struct
processor
*
*
res
,
unsigned
long
*
isa_flags
)
{
enum
aarch64_parse_opt_result
parse_res
=
aarch64_parse_cpu
(
str
,
res
,
isa_flags
)
;
if
(
parse_res
==
AARCH64_PARSE_OK
)
return
true
;
switch
(
parse_res
)
{
case
AARCH64_PARSE_MISSING_ARG
:
error
(
"missing cpu name in -mcpu=%qs"
,
str
)
;
break
;
case
AARCH64_PARSE_INVALID_ARG
:
error
(
"unknown value %qs for -mcpu"
,
str
)
;
break
;
case
AARCH64_PARSE_INVALID_FEATURE
:
error
(
"invalid feature modifier in -mcpu=%qs"
,
str
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
return
false
;
}
</s>

Validate a command-line -mcpu option . Parse the cpu and extensions ( if any ) specified in STR and throw errors if appropriate . Put the results if they are valid in RES and ISA_FLAGS . Return whether the option is valid .

aarch64
"missing cpu name in -mcpu=%qs"
"unknown value %qs for -mcpu"
"invalid feature modifier in -mcpu=%qs"


<s> const_iterator begin ( ) const { return Map . begin ( ) ; } </s>


<s> void R600InstrInfo :: reserveIndirectRegisters ( BitVector & Reserved , const MachineFunction & MF ) const { const R600Subtarget & ST = MF . getSubtarget < R600Subtarget > ( ) ; const R600FrameLowering * TFL = ST . getFrameLowering ( ) ; unsigned StackWidth = TFL -> getStackWidth ( MF ) ; int End = getIndirectIndexEnd ( MF ) ; if ( End == - 1 ) return ; for ( int Index = getIndirectIndexBegin ( MF ) ; Index <= End ; ++ Index ) { unsigned SuperReg = AMDGPU :: R600_Reg128RegClass . getRegister ( Index ) ; Reserved . set ( SuperReg ) ; for ( unsigned Chan = 0 ; Chan < StackWidth ; ++ Chan ) { unsigned Reg = AMDGPU :: R600_TReg32RegClass . getRegister ( ( 4 * Index ) + Chan ) ; Reserved . set ( Reg ) ; } } } </s>

Reserve the registers that may be accessed using indirect addressing .


<s> MVT SITargetLowering :: getScalarShiftAmountTy ( const DataLayout & , EVT VT ) const { return ( VT == MVT :: i16 ) ? MVT :: i16 : MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> static bool nds32_symbol_binds_local_p ( const_rtx x ) { return ( SYMBOL_REF_DECL ( x ) ? targetm . binds_local_p ( SYMBOL_REF_DECL ( x ) ) : SYMBOL_REF_LOCAL_P ( x ) ) ; } </s>

Return true if SYMBOL_REF X binds locally .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool shouldTransformSignedTruncationCheck ( EVT XVT , unsigned KeptBits ) const override { if ( XVT . isVector ( ) ) return false ; auto VTIsOk = [ ] ( EVT VT ) -> bool { return VT == MVT :: i8 || VT == MVT :: i16 || VT == MVT :: i32 || VT == MVT :: i64 ; } ; MVT KeptBitsVT = MVT :: getIntegerVT ( KeptBits ) ; return VTIsOk ( XVT ) && VTIsOk ( KeptBitsVT ) ; } </s>

Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be truncating or not : ( add x , ( 1 < < ( KeptBits-1 ) ) ) srccond ( 1 < < KeptBits ) Into it 's more traditional form : ( ( x < < C ) a > > C ) dstcond x Return true if we should transform .


<s> static rtx nvptx_function_value ( const_tree type , const_tree ARG_UNUSED ( func ) , bool outgoing ) { machine_mode mode = promote_return ( TYPE_MODE ( type ) ) ; if ( outgoing ) { cfun -> machine -> return_mode = mode ; return gen_rtx_REG ( mode , NVPTX_RETURN_REGNUM ) ; } return nvptx_libcall_value ( mode , NULL_RTX ) ; } </s>

TARGET_FUNCTION_VALUE implementation . Returns an RTX representing the place where function FUNC returns or receives a value of data type TYPE .


<s>
bool
SILoadStoreOptimizer
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
STM
=
&
MF
.
getSubtarget
<
GCNSubtarget
>
(
)
;
if
(
!
STM
->
loadStoreOptEnabled
(
)
)
return
false
;
TII
=
STM
->
getInstrInfo
(
)
;
TRI
=
&
TII
->
getRegisterInfo
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
AA
=
&
getAnalysis
<
AAResultsWrapperPass
>
(
)
.
getAAResults
(
)
;
assert
(
MRI
->
isSSA
(
)
&&
"Must be run on SSA"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Running SILoadStoreOptimizer\n"
)
;
bool
Modified
=
false
;
SmallPtrSet
<
MachineInstr
*
,
4
>
AnchorList
;
MemInfoMap
Visited
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
MachineBasicBlock
::
iterator
SectionEnd
;
for
(
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
,
E
=
MBB
.
end
(
)
;
I
!=
E
;
I
=
SectionEnd
)
{
bool
CollectModified
;
std
::
list
<
std
::
list
<
CombineInfo
>>
MergeableInsts
;
std
::
tie
(
SectionEnd
,
CollectModified
)
=
collectMergeableInsts
(
I
,
E
,
Visited
,
AnchorList
,
MergeableInsts
)
;
Modified
|=
CollectModified
;
do
{
OptimizeAgain
=
false
;
Modified
|=
optimizeBlock
(
MergeableInsts
)
;
}
while
(
OptimizeAgain
)
;
}
Visited
.
clear
(
)
;
AnchorList
.
clear
(
)
;
}
return
Modified
;
}
</s>

runOnMachineFunction - Emit the function body .

AMDGPU
SI
"Must be run on SSA"
"Running SILoadStoreOptimizer\n"
4


<s> void HexagonPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) { addPass ( createConstantPropagationPass ( ) ) ; addPass ( createDeadCodeEliminationPass ( ) ) ; } addPass ( createAtomicExpandPass ( ) ) ; if ( ! NoOpt ) { if ( EnableInitialCFGCleanup ) addPass ( createCFGSimplificationPass ( 1 , true , true , false , true ) ) ; if ( EnableLoopPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableCommGEP ) addPass ( createHexagonCommonGEP ( ) ) ; if ( EnableGenExtract ) addPass ( createHexagonGenExtract ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static bool rx_small_data_operand ( rtx op ) { if ( rx_small_data_limit == 0 ) return false ; if ( GET_CODE ( op ) == SYMBOL_REF ) return SYMBOL_REF_SMALL_P ( op ) ; return false ; } </s>

Return true if OP is a reference to an object in a small data area .


<s> static rtx pa_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { if ( ! TARGET_SOFT_FLOAT && ( mode == SFmode || mode == DFmode ) ) return gen_rtx_REG ( mode , 32 ) ; else return gen_rtx_REG ( mode , 28 ) ; } </s>

Implement the TARGET_LIBCALL_VALUE hook .


<s>
bool
SIInstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
MachineBasicBlock
::
iterator
I
=
MBB
.
getFirstTerminator
(
)
;
auto
E
=
MBB
.
end
(
)
;
if
(
I
==
E
)
return
false
;
while
(
I
!=
E
&&
!
I
->
isBranch
(
)
&&
!
I
->
isReturn
(
)
&&
I
->
getOpcode
(
)
!=
AMDGPU
::
SI_MASK_BRANCH
)
{
switch
(
I
->
getOpcode
(
)
)
{
case
AMDGPU
::
SI_MASK_BRANCH
:
case
AMDGPU
::
S_MOV_B64_term
:
case
AMDGPU
::
S_XOR_B64_term
:
case
AMDGPU
::
S_ANDN2_B64_term
:
break
;
case
AMDGPU
::
SI_IF
:
case
AMDGPU
::
SI_ELSE
:
case
AMDGPU
::
SI_KILL_I1_TERMINATOR
:
case
AMDGPU
::
SI_KILL_F32_COND_IMM_TERMINATOR
:
return
true
;
default
:
llvm_unreachable
(
"unexpected non-branch terminator inst"
)
;
}
++
I
;
}
if
(
I
==
E
)
return
false
;
if
(
I
->
getOpcode
(
)
!=
AMDGPU
::
SI_MASK_BRANCH
)
return
analyzeBranchImpl
(
MBB
,
I
,
TBB
,
FBB
,
Cond
,
AllowModify
)
;
++
I
;
if
(
I
==
MBB
.
end
(
)
)
return
true
;
if
(
analyzeBranchImpl
(
MBB
,
I
,
TBB
,
FBB
,
Cond
,
AllowModify
)
)
return
true
;
MachineBasicBlock
*
MaskBrDest
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
if
(
TBB
!=
MaskBrDest
||
Cond
.
empty
(
)
)
return
true
;
auto
Pred
=
Cond
[
0
]
.
getImm
(
)
;
return
(
Pred
!=
EXECZ
&&
Pred
!=
EXECNZ
)
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


"********** Abstract Member Accesses **********\n"

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> bool frv_const_unspec_p ( rtx x , struct frv_unspec * unspec ) { if ( GET_CODE ( x ) == CONST ) { unspec -> offset = 0 ; x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) { unspec -> offset += INTVAL ( XEXP ( x , 1 ) ) ; x = XEXP ( x , 0 ) ; } if ( GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNSPEC_GOT ) { unspec -> symbol = XVECEXP ( x , 0 , 0 ) ; unspec -> reloc = INTVAL ( XVECEXP ( x , 0 , 1 ) ) ; if ( unspec -> offset == 0 ) return true ; if ( frv_small_data_reloc_p ( unspec -> symbol , unspec -> reloc ) && unspec -> offset > 0 && ( unsigned HOST_WIDE_INT ) unspec -> offset < g_switch_value ) return true ; } } return false ; } </s>

Return true if X is a valid relocation unspec . If it is , fill in UNSPEC appropriately .


<s>
static
void
tilegx_asm_trampoline_template
(
FILE
*
file
)
{
int
ptr_mode_size
=
GET_MODE_SIZE
(
ptr_mode
)
;
if
(
TARGET_32BIT
)
{
fprintf
(
file
,
"\tlnk      r10\n"
)
;
fprintf
(
file
,
"\taddxi    r10, r10, 32\n"
)
;
fprintf
(
file
,
"\tld4s_add r11, r10, %d\n"
,
ptr_mode_size
)
;
fprintf
(
file
,
"\tld4s     r10, r10\n"
)
;
fprintf
(
file
,
"\tjr       r11\n"
)
;
fprintf
(
file
,
"\t.word 0 # <function address>\n"
)
;
fprintf
(
file
,
"\t.word 0 # <static chain value>\n"
)
;
}
else
{
fprintf
(
file
,
"\tlnk      r10\n"
)
;
fprintf
(
file
,
"\taddi     r10, r10, 32\n"
)
;
fprintf
(
file
,
"\tld_add   r11, r10, %d\n"
,
ptr_mode_size
)
;
fprintf
(
file
,
"\tld       r10, r10\n"
)
;
fprintf
(
file
,
"\tjr       r11\n"
)
;
fprintf
(
file
,
"\t.quad 0 # <function address>\n"
)
;
fprintf
(
file
,
"\t.quad 0 # <static chain value>\n"
)
;
}
}
</s>

tilegx
"\tlnk      r10\n"
"\taddxi    r10, r10, 32\n"
"\tld4s_add r11, r10, %d\n"
"\tld4s     r10, r10\n"
"\tjr       r11\n"
"\t.word 0 # <function address>\n"
"\t.word 0 # <static chain value>\n"
"\tlnk      r10\n"
"\taddi     r10, r10, 32\n"
"\tld_add   r11, r10, %d\n"
"\tld       r10, r10\n"
"\tjr       r11\n"
"\t.quad 0 # <function address>\n"
"\t.quad 0 # <static chain value>\n"


"\033[41;30m Unrecognized *virtual* insn \033[0m\n"

Rescans an insn to see if it 's recognized again . This is done carefully to ensure that all the constraint information is accurate for the newly matched insn .


<s> bool HexagonInstrInfo :: isPredicable ( const MachineInstr & MI ) const { if ( ! MI . getDesc ( ) . isPredicable ( ) ) return false ; if ( MI . isCall ( ) || isTailCall ( MI ) ) { if ( ! Subtarget . usePredicatedCalls ( ) ) return false ; } if ( ! Subtarget . hasV62Ops ( ) ) { switch ( MI . getOpcode ( ) ) { case Hexagon :: V6_vL32b_ai : case Hexagon :: V6_vL32b_pi : case Hexagon :: V6_vL32b_ppu : case Hexagon :: V6_vL32b_cur_ai : case Hexagon :: V6_vL32b_cur_pi : case Hexagon :: V6_vL32b_cur_ppu : case Hexagon :: V6_vL32b_nt_ai : case Hexagon :: V6_vL32b_nt_pi : case Hexagon :: V6_vL32b_nt_ppu : case Hexagon :: V6_vL32b_tmp_ai : case Hexagon :: V6_vL32b_tmp_pi : case Hexagon :: V6_vL32b_tmp_ppu : case Hexagon :: V6_vL32b_nt_cur_ai : case Hexagon :: V6_vL32b_nt_cur_pi : case Hexagon :: V6_vL32b_nt_cur_ppu : case Hexagon :: V6_vL32b_nt_tmp_ai : case Hexagon :: V6_vL32b_nt_tmp_pi : case Hexagon :: V6_vL32b_nt_tmp_ppu : return false ; } } return true ; } </s>

Return true if the specified instruction can be predicated .


<s>
void
ARCRegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected"
)
;
MachineInstr
&
MI
=
*
II
;
MachineOperand
&
FrameOp
=
MI
.
getOperand
(
FIOperandNum
)
;
int
FrameIndex
=
FrameOp
.
getIndex
(
)
;
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
const
ARCInstrInfo
&
TII
=
*
MF
.
getSubtarget
<
ARCSubtarget
>
(
)
.
getInstrInfo
(
)
;
const
ARCFrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
int
Offset
=
MF
.
getFrameInfo
(
)
.
getObjectOffset
(
FrameIndex
)
;
int
ObjSize
=
MF
.
getFrameInfo
(
)
.
getObjectSize
(
FrameIndex
)
;
int
StackSize
=
MF
.
getFrameInfo
(
)
.
getStackSize
(
)
;
int
LocalFrameSize
=
MF
.
getFrameInfo
(
)
.
getLocalFrameSize
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"\nFunction         : "
<<
MF
.
getName
(
)
<<
"\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"<--------->\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
MI
<<
"\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"FrameIndex         : "
<<
FrameIndex
<<
"\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ObjSize            : "
<<
ObjSize
<<
"\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"FrameOffset        : "
<<
Offset
<<
"\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"StackSize          : "
<<
StackSize
<<
"\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"LocalFrameSize     : "
<<
LocalFrameSize
<<
"\n"
)
;
(
void
)
LocalFrameSize
;
if
(
MI
.
isDebugValue
(
)
)
{
Register
FrameReg
=
getFrameRegister
(
MF
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
)
;
return
;
}
Offset
+=
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Offset             : "
<<
Offset
<<
"\n"
<<
"<--------->\n"
)
;
Register
Reg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
assert
(
ARC
::
GPR32RegClass
.
contains
(
Reg
)
&&
"Unexpected register operand"
)
;
if
(
!
TFI
->
hasFP
(
MF
)
)
{
Offset
=
StackSize
+
Offset
;
if
(
FrameIndex
>=
0
)
assert
(
(
Offset
>=
0
&&
Offset
<
StackSize
)
&&
"SP Offset not in bounds."
)
;
}
else
{
if
(
FrameIndex
>=
0
)
{
assert
(
(
Offset
<
0
&&
Offset
<=
StackSize
)
&&
"FP Offset not in bounds."
)
;
}
}
ReplaceFrameIndex
(
II
,
TII
,
Reg
,
getFrameRegister
(
MF
)
,
Offset
,
StackSize
,
ObjSize
,
RS
,
SPAdj
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .

ARC
ARC
0
"Unexpected"
ARC
ARC
ARC
"\nFunction         : "
"\n"
"<--------->\n"
"\n"
"FrameIndex         : "
"\n"
"ObjSize            : "
"\n"
"FrameOffset        : "
"\n"
"StackSize          : "
"\n"
"LocalFrameSize     : "
"\n"
1
1
"Offset             : "
"\n"
"<--------->\n"
0
ARC::GPR32RegClass
"Unexpected register operand"
0
0
"SP Offset not in bounds."
0
0
"FP Offset not in bounds."


<s> bool ARMSubtarget :: enablePostRAMachineScheduler ( ) const { if ( ! enableMachineScheduler ( ) ) return false ; if ( disablePostRAScheduler ( ) ) return false ; return ! isThumb1Only ( ) ; } </s>

True if the subtarget should run a machine scheduler after register allocation .


<s> TargetPassConfig * OR1KTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new OR1KPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> const char * riscv_output_gpr_save ( unsigned mask ) { static char s [ 32 ] ; unsigned n = riscv_save_libcall_count ( mask ) ; ssize_t bytes = snprintf ( s , sizeof ( s ) , "call\tt0,__riscv_save_%u" , n ) ; gcc_assert ( ( size_t ) bytes < sizeof ( s ) ) ; return s ; } </s>

Return the code to invoke the GPR save routine .


<s> bool hasReadVCCZBug ( ) const { return getGeneration ( ) <= SEA_ISLANDS ; } </s>

Extra wait hazard is needed in some cases before s_cbranch_vccnz/s_cbranch_vccz .


<s> static bool s390_bb_fallthru_entry_likely ( basic_block bb ) { edge e , fallthru_edge ; edge_iterator ei ; if ( ! bb ) return false ; fallthru_edge = find_fallthru_edge ( bb -> preds ) ; if ( ! fallthru_edge ) return false ; FOR_EACH_EDGE ( e , ei , bb -> preds ) if ( e != fallthru_edge && e -> probability >= profile_probability :: likely ( ) ) return false ; return true ; } </s>

Returns TRUE if BB is entered via a fallthru edge and all other incoming edges are less than unlikely .


<s> bool csky_symbolic_address_p ( rtx x ) { switch ( GET_CODE ( x ) ) { case SYMBOL_REF : case LABEL_REF : return 1 ; case CONST : x = XEXP ( x , 0 ) ; return ( ( GET_CODE ( XEXP ( x , 0 ) ) == SYMBOL_REF || GET_CODE ( XEXP ( x , 0 ) ) == LABEL_REF ) && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) ; default : return 0 ; } } </s>

Return true if X is an address form involving a symbol or label ref .


<s> static rtx frv_expand_binopimm_builtin ( enum insn_code icode , tree arglist , rtx target ) { rtx pat ; rtx op0 = frv_read_argument ( & arglist ) ; rtx op1 = frv_read_argument ( & arglist ) ; if ( ! frv_check_constant_argument ( icode , 2 , op1 ) ) return NULL_RTX ; target = frv_legitimize_target ( icode , target ) ; op0 = frv_legitimize_argument ( icode , 1 , op0 ) ; pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return target ; } </s>

Expand builtins that take two operands and the second is immediate .


<s>
LLVM_DUMP_METHOD
void
dump
(
const
MachineRegisterInfo
*
MRI
)
const
{
dbgs
(
)
<<
"Registers: "
;
bool
First
=
true
;
for
(
unsigned
Reg
:
Edges
)
{
if
(
!
First
)
dbgs
(
)
<<
", "
;
First
=
false
;
dbgs
(
)
<<
printReg
(
Reg
,
MRI
->
getTargetRegisterInfo
(
)
,
0
,
MRI
)
;
}
dbgs
(
)
<<
"\n"
<<
"Instructions:"
;
for
(
MachineInstr
*
MI
:
Instrs
)
{
dbgs
(
)
<<
"\n  "
;
MI
->
print
(
dbgs
(
)
)
;
}
dbgs
(
)
<<
"\n"
;
}
</s>

Dump the plan to stderr ( for debugging ) .

X86
"Registers: "
", "
0
"\n"
"Instructions:"
"\n  "
"\n"


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineModuleInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static rtx sh_legitimize_address ( rtx x , rtx oldx , machine_mode mode ) { if ( flag_pic ) x = legitimize_pic_address ( oldx , mode , NULL_RTX ) ; if ( TARGET_SHMEDIA ) return x ; if ( ( ( TARGET_SH4 || TARGET_SH2A_DOUBLE ) && mode == DFmode ) || ( TARGET_SH2E && mode == SFmode ) ) return x ; if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , 1 ) ) && BASE_REGISTER_RTX_P ( XEXP ( x , 0 ) ) ) { struct disp_adjust adj = sh_find_mov_disp_adjust ( mode , INTVAL ( XEXP ( x , 1 ) ) ) ; if ( adj . offset_adjust != NULL_RTX && adj . mov_disp != NULL_RTX ) { rtx sum = expand_binop ( Pmode , add_optab , XEXP ( x , 0 ) , adj . offset_adjust , NULL_RTX , 0 , OPTAB_LIB_WIDEN ) ; return gen_rtx_PLUS ( Pmode , sum , adj . mov_disp ) ; } } return x ; } </s>

Try to modify an illegitimate address and make it legitimate . If we find one , return the new , valid address . Otherwise , return the original address .


<s> static void output_reg ( FILE * file , unsigned regno , machine_mode inner_mode , int subreg_offset = - 1 ) { if ( inner_mode == VOIDmode ) { if ( HARD_REGISTER_NUM_P ( regno ) ) fprintf ( file , "%s" , reg_names [ regno ] ) ; else fprintf ( file , "%%r%d" , regno ) ; } else if ( subreg_offset >= 0 ) { output_reg ( file , regno , VOIDmode ) ; fprintf ( file , "$%d" , subreg_offset ) ; } else { if ( subreg_offset == - 1 ) fprintf ( file , "{" ) ; output_reg ( file , regno , inner_mode , GET_MODE_SIZE ( inner_mode ) ) ; fprintf ( file , "," ) ; output_reg ( file , regno , inner_mode , 0 ) ; if ( subreg_offset == - 1 ) fprintf ( file , "}" ) ; } } </s>

Output a register , subreg , or register pair ( with optional enclosing braces ) .


<s> SDValue PIC16TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { unsigned NumArgVals = Ins . size ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function * F = MF . getFunction ( ) ; std :: string FuncName = F -> getName ( ) ; ResetTmpOffsetMap ( DAG ) ; InitReservedFrameCount ( F , DAG ) ; const char * tmpName = ESNames :: createESName ( PAN :: getArgsLabel ( FuncName ) ) ; SDValue ES = DAG . getTargetExternalSymbol ( tmpName , MVT :: i8 ) ; SDVTList VTs = DAG . getVTList ( MVT :: i8 , MVT :: Other ) ; SDValue BS = DAG . getConstant ( 1 , MVT :: i8 ) ; for ( unsigned i = 0 ; i < NumArgVals ; ++ i ) { SDValue Offset = DAG . getConstant ( i , MVT :: i8 ) ; SDValue PICLoad = DAG . getNode ( PIC16ISD :: PIC16LdArg , dl , VTs , Chain , ES , BS , Offset ) ; Chain = getChain ( PICLoad ) ; InVals . push_back ( PICLoad ) ; } return Chain ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> uint32_t fpDenormModeSPValue ( ) const { if ( FP32InputDenormals && FP32OutputDenormals ) return FP_DENORM_FLUSH_NONE ; if ( FP32InputDenormals ) return FP_DENORM_FLUSH_OUT ; if ( FP32OutputDenormals ) return FP_DENORM_FLUSH_IN ; return FP_DENORM_FLUSH_IN_FLUSH_OUT ; } </s>

Get the encoding value for the FP_DENORM bits of the mode register for the FP32 denormal mode .


<s> int eligible_for_return_delay ( rtx_insn * trial ) { int regno ; rtx pat ; if ( crtl -> calls_eh_return ) return 0 ; if ( get_attr_in_branch_delay ( trial ) == IN_BRANCH_DELAY_FALSE ) return 0 ; if ( sparc_leaf_function_p || TARGET_FLAT ) return 1 ; if ( ! NONJUMP_INSN_P ( trial ) ) return 0 ; pat = PATTERN ( trial ) ; if ( GET_CODE ( pat ) == PARALLEL ) { int i ; if ( ! TARGET_V9 ) return 0 ; for ( i = XVECLEN ( pat , 0 ) - 1 ; i >= 0 ; i -- ) { rtx expr = XVECEXP ( pat , 0 , i ) ; if ( GET_CODE ( expr ) != SET ) return 0 ; if ( GET_CODE ( SET_DEST ( expr ) ) != REG ) return 0 ; regno = REGNO ( SET_DEST ( expr ) ) ; if ( regno >= 8 && regno < 24 ) return 0 ; } return ! epilogue_renumber ( & pat , 1 ) ; } if ( GET_CODE ( pat ) != SET ) return 0 ; if ( GET_CODE ( SET_DEST ( pat ) ) != REG ) return 0 ; regno = REGNO ( SET_DEST ( pat ) ) ; if ( regno >= 8 && regno < 24 ) return 0 ; if ( ! SPARC_INT_REG_P ( regno ) ) return TARGET_V9 && ! epilogue_renumber ( & pat , 1 ) ; return eligible_for_restore_insn ( trial , true ) ; } </s>

Return nonzero if TRIAL can go into the function return 's delay slot .


<s> static bool alpha_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) { if ( arg . mode == SFmode || arg . mode == SCmode ) return ! arg . named ; return arg . mode == TFmode || arg . mode == TCmode ; } </s>

Return true if TYPE should be passed by invisible reference .


<s> void override_options ( ) { s390_sr_alias_set = new_alias_set ( ) ; } </s>

Set global variables as needed for the options enabled .


<s> static int length_fp_args ( rtx insn ) { int length = 0 ; rtx link ; for ( link = CALL_INSN_FUNCTION_USAGE ( insn ) ; link ; link = XEXP ( link , 1 ) ) { int arg_mode , regno ; rtx use = XEXP ( link , 0 ) ; if ( ! ( GET_CODE ( use ) == USE && GET_CODE ( XEXP ( use , 0 ) ) == REG && FUNCTION_ARG_REGNO_P ( REGNO ( XEXP ( use , 0 ) ) ) ) ) continue ; arg_mode = GET_MODE ( XEXP ( use , 0 ) ) ; regno = REGNO ( XEXP ( use , 0 ) ) ; if ( regno >= 32 && regno <= 39 ) { if ( arg_mode == SFmode ) length += 8 ; else length += 12 ; } } return length ; } </s>

Compute length of the FP argument copy sequence for INSN .


<s>
StringRef
getPassName
(
)
const
override
{
return
"WebAssembly Optimize Live Intervals"
;
}
</s>

getPassName - Return a nice clean name for a pass .

WebAssembly
"WebAssembly Optimize Live Intervals"


<s> bool X86InstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { bool HasAVX = TM . getSubtarget < X86Subtarget > ( ) . hasAVX ( ) ; switch ( MI -> getOpcode ( ) ) { case X86 :: V_SET0 : return Expand2AddrUndef ( MI , get ( HasAVX ? X86 :: VXORPSrr : X86 :: XORPSrr ) ) ; case X86 :: TEST8ri_NOREX : MI -> setDesc ( get ( X86 :: TEST8ri ) ) ; return true ; } return false ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> static bool aarch64_pass_by_reference ( cumulative_args_t pcum ATTRIBUTE_UNUSED , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { HOST_WIDE_INT size ; machine_mode dummymode ; int nregs ; size = ( mode == BLKmode && type ) ? int_size_in_bytes ( type ) : ( int ) GET_MODE_SIZE ( mode ) ; if ( type && AGGREGATE_TYPE_P ( type ) ) { size = int_size_in_bytes ( type ) ; } if ( size < 0 ) return true ; if ( aarch64_vfp_is_call_or_return_candidate ( mode , type , & dummymode , & nregs , NULL ) ) return false ; return size > 2 * UNITS_PER_WORD ; } </s>


<s> static void mips_deallocate_stack ( rtx base , rtx offset , HOST_WIDE_INT new_frame_size ) { if ( base == stack_pointer_rtx && offset == const0_rtx ) return ; mips_frame_barrier ( ) ; if ( offset == const0_rtx ) { emit_move_insn ( stack_pointer_rtx , base ) ; mips_epilogue_set_cfa ( stack_pointer_rtx , new_frame_size ) ; } else if ( TARGET_MIPS16 && base != stack_pointer_rtx ) { emit_insn ( gen_add3_insn ( base , base , offset ) ) ; mips_epilogue_set_cfa ( base , new_frame_size ) ; emit_move_insn ( stack_pointer_rtx , base ) ; } else { emit_insn ( gen_add3_insn ( stack_pointer_rtx , base , offset ) ) ; mips_epilogue_set_cfa ( stack_pointer_rtx , new_frame_size ) ; } } </s>

Emit code to set the stack pointer to BASE + OFFSET , given that BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame . BASE , if not the stack pointer , is available as a temporary .


<s> AMDGPUAAResult run ( Function & F , AnalysisManager < Function > & AM ) { return AMDGPUAAResult ( F . getParent ( ) -> getDataLayout ( ) ) ; } </s>

Run the analysis pass over a function and produce a dominator tree .


<s> Register MMIXRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return MMIX :: r253 ; } </s>


<s> static rtx gen_push ( rtx arg ) { struct machine_function * m = cfun -> machine ; if ( m -> fs . cfa_reg == stack_pointer_rtx ) m -> fs . cfa_offset += UNITS_PER_WORD ; m -> fs . sp_offset += UNITS_PER_WORD ; if ( REG_P ( arg ) && GET_MODE ( arg ) != word_mode ) arg = gen_rtx_REG ( word_mode , REGNO ( arg ) ) ; return gen_rtx_SET ( gen_rtx_MEM ( word_mode , gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ) , arg ) ; } </s>

Code to generate prologue and epilogue sequences


<s> bool RISCVAsmBackend :: shouldInsertExtraNopBytesForCodeAlign ( const MCAlignFragment & AF , unsigned & Size ) { if ( ! STI . getFeatureBits ( ) [ RISCV :: FeatureRelax ] ) return false ; bool HasStdExtC = STI . getFeatureBits ( ) [ RISCV :: FeatureStdExtC ] ; unsigned MinNopLen = HasStdExtC ? 2 : 4 ; if ( AF . getAlignment ( ) <= MinNopLen ) { return false ; } else { Size = AF . getAlignment ( ) - MinNopLen ; return true ; } } </s>

Hook to check if extra nop bytes must be inserted for alignment directive .

RISCV RISCV RISCV::FeatureRelax RISCV::FeatureStdExtC 2 4


<s> unsigned X86TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , EVT VT ) const { if ( VT == MVT :: v32i1 && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return 1 ; return TargetLowering :: getNumRegistersForCallingConv ( Context , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s>
bool
AArch64BranchRelaxation
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
MF
=
&
mf
;
if
(
!
BranchRelaxation
)
return
false
;
DEBUG
(
dbgs
(
)
<<
"***** AArch64BranchRelaxation *****\n"
)
;
TII
=
(
const
AArch64InstrInfo
*
)
MF
->
getTarget
(
)
.
getSubtargetImpl
(
)
->
getInstrInfo
(
)
;
MF
->
RenumberBlocks
(
)
;
scanFunction
(
)
;
DEBUG
(
dbgs
(
)
<<
"  Basic blocks before relaxation\n"
)
;
DEBUG
(
dumpBBs
(
)
)
;
bool
MadeChange
=
false
;
while
(
relaxBranchInstructions
(
)
)
MadeChange
=
true
;
verify
(
)
;
DEBUG
(
dbgs
(
)
<<
"  Basic blocks after relaxation\n"
)
;
DEBUG
(
dbgs
(
)
<<
'\n'
;
dumpBBs
(
)
)
;
BlockInfo
.
clear
(
)
;
return
MadeChange
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> int nds32_adjust_insn_length ( rtx_insn * insn , int length ) { rtx src , dst ; switch ( recog_memoized ( insn ) ) { case CODE_FOR_move_df : case CODE_FOR_move_di : src = XEXP ( PATTERN ( insn ) , 1 ) ; dst = XEXP ( PATTERN ( insn ) , 0 ) ; if ( REG_P ( src ) && REG_P ( dst ) && ( REGNO ( src ) % 2 ) == 0 && ( REGNO ( dst ) % 2 ) == 0 ) length = 2 ; break ; default : break ; } return length ; } </s>

Computing the Length of an Insn . Modifies the length assigned to instruction INSN . LEN is the initially computed length of the insn .


<s> MVT AMDGPUTargetLowering :: getVectorIdxTy ( const DataLayout & ) const { return MVT :: i32 ; } </s>

Returns the type to be used for the index operand of : ISD : :INSERT_VECTOR_ELT , ISD : :EXTRACT_VECTOR_ELT , ISD : :INSERT_SUBVECTOR , and ISD : :EXTRACT_SUBVECTOR .


<s> bool MSP430TargetLowering :: isTruncateFree ( const Type * Ty1 , const Type * Ty2 ) const { if ( ! Ty1 -> isIntegerTy ( ) || ! Ty2 -> isIntegerTy ( ) ) return false ; return ( Ty1 -> getPrimitiveSizeInBits ( ) > Ty2 -> getPrimitiveSizeInBits ( ) ) ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s> unsigned getCSRFirstUseCost ( const MachineFunction & MF ) const override { return 100 ; } </s>

Allow the target to override the cost of using a callee-saved register for the first time .


<s> void R600PassConfig :: addPreRegAlloc ( ) { addPass ( createR600VectorRegMerger ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static tree altivec_build_resolved_builtin ( tree * args , int n , const struct altivec_builtin_types * desc ) { tree impl_fndecl = rs6000_builtin_decls [ desc -> overloaded_code ] ; tree ret_type = rs6000_builtin_type ( desc -> ret_type ) ; tree argtypes = TYPE_ARG_TYPES ( TREE_TYPE ( impl_fndecl ) ) ; tree arglist = NULL_TREE , arg_type [ 3 ] ; int i ; for ( i = 0 ; i < n ; i ++ ) arg_type [ i ] = TREE_VALUE ( argtypes ) , argtypes = TREE_CHAIN ( argtypes ) ; if ( desc -> code == ALTIVEC_BUILTIN_VCMPGE_P && desc -> overloaded_code != ALTIVEC_BUILTIN_VCMPGEFP_P ) { tree t ; t = args [ 2 ] , args [ 2 ] = args [ 1 ] , args [ 1 ] = t ; t = arg_type [ 2 ] , arg_type [ 2 ] = arg_type [ 1 ] , arg_type [ 1 ] = t ; args [ 0 ] = fold_build2 ( BIT_XOR_EXPR , TREE_TYPE ( args [ 0 ] ) , args [ 0 ] , build_int_cst ( NULL_TREE , 2 ) ) ; } while ( -- n >= 0 ) arglist = tree_cons ( NULL_TREE , fold_convert ( arg_type [ n ] , args [ n ] ) , arglist ) ; return fold_convert ( ret_type , build_function_call_expr ( impl_fndecl , arglist ) ) ; } </s>

Build a tree for a function call to an Altivec non-overloaded builtin . The overloaded builtin that matched the types and args is described by DESC . The N arguments are given in ARGS , respectively . Actually the only thing it does is calling fold_convert on ARGS , with a small exception for vec_ { all , any } _ { ge , le } predicates .


<s> InstructionCost ARMTTIImpl :: getArithmeticReductionCost ( unsigned Opcode , VectorType * ValTy , Optional < FastMathFlags > FMF , TTI :: TargetCostKind CostKind ) { if ( TTI :: requiresOrderedReduction ( FMF ) ) return BaseT :: getArithmeticReductionCost ( Opcode , ValTy , FMF , CostKind ) ; EVT ValVT = TLI -> getValueType ( DL , ValTy ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( ! ST -> hasMVEIntegerOps ( ) || ! ValVT . isSimple ( ) || ISD != ISD :: ADD ) return BaseT :: getArithmeticReductionCost ( Opcode , ValTy , FMF , CostKind ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; static const CostTblEntry CostTblAdd [ ] { { ISD :: ADD , MVT :: v16i8 , 1 } , { ISD :: ADD , MVT :: v8i16 , 1 } , { ISD :: ADD , MVT :: v4i32 , 1 } , } ; if ( const auto * Entry = CostTableLookup ( CostTblAdd , ISD , LT . second ) ) return Entry -> Cost * ST -> getMVEVectorCostFactor ( CostKind ) * LT . first ; return BaseT :: getArithmeticReductionCost ( Opcode , ValTy , FMF , CostKind ) ; } </s>

Calculate the cost of vector reduction intrinsics .


<s>
unsigned
TOYMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
{
return
CTX
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
}
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
assert
(
MO
.
isExpr
(
)
&&
"unknown operand kind in printOperand"
)
;
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
MCExpr
::
ExprKind
Kind
=
Expr
->
getKind
(
)
;
if
(
Kind
==
MCExpr
::
Binary
)
{
Expr
=
static_cast
<
const
MCBinaryExpr
*
>
(
Expr
)
->
getLHS
(
)
;
Kind
=
Expr
->
getKind
(
)
;
}
assert
(
Kind
==
MCExpr
::
SymbolRef
)
;
unsigned
FixupKind
;
switch
(
cast
<
MCSymbolRefExpr
>
(
Expr
)
->
getKind
(
)
)
{
default
:
llvm_unreachable
(
"Unknown fixup kind!"
)
;
case
MCSymbolRefExpr
::
VK_TOY_LO
:
{
FixupKind
=
TOY
::
fixup_toy_mov_lo16_pcrel
;
break
;
}
case
MCSymbolRefExpr
::
VK_TOY_HI
:
{
FixupKind
=
TOY
::
fixup_toy_mov_hi16_pcrel
;
break
;
}
}
Fixups
.
push_back
(
MCFixup
::
create
(
0
,
MO
.
getExpr
(
)
,
MCFixupKind
(
FixupKind
)
)
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> SDValue CSKYTargetLowering :: getTargetNode ( BlockAddressSDNode * N , SDLoc DL , EVT Ty , SelectionDAG & DAG , unsigned Flags ) const { return DAG . getTargetBlockAddress ( N -> getBlockAddress ( ) , Ty , N -> getOffset ( ) , Flags ) ; } </s>

Retrieve the target node this edge connects to .


<s> rtx xtensa_copy_incoming_a7 ( rtx opnd ) { rtx entry_insns = 0 ; rtx reg , tmp ; machine_mode mode ; if ( ! cfun -> machine -> need_a7_copy ) return opnd ; gcc_assert ( ! cfun -> machine -> set_frame_ptr_insn ) ; mode = GET_MODE ( opnd ) ; reg = opnd ; if ( GET_CODE ( reg ) == SUBREG ) { gcc_assert ( SUBREG_BYTE ( reg ) == 0 ) ; reg = SUBREG_REG ( reg ) ; } if ( GET_CODE ( reg ) != REG || REGNO ( reg ) > A7_REG || REGNO ( reg ) + HARD_REGNO_NREGS ( A7_REG , mode ) <= A7_REG ) return opnd ; gcc_assert ( REGNO ( reg ) + HARD_REGNO_NREGS ( A7_REG , mode ) - 1 == A7_REG ) ; cfun -> machine -> need_a7_copy = false ; start_sequence ( ) ; tmp = gen_reg_rtx ( mode ) ; switch ( mode ) { case DFmode : case DImode : emit_insn ( gen_movsi_internal ( gen_rtx_SUBREG ( SImode , tmp , 4 ) , gen_raw_REG ( SImode , A7_REG ) ) ) ; break ; case SFmode : emit_insn ( gen_movsf_internal ( tmp , gen_raw_REG ( mode , A7_REG ) ) ) ; break ; case SImode : emit_insn ( gen_movsi_internal ( tmp , gen_raw_REG ( mode , A7_REG ) ) ) ; break ; case HImode : emit_insn ( gen_movhi_internal ( tmp , gen_raw_REG ( mode , A7_REG ) ) ) ; break ; case QImode : emit_insn ( gen_movqi_internal ( tmp , gen_raw_REG ( mode , A7_REG ) ) ) ; break ; default : gcc_unreachable ( ) ; } cfun -> machine -> set_frame_ptr_insn = emit_insn ( gen_set_frame_ptr ( ) ) ; if ( mode == DFmode || mode == DImode ) emit_insn ( gen_movsi_internal ( gen_rtx_SUBREG ( SImode , tmp , 0 ) , gen_rtx_REG ( SImode , A7_REG - 1 ) ) ) ; entry_insns = get_insns ( ) ; end_sequence ( ) ; if ( cfun -> machine -> vararg_a7 ) { cfun -> machine -> vararg_a7_copy = entry_insns ; } else { push_topmost_sequence ( ) ; emit_insn_after ( entry_insns , get_insns ( ) ) ; pop_topmost_sequence ( ) ; } return tmp ; } </s>

Check if an incoming argument in a7 is expected to be used soon and if OPND is a register or register pair that includes a7 . If so , create a new pseudo and copy a7 into that pseudo at the very beginning of the function , followed by the special `` set_frame_ptr '' unspec_volatile insn . The return value is either the original operand , if it is not a7 , or the new pseudo containing a copy of the incoming argument . This is necessary because the register allocator will ignore conflicts with a7 and may either assign some other pseudo to a7 or use a7 as the hard_frame_pointer , clobbering the incoming argument in a7 . By copying the argument out of a7 as the very first thing , and then immediately following that with an unspec_volatile to keep the scheduler away , we should avoid any problems . Putting the set_frame_ptr insn at the beginning , with only the a7 copy before it , also makes it easier for the prologue expander to initialize the frame pointer after the a7 copy and to fix up the a7 copy to use the stack pointer instead of the frame pointer .


<s> int ep_memory_operand ( rtx op , machine_mode mode , int unsigned_load ) { rtx addr , op0 , op1 ; int max_offset ; int mask ; if ( ! TARGET_EP ) return FALSE ; if ( GET_CODE ( op ) != MEM ) return FALSE ; max_offset = ep_memory_offset ( mode , unsigned_load ) ; mask = GET_MODE_SIZE ( mode ) - 1 ; addr = XEXP ( op , 0 ) ; if ( GET_CODE ( addr ) == CONST ) addr = XEXP ( addr , 0 ) ; switch ( GET_CODE ( addr ) ) { default : break ; case SYMBOL_REF : return SYMBOL_REF_TDA_P ( addr ) ; case REG : return REGNO ( addr ) == EP_REGNUM ; case PLUS : op0 = XEXP ( addr , 0 ) ; op1 = XEXP ( addr , 1 ) ; if ( GET_CODE ( op1 ) == CONST_INT && INTVAL ( op1 ) < max_offset && INTVAL ( op1 ) >= 0 && ( INTVAL ( op1 ) & mask ) == 0 ) { if ( GET_CODE ( op0 ) == REG && REGNO ( op0 ) == EP_REGNUM ) return TRUE ; if ( GET_CODE ( op0 ) == SYMBOL_REF && SYMBOL_REF_TDA_P ( op0 ) ) return TRUE ; } break ; } return FALSE ; } </s>

Return true if OP is a valid short EP memory reference


<s> void AArch64MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; if ( MI . getOpcode ( ) == AArch64 :: TLSDESCCALL ) { MCFixupKind Fixup = MCFixupKind ( AArch64 :: fixup_aarch64_tlsdesc_call ) ; Fixups . push_back ( MCFixup :: create ( 0 , MI . getOperand ( 0 ) . getExpr ( ) , Fixup ) ) ; return ; } if ( MI . getOpcode ( ) == AArch64 :: CompilerBarrier || MI . getOpcode ( ) == AArch64 :: SPACE ) { return ; } uint64_t Binary = getBinaryCodeForInstr ( MI , Fixups , STI ) ; support :: endian :: write < uint32_t > ( OS , Binary , support :: little ) ; ++ MCNumEmitted ; } </s>

Encode the given Inst to bytes and append to CB .


<s>
bool
R600Packetizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
const
TargetInstrInfo
*
TII
=
Fn
.
getTarget
(
)
.
getInstrInfo
(
)
;
MachineLoopInfo
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
MachineDominatorTree
&
MDT
=
getAnalysis
<
MachineDominatorTree
>
(
)
;
R600PacketizerList
Packetizer
(
Fn
,
MLI
,
MDT
)
;
assert
(
Packetizer
.
getResourceTracker
(
)
&&
"Empty DFA table!"
)
;
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
MachineBasicBlock
::
iterator
End
=
MBB
->
end
(
)
;
MachineBasicBlock
::
iterator
MI
=
MBB
->
begin
(
)
;
while
(
MI
!=
End
)
{
if
(
MI
->
isKill
(
)
||
MI
->
getOpcode
(
)
==
AMDGPU
::
IMPLICIT_DEF
||
(
MI
->
getOpcode
(
)
==
AMDGPU
::
CF_ALU
&&
!
MI
->
getOperand
(
8
)
.
getImm
(
)
)
)
{
MachineBasicBlock
::
iterator
DeleteMI
=
MI
;
++
MI
;
MBB
->
erase
(
DeleteMI
)
;
End
=
MBB
->
end
(
)
;
continue
;
}
++
MI
;
}
}
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
unsigned
RemainingCount
=
MBB
->
size
(
)
;
for
(
MachineBasicBlock
::
iterator
RegionEnd
=
MBB
->
end
(
)
;
RegionEnd
!=
MBB
->
begin
(
)
;
)
{
MachineBasicBlock
::
iterator
I
=
RegionEnd
;
for
(
;
I
!=
MBB
->
begin
(
)
;
I
,
RemainingCount
)
{
if
(
TII
->
isSchedulingBoundary
(
std
::
prev
(
I
)
,
MBB
,
Fn
)
)
break
;
}
I
=
MBB
->
begin
(
)
;
if
(
I
==
RegionEnd
)
{
RegionEnd
=
std
::
prev
(
RegionEnd
)
;
RemainingCount
;
continue
;
}
if
(
I
==
std
::
prev
(
RegionEnd
)
)
{
RegionEnd
=
std
::
prev
(
RegionEnd
)
;
continue
;
}
Packetizer
.
PacketizeMIs
(
MBB
,
I
,
RegionEnd
)
;
RegionEnd
=
I
;
}
}
return
true
;
}
</s>


<s> static void sh_emit_storesi ( rtx addr , HOST_WIDE_INT offset , rtx value ) { gcc_assert ( ( offset & 3 ) == 0 ) ; emit_move_insn ( offset == 0 ? change_address ( addr , SImode , NULL_RTX ) : adjust_address ( addr , SImode , offset ) , value ) ; } </s>

Emit insns to store a value at memory address + offset .


<s> static void iq2000_setup_incoming_varargs ( cumulative_args_t cum_v , const function_arg_info & , int * pretend_size , int no_rtl ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; unsigned int iq2000_off = ! cum -> last_arg_fp ; unsigned int iq2000_fp_off = cum -> last_arg_fp ; if ( ( cum -> arg_words < MAX_ARGS_IN_REGISTERS - iq2000_off ) ) { int iq2000_save_gp_regs = MAX_ARGS_IN_REGISTERS - cum -> arg_words - iq2000_off ; int iq2000_save_fp_regs = ( MAX_ARGS_IN_REGISTERS - cum -> fp_arg_words - iq2000_fp_off ) ; if ( iq2000_save_gp_regs < 0 ) iq2000_save_gp_regs = 0 ; if ( iq2000_save_fp_regs < 0 ) iq2000_save_fp_regs = 0 ; * pretend_size = ( ( iq2000_save_gp_regs * UNITS_PER_WORD ) + ( iq2000_save_fp_regs * UNITS_PER_FPREG ) ) ; if ( ! ( no_rtl ) ) { if ( cum -> arg_words < MAX_ARGS_IN_REGISTERS - iq2000_off ) { rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , - ( iq2000_save_gp_regs * UNITS_PER_WORD ) ) ; mem = gen_rtx_MEM ( BLKmode , ptr ) ; move_block_from_reg ( cum -> arg_words + GP_ARG_FIRST + iq2000_off , mem , iq2000_save_gp_regs ) ; } } } } </s>

Worker function for TARGET_SETUP_INCOMING_VARARGS .


<s> bool AArch64WinCOFFObjectWriter :: recordRelocation ( const MCFixup & Fixup ) const { return true ; } </s>


<s> BitVector MINA32RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , MINA32 :: SP ) ; markSuperRegs ( Reserved , MINA32 :: PC ) ; markSuperRegs ( Reserved , MINA32 :: R8_USER ) ; markSuperRegs ( Reserved , MINA32 :: R9_USER ) ; markSuperRegs ( Reserved , MINA32 :: R10_USER ) ; markSuperRegs ( Reserved , MINA32 :: R11_USER ) ; markSuperRegs ( Reserved , MINA32 :: R12_USER ) ; markSuperRegs ( Reserved , MINA32 :: SP_USER ) ; markSuperRegs ( Reserved , MINA32 :: LR_USER ) ; markSuperRegs ( Reserved , MINA32 :: PC_USER ) ; markSuperRegs ( Reserved , MINA32 :: MCR ) ; markSuperRegs ( Reserved , MINA32 :: FRET ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , MINA32 :: R11 ) ; if ( hasBasePointer ( MF ) ) markSuperRegs ( Reserved , BasePtr ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static bool ix86_dep_by_shift_count_body ( const_rtx set_body , const_rtx use_body ) { rtx set_dest ; rtx shift_rtx ; int i ; switch ( GET_CODE ( set_body ) ) { case SET : set_dest = SET_DEST ( set_body ) ; if ( ! set_dest || ! REG_P ( set_dest ) ) return false ; break ; case PARALLEL : for ( i = XVECLEN ( set_body , 0 ) - 1 ; i >= 0 ; i -- ) if ( ix86_dep_by_shift_count_body ( XVECEXP ( set_body , 0 , i ) , use_body ) ) return true ; default : return false ; break ; } switch ( GET_CODE ( use_body ) ) { case SET : shift_rtx = XEXP ( use_body , 1 ) ; break ; case PARALLEL : for ( i = XVECLEN ( use_body , 0 ) - 1 ; i >= 0 ; i -- ) if ( ix86_dep_by_shift_count_body ( set_body , XVECEXP ( use_body , 0 , i ) ) ) return true ; default : return false ; break ; } if ( shift_rtx && ( GET_CODE ( shift_rtx ) == ASHIFT || GET_CODE ( shift_rtx ) == LSHIFTRT || GET_CODE ( shift_rtx ) == ASHIFTRT || GET_CODE ( shift_rtx ) == ROTATE || GET_CODE ( shift_rtx ) == ROTATERT ) ) { rtx shift_count = XEXP ( shift_rtx , 1 ) ; if ( REG_P ( shift_count ) ) { if ( reload_completed && true_regnum ( set_dest ) == true_regnum ( shift_count ) ) return true ; else if ( REGNO ( set_dest ) == REGNO ( shift_count ) ) return true ; } } return false ; } </s>

Return true if destination reg of SET_BODY is shift count of USE_BODY .


<s> bool SIInstrInfo :: shouldClusterMemOps ( ArrayRef < const MachineOperand * > BaseOps1 , ArrayRef < const MachineOperand * > BaseOps2 , unsigned NumLoads , unsigned NumBytes ) const { assert ( ! BaseOps1 . empty ( ) && ! BaseOps2 . empty ( ) ) ; const MachineInstr & FirstLdSt = * BaseOps1 . front ( ) -> getParent ( ) ; const MachineInstr & SecondLdSt = * BaseOps2 . front ( ) -> getParent ( ) ; if ( ! memOpsHaveSameBasePtr ( FirstLdSt , BaseOps1 , SecondLdSt , BaseOps2 ) ) return false ; const unsigned LoadSize = NumBytes / NumLoads ; const unsigned NumDWORDs = ( ( LoadSize + 3 ) / 4 ) * NumLoads ; return NumDWORDs <= 8 ; } </s>

Returns true if the two given memory operations should be scheduled adjacent .


<s> static bool cris_rtx_costs ( rtx x , int code , int outer_code , int opno , int * total , bool speed ) { switch ( code ) { case CONST_INT : { HOST_WIDE_INT val = INTVAL ( x ) ; if ( val == 0 ) * total = 0 ; else if ( val < 32 && val >= - 32 ) * total = 1 ; else if ( val <= 32767 && val >= - 32768 ) * total = 2 ; else * total = 4 ; return true ; } case LABEL_REF : * total = 6 ; return true ; case CONST : case SYMBOL_REF : * total = 6 ; return true ; case CONST_DOUBLE : if ( x != CONST0_RTX ( GET_MODE ( x ) == VOIDmode ? DImode : GET_MODE ( x ) ) ) * total = 12 ; else * total = 0 ; return true ; case MULT : if ( outer_code == PLUS && cris_biap_index_p ( x , false ) ) { * total = 0 ; return true ; } if ( ! CONST_INT_P ( XEXP ( x , 1 ) ) || exact_log2 ( INTVAL ( XEXP ( x , 1 ) ) < 0 ) ) { if ( TARGET_HAS_MUL_INSNS ) { * total = COSTS_N_INSNS ( 1 ) + COSTS_N_INSNS ( 1 ) / 2 ; return true ; } * total = COSTS_N_INSNS ( 132 ) ; return true ; } return false ; case UDIV : case MOD : case UMOD : case DIV : if ( ! CONST_INT_P ( XEXP ( x , 1 ) ) || exact_log2 ( INTVAL ( XEXP ( x , 1 ) ) < 0 ) ) { * total = COSTS_N_INSNS ( 260 ) ; return true ; } return false ; case AND : if ( CONST_INT_P ( XEXP ( x , 1 ) ) && ! CONST_INT_P ( XEXP ( x , 0 ) ) && ! satisfies_constraint_I ( XEXP ( x , 1 ) ) ) { * total = ( rtx_cost ( XEXP ( x , 0 ) , ( enum rtx_code ) outer_code , opno , speed ) + 2 + 2 * GET_MODE_NUNITS ( GET_MODE ( XEXP ( x , 0 ) ) ) ) ; return true ; } return false ; case ZERO_EXTRACT : if ( outer_code != COMPARE ) return false ; case ZERO_EXTEND : case SIGN_EXTEND : * total = rtx_cost ( XEXP ( x , 0 ) , ( enum rtx_code ) outer_code , opno , speed ) ; return true ; default : return false ; } } </s>

Compute a ( partial ) cost for rtx X . Return true if the complete cost has been computed , and false if subexpressions should be scanned . In either case , * TOTAL contains the cost result .


<s> MachineBasicBlock :: iterator MOSFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { int64_t Offset = MI -> getOperand ( 0 ) . getImm ( ) ; if ( hasReservedCallFrame ( MF ) || ! Offset ) return MBB . erase ( MI ) ; MachineIRBuilder Builder ( MBB , MI ) ; if ( MI -> getOpcode ( ) == MF . getSubtarget ( ) . getInstrInfo ( ) -> getCallFrameSetupOpcode ( ) ) Offset = - Offset ; offsetSP ( Builder , Offset ) ; return MBB . erase ( MI ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> EVT PPCTargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return Subtarget . useCRBits ( ) ? MVT :: i1 : MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> MVT getScalarShiftAmountTy ( EVT LHSTy ) const override { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> static void unicosmk_output_externs ( FILE * file ) { struct unicosmk_extern_list * p ; const char * real_name ; int len ; tree name_tree ; len = strlen ( user_label_prefix ) ; for ( p = unicosmk_extern_head ; p != 0 ; p = p -> next ) { real_name = default_strip_name_encoding ( p -> name ) ; if ( len && p -> name [ 0 ] == '*' && ! memcmp ( real_name , user_label_prefix , len ) ) real_name += len ; name_tree = get_identifier ( real_name ) ; if ( ! TREE_ASM_WRITTEN ( name_tree ) ) { TREE_ASM_WRITTEN ( name_tree ) = 1 ; fputs ( "\t.extern\t" , file ) ; assemble_name ( file , p -> name ) ; putc ( '\n' , file ) ; } } } </s>

Output extern declarations for global symbols which are have been referenced but not defined .


<s> bool VLIWResourceModel :: isResourceAvailable ( SUnit * SU ) { if ( ! SU || ! SU -> getInstr ( ) ) return false ; switch ( SU -> getInstr ( ) -> getOpcode ( ) ) { default : if ( ! ResourcesModel -> canReserveResources ( * SU -> getInstr ( ) ) ) return false ; case TargetOpcode :: EXTRACT_SUBREG : case TargetOpcode :: INSERT_SUBREG : case TargetOpcode :: SUBREG_TO_REG : case TargetOpcode :: REG_SEQUENCE : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: COPY : case TargetOpcode :: INLINEASM : break ; } MachineFunction & MF = * SU -> getInstr ( ) -> getParent ( ) -> getParent ( ) ; auto & QII = * MF . getSubtarget < HexagonSubtarget > ( ) . getInstrInfo ( ) ; for ( unsigned i = 0 , e = Packet . size ( ) ; i != e ; ++ i ) { if ( Packet [ i ] -> Succs . size ( ) == 0 ) continue ; if ( QII . mayBeCurLoad ( * Packet [ i ] -> getInstr ( ) ) ) continue ; for ( SUnit :: const_succ_iterator I = Packet [ i ] -> Succs . begin ( ) , E = Packet [ i ] -> Succs . end ( ) ; I != E ; ++ I ) { if ( I -> isCtrl ( ) ) continue ; if ( I -> getSUnit ( ) == SU ) return false ; } } return true ; } </s>

Check if scheduling of this SU is possible in the current packet .


"Patmos DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> TargetPassConfig * AAPTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new AAPPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> const TL45InstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> bool PPCTargetLowering :: hasInlineStackProbe ( MachineFunction & MF ) const { if ( MF . getFunction ( ) . hasFnAttribute ( "probe-stack" ) ) return MF . getFunction ( ) . getFnAttribute ( "probe-stack" ) . getValueAsString ( ) == "inline-asm" ; return false ; } </s>

Returns true if stack probing through inline assembly is requested .

PowerPC PPC "probe-stack" "probe-stack" "inline-asm"


<s> Sched :: Preference ARMTargetLowering :: getSchedulingPreference ( SDNode * N ) const { unsigned NumVals = N -> getNumValues ( ) ; if ( ! NumVals ) return Sched :: RegPressure ; for ( unsigned i = 0 ; i != NumVals ; ++ i ) { EVT VT = N -> getValueType ( i ) ; if ( VT == MVT :: Glue || VT == MVT :: Other ) continue ; if ( VT . isFloatingPoint ( ) || VT . isVector ( ) ) return Sched :: ILP ; } if ( ! N -> isMachineOpcode ( ) ) return Sched :: RegPressure ; const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; const MCInstrDesc & MCID = TII -> get ( N -> getMachineOpcode ( ) ) ; if ( MCID . getNumDefs ( ) == 0 ) return Sched :: RegPressure ; if ( ! Itins -> isEmpty ( ) && Itins -> getOperandCycle ( MCID . getSchedClass ( ) , 0 ) > 2 ) return Sched :: ILP ; return Sched :: RegPressure ; } </s>


<s> bool MSP430TargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { LoadSDNode * LD = cast < LoadSDNode > ( N ) ; if ( LD -> getExtensionType ( ) != ISD :: NON_EXTLOAD ) return false ; EVT VT = LD -> getMemoryVT ( ) ; if ( VT != MVT :: i8 && VT != MVT :: i16 ) return false ; if ( Op -> getOpcode ( ) != ISD :: ADD ) return false ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ) { uint64_t RHSC = RHS -> getZExtValue ( ) ; if ( ( VT == MVT :: i16 && RHSC != 2 ) || ( VT == MVT :: i8 && RHSC != 1 ) ) return false ; Base = Op -> getOperand ( 0 ) ; Offset = DAG . getConstant ( RHSC , VT ) ; AM = ISD :: POST_INC ; return true ; } return false ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> static section * pa_select_section ( tree exp , int reloc , unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED ) { if ( TREE_CODE ( exp ) == VAR_DECL && TREE_READONLY ( exp ) && ! TREE_THIS_VOLATILE ( exp ) && DECL_INITIAL ( exp ) && ( DECL_INITIAL ( exp ) == error_mark_node || TREE_CONSTANT ( DECL_INITIAL ( exp ) ) ) && ! reloc ) { if ( TARGET_SOM && DECL_ONE_ONLY ( exp ) && ! DECL_WEAK ( exp ) ) return som_one_only_readonly_data_section ; else return readonly_data_section ; } else if ( CONSTANT_CLASS_P ( exp ) && ! reloc ) return readonly_data_section ; else if ( TARGET_SOM && TREE_CODE ( exp ) == VAR_DECL && DECL_ONE_ONLY ( exp ) && ! DECL_WEAK ( exp ) ) return som_one_only_data_section ; else return data_section ; } </s>

On hpux10 , the linker will give an error if we have a reference in the read-only data section to a symbol defined in a shared library . Therefore , expressions that might require a reloc can not be placed in the read-only data section .


<s> static unsigned int mips_build_integer ( struct mips_integer_op * codes , unsigned HOST_WIDE_INT value ) { if ( SMALL_OPERAND ( value ) || SMALL_OPERAND_UNSIGNED ( value ) || LUI_OPERAND ( value ) ) { codes [ 0 ] . code = UNKNOWN ; codes [ 0 ] . value = value ; return 1 ; } else if ( ( value & 1 ) != 0 || LUI_OPERAND ( CONST_HIGH_PART ( value ) ) ) { return mips_build_lower ( codes , value ) ; } else if ( ( value & 0xffff ) == 0 ) { return mips_build_shift ( codes , value ) ; } else { struct mips_integer_op alt_codes [ MIPS_MAX_INTEGER_OPS ] ; unsigned int cost , alt_cost ; cost = mips_build_shift ( codes , value ) ; alt_cost = mips_build_lower ( alt_codes , value ) ; if ( alt_cost < cost ) { memcpy ( codes , alt_codes , alt_cost * sizeof ( codes [ 0 ] ) ) ; cost = alt_cost ; } return cost ; } } </s>

Fill CODES with a sequence of rtl operations to load VALUE . Return the number of operations needed .


<s> unsigned SystemZTTIImpl :: getNumberOfRegisters ( unsigned ClassID ) const { bool Vector = ( ClassID == 1 ) ; if ( ! Vector ) return 14 ; if ( ST -> hasVector ( ) ) return 32 ; return 0 ; } </s>


<s> bool ExpandPseudo :: expand ( ) { bool Expanded = false ; for ( auto & MBB : MF ) { for ( Iter I = MBB . begin ( ) , End = MBB . end ( ) ; I != End ; ) Expanded |= expandInstr ( MBB , I ++ ) ; } return Expanded ; } </s>

expand - Expand a record into a set of elements if possible .


<s> rtx shmedia_prepare_call_address ( rtx fnaddr , int is_sibcall ) { int is_sym ; fnaddr = XEXP ( fnaddr , 0 ) ; is_sym = GET_CODE ( fnaddr ) == SYMBOL_REF ; if ( flag_pic && is_sym ) { if ( ! SYMBOL_REF_LOCAL_P ( fnaddr ) ) { rtx reg = gen_reg_rtx ( Pmode ) ; if ( is_sibcall ) emit_insn ( gen_symGOT2reg ( reg , fnaddr ) ) ; else emit_insn ( gen_symGOTPLT2reg ( reg , fnaddr ) ) ; fnaddr = reg ; } else { fnaddr = gen_sym2PIC ( fnaddr ) ; PUT_MODE ( fnaddr , Pmode ) ; } } if ( ! TARGET_PT_FIXED && ( ! is_sym || TARGET_INVALID_SYMBOLS ) && ( ! REG_P ( fnaddr ) || ! TARGET_REGISTER_P ( REGNO ( fnaddr ) ) ) ) { rtx tr = gen_reg_rtx ( PDImode ) ; emit_insn ( gen_ptabs ( tr , fnaddr ) ) ; fnaddr = tr ; } else if ( ! target_reg_operand ( fnaddr , Pmode ) ) fnaddr = copy_to_mode_reg ( Pmode , fnaddr ) ; return fnaddr ; } </s>

FNADDR is the MEM expression from a call expander . Return an address to use in an SHmedia insn pattern .


<s> unsigned FISCRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return FISC :: SP ; } </s>


<s>
unsigned
getPointerSize
(
)
const
{
StringRef
Name
=
TheTarget
.
getName
(
)
;
if
(
Name
==
"ppc64"
||
Name
==
"ppc64le"
)
return
8
;
assert
(
Name
==
"ppc32"
&&
"Unknown target name!"
)
;
return
4
;
}
</s>

Layout pointer size in bytes , rounded up to a whole number of bytes .


<s> void arc_ccfsm_at_label ( const char * prefix , int num ) { if ( arc_ccfsm_state == 3 && arc_ccfsm_target_label == num && ! strcmp ( prefix , "L" ) ) { arc_ccfsm_state = 0 ; arc_ccfsm_target_insn = NULL_RTX ; } } </s>

Record that we are currently outputting label NUM with prefix PREFIX . It it 's the label we 're looking for , reset the ccfsm machinery . Called from ( * targetm.asm_out.internal_label ) .


<s> void rs6000_emit_sCOND ( machine_mode mode , rtx operands [ ] ) { rtx condition_rtx ; machine_mode op_mode ; enum rtx_code cond_code ; rtx result = operands [ 0 ] ; condition_rtx = rs6000_generate_compare ( operands [ 1 ] , mode ) ; cond_code = GET_CODE ( condition_rtx ) ; if ( FLOAT_MODE_P ( mode ) && ! TARGET_FPRS && TARGET_HARD_FLOAT ) { rtx t ; PUT_MODE ( condition_rtx , SImode ) ; t = XEXP ( condition_rtx , 0 ) ; gcc_assert ( cond_code == NE || cond_code == EQ ) ; if ( cond_code == NE ) emit_insn ( gen_e500_flip_gt_bit ( t , t ) ) ; emit_insn ( gen_move_from_CR_gt_bit ( result , t ) ) ; return ; } if ( cond_code == NE || cond_code == GE || cond_code == LE || cond_code == GEU || cond_code == LEU || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE ) { rtx not_result = gen_reg_rtx ( CCEQmode ) ; rtx not_op , rev_cond_rtx ; machine_mode cc_mode ; cc_mode = GET_MODE ( XEXP ( condition_rtx , 0 ) ) ; rev_cond_rtx = gen_rtx_fmt_ee ( rs6000_reverse_condition ( cc_mode , cond_code ) , SImode , XEXP ( condition_rtx , 0 ) , const0_rtx ) ; not_op = gen_rtx_COMPARE ( CCEQmode , rev_cond_rtx , const0_rtx ) ; emit_insn ( gen_rtx_SET ( not_result , not_op ) ) ; condition_rtx = gen_rtx_EQ ( VOIDmode , not_result , const0_rtx ) ; } op_mode = GET_MODE ( XEXP ( operands [ 1 ] , 0 ) ) ; if ( op_mode == VOIDmode ) op_mode = GET_MODE ( XEXP ( operands [ 1 ] , 1 ) ) ; if ( TARGET_POWERPC64 && ( op_mode == DImode || FLOAT_MODE_P ( mode ) ) ) { PUT_MODE ( condition_rtx , DImode ) ; convert_move ( result , condition_rtx , 0 ) ; } else { PUT_MODE ( condition_rtx , SImode ) ; emit_insn ( gen_rtx_SET ( result , condition_rtx ) ) ; } } </s>


<s> bool legitimate_constant_pool_address_p ( const_rtx x , machine_mode mode , bool strict ) { const_rtx tocrel_base , tocrel_offset ; return ( toc_relative_expr_p ( x , strict , & tocrel_base , & tocrel_offset ) && ( TARGET_CMODEL != CMODEL_MEDIUM || constant_pool_expr_p ( XVECEXP ( tocrel_base , 0 , 0 ) ) || mode == QImode || offsettable_ok_by_alignment ( XVECEXP ( tocrel_base , 0 , 0 ) , INTVAL ( tocrel_offset ) , mode ) ) ) ; } </s>

Return true if X is a constant pool address , and also for cmodel=medium if X is a toc-relative address known to be offsettable within MODE .


<s> void emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const override { } </s>


<s>
void
write_fntype_init
(
char
*
str
)
{
char
*
tok
;
int
tf_found
=
strstr
(
str
,
"tf"
)
!=
;
int
dfp_found
=
(
strstr
(
str
,
"dd"
)
!=
||
strstr
(
str
,
"td"
)
!=
||
strstr
(
str
,
"sd"
)
!=
)
;
char
*
buf
=
strdup
(
str
)
;
if
(
tf_found
||
dfp_found
)
fprintf
(
init_file
,
"  tree %s = NULL_TREE;\n"
,
buf
)
;
else
fprintf
(
init_file
,
"  tree "
)
;
if
(
tf_found
)
fprintf
(
init_file
,
"  if (float128_type_node)\n    "
)
;
else
if
(
dfp_found
)
fprintf
(
init_file
,
"  if (dfloat64_type_node)\n    "
)
;
fprintf
(
init_file
,
"%s\n    = build_function_type_list ("
,
buf
)
;
tok
=
strtok
(
buf
,
"_"
)
;
write_type_node
(
tok
,
tf_found
||
dfp_found
)
;
tok
=
strtok
(
0
,
"_"
)
;
assert
(
tok
)
;
assert
(
!
strcmp
(
tok
,
"ftype"
)
)
;
tok
=
strtok
(
0
,
"_"
)
;
if
(
tok
)
fprintf
(
init_file
,
",\n\t\t\t\t"
)
;
while
(
tok
&&
strcmp
(
tok
,
"v"
)
)
{
write_type_node
(
tok
,
tf_found
||
dfp_found
)
;
tok
=
strtok
(
0
,
"_"
)
;
fprintf
(
init_file
,
",\n\t\t\t\t"
)
;
}
fprintf
(
init_file
,
"NULL_TREE);\n"
)
;
free
(
buf
)
;
}
</s>

Write an initializer for a function type identified by STR .


<s> int loongarch_const_insns ( rtx x ) { enum loongarch_symbol_type symbol_type ; rtx offset ; switch ( GET_CODE ( x ) ) { case CONST_INT : return loongarch_integer_cost ( INTVAL ( x ) ) ; case CONST_VECTOR : case CONST_DOUBLE : return x == CONST0_RTX ( GET_MODE ( x ) ) ? 1 : 0 ; case CONST : if ( loongarch_symbolic_constant_p ( x , & symbol_type ) ) return loongarch_symbol_insns ( symbol_type , MAX_MACHINE_MODE ) ; split_const ( x , & x , & offset ) ; if ( offset != 0 ) { int n = loongarch_const_insns ( x ) ; if ( n != 0 ) { if ( IMM12_INT ( offset ) ) return n + 1 ; else if ( ! targetm . cannot_force_const_mem ( GET_MODE ( x ) , x ) ) return n + 1 + loongarch_integer_cost ( INTVAL ( offset ) ) ; } } return 0 ; case SYMBOL_REF : case LABEL_REF : return loongarch_symbol_insns ( loongarch_classify_symbol ( x ) , MAX_MACHINE_MODE ) ; default : return 0 ; } } </s>

Return the number of instructions needed to load constant X , Return 0 if X is n't a valid constant .


<s>
void
JVMDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
LLVM_DEBUG
(
errs
(
)
<<
"Selecting: "
)
;
LLVM_DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
LLVM_DEBUG
(
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
EVT
VT
=
Node
->
getValueType
(
0
)
;
switch
(
Node
->
getOpcode
(
)
)
{
default
:
break
;
(
void
)
VT
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

JVM
JVM
"Selecting: "
"\n"
"== "
"\n"
1
0


<s> std :: string getNodeLabel ( NodeRef Node , GraphType * ) { if ( Node -> getValue ( ) == MachineGadgetGraph :: ArgNodeSentinel ) return "ARGS" ; std :: string Str ; raw_string_ostream OS ( Str ) ; OS << * Node -> getValue ( ) ; return OS . str ( ) ; } </s>

Print a DDG node either in concise form ( -ddg-dot-only ) or verbose mode ( -ddg-dot ) .


<s> const MCPhysReg * P2RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_SaveList ; } </s>


<s> void DLXInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator Position , unsigned DestinationRegister , int FrameIndex , const TargetRegisterClass * RegisterClass , const TargetRegisterInfo * RegisterInfo ) const { } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> static int compute_cpymem_length ( rtx_insn * insn ) { rtx pat = PATTERN ( insn ) ; unsigned int align = INTVAL ( XEXP ( XVECEXP ( pat , 0 , 7 ) , 0 ) ) ; unsigned long n_bytes = INTVAL ( XEXP ( XVECEXP ( pat , 0 , 6 ) , 0 ) ) ; unsigned int n_insns = 0 ; if ( align > ( TARGET_64BIT ? 8 : 4 ) ) align = ( TARGET_64BIT ? 8 : 4 ) ; n_insns = 6 ; if ( n_bytes % ( 2 * align ) != 0 ) { if ( ( n_bytes % ( 2 * align ) ) >= align ) n_insns += 2 ; if ( ( n_bytes % align ) != 0 ) n_insns += 2 ; } return n_insns * 4 ; } </s>

Count the number of insns necessary to handle this block move . Basic structure is the same as emit_block_move , except that we count insns rather than emit them .


<s> bool mep_vliw_function_p ( tree decl ) { return lookup_attribute ( "vliw" , TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ) != 0 ; } </s>

Return true if function DECL was declared with the vliw attribute .


<s> const M680x0RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool SITargetLowering :: canMergeStoresTo ( unsigned AS , EVT MemVT , const MachineFunction & MF ) const { if ( AS == AMDGPUAS :: GLOBAL_ADDRESS || AS == AMDGPUAS :: FLAT_ADDRESS ) { return ( MemVT . getSizeInBits ( ) <= 4 * 32 ) ; } else if ( AS == AMDGPUAS :: PRIVATE_ADDRESS ) { unsigned MaxPrivateBits = 8 * getSubtarget ( ) -> getMaxPrivateElementSize ( ) ; return ( MemVT . getSizeInBits ( ) <= MaxPrivateBits ) ; } else if ( AS == AMDGPUAS :: LOCAL_ADDRESS || AS == AMDGPUAS :: REGION_ADDRESS ) { return ( MemVT . getSizeInBits ( ) <= 2 * 32 ) ; } return true ; } </s>

Returns if it 's reasonable to merge stores to MemVT size .


<s> EVT AArch64TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { bool Fast ; const Function * F = MF . getFunction ( ) ; if ( Subtarget -> hasFPARMv8 ( ) && ! IsMemset && Size >= 16 && ! F -> hasFnAttribute ( Attribute :: NoImplicitFloat ) && ( memOpAlign ( SrcAlign , DstAlign , 16 ) || ( allowsMisalignedMemoryAccesses ( MVT :: f128 , 0 , 1 , & Fast ) && Fast ) ) ) return MVT :: f128 ; return Size >= 8 ? MVT :: i64 : MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> bool VETargetLowering :: hasAndNot ( SDValue Y ) const { EVT VT = Y . getValueType ( ) ; if ( VT . isVector ( ) ) return false ; if ( isa < ConstantSDNode > ( Y ) ) return false ; return true ; } </s>

Return true if the target has a bitwise and-not operation : X = ~A & B This can be used to simplify select or other instructions .


<s> int HexagonInstrInfo :: getOperandLatency ( const InstrItineraryData * ItinData , const MachineInstr & DefMI , unsigned DefIdx , const MachineInstr & UseMI , unsigned UseIdx ) const { const MachineFunction & MF = * DefMI . getParent ( ) -> getParent ( ) ; const auto & HRI = * MF . getSubtarget < HexagonSubtarget > ( ) . getRegisterInfo ( ) ; MachineOperand DefMO = DefMI . getOperand ( DefIdx ) ; if ( HRI . isPhysicalRegister ( DefMO . getReg ( ) ) ) { if ( DefMO . isImplicit ( ) ) { for ( MCSuperRegIterator SR ( DefMO . getReg ( ) , & HRI ) ; SR . isValid ( ) ; ++ SR ) { int Idx = DefMI . findRegisterDefOperandIdx ( * SR , false , false , & HRI ) ; if ( Idx != - 1 ) { DefIdx = Idx ; break ; } } } MachineOperand UseMO = UseMI . getOperand ( UseIdx ) ; if ( UseMO . isImplicit ( ) ) { for ( MCSuperRegIterator SR ( UseMO . getReg ( ) , & HRI ) ; SR . isValid ( ) ; ++ SR ) { int Idx = UseMI . findRegisterUseOperandIdx ( * SR , false , & HRI ) ; if ( Idx != - 1 ) { UseIdx = Idx ; break ; } } } } return TargetInstrInfo :: getOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ; } </s>

Compute and return the use operand latency of a given pair of def and use .


<s> static void arm_insert_attributes ( tree fndecl , tree * attributes ) { const char * mode ; if ( ! TARGET_FLIP_THUMB ) return ; if ( TREE_CODE ( fndecl ) != FUNCTION_DECL || DECL_EXTERNAL ( fndecl ) || fndecl_built_in_p ( fndecl ) || DECL_ARTIFICIAL ( fndecl ) ) return ; if ( current_function_decl ) { mode = TARGET_THUMB ? "thumb" : "arm" ; add_attribute ( mode , attributes ) ; return ; } if ( lookup_attribute ( "target" , * attributes ) != NULL ) return ; mode = thumb_flipper ? "thumb" : "arm" ; add_attribute ( mode , attributes ) ; thumb_flipper = ! thumb_flipper ; } </s>

For testing . Insert thumb or arm modes alternatively on functions .

arm "thumb" "arm" "target" "thumb" "arm"


<s> static machine_mode riscv_promote_function_mode ( const_tree type ATTRIBUTE_UNUSED , machine_mode mode , int * punsignedp ATTRIBUTE_UNUSED , const_tree fntype ATTRIBUTE_UNUSED , int for_return ATTRIBUTE_UNUSED ) { int unsignedp ; if ( type != NULL_TREE ) return promote_mode ( type , mode , punsignedp ) ; unsignedp = * punsignedp ; PROMOTE_MODE ( mode , unsignedp , type ) ; * punsignedp = unsignedp ; return mode ; } </s>


<s>
void
Z80oldRegisterInfo
::
resolveFrameIndex
(
MachineInstr
&
MI
,
unsigned
BaseReg
,
int64_t
Offset
)
const
{
unsigned
FIOperandNum
=
0
;
while
(
!
MI
.
getOperand
(
FIOperandNum
)
.
isFI
(
)
)
{
FIOperandNum
++
;
assert
(
FIOperandNum
<
MI
.
getNumOperands
(
)
&&
"Expected a frame index"
)
;
}
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
BaseReg
,
false
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
+
Offset
)
;
}
</s>

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"MBlaze Delay Slot Filler"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"Cannot store this register to stack slot!"

Store the specified register of the given register class to the specified stack frame index .


<s>
bool
AArch64AdvSIMDScalar
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
bool
Changed
=
false
;
DEBUG
(
dbgs
(
)
<<
"***** AArch64AdvSIMDScalar *****\n"
)
;
const
TargetMachine
&
TM
=
mf
.
getTarget
(
)
;
MRI
=
&
mf
.
getRegInfo
(
)
;
TII
=
static_cast
<
const
AArch64InstrInfo
*
>
(
TM
.
getSubtargetImpl
(
)
->
getInstrInfo
(
)
)
;
for
(
MachineFunction
::
iterator
I
=
mf
.
begin
(
)
,
E
=
mf
.
end
(
)
;
I
!=
E
;
++
I
)
if
(
processMachineBasicBlock
(
I
)
)
Changed
=
true
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static bool arm_block_set_unaligned_non_vect ( rtx dstbase , unsigned HOST_WIDE_INT length , unsigned HOST_WIDE_INT value , unsigned HOST_WIDE_INT align ) { unsigned int i ; rtx dst , addr , mem ; rtx val_exp , val_reg , reg ; machine_mode mode ; HOST_WIDE_INT v = value ; gcc_assert ( align == 1 || align == 2 ) ; if ( align == 2 ) v |= ( value << BITS_PER_UNIT ) ; v = sext_hwi ( v , BITS_PER_WORD ) ; val_exp = GEN_INT ( v ) ; if ( ! arm_block_set_non_vect_profit_p ( val_exp , length , align , true , false ) ) return false ; dst = copy_addr_to_reg ( XEXP ( dstbase , 0 ) ) ; mode = ( align == 2 ? HImode : QImode ) ; val_reg = force_reg ( SImode , val_exp ) ; reg = gen_lowpart ( mode , val_reg ) ; for ( i = 0 ; ( i + GET_MODE_SIZE ( mode ) <= length ) ; i += GET_MODE_SIZE ( mode ) ) { addr = plus_constant ( Pmode , dst , i ) ; mem = adjust_automodify_address ( dstbase , mode , addr , i ) ; emit_move_insn ( mem , reg ) ; } if ( i + 1 == length ) { reg = gen_lowpart ( QImode , val_reg ) ; addr = plus_constant ( Pmode , dst , i ) ; mem = adjust_automodify_address ( dstbase , QImode , addr , i ) ; emit_move_insn ( mem , reg ) ; i ++ ; } gcc_assert ( i == length ) ; return true ; } </s>

Set a block of memory using plain strh/strb instructions , only using instructions allowed by ALIGN on processor . We fill the first LENGTH bytes of the memory area starting from DSTBASE with byte constant VALUE . ALIGN is the alignment requirement of memory .


<s> bool GCNTTIImpl :: rewriteIntrinsicWithAddressSpace ( IntrinsicInst * II , Value * OldV , Value * NewV ) const { switch ( II -> getIntrinsicID ( ) ) { case Intrinsic :: amdgcn_atomic_inc : case Intrinsic :: amdgcn_atomic_dec : case Intrinsic :: amdgcn_ds_fadd : case Intrinsic :: amdgcn_ds_fmin : case Intrinsic :: amdgcn_ds_fmax : { const ConstantInt * IsVolatile = cast < ConstantInt > ( II -> getArgOperand ( 4 ) ) ; if ( ! IsVolatile -> isZero ( ) ) return false ; Module * M = II -> getParent ( ) -> getParent ( ) -> getParent ( ) ; Type * DestTy = II -> getType ( ) ; Type * SrcTy = NewV -> getType ( ) ; Function * NewDecl = Intrinsic :: getDeclaration ( M , II -> getIntrinsicID ( ) , { DestTy , SrcTy } ) ; II -> setArgOperand ( 0 , NewV ) ; II -> setCalledFunction ( NewDecl ) ; return true ; } default : return false ; } } </s>

Rewrite intrinsic call II such that OldV will be replaced with NewV , which has a different address space .


"calling %qD with attribute sseregparm without "

"calling %qT with attribute sseregparm without "

"calling %qD with SSE caling convention without "

Return 1 or 2 , if we can pass up to SSE_REGPARM_MAX SFmode ( 1 ) and DFmode ( 2 ) arguments in SSE registers for a function with the indicated TYPE and DECL . DECL may be NULL when calling function indirectly or considering a libcall . Otherwise return 0 .


<s> static bool convertible_comparison_p ( rtx_insn * insn , enum machine_mode mode ) { if ( mode != ( TARGET_64BIT ? TImode : DImode ) ) return false ; if ( ! TARGET_SSE4_1 ) return false ; rtx def_set = single_set ( insn ) ; gcc_assert ( def_set ) ; rtx src = SET_SRC ( def_set ) ; rtx dst = SET_DEST ( def_set ) ; gcc_assert ( GET_CODE ( src ) == COMPARE ) ; if ( GET_CODE ( dst ) != REG || REGNO ( dst ) != FLAGS_REG || GET_MODE ( dst ) != CCZmode ) return false ; rtx op1 = XEXP ( src , 0 ) ; rtx op2 = XEXP ( src , 1 ) ; if ( ( CONST_SCALAR_INT_P ( op1 ) || ( ( REG_P ( op1 ) || MEM_P ( op1 ) ) && GET_MODE ( op1 ) == mode ) ) && ( CONST_SCALAR_INT_P ( op2 ) || ( ( REG_P ( op2 ) || MEM_P ( op2 ) ) && GET_MODE ( op2 ) == mode ) ) ) return true ; if ( op2 == const0_rtx && GET_CODE ( op1 ) == AND && REG_P ( XEXP ( op1 , 0 ) ) ) { rtx op12 = XEXP ( op1 , 1 ) ; return GET_MODE ( XEXP ( op1 , 0 ) ) == TImode && ( CONST_SCALAR_INT_P ( op12 ) || ( ( REG_P ( op12 ) || MEM_P ( op12 ) ) && GET_MODE ( op12 ) == TImode ) ) ; } if ( op2 == const0_rtx && GET_CODE ( op1 ) == AND && GET_CODE ( XEXP ( op1 , 0 ) ) == NOT ) { rtx op11 = XEXP ( XEXP ( op1 , 0 ) , 0 ) ; rtx op12 = XEXP ( op1 , 1 ) ; return ( REG_P ( op11 ) || MEM_P ( op11 ) ) && ( REG_P ( op12 ) || MEM_P ( op12 ) ) && GET_MODE ( op11 ) == mode && GET_MODE ( op12 ) == mode ; } return false ; } </s>

Check if comparison INSN may be transformed into vector comparison . Currently we transform equality/inequality checks which look like : ( set ( reg : CCZ 17 flags ) ( compare : CCZ ( reg : TI x ) ( reg : TI y ) ) )


<s> unsigned R600InstrInfo :: isLegalUpTo ( const std :: vector < std :: vector < std :: pair < int , unsigned > > > & IGSrcs , const std :: vector < R600InstrInfo :: BankSwizzle > & Swz , const std :: vector < std :: pair < int , unsigned > > & TransSrcs , R600InstrInfo :: BankSwizzle TransSwz ) const { int Vector [ 4 ] [ 3 ] ; memset ( Vector , - 1 , sizeof ( Vector ) ) ; for ( unsigned i = 0 , e = IGSrcs . size ( ) ; i < e ; i ++ ) { const std :: vector < std :: pair < int , unsigned > > & Srcs = Swizzle ( IGSrcs [ i ] , Swz [ i ] ) ; for ( unsigned j = 0 ; j < 3 ; j ++ ) { const std :: pair < int , unsigned > & Src = Srcs [ j ] ; if ( Src . first < 0 || Src . first == 255 ) continue ; if ( Src . first == GET_REG_INDEX ( RI . getEncodingValue ( AMDGPU :: OQAP ) ) ) { if ( Swz [ i ] != R600InstrInfo :: ALU_VEC_012_SCL_210 && Swz [ i ] != R600InstrInfo :: ALU_VEC_021_SCL_122 ) { return false ; } continue ; } if ( Vector [ Src . second ] [ j ] < 0 ) Vector [ Src . second ] [ j ] = Src . first ; if ( Vector [ Src . second ] [ j ] != Src . first ) return i ; } } for ( unsigned i = 0 , e = TransSrcs . size ( ) ; i < e ; ++ i ) { const std :: pair < int , unsigned > & Src = TransSrcs [ i ] ; unsigned Cycle = getTransSwizzle ( TransSwz , i ) ; if ( Src . first < 0 ) continue ; if ( Src . first == 255 ) continue ; if ( Vector [ Src . second ] [ Cycle ] < 0 ) Vector [ Src . second ] [ Cycle ] = Src . first ; if ( Vector [ Src . second ] [ Cycle ] != Src . first ) return IGSrcs . size ( ) - 1 ; } return IGSrcs . size ( ) ; } </s>

returns how many MIs ( whose inputs are represented by IGSrcs ) can be packed in the same Instruction Group while meeting read port limitations given a Swz swizzle sequence .


<s> bool ARMSubtarget :: enablePostRAScheduler ( ) const { if ( enableMachineScheduler ( ) ) return false ; if ( disablePostRAScheduler ( ) ) return false ; return ! isThumb1Only ( ) ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s>
void
dump
(
SelectionDAG
*
DAG
=
nullptr
)
{
dbgs
(
)
<<
"X86ISelAddressMode "
<<
this
<<
'\n'
;
dbgs
(
)
<<
"Base_Reg "
;
if
(
Base_Reg
.
getNode
(
)
)
Base_Reg
.
getNode
(
)
->
dump
(
DAG
)
;
else
dbgs
(
)
<<
"nul\n"
;
if
(
BaseType
==
FrameIndexBase
)
dbgs
(
)
<<
" Base.FrameIndex "
<<
Base_FrameIndex
<<
'\n'
;
dbgs
(
)
<<
" Scale "
<<
Scale
<<
'\n'
<<
"IndexReg "
;
if
(
NegateIndex
)
dbgs
(
)
<<
"negate "
;
if
(
IndexReg
.
getNode
(
)
)
IndexReg
.
getNode
(
)
->
dump
(
DAG
)
;
else
dbgs
(
)
<<
"nul\n"
;
dbgs
(
)
<<
" Disp "
<<
Disp
<<
'\n'
<<
"GV "
;
if
(
GV
)
GV
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" CP "
;
if
(
CP
)
CP
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
'\n'
<<
"ES "
;
if
(
ES
)
dbgs
(
)
<<
ES
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" MCSym "
;
if
(
MCSym
)
dbgs
(
)
<<
MCSym
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" JT"
<<
JT
<<
" Align"
<<
Alignment
.
value
(
)
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

X86
"X86ISelAddressMode "
"Base_Reg "
"nul\n"
" Base.FrameIndex "
" Scale "
"IndexReg "
"negate "
"nul\n"
" Disp "
"GV "
"nul"
" CP "
"nul"
"ES "
"nul"
" MCSym "
"nul"
" JT"
" Align"


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> virtual const ARMFrameInfo * getFrameInfo ( ) const { return FrameInfo . get ( ) ; } </s>

getFrameInfo - Return the frame info object for the current function .


<s> Value * AArch64TargetLowering :: getSDagStackGuard ( const Module & M ) const { if ( Subtarget -> getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) ) return M . getGlobalVariable ( "__security_cookie" ) ; return TargetLowering :: getSDagStackGuard ( M ) ; } </s>

Return the variable that 's previously inserted by insertSSPDeclarations , if any , otherwise return nullptr .


Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> static unsigned int insn_is_store_p ( rtx insn ) { rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) == SET && GET_CODE ( SET_DEST ( body ) ) == MEM ) return 1 ; if ( GET_CODE ( body ) != PARALLEL ) return 0 ; rtx set = XVECEXP ( body , 0 , 0 ) ; if ( GET_CODE ( set ) == SET && GET_CODE ( SET_DEST ( set ) ) == MEM ) return 1 ; return 0 ; } </s>

Return 1 iff INSN is a store insn , including permuting stores that represent an stvxd2x instruction ; else return 0 .


<s> virtual void addBlockPlacement ( ) { } </s>

Add standard basic block placement passes .


<s>
void
ATTRIBUTE_UNUSED
ix86_debug_options
(
void
)
{
char
*
opts
=
ix86_target_string
(
ix86_isa_flags
,
ix86_isa_flags2
,
target_flags
,
ix86_target_flags
,
ix86_arch_string
,
ix86_tune_string
,
ix86_fpmath
,
prefer_vector_width_type
,
ix86_move_max
,
ix86_store_max
,
true
,
true
)
;
if
(
opts
)
{
fprintf
(
stderr
,
"%s\n\n"
,
opts
)
;
free
(
opts
)
;
}
else
fputs
(
"<no options>\n\n"
,
stderr
)
;
return
;
}
</s>

Function that is callable from the debugger to print the current options .


<s> bool runOnFunction ( Function & F ) override { this -> F = & F ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; bool Changed = false ; for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L = df_begin ( * I ) , LE = df_end ( * I ) ; L != LE ; ++ L ) Changed |= runOnLoop ( * L ) ; return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static int sched_get_indexed_address_scale ( rtx_insn * pro , rtx_insn * con ) { rtx reg ; rtx mem ; struct m68k_address address ; reg = sched_get_reg_operand ( pro , true ) ; if ( reg == NULL ) return 0 ; mem = sched_get_mem_operand ( con , true , false ) ; gcc_assert ( mem != NULL && MEM_P ( mem ) ) ; if ( ! m68k_decompose_address ( GET_MODE ( mem ) , XEXP ( mem , 0 ) , reload_completed , & address ) ) gcc_unreachable ( ) ; if ( REGNO ( reg ) == REGNO ( address . index ) ) { gcc_assert ( address . scale != 0 ) ; return address . scale ; } return 0 ; } </s>

Helper function for m68k_sched_indexed_address_bypass_p . if PRO modifies register used as index in CON , return scale of indexed memory access in CON . Return zero overwise .


<s> static rtx c6x_dwarf_register_span ( rtx rtl ) { unsigned regno ; unsigned real_regno ; int nregs ; int i ; rtx p ; regno = REGNO ( rtl ) ; nregs = REG_NREGS ( rtl ) ; if ( nregs == 1 ) return NULL_RTX ; p = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nregs ) ) ; for ( i = 0 ; i < nregs ; i ++ ) { if ( TARGET_BIG_ENDIAN ) real_regno = regno + nregs - ( i + 1 ) ; else real_regno = regno + i ; XVECEXP ( p , 0 , i ) = gen_rtx_REG ( SImode , real_regno ) ; } return p ; } </s>

We save pairs of registers using a DImode store . Describe the component registers for DWARF generation code .


<s> virtual void initializePass ( ) { pushTTIStack ( this ) ; } </s>

initializePass - This method may be overriden by immutable passes to allow them to perform various initialization actions they require .


<s> void SITargetLowering :: AdjustInstrPostInstrSelection ( MachineInstr * MI , SDNode * Node ) const { const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; TII -> legalizeOperands ( MI ) ; if ( TII -> isMIMG ( MI -> getOpcode ( ) ) ) { unsigned VReg = MI -> getOperand ( 0 ) . getReg ( ) ; unsigned Writemask = MI -> getOperand ( 1 ) . getImm ( ) ; unsigned BitsSet = 0 ; for ( unsigned i = 0 ; i < 4 ; ++ i ) BitsSet += Writemask & ( 1 << i ) ? 1 : 0 ; const TargetRegisterClass * RC ; switch ( BitsSet ) { default : return ; case 1 : RC = & AMDGPU :: VGPR_32RegClass ; break ; case 2 : RC = & AMDGPU :: VReg_64RegClass ; break ; case 3 : RC = & AMDGPU :: VReg_96RegClass ; break ; } unsigned NewOpcode = TII -> getMaskedMIMGOp ( MI -> getOpcode ( ) , BitsSet ) ; MI -> setDesc ( TII -> get ( NewOpcode ) ) ; MRI . setRegClass ( VReg , RC ) ; return ; } int NoRetAtomicOp = AMDGPU :: getAtomicNoRetOp ( MI -> getOpcode ( ) ) ; if ( NoRetAtomicOp != - 1 ) { if ( ! Node -> hasAnyUseOfValue ( 0 ) ) { MI -> setDesc ( TII -> get ( NoRetAtomicOp ) ) ; MI -> RemoveOperand ( 0 ) ; } return ; } } </s>

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


<s> bool null_epilogue ( ) { int i ; if ( ! reload_completed ) return false ; if ( frame_pointer_needed ) return false ; if ( get_frame_size ( ) ) return false ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { if ( df_regs_ever_live_p ( i ) && ! call_used_regs [ i ] ) return false ; } return true ; } </s>

return 1 if there is n't anything tricky to do


<s> static tree mips_std_gimplify_va_arg_expr ( tree valist , tree type , gimple_seq * pre_p , gimple_seq * post_p ) { tree addr , t , type_size , rounded_size , valist_tmp ; unsigned HOST_WIDE_INT align , boundary ; bool indirect ; indirect = pass_va_arg_by_reference ( type ) ; if ( indirect ) type = build_pointer_type ( type ) ; align = PARM_BOUNDARY / BITS_PER_UNIT ; boundary = targetm . calls . function_arg_boundary ( TYPE_MODE ( type ) , type ) ; if ( boundary > MAX_SUPPORTED_STACK_ALIGNMENT ) boundary = MAX_SUPPORTED_STACK_ALIGNMENT ; boundary /= BITS_PER_UNIT ; valist_tmp = get_initialized_tmp_var ( valist , pre_p , NULL ) ; if ( boundary > align ) { t = build2 ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist_tmp , fold_build_pointer_plus_hwi ( valist_tmp , boundary - 1 ) ) ; gimplify_and_add ( t , pre_p ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist_tmp , fold_build2 ( BIT_AND_EXPR , TREE_TYPE ( valist ) , valist_tmp , build_int_cst ( TREE_TYPE ( valist ) , - boundary ) ) ) ; gimplify_and_add ( t , pre_p ) ; } else boundary = align ; boundary *= BITS_PER_UNIT ; if ( boundary < TYPE_ALIGN ( type ) ) { type = build_variant_type_copy ( type ) ; SET_TYPE_ALIGN ( type , boundary ) ; } type_size = size_in_bytes ( type ) ; rounded_size = round_up ( type_size , align ) ; gimplify_expr ( & rounded_size , pre_p , post_p , is_gimple_val , fb_rvalue ) ; addr = valist_tmp ; if ( PAD_VARARGS_DOWN && ! integer_zerop ( rounded_size ) ) { t = fold_build2_loc ( input_location , GT_EXPR , sizetype , rounded_size , size_int ( align ) ) ; t = fold_build3 ( COND_EXPR , sizetype , t , size_zero_node , size_binop ( MINUS_EXPR , rounded_size , type_size ) ) ; addr = fold_build_pointer_plus ( addr , t ) ; } t = fold_build_pointer_plus ( valist_tmp , rounded_size ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist , t ) ; gimplify_and_add ( t , pre_p ) ; addr = fold_convert ( build_pointer_type ( type ) , addr ) ; if ( indirect ) addr = build_va_arg_indirect_ref ( addr ) ; return build_va_arg_indirect_ref ( addr ) ; } </s>

Like std_gimplify_va_arg_expr , but apply alignment to zero-sized types as well .


"Instruction should be in a basic block!"

"Generic instruction has unexpected implicit operands\n"

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s> void NyuziMCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { ++ MCNumEmitted ; unsigned Value = getBinaryCodeForInstr ( MI , Fixups , STI ) ; EmitLEConstant ( Value , 4 , OS ) ; } </s>

Encode the given Inst to bytes and append to CB .


"const enum insn_code %s_multiply_insn_seq_decode_opcode[] = {\n"

"  CODE_FOR_nothing /* must be first */ "

For each insn_code used by an operator , choose a compact number so it takes less space in the output data structure . This prints out a lookup table used to map the compactified number back to an insn_code .


<s> bool Cpu0RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> bool SPIRVPassConfig :: addLegalizeMachineIR ( ) { addPass ( new Legalizer ( ) ) ; return false ; } </s>

This method should install a legalize pass , which converts the instruction sequence into one that can be selected by the target .


<s> static bool tryAddingSymbolicOperand ( int64_t Value , bool isBranch , uint64_t Address , uint64_t Offset , uint64_t Width , MCInst & MI , const void * Decoder ) { const MCDisassembler * Dis = static_cast < const MCDisassembler * > ( Decoder ) ; return Dis -> tryAddingSymbolicOperand ( MI , Value , Address , isBranch , Offset , Width ) ; } </s>

Try to add a symbolic operand instead of Value to the MCInst .


<s> bool MBlazeSubtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = TargetSubtargetInfo :: ANTIDEP_CRITICAL ; CriticalPathRCs . clear ( ) ; CriticalPathRCs . push_back ( & MBlaze :: GPRRegClass ) ; return HasItin && OptLevel >= CodeGenOpt :: Default ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s> bool nds32_n9_3r2w_mm_to_ex_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx def_reg ; switch ( get_attr_type ( producer ) ) { case TYPE_LOAD : case TYPE_MUL : case TYPE_MAC : def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; case TYPE_DIV : if ( INSN_CODE ( producer ) == CODE_FOR_divmodsi4 || INSN_CODE ( producer ) == CODE_FOR_udivmodsi4 ) { rtx def_reg1 = SET_DEST ( parallel_element ( producer , 0 ) ) ; rtx def_reg2 = SET_DEST ( parallel_element ( producer , 1 ) ) ; return ( n9_3r2w_consumed_by_ex_dep_p ( consumer , def_reg1 ) || n9_3r2w_consumed_by_ex_dep_p ( consumer , def_reg2 ) ) ; } def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; default : gcc_unreachable ( ) ; } return n9_3r2w_consumed_by_ex_dep_p ( consumer , def_reg ) ; } </s>


<s> bool AArch64TargetLowering :: isUsedByReturnOnly ( SDNode * N , SDValue & Chain ) const { if ( N -> getNumValues ( ) != 1 ) return false ; if ( ! N -> hasNUsesOfValue ( 1 , 0 ) ) return false ; SDValue TCChain = Chain ; SDNode * Copy = * N -> use_begin ( ) ; if ( Copy -> getOpcode ( ) == ISD :: CopyToReg ) { if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - 1 ) . getValueType ( ) == MVT :: Glue ) return false ; TCChain = Copy -> getOperand ( 0 ) ; } else if ( Copy -> getOpcode ( ) != ISD :: FP_EXTEND ) return false ; bool HasRet = false ; for ( SDNode * Node : Copy -> uses ( ) ) { if ( Node -> getOpcode ( ) != AArch64ISD :: RET_FLAG ) return false ; HasRet = true ; } if ( ! HasRet ) return false ; Chain = TCChain ; return true ; } </s>

Return true if result of the specified node is used by a return node only .


<s> unsigned getNumberOfRegisters ( bool Vector ) { if ( Vector ) { if ( ST -> hasNEON ( ) ) return 16 ; return 0 ; } if ( ST -> isThumb1Only ( ) ) return 8 ; return 13 ; } </s>


<s>
static
bool
rs6000_declare_alias
(
struct
symtab_node
*
n
,
void
*
d
)
{
struct
declare_alias_data
*
data
=
(
struct
declare_alias_data
*
)
d
;
if
(
!
n
->
alias
||
n
->
weakref
)
return
false
;
if
(
lookup_attribute
(
"ifunc"
,
DECL_ATTRIBUTES
(
n
->
decl
)
)
)
return
false
;
TREE_ASM_WRITTEN
(
n
->
decl
)
=
true
;
const
char
*
name
=
IDENTIFIER_POINTER
(
DECL_ASSEMBLER_NAME
(
n
->
decl
)
)
;
char
*
buffer
=
(
char
*
)
alloca
(
strlen
(
name
)
+
2
)
;
char
*
p
;
int
dollar_inside
=
0
;
strcpy
(
buffer
,
name
)
;
p
=
strchr
(
buffer
,
'$'
)
;
while
(
p
)
{
*
p
=
'_'
;
dollar_inside
++
;
p
=
strchr
(
p
+
1
,
'$'
)
;
}
if
(
TREE_PUBLIC
(
n
->
decl
)
)
{
if
(
!
RS6000_WEAK
||
!
DECL_WEAK
(
n
->
decl
)
)
{
if
(
dollar_inside
)
{
if
(
data
->
function_descriptor
)
fprintf
(
data
->
file
,
"\t.rename .%s,\".%s\"\n"
,
buffer
,
name
)
;
fprintf
(
data
->
file
,
"\t.rename %s,\"%s\"\n"
,
buffer
,
name
)
;
}
if
(
data
->
function_descriptor
)
{
fputs
(
"\t.globl ."
,
data
->
file
)
;
RS6000_OUTPUT_BASENAME
(
data
->
file
,
buffer
)
;
putc
(
'\n'
,
data
->
file
)
;
}
fputs
(
"\t.globl "
,
data
->
file
)
;
assemble_name
(
data
->
file
,
buffer
)
;
putc
(
'\n'
,
data
->
file
)
;
}
else
if
(
DECL_WEAK
(
n
->
decl
)
&&
!
data
->
function_descriptor
)
ASM_WEAKEN_DECL
(
data
->
file
,
n
->
decl
,
name
,
)
;
}
else
{
if
(
dollar_inside
)
{
if
(
data
->
function_descriptor
)
fprintf
(
data
->
file
,
"\t.rename .%s,\".%s\"\n"
,
buffer
,
name
)
;
fprintf
(
data
->
file
,
"\t.rename %s,\"%s\"\n"
,
buffer
,
name
)
;
}
if
(
data
->
function_descriptor
)
{
fputs
(
"\t.lglobl ."
,
data
->
file
)
;
RS6000_OUTPUT_BASENAME
(
data
->
file
,
buffer
)
;
putc
(
'\n'
,
data
->
file
)
;
}
fputs
(
"\t.lglobl "
,
data
->
file
)
;
assemble_name
(
data
->
file
,
buffer
)
;
putc
(
'\n'
,
data
->
file
)
;
}
if
(
data
->
function_descriptor
)
putc
(
'.'
,
data
->
file
)
;
ASM_OUTPUT_LABEL
(
data
->
file
,
buffer
)
;
return
false
;
}
</s>

Declare alias N. A helper function for for_node_and_aliases .


<s> static int arm_save_coproc_regs ( void ) { int saved_size = 0 ; unsigned reg ; unsigned start_reg ; rtx insn ; for ( reg = LAST_IWMMXT_REGNUM ; reg >= FIRST_IWMMXT_REGNUM ; reg -- ) if ( df_regs_ever_live_p ( reg ) && ! call_used_regs [ reg ] ) { insn = gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ; insn = gen_rtx_MEM ( V2SImode , insn ) ; insn = emit_set_insn ( insn , gen_rtx_REG ( V2SImode , reg ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; saved_size += 8 ; } if ( TARGET_HARD_FLOAT ) { start_reg = FIRST_VFP_REGNUM ; for ( reg = FIRST_VFP_REGNUM ; reg < LAST_VFP_REGNUM ; reg += 2 ) { if ( ( ! df_regs_ever_live_p ( reg ) || call_used_regs [ reg ] ) && ( ! df_regs_ever_live_p ( reg + 1 ) || call_used_regs [ reg + 1 ] ) ) { if ( start_reg != reg ) saved_size += vfp_emit_fstmd ( start_reg , ( reg - start_reg ) / 2 ) ; start_reg = reg + 2 ; } } if ( start_reg != reg ) saved_size += vfp_emit_fstmd ( start_reg , ( reg - start_reg ) / 2 ) ; } return saved_size ; } </s>

Emit RTL to save coprocessor registers on function entry . Returns the number of bytes pushed .


<s> bool ia64_const_ok_for_letter_p ( HOST_WIDE_INT value , char c ) { switch ( c ) { case 'I' : return CONST_OK_FOR_I ( value ) ; case 'J' : return CONST_OK_FOR_J ( value ) ; case 'K' : return CONST_OK_FOR_K ( value ) ; case 'L' : return CONST_OK_FOR_L ( value ) ; case 'M' : return CONST_OK_FOR_M ( value ) ; case 'N' : return CONST_OK_FOR_N ( value ) ; case 'O' : return CONST_OK_FOR_O ( value ) ; case 'P' : return CONST_OK_FOR_P ( value ) ; default : return false ; } } </s>


"Opcode has no flag setting equivalent!"

Return the opcode that set flags when possible .


<s> void ARMInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << markup ( "<reg:" ) << getRegisterName ( RegNo ) << markup ( ">" ) ; } </s>


<s> bool HexagonMCInst :: isExtended ( void ) const { const uint64_t F = MCID . TSFlags ; return ( F >> HexagonII :: ExtendedPos ) & HexagonII :: ExtendedMask ; } </s>

Test if the given EVT is extended ( as opposed to being simple ) .

Hexagon Hexagon HexagonII::ExtendedPos HexagonII::ExtendedMask


<s> tree ix86_vectorize_builtin_gather ( const_tree mem_vectype , const_tree index_type , int scale ) { bool si ; enum ix86_builtins code ; if ( ! TARGET_AVX2 || ( known_eq ( TYPE_VECTOR_SUBPARTS ( mem_vectype ) , 2u ) ? ! TARGET_USE_GATHER_2PARTS : ( known_eq ( TYPE_VECTOR_SUBPARTS ( mem_vectype ) , 4u ) ? ! TARGET_USE_GATHER_4PARTS : ! TARGET_USE_GATHER ) ) ) return NULL_TREE ; if ( ( TREE_CODE ( index_type ) != INTEGER_TYPE && ! POINTER_TYPE_P ( index_type ) ) || ( TYPE_MODE ( index_type ) != SImode && TYPE_MODE ( index_type ) != DImode ) ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) > POINTER_SIZE ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) < POINTER_SIZE && TYPE_UNSIGNED ( index_type ) ) return NULL_TREE ; if ( scale <= 0 || scale > 8 || ( scale & ( scale - 1 ) ) != 0 ) return NULL_TREE ; si = TYPE_MODE ( index_type ) == SImode ; switch ( TYPE_MODE ( mem_vectype ) ) { case E_V2DFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV2DF : IX86_BUILTIN_GATHER3DIV2DF ; else code = si ? IX86_BUILTIN_GATHERSIV2DF : IX86_BUILTIN_GATHERDIV2DF ; break ; case E_V4DFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3ALTSIV4DF : IX86_BUILTIN_GATHER3DIV4DF ; else code = si ? IX86_BUILTIN_GATHERALTSIV4DF : IX86_BUILTIN_GATHERDIV4DF ; break ; case E_V2DImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV2DI : IX86_BUILTIN_GATHER3DIV2DI ; else code = si ? IX86_BUILTIN_GATHERSIV2DI : IX86_BUILTIN_GATHERDIV2DI ; break ; case E_V4DImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3ALTSIV4DI : IX86_BUILTIN_GATHER3DIV4DI ; else code = si ? IX86_BUILTIN_GATHERALTSIV4DI : IX86_BUILTIN_GATHERDIV4DI ; break ; case E_V4SFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV4SF : IX86_BUILTIN_GATHER3DIV4SF ; else code = si ? IX86_BUILTIN_GATHERSIV4SF : IX86_BUILTIN_GATHERDIV4SF ; break ; case E_V8SFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV8SF : IX86_BUILTIN_GATHER3ALTDIV8SF ; else code = si ? IX86_BUILTIN_GATHERSIV8SF : IX86_BUILTIN_GATHERALTDIV8SF ; break ; case E_V4SImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV4SI : IX86_BUILTIN_GATHER3DIV4SI ; else code = si ? IX86_BUILTIN_GATHERSIV4SI : IX86_BUILTIN_GATHERDIV4SI ; break ; case E_V8SImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV8SI : IX86_BUILTIN_GATHER3ALTDIV8SI ; else code = si ? IX86_BUILTIN_GATHERSIV8SI : IX86_BUILTIN_GATHERALTDIV8SI ; break ; case E_V8DFmode : if ( TARGET_AVX512F ) code = si ? IX86_BUILTIN_GATHER3ALTSIV8DF : IX86_BUILTIN_GATHER3DIV8DF ; else return NULL_TREE ; break ; case E_V8DImode : if ( TARGET_AVX512F ) code = si ? IX86_BUILTIN_GATHER3ALTSIV8DI : IX86_BUILTIN_GATHER3DIV8DI ; else return NULL_TREE ; break ; case E_V16SFmode : if ( TARGET_AVX512F ) code = si ? IX86_BUILTIN_GATHER3SIV16SF : IX86_BUILTIN_GATHER3ALTDIV16SF ; else return NULL_TREE ; break ; case E_V16SImode : if ( TARGET_AVX512F ) code = si ? IX86_BUILTIN_GATHER3SIV16SI : IX86_BUILTIN_GATHER3ALTDIV16SI ; else return NULL_TREE ; break ; default : return NULL_TREE ; } return ix86_get_builtin ( code ) ; } </s>

Returns a decl of a function that implements gather load with memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE . Return NULL_TREE if it is not available .


<s> static void v850_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( ! TARGET_GCC_ABI ) cum -> nbytes += ( ( ( mode != BLKmode ? GET_MODE_SIZE ( mode ) : int_size_in_bytes ( type ) ) + UNITS_PER_WORD - 1 ) & - UNITS_PER_WORD ) ; else cum -> nbytes += ( ( ( type && int_size_in_bytes ( type ) > 8 ? GET_MODE_SIZE ( Pmode ) : ( mode != BLKmode ? GET_MODE_SIZE ( mode ) : int_size_in_bytes ( type ) ) ) + UNITS_PER_WORD - 1 ) & - UNITS_PER_WORD ) ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


"Unknown regclass in loadRegFromStackSlot!"

Load the specified register of the given register class from the specified stack frame index .


<s> static rtx_code_label * ix86_expand_sse_compare_and_jump ( enum rtx_code code , rtx op0 , rtx op1 , bool swap_operands ) { bool unordered_compare = ix86_unordered_fp_compare ( code ) ; rtx_code_label * label ; rtx tmp , reg ; if ( swap_operands ) std :: swap ( op0 , op1 ) ; label = gen_label_rtx ( ) ; tmp = gen_rtx_COMPARE ( CCFPmode , op0 , op1 ) ; if ( unordered_compare ) tmp = gen_rtx_UNSPEC ( CCFPmode , gen_rtvec ( 1 , tmp ) , UNSPEC_NOTRAP ) ; reg = gen_rtx_REG ( CCFPmode , FLAGS_REG ) ; emit_insn ( gen_rtx_SET ( reg , tmp ) ) ; tmp = gen_rtx_fmt_ee ( code , VOIDmode , reg , const0_rtx ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; tmp = emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; JUMP_LABEL ( tmp ) = label ; return label ; } </s>

Expands a comparison of OP0 with OP1 using comparison code CODE , swapping the operands if SWAP_OPERANDS is true . The expanded code is a forward jump to a newly created label in case the comparison is true . The generated label rtx is returned .