<s> StringRef getPassName ( ) const override { return SYSTEMZ_POSTREWRITE_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> Optional < MCFixupKind > SystemZMCAsmBackend :: getFixupKind ( StringRef Name ) const { unsigned Type = llvm :: StringSwitch < unsigned > ( Name ) . Case ( "BFD_RELOC_NONE" , ELF :: R_390_NONE ) . Case ( "BFD_RELOC_8" , ELF :: R_390_8 ) . Case ( "BFD_RELOC_16" , ELF :: R_390_16 ) . Case ( "BFD_RELOC_32" , ELF :: R_390_32 ) . Case ( "BFD_RELOC_64" , ELF :: R_390_64 ) . Default ( - 1u ) ; if ( Type != - 1u ) return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ; return None ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> StringRef getPassName ( ) const override { return RISCV_CLEANUP_VSETVLI_NAME ; } </s>


<s> int hppa_can_use_return_insn_p ( ) { return ( reload_completed && ( compute_frame_size ( get_frame_size ( ) , 0 ) ? 0 : 1 ) && ! regs_ever_live [ 2 ] && ! frame_pointer_needed ) ; } </s>

This is only valid once reload has completed because it depends on knowing exactly how much ( if any ) frame there is and ... It 's only valid if there is no frame marker to de-allocate and ... It 's only valid if % r2 has n't been saved into the caller 's frame ( we 're not profiling and % r2 is n't live anywhere ) .


<s> const MCPhysReg * SICRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_O32_SaveList ; } </s>


<s> SDValue AlphaTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_Alpha ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) . getValue ( 1 ) ; SDValue RetValue = Chain . getValue ( 0 ) ; InFlag = Chain . getValue ( 2 ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) RetValue = DAG . getNode ( ISD :: AssertSext , dl , VA . getLocVT ( ) , RetValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) RetValue = DAG . getNode ( ISD :: AssertZext , dl , VA . getLocVT ( ) , RetValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) RetValue = DAG . getNode ( ISD :: TRUNCATE , dl , VA . getValVT ( ) , RetValue ) ; InVals . push_back ( RetValue ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> void ARMBankConflictHazardRecognizer :: AdvanceCycle ( ) { Accesses . clear ( ) ; } </s>

AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled can not issue in the current cycle , either because of latency or resource conflicts .


<s> void NVPTXTargetStreamer :: emitDwarfFileDirective ( StringRef Directive ) { DwarfFiles . emplace_back ( Directive ) ; } </s>

Record DWARF file directives for later output .


<s> bool single_dest_per_chain ( const rtx & t ATTRIBUTE_UNUSED , insn_info_list_t * v , void * arg ATTRIBUTE_UNUSED ) { for ( int i = v -> length ( ) - 1 ; i >= 1 ; i -- ) { tag_insn_info * insn_info = ( * v ) [ i ] ; for ( int j = v -> length ( ) - 2 ; j >= 0 ; j -- ) { if ( in_same_chain ( insn_info -> insn , ( * v ) [ j ] -> insn , REGNO ( insn_info -> dest ) ) ) { v -> ordered_remove ( j ) ; i = v -> length ( ) ; break ; } } } return true ; } </s>

Callback function to traverse the tag map and drop loads that have the same destination and and in the same chain of occurrence . Routine always returns true to allow traversal through all of TAG_MAP .


<s> int h8300_legitimate_address_p ( enum machine_mode mode , rtx x , int strict ) { if ( h8300_rtx_ok_for_base_p ( x , strict ) ) return 1 ; if ( CONSTANT_ADDRESS_P ( x ) ) return 1 ; if ( TARGET_H8300SX && ( GET_CODE ( x ) == PRE_INC || GET_CODE ( x ) == PRE_DEC || GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == POST_DEC ) && h8300_rtx_ok_for_base_p ( XEXP ( x , 0 ) , strict ) ) return 1 ; if ( GET_CODE ( x ) == PLUS && CONSTANT_ADDRESS_P ( XEXP ( x , 1 ) ) && h8300_rtx_ok_for_base_p ( h8300_get_index ( XEXP ( x , 0 ) , mode , 0 ) , strict ) ) return 1 ; return 0 ; } </s>

Return nozero if X is a legitimate address . On the H8/300 , a legitimate address has the form REG , REG+CONSTANT_ADDRESS or CONSTANT_ADDRESS .


<s> Register AVRRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { return AVR :: R28 ; } return AVR :: SP ; } </s>


<s> void X86InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , Register DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { if ( RC -> getID ( ) == X86 :: TILERegClassID ) { unsigned Opc = X86 :: TILELOADD ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; Register VirtReg = RegInfo . createVirtualRegister ( & X86 :: GR64_NOSPRegClass ) ; MachineInstr * NewMI = BuildMI ( MBB , MI , DebugLoc ( ) , get ( X86 :: MOV64ri ) , VirtReg ) . addImm ( 64 ) ; NewMI = addFrameReference ( BuildMI ( MBB , MI , DebugLoc ( ) , get ( Opc ) , DestReg ) , FrameIdx ) ; MachineOperand & MO = NewMI -> getOperand ( 3 ) ; MO . setReg ( VirtReg ) ; MO . setIsKill ( true ) ; } else { const MachineFunction & MF = * MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned Alignment = std :: max < uint32_t > ( TRI -> getSpillSize ( * RC ) , 16 ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlign ( ) >= Alignment ) || ( RI . canRealignStack ( MF ) && ! MFI . isFixedObjectIndex ( FrameIdx ) ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , Subtarget ) ; addFrameReference ( BuildMI ( MBB , MI , DebugLoc ( ) , get ( Opc ) , DestReg ) , FrameIdx ) ; } } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> RISCVSubtarget & RISCVSubtarget :: initializeSubtargetDependencies ( const Triple & TT , StringRef CPU , StringRef FS , StringRef ABIName ) { bool Is64Bit = TT . isArch64Bit ( ) ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = Is64Bit ? "generic-rv64" : "generic-rv32" ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( Is64Bit ) { XLenVT = MVT :: i64 ; XLen = 64 ; } TargetABI = RISCVABI :: computeTargetABI ( TT , getFeatureBits ( ) , ABIName ) ; RISCVFeatures :: validate ( TT , getFeatureBits ( ) ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> static void desc_prologue ( int body , unw_word rlen , unsigned char mask , unsigned char grsave , struct unw_state_record * sr ) { int i ; if ( ! ( sr -> in_body || sr -> first_region ) ) finish_prologue ( sr ) ; sr -> first_region = 0 ; if ( sr -> when_target < sr -> region_start + sr -> region_len ) { sr -> done = 1 ; return ; } for ( i = 0 ; i < sr -> epilogue_count ; ++ i ) pop ( sr ) ; sr -> epilogue_count = 0 ; sr -> epilogue_start = UNW_WHEN_NEVER ; if ( ! body ) push ( sr ) ; sr -> region_start += sr -> region_len ; sr -> region_len = rlen ; sr -> in_body = body ; if ( ! body ) { for ( i = 0 ; i < 4 ; ++ i ) { if ( mask & 0x8 ) set_reg ( sr -> curr . reg + save_order [ i ] , UNW_WHERE_GR , sr -> region_start + sr -> region_len - 1 , grsave ++ ) ; mask <<= 1 ; } sr -> gr_save_loc = grsave ; sr -> any_spills = 0 ; sr -> imask = 0 ; sr -> spill_offset = 0x10 ; } } </s>


<s> bool isLegalMaskedGather ( Type * Ty , MaybeAlign Alignment ) { return false ; } </s>

Return true if the target supports masked gather .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s>
void
AMDGPUInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
llvm_unreachable
(
"Not Implemented"
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> static bool mep_get_intrinsic_insn ( int intrinsic ATTRIBUTE_UNUSED , const struct cgen_insn * * insn_ptr ATTRIBUTE_UNUSED ) { int i ; i = mep_intrinsic_insn [ intrinsic ] ; while ( i >= 0 && ! CGEN_ENABLE_INSN_P ( i ) ) i = mep_intrinsic_chain [ i ] ; if ( i >= 0 ) { * insn_ptr = & cgen_insns [ i ] ; return true ; } return false ; } </s>

See if any implementation of INTRINSIC is available to the current function . If so , store the most general implementation in * INSN_PTR and return true . Return false otherwise .


<s> bool SparcFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> const char * getClearCacheBuiltinName ( ) const { return 0 ; } </s>

Intel processors have a unified instruction and data cache .


<s> bool SIMemoryLegalizer :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; const IsaInfo :: IsaVersion IV = IsaInfo :: getIsaVersion ( ST . getFeatureBits ( ) ) ; MMI = & MF . getMMI ( ) . getObjFileInfo < AMDGPUMachineModuleInfo > ( ) ; TII = ST . getInstrInfo ( ) ; Vmcnt0Immediate = AMDGPU :: encodeWaitcnt ( IV , 0 , getExpcntBitMask ( IV ) , getLgkmcntBitMask ( IV ) ) ; VmemSIMDCacheInvalidateOpc = ST . getGeneration ( ) <= AMDGPUSubtarget :: SOUTHERN_ISLANDS ? AMDGPU :: BUFFER_WBINVL1 : AMDGPU :: BUFFER_WBINVL1_VOL ; for ( auto & MBB : MF ) { for ( auto MI = MBB . begin ( ) ; MI != MBB . end ( ) ; ++ MI ) { if ( ! ( MI -> getDesc ( ) . TSFlags & SIInstrFlags :: maybeAtomic ) ) continue ; if ( const auto & MOI = SIMemOpInfo :: getLoadInfo ( MI ) ) Changed |= expandLoad ( MOI . getValue ( ) , MI ) ; else if ( const auto & MOI = SIMemOpInfo :: getStoreInfo ( MI ) ) Changed |= expandStore ( MOI . getValue ( ) , MI ) ; else if ( const auto & MOI = SIMemOpInfo :: getAtomicFenceInfo ( MI ) ) Changed |= expandAtomicFence ( MOI . getValue ( ) , MI ) ; else if ( const auto & MOI = SIMemOpInfo :: getAtomicCmpxchgOrRmwInfo ( MI ) ) Changed |= expandAtomicCmpxchgOrRmw ( MOI . getValue ( ) , MI ) ; } } Changed |= removeAtomicPseudoMIs ( ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .

AMDGPU SI SI SI AMDGPU AMDGPU::encodeWaitcnt 0 SI AMDGPU AMDGPU::BUFFER_WBINVL1 AMDGPU::BUFFER_WBINVL1_VOL SIInstrFlags::maybeAtomic SI SI SI SI


<s> static bool ix86_additional_allocno_class_p ( reg_class_t cl ) { return cl == MOD4_SSE_REGS ; } </s>

Return true if register class CL should be an additional allocno class .


<s> int GCNTTIImpl :: getIntrinsicInstrCost ( Intrinsic :: ID ID , Type * RetTy , ArrayRef < Type * > Tys , FastMathFlags FMF , unsigned ScalarizationCostPassed ) { return getIntrinsicInstrCost < Type > ( ID , RetTy , Tys , FMF , ScalarizationCostPassed ) ; } </s>


<s> static void function_arg_record_value_1 ( tree type , HOST_WIDE_INT startbitpos , struct function_arg_record_value_parms * parms , bool packed_p ) { tree field ; if ( ! packed_p ) for ( field = TYPE_FIELDS ( type ) ; field ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) == FIELD_DECL && DECL_PACKED ( field ) ) { packed_p = true ; break ; } } for ( field = TYPE_FIELDS ( type ) ; field ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) == FIELD_DECL ) { HOST_WIDE_INT bitpos = startbitpos ; if ( DECL_SIZE ( field ) != 0 ) { if ( integer_zerop ( DECL_SIZE ( field ) ) ) continue ; if ( host_integerp ( bit_position ( field ) , 1 ) ) bitpos += int_bit_position ( field ) ; } if ( TREE_CODE ( TREE_TYPE ( field ) ) == RECORD_TYPE ) function_arg_record_value_1 ( TREE_TYPE ( field ) , bitpos , parms , packed_p ) ; else if ( ( FLOAT_TYPE_P ( TREE_TYPE ( field ) ) || TREE_CODE ( TREE_TYPE ( field ) ) == VECTOR_TYPE ) && TARGET_FPU && parms -> named && ! packed_p ) { if ( parms -> intoffset != - 1 ) { unsigned int startbit , endbit ; int intslots , this_slotno ; startbit = parms -> intoffset & - BITS_PER_WORD ; endbit = ( bitpos + BITS_PER_WORD - 1 ) & - BITS_PER_WORD ; intslots = ( endbit - startbit ) / BITS_PER_WORD ; this_slotno = parms -> slotno + parms -> intoffset / BITS_PER_WORD ; if ( intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno ) { intslots = MAX ( 0 , SPARC_INT_ARG_MAX - this_slotno ) ; parms -> stack = 1 ; } parms -> nregs += intslots ; parms -> intoffset = - 1 ; } if ( TREE_CODE ( TREE_TYPE ( field ) ) == VECTOR_TYPE && DECL_MODE ( field ) == BLKmode ) parms -> nregs += TYPE_VECTOR_SUBPARTS ( TREE_TYPE ( field ) ) ; else if ( TREE_CODE ( TREE_TYPE ( field ) ) == COMPLEX_TYPE ) parms -> nregs += 2 ; else parms -> nregs += 1 ; } else { if ( parms -> intoffset == - 1 ) parms -> intoffset = bitpos ; } } } } </s>

A subroutine of function_arg_record_value . Traverse the structure recursively and determine how many registers will be required .


<s> void X86PassConfig :: addPreEmitPass2 ( ) { const Triple & TT = TM -> getTargetTriple ( ) ; const MCAsmInfo * MAI = TM -> getMCAsmInfo ( ) ; addPass ( createX86RetpolineThunksPass ( ) ) ; if ( TT . isOSWindows ( ) && TT . getArch ( ) == Triple :: x86_64 ) addPass ( createX86AvoidTrailingCallPass ( ) ) ; if ( ! TT . isOSDarwin ( ) && ( ! TT . isOSWindows ( ) || MAI -> getExceptionHandlingType ( ) == ExceptionHandling :: DwarfCFI ) ) addPass ( createCFIInstrInserter ( ) ) ; if ( TT . isOSWindows ( ) ) addPass ( createCFGuardLongjmpPass ( ) ) ; } </s>

Targets may add passes immediately before machine code is emitted in this callback .


"Successfully decoded 64-bit instruction."

"Not a 64-bit instruction, falling back to 32-bit."

"Successfully decoded 16-bit instruction with limm."

"Not a 16-bit instruction with limm, try without it."

Returns the disassembly of a single instruction .


<s> bool SIInsertWaits :: runOnMachineFunction ( MachineFunction & MF ) { bool Changes = false ; TII = static_cast < const SIInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = static_cast < const SIRegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; MRI = & MF . getRegInfo ( ) ; WaitedOn = ZeroCounts ; LastIssued = ZeroCounts ; LastOpcodeType = OTHER ; memset ( & UsedRegs , 0 , sizeof ( UsedRegs ) ) ; memset ( & DefinedRegs , 0 , sizeof ( DefinedRegs ) ) ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { if ( I -> getOpcode ( ) == AMDGPU :: S_BARRIER ) Changes |= insertWait ( MBB , I , LastIssued ) ; else Changes |= insertWait ( MBB , I , handleOperands ( * I ) ) ; pushInstruction ( MBB , I ) ; } Changes |= insertWait ( MBB , MBB . getFirstTerminator ( ) , LastIssued ) ; } return Changes ; } </s>


<s> static void ia64_emit_insn_before ( rtx insn , rtx before ) { emit_insn_before ( insn , before ) ; } </s>

Like emit_insn_before , but skip cycle_display insns . This makes the assembly output a bit prettier .


<s> static bool cris_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) { return ( targetm . calls . must_pass_in_stack ( arg ) || CRIS_FUNCTION_ARG_SIZE ( arg . mode , arg . type ) > 8 ) ; } </s>

Return true if TYPE must be passed by invisible reference . For cris , we pass < = 8 bytes by value , others by reference .


Emit a comparison between OP0 and OP1 . Return true iff the comparison was reversed . SC1 is an SImode scratch reg , and SC2 a DImode scratch reg , as needed . CODE is the code of the comparison , we return it unchanged or swapped , as necessary .


<s> int compare_diff_p ( rtx insn ) { RTX_CODE cond = compare_condition ( insn ) ; return ( cond == GT || cond == GTU || cond == LE || cond == LEU ) ? cond : 0 ; } </s>

Returns nonzero if the next insn is a JUMP_INSN with a condition that needs to be swapped ( GT , GTU , LE , LEU ) .


<s> auto begin ( ) const { return Data . begin ( ) ; } </s>


<s>
SDValue
VETargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
ATOMIC_FENCE
:
return
lowerATOMIC_FENCE
(
Op
,
DAG
)
;
case
ISD
::
ATOMIC_SWAP
:
return
lowerATOMIC_SWAP
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
lowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
lowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
lowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
EH_SJLJ_LONGJMP
:
return
lowerEH_SJLJ_LONGJMP
(
Op
,
DAG
)
;
case
ISD
::
EH_SJLJ_SETJMP
:
return
lowerEH_SJLJ_SETJMP
(
Op
,
DAG
)
;
case
ISD
::
EH_SJLJ_SETUP_DISPATCH
:
return
lowerEH_SJLJ_SETUP_DISPATCH
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
lowerFRAMEADDR
(
Op
,
DAG
,
*
this
,
Subtarget
)
;
case
ISD
::
GlobalAddress
:
return
lowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
lowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
lowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
lowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
LOAD
:
return
lowerLOAD
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
lowerRETURNADDR
(
Op
,
DAG
,
*
this
,
Subtarget
)
;
case
ISD
::
BUILD_VECTOR
:
return
lowerBUILD_VECTOR
(
Op
,
DAG
)
;
case
ISD
::
STORE
:
return
lowerSTORE
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
lowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
VAARG
:
return
lowerVAARG
(
Op
,
DAG
)
;
return
lowerToVVP
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> unsigned Tile64InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> static rtx gen_int_si ( HOST_WIDE_INT val ) { return gen_int_mode ( val , SImode ) ; } </s>

Returns an SImode integer rtx with value VAL .


<s> MachineBasicBlock :: iterator MipsFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { unsigned SP = STI . getABI ( ) . GetStackPtr ( ) ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( 0 ) . getImm ( ) ; if ( ( I -> getOpcode ( ) == Mips :: ADJCALLSTACKDOWN ) || ( I -> getOpcode ( ) == Mips :: ADJCALLSTACKCAPDOWN ) ) Amount = - Amount ; STI . getInstrInfo ( ) -> adjustStackPtr ( SP , Amount , MBB , I ) ; } return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

Mips Mips 0 Mips::ADJCALLSTACKDOWN Mips::ADJCALLSTACKCAPDOWN


<s> static inline bool current_function_saves_fp ( void ) { return current_frame_info . save_fp != 0 ; } </s>

Accessor for current_frame_info.save_fp .


<s> bool ARMSubtarget :: isGVIndirectSymbol ( const GlobalValue * GV ) const { if ( ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return true ; if ( isTargetMachO ( ) && TM . isPositionIndependent ( ) && ( GV -> isDeclarationForLinker ( ) || GV -> hasCommonLinkage ( ) ) ) return true ; return false ; } </s>

True if the GV will be accessed via an indirect symbol .


<s> const Z80RegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
static
void
write_var_marker
(
FILE
*
file
,
bool
is_defn
,
bool
globalize
,
const
char
*
name
)
{
fprintf
(
file
,
"\n// BEGIN%s VAR %s: "
,
globalize
" GLOBAL"
:
""
,
is_defn
"DEF"
:
"DECL"
)
;
assemble_name_raw
(
file
,
name
)
;
fputs
(
"\n"
,
file
)
;
}
</s>

Emit a linker marker for a variable decl or defn .

nvptx
"\n// BEGIN%s VAR %s: "
" GLOBAL"
""
"DEF"
"DECL"
"\n"


<s>
void
X86AsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
unsigned
Kind
=
Fixup
.
getKind
(
)
;
if
(
Kind
>=
FirstLiteralRelocationKind
)
return
;
unsigned
Size
=
getFixupKindSize
(
Kind
)
;
assert
(
Fixup
.
getOffset
(
)
+
Size
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
int64_t
SignedValue
=
static_cast
<
int64_t
>
(
Value
)
;
if
(
(
Target
.
isAbsolute
(
)
||
IsResolved
)
&&
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
.
Flags
&
MCFixupKindInfo
::
FKF_IsPCRel
)
{
if
(
Size
>
0
&&
!
isIntN
(
Size
*
8
,
SignedValue
)
)
Asm
.
getContext
(
)
.
reportError
(
Fixup
.
getLoc
(
)
,
"value of "
+
Twine
(
SignedValue
)
+
" is too large for field of "
+
Twine
(
Size
)
+
(
(
Size
==
1
)
" byte."
:
" bytes."
)
)
;
}
else
{
assert
(
(
Size
==
0
||
isIntN
(
Size
*
8
+
1
,
SignedValue
)
)
&&
"Value does not fit in the Fixup field"
)
;
}
for
(
unsigned
i
=
0
;
i
!=
Size
;
++
i
)
Data
[
Fixup
.
getOffset
(
)
+
i
]
=
uint8_t
(
Value
>>
(
i
*
8
)
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool VERegisterInfo :: isConstantPhysReg ( unsigned PhysReg ) const { return false ; } </s>

Returns true if PhysReg is unallocatable and constant throughout the function .


<s> bool AArch64MIPeepholeOpt :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; TII = static_cast < const AArch64InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MRI = & MF . getRegInfo ( ) ; if ( ! MRI -> isSSA ( ) ) return false ; bool Changed = false ; SmallSetVector < MachineInstr * , 8 > ToBeRemoved ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) { switch ( MI . getOpcode ( ) ) { default : break ; case AArch64 :: ANDWrr : Changed = visitAND < uint32_t > ( MI , ToBeRemoved ) ; break ; case AArch64 :: ANDXrr : Changed = visitAND < uint64_t > ( MI , ToBeRemoved ) ; break ; } } } for ( MachineInstr * MI : ToBeRemoved ) MI -> eraseFromParent ( ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s>
static
void
macho_branch_islands
(
void
)
{
char
tmp_buf
[
512
]
;
while
(
!
vec_safe_is_empty
(
branch_islands
)
)
{
branch_island
*
bi
=
&
branch_islands
->
last
(
)
;
const
char
*
label
=
IDENTIFIER_POINTER
(
bi
->
label_name
)
;
const
char
*
name
=
IDENTIFIER_POINTER
(
bi
->
function_name
)
;
char
name_buf
[
512
]
;
if
(
name
[
0
]
==
'*'
||
name
[
0
]
==
'&'
)
strcpy
(
name_buf
,
name
+
1
)
;
else
{
name_buf
[
0
]
=
'_'
;
strcpy
(
name_buf
+
1
,
name
)
;
}
strcpy
(
tmp_buf
,
"\n"
)
;
strcat
(
tmp_buf
,
label
)
;
if
(
write_symbols
==
DBX_DEBUG
||
write_symbols
==
XCOFF_DEBUG
)
dbxout_stabd
(
N_SLINE
,
bi
->
line_number
)
;
if
(
flag_pic
)
{
if
(
TARGET_LINK_STACK
)
{
char
name
[
32
]
;
get_ppc476_thunk_name
(
name
)
;
strcat
(
tmp_buf
,
":\n\tmflr r0\n\tbl "
)
;
strcat
(
tmp_buf
,
name
)
;
strcat
(
tmp_buf
,
"\n"
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic:\n\tmflr r11\n"
)
;
}
else
{
strcat
(
tmp_buf
,
":\n\tmflr r0\n\tbcl 20,31,"
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic\n"
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic:\n\tmflr r11\n"
)
;
}
strcat
(
tmp_buf
,
"\taddis r11,r11,ha16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
" - "
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic)\n"
)
;
strcat
(
tmp_buf
,
"\tmtlr r0\n"
)
;
strcat
(
tmp_buf
,
"\taddi r12,r11,lo16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
" - "
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic)\n"
)
;
strcat
(
tmp_buf
,
"\tmtctr r12\n\tbctr\n"
)
;
}
else
{
strcat
(
tmp_buf
,
":\nlis r12,hi16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
")\n\tori r12,r12,lo16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
")\n\tmtctr r12\n\tbctr"
)
;
}
output_asm_insn
(
tmp_buf
,
0
)
;
if
(
write_symbols
==
DBX_DEBUG
||
write_symbols
==
XCOFF_DEBUG
)
dbxout_stabd
(
N_SLINE
,
bi
->
line_number
)
;
branch_islands
->
pop
(
)
;
}
}
</s>

Generate far-jump branch islands for everything on the branch_island_list . Invoked immediately after the last instruction of the epilogue has been emitted ; the branch-islands must be appended to , and contiguous with , the function body . Mach-O stubs are generated in machopic_output_stub ( ) .


<s> void xtensa_expand_compare_and_swap ( rtx target , rtx mem , rtx cmp , rtx new_rtx ) { machine_mode mode = GET_MODE ( mem ) ; struct alignment_context ac ; rtx tmp , cmpv , newv , val ; rtx oldval = gen_reg_rtx ( SImode ) ; rtx res = gen_reg_rtx ( SImode ) ; rtx_code_label * csloop = gen_label_rtx ( ) ; rtx_code_label * csend = gen_label_rtx ( ) ; init_alignment_context ( & ac , mem ) ; if ( ac . shift != NULL_RTX ) { cmp = xtensa_expand_mask_and_shift ( cmp , mode , ac . shift ) ; new_rtx = xtensa_expand_mask_and_shift ( new_rtx , mode , ac . shift ) ; } val = force_reg ( SImode , expand_simple_binop ( SImode , AND , ac . memsi , ac . modemaski , NULL_RTX , 1 , OPTAB_DIRECT ) ) ; emit_label ( csloop ) ; cmpv = force_reg ( SImode , expand_simple_binop ( SImode , IOR , cmp , val , NULL_RTX , 1 , OPTAB_DIRECT ) ) ; newv = force_reg ( SImode , expand_simple_binop ( SImode , IOR , new_rtx , val , NULL_RTX , 1 , OPTAB_DIRECT ) ) ; emit_insn ( gen_sync_compare_and_swapsi ( res , ac . memsi , cmpv , newv ) ) ; emit_cmp_and_jump_insns ( res , cmpv , EQ , const0_rtx , SImode , true , csend ) ; emit_move_insn ( oldval , val ) ; tmp = expand_simple_binop ( SImode , AND , res , ac . modemaski , val , 1 , OPTAB_DIRECT ) ; if ( tmp != val ) emit_move_insn ( val , tmp ) ; emit_cmp_and_jump_insns ( oldval , val , NE , const0_rtx , SImode , true , csloop ) ; emit_label ( csend ) ; convert_move ( target , ( ac . shift == NULL_RTX ? res : expand_simple_binop ( SImode , LSHIFTRT , res , ac . shift , NULL_RTX , 1 , OPTAB_DIRECT ) ) , 1 ) ; } </s>

Expand an atomic compare and swap operation for HImode and QImode . MEM is the memory location , CMP the old value to compare MEM with and NEW_RTX the value to set if CMP == MEM .


"Run 'TMS320C64XIfConversion' pass for '"


<s> static void record_jump ( int cycle , rtx cond ) { if ( ss . jump_cycle_index == 0 ) ss . jump_cycle_index = 11 ; else ss . jump_cycle_index -- ; ss . jump_cycles [ ss . jump_cycle_index ] = cycle ; ss . jump_cond [ ss . jump_cycle_index ] = cond ; } </s>

Add a new entry in our scheduling state for a jump that occurs in CYCLE and has the opposite condition of COND .


<s> bool ARMBaseInstrInfo :: PredicateInstruction ( MachineInstr & MI , ArrayRef < MachineOperand > Pred ) const { unsigned Opc = MI . getOpcode ( ) ; if ( isUncondBranchOpcode ( Opc ) ) { MI . setDesc ( get ( getMatchingCondBranchOpcode ( Opc ) ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( Pred [ 0 ] . getImm ( ) ) . addReg ( Pred [ 1 ] . getReg ( ) ) ; return true ; } int PIdx = MI . findFirstPredOperandIdx ( ) ; if ( PIdx != - 1 ) { MachineOperand & PMO = MI . getOperand ( PIdx ) ; PMO . setImm ( Pred [ 0 ] . getImm ( ) ) ; MI . getOperand ( PIdx + 1 ) . setReg ( Pred [ 1 ] . getReg ( ) ) ; return true ; } return false ; } </s>

Convert the instruction into a predicated instruction .


<s> bool isValidUnquotedName ( StringRef Name ) const override { return true ; } </s>

Return true if the identifier Name does not need quotes to be syntactically correct .


<s>
void
final_prescan_insn
(
rtx
insn
,
rtx
*
operand
ATTRIBUTE_UNUSED
,
int
num_operands
ATTRIBUTE_UNUSED
)
{
int
uid
=
INSN_UID
(
insn
)
;
if
(
TARGET_INSN_SIZE_DUMP
||
TARGET_ALL_DEBUG
)
{
fprintf
(
asm_out_file
,
"/*DEBUG: 0x%x\t\t%d\t%d */\n"
,
INSN_ADDRESSES
(
uid
)
,
INSN_ADDRESSES
(
uid
)
last_insn_address
,
rtx_cost
(
PATTERN
(
insn
)
,
INSN
)
)
;
}
last_insn_address
=
INSN_ADDRESSES
(
uid
)
;
}
</s>

If defined , a C statement to be executed just prior to the output of assembler code for INSN , to modify the extracted operands so they will be output differently . Here the argument OPVEC is the vector containing the operands extracted from INSN , and NOPERANDS is the number of elements of the vector which contain meaningful data for this insn . The contents of this vector are what will be used to convert the insn template into assembler code , so you can change the assembler output by changing the contents of the vector . We use it to check if the current insn needs a nop in front of it because of load delays , and also to update the delay slot statistics .


<s>
SDValue
Z80TargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
switch
(
CallConv
)
{
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
break
;
default
:
report_fatal_error
(
"Only FastCC and CCC is supported"
)
;
}
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
analyzeOutputArgs
(
DAG
.
getMachineFunction
(
)
,
CCInfo
,
Outs
,
true
,
nullptr
)
;
SDValue
Glue
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
<
e
;
++
i
)
{
SDValue
Val
=
OutVals
[
i
]
;
CCValAssign
&
VA
=
RVLocs
[
i
]
;
Val
=
convertValVTToLocVT
(
DAG
,
Val
,
VA
,
DL
)
;
if
(
VA
.
isRegLoc
(
)
)
{
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
Val
,
Glue
)
;
Glue
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
else
if
(
VA
.
isMemLoc
(
)
)
{
report_fatal_error
(
"Stack Return is not supported"
)
;
}
else
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Trying to return VAType: "
<<
EVT
(
VA
.
getLocVT
(
)
)
.
getEVTString
(
)
<<
"\n"
)
;
llvm_unreachable
(
"Unsupported Return Value / Location"
)
;
}
}
RetOps
[
0
]
=
Chain
;
if
(
Glue
.
getNode
(
)
)
{
RetOps
.
push_back
(
Glue
)
;
}
return
DAG
.
getNode
(
Z80ISD
::
RET
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool isMem ( ) const override { return false ; } </s>


<s> void bpf_expand_cbranch ( machine_mode mode , rtx * operands ) { if ( bpf_has_jmpext ) return ; enum rtx_code code = GET_CODE ( operands [ 0 ] ) ; if ( ( code == LT || code == LE || code == LTU || code == LEU ) ) { PUT_CODE ( operands [ 0 ] , reverse_condition ( code ) ) ; if ( ! register_operand ( operands [ 2 ] , mode ) ) operands [ 2 ] = force_reg ( mode , operands [ 2 ] ) ; rtx tmp = operands [ 1 ] ; operands [ 1 ] = operands [ 2 ] ; operands [ 2 ] = tmp ; } } </s>

Expand to the instructions for a conditional branch . This function is called when expanding the 'cbranch < mode > 4 ' pattern in bpf.md .


<s> bool targetHandlesStackFrameRounding ( ) const override { return true ; } </s>

targetHandlesStackFrameRounding - Returns true if the target is responsible for rounding up the stack frame ( probably at emitPrologue time ) .


"malformed %<target()%> pragma or attribute"

"pragma or attribute %<target(\"%s\")%> does not accept an argument"

"pragma or attribute %<target(\"%s\")%> does not allow a negated form"

"pragma or attribute %<target(\"%s=%s\")%> is not valid"

Parse ARG_STR which contains the definition of one target attribute . Show appropriate errors if any or return true if the attribute is valid . PRAGMA_OR_ATTR holds the string to use in error messages about whether we 're processing a target attribute or pragma .


<s>
void
load_pic_register
(
)
{
int
orig_flag_pic
=
flag_pic
;
if
(
!
flag_pic
)
abort
(
)
;
if
(
get_pc_symbol_name
[
0
]
==
0
)
{
int
align
;
ASM_GENERATE_INTERNAL_LABEL
(
get_pc_symbol_name
,
"LGETPC"
,
0
)
;
text_section
(
)
;
align
=
floor_log2
(
FUNCTION_BOUNDARY
/
BITS_PER_UNIT
)
;
if
(
align
>
0
)
ASM_OUTPUT_ALIGN
(
asm_out_file
,
align
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
"LGETPC"
,
0
)
;
fputs
(
"\tretl\n\tadd\t%o7, %l7, %l7\n"
,
asm_out_file
)
;
}
global_offset_table
=
gen_rtx_SYMBOL_REF
(
Pmode
,
"_GLOBAL_OFFSET_TABLE_"
)
;
get_pc_symbol
=
gen_rtx_SYMBOL_REF
(
Pmode
,
get_pc_symbol_name
)
;
flag_pic
=
0
;
emit_insn
(
gen_get_pc
(
pic_offset_table_rtx
,
global_offset_table
,
get_pc_symbol
)
)
;
flag_pic
=
orig_flag_pic
;
emit_insn
(
gen_rtx_USE
(
VOIDmode
,
pic_offset_table_rtx
)
)
;
}
</s>


<s> static bool cortex_a9_sched_adjust_cost ( rtx_insn * insn , int dep_type , rtx_insn * dep , int * cost ) { switch ( dep_type ) { case REG_DEP_ANTI : * cost = 0 ; return false ; case REG_DEP_TRUE : case REG_DEP_OUTPUT : if ( recog_memoized ( insn ) >= 0 && recog_memoized ( dep ) >= 0 ) { if ( GET_CODE ( PATTERN ( insn ) ) == SET ) { if ( GET_MODE_CLASS ( GET_MODE ( SET_DEST ( PATTERN ( insn ) ) ) ) == MODE_FLOAT || GET_MODE_CLASS ( GET_MODE ( SET_SRC ( PATTERN ( insn ) ) ) ) == MODE_FLOAT ) { enum attr_type attr_type_insn = get_attr_type ( insn ) ; enum attr_type attr_type_dep = get_attr_type ( dep ) ; if ( REG_P ( SET_DEST ( PATTERN ( insn ) ) ) && reg_set_p ( SET_DEST ( PATTERN ( insn ) ) , dep ) ) { if ( ( attr_type_insn == TYPE_FMACS || attr_type_insn == TYPE_FMACD ) && ( attr_type_dep == TYPE_FMACS || attr_type_dep == TYPE_FMACD ) ) { if ( dep_type == REG_DEP_OUTPUT ) * cost = insn_default_latency ( dep ) - 3 ; else * cost = insn_default_latency ( dep ) ; return false ; } else { if ( dep_type == REG_DEP_OUTPUT ) * cost = insn_default_latency ( dep ) + 1 ; else * cost = insn_default_latency ( dep ) ; } return false ; } } } } break ; default : gcc_unreachable ( ) ; } return true ; } </s>


<s> bool ARMBaseInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TBB , unsigned TCycles , unsigned TExtra , MachineBasicBlock & FBB , unsigned FCycles , unsigned FExtra , BranchProbability Probability ) const { if ( ! TCycles ) return false ; if ( Subtarget . isThumb2 ( ) && TBB . getParent ( ) -> getFunction ( ) . hasMinSize ( ) ) { if ( TBB . pred_size ( ) != 1 || FBB . pred_size ( ) != 1 ) return false ; } const unsigned ScalingUpFactor = 1024 ; unsigned PredCost = ( TCycles + FCycles + TExtra + FExtra ) * ScalingUpFactor ; unsigned UnpredCost ; if ( ! Subtarget . hasBranchPredictor ( ) ) { unsigned NotTakenBranchCost = 1 ; unsigned TakenBranchCost = Subtarget . getMispredictionPenalty ( ) ; unsigned TUnpredCycles , FUnpredCycles ; if ( ! FCycles ) { TUnpredCycles = TCycles + NotTakenBranchCost ; FUnpredCycles = TakenBranchCost ; } else { TUnpredCycles = TCycles + TakenBranchCost ; FUnpredCycles = FCycles + NotTakenBranchCost ; PredCost -= 1 * ScalingUpFactor ; } unsigned TUnpredCost = Probability . scale ( TUnpredCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FUnpredCycles * ScalingUpFactor ) ; UnpredCost = TUnpredCost + FUnpredCost ; if ( Subtarget . isThumb2 ( ) && TCycles + FCycles > 4 ) { PredCost += ( ( TCycles + FCycles - 4 ) / 4 ) * ScalingUpFactor ; } } else { unsigned TUnpredCost = Probability . scale ( TCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FCycles * ScalingUpFactor ) ; UnpredCost = TUnpredCost + FUnpredCost ; UnpredCost += 1 * ScalingUpFactor ; UnpredCost += Subtarget . getMispredictionPenalty ( ) * ScalingUpFactor / 10 ; } return PredCost <= UnpredCost ; } </s>


<s> bool shouldTrackLaneMasks ( ) const override { return true ; } </s>

Returns true if lanemasks should be tracked .


"getIntImmCost can only estimate cost of materialising integers"

Calculate the cost of materializing a 64-bit value .


<s> bool toc_relative_expr_p ( const_rtx op , bool strict , const_rtx * tocrel_base_ret , const_rtx * tocrel_offset_ret ) { if ( ! TARGET_TOC ) return false ; if ( TARGET_CMODEL != CMODEL_SMALL ) { if ( strict && ! ( GET_CODE ( op ) == LO_SUM && REG_P ( XEXP ( op , 0 ) ) && INT_REG_OK_FOR_BASE_P ( XEXP ( op , 0 ) , strict ) ) ) return false ; if ( GET_CODE ( op ) == LO_SUM ) op = XEXP ( op , 1 ) ; } const_rtx tocrel_base = op ; const_rtx tocrel_offset = const0_rtx ; if ( GET_CODE ( op ) == PLUS && add_cint_operand ( XEXP ( op , 1 ) , GET_MODE ( op ) ) ) { tocrel_base = XEXP ( op , 0 ) ; tocrel_offset = XEXP ( op , 1 ) ; } if ( tocrel_base_ret ) * tocrel_base_ret = tocrel_base ; if ( tocrel_offset_ret ) * tocrel_offset_ret = tocrel_offset ; return ( GET_CODE ( tocrel_base ) == UNSPEC && XINT ( tocrel_base , 1 ) == UNSPEC_TOCREL ) ; } </s>

Return true if OP is a toc pointer relative address ( the output of create_TOC_reference ) . If STRICT , do not match high part or non-split -mcmodel=large/medium toc pointer relative addresses .


<s> bool AArch64CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) == 0 ) continue ; ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , F . getCallingConv ( ) ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; AArch64FunctionInfo * FuncInfo = MF . getInfo < AArch64FunctionInfo > ( ) ; uint64_t StackOffset = Handler . StackUsed ; if ( F . isVarArg ( ) ) { auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; if ( ! Subtarget . isTargetDarwin ( ) ) { return false ; } StackOffset = alignTo ( Handler . StackUsed , Subtarget . isTargetILP32 ( ) ? 4 : 8 ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( 4 , StackOffset , true ) ) ; } if ( doesCalleeRestoreStack ( F . getCallingConv ( ) , MF . getTarget ( ) . Options . GuaranteedTailCallOpt ) ) { StackOffset = alignTo ( StackOffset , 16 ) ; FuncInfo -> setArgumentStackToRestore ( StackOffset ) ; } FuncInfo -> setBytesInStackArgArea ( StackOffset ) ; auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; if ( Subtarget . hasCustomCallingConv ( ) ) Subtarget . getRegisterInfo ( ) -> UpdateCustomCalleeSavedRegs ( MF ) ; handleMustTailForwardedRegisters ( MIRBuilder , AssignFn ) ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


"Unused function on X86. Otherwise need a test case."

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register .


<s> bool contains ( int32_t V ) const { return Min <= V && V <= Max && ( V - Offset ) % Align == 0 ; } </s>

contains - Returns true if this trace contains the given basic block .


<s>
bool
R600VectorRegMerger
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
if
(
skipFunction
(
Fn
.
getFunction
(
)
)
)
return
false
;
const
R600Subtarget
&
ST
=
Fn
.
getSubtarget
<
R600Subtarget
>
(
)
;
TII
=
ST
.
getInstrInfo
(
)
;
MRI
=
&
Fn
.
getRegInfo
(
)
;
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
MachineBasicBlock
*
MB
=
&
*
MBB
;
PreviousRegSeq
.
clear
(
)
;
PreviousRegSeqByReg
.
clear
(
)
;
PreviousRegSeqByUndefCount
.
clear
(
)
;
for
(
MachineBasicBlock
::
iterator
MII
=
MB
->
begin
(
)
,
MIIE
=
MB
->
end
(
)
;
MII
!=
MIIE
;
++
MII
)
{
MachineInstr
&
MI
=
*
MII
;
if
(
MI
.
getOpcode
(
)
!=
AMDGPU
::
REG_SEQUENCE
)
{
if
(
TII
->
get
(
MI
.
getOpcode
(
)
)
.
TSFlags
&
R600_InstFlag
::
TEX_INST
)
{
unsigned
Reg
=
MI
.
getOperand
(
1
)
.
getReg
(
)
;
for
(
MachineRegisterInfo
::
def_instr_iterator
It
=
MRI
->
def_instr_begin
(
Reg
)
,
E
=
MRI
->
def_instr_end
(
)
;
It
!=
E
;
++
It
)
{
RemoveMI
(
&
(
*
It
)
)
;
}
}
continue
;
}
RegSeqInfo
RSI
(
*
MRI
,
&
MI
)
;
unsigned
Reg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
if
(
!
areAllUsesSwizzeable
(
Reg
)
)
continue
;
DEBUG
(
{
dbgs
(
)
<<
"Trying to optimize "
;
MI
.
dump
(
)
;
}
)
;
RegSeqInfo
CandidateRSI
;
std
::
vector
<
std
::
pair
<
unsigned
,
unsigned
>>
RemapChan
;
DEBUG
(
dbgs
(
)
<<
"Using common slots...\n"
;
)
;
if
(
tryMergeUsingCommonSlot
(
RSI
,
CandidateRSI
,
RemapChan
)
)
{
RemoveMI
(
CandidateRSI
.
Instr
)
;
MII
=
RebuildVector
(
&
RSI
,
&
CandidateRSI
,
RemapChan
)
;
trackRSI
(
RSI
)
;
continue
;
}
DEBUG
(
dbgs
(
)
<<
"Using free slots...\n"
;
)
;
RemapChan
.
clear
(
)
;
if
(
tryMergeUsingFreeSlot
(
RSI
,
CandidateRSI
,
RemapChan
)
)
{
RemoveMI
(
CandidateRSI
.
Instr
)
;
MII
=
RebuildVector
(
&
RSI
,
&
CandidateRSI
,
RemapChan
)
;
trackRSI
(
RSI
)
;
continue
;
}
trackRSI
(
RSI
)
;
}
}
</s>

runOnMachineFunction - Emit the function body .

AMDGPU
R600
R600
R600
AMDGPU::REG_SEQUENCE
R600_InstFlag::TEX_INST
1
SI
0
"Trying to optimize "
SI
"Using common slots...\n"
SI
SI
SI
SI
SI
SI
SI
"Using free slots...\n"
SI
SI
SI
SI
SI
SI
SI
SI
SI


<s> static MachineBasicBlock * split ( MachineBasicBlock :: iterator I ) { MachineBasicBlock * MBB = ( * I ) . getParent ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; MachineBasicBlock * SuccMBB = MF -> CreateMachineBasicBlock ( ) ; auto MBBIter = ++ ( MBB -> getIterator ( ) ) ; MF -> insert ( MBBIter , SuccMBB ) ; SuccMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; MBB -> addSuccessor ( SuccMBB ) ; SuccMBB -> splice ( SuccMBB -> end ( ) , MBB , I , MBB -> end ( ) ) ; return SuccMBB ; } </s>

Split into substrings around the occurrences of a separator character .


<s> static bool aarch64_empty_mask_is_expensive ( unsigned ) { return false ; } </s>


<s> StringRef getPassName ( ) const override { return AVR_INSTRUMENT_FUNCTIONS_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s>
void
assignValueToAddress
(
unsigned
ValVReg
,
unsigned
Addr
,
uint64_t
Size
,
MachinePointerInfo
&
MPO
,
CCValAssign
&
VA
)
override
{
assert
(
Size
==
4
&&
"Unsupported size"
)
;
auto
MMO
=
MIRBuilder
.
getMF
(
)
.
getMachineMemOperand
(
MPO
,
MachineMemOperand
::
MOLoad
,
Size
,
0
)
;
MIRBuilder
.
buildLoad
(
ValVReg
,
Addr
,
*
MMO
)
;
}
</s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> AliasResult AMDGPUAAResult :: alias ( const MemoryLocation & LocA , const MemoryLocation & LocB ) { unsigned asA = LocA . Ptr -> getType ( ) -> getPointerAddressSpace ( ) ; unsigned asB = LocB . Ptr -> getType ( ) -> getPointerAddressSpace ( ) ; AliasResult Result = ASAliasRules . getAliasResult ( asA , asB ) ; if ( Result == NoAlias ) return Result ; return AAResultBase :: alias ( LocA , LocB ) ; } </s>

alias - If one of the pointers is to a global that we are tracking , and the other is some random pointer , we know there can not be an alias , because the address of the global is n't taken .


Function to check whether the OP is a valid load/store operation . This is a helper function for the predicates : 'nds32_load_multiple_operation ' and 'nds32_store_multiple_operation ' in predicates.md file . The OP is supposed to be a parallel rtx . For each element within this parallel rtx : ( set ( reg ) ( mem addr ) ) is the form for load operation . ( set ( mem addr ) ( reg ) ) is the form for store operation . We have to extract reg and mem of every element and check if the information is valid for multiple load/store operation .


<s> static void sh_print_operand_address ( FILE * stream , machine_mode , rtx x ) { switch ( GET_CODE ( x ) ) { case REG : case SUBREG : fprintf ( stream , "@%s" , reg_names [ true_regnum ( x ) ] ) ; break ; case PLUS : { rtx base = XEXP ( x , 0 ) ; rtx index = XEXP ( x , 1 ) ; switch ( GET_CODE ( index ) ) { case CONST_INT : fprintf ( stream , "@(%d,%s)" , ( int ) INTVAL ( index ) , reg_names [ true_regnum ( base ) ] ) ; break ; case REG : case SUBREG : { int base_num = true_regnum ( base ) ; int index_num = true_regnum ( index ) ; fprintf ( stream , "@(r0,%s)" , reg_names [ MAX ( base_num , index_num ) ] ) ; break ; } default : gcc_unreachable ( ) ; } } break ; case PRE_DEC : fprintf ( stream , "@-%s" , reg_names [ true_regnum ( XEXP ( x , 0 ) ) ] ) ; break ; case POST_INC : fprintf ( stream , "@%s+" , reg_names [ true_regnum ( XEXP ( x , 0 ) ) ] ) ; break ; default : x = mark_constant_pool_use ( x ) ; output_addr_const ( stream , x ) ; break ; } } </s>

Print the operand address in x to the stream .


"Combine common expressions into functions"


<s> bool X86FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || TRI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasOpaqueSPAdjustment ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) || MMI . hasEHFunclets ( ) || MMI . callsEHReturn ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || MFI . hasCopyImplyingStackAdjustment ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool MandarinAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , O ) ; case 'r' : break ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s>
void
WebAssemblyInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
OS
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
)
{
printInstruction
(
MI
,
OS
)
;
const
MCInstrDesc
&
Desc
=
MII
.
get
(
MI
->
getOpcode
(
)
)
;
if
(
Desc
.
isVariadic
(
)
)
for
(
auto
i
=
Desc
.
getNumOperands
(
)
,
e
=
MI
->
getNumOperands
(
)
;
i
<
e
;
++
i
)
{
if
(
i
!=
0
&&
(
(
MI
->
getOpcode
(
)
!=
WebAssembly
::
CALL_INDIRECT_VOID
&&
MI
->
getOpcode
(
)
!=
WebAssembly
::
CALL_INDIRECT_VOID_S
)
||
i
!=
Desc
.
getNumOperands
(
)
)
)
OS
<<
", "
;
printOperand
(
MI
,
i
,
OS
)
;
}
printAnnotation
(
OS
,
Annot
)
;
if
(
CommentStream
)
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
WebAssembly
::
LOOP
:
case
WebAssembly
::
LOOP_S
:
{
printAnnotation
(
OS
,
"label"
+
utostr
(
ControlFlowCounter
)
+
':'
)
;
ControlFlowStack
.
push_back
(
std
::
make_pair
(
ControlFlowCounter
++
,
true
)
)
;
break
;
}
case
WebAssembly
::
BLOCK
:
case
WebAssembly
::
BLOCK_S
:
ControlFlowStack
.
push_back
(
std
::
make_pair
(
ControlFlowCounter
++
,
false
)
)
;
break
;
case
WebAssembly
::
END_LOOP
:
case
WebAssembly
::
END_LOOP_S
:
if
(
!
ControlFlowStack
.
empty
(
)
)
ControlFlowStack
.
pop_back
(
)
;
break
;
case
WebAssembly
::
END_BLOCK
:
case
WebAssembly
::
END_BLOCK_S
:
if
(
!
ControlFlowStack
.
empty
(
)
)
printAnnotation
(
OS
,
"label"
+
utostr
(
ControlFlowStack
.
pop_back_val
(
)
.
first
)
+
':'
)
;
break
;
}
unsigned
NumFixedOperands
=
Desc
.
NumOperands
;
SmallSet
<
uint64_t
,
8
>
Printed
;
for
(
unsigned
i
=
0
,
e
=
MI
->
getNumOperands
(
)
;
i
<
e
;
++
i
)
{
if
(
!
(
i
<
NumFixedOperands
(
Desc
.
OpInfo
[
i
]
.
OperandType
==
WebAssembly
::
OPERAND_BASIC_BLOCK
)
:
(
Desc
.
TSFlags
&
WebAssemblyII
::
VariableOpImmediateIsLabel
)
)
)
continue
;
uint64_t
Depth
=
MI
->
getOperand
(
i
)
.
getImm
(
)
;
if
(
!
Printed
.
insert
(
Depth
)
.
second
)
continue
;
const
auto
&
Pair
=
ControlFlowStack
.
rbegin
(
)
[
Depth
]
;
printAnnotation
(
OS
,
utostr
(
Depth
)
+
": "
+
(
Pair
.
second
"up"
:
"down"
)
+
" to label"
+
utostr
(
Pair
.
first
)
)
;
}
}
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s> void GBZ80FrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; GBZ80MachineFunctionInfo * GBZ80FI = MF . getInfo < GBZ80MachineFunctionInfo > ( ) ; const GBZ80InstrInfo & TII = * static_cast < const GBZ80InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; uint64_t CallFrameSize = MFI -> getMaxCallFrameSize ( ) ; uint64_t FrameSize = GBZ80FI -> getCalleeSavedFrameSize ( ) ; uint64_t NumBytes = StackSize + CallFrameSize - FrameSize ; while ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == GBZ80 :: PUSH16r ) ) MBBI ++ ; if ( NumBytes || GBZ80FI -> isNeedFP ( ) ) { unsigned FP = TII . getRegisterInfo ( ) . getFrameRegister ( MF ) ; BuildMI ( MBB , MBBI , dl , TII . get ( GBZ80 :: LD16ri ) , FP ) . addImm ( - NumBytes ) ; BuildMI ( MBB , MBBI , dl , TII . get ( GBZ80 :: ADD16rSP ) , FP ) ; BuildMI ( MBB , MBBI , dl , TII . get ( GBZ80 :: LD16SPr ) ) . addReg ( FP ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool VEFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ; } </s>


Return an array that contains the bitmask target flag values and their names .


<s> static void mmix_target_asm_function_prologue ( FILE * ) { cfun -> machine -> in_prologue = 1 ; } </s>

Emit the function prologue . For simplicity while the port is still in a flux , we do it as text rather than the now preferred RTL way , as ( define_insn `` function_prologue '' ) . FIXME : Translate to RTL and/or optimize some of the DWARF 2 stuff .


<s> unsigned WebAssemblyTTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args ) { unsigned Cost = BasicTTIImplBase < WebAssemblyTTIImpl > :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( auto * VTy = dyn_cast < VectorType > ( Ty ) ) { switch ( Opcode ) { case Instruction :: LShr : case Instruction :: AShr : case Instruction :: Shl : if ( Opd2Info != TTI :: OK_UniformValue && Opd2Info != TTI :: OK_UniformConstantValue ) Cost = VTy -> getNumElements ( ) * ( TargetTransformInfo :: TCC_Basic + getArithmeticInstrCost ( Opcode , VTy -> getElementType ( ) ) + TargetTransformInfo :: TCC_Basic ) ; break ; } } return Cost ; } </s>

This is an approximation of reciprocal throughput of a math/logic op .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> static struct machine_function * avr_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function > ( ) ; } </s>

Function to set up the backend function structure .


"Unexpected instruction to emit with custom inserter"

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static int rank_for_reorder ( const void * x , const void * y ) { rtx tmp = * ( const rtx * ) y ; rtx tmp2 = * ( const rtx * ) x ; if ( SCHED_GROUP_P ( tmp ) != SCHED_GROUP_P ( tmp2 ) ) return SCHED_GROUP_P ( tmp2 ) ? 1 : - 1 ; return INSN_LUID ( tmp ) - INSN_LUID ( tmp2 ) ; } </s>

Comparison function for ready queue sorting .


<s>
void
mmix_asm_output_skip
(
FILE
*
stream
,
int
nbytes
)
{
fprintf
(
stream
,
"\tLOC @+%d\n"
,
nbytes
)
;
}
</s>


<s> bool ARMBaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const ARMFrameLowering * TFI = getFrameLowering ( MF ) ; const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; if ( ! MRI -> canReserveReg ( getFramePointerReg ( MF . getSubtarget < ARMSubtarget > ( ) ) ) ) return false ; if ( STI . isGPRegisterReserved ( BasePtr - ARM :: R0 ) ) return false ; if ( TFI -> hasReservedCallFrame ( MF ) ) return true ; return MRI -> canReserveReg ( BasePtr ) ; } </s>

True if the stack can be realigned for the target .


<s> static poly_uint16 aarch64_convert_sve_vector_bits ( aarch64_sve_vector_bits_enum value ) { if ( value == SVE_SCALABLE || ( value == SVE_128 && BYTES_BIG_ENDIAN ) ) return poly_uint16 ( 2 , 2 ) ; else return ( int ) value / 64 ; } </s>

Return the VG value associated with -msve-vector-bits= value VALUE .


<s> bool enableOrderedReductions ( ) const { return true ; } </s>

Return true if we should be enabling ordered reductions for the target .


<s> std :: pair < unsigned , const TargetRegisterClass * > BPFTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , & BPF :: GPRRegClass ) ; case 'w' : if ( HasAlu32 ) return std :: make_pair ( 0U , & BPF :: GPR32RegClass ) ; break ; default : break ; } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> static bool vspltis_constant ( rtx op , unsigned step , unsigned copies ) { machine_mode mode = GET_MODE ( op ) ; machine_mode inner = GET_MODE_INNER ( mode ) ; unsigned i ; unsigned nunits ; unsigned bitsize ; unsigned mask ; HOST_WIDE_INT val ; HOST_WIDE_INT splat_val ; HOST_WIDE_INT msb_val ; if ( mode == V2DImode || mode == V2DFmode || mode == V1TImode ) return false ; nunits = GET_MODE_NUNITS ( mode ) ; bitsize = GET_MODE_BITSIZE ( inner ) ; mask = GET_MODE_MASK ( inner ) ; val = const_vector_elt_as_int ( op , BYTES_BIG_ENDIAN ? nunits - 1 : 0 ) ; splat_val = val ; msb_val = val >= 0 ? 0 : - 1 ; for ( i = 2 ; i <= copies ; i *= 2 ) { HOST_WIDE_INT small_val ; bitsize /= 2 ; small_val = splat_val >> bitsize ; mask >>= bitsize ; if ( splat_val != ( ( HOST_WIDE_INT ) ( ( unsigned HOST_WIDE_INT ) small_val << bitsize ) | ( small_val & mask ) ) ) return false ; splat_val = small_val ; } if ( EASY_VECTOR_15 ( splat_val ) ) ; else if ( EASY_VECTOR_15_ADD_SELF ( splat_val ) && ( splat_val >= 0 || ( step == 1 && copies == 1 ) ) ) ; else if ( EASY_VECTOR_MSB ( splat_val , inner ) ) ; else return false ; for ( i = 1 ; i < nunits ; ++ i ) { HOST_WIDE_INT desired_val ; unsigned elt = BYTES_BIG_ENDIAN ? nunits - 1 - i : i ; if ( ( i & ( step - 1 ) ) == 0 ) desired_val = val ; else desired_val = msb_val ; if ( desired_val != const_vector_elt_as_int ( op , elt ) ) return false ; } return true ; } </s>

Return true if OP can be synthesized with a particular vspltisb , vspltish or vspltisw instruction . OP is a CONST_VECTOR . Which instruction is used depends on STEP and COPIES , one of which will be 1 . If COPIES > 1 , all items are set to the same value and contain COPIES replicas of the vsplt 's operand ; if STEP > 1 , one in STEP elements is set to the vsplt 's operand and the others are set to the value of the operand 's msb .


<s>
CCAssignFn
*
AMDGPUCallLowering
::
CCAssignFnForReturn
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
{
switch
(
CC
)
{
case
CallingConv
::
AMDGPU_KERNEL
:
case
CallingConv
::
SPIR_KERNEL
:
return
CC_AMDGPU_Kernel
;
case
CallingConv
::
AMDGPU_VS
:
case
CallingConv
::
AMDGPU_GS
:
case
CallingConv
::
AMDGPU_PS
:
case
CallingConv
::
AMDGPU_CS
:
case
CallingConv
::
AMDGPU_HS
:
case
CallingConv
::
AMDGPU_ES
:
case
CallingConv
::
AMDGPU_LS
:
return
RetCC_SI_Shader
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
case
CallingConv
::
Cold
:
return
RetCC_AMDGPU_Func
;
default
:
report_fatal_error
(
"Unsupported calling convention."
)
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .

AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
SI
AMDGPU
"Unsupported calling convention."


<s> static bool riscv_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_VECTOR ) return riscv_v_ext_vector_mode_p ( mode ) ; return false ; } </s>


<s> int memory_address_length ( rtx addr ) { struct ix86_address parts ; rtx base , index , disp ; int len ; int ok ; if ( GET_CODE ( addr ) == PRE_DEC || GET_CODE ( addr ) == POST_INC || GET_CODE ( addr ) == PRE_MODIFY || GET_CODE ( addr ) == POST_MODIFY ) return 0 ; ok = ix86_decompose_address ( addr , & parts ) ; gcc_assert ( ok ) ; if ( parts . base && GET_CODE ( parts . base ) == SUBREG ) parts . base = SUBREG_REG ( parts . base ) ; if ( parts . index && GET_CODE ( parts . index ) == SUBREG ) parts . index = SUBREG_REG ( parts . index ) ; base = parts . base ; index = parts . index ; disp = parts . disp ; len = 0 ; if ( base && ! index && ! disp ) { if ( addr == stack_pointer_rtx || addr == arg_pointer_rtx || addr == frame_pointer_rtx || addr == hard_frame_pointer_rtx ) len = 1 ; } else if ( disp && ! base && ! index ) len = 4 ; else { if ( disp ) { if ( GET_CODE ( disp ) == CONST_INT && CONST_OK_FOR_LETTER_P ( INTVAL ( disp ) , 'K' ) && base ) len = 1 ; else len = 4 ; } else if ( base == hard_frame_pointer_rtx ) len = 1 ; if ( index || base == stack_pointer_rtx || base == arg_pointer_rtx || base == frame_pointer_rtx ) len += 1 ; } return len ; } </s>

Calculate the length of the memory address in the instruction encoding . Does not include the one-byte modrm , opcode , or prefix .


<s> bool RISCVCallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < Register > VRegs , FunctionLoweringInfo & FLI ) const { MachineInstrBuilder Ret = MIRBuilder . buildInstrNoInsert ( RISCV :: PseudoRET ) ; if ( Val != nullptr ) { return false ; } MIRBuilder . insertInstr ( Ret ) ; return true ; } </s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> Optional < Instruction * > AArch64TTIImpl :: instCombineIntrinsic ( InstCombiner & IC , IntrinsicInst & II ) const { Intrinsic :: ID IID = II . getIntrinsicID ( ) ; switch ( IID ) { default : break ; case Intrinsic :: aarch64_neon_fmaxnm : case Intrinsic :: aarch64_neon_fminnm : return instCombineMaxMinNM ( IC , II ) ; case Intrinsic :: aarch64_sve_convert_from_svbool : return instCombineConvertFromSVBool ( IC , II ) ; case Intrinsic :: aarch64_sve_dup : return instCombineSVEDup ( IC , II ) ; case Intrinsic :: aarch64_sve_dup_x : return instCombineSVEDupX ( IC , II ) ; case Intrinsic :: aarch64_sve_cmpne : case Intrinsic :: aarch64_sve_cmpne_wide : return instCombineSVECmpNE ( IC , II ) ; case Intrinsic :: aarch64_sve_rdffr : return instCombineRDFFR ( IC , II ) ; case Intrinsic :: aarch64_sve_lasta : case Intrinsic :: aarch64_sve_lastb : return instCombineSVELast ( IC , II ) ; case Intrinsic :: aarch64_sve_cntd : return instCombineSVECntElts ( IC , II , 2 ) ; case Intrinsic :: aarch64_sve_cntw : return instCombineSVECntElts ( IC , II , 4 ) ; case Intrinsic :: aarch64_sve_cnth : return instCombineSVECntElts ( IC , II , 8 ) ; case Intrinsic :: aarch64_sve_cntb : return instCombineSVECntElts ( IC , II , 16 ) ; case Intrinsic :: aarch64_sve_ptest_any : case Intrinsic :: aarch64_sve_ptest_first : case Intrinsic :: aarch64_sve_ptest_last : return instCombineSVEPTest ( IC , II ) ; case Intrinsic :: aarch64_sve_mul : case Intrinsic :: aarch64_sve_fmul : return instCombineSVEVectorMul ( IC , II ) ; case Intrinsic :: aarch64_sve_fadd : return instCombineSVEVectorFAdd ( IC , II ) ; case Intrinsic :: aarch64_sve_fsub : return instCombineSVEVectorBinOp ( IC , II ) ; case Intrinsic :: aarch64_sve_tbl : return instCombineSVETBL ( IC , II ) ; case Intrinsic :: aarch64_sve_uunpkhi : case Intrinsic :: aarch64_sve_uunpklo : case Intrinsic :: aarch64_sve_sunpkhi : case Intrinsic :: aarch64_sve_sunpklo : return instCombineSVEUnpack ( IC , II ) ; case Intrinsic :: aarch64_sve_tuple_get : return instCombineSVETupleGet ( IC , II ) ; case Intrinsic :: aarch64_sve_zip1 : case Intrinsic :: aarch64_sve_zip2 : return instCombineSVEZip ( IC , II ) ; case Intrinsic :: aarch64_sve_ld1_gather_index : return instCombineLD1GatherIndex ( IC , II ) ; case Intrinsic :: aarch64_sve_st1_scatter_index : return instCombineST1ScatterIndex ( IC , II ) ; case Intrinsic :: aarch64_sve_ld1 : return instCombineSVELD1 ( IC , II , DL ) ; case Intrinsic :: aarch64_sve_st1 : return instCombineSVEST1 ( IC , II , DL ) ; case Intrinsic :: aarch64_sve_sdiv : return instCombineSVESDIV ( IC , II ) ; case Intrinsic :: aarch64_sve_sel : return instCombineSVESel ( IC , II ) ; case Intrinsic :: aarch64_sve_srshl : return instCombineSVESrshl ( IC , II ) ; } return None ; } </s>

Targets can implement their own combinations for target-specific intrinsics .


<s> static void mips_push_asm_switch_1 ( struct mips_asm_switch * asm_switch , const char * prefix , const char * suffix ) { if ( asm_switch -> nesting_level == 0 ) fprintf ( asm_out_file , "%s.set\tno%s%s" , prefix , asm_switch -> name , suffix ) ; asm_switch -> nesting_level ++ ; } </s>

Start a new block with the given asm switch enabled . If we need to print a directive , emit PREFIX before it and SUFFIX after it .


<s> bool R600InstrInfo :: PredicateInstruction ( MachineInstr * MI , const SmallVectorImpl < MachineOperand > & Pred ) const { int PIdx = MI -> findFirstPredOperandIdx ( ) ; if ( MI -> getOpcode ( ) == AMDGPU :: CF_ALU ) { MI -> getOperand ( 8 ) . setImm ( 0 ) ; return true ; } if ( MI -> getOpcode ( ) == AMDGPU :: DOT_4 ) { MI -> getOperand ( getOperandIdx ( * MI , AMDGPU :: OpName :: pred_sel_X ) ) . setReg ( Pred [ 2 ] . getReg ( ) ) ; MI -> getOperand ( getOperandIdx ( * MI , AMDGPU :: OpName :: pred_sel_Y ) ) . setReg ( Pred [ 2 ] . getReg ( ) ) ; MI -> getOperand ( getOperandIdx ( * MI , AMDGPU :: OpName :: pred_sel_Z ) ) . setReg ( Pred [ 2 ] . getReg ( ) ) ; MI -> getOperand ( getOperandIdx ( * MI , AMDGPU :: OpName :: pred_sel_W ) ) . setReg ( Pred [ 2 ] . getReg ( ) ) ; MachineInstrBuilder MIB ( * MI -> getParent ( ) -> getParent ( ) , MI ) ; MIB . addReg ( AMDGPU :: PREDICATE_BIT , RegState :: Implicit ) ; return true ; } if ( PIdx != - 1 ) { MachineOperand & PMO = MI -> getOperand ( PIdx ) ; PMO . setReg ( Pred [ 2 ] . getReg ( ) ) ; MachineInstrBuilder MIB ( * MI -> getParent ( ) -> getParent ( ) , MI ) ; MIB . addReg ( AMDGPU :: PREDICATE_BIT , RegState :: Implicit ) ; return true ; } return false ; } </s>

Convert the instruction into a predicated instruction .


<s>
SDValue
X86TargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
bool
Is64Bit
=
Subtarget
->
is64Bit
(
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_X86
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
CopyVT
=
VA
.
getValVT
(
)
;
if
(
(
CopyVT
==
MVT
::
f32
||
CopyVT
==
MVT
::
f64
)
&&
(
(
Is64Bit
||
Ins
[
i
]
.
Flags
.
isInReg
(
)
)
&&
!
Subtarget
->
hasSSE1
(
)
)
)
{
report_fatal_error
(
"SSE register return with SSE disabled"
)
;
}
SDValue
Val
;
if
(
VA
.
getLocReg
(
)
==
X86
::
ST0
||
VA
.
getLocReg
(
)
==
X86
::
ST1
)
{
if
(
isScalarFPTypeInSSEReg
(
VA
.
getValVT
(
)
)
)
CopyVT
=
MVT
::
f80
;
SDValue
Ops
[
]
=
{
Chain
,
InFlag
}
;
Chain
=
SDValue
(
DAG
.
getMachineNode
(
X86
::
FpPOP_RETVAL
,
dl
,
CopyVT
,
MVT
::
Other
,
MVT
::
Glue
,
Ops
)
,
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
if
(
CopyVT
!=
VA
.
getValVT
(
)
)
Val
=
DAG
.
getNode
(
ISD
::
FP_ROUND
,
dl
,
VA
.
getValVT
(
)
,
Val
,
DAG
.
getIntPtrConstant
(
1
)
)
;
}
else
{
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
CopyVT
,
InFlag
)
.
getValue
(
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
}
InFlag
=
Chain
.
getValue
(
2
)
;
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> void ARMELFMCAsmInfo :: setUseIntegratedAssembler ( bool Value ) { UseIntegratedAssembler = Value ; if ( ! UseIntegratedAssembler ) { DwarfRegNumForCFI = true ; } } </s>

Set whether assembly ( inline or otherwise ) should be parsed .


<s> void MipsTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; this -> TM = & TM ; } </s>

This method must be called before any actual lowering is done .


<s> void GCNHazardRecognizer :: AdvanceCycle ( ) { if ( ! CurrCycleInstr ) { EmittedInstrs . push_front ( nullptr ) ; return ; } if ( CurrCycleInstr -> isBundle ( ) ) { processBundle ( ) ; return ; } unsigned NumWaitStates = TII . getNumWaitStates ( * CurrCycleInstr ) ; if ( ! NumWaitStates ) { CurrCycleInstr = nullptr ; return ; } EmittedInstrs . push_front ( CurrCycleInstr ) ; for ( unsigned i = 1 , e = std :: min ( NumWaitStates , getMaxLookAhead ( ) ) ; i < e ; ++ i ) { EmittedInstrs . push_front ( nullptr ) ; } EmittedInstrs . resize ( getMaxLookAhead ( ) ) ; CurrCycleInstr = nullptr ; } </s>

AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled can not issue in the current cycle , either because of latency or resource conflicts .


PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static rtx rs6000_mask_atomic_subword ( rtx oldval , rtx newval , rtx mask ) { rtx x ; x = gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( x , gen_rtx_AND ( SImode , gen_rtx_NOT ( SImode , mask ) , oldval ) ) ) ; x = expand_simple_binop ( SImode , IOR , newval , x , x , 1 , OPTAB_LIB_WIDEN ) ; return x ; } </s>

A subroutine of the various atomic expanders . For sub-word operands , combine OLDVAL and NEWVAL via MASK . Returns a new pseduo .


<s> bool HexagonGenInsert :: removeDeadCode ( MachineDomTreeNode * N ) { bool Changed = false ; for ( auto * DTN : children < MachineDomTreeNode * > ( N ) ) Changed |= removeDeadCode ( DTN ) ; MachineBasicBlock * B = N -> getBlock ( ) ; std :: vector < MachineInstr * > Instrs ; for ( auto I = B -> rbegin ( ) , E = B -> rend ( ) ; I != E ; ++ I ) Instrs . push_back ( & * I ) ; for ( MachineInstr * MI : Instrs ) { unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == TargetOpcode :: LIFETIME_START || Opc == TargetOpcode :: LIFETIME_END ) continue ; bool Store = false ; if ( MI -> isInlineAsm ( ) || ! MI -> isSafeToMove ( nullptr , Store ) ) continue ; bool AllDead = true ; SmallVector < unsigned , 2 > Regs ; for ( const MachineOperand & MO : MI -> operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; Register R = MO . getReg ( ) ; if ( ! R . isVirtual ( ) || ! MRI -> use_nodbg_empty ( R ) ) { AllDead = false ; break ; } Regs . push_back ( R ) ; } if ( ! AllDead ) continue ; B -> erase ( MI ) ; for ( unsigned I = 0 , N = Regs . size ( ) ; I != N ; ++ I ) MRI -> markUsesInDebugValueAsUndef ( Regs [ I ] ) ; Changed = true ; } return Changed ; } </s>

Remove all dead instructions between the I and E .


<s> const MCInstrDesc & getMCOpcodeFromPseudo ( unsigned Opcode ) const { return get ( pseudoToMCOpcode ( Opcode ) ) ; } </s>

Return the descriptor of the target-specific machine instruction that corresponds to the specified pseudo or native opcode .


<s> int SystemZTTIImpl :: getIntImmCost ( Intrinsic :: ID IID , unsigned Idx , const APInt & Imm , Type * Ty ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; if ( BitSize > 64 ) return TTI :: TCC_Free ; switch ( IID ) { default : return TTI :: TCC_Free ; case Intrinsic :: sadd_with_overflow : case Intrinsic :: uadd_with_overflow : case Intrinsic :: ssub_with_overflow : case Intrinsic :: usub_with_overflow : if ( Idx == 1 && Imm . getBitWidth ( ) <= 64 ) { if ( isUInt < 32 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( isUInt < 32 > ( - Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; } break ; case Intrinsic :: smul_with_overflow : case Intrinsic :: umul_with_overflow : if ( Idx == 1 && Imm . getBitWidth ( ) <= 64 ) { if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; } break ; case Intrinsic :: experimental_stackmap : if ( ( Idx < 2 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; case Intrinsic :: experimental_patchpoint_void : case Intrinsic :: experimental_patchpoint_i64 : if ( ( Idx < 4 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; } return SystemZTTIImpl :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> ArrayRef < std :: pair < int , const char * >> MOSInstrInfo :: getSerializableTargetIndices ( ) const { static const std :: pair < int , const char * > Flags [ ] = { { MOS :: TI_STATIC_STACK , "mos-static-stack" } } ; return Flags ; } </s>

Return an array that contains the ids of the target indices ( used for the TargetIndex machine operand ) and their names .

MOS MOS MOS::TI_STATIC_STACK "mos-static-stack"


<s> static bool expand_vec_perm_vpermi2_vpshub2 ( struct expand_vec_perm_d * d ) { if ( ! TARGET_AVX512BW || ! ( d -> vmode == V64QImode ) ) return false ; if ( d -> testing_p ) return true ; struct expand_vec_perm_d ds [ 2 ] ; rtx rperm [ 128 ] , vperm , target0 , target1 ; unsigned int i , nelt ; machine_mode vmode ; nelt = d -> nelt ; vmode = V64QImode ; for ( i = 0 ; i < 2 ; i ++ ) { ds [ i ] = * d ; ds [ i ] . vmode = V32HImode ; ds [ i ] . nelt = 32 ; ds [ i ] . target = gen_reg_rtx ( V32HImode ) ; ds [ i ] . op0 = gen_lowpart ( V32HImode , d -> op0 ) ; ds [ i ] . op1 = gen_lowpart ( V32HImode , d -> op1 ) ; } for ( i = 0 ; i < nelt ; i ++ ) { ds [ i & 1 ] . perm [ i / 2 ] = d -> perm [ i ] / 2 ; if ( i & 1 ) { rperm [ i ] = constm1_rtx ; rperm [ i + 64 ] = GEN_INT ( ( i & 14 ) + ( d -> perm [ i ] & 1 ) ) ; } else { rperm [ i ] = GEN_INT ( ( i & 14 ) + ( d -> perm [ i ] & 1 ) ) ; rperm [ i + 64 ] = constm1_rtx ; } } bool ok = expand_vec_perm_1 ( & ds [ 0 ] ) ; gcc_assert ( ok ) ; ds [ 0 ] . target = gen_lowpart ( V64QImode , ds [ 0 ] . target ) ; ok = expand_vec_perm_1 ( & ds [ 1 ] ) ; gcc_assert ( ok ) ; ds [ 1 ] . target = gen_lowpart ( V64QImode , ds [ 1 ] . target ) ; vperm = gen_rtx_CONST_VECTOR ( V64QImode , gen_rtvec_v ( 64 , rperm ) ) ; vperm = force_reg ( vmode , vperm ) ; target0 = gen_reg_rtx ( V64QImode ) ; emit_insn ( gen_avx512bw_pshufbv64qi3 ( target0 , ds [ 0 ] . target , vperm ) ) ; vperm = gen_rtx_CONST_VECTOR ( V64QImode , gen_rtvec_v ( 64 , rperm + 64 ) ) ; vperm = force_reg ( vmode , vperm ) ; target1 = gen_reg_rtx ( V64QImode ) ; emit_insn ( gen_avx512bw_pshufbv64qi3 ( target1 , ds [ 1 ] . target , vperm ) ) ; emit_insn ( gen_iorv64qi3 ( d -> target , target0 , target1 ) ) ; return true ; } </s>

Implement arbitrary permutations of two V64QImode operands will 2 vpermi2w , 2 vpshufb and one vpor instruction .


<s> static unsigned long arm_compute_save_core_reg_mask ( void ) { unsigned int save_reg_mask = 0 ; unsigned long func_type = arm_current_func_type ( ) ; unsigned int reg ; if ( IS_NAKED ( func_type ) ) return 0 ; if ( TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM ) save_reg_mask |= ( 1 << ARM_HARD_FRAME_POINTER_REGNUM ) | ( 1 << IP_REGNUM ) | ( 1 << LR_REGNUM ) | ( 1 << PC_REGNUM ) ; save_reg_mask |= arm_compute_save_reg0_reg12_mask ( ) ; if ( df_regs_ever_live_p ( LR_REGNUM ) || ( save_reg_mask && optimize_size && ARM_FUNC_TYPE ( func_type ) == ARM_FT_NORMAL && ! crtl -> tail_call_emit && ! crtl -> calls_eh_return ) ) save_reg_mask |= 1 << LR_REGNUM ; if ( cfun -> machine -> lr_save_eliminated ) save_reg_mask &= ~ ( 1 << LR_REGNUM ) ; if ( TARGET_REALLY_IWMMXT && ( ( bit_count ( save_reg_mask ) + ARM_NUM_INTS ( crtl -> args . pretend_args_size + arm_compute_static_chain_stack_bytes ( ) ) ) % 2 ) != 0 ) { for ( reg = 4 ; reg <= 12 ; reg ++ ) if ( ( save_reg_mask & ( 1 << reg ) ) == 0 ) break ; if ( reg <= 12 ) save_reg_mask |= ( 1 << reg ) ; else { cfun -> machine -> sibcall_blocked = 1 ; save_reg_mask |= ( 1 << 3 ) ; } } if ( TARGET_THUMB2 && IS_NESTED ( func_type ) && flag_pic && ( save_reg_mask & THUMB2_WORK_REGS ) == 0 ) { reg = thumb_find_work_register ( 1 << 4 ) ; if ( ! call_used_or_fixed_reg_p ( reg ) ) save_reg_mask |= ( 1 << reg ) ; } return save_reg_mask ; } </s>

Compute a bit mask of which core registers need to be saved on the stack for the current function . This is used by arm_compute_frame_layout , which may add extra registers .


<s> SDNode * SparcDAGToDAGISel :: Select ( SDNode * N ) { DebugLoc dl = N -> getDebugLoc ( ) ; if ( N -> isMachineOpcode ( ) ) return NULL ; switch ( N -> getOpcode ( ) ) { default : break ; case SPISD :: GLOBAL_BASE_REG : return getGlobalBaseReg ( ) ; case ISD :: SDIV : case ISD :: UDIV : { SDValue DivLHS = N -> getOperand ( 0 ) ; SDValue DivRHS = N -> getOperand ( 1 ) ; SDValue TopPart ; if ( N -> getOpcode ( ) == ISD :: SDIV ) { TopPart = SDValue ( CurDAG -> getMachineNode ( SP :: SRAri , dl , MVT :: i32 , DivLHS , CurDAG -> getTargetConstant ( 31 , MVT :: i32 ) ) , 0 ) ; } else { TopPart = CurDAG -> getRegister ( SP :: G0 , MVT :: i32 ) ; } TopPart = SDValue ( CurDAG -> getMachineNode ( SP :: WRYrr , dl , MVT :: Flag , TopPart , CurDAG -> getRegister ( SP :: G0 , MVT :: i32 ) ) , 0 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: SDIV ? SP :: SDIVrr : SP :: UDIVrr ; return CurDAG -> SelectNodeTo ( N , Opcode , MVT :: i32 , DivLHS , DivRHS , TopPart ) ; } case ISD :: MULHU : case ISD :: MULHS : { SDValue MulLHS = N -> getOperand ( 0 ) ; SDValue MulRHS = N -> getOperand ( 1 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: MULHU ? SP :: UMULrr : SP :: SMULrr ; SDNode * Mul = CurDAG -> getMachineNode ( Opcode , dl , MVT :: i32 , MVT :: Flag , MulLHS , MulRHS ) ; return CurDAG -> SelectNodeTo ( N , SP :: RDY , MVT :: i32 , SDValue ( Mul , 1 ) ) ; return NULL ; } } return SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> static int rs6000_issue_rate ( void ) { if ( ! reload_completed ) return 1 ; switch ( rs6000_cpu_attr ) { case CPU_RIOS1 : case CPU_RS64A : case CPU_PPC601 : case CPU_PPC7450 : return 3 ; case CPU_PPC440 : case CPU_PPC603 : case CPU_PPC750 : case CPU_PPC7400 : case CPU_PPC8540 : return 2 ; case CPU_RIOS2 : case CPU_PPC604 : case CPU_PPC604E : case CPU_PPC620 : case CPU_PPC630 : return 4 ; case CPU_POWER4 : case CPU_POWER5 : return 5 ; default : return 1 ; } } </s>

Return how many instructions the machine can issue per cycle .


<s>
void
R600SchedStrategy
::
releaseTopNode
(
SUnit
*
SU
)
{
DEBUG
(
dbgs
(
)
<<
"Top Releasing "
;
SU
->
dump
(
DAG
)
;
)
;
}
</s>

SU has had all predecessor dependencies resolved .


Define the ` __builtin_va_list ' type for the ABI .


<s> const MCPhysReg * SIRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { CallingConv :: ID CC = MF -> getFunction ( ) . getCallingConv ( ) ; switch ( CC ) { case CallingConv :: C : case CallingConv :: Fast : case CallingConv :: Cold : case CallingConv :: AMDGPU_Gfx : return CSR_AMDGPU_HighRegs_SaveList ; default : { static const MCPhysReg NoCalleeSavedReg = AMDGPU :: NoRegister ; return & NoCalleeSavedReg ; } } } </s>

AMDGPU SI AMDGPU AMDGPU AMDGPU::NoRegister


"LR & FP are always handled in emitEpilogue"

"loadRegFromStackSlot didn't insert any code!"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> void ia64_expand_vecint_cmov ( rtx operands [ ] ) { enum machine_mode mode = GET_MODE ( operands [ 0 ] ) ; enum rtx_code code = GET_CODE ( operands [ 3 ] ) ; bool negate ; rtx cmp , x , ot , of ; cmp = gen_reg_rtx ( mode ) ; negate = ia64_expand_vecint_compare ( code , mode , cmp , operands [ 4 ] , operands [ 5 ] ) ; ot = operands [ 1 + negate ] ; of = operands [ 2 - negate ] ; if ( ot == CONST0_RTX ( mode ) ) { if ( of == CONST0_RTX ( mode ) ) { emit_move_insn ( operands [ 0 ] , ot ) ; return ; } x = gen_rtx_NOT ( mode , cmp ) ; x = gen_rtx_AND ( mode , x , of ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , x ) ) ; } else if ( of == CONST0_RTX ( mode ) ) { x = gen_rtx_AND ( mode , cmp , ot ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , x ) ) ; } else { rtx t , f ; t = gen_reg_rtx ( mode ) ; x = gen_rtx_AND ( mode , cmp , operands [ 1 + negate ] ) ; emit_insn ( gen_rtx_SET ( VOIDmode , t , x ) ) ; f = gen_reg_rtx ( mode ) ; x = gen_rtx_NOT ( mode , cmp ) ; x = gen_rtx_AND ( mode , x , operands [ 2 - negate ] ) ; emit_insn ( gen_rtx_SET ( VOIDmode , f , x ) ) ; x = gen_rtx_IOR ( mode , t , f ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , x ) ) ; } } </s>

Emit an integral vector conditional move .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM ) , OL ) , TargetABI ( computeTargetABI ( TT , CPU , Options ) ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) { if ( TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF || TargetTriple . getEnvironment ( ) == Triple :: EABIHF || TargetTriple . isOSWindows ( ) || TargetABI == ARMBaseTargetMachine :: ARM_ABI_AAPCS16 ) this -> Options . FloatABIType = FloatABI :: Hard ; else this -> Options . FloatABIType = FloatABI :: Soft ; } if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( ( TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABI || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF ) && ! ( TargetTriple . isOSWindows ( ) || TargetTriple . isOSDarwin ( ) ) ) this -> Options . EABIVersion = EABI :: GNU ; else this -> Options . EABIVersion = EABI :: EABI5 ; } initAsmInfo ( ) ; } </s>


<s>
const
char
*
getPassName
(
)
const
override
{
return
"X86 Assembly / Object Emitter"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> DecodeStatus BPFDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & VStream , raw_ostream & CStream ) const { uint64_t Insn ; DecodeStatus Result ; Result = readInstruction64 ( Bytes , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTableBPF64 , Instr , Insn , Address , this , STI ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; switch ( Instr . getOpcode ( ) ) { case BPF :: LD_imm64 : { if ( Bytes . size ( ) < 16 ) { Size = 0 ; return MCDisassembler :: Fail ; } Size = 16 ; uint64_t Hi = ( Bytes [ 12 ] << 0 ) | ( Bytes [ 13 ] << 8 ) | ( Bytes [ 14 ] << 16 ) | ( Bytes [ 15 ] << 24 ) ; auto & Op = Instr . getOperand ( 1 ) ; Op . setImm ( Make_64 ( Hi , Op . getImm ( ) ) ) ; break ; } case BPF :: LD_ABS_B : case BPF :: LD_ABS_H : case BPF :: LD_ABS_W : case BPF :: LD_IND_B : case BPF :: LD_IND_H : case BPF :: LD_IND_W : { auto Op = Instr . getOperand ( 0 ) ; Instr . clear ( ) ; Instr . addOperand ( MCOperand :: createReg ( BPF :: R6 ) ) ; Instr . addOperand ( Op ) ; break ; } } return Result ; } </s>

Returns the disassembly of a single instruction .


<s> bool riscv_split_symbol ( rtx temp , rtx addr , enum machine_mode mode , rtx * low_out ) { enum riscv_symbol_type symbol_type ; if ( ( GET_CODE ( addr ) == HIGH && mode == MAX_MACHINE_MODE ) || ! riscv_symbolic_constant_p ( addr , & symbol_type ) || riscv_symbol_insns ( symbol_type ) == 0 || ! riscv_split_symbol_type ( symbol_type ) ) return false ; if ( low_out ) switch ( symbol_type ) { case SYMBOL_ABSOLUTE : { rtx high = gen_rtx_HIGH ( Pmode , copy_rtx ( addr ) ) ; high = riscv_force_temporary ( temp , high ) ; * low_out = gen_rtx_LO_SUM ( Pmode , high , addr ) ; } break ; case SYMBOL_PCREL : { static unsigned seqno ; char buf [ 32 ] ; rtx label ; ssize_t bytes = snprintf ( buf , sizeof ( buf ) , ".LA%u" , seqno ) ; gcc_assert ( ( size_t ) bytes < sizeof ( buf ) ) ; label = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; SYMBOL_REF_FLAGS ( label ) |= SYMBOL_FLAG_LOCAL ; if ( temp == NULL ) temp = gen_reg_rtx ( Pmode ) ; if ( Pmode == DImode ) emit_insn ( gen_auipcdi ( temp , copy_rtx ( addr ) , GEN_INT ( seqno ) ) ) ; else emit_insn ( gen_auipcsi ( temp , copy_rtx ( addr ) , GEN_INT ( seqno ) ) ) ; * low_out = gen_rtx_LO_SUM ( Pmode , temp , label ) ; seqno ++ ; } break ; default : gcc_unreachable ( ) ; } return true ; } </s>

If MODE is MAX_MACHINE_MODE , ADDR appears as a move operand , otherwise it appears in a MEM of that mode . Return true if ADDR is a legitimate constant in that context and can be split into high and low parts . If so , and if LOW_OUT is nonnull , emit the high part and store the low part in * LOW_OUT . Leave * LOW_OUT unchanged otherwise . TEMP is as for riscv_force_temporary and is used to load the high part into a register . When MODE is MAX_MACHINE_MODE , the low part is guaranteed to be a legitimize SET_SRC for an .md pattern , otherwise the low part is guaranteed to be a legitimate address for mode MODE .


<s> static rtx loongarch_got_load_tls_ie ( rtx dest , rtx sym ) { return gen_got_load_tls_ie ( Pmode , dest , sym ) ; } </s>

Load an entry from the GOT for a TLS IE access .


<s> bool AMDGPUAlwaysInline :: runOnModule ( Module & M ) { std :: vector < GlobalAlias * > AliasesToRemove ; std :: vector < Function * > FuncsToClone ; for ( GlobalAlias & A : M . aliases ( ) ) { if ( Function * F = dyn_cast < Function > ( A . getAliasee ( ) ) ) { A . replaceAllUsesWith ( F ) ; AliasesToRemove . push_back ( & A ) ; } } if ( GlobalOpt ) { for ( GlobalAlias * A : AliasesToRemove ) { A -> eraseFromParent ( ) ; } } for ( Function & F : M ) { if ( ! F . hasLocalLinkage ( ) && ! F . isDeclaration ( ) && ! F . use_empty ( ) && ! F . hasFnAttribute ( Attribute :: NoInline ) ) FuncsToClone . push_back ( & F ) ; } for ( Function * F : FuncsToClone ) { ValueToValueMapTy VMap ; Function * NewFunc = CloneFunction ( F , VMap ) ; NewFunc -> setLinkage ( GlobalValue :: InternalLinkage ) ; F -> replaceAllUsesWith ( NewFunc ) ; } for ( Function & F : M ) { if ( F . hasLocalLinkage ( ) && ! F . hasFnAttribute ( Attribute :: NoInline ) ) { F . addFnAttr ( Attribute :: AlwaysInline ) ; } } return false ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> static rtx get_vl ( rtx_insn * rinsn ) { if ( has_vl_op ( rinsn ) ) { extract_insn_cached ( rinsn ) ; return recog_data . operand [ get_attr_vl_op_idx ( rinsn ) ] ; } return SET_DEST ( XVECEXP ( PATTERN ( rinsn ) , 0 , 0 ) ) ; } </s>


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , int64_t NumBytes , bool Is64Bit , const TargetInstrInfo & TII ) { bool isSub = NumBytes < 0 ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; unsigned Opc = isSub ? ( ( Offset < 128 ) ? ( Is64Bit ? X86 :: SUB64ri8 : X86 :: SUB32ri8 ) : ( Is64Bit ? X86 :: SUB64ri32 : X86 :: SUB32ri ) ) : ( ( Offset < 128 ) ? ( Is64Bit ? X86 :: ADD64ri8 : X86 :: ADD32ri8 ) : ( Is64Bit ? X86 :: ADD64ri32 : X86 :: ADD32ri ) ) ; uint64_t Chunk = ( 1LL << 31 ) - 1 ; DebugLoc DL = ( MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc :: getUnknownLoc ( ) ) ; while ( Offset ) { uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( ThisVal ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> void OrderedRegisterList :: remove ( unsigned VR ) { iterator L = llvm :: lower_bound ( Seq , VR , Ord ) ; if ( L != Seq . end ( ) ) Seq . erase ( L ) ; } </s>

remove - Remove the specified key/value pair from the map , but do not erase it .


<s>
static
void
v850_asm_trampoline_template
(
FILE
*
f
)
{
fprintf
(
f
,
"\tjarl .+4,r12\n"
)
;
fprintf
(
f
,
"\tld.w 12[r12],r19\n"
)
;
fprintf
(
f
,
"\tld.w 16[r12],r12\n"
)
;
fprintf
(
f
,
"\tjmp [r12]\n"
)
;
fprintf
(
f
,
"\tnop\n"
)
;
fprintf
(
f
,
"\t.long 0\n"
)
;
fprintf
(
f
,
"\t.long 0\n"
)
;
}
</s>

Worker function for TARGET_ASM_TRAMPOLINE_TEMPLATE .


<s> bool X86InstrInfo :: findCommutedOpIndices ( MachineInstr * MI , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { switch ( MI -> getOpcode ( ) ) { case X86 :: CMPPDrri : case X86 :: CMPPSrri : case X86 :: VCMPPDrri : case X86 :: VCMPPSrri : case X86 :: VCMPPDYrri : case X86 :: VCMPPSYrri : { unsigned Imm = MI -> getOperand ( 3 ) . getImm ( ) & 0x7 ; switch ( Imm ) { case 0x00 : case 0x03 : case 0x04 : case 0x07 : return fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , 1 , 2 ) ; } return false ; } default : if ( isFMA3 ( MI -> getOpcode ( ) ) ) return findFMA3CommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; } return false ; } </s>

Returns true iff the routine could find two commutable operands in the given machine instruction .


<s> MachineBasicBlock :: iterator RISCVFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { Register SPReg = RISCV :: X2 ; DebugLoc DL = MI -> getDebugLoc ( ) ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = MI -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { Amount = alignSPAdjust ( Amount ) ; if ( MI -> getOpcode ( ) == RISCV :: ADJCALLSTACKDOWN ) Amount = - Amount ; adjustReg ( MBB , MI , DL , SPReg , SPReg , Amount , MachineInstr :: NoFlags ) ; } } return MBB . erase ( MI ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool mep_expand_unary_intrinsic ( int ATTRIBUTE_UNUSED intrinsic , rtx * operands ATTRIBUTE_UNUSED ) { return false ; } </s>

Apply the given unary intrinsic to OPERANDS [ 1 ] and store it on OPERANDS [ 0 ] . Report an error if the instruction could not be synthesized . OPERANDS [ 1 ] is a register_operand . For sign and zero extensions , it may be smaller than SImode .


<s>
unsigned
ARMTargetLowering
::
getRegisterByName
(
const
char
*
RegName
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"sp"
,
ARM
::
SP
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .

ARM
ARM
"sp"
ARM::SP
0
"Invalid register name global variable"


<s> static bool mips_expand_msa_shuffle ( struct expand_vec_perm_d * d ) { rtx x , elts [ MAX_VECT_LEN ] ; rtvec v ; rtx_insn * insn ; unsigned i ; if ( ! ISA_HAS_MSA ) return false ; for ( i = 0 ; i < d -> nelt ; i ++ ) elts [ i ] = GEN_INT ( d -> perm [ i ] ) ; v = gen_rtvec_v ( d -> nelt , elts ) ; x = gen_rtx_PARALLEL ( VOIDmode , v ) ; if ( ! mips_const_vector_shuffle_set_p ( x , d -> vmode ) ) return false ; x = gen_rtx_VEC_SELECT ( d -> vmode , d -> op0 , x ) ; x = gen_rtx_SET ( d -> target , x ) ; insn = emit_insn ( x ) ; if ( recog_memoized ( insn ) < 0 ) { remove_insn ( insn ) ; return false ; } return true ; } </s>

Construct ( set target ( vec_select op0 ( parallel selector ) ) ) and return true if that 's a valid instruction in the active ISA .


<s> rtx mmix_eh_return_handler_rtx ( ) { return gen_rtx_REG ( Pmode , MMIX_INCOMING_RETURN_ADDRESS_REGNUM ) ; } </s>


"Instruction should be in a basic block!"

"Generic instruction has unexpected implicit operands\n"

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s>
InstructionCost
X86TTIImpl
::
getScalarizationOverhead
(
VectorType
*
Ty
,
const
APInt
&
DemandedElts
,
bool
Insert
,
bool
Extract
)
{
InstructionCost
Cost
=
0
;
if
(
Insert
)
{
std
::
pair
<
InstructionCost
,
MVT
>
LT
=
TLI
->
getTypeLegalizationCost
(
DL
,
Ty
)
;
MVT
MScalarTy
=
LT
.
second
.
getScalarType
(
)
;
if
(
(
MScalarTy
==
MVT
::
i16
&&
ST
->
hasSSE2
(
)
)
||
(
MScalarTy
.
isInteger
(
)
&&
ST
->
hasSSE41
(
)
)
||
(
MScalarTy
==
MVT
::
f32
&&
ST
->
hasSSE41
(
)
)
)
{
if
(
LT
.
second
.
getSizeInBits
(
)
<=
128
)
{
Cost
+=
BaseT
::
getScalarizationOverhead
(
Ty
,
DemandedElts
,
Insert
,
false
)
;
}
else
{
const
int
CostValue
=
*
LT
.
first
.
getValue
(
)
;
assert
(
CostValue
>=
0
&&
"Negative cost!"
)
;
unsigned
Num128Lanes
=
LT
.
second
.
getSizeInBits
(
)
/
128
*
CostValue
;
unsigned
NumElts
=
LT
.
second
.
getVectorNumElements
(
)
*
CostValue
;
APInt
WidenedDemandedElts
=
DemandedElts
.
zextOrSelf
(
NumElts
)
;
unsigned
Scale
=
NumElts
/
Num128Lanes
;
for
(
unsigned
I
=
0
;
I
<
NumElts
;
I
+=
Scale
)
{
APInt
Mask
=
WidenedDemandedElts
.
getBitsSet
(
NumElts
,
I
,
I
+
Scale
)
;
APInt
MaskedDE
=
Mask
&
WidenedDemandedElts
;
unsigned
Population
=
MaskedDE
.
countPopulation
(
)
;
Cost
+=
(
Population
>
0
&&
Population
!=
Scale
&&
I
%
LT
.
second
.
getVectorNumElements
(
)
!=
0
)
;
Cost
+=
Population
>
0
;
}
Cost
+=
DemandedElts
.
countPopulation
(
)
;
if
(
MScalarTy
==
MVT
::
f32
)
for
(
unsigned
i
=
0
,
e
=
cast
<
FixedVectorType
>
(
Ty
)
->
getNumElements
(
)
;
i
<
e
;
i
+=
4
)
if
(
DemandedElts
[
i
]
)
Cost
;
}
}
else
if
(
LT
.
second
.
isVector
(
)
)
{
if
(
Ty
->
isIntOrIntVectorTy
(
)
)
Cost
+=
DemandedElts
.
countPopulation
(
)
;
unsigned
NumElts
=
LT
.
second
.
getVectorNumElements
(
)
;
unsigned
Pow2Elts
=
PowerOf2Ceil
(
cast
<
FixedVectorType
>
(
Ty
)
->
getNumElements
(
)
)
;
Cost
+=
(
std
::
min
<
unsigned
>
(
NumElts
,
Pow2Elts
)
1
)
*
LT
.
first
;
}
}
if
(
Extract
)
Cost
+=
BaseT
::
getScalarizationOverhead
(
Ty
,
DemandedElts
,
false
,
Extract
)
;
return
Cost
;
}
</s>

Estimate the overhead of scalarizing an instruction .


<s> static unsigned int ix86_autovectorize_vector_modes ( vector_modes * modes , bool all ) { if ( TARGET_AVX512F && ! TARGET_PREFER_AVX256 ) { modes -> safe_push ( V64QImode ) ; modes -> safe_push ( V32QImode ) ; modes -> safe_push ( V16QImode ) ; } else if ( TARGET_AVX512F && all ) { modes -> safe_push ( V32QImode ) ; modes -> safe_push ( V16QImode ) ; modes -> safe_push ( V64QImode ) ; } else if ( TARGET_AVX && ! TARGET_PREFER_AVX128 ) { modes -> safe_push ( V32QImode ) ; modes -> safe_push ( V16QImode ) ; } else if ( TARGET_AVX && all ) { modes -> safe_push ( V16QImode ) ; modes -> safe_push ( V32QImode ) ; } else if ( TARGET_SSE2 ) modes -> safe_push ( V16QImode ) ; if ( TARGET_MMX_WITH_SSE ) modes -> safe_push ( V8QImode ) ; if ( TARGET_SSE2 ) modes -> safe_push ( V4QImode ) ; return 0 ; } </s>

If AVX is enabled then try vectorizing with both 256bit and 128bit vectors . If AVX512F is enabled then try vectorizing with 512bit , 256bit and 128bit vectors .


<s> unsigned DLXInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { return 1 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> const TargetRegisterClass * ARMBaseRegisterInfo :: getPointerRegClass ( unsigned Kind ) const { return ARM :: GPRRegisterClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> static void h8300_reorg ( void ) { if ( flag_delayed_branch ) shorten_branches ( get_insns ( ) ) ; } </s>

Delayed-branch scheduling is more effective if we have some idea how long each instruction will be . Use a shorten_branches pass to get an initial estimate .


<s>
unsigned
VEMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
if
(
MO
.
isImm
(
)
)
return
MO
.
getImm
(
)
;
assert
(
MO
.
isExpr
(
)
)
;
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
if
(
const
VEMCExpr
*
SExpr
=
dyn_cast
<
VEMCExpr
>
(
Expr
)
)
{
MCFixupKind
Kind
=
(
MCFixupKind
)
SExpr
->
getFixupKind
(
)
;
Fixups
.
push_back
(
MCFixup
::
create
(
0
,
Expr
,
Kind
)
)
;
return
0
;
}
int64_t
Res
;
if
(
Expr
->
evaluateAsAbsolute
(
Res
)
)
return
Res
;
llvm_unreachable
(
"Unhandled expression!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> const MipsSubtarget * MipsTargetMachine :: getSubtargetImpl ( const Function & F ) const { AttributeSet FnAttrs = F . getAttributes ( ) ; Attribute CPUAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "target-cpu" ) ; Attribute FSAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool hasMips16Attr = ! FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "mips16" ) . hasAttribute ( Attribute :: None ) ; bool hasNoMips16Attr = ! FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "nomips16" ) . hasAttribute ( Attribute :: None ) ; Attribute SFAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "use-soft-float" ) ; bool softFloat = ! SFAttr . hasAttribute ( Attribute :: None ) ? SFAttr . getValueAsString ( ) == "true" : Options . UseSoftFloat ; if ( hasMips16Attr ) FS += FS . empty ( ) ? "+mips16" : ",+mips16" ; else if ( hasNoMips16Attr ) FS += FS . empty ( ) ? "-mips16" : ",-mips16" ; auto & I = SubtargetMap [ CPU + FS + ( softFloat ? "use-soft-float=true" : "use-soft-float=false" ) ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < MipsSubtarget > ( TargetTriple , CPU , FS , isLittle , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

Mips Mips Mips "target-cpu" "target-features" Mips "mips16" Mips "nomips16" "use-soft-float" "true" Mips "+mips16" ",+mips16" Mips "-mips16" ",-mips16" "use-soft-float=true" "use-soft-float=false" Mips


<s> bool aarch64_address_valid_for_prefetch_p ( rtx x , bool strict_p ) { struct aarch64_address_info addr ; bool res = aarch64_classify_address ( & addr , x , DImode , strict_p ) ; if ( ! res ) return false ; return addr . type != ADDRESS_REG_WB ; } </s>

Return true if the address X is valid for a PRFM instruction . STRICT_P is true if we should do strict checking with aarch64_classify_address .


<s> bool SPUFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MFI -> getStackSize ( ) && ( DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool PPCTargetLowering :: shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 || BitSize > 64 ) return false ; return true ; } </s>

Returns true if it is beneficial to convert a load of a constant to just the constant itself .


<s> StringRef getType ( ) { return CurType ; } </s>

Overload to return most specific vector type .


<s> X86Subtarget :: X86Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , X86TargetMachine & TM , unsigned StackAlignOverride ) : X86GenSubtargetInfo ( TT , CPU , FS ) , X86ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , DL ( computeDataLayout ( * this ) ) , TSInfo ( DL ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM ) , FrameLowering ( TargetFrameLowering :: StackGrowsDown , getStackAlignment ( ) , is64Bit ( ) ? - 8 : - 4 ) , JITInfo ( hasSSE1 ( ) ) { } </s>

This constructor initializes the data members to match that of the specified triple .


"********** Prepare For LiveIntervals **********\n"

"LiveIntervals shouldn't be active yet!"

runOnMachineFunction - Emit the function body .