<s> void RISCVTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { if ( Constraint . length ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'I' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) { uint64_t CVal = C -> getSExtValue ( ) ; if ( isInt < 12 > ( CVal ) ) Ops . push_back ( DAG . getTargetConstant ( CVal , SDLoc ( Op ) , Subtarget . getXLenVT ( ) ) ) ; } return ; case 'J' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( C -> getZExtValue ( ) == 0 ) Ops . push_back ( DAG . getTargetConstant ( 0 , SDLoc ( Op ) , Subtarget . getXLenVT ( ) ) ) ; return ; case 'K' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) { uint64_t CVal = C -> getZExtValue ( ) ; if ( isUInt < 5 > ( CVal ) ) Ops . push_back ( DAG . getTargetConstant ( CVal , SDLoc ( Op ) , Subtarget . getXLenVT ( ) ) ) ; } return ; case 'S' : if ( const auto * GA = dyn_cast < GlobalAddressSDNode > ( Op ) ) { Ops . push_back ( DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , SDLoc ( Op ) , GA -> getValueType ( 0 ) ) ) ; } else if ( const auto * BA = dyn_cast < BlockAddressSDNode > ( Op ) ) { Ops . push_back ( DAG . getTargetBlockAddress ( BA -> getBlockAddress ( ) , BA -> getValueType ( 0 ) ) ) ; } return ; default : break ; } } TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; } </s>

Lower the specified operand into the Ops vector .


"PPC pre-emit peephole: erasing instruction: "

runOnMachineFunction - Emit the function body .


<s>
static
tree
m68hc11_handle_page0_attribute
(
tree
*
node
,
tree
name
,
tree
args
ATTRIBUTE_UNUSED
,
int
flags
ATTRIBUTE_UNUSED
,
bool
*
no_add_attrs
)
{
tree
decl
=
*
node
;
if
(
TREE_STATIC
(
decl
)
||
DECL_EXTERNAL
(
decl
)
)
{
DECL_SECTION_NAME
(
decl
)
=
build_string
(
6
,
".page0"
)
;
}
else
{
warning
(
OPT_Wattributes
,
"%qs attribute ignored"
,
IDENTIFIER_POINTER
(
name
)
)
;
*
no_add_attrs
=
true
;
}
return
NULL_TREE
;
}
</s>

Handle an `` tiny_data '' attribute ; arguments as in struct attribute_spec.handler .


<s>
const
char
*
avr_out_sign_extend
(
rtx_insn
*
insn
,
rtx
*
xop
,
int
*
plen
)
{
unsigned
n_src
=
GET_MODE_SIZE
(
GET_MODE
(
xop
[
1
]
)
)
;
unsigned
n_dest
=
GET_MODE_SIZE
(
GET_MODE
(
xop
[
0
]
)
)
;
rtx
r_msb
=
all_regs_rtx
[
REGNO
(
xop
[
1
]
)
+
n_src
1
]
;
if
(
plen
)
*
plen
=
0
;
if
(
REGNO
(
xop
[
0
]
)
!=
REGNO
(
xop
[
1
]
)
)
{
gcc_assert
(
n_src
<=
2
)
;
if
(
n_src
==
2
)
avr_asm_len
(
AVR_HAVE_MOVW
"movw %0,%1"
:
"mov %B0,%B1"
,
xop
,
plen
,
1
)
;
if
(
n_src
==
1
||
!
AVR_HAVE_MOVW
)
avr_asm_len
(
"mov %A0,%A1"
,
xop
,
plen
,
1
)
;
}
if
(
REGNO
(
xop
[
0
]
)
==
REGNO
(
xop
[
1
]
)
||
!
reg_unused_after
(
insn
,
r_msb
)
)
{
avr_asm_len
(
"mov __tmp_reg__,%0"
,
&
r_msb
,
plen
,
1
)
;
r_msb
=
tmp_reg_rtx
;
}
avr_asm_len
(
"lsl %0"
,
&
r_msb
,
plen
,
1
)
;
for
(
unsigned
n
=
n_src
;
n
<
n_dest
;
n
++
)
avr_asm_len
(
"sbc %0,%0"
,
&
all_regs_rtx
[
REGNO
(
xop
[
0
]
)
+
n
]
,
plen
,
1
)
;
return
""
;
}
</s>

Output sign extension from XOP [ 1 ] to XOP [ 0 ] and return `` '' . If PLEN == NULL , print assembler instructions to perform the operation ; otherwise , set * PLEN to the length of the instruction sequence ( in words ) as printed with PLEN == NULL .


<s> void AMDGPURegisterBankInfo :: split64BitValueForMapping ( MachineIRBuilder & B , SmallVector < Register , 2 > & Regs , LLT HalfTy , unsigned Reg ) const { assert ( HalfTy . getSizeInBits ( ) == 32 ) ; MachineRegisterInfo * MRI = B . getMRI ( ) ; unsigned LoLHS = MRI -> createGenericVirtualRegister ( HalfTy ) ; unsigned HiLHS = MRI -> createGenericVirtualRegister ( HalfTy ) ; const RegisterBank * Bank = getRegBank ( Reg , * MRI , * TRI ) ; MRI -> setRegBank ( LoLHS , * Bank ) ; MRI -> setRegBank ( HiLHS , * Bank ) ; Regs . push_back ( LoLHS ) ; Regs . push_back ( HiLHS ) ; B . buildInstr ( AMDGPU :: G_UNMERGE_VALUES ) . addDef ( LoLHS ) . addDef ( HiLHS ) . addUse ( Reg ) ; } </s>

Split 64-bit value Reg into two 32-bit halves and populate them into Regs .


<s> int avr_simplify_comparison_p ( enum machine_mode mode , RTX_CODE operator , rtx x ) { unsigned int max = ( mode == QImode ? 0xff : mode == HImode ? 0xffff : mode == SImode ? 0xffffffff : 0 ) ; if ( max && operator && GET_CODE ( x ) == CONST_INT ) { if ( unsigned_condition ( operator ) != operator ) max >>= 1 ; if ( max != ( INTVAL ( x ) & max ) && INTVAL ( x ) != 0xff ) return 1 ; } return 0 ; } </s>

Return 0 if undefined , 1 if always true or always false .


<s> static int arc_save_callee_enter ( uint64_t gmask , bool save_blink , bool save_fp , HOST_WIDE_INT offset ) { int start_reg = ENTER_LEAVE_START_REG ; int end_reg = ENTER_LEAVE_END_REG ; int regno , indx , off , nregs ; rtx insn , reg , mem ; int frame_allocated = 0 ; for ( regno = start_reg ; regno <= end_reg && ( gmask & ( 1ULL << regno ) ) ; ) regno ++ ; end_reg = regno - 1 ; nregs = end_reg - start_reg + 1 ; nregs += save_blink ? 1 : 0 ; nregs += save_fp ? 1 : 0 ; if ( offset ) frame_stack_add ( offset ) ; insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nregs + ( save_fp ? 1 : 0 ) + 1 ) ) ; indx = 0 ; reg = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - nregs * UNITS_PER_WORD ) ) ; RTX_FRAME_RELATED_P ( reg ) = 1 ; XVECEXP ( insn , 0 , indx ++ ) = reg ; off = nregs * UNITS_PER_WORD ; if ( save_blink ) { reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , off ) ) ; XVECEXP ( insn , 0 , indx ) = gen_rtx_SET ( mem , reg ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , 0 , indx ++ ) ) = 1 ; off -= UNITS_PER_WORD ; save_blink = false ; } for ( regno = start_reg ; regno <= end_reg ; regno ++ , indx ++ , off -= UNITS_PER_WORD ) { reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , off ) ) ; XVECEXP ( insn , 0 , indx ) = gen_rtx_SET ( mem , reg ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , 0 , indx ) ) = 1 ; gmask = gmask & ~ ( 1ULL << regno ) ; } if ( save_fp ) { mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , off ) ) ; XVECEXP ( insn , 0 , indx ) = gen_rtx_SET ( mem , hard_frame_pointer_rtx ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , 0 , indx ++ ) ) = 1 ; off -= UNITS_PER_WORD ; XVECEXP ( insn , 0 , indx ) = gen_rtx_SET ( hard_frame_pointer_rtx , stack_pointer_rtx ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , 0 , indx ++ ) ) = 1 ; save_fp = false ; } gcc_assert ( off == 0 ) ; insn = frame_insn ( insn ) ; add_reg_note ( insn , REG_INC , stack_pointer_rtx ) ; frame_allocated = nregs * UNITS_PER_WORD ; return frame_allocated - offset ; } </s>

ARC prologue , save the registers using enter instruction . Leave instruction can also save $ blink ( SAVE_BLINK ) and $ fp ( SAVE_FP ) register .


<s> DecodeStatus BPFDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CStream ) const { bool IsLittleEndian = getContext ( ) . getAsmInfo ( ) -> isLittleEndian ( ) ; uint64_t Insn , Hi ; DecodeStatus Result ; Result = readInstruction64 ( Bytes , Address , Size , Insn , IsLittleEndian ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; uint8_t InstClass = getInstClass ( Insn ) ; uint8_t InstMode = getInstMode ( Insn ) ; if ( ( InstClass == BPF_LDX || InstClass == BPF_STX ) && getInstSize ( Insn ) != BPF_DW && ( InstMode == BPF_MEM || InstMode == BPF_ATOMIC ) && STI . getFeatureBits ( ) [ BPF :: ALU32 ] ) Result = decodeInstruction ( DecoderTableBPFALU3264 , Instr , Insn , Address , this , STI ) ; else Result = decodeInstruction ( DecoderTableBPF64 , Instr , Insn , Address , this , STI ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; switch ( Instr . getOpcode ( ) ) { case BPF :: LD_imm64 : case BPF :: LD_pseudo : { if ( Bytes . size ( ) < 16 ) { Size = 0 ; return MCDisassembler :: Fail ; } Size = 16 ; if ( IsLittleEndian ) Hi = ( Bytes [ 12 ] << 0 ) | ( Bytes [ 13 ] << 8 ) | ( Bytes [ 14 ] << 16 ) | ( Bytes [ 15 ] << 24 ) ; else Hi = ( Bytes [ 12 ] << 24 ) | ( Bytes [ 13 ] << 16 ) | ( Bytes [ 14 ] << 8 ) | ( Bytes [ 15 ] << 0 ) ; auto & Op = Instr . getOperand ( 1 ) ; Op . setImm ( Make_64 ( Hi , Op . getImm ( ) ) ) ; break ; } case BPF :: LD_ABS_B : case BPF :: LD_ABS_H : case BPF :: LD_ABS_W : case BPF :: LD_IND_B : case BPF :: LD_IND_H : case BPF :: LD_IND_W : { auto Op = Instr . getOperand ( 0 ) ; Instr . clear ( ) ; Instr . addOperand ( MCOperand :: createReg ( BPF :: R6 ) ) ; Instr . addOperand ( Op ) ; break ; } } return Result ; } </s>

Returns the disassembly of a single instruction .


<s> void XNCMFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


<s> int nios2_can_use_return_insn ( void ) { if ( ! reload_completed || crtl -> profile ) return 0 ; return nios2_compute_frame_layout ( ) == 0 ; } </s>

Return nonzero if this function is known to have a null epilogue . This allows the optimizer to omit jumps to jumps if no stack was created .


<s> bool HexagonFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF -> getTarget ( ) . getInstrInfo ( ) ; if ( CSI . empty ( ) ) { return false ; } bool ContiguousRegs = true ; for ( unsigned i = 0 ; i < CSI . size ( ) ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; unsigned SuperReg = uniqueSuperReg ( Reg , TRI ) ; bool CanUseDblStore = false ; const TargetRegisterClass * SuperRegClass = nullptr ; if ( ContiguousRegs && ( i < CSI . size ( ) - 1 ) ) { unsigned SuperRegNext = uniqueSuperReg ( CSI [ i + 1 ] . getReg ( ) , TRI ) ; SuperRegClass = TRI -> getMinimalPhysRegClass ( SuperReg ) ; CanUseDblStore = ( SuperRegNext == SuperReg ) ; } if ( CanUseDblStore ) { TII . storeRegToStackSlot ( MBB , MI , SuperReg , true , CSI [ i + 1 ] . getFrameIdx ( ) , SuperRegClass , TRI ) ; MBB . addLiveIn ( SuperReg ) ; ++ i ; } else { ContiguousRegs = false ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; MBB . addLiveIn ( Reg ) ; } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
llvm_unreachable
(
"getFixupKindInfo() unimplemented"
)
;
}
</s>


<s> bool AMDGPUTargetELFStreamer :: EmitHSAMetadata ( std :: shared_ptr < msgpack :: Node > & HSAMetadataRoot , bool Strict ) { V3 :: MetadataVerifier Verifier ( Strict ) ; if ( ! Verifier . verify ( * HSAMetadataRoot ) ) return false ; std :: string HSAMetadataString ; raw_string_ostream StrOS ( HSAMetadataString ) ; msgpack :: Writer MPWriter ( StrOS ) ; HSAMetadataRoot -> write ( MPWriter ) ; auto & Context = getContext ( ) ; auto * DescBegin = Context . createTempSymbol ( ) ; auto * DescEnd = Context . createTempSymbol ( ) ; auto * DescSZ = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( DescEnd , Context ) , MCSymbolRefExpr :: create ( DescBegin , Context ) , Context ) ; EmitNote ( ElfNote :: NoteNameV3 , DescSZ , ELF :: NT_AMDGPU_METADATA , [ & ] ( MCELFStreamer & OS ) { OS . EmitLabel ( DescBegin ) ; OS . EmitBytes ( StrOS . str ( ) ) ; OS . EmitLabel ( DescEnd ) ; } ) ; return true ; } </s>


<s> bool isImm ( ) const { return Kind == k_Immediate ; } </s>


<s> static void maybe_set_link_compat ( void ) { } </s>

Checks if logical names are defined for setting system library path and linker program to enable compatibility with earlier VMS versions .


<s> bool HexagonRemoveExtendArgs :: runOnFunction ( Function & F ) { unsigned Idx = 1 ; for ( Function :: arg_iterator AI = F . arg_begin ( ) , AE = F . arg_end ( ) ; AI != AE ; ++ AI , ++ Idx ) { if ( F . getAttributes ( ) . hasAttribute ( Idx , Attribute :: SExt ) ) { Argument * Arg = AI ; if ( ! isa < PointerType > ( Arg -> getType ( ) ) ) { for ( auto UI = Arg -> user_begin ( ) ; UI != Arg -> user_end ( ) ; ) { if ( isa < SExtInst > ( * UI ) ) { Instruction * I = cast < Instruction > ( * UI ) ; SExtInst * SI = new SExtInst ( Arg , I -> getType ( ) ) ; assert ( EVT :: getEVT ( SI -> getType ( ) ) == ( EVT :: getEVT ( I -> getType ( ) ) ) ) ; ++ UI ; I -> replaceAllUsesWith ( SI ) ; Instruction * First = F . getEntryBlock ( ) . begin ( ) ; SI -> insertBefore ( First ) ; I -> eraseFromParent ( ) ; } else { ++ UI ; } } } } } return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void fr30_expand_prologue ( void ) { int regno ; rtx insn ; if ( ! current_frame_info . initialised ) fr30_compute_frame_size ( 0 , 0 ) ; gcc_assert ( current_frame_info . total_size || ! current_frame_info . gmask ) ; if ( current_frame_info . pretend_size ) { int regs_to_save = current_frame_info . pretend_size / UNITS_PER_WORD ; for ( regno = FIRST_ARG_REGNUM + FR30_NUM_ARG_REGS ; regno -- , regs_to_save -- ; ) { insn = emit_insn ( gen_movsi_push ( gen_rtx_REG ( Pmode , regno ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } if ( current_frame_info . gmask ) { for ( regno = STACK_POINTER_REGNUM ; regno -- ; ) { if ( ( current_frame_info . gmask & ( 1 << regno ) ) != 0 ) { insn = emit_insn ( gen_movsi_push ( gen_rtx_REG ( Pmode , regno ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } } if ( current_frame_info . save_rp ) { insn = emit_insn ( gen_movsi_push ( gen_rtx_REG ( Pmode , RETURN_POINTER_REGNUM ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } if ( current_frame_info . save_fp ) { if ( current_frame_info . frame_size < ( ( 1 << 10 ) - UNITS_PER_WORD ) ) { int enter_size = current_frame_info . frame_size + UNITS_PER_WORD ; rtx pattern ; insn = emit_insn ( gen_enter_func ( GEN_INT ( enter_size ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) == PARALLEL ) { int x ; for ( x = XVECLEN ( pattern , 0 ) ; x -- ; ) { rtx part = XVECEXP ( pattern , 0 , x ) ; if ( ! frame_pointer_needed && GET_CODE ( part ) == SET && REGNO ( SET_DEST ( part ) ) == HARD_FRAME_POINTER_REGNUM ) RTX_FRAME_RELATED_P ( part ) = 0 ; else RTX_FRAME_RELATED_P ( part ) = 1 ; } } } else { insn = emit_insn ( gen_movsi_push ( frame_pointer_rtx ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( frame_pointer_needed ) { insn = emit_insn ( gen_movsi ( frame_pointer_rtx , stack_pointer_rtx ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } } if ( current_frame_info . frame_size == 0 ) ; else if ( current_frame_info . save_fp && current_frame_info . frame_size < ( ( 1 << 10 ) - UNITS_PER_WORD ) ) ; else if ( current_frame_info . frame_size <= 512 ) { insn = emit_insn ( gen_add_to_stack ( GEN_INT ( - current_frame_info . frame_size ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } else { rtx tmp = gen_rtx_REG ( Pmode , PROLOGUE_TMP_REGNUM ) ; insn = emit_insn ( gen_movsi ( tmp , GEN_INT ( current_frame_info . frame_size ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; insn = emit_insn ( gen_subsi3 ( stack_pointer_rtx , stack_pointer_rtx , tmp ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } if ( current_function_profile ) emit_insn ( gen_blockage ( ) ) ; } </s>

Called after register allocation to add any instructions needed for the prologue . Using a prologue insn is favored compared to putting all of the instructions in output_function_prologue ( ) , since it allows the scheduler to intermix instructions with the saves of the caller saved registers . In some cases , it might be necessary to emit a barrier instruction as the last insn to prevent such scheduling .


<s> bool AArch64InstrInfo :: isThroughputPattern ( MachineCombinerPattern Pattern ) const { switch ( Pattern ) { default : break ; case MachineCombinerPattern :: FMULADDS_OP1 : case MachineCombinerPattern :: FMULADDS_OP2 : case MachineCombinerPattern :: FMULSUBS_OP1 : case MachineCombinerPattern :: FMULSUBS_OP2 : case MachineCombinerPattern :: FMULADDD_OP1 : case MachineCombinerPattern :: FMULADDD_OP2 : case MachineCombinerPattern :: FMULSUBD_OP1 : case MachineCombinerPattern :: FMULSUBD_OP2 : case MachineCombinerPattern :: FNMULSUBS_OP1 : case MachineCombinerPattern :: FNMULSUBD_OP1 : case MachineCombinerPattern :: FMLAv1i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv1i32_indexed_OP2 : case MachineCombinerPattern :: FMLAv1i64_indexed_OP1 : case MachineCombinerPattern :: FMLAv1i64_indexed_OP2 : case MachineCombinerPattern :: FMLAv2f32_OP2 : case MachineCombinerPattern :: FMLAv2f32_OP1 : case MachineCombinerPattern :: FMLAv2f64_OP1 : case MachineCombinerPattern :: FMLAv2f64_OP2 : case MachineCombinerPattern :: FMLAv2i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv2i32_indexed_OP2 : case MachineCombinerPattern :: FMLAv2i64_indexed_OP1 : case MachineCombinerPattern :: FMLAv2i64_indexed_OP2 : case MachineCombinerPattern :: FMLAv4f32_OP1 : case MachineCombinerPattern :: FMLAv4f32_OP2 : case MachineCombinerPattern :: FMLAv4i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv4i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv1i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv1i64_indexed_OP2 : case MachineCombinerPattern :: FMLSv2i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv2i64_indexed_OP2 : case MachineCombinerPattern :: FMLSv2f32_OP2 : case MachineCombinerPattern :: FMLSv2f64_OP2 : case MachineCombinerPattern :: FMLSv4i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv4f32_OP2 : return true ; } return false ; } </s>

Return true when a code sequence can improve throughput .


<s> bool X86TTIImpl :: isLegalNTStore ( Type * DataType , Align Alignment ) { unsigned DataSize = DL . getTypeStoreSize ( DataType ) ; if ( ST -> hasSSE4A ( ) && ( DataType -> isFloatTy ( ) || DataType -> isDoubleTy ( ) ) ) return true ; if ( Alignment < DataSize || DataSize < 4 || DataSize > 32 || ! isPowerOf2_32 ( DataSize ) ) return false ; if ( DataSize == 32 ) return ST -> hasAVX ( ) ; else if ( DataSize == 16 ) return ST -> hasSSE1 ( ) ; return true ; } </s>

Return true if the target supports nontemporal store .


<s>
bool
X86AsmPrinter
::
PrintAsmOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
{
if
(
ExtraCode
[
1
]
!=
0
)
return
true
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNo
)
;
switch
(
ExtraCode
[
0
]
)
{
default
:
return
AsmPrinter
::
PrintAsmOperand
(
MI
,
OpNo
,
AsmVariant
,
ExtraCode
,
O
)
;
case
'a'
:
switch
(
MO
.
getType
(
)
)
{
default
:
return
true
;
case
MachineOperand
::
MO_Immediate
:
O
<<
MO
.
getImm
(
)
;
return
false
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
case
MachineOperand
::
MO_JumpTableIndex
:
case
MachineOperand
::
MO_ExternalSymbol
:
llvm_unreachable
(
"unexpected operand type!"
)
;
case
MachineOperand
::
MO_GlobalAddress
:
printSymbolOperand
(
*
this
,
MO
,
O
)
;
if
(
Subtarget
->
isPICStyleRIPRel
(
)
)
O
<<
"(%rip)"
;
return
false
;
case
MachineOperand
::
MO_Register
:
O
<<
'('
;
printOperand
(
*
this
,
MI
,
OpNo
,
O
)
;
O
<<
')'
;
return
false
;
}
case
'c'
:
switch
(
MO
.
getType
(
)
)
{
default
:
printOperand
(
*
this
,
MI
,
OpNo
,
O
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
O
<<
MO
.
getImm
(
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
case
MachineOperand
::
MO_JumpTableIndex
:
case
MachineOperand
::
MO_ExternalSymbol
:
llvm_unreachable
(
"unexpected operand type!"
)
;
case
MachineOperand
::
MO_GlobalAddress
:
printSymbolOperand
(
*
this
,
MO
,
O
)
;
break
;
}
return
false
;
case
'A'
:
if
(
MO
.
isReg
(
)
)
{
O
<<
'*'
;
printOperand
(
*
this
,
MI
,
OpNo
,
O
)
;
return
false
;
}
return
true
;
case
'b'
:
case
'h'
:
case
'w'
:
case
'k'
:
case
'q'
:
if
(
MO
.
isReg
(
)
)
return
printAsmMRegister
(
*
this
,
MO
,
ExtraCode
[
0
]
,
O
)
;
printOperand
(
*
this
,
MI
,
OpNo
,
O
)
;
return
false
;
case
'P'
:
printPCRelImm
(
*
this
,
MI
,
OpNo
,
O
)
;
return
false
;
case
'n'
:
if
(
MO
.
isImm
(
)
)
{
O
<<
MO
.
getImm
(
)
;
return
false
;
}
O
<<
'-'
;
}
}
printOperand
(
*
this
,
MI
,
OpNo
,
O
,
nullptr
,
AsmVariant
)
;
return
false
;
}
</s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> bool HexagonTargetLowering :: shouldExpandAtomicStoreInIR ( StoreInst * SI ) const { return SI -> getValueOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) > 64 ; } </s>

Returns how the given ( atomic ) store should be expanded by the IR-level AtomicExpand pass into .


<s> void RISCVFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; Align StackAlign = getStackAlign ( ) ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI . setStackSize ( FrameSize ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; if ( RVFI -> getRVVStackSize ( ) && ( ! hasFP ( MF ) || TRI -> hasStackRealignment ( MF ) ) ) { int ScalarLocalVarSize = FrameSize - RVFI -> getCalleeSavedStackSize ( ) - RVFI -> getVarArgsSaveSize ( ) ; if ( auto RVVPadding = offsetToAlignment ( ScalarLocalVarSize , RVFI -> getRVVStackAlign ( ) ) ) RVFI -> setRVVPadding ( RVVPadding ) ; } } </s>

Determine the frame layout but do not update the machine function .


<s> unsigned getNumFixupKinds ( ) const { return Videocore :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> bool Mips16InstrInfo :: isCopyInstr ( const MachineInstr & MI , MachineOperand & Src , MachineOperand & Dest ) const { if ( MI . isMoveReg ( ) ) { Dest = MI . getOperand ( 0 ) ; Src = MI . getOperand ( 1 ) ; return true ; } return false ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


<s> Value * simplify ( Instruction * I , const TargetLibraryInfo * TLI ) { return SimplifyInstruction ( I , { * TD , TLI , DT } ) ; } </s>

Go through all the nodes in the graph and collapse any two nodes ' a ' and ' b ' if all of the following are true :


<s> static bool rs6000_legitimate_constant_p ( machine_mode mode , rtx x ) { if ( TARGET_ELF && tls_referenced_p ( x ) ) return false ; return ( ( GET_CODE ( x ) != CONST_DOUBLE && GET_CODE ( x ) != CONST_VECTOR ) || GET_MODE ( x ) == VOIDmode || ( TARGET_POWERPC64 && mode == DImode ) || easy_fp_constant ( x , mode ) || easy_vector_constant ( x , mode ) ) ; } </s>

Implement TARGET_LEGITIMATE_CONSTANT_P . On the RS/6000 , all integer constants are acceptable , most wo n't be valid for particular insns , though . Only easy FP constants are acceptable .


<s> static unsigned int aarch64_get_next_set_bit ( sbitmap bmp , unsigned int start ) { unsigned int nbits = SBITMAP_SIZE ( bmp ) ; if ( start == nbits ) return start ; gcc_assert ( start < nbits ) ; for ( unsigned int i = start ; i < nbits ; i ++ ) if ( bitmap_bit_p ( bmp , i ) ) return i ; return nbits ; } </s>

Return the next set bit in BMP from START onwards . Return the total number of bits in BMP if no set bit is found at or after START .


<s> rtx rs6000_function_value ( tree valtype , tree func ATTRIBUTE_UNUSED ) { enum machine_mode mode ; unsigned int regno ; if ( rs6000_darwin64_abi && TYPE_MODE ( valtype ) == BLKmode && TREE_CODE ( valtype ) == RECORD_TYPE && int_size_in_bytes ( valtype ) > 0 ) { CUMULATIVE_ARGS valcum ; rtx valret ; valcum . words = 0 ; valcum . fregno = FP_ARG_MIN_REG ; valcum . vregno = ALTIVEC_ARG_MIN_REG ; valret = rs6000_darwin64_record_arg ( & valcum , valtype , 1 , true ) ; if ( valret ) return valret ; } if ( TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE ( valtype ) == DImode ) { return gen_rtx_PARALLEL ( DImode , gen_rtvec ( 2 , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , GP_ARG_RETURN ) , const0_rtx ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , GP_ARG_RETURN + 1 ) , GEN_INT ( 4 ) ) ) ) ; } if ( TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE ( valtype ) == DCmode ) { return gen_rtx_PARALLEL ( DCmode , gen_rtvec ( 4 , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , GP_ARG_RETURN ) , const0_rtx ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , GP_ARG_RETURN + 1 ) , GEN_INT ( 4 ) ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , GP_ARG_RETURN + 2 ) , GEN_INT ( 8 ) ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , GP_ARG_RETURN + 3 ) , GEN_INT ( 12 ) ) ) ) ; } if ( ( INTEGRAL_TYPE_P ( valtype ) && TYPE_PRECISION ( valtype ) < BITS_PER_WORD ) || POINTER_TYPE_P ( valtype ) ) mode = TARGET_32BIT ? SImode : DImode ; else mode = TYPE_MODE ( valtype ) ; if ( SCALAR_FLOAT_TYPE_P ( valtype ) && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = FP_ARG_RETURN ; else if ( TREE_CODE ( valtype ) == COMPLEX_TYPE && targetm . calls . split_complex_arg ) return rs6000_complex_function_value ( mode ) ; else if ( TREE_CODE ( valtype ) == VECTOR_TYPE && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE ( mode ) ) regno = ALTIVEC_ARG_RETURN ; else if ( TARGET_E500_DOUBLE && TARGET_HARD_FLOAT && ( mode == DFmode || mode == DCmode ) ) return spe_build_register_parallel ( mode , GP_ARG_RETURN ) ; else regno = GP_ARG_RETURN ; return gen_rtx_REG ( mode , regno ) ; } </s>

Define how to find the value returned by a function . VALTYPE is the data type of the value ( as a tree ) . If the precise function being called is known , FUNC is its FUNCTION_DECL ; otherwise , FUNC is 0 . On the SPE , both FPs and vectors are returned in r3 . On RS/6000 an integer value is in r3 and a floating-point value is in fp1 , unless -msoft-float .


<s> static rtvec rs6000_const_vec ( machine_mode mode ) { int i , subparts ; rtvec v ; switch ( mode ) { case V1TImode : subparts = 1 ; break ; case V2DFmode : case V2DImode : subparts = 2 ; break ; case V4SFmode : case V4SImode : subparts = 4 ; break ; case V8HImode : subparts = 8 ; break ; case V16QImode : subparts = 16 ; break ; default : gcc_unreachable ( ) ; } v = rtvec_alloc ( subparts ) ; for ( i = 0 ; i < subparts / 2 ; ++ i ) RTVEC_ELT ( v , i ) = gen_rtx_CONST_INT ( DImode , i + subparts / 2 ) ; for ( i = subparts / 2 ; i < subparts ; ++ i ) RTVEC_ELT ( v , i ) = gen_rtx_CONST_INT ( DImode , i - subparts / 2 ) ; return v ; } </s>

Generate a vector of constants to permute MODE for a little-endian storage operation by swapping the two halves of a vector .


<s> rtx_insn * s390_load_got ( void ) { rtx_insn * insns ; rtx got_rtx = gen_rtx_REG ( Pmode , 12 ) ; if ( ! got_symbol ) { got_symbol = gen_rtx_SYMBOL_REF ( Pmode , "_GLOBAL_OFFSET_TABLE_" ) ; SYMBOL_REF_FLAGS ( got_symbol ) = SYMBOL_FLAG_LOCAL ; } start_sequence ( ) ; if ( TARGET_CPU_ZARCH ) { emit_move_insn ( got_rtx , got_symbol ) ; } else { rtx offset ; offset = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , got_symbol ) , UNSPEC_LTREL_OFFSET ) ; offset = gen_rtx_CONST ( Pmode , offset ) ; offset = force_const_mem ( Pmode , offset ) ; emit_move_insn ( got_rtx , offset ) ; offset = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , XEXP ( offset , 0 ) ) , UNSPEC_LTREL_BASE ) ; offset = gen_rtx_PLUS ( Pmode , got_rtx , offset ) ; emit_move_insn ( got_rtx , offset ) ; } insns = get_insns ( ) ; end_sequence ( ) ; return insns ; } </s>

Return insn sequence to load the GOT register .


<s> inline static void drop_front ( StringRef & str , size_t n = 1 ) { str = str . drop_front ( n ) ; } </s>

Return a StringRef equal to 'this ' but with the first N elements dropped .


"expression value must be representable in 32 bits"

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> void MipsTargetELFStreamer :: finish ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; MCContext & Context = MCA . getContext ( ) ; MCStreamer & OS = getStreamer ( ) ; const MCObjectFileInfo & OFI = * Context . getObjectFileInfo ( ) ; Triple T ( STI . getTargetTriple ( ) ) ; uint64_t Features = STI . getFeatureBits ( ) ; MCSectionData & TextSectionData = MCA . getOrCreateSectionData ( * OFI . getTextSection ( ) ) ; MCSectionData & DataSectionData = MCA . getOrCreateSectionData ( * OFI . getDataSection ( ) ) ; MCSectionData & BSSSectionData = MCA . getOrCreateSectionData ( * OFI . getBSSSection ( ) ) ; TextSectionData . setAlignment ( std :: max ( 16u , TextSectionData . getAlignment ( ) ) ) ; DataSectionData . setAlignment ( std :: max ( 16u , DataSectionData . getAlignment ( ) ) ) ; BSSSectionData . setAlignment ( std :: max ( 16u , BSSSectionData . getAlignment ( ) ) ) ; if ( T . isArch64Bit ( ) && ( Features & Mips :: FeatureN64 ) ) { const MCSectionELF * Sec = Context . getELFSection ( ".MIPS.options" , ELF :: SHT_MIPS_OPTIONS , ELF :: SHF_ALLOC | ELF :: SHF_MIPS_NOSTRIP , SectionKind :: getMetadata ( ) , 1 , "" ) ; MCA . getOrCreateSectionData ( * Sec ) . setAlignment ( 8 ) ; OS . SwitchSection ( Sec ) ; OS . EmitIntValue ( 1 , 1 ) ; OS . EmitIntValue ( 40 , 1 ) ; OS . EmitIntValue ( 0 , 2 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 8 ) ; } else { const MCSectionELF * Sec = Context . getELFSection ( ".reginfo" , ELF :: SHT_MIPS_REGINFO , ELF :: SHF_ALLOC , SectionKind :: getMetadata ( ) , 24 , "" ) ; MCA . getOrCreateSectionData ( * Sec ) . setAlignment ( Features & Mips :: FeatureN32 ? 8 : 4 ) ; OS . SwitchSection ( Sec ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; } emitMipsAbiFlags ( ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> SDValue AlphaTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_Alpha ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) . getValue ( 1 ) ; SDValue RetValue = Chain . getValue ( 0 ) ; InFlag = Chain . getValue ( 2 ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) RetValue = DAG . getNode ( ISD :: AssertSext , dl , VA . getLocVT ( ) , RetValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) RetValue = DAG . getNode ( ISD :: AssertZext , dl , VA . getLocVT ( ) , RetValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) RetValue = DAG . getNode ( ISD :: TRUNCATE , dl , VA . getValVT ( ) , RetValue ) ; InVals . push_back ( RetValue ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> void ix86_emit_swsqrtsf ( rtx res , rtx a , machine_mode mode , bool recip ) { rtx x0 , e0 , e1 , e2 , e3 , mthree , mhalf ; REAL_VALUE_TYPE r ; int unspec ; x0 = gen_reg_rtx ( mode ) ; e0 = gen_reg_rtx ( mode ) ; e1 = gen_reg_rtx ( mode ) ; e2 = gen_reg_rtx ( mode ) ; e3 = gen_reg_rtx ( mode ) ; real_from_integer ( & r , VOIDmode , - 3 , SIGNED ) ; mthree = const_double_from_real_value ( r , SFmode ) ; real_arithmetic ( & r , NEGATE_EXPR , & dconsthalf , NULL ) ; mhalf = const_double_from_real_value ( r , SFmode ) ; unspec = UNSPEC_RSQRT ; if ( VECTOR_MODE_P ( mode ) ) { mthree = ix86_build_const_vector ( mode , true , mthree ) ; mhalf = ix86_build_const_vector ( mode , true , mhalf ) ; if ( GET_MODE_SIZE ( mode ) == 64 ) unspec = UNSPEC_RSQRT14 ; } a = force_reg ( mode , a ) ; emit_insn ( gen_rtx_SET ( x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , a ) , unspec ) ) ) ; if ( ! recip ) { rtx zero = force_reg ( mode , CONST0_RTX ( mode ) ) ; rtx mask ; if ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == 64 ) { mask = gen_reg_rtx ( HImode ) ; emit_insn ( gen_avx512f_cmpv16sf3 ( mask , zero , a , GEN_INT ( 0x4 ) ) ) ; emit_insn ( gen_avx512f_blendmv16sf ( x0 , zero , x0 , mask ) ) ; } else { mask = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( mask , gen_rtx_NE ( mode , zero , a ) ) ) ; emit_insn ( gen_rtx_SET ( x0 , gen_rtx_AND ( mode , x0 , mask ) ) ) ; } } emit_insn ( gen_rtx_SET ( e0 , gen_rtx_MULT ( mode , x0 , a ) ) ) ; emit_insn ( gen_rtx_SET ( e1 , gen_rtx_MULT ( mode , e0 , x0 ) ) ) ; mthree = force_reg ( mode , mthree ) ; emit_insn ( gen_rtx_SET ( e2 , gen_rtx_PLUS ( mode , e1 , mthree ) ) ) ; mhalf = force_reg ( mode , mhalf ) ; if ( recip ) emit_insn ( gen_rtx_SET ( e3 , gen_rtx_MULT ( mode , x0 , mhalf ) ) ) ; else emit_insn ( gen_rtx_SET ( e3 , gen_rtx_MULT ( mode , e0 , mhalf ) ) ) ; emit_insn ( gen_rtx_SET ( res , gen_rtx_MULT ( mode , e2 , e3 ) ) ) ; } </s>

Output code to perform a Newton-Rhapson approximation of a single precision floating point [ reciprocal ] square root .


<s> virtual MVT getShiftAmountTy ( EVT LHSTy ) const { return MVT :: i32 ; } </s>

Returns the type for the shift amount of a shift opcode .


<s>
bool
HCE
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
DEBUG
(
MF
.
print
(
dbgs
(
)
<<
"Before "
<<
getPassName
(
)
<<
'\n'
,
nullptr
)
)
;
HII
=
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getInstrInfo
(
)
;
HRI
=
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getRegisterInfo
(
)
;
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
AssignmentMap
IMap
;
collect
(
MF
)
;
std
::
sort
(
Extenders
.
begin
(
)
,
Extenders
.
end
(
)
,
[
]
(
const
ExtDesc
&
A
,
const
ExtDesc
&
B
)
{
return
ExtValue
(
A
)
<
ExtValue
(
B
)
;
}
)
;
bool
Changed
=
false
;
DEBUG
(
dbgs
(
)
<<
"Collected "
<<
Extenders
.
size
(
)
<<
" extenders\n"
)
;
for
(
unsigned
I
=
0
,
E
=
Extenders
.
size
(
)
;
I
!=
E
;
)
{
unsigned
B
=
I
;
const
ExtRoot
&
T
=
Extenders
[
B
]
.
getOp
(
)
;
while
(
I
!=
E
&&
ExtRoot
(
Extenders
[
I
]
.
getOp
(
)
)
==
T
)
++
I
;
IMap
.
clear
(
)
;
assignInits
(
T
,
B
,
I
,
IMap
)
;
Changed
|=
replaceExtenders
(
IMap
)
;
}
DEBUG
(
{
if
(
Changed
)
MF
.
print
(
dbgs
(
)
<<
"After "
<<
getPassName
(
)
<<
'\n'
,
nullptr
)
;
else
dbgs
(
)
<<
"No changes\n"
;
}
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

Hexagon
"Before "
Hexagon
Hexagon
"Collected "
" extenders\n"
0
"After "
"No changes\n"


<s> bool MipsCallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < Register > VRegs , FunctionLoweringInfo & FLI ) const { MachineInstrBuilder Ret = MIRBuilder . buildInstrNoInsert ( Mips :: RetRA ) ; if ( Val != nullptr && ! isSupportedReturnType ( Val -> getType ( ) ) ) return false ; if ( ! VRegs . empty ( ) ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const MipsTargetLowering & TLI = * getTLI < MipsTargetLowering > ( ) ; SmallVector < ArgInfo , 8 > RetInfos ; SmallVector < unsigned , 8 > OrigArgIndices ; ArgInfo ArgRetInfo ( VRegs , Val -> getType ( ) ) ; setArgFlags ( ArgRetInfo , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( DL , ArgRetInfo , 0 , RetInfos , OrigArgIndices ) ; SmallVector < ISD :: OutputArg , 8 > Outs ; subTargetRegTypeForCallingConv ( F , RetInfos , OrigArgIndices , Outs ) ; SmallVector < CCValAssign , 16 > ArgLocs ; MipsCCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , TLI . CCAssignFnForReturn ( ) ) ; setLocInfo ( ArgLocs , Outs ) ; MipsOutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , Ret ) ; if ( ! RetHandler . handle ( ArgLocs , RetInfos ) ) { return false ; } } MIRBuilder . insertInstr ( Ret ) ; return true ; } </s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> int X86RegisterInfo :: getDwarfRegNum ( unsigned RegNo , bool isEH ) const { const X86Subtarget * Subtarget = & TM . getSubtarget < X86Subtarget > ( ) ; unsigned Flavour = DWARFFlavour :: X86_64 ; if ( ! Subtarget -> is64Bit ( ) ) { if ( Subtarget -> isTargetDarwin ( ) ) { if ( isEH ) Flavour = DWARFFlavour :: X86_32_DarwinEH ; else Flavour = DWARFFlavour :: X86_32_Generic ; } else if ( Subtarget -> isTargetCygMing ( ) ) { Flavour = DWARFFlavour :: X86_32_Generic ; } else { Flavour = DWARFFlavour :: X86_32_Generic ; } } return X86GenRegisterInfo :: getDwarfRegNumFull ( RegNo , Flavour ) ; } </s>

Map a target register to an equivalent dwarf register number .


<s> int arm_legitimate_address_p ( enum machine_mode mode , rtx x , RTX_CODE outer , int strict_p ) { bool use_ldrd ; enum rtx_code code = GET_CODE ( x ) ; if ( arm_address_register_rtx_p ( x , strict_p ) ) return 1 ; use_ldrd = ( TARGET_LDRD && ( mode == DImode || ( mode == DFmode && ( TARGET_SOFT_FLOAT || TARGET_VFP ) ) ) ) ; if ( code == POST_INC || code == PRE_DEC || ( ( code == PRE_INC || code == POST_DEC ) && ( use_ldrd || GET_MODE_SIZE ( mode ) <= 4 ) ) ) return arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) ; else if ( ( code == POST_MODIFY || code == PRE_MODIFY ) && arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) && GET_CODE ( XEXP ( x , 1 ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( x , 1 ) , 0 ) , XEXP ( x , 0 ) ) ) { rtx addend = XEXP ( XEXP ( x , 1 ) , 1 ) ; if ( use_ldrd && GET_CODE ( x ) == POST_MODIFY && GET_CODE ( addend ) == REG ) return 0 ; return ( ( use_ldrd || GET_MODE_SIZE ( mode ) <= 4 ) && arm_legitimate_index_p ( mode , addend , outer , strict_p ) ) ; } else if ( reload_completed && ( code == LABEL_REF || ( code == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == LABEL_REF && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 1 ) ) == CONST_INT ) ) ) return 1 ; else if ( mode == TImode ) return 0 ; else if ( code == PLUS ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; return ( ( arm_address_register_rtx_p ( xop0 , strict_p ) && arm_legitimate_index_p ( mode , xop1 , outer , strict_p ) ) || ( arm_address_register_rtx_p ( xop1 , strict_p ) && arm_legitimate_index_p ( mode , xop0 , outer , strict_p ) ) ) ; } else if ( GET_CODE ( x ) == MINUS ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; return ( arm_address_register_rtx_p ( xop0 , strict_p ) && arm_legitimate_index_p ( mode , xop1 , outer , strict_p ) ) ; } else if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && code == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) && ! ( flag_pic && symbol_mentioned_p ( get_pool_constant ( x ) ) && ! pcrel_constant_p ( get_pool_constant ( x ) ) ) ) return 1 ; return 0 ; } </s>

Return nonzero if X is a valid ARM state address operand .


<s> static inline tree def_builtin_pure ( HOST_WIDE_INT mask , const char * name , enum ix86_builtin_func_type tcode , enum ix86_builtins code ) { tree decl = def_builtin ( mask , name , tcode , code ) ; if ( decl ) DECL_PURE_P ( decl ) = 1 ; else ix86_builtins_isa [ ( int ) code ] . pure_p = true ; return decl ; } </s>

Like def_builtin , but also marks the function decl `` pure '' .


<s> void s390_expand_vec_compare ( rtx target , enum rtx_code cond , rtx cmp_op1 , rtx cmp_op2 ) { machine_mode mode = GET_MODE ( target ) ; bool neg_p = false , swap_p = false ; rtx tmp ; if ( GET_MODE_CLASS ( GET_MODE ( cmp_op1 ) ) == MODE_VECTOR_FLOAT ) { cmp_op2 = force_reg ( GET_MODE ( cmp_op1 ) , cmp_op2 ) ; switch ( cond ) { case NE : cond = EQ ; neg_p = true ; break ; case UNGT : emit_insn ( gen_vec_cmpungt ( target , cmp_op1 , cmp_op2 ) ) ; return ; case UNGE : emit_insn ( gen_vec_cmpunge ( target , cmp_op1 , cmp_op2 ) ) ; return ; case LE : cond = GE ; swap_p = true ; break ; case UNLE : emit_insn ( gen_vec_cmpunge ( target , cmp_op2 , cmp_op1 ) ) ; return ; case LT : cond = GT ; swap_p = true ; break ; case UNLT : emit_insn ( gen_vec_cmpungt ( target , cmp_op2 , cmp_op1 ) ) ; return ; case UNEQ : emit_insn ( gen_vec_cmpuneq ( target , cmp_op1 , cmp_op2 ) ) ; return ; case LTGT : emit_insn ( gen_vec_cmpltgt ( target , cmp_op1 , cmp_op2 ) ) ; return ; case ORDERED : emit_insn ( gen_vec_cmpordered ( target , cmp_op1 , cmp_op2 ) ) ; return ; case UNORDERED : emit_insn ( gen_vec_cmpunordered ( target , cmp_op1 , cmp_op2 ) ) ; return ; default : break ; } } else { if ( cond == LT && cmp_op2 == CONST0_RTX ( mode ) ) { int shift = GET_MODE_BITSIZE ( GET_MODE_INNER ( mode ) ) - 1 ; rtx res = expand_simple_binop ( mode , ASHIFTRT , cmp_op1 , GEN_INT ( shift ) , target , 0 , OPTAB_DIRECT ) ; if ( res != target ) emit_move_insn ( target , res ) ; return ; } cmp_op2 = force_reg ( GET_MODE ( cmp_op1 ) , cmp_op2 ) ; switch ( cond ) { case NE : cond = EQ ; neg_p = true ; break ; case GE : cond = GT ; neg_p = true ; swap_p = true ; break ; case GEU : cond = GTU ; neg_p = true ; swap_p = true ; break ; case LE : cond = GT ; neg_p = true ; break ; case LEU : cond = GTU ; neg_p = true ; break ; case LT : cond = GT ; swap_p = true ; break ; case LTU : cond = GTU ; swap_p = true ; break ; default : break ; } } if ( swap_p ) { tmp = cmp_op1 ; cmp_op1 = cmp_op2 ; cmp_op2 = tmp ; } emit_insn ( gen_rtx_SET ( target , gen_rtx_fmt_ee ( cond , mode , cmp_op1 , cmp_op2 ) ) ) ; if ( neg_p ) emit_insn ( gen_rtx_SET ( target , gen_rtx_NOT ( mode , target ) ) ) ; } </s>

Generate a vector comparison COND of CMP_OP1 and CMP_OP2 and store the result in TARGET .


<s> int same_cmp_following_p ( rtx_insn * i1 ) { rtx_insn * i2 , * i3 ; i2 = next_nonnote_insn ( i1 ) ; if ( i2 == NULL ) return 0 ; i3 = next_nonnote_insn ( i2 ) ; if ( i3 == NULL ) return 0 ; return ( INSN_P ( i3 ) && rtx_equal_p ( PATTERN ( i1 ) , PATTERN ( i3 ) ) && any_condjump_p ( i2 ) && onlyjump_p ( i2 ) ) ; } </s>

Return nonzero if we have the same comparison insn as I1 two insns after I1 . I1 is assumed to be a comparison insn .


<s> void SICPassConfig :: addPreEmitPass ( ) { SICTargetMachine & TM = getSICTargetMachine ( ) ; addPass ( createSICDelJmpPass ( TM ) ) ; return ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> unsigned ARMTargetLowering :: getABIAlignmentForCallingConv ( Type * ArgTy , DataLayout DL ) const { if ( ! ArgTy -> isVectorTy ( ) ) return DL . getABITypeAlignment ( ArgTy ) ; return std :: min ( DL . getABITypeAlignment ( ArgTy ) , DL . getStackAlignment ( ) ) ; } </s>

Return the correct alignment for the current calling convention .


<s> static void rx_elf_asm_cdtor ( rtx symbol , int priority , bool is_ctor ) { section * s ; if ( priority != DEFAULT_INIT_PRIORITY ) { char buf [ 18 ] ; sprintf ( buf , "%s.%.5u" , is_ctor ? ".init_array" : ".fini_array" , priority ) ; s = get_section ( buf , SECTION_WRITE , NULL_TREE ) ; } else if ( is_ctor ) s = ctors_section ; else s = dtors_section ; switch_to_section ( s ) ; assemble_align ( POINTER_SIZE ) ; assemble_integer ( symbol , POINTER_SIZE / BITS_PER_UNIT , POINTER_SIZE , 1 ) ; } </s>


<s> bool AAPAsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> static void ix86_emit_leave ( rtx_insn * insn ) { struct machine_function * m = cfun -> machine ; if ( ! insn ) insn = emit_insn ( gen_leave ( word_mode ) ) ; ix86_add_queued_cfa_restore_notes ( insn ) ; gcc_assert ( m -> fs . fp_valid ) ; m -> fs . sp_valid = true ; m -> fs . sp_realigned = false ; m -> fs . sp_offset = m -> fs . fp_offset - UNITS_PER_WORD ; m -> fs . fp_valid = false ; if ( m -> fs . cfa_reg == hard_frame_pointer_rtx ) { m -> fs . cfa_reg = stack_pointer_rtx ; m -> fs . cfa_offset = m -> fs . sp_offset ; add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , stack_pointer_rtx , m -> fs . sp_offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } ix86_add_cfa_restore_note ( insn , hard_frame_pointer_rtx , m -> fs . fp_offset ) ; } </s>

Emit code and notes for the LEAVE instruction .


<s> int pdp11_initial_elimination_offset ( int from , int to ) { int spoff ; if ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) return 4 ; else if ( from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) return 0 ; else { gcc_assert ( to == STACK_POINTER_REGNUM ) ; spoff = pdp11_sp_frame_offset ( ) ; if ( from == FRAME_POINTER_REGNUM ) return spoff ; gcc_assert ( from == ARG_POINTER_REGNUM ) ; if ( frame_pointer_needed ) spoff += 2 ; return spoff + 2 ; } } </s>

Return the offset between two registers , one to be eliminated , and the other its replacement , at the start of a routine .


<s> static bool ia64_print_operand_punct_valid_p ( unsigned char code ) { return ( code == '+' || code == ',' ) ; } </s>

Worker function for TARGET_PRINT_OPERAND_PUNCT_VALID_P .


<s> bool enableMachineScheduler ( ) const override { return true ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( TM ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Cpu0 Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static rtx compute_frame_addr ( int offset_from_fp , int * next_scratch_regno ) { rtx base_reg_rtx , tmp_reg_rtx , offset_rtx ; int offset_from_base ; if ( frame_pointer_needed ) { base_reg_rtx = hard_frame_pointer_rtx ; offset_from_base = offset_from_fp ; } else { int offset_from_sp = compute_total_frame_size ( ) + offset_from_fp ; base_reg_rtx = stack_pointer_rtx ; offset_from_base = offset_from_sp ; } if ( offset_from_base == 0 ) return base_reg_rtx ; tmp_reg_rtx = gen_rtx_REG ( Pmode , ( * next_scratch_regno ) -- ) ; offset_rtx = gen_int_si ( offset_from_base ) ; if ( ! tilepro_expand_addsi ( tmp_reg_rtx , base_reg_rtx , offset_rtx ) ) { emit_insn ( gen_rtx_SET ( VOIDmode , tmp_reg_rtx , gen_rtx_PLUS ( Pmode , base_reg_rtx , offset_rtx ) ) ) ; } return tmp_reg_rtx ; } </s>

Returns an rtx for a stack slot at 'FP + offset_from_fp ' . If there is a frame pointer , it computes the value relative to that . Otherwise it uses the stack pointer .


<s> bool RISCVPassConfig :: addInstSelector ( ) { addPass ( createRISCVISelDag ( getRISCVTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> DecodeStatus HexagonDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & os , raw_ostream & cs ) const { DecodeStatus Result = DecodeStatus :: Success ; bool Complete = false ; Size = 0 ; * CurrentBundle = & MI ; MI = HexagonMCInstrInfo :: createBundle ( ) ; while ( Result == Success && ! Complete ) { if ( Bytes . size ( ) < HEXAGON_INSTR_SIZE ) return MCDisassembler :: Fail ; MCInst * Inst = new ( getContext ( ) ) MCInst ; Result = getSingleInstruction ( * Inst , MI , Bytes , Address , os , cs , Complete ) ; MI . addOperand ( MCOperand :: createInst ( Inst ) ) ; Size += HEXAGON_INSTR_SIZE ; Bytes = Bytes . slice ( HEXAGON_INSTR_SIZE ) ; } if ( Result == MCDisassembler :: Fail ) return Result ; HexagonMCChecker Checker ( * MCII , STI , MI , MI , * getContext ( ) . getRegisterInfo ( ) ) ; if ( ! Checker . check ( ) ) return MCDisassembler :: Fail ; return MCDisassembler :: Success ; } </s>

Returns the disassembly of a single instruction .


<s> const FISCInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> static bool riscv_valid_offset_p ( rtx x , enum machine_mode mode ) { if ( ! const_arith_operand ( x , Pmode ) ) return false ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && ! SMALL_OPERAND ( INTVAL ( x ) + GET_MODE_SIZE ( mode ) - UNITS_PER_WORD ) ) return false ; return true ; } </s>

Return true if , for every base register BASE_REG , ( plus BASE_REG X ) can address a value of mode MODE .


<s> void Clear ( ) { Stack . clear ( ) ; LocalTypes . clear ( ) ; ReturnTypes . clear ( ) ; TypeErrorThisFunction = false ; Unreachable = false ; } </s>

Clear value data entries and edge counters .


<s> const VERegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool Mips16FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return isInt < 15 > ( MFI . getMaxCallFrameSize ( ) ) && ! MFI . hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> MSP430Subtarget :: MSP430Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : MSP430GenSubtargetInfo ( TT , CPU , FS ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , TSInfo ( * TM . getDataLayout ( ) ) { } </s>

This constructor initializes the data members to match that of the specified triple .


<s> static bool aarch64_could_trap_p ( aarch64_simd_builtin_datum * d ) { unsigned int flags = aarch64_call_properties ( d ) ; if ( flags & FLAG_RAISE_FP_EXCEPTIONS ) return true ; if ( flags & ( FLAG_READ_MEMORY | FLAG_WRITE_MEMORY ) ) return true ; return false ; } </s>

Return true if calls to the function could raise a signal .


<s> void mips_output_load_label ( rtx target ) { mips_push_asm_switch ( & mips_noat ) ; if ( TARGET_EXPLICIT_RELOCS ) { mips_process_load_label ( target ) ; mips_multi_write ( ) ; } else { if ( Pmode == DImode ) output_asm_insn ( "dla\t%@,%0" , & target ) ; else output_asm_insn ( "la\t%@,%0" , & target ) ; } } </s>

Return an asm sequence to start a noat block and load the address of a label into $ 1 .


<s> class LLVM_LIBRARY_VISIBILITY KudeyarMCInstLower { typedef MachineOperand :: MachineOperandType MachineOperandType ; KudeyarAsmPrinter & Printer ; public : KudeyarMCInstLower ( KudeyarAsmPrinter & asmprinter ) ; void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ; private : MCSymbol * GetGlobalAddressSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetExternalSymbolSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetJumpTableSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetConstantPoolIndexSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetBlockAddressSymbol ( const MachineOperand & MO ) const ; MCOperand LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym ) const ; MCOperand LowerOperand ( const MachineOperand & MO , unsigned offset = 0 ) const ; } </s>

Return the MCSymbol for the specified ExternalSymbol .

Kudeyar Kudeyar Kudeyar Kudeyar Kudeyar 0


<s>
int64_t
ARMBaseRegisterInfo
::
getFrameIndexInstrOffset
(
const
MachineInstr
*
MI
,
int
Idx
)
const
{
const
MCInstrDesc
&
Desc
=
MI
->
getDesc
(
)
;
unsigned
AddrMode
=
(
Desc
.
TSFlags
&
ARMII
::
AddrModeMask
)
;
int64_t
InstrOffs
=
0
;
;
int
Scale
=
1
;
unsigned
ImmIdx
=
0
;
switch
(
AddrMode
)
{
case
ARMII
::
AddrModeT2_i8
:
case
ARMII
::
AddrModeT2_i12
:
case
ARMII
::
AddrMode_i12
:
InstrOffs
=
MI
->
getOperand
(
Idx
+
1
)
.
getImm
(
)
;
Scale
=
1
;
break
;
case
ARMII
::
AddrMode5
:
{
const
MachineOperand
&
OffOp
=
MI
->
getOperand
(
Idx
+
1
)
;
InstrOffs
=
ARM_AM
::
getAM5Offset
(
OffOp
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM5Op
(
OffOp
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
Scale
=
4
;
break
;
}
case
ARMII
::
AddrMode2
:
{
ImmIdx
=
Idx
+
2
;
InstrOffs
=
ARM_AM
::
getAM2Offset
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM2Op
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
break
;
}
case
ARMII
::
AddrMode3
:
{
ImmIdx
=
Idx
+
2
;
InstrOffs
=
ARM_AM
::
getAM3Offset
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM3Op
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
break
;
}
case
ARMII
::
AddrModeT1_s
:
{
ImmIdx
=
Idx
+
1
;
InstrOffs
=
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
;
Scale
=
4
;
break
;
}
default
:
llvm_unreachable
(
"Unsupported addressing mode!"
)
;
}
return
InstrOffs
*
Scale
;
}
</s>

Get the offset from the referenced frame index in the instruction , if there is one .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> static int translate_unix ( char * name , int type ATTRIBUTE_UNUSED ) { strcpy ( filename_buff , name ) ; return 0 ; } </s>

Action routine called by decc $ to_vms . NAME is a file name or directory name . TYPE is unused .


<s>
void
SystemZInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MBBI
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
SystemZ
::
GR128BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
copyPhysReg
(
MBB
,
MBBI
,
DL
,
RI
.
getSubReg
(
DestReg
,
SystemZ
::
subreg_h64
)
,
RI
.
getSubReg
(
SrcReg
,
SystemZ
::
subreg_h64
)
,
KillSrc
)
;
MachineInstrBuilder
(
*
MBB
.
getParent
(
)
,
std
::
prev
(
MBBI
)
)
.
addReg
(
SrcReg
,
RegState
::
Implicit
)
;
copyPhysReg
(
MBB
,
MBBI
,
DL
,
RI
.
getSubReg
(
DestReg
,
SystemZ
::
subreg_l64
)
,
RI
.
getSubReg
(
SrcReg
,
SystemZ
::
subreg_l64
)
,
KillSrc
)
;
MachineInstrBuilder
(
*
MBB
.
getParent
(
)
,
std
::
prev
(
MBBI
)
)
.
addReg
(
SrcReg
,
(
getKillRegState
(
KillSrc
)
|
RegState
::
Implicit
)
)
;
return
;
}
if
(
SystemZ
::
GRX32BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
emitGRX32Move
(
MBB
,
MBBI
,
DL
,
DestReg
,
SrcReg
,
SystemZ
::
LR
,
32
,
KillSrc
,
false
)
;
return
;
}
unsigned
Opcode
;
if
(
SystemZ
::
GR64BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LGR
;
else
if
(
SystemZ
::
FP32BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
STI
.
hasVector
(
)
SystemZ
::
LDR32
:
SystemZ
::
LER
;
else
if
(
SystemZ
::
FP64BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LDR
;
else
if
(
SystemZ
::
FP128BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LXR
;
else
if
(
SystemZ
::
VR32BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
VLR32
;
else
if
(
SystemZ
::
VR64BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
VLR64
;
else
if
(
SystemZ
::
VR128BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
VLR
;
else
if
(
SystemZ
::
AR32BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
CPYA
;
else
if
(
SystemZ
::
AR32BitRegClass
.
contains
(
DestReg
)
&&
SystemZ
::
GR32BitRegClass
.
contains
(
SrcReg
)
)
Opcode
=
SystemZ
::
SAR
;
else
if
(
SystemZ
::
GR32BitRegClass
.
contains
(
DestReg
)
&&
SystemZ
::
AR32BitRegClass
.
contains
(
SrcReg
)
)
Opcode
=
SystemZ
::
EAR
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
Opcode
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> bool XCoreFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return true ; MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF -> getTarget ( ) . getInstrInfo ( ) ; XCoreFunctionInfo * XFI = MF -> getInfo < XCoreFunctionInfo > ( ) ; bool emitFrameMoves = XCoreRegisterInfo :: needsFrameMoves ( * MF ) ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator it = CSI . begin ( ) ; it != CSI . end ( ) ; ++ it ) { MBB . addLiveIn ( it -> getReg ( ) ) ; unsigned Reg = it -> getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , it -> getFrameIdx ( ) , RC , TRI ) ; if ( emitFrameMoves ) { MCSymbol * SaveLabel = MF -> getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MI , DL , TII . get ( XCore :: PROLOG_LABEL ) ) . addSym ( SaveLabel ) ; XFI -> getSpillLabels ( ) . push_back ( std :: make_pair ( SaveLabel , * it ) ) ; } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .

XCore XCore XCore XCore XCore XCore::PROLOG_LABEL


<s> bool R600InstrInfo :: isProfitableToUnpredicate ( MachineBasicBlock & TMBB , MachineBasicBlock & FMBB ) const { return false ; } </s>

Return true if it 's profitable to unpredicate one side of a 'diamond ' , i.e .


<s> bool X86InstrInfo :: canMakeTailCallConditional ( SmallVectorImpl < MachineOperand > & BranchCond , const MachineInstr & TailCall ) const { if ( TailCall . getOpcode ( ) != X86 :: TCRETURNdi && TailCall . getOpcode ( ) != X86 :: TCRETURNdi64 ) { return false ; } const MachineFunction * MF = TailCall . getParent ( ) -> getParent ( ) ; if ( Subtarget . isTargetWin64 ( ) && MF -> hasWinCFI ( ) ) { return false ; } assert ( BranchCond . size ( ) == 1 ) ; if ( BranchCond [ 0 ] . getImm ( ) > X86 :: LAST_VALID_COND ) { return false ; } const X86MachineFunctionInfo * X86FI = MF -> getInfo < X86MachineFunctionInfo > ( ) ; if ( X86FI -> getTCReturnAddrDelta ( ) != 0 || TailCall . getOperand ( 1 ) . getImm ( ) != 0 ) { return false ; } return true ; } </s>

Returns true if the tail call can be made conditional on BranchCond .


<s> ScheduleHazardRecognizer * ARMBaseInstrInfo :: CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II , const ScheduleDAG * DAG ) const { if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2 ( ) ) return ( ScheduleHazardRecognizer * ) new ARMHazardRecognizer ( II , * this , getRegisterInfo ( ) , Subtarget , DAG ) ; return TargetInstrInfoImpl :: CreateTargetPostRAHazardRecognizer ( II , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for by non-scheduling passes .


<s>
MachineBasicBlock
*
RISCVTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
MBB
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
case
RISCV
::
SELECT_CC
:
case
RISCV
::
SELECT_CC64
:
case
RISCV
::
FSELECT_CC_F
:
case
RISCV
::
FSELECT_CC_D
:
return
emitSelectCC
(
MI
,
MBB
)
;
case
RISCV
::
CALL
:
case
RISCV
::
CALLREG
:
case
RISCV
::
CALL64
:
case
RISCV
::
CALLREG64
:
return
emitCALL
(
MI
,
MBB
)
;
default
:
llvm_unreachable
(
"Unexpected instr type to insert"
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static int epilogue_renumber ( rtx * where , int test ) { const char * fmt ; int i ; enum rtx_code code ; if ( * where == 0 ) return 0 ; code = GET_CODE ( * where ) ; switch ( code ) { case REG : if ( REGNO ( * where ) >= 8 && REGNO ( * where ) < 24 ) return 1 ; if ( ! test && REGNO ( * where ) >= 24 && REGNO ( * where ) < 32 ) { if ( ORIGINAL_REGNO ( * where ) ) { rtx n = gen_raw_REG ( GET_MODE ( * where ) , OUTGOING_REGNO ( REGNO ( * where ) ) ) ; ORIGINAL_REGNO ( n ) = ORIGINAL_REGNO ( * where ) ; * where = n ; } else * where = gen_rtx_REG ( GET_MODE ( * where ) , OUTGOING_REGNO ( REGNO ( * where ) ) ) ; } return 0 ; case SCRATCH : case PC : case CONST_INT : case CONST_WIDE_INT : case CONST_DOUBLE : return 0 ; case PLUS : if ( GET_CODE ( XEXP ( * where , 0 ) ) == REG && REGNO ( XEXP ( * where , 0 ) ) == HARD_FRAME_POINTER_REGNUM && ( GET_CODE ( XEXP ( * where , 1 ) ) != CONST_INT || INTVAL ( XEXP ( * where , 1 ) ) < SPARC_STACK_BIAS ) ) return 1 ; break ; case MEM : if ( SPARC_STACK_BIAS && GET_CODE ( XEXP ( * where , 0 ) ) == REG && REGNO ( XEXP ( * where , 0 ) ) == HARD_FRAME_POINTER_REGNUM ) return 1 ; break ; default : break ; } fmt = GET_RTX_FORMAT ( code ) ; for ( i = GET_RTX_LENGTH ( code ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( * where , i ) - 1 ; j >= 0 ; j -- ) if ( epilogue_renumber ( & ( XVECEXP ( * where , i , j ) ) , test ) ) return 1 ; } else if ( fmt [ i ] == 'e' && epilogue_renumber ( & ( XEXP ( * where , i ) ) , test ) ) return 1 ; } return 0 ; } </s>

Return 1 , if any of the registers of the instruction are % l [ 0-7 ] or % o [ 0-7 ] . Such instructions can not be used in the delay slot of return insn on v9 . If TEST is 0 , also rename all % i [ 0-7 ] registers to their % o [ 0-7 ] counterparts .


"WDC_TODO - Unimplemented method called, opcode="

Main hook for targets to transform nodes into machine nodes .


<s> const MipsTargetLowering * MipsTargetLowering :: create ( MipsTargetMachine & TM ) { if ( TM . getSubtargetImpl ( ) -> inMips16Mode ( ) ) return llvm :: createMips16TargetLowering ( TM ) ; return llvm :: createMipsSETargetLowering ( TM ) ; } </s>


<s> static rtx rs6000_pre_atomic_barrier ( rtx mem , enum memmodel model ) { rtx addr = XEXP ( mem , 0 ) ; int strict_p = ( reload_in_progress || reload_completed ) ; if ( ! legitimate_indirect_address_p ( addr , strict_p ) && ! legitimate_indexed_address_p ( addr , strict_p ) ) { addr = force_reg ( Pmode , addr ) ; mem = replace_equiv_address_nv ( mem , addr ) ; } switch ( model ) { case MEMMODEL_RELAXED : case MEMMODEL_CONSUME : case MEMMODEL_ACQUIRE : break ; case MEMMODEL_RELEASE : case MEMMODEL_ACQ_REL : emit_insn ( gen_lwsync ( ) ) ; break ; case MEMMODEL_SEQ_CST : emit_insn ( gen_hwsync ( ) ) ; break ; default : gcc_unreachable ( ) ; } return mem ; } </s>

Expand barriers before and after a load_locked/store_cond sequence .


<s>
void
MetadataStreamerV3
::
dump
(
StringRef
HSAMetadataString
)
const
{
errs
(
)
<<
"AMDGPU HSA Metadata:\n"
<<
HSAMetadataString
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .


<s> rtx function_expander :: use_unpred_insn ( insn_code icode ) { gcc_assert ( pred == PRED_x || pred == PRED_none ) ; unsigned int nops = insn_data [ icode ] . n_operands - 1 ; unsigned int bias = ( pred == PRED_x ? 1 : 0 ) ; unsigned int i = 0 ; add_output_operand ( icode ) ; for ( ; i < nops ; ++ i ) add_input_operand ( icode , args [ i + bias ] ) ; return generate_insn ( icode ) ; } </s>

Implement the call using instruction ICODE , which does not use a governing predicate . We must therefore drop the GP from an _x call .


<s> MachineRegisterInfo * getMRI ( ) { return & MRI ; } </s>


<s>
bool
SHUXIInstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
!
isUnpredicatedTerminator
(
*
I
)
)
break
;
if
(
!
I
->
isBranch
(
)
)
return
true
;
if
(
I
->
getOpcode
(
)
==
SHUXI
::
JMP
)
{
if
(
!
AllowModify
)
{
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
continue
;
}
while
(
std
::
next
(
I
)
!=
MBB
.
end
(
)
)
std
::
next
(
I
)
->
eraseFromParent
(
)
;
Cond
.
clear
(
)
;
FBB
=
nullptr
;
if
(
MBB
.
isLayoutSuccessor
(
I
->
getOperand
(
0
)
.
getMBB
(
)
)
)
{
TBB
=
nullptr
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
continue
;
}
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
continue
;
}
assert
(
I
->
getOpcode
(
)
==
SHUXI
::
JCC
&&
"Invalid conditional branch"
)
;
SHUXICC
::
CondCodes
BranchCode
=
static_cast
<
SHUXICC
::
CondCodes
>
(
I
->
getOperand
(
1
)
.
getImm
(
)
)
;
if
(
BranchCode
==
SHUXICC
::
COND_INVALID
)
return
true
;
if
(
Cond
.
empty
(
)
)
{
FBB
=
TBB
;
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
BranchCode
)
)
;
continue
;
}
assert
(
Cond
.
size
(
)
==
1
)
;
assert
(
TBB
)
;
if
(
TBB
!=
I
->
getOperand
(
0
)
.
getMBB
(
)
)
return
true
;
SHUXICC
::
CondCodes
OldBranchCode
=
(
SHUXICC
::
CondCodes
)
Cond
[
0
]
.
getImm
(
)
;
if
(
OldBranchCode
==
BranchCode
)
continue
;
return
true
;
}
return
false
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s>
static
const
char
*
arm_invalid_return_type
(
const_tree
t
)
{
if
(
SCALAR_FLOAT_TYPE_P
(
t
)
&&
TYPE_PRECISION
(
t
)
==
16
)
return
N_
(
"functions cannot return __fp16 type"
)
;
return
;
}
</s>

arm
16
"functions cannot return __fp16 type"


"AMDGPU DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> static void c6x_output_fn_unwind ( FILE * f ) { if ( ! ( flag_unwind_tables || flag_exceptions ) ) return ; if ( ! ( flag_unwind_tables || crtl -> uses_eh_lsda ) && ( TREE_NOTHROW ( current_function_decl ) || crtl -> all_throwers_are_sibcalls ) ) fputs ( "\t.cantunwind\n" , f ) ; fputs ( "\t.endp\n" , f ) ; } </s>

Output unwind directives at the end of a function .


<s> bool X86InstrInfo :: getMemOperandsWithOffsetWidth ( const MachineInstr & MemOp , SmallVectorImpl < const MachineOperand * > & BaseOps , int64_t & Offset , bool & OffsetIsScalable , unsigned & Width , const TargetRegisterInfo * TRI ) const { const MCInstrDesc & Desc = MemOp . getDesc ( ) ; int MemRefBegin = X86II :: getMemoryOperandNo ( Desc . TSFlags ) ; if ( MemRefBegin < 0 ) return false ; MemRefBegin += X86II :: getOperandBias ( Desc ) ; const MachineOperand * BaseOp = & MemOp . getOperand ( MemRefBegin + X86 :: AddrBaseReg ) ; if ( ! BaseOp -> isReg ( ) ) return false ; if ( MemOp . getOperand ( MemRefBegin + X86 :: AddrScaleAmt ) . getImm ( ) != 1 ) return false ; if ( MemOp . getOperand ( MemRefBegin + X86 :: AddrIndexReg ) . getReg ( ) != X86 :: NoRegister ) return false ; const MachineOperand & DispMO = MemOp . getOperand ( MemRefBegin + X86 :: AddrDisp ) ; if ( ! DispMO . isImm ( ) ) return false ; Offset = DispMO . getImm ( ) ; if ( ! BaseOp -> isReg ( ) ) return false ; OffsetIsScalable = false ; Width = ! MemOp . memoperands_empty ( ) ? MemOp . memoperands ( ) . front ( ) -> getSize ( ) : 0 ; BaseOps . push_back ( BaseOp ) ; return true ; } </s>

Get zero or more base operands and the byte offset of an instruction that reads/writes memory .


"internal error: builtin function %s already processed"

Add a SPARC builtin function with NAME , ICODE , CODE and TYPE . Return the function decl or NULL_TREE if the builtin was not added .


<s> static int thumb2_legitimate_address_p ( machine_mode mode , rtx x , int strict_p ) { bool use_ldrd ; enum rtx_code code = GET_CODE ( x ) ; if ( arm_address_register_rtx_p ( x , strict_p ) ) return 1 ; use_ldrd = ( TARGET_LDRD && ( mode == DImode || mode == DFmode ) ) ; if ( code == POST_INC || code == PRE_DEC || ( ( code == PRE_INC || code == POST_DEC ) && ( use_ldrd || GET_MODE_SIZE ( mode ) <= 4 ) ) ) return arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) ; else if ( ( code == POST_MODIFY || code == PRE_MODIFY ) && arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) && GET_CODE ( XEXP ( x , 1 ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( x , 1 ) , 0 ) , XEXP ( x , 0 ) ) ) { rtx addend = XEXP ( XEXP ( x , 1 ) , 1 ) ; HOST_WIDE_INT offset ; if ( ! CONST_INT_P ( addend ) ) return 0 ; offset = INTVAL ( addend ) ; if ( GET_MODE_SIZE ( mode ) <= 4 ) return ( offset > - 256 && offset < 256 ) ; return ( use_ldrd && offset > - 1024 && offset < 1024 && ( offset & 3 ) == 0 ) ; } else if ( reload_completed && ( code == LABEL_REF || ( code == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ) ) ) return 1 ; else if ( mode == TImode || ( TARGET_NEON && VALID_NEON_STRUCT_MODE ( mode ) ) ) return 0 ; else if ( code == PLUS ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; return ( ( arm_address_register_rtx_p ( xop0 , strict_p ) && ( thumb2_legitimate_index_p ( mode , xop1 , strict_p ) || ( ! strict_p && will_be_in_index_register ( xop1 ) ) ) ) || ( arm_address_register_rtx_p ( xop1 , strict_p ) && thumb2_legitimate_index_p ( mode , xop0 , strict_p ) ) ) ; } else if ( arm_disable_literal_pool && code == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) ) return 0 ; else if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && code == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) && ! ( flag_pic && symbol_mentioned_p ( get_pool_constant ( x ) ) && ! pcrel_constant_p ( get_pool_constant ( x ) ) ) ) return 1 ; return 0 ; } </s>

Return nonzero if X is a valid Thumb-2 address operand .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < DominatorTree > ( ) ; AU . addPreserved < DominatorTree > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
MachineBasicBlock
::
iterator
ARCFrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
DEBUG
(
dbgs
(
)
<<
"EmitCallFramePseudo: "
<<
MF
.
getName
(
)
<<
"\n"
)
;
const
ARCInstrInfo
*
TII
=
MF
.
getSubtarget
<
ARCSubtarget
>
(
)
.
getInstrInfo
(
)
;
MachineInstr
&
Old
=
*
I
;
DebugLoc
dl
=
Old
.
getDebugLoc
(
)
;
unsigned
Amt
=
Old
.
getOperand
(
0
)
.
getImm
(
)
;
auto
*
AFI
=
MF
.
getInfo
<
ARCFunctionInfo
>
(
)
;
if
(
!
hasFP
(
MF
)
)
{
if
(
Amt
>
AFI
->
MaxCallStackReq
&&
Old
.
getOpcode
(
)
==
ARC
::
ADJCALLSTACKDOWN
)
AFI
->
MaxCallStackReq
=
Amt
;
}
else
{
if
(
Amt
!=
0
)
{
assert
(
(
Old
.
getOpcode
(
)
==
ARC
::
ADJCALLSTACKDOWN
||
Old
.
getOpcode
(
)
==
ARC
::
ADJCALLSTACKUP
)
&&
"Unknown Frame Pseudo."
)
;
bool
IsAdd
=
(
Old
.
getOpcode
(
)
==
ARC
::
ADJCALLSTACKUP
)
;
emitRegUpdate
(
MBB
,
I
,
dl
,
ARC
::
SP
,
Amt
,
IsAdd
,
TII
)
;
}
}
return
MBB
.
erase
(
I
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

ARC
ARC
"EmitCallFramePseudo: "
"\n"
ARC
ARC
0
ARC
ARC::ADJCALLSTACKDOWN
0
ARC::ADJCALLSTACKDOWN
ARC::ADJCALLSTACKUP
"Unknown Frame Pseudo."
ARC::ADJCALLSTACKUP
ARC::SP


"could not find corresponding %pcrel_hi"

Hook to check if a relocation is needed for some target specific reason .


<s> static void emit_compare ( rtx_code code , rtx a , rtx b ) { emit_insn ( gen_rtx_SET ( gen_rtx_REG ( BImode , SR_F_REGNUM ) , gen_rtx_fmt_ee ( code , BImode , a , b ) ) ) ; } </s>

A subroutine of the atomic operation splitters . Emit a raw comparison for A CODE B .


<s> XCoreSubtarget :: XCoreSubtarget ( const TargetMachine & TM , const Module & M , const std :: string & FS ) : IsXS1A ( false ) , IsXS1B ( false ) { std :: string CPU = "xs1a-generic" ; ParseSubtargetFeatures ( FS , CPU ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> void fma_forest :: fma_node_created ( fma_node * node ) { bool created = ! this -> m_globals -> put_node ( node ) ; gcc_assert ( created ) ; this -> m_nb_nodes ++ ; } </s>

Act on the creation of NODE by updating statistics in FOREST and adding an entry for it in the func_fma_steering hashmap .


<s> void RISCVInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { if ( NoAliases || ! printAliasInstr ( MI , O ) ) printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s>
static
void
copy_fp_args
(
rtx
insn
)
{
rtx
link
;
rtx
xoperands
[
2
]
;
for
(
link
=
CALL_INSN_FUNCTION_USAGE
(
insn
)
;
link
;
link
=
XEXP
(
link
,
1
)
)
{
int
arg_mode
,
regno
;
rtx
use
=
XEXP
(
link
,
0
)
;
if
(
!
(
GET_CODE
(
use
)
==
USE
&&
GET_CODE
(
XEXP
(
use
,
0
)
)
==
REG
&&
FUNCTION_ARG_REGNO_P
(
REGNO
(
XEXP
(
use
,
0
)
)
)
)
)
continue
;
arg_mode
=
GET_MODE
(
XEXP
(
use
,
0
)
)
;
regno
=
REGNO
(
XEXP
(
use
,
0
)
)
;
if
(
regno
>=
32
&&
regno
<=
39
)
{
if
(
arg_mode
==
SFmode
)
{
xoperands
[
0
]
=
XEXP
(
use
,
0
)
;
xoperands
[
1
]
=
gen_rtx_REG
(
SImode
,
26
(
regno
32
)
/
2
)
;
output_asm_insn
(
"{fstws|fstw} %0,-16(%%sr0,%%r30)"
,
xoperands
)
;
output_asm_insn
(
"ldw -16(%%sr0,%%r30),%1"
,
xoperands
)
;
}
else
{
xoperands
[
0
]
=
XEXP
(
use
,
0
)
;
xoperands
[
1
]
=
gen_rtx_REG
(
DImode
,
25
(
regno
34
)
/
2
)
;
output_asm_insn
(
"{fstds|fstd} %0,-16(%%sr0,%%r30)"
,
xoperands
)
;
output_asm_insn
(
"ldw -12(%%sr0,%%r30),%R1"
,
xoperands
)
;
output_asm_insn
(
"ldw -16(%%sr0,%%r30),%1"
,
xoperands
)
;
}
}
}
}
</s>

Copy any FP arguments in INSN into integer registers .


<s> rtx sfunc_symbol ( const char * name ) { rtx sym = gen_rtx_SYMBOL_REF ( Pmode , name ) ; SYMBOL_REF_FLAGS ( sym ) = SYMBOL_FLAG_FUNCTION | SYMBOL_FLAG_LOCAL ; if ( TARGET_SHORT_CALLS ) ; else if ( can_create_pseudo_p ( ) ) sym = copy_to_mode_reg ( Pmode , sym ) ; else gcc_assert ( ! reload_in_progress || reload_completed ) ; return sym ; } </s>

Generate a SYMBOL_REF for the special function NAME . When the address ca n't be placed directly into a call instruction , and if possible , copy it to a register so that cse / code hoisting is possible .


<s> void RV16KInstPrinter :: printRegName ( raw_ostream & O , unsigned RegNo ) const { O << getRegisterName ( RegNo ) ; } </s>


<s> Value * X86TargetLowering :: getIRStackGuard ( IRBuilderBase & IRB ) const { if ( hasStackGuardSlotTLS ( Subtarget . getTargetTriple ( ) ) ) { if ( Subtarget . isTargetFuchsia ( ) ) { return SegmentOffset ( IRB , 0x10 , getAddressSpace ( ) ) ; } else { unsigned AddressSpace = getAddressSpace ( ) ; Module * M = IRB . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; int Offset = M -> getStackProtectorGuardOffset ( ) ; if ( Offset == INT_MAX ) Offset = ( Subtarget . is64Bit ( ) ) ? 0x28 : 0x14 ; StringRef GuardReg = M -> getStackProtectorGuardReg ( ) ; if ( GuardReg == "fs" ) AddressSpace = X86AS :: FS ; else if ( GuardReg == "gs" ) AddressSpace = X86AS :: GS ; return SegmentOffset ( IRB , Offset , AddressSpace ) ; } } return TargetLowering :: getIRStackGuard ( IRB ) ; } </s>

If the target has a standard location for the stack protector cookie , returns the address of that location .


<s> MCELFStreamer & AMDGPUTargetELFStreamer :: getStreamer ( ) { return static_cast < MCELFStreamer & > ( Streamer ) ; } </s>

Return the output streamer for the assembler .


The AVR backend 's rtx_cost function . X is rtx expression whose cost is to be calculated . Return true if the complete cost has been computed , and false if subexpressions should be scanned . In either case , * TOTAL contains the cost result .


<s> void sparc_flat_expand_epilogue ( bool for_eh ) { HOST_WIDE_INT size = sparc_frame_size ; if ( sparc_n_global_fp_regs > 0 ) emit_save_or_restore_global_fp_regs ( sparc_frame_base_reg , sparc_frame_base_offset - sparc_apparent_frame_size , SORR_RESTORE ) ; if ( frame_pointer_needed && ! for_eh ) emit_move_insn ( gen_rtx_REG ( Pmode , 1 ) , hard_frame_pointer_rtx ) ; if ( return_addr_reg_needed_p ( sparc_leaf_function_p ) ) emit_move_insn ( gen_rtx_REG ( Pmode , INCOMING_RETURN_ADDR_REGNUM ) , gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ) ; if ( sparc_save_local_in_regs_p ) emit_save_or_restore_local_in_regs ( sparc_frame_base_reg , sparc_frame_base_offset , SORR_RESTORE ) ; if ( size == 0 || for_eh ) ; else if ( frame_pointer_needed ) { emit_insn ( gen_blockage ( ) ) ; emit_move_insn ( stack_pointer_rtx , gen_rtx_REG ( Pmode , 1 ) ) ; } else { emit_insn ( gen_blockage ( ) ) ; if ( size <= 4096 ) emit_insn ( gen_stack_pointer_inc ( GEN_INT ( size ) ) ) ; else if ( size <= 8192 ) { emit_insn ( gen_stack_pointer_inc ( GEN_INT ( 4096 ) ) ) ; emit_insn ( gen_stack_pointer_inc ( GEN_INT ( size - 4096 ) ) ) ; } else { rtx reg = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( reg , GEN_INT ( size ) ) ; emit_insn ( gen_stack_pointer_inc ( reg ) ) ; } } } </s>

Expand the function epilogue , either normal or part of a sibcall . We emit all the instructions except the return or the call .


<s> static rtx mips_dwarf_register_span ( rtx reg ) { rtx high , low ; machine_mode mode ; mode = GET_MODE ( reg ) ; if ( FP_REG_P ( REGNO ( reg ) ) && TARGET_FLOATXX && GET_MODE_SIZE ( mode ) > UNITS_PER_FPREG ) { return gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 1 , reg ) ) ; } else if ( FP_REG_P ( REGNO ( reg ) ) && TARGET_BIG_ENDIAN && MAX_FPRS_PER_FMT > 1 && GET_MODE_SIZE ( mode ) > UNITS_PER_FPREG ) { gcc_assert ( GET_MODE_SIZE ( mode ) == UNITS_PER_HWFPVALUE ) ; high = mips_subword ( reg , true ) ; low = mips_subword ( reg , false ) ; return gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , high , low ) ) ; } return NULL_RTX ; } </s>


<s> void MipsOutgoingValueHandler :: assignValueToAddress ( Register ValVReg , Register Addr , LLT MemTy , MachinePointerInfo & MPO , CCValAssign & VA ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; uint64_t LocMemOffset = VA . getLocMemOffset ( ) ; auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , MemTy , commonAlignment ( STI . getStackAlignment ( ) , LocMemOffset ) ) ; Register ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildStore ( ExtReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> SDValue AlphaTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , unsigned CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_Alpha ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) . getValue ( 1 ) ; SDValue RetValue = Chain . getValue ( 0 ) ; InFlag = Chain . getValue ( 2 ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) RetValue = DAG . getNode ( ISD :: AssertSext , dl , VA . getLocVT ( ) , RetValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) RetValue = DAG . getNode ( ISD :: AssertZext , dl , VA . getLocVT ( ) , RetValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) RetValue = DAG . getNode ( ISD :: TRUNCATE , dl , VA . getValVT ( ) , RetValue ) ; InVals . push_back ( RetValue ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


"What the hell register is this?? Unable to store to stack slot!"

Store the specified register of the given register class to the specified stack frame index .


<s> void HSAILAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { HSAILMCInstLower MCInstLowering ( OutContext , * this ) ; MCInst TmpInst ; MCInstLowering . lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> Register getExceptionPointerRegister ( const Constant * PersonalityFn ) const override { return ABI . IsN64 ( ) ? Mips :: A0_64 : Mips :: A0 ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s> void MetadataStreamerV3 :: end ( ) { std :: string HSAMetadataString ; raw_string_ostream StrOS ( HSAMetadataString ) ; HSAMetadataDoc -> toYAML ( StrOS ) ; if ( DumpHSAMetadata ) dump ( StrOS . str ( ) ) ; if ( VerifyHSAMetadata ) verify ( StrOS . str ( ) ) ; } </s>

Get a const_iterator to the end of the symbol table .


<s>
const
char
*
PTXTargetLowering
::
getTargetNodeName
(
unsigned
Opcode
)
const
{
switch
(
Opcode
)
{
default
:
llvm_unreachable
(
"Unknown opcode"
)
;
case
PTXISD
::
EXIT
:
return
"PTXISD::EXIT"
;
case
PTXISD
::
RET
:
return
"PTXISD::RET"
;
}
}
</s>

getTargetNodeName - This method returns the name of a target specific

PTX
PTX
"Unknown opcode"
PTXISD::EXIT
"PTXISD::EXIT"
PTXISD::RET
"PTXISD::RET"


<s> void NVPTXPassConfig :: addPostRegAlloc ( ) { addPass ( createNVPTXPrologEpilogPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createNVPTXPeephole ( ) ) ; } } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> StringRef getPassName ( ) const override { return "M88kPreLegalizerCombiner" ; } </s>

getPassName - Return a nice clean name for a pass .


"XNCM DAG->DAG Pattern Instruction Selection"


<s> bool Error ( SMLoc L , const Twine & Msg ) { return Parser . Error ( L , Msg ) ; } </s>

Return an error at the location L , with the message Msg .


<s> unsigned int getNumFixupKinds ( ) const override { return AArch64 :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> void AMDGPUPromoteKernelArguments :: enqueueUsers ( Value * Ptr ) { SmallVector < User * > PtrUsers ( Ptr -> users ( ) ) ; while ( ! PtrUsers . empty ( ) ) { Instruction * U = dyn_cast < Instruction > ( PtrUsers . pop_back_val ( ) ) ; if ( ! U ) continue ; switch ( U -> getOpcode ( ) ) { default : break ; case Instruction :: Load : { LoadInst * LD = cast < LoadInst > ( U ) ; PointerType * PT = dyn_cast < PointerType > ( LD -> getType ( ) ) ; if ( ! PT || ( PT -> getAddressSpace ( ) != AMDGPUAS :: FLAT_ADDRESS && PT -> getAddressSpace ( ) != AMDGPUAS :: GLOBAL_ADDRESS && PT -> getAddressSpace ( ) != AMDGPUAS :: CONSTANT_ADDRESS ) || LD -> getPointerOperand ( ) -> stripInBoundsOffsets ( ) != Ptr ) break ; const MemoryAccess * MA = MSSA -> getWalker ( ) -> getClobberingMemoryAccess ( LD ) ; if ( MSSA -> isLiveOnEntryDef ( MA ) ) Ptrs . push_back ( LD ) ; break ; } case Instruction :: GetElementPtr : case Instruction :: AddrSpaceCast : case Instruction :: BitCast : if ( U -> getOperand ( 0 ) -> stripInBoundsOffsets ( ) == Ptr ) PtrUsers . append ( U -> user_begin ( ) , U -> user_end ( ) ) ; break ; } } } </s>

Enqueue the users of this instruction in the visit worklist .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { const Function * F = MF . getFunction ( ) ; if ( ! F ) return false ; if ( skipFunction ( * F ) ) return false ; HexagonConstEvaluator HCE ( MF ) ; return MachineConstPropagator ( HCE ) . run ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


"Basic block should contain at least a RET but is empty"


<s> bool Z80MachineLateOptimization :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; return Changed ; } </s>


<s> static bool isAssociativeAndCommutative ( unsigned Opcode ) { switch ( Opcode ) { case PPC :: FADD : case PPC :: FADDS : case PPC :: FMUL : case PPC :: FMULS : case PPC :: VADDFP : case PPC :: XSADDDP : case PPC :: XVADDDP : case PPC :: XVADDSP : case PPC :: XSADDSP : case PPC :: XSMULDP : case PPC :: XVMULDP : case PPC :: XVMULSP : case PPC :: XSMULSP : case PPC :: QVFADD : case PPC :: QVFADDS : case PPC :: QVFADDSs : case PPC :: QVFMUL : case PPC :: QVFMULS : case PPC :: QVFMULSs : return true ; default : return false ; } } </s>

Return true when \P Inst is both associative and commutative .

PowerPC PPC::FADD PPC::FADDS PPC::FMUL PPC::FMULS PPC::VADDFP PPC::XSADDDP PPC::XVADDDP PPC::XVADDSP PPC::XSADDSP PPC::XSMULDP PPC::XVMULDP PPC::XVMULSP PPC::XSMULSP PPC::QVFADD PPC::QVFADDS PPC::QVFADDSs PPC::QVFMUL PPC::QVFMULS PPC::QVFMULSs


<s> static inline bool avr_reg_ok_for_addr_p ( rtx reg , addr_space_t as , RTX_CODE outer_code , bool strict ) { return ( REG_P ( reg ) && ( avr_regno_mode_code_ok_for_base_p ( REGNO ( reg ) , QImode , as , outer_code , UNKNOWN ) || ( ! strict && REGNO ( reg ) >= FIRST_PSEUDO_REGISTER ) ) ) ; } </s>

Helper function for ` avr_legitimate_address_p ' .


"PatmosInstrInfo::PredicateInstruction() can't handle bundles"

"Cannot predicate an instruction already predicated."

Convert the instruction into a predicated instruction .


Relax the instruction in the given fragment to the next wider instruction .


<s> unsigned PPCInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case PPC :: LD : case PPC :: LWZ : case PPC :: LFS : case PPC :: LFD : case PPC :: RESTORE_CR : case PPC :: RESTORE_CRBIT : case PPC :: LVX : case PPC :: LXVD2X : case PPC :: LXV : case PPC :: QVLFDX : case PPC :: QVLFSXs : case PPC :: QVLFDXb : case PPC :: RESTORE_VRSAVE : case PPC :: SPILLTOVSR_LD : if ( MI . getOperand ( 1 ) . isImm ( ) && ! MI . getOperand ( 1 ) . getImm ( ) && MI . getOperand ( 2 ) . isFI ( ) ) { FrameIndex = MI . getOperand ( 2 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> const TargetRegisterClass * getMatchingSuperRegClass ( const TargetRegisterClass * A , const TargetRegisterClass * B , unsigned Idx ) const override { return A ; } </s>

getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register in it has a sub-register of the specified sub-register index which is in the specified register class B .


<s> bool ARMAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AFI = MF . getInfo < ARMFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; Subtarget = & MF . getSubtarget < ARMSubtarget > ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) { NaClAlignAllJumpTargetsAndConstantPools ( MF ) ; } SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = MF . getFunction ( ) -> hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer . BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer . EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer . EmitCOFFSymbolType ( Type ) ; OutStreamer . EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; if ( ! ThumbIndirectPads . empty ( ) ) { OutStreamer . EmitAssemblerFlag ( MCAF_Code16 ) ; EmitAlignment ( 1 ) ; for ( unsigned i = 0 , e = ThumbIndirectPads . size ( ) ; i < e ; i ++ ) { OutStreamer . EmitLabel ( ThumbIndirectPads [ i ] . second ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( ARM :: tBX ) . addReg ( ThumbIndirectPads [ i ] . first ) . addImm ( ARMCC :: AL ) . addReg ( 0 ) ) ; } ThumbIndirectPads . clear ( ) ; } return false ; } </s>

ARM ARM ARM ARM 1 0 ARM::tBX ARMCC::AL 0


<s> unsigned RISCVAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { RISCVOperand & Op = static_cast < RISCVOperand & > ( AsmOp ) ; if ( ! Op . isReg ( ) ) return Match_InvalidOperand ; Register Reg = Op . getReg ( ) ; bool IsRegFPR64 = RISCVMCRegisterClasses [ RISCV :: FPR64RegClassID ] . contains ( Reg ) ; bool IsRegFPR64C = RISCVMCRegisterClasses [ RISCV :: FPR64CRegClassID ] . contains ( Reg ) ; if ( ( IsRegFPR64 && Kind == MCK_FPR16 ) || ( IsRegFPR64C && Kind == MCK_FPR32C ) ) { Op . Reg . RegNum = convertFPR64ToFPR32 ( Reg ) ; return Match_Success ; } return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .

RISCV RISCV RISCV RISCV RISCV RISCV::FPR64RegClassID RISCV RISCV::FPR64CRegClassID


"Wasn't expecting to be able to lower this!"

LowerOperation - Provide custom lowering hooks for some operations .


<s> static tree nvptx_reduction_update ( location_t loc , gimple_stmt_iterator * gsi , tree ptr , tree var , tree_code op , int level ) { tree type = TREE_TYPE ( var ) ; tree size = TYPE_SIZE ( type ) ; if ( size == TYPE_SIZE ( unsigned_type_node ) || size == TYPE_SIZE ( long_long_unsigned_type_node ) ) return nvptx_lockless_update ( loc , gsi , ptr , var , op ) ; else return nvptx_lockfull_update ( loc , gsi , ptr , var , op , level ) ; } </s>

Emit a sequence to update a reduction accumlator at * PTR with the value held in VAR using operator OP . Return the updated value . TODO : optimize for atomic ops and indepedent complex ops .


<s>
void
arc_final_prescan_insn
(
rtx_insn
*
insn
,
rtx
*
opvec
ATTRIBUTE_UNUSED
,
int
noperands
ATTRIBUTE_UNUSED
)
{
if
(
TARGET_DUMPISIZE
)
fprintf
(
asm_out_file
,
"\n; at %04x\n"
,
INSN_ADDRESSES
(
INSN_UID
(
insn
)
)
)
;
if
(
!
cfun
->
machine
->
prescan_initialized
)
{
memset
(
&
arc_ccfsm_current
,
0
,
sizeof
arc_ccfsm_current
)
;
cfun
->
machine
->
prescan_initialized
=
1
;
}
arc_ccfsm_advance
(
insn
,
&
arc_ccfsm_current
)
;
}
</s>

The state of the fsm controlling condition codes are : 0 : normal , do nothing special 1 : do n't output this insn 2 : do n't output this insn 3 : make insns conditional 4 : make insns conditional State transitions ( state- > state by whom , under what condition ) : 0 - > 1 final_prescan_insn , if insn is conditional branch 0 - > 2 final_prescan_insn , if the ` target ' is an unconditional branch 1 - > 3 branch patterns , after having not output the conditional branch 2 - > 4 branch patterns , after having not output the conditional branch 3 - > 0 ( * targetm.asm_out.internal_label ) , if the ` target ' label is reached ( the target label has CODE_LABEL_NUMBER equal to arc_ccfsm_target_label ) . 4 - > 0 final_prescan_insn , if ` target ' unconditional branch is reached If the jump clobbers the conditions then we use states 2 and 4 . A similar thing can be done with conditional return insns . We also handle separating branches from sets of the condition code . This is done here because knowledge of the ccfsm state is required , we may not be outputting the branch .


<s> static tree alpha_builtin_decl ( unsigned code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= ALPHA_BUILTIN_max ) return error_mark_node ; return alpha_builtins [ code ] ; } </s>


<s> unsigned getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { LLT p0 = LLT :: pointer ( 0 , 64 ) ; LLT s64 = LLT :: scalar ( 64 ) ; unsigned SPReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildCopy ( SPReg , AArch64 :: SP ) ; unsigned OffsetReg = MRI . createGenericVirtualRegister ( s64 ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildGEP ( AddrReg , SPReg , OffsetReg ) ; MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ; StackSize = std :: max ( StackSize , Size + Offset ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


"-max-stackframe=%d is not usable, not between 0 and %d"

"unknown CRIS version specification in -march= or -mcpu= : %s"

"unknown CRIS cpu version specification in -mtune= : %s"

"-fPIC and -fpic are not supported in this configuration"

"that particular -g option is invalid with -maout and -melinux"

The OVERRIDE_OPTIONS worker . As is the norm , this also parses -mfoo=bar type parameters .


<s> SDNode * MipsDAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI . getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static int mips_immediate_operand_p ( int code , HOST_WIDE_INT x ) { switch ( code ) { case ASHIFT : case ASHIFTRT : case LSHIFTRT : return true ; case ROTATE : case ROTATERT : return ISA_HAS_ROR ; case AND : case IOR : case XOR : return SMALL_OPERAND_UNSIGNED ( x ) ; case PLUS : case LT : case LTU : return SMALL_OPERAND ( x ) ; case EQ : case NE : case GT : case GTU : return x == 0 ; case GE : case GEU : return x == 1 ; case LE : return SMALL_OPERAND ( x + 1 ) ; case LEU : return SMALL_OPERAND ( x + 1 ) && x + 1 != 0 ; case SIGN_EXTRACT : case ZERO_EXTRACT : return ISA_HAS_EXT_INS ; default : return x == 0 ; } } </s>

Return true if there is a non-MIPS16 instruction that implements CODE and if that instruction accepts X as an immediate operand .


<s>
static
void
x86_print_call_or_nop
(
FILE
*
file
,
const
char
*
target
)
{
if
(
flag_nop_mcount
)
fprintf
(
file
,
"1:"
ASM_BYTE
"0x0f, 0x1f, 0x44, 0x00, 0x00\n"
)
;
else
fprintf
(
file
,
"1:\tcall\t%s\n"
,
target
)
;
}
</s>


<s> rtx tilepro_simd_int ( rtx num , machine_mode mode ) { HOST_WIDE_INT n = 0 ; gcc_assert ( CONST_INT_P ( num ) ) ; n = INTVAL ( num ) ; switch ( mode ) { case QImode : n = 0x01010101 * ( n & 0x000000FF ) ; break ; case HImode : n = 0x00010001 * ( n & 0x0000FFFF ) ; break ; case SImode : break ; case DImode : break ; default : gcc_unreachable ( ) ; } return gen_int_si ( n ) ; } </s>

Return the simd variant of the constant NUM of mode MODE , by replicating it to fill an interger of mode SImode . NUM is first truncated to fit in MODE .


<s>
bool
AMDGPUAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
SetupMachineFunction
(
MF
)
;
OutStreamer
.
emitRawComment
(
Twine
(
'@'
)
+
MF
.
getName
(
)
+
Twine
(
':'
)
)
;
MCContext
&
Context
=
getObjFileLowering
(
)
.
getContext
(
)
;
const
MCSectionELF
*
ConfigSection
=
Context
.
getELFSection
(
".AMDGPU.config"
,
ELF
::
SHT_PROGBITS
,
0
,
SectionKind
::
getReadOnly
(
)
)
;
OutStreamer
.
SwitchSection
(
ConfigSection
)
;
const
AMDGPUSubtarget
&
STM
=
TM
.
getSubtarget
<
AMDGPUSubtarget
>
(
)
;
SIProgramInfo
KernelInfo
;
if
(
STM
.
getGeneration
(
)
>
AMDGPUSubtarget
::
NORTHERN_ISLANDS
)
{
getSIProgramInfo
(
KernelInfo
,
MF
)
;
EmitProgramInfoSI
(
MF
,
KernelInfo
)
;
}
else
{
EmitProgramInfoR600
(
MF
)
;
}
DisasmLines
.
clear
(
)
;
HexLines
.
clear
(
)
;
DisasmLineMaxLen
=
0
;
OutStreamer
.
SwitchSection
(
getObjFileLowering
(
)
.
getTextSection
(
)
)
;
EmitFunctionBody
(
)
;
if
(
isVerbose
(
)
)
{
const
MCSectionELF
*
CommentSection
=
Context
.
getELFSection
(
".AMDGPU.csdata"
,
ELF
::
SHT_PROGBITS
,
0
,
SectionKind
::
getReadOnly
(
)
)
;
OutStreamer
.
SwitchSection
(
CommentSection
)
;
if
(
STM
.
getGeneration
(
)
>=
AMDGPUSubtarget
::
SOUTHERN_ISLANDS
)
{
OutStreamer
.
emitRawComment
(
" Kernel info:"
,
false
)
;
OutStreamer
.
emitRawComment
(
" codeLenInByte = "
+
Twine
(
KernelInfo
.
CodeLen
)
,
false
)
;
OutStreamer
.
emitRawComment
(
" NumSgprs: "
+
Twine
(
KernelInfo
.
NumSGPR
)
,
false
)
;
OutStreamer
.
emitRawComment
(
" NumVgprs: "
+
Twine
(
KernelInfo
.
NumVGPR
)
,
false
)
;
}
else
{
R600MachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
R600MachineFunctionInfo
>
(
)
;
OutStreamer
.
emitRawComment
(
Twine
(
"SQ_PGM_RESOURCES:STACK_SIZE = "
+
Twine
(
MFI
->
StackSize
)
)
)
;
}
}
if
(
STM
.
dumpCode
(
)
)
{
MF
.
dump
(
)
;
if
(
DisasmEnabled
)
{
OutStreamer
.
SwitchSection
(
Context
.
getELFSection
(
".AMDGPU.disasm"
,
ELF
::
SHT_NOTE
,
0
,
SectionKind
::
getReadOnly
(
)
)
)
;
for
(
size_t
i
=
0
;
i
<
DisasmLines
.
size
(
)
;
++
i
)
{
std
::
string
Comment
(
DisasmLineMaxLen
DisasmLines
[
i
]
.
size
(
)
,
' '
)
;
Comment
+=
" ; "
+
HexLines
[
i
]
+
"\n"
;
OutStreamer
.
EmitBytes
(
StringRef
(
DisasmLines
[
i
]
)
)
;
OutStreamer
.
EmitBytes
(
StringRef
(
Comment
)
)
;
}
}
}
return
false
;
}
</s>


<s> void BPFPassConfig :: addPreEmitPass ( ) { const BPFSubtarget * Subtarget = getBPFTargetMachine ( ) . getSubtargetImpl ( ) ; addPass ( createBPFMIPreEmitCheckingPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) if ( Subtarget -> getHasAlu32 ( ) && ! DisableMIPeephole ) addPass ( createBPFMIPreEmitPeepholePass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void BTFTypeFuncProto :: completeType ( BTFDebug & BDebug ) { DITypeRefArray Elements = STy -> getTypeArray ( ) ; auto RetType = Elements [ 0 ] ; BTFType . Type = RetType ? BDebug . getTypeId ( RetType ) : 0 ; BTFType . NameOff = 0 ; for ( unsigned I = 1 , N = Elements . size ( ) ; I < N ; ++ I ) { struct BTF :: BTFParam Param ; auto Element = Elements [ I ] ; if ( Element ) { Param . NameOff = BDebug . addString ( FuncArgNames [ I ] ) ; Param . Type = BDebug . getTypeId ( Element ) ; } else { Param . NameOff = 0 ; Param . Type = 0 ; } Parameters . push_back ( Param ) ; } } </s>

Complete BTF type generation after all related DebugInfo types have been visited so their BTF type id 's are available for cross referece .


Return true if the vector misalignment factor is supported by the target .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Hexagon Store Widening"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool ix86_avoid_lea_for_addr ( rtx_insn * insn , rtx operands [ ] ) { unsigned int regno0 , regno1 , regno2 ; int split_cost ; struct ix86_address parts ; int ok ; if ( ! TARGET_AVOID_LEA_FOR_ADDR || optimize_function_for_size_p ( cfun ) ) return false ; if ( REG_P ( operands [ 1 ] ) || ( SImode_address_operand ( operands [ 1 ] , VOIDmode ) && REG_P ( XEXP ( operands [ 1 ] , 0 ) ) ) ) return false ; if ( ! ix86_ok_to_clobber_flags ( insn ) ) return false ; ok = ix86_decompose_address ( operands [ 1 ] , & parts ) ; gcc_assert ( ok ) ; if ( ( parts . base != NULL_RTX ) + ( parts . index != NULL_RTX ) + ( parts . disp != NULL_RTX ) + ( parts . scale > 1 ) < 2 ) return false ; if ( parts . disp && flag_pic && ! LEGITIMATE_PIC_OPERAND_P ( parts . disp ) ) return false ; regno0 = true_regnum ( operands [ 0 ] ) ; regno1 = INVALID_REGNUM ; regno2 = INVALID_REGNUM ; if ( parts . base ) regno1 = true_regnum ( parts . base ) ; if ( parts . index ) regno2 = true_regnum ( parts . index ) ; split_cost = 0 ; if ( parts . base || parts . index ) { if ( regno1 != regno0 && regno2 != regno0 ) split_cost += 1 ; if ( parts . base && parts . index ) split_cost += 1 ; if ( parts . scale > 1 ) { if ( regno0 != regno1 ) split_cost += 1 ; else if ( regno2 == regno0 ) split_cost += 4 ; else split_cost += parts . scale ; } if ( parts . disp && parts . disp != const0_rtx ) split_cost += 1 ; split_cost -= 1 ; } return ! ix86_lea_outperforms ( insn , regno0 , regno1 , regno2 , split_cost , parts . scale > 1 ) ; } </s>

Return true if we need to split lea into a sequence of instructions to avoid AGU stalls during peephole2 .


<s>
unsigned
MipsCodeEmitter
::
getBranchTarget26OpValue
(
const
MachineInstr
&
MI
,
unsigned
OpNo
)
const
{
llvm_unreachable
(
"Unimplemented function."
)
;
return
0
;
}
</s>

getBranchTarget26OpValue - Return binary encoding of the branch target operand .