<s>
void
M680x0AsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
{
if
(
MI
->
isPseudo
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Pseudo opcode("
<<
MI
->
getOpcode
(
)
<<
") found in EmitInstruction()\n"
)
;
llvm_unreachable
(
"Cannot proceed"
)
;
}
break
;
}
case
M680x0
::
TAILJMPj
:
case
M680x0
::
TAILJMPq
:
OutStreamer
->
AddComment
(
"TAILCALL"
)
;
break
;
}
MCInst
TmpInst0
;
MCInstLowering
->
Lower
(
MI
,
TmpInst0
)
;
OutStreamer
->
EmitInstruction
(
TmpInst0
,
getSubtargetInfo
(
)
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> unsigned AlphaRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? Alpha :: R15 : Alpha :: R30 ; } </s>


<s> static bool epiphany_rtx_costs ( rtx x , int code , int outer_code , int opno ATTRIBUTE_UNUSED , int * total , bool speed ATTRIBUTE_UNUSED ) { switch ( code ) { case CONST_INT : if ( ( outer_code == PLUS || outer_code == MINUS ) && SIMM11 ( INTVAL ( x ) ) ) { * total = 0 ; return true ; } if ( IMM16 ( INTVAL ( x ) ) ) { * total = outer_code == SET ? 0 : COSTS_N_INSNS ( 1 ) ; return true ; } case CONST : case LABEL_REF : case SYMBOL_REF : * total = COSTS_N_INSNS ( ( epiphany_small16 ( x ) ? 0 : 1 ) + ( outer_code == SET ? 0 : 1 ) ) ; return true ; case CONST_DOUBLE : { rtx high , low ; split_double ( x , & high , & low ) ; * total = COSTS_N_INSNS ( ! IMM16 ( INTVAL ( high ) ) + ! IMM16 ( INTVAL ( low ) ) ) ; return true ; } case ASHIFT : case ASHIFTRT : case LSHIFTRT : * total = COSTS_N_INSNS ( 1 ) ; return true ; case COMPARE : switch ( GET_MODE ( x ) ) { case CC_N_NEmode : case CC_C_LTUmode : case CC_C_GTUmode : return true ; default : return false ; } case SET : { rtx src = SET_SRC ( x ) ; if ( BINARY_P ( src ) ) * total = 0 ; return false ; } default : return false ; } } </s>

Compute a ( partial ) cost for rtx X . Return true if the complete cost has been computed , and false if subexpressions should be scanned . In either case , * TOTAL contains the cost result .


<s>
StringRef
getPassName
(
)
const
override
{
return
"TVM Register Stackify"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool ARM64TargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { if ( ! EnableARM64TailCalls ) return false ; if ( ! CI -> isTailCall ( ) ) return false ; return true ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> bool nds32_e8_load_to_ii_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx def_reg = SET_DEST ( PATTERN ( producer ) ) ; return e8_consumed_by_addr_in_p ( consumer , def_reg ) ; } </s>


<s> static bool bfin_can_use_doloop_p ( const widest_int & , const widest_int & iterations_max , unsigned int , bool ) { if ( ! flag_unsafe_loop_optimizations && wi :: geu_p ( iterations_max , 0xFFFFFFFF ) ) return false ; return true ; } </s>


<s> bool SIInstrInfo :: hasUnwantedEffectsWhenEXECEmpty ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( MI . mayStore ( ) && isSMRD ( MI ) ) return true ; if ( MI . isReturn ( ) ) return true ; if ( Opcode == AMDGPU :: S_SENDMSG || Opcode == AMDGPU :: S_SENDMSGHALT || Opcode == AMDGPU :: EXP || Opcode == AMDGPU :: EXP_DONE || Opcode == AMDGPU :: DS_ORDERED_COUNT || Opcode == AMDGPU :: S_TRAP || Opcode == AMDGPU :: DS_GWS_INIT || Opcode == AMDGPU :: DS_GWS_BARRIER ) return true ; if ( MI . isCall ( ) || MI . isInlineAsm ( ) ) return true ; if ( modifiesModeRegister ( MI ) ) return true ; if ( Opcode == AMDGPU :: V_READFIRSTLANE_B32 || Opcode == AMDGPU :: V_READLANE_B32 ) return true ; return false ; } </s>

Whether we must prevent this instruction from executing with EXEC = 0 .


<s> static rtx rs6000_function_value ( const_tree valtype , const_tree fn_decl_or_type ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode mode ; unsigned int regno ; machine_mode elt_mode ; int n_elts ; if ( TARGET_MACHO && rs6000_darwin64_struct_check_p ( TYPE_MODE ( valtype ) , valtype ) ) { CUMULATIVE_ARGS valcum ; rtx valret ; valcum . words = 0 ; valcum . fregno = FP_ARG_MIN_REG ; valcum . vregno = ALTIVEC_ARG_MIN_REG ; valret = rs6000_darwin64_record_arg ( & valcum , valtype , true , true ) ; if ( valret ) return valret ; } mode = TYPE_MODE ( valtype ) ; if ( rs6000_discover_homogeneous_aggregate ( mode , valtype , & elt_mode , & n_elts ) ) { int first_reg , n_regs ; if ( SCALAR_FLOAT_MODE_P ( elt_mode ) ) { first_reg = ( elt_mode == TDmode ) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN ; n_regs = ( GET_MODE_SIZE ( elt_mode ) + 7 ) >> 3 ; } else { first_reg = ALTIVEC_ARG_RETURN ; n_regs = 1 ; } return rs6000_parallel_return ( mode , n_elts , elt_mode , first_reg , n_regs ) ; } if ( TARGET_32BIT && TARGET_POWERPC64 ) switch ( mode ) { default : break ; case DImode : case SCmode : case DCmode : case TCmode : int count = GET_MODE_SIZE ( mode ) / 4 ; return rs6000_parallel_return ( mode , count , SImode , GP_ARG_RETURN , 1 ) ; } if ( ( INTEGRAL_TYPE_P ( valtype ) && GET_MODE_BITSIZE ( mode ) < ( TARGET_32BIT ? 32 : 64 ) ) || POINTER_TYPE_P ( valtype ) ) mode = TARGET_32BIT ? SImode : DImode ; if ( DECIMAL_FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = ( mode == TDmode ) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN ; else if ( SCALAR_FLOAT_TYPE_P ( valtype ) && TARGET_HARD_FLOAT && TARGET_FPRS && ( ( TARGET_SINGLE_FLOAT && ( mode == SFmode ) ) || TARGET_DOUBLE_FLOAT ) ) regno = FP_ARG_RETURN ; else if ( TREE_CODE ( valtype ) == COMPLEX_TYPE && targetm . calls . split_complex_arg ) return rs6000_complex_function_value ( mode ) ; else if ( TREE_CODE ( valtype ) == VECTOR_TYPE && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI && ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) ) regno = ALTIVEC_ARG_RETURN ; else if ( TARGET_E500_DOUBLE && TARGET_HARD_FLOAT && ( mode == DFmode || mode == DCmode || mode == TFmode || mode == TCmode ) ) return spe_build_register_parallel ( mode , GP_ARG_RETURN ) ; else regno = GP_ARG_RETURN ; return gen_rtx_REG ( mode , regno ) ; } </s>

Define how to find the value returned by a function . VALTYPE is the data type of the value ( as a tree ) . If the precise function being called is known , FUNC is its FUNCTION_DECL ; otherwise , FUNC is 0 . On the SPE , both FPs and vectors are returned in r3 . On RS/6000 an integer value is in r3 and a floating-point value is in fp1 , unless -msoft-float .


<s> bool M68kPassConfig :: addInstSelector ( ) { addPass ( createM68kISelDag ( getM68kTargetMachine ( ) ) ) ; addPass ( createM68kGlobalBaseRegPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s>
void
X86InstrInfo
::
reMaterialize
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
Register
DestReg
,
unsigned
SubIdx
,
const
MachineInstr
&
Orig
,
const
TargetRegisterInfo
&
TRI
)
const
{
bool
ClobbersEFLAGS
=
Orig
.
modifiesRegister
(
X86
::
EFLAGS
,
&
TRI
)
;
if
(
ClobbersEFLAGS
&&
MBB
.
computeRegisterLiveness
(
&
TRI
,
X86
::
EFLAGS
,
I
)
!=
MachineBasicBlock
::
LQR_Dead
)
{
int
Value
;
switch
(
Orig
.
getOpcode
(
)
)
{
case
X86
::
MOV32r0
:
Value
=
0
;
break
;
case
X86
::
MOV32r1
:
Value
=
1
;
break
;
case
X86
::
MOV32r_1
:
Value
=
1
;
break
;
default
:
llvm_unreachable
(
"Unexpected instruction!"
)
;
}
const
DebugLoc
&
DL
=
Orig
.
getDebugLoc
(
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
X86
::
MOV32ri
)
)
.
add
(
Orig
.
getOperand
(
0
)
)
.
addImm
(
Value
)
;
}
else
{
MachineInstr
*
MI
=
MBB
.
getParent
(
)
->
CloneMachineInstr
(
&
Orig
)
;
MBB
.
insert
(
I
,
MI
)
;
}
MachineInstr
&
NewMI
=
*
std
::
prev
(
I
)
;
NewMI
.
substituteRegister
(
Orig
.
getOperand
(
0
)
.
getReg
(
)
,
DestReg
,
SubIdx
,
TRI
)
;
}
</s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s> static rtx altivec_expand_vec_init_builtin ( tree type , tree exp , rtx target ) { machine_mode tmode = TYPE_MODE ( type ) ; machine_mode inner_mode = GET_MODE_INNER ( tmode ) ; int i , n_elt = GET_MODE_NUNITS ( tmode ) ; gcc_assert ( VECTOR_MODE_P ( tmode ) ) ; gcc_assert ( n_elt == call_expr_nargs ( exp ) ) ; if ( ! target || ! register_operand ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( n_elt == 1 && GET_MODE_SIZE ( tmode ) == GET_MODE_SIZE ( inner_mode ) ) { rtx x = expand_normal ( CALL_EXPR_ARG ( exp , 0 ) ) ; emit_move_insn ( target , gen_lowpart ( tmode , x ) ) ; } else { rtvec v = rtvec_alloc ( n_elt ) ; for ( i = 0 ; i < n_elt ; ++ i ) { rtx x = expand_normal ( CALL_EXPR_ARG ( exp , i ) ) ; RTVEC_ELT ( v , i ) = gen_lowpart ( inner_mode , x ) ; } rs6000_expand_vector_init ( target , gen_rtx_PARALLEL ( tmode , v ) ) ; } return target ; } </s>


<s> MVT TeakTargetLowering :: getScalarShiftAmountTy ( const DataLayout & DL , EVT ) const { return MVT :: i40 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> static bool tilepro_return_in_memory ( const_tree type , const_tree fndecl ATTRIBUTE_UNUSED ) { return ! IN_RANGE ( int_size_in_bytes ( type ) , 0 , TILEPRO_NUM_RETURN_REGS * UNITS_PER_WORD ) ; } </s>


"frame pointer should not have been eliminated"

"SecondSPAdjustAmount should be greater than zero"


<s>
bool
SIFoldOperands
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
*
MF
.
getFunction
(
)
)
)
return
false
;
const
SISubtarget
&
ST
=
MF
.
getSubtarget
<
SISubtarget
>
(
)
;
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
const
SIInstrInfo
*
TII
=
ST
.
getInstrInfo
(
)
;
const
SIRegisterInfo
&
TRI
=
TII
->
getRegisterInfo
(
)
;
for
(
MachineFunction
::
iterator
BI
=
MF
.
begin
(
)
,
BE
=
MF
.
end
(
)
;
BI
!=
BE
;
++
BI
)
{
MachineBasicBlock
&
MBB
=
*
BI
;
MachineBasicBlock
::
iterator
I
,
Next
;
for
(
I
=
MBB
.
begin
(
)
;
I
!=
MBB
.
end
(
)
;
I
=
Next
)
{
Next
=
std
::
next
(
I
)
;
MachineInstr
&
MI
=
*
I
;
if
(
!
isSafeToFold
(
MI
.
getOpcode
(
)
)
)
continue
;
unsigned
OpSize
=
TII
->
getOpSize
(
MI
,
1
)
;
MachineOperand
&
OpToFold
=
MI
.
getOperand
(
1
)
;
bool
FoldingImm
=
OpToFold
.
isImm
(
)
;
if
(
!
FoldingImm
&&
!
OpToFold
.
isReg
(
)
)
continue
;
if
(
FoldingImm
&&
!
TII
->
isInlineConstant
(
OpToFold
,
OpSize
)
&&
!
MRI
.
hasOneUse
(
MI
.
getOperand
(
0
)
.
getReg
(
)
)
)
continue
;
if
(
OpToFold
.
isReg
(
)
&&
!
TargetRegisterInfo
::
isVirtualRegister
(
OpToFold
.
getReg
(
)
)
)
continue
;
MachineOperand
&
Dst
=
MI
.
getOperand
(
0
)
;
if
(
Dst
.
isReg
(
)
&&
!
TargetRegisterInfo
::
isVirtualRegister
(
Dst
.
getReg
(
)
)
)
continue
;
SmallVector
<
MachineInstr
*
,
4
>
CopiesToReplace
;
std
::
vector
<
FoldCandidate
>
FoldList
;
for
(
MachineRegisterInfo
::
use_iterator
Use
=
MRI
.
use_begin
(
MI
.
getOperand
(
0
)
.
getReg
(
)
)
,
E
=
MRI
.
use_end
(
)
;
Use
!=
E
;
++
Use
)
{
MachineInstr
*
UseMI
=
Use
->
getParent
(
)
;
foldOperand
(
OpToFold
,
UseMI
,
Use
.
getOperandNo
(
)
,
FoldList
,
CopiesToReplace
,
TII
,
TRI
,
MRI
)
;
}
for
(
MachineInstr
*
Copy
:
CopiesToReplace
)
Copy
->
addImplicitDefUseOperands
(
MF
)
;
for
(
FoldCandidate
&
Fold
:
FoldList
)
{
if
(
updateOperand
(
Fold
,
TRI
)
)
{
if
(
!
Fold
.
isImm
(
)
)
{
assert
(
Fold
.
OpToFold
&&
Fold
.
OpToFold
->
isReg
(
)
)
;
MRI
.
clearKillFlags
(
Fold
.
OpToFold
->
getReg
(
)
)
;
}
DEBUG
(
dbgs
(
)
<<
"Folded source from "
<<
MI
<<
" into OpNo "
<<
Fold
.
UseOpNo
<<
" of "
<<
*
Fold
.
UseMI
<<
'\n'
)
;
}
}
}
}
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> void ARMBaseRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { ARMFunctionInfo * AFI = MBB -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? ARM :: ADDri : ( AFI -> isThumb1OnlyFunction ( ) ? ARM :: tADDframe : ARM :: t2ADDri ) ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , 0 , this , MF ) ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ; if ( ! AFI -> isThumb1OnlyFunction ( ) ) MIB . add ( predOps ( ARMCC :: AL ) ) . add ( condCodeOp ( ) ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .

ARM ARM ARM ARM ARM::ADDri ARM::tADDframe ARM::t2ADDri 0 ARMCC::AL


<s> const VEInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> void BPFDAGToDAGISel :: PreprocessISelDAG ( ) { if ( ! curr_func_ ) { curr_func_ = FuncInfo -> Fn ; } else if ( curr_func_ != FuncInfo -> Fn ) { load_to_vreg_ . clear ( ) ; curr_func_ = FuncInfo -> Fn ; } for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * Node = & * I ++ ; unsigned Opcode = Node -> getOpcode ( ) ; if ( Opcode == ISD :: LOAD ) PreprocessLoad ( Node , I ) ; else if ( Opcode == ISD :: CopyToReg ) PreprocessCopyToReg ( Node ) ; else if ( Opcode == ISD :: AND ) PreprocessTrunc ( Node , I ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .

BPF BPF ISD::LOAD ISD::CopyToReg ISD::AND


<s> void AMDGPUAsmPrinter :: emitFunctionEntryLabel ( ) { if ( TM . getTargetTriple ( ) . getOS ( ) == Triple :: AMDHSA && isHsaAbiVersion3Or4 ( getGlobalSTI ( ) ) ) { AsmPrinter :: emitFunctionEntryLabel ( ) ; return ; } const SIMachineFunctionInfo * MFI = MF -> getInfo < SIMachineFunctionInfo > ( ) ; const GCNSubtarget & STM = MF -> getSubtarget < GCNSubtarget > ( ) ; if ( MFI -> isEntryFunction ( ) && STM . isAmdHsaOrMesa ( MF -> getFunction ( ) ) ) { SmallString < 128 > SymbolName ; getNameWithPrefix ( SymbolName , & MF -> getFunction ( ) ) , getTargetStreamer ( ) -> EmitAMDGPUSymbolType ( SymbolName , ELF :: STT_AMDGPU_HSA_KERNEL ) ; } if ( DumpCodeInstEmitter ) { DisasmLines . push_back ( MF -> getName ( ) . str ( ) + ":" ) ; DisasmLineMaxLen = std :: max ( DisasmLineMaxLen , DisasmLines . back ( ) . size ( ) ) ; HexLines . push_back ( "" ) ; } AsmPrinter :: emitFunctionEntryLabel ( ) ; } </s>

EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function .

AMDGPU AMDGPU SI SI 128 AMDGPU AMDGPU ":" ""


<s> unsigned getEUsPerCU ( const MCSubtargetInfo * STI ) { if ( isGFX10 ( * STI ) && STI -> getFeatureBits ( ) . test ( FeatureCuMode ) ) return 2 ; return 4 ; } </s>

Number of SIMDs/EUs ( execution units ) per `` CU '' ( `` compute unit '' ) , where the `` CU '' is the unit onto which workgroups are mapped .


<s>
static
rtx
s390_expand_builtin
(
tree
exp
,
rtx
target
,
rtx
subtarget
ATTRIBUTE_UNUSED
,
enum
machine_mode
mode
ATTRIBUTE_UNUSED
,
int
ignore
ATTRIBUTE_UNUSED
)
{
unsigned
int
const
*
code_for_builtin
=
TARGET_64BIT
code_for_builtin_64
:
code_for_builtin_31
;
tree
fndecl
=
TREE_OPERAND
(
TREE_OPERAND
(
exp
,
0
)
,
0
)
;
unsigned
int
fcode
=
DECL_FUNCTION_CODE
(
fndecl
)
;
tree
arglist
=
TREE_OPERAND
(
exp
,
1
)
;
enum
insn_code
icode
;
rtx
op
[
MAX_ARGS
]
,
pat
;
int
arity
;
bool
nonvoid
;
if
(
fcode
>=
S390_BUILTIN_max
)
internal_error
(
"bad builtin fcode"
)
;
icode
=
code_for_builtin
[
fcode
]
;
if
(
icode
==
0
)
internal_error
(
"bad builtin fcode"
)
;
nonvoid
=
TREE_TYPE
(
TREE_TYPE
(
fndecl
)
)
!=
void_type_node
;
for
(
arglist
=
TREE_OPERAND
(
exp
,
1
)
,
arity
=
0
;
arglist
;
arglist
=
TREE_CHAIN
(
arglist
)
,
arity
++
)
{
const
struct
insn_operand_data
*
insn_op
;
tree
arg
=
TREE_VALUE
(
arglist
)
;
if
(
arg
==
error_mark_node
)
return
NULL_RTX
;
if
(
arity
>
MAX_ARGS
)
return
NULL_RTX
;
insn_op
=
&
insn_data
[
icode
]
.
operand
[
arity
+
nonvoid
]
;
op
[
arity
]
=
expand_expr
(
arg
,
NULL_RTX
,
insn_op
->
mode
,
0
)
;
if
(
!
(
*
insn_op
->
predicate
)
(
op
[
arity
]
,
insn_op
->
mode
)
)
op
[
arity
]
=
copy_to_mode_reg
(
insn_op
->
mode
,
op
[
arity
]
)
;
}
if
(
nonvoid
)
{
enum
machine_mode
tmode
=
insn_data
[
icode
]
.
operand
[
0
]
.
mode
;
if
(
!
target
||
GET_MODE
(
target
)
!=
tmode
||
!
(
*
insn_data
[
icode
]
.
operand
[
0
]
.
predicate
)
(
target
,
tmode
)
)
target
=
gen_reg_rtx
(
tmode
)
;
}
switch
(
arity
)
{
case
0
:
pat
=
GEN_FCN
(
icode
)
(
target
)
;
break
;
case
1
:
if
(
nonvoid
)
pat
=
GEN_FCN
(
icode
)
(
target
,
op
[
0
]
)
;
else
pat
=
GEN_FCN
(
icode
)
(
op
[
0
]
)
;
break
;
case
2
:
pat
=
GEN_FCN
(
icode
)
(
target
,
op
[
0
]
,
op
[
1
]
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
if
(
!
pat
)
return
NULL_RTX
;
emit_insn
(
pat
)
;
if
(
nonvoid
)
return
target
;
else
return
const0_rtx
;
}
</s>

Expand an expression EXP that calls a built-in function , with result going to TARGET if that 's convenient ( and in mode MODE if that 's convenient ) . SUBTARGET may be used as the target for computing one of EXP 's operands . IGNORE is nonzero if the value is to be ignored .


<s> bool MBlazeAsmBackend :: mayNeedRelaxation ( const MCInst & Inst ) const { if ( getRelaxedOpcode ( Inst . getOpcode ( ) ) == Inst . getOpcode ( ) ) return false ; bool hasExprOrImm = false ; for ( unsigned i = 0 ; i < Inst . getNumOperands ( ) ; ++ i ) hasExprOrImm |= Inst . getOperand ( i ) . isExpr ( ) ; return hasExprOrImm ; } </s>

Check whether the given instruction may need relaxation .


<s> static void tilegx_setup_incoming_varargs ( cumulative_args_t cum , machine_mode mode , tree type , int * pretend_args , int no_rtl ) { CUMULATIVE_ARGS local_cum = * get_cumulative_args ( cum ) ; int first_reg ; targetm . calls . function_arg_advance ( pack_cumulative_args ( & local_cum ) , mode , type , true ) ; first_reg = local_cum ; if ( local_cum < TILEGX_NUM_ARG_REGS ) { * pretend_args = UNITS_PER_WORD * ( TILEGX_NUM_ARG_REGS - first_reg ) ; if ( ! no_rtl ) { alias_set_type set = get_varargs_alias_set ( ) ; rtx tmp = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , virtual_incoming_args_rtx , - STACK_POINTER_OFFSET - UNITS_PER_WORD * ( TILEGX_NUM_ARG_REGS - first_reg ) ) ) ; MEM_NOTRAP_P ( tmp ) = 1 ; set_mem_alias_set ( tmp , set ) ; move_block_from_reg ( first_reg , tmp , TILEGX_NUM_ARG_REGS - first_reg ) ; } } else * pretend_args = 0 ; } </s>


<s>
const
char
*
ix86_output_function_return
(
bool
long_p
)
{
output_return_instrumentation
(
)
;
if
(
cfun
->
machine
->
function_return_type
!=
indirect_branch_keep
)
{
char
thunk_name
[
32
]
;
enum
indirect_thunk_prefix
need_prefix
=
indirect_thunk_need_prefix
(
current_output_insn
)
;
if
(
cfun
->
machine
->
function_return_type
!=
indirect_branch_thunk_inline
)
{
bool
need_thunk
=
(
cfun
->
machine
->
function_return_type
==
indirect_branch_thunk
)
;
indirect_thunk_name
(
thunk_name
,
INVALID_REGNUM
,
need_prefix
,
true
)
;
indirect_return_needed
|=
need_thunk
;
fprintf
(
asm_out_file
,
"\tjmp\t%s\n"
,
thunk_name
)
;
}
else
output_indirect_thunk
(
INVALID_REGNUM
)
;
return
""
;
}
if
(
!
long_p
)
return
"%!ret"
;
return
"rep%; ret"
;
}
</s>

Output function return . CALL_OP is the jump target . Add a REP prefix to RET if LONG_P is true and function return is kept .


<s> bool MCS51FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MCS51MachineFunctionInfo * FuncInfo = MF . getInfo < MCS51MachineFunctionInfo > ( ) ; return ( FuncInfo -> getHasSpills ( ) || FuncInfo -> getHasAllocas ( ) || FuncInfo -> getHasStackArgs ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
char
*
aarch64_output_simd_mov_immediate
(
rtx
const_vector
,
unsigned
width
,
enum
simd_immediate_check
which
)
{
bool
is_valid
;
static
char
templ
[
40
]
;
const
char
*
mnemonic
;
const
char
*
shift_op
;
unsigned
int
lane_count
=
0
;
char
element_char
;
struct
simd_immediate_info
info
;
is_valid
=
aarch64_simd_valid_immediate
(
const_vector
,
&
info
,
which
)
;
gcc_assert
(
is_valid
)
;
element_char
=
sizetochar
(
GET_MODE_BITSIZE
(
info
.
elt_mode
)
)
;
lane_count
=
width
/
GET_MODE_BITSIZE
(
info
.
elt_mode
)
;
if
(
GET_MODE_CLASS
(
info
.
elt_mode
)
==
MODE_FLOAT
)
{
gcc_assert
(
info
.
shift
==
0
&&
info
.
insn
==
simd_immediate_info
::
MOV
)
;
if
(
aarch64_float_const_zero_rtx_p
(
info
.
value
)
)
info
.
value
=
GEN_INT
(
0
)
;
else
{
const
unsigned
int
buf_size
=
20
;
char
float_buf
[
buf_size
]
=
{
'\0'
}
;
real_to_decimal_for_mode
(
float_buf
,
CONST_DOUBLE_REAL_VALUE
(
info
.
value
)
,
buf_size
,
buf_size
,
1
,
info
.
elt_mode
)
;
if
(
lane_count
==
1
)
snprintf
(
templ
,
sizeof
(
templ
)
,
"fmov\t%%d0, %s"
,
float_buf
)
;
else
snprintf
(
templ
,
sizeof
(
templ
)
,
"fmov\t%%0.%d%c, %s"
,
lane_count
,
element_char
,
float_buf
)
;
return
templ
;
}
}
gcc_assert
(
CONST_INT_P
(
info
.
value
)
)
;
if
(
which
==
AARCH64_CHECK_MOV
)
{
mnemonic
=
info
.
insn
==
simd_immediate_info
::
MVN
"mvni"
:
"movi"
;
shift_op
=
info
.
modifier
==
simd_immediate_info
::
MSL
"msl"
:
"lsl"
;
if
(
lane_count
==
1
)
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%d0, "
HOST_WIDE_INT_PRINT_HEX
,
mnemonic
,
UINTVAL
(
info
.
value
)
)
;
else
if
(
info
.
shift
)
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%0.%d%c, "
HOST_WIDE_INT_PRINT_HEX
", %s %d"
,
mnemonic
,
lane_count
,
element_char
,
UINTVAL
(
info
.
value
)
,
shift_op
,
info
.
shift
)
;
else
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%0.%d%c, "
HOST_WIDE_INT_PRINT_HEX
,
mnemonic
,
lane_count
,
element_char
,
UINTVAL
(
info
.
value
)
)
;
}
else
{
mnemonic
=
info
.
insn
==
simd_immediate_info
::
MVN
"bic"
:
"orr"
;
if
(
info
.
shift
)
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%0.%d%c, #"
HOST_WIDE_INT_PRINT_DEC
", %s #%d"
,
mnemonic
,
lane_count
,
element_char
,
UINTVAL
(
info
.
value
)
,
"lsl"
,
info
.
shift
)
;
else
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%0.%d%c, #"
HOST_WIDE_INT_PRINT_DEC
,
mnemonic
,
lane_count
,
element_char
,
UINTVAL
(
info
.
value
)
)
;
}
return
templ
;
}
</s>

Returns the string with the instruction for AdvSIMD MOVI , MVNI , ORR or BIC immediate with a CONST_VECTOR of MODE and WIDTH . WHICH selects whether to output MOVI/MVNI , ORR or BIC immediate .


<s> static void emit_predicate_relation_info ( void ) { basic_block bb ; FOR_EACH_BB_REVERSE_FN ( bb , cfun ) { int r ; rtx_insn * head = BB_HEAD ( bb ) ; if ( ! LABEL_P ( head ) ) continue ; if ( NOTE_INSN_BASIC_BLOCK_P ( NEXT_INSN ( head ) ) ) head = NEXT_INSN ( head ) ; for ( r = PR_REG ( 2 ) ; r < PR_REG ( 64 ) ; r += 2 ) if ( REGNO_REG_SET_P ( df_get_live_in ( bb ) , r ) ) { rtx p = gen_rtx_REG ( BImode , r ) ; rtx_insn * n = emit_insn_after ( gen_pred_rel_mutex ( p ) , head ) ; if ( head == BB_END ( bb ) ) BB_END ( bb ) = n ; head = n ; } } FOR_EACH_BB_REVERSE_FN ( bb , cfun ) { rtx_insn * insn = BB_HEAD ( bb ) ; while ( 1 ) { if ( CALL_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == COND_EXEC && find_reg_note ( insn , REG_NORETURN , NULL_RTX ) ) { rtx_insn * b = emit_insn_before ( gen_safe_across_calls_all ( ) , insn ) ; rtx_insn * a = emit_insn_after ( gen_safe_across_calls_normal ( ) , insn ) ; if ( BB_HEAD ( bb ) == insn ) BB_HEAD ( bb ) = b ; if ( BB_END ( bb ) == insn ) BB_END ( bb ) = a ; } if ( insn == BB_END ( bb ) ) break ; insn = NEXT_INSN ( insn ) ; } } } </s>

Emit pseudo-ops for the assembler to describe predicate relations . At present this assumes that we only consider predicate pairs to be mutex , and that the assembler can deduce proper values from straight-line code .


<s> HOST_WIDE_INT pa_initial_elimination_offset ( int from , int to ) { HOST_WIDE_INT offset ; if ( ( from == HARD_FRAME_POINTER_REGNUM || from == FRAME_POINTER_REGNUM ) && to == STACK_POINTER_REGNUM ) offset = - pa_compute_frame_size ( get_frame_size ( ) , 0 ) ; else if ( from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) offset = 0 ; else gcc_unreachable ( ) ; return offset ; } </s>

Define the offset between two registers , FROM to be eliminated and its replacement TO , at the start of a routine .


<s> SMRange getLocRange ( ) const { return SMRange ( StartLoc , EndLoc ) ; } </s>

getLocRange - Get the range between the first and last token of this operand .


<s> void ScheduleDAGPostRA :: enterRegion ( MachineBasicBlock * bb , MachineBasicBlock :: iterator begin , MachineBasicBlock :: iterator end , unsigned endcount ) { EndIndex = endcount ; ScheduleDAGInstrs :: enterRegion ( bb , begin , end , endcount ) ; } </s>

Implement the ScheduleDAGInstrs interface for handling the next scheduling region .


<s> bool AArch64TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( AM . BaseGV ) return false ; if ( AM . HasBaseReg && AM . BaseOffs && AM . Scale ) return false ; if ( isa < ScalableVectorType > ( Ty ) ) { uint64_t VecElemNumBytes = DL . getTypeSizeInBits ( cast < VectorType > ( Ty ) -> getElementType ( ) ) / 8 ; return AM . HasBaseReg && ! AM . BaseOffs && ( AM . Scale == 0 || ( uint64_t ) AM . Scale == VecElemNumBytes ) ; } uint64_t NumBytes = 0 ; if ( Ty -> isSized ( ) ) { uint64_t NumBits = DL . getTypeSizeInBits ( Ty ) ; NumBytes = NumBits / 8 ; if ( ! isPowerOf2_64 ( NumBits ) ) NumBytes = 0 ; } if ( ! AM . Scale ) { int64_t Offset = AM . BaseOffs ; if ( isInt < 9 > ( Offset ) ) return true ; unsigned shift = Log2_64 ( NumBytes ) ; if ( NumBytes && Offset > 0 && ( Offset / NumBytes ) <= ( 1LL << 12 ) - 1 && ( Offset >> shift ) << shift == Offset ) return true ; return false ; } return AM . Scale == 1 || ( AM . Scale > 0 && ( uint64_t ) AM . Scale == NumBytes ) ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> void ARMBaseRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { ARMFunctionInfo * AFI = MBB -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? ARM :: ADDri : ( AFI -> isThumb1OnlyFunction ( ) ? ARM :: tADDrSPi : ARM :: t2ADDri ) ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , 0 , this , MF ) ) ; MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ) ; if ( ! AFI -> isThumb1OnlyFunction ( ) ) AddDefaultCC ( MIB ) ; } </s>

ARM ARM ARM ARM ARM::ADDri ARM::tADDrSPi ARM::t2ADDri 0


<s> static bool reg_ok_for_base_p ( rtx r , bool strict ) { int NUM = REGNO ( r ) ; if ( strict ) return ( HARD_REGNO_OK_FOR_BASE_P ( NUM ) || HARD_REGNO_OK_FOR_BASE_P ( reg_renumber [ ( NUM ) ] ) ) ; else return ( ( NUM ) >= FIRST_PSEUDO_REGISTER || HARD_REGNO_OK_FOR_BASE_P ( NUM ) ) ; } </s>

Nonzero if X is a hard reg that can be used as an index .


"ERROR: Unknown type of MachineOperand: "

getMachineOpValue - Return binary encoding of operand .


<s> inline set_of_reg sh_find_set_of_reg ( rtx reg , rtx_insn * insn , F stepfunc , bool ignore_reg_reg_copies = false ) { set_of_reg result ; result . insn = insn ; result . set_rtx = NULL_RTX ; result . set_src = NULL_RTX ; if ( ! REG_P ( reg ) || insn == NULL_RTX ) return result ; for ( rtx_insn * i = stepfunc ( insn ) ; i != NULL_RTX ; i = stepfunc ( i ) ) { if ( BARRIER_P ( i ) ) break ; if ( ! INSN_P ( i ) || DEBUG_INSN_P ( i ) ) continue ; if ( reg_set_p ( reg , i ) ) { if ( CALL_P ( i ) ) break ; result . insn = i ; result . set_rtx = set_of ( reg , i ) ; if ( result . set_rtx == NULL_RTX || GET_CODE ( result . set_rtx ) != SET ) break ; result . set_src = XEXP ( result . set_rtx , 1 ) ; if ( ignore_reg_reg_copies && REG_P ( result . set_src ) ) { reg = result . set_src ; continue ; } if ( ignore_reg_reg_copies && SUBREG_P ( result . set_src ) && REG_P ( SUBREG_REG ( result . set_src ) ) ) { reg = SUBREG_REG ( result . set_src ) ; continue ; } break ; } } if ( result . set_src != NULL && result . set_rtx == NULL ) result . set_src = NULL ; return result ; } </s>

Given a reg rtx and a start insn , try to find the insn that sets the specified reg by using the specified insn stepping function , such as 'prev_nonnote_insn_bb ' . When the insn is found , try to extract the rtx of the reg set .


<s> bool mayNeedRelaxation ( const MCInst & ) const { return false ; } </s>


<s> const char * SparcTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case SPISD :: CMPICC : return "SPISD::CMPICC" ; case SPISD :: CMPFCC : return "SPISD::CMPFCC" ; case SPISD :: BRICC : return "SPISD::BRICC" ; case SPISD :: BRFCC : return "SPISD::BRFCC" ; case SPISD :: SELECT_ICC : return "SPISD::SELECT_ICC" ; case SPISD :: SELECT_FCC : return "SPISD::SELECT_FCC" ; case SPISD :: Hi : return "SPISD::Hi" ; case SPISD :: Lo : return "SPISD::Lo" ; case SPISD :: FTOI : return "SPISD::FTOI" ; case SPISD :: ITOF : return "SPISD::ITOF" ; case SPISD :: CALL : return "SPISD::CALL" ; case SPISD :: RET_FLAG : return "SPISD::RET_FLAG" ; case SPISD :: GLOBAL_BASE_REG : return "SPISD::GLOBAL_BASE_REG" ; case SPISD :: FLUSHW : return "SPISD::FLUSHW" ; } } </s>

getTargetNodeName - This method returns the name of a target specific

Sparc Sparc 0 SPISD::CMPICC "SPISD::CMPICC" SPISD::CMPFCC "SPISD::CMPFCC" SPISD::BRICC "SPISD::BRICC" SPISD::BRFCC "SPISD::BRFCC" SPISD::SELECT_ICC "SPISD::SELECT_ICC" SPISD::SELECT_FCC "SPISD::SELECT_FCC" SPISD::Hi "SPISD::Hi" SPISD::Lo "SPISD::Lo" SPISD::FTOI "SPISD::FTOI" SPISD::ITOF "SPISD::ITOF" SPISD::CALL "SPISD::CALL" SPISD::RET_FLAG "SPISD::RET_FLAG" SPISD::GLOBAL_BASE_REG "SPISD::GLOBAL_BASE_REG" SPISD::FLUSHW "SPISD::FLUSHW"


<s> bool AAPRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return false ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> static rtx strip_carry_operation ( rtx op ) { gcc_assert ( GET_CODE ( op ) == PLUS ) ; if ( arm_carry_operation ( XEXP ( op , 0 ) , GET_MODE ( op ) ) ) return XEXP ( op , 1 ) ; else if ( arm_carry_operation ( XEXP ( op , 1 ) , GET_MODE ( op ) ) ) return XEXP ( op , 0 ) ; return op ; } </s>

Helper function for arm_rtx_costs . If one operand of the OP , a PLUS , adds the carry flag , then return the other operand . If neither is a carry , return OP unchanged .


"getJumpTargetOpValue expects only expressions"

"unexpect opcode in getJumpAbsoluteTargetOpValue()"

getJumpTargetOpValue - Return binary encoding of the jump target operand .


<s> void SITargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { switch ( N -> getOpcode ( ) ) { case ISD :: INSERT_VECTOR_ELT : { if ( SDValue Res = lowerINSERT_VECTOR_ELT ( SDValue ( N , 0 ) , DAG ) ) Results . push_back ( Res ) ; return ; } case ISD :: EXTRACT_VECTOR_ELT : { if ( SDValue Res = lowerEXTRACT_VECTOR_ELT ( SDValue ( N , 0 ) , DAG ) ) Results . push_back ( Res ) ; return ; } case ISD :: INTRINSIC_WO_CHAIN : { unsigned IID = cast < ConstantSDNode > ( N -> getOperand ( 0 ) ) -> getZExtValue ( ) ; switch ( IID ) { case Intrinsic :: amdgcn_cvt_pkrtz : { SDValue Src0 = N -> getOperand ( 1 ) ; SDValue Src1 = N -> getOperand ( 2 ) ; SDLoc SL ( N ) ; SDValue Cvt = DAG . getNode ( AMDGPUISD :: CVT_PKRTZ_F16_F32 , SL , MVT :: i32 , Src0 , Src1 ) ; Results . push_back ( DAG . getNode ( ISD :: BITCAST , SL , MVT :: v2f16 , Cvt ) ) ; return ; } default : break ; } } case ISD :: SELECT : { SDLoc SL ( N ) ; EVT VT = N -> getValueType ( 0 ) ; EVT NewVT = getEquivalentMemType ( * DAG . getContext ( ) , VT ) ; SDValue LHS = DAG . getNode ( ISD :: BITCAST , SL , NewVT , N -> getOperand ( 1 ) ) ; SDValue RHS = DAG . getNode ( ISD :: BITCAST , SL , NewVT , N -> getOperand ( 2 ) ) ; EVT SelectVT = NewVT ; if ( NewVT . bitsLT ( MVT :: i32 ) ) { LHS = DAG . getNode ( ISD :: ANY_EXTEND , SL , MVT :: i32 , LHS ) ; RHS = DAG . getNode ( ISD :: ANY_EXTEND , SL , MVT :: i32 , RHS ) ; SelectVT = MVT :: i32 ; } SDValue NewSelect = DAG . getNode ( ISD :: SELECT , SL , SelectVT , N -> getOperand ( 0 ) , LHS , RHS ) ; if ( NewVT != SelectVT ) NewSelect = DAG . getNode ( ISD :: TRUNCATE , SL , NewVT , NewSelect ) ; Results . push_back ( DAG . getNode ( ISD :: BITCAST , SL , VT , NewSelect ) ) ; return ; } default : break ; } } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> int arc_label_align ( rtx_insn * label ) { if ( align_labels_log < 1 ) { rtx_insn * next = next_nonnote_nondebug_insn ( label ) ; if ( INSN_P ( next ) && recog_memoized ( next ) >= 0 ) return 1 ; } return align_labels_log ; } </s>

Oddly enough , sometimes we get a zero overhead loop that branch shortening does n't think is a loop - observed with compile/pr24883.c -O3 -fomit-frame-pointer -funroll-loops . Make sure to include the alignment visible for branch shortening ( we actually align the loop insn before it , but that is equivalent since the loop insn is 4 byte long . )


The darwin64 ABI calls for us to recurse down through structs , looking for elements passed in registers . Unfortunately , we have to track int register count here also because of misalignments in powerpc alignment mode .


<s> Value * RISCVTargetLowering :: emitMaskedAtomicRMWIntrinsic ( IRBuilderBase & Builder , AtomicRMWInst * AI , Value * AlignedAddr , Value * Incr , Value * Mask , Value * ShiftAmt , AtomicOrdering Ord ) const { assert ( ! RISCVABI :: isCheriPureCapABI ( Subtarget . getTargetABI ( ) ) ) ; unsigned XLen = Subtarget . getXLen ( ) ; Value * Ordering = Builder . getIntN ( XLen , static_cast < uint64_t > ( AI -> getOrdering ( ) ) ) ; Type * Tys [ ] = { AlignedAddr -> getType ( ) } ; Function * LrwOpScwLoop = Intrinsic :: getDeclaration ( AI -> getModule ( ) , getIntrinsicForMaskedAtomicRMWBinOp ( XLen , AI -> getOperation ( ) ) , Tys ) ; if ( XLen == 64 ) { Incr = Builder . CreateSExt ( Incr , Builder . getInt64Ty ( ) ) ; Mask = Builder . CreateSExt ( Mask , Builder . getInt64Ty ( ) ) ; ShiftAmt = Builder . CreateSExt ( ShiftAmt , Builder . getInt64Ty ( ) ) ; } Value * Result ; if ( AI -> getOperation ( ) == AtomicRMWInst :: Min || AI -> getOperation ( ) == AtomicRMWInst :: Max ) { const DataLayout & DL = AI -> getModule ( ) -> getDataLayout ( ) ; unsigned ValWidth = DL . getTypeStoreSizeInBits ( AI -> getValOperand ( ) -> getType ( ) ) ; Value * SextShamt = Builder . CreateSub ( Builder . getIntN ( XLen , XLen - ValWidth ) , ShiftAmt ) ; Result = Builder . CreateCall ( LrwOpScwLoop , { AlignedAddr , Incr , Mask , SextShamt , Ordering } ) ; } else { Result = Builder . CreateCall ( LrwOpScwLoop , { AlignedAddr , Incr , Mask , Ordering } ) ; } if ( XLen == 64 ) Result = Builder . CreateTrunc ( Result , Builder . getInt32Ty ( ) ) ; return Result ; } </s>

Perform a masked atomicrmw using a target-specific intrinsic .

RISCV RISCV RISCVABI::isCheriPureCapABI Intrinsic::getDeclaration 64 64


initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s>
void
alpha_end_function
(
FILE
*
file
,
const
char
*
fnname
,
tree
decl
ATTRIBUTE_UNUSED
)
{
rtx_insn
*
insn
;
insn
=
get_last_insn
(
)
;
if
(
!
INSN_P
(
insn
)
)
insn
=
prev_active_insn
(
insn
)
;
if
(
insn
&&
CALL_P
(
insn
)
)
output_asm_insn
(
get_insn_template
(
CODE_FOR_nop
,
)
,
)
;
alpha_write_linkage
(
file
,
fnname
)
;
if
(
TARGET_ABI_OPEN_VMS
||
!
flag_inhibit_size_directive
)
{
fputs
(
"\t.end "
,
file
)
;
assemble_name
(
file
,
fnname
)
;
putc
(
'\n'
,
file
)
;
}
inside_function
=
FALSE
;
}
</s>

Output the rest of the textual info surrounding the epilogue .


<s> void sparc_flat_expand_prologue ( void ) { HOST_WIDE_INT size ; rtx_insn * insn ; sparc_leaf_function_p = optimize > 0 && crtl -> is_leaf ; size = sparc_compute_frame_size ( get_frame_size ( ) , sparc_leaf_function_p ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = size ; if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK ) { if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { if ( size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT ) sparc_emit_probe_stack_range ( STACK_CHECK_PROTECT , size - STACK_CHECK_PROTECT ) ; } else if ( size > 0 ) sparc_emit_probe_stack_range ( STACK_CHECK_PROTECT , size ) ; } if ( sparc_save_local_in_regs_p ) emit_save_or_restore_local_in_regs ( stack_pointer_rtx , SPARC_STACK_BIAS , SORR_SAVE ) ; if ( size == 0 ) ; else { rtx size_int_rtx , size_rtx ; size_rtx = size_int_rtx = GEN_INT ( - size ) ; if ( size <= 4096 ) insn = emit_insn ( gen_stack_pointer_inc ( size_int_rtx ) ) ; else if ( size <= 8192 && ! frame_pointer_needed ) { insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - 4096 ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( 4096 - size ) ) ) ; } else { size_rtx = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( size_rtx , size_int_rtx ) ; insn = emit_insn ( gen_stack_pointer_inc ( size_rtx ) ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_stack_pointer_inc ( size_int_rtx ) ) ; } RTX_FRAME_RELATED_P ( insn ) = 1 ; emit_insn ( gen_blockage ( ) ) ; if ( frame_pointer_needed ) { insn = emit_insn ( gen_rtx_SET ( hard_frame_pointer_rtx , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , size_rtx ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( hard_frame_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , size ) ) ) ; } if ( return_addr_reg_needed_p ( sparc_leaf_function_p ) ) { rtx o7 = gen_rtx_REG ( Pmode , INCOMING_RETURN_ADDR_REGNUM ) ; rtx i7 = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; insn = emit_move_insn ( i7 , o7 ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_REGISTER , gen_rtx_SET ( i7 , o7 ) ) ; emit_use ( i7 ) ; } } if ( frame_pointer_needed ) { sparc_frame_base_reg = hard_frame_pointer_rtx ; sparc_frame_base_offset = SPARC_STACK_BIAS ; } else { sparc_frame_base_reg = stack_pointer_rtx ; sparc_frame_base_offset = size + SPARC_STACK_BIAS ; } if ( sparc_n_global_fp_regs > 0 ) emit_save_or_restore_global_fp_regs ( sparc_frame_base_reg , sparc_frame_base_offset - sparc_apparent_frame_size , SORR_SAVE ) ; if ( crtl -> uses_pic_offset_table ) load_got_register ( ) ; sparc_prologue_data_valid_p = true ; } </s>

Expand the function prologue . The prologue is responsible for reserving storage for the frame , saving the call-saved registers and loading the GOT register if needed .


<s> static bool visium_frame_pointer_required ( void ) { if ( ! crtl -> is_leaf ) return true ; if ( ! crtl -> sp_is_unchanging ) return true ; if ( cfun -> has_nonlocal_label ) return true ; if ( visium_frame_needed ) return true ; return false ; } </s>

Return true if the current function must have and use a frame pointer .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < ScalarEvolutionWrapperPass > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> unsigned MipsFastISel :: fastEmitInst_rr ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , bool Op0IsKill , unsigned Op1 , bool Op1IsKill ) { if ( MachineInstOpcode == Mips :: MUL ) { unsigned ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , II . getNumDefs ( ) ) ; Op1 = constrainOperandRegClass ( II , Op1 , II . getNumDefs ( ) + 1 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 , getKillRegState ( Op0IsKill ) ) . addReg ( Op1 , getKillRegState ( Op1IsKill ) ) . addReg ( Mips :: HI0 , RegState :: ImplicitDefine | RegState :: Dead ) . addReg ( Mips :: LO0 , RegState :: ImplicitDefine | RegState :: Dead ) ; return ResultReg ; } return FastISel :: fastEmitInst_rr ( MachineInstOpcode , RC , Op0 , Op0IsKill , Op1 , Op1IsKill ) ; } </s>

Emit a MachineInstr with two register operands and a result register in the given register class .


<s> void ARMAsmBackend :: handleAssemblerFlag ( MCAssemblerFlag Flag ) { switch ( Flag ) { default : break ; case MCAF_Code16 : setIsThumb ( true ) ; break ; case MCAF_Code32 : setIsThumb ( false ) ; break ; } } </s>

Handle any target-specific assembler flags . By default , do nothing .


"EFLAGS are not live-out from a patchpoint."

Prior to adding the live-out mask to a stackmap or patchpoint instruction , provide the target the opportunity to adjust it ( mainly to remove pseudo-registers that should be ignored ) .


<s> static void ft32_compute_frame ( void ) { int stack_alignment = STACK_BOUNDARY / BITS_PER_UNIT ; int padding_locals ; int regno ; cfun -> machine -> local_vars_size = get_frame_size ( ) ; padding_locals = cfun -> machine -> local_vars_size % stack_alignment ; if ( padding_locals ) padding_locals = stack_alignment - padding_locals ; cfun -> machine -> local_vars_size += padding_locals ; cfun -> machine -> callee_saved_reg_size = 0 ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ( ! call_used_regs [ regno ] ) ) cfun -> machine -> callee_saved_reg_size += 4 ; cfun -> machine -> size_for_adjusting_sp = 0 + cfun -> machine -> local_vars_size + ( ACCUMULATE_OUTGOING_ARGS ? ( HOST_WIDE_INT ) crtl -> outgoing_args_size : 0 ) ; } </s>

Compute the size of the local area and the size to be adjusted by the * prologue and epilogue .


<s> static bool riscv_function_ok_for_sibcall ( tree decl ATTRIBUTE_UNUSED , tree exp ATTRIBUTE_UNUSED ) { if ( TARGET_SAVE_RESTORE ) return false ; if ( cfun -> machine -> naked_p ) return false ; return true ; } </s>


<s> const MCPhysReg * PPCRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const PPCSubtarget & Subtarget = MF -> getSubtarget < PPCSubtarget > ( ) ; if ( MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: AnyReg ) { if ( Subtarget . hasVSX ( ) ) return CSR_64_AllRegs_VSX_SaveList ; if ( Subtarget . hasAltivec ( ) ) return CSR_64_AllRegs_Altivec_SaveList ; return CSR_64_AllRegs_SaveList ; } if ( Subtarget . isDarwinABI ( ) ) return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_SaveList : CSR_Darwin64_SaveList ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_SaveList : CSR_Darwin32_SaveList ) ; bool SaveR2 = MF -> getRegInfo ( ) . isAllocatable ( PPC :: X2 ) ; return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? ( SaveR2 ? CSR_SVR464_R2_Altivec_SaveList : CSR_SVR464_Altivec_SaveList ) : ( SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList ) ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR432_Altivec_SaveList : CSR_SVR432_SaveList ) ; } </s>


<s> MCDisassembler :: DecodeStatus WebAssemblyDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t , raw_ostream & OS , raw_ostream & CS ) const { return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s> bool LoongArchRegisterInfo :: isConstantPhysReg ( MCRegister PhysReg ) const { return PhysReg == LoongArch :: R0 ; } </s>

Returns true if PhysReg is unallocatable and constant throughout the function .


<s> bool RISCVDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { bool ret = SelectionDAGISel :: runOnMachineFunction ( MF ) ; processFunctionAfterISel ( MF ) ; return ret ; } </s>

runOnMachineFunction - Emit the function body .


<s> EVT getSetCCResultType ( LLVMContext & Ctx , EVT VT ) const override { if ( VT . isVector ( ) ) return EVT :: getVectorVT ( Ctx , MVT :: i1 , VT . getVectorNumElements ( ) ) ; return MVT :: i1 ; } </s>

Return the value type to use for ISD : :SETCC .


<s> bool PPCFastISel :: isTypeLegal ( Type * Ty , MVT & VT ) { EVT Evt = TLI . getValueType ( Ty , true ) ; if ( Evt == MVT :: Other || ! Evt . isSimple ( ) ) return false ; VT = Evt . getSimpleVT ( ) ; return TLI . isTypeLegal ( VT ) ; } </s>


<s> uint64_t R600MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) { if ( HAS_NATIVE_OPERANDS ( MCII . get ( MI . getOpcode ( ) ) . TSFlags ) ) return MRI . getEncodingValue ( MO . getReg ( ) ) ; return getHWReg ( MO . getReg ( ) ) ; } if ( MO . isExpr ( ) ) { const unsigned offset = ( & MO == & MI . getOperand ( 0 ) ) ? 0 : 4 ; Fixups . push_back ( MCFixup :: create ( offset , MO . getExpr ( ) , FK_SecRel_4 , MI . getLoc ( ) ) ) ; return 0 ; } assert ( MO . isImm ( ) ) ; return MO . getImm ( ) ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> static bool arm_bfi_1_p ( rtx op0 , rtx op1 , rtx * sub0 , rtx * sub1 ) { unsigned HOST_WIDE_INT const1 ; unsigned HOST_WIDE_INT const2 = 0 ; if ( ! CONST_INT_P ( XEXP ( op0 , 1 ) ) ) return false ; const1 = UINTVAL ( XEXP ( op0 , 1 ) ) ; if ( ! CONST_INT_P ( XEXP ( op1 , 1 ) ) || ~ UINTVAL ( XEXP ( op1 , 1 ) ) != const1 ) return false ; if ( GET_CODE ( XEXP ( op0 , 0 ) ) == ASHIFT && CONST_INT_P ( XEXP ( XEXP ( op0 , 0 ) , 1 ) ) ) { const2 = UINTVAL ( XEXP ( XEXP ( op0 , 0 ) , 1 ) ) ; * sub0 = XEXP ( XEXP ( op0 , 0 ) , 0 ) ; } else * sub0 = XEXP ( op0 , 0 ) ; if ( const2 >= GET_MODE_BITSIZE ( GET_MODE ( op0 ) ) ) return false ; * sub1 = XEXP ( op1 , 0 ) ; return exact_log2 ( const1 + ( HOST_WIDE_INT_1U << const2 ) ) >= 0 ; } </s>


<s> bool MipsRegisterInfo :: isConstantPhysReg ( MCRegister PhysReg ) const { return PhysReg == Mips :: ZERO || PhysReg == Mips :: ZERO_64 || PhysReg == Mips :: CNULL ; } </s>

Mips Mips Mips::ZERO Mips::ZERO_64 Mips::CNULL


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineModuleInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> rtx aarch64_return_addr ( int count , rtx frame ATTRIBUTE_UNUSED ) { if ( count != 0 ) return const0_rtx ; return aarch64_return_addr_rtx ( ) ; } </s>

Implement RETURN_ADDR_RTX . We do not support moving back to a previous frame .


<s> static void rl78_alloc_physical_registers_cmp ( rtx_insn * insn ) { int tmp_id ; rtx saved_op1 ; rtx_insn * prev = prev_nonnote_nondebug_insn ( insn ) ; rtx_insn * first ; OP ( 1 ) = transcode_memory_rtx ( OP ( 1 ) , DE , insn ) ; OP ( 2 ) = transcode_memory_rtx ( OP ( 2 ) , HL , insn ) ; MAYBE_OK ( insn ) ; if ( REG_P ( OP ( 1 ) ) && REGNO ( OP ( 1 ) ) != AX_REG && GET_MODE ( OP ( 1 ) ) == HImode && MEM_P ( OP ( 2 ) ) ) { rtx cmp = XEXP ( SET_SRC ( PATTERN ( insn ) ) , 0 ) ; OP ( 2 ) = move_to_acc ( 2 , insn ) ; switch ( GET_CODE ( cmp ) ) { case EQ : case NE : break ; case LTU : cmp = gen_rtx_GTU ( HImode , OP ( 2 ) , OP ( 1 ) ) ; break ; case GTU : cmp = gen_rtx_LTU ( HImode , OP ( 2 ) , OP ( 1 ) ) ; break ; case LEU : cmp = gen_rtx_GEU ( HImode , OP ( 2 ) , OP ( 1 ) ) ; break ; case GEU : cmp = gen_rtx_LEU ( HImode , OP ( 2 ) , OP ( 1 ) ) ; break ; case LT : case GT : case LE : case GE : debug_rtx ( insn ) ; default : gcc_unreachable ( ) ; } if ( GET_CODE ( cmp ) == EQ || GET_CODE ( cmp ) == NE ) PATTERN ( insn ) = gen_cbranchhi4_real ( cmp , OP ( 2 ) , OP ( 1 ) , OP ( 3 ) ) ; else PATTERN ( insn ) = gen_cbranchhi4_real_inverted ( cmp , OP ( 2 ) , OP ( 1 ) , OP ( 3 ) ) ; MUST_BE_OK ( insn ) ; } if ( rtx_equal_p ( OP ( 1 ) , OP ( 2 ) ) ) { OP ( 1 ) = OP ( 2 ) = BC ; MUST_BE_OK ( insn ) ; } tmp_id = get_max_insn_count ( ) ; saved_op1 = OP ( 1 ) ; OP ( 1 ) = move_to_acc ( 1 , insn ) ; MAYBE_OK ( insn ) ; if ( tmp_id == get_max_insn_count ( ) ) force_into_acc ( saved_op1 , insn ) ; if ( prev ) first = next_nonnote_nondebug_insn ( prev ) ; else for ( first = insn ; prev_nonnote_nondebug_insn ( first ) ; first = prev_nonnote_nondebug_insn ( first ) ) ; OP ( 2 ) = move_to_hl ( 2 , first ) ; MUST_BE_OK ( insn ) ; } </s>


<s> BitVector ARMBaseRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; const ARMFrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( ARM :: SP ) ; Reserved . set ( ARM :: PC ) ; Reserved . set ( ARM :: FPSCR ) ; Reserved . set ( ARM :: APSR_NZCV ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( getFramePointerReg ( STI ) ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( BasePtr ) ; if ( STI . isR9Reserved ( ) ) Reserved . set ( ARM :: R9 ) ; if ( ! STI . hasVFP3 ( ) || STI . hasD16 ( ) ) { assert ( ARM :: D31 == ARM :: D16 + 15 ) ; for ( unsigned i = 0 ; i != 16 ; ++ i ) Reserved . set ( ARM :: D16 + i ) ; } const TargetRegisterClass * RC = & ARM :: GPRPairRegClass ; for ( TargetRegisterClass :: iterator I = RC -> begin ( ) , E = RC -> end ( ) ; I != E ; ++ I ) for ( MCSubRegIterator SI ( * I , this ) ; SI . isValid ( ) ; ++ SI ) if ( Reserved . test ( * SI ) ) Reserved . set ( * I ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
bool
X86FrameLowering
::
canUseAsPrologue
(
const
MachineBasicBlock
&
MBB
)
const
{
assert
(
MBB
.
getParent
(
)
&&
"Block is not attached to a function!"
)
;
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
return
!
TRI
->
needsStackRealignment
(
MF
)
||
!
MBB
.
isLiveIn
(
X86
::
EFLAGS
)
;
}
</s>

Check whether or not the given MBB can be used as a prologue for the target .


<s> const char * WDC65816TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case WDCISD :: RET_FLAG : return "WDCSD::RET_FLAG" ; case WDCISD :: Wrapper : return "WDCISD::Wrapper" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static void msp430_evaluate_arg ( cumulative_args_t cap , machine_mode mode , const_tree type ATTRIBUTE_UNUSED , bool named ) { CUMULATIVE_ARGS * ca = get_cumulative_args ( cap ) ; int nregs = GET_MODE_SIZE ( mode ) ; int i ; ca -> reg_count = 0 ; ca -> mem_count = 0 ; if ( ! named ) return ; if ( mode == PSImode ) nregs = 1 ; else nregs = ( nregs + 1 ) / 2 ; if ( ca -> special_p ) { ca -> start_reg = 8 ; ca -> reg_count = 4 ; return ; } switch ( nregs ) { case 1 : for ( i = 0 ; i < 4 ; i ++ ) if ( ! ca -> reg_used [ i ] ) { ca -> reg_count = 1 ; ca -> start_reg = CA_FIRST_REG + i ; return ; } break ; case 2 : for ( i = 0 ; i < 3 ; i ++ ) if ( ! ca -> reg_used [ i ] && ! ca -> reg_used [ i + 1 ] ) { ca -> reg_count = 2 ; ca -> start_reg = CA_FIRST_REG + i ; return ; } if ( ! ca -> reg_used [ 3 ] && ca -> can_split ) { ca -> reg_count = 1 ; ca -> mem_count = 2 ; ca -> start_reg = CA_FIRST_REG + 3 ; return ; } break ; case 3 : case 4 : ca -> can_split = 0 ; if ( ! ca -> reg_used [ 0 ] && ! ca -> reg_used [ 1 ] && ! ca -> reg_used [ 2 ] && ! ca -> reg_used [ 3 ] ) { ca -> reg_count = 4 ; ca -> start_reg = CA_FIRST_REG ; return ; } break ; } } </s>

Helper function for argument passing ; this function is the common code that determines where an argument will be passed .


<s> static bool aarch64_option_valid_attribute_p ( tree fndecl , tree , tree args , int ) { struct cl_target_option cur_target ; bool ret ; tree old_optimize ; tree new_target , new_optimize ; tree existing_target = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( ! existing_target && args == current_target_pragma ) { DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = target_option_current_node ; return true ; } tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; old_optimize = build_optimization_node ( & global_options ) ; func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( func_optimize && func_optimize != old_optimize ) cl_optimization_restore ( & global_options , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_save ( & cur_target , & global_options ) ; if ( existing_target ) { struct cl_target_option * existing_options = TREE_TARGET_OPTION ( existing_target ) ; if ( existing_options ) cl_target_option_restore ( & global_options , existing_options ) ; } else cl_target_option_restore ( & global_options , TREE_TARGET_OPTION ( target_option_current_node ) ) ; ret = aarch64_process_target_attr ( args ) ; if ( ret ) { aarch64_override_options_internal ( & global_options ) ; if ( TARGET_SIMD ) { tree saved_current_target_pragma = current_target_pragma ; current_target_pragma = NULL ; aarch64_init_simd_builtins ( ) ; current_target_pragma = saved_current_target_pragma ; } new_target = build_target_option_node ( & global_options ) ; } else new_target = NULL ; new_optimize = build_optimization_node ( & global_options ) ; if ( fndecl && ret ) { DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = new_target ; if ( old_optimize != new_optimize ) DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) = new_optimize ; } cl_target_option_restore ( & global_options , & cur_target ) ; if ( old_optimize != new_optimize ) cl_optimization_restore ( & global_options , TREE_OPTIMIZATION ( old_optimize ) ) ; return ret ; } </s>

Implement TARGET_OPTION_VALID_ATTRIBUTE_P . This is used to process attribute ( ( target ( `` ... '' ) ) ) .


<s> bool areJTsAllowed ( const Function * Fn ) const override { return ! Fn -> getFnAttribute ( "no-jump-tables" ) . getValueAsBool ( ) ; } </s>

Returns true if lowering to a jump table is allowed .


<s> SDNode * PPCDAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; const Module * M = MF -> getFunction ( ) -> getParent ( ) ; DebugLoc dl ; if ( PPCLowering -> getPointerTy ( ) == MVT :: i32 ) { if ( PPCSubTarget -> isTargetELF ( ) ) { GlobalBaseReg = PPC :: R30 ; if ( M -> getPICLevel ( ) == PICLevel :: Small ) { BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MoveGOTtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; MF -> getInfo < PPCFunctionInfo > ( ) -> setUsesPICBase ( true ) ; } else { BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; unsigned TempReg = RegInfo -> createVirtualRegister ( & PPC :: GPRCRegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: UpdateGBR ) ) . addReg ( GlobalBaseReg ) . addReg ( TempReg , RegState :: Define ) . addReg ( GlobalBaseReg ) ; MF -> getInfo < PPCFunctionInfo > ( ) -> setUsesPICBase ( true ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: GPRC_NOR0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: G8RC_NOX0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR8 ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR8 ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , PPCLowering -> getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

PowerPC PPC PPC MVT::i32 PPC PPC::R30 PPC::MoveGOTtoLR PPC::MFLR PPC PPC::MovePCtoLR PPC::MFLR PPC::GPRCRegClass PPC::UpdateGBR PPC PPC::GPRC_NOR0RegClass PPC::MovePCtoLR PPC::MFLR PPC::G8RC_NOX0RegClass PPC::MovePCtoLR8 PPC::MFLR8 PPC


<s> bool MSP430InstrInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) BuildMI ( MBB , MI , DL , get ( MSP430 :: POP16r ) , CSI [ i ] . getReg ( ) ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static bool sparc_cannot_force_const_mem ( rtx x ) { switch ( GET_CODE ( x ) ) { case CONST_INT : case CONST_DOUBLE : case CONST_VECTOR : return false ; case LABEL_REF : return flag_pic != 0 ; case SYMBOL_REF : if ( SYMBOL_REF_TLS_MODEL ( x ) ) return true ; else return flag_pic != 0 ; case CONST : return sparc_cannot_force_const_mem ( XEXP ( x , 0 ) ) ; case PLUS : case MINUS : return sparc_cannot_force_const_mem ( XEXP ( x , 0 ) ) || sparc_cannot_force_const_mem ( XEXP ( x , 1 ) ) ; case UNSPEC : return true ; default : gcc_unreachable ( ) ; } } </s>

Determine if it 's legal to put X into the constant pool . This is not possible if X contains the address of a symbol that is not constant ( TLS ) or not known at final link time ( PIC ) .


<s> void MipsSEFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; const MipsSEInstrInfo & TII = * static_cast < const MipsSEInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; const MipsRegisterInfo & RegInfo = * static_cast < const MipsRegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; unsigned SP = STI . isABI_N64 ( ) ? Mips :: SP_64 : Mips :: SP ; unsigned FP = STI . isABI_N64 ( ) ? Mips :: FP_64 : Mips :: FP ; unsigned ZERO = STI . isABI_N64 ( ) ? Mips :: ZERO_64 : Mips :: ZERO ; unsigned ADDu = Mips :: ADDu ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( ADDu ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( MipsFI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = 0 ; J < 4 ; ++ J ) { TII . loadRegFromStackSlot ( MBB , I , ehDataReg ( J ) , MipsFI -> getEhDataRegFI ( J ) , RC , & RegInfo ) ; } } uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize , MBB , MBBI ) ; } </s>


<s> bool ARMTargetLowering :: shouldExpandAtomicStoreInIR ( StoreInst * SI ) const { unsigned Size = SI -> getValueOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return ( Size == 64 ) && ! Subtarget -> isMClass ( ) ; } </s>

Returns how the given ( atomic ) store should be expanded by the IR-level AtomicExpand pass into .


<s> void ARMBaseInstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , unsigned SubIdx , const MachineInstr & Orig , const TargetRegisterInfo & TRI ) const { unsigned Opcode = Orig . getOpcode ( ) ; switch ( Opcode ) { default : { MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( & Orig ) ; MI -> substituteRegister ( Orig . getOperand ( 0 ) . getReg ( ) , DestReg , SubIdx , TRI ) ; MBB . insert ( I , MI ) ; break ; } case ARM :: tLDRpci_pic : case ARM :: t2LDRpci_pic : { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CPI = Orig . getOperand ( 1 ) . getIndex ( ) ; unsigned PCLabelId = duplicateCPV ( MF , CPI ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , Orig . getDebugLoc ( ) , get ( Opcode ) , DestReg ) . addConstantPoolIndex ( CPI ) . addImm ( PCLabelId ) ; MIB -> setMemRefs ( Orig . memoperands_begin ( ) , Orig . memoperands_end ( ) ) ; break ; } } } </s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == nullptr ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( const MCConstantExpr * ConstExpr = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( static_cast < int32_t > ( ConstExpr -> getValue ( ) ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s> TargetPassConfig * PPCTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new PPCPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> virtual void releaseBottomNode ( SUnit * SU ) { } </s>

Currently only scheduling top-down , so this method is empty .


<s> void SITargetLowering :: finalizeLowering ( MachineFunction & MF ) const { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; SIMachineFunctionInfo * Info = MF . getInfo < SIMachineFunctionInfo > ( ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const SIRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; if ( Info -> isEntryFunction ( ) ) { reservePrivateMemoryRegs ( getTargetMachine ( ) , MF , * TRI , * Info ) ; } assert ( ! TRI -> isSubRegister ( Info -> getScratchRSrcReg ( ) , Info -> getStackPtrOffsetReg ( ) ) ) ; if ( Info -> getStackPtrOffsetReg ( ) != AMDGPU :: SP_REG ) MRI . replaceRegWith ( AMDGPU :: SP_REG , Info -> getStackPtrOffsetReg ( ) ) ; if ( Info -> getScratchRSrcReg ( ) != AMDGPU :: PRIVATE_RSRC_REG ) MRI . replaceRegWith ( AMDGPU :: PRIVATE_RSRC_REG , Info -> getScratchRSrcReg ( ) ) ; if ( Info -> getFrameOffsetReg ( ) != AMDGPU :: FP_REG ) MRI . replaceRegWith ( AMDGPU :: FP_REG , Info -> getFrameOffsetReg ( ) ) ; Info -> limitOccupancy ( MF ) ; if ( ST . isWave32 ( ) && ! MF . empty ( ) ) { const SIInstrInfo * TII = ST . getInstrInfo ( ) ; DebugLoc DL ; MachineBasicBlock & MBB = MF . front ( ) ; MachineBasicBlock :: iterator I = MBB . getFirstNonDebugInstr ( ) ; BuildMI ( MBB , I , DL , TII -> get ( TargetOpcode :: IMPLICIT_DEF ) , AMDGPU :: VCC_HI ) ; for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { TII -> fixImplicitOperands ( MI ) ; } } } TargetLoweringBase :: finalizeLowering ( MF ) ; if ( VGPRReserveforSGPRSpill && ! Info -> VGPRReservedForSGPRSpill && ! Info -> isEntryFunction ( ) && MF . getFrameInfo ( ) . hasStackObjects ( ) ) Info -> reserveVGPRforSGPRSpills ( MF ) ; } </s>

Execute target specific actions to finalize target lowering .


<s>
const
MCFixupKindInfo
&
Cpu0AsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
Cpu0
::
NumTargetFixupKinds
]
=
{
{
"fixup_Cpu0_32"
,
0
,
32
,
0
}
,
{
"fixup_Cpu0_HI16"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_LO16"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_GPREL16"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_GOT"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_PC16"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_Cpu0_PC24"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_Cpu0_CALL16"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_TLSGD"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_GOTTP"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_TP_HI"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_TP_LO"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_TLSLDM"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_DTP_HI"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_DTP_LO"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_GOT_HI16"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_GOT_LO16"
,
0
,
16
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s>
unsigned
XtensaInstrInfo
::
insertBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
TBB
,
MachineBasicBlock
*
FBB
,
ArrayRef
<
MachineOperand
>
Cond
,
const
DebugLoc
&
DL
,
int
*
BytesAdded
)
const
{
llvm_unreachable
(
"Unimplemented operand"
)
;
}
</s>

Insert branch code into the end of the specified MachineBasicBlock .


<s> bool MOSFrameLowering :: enableShrinkWrapping ( const MachineFunction & MF ) const { return ! isISR ( MF ) ; } </s>

Returns true if the target will correctly handle shrink wrapping .


<s> bool rx_reg_dead_or_unused_after_insn ( const rtx_insn * i , int regno ) { return find_regno_note ( i , REG_DEAD , regno ) != NULL || find_regno_note ( i , REG_UNUSED , regno ) != NULL ; } </s>

Given an insn and a reg number , tell whether the reg dies or is unused after the insn .


<s> static bool bfin_vector_mode_supported_p ( machine_mode mode ) { return mode == V2HImode ; } </s>

Implements target hook vector_mode_supported_p .


<s> DecodeStatus AArch64Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CS ) const { CommentStream = & CS ; Size = 0 ; if ( Bytes . size ( ) < 4 ) return Fail ; Size = 4 ; uint32_t Insn = ( Bytes [ 3 ] << 24 ) | ( Bytes [ 2 ] << 16 ) | ( Bytes [ 1 ] << 8 ) | ( Bytes [ 0 ] << 0 ) ; return decodeInstruction ( DecoderTable32 , MI , Insn , Address , this , STI ) ; } </s>

Returns the disassembly of a single instruction .


<s> static bool spu_ref_may_alias_errno ( ao_ref * ref ) { tree base = ao_ref_base ( ref ) ; if ( TREE_CODE ( base ) == VAR_DECL && ! TREE_STATIC ( base ) && DECL_EXTERNAL ( base ) && TREE_CODE ( TREE_TYPE ( base ) ) == RECORD_TYPE && strcmp ( IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( base ) ) , "_impure_data" ) == 0 && ref -> offset == 0 ) return true ; return default_ref_may_alias_errno ( ref ) ; } </s>


<s> bool AArch64InstrInfo :: getMemOperandWithOffset ( const MachineInstr & LdSt , const MachineOperand * & BaseOp , int64_t & Offset , const TargetRegisterInfo * TRI ) const { if ( ! LdSt . mayLoadOrStore ( ) ) return false ; unsigned Width ; return getMemOperandWithOffsetWidth ( LdSt , BaseOp , Offset , Width , TRI ) ; } </s>

Get the base operand and byte offset of an instruction that reads/writes memory .


<s> static void mcore_mark_dllexport ( tree decl ) { const char * oldname ; char * newname ; rtx rtlname ; tree idp ; rtlname = XEXP ( DECL_RTL ( decl ) , 0 ) ; if ( GET_CODE ( rtlname ) == MEM ) rtlname = XEXP ( rtlname , 0 ) ; gcc_assert ( GET_CODE ( rtlname ) == SYMBOL_REF ) ; oldname = XSTR ( rtlname , 0 ) ; if ( mcore_dllexport_name_p ( oldname ) ) return ; newname = alloca ( strlen ( oldname ) + 4 ) ; sprintf ( newname , "@e.%s" , oldname ) ; idp = get_identifier ( newname ) ; XEXP ( DECL_RTL ( decl ) , 0 ) = gen_rtx_SYMBOL_REF ( Pmode , IDENTIFIER_POINTER ( idp ) ) ; } </s>


<s> bool Mips16InstrInfo :: isCopyInstr ( const MachineInstr & MI , const MachineOperand * & Src , const MachineOperand * & Dest ) const { if ( MI . isMoveReg ( ) ) { Dest = & MI . getOperand ( 0 ) ; Src = & MI . getOperand ( 1 ) ; return true ; } return false ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


"********** Abstract Member Accesses **********\n"

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static void nds32_emit_stack_push_multiple ( unsigned Rb , unsigned Re , bool save_fp_p , bool save_gp_p , bool save_lp_p , bool vaarg_p ) { unsigned regno ; int extra_count ; int num_use_regs ; int par_index ; int offset ; rtx reg ; rtx mem ; rtx push_rtx ; rtx adjust_sp_rtx ; rtx parallel_insn ; rtx dwarf ; extra_count = 0 ; if ( save_fp_p ) extra_count ++ ; if ( save_gp_p ) extra_count ++ ; if ( save_lp_p ) extra_count ++ ; if ( Rb == SP_REGNUM && Re == SP_REGNUM ) num_use_regs = extra_count ; else num_use_regs = Re - Rb + 1 + extra_count ; parallel_insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_use_regs + 1 ) ) ; par_index = 0 ; offset = - ( num_use_regs * 4 ) ; for ( regno = Rb ; regno <= Re ; regno ++ ) { if ( regno == SP_REGNUM ) break ; reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( mem , reg ) ; XVECEXP ( parallel_insn , 0 , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; } if ( save_fp_p ) { reg = gen_rtx_REG ( SImode , FP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( mem , reg ) ; XVECEXP ( parallel_insn , 0 , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; } if ( save_gp_p ) { reg = gen_rtx_REG ( SImode , GP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( mem , reg ) ; XVECEXP ( parallel_insn , 0 , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; } if ( save_lp_p ) { reg = gen_rtx_REG ( SImode , LP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( mem , reg ) ; XVECEXP ( parallel_insn , 0 , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; } offset = - ( num_use_regs * 4 ) ; adjust_sp_rtx = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; XVECEXP ( parallel_insn , 0 , par_index ) = adjust_sp_rtx ; RTX_FRAME_RELATED_P ( adjust_sp_rtx ) = 1 ; parallel_insn = emit_insn ( parallel_insn ) ; RTX_FRAME_RELATED_P ( parallel_insn ) = 1 ; if ( vaarg_p ) { dwarf = alloc_reg_note ( REG_CFA_ADJUST_CFA , copy_rtx ( adjust_sp_rtx ) , NULL_RTX ) ; REG_NOTES ( parallel_insn ) = dwarf ; } } </s>

Function to create a parallel rtx pattern which presents stack push multiple behavior . The overall concept are : `` push registers to memory '' , `` adjust stack pointer '' .


<s> void GCNPassConfig :: addPreEmitPass ( ) { addPass ( createSIMemoryLegalizerPass ( ) ) ; addPass ( createSIInsertWaitcntsPass ( ) ) ; if ( TM -> getOptLevel ( ) > CodeGenOpt :: None ) addPass ( createSIShrinkInstructionsPass ( ) ) ; addPass ( createSIModeRegisterPass ( ) ) ; if ( getOptLevel ( ) > CodeGenOpt :: None ) addPass ( & SIInsertHardClausesID ) ; addPass ( & SILateBranchLoweringPassID ) ; if ( getOptLevel ( ) > CodeGenOpt :: None ) addPass ( & SIPreEmitPeepholeID ) ; addPass ( & PostRAHazardRecognizerID ) ; addPass ( & BranchRelaxationPassID ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void SIScheduleBlock :: addUnit ( SUnit * SU ) { NodeNum2Index [ SU -> NodeNum ] = SUnits . size ( ) ; SUnits . push_back ( SU ) ; } </s>


<s> MachineBasicBlock :: iterator PPCFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && I -> getOpcode ( ) == PPC :: ADJCALLSTACKUP ) { if ( int CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { bool is64Bit = Subtarget . isPPC64 ( ) ; CalleeAmt *= - 1 ; unsigned StackReg = is64Bit ? PPC :: X1 : PPC :: R1 ; unsigned TmpReg = is64Bit ? PPC :: X0 : PPC :: R0 ; unsigned ADDIInstr = is64Bit ? PPC :: ADDI8 : PPC :: ADDI ; unsigned ADDInstr = is64Bit ? PPC :: ADD8 : PPC :: ADD4 ; unsigned LISInstr = is64Bit ? PPC :: LIS8 : PPC :: LIS ; unsigned ORIInstr = is64Bit ? PPC :: ORI8 : PPC :: ORI ; MachineInstr * MI = I ; const DebugLoc & dl = MI -> getDebugLoc ( ) ; if ( isInt < 16 > ( CalleeAmt ) ) { BuildMI ( MBB , I , dl , TII . get ( ADDIInstr ) , StackReg ) . addReg ( StackReg , RegState :: Kill ) . addImm ( CalleeAmt ) ; } else { MachineBasicBlock :: iterator MBBI = I ; BuildMI ( MBB , MBBI , dl , TII . get ( LISInstr ) , TmpReg ) . addImm ( CalleeAmt >> 16 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ORIInstr ) , TmpReg ) . addReg ( TmpReg , RegState :: Kill ) . addImm ( CalleeAmt & 0xFFFF ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ADDInstr ) , StackReg ) . addReg ( StackReg , RegState :: Kill ) . addReg ( TmpReg ) ; } } } return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> void HexagonTargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { const SDLoc & dl ( N ) ; switch ( N -> getOpcode ( ) ) { case ISD :: SRL : case ISD :: SRA : case ISD :: SHL : return ; case ISD :: BITCAST : if ( N -> getValueType ( 0 ) == MVT :: i8 ) { SDValue P = getNode ( Hexagon :: C2_tfrpr , dl , MVT :: i32 , N -> getOperand ( 0 ) , DAG ) ; Results . push_back ( P ) ; } break ; } } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> bool MCS51AsmParser :: emit ( MCInst & Inst , SMLoc const & Loc , MCStreamer & Out ) const { Inst . setLoc ( Loc ) ; Out . emitInstruction ( Inst , STI ) ; return false ; } </s>

Output the remark via the diagnostic handler and to the optimization record file .


<s> MachineBasicBlock :: iterator X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { bool reserveCallFrame = hasReservedCallFrame ( MF ) ; unsigned Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? TII . getFrameSize ( * I ) : 0 ; uint64_t InternalAmt = ( isDestroy || Amount ) ? TII . getFrameAdjustment ( * I ) : 0 ; I = MBB . erase ( I ) ; auto InsertPos = skipDebugInstructionsForward ( I , MBB . end ( ) ) ; if ( ! reserveCallFrame ) { unsigned StackAlign = getStackAlignment ( ) ; Amount = alignTo ( Amount , StackAlign ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const Function & F = MF . getFunction ( ) ; bool WindowsCFI = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool DwarfCFI = ! WindowsCFI && ( MMI . hasDebugInfo ( ) || F . needsUnwindTableEntry ( ) ) ; bool HasDwarfEHHandlers = ! WindowsCFI && ! MF . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < X86MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == 0 ) return I ; Amount -= InternalAmt ; if ( isDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ; int64_t StackAdjustment = isDestroy ? Amount : - Amount ; if ( StackAdjustment ) { StackAdjustment += mergeSPUpdates ( MBB , InsertPos , true ) ; StackAdjustment += mergeSPUpdates ( MBB , InsertPos , false ) ; if ( StackAdjustment ) { if ( ! ( F . hasMinSize ( ) && adjustStackWithPops ( MBB , InsertPos , DL , StackAdjustment ) ) ) BuildStackAdjustment ( MBB , InsertPos , DL , StackAdjustment , false ) ; } } if ( DwarfCFI && ! hasFP ( MF ) ) { int64_t CfaAdjustment = - StackAdjustment ; if ( CfaAdjustment ) { BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , CfaAdjustment ) ) ; } } return I ; } if ( isDestroy && InternalAmt ) { MachineBasicBlock :: iterator CI = I ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( CI != B && ! std :: prev ( CI ) -> isCall ( ) ) -- CI ; BuildStackAdjustment ( MBB , CI , DL , - InternalAmt , false ) ; } return I ; } </s>


<s> bool OR1KFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || TRI -> needsStackRealignment ( MF ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> bool ARMPassConfig :: addPreEmitPass ( ) { if ( getARMSubtarget ( ) . isThumb2 ( ) ) { if ( ! getARMSubtarget ( ) . prefers32BitThumb ( ) ) addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( & UnpackMachineBundlesID ) ; } addPass ( createARMOptimizeBarriersPass ( ) ) ; if ( getARMSubtarget ( ) . useConstIslands ( ) ) addPass ( createARMConstantIslandPass ( ) ) ; if ( getARMSubtarget ( ) . isTargetNaCl ( ) ) { addPass ( createARMNaClRewritePass ( ) ) ; } return true ; } </s>


<s> static void aarch64_test_loading_full_dump ( ) { rtl_dump_test t ( SELFTEST_LOCATION , locate_file ( "aarch64/times-two.rtl" ) ) ; ASSERT_STREQ ( "times_two" , IDENTIFIER_POINTER ( DECL_NAME ( cfun -> decl ) ) ) ; rtx_insn * insn_1 = get_insn_by_uid ( 1 ) ; ASSERT_EQ ( NOTE , GET_CODE ( insn_1 ) ) ; rtx_insn * insn_15 = get_insn_by_uid ( 15 ) ; ASSERT_EQ ( INSN , GET_CODE ( insn_15 ) ) ; ASSERT_EQ ( USE , GET_CODE ( PATTERN ( insn_15 ) ) ) ; ASSERT_EQ ( REG , GET_CODE ( crtl -> return_rtx ) ) ; ASSERT_EQ ( 0 , REGNO ( crtl -> return_rtx ) ) ; ASSERT_EQ ( SImode , GET_MODE ( crtl -> return_rtx ) ) ; } </s>

Selftest for the RTL loader . Verify that the RTL loader copes with a dump from print_rtx_function . This is essentially just a test that class function_reader can handle a real dump , but it also verifies that lookup_reg_by_dump_name correctly handles hard regs . The presence of hard reg names in the dump means that the test is target-specific , hence it is in this file .


<s> bool X86PassConfig :: addPostRegAlloc ( ) { addPass ( createX86FloatingPointStackifierPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> const char * X86TargetLowering :: LowerXConstraint ( EVT ConstraintVT ) const { if ( ConstraintVT . isFloatingPoint ( ) ) { if ( Subtarget -> hasXMMInt ( ) ) return "Y" ; if ( Subtarget -> hasXMM ( ) ) return "x" ; } return TargetLowering :: LowerXConstraint ( ConstraintVT ) ; } </s>

Try to replace an X constraint , which matches anything , with another that has more specific requirements based on the type of the corresponding operand .


<s> SMLoc getEndLoc ( ) const override { return End ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> static bool riscv_cannot_copy_insn_p ( rtx_insn * insn ) { return recog_memoized ( insn ) >= 0 && get_attr_cannot_copy ( insn ) ; } </s>


<s> void AMDGPUPassConfig :: addPreEmitPass ( ) { const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) { addPass ( createAMDGPUCFGStructurizerPass ( ) , false ) ; addPass ( createR600ExpandSpecialInstrsPass ( * TM ) , false ) ; addPass ( & FinalizeMachineBundlesID , false ) ; addPass ( createR600Packetizer ( * TM ) , false ) ; addPass ( createR600ControlFlowFinalizer ( * TM ) , false ) ; } else { addPass ( createSILowerControlFlowPass ( * TM ) , false ) ; } } </s>


<s> const char * MipsTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case MipsISD :: JmpLink : return "MipsISD::JmpLink" ; case MipsISD :: TailCall : return "MipsISD::TailCall" ; case MipsISD :: Hi : return "MipsISD::Hi" ; case MipsISD :: Lo : return "MipsISD::Lo" ; case MipsISD :: GPRel : return "MipsISD::GPRel" ; case MipsISD :: ThreadPointer : return "MipsISD::ThreadPointer" ; case MipsISD :: Ret : return "MipsISD::Ret" ; case MipsISD :: FPBrcond : return "MipsISD::FPBrcond" ; case MipsISD :: FPCmp : return "MipsISD::FPCmp" ; case MipsISD :: CMovFP_T : return "MipsISD::CMovFP_T" ; case MipsISD :: CMovFP_F : return "MipsISD::CMovFP_F" ; case MipsISD :: FPRound : return "MipsISD::FPRound" ; case MipsISD :: MAdd : return "MipsISD::MAdd" ; case MipsISD :: MAddu : return "MipsISD::MAddu" ; case MipsISD :: MSub : return "MipsISD::MSub" ; case MipsISD :: MSubu : return "MipsISD::MSubu" ; case MipsISD :: DivRem : return "MipsISD::DivRem" ; case MipsISD :: DivRemU : return "MipsISD::DivRemU" ; case MipsISD :: BuildPairF64 : return "MipsISD::BuildPairF64" ; case MipsISD :: ExtractElementF64 : return "MipsISD::ExtractElementF64" ; case MipsISD :: Wrapper : return "MipsISD::Wrapper" ; case MipsISD :: DynAlloc : return "MipsISD::DynAlloc" ; case MipsISD :: Sync : return "MipsISD::Sync" ; case MipsISD :: Ext : return "MipsISD::Ext" ; case MipsISD :: Ins : return "MipsISD::Ins" ; case MipsISD :: LWL : return "MipsISD::LWL" ; case MipsISD :: LWR : return "MipsISD::LWR" ; case MipsISD :: SWL : return "MipsISD::SWL" ; case MipsISD :: SWR : return "MipsISD::SWR" ; case MipsISD :: LDL : return "MipsISD::LDL" ; case MipsISD :: LDR : return "MipsISD::LDR" ; case MipsISD :: SDL : return "MipsISD::SDL" ; case MipsISD :: SDR : return "MipsISD::SDR" ; case MipsISD :: EXTP : return "MipsISD::EXTP" ; case MipsISD :: EXTPDP : return "MipsISD::EXTPDP" ; case MipsISD :: EXTR_S_H : return "MipsISD::EXTR_S_H" ; case MipsISD :: EXTR_W : return "MipsISD::EXTR_W" ; case MipsISD :: EXTR_R_W : return "MipsISD::EXTR_R_W" ; case MipsISD :: EXTR_RS_W : return "MipsISD::EXTR_RS_W" ; case MipsISD :: SHILO : return "MipsISD::SHILO" ; case MipsISD :: MTHLIP : return "MipsISD::MTHLIP" ; case MipsISD :: MULT : return "MipsISD::MULT" ; case MipsISD :: MULTU : return "MipsISD::MULTU" ; case MipsISD :: MADD_DSP : return "MipsISD::MADD_DSPDSP" ; case MipsISD :: MADDU_DSP : return "MipsISD::MADDU_DSP" ; case MipsISD :: MSUB_DSP : return "MipsISD::MSUB_DSP" ; case MipsISD :: MSUBU_DSP : return "MipsISD::MSUBU_DSP" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific

Mips Mips MipsISD::JmpLink "MipsISD::JmpLink" MipsISD::TailCall "MipsISD::TailCall" MipsISD::Hi "MipsISD::Hi" MipsISD::Lo "MipsISD::Lo" MipsISD::GPRel "MipsISD::GPRel" MipsISD::ThreadPointer "MipsISD::ThreadPointer" MipsISD::Ret "MipsISD::Ret" MipsISD::FPBrcond "MipsISD::FPBrcond" MipsISD::FPCmp "MipsISD::FPCmp" MipsISD::CMovFP_T "MipsISD::CMovFP_T" MipsISD::CMovFP_F "MipsISD::CMovFP_F" MipsISD::FPRound "MipsISD::FPRound" MipsISD::MAdd "MipsISD::MAdd" MipsISD::MAddu "MipsISD::MAddu" MipsISD::MSub "MipsISD::MSub" MipsISD::MSubu "MipsISD::MSubu" MipsISD::DivRem "MipsISD::DivRem" MipsISD::DivRemU "MipsISD::DivRemU" MipsISD::BuildPairF64 "MipsISD::BuildPairF64" MipsISD::ExtractElementF64 "MipsISD::ExtractElementF64" MipsISD::Wrapper "MipsISD::Wrapper" MipsISD::DynAlloc "MipsISD::DynAlloc" MipsISD::Sync "MipsISD::Sync" MipsISD::Ext "MipsISD::Ext" MipsISD::Ins "MipsISD::Ins" MipsISD::LWL "MipsISD::LWL" MipsISD::LWR "MipsISD::LWR" MipsISD::SWL "MipsISD::SWL" MipsISD::SWR "MipsISD::SWR" MipsISD::LDL "MipsISD::LDL" MipsISD::LDR "MipsISD::LDR" MipsISD::SDL "MipsISD::SDL" MipsISD::SDR "MipsISD::SDR" MipsISD::EXTP "MipsISD::EXTP" MipsISD::EXTPDP "MipsISD::EXTPDP" MipsISD::EXTR_S_H "MipsISD::EXTR_S_H" MipsISD::EXTR_W "MipsISD::EXTR_W" MipsISD::EXTR_R_W "MipsISD::EXTR_R_W" MipsISD::EXTR_RS_W "MipsISD::EXTR_RS_W" MipsISD::SHILO "MipsISD::SHILO" MipsISD::MTHLIP "MipsISD::MTHLIP" MipsISD::MULT "MipsISD::MULT" MipsISD::MULTU "MipsISD::MULTU" MipsISD::MADD_DSP "MipsISD::MADD_DSPDSP" MipsISD::MADDU_DSP "MipsISD::MADDU_DSP" MipsISD::MSUB_DSP "MipsISD::MSUB_DSP" MipsISD::MSUBU_DSP "MipsISD::MSUBU_DSP"


<s> void Cpu0TargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; this -> TM = & static_cast < const Cpu0TargetMachine & > ( TM ) ; } </s>

This method must be called before any actual lowering is done .


<s> void TeakInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & OS ) { printInstruction ( MI , Address , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static unsigned int ix86_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( GENERAL_REGNO_P ( regno ) ) { if ( mode == XFmode ) return TARGET_64BIT ? 2 : 3 ; if ( mode == XCmode ) return TARGET_64BIT ? 4 : 6 ; return CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ; } if ( COMPLEX_MODE_P ( mode ) ) return 2 ; if ( mode == V64SFmode || mode == V64SImode ) return 4 ; return 1 ; } </s>

Implement TARGET_HARD_REGNO_NREGS . This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers . Actually there are no two word move instructions for consecutive registers . And only registers 0-3 may have mov byte instructions applied to them .


<s> void AMDGPURegisterBankInfo :: applyMappingImpl ( const OperandsMapper & OpdMapper ) const { MachineInstr & MI = OpdMapper . getMI ( ) ; unsigned Opc = MI . getOpcode ( ) ; MachineRegisterInfo & MRI = OpdMapper . getMRI ( ) ; switch ( Opc ) { case AMDGPU :: G_AND : case AMDGPU :: G_OR : case AMDGPU :: G_XOR : { unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ; if ( MRI . getType ( DstReg ) . getSizeInBits ( ) != 64 ) break ; SmallVector < unsigned , 2 > DefRegs ( OpdMapper . getVRegs ( 0 ) ) ; SmallVector < unsigned , 2 > Src0Regs ( OpdMapper . getVRegs ( 1 ) ) ; SmallVector < unsigned , 2 > Src1Regs ( OpdMapper . getVRegs ( 2 ) ) ; if ( DefRegs . empty ( ) ) { assert ( Src0Regs . empty ( ) && Src1Regs . empty ( ) ) ; break ; } assert ( DefRegs . size ( ) == 2 ) ; assert ( Src0Regs . size ( ) == Src1Regs . size ( ) && ( Src0Regs . empty ( ) || Src0Regs . size ( ) == 2 ) ) ; MachineIRBuilder B ( MI ) ; if ( Src0Regs . empty ( ) ) split64BitValueForMapping ( B , Src0Regs , MI . getOperand ( 1 ) . getReg ( ) ) ; if ( Src1Regs . empty ( ) ) split64BitValueForMapping ( B , Src1Regs , MI . getOperand ( 2 ) . getReg ( ) ) ; B . buildInstr ( Opc ) . addDef ( DefRegs [ 0 ] ) . addUse ( Src0Regs [ 0 ] ) . addUse ( Src1Regs [ 0 ] ) ; B . buildInstr ( Opc ) . addDef ( DefRegs [ 1 ] ) . addUse ( Src0Regs [ 1 ] ) . addUse ( Src1Regs [ 1 ] ) ; MRI . setRegBank ( DstReg , getRegBank ( AMDGPU :: VGPRRegBankID ) ) ; MI . eraseFromParent ( ) ; return ; } default : break ; } return applyDefaultMapping ( OpdMapper ) ; } </s>


<s> static section * pa_elf_select_rtx_section ( machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ) { if ( function_label_operand ( x , VOIDmode ) ) { tree decl = SYMBOL_REF_DECL ( x ) ; if ( ! decl || ( DECL_P ( decl ) && DECL_COMDAT_GROUP ( decl ) ) ) return get_named_section ( NULL , ".data.rel.ro.local" , 1 ) ; } return default_elf_select_rtx_section ( mode , x , align ) ; } </s>

Implement pa_elf_select_rtx_section . If X is a function label operand and the function is in a COMDAT group , place the plabel reference in the .data.rel.ro.local section . The linker ignores references to symbols in discarded sections from this section .


<s> virtual MVT getScalarShiftAmountTy ( EVT LHSTy ) const LLVM_OVERRIDE { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> static bool arc_return_in_memory ( tree type , tree fntype ATTRIBUTE_UNUSED ) { if ( AGGREGATE_TYPE_P ( type ) ) return true ; else { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; return ( size == - 1 || size > 8 ) ; } } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


<s> bool VLIWResourceModel :: isResourceAvailable ( SUnit * SU ) { if ( ! SU || ! SU -> getInstr ( ) ) return false ; switch ( SU -> getInstr ( ) -> getOpcode ( ) ) { default : if ( ! ResourcesModel -> canReserveResources ( * SU -> getInstr ( ) ) ) return false ; case TargetOpcode :: EXTRACT_SUBREG : case TargetOpcode :: INSERT_SUBREG : case TargetOpcode :: SUBREG_TO_REG : case TargetOpcode :: REG_SEQUENCE : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: COPY : case TargetOpcode :: INLINEASM : break ; } MachineFunction & MF = * SU -> getInstr ( ) -> getParent ( ) -> getParent ( ) ; auto & QII = * MF . getSubtarget < HexagonSubtarget > ( ) . getInstrInfo ( ) ; for ( unsigned i = 0 , e = Packet . size ( ) ; i != e ; ++ i ) { if ( Packet [ i ] -> Succs . size ( ) == 0 ) continue ; if ( QII . mayBeCurLoad ( Packet [ i ] -> getInstr ( ) ) ) continue ; for ( SUnit :: const_succ_iterator I = Packet [ i ] -> Succs . begin ( ) , E = Packet [ i ] -> Succs . end ( ) ; I != E ; ++ I ) { if ( I -> isCtrl ( ) ) continue ; if ( I -> getSUnit ( ) == SU ) return false ; } } return true ; } </s>

Check if scheduling of this SU is possible in the current packet .


"MIa must load from or modify a memory location"

"MIb must load from or modify a memory location"

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> virtual const OR1KRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> const char * ARMTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case ARMISD :: Wrapper : return "ARMISD::Wrapper" ; case ARMISD :: WrapperJT : return "ARMISD::WrapperJT" ; case ARMISD :: CALL : return "ARMISD::CALL" ; case ARMISD :: CALL_PRED : return "ARMISD::CALL_PRED" ; case ARMISD :: CALL_NOLINK : return "ARMISD::CALL_NOLINK" ; case ARMISD :: tCALL : return "ARMISD::tCALL" ; case ARMISD :: BRCOND : return "ARMISD::BRCOND" ; case ARMISD :: BR_JT : return "ARMISD::BR_JT" ; case ARMISD :: RET_FLAG : return "ARMISD::RET_FLAG" ; case ARMISD :: PIC_ADD : return "ARMISD::PIC_ADD" ; case ARMISD :: CMP : return "ARMISD::CMP" ; case ARMISD :: CMPNZ : return "ARMISD::CMPNZ" ; case ARMISD :: CMPFP : return "ARMISD::CMPFP" ; case ARMISD :: CMPFPw0 : return "ARMISD::CMPFPw0" ; case ARMISD :: FMSTAT : return "ARMISD::FMSTAT" ; case ARMISD :: CMOV : return "ARMISD::CMOV" ; case ARMISD :: CNEG : return "ARMISD::CNEG" ; case ARMISD :: FTOSI : return "ARMISD::FTOSI" ; case ARMISD :: FTOUI : return "ARMISD::FTOUI" ; case ARMISD :: SITOF : return "ARMISD::SITOF" ; case ARMISD :: UITOF : return "ARMISD::UITOF" ; case ARMISD :: SRL_FLAG : return "ARMISD::SRL_FLAG" ; case ARMISD :: SRA_FLAG : return "ARMISD::SRA_FLAG" ; case ARMISD :: RRX : return "ARMISD::RRX" ; case ARMISD :: FMRRD : return "ARMISD::FMRRD" ; case ARMISD :: FMDRR : return "ARMISD::FMDRR" ; case ARMISD :: THREAD_POINTER : return "ARMISD::THREAD_POINTER" ; } } </s>

ARM ARM 0 ARMISD::Wrapper "ARMISD::Wrapper" ARMISD::WrapperJT "ARMISD::WrapperJT" ARMISD::CALL "ARMISD::CALL" ARMISD::CALL_PRED "ARMISD::CALL_PRED" ARMISD::CALL_NOLINK "ARMISD::CALL_NOLINK" ARMISD::tCALL "ARMISD::tCALL" ARMISD::BRCOND "ARMISD::BRCOND" ARMISD::BR_JT "ARMISD::BR_JT" ARMISD::RET_FLAG "ARMISD::RET_FLAG" ARMISD::PIC_ADD "ARMISD::PIC_ADD" ARMISD::CMP "ARMISD::CMP" ARMISD::CMPNZ "ARMISD::CMPNZ" ARMISD::CMPFP "ARMISD::CMPFP" ARMISD::CMPFPw0 "ARMISD::CMPFPw0" ARMISD::FMSTAT "ARMISD::FMSTAT" ARMISD::CMOV "ARMISD::CMOV" ARMISD::CNEG "ARMISD::CNEG" ARMISD::FTOSI "ARMISD::FTOSI" ARMISD::FTOUI "ARMISD::FTOUI" ARMISD::SITOF "ARMISD::SITOF" ARMISD::UITOF "ARMISD::UITOF" ARMISD::SRL_FLAG "ARMISD::SRL_FLAG" ARMISD::SRA_FLAG "ARMISD::SRA_FLAG" ARMISD::RRX "ARMISD::RRX" ARMISD::FMRRD "ARMISD::FMRRD" ARMISD::FMDRR "ARMISD::FMDRR" ARMISD::THREAD_POINTER "ARMISD::THREAD_POINTER"


<s> TargetIRAnalysis SystemZTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( Function & F ) { return TargetTransformInfo ( SystemZTTIImpl ( this , F ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


<s> static std :: unique_ptr < AMDGPUOperand > CreateReg ( unsigned RegNo , SMLoc S , SMLoc E , const MCRegisterInfo * TRI , const MCSubtargetInfo * STI , bool ForceVOP3 ) { auto Op = llvm :: make_unique < AMDGPUOperand > ( Register ) ; Op -> Reg . RegNo = RegNo ; Op -> Reg . TRI = TRI ; Op -> Reg . STI = STI ; Op -> Reg . Modifiers = - 1 ; Op -> Reg . IsForcedVOP3 = ForceVOP3 ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> void ix86_emit_i387_log1p ( rtx op0 , rtx op1 ) { rtx_code_label * label1 = gen_label_rtx ( ) ; rtx_code_label * label2 = gen_label_rtx ( ) ; rtx tmp = gen_reg_rtx ( XFmode ) ; rtx res = gen_reg_rtx ( XFmode ) ; rtx cst , cstln2 , cst1 ; rtx_insn * insn ; do_pending_stack_adjust ( ) ; cst = const_double_from_real_value ( REAL_VALUE_ATOF ( "0.29289321881345247561810596348408353" , XFmode ) , XFmode ) ; cstln2 = force_reg ( XFmode , standard_80387_constant_rtx ( 4 ) ) ; emit_insn ( gen_absxf2 ( tmp , op1 ) ) ; cst = force_reg ( XFmode , cst ) ; ix86_expand_branch ( GE , tmp , cst , label1 ) ; predict_jump ( REG_BR_PROB_BASE * 10 / 100 ) ; insn = get_last_insn ( ) ; JUMP_LABEL ( insn ) = label1 ; emit_insn ( gen_fyl2xp1xf3_i387 ( res , op1 , cstln2 ) ) ; emit_jump ( label2 ) ; emit_label ( label1 ) ; LABEL_NUSES ( label1 ) = 1 ; cst1 = force_reg ( XFmode , CONST1_RTX ( XFmode ) ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_PLUS ( XFmode , op1 , cst1 ) ) ) ; emit_insn ( gen_fyl2xxf3_i387 ( res , tmp , cstln2 ) ) ; emit_label ( label2 ) ; LABEL_NUSES ( label2 ) = 1 ; emit_move_insn ( op0 , res ) ; } </s>

Output code to perform a log1p XFmode calculation .


<s> static bool isMicroMips ( const MCSubtargetInfo * STI ) { return STI -> getFeatureBits ( ) [ Mips :: FeatureMicroMips ] ; } </s>

Check whether a given symbol has been flagged with MICROMIPS flag .


<s> void AArch64TargetStreamer :: emitInst ( uint32_t Inst ) { } </s>

Callback used to implement the .inst directive .


<s> static int stackSlotSize ( ) { return 4 ; } </s>


<s> bool ARMBaseInstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( MI . isDebugInstr ( ) ) return false ; if ( MI . isTerminator ( ) || MI . isPosition ( ) ) return true ; MachineBasicBlock :: const_iterator I = MI ; while ( ++ I != MBB -> end ( ) && I -> isDebugInstr ( ) ) ; if ( I != MBB -> end ( ) && I -> getOpcode ( ) == ARM :: t2IT ) return true ; if ( ! MI . isCall ( ) && MI . definesRegister ( ARM :: SP ) ) return true ; return false ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> const SICInstrInfo * SICInstrInfo :: create ( SICSubtarget & STI ) { return new SICInstrInfo ( STI ) ; } </s>


<s> const AArch64Subtarget * AArch64TargetMachine :: getSubtargetImpl ( const Function & F ) const { AttributeSet FnAttrs = F . getAttributes ( ) ; Attribute CPUAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "target-cpu" ) ; Attribute FSAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < AArch64Subtarget > ( TargetTriple , CPU , FS , * this , isLittle ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
const
MCFixupKindInfo
&
M88kMCAsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
static
const
MCFixupKindInfo
Infos
[
M88k
::
NumTargetFixupKinds
]
=
{
{
"FK_88K_NONE"
,
0
,
32
,
0
}
,
{
"FK_88K_DISP16"
,
16
,
16
,
0
}
,
{
"FK_88K_DISP26"
,
6
,
26
,
0
}
,
{
"FK_88K_HI"
,
16
,
16
,
0
}
,
{
"FK_88K_LO"
,
16
,
16
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> static bool arc_lra_p ( void ) { return ! TARGET_NO_LRA ; } </s>

Return true if we use LRA instead of reload pass .


<s> bool X86InstrInfo :: isReallyTriviallyReMaterializable ( const MachineInstr * MI , AliasAnalysis * AA ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case X86 :: MOV8rm : case X86 :: MOV16rm : case X86 :: MOV32rm : case X86 :: MOV64rm : case X86 :: LD_Fp64m : case X86 :: MOVSSrm : case X86 :: MOVSDrm : case X86 :: MOVAPSrm : case X86 :: MOVUPSrm : case X86 :: MOVAPDrm : case X86 :: MOVDQArm : case X86 :: VMOVSSrm : case X86 :: VMOVSDrm : case X86 :: VMOVAPSrm : case X86 :: VMOVUPSrm : case X86 :: VMOVAPDrm : case X86 :: VMOVDQArm : case X86 :: VMOVAPSYrm : case X86 :: VMOVUPSYrm : case X86 :: VMOVAPDYrm : case X86 :: VMOVDQAYrm : case X86 :: MMX_MOVD64rm : case X86 :: MMX_MOVQ64rm : case X86 :: FsVMOVAPSrm : case X86 :: FsVMOVAPDrm : case X86 :: FsMOVAPSrm : case X86 :: FsMOVAPDrm : { if ( MI -> getOperand ( 1 ) . isReg ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 3 ) . isReg ( ) && MI -> getOperand ( 3 ) . getReg ( ) == 0 && MI -> isInvariantLoad ( AA ) ) { unsigned BaseReg = MI -> getOperand ( 1 ) . getReg ( ) ; if ( BaseReg == 0 || BaseReg == X86 :: RIP ) return true ; if ( ! ReMatPICStubLoad && MI -> getOperand ( 4 ) . isGlobal ( ) ) return false ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; return regIsPICBase ( BaseReg , MRI ) ; } return false ; } case X86 :: LEA32r : case X86 :: LEA64r : { if ( MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 3 ) . isReg ( ) && MI -> getOperand ( 3 ) . getReg ( ) == 0 && ! MI -> getOperand ( 4 ) . isReg ( ) ) { if ( ! MI -> getOperand ( 1 ) . isReg ( ) ) return true ; unsigned BaseReg = MI -> getOperand ( 1 ) . getReg ( ) ; if ( BaseReg == 0 ) return true ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; return regIsPICBase ( BaseReg , MRI ) ; } return false ; } } return true ; } </s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> virtual const MandarinRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>