<s>
SDValue
AAPTargetLowering
::
LowerCall
(
TargetLowering
::
CallLoweringInfo
&
CLI
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SelectionDAG
&
DAG
=
CLI
.
DAG
;
SDLoc
&
DL
=
CLI
.
DL
;
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
=
CLI
.
Outs
;
SmallVectorImpl
<
SDValue
>
&
OutVals
=
CLI
.
OutVals
;
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
=
CLI
.
Ins
;
SDValue
Chain
=
CLI
.
Chain
;
SDValue
Callee
=
CLI
.
Callee
;
bool
&
isTailCall
=
CLI
.
IsTailCall
;
CallingConv
::
ID
CallConv
=
CLI
.
CallConv
;
bool
isVarArg
=
CLI
.
IsVarArg
;
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
OutVals
,
Ins
,
DL
,
DAG
,
InVals
)
;
}
}
</s>

AAP
AAP
ISD::OutputArg
ISD::InputArg
"Unsupported calling convention"


<s> void P2MCInstLower :: lowerInstruction ( const MachineInstr & MI , MCInst & OutMI ) const { OutMI . setOpcode ( MI . getOpcode ( ) ) ; OutMI . setFlags ( MI . getDesc ( ) . TSFlags ) ; for ( unsigned i = 0 , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; MCOperand MCOp = lowerOperand ( MO ) ; if ( MCOp . isValid ( ) ) OutMI . addOperand ( MCOp ) ; } } </s>


<s> const MCRegisterInfo * getRegInfo ( ) const { return RegInfo . get ( ) ; } </s>

getRegInfo - Return information about the registers currently in use .


<s> EVT PPCTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { if ( Subtarget . isPPC64 ( ) ) { return MVT :: i64 ; } else { return MVT :: i32 ; } } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> bool HexagonTargetLowering :: isFMAFasterThanFMulAndFAdd ( EVT VT ) const { return isOperationLegalOrCustom ( ISD :: FMA , VT ) ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> int PatmosInstrInfo :: getOperandLatency ( const InstrItineraryData * ItinData , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * UseMI , unsigned UseIdx ) const { if ( UseMI -> isInlineAsm ( ) ) { return getDefOperandLatency ( ItinData , DefMI , DefIdx ) ; } return TargetInstrInfo :: getOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ; } </s>

Compute and return the use operand latency of a given pair of def and use .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> SDNode * SparcDAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI -> getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


Returns the number of bytes offset between FROM_REG and TO_REG for the current function . As a side effect it fills in the current_frame_info structure , if the data is available .


<s> static reg_class_t s390_preferred_reload_class ( rtx op , reg_class_t rclass ) { switch ( GET_CODE ( op ) ) { case CONST_VECTOR : case CONST_DOUBLE : case CONST_INT : case CONST_WIDE_INT : if ( reg_class_subset_p ( GENERAL_REGS , rclass ) && legitimate_reload_constant_p ( op ) ) return GENERAL_REGS ; else if ( reg_class_subset_p ( ADDR_REGS , rclass ) && legitimate_reload_constant_p ( op ) ) return ADDR_REGS ; else if ( reg_class_subset_p ( FP_REGS , rclass ) && legitimate_reload_fp_constant_p ( op ) ) return FP_REGS ; else if ( reg_class_subset_p ( VEC_REGS , rclass ) && legitimate_reload_vector_constant_p ( op ) ) return VEC_REGS ; return NO_REGS ; case CONST : if ( TARGET_CPU_ZARCH && GET_CODE ( XEXP ( op , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( op , 0 ) , 0 ) ) == SYMBOL_REF && GET_CODE ( XEXP ( XEXP ( op , 0 ) , 1 ) ) == CONST_INT ) { if ( flag_pic && reg_class_subset_p ( ADDR_REGS , rclass ) ) return ADDR_REGS ; else return NO_REGS ; } case LABEL_REF : case SYMBOL_REF : if ( ! legitimate_reload_constant_p ( op ) ) return NO_REGS ; case PLUS : if ( reg_class_subset_p ( ADDR_REGS , rclass ) ) return ADDR_REGS ; else return NO_REGS ; default : break ; } return rclass ; } </s>

Given an rtx OP being reloaded into a reg required to be in class CLASS , return the class of reg to actually use .


<s> unsigned int nds32_data_alignment ( tree data , unsigned int basic_align ) { if ( ( basic_align < BITS_PER_WORD ) && ( TREE_CODE ( data ) == ARRAY_TYPE || TREE_CODE ( data ) == UNION_TYPE || TREE_CODE ( data ) == RECORD_TYPE ) ) return BITS_PER_WORD ; else return basic_align ; } </s>


<s> bool LanaiTargetObjectFile :: isConstantInSmallSection ( const DataLayout & DL , const Constant * CN ) const { return isInSmallSection ( DL . getTypeAllocSize ( CN -> getType ( ) ) ) ; } </s>

Return true if this constant should be placed into small data section .


<s> static void nds32_emit_load_store ( rtx reg , rtx mem , enum machine_mode mode , int offset , bool load_p ) { rtx new_mem ; new_mem = adjust_address ( mem , mode , offset ) ; if ( load_p ) emit_move_insn ( reg , new_mem ) ; else emit_move_insn ( new_mem , reg ) ; } </s>


<s> const SPIRVRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void AMDGPUPassConfig :: addCodeGenPrepare ( ) { if ( TM -> getTargetTriple ( ) . getArch ( ) == Triple :: amdgcn && EnableLowerKernelArguments ) addPass ( createAMDGPULowerKernelArgumentsPass ( ) ) ; TargetPassConfig :: addCodeGenPrepare ( ) ; if ( EnableLoadStoreVectorizer ) addPass ( createLoadStoreVectorizerPass ( ) ) ; } </s>

Add pass to prepare the LLVM IR for code generation .


<s> StringRef getPassName ( ) const override { return COREV_HWLP_BLOCKS_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> inline type_suffix_index find_type_suffix ( type_class_index tclass , unsigned int element_bits ) { for ( unsigned int i = 0 ; i < NUM_TYPE_SUFFIXES ; ++ i ) if ( type_suffixes [ i ] . tclass == tclass && type_suffixes [ i ] . element_bits == element_bits ) return type_suffix_index ( i ) ; gcc_unreachable ( ) ; } </s>

Return the type suffix associated with ELEMENT_BITS-bit elements of type class TCLASS .


<s> static void replace_swapped_aligned_store ( swap_web_entry * insn_entry , rtx_insn * store_insn ) { unsigned uid = INSN_UID ( store_insn ) ; gcc_assert ( insn_entry [ uid ] . is_swap && insn_entry [ uid ] . is_store ) ; rtx body = PATTERN ( store_insn ) ; rtx dest_address = XEXP ( SET_DEST ( body ) , 0 ) ; rtx swap_reg = XEXP ( SET_SRC ( body ) , 0 ) ; gcc_assert ( REG_P ( dest_address ) || rs6000_sum_of_two_registers_p ( dest_address ) ) ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( store_insn ) ; df_ref use ; rtx_insn * swap_insn = NULL ; unsigned uid2 = 0 ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( ! rtx_equal_p ( DF_REF_REG ( use ) , swap_reg ) ) continue ; gcc_assert ( def_link && def_link -> ref && ! def_link -> next && ! DF_REF_IS_ARTIFICIAL ( def_link -> ref ) ) ; swap_insn = DF_REF_INSN ( def_link -> ref ) ; uid2 = INSN_UID ( swap_insn ) ; gcc_assert ( insn_entry [ uid2 ] . is_swap && ! insn_entry [ uid2 ] . is_load && ! insn_entry [ uid2 ] . is_store ) ; break ; } gcc_assert ( swap_insn ) ; rtx set = single_set ( store_insn ) ; gcc_assert ( set ) ; rtx dest_exp = SET_DEST ( set ) ; rtx src_exp = XEXP ( SET_SRC ( body ) , 0 ) ; enum machine_mode mode = GET_MODE ( dest_exp ) ; gcc_assert ( MEM_P ( dest_exp ) ) ; gcc_assert ( MEM_ALIGN ( dest_exp ) >= 128 ) ; rtx stvx ; stvx = rs6000_gen_stvx ( mode , dest_exp , src_exp ) ; rtx_insn * new_insn = emit_insn_before ( stvx , store_insn ) ; rtx new_body = PATTERN ( new_insn ) ; gcc_assert ( ( GET_CODE ( new_body ) == SET ) && ( GET_CODE ( SET_DEST ( new_body ) ) == MEM ) ) ; set_block_for_insn ( new_insn , BLOCK_FOR_INSN ( store_insn ) ) ; df_insn_rescan ( new_insn ) ; df_insn_delete ( store_insn ) ; remove_insn ( store_insn ) ; store_insn -> set_deleted ( ) ; uid2 = INSN_UID ( swap_insn ) ; mark_swaps_for_removal ( insn_entry , uid2 ) ; replace_swap_with_copy ( insn_entry , uid2 ) ; } </s>

Given that STORE_INSN represents an aligned store-with-swap of a swapped value , replace the store with an aligned store ( without swap ) and replace the swap with a copy insn .


<s> static tree ia64_gimplify_va_arg ( tree valist , tree type , tree * pre_p , tree * post_p ) { if ( pass_by_reference ( NULL , TYPE_MODE ( type ) , type , false ) ) { tree ptrtype = build_pointer_type ( type ) ; tree addr = std_gimplify_va_arg_expr ( valist , ptrtype , pre_p , post_p ) ; return build_va_arg_indirect_ref ( addr ) ; } if ( ( TREE_CODE ( type ) == REAL_TYPE || TREE_CODE ( type ) == INTEGER_TYPE ) ? int_size_in_bytes ( type ) > 8 : TYPE_ALIGN ( type ) > 8 * BITS_PER_UNIT ) { tree t = build ( PLUS_EXPR , TREE_TYPE ( valist ) , valist , build_int_cst ( NULL_TREE , 2 * UNITS_PER_WORD - 1 ) ) ; t = build ( BIT_AND_EXPR , TREE_TYPE ( t ) , t , build_int_cst ( NULL_TREE , - 2 * UNITS_PER_WORD ) ) ; t = build ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist , t ) ; gimplify_and_add ( t , pre_p ) ; } return std_gimplify_va_arg_expr ( valist , type , pre_p , post_p ) ; } </s>


<s> bool isKZeroMasked ( ) const { return ( Attributes & X86FMA3KZeroMasked ) != 0 ; } </s>

Returns true iff the group of FMA opcodes holds k-zero-masked opcodes .


<s> enum aarch64_symbol_type aarch64_classify_symbolic_expression ( rtx x ) { rtx offset ; split_const ( x , & x , & offset ) ; return aarch64_classify_symbol ( x , offset ) ; } </s>

Classify the base of symbolic expression X , given that X appears in context CONTEXT .


<s> static inline CvtDirection getTombstoneKey ( ) { return { T_UNDEF , 0 ; } </s>

Difference in tombstone is that the Optional is meaningful .


<s> static uint32_t getFastMathFlags ( const MachineInstr & I ) { uint32_t flags = FPFastMathMode :: None ; if ( I . getFlag ( MachineInstr :: MIFlag :: FmNoNans ) ) flags |= FPFastMathMode :: NotNaN ; if ( I . getFlag ( MachineInstr :: MIFlag :: FmNoInfs ) ) flags |= FPFastMathMode :: NotInf ; if ( I . getFlag ( MachineInstr :: MIFlag :: FmNsz ) ) flags |= FPFastMathMode :: NSZ ; if ( I . getFlag ( MachineInstr :: MIFlag :: FmArcp ) ) flags |= FPFastMathMode :: AllowRecip ; if ( I . getFlag ( MachineInstr :: MIFlag :: FmReassoc ) ) flags |= FPFastMathMode :: Fast ; return flags ; } </s>

Get the flags to be applied to created floating point ops .


<s> BitVector RISCVRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const RISCVFrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; const auto * RVFI = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; for ( size_t Reg = 0 ; Reg < getNumRegs ( ) ; Reg ++ ) { if ( MF . getSubtarget < RISCVSubtarget > ( ) . isRegisterReservedByUser ( Reg ) ) markSuperRegs ( Reserved , Reg ) ; } markSuperRegs ( Reserved , RISCV :: X0 ) ; markSuperRegs ( Reserved , RISCV :: X2 ) ; markSuperRegs ( Reserved , RISCV :: X3 ) ; markSuperRegs ( Reserved , RISCV :: X4 ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , RISCV :: X8 ) ; if ( TFI -> hasBP ( MF ) ) markSuperRegs ( Reserved , RISCVABI :: getBPReg ( ) ) ; markSuperRegs ( Reserved , RISCV :: VL ) ; markSuperRegs ( Reserved , RISCV :: VTYPE ) ; markSuperRegs ( Reserved , RISCV :: VXSAT ) ; markSuperRegs ( Reserved , RISCV :: VXRM ) ; for ( unsigned n = 0 ; n != 8 ; ++ n ) { if ( RVFI -> getUsedSSR ( ) & ( 1 << n ) ) markSuperRegs ( Reserved , RISCV :: F0_D + n ) ; } assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static inline bool bpf_address_base_p ( rtx x , bool strict ) { return ( GET_CODE ( x ) == REG && ( REGNO ( x ) < 11 || ( ! strict && REGNO ( x ) >= FIRST_PSEUDO_REGISTER ) ) ) ; } </s>

Return ` true ' if the given RTX X is a valid base for an indirect memory access . STRICT has the same meaning than in bpf_legitimate_address_p .


<s> int s390_agen_dep_p ( rtx_insn * dep_insn , rtx_insn * insn ) { rtx dep_rtx = PATTERN ( dep_insn ) ; int i ; if ( GET_CODE ( dep_rtx ) == SET && addr_generation_dependency_p ( dep_rtx , insn ) ) return 1 ; else if ( GET_CODE ( dep_rtx ) == PARALLEL ) { for ( i = 0 ; i < XVECLEN ( dep_rtx , 0 ) ; i ++ ) { if ( addr_generation_dependency_p ( XVECEXP ( dep_rtx , 0 , i ) , insn ) ) return 1 ; } } return 0 ; } </s>

Return 1 , if dep_insn sets register used in insn in the agen unit .


<s> Value * AArch64TargetLowering :: emitStoreConditional ( IRBuilder < > & Builder , Value * Val , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == 128 ) { Intrinsic :: ID Int = IsRelease ? Intrinsic :: aarch64_stlxp : Intrinsic :: aarch64_stxp ; Function * Stxr = Intrinsic :: getDeclaration ( M , Int ) ; Type * Int64Ty = Type :: getInt64Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int64Ty , "lo" ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , 64 ) , Int64Ty , "hi" ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall3 ( Stxr , Lo , Hi , Addr ) ; } Intrinsic :: ID Int = IsRelease ? Intrinsic :: aarch64_stlxr : Intrinsic :: aarch64_stxr ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Stxr = Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateCall2 ( Stxr , Builder . CreateZExtOrBitCast ( Val , Stxr -> getFunctionType ( ) -> getParamType ( 0 ) ) , Addr ) ; } </s>

Perform a store-conditional operation to Addr .


"Basic block without predecessors do not emit labels, unsupported."

Targets can override this to emit stuff at the start of a basic block .


<s> rtx alpha_tablejump_addr_vec ( rtx insn ) { rtx tmp ; tmp = JUMP_LABEL ( insn ) ; if ( ! tmp ) return NULL_RTX ; tmp = NEXT_INSN ( tmp ) ; if ( ! tmp ) return NULL_RTX ; if ( GET_CODE ( tmp ) == JUMP_INSN && GET_CODE ( PATTERN ( tmp ) ) == ADDR_DIFF_VEC ) return PATTERN ( tmp ) ; return NULL_RTX ; } </s>

Return the ADDR_VEC associated with a tablejump insn .


<s>
void
Comet2DAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"### Select\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> bool ARM64RegisterInfo :: requiresFrameIndexScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> void SparcRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const SparcSubtarget & Subtarget = MF . getSubtarget < SparcSubtarget > ( ) ; const SparcFrameLowering * TFI = getFrameLowering ( MF ) ; unsigned FrameReg ; int Offset ; Offset = TFI -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) ; Offset += MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ; if ( ! Subtarget . isV9 ( ) || ! Subtarget . hasHardQuad ( ) ) { if ( MI . getOpcode ( ) == SP :: STQFri ) { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; unsigned SrcReg = MI . getOperand ( 2 ) . getReg ( ) ; unsigned SrcEvenReg = getSubReg ( SrcReg , SP :: sub_even64 ) ; unsigned SrcOddReg = getSubReg ( SrcReg , SP :: sub_odd64 ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( SP :: STDFri ) ) . addReg ( FrameReg ) . addImm ( 0 ) . addReg ( SrcEvenReg ) ; replaceFI ( MF , II , * StMI , dl , 0 , Offset , FrameReg ) ; MI . setDesc ( TII . get ( SP :: STDFri ) ) ; MI . getOperand ( 2 ) . setReg ( SrcOddReg ) ; Offset += 8 ; } else if ( MI . getOpcode ( ) == SP :: LDQFri ) { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; unsigned DestReg = MI . getOperand ( 0 ) . getReg ( ) ; unsigned DestEvenReg = getSubReg ( DestReg , SP :: sub_even64 ) ; unsigned DestOddReg = getSubReg ( DestReg , SP :: sub_odd64 ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( SP :: LDDFri ) , DestEvenReg ) . addReg ( FrameReg ) . addImm ( 0 ) ; replaceFI ( MF , II , * StMI , dl , 1 , Offset , FrameReg ) ; MI . setDesc ( TII . get ( SP :: LDDFri ) ) ; MI . getOperand ( 0 ) . setReg ( DestOddReg ) ; Offset += 8 ; } } replaceFI ( MF , II , MI , dl , FIOperandNum , Offset , FrameReg ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> void PPCVSXSwapRemoval :: initialize ( MachineFunction & MFParm ) { MF = & MFParm ; MRI = & MF -> getRegInfo ( ) ; TII = static_cast < const PPCInstrInfo * > ( MF -> getSubtarget ( ) . getInstrInfo ( ) ) ; const int InitialVectorSize ( 256 ) ; SwapVector . clear ( ) ; SwapVector . reserve ( InitialVectorSize ) ; EC = new EquivalenceClasses < int > ; } </s>

Initialize the strategy after building the DAG for a new region .


<s>
void
F2003fMCAsmStreamer
::
EmitInstruction
(
const
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
,
bool
PrintSchedInfo
)
{
MCStreamer
::
EmitInstruction
(
Inst
,
STI
)
;
if
(
ShowInst
)
{
if
(
PrintSchedInfo
)
GetCommentOS
(
)
<<
"\n"
;
Inst
.
dump_pretty
(
GetCommentOS
(
)
,
InstPrinter
.
get
(
)
,
"\n "
)
;
GetCommentOS
(
)
<<
"\n"
;
}
std
::
string
Buffer
;
{
raw_string_ostream
TempStream
(
Buffer
)
;
InstPrinter
->
printInst
(
&
Inst
,
TempStream
,
""
,
STI
)
;
}
OS
<<
Buffer
.
substr
(
1
)
;
flushLabel
(
false
)
;
if
(
PrintSchedInfo
)
{
std
::
string
SI
=
STI
.
getSchedInfoStr
(
Inst
)
;
if
(
!
SI
.
empty
(
)
)
GetCommentOS
(
)
<<
SI
;
}
StringRef
Comments
=
CommentToEmit
;
if
(
Comments
.
size
(
)
&&
Comments
.
back
(
)
!=
'\n'
)
GetCommentOS
(
)
<<
"\n"
;
EmitEOL
(
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


Return an array that contains the bitmask target flag values and their names .

PowerPC PPC PPC "ppc-plt-or-stub" "ppc-pic" "ppc-nlp" "ppc-nlp-hidden"


<s> SDValue PPCTargetLowering :: getPICJumpTableRelocBase ( SDValue Table , SelectionDAG & DAG ) const { if ( ! Subtarget . isPPC64 ( ) ) return TargetLowering :: getPICJumpTableRelocBase ( Table , DAG ) ; switch ( getTargetMachine ( ) . getCodeModel ( ) ) { case CodeModel :: Default : case CodeModel :: Small : case CodeModel :: Medium : return TargetLowering :: getPICJumpTableRelocBase ( Table , DAG ) ; default : return DAG . getNode ( PPCISD :: GlobalBaseReg , SDLoc ( ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; } } </s>

Returns relocation base for the given PIC jumptable .


<s> const uint32_t * CSKYRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID Id ) const { const CSKYSubtarget & STI = MF . getSubtarget < CSKYSubtarget > ( ) ; return CSR_I32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static int scheduled_good_insn ( rtx_insn * last ) { if ( last && recog_memoized ( last ) >= 0 ) return 1 ; for ( ; last != NULL && ! NOTE_INSN_BASIC_BLOCK_P ( last ) && ! stops_p [ INSN_UID ( last ) ] ; last = PREV_INSN ( last ) ) if ( INSN_P ( last ) && recog_memoized ( last ) >= 0 ) return 1 ; return 0 ; } </s>

Returns 1 when a meaningful insn was scheduled between the last group barrier and LAST .


<s> static bool arm_array_mode_supported_p ( machine_mode mode , unsigned HOST_WIDE_INT nelems ) { if ( TARGET_NEON && ! BYTES_BIG_ENDIAN && ( VALID_NEON_DREG_MODE ( mode ) || VALID_NEON_QREG_MODE ( mode ) ) && ( nelems >= 2 && nelems <= 4 ) ) return true ; return false ; } </s>

Implements target hook array_mode_supported_p .


<s> int msp430_expand_shift ( enum rtx_code code , machine_mode mode , rtx * operands ) { if ( ! CONST_INT_P ( operands [ 2 ] ) || mode == E_DImode || use_helper_for_const_shift ( mode , INTVAL ( operands [ 2 ] ) ) ) { const char * helper_name = NULL ; bool const_variant = ! optimize_size ; switch ( mode ) { case E_HImode : helper_name = ( code == ASHIFT ? "__mspabi_slli" : ( code == ASHIFTRT ? "__mspabi_srai" : ( code == LSHIFTRT ? "__mspabi_srli" : NULL ) ) ) ; break ; case E_PSImode : helper_name = ( code == ASHIFT ? "__gnu_mspabi_sllp" : ( code == ASHIFTRT ? "__gnu_mspabi_srap" : ( code == LSHIFTRT ? "__gnu_mspabi_srlp" : NULL ) ) ) ; const_variant = false ; break ; case E_SImode : helper_name = ( code == ASHIFT ? "__mspabi_slll" : ( code == ASHIFTRT ? "__mspabi_sral" : ( code == LSHIFTRT ? "__mspabi_srll" : NULL ) ) ) ; break ; case E_DImode : helper_name = ( code == ASHIFT ? "__mspabi_sllll" : ( code == ASHIFTRT ? "__mspabi_srall" : ( code == LSHIFTRT ? "__mspabi_srlll" : NULL ) ) ) ; const_variant = false ; break ; default : gcc_unreachable ( ) ; break ; } gcc_assert ( helper_name ) ; msp430_expand_helper ( operands , helper_name , const_variant ) ; return 1 ; } return 0 ; } </s>

For shift operations which will use an mspabi helper function , setup the call to msp430_expand helper . Return 1 to indicate we have finished with this insn and invoke `` DONE '' . Otherwise return 0 to indicate the insn should fallthrough . Never FAIL .


<s> int NVPTXTTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: ADD : case ISD :: MUL : case ISD :: XOR : case ISD :: OR : case ISD :: AND : if ( LT . second . SimpleTy == MVT :: i64 ) return 2 * LT . first ; return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .

NVPTX NVPTX ISD::ADD ISD::MUL ISD::XOR ISD::OR ISD::AND MVT::i64 2


<s> SDValue XtensaTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SDValue ret ; return ret ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
X86
::
NumTargetFixupKinds
]
=
{
{
"reloc_riprel_4byte"
,
0
,
4
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_movq_load"
,
0
,
4
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_signed_4byte"
,
0
,
4
*
8
,
0
}
,
{
"reloc_global_offset_table"
,
0
,
4
*
8
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
TargetAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s>
bool
X86FrameLowering
::
canUseAsPrologue
(
const
MachineBasicBlock
&
MBB
)
const
{
assert
(
MBB
.
getParent
(
)
&&
"Block is not attached to a function!"
)
;
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
if
(
!
MBB
.
isLiveIn
(
X86
::
EFLAGS
)
)
return
true
;
const
X86MachineFunctionInfo
*
X86FI
=
MF
.
getInfo
<
X86MachineFunctionInfo
>
(
)
;
return
!
TRI
->
needsStackRealignment
(
MF
)
&&
!
X86FI
->
hasSwiftAsyncContext
(
)
;
}
</s>

Check whether or not the given MBB can be used as a prologue for the target .


<s> int m32c_hard_regno_nregs ( int regno , enum machine_mode mode ) { if ( regno == FLG_REGNO && mode == CCmode ) return 1 ; if ( regno >= FIRST_PSEUDO_REGISTER ) return ( ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ) ; if ( regno >= MEM0_REGNO && regno <= MEM7_REGNO ) return ( GET_MODE_SIZE ( mode ) + 1 ) / 2 ; if ( GET_MODE_SIZE ( mode ) <= 1 ) return nregs_table [ regno ] . qi_regs ; if ( GET_MODE_SIZE ( mode ) <= 2 ) return nregs_table [ regno ] . hi_regs ; if ( regno == A0_REGNO && mode == PSImode && TARGET_A16 ) return 2 ; if ( ( GET_MODE_SIZE ( mode ) <= 3 || mode == PSImode ) && TARGET_A24 ) return nregs_table [ regno ] . pi_regs ; if ( GET_MODE_SIZE ( mode ) <= 4 ) return nregs_table [ regno ] . si_regs ; if ( GET_MODE_SIZE ( mode ) <= 8 ) return nregs_table [ regno ] . di_regs ; return 0 ; } </s>

Implements HARD_REGNO_NREGS . This is complicated by the fact that different registers are different sizes from each other , * and * may be different sizes in different chip families .


<s> const LM32RegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool loongarch_check_zero_div_p ( void ) { if ( target_flags_explicit & MASK_CHECK_ZERO_DIV ) return TARGET_CHECK_ZERO_DIV ; return ! optimize || optimize_debug ; } </s>

Return true if we need to trap on division by zero .


<s> int arm_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( GET_MODE_CLASS ( mode ) == MODE_CC ) return ( regno == CC_REGNUM || ( TARGET_HARD_FLOAT && TARGET_VFP && regno == VFPCC_REGNUM ) ) ; if ( regno == CC_REGNUM && GET_MODE_CLASS ( mode ) != MODE_CC ) return false ; if ( TARGET_THUMB1 ) return ( ARM_NUM_REGS ( mode ) < 2 ) || ( regno < LAST_LO_REGNUM ) ; if ( TARGET_HARD_FLOAT && TARGET_VFP && IS_VFP_REGNUM ( regno ) ) { if ( mode == SFmode || mode == SImode ) return VFP_REGNO_OK_FOR_SINGLE ( regno ) ; if ( mode == DFmode ) return VFP_REGNO_OK_FOR_DOUBLE ( regno ) ; if ( mode == HFmode ) return TARGET_FP16 && VFP_REGNO_OK_FOR_SINGLE ( regno ) ; if ( TARGET_NEON ) return ( VALID_NEON_DREG_MODE ( mode ) && VFP_REGNO_OK_FOR_DOUBLE ( regno ) ) || ( VALID_NEON_QREG_MODE ( mode ) && NEON_REGNO_OK_FOR_QUAD ( regno ) ) || ( mode == TImode && NEON_REGNO_OK_FOR_NREGS ( regno , 2 ) ) || ( mode == EImode && NEON_REGNO_OK_FOR_NREGS ( regno , 3 ) ) || ( mode == OImode && NEON_REGNO_OK_FOR_NREGS ( regno , 4 ) ) || ( mode == CImode && NEON_REGNO_OK_FOR_NREGS ( regno , 6 ) ) || ( mode == XImode && NEON_REGNO_OK_FOR_NREGS ( regno , 8 ) ) ; return FALSE ; } if ( TARGET_REALLY_IWMMXT ) { if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return mode == SImode ; if ( IS_IWMMXT_REGNUM ( regno ) ) return VALID_IWMMXT_REG_MODE ( mode ) ; } if ( regno <= LAST_ARM_REGNUM ) { if ( ARM_NUM_REGS ( mode ) > 4 ) return FALSE ; if ( TARGET_THUMB2 ) return TRUE ; return ! ( TARGET_LDRD && GET_MODE_SIZE ( mode ) > 4 && ( regno & 1 ) != 0 ) ; } if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return GET_MODE_CLASS ( mode ) == MODE_INT ; return FALSE ; } </s>

Returns true if REGNO is a valid register for holding a quantity of type MODE .


<s> static vector_costs * ix86_vectorize_create_costs ( vec_info * vinfo , bool costing_for_scalar ) { return new ix86_vector_costs ( vinfo , costing_for_scalar ) ; } </s>


<s>
unsigned
AlphaRegisterInfo
::
getRARegister
(
)
const
{
assert
(
0
&&
"What is the return address register"
)
;
return
0
;
}
</s>

This method should return the register where the return address can be found .


<s> static void rs6000_split_v4si_init_di_reg ( rtx dest , rtx si1 , rtx si2 , rtx tmp ) { const unsigned HOST_WIDE_INT mask_32bit = HOST_WIDE_INT_C ( 0xffffffff ) ; if ( CONST_INT_P ( si1 ) && CONST_INT_P ( si2 ) ) { unsigned HOST_WIDE_INT const1 = ( UINTVAL ( si1 ) & mask_32bit ) << 32 ; unsigned HOST_WIDE_INT const2 = UINTVAL ( si2 ) & mask_32bit ; emit_move_insn ( dest , GEN_INT ( const1 | const2 ) ) ; return ; } if ( CONST_INT_P ( si1 ) ) emit_move_insn ( dest , GEN_INT ( ( UINTVAL ( si1 ) & mask_32bit ) << 32 ) ) ; else { rtx si1_di = gen_rtx_REG ( DImode , regno_or_subregno ( si1 ) ) ; rtx shift_rtx = gen_rtx_ASHIFT ( DImode , si1_di , GEN_INT ( 32 ) ) ; rtx mask_rtx = GEN_INT ( mask_32bit << 32 ) ; rtx and_rtx = gen_rtx_AND ( DImode , shift_rtx , mask_rtx ) ; gcc_assert ( ! reg_overlap_mentioned_p ( dest , si1 ) ) ; emit_insn ( gen_rtx_SET ( dest , and_rtx ) ) ; } gcc_assert ( ! reg_overlap_mentioned_p ( dest , tmp ) ) ; if ( CONST_INT_P ( si2 ) ) emit_move_insn ( tmp , GEN_INT ( UINTVAL ( si2 ) & mask_32bit ) ) ; else emit_insn ( gen_zero_extendsidi2 ( tmp , si2 ) ) ; emit_insn ( gen_iordi3 ( dest , dest , tmp ) ) ; return ; } </s>

Helper function for rs6000_split_v4si_init to build up a DImode value from two SImode values .


<s>
DEBUG_FUNCTION
void
rs6000_debug_print_mode
(
ssize_t
m
)
{
ssize_t
rc
;
int
spaces
=
0
;
fprintf
(
stderr
,
"Mode: %-5s"
,
GET_MODE_NAME
(
m
)
)
;
for
(
rc
=
0
;
rc
<
N_RELOAD_REG
;
rc
++
)
fprintf
(
stderr
,
" %s: %s"
,
reload_reg_map
[
rc
]
.
name
,
rs6000_debug_addr_mask
(
reg_addr
[
m
]
.
addr_mask
[
rc
]
,
true
)
)
;
if
(
(
reg_addr
[
m
]
.
reload_store
!=
CODE_FOR_nothing
)
||
(
reg_addr
[
m
]
.
reload_load
!=
CODE_FOR_nothing
)
)
{
fprintf
(
stderr
,
"%*s  Reload=%c%c"
,
spaces
,
""
,
(
reg_addr
[
m
]
.
reload_store
!=
CODE_FOR_nothing
)
's'
:
'*'
,
(
reg_addr
[
m
]
.
reload_load
!=
CODE_FOR_nothing
)
'l'
:
'*'
)
;
spaces
=
0
;
}
else
spaces
+=
strlen
(
"  Reload=sl"
)
;
if
(
reg_addr
[
m
]
.
scalar_in_vmx_p
)
{
fprintf
(
stderr
,
"%*s  Upper=y"
,
spaces
,
""
)
;
spaces
=
0
;
}
else
spaces
+=
strlen
(
"  Upper=y"
)
;
if
(
rs6000_vector_unit
[
m
]
!=
VECTOR_NONE
||
rs6000_vector_mem
[
m
]
!=
VECTOR_NONE
)
{
fprintf
(
stderr
,
"%*s  vector: arith=%-10s mem=%s"
,
spaces
,
""
,
rs6000_debug_vector_unit
(
rs6000_vector_unit
[
m
]
)
,
rs6000_debug_vector_unit
(
rs6000_vector_mem
[
m
]
)
)
;
}
fputs
(
"\n"
,
stderr
)
;
}
</s>

Print the address masks in a human readble fashion .


<s> bool X86TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( ! VT . isSimple ( ) ) return false ; MVT SVT = VT . getSimpleVT ( ) ; if ( VT . getSizeInBits ( ) == 64 ) return false ; if ( ExperimentalVectorShuffleLegality ) return isTypeLegal ( SVT ) ; if ( ( SVT . is128BitVector ( ) && Subtarget -> hasSSSE3 ( ) ) || ( SVT . is256BitVector ( ) && Subtarget -> hasInt256 ( ) ) ) { bool isLegal = true ; for ( unsigned I = 0 , E = M . size ( ) ; I != E ; ++ I ) { if ( M [ I ] >= ( int ) SVT . getVectorNumElements ( ) || ShuffleCrosses128bitLane ( SVT , I , M [ I ] ) ) { isLegal = false ; break ; } } if ( isLegal ) return true ; } return ( SVT . getVectorNumElements ( ) == 2 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isMOVLMask ( M , SVT ) || isCommutedMOVLMask ( M , SVT ) || isMOVHLPSMask ( M , SVT ) || isSHUFPMask ( M , SVT ) || isSHUFPMask ( M , SVT , true ) || isPSHUFDMask ( M , SVT ) || isPSHUFDMask ( M , SVT , true ) || isPSHUFHWMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isPSHUFLWMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isPALIGNRMask ( M , SVT , Subtarget ) || isUNPCKLMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isUNPCKHMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isUNPCKL_v_undef_Mask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isUNPCKH_v_undef_Mask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isBlendMask ( M , SVT , Subtarget -> hasSSE41 ( ) , Subtarget -> hasInt256 ( ) ) || ( Subtarget -> hasSSE41 ( ) && isINSERTPSMask ( M , SVT ) ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


"CSKY DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Patmos Delay Slot Killer"
;
}
</s>


<s> void HexagonInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned KillFlag = getKillRegState ( isKill ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; if ( Hexagon :: IntRegsRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: S2_storeri_io ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( Hexagon :: DoubleRegsRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: S2_storerd_io ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( Hexagon :: PredRegsRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: STriw_pred ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( Hexagon :: ModRegsRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: STriw_ctr ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( Hexagon :: HvxQRRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: PS_vstorerq_ai ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( Hexagon :: HvxVRRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: PS_vstorerv_ai ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( Hexagon :: HvxWRRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: PS_vstorerw_ai ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else { llvm_unreachable ( "Unimplemented" ) ; } } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> virtual const AMDGPURegisterInfo * getRegisterInfo ( ) const { return & InstrInfo -> getRegisterInfo ( ) ; } </s>


<s> static bool mips_vector_mode_supported_p ( machine_mode mode ) { switch ( mode ) { case E_V2SFmode : return TARGET_PAIRED_SINGLE_FLOAT ; case E_V2HImode : case E_V4QImode : case E_V2HQmode : case E_V2UHQmode : case E_V2HAmode : case E_V2UHAmode : case E_V4QQmode : case E_V4UQQmode : return TARGET_DSP ; case E_V2SImode : case E_V4HImode : case E_V8QImode : return TARGET_LOONGSON_MMI ; default : return MSA_SUPPORTED_MODE_P ( mode ) ; } } </s>

Target hook for vector_mode_supported_p .


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( CommentStream ) HasCustomInstComment = EmitAnyX86InstComments ( MI , * CommentStream , getRegisterName ) ; if ( TSFlags & X86II :: LOCK ) OS << "\tlock\t" ; if ( MI -> getOpcode ( ) == X86 :: CALLpcrel32 && ( STI . getFeatureBits ( ) [ X86 :: Mode64Bit ] ) ) { OS << "\tcallq\t" ; printPCRelImm ( MI , 0 , OS ) ; } else if ( ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> rtx s390_emit_compare ( enum rtx_code code , rtx op0 , rtx op1 ) { machine_mode mode = s390_select_ccmode ( code , op0 , op1 ) ; rtx cc ; if ( TARGET_VXE && GET_MODE ( op1 ) == TFmode ) op1 = force_reg ( TFmode , op1 ) ; if ( GET_MODE_CLASS ( GET_MODE ( op0 ) ) == MODE_CC ) { gcc_assert ( s390_cc_modes_compatible ( GET_MODE ( op0 ) , mode ) == GET_MODE ( op0 ) ) ; cc = op0 ; } else { cc = gen_rtx_REG ( mode , CC_REGNUM ) ; emit_insn ( gen_rtx_SET ( cc , gen_rtx_COMPARE ( mode , op0 , op1 ) ) ) ; } return gen_rtx_fmt_ee ( code , VOIDmode , cc , const0_rtx ) ; } </s>

Emit a compare instruction suitable to implement the comparison OP0 CODE OP1 . Return the correct condition RTL to be placed in the IF_THEN_ELSE of the conditional branch testing the result .


<s> bool TPCHWWAGeneral :: runOnMachineFunction ( MachineFunction & Func ) { bool Status = lookupWorkAround ( Func ) ; return Status ; } </s>

runOnMachineFunction - Emit the function body .


<s> StringRef getPassName ( ) const override { return "AArch64PostLegalizerLowering" ; } </s>


<s> bool PPCPassConfig :: addPreISel ( ) { if ( ! DisablePreIncPrep && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCLoopPreIncPrepPass ( getPPCTargetMachine ( ) ) ) ; if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCCTRLoops ( getPPCTargetMachine ( ) ) ) ; return false ; } </s>


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
Register
:
OS
<<
"<register x"
;
OS
<<
getReg
(
)
<<
">"
;
break
;
case
Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
case
SystemRegister
:
OS
<<
"<sysreg: "
<<
getSysReg
(
)
<<
'>'
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

RISCV
"<register x"
">"
"'"
"'"
"<sysreg: "


PowerPC
PPC
PPC
PPC
PPC
"AnyReg unimplemented on 32-bit AIX."
PPC::X2
"Cold calling unimplemented on AIX."
PPC
PPC
PPC
PPC
PPC
PPC


<s> static int sh_address_cost ( rtx X ) { return ( GET_CODE ( X ) == PLUS && ! CONSTANT_P ( XEXP ( X , 1 ) ) && ! TARGET_SHMEDIA ? 1 : 0 ) ; } </s>

Compute the cost of an address . For the SH , all valid addresses are the same cost . Use a slightly higher cost for reg + reg addressing , since it increases pressure on r0 .


<s>
bool
SparcAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
this
->
MF
=
&
MF
;
SetupMachineFunction
(
MF
)
;
EmitConstantPool
(
MF
.
getConstantPool
(
)
)
;
static
unsigned
BBNumber
=
0
;
O
<<
"\n\n"
;
const
Function
*
F
=
MF
.
getFunction
(
)
;
SwitchToSection
(
TAI
->
SectionForGlobal
(
F
)
)
;
EmitAlignment
(
4
,
F
)
;
O
<<
"\t.globl\t"
<<
CurrentFnName
<<
'\n'
;
printVisibility
(
CurrentFnName
,
F
->
getVisibility
(
)
)
;
O
<<
"\t.type\t"
<<
CurrentFnName
<<
", #function\n"
;
O
<<
CurrentFnName
<<
":\n"
;
NumberForBB
.
clear
(
)
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
NumberForBB
[
I
->
getBasicBlock
(
)
]
=
BBNumber
++
;
}
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
I
!=
MF
.
begin
(
)
)
{
printBasicBlockLabel
(
I
,
true
,
true
)
;
O
<<
'\n'
;
}
for
(
MachineBasicBlock
::
const_iterator
II
=
I
->
begin
(
)
,
E
=
I
->
end
(
)
;
II
!=
E
;
++
II
)
{
printInstruction
(
II
)
;
++
EmittedInsts
;
}
}
return
false
;
}
</s>


<s> bool SICFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return isUInt < 12 > ( MFI -> getMaxCallFrameSize ( ) + getStackAlignment ( ) ) && ! MFI -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> bool ix86_expand_int_vec_cmp ( rtx operands [ ] ) { rtx_code code = GET_CODE ( operands [ 1 ] ) ; bool negate = false ; rtx cmp = ix86_expand_int_sse_cmp ( operands [ 0 ] , code , operands [ 2 ] , operands [ 3 ] , NULL , NULL , & negate ) ; if ( ! cmp ) return false ; if ( negate ) cmp = ix86_expand_int_sse_cmp ( operands [ 0 ] , EQ , cmp , CONST0_RTX ( GET_MODE ( cmp ) ) , NULL , NULL , & negate ) ; gcc_assert ( ! negate ) ; if ( operands [ 0 ] != cmp ) emit_move_insn ( operands [ 0 ] , cmp ) ; return true ; } </s>


<s> SDNode * Tile64DAGToDAGISel :: Select ( SDNode * N ) { DebugLoc DL = N -> getDebugLoc ( ) ; if ( N -> isMachineOpcode ( ) ) return NULL ; switch ( N -> getOpcode ( ) ) { default : break ; case T64ISD :: GLOBAL_BASE_REG : return getGlobalBaseReg ( ) ; case ISD :: MUL : { SDValue MulLHS = N -> getOperand ( 0 ) ; SDValue MulRHS = N -> getOperand ( 1 ) ; SDNode * Mul = CurDAG -> getMachineNode ( T64 :: MULLL_UU , DL , MVT :: i32 , MulLHS , MulRHS ) ; Mul = CurDAG -> getMachineNode ( T64 :: MULHLSA_UU , DL , MVT :: i32 , SDValue ( Mul , 0 ) , MulLHS , MulRHS ) ; return CurDAG -> SelectNodeTo ( N , T64 :: MULHLSA_UU , MVT :: i32 , SDValue ( Mul , 0 ) , MulRHS , MulLHS ) ; } case ISD :: MULHU : case ISD :: MULHS : { SDValue MulLHS = N -> getOperand ( 0 ) ; SDValue MulRHS = N -> getOperand ( 1 ) ; unsigned OldOpcode = N -> getOpcode ( ) ; unsigned Opcode = OldOpcode == ISD :: MULHU ? T64 :: MULHL_UU : T64 :: MULHL_SS ; SDNode * Mul = CurDAG -> getMachineNode ( Opcode , DL , MVT :: i32 , MulLHS , MulRHS ) ; Opcode = OldOpcode == ISD :: MULHU ? T64 :: MULHLA_UU : T64 :: MULHLA_SS ; Mul = CurDAG -> getMachineNode ( Opcode , DL , MVT :: i32 , SDValue ( Mul , 0 ) , MulRHS , MulLHS ) ; Opcode = OldOpcode == ISD :: MULHU ? T64 :: SHRI : T64 :: SRAI ; Mul = CurDAG -> getMachineNode ( Opcode , DL , MVT :: i32 , SDValue ( Mul , 0 ) , CurDAG -> getTargetConstant ( 16 , MVT :: i8 ) ) ; Opcode = OldOpcode == ISD :: MULHU ? T64 :: MULHHA_UU : T64 :: MULHHA_SS ; return CurDAG -> SelectNodeTo ( N , Opcode , MVT :: i32 , SDValue ( Mul , 0 ) , MulLHS , MulRHS ) ; } } return SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> bool isFPImm ( ) const { return Kind == Float ; } </s>

isFPImm - Tests if this is a MO_FPImmediate operand .


<s> unsigned AMDGPUTargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const SelectionDAG & DAG , unsigned Depth ) const { switch ( Op . getOpcode ( ) ) { case AMDGPUISD :: BFE_I32 : { ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ; if ( ! Width ) return 1 ; unsigned SignBits = 32 - Width -> getZExtValue ( ) + 1 ; ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) ; if ( ! Offset || ! Offset -> isNullValue ( ) ) return SignBits ; unsigned Op0SignBits = DAG . ComputeNumSignBits ( Op . getOperand ( 0 ) , Depth + 1 ) ; return std :: max ( SignBits , Op0SignBits ) ; } case AMDGPUISD :: BFE_U32 : { ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ; return Width ? 32 - ( Width -> getZExtValue ( ) & 0x1f ) : 1 ; } default : return 1 ; } } </s>

Determine the number of bits in the operation that are sign bits .


<s> virtual bool doInitialization ( Module & M ) override { if ( ! TOC . empty ( ) ) TOC . clear ( ) ; return AsmPrinter :: doInitialization ( M ) ; } </s>

Set up the AsmPrinter when we are working on a new module .


"%<target_clones%> attribute needs GLIBC (2.23 and newer) that "

"multiversioning needs %<ifunc%> which is not supported "

Make a dispatcher declaration for the multi-versioned function DECL . Calls to DECL function will be replaced with calls to the dispatcher by the front-end . Returns the decl of the dispatcher function .


"unknown value %qs for 'tune' target %s"

Handle the argument STR to the tune= target attribute . PRAGMA_OR_ATTR is used in potential error messages .


<s>
MachineBasicBlock
::
iterator
SNESFrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
)
const
{
const
SNESSubtarget
&
STI
=
MF
.
getSubtarget
<
SNESSubtarget
>
(
)
;
const
TargetFrameLowering
&
TFI
=
*
STI
.
getFrameLowering
(
)
;
const
SNESInstrInfo
&
TII
=
*
STI
.
getInstrInfo
(
)
;
if
(
TFI
.
hasReservedCallFrame
(
MF
)
)
{
fixStackStores
(
MBB
,
MI
,
TII
,
false
)
;
return
MBB
.
erase
(
MI
)
;
}
DebugLoc
DL
=
MI
->
getDebugLoc
(
)
;
unsigned
int
Opcode
=
MI
->
getOpcode
(
)
;
int
Amount
=
TII
.
getFrameSize
(
*
MI
)
;
if
(
Amount
!=
0
)
{
assert
(
TFI
.
getStackAlignment
(
)
==
1
&&
"Unsupported stack alignment"
)
;
if
(
Opcode
==
TII
.
getCallFrameSetupOpcode
(
)
)
{
fixStackStores
(
MBB
,
MI
,
TII
,
true
)
;
}
else
{
assert
(
Opcode
==
TII
.
getCallFrameDestroyOpcode
(
)
)
;
unsigned
addOpcode
;
addOpcode
=
SNES
::
SUBIWRdK
;
Amount
=
Amount
;
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
SNES
::
SPREAD
)
,
SNES
::
A
)
.
addReg
(
SNES
::
SP
)
;
MachineInstr
*
New
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
addOpcode
)
,
SNES
::
A
)
.
addReg
(
SNES
::
A
,
RegState
::
Kill
)
.
addImm
(
Amount
)
;
New
->
getOperand
(
3
)
.
setIsDead
(
)
;
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
SNES
::
SPWRITE
)
,
SNES
::
SP
)
.
addReg
(
SNES
::
A
,
RegState
::
Kill
)
;
}
}
return
MBB
.
erase
(
MI
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

SNES
SNES
SNES
SNES
SNES
0
1
"Unsupported stack alignment"
SNES::SUBIWRdK
SNES::SPREAD
SNES::A
SNES::SP
SNES::A
SNES::A
3
SNES::SPWRITE
SNES::SP
SNES::A


<s> static bool ix86_expand_vector_init_one_var ( bool mmx_ok , machine_mode mode , rtx target , rtx vals , int one_var ) { rtx var = XVECEXP ( vals , 0 , one_var ) ; machine_mode wmode ; rtx const_vec , x ; const_vec = copy_rtx ( vals ) ; XVECEXP ( const_vec , 0 , one_var ) = CONST0_RTX ( GET_MODE_INNER ( mode ) ) ; const_vec = gen_rtx_CONST_VECTOR ( mode , XVEC ( const_vec , 0 ) ) ; switch ( mode ) { case E_V2DFmode : case E_V2DImode : case E_V2SFmode : case E_V2SImode : return false ; case E_V4DImode : if ( ! TARGET_64BIT ) return false ; case E_V8HFmode : case E_V16HFmode : case E_V8BFmode : case E_V16BFmode : case E_V4DFmode : case E_V8SFmode : case E_V8SImode : case E_V16HImode : case E_V32QImode : case E_V4SFmode : case E_V4SImode : case E_V8HImode : case E_V4HImode : break ; case E_V16QImode : if ( TARGET_SSE4_1 ) break ; wmode = V8HImode ; goto widen ; case E_V8QImode : if ( TARGET_MMX_WITH_SSE && TARGET_SSE4_1 ) break ; wmode = V4HImode ; goto widen ; case E_V4QImode : if ( TARGET_SSE4_1 ) break ; wmode = V2HImode ; widen : x = XVECEXP ( vals , 0 , one_var ^ 1 ) ; if ( one_var & 1 ) { var = convert_modes ( HImode , QImode , var , true ) ; var = expand_simple_binop ( HImode , ASHIFT , var , GEN_INT ( 8 ) , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; x = GEN_INT ( INTVAL ( x ) & 0xff ) ; } else { var = convert_modes ( HImode , QImode , var , true ) ; x = gen_int_mode ( UINTVAL ( x ) << 8 , HImode ) ; } if ( x != const0_rtx ) var = expand_simple_binop ( HImode , IOR , var , x , var , 1 , OPTAB_LIB_WIDEN ) ; x = gen_reg_rtx ( wmode ) ; emit_move_insn ( x , gen_lowpart ( wmode , const_vec ) ) ; ix86_expand_vector_set ( mmx_ok , x , var , one_var >> 1 ) ; emit_move_insn ( target , gen_lowpart ( mode , x ) ) ; return true ; default : return false ; } emit_move_insn ( target , const_vec ) ; ix86_expand_vector_set ( mmx_ok , target , var , one_var ) ; return true ; } </s>

A subroutine of ix86_expand_vector_init . Store into TARGET a vector consisting of the values in VALS . It is known that all elements except ONE_VAR are constants . Return true if successful .


<s> static void mips_init_libfuncs ( void ) { if ( TARGET_FIX_VR4120 ) { set_optab_libfunc ( sdiv_optab , SImode , "__vr4120_divsi3" ) ; set_optab_libfunc ( smod_optab , SImode , "__vr4120_modsi3" ) ; } if ( TARGET_MIPS16 && mips16_hard_float ) { set_optab_libfunc ( add_optab , SFmode , "__mips16_addsf3" ) ; set_optab_libfunc ( sub_optab , SFmode , "__mips16_subsf3" ) ; set_optab_libfunc ( smul_optab , SFmode , "__mips16_mulsf3" ) ; set_optab_libfunc ( sdiv_optab , SFmode , "__mips16_divsf3" ) ; set_optab_libfunc ( eq_optab , SFmode , "__mips16_eqsf2" ) ; set_optab_libfunc ( ne_optab , SFmode , "__mips16_nesf2" ) ; set_optab_libfunc ( gt_optab , SFmode , "__mips16_gtsf2" ) ; set_optab_libfunc ( ge_optab , SFmode , "__mips16_gesf2" ) ; set_optab_libfunc ( lt_optab , SFmode , "__mips16_ltsf2" ) ; set_optab_libfunc ( le_optab , SFmode , "__mips16_lesf2" ) ; set_conv_libfunc ( sfix_optab , SImode , SFmode , "__mips16_fix_truncsfsi" ) ; set_conv_libfunc ( sfloat_optab , SFmode , SImode , "__mips16_floatsisf" ) ; if ( TARGET_DOUBLE_FLOAT ) { set_optab_libfunc ( add_optab , DFmode , "__mips16_adddf3" ) ; set_optab_libfunc ( sub_optab , DFmode , "__mips16_subdf3" ) ; set_optab_libfunc ( smul_optab , DFmode , "__mips16_muldf3" ) ; set_optab_libfunc ( sdiv_optab , DFmode , "__mips16_divdf3" ) ; set_optab_libfunc ( eq_optab , DFmode , "__mips16_eqdf2" ) ; set_optab_libfunc ( ne_optab , DFmode , "__mips16_nedf2" ) ; set_optab_libfunc ( gt_optab , DFmode , "__mips16_gtdf2" ) ; set_optab_libfunc ( ge_optab , DFmode , "__mips16_gedf2" ) ; set_optab_libfunc ( lt_optab , DFmode , "__mips16_ltdf2" ) ; set_optab_libfunc ( le_optab , DFmode , "__mips16_ledf2" ) ; set_conv_libfunc ( sext_optab , DFmode , SFmode , "__mips16_extendsfdf2" ) ; set_conv_libfunc ( trunc_optab , SFmode , DFmode , "__mips16_truncdfsf2" ) ; set_conv_libfunc ( sfix_optab , SImode , DFmode , "__mips16_fix_truncdfsi" ) ; set_conv_libfunc ( sfloat_optab , DFmode , SImode , "__mips16_floatsidf" ) ; } } else gofast_maybe_init_libfuncs ( ) ; } </s>


<s> JVMSubtarget & JVMSubtarget :: initializeSubtargetDependencies ( StringRef FS ) { if ( CPUString . empty ( ) ) CPUString = "jvm" ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> void MipsTargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { return LowerOperationWrapper ( N , Results , DAG ) ; } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> bool SITargetLowering :: isKnownNeverNaNForTargetNode ( SDValue Op , const SelectionDAG & DAG , bool SNaN , unsigned Depth ) const { if ( Op . getOpcode ( ) == AMDGPUISD :: CLAMP ) { const MachineFunction & MF = DAG . getMachineFunction ( ) ; const SIMachineFunctionInfo * Info = MF . getInfo < SIMachineFunctionInfo > ( ) ; if ( Info -> getMode ( ) . DX10Clamp ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( 0 ) , SNaN , Depth + 1 ) ; } return AMDGPUTargetLowering :: isKnownNeverNaNForTargetNode ( Op , DAG , SNaN , Depth ) ; } </s>

AMDGPU SI AMDGPUISD::CLAMP SI SI 0 1 AMDGPU


<s> static void load_reg ( int reg , HOST_WIDE_INT disp , int base ) { rtx dest = gen_rtx_REG ( word_mode , reg ) ; rtx basereg = gen_rtx_REG ( Pmode , base ) ; rtx src ; if ( VAL_14_BITS_P ( disp ) ) src = gen_rtx_MEM ( word_mode , plus_constant ( basereg , disp ) ) ; else if ( TARGET_64BIT && ! VAL_32_BITS_P ( disp ) ) { rtx delta = GEN_INT ( disp ) ; rtx tmpreg = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( tmpreg , delta ) ; if ( TARGET_DISABLE_INDEXING ) { emit_move_insn ( tmpreg , gen_rtx_PLUS ( Pmode , tmpreg , basereg ) ) ; src = gen_rtx_MEM ( word_mode , tmpreg ) ; } else src = gen_rtx_MEM ( word_mode , gen_rtx_PLUS ( Pmode , tmpreg , basereg ) ) ; } else { rtx delta = GEN_INT ( disp ) ; rtx high = gen_rtx_PLUS ( Pmode , basereg , gen_rtx_HIGH ( Pmode , delta ) ) ; rtx tmpreg = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( tmpreg , high ) ; src = gen_rtx_MEM ( word_mode , gen_rtx_LO_SUM ( Pmode , tmpreg , delta ) ) ; } emit_move_insn ( dest , src ) ; } </s>

Emit RTL to load REG from the memory location specified by BASE+DISP . Handle case where DISP > 8k by using the add_high_const patterns .


<s> static rtx frame_stack_add ( HOST_WIDE_INT offset ) { return frame_add ( stack_pointer_rtx , offset ) ; } </s>

Emit a frame insn which adjusts stack pointer by OFFSET .


<s> unsigned MSP430RegisterInfo :: getRARegister ( ) const { return MSP430 :: PCW ; } </s>

This method should return the register where the return address can be found .


<s> const char * SystemZTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { OPCODE ( RET_FLAG ) ; OPCODE ( CALL ) ; OPCODE ( SIBCALL ) ; OPCODE ( PCREL_WRAPPER ) ; OPCODE ( ICMP ) ; OPCODE ( FCMP ) ; OPCODE ( TM ) ; OPCODE ( BR_CCMASK ) ; OPCODE ( SELECT_CCMASK ) ; OPCODE ( ADJDYNALLOC ) ; OPCODE ( EXTRACT_ACCESS ) ; OPCODE ( UMUL_LOHI64 ) ; OPCODE ( SDIVREM64 ) ; OPCODE ( UDIVREM32 ) ; OPCODE ( UDIVREM64 ) ; OPCODE ( MVC ) ; OPCODE ( MVC_LOOP ) ; OPCODE ( NC ) ; OPCODE ( NC_LOOP ) ; OPCODE ( OC ) ; OPCODE ( OC_LOOP ) ; OPCODE ( XC ) ; OPCODE ( XC_LOOP ) ; OPCODE ( CLC ) ; OPCODE ( CLC_LOOP ) ; OPCODE ( STRCMP ) ; OPCODE ( STPCPY ) ; OPCODE ( SEARCH_STRING ) ; OPCODE ( IPM ) ; OPCODE ( ATOMIC_SWAPW ) ; OPCODE ( ATOMIC_LOADW_ADD ) ; OPCODE ( ATOMIC_LOADW_SUB ) ; OPCODE ( ATOMIC_LOADW_AND ) ; OPCODE ( ATOMIC_LOADW_OR ) ; OPCODE ( ATOMIC_LOADW_XOR ) ; OPCODE ( ATOMIC_LOADW_NAND ) ; OPCODE ( ATOMIC_LOADW_MIN ) ; OPCODE ( ATOMIC_LOADW_MAX ) ; OPCODE ( ATOMIC_LOADW_UMIN ) ; OPCODE ( ATOMIC_LOADW_UMAX ) ; OPCODE ( ATOMIC_CMP_SWAPW ) ; OPCODE ( PREFETCH ) ; } return NULL ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> BitVector AArch64RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AArch64 :: SP ) ; Reserved . set ( AArch64 :: XZR ) ; Reserved . set ( AArch64 :: WSP ) ; Reserved . set ( AArch64 :: WZR ) ; if ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) { Reserved . set ( AArch64 :: FP ) ; Reserved . set ( AArch64 :: W29 ) ; } if ( TT . isOSDarwin ( ) || ReserveX18 ) { Reserved . set ( AArch64 :: X18 ) ; Reserved . set ( AArch64 :: W18 ) ; } if ( hasBasePointer ( MF ) ) { Reserved . set ( AArch64 :: X19 ) ; Reserved . set ( AArch64 :: W19 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static rtx zero_all_vector_registers ( HARD_REG_SET need_zeroed_hardregs ) { if ( ! TARGET_AVX ) return NULL ; for ( unsigned int regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ( IN_RANGE ( regno , FIRST_SSE_REG , LAST_SSE_REG ) || ( TARGET_64BIT && ( REX_SSE_REGNO_P ( regno ) || ( TARGET_AVX512F && EXT_REX_SSE_REGNO_P ( regno ) ) ) ) ) && ! TEST_HARD_REG_BIT ( need_zeroed_hardregs , regno ) ) return NULL ; return gen_avx_vzeroall ( ) ; } </s>

Generate a rtx to zero all vector registers together if possible , otherwise , return NULL .


"Patmos Single-Path Mark (machine code)"

getPassName - Return a nice clean name for a pass .


<s> static void frv_extract_membar ( struct frv_io * io , rtx insn ) { extract_insn ( insn ) ; io -> type = INTVAL ( recog_data . operand [ 2 ] ) ; io -> const_address = INTVAL ( recog_data . operand [ 1 ] ) ; io -> var_address = XEXP ( recog_data . operand [ 0 ] , 0 ) ; } </s>

Fill IO with information about the load or store associated with membar instruction INSN .


<s> void gen_conditional_branch ( rtx * operands , enum rtx_code code ) { rtx op0 , op1 , target ; mips_emit_compare ( & code , & op0 , & op1 , TARGET_MIPS16 ) ; target = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 , op1 ) , gen_rtx_LABEL_REF ( VOIDmode , operands [ 0 ] ) , pc_rtx ) ; emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , target ) ) ; } </s>

Emit the common code for doing conditional branches . operand [ 0 ] is the label to jump to . The comparison operands are saved away by cmp { si , di , sf , df } .


<s> std :: pair < uint16_t , uint16_t > X86InstrInfo :: getExecutionDomain ( const MachineInstr * MI ) const { uint16_t domain = ( MI -> getDesc ( ) . TSFlags >> X86II :: SSEDomainShift ) & 3 ; return std :: make_pair ( domain , domain && lookup ( MI -> getOpcode ( ) , domain ) ? 0xe : 0 ) ; } </s>

Return the current execution domain and bit mask of possible domains for instruction .


"insertBranch must not be told to insert a fallthrough"

"RISCV branch conditions have two components!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> bool PPCAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == ".word" ) return ParseDirectiveWord ( 4 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".tc" ) return ParseDirectiveTC ( isPPC64 ( ) ? 8 : 4 , DirectiveID . getLoc ( ) ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> static cond_type is_cond_candidate ( rtx insn ) { if ( GET_CODE ( insn ) == INSN ) { rtx pat = PATTERN ( insn ) ; rtx src , dst ; if ( GET_CODE ( pat ) != SET ) return COND_NO ; dst = XEXP ( pat , 0 ) ; if ( ( GET_CODE ( dst ) != REG && GET_CODE ( dst ) != SUBREG ) || GET_MODE ( dst ) != SImode ) return COND_NO ; src = XEXP ( pat , 1 ) ; if ( ( GET_CODE ( src ) == REG || ( GET_CODE ( src ) == SUBREG && GET_CODE ( SUBREG_REG ( src ) ) == REG ) ) && GET_MODE ( src ) == SImode ) return COND_MOV_INSN ; else if ( GET_CODE ( src ) == CONST_INT && INTVAL ( src ) == 0 ) return COND_CLR_INSN ; else if ( GET_CODE ( src ) == PLUS && ( GET_CODE ( XEXP ( src , 0 ) ) == REG || ( GET_CODE ( XEXP ( src , 0 ) ) == SUBREG && GET_CODE ( SUBREG_REG ( XEXP ( src , 0 ) ) ) == REG ) ) && GET_MODE ( XEXP ( src , 0 ) ) == SImode && GET_CODE ( XEXP ( src , 1 ) ) == CONST_INT && INTVAL ( XEXP ( src , 1 ) ) == 1 ) return COND_INC_INSN ; else if ( ( ( GET_CODE ( src ) == MINUS && GET_CODE ( XEXP ( src , 1 ) ) == CONST_INT && INTVAL ( XEXP ( src , 1 ) ) == 1 ) || ( GET_CODE ( src ) == PLUS && GET_CODE ( XEXP ( src , 1 ) ) == CONST_INT && INTVAL ( XEXP ( src , 1 ) ) == - 1 ) ) && ( GET_CODE ( XEXP ( src , 0 ) ) == REG || ( GET_CODE ( XEXP ( src , 0 ) ) == SUBREG && GET_CODE ( SUBREG_REG ( XEXP ( src , 0 ) ) ) == REG ) ) && GET_MODE ( XEXP ( src , 0 ) ) == SImode ) return COND_DEC_INSN ; } else if ( GET_CODE ( insn ) == JUMP_INSN && GET_CODE ( PATTERN ( insn ) ) == SET && GET_CODE ( XEXP ( PATTERN ( insn ) , 1 ) ) == LABEL_REF ) return COND_BRANCH_INSN ; return COND_NO ; } </s>

Check whether insn is a candidate for a conditional .


<s> bool R600InstrInfo :: SubsumesPredicate ( const SmallVectorImpl < MachineOperand > & Pred1 , const SmallVectorImpl < MachineOperand > & Pred2 ) const { return false ; } </s>

Returns true if the first specified predicate subsumes the second , e.g .


<s> Function * AMDGPULibFunc :: getOrInsertFunction ( Module * M , const AMDGPULibFunc & fInfo ) { std :: string const FuncName = fInfo . mangle ( ) ; Function * F = dyn_cast_or_null < Function > ( M -> getValueSymbolTable ( ) . lookup ( FuncName ) ) ; if ( F && ! F -> isDeclaration ( ) && ! F -> isVarArg ( ) && F -> arg_size ( ) == fInfo . getNumArgs ( ) ) { return F ; } FunctionType * FuncTy = fInfo . getFunctionType ( * M ) ; bool hasPtr = false ; for ( FunctionType :: param_iterator PI = FuncTy -> param_begin ( ) , PE = FuncTy -> param_end ( ) ; PI != PE ; ++ PI ) { const Type * argTy = static_cast < const Type * > ( * PI ) ; if ( argTy -> isPointerTy ( ) ) { hasPtr = true ; break ; } } Constant * C = nullptr ; if ( hasPtr ) { C = M -> getOrInsertFunction ( FuncName , FuncTy ) ; } else { AttributeList Attr ; LLVMContext & Ctx = M -> getContext ( ) ; Attr = Attr . addAttribute ( Ctx , AttributeList :: FunctionIndex , Attribute :: ReadOnly ) ; Attr = Attr . addAttribute ( Ctx , AttributeList :: FunctionIndex , Attribute :: NoUnwind ) ; C = M -> getOrInsertFunction ( FuncName , FuncTy , Attr ) ; } return cast < Function > ( C ) ; } </s>

Look up the specified function in the module symbol table .


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < SparcELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this , is64bit ) { initAsmInfo ( ) ; } </s>


<s> virtual bool isToken ( ) const LLVM_OVERRIDE { return Kind == KindToken ; } </s>


<s> NodeId getNext ( ) const { return Next ; } </s>


<s> void ix86_expand_round_sse4 ( rtx op0 , rtx op1 ) { machine_mode mode = GET_MODE ( op0 ) ; rtx e1 , e2 , res , half ; const struct real_format * fmt ; REAL_VALUE_TYPE pred_half , half_minus_pred_half ; rtx ( * gen_copysign ) ( rtx , rtx , rtx ) ; rtx ( * gen_round ) ( rtx , rtx , rtx ) ; switch ( mode ) { case E_SFmode : gen_copysign = gen_copysignsf3 ; gen_round = gen_sse4_1_roundsf2 ; break ; case E_DFmode : gen_copysign = gen_copysigndf3 ; gen_round = gen_sse4_1_rounddf2 ; break ; default : gcc_unreachable ( ) ; } fmt = REAL_MODE_FORMAT ( mode ) ; real_2expN ( & half_minus_pred_half , - ( fmt -> p ) - 1 , mode ) ; real_arithmetic ( & pred_half , MINUS_EXPR , & dconsthalf , & half_minus_pred_half ) ; half = const_double_from_real_value ( pred_half , mode ) ; e1 = gen_reg_rtx ( mode ) ; emit_insn ( gen_copysign ( e1 , half , op1 ) ) ; e2 = expand_simple_binop ( mode , PLUS , op1 , e1 , NULL_RTX , 0 , OPTAB_DIRECT ) ; res = gen_reg_rtx ( mode ) ; emit_insn ( gen_round ( res , e2 , GEN_INT ( ROUND_TRUNC ) ) ) ; emit_move_insn ( op0 , res ) ; } </s>

Expand SSE sequence for computing round from OP1 storing into OP0 using sse4 round insn .


<s> void AMDGPUPassConfig :: addIRPasses ( ) { disablePass ( & StackMapLivenessID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & PatchableFunctionID ) ; addPass ( createAMDGPULowerIntrinsicsPass ( ) ) ; addPass ( createAMDGPUAlwaysInlinePass ( ) ) ; addPass ( createAlwaysInlinerLegacyPass ( ) ) ; addPass ( createBarrierNoopPass ( ) ) ; const AMDGPUTargetMachine & TM = getAMDGPUTargetMachine ( ) ; if ( TM . getTargetTriple ( ) . getArch ( ) == Triple :: amdgcn ) { addPass ( createAMDGPUCodeGenPreparePass ( static_cast < const GCNTargetMachine * > ( & TM ) ) ) ; } addPass ( createAMDGPUOpenCLImageTypeLoweringPass ( ) ) ; if ( TM . getOptLevel ( ) > CodeGenOpt :: None ) { addPass ( createInferAddressSpacesPass ( ) ) ; addPass ( createAMDGPUPromoteAlloca ( & TM ) ) ; if ( EnableSROA ) addPass ( createSROAPass ( ) ) ; addStraightLineScalarOptimizationPasses ( ) ; if ( EnableAMDGPUAliasAnalysis ) { addPass ( createAMDGPUAAWrapperPass ( ) ) ; addPass ( createExternalAAWrapperPass ( [ ] ( Pass & P , Function & , AAResults & AAR ) { if ( auto * WrapperPass = P . getAnalysisIfAvailable < AMDGPUAAWrapperPass > ( ) ) AAR . addAAResult ( WrapperPass -> getResult ( ) ) ; } ) ) ; } } TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addEarlyCSEOrGVNPass ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU


<s>
unsigned
getReg
(
)
const
{
assert
(
Kind
==
Register
&&
"Invalid access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s> static int tilepro_sched_adjust_cost ( rtx_insn * insn , rtx link , rtx_insn * dep_insn , int cost ) { if ( CALL_P ( insn ) && REG_NOTE_KIND ( link ) == REG_DEP_TRUE ) { rtx target = get_jump_target ( insn ) ; if ( ! REG_P ( target ) || ! set_of ( target , dep_insn ) ) return 0 ; } return cost ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"ARM MVE VPT Optimisation Pass"
;
}
</s>


<s> bool RISCVTargetLowering :: isZExtFree ( SDValue Val , EVT VT2 ) const { if ( auto * LD = dyn_cast < LoadSDNode > ( Val ) ) { EVT MemVT = LD -> getMemoryVT ( ) ; if ( ( MemVT == MVT :: i8 || MemVT == MVT :: i16 || ( Subtarget . is64Bit ( ) && MemVT == MVT :: i32 ) ) && ( LD -> getExtensionType ( ) == ISD :: NON_EXTLOAD || LD -> getExtensionType ( ) == ISD :: ZEXTLOAD ) ) return true ; } return TargetLowering :: isZExtFree ( Val , VT2 ) ; } </s>

Return true if zero-extending the specific node Val to type VT2 is free ( either because it 's implicitly zero-extended such as ARM ldrb / ldrh or because it 's folded such as X86 zero-extending loads ) .


<s> bool ix86_expand_int_addcc ( rtx operands [ ] ) { enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; rtx flags ; rtx ( * insn ) ( rtx , rtx , rtx , rtx , rtx ) ; rtx compare_op ; rtx val = const0_rtx ; bool fpcmp = false ; machine_mode mode ; rtx op0 = XEXP ( operands [ 1 ] , 0 ) ; rtx op1 = XEXP ( operands [ 1 ] , 1 ) ; if ( operands [ 3 ] != const1_rtx && operands [ 3 ] != constm1_rtx ) return false ; if ( ! ix86_expand_carry_flag_compare ( code , op0 , op1 , & compare_op ) ) return false ; code = GET_CODE ( compare_op ) ; flags = XEXP ( compare_op , 0 ) ; if ( GET_MODE ( flags ) == CCFPmode || GET_MODE ( flags ) == CCFPUmode ) { fpcmp = true ; code = ix86_fp_compare_code_to_integer ( code ) ; } if ( code != LTU ) { val = constm1_rtx ; if ( fpcmp ) PUT_CODE ( compare_op , reverse_condition_maybe_unordered ( GET_CODE ( compare_op ) ) ) ; else PUT_CODE ( compare_op , reverse_condition ( GET_CODE ( compare_op ) ) ) ; } mode = GET_MODE ( operands [ 0 ] ) ; if ( ( code == LTU ) == ( operands [ 3 ] == constm1_rtx ) ) { switch ( mode ) { case QImode : insn = gen_subqi3_carry ; break ; case HImode : insn = gen_subhi3_carry ; break ; case SImode : insn = gen_subsi3_carry ; break ; case DImode : insn = gen_subdi3_carry ; break ; default : gcc_unreachable ( ) ; } } else { switch ( mode ) { case QImode : insn = gen_addqi3_carry ; break ; case HImode : insn = gen_addhi3_carry ; break ; case SImode : insn = gen_addsi3_carry ; break ; case DImode : insn = gen_adddi3_carry ; break ; default : gcc_unreachable ( ) ; } } emit_insn ( insn ( operands [ 0 ] , operands [ 2 ] , val , flags , compare_op ) ) ; return true ; } </s>

Expand conditional increment or decrement using adb/sbb instructions . The default case using setcc followed by the conditional move can be done by generic code .


<s> void AVRTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { Base :: Initialize ( Ctx , TM ) ; ProgmemDataSection = Ctx . getELFSection ( ".progmem.data" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ; Progmem1DataSection = Ctx . getELFSection ( ".progmem1.data" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ; Progmem2DataSection = Ctx . getELFSection ( ".progmem2.data" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ; Progmem3DataSection = Ctx . getELFSection ( ".progmem3.data" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ; Progmem4DataSection = Ctx . getELFSection ( ".progmem4.data" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ; Progmem5DataSection = Ctx . getELFSection ( ".progmem5.data" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ; } </s>

This method must be called before any actual lowering is done .


<s> static void handle_attr_preserve ( function * fn ) { basic_block bb ; rtx_insn * insn ; rtx_code_label * label ; FOR_EACH_BB_FN ( bb , fn ) { FOR_BB_INSNS ( bb , insn ) { if ( ! NONJUMP_INSN_P ( insn ) ) continue ; rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) != SET ) continue ; start_sequence ( ) ; for ( int i = 0 ; i < 2 ; i ++ ) { rtx mem = XEXP ( pat , i ) ; if ( MEM_P ( mem ) ) { tree expr = MEM_EXPR ( mem ) ; if ( ! expr ) continue ; if ( TREE_CODE ( expr ) == MEM_REF && TREE_CODE ( TREE_OPERAND ( expr , 0 ) ) == SSA_NAME ) { gimple * def_stmt = SSA_NAME_DEF_STMT ( TREE_OPERAND ( expr , 0 ) ) ; if ( def_stmt && is_gimple_assign ( def_stmt ) ) expr = gimple_assign_rhs1 ( def_stmt ) ; } if ( is_attr_preserve_access ( expr ) ) { auto_vec < unsigned int , 16 > accessors ; tree container = bpf_core_compute ( expr , & accessors ) ; if ( accessors . length ( ) < 1 ) continue ; accessors . reverse ( ) ; container = TREE_TYPE ( container ) ; const char * section_name ; if ( DECL_SECTION_NAME ( fn -> decl ) ) section_name = DECL_SECTION_NAME ( fn -> decl ) ; else section_name = ".text" ; label = gen_label_rtx ( ) ; LABEL_PRESERVE_P ( label ) = 1 ; emit_label ( label ) ; bpf_core_reloc_add ( container , section_name , & accessors , label ) ; } } } rtx_insn * seq = get_insns ( ) ; end_sequence ( ) ; emit_insn_before ( seq , insn ) ; } } } </s>

The body of pass_bpf_core_attr . Scan RTL for accesses to structs/unions marked with __attribute__ ( ( preserve_access_index ) ) and generate a CO-RE relocation for any such access .


<s> enum machine_mode select_cc_mode ( enum rtx_code op , rtx x , rtx y ATTRIBUTE_UNUSED ) { if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) { switch ( op ) { case EQ : case NE : case UNORDERED : case ORDERED : case UNLT : case UNLE : case UNGT : case UNGE : case UNEQ : case LTGT : return CCFPmode ; case LT : case LE : case GT : case GE : return CCFPEmode ; default : gcc_unreachable ( ) ; } } else if ( GET_CODE ( x ) == PLUS || GET_CODE ( x ) == MINUS || GET_CODE ( x ) == NEG || GET_CODE ( x ) == ASHIFT ) { if ( TARGET_ARCH64 && GET_MODE ( x ) == DImode ) return CCX_NOOVmode ; else return CC_NOOVmode ; } else { if ( TARGET_ARCH64 && GET_MODE ( x ) == DImode ) return CCXmode ; else return CCmode ; } } </s>

Given a comparison code ( EQ , NE , etc . ) and the first operand of a COMPARE , return the mode to be used for the comparison . For floating-point , CCFP [ E ] mode is used . CC_NOOVmode should be used when the first operand is a PLUS , MINUS , NEG , or ASHIFT . CCmode should be used when no special processing is needed .


<s>
void
relaxInstruction
(
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
)
const
override
{
llvm_unreachable
(
"relaxInstruction() unimplemented"
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s>
void
X86InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
assert
(
MF
.
getFrameInfo
(
)
->
getObjectSize
(
FrameIdx
)
>=
RC
->
getSize
(
)
&&
"Stack slot too small for store"
)
;
bool
isAligned
=
(
RI
.
getStackAlignment
(
)
>=
16
)
||
RI
.
canRealignStack
(
MF
)
;
unsigned
Opc
=
getStoreRegOpcode
(
SrcReg
,
RC
,
isAligned
,
TM
)
;
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s>
virtual
const
ARMBaseInstrInfo
*
getInstrInfo
(
)
const
{
llvm_unreachable
(
"getInstrInfo not implemented"
)
;
}
</s>


<s>
void
SystemZPostRASchedStrategy
::
schedNode
(
SUnit
*
SU
,
bool
IsTopNode
)
{
DEBUG
(
dbgs
(
)
<<
"+++ Scheduling SU("
<<
SU
->
NodeNum
<<
")\n"
;
)
;
Available
.
erase
(
SU
)
;
HazardRec
->
EmitInstruction
(
SU
)
;
}
</s>

ScheduleDAGMI has scheduled an instruction - tell HazardRec about it .

SystemZ
SystemZ
"+++ Scheduling SU("
")\n"


<s> bool AMDGPUTargetLowering :: isFNegFree ( EVT VT ) const { assert ( VT . isFloatingPoint ( ) ) ; VT = VT . getScalarType ( ) ; return VT == MVT :: f32 || VT == MVT :: f64 || VT == MVT :: f16 ; } </s>

Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation .


<s> MCObjectWriter * BPFAsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { return createBPFELFObjectWriter ( OS , 0 , IsLittleEndian ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> std :: pair < unsigned , const TargetRegisterClass * > NVPTXTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'b' : return std :: make_pair ( 0U , & NVPTX :: Int1RegsRegClass ) ; case 'c' : return std :: make_pair ( 0U , & NVPTX :: Int16RegsRegClass ) ; case 'h' : return std :: make_pair ( 0U , & NVPTX :: Int16RegsRegClass ) ; case 'r' : return std :: make_pair ( 0U , & NVPTX :: Int32RegsRegClass ) ; case 'l' : case 'N' : return std :: make_pair ( 0U , & NVPTX :: Int64RegsRegClass ) ; case 'f' : return std :: make_pair ( 0U , & NVPTX :: Float32RegsRegClass ) ; case 'd' : return std :: make_pair ( 0U , & NVPTX :: Float64RegsRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


"SPUTargetLowering::ReplaceNodeResults(): need to fix this!\n"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> MachineInstr * ARMBaseInstrInfo :: commuteInstructionImpl ( MachineInstr & MI , bool NewMI , unsigned OpIdx1 , unsigned OpIdx2 ) const { switch ( MI . getOpcode ( ) ) { case ARM :: MOVCCr : case ARM :: t2MOVCCr : { Register PredReg ; ARMCC :: CondCodes CC = getInstrPredicate ( MI , PredReg ) ; if ( CC == ARMCC :: AL || PredReg != ARM :: CPSR ) return nullptr ; MachineInstr * CommutedMI = TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1 , OpIdx2 ) ; if ( ! CommutedMI ) return nullptr ; CommutedMI -> getOperand ( CommutedMI -> findFirstPredOperandIdx ( ) ) . setImm ( ARMCC :: getOppositeCondition ( CC ) ) ; return CommutedMI ; } } return TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1 , OpIdx2 ) ; } </s>

Commutes the operands in the given instruction by changing the operands order and/or changing the instruction 's opcode and/or the immediate value operand .

ARM ARM ARM::MOVCCr ARM::t2MOVCCr ARMCC::CondCodes ARMCC::AL ARM::CPSR ARMCC::getOppositeCondition


<s> bool ARCompactTargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createARCompactISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


"selected fp16 options are incompatible"

"%<-mstack-protector-guard=tls%> needs a hardware TLS register"

Reconfigure global status flags from the active_target.isa .


<s> const MCPhysReg * SIRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { CallingConv :: ID CC = MF -> getFunction ( ) -> getCallingConv ( ) ; switch ( CC ) { case CallingConv :: C : case CallingConv :: Fast : return CSR_AMDGPU_HighRegs_SaveList ; default : { static const MCPhysReg NoCalleeSavedReg = AMDGPU :: NoRegister ; return & NoCalleeSavedReg ; } } } </s>


<s>
unsigned
getReg
(
)
const
override
{
assert
(
Kind
==
Register
&&
"Invalid type access!"
)
;
return
Reg
.
RegNum
;
}
</s>


<s> static void arm_init_mve_builtins ( void ) { volatile unsigned int i , fcode = ARM_BUILTIN_MVE_PATTERN_START ; arm_init_simd_builtin_scalar_types ( ) ; arm_init_simd_builtin_types ( ) ; tree get_fpscr_nzcvqc = build_function_type_list ( intSI_type_node , NULL ) ; tree set_fpscr_nzcvqc = build_function_type_list ( void_type_node , intSI_type_node , NULL ) ; arm_builtin_decls [ ARM_BUILTIN_GET_FPSCR_NZCVQC ] = add_builtin_function ( "__builtin_arm_get_fpscr_nzcvqc" , get_fpscr_nzcvqc , ARM_BUILTIN_GET_FPSCR_NZCVQC , BUILT_IN_MD , NULL , NULL_TREE ) ; arm_builtin_decls [ ARM_BUILTIN_SET_FPSCR_NZCVQC ] = add_builtin_function ( "__builtin_arm_set_fpscr_nzcvqc" , set_fpscr_nzcvqc , ARM_BUILTIN_SET_FPSCR_NZCVQC , BUILT_IN_MD , NULL , NULL_TREE ) ; for ( i = 0 ; i < ARRAY_SIZE ( mve_builtin_data ) ; i ++ , fcode ++ ) { arm_builtin_datum * d = & mve_builtin_data [ i ] ; arm_init_builtin ( fcode , d , "__builtin_mve" ) ; } } </s>

Set up all the MVE builtins mentioned in arm_mve_builtins.def file .


<s> bool AMDGPUCommonSubtarget :: makeLIDRangeMetadata ( Instruction * I ) const { Function * Kernel = I -> getParent ( ) -> getParent ( ) ; unsigned MinSize = 0 ; unsigned MaxSize = getFlatWorkGroupSizes ( * Kernel ) . second ; bool IdQuery = false ; if ( auto * CI = dyn_cast < CallInst > ( I ) ) { const Function * F = CI -> getCalledFunction ( ) ; if ( F ) { unsigned Dim = UINT_MAX ; switch ( F -> getIntrinsicID ( ) ) { case Intrinsic :: amdgcn_workitem_id_x : case Intrinsic :: r600_read_tidig_x : IdQuery = true ; LLVM_FALLTHROUGH ; case Intrinsic :: r600_read_local_size_x : Dim = 0 ; break ; case Intrinsic :: amdgcn_workitem_id_y : case Intrinsic :: r600_read_tidig_y : IdQuery = true ; LLVM_FALLTHROUGH ; case Intrinsic :: r600_read_local_size_y : Dim = 1 ; break ; case Intrinsic :: amdgcn_workitem_id_z : case Intrinsic :: r600_read_tidig_z : IdQuery = true ; LLVM_FALLTHROUGH ; case Intrinsic :: r600_read_local_size_z : Dim = 2 ; break ; default : break ; } if ( Dim <= 3 ) { if ( auto Node = Kernel -> getMetadata ( "reqd_work_group_size" ) ) if ( Node -> getNumOperands ( ) == 3 ) MinSize = MaxSize = mdconst :: extract < ConstantInt > ( Node -> getOperand ( Dim ) ) -> getZExtValue ( ) ; } } } if ( ! MaxSize ) return false ; if ( IdQuery ) MinSize = 0 ; else ++ MaxSize ; MDBuilder MDB ( I -> getContext ( ) ) ; MDNode * MaxWorkGroupSizeRange = MDB . createRange ( APInt ( 32 , MinSize ) , APInt ( 32 , MaxSize ) ) ; I -> setMetadata ( LLVMContext :: MD_range , MaxWorkGroupSizeRange ) ; return true ; } </s>

Creates value range metadata on an workitemid . * intrinsic call or load .


<s> void pdp11_expand_prologue ( void ) { HOST_WIDE_INT fsize = get_frame_size ( ) ; unsigned regno ; rtx x , via_ac = NULL ; if ( MAIN_NAME_P ( DECL_NAME ( current_function_decl ) ) && TARGET_FPU ) { emit_insn ( gen_setd ( ) ) ; emit_insn ( gen_seti ( ) ) ; } for ( regno = R0_REGNUM ; regno <= PC_REGNUM ; regno ++ ) if ( pdp11_saved_regno ( regno ) ) { x = gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ; x = gen_frame_mem ( Pmode , x ) ; emit_move_insn ( x , gen_rtx_REG ( Pmode , regno ) ) ; } for ( regno = AC0_REGNUM ; regno <= AC3_REGNUM ; regno ++ ) if ( pdp11_saved_regno ( regno ) ) { x = gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ; x = gen_frame_mem ( DFmode , x ) ; via_ac = gen_rtx_REG ( DFmode , regno ) ; emit_move_insn ( x , via_ac ) ; } for ( regno = AC4_REGNUM ; regno <= AC5_REGNUM ; regno ++ ) if ( pdp11_saved_regno ( regno ) ) { gcc_assert ( via_ac != NULL ) ; emit_move_insn ( via_ac , gen_rtx_REG ( DFmode , regno ) ) ; x = gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ; x = gen_frame_mem ( DFmode , x ) ; emit_move_insn ( x , via_ac ) ; } if ( frame_pointer_needed ) emit_move_insn ( frame_pointer_rtx , stack_pointer_rtx ) ; if ( fsize ) emit_insn ( gen_addhi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - fsize ) ) ) ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"Hexagon generate predicate operations"
;
}
</s>

getPassName - Return a nice clean name for a pass .

Hexagon
"Hexagon generate predicate operations"


"emitting PIC operand, but PIC register isn't set up"

Worker function for ASM_OUTPUT_LABEL_REF .


<s> void SITargetLowering :: computeKnownBitsForTargetInstr ( GISelKnownBits & KB , Register R , KnownBits & Known , const APInt & DemandedElts , const MachineRegisterInfo & MRI , unsigned Depth ) const { const MachineInstr * MI = MRI . getVRegDef ( R ) ; switch ( MI -> getOpcode ( ) ) { case AMDGPU :: G_INTRINSIC : { switch ( MI -> getIntrinsicID ( ) ) { case Intrinsic :: amdgcn_workitem_id_x : knownBitsForWorkitemID ( * getSubtarget ( ) , KB , Known , 0 ) ; break ; case Intrinsic :: amdgcn_workitem_id_y : knownBitsForWorkitemID ( * getSubtarget ( ) , KB , Known , 1 ) ; break ; case Intrinsic :: amdgcn_workitem_id_z : knownBitsForWorkitemID ( * getSubtarget ( ) , KB , Known , 2 ) ; break ; case Intrinsic :: amdgcn_mbcnt_lo : case Intrinsic :: amdgcn_mbcnt_hi : { unsigned Size = MRI . getType ( R ) . getSizeInBits ( ) ; Known . Zero . setHighBits ( Size - getSubtarget ( ) -> getWavefrontSizeLog2 ( ) ) ; break ; } case Intrinsic :: amdgcn_groupstaticsize : { Known . Zero . setHighBits ( countLeadingZeros ( getSubtarget ( ) -> getLocalMemorySize ( ) ) ) ; break ; } default : break ; } } } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> static void frv_registers_update_1 ( rtx x , rtx pat ATTRIBUTE_UNUSED , void * data ) { unsigned int regno ; if ( GET_CODE ( x ) == REG ) FOR_EACH_REGNO ( regno , x ) frv_packet . regstate [ regno ] |= * ( regstate_t * ) data ; if ( GET_CODE ( x ) == MEM ) { if ( frv_packet . num_mems < ARRAY_SIZE ( frv_packet . mems ) ) { frv_packet . mems [ frv_packet . num_mems ] . mem = x ; frv_packet . mems [ frv_packet . num_mems ] . cond = * ( regstate_t * ) data ; } frv_packet . num_mems ++ ; } } </s>

A note_stores callback . DATA points to the regstate_t condition under which X is modified . Update FRV_PACKET accordingly .


"WebAssembly should not have callee-saved registers"

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
KindTy
::
Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
KindTy
::
Register
:
OS
<<
"<register x"
;
OS
<<
getReg
(
)
<<
">"
;
break
;
case
KindTy
::
Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
case
KindTy
::
SystemRegister
:
OS
<<
"<sysreg: "
<<
getSysReg
(
)
<<
'>'
;
break
;
case
KindTy
::
VectorRegister
:
OS
<<
"<vecreg: "
<<
getVecReg
(
)
<<
'>'
;
break
;
case
KindTy
::
VTypeImm
:
SmallVector
<
char
,
8
>
VTypeBuf
;
OS
<<
"<vtypei: "
<<
getVTypeImm
(
VTypeBuf
)
<<
'>'
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

RISCV
"<register x"
">"
"'"
"'"
"<sysreg: "
"<vecreg: "
8
"<vtypei: "


<s> static void nios2_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; HOST_WIDE_INT param_size = arg . promoted_size_in_bytes ( ) ; gcc_assert ( param_size >= 0 ) ; param_size = ( UNITS_PER_WORD - 1 + param_size ) / UNITS_PER_WORD ; if ( cum -> regs_used + param_size > NUM_ARG_REGS ) cum -> regs_used = NUM_ARG_REGS ; else cum -> regs_used += param_size ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE ; TYPE is null for libcalls where that information may not be available .


<s> Value * X86TargetLowering :: getIRStackGuard ( IRBuilder < > & IRB ) const { if ( hasStackGuardSlotTLS ( Subtarget . getTargetTriple ( ) ) ) { if ( Subtarget . isTargetFuchsia ( ) ) { return SegmentOffset ( IRB , 0x10 , getAddressSpace ( ) ) ; } else { unsigned AddressSpace = getAddressSpace ( ) ; int Offset = getTargetMachine ( ) . Options . StackProtectorGuardOffset ; if ( Offset == INT_MAX ) Offset = ( Subtarget . is64Bit ( ) ) ? 0x28 : 0x14 ; const auto & GuardReg = getTargetMachine ( ) . Options . StackProtectorGuardReg ; if ( GuardReg == "fs" ) AddressSpace = X86AS :: FS ; else if ( GuardReg == "gs" ) AddressSpace = X86AS :: GS ; return SegmentOffset ( IRB , Offset , AddressSpace ) ; } } return TargetLowering :: getIRStackGuard ( IRB ) ; } </s>

If the target has a standard location for the stack protector cookie , returns the address of that location .


<s> SDValue MipsSelectionDAGInfo :: EmitTargetCodeForMemmove ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , bool MustPreserveCheriCapabilities , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { return EmitTargetCodeForMemOp ( DAG , dl , Chain , Dst , Src , Size , Alignment , isVolatile , false , MustPreserveCheriCapabilities , DstPtrInfo , SrcPtrInfo , false ) ; } </s>

Emit target-specific code that performs a memmove .


<s> unsigned PPCInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case PPC :: LD : case PPC :: LWZ : case PPC :: LFS : case PPC :: LFD : case PPC :: RESTORE_CR : case PPC :: LVX : case PPC :: RESTORE_VRSAVE : if ( MI -> getOperand ( 1 ) . isImm ( ) && ! MI -> getOperand ( 1 ) . getImm ( ) && MI -> getOperand ( 2 ) . isFI ( ) ) { FrameIndex = MI -> getOperand ( 2 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s>
void
RISCVAsmBackend
::
relaxInstruction
(
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
)
const
{
MCInst
Res
;
switch
(
Inst
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Opcode not expected!"
)
;
case
RISCV
::
C_BEQZ
:
Res
.
setOpcode
(
RISCV
::
BEQ
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
Res
.
addOperand
(
MCOperand
::
createReg
(
RISCV
::
X0
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
1
)
)
;
break
;
case
RISCV
::
C_BNEZ
:
Res
.
setOpcode
(
RISCV
::
BNE
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
Res
.
addOperand
(
MCOperand
::
createReg
(
RISCV
::
X0
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
1
)
)
;
break
;
case
RISCV
::
C_J
:
Res
.
setOpcode
(
RISCV
::
JAL
)
;
Res
.
addOperand
(
MCOperand
::
createReg
(
RISCV
::
X0
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
break
;
case
RISCV
::
C_JAL
:
Res
.
setOpcode
(
RISCV
::
JAL
)
;
Res
.
addOperand
(
MCOperand
::
createReg
(
RISCV
::
X1
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
break
;
}
Inst
=
std
::
move
(
Res
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & getSubtargetImpl ( ) -> getInstrItineraryData ( ) ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s>
bool
TVMArgumentMove
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
LLVM_DEBUG
(
{
dbgs
(
)
<<
"********** Argument Move **********\n"
<<
"********** Function: "
<<
MF
.
getName
(
)
<<
'\n'
;
}
)
;
bool
Changed
=
false
;
MachineBasicBlock
&
EntryMBB
=
MF
.
front
(
)
;
MachineBasicBlock
::
iterator
InsertPt
=
EntryMBB
.
end
(
)
;
for
(
MachineInstr
&
MI
:
EntryMBB
)
{
if
(
!
TVM
::
isArgument
(
MI
)
)
{
InsertPt
=
MI
;
break
;
}
}
for
(
MachineInstr
&
MI
:
llvm
::
make_range
(
InsertPt
,
EntryMBB
.
end
(
)
)
)
{
if
(
TVM
::
isArgument
(
MI
)
)
{
EntryMBB
.
insert
(
InsertPt
,
MI
.
removeFromParent
(
)
)
;
Changed
=
true
;
}
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

TVM
TVM
"********** Argument Move **********\n"
"********** Function: "
TVM::isArgument
TVM::isArgument


<s> void c6x_final_prescan_insn ( rtx_insn * insn , rtx * opvec ATTRIBUTE_UNUSED , int noperands ATTRIBUTE_UNUSED ) { c6x_current_insn = insn ; } </s>


<s> SDValue HexagonTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SmallVectorImpl < SDValue > & OutVals , SDValue Callee ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_Hexagon ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static bool backward_propagate_worthwhile_p ( const basic_block cfg_bb , const vector_block_info block_info ) { if ( loop_basic_block_p ( cfg_bb ) ) { if ( block_info . reaching_out . valid_or_dirty_p ( ) ) { if ( block_info . local_dem . compatible_p ( block_info . reaching_out ) ) { return true ; } else { if ( support_relaxed_compatible_p ( block_info . reaching_out , block_info . local_dem ) ) return true ; return false ; } } else { gcc_assert ( block_info . reaching_out . unknown_p ( ) ) ; return false ; } } return true ; } </s>

Return true if the block is worthwhile backward propagation .


"FPDelta isn't aligned per the Win64 ABI!"

"VLAs and dynamic stack realign, but no FP?!"

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> static bool isEqual ( const TOCKey & A , const TOCKey & B ) { return A == B ; } </s>

isEqual - Compares two trees for structural equality and returns true if they are equal .


<s> bool SITargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return ( GA -> getAddressSpace ( ) == AMDGPUAS :: GLOBAL_ADDRESS || GA -> getAddressSpace ( ) == AMDGPUAS :: CONSTANT_ADDRESS ) && ! shouldEmitGOTReloc ( GA -> getGlobal ( ) ) ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


Create a TOC reference for symbol_ref SYMBOL . If LARGETOC_REG is non-null , use that as the register to put the HIGH value into if register allocation is already done .


<s> bool isMaskAndCmp0FoldingBeneficial ( const Instruction & AndI ) const override { ConstantInt * Mask = dyn_cast < ConstantInt > ( AndI . getOperand ( 1 ) ) ; return Mask && Mask -> getValue ( ) . isIntN ( 16 ) ; } </s>

Return if the target supports combining a chain like :


<s> void CSKYInstPrinter :: printRegName ( raw_ostream & O , unsigned RegNo ) const { O << getRegisterName ( RegNo ) ; } </s>


<s> bool X86TargetLowering :: isTruncateFree ( const Type * Ty1 , const Type * Ty2 ) const { if ( ! Ty1 -> isIntegerTy ( ) || ! Ty2 -> isIntegerTy ( ) ) return false ; unsigned NumBits1 = Ty1 -> getPrimitiveSizeInBits ( ) ; unsigned NumBits2 = Ty2 -> getPrimitiveSizeInBits ( ) ; if ( NumBits1 <= NumBits2 ) return false ; return true ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook .


<s> virtual const OR1KInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s>
bool
SystemZAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
applyMnemonicAliases
(
Name
,
getAvailableFeatures
(
)
,
0
)
;
Operands
.
push_back
(
SystemZOperand
::
createToken
(
Name
,
NameLoc
)
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
parseOperand
(
Operands
,
Name
)
)
{
return
true
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
)
{
return
true
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

SystemZ
SystemZ
0
SystemZ
"unexpected token in argument list"


<s> StackOffset ( const StackOffset & Other ) : Bytes ( Other . Bytes ) , ScalableBytes ( Other . ScalableBytes ) { } </s>


<s> void VEFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const VEMachineFunctionInfo * FuncInfo = MF . getInfo < VEMachineFunctionInfo > ( ) ; DebugLoc DL ; MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const VEInstrInfo & TII = * STI . getInstrInfo ( ) ; uint64_t NumBytes = MFI . getStackSize ( ) ; if ( ! FuncInfo -> isLeafProc ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( VE :: ORri ) , VE :: SX11 ) . addReg ( VE :: SX9 ) . addImm ( 0 ) ; } else { emitSPAdjustment ( MF , MBB , MBBI , NumBytes , None ) ; } emitEpilogueInsns ( MF , MBB , MBBI , NumBytes , true ) ; } </s>

VE VE VE VE VE VE::ORri VE::SX11 VE::SX9 0


<s> static bool nds32_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { return ( ! TARGET_V3PUSH && ( cfun -> machine -> va_args_size == 0 ) && decl ) ; } </s>

Return true if it is ok to do sibling call optimization .


<s> static bool timode_mem_p ( rtx x ) { return MEM_P ( x ) && ( TARGET_SSE_UNALIGNED_LOAD_OPTIMAL || ! misaligned_operand ( x , TImode ) ) ; } </s>

Check for a suitable TImode memory operand .


<s> bool GCNDownwardRPTracker :: advance ( MachineBasicBlock :: const_iterator Begin , MachineBasicBlock :: const_iterator End , const LiveRegSet * LiveRegsCopy ) { reset ( * Begin , LiveRegsCopy ) ; return advance ( End ) ; } </s>

Advance across the current instruction .


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( AFI -> getGlobalBaseReg ( ) == 0 ) return false ; const ARMTargetMachine * TM = static_cast < const ARMTargetMachine * > ( & MF . getTarget ( ) ) ; if ( TM -> getRelocationModel ( ) != Reloc :: PIC_ ) return false ; LLVMContext * Context = & MF . getFunction ( ) -> getContext ( ) ; GlobalValue * GV = new GlobalVariable ( Type :: getInt32Ty ( * Context ) , false , GlobalValue :: ExternalLinkage , 0 , "_GLOBAL_OFFSET_TABLE_" ) ; unsigned Id = AFI -> createPICLabelUId ( ) ; ARMConstantPoolValue * CPV = ARMConstantPoolConstant :: Create ( GV , Id ) ; unsigned Align = TM -> getDataLayout ( ) -> getPrefTypeAlignment ( GV -> getType ( ) ) ; unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; unsigned Opc = TM -> getSubtarget < ARMSubtarget > ( ) . isThumb2 ( ) ? ARM :: t2LDRpci : ARM :: LDRcp ; const TargetInstrInfo & TII = * TM -> getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == ARM :: LDRcp ) MIB . addImm ( 0 ) ; AddDefaultPred ( MIB ) ; return true ; } </s>

ARM ARM ARM 0 ARM ARM 0 "_GLOBAL_OFFSET_TABLE_" ARM ARM ARM ARM::t2LDRpci ARM::LDRcp ARM::LDRcp 0


<s> void HexagonDAGToDAGISel :: Select ( SDNode * N ) { if ( N -> isMachineOpcode ( ) ) return N -> setNodeId ( - 1 ) ; switch ( N -> getOpcode ( ) ) { case ISD :: Constant : return SelectConstant ( N ) ; case ISD :: ConstantFP : return SelectConstantFP ( N ) ; case ISD :: FrameIndex : return SelectFrameIndex ( N ) ; case ISD :: SHL : return SelectSHL ( N ) ; case ISD :: LOAD : return SelectLoad ( N ) ; case ISD :: STORE : return SelectStore ( N ) ; case ISD :: INTRINSIC_W_CHAIN : return SelectIntrinsicWChain ( N ) ; case ISD :: INTRINSIC_WO_CHAIN : return SelectIntrinsicWOChain ( N ) ; case HexagonISD :: VALIGN : return SelectVAlign ( N ) ; case HexagonISD :: VALIGNADDR : return SelectVAlignAddr ( N ) ; case HexagonISD :: TYPECAST : return SelectTypecast ( N ) ; case HexagonISD :: P2D : return SelectP2D ( N ) ; case HexagonISD :: D2P : return SelectD2P ( N ) ; case HexagonISD :: Q2V : return SelectQ2V ( N ) ; case HexagonISD :: V2Q : return SelectV2Q ( N ) ; } if ( HST -> useHVXOps ( ) ) { switch ( N -> getOpcode ( ) ) { case ISD :: VECTOR_SHUFFLE : return SelectHvxShuffle ( N ) ; case HexagonISD :: VROR : return SelectHvxRor ( N ) ; } } SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> unsigned getNumFixupKinds ( ) const { return X86 :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


Worker function for TARGET_FUNCTION_VALUE . On the H8 the return value is in R0/R1 .


<s> void h8300_expand_branch ( enum rtx_code code , rtx label ) { rtx tmp ; tmp = gen_rtx_fmt_ee ( code , VOIDmode , cc0_rtx , const0_rtx ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , tmp ) ) ; } </s>


<s>
static
void
pru_print_operand_address
(
FILE
*
file
,
machine_mode
mode
,
rtx
op
)
{
if
(
CONSTANT_ADDRESS_P
(
op
)
&&
text_segment_operand
(
op
,
VOIDmode
)
)
{
output_operand_lossage
(
"unexpected text address:"
)
;
return
;
}
switch
(
GET_CODE
(
op
)
)
{
case
CONST
:
case
LABEL_REF
:
case
CONST_WIDE_INT
:
case
SYMBOL_REF
:
break
;
case
CONST_INT
:
{
unsigned
HOST_WIDE_INT
caddr
=
INTVAL
(
op
)
;
int
base
=
pru_get_ctable_base_index
(
caddr
)
;
int
offs
=
pru_get_ctable_base_offset
(
caddr
)
;
if
(
base
<
0
)
{
output_operand_lossage
(
"unsupported constant address:"
)
;
return
;
}
fprintf
(
file
,
"%d, %d"
,
base
,
offs
)
;
return
;
}
break
;
case
PLUS
:
{
int
base
;
rtx
op0
=
XEXP
(
op
,
0
)
;
rtx
op1
=
XEXP
(
op
,
1
)
;
if
(
REG_P
(
op0
)
&&
CONST_INT_P
(
op1
)
&&
pru_get_ctable_exact_base_index
(
INTVAL
(
op1
)
)
>=
0
)
{
base
=
pru_get_ctable_exact_base_index
(
INTVAL
(
op1
)
)
;
fprintf
(
file
,
"%d, %s"
,
base
,
pru_asm_regname
(
op0
)
)
;
return
;
}
else
if
(
REG_P
(
op1
)
&&
CONST_INT_P
(
op0
)
&&
pru_get_ctable_exact_base_index
(
INTVAL
(
op0
)
)
>=
0
)
{
gcc_unreachable
(
)
;
}
else
if
(
REG_P
(
op0
)
&&
CONSTANT_P
(
op1
)
)
{
fprintf
(
file
,
"%s, "
,
pru_asm_regname
(
op0
)
)
;
output_addr_const
(
file
,
op1
)
;
return
;
}
else
if
(
REG_P
(
op1
)
&&
CONSTANT_P
(
op0
)
)
{
gcc_unreachable
(
)
;
}
else
if
(
REG_P
(
op1
)
&&
REG_P
(
op0
)
)
{
fprintf
(
file
,
"%s, %s"
,
pru_asm_regname
(
op0
)
,
pru_asm_regname
(
op1
)
)
;
return
;
}
}
break
;
case
REG
:
fprintf
(
file
,
"%s, 0"
,
pru_asm_regname
(
op
)
)
;
return
;
case
MEM
:
{
rtx
base
=
XEXP
(
op
,
0
)
;
pru_print_operand_address
(
file
,
mode
,
base
)
;
return
;
}
default
:
break
;
}
output_operand_lossage
(
"unsupported memory expression:"
)
;
}
</s>


<s> void MipsTargetStreamer :: emitGPRestore ( int Offset , SMLoc IDLoc , const MCSubtargetInfo * STI ) { emitLoadWithImmOffset ( Mips :: LW , GPReg , Mips :: SP , Offset , GPReg , IDLoc , STI ) ; } </s>

Emit the $ gp restore operation for .cprestore .


<s> unsigned getNumBlocks ( ) const override { return Region -> getNumBlocks ( ) ; } </s>

Get the number of blocks in this loop in constant time .


<s> bool MBlazeFrameInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool X86TargetLowering :: isVectorShiftByScalarCheap ( Type * Ty ) const { unsigned Bits = Ty -> getScalarSizeInBits ( ) ; if ( Bits == 8 ) return false ; if ( Subtarget . hasXOP ( ) && Ty -> getPrimitiveSizeInBits ( ) == 128 && ( Bits == 8 || Bits == 16 || Bits == 32 || Bits == 64 ) ) return false ; if ( Subtarget . hasAVX2 ( ) && ( Bits == 32 || Bits == 64 ) ) return false ; if ( Subtarget . hasBWI ( ) && Bits == 16 ) return false ; return true ; } </s>

This is used to enable splatted operand transforms for vector shifts and vector funnel shifts .