<s> static rtx ix86_expand_sse_comi ( const struct builtin_description * d , tree exp , rtx target ) { rtx pat , set_dst ; tree arg0 = CALL_EXPR_ARG ( exp , 0 ) ; tree arg1 = CALL_EXPR_ARG ( exp , 1 ) ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; enum insn_code icode = d -> icode ; const struct insn_data_d * insn_p = & insn_data [ icode ] ; machine_mode mode0 = insn_p -> operand [ 0 ] . mode ; machine_mode mode1 = insn_p -> operand [ 1 ] . mode ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; enum rtx_code comparison = d -> comparison ; rtx const_val = const0_rtx ; bool check_unordered = false ; machine_mode mode = CCFPmode ; switch ( comparison ) { case LE : case LT : std :: swap ( op0 , op1 ) ; comparison = swap_condition ( comparison ) ; case GT : case GE : break ; case EQ : check_unordered = true ; mode = CCZmode ; break ; case NE : check_unordered = true ; mode = CCZmode ; const_val = const1_rtx ; break ; default : gcc_unreachable ( ) ; } target = gen_reg_rtx ( SImode ) ; emit_move_insn ( target , const_val ) ; target = gen_rtx_SUBREG ( QImode , target , 0 ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! insn_p -> operand [ 0 ] . predicate ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ( optimize && ! register_operand ( op1 , mode1 ) ) || ! insn_p -> operand [ 1 ] . predicate ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( ! pat ) return 0 ; set_dst = SET_DEST ( pat ) ; emit_insn ( pat ) ; return ix86_ssecom_setcc ( comparison , check_unordered , mode , set_dst , target ) ; } </s>

Subroutine of ix86_expand_builtin to take care of comi insns .


<s> bool Mips16InstrInfo :: isCopyInstrImpl ( const MachineInstr & MI , const MachineOperand * & Src , const MachineOperand * & Dest ) const { if ( MI . isMoveReg ( ) ) { Dest = & MI . getOperand ( 0 ) ; Src = & MI . getOperand ( 1 ) ; return true ; } return false ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


<s> unsigned WebAssemblyTTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args , const Instruction * CxtI ) { unsigned Cost = BasicTTIImplBase < WebAssemblyTTIImpl > :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( auto * VTy = dyn_cast < VectorType > ( Ty ) ) { switch ( Opcode ) { case Instruction :: LShr : case Instruction :: AShr : case Instruction :: Shl : if ( Opd2Info != TTI :: OK_UniformValue && Opd2Info != TTI :: OK_UniformConstantValue ) Cost = VTy -> getNumElements ( ) * ( TargetTransformInfo :: TCC_Basic + getArithmeticInstrCost ( Opcode , VTy -> getElementType ( ) ) + TargetTransformInfo :: TCC_Basic ) ; break ; } } return Cost ; } </s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> bool aarch64_operands_ok_for_ldpstp ( rtx * operands , bool load , enum machine_mode mode ) { HOST_WIDE_INT offval_1 , offval_2 , msize ; enum reg_class rclass_1 , rclass_2 ; rtx mem_1 , mem_2 , reg_1 , reg_2 , base_1 , base_2 , offset_1 , offset_2 ; if ( load ) { mem_1 = operands [ 1 ] ; mem_2 = operands [ 3 ] ; reg_1 = operands [ 0 ] ; reg_2 = operands [ 2 ] ; gcc_assert ( REG_P ( reg_1 ) && REG_P ( reg_2 ) ) ; if ( REGNO ( reg_1 ) == REGNO ( reg_2 ) ) return false ; } else { mem_1 = operands [ 0 ] ; mem_2 = operands [ 2 ] ; reg_1 = operands [ 1 ] ; reg_2 = operands [ 3 ] ; } if ( MEM_VOLATILE_P ( mem_1 ) || MEM_VOLATILE_P ( mem_2 ) ) return false ; if ( mode == SImode && ( aarch64_tune_params . extra_tuning_flags & AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW ) && ! optimize_size && MEM_ALIGN ( mem_1 ) < 8 * BITS_PER_UNIT ) return false ; extract_base_offset_in_addr ( mem_1 , & base_1 , & offset_1 ) ; if ( base_1 == NULL_RTX || offset_1 == NULL_RTX ) return false ; extract_base_offset_in_addr ( mem_2 , & base_2 , & offset_2 ) ; if ( base_2 == NULL_RTX || offset_2 == NULL_RTX ) return false ; if ( ! rtx_equal_p ( base_1 , base_2 ) ) return false ; offval_1 = INTVAL ( offset_1 ) ; offval_2 = INTVAL ( offset_2 ) ; msize = GET_MODE_SIZE ( mode ) ; if ( offval_1 != ( offval_2 + msize ) && offval_2 != ( offval_1 + msize ) ) return false ; if ( load ) { if ( reg_mentioned_p ( reg_1 , mem_1 ) ) return false ; if ( offval_1 > offval_2 && reg_mentioned_p ( reg_2 , mem_2 ) ) return false ; } if ( REG_P ( reg_1 ) && FP_REGNUM_P ( REGNO ( reg_1 ) ) ) rclass_1 = FP_REGS ; else rclass_1 = GENERAL_REGS ; if ( REG_P ( reg_2 ) && FP_REGNUM_P ( REGNO ( reg_2 ) ) ) rclass_2 = FP_REGS ; else rclass_2 = GENERAL_REGS ; if ( rclass_1 != rclass_2 ) return false ; return true ; } </s>

Given OPERANDS of consecutive load/store , check if we can merge them into ldp/stp . LOAD is true if they are load instructions . MODE is the mode of memory operands .


<s> bool PPCCTRLoops :: isDead ( const MachineInstr * MI , SmallVector < MachineInstr * , 1 > & DeadPhis ) const { for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDef ( ) ) { unsigned Reg = MO . getReg ( ) ; if ( ! MRI -> use_nodbg_empty ( Reg ) ) { MachineRegisterInfo :: use_iterator I = MRI -> use_begin ( Reg ) ; if ( llvm :: next ( I ) == MRI -> use_end ( ) && I . getOperand ( ) . getParent ( ) -> isPHI ( ) ) { MachineInstr * OnePhi = I . getOperand ( ) . getParent ( ) ; for ( unsigned j = 0 , f = OnePhi -> getNumOperands ( ) ; j != f ; ++ j ) { const MachineOperand & OPO = OnePhi -> getOperand ( j ) ; if ( OPO . isReg ( ) && OPO . isDef ( ) ) { unsigned OPReg = OPO . getReg ( ) ; MachineRegisterInfo :: use_iterator nextJ ; for ( MachineRegisterInfo :: use_iterator J = MRI -> use_begin ( OPReg ) , E = MRI -> use_end ( ) ; J != E ; J = nextJ ) { nextJ = llvm :: next ( J ) ; MachineOperand & Use = J . getOperand ( ) ; MachineInstr * UseMI = Use . getParent ( ) ; if ( MI != UseMI ) { return false ; } } } } DeadPhis . push_back ( OnePhi ) ; } else { return false ; } } } } return true ; } </s>

isDead - Returns true if this is a dead def kill slot .


<s>
static
rtx
gen_float_relational
(
enum
rtx_code
test_code
,
rtx
cmp0
,
rtx
cmp1
)
{
rtx
(
*
gen_fn
)
(
rtx
,
rtx
,
rtx
)
;
rtx
brtmp
;
int
reverse_regs
,
invert
;
switch
(
test_code
)
{
case
EQ
:
reverse_regs
=
0
;
invert
=
0
;
gen_fn
=
gen_seq_sf
;
break
;
case
NE
:
reverse_regs
=
0
;
invert
=
1
;
gen_fn
=
gen_seq_sf
;
break
;
case
LE
:
reverse_regs
=
0
;
invert
=
0
;
gen_fn
=
gen_sle_sf
;
break
;
case
GT
:
reverse_regs
=
1
;
invert
=
0
;
gen_fn
=
gen_slt_sf
;
break
;
case
LT
:
reverse_regs
=
0
;
invert
=
0
;
gen_fn
=
gen_slt_sf
;
break
;
case
GE
:
reverse_regs
=
1
;
invert
=
0
;
gen_fn
=
gen_sle_sf
;
break
;
default
:
fatal_insn
(
"bad test"
,
gen_rtx_fmt_ee
(
test_code
,
VOIDmode
,
cmp0
,
cmp1
)
)
;
reverse_regs
=
0
;
invert
=
0
;
gen_fn
=
0
;
}
if
(
reverse_regs
)
{
rtx
temp
=
cmp0
;
cmp0
=
cmp1
;
cmp1
=
temp
;
}
brtmp
=
gen_rtx_REG
(
CCmode
,
FPCC_REGNUM
)
;
emit_insn
(
gen_fn
(
brtmp
,
cmp0
,
cmp1
)
)
;
return
gen_rtx_fmt_ee
(
invert
EQ
:
NE
,
VOIDmode
,
brtmp
,
const0_rtx
)
;
}
</s>

Generate the code to compare two float values . The return value is the comparison expression .


<s> Align SITargetLowering :: computeKnownAlignForTargetInstr ( GISelKnownBits & KB , Register R , const MachineRegisterInfo & MRI , unsigned Depth ) const { const MachineInstr * MI = MRI . getVRegDef ( R ) ; switch ( MI -> getOpcode ( ) ) { case AMDGPU :: G_INTRINSIC : case AMDGPU :: G_INTRINSIC_W_SIDE_EFFECTS : { Intrinsic :: ID IID = MI -> getIntrinsicID ( ) ; LLVMContext & Ctx = KB . getMachineFunction ( ) . getFunction ( ) . getContext ( ) ; AttributeList Attrs = Intrinsic :: getAttributes ( Ctx , IID ) ; if ( MaybeAlign RetAlign = Attrs . getRetAlignment ( ) ) return * RetAlign ; return Align ( 1 ) ; } default : return Align ( 1 ) ; } } </s>

Determine the known alignment for the pointer value R .


<s> static void sh_function_arg_advance ( cumulative_args_t ca_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * ca = get_cumulative_args ( ca_v ) ; if ( ca -> force_mem ) ca -> force_mem = false ; if ( ( TARGET_HITACHI || ca -> renesas_abi ) && TARGET_FPU_DOUBLE ) { if ( arg . mode == SFmode && ca -> free_single_fp_reg ) { ca -> free_single_fp_reg = 0 ; return ; } if ( arg . mode == DFmode && sh_round_reg ( * ca , DFmode ) != sh_round_reg ( * ca , SFmode ) ) { ca -> free_single_fp_reg = ( sh_round_reg ( * ca , SFmode ) + BASE_ARG_REG ( arg . mode ) ) ; } } if ( ! ( ( TARGET_SH4 || TARGET_SH2A ) || ca -> renesas_abi ) || sh_pass_in_reg_p ( * ca , arg . mode , arg . type ) ) ( ca -> arg_count [ ( int ) get_sh_arg_class ( arg . mode ) ] = ( sh_round_reg ( * ca , arg . mode ) + CEIL ( arg . promoted_size_in_bytes ( ) , UNITS_PER_WORD ) ) ) ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> void get_aligned_mem ( rtx ref , rtx * paligned_mem , rtx * pbitnum ) { rtx base ; HOST_WIDE_INT disp , offset ; gcc_assert ( GET_CODE ( ref ) == MEM ) ; if ( reload_in_progress && ! memory_address_p ( GET_MODE ( ref ) , XEXP ( ref , 0 ) ) ) { base = find_replacement ( & XEXP ( ref , 0 ) ) ; gcc_assert ( memory_address_p ( GET_MODE ( ref ) , base ) ) ; } else base = XEXP ( ref , 0 ) ; if ( GET_CODE ( base ) == PLUS ) disp = INTVAL ( XEXP ( base , 1 ) ) , base = XEXP ( base , 0 ) ; else disp = 0 ; if ( MEM_ALIGN ( ref ) >= 32 ) offset = 0 ; else offset = disp & 3 ; * paligned_mem = widen_memory_access ( ref , SImode , - offset ) ; if ( WORDS_BIG_ENDIAN ) offset = 32 - ( GET_MODE_BITSIZE ( GET_MODE ( ref ) ) + offset * 8 ) ; else offset *= 8 ; * pbitnum = GEN_INT ( offset ) ; } </s>

REF is an alignable memory location . Place an aligned SImode reference into * PALIGNED_MEM and the number of bits to shift into * PBITNUM . SCRATCH is a free register for use in reloading out of range stack slots .


<s> static rtx mep_frame_expr ( rtx_insn * insn ) { rtx note , expr ; note = find_reg_note ( insn , REG_FRAME_RELATED_EXPR , 0 ) ; expr = ( note != 0 ? XEXP ( note , 0 ) : copy_rtx ( PATTERN ( insn ) ) ) ; RTX_FRAME_RELATED_P ( expr ) = 1 ; return expr ; } </s>

Return the effect of frame-related instruction INSN .


<s> bool X86InstrInfo :: getMemOperandWithOffset ( const MachineInstr & MemOp , const MachineOperand * & BaseOp , int64_t & Offset , const TargetRegisterInfo * TRI ) const { const MCInstrDesc & Desc = MemOp . getDesc ( ) ; int MemRefBegin = X86II :: getMemoryOperandNo ( Desc . TSFlags ) ; if ( MemRefBegin < 0 ) return false ; MemRefBegin += X86II :: getOperandBias ( Desc ) ; BaseOp = & MemOp . getOperand ( MemRefBegin + X86 :: AddrBaseReg ) ; if ( ! BaseOp -> isReg ( ) ) return false ; if ( MemOp . getOperand ( MemRefBegin + X86 :: AddrScaleAmt ) . getImm ( ) != 1 ) return false ; if ( MemOp . getOperand ( MemRefBegin + X86 :: AddrIndexReg ) . getReg ( ) != X86 :: NoRegister ) return false ; const MachineOperand & DispMO = MemOp . getOperand ( MemRefBegin + X86 :: AddrDisp ) ; if ( ! DispMO . isImm ( ) ) return false ; Offset = DispMO . getImm ( ) ; if ( ! BaseOp -> isReg ( ) ) return false ; return true ; } </s>

Get the base operand and byte offset of an instruction that reads/writes memory .


<s> void XCoreFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; XCoreFunctionInfo * XFI = MF . getInfo < XCoreFunctionInfo > ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool LRUsed = MRI . isPhysRegModified ( XCore :: LR ) ; if ( ! LRUsed && ! MF . getFunction ( ) . isVarArg ( ) && MF . getFrameInfo ( ) . estimateStackSize ( MF ) ) LRUsed = true ; if ( MF . callsUnwindInit ( ) || MF . callsEHReturn ( ) ) { XFI -> createEHSpillSlot ( MF ) ; LRUsed = true ; } if ( LRUsed ) { SavedRegs . reset ( XCore :: LR ) ; XFI -> createLRSpillSlot ( MF ) ; } if ( hasFP ( MF ) ) XFI -> createFPSpillSlot ( MF ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .

XCore XCore XCore XCore XCore::LR XCore::LR


<s> int avr_initial_elimination_offset ( int from , int to ) { if ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) return 0 ; else { int offset = frame_pointer_needed ? 2 : 0 ; int avr_pc_size = AVR_HAVE_EIJMP_EICALL ? 3 : 2 ; offset += avr_regs_to_save ( NULL ) ; return ( get_frame_size ( ) + avr_outgoing_args_size ( ) + avr_pc_size + 1 + offset ) ; } } </s>

Compute offset between arg_pointer and frame_pointer .


<s> static void aarch64_save_callee_saves ( machine_mode mode , poly_int64 start_offset , unsigned start , unsigned limit , bool skip_wb ) { rtx_insn * insn ; unsigned regno ; unsigned regno2 ; for ( regno = aarch64_next_callee_save ( start , limit ) ; regno <= limit ; regno = aarch64_next_callee_save ( regno + 1 , limit ) ) { rtx reg , mem ; poly_int64 offset ; if ( skip_wb && ( regno == cfun -> machine -> frame . wb_candidate1 || regno == cfun -> machine -> frame . wb_candidate2 ) ) continue ; if ( cfun -> machine -> reg_is_wrapped_separately [ regno ] ) continue ; reg = gen_rtx_REG ( mode , regno ) ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno ] ; mem = gen_frame_mem ( mode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; regno2 = aarch64_next_callee_save ( regno + 1 , limit ) ; if ( regno2 <= limit && ! cfun -> machine -> reg_is_wrapped_separately [ regno2 ] && ( ( cfun -> machine -> frame . reg_offset [ regno ] + UNITS_PER_WORD ) == cfun -> machine -> frame . reg_offset [ regno2 ] ) ) { rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; rtx mem2 ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno2 ] ; mem2 = gen_frame_mem ( mode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; insn = emit_insn ( aarch64_gen_store_pair ( mode , mem , reg , mem2 , reg2 ) ) ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , 0 , 1 ) ) = 1 ; regno = regno2 ; } else insn = emit_move_insn ( mem , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } </s>

Emit code to save the callee-saved registers from register number START to LIMIT to the stack at the location starting at offset START_OFFSET , skipping any write-back candidates if SKIP_WB is true .


<s> static bool pa_callee_copies ( cumulative_args_t , const function_arg_info & ) { return ! TARGET_CALLER_COPIES ; } </s>

Implement TARGET_CALLEE_COPIES . The callee is responsible for copying arguments passed by hidden reference in the 32-bit HP runtime . Users can override this behavior for better compatibility with openmp at the risk of library incompatibilities . Arguments are always passed by value in the 64-bit HP runtime .


<s> void arm_expand_vcond ( rtx * operands , machine_mode cmp_result_mode ) { rtx mask ; if ( TARGET_HAVE_MVE ) mask = gen_reg_rtx ( arm_mode_to_pred_mode ( cmp_result_mode ) . require ( ) ) ; else mask = gen_reg_rtx ( cmp_result_mode ) ; bool inverted = arm_expand_vector_compare ( mask , GET_CODE ( operands [ 3 ] ) , operands [ 4 ] , operands [ 5 ] , true ) ; if ( inverted ) std :: swap ( operands [ 1 ] , operands [ 2 ] ) ; if ( TARGET_NEON ) emit_insn ( gen_neon_vbsl ( GET_MODE ( operands [ 0 ] ) , operands [ 0 ] , mask , operands [ 1 ] , operands [ 2 ] ) ) ; else { machine_mode cmp_mode = GET_MODE ( operands [ 0 ] ) ; switch ( GET_MODE_CLASS ( cmp_mode ) ) { case MODE_VECTOR_INT : emit_insn ( gen_mve_vpselq ( VPSELQ_S , cmp_mode , operands [ 0 ] , operands [ 1 ] , operands [ 2 ] , mask ) ) ; break ; case MODE_VECTOR_FLOAT : if ( TARGET_HAVE_MVE_FLOAT ) emit_insn ( gen_mve_vpselq_f ( cmp_mode , operands [ 0 ] , operands [ 1 ] , operands [ 2 ] , mask ) ) ; else gcc_unreachable ( ) ; break ; default : gcc_unreachable ( ) ; } } } </s>

Expand a vcond or vcondu pattern with operands OPERANDS . CMP_RESULT_MODE is the mode of the comparison result .


<s> static bool s390_can_eliminate ( const int from , const int to ) { if ( from == BASE_REGNUM && to == BASE_REGNUM ) { if ( TARGET_CPU_ZARCH ) { s390_init_frame_layout ( ) ; return cfun -> machine -> base_reg == NULL_RTX ; } return false ; } gcc_assert ( to == STACK_POINTER_REGNUM || to == HARD_FRAME_POINTER_REGNUM ) ; gcc_assert ( from == FRAME_POINTER_REGNUM || from == ARG_POINTER_REGNUM || from == RETURN_ADDRESS_POINTER_REGNUM ) ; if ( from == RETURN_ADDRESS_POINTER_REGNUM ) if ( ! crtl -> calls_eh_return && ! cfun -> stdarg && ! cfun_frame_layout . save_return_addr_p ) return false ; return true ; } </s>

Return true if register FROM can be eliminated via register TO .


<s> static rtx_insn * avr_parallel_insn_from_insns ( rtx_insn * i [ 5 ] ) { rtvec vec = gen_rtvec ( 5 , PATTERN ( i [ 0 ] ) , PATTERN ( i [ 1 ] ) , PATTERN ( i [ 2 ] ) , PATTERN ( i [ 3 ] ) , PATTERN ( i [ 4 ] ) ) ; start_sequence ( ) ; emit ( gen_rtx_PARALLEL ( VOIDmode , vec ) ) ; rtx_insn * insn = get_insns ( ) ; end_sequence ( ) ; return insn ; } </s>

Make one parallel insn with all the patterns from insns i [ 0 ] .. i [ 5 ] .


<s> const ARMSubtarget * ARMBaseTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . hasFnAttribute ( "use-soft-float" ) && F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < ARMSubtarget > ( TargetTriple , CPU , FS , * this , isLittle ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

ARM ARM ARM "target-cpu" "target-features" "use-soft-float" "use-soft-float" "true" "+soft-float" ",+soft-float" ARM


<s> const ARMSubtarget * ARMBaseTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < ARMSubtarget > ( TargetTriple , CPU , FS , * this , isLittle ) ; } return I . get ( ) ; } </s>

ARM ARM ARM "target-cpu" "target-features" "use-soft-float" "true" "+soft-float" ",+soft-float" ARM


<s>
bool
SystemZDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_Q
:
case
InlineAsm
::
Constraint_R
:
case
InlineAsm
::
Constraint_S
:
case
InlineAsm
::
Constraint_T
:
SDValue
Base
,
Disp
,
Index
;
if
(
selectBDXAddr
(
SystemZAddressingMode
::
FormBD
,
SystemZAddressingMode
::
Disp12Only
,
Op
,
Base
,
Disp
,
Index
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Disp
)
;
OutOps
.
push_back
(
Index
)
;
return
false
;
}
break
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .

SystemZ
SystemZ
"Unexpected asm memory constraint"
SystemZAddressingMode::FormBD
SystemZAddressingMode::Disp12Only


<s> static const char * pa_strip_name_encoding ( const char * str ) { str += ( * str == '@' ) ; str += ( * str == '*' ) ; return str ; } </s>

This is sort of inverse to pa_encode_section_info .


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
break
;
case
ISD
::
BIT_CONVERT
:
Res
=
ExpandBIT_CONVERT
(
N
,
DAG
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
Res
=
LowerShift
(
N
,
DAG
,
Subtarget
)
;
break
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

ARM
ARM
"Don't know how to custom expand this!"
ISD::BIT_CONVERT
ISD::SRL
ISD::SRA


<s> bool PPCFunctionInfo :: isLiveInZExt ( Register VReg ) const { for ( const std :: pair < Register , ISD :: ArgFlagsTy > & LiveIn : LiveInAttrs ) if ( LiveIn . first == VReg ) return LiveIn . second . isZExt ( ) ; return false ; } </s>

This function returns true if the specified vreg is a live-in register and zero-extended .


<s> bool isImm ( ) const override { return Kind == k_Immediate ; } </s>


<s> unsigned HexagonTTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * DataTy , const Value * Ptr , bool VariableMask , Align Alignment , TTI :: TargetCostKind CostKind , const Instruction * I ) { return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , CostKind , I ) ; } </s>

Calculate the cost of Gather / Scatter operation .


<s> bool AArch64PassConfig :: addILPOpts ( ) { if ( EnableCCMP ) addPass ( createAArch64ConditionalCompares ( ) ) ; if ( EnableMCR ) addPass ( & MachineCombinerID ) ; if ( EnableEarlyIfConversion ) addPass ( & EarlyIfConverterID ) ; if ( EnableStPairSuppress ) addPass ( createAArch64StorePairSuppressPass ( ) ) ; return true ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .


<s> bool X86TargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty ) const { CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; Reloc :: Model R = getTargetMachine ( ) . getRelocationModel ( ) ; if ( ! X86 :: isOffsetSuitableForCodeModel ( AM . BaseOffs , M , AM . BaseGV != NULL ) ) return false ; if ( AM . BaseGV ) { unsigned GVFlags = Subtarget -> ClassifyGlobalReference ( AM . BaseGV , getTargetMachine ( ) ) ; if ( isGlobalStubReference ( GVFlags ) ) return false ; if ( AM . HasBaseReg && isGlobalRelativeToPICBase ( GVFlags ) ) return false ; if ( ( M != CodeModel :: Small || R != Reloc :: Static ) && Subtarget -> is64Bit ( ) && ( AM . BaseOffs || AM . Scale > 1 ) ) return false ; } switch ( AM . Scale ) { case 0 : case 1 : case 2 : case 4 : case 8 : break ; case 3 : case 5 : case 9 : if ( AM . HasBaseReg ) return false ; break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


"-misched-topdown incompatible with -misched-bottomup"

Initialize the strategy after building the DAG for a new region .


<s>
void
print_operand_address
(
FILE
*
file
,
rtx
addr
)
{
struct
s390_address
ad
;
if
(
!
s390_decompose_address
(
addr
,
&
ad
)
||
(
ad
.
base
&&
!
REG_OK_FOR_BASE_STRICT_P
(
ad
.
base
)
)
||
(
ad
.
indx
&&
!
REG_OK_FOR_INDEX_STRICT_P
(
ad
.
indx
)
)
)
output_operand_lossage
(
"cannot decompose address"
)
;
if
(
ad
.
disp
)
output_addr_const
(
file
,
ad
.
disp
)
;
else
fprintf
(
file
,
"0"
)
;
if
(
ad
.
base
&&
ad
.
indx
)
fprintf
(
file
,
"(%s,%s)"
,
reg_names
[
REGNO
(
ad
.
indx
)
]
,
reg_names
[
REGNO
(
ad
.
base
)
]
)
;
else
if
(
ad
.
base
)
fprintf
(
file
,
"(%s)"
,
reg_names
[
REGNO
(
ad
.
base
)
]
)
;
}
</s>

Print the operand address represented by the rtx addr


<s>
void
BPFInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
BPF
::
GPRRegClass
.
contains
(
DestReg
,
SrcReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
BPF
::
MOV_rr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
</s>

BPF
BPF
BPF::GPRRegClass
BPF::MOV_rr
"Impossible reg-to-reg copy"


<s> unsigned PPCTargetLowering :: getByValTypeAlignment ( Type * Ty ) const { if ( PPCSubTarget . isDarwin ( ) ) return 4 ; unsigned Align = PPCSubTarget . isPPC64 ( ) ? 8 : 4 ; if ( PPCSubTarget . hasAltivec ( ) || PPCSubTarget . hasQPX ( ) ) getMaxByValAlign ( Ty , Align , PPCSubTarget . hasQPX ( ) ? 32 : 16 ) ; return Align ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


<s> const LegalizerInfo * getLegalizerInfo ( ) const override { return nullptr ; } </s>

Expose LegalizerInfo so the clients can re-use .


<s> bool PPCAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; if ( MI -> getOperand ( OpNo ) . isReg ( ) ) printMemRegReg ( MI , OpNo ) ; else printMemRegImm ( MI , OpNo ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s>
void
thumb1_final_prescan_insn
(
rtx_insn
*
insn
)
{
if
(
flag_print_asm_name
)
asm_fprintf
(
asm_out_file
,
"%@ 0x%04x\n"
,
INSN_ADDRESSES
(
INSN_UID
(
insn
)
)
)
;
if
(
INSN_CODE
(
insn
)
!=
CODE_FOR_cbranchsi4_insn
)
{
enum
attr_conds
conds
;
if
(
cfun
->
machine
->
thumb1_cc_insn
)
{
if
(
modified_in_p
(
cfun
->
machine
->
thumb1_cc_op0
,
insn
)
||
modified_in_p
(
cfun
->
machine
->
thumb1_cc_op1
,
insn
)
)
CC_STATUS_INIT
;
}
conds
=
get_attr_conds
(
insn
)
;
if
(
conds
==
CONDS_SET
)
{
rtx
set
=
single_set
(
insn
)
;
cfun
->
machine
->
thumb1_cc_insn
=
insn
;
cfun
->
machine
->
thumb1_cc_op0
=
SET_DEST
(
set
)
;
cfun
->
machine
->
thumb1_cc_op1
=
const0_rtx
;
cfun
->
machine
->
thumb1_cc_mode
=
CC_NZmode
;
if
(
INSN_CODE
(
insn
)
==
CODE_FOR_thumb1_subsi3_insn
)
{
rtx
src1
=
XEXP
(
SET_SRC
(
set
)
,
1
)
;
if
(
src1
==
const0_rtx
)
cfun
->
machine
->
thumb1_cc_mode
=
CCmode
;
}
else
if
(
REG_P
(
SET_DEST
(
set
)
)
&&
REG_P
(
SET_SRC
(
set
)
)
)
{
cfun
->
machine
->
thumb1_cc_op0
=
SET_SRC
(
set
)
;
}
}
else
if
(
conds
!=
CONDS_NOCOND
)
cfun
->
machine
->
thumb1_cc_insn
=
NULL_RTX
;
}
if
(
cfun
->
machine
->
lr_save_eliminated
&&
get_attr_far_jump
(
insn
)
==
FAR_JUMP_YES
)
internal_error
(
"Unexpected thumb1 far jump"
)
;
}
</s>

Scan INSN just before assembler is output for it . For Thumb-1 , we track the status of the condition codes ; this information is used in the cbranchsi4_insn pattern .

arm
"%@ 0x%04x\n"
1
"Unexpected thumb1 far jump"


<s> void emitBasicBlockEnd ( const MachineBasicBlock & MBB ) override { } </s>

Targets can override this to emit stuff at the end of a basic block .


<s> bool systemSupportsUnalignedAccess ( ) const { return hasMips32r6 ( ) ; } </s>

Does the system support unaligned memory access .


"density %d%%, cost %d exceeds threshold, penalizing "

Test for likely overcommitment of vector hardware resources . If a loop iteration is relatively large , and too large a percentage of instructions in the loop are vectorized , the cost model may not adequately reflect delays from unavailable vector resources . Penalize the loop body cost for this case .


<s> bool isToken ( ) const override { return Kind == Token ; } </s>


<s>
bool
VideocoreAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
SmallVectorImpl
<
MCParsedAsmOperand
*
>
&
Operands
)
{
unsigned
CondCode
;
StringRef
Postfix
;
StringRef
Mnemonic
=
splitMnemonic
(
Name
,
CondCode
,
Postfix
)
;
Operands
.
push_back
(
VideocoreOperand
::
createToken
(
Mnemonic
,
NameLoc
)
)
;
if
(
Postfix
!=
""
)
{
Postfix
=
"."
+
Postfix
.
str
(
)
;
Operands
.
push_back
(
VideocoreOperand
::
createToken
(
Postfix
,
NameLoc
)
)
;
}
int
numOperands
=
0
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
parseOperand
(
Operands
,
Mnemonic
)
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
true
;
}
numOperands
++
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Mnemonic
)
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
true
;
}
numOperands
++
;
}
while
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
StringRef
Str
=
getLexer
(
)
.
getTok
(
)
.
getString
(
)
;
Operands
.
push_back
(
VideocoreOperand
::
createToken
(
Str
,
Loc
)
)
;
Parser
.
Lex
(
)
;
}
}
if
(
InstructionIsConditional
(
Mnemonic
,
numOperands
,
Operands
)
)
{
SMLoc
S
=
SMLoc
::
getFromPointer
(
NameLoc
.
getPointer
(
)
+
Mnemonic
.
size
(
)
)
;
SMLoc
E
=
SMLoc
::
getFromPointer
(
NameLoc
.
getPointer
(
)
+
Name
.
size
(
)
)
;
Operands
.
insert
(
Operands
.
begin
(
)
+
1
,
VideocoreOperand
::
createCondCode
(
CondCode
,
S
,
E
)
)
;
}
else
if
(
CondCode
!=
VCCC
::
AL
)
{
SMLoc
Loc
=
SMLoc
::
getFromPointer
(
NameLoc
.
getPointer
(
)
+
Mnemonic
.
size
(
)
)
;
Error
(
Loc
,
"Unexpected Condition Code"
)
;
return
true
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Videocore
Videocore
Videocore
""
"."
Videocore
0
Videocore
1
Videocore
VCCC::AL
"Unexpected Condition Code"


<s> explicit value ( Value * Val , const value_var & v ) { * static_cast < value_var * > ( this ) = v ; llvmVal = Val ; } </s>


<s>
static
X86Operand
*
CreateMem
(
unsigned
SegReg
,
const
MCExpr
*
Disp
,
unsigned
BaseReg
,
unsigned
IndexReg
,
unsigned
Scale
,
SMLoc
StartLoc
,
SMLoc
EndLoc
,
unsigned
Size
=
0
)
{
assert
(
(
SegReg
||
BaseReg
||
IndexReg
)
&&
"Invalid memory operand!"
)
;
assert
(
(
(
Scale
==
1
||
Scale
==
2
||
Scale
==
4
||
Scale
==
8
)
)
&&
"Invalid scale!"
)
;
X86Operand
*
Res
=
new
X86Operand
(
Memory
,
StartLoc
,
EndLoc
)
;
Res
->
Mem
.
SegReg
=
SegReg
;
Res
->
Mem
.
Disp
=
Disp
;
Res
->
Mem
.
BaseReg
=
BaseReg
;
Res
->
Mem
.
IndexReg
=
IndexReg
;
Res
->
Mem
.
Scale
=
Scale
;
Res
->
Mem
.
Size
=
Size
;
return
Res
;
}
</s>


<s>
void
print
(
)
{
if
(
numSymbols
==
0
)
{
for
(
unsigned
i
=
0
;
i
<
size
;
i
++
)
{
if
(
i
)
O
<<
", "
;
O
<<
(
unsigned
int
)
buffer
[
i
]
;
}
}
else
{
unsigned
int
pos
=
0
;
unsigned
int
nSym
=
0
;
unsigned
int
nextSymbolPos
=
symbolPosInBuffer
[
nSym
]
;
unsigned
int
nBytes
=
4
;
if
(
AP
.
nvptxSubtarget
.
is64Bit
(
)
)
nBytes
=
8
;
for
(
pos
=
0
;
pos
<
size
;
pos
+=
nBytes
)
{
if
(
pos
)
O
<<
", "
;
if
(
pos
==
nextSymbolPos
)
{
Value
*
v
=
Symbols
[
nSym
]
;
if
(
GlobalValue
*
GVar
=
dyn_cast
<
GlobalValue
>
(
v
)
)
{
MCSymbol
*
Name
=
AP
.
Mang
->
getSymbol
(
GVar
)
;
O
<<
*
Name
;
}
else
if
(
ConstantExpr
*
Cexpr
=
dyn_cast
<
ConstantExpr
>
(
v
)
)
{
O
<<
*
nvptx
::
LowerConstant
(
Cexpr
,
AP
)
;
}
else
llvm_unreachable
(
"symbol type unknown"
)
;
nSym
++
;
if
(
nSym
>=
numSymbols
)
nextSymbolPos
=
size
+
1
;
else
nextSymbolPos
=
symbolPosInBuffer
[
nSym
]
;
}
else
if
(
nBytes
==
4
)
O
<<
*
(
unsigned
int
*
)
(
buffer
+
pos
)
;
else
O
<<
*
(
unsigned
long
long
*
)
(
buffer
+
pos
)
;
}
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> static tree ix86_get_builtin_type ( enum ix86_builtin_type tcode ) { unsigned int index ; tree type , itype ; gcc_assert ( ( unsigned ) tcode < ARRAY_SIZE ( ix86_builtin_type_tab ) ) ; type = ix86_builtin_type_tab [ ( int ) tcode ] ; if ( type != NULL ) return type ; gcc_assert ( tcode > IX86_BT_LAST_PRIM ) ; if ( tcode <= IX86_BT_LAST_VECT ) { machine_mode mode ; index = tcode - IX86_BT_LAST_PRIM - 1 ; itype = ix86_get_builtin_type ( ix86_builtin_type_vect_base [ index ] ) ; mode = ix86_builtin_type_vect_mode [ index ] ; type = build_vector_type_for_mode ( itype , mode ) ; } else { int quals ; index = tcode - IX86_BT_LAST_VECT - 1 ; if ( tcode <= IX86_BT_LAST_PTR ) quals = TYPE_UNQUALIFIED ; else quals = TYPE_QUAL_CONST ; itype = ix86_get_builtin_type ( ix86_builtin_type_ptr_base [ index ] ) ; if ( quals != TYPE_UNQUALIFIED ) itype = build_qualified_type ( itype , quals ) ; type = build_pointer_type ( itype ) ; } ix86_builtin_type_tab [ ( int ) tcode ] = type ; return type ; } </s>

Retrieve an element from the above table , building some of the types lazily .


"ACLE function %qD requires ISA extension %qs"

"you can enable %qs using the command-line"

" option %<-march%>, or by using the %<target%>"

Report an error against LOCATION that the user has tried to use function FNDECL when extension EXTENSION is disabled .


<s> static void tilepro_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int byte_size = arg . promoted_size_in_bytes ( ) ; int word_size = ( byte_size + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; bool doubleword_aligned_p ; doubleword_aligned_p = tilepro_function_arg_boundary ( arg . mode , arg . type ) > BITS_PER_WORD ; if ( doubleword_aligned_p ) * cum += * cum & 1 ; if ( * cum < TILEPRO_NUM_ARG_REGS && * cum + word_size > TILEPRO_NUM_ARG_REGS ) * cum = TILEPRO_NUM_ARG_REGS ; * cum += word_size ; } </s>


<s> bool ARMAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { const uint16_t Thumb1_16bitNopEncoding = 0x46c0 ; const uint16_t Thumb2_16bitNopEncoding = 0xbf00 ; const uint32_t ARMv4_NopEncoding = 0xe1a0000 ; const uint32_t ARMv6T2_NopEncoding = 0xe320f000 ; if ( isThumb ( ) ) { const uint16_t nopEncoding = hasNOP ( ) ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding ; uint64_t NumNops = Count / 2 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> Write16 ( nopEncoding ) ; if ( Count & 1 ) OW -> Write8 ( 0 ) ; return true ; } const uint32_t nopEncoding = hasNOP ( ) ? ARMv6T2_NopEncoding : ARMv4_NopEncoding ; uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> Write32 ( nopEncoding ) ; switch ( Count % 4 ) { default : break ; case 1 : OW -> Write8 ( 0 ) ; break ; case 2 : OW -> Write16 ( 0 ) ; break ; case 3 : OW -> Write16 ( 0 ) ; OW -> Write8 ( 0xa0 ) ; break ; } return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s>
unsigned
X86InstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
I
->
getOpcode
(
)
!=
X86
::
JMP_1
&&
getCondFromBranchOpc
(
I
->
getOpcode
(
)
)
==
X86
::
COND_INVALID
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> static int rs6000_tls_symbol_ref_1 ( rtx * x , void * data ATTRIBUTE_UNUSED ) { return RS6000_SYMBOL_REF_TLS_P ( * x ) ; } </s>

Return 1 if * X is a thread-local symbol . This is the same as rs6000_tls_symbol_ref except for the type of the unused argument .


<s> const MCExpr * getSubExpr ( ) const { return Expr ; } </s>

getSubExpr - Get the child of this expression .


<s> bool X86CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto DL = MF . getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArg ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArg , Idx + 1 , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs ) { MIRBuilder . buildMerge ( VRegs [ Idx ] , Regs ) ; } ) ; Idx ++ ; } MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; FormalArgHandler Handler ( MIRBuilder , MRI , CC_X86 , DL ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> static void cr16_create_dwarf_for_multi_push ( rtx insn ) { rtx dwarf , reg , tmp ; int i , j , from , to , word_cnt , dwarf_par_index , inc ; machine_mode mode ; int num_regs = 0 , offset = 0 , split_here = 0 , total_push_bytes = 0 ; for ( i = 0 ; i <= current_frame_info . last_reg_to_save ; ++ i ) { if ( current_frame_info . save_regs [ i ] ) { ++ num_regs ; if ( i < CR16_FIRST_DWORD_REGISTER ) total_push_bytes += 2 ; else total_push_bytes += 4 ; } } if ( ! num_regs ) return ; dwarf = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( num_regs + 1 ) ) ; dwarf_par_index = num_regs ; from = current_frame_info . last_reg_to_save + 1 ; to = current_frame_info . last_reg_to_save ; word_cnt = 0 ; for ( i = current_frame_info . last_reg_to_save ; i >= 0 ; ) { if ( ! current_frame_info . save_regs [ i ] || i == 0 || split_here ) { if ( i == 0 && current_frame_info . save_regs [ i ] ) from = 0 ; for ( j = to ; j >= from ; -- j ) { if ( j < CR16_FIRST_DWORD_REGISTER ) { mode = HImode ; inc = 1 ; } else { mode = SImode ; inc = 2 ; } reg = gen_rtx_REG ( mode , j ) ; offset += 2 * inc ; tmp = gen_rtx_SET ( gen_frame_mem ( mode , plus_constant ( Pmode , stack_pointer_rtx , total_push_bytes - offset ) ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , dwarf_par_index -- ) = tmp ; } from = i ; to = -- i ; split_here = 0 ; word_cnt = 0 ; continue ; } if ( i != RETURN_ADDRESS_REGNUM ) { inc = ( i < CR16_FIRST_DWORD_REGISTER ) ? 1 : 2 ; if ( word_cnt + inc >= MAX_COUNT || FRAME_POINTER_REGNUM == i ) { split_here = 1 ; from = i ; continue ; } word_cnt += inc ; } from = i -- ; } tmp = gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( SImode , stack_pointer_rtx , GEN_INT ( - offset ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , 0 ) = tmp ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , dwarf ) ; } </s>

Generate DWARF2 annotation for multi-push instruction .


<s> static void do_unlink ( rtx spreg , HOST_WIDE_INT frame_size , bool all , int epilogue_p ) { frame_size += arg_area_size ( ) ; if ( stack_frame_needed_p ( ) ) emit_insn ( gen_unlink ( ) ) ; else { rtx postinc = gen_rtx_MEM ( Pmode , gen_rtx_POST_INC ( Pmode , spreg ) ) ; add_to_reg ( spreg , frame_size , 0 , epilogue_p ) ; if ( all || must_save_fp_p ( ) ) { rtx fpreg = gen_rtx_REG ( Pmode , REG_FP ) ; emit_move_insn ( fpreg , postinc ) ; emit_use ( fpreg ) ; } if ( all || must_save_rets_p ( ) ) { emit_move_insn ( bfin_rets_rtx , postinc ) ; emit_use ( bfin_rets_rtx ) ; } } } </s>

Like do_link , but used for epilogues to deallocate the stack frame .


<s> static bool needs_neutering_p ( rtx_insn * insn ) { if ( ! INSN_P ( insn ) ) return false ; switch ( recog_memoized ( insn ) ) { case CODE_FOR_nvptx_fork : case CODE_FOR_nvptx_forked : case CODE_FOR_nvptx_joining : case CODE_FOR_nvptx_join : case CODE_FOR_nvptx_barsync : return false ; default : return true ; } } </s>


<s> static void nios2_asm_function_prologue ( FILE * file ) { if ( flag_verbose_asm || flag_debug_asm ) { nios2_compute_frame_layout ( ) ; nios2_dump_frame_layout ( file ) ; } } </s>


<s> bool M68kRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s>
bool
ARMCodeGenPrepare
::
runOnFunction
(
Function
&
F
)
{
if
(
skipFunction
(
F
)
||
DisableCGP
)
return
false
;
auto
*
TPC
=
&
getAnalysis
<
TargetPassConfig
>
(
)
;
if
(
!
TPC
)
return
false
;
const
TargetMachine
&
TM
=
TPC
->
getTM
<
TargetMachine
>
(
)
;
ST
=
&
TM
.
getSubtarget
<
ARMSubtarget
>
(
F
)
;
bool
MadeChange
=
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM CGP: Running on "
<<
F
.
getName
(
)
<<
"\n"
)
;
for
(
BasicBlock
&
BB
:
F
)
{
auto
&
Insts
=
BB
.
getInstList
(
)
;
for
(
auto
&
I
:
Insts
)
{
if
(
AllVisited
.
count
(
&
I
)
)
continue
;
if
(
isa
<
ICmpInst
>
(
I
)
)
{
auto
&
CI
=
cast
<
ICmpInst
>
(
I
)
;
if
(
CI
.
isSigned
(
)
||
!
isa
<
IntegerType
>
(
CI
.
getOperand
(
0
)
->
getType
(
)
)
)
continue
;
for
(
auto
&
Op
:
CI
.
operands
(
)
)
{
if
(
auto
*
I
=
dyn_cast
<
Instruction
>
(
Op
)
)
MadeChange
|=
TryToPromote
(
I
)
;
}
}
}
Promoter
->
Cleanup
(
)
;
LLVM_DEBUG
(
if
(
verifyFunction
(
F
,
&
dbgs
(
)
)
)
{
dbgs
(
)
;
report_fatal_error
(
"Broken function after type promotion"
)
;
}
)
;
}
if
(
MadeChange
)
LLVM_DEBUG
(
dbgs
(
)
<<
"After ARMCodeGenPrepare: "
<<
F
<<
"\n"
)
;
return
MadeChange
;
}
</s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .

ARM
ARM
ARM
"ARM CGP: Running on "
"\n"
0
"Broken function after type promotion"
"After ARMCodeGenPrepare: "
"\n"


<s> void ARMBaseRegisterInfo :: updateRegAllocHint ( unsigned Reg , unsigned NewReg , MachineFunction & MF ) const { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; std :: pair < unsigned , unsigned > Hint = MRI -> getRegAllocationHint ( Reg ) ; if ( ( Hint . first == ( unsigned ) ARMRI :: RegPairOdd || Hint . first == ( unsigned ) ARMRI :: RegPairEven ) && Register :: isVirtualRegister ( Hint . second ) ) { unsigned OtherReg = Hint . second ; Hint = MRI -> getRegAllocationHint ( OtherReg ) ; if ( Hint . second == Reg ) { MRI -> setRegAllocationHint ( OtherReg , Hint . first , NewReg ) ; if ( Register :: isVirtualRegister ( NewReg ) ) MRI -> setRegAllocationHint ( NewReg , Hint . first == ( unsigned ) ARMRI :: RegPairOdd ? ARMRI :: RegPairEven : ARMRI :: RegPairOdd , OtherReg ) ; } } } </s>

A callback to allow target a chance to update register allocation hints when a register is `` changed '' ( e.g .

ARM ARM ARMRI::RegPairOdd ARMRI::RegPairEven ARMRI::RegPairOdd ARMRI::RegPairEven ARMRI::RegPairOdd


<s> bool ARMPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( ! getARMSubtarget ( ) . isThumb1Only ( ) ) PM . add ( createARMLoadStoreOptimizationPass ( ) ) ; if ( getARMSubtarget ( ) . hasNEON ( ) ) PM . add ( createExecutionDependencyFixPass ( & ARM :: DPRRegClass ) ) ; } PM . add ( createARMExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( ! getARMSubtarget ( ) . isThumb1Only ( ) ) addPass ( IfConverterID ) ; } if ( getARMSubtarget ( ) . isThumb2 ( ) ) PM . add ( createThumb2ITBlockPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .

ARM ARM ARM ARM ARM ARM::DPRRegClass ARM ARM ARM


<s> Register SIRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , int FrameIdx , int64_t Offset ) const { MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const SIInstrInfo * TII = ST . getInstrInfo ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; unsigned MovOpc = ST . enableFlatScratch ( ) ? AMDGPU :: S_MOV_B32 : AMDGPU :: V_MOV_B32_e32 ; Register BaseReg = MRI . createVirtualRegister ( ST . enableFlatScratch ( ) ? & AMDGPU :: SReg_32_XEXEC_HIRegClass : & AMDGPU :: VGPR_32RegClass ) ; if ( Offset == 0 ) { BuildMI ( * MBB , Ins , DL , TII -> get ( MovOpc ) , BaseReg ) . addFrameIndex ( FrameIdx ) ; return BaseReg ; } Register OffsetReg = MRI . createVirtualRegister ( & AMDGPU :: SReg_32_XM0RegClass ) ; Register FIReg = MRI . createVirtualRegister ( ST . enableFlatScratch ( ) ? & AMDGPU :: SReg_32_XM0RegClass : & AMDGPU :: VGPR_32RegClass ) ; BuildMI ( * MBB , Ins , DL , TII -> get ( AMDGPU :: S_MOV_B32 ) , OffsetReg ) . addImm ( Offset ) ; BuildMI ( * MBB , Ins , DL , TII -> get ( MovOpc ) , FIReg ) . addFrameIndex ( FrameIdx ) ; if ( ST . enableFlatScratch ( ) ) { BuildMI ( * MBB , Ins , DL , TII -> get ( AMDGPU :: S_ADD_U32 ) , BaseReg ) . addReg ( OffsetReg , RegState :: Kill ) . addReg ( FIReg ) ; return BaseReg ; } TII -> getAddNoCarry ( * MBB , Ins , DL , BaseReg ) . addReg ( OffsetReg , RegState :: Kill ) . addReg ( FIReg ) . addImm ( 0 ) ; return BaseReg ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .


<s> int arm_no_early_store_addr_dep ( rtx producer , rtx consumer ) { rtx value = arm_find_sub_rtx_with_code ( PATTERN ( producer ) , SET , false ) ; rtx addr = arm_find_sub_rtx_with_code ( PATTERN ( consumer ) , SET , false ) ; if ( value ) value = SET_DEST ( value ) ; if ( addr ) addr = SET_DEST ( addr ) ; if ( ! value || ! addr ) return 0 ; return ! reg_overlap_mentioned_p ( value , addr ) ; } </s>

Return nonzero if the CONSUMER instruction ( a store ) does not need PRODUCER 's value to calculate the address .


<s> unsigned HexagonInstrInfo :: getUnits ( const MachineInstr & MI ) const { const TargetSubtargetInfo & ST = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) ; const InstrItineraryData & II = * ST . getInstrItineraryData ( ) ; const InstrStage & IS = * II . beginStage ( MI . getDesc ( ) . getSchedClass ( ) ) ; return IS . getUnits ( ) ; } </s>


<s> int arc_output_addsi ( rtx * operands , bool cond_p , bool output_p ) { char format [ 35 ] ; int match = operands_match_p ( operands [ 0 ] , operands [ 1 ] ) ; int match2 = operands_match_p ( operands [ 0 ] , operands [ 2 ] ) ; int intval = ( REG_P ( operands [ 2 ] ) ? 1 : CONST_INT_P ( operands [ 2 ] ) ? INTVAL ( operands [ 2 ] ) : 0xbadc057 ) ; int neg_intval = - intval ; int short_0 = arc_check_short_reg_p ( operands [ 0 ] ) ; int short_p = ( ! cond_p && short_0 && arc_check_short_reg_p ( operands [ 1 ] ) ) ; int ret = 0 ; && REGNO ( OP ) != 30 ) \ || ! TARGET_V2 ) ) if ( output_p ) \ output_asm_insn ( FORMAT , operands ) ; \ return ret ; \ } </s>

Emit code for an addsi3 instruction with OPERANDS . COND_P indicates if this will use conditional execution . Return the length of the instruction . If OUTPUT_P is false , do n't actually output the instruction , just return its length .


<s> SDNode * PPCDAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * TM . getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc dl ; if ( PPCLowering . getPointerTy ( ) == MVT :: i32 ) { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: GPRCRegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: G8RCRegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR8 ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR8 ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , PPCLowering . getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static int num_insns_constant_multi ( HOST_WIDE_INT value , machine_mode mode ) { int nregs = ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; int total = 0 ; while ( nregs -- > 0 ) { HOST_WIDE_INT low = sext_hwi ( value , BITS_PER_WORD ) ; int insns = num_insns_constant_gpr ( low ) ; if ( insns > 2 && rs6000_is_valid_and_mask ( GEN_INT ( low ) , DImode ) ) insns = 2 ; total += insns ; value >>= ( BITS_PER_WORD - 1 ) ; value >>= 1 ; } return total ; } </s>

Helper for num_insns_constant . Allow constants formed by the num_insns_constant_gpr sequences , plus li -1 , rldicl/rldicr/rlwinm , and handle modes that require multiple gprs .


<s> int mn10300_split_and_operand_count ( rtx op ) { HOST_WIDE_INT val = INTVAL ( op ) ; int count ; if ( val < 0 ) { count = exact_log2 ( - val ) ; if ( count < 0 ) return 0 ; if ( count > ( optimize_insn_for_speed_p ( ) ? 2 : 4 ) ) return 0 ; return count ; } else { count = exact_log2 ( val + 1 ) ; count = 32 - count ; if ( count > ( optimize_insn_for_speed_p ( ) ? 2 : 4 ) ) return 0 ; return - count ; } } </s>

This function is used to help split : ( set ( reg ) ( and ( reg ) ( int ) ) ) into : ( set ( reg ) ( shift ( reg ) ( int ) ) ( set ( reg ) ( shift ( reg ) ( int ) ) where the shitfs will be shorter than the `` and '' insn . It returns the number of bits that should be shifted . A positive values means that the low bits are to be cleared ( and hence the shifts should be right followed by left ) whereas a negative value means that the high bits are to be cleared ( left followed by right ) . Zero is returned when it would not be economical to split the AND .


<s> bool ARMTargetLowering :: isShuffleMaskLegal ( ArrayRef < int > M , EVT VT ) const { if ( VT . getVectorNumElements ( ) == 4 && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ 4 ] ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { if ( M [ i ] < 0 ) PFIndexes [ i ] = 8 ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ 0 ] * 9 * 9 * 9 + PFIndexes [ 1 ] * 9 * 9 + PFIndexes [ 2 ] * 9 + PFIndexes [ 3 ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> 30 ) ; if ( Cost <= 4 && ( Subtarget -> hasNEON ( ) || isLegalMVEShuffleOp ( PFEntry ) ) ) return true ; } bool ReverseVEXT , isV_UNDEF ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; if ( EltSize >= 32 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || ShuffleVectorInst :: isIdentityMask ( M ) || isVREVMask ( M , VT , 64 ) || isVREVMask ( M , VT , 32 ) || isVREVMask ( M , VT , 16 ) ) return true ; else if ( Subtarget -> hasNEON ( ) && ( isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTBLMask ( M , VT ) || isNEONTwoResultShuffleMask ( M , VT , WhichResult , isV_UNDEF ) ) ) return true ; else if ( Subtarget -> hasNEON ( ) && ( VT == MVT :: v8i16 || VT == MVT :: v16i8 ) && isReverseMask ( M , VT ) ) return true ; else if ( Subtarget -> hasMVEIntegerOps ( ) && ( isVMOVNMask ( M , VT , 0 ) || isVMOVNMask ( M , VT , 1 ) ) ) return true ; else return false ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> static void alpha_expand_unaligned_load_words ( rtx * out_regs , rtx smem , HOST_WIDE_INT words , HOST_WIDE_INT ofs ) { rtx const im8 = GEN_INT ( - 8 ) ; rtx ext_tmps [ MAX_MOVE_WORDS ] , data_regs [ MAX_MOVE_WORDS + 1 ] ; rtx sreg , areg , tmp , smema ; HOST_WIDE_INT i ; smema = XEXP ( smem , 0 ) ; if ( GET_CODE ( smema ) == LO_SUM ) smema = force_reg ( Pmode , smema ) ; for ( i = 0 ; i < words ; ++ i ) { data_regs [ i ] = out_regs [ i ] ; ext_tmps [ i ] = gen_reg_rtx ( DImode ) ; } data_regs [ words ] = gen_reg_rtx ( DImode ) ; if ( ofs != 0 ) smem = adjust_address ( smem , GET_MODE ( smem ) , ofs ) ; for ( i = 0 ; i < words ; ++ i ) { tmp = change_address ( smem , DImode , gen_rtx_AND ( DImode , plus_constant ( DImode , smema , 8 * i ) , im8 ) ) ; set_mem_alias_set ( tmp , 0 ) ; emit_move_insn ( data_regs [ i ] , tmp ) ; } tmp = change_address ( smem , DImode , gen_rtx_AND ( DImode , plus_constant ( DImode , smema , 8 * words - 1 ) , im8 ) ) ; set_mem_alias_set ( tmp , 0 ) ; emit_move_insn ( data_regs [ words ] , tmp ) ; sreg = copy_addr_to_reg ( smema ) ; areg = expand_binop ( DImode , and_optab , sreg , GEN_INT ( 7 ) , NULL , 1 , OPTAB_WIDEN ) ; for ( i = 0 ; i < words ; ++ i ) { emit_insn ( gen_extql ( data_regs [ i ] , data_regs [ i ] , sreg ) ) ; emit_insn ( gen_extqh ( ext_tmps [ i ] , data_regs [ i + 1 ] , sreg ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , ext_tmps [ i ] , gen_rtx_IF_THEN_ELSE ( DImode , gen_rtx_EQ ( DImode , areg , const0_rtx ) , const0_rtx , ext_tmps [ i ] ) ) ) ; } for ( i = 0 ; i < words ; ++ i ) { out_regs [ i ] = expand_binop ( DImode , ior_optab , data_regs [ i ] , ext_tmps [ i ] , data_regs [ i ] , 1 , OPTAB_WIDEN ) ; } } </s>

Load an integral number of consecutive unaligned quadwords .


<s> static rtx aarch64_expand_builtin_ls64 ( int fcode , tree exp , rtx target ) { expand_operand ops [ 3 ] ; switch ( fcode ) { case AARCH64_LS64_BUILTIN_LD64B : { rtx op0 = expand_normal ( CALL_EXPR_ARG ( exp , 0 ) ) ; create_output_operand ( & ops [ 0 ] , target , V8DImode ) ; create_input_operand ( & ops [ 1 ] , op0 , DImode ) ; expand_insn ( CODE_FOR_ld64b , 2 , ops ) ; return ops [ 0 ] . value ; } case AARCH64_LS64_BUILTIN_ST64B : { rtx op0 = expand_normal ( CALL_EXPR_ARG ( exp , 0 ) ) ; rtx op1 = expand_normal ( CALL_EXPR_ARG ( exp , 1 ) ) ; create_output_operand ( & ops [ 0 ] , op0 , DImode ) ; create_input_operand ( & ops [ 1 ] , op1 , V8DImode ) ; expand_insn ( CODE_FOR_st64b , 2 , ops ) ; return const0_rtx ; } case AARCH64_LS64_BUILTIN_ST64BV : { rtx op0 = expand_normal ( CALL_EXPR_ARG ( exp , 0 ) ) ; rtx op1 = expand_normal ( CALL_EXPR_ARG ( exp , 1 ) ) ; create_output_operand ( & ops [ 0 ] , target , DImode ) ; create_input_operand ( & ops [ 1 ] , op0 , DImode ) ; create_input_operand ( & ops [ 2 ] , op1 , V8DImode ) ; expand_insn ( CODE_FOR_st64bv , 3 , ops ) ; return ops [ 0 ] . value ; } case AARCH64_LS64_BUILTIN_ST64BV0 : { rtx op0 = expand_normal ( CALL_EXPR_ARG ( exp , 0 ) ) ; rtx op1 = expand_normal ( CALL_EXPR_ARG ( exp , 1 ) ) ; create_output_operand ( & ops [ 0 ] , target , DImode ) ; create_input_operand ( & ops [ 1 ] , op0 , DImode ) ; create_input_operand ( & ops [ 2 ] , op1 , V8DImode ) ; expand_insn ( CODE_FOR_st64bv0 , 3 , ops ) ; return ops [ 0 ] . value ; } } gcc_unreachable ( ) ; } </s>

Function to expand an expression EXP which calls one of the Load/Store 64 Byte extension ( LS64 ) builtins FCODE with the result going to TARGET .


<s> int s390_class_max_nregs ( enum reg_class rclass , machine_mode mode ) { switch ( rclass ) { case FP_REGS : if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) return 2 * ( ( GET_MODE_SIZE ( mode ) / 2 + 8 - 1 ) / 8 ) ; else return ( GET_MODE_SIZE ( mode ) + 8 - 1 ) / 8 ; case ACCESS_REGS : return ( GET_MODE_SIZE ( mode ) + 4 - 1 ) / 4 ; default : break ; } return ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } </s>

Maximum number of registers to represent a value of mode MODE in a register of class RCLASS .


<s> VariantKind getKind ( ) const { return Kind ; } </s>


<s> static char * detect_caches_darwin ( void ) { unsigned l1_sizekb , l1_line , l1_assoc , l2_sizekb ; size_t len = 4 ; static int l1_size_name [ 2 ] = { CTL_HW , HW_L1DCACHESIZE } ; static int l1_line_name [ 2 ] = { CTL_HW , HW_CACHELINE } ; static int l2_size_name [ 2 ] = { CTL_HW , HW_L2CACHESIZE } ; sysctl ( l1_size_name , 2 , & l1_sizekb , & len , NULL , 0 ) ; sysctl ( l1_line_name , 2 , & l1_line , & len , NULL , 0 ) ; sysctl ( l2_size_name , 2 , & l2_sizekb , & len , NULL , 0 ) ; l1_assoc = 0 ; return describe_cache ( l1_sizekb / 1024 , l1_line , l1_assoc , l2_sizekb / 1024 ) ; } </s>

Returns the description of caches on Darwin .


<s> unsigned getGlobalBaseReg ( ) const { return GlobalBaseReg ; } </s>


<s> static void emit_split_stack_prologue ( rs6000_stack_t * info , rtx_insn * sp_adjust , HOST_WIDE_INT frame_off , rtx frame_reg_rtx ) { cfun -> machine -> split_stack_argp_used = true ; if ( sp_adjust ) { rtx r12 = gen_rtx_REG ( Pmode , 12 ) ; rtx sp_reg_rtx = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; rtx set_r12 = gen_rtx_SET ( r12 , sp_reg_rtx ) ; emit_insn_before ( set_r12 , sp_adjust ) ; } else if ( frame_off != 0 || REGNO ( frame_reg_rtx ) != 12 ) { rtx r12 = gen_rtx_REG ( Pmode , 12 ) ; if ( frame_off == 0 ) emit_move_insn ( r12 , frame_reg_rtx ) ; else emit_insn ( gen_add3_insn ( r12 , frame_reg_rtx , GEN_INT ( frame_off ) ) ) ; } if ( info -> push_p ) { rtx r12 = gen_rtx_REG ( Pmode , 12 ) ; rtx r29 = gen_rtx_REG ( Pmode , 29 ) ; rtx cr7 = gen_rtx_REG ( CCUNSmode , CR7_REGNO ) ; rtx not_more = gen_label_rtx ( ) ; rtx jump ; jump = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_GEU ( VOIDmode , cr7 , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , not_more ) , pc_rtx ) ; jump = emit_jump_insn ( gen_rtx_SET ( pc_rtx , jump ) ) ; JUMP_LABEL ( jump ) = not_more ; LABEL_NUSES ( not_more ) += 1 ; emit_move_insn ( r12 , r29 ) ; emit_label ( not_more ) ; } } </s>

Set up the arg pointer ( r12 ) for -fsplit-stack code . If __morestack was called , it left the arg pointer to the old stack in r29 . Otherwise , the arg pointer is the top of the current frame .


<s> bool X86FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || TRI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasOpaqueSPAdjustment ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> hasPreallocatedCall ( ) || MF . callsUnwindInit ( ) || MF . hasEHFunclets ( ) || MF . callsEHReturn ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || MFI . hasCopyImplyingStackAdjustment ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
void
MMIXInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MBBI
,
const
DebugLoc
&
DL
,
MCRegister
DstReg
,
MCRegister
SrcReg
,
bool
KillSrc
)
const
{
assert
(
MMIX
::
GPRRegClass
.
contains
(
DstReg
,
SrcReg
)
&&
"Impossible reg-to-reg copy"
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
MMIX
::
ADD_I
)
,
DstReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
0
)
;
}
</s>

MMIX
MMIX
MMIX::GPRRegClass
"Impossible reg-to-reg copy"
MMIX::ADD_I
0


<s> bool SystemZTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( AM . BaseGV ) return false ; if ( ! isInt < 20 > ( AM . BaseOffs ) ) return false ; return AM . Scale == 0 || AM . Scale == 1 ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s>
static
void
pa_output_function_prologue
(
FILE
*
file
,
HOST_WIDE_INT
size
ATTRIBUTE_UNUSED
)
{
ASM_OUTPUT_LABEL
(
file
,
XSTR
(
XEXP
(
DECL_RTL
(
current_function_decl
)
,
0
)
,
0
)
)
;
fputs
(
"\t.PROC\n"
,
file
)
;
fprintf
(
file
,
"\t.CALLINFO FRAME="
HOST_WIDE_INT_PRINT_DEC
,
actual_fsize
)
;
if
(
regs_ever_live
[
2
]
)
fputs
(
",CALLS,SAVE_RP"
,
file
)
;
else
fputs
(
",NO_CALLS"
,
file
)
;
if
(
frame_pointer_needed
)
fputs
(
",SAVE_SP"
,
file
)
;
if
(
gr_saved
)
fprintf
(
file
,
",ENTRY_GR=%d"
,
gr_saved
+
2
)
;
if
(
fr_saved
)
fprintf
(
file
,
",ENTRY_FR=%d"
,
fr_saved
+
11
)
;
fputs
(
"\n\t.ENTRY\n"
,
file
)
;
remove_useless_addtr_insns
(
0
)
;
}
</s>

On HP-PA , move-double insns between fpu and cpu need an 8-byte block of memory . If any fpu reg is used in the function , we allocate such a block here , at the bottom of the frame , just in case it 's needed . If this function is a leaf procedure , then we may choose not to do a `` save '' insn . The decision about whether or not to do this is made in regclass.c .


<s> BitVector Tile64RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( T64 :: R51 ) ; Reserved . set ( T64 :: FramePointer ) ; Reserved . set ( T64 :: ThreadLocalData ) ; Reserved . set ( T64 :: StackPointer ) ; Reserved . set ( T64 :: LinkRegister ) ; Reserved . set ( T64 :: SN ) ; Reserved . set ( T64 :: IDN0 ) ; Reserved . set ( T64 :: IDN1 ) ; Reserved . set ( T64 :: UDN0 ) ; Reserved . set ( T64 :: UDN1 ) ; Reserved . set ( T64 :: UDN2 ) ; Reserved . set ( T64 :: UDN3 ) ; Reserved . set ( T64 :: Zero ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) -> findAssociatedFragment ( ) ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s> unsigned RISCVTargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT == MVT :: f16 && Subtarget . hasStdExtF ( ) && ! Subtarget . hasStdExtZfh ( ) ) return 1 ; return TargetLowering :: getNumRegistersForCallingConv ( Context , CC , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s> void ix86_output_patchable_area ( unsigned int patch_area_size , bool record_p ) { default_print_patchable_function_entry ( asm_out_file , patch_area_size , record_p ) ; } </s>

Output patchable area . NB : default_print_patchable_function_entry is n't available in i386.md .


<s> bool has ( Register R ) const { if ( ! R . isVirtual ( ) ) return true ; MapType :: const_iterator F = Map . find ( R ) ; return F != Map . end ( ) ; } </s>

Tests whether a library function is available .


<s> bool frv_function_value_regno_p ( const unsigned int regno ) { return ( regno == RETURN_VALUE_REGNUM ) ; } </s>


<s> unsigned ARM64TTI :: getIntImmCost ( Intrinsic :: ID IID , unsigned Idx , const APInt & Imm , Type * Ty ) const { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TCC_Free ; switch ( IID ) { default : return TCC_Free ; case Intrinsic :: sadd_with_overflow : case Intrinsic :: uadd_with_overflow : case Intrinsic :: ssub_with_overflow : case Intrinsic :: usub_with_overflow : case Intrinsic :: smul_with_overflow : case Intrinsic :: umul_with_overflow : if ( Idx == 1 ) { unsigned NumConstants = ( BitSize + 63 ) / 64 ; unsigned Cost = ARM64TTI :: getIntImmCost ( Imm , Ty ) ; return ( Cost <= NumConstants * TCC_Basic ) ? static_cast < unsigned > ( TCC_Free ) : Cost ; } break ; case Intrinsic :: experimental_stackmap : if ( ( Idx < 2 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TCC_Free ; break ; case Intrinsic :: experimental_patchpoint_void : case Intrinsic :: experimental_patchpoint_i64 : if ( ( Idx < 4 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TCC_Free ; break ; } return ARM64TTI :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> static void arm_emit_load_exclusive ( machine_mode mode , rtx rval , rtx mem , bool acq ) { rtx ( * gen ) ( rtx , rtx ) ; if ( acq ) { switch ( mode ) { case E_QImode : gen = gen_arm_load_acquire_exclusiveqi ; break ; case E_HImode : gen = gen_arm_load_acquire_exclusivehi ; break ; case E_SImode : gen = gen_arm_load_acquire_exclusivesi ; break ; case E_DImode : gen = gen_arm_load_acquire_exclusivedi ; break ; default : gcc_unreachable ( ) ; } } else { switch ( mode ) { case E_QImode : gen = gen_arm_load_exclusiveqi ; break ; case E_HImode : gen = gen_arm_load_exclusivehi ; break ; case E_SImode : gen = gen_arm_load_exclusivesi ; break ; case E_DImode : gen = gen_arm_load_exclusivedi ; break ; default : gcc_unreachable ( ) ; } } emit_insn ( gen ( rval , mem ) ) ; } </s>

Emit the load-exclusive and store-exclusive instructions . Use acquire and release versions if necessary .


<s> void SparcFrameLowering :: emitPrologue ( MachineFunction & MF ) const { SparcMachineFunctionInfo * FuncInfo = MF . getInfo < SparcMachineFunctionInfo > ( ) ; MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const SparcInstrInfo & TII = * static_cast < const SparcInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; unsigned SAVEri = SP :: SAVEri ; unsigned SAVErr = SP :: SAVErr ; if ( FuncInfo -> isLeafProc ( ) ) { if ( NumBytes == 0 ) return ; SAVEri = SP :: ADDri ; SAVErr = SP :: ADDrr ; } NumBytes = - SubTarget . getAdjustedFrameSize ( NumBytes ) ; emitSPAdjustment ( MF , MBB , MBBI , NumBytes , SAVErr , SAVEri ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; MCSymbol * FrameLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: PROLOG_LABEL ) ) . addSym ( FrameLabel ) ; unsigned regFP = MRI -> getDwarfRegNum ( SP :: I6 , true ) ; MMI . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( FrameLabel , regFP ) ) ; MMI . addFrameInst ( MCCFIInstruction :: createWindowSave ( FrameLabel ) ) ; unsigned regInRA = MRI -> getDwarfRegNum ( SP :: I7 , true ) ; unsigned regOutRA = MRI -> getDwarfRegNum ( SP :: O7 , true ) ; MMI . addFrameInst ( MCCFIInstruction :: createRegister ( FrameLabel , regOutRA , regInRA ) ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Sparc Sparc Sparc Sparc Sparc Sparc SP::SAVEri SP::SAVErr 0 SP::ADDri SP::ADDrr SP SP::PROLOG_LABEL SP::I6 SP::I7 SP::O7


<s> void BPFPassConfig :: addMachineSSAOptimization ( ) { addPass ( createBPFMISimplifyPatchablePass ( ) ) ; TargetPassConfig :: addMachineSSAOptimization ( ) ; const BPFSubtarget * Subtarget = getBPFTargetMachine ( ) . getSubtargetImpl ( ) ; if ( ! DisableMIPeephole ) { if ( Subtarget -> getHasAlu32 ( ) ) addPass ( createBPFMIPeepholePass ( ) ) ; addPass ( createBPFMIPeepholeTruncElimPass ( ) ) ; } } </s>

Methods with trivial inline returns are convenient points in the common codegen pass pipeline where targets may insert passes .


<s> DecodeStatus OR1KDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & vStream , raw_ostream & cStream ) const { uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Bytes , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTableOR1K32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { if ( RC == ARM :: GPRRegisterClass || RC == ARM :: tGPRRegisterClass || RC == ARM :: tcGPRRegisterClass || RC == ARM :: rGPRRegisterClass || RC == ARM :: GPRnopcRegisterClass ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2LDRi12 ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } ARMBaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC , TRI ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .

ARM ARM::GPRRegisterClass ARM::tGPRRegisterClass ARM::tcGPRRegisterClass ARM::rGPRRegisterClass ARM::GPRnopcRegisterClass ARM::t2LDRi12 0 ARM


<s>
static
MCSymbol
*
GetSymbolFromOperand
(
const
MachineOperand
&
MO
,
AsmPrinter
&
AP
)
{
const
TargetMachine
&
TM
=
AP
.
TM
;
Mangler
*
Mang
=
AP
.
Mang
;
const
DataLayout
*
DL
=
TM
.
getDataLayout
(
)
;
MCContext
&
Ctx
=
AP
.
OutContext
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_DARWIN_STUB
)
Suffix
=
"$stub"
;
else
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
Suffix
=
"$non_lazy_ptr"
;
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
->
getPrivateGlobalPrefix
(
)
;
unsigned
PrefixLen
=
Name
.
size
(
)
;
if
(
!
MO
.
isGlobal
(
)
)
{
assert
(
MO
.
isSymbol
(
)
&&
"Isn't a symbol reference"
)
;
Mang
->
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
)
;
}
else
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
TM
.
getNameWithPrefix
(
Name
,
GV
,
*
Mang
)
;
}
unsigned
OrigLen
=
Name
.
size
(
)
PrefixLen
;
Name
+=
Suffix
;
MCSymbol
*
Sym
=
Ctx
.
GetOrCreateSymbol
(
Name
.
str
(
)
)
;
StringRef
OrigName
=
StringRef
(
Name
)
.
substr
(
PrefixLen
,
OrigLen
)
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_DARWIN_STUB
)
{
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
getMachOMMI
(
AP
)
.
getFnStubEntry
(
Sym
)
;
if
(
StubSym
.
getPointer
(
)
)
return
Sym
;
if
(
MO
.
isGlobal
(
)
)
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
else
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
Ctx
.
GetOrCreateSymbol
(
OrigName
)
,
false
)
;
}
return
Sym
;
}
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
{
MachineModuleInfoMachO
&
MachO
=
getMachOMMI
(
AP
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_HIDDEN_FLAG
)
MachO
.
getHiddenGVStubEntry
(
Sym
)
:
MachO
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
return
Sym
;
}
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


<s> rtx sfunc_uses_reg ( rtx_insn * insn ) { int i ; rtx pattern , part , reg_part , reg ; if ( ! NONJUMP_INSN_P ( insn ) ) return NULL_RTX ; pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) != PARALLEL || get_attr_type ( insn ) != TYPE_SFUNC ) return NULL_RTX ; for ( reg_part = NULL_RTX , i = XVECLEN ( pattern , 0 ) - 1 ; i >= 1 ; i -- ) { part = XVECEXP ( pattern , 0 , i ) ; if ( GET_CODE ( part ) == USE && GET_MODE ( XEXP ( part , 0 ) ) == SImode ) reg_part = part ; } if ( ! reg_part ) return NULL_RTX ; reg = XEXP ( reg_part , 0 ) ; for ( i = XVECLEN ( pattern , 0 ) - 1 ; i >= 0 ; i -- ) { part = XVECEXP ( pattern , 0 , i ) ; if ( part == reg_part || GET_CODE ( part ) == CLOBBER ) continue ; if ( reg_mentioned_p ( reg , ( ( GET_CODE ( part ) == SET && REG_P ( SET_DEST ( part ) ) ) ? SET_SRC ( part ) : part ) ) ) return NULL_RTX ; } return reg ; } </s>

If the instruction INSN is implemented by a special function , and we can positively find the register that is used to call the sfunc , and this register is not used anywhere else in this instruction - except as the destination of a set , return this register ; else , return 0 .


<s> unsigned Z80oldRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { return 3 ; const Z80oldFrameLowering * TFI = getFrameLowering ( MF ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case Z80old :: R16RegClassID : return 2 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


"The Prefetches vector should contain at least a value if "

"Unexpected change in X86 operand offset order."

runOnMachineFunction - Emit the function body .


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( ( unsigned ) Kind , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( ( getFixupKindInfo ( Kind ) . TargetSize - 1 ) / 8 ) + 1 ; uint64_t Mask = ( ( uint64_t ) 1 << getFixupKindInfo ( Kind ) . TargetSize ) - 1 ; uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) CurVal |= ( ( uint8_t ) Data [ Offset + i ] ) << ( i * 8 ) ; CurVal = ( CurVal & ~ Mask ) | ( ( CurVal + Value ) & Mask ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { Data [ Offset + i ] = uint8_t ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
OpKind_Imm
:
OS
<<
"Imm: "
<<
getImm
(
)
<<
"\n"
;
break
;
case
OpKind_Token
:
OS
<<
"Token: "
<<
getToken
(
)
<<
"\n"
;
break
;
case
OpKind_Reg
:
OS
<<
"Reg: "
;
OS
<<
"%r"
;
OS
<<
"\n"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> void aarch64_split_atomic_op ( enum rtx_code code , rtx old_out , rtx new_out , rtx mem , rtx value , rtx model_rtx , rtx cond ) { machine_mode mode = GET_MODE ( mem ) ; machine_mode wmode = ( mode == DImode ? DImode : SImode ) ; const enum memmodel model = memmodel_from_int ( INTVAL ( model_rtx ) ) ; const bool is_sync = is_mm_sync ( model ) ; rtx_code_label * label ; rtx x ; label = gen_label_rtx ( ) ; emit_label ( label ) ; if ( new_out ) new_out = gen_lowpart ( wmode , new_out ) ; if ( old_out ) old_out = gen_lowpart ( wmode , old_out ) ; else old_out = new_out ; value = simplify_gen_subreg ( wmode , value , mode , 0 ) ; if ( is_sync ) aarch64_emit_load_exclusive ( mode , old_out , mem , GEN_INT ( MEMMODEL_RELAXED ) ) ; else aarch64_emit_load_exclusive ( mode , old_out , mem , model_rtx ) ; switch ( code ) { case SET : new_out = value ; break ; case NOT : x = gen_rtx_AND ( wmode , old_out , value ) ; emit_insn ( gen_rtx_SET ( new_out , x ) ) ; x = gen_rtx_NOT ( wmode , new_out ) ; emit_insn ( gen_rtx_SET ( new_out , x ) ) ; break ; case MINUS : if ( CONST_INT_P ( value ) ) { value = GEN_INT ( - INTVAL ( value ) ) ; code = PLUS ; } default : x = gen_rtx_fmt_ee ( code , wmode , old_out , value ) ; emit_insn ( gen_rtx_SET ( new_out , x ) ) ; break ; } aarch64_emit_store_exclusive ( mode , cond , mem , gen_lowpart ( mode , new_out ) , model_rtx ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; if ( is_sync ) aarch64_emit_post_barrier ( model ) ; } </s>


<s>
bool
sh_symbian_dllexport_p
(
tree
decl
)
{
tree
exp
;
if
(
TREE_CODE
(
decl
)
!=
VAR_DECL
&&
TREE_CODE
(
decl
)
!=
FUNCTION_DECL
)
return
false
;
exp
=
lookup_attribute
(
"dllexport"
,
DECL_ATTRIBUTES
(
decl
)
)
;
if
(
exp
==
)
{
tree
class
=
sh_symbian_associated_type
(
decl
)
;
if
(
class
)
exp
=
lookup_attribute
(
"dllexport"
,
TYPE_ATTRIBUTES
(
class
)
)
;
}
if
(
exp
)
{
print_node_brief
(
stderr
,
"dllexport:"
,
decl
,
0
)
;
fprintf
(
stderr
,
"\n"
)
;
}
else
if
(
TREE_CODE
(
decl
)
!=
FUNCTION_DECL
)
{
print_node_brief
(
stderr
,
"no dllexport:"
,
decl
,
0
)
;
fprintf
(
stderr
,
"\n"
)
;
}
return
exp
true
:
false
;
}
</s>

Return nonzero if DECL is a dllexport 'd object .

sh
"dllexport"
"dllexport"
"dllexport:"
0
"\n"
"no dllexport:"
0
"\n"


<s> ARMSubtarget :: ARMSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const ARMBaseTargetMachine & TM , bool IsLittle ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , UseMulOps ( UseFusedMulOps ) , GenExecuteOnly ( EnableExecuteOnly ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( ARMBaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( ARMBaseInstrInfo * ) new ARMInstrInfo ( * this ) : ( ARMBaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) { } </s>

This constructor initializes the data members to match that of the specified triple .


<s> DecodeStatus getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & OS , raw_ostream & CS ) const override { if ( Bytes . size ( ) < 2 ) { Size = 0 ; return MCDisassembler :: Fail ; } uint16_t Insn = 0 ; DecodeStatus Result = MCDisassembler :: Fail ; Insn = ( Bytes [ 1 ] << 8 ) | ( Bytes [ 0 ] << 0 ) ; Result = decodeInstruction ( DecoderTable16 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 2 ; return Result ; } return MCDisassembler :: Fail ; } </s>


<s> bool isAtomic ( uint16_t Opcode ) const { return get ( Opcode ) . TSFlags & ( SIInstrFlags :: IsAtomicRet | SIInstrFlags :: IsAtomicNoRet ) ; } </s>

Returns true if this operation has an atomic ordering requirement of unordered or higher , false otherwise .


<s> void emitValueToOffset ( const MCExpr * Offset , unsigned char Value , SMLoc Loc ) override { } </s>

Emit some number of copies of Value until the byte offset Offset is reached .


<s> static bool arm_evpc_neon_vtrn ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> perm . length ( ) ; rtx out0 , out1 , in0 , in1 ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; if ( d -> perm [ 0 ] == 0 ) odd = 0 ; else if ( d -> perm [ 0 ] == 1 ) odd = 1 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt ; i += 2 ) { if ( d -> perm [ i ] != i + odd ) return false ; if ( d -> perm [ i + 1 ] != ( ( i + nelt + odd ) & mask ) ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case E_V16QImode : gen = gen_neon_vtrnv16qi_internal ; break ; case E_V8QImode : gen = gen_neon_vtrnv8qi_internal ; break ; case E_V8HImode : gen = gen_neon_vtrnv8hi_internal ; break ; case E_V4HImode : gen = gen_neon_vtrnv4hi_internal ; break ; case E_V8HFmode : gen = gen_neon_vtrnv8hf_internal ; break ; case E_V4HFmode : gen = gen_neon_vtrnv4hf_internal ; break ; case E_V4SImode : gen = gen_neon_vtrnv4si_internal ; break ; case E_V2SImode : gen = gen_neon_vtrnv2si_internal ; break ; case E_V2SFmode : gen = gen_neon_vtrnv2sf_internal ; break ; case E_V4SFmode : gen = gen_neon_vtrnv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN ) { std :: swap ( in0 , in1 ) ; odd = ! odd ; } out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( odd ) std :: swap ( out0 , out1 ) ; emit_insn ( gen ( out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s> bool aarch64_legitimate_address_p ( machine_mode mode , rtx x , RTX_CODE outer_code , bool strict_p ) { struct aarch64_address_info addr ; return aarch64_classify_address ( & addr , x , mode , outer_code , strict_p ) ; } </s>

Return TRUE if X is a legitimate address for accessing memory in mode MODE . OUTER_CODE will be PARALLEL if this is a load/store pair operation .


<s> void MipsRegisterBankInfo :: applyMappingImpl ( const OperandsMapper & OpdMapper ) const { MachineInstr & MI = OpdMapper . getMI ( ) ; InstListTy NewInstrs ; MachineFunction * MF = MI . getMF ( ) ; MachineRegisterInfo & MRI = OpdMapper . getMRI ( ) ; const LegalizerInfo & LegInfo = * MF -> getSubtarget ( ) . getLegalizerInfo ( ) ; InstManager NewInstrObserver ( NewInstrs ) ; MachineIRBuilder B ( MI , NewInstrObserver ) ; LegalizerHelper Helper ( * MF , NewInstrObserver , B ) ; LegalizationArtifactCombiner ArtCombiner ( B , MF -> getRegInfo ( ) , LegInfo ) ; switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_LOAD : case TargetOpcode :: G_STORE : case TargetOpcode :: G_PHI : case TargetOpcode :: G_SELECT : case TargetOpcode :: G_IMPLICIT_DEF : { Helper . narrowScalar ( MI , 0 , LLT :: scalar ( 32 ) ) ; while ( ! NewInstrs . empty ( ) ) { MachineInstr * NewMI = NewInstrs . pop_back_val ( ) ; if ( NewMI -> getOpcode ( ) == TargetOpcode :: G_UNMERGE_VALUES ) combineAwayG_UNMERGE_VALUES ( ArtCombiner , * NewMI , NewInstrObserver ) ; else if ( NewMI -> getOpcode ( ) == TargetOpcode :: G_MERGE_VALUES ) continue ; else setRegBank ( * NewMI , MRI ) ; } return ; } case TargetOpcode :: G_UNMERGE_VALUES : combineAwayG_UNMERGE_VALUES ( ArtCombiner , MI , NewInstrObserver ) ; return ; default : break ; } return applyDefaultMapping ( OpdMapper ) ; } </s>


<s> bool and_operands_ok ( machine_mode mode , rtx op1 , rtx op2 ) { return ( memory_operand ( op1 , mode ) ? and_load_operand ( op2 , mode ) : and_reg_operand ( op2 , mode ) ) ; } </s>

Return true iff OP1 and OP2 are valid operands together for the * and < MODE > 3 and * and < MODE > 3_mips16 patterns . For the cases to consider , see the table in the comment before the pattern .


<s> bool XCoreAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { return true ; } printOperand ( MI , OpNum , O ) ; O << '[' ; printOperand ( MI , OpNum + 1 , O ) ; O << ']' ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> const TargetRegisterClass * CJGRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & CJG :: GPRegsRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> static void increment_stack ( HOST_WIDE_INT amount ) { rtx inc ; rtx sp = stack_pointer_rtx ; if ( amount == 0 ) return ; if ( amount < 0 ) { inc = GEN_INT ( - amount ) ; if ( TARGET_LARGE ) F ( emit_insn ( gen_subpsi3 ( sp , sp , inc ) ) ) ; else F ( emit_insn ( gen_subhi3 ( sp , sp , inc ) ) ) ; } else { inc = GEN_INT ( amount ) ; if ( TARGET_LARGE ) F ( emit_insn ( gen_addpsi3 ( sp , sp , inc ) ) ) ; else F ( emit_insn ( gen_addhi3 ( sp , sp , inc ) ) ) ; } } </s>

Common code to change the stack pointer .


<s> static machine_mode arg_promotion ( machine_mode mode ) { if ( mode == QImode || mode == HImode ) return SImode ; return mode ; } </s>

Perform a mode promotion for a function argument with MODE . Return the promoted mode .


<s> inline const BitTracker :: RegisterCell & BitTracker :: lookup ( unsigned Reg ) const { CellMapType :: const_iterator F = Map . find ( Reg ) ; assert ( F != Map . end ( ) ) ; return F -> second ; } </s>

This method finds the value with the given Name in the the symbol table .


<s> void mprocRegisterInfo :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const { } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> int sparc_split_regreg_legitimate ( rtx reg1 , rtx reg2 ) { int regno1 , regno2 ; if ( GET_CODE ( reg1 ) == SUBREG ) reg1 = SUBREG_REG ( reg1 ) ; if ( GET_CODE ( reg1 ) != REG ) return 0 ; regno1 = REGNO ( reg1 ) ; if ( GET_CODE ( reg2 ) == SUBREG ) reg2 = SUBREG_REG ( reg2 ) ; if ( GET_CODE ( reg2 ) != REG ) return 0 ; regno2 = REGNO ( reg2 ) ; if ( SPARC_INT_REG_P ( regno1 ) && SPARC_INT_REG_P ( regno2 ) ) return 1 ; if ( TARGET_VIS3 ) { if ( ( SPARC_INT_REG_P ( regno1 ) && SPARC_FP_REG_P ( regno2 ) ) || ( SPARC_FP_REG_P ( regno1 ) && SPARC_INT_REG_P ( regno2 ) ) ) return 1 ; } return 0 ; } </s>

Like sparc_splitdi_legitimate but for REG < -- > REG moves .


<s> bool X86AsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == ".word" ) return ParseDirectiveWord ( 2 , DirectiveID . getLoc ( ) ) ; else if ( IDVal . startswith ( ".code" ) ) return ParseDirectiveCode ( IDVal , DirectiveID . getLoc ( ) ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> void storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const override { storeRegToStack ( MBB , MBBI , SrcReg , isKill , FrameIndex , RC , TRI , 0 ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> const uint16_t * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( ReserveR9 ) return CSR_NaCl_SaveList ; bool ghcCall = false ; if ( MF ) { const Function * F = MF -> getFunction ( ) ; ghcCall = ( F ? F -> getCallingConv ( ) == CallingConv :: GHC : false ) ; } if ( ghcCall ) { return CSR_GHC_SaveList ; } else { return ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ; } } </s>


<s> SDValue AArch64TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: AND : return PerformANDCombine ( N , DCI ) ; case ISD :: OR : return PerformORCombine ( N , DCI , getSubtarget ( ) ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DCI , getSubtarget ( ) ) ; case ISD :: SETCC : return PerformSETCCCombine ( N , DCI . DAG ) ; case ISD :: VSELECT : return PerformVSelectCombine ( N , DCI . DAG ) ; case ISD :: SIGN_EXTEND : return PerformSignExtendCombine ( N , DCI . DAG ) ; case ISD :: INTRINSIC_WO_CHAIN : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case AArch64ISD :: NEON_VDUPLANE : return CombineVLDDUP ( N , DCI ) ; case AArch64ISD :: NEON_LD2DUP : case AArch64ISD :: NEON_LD3DUP : case AArch64ISD :: NEON_LD4DUP : return CombineBaseUpdate ( N , DCI ) ; case ISD :: INTRINSIC_VOID : case ISD :: INTRINSIC_W_CHAIN : switch ( cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) -> getZExtValue ( ) ) { case Intrinsic :: arm_neon_vld1 : case Intrinsic :: arm_neon_vld2 : case Intrinsic :: arm_neon_vld3 : case Intrinsic :: arm_neon_vld4 : case Intrinsic :: arm_neon_vst1 : case Intrinsic :: arm_neon_vst2 : case Intrinsic :: arm_neon_vst3 : case Intrinsic :: arm_neon_vst4 : case Intrinsic :: arm_neon_vld2lane : case Intrinsic :: arm_neon_vld3lane : case Intrinsic :: arm_neon_vld4lane : case Intrinsic :: aarch64_neon_vld1x2 : case Intrinsic :: aarch64_neon_vld1x3 : case Intrinsic :: aarch64_neon_vld1x4 : case Intrinsic :: aarch64_neon_vst1x2 : case Intrinsic :: aarch64_neon_vst1x3 : case Intrinsic :: aarch64_neon_vst1x4 : case Intrinsic :: arm_neon_vst2lane : case Intrinsic :: arm_neon_vst3lane : case Intrinsic :: arm_neon_vst4lane : return CombineBaseUpdate ( N , DCI ) ; default : break ; } } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Hexagon Hardware Loop Fixup"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> Register getFrameRegister ( const MachineFunction & MF ) const override { return 0 ; } </s>


<s> unsigned getSlotSize ( ) const { return 4 ; } </s>

getSlotSize - Stack slot size in bytes .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addPreserved < SlotIndexes > ( ) ; AU . addPreserved < LiveIntervals > ( ) ; AU . addPreserved < LiveVariables > ( ) ; AU . addRequired < LiveIntervals > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> DecodeStatus NyuziDisassembler :: getInstruction ( MCInst & instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & vStream , raw_ostream & cStream ) const { uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Bytes , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTable32 , instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s> bool XCoreRegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> static bool m32r_rtx_costs ( rtx x , int code , int outer_code ATTRIBUTE_UNUSED , int opno ATTRIBUTE_UNUSED , int * total , bool speed ATTRIBUTE_UNUSED ) { switch ( code ) { case CONST_INT : if ( INT16_P ( INTVAL ( x ) ) ) { * total = 0 ; return true ; } case CONST : case LABEL_REF : case SYMBOL_REF : * total = COSTS_N_INSNS ( 1 ) ; return true ; case CONST_DOUBLE : { rtx high , low ; split_double ( x , & high , & low ) ; * total = COSTS_N_INSNS ( ! INT16_P ( INTVAL ( high ) ) + ! INT16_P ( INTVAL ( low ) ) ) ; return true ; } case MULT : * total = COSTS_N_INSNS ( 3 ) ; return true ; case DIV : case UDIV : case MOD : case UMOD : * total = COSTS_N_INSNS ( 10 ) ; return true ; default : return false ; } } </s>


"pointer offset from symbol maybe incorrect"


"mips16 and nomips16 specified on the same function"

Reset the subtarget for the Mips target .


<s>
static
const
char
*
match_to_right_bracket
(
void
)
{
int
lastpos
=
pos
1
;
while
(
lastpos
<
LINELEN
1
&&
linebuf
[
lastpos
+
1
]
!=
']'
)
{
if
(
linebuf
[
lastpos
+
1
]
==
'\n'
)
fatal
(
"no ']' found before end of line.\n"
)
;
++
lastpos
;
}
if
(
lastpos
>=
LINELEN
1
)
{
diag
(
lastpos
,
"line length overrun.\n"
)
;
exit
(
1
)
;
}
if
(
lastpos
<
pos
)
return
0
;
char
*
buf
=
(
char
*
)
malloc
(
lastpos
pos
+
2
)
;
memcpy
(
buf
,
&
linebuf
[
pos
]
,
lastpos
pos
+
1
)
;
buf
[
lastpos
pos
+
1
]
=
'\0'
;
pos
=
lastpos
+
1
;
return
buf
;
}
</s>

Match a string up to but not including a ' ] ' , and return its value , or zero if there is nothing before the ' ] ' . Error if we do n't find such a character .


"Builtin function %s is only valid for the cell processor"

"Builtin function %s requires the -mvsx option"

"Builtin function %s requires the -mhtm option"

"Builtin function %s requires the -maltivec option"

"Builtin function %s requires the -mpaired option"

"Builtin function %s requires the -mspe option"

"Builtin function %s requires the -mhard-dfp and"

"Builtin function %s requires the -mhard-dfp option"

"Builtin function %s requires the -mpower8-vector option"

"Builtin function %s requires the -mcpu=power9 and"

"Builtin function %s requires the -mcpu=power9 option"

"Builtin function %s requires the -mhard-float and"

"Builtin function %s requires the -mhard-float option"

"Builtin function %s requires the -mfloat128 option"

"Builtin function %s is not supported with the current options"

Raise an error message for a builtin function that is called without the appropriate target options being set .


<s> static int m32r_adjust_priority ( rtx insn , int priority ) { if ( m32r_is_insn ( insn ) && get_attr_insn_size ( insn ) != INSN_SIZE_SHORT ) priority <<= 3 ; return priority ; } </s>

Increase the priority of long instructions so that the short instructions are scheduled ahead of the long ones .


<s> uint64_t ARMGOT :: emit ( MemoryRegion & pRegion ) { uint32_t * buffer = reinterpret_cast < uint32_t * > ( pRegion . begin ( ) ) ; ARMGOTEntry * got = NULL ; uint64_t result = 0x0 ; for ( iterator it = begin ( ) , ie = end ( ) ; it != ie ; ++ it , ++ buffer ) { got = & ( llvm :: cast < ARMGOTEntry > ( ( * it ) ) ) ; * buffer = static_cast < uint32_t > ( got -> getValue ( ) ) ; result += ARMGOTEntry :: EntrySize ; } return result ; } </s>

Output the remark via the diagnostic handler and to the optimization record file .

ARM ARM ARM 0x0 ARM ARMGOTEntry::EntrySize


<s> void PPCHazardRecognizer970 :: EmitInstruction ( SUnit * SU ) { MachineInstr * MI = SU -> getInstr ( ) ; if ( MI -> isDebugInstr ( ) ) return ; unsigned Opcode = MI -> getOpcode ( ) ; bool isFirst , isSingle , isCracked , isLoad , isStore ; PPCII :: PPC970_Unit InstrType = GetInstrType ( Opcode , isFirst , isSingle , isCracked , isLoad , isStore ) ; if ( InstrType == PPCII :: PPC970_Pseudo ) return ; if ( Opcode == PPC :: MTCTR || Opcode == PPC :: MTCTR8 ) HasCTRSet = true ; if ( isStore && NumStores < 4 && ! MI -> memoperands_empty ( ) ) { MachineMemOperand * MO = * MI -> memoperands_begin ( ) ; StoreSize [ NumStores ] = MO -> getSize ( ) ; StoreOffset [ NumStores ] = MO -> getOffset ( ) ; StoreValue [ NumStores ] = MO -> getValue ( ) ; ++ NumStores ; } if ( InstrType == PPCII :: PPC970_BRU || isSingle ) NumIssued = 4 ; ++ NumIssued ; if ( isCracked ) ++ NumIssued ; if ( NumIssued == 5 ) EndDispatchGroup ( ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void MipsPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; if ( getMipsSubtarget ( ) . os16 ( ) ) addPass ( createMipsOs16 ( getMipsTargetMachine ( ) ) ) ; if ( getMipsSubtarget ( ) . inMips16HardFloat ( ) ) addPass ( createMips16HardFloat ( getMipsTargetMachine ( ) ) ) ; addPass ( createPartiallyInlineLibCallsPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

Mips Mips Mips Mips Mips Mips Mips Mips Mips


"Relocation required in an instruction that we cannot encode!"

getMachineOpValue - Return binary encoding of operand .


<s> static bool aarch64_register_saved_on_entry ( int regno ) { return known_ge ( cfun -> machine -> frame . reg_offset [ regno ] , 0 ) ; } </s>

Return true if the register REGNO is saved on entry to the current function .


<s> int mips_class_max_nregs ( enum reg_class class ATTRIBUTE_UNUSED , enum machine_mode mode ) { if ( class == ST_REGS ) return ( GET_MODE_SIZE ( mode ) + 3 ) / 4 ; else return ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } </s>

Implement CLASS_MAX_NREGS . Usually all registers are word-sized . The only supported exception is -mgp64 -msingle-float , which has 64-bit words but 32-bit float registers . A word-based calculation is correct even in that case , since -msingle-float disallows multi-FPR values . The FP status registers are an exception to this rule . They are always 4 bytes wide as they only hold condition code modes , and CCmode is always considered to be 4 bytes wide .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s>
StringRef
getPassName
(
)
const
override
{
return
"SPIRV Assembly Printer"
;
}
</s>


<s>
unsigned
getReg
(
)
const
{
assert
(
Kind
==
Register
&&
"Invalid access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s>
PPC
::
Predicate
PPC
::
getSwappedPredicate
(
PPC
::
Predicate
Opcode
)
{
switch
(
Opcode
)
{
case
PPC
::
PRED_EQ
:
return
PPC
::
PRED_EQ
;
case
PPC
::
PRED_NE
:
return
PPC
::
PRED_NE
;
case
PPC
::
PRED_LT
:
return
PPC
::
PRED_GT
;
case
PPC
::
PRED_GE
:
return
PPC
::
PRED_LE
;
case
PPC
::
PRED_GT
:
return
PPC
::
PRED_LT
;
case
PPC
::
PRED_LE
:
return
PPC
::
PRED_GE
;
case
PPC
::
PRED_NU
:
return
PPC
::
PRED_NU
;
case
PPC
::
PRED_UN
:
return
PPC
::
PRED_UN
;
}
llvm_unreachable
(
"Unknown PPC branch opcode!"
)
;
}
</s>

This is a static version that you can use without an instruction available .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { bool Changed = false ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed = true ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s>
virtual
bool
runOnMachineFunction
(
MachineFunction
&
MF
)
{
PatmosSinglePathInfo
&
PSPI
=
getAnalysis
<
PatmosSinglePathInfo
>
(
)
;
bool
changed
=
false
;
if
(
PSPI
.
isConverting
(
MF
)
)
{
DEBUG
(
dbgs
(
)
<<
"[Single-Path] Preparing "
<<
MF
.
getFunction
(
)
->
getName
(
)
<<
"\n"
)
;
doPrepareFunction
(
MF
)
;
changed
|=
true
;
}
return
changed
;
}
</s>

Patmos
Patmos
Patmos
"[Single-Path] Preparing "
"\n"


<s> bool mips_split_move_insn_p ( rtx dest , rtx src , rtx insn ) { return mips_split_move_p ( dest , src , mips_insn_split_type ( insn ) ) ; } </s>

Return true if a move from SRC to DEST in INSN should be split .


<s> void R600SchedStrategy :: releaseBottomNode ( SUnit * SU ) { } </s>

Currently only scheduling top-down , so this method is empty .


<s> SDValue PPCTargetLowering :: getRecipEstimate ( SDValue Operand , SelectionDAG & DAG , int Enabled , int & RefinementSteps ) const { EVT VT = Operand . getValueType ( ) ; if ( ( VT == MVT :: f32 && Subtarget . hasFRES ( ) ) || ( VT == MVT :: f64 && Subtarget . hasFRE ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasAltivec ( ) ) || ( VT == MVT :: v2f64 && Subtarget . hasVSX ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasQPX ( ) ) || ( VT == MVT :: v4f64 && Subtarget . hasQPX ( ) ) ) { if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = getEstimateRefinementSteps ( VT , Subtarget ) ; return DAG . getNode ( PPCISD :: FRE , SDLoc ( Operand ) , VT , Operand ) ; } return SDValue ( ) ; } </s>

Return a reciprocal estimate value for the input operand .


<s> bool isProfitableToUnpredicate ( MachineBasicBlock & TMBB , MachineBasicBlock & FMBB ) const override { return false ; } </s>

Return true if it 's profitable to unpredicate one side of a 'diamond ' , i.e .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < AArch64Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>


<s> static void rs6000_function_specific_restore ( struct gcc_options * opts , struct gcc_options * , struct cl_target_option * ptr ) { opts -> x_rs6000_isa_flags = ptr -> x_rs6000_isa_flags ; opts -> x_rs6000_isa_flags_explicit = ptr -> x_rs6000_isa_flags_explicit ; ( void ) rs6000_option_override_internal ( false ) ; } </s>


<s> bool enableMachineScheduler ( ) const override { return getGeneration ( ) <= NORTHERN_ISLANDS ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .