<s> static rtx sparc_got ( void ) { if ( ! got_symbol_rtx ) got_symbol_rtx = gen_rtx_SYMBOL_REF ( Pmode , "_GLOBAL_OFFSET_TABLE_" ) ; return got_symbol_rtx ; } </s>

Return the SYMBOL_REF for the Global Offset Table .


<s> static void init_insn_group_barriers ( ) { memset ( rws_sum , 0 , sizeof ( rws_sum ) ) ; first_instruction = 1 ; } </s>

Clear out the state for group_barrier_needed_p at the start of a sequence of insns .


<s> const WebAssemblySubtarget * WebAssemblyTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < WebAssemblySubtarget > ( TargetTriple , CPU , FS , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

WebAssembly WebAssembly WebAssembly "target-cpu" "target-features" WebAssembly


<s> const CallLowering * PPCSubtarget :: getCallLowering ( ) const { return CallLoweringInfo . get ( ) ; } </s>


<s>
bool
AlphaAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
this
->
MF
=
&
MF
;
SetupMachineFunction
(
MF
)
;
O
<<
"\n\n"
;
EmitConstantPool
(
MF
.
getConstantPool
(
)
)
;
EmitJumpTableInfo
(
MF
.
getJumpTableInfo
(
)
,
MF
)
;
const
Function
*
F
=
MF
.
getFunction
(
)
;
OutStreamer
.
SwitchSection
(
getObjFileLowering
(
)
.
SectionForGlobal
(
F
,
Mang
,
TM
)
)
;
EmitAlignment
(
MF
.
getAlignment
(
)
,
F
)
;
switch
(
F
->
getLinkage
(
)
)
{
default
:
llvm_unreachable
(
"Unknown linkage type!"
)
;
case
Function
::
InternalLinkage
:
case
Function
::
PrivateLinkage
:
case
Function
::
LinkerPrivateLinkage
:
break
;
case
Function
::
ExternalLinkage
:
O
<<
"\t.globl "
<<
CurrentFnName
<<
"\n"
;
break
;
case
Function
::
WeakAnyLinkage
:
case
Function
::
WeakODRLinkage
:
case
Function
::
LinkOnceAnyLinkage
:
case
Function
::
LinkOnceODRLinkage
:
O
<<
TAI
->
getWeakRefDirective
(
)
<<
CurrentFnName
<<
"\n"
;
break
;
}
printVisibility
(
CurrentFnName
,
F
->
getVisibility
(
)
)
;
O
<<
"\t.ent "
<<
CurrentFnName
<<
"\n"
;
O
<<
CurrentFnName
<<
":\n"
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
I
!=
MF
.
begin
(
)
)
{
printBasicBlockLabel
(
I
,
true
,
true
)
;
O
<<
'\n'
;
}
for
(
MachineBasicBlock
::
const_iterator
II
=
I
->
begin
(
)
,
E
=
I
->
end
(
)
;
II
!=
E
;
++
II
)
{
++
EmittedInsts
;
printInstruction
(
II
)
;
}
}
O
<<
"\t.end "
<<
CurrentFnName
<<
"\n"
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .

Alpha
Alpha
"\n\n"
"Unknown linkage type!"
"\t.globl "
"\n"
"\n"
"\t.ent "
"\n"
":\n"
"\t.end "
"\n"


<s> static rtx lxvrze_expand_builtin ( rtx target , insn_code icode , rtx * op , machine_mode tmode , machine_mode smode ) { rtx pat , addr ; op [ 1 ] = copy_to_mode_reg ( Pmode , op [ 1 ] ) ; if ( op [ 0 ] == const0_rtx ) addr = gen_rtx_MEM ( tmode , op [ 1 ] ) ; else { op [ 0 ] = copy_to_mode_reg ( Pmode , op [ 0 ] ) ; addr = gen_rtx_MEM ( smode , gen_rtx_PLUS ( Pmode , op [ 1 ] , op [ 0 ] ) ) ; } pat = GEN_FCN ( icode ) ( target , addr ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>

Expand a builtin function that loads a scalar into a vector register with zero extension , and return the expanded rtx .


<s> bool mmix_legitimate_address_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x , bool strict_checking ) { ( ( strict_checking \ && ( REGNO ( X ) <= MMIX_LAST_GENERAL_REGISTER \ || ( reg_renumber [ REGNO ( X ) ] > 0 \ && reg_renumber [ REGNO ( X ) ] <= MMIX_LAST_GENERAL_REGISTER ) ) ) \ || ( ! strict_checking \ && ( REGNO ( X ) <= MMIX_LAST_GENERAL_REGISTER \ || REGNO ( X ) >= FIRST_PSEUDO_REGISTER \ || REGNO ( X ) == ARG_POINTER_REGNUM ) ) ) if ( REG_P ( x ) && MMIX_REG_OK ( x ) ) return 1 ; if ( GET_CODE ( x ) == PLUS ) { rtx x1 = XEXP ( x , 0 ) ; rtx x2 = XEXP ( x , 1 ) ; if ( ! REG_P ( x1 ) ) { rtx tem = x1 ; x1 = x2 ; x2 = tem ; } if ( ! REG_P ( x1 ) || ! MMIX_REG_OK ( x1 ) ) return TARGET_BASE_ADDRESSES && mmix_constant_address_p ( x ) ; if ( REG_P ( x2 ) && MMIX_REG_OK ( x2 ) ) return 1 ; if ( satisfies_constraint_I ( x2 ) ) return 1 ; return 0 ; } return TARGET_BASE_ADDRESSES && mmix_constant_address_p ( x ) ; } </s>

Return 1 if the address is OK , otherwise 0 .


<s> const char * SITargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return AMDGPUTargetLowering :: getTargetNodeName ( Opcode ) ; NODE_NAME_CASE ( VCC_AND ) NODE_NAME_CASE ( VCC_BITCAST ) } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> MCFragment * findAssociatedFragment ( ) const override { return nullptr ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s> MCSymbol * AArch64AsmPrinter :: GetCPISymbol ( unsigned CPID ) const { if ( getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) [ 0 ] ) return OutContext . getOrCreateSymbol ( Twine ( getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) ) + "CPI" + Twine ( getFunctionNumber ( ) ) + "_" + Twine ( CPID ) ) ; return OutContext . getOrCreateSymbol ( Twine ( getDataLayout ( ) . getPrivateGlobalPrefix ( ) ) + "CPI" + Twine ( getFunctionNumber ( ) ) + "_" + Twine ( CPID ) ) ; } </s>

Return the symbol for the specified constant pool entry .


<s> memory_access_direction determine_access_direction ( rtx_insn * insn ) { int post_update_rtx_index ; rtx plus_rtx ; rtx mem_rtx ; rtx offset_rtx ; switch ( get_attr_type ( insn ) ) { case TYPE_LOAD_MULTIPLE : gcc_assert ( parallel_elements ( insn ) >= 2 ) ; post_update_rtx_index = find_post_update_rtx ( insn ) ; if ( post_update_rtx_index != - 1 ) plus_rtx = SET_SRC ( parallel_element ( insn , post_update_rtx_index ) ) ; else { mem_rtx = SET_SRC ( parallel_element ( insn , 1 ) ) ; if ( GET_CODE ( mem_rtx ) == UNSPEC ) mem_rtx = XVECEXP ( mem_rtx , 0 , 0 ) ; gcc_assert ( MEM_P ( mem_rtx ) ) ; plus_rtx = XEXP ( mem_rtx , 0 ) ; } break ; case TYPE_STORE_MULTIPLE : gcc_assert ( parallel_elements ( insn ) >= 2 ) ; post_update_rtx_index = find_post_update_rtx ( insn ) ; if ( post_update_rtx_index != - 1 ) plus_rtx = SET_SRC ( parallel_element ( insn , post_update_rtx_index ) ) ; else { mem_rtx = SET_DEST ( parallel_element ( insn , 1 ) ) ; if ( GET_CODE ( mem_rtx ) == UNSPEC ) mem_rtx = XVECEXP ( mem_rtx , 0 , 0 ) ; gcc_assert ( MEM_P ( mem_rtx ) ) ; plus_rtx = XEXP ( mem_rtx , 0 ) ; } break ; case TYPE_LOAD : case TYPE_STORE : mem_rtx = extract_mem_rtx ( insn ) ; switch ( GET_CODE ( XEXP ( mem_rtx , 0 ) ) ) { case POST_INC : return MEM_ACCESS_DIR_POS ; case POST_DEC : return MEM_ACCESS_DIR_NEG ; case PLUS : plus_rtx = XEXP ( mem_rtx , 0 ) ; break ; case POST_MODIFY : plus_rtx = XEXP ( XEXP ( mem_rtx , 0 ) , 1 ) ; break ; default : gcc_unreachable ( ) ; } break ; default : gcc_unreachable ( ) ; } gcc_assert ( GET_CODE ( plus_rtx ) == PLUS ) ; offset_rtx = XEXP ( plus_rtx , 1 ) ; if ( GET_CODE ( offset_rtx ) == CONST_INT ) { if ( INTVAL ( offset_rtx ) < 0 ) return MEM_ACCESS_DIR_NEG ; else return MEM_ACCESS_DIR_POS ; } return MEM_ACCESS_DIR_UNKNOWN ; } </s>

Determine the memory access direction of a load/store insn .


<s> bool PhysicalRegisterInfo :: alias ( RegisterRef RA , RegisterRef RB ) const { assert ( TargetRegisterInfo :: isPhysicalRegister ( RA . Reg ) ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( RB . Reg ) ) ; MCRegUnitMaskIterator UMA ( RA . Reg , & TRI ) ; MCRegUnitMaskIterator UMB ( RB . Reg , & TRI ) ; while ( UMA . isValid ( ) && UMB . isValid ( ) ) { std :: pair < uint32_t , LaneBitmask > PA = * UMA ; std :: pair < uint32_t , LaneBitmask > PB = * UMB ; if ( PA . first == PB . first ) { if ( PA . second . none ( ) || PB . second . none ( ) ) return true ; LaneBitmask LA = PA . second & RA . Mask ; LaneBitmask LB = PB . second & RB . Mask ; if ( LA . any ( ) && LB . any ( ) ) { unsigned Root = * MCRegUnitRootIterator ( PA . first , & TRI ) ; uint32_t SubA = TRI . getSubRegIndex ( RA . Reg , Root ) ; uint32_t SubB = TRI . getSubRegIndex ( RB . Reg , Root ) ; const TargetRegisterClass * RC = RegInfos [ Root ] . RegClass ; LaneBitmask RCMask = RC != nullptr ? RC -> LaneMask : LaneBitmask ( 0x1 ) ; LaneBitmask MaskA = TRI . reverseComposeSubRegIndexLaneMask ( SubA , LA ) ; LaneBitmask MaskB = TRI . reverseComposeSubRegIndexLaneMask ( SubB , LB ) ; if ( ( MaskA & MaskB & RCMask ) . any ( ) ) return true ; } ++ UMA ; ++ UMB ; continue ; } if ( PA . first < PB . first ) ++ UMA ; else if ( PB . first < PA . first ) ++ UMB ; } return false ; } </s>

alias - If one of the pointers is to a global that we are tracking , and the other is some random pointer , we know there can not be an alias , because the address of the global is n't taken .


<s>
unsigned
ARMBaseInstrInfo
::
getPartialRegUpdateClearance
(
const
MachineInstr
&
MI
,
unsigned
OpNum
,
const
TargetRegisterInfo
*
TRI
)
const
{
auto
PartialUpdateClearance
=
Subtarget
.
getPartialUpdateClearance
(
)
;
if
(
!
PartialUpdateClearance
)
return
0
;
assert
(
TRI
&&
"Need TRI instance"
)
;
const
MachineOperand
&
MO
=
MI
.
getOperand
(
OpNum
)
;
if
(
MO
.
readsReg
(
)
)
return
0
;
unsigned
Reg
=
MO
.
getReg
(
)
;
int
UseOp
=
1
;
switch
(
MI
.
getOpcode
(
)
)
{
case
ARM
::
VLDRS
:
case
ARM
::
FCONSTS
:
case
ARM
::
VMOVSR
:
case
ARM
::
VMOVv8i8
:
case
ARM
::
VMOVv4i16
:
case
ARM
::
VMOVv2i32
:
case
ARM
::
VMOVv2f32
:
case
ARM
::
VMOVv1i64
:
UseOp
=
MI
.
findRegisterUseOperandIdx
(
Reg
,
false
,
TRI
)
;
break
;
case
ARM
::
VLD1LNd32
:
UseOp
=
3
;
break
;
default
:
return
0
;
}
if
(
UseOp
!=
1
&&
MI
.
getOperand
(
UseOp
)
.
readsReg
(
)
)
return
0
;
if
(
TargetRegisterInfo
::
isVirtualRegister
(
Reg
)
)
{
if
(
!
MO
.
getSubReg
(
)
||
MI
.
readsVirtualRegister
(
Reg
)
)
return
0
;
}
else
if
(
ARM
::
SPRRegClass
.
contains
(
Reg
)
)
{
unsigned
DReg
=
TRI
->
getMatchingSuperReg
(
Reg
,
ARM
::
ssub_0
,
&
ARM
::
DPRRegClass
)
;
if
(
!
DReg
||
!
MI
.
definesRegister
(
DReg
,
TRI
)
)
return
0
;
}
return
PartialUpdateClearance
;
}
</s>

Inform the BreakFalseDeps pass how many idle instructions we would like before a partial register update .


<s> BitVector XCoreRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const XCoreFrameLowering * TFI = getFrameLowering ( MF ) ; Reserved . set ( XCore :: CP ) ; Reserved . set ( XCore :: DP ) ; Reserved . set ( XCore :: SP ) ; Reserved . set ( XCore :: LR ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( XCore :: R10 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .

XCore XCore XCore XCore::CP XCore::DP XCore::SP XCore::LR XCore::R10


"Wrong register class for memory operand."

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> bool MSP430FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) BuildMI ( MBB , MI , DL , TII . get ( MSP430 :: POP16r ) , CSI [ i ] . getReg ( ) ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) { switch ( Op . getOpcode ( ) ) { case ISD :: AND : return LowerANDOR ( Op , DAG ) ; case ISD :: BRCOND : return LowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return LowerConstantPool ( Op , DAG ) ; case ISD :: DYNAMIC_STACKALLOC : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case ISD :: FP_TO_SINT : return LowerFP_TO_SINT ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return LowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( Op , DAG ) ; case ISD :: OR : return LowerANDOR ( Op , DAG ) ; case ISD :: SELECT : return LowerSELECT ( Op , DAG ) ; case ISD :: SETCC : return LowerSETCC ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::AND ISD::BRCOND ISD::ConstantPool ISD::DYNAMIC_STACKALLOC ISD::FP_TO_SINT ISD::GlobalAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::OR ISD::SELECT ISD::SETCC


<s> static unsigned int constant_pool_broadcast ( void ) { timevar_push ( TV_MACH_DEP ) ; rtx_insn * insn ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( INSN_P ( insn ) ) replace_constant_pool_with_broadcast ( insn ) ; } timevar_pop ( TV_MACH_DEP ) ; return 0 ; } </s>

For const vector having one duplicated value , there 's no need to put whole vector in the constant pool when target supports embedded broadcast .


<s> bool Cpu0TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> static rtx sparc_function_value_1 ( const_tree type , machine_mode mode , bool outgoing ) { int regbase = ( outgoing ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST ) ; enum mode_class mclass = GET_MODE_CLASS ( mode ) ; int regno ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( ( TARGET_ARCH32 && size <= 8 ) || ( TARGET_ARCH64 && size <= 32 ) ) ; if ( mode == BLKmode ) return function_arg_vector_value ( size , SPARC_FP_ARG_FIRST ) ; mclass = MODE_FLOAT ; } if ( TARGET_ARCH64 && type ) { if ( TREE_CODE ( type ) == RECORD_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 32 ) ; return function_arg_record_value ( type , mode , 0 , 1 , regbase ) ; } else if ( TREE_CODE ( type ) == UNION_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 32 ) ; return function_arg_union_value ( size , mode , 0 , regbase ) ; } else if ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) ; else if ( AGGREGATE_TYPE_P ( type ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 32 ) ; mode = int_mode_for_size ( size * BITS_PER_UNIT , 0 ) . else_blk ( ) ; if ( mode == BLKmode ) return function_arg_union_value ( size , mode , 0 , regbase ) ; else mclass = MODE_INT ; } else if ( mclass == MODE_INT && GET_MODE_SIZE ( mode ) < UNITS_PER_WORD ) mode = word_mode ; } else if ( TARGET_ARCH32 && ! ( type && AGGREGATE_TYPE_P ( type ) ) && mclass == MODE_INT && GET_MODE_SIZE ( mode ) < UNITS_PER_WORD ) mode = word_mode ; if ( ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) && TARGET_FPU ) regno = SPARC_FP_ARG_FIRST ; else regno = regbase ; return gen_rtx_REG ( mode , regno ) ; } </s>

Handle TARGET_FUNCTION_VALUE , and TARGET_LIBCALL_VALUE target hook . For v9 , function return values are subject to the same rules as arguments , except that up to 32 bytes may be returned in registers .


<s>
void
assignValueToAddress
(
unsigned
ValVReg
,
unsigned
Addr
,
uint64_t
Size
,
MachinePointerInfo
&
MPO
,
CCValAssign
&
VA
)
override
{
assert
(
(
Size
==
1
||
Size
==
2
||
Size
==
4
)
&&
"Unsupported size"
)
;
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
SExt
||
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExt
)
{
Size
=
4
;
assert
(
MRI
.
getType
(
ValVReg
)
.
isScalar
(
)
&&
"Only scalars supported atm"
)
;
MRI
.
setType
(
ValVReg
,
LLT
::
scalar
(
32
)
)
;
}
auto
MMO
=
MIRBuilder
.
getMF
(
)
.
getMachineMemOperand
(
MPO
,
MachineMemOperand
::
MOLoad
,
Size
,
0
)
;
MIRBuilder
.
buildLoad
(
ValVReg
,
Addr
,
*
MMO
)
;
}
</s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> bool Thumb1FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( ARM :: tPUSH ) ) ; AddDefaultPred ( MIB ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; bool isKill = true ; if ( Reg == ARM :: LR ) { MachineFunction & MF = * MBB . getParent ( ) ; if ( MF . getFrameInfo ( ) . isReturnAddressTaken ( ) && MF . getRegInfo ( ) . isLiveIn ( Reg ) ) isKill = false ; } if ( isKill ) MBB . addLiveIn ( Reg ) ; MIB . addReg ( Reg , getKillRegState ( isKill ) ) ; } MIB . setMIFlags ( MachineInstr :: FrameSetup ) ; return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s>
bool
AVRAsmParser
::
MatchAndEmitInstruction
(
SMLoc
Loc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MatchingInlineAsm
)
;
switch
(
MatchResult
)
{
case
Match_Success
:
return
emit
(
Inst
,
Loc
,
Out
)
;
case
Match_MissingFeature
:
return
missingFeature
(
Loc
,
ErrorInfo
)
;
case
Match_InvalidOperand
:
return
invalidOperand
(
Loc
,
Operands
,
ErrorInfo
)
;
case
Match_MnemonicFail
:
return
Error
(
Loc
,
"invalid instruction"
)
;
case
Match_InvalidRegisterOnTiny
:
return
Error
(
Loc
,
"invalid register on avrtiny"
)
;
default
:
return
true
;
}
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .

AVR
AVR
"invalid instruction"
"invalid register on avrtiny"


<s> inline tree function_instance :: scalar_type ( unsigned int i ) const { return scalar_types [ type_suffix ( i ) . vector_type ] ; } </s>

Return the scalar type associated with type suffix I .


"insertBranch must not be told to insert a fallthrough"

"VE branch conditions should have three component!"

"Unconditional branch with multiple successors!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> int unicosmk_initial_elimination_offset ( int from , int to ) { int fixed_size ; fixed_size = alpha_sa_size ( ) ; if ( fixed_size != 0 ) fixed_size += 48 ; if ( from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) return - fixed_size ; else if ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) return 0 ; else if ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) return ( ALPHA_ROUND ( current_function_outgoing_args_size ) + ALPHA_ROUND ( get_frame_size ( ) ) ) ; else if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) return ( ALPHA_ROUND ( fixed_size ) + ALPHA_ROUND ( get_frame_size ( ) + current_function_outgoing_args_size ) ) ; else gcc_unreachable ( ) ; } </s>

Define the offset between two registers , one to be eliminated , and the other its replacement , at the start of a routine .


<s>
MCSymbol
*
TeeRISCMCInstLower
::
GetExternalSymbolSymbol
(
const
MachineOperand
&
MO
)
const
{
switch
(
MO
.
getTargetFlags
(
)
)
{
default
:
llvm_unreachable
(
"Unknown target flag on GV operand"
)
;
case
0
:
break
;
}
return
Printer
.
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
;
}
</s>

Return the MCSymbol for the specified ExternalSymbol .

TeeRISC
TeeRISC
"Unknown target flag on GV operand"
0


<s> bool PPCCallLowering :: lowerCall ( MachineIRBuilder & MIRBuilder , CallLoweringInfo & Info ) const { return false ; } </s>

This hook must be implemented to lower the given call instruction , including argument and return value marshalling .


<s> static rtx tilegx_text_label_symbol ( void ) { return cfun -> machine -> text_label_symbol ; } </s>

Return the rtx containing SYMBOL_REF to the text label .


<s> bool riscv_gimple_fold_builtin ( gimple_stmt_iterator * gsi ) { gcall * stmt = as_a < gcall * > ( gsi_stmt ( * gsi ) ) ; tree fndecl = gimple_call_fndecl ( stmt ) ; unsigned int code = DECL_MD_FUNCTION_CODE ( fndecl ) ; unsigned int subcode = code >> RISCV_BUILTIN_SHIFT ; gimple * new_stmt = NULL ; switch ( code & RISCV_BUILTIN_CLASS ) { case RISCV_BUILTIN_GENERAL : new_stmt = NULL ; break ; case RISCV_BUILTIN_VECTOR : new_stmt = riscv_vector :: gimple_fold_builtin ( subcode , gsi , stmt ) ; break ; } if ( ! new_stmt ) return false ; gsi_replace ( gsi , new_stmt , false ) ; return true ; } </s>


<s>
void
NVPTXAsmPrinter
::
emitImplicitDef
(
const
MachineInstr
*
MI
)
const
{
Register
RegNo
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
if
(
Register
::
isVirtualRegister
(
RegNo
)
)
{
OutStreamer
->
AddComment
(
Twine
(
"implicit-def: "
)
+
getVirtualRegisterName
(
RegNo
)
)
;
}
else
{
const
NVPTXSubtarget
&
STI
=
MI
->
getMF
(
)
->
getSubtarget
<
NVPTXSubtarget
>
(
)
;
OutStreamer
->
AddComment
(
Twine
(
"implicit-def: "
)
+
STI
.
getRegisterInfo
(
)
->
getName
(
RegNo
)
)
;
}
OutStreamer
->
AddBlankLine
(
)
;
}
</s>

Targets can override this to customize the output of IMPLICIT_DEF instructions in verbose mode .

NVPTX
NVPTX
0
"implicit-def: "
NVPTX
NVPTX
"implicit-def: "


<s> bool ARMBaseRegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> void MipsSETargetLowering :: getOpndList ( SmallVectorImpl < SDValue > & Ops , std :: deque < std :: pair < unsigned , SDValue > > & RegsToPass , bool IsPICCall , bool GlobalOrExternal , bool InternalLinkage , bool IsCallReloc , CallLoweringInfo & CLI , SDValue Callee , SDValue Chain ) const { Ops . push_back ( Callee ) ; MipsTargetLowering :: getOpndList ( Ops , RegsToPass , IsPICCall , GlobalOrExternal , InternalLinkage , IsCallReloc , CLI , Callee , Chain ) ; } </s>

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineRegionInfoPass > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static bool csky_can_use_ldstm ( int mask , int * br , int * er ) { int regno ; int begin_reg = 0 , end_reg = 0 ; int count = 0 ; if ( ! TARGET_MULTIPLE_STLD ) return false ; if ( mask & 0xf ) return false ; for ( regno = 4 ; regno <= 11 ; regno ++ ) { if ( mask & 1 << regno ) { if ( ! begin_reg ) begin_reg = regno ; end_reg = regno ; count ++ ; } else if ( begin_reg ) break ; } if ( count >= CSKY_MIN_MULTIPLE_STLD && count <= CSKY_MAX_MULTIPLE_STLD ) { if ( br ) * br = begin_reg ; if ( er ) * er = end_reg ; return true ; } return false ; } </s>

Return true if store/load multiple instructions can be used to save/restore at least some of the registers indicated by MASK . Unlike the push/pop case , this does handle partial ranges . Set * BR and * ER to the beginning and end ( respectively ) of the register range that can be handled .


<s> static void riscv_setup_incoming_varargs ( cumulative_args_t cum , machine_mode mode , tree type , int * pretend_size ATTRIBUTE_UNUSED , int no_rtl ) { CUMULATIVE_ARGS local_cum ; int gp_saved ; local_cum = * get_cumulative_args ( cum ) ; riscv_function_arg_advance ( pack_cumulative_args ( & local_cum ) , mode , type , 1 ) ; gp_saved = MAX_ARGS_IN_REGISTERS - local_cum . num_gprs ; if ( ! no_rtl && gp_saved > 0 ) { rtx ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , REG_PARM_STACK_SPACE ( cfun -> decl ) - gp_saved * UNITS_PER_WORD ) ; rtx mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . num_gprs + GP_ARG_FIRST , mem , gp_saved ) ; } if ( REG_PARM_STACK_SPACE ( cfun -> decl ) == 0 ) cfun -> machine -> varargs_size = gp_saved * UNITS_PER_WORD ; } </s>


<s> VariantKind getKind ( ) const { return Kind ; } </s>


<s> static rtx csky_libcall_value ( machine_mode mode , const_rtx libcall ATTRIBUTE_UNUSED ) { if ( FUNCTION_VARG_MODE_P ( mode ) ) { return gen_rtx_REG ( mode , CSKY_FIRST_VFP_REGNUM ) ; } return gen_rtx_REG ( mode , CSKY_FIRST_RET_REGNUM ) ; } </s>


<s> static rtx F ( rtx x ) { RTX_FRAME_RELATED_P ( x ) = 1 ; return x ; } </s>

We use this to wrap all emitted insns in the prologue , so they get the `` frame-related '' ( /f ) flag set .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"R600 Control Flow Finalizer Pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < DominatorTree > ( ) ; AU . addPreserved < DominatorTree > ( ) ; RegionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> SDValue PPCTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { if ( Subtarget . isAIXABI ( ) ) return LowerFormalArguments_AIX ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; if ( Subtarget . is64BitELFABI ( ) ) return LowerFormalArguments_64SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; if ( Subtarget . is32BitELFABI ( ) ) return LowerFormalArguments_32SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; return LowerFormalArguments_Darwin ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> bool HexagonCopyToCombine :: runOnMachineFunction ( MachineFunction & MF ) { if ( IsCombinesDisabled ) return false ; bool HasChanged = false ; TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; TII = static_cast < const HexagonInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; ShouldCombineAggressively = MF . getTarget ( ) . getOptLevel ( ) <= CodeGenOpt :: Default ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( * BI ) ; for ( MachineBasicBlock :: iterator MI = BI -> begin ( ) , End = BI -> end ( ) ; MI != End ; ) { MachineInstr * I1 = MI ++ ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( I1 ) ) continue ; if ( ! isCombinableInstType ( I1 , TII , ShouldCombineAggressively ) ) continue ; bool DoInsertAtI1 = false ; MachineInstr * I2 = findPairable ( I1 , DoInsertAtI1 ) ; if ( I2 ) { HasChanged = true ; combine ( I1 , I2 , MI , DoInsertAtI1 ) ; } } } return HasChanged ; } </s>

runOnMachineFunction - Emit the function body .


<s> void MSP430FrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MSP430MachineFunctionInfo * MSP430FI = MF . getInfo < MSP430MachineFunctionInfo > ( ) ; const MSP430InstrInfo & TII = * static_cast < const MSP430InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; uint64_t NumBytes = 0 ; if ( hasFP ( MF ) ) { uint64_t FrameSize = StackSize - 2 ; NumBytes = FrameSize - MSP430FI -> getCalleeSavedFrameSize ( ) ; MFI -> setOffsetAdjustment ( - NumBytes ) ; BuildMI ( MBB , MBBI , DL , TII . get ( MSP430 :: PUSH16r ) ) . addReg ( MSP430 :: FPW , RegState :: Kill ) ; BuildMI ( MBB , MBBI , DL , TII . get ( MSP430 :: MOV16rr ) , MSP430 :: FPW ) . addReg ( MSP430 :: SPW ) ; for ( MachineFunction :: iterator I = std :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( MSP430 :: FPW ) ; } else NumBytes = StackSize - MSP430FI -> getCalleeSavedFrameSize ( ) ; while ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == MSP430 :: PUSH16r ) ) ++ MBBI ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes ) { if ( NumBytes ) { MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( MSP430 :: SUB16ri ) , MSP430 :: SPW ) . addReg ( MSP430 :: SPW ) . addImm ( NumBytes ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; } } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> const MCExpr * AArch64TargetStreamer :: addConstantPoolEntry ( const MCExpr * Expr , unsigned Size ) { return ConstantPools -> addEntry ( Streamer , Expr , Size ) ; } </s>

Add a new entry to the constant pool for the current section and return an MCExpr that can be used to refer to the constant pool location .


<s> bool runOnMachineFunction ( MachineFunction & F ) { bool Changed = false ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; return Changed ; } </s>


<s> rtx expand ( function_expander & e ) const override { machine_mode mode = GET_MODE ( e . target ) ; rtx vlenb = gen_int_mode ( BYTES_PER_RISCV_VECTOR , mode ) ; emit_move_insn ( e . target , vlenb ) ; return e . target ; } </s>


<s> std :: pair < unsigned , const TargetRegisterClass * > XNCMTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'r' : if ( VT == MVT :: i8 ) return std :: make_pair ( 0U , XNCM :: GR8RegisterClass ) ; return std :: make_pair ( 0U , XNCM :: GR16RegisterClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> bool WebAssemblyTargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * ) const { return true ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> bool X86AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { static const uint8_t Nops [ 10 ] [ 10 ] = { { 0x90 } , { 0x66 , 0x90 } , { 0x0f , 0x1f , 0x00 } , { 0x0f , 0x1f , 0x40 , 0x00 } , { 0x0f , 0x1f , 0x44 , 0x00 , 0x00 } , { 0x66 , 0x0f , 0x1f , 0x44 , 0x00 , 0x00 } , { 0x0f , 0x1f , 0x80 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x66 , 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x66 , 0x2e , 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , } ; if ( ! HasNopl ) { for ( uint64_t i = 0 ; i < Count ; ++ i ) OW -> Write8 ( 0x90 ) ; return true ; } do { const uint8_t ThisNopLength = ( uint8_t ) std :: min ( Count , MaxNopLength ) ; const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10 ; for ( uint8_t i = 0 ; i < Prefixes ; i ++ ) OW -> Write8 ( 0x66 ) ; const uint8_t Rest = ThisNopLength - Prefixes ; for ( uint8_t i = 0 ; i < Rest ; i ++ ) OW -> Write8 ( Nops [ Rest - 1 ] [ i ] ) ; Count -= ThisNopLength ; } while ( Count != 0 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> MachineInstrBuilder SIInstrInfo :: buildIndirectWrite ( MachineBasicBlock * MBB , MachineBasicBlock :: iterator I , unsigned ValueReg , unsigned Address , unsigned OffsetReg ) const { const DebugLoc & DL = MBB -> findDebugLoc ( I ) ; unsigned IndirectBaseReg = AMDGPU :: VReg_32RegClass . getRegister ( getIndirectIndexBegin ( * MBB -> getParent ( ) ) ) ; return BuildMI ( * MBB , I , DL , get ( AMDGPU :: SI_INDIRECT_DST_V1 ) ) . addReg ( IndirectBaseReg , RegState :: Define ) . addOperand ( I -> getOperand ( 0 ) ) . addReg ( IndirectBaseReg ) . addReg ( OffsetReg ) . addImm ( 0 ) . addReg ( ValueReg ) ; } </s>

Build instruction ( s ) for an indirect register write .


<s> int c4x_S_constraint ( rtx op ) { enum machine_mode mode = GET_MODE ( op ) ; if ( GET_CODE ( op ) != MEM ) return 0 ; op = XEXP ( op , 0 ) ; switch ( GET_CODE ( op ) ) { case REG : return 1 ; case PRE_MODIFY : case POST_MODIFY : { rtx op0 = XEXP ( op , 0 ) ; rtx op1 = XEXP ( op , 1 ) ; if ( ( GET_CODE ( op1 ) != PLUS && GET_CODE ( op1 ) != MINUS ) || ( op0 != XEXP ( op1 , 0 ) ) ) return 0 ; op0 = XEXP ( op1 , 0 ) ; op1 = XEXP ( op1 , 1 ) ; return REG_P ( op0 ) && REG_P ( op1 ) ; } break ; case PLUS : { rtx op0 = XEXP ( op , 0 ) ; rtx op1 = XEXP ( op , 1 ) ; if ( ! REG_P ( op0 ) ) return 0 ; if ( REG_P ( op1 ) ) return 1 ; if ( GET_CODE ( op1 ) != CONST_INT ) return 0 ; if ( mode == HImode || mode == HFmode ) return IS_DISP1_OFF_CONST ( INTVAL ( op1 ) ) ; return IS_DISP1_CONST ( INTVAL ( op1 ) ) ; } break ; default : break ; } return 0 ; } </s>

ARx + 1-bit unsigned const or IRn * ARx , * +ARx ( 1 ) , * -ARx ( 1 ) , * +ARx ( IRn ) , * -Arx ( IRn ) We do n't include the pre/post inc/dec forms here since they are handled by the < > constraints .


<s> virtual MachineInstr * foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const { return 0 ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> unsigned M68kAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & Op , unsigned Kind ) { M68kOperand & Operand = ( M68kOperand & ) Op ; switch ( Kind ) { case MCK_XR16 : case MCK_SPILL : if ( Operand . isReg ( ) && checkRegisterClass ( Operand . getReg ( ) , true , true , true ) ) { return Match_Success ; } break ; case MCK_AR16 : case MCK_AR32 : if ( Operand . isReg ( ) && checkRegisterClass ( Operand . getReg ( ) , false , true , true ) ) { return Match_Success ; } break ; case MCK_AR32_NOSP : if ( Operand . isReg ( ) && checkRegisterClass ( Operand . getReg ( ) , false , true , false ) ) { return Match_Success ; } break ; case MCK_DR8 : case MCK_DR16 : case MCK_DR32 : if ( Operand . isReg ( ) && checkRegisterClass ( Operand . getReg ( ) , true , false , false ) ) { return Match_Success ; } break ; case MCK_AR16_TC : if ( Operand . isReg ( ) && ( ( Operand . getReg ( ) == M68k :: A0 ) || ( Operand . getReg ( ) == M68k :: A1 ) ) ) { return Match_Success ; } break ; case MCK_DR16_TC : if ( Operand . isReg ( ) && ( ( Operand . getReg ( ) == M68k :: D0 ) || ( Operand . getReg ( ) == M68k :: D1 ) ) ) { return Match_Success ; } break ; case MCK_XR16_TC : if ( Operand . isReg ( ) && ( ( Operand . getReg ( ) == M68k :: D0 ) || ( Operand . getReg ( ) == M68k :: D1 ) || ( Operand . getReg ( ) == M68k :: A0 ) || ( Operand . getReg ( ) == M68k :: A1 ) ) ) { return Match_Success ; } break ; } return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> static bool addr_generation_dependency_p ( rtx dep_rtx , rtx insn ) { rtx target , pat ; if ( GET_CODE ( dep_rtx ) == INSN ) dep_rtx = PATTERN ( dep_rtx ) ; if ( GET_CODE ( dep_rtx ) == SET ) { target = SET_DEST ( dep_rtx ) ; if ( GET_CODE ( target ) == STRICT_LOW_PART ) target = XEXP ( target , 0 ) ; while ( GET_CODE ( target ) == SUBREG ) target = SUBREG_REG ( target ) ; if ( GET_CODE ( target ) == REG ) { int regno = REGNO ( target ) ; if ( s390_safe_attr_type ( insn ) == TYPE_LA ) { pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == PARALLEL ) { gcc_assert ( XVECLEN ( pat , 0 ) == 2 ) ; pat = XVECEXP ( pat , 0 , 0 ) ; } gcc_assert ( GET_CODE ( pat ) == SET ) ; return refers_to_regno_p ( regno , regno + 1 , SET_SRC ( pat ) , 0 ) ; } else if ( get_attr_atype ( insn ) == ATYPE_AGEN ) return reg_used_in_mem_p ( regno , PATTERN ( insn ) ) ; } } return false ; } </s>

Returns true if expression DEP_RTX sets an address register used by instruction INSN to address memory .


<s> std :: pair < unsigned , unsigned > ARMBaseInstrInfo :: decomposeMachineOperandsTargetFlags ( unsigned TF ) const { const unsigned Mask = ARMII :: MO_OPTION_MASK ; return std :: make_pair ( TF & Mask , TF & ~ Mask ) ; } </s>

Decompose the machine operand 's target flags into two values - the direct target flag value and any of bit flags that are applied .


<s>
static
void
arm_print_asm_arch_directives
(
)
{
const
arch_option
*
arch
=
arm_parse_arch_option_name
(
all_architectures
,
"-march"
,
arm_active_target
.
arch_name
)
;
auto_sbitmap
opt_bits
(
isa_num_bits
)
;
gcc_assert
(
arch
)
;
asm_fprintf
(
asm_out_file
,
"\t.arch %s\n"
,
arm_active_target
.
arch_name
)
;
arm_last_printed_arch_string
=
arm_active_target
.
arch_name
;
if
(
!
arch
->
common
.
extensions
)
return
;
for
(
const
struct
cpu_arch_extension
*
opt
=
arch
->
common
.
extensions
;
opt
->
name
!=
;
opt
++
)
{
if
(
!
opt
->
remove
)
{
arm_initialize_isa
(
opt_bits
,
opt
->
isa_bits
)
;
if
(
bitmap_subset_p
(
opt_bits
,
arm_active_target
.
isa
)
&&
!
bitmap_subset_p
(
opt_bits
,
isa_all_fpubits
)
)
asm_fprintf
(
asm_out_file
,
"\t.arch_extension %s\n"
,
opt
->
name
)
;
}
}
}
</s>

Print .arch and .arch_extension directives corresponding to the current architecture configuration .

arm
"-march"
"\t.arch %s\n"
"\t.arch_extension %s\n"


<s> virtual const TargetRegisterClass * getCFGStructurizerRegClass ( MVT VT ) const { assert ( ! "Unimplemented" ) ; return nullptr ; } </s>

get the register class of the specified type to use in the CFGStructurizer


<s> const uint32_t * P2RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { LLVM_DEBUG ( errs ( ) << CSR_RegMask [ 0 ] << "\n" ) ; return CSR_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
bool
PPCAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
{
if
(
ExtraCode
[
1
]
!=
0
)
return
true
;
switch
(
ExtraCode
[
0
]
)
{
default
:
return
true
;
case
'y'
:
{
const
char
*
RegName
=
"r0"
;
if
(
!
Subtarget
->
isDarwin
(
)
)
RegName
=
PPCRegisterInfo
::
stripRegisterPrefix
(
RegName
)
;
O
<<
RegName
<<
", "
;
printOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
}
case
'U'
:
case
'X'
:
{
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
return
false
;
}
}
}
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
O
<<
"0("
;
printOperand
(
MI
,
OpNo
,
O
)
;
O
<<
")"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> SDValue AArch64TargetLowering :: getTargetNode ( ConstantPoolSDNode * N , EVT Ty , SelectionDAG & DAG , unsigned Flag ) const { return DAG . getTargetConstantPool ( N -> getConstVal ( ) , Ty , N -> getAlignment ( ) , N -> getOffset ( ) , Flag ) ; } </s>

Retrieve the target node this edge connects to .


<s> unsigned PPCRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; if ( ! Subtarget . isPPC64 ( ) ) return TFI -> hasFP ( MF ) ? PPC :: R31 : PPC :: R1 ; else return TFI -> hasFP ( MF ) ? PPC :: X31 : PPC :: X1 ; } </s>


<s>
void
WebAssemblyTargetAsmStreamer
::
emitGlobalType
(
const
MCSymbolWasm
*
Sym
)
{
assert
(
Sym
->
isGlobal
(
)
)
;
OS
<<
"\t.globaltype\t"
<<
Sym
->
getName
(
)
<<
", "
<<
WebAssembly
::
TypeToString
(
static_cast
<
wasm
::
ValType
>
(
Sym
->
getGlobalType
(
)
.
Type
)
)
<<
'\n'
;
}
</s>

WebAssembly
WebAssembly
"\t.globaltype\t"
", "
WebAssembly::TypeToString
wasm::ValType


<s> bool Inserter :: runOnMachineFunction ( MachineFunction & F ) { Cpu0FunctionInfo * Cpu0FI = F . getInfo < Cpu0FunctionInfo > ( ) ; const TargetSubtargetInfo * STI = TM . getSubtargetImpl ( * ( F . getFunction ( ) ) ) ; const TargetInstrInfo * TII = STI -> getInstrInfo ( ) ; if ( ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) || ( ! Cpu0FI -> globalBaseRegFixed ( ) ) ) return false ; bool Changed = false ; int FI = Cpu0FI -> getGPFI ( ) ; for ( MachineFunction :: iterator MFI = F . begin ( ) , MFE = F . end ( ) ; MFI != MFE ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; MachineBasicBlock :: iterator I = MFI -> begin ( ) ; if ( MBB . isEHPad ( ) ) { for ( ; I -> getOpcode ( ) != TargetOpcode :: EH_LABEL ; ++ I ) ; ++ I ; DebugLoc dl = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; BuildMI ( MBB , I , dl , TII -> get ( Cpu0 :: LD ) , Cpu0 :: GP ) . addFrameIndex ( FI ) . addImm ( 0 ) ; Changed = true ; } while ( I != MFI -> end ( ) ) { if ( I -> getOpcode ( ) != Cpu0 :: JALR ) { ++ I ; continue ; } DebugLoc dl = I -> getDebugLoc ( ) ; BuildMI ( MBB , ++ I , dl , TII -> get ( Cpu0 :: LD ) , Cpu0 :: GP ) . addFrameIndex ( FI ) . addImm ( 0 ) ; Changed = true ; } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> static unsigned int mips_mult_zero_zero_cost ( struct mips_sim * state , bool setting ) { mips_tuning_info . fast_mult_zero_zero_p = setting ; start_sequence ( ) ; machine_mode dword_mode = TARGET_64BIT ? TImode : DImode ; rtx hilo = gen_rtx_REG ( dword_mode , MD_REG_FIRST ) ; mips_emit_move_or_split ( hilo , const0_rtx , SPLIT_FOR_SPEED ) ; if ( dword_mode == DImode && HAVE_maddsidi4 ) { rtx gpr = gen_rtx_REG ( SImode , GP_REG_FIRST + 4 ) ; emit_insn ( gen_maddsidi4 ( hilo , gpr , gpr , hilo ) ) ; } unsigned int time = mips_seq_time ( state , get_insns ( ) ) ; end_sequence ( ) ; return time ; } </s>

Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p setting SETTING , using STATE to simulate instruction sequences .


<s> bool SIInstrInfo :: hasUnwantedEffectsWhenEXECEmpty ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( MI . mayStore ( ) && isSMRD ( MI ) ) return true ; if ( MI . isReturn ( ) ) return true ; if ( Opcode == AMDGPU :: S_SENDMSG || Opcode == AMDGPU :: S_SENDMSGHALT || isEXP ( Opcode ) || Opcode == AMDGPU :: DS_ORDERED_COUNT || Opcode == AMDGPU :: S_TRAP || Opcode == AMDGPU :: DS_GWS_INIT || Opcode == AMDGPU :: DS_GWS_BARRIER ) return true ; if ( MI . isCall ( ) || MI . isInlineAsm ( ) ) return true ; if ( modifiesModeRegister ( MI ) ) return true ; if ( Opcode == AMDGPU :: V_READFIRSTLANE_B32 || Opcode == AMDGPU :: V_READLANE_B32 || Opcode == AMDGPU :: V_WRITELANE_B32 ) return true ; return false ; } </s>

Whether we must prevent this instruction from executing with EXEC = 0 .


<s> static void c6x_conditional_register_usage ( void ) { int i ; if ( c6x_arch == C6X_CPU_C62X || c6x_arch == C6X_CPU_C67X ) for ( i = 16 ; i < 32 ; i ++ ) { fixed_regs [ i ] = 1 ; fixed_regs [ 32 + i ] = 1 ; } if ( TARGET_INSNS_64 ) { SET_HARD_REG_BIT ( reg_class_contents [ ( int ) PREDICATE_A_REGS ] , REG_A0 ) ; SET_HARD_REG_BIT ( reg_class_contents [ ( int ) PREDICATE_REGS ] , REG_A0 ) ; CLEAR_HARD_REG_BIT ( reg_class_contents [ ( int ) NONPREDICATE_A_REGS ] , REG_A0 ) ; CLEAR_HARD_REG_BIT ( reg_class_contents [ ( int ) NONPREDICATE_REGS ] , REG_A0 ) ; } } </s>

Implement the TARGET_CONDITIONAL_REGISTER_USAGE hook .


<s>
StringRef
getPassName
(
)
const
override
{
return
"TVM Stack Model"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> Type * getType ( ) const { return T ; } </s>

Overload to return most specific vector type .


"Unexpected register class in CSRsViaCopy!"

Insert explicit copies in entry and exit blocks .


<s> virtual const TargetFrameInfo * getFrameInfo ( ) const { return & FrameInfo ; } </s>

getFrameInfo - Return the frame info object for the current function .


<s> HOST_WIDE_INT ix86_initial_elimination_offset ( int from , int to ) { struct ix86_frame & frame = cfun -> machine -> frame ; if ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) return frame . hard_frame_pointer_offset ; else if ( from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) return frame . hard_frame_pointer_offset - frame . frame_pointer_offset ; else { gcc_assert ( to == STACK_POINTER_REGNUM ) ; if ( from == ARG_POINTER_REGNUM ) return frame . stack_pointer_offset ; gcc_assert ( from == FRAME_POINTER_REGNUM ) ; return frame . stack_pointer_offset - frame . frame_pointer_offset ; } } </s>

Return the offset between two registers , one to be eliminated , and the other its replacement , at the start of a routine .


<s> unsigned MSP430RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; return TFI -> hasFP ( MF ) ? MSP430 :: FPW : MSP430 :: SPW ; } </s>


<s> static bool offsettable_ok_by_alignment ( rtx op , HOST_WIDE_INT offset , machine_mode mode ) { tree decl ; unsigned HOST_WIDE_INT dsize , dalign , lsb , mask ; if ( GET_CODE ( op ) != SYMBOL_REF ) return false ; dsize = GET_MODE_SIZE ( mode ) ; decl = SYMBOL_REF_DECL ( op ) ; if ( ! decl ) { if ( dsize == 0 ) return false ; dalign = BITS_PER_UNIT ; if ( SYMBOL_REF_HAS_BLOCK_INFO_P ( op ) && SYMBOL_REF_ANCHOR_P ( op ) && SYMBOL_REF_BLOCK ( op ) != NULL ) { struct object_block * block = SYMBOL_REF_BLOCK ( op ) ; dalign = block -> alignment ; offset += SYMBOL_REF_BLOCK_OFFSET ( op ) ; } else if ( CONSTANT_POOL_ADDRESS_P ( op ) ) { machine_mode cmode = get_pool_mode ( op ) ; dalign = GET_MODE_ALIGNMENT ( cmode ) ; } } else if ( DECL_P ( decl ) ) { dalign = DECL_ALIGN ( decl ) ; if ( dsize == 0 ) { if ( ! DECL_SIZE_UNIT ( decl ) ) return false ; if ( ! tree_fits_uhwi_p ( DECL_SIZE_UNIT ( decl ) ) ) return false ; dsize = tree_to_uhwi ( DECL_SIZE_UNIT ( decl ) ) ; if ( dsize > 32768 ) return false ; dalign /= BITS_PER_UNIT ; if ( dalign > POWERPC64_TOC_POINTER_ALIGNMENT ) dalign = POWERPC64_TOC_POINTER_ALIGNMENT ; return dalign >= dsize ; } } else gcc_unreachable ( ) ; dalign /= BITS_PER_UNIT ; if ( dalign > POWERPC64_TOC_POINTER_ALIGNMENT ) dalign = POWERPC64_TOC_POINTER_ALIGNMENT ; mask = dalign - 1 ; lsb = offset & - offset ; mask &= lsb - 1 ; dalign = mask + 1 ; return dalign >= dsize ; } </s>

Return true if a MODE sized memory accesses to OP plus OFFSET is known to not straddle a 32k boundary .


<s> unsigned AArch64RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const AArch64FrameLowering * TFI = getFrameLowering ( MF ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case AArch64 :: GPR32RegClassID : case AArch64 :: GPR32spRegClassID : case AArch64 :: GPR32allRegClassID : case AArch64 :: GPR64spRegClassID : case AArch64 :: GPR64allRegClassID : case AArch64 :: GPR64RegClassID : case AArch64 :: GPR32commonRegClassID : case AArch64 :: GPR64commonRegClassID : return 32 - 1 - ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) - MF . getSubtarget < AArch64Subtarget > ( ) . isX18Reserved ( ) - hasBasePointer ( MF ) ; case AArch64 :: FPR8RegClassID : case AArch64 :: FPR16RegClassID : case AArch64 :: FPR32RegClassID : case AArch64 :: FPR64RegClassID : case AArch64 :: FPR128RegClassID : case AArch64 :: ZPRRegClassID : return 32 ; case AArch64 :: DDRegClassID : case AArch64 :: DDDRegClassID : case AArch64 :: DDDDRegClassID : case AArch64 :: QQRegClassID : case AArch64 :: QQQRegClassID : case AArch64 :: QQQQRegClassID : case AArch64 :: ZPR2RegClassID : case AArch64 :: ZPR3RegClassID : case AArch64 :: ZPR4RegClassID : return 32 ; case AArch64 :: FPR128_loRegClassID : return 16 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> bool AArch64TargetLowering :: shouldConvertFpToSat ( unsigned Op , EVT FPVT , EVT VT ) const { if ( FPVT == MVT :: v8f16 && ! Subtarget -> hasFullFP16 ( ) ) return false ; return TargetLowering :: shouldConvertFpToSat ( Op , FPVT , VT ) ; } </s>

Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min ( max ( fptoi ) ) saturation patterns .


<s> const MCExpr * X86ELFTargetObjectFile :: getDebugThreadLocalSymbol ( const MCSymbol * Sym ) const { return MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_DTPOFF , getContext ( ) ) ; } </s>

Describe a TLS variable address within debug info .


<s>
void
SystemZHazardRecognizer
::
emitInstruction
(
MachineInstr
*
MI
,
bool
TakenBranch
)
{
SUnit
SU
(
MI
,
0
)
;
SU
.
isCall
=
MI
->
isCall
(
)
;
const
MCSchedClassDesc
*
SC
=
SchedModel
->
resolveSchedClass
(
MI
)
;
for
(
const
MCWriteProcResEntry
&
PRE
:
make_range
(
SchedModel
->
getWriteProcResBegin
(
SC
)
,
SchedModel
->
getWriteProcResEnd
(
SC
)
)
)
{
switch
(
SchedModel
->
getProcResource
(
PRE
.
ProcResourceIdx
)
->
BufferSize
)
{
case
0
:
SU
.
hasReservedResource
=
true
;
break
;
case
1
:
SU
.
isUnbuffered
=
true
;
break
;
default
:
break
;
}
}
EmitInstruction
(
&
SU
)
;
if
(
TakenBranch
&&
CurrGroupSize
>
0
)
nextGroup
(
false
)
;
assert
(
(
!
MI
->
isTerminator
(
)
||
isBranchRetTrap
(
MI
)
)
&&
"Scheduler: unhandled terminator!"
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void mips_init_cumulative_args ( CUMULATIVE_ARGS * cum , tree fntype ) { memset ( cum , 0 , sizeof ( * cum ) ) ; cum -> prototype = ( fntype && prototype_p ( fntype ) ) ; cum -> gp_reg_found = ( cum -> prototype && stdarg_p ( fntype ) ) ; } </s>

Initialize * CUM for a call to a function of type FNTYPE .


<s>
static
uint16_t
name
(
struct
InternalInstruction
*
insn
,
OperandType
type
,
\
uint8_t
index
,
uint8_t
*
valid
)
{
\
*
valid
=
1
;
\
switch
(
type
)
{
\
default
:
\
debug
(
"Unhandled register type"
)
;
\
*
valid
=
0
;
\
return
0
;
\
case
TYPE_Rv
:
\
return
base
+
index
;
\
case
TYPE_R8
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
if
(
insn
->
rexPrefix
&&
index
>=
4
&&
index
<=
7
)
{
\
return
prefix
##
_SPL
+
(
index
4
)
;
\
}
else
{
\
return
prefix
##
_AL
+
index
;
\
}
\
case
TYPE_R16
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
return
prefix
##
_AX
+
index
;
\
case
TYPE_R32
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
return
prefix
##
_EAX
+
index
;
\
case
TYPE_R64
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
return
prefix
##
_RAX
+
index
;
\
case
TYPE_ZMM
:
\
return
prefix
##
_ZMM0
+
index
;
\
case
TYPE_YMM
:
\
return
prefix
##
_YMM0
+
index
;
\
case
TYPE_XMM
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_TMM
:
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_TMM0
+
index
;
\
case
TYPE_VK
:
\
index
&=
0xf
;
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_K0
+
index
;
\
case
TYPE_VK_PAIR
:
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_K0_K1
+
(
index
/
2
)
;
\
case
TYPE_MM64
:
\
return
prefix
##
_MM0
+
(
index
&
0x7
)
;
\
case
TYPE_SEGMENTREG
:
\
if
(
(
index
&
7
)
>
5
)
\
*
valid
=
0
;
\
return
prefix
##
_ES
+
(
index
&
7
)
;
\
case
TYPE_DEBUGREG
:
\
return
prefix
##
_DR0
+
index
;
\
case
TYPE_CONTROLREG
:
\
return
prefix
##
_CR0
+
index
;
\
case
TYPE_MVSIBX
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_MVSIBY
:
\
return
prefix
##
_YMM0
+
index
;
\
case
TYPE_MVSIBZ
:
\
return
prefix
##
_ZMM0
+
index
;
\
}
\
}
</s>

Gets the name of the pass we are mixed into .


"getBranchTargetOpValuePC10 expects only expressions or immediates"

getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS 10-bit branch target operand .


<s> void get_aligned_mem ( rtx ref , rtx * paligned_mem , rtx * pbitnum ) { rtx base ; HOST_WIDE_INT disp , offset ; gcc_assert ( MEM_P ( ref ) ) ; if ( reload_in_progress && ! memory_address_p ( GET_MODE ( ref ) , XEXP ( ref , 0 ) ) ) { base = find_replacement ( & XEXP ( ref , 0 ) ) ; gcc_assert ( memory_address_p ( GET_MODE ( ref ) , base ) ) ; } else base = XEXP ( ref , 0 ) ; if ( GET_CODE ( base ) == PLUS ) disp = INTVAL ( XEXP ( base , 1 ) ) , base = XEXP ( base , 0 ) ; else disp = 0 ; if ( MEM_ALIGN ( ref ) >= 32 ) offset = 0 ; else offset = disp & 3 ; gcc_assert ( offset + GET_MODE_SIZE ( GET_MODE ( ref ) ) <= GET_MODE_SIZE ( SImode ) ) ; * paligned_mem = widen_memory_access ( ref , SImode , - offset ) ; offset *= BITS_PER_UNIT ; * pbitnum = GEN_INT ( offset ) ; } </s>

REF is an alignable memory location . Place an aligned SImode reference into * PALIGNED_MEM and the number of bits to shift into * PBITNUM . SCRATCH is a free register for use in reloading out of range stack slots .


<s> void VideocoreAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( MI -> isDebugValue ( ) ) { SmallString < 128 > Str ; raw_svector_ostream O ( Str ) ; PrintDebugValueComment ( MI , O ) ; return ; } MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; OutStreamer . EmitInstruction ( TmpInst ) ; } </s>


<s> SDValue SparcTargetLowering :: LowerCall ( TargetLowering :: CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const { if ( Subtarget -> is64Bit ( ) ) return LowerCall_64 ( CLI , InVals ) ; return LowerCall_32 ( CLI , InVals ) ; } </s>

This hook must be implemented to lower calls into the specified DAG .


"RegScavenger required for long branching"

"new block should be inserted for expanding unconditional branch"

"Branch offsets outside of the signed 32-bit range not supported"

Insert an unconditional indirect branch at the end of MBB to NewDestBB .


<s> static void indirect_thunk_name ( char name [ 32 ] , unsigned int regno , enum indirect_thunk_prefix need_prefix , bool ret_p ) { if ( regno != INVALID_REGNUM && regno != CX_REG && ret_p ) gcc_unreachable ( ) ; if ( USE_HIDDEN_LINKONCE ) { const char * prefix ; if ( need_prefix == indirect_thunk_prefix_bnd ) prefix = "_bnd" ; else if ( need_prefix == indirect_thunk_prefix_nt && regno != INVALID_REGNUM ) { prefix = "_nt" ; } else prefix = "" ; const char * ret = ret_p ? "return" : "indirect" ; if ( regno != INVALID_REGNUM ) { const char * reg_prefix ; if ( LEGACY_INT_REGNO_P ( regno ) ) reg_prefix = TARGET_64BIT ? "r" : "e" ; else reg_prefix = "" ; sprintf ( name , "__x86_%s_thunk%s_%s%s" , ret , prefix , reg_prefix , reg_names [ regno ] ) ; } else sprintf ( name , "__x86_%s_thunk%s" , ret , prefix ) ; } else { if ( regno != INVALID_REGNUM ) { if ( need_prefix == indirect_thunk_prefix_bnd ) ASM_GENERATE_INTERNAL_LABEL ( name , "LITBR" , regno ) ; else ASM_GENERATE_INTERNAL_LABEL ( name , "LITR" , regno ) ; } else { if ( ret_p ) { if ( need_prefix == indirect_thunk_prefix_bnd ) ASM_GENERATE_INTERNAL_LABEL ( name , "LRTB" , 0 ) ; else ASM_GENERATE_INTERNAL_LABEL ( name , "LRT" , 0 ) ; } else { if ( need_prefix == indirect_thunk_prefix_bnd ) ASM_GENERATE_INTERNAL_LABEL ( name , "LITB" , 0 ) ; else ASM_GENERATE_INTERNAL_LABEL ( name , "LIT" , 0 ) ; } } } } </s>

Fills in the label name that should be used for the indirect thunk .


<s> unsigned PPCAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { int64_t ImmVal ; switch ( Kind ) { case MCK_0 : ImmVal = 0 ; break ; case MCK_1 : ImmVal = 1 ; break ; case MCK_2 : ImmVal = 2 ; break ; case MCK_3 : ImmVal = 3 ; break ; default : return Match_InvalidOperand ; } PPCOperand & Op = static_cast < PPCOperand & > ( AsmOp ) ; if ( Op . isImm ( ) && Op . getImm ( ) == ImmVal ) return Match_Success ; return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> static rtx promote_duplicated_reg ( machine_mode mode , rtx val ) { machine_mode valmode = GET_MODE ( val ) ; rtx tmp ; int nops = mode == DImode ? 3 : 2 ; gcc_assert ( mode == SImode || mode == DImode || val == const0_rtx ) ; if ( val == const0_rtx ) return copy_to_mode_reg ( mode , CONST0_RTX ( mode ) ) ; if ( CONST_INT_P ( val ) ) { HOST_WIDE_INT v = INTVAL ( val ) & 255 ; v |= v << 8 ; v |= v << 16 ; if ( mode == DImode ) v |= ( v << 16 ) << 16 ; return copy_to_mode_reg ( mode , gen_int_mode ( v , mode ) ) ; } if ( valmode == VOIDmode ) valmode = QImode ; if ( valmode != QImode ) val = gen_lowpart ( QImode , val ) ; if ( mode == QImode ) return val ; if ( ! TARGET_PARTIAL_REG_STALL ) nops -- ; if ( ix86_cost -> mult_init [ mode == DImode ? 3 : 2 ] + ix86_cost -> mult_bit * ( mode == DImode ? 8 : 4 ) <= ( ix86_cost -> shift_const + ix86_cost -> add ) * nops + ( COSTS_N_INSNS ( TARGET_PARTIAL_REG_STALL == 0 ) ) ) { rtx reg = convert_modes ( mode , QImode , val , true ) ; tmp = promote_duplicated_reg ( mode , const1_rtx ) ; return expand_simple_binop ( mode , MULT , reg , tmp , NULL , 1 , OPTAB_DIRECT ) ; } else { rtx reg = convert_modes ( mode , QImode , val , true ) ; if ( ! TARGET_PARTIAL_REG_STALL ) if ( mode == SImode ) emit_insn ( gen_movsi_insv_1 ( reg , reg ) ) ; else emit_insn ( gen_movdi_insv_1 ( reg , reg ) ) ; else { tmp = expand_simple_binop ( mode , ASHIFT , reg , GEN_INT ( 8 ) , NULL , 1 , OPTAB_DIRECT ) ; reg = expand_simple_binop ( mode , IOR , reg , tmp , reg , 1 , OPTAB_DIRECT ) ; } tmp = expand_simple_binop ( mode , ASHIFT , reg , GEN_INT ( 16 ) , NULL , 1 , OPTAB_DIRECT ) ; reg = expand_simple_binop ( mode , IOR , reg , tmp , reg , 1 , OPTAB_DIRECT ) ; if ( mode == SImode ) return reg ; tmp = expand_simple_binop ( mode , ASHIFT , reg , GEN_INT ( 32 ) , NULL , 1 , OPTAB_DIRECT ) ; reg = expand_simple_binop ( mode , IOR , reg , tmp , reg , 1 , OPTAB_DIRECT ) ; return reg ; } } </s>

Helper function for memcpy . For QImode value 0xXY produce 0xXYXYXYXY of wide specified by MODE . This is essentially a * 0x10101010 , but we can do slightly better than synth_mult by unwinding the sequence by hand on CPUs with slow multiply .


<s> static void nvptx_maybe_record_fnsym ( rtx sym ) { tree decl = SYMBOL_REF_DECL ( sym ) ; if ( decl && TREE_CODE ( decl ) == FUNCTION_DECL && DECL_EXTERNAL ( decl ) ) nvptx_record_needed_fndecl ( decl ) ; } </s>

SYM is a SYMBOL_REF . If it refers to an external function , record it as needed .


<s> unsigned PPCTargetLowering :: getByValTypeAlignment ( Type * Ty , const DataLayout & DL ) const { unsigned Align = Subtarget . isPPC64 ( ) ? 8 : 4 ; if ( Subtarget . hasAltivec ( ) || Subtarget . hasQPX ( ) ) getMaxByValAlign ( Ty , Align , Subtarget . hasQPX ( ) ? 32 : 16 ) ; return Align ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


<s> const uint16_t * AVRRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const AVRMachineFunctionInfo * AFI = MF -> getInfo < AVRMachineFunctionInfo > ( ) ; const AVRSubtarget & STI = MF -> getSubtarget < AVRSubtarget > ( ) ; if ( STI . hasTinyEncoding ( ) ) return AFI -> isInterruptOrSignalHandler ( ) ? CSR_InterruptsTiny_SaveList : CSR_NormalTiny_SaveList ; else return AFI -> isInterruptOrSignalHandler ( ) ? CSR_Interrupts_SaveList : CSR_Normal_SaveList ; } </s>


<s> static rtx aarch64_gen_loadwb_pair ( machine_mode mode , rtx base , rtx reg , rtx reg2 , HOST_WIDE_INT adjustment ) { switch ( mode ) { case E_DImode : return gen_loadwb_pairdi_di ( base , base , reg , reg2 , GEN_INT ( adjustment ) , GEN_INT ( UNITS_PER_WORD ) ) ; case E_DFmode : return gen_loadwb_pairdf_di ( base , base , reg , reg2 , GEN_INT ( adjustment ) , GEN_INT ( UNITS_PER_WORD ) ) ; default : gcc_unreachable ( ) ; } } </s>

Load the pair of register REG , REG2 of mode MODE from stack location BASE , adjusting it by ADJUSTMENT afterwards .


<s>
void
s390_asm_output_function_prefix
(
FILE
*
asm_out_file
,
const
char
*
fnname
ATTRIBUTE_UNUSED
)
{
if
(
DECL_FUNCTION_SPECIFIC_TARGET
(
current_function_decl
)
==
)
return
;
fprintf
(
asm_out_file
,
"\t.machinemode push\n"
)
;
fprintf
(
asm_out_file
,
"\t.machine push\n"
)
;
s390_asm_output_machine_for_arch
(
asm_out_file
)
;
}
</s>

Write an extra function header before the very start of the function .

s390
"\t.machinemode push\n"
"\t.machine push\n"


<s> void MOSCombiner :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < TargetPassConfig > ( ) ; AU . setPreservesCFG ( ) ; getSelectionDAGFallbackAnalysisUsage ( AU ) ; AU . addRequired < GISelKnownBitsAnalysis > ( ) ; AU . addPreserved < GISelKnownBitsAnalysis > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < GISelCSEAnalysisWrapperPass > ( ) ; AU . addPreserved < GISelCSEAnalysisWrapperPass > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
unsigned
HexagonAsmParser
::
validateTargetOperandClass
(
MCParsedAsmOperand
&
AsmOp
,
unsigned
Kind
)
{
HexagonOperand
*
Op
=
static_cast
<
HexagonOperand
*
>
(
&
AsmOp
)
;
switch
(
Kind
)
{
case
MCK_0
:
{
int64_t
Value
;
return
Op
->
isImm
(
)
&&
Op
->
Imm
.
Val
->
evaluateAsAbsolute
(
Value
)
&&
Value
==
0
Match_Success
:
Match_InvalidOperand
;
}
case
MCK_1
:
{
int64_t
Value
;
return
Op
->
isImm
(
)
&&
Op
->
Imm
.
Val
->
evaluateAsAbsolute
(
Value
)
&&
Value
==
1
Match_Success
:
Match_InvalidOperand
;
}
}
if
(
Op
->
Kind
==
HexagonOperand
::
Token
&&
Kind
!=
InvalidMatchClass
)
{
StringRef
myStringRef
=
StringRef
(
Op
->
Tok
.
Data
,
Op
->
Tok
.
Length
)
;
if
(
matchTokenString
(
myStringRef
.
lower
(
)
)
==
(
MatchClassKind
)
Kind
)
return
Match_Success
;
if
(
matchTokenString
(
myStringRef
.
upper
(
)
)
==
(
MatchClassKind
)
Kind
)
return
Match_Success
;
}
DEBUG
(
dbgs
(
)
<<
"Unmatched Operand:"
)
;
DEBUG
(
Op
->
dump
(
)
)
;
DEBUG
(
dbgs
(
)
<<
"\n"
)
;
return
Match_InvalidOperand
;
}
</s>

Hexagon
Hexagon
Hexagon
Hexagon
0
1
Hexagon
"Unmatched Operand:"
"\n"


<s> bool mips_split_128bit_move_p ( rtx dest , rtx src ) { if ( FP_REG_RTX_P ( src ) && FP_REG_RTX_P ( dest ) ) return false ; if ( FP_REG_RTX_P ( dest ) && MEM_P ( src ) ) return false ; if ( FP_REG_RTX_P ( src ) && MEM_P ( dest ) ) return false ; if ( FP_REG_RTX_P ( dest ) && mips_const_vector_same_int_p ( src , GET_MODE ( src ) , - 512 , 511 ) ) return false ; if ( FP_REG_RTX_P ( dest ) && src == CONST0_RTX ( GET_MODE ( src ) ) ) return false ; return true ; } </s>

Return true if a 128-bit move from SRC to DEST should be split .


<s> bool X86TargetLowering :: shouldReduceLoadWidth ( SDNode * Load , ISD :: LoadExtType ExtTy , EVT NewVT ) const { SDValue BasePtr = cast < LoadSDNode > ( Load ) -> getBasePtr ( ) ; if ( BasePtr . getOpcode ( ) == X86ISD :: WrapperRIP ) if ( const auto * GA = dyn_cast < GlobalAddressSDNode > ( BasePtr . getOperand ( 0 ) ) ) return GA -> getTargetFlags ( ) != X86II :: MO_GOTTPOFF ; return true ; } </s>

Return true if we believe it is correct and profitable to reduce the load node to a smaller type .


<s> unsigned getPrefetchDistance ( ) const override { return 2000 ; } </s>

Return the preferred prefetch distance in terms of instructions .


<s>
bool
HexagonPassConfig
::
addInstSelector
(
)
{
HexagonTargetMachine
&
TM
=
getHexagonTargetMachine
(
)
;
bool
NoOpt
=
(
getOptLevel
(
)
==
CodeGenOpt
::
)
;
if
(
!
NoOpt
)
addPass
(
createHexagonOptimizeSZextends
(
)
)
;
addPass
(
createHexagonISelDag
(
TM
,
getOptLevel
(
)
)
)
;
if
(
!
NoOpt
)
{
if
(
EnableGenPred
)
addPass
(
createHexagonGenPredicate
(
)
)
;
if
(
EnableLoopResched
)
addPass
(
createHexagonLoopRescheduling
(
)
)
;
if
(
!
DisableHSDR
)
addPass
(
createHexagonSplitDoubleRegs
(
)
)
;
if
(
EnableBitSimplify
)
addPass
(
createHexagonBitSimplify
(
)
)
;
addPass
(
createHexagonPeephole
(
)
)
;
printAndVerify
(
"After hexagon peephole pass"
)
;
if
(
!
DisableHCP
)
{
addPass
(
createHexagonConstPropagationPass
(
)
)
;
addPass
(
&
UnreachableMachineBlockElimID
)
;
}
if
(
EnableGenInsert
)
addPass
(
createHexagonGenInsert
(
)
)
;
if
(
EnableEarlyIf
)
addPass
(
createHexagonEarlyIfConversion
(
)
)
;
}
return
false
;
}
</s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .

Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
"After hexagon peephole pass"
Hexagon
Hexagon
Hexagon


<s> static void reorg_emit_nops ( rtx_code_label * * call_labels ) { bool first ; rtx last_call ; rtx_insn * prev ; int prev_clock , earliest_bb_end ; int prev_implicit_nops ; rtx_insn * insn = get_insns ( ) ; insn = next_real_insn ( insn ) ; last_call = prev = NULL ; prev_clock = - 1 ; earliest_bb_end = 0 ; prev_implicit_nops = 0 ; first = true ; while ( insn ) { int this_clock = - 1 ; rtx_insn * next ; int max_cycles = 0 ; next = next_real_insn ( insn ) ; if ( DEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER || shadow_or_blockage_p ( insn ) || JUMP_TABLE_DATA_P ( insn ) ) goto next_insn ; if ( ! c6x_flag_schedule_insns2 ) PUT_MODE ( insn , TImode ) ; else { int cycles ; this_clock = insn_get_clock ( insn ) ; if ( this_clock != prev_clock ) { PUT_MODE ( insn , TImode ) ; if ( ! first ) { cycles = this_clock - prev_clock ; cycles -= prev_implicit_nops ; if ( cycles > 1 ) { rtx nop = emit_nop_after ( cycles - 1 , prev ) ; insn_set_clock ( nop , prev_clock + prev_implicit_nops + 1 ) ; } } prev_clock = this_clock ; if ( last_call && insn_get_clock ( last_call ) + 6 <= this_clock ) { emit_label_before ( call_labels [ INSN_UID ( last_call ) ] , insn ) ; last_call = NULL_RTX ; } prev_implicit_nops = 0 ; } } if ( recog_memoized ( insn ) >= 0 && ( c6x_flag_schedule_insns2 || ! returning_call_p ( insn ) ) ) { max_cycles = get_attr_cycles ( insn ) ; if ( get_attr_type ( insn ) == TYPE_CALLP ) prev_implicit_nops = 5 ; } else max_cycles = 1 ; if ( returning_call_p ( insn ) ) last_call = insn ; if ( c6x_flag_schedule_insns2 ) { gcc_assert ( this_clock >= 0 ) ; if ( earliest_bb_end < this_clock + max_cycles ) earliest_bb_end = this_clock + max_cycles ; } else if ( max_cycles > 1 ) emit_nop_after ( max_cycles - 1 , insn ) ; prev = insn ; first = false ; next_insn : if ( c6x_flag_schedule_insns2 && ( next == NULL_RTX || ( GET_MODE ( next ) == TImode && INSN_INFO_ENTRY ( INSN_UID ( next ) ) . ebb_start ) ) && earliest_bb_end > 0 ) { int cycles = earliest_bb_end - prev_clock ; if ( cycles > 1 ) { prev = emit_nop_after ( cycles - 1 , prev ) ; insn_set_clock ( prev , prev_clock + prev_implicit_nops + 1 ) ; } earliest_bb_end = 0 ; prev_clock = - 1 ; first = true ; if ( last_call ) emit_label_after ( call_labels [ INSN_UID ( last_call ) ] , prev ) ; last_call = NULL_RTX ; } insn = next ; } } </s>

Called as part of c6x_reorg . This function emits multi-cycle NOP insns as required for correctness . CALL_LABELS is the array that holds the return labels for call insns ; we emit these here if scheduling was run earlier .


<s> static bool aarch64_extr_rtx_p ( rtx x , rtx * res_op0 , rtx * res_op1 ) { rtx op0 , op1 ; machine_mode mode = GET_MODE ( x ) ; * res_op0 = NULL_RTX ; * res_op1 = NULL_RTX ; if ( GET_CODE ( x ) != IOR ) return false ; op0 = XEXP ( x , 0 ) ; op1 = XEXP ( x , 1 ) ; if ( ( GET_CODE ( op0 ) == ASHIFT && GET_CODE ( op1 ) == LSHIFTRT ) || ( GET_CODE ( op1 ) == ASHIFT && GET_CODE ( op0 ) == LSHIFTRT ) ) { if ( GET_CODE ( op1 ) == ASHIFT ) std :: swap ( op0 , op1 ) ; if ( ! CONST_INT_P ( XEXP ( op0 , 1 ) ) || ! CONST_INT_P ( XEXP ( op1 , 1 ) ) ) return false ; unsigned HOST_WIDE_INT shft_amnt_0 = UINTVAL ( XEXP ( op0 , 1 ) ) ; unsigned HOST_WIDE_INT shft_amnt_1 = UINTVAL ( XEXP ( op1 , 1 ) ) ; if ( shft_amnt_0 < GET_MODE_BITSIZE ( mode ) && shft_amnt_0 + shft_amnt_1 == GET_MODE_BITSIZE ( mode ) ) { * res_op0 = XEXP ( op0 , 0 ) ; * res_op1 = XEXP ( op1 , 0 ) ; return true ; } } return false ; } </s>

Return true iff X is an rtx that will match an extr instruction i.e . as described in the * extr < mode > 5_insn family of patterns . OP0 and OP1 will be set to the operands of the shifts involved on success and will be NULL_RTX otherwise .


<s> void mips_expand_vec_reduc ( rtx target , rtx in , rtx ( * gen ) ( rtx , rtx , rtx ) ) { machine_mode vmode = GET_MODE ( in ) ; unsigned char perm2 [ 2 ] ; rtx last , next , fold , x ; bool ok ; last = in ; fold = gen_reg_rtx ( vmode ) ; switch ( vmode ) { case V2SFmode : perm2 [ 0 ] = 1 ; perm2 [ 1 ] = 2 ; ok = mips_expand_vselect_vconcat ( fold , last , last , perm2 , 2 ) ; gcc_assert ( ok ) ; break ; case V2SImode : emit_insn ( gen_loongson_punpckhwd ( fold , last , last ) ) ; break ; case V4HImode : emit_insn ( gen_loongson_punpckhwd_hi ( fold , last , last ) ) ; next = gen_reg_rtx ( vmode ) ; emit_insn ( gen ( next , last , fold ) ) ; last = next ; fold = gen_reg_rtx ( vmode ) ; x = force_reg ( SImode , GEN_INT ( 16 ) ) ; emit_insn ( gen_vec_shr_v4hi ( fold , last , x ) ) ; break ; case V8QImode : emit_insn ( gen_loongson_punpckhwd_qi ( fold , last , last ) ) ; next = gen_reg_rtx ( vmode ) ; emit_insn ( gen ( next , last , fold ) ) ; last = next ; fold = gen_reg_rtx ( vmode ) ; x = force_reg ( SImode , GEN_INT ( 16 ) ) ; emit_insn ( gen_vec_shr_v8qi ( fold , last , x ) ) ; next = gen_reg_rtx ( vmode ) ; emit_insn ( gen ( next , last , fold ) ) ; last = next ; fold = gen_reg_rtx ( vmode ) ; x = force_reg ( SImode , GEN_INT ( 8 ) ) ; emit_insn ( gen_vec_shr_v8qi ( fold , last , x ) ) ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( target , last , fold ) ) ; } </s>


<s> static rtx move_to_acc ( int opno , rtx_insn * before ) { rtx src = OP ( opno ) ; machine_mode mode = GET_MODE ( src ) ; if ( REG_P ( src ) && REGNO ( src ) < 2 ) return src ; if ( mode == VOIDmode ) mode = recog_data . operand_mode [ opno ] ; return gen_and_emit_move ( mode == QImode ? A : AX , src , before , true ) ; } </s>

Copy SRC to accumulator ( A or AX ) , placing any generated insns before BEFORE . Returns accumulator RTX .


<s>
void
maybe_unlink
(
const
char
*
file
)
{
if
(
!
save_temps
)
{
if
(
unlink_if_ordinary
(
file
)
&&
errno
!=
ENOENT
)
fatal_error
(
input_location
,
"deleting file %s: %m"
,
file
)
;
}
else
if
(
verbose
)
fprintf
(
stderr
,
"[Leaving %s]\n"
,
file
)
;
}
</s>

Unlink a temporary file unless requested otherwise .

i386
"deleting file %s: %m"
"[Leaving %s]\n"


<s>
bool
HexagonInstrInfo
::
PredicateInstruction
(
MachineInstr
&
MI
,
ArrayRef
<
MachineOperand
>
Cond
)
const
{
if
(
Cond
.
empty
(
)
||
isNewValueJump
(
Cond
[
0
]
.
getImm
(
)
)
||
isEndLoopN
(
Cond
[
0
]
.
getImm
(
)
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"\nCannot predicate:"
;
MI
.
dump
(
)
;
)
;
return
false
;
}
int
Opc
=
MI
.
getOpcode
(
)
;
assert
(
isPredicable
(
MI
)
&&
"Expected predicable instruction"
)
;
bool
invertJump
=
predOpcodeHasNot
(
Cond
)
;
MachineBasicBlock
&
B
=
*
MI
.
getParent
(
)
;
DebugLoc
DL
=
MI
.
getDebugLoc
(
)
;
unsigned
PredOpc
=
getCondOpcode
(
Opc
,
invertJump
)
;
MachineInstrBuilder
T
=
BuildMI
(
B
,
MI
,
DL
,
get
(
PredOpc
)
)
;
unsigned
NOp
=
0
,
NumOps
=
MI
.
getNumOperands
(
)
;
while
(
NOp
<
NumOps
)
{
MachineOperand
&
Op
=
MI
.
getOperand
(
NOp
)
;
if
(
!
Op
.
isReg
(
)
||
!
Op
.
isDef
(
)
||
Op
.
isImplicit
(
)
)
break
;
T
.
add
(
Op
)
;
NOp
++
;
}
unsigned
PredReg
,
PredRegPos
,
PredRegFlags
;
bool
GotPredReg
=
getPredReg
(
Cond
,
PredReg
,
PredRegPos
,
PredRegFlags
)
;
(
void
)
GotPredReg
;
assert
(
GotPredReg
)
;
T
.
addReg
(
PredReg
,
PredRegFlags
)
;
while
(
NOp
<
NumOps
)
T
.
add
(
MI
.
getOperand
(
NOp
++
)
)
;
MI
.
setDesc
(
get
(
PredOpc
)
)
;
while
(
unsigned
n
=
MI
.
getNumOperands
(
)
)
MI
.
removeOperand
(
n
1
)
;
for
(
unsigned
i
=
0
,
n
=
T
->
getNumOperands
(
)
;
i
<
n
;
++
i
)
MI
.
addOperand
(
T
->
getOperand
(
i
)
)
;
MachineBasicBlock
::
instr_iterator
TI
=
T
->
getIterator
(
)
;
B
.
erase
(
TI
)
;
MachineRegisterInfo
&
MRI
=
B
.
getParent
(
)
->
getRegInfo
(
)
;
MRI
.
clearKillFlags
(
PredReg
)
;
return
true
;
}
</s>

Convert the instruction into a predicated instruction .


<s> static rtx arm_libcall_value ( machine_mode mode , const_rtx libcall ) { if ( TARGET_AAPCS_BASED && arm_pcs_default != ARM_PCS_AAPCS && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { if ( arm_libcall_uses_aapcs_base ( libcall ) ) return gen_rtx_REG ( mode , ARG_REGISTER ( 1 ) ) ; } return arm_libcall_value_1 ( mode ) ; } </s>

Define how to find the value returned by a library function assuming the value has mode MODE .


<s>
SDValue
SystemZTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_SystemZ
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
if
(
RVLocs
[
i
]
.
isRegLoc
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
SDValue
ResValue
=
Outs
[
i
]
.
Val
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
SExt
)
ResValue
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
ResValue
)
;
else
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExt
)
ResValue
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
ResValue
)
;
else
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
AExt
)
ResValue
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
ResValue
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
ResValue
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> InstructionCost ARMTTIImpl :: getIntImmCodeSizeCost ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) { if ( Imm . isNonNegative ( ) && Imm . getLimitedValue ( ) < 256 ) return 0 ; return 1 ; } </s>

Return the expected cost for the given integer when optimising for size .


<s> ARMSubtarget :: ARMSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const ARMBaseTargetMachine & TM , bool IsLittle , bool MinSize ) : ARMGenSubtargetInfo ( TT , CPU , CPU , FS ) , UseMulOps ( UseFusedMulOps ) , CPUString ( CPU ) , OptMinSize ( MinSize ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( ARMBaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( ARMBaseInstrInfo * ) new ARMInstrInfo ( * this ) : ( ARMBaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) { CallLoweringInfo . reset ( new ARMCallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new ARMLegalizerInfo ( * this ) ) ; auto * RBI = new ARMRegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( createARMInstructionSelector ( * static_cast < const ARMBaseTargetMachine * > ( & TM ) , * this , * RBI ) ) ; RegBankInfo . reset ( RBI ) ; } </s>

This constructor initializes the data members to match that of the specified triple .

ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM


<s> bool MBlazeTargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createMBlazeDelaySlotFillerPass ( * this ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> const char * arm_strip_name_encoding ( const char * name ) { int skip ; while ( ( skip = arm_get_strip_length ( * name ) ) ) name += skip ; return name ; } </s>

Return a pointer to a function 's name with any and all prefix encodings stripped from it .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> bool ARMFrameLowering :: keepFramePointer ( const MachineFunction & MF ) const { return MF . getSubtarget < ARMSubtarget > ( ) . useFastISel ( ) ; } </s>

Return true if the target wants to keep the frame pointer regardless of the function attribute `` frame-pointer '' .


" was Pass-through, is now Dirty-out.\n"

runOnMachineFunction - Emit the function body .


<s>
void
AVRAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
,
MCContext
&
Ctx
)
const
{
if
(
Value
==
0
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
auto
NumBits
=
Info
.
TargetSize
+
Info
.
TargetOffset
;
auto
NumBytes
=
(
NumBits
/
8
)
+
(
(
NumBits
%
8
)
==
0
0
:
1
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
<
NumBytes
;
++
i
)
{
uint8_t
mask
=
(
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
)
;
Data
[
Offset
+
i
]
|=
mask
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static e_funkind funkind ( tree funtype ) { tree attrs = TYPE_ATTRIBUTES ( funtype ) ; if ( lookup_attribute ( "interrupt_handler" , attrs ) ) return INTERRUPT_HANDLER ; else if ( lookup_attribute ( "exception_handler" , attrs ) ) return EXCPT_HANDLER ; else if ( lookup_attribute ( "nmi_handler" , attrs ) ) return NMI_HANDLER ; else return SUBROUTINE ; } </s>

Examine machine-dependent attributes of function type FUNTYPE and return its type . See the definition of E_FUNKIND .


<s> unsigned int vectors_per_tuple ( ) const OVERRIDE { return m_vectors_per_tuple ; } </s>

If the function operates on tuples of vectors , return the number of vectors in the tuples , otherwise return 1 .


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { const ARMSubtarget & Subtarget = DAG . getMachineFunction ( ) . getSubtarget < ARMSubtarget > ( ) ; if ( ! Subtarget . isAAPCS_ABI ( ) || Subtarget . isTargetMachO ( ) || Subtarget . isTargetWindows ( ) ) return SDValue ( ) ; const ARMTargetLowering & TLI = * Subtarget . getTargetLowering ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Type * IntPtrTy = TLI . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( MVT :: i32 ) ) Src = DAG . getNode ( ISD :: TRUNCATE , dl , MVT :: i32 , Src ) ; else Src = DAG . getNode ( ISD :: ZERO_EXTEND , dl , MVT :: i32 , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , std :: move ( Args ) , 0 ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } </s>

Emit target-specific code that performs a memset .


<s> int valid_mov3q_const ( rtx constant ) { int i ; if ( TARGET_CFV4 && GET_CODE ( constant ) == CONST_INT ) { i = INTVAL ( constant ) ; if ( ( i == - 1 ) || ( i >= 1 && i <= 7 ) ) return 1 ; } return 0 ; } </s>

Return 1 if 'constant ' can be represented by mov3q on a ColdFire V4 core .


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) Data [ Offset + i ] |= uint8_t ( ( Value >> ( ( NumBytes - i - 1 ) * 8 ) ) & 0xff ) ; } </s>


"Only Immediates and Registers implemented right now"

getMachineOpValue - Return binary encoding of operand .


<s> bool X86TargetLowering :: useLoadStackGuardNode ( ) const { return Subtarget -> isTargetMachO ( ) && Subtarget -> is64Bit ( ) ; } </s>

If this function returns true , SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic : :stackprotector .


<s> bool HexagonRegisterInfo :: shouldCoalesce ( MachineInstr * MI , const TargetRegisterClass * SrcRC , unsigned SubReg , const TargetRegisterClass * DstRC , unsigned DstSubReg , const TargetRegisterClass * NewRC , LiveIntervals & LIS ) const { MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const HexagonSubtarget & HST = MF . getSubtarget < HexagonSubtarget > ( ) ; if ( ! HST . useHVXOps ( ) || NewRC -> getID ( ) != Hexagon :: HvxWRRegClass . getID ( ) ) return true ; bool SmallSrc = SrcRC -> getID ( ) == Hexagon :: HvxVRRegClass . getID ( ) ; bool SmallDst = DstRC -> getID ( ) == Hexagon :: HvxVRRegClass . getID ( ) ; if ( ! SmallSrc && ! SmallDst ) return true ; Register DstReg = MI -> getOperand ( 0 ) . getReg ( ) ; Register SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; const SlotIndexes & Indexes = * LIS . getSlotIndexes ( ) ; auto HasCall = [ & Indexes ] ( const LiveInterval :: Segment & S ) { for ( SlotIndex I = S . start . getBaseIndex ( ) , E = S . end . getBaseIndex ( ) ; I != E ; I = I . getNextIndex ( ) ) { if ( const MachineInstr * MI = Indexes . getInstructionFromIndex ( I ) ) if ( MI -> isCall ( ) ) return true ; } return false ; } ; if ( SmallSrc == SmallDst ) { return ! any_of ( LIS . getInterval ( DstReg ) , HasCall ) && ! any_of ( LIS . getInterval ( SrcReg ) , HasCall ) ; } unsigned SmallReg = SmallSrc ? SrcReg : DstReg ; unsigned LargeReg = SmallSrc ? DstReg : SrcReg ; return any_of ( LIS . getInterval ( LargeReg ) , HasCall ) || ! any_of ( LIS . getInterval ( SmallReg ) , HasCall ) ; } </s>

Hexagon Hexagon Hexagon Hexagon Hexagon::HvxWRRegClass Hexagon::HvxVRRegClass Hexagon::HvxVRRegClass 0 1


<s> rtx function_expander :: use_contiguous_store_insn ( insn_code icode ) { machine_mode mem_mode = memory_vector_mode ( ) ; add_mem_operand ( mem_mode , get_contiguous_base ( mem_mode ) ) ; add_input_operand ( icode , args . last ( ) ) ; add_input_operand ( icode , args [ 0 ] ) ; return generate_insn ( icode ) ; } </s>


<s> void OrderedRegisterList :: insert ( unsigned VR ) { iterator L = std :: lower_bound ( Seq . begin ( ) , Seq . end ( ) , VR , Ord ) ; if ( L == Seq . end ( ) ) Seq . push_back ( VR ) ; else Seq . insert ( L , VR ) ; unsigned S = Seq . size ( ) ; if ( S > MaxSize ) Seq . resize ( MaxSize ) ; assert ( Seq . size ( ) <= MaxSize ) ; } </s>

insert - Append entry to the vector if it does n't already exist .


<s> void visium_profile_hook ( void ) { visium_frame_needed = true ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , "mcount" ) , LCT_NORMAL , VOIDmode , 0 ) ; } </s>

Profiling support . Just a call to MCOUNT is needed . No labelled counter location is involved . Proper support for __builtin_return_address is also required , which is fairly straightforward provided a frame gets created .


<s> unsigned HSAILTargetLowering :: getJumpTableEncoding ( ) const { return MachineJumpTableInfo :: EK_BlockAddress ; } </s>

Return the entry encoding for a jump table in the current function .


<s> static unsigned int get_csky_live_regs ( int * count ) { int reg ; unsigned int live_regs_mask = 0 ; * count = 0 ; for ( reg = 0 ; reg < CSKY_NGPR_REGS ; reg ++ ) { bool save = false ; if ( CSKY_TARGET_ARCH ( CK801 ) && reg > 8 && reg < 13 ) continue ; if ( ( CSKY_TARGET_ARCH ( CK801 ) || CSKY_TARGET_ARCH ( CK802 ) || CSKY_TARGET_ARCH ( CK803 ) ) && reg > 15 ) break ; if ( df_regs_ever_live_p ( reg ) && ! call_used_regs [ reg ] ) save = true ; else if ( frame_pointer_needed && reg == HARD_FRAME_POINTER_REGNUM ) save = true ; else if ( crtl -> calls_eh_return && reg == HARD_FRAME_POINTER_REGNUM ) save = true ; else if ( ( CSKY_TARGET_ARCH ( CK801 ) || CSKY_TARGET_ARCH ( CK802 ) ) && reg == CSKY_LR_REGNUM && ( ! crtl -> is_leaf || csky_far_jump_used_p ( ) ) ) save = true ; else if ( crtl -> calls_eh_return && reg >= CSKY_FIRST_EH_RETDATA_REGNUM && reg <= CSKY_LAST_EH_RETDATA_REGNUM ) save = true ; if ( reg == CSKY_STACKADJUST_REGNUM && cfun -> machine -> reg_offset > CSKY_MAX_SP_ADJUST * 2 ) save = true ; if ( save ) { ( * count ) ++ ; live_regs_mask |= ( 1 << reg ) ; } } return live_regs_mask ; } </s>

Return the mask of registers used by the current function . Set COUNT to the number of registers used .


<s> static int get_some_local_dynamic_name_1 ( rtx * px , void * data ATTRIBUTE_UNUSED ) { rtx x = * px ; if ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_DYNAMIC ) { cfun -> machine -> some_ld_name = XSTR ( x , 0 ) ; return 1 ; } return 0 ; } </s>


<s> void AMDGPUAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { uint16_t * Dst = ( uint16_t * ) ( Data + Fixup . getOffset ( ) ) ; assert ( Fixup . getKind ( ) == FK_PCRel_4 ) ; * Dst = ( Value - 4 ) / 4 ; } </s>


<s> bool SIInstrInfo :: isBranchOffsetInRange ( unsigned BranchOp , int64_t BrOffset ) const { assert ( BranchOp != AMDGPU :: S_SETPC_B64 ) ; BrOffset /= 4 ; BrOffset -= 1 ; return isIntN ( BranchOffsetBits , BrOffset ) ; } </s>

Determine if the branch target is in range .


<s> static int ix86_builtin_vectorization_cost ( enum vect_cost_for_stmt type_of_cost , tree vectype , int ) { bool fp = false ; machine_mode mode = TImode ; int index ; if ( vectype != NULL ) { fp = FLOAT_TYPE_P ( vectype ) ; mode = TYPE_MODE ( vectype ) ; } switch ( type_of_cost ) { case scalar_stmt : return fp ? ix86_cost -> addss : COSTS_N_INSNS ( 1 ) ; case scalar_load : return COSTS_N_INSNS ( fp ? ix86_cost -> sse_load [ 0 ] : ix86_cost -> int_load [ 2 ] ) / 2 ; case scalar_store : return COSTS_N_INSNS ( fp ? ix86_cost -> sse_store [ 0 ] : ix86_cost -> int_store [ 2 ] ) / 2 ; case vector_stmt : return ix86_vec_cost ( mode , fp ? ix86_cost -> addss : ix86_cost -> sse_op , true ) ; case vector_load : index = sse_store_index ( mode ) ; if ( index < 0 ) index = 2 ; return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> sse_load [ index ] ) / 2 , true ) ; case vector_store : index = sse_store_index ( mode ) ; if ( index < 0 ) index = 2 ; return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> sse_store [ index ] ) / 2 , true ) ; case vec_to_scalar : case scalar_to_vec : return ix86_vec_cost ( mode , ix86_cost -> sse_op , true ) ; case unaligned_load : index = sse_store_index ( mode ) ; if ( index < 0 ) index = 2 ; return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> sse_unaligned_load [ index ] ) / 2 , true ) ; case unaligned_store : index = sse_store_index ( mode ) ; if ( index < 0 ) index = 2 ; return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> sse_unaligned_store [ index ] ) / 2 , true ) ; case vector_gather_load : return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> gather_static + ix86_cost -> gather_per_elt * TYPE_VECTOR_SUBPARTS ( vectype ) ) / 2 , true ) ; case vector_scatter_store : return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> scatter_static + ix86_cost -> scatter_per_elt * TYPE_VECTOR_SUBPARTS ( vectype ) ) / 2 , true ) ; case cond_branch_taken : return ix86_cost -> cond_taken_branch_cost ; case cond_branch_not_taken : return ix86_cost -> cond_not_taken_branch_cost ; case vec_perm : case vec_promote_demote : return ix86_vec_cost ( mode , ix86_cost -> sse_op , true ) ; case vec_construct : { int cost = ix86_vec_cost ( mode , ix86_cost -> sse_op , false ) ; if ( GET_MODE_BITSIZE ( mode ) == 256 ) cost += ix86_vec_cost ( mode , ix86_cost -> addss , true ) ; else if ( GET_MODE_BITSIZE ( mode ) == 512 ) cost += 3 * ix86_vec_cost ( mode , ix86_cost -> addss , true ) ; return cost ; } default : gcc_unreachable ( ) ; } } </s>


"Copy one register into another with a different width"


<s>
SDValue
VECustomDAG
::
getLegalReductionOpVVP
(
unsigned
VVPOpcode
,
EVT
ResVT
,
SDValue
StartV
,
SDValue
VectorV
,
SDValue
Mask
,
SDValue
AVL
,
SDNodeFlags
Flags
)
const
{
bool
scalarizeStartParam
=
StartV
&&
!
hasReductionStartParam
(
VVPOpcode
)
;
bool
IsMaskReduction
=
isMaskType
(
VectorV
.
getValueType
(
)
)
;
assert
(
!
IsMaskReduction
&&
"TODO Implement"
)
;
auto
AttachStartValue
=
[
&
]
(
SDValue
ReductionResV
)
{
if
(
!
scalarizeStartParam
)
return
ReductionResV
;
auto
ScalarOC
=
getScalarReductionOpcode
(
VVPOpcode
,
IsMaskReduction
)
;
return
getNode
(
ScalarOC
,
ResVT
,
{
StartV
,
ReductionResV
}
)
;
}
;
if
(
!
scalarizeStartParam
&&
StartV
)
{
assert
(
hasReductionStartParam
(
VVPOpcode
)
)
;
return
AttachStartValue
(
getNode
(
VVPOpcode
,
ResVT
,
{
StartV
,
VectorV
,
Mask
,
AVL
}
,
Flags
)
)
;
}
else
return
AttachStartValue
(
getNode
(
VVPOpcode
,
ResVT
,
{
VectorV
,
Mask
,
AVL
}
,
Flags
)
)
;
}
</s>

VE
VECustomDAG::getLegalReductionOpVVP
"TODO Implement"


<s> unsigned RISCVInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { return isSimpleMove ( MI , FrameIndex , RISCVII :: SimpleLoad ) ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> virtual const MBlazeSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


"rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n"

A C expression returning the cost of moving data from a register of class CLASS1 to one of CLASS2 .


<s> static int iq2000_address_cost ( rtx addr , machine_mode mode , addr_space_t as , bool speed ) { switch ( GET_CODE ( addr ) ) { case LO_SUM : return 1 ; case LABEL_REF : return 2 ; case CONST : { rtx offset = const0_rtx ; addr = eliminate_constant_term ( XEXP ( addr , 0 ) , & offset ) ; if ( GET_CODE ( addr ) == LABEL_REF ) return 2 ; if ( GET_CODE ( addr ) != SYMBOL_REF ) return 4 ; if ( ! SMALL_INT ( offset ) ) return 2 ; } case SYMBOL_REF : return SYMBOL_REF_FLAG ( addr ) ? 1 : 2 ; case PLUS : { rtx plus0 = XEXP ( addr , 0 ) ; rtx plus1 = XEXP ( addr , 1 ) ; if ( GET_CODE ( plus0 ) != REG && GET_CODE ( plus1 ) == REG ) plus0 = XEXP ( addr , 1 ) , plus1 = XEXP ( addr , 0 ) ; if ( GET_CODE ( plus0 ) != REG ) break ; switch ( GET_CODE ( plus1 ) ) { case CONST_INT : return SMALL_INT ( plus1 ) ? 1 : 2 ; case CONST : case SYMBOL_REF : case LABEL_REF : case HIGH : case LO_SUM : return iq2000_address_cost ( plus1 , mode , as , speed ) + 1 ; default : break ; } } default : break ; } return 4 ; } </s>

Provide the costs of an addressing mode that contains ADDR .


<s> const char * pa_output_mul_insn ( int unsignedp ATTRIBUTE_UNUSED , rtx_insn * insn ) { import_milli ( mulI ) ; return pa_output_millicode_call ( insn , gen_rtx_SYMBOL_REF ( Pmode , "$$mulI" ) ) ; } </s>

The register constraints have put the operands and return value in the proper registers .


<s> void push ( MachineInstr * MI ) { if ( Set . insert ( MI ) . second ) Uses . push ( MI ) ; } </s>


<s> static rtx loongarch_function_value_1 ( const_tree type , const_tree func , machine_mode mode ) { struct loongarch_arg_info info ; CUMULATIVE_ARGS args ; if ( type ) { int unsigned_p = TYPE_UNSIGNED ( type ) ; mode = TYPE_MODE ( type ) ; mode = promote_function_mode ( type , mode , & unsigned_p , func , 1 ) ; } memset ( & args , 0 , sizeof ( args ) ) ; return loongarch_get_arg_info ( & info , & args , mode , type , true , true ) ; } </s>

Implement FUNCTION_VALUE and LIBCALL_VALUE . For normal calls , VALTYPE is the return type and MODE is VOIDmode . For libcalls , VALTYPE is null and MODE is the mode of the return value .


<s> int AMDGPUInstrInfo :: pseudoToMCOpcode ( int Opcode ) const { int MCOp = AMDGPU :: getMCOpcode ( Opcode , AMDGPUSubtargetToSISubtarget ( RI . ST . getGeneration ( ) ) ) ; if ( MCOp == - 1 ) return Opcode ; if ( MCOp == ( uint16_t ) - 1 ) return - 1 ; return MCOp ; } </s>

Return a target-specific opcode if Opcode is a pseudo instruction .


<s> SDValue ARMTargetLowering :: PerformCMOVCombine ( SDNode * N , SelectionDAG & DAG ) const { SDValue Cmp = N -> getOperand ( 4 ) ; if ( Cmp . getOpcode ( ) != ARMISD :: CMPZ ) return SDValue ( ) ; EVT VT = N -> getValueType ( 0 ) ; SDLoc dl ( N ) ; SDValue LHS = Cmp . getOperand ( 0 ) ; SDValue RHS = Cmp . getOperand ( 1 ) ; SDValue FalseVal = N -> getOperand ( 0 ) ; SDValue TrueVal = N -> getOperand ( 1 ) ; SDValue ARMcc = N -> getOperand ( 2 ) ; ARMCC :: CondCodes CC = ( ARMCC :: CondCodes ) cast < ConstantSDNode > ( ARMcc ) -> getZExtValue ( ) ; SDValue Res ; if ( CC == ARMCC :: NE && FalseVal == RHS && FalseVal != LHS ) { Res = DAG . getNode ( ARMISD :: CMOV , dl , VT , LHS , TrueVal , ARMcc , N -> getOperand ( 3 ) , Cmp ) ; } else if ( CC == ARMCC :: EQ && TrueVal == RHS ) { SDValue ARMcc ; SDValue NewCmp = getARMCmp ( LHS , RHS , ISD :: SETNE , ARMcc , DAG , dl ) ; Res = DAG . getNode ( ARMISD :: CMOV , dl , VT , LHS , FalseVal , ARMcc , N -> getOperand ( 3 ) , NewCmp ) ; } if ( Res . getNode ( ) ) { APInt KnownZero , KnownOne ; DAG . computeKnownBits ( SDValue ( N , 0 ) , KnownZero , KnownOne ) ; if ( KnownZero == 0xfffffffe ) Res = DAG . getNode ( ISD :: AssertZext , dl , MVT :: i32 , Res , DAG . getValueType ( MVT :: i1 ) ) ; else if ( KnownZero == 0xffffff00 ) Res = DAG . getNode ( ISD :: AssertZext , dl , MVT :: i32 , Res , DAG . getValueType ( MVT :: i8 ) ) ; else if ( KnownZero == 0xffff0000 ) Res = DAG . getNode ( ISD :: AssertZext , dl , MVT :: i32 , Res , DAG . getValueType ( MVT :: i16 ) ) ; } return Res ; } </s>

PerformCMOVCombine - Target-specific DAG combining for ARMISD : :CMOV .


<s>
void
HvxSelector
::
materialize
(
const
ResultStack
&
Results
)
{
DEBUG_WITH_TYPE
(
"isel"
,
{
dbgs
(
)
<<
"Materializing\n"
;
Results
.
print
(
dbgs
(
)
,
DAG
)
;
}
)
;
if
(
Results
.
empty
(
)
)
return
;
const
SDLoc
&
dl
(
Results
.
InpNode
)
;
std
::
vector
<
SDValue
>
Output
;
for
(
unsigned
I
=
0
,
E
=
Results
.
size
(
)
;
I
!=
E
;
++
I
)
{
const
NodeTemplate
&
Node
=
Results
[
I
]
;
std
::
vector
<
SDValue
>
Ops
;
for
(
const
OpRef
&
R
:
Node
.
Ops
)
{
assert
(
R
.
isValid
(
)
)
;
if
(
R
.
isValue
(
)
)
{
Ops
.
push_back
(
R
.
OpV
)
;
continue
;
}
if
(
R
.
OpN
&
OpRef
::
Undef
)
{
MVT
::
SimpleValueType
SVT
=
MVT
::
SimpleValueType
(
R
.
OpN
&
OpRef
::
Index
)
;
Ops
.
push_back
(
ISel
.
selectUndef
(
dl
,
MVT
(
SVT
)
)
)
;
continue
;
}
unsigned
Part
=
R
.
OpN
&
OpRef
::
Whole
;
int
Idx
=
SignExtend32
(
R
.
OpN
&
OpRef
::
Index
,
OpRef
::
IndexBits
)
;
if
(
Idx
<
0
)
Idx
+=
I
;
assert
(
Idx
>=
0
&&
unsigned
(
Idx
)
<
Output
.
size
(
)
)
;
SDValue
Op
=
Output
[
Idx
]
;
MVT
OpTy
=
Op
.
getValueType
(
)
.
getSimpleVT
(
)
;
if
(
Part
!=
OpRef
::
Whole
)
{
assert
(
Part
==
OpRef
::
LoHalf
||
Part
==
OpRef
::
HiHalf
)
;
MVT
HalfTy
=
MVT
::
getVectorVT
(
OpTy
.
getVectorElementType
(
)
,
OpTy
.
getVectorNumElements
(
)
/
2
)
;
unsigned
Sub
=
(
Part
==
OpRef
::
LoHalf
)
Hexagon
::
vsub_lo
:
Hexagon
::
vsub_hi
;
Op
=
DAG
.
getTargetExtractSubreg
(
Sub
,
dl
,
HalfTy
,
Op
)
;
}
Ops
.
push_back
(
Op
)
;
}
assert
(
Node
.
Ty
!=
MVT
::
Other
)
;
SDNode
*
ResN
=
(
Node
.
Opc
==
TargetOpcode
::
COPY
)
Ops
.
front
(
)
.
getNode
(
)
:
DAG
.
getMachineNode
(
Node
.
Opc
,
dl
,
Node
.
Ty
,
Ops
)
;
Output
.
push_back
(
SDValue
(
ResN
,
0
)
)
;
}
SDNode
*
OutN
=
Output
.
back
(
)
.
getNode
(
)
;
SDNode
*
InpN
=
Results
.
InpNode
;
DEBUG_WITH_TYPE
(
"isel"
,
{
dbgs
(
)
<<
"Generated node:\n"
;
OutN
->
dumpr
(
&
DAG
)
;
}
)
;
ISel
.
ReplaceNode
(
InpN
,
OutN
)
;
selectVectorConstants
(
OutN
)
;
DAG
.
RemoveDeadNodes
(
)
;
}
</s>

This method can be implemented to generate a mapped Value on demand .


" Emitting these undefined symbol references causes us to link the"

" libgcc code that runs our constructors/destructors"

Targets can override this to change how global constants that are part of a C++ static/global constructor list are emitted .


<s> bool AMDGPUCallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < unsigned > VRegs ) const { if ( Val ) return false ; MIRBuilder . buildInstr ( AMDGPU :: S_ENDPGM ) . addImm ( 0 ) ; return true ; } </s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Patmos Ensure Alignment"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool RISCVFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) && ! ( hasFP ( MF ) && hasRVVFrameObject ( MF ) ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> bool PPCPassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCEarlyReturnPass ( ) ) ; addPass ( createPPCBranchSelectionPass ( ) ) ; return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
void
ARMAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
Value
=
adjustFixupValue
(
Asm
,
Fixup
,
Target
,
Value
,
IsResolved
,
Ctx
,
STI
)
;
if
(
!
Value
)
return
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
unsigned
FullSizeBytes
;
if
(
Endian
==
support
::
big
)
{
FullSizeBytes
=
getFixupKindContainerSizeBytes
(
Fixup
.
getKind
(
)
)
;
assert
(
(
Offset
+
FullSizeBytes
)
<=
Data
.
size
(
)
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FullSizeBytes
&&
"Invalid fixup size!"
)
;
}
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
Endian
==
support
::
little
i
:
(
FullSizeBytes
1
i
)
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
void
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
)
const
override
{
unsigned
Size
=
1
<<
getFixupKindLog2Size
(
Fixup
.
getKind
(
)
)
;
assert
(
Fixup
.
getOffset
(
)
+
Size
<=
DataSize
&&
"Invalid fixup offset!"
)
;
assert
(
isIntN
(
Size
*
8
+
1
,
Value
)
&&
"Value does not fit in the Fixup field"
)
;
for
(
unsigned
i
=
0
;
i
!=
Size
;
++
i
)
Data
[
Fixup
.
getOffset
(
)
+
i
]
=
uint8_t
(
Value
>>
(
i
*
8
)
)
;
}
</s>