This routine handles output of long unconditional branches that exceed the maximum range of a simple branch instruction . Since we do n't have a register available for the branch , we save register % r1 in the frame marker , load the branch destination DEST into % r1 , execute the branch , and restore % r1 in the delay slot of the branch . Since long branches may have an insn in the delay slot and the delay slot is used to restore % r1 , we in general need to extract this insn and execute it before the branch . However , to facilitate use of this function by conditional branches , we also provide an option to not extract the delay insn so that it will be emitted after the long branch . So , if there is an insn in the delay slot , it is extracted if XDELAY is nonzero . The lengths of the various long-branch sequences are 20 , 16 and 24 bytes for the portable runtime , non-PIC and PIC cases , respectively .


"After expanding ARM pseudo instructions."

runOnMachineFunction - Emit the function body .


<s> const DataLayout * getDataLayout ( ) const override { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> static bool arm_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL ; if ( cfun -> machine -> sibcall_blocked ) return false ; if ( decl == NULL || TARGET_THUMB ) return false ; if ( lookup_attribute ( "short_call" , TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ) ) call_type = CALL_SHORT ; else if ( lookup_attribute ( "long_call" , TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ) ) call_type = CALL_LONG ; if ( call_type == CALL_LONG && ( flag_pic || ! TREE_ASM_WRITTEN ( decl ) ) ) return false ; if ( TARGET_INTERWORK && TREE_PUBLIC ( decl ) && ! TREE_ASM_WRITTEN ( decl ) ) return false ; if ( IS_INTERRUPT ( arm_current_func_type ( ) ) ) return false ; return true ; } </s>

Return non-zero if it is ok to make a tail-call to DECL .


<s> ScheduleHazardRecognizer * PPCInstrInfo :: CreateTargetHazardRecognizer ( const TargetSubtargetInfo * STI , const ScheduleDAG * DAG ) const { unsigned Directive = static_cast < const PPCSubtarget * > ( STI ) -> getCPUDirective ( ) ; if ( Directive == PPC :: DIR_440 || Directive == PPC :: DIR_A2 || Directive == PPC :: DIR_E500mc || Directive == PPC :: DIR_E5500 ) { const InstrItineraryData * II = static_cast < const PPCSubtarget * > ( STI ) -> getInstrItineraryData ( ) ; return new ScoreboardHazardRecognizer ( II , DAG ) ; } return TargetInstrInfo :: CreateTargetHazardRecognizer ( STI , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .


<s> bool MSP430AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) { return true ; } printSrcMemOperand ( MI , OpNo ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


"value of -mirq-ctrl-saved must have form R0-REGx"

"last register name %s must be an odd register"

Parse -mirq-ctrl-saved=RegisterRange , blink , lp_copunt . The register range is specified as two registers separated by a dash . It always starts with r0 , and its upper limit is fp register . blink and lp_count registers are optional .


<s> unsigned HSAILTargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const SelectionDAG & DAG , unsigned Depth ) const { return 1 ; } </s>

Determine the number of bits in the operation that are sign bits .


<s> int rl78_force_nonfar_3 ( rtx * operands , rtx ( * gen ) ( rtx , rtx , rtx ) ) { int did = 0 ; rtx temp_reg = NULL ; if ( rl78_far_p ( operands [ 1 ] ) ) { rtx temp_reg = gen_reg_rtx ( GET_MODE ( operands [ 1 ] ) ) ; emit_move_insn ( temp_reg , operands [ 1 ] ) ; operands [ 1 ] = temp_reg ; did = 1 ; } if ( rl78_far_p ( operands [ 0 ] ) ) { temp_reg = operands [ 0 ] ; operands [ 0 ] = gen_reg_rtx ( GET_MODE ( operands [ 0 ] ) ) ; did = 1 ; } if ( ! did ) return 0 ; emit_insn ( gen ( operands [ 0 ] , operands [ 1 ] , operands [ 2 ] ) ) ; if ( temp_reg ) emit_move_insn ( temp_reg , operands [ 0 ] ) ; return 1 ; } </s>

Likewise , but for three-operand expanders .


<s>
void
J2DAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
SDLoc
DL
(
Node
)
;
switch
(
Node
->
getOpcode
(
)
)
{
case
ISD
::
FrameIndex
:
assert
(
Node
->
getValueType
(
0
)
==
MVT
::
i32
)
;
int
FI
=
cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
MVT
::
i32
)
;
const
auto
Opc
=
J2
::
MOV32rr
;
CurDAG
->
SelectNodeTo
(
Node
,
Opc
,
MVT
::
i32
,
TFI
)
;
return
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> uint64_t AArch64GOT :: emit ( MemoryRegion & pRegion ) { uint64_t * buffer = reinterpret_cast < uint64_t * > ( pRegion . begin ( ) ) ; AArch64GOTEntry * got = NULL ; uint64_t result = 0x0 ; for ( iterator it = begin ( ) , ie = end ( ) ; it != ie ; ++ it , ++ buffer ) { got = & ( llvm :: cast < AArch64GOTEntry > ( ( * it ) ) ) ; * buffer = static_cast < uint64_t > ( got -> getValue ( ) ) ; result += AArch64GOTEntry :: EntrySize ; } return result ; } </s>

Output the remark via the diagnostic handler and to the optimization record file .


<s>
void
SIScheduleBlock
::
releaseSucc
(
SUnit
*
SU
,
SDep
*
SuccEdge
)
{
SUnit
*
SuccSU
=
SuccEdge
->
getSUnit
(
)
;
if
(
SuccEdge
->
isWeak
(
)
)
{
SuccSU
->
WeakPredsLeft
;
return
;
}
if
(
SuccSU
->
NumPredsLeft
==
0
)
{
dbgs
(
)
<<
"*** Scheduling failed! ***\n"
;
SuccSU
->
dump
(
DAG
)
;
dbgs
(
)
<<
" has been released too many times!\n"
;
llvm_unreachable
(
nullptr
)
;
}
SuccSU
->
NumPredsLeft
;
}
</s>

ReleaseSucc - Decrement the NumPredsLeft count of a successor .

AMDGPU
SI
0
"*** Scheduling failed! ***\n"
" has been released too many times!\n"


<s> const char * MSP430TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( MSP430ISD :: NodeType ) Opcode ) { case MSP430ISD :: FIRST_NUMBER : break ; case MSP430ISD :: RET_FLAG : return "MSP430ISD::RET_FLAG" ; case MSP430ISD :: RETI_FLAG : return "MSP430ISD::RETI_FLAG" ; case MSP430ISD :: RRA : return "MSP430ISD::RRA" ; case MSP430ISD :: RLA : return "MSP430ISD::RLA" ; case MSP430ISD :: RRC : return "MSP430ISD::RRC" ; case MSP430ISD :: CALL : return "MSP430ISD::CALL" ; case MSP430ISD :: Wrapper : return "MSP430ISD::Wrapper" ; case MSP430ISD :: BR_CC : return "MSP430ISD::BR_CC" ; case MSP430ISD :: CMP : return "MSP430ISD::CMP" ; case MSP430ISD :: SETCC : return "MSP430ISD::SETCC" ; case MSP430ISD :: SELECT_CC : return "MSP430ISD::SELECT_CC" ; case MSP430ISD :: SHL : return "MSP430ISD::SHL" ; case MSP430ISD :: SRA : return "MSP430ISD::SRA" ; case MSP430ISD :: SRL : return "MSP430ISD::SRL" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> unsigned char AArch64Subtarget :: ClassifyGlobalReference ( const GlobalValue * GV , const TargetMachine & TM ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) ) return AArch64II :: MO_GOT ; unsigned Flags = GV -> hasDLLImportStorageClass ( ) ? AArch64II :: MO_DLLIMPORT : AArch64II :: MO_NO_FLAG ; if ( ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return AArch64II :: MO_GOT | Flags ; if ( useSmallAddressing ( ) && GV -> hasExternalWeakLinkage ( ) ) return AArch64II :: MO_GOT | Flags ; return Flags ; } </s>

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be referenced for the current subtarget .


<s> SDValue MipsTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SDNode * CallNode , const Type * RetTy ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; MipsCC MipsCCInfo ( CallConv , Subtarget . isABI_O32 ( ) , Subtarget . isFP64bit ( ) , CCInfo ) ; MipsCCInfo . analyzeCallResult ( Ins , Subtarget . abiUsesSoftFloat ( ) , CallNode , RetTy ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( 1 ) ; InFlag = Val . getValue ( 2 ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( ISD :: BITCAST , DL , RVLocs [ i ] . getValVT ( ) , Val ) ; InVals . push_back ( Val ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> void Reset ( ) { Ops . clear ( ) ; OpBegins . clear ( ) ; OpBegins . push_back ( 0 ) ; HasPersonality = false ; } </s>


<s> bool ARMAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AFI = MF . getInfo < ARMFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; Subtarget = & MF . getSubtarget < ARMSubtarget > ( ) ; SetupMachineFunction ( MF ) ; const Function & F = MF . getFunction ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; for ( auto * GV : AFI -> getGlobalsPromotedToConstantPool ( ) ) PromotedGlobals . insert ( GV ) ; unsigned OptimizationGoal ; if ( F . hasOptNone ( ) ) OptimizationGoal = 6 ; else if ( F . hasMinSize ( ) ) OptimizationGoal = 4 ; else if ( F . hasOptSize ( ) ) OptimizationGoal = 3 ; else if ( TM . getOptLevel ( ) == CodeGenOpt :: Aggressive ) OptimizationGoal = 2 ; else if ( TM . getOptLevel ( ) > CodeGenOpt :: None ) OptimizationGoal = 1 ; else OptimizationGoal = 5 ; if ( OptimizationGoals == - 1 ) OptimizationGoals = OptimizationGoal ; else if ( OptimizationGoals != ( int ) OptimizationGoal ) OptimizationGoals = 0 ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = F . hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer -> EmitCOFFSymbolType ( Type ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; emitXRayTable ( ) ; if ( ! ThumbIndirectPads . empty ( ) ) { OutStreamer -> EmitAssemblerFlag ( MCAF_Code16 ) ; EmitAlignment ( 1 ) ; for ( std :: pair < unsigned , MCSymbol * > & TIP : ThumbIndirectPads ) { OutStreamer -> EmitLabel ( TIP . second ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( ARM :: tBX ) . addReg ( TIP . first ) . addImm ( ARMCC :: AL ) . addReg ( 0 ) ) ; } ThumbIndirectPads . clear ( ) ; } return false ; } </s>


<s> bool AArch64FrameLowering :: canUseRedZone ( const MachineFunction & MF ) const { if ( ! EnableRedZone ) return false ; if ( MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoRedZone ) ) return false ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const AArch64FunctionInfo * AFI = MF . getInfo < AArch64FunctionInfo > ( ) ; unsigned NumBytes = AFI -> getLocalStackSize ( ) ; return ! ( MFI . hasCalls ( ) || hasFP ( MF ) || NumBytes > 128 ) ; } </s>

Can this function use the red zone for local allocations .


<s>
void
WebAssemblyTargetAsmStreamer
::
emitFunctionType
(
const
MCSymbolWasm
*
Sym
)
{
assert
(
Sym
->
isFunction
(
)
)
;
OS
<<
"\t.functype\t"
<<
Sym
->
getName
(
)
<<
" "
;
emitSignature
(
Sym
->
getSignature
(
)
)
;
OS
<<
"\n"
;
}
</s>

WebAssembly
WebAssembly
"\t.functype\t"
" "
"\n"


<s>
static
void
output_file_start
(
void
)
{
FILE
*
file
=
asm_out_file
;
int
i
;
fprintf
(
file
,
".file \"%s\";\n"
,
input_filename
)
;
for
(
i
=
0
;
arg_regs
[
i
]
>=
0
;
i
++
)
;
max_arg_registers
=
i
;
}
</s>

Output to FILE the start of the assembler file .


Try to add a comment on the PC-relative load .


"%<-mexr%> is used without %<-ms%> or %<-msx%>"

"%<-mno-exr%> is valid only with %<-ms%> or "

"%<-mn%> is not supported for linux targets"

Initialize various cpu specific globals at start up .


<s> std :: unique_ptr < MCObjectWriter > createObjectWriter ( raw_pwrite_stream & OS ) const override { return createARMMachObjectWriter ( OS , false , MachO :: CPU_TYPE_ARM , Subtype ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s>
bool
m32c_mov_ok
(
rtx
*
operands
,
machine_mode
mode
ATTRIBUTE_UNUSED
)
{
rtx
op0
=
operands
[
0
]
;
rtx
op1
=
operands
[
1
]
;
if
(
TARGET_A24
)
return
true
;
fprintf
(
stderr
,
"m32c_mov_ok %s\n"
,
mode_name
[
mode
]
)
;
debug_rtx
(
op0
)
;
debug_rtx
(
op1
)
;
if
(
GET_CODE
(
op0
)
==
SUBREG
)
op0
=
XEXP
(
op0
,
0
)
;
if
(
GET_CODE
(
op1
)
==
SUBREG
)
op1
=
XEXP
(
op1
,
0
)
;
if
(
GET_CODE
(
op0
)
==
MEM
&&
GET_CODE
(
op1
)
==
MEM
&&
!
reload_completed
)
{
fprintf
(
stderr
,
" - no, mem to mem\n"
)
;
return
false
;
}
fprintf
(
stderr
,
" - ok\n"
)
;
return
true
;
}
</s>

Returns TRUE if we support a move between the first two operands . At the moment , we just want to discourage mem to mem moves until after reload , because reload has a hard time with our limited number of address registers , and we can get into a situation where we need three of them when we only have two .


<s>
bool
LanaiInstrInfo
::
areMemAccessesTriviallyDisjoint
(
MachineInstr
*
MIa
,
MachineInstr
*
MIb
,
AliasAnalysis
*
AA
)
const
{
assert
(
MIa
&&
MIa
->
mayLoadOrStore
(
)
&&
"MIa must be a load or store."
)
;
assert
(
MIb
&&
MIb
->
mayLoadOrStore
(
)
&&
"MIb must be a load or store."
)
;
if
(
MIa
->
hasUnmodeledSideEffects
(
)
||
MIb
->
hasUnmodeledSideEffects
(
)
||
MIa
->
hasOrderedMemoryRef
(
)
||
MIb
->
hasOrderedMemoryRef
(
)
)
return
false
;
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
unsigned
BaseRegA
=
0
,
BaseRegB
=
0
;
int64_t
OffsetA
=
0
,
OffsetB
=
0
;
unsigned
int
WidthA
=
0
,
WidthB
=
0
;
if
(
getMemOpBaseRegImmOfsWidth
(
MIa
,
BaseRegA
,
OffsetA
,
WidthA
,
TRI
)
&&
getMemOpBaseRegImmOfsWidth
(
MIb
,
BaseRegB
,
OffsetB
,
WidthB
,
TRI
)
)
{
if
(
BaseRegA
==
BaseRegB
)
{
int
LowOffset
=
std
::
min
(
OffsetA
,
OffsetB
)
;
int
HighOffset
=
std
::
max
(
OffsetA
,
OffsetB
)
;
int
LowWidth
=
(
LowOffset
==
OffsetA
)
WidthA
:
WidthB
;
if
(
LowOffset
+
LowWidth
<=
HighOffset
)
return
true
;
}
}
return
false
;
}
</s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s>
void
insert
(
MachineInstr
*
MI
)
{
Insts
.
push_back
(
MI
)
;
assert
(
Insts
.
size
(
)
<=
5
&&
"Too many instructions in VPT block!"
)
;
}
</s>

insert - Append entry to the vector if it does n't already exist .

ARM
5
"Too many instructions in VPT block!"


"Switch should handle all register classes"


<s>
static
void
csky_print_operand_address
(
FILE
*
stream
,
machine_mode
mode
ATTRIBUTE_UNUSED
,
rtx
x
)
{
struct
csky_address
addr
;
decompose_csky_address
(
x
,
&
addr
)
;
if
(
addr
.
label
&&
addr
.
disp
&&
GET_CODE
(
addr
.
disp
)
==
CONST_INT
)
{
fprintf
(
stream
,
"["
)
;
csky_output_constpool_label
(
stream
,
addr
.
label
)
;
fprintf
(
stream
,
"+%d]"
,
(
int
)
INTVAL
(
addr
.
disp
)
)
;
}
else
if
(
addr
.
label
)
{
fprintf
(
stream
,
"["
)
;
csky_output_constpool_label
(
stream
,
addr
.
label
)
;
fprintf
(
stream
,
"]"
)
;
}
else
if
(
addr
.
symbol
&&
addr
.
disp
&&
GET_CODE
(
addr
.
disp
)
==
CONST_INT
)
{
fprintf
(
stream
,
"["
)
;
output_addr_const
(
stream
,
addr
.
symbol
)
;
fprintf
(
stream
,
"+%d]"
,
(
int
)
INTVAL
(
addr
.
disp
)
)
;
}
else
if
(
addr
.
symbol
)
{
fprintf
(
stream
,
"["
)
;
output_addr_const
(
stream
,
addr
.
symbol
)
;
fprintf
(
stream
,
"]"
)
;
}
else
if
(
addr
.
disp
&&
GET_CODE
(
addr
.
disp
)
==
CONST_INT
)
fprintf
(
stream
,
"(%s, %d)"
,
reg_names
[
REGNO
(
addr
.
base
)
]
,
(
int
)
INTVAL
(
addr
.
disp
)
)
;
else
if
(
addr
.
disp
&&
GET_CODE
(
addr
.
disp
)
==
UNSPEC
)
{
if
(
REGNO
(
addr
.
base
)
!=
CSKY_GB_REGNUM
)
fprintf
(
stream
,
"(%s, "
,
reg_names
[
REGNO
(
addr
.
base
)
]
)
;
else
fprintf
(
stream
,
"["
)
;
csky_output_pic_addr_const
(
stream
,
addr
.
disp
,
0
)
;
fprintf
(
stream
,
"%s"
,
(
REGNO
(
addr
.
base
)
!=
CSKY_GB_REGNUM
)
")"
:
"]"
)
;
}
else
if
(
addr
.
index
)
fprintf
(
stream
,
"(%s, %s << %d)"
,
reg_names
[
REGNO
(
addr
.
base
)
]
,
reg_names
[
REGNO
(
addr
.
index
)
]
,
exact_log2
(
(
int
)
(
addr
.
scale
)
)
)
;
else
fprintf
(
stream
,
"(%s, 0)"
,
reg_names
[
REGNO
(
addr
.
base
)
]
)
;
}
</s>


<s>
bool
AArch64FrameLowering
::
spillCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
;
SmallVector
<
RegPairInfo
,
8
>
RegPairs
;
computeCalleeSaveRegisterPairs
(
MF
,
CSI
,
TRI
,
RegPairs
)
;
const
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
for
(
auto
RPII
=
RegPairs
.
rbegin
(
)
,
RPIE
=
RegPairs
.
rend
(
)
;
RPII
!=
RPIE
;
++
RPII
)
{
RegPairInfo
RPI
=
*
RPII
;
unsigned
Reg1
=
RPI
.
Reg1
;
unsigned
Reg2
=
RPI
.
Reg2
;
unsigned
StrOpc
;
if
(
RPI
.
IsGPR
)
StrOpc
=
RPI
.
isPaired
(
)
AArch64
::
STPXi
:
AArch64
::
STRXui
;
else
StrOpc
=
RPI
.
isPaired
(
)
AArch64
::
STPDi
:
AArch64
::
STRDui
;
DEBUG
(
dbgs
(
)
<<
"CSR spill: ("
<<
TRI
->
getName
(
Reg1
)
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
TRI
->
getName
(
Reg2
)
;
dbgs
(
)
<<
") -> fi#("
<<
RPI
.
FrameIdx
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
RPI
.
FrameIdx
+
1
;
dbgs
(
)
<<
")\n"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
StrOpc
)
)
;
if
(
!
MRI
.
isReserved
(
Reg1
)
)
MBB
.
addLiveIn
(
Reg1
)
;
if
(
RPI
.
isPaired
(
)
)
{
if
(
!
MRI
.
isReserved
(
Reg2
)
)
MBB
.
addLiveIn
(
Reg2
)
;
MIB
.
addReg
(
Reg2
,
getPrologueDeath
(
MF
,
Reg2
)
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
+
1
)
,
MachineMemOperand
::
MOStore
,
8
,
8
)
)
;
}
MIB
.
addReg
(
Reg1
,
getPrologueDeath
(
MF
,
Reg1
)
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
RPI
.
Offset
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
)
,
MachineMemOperand
::
MOStore
,
8
,
8
)
)
;
}
return
true
;
}
</s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static const char * sparc_mangle_fundamental_type ( tree type ) { if ( ! TARGET_64BIT && TYPE_MAIN_VARIANT ( type ) == long_double_type_node && TARGET_LONG_DOUBLE_128 ) return "g" ; return NULL ; } </s>


<s> bool ARMTargetLowering :: isVectorLoadExtDesirable ( SDValue ExtVal ) const { EVT VT = ExtVal . getValueType ( ) ; if ( ! isTypeLegal ( VT ) ) return false ; if ( ExtVal -> use_empty ( ) || ! ExtVal -> use_begin ( ) -> isOnlyUserOf ( ExtVal . getNode ( ) ) ) return true ; SDNode * U = * ExtVal -> use_begin ( ) ; if ( ( U -> getOpcode ( ) == ISD :: ADD || U -> getOpcode ( ) == ISD :: SUB || U -> getOpcode ( ) == ISD :: SHL || U -> getOpcode ( ) == ARMISD :: VSHLIMM ) ) return false ; return true ; } </s>

Return true if folding a vector load into ExtVal ( a sign , zero , or any extend node ) is profitable .

ARM ARM ISD::ADD ISD::SUB ISD::SHL ARMISD::VSHLIMM


"\nm32c_legitimize_reload_address for mode %s\n"

Implements LEGITIMIZE_RELOAD_ADDRESS . See comment above .


<s> bool ARMPassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge ) PM -> add ( createGlobalMergePass ( TM -> getTargetLowering ( ) ) ) ; return false ; } </s>


<s> bool isLegalMaskedStore ( Type * DataType , MaybeAlign Alignment ) { return isVectorLaneType ( * getLaneType ( DataType ) ) ; } </s>

Return true if the target supports masked store .


<s> void KudeyarAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( MI -> isDebugValue ( ) ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; PrintDebugValueComment ( MI , OS ) ; return ; } MCInst TmpInst0 ; MCInstLowering . Lower ( MI , TmpInst0 ) ; OutStreamer . EmitInstruction ( TmpInst0 ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void AArch64MacroFusion :: apply ( ScheduleDAGInstrs * DAGInstrs ) { ScheduleDAGMI * DAG = static_cast < ScheduleDAGMI * > ( DAGInstrs ) ; for ( SUnit & ASU : DAG -> SUnits ) scheduleAdjacentImpl ( DAG , & ASU , ASU . Succs , false ) ; scheduleAdjacentImpl ( DAG , & DAG -> ExitSU , DAG -> ExitSU . Preds , true ) ; } </s>

Apply the profile inference algorithm for a given function .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { FunctionPass :: getAnalysisUsage ( AU ) ; AU . addRequired < AssumptionCacheTracker > ( ) ; AU . addRequired < ScalarEvolutionWrapperPass > ( ) ; AU . addRequired < AAResultsWrapperPass > ( ) ; AU . addRequired < TargetLibraryInfoWrapperPass > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addRequired < TargetPassConfig > ( ) ; AU . addPreserved < ScalarEvolutionWrapperPass > ( ) ; AU . addPreserved < GlobalsAAWrapperPass > ( ) ; AU . setPreservesCFG ( ) ; } </s>


<s> static int loongarch_move_from_gpr_cost ( reg_class_t to ) { switch ( to ) { case GENERAL_REGS : return 2 ; case FP_REGS : return 4 ; default : return 0 ; } } </s>

Return the cost of moving a value from a GPR to a register of class TO . Return 0 for classes that are unions of other classes handled by this function .


<s> bool SITypeRewriter :: doInitialization ( Module & M ) { Mod = & M ; v16i8 = VectorType :: get ( Type :: getInt8Ty ( M . getContext ( ) ) , 16 ) ; v4i32 = VectorType :: get ( Type :: getInt32Ty ( M . getContext ( ) ) , 4 ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> void h8300_expand_prologue ( void ) { int regno ; int saved_regs ; int n_regs ; if ( h8300_os_task_function_p ( current_function_decl ) ) return ; if ( h8300_monitor_function_p ( current_function_decl ) ) emit_insn ( gen_monitor_prologue ( ) ) ; if ( frame_pointer_needed ) { push ( HARD_FRAME_POINTER_REGNUM ) ; emit_move_insn ( hard_frame_pointer_rtx , stack_pointer_rtx ) ; } saved_regs = compute_saved_regs ( ) ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno += n_regs ) { n_regs = 1 ; if ( saved_regs & ( 1 << regno ) ) { if ( TARGET_H8300S ) { if ( ( ! TARGET_H8300SX || ( regno & 3 ) == 0 ) && ( ( saved_regs >> regno ) & 0x0f ) == 0x0f ) n_regs = 4 ; else if ( ( ! TARGET_H8300SX || ( regno & 3 ) == 0 ) && ( ( saved_regs >> regno ) & 0x07 ) == 0x07 ) n_regs = 3 ; else if ( ( ! TARGET_H8300SX || ( regno & 1 ) == 0 ) && ( ( saved_regs >> regno ) & 0x03 ) == 0x03 ) n_regs = 2 ; } h8300_push_pop ( regno , n_regs , 0 , 0 ) ; } } h8300_emit_stack_adjustment ( - 1 , round_frame_size ( get_frame_size ( ) ) ) ; } </s>

Generate RTL code for the function prologue .


<s> static void pa_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain_value ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx start_addr = gen_reg_rtx ( Pmode ) ; rtx end_addr = gen_reg_rtx ( Pmode ) ; rtx line_length = gen_reg_rtx ( Pmode ) ; rtx r_tramp , tmp ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ; r_tramp = force_reg ( Pmode , XEXP ( m_tramp , 0 ) ) ; if ( ! TARGET_64BIT ) { tmp = adjust_address ( m_tramp , Pmode , 36 ) ; emit_move_insn ( tmp , fnaddr ) ; tmp = adjust_address ( m_tramp , Pmode , 40 ) ; emit_move_insn ( tmp , chain_value ) ; tmp = adjust_address ( m_tramp , Pmode , 44 ) ; emit_move_insn ( tmp , r_tramp ) ; tmp = adjust_address ( m_tramp , Pmode , 48 ) ; emit_move_insn ( tmp , gen_rtx_REG ( Pmode , 19 ) ) ; emit_insn ( gen_andsi3 ( start_addr , r_tramp , GEN_INT ( - MIN_CACHELINE_SIZE ) ) ) ; tmp = force_reg ( Pmode , plus_constant ( Pmode , r_tramp , TRAMPOLINE_CODE_SIZE - 1 ) ) ; emit_insn ( gen_andsi3 ( end_addr , tmp , GEN_INT ( - MIN_CACHELINE_SIZE ) ) ) ; emit_move_insn ( line_length , GEN_INT ( MIN_CACHELINE_SIZE ) ) ; emit_insn ( gen_dcacheflushsi ( start_addr , end_addr , line_length ) ) ; emit_insn ( gen_icacheflushsi ( start_addr , end_addr , line_length , gen_reg_rtx ( Pmode ) , gen_reg_rtx ( Pmode ) ) ) ; } else { tmp = adjust_address ( m_tramp , Pmode , 56 ) ; emit_move_insn ( tmp , fnaddr ) ; tmp = adjust_address ( m_tramp , Pmode , 64 ) ; emit_move_insn ( tmp , chain_value ) ; tmp = adjust_address ( m_tramp , Pmode , 16 ) ; emit_move_insn ( tmp , force_reg ( Pmode , plus_constant ( Pmode , r_tramp , 32 ) ) ) ; tmp = adjust_address ( m_tramp , Pmode , 24 ) ; emit_move_insn ( tmp , gen_rtx_REG ( Pmode , 27 ) ) ; tmp = force_reg ( Pmode , plus_constant ( Pmode , r_tramp , 32 ) ) ; emit_insn ( gen_anddi3 ( start_addr , tmp , GEN_INT ( - MIN_CACHELINE_SIZE ) ) ) ; tmp = force_reg ( Pmode , plus_constant ( Pmode , tmp , TRAMPOLINE_CODE_SIZE - 1 ) ) ; emit_insn ( gen_anddi3 ( end_addr , tmp , GEN_INT ( - MIN_CACHELINE_SIZE ) ) ) ; emit_move_insn ( line_length , GEN_INT ( MIN_CACHELINE_SIZE ) ) ; emit_insn ( gen_dcacheflushdi ( start_addr , end_addr , line_length ) ) ; emit_insn ( gen_icacheflushdi ( start_addr , end_addr , line_length , gen_reg_rtx ( Pmode ) , gen_reg_rtx ( Pmode ) ) ) ; } emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , "__enable_execute_stack" ) , LCT_NORMAL , VOIDmode , XEXP ( m_tramp , 0 ) , Pmode ) ; } </s>

Emit RTL insns to initialize the variable parts of a trampoline . FNADDR is an RTX for the address of the function 's pure code . CXT is an RTX for the static chain value for the function . Move the function address to the trampoline template at offset 36 . Move the static chain value to trampoline template at offset 40 . Move the trampoline address to trampoline template at offset 44 . Move r19 to trampoline template at offset 48 . The latter two words create a plabel for the indirect call to the trampoline . A similar sequence is used for the 64-bit port but the plabel is at the beginning of the trampoline . Finally , the cache entries for the trampoline code are flushed . This is necessary to ensure that the trampoline instruction sequence is written to memory prior to any attempts at prefetching the code sequence .


<s> static bool match_pcrel_step1 ( rtx insn ) { rtx pattern = PATTERN ( insn ) ; rtx src ; if ( GET_CODE ( pattern ) != SET ) return false ; src = SET_SRC ( pattern ) ; return ( GET_CODE ( src ) == CONST && GET_CODE ( XEXP ( src , 0 ) ) == UNSPEC && XINT ( XEXP ( src , 0 ) , 1 ) == UNSPEC_HW1_LAST_PCREL ) ; } </s>

Returns true if INSN is the first instruction of a pc-relative address compuatation .


<s> static bool has_dispatch ( rtx_insn * insn , int action ) { if ( ( TARGET_BDVER1 || TARGET_BDVER2 || TARGET_BDVER3 || TARGET_BDVER4 ) && flag_dispatch_scheduler ) switch ( action ) { default : return false ; case IS_DISPATCH_ON : return true ; break ; case IS_CMP : return is_cmp ( insn ) ; case DISPATCH_VIOLATION : return dispatch_violation ( ) ; case FITS_DISPATCH_WINDOW : return fits_dispatch_window ( insn ) ; } return false ; } </s>

Return TRUE if Dispatch Scheduling is supported .


<s> bool MipsBranchExpansion :: runOnMachineFunction ( MachineFunction & MF ) { const TargetMachine & TM = MF . getTarget ( ) ; IsPIC = TM . isPositionIndependent ( ) ; ABI = static_cast < const MipsTargetMachine & > ( TM ) . getABI ( ) ; STI = & static_cast < const MipsSubtarget & > ( MF . getSubtarget ( ) ) ; TII = static_cast < const MipsInstrInfo * > ( STI -> getInstrInfo ( ) ) ; if ( IsPIC && ABI . IsO32 ( ) && MF . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( MF , TII ) ; MFp = & MF ; ForceLongBranchFirstPass = ForceLongBranch ; bool longBranchChanged = handlePossibleLongBranch ( ) ; bool forbiddenSlotChanged = handleForbiddenSlot ( ) ; bool fpuDelaySlotChanged = handleFPUDelaySlot ( ) ; bool Changed = longBranchChanged || forbiddenSlotChanged || fpuDelaySlotChanged ; while ( forbiddenSlotChanged ) { longBranchChanged = handlePossibleLongBranch ( ) ; fpuDelaySlotChanged = handleFPUDelaySlot ( ) ; if ( ! longBranchChanged && ! fpuDelaySlotChanged ) break ; forbiddenSlotChanged = handleForbiddenSlot ( ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool aarch64_macro_fusion_p ( void ) { return aarch64_tune_params . fusible_ops != AARCH64_FUSE_NOTHING ; } </s>

Implement TARGET_SCHED_MACRO_FUSION_P . Return true if target supports instruction fusion of some sort .


Internal function to either define or undef the appropriate system macros .


<s> void rbt_dump ( struct rbt_strings * t , struct rbt_string_node * subtree ) { if ( subtree != t -> rbt_nil ) { rbt_dump ( t , subtree -> left ) ; fprintf ( stderr , "%s\n" , subtree -> str ) ; rbt_dump ( t , subtree -> right ) ; } } </s>

Inorder dump of the binary search tree .


"loadRegFromStackSlot didn't insert any code!"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> int arm_const_double_rtx ( rtx x ) { const REAL_VALUE_TYPE * r ; if ( ! fp_consts_inited ) init_fp_table ( ) ; r = CONST_DOUBLE_REAL_VALUE ( x ) ; if ( REAL_VALUE_MINUS_ZERO ( * r ) ) return 0 ; if ( real_equal ( r , & value_fp0 ) ) return 1 ; return 0 ; } </s>

Return TRUE if rtx X is a valid immediate FP constant .


<s> bool MOVToLEAPass :: runOnMachineFunction ( MachineFunction & Fn ) { const TargetInstrInfo * TII = Fn . getSubtarget ( ) . getInstrInfo ( ) ; if ( Seed != 0 ) RNG . reset ( Fn . getFunction ( ) -> getParent ( ) -> createRNG ( Seed , this , Fn . getFunction ( ) -> getName ( ) ) ) ; else if ( ! RNG ) RNG . reset ( Fn . getFunction ( ) -> getParent ( ) -> createRNG ( this ) ) ; bool Changed = false ; for ( MachineFunction :: iterator BB = Fn . begin ( ) , E = Fn . end ( ) ; BB != E ; ++ BB ) for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ) { ++ PreMOVtoLEAInstructionCount ; if ( I -> getNumOperands ( ) != 2 || ! I -> getOperand ( 0 ) . isReg ( ) || ! I -> getOperand ( 1 ) . isReg ( ) ) { ++ I ; continue ; } unsigned leaOpc ; if ( I -> getOpcode ( ) == X86 :: MOV32rr ) { leaOpc = X86 :: LEA32r ; } else if ( I -> getOpcode ( ) == X86 :: MOV64rr ) { leaOpc = X86 :: LEA64r ; } else { ++ I ; continue ; } unsigned int Roll = RNG -> Random ( 100 ) ; ++ MOVCandidates ; if ( Roll >= multicompiler :: MOVToLEAPercentage ) { ++ I ; continue ; } ++ ReplacedMOV ; MachineBasicBlock :: iterator J = I ; ++ I ; addRegOffset ( BuildMI ( * BB , J , J -> getDebugLoc ( ) , TII -> get ( leaOpc ) , J -> getOperand ( 0 ) . getReg ( ) ) , J -> getOperand ( 1 ) . getReg ( ) , false , 0 ) ; J -> eraseFromParent ( ) ; Changed = true ; } return Changed ; } </s>


<s> static void avr_reorg ( void ) { rtx_insn * insn = get_insns ( ) ; for ( insn = next_real_insn ( insn ) ; insn ; insn = next_real_insn ( insn ) ) { rtx pattern = avr_compare_pattern ( insn ) ; if ( ! pattern ) continue ; if ( optimize && avr_reorg_remove_redundant_compare ( insn ) ) { continue ; } if ( compare_diff_p ( insn ) ) { rtx next = next_real_insn ( insn ) ; rtx pat = PATTERN ( next ) ; pattern = SET_SRC ( pattern ) ; if ( true_regnum ( XEXP ( pattern , 0 ) ) >= 0 && true_regnum ( XEXP ( pattern , 1 ) ) >= 0 ) { rtx x = XEXP ( pattern , 0 ) ; rtx src = SET_SRC ( pat ) ; rtx t = XEXP ( src , 0 ) ; PUT_CODE ( t , swap_condition ( GET_CODE ( t ) ) ) ; XEXP ( pattern , 0 ) = XEXP ( pattern , 1 ) ; XEXP ( pattern , 1 ) = x ; INSN_CODE ( next ) = - 1 ; } else if ( true_regnum ( XEXP ( pattern , 0 ) ) >= 0 && XEXP ( pattern , 1 ) == const0_rtx ) { rtx src = SET_SRC ( pat ) ; rtx t = XEXP ( src , 0 ) ; PUT_CODE ( t , swap_condition ( GET_CODE ( t ) ) ) ; XEXP ( pattern , 1 ) = XEXP ( pattern , 0 ) ; XEXP ( pattern , 0 ) = const0_rtx ; INSN_CODE ( next ) = - 1 ; INSN_CODE ( insn ) = - 1 ; } else if ( true_regnum ( XEXP ( pattern , 0 ) ) >= 0 && CONST_INT_P ( XEXP ( pattern , 1 ) ) ) { rtx x = XEXP ( pattern , 1 ) ; rtx src = SET_SRC ( pat ) ; rtx t = XEXP ( src , 0 ) ; machine_mode mode = GET_MODE ( XEXP ( pattern , 0 ) ) ; if ( avr_simplify_comparison_p ( mode , GET_CODE ( t ) , x ) ) { XEXP ( pattern , 1 ) = gen_int_mode ( INTVAL ( x ) + 1 , mode ) ; PUT_CODE ( t , avr_normalize_condition ( GET_CODE ( t ) ) ) ; INSN_CODE ( next ) = - 1 ; INSN_CODE ( insn ) = - 1 ; } } } } } </s>

This function optimizes conditional jumps .


<s> bool AMDGPUCFGStructurizer :: prepare ( ) { bool Changed = false ; LLVM_DEBUG ( dbgs ( ) << "AMDGPUCFGStructurizer::prepare\n" ; ) ; orderBlocks ( FuncRep ) ; SmallVector < MachineBasicBlock * , DEFAULT_VEC_SLOTS > RetBlks ; for ( MachineLoopInfo :: iterator It = MLI -> begin ( ) , E = MLI -> end ( ) ; It != E ; ++ It ) { MachineLoop * LoopRep = ( * It ) ; MBBVector ExitingMBBs ; LoopRep -> getExitingBlocks ( ExitingMBBs ) ; if ( ExitingMBBs . size ( ) == 0 ) { MachineBasicBlock * DummyExitBlk = normalizeInfiniteLoopExit ( LoopRep ) ; if ( DummyExitBlk ) RetBlks . push_back ( DummyExitBlk ) ; } } for ( MachineBasicBlock * MBB : OrderedBlks ) { removeUnconditionalBranch ( MBB ) ; removeRedundantConditionalBranch ( MBB ) ; if ( isReturnBlock ( MBB ) ) { RetBlks . push_back ( MBB ) ; } assert ( MBB -> succ_size ( ) <= 2 ) ; } if ( RetBlks . size ( ) >= 2 ) { addDummyExitBlock ( RetBlks ) ; Changed = true ; } return Changed ; } </s>

prepare - Reset state and prepare for a new spill placement computation .


"Not keeping track of debug information yet!!"

Map a target register to an equivalent dwarf register number .


<s>
void
PTXPassConfig
::
addMachineLateOptimization
(
)
{
if
(
addPass
(
BranchFolderPassID
)
!=
&
NoPassID
)
printAndVerify
(
"After BranchFolding"
)
;
if
(
addPass
(
TailDuplicateID
)
!=
&
NoPassID
)
printAndVerify
(
"After TailDuplicate"
)
;
}
</s>

Add passes that optimize machine instructions after register allocation .

PTX
PTX
"After BranchFolding"
"After TailDuplicate"


<s> bool doFinalization ( Module & M ) override { Result . reset ( ) ; return false ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> bool WinEHStatePass :: runOnFunction ( Function & F ) { if ( ! F . hasPersonalityFn ( ) ) return false ; PersonalityFn = dyn_cast < Function > ( F . getPersonalityFn ( ) -> stripPointerCasts ( ) ) ; if ( ! PersonalityFn ) return false ; Personality = classifyEHPersonality ( PersonalityFn ) ; if ( ! isFuncletEHPersonality ( Personality ) ) return false ; bool HasPads = false ; for ( BasicBlock & BB : F ) { if ( BB . isEHPad ( ) ) { HasPads = true ; break ; } } if ( ! HasPads ) return false ; Type * Int8PtrType = Type :: getInt8PtrTy ( TheModule -> getContext ( ) ) ; SetJmp3 = TheModule -> getOrInsertFunction ( "_setjmp3" , FunctionType :: get ( Type :: getInt32Ty ( TheModule -> getContext ( ) ) , { Int8PtrType , Type :: getInt32Ty ( TheModule -> getContext ( ) ) } , true ) ) ; F . addFnAttr ( "no-frame-pointer-elim" , "true" ) ; emitExceptionRegistrationRecord ( & F ) ; WinEHFuncInfo FuncInfo ; addStateStores ( F , FuncInfo ) ; PersonalityFn = nullptr ; Personality = EHPersonality :: Unknown ; UseStackGuard = false ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static bool aarch64_simd_call_p ( rtx_insn * insn ) { rtx symbol ; rtx call ; tree fndecl ; gcc_assert ( CALL_P ( insn ) ) ; call = get_call_rtx_from ( insn ) ; symbol = XEXP ( XEXP ( call , 0 ) , 0 ) ; if ( GET_CODE ( symbol ) != SYMBOL_REF ) return false ; fndecl = SYMBOL_REF_DECL ( symbol ) ; if ( ! fndecl ) return false ; return aarch64_simd_decl_p ( fndecl ) ; } </s>

Return true if the instruction is a call to a SIMD function , false if it is not a SIMD function or if we do not know anything about the function .


<s>
unsigned
MipsCodeEmitter
::
getMachineOpValue
(
const
MachineInstr
&
MI
,
const
MachineOperand
&
MO
)
const
{
if
(
MO
.
isReg
(
)
)
return
MipsRegisterInfo
::
getRegisterNumbering
(
MO
.
getReg
(
)
)
;
else
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
else
if
(
MO
.
isGlobal
(
)
)
{
if
(
MI
.
getOpcode
(
)
==
Mips
::
ULW
||
MI
.
getOpcode
(
)
==
Mips
::
USW
||
MI
.
getOpcode
(
)
==
Mips
::
ULH
||
MI
.
getOpcode
(
)
==
Mips
::
ULHu
)
emitGlobalAddressUnaligned
(
MO
.
getGlobal
(
)
,
getRelocation
(
MI
,
MO
)
,
4
)
;
else
if
(
MI
.
getOpcode
(
)
==
Mips
::
USH
)
emitGlobalAddressUnaligned
(
MO
.
getGlobal
(
)
,
getRelocation
(
MI
,
MO
)
,
8
)
;
else
emitGlobalAddress
(
MO
.
getGlobal
(
)
,
getRelocation
(
MI
,
MO
)
,
true
)
;
}
else
if
(
MO
.
isSymbol
(
)
)
emitExternalSymbolAddress
(
MO
.
getSymbolName
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isCPI
(
)
)
emitConstPoolAddress
(
MO
.
getIndex
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isJTI
(
)
)
emitJumpTableAddress
(
MO
.
getIndex
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isMBB
(
)
)
emitMachineBasicBlock
(
MO
.
getMBB
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
llvm_unreachable
(
"Unable to encode MachineOperand!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .

Mips
Mips
Mips
Mips::ULW
Mips::USW
Mips::ULH
Mips::ULHu
4
Mips::USH
8
"Unable to encode MachineOperand!"
0


<s>
StringRef
getPassName
(
)
const
override
{
return
"Workaround A53 erratum 835769 pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
int
X86FrameLowering
::
getFrameIndexReferencePreferSP
(
const
MachineFunction
&
MF
,
int
FI
,
unsigned
&
FrameReg
,
bool
IgnoreSPUpdates
)
const
{
const
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
const
uint64_t
StackSize
=
MFI
.
getStackSize
(
)
;
if
(
MFI
.
isFixedObjectIndex
(
FI
)
&&
TRI
->
needsStackRealignment
(
MF
)
&&
!
STI
.
isTargetWin64
(
)
)
return
getFrameIndexReference
(
MF
,
FI
,
FrameReg
)
;
const
TargetFrameLowering
*
TFI
=
MF
.
getSubtarget
(
)
.
getFrameLowering
(
)
;
if
(
!
IgnoreSPUpdates
&&
!
TFI
->
hasReservedCallFrame
(
MF
)
)
return
getFrameIndexReference
(
MF
,
FI
,
FrameReg
)
;
assert
(
MF
.
getInfo
<
X86MachineFunctionInfo
>
(
)
->
getTCReturnAddrDelta
(
)
>=
0
&&
"we don't handle this case!"
)
;
FrameReg
=
TRI
->
getStackRegister
(
)
;
int
Offset
=
MFI
.
getObjectOffset
(
FI
)
getOffsetOfLocalArea
(
)
;
return
Offset
+
StackSize
;
}
</s>

Same as getFrameIndexReference , except that the stack pointer ( as opposed to the frame pointer ) will be the preferred value for FrameReg .


<s> static rtx v850_function_arg ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; rtx result = NULL_RTX ; int size , align ; if ( ! arg . named ) return NULL_RTX ; size = arg . promoted_size_in_bytes ( ) ; size = ( size + UNITS_PER_WORD - 1 ) & ~ ( UNITS_PER_WORD - 1 ) ; if ( size < 1 ) { cum -> nbytes = 4 * UNITS_PER_WORD ; return NULL_RTX ; } if ( ! TARGET_GCC_ABI ) align = UNITS_PER_WORD ; else if ( size <= UNITS_PER_WORD && arg . type ) align = TYPE_ALIGN ( arg . type ) / BITS_PER_UNIT ; else align = size ; cum -> nbytes = ( cum -> nbytes + align - 1 ) & ~ ( align - 1 ) ; if ( cum -> nbytes > 4 * UNITS_PER_WORD ) return NULL_RTX ; if ( arg . type == NULL_TREE && cum -> nbytes + size > 4 * UNITS_PER_WORD ) return NULL_RTX ; switch ( cum -> nbytes / UNITS_PER_WORD ) { case 0 : result = gen_rtx_REG ( arg . mode , 6 ) ; break ; case 1 : result = gen_rtx_REG ( arg . mode , 7 ) ; break ; case 2 : result = gen_rtx_REG ( arg . mode , 8 ) ; break ; case 3 : result = gen_rtx_REG ( arg . mode , 9 ) ; break ; default : result = NULL_RTX ; } return result ; } </s>

Return an RTX to represent where an argument with mode MODE and type TYPE will be passed to a function . If the result is NULL_RTX , the argument will be pushed .


<s> bool Z80ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { getAnalysis < LiveIntervals > ( ) . addKillFlags ( & getAnalysis < VirtRegMap > ( ) ) ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; bool Modified = false ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s>
bool
AArch64PostLegalizerCombiner
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
MF
.
getProperties
(
)
.
hasProperty
(
MachineFunctionProperties
::
Property
::
FailedISel
)
)
return
false
;
assert
(
MF
.
getProperties
(
)
.
hasProperty
(
MachineFunctionProperties
::
Property
::
Legalized
)
&&
"Expected a legalized function?"
)
;
auto
*
TPC
=
&
getAnalysis
<
TargetPassConfig
>
(
)
;
const
Function
&
F
=
MF
.
getFunction
(
)
;
bool
EnableOpt
=
MF
.
getTarget
(
)
.
getOptLevel
(
)
!=
CodeGenOpt
::
&&
!
skipFunction
(
F
)
;
GISelKnownBits
*
KB
=
&
getAnalysis
<
GISelKnownBitsAnalysis
>
(
)
.
get
(
MF
)
;
MachineDominatorTree
*
MDT
=
IsOptNone
nullptr
:
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
AArch64PostLegalizerCombinerInfo
PCInfo
(
EnableOpt
,
F
.
hasOptSize
(
)
,
F
.
hasMinSize
(
)
,
KB
,
MDT
)
;
Combiner
C
(
PCInfo
,
TPC
)
;
return
C
.
combineMachineInstrs
(
MF
,
nullptr
)
;
}
</s>


<s> void assignValueToAddress ( Register ValVReg , Register Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { MachineFunction & MF = MIRBuilder . getMF ( ) ; unsigned Align = inferAlignmentFromPtrInfo ( MF , MPO ) ; auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant , Size , Align ) ; MIRBuilder . buildLoad ( ValVReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveAArch64CodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } if ( getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) { this -> Options . TrapUnreachable = true ; } if ( getOptLevel ( ) <= EnableGlobalISelAtO ) { setGlobalISel ( true ) ; setGlobalISelAbort ( GlobalISelAbortMode :: Disable ) ; } setMachineOutliner ( true ) ; setSupportsDefaultOutlining ( true ) ; } </s>


<s> rtx function_value ( const_tree valtype , const_tree func ATTRIBUTE_UNUSED , machine_mode mode ) { unsigned int regnum , dummy ATTRIBUTE_UNUSED ; enum mode_class mclass ; gcc_assert ( ! valtype || ! alpha_return_in_memory ( valtype , func ) ) ; if ( valtype ) mode = TYPE_MODE ( valtype ) ; mclass = GET_MODE_CLASS ( mode ) ; switch ( mclass ) { case MODE_INT : if ( ! ( TARGET_ABI_OPEN_VMS && valtype && AGGREGATE_TYPE_P ( valtype ) ) ) PROMOTE_MODE ( mode , dummy , valtype ) ; case MODE_COMPLEX_INT : case MODE_VECTOR_INT : regnum = 0 ; break ; case MODE_FLOAT : regnum = 32 ; break ; case MODE_COMPLEX_FLOAT : { machine_mode cmode = GET_MODE_INNER ( mode ) ; return gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( cmode , 32 ) , const0_rtx ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( cmode , 33 ) , GEN_INT ( GET_MODE_SIZE ( cmode ) ) ) ) ) ; } case MODE_RANDOM : gcc_assert ( TARGET_ABI_OPEN_VMS && mode == BLKmode ) ; regnum = 0 ; break ; default : gcc_unreachable ( ) ; } return gen_rtx_REG ( mode , regnum ) ; } </s>

Handle FUNCTION_VALUE , FUNCTION_OUTGOING_VALUE , and LIBCALL_VALUE macros . For v9 , function return values are subject to the same rules as arguments , except that up to 32 bytes may be returned in registers .


<s> bool AAPFrameLowering :: hasFP ( const MachineFunction & MF ) const { return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> int ccr_bit ( rtx op , int scc_p ) { enum rtx_code code = GET_CODE ( op ) ; enum machine_mode cc_mode ; int cc_regnum ; int base_bit ; rtx reg ; if ( ! COMPARISON_P ( op ) ) return - 1 ; reg = XEXP ( op , 0 ) ; gcc_assert ( GET_CODE ( reg ) == REG && CR_REGNO_P ( REGNO ( reg ) ) ) ; cc_mode = GET_MODE ( reg ) ; cc_regnum = REGNO ( reg ) ; base_bit = 4 * ( cc_regnum - CR0_REGNO ) ; validate_condition_mode ( code , cc_mode ) ; gcc_assert ( ! scc_p || code == EQ || code == GT || code == LT || code == UNORDERED || code == GTU || code == LTU ) ; switch ( code ) { case NE : return scc_p ? base_bit + 3 : base_bit + 2 ; case EQ : return base_bit + 2 ; case GT : case GTU : case UNLE : return base_bit + 1 ; case LT : case LTU : case UNGE : return base_bit ; case ORDERED : case UNORDERED : return base_bit + 3 ; case GE : case GEU : return scc_p ? base_bit + 3 : base_bit ; case LE : case LEU : return scc_p ? base_bit + 3 : base_bit + 1 ; default : gcc_unreachable ( ) ; } } </s>

Given a comparison operation , return the bit number in CCR to test . We know this is a valid comparison . SCC_P is 1 if this is for an scc . That means that % D will have been used instead of % C , so the bits will be in different places . Return -1 if OP is n't a valid comparison for some reason .


<s> unsigned getGlobalBaseReg ( ) const { return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s>
bool
AArch64InstrInfo
::
isFPRCopy
(
const
MachineInstr
*
MI
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
TargetOpcode
::
COPY
:
{
unsigned
DstReg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
return
(
AArch64
::
FPR64RegClass
.
contains
(
DstReg
)
||
AArch64
::
FPR128RegClass
.
contains
(
DstReg
)
)
;
}
case
AArch64
::
ORRv16i8
:
if
(
MI
->
getOperand
(
1
)
.
getReg
(
)
==
MI
->
getOperand
(
2
)
.
getReg
(
)
)
{
assert
(
MI
->
getDesc
(
)
.
getNumOperands
(
)
==
3
&&
MI
->
getOperand
(
0
)
.
isReg
(
)
&&
"invalid ORRv16i8 operands"
)
;
return
true
;
}
break
;
}
return
false
;
}
</s>

Does this instruction rename an FPR without modifying bits ?


<s> int cirrus_memory_offset ( rtx op ) { if ( ! ( reload_in_progress || reload_completed ) && ( reg_mentioned_p ( frame_pointer_rtx , op ) || reg_mentioned_p ( arg_pointer_rtx , op ) || reg_mentioned_p ( virtual_incoming_args_rtx , op ) || reg_mentioned_p ( virtual_outgoing_args_rtx , op ) || reg_mentioned_p ( virtual_stack_dynamic_rtx , op ) || reg_mentioned_p ( virtual_stack_vars_rtx , op ) ) ) return 0 ; if ( GET_CODE ( op ) == MEM ) { rtx ind ; ind = XEXP ( op , 0 ) ; if ( GET_CODE ( ind ) == REG ) return 1 ; if ( GET_CODE ( ind ) == PLUS && GET_CODE ( XEXP ( ind , 0 ) ) == REG && REG_MODE_OK_FOR_BASE_P ( XEXP ( ind , 0 ) , VOIDmode ) && GET_CODE ( XEXP ( ind , 1 ) ) == CONST_INT ) return 1 ; } return 0 ; } </s>

Return nonzero if OP is a valid Cirrus memory address pattern .


"AppendingLinkage is not supported by this target!"

Emit the specified global variable to the .s file .


<s>
MachineBasicBlock
*
MSP430TargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
unsigned
Opc
=
MI
->
getOpcode
(
)
;
if
(
Opc
==
MSP430
::
Shl8
||
Opc
==
MSP430
::
Shl16
||
Opc
==
MSP430
::
Sra8
||
Opc
==
MSP430
::
Sra16
||
Opc
==
MSP430
::
Srl8
||
Opc
==
MSP430
::
Srl16
)
return
EmitShiftInstr
(
MI
,
BB
)
;
const
TargetInstrInfo
&
TII
=
*
getTargetMachine
(
)
.
getInstrInfo
(
)
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
assert
(
(
Opc
==
MSP430
::
Select16
||
Opc
==
MSP430
::
Select8
)
&&
"Unexpected instr type to insert"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
I
=
BB
;
++
I
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
copy1MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
F
->
insert
(
I
,
copy0MBB
)
;
F
->
insert
(
I
,
copy1MBB
)
;
copy1MBB
->
splice
(
copy1MBB
->
begin
(
)
,
BB
,
llvm
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
BB
->
end
(
)
)
;
copy1MBB
->
transferSuccessorsAndUpdatePHIs
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
copy1MBB
)
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
MSP430
::
JCC
)
)
.
addMBB
(
copy1MBB
)
.
addImm
(
MI
->
getOperand
(
3
)
.
getImm
(
)
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
copy1MBB
)
;
BB
=
copy1MBB
;
BuildMI
(
*
BB
,
BB
->
begin
(
)
,
dl
,
TII
.
get
(
MSP430
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
MI
->
eraseFromParent
(
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static void riscv_conditional_register_usage ( void ) { if ( ! TARGET_HARD_FLOAT ) { for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) fixed_regs [ regno ] = call_used_regs [ regno ] = 1 ; } } </s>


<s> bool MipsPassConfig :: addInstSelector ( ) { addPass ( createMipsModuleISelDagPass ( getMipsTargetMachine ( ) ) ) ; addPass ( createMips16ISelDag ( getMipsTargetMachine ( ) , getOptLevel ( ) ) ) ; addPass ( createMipsSEISelDag ( getMipsTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> unsigned M68kRegisterInfo :: getMatchingMegaReg ( unsigned Reg , const TargetRegisterClass * RC ) const { for ( MCSuperRegIterator Super ( Reg , this ) ; Super . isValid ( ) ; ++ Super ) if ( RC -> contains ( * Super ) ) return * Super ; return 0 ; } </s>

Return a mega-register of the specified register Reg so its sub-register of index SubIdx is Reg , its super ( or mega ) Reg .


<s> static bool frv_function_ok_for_sibcall ( tree decl ATTRIBUTE_UNUSED , tree exp ATTRIBUTE_UNUSED ) { return true ; } </s>

Any function call that satisfies the machine-independent requirements is eligible on FR-V .


<s> static enum reg_class rs6000_secondary_reload_class ( enum reg_class rclass , machine_mode mode , rtx in ) { int regno ; if ( TARGET_ELF || ( DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT ) ) { if ( rclass != BASE_REGS && ( GET_CODE ( in ) == SYMBOL_REF || GET_CODE ( in ) == HIGH || GET_CODE ( in ) == LABEL_REF || GET_CODE ( in ) == CONST ) ) return BASE_REGS ; } if ( GET_CODE ( in ) == REG ) { regno = REGNO ( in ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) { regno = true_regnum ( in ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) regno = - 1 ; } } else if ( GET_CODE ( in ) == SUBREG ) { regno = true_regnum ( in ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) regno = - 1 ; } else regno = - 1 ; if ( TARGET_VSX && GET_MODE_SIZE ( mode ) < 16 && ( ( ( rclass == GENERAL_REGS || rclass == BASE_REGS ) && ( regno >= 0 && ALTIVEC_REGNO_P ( regno ) ) ) || ( ( rclass == VSX_REGS || rclass == ALTIVEC_REGS ) && ( regno >= 0 && INT_REGNO_P ( regno ) ) ) ) ) return FLOAT_REGS ; if ( rclass == GENERAL_REGS || rclass == BASE_REGS || ( regno >= 0 && INT_REGNO_P ( regno ) ) ) return NO_REGS ; if ( rclass == VSX_REGS && ( regno == - 1 || VSX_REGNO_P ( regno ) ) ) return NO_REGS ; if ( ( regno == - 1 || FP_REGNO_P ( regno ) ) && ( rclass == FLOAT_REGS || rclass == NON_SPECIAL_REGS ) ) return ( mode != SDmode || lra_in_progress ) ? NO_REGS : GENERAL_REGS ; if ( ( regno == - 1 || ALTIVEC_REGNO_P ( regno ) ) && rclass == ALTIVEC_REGS ) return NO_REGS ; if ( ( rclass == CR_REGS || rclass == CR0_REGS ) && regno >= 0 && CR_REGNO_P ( regno ) ) return NO_REGS ; return GENERAL_REGS ; } </s>

Return the register class of a scratch register needed to copy IN into or out of a register in RCLASS in MODE . If it can be done directly , NO_REGS is returned .


<s> void CSKYAsmPrinter :: emitStartOfAsmFile ( Module & M ) { if ( TM . getTargetTriple ( ) . isOSBinFormatELF ( ) ) emitAttributes ( ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the start of their file .


<s> int PPCTTIImpl :: getIntImmCost ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) { if ( DisablePPCConstHoist ) return BaseT :: getIntImmCost ( Opcode , Idx , Imm , Ty ) ; assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return ~ 0U ; unsigned ImmIdx = ~ 0U ; bool ShiftedFree = false , RunFree = false , UnsignedFree = false , ZeroFree = false ; switch ( Opcode ) { default : return TTI :: TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: And : RunFree = true ; LLVM_FALLTHROUGH ; case Instruction :: Add : case Instruction :: Or : case Instruction :: Xor : ShiftedFree = true ; LLVM_FALLTHROUGH ; case Instruction :: Sub : case Instruction :: Mul : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : ImmIdx = 1 ; break ; case Instruction :: ICmp : UnsignedFree = true ; ImmIdx = 1 ; LLVM_FALLTHROUGH ; case Instruction :: Select : ZeroFree = true ; break ; case Instruction :: PHI : case Instruction :: Call : case Instruction :: Ret : case Instruction :: Load : case Instruction :: Store : break ; } if ( ZeroFree && Imm == 0 ) return TTI :: TCC_Free ; if ( Idx == ImmIdx && Imm . getBitWidth ( ) <= 64 ) { if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; if ( RunFree ) { if ( Imm . getBitWidth ( ) <= 32 && ( isShiftedMask_32 ( Imm . getZExtValue ( ) ) || isShiftedMask_32 ( ~ Imm . getZExtValue ( ) ) ) ) return TTI :: TCC_Free ; if ( ST -> isPPC64 ( ) && ( isShiftedMask_64 ( Imm . getZExtValue ( ) ) || isShiftedMask_64 ( ~ Imm . getZExtValue ( ) ) ) ) return TTI :: TCC_Free ; } if ( UnsignedFree && isUInt < 16 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( ShiftedFree && ( Imm . getZExtValue ( ) & 0xFFFF ) == 0 ) return TTI :: TCC_Free ; } return PPCTTIImpl :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> bool PTXTargetMachine :: addPostRegAlloc ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { return false ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s>
StringRef
getPassName
(
)
const
override
{
return
"AArch64 Stack Tagging"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool PPCSubtarget :: enableMachineScheduler ( ) const { return needsAggressiveScheduling ( DarwinDirective ) ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


<s> static bool sh1_builtin_p ( void ) { return TARGET_SH1 ; } </s>

This function can be used if there are any built-ins that are not for SHmedia . It 's commented out to avoid the defined-but-unused warning .


<s> std :: pair < unsigned , const TargetRegisterClass * > ARMTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return std :: make_pair ( 0U , ARM :: tGPRRegisterClass ) ; else return std :: make_pair ( 0U , ARM :: GPRRegisterClass ) ; case 'r' : return std :: make_pair ( 0U , ARM :: GPRRegisterClass ) ; case 'w' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , ARM :: SPRRegisterClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , ARM :: DPRRegisterClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , ARM :: QPRRegisterClass ) ; break ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> void RISCVTargetLowering :: AdjustInstrPostInstrSelection ( MachineInstr & MI , SDNode * Node ) const { unsigned Opc = MI . getOpcode ( ) ; auto Idx = RISCV :: getNamedOperandIdx ( Opc , RISCV :: OpName :: frm ) ; if ( Idx < 0 ) return ; if ( MI . getOperand ( Idx ) . getImm ( ) != RISCVFPRndMode :: DYN ) return ; if ( MI . readsRegister ( RISCV :: FRM ) ) return ; MI . addOperand ( MachineOperand :: CreateReg ( RISCV :: FRM , false , true ) ) ; } </s>

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .

RISCV RISCV RISCV::getNamedOperandIdx RISCV::OpName 0 RISCVFPRndMode::DYN RISCV::FRM RISCV::FRM


<s> void MipsTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ; const MipsSubtarget & Subtarget = TM . getSubtarget < MipsSubtarget > ( ) ; if ( Subtarget . isTargetNaCl ( ) ) { StaticCtorSection = getContext ( ) . getELFSection ( ".init_array" , ELF :: SHT_INIT_ARRAY , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; StaticDtorSection = getContext ( ) . getELFSection ( ".fini_array" , ELF :: SHT_FINI_ARRAY , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; } } </s>

This method must be called before any actual lowering is done .


<s> bool mep_store_data_bypass_p ( rtx_insn * prev , rtx_insn * insn ) { return INSN_P ( insn ) ? mep_store_data_bypass_1 ( prev , PATTERN ( insn ) ) : false ; } </s>

Return true if INSN is a store instruction and if the store address has no true dependence on PREV .


<s> unsigned HexagonRegisterInfo :: getFrameRegister ( ) const { return Hexagon :: R30 ; } </s>


<s> static void rs6000_darwin64_record_arg_flush ( CUMULATIVE_ARGS * cum , HOST_WIDE_INT bitpos , rtx rvec [ ] , int * k ) { enum machine_mode mode ; unsigned int regno ; unsigned int startbit , endbit ; int this_regno , intregs , intoffset ; rtx reg ; if ( cum -> intoffset == - 1 ) return ; intoffset = cum -> intoffset ; cum -> intoffset = - 1 ; if ( intoffset % BITS_PER_WORD != 0 ) { mode = mode_for_size ( BITS_PER_WORD - intoffset % BITS_PER_WORD , MODE_INT , 0 ) ; if ( mode == BLKmode ) { intoffset = intoffset & - BITS_PER_WORD ; mode = word_mode ; } } else mode = word_mode ; startbit = intoffset & - BITS_PER_WORD ; endbit = ( bitpos + BITS_PER_WORD - 1 ) & - BITS_PER_WORD ; intregs = ( endbit - startbit ) / BITS_PER_WORD ; this_regno = cum -> words + intoffset / BITS_PER_WORD ; if ( intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno ) cum -> use_stack = 1 ; intregs = MIN ( intregs , GP_ARG_NUM_REG - this_regno ) ; if ( intregs <= 0 ) return ; intoffset /= BITS_PER_UNIT ; do { regno = GP_ARG_MIN_REG + this_regno ; reg = gen_rtx_REG ( mode , regno ) ; rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( intoffset ) ) ; this_regno += 1 ; intoffset = ( intoffset | ( UNITS_PER_WORD - 1 ) ) + 1 ; mode = word_mode ; intregs -= 1 ; } while ( intregs > 0 ) ; } </s>

A subroutine of rs6000_darwin64_record_arg . Assign the bits of the structure between cum- > intoffset and bitpos to integer registers .


"Splitting double registers in function: "

"Register partitioning: (partition #0 is fixed)\n"

runOnMachineFunction - Emit the function body .


<s> void KudeyarInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << markup ( "<reg:" ) << getRegisterName ( RegNo ) << markup ( ">" ) ; } </s>


<s> static void expand_epilogue_reg_restore ( rtx spreg , bool saveall , bool is_inthandler ) { int ndregs = saveall ? 8 : n_dregs_to_save ( is_inthandler ) ; int npregs = saveall ? 6 : n_pregs_to_save ( is_inthandler ) ; int total = ndregs + npregs ; int i , regno ; rtx pat , insn ; if ( total == 0 ) return ; pat = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( total + 1 ) ) ; XVECEXP ( pat , 0 , 0 ) = gen_rtx_SET ( VOIDmode , spreg , gen_rtx_PLUS ( Pmode , spreg , GEN_INT ( total * 4 ) ) ) ; if ( npregs > 0 ) regno = REG_P5 + 1 ; else regno = REG_R7 + 1 ; for ( i = 0 ; i < total ; i ++ ) { rtx addr = ( i > 0 ? gen_rtx_PLUS ( Pmode , spreg , GEN_INT ( i * 4 ) ) : spreg ) ; rtx memref = gen_rtx_MEM ( word_mode , addr ) ; regno -- ; XVECEXP ( pat , 0 , i + 1 ) = gen_rtx_SET ( VOIDmode , gen_rtx_REG ( word_mode , regno ) , memref ) ; if ( npregs > 0 ) { if ( -- npregs == 0 ) regno = REG_R7 + 1 ; } } insn = emit_insn ( pat ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Emit code to restore registers in the epilogue . SAVEALL is nonzero if we must save all registers ; this is used for interrupt handlers . SPREG contains ( reg : SI REG_SP ) . IS_INTHANDLER is true if we 're doing this for an interrupt ( or exception ) handler .


<s> static unsigned getFramePointerSaveOffset ( bool isPPC64 , bool isDarwinABI ) { if ( isDarwinABI ) return isPPC64 ? 40 : 20 ; return - 4U ; } </s>

getFramePointerSaveOffset - Return the previous frame offset to save the frame pointer .


<s> bool OptimizePICCall :: runOnMachineFunction ( MachineFunction & F ) { if ( static_cast < const MipsSubtarget & > ( F . getSubtarget ( ) ) . inMips16Mode ( ) ) return false ; MachineDominatorTree * MDT = & getAnalysis < MachineDominatorTree > ( ) ; bool Changed = false ; SmallVector < MBBInfo , 8 > WorkList ( 1 , MBBInfo ( MDT -> getRootNode ( ) ) ) ; while ( ! WorkList . empty ( ) ) { MBBInfo & MBBI = WorkList . back ( ) ; if ( MBBI . isVisited ( ) ) { MBBI . postVisit ( ) ; WorkList . pop_back ( ) ; continue ; } MBBI . preVisit ( ScopedHT ) ; Changed |= visitNode ( MBBI ) ; const MachineDomTreeNode * Node = MBBI . getNode ( ) ; const std :: vector < MachineDomTreeNode * > & Children = Node -> getChildren ( ) ; WorkList . append ( Children . begin ( ) , Children . end ( ) ) ; } return Changed ; } </s>


<s> static void spu_setup_incoming_varargs ( cumulative_args_t cum , machine_mode mode , tree type , int * pretend_size , int no_rtl ) { if ( ! no_rtl ) { rtx tmp ; int regno ; int offset ; int ncum = * get_cumulative_args ( cum ) ; spu_function_arg_advance ( pack_cumulative_args ( & ncum ) , mode , type , true ) ; offset = - STACK_POINTER_OFFSET ; for ( regno = ncum ; regno < MAX_REGISTER_ARGS ; regno ++ ) { tmp = gen_frame_mem ( V4SImode , plus_constant ( Pmode , virtual_incoming_args_rtx , offset ) ) ; emit_move_insn ( tmp , gen_rtx_REG ( V4SImode , FIRST_ARG_REGNUM + regno ) ) ; offset += 16 ; } * pretend_size = offset + STACK_POINTER_OFFSET ; } } </s>

Save parameter registers starting with the register that corresponds to the first unnamed parameters . If the first unnamed parameter is in the stack then save no registers . Set pretend_args_size to the amount of space needed to save the registers .


"/* Automatically generated by the program '%s'\n"

"   from the files '%s' and '%s'.  */\n\n"

Write a comment at the top of FILE about how the code was generated .

"   from the files '%s' and '%s'.  */\n\n"


"Missing call preserved mask for calling convention"

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


"only uninitialized variables can be placed in a "

Some Xtensa targets support multiple bss sections . If the section name ends with `` .bss '' , add SECTION_BSS to the flags .


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const X86Subtarget & Subtarget = MF . getSubtarget < X86Subtarget > ( ) ; bool HasSSE = Subtarget . hasSSE1 ( ) ; bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return CSR_64_TLS_Darwin_RegMask ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: X86_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_RegMask : CSR_Win64_RegCall_NoSSE_RegMask ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_RegMask : CSR_SysV64_RegCall_NoSSE_RegMask ) ; } } else { return ( HasSSE ? CSR_32_RegCall_RegMask : CSR_32_RegCall_NoSSE_RegMask ) ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: Win64 : return CSR_Win64_RegMask ; case CallingConv :: X86_64_SysV : return CSR_64_RegMask ; case CallingConv :: X86_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_64_AllRegs_RegMask ; return CSR_64_AllRegs_NoSSE_RegMask ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_32_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_32_AllRegs_SSE_RegMask ; return CSR_32_AllRegs_RegMask ; } default : break ; } if ( Is64Bit ) { const Function * F = MF . getFunction ( ) ; bool IsSwiftCC = Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && F -> getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ; if ( IsSwiftCC ) return IsWin64 ? CSR_Win64_SwiftError_RegMask : CSR_64_SwiftError_RegMask ; return IsWin64 ? CSR_Win64_RegMask : CSR_64_RegMask ; } return CSR_32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


"instruction requires a CPU feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> static bool rs6000_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE ( mode ) ) return true ; if ( TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) return true ; else if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) && ! FLOAT128_IEEE_P ( mode ) ) return true ; else return false ; } </s>

Target hook for vector_mode_supported_p .


<s>
bool
VLIWResourceModel
::
reserveResources
(
SUnit
*
SU
)
{
bool
startNewCycle
=
false
;
if
(
!
SU
)
{
ResourcesModel
->
clearResources
(
)
;
savePacket
(
)
;
Packet
.
clear
(
)
;
TotalPackets
++
;
return
false
;
}
if
(
!
isResourceAvailable
(
SU
)
)
{
ResourcesModel
->
clearResources
(
)
;
savePacket
(
)
;
Packet
.
clear
(
)
;
TotalPackets
++
;
startNewCycle
=
true
;
}
switch
(
SU
->
getInstr
(
)
->
getOpcode
(
)
)
{
default
:
ResourcesModel
->
reserveResources
(
*
SU
->
getInstr
(
)
)
;
break
;
case
TargetOpcode
::
EXTRACT_SUBREG
:
case
TargetOpcode
::
INSERT_SUBREG
:
case
TargetOpcode
::
SUBREG_TO_REG
:
case
TargetOpcode
::
REG_SEQUENCE
:
case
TargetOpcode
::
IMPLICIT_DEF
:
case
TargetOpcode
::
KILL
:
case
TargetOpcode
::
CFI_INSTRUCTION
:
case
TargetOpcode
::
EH_LABEL
:
case
TargetOpcode
::
COPY
:
case
TargetOpcode
::
INLINEASM
:
break
;
}
Packet
.
push_back
(
SU
)
;
DEBUG
(
dbgs
(
)
<<
"Packet["
<<
TotalPackets
<<
"]:\n"
)
;
for
(
unsigned
i
=
0
,
e
=
Packet
.
size
(
)
;
i
!=
e
;
++
i
)
{
DEBUG
(
dbgs
(
)
<<
"\t["
<<
i
<<
"] SU("
)
;
DEBUG
(
dbgs
(
)
<<
Packet
[
i
]
->
NodeNum
<<
")\t"
)
;
DEBUG
(
Packet
[
i
]
->
getInstr
(
)
->
dump
(
)
)
;
}
if
(
Packet
.
size
(
)
>=
SchedModel
->
getIssueWidth
(
)
)
{
ResourcesModel
->
clearResources
(
)
;
savePacket
(
)
;
Packet
.
clear
(
)
;
TotalPackets
++
;
startNewCycle
=
true
;
}
return
startNewCycle
;
}
</s>


<s> MCDisassembler :: DecodeStatus X86GenericDisassembler :: getInstruction ( MCInst & instr , uint64_t & size , const MemoryObject & region , uint64_t address , raw_ostream & vStream , raw_ostream & cStream ) const { CommentStream = & cStream ; InternalInstruction internalInstr ; dlog_t loggerFn = logger ; if ( & vStream == & nulls ( ) ) loggerFn = nullptr ; int ret = decodeInstruction ( & internalInstr , regionReader , ( const void * ) & region , loggerFn , ( void * ) & vStream , ( const void * ) MII . get ( ) , address , fMode ) ; if ( ret ) { size = internalInstr . readerCursor - address ; return Fail ; } else { size = internalInstr . length ; return ( ! translateInstruction ( instr , internalInstr , this ) ) ? Success : Fail ; } } </s>

Returns the disassembly of a single instruction .


<s> bool XCoreAsmPrinter :: doFinalization ( Module & M ) { for ( Module :: const_global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ; I != E ; ++ I ) { emitGlobal ( I ) ; } DW -> EndModule ( ) ; return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> bool AMDGPUIntrinsicInfo :: isOverloaded ( unsigned id ) const { } </s>

Returns true if the intrinsic can be overloaded .


<s> void Thumb2InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { if ( ! ARM :: GPRRegClass . contains ( DestReg , SrcReg ) ) return ARMBaseInstrInfo :: copyPhysReg ( MBB , I , DL , DestReg , SrcReg , KillSrc ) ; bool tDest = ARM :: tGPRRegClass . contains ( DestReg ) ; bool tSrc = ARM :: tGPRRegClass . contains ( SrcReg ) ; unsigned Opc = ARM :: tMOVgpr2gpr ; if ( tDest && tSrc ) Opc = ARM :: tMOVr ; else if ( tSrc ) Opc = ARM :: tMOVtgpr2gpr ; else if ( tDest ) Opc = ARM :: tMOVgpr2tgpr ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } </s>

ARM ARM::GPRRegClass ARM ARM::tGPRRegClass ARM::tGPRRegClass ARM::tMOVgpr2gpr ARM::tMOVr ARM::tMOVtgpr2gpr ARM::tMOVgpr2tgpr


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addRequiredID ( LoopSimplifyID ) ; AU . addRequiredID ( LCSSAID ) ; AU . addPreservedID ( LCSSAID ) ; AU . setPreservesCFG ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


"Stack frame larger than 2G is not supported for -fsplit-stack"

Emit -fsplit-stack prologue , which goes before the regular function prologue ( at local entry point in the case of ELFv2 ) .


<s> bool PPCTargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> static unsigned int parse_count ( const function_instance & instance , const char * & format ) { if ( format [ 0 ] == '*' && format [ 1 ] == 'q' ) { format += 2 ; return instance . elements_per_vq ( 0 ) ; } if ( format [ 0 ] == '*' && format [ 1 ] == 't' ) { format += 2 ; return instance . vectors_per_tuple ( ) ; } return 1 ; } </s>

Read and move past any argument count at FORMAT for the function signature of INSTANCE . The counts are : * q : one argument per element in a 128-bit quadword ( as for svdupq ) * t : one argument per vector in a tuple ( as for svcreate ) Otherwise the count is 1 .


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> unsigned PPCFastISel :: fastEmit_i ( MVT Ty , MVT VT , unsigned Opc , uint64_t Imm ) { if ( Opc != ISD :: Constant ) return 0 ; if ( VT == MVT :: i1 && Subtarget -> useCRBits ( ) ) { Register ImmReg = createResultReg ( & PPC :: CRBITRCRegClass ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Imm == 0 ? PPC :: CRUNSET : PPC :: CRSET ) , ImmReg ) ; return ImmReg ; } if ( VT != MVT :: i64 && VT != MVT :: i32 && VT != MVT :: i16 && VT != MVT :: i8 && VT != MVT :: i1 ) return 0 ; const TargetRegisterClass * RC = ( ( VT == MVT :: i64 ) ? & PPC :: G8RCRegClass : & PPC :: GPRCRegClass ) ; if ( VT == MVT :: i64 ) return PPCMaterialize64BitInt ( Imm , RC ) ; else return PPCMaterialize32BitInt ( Imm , RC ) ; } </s>

This method is called by target-independent code to request that an instruction with the given type , opcode , and immediate operand be emitted .


<s> virtual const SPUFrameInfo * getFrameInfo ( ) const { return & FrameInfo ; } </s>

getFrameInfo - Return the frame info object for the current function .


"you cannot take the address of a nested function if you use "

Emit RTL insns to initialize the variable parts of a trampoline . FNADDR is an RTX for the address of the function 's pure code . CXT is an RTX for the static chain value for the function .


<s> static int msp430_shift_costs ( rtx src , rtx dst , bool speed , rtx outer_rtx ) { int amt ; enum rtx_code src_code = GET_CODE ( src ) ; enum rtx_code dst_code = GET_CODE ( dst ) ; const struct single_op_cost * cost_p ; cost_p = ( speed ? & cycle_cost_single_op : & size_cost_single_op ) ; if ( src_code != CONST_INT ) return 2 * msp430_costs ( src , dst , speed , outer_rtx ) ; if ( use_helper_for_const_shift ( GET_MODE ( outer_rtx ) , amt = INTVAL ( src ) ) ) { return msp430_costs ( src , dst , speed , outer_rtx ) ; } if ( ! msp430x ) { switch ( dst_code ) { case REG : case CONST_INT : return amt * cost_p -> reg ; case MEM : if ( msp430_is_mem_indirect ( dst ) ) return amt * cost_p -> ind ; else return amt * cost_p -> mem ; default : return amt * cost_p -> mem ; } } return ( amt <= 4 ? ( speed ? amt : 1 ) : ( speed ? amt + 1 : 2 ) + ( dst_code == REG ? 0 : msp430_costs ( dst , gen_rtx_REG ( HImode , 10 ) , speed , outer_rtx ) ) ) ; } </s>

Given source operand SRC and destination operand DST from the shift or rotate RTX OUTER_RTX , return the cost of performing that shift , assuming optimization for speed when SPEED is true .


<s> MSP430Subtarget & MSP430Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { StringRef CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "msp430" ; ParseSubtargetFeatures ( CPUName , CPUName , FS ) ; if ( HWMultModeOption != NoHWMult ) HWMultMode = HWMultModeOption ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool mayNeedRelaxation ( const MCInst & ) const override { return false ; } </s>


<s> void R600TTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP , OptimizationRemarkEmitter * ORE ) { CommonTTI . getUnrollingPreferences ( L , SE , UP , ORE ) ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s>
StringRef
CAHPMCExpr
::
getVariantKindName
(
VariantKind
Kind
)
{
switch
(
Kind
)
{
default
:
llvm_unreachable
(
"Invalid ELF symbol kind"
)
;
case
VK_CAHP_LO
:
return
"lo"
;
case
VK_CAHP_HI
:
return
"hi"
;
}
}
</s>

Convert the variant kind into an ELF-appropriate modifier ( e.g .

CAHP
CAHP
"Invalid ELF symbol kind"
CAHP
"lo"
CAHP
"hi"


<s> bool M68kFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { auto & MRI = * static_cast < const M68kRegisterInfo * > ( TRI ) ; auto DL = MBB . findDebugLoc ( MI ) ; int FI = 0 ; unsigned Mask = 0 ; for ( const auto & Info : CSI ) { FI = std :: max ( FI , Info . getFrameIdx ( ) ) ; unsigned Reg = Info . getReg ( ) ; unsigned Shift = MRI . getSpillRegisterOrder ( Reg ) ; Mask |= 1 << Shift ; } auto I = M68k :: addFrameReference ( BuildMI ( MBB , MI , DL , TII . get ( M68k :: MOVM32pm ) ) , FI ) . addImm ( Mask ) . setMIFlag ( MachineInstr :: FrameSetup ) ; const MachineFunction & MF = * MBB . getParent ( ) ; const MachineRegisterInfo & RI = MF . getRegInfo ( ) ; for ( const auto & Info : CSI ) { unsigned Reg = Info . getReg ( ) ; bool IsLiveIn = RI . isLiveIn ( Reg ) ; if ( ! IsLiveIn ) MBB . addLiveIn ( Reg ) ; I . addReg ( Reg , IsLiveIn ? RegState :: Implicit : RegState :: ImplicitKill ) ; M68k :: addMemOperand ( I , Info . getFrameIdx ( ) , 0 ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const PPCFrameLowering * PPCFI = static_cast < const PPCFrameLowering * > ( Subtarget . getFrameLowering ( ) ) ; Reserved . set ( PPC :: ZERO ) ; Reserved . set ( PPC :: ZERO8 ) ; Reserved . set ( PPC :: FP ) ; Reserved . set ( PPC :: FP8 ) ; Reserved . set ( PPC :: BP ) ; Reserved . set ( PPC :: BP8 ) ; Reserved . set ( PPC :: CTR ) ; Reserved . set ( PPC :: CTR8 ) ; Reserved . set ( PPC :: R1 ) ; Reserved . set ( PPC :: LR ) ; Reserved . set ( PPC :: LR8 ) ; Reserved . set ( PPC :: RM ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) Reserved . set ( PPC :: VRSAVE ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: R2 ) ; Reserved . set ( PPC :: R13 ) ; } if ( Subtarget . isPPC64 ( ) ) { Reserved . set ( PPC :: R13 ) ; Reserved . set ( PPC :: X1 ) ; Reserved . set ( PPC :: X13 ) ; if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: X31 ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( PPC :: X30 ) ; if ( Subtarget . isSVR4ABI ( ) ) { const PPCFunctionInfo * FuncInfo = MF . getInfo < PPCFunctionInfo > ( ) ; if ( FuncInfo -> usesTOCBasePtr ( ) || MF . hasInlineAsm ( ) ) Reserved . set ( PPC :: X2 ) ; else Reserved . reset ( PPC :: R2 ) ; } } if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: R31 ) ; if ( hasBasePointer ( MF ) ) { if ( Subtarget . isSVR4ABI ( ) && ! Subtarget . isPPC64 ( ) && MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) Reserved . set ( PPC :: R29 ) ; else Reserved . set ( PPC :: R30 ) ; } if ( Subtarget . isSVR4ABI ( ) && ! Subtarget . isPPC64 ( ) && MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) Reserved . set ( PPC :: R30 ) ; if ( ! Subtarget . hasAltivec ( ) ) for ( TargetRegisterClass :: iterator I = PPC :: VRRCRegClass . begin ( ) , IE = PPC :: VRRCRegClass . end ( ) ; I != IE ; ++ I ) Reserved . set ( * I ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


"Basic block should contain at least a RET but is empty"

runOnMachineFunction - Emit the function body .


"getBranchTargetOpValueMM expects only expressions or immediates"

getBranchTargetOpValue - Return binary encoding of the microMIPS branch target operand .


<s> const char * avr_out_compare64 ( rtx_insn * insn , rtx * op , int * plen ) { rtx xop [ 3 ] ; xop [ 0 ] = gen_rtx_REG ( DImode , 18 ) ; xop [ 1 ] = op [ 0 ] ; xop [ 2 ] = op [ 1 ] ; return avr_out_compare ( insn , xop , plen ) ; } </s>

Prepare operands of compare_const_di2 to be used with avr_out_compare .


<s> unsigned X86TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT == MVT :: v32i1 && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return 1 ; if ( VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i1 && Subtarget . hasAVX512 ( ) && ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) || ( VT . getVectorNumElements ( ) > 16 && ! Subtarget . hasBWI ( ) ) || ( VT . getVectorNumElements ( ) > 64 && Subtarget . hasBWI ( ) ) ) ) return VT . getVectorNumElements ( ) ; if ( ( VT == MVT :: v32i16 || VT == MVT :: v64i8 ) && ! EnableOldKNLABI && Subtarget . useAVX512Regs ( ) && ! Subtarget . hasBWI ( ) ) return 1 ; return TargetLowering :: getNumRegistersForCallingConv ( Context , CC , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s>
MachineInstr
*
PPCInstrInfo
::
commuteInstruction
(
MachineInstr
*
MI
,
bool
NewMI
)
const
{
MachineFunction
&
MF
=
*
MI
->
getParent
(
)
->
getParent
(
)
;
if
(
MI
->
getOpcode
(
)
!=
PPC
::
RLWIMI
)
return
TargetInstrInfoImpl
::
commuteInstruction
(
MI
,
NewMI
)
;
if
(
MI
->
getOperand
(
3
)
.
getImm
(
)
!=
0
)
return
0
;
unsigned
Reg0
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
unsigned
Reg1
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
unsigned
Reg2
=
MI
->
getOperand
(
2
)
.
getReg
(
)
;
bool
Reg1IsKill
=
MI
->
getOperand
(
1
)
.
isKill
(
)
;
bool
Reg2IsKill
=
MI
->
getOperand
(
2
)
.
isKill
(
)
;
bool
ChangeReg0
=
false
;
if
(
Reg0
==
Reg1
)
{
assert
(
MI
->
getDesc
(
)
.
getOperandConstraint
(
0
,
TOI
::
TIED_TO
)
&&
"Expecting a two-address instruction!"
)
;
Reg2IsKill
=
false
;
ChangeReg0
=
true
;
}
unsigned
MB
=
MI
->
getOperand
(
4
)
.
getImm
(
)
;
unsigned
ME
=
MI
->
getOperand
(
5
)
.
getImm
(
)
;
if
(
NewMI
)
{
unsigned
Reg0
=
ChangeReg0
Reg2
:
MI
->
getOperand
(
0
)
.
getReg
(
)
;
bool
Reg0IsDead
=
MI
->
getOperand
(
0
)
.
isDead
(
)
;
return
BuildMI
(
MF
,
MI
->
getDebugLoc
(
)
,
MI
->
getDesc
(
)
)
.
addReg
(
Reg0
,
true
,
false
,
false
,
Reg0IsDead
)
.
addReg
(
Reg2
,
false
,
false
,
Reg2IsKill
)
.
addReg
(
Reg1
,
false
,
false
,
Reg1IsKill
)
.
addImm
(
(
ME
+
1
)
&
31
)
.
addImm
(
(
MB
1
)
&
31
)
;
}
if
(
ChangeReg0
)
MI
->
getOperand
(
0
)
.
setReg
(
Reg2
)
;
MI
->
getOperand
(
2
)
.
setReg
(
Reg1
)
;
MI
->
getOperand
(
1
)
.
setReg
(
Reg2
)
;
MI
->
getOperand
(
2
)
.
setIsKill
(
Reg1IsKill
)
;
MI
->
getOperand
(
1
)
.
setIsKill
(
Reg2IsKill
)
;
MI
->
getOperand
(
4
)
.
setImm
(
(
ME
+
1
)
&
31
)
;
MI
->
getOperand
(
5
)
.
setImm
(
(
MB
1
)
&
31
)
;
return
MI
;
}
</s>

This method commutes the operands of the given machine instruction MI .


<s>
bool
shouldForceRelocation
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
)
override
{
MCFixupKind
Kind
=
Fixup
.
getKind
(
)
;
switch
(
(
unsigned
)
Kind
)
{
default
:
llvm_unreachable
(
"Unknown Fixup Kind!"
)
;
case
fixup_Hexagon_LO16
:
case
fixup_Hexagon_HI16
:
case
fixup_Hexagon_16
:
case
fixup_Hexagon_8
:
case
fixup_Hexagon_GPREL16_0
:
case
fixup_Hexagon_GPREL16_1
:
case
fixup_Hexagon_GPREL16_2
:
case
fixup_Hexagon_GPREL16_3
:
case
fixup_Hexagon_HL16
:
case
fixup_Hexagon_32_6_X
:
case
fixup_Hexagon_16_X
:
case
fixup_Hexagon_12_X
:
case
fixup_Hexagon_11_X
:
case
fixup_Hexagon_10_X
:
case
fixup_Hexagon_9_X
:
case
fixup_Hexagon_8_X
:
case
fixup_Hexagon_7_X
:
case
fixup_Hexagon_6_X
:
case
fixup_Hexagon_COPY
:
case
fixup_Hexagon_GLOB_DAT
:
case
fixup_Hexagon_JMP_SLOT
:
case
fixup_Hexagon_RELATIVE
:
case
fixup_Hexagon_PLT_B22_PCREL
:
case
fixup_Hexagon_GOTREL_LO16
:
case
fixup_Hexagon_GOTREL_HI16
:
case
fixup_Hexagon_GOTREL_32
:
case
fixup_Hexagon_GOT_LO16
:
case
fixup_Hexagon_GOT_HI16
:
case
fixup_Hexagon_GOT_32
:
case
fixup_Hexagon_GOT_16
:
case
fixup_Hexagon_DTPMOD_32
:
case
fixup_Hexagon_DTPREL_LO16
:
case
fixup_Hexagon_DTPREL_HI16
:
case
fixup_Hexagon_DTPREL_32
:
case
fixup_Hexagon_DTPREL_16
:
case
fixup_Hexagon_GD_PLT_B22_PCREL
:
case
fixup_Hexagon_LD_PLT_B22_PCREL
:
case
fixup_Hexagon_GD_GOT_LO16
:
case
fixup_Hexagon_GD_GOT_HI16
:
case
fixup_Hexagon_GD_GOT_32
:
case
fixup_Hexagon_GD_GOT_16
:
case
fixup_Hexagon_LD_GOT_LO16
:
case
fixup_Hexagon_LD_GOT_HI16
:
case
fixup_Hexagon_LD_GOT_32
:
case
fixup_Hexagon_LD_GOT_16
:
case
fixup_Hexagon_IE_LO16
:
case
fixup_Hexagon_IE_HI16
:
case
fixup_Hexagon_IE_32
:
case
fixup_Hexagon_IE_16
:
case
fixup_Hexagon_IE_GOT_LO16
:
case
fixup_Hexagon_IE_GOT_HI16
:
case
fixup_Hexagon_IE_GOT_32
:
case
fixup_Hexagon_IE_GOT_16
:
case
fixup_Hexagon_TPREL_LO16
:
case
fixup_Hexagon_TPREL_HI16
:
case
fixup_Hexagon_TPREL_32
:
case
fixup_Hexagon_TPREL_16
:
case
fixup_Hexagon_GOTREL_32_6_X
:
case
fixup_Hexagon_GOTREL_16_X
:
case
fixup_Hexagon_GOTREL_11_X
:
case
fixup_Hexagon_GOT_32_6_X
:
case
fixup_Hexagon_GOT_16_X
:
case
fixup_Hexagon_GOT_11_X
:
case
fixup_Hexagon_DTPREL_32_6_X
:
case
fixup_Hexagon_DTPREL_16_X
:
case
fixup_Hexagon_DTPREL_11_X
:
case
fixup_Hexagon_GD_GOT_32_6_X
:
case
fixup_Hexagon_GD_GOT_16_X
:
case
fixup_Hexagon_GD_GOT_11_X
:
case
fixup_Hexagon_LD_GOT_32_6_X
:
case
fixup_Hexagon_LD_GOT_16_X
:
case
fixup_Hexagon_LD_GOT_11_X
:
case
fixup_Hexagon_IE_32_6_X
:
case
fixup_Hexagon_IE_16_X
:
case
fixup_Hexagon_IE_GOT_32_6_X
:
case
fixup_Hexagon_IE_GOT_16_X
:
case
fixup_Hexagon_IE_GOT_11_X
:
case
fixup_Hexagon_TPREL_32_6_X
:
case
fixup_Hexagon_TPREL_16_X
:
case
fixup_Hexagon_TPREL_11_X
:
case
fixup_Hexagon_32_PCREL
:
case
fixup_Hexagon_6_PCREL_X
:
case
fixup_Hexagon_23_REG
:
case
fixup_Hexagon_27_REG
:
case
fixup_Hexagon_GD_PLT_B22_PCREL_X
:
case
fixup_Hexagon_GD_PLT_B32_PCREL_X
:
case
fixup_Hexagon_LD_PLT_B22_PCREL_X
:
case
fixup_Hexagon_LD_PLT_B32_PCREL_X
:
return
true
;
case
fixup_Hexagon_B22_PCREL
:
break
;
case
fixup_Hexagon_B13_PCREL
:
case
fixup_Hexagon_B13_PCREL_X
:
case
fixup_Hexagon_B32_PCREL_X
:
case
fixup_Hexagon_B22_PCREL_X
:
case
fixup_Hexagon_B15_PCREL
:
case
fixup_Hexagon_B15_PCREL_X
:
case
fixup_Hexagon_B9_PCREL
:
case
fixup_Hexagon_B9_PCREL_X
:
case
fixup_Hexagon_B7_PCREL
:
case
fixup_Hexagon_B7_PCREL_X
:
if
(
DisableFixup
)
return
true
;
break
;
case
FK_Data_1
:
case
FK_Data_2
:
case
FK_Data_4
:
case
FK_PCRel_4
:
case
fixup_Hexagon_32
:
return
false
;
}
return
false
;
}
</s>

Hook to check if a relocation is needed for some target specific reason .

Hexagon
"Unknown Fixup Kind!"
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon


"call to %qE is ambiguous; argument %d has type"

Argument FIRST_ARGNO is a scalar with type EXPECTED_TYPE , and argument ARGNO should be consistent with it . Return true if it is , otherwise report an appropriate error .


"Not all fixup kinds added to Infos array"


<s> bool LanaiTargetObjectFile :: isGlobalInSmallSection ( const GlobalObject * GO , const TargetMachine & TM , SectionKind Kind ) const { return isGlobalInSmallSectionImpl ( GO , TM ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> bool SITypeRewriter :: doInitialization ( Module & M ) { Mod = & M ; v16i8 = VectorType :: get ( Type :: getInt8Ty ( M . getContext ( ) ) , 16 ) ; i128 = Type :: getIntNTy ( M . getContext ( ) , 128 ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> WebAssemblyTargetMachine :: WebAssemblyTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , TT . isArch64Bit ( ) ? "e-m:e-p:64:64-i64:64-n32:64-S128" : "e-m:e-p:32:32-i64:64-n32:64-S128" , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffectiveCodeModel ( CM , CodeModel :: Large ) , OL ) , TLOF ( new WebAssemblyTargetObjectFile ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . FunctionSections = true ; this -> Options . DataSections = true ; this -> Options . UniqueSectionNames = true ; initAsmInfo ( ) ; } </s>

Create an WebAssembly architecture model .

WebAssembly WebAssembly WebAssembly "e-m:e-p:64:64-i64:64-n32:64-S128" "e-m:e-p:32:32-i64:64-n32:64-S128" WebAssembly


<s> bool easy_altivec_constant ( rtx op , machine_mode mode ) { unsigned step , copies ; if ( mode == VOIDmode ) mode = GET_MODE ( op ) ; else if ( mode != GET_MODE ( op ) ) return false ; if ( mode == V2DFmode ) return zero_constant ( op , mode ) ; else if ( mode == V2DImode ) { if ( GET_CODE ( CONST_VECTOR_ELT ( op , 0 ) ) != CONST_INT || GET_CODE ( CONST_VECTOR_ELT ( op , 1 ) ) != CONST_INT ) return false ; if ( zero_constant ( op , mode ) ) return true ; if ( INTVAL ( CONST_VECTOR_ELT ( op , 0 ) ) == - 1 && INTVAL ( CONST_VECTOR_ELT ( op , 1 ) ) == - 1 ) return true ; return false ; } else if ( mode == V1TImode ) return false ; step = GET_MODE_NUNITS ( mode ) / 4 ; copies = 1 ; if ( vspltis_constant ( op , step , copies ) ) return true ; if ( step == 1 ) copies <<= 1 ; else step >>= 1 ; if ( vspltis_constant ( op , step , copies ) ) return true ; if ( step == 1 ) copies <<= 1 ; else step >>= 1 ; if ( vspltis_constant ( op , step , copies ) ) return true ; if ( vspltis_shifted ( op ) != 0 ) return true ; return false ; } </s>

Return true if OP is of the given MODE and can be synthesized with a vspltisb , vspltish or vspltisw .


<s> static int riscv_split_integer_cost ( HOST_WIDE_INT val ) { int cost ; unsigned HOST_WIDE_INT loval = sext_hwi ( val , 32 ) ; unsigned HOST_WIDE_INT hival = sext_hwi ( ( val - loval ) >> 32 , 32 ) ; struct riscv_integer_op codes [ RISCV_MAX_INTEGER_OPS ] ; cost = 2 + riscv_build_integer ( codes , loval , VOIDmode ) ; if ( loval != hival ) cost += riscv_build_integer ( codes , hival , VOIDmode ) ; return cost ; } </s>

Return the cost of constructing VAL in the event that a scratch register is available .


INSN is being issued in current solution . Account for its impact on the decoder model .


<s> void MipsRegisterInfo :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; bool isPIC = ( MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ; if ( MFI -> hasCalls ( ) && isPIC ) { MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; MFI -> setObjectOffset ( MipsFI -> getGPFI ( ) , MipsFI -> getGPStackOffset ( ) ) ; } } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> static bool riscv_verify_type_context ( location_t loc , type_context_kind context , const_tree type , bool silent_p ) { return riscv_vector :: verify_type_context ( loc , context , type , silent_p ) ; } </s>


<s> Value * X86TargetLowering :: getSafeStackPointerLocation ( IRBuilder < > & IRB ) const { if ( Subtarget . getTargetTriple ( ) . isOSContiki ( ) ) return getDefaultSafeStackPointerLocation ( IRB , false ) ; if ( Subtarget . isTargetAndroid ( ) ) { int Offset = ( Subtarget . is64Bit ( ) ) ? 0x48 : 0x24 ; return SegmentOffset ( IRB , Offset , getAddressSpace ( ) ) ; } if ( Subtarget . isTargetFuchsia ( ) ) { return SegmentOffset ( IRB , 0x18 , getAddressSpace ( ) ) ; } return TargetLowering :: getSafeStackPointerLocation ( IRB ) ; } </s>

Return true if the target stores SafeStack pointer at a fixed offset in some non-standard address space , and populates the address space and offset as appropriate .


<s> bool rs6000_overloaded_builtin_p ( enum rs6000_builtins fncode ) { return ( rs6000_builtin_info [ ( int ) fncode ] . attr & RS6000_BTC_OVERLOADED ) != 0 ; } </s>

Return true if a builtin function is overloaded .


"%qE attribute only applies to functions"

Handle an attribute requiring a FUNCTION_DECL ; arguments as in struct attribute_spec.handler .


<s> bool gen_operands_ldd_std ( rtx * operands , bool load , bool commute ) { int i , gap ; HOST_WIDE_INT offsets [ 2 ] , offset ; int nops = 2 ; rtx cur_base , cur_offset , tmp ; rtx base = NULL_RTX ; for ( i = 0 ; i < nops ; i ++ ) { if ( ! mem_ok_for_ldd_std ( operands [ nops + i ] , & cur_base , & cur_offset ) ) return false ; if ( i == 0 ) base = cur_base ; else if ( REGNO ( base ) != REGNO ( cur_base ) ) return false ; offsets [ i ] = INTVAL ( cur_offset ) ; if ( GET_CODE ( operands [ i ] ) == SUBREG ) { tmp = SUBREG_REG ( operands [ i ] ) ; gcc_assert ( GET_MODE ( operands [ i ] ) == GET_MODE ( tmp ) ) ; operands [ i ] = tmp ; } } if ( load && REGNO ( operands [ 0 ] ) == REGNO ( base ) ) return false ; if ( load && REGNO ( operands [ 0 ] ) == REGNO ( operands [ 1 ] ) ) return false ; if ( offsets [ 0 ] > offsets [ 1 ] ) { gap = offsets [ 0 ] - offsets [ 1 ] ; offset = offsets [ 1 ] ; std :: swap ( operands [ 0 ] , operands [ 1 ] ) ; std :: swap ( operands [ 2 ] , operands [ 3 ] ) ; } else { gap = offsets [ 1 ] - offsets [ 0 ] ; offset = offsets [ 0 ] ; } if ( gap != 4 ) return false ; if ( operands_ok_ldd_std ( operands [ 0 ] , operands [ 1 ] , offset ) ) return true ; if ( load && commute ) { std :: swap ( operands [ 0 ] , operands [ 1 ] ) ; if ( operands_ok_ldd_std ( operands [ 0 ] , operands [ 1 ] , offset ) ) return true ; } return false ; } </s>

Called from peephole2 to replace two word-size accesses with a single LDD/STD instruction . Returns true iff we can generate a new instruction sequence . That is , both accesses use the same base register and the gap between constant offsets is 4 . OPERANDS are the operands found by the peephole matcher ; OPERANDS [ 0,1 ] are register operands , and OPERANDS [ 2,3 ] are the corresponding memory operands . LOAD indicates whether the access is load or store .


<s>
MipsSubtarget
::
MipsSubtarget
(
const
std
::
string
&
TT
,
const
std
::
string
&
CPU
,
const
std
::
string
&
FS
,
bool
little
,
Reloc
::
Model
RM
)
:
MipsGenSubtargetInfo
(
TT
,
CPU
,
FS
)
,
MipsArchVersion
(
Mips32
)
,
MipsABI
(
UnknownABI
)
,
IsLittle
(
little
)
,
IsSingleFloat
(
false
)
,
IsFP64bit
(
false
)
,
IsGP64bit
(
false
)
,
HasVFPU
(
false
)
,
IsLinux
(
true
)
,
HasSEInReg
(
false
)
,
HasCondMov
(
false
)
,
HasMulDivAdd
(
false
)
,
HasMinMax
(
false
)
,
HasSwap
(
false
)
,
HasBitCount
(
false
)
,
HasFPIdx
(
false
)
,
InMips16Mode
(
false
)
,
HasDSP
(
false
)
,
HasDSPR2
(
false
)
,
IsAndroid
(
false
)
{
std
::
string
CPUName
=
CPU
;
if
(
CPUName
.
empty
(
)
)
CPUName
=
"mips32"
;
ParseSubtargetFeatures
(
CPUName
,
FS
)
;
InstrItins
=
getInstrItineraryForCPU
(
CPUName
)
;
if
(
MipsABI
==
UnknownABI
)
MipsABI
=
hasMips64
(
)
N64
:
O32
;
assert
(
(
(
!
hasMips64
(
)
&&
(
isABI_O32
(
)
||
isABI_EABI
(
)
)
)
||
(
hasMips64
(
)
&&
(
isABI_N32
(
)
||
isABI_N64
(
)
)
)
)
&&
"Invalid  Arch & ABI pair."
)
;
if
(
TT
.
find
(
"linux"
)
==
std
::
string
::
npos
)
IsLinux
=
false
;
UseSmallSection
=
!
IsLinux
&&
(
RM
==
Reloc
::
Static
)
;
}
</s>

This constructor initializes the data members to match that of the specified triple .

Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
"mips32"
Mips
Mips
Mips
Mips
Mips
"Invalid  Arch & ABI pair."
"linux"


<s> unsigned M680x0RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? FramePtr : StackPtr ; } </s>


<s> void GCNPassConfig :: addFastRegAlloc ( ) { insertPass ( & PHIEliminationID , & SILowerControlFlowID , false ) ; insertPass ( & SILowerControlFlowID , & SIFixWWMLivenessID , false ) ; TargetPassConfig :: addFastRegAlloc ( ) ; } </s>

addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast register allocation .


<s> bool X86TTIImpl :: isLegalMaskedLoad ( Type * DataTy ) { if ( ! ST -> hasAVX ( ) ) return false ; if ( isa < VectorType > ( DataTy ) && DataTy -> getVectorNumElements ( ) == 1 ) return false ; Type * ScalarTy = DataTy -> getScalarType ( ) ; if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == 32 || IntWidth == 64 || ( ( IntWidth == 8 || IntWidth == 16 ) && ST -> hasBWI ( ) ) ; } </s>

Return true if the target supports masked load .


"Instr doesn't have FrameIndex operand!"

"16-byte alignment violated in eliminateFrameIndex"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static void unicosmk_output_addr_vec ( FILE * file , rtx vec ) { rtx lab = XEXP ( vec , 0 ) ; rtx body = XEXP ( vec , 1 ) ; int vlen = XVECLEN ( body , 0 ) ; int idx ; ( * targetm . asm_out . internal_label ) ( file , "L" , CODE_LABEL_NUMBER ( lab ) ) ; for ( idx = 0 ; idx < vlen ; idx ++ ) { ASM_OUTPUT_ADDR_VEC_ELT ( file , CODE_LABEL_NUMBER ( XEXP ( XVECEXP ( body , 0 , idx ) , 0 ) ) ) ; } } </s>


<s> const AlphaTargetMachine & getTargetMachine ( ) { return static_cast < const AlphaTargetMachine & > ( TM ) ; } </s>

Return the target machine ( if available ) .


<s> static bool h8300_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { return ( mode1 == mode2 || ( ( mode1 == QImode || mode1 == HImode || mode1 == SImode ) && ( mode2 == QImode || mode2 == HImode || mode2 == SImode ) ) ) ; } </s>


Create and return the va_list datatype . On S/390 , va_list is an array type equivalent to typedef struct __va_list_tag { long __gpr ; long __fpr ; void * __overflow_arg_area ; void * __reg_save_area ; } va_list [ 1 ] ; where __gpr and __fpr hold the number of general purpose or floating point arguments used up to now , respectively , __overflow_arg_area points to the stack location of the next argument passed on the stack , and __reg_save_area always points to the start of the register area in the call frame of the current function . The function prologue saves all registers used for argument passing into this area if the function uses variable arguments .


"insertBranch must not be told to insert a fallthrough"

"CJG branch conditions have one component!"

"Unconditional branch with multiple successors!"

Insert branch code into the end of the specified MachineBasicBlock .