<s> MachineInstr * SIInstrInfo :: createPHIDestinationCopy ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator LastPHIIt , const DebugLoc & DL , Register Src , Register Dst ) const { auto Cur = MBB . begin ( ) ; if ( Cur != MBB . end ( ) ) do { if ( ! Cur -> isPHI ( ) && Cur -> readsRegister ( Dst ) ) return BuildMI ( MBB , Cur , DL , get ( TargetOpcode :: COPY ) , Dst ) . addReg ( Src ) ; ++ Cur ; } while ( Cur != MBB . end ( ) && Cur != LastPHIIt ) ; return TargetInstrInfo :: createPHIDestinationCopy ( MBB , LastPHIIt , DL , Src , Dst ) ; } </s>

During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destination register in a target specific manner .


<s> MachineInstrBuilder SIInstrInfo :: getAddNoCarry ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , Register DestReg , RegScavenger & RS ) const { if ( ST . hasAddNoCarry ( ) ) return BuildMI ( MBB , I , DL , get ( AMDGPU :: V_ADD_U32_e64 ) , DestReg ) ; Register UnusedCarry = RS . scavengeRegister ( RI . getBoolRC ( ) , I , 0 , false ) ; if ( ! UnusedCarry . isValid ( ) ) return MachineInstrBuilder ( ) ; return BuildMI ( MBB , I , DL , get ( AMDGPU :: V_ADD_I32_e64 ) , DestReg ) . addReg ( UnusedCarry , RegState :: Define | RegState :: Dead ) ; } </s>

Return a partially built integer add instruction without carry .


<s>
void
assignValueToAddress
(
unsigned
ValVReg
,
unsigned
Addr
,
uint64_t
Size
,
MachinePointerInfo
&
MPO
,
CCValAssign
&
VA
)
override
{
assert
(
(
Size
==
1
||
Size
==
2
||
Size
==
4
||
Size
==
8
)
&&
"Unsupported size"
)
;
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
SExt
||
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExt
)
{
Size
=
4
;
assert
(
MRI
.
getType
(
ValVReg
)
.
isScalar
(
)
&&
"Only scalars supported atm"
)
;
auto
LoadVReg
=
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
32
)
)
;
buildLoad
(
LoadVReg
,
Addr
,
Size
,
1
,
MPO
)
;
MIRBuilder
.
buildTrunc
(
ValVReg
,
LoadVReg
)
;
}
else
{
buildLoad
(
ValVReg
,
Addr
,
Size
,
1
,
MPO
)
;
}
}
</s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s>
static
bool
write_as_kernel
(
tree
attrs
)
{
return
(
lookup_attribute
(
"kernel"
,
attrs
)
!=
NULL_TREE
||
(
lookup_attribute
(
"omp target entrypoint"
,
attrs
)
!=
NULL_TREE
&&
lookup_attribute
(
"oacc function"
,
attrs
)
!=
NULL_TREE
)
)
;
}
</s>

Look for attributes in ATTRS that would indicate we must write a function as a .entry kernel rather than a .func . Return true if one is found .

nvptx
"kernel"
"omp target entrypoint"
"oacc function"


<s> void MipsSEFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MipsSEInstrInfo & TII = * static_cast < const MipsSEInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; unsigned SP = STI . isABI_N64 ( ) ? Mips :: SP_64 : Mips :: SP ; unsigned FP = STI . isABI_N64 ( ) ? Mips :: FP_64 : Mips :: FP ; unsigned ZERO = STI . isABI_N64 ( ) ? Mips :: ZERO_64 : Mips :: ZERO ; unsigned ADDu = STI . isABI_N64 ( ) ? Mips :: DADDu : Mips :: ADDu ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( ADDu ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize , MBB , MBBI ) ; } </s>

Mips Mips Mips Mips Mips::SP_64 Mips::SP Mips::FP_64 Mips::FP Mips::ZERO_64 Mips::ZERO Mips::DADDu Mips::ADDu 0


<s> int NVPTXFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; FrameReg = NVPTX :: VRDepot ; return MFI . getObjectOffset ( FI ) - getOffsetOfLocalArea ( ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> static rtx ix86_expand_vec_init_builtin ( tree type , tree arglist , rtx target ) { enum machine_mode tmode = TYPE_MODE ( type ) ; enum machine_mode inner_mode = GET_MODE_INNER ( tmode ) ; int i , n_elt = GET_MODE_NUNITS ( tmode ) ; rtvec v = rtvec_alloc ( n_elt ) ; gcc_assert ( VECTOR_MODE_P ( tmode ) ) ; for ( i = 0 ; i < n_elt ; ++ i , arglist = TREE_CHAIN ( arglist ) ) { rtx x = expand_expr ( TREE_VALUE ( arglist ) , NULL_RTX , VOIDmode , 0 ) ; RTVEC_ELT ( v , i ) = gen_lowpart ( inner_mode , x ) ; } gcc_assert ( arglist == NULL ) ; if ( ! target || ! register_operand ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; ix86_expand_vector_init ( true , target , gen_rtx_PARALLEL ( tmode , v ) ) ; return target ; } </s>

A subroutine of ix86_expand_builtin . These builtins are a wrapper around ix86_expand_vector_init . We DO have language-level syntax for this , in the form of ( type ) { init-list } . Except that since we ca n't place emms instructions from inside the compiler , we ca n't allow the use of MMX registers unless the user explicitly asks for it . So we do * not * define vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md . Instead we have builtins invoked by mmintrin.h that gives us license to emit these sorts of instructions .


"getMemOperandWithOffset only supports base "

"operands of type register or frame index."

Return true if get the base operand , byte offset of an instruction and the memory width .


<s> void AMDGPUInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot ) { OS . flush ( ) ; printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static void mips_sim_wait_regs_1 ( rtx * x , void * data ) { for_each_rtx ( x , mips_sim_wait_regs_2 , data ) ; } </s>

Call mips_sim_wait_regs_2 ( R , DATA ) for each register R mentioned in * X .


"Cannot store this register into a stack slot!"

Store the specified register of the given register class to the specified stack frame index .


<s> bool Z80ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { getAnalysis < LiveIntervals > ( ) . addKillFlags ( & getAnalysis < VirtRegMap > ( ) ) ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; bool Modified = false ; for ( auto & MBB : MF ) Modified |= ExpandMBB ( MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> yaml :: MachineFunctionInfo * GCNTargetMachine :: convertFuncInfoToYAML ( const MachineFunction & MF ) const { const SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; return new yaml :: SIMachineFunctionInfo ( * MFI , * MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; } </s>

Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo .


<s> bool MipsInstrInfo :: SafeInLoadDelaySlot ( const MachineInstr & MIInSlot , const MachineInstr & LoadMI ) const { if ( MIInSlot . isInlineAsm ( ) ) return false ; return ! llvm :: any_of ( LoadMI . defs ( ) , [ & ] ( const MachineOperand & Op ) { return Op . isReg ( ) && MIInSlot . readsRegister ( Op . getReg ( ) ) ; } ) ; } </s>

Predicate to determine if an instruction can go in a load delay slot .


<s> static void aarch64_process_components ( sbitmap components , bool prologue_p ) { rtx ptr_reg = gen_rtx_REG ( Pmode , frame_pointer_needed ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ) ; unsigned last_regno = SBITMAP_SIZE ( components ) ; unsigned regno = aarch64_get_next_set_bit ( components , R0_REGNUM ) ; rtx_insn * insn = NULL ; while ( regno != last_regno ) { machine_mode mode = GP_REGNUM_P ( regno ) ? DImode : DFmode ; rtx reg = gen_rtx_REG ( mode , regno ) ; HOST_WIDE_INT offset = cfun -> machine -> frame . reg_offset [ regno ] ; if ( ! frame_pointer_needed ) offset += cfun -> machine -> frame . frame_size - cfun -> machine -> frame . hard_fp_offset ; rtx addr = plus_constant ( Pmode , ptr_reg , offset ) ; rtx mem = gen_frame_mem ( mode , addr ) ; rtx set = prologue_p ? gen_rtx_SET ( mem , reg ) : gen_rtx_SET ( reg , mem ) ; unsigned regno2 = aarch64_get_next_set_bit ( components , regno + 1 ) ; if ( regno2 == last_regno ) { insn = emit_insn ( set ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( prologue_p ) add_reg_note ( insn , REG_CFA_OFFSET , copy_rtx ( set ) ) ; else add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; break ; } HOST_WIDE_INT offset2 = cfun -> machine -> frame . reg_offset [ regno2 ] ; if ( ! satisfies_constraint_Ump ( mem ) || GP_REGNUM_P ( regno ) != GP_REGNUM_P ( regno2 ) || ( offset2 - cfun -> machine -> frame . reg_offset [ regno ] ) != GET_MODE_SIZE ( mode ) ) { insn = emit_insn ( set ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( prologue_p ) add_reg_note ( insn , REG_CFA_OFFSET , copy_rtx ( set ) ) ; else add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; regno = regno2 ; continue ; } rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; if ( ! frame_pointer_needed ) offset2 += cfun -> machine -> frame . frame_size - cfun -> machine -> frame . hard_fp_offset ; rtx addr2 = plus_constant ( Pmode , ptr_reg , offset2 ) ; rtx mem2 = gen_frame_mem ( mode , addr2 ) ; rtx set2 = prologue_p ? gen_rtx_SET ( mem2 , reg2 ) : gen_rtx_SET ( reg2 , mem2 ) ; if ( prologue_p ) insn = emit_insn ( aarch64_gen_store_pair ( mode , mem , reg , mem2 , reg2 ) ) ; else insn = emit_insn ( aarch64_gen_load_pair ( mode , reg , mem , reg2 , mem2 ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( prologue_p ) { add_reg_note ( insn , REG_CFA_OFFSET , set ) ; add_reg_note ( insn , REG_CFA_OFFSET , set2 ) ; } else { add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; add_reg_note ( insn , REG_CFA_RESTORE , reg2 ) ; } regno = aarch64_get_next_set_bit ( components , regno2 + 1 ) ; } } </s>

Do the work for aarch64_emit_prologue_components and aarch64_emit_epilogue_components . COMPONENTS is the bitmap of registers to save/restore , PROLOGUE_P indicates whether to emit the prologue sequence for these components or the epilogue sequence . That is , it determines whether we should emit stores or loads and what kind of CFA notes to attach to the insns . Otherwise the logic for the two sequences is very similar .


<s> static machine_mode sparc_promote_function_mode ( const_tree type , machine_mode mode , int * punsignedp , const_tree , int ) { if ( type && POINTER_TYPE_P ( type ) ) { * punsignedp = POINTERS_EXTEND_UNSIGNED ; return Pmode ; } if ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) < UNITS_PER_WORD ) return word_mode ; return mode ; } </s>

Handle promotion of pointer and integer arguments .


<s> bool HexagonPassConfig :: addPreRegAlloc ( ) { if ( ! DisableHardwareLoops ) { addPass ( createHexagonHardwareLoops ( ) ) ; } return false ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> void erasingInstr ( MachineInstr & MI ) override { } </s>


<s>
const
char
*
fpuv3_output_move
(
rtx
*
operands
)
{
rtx
reg
,
mem
,
addr
,
ops
[
2
]
;
bool
isload
=
REG_P
(
operands
[
0
]
)
;
const
char
*
templ
=
"f%s%s.%s\t%%0, %%1"
;
char
buff
[
50
]
;
machine_mode
mode
;
reg
=
operands
[
isload
0
:
1
]
;
mem
=
operands
[
isload
1
:
0
]
;
gcc_assert
(
REG_P
(
reg
)
)
;
gcc_assert
(
CSKY_VREG_P
(
REGNO
(
reg
)
)
)
;
gcc_assert
(
MEM_P
(
mem
)
)
;
mode
=
GET_MODE
(
reg
)
;
const
char
*
type
=
mode
==
DFmode
"64"
:
mode
==
SFmode
"32"
:
mode
==
HFmode
"16"
:
;
gcc_assert
(
type
!=
)
;
addr
=
XEXP
(
mem
,
0
)
;
struct
csky_address
caddr
;
decompose_csky_address
(
addr
,
&
caddr
)
;
ops
[
0
]
=
reg
;
ops
[
1
]
=
mem
;
sprintf
(
buff
,
templ
,
isload
"ld"
:
"st"
,
caddr
.
index
"r"
:
""
,
type
)
;
output_asm_insn
(
buff
,
ops
)
;
return
""
;
}
</s>

Output float point load/store instructions for fpuv3 .


<s> DecodeStatus PPCDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & OS , raw_ostream & CS ) const { Size = 4 ; if ( Bytes . size ( ) < 4 ) { Size = 0 ; return MCDisassembler :: Fail ; } uint32_t Inst = IsLittleEndian ? support :: endian :: read32le ( Bytes . data ( ) ) : support :: endian :: read32be ( Bytes . data ( ) ) ; if ( STI . getFeatureBits ( ) [ PPC :: FeatureQPX ] ) { DecodeStatus result = decodeInstruction ( DecoderTableQPX32 , MI , Inst , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) return result ; } else if ( STI . getFeatureBits ( ) [ PPC :: FeatureSPE ] ) { DecodeStatus result = decodeInstruction ( DecoderTableSPE32 , MI , Inst , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) return result ; } return decodeInstruction ( DecoderTable32 , MI , Inst , Address , this , STI ) ; } </s>

Returns the disassembly of a single instruction .

PowerPC PPC 4 4 0 support::endian support::endian PPC::FeatureQPX PPC::FeatureSPE


Emit the appropriate code to do a comparison , returning the register the comparison was done it .


<s> bool MipsFastISel :: fastLowerCall ( CallLoweringInfo & CLI ) { CallingConv :: ID CC = CLI . CallConv ; bool IsTailCall = CLI . IsTailCall ; bool IsVarArg = CLI . IsVarArg ; const Value * Callee = CLI . Callee ; MCSymbol * Symbol = CLI . Symbol ; if ( CC == CallingConv :: Fast ) return false ; if ( IsTailCall ) return false ; if ( IsVarArg ) return false ; MVT RetVT ; if ( CLI . RetTy -> isVoidTy ( ) ) RetVT = MVT :: isVoid ; else if ( ! isTypeSupported ( CLI . RetTy , RetVT ) ) return false ; for ( auto Flag : CLI . OutFlags ) if ( Flag . isInReg ( ) || Flag . isSRet ( ) || Flag . isNest ( ) || Flag . isByVal ( ) ) return false ; SmallVector < MVT , 16 > OutVTs ; OutVTs . reserve ( CLI . OutVals . size ( ) ) ; for ( auto * Val : CLI . OutVals ) { MVT VT ; if ( ! isTypeLegal ( Val -> getType ( ) , VT ) && ! ( VT == MVT :: i1 || VT == MVT :: i8 || VT == MVT :: i16 ) ) return false ; if ( VT . isVector ( ) || VT . getSizeInBits ( ) > 64 ) return false ; OutVTs . push_back ( VT ) ; } Address Addr ; if ( ! computeCallAddress ( Callee , Addr ) ) return false ; unsigned NumBytes ; if ( ! processCallArgs ( CLI , OutVTs , NumBytes ) ) return false ; if ( ! Addr . getGlobalValue ( ) ) return false ; unsigned DestAddress ; if ( Symbol ) DestAddress = materializeExternalCallSym ( Symbol ) ; else DestAddress = materializeGV ( Addr . getGlobalValue ( ) , MVT :: i32 ) ; emitInst ( TargetOpcode :: COPY , Mips :: T9 ) . addReg ( DestAddress ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Mips :: JALR ) , Mips :: RA ) . addReg ( Mips :: T9 ) ; for ( auto Reg : CLI . OutRegs ) MIB . addReg ( Reg , RegState :: Implicit ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( * FuncInfo . MF , CC ) ) ; CLI . Call = MIB ; if ( EmitJalrReloc && ! Subtarget -> inMips16Mode ( ) ) { if ( Symbol ) MIB . addSym ( Symbol , MipsII :: MO_JALR ) ; else MIB . addSym ( FuncInfo . MF -> getContext ( ) . getOrCreateSymbol ( Addr . getGlobalValue ( ) -> getName ( ) ) , MipsII :: MO_JALR ) ; } return finishCall ( CLI , RetVT , NumBytes ) ; } </s>

This method is called by target-independent code to do target- specific call lowering .


<s> static void nios2_deregister_custom_code ( unsigned int N ) { if ( N <= 255 ) { custom_code_status [ N ] = CCS_UNUSED ; custom_code_index [ N ] = 0 ; } } </s>


Return an array that contains the bitmask target flag values and their names .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Lanai Delay Slot Filler"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
void
assignValueToReg
(
unsigned
ValVReg
,
unsigned
PhysReg
,
CCValAssign
&
VA
)
override
{
assert
(
VA
.
isRegLoc
(
)
&&
"Value shouldn't be assigned to reg"
)
;
assert
(
VA
.
getLocReg
(
)
==
PhysReg
&&
"Assigning to the wrong reg?"
)
;
assert
(
VA
.
getValVT
(
)
.
getSizeInBits
(
)
<=
32
&&
"Unsupported value size"
)
;
assert
(
VA
.
getLocVT
(
)
.
getSizeInBits
(
)
==
32
&&
"Unsupported location size"
)
;
MIRBuilder
.
getMBB
(
)
.
addLiveIn
(
PhysReg
)
;
MIRBuilder
.
buildCopy
(
ValVReg
,
PhysReg
)
;
}
</s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .

ARM
"Value shouldn't be assigned to reg"
"Assigning to the wrong reg?"
32
"Unsupported value size"
32
"Unsupported location size"


<s> bool X86TargetLowering :: canMergeStoresTo ( unsigned AddressSpace , EVT MemVT , const SelectionDAG & DAG ) const { bool NoFloat = DAG . getMachineFunction ( ) . getFunction ( ) . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; if ( NoFloat ) { unsigned MaxIntSize = Subtarget . is64Bit ( ) ? 64 : 32 ; return ( MemVT . getSizeInBits ( ) <= MaxIntSize ) ; } if ( MemVT . getSizeInBits ( ) > Subtarget . getPreferVectorWidth ( ) ) return false ; return true ; } </s>

Returns if it 's reasonable to merge stores to MemVT size .


<s> static unsigned int flags_from_mode ( machine_mode mode ) { switch ( mode ) { case E_CC_ZSmode : return CC_FLAG_S | CC_FLAG_Z ; case E_CC_ZSOmode : return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_O ; case E_CC_ZSCmode : return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_C ; case E_CCmode : return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_O | CC_FLAG_C ; case E_CC_Fmode : return CC_FLAG_FP ; default : gcc_unreachable ( ) ; } } </s>

Convert a CC_MODE to the set of flags that it represents .


<s> void LanaiInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annotation , const MCSubtargetInfo & , raw_ostream & OS ) { if ( ! printAlias ( MI , OS ) && ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , Address , OS ) ; printAnnotation ( OS , Annotation ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool AArch64TargetLowering :: shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return false ; int64_t Val = Imm . getSExtValue ( ) ; if ( Val == 0 || AArch64_AM :: isLogicalImmediate ( Val , BitSize ) ) return true ; if ( ( int64_t ) Val < 0 ) Val = ~ Val ; if ( BitSize == 32 ) Val &= ( 1LL << 32 ) - 1 ; unsigned LZ = countLeadingZeros ( ( uint64_t ) Val ) ; unsigned Shift = ( 63 - LZ ) / 16 ; return ( Shift < 3 ) ? true : false ; } </s>

Returns true if it is beneficial to convert a load of a constant to just the constant itself .


<s>
StringRef
AArch64MCExpr
::
getVariantKindName
(
)
const
{
switch
(
static_cast
<
uint32_t
>
(
getKind
(
)
)
)
{
case
VK_CALL
:
return
""
;
case
VK_LO12
:
return
":lo12:"
;
case
VK_ABS_G3
:
return
":abs_g3:"
;
case
VK_ABS_G2
:
return
":abs_g2:"
;
case
VK_ABS_G2_S
:
return
":abs_g2_s:"
;
case
VK_ABS_G2_NC
:
return
":abs_g2_nc:"
;
case
VK_ABS_G1
:
return
":abs_g1:"
;
case
VK_ABS_G1_S
:
return
":abs_g1_s:"
;
case
VK_ABS_G1_NC
:
return
":abs_g1_nc:"
;
case
VK_ABS_G0
:
return
":abs_g0:"
;
case
VK_ABS_G0_S
:
return
":abs_g0_s:"
;
case
VK_ABS_G0_NC
:
return
":abs_g0_nc:"
;
case
VK_PREL_G3
:
return
":prel_g3:"
;
case
VK_PREL_G2
:
return
":prel_g2:"
;
case
VK_PREL_G2_NC
:
return
":prel_g2_nc:"
;
case
VK_PREL_G1
:
return
":prel_g1:"
;
case
VK_PREL_G1_NC
:
return
":prel_g1_nc:"
;
case
VK_PREL_G0
:
return
":prel_g0:"
;
case
VK_PREL_G0_NC
:
return
":prel_g0_nc:"
;
case
VK_DTPREL_G2
:
return
":dtprel_g2:"
;
case
VK_DTPREL_G1
:
return
":dtprel_g1:"
;
case
VK_DTPREL_G1_NC
:
return
":dtprel_g1_nc:"
;
case
VK_DTPREL_G0
:
return
":dtprel_g0:"
;
case
VK_DTPREL_G0_NC
:
return
":dtprel_g0_nc:"
;
case
VK_DTPREL_HI12
:
return
":dtprel_hi12:"
;
case
VK_DTPREL_LO12
:
return
":dtprel_lo12:"
;
case
VK_DTPREL_LO12_NC
:
return
":dtprel_lo12_nc:"
;
case
VK_TPREL_G2
:
return
":tprel_g2:"
;
case
VK_TPREL_G1
:
return
":tprel_g1:"
;
case
VK_TPREL_G1_NC
:
return
":tprel_g1_nc:"
;
case
VK_TPREL_G0
:
return
":tprel_g0:"
;
case
VK_TPREL_G0_NC
:
return
":tprel_g0_nc:"
;
case
VK_TPREL_HI12
:
return
":tprel_hi12:"
;
case
VK_TPREL_LO12
:
return
":tprel_lo12:"
;
case
VK_TPREL_LO12_NC
:
return
":tprel_lo12_nc:"
;
case
VK_TLSDESC_LO12
:
return
":tlsdesc_lo12:"
;
case
VK_ABS_PAGE
:
return
""
;
case
VK_ABS_PAGE_NC
:
return
":pg_hi21_nc:"
;
case
VK_GOT
:
return
":got:"
;
case
VK_GOT_PAGE
:
return
":got:"
;
case
VK_GOT_PAGE_LO15
:
return
":gotpage_lo15:"
;
case
VK_GOT_LO12
:
return
":got_lo12:"
;
case
VK_GOTTPREL
:
return
":gottprel:"
;
case
VK_GOTTPREL_PAGE
:
return
":gottprel:"
;
case
VK_GOTTPREL_LO12_NC
:
return
":gottprel_lo12:"
;
case
VK_GOTTPREL_G1
:
return
":gottprel_g1:"
;
case
VK_GOTTPREL_G0_NC
:
return
":gottprel_g0_nc:"
;
case
VK_TLSDESC
:
return
""
;
case
VK_TLSDESC_PAGE
:
return
":tlsdesc:"
;
case
VK_SECREL_LO12
:
return
":secrel_lo12:"
;
case
VK_SECREL_HI12
:
return
":secrel_hi12:"
;
default
:
llvm_unreachable
(
"Invalid ELF symbol kind"
)
;
}
}
</s>

Convert the variant kind into an ELF-appropriate modifier ( e.g .


<s> TargetLowering :: ConstraintWeight MipsTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'd' : case 'y' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> unsigned int compute_mov_length ( rtx * operands ) { machine_mode mode = GET_MODE ( operands [ 0 ] ) ; rtx dest = operands [ 0 ] ; rtx src = operands [ 1 ] ; rtx addr ; if ( GET_CODE ( src ) == MEM ) addr = XEXP ( src , 0 ) ; else if ( GET_CODE ( dest ) == MEM ) addr = XEXP ( dest , 0 ) ; else addr = NULL_RTX ; unsigned int base_length ; switch ( mode ) { case E_QImode : if ( addr == NULL_RTX ) return 2 ; if ( h8300_eightbit_constant_address_p ( addr ) ) return 2 ; base_length = 8 ; break ; case E_HImode : if ( addr == NULL_RTX ) { if ( REG_P ( src ) ) return 2 ; if ( src == const0_rtx ) return 2 ; return 4 ; } base_length = 8 ; break ; case E_SImode : if ( addr == NULL_RTX ) { if ( REG_P ( src ) ) { if ( REGNO ( src ) == MAC_REG || REGNO ( dest ) == MAC_REG ) return 4 ; else return 2 ; } if ( GET_CODE ( src ) == CONST_INT ) { int val = INTVAL ( src ) ; if ( val == 0 ) return 2 ; if ( val == ( val & 0x00ff ) || val == ( val & 0xff00 ) ) return 4 ; switch ( val & 0xffffffff ) { case 0xffffffff : case 0xfffffffe : case 0xfffffffc : case 0x0000ffff : case 0x0000fffe : case 0xffff0000 : case 0xfffe0000 : case 0x00010000 : case 0x00020000 : return 4 ; } } return 6 ; } base_length = 10 ; break ; case E_SFmode : if ( addr == NULL_RTX ) { if ( REG_P ( src ) ) return 2 ; if ( satisfies_constraint_G ( src ) ) return 2 ; return 6 ; } base_length = 10 ; break ; default : gcc_unreachable ( ) ; } if ( GET_CODE ( addr ) == PRE_DEC || GET_CODE ( addr ) == POST_INC ) return base_length - 6 ; if ( GET_CODE ( addr ) == REG ) return base_length - 6 ; if ( GET_CODE ( addr ) == PLUS && GET_CODE ( XEXP ( addr , 0 ) ) == REG && GET_CODE ( XEXP ( addr , 1 ) ) == CONST_INT && INTVAL ( XEXP ( addr , 1 ) ) > - 32768 && INTVAL ( XEXP ( addr , 1 ) ) < 32767 ) return base_length - 4 ; if ( h8300_tiny_constant_address_p ( addr ) ) return base_length - 4 ; if ( CONSTANT_P ( addr ) ) return base_length - 2 ; return base_length ; } </s>


Return the DataLayout associated with the module this SCEV instance is operating on .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Mips Constant Islands"
;
}
</s>


<s> const Nios2RegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void spu_allocate_stack ( rtx op0 , rtx op1 ) { HOST_WIDE_INT v ; rtx chain = gen_reg_rtx ( V4SImode ) ; rtx stack_bot = gen_frame_mem ( V4SImode , stack_pointer_rtx ) ; rtx sp = gen_reg_rtx ( V4SImode ) ; rtx splatted = gen_reg_rtx ( V4SImode ) ; rtx pat = gen_reg_rtx ( TImode ) ; emit_move_insn ( chain , stack_bot ) ; op1 = force_reg ( SImode , op1 ) ; v = 0x1020300010203ll ; emit_move_insn ( pat , immed_double_const ( v , v , TImode ) ) ; emit_insn ( gen_shufb ( splatted , op1 , op1 , pat ) ) ; emit_insn ( gen_spu_convert ( sp , stack_pointer_rtx ) ) ; emit_insn ( gen_subv4si3 ( sp , sp , splatted ) ) ; if ( flag_stack_check || flag_stack_clash_protection ) { rtx avail = gen_reg_rtx ( SImode ) ; rtx result = gen_reg_rtx ( SImode ) ; emit_insn ( gen_vec_extractv4sisi ( avail , sp , GEN_INT ( 1 ) ) ) ; emit_insn ( gen_cgt_si ( result , avail , GEN_INT ( - 1 ) ) ) ; emit_insn ( gen_spu_heq ( result , GEN_INT ( 0 ) ) ) ; } emit_insn ( gen_spu_convert ( stack_pointer_rtx , sp ) ) ; emit_move_insn ( stack_bot , chain ) ; emit_move_insn ( op0 , virtual_stack_dynamic_rtx ) ; } </s>

We need to correctly update the back chain pointer and the Available Stack Size ( which is in the second slot of the sp register . )


<s> BitVector ARCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( ARC :: ILINK ) ; Reserved . set ( ARC :: SP ) ; Reserved . set ( ARC :: GP ) ; Reserved . set ( ARC :: R25 ) ; Reserved . set ( ARC :: BLINK ) ; Reserved . set ( ARC :: FP ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .

ARC ARC ARC::ILINK ARC::SP ARC::GP ARC::R25 ARC::BLINK ARC::FP


<s> void M68kInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << "%" << getRegisterName ( RegNo ) ; } </s>


<s> bool AMDGPUPropagateAttributesEarly :: runOnFunction ( Function & F ) { if ( ! TM ) { auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; TM = & TPC -> getTM < TargetMachine > ( ) ; } if ( ! AMDGPU :: isKernel ( F . getCallingConv ( ) ) ) return false ; return AMDGPUPropagateAttributes ( TM , false ) . process ( F ) ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool PPCFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( ! Subtarget . isSVR4ABI ( ) ) return false ; MachineFunction * MF = MBB . getParent ( ) ; const PPCInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; PPCFunctionInfo * FI = MF -> getInfo < PPCFunctionInfo > ( ) ; bool MustSaveTOC = FI -> mustSaveTOC ( ) ; DebugLoc DL ; bool CRSpilled = false ; MachineInstrBuilder CRMIB ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg == PPC :: VRSAVE ) continue ; bool IsCRField = PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ; const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; bool IsLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! IsLiveIn ) MBB . addLiveIn ( Reg ) ; if ( CRSpilled && IsCRField ) { CRMIB . addReg ( Reg , RegState :: ImplicitKill ) ; continue ; } if ( ( Reg == PPC :: X2 || Reg == PPC :: R2 ) && MustSaveTOC ) continue ; if ( IsCRField ) { PPCFunctionInfo * FuncInfo = MF -> getInfo < PPCFunctionInfo > ( ) ; if ( Subtarget . isPPC64 ( ) ) { FuncInfo -> addMustSaveCR ( Reg ) ; } else { CRSpilled = true ; FuncInfo -> setSpillsCR ( ) ; CRMIB = BuildMI ( * MF , DL , TII . get ( PPC :: MFCR ) , PPC :: R12 ) . addReg ( Reg , RegState :: ImplicitKill ) ; MBB . insert ( MI , CRMIB ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( PPC :: STW ) ) . addReg ( PPC :: R12 , getKillRegState ( true ) ) , CSI [ i ] . getFrameIdx ( ) ) ) ; } } else { if ( CSI [ i ] . isSpilledToReg ( ) ) { NumPESpillVSR ++ ; BuildMI ( MBB , MI , DL , TII . get ( PPC :: MTVSRD ) , CSI [ i ] . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , ! IsLiveIn , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


"switch %<-mcpu=%s%> conflicts with %<-march=%s%> switch"

"assembler does not support %<-mabi=ilp32%>"

"return address signing is only supported for %<-mabi=lp64%>"


Implement the allocate_stack pattern ( alloca ) .


<s> void m68hc11_init_cumulative_args ( CUMULATIVE_ARGS * cum , tree fntype , rtx libname ) { tree ret_type ; z_replacement_completed = 0 ; cum -> words = 0 ; cum -> nregs = 0 ; if ( fntype == 0 ) { const char * name ; size_t len ; if ( libname == 0 || GET_CODE ( libname ) != SYMBOL_REF ) return ; name = XSTR ( libname , 0 ) ; len = strlen ( name ) ; if ( len > 3 && ( ( name [ len - 2 ] == 'd' && ( name [ len - 1 ] == 'f' || name [ len - 1 ] == 'i' ) ) || ( name [ len - 3 ] == 'd' && ( name [ len - 2 ] == 'i' || name [ len - 2 ] == 'f' ) ) ) ) { cum -> words = 1 ; cum -> nregs = 1 ; } return ; } ret_type = TREE_TYPE ( fntype ) ; if ( ret_type && aggregate_value_p ( ret_type , fntype ) ) { cum -> words = 1 ; cum -> nregs = 1 ; } } </s>

Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is 0 .


"Removing insn %d from candidates list\n"

For a given bitmap of insn UIDs scans all instructions and remove insn from CANDIDATES in case it has both convertible and not convertible definitions . All insns in a bitmap are conversion candidates according to scalar_to_vector_candidate_p . Currently it implies all insns are single_set .


<s> void i386_pe_unique_section ( tree decl , int reloc ) { int len ; const char * name , * prefix ; char * string ; if ( ! flag_writable_rel_rdata ) reloc = 0 ; name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; name = i386_pe_strip_name_encoding_full ( name ) ; if ( TREE_CODE ( decl ) == FUNCTION_DECL ) prefix = ".text$" ; else if ( decl_readonly_section ( decl , reloc ) ) prefix = ".rdata$" ; else prefix = ".data$" ; len = strlen ( name ) + strlen ( prefix ) ; string = XALLOCAVEC ( char , len + 1 ) ; sprintf ( string , "%s%s" , prefix , name ) ; set_decl_section_name ( decl , string ) ; } </s>


"WebAssembly can only return up to one value"

"WebAssembly doesn't support non-C calling conventions"

"WebAssembly hasn't implemented inalloca results"

"WebAssembly hasn't implemented cons regs results"

"WebAssembly hasn't implemented cons regs last results"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> SDValue MipsSETargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: LOAD : return lowerLOAD ( Op , DAG ) ; case ISD :: STORE : return lowerSTORE ( Op , DAG ) ; case ISD :: SMUL_LOHI : return lowerMulDiv ( Op , MipsISD :: Mult , true , true , DAG ) ; case ISD :: UMUL_LOHI : return lowerMulDiv ( Op , MipsISD :: Multu , true , true , DAG ) ; case ISD :: MULHS : return lowerMulDiv ( Op , MipsISD :: Mult , false , true , DAG ) ; case ISD :: MULHU : return lowerMulDiv ( Op , MipsISD :: Multu , false , true , DAG ) ; case ISD :: MUL : return lowerMulDiv ( Op , MipsISD :: Mult , true , false , DAG ) ; case ISD :: SDIVREM : return lowerMulDiv ( Op , MipsISD :: DivRem , true , true , DAG ) ; case ISD :: UDIVREM : return lowerMulDiv ( Op , MipsISD :: DivRemU , true , true , DAG ) ; case ISD :: INTRINSIC_WO_CHAIN : return lowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case ISD :: INTRINSIC_W_CHAIN : return lowerINTRINSIC_W_CHAIN ( Op , DAG ) ; case ISD :: INTRINSIC_VOID : return lowerINTRINSIC_VOID ( Op , DAG ) ; case ISD :: EXTRACT_VECTOR_ELT : return lowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case ISD :: BUILD_VECTOR : return lowerBUILD_VECTOR ( Op , DAG ) ; case ISD :: VECTOR_SHUFFLE : return lowerVECTOR_SHUFFLE ( Op , DAG ) ; case ISD :: SELECT : return lowerSELECT ( Op , DAG ) ; } return MipsTargetLowering :: LowerOperation ( Op , DAG ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::LOAD ISD::STORE ISD::SMUL_LOHI MipsISD::Mult ISD::UMUL_LOHI MipsISD::Multu ISD::MULHS MipsISD::Mult ISD::MULHU MipsISD::Multu ISD::MUL MipsISD::Mult ISD::SDIVREM MipsISD::DivRem ISD::UDIVREM MipsISD::DivRemU ISD::INTRINSIC_WO_CHAIN ISD::INTRINSIC_W_CHAIN ISD::INTRINSIC_VOID ISD::EXTRACT_VECTOR_ELT ISD::BUILD_VECTOR ISD::VECTOR_SHUFFLE ISD::SELECT Mips


<s> static int get_some_local_dynamic_name_1 ( rtx * px , void * data ATTRIBUTE_UNUSED ) { rtx x = * px ; if ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_DYNAMIC ) { cfun -> machine -> some_ld_name = XSTR ( x , 0 ) ; return 1 ; } return 0 ; } </s>


"X86 Load Value Injection (LVI) Load Hardening (Unoptimized)"

getPassName - Return a nice clean name for a pass .


<s>
bool
RISCVInstrInfo
::
reverseBranchCondition
(
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
assert
(
(
Cond
.
size
(
)
==
3
)
&&
"Invalid branch condition!"
)
;
Cond
[
0
]
.
setImm
(
getOppositeBranchOpcode
(
Cond
[
0
]
.
getImm
(
)
)
)
;
return
false
;
}
</s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> bool mn10300_can_use_retf_insn ( void ) { if ( ! optimize ) return false ; if ( crtl -> calls_eh_return ) return false ; if ( df_regs_ever_live_p ( MDR_REG ) ) return false ; gcc_assert ( ! in_sequence_p ( ) ) ; return leaf_function_p ( ) ; } </s>

If the MDR register is never clobbered , we can use the RETF instruction which takes the address from the MDR register . This is 3 cycles faster than having to load the address from the stack .


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , CM , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) { if ( ( TT . isOSWindows ( ) && TT . getArch ( ) == Triple :: x86_64 ) || TT . isPS4 ( ) ) this -> Options . TrapUnreachable = true ; initAsmInfo ( ) ; } </s>


<s> unsigned AMDGPUSubtarget :: getOccupancyWithLocalMemSize ( const MachineFunction & MF ) const { const auto * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; return getOccupancyWithLocalMemSize ( MFI -> getLDSSize ( ) , MF . getFunction ( ) ) ; } </s>

Inverse of getMaxLocalMemWithWaveCount .


"\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "


<s> void HexagonExpandCondsets :: shrinkToUses ( unsigned Reg , LiveInterval & LI ) { SmallVector < MachineInstr * , 4 > Deads ; LIS -> shrinkToUses ( & LI , & Deads ) ; for ( unsigned i = 0 , n = Deads . size ( ) ; i < n ; ++ i ) { MachineInstr * MI = Deads [ i ] ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) || Op . getReg ( ) != Reg ) continue ; Op . setIsDead ( false ) ; } LiveInterval :: iterator End = LI . end ( ) ; SlotIndex S = LIS -> getInstructionIndex ( MI ) . getRegSlot ( ) ; LiveInterval :: iterator T = LI . FindSegmentContaining ( S ) ; assert ( T != End ) ; LiveInterval :: iterator N = std :: next ( T ) ; if ( N != End ) T -> end = N -> start ; else T -> end = LIS -> getMBBEndIdx ( MI -> getParent ( ) ) ; } updateKillFlags ( Reg , LI ) ; } </s>

Specialized version of shrinkToUses ( LiveInterval li , SmallVectorImpl < MachineInstr > * dead ) that works on a subregister live range and only looks at uses matching the lane mask of the subregister range .


<s> std :: pair < uint16_t , uint16_t > X86InstrInfo :: getExecutionDomain ( const MachineInstr & MI ) const { uint16_t domain = ( MI . getDesc ( ) . TSFlags >> X86II :: SSEDomainShift ) & 3 ; uint16_t validDomains = 0 ; if ( domain && lookup ( MI . getOpcode ( ) , domain ) ) validDomains = 0xe ; else if ( domain && lookupAVX2 ( MI . getOpcode ( ) , domain ) ) validDomains = Subtarget . hasAVX2 ( ) ? 0xe : 0x6 ; else if ( domain && lookupAVX512 ( MI . getOpcode ( ) , domain ) ) validDomains = 0xe ; else if ( domain && lookupAVX512DQ ( MI . getOpcode ( ) , domain ) ) validDomains = Subtarget . hasDQI ( ) ? 0xe : 0x8 ; return std :: make_pair ( domain , validDomains ) ; } </s>

Return the current execution domain and bit mask of possible domains for instruction .


"InsertBranch must not be told to insert a fallthrough"

"ARC branch conditions have two components!"

Insert branch code into the end of the specified MachineBasicBlock .


"Can only insert epilog into returning blocks"

"Expected to see callee-save register restore code"


<s> void EmitInstruction ( uint64_t Val , unsigned Size , const MCSubtargetInfo & STI , raw_ostream & OS ) const { if ( IsLittleEndian && Size == 4 && isMicroMips ( STI ) ) { EmitInstruction ( Val >> 16 , 2 , STI , OS ) ; EmitInstruction ( Val , 2 , STI , OS ) ; } else { for ( unsigned i = 0 ; i < Size ; ++ i ) { unsigned Shift = IsLittleEndian ? i * 8 : ( Size - 1 - i ) * 8 ; EmitByte ( ( Val >> Shift ) & 0xff , OS ) ; } } } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> SDNode * SITargetLowering :: PostISelFolding ( MachineSDNode * Node , SelectionDAG & DAG ) const { const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; Node = AdjustRegClass ( Node , DAG ) ; if ( TII -> isMIMG ( Node -> getMachineOpcode ( ) ) ) adjustWritemask ( Node , DAG ) ; if ( Node -> getMachineOpcode ( ) == AMDGPU :: INSERT_SUBREG || Node -> getMachineOpcode ( ) == AMDGPU :: REG_SEQUENCE ) { legalizeTargetIndependentNode ( Node , DAG ) ; return Node ; } return Node ; } </s>

Fold the instructions after selecting them .


<s> MachineInstrBuilder R600InstrInfo :: buildDefaultInstruction ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned Opcode , unsigned DstReg , unsigned Src0Reg , unsigned Src1Reg ) const { MachineInstrBuilder MIB = BuildMI ( MBB , I , MBB . findDebugLoc ( I ) , get ( Opcode ) , DstReg ) ; if ( Src1Reg ) { MIB . addImm ( 0 ) . addImm ( 0 ) ; } MIB . addImm ( 1 ) . addImm ( 0 ) . addImm ( 0 ) . addImm ( 0 ) . addReg ( Src0Reg ) . addImm ( 0 ) . addImm ( 0 ) . addImm ( 0 ) . addImm ( - 1 ) ; if ( Src1Reg ) { MIB . addReg ( Src1Reg ) . addImm ( 0 ) . addImm ( 0 ) . addImm ( 0 ) . addImm ( - 1 ) ; } MIB . addImm ( 1 ) . addReg ( AMDGPU :: PRED_SEL_OFF ) . addImm ( 0 ) . addImm ( 0 ) ; return MIB ; } </s>

buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers initialized to their default values .


<s>
void
alpha_end_function
(
FILE
*
file
,
const
char
*
fnname
,
tree
decl
ATTRIBUTE_UNUSED
)
{
alpha_write_linkage
(
file
,
fnname
,
decl
)
;
if
(
!
TARGET_ABI_UNICOSMK
&&
!
flag_inhibit_size_directive
)
{
fputs
(
"\t.end "
,
file
)
;
assemble_name
(
file
,
fnname
)
;
putc
(
'\n'
,
file
)
;
}
inside_function
=
FALSE
;
if
(
TARGET_ABI_UNICOSMK
)
{
unicosmk_output_ssib
(
file
,
fnname
)
;
unicosmk_output_deferred_case_vectors
(
file
)
;
}
}
</s>

Output the rest of the textual info surrounding the epilogue .


<s>
void
Thumb1InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
Register
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
&
ARM
::
tGPRRegClass
||
(
Register
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
&
ARM
::
tGPRRegClass
||
(
Register
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
,
MachineMemOperand
::
MOStore
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tSTRspi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .

ARM
ARM::tGPRRegClass
ARM
"Unknown regclass!"
ARM::tGPRRegClass
ARM
ARM::tSTRspi
0
ARMCC::AL


<s> bool Z80oldTargetLowering :: isLegalAddImmediate ( int64_t Imm ) const { return isInt < 8 > ( Imm ) ; } </s>

Return true if the specified immediate is legal add immediate , that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register .


<s> BitVector SIRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AMDGPU :: INDIRECT_BASE_ADDR ) ; reserveRegisterTuples ( Reserved , AMDGPU :: EXEC ) ; reserveRegisterTuples ( Reserved , AMDGPU :: FLAT_SCR ) ; reserveRegisterTuples ( Reserved , AMDGPU :: M0 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_SHARED_BASE ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_SHARED_LIMIT ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_PRIVATE_BASE ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_PRIVATE_LIMIT ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TBA ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TMA ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP0_TTMP1 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP2_TTMP3 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP4_TTMP5 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP6_TTMP7 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP8_TTMP9 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP10_TTMP11 ) ; const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; unsigned MaxNumSGPRs = ST . getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = AMDGPU :: SGPR_32RegClass . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = AMDGPU :: SGPR_32RegClass . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } unsigned MaxNumVGPRs = ST . getMaxNumVGPRs ( MF ) ; unsigned TotalNumVGPRs = AMDGPU :: VGPR_32RegClass . getNumRegs ( ) ; for ( unsigned i = MaxNumVGPRs ; i < TotalNumVGPRs ; ++ i ) { unsigned Reg = AMDGPU :: VGPR_32RegClass . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } const SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , ScratchWaveOffsetReg ) ; } unsigned ScratchRSrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRSrcReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , ScratchRSrcReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , ScratchWaveOffsetReg ) ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> const char * SNESMCExpr :: getName ( ) const { const auto & Modifier = std :: find_if ( std :: begin ( ModifierNames ) , std :: end ( ModifierNames ) , [ this ] ( ModifierEntry const & Mod ) { return Mod . VariantKind == Kind ; } ) ; if ( Modifier != std :: end ( ModifierNames ) ) { return Modifier -> Spelling ; } return nullptr ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s>
LLVM_DUMP_METHOD
void
M68kInstructionLookup
::
dump
(
)
const
{
dbgs
(
)
<<
"M68kInstructionLookup "
<<
OpCode
<<
" "
;
for
(
unsigned
I
=
0
,
E
=
Mask
.
size
(
)
;
I
<
E
;
++
I
)
{
uint16_t
WordMask
=
Mask
[
I
]
;
uint16_t
WordValue
=
Value
[
I
]
;
for
(
unsigned
B
=
0
;
B
<
16
;
++
B
)
{
uint16_t
Bit
=
(
1
<<
(
15
B
)
)
;
unsigned
IsMasked
=
!
(
WordMask
&
Bit
)
;
unsigned
IsClear
=
!
(
WordValue
&
Bit
)
;
if
(
B
==
8
)
dbgs
(
)
<<
" "
;
char
Ch
=
IsMasked
'?'
:
(
IsClear
'0'
:
'1'
)
;
dbgs
(
)
<<
Ch
;
}
dbgs
(
)
<<
" "
;
}
dbgs
(
)
<<
"\n"
;
}
</s>

Dump the plan to stderr ( for debugging ) .


<s> void AArch64PassConfig :: addPreEmitPass ( ) { if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Aggressive && EnableLoadStoreOpt ) addPass ( createAArch64LoadStoreOptimizationPass ( ) ) ; addPass ( createAArch64A53Fix835769 ( ) ) ; if ( EnableBranchTargets ) addPass ( createAArch64BranchTargetsPass ( ) ) ; if ( BranchRelaxation ) addPass ( & BranchRelaxationPassID ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) { addPass ( createCFGuardLongjmpPass ( ) ) ; addPass ( createEHContGuardCatchretPass ( ) ) ; } if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCompressJumpTables ) addPass ( createAArch64CompressJumpTablesPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> SDValue WebAssemblySelectionDAGInfo :: EmitTargetCodeForMemmove ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Op1 , SDValue Op2 , SDValue Op3 , Align Alignment , bool IsVolatile , bool MustPreserveCheriCapabilities , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { return EmitTargetCodeForMemcpy ( DAG , DL , Chain , Op1 , Op2 , Op3 , Alignment , IsVolatile , false , MustPreserveCheriCapabilities , DstPtrInfo , SrcPtrInfo ) ; } </s>

Emit target-specific code that performs a memmove .


<s> SDNode * ARCompactDAGToDAGISel :: Select ( SDNode * Op ) { DebugLoc dl = Op -> getDebugLoc ( ) ; if ( Op -> isMachineOpcode ( ) ) { return NULL ; } switch ( Op -> getOpcode ( ) ) { case ISD :: FrameIndex : { assert ( Op -> getValueType ( 0 ) == MVT :: i32 ) ; int FI = cast < FrameIndexSDNode > ( Op ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , MVT :: i32 ) ; if ( Op -> hasOneUse ( ) ) { return CurDAG -> SelectNodeTo ( Op , ARC :: ADDrli , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , MVT :: i32 ) ) ; } return CurDAG -> getMachineNode ( ARC :: ADDrli , dl , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , MVT :: i32 ) ) ; } default : break ; } return SelectCode ( Op ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> bool PPCInstrInfo :: isAssociativeAndCommutative ( const MachineInstr & Inst ) const { switch ( Inst . getOpcode ( ) ) { case PPC :: FADD : case PPC :: FADDS : case PPC :: FMUL : case PPC :: FMULS : case PPC :: VADDFP : case PPC :: XSADDDP : case PPC :: XVADDDP : case PPC :: XVADDSP : case PPC :: XSADDSP : case PPC :: XSMULDP : case PPC :: XVMULDP : case PPC :: XVMULSP : case PPC :: XSMULSP : case PPC :: QVFADD : case PPC :: QVFADDS : case PPC :: QVFADDSs : case PPC :: QVFMUL : case PPC :: QVFMULS : case PPC :: QVFMULSs : return true ; default : return false ; } } </s>

Return true when \P Inst is both associative and commutative .

PowerPC PPC PPC::FADD PPC::FADDS PPC::FMUL PPC::FMULS PPC::VADDFP PPC::XSADDDP PPC::XVADDDP PPC::XVADDSP PPC::XSADDSP PPC::XSMULDP PPC::XVMULDP PPC::XVMULSP PPC::XSMULSP PPC::QVFADD PPC::QVFADDS PPC::QVFADDSs PPC::QVFMUL PPC::QVFMULS PPC::QVFMULSs


<s> unsigned TeakInstrInfo :: insertIndirectBranch ( MachineBasicBlock & MBB , MachineBasicBlock & NewDestBB , const DebugLoc & DL , int64_t BrOffset , RegScavenger * RS ) const { auto & MI = * BuildMI ( & MBB , DL , get ( Teak :: BR_imm18 ) ) . addMBB ( & NewDestBB ) . addImm ( TeakCC :: True ) . addReg ( 0 ) ; return getInstSizeInBytes ( MI ) ; } </s>

Insert an unconditional indirect branch at the end of MBB to NewDestBB .


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return createAMDGPUELFObjectWriter ( OS ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> bool isConstant ( const MachineFrameInfo * ) const override { return false ; } </s>

Returns true if we know the value of all bits .


"This resolveFrameIndex does not support Thumb1!"

"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> unsigned SIInstrInfo :: calculateIndirectAddress ( unsigned RegIndex , unsigned Channel ) const { assert ( Channel == 0 ) ; return RegIndex ; } </s>

Calculate the `` Indirect Address '' for the given RegIndex and Channel .


<s> bool M88kFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return true ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> unsigned ARM64RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? ARM64 :: FP : ARM64 :: SP ; } </s>


<s> bool RISCVTargetLowering :: hasBitTest ( SDValue X , SDValue Y ) const { auto * C = dyn_cast < ConstantSDNode > ( Y ) ; return C && C -> getAPIntValue ( ) . ule ( 10 ) ; } </s>

Return true if the target has a bit-test instruction : ( X & ( 1 < < Y ) ) ==/ ! = 0 This knowledge can be used to prevent breaking the pattern , or creating it if it could be recognized .


<s>
int
extra_constraint
(
rtx
x
,
int
c
)
{
if
(
c
==
'Q'
&&
GET_CODE
(
x
)
==
MEM
&&
GET_CODE
(
XEXP
(
x
,
0
)
)
==
PLUS
)
{
if
(
TARGET_ALL_DEBUG
)
{
fprintf
(
stderr
,
(
"extra_constraint:\n"
"reload_completed: %d\n"
"reload_in_progress: %d\n"
)
,
reload_completed
,
reload_in_progress
)
;
debug_rtx
(
x
)
;
}
if
(
GET_CODE
(
x
)
==
MEM
&&
GET_CODE
(
XEXP
(
x
,
0
)
)
==
PLUS
&&
REG_P
(
XEXP
(
XEXP
(
x
,
0
)
,
0
)
)
&&
GET_CODE
(
XEXP
(
XEXP
(
x
,
0
)
,
1
)
)
==
CONST_INT
&&
(
INTVAL
(
XEXP
(
XEXP
(
x
,
0
)
,
1
)
)
<=
MAX_LD_OFFSET
(
GET_MODE
(
x
)
)
)
)
{
rtx
xx
=
XEXP
(
XEXP
(
x
,
0
)
,
0
)
;
int
regno
=
REGNO
(
xx
)
;
if
(
TARGET_ALL_DEBUG
)
{
fprintf
(
stderr
,
(
"extra_constraint:\n"
"reload_completed: %d\n"
"reload_in_progress: %d\n"
)
,
reload_completed
,
reload_in_progress
)
;
debug_rtx
(
x
)
;
}
if
(
regno
>=
FIRST_PSEUDO_REGISTER
)
return
1
;
else
if
(
regno
==
REG_Z
||
regno
==
REG_Y
)
return
1
;
else
if
(
xx
==
frame_pointer_rtx
||
xx
==
arg_pointer_rtx
)
return
1
;
}
}
return
0
;
}
</s>


"ARM hazards don't support scoreboard lookahead"

getHazardType - Return the hazard type of emitting this node .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"mproc Branch Selector"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> unsigned ARMBaseInstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr * MI , int & FrameIndex ) const { const MachineMemOperand * Dummy ; return MI -> getDesc ( ) . mayLoad ( ) && hasLoadFromStackSlot ( MI , Dummy , FrameIndex ) ; } </s>

isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s> bool ParseDirective ( AsmToken DirectiveID ) override { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal . startswith ( ".mos_addr_asciz" ) ) return parseAddrAsciz ( DirectiveID . getLoc ( ) ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool is_interrupt_func ( const_tree decl ) { return has_func_attr ( decl , "interrupt" ) ; } </s>

Returns true if the provided function has the `` interrupt '' attribute .


<s> void ix86_setup_frame_addresses ( void ) { cfun -> machine -> accesses_prev_frame = 1 ; } </s>

Record that the current function accesses previous call frames .


<s> MachineInstrBuilder SIInstrInfo :: getAddNoCarry ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , Register DestReg , RegScavenger & RS ) const { if ( ST . hasAddNoCarry ( ) ) return BuildMI ( MBB , I , DL , get ( AMDGPU :: V_ADD_U32_e32 ) , DestReg ) ; Register UnusedCarry = ! RS . isRegUsed ( AMDGPU :: VCC ) ? Register ( RI . getVCC ( ) ) : RS . scavengeRegister ( RI . getBoolRC ( ) , I , 0 , false ) ; if ( ! UnusedCarry . isValid ( ) ) return MachineInstrBuilder ( ) ; return BuildMI ( MBB , I , DL , get ( AMDGPU :: V_ADD_I32_e64 ) , DestReg ) . addReg ( UnusedCarry , RegState :: Define | RegState :: Dead ) ; } </s>

Return a partially built integer add instruction without carry .


<s> static rtx arm_expand_unop_builtin ( enum insn_code icode , tree exp , rtx target , int do_load ) { rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , 0 ) ; rtx op0 = expand_normal ( arg0 ) ; machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; machine_mode mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( do_load ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; else { if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; } pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>

Subroutine of arm_expand_builtin to take care of unop insns .


"internal error: instruction without _e64 suffix "

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> const TPCSubtarget * TPCTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; return createSubtarget ( CPU , FS ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

TPC TPC TPC "target-cpu" "target-features"


<s> void MBlazeFrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MBlazeInstrInfo & TII = * static_cast < const MBlazeInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MBlazeFunctionInfo * MBlazeFI = MF . getInfo < MBlazeFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; CallingConv :: ID CallConv = MF . getFunction ( ) -> getCallingConv ( ) ; bool requiresRA = CallConv == CallingConv :: MBLAZE_INTR ; determineFrameLayout ( MF ) ; unsigned StackSize = MFI -> getStackSize ( ) ; if ( StackSize == 0 && ! MFI -> adjustsStack ( ) && ! requiresRA ) return ; int FPOffset = MBlazeFI -> getFPStackOffset ( ) ; int RAOffset = MBlazeFI -> getRAStackOffset ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( MBlaze :: ADDIK ) , MBlaze :: R1 ) . addReg ( MBlaze :: R1 ) . addImm ( - StackSize ) ; if ( MFI -> adjustsStack ( ) || requiresRA ) { BuildMI ( MBB , MBBI , DL , TII . get ( MBlaze :: SWI ) ) . addReg ( MBlaze :: R15 ) . addReg ( MBlaze :: R1 ) . addImm ( RAOffset ) ; } if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( MBlaze :: SWI ) ) . addReg ( MBlaze :: R19 ) . addReg ( MBlaze :: R1 ) . addImm ( FPOffset ) ; BuildMI ( MBB , MBBI , DL , TII . get ( MBlaze :: ADD ) , MBlaze :: R19 ) . addReg ( MBlaze :: R1 ) . addReg ( MBlaze :: R0 ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static unsigned char riscv_class_max_nregs ( reg_class_t rclass , machine_mode mode ) { if ( reg_class_subset_p ( rclass , FP_REGS ) ) return riscv_hard_regno_nregs ( FP_REG_FIRST , mode ) ; if ( reg_class_subset_p ( rclass , GR_REGS ) ) return riscv_hard_regno_nregs ( GP_REG_FIRST , mode ) ; return 0 ; } </s>


<s> std :: pair < const TargetRegisterClass * , uint8_t > ARMTargetLowering :: findRepresentativeClass ( MVT VT ) const { const TargetRegisterClass * RRC = nullptr ; uint8_t Cost = 1 ; switch ( VT . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( VT ) ; case MVT :: f32 : case MVT :: f64 : case MVT :: v8i8 : case MVT :: v4i16 : case MVT :: v2i32 : case MVT :: v1i64 : case MVT :: v2f32 : RRC = & ARM :: DPRRegClass ; if ( Subtarget -> useNEONForSinglePrecisionFP ( ) ) Cost = 2 ; break ; case MVT :: v16i8 : case MVT :: v8i16 : case MVT :: v4i32 : case MVT :: v2i64 : case MVT :: v4f32 : case MVT :: v2f64 : RRC = & ARM :: DPRRegClass ; Cost = 2 ; break ; case MVT :: v4i64 : RRC = & ARM :: DPRRegClass ; Cost = 4 ; break ; case MVT :: v8i64 : RRC = & ARM :: DPRRegClass ; Cost = 8 ; break ; } return std :: make_pair ( RRC , Cost ) ; } </s>

Return the largest legal super-reg register class of the register class for the specified type and its associated `` cost '' .


<s>
bool
HexagonInstrInfo
::
PredicateInstruction
(
MachineInstr
&
MI
,
ArrayRef
<
MachineOperand
>
Cond
)
const
{
if
(
Cond
.
empty
(
)
||
isNewValueJump
(
Cond
[
0
]
.
getImm
(
)
)
||
isEndLoopN
(
Cond
[
0
]
.
getImm
(
)
)
)
{
DEBUG
(
dbgs
(
)
<<
"\nCannot predicate:"
;
MI
.
dump
(
)
;
)
;
return
false
;
}
int
Opc
=
MI
.
getOpcode
(
)
;
assert
(
isPredicable
(
MI
)
&&
"Expected predicable instruction"
)
;
bool
invertJump
=
predOpcodeHasNot
(
Cond
)
;
MachineBasicBlock
&
B
=
*
MI
.
getParent
(
)
;
DebugLoc
DL
=
MI
.
getDebugLoc
(
)
;
unsigned
PredOpc
=
getCondOpcode
(
Opc
,
invertJump
)
;
MachineInstrBuilder
T
=
BuildMI
(
B
,
MI
,
DL
,
get
(
PredOpc
)
)
;
unsigned
NOp
=
0
,
NumOps
=
MI
.
getNumOperands
(
)
;
while
(
NOp
<
NumOps
)
{
MachineOperand
&
Op
=
MI
.
getOperand
(
NOp
)
;
if
(
!
Op
.
isReg
(
)
||
!
Op
.
isDef
(
)
||
Op
.
isImplicit
(
)
)
break
;
T
.
add
(
Op
)
;
NOp
++
;
}
unsigned
PredReg
,
PredRegPos
,
PredRegFlags
;
bool
GotPredReg
=
getPredReg
(
Cond
,
PredReg
,
PredRegPos
,
PredRegFlags
)
;
(
void
)
GotPredReg
;
assert
(
GotPredReg
)
;
T
.
addReg
(
PredReg
,
PredRegFlags
)
;
while
(
NOp
<
NumOps
)
T
.
add
(
MI
.
getOperand
(
NOp
++
)
)
;
MI
.
setDesc
(
get
(
PredOpc
)
)
;
while
(
unsigned
n
=
MI
.
getNumOperands
(
)
)
MI
.
RemoveOperand
(
n
1
)
;
for
(
unsigned
i
=
0
,
n
=
T
->
getNumOperands
(
)
;
i
<
n
;
++
i
)
MI
.
addOperand
(
T
->
getOperand
(
i
)
)
;
MachineBasicBlock
::
instr_iterator
TI
=
T
->
getIterator
(
)
;
B
.
erase
(
TI
)
;
MachineRegisterInfo
&
MRI
=
B
.
getParent
(
)
->
getRegInfo
(
)
;
MRI
.
clearKillFlags
(
PredReg
)
;
return
true
;
}
</s>

Convert the instruction into a predicated instruction .


"\n======\nTARGET_LEGITIMATE_ADDRESS_P, mode = %s, strict = %d"

Implementation of TARGET_LEGITIMATE_ADDRESS_P .


<s> std :: pair < int64_t , int64_t > SIInstrInfo :: splitFlatOffset ( int64_t COffsetVal , unsigned AddrSpace , bool IsSigned ) const { int64_t RemainderOffset = COffsetVal ; int64_t ImmField = 0 ; const unsigned NumBits = AMDGPU :: getNumFlatOffsetBits ( ST , IsSigned ) ; if ( IsSigned ) { int64_t D = 1LL << ( NumBits - 1 ) ; RemainderOffset = ( COffsetVal / D ) * D ; ImmField = COffsetVal - RemainderOffset ; } else if ( COffsetVal >= 0 ) { ImmField = COffsetVal & maskTrailingOnes < uint64_t > ( NumBits ) ; RemainderOffset = COffsetVal - ImmField ; } assert ( isLegalFLATOffset ( ImmField , AddrSpace , IsSigned ) ) ; assert ( RemainderOffset + ImmField == COffsetVal ) ; return { ImmField , RemainderOffset } ; } </s>

Split COffsetVal into { immediate offset field , remainder offset } values .


<s> SMLoc getStartLoc ( ) const { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> bool X86InstrInfo :: analyzeCompare ( const MachineInstr & MI , Register & SrcReg , Register & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI . getOpcode ( ) ) { default : break ; case X86 :: CMP64ri32 : case X86 :: CMP64ri8 : case X86 :: CMP32ri : case X86 :: CMP32ri8 : case X86 :: CMP16ri : case X86 :: CMP16ri8 : case X86 :: CMP8ri : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; if ( MI . getOperand ( 1 ) . isImm ( ) ) { CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 1 ) . getImm ( ) ; } else { CmpMask = CmpValue = 0 ; } return true ; case X86 :: SUB64rm : case X86 :: SUB32rm : case X86 :: SUB16rm : case X86 :: SUB8rm : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = 0 ; CmpValue = 0 ; return true ; case X86 :: SUB64rr : case X86 :: SUB32rr : case X86 :: SUB16rr : case X86 :: SUB8rr : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 2 ) . getReg ( ) ; CmpMask = 0 ; CmpValue = 0 ; return true ; case X86 :: SUB64ri32 : case X86 :: SUB64ri8 : case X86 :: SUB32ri : case X86 :: SUB32ri8 : case X86 :: SUB16ri : case X86 :: SUB16ri8 : case X86 :: SUB8ri : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; if ( MI . getOperand ( 2 ) . isImm ( ) ) { CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 2 ) . getImm ( ) ; } else { CmpMask = CmpValue = 0 ; } return true ; case X86 :: CMP64rr : case X86 :: CMP32rr : case X86 :: CMP16rr : case X86 :: CMP8rr : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 1 ) . getReg ( ) ; CmpMask = 0 ; CmpValue = 0 ; return true ; case X86 :: TEST8rr : case X86 :: TEST16rr : case X86 :: TEST32rr : case X86 :: TEST64rr : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; if ( MI . getOperand ( 1 ) . getReg ( ) != SrcReg ) return false ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> static unsigned int h8300_classify_operand ( rtx op , int size , enum h8300_operand_class * class ) { enum h8300_operand_class dummy ; if ( class == 0 ) class = & dummy ; if ( CONSTANT_P ( op ) ) { * class = H8OP_IMMEDIATE ; if ( size == 1 ) return 0 ; if ( TARGET_H8300SX && size == 4 && GET_CODE ( op ) == CONST_INT && IN_RANGE ( INTVAL ( op ) , 0 , 0xffff ) ) return 2 ; return size ; } else if ( GET_CODE ( op ) == MEM ) { op = XEXP ( op , 0 ) ; if ( CONSTANT_P ( op ) ) { * class = H8OP_MEM_ABSOLUTE ; return h8300_constant_length ( op ) ; } else if ( GET_CODE ( op ) == PLUS && CONSTANT_P ( XEXP ( op , 1 ) ) ) { * class = H8OP_MEM_COMPLEX ; return h8300_displacement_length ( op , size ) ; } else if ( GET_RTX_CLASS ( GET_CODE ( op ) ) == RTX_AUTOINC ) { * class = H8OP_MEM_COMPLEX ; return 0 ; } else if ( register_operand ( op , VOIDmode ) ) { * class = H8OP_MEM_BASE ; return 0 ; } } gcc_assert ( register_operand ( op , VOIDmode ) ) ; * class = H8OP_REGISTER ; return 0 ; } </s>

Store the class of operand OP in * CLASS and return the length of any extra operand fields . SIZE is the number of bytes in OP . CLASS can be null if only the length is needed .


<s>
Register
SparcTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
LLT
VT
,
const
MachineFunction
&
MF
)
const
{
Register
Reg
=
StringSwitch
<
Register
>
(
RegName
)
.
Case
(
"i0"
,
SP
::
I0
)
.
Case
(
"i1"
,
SP
::
I1
)
.
Case
(
"i2"
,
SP
::
I2
)
.
Case
(
"i3"
,
SP
::
I3
)
.
Case
(
"i4"
,
SP
::
I4
)
.
Case
(
"i5"
,
SP
::
I5
)
.
Case
(
"i6"
,
SP
::
I6
)
.
Case
(
"i7"
,
SP
::
I7
)
.
Case
(
"o0"
,
SP
::
O0
)
.
Case
(
"o1"
,
SP
::
O1
)
.
Case
(
"o2"
,
SP
::
O2
)
.
Case
(
"o3"
,
SP
::
O3
)
.
Case
(
"o4"
,
SP
::
O4
)
.
Case
(
"o5"
,
SP
::
O5
)
.
Case
(
"o6"
,
SP
::
O6
)
.
Case
(
"o7"
,
SP
::
O7
)
.
Case
(
"l0"
,
SP
::
L0
)
.
Case
(
"l1"
,
SP
::
L1
)
.
Case
(
"l2"
,
SP
::
L2
)
.
Case
(
"l3"
,
SP
::
L3
)
.
Case
(
"l4"
,
SP
::
L4
)
.
Case
(
"l5"
,
SP
::
L5
)
.
Case
(
"l6"
,
SP
::
L6
)
.
Case
(
"l7"
,
SP
::
L7
)
.
Case
(
"g0"
,
SP
::
G0
)
.
Case
(
"g1"
,
SP
::
G1
)
.
Case
(
"g2"
,
SP
::
G2
)
.
Case
(
"g3"
,
SP
::
G3
)
.
Case
(
"g4"
,
SP
::
G4
)
.
Case
(
"g5"
,
SP
::
G5
)
.
Case
(
"g6"
,
SP
::
G6
)
.
Case
(
"g7"
,
SP
::
G7
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> static int supersparc_adjust_cost ( rtx_insn * insn , rtx link , rtx_insn * dep_insn , int cost ) { enum attr_type insn_type ; if ( ! recog_memoized ( insn ) ) return 0 ; insn_type = get_attr_type ( insn ) ; if ( REG_NOTE_KIND ( link ) == 0 ) { if ( insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD ) return cost + 3 ; if ( insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE ) { rtx pat = PATTERN ( insn ) ; rtx dep_pat = PATTERN ( dep_insn ) ; if ( GET_CODE ( pat ) != SET || GET_CODE ( dep_pat ) != SET ) return cost ; if ( rtx_equal_p ( SET_DEST ( dep_pat ) , SET_SRC ( pat ) ) ) return cost ; return cost + 3 ; } if ( insn_type == TYPE_SHIFT ) return cost + 3 ; } else { if ( insn_type == TYPE_IALU || insn_type == TYPE_SHIFT ) return 0 ; } return cost ; } </s>

Adjust the cost of a scheduling dependency . Return the new cost of a dependency LINK or INSN on DEP_INSN . COST is the current cost .


<s> void VideocoreInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot ) { printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> XCoreSubtarget :: XCoreSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : XCoreGenSubtargetInfo ( TT , CPU , CPU , FS ) , InstrInfo ( ) , FrameLowering ( * this ) , TLInfo ( TM , * this ) , TSInfo ( ) { } </s>

This constructor initializes the data members to match that of the specified triple .


"Only floating point immediates are supported at the moment."


<s> virtual bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , const BranchProbability & Probability ) const { const MCInstrDesc & MCID = prior ( MBB . end ( ) ) -> getDesc ( ) ; if ( MCID . isReturn ( ) || MCID . isCall ( ) ) return false ; return NumCycles <= 4 ; } </s>

Return true if it 's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion .


<s> unsigned ARMBaseInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case ARM :: LDRrs : case ARM :: t2LDRs : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isReg ( ) && MI -> getOperand ( 3 ) . isImm ( ) && MI -> getOperand ( 2 ) . getReg ( ) == 0 && MI -> getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: LDRi12 : case ARM :: t2LDRi12 : case ARM :: tLDRspi : case ARM :: VLDRD : case ARM :: VLDRS : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VLD1q64 : case ARM :: VLD1d64TPseudo : case ARM :: VLD1d64QPseudo : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VLDMQIA : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> bool isImm ( int64_t MinValue , int64_t MaxValue ) const { return Kind == KindImm && inRange ( Imm , MinValue , MaxValue ) ; } </s>


<s> static const char * mips_sync_insn2_template ( enum attr_sync_insn2 type ) { switch ( type ) { case SYNC_INSN2_NOP : gcc_unreachable ( ) ; case SYNC_INSN2_AND : return "and\t%0,%1,%z2" ; case SYNC_INSN2_XOR : return "xor\t%0,%1,%z2" ; case SYNC_INSN2_NOT : return "nor\t%0,%1,%." ; } gcc_unreachable ( ) ; } </s>

Return the asm template associated with sync_insn2 value TYPE .


<s>
unsigned
assignCustomValue
(
const
ARMCallLowering
::
ArgInfo
&
Arg
,
ArrayRef
<
CCValAssign
>
VAs
)
override
{
CCValAssign
VA
=
VAs
[
0
]
;
assert
(
VA
.
needsCustom
(
)
&&
"Value doesn't need custom handling"
)
;
assert
(
VA
.
getValVT
(
)
==
MVT
::
f64
&&
"Unsupported type"
)
;
CCValAssign
NextVA
=
VAs
[
1
]
;
assert
(
NextVA
.
needsCustom
(
)
&&
"Value doesn't need custom handling"
)
;
assert
(
NextVA
.
getValVT
(
)
==
MVT
::
f64
&&
"Unsupported type"
)
;
assert
(
VA
.
getValNo
(
)
==
NextVA
.
getValNo
(
)
&&
"Values belong to different arguments"
)
;
assert
(
VA
.
isRegLoc
(
)
&&
"Value should be in reg"
)
;
assert
(
NextVA
.
isRegLoc
(
)
&&
"Value should be in reg"
)
;
unsigned
NewRegs
[
]
=
{
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
32
)
)
,
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
32
)
)
}
;
assignValueToReg
(
NewRegs
[
0
]
,
VA
.
getLocReg
(
)
,
VA
)
;
assignValueToReg
(
NewRegs
[
1
]
,
NextVA
.
getLocReg
(
)
,
NextVA
)
;
bool
IsLittle
=
MIRBuilder
.
getMF
(
)
.
getSubtarget
<
ARMSubtarget
>
(
)
.
isLittle
(
)
;
if
(
!
IsLittle
)
std
::
swap
(
NewRegs
[
0
]
,
NewRegs
[
1
]
)
;
MIRBuilder
.
buildMerge
(
Arg
.
Reg
,
NewRegs
)
;
return
1
;
}
</s>

Handle custom values , which may be passed into one or more of VAs .


<s> void GCNSubtarget :: adjustSchedDependency ( SUnit * Def , int DefOpIdx , SUnit * Use , int UseOpIdx , SDep & Dep ) const { if ( Dep . getKind ( ) != SDep :: Kind :: Data || ! Dep . getReg ( ) || ! Def -> isInstr ( ) || ! Use -> isInstr ( ) ) return ; MachineInstr * DefI = Def -> getInstr ( ) ; MachineInstr * UseI = Use -> getInstr ( ) ; if ( DefI -> isBundle ( ) ) { const SIRegisterInfo * TRI = getRegisterInfo ( ) ; auto Reg = Dep . getReg ( ) ; MachineBasicBlock :: const_instr_iterator I ( DefI -> getIterator ( ) ) ; MachineBasicBlock :: const_instr_iterator E ( DefI -> getParent ( ) -> instr_end ( ) ) ; unsigned Lat = 0 ; for ( ++ I ; I != E && I -> isBundledWithPred ( ) ; ++ I ) { if ( I -> modifiesRegister ( Reg , TRI ) ) Lat = InstrInfo . getInstrLatency ( getInstrItineraryData ( ) , * I ) ; else if ( Lat ) -- Lat ; } Dep . setLatency ( Lat ) ; } else if ( UseI -> isBundle ( ) ) { const SIRegisterInfo * TRI = getRegisterInfo ( ) ; auto Reg = Dep . getReg ( ) ; MachineBasicBlock :: const_instr_iterator I ( UseI -> getIterator ( ) ) ; MachineBasicBlock :: const_instr_iterator E ( UseI -> getParent ( ) -> instr_end ( ) ) ; unsigned Lat = InstrInfo . getInstrLatency ( getInstrItineraryData ( ) , * DefI ) ; for ( ++ I ; I != E && I -> isBundledWithPred ( ) && Lat ; ++ I ) { if ( I -> readsRegister ( Reg , TRI ) ) break ; -- Lat ; } Dep . setLatency ( Lat ) ; } } </s>

Perform target specific adjustments to the latency of a schedule dependency .


<s> void MipsPassConfig :: addPreRegAlloc ( ) { addPass ( createMipsOptimizePICCallPass ( getMipsTargetMachine ( ) ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


"Tail call for extern symbol not yet supported."

Targets should implement this to emit instructions .


<s> void PPCFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const PPCInstrInfo & TII = * static_cast < const PPCInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && I -> getOpcode ( ) == PPC :: ADJCALLSTACKUP ) { if ( int CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { bool is64Bit = Subtarget . isPPC64 ( ) ; CalleeAmt *= - 1 ; unsigned StackReg = is64Bit ? PPC :: X1 : PPC :: R1 ; unsigned TmpReg = is64Bit ? PPC :: X0 : PPC :: R0 ; unsigned ADDIInstr = is64Bit ? PPC :: ADDI8 : PPC :: ADDI ; unsigned ADDInstr = is64Bit ? PPC :: ADD8 : PPC :: ADD4 ; unsigned LISInstr = is64Bit ? PPC :: LIS8 : PPC :: LIS ; unsigned ORIInstr = is64Bit ? PPC :: ORI8 : PPC :: ORI ; MachineInstr * MI = I ; DebugLoc dl = MI -> getDebugLoc ( ) ; if ( isInt < 16 > ( CalleeAmt ) ) { BuildMI ( MBB , I , dl , TII . get ( ADDIInstr ) , StackReg ) . addReg ( StackReg , RegState :: Kill ) . addImm ( CalleeAmt ) ; } else { MachineBasicBlock :: iterator MBBI = I ; BuildMI ( MBB , MBBI , dl , TII . get ( LISInstr ) , TmpReg ) . addImm ( CalleeAmt >> 16 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ORIInstr ) , TmpReg ) . addReg ( TmpReg , RegState :: Kill ) . addImm ( CalleeAmt & 0xFFFF ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ADDInstr ) , StackReg ) . addReg ( StackReg , RegState :: Kill ) . addReg ( TmpReg ) ; } } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool MipsSEFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return isInt < 16 > ( MFI . getMaxCallFrameSize ( ) + getStackAlignment ( ) ) && ! MFI . hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> void arm_reset_previous_fndecl ( void ) { arm_previous_fndecl = NULL_TREE ; } </s>


<s> StringRef getPassName ( ) const override { return "AArch64PostLegalizerCombiner" ; } </s>

getPassName - Return a nice clean name for a pass .


<s> static bool mem_ok_for_ldd_std ( rtx mem , rtx * base , rtx * offset ) { rtx addr ; gcc_assert ( base != NULL && offset != NULL ) ; if ( side_effects_p ( mem ) ) return false ; if ( GET_CODE ( mem ) == SUBREG ) return false ; gcc_assert ( MEM_P ( mem ) ) ; * offset = const0_rtx ; addr = XEXP ( mem , 0 ) ; if ( ! arc_legitimate_address_p ( DImode , addr , reload_in_progress || reload_completed ) ) return false ; if ( REG_P ( addr ) ) { * base = addr ; return true ; } else if ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == MINUS ) { * base = XEXP ( addr , 0 ) ; * offset = XEXP ( addr , 1 ) ; return ( REG_P ( * base ) && CONST_INT_P ( * offset ) ) ; } return false ; } </s>

Helper for gen_operands_ldd_std . Returns true iff the memory operand MEM 's address contains an immediate offset from the base register and has no side effects , in which case it sets BASE and OFFSET accordingly .


<s> bool hasFP ( const MachineFunction & MF ) const override { return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> rtx mmix_return_addr_rtx ( int count , rtx frame ATTRIBUTE_UNUSED ) { return count == 0 ? ( MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS ? validize_mem ( gen_rtx_MEM ( Pmode , plus_constant ( Pmode , frame_pointer_rtx , - 16 ) ) ) : get_hard_reg_initial_val ( Pmode , MMIX_INCOMING_RETURN_ADDRESS_REGNUM ) ) : NULL_RTX ; } </s>


<s> static bool moxie_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) { if ( arg . aggregate_type_p ( ) ) return true ; unsigned HOST_WIDE_INT size = arg . type_size_in_bytes ( ) ; return size > 4 * 6 ; } </s>

Return non-zero if the function argument described by TYPE is to be passed by reference .


<s> const InstrItineraryData & getInstrItineraryData ( ) const { return InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s>
const
char
*
getPassName
(
)
const
{
return
"R600 Emit Clause Markers Pass"
;
}
</s>


<s> bool TVMTargetLowering :: allowsMisalignedMemoryAccesses ( EVT , unsigned , unsigned , bool * ) const { return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> void print_operand_address ( FILE * file , rtx addr ) { visium_output_address ( file , QImode , addr ) ; } </s>

Print the operand address represented by the rtx addr


<s> void fma_forest :: merge_forest ( fma_forest * other_forest ) { std :: list < fma_root_node * > * other_roots ; std :: list < fma_root_node * > :: iterator other_root_iter ; if ( this == other_forest ) return ; other_roots = other_forest -> m_roots ; for ( other_root_iter = other_roots -> begin ( ) ; other_root_iter != other_roots -> end ( ) ; other_root_iter ++ ) ( * other_root_iter ) -> set_forest ( this ) ; this -> m_globals -> remove_forest ( other_forest ) ; this -> m_roots -> splice ( this -> m_roots -> begin ( ) , * other_roots ) ; delete other_forest ; this -> m_nb_nodes += other_forest -> m_nb_nodes ; } </s>

Merge REF_FOREST and OTHER_FOREST together , making REF_FOREST the canonical fma_forest object to represent both .


<s>
bool
AArch64AddressTypePromotion
::
runOnFunction
(
Function
&
F
)
{
if
(
skipFunction
(
F
)
)
return
false
;
if
(
!
EnableAddressTypePromotion
||
F
.
isDeclaration
(
)
)
return
false
;
Func
=
&
F
;
ConsideredSExtType
=
Type
::
getInt64Ty
(
Func
->
getContext
(
)
)
;
DEBUG
(
dbgs
(
)
<<
"*** "
<<
getPassName
(
)
<<
": "
<<
Func
->
getName
(
)
<<
'\n'
)
;
Instructions
SExtInsts
;
analyzeSExtension
(
SExtInsts
)
;
return
propagateSignExtension
(
SExtInsts
)
;
}
</s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool AArch64LoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { if ( skipFunction ( * Fn . getFunction ( ) ) ) return false ; Subtarget = & static_cast < const AArch64Subtarget & > ( Fn . getSubtarget ( ) ) ; TII = static_cast < const AArch64InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; TRI = Subtarget -> getRegisterInfo ( ) ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; ModifiedRegs . resize ( TRI -> getNumRegs ( ) ) ; UsedRegs . resize ( TRI -> getNumRegs ( ) ) ; bool Modified = false ; bool enableNarrowZeroStOpt = ! Subtarget -> requiresStrictAlign ( ) ; for ( auto & MBB : Fn ) Modified |= optimizeBlock ( MBB , enableNarrowZeroStOpt ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool loongarch_split_move_insn_p ( rtx dest , rtx src ) { return loongarch_split_move_p ( dest , src ) ; } </s>

Return true if a move from SRC to DEST in INSN should be split .


<s> static void sparc_init_builtins ( void ) { if ( TARGET_VIS ) sparc_vis_init_builtins ( ) ; } </s>

Implement the TARGET_INIT_BUILTINS target hook . Create builtin functions for special SPARC instructions .


<s> static bool save_local_or_in_reg_p ( unsigned int regno , int leaf_function ) { if ( ! call_used_regs [ regno ] && df_regs_ever_live_p ( regno ) ) return true ; if ( regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed ) return true ; if ( regno == RETURN_ADDR_REGNUM && return_addr_reg_needed_p ( leaf_function ) ) return true ; if ( regno == GLOBAL_OFFSET_TABLE_REGNUM && got_register_rtx ) return true ; if ( crtl -> accesses_prior_frames && ( regno == HARD_FRAME_POINTER_REGNUM || regno == RETURN_ADDR_REGNUM ) ) return true ; return false ; } </s>

Return whether REGNO , a local or in register , must be saved/restored .


<s> bool X86TargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { const IntrinsicData * IntrData = getIntrinsicWithChain ( Intrinsic ) ; if ( ! IntrData ) return false ; Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . flags = MachineMemOperand :: MONone ; Info . offset = 0 ; switch ( IntrData -> Type ) { case EXPAND_FROM_MEM : { Info . ptrVal = I . getArgOperand ( 0 ) ; Info . memVT = MVT :: getVT ( I . getType ( ) ) ; Info . align = 1 ; Info . flags |= MachineMemOperand :: MOLoad ; break ; } case COMPRESS_TO_MEM : { Info . ptrVal = I . getArgOperand ( 0 ) ; Info . memVT = MVT :: getVT ( I . getArgOperand ( 1 ) -> getType ( ) ) ; Info . align = 1 ; Info . flags |= MachineMemOperand :: MOStore ; break ; } case TRUNCATE_TO_MEM_VI8 : case TRUNCATE_TO_MEM_VI16 : case TRUNCATE_TO_MEM_VI32 : { Info . ptrVal = I . getArgOperand ( 0 ) ; MVT VT = MVT :: getVT ( I . getArgOperand ( 1 ) -> getType ( ) ) ; MVT ScalarVT = MVT :: INVALID_SIMPLE_VALUE_TYPE ; if ( IntrData -> Type == TRUNCATE_TO_MEM_VI8 ) ScalarVT = MVT :: i8 ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI16 ) ScalarVT = MVT :: i16 ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI32 ) ScalarVT = MVT :: i32 ; Info . memVT = MVT :: getVectorVT ( ScalarVT , VT . getVectorNumElements ( ) ) ; Info . align = 1 ; Info . flags |= MachineMemOperand :: MOStore ; break ; } default : return false ; } return true ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> void MipsOutgoingValueHandler :: assignValueToAddress ( Register ValVReg , const CCValAssign & VA ) { MachineMemOperand * MMO ; Register Addr = getStackAddress ( VA , MMO ) ; Register ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildStore ( ExtReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


"Trying RISCV32Only_16 table (16-bit Instruction):\n"

"Trying RISCV_C table (16-bit Instruction):\n"

Returns the disassembly of a single instruction .


<s> bool X86InstrInfo :: analyzeCompare ( const MachineInstr & MI , unsigned & SrcReg , unsigned & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI . getOpcode ( ) ) { default : break ; case X86 :: CMP64ri32 : case X86 :: CMP64ri8 : case X86 :: CMP32ri : case X86 :: CMP32ri8 : case X86 :: CMP16ri : case X86 :: CMP16ri8 : case X86 :: CMP8ri : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; if ( MI . getOperand ( 1 ) . isImm ( ) ) { CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 1 ) . getImm ( ) ; } else { CmpMask = CmpValue = 0 ; } return true ; case X86 :: SUB64rm : case X86 :: SUB32rm : case X86 :: SUB16rm : case X86 :: SUB8rm : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = 0 ; CmpValue = 0 ; return true ; case X86 :: SUB64rr : case X86 :: SUB32rr : case X86 :: SUB16rr : case X86 :: SUB8rr : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 2 ) . getReg ( ) ; CmpMask = 0 ; CmpValue = 0 ; return true ; case X86 :: SUB64ri32 : case X86 :: SUB64ri8 : case X86 :: SUB32ri : case X86 :: SUB32ri8 : case X86 :: SUB16ri : case X86 :: SUB16ri8 : case X86 :: SUB8ri : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; if ( MI . getOperand ( 2 ) . isImm ( ) ) { CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 2 ) . getImm ( ) ; } else { CmpMask = CmpValue = 0 ; } return true ; case X86 :: CMP64rr : case X86 :: CMP32rr : case X86 :: CMP16rr : case X86 :: CMP8rr : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 1 ) . getReg ( ) ; CmpMask = 0 ; CmpValue = 0 ; return true ; case X86 :: TEST8rr : case X86 :: TEST16rr : case X86 :: TEST32rr : case X86 :: TEST64rr : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; if ( MI . getOperand ( 1 ) . getReg ( ) != SrcReg ) return false ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> int SIInstrInfo :: pseudoToMCOpcode ( int Opcode ) const { SIEncodingFamily Gen = subtargetEncodingFamily ( ST ) ; if ( ( get ( Opcode ) . TSFlags & SIInstrFlags :: renamedInGFX9 ) != 0 && ST . getGeneration ( ) == AMDGPUSubtarget :: GFX9 ) Gen = SIEncodingFamily :: GFX9 ; if ( ST . hasUnpackedD16VMem ( ) && ( get ( Opcode ) . TSFlags & SIInstrFlags :: D16Buf ) ) Gen = SIEncodingFamily :: GFX80 ; if ( get ( Opcode ) . TSFlags & SIInstrFlags :: SDWA ) { switch ( ST . getGeneration ( ) ) { default : Gen = SIEncodingFamily :: SDWA ; break ; case AMDGPUSubtarget :: GFX9 : Gen = SIEncodingFamily :: SDWA9 ; break ; case AMDGPUSubtarget :: GFX10 : Gen = SIEncodingFamily :: SDWA10 ; break ; } } int MCOp = AMDGPU :: getMCOpcode ( Opcode , Gen ) ; if ( MCOp == - 1 ) return Opcode ; if ( MCOp == ( uint16_t ) - 1 ) return - 1 ; return MCOp ; } </s>

Return a target-specific opcode if Opcode is a pseudo instruction .


<s>
const
char
*
output_addsi3
(
rtx
*
operands
)
{
if
(
!
operands_match_p
(
operands
[
0
]
,
operands
[
1
]
)
)
{
if
(
!
ADDRESS_REG_P
(
operands
[
1
]
)
)
{
rtx
tmp
=
operands
[
1
]
;
operands
[
1
]
=
operands
[
2
]
;
operands
[
2
]
=
tmp
;
}
if
(
GET_CODE
(
operands
[
2
]
)
==
CONST_INT
&&
(
INTVAL
(
operands
[
2
]
)
<
32768
||
INTVAL
(
operands
[
2
]
)
>
32767
)
)
return
"move%.l %2,%0\n\tadd%.l %1,%0"
;
if
(
GET_CODE
(
operands
[
2
]
)
==
REG
)
return
MOTOROLA
"lea (%1,%2.l),%0"
:
"lea %1@(0,%2:l),%0"
;
return
MOTOROLA
"lea (%c2,%1),%0"
:
"lea %1@(%c2),%0"
;
}
if
(
GET_CODE
(
operands
[
2
]
)
==
CONST_INT
)
{
if
(
INTVAL
(
operands
[
2
]
)
>
0
&&
INTVAL
(
operands
[
2
]
)
<=
8
)
return
"addq%.l %2,%0"
;
if
(
INTVAL
(
operands
[
2
]
)
<
0
&&
INTVAL
(
operands
[
2
]
)
>=
8
)
{
operands
[
2
]
=
GEN_INT
(
INTVAL
(
operands
[
2
]
)
)
;
return
"subq%.l %2,%0"
;
}
if
(
TARGET_CPU32
&&
REG_P
(
operands
[
0
]
)
)
{
if
(
INTVAL
(
operands
[
2
]
)
>
8
&&
INTVAL
(
operands
[
2
]
)
<=
16
)
{
operands
[
2
]
=
GEN_INT
(
INTVAL
(
operands
[
2
]
)
8
)
;
return
"addq%.l #8,%0\n\taddq%.l %2,%0"
;
}
if
(
INTVAL
(
operands
[
2
]
)
<
8
&&
INTVAL
(
operands
[
2
]
)
>=
16
)
{
operands
[
2
]
=
GEN_INT
(
INTVAL
(
operands
[
2
]
)
8
)
;
return
"subq%.l #8,%0\n\tsubq%.l %2,%0"
;
}
}
if
(
ADDRESS_REG_P
(
operands
[
0
]
)
&&
INTVAL
(
operands
[
2
]
)
>=
0x8000
&&
INTVAL
(
operands
[
2
]
)
<
0x8000
)
{
if
(
TARGET_68040
)
return
"add%.w %2,%0"
;
else
return
MOTOROLA
"lea (%c2,%0),%0"
:
"lea %0@(%c2),%0"
;
}
}
return
"add%.l %2,%0"
;
}
</s>

Output assembler code to perform a 32 bit 3 operand add .


<s>
static
void
rs6000_xcoff_file_end
(
void
)
{
text_section
(
)
;
fputs
(
"_section_.text:\n"
,
asm_out_file
)
;
data_section
(
)
;
fputs
(
TARGET_32BIT
"\t.long _section_.text\n"
:
"\t.llong _section_.text\n"
,
asm_out_file
)
;
}
</s>

Output at end of assembler file . On the RS/6000 , referencing data should automatically pull in text .


<s> TargetLowering :: ConstraintWeight SystemZTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'a' : case 'd' : case 'h' : case 'r' : if ( CallOperandVal -> getType ( ) -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatingPointTy ( ) ) weight = CW_Register ; break ; case 'I' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isUInt < 8 > ( C -> getZExtValue ( ) ) ) weight = CW_Constant ; break ; case 'J' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isUInt < 12 > ( C -> getZExtValue ( ) ) ) weight = CW_Constant ; break ; case 'K' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isInt < 16 > ( C -> getSExtValue ( ) ) ) weight = CW_Constant ; break ; case 'L' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isInt < 20 > ( C -> getSExtValue ( ) ) ) weight = CW_Constant ; break ; case 'M' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( C -> getZExtValue ( ) == 0x7fffffff ) weight = CW_Constant ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s>
void
X86IntelInstPrinter
::
printPCRelImm
(
const
MCInst
*
MI
,
unsigned
OpNo
,
raw_ostream
&
O
)
{
const
MCOperand
&
Op
=
MI
->
getOperand
(
OpNo
)
;
if
(
Op
.
isImm
(
)
)
O
<<
Op
.
getImm
(
)
;
else
{
assert
(
Op
.
isExpr
(
)
&&
"unknown pcrel immediate operand"
)
;
const
MCConstantExpr
*
BranchTarget
=
dyn_cast
<
MCConstantExpr
>
(
Op
.
getExpr
(
)
)
;
int64_t
Address
;
if
(
BranchTarget
&&
BranchTarget
->
EvaluateAsAbsolute
(
Address
)
)
{
O
<<
"0x"
;
O
.
write_hex
(
Address
)
;
}
else
{
O
<<
*
Op
.
getExpr
(
)
;
}
}
}
</s>


<s> static rtx_insn * nds32_md_asm_adjust ( vec < rtx > & outputs ATTRIBUTE_UNUSED , vec < rtx > & inputs ATTRIBUTE_UNUSED , vec < machine_mode > & input_modes ATTRIBUTE_UNUSED , vec < const char * > & constraints ATTRIBUTE_UNUSED , vec < rtx > & clobbers , HARD_REG_SET & clobbered_regs ) { if ( ! flag_inline_asm_r15 ) { clobbers . safe_push ( gen_rtx_REG ( SImode , TA_REGNUM ) ) ; SET_HARD_REG_BIT ( clobbered_regs , TA_REGNUM ) ; } return NULL ; } </s>


<s> bool X86AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < X86Subtarget > ( ) ; SMShadowTracker . startFunction ( MF ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Intrn = MF . getFunction ( ) -> hasInternalLinkage ( ) ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Intrn ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; return false ; } </s>


<s> bool RISCVInstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF , bool OutlineFromLinkOnceODRs ) const { const Function & F = MF . getFunction ( ) ; if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) ) return false ; if ( F . hasSection ( ) ) return false ; return true ; } </s>

Return true if the function can safely be outlined from .


<s> TargetPassConfig * Cpu0TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new Cpu0PassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> void SparcInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & O ) { if ( ! printAliasInstr ( MI , STI , O ) && ! printSparcAliasInstr ( MI , STI , O ) ) printInstruction ( MI , Address , STI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> SDValue AMDGPUTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & DL , SelectionDAG & DAG ) const { return DAG . getNode ( AMDGPUISD :: ENDPGM , DL , MVT :: Other , Chain ) ; } </s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .

AMDGPU AMDGPU ISD::OutputArg AMDGPUISD::ENDPGM MVT::Other


<s>
void
output_dbcc_and_branch
(
rtx
*
operands
)
{
switch
(
GET_CODE
(
operands
[
3
]
)
)
{
case
EQ
:
output_asm_insn
(
"dbeq %0,%l1\n\tjeq %l2"
,
operands
)
;
break
;
case
NE
:
output_asm_insn
(
"dbne %0,%l1\n\tjne %l2"
,
operands
)
;
break
;
case
GT
:
output_asm_insn
(
"dbgt %0,%l1\n\tjgt %l2"
,
operands
)
;
break
;
case
GTU
:
output_asm_insn
(
"dbhi %0,%l1\n\tjhi %l2"
,
operands
)
;
break
;
case
LT
:
output_asm_insn
(
"dblt %0,%l1\n\tjlt %l2"
,
operands
)
;
break
;
case
LTU
:
output_asm_insn
(
"dbcs %0,%l1\n\tjcs %l2"
,
operands
)
;
break
;
case
GE
:
output_asm_insn
(
"dbge %0,%l1\n\tjge %l2"
,
operands
)
;
break
;
case
GEU
:
output_asm_insn
(
"dbcc %0,%l1\n\tjcc %l2"
,
operands
)
;
break
;
case
LE
:
output_asm_insn
(
"dble %0,%l1\n\tjle %l2"
,
operands
)
;
break
;
case
LEU
:
output_asm_insn
(
"dbls %0,%l1\n\tjls %l2"
,
operands
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
switch
(
GET_MODE
(
operands
[
0
]
)
)
{
case
E_SImode
:
output_asm_insn
(
"clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1"
,
operands
)
;
break
;
case
E_HImode
:
break
;
default
:
gcc_unreachable
(
)
;
}
}
</s>

Output a dbCC ; jCC sequence . Note we do not handle the floating point version of this sequence ( Fdbcc ) . We also do not handle alternative conditions when CC_NO_OVERFLOW is set . It is assumed that valid_dbcc_comparison_p and flags_in_68881 will kick those out before we get here .


<s> virtual const BPFRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> rtx swap_endian_selector_for_mode ( machine_mode mode ) { unsigned int swap1 [ 16 ] = { 15 , 14 , 13 , 12 , 11 , 10 , 9 , 8 , 7 , 6 , 5 , 4 , 3 , 2 , 1 , 0 } ; unsigned int swap2 [ 16 ] = { 7 , 6 , 5 , 4 , 3 , 2 , 1 , 0 , 15 , 14 , 13 , 12 , 11 , 10 , 9 , 8 } ; unsigned int swap4 [ 16 ] = { 3 , 2 , 1 , 0 , 7 , 6 , 5 , 4 , 11 , 10 , 9 , 8 , 15 , 14 , 13 , 12 } ; unsigned int swap8 [ 16 ] = { 1 , 0 , 3 , 2 , 5 , 4 , 7 , 6 , 9 , 8 , 11 , 10 , 13 , 12 , 15 , 14 } ; unsigned int * swaparray , i ; rtx perm [ 16 ] ; switch ( mode ) { case E_V1TImode : swaparray = swap1 ; break ; case E_V2DFmode : case E_V2DImode : swaparray = swap2 ; break ; case E_V4SFmode : case E_V4SImode : swaparray = swap4 ; break ; case E_V8HImode : swaparray = swap8 ; break ; default : gcc_unreachable ( ) ; } for ( i = 0 ; i < 16 ; ++ i ) perm [ i ] = GEN_INT ( swaparray [ i ] ) ; return force_reg ( V16QImode , gen_rtx_CONST_VECTOR ( V16QImode , gen_rtvec_v ( 16 , perm ) ) ) ; } </s>

Return the permutation index for the swapping on the given vector mode . Note that the permutation index is correspondingly generated by endianness , it should be used by direct vector permutation .


<s> bool Error ( SMLoc L , const Twine & Msg , SMRange Range = None , bool MatchingInlineAsm = false ) { MCAsmParser & Parser = getParser ( ) ; if ( MatchingInlineAsm ) { if ( ! getLexer ( ) . isAtStartOfStatement ( ) ) Parser . eatToEndOfStatement ( ) ; return false ; } return Parser . Error ( L , Msg , Range ) ; } </s>

Return an error at the location L , with the message Msg .


<s> static rtx riscv_emit_set ( rtx target , rtx src ) { emit_insn ( gen_rtx_SET ( target , src ) ) ; return target ; } </s>

Emit an instruction of the form ( set TARGET SRC ) .


<s>
StringRef
getPassName
(
)
const
override
{
return
"PULP Hardware Loop Fixup"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"PPC hazards don't support scoreboard lookahead"

getHazardType - Return the hazard type of emitting this node .


<s> MachinePointerInfo MipsFunctionInfo :: callPtrInfo ( MachineFunction & MF , const GlobalValue * GV ) { return MachinePointerInfo ( MF . getPSVManager ( ) . getGlobalValueCallEntry ( GV ) ) ; } </s>

Create a MachinePointerInfo that has a GlobalValuePseudoSourceValue object representing a GOT entry for a global function .


<s> bool AArch64PassConfig :: addLegalizeMachineIR ( ) { addPass ( new Legalizer ( ) ) ; return false ; } </s>

This method should install a legalize pass , which converts the instruction sequence into one that can be selected by the target .


<s> static inline rtx s390_expand_mask_and_shift ( rtx val , machine_mode mode , rtx count ) { val = expand_simple_binop ( SImode , AND , val , GEN_INT ( GET_MODE_MASK ( mode ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ; return expand_simple_binop ( SImode , ASHIFT , val , count , NULL_RTX , 1 , OPTAB_DIRECT ) ; } </s>

A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a register that holds VAL of mode MODE shifted by COUNT bits .


<s> static void Query ( const MachineInstr & MI , AliasAnalysis & AA , bool & Read , bool & Write , bool & Effects , bool & StackPointer ) { assert ( ! MI . isTerminator ( ) ) ; if ( MI . isDebugInstr ( ) || MI . isPosition ( ) ) return ; if ( MI . mayLoad ( ) && ! MI . isDereferenceableInvariantLoad ( & AA ) ) Read = true ; if ( MI . mayStore ( ) ) { Write = true ; } else if ( MI . hasOrderedMemoryRef ( ) ) { switch ( MI . getOpcode ( ) ) { case WebAssembly :: DIV_S_I32 : case WebAssembly :: DIV_S_I64 : case WebAssembly :: REM_S_I32 : case WebAssembly :: REM_S_I64 : case WebAssembly :: DIV_U_I32 : case WebAssembly :: DIV_U_I64 : case WebAssembly :: REM_U_I32 : case WebAssembly :: REM_U_I64 : case WebAssembly :: I32_TRUNC_S_F32 : case WebAssembly :: I64_TRUNC_S_F32 : case WebAssembly :: I32_TRUNC_S_F64 : case WebAssembly :: I64_TRUNC_S_F64 : case WebAssembly :: I32_TRUNC_U_F32 : case WebAssembly :: I64_TRUNC_U_F32 : case WebAssembly :: I32_TRUNC_U_F64 : case WebAssembly :: I64_TRUNC_U_F64 : break ; default : if ( ! MI . isCall ( ) ) { Write = true ; Effects = true ; } break ; } } if ( MI . hasUnmodeledSideEffects ( ) ) { switch ( MI . getOpcode ( ) ) { case WebAssembly :: DIV_S_I32 : case WebAssembly :: DIV_S_I64 : case WebAssembly :: REM_S_I32 : case WebAssembly :: REM_S_I64 : case WebAssembly :: DIV_U_I32 : case WebAssembly :: DIV_U_I64 : case WebAssembly :: REM_U_I32 : case WebAssembly :: REM_U_I64 : case WebAssembly :: I32_TRUNC_S_F32 : case WebAssembly :: I64_TRUNC_S_F32 : case WebAssembly :: I32_TRUNC_S_F64 : case WebAssembly :: I64_TRUNC_S_F64 : case WebAssembly :: I32_TRUNC_U_F32 : case WebAssembly :: I64_TRUNC_U_F32 : case WebAssembly :: I32_TRUNC_U_F64 : case WebAssembly :: I64_TRUNC_U_F64 : break ; default : Effects = true ; break ; } } if ( MI . getOpcode ( ) == WebAssembly :: GLOBAL_SET_I32 && strcmp ( MI . getOperand ( 0 ) . getSymbolName ( ) , "__stack_pointer" ) == 0 ) StackPointer = true ; if ( MI . isCall ( ) ) { unsigned CalleeOpNo = WebAssembly :: getCalleeOpNo ( MI ) ; QueryCallee ( MI , CalleeOpNo , Read , Write , Effects , StackPointer ) ; } } </s>


<s> SDNode * M680x0DAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; auto & DL = MF -> getDataLayout ( ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI -> getPointerTy ( DL ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> const HexagonLDBackend & getTarget ( ) const { return m_Target ; } </s>

getTarget - Return the target machine this machine code is compiled with