<s> bool isLegalMaskedStore ( Type * DataType , Align Alignment ) { return isLegalMaskedLoadStore ( DataType , Alignment ) ; } </s>

Return true if the target supports masked store .


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , is64bit ) , DL ( computeDataLayout ( Subtarget ) ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) { initAsmInfo ( ) ; } </s>


<s>
void
ARMInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
O
)
{
unsigned
Opcode
=
MI
->
getOpcode
(
)
;
if
(
Opcode
==
ARM
::
MOVs
)
{
const
MCOperand
&
Dst
=
MI
->
getOperand
(
0
)
;
const
MCOperand
&
MO1
=
MI
->
getOperand
(
1
)
;
const
MCOperand
&
MO2
=
MI
->
getOperand
(
2
)
;
const
MCOperand
&
MO3
=
MI
->
getOperand
(
3
)
;
O
<<
'\t'
<<
ARM_AM
::
getShiftOpcStr
(
ARM_AM
::
getSORegShOp
(
MO3
.
getImm
(
)
)
)
;
printSBitModifierOperand
(
MI
,
6
,
O
)
;
printPredicateOperand
(
MI
,
4
,
O
)
;
O
<<
'\t'
<<
getRegisterName
(
Dst
.
getReg
(
)
)
<<
", "
<<
getRegisterName
(
MO1
.
getReg
(
)
)
;
if
(
ARM_AM
::
getSORegShOp
(
MO3
.
getImm
(
)
)
==
ARM_AM
::
rrx
)
return
;
O
<<
", "
;
if
(
MO2
.
getReg
(
)
)
{
O
<<
getRegisterName
(
MO2
.
getReg
(
)
)
;
assert
(
ARM_AM
::
getSORegOffset
(
MO3
.
getImm
(
)
)
==
0
)
;
}
else
{
O
<<
"#"
<<
ARM_AM
::
getSORegOffset
(
MO3
.
getImm
(
)
)
;
}
return
;
}
if
(
(
Opcode
==
ARM
::
STMDB_UPD
||
Opcode
==
ARM
::
t2STMDB_UPD
)
&&
MI
->
getOperand
(
0
)
.
getReg
(
)
==
ARM
::
SP
)
{
O
<<
'\t'
<<
"push"
;
printPredicateOperand
(
MI
,
2
,
O
)
;
if
(
Opcode
==
ARM
::
t2STMDB_UPD
)
O
<<
".w"
;
O
<<
'\t'
;
printRegisterList
(
MI
,
4
,
O
)
;
return
;
}
if
(
(
Opcode
==
ARM
::
LDMIA_UPD
||
Opcode
==
ARM
::
t2LDMIA_UPD
)
&&
MI
->
getOperand
(
0
)
.
getReg
(
)
==
ARM
::
SP
)
{
O
<<
'\t'
<<
"pop"
;
printPredicateOperand
(
MI
,
2
,
O
)
;
if
(
Opcode
==
ARM
::
t2LDMIA_UPD
)
O
<<
".w"
;
O
<<
'\t'
;
printRegisterList
(
MI
,
4
,
O
)
;
return
;
}
if
(
(
Opcode
==
ARM
::
VSTMSDB_UPD
||
Opcode
==
ARM
::
VSTMDDB_UPD
)
&&
MI
->
getOperand
(
0
)
.
getReg
(
)
==
ARM
::
SP
)
{
O
<<
'\t'
<<
"vpush"
;
printPredicateOperand
(
MI
,
2
,
O
)
;
O
<<
'\t'
;
printRegisterList
(
MI
,
4
,
O
)
;
return
;
}
if
(
(
Opcode
==
ARM
::
VLDMSIA_UPD
||
Opcode
==
ARM
::
VLDMDIA_UPD
)
&&
MI
->
getOperand
(
0
)
.
getReg
(
)
==
ARM
::
SP
)
{
O
<<
'\t'
<<
"vpop"
;
printPredicateOperand
(
MI
,
2
,
O
)
;
O
<<
'\t'
;
printRegisterList
(
MI
,
4
,
O
)
;
return
;
}
printInstruction
(
MI
,
O
)
;
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s> bool rl78_real_insns_ok ( void ) { if ( cfun ) return cfun -> machine -> real_insns_ok ; return false ; } </s>

Predicates used in the MD patterns . This one is true when real insns may be matched , which typically means after ( or during ) the devirt pass .


<s> bool P2AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { P2FI = MF . getInfo < P2FunctionInfo > ( ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> void loongarch_expand_atomic_qihi ( union loongarch_gen_fn_ptrs generator , rtx result , rtx mem , rtx oldval , rtx newval , rtx model ) { rtx orig_addr , memsi_addr , memsi , shift , shiftsi , unshifted_mask ; rtx unshifted_mask_reg , mask , inverted_mask , si_op ; rtx res = NULL ; machine_mode mode ; mode = GET_MODE ( mem ) ; orig_addr = force_reg ( Pmode , XEXP ( mem , 0 ) ) ; memsi_addr = loongarch_force_binary ( Pmode , AND , orig_addr , force_reg ( Pmode , GEN_INT ( - 4 ) ) ) ; memsi = gen_rtx_MEM ( SImode , memsi_addr ) ; set_mem_alias_set ( memsi , ALIAS_SET_MEMORY_BARRIER ) ; MEM_VOLATILE_P ( memsi ) = MEM_VOLATILE_P ( mem ) ; shift = loongarch_force_binary ( Pmode , AND , orig_addr , GEN_INT ( 3 ) ) ; loongarch_emit_binary ( ASHIFT , shift , shift , GEN_INT ( 3 ) ) ; shiftsi = force_reg ( SImode , gen_lowpart ( SImode , shift ) ) ; unshifted_mask = GEN_INT ( GET_MODE_MASK ( mode ) ) ; unshifted_mask_reg = force_reg ( SImode , unshifted_mask ) ; mask = loongarch_force_binary ( SImode , ASHIFT , unshifted_mask_reg , shiftsi ) ; inverted_mask = gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( inverted_mask , gen_rtx_NOT ( SImode , mask ) ) ) ; if ( oldval != const0_rtx ) { oldval = convert_modes ( SImode , mode , oldval , true ) ; oldval = force_reg ( SImode , oldval ) ; oldval = loongarch_force_binary ( SImode , ASHIFT , oldval , shiftsi ) ; } if ( newval && newval != const0_rtx ) { newval = convert_modes ( SImode , mode , newval , true ) ; newval = force_reg ( SImode , newval ) ; newval = loongarch_force_binary ( SImode , ASHIFT , newval , shiftsi ) ; } if ( result ) res = gen_reg_rtx ( SImode ) ; if ( newval ) si_op = generator . fn_7 ( res , memsi , mask , inverted_mask , oldval , newval , model ) ; else if ( result ) si_op = generator . fn_6 ( res , memsi , mask , inverted_mask , oldval , model ) ; else si_op = generator . fn_5 ( memsi , mask , inverted_mask , oldval , model ) ; emit_insn ( si_op ) ; if ( result ) { loongarch_emit_binary ( AND , res , res , mask ) ; loongarch_emit_binary ( LSHIFTRT , res , res , shiftsi ) ; loongarch_emit_move ( result , gen_lowpart ( GET_MODE ( result ) , res ) ) ; } } </s>

Expand a QI or HI mode atomic memory operation . GENERATOR contains a pointer to the gen_ * function that generates the SI mode underlying atomic operation using masks that we calculate . RESULT is the return register for the operation . Its value is NULL if unused . MEM is the location of the atomic access . OLDVAL is the first operand for the operation . NEWVAL is the optional second operand for the operation . Its value is NULL if unused .


<s> void PPCFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const PPCRegisterInfo * RegInfo = static_cast < const PPCRegisterInfo * > ( Subtarget . getRegisterInfo ( ) ) ; PPCFunctionInfo * FI = MF . getInfo < PPCFunctionInfo > ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; SavedRegs . reset ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; bool isPPC64 = Subtarget . isPPC64 ( ) ; bool isDarwinABI = Subtarget . isDarwinABI ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( ) ; FPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int BPSI = FI -> getBasePointerSaveIndex ( ) ; if ( ! BPSI && RegInfo -> hasBasePointer ( MF ) ) { int BPOffset = getBasePointerSaveOffset ( ) ; BPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , BPOffset , true ) ; FI -> setBasePointerSaveIndex ( BPSI ) ; } if ( FI -> usesPICBase ( ) ) { int PBPSI = MFI . CreateFixedObject ( 4 , - 8 , true ) ; FI -> setPICBasePointerSaveIndex ( PBPSI ) ; } int TCSPDelta = 0 ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < 0 ) { MFI . CreateFixedObject ( - 1 * TCSPDelta , TCSPDelta , true ) ; } if ( ! isPPC64 && ! isDarwinABI && ( SavedRegs . test ( PPC :: CR2 ) || SavedRegs . test ( PPC :: CR3 ) || SavedRegs . test ( PPC :: CR4 ) ) ) { int FrameIdx = MFI . CreateFixedObject ( ( uint64_t ) 4 , ( int64_t ) - 4 , true ) ; FI -> setCRSpillFrameIndex ( FrameIdx ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> bool aarch64_sve_ptrue_svpattern_p ( rtx x , struct simd_immediate_info * info ) { if ( GET_CODE ( x ) != CONST ) return false ; x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) != UNSPEC || XINT ( x , 1 ) != UNSPEC_PTRUE ) return false ; if ( info ) { aarch64_svpattern pattern = ( aarch64_svpattern ) INTVAL ( XVECEXP ( x , 0 , 0 ) ) ; machine_mode pred_mode = GET_MODE ( XVECEXP ( x , 0 , 1 ) ) ; scalar_int_mode int_mode = aarch64_sve_element_int_mode ( pred_mode ) ; * info = simd_immediate_info ( int_mode , pattern ) ; } return true ; } </s>

Return true if X is an UNSPEC_PTRUE constant of the form : ( const ( unspec [ PATTERN ZERO ] UNSPEC_PTRUE ) ) where PATTERN is the svpattern as a CONST_INT and where ZERO is a zero constant of the required PTRUE mode ( which can have fewer elements than X 's mode , if zero bits are significant ) . If so , and if INFO is nonnull , describe the immediate in INFO .


<s>
bool
MipsOs16
::
runOnModule
(
Module
&
M
)
{
bool
usingMask
=
Mips32FunctionMask
.
length
(
)
>
0
;
bool
doneUsingMask
=
false
;
DEBUG
(
dbgs
(
)
<<
"Run on Module MipsOs16 \n"
<<
Mips32FunctionMask
<<
"\n"
)
;
if
(
usingMask
)
DEBUG
(
dbgs
(
)
<<
"using mask \n"
<<
Mips32FunctionMask
<<
"\n"
)
;
unsigned
int
functionIndex
=
0
;
bool
modified
=
false
;
for
(
auto
&
F
:
M
)
{
if
(
F
.
isDeclaration
(
)
)
continue
;
DEBUG
(
dbgs
(
)
<<
"Working on "
<<
F
.
getName
(
)
<<
"\n"
)
;
if
(
usingMask
)
{
if
(
!
doneUsingMask
)
{
if
(
functionIndex
==
Mips32FunctionMask
.
length
(
)
)
functionIndex
=
0
;
switch
(
Mips32FunctionMask
[
functionIndex
]
)
{
case
'1'
:
DEBUG
(
dbgs
(
)
<<
"mask forced mips32: "
<<
F
.
getName
(
)
<<
"\n"
)
;
F
.
addFnAttr
(
"nomips16"
)
;
break
;
case
'.'
:
doneUsingMask
=
true
;
break
;
default
:
break
;
}
functionIndex
++
;
}
}
else
{
if
(
needsFP
(
F
)
)
{
DEBUG
(
dbgs
(
)
<<
"os16 forced mips32: "
<<
F
.
getName
(
)
<<
"\n"
)
;
F
.
addFnAttr
(
"nomips16"
)
;
}
else
{
DEBUG
(
dbgs
(
)
<<
"os16 forced mips16: "
<<
F
.
getName
(
)
<<
"\n"
)
;
F
.
addFnAttr
(
"mips16"
)
;
}
}
}
return
modified
;
}
</s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .

Mips
Mips
Mips
0
"Run on Module MipsOs16 \n"
Mips
"\n"
"using mask \n"
Mips
"\n"
0
"Working on "
"\n"
Mips
0
Mips
"mask forced mips32: "
"\n"
"nomips16"
"os16 forced mips32: "
"\n"
"nomips16"
"os16 forced mips16: "
"\n"
"mips16"


<s> static rtx function_arg_union_value ( int size , machine_mode mode , int slotno , int regno ) { int nwords = CEIL_NWORDS ( size ) , i ; rtx regs ; if ( nwords == 0 ) return gen_rtx_REG ( mode , regno ) ; if ( slotno == SPARC_INT_ARG_MAX - 1 ) nwords = 1 ; regs = gen_rtx_PARALLEL ( mode , rtvec_alloc ( nwords ) ) ; for ( i = 0 ; i < nwords ; i ++ ) { XVECEXP ( regs , 0 , i ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( word_mode , regno ) , GEN_INT ( UNITS_PER_WORD * i ) ) ; regno ++ ; } return regs ; } </s>

Used by function_arg and sparc_function_value_1 to implement the conventions of the 64-bit ABI for passing and returning unions . Return an expression valid as a return value for the FUNCTION_ARG and TARGET_FUNCTION_VALUE . SIZE is the size in bytes of the union . MODE is the argument 's machine mode . REGNO is the hard register the union will be passed in .


"ERROR: Unknown type of MachineOperand: "

getMachineOpValue - Return binary encoding of operand .


<s> bool runOnMachineFunction ( MachineFunction & MF ) { if ( InstrumentSandboxingCFI ) removeCall64m ( MF ) ; addBoundChecks ( MF ) ; return 0 ; } </s>


<s> int AArch64TTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind , Instruction * Inst ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; unsigned ImmIdx = ~ 0U ; switch ( Opcode ) { default : return TTI :: TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: Store : ImmIdx = 0 ; break ; case Instruction :: Add : case Instruction :: Sub : case Instruction :: Mul : case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : case Instruction :: ICmp : ImmIdx = 1 ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == 1 ) return TTI :: TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: IntToPtr : case Instruction :: PtrToInt : case Instruction :: BitCast : case Instruction :: PHI : case Instruction :: Call : case Instruction :: Select : case Instruction :: Ret : case Instruction :: Load : break ; } if ( Idx == ImmIdx ) { int NumConstants = ( BitSize + 63 ) / 64 ; int Cost = AArch64TTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ; return ( Cost <= NumConstants * TTI :: TCC_Basic ) ? static_cast < int > ( TTI :: TCC_Free ) : Cost ; } return AArch64TTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> bool ARMBaseInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & , unsigned TCycles , unsigned TExtra , MachineBasicBlock & , unsigned FCycles , unsigned FExtra , BranchProbability Probability ) const { if ( ! TCycles ) return false ; const unsigned ScalingUpFactor = 1024 ; unsigned TUnpredCost = Probability . scale ( TCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FCycles * ScalingUpFactor ) ; unsigned UnpredCost = TUnpredCost + FUnpredCost ; UnpredCost += 1 * ScalingUpFactor ; UnpredCost += Subtarget . getMispredictionPenalty ( ) * ScalingUpFactor / 10 ; return ( TCycles + FCycles + TExtra + FExtra ) * ScalingUpFactor <= UnpredCost ; } </s>


<s> static bool ia64_cannot_force_const_mem ( machine_mode mode , rtx x ) { if ( mode == RFmode ) return true ; return tls_symbolic_operand_type ( x ) != 0 ; } </s>

Do n't allow TLS addresses to get spilled to memory .


<s> RegisterSet & insert ( const RegisterSet & Rs ) { for ( unsigned R = Rs . find_first ( ) ; R ; R = Rs . find_next ( R ) ) insert ( R ) ; return * this ; } </s>

insert - Append entry to the vector if it does n't already exist .


<s> SMLoc getStartLoc ( ) const { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> static bool expand_vec_perm_broadcast ( struct expand_vec_perm_d * d ) { unsigned i , elt , nelt = d -> nelt ; if ( ! d -> one_operand_p ) return false ; elt = d -> perm [ 0 ] ; for ( i = 1 ; i < nelt ; ++ i ) if ( d -> perm [ i ] != elt ) return false ; return expand_vec_perm_broadcast_1 ( d ) ; } </s>


<s> static int ix86_issue_rate ( void ) { switch ( ix86_tune ) { case PROCESSOR_PENTIUM : case PROCESSOR_K6 : return 2 ; case PROCESSOR_PENTIUMPRO : case PROCESSOR_PENTIUM4 : case PROCESSOR_ATHLON : case PROCESSOR_K8 : case PROCESSOR_NOCONA : return 3 ; default : return 1 ; } } </s>

Return the maximum number of instructions a cpu can issue .


<s>
bool
AMDGPULegalizerInfo
::
legalizeCustom
(
MachineInstr
&
MI
,
MachineRegisterInfo
&
MRI
,
MachineIRBuilder
&
MIRBuilder
,
GISelChangeObserver
&
Observer
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
case
TargetOpcode
::
G_ADDRSPACE_CAST
:
return
legalizeAddrSpaceCast
(
MI
,
MRI
,
MIRBuilder
)
;
case
TargetOpcode
::
G_FRINT
:
return
legalizeFrint
(
MI
,
MRI
,
MIRBuilder
)
;
case
TargetOpcode
::
G_FCEIL
:
return
legalizeFceil
(
MI
,
MRI
,
MIRBuilder
)
;
case
TargetOpcode
::
G_INTRINSIC_TRUNC
:
return
legalizeIntrinsicTrunc
(
MI
,
MRI
,
MIRBuilder
)
;
case
TargetOpcode
::
G_SITOFP
:
return
legalizeITOFP
(
MI
,
MRI
,
MIRBuilder
,
true
)
;
case
TargetOpcode
::
G_UITOFP
:
return
legalizeITOFP
(
MI
,
MRI
,
MIRBuilder
,
false
)
;
case
TargetOpcode
::
G_FMINNUM
:
case
TargetOpcode
::
G_FMAXNUM
:
case
TargetOpcode
::
G_FMINNUM_IEEE
:
case
TargetOpcode
::
G_FMAXNUM_IEEE
:
return
legalizeMinNumMaxNum
(
MI
,
MRI
,
MIRBuilder
)
;
case
TargetOpcode
::
G_EXTRACT_VECTOR_ELT
:
return
legalizeExtractVectorElt
(
MI
,
MRI
,
MIRBuilder
)
;
case
TargetOpcode
::
G_INSERT_VECTOR_ELT
:
return
legalizeInsertVectorElt
(
MI
,
MRI
,
MIRBuilder
)
;
default
:
return
false
;
}
llvm_unreachable
(
"expected switch to return"
)
;
}
</s>

Called for instructions with the Custom LegalizationAction .

AMDGPU
AMDGPU
SI
SI
"expected switch to return"


<s> bool fr30_frame_pointer_required ( void ) { return ( flag_omit_frame_pointer == 0 || crtl -> args . pretend_args_size > 0 ) ; } </s>


<s> Align getStackAlignment ( ) const { return StackAlignment ; } </s>

Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget .


<s> TargetLowering :: AtomicExpansionKind RISCVTargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * CI ) const { unsigned Size = CI -> getCompareOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( ( Size == 8 || Size == 16 ) && ! RISCVABI :: isCheriPureCapABI ( Subtarget . getTargetABI ( ) ) ) return AtomicExpansionKind :: MaskedIntrinsic ; return AtomicExpansionKind :: None ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> static rtx s390_find_execute ( struct constant_pool * pool , rtx insn ) { struct constant * c ; rtx offset ; for ( c = pool -> execute ; c != NULL ; c = c -> next ) if ( INSN_UID ( insn ) == INSN_UID ( c -> value ) ) break ; gcc_assert ( c ) ; offset = gen_rtx_MINUS ( Pmode , gen_rtx_LABEL_REF ( Pmode , c -> label ) , gen_rtx_LABEL_REF ( Pmode , pool -> label ) ) ; offset = gen_rtx_CONST ( Pmode , offset ) ; return offset ; } </s>

Find execute target for INSN in the constant pool POOL . Return an RTX describing the distance from the start of the pool to the location of the execute target .


<s> MachineBasicBlock :: iterator X86InstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , const MachineOutlinerInfo & MInfo ) const { if ( MInfo . CallConstructionID == MachineOutlinerTailCall ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( X86 :: JMP_1 ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; } else { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( X86 :: CALL64pcrel32 ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; } return It ; } </s>

Insert a call to an outlined function into the program .


"Cannot store this register into a stack slot!"

Store the specified register of the given register class to the specified stack frame index .


<s> bool SystemZXPLINKFrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; SystemZMachineFunctionInfo * MFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; const SystemZSubtarget & Subtarget = MF . getSubtarget < SystemZSubtarget > ( ) ; auto & Regs = Subtarget . getSpecialRegisters < SystemZXPLINK64Registers > ( ) ; unsigned LowGPR = 0 ; int LowOffset = INT32_MAX ; unsigned HighGPR = LowGPR ; int HighOffset = - 1 ; unsigned RegSP = Regs . getStackPointerRegister ( ) ; auto & GRRegClass = SystemZ :: GR64BitRegClass ; const unsigned RegSize = 8 ; auto ProcessCSI = [ & ] ( std :: vector < CalleeSavedInfo > & CSIList ) { for ( auto & CS : CSIList ) { unsigned Reg = CS . getReg ( ) ; int Offset = RegSpillOffsets [ Reg ] ; if ( Offset >= 0 ) { if ( GRRegClass . contains ( Reg ) ) { if ( LowOffset > Offset ) { LowOffset = Offset ; LowGPR = Reg ; } if ( Offset > HighOffset ) { HighOffset = Offset ; HighGPR = Reg ; } } int FrameIdx = MFFrame . CreateFixedSpillStackObject ( RegSize , Offset ) ; CS . setFrameIdx ( FrameIdx ) ; } else CS . setFrameIdx ( INT32_MAX ) ; } } ; std :: vector < CalleeSavedInfo > Spills ; Spills . push_back ( CalleeSavedInfo ( Regs . getAddressOfCalleeRegister ( ) ) ) ; if ( hasFP ( MF ) || MF . getFunction ( ) . hasFnAttribute ( "backchain" ) ) Spills . push_back ( CalleeSavedInfo ( RegSP ) ) ; ProcessCSI ( CSI ) ; MFI -> setRestoreGPRRegs ( LowGPR , HighGPR , LowOffset ) ; ProcessCSI ( Spills ) ; MFI -> setSpillGPRRegs ( LowGPR , HighGPR , LowOffset ) ; for ( auto & CS : CSI ) { if ( CS . getFrameIdx ( ) != INT32_MAX ) continue ; unsigned Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; Align Alignment = TRI -> getSpillAlign ( * RC ) ; unsigned Size = TRI -> getSpillSize ( * RC ) ; Alignment = std :: min ( Alignment , getStackAlign ( ) ) ; int FrameIdx = MFFrame . CreateStackObject ( Size , Alignment , true ) ; CS . setFrameIdx ( FrameIdx ) ; } return true ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> static const MachineOperand & getLdStBaseOp ( const MachineInstr & MI ) { unsigned Idx = isPairedLdSt ( MI ) ? 2 : 1 ; return MI . getOperand ( Idx ) ; } </s>

Returns the base register operator of a load/store .


<s> void Mips16FrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( StackSize == 0 && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; MachineLocation DstML , SrcML ; TII . makeFrame ( Mips :: SP , StackSize , MBB , MBBI ) ; MCSymbol * AdjustSPLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( AdjustSPLabel ) ; MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( AdjustSPLabel , - StackSize ) ) ; MCSymbol * CSLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( CSLabel ) ; unsigned S1 = MRI -> getDwarfRegNum ( Mips :: S1 , true ) ; MMI . addFrameInst ( MCCFIInstruction :: createOffset ( CSLabel , S1 , - 8 ) ) ; unsigned S0 = MRI -> getDwarfRegNum ( Mips :: S0 , true ) ; MMI . addFrameInst ( MCCFIInstruction :: createOffset ( CSLabel , S0 , - 12 ) ) ; unsigned RA = MRI -> getDwarfRegNum ( Mips :: RA , true ) ; MMI . addFrameInst ( MCCFIInstruction :: createOffset ( CSLabel , RA , - 4 ) ) ; if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: MoveR3216 ) , Mips :: S0 ) . addReg ( Mips :: SP ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> void GCNPassConfig :: addIRPasses ( ) { addPass ( createAMDGPUCodeGenPreparePass ( & getGCNTargetMachine ( ) ) ) ; AMDGPUPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> rtx * neon_vcmla_lane_prepare_operands ( rtx * operands ) { int lane = INTVAL ( operands [ 4 ] ) ; machine_mode constmode = SImode ; machine_mode mode = GET_MODE ( operands [ 3 ] ) ; int regno = REGNO ( operands [ 3 ] ) ; regno = ( ( regno - FIRST_VFP_REGNUM ) >> 1 ) ; if ( lane > 0 && lane >= GET_MODE_NUNITS ( mode ) / 4 ) { operands [ 3 ] = gen_int_mode ( regno + 1 , constmode ) ; operands [ 4 ] = gen_int_mode ( lane - GET_MODE_NUNITS ( mode ) / 4 , constmode ) ; } else { operands [ 3 ] = gen_int_mode ( regno , constmode ) ; operands [ 4 ] = gen_int_mode ( lane , constmode ) ; } return operands ; } </s>

Prepares the operands for the VCMLA by lane instruction such that the right register number is selected . This instruction is special in that it always requires a D register , however there is a choice to be made between Dn [ 0 ] , Dn [ 1 ] , D ( n+1 ) [ 0 ] , and D ( n+1 ) [ 1 ] depending on the mode of the registers . The VCMLA by lane function always selects two values . For instance given D0 and a V2SF , the only valid index is 0 as the values in S0 and S1 will be used by the instruction . However given V4SF then index 0 and 1 are valid as D0 [ 0 ] or D1 [ 0 ] are both valid . This function centralizes that information based on OPERANDS , OPERANDS [ 3 ] will be changed from a REG into a CONST_INT RTX and OPERANDS [ 4 ] will be updated to contain the right index .


<s>
bool
ARMDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
char
ConstraintCode
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
assert
(
ConstraintCode
==
'm'
&&
"unexpected asm memory constraint"
)
;
SDValue
Base
,
Offset
,
Opc
;
if
(
!
SelectAddrMode2
(
Op
,
Op
,
Base
,
Offset
,
Opc
)
)
return
true
;
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
OutOps
.
push_back
(
Opc
)
;
return
false
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .

ARM
ARM
"unexpected asm memory constraint"


<s> unsigned AArch64RegisterBankInfo :: copyCost ( const RegisterBank & A , const RegisterBank & B , unsigned Size ) const { return RegisterBankInfo :: copyCost ( A , B , Size ) ; } </s>

Get the cost of a copy from B to A , or put differently , get the cost of A = COPY B .


"JIT relocation model must be set to static or default!"

runOnMachineFunction - Emit the function body .


<s> unsigned HexagonInstrInfo :: getInstrLatency ( const InstrItineraryData * ItinData , const MachineInstr & MI , unsigned * PredCost ) const { return getInstrTimingClassLatency ( ItinData , MI ) ; } </s>

Compute the instruction latency of a given instruction .


<s> bool ix86_expand_fp_movcc ( rtx operands [ ] ) { machine_mode mode = GET_MODE ( operands [ 0 ] ) ; enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; rtx tmp , compare_op ; rtx op0 = XEXP ( operands [ 1 ] , 0 ) ; rtx op1 = XEXP ( operands [ 1 ] , 1 ) ; if ( GET_MODE ( op0 ) == BFmode && ! ix86_fp_comparison_operator ( operands [ 1 ] , VOIDmode ) ) return false ; if ( SSE_FLOAT_MODE_SSEMATH_OR_HF_P ( mode ) ) { machine_mode cmode ; cmode = GET_MODE ( op0 ) ; if ( cmode == VOIDmode ) cmode = GET_MODE ( op1 ) ; if ( cmode != mode ) return false ; code = ix86_prepare_sse_fp_compare_args ( operands [ 0 ] , code , & op0 , & op1 ) ; if ( code == UNKNOWN ) return false ; if ( ix86_expand_sse_fp_minmax ( operands [ 0 ] , code , op0 , op1 , operands [ 2 ] , operands [ 3 ] ) ) return true ; tmp = ix86_expand_sse_cmp ( operands [ 0 ] , code , op0 , op1 , operands [ 2 ] , operands [ 3 ] ) ; ix86_expand_sse_movcc ( operands [ 0 ] , tmp , operands [ 2 ] , operands [ 3 ] ) ; return true ; } if ( GET_MODE ( op0 ) == TImode || ( GET_MODE ( op0 ) == DImode && ! TARGET_64BIT ) ) return false ; compare_op = ix86_expand_compare ( code , op0 , op1 ) ; if ( ! fcmov_comparison_operator ( compare_op , VOIDmode ) ) { tmp = gen_reg_rtx ( QImode ) ; ix86_expand_setcc ( tmp , code , op0 , op1 ) ; compare_op = ix86_expand_compare ( NE , tmp , const0_rtx ) ; } emit_insn ( gen_rtx_SET ( operands [ 0 ] , gen_rtx_IF_THEN_ELSE ( mode , compare_op , operands [ 2 ] , operands [ 3 ] ) ) ) ; return true ; } </s>

Expand a floating-point conditional move . Return true if successful .


<s> EVT NyuziTargetLowering :: getSetCCResultType ( const DataLayout & , LLVMContext & Context , EVT VT ) const { if ( VT . isVector ( ) ) { return EVT :: getVectorVT ( Context , MVT :: i1 , VT . getVectorNumElements ( ) ) ; } else { return MVT :: i32 ; } } </s>

Return the value type to use for ISD : :SETCC .


<s> bool SystemZTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , MachineMemOperand :: Flags , bool * Fast ) const { if ( Fast ) * Fast = true ; return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> Align getABIAlignmentForCallingConv ( Type * ArgTy , DataLayout DL ) const override { const Align ABIAlign = DL . getABITypeAlign ( ArgTy ) ; if ( ArgTy -> isVectorTy ( ) ) return std :: min ( ABIAlign , Align ( 8 ) ) ; return ABIAlign ; } </s>

Return the correct alignment for the current calling convention .


<s> static machine_mode m68k_promote_function_mode ( const_tree type , machine_mode mode , int * punsignedp ATTRIBUTE_UNUSED , const_tree fntype ATTRIBUTE_UNUSED , int for_return ) { if ( type == NULL_TREE && ! for_return && ( mode == QImode || mode == HImode ) ) return SImode ; return mode ; } </s>


<s>
bool
M68kAsmParser
::
MatchAndEmitInstruction
(
SMLoc
Loc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MatchingInlineAsm
)
;
switch
(
MatchResult
)
{
case
Match_Success
:
return
emit
(
Inst
,
Loc
,
Out
)
;
case
Match_MissingFeature
:
return
missingFeature
(
Loc
,
ErrorInfo
)
;
case
Match_InvalidOperand
:
return
invalidOperand
(
Loc
,
Operands
,
ErrorInfo
)
;
case
Match_MnemonicFail
:
return
Error
(
Loc
,
"invalid instruction"
)
;
default
:
return
true
;
}
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> static rtx loongarch_add_offset ( rtx temp , rtx reg , HOST_WIDE_INT offset ) { if ( ! IMM12_OPERAND ( offset ) ) { rtx high ; high = gen_int_mode ( CONST_HIGH_PART ( offset ) , Pmode ) ; offset = CONST_LOW_PART ( offset ) ; high = loongarch_force_temporary ( temp , high ) ; reg = loongarch_force_temporary ( temp , gen_rtx_PLUS ( Pmode , high , reg ) ) ; } return plus_constant ( Pmode , reg , offset ) ; } </s>

Return a legitimate address for REG + OFFSET . TEMP is as for loongarch_force_temporary ; it is only needed when OFFSET is not a IMM12_OPERAND .


<s> static bool ix86_handle_option ( size_t code , const char * arg ATTRIBUTE_UNUSED , int value ) { switch ( code ) { case OPT_m3dnow : if ( ! value ) { target_flags &= ~ MASK_3DNOW_A ; target_flags_explicit |= MASK_3DNOW_A ; } return true ; case OPT_mmmx : if ( ! value ) { target_flags &= ~ ( MASK_3DNOW | MASK_3DNOW_A ) ; target_flags_explicit |= MASK_3DNOW | MASK_3DNOW_A ; } return true ; case OPT_msse : if ( ! value ) { target_flags &= ~ ( MASK_SSE2 | MASK_SSE3 ) ; target_flags_explicit |= MASK_SSE2 | MASK_SSE3 ; } return true ; case OPT_msse2 : if ( ! value ) { target_flags &= ~ MASK_SSE3 ; target_flags_explicit |= MASK_SSE3 ; } return true ; default : return true ; } } </s>


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> void assignValueToReg ( Register ValVReg , Register PhysReg , CCValAssign & VA ) override { MIB . addUse ( PhysReg , RegState :: Implicit ) ; Register ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildCopy ( PhysReg , ExtReg ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s>
SDValue
X86TargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
bool
Is64Bit
=
Subtarget
.
is64Bit
(
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_X86
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
CopyVT
=
VA
.
getLocVT
(
)
;
if
(
(
CopyVT
==
MVT
::
f32
||
CopyVT
==
MVT
::
f64
||
CopyVT
==
MVT
::
f128
)
&&
(
(
Is64Bit
||
Ins
[
i
]
.
Flags
.
isInReg
(
)
)
&&
!
Subtarget
.
hasSSE1
(
)
)
)
{
report_fatal_error
(
"SSE register return with SSE disabled"
)
;
}
bool
RoundAfterCopy
=
false
;
if
(
(
VA
.
getLocReg
(
)
==
X86
::
FP0
||
VA
.
getLocReg
(
)
==
X86
::
FP1
)
&&
isScalarFPTypeInSSEReg
(
VA
.
getValVT
(
)
)
)
{
CopyVT
=
MVT
::
f80
;
RoundAfterCopy
=
(
CopyVT
!=
VA
.
getLocVT
(
)
)
;
}
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
CopyVT
,
InFlag
)
.
getValue
(
1
)
;
SDValue
Val
=
Chain
.
getValue
(
0
)
;
if
(
RoundAfterCopy
)
Val
=
DAG
.
getNode
(
ISD
::
FP_ROUND
,
dl
,
VA
.
getValVT
(
)
,
Val
,
DAG
.
getIntPtrConstant
(
1
,
dl
)
)
;
if
(
VA
.
isExtInLoc
(
)
&&
VA
.
getValVT
(
)
.
getScalarType
(
)
==
MVT
::
i1
)
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
InFlag
=
Chain
.
getValue
(
2
)
;
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


Return an array that contains the bitmask target flag values and their names .

ARM ARM ARM "arm-got" "arm-sbrel" "arm-dllimport" "arm-secrel" "arm-nonlazy"


<s> bool X86InstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { bool HasAVX = TM . getSubtarget < X86Subtarget > ( ) . hasAVX ( ) ; switch ( MI -> getOpcode ( ) ) { case X86 :: V_SET0 : case X86 :: FsFLD0SS : case X86 :: FsFLD0SD : return Expand2AddrUndef ( MI , get ( HasAVX ? X86 :: VXORPSrr : X86 :: XORPSrr ) ) ; case X86 :: TEST8ri_NOREX : MI -> setDesc ( get ( X86 :: TEST8ri ) ) ; return true ; } return false ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> unsigned int R600InstrInfo :: getInstrLatency ( const InstrItineraryData * ItinData , const MachineInstr & , unsigned * PredCost ) const { if ( PredCost ) * PredCost = 2 ; return 2 ; } </s>


<s> void emitVERegisterIgnore ( unsigned reg ) override { } </s>

Emit `` .register < reg > , # ignore '' .


<s> void ARMElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { const ARMTargetMachine & ARM_TM = static_cast < const ARMTargetMachine & > ( TM ) ; bool isAAPCS_ABI = ARM_TM . TargetABI == ARMTargetMachine :: ARMABI :: ARM_ABI_AAPCS ; genExecuteOnly = ARM_TM . getSubtargetImpl ( ) -> genExecuteOnly ( ) ; TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( isAAPCS_ABI ) ; if ( isAAPCS_ABI ) { LSDASection = nullptr ; } AttributesSection = getContext ( ) . getELFSection ( ".ARM.attributes" , ELF :: SHT_ARM_ATTRIBUTES , 0 ) ; if ( genExecuteOnly ) { unsigned Type = ELF :: SHT_PROGBITS ; unsigned Flags = ELF :: SHF_EXECINSTR | ELF :: SHF_ALLOC | ELF :: SHF_ARM_PURECODE ; TextSection = Ctx . getELFSection ( ".text" , Type , Flags , 0 , "" , 0U ) ; } } </s>

This method must be called before any actual lowering is done .


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( ( N -> getOpcode ( ) == X86ISD :: CALL && ! Subtarget -> callRegIndirect ( ) ) || ( N -> getOpcode ( ) == X86ISD :: TC_RETURN && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; EVT SrcVT = N -> getOperand ( 0 ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( 0 ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; bool SrcIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> const SIRegisterInfo & getRegisterInfo ( ) const override { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> const InstrItineraryData & getInstrItineraryData ( ) const { return InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( ( N -> getOpcode ( ) == X86ISD :: CALL && ! Subtarget -> callRegIndirect ( ) ) || ( N -> getOpcode ( ) == X86ISD :: TC_RETURN && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; MVT SrcVT = N -> getOperand ( 0 ) . getSimpleValueType ( ) ; MVT DstVT = N -> getSimpleValueType ( 0 ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const X86TargetLowering * X86Lowering = static_cast < const X86TargetLowering * > ( TLI ) ; bool SrcIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } MVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>


<s> bool AMDGPUAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == ".hsa_code_object_version" ) return ParseDirectiveHSACodeObjectVersion ( ) ; if ( IDVal == ".hsa_code_object_isa" ) return ParseDirectiveHSACodeObjectISA ( ) ; if ( IDVal == AMDGPU :: CodeObject :: MetadataAssemblerDirectiveBegin ) return ParseDirectiveCodeObjectMetadata ( ) ; if ( IDVal == ".amd_kernel_code_t" ) return ParseDirectiveAMDKernelCodeT ( ) ; if ( IDVal == ".amdgpu_hsa_kernel" ) return ParseDirectiveAMDGPUHsaKernel ( ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> static void mips_sim_wait_regs ( struct mips_sim * state , rtx_insn * insn ) { mips_sim_insn = insn ; note_uses ( & PATTERN ( insn ) , mips_sim_wait_regs_1 , state ) ; } </s>

Advance simulation state STATE until all of INSN 's register dependencies are satisfied .


<s> static tree rs6000_builtin_vectorized_libmass ( combined_fn fn , tree type_out , tree type_in ) { char name [ 32 ] ; const char * suffix = NULL ; tree fntype , new_fndecl , bdecl = NULL_TREE ; int n_args = 1 ; const char * bname ; machine_mode el_mode , in_mode ; int n , in_n ; if ( ! flag_unsafe_math_optimizations || ! TARGET_VSX ) return NULL_TREE ; el_mode = TYPE_MODE ( TREE_TYPE ( type_out ) ) ; n = TYPE_VECTOR_SUBPARTS ( type_out ) ; in_mode = TYPE_MODE ( TREE_TYPE ( type_in ) ) ; in_n = TYPE_VECTOR_SUBPARTS ( type_in ) ; if ( el_mode != in_mode || n != in_n ) return NULL_TREE ; switch ( fn ) { CASE_CFN_ATAN2 : CASE_CFN_HYPOT : CASE_CFN_POW : n_args = 2 ; gcc_fallthrough ( ) ; CASE_CFN_ACOS : CASE_CFN_ACOSH : CASE_CFN_ASIN : CASE_CFN_ASINH : CASE_CFN_ATAN : CASE_CFN_ATANH : CASE_CFN_CBRT : CASE_CFN_COS : CASE_CFN_COSH : CASE_CFN_ERF : CASE_CFN_ERFC : CASE_CFN_EXP2 : CASE_CFN_EXP : CASE_CFN_EXPM1 : CASE_CFN_LGAMMA : CASE_CFN_LOG10 : CASE_CFN_LOG1P : CASE_CFN_LOG2 : CASE_CFN_LOG : CASE_CFN_SIN : CASE_CFN_SINH : CASE_CFN_SQRT : CASE_CFN_TAN : CASE_CFN_TANH : if ( el_mode == DFmode && n == 2 ) { bdecl = mathfn_built_in ( double_type_node , fn ) ; suffix = "d2" ; } else if ( el_mode == SFmode && n == 4 ) { bdecl = mathfn_built_in ( float_type_node , fn ) ; suffix = "4" ; } else return NULL_TREE ; if ( ! bdecl ) return NULL_TREE ; break ; default : return NULL_TREE ; } gcc_assert ( suffix != NULL ) ; bname = IDENTIFIER_POINTER ( DECL_NAME ( bdecl ) ) ; if ( ! bname ) return NULL_TREE ; strcpy ( name , bname + strlen ( "__builtin_" ) ) ; strcat ( name , suffix ) ; if ( n_args == 1 ) fntype = build_function_type_list ( type_out , type_in , NULL ) ; else if ( n_args == 2 ) fntype = build_function_type_list ( type_out , type_in , type_in , NULL ) ; else gcc_unreachable ( ) ; new_fndecl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , fntype ) ; TREE_PUBLIC ( new_fndecl ) = 1 ; DECL_EXTERNAL ( new_fndecl ) = 1 ; DECL_IS_NOVOPS ( new_fndecl ) = 1 ; TREE_READONLY ( new_fndecl ) = 1 ; return new_fndecl ; } </s>

Handler for the Mathematical Acceleration Subsystem ( mass ) interface to a library with vectorized intrinsics .


<s> const uint32_t * ARMBaseRegisterInfo :: getThisReturnPreservedMask ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return NULL ; return ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ? CSR_iOS_ThisReturn_RegMask : CSR_AAPCS_ThisReturn_RegMask ; } </s>

getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned ' is on an i32 first argument if the calling convention is one that can ( partially ) model this attribute with a preserved mask ( i.e .


<s> tree rs6000_builtin_mask_for_load ( void ) { if ( ( TARGET_ALTIVEC && ! TARGET_VSX ) || ( TARGET_VSX && ! TARGET_EFFICIENT_UNALIGNED_VSX ) ) return altivec_builtin_mask_for_load ; else return 0 ; } </s>


<s> static size_t mingw32_gt_pch_alloc_granularity ( void ) { SYSTEM_INFO si ; GetSystemInfo ( & si ) ; va_granularity = ( size_t ) si . dwAllocationGranularity ; return va_granularity ; } </s>

Granularity for reserving address space .


<s> static int spu_builtin_vectorization_cost ( enum vect_cost_for_stmt type_of_cost , tree vectype , int misalign ATTRIBUTE_UNUSED ) { unsigned elements ; switch ( type_of_cost ) { case scalar_stmt : case vector_stmt : case vector_load : case vector_store : case vec_to_scalar : case scalar_to_vec : case cond_branch_not_taken : case vec_perm : case vec_promote_demote : return 1 ; case scalar_store : return 10 ; case scalar_load : return 2 ; case unaligned_load : case vector_gather_load : case vector_scatter_store : return 2 ; case cond_branch_taken : return 6 ; case vec_construct : elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; return elements / 2 + 1 ; default : gcc_unreachable ( ) ; } } </s>


<s> static void mep_jmp_return_reorg ( rtx_insn * insns ) { rtx_insn * insn , * label , * ret ; int ret_code ; for ( insn = insns ; insn ; insn = NEXT_INSN ( insn ) ) if ( simplejump_p ( insn ) ) { label = ret = safe_as_a < rtx_insn * > ( JUMP_LABEL ( insn ) ) ; while ( ret && ( NOTE_P ( ret ) || LABEL_P ( ret ) || GET_CODE ( PATTERN ( ret ) ) == USE ) ) ret = NEXT_INSN ( ret ) ; if ( ret ) { ret_code = recog_memoized ( ret ) ; if ( ret_code == CODE_FOR_return_internal || ret_code == CODE_FOR_eh_return_internal ) { LABEL_NUSES ( label ) -- ; if ( LABEL_NUSES ( label ) == 0 ) delete_insn ( label ) ; PATTERN ( insn ) = copy_rtx ( PATTERN ( ret ) ) ; INSN_CODE ( insn ) = - 1 ; } } } } </s>

Replace a jump to a return , with a copy of the return . GCC does n't always do this on its own .


<s> uint64_t MipsGNUInfo :: flags ( ) const { return m_ElfFlags ; } </s>

Get the flags for this GlobalValue ( see struct GVFlags ) .


"MIPS16 PIC for ABIs other than o32 and o64"

"%<hard-float%> MIPS16 code for ABIs other than o32 and o64"

Set up the target-dependent global state for ISA mode COMPRESSION_MODE , which is either MASK_MIPS16 or MASK_MICROMIPS .


<s> static void rs6000_frame_related ( rtx insn , rtx reg , HOST_WIDE_INT val , rtx reg2 , rtx rreg ) { rtx real , temp ; if ( reg == reg2 ) reg = gen_raw_REG ( GET_MODE ( reg ) , REGNO ( reg ) ) ; if ( reg == rreg ) reg = gen_raw_REG ( GET_MODE ( reg ) , REGNO ( reg ) ) ; real = copy_rtx ( PATTERN ( insn ) ) ; if ( reg2 != NULL_RTX ) real = replace_rtx ( real , reg2 , rreg ) ; real = replace_rtx ( real , reg , gen_rtx_PLUS ( Pmode , gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) , GEN_INT ( val ) ) ) ; if ( GET_CODE ( real ) == SET ) { rtx set = real ; temp = simplify_rtx ( SET_SRC ( set ) ) ; if ( temp ) SET_SRC ( set ) = temp ; temp = simplify_rtx ( SET_DEST ( set ) ) ; if ( temp ) SET_DEST ( set ) = temp ; if ( GET_CODE ( SET_DEST ( set ) ) == MEM ) { temp = simplify_rtx ( XEXP ( SET_DEST ( set ) , 0 ) ) ; if ( temp ) XEXP ( SET_DEST ( set ) , 0 ) = temp ; } } else { int i ; gcc_assert ( GET_CODE ( real ) == PARALLEL ) ; for ( i = 0 ; i < XVECLEN ( real , 0 ) ; i ++ ) if ( GET_CODE ( XVECEXP ( real , 0 , i ) ) == SET ) { rtx set = XVECEXP ( real , 0 , i ) ; temp = simplify_rtx ( SET_SRC ( set ) ) ; if ( temp ) SET_SRC ( set ) = temp ; temp = simplify_rtx ( SET_DEST ( set ) ) ; if ( temp ) SET_DEST ( set ) = temp ; if ( GET_CODE ( SET_DEST ( set ) ) == MEM ) { temp = simplify_rtx ( XEXP ( SET_DEST ( set ) , 0 ) ) ; if ( temp ) XEXP ( SET_DEST ( set ) , 0 ) = temp ; } RTX_FRAME_RELATED_P ( set ) = 1 ; } } if ( TARGET_SPE ) real = spe_synthesize_frame_save ( real ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , real , REG_NOTES ( insn ) ) ; } </s>

Add to 'insn ' a note which is PATTERN ( INSN ) but with REG replaced with ( plus : P ( reg 1 ) VAL ) , and with REG2 replaced with RREG if REG2 is not NULL . It would be nice if dwarf2out_frame_debug_expr could deduce these equivalences by itself so it was n't necessary to hold its hand so much . Do n't be tempted to always supply d2_f_d_e with the actual cfa register , ie . r31 when we are using a hard frame pointer . That fails when saving regs off r1 , and sched moves the r31 setup past the reg saves .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
X86
::
NumTargetFixupKinds
]
=
{
{
"reloc_riprel_4byte"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_movq_load"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_relax"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_relax_rex"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_signed_4byte"
,
0
,
32
,
0
}
,
{
"reloc_signed_4byte_relax"
,
0
,
32
,
0
}
,
{
"reloc_global_offset_table"
,
0
,
32
,
0
}
,
{
"reloc_global_offset_table8"
,
0
,
64
,
0
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


";; [Local] Removing membar %d since order"

";; [Local] Removing membar %d since the target"

" of %d is used before the I/O operation\n"

Go through block BB looking for membars to remove . There are two cases where intra-block analysis is enough : - a membar is redundant if it occurs between two consecutive I/O operations and if those operations are guaranteed to complete in order . - a membar for a __builtin_read is redundant if the result is used before the next I/O operation is issued . If the last membar in the block could not be removed , and there are guaranteed to be no I/O operations between that membar and the end of the block , store the membar in * LAST_MEMBAR , otherwise store null . Describe the block 's first I/O operation in * NEXT_IO . Describe an unknown operation if the block does n't do any I/O .


This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static void m68k_sched_dfa_post_advance_cycle ( void ) { int i ; if ( ! sched_ib . enabled_p ) return ; i = max_insn_size - sched_ib . filled ; while ( -- i >= 0 ) { if ( state_transition ( curr_state , sched_ib . insn ) >= 0 ) ++ sched_ib . filled ; } } </s>

Implementation of targetm.sched.dfa_post_advance_cycle ( ) hook . It is invoked just after new cycle begins and is used here to setup number of filled words in the instruction buffer so that instructions which wo n't have all their words prefetched would be stalled for a cycle .


<s> static void gen_safe_add ( rtx dest , rtx src , rtx val , bool is_frame_related ) { rtx insn ; if ( val == NULL_RTX || INTVAL ( val ) == 0 ) { gcc_assert ( dest != src ) ; insn = emit_move_insn ( dest , src ) ; } else if ( ok_for_max_constant ( INTVAL ( val ) ) ) insn = emit_insn ( gen_addsi3 ( dest , src , val ) ) ; else { val = gen_rtx_CONST ( SImode , gen_rtx_UNSPEC ( SImode , gen_rtvec ( 1 , val ) , UNSPEC_CONST ) ) ; insn = emit_insn ( gen_addsi3 ( dest , src , val ) ) ; if ( is_frame_related ) add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( SImode , dest , gen_rtx_PLUS ( SImode , src , val ) ) ) ; return ; } if ( is_frame_related ) RTX_FRAME_RELATED_P ( insn ) = 1 ; return ; } </s>

Generate an ADD of SRC plus VAL into DEST . Handles the case where VAL is too big for max_constant_value . Sets FRAME_RELATED_P on the insn if IS_FRAME_RELATED is true .


"Can only return in upper and lower accumulators!"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static int mips_issue_rate ( void ) { switch ( mips_tune ) { case PROCESSOR_74KC : case PROCESSOR_74KF2_1 : case PROCESSOR_74KF1_1 : case PROCESSOR_74KF3_2 : case PROCESSOR_R10000 : return 4 ; case PROCESSOR_20KC : case PROCESSOR_R4130 : case PROCESSOR_R5400 : case PROCESSOR_R5500 : case PROCESSOR_R5900 : case PROCESSOR_R7000 : case PROCESSOR_R9000 : case PROCESSOR_OCTEON : case PROCESSOR_OCTEON2 : case PROCESSOR_OCTEON3 : return 2 ; case PROCESSOR_SB1 : case PROCESSOR_SB1A : return 3 ; case PROCESSOR_LOONGSON_2E : case PROCESSOR_LOONGSON_2F : case PROCESSOR_LOONGSON_3A : case PROCESSOR_P5600 : return 4 ; case PROCESSOR_XLP : return ( reload_completed ? 4 : 3 ) ; default : return 1 ; } } </s>

Return the number of instructions that can be issued per cycle .


<s> static int mips_binary_cost ( rtx x , int single_cost , int double_cost , bool speed ) { int cost ; if ( GET_MODE_SIZE ( GET_MODE ( x ) ) == UNITS_PER_WORD * 2 ) cost = double_cost ; else cost = single_cost ; return ( cost + set_src_cost ( XEXP ( x , 0 ) , GET_MODE ( x ) , speed ) + rtx_cost ( XEXP ( x , 1 ) , GET_MODE ( x ) , GET_CODE ( x ) , 1 , speed ) ) ; } </s>

Return the cost of binary operation X , given that the instruction sequence for a word-sized or smaller operation has cost SINGLE_COST and that the sequence of a double-word operation has cost DOUBLE_COST . If SPEED is true , optimize for speed otherwise optimize for size .


<s> const TargetRegisterClass * VERegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & VE :: I64RegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> int condexec_memory_operand ( rtx op , enum machine_mode mode ) { enum machine_mode op_mode = GET_MODE ( op ) ; rtx addr ; if ( mode != VOIDmode && op_mode != mode ) return FALSE ; switch ( op_mode ) { default : return FALSE ; case QImode : case HImode : case SImode : case SFmode : break ; } if ( GET_CODE ( op ) != MEM ) return FALSE ; addr = XEXP ( op , 0 ) ; return frv_legitimate_address_p ( mode , addr , reload_completed , TRUE , FALSE ) ; } </s>

Return true if the memory operand is one that can be conditionally executed .


<s> static void c6x_print_operand_address ( FILE * file , rtx addr ) { c6x_print_address_operand ( file , addr , VOIDmode ) ; } </s>

Output assembly language output for the address ADDR to FILE .


<s> HOST_WIDE_INT aarch64_fold_sve_cnt_pat ( aarch64_svpattern pattern , unsigned int nelts_per_vq ) { unsigned int vl , const_vg ; if ( pattern >= AARCH64_SV_VL1 && pattern <= AARCH64_SV_VL8 ) vl = 1 + ( pattern - AARCH64_SV_VL1 ) ; else if ( pattern >= AARCH64_SV_VL16 && pattern <= AARCH64_SV_VL256 ) vl = 16 << ( pattern - AARCH64_SV_VL16 ) ; else if ( aarch64_sve_vg . is_constant ( & const_vg ) ) { unsigned int nelts = ( const_vg / 2 ) * nelts_per_vq ; switch ( pattern ) { case AARCH64_SV_POW2 : return 1 << floor_log2 ( nelts ) ; case AARCH64_SV_MUL4 : return nelts & - 4 ; case AARCH64_SV_MUL3 : return ( nelts / 3 ) * 3 ; case AARCH64_SV_ALL : return nelts ; default : gcc_unreachable ( ) ; } } else return - 1 ; poly_uint64 nelts_all = exact_div ( aarch64_sve_vg , 2 ) * nelts_per_vq ; if ( known_le ( vl , nelts_all ) ) return vl ; if ( known_gt ( vl , nelts_all ) ) return 0 ; return - 1 ; } </s>

Check whether we can calculate the number of elements in PATTERN at compile time , given that there are NELTS_PER_VQ elements per 128-bit block . Return the value if so , otherwise return -1 .


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { const MCInstrDesc & Desc = Info -> get ( Inst . getOpcode ( ) ) ; for ( unsigned OpNum = 0 ; OpNum < Desc . getNumOperands ( ) ; ++ OpNum ) { if ( Inst . getOperand ( OpNum ) . isImm ( ) && Desc . OpInfo [ OpNum ] . OperandType == MCOI :: OPERAND_PCREL ) { int64_t Imm = Inst . getOperand ( OpNum ) . getImm ( ) ; Target = ARM_MC :: evaluateBranchTarget ( Desc , Addr , Imm ) ; return true ; } } return false ; } </s>

Given a branch instruction try to get the address the branch targets .


<s> static void aarch64_emit_prologue_components ( sbitmap components ) { aarch64_process_components ( components , true ) ; } </s>


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ! Subtarget -> isTargetNaCl ( ) && ( ( N -> getOpcode ( ) == X86ISD :: CALL && ! Subtarget -> callRegIndirect ( ) ) || ( N -> getOpcode ( ) == X86ISD :: TC_RETURN && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; MVT SrcVT = N -> getOperand ( 0 ) . getSimpleValueType ( ) ; MVT DstVT = N -> getSimpleValueType ( 0 ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const X86TargetLowering * X86Lowering = static_cast < const X86TargetLowering * > ( getTargetLowering ( ) ) ; bool SrcIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } MVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> static int riscv_arg_partial_bytes ( cumulative_args_t cum , const function_arg_info & generic_arg ) { struct riscv_arg_info arg ; riscv_get_arg_info ( & arg , get_cumulative_args ( cum ) , generic_arg . mode , generic_arg . type , generic_arg . named , false ) ; return arg . stack_p ? arg . num_gprs * UNITS_PER_WORD : 0 ; } </s>


<s>
void
SystemZPostRASchedStrategy
::
enterMBB
(
MachineBasicBlock
*
NextMBB
)
{
assert
(
(
SchedStates
.
find
(
NextMBB
)
==
SchedStates
.
end
(
)
)
&&
"Entering MBB twice?"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"** Entering "
<<
printMBBReference
(
*
NextMBB
)
)
;
MBB
=
NextMBB
;
HazardRec
=
SchedStates
[
MBB
]
=
new
SystemZHazardRecognizer
(
TII
,
&
SchedModel
)
;
LLVM_DEBUG
(
const
MachineLoop
*
Loop
=
MLI
->
getLoopFor
(
MBB
)
;
if
(
Loop
&&
Loop
->
getHeader
(
)
==
MBB
)
dbgs
(
)
<<
" (Loop header)"
;
dbgs
(
)
<<
":\n"
;
)
;
MachineBasicBlock
*
SinglePredMBB
=
getSingleSchedPred
(
MBB
,
MLI
->
getLoopFor
(
MBB
)
)
;
if
(
SinglePredMBB
==
nullptr
||
SchedStates
.
find
(
SinglePredMBB
)
==
SchedStates
.
end
(
)
)
return
;
LLVM_DEBUG
(
dbgs
(
)
<<
"** Continued scheduling from "
<<
printMBBReference
(
*
SinglePredMBB
)
<<
"\n"
;
)
;
HazardRec
->
copyState
(
SchedStates
[
SinglePredMBB
]
)
;
LLVM_DEBUG
(
HazardRec
->
dumpState
(
)
;
)
;
for
(
MachineBasicBlock
::
iterator
I
=
SinglePredMBB
->
getFirstTerminator
(
)
;
I
!=
SinglePredMBB
->
end
(
)
;
I
++
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"** Emitting incoming branch: "
;
I
->
dump
(
)
;
)
;
bool
TakenBranch
=
(
I
->
isBranch
(
)
&&
(
TII
->
getBranchInfo
(
*
I
)
.
Target
->
isReg
(
)
||
TII
->
getBranchInfo
(
*
I
)
.
Target
->
getMBB
(
)
==
MBB
)
)
;
HazardRec
->
emitInstruction
(
&
*
I
,
TakenBranch
)
;
if
(
TakenBranch
)
break
;
}
}
</s>

Tell the strategy that MBB is about to be processed .

SystemZ
SystemZ
"Entering MBB twice?"
"** Entering "
SystemZ
" (Loop header)"
":\n"
"** Continued scheduling from "
"\n"
"** Emitting incoming branch: "


<s> void AArch64AsmPrinter :: emitJumpTableInfo ( ) { const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; if ( ! MJTI ) return ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; if ( JT . empty ( ) ) return ; const Function & F = MF -> getFunction ( ) ; const TargetLoweringObjectFile & TLOF = getObjFileLowering ( ) ; bool JTInDiffSection = ! STI -> isTargetCOFF ( ) || ! TLOF . shouldPutJumpTableInFunctionSection ( MJTI -> getEntryKind ( ) == MachineJumpTableInfo :: EK_LabelDifference32 , F ) ; if ( JTInDiffSection ) { MCSection * ReadOnlySec = TLOF . getSectionForJumpTable ( F , TM ) ; OutStreamer -> SwitchSection ( ReadOnlySec ) ; } auto AFI = MF -> getInfo < AArch64FunctionInfo > ( ) ; for ( unsigned JTI = 0 , e = JT . size ( ) ; JTI != e ; ++ JTI ) { const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; if ( JTBBs . empty ( ) ) continue ; unsigned Size = AFI -> getJumpTableEntrySize ( JTI ) ; emitAlignment ( Align ( Size ) ) ; OutStreamer -> emitLabel ( GetJTISymbol ( JTI ) ) ; const MCSymbol * BaseSym = AArch64FI -> getJumpTableEntryPCRelSymbol ( JTI ) ; const MCExpr * Base = MCSymbolRefExpr :: create ( BaseSym , OutContext ) ; for ( auto * JTBB : JTBBs ) { const MCExpr * Value = MCSymbolRefExpr :: create ( JTBB -> getSymbol ( ) , OutContext ) ; Value = MCBinaryExpr :: createSub ( Value , Base , OutContext ) ; if ( Size != 4 ) Value = MCBinaryExpr :: createLShr ( Value , MCConstantExpr :: create ( 2 , OutContext ) , OutContext ) ; OutStreamer -> emitValue ( Value , Size ) ; } } } </s>

Print assembly representations of the jump tables used by the current function to the current output stream .


<s> unsigned int h8300_insn_length_from_table ( rtx_insn * insn , rtx * operands ) { switch ( get_attr_length_table ( insn ) ) { case LENGTH_TABLE_NONE : gcc_unreachable ( ) ; case LENGTH_TABLE_ADD : if ( GET_MODE ( operands [ 0 ] ) == QImode ) return h8300_binary_length ( insn , & addb_length_table ) ; else if ( GET_MODE ( operands [ 0 ] ) == HImode ) return h8300_binary_length ( insn , & addw_length_table ) ; else if ( GET_MODE ( operands [ 0 ] ) == SImode ) return h8300_binary_length ( insn , & addl_length_table ) ; gcc_unreachable ( ) ; case LENGTH_TABLE_LOGICB : return h8300_binary_length ( insn , & logicb_length_table ) ; case LENGTH_TABLE_MOVB : return h8300_move_length ( operands , & movb_length_table ) ; case LENGTH_TABLE_MOVW : return h8300_move_length ( operands , & movw_length_table ) ; case LENGTH_TABLE_MOVL : return h8300_move_length ( operands , & movl_length_table ) ; case LENGTH_TABLE_MOVA : return h8300_mova_length ( operands [ 0 ] , operands [ 1 ] , operands [ 2 ] ) ; case LENGTH_TABLE_MOVA_ZERO : return h8300_mova_length ( operands [ 0 ] , operands [ 1 ] , const0_rtx ) ; case LENGTH_TABLE_UNARY : return h8300_unary_length ( operands [ 0 ] ) ; case LENGTH_TABLE_MOV_IMM4 : return 2 + h8300_classify_operand ( operands [ 0 ] , 0 , 0 ) ; case LENGTH_TABLE_SHORT_IMMEDIATE : return h8300_short_immediate_length ( operands [ 0 ] ) ; case LENGTH_TABLE_BITFIELD : return h8300_bitfield_length ( operands [ 0 ] , operands [ 1 ] ) ; case LENGTH_TABLE_BITBRANCH : return h8300_bitfield_length ( operands [ 1 ] , operands [ 2 ] ) - 2 ; default : gcc_unreachable ( ) ; } } </s>

Compute the length of INSN based on its length_table attribute . OPERANDS is the array of its operands .


<s> unsigned AArch64InstrInfo :: getLoadStoreImmIdx ( unsigned Opc ) { switch ( Opc ) { default : return 2 ; case AArch64 :: LDPXi : case AArch64 :: LDPDi : case AArch64 :: STPXi : case AArch64 :: STPDi : case AArch64 :: LDNPXi : case AArch64 :: LDNPDi : case AArch64 :: STNPXi : case AArch64 :: STNPDi : case AArch64 :: LDPQi : case AArch64 :: STPQi : case AArch64 :: LDNPQi : case AArch64 :: STNPQi : case AArch64 :: LDPWi : case AArch64 :: LDPSi : case AArch64 :: STPWi : case AArch64 :: STPSi : case AArch64 :: LDNPWi : case AArch64 :: LDNPSi : case AArch64 :: STNPWi : case AArch64 :: STNPSi : return 3 ; } } </s>

Returns the index for the immediate for a given instruction .


<s>
void
HexagonFrameLowering
::
processFunctionBeforeFrameFinalized
(
MachineFunction
&
MF
,
RegScavenger
*
RS
)
const
{
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
bool
HasAlloca
=
MFI
->
hasVarSizedObjects
(
)
;
bool
NeedsAlign
=
(
MFI
->
getMaxAlignment
(
)
>
getStackAlignment
(
)
)
;
if
(
!
HasAlloca
||
!
NeedsAlign
)
return
;
unsigned
LFS
=
MFI
->
getLocalFrameSize
(
)
;
int
Offset
=
LFS
;
for
(
int
i
=
0
,
e
=
MFI
->
getObjectIndexEnd
(
)
;
i
!=
e
;
++
i
)
{
if
(
!
MFI
->
isSpillSlotObjectIndex
(
i
)
||
MFI
->
isDeadObjectIndex
(
i
)
)
continue
;
int
S
=
MFI
->
getObjectSize
(
i
)
;
LFS
+=
S
;
Offset
-=
S
;
MFI
->
mapLocalFrameObject
(
i
,
Offset
)
;
}
MFI
->
setLocalFrameSize
(
LFS
)
;
unsigned
A
=
MFI
->
getLocalFrameMaxAlign
(
)
;
assert
(
A
<=
8
&&
"Unexpected local frame alignment"
)
;
if
(
A
==
0
)
MFI
->
setLocalFrameMaxAlign
(
8
)
;
MFI
->
setUseLocalStackAllocationBlock
(
true
)
;
}
</s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> static parse_codes parse_ovld ( void ) { parse_codes result = PC_OK ; diag = & ovld_diag ; if ( ! advance_line ( ovld_file ) ) return PC_OK ; while ( result == PC_OK ) result = parse_ovld_stanza ( ) ; if ( result == PC_EOFILE ) return PC_OK ; return result ; } </s>


<s> void nvptx_output_ascii ( FILE * , const char * str , unsigned HOST_WIDE_INT size ) { for ( unsigned HOST_WIDE_INT i = 0 ; i < size ; i ++ ) nvptx_assemble_value ( str [ i ] , 1 ) ; } </s>

Output a string STR with length SIZE . As in nvptx_output_skip we ignore the FILE arg .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> unsigned PPCTTIImpl :: getNumberOfRegisters ( bool Vector ) { if ( Vector && ! ST -> hasAltivec ( ) ) return 0 ; return ST -> hasVSX ( ) ? 64 : 32 ; } </s>


"the ABI of passing aggregates with %d-byte alignment"

If defined , a C expression that gives the alignment boundary , in bits , of an argument with the specified mode and type . If it is not defined , PARM_BOUNDARY is used for all arguments . V.4 wants long longs and doubles to be double word aligned . Just testing the mode size is a boneheaded way to do this as it means that other types such as complex int are also double word aligned . However , we 're stuck with this because changing the ABI might break existing library interfaces . Quadword align Altivec/VSX vectors . Quadword align large synthetic vector types .


<s> const MCExpr * X86TargetLowering :: getPICJumpTableRelocBaseExpr ( const MachineFunction * MF , unsigned JTI , MCContext & Ctx ) const { if ( Subtarget . isPICStyleRIPRel ( ) || Subtarget . is64Bit ( ) ) return TargetLowering :: getPICJumpTableRelocBaseExpr ( MF , JTI , Ctx ) ; return MCSymbolRefExpr :: create ( MF -> getPICBaseSymbol ( ) , Ctx ) ; } </s>

This returns the relocation base for the given PIC jumptable , the same as getPICJumpTableRelocBase , but as an MCExpr .


Invoke the PassBuilder callback registration .


"Pseudo opcode found in EmitInstruction()"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> int v850_output_addr_const_extra ( FILE * file , rtx x ) { if ( GET_CODE ( x ) != TRUNCATE ) return 0 ; x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == MINUS && GET_CODE ( XEXP ( x , 0 ) ) == LABEL_REF && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == CODE_LABEL && INSN_DELETED_P ( XEXP ( XEXP ( x , 0 ) , 0 ) ) ) return 1 ; output_addr_const ( file , x ) ; return 1 ; } </s>

When assemble_integer is used to emit the offsets for a switch table it can encounter ( TRUNCATE : HI ( MINUS : SI ( LABEL_REF : SI ) ( LABEL_REF : SI ) ) ) . output_addr_const will normally barf at this , but it is OK to omit the truncate and just emit the difference of the two labels . The .hword directive will automatically handle the truncation for us . Returns 1 if rtx was handled , 0 otherwise .


<s>
void
WebAssemblyTargetAsmStreamer
::
emitImportModule
(
const
MCSymbolWasm
*
Sym
,
StringRef
ImportModule
)
{
OS
<<
"\t.import_module\t"
<<
Sym
->
getName
(
)
<<
", "
<<
ImportModule
<<
'\n'
;
}
</s>

WebAssembly
WebAssembly
"\t.import_module\t"
", "


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> static bool ix86_lea_outperforms ( rtx_insn * insn , unsigned int regno0 , unsigned int regno1 , unsigned int regno2 , int split_cost , bool has_scale ) { int dist_define , dist_use ; if ( TARGET_SILVERMONT || TARGET_INTEL ) { if ( has_scale ) return true ; if ( split_cost < 1 ) return false ; if ( regno0 == regno1 || regno0 == regno2 ) return false ; return true ; } dist_define = distance_non_agu_define ( regno1 , regno2 , insn ) ; dist_use = distance_agu_use ( regno0 , insn ) ; if ( dist_define < 0 || dist_define >= LEA_MAX_STALL ) { if ( dist_use < 0 && split_cost == 0 ) return TARGET_64BIT || IX86_LEA_PRIORITY ; else return true ; } dist_define += split_cost + IX86_LEA_PRIORITY ; if ( dist_use < 0 ) return dist_define > LEA_MAX_STALL ; return dist_define >= dist_use ; } </s>

Return true if usage of lea INSN has performance advantage over a sequence of instructions . Instructions sequence has SPLIT_COST cycles higher latency than lea latency .


<s> unsigned bfin_local_alignment ( tree type , unsigned align ) { if ( TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && wi :: gtu_p ( TYPE_SIZE ( type ) , 8 ) && align < 32 ) return 32 ; return align ; } </s>

Compute the alignment for a local variable . TYPE is the data type , and ALIGN is the alignment that the object would ordinarily have . The value of this macro is used instead of that alignment to align the object .


<s> const TargetSubtargetInfo * GCNTargetMachine :: getSubtargetImpl ( const Function & F ) const { StringRef GPU = getGPUName ( F ) ; StringRef FS = getFeatureString ( F ) ; SmallString < 128 > SubtargetKey ( GPU ) ; SubtargetKey . append ( FS ) ; auto & I = SubtargetMap [ SubtargetKey ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < GCNSubtarget > ( TargetTriple , GPU , FS , * this ) ; } I -> setScalarizeGlobalBehavior ( ScalarizeGlobal ) ; return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> Value * AArch64TargetLowering :: emitStoreConditional ( IRBuilderBase & Builder , Value * Val , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = isReleaseOrStronger ( Ord ) ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == 128 ) { Intrinsic :: ID Int = IsRelease ? Intrinsic :: aarch64_stlxp : Intrinsic :: aarch64_stxp ; Function * Stxr = Intrinsic :: getDeclaration ( M , Int ) ; Type * Int64Ty = Type :: getInt64Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int64Ty , "lo" ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , 64 ) , Int64Ty , "hi" ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall ( Stxr , { Lo , Hi , Addr } ) ; } Intrinsic :: ID Int = IsRelease ? Intrinsic :: aarch64_stlxr : Intrinsic :: aarch64_stxr ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Stxr = Intrinsic :: getDeclaration ( M , Int , Tys ) ; const DataLayout & DL = M -> getDataLayout ( ) ; IntegerType * IntValTy = Builder . getIntNTy ( DL . getTypeSizeInBits ( Val -> getType ( ) ) ) ; Val = Builder . CreateBitCast ( Val , IntValTy ) ; return Builder . CreateCall ( Stxr , { Builder . CreateZExtOrBitCast ( Val , Stxr -> getFunctionType ( ) -> getParamType ( 0 ) ) , Addr } ) ; } </s>

Perform a store-conditional operation to Addr .


<s> void func_fma_steering :: execute_fma_steering ( ) { df_set_flags ( DF_LR_RUN_DCE ) ; df_note_add_problem ( ) ; df_analyze ( ) ; df_set_flags ( DF_DEFER_INSN_RESCAN ) ; regrename_init ( true ) ; regrename_analyze ( NULL ) ; this -> analyze ( ) ; this -> rename_fma_trees ( ) ; regrename_finish ( ) ; } </s>


<s> const char * PIC16TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return NULL ; case PIC16ISD :: Lo : return "PIC16ISD::Lo" ; case PIC16ISD :: Hi : return "PIC16ISD::Hi" ; case PIC16ISD :: MTLO : return "PIC16ISD::MTLO" ; case PIC16ISD :: MTHI : return "PIC16ISD::MTHI" ; case PIC16ISD :: MTPCLATH : return "PIC16ISD::MTPCLATH" ; case PIC16ISD :: PIC16Connect : return "PIC16ISD::PIC16Connect" ; case PIC16ISD :: Banksel : return "PIC16ISD::Banksel" ; case PIC16ISD :: PIC16Load : return "PIC16ISD::PIC16Load" ; case PIC16ISD :: PIC16LdArg : return "PIC16ISD::PIC16LdArg" ; case PIC16ISD :: PIC16LdWF : return "PIC16ISD::PIC16LdWF" ; case PIC16ISD :: PIC16Store : return "PIC16ISD::PIC16Store" ; case PIC16ISD :: PIC16StWF : return "PIC16ISD::PIC16StWF" ; case PIC16ISD :: BCF : return "PIC16ISD::BCF" ; case PIC16ISD :: LSLF : return "PIC16ISD::LSLF" ; case PIC16ISD :: LRLF : return "PIC16ISD::LRLF" ; case PIC16ISD :: RLF : return "PIC16ISD::RLF" ; case PIC16ISD :: RRF : return "PIC16ISD::RRF" ; case PIC16ISD :: CALL : return "PIC16ISD::CALL" ; case PIC16ISD :: CALLW : return "PIC16ISD::CALLW" ; case PIC16ISD :: SUBCC : return "PIC16ISD::SUBCC" ; case PIC16ISD :: SELECT_ICC : return "PIC16ISD::SELECT_ICC" ; case PIC16ISD :: BRCOND : return "PIC16ISD::BRCOND" ; case PIC16ISD :: Dummy : return "PIC16ISD::Dummy" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


"use_as_extended_reg: converting non-extending mem load in "

"use_as_extended_reg: dest reg %d of extending insn %d is "

Given a reg that is known to be sign or zero extended at some insn , take the appropriate measures so that the extended value can be used as a reg at the specified insn and return the resulting reg rtx .


<s> static bool arm_default_short_enums ( void ) { return TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX ; } </s>

AAPCS based ABIs use short enums by default .


<s> static bool arm_block_set_unaligned_vect ( rtx dstbase , unsigned HOST_WIDE_INT length , unsigned HOST_WIDE_INT value , unsigned HOST_WIDE_INT align ) { unsigned int i , nelt_v16 , nelt_v8 , nelt_mode ; rtx dst , mem ; rtx val_vec , reg ; rtx ( * gen_func ) ( rtx , rtx ) ; machine_mode mode ; unsigned HOST_WIDE_INT v = value ; unsigned int offset = 0 ; gcc_assert ( ( align & 0x3 ) != 0 ) ; nelt_v8 = GET_MODE_NUNITS ( V8QImode ) ; nelt_v16 = GET_MODE_NUNITS ( V16QImode ) ; if ( length >= nelt_v16 ) { mode = V16QImode ; gen_func = gen_movmisalignv16qi ; } else { mode = V8QImode ; gen_func = gen_movmisalignv8qi ; } nelt_mode = GET_MODE_NUNITS ( mode ) ; gcc_assert ( length >= nelt_mode ) ; if ( ! arm_block_set_vect_profit_p ( length , align , mode ) ) return false ; dst = copy_addr_to_reg ( XEXP ( dstbase , 0 ) ) ; mem = adjust_automodify_address ( dstbase , mode , dst , offset ) ; v = sext_hwi ( v , BITS_PER_WORD ) ; reg = gen_reg_rtx ( mode ) ; val_vec = gen_const_vec_duplicate ( mode , GEN_INT ( v ) ) ; emit_move_insn ( reg , val_vec ) ; for ( i = 0 ; ( i + nelt_mode <= length ) ; i += nelt_mode ) { emit_insn ( ( * gen_func ) ( mem , reg ) ) ; if ( i + 2 * nelt_mode <= length ) { emit_insn ( gen_add2_insn ( dst , GEN_INT ( nelt_mode ) ) ) ; offset += nelt_mode ; mem = adjust_automodify_address ( dstbase , mode , dst , offset ) ; } } gcc_assert ( ( i + nelt_v8 ) > length || mode == V16QImode ) ; if ( i + nelt_v8 < length ) { emit_insn ( gen_add2_insn ( dst , GEN_INT ( length - i ) ) ) ; offset += length - i ; mem = adjust_automodify_address ( dstbase , mode , dst , offset ) ; if ( ( length & 1 ) != 0 && align >= 2 ) set_mem_align ( mem , BITS_PER_UNIT ) ; emit_insn ( gen_movmisalignv16qi ( mem , reg ) ) ; } else if ( i < length && i + nelt_v8 >= length ) { if ( mode == V16QImode ) reg = gen_lowpart ( V8QImode , reg ) ; emit_insn ( gen_add2_insn ( dst , GEN_INT ( ( length - i ) + ( nelt_mode - nelt_v8 ) ) ) ) ; offset += ( length - i ) + ( nelt_mode - nelt_v8 ) ; mem = adjust_automodify_address ( dstbase , V8QImode , dst , offset ) ; if ( ( length & 1 ) != 0 && align >= 2 ) set_mem_align ( mem , BITS_PER_UNIT ) ; emit_insn ( gen_movmisalignv8qi ( mem , reg ) ) ; } return true ; } </s>

Set a block of memory using vectorization instructions for the unaligned case . We fill the first LENGTH bytes of the memory area starting from DSTBASE with byte constant VALUE . ALIGN is the alignment requirement of memory . Return TRUE if succeeded .


<s> bool XNCMTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { LoadSDNode * LD = cast < LoadSDNode > ( N ) ; if ( LD -> getExtensionType ( ) != ISD :: NON_EXTLOAD ) return false ; EVT VT = LD -> getMemoryVT ( ) ; if ( VT != MVT :: i8 && VT != MVT :: i16 ) return false ; if ( Op -> getOpcode ( ) != ISD :: ADD ) return false ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ) { uint64_t RHSC = RHS -> getZExtValue ( ) ; if ( ( VT == MVT :: i16 && RHSC != 2 ) || ( VT == MVT :: i8 && RHSC != 1 ) ) return false ; Base = Op -> getOperand ( 0 ) ; Offset = DAG . getConstant ( RHSC , VT ) ; AM = ISD :: POST_INC ; return true ; } return false ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .


<s> void MipsELFStreamer :: EmitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) { MCELFStreamer :: EmitInstruction ( Inst , STI ) ; MCContext & Context = getContext ( ) ; const MCRegisterInfo * MCRegInfo = Context . getRegisterInfo ( ) ; for ( unsigned OpIndex = 0 ; OpIndex < Inst . getNumOperands ( ) ; ++ OpIndex ) { const MCOperand & Op = Inst . getOperand ( OpIndex ) ; if ( ! Op . isReg ( ) ) continue ; unsigned Reg = Op . getReg ( ) ; RegInfoRecord -> SetPhysRegUsed ( Reg , MCRegInfo ) ; } } </s>


<s> bool pcrel_opt_valid_mem_p ( rtx reg , machine_mode mode , rtx mem ) { enum non_prefixed_form non_prefixed = reg_to_non_prefixed ( reg , mode ) ; if ( non_prefixed == NON_PREFIXED_X ) return false ; rtx addr = XEXP ( mem , 0 ) ; enum insn_form iform = address_to_insn_form ( addr , mode , non_prefixed ) ; return ( iform == INSN_FORM_BASE_REG || iform == INSN_FORM_D || iform == INSN_FORM_DS || iform == INSN_FORM_DQ ) ; } </s>

Return true if an REG with a given MODE is loaded from or stored into a MEM location uses a non-prefixed D/DS/DQ-form address . This is used to validate the load or store with the PCREL_OPT optimization to make sure it is an instruction that can be optimized . We need to specify the MODE separately from the REG to allow for loads that include zero/sign/float extension .


<s> static void seh_frame_related_expr ( FILE * f , struct seh_frame_state * seh , rtx pat ) { rtx dest , src ; HOST_WIDE_INT addend ; if ( GET_CODE ( pat ) == PARALLEL || GET_CODE ( pat ) == SEQUENCE ) { int i , n = XVECLEN ( pat , 0 ) , pass , npass ; npass = ( GET_CODE ( pat ) == PARALLEL ? 2 : 1 ) ; for ( pass = 0 ; pass < npass ; ++ pass ) for ( i = 0 ; i < n ; ++ i ) { rtx ele = XVECEXP ( pat , 0 , i ) ; if ( GET_CODE ( ele ) != SET ) continue ; dest = SET_DEST ( ele ) ; if ( i == 0 || RTX_FRAME_RELATED_P ( ele ) ) { if ( ( MEM_P ( dest ) ^ pass ) || npass == 1 ) seh_frame_related_expr ( f , seh , ele ) ; } } return ; } dest = SET_DEST ( pat ) ; src = SET_SRC ( pat ) ; switch ( GET_CODE ( dest ) ) { case REG : switch ( GET_CODE ( src ) ) { case REG : gcc_assert ( src == stack_pointer_rtx ) ; gcc_assert ( dest == hard_frame_pointer_rtx ) ; seh_cfa_adjust_cfa ( f , seh , pat ) ; break ; case PLUS : addend = INTVAL ( XEXP ( src , 1 ) ) ; src = XEXP ( src , 0 ) ; if ( dest == hard_frame_pointer_rtx ) seh_cfa_adjust_cfa ( f , seh , pat ) ; else if ( dest == stack_pointer_rtx ) { gcc_assert ( src == stack_pointer_rtx ) ; seh_emit_stackalloc ( f , seh , addend ) ; } else gcc_unreachable ( ) ; break ; default : gcc_unreachable ( ) ; } break ; case MEM : dest = XEXP ( dest , 0 ) ; if ( GET_CODE ( dest ) == PRE_DEC ) { gcc_checking_assert ( GET_MODE ( src ) == Pmode ) ; gcc_checking_assert ( REG_P ( src ) ) ; seh_emit_push ( f , seh , src ) ; } else seh_cfa_offset ( f , seh , pat ) ; break ; default : gcc_unreachable ( ) ; } } </s>


<s> static int xtensa_insn_cost ( rtx_insn * insn , bool speed ) { if ( ! ( recog_memoized ( insn ) < 0 ) ) { int len = get_attr_length ( insn ) ; if ( len == 0 ) return COSTS_N_INSNS ( 0 ) ; if ( speed ) { int n = ( len + 2 ) / 3 ; if ( xtensa_is_insn_L32R_p ( insn ) ) return COSTS_N_INSNS ( 1 + xtensa_extra_l32r_costs ) ; switch ( get_attr_type ( insn ) ) { case TYPE_STORE : case TYPE_MOVE : case TYPE_ARITH : case TYPE_MULTI : case TYPE_NOP : case TYPE_FSTORE : return COSTS_N_INSNS ( n ) ; case TYPE_LOAD : return COSTS_N_INSNS ( n - 1 + 2 ) ; case TYPE_JUMP : case TYPE_CALL : return COSTS_N_INSNS ( n - 1 + 3 ) ; case TYPE_FCONV : case TYPE_FLOAD : case TYPE_MUL16 : case TYPE_MUL32 : case TYPE_RSR : return COSTS_N_INSNS ( n * 2 ) ; case TYPE_FMADD : return COSTS_N_INSNS ( n * 4 ) ; case TYPE_DIV32 : return COSTS_N_INSNS ( n * 16 ) ; default : break ; } } else { if ( get_attr_type ( insn ) != TYPE_UNKNOWN ) { if ( xtensa_is_insn_L32R_p ( insn ) ) len = 3 + 4 ; return ( COSTS_N_INSNS ( len ) + 1 ) / 3 ; } } } return pattern_cost ( PATTERN ( insn ) , speed ) ; } </s>

Compute a relative costs of RTL insns . This is necessary in order to achieve better RTL insn splitting/combination result .


<s> static void mips_output_function_epilogue ( FILE * ) { const char * fnname ; SET_REGNO ( pic_offset_table_rtx , GLOBAL_POINTER_REGNUM ) ; mips_output_cplocal ( ) ; if ( cfun -> machine -> all_noreorder_p ) { mips_pop_asm_switch ( & mips_nomacro ) ; mips_pop_asm_switch ( & mips_noreorder ) ; } fnname = XSTR ( XEXP ( DECL_RTL ( current_function_decl ) , 0 ) , 0 ) ; mips_end_function_definition ( fnname ) ; } </s>


<s> bool M680x0FrameLowering :: canSimplifyCallFramePseudos ( const MachineFunction & MF ) const { return hasReservedCallFrame ( MF ) || ( hasFP ( MF ) && ! TRI -> needsStackRealignment ( MF ) ) || TRI -> hasBasePointer ( MF ) ; } </s>

canSimplifyCallFramePseudos - If there is a reserved call frame , the call frame pseudos can be simplified .


<s> static reg_class_t pdp11_preferred_output_reload_class ( rtx x , reg_class_t rclass ) { if ( rclass == FPU_REGS ) return LOAD_FPU_REGS ; if ( rclass == ALL_REGS ) { if ( FLOAT_MODE_P ( GET_MODE ( x ) ) ) return LOAD_FPU_REGS ; else return GENERAL_REGS ; } return rclass ; } </s>

TARGET_PREFERRED_OUTPUT_RELOAD_CLASS Given an rtx X being reloaded into a reg required to be in class CLASS , return the class of reg to actually use . In general this is just CLASS ; but on some machines in some cases it is preferable to use a more restrictive class . loading is easier into LOAD_FPU_REGS than FPU_REGS !


<s> void pop ( int rn , enum machine_mode mode ) { emit_insn ( gen_pop ( gen_rtx_REG ( mode , rn ) , mode ) ) ; } </s>

Output RTL to pop register RN from the stack .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
InfosBE
[
PPC
::
NumTargetFixupKinds
]
=
{
{
"fixup_ppc_br24"
,
6
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_brcond14"
,
16
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_br24abs"
,
6
,
24
,
0
}
,
{
"fixup_ppc_brcond14abs"
,
16
,
14
,
0
}
,
{
"fixup_ppc_half16"
,
0
,
16
,
0
}
,
{
"fixup_ppc_half16ds"
,
0
,
14
,
0
}
,
{
"fixup_ppc_nofixup"
,
0
,
0
,
0
}
}
;
const
static
MCFixupKindInfo
InfosLE
[
PPC
::
NumTargetFixupKinds
]
=
{
{
"fixup_ppc_br24"
,
2
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_brcond14"
,
2
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_br24abs"
,
2
,
24
,
0
}
,
{
"fixup_ppc_brcond14abs"
,
2
,
14
,
0
}
,
{
"fixup_ppc_half16"
,
0
,
16
,
0
}
,
{
"fixup_ppc_half16ds"
,
2
,
14
,
0
}
,
{
"fixup_ppc_nofixup"
,
0
,
0
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
(
Endian
==
support
::
little
InfosLE
:
InfosBE
)
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> MCSymbol * DLXMCInstLower :: GetExternalSymbolSymbol ( const MachineOperand & MO ) const { return Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; } </s>

Return the MCSymbol for the specified ExternalSymbol .


<s>
bool
AMDGPUAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Name
=
parseMnemonicSuffix
(
Name
)
;
Operands
.
push_back
(
AMDGPUOperand
::
CreateToken
(
this
,
Name
,
NameLoc
)
)
;
bool
IsMIMG
=
Name
.
startswith
(
"image_"
)
;
while
(
!
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
{
OperandMode
Mode
=
OperandMode_Default
;
if
(
IsMIMG
&&
isGFX10
(
)
&&
Operands
.
size
(
)
==
2
)
Mode
=
OperandMode_NSA
;
OperandMatchResultTy
Res
=
parseOperand
(
Operands
,
Name
,
Mode
)
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
Parser
.
Lex
(
)
;
if
(
Res
!=
MatchOperand_Success
)
{
if
(
!
Parser
.
hasPendingError
(
)
)
{
StringRef
Msg
=
(
Res
==
MatchOperand_ParseFail
)
"failed parsing operand."
:
"not a valid operand."
;
Error
(
getLexer
(
)
.
getLoc
(
)
,
Msg
)
;
}
while
(
!
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
{
Parser
.
Lex
(
)
;
}
return
true
;
}
}
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

AMDGPU
AMDGPU
AMDGPU
"image_"
2
"failed parsing operand."
"not a valid operand."


<s> void SparcELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; } </s>

This method must be called before any actual lowering is done .


<s>
const
MCPhysReg
*
Z80RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
switch
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
Is24Bit
CSR_EZ80_C_SaveList
:
CSR_Z80_C_SaveList
;
case
CallingConv
::
PreserveAll
:
case
CallingConv
::
Z80_LibCall
:
case
CallingConv
::
Z80_LibCall_AC
:
case
CallingConv
::
Z80_LibCall_BC
:
case
CallingConv
::
Z80_LibCall_C
:
case
CallingConv
::
Z80_LibCall_L
:
return
Is24Bit
CSR_EZ80_AllRegs_SaveList
:
CSR_Z80_AllRegs_SaveList
;
}
}
</s>


<s>
virtual
SDValue
LowerCall
(
CallLoweringInfo
&
CLI
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
CLI
.
Callee
.
dump
(
)
;
llvm_unreachable
(
"Undefined function"
)
;
}
</s>

This hook must be implemented to lower calls into the specified DAG .


<s> bool ARMFastISel :: fastLowerArguments ( ) { if ( ! FuncInfo . CanLowerReturn ) return false ; const Function * F = FuncInfo . Fn ; if ( F -> isVarArg ( ) ) return false ; CallingConv :: ID CC = F -> getCallingConv ( ) ; switch ( CC ) { default : return false ; case CallingConv :: Fast : case CallingConv :: C : case CallingConv :: ARM_AAPCS_VFP : case CallingConv :: ARM_AAPCS : case CallingConv :: ARM_APCS : case CallingConv :: Swift : break ; } for ( const Argument & Arg : F -> args ( ) ) { if ( Arg . getArgNo ( ) >= 4 ) return false ; if ( Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: ByVal ) ) return false ; Type * ArgTy = Arg . getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( DL , ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : break ; default : return false ; } } static const MCPhysReg GPRArgRegs [ ] = { ARM :: R0 , ARM :: R1 , ARM :: R2 , ARM :: R3 } ; const TargetRegisterClass * RC = & ARM :: rGPRRegClass ; for ( const Argument & Arg : F -> args ( ) ) { unsigned ArgNo = Arg . getArgNo ( ) ; unsigned SrcReg = GPRArgRegs [ ArgNo ] ; unsigned DstReg = FuncInfo . MF -> addLiveIn ( SrcReg , RC ) ; unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( DstReg , getKillRegState ( true ) ) ; updateValueMap ( & Arg , ResultReg ) ; } return true ; } </s>

This method is called by target-independent code to do target- specific argument lowering .


<s> bool sh_small_register_classes_for_mode_p ( machine_mode mode ATTRIBUTE_UNUSED ) { return ( ! TARGET_SHMEDIA ) ; } </s>

Return true if registers in machine mode MODE will likely be allocated to registers in small register classes .


"LR & FP are always handled in emitPrologue"

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static void nvptx_goacc_reduction ( gcall * call ) { unsigned code = ( unsigned ) TREE_INT_CST_LOW ( gimple_call_arg ( call , 0 ) ) ; offload_attrs oa ; populate_offload_attrs ( & oa ) ; switch ( code ) { case IFN_GOACC_REDUCTION_SETUP : nvptx_goacc_reduction_setup ( call , & oa ) ; break ; case IFN_GOACC_REDUCTION_INIT : nvptx_goacc_reduction_init ( call , & oa ) ; break ; case IFN_GOACC_REDUCTION_FINI : nvptx_goacc_reduction_fini ( call , & oa ) ; break ; case IFN_GOACC_REDUCTION_TEARDOWN : nvptx_goacc_reduction_teardown ( call , & oa ) ; break ; default : gcc_unreachable ( ) ; } } </s>


<s> void rs6000_live_on_entry ( bitmap regs ) { if ( flag_split_stack ) bitmap_set_bit ( regs , 12 ) ; } </s>

We may have to tell the dataflow pass that the split stack prologue is initializing a register .


<s> TargetLowering :: AtomicExpansionKind ARMTargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { if ( AI -> isFloatingPointOperation ( ) ) return AtomicExpansionKind :: CmpXChg ; unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; bool hasAtomicRMW ; if ( Subtarget -> isMClass ( ) ) hasAtomicRMW = Subtarget -> hasV8MBaselineOps ( ) ; else if ( Subtarget -> isThumb ( ) ) hasAtomicRMW = Subtarget -> hasV7Ops ( ) ; else hasAtomicRMW = Subtarget -> hasV6Ops ( ) ; if ( Size <= ( Subtarget -> isMClass ( ) ? 32U : 64U ) && hasAtomicRMW ) { if ( getTargetMachine ( ) . getOptLevel ( ) == CodeGenOpt :: None ) return AtomicExpansionKind :: CmpXChg ; return AtomicExpansionKind :: LLSC ; } return AtomicExpansionKind :: None ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> static bool cr16_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( ( GET_MODE_SIZE ( mode ) >= 4 ) && ( regno == 11 ) ) return false ; if ( mode == DImode || mode == DFmode ) { if ( ( regno > 8 ) || ( regno & 1 ) ) return false ; return true ; } if ( ( TARGET_INT32 ) && ( ( regno >= 12 ) && ( GET_MODE_SIZE ( mode ) < 4 ) ) ) return false ; if ( GET_MODE_CLASS ( mode ) == MODE_CC ) return false ; return true ; } </s>

Return 1 if hard register REGNO can hold a value of machine-mode MODE .


<s>
bool
FixupBWInstPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
!
FixupBWInsts
||
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
this
->
MF
=
&
MF
;
TII
=
MF
.
getSubtarget
<
X86Subtarget
>
(
)
.
getInstrInfo
(
)
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
PSI
=
&
getAnalysis
<
ProfileSummaryInfoWrapperPass
>
(
)
.
getPSI
(
)
;
MBFI
=
(
PSI
&&
PSI
->
hasProfileSummary
(
)
)
&
getAnalysis
<
LazyMachineBlockFrequencyInfoPass
>
(
)
.
getBFI
(
)
:
nullptr
;
LiveRegs
.
init
(
TII
->
getRegisterInfo
(
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Start X86FixupBWInsts\n"
;
)
;
for
(
auto
&
MBB
:
MF
)
processBasicBlock
(
MF
,
MBB
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"End X86FixupBWInsts\n"
;
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


"%<-mcall-ms2sysv-xlogues%> is not compatible with %s"

Emits a warning for unsupported msabi to sysv pro/epilogues .


<s> Sched :: Preference PPCTargetLowering :: getSchedulingPreference ( SDNode * N ) const { if ( DisableILPPref || Subtarget . enableMachineScheduler ( ) ) return TargetLowering :: getSchedulingPreference ( N ) ; return Sched :: ILP ; } </s>


<s> void print ( raw_ostream & OS ) const override { switch ( Kind ) { case k_Register : OS << "Reg<" << Reg . Num << ">" ; break ; case k_Immediate : OS << "Imm<" << ( ( const MCConstantExpr * ) Imm . Val ) -> getValue ( ) << ">" ; break ; case k_Token : OS << Tok . Data ; break ; } } </s>

print - Print a debug representation of the operand to the given stream .


<s> const MipsSubtarget * MipsTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool hasMips16Attr = ! F . getFnAttribute ( "mips16" ) . hasAttribute ( Attribute :: None ) ; bool hasNoMips16Attr = ! F . getFnAttribute ( "nomips16" ) . hasAttribute ( Attribute :: None ) ; bool softFloat = F . hasFnAttribute ( "use-soft-float" ) && F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( hasMips16Attr ) FS += FS . empty ( ) ? "+mips16" : ",+mips16" ; else if ( hasNoMips16Attr ) FS += FS . empty ( ) ? "-mips16" : ",-mips16" ; if ( softFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < MipsSubtarget > ( TargetTriple , CPU , FS , isLittle , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

Mips Mips Mips "target-cpu" "target-features" Mips "mips16" Mips "nomips16" "use-soft-float" "use-soft-float" "true" Mips "+mips16" ",+mips16" Mips "-mips16" ",-mips16" "+soft-float" ",+soft-float" Mips


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { TM = static_cast < const PPCTargetMachine * > ( & MF . getTarget ( ) ) ; TII = TM -> getInstrInfo ( ) ; bool Changed = false ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed = true ; } return Changed ; } </s>


<s> bool aarch64_float_const_representable_p ( rtx x ) { int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1 ; int exponent ; unsigned HOST_WIDE_INT mantissa , mask ; REAL_VALUE_TYPE r , m ; bool fail ; if ( ! CONST_DOUBLE_P ( x ) ) return false ; if ( GET_MODE ( x ) == VOIDmode || GET_MODE ( x ) == HFmode ) return false ; r = * CONST_DOUBLE_REAL_VALUE ( x ) ; if ( REAL_VALUE_ISINF ( r ) || REAL_VALUE_ISNAN ( r ) || REAL_VALUE_MINUS_ZERO ( r ) ) return false ; r = real_value_abs ( & r ) ; exponent = REAL_EXP ( & r ) ; real_ldexp ( & m , & r , point_pos - exponent ) ; wide_int w = real_to_integer ( & m , & fail , HOST_BITS_PER_WIDE_INT * 2 ) ; if ( w . ulow ( ) != 0 ) return false ; mantissa = w . elt ( 1 ) ; point_pos -= HOST_BITS_PER_WIDE_INT ; mask = ( ( unsigned HOST_WIDE_INT ) 1 << ( point_pos - 5 ) ) - 1 ; if ( ( mantissa & mask ) != 0 ) return false ; mantissa >>= point_pos - 5 ; if ( mantissa == 0 ) return false ; mantissa &= ~ ( 1 << 4 ) ; gcc_assert ( mantissa <= 15 ) ; exponent = 5 - exponent ; return ( exponent >= 0 && exponent <= 7 ) ; } </s>

Return true iff X can be represented by a quarter-precision floating point immediate operand X . Note , we can not represent 0.0 .


<s> DecodeStatus FISCDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & VStream , raw_ostream & CStream ) const { uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Bytes , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return Result ; Result = decodeInstruction ( DecoderTableFISC32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s> static void emit_unlikely_jump ( rtx_code code , rtx label ) { rtx x ; x = gen_rtx_REG ( BImode , SR_F_REGNUM ) ; x = gen_rtx_fmt_ee ( code , VOIDmode , x , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , label , pc_rtx ) ; emit_jump_insn ( gen_rtx_SET ( pc_rtx , x ) ) ; } </s>

Mark the previous jump instruction as unlikely .


<s> EVT X86TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , const AttributeList & FuncAttributes ) const { if ( ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { if ( Size >= 16 && ( ! Subtarget . isUnalignedMem16Slow ( ) || ( ( DstAlign == 0 || DstAlign >= 16 ) && ( SrcAlign == 0 || SrcAlign >= 16 ) ) ) ) { if ( Size >= 64 && Subtarget . hasAVX512 ( ) && ( Subtarget . getPreferVectorWidth ( ) >= 512 ) ) { return Subtarget . hasBWI ( ) ? MVT :: v64i8 : MVT :: v16i32 ; } if ( Size >= 32 && Subtarget . hasAVX ( ) && ( Subtarget . getPreferVectorWidth ( ) >= 256 ) ) { return MVT :: v32i8 ; } if ( Subtarget . hasSSE2 ( ) && ( Subtarget . getPreferVectorWidth ( ) >= 128 ) ) return MVT :: v16i8 ; if ( Subtarget . hasSSE1 ( ) && ( Subtarget . is64Bit ( ) || Subtarget . hasX87 ( ) ) && ( Subtarget . getPreferVectorWidth ( ) >= 128 ) ) return MVT :: v4f32 ; } else if ( ( ! IsMemset || ZeroMemset ) && ! MemcpyStrSrc && Size >= 8 && ! Subtarget . is64Bit ( ) && Subtarget . hasSSE2 ( ) ) { return MVT :: f64 ; } } if ( Subtarget . is64Bit ( ) && Size >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s>
bool
ARMTargetLowering
::
canCombineStoreAndExtract
(
Type
*
VectorTy
,
Value
*
Idx
,
unsigned
&
Cost
)
const
{
if
(
!
Subtarget
->
hasNEON
(
)
)
return
false
;
if
(
VectorTy
->
isFPOrFPVectorTy
(
)
)
return
false
;
if
(
!
isa
<
ConstantInt
>
(
Idx
)
)
return
false
;
assert
(
VectorTy
->
isVectorTy
(
)
&&
"VectorTy is not a vector type"
)
;
unsigned
BitWidth
=
cast
<
VectorType
>
(
VectorTy
)
->
getBitWidth
(
)
;
if
(
BitWidth
==
64
||
BitWidth
==
128
)
{
Cost
=
0
;
return
true
;
}
return
false
;
}
</s>

Return true if the target can combine store ( extractelement VectorTy , Idx ) .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const override { return createLEGELFObjectWriter ( OS , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static section * riscv_elf_select_rtx_section ( enum machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ) { section * s = default_elf_select_rtx_section ( mode , x , align ) ; if ( riscv_size_ok_for_small_data_p ( GET_MODE_SIZE ( mode ) ) ) { if ( strncmp ( s -> named . name , ".rodata.cst" , strlen ( ".rodata.cst" ) ) == 0 ) { char * name = ( char * ) alloca ( strlen ( s -> named . name ) + 2 ) ; sprintf ( name , ".s%s" , s -> named . name + 1 ) ; return get_section ( name , s -> named . common . flags , NULL ) ; } if ( s == data_section ) return sdata_section ; } return s ; } </s>

Return a section for X , handling small data .