<s>
bool
shouldForceRelocation
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
)
override
{
switch
(
Fixup
.
getTargetKind
(
)
)
{
default
:
llvm_unreachable
(
"Unknown Fixup Kind!"
)
;
case
fixup_Hexagon_LO16
:
case
fixup_Hexagon_HI16
:
case
fixup_Hexagon_16
:
case
fixup_Hexagon_8
:
case
fixup_Hexagon_GPREL16_0
:
case
fixup_Hexagon_GPREL16_1
:
case
fixup_Hexagon_GPREL16_2
:
case
fixup_Hexagon_GPREL16_3
:
case
fixup_Hexagon_HL16
:
case
fixup_Hexagon_32_6_X
:
case
fixup_Hexagon_16_X
:
case
fixup_Hexagon_12_X
:
case
fixup_Hexagon_11_X
:
case
fixup_Hexagon_10_X
:
case
fixup_Hexagon_9_X
:
case
fixup_Hexagon_8_X
:
case
fixup_Hexagon_7_X
:
case
fixup_Hexagon_6_X
:
case
fixup_Hexagon_COPY
:
case
fixup_Hexagon_GLOB_DAT
:
case
fixup_Hexagon_JMP_SLOT
:
case
fixup_Hexagon_RELATIVE
:
case
fixup_Hexagon_PLT_B22_PCREL
:
case
fixup_Hexagon_GOTREL_LO16
:
case
fixup_Hexagon_GOTREL_HI16
:
case
fixup_Hexagon_GOTREL_32
:
case
fixup_Hexagon_GOT_LO16
:
case
fixup_Hexagon_GOT_HI16
:
case
fixup_Hexagon_GOT_32
:
case
fixup_Hexagon_GOT_16
:
case
fixup_Hexagon_DTPMOD_32
:
case
fixup_Hexagon_DTPREL_LO16
:
case
fixup_Hexagon_DTPREL_HI16
:
case
fixup_Hexagon_DTPREL_32
:
case
fixup_Hexagon_DTPREL_16
:
case
fixup_Hexagon_GD_PLT_B22_PCREL
:
case
fixup_Hexagon_LD_PLT_B22_PCREL
:
case
fixup_Hexagon_GD_GOT_LO16
:
case
fixup_Hexagon_GD_GOT_HI16
:
case
fixup_Hexagon_GD_GOT_32
:
case
fixup_Hexagon_GD_GOT_16
:
case
fixup_Hexagon_LD_GOT_LO16
:
case
fixup_Hexagon_LD_GOT_HI16
:
case
fixup_Hexagon_LD_GOT_32
:
case
fixup_Hexagon_LD_GOT_16
:
case
fixup_Hexagon_IE_LO16
:
case
fixup_Hexagon_IE_HI16
:
case
fixup_Hexagon_IE_32
:
case
fixup_Hexagon_IE_16
:
case
fixup_Hexagon_IE_GOT_LO16
:
case
fixup_Hexagon_IE_GOT_HI16
:
case
fixup_Hexagon_IE_GOT_32
:
case
fixup_Hexagon_IE_GOT_16
:
case
fixup_Hexagon_TPREL_LO16
:
case
fixup_Hexagon_TPREL_HI16
:
case
fixup_Hexagon_TPREL_32
:
case
fixup_Hexagon_TPREL_16
:
case
fixup_Hexagon_GOTREL_32_6_X
:
case
fixup_Hexagon_GOTREL_16_X
:
case
fixup_Hexagon_GOTREL_11_X
:
case
fixup_Hexagon_GOT_32_6_X
:
case
fixup_Hexagon_GOT_16_X
:
case
fixup_Hexagon_GOT_11_X
:
case
fixup_Hexagon_DTPREL_32_6_X
:
case
fixup_Hexagon_DTPREL_16_X
:
case
fixup_Hexagon_DTPREL_11_X
:
case
fixup_Hexagon_GD_GOT_32_6_X
:
case
fixup_Hexagon_GD_GOT_16_X
:
case
fixup_Hexagon_GD_GOT_11_X
:
case
fixup_Hexagon_LD_GOT_32_6_X
:
case
fixup_Hexagon_LD_GOT_16_X
:
case
fixup_Hexagon_LD_GOT_11_X
:
case
fixup_Hexagon_IE_32_6_X
:
case
fixup_Hexagon_IE_16_X
:
case
fixup_Hexagon_IE_GOT_32_6_X
:
case
fixup_Hexagon_IE_GOT_16_X
:
case
fixup_Hexagon_IE_GOT_11_X
:
case
fixup_Hexagon_TPREL_32_6_X
:
case
fixup_Hexagon_TPREL_16_X
:
case
fixup_Hexagon_TPREL_11_X
:
case
fixup_Hexagon_32_PCREL
:
case
fixup_Hexagon_6_PCREL_X
:
case
fixup_Hexagon_23_REG
:
case
fixup_Hexagon_27_REG
:
case
fixup_Hexagon_GD_PLT_B22_PCREL_X
:
case
fixup_Hexagon_GD_PLT_B32_PCREL_X
:
case
fixup_Hexagon_LD_PLT_B22_PCREL_X
:
case
fixup_Hexagon_LD_PLT_B32_PCREL_X
:
return
true
;
case
fixup_Hexagon_B22_PCREL
:
break
;
case
fixup_Hexagon_B13_PCREL
:
case
fixup_Hexagon_B13_PCREL_X
:
case
fixup_Hexagon_B32_PCREL_X
:
case
fixup_Hexagon_B22_PCREL_X
:
case
fixup_Hexagon_B15_PCREL
:
case
fixup_Hexagon_B15_PCREL_X
:
case
fixup_Hexagon_B9_PCREL
:
case
fixup_Hexagon_B9_PCREL_X
:
case
fixup_Hexagon_B7_PCREL
:
case
fixup_Hexagon_B7_PCREL_X
:
if
(
DisableFixup
)
return
true
;
break
;
case
FK_Data_1
:
case
FK_Data_2
:
case
FK_Data_4
:
case
FK_PCRel_4
:
case
fixup_Hexagon_32
:
return
false
;
}
return
false
;
}
</s>

Hexagon
"Unknown Fixup Kind!"
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon


<s> bool HSAILTargetMachine :: addPassesToEmitFile ( PassManagerBase & PM , raw_pwrite_stream & Out , CodeGenFileType FT , bool DisableVerify , AnalysisID StartBefore , AnalysisID StartAfter , AnalysisID StopAfter , MachineFunctionInitializer * MFInitializer ) { return LLVMTargetMachine :: addPassesToEmitFile ( PM , Out , FT , DisableVerify , StartAfter , StopAfter , MFInitializer ) ; } </s>

Add passes to the specified pass manager to get the specified file emitted .


<s>
void
Thumb1InstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
&
ARM
::
tGPRRegClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
&
ARM
::
tGPRRegClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
,
MachineMemOperand
::
MOLoad
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tLDRspi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .

ARM
ARM::tGPRRegClass
ARM
"Unknown regclass!"
ARM::tGPRRegClass
ARM
ARM::tLDRspi
0


"unimplemented opcode in encodeInstruction()"

Encode the given Inst to bytes and append to CB .


<s> SDValue VETargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: TRUNCATE : return combineTRUNCATE ( N , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


"More vector elements requested than available!"

Split a vector value into two parts of types LoVT and HiVT .


<s> unsigned X86RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return hasFP ( MF ) ? FramePtr : StackPtr ; } </s>


<s> int AMDGPUInstrInfo :: pseudoToMCOpcode ( int Opcode ) const { int MCOp = AMDGPU :: getMCOpcode ( Opcode , AMDGPUSubtargetToSISubtarget ( ST . getGeneration ( ) ) ) ; if ( MCOp == - 1 ) return Opcode ; if ( MCOp == ( uint16_t ) - 1 ) return - 1 ; return MCOp ; } </s>

Return a target-specific opcode if Opcode is a pseudo instruction .


<s> bool AMDGPUInstructionSelector :: select ( MachineInstr & I ) { if ( I . isPHI ( ) ) return selectPHI ( I ) ; if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) { if ( I . isCopy ( ) ) return selectCOPY ( I ) ; return true ; } switch ( I . getOpcode ( ) ) { case TargetOpcode :: G_AND : case TargetOpcode :: G_OR : case TargetOpcode :: G_XOR : if ( selectG_AND_OR_XOR ( I ) ) return true ; return selectImpl ( I , * CoverageInfo ) ; case TargetOpcode :: G_ADD : case TargetOpcode :: G_SUB : if ( selectG_ADD_SUB ( I ) ) return true ; LLVM_FALLTHROUGH ; default : return selectImpl ( I , * CoverageInfo ) ; case TargetOpcode :: G_INTTOPTR : case TargetOpcode :: G_BITCAST : return selectCOPY ( I ) ; case TargetOpcode :: G_CONSTANT : case TargetOpcode :: G_FCONSTANT : return selectG_CONSTANT ( I ) ; case TargetOpcode :: G_EXTRACT : return selectG_EXTRACT ( I ) ; case TargetOpcode :: G_MERGE_VALUES : case TargetOpcode :: G_BUILD_VECTOR : case TargetOpcode :: G_CONCAT_VECTORS : return selectG_MERGE_VALUES ( I ) ; case TargetOpcode :: G_UNMERGE_VALUES : return selectG_UNMERGE_VALUES ( I ) ; case TargetOpcode :: G_GEP : return selectG_GEP ( I ) ; case TargetOpcode :: G_IMPLICIT_DEF : return selectG_IMPLICIT_DEF ( I ) ; case TargetOpcode :: G_INSERT : return selectG_INSERT ( I ) ; case TargetOpcode :: G_INTRINSIC : return selectG_INTRINSIC ( I ) ; case TargetOpcode :: G_INTRINSIC_W_SIDE_EFFECTS : return selectG_INTRINSIC_W_SIDE_EFFECTS ( I ) ; case TargetOpcode :: G_ICMP : if ( selectG_ICMP ( I ) ) return true ; return selectImpl ( I , * CoverageInfo ) ; case TargetOpcode :: G_LOAD : case TargetOpcode :: G_ATOMIC_CMPXCHG : case TargetOpcode :: G_ATOMICRMW_XCHG : case TargetOpcode :: G_ATOMICRMW_ADD : case TargetOpcode :: G_ATOMICRMW_SUB : case TargetOpcode :: G_ATOMICRMW_AND : case TargetOpcode :: G_ATOMICRMW_OR : case TargetOpcode :: G_ATOMICRMW_XOR : case TargetOpcode :: G_ATOMICRMW_MIN : case TargetOpcode :: G_ATOMICRMW_MAX : case TargetOpcode :: G_ATOMICRMW_UMIN : case TargetOpcode :: G_ATOMICRMW_UMAX : case TargetOpcode :: G_ATOMICRMW_FADD : return selectG_LOAD_ATOMICRMW ( I ) ; case TargetOpcode :: G_SELECT : return selectG_SELECT ( I ) ; case TargetOpcode :: G_STORE : return selectG_STORE ( I ) ; case TargetOpcode :: G_TRUNC : return selectG_TRUNC ( I ) ; case TargetOpcode :: G_SEXT : case TargetOpcode :: G_ZEXT : case TargetOpcode :: G_ANYEXT : return selectG_SZA_EXT ( I ) ; case TargetOpcode :: G_BRCOND : return selectG_BRCOND ( I ) ; case TargetOpcode :: G_FRAME_INDEX : return selectG_FRAME_INDEX ( I ) ; case TargetOpcode :: G_FENCE : I . setDesc ( TII . get ( AMDGPU :: ATOMIC_FENCE ) ) ; return true ; } return false ; } </s>

Select the ( possibly generic ) instruction I to only use target-specific opcodes .

AMDGPU AMDGPU SI SI SI SI AMDGPU::ATOMIC_FENCE


<s> static tree fold_build_vec_cmp ( tree_code code , tree type , tree arg0 , tree arg1 , gimple_stmt_iterator * gsi ) { tree cmp_type = truth_type_for ( type ) ; tree zero_vec = build_zero_cst ( type ) ; tree minus_one_vec = build_minus_one_cst ( type ) ; tree temp = create_tmp_reg_or_ssa_name ( cmp_type ) ; gimple * g = gimple_build_assign ( temp , code , arg0 , arg1 ) ; gsi_insert_before ( gsi , g , GSI_SAME_STMT ) ; return fold_build3 ( VEC_COND_EXPR , type , temp , minus_one_vec , zero_vec ) ; } </s>

Helper function to handle the gimple folding of a vector compare operation . This sets up true/false vectors , and uses the VEC_COND_EXPR operation . CODE indicates which comparison is to be made . ( EQ , GT , ... ) . TYPE indicates the type of the result .


<s>
void
ARMAsmBackend
::
relaxInstruction
(
const
MCInst
&
Inst
,
MCInst
&
Res
)
const
{
unsigned
RelaxedOp
=
getRelaxedOpcode
(
Inst
.
getOpcode
(
)
)
;
if
(
RelaxedOp
==
Inst
.
getOpcode
(
)
)
{
SmallString
<
256
>
Tmp
;
raw_svector_ostream
OS
(
Tmp
)
;
Inst
.
dump_pretty
(
OS
)
;
OS
<<
"\n"
;
report_fatal_error
(
"unexpected instruction to relax: "
+
OS
.
str
(
)
)
;
}
if
(
(
Inst
.
getOpcode
(
)
==
ARM
::
tCBZ
||
Inst
.
getOpcode
(
)
==
ARM
::
tCBNZ
)
&&
RelaxedOp
==
ARM
::
tHINT
)
{
Res
.
setOpcode
(
RelaxedOp
)
;
Res
.
addOperand
(
MCOperand
::
CreateImm
(
0
)
)
;
Res
.
addOperand
(
MCOperand
::
CreateImm
(
14
)
)
;
Res
.
addOperand
(
MCOperand
::
CreateReg
(
0
)
)
;
return
;
}
Res
=
Inst
;
Res
.
setOpcode
(
RelaxedOp
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> void PPCFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - 1 ; bool DisableRedZone = MF . getFunction ( ) -> getFnAttributes ( ) . hasAttribute ( Attributes :: NoRedZone ) ; if ( ! DisableRedZone && FrameSize <= 224 && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! ( Subtarget . isPPC64 ( ) && Subtarget . isSVR4ABI ( ) && spillsCR ( MF ) ) && ( ! ALIGN_STACK || MaxAlign <= TargetAlign ) ) { MFI -> setStackSize ( 0 ) ; return ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getMinCallFrameSize ( Subtarget . isPPC64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; MFI -> setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s> BitVector SparcRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( SP :: G1 ) ; Reserved . set ( SP :: G2 ) ; Reserved . set ( SP :: G3 ) ; Reserved . set ( SP :: G4 ) ; Reserved . set ( SP :: O6 ) ; Reserved . set ( SP :: I6 ) ; Reserved . set ( SP :: I7 ) ; Reserved . set ( SP :: G0 ) ; Reserved . set ( SP :: G5 ) ; Reserved . set ( SP :: G6 ) ; Reserved . set ( SP :: G7 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> unsigned getNumFixupKinds ( ) const override { return Cpu0 :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s>
static
void
handle_special_swappables
(
swap_web_entry
*
insn_entry
,
unsigned
i
)
{
rtx_insn
*
insn
=
insn_entry
[
i
]
.
insn
;
rtx
body
=
PATTERN
(
insn
)
;
switch
(
insn_entry
[
i
]
.
special_handling
)
{
default
:
gcc_unreachable
(
)
;
case
SH_CONST_VECTOR
:
{
gcc_assert
(
GET_CODE
(
body
)
==
SET
)
;
rtx
rhs
=
SET_SRC
(
body
)
;
swap_const_vector_halves
(
rhs
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Swapping constant halves in insn %d\n"
,
i
)
;
break
;
}
case
SH_SUBREG
:
adjust_subreg_index
(
body
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Adjusting subreg in insn %d\n"
,
i
)
;
break
;
case
SH_NOSWAP_LD
:
permute_load
(
insn
)
;
break
;
case
SH_NOSWAP_ST
:
permute_store
(
insn
)
;
break
;
case
SH_EXTRACT
:
adjust_extract
(
insn
)
;
break
;
case
SH_SPLAT
:
adjust_splat
(
insn
)
;
break
;
case
SH_XXPERMDI
:
adjust_xxpermdi
(
insn
)
;
break
;
case
SH_CONCAT
:
adjust_concat
(
insn
)
;
break
;
case
SH_VPERM
:
adjust_vperm
(
insn
)
;
break
;
}
}
</s>

The insn described by INSN_ENTRY [ I ] can be swapped , but only with special handling . Take care of that here .

rs6000
"Swapping constant halves in insn %d\n"
"Adjusting subreg in insn %d\n"


<s> static rtx altivec_expand_vec_init_builtin ( tree type , tree exp , rtx target ) { machine_mode tmode = TYPE_MODE ( type ) ; machine_mode inner_mode = GET_MODE_INNER ( tmode ) ; int i , n_elt = GET_MODE_NUNITS ( tmode ) ; gcc_assert ( VECTOR_MODE_P ( tmode ) ) ; gcc_assert ( n_elt == call_expr_nargs ( exp ) ) ; if ( ! target || ! register_operand ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( n_elt == 1 && GET_MODE_SIZE ( tmode ) == GET_MODE_SIZE ( inner_mode ) ) { rtx x = expand_normal ( CALL_EXPR_ARG ( exp , 0 ) ) ; emit_move_insn ( target , gen_lowpart ( tmode , x ) ) ; } else { rtvec v = rtvec_alloc ( n_elt ) ; for ( i = 0 ; i < n_elt ; ++ i ) { rtx x = expand_normal ( CALL_EXPR_ARG ( exp , i ) ) ; RTVEC_ELT ( v , i ) = gen_lowpart ( inner_mode , x ) ; } rs6000_expand_vector_init ( target , gen_rtx_PARALLEL ( tmode , v ) ) ; } return target ; } </s>


<s> bool X86TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( ! VT . isSimple ( ) ) return false ; if ( VT . getScalarType ( ) == MVT :: i1 ) return false ; if ( VT . getSizeInBits ( ) == 64 ) return false ; return isTypeLegal ( VT . getSimpleVT ( ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s>
X86TTI
::
PopcntSupportKind
X86TTI
::
getPopcntSupport
(
unsigned
TyWidth
)
const
{
assert
(
isPowerOf2_32
(
TyWidth
)
&&
"Ty width must be power of 2"
)
;
return
ST
->
hasSSE41
(
)
PSK_FastHardware
:
PSK_Software
;
}
</s>

Return hardware support for population count .


<s> bool X86InstrInfo :: isHighLatencyDef ( int opc ) const { switch ( opc ) { default : return false ; case X86 :: DIVSDrm : case X86 :: DIVSDrm_Int : case X86 :: DIVSDrr : case X86 :: DIVSDrr_Int : case X86 :: DIVSSrm : case X86 :: DIVSSrm_Int : case X86 :: DIVSSrr : case X86 :: DIVSSrr_Int : case X86 :: SQRTPDm : case X86 :: SQRTPDm_Int : case X86 :: SQRTPDr : case X86 :: SQRTPDr_Int : case X86 :: SQRTPSm : case X86 :: SQRTPSm_Int : case X86 :: SQRTPSr : case X86 :: SQRTPSr_Int : case X86 :: SQRTSDm : case X86 :: SQRTSDm_Int : case X86 :: SQRTSDr : case X86 :: SQRTSDr_Int : case X86 :: SQRTSSm : case X86 :: SQRTSSm_Int : case X86 :: SQRTSSr : case X86 :: SQRTSSr_Int : case X86 :: VDIVSDrm : case X86 :: VDIVSDrm_Int : case X86 :: VDIVSDrr : case X86 :: VDIVSDrr_Int : case X86 :: VDIVSSrm : case X86 :: VDIVSSrm_Int : case X86 :: VDIVSSrr : case X86 :: VDIVSSrr_Int : case X86 :: VSQRTPDm : case X86 :: VSQRTPDm_Int : case X86 :: VSQRTPDr : case X86 :: VSQRTPDr_Int : case X86 :: VSQRTPSm : case X86 :: VSQRTPSm_Int : case X86 :: VSQRTPSr : case X86 :: VSQRTPSr_Int : case X86 :: VSQRTSDm : case X86 :: VSQRTSDm_Int : case X86 :: VSQRTSDr : case X86 :: VSQRTSSm : case X86 :: VSQRTSSm_Int : case X86 :: VSQRTSSr : return true ; } } </s>

Return true if this opcode has high latency to its result .


<s>
MachineBasicBlock
*
Cpu0TargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unexpected instr type to insert"
)
;
case
Cpu0
::
ATOMIC_LOAD_ADD_I8
:
return
emitAtomicBinaryPartword
(
MI
,
BB
,
1
,
Cpu0
::
ADDu
)
;
case
Cpu0
::
ATOMIC_LOAD_ADD_I16
:
return
emitAtomicBinaryPartword
(
MI
,
BB
,
2
,
Cpu0
::
ADDu
)
;
case
Cpu0
::
ATOMIC_LOAD_ADD_I32
:
return
emitAtomicBinary
(
MI
,
BB
,
4
,
Cpu0
::
ADDu
)
;
case
Cpu0
::
ATOMIC_LOAD_AND_I8
:
return
emitAtomicBinaryPartword
(
MI
,
BB
,
1
,
Cpu0
::
AND
)
;
case
Cpu0
::
ATOMIC_LOAD_AND_I16
:
return
emitAtomicBinaryPartword
(
MI
,
BB
,
2
,
Cpu0
::
AND
)
;
case
Cpu0
::
ATOMIC_LOAD_AND_I32
:
return
emitAtomicBinary
(
MI
,
BB
,
4
,
Cpu0
::
AND
)
;
case
Cpu0
::
ATOMIC_LOAD_OR_I8
:
return
emitAtomicBinaryPartword
(
MI
,
BB
,
1
,
Cpu0
::
OR
)
;
case
Cpu0
::
ATOMIC_LOAD_OR_I16
:
return
emitAtomicBinaryPartword
(
MI
,
BB
,
2
,
Cpu0
::
OR
)
;
case
Cpu0
::
ATOMIC_LOAD_OR_I32
:
return
emitAtomicBinary
(
MI
,
BB
,
4
,
Cpu0
::
OR
)
;
case
Cpu0
::
ATOMIC_LOAD_XOR_I8
:
return
emitAtomicBinaryPartword
(
MI
,
BB
,
1
,
Cpu0
::
XOR
)
;
case
Cpu0
::
ATOMIC_LOAD_XOR_I16
:
return
emitAtomicBinaryPartword
(
MI
,
BB
,
2
,
Cpu0
::
XOR
)
;
case
Cpu0
::
ATOMIC_LOAD_XOR_I32
:
return
emitAtomicBinary
(
MI
,
BB
,
4
,
Cpu0
::
XOR
)
;
case
Cpu0
::
ATOMIC_LOAD_NAND_I8
:
return
emitAtomicBinaryPartword
(
MI
,
BB
,
1
,
0
,
true
)
;
case
Cpu0
::
ATOMIC_LOAD_NAND_I16
:
return
emitAtomicBinaryPartword
(
MI
,
BB
,
2
,
0
,
true
)
;
case
Cpu0
::
ATOMIC_LOAD_NAND_I32
:
return
emitAtomicBinary
(
MI
,
BB
,
4
,
0
,
true
)
;
case
Cpu0
::
ATOMIC_LOAD_SUB_I8
:
return
emitAtomicBinaryPartword
(
MI
,
BB
,
1
,
Cpu0
::
SUBu
)
;
case
Cpu0
::
ATOMIC_LOAD_SUB_I16
:
return
emitAtomicBinaryPartword
(
MI
,
BB
,
2
,
Cpu0
::
SUBu
)
;
case
Cpu0
::
ATOMIC_LOAD_SUB_I32
:
return
emitAtomicBinary
(
MI
,
BB
,
4
,
Cpu0
::
SUBu
)
;
case
Cpu0
::
ATOMIC_SWAP_I8
:
return
emitAtomicBinaryPartword
(
MI
,
BB
,
1
,
0
)
;
case
Cpu0
::
ATOMIC_SWAP_I16
:
return
emitAtomicBinaryPartword
(
MI
,
BB
,
2
,
0
)
;
case
Cpu0
::
ATOMIC_SWAP_I32
:
return
emitAtomicBinary
(
MI
,
BB
,
4
,
0
)
;
case
Cpu0
::
ATOMIC_CMP_SWAP_I8
:
return
emitAtomicCmpSwapPartword
(
MI
,
BB
,
1
)
;
case
Cpu0
::
ATOMIC_CMP_SWAP_I16
:
return
emitAtomicCmpSwapPartword
(
MI
,
BB
,
2
)
;
case
Cpu0
::
ATOMIC_CMP_SWAP_I32
:
return
emitAtomicCmpSwap
(
MI
,
BB
,
4
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static bool aarch64_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_SIMD && ( mode == V4SImode || mode == V8HImode || mode == V16QImode || mode == V2DImode || mode == V2SImode || mode == V4HImode || mode == V8QImode || mode == V2SFmode || mode == V4SFmode || mode == V2DFmode || mode == V4HFmode || mode == V8HFmode || mode == V1DFmode ) ) return true ; return false ; } </s>

Implements target hook vector_mode_supported_p .


<s>
bool
R600AsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MF
.
ensureAlignment
(
Align
(
256
)
)
;
SetupMachineFunction
(
MF
)
;
MCContext
&
Context
=
getObjFileLowering
(
)
.
getContext
(
)
;
MCSectionELF
*
ConfigSection
=
Context
.
getELFSection
(
".AMDGPU.config"
,
ELF
::
SHT_PROGBITS
,
0
)
;
OutStreamer
->
SwitchSection
(
ConfigSection
)
;
EmitProgramInfoR600
(
MF
)
;
EmitFunctionBody
(
)
;
if
(
isVerbose
(
)
)
{
MCSectionELF
*
CommentSection
=
Context
.
getELFSection
(
".AMDGPU.csdata"
,
ELF
::
SHT_PROGBITS
,
0
)
;
OutStreamer
->
SwitchSection
(
CommentSection
)
;
R600MachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
R600MachineFunctionInfo
>
(
)
;
OutStreamer
->
emitRawComment
(
Twine
(
"SQ_PGM_RESOURCES:STACK_SIZE = "
+
Twine
(
MFI
->
CFStackSize
)
)
)
;
}
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static void visium_trampoline_init ( rtx m_tramp , tree fndecl , rtx static_chain ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx addr = XEXP ( m_tramp , 0 ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( Pmode , addr , 0 ) ) , plus_constant ( SImode , expand_shift ( RSHIFT_EXPR , SImode , fnaddr , 16 , NULL_RTX , 1 ) , 0x04a90000 ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( Pmode , addr , 4 ) ) , plus_constant ( SImode , expand_and ( SImode , fnaddr , GEN_INT ( 0xffff ) , NULL_RTX ) , 0x04890000 ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( Pmode , addr , 8 ) ) , plus_constant ( SImode , expand_shift ( RSHIFT_EXPR , SImode , static_chain , 16 , NULL_RTX , 1 ) , 0x04b40000 ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( Pmode , addr , 12 ) ) , gen_int_mode ( 0xff892404 , SImode ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( Pmode , addr , 16 ) ) , plus_constant ( SImode , expand_and ( SImode , static_chain , GEN_INT ( 0xffff ) , NULL_RTX ) , 0x04940000 ) ) ; emit_library_call ( set_trampoline_parity_libfunc , LCT_NORMAL , VOIDmode , 1 , addr , SImode ) ; } </s>

Initialize a trampoline . M_TRAMP is an RTX for the memory block for the trampoline , FNDECL is the FUNCTION_DECL for the nested function and STATIC_CHAIN is an RTX for the static chain value that should be passed to the function when it is called .


<s> inline static int number_of_first_bit_set ( unsigned mask ) { return ctz_hwi ( mask ) ; } </s>

Return the number ( counting from 0 ) of the least significant set bit in MASK .


<s> int num_insns_constant ( rtx op , enum machine_mode mode ) { HOST_WIDE_INT low , high ; switch ( GET_CODE ( op ) ) { case CONST_INT : if ( ( INTVAL ( op ) >> 31 ) != 0 && ( INTVAL ( op ) >> 31 ) != - 1 && mask64_operand ( op , mode ) ) return 2 ; else return num_insns_constant_wide ( INTVAL ( op ) ) ; case CONST_DOUBLE : if ( mode == SFmode ) { long l ; REAL_VALUE_TYPE rv ; REAL_VALUE_FROM_CONST_DOUBLE ( rv , op ) ; REAL_VALUE_TO_TARGET_SINGLE ( rv , l ) ; return num_insns_constant_wide ( ( HOST_WIDE_INT ) l ) ; } if ( mode == VOIDmode || mode == DImode ) { high = CONST_DOUBLE_HIGH ( op ) ; low = CONST_DOUBLE_LOW ( op ) ; } else { long l [ 2 ] ; REAL_VALUE_TYPE rv ; REAL_VALUE_FROM_CONST_DOUBLE ( rv , op ) ; REAL_VALUE_TO_TARGET_DOUBLE ( rv , l ) ; high = l [ WORDS_BIG_ENDIAN == 0 ] ; low = l [ WORDS_BIG_ENDIAN != 0 ] ; } if ( TARGET_32BIT ) return ( num_insns_constant_wide ( low ) + num_insns_constant_wide ( high ) ) ; else { if ( ( high == 0 && low >= 0 ) || ( high == - 1 && low < 0 ) ) return num_insns_constant_wide ( low ) ; else if ( mask64_operand ( op , mode ) ) return 2 ; else if ( low == 0 ) return num_insns_constant_wide ( high ) + 1 ; else return ( num_insns_constant_wide ( high ) + num_insns_constant_wide ( low ) + 1 ) ; } default : gcc_unreachable ( ) ; } } </s>

Return the number of instructions it takes to form a constant in as many gprs are needed for MODE .


<s> void riscv_atomic_assign_expand_fenv ( tree * hold , tree * clear , tree * update ) { if ( ! ( TARGET_HARD_FLOAT || TARGET_ZFINX ) ) return ; tree frflags = GET_BUILTIN_DECL ( CODE_FOR_riscv_frflags ) ; tree fsflags = GET_BUILTIN_DECL ( CODE_FOR_riscv_fsflags ) ; tree old_flags = create_tmp_var_raw ( RISCV_ATYPE_USI ) ; * hold = build4 ( TARGET_EXPR , RISCV_ATYPE_USI , old_flags , build_call_expr ( frflags , 0 ) , NULL_TREE , NULL_TREE ) ; * clear = build_call_expr ( fsflags , 1 , old_flags ) ; * update = NULL_TREE ; } </s>


<s> rtx rs6000_libcall_value ( machine_mode mode ) { unsigned int regno ; if ( TARGET_32BIT && TARGET_POWERPC64 && mode == DImode ) return rs6000_parallel_return ( mode , 2 , SImode , GP_ARG_RETURN , 1 ) ; if ( DECIMAL_FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT ) regno = ( mode == TDmode ) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN ; else if ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( mode ) && TARGET_HARD_FLOAT ) regno = FP_ARG_RETURN ; else if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI ) regno = ALTIVEC_ARG_RETURN ; else if ( COMPLEX_MODE_P ( mode ) && targetm . calls . split_complex_arg ) return rs6000_complex_function_value ( mode ) ; else regno = GP_ARG_RETURN ; return gen_rtx_REG ( mode , regno ) ; } </s>

Define how to find the value returned by a library function assuming the value has mode MODE .


<s> OperandMatchResultTy PatmosAsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { if ( ParseRegister ( RegNo , StartLoc , EndLoc ) ) { return OperandMatchResultTy :: MatchOperand_ParseFail ; } if ( RegNo == 0 ) { return OperandMatchResultTy :: MatchOperand_ParseFail ; } return OperandMatchResultTy :: MatchOperand_Success ; } </s>

tryParseRegister - parse one register if possible


<s> void LanaiFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const LanaiRegisterInfo * LRI = static_cast < const LanaiRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; int Offset = - 4 ; MFI . CreateFixedObject ( 4 , Offset , true ) ; Offset -= 4 ; MFI . CreateFixedObject ( 4 , Offset , true ) ; Offset -= 4 ; if ( LRI -> hasBasePointer ( MF ) ) { MFI . CreateFixedObject ( 4 , Offset , true ) ; SavedRegs . reset ( LRI -> getBaseRegister ( ) ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> static void * ix86_init_cost ( struct loop * ) { unsigned * cost = XNEWVEC ( unsigned , 3 ) ; cost [ vect_prologue ] = cost [ vect_body ] = cost [ vect_epilogue ] = 0 ; return cost ; } </s>


<s>
void
WaitcntBrackets
::
print
(
raw_ostream
&
OS
)
{
OS
<<
'\n'
;
for
(
auto
T
:
inst_counter_types
(
)
)
{
uint32_t
LB
=
getScoreLB
(
T
)
;
uint32_t
UB
=
getScoreUB
(
T
)
;
switch
(
T
)
{
case
VM_CNT
:
OS
<<
"    VM_CNT("
<<
UB
LB
<<
"): "
;
break
;
case
LGKM_CNT
:
OS
<<
"    LGKM_CNT("
<<
UB
LB
<<
"): "
;
break
;
case
EXP_CNT
:
OS
<<
"    EXP_CNT("
<<
UB
LB
<<
"): "
;
break
;
default
:
OS
<<
"    UNKNOWN("
<<
UB
LB
<<
"): "
;
break
;
}
if
(
LB
<
UB
)
{
for
(
int
J
=
0
;
J
<=
getMaxVGPR
(
)
;
J
++
)
{
uint32_t
RegScore
=
getRegScore
(
J
,
T
)
;
if
(
RegScore
<=
LB
)
continue
;
uint32_t
RelScore
=
RegScore
LB
1
;
if
(
J
<
SQ_MAX_PGM_VGPRS
+
EXTRA_VGPR_LDS
)
{
OS
<<
RelScore
<<
":v"
<<
J
<<
" "
;
}
else
{
OS
<<
RelScore
<<
":ds "
;
}
}
if
(
T
==
LGKM_CNT
)
{
for
(
int
J
=
0
;
J
<=
getMaxSGPR
(
)
;
J
++
)
{
uint32_t
RegScore
=
getRegScore
(
J
+
NUM_ALL_VGPRS
,
LGKM_CNT
)
;
if
(
RegScore
<=
LB
)
continue
;
uint32_t
RelScore
=
RegScore
LB
1
;
OS
<<
RelScore
<<
":s"
<<
J
<<
" "
;
}
}
}
OS
<<
'\n'
;
}
OS
<<
'\n'
;
}
</s>

print - Print a debug representation of the operand to the given stream .


<s>
MCOperand
SystemZMCInstLower
::
lowerOperand
(
const
MachineOperand
&
MO
)
const
{
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
return
MCOperand
::
CreateReg
(
MO
.
getReg
(
)
)
;
case
MachineOperand
::
MO_Immediate
:
return
MCOperand
::
CreateImm
(
MO
.
getImm
(
)
)
;
case
MachineOperand
::
MO_MachineBasicBlock
:
return
lowerSymbolOperand
(
MO
,
MO
.
getMBB
(
)
->
getSymbol
(
)
,
0
)
;
case
MachineOperand
::
MO_GlobalAddress
:
return
lowerSymbolOperand
(
MO
,
Mang
->
getSymbol
(
MO
.
getGlobal
(
)
)
,
MO
.
getOffset
(
)
)
;
case
MachineOperand
::
MO_ExternalSymbol
:
{
StringRef
Name
=
MO
.
getSymbolName
(
)
;
return
lowerSymbolOperand
(
MO
,
AsmPrinter
.
GetExternalSymbolSymbol
(
Name
)
,
MO
.
getOffset
(
)
)
;
}
case
MachineOperand
::
MO_JumpTableIndex
:
return
lowerSymbolOperand
(
MO
,
AsmPrinter
.
GetJTISymbol
(
MO
.
getIndex
(
)
)
,
0
)
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
return
lowerSymbolOperand
(
MO
,
AsmPrinter
.
GetCPISymbol
(
MO
.
getIndex
(
)
)
,
MO
.
getOffset
(
)
)
;
case
MachineOperand
::
MO_BlockAddress
:
{
const
BlockAddress
*
BA
=
MO
.
getBlockAddress
(
)
;
return
lowerSymbolOperand
(
MO
,
AsmPrinter
.
GetBlockAddressSymbol
(
BA
)
,
MO
.
getOffset
(
)
)
;
}
}
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> const JVMSubtarget & getSubtarget ( ) const { return * Subtarget ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


<s> static bool rs6000_output_addr_const_extra ( FILE * file , rtx x ) { if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , 1 ) ) { case UNSPEC_TOCREL : gcc_checking_assert ( GET_CODE ( XVECEXP ( x , 0 , 0 ) ) == SYMBOL_REF && REG_P ( XVECEXP ( x , 0 , 1 ) ) && REGNO ( XVECEXP ( x , 0 , 1 ) ) == TOC_REGISTER ) ; output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; if ( x == tocrel_base && tocrel_offset != const0_rtx ) { if ( INTVAL ( tocrel_offset ) >= 0 ) fprintf ( file , "+" ) ; output_addr_const ( file , CONST_CAST_RTX ( tocrel_offset ) ) ; } if ( ! TARGET_AIX || ( TARGET_ELF && TARGET_MINIMAL_TOC ) ) { putc ( '-' , file ) ; assemble_name ( file , toc_label_name ) ; need_toc_init = 1 ; } else if ( TARGET_ELF ) fputs ( "@toc" , file ) ; return true ; case UNSPEC_MACHOPIC_OFFSET : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; putc ( '-' , file ) ; machopic_output_function_base_name ( file ) ; return true ; } return false ; } </s>


"OffsetRegShifted must imply OffsetIsReg!"

"Offset must exists unless register offset is used!"

"Cannot have shift amount without shifted register offset!"

"Cannot have expression offset and register offset!"


<s> bool MipsTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( ! AM . HasBaseReg ) break ; return false ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> bool targetHandlesStackFrameRounding ( ) const { return true ; } </s>

targetHandlesStackFrameRounding - Returns true if the target is responsible for rounding up the stack frame ( probably at emitPrologue time ) .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachinePostDominatorTree > ( ) ; AU . addPreserved < MachinePostDominatorTree > ( ) ; AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static void ix86_emit_probe_stack_range ( HOST_WIDE_INT first , HOST_WIDE_INT size ) { if ( size <= 6 * PROBE_INTERVAL ) { HOST_WIDE_INT i ; for ( i = PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + i ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + size ) ) ) ; } else { HOST_WIDE_INT rounded_size , last ; struct scratch_reg sr ; get_scratch_register_on_entry ( & sr ) ; rounded_size = ROUND_DOWN ( size , PROBE_INTERVAL ) ; emit_move_insn ( sr . reg , GEN_INT ( - first ) ) ; last = first + rounded_size ; emit_insn ( ix86_gen_probe_stack_range ( sr . reg , sr . reg , GEN_INT ( - last ) ) ) ; if ( size != rounded_size ) emit_stack_probe ( plus_constant ( Pmode , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , sr . reg ) , rounded_size - size ) ) ; release_scratch_register_on_entry ( & sr ) ; } emit_insn ( gen_blockage ( ) ) ; } </s>

Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE , inclusive . These are offsets from the current stack pointer .


<s>
unsigned
X86TargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"esp"
,
X86
::
ESP
)
.
Case
(
"rsp"
,
X86
::
RSP
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s>
static
void
rl78_note_reg_uses
(
char
*
dead
,
rtx
s
,
rtx
insn
)
{
const
char
*
fmt
;
int
i
,
r
;
enum
rtx_code
code
;
if
(
!
s
)
return
;
code
=
GET_CODE
(
s
)
;
switch
(
code
)
{
case
REG
:
r
=
REGNO
(
s
)
;
if
(
dump_file
)
{
fprintf
(
dump_file
,
"note use reg %d size %d on insn %d\n"
,
r
,
GET_MODE_SIZE
(
GET_MODE
(
s
)
)
,
INSN_UID
(
insn
)
)
;
print_rtl_single
(
dump_file
,
s
)
;
}
if
(
dead
[
r
]
)
add_reg_note
(
insn
,
REG_DEAD
,
gen_rtx_REG
(
GET_MODE
(
s
)
,
r
)
)
;
for
(
i
=
0
;
i
<
GET_MODE_SIZE
(
GET_MODE
(
s
)
)
;
i
++
)
dead
[
r
+
i
]
=
0
;
return
;
case
SCRATCH
:
case
PC
:
return
;
case
CONST_INT
:
case
CONST_VECTOR
:
case
CONST_DOUBLE
:
case
CONST_FIXED
:
return
;
default
:
break
;
}
fmt
=
GET_RTX_FORMAT
(
code
)
;
for
(
i
=
GET_RTX_LENGTH
(
code
)
1
;
i
>=
0
;
i
)
{
if
(
fmt
[
i
]
==
'E'
)
{
int
j
;
for
(
j
=
XVECLEN
(
s
,
i
)
1
;
j
>=
0
;
j
)
rl78_note_reg_uses
(
dead
,
XVECEXP
(
s
,
i
,
j
)
,
insn
)
;
}
else
if
(
fmt
[
i
]
==
'e'
)
rl78_note_reg_uses
(
dead
,
XEXP
(
s
,
i
)
,
insn
)
;
}
}
</s>

Add REG_DEAD notes using DEAD [ reg ] for rtx S which is part of INSN . This function scans for uses of registers ; the last use ( i.e . first encounter when scanning backwards ) triggers a REG_DEAD note if the reg was previously in DEAD [ ] .


"Trying RV32Zdinx table (Double in Integer and"

"Trying RVZfinx table (Float in Integer):\n"

"Trying RISCV32Only_16 table (16-bit Instruction):\n"

"Trying RISCV_C table (16-bit Instruction):\n"

Returns the disassembly of a single instruction .


<s>
const
MCFixupKindInfo
&
LanaiAsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
static
const
MCFixupKindInfo
Infos
[
Lanai
::
NumTargetFixupKinds
]
=
{
{
"FIXUP_LANAI_NONE"
,
0
,
32
,
0
}
,
{
"FIXUP_LANAI_21"
,
16
,
16
,
0
}
,
{
"FIXUP_LANAI_21_F"
,
16
,
16
,
0
}
,
{
"FIXUP_LANAI_25"
,
7
,
25
,
0
}
,
{
"FIXUP_LANAI_32"
,
0
,
32
,
0
}
,
{
"FIXUP_LANAI_HI16"
,
16
,
16
,
0
}
,
{
"FIXUP_LANAI_LO16"
,
16
,
16
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> static int rs6000_loop_align_max_skip ( rtx_insn * label ) { return ( 1 << rs6000_loop_align ( label ) ) - 1 ; } </s>


"non-standard ABI extension with no compatibility guarantee"

Return a nonzero value to say to return the function value in memory , just as large structures are always returned . TYPE will be the data type of the value , and FNTYPE will be the type of the function doing the returning , or @ code { NULL } for libcalls . The AIX ABI for the RS/6000 specifies that all structures are returned in memory . The Darwin ABI does the same . The SVR4 ABI specifies that structures < = 8 bytes are returned in r3/r4 , but a draft put them in memory , and GCC used to implement the draft instead of the final standard . Therefore , aix_struct_return controls this instead of DEFAULT_ABI ; V.4 targets needing backward compatibility can change DRAFT_V4_STRUCT_RET to override the default , and -m switches get the final word . See rs6000_override_options for more details . The PPC32 SVR4 ABI uses IEEE double extended for long double , if 128-bit long double support is enabled . These values are returned in memory . int_size_in_bytes returns -1 for variable size objects , which go in memory always . The cast to unsigned makes -1 > 8 .


<s>
void
Thumb1InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
ARMSubtarget
&
st
=
MF
.
getTarget
(
)
.
getSubtarget
<
ARMSubtarget
>
(
)
;
assert
(
ARM
::
GPRRegClass
.
contains
(
DestReg
,
SrcReg
)
&&
"Thumb1 can only copy GPR registers"
)
;
if
(
st
.
hasV6Ops
(
)
||
ARM
::
hGPRRegClass
.
contains
(
SrcReg
)
||
!
ARM
::
tGPRRegClass
.
contains
(
DestReg
)
)
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tMOVr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
)
;
else
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tPUSH
)
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tPOP
)
)
)
.
addReg
(
DestReg
,
getDefRegState
(
true
)
)
;
}
}
</s>

ARM
ARM
ARM
ARM::GPRRegClass
"Thumb1 can only copy GPR registers"
ARM::hGPRRegClass
ARM::tGPRRegClass
ARM::tMOVr
ARM::tPUSH
ARM::tPOP


<s> bool fixupNeedsRelaxationAdvanced ( const MCFixup & Fixup , bool Resolved , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { MCInst const & MCB = DF -> getInst ( ) ; assert ( HexagonMCInstrInfo :: isBundle ( MCB ) ) ; * RelaxTarget = nullptr ; MCInst & MCI = const_cast < MCInst & > ( HexagonMCInstrInfo :: instruction ( MCB , Fixup . getOffset ( ) / HEXAGON_INSTR_SIZE ) ) ; if ( ! Resolved ) { switch ( ( unsigned ) Fixup . getKind ( ) ) { case fixup_Hexagon_B22_PCREL : default : return false ; break ; case fixup_Hexagon_B13_PCREL : case fixup_Hexagon_B15_PCREL : case fixup_Hexagon_B9_PCREL : case fixup_Hexagon_B7_PCREL : { if ( HexagonMCInstrInfo :: bundleSize ( MCB ) < HEXAGON_PACKET_SIZE ) { ++ relaxedCnt ; * RelaxTarget = & MCI ; setExtender ( Layout . getAssembler ( ) . getContext ( ) ) ; return true ; } else { return false ; } break ; } } } bool Relaxable = isInstRelaxable ( MCI ) ; if ( Relaxable == false ) return false ; MCFixupKind Kind = Fixup . getKind ( ) ; int64_t sValue = Value ; int64_t maxValue ; switch ( ( unsigned ) Kind ) { case fixup_Hexagon_B7_PCREL : maxValue = 1 << 8 ; break ; case fixup_Hexagon_B9_PCREL : maxValue = 1 << 10 ; break ; case fixup_Hexagon_B15_PCREL : maxValue = 1 << 16 ; break ; case fixup_Hexagon_B22_PCREL : maxValue = 1 << 23 ; break ; default : maxValue = INT64_MAX ; break ; } bool isFarAway = - maxValue > sValue || sValue > maxValue - 1 ; if ( isFarAway ) { if ( HexagonMCInstrInfo :: bundleSize ( MCB ) < HEXAGON_PACKET_SIZE ) { ++ relaxedCnt ; * RelaxTarget = & MCI ; setExtender ( Layout . getAssembler ( ) . getContext ( ) ) ; return true ; } } return false ; } </s>

Target specific predicate for whether a given fixup requires the associated instruction to be relaxed .


<s> bool MOSInstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { assert ( Cond . size ( ) == 2 ) ; auto & Val = Cond [ 1 ] ; Val . setImm ( ! Val . getImm ( ) ) ; return false ; } </s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> bool n7_consumed_by_ii_dep_p ( rtx_insn * consumer , rtx def_reg ) { rtx use_rtx ; switch ( get_attr_type ( consumer ) ) { case TYPE_ALU : if ( movd44_even_dep_p ( consumer , def_reg ) ) return true ; use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_MUL : use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_MAC : use_rtx = extract_mac_non_acc_rtx ( consumer ) ; break ; case TYPE_DIV : if ( divmod_p ( consumer ) ) use_rtx = SET_SRC ( parallel_element ( consumer , 0 ) ) ; else use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_LOAD : if ( post_update_insn_p ( consumer ) ) use_rtx = extract_base_reg ( consumer ) ; else use_rtx = extract_mem_rtx ( consumer ) ; break ; case TYPE_STORE : if ( post_update_insn_p ( consumer ) ) use_rtx = extract_base_reg ( consumer ) ; else use_rtx = extract_mem_rtx ( consumer ) ; if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; if ( ! post_update_insn_p ( consumer ) && ! immed_offset_p ( extract_mem_rtx ( consumer ) ) ) return false ; use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_LOAD_MULTIPLE : use_rtx = extract_base_reg ( consumer ) ; break ; case TYPE_STORE_MULTIPLE : use_rtx = extract_base_reg ( consumer ) ; if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; use_rtx = extract_nth_access_rtx ( consumer , 0 ) ; break ; case TYPE_BRANCH : use_rtx = PATTERN ( consumer ) ; break ; default : gcc_unreachable ( ) ; } if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; return false ; } </s>

Check the dependency between the producer defining DEF_REG and CONSUMER requiring input operand at II .


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , Options . StackAlignmentOverride ) , FrameLowering ( * this , Subtarget ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) , DL ( computeDataLayout ( * getSubtargetImpl ( ) ) ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , JITInfo ( * this ) { if ( getRelocationModel ( ) == Reloc :: Static ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . is64Bit ( ) ) { Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; } else if ( Subtarget . isTargetCOFF ( ) ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . isTargetDarwin ( ) ) { if ( getRelocationModel ( ) == Reloc :: PIC_ ) Subtarget . setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; Subtarget . setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( Subtarget . isTargetELF ( ) ) { Subtarget . setPICStyle ( PICStyles :: GOT ) ; } if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = FloatABI :: Hard ; if ( Subtarget . isTargetWin64 ( ) ) this -> Options . TrapUnreachable = true ; initAsmInfo ( ) ; } </s>


<s> static bool nvptx_warp_propagate ( bool is_call , basic_block block , rtx_insn * insn ) { return nvptx_propagate ( is_call , block , insn , PM_read_write , warp_prop_gen , 0 , false ) ; } </s>

Propagate state that is live at start of BLOCK across the vectors of a single warp . Propagation is inserted just after INSN . IS_CALL and return as for nvptx_propagate .


<s> void MSP430InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool Mips16TargetLowering :: isEligibleForTailCallOptimization ( const CCState & CCInfo , unsigned NextStackOffset , const MipsFunctionInfo & FI ) const { return false ; } </s>

Returns true if the call can be lowered as a tail call .


<s> int condexec_memory_operand ( rtx op , machine_mode mode ) { machine_mode op_mode = GET_MODE ( op ) ; rtx addr ; if ( mode != VOIDmode && op_mode != mode ) return FALSE ; switch ( op_mode ) { default : return FALSE ; case QImode : case HImode : case SImode : case SFmode : break ; } if ( GET_CODE ( op ) != MEM ) return FALSE ; addr = XEXP ( op , 0 ) ; return frv_legitimate_address_p_1 ( mode , addr , reload_completed , TRUE , FALSE ) ; } </s>

Return true if the memory operand is one that can be conditionally executed .


<s>
void
Finish
(
)
{
const
size_t
VendorHeaderSize
=
4
+
CurrentVendor
.
size
(
)
+
1
;
const
size_t
TagHeaderSize
=
1
+
4
;
Streamer
.
EmitIntValue
(
VendorHeaderSize
+
TagHeaderSize
+
ContentsSize
,
4
)
;
Streamer
.
EmitBytes
(
CurrentVendor
,
0
)
;
Streamer
.
EmitIntValue
(
0
,
1
)
;
Streamer
.
EmitIntValue
(
ARMBuildAttrs
::
File
,
1
)
;
Streamer
.
EmitIntValue
(
TagHeaderSize
+
ContentsSize
,
4
)
;
for
(
unsigned
int
i
=
0
;
i
<
Contents
.
size
(
)
;
++
i
)
{
AttributeItemType
item
=
Contents
[
i
]
;
Streamer
.
EmitULEB128IntValue
(
item
.
Tag
,
0
)
;
switch
(
item
.
Type
)
{
case
AttributeItemType
::
NumericAttribute
:
Streamer
.
EmitULEB128IntValue
(
item
.
IntValue
,
0
)
;
break
;
case
AttributeItemType
::
TextAttribute
:
Streamer
.
EmitBytes
(
UppercaseString
(
item
.
StringValue
)
,
0
)
;
Streamer
.
EmitIntValue
(
0
,
1
)
;
break
;
default
:
assert
(
0
&&
"Invalid attribute type"
)
;
}
}
Contents
.
clear
(
)
;
}
</s>

Finish - Do final processing and write the object to the output stream .


<s> TargetTransformInfo ARMBaseTargetMachine :: getTargetTransformInfo ( const Function & F ) { return TargetTransformInfo ( ARMTTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> static unsigned addLiveIn ( MachineFunction & MF , unsigned PReg , const TargetRegisterClass * RC ) { unsigned VReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MF . getRegInfo ( ) . addLiveIn ( PReg , VReg ) ; return VReg ; } </s>

addLiveIn - Add the specified register as a live-in .


<s> const MCPhysReg * SystemZXPLINK64Registers :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_SystemZ_XPLINK64_SaveList ; } </s>


<s> void R600TargetLowering :: getStackAddress ( unsigned StackWidth , unsigned ElemIdx , unsigned & Channel , unsigned & PtrIncr ) const { switch ( StackWidth ) { default : case 1 : Channel = 0 ; if ( ElemIdx > 0 ) { PtrIncr = 1 ; } else { PtrIncr = 0 ; } break ; case 2 : Channel = ElemIdx % 2 ; if ( ElemIdx == 2 ) { PtrIncr = 1 ; } else { PtrIncr = 0 ; } break ; case 4 : Channel = ElemIdx ; PtrIncr = 0 ; break ; } } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> static void allocateSpecialInputVGPRs ( CCState & CCInfo , MachineFunction & MF , const SIRegisterInfo & TRI , SIMachineFunctionInfo & Info ) { if ( Info . hasWorkItemIDX ( ) ) { unsigned Reg = TRI . getPreloadedValue ( MF , SIRegisterInfo :: WORKITEM_ID_X ) ; MF . addLiveIn ( Reg , & AMDGPU :: VGPR_32RegClass ) ; CCInfo . AllocateReg ( Reg ) ; } if ( Info . hasWorkItemIDY ( ) ) { unsigned Reg = TRI . getPreloadedValue ( MF , SIRegisterInfo :: WORKITEM_ID_Y ) ; MF . addLiveIn ( Reg , & AMDGPU :: VGPR_32RegClass ) ; CCInfo . AllocateReg ( Reg ) ; } if ( Info . hasWorkItemIDZ ( ) ) { unsigned Reg = TRI . getPreloadedValue ( MF , SIRegisterInfo :: WORKITEM_ID_Z ) ; MF . addLiveIn ( Reg , & AMDGPU :: VGPR_32RegClass ) ; CCInfo . AllocateReg ( Reg ) ; } } </s>

Allocate implicit function VGPR arguments at the end of allocated user arguments .

AMDGPU SI SI SI AMDGPU::VGPR_32RegClass SI AMDGPU::VGPR_32RegClass SI AMDGPU::VGPR_32RegClass


"MEMOPw offset is not aligned correctly."

"MEMOPh offset is not aligned correctly."

"No offset range is defined for this opcode. "

"Please define it in the above switch statement!"


<s> bool AMDGPULowerIntrinsics :: makeLIDRangeMetadata ( Function & F ) const { auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; const TargetMachine & TM = TPC -> getTM < TargetMachine > ( ) ; const AMDGPUSubtarget & ST = TM . getSubtarget < AMDGPUSubtarget > ( F ) ; bool Changed = false ; for ( auto * U : F . users ( ) ) { auto * CI = dyn_cast < CallInst > ( U ) ; if ( ! CI ) continue ; Changed |= ST . makeLIDRangeMetadata ( CI ) ; } return Changed ; } </s>

Creates value range metadata on an workitemid . * intrinsic call or load .


<s> BitVector BlackfinRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; using namespace BF ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AZ ) ; Reserved . set ( AN ) ; Reserved . set ( AQ ) ; Reserved . set ( AC0 ) ; Reserved . set ( AC1 ) ; Reserved . set ( AV0 ) ; Reserved . set ( AV0S ) ; Reserved . set ( AV1 ) ; Reserved . set ( AV1S ) ; Reserved . set ( V ) ; Reserved . set ( VS ) ; Reserved . set ( CYCLES ) . set ( CYCLES2 ) ; Reserved . set ( L0 ) ; Reserved . set ( L1 ) ; Reserved . set ( L2 ) ; Reserved . set ( L3 ) ; Reserved . set ( SP ) ; Reserved . set ( RETS ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( FP ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
void
SystemZInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
DestReg
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
DebugLoc
::
getUnknownLoc
(
)
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
unsigned
Opc
=
0
;
if
(
RC
==
&
SystemZ
::
GR32RegClass
||
RC
==
&
SystemZ
::
ADDR32RegClass
)
Opc
=
SystemZ
::
MOV32rm
;
else
if
(
RC
==
&
SystemZ
::
GR64RegClass
||
RC
==
&
SystemZ
::
ADDR64RegClass
)
{
Opc
=
SystemZ
::
MOV64rm
;
}
else
if
(
RC
==
&
SystemZ
::
FP32RegClass
)
{
Opc
=
SystemZ
::
FMOV32rm
;
}
else
if
(
RC
==
&
SystemZ
::
FP64RegClass
)
{
Opc
=
SystemZ
::
FMOV64rm
;
}
else
if
(
RC
==
&
SystemZ
::
GR64PRegClass
)
{
Opc
=
SystemZ
::
MOV64Prm
;
}
else
if
(
RC
==
&
SystemZ
::
GR128RegClass
)
{
Opc
=
SystemZ
::
MOV128rm
;
}
else
llvm_unreachable
(
"Unsupported regclass to load"
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
,
DestReg
)
,
FrameIdx
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> void SIInstrInfo :: legalizeOperandsVOP3 ( MachineRegisterInfo & MRI , MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; int VOP3Idx [ 3 ] = { AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src0 ) , AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src1 ) , AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src2 ) } ; int ConstantBusLimit = ST . getConstantBusLimit ( Opc ) ; int LiteralLimit = ST . hasVOP3Literal ( ) ? 1 : 0 ; SmallDenseSet < unsigned > SGPRsUsed ; unsigned SGPRReg = findUsedSGPR ( MI , VOP3Idx ) ; if ( SGPRReg != AMDGPU :: NoRegister ) { SGPRsUsed . insert ( SGPRReg ) ; -- ConstantBusLimit ; } for ( unsigned i = 0 ; i < 3 ; ++ i ) { int Idx = VOP3Idx [ i ] ; if ( Idx == - 1 ) break ; MachineOperand & MO = MI . getOperand ( Idx ) ; if ( ! MO . isReg ( ) ) { if ( ! isLiteralConstantLike ( MO , get ( Opc ) . OpInfo [ Idx ] ) ) continue ; if ( LiteralLimit > 0 && ConstantBusLimit > 0 ) { -- LiteralLimit ; -- ConstantBusLimit ; continue ; } -- LiteralLimit ; -- ConstantBusLimit ; legalizeOpWithMove ( MI , Idx ) ; continue ; } if ( ! RI . isSGPRClass ( MRI . getRegClass ( MO . getReg ( ) ) ) ) continue ; if ( SGPRsUsed . count ( MO . getReg ( ) ) ) continue ; if ( ConstantBusLimit > 0 ) { SGPRsUsed . insert ( MO . getReg ( ) ) ; -- ConstantBusLimit ; continue ; } legalizeOpWithMove ( MI , Idx ) ; } } </s>

Fix operands in MI to satisfy constant bus requirements .


"Constant Island pass failed to converge!"

"Branch Fix Up pass failed to converge!"

runOnMachineFunction - Emit the function body .


<s>
unsigned
getPointerSize
(
)
{
if
(
is16BitMode
(
)
)
return
16
;
if
(
is32BitMode
(
)
)
return
32
;
if
(
is64BitMode
(
)
)
return
64
;
llvm_unreachable
(
"invalid mode"
)
;
}
</s>

Layout pointer size in bytes , rounded up to a whole number of bytes .


<s> unsigned GCNHazardRecognizer :: PreEmitNoops ( MachineInstr * MI ) { int WaitStates = std :: max ( 0 , checkAnyInstHazards ( MI ) ) ; if ( SIInstrInfo :: isSMRD ( * MI ) ) return std :: max ( WaitStates , checkSMRDHazards ( MI ) ) ; if ( SIInstrInfo :: isVALU ( * MI ) ) { WaitStates = std :: max ( WaitStates , checkVALUHazards ( MI ) ) ; if ( SIInstrInfo :: isVMEM ( * MI ) ) WaitStates = std :: max ( WaitStates , checkVMEMHazards ( MI ) ) ; if ( SIInstrInfo :: isDPP ( * MI ) ) WaitStates = std :: max ( WaitStates , checkDPPHazards ( MI ) ) ; if ( isDivFMas ( MI -> getOpcode ( ) ) ) WaitStates = std :: max ( WaitStates , checkDivFMasHazards ( MI ) ) ; if ( isRWLane ( MI -> getOpcode ( ) ) ) WaitStates = std :: max ( WaitStates , checkRWLaneHazards ( MI ) ) ; if ( isVInterp ( MI -> getOpcode ( ) ) ) WaitStates = std :: max ( WaitStates , checkReadM0Hazards ( MI ) ) ; return WaitStates ; } if ( isSGetReg ( MI -> getOpcode ( ) ) ) return std :: max ( WaitStates , checkGetRegHazards ( MI ) ) ; if ( isSSetReg ( MI -> getOpcode ( ) ) ) return std :: max ( WaitStates , checkSetRegHazards ( MI ) ) ; if ( isRFE ( MI -> getOpcode ( ) ) ) return std :: max ( WaitStates , checkRFEHazards ( MI ) ) ; if ( isSMovRel ( MI -> getOpcode ( ) ) ) return std :: max ( WaitStates , checkReadM0Hazards ( MI ) ) ; return WaitStates ; } </s>

PreEmitNoops - This callback is invoked prior to emitting an instruction .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> bool X86TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( VT . getSizeInBits ( ) == 64 ) return isPALIGNRMask ( M , VT , Subtarget -> hasSSSE3 ( ) ) ; return ( VT . getVectorNumElements ( ) == 2 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isMOVLMask ( M , VT ) || isSHUFPMask ( M , VT ) || isPSHUFDMask ( M , VT ) || isPSHUFHWMask ( M , VT ) || isPSHUFLWMask ( M , VT ) || isPALIGNRMask ( M , VT , Subtarget -> hasSSSE3 ( ) ) || isUNPCKLMask ( M , VT ) || isUNPCKHMask ( M , VT ) || isUNPCKL_v_undef_Mask ( M , VT ) || isUNPCKH_v_undef_Mask ( M , VT ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s>
int
m32c_split_psi_p
(
rtx
*
operands
)
{
fprintf
(
stderr
,
"\nm32c_split_psi_p\n"
)
;
debug_rtx
(
operands
[
0
]
)
;
debug_rtx
(
operands
[
1
]
)
;
if
(
TARGET_A16
)
{
fprintf
(
stderr
,
"yes, A16\n"
)
;
return
1
;
}
if
(
GET_CODE
(
operands
[
1
]
)
==
MEM
&&
GET_CODE
(
XEXP
(
operands
[
1
]
,
0
)
)
==
POST_INC
)
{
fprintf
(
stderr
,
"yes, pop.l\n"
)
;
return
1
;
}
fprintf
(
stderr
,
"no, default\n"
)
;
return
0
;
}
</s>

Returns TRUE if the given PSImode move should be split . We split for all r8c/m16c moves , since it does n't support them , and for POP.L as we can only * push * SImode .


<s>
SDValue
XCoreTargetLowering
::
LowerCall
(
TargetLowering
::
CallLoweringInfo
&
CLI
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SelectionDAG
&
DAG
=
CLI
.
DAG
;
SDLoc
&
dl
=
CLI
.
DL
;
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
=
CLI
.
Outs
;
SmallVectorImpl
<
SDValue
>
&
OutVals
=
CLI
.
OutVals
;
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
=
CLI
.
Ins
;
SDValue
Chain
=
CLI
.
Chain
;
SDValue
Callee
=
CLI
.
Callee
;
bool
&
isTailCall
=
CLI
.
IsTailCall
;
CallingConv
::
ID
CallConv
=
CLI
.
CallConv
;
bool
isVarArg
=
CLI
.
IsVarArg
;
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
OutVals
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .

XCore
XCore
ISD::OutputArg
ISD::InputArg
"Unsupported calling convention"


"Alpha DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> unsigned getMaxMemcpyTPInlineSizeThreshold ( ) const { return 128 ; } </s>

getMaxMemcpyTPInlineSizeThreshold - Returns the maximum size that still makes it profitable to inline a llvm.memcpy as a Tail Predicated loop .


<s>
unsigned
M68kInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
I
->
getOpcode
(
)
!=
M68k
::
BRA8
&&
getCondFromBranchOpc
(
I
->
getOpcode
(
)
)
==
M68k
::
COND_INVALID
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s> bool X86FastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Load : return X86SelectLoad ( I ) ; case Instruction :: Store : return X86SelectStore ( I ) ; case Instruction :: Ret : return X86SelectRet ( I ) ; case Instruction :: ICmp : case Instruction :: FCmp : return X86SelectCmp ( I ) ; case Instruction :: ZExt : return X86SelectZExt ( I ) ; case Instruction :: Br : return X86SelectBranch ( I ) ; case Instruction :: LShr : case Instruction :: AShr : case Instruction :: Shl : return X86SelectShift ( I ) ; case Instruction :: SDiv : case Instruction :: UDiv : case Instruction :: SRem : case Instruction :: URem : return X86SelectDivRem ( I ) ; case Instruction :: Select : return X86SelectSelect ( I ) ; case Instruction :: Trunc : return X86SelectTrunc ( I ) ; case Instruction :: FPExt : return X86SelectFPExt ( I ) ; case Instruction :: FPTrunc : return X86SelectFPTrunc ( I ) ; case Instruction :: IntToPtr : case Instruction :: PtrToInt : { EVT SrcVT = TLI . getValueType ( I -> getOperand ( 0 ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( I -> getType ( ) ) ; if ( DstVT . bitsGT ( SrcVT ) ) return X86SelectZExt ( I ) ; if ( DstVT . bitsLT ( SrcVT ) ) return X86SelectTrunc ( I ) ; unsigned Reg = getRegForValue ( I -> getOperand ( 0 ) ) ; if ( Reg == 0 ) return false ; updateValueMap ( I , Reg ) ; return true ; } } return false ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> bool PatmosAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == ".word" ) return ParseDirectiveWord ( 4 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".half" || IDVal == ".hword" ) return ParseDirectiveWord ( 2 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".fstart" ) return ParseDirectiveFStart ( DirectiveID . getLoc ( ) ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s>
MCSymbol
*
DCPU16MCInstLower
::
GetExternalSymbolSymbol
(
const
MachineOperand
&
MO
)
const
{
switch
(
MO
.
getTargetFlags
(
)
)
{
default
:
llvm_unreachable
(
"Unknown target flag on GV operand"
)
;
case
0
:
break
;
}
return
Printer
.
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
;
}
</s>

Return the MCSymbol for the specified ExternalSymbol .


<s> static void output_btfext_core_sections ( void ) { size_t i ; bpf_core_section_ref sec ; dw2_asm_output_data ( 4 , sizeof ( struct btf_ext_reloc ) , "btfext_core_info_rec_size" ) ; FOR_EACH_VEC_ELT ( * bpf_core_sections , i , sec ) { sec -> name_offset += ctfc_get_strtab_len ( ctf_get_tu_ctfc ( ) , CTF_STRTAB ) ; dw2_asm_output_data ( 4 , sec -> name_offset , "btfext_secinfo_sec_name_off" ) ; dw2_asm_output_data ( 4 , vec_safe_length ( sec -> relocs ) , "btfext_secinfo_num_recs" ) ; output_btfext_core_relocs ( sec ) ; } } </s>


<s> static bool mips_lra_p ( void ) { return mips_lra_flag ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"TVM move materializable"
;
}
</s>


<s> static void arm_emit_vfp_multi_reg_pop ( int first_reg , int num_regs , rtx base_reg ) { int i , j ; rtx par ; rtx dwarf = NULL_RTX ; rtx tmp , reg ; gcc_assert ( num_regs && num_regs <= 32 ) ; if ( num_regs == 2 && ! arm_arch6 ) { if ( first_reg == 15 ) first_reg -- ; num_regs ++ ; } if ( num_regs > 16 ) { arm_emit_vfp_multi_reg_pop ( first_reg , 16 , base_reg ) ; arm_emit_vfp_multi_reg_pop ( first_reg + 16 , num_regs - 16 , base_reg ) ; return ; } par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs + 1 ) ) ; tmp = gen_rtx_SET ( base_reg , plus_constant ( Pmode , base_reg , 8 * num_regs ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , 0 ) = tmp ; for ( j = 0 , i = first_reg ; j < num_regs ; i += 2 ) { reg = gen_rtx_REG ( DFmode , i ) ; tmp = gen_rtx_SET ( reg , gen_frame_mem ( DFmode , plus_constant ( Pmode , base_reg , 8 * j ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , j + 1 ) = tmp ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; j ++ ; } par = emit_insn ( par ) ; REG_NOTES ( par ) = dwarf ; if ( REGNO ( base_reg ) == IP_REGNUM ) { RTX_FRAME_RELATED_P ( par ) = 1 ; add_reg_note ( par , REG_CFA_DEF_CFA , hard_frame_pointer_rtx ) ; } else arm_add_cfa_adjust_cfa_note ( par , 2 * UNITS_PER_WORD * num_regs , base_reg , base_reg ) ; } </s>

Generate and emit an insn pattern that we will recognize as a pop_multi of NUM_REGS consecutive VFP regs , starting at FIRST_REG . Unfortunately , since this insn does not reflect very well the actual semantics of the operation , we need to annotate the insn for the benefit of DWARF2 frame unwind information .


<s> bool ARMTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( Subtarget -> isThumb ( ) ) return false ; MVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == ISD :: SEXTLOAD ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; } else return false ; bool isInc ; bool isLegal = getIndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( isLegal ) { AM = isInc ? ISD :: POST_INC : ISD :: POST_DEC ; return true ; } return false ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .

ARM ARM ISD::MemIndexedMode ISD::SEXTLOAD ISD::POST_INC ISD::POST_DEC


<s> void arm_register_target_pragmas ( void ) { targetm . target_option . pragma_parse = arm_pragma_target_parse ; targetm . resolve_overloaded_builtin = arm_resolve_overloaded_builtin ; c_register_pragma ( "GCC" , "arm" , arm_pragma_arm ) ; REGISTER_SUBTARGET_PRAGMAS ( ) ; } </s>

Register target pragmas . We need to add the hook for parsing # pragma GCC option here rather than in arm.cc since it will pull in various preprocessor functions , and those are not present in languages like fortran without a preprocessor .


<s>
void
CSKYAsmPrinter
::
emitMachineConstantPoolValue
(
MachineConstantPoolValue
*
MCPV
)
{
int
Size
=
getDataLayout
(
)
.
getTypeAllocSize
(
MCPV
->
getType
(
)
)
;
CSKYConstantPoolValue
*
CCPV
=
static_cast
<
CSKYConstantPoolValue
*
>
(
MCPV
)
;
MCSymbol
*
MCSym
;
if
(
CCPV
->
isBlockAddress
(
)
)
{
const
BlockAddress
*
BA
=
cast
<
CSKYConstantPoolConstant
>
(
CCPV
)
->
getBlockAddress
(
)
;
MCSym
=
GetBlockAddressSymbol
(
BA
)
;
}
else
if
(
CCPV
->
isGlobalValue
(
)
)
{
const
GlobalValue
*
GV
=
cast
<
CSKYConstantPoolConstant
>
(
CCPV
)
->
getGV
(
)
;
MCSym
=
getSymbol
(
GV
)
;
}
else
if
(
CCPV
->
isMachineBasicBlock
(
)
)
{
const
MachineBasicBlock
*
MBB
=
cast
<
CSKYConstantPoolMBB
>
(
CCPV
)
->
getMBB
(
)
;
MCSym
=
MBB
->
getSymbol
(
)
;
}
else
if
(
CCPV
->
isJT
(
)
)
{
signed
JTI
=
cast
<
CSKYConstantPoolJT
>
(
CCPV
)
->
getJTI
(
)
;
MCSym
=
GetJTISymbol
(
JTI
)
;
}
else
{
assert
(
CCPV
->
isExtSymbol
(
)
&&
"unrecognized constant pool value"
)
;
StringRef
Sym
=
cast
<
CSKYConstantPoolSymbol
>
(
CCPV
)
->
getSymbol
(
)
;
MCSym
=
GetExternalSymbolSymbol
(
Sym
)
;
}
const
MCExpr
*
Expr
=
MCSymbolRefExpr
::
create
(
MCSym
,
MCSymbolRefExpr
::
VK_None
,
OutContext
)
;
if
(
CCPV
->
getPCAdjustment
(
)
)
{
MCSymbol
*
PCLabel
=
OutContext
.
getOrCreateSymbol
(
Twine
(
MAI
->
getPrivateGlobalPrefix
(
)
)
+
"PC"
+
Twine
(
getFunctionNumber
(
)
)
+
"_"
+
Twine
(
CCPV
->
getLabelID
(
)
)
)
;
const
MCExpr
*
PCRelExpr
=
MCSymbolRefExpr
::
create
(
PCLabel
,
OutContext
)
;
if
(
CCPV
->
mustAddCurrentAddress
(
)
)
{
MCSymbol
*
DotSym
=
OutContext
.
createTempSymbol
(
)
;
OutStreamer
->
emitLabel
(
DotSym
)
;
const
MCExpr
*
DotExpr
=
MCSymbolRefExpr
::
create
(
DotSym
,
OutContext
)
;
PCRelExpr
=
MCBinaryExpr
::
createSub
(
PCRelExpr
,
DotExpr
,
OutContext
)
;
}
Expr
=
MCBinaryExpr
::
createSub
(
Expr
,
PCRelExpr
,
OutContext
)
;
}
Expr
=
CSKYMCExpr
::
create
(
Expr
,
getModifierVariantKind
(
CCPV
->
getModifier
(
)
)
,
OutContext
)
;
OutStreamer
->
emitValue
(
Expr
,
Size
)
;
}
</s>

EmitMachineConstantPoolValue - Print a machine constantpool value to the .s file .

CSKY
CSKY
CSKY
CSKY
CSKY
CSKY
CSKY
CSKY
"unrecognized constant pool value"
CSKY
"PC"
"_"
CSKY


<s> const PPCSubtarget * getSubtargetImpl ( ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> TargetLowering :: AtomicExpansionKind ARMTargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { bool has64BitAtomicLoad ; if ( Subtarget -> isMClass ( ) ) has64BitAtomicLoad = false ; else if ( Subtarget -> isThumb ( ) ) has64BitAtomicLoad = Subtarget -> hasV7Ops ( ) ; else has64BitAtomicLoad = Subtarget -> hasV6Ops ( ) ; unsigned Size = LI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return ( Size == 64 && has64BitAtomicLoad ) ? AtomicExpansionKind :: LLOnly : AtomicExpansionKind :: None ; } </s>

Returns how the given ( atomic ) load should be expanded by the IR-level AtomicExpand pass .


<s> void SIInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; SIMachineFunctionInfo * MFI = MBB . getParent ( ) -> getInfo < SIMachineFunctionInfo > ( ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; if ( TRI -> getCommonSubClass ( RC , & AMDGPU :: SReg_32RegClass ) ) { SIMachineFunctionInfo :: SpilledReg Spill = MFI -> SpillTracker . getSpilledReg ( FrameIndex ) ; assert ( Spill . VGPR ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: V_READLANE_B32 ) , DestReg ) . addReg ( Spill . VGPR ) . addImm ( Spill . Lane ) ; } else { for ( unsigned i = 0 , e = RC -> getSize ( ) / 4 ; i != e ; ++ i ) { unsigned Flags = RegState :: Define ; if ( i == 0 ) { Flags |= RegState :: Undef ; } unsigned SubReg = MRI . createVirtualRegister ( & AMDGPU :: SReg_32RegClass ) ; loadRegFromStackSlot ( MBB , MI , SubReg , FrameIndex + i , & AMDGPU :: SReg_32RegClass , TRI ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: COPY ) ) . addReg ( DestReg , Flags , RI . getSubRegFromChannel ( i ) ) . addReg ( SubReg ) ; } } } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> bool LanaiInstrInfo :: expandPostRAPseudo ( MachineInstr & ) const { return false ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> void setType ( StringRef Type ) { CurType = Type ; } </s>


<s> void cr16_init_cumulative_args ( CUMULATIVE_ARGS * cum , tree fntype , rtx libfunc ATTRIBUTE_UNUSED ) { tree param , next_param ; cum -> ints = 0 ; for ( param = ( fntype ) ? TYPE_ARG_TYPES ( fntype ) : 0 ; param != NULL_TREE ; param = next_param ) { next_param = TREE_CHAIN ( param ) ; if ( ( next_param == NULL_TREE ) && ( TREE_VALUE ( param ) != void_type_node ) ) { cum -> ints = - 1 ; return ; } } } </s>

Implements the macro INIT_CUMULATIVE_ARGS defined in cr16.h .


"%qs is only valid for the cell processor"

"%qs requires ISA 3.0 IEEE 128-bit floating point"

"%qs requires the %qs (or newer), and %qs or %qs options"

"%qs is not supported with the current options"

Raise an error message for a builtin function that is called without the appropriate target options being set .


"The function works only with LEA instructions"


<s> bool isMem ( ) const { return Kind == Memory ; } </s>


<s> static bool v850_handle_option ( size_t code , const char * arg , int value ATTRIBUTE_UNUSED ) { switch ( code ) { case OPT_mspace : target_flags |= MASK_EP | MASK_PROLOG_FUNCTION ; return true ; case OPT_mv850 : target_flags &= ~ ( MASK_CPU ^ MASK_V850 ) ; return true ; case OPT_mv850e : case OPT_mv850e1 : target_flags &= ~ ( MASK_CPU ^ MASK_V850E ) ; return true ; case OPT_mtda : return v850_handle_memory_option ( SMALL_MEMORY_TDA , arg ) ; case OPT_msda : return v850_handle_memory_option ( SMALL_MEMORY_SDA , arg ) ; case OPT_mzda : return v850_handle_memory_option ( SMALL_MEMORY_ZDA , arg ) ; default : return true ; } } </s>


<s> rtx legitimize_pic_address ( rtx orig , rtx reg ) { if ( GET_CODE ( orig ) == LABEL_REF || ( GET_CODE ( orig ) == SYMBOL_REF && ( CONSTANT_POOL_ADDRESS_P ( orig ) || ! MN10300_GLOBAL_P ( orig ) ) ) ) { if ( reg == 0 ) reg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_symGOTOFF2reg ( reg , orig ) ) ; return reg ; } else if ( GET_CODE ( orig ) == SYMBOL_REF ) { if ( reg == 0 ) reg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_symGOT2reg ( reg , orig ) ) ; return reg ; } return orig ; } </s>

Legitimize PIC addresses . If the address is already position-independent , we return ORIG . Newly generated position-independent addresses go into a reg . This is REG if nonzero , otherwise we allocate register ( s ) as necessary .


<s>
bool
AArch64InstrInfo
::
isCandidateToMergeOrPair
(
MachineInstr
*
MI
)
const
{
if
(
MI
->
hasOrderedMemoryRef
(
)
)
return
false
;
assert
(
MI
->
getOperand
(
1
)
.
isReg
(
)
&&
"Expected a reg operand."
)
;
if
(
!
MI
->
getOperand
(
2
)
.
isImm
(
)
)
return
false
;
unsigned
BaseReg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
if
(
MI
->
modifiesRegister
(
BaseReg
,
TRI
)
)
return
false
;
if
(
isLdStPairSuppressed
(
MI
)
)
return
false
;
if
(
Subtarget
.
avoidQuadLdStPairs
(
)
)
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
AArch64
::
LDURQi
:
case
AArch64
::
STURQi
:
case
AArch64
::
LDRQui
:
case
AArch64
::
STRQui
:
return
false
;
}
}
return
true
;
}
</s>

Return true if this is a load/store that can be potentially paired/merged .


<s> static tree cris_md_asm_clobbers ( tree outputs , tree inputs , tree in_clobbers ) { HARD_REG_SET mof_set ; tree clobbers ; tree t ; CLEAR_HARD_REG_SET ( mof_set ) ; SET_HARD_REG_BIT ( mof_set , CRIS_MOF_REGNUM ) ; clobbers = tree_cons ( NULL_TREE , build_string ( strlen ( reg_names [ CRIS_CC0_REGNUM ] ) , reg_names [ CRIS_CC0_REGNUM ] ) , in_clobbers ) ; for ( t = outputs ; t != NULL ; t = TREE_CHAIN ( t ) ) { tree val = TREE_VALUE ( t ) ; if ( strchr ( TREE_STRING_POINTER ( TREE_VALUE ( TREE_PURPOSE ( t ) ) ) , 'h' ) != NULL || tree_overlaps_hard_reg_set ( val , & mof_set ) != NULL_TREE ) return clobbers ; } for ( t = inputs ; t != NULL ; t = TREE_CHAIN ( t ) ) { tree val = TREE_VALUE ( t ) ; if ( strchr ( TREE_STRING_POINTER ( TREE_VALUE ( TREE_PURPOSE ( t ) ) ) , 'h' ) != NULL || tree_overlaps_hard_reg_set ( val , & mof_set ) != NULL_TREE ) return clobbers ; } return tree_cons ( NULL_TREE , build_string ( strlen ( reg_names [ CRIS_MOF_REGNUM ] ) , reg_names [ CRIS_MOF_REGNUM ] ) , clobbers ) ; } </s>

Worker function for TARGET_MD_ASM_CLOBBERS .


<s>
bool
X86CallLowering
::
lowerReturn
(
MachineIRBuilder
&
MIRBuilder
,
const
Value
*
Val
,
ArrayRef
<
Register
>
VRegs
,
FunctionLoweringInfo
&
FLI
)
const
{
assert
(
(
(
Val
&&
!
VRegs
.
empty
(
)
)
||
(
!
Val
&&
VRegs
.
empty
(
)
)
)
&&
"Return value without a vreg"
)
;
auto
MIB
=
MIRBuilder
.
buildInstrNoInsert
(
X86
::
RET
)
.
addImm
(
0
)
;
if
(
!
VRegs
.
empty
(
)
)
{
MachineFunction
&
MF
=
MIRBuilder
.
getMF
(
)
;
const
Function
&
F
=
MF
.
getFunction
(
)
;
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
const
DataLayout
&
DL
=
MF
.
getDataLayout
(
)
;
ArgInfo
OrigRetInfo
(
VRegs
,
Val
->
getType
(
)
,
0
)
;
setArgFlags
(
OrigRetInfo
,
AttributeList
::
ReturnIndex
,
DL
,
F
)
;
SmallVector
<
ArgInfo
,
4
>
SplitRetInfos
;
splitToValueTypes
(
OrigRetInfo
,
SplitRetInfos
,
DL
,
F
.
getCallingConv
(
)
)
;
X86OutgoingValueAssigner
Assigner
(
RetCC_X86
)
;
X86OutgoingValueHandler
Handler
(
MIRBuilder
,
MRI
,
MIB
)
;
if
(
!
determineAndHandleAssignments
(
Handler
,
Assigner
,
SplitRetInfos
,
MIRBuilder
,
F
.
getCallingConv
(
)
,
F
.
isVarArg
(
)
)
)
return
false
;
}
MIRBuilder
.
insertInstr
(
MIB
)
;
return
true
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> const char * SPUTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { if ( node_names . empty ( ) ) { node_names [ ( unsigned ) SPUISD :: RET_FLAG ] = "SPUISD::RET_FLAG" ; node_names [ ( unsigned ) SPUISD :: Hi ] = "SPUISD::Hi" ; node_names [ ( unsigned ) SPUISD :: Lo ] = "SPUISD::Lo" ; node_names [ ( unsigned ) SPUISD :: PCRelAddr ] = "SPUISD::PCRelAddr" ; node_names [ ( unsigned ) SPUISD :: AFormAddr ] = "SPUISD::AFormAddr" ; node_names [ ( unsigned ) SPUISD :: IndirectAddr ] = "SPUISD::IndirectAddr" ; node_names [ ( unsigned ) SPUISD :: LDRESULT ] = "SPUISD::LDRESULT" ; node_names [ ( unsigned ) SPUISD :: CALL ] = "SPUISD::CALL" ; node_names [ ( unsigned ) SPUISD :: SHUFB ] = "SPUISD::SHUFB" ; node_names [ ( unsigned ) SPUISD :: SHUFFLE_MASK ] = "SPUISD::SHUFFLE_MASK" ; node_names [ ( unsigned ) SPUISD :: CNTB ] = "SPUISD::CNTB" ; node_names [ ( unsigned ) SPUISD :: PREFSLOT2VEC ] = "SPUISD::PREFSLOT2VEC" ; node_names [ ( unsigned ) SPUISD :: VEC2PREFSLOT ] = "SPUISD::VEC2PREFSLOT" ; node_names [ ( unsigned ) SPUISD :: SHLQUAD_L_BITS ] = "SPUISD::SHLQUAD_L_BITS" ; node_names [ ( unsigned ) SPUISD :: SHLQUAD_L_BYTES ] = "SPUISD::SHLQUAD_L_BYTES" ; node_names [ ( unsigned ) SPUISD :: VEC_ROTL ] = "SPUISD::VEC_ROTL" ; node_names [ ( unsigned ) SPUISD :: VEC_ROTR ] = "SPUISD::VEC_ROTR" ; node_names [ ( unsigned ) SPUISD :: ROTBYTES_LEFT ] = "SPUISD::ROTBYTES_LEFT" ; node_names [ ( unsigned ) SPUISD :: ROTBYTES_LEFT_BITS ] = "SPUISD::ROTBYTES_LEFT_BITS" ; node_names [ ( unsigned ) SPUISD :: SELECT_MASK ] = "SPUISD::SELECT_MASK" ; node_names [ ( unsigned ) SPUISD :: SELB ] = "SPUISD::SELB" ; node_names [ ( unsigned ) SPUISD :: ADD64_MARKER ] = "SPUISD::ADD64_MARKER" ; node_names [ ( unsigned ) SPUISD :: SUB64_MARKER ] = "SPUISD::SUB64_MARKER" ; node_names [ ( unsigned ) SPUISD :: MUL64_MARKER ] = "SPUISD::MUL64_MARKER" ; } std :: map < unsigned , const char * > :: iterator i = node_names . find ( Opcode ) ; return ( ( i != node_names . end ( ) ) ? i -> second : 0 ) ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s>
static
bool
cortexa7_younger
(
FILE
*
file
,
int
verbose
,
rtx_insn
*
insn
)
{
if
(
recog_memoized
(
insn
)
<
0
)
{
if
(
verbose
>
5
)
fprintf
(
file
,
";; not cortexa7_younger %d\n"
,
INSN_UID
(
insn
)
)
;
return
false
;
}
switch
(
get_attr_type
(
insn
)
)
{
case
TYPE_ALU_IMM
:
case
TYPE_ALUS_IMM
:
case
TYPE_LOGIC_IMM
:
case
TYPE_LOGICS_IMM
:
case
TYPE_EXTEND
:
case
TYPE_MVN_IMM
:
case
TYPE_MOV_IMM
:
case
TYPE_MOV_REG
:
case
TYPE_MOV_SHIFT
:
case
TYPE_MOV_SHIFT_REG
:
case
TYPE_BRANCH
:
case
TYPE_CALL
:
return
true
;
default
:
return
false
;
}
}
</s>

Return true if and only if this insn can dual-issue as younger .


<s> static bool isBranch ( unsigned Opcode ) { return Opcode == AMDGPU :: BRANCH || Opcode == AMDGPU :: BRANCH_COND_i32 || Opcode == AMDGPU :: BRANCH_COND_f32 ; } </s>

Returns true if this is a conditional , unconditional , or indirect branch .


<s> bool xxspltib_constant_p ( rtx op , machine_mode mode , int * num_insns_ptr , int * constant_ptr ) { size_t nunits = GET_MODE_NUNITS ( mode ) ; size_t i ; HOST_WIDE_INT value ; rtx element ; * num_insns_ptr = - 1 ; * constant_ptr = 256 ; if ( ! TARGET_P9_VECTOR ) return false ; if ( mode == VOIDmode ) mode = GET_MODE ( op ) ; else if ( mode != GET_MODE ( op ) && GET_MODE ( op ) != VOIDmode ) return false ; if ( GET_CODE ( op ) == VEC_DUPLICATE ) { if ( mode != V16QImode && mode != V8HImode && mode != V4SImode && mode != V2DImode ) return false ; element = XEXP ( op , 0 ) ; if ( ! CONST_INT_P ( element ) ) return false ; value = INTVAL ( element ) ; if ( ! IN_RANGE ( value , - 128 , 127 ) ) return false ; } else if ( GET_CODE ( op ) == CONST_VECTOR ) { if ( mode != V16QImode && mode != V8HImode && mode != V4SImode && mode != V2DImode ) return false ; element = CONST_VECTOR_ELT ( op , 0 ) ; if ( ! CONST_INT_P ( element ) ) return false ; value = INTVAL ( element ) ; if ( ! IN_RANGE ( value , - 128 , 127 ) ) return false ; for ( i = 1 ; i < nunits ; i ++ ) { element = CONST_VECTOR_ELT ( op , i ) ; if ( ! CONST_INT_P ( element ) ) return false ; if ( value != INTVAL ( element ) ) return false ; } } else if ( CONST_INT_P ( op ) ) { if ( ! SCALAR_INT_MODE_P ( mode ) ) return false ; value = INTVAL ( op ) ; if ( ! IN_RANGE ( value , - 128 , 127 ) ) return false ; if ( ! IN_RANGE ( value , - 1 , 0 ) ) { if ( ! ( reg_addr [ mode ] . addr_mask [ RELOAD_REG_VMX ] & RELOAD_REG_VALID ) ) return false ; if ( EASY_VECTOR_15 ( value ) ) return false ; } } else return false ; if ( ( mode == V4SImode || mode == V8HImode ) && ! IN_RANGE ( value , - 1 , 0 ) && EASY_VECTOR_15 ( value ) ) return false ; if ( mode == V16QImode ) * num_insns_ptr = 1 ; else if ( IN_RANGE ( value , - 1 , 0 ) ) * num_insns_ptr = 1 ; else * num_insns_ptr = 2 ; * constant_ptr = ( int ) value ; return true ; } </s>

Return true if OP is of the given MODE and can be synthesized with ISA 3.0 instructions ( xxspltib , vupkhsb/vextsb2w/vextb2d ) . Return the number of instructions needed ( 1 or 2 ) into the address pointed via NUM_INSNS_PTR . Return the constant that is being split via CONSTANT_PTR .


<s> unsigned int rs6000_dbx_register_number ( unsigned int regno , unsigned int format ) { if ( SPE_HIGH_REGNO_P ( regno ) ) return regno - FIRST_SPE_HIGH_REGNO + 1200 ; if ( ( format == 0 && write_symbols != DWARF2_DEBUG ) || format == 2 ) return regno ; if ( regno <= 63 ) return regno ; if ( regno == LR_REGNO ) return 108 ; if ( regno == CTR_REGNO ) return 109 ; if ( format == 1 && regno == CR2_REGNO ) return 64 ; if ( CR_REGNO_P ( regno ) ) return regno - CR0_REGNO + 86 ; if ( regno == CA_REGNO ) return 101 ; if ( ALTIVEC_REGNO_P ( regno ) ) return regno - FIRST_ALTIVEC_REGNO + 1124 ; if ( regno == VRSAVE_REGNO ) return 356 ; if ( regno == VSCR_REGNO ) return 67 ; if ( regno == SPE_ACC_REGNO ) return 99 ; if ( regno == SPEFSCR_REGNO ) return 612 ; return regno ; } </s>

Map internal gcc register numbers to DWARF2 register numbers .


"attribute %<target%> argument not a string"

Parse the tree in ARGS that contains the target attribute information and update the global target options space . PRAGMA_OR_ATTR is a string to be used in error messages , specifying whether this is processing a target attribute or a target pragma .


<s> static rtx_insn * emit_window_save ( rtx increment ) { rtx_insn * insn = emit_insn ( gen_window_save ( increment ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_REGISTER , gen_rtx_SET ( gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) , gen_rtx_REG ( Pmode , INCOMING_RETURN_ADDR_REGNUM ) ) ) ; add_reg_note ( insn , REG_CFA_WINDOW_SAVE , const0_rtx ) ; add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , hard_frame_pointer_rtx , INCOMING_FRAME_SP_OFFSET ) ) ; return insn ; } </s>


"MIPS16 PIC for ABIs other than o32 and o64"

"hard-float MIPS16 code for ABIs other than o32 and o64"

Set up the target-dependent global state for ISA mode COMPRESSION_MODE , which is either MASK_MIPS16 or MASK_MICROMIPS .


<s> int find_post_update_rtx ( rtx_insn * insn ) { rtx mem_rtx ; int i , len ; switch ( get_attr_type ( insn ) ) { case TYPE_LOAD_MULTIPLE : case TYPE_STORE_MULTIPLE : len = parallel_elements ( insn ) ; for ( i = 0 ; i < len ; ++ i ) { rtx curr_insn = parallel_element ( insn , i ) ; if ( GET_CODE ( curr_insn ) == SET && REG_P ( SET_DEST ( curr_insn ) ) && GET_CODE ( SET_SRC ( curr_insn ) ) == PLUS ) return i ; } return - 1 ; case TYPE_LOAD : case TYPE_FLOAD : case TYPE_STORE : case TYPE_FSTORE : mem_rtx = extract_mem_rtx ( insn ) ; switch ( GET_CODE ( XEXP ( mem_rtx , 0 ) ) ) { case POST_INC : case POST_DEC : case POST_MODIFY : return 0 ; default : return - 1 ; } default : gcc_unreachable ( ) ; } } </s>

Find the post update rtx in INSN . If INSN is a load/store multiple insn , the function returns the vector index of its parallel part . If INSN is a single load/store insn , the function returns 0 . If INSN is not a post- update insn , the function returns -1 .


"function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n"

A C statement ( sans semicolon ) to update the summarizer variable CUM to advance past an argument in the argument list . The values MODE , TYPE and NAMED describe that argument . Once this is done , the variable CUM is suitable for analyzing the * following * argument with ` FUNCTION_ARG ' , etc . This macro need not do anything if the argument in question was passed on the stack . The compiler knows how to track the amount of stack space used for arguments without any special help .


"Missing call preserved mask for calling convention"

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


<s> MCSectionGBZ80 * GBZ80TargetObjectFile :: getSection ( SectionKind Kind , StringRef N , GBSectionType T , uint16_t A , unsigned B , unsigned Align , const GlobalObject * GO ) const { GBZ80SectionData Data ( N , T , A , B , Align , GO ) ; if ( Sections . count ( Data ) ) return Sections [ Data ] ; MCSectionGBZ80 * Section = new MCSectionGBZ80 ( Kind , Data , nullptr ) ; Sections [ Data ] = Section ; return Section ; } </s>

Get the section associated with a defined , non-absolute symbol .


<s> static bool Check ( DecodeStatus & Out , DecodeStatus In ) { switch ( In ) { case MCDisassembler :: Success : return true ; case MCDisassembler :: SoftFail : Out = In ; return true ; case MCDisassembler :: Fail : Out = In ; return false ; } return false ; } </s>

Matches check string and its `` not strings '' and/or `` dag strings '' .


<s> static void arc_override_options ( void ) { if ( arc_cpu == PROCESSOR_NONE ) arc_cpu = PROCESSOR_ARC700 ; if ( arc_size_opt_level == 3 ) optimize_size = 1 ; if ( flag_pic ) target_flags |= MASK_NO_SDATA_SET ; if ( flag_no_common == 255 ) flag_no_common = ! TARGET_NO_SDATA_SET ; \ if ( TARGET_MIXED_CODE ) TARGET_Q_CLASS = 1 ; if ( ! TARGET_Q_CLASS ) TARGET_COMPACT_CASESI = 0 ; if ( TARGET_COMPACT_CASESI ) TARGET_CASE_VECTOR_PC_RELATIVE = 1 ; arc_init ( ) ; } </s>

Check ARC options , generate derived target attributes .


<s> bool AMDGPUCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function :: ArgumentListType & Args , const SmallVectorImpl < unsigned > & VRegs ) const { return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> static HOST_WIDE_INT cris_constant_alignment ( const_tree , HOST_WIDE_INT basic_align ) { return MAX ( cris_preferred_minimum_alignment ( ) , basic_align ) ; } </s>

Implement TARGET_CONSTANT_ALIGNMENT . Note that this hook has the effect of making gcc believe that ALL references to constant stuff ( in code segment , like strings ) have this alignment . That is a rather rushed assumption . Luckily we do not care about the `` alignment '' operand to builtin memcpy ( only place where it counts ) , so it does n't affect any bad spots .


<s> bool ARMBaseInstrInfo :: PredicateInstruction ( MachineInstr * MI , const SmallVectorImpl < MachineOperand > & Pred ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( isUncondBranchOpcode ( Opc ) ) { MI -> setDesc ( get ( getMatchingCondBranchOpcode ( Opc ) ) ) ; MachineInstrBuilder ( * MI -> getParent ( ) -> getParent ( ) , MI ) . addImm ( Pred [ 0 ] . getImm ( ) ) . addReg ( Pred [ 1 ] . getReg ( ) ) ; return true ; } int PIdx = MI -> findFirstPredOperandIdx ( ) ; if ( PIdx != - 1 ) { MachineOperand & PMO = MI -> getOperand ( PIdx ) ; PMO . setImm ( Pred [ 0 ] . getImm ( ) ) ; MI -> getOperand ( PIdx + 1 ) . setReg ( Pred [ 1 ] . getReg ( ) ) ; return true ; } return false ; } </s>

Convert the instruction into a predicated instruction .


<s> bool PPCTargetLowering :: useLoadStackGuardNode ( ) const { if ( ! Subtarget . isTargetLinux ( ) ) return TargetLowering :: useLoadStackGuardNode ( ) ; return true ; } </s>

If this function returns true , SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic : :stackprotector .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TargetABI ( computeTargetABI ( TT , CPU , Options ) ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) { if ( isTargetHardFloat ( ) ) this -> Options . FloatABIType = FloatABI :: Hard ; else this -> Options . FloatABIType = FloatABI :: Soft ; } if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( ( TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABI || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF ) && ! ( TargetTriple . isOSWindows ( ) || TargetTriple . isOSDarwin ( ) ) ) this -> Options . EABIVersion = EABI :: GNU ; else this -> Options . EABIVersion = EABI :: EABI5 ; } if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } initAsmInfo ( ) ; } </s>


<s> static rtx c6x_sched_dfa_pre_cycle_insn ( void ) { return const0_rtx ; } </s>

Used together with the collapse_ndfa option , this ensures that we reach a deterministic automaton state before trying to advance a cycle . With collapse_ndfa , genautomata creates advance cycle arcs only for such deterministic states .


<s> void LanaiInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annotation , const MCSubtargetInfo & ) { if ( ! printAlias ( MI , OS ) && ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annotation ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static unsigned long rs6000_arg_size ( enum machine_mode mode , tree type ) { unsigned long size ; if ( mode != BLKmode ) size = GET_MODE_SIZE ( mode ) ; else size = int_size_in_bytes ( type ) ; if ( TARGET_32BIT ) return ( size + 3 ) >> 2 ; else return ( size + 7 ) >> 3 ; } </s>

Compute the size ( in words ) of a function argument .


<s> static bool classof ( const DiagnosticInfo * DI ) { return DI -> getKind ( ) == getKindID ( ) ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> bool ARMTargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { unsigned Size = LI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return ( Size == 64 ) && ! Subtarget -> isMClass ( ) ; } </s>

Returns how the given ( atomic ) load should be expanded by the IR-level AtomicExpand pass .


<s> bool RISCVTargetLowering :: shouldSinkOperands ( Instruction * I , SmallVectorImpl < Use * > & Ops ) const { using namespace llvm :: PatternMatch ; if ( ! I -> getType ( ) -> isVectorTy ( ) || ! Subtarget . hasVInstructions ( ) ) return false ; auto IsSinker = [ & ] ( Instruction * I , int Operand ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Add : case Instruction :: Sub : case Instruction :: Mul : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : case Instruction :: FAdd : case Instruction :: FSub : case Instruction :: FMul : case Instruction :: FDiv : case Instruction :: ICmp : case Instruction :: FCmp : return true ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return Operand == 1 ; case Instruction :: Call : if ( auto * II = dyn_cast < IntrinsicInst > ( I ) ) { switch ( II -> getIntrinsicID ( ) ) { case Intrinsic :: fma : return Operand == 0 || Operand == 1 ; default : return false ; } } return false ; default : return false ; } } ; for ( auto OpIdx : enumerate ( I -> operands ( ) ) ) { if ( ! IsSinker ( I , OpIdx . index ( ) ) ) continue ; Instruction * Op = dyn_cast < Instruction > ( OpIdx . value ( ) . get ( ) ) ; if ( ! Op || any_of ( Ops , [ & ] ( Use * U ) { return U -> get ( ) == Op ; } ) ) continue ; if ( ! match ( Op , m_Shuffle ( m_InsertElt ( m_Undef ( ) , m_Value ( ) , m_ZeroInt ( ) ) , m_Undef ( ) , m_ZeroMask ( ) ) ) ) continue ; for ( Use & U : Op -> uses ( ) ) { Instruction * Insn = cast < Instruction > ( U . getUser ( ) ) ; if ( ! IsSinker ( Insn , U . getOperandNo ( ) ) ) return false ; } Ops . push_back ( & Op -> getOperandUse ( 0 ) ) ; Ops . push_back ( & OpIdx . value ( ) ) ; } return true ; } </s>

Return true if sinking I 's operands to the same basic block as I is profitable , e.g .


<s> static const simd_vec_cost * aarch64_simd_vec_costs_for_flags ( unsigned int flags ) { const cpu_vector_cost * costs = aarch64_tune_params . vec_costs ; if ( ( flags & VEC_ANY_SVE ) && costs -> sve ) return costs -> sve ; return costs -> advsimd ; } </s>

Return the appropriate SIMD costs for vectors with VEC_ * flags FLAGS .


"********** Replace Physical Registers **********\n"

"LiveIntervals shouldn't be active yet!"

runOnMachineFunction - Emit the function body .


<s> static tree build_processor_model_struct ( void ) { const char * field_name [ ] = { "__cpu_vendor" , "__cpu_type" , "__cpu_subtype" , "__cpu_features" } ; tree field = NULL_TREE , field_chain = NULL_TREE ; int i ; tree type = make_node ( RECORD_TYPE ) ; for ( i = 0 ; i < 3 ; ++ i ) { field = build_decl ( UNKNOWN_LOCATION , FIELD_DECL , get_identifier ( field_name [ i ] ) , unsigned_type_node ) ; if ( field_chain != NULL_TREE ) DECL_CHAIN ( field ) = field_chain ; field_chain = field ; } field = build_decl ( UNKNOWN_LOCATION , FIELD_DECL , get_identifier ( field_name [ 3 ] ) , build_array_type ( unsigned_type_node , build_index_type ( size_one_node ) ) ) ; if ( field_chain != NULL_TREE ) DECL_CHAIN ( field ) = field_chain ; field_chain = field ; finish_builtin_struct ( type , "__processor_model" , field_chain , NULL_TREE ) ; return type ; } </s>

This builds the processor_model struct type defined in libgcc/config/i386/cpuinfo.c


"***** Machine Function before Domain Reassignment *****\n"

"***** Machine Function after Domain Reassignment *****\n"


<s>
void
XtensaInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
Xtensa
::
GPRRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
Xtensa
::
MOV_r
)
,
DestReg
)
.
addReg
(
SrcReg
)
;
}
else
{
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
}
</s>

Xtensa
Xtensa
Xtensa::GPRRegClass
Xtensa::MOV_r
"Impossible reg-to-reg copy"


<s> DecodeStatus AGCDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & OS , raw_ostream & CS ) const { uint16_t Instruction ; DecodeStatus Result ; Instruction = support :: endian :: read16be ( Bytes . data ( ) ) ; Instruction = ( Instruction & 0xFFFE ) >> 1 ; Result = decodeInstruction ( DecoderTable16 , MI , Instruction , Address , this , STI ) ; if ( MI . getOpcode ( ) != AGC :: EXTEND ) { Size = 2 ; return Result ; } Instruction = support :: endian :: read16be ( Bytes . drop_front ( 2 ) . data ( ) ) ; Instruction = ( Instruction & 0xFFFE ) >> 1 ; Result = decodeInstruction ( DecoderTableExtracode16 , MI , Instruction , Address , this , STI ) ; Size = 4 ; return Result ; } </s>

Returns the disassembly of a single instruction .


<s> const uint16_t * SparcRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_SaveList ; } </s>


<s> bool aarch64_simd_shift_imm_p ( rtx x , machine_mode mode , bool left ) { x = unwrap_const_vec_duplicate ( x ) ; if ( ! CONST_INT_P ( x ) ) return false ; int bit_width = GET_MODE_UNIT_SIZE ( mode ) * BITS_PER_UNIT ; if ( left ) return IN_RANGE ( INTVAL ( x ) , 0 , bit_width - 1 ) ; else return IN_RANGE ( INTVAL ( x ) , 1 , bit_width ) ; } </s>

Check of immediate shift constants are within range .


<s> void m32r_init_expanders ( void ) { } </s>

Do anything needed before RTL is emitted for each function .


<s> bool AArch64RegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MFI -> hasVarSizedObjects ( ) && ! hasBasePointer ( MF ) ; } </s>

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot .


initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> static void rl78_alloc_physical_registers_cmp ( rtx_insn * insn ) { int tmp_id ; rtx saved_op1 ; rtx_insn * prev = prev_nonnote_nondebug_insn ( insn ) ; rtx first ; OP ( 1 ) = transcode_memory_rtx ( OP ( 1 ) , DE , insn ) ; OP ( 2 ) = transcode_memory_rtx ( OP ( 2 ) , HL , insn ) ; MAYBE_OK ( insn ) ; if ( REG_P ( OP ( 1 ) ) && REGNO ( OP ( 1 ) ) != AX_REG && GET_MODE ( OP ( 1 ) ) == HImode && MEM_P ( OP ( 2 ) ) ) { rtx cmp = XEXP ( SET_SRC ( PATTERN ( insn ) ) , 0 ) ; OP ( 2 ) = move_to_acc ( 2 , insn ) ; switch ( GET_CODE ( cmp ) ) { case EQ : case NE : break ; case LTU : cmp = gen_rtx_GTU ( HImode , OP ( 2 ) , OP ( 1 ) ) ; break ; case GTU : cmp = gen_rtx_LTU ( HImode , OP ( 2 ) , OP ( 1 ) ) ; break ; case LEU : cmp = gen_rtx_GEU ( HImode , OP ( 2 ) , OP ( 1 ) ) ; break ; case GEU : cmp = gen_rtx_LEU ( HImode , OP ( 2 ) , OP ( 1 ) ) ; break ; case LT : case GT : case LE : case GE : debug_rtx ( insn ) ; default : gcc_unreachable ( ) ; } if ( GET_CODE ( cmp ) == EQ || GET_CODE ( cmp ) == NE ) PATTERN ( insn ) = gen_cbranchhi4_real ( cmp , OP ( 2 ) , OP ( 1 ) , OP ( 3 ) ) ; else PATTERN ( insn ) = gen_cbranchhi4_real_inverted ( cmp , OP ( 2 ) , OP ( 1 ) , OP ( 3 ) ) ; MUST_BE_OK ( insn ) ; } if ( rtx_equal_p ( OP ( 1 ) , OP ( 2 ) ) ) { OP ( 1 ) = OP ( 2 ) = BC ; MUST_BE_OK ( insn ) ; } tmp_id = get_max_insn_count ( ) ; saved_op1 = OP ( 1 ) ; OP ( 1 ) = move_to_acc ( 1 , insn ) ; MAYBE_OK ( insn ) ; if ( tmp_id == get_max_insn_count ( ) ) force_into_acc ( saved_op1 , insn ) ; if ( prev ) first = next_nonnote_nondebug_insn ( prev ) ; else for ( first = insn ; prev_nonnote_nondebug_insn ( first ) ; first = prev_nonnote_nondebug_insn ( first ) ) ; OP ( 2 ) = move_to_hl ( 2 , first ) ; MUST_BE_OK ( insn ) ; } </s>


<s> std :: pair < SDValue , SDValue > SystemZSelectionDAGInfo :: EmitTargetCodeForMemchr ( SelectionDAG & DAG , SDLoc DL , SDValue Chain , SDValue Src , SDValue Char , SDValue Length , MachinePointerInfo SrcPtrInfo ) const { EVT PtrVT = Src . getValueType ( ) ; SDVTList VTs = DAG . getVTList ( PtrVT , MVT :: Other , MVT :: Glue ) ; Length = DAG . getZExtOrTrunc ( Length , DL , PtrVT ) ; Char = DAG . getZExtOrTrunc ( Char , DL , MVT :: i32 ) ; Char = DAG . getNode ( ISD :: AND , DL , MVT :: i32 , Char , DAG . getConstant ( 255 , MVT :: i32 ) ) ; SDValue Limit = DAG . getNode ( ISD :: ADD , DL , PtrVT , Src , Length ) ; SDValue End = DAG . getNode ( SystemZISD :: SEARCH_STRING , DL , VTs , Chain , Limit , Src , Char ) ; Chain = End . getValue ( 1 ) ; SDValue Glue = End . getValue ( 2 ) ; SDValue Ops [ ] = { End , DAG . getConstant ( 0 , PtrVT ) , DAG . getConstant ( SystemZ :: CCMASK_SRST , MVT :: i32 ) , DAG . getConstant ( SystemZ :: CCMASK_SRST_FOUND , MVT :: i32 ) , Glue } ; VTs = DAG . getVTList ( PtrVT , MVT :: Glue ) ; End = DAG . getNode ( SystemZISD :: SELECT_CCMASK , DL , VTs , Ops ) ; return std :: make_pair ( End , Chain ) ; } </s>

Emit target-specific code that performs a memchr , in cases where that is faster than a libcall .


<s> const uint16_t * SPURegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t SPU_CalleeSaveRegs [ ] = { SPU :: R80 , SPU :: R81 , SPU :: R82 , SPU :: R83 , SPU :: R84 , SPU :: R85 , SPU :: R86 , SPU :: R87 , SPU :: R88 , SPU :: R89 , SPU :: R90 , SPU :: R91 , SPU :: R92 , SPU :: R93 , SPU :: R94 , SPU :: R95 , SPU :: R96 , SPU :: R97 , SPU :: R98 , SPU :: R99 , SPU :: R100 , SPU :: R101 , SPU :: R102 , SPU :: R103 , SPU :: R104 , SPU :: R105 , SPU :: R106 , SPU :: R107 , SPU :: R108 , SPU :: R109 , SPU :: R110 , SPU :: R111 , SPU :: R112 , SPU :: R113 , SPU :: R114 , SPU :: R115 , SPU :: R116 , SPU :: R117 , SPU :: R118 , SPU :: R119 , SPU :: R120 , SPU :: R121 , SPU :: R122 , SPU :: R123 , SPU :: R124 , SPU :: R125 , SPU :: R126 , SPU :: R127 , SPU :: R2 , SPU :: R1 , SPU :: R0 , 0 } ; return SPU_CalleeSaveRegs ; } </s>


"LM32 DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> size_t size ( ) const { return Vector . size ( ) ; } </s>

The number of name/type pairs is returned .


"getBranchTarget26OpValue expects only expressions or immediates"

getBranchTarget26OpValue - Return binary encoding of the branch target operand .


<s> AArch64Subtarget :: AArch64Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasV8_1aOps ( false ) , HasFPARMv8 ( false ) , HasNEON ( false ) , HasCrypto ( false ) , HasCRC ( false ) , HasZeroCycleRegMove ( false ) , HasZeroCycleZeroing ( false ) , IsLittle ( LittleEndian ) , CPUString ( CPU ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS ) ) , TSInfo ( TM . getDataLayout ( ) ) , TLInfo ( TM , * this ) { } </s>

This constructor initializes the data members to match that of the specified triple .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addPreserved < ScalarEvolutionWrapperPass > ( ) ; getLoopAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .