<s> rtx pa_legitimize_reload_address ( rtx ad , machine_mode mode , int opnum , int type , int ind_levels ATTRIBUTE_UNUSED ) { long offset , newoffset , mask ; rtx new_rtx , temp = NULL_RTX ; mask = ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && ! INT14_OK_STRICT ? 0x1f : 0x3fff ) ; if ( optimize && GET_CODE ( ad ) == PLUS ) temp = simplify_binary_operation ( PLUS , Pmode , XEXP ( ad , 0 ) , XEXP ( ad , 1 ) ) ; new_rtx = temp ? temp : ad ; if ( optimize && GET_CODE ( new_rtx ) == PLUS && GET_CODE ( XEXP ( new_rtx , 0 ) ) == REG && GET_CODE ( XEXP ( new_rtx , 1 ) ) == CONST_INT ) { offset = INTVAL ( XEXP ( ( new_rtx ) , 1 ) ) ; if ( ( offset & mask ) >= ( ( mask + 1 ) / 2 ) ) newoffset = ( offset & ~ mask ) + mask + 1 ; else newoffset = offset & ~ mask ; if ( mask == 0x3fff && ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || ( TARGET_64BIT && ( mode ) == DImode ) ) ) newoffset &= ~ ( GET_MODE_SIZE ( mode ) - 1 ) ; if ( newoffset != 0 && VAL_14_BITS_P ( newoffset ) ) { temp = gen_rtx_PLUS ( Pmode , XEXP ( new_rtx , 0 ) , GEN_INT ( newoffset ) ) ; ad = gen_rtx_PLUS ( Pmode , temp , GEN_INT ( offset - newoffset ) ) ; push_reload ( XEXP ( ad , 0 ) , 0 , & XEXP ( ad , 0 ) , 0 , BASE_REG_CLASS , Pmode , VOIDmode , 0 , 0 , opnum , ( enum reload_type ) type ) ; return ad ; } } return NULL_RTX ; } </s>

Look for machine dependent ways to make the invalid address AD a valid address . For the PA , transform : memory ( X + < large int > ) into : if ( < large int > & mask ) > = 16 Y = ( < large int > & ~mask ) + mask + 1 Round up . else Y = ( < large int > & ~mask ) Round down . Z = X + Y memory ( Z + ( < large int > - Y ) ) ; This makes reload inheritance and reload_cse work better since Z can be reused . There may be more opportunities to improve code with this hook .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"SI prepare scratch registers"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
bool
R600VectorRegMerger
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
if
(
skipFunction
(
Fn
.
getFunction
(
)
)
)
return
false
;
const
R600Subtarget
&
ST
=
Fn
.
getSubtarget
<
R600Subtarget
>
(
)
;
TII
=
ST
.
getInstrInfo
(
)
;
MRI
=
&
Fn
.
getRegInfo
(
)
;
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
MachineBasicBlock
*
MB
=
&
*
MBB
;
PreviousRegSeq
.
clear
(
)
;
PreviousRegSeqByReg
.
clear
(
)
;
PreviousRegSeqByUndefCount
.
clear
(
)
;
for
(
MachineBasicBlock
::
iterator
MII
=
MB
->
begin
(
)
,
MIIE
=
MB
->
end
(
)
;
MII
!=
MIIE
;
++
MII
)
{
MachineInstr
&
MI
=
*
MII
;
if
(
MI
.
getOpcode
(
)
!=
R600
::
REG_SEQUENCE
)
{
if
(
TII
->
get
(
MI
.
getOpcode
(
)
)
.
TSFlags
&
R600_InstFlag
::
TEX_INST
)
{
unsigned
Reg
=
MI
.
getOperand
(
1
)
.
getReg
(
)
;
for
(
MachineRegisterInfo
::
def_instr_iterator
It
=
MRI
->
def_instr_begin
(
Reg
)
,
E
=
MRI
->
def_instr_end
(
)
;
It
!=
E
;
++
It
)
{
RemoveMI
(
&
(
*
It
)
)
;
}
}
continue
;
}
RegSeqInfo
RSI
(
*
MRI
,
&
MI
)
;
unsigned
Reg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
if
(
!
areAllUsesSwizzeable
(
Reg
)
)
continue
;
LLVM_DEBUG
(
{
dbgs
(
)
<<
"Trying to optimize "
;
MI
.
dump
(
)
;
}
)
;
RegSeqInfo
CandidateRSI
;
std
::
vector
<
std
::
pair
<
unsigned
,
unsigned
>>
RemapChan
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Using common slots...\n"
;
)
;
if
(
tryMergeUsingCommonSlot
(
RSI
,
CandidateRSI
,
RemapChan
)
)
{
RemoveMI
(
CandidateRSI
.
Instr
)
;
MII
=
RebuildVector
(
&
RSI
,
&
CandidateRSI
,
RemapChan
)
;
trackRSI
(
RSI
)
;
continue
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Using free slots...\n"
;
)
;
RemapChan
.
clear
(
)
;
if
(
tryMergeUsingFreeSlot
(
RSI
,
CandidateRSI
,
RemapChan
)
)
{
RemoveMI
(
CandidateRSI
.
Instr
)
;
MII
=
RebuildVector
(
&
RSI
,
&
CandidateRSI
,
RemapChan
)
;
trackRSI
(
RSI
)
;
continue
;
}
trackRSI
(
RSI
)
;
}
}
</s>

runOnMachineFunction - Emit the function body .

AMDGPU
R600
R600
R600
R600::REG_SEQUENCE
R600_InstFlag::TEX_INST
1
SI
0
"Trying to optimize "
SI
"Using common slots...\n"
SI
SI
SI
SI
SI
SI
SI
"Using free slots...\n"
SI
SI
SI
SI
SI
SI
SI
SI
SI


<s> rtx mips_loongson_ext2_prefetch_cookie ( rtx write , rtx ) { if ( INTVAL ( write ) == 1 ) return GEN_INT ( INTVAL ( write ) ) ; if ( INTVAL ( write ) == 0 ) return GEN_INT ( INTVAL ( write ) ) ; gcc_unreachable ( ) ; } </s>

Loongson EXT2 only implements pref hint=0 ( prefetch for load ) and hint=1 ( prefetch for store ) , other hint just scale to hint = 0 and hint = 1 .


<s> bool RISCVTTIImpl :: isLoweredToCall ( const Function * F ) { if ( F -> getName ( ) . startswith ( "llvm.riscv.pulp" ) ) return false ; return BaseT :: isLoweredToCall ( F ) ; } </s>

Test whether calls to a function lower to actual program function calls .


<s> void altivec_expand_vec_perm_le ( rtx operands [ 4 ] ) { rtx notx , iorx , unspec ; rtx target = operands [ 0 ] ; rtx op0 = operands [ 1 ] ; rtx op1 = operands [ 2 ] ; rtx sel = operands [ 3 ] ; rtx tmp = target ; rtx norreg = gen_reg_rtx ( V16QImode ) ; machine_mode mode = GET_MODE ( target ) ; if ( ! REG_P ( op0 ) ) op0 = force_reg ( mode , op0 ) ; if ( ! REG_P ( op1 ) ) op1 = force_reg ( mode , op1 ) ; if ( ! REG_P ( sel ) ) sel = force_reg ( V16QImode , sel ) ; if ( ! REG_P ( target ) ) tmp = gen_reg_rtx ( mode ) ; if ( TARGET_P9_VECTOR ) { unspec = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , op0 , op1 , sel ) , UNSPEC_VPERMR ) ; } else { notx = gen_rtx_NOT ( V16QImode , sel ) ; iorx = ( TARGET_P8_VECTOR ? gen_rtx_IOR ( V16QImode , notx , notx ) : gen_rtx_AND ( V16QImode , notx , notx ) ) ; emit_insn ( gen_rtx_SET ( norreg , iorx ) ) ; unspec = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , op1 , op0 , norreg ) , UNSPEC_VPERM ) ; } if ( ! REG_P ( target ) ) { emit_move_insn ( tmp , unspec ) ; unspec = tmp ; } emit_move_insn ( target , unspec ) ; } </s>

Similarly to altivec_expand_vec_perm_const_le , we must adjust the permute control vector . But here it 's not a constant , so we must generate a vector NAND or NOR to do the adjustment .


<s> static bool nios2_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { if ( to == STACK_POINTER_REGNUM ) return ! frame_pointer_needed ; return true ; } </s>


Hook to validate the current # pragma GCC target and set the arch custom mode state . If ARGS is NULL , then POP_TARGET is used to reset the options .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"SIC Del Useless jump"
;
}
</s>


<s>
SDValue
SNESTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
auto
CCFunction
=
CCAssignFnForReturn
(
CallConv
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
CCFunction
)
;
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
unsigned
e
=
RVLocs
.
size
(
)
;
if
(
e
>
1
)
{
std
::
reverse
(
RVLocs
.
begin
(
)
,
RVLocs
.
end
(
)
)
;
}
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
if
(
MF
.
getFunction
(
)
->
getAttributes
(
)
.
hasAttribute
(
AttributeList
::
FunctionIndex
,
Attribute
::
Naked
)
)
{
return
Chain
;
}
unsigned
RetOpc
=
SNESISD
::
RET_FLAG
;
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
{
RetOps
.
push_back
(
Flag
)
;
}
return
DAG
.
getNode
(
RetOpc
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> unsigned AMDGPUTargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { switch ( Op . getOpcode ( ) ) { case AMDGPUISD :: BFE_I32 : { ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ; if ( ! Width ) return 1 ; unsigned SignBits = 32 - Width -> getZExtValue ( ) + 1 ; if ( ! isNullConstant ( Op . getOperand ( 1 ) ) ) return SignBits ; unsigned Op0SignBits = DAG . ComputeNumSignBits ( Op . getOperand ( 0 ) , Depth + 1 ) ; return std :: max ( SignBits , Op0SignBits ) ; } case AMDGPUISD :: BFE_U32 : { ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ; return Width ? 32 - ( Width -> getZExtValue ( ) & 0x1f ) : 1 ; } case AMDGPUISD :: CARRY : case AMDGPUISD :: BORROW : return 31 ; case AMDGPUISD :: FP_TO_FP16 : case AMDGPUISD :: FP16_ZEXT : return 16 ; default : return 1 ; } } </s>

Determine the number of bits in the operation that are sign bits .


<s> SDValue NVPTXTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { CodeGenOpt :: Level OptLevel = getTargetMachine ( ) . getOptLevel ( ) ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : case ISD :: FADD : return PerformADDCombine ( N , DCI , STI , OptLevel ) ; case ISD :: MUL : return PerformMULCombine ( N , DCI , OptLevel ) ; case ISD :: SHL : return PerformSHLCombine ( N , DCI , OptLevel ) ; case ISD :: AND : return PerformANDCombine ( N , DCI ) ; case ISD :: UREM : case ISD :: SREM : return PerformREMCombine ( N , DCI , OptLevel ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

NVPTX NVPTX ISD::ADD ISD::FADD ISD::MUL ISD::SHL ISD::AND ISD::UREM ISD::SREM


<s> bool GCNTTIImpl :: rewriteIntrinsicWithAddressSpace ( IntrinsicInst * II , Value * OldV , Value * NewV ) const { auto IntrID = II -> getIntrinsicID ( ) ; switch ( IntrID ) { case Intrinsic :: amdgcn_atomic_inc : case Intrinsic :: amdgcn_atomic_dec : case Intrinsic :: amdgcn_ds_fadd : case Intrinsic :: amdgcn_ds_fmin : case Intrinsic :: amdgcn_ds_fmax : { const ConstantInt * IsVolatile = cast < ConstantInt > ( II -> getArgOperand ( 4 ) ) ; if ( ! IsVolatile -> isZero ( ) ) return false ; Module * M = II -> getParent ( ) -> getParent ( ) -> getParent ( ) ; Type * DestTy = II -> getType ( ) ; Type * SrcTy = NewV -> getType ( ) ; Function * NewDecl = Intrinsic :: getDeclaration ( M , II -> getIntrinsicID ( ) , { DestTy , SrcTy } ) ; II -> setArgOperand ( 0 , NewV ) ; II -> setCalledFunction ( NewDecl ) ; return true ; } case Intrinsic :: amdgcn_is_shared : case Intrinsic :: amdgcn_is_private : { unsigned TrueAS = IntrID == Intrinsic :: amdgcn_is_shared ? AMDGPUAS :: LOCAL_ADDRESS : AMDGPUAS :: PRIVATE_ADDRESS ; unsigned NewAS = NewV -> getType ( ) -> getPointerAddressSpace ( ) ; LLVMContext & Ctx = NewV -> getType ( ) -> getContext ( ) ; ConstantInt * NewVal = ( TrueAS == NewAS ) ? ConstantInt :: getTrue ( Ctx ) : ConstantInt :: getFalse ( Ctx ) ; II -> replaceAllUsesWith ( NewVal ) ; II -> eraseFromParent ( ) ; return true ; } default : return false ; } } </s>

Rewrite intrinsic call II such that OldV will be replaced with NewV , which has a different address space .


<s> bool nios2_validate_compare ( machine_mode mode , rtx * cmp , rtx * op1 , rtx * op2 ) { enum rtx_code code = GET_CODE ( * cmp ) ; enum rtx_code alt_code ; rtx alt_op2 ; if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return nios2_validate_fpu_compare ( mode , cmp , op1 , op2 , true ) ; if ( CONST_INT_P ( * op2 ) && * op2 != const0_rtx ) { nios2_alternate_compare_const ( code , * op2 , & alt_code , & alt_op2 , mode ) ; if ( alt_op2 == const0_rtx ) { code = alt_code ; * op2 = alt_op2 ; goto check_rebuild_cmp ; } if ( nios2_valid_compare_const_p ( code , * op2 ) ) return true ; else if ( nios2_valid_compare_const_p ( alt_code , alt_op2 ) ) { code = alt_code ; * op2 = alt_op2 ; goto rebuild_cmp ; } if ( ! nios2_simple_const_p ( * op2 ) && nios2_simple_const_p ( alt_op2 ) ) { code = alt_code ; * op2 = alt_op2 ; } * op2 = force_reg ( mode , * op2 ) ; } else if ( ! reg_or_0_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; check_rebuild_cmp : if ( code == GT || code == GTU || code == LE || code == LEU ) { rtx t = * op1 ; * op1 = * op2 ; * op2 = t ; code = swap_condition ( code ) ; } rebuild_cmp : * cmp = gen_rtx_fmt_ee ( code , mode , * op1 , * op2 ) ; return true ; } </s>

Checks and modifies the comparison in * CMP , * OP1 , and * OP2 into valid nios2 supported form . Returns true if success .


<s> bool GBZ80SectionData :: get ( StringRef Specifier , GBZ80SectionData & Data ) { Data . Type = ST_NONE ; Data . Address = 0 ; Data . Bank = ~ 0U ; Data . Alignment = 1 ; return false ; } </s>

Get the generated Value for a given VPValue and given Part and Lane .


<s> void MipsPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; addPass ( createAtomicExpandPass ( ) ) ; if ( getMipsSubtarget ( ) . os16 ( ) ) addPass ( createMipsOs16Pass ( ) ) ; if ( getMipsSubtarget ( ) . inMips16HardFloat ( ) ) addPass ( createMips16HardFloatPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s>
SDValue
AMDGPUTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
Op
.
getNode
(
)
->
dump
(
)
;
assert
(
0
&&
"Custom lowering code for this"
"instruction is not implemented yet!"
)
;
break
;
case
ISD
::
SDIV
:
return
LowerSDIV
(
Op
,
DAG
)
;
case
ISD
::
SREM
:
return
LowerSREM
(
Op
,
DAG
)
;
case
ISD
::
SIGN_EXTEND_INREG
:
return
LowerSIGN_EXTEND_INREG
(
Op
,
DAG
)
;
case
ISD
::
BRCOND
:
return
LowerBRCOND
(
Op
,
DAG
)
;
case
ISD
::
CONCAT_VECTORS
:
return
LowerCONCAT_VECTORS
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_SUBVECTOR
:
return
LowerEXTRACT_SUBVECTOR
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
STORE
:
return
LowerSTORE
(
Op
,
DAG
)
;
case
ISD
::
UDIVREM
:
return
LowerUDIVREM
(
Op
,
DAG
)
;
case
ISD
::
UINT_TO_FP
:
return
LowerUINT_TO_FP
(
Op
,
DAG
)
;
}
return
Op
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> static int try_constant_tricks ( long value , int * x , int * y ) { int i ; unsigned bit , shf , rot ; if ( const_ok_for_mcore ( value ) ) return 1 ; if ( TARGET_HARDLIT ) { if ( const_ok_for_mcore ( ~ value ) ) { * x = ~ value ; return 2 ; } for ( i = 1 ; i <= 32 ; i ++ ) { if ( const_ok_for_mcore ( value - i ) ) { * x = value - i ; * y = i ; return 3 ; } if ( const_ok_for_mcore ( value + i ) ) { * x = value + i ; * y = i ; return 4 ; } } bit = 0x80000000L ; for ( i = 0 ; i <= 31 ; i ++ ) { if ( const_ok_for_mcore ( i - value ) ) { * x = i - value ; * y = i ; return 5 ; } if ( const_ok_for_mcore ( value & ~ bit ) ) { * y = bit ; * x = value & ~ bit ; return 6 ; } if ( const_ok_for_mcore ( value | bit ) ) { * y = ~ bit ; * x = value | bit ; return 7 ; } bit >>= 1 ; } shf = value ; rot = value ; for ( i = 1 ; i < 31 ; i ++ ) { int c ; c = rot << 31 ; rot >>= 1 ; rot &= 0x7FFFFFFF ; rot |= c ; if ( const_ok_for_mcore ( rot ) ) { * y = i ; * x = rot ; return 8 ; } if ( shf & 1 ) shf = 0 ; shf >>= 1 ; if ( shf != 0 && const_ok_for_mcore ( shf ) ) { * y = i ; * x = shf ; return 9 ; } } if ( ( value % 3 ) == 0 && const_ok_for_mcore ( value / 3 ) ) { * x = value / 3 ; return 10 ; } if ( ( value % 5 ) == 0 && const_ok_for_mcore ( value / 5 ) ) { * x = value / 5 ; return 11 ; } } return 0 ; } </s>

Try tricks to load a constant inline and return the trick number if success ( 0 is non-inlinable ) . 0 : not inlinable 1 : single instruction ( do the usual thing ) 2 : single insn followed by a 'not ' 3 : single insn followed by a subi 4 : single insn followed by an addi 5 : single insn followed by rsubi 6 : single insn followed by bseti 7 : single insn followed by bclri 8 : single insn followed by rotli 9 : single insn followed by lsli 10 : single insn followed by ixh 11 : single insn followed by ixw .


<s> void MetadataStreamer :: end ( ) { std :: string HSAMetadataString ; if ( toString ( HSAMetadata , HSAMetadataString ) ) return ; if ( DumpHSAMetadata ) dump ( HSAMetadataString ) ; if ( VerifyHSAMetadata ) verify ( HSAMetadataString ) ; } </s>

Get a const_iterator to the end of the symbol table .


<s> void SIInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { assert ( DestReg != AMDGPU :: SCC && SrcReg != AMDGPU :: SCC ) ; if ( AMDGPU :: SReg_64RegClass . contains ( DestReg ) ) { assert ( AMDGPU :: SReg_64RegClass . contains ( SrcReg ) ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: S_MOV_B64 ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else if ( AMDGPU :: VReg_32RegClass . contains ( DestReg ) ) { assert ( AMDGPU :: VReg_32RegClass . contains ( SrcReg ) || AMDGPU :: SReg_32RegClass . contains ( SrcReg ) ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: V_MOV_B32_e32 ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else { assert ( AMDGPU :: SReg_32RegClass . contains ( DestReg ) ) ; assert ( AMDGPU :: SReg_32RegClass . contains ( SrcReg ) ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: S_MOV_B32 ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } } </s>


<s>
void
AArch64InstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
O
,
StringRef
Annot
)
{
if
(
MI
->
getOpcode
(
)
==
AArch64
::
TLSDESCCALL
)
{
O
<<
"\t.tlsdesccall "
<<
*
MI
->
getOperand
(
0
)
.
getExpr
(
)
;
}
else
if
(
!
printAliasInstr
(
MI
,
O
)
)
printInstruction
(
MI
,
O
)
;
printAnnotation
(
O
,
Annot
)
;
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s> void emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const override { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool PatmosSinglePathInfo :: isEnabled ( const MachineFunction & MF ) { return PatmosSinglePathInfo :: isEnabled ( MF . getFunction ( ) ) ; } </s>


<s>
char
*
cr16_prepare_push_pop_string
(
int
push_or_pop
)
{
static
char
one_inst_str
[
50
]
;
int
i
,
start_reg
;
int
word_cnt
;
int
print_ra
;
char
*
return_str
;
char
*
temp_str
;
return_str
=
(
char
*
)
xmalloc
(
160
)
;
temp_str
=
(
char
*
)
xmalloc
(
160
)
;
memset
(
return_str
,
0
,
3
)
;
i
=
0
;
while
(
i
<=
current_frame_info
.
last_reg_to_save
)
{
one_inst_str
[
0
]
=
0
;
word_cnt
=
0
;
start_reg
=
i
;
print_ra
=
0
;
while
(
(
word_cnt
<
MAX_COUNT
)
&&
(
i
<=
current_frame_info
.
last_reg_to_save
)
)
{
if
(
!
current_frame_info
.
save_regs
[
i
]
)
{
++
i
;
break
;
}
if
(
i
==
RETURN_ADDRESS_REGNUM
)
print_ra
=
1
;
else
{
if
(
(
word_cnt
+
(
(
i
<
CR16_FIRST_DWORD_REGISTER
)
1
:
2
)
)
>=
MAX_COUNT
)
break
;
word_cnt
+=
(
(
i
<
CR16_FIRST_DWORD_REGISTER
)
1
:
2
)
;
}
++
i
;
}
if
(
(
word_cnt
==
0
)
&&
(
print_ra
==
0
)
)
continue
;
if
(
word_cnt
>
0
)
{
sprintf
(
one_inst_str
,
"$%d, %s"
,
word_cnt
,
reg_names
[
start_reg
]
)
;
if
(
print_ra
)
strcat
(
one_inst_str
,
", ra"
)
;
}
else
strcat
(
one_inst_str
,
"ra"
)
;
if
(
push_or_pop
==
1
)
{
if
(
print_ra
&&
!
cr16_interrupt_function_p
(
)
&&
!
crtl
->
calls_eh_return
)
strcpy
(
temp_str
,
"\n\tpopret\t"
)
;
else
strcpy
(
temp_str
,
"\n\tpop\t"
)
;
strcat
(
temp_str
,
one_inst_str
)
;
strcat
(
return_str
,
temp_str
)
;
}
else
{
strcpy
(
temp_str
,
"\n\tpush\t"
)
;
strcat
(
temp_str
,
one_inst_str
)
;
strcat
(
temp_str
,
return_str
)
;
strcpy
(
return_str
,
temp_str
)
;
}
}
if
(
push_or_pop
==
1
)
{
if
(
cr16_interrupt_function_p
(
)
)
strcat
(
return_str
,
"\n\tretx\n"
)
;
else
if
(
crtl
->
calls_eh_return
)
{
strcat
(
return_str
,
"\n\taddd\t (r5, r4), (sp)\t\n"
)
;
strcat
(
return_str
,
"\n\tjump\t (ra)\n"
)
;
strcpy
(
temp_str
,
"\n\tsubd\t (r5, r4), (sp)\t\n"
)
;
strcat
(
temp_str
,
return_str
)
;
strcpy
(
return_str
,
temp_str
)
;
}
else
if
(
!
FUNC_IS_NORETURN_P
(
current_function_decl
)
&&
!
(
current_frame_info
.
save_regs
[
RETURN_ADDRESS_REGNUM
]
)
)
strcat
(
return_str
,
"\n\tjump\t (ra)\n"
)
;
}
return_str
+=
2
;
return
return_str
;
}
</s>

Called from cr16.md . The return value depends on the parameter push_or_pop : When push_or_pop is zero - > string for push instructions of prologue . When push_or_pop is nonzero - > string for pop/popret/retx in epilogue . Relies on the assumptions : 1 . RA is the last register to be saved . 2 . The maximal value of the counter is MAX_COUNT .


<s> bool M680x0InstrInfo :: ExpandCCR ( MachineInstrBuilder & MIB , bool isToCCR ) const { if ( isToCCR ) { MIB -> setDesc ( get ( M680x0 :: MOV16cd ) ) ; } else { MIB -> setDesc ( get ( M680x0 :: MOV16dc ) ) ; } auto & Opd = MIB -> getOperand ( 1 ) ; Opd . setReg ( getRegisterInfo ( ) . getMatchingSuperReg ( Opd . getReg ( ) , M680x0 :: MxSubRegIndex8Lo , & M680x0 :: DR16RegClass ) ) ; return true ; } </s>


<s> static bool ix86_use_mask_cmp_p ( machine_mode mode , machine_mode cmp_mode , rtx op_true , rtx op_false ) { int vector_size = GET_MODE_SIZE ( mode ) ; if ( cmp_mode == HFmode ) return true ; else if ( vector_size < 16 ) return false ; else if ( vector_size == 64 ) return true ; else if ( GET_MODE_INNER ( cmp_mode ) == HFmode ) return true ; gcc_assert ( ! op_true == ! op_false ) ; if ( ! op_true || ! ix86_valid_mask_cmp_mode ( cmp_mode ) ) return false ; if ( op_false == CONST0_RTX ( mode ) || op_true == CONST0_RTX ( mode ) || ( INTEGRAL_MODE_P ( mode ) && ( op_true == CONSTM1_RTX ( mode ) || op_false == CONSTM1_RTX ( mode ) ) ) ) return false ; return true ; } </s>

Return true if integer mask comparison should be used .


<s> void arc_expand_atomic_op ( enum rtx_code code , rtx mem , rtx val , rtx orig_before , rtx orig_after , rtx model_rtx ) { enum memmodel model = ( enum memmodel ) INTVAL ( model_rtx ) ; machine_mode mode = GET_MODE ( mem ) ; rtx label , x , cond ; rtx before = orig_before , after = orig_after ; gcc_assert ( mode == SImode ) ; arc_pre_atomic_barrier ( model ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; label = gen_rtx_LABEL_REF ( VOIDmode , label ) ; if ( before == NULL_RTX ) before = gen_reg_rtx ( mode ) ; if ( after == NULL_RTX ) after = gen_reg_rtx ( mode ) ; emit_insn ( gen_arc_load_exclusivesi ( before , mem ) ) ; switch ( code ) { case NOT : x = gen_rtx_AND ( mode , before , val ) ; emit_insn ( gen_rtx_SET ( after , x ) ) ; x = gen_rtx_NOT ( mode , after ) ; emit_insn ( gen_rtx_SET ( after , x ) ) ; break ; case MINUS : if ( CONST_INT_P ( val ) ) { val = GEN_INT ( - INTVAL ( val ) ) ; code = PLUS ; } default : x = gen_rtx_fmt_ee ( code , mode , before , val ) ; emit_insn ( gen_rtx_SET ( after , x ) ) ; break ; } emit_insn ( gen_arc_store_exclusivesi ( mem , after ) ) ; cond = gen_rtx_REG ( CC_Zmode , CC_REG ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , label , pc_rtx ) ; emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; arc_post_atomic_barrier ( model ) ; } </s>

Expand an atomic fetch-and-operate pattern . CODE is the binary operation to perform . MEM is the memory on which to operate . VAL is the second operand of the binary operator . BEFORE and AFTER are optional locations to return the value of MEM either before of after the operation . MODEL_RTX is a CONST_INT containing the memory model to use .


<s> void M680x0InstrInfo :: AddZExt ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned Reg , MVT From , MVT To ) const { unsigned Mask , And ; if ( From == MVT :: i8 ) { Mask = 0xFF ; } else { Mask = 0xFFFF ; } if ( To == MVT :: i16 ) { And = M680x0 :: AND16di ; } else { And = M680x0 :: AND32di ; } BuildMI ( MBB , I , DL , get ( And ) , Reg ) . addReg ( Reg ) . addImm ( Mask ) ; } </s>


<s> static bool ix86_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_SSE && VALID_SSE_REG_MODE ( mode ) ) return true ; if ( TARGET_SSE2 && VALID_SSE2_REG_MODE ( mode ) ) return true ; if ( TARGET_AVX && VALID_AVX256_REG_MODE ( mode ) ) return true ; if ( TARGET_AVX512F && VALID_AVX512F_REG_MODE ( mode ) ) return true ; if ( ( TARGET_MMX || TARGET_MMX_WITH_SSE ) && VALID_MMX_REG_MODE ( mode ) ) return true ; if ( ( TARGET_3DNOW || TARGET_MMX_WITH_SSE ) && VALID_MMX_REG_MODE_3DNOW ( mode ) ) return true ; return false ; } </s>

Implements target hook vector_mode_supported_p .


<s> bool PPCLoopPreIncPrep :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; auto * DTWP = getAnalysisIfAvailable < DominatorTreeWrapperPass > ( ) ; DT = DTWP ? & DTWP -> getDomTree ( ) : nullptr ; PreserveLCSSA = mustPreserveAnalysisID ( LCSSAID ) ; ST = TM ? TM -> getSubtargetImpl ( F ) : nullptr ; bool MadeChange = false ; for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L = df_begin ( * I ) , LE = df_end ( * I ) ; L != LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ; return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool SIInstrInfo :: moveFlatAddrToVGPR ( MachineInstr & Inst ) const { unsigned Opc = Inst . getOpcode ( ) ; int OldSAddrIdx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: saddr ) ; if ( OldSAddrIdx < 0 ) return false ; assert ( isSegmentSpecificFLAT ( Inst ) ) ; int NewOpc = AMDGPU :: getGlobalVaddrOp ( Opc ) ; if ( NewOpc < 0 ) NewOpc = AMDGPU :: getFlatScratchInstSVfromSS ( Opc ) ; if ( NewOpc < 0 ) return false ; MachineRegisterInfo & MRI = Inst . getMF ( ) -> getRegInfo ( ) ; MachineOperand & SAddr = Inst . getOperand ( OldSAddrIdx ) ; if ( RI . isSGPRReg ( MRI , SAddr . getReg ( ) ) ) return false ; int NewVAddrIdx = AMDGPU :: getNamedOperandIdx ( NewOpc , AMDGPU :: OpName :: vaddr ) ; if ( NewVAddrIdx < 0 ) return false ; int OldVAddrIdx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: vaddr ) ; MachineInstr * VAddrDef = nullptr ; if ( OldVAddrIdx >= 0 ) { MachineOperand & VAddr = Inst . getOperand ( OldVAddrIdx ) ; VAddrDef = MRI . getUniqueVRegDef ( VAddr . getReg ( ) ) ; if ( ! VAddrDef || VAddrDef -> getOpcode ( ) != AMDGPU :: V_MOV_B32_e32 || ! VAddrDef -> getOperand ( 1 ) . isImm ( ) || VAddrDef -> getOperand ( 1 ) . getImm ( ) != 0 ) return false ; } const MCInstrDesc & NewDesc = get ( NewOpc ) ; Inst . setDesc ( NewDesc ) ; if ( OldVAddrIdx == NewVAddrIdx ) { MachineOperand & NewVAddr = Inst . getOperand ( NewVAddrIdx ) ; MRI . removeRegOperandFromUseList ( & NewVAddr ) ; MRI . moveOperands ( & NewVAddr , & SAddr , 1 ) ; Inst . removeOperand ( OldSAddrIdx ) ; MRI . removeRegOperandFromUseList ( & NewVAddr ) ; MRI . addRegOperandToUseList ( & NewVAddr ) ; } else { assert ( OldSAddrIdx == NewVAddrIdx ) ; if ( OldVAddrIdx >= 0 ) { int NewVDstIn = AMDGPU :: getNamedOperandIdx ( NewOpc , AMDGPU :: OpName :: vdst_in ) ; if ( NewVDstIn != - 1 ) { int OldVDstIn = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: vdst_in ) ; Inst . untieRegOperand ( OldVDstIn ) ; } Inst . removeOperand ( OldVAddrIdx ) ; if ( NewVDstIn != - 1 ) { int NewVDst = AMDGPU :: getNamedOperandIdx ( NewOpc , AMDGPU :: OpName :: vdst ) ; Inst . tieOperands ( NewVDst , NewVDstIn ) ; } } } if ( VAddrDef && MRI . use_nodbg_empty ( VAddrDef -> getOperand ( 0 ) . getReg ( ) ) ) VAddrDef -> eraseFromParent ( ) ; return true ; } </s>

Change SADDR form of a FLAT Inst to its VADDR form if saddr operand was moved to VGPR .


"not generating patch area, nops not supported"


<s> static bool rs6000_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE ( mode ) ) return true ; else if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) && ! FLOAT128_IEEE_P ( mode ) ) return true ; else return false ; } </s>

Target hook for vector_mode_supported_p .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Patmos Call Graph Builder"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
static
void
nios2_dump_frame_layout
(
FILE
*
file
)
{
fprintf
(
file
,
"\t%s Current Frame Info\n"
,
ASM_COMMENT_START
)
;
fprintf
(
file
,
"\t%s total_size = %d\n"
,
ASM_COMMENT_START
,
cfun
->
machine
->
total_size
)
;
fprintf
(
file
,
"\t%s var_size = %d\n"
,
ASM_COMMENT_START
,
cfun
->
machine
->
var_size
)
;
fprintf
(
file
,
"\t%s args_size = %d\n"
,
ASM_COMMENT_START
,
cfun
->
machine
->
args_size
)
;
fprintf
(
file
,
"\t%s save_reg_size = %d\n"
,
ASM_COMMENT_START
,
cfun
->
machine
->
save_reg_size
)
;
fprintf
(
file
,
"\t%s initialized = %d\n"
,
ASM_COMMENT_START
,
cfun
->
machine
->
initialized
)
;
fprintf
(
file
,
"\t%s save_regs_offset = %d\n"
,
ASM_COMMENT_START
,
cfun
->
machine
->
save_regs_offset
)
;
fprintf
(
file
,
"\t%s is_leaf = %d\n"
,
ASM_COMMENT_START
,
crtl
->
is_leaf
)
;
fprintf
(
file
,
"\t%s frame_pointer_needed = %d\n"
,
ASM_COMMENT_START
,
frame_pointer_needed
)
;
fprintf
(
file
,
"\t%s pretend_args_size = %d\n"
,
ASM_COMMENT_START
,
crtl
->
args
.
pretend_args_size
)
;
}
</s>

nios2
"\t%s Current Frame Info\n"
"\t%s total_size = %d\n"
"\t%s var_size = %d\n"
"\t%s args_size = %d\n"
"\t%s save_reg_size = %d\n"
"\t%s initialized = %d\n"
"\t%s save_regs_offset = %d\n"
"\t%s is_leaf = %d\n"
"\t%s frame_pointer_needed = %d\n"
"\t%s pretend_args_size = %d\n"


<s> const TargetRegisterClass * MipsRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { MipsABIInfo ABI = MF . getSubtarget < MipsSubtarget > ( ) . getABI ( ) ; return ABI . ArePtrs64bit ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .

Mips Mips Mips Mips Mips::GPR64RegClass Mips::GPR32RegClass


<s> void BitcodeWriter :: copyStrtab ( StringRef Strtab ) { writeBlob ( bitc :: STRTAB_BLOCK_ID , bitc :: STRTAB_BLOB , Strtab ) ; WroteStrtab = true ; } </s>

Copy the string table for another module into this bitcode file .


<s> bool Thumb2SizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { const TargetMachine & TM = MF . getTarget ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( TM . getInstrInfo ( ) ) ; STI = & TM . getSubtarget < ARMSubtarget > ( ) ; AttributeSet FnAttrs = MF . getFunction ( ) -> getAttributes ( ) ; OptimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; MinimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; ReversePostOrderTraversal < MachineFunction * > RPOT ( & MF ) ; bool Modified = false ; for ( ReversePostOrderTraversal < MachineFunction * > :: rpo_iterator I = RPOT . begin ( ) , E = RPOT . end ( ) ; I != E ; ++ I ) Modified |= ReduceMBB ( * * I ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool NVPTXImageOptimizer :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; bool Changed = false ; InstrToDelete . clear ( ) ; for ( BasicBlock & BB : F ) { for ( Instruction & Instr : BB ) { if ( CallInst * CI = dyn_cast < CallInst > ( & Instr ) ) { Function * CalledF = CI -> getCalledFunction ( ) ; if ( CalledF && CalledF -> isIntrinsic ( ) ) { switch ( CalledF -> getIntrinsicID ( ) ) { default : break ; case Intrinsic :: nvvm_istypep_sampler : Changed |= replaceIsTypePSampler ( Instr ) ; break ; case Intrinsic :: nvvm_istypep_surface : Changed |= replaceIsTypePSurface ( Instr ) ; break ; case Intrinsic :: nvvm_istypep_texture : Changed |= replaceIsTypePTexture ( Instr ) ; break ; } } } } } for ( Instruction * I : InstrToDelete ) I -> eraseFromParent ( ) ; return Changed ; } </s>


<s> int flags_in_68881 ( void ) { return cc_status . flags & CC_IN_68881 ; } </s>

Return nonzero if flags are currently in the 68881 flag register .


<s>
unsigned
FISCMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
CTX
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
assert
(
MO
.
isExpr
(
)
&&
"unknown operand kind in printOperand"
)
;
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
MCExpr
::
ExprKind
Kind
=
Expr
->
getKind
(
)
;
if
(
Kind
==
MCExpr
::
Binary
)
{
Expr
=
static_cast
<
const
MCBinaryExpr
*
>
(
Expr
)
->
getLHS
(
)
;
Kind
=
Expr
->
getKind
(
)
;
}
if
(
Kind
==
MCExpr
::
Constant
)
return
cast
<
MCConstantExpr
>
(
Expr
)
->
getValue
(
)
;
assert
(
Kind
==
MCExpr
::
SymbolRef
)
;
unsigned
FixupKind
;
unsigned
VKind
=
cast
<
MCSymbolRefExpr
>
(
Expr
)
->
getKind
(
)
;
switch
(
VKind
)
{
case
MCSymbolRefExpr
::
VK_None
:
return
0
;
default
:
{
std
::
string
msg
=
"Unknown fixup kind! ("
+
std
::
to_string
(
VKind
)
+
")"
;
llvm_unreachable
(
msg
.
c_str
(
)
)
;
}
case
MCSymbolRefExpr
::
VK_FISC_Q1
:
FixupKind
=
FISC
::
fixup_fisc_mov_q1_pcrel
;
break
;
case
MCSymbolRefExpr
::
VK_FISC_Q2
:
FixupKind
=
FISC
::
fixup_fisc_mov_q2_pcrel
;
break
;
case
MCSymbolRefExpr
::
VK_FISC_Q3
:
FixupKind
=
FISC
::
fixup_fisc_mov_q3_pcrel
;
break
;
case
MCSymbolRefExpr
::
VK_FISC_Q4
:
FixupKind
=
FISC
::
fixup_fisc_mov_q4_pcrel
;
break
;
case
MCSymbolRefExpr
::
VK_FISC_CALL26
:
FixupKind
=
FISC
::
fixup_fisc_call26_pcrel
;
break
;
case
MCSymbolRefExpr
::
VK_FISC_CALL19
:
FixupKind
=
FISC
::
fixup_fisc_call19_pcrel
;
break
;
case
MCSymbolRefExpr
::
VK_FISC_9BIT
:
FixupKind
=
FISC
::
fixup_fisc_9bit_address
;
break
;
case
MCSymbolRefExpr
::
VK_FISC_6BIT
:
FixupKind
=
FISC
::
fixup_fisc_6bit_shamt
;
break
;
case
MCSymbolRefExpr
::
VK_FISC_12BIT
:
FixupKind
=
FISC
::
fixup_fisc_12bit_imm
;
break
;
case
MCSymbolRefExpr
::
VK_FISC_MOVRZ
:
FixupKind
=
FISC
::
fixup_fisc_movrz_pcrel
;
break
;
}
Fixups
.
push_back
(
MCFixup
::
create
(
0
,
MO
.
getExpr
(
)
,
MCFixupKind
(
FixupKind
)
)
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> static inline bool rs6000_builtin_type_compatible ( tree t , int id ) { tree builtin_type ; builtin_type = rs6000_builtin_type ( id ) ; if ( t == error_mark_node ) return false ; if ( INTEGRAL_TYPE_P ( t ) && INTEGRAL_TYPE_P ( builtin_type ) ) return true ; else return lang_hooks . types_compatible_p ( t , builtin_type ) ; } </s>

Return true iff ARGTYPE can be compatibly passed as PARMTYPE .


<s> bool doInitialization ( Module & M ) override { FDivFunc = findFunction ( M , "__fdiv" ) ; FRemFunc = findFunction ( M , "__frem" ) ; UDivFunc = findFunction ( M , "__udiv" ) ; URemFunc = findFunction ( M , "__urem" ) ; SDivFunc = findFunction ( M , "__sdiv" ) ; SRemFunc = findFunction ( M , "__srem" ) ; if ( FDivFunc ) FDivFunc -> setUnnamedAddr ( GlobalValue :: UnnamedAddr :: Local ) ; if ( FRemFunc ) FRemFunc -> setUnnamedAddr ( GlobalValue :: UnnamedAddr :: Local ) ; if ( UDivFunc ) UDivFunc -> setUnnamedAddr ( GlobalValue :: UnnamedAddr :: Local ) ; if ( URemFunc ) URemFunc -> setUnnamedAddr ( GlobalValue :: UnnamedAddr :: Local ) ; if ( SDivFunc ) SDivFunc -> setUnnamedAddr ( GlobalValue :: UnnamedAddr :: Local ) ; if ( SRemFunc ) SRemFunc -> setUnnamedAddr ( GlobalValue :: UnnamedAddr :: Local ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Lanai SET_FLAG ALU combiner pass"
;
}
</s>

Lanai
"Lanai SET_FLAG ALU combiner pass"


<s> void X86PassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & LiveRangeShrinkID ) ; addPass ( createX86FixupSetCC ( ) ) ; addPass ( createX86OptimizeLEAs ( ) ) ; addPass ( createX86CallFrameOptimization ( ) ) ; addPass ( createX86AvoidStoreForwardingBlocks ( ) ) ; } addPass ( createX86FlagsCopyLoweringPass ( ) ) ; addPass ( createX86WinAllocaExpander ( ) ) ; addPass ( createSandBoxingPreRegallocPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static int dispatch_function_versions ( tree dispatch_decl , void * fndecls_p , basic_block * empty_bb ) { tree default_decl ; gimple * ifunc_cpu_init_stmt ; gimple_seq gseq ; int ix ; tree ele ; vec < tree > * fndecls ; unsigned int num_versions = 0 ; unsigned int actual_versions = 0 ; unsigned int i ; struct _function_version_info { tree version_decl ; tree predicate_chain ; unsigned int dispatch_priority ; } * function_version_info ; gcc_assert ( dispatch_decl != NULL && fndecls_p != NULL && empty_bb != NULL ) ; fndecls = static_cast < vec < tree > * > ( fndecls_p ) ; num_versions = fndecls -> length ( ) ; gcc_assert ( num_versions >= 2 ) ; function_version_info = ( struct _function_version_info * ) XNEWVEC ( struct _function_version_info , ( num_versions - 1 ) ) ; default_decl = ( * fndecls ) [ 0 ] ; push_cfun ( DECL_STRUCT_FUNCTION ( dispatch_decl ) ) ; gseq = bb_seq ( * empty_bb ) ; ifunc_cpu_init_stmt = gimple_build_call_vec ( ix86_builtins [ ( int ) IX86_BUILTIN_CPU_INIT ] , vNULL ) ; gimple_seq_add_stmt ( & gseq , ifunc_cpu_init_stmt ) ; gimple_set_bb ( ifunc_cpu_init_stmt , * empty_bb ) ; set_bb_seq ( * empty_bb , gseq ) ; pop_cfun ( ) ; for ( ix = 1 ; fndecls -> iterate ( ix , & ele ) ; ++ ix ) { tree version_decl = ele ; tree predicate_chain = NULL_TREE ; unsigned int priority ; priority = get_builtin_code_for_version ( version_decl , & predicate_chain ) ; if ( predicate_chain == NULL_TREE ) continue ; function_version_info [ actual_versions ] . version_decl = version_decl ; function_version_info [ actual_versions ] . predicate_chain = predicate_chain ; function_version_info [ actual_versions ] . dispatch_priority = priority ; actual_versions ++ ; } qsort ( function_version_info , actual_versions , sizeof ( struct _function_version_info ) , feature_compare ) ; for ( i = 0 ; i < actual_versions ; ++ i ) * empty_bb = add_condition_to_bb ( dispatch_decl , function_version_info [ i ] . version_decl , function_version_info [ i ] . predicate_chain , * empty_bb ) ; * empty_bb = add_condition_to_bb ( dispatch_decl , default_decl , NULL , * empty_bb ) ; free ( function_version_info ) ; return 0 ; } </s>

This function generates the dispatch function for multi-versioned functions . DISPATCH_DECL is the function which will contain the dispatch logic . FNDECLS are the function choices for dispatch , and is a tree chain . EMPTY_BB is the basic block pointer in DISPATCH_DECL in which the dispatch code is generated .


<s> unsigned SPUTargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , unsigned Depth ) const { switch ( Op . getOpcode ( ) ) { default : return 1 ; case ISD :: SETCC : { MVT VT = Op . getValueType ( ) ; if ( VT != MVT :: i8 && VT != MVT :: i16 && VT != MVT :: i32 ) { VT = MVT :: i32 ; } return VT . getSizeInBits ( ) ; } } } </s>

Determine the number of bits in the operation that are sign bits .


<s> bool AArch64TargetLowering :: isProfitableToHoist ( Instruction * I ) const { if ( I -> getOpcode ( ) != Instruction :: FMul ) return true ; if ( ! I -> hasOneUse ( ) ) return true ; Instruction * User = I -> user_back ( ) ; if ( User && ! ( User -> getOpcode ( ) == Instruction :: FSub || User -> getOpcode ( ) == Instruction :: FAdd ) ) return true ; const TargetOptions & Options = getTargetMachine ( ) . Options ; const DataLayout & DL = I -> getModule ( ) -> getDataLayout ( ) ; EVT VT = getValueType ( DL , User -> getOperand ( 0 ) -> getType ( ) ) ; return ! ( isFMAFasterThanFMulAndFAdd ( VT ) && isOperationLegalOrCustom ( ISD :: FMA , VT ) && ( Options . AllowFPOpFusion == FPOpFusion :: Fast || Options . UnsafeFPMath ) ) ; } </s>

Return true if it is profitable to hoist instruction in the then/else to before if .


"' value must be in the range [0, 100]!"

Parses just-constructed SpecialCaseList entries from a memory buffer .


<s> void GCNHazardRecognizer :: AdvanceCycle ( ) { if ( ! CurrCycleInstr ) return ; if ( CurrCycleInstr -> isImplicitDef ( ) || CurrCycleInstr -> isDebugInstr ( ) || CurrCycleInstr -> isKill ( ) ) return ; if ( CurrCycleInstr -> isBundle ( ) ) { processBundle ( ) ; return ; } unsigned NumWaitStates = TII . getNumWaitStates ( * CurrCycleInstr ) ; EmittedInstrs . push_front ( CurrCycleInstr ) ; for ( unsigned i = 1 , e = std :: min ( NumWaitStates , getMaxLookAhead ( ) ) ; i < e ; ++ i ) { EmittedInstrs . push_front ( nullptr ) ; } EmittedInstrs . resize ( getMaxLookAhead ( ) ) ; CurrCycleInstr = nullptr ; } </s>

AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled can not issue in the current cycle , either because of latency or resource conflicts .


<s>
void
WebAssemblyInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
OS
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
)
{
llvm_unreachable
(
"TODO: implement printInst"
)
;
}
</s>

Print the specified MCInst to the specified raw_ostream .

WebAssembly
WebAssembly
"TODO: implement printInst"


<s> int riscv_split_const_insns ( rtx x ) { unsigned int low , high ; low = riscv_const_insns ( riscv_subword ( x , false ) ) ; high = riscv_const_insns ( riscv_subword ( x , true ) ) ; gcc_assert ( low > 0 && high > 0 ) ; return low + high ; } </s>

X is a doubleword constant that can be handled by splitting it into two words and loading each word separately . Return the number of instructions required to do this .


<s> static void nios2_trampoline_init ( rtx m_tramp , tree fndecl , rtx cxt ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx ctx_reg = force_reg ( Pmode , cxt ) ; rtx addr = force_reg ( Pmode , XEXP ( m_tramp , 0 ) ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , "__trampoline_setup" ) , LCT_NORMAL , VOIDmode , 3 , addr , Pmode , fnaddr , Pmode , ctx_reg , Pmode ) ; } </s>

Emit RTL insns to initialize the variable parts of a trampoline . FNADDR is an RTX for the address of the function 's pure code . CXT is an RTX for the static chain value for the function . On Nios II , we handle this by a library call .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"SPARC Delay Slot Filler"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static MachineInstr * getDef ( unsigned Reg , const MachineRegisterInfo * MRI ) { if ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) return nullptr ; return MRI -> getUniqueVRegDef ( Reg ) ; } </s>

Get the concrete record with the specified name .


"LR & FP are always handled in emitPrologue"

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


"Only base registers and frame indices are supported."

Returns true if the two given memory operations should be scheduled adjacent .


<s> bool isToken ( ) const { return Kind == Token ; } </s>


<s> unsigned AMDGPUTargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { switch ( Op . getOpcode ( ) ) { case AMDGPUISD :: BFE_I32 : { ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ; if ( ! Width ) return 1 ; unsigned SignBits = 32 - Width -> getZExtValue ( ) + 1 ; if ( ! isNullConstant ( Op . getOperand ( 1 ) ) ) return SignBits ; unsigned Op0SignBits = DAG . ComputeNumSignBits ( Op . getOperand ( 0 ) , Depth + 1 ) ; return std :: max ( SignBits , Op0SignBits ) ; } case AMDGPUISD :: BFE_U32 : { ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ; return Width ? 32 - ( Width -> getZExtValue ( ) & 0x1f ) : 1 ; } case AMDGPUISD :: CARRY : case AMDGPUISD :: BORROW : return 31 ; case AMDGPUISD :: BUFFER_LOAD_BYTE : return 25 ; case AMDGPUISD :: BUFFER_LOAD_SHORT : return 17 ; case AMDGPUISD :: BUFFER_LOAD_UBYTE : return 24 ; case AMDGPUISD :: BUFFER_LOAD_USHORT : return 16 ; case AMDGPUISD :: FP_TO_FP16 : case AMDGPUISD :: FP16_ZEXT : return 16 ; default : return 1 ; } } </s>


<s> TargetIRAnalysis PPCTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( const Function & F ) { return TargetTransformInfo ( PPCTTIImpl ( this , F ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < MachinePostDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addPreserved < MachinePostDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


"Unknown parameter to option -mtune-ctrl: %s"

parse -mtune-ctrl= option . When DUMP is true , print the features that are explicitly set .


<s> unsigned PPCInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case PPC :: LD : case PPC :: LWZ : case PPC :: LFS : case PPC :: LFD : case PPC :: RESTORE_CR : case PPC :: RESTORE_CRBIT : case PPC :: LVX : case PPC :: RESTORE_VRSAVE : if ( MI -> getOperand ( 1 ) . isImm ( ) && ! MI -> getOperand ( 1 ) . getImm ( ) && MI -> getOperand ( 2 ) . isFI ( ) ) { FrameIndex = MI -> getOperand ( 2 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> static bool rs6000_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { unsigned from_size = GET_MODE_SIZE ( from ) ; unsigned to_size = GET_MODE_SIZE ( to ) ; if ( from_size != to_size ) { enum reg_class xclass = ( TARGET_VSX ) ? VSX_REGS : FLOAT_REGS ; if ( reg_classes_intersect_p ( xclass , rclass ) ) { unsigned to_nregs = hard_regno_nregs ( FIRST_FPR_REGNO , to ) ; unsigned from_nregs = hard_regno_nregs ( FIRST_FPR_REGNO , from ) ; bool to_float128_vector_p = FLOAT128_VECTOR_P ( to ) ; bool from_float128_vector_p = FLOAT128_VECTOR_P ( from ) ; if ( to_float128_vector_p && from_float128_vector_p ) return true ; else if ( to_float128_vector_p || from_float128_vector_p ) return false ; if ( ! BYTES_BIG_ENDIAN && ( to == TDmode || from == TDmode ) ) return false ; if ( from_size < 8 || to_size < 8 ) return false ; if ( from_size == 8 && ( 8 * to_nregs ) != to_size ) return false ; if ( to_size == 8 && ( 8 * from_nregs ) != from_size ) return false ; return true ; } else return true ; } if ( TARGET_VSX && VSX_REG_CLASS_P ( rclass ) ) { unsigned num_regs = ( from_size + 15 ) / 16 ; if ( hard_regno_nregs ( FIRST_FPR_REGNO , to ) > num_regs || hard_regno_nregs ( FIRST_FPR_REGNO , from ) > num_regs ) return false ; return ( from_size == 8 || from_size == 16 ) ; } if ( TARGET_ALTIVEC && rclass == ALTIVEC_REGS && ( ALTIVEC_VECTOR_MODE ( from ) + ALTIVEC_VECTOR_MODE ( to ) ) == 1 ) return false ; return true ; } </s>


<s>
void
AVRInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
DebugLoc
&
DL
,
MCRegister
DestReg
,
MCRegister
SrcReg
,
bool
KillSrc
)
const
{
const
AVRSubtarget
&
STI
=
MBB
.
getParent
(
)
->
getSubtarget
<
AVRSubtarget
>
(
)
;
const
AVRRegisterInfo
&
TRI
=
*
STI
.
getRegisterInfo
(
)
;
unsigned
Opc
;
if
(
AVR
::
DREGSRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
if
(
STI
.
hasMOVW
(
)
)
{
BuildMI
(
MBB
,
MI
,
DL
,
get
(
AVR
::
MOVWRdRr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
else
{
Register
DestLo
,
DestHi
,
SrcLo
,
SrcHi
;
TRI
.
splitReg
(
DestReg
,
DestLo
,
DestHi
)
;
TRI
.
splitReg
(
SrcReg
,
SrcLo
,
SrcHi
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
AVR
::
MOVRdRr
)
,
DestLo
)
.
addReg
(
SrcLo
,
getKillRegState
(
KillSrc
)
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
AVR
::
MOVRdRr
)
,
DestHi
)
.
addReg
(
SrcHi
,
getKillRegState
(
KillSrc
)
)
;
}
}
else
{
if
(
AVR
::
GPR8RegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
Opc
=
AVR
::
MOVRdRr
;
}
else
if
(
SrcReg
==
AVR
::
SP
&&
AVR
::
DREGSRegClass
.
contains
(
DestReg
)
)
{
Opc
=
AVR
::
SPREAD
;
}
else
if
(
DestReg
==
AVR
::
SP
&&
AVR
::
DREGSRegClass
.
contains
(
SrcReg
)
)
{
Opc
=
AVR
::
SPWRITE
;
}
else
{
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
}
</s>

AVR
AVR
AVR
AVR
AVR
AVR::DREGSRegClass
AVR::MOVWRdRr
AVR::MOVRdRr
AVR::MOVRdRr
AVR::GPR8RegClass
AVR::MOVRdRr
AVR::SP
AVR::DREGSRegClass
AVR::SPREAD
AVR::SP
AVR::DREGSRegClass
AVR::SPWRITE
"Impossible reg-to-reg copy"


<s> bool AArch64InstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( TargetInstrInfo :: isSchedulingBoundary ( MI , MBB , MF ) ) return true ; switch ( MI . getOpcode ( ) ) { case AArch64 :: HINT : if ( MI . getOperand ( 0 ) . getImm ( ) == 0x14 ) return true ; break ; case AArch64 :: DSB : case AArch64 :: ISB : return true ; default : ; } if ( isSEHInstruction ( MI ) ) return true ; auto Next = std :: next ( MI . getIterator ( ) ) ; return Next != MBB -> end ( ) && Next -> isCFIInstruction ( ) ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s>
void
SNESRegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected SPAdj value"
)
;
MachineInstr
&
MI
=
*
II
;
DebugLoc
dl
=
MI
.
getDebugLoc
(
)
;
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
SNESTargetMachine
&
TM
=
(
const
SNESTargetMachine
&
)
MF
.
getTarget
(
)
;
const
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
const
TargetFrameLowering
*
TFI
=
TM
.
getSubtargetImpl
(
)
->
getFrameLowering
(
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
int
Offset
=
MFI
.
getObjectOffset
(
FrameIndex
)
;
Offset
+=
MFI
.
getStackSize
(
)
TFI
->
getOffsetOfLocalArea
(
)
+
1
;
Offset
+=
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
SNES
::
A
,
false
)
;
assert
(
isUInt
<
6
>
(
Offset
)
&&
"Offset is out of range"
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool XNCMFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static int bfin_issue_rate ( void ) { return 3 ; } </s>


<s> virtual bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumInstrs ) const { return NumInstrs && NumInstrs == 1 ; } </s>

Return true if it 's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion .


<s> void ix86_emit_binop ( enum rtx_code code , machine_mode mode , rtx dst , rtx src ) { rtx op , clob ; op = gen_rtx_SET ( dst , gen_rtx_fmt_ee ( code , mode , dst , src ) ) ; clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , op , clob ) ) ) ; } </s>

Emit x86 binary operand CODE in mode MODE , where the first operand matches destination . RTX includes clobber of FLAGS_REG .


<s>
void
MetadataStreamerV3
::
verify
(
StringRef
HSAMetadataString
)
const
{
errs
(
)
<<
"AMDGPU HSA Metadata Parser Test: "
;
msgpack
::
Document
FromHSAMetadataString
;
if
(
!
FromHSAMetadataString
.
fromYAML
(
HSAMetadataString
)
)
{
errs
(
)
<<
"FAIL\n"
;
return
;
}
std
::
string
ToHSAMetadataString
;
raw_string_ostream
StrOS
(
ToHSAMetadataString
)
;
FromHSAMetadataString
.
toYAML
(
StrOS
)
;
errs
(
)
<<
(
HSAMetadataString
==
StrOS
.
str
(
)
"PASS"
:
"FAIL"
)
<<
'\n'
;
if
(
HSAMetadataString
!=
ToHSAMetadataString
)
{
errs
(
)
<<
"Original input: "
<<
HSAMetadataString
<<
'\n'
<<
"Produced output: "
<<
StrOS
.
str
(
)
<<
'\n'
;
}
}
</s>

AMDGPU
"AMDGPU HSA Metadata Parser Test: "
"FAIL\n"
"PASS"
"FAIL"
"Original input: "
"Produced output: "


<s> unsigned getFramePred ( const MachineInstr & MI ) const { assert ( isFrameInstr ( MI ) ) ; if ( isFrameSetup ( MI ) ) return MI . getOperand ( 2 ) . getReg ( ) ; assert ( MI . getOpcode ( ) == ARM :: ADJCALLSTACKUP || MI . getOpcode ( ) == ARM :: tADJCALLSTACKUP ) ; return MI . getOperand ( 3 ) . getReg ( ) ; } </s>

Returns predicate register associated with the given frame instruction .


<s> static sbitmap aarch64_get_separate_components ( void ) { sbitmap components = sbitmap_alloc ( LAST_SAVED_REGNUM + 1 ) ; bitmap_clear ( components ) ; for ( unsigned regno = 0 ; regno <= LAST_SAVED_REGNUM ; regno ++ ) if ( aarch64_register_saved_on_entry ( regno ) ) { poly_int64 offset = cfun -> machine -> frame . reg_offset [ regno ] ; if ( ! frame_pointer_needed ) offset += cfun -> machine -> frame . frame_size - cfun -> machine -> frame . hard_fp_offset ; if ( offset_12bit_unsigned_scaled_p ( DImode , offset ) ) bitmap_set_bit ( components , regno ) ; } if ( frame_pointer_needed ) bitmap_clear_bit ( components , HARD_FRAME_POINTER_REGNUM ) ; unsigned reg1 = cfun -> machine -> frame . wb_candidate1 ; unsigned reg2 = cfun -> machine -> frame . wb_candidate2 ; if ( reg2 != INVALID_REGNUM ) bitmap_clear_bit ( components , reg2 ) ; if ( reg1 != INVALID_REGNUM ) bitmap_clear_bit ( components , reg1 ) ; bitmap_clear_bit ( components , LR_REGNUM ) ; bitmap_clear_bit ( components , SP_REGNUM ) ; return components ; } </s>


"***** Machine Function before Domain Reassignment *****\n"

"***** Machine Function after Domain Reassignment *****\n"

runOnMachineFunction - Emit the function body .


<s> bool MandarinFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static machine_mode cris_cc_modes_compatible ( machine_mode m1 , machine_mode m2 ) { if ( m1 == CC_NZVCmode ) { if ( m2 == CC_NZVCmode || m2 == CCmode ) return CC_NZVCmode ; return VOIDmode ; } if ( m2 == CC_NZVCmode ) { if ( m1 == CC_NZVCmode || m1 == CCmode ) return CC_NZVCmode ; return VOIDmode ; } if ( m1 != m2 ) return CC_NZmode ; return m1 ; } </s>

Worker function for TARGET_CC_MODES_COMPATIBLE . We start with CCmode for most comparisons , which merges and yields to CC_NZmode or CC_NZVCmode . The exceptions have CC_NZVCmode and ca n't do with another mode .


<s> static int loongarch_address_cost ( rtx addr , machine_mode mode , addr_space_t as ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { return loongarch_address_insns ( addr , mode , false ) ; } </s>


<s> static void alpha_reorg ( void ) { if ( alpha_tp != ALPHA_TP_PROG || flag_exceptions ) alpha_handle_trap_shadows ( ) ; if ( optimize && ! optimize_size && alpha_tp != ALPHA_TP_INSN && flag_schedule_insns_after_reload ) { if ( alpha_tune == PROCESSOR_EV4 ) alpha_align_insns ( 8 , alphaev4_next_group , alphaev4_next_nop ) ; else if ( alpha_tune == PROCESSOR_EV5 ) alpha_align_insns ( 16 , alphaev5_next_group , alphaev5_next_nop ) ; } } </s>


<s> bool AMDGPUAlwaysInline :: runOnModule ( Module & M ) { AMDGPUAS AMDGPUAS = AMDGPU :: getAMDGPUAS ( M ) ; std :: vector < GlobalAlias * > AliasesToRemove ; SmallPtrSet < Function * , 8 > FuncsToAlwaysInline ; SmallPtrSet < Function * , 8 > FuncsToNoInline ; for ( GlobalAlias & A : M . aliases ( ) ) { if ( Function * F = dyn_cast < Function > ( A . getAliasee ( ) ) ) { A . replaceAllUsesWith ( F ) ; AliasesToRemove . push_back ( & A ) ; } } if ( GlobalOpt ) { for ( GlobalAlias * A : AliasesToRemove ) { A -> eraseFromParent ( ) ; } } for ( GlobalVariable & GV : M . globals ( ) ) { unsigned AS = GV . getType ( ) -> getAddressSpace ( ) ; if ( AS != AMDGPUAS :: LOCAL_ADDRESS && AS != AMDGPUAS . REGION_ADDRESS ) continue ; recursivelyVisitUsers ( GV , FuncsToAlwaysInline ) ; } if ( ! AMDGPUTargetMachine :: EnableFunctionCalls || StressCalls ) { auto IncompatAttr = StressCalls ? Attribute :: AlwaysInline : Attribute :: NoInline ; for ( Function & F : M ) { if ( ! F . isDeclaration ( ) && ! F . use_empty ( ) && ! F . hasFnAttribute ( IncompatAttr ) ) { if ( StressCalls ) { if ( ! FuncsToAlwaysInline . count ( & F ) ) FuncsToNoInline . insert ( & F ) ; } else FuncsToAlwaysInline . insert ( & F ) ; } } } for ( Function * F : FuncsToAlwaysInline ) F -> addFnAttr ( Attribute :: AlwaysInline ) ; for ( Function * F : FuncsToNoInline ) F -> addFnAttr ( Attribute :: NoInline ) ; return ! FuncsToAlwaysInline . empty ( ) || ! FuncsToNoInline . empty ( ) ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU::getAMDGPUAS 8 8 AMDGPU AMDGPU AMDGPU


<s> void CSKYAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const { return ; } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void mips_d_target_versions ( void ) { if ( TARGET_64BIT ) d_add_builtin_version ( "MIPS64" ) ; else d_add_builtin_version ( "MIPS32" ) ; if ( mips_abi == ABI_32 ) d_add_builtin_version ( "MIPS_O32" ) ; else if ( mips_abi == ABI_EABI ) d_add_builtin_version ( "MIPS_EABI" ) ; else if ( mips_abi == ABI_N32 ) d_add_builtin_version ( "MIPS_N32" ) ; else if ( mips_abi == ABI_64 ) d_add_builtin_version ( "MIPS_N64" ) ; else if ( mips_abi == ABI_O64 ) d_add_builtin_version ( "MIPS_O64" ) ; if ( TARGET_HARD_FLOAT_ABI ) { d_add_builtin_version ( "MIPS_HardFloat" ) ; d_add_builtin_version ( "D_HardFloat" ) ; } else if ( TARGET_SOFT_FLOAT_ABI ) { d_add_builtin_version ( "MIPS_SoftFloat" ) ; d_add_builtin_version ( "D_SoftFloat" ) ; } } </s>

Implement TARGET_D_CPU_VERSIONS for MIPS targets .


<s> bool LC2200InstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: reverse_iterator I = MBB . rbegin ( ) , REnd = MBB . rend ( ) ; while ( I != REnd && I -> isDebugInstr ( ) ) ++ I ; if ( I == REnd || ! isUnpredicatedTerminator ( * I ) ) { TBB = FBB = nullptr ; return false ; } SmallVector < MachineInstr * , 4 > BranchInstrs ; MachineInstr * LastInst = & * I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; BranchInstrs . push_back ( LastInst ) ; if ( ! getAnalyzableBrOpc ( LastOpc ) ) return true ; unsigned SecondLastOpc = 0 ; MachineInstr * SecondLastInst = nullptr ; ++ I ; while ( I != REnd && I -> isDebugInstr ( ) ) ++ I ; if ( I != REnd ) { SecondLastInst = & * I ; SecondLastOpc = SecondLastInst -> getOpcode ( ) ; if ( isUnpredicatedTerminator ( * SecondLastInst ) && ! getAnalyzableBrOpc ( SecondLastOpc ) ) return true ; } if ( ! SecondLastOpc || ( SecondLastOpc != LC2200 :: JMP && SecondLastOpc != LC2200 :: CMP_JMP && SecondLastOpc != LC2200 :: GOTO ) ) { if ( LastInst -> isUnconditionalBranch ( ) ) { TBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } AnalyzeCondBr ( LastInst , LastOpc , TBB , Cond ) ; return false ; } if ( ++ I != REnd && isUnpredicatedTerminator ( * I ) ) return true ; BranchInstrs . insert ( BranchInstrs . begin ( ) , SecondLastInst ) ; if ( SecondLastInst -> isUnconditionalBranch ( ) ) { if ( ! AllowModify ) { return true ; } TBB = SecondLastInst -> getOperand ( 0 ) . getMBB ( ) ; LastInst -> eraseFromParent ( ) ; BranchInstrs . pop_back ( ) ; return false ; } if ( ! LastInst -> isUnconditionalBranch ( ) ) return true ; AnalyzeCondBr ( SecondLastInst , SecondLastOpc , TBB , Cond ) ; FBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> const TargetRegisterClass * WDC65816RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & WDC :: Int32RegsRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> bool isMachineVerifierClean ( ) const override { return false ; } </s>

Returns true if the target is expected to pass all machine verifier checks .


"Couldn't get MachineMemOperand for store to stack."

"Only support 4-byte loads from stack now."

"Only support GPR32 stores to stack now."

Load the specified register of the given register class from the specified stack frame index .


"ASSIGNMENT of location to itself detected! [%s]\n"

Record that LOC contains VALUE . For HImode locations record that LOC+1 contains VALUE+1 . If LOC is not a register or stack slot , do nothing . If VALUE is not a register or stack slot , clear the recorded content .


<s> MipsInstrInfo :: BranchType MipsInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify , SmallVectorImpl < MachineInstr * > & BranchInstrs ) const { MachineBasicBlock :: reverse_iterator I = MBB . rbegin ( ) , REnd = MBB . rend ( ) ; while ( I != REnd && I -> isDebugValue ( ) ) ++ I ; if ( I == REnd || ! isUnpredicatedTerminator ( * I ) ) { TBB = FBB = nullptr ; return BT_NoBranch ; } MachineInstr * LastInst = & * I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; BranchInstrs . push_back ( LastInst ) ; if ( ! getAnalyzableBrOpc ( LastOpc ) ) return LastInst -> isIndirectBranch ( ) ? BT_Indirect : BT_None ; unsigned SecondLastOpc = 0 ; MachineInstr * SecondLastInst = nullptr ; ++ I ; while ( I != REnd && I -> isDebugValue ( ) ) ++ I ; if ( I != REnd ) { SecondLastInst = & * I ; SecondLastOpc = getAnalyzableBrOpc ( SecondLastInst -> getOpcode ( ) ) ; if ( isUnpredicatedTerminator ( * SecondLastInst ) && ! SecondLastOpc ) return BT_None ; } if ( ! SecondLastOpc ) { if ( LastInst -> isUnconditionalBranch ( ) ) { TBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return BT_Uncond ; } AnalyzeCondBr ( LastInst , LastOpc , TBB , Cond ) ; return BT_Cond ; } if ( ++ I != REnd && isUnpredicatedTerminator ( * I ) ) return BT_None ; BranchInstrs . insert ( BranchInstrs . begin ( ) , SecondLastInst ) ; if ( SecondLastInst -> isUnconditionalBranch ( ) ) { if ( ! AllowModify ) return BT_None ; TBB = SecondLastInst -> getOperand ( 0 ) . getMBB ( ) ; LastInst -> eraseFromParent ( ) ; BranchInstrs . pop_back ( ) ; return BT_Uncond ; } if ( ! LastInst -> isUnconditionalBranch ( ) ) return BT_None ; AnalyzeCondBr ( SecondLastInst , SecondLastOpc , TBB , Cond ) ; FBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return BT_CondUncond ; } </s>


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; default : break ; } if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_RegMask ; return CSR_64_RegMask ; } return CSR_32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
SDValue
BPFTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
DL
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
MF
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
if
(
MF
.
getFunction
(
)
->
getReturnType
(
)
->
isAggregateType
(
)
)
{
fail
(
DL
,
DAG
,
"only integer returns supported"
)
;
}
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_BPF64
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
unsigned
Opc
=
BPFISD
::
RET_FLAG
;
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
Opc
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s>
bool
R600Packetizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
const
TargetInstrInfo
*
TII
=
Fn
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
MachineLoopInfo
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
R600PacketizerList
Packetizer
(
Fn
,
MLI
)
;
assert
(
Packetizer
.
getResourceTracker
(
)
&&
"Empty DFA table!"
)
;
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
MachineBasicBlock
::
iterator
End
=
MBB
->
end
(
)
;
MachineBasicBlock
::
iterator
MI
=
MBB
->
begin
(
)
;
while
(
MI
!=
End
)
{
if
(
MI
->
isKill
(
)
||
MI
->
getOpcode
(
)
==
AMDGPU
::
IMPLICIT_DEF
||
(
MI
->
getOpcode
(
)
==
AMDGPU
::
CF_ALU
&&
!
MI
->
getOperand
(
8
)
.
getImm
(
)
)
)
{
MachineBasicBlock
::
iterator
DeleteMI
=
MI
;
++
MI
;
MBB
->
erase
(
DeleteMI
)
;
End
=
MBB
->
end
(
)
;
continue
;
}
++
MI
;
}
}
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
unsigned
RemainingCount
=
MBB
->
size
(
)
;
for
(
MachineBasicBlock
::
iterator
RegionEnd
=
MBB
->
end
(
)
;
RegionEnd
!=
MBB
->
begin
(
)
;
)
{
MachineBasicBlock
::
iterator
I
=
RegionEnd
;
for
(
;
I
!=
MBB
->
begin
(
)
;
I
,
RemainingCount
)
{
if
(
TII
->
isSchedulingBoundary
(
std
::
prev
(
I
)
,
MBB
,
Fn
)
)
break
;
}
I
=
MBB
->
begin
(
)
;
if
(
I
==
RegionEnd
)
{
RegionEnd
=
std
::
prev
(
RegionEnd
)
;
RemainingCount
;
continue
;
}
if
(
I
==
std
::
prev
(
RegionEnd
)
)
{
RegionEnd
=
std
::
prev
(
RegionEnd
)
;
continue
;
}
Packetizer
.
PacketizeMIs
(
MBB
,
I
,
RegionEnd
)
;
RegionEnd
=
I
;
}
}
return
true
;
}
</s>


<s>
SUnit
*
R600SchedStrategy
::
pickNode
(
bool
&
IsTopNode
)
{
SUnit
*
SU
=
nullptr
;
NextInstKind
=
IDOther
;
IsTopNode
=
false
;
bool
AllowSwitchToAlu
=
(
CurEmitted
>=
InstKindLimit
[
CurInstKind
]
)
||
(
Available
[
CurInstKind
]
.
empty
(
)
)
;
bool
AllowSwitchFromAlu
=
(
CurEmitted
>=
InstKindLimit
[
CurInstKind
]
)
&&
(
!
Available
[
IDFetch
]
.
empty
(
)
||
!
Available
[
IDOther
]
.
empty
(
)
)
;
if
(
CurInstKind
==
IDAlu
&&
!
Available
[
IDFetch
]
.
empty
(
)
)
{
float
ALUFetchRationEstimate
=
(
AluInstCount
+
AvailablesAluCount
(
)
+
Pending
[
IDAlu
]
.
size
(
)
)
/
(
FetchInstCount
+
Available
[
IDFetch
]
.
size
(
)
)
;
unsigned
NeededWF
=
62.5f
/
ALUFetchRationEstimate
;
DEBUG
(
dbgs
(
)
<<
NeededWF
<<
" approx. Wavefronts Required\n"
)
;
unsigned
NearRegisterRequirement
=
2
*
Available
[
IDFetch
]
.
size
(
)
;
if
(
NeededWF
>
getWFCountLimitedByGPR
(
NearRegisterRequirement
)
)
AllowSwitchFromAlu
=
true
;
}
if
(
!
SU
&&
(
(
AllowSwitchToAlu
&&
CurInstKind
!=
IDAlu
)
||
(
!
AllowSwitchFromAlu
&&
CurInstKind
==
IDAlu
)
)
)
{
SU
=
pickAlu
(
)
;
if
(
!
SU
&&
!
PhysicalRegCopy
.
empty
(
)
)
{
SU
=
PhysicalRegCopy
.
front
(
)
;
PhysicalRegCopy
.
erase
(
PhysicalRegCopy
.
begin
(
)
)
;
}
if
(
SU
)
{
if
(
CurEmitted
>=
InstKindLimit
[
IDAlu
]
)
CurEmitted
=
0
;
NextInstKind
=
IDAlu
;
}
}
if
(
!
SU
)
{
SU
=
pickOther
(
IDFetch
)
;
if
(
SU
)
NextInstKind
=
IDFetch
;
}
if
(
!
SU
)
{
SU
=
pickOther
(
IDOther
)
;
if
(
SU
)
NextInstKind
=
IDOther
;
}
DEBUG
(
if
(
SU
)
{
dbgs
(
)
<<
" ** Pick node **\n"
;
SU
->
dump
(
DAG
)
;
}
else
{
dbgs
(
)
<<
"NO NODE \n"
;
for
(
unsigned
i
=
0
;
i
<
DAG
->
SUnits
.
size
(
)
;
i
++
)
{
const
SUnit
&
S
=
DAG
->
SUnits
[
i
]
;
if
(
!
S
.
isScheduled
)
S
.
dump
(
DAG
)
;
}
}
</s>

Pick the next node to schedule , or return NULL .


<s> Register SIInstrInfo :: readlaneVGPRToSGPR ( Register SrcReg , MachineInstr & UseMI , MachineRegisterInfo & MRI ) const { const TargetRegisterClass * VRC = MRI . getRegClass ( SrcReg ) ; const TargetRegisterClass * SRC = RI . getEquivalentSGPRClass ( VRC ) ; Register DstReg = MRI . createVirtualRegister ( SRC ) ; unsigned SubRegs = RI . getRegSizeInBits ( * VRC ) / 32 ; if ( RI . hasAGPRs ( VRC ) ) { VRC = RI . getEquivalentVGPRClass ( VRC ) ; Register NewSrcReg = MRI . createVirtualRegister ( VRC ) ; BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) , NewSrcReg ) . addReg ( SrcReg ) ; SrcReg = NewSrcReg ; } if ( SubRegs == 1 ) { BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( AMDGPU :: V_READFIRSTLANE_B32 ) , DstReg ) . addReg ( SrcReg ) ; return DstReg ; } SmallVector < unsigned , 8 > SRegs ; for ( unsigned i = 0 ; i < SubRegs ; ++ i ) { Register SGPR = MRI . createVirtualRegister ( & AMDGPU :: SGPR_32RegClass ) ; BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( AMDGPU :: V_READFIRSTLANE_B32 ) , SGPR ) . addReg ( SrcReg , 0 , RI . getSubRegFromChannel ( i ) ) ; SRegs . push_back ( SGPR ) ; } MachineInstrBuilder MIB = BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( AMDGPU :: REG_SEQUENCE ) , DstReg ) ; for ( unsigned i = 0 ; i < SubRegs ; ++ i ) { MIB . addReg ( SRegs [ i ] ) ; MIB . addImm ( RI . getSubRegFromChannel ( i ) ) ; } return DstReg ; } </s>

Copy a value from a VGPR ( SrcReg ) to SGPR .


<s> static inline int avr_outgoing_args_size ( void ) { return ACCUMULATE_OUTGOING_ARGS ? crtl -> outgoing_args_size : 0 ; } </s>

Report contribution of accumulated outgoing arguments to stack size .


<s> const M68kInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> virtual bool ShouldShrinkFPConstant ( MVT VT ) const { return ! X86ScalarSSEf64 || VT == MVT :: f80 ; } </s>

If true , then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime .


<s> bool ARM64InstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , const SmallVectorImpl < MachineOperand > & Cond , unsigned TrueReg , unsigned FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; unsigned ExtraCondLat = Cond . size ( ) != 1 ; if ( ARM64 :: GPR64allRegClass . hasSubClassEq ( RC ) || ARM64 :: GPR32allRegClass . hasSubClassEq ( RC ) ) { CondCycles = 1 + ExtraCondLat ; TrueCycles = FalseCycles = 1 ; if ( canFoldIntoCSel ( MRI , TrueReg ) ) TrueCycles = 0 ; else if ( canFoldIntoCSel ( MRI , FalseReg ) ) FalseCycles = 0 ; return true ; } if ( ARM64 :: FPR64RegClass . hasSubClassEq ( RC ) || ARM64 :: FPR32RegClass . hasSubClassEq ( RC ) ) { CondCycles = 5 + ExtraCondLat ; TrueCycles = FalseCycles = 2 ; return true ; } return false ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> bool ARMTargetLowering :: isUsedByReturnOnly ( SDNode * N , SDValue & Chain ) const { if ( N -> getNumValues ( ) != 1 ) return false ; if ( ! N -> hasNUsesOfValue ( 1 , 0 ) ) return false ; SDValue TCChain = Chain ; SDNode * Copy = * N -> use_begin ( ) ; if ( Copy -> getOpcode ( ) == ISD :: CopyToReg ) { if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - 1 ) . getValueType ( ) == MVT :: Glue ) return false ; TCChain = Copy -> getOperand ( 0 ) ; } else if ( Copy -> getOpcode ( ) == ARMISD :: VMOVRRD ) { SDNode * VMov = Copy ; SmallPtrSet < SDNode * , 2 > Copies ; for ( SDNode :: use_iterator UI = VMov -> use_begin ( ) , UE = VMov -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != ISD :: CopyToReg ) return false ; Copies . insert ( * UI ) ; } if ( Copies . size ( ) > 2 ) return false ; for ( SDNode :: use_iterator UI = VMov -> use_begin ( ) , UE = VMov -> use_end ( ) ; UI != UE ; ++ UI ) { SDValue UseChain = UI -> getOperand ( 0 ) ; if ( Copies . count ( UseChain . getNode ( ) ) ) Copy = * UI ; else TCChain = UseChain ; } } else if ( Copy -> getOpcode ( ) == ISD :: BITCAST ) { if ( ! Copy -> hasOneUse ( ) ) return false ; Copy = * Copy -> use_begin ( ) ; if ( Copy -> getOpcode ( ) != ISD :: CopyToReg || ! Copy -> hasNUsesOfValue ( 1 , 0 ) ) return false ; TCChain = Copy -> getOperand ( 0 ) ; } else { return false ; } bool HasRet = false ; for ( SDNode :: use_iterator UI = Copy -> use_begin ( ) , UE = Copy -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != ARMISD :: RET_FLAG && UI -> getOpcode ( ) != ARMISD :: INTRET_FLAG ) return false ; HasRet = true ; } if ( ! HasRet ) return false ; Chain = TCChain ; return true ; } </s>

Return true if result of the specified node is used by a return node only .


<s> bool invalid_e500_subreg ( rtx op , machine_mode mode ) { if ( TARGET_E500_DOUBLE ) { if ( GET_CODE ( op ) == SUBREG && ( mode == SImode || mode == DImode || mode == TImode || mode == DDmode || mode == TDmode || mode == PTImode ) && REG_P ( SUBREG_REG ( op ) ) && ( GET_MODE ( SUBREG_REG ( op ) ) == DFmode || GET_MODE ( SUBREG_REG ( op ) ) == TFmode ) ) return true ; if ( GET_CODE ( op ) == SUBREG && ( mode == DFmode || mode == TFmode ) && REG_P ( SUBREG_REG ( op ) ) && ( GET_MODE ( SUBREG_REG ( op ) ) == DImode || GET_MODE ( SUBREG_REG ( op ) ) == TImode || GET_MODE ( SUBREG_REG ( op ) ) == PTImode || GET_MODE ( SUBREG_REG ( op ) ) == DDmode || GET_MODE ( SUBREG_REG ( op ) ) == TDmode ) ) return true ; } if ( TARGET_SPE && GET_CODE ( op ) == SUBREG && mode == SImode && REG_P ( SUBREG_REG ( op ) ) && SPE_VECTOR_MODE ( GET_MODE ( SUBREG_REG ( op ) ) ) ) return true ; return false ; } </s>

Return TRUE if OP is an invalid SUBREG operation on the e500 .


<s> bool fixupNeedsRelaxationAdvanced ( const MCFixup & Fixup , bool Resolved , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { MCInst const & MCB = DF -> getInst ( ) ; assert ( HexagonMCInstrInfo :: isBundle ( MCB ) ) ; * RelaxTarget = nullptr ; MCInst & MCI = const_cast < MCInst & > ( HexagonMCInstrInfo :: instruction ( MCB , Fixup . getOffset ( ) / HEXAGON_INSTR_SIZE ) ) ; bool Relaxable = isInstRelaxable ( MCI ) ; if ( Relaxable == false ) return false ; if ( ! Resolved ) { switch ( ( unsigned ) Fixup . getKind ( ) ) { case fixup_Hexagon_B22_PCREL : LLVM_FALLTHROUGH ; default : return false ; break ; case fixup_Hexagon_B13_PCREL : case fixup_Hexagon_B15_PCREL : case fixup_Hexagon_B9_PCREL : case fixup_Hexagon_B7_PCREL : { if ( HexagonMCInstrInfo :: bundleSize ( MCB ) < HEXAGON_PACKET_SIZE ) { ++ relaxedCnt ; * RelaxTarget = & MCI ; setExtender ( Layout . getAssembler ( ) . getContext ( ) ) ; return true ; } else { return false ; } break ; } } } MCFixupKind Kind = Fixup . getKind ( ) ; int64_t sValue = Value ; int64_t maxValue ; switch ( ( unsigned ) Kind ) { case fixup_Hexagon_B7_PCREL : maxValue = 1 << 8 ; break ; case fixup_Hexagon_B9_PCREL : maxValue = 1 << 10 ; break ; case fixup_Hexagon_B15_PCREL : maxValue = 1 << 16 ; break ; case fixup_Hexagon_B22_PCREL : maxValue = 1 << 23 ; break ; default : maxValue = INT64_MAX ; break ; } bool isFarAway = - maxValue > sValue || sValue > maxValue - 1 ; if ( isFarAway ) { if ( HexagonMCInstrInfo :: bundleSize ( MCB ) < HEXAGON_PACKET_SIZE ) { ++ relaxedCnt ; * RelaxTarget = & MCI ; setExtender ( Layout . getAssembler ( ) . getContext ( ) ) ; return true ; } } return false ; } </s>

Target specific predicate for whether a given fixup requires the associated instruction to be relaxed .


<s> void MBlazeFrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MBlazeInstrInfo & TII = * static_cast < const MBlazeInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MBlazeFunctionInfo * MBlazeFI = MF . getInfo < MBlazeFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; llvm :: CallingConv :: ID CallConv = MF . getFunction ( ) -> getCallingConv ( ) ; bool requiresRA = CallConv == llvm :: CallingConv :: MBLAZE_INTR ; determineFrameLayout ( MF ) ; unsigned StackSize = MFI -> getStackSize ( ) ; if ( StackSize == 0 && ! MFI -> adjustsStack ( ) && ! requiresRA ) return ; int FPOffset = MBlazeFI -> getFPStackOffset ( ) ; int RAOffset = MBlazeFI -> getRAStackOffset ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( MBlaze :: ADDIK ) , MBlaze :: R1 ) . addReg ( MBlaze :: R1 ) . addImm ( - StackSize ) ; if ( MFI -> adjustsStack ( ) || requiresRA ) { BuildMI ( MBB , MBBI , DL , TII . get ( MBlaze :: SWI ) ) . addReg ( MBlaze :: R15 ) . addReg ( MBlaze :: R1 ) . addImm ( RAOffset ) ; } if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( MBlaze :: SWI ) ) . addReg ( MBlaze :: R19 ) . addReg ( MBlaze :: R1 ) . addImm ( FPOffset ) ; BuildMI ( MBB , MBBI , DL , TII . get ( MBlaze :: ADD ) , MBlaze :: R19 ) . addReg ( MBlaze :: R1 ) . addReg ( MBlaze :: R0 ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"AMDGPU simplify control flow"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static rtx alpha_function_arg ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int basereg ; int num_args ; if ( type && AGGREGATE_TYPE_P ( type ) ) basereg = 16 ; else { gcc_checking_assert ( ! COMPLEX_MODE_P ( mode ) ) ; if ( TARGET_FPREGS && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) basereg = 32 + 16 ; else basereg = 16 ; } { if ( mode == VOIDmode ) return alpha_arg_info_reg_val ( * cum ) ; num_args = cum -> num_args ; if ( num_args >= 6 || targetm . calls . must_pass_in_stack ( mode , type ) ) return NULL_RTX ; } { if ( * cum >= 6 ) return NULL_RTX ; num_args = * cum ; if ( type == void_type_node ) basereg = 16 ; else if ( targetm . calls . must_pass_in_stack ( mode , type ) ) return NULL_RTX ; } return gen_rtx_REG ( mode , num_args + basereg ) ; } </s>

Determine where to put an argument to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . On Alpha the first 6 words of args are normally in registers and the rest are pushed .


<s> bool X86FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( MI ) ; if ( MBB . isEHFuncletEntry ( ) && STI . is32Bit ( ) && STI . isOSWindows ( ) ) return true ; const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Opc = STI . is64Bit ( ) ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; bool isLiveIn = MF . getRegInfo ( ) . isLiveIn ( Reg ) ; if ( ! isLiveIn ) MBB . addLiveIn ( Reg ) ; bool isKill = ! isLiveIn ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , getKillRegState ( isKill ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - 1 ] . getFrameIdx ( ) , RC , TRI ) ; -- MI ; MI -> setFlag ( MachineInstr :: FrameSetup ) ; ++ MI ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s>
void
ARM64Operand
::
print
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
k_FPImm
:
OS
<<
"<fpimm "
<<
getFPImm
(
)
<<
"("
<<
ARM64_AM
::
getFPImmFloat
(
getFPImm
(
)
)
<<
") >"
;
break
;
case
k_Barrier
:
{
bool
Valid
;
StringRef
Name
=
ARM64DB
::
DBarrierMapper
(
)
.
toString
(
getBarrier
(
)
,
Valid
)
;
if
(
Valid
)
OS
<<
"<barrier "
<<
Name
<<
">"
;
else
OS
<<
"<barrier invalid #"
<<
getBarrier
(
)
<<
">"
;
break
;
}
case
k_Immediate
:
getImm
(
)
->
print
(
OS
)
;
break
;
case
k_Memory
:
OS
<<
"<memory>"
;
break
;
case
k_Register
:
OS
<<
"<register "
<<
getReg
(
)
<<
">"
;
break
;
case
k_VectorList
:
{
OS
<<
"<vectorlist "
;
unsigned
Reg
=
getVectorListStart
(
)
;
for
(
unsigned
i
=
0
,
e
=
getVectorListCount
(
)
;
i
!=
e
;
++
i
)
OS
<<
Reg
+
i
<<
" "
;
OS
<<
">"
;
break
;
}
case
k_VectorIndex
:
OS
<<
"<vectorindex "
<<
getVectorIndex
(
)
<<
">"
;
break
;
case
k_SysReg
:
OS
<<
"<sysreg: "
<<
getSysReg
(
)
<<
'>'
;
break
;
case
k_Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
case
k_SysCR
:
OS
<<
"c"
<<
getSysCR
(
)
;
break
;
case
k_Prefetch
:
{
bool
Valid
;
StringRef
Name
=
ARM64PRFM
::
PRFMMapper
(
)
.
toString
(
getPrefetch
(
)
,
Valid
)
;
if
(
Valid
)
OS
<<
"<prfop "
<<
Name
<<
">"
;
else
OS
<<
"<prfop invalid #"
<<
getPrefetch
(
)
<<
">"
;
break
;
}
case
k_Shifter
:
{
unsigned
Val
=
getShifter
(
)
;
OS
<<
"<"
<<
ARM64_AM
::
getShiftName
(
ARM64_AM
::
getShiftType
(
Val
)
)
<<
" #"
<<
ARM64_AM
::
getShiftValue
(
Val
)
<<
">"
;
break
;
}
case
k_Extend
:
{
unsigned
Val
=
getExtend
(
)
;
OS
<<
"<"
<<
ARM64_AM
::
getExtendName
(
ARM64_AM
::
getArithExtendType
(
Val
)
)
<<
" #"
<<
ARM64_AM
::
getArithShiftValue
(
Val
)
<<
">"
;
break
;
}
}
}
</s>

print - Print a debug representation of the operand to the given stream .

ARM64
ARM64
"<fpimm "
"("
ARM64_AM::getFPImmFloat
") >"
ARM64DB::DBarrierMapper
"<barrier "
">"
"<barrier invalid #"
">"
"<memory>"
"<register "
">"
"<vectorlist "
0
" "
">"
"<vectorindex "
">"
"<sysreg: "
"'"
"'"
"c"
ARM64PRFM::PRFMMapper
"<prfop "
">"
"<prfop invalid #"
">"
"<"
ARM64_AM::getShiftName
ARM64_AM::getShiftType
" #"
ARM64_AM::getShiftValue
">"
"<"
ARM64_AM::getExtendName
ARM64_AM::getArithExtendType
" #"
ARM64_AM::getArithShiftValue
">"


<s> unsigned MSP430RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const MSP430FrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? MSP430 :: FP : MSP430 :: SP ; } </s>


<s>
bool
PPCAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
{
if
(
ExtraCode
[
1
]
!=
0
)
return
true
;
switch
(
ExtraCode
[
0
]
)
{
default
:
return
true
;
case
'L'
:
O
<<
getDataLayout
(
)
.
getPointerSize
(
)
<<
"("
;
printOperand
(
MI
,
OpNo
,
O
)
;
O
<<
")"
;
return
false
;
case
'y'
:
O
<<
"0, "
;
printOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
case
'U'
:
case
'X'
:
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
return
false
;
}
}
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
O
<<
"0("
;
printOperand
(
MI
,
OpNo
,
O
)
;
O
<<
")"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> static void aarch64_adjust_generic_arch_tuning ( struct tune_params & current_tune ) { if ( TARGET_SVE2 ) current_tune . extra_tuning_flags &= ~ AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS ; } </s>

Adjust CURRENT_TUNE ( a generic tuning struct ) with settings that are best for a generic target with the currently-enabled architecture extensions .


"iwmmxt requires an AAPCS compatible ABI for proper operation"

"iwmmxt abi requires an iwmmxt capable cpu"

"target CPU does not support interworking"

"AAPCS does not support %<-mcaller-super-interworking%>"

"AAPCS does not support %<-mcallee-super-interworking%>"

"target CPU does not support ARMv8-M Security Extensions"

"ARMv8-M Security Extensions incompatible with selected FPU"

"%<-mfloat-abi=hard%>: selected architecture lacks an FPU"

Perform some validation between the desired architecture and the rest of the options .


<s> ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const override { ScheduleDAGMILive * DAG = createGenericSchedLive ( C ) ; const ARMSubtarget & ST = C -> MF -> getSubtarget < ARMSubtarget > ( ) ; if ( ST . hasFusion ( ) ) DAG -> addMutation ( createARMMacroFusionDAGMutation ( ) ) ; return DAG ; } </s>

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level .


"argument %d of %qE must be in the range %d...%d"

"argument %d of %qE must be a multiple of %d"

"incompatible type for argument %d of %qE"

Report that ARG can not be passed to argument ARGNUM of intrinsic function FNNAME . OPERAND describes the operand to which ARGNUM is mapped .


<s> static void tilepro_trampoline_init ( rtx m_tramp , tree fndecl , rtx static_chain ) { rtx fnaddr , chaddr ; rtx mem ; rtx begin_addr , end_addr ; int ptr_mode_size = GET_MODE_SIZE ( ptr_mode ) ; fnaddr = copy_to_reg ( XEXP ( DECL_RTL ( fndecl ) , 0 ) ) ; chaddr = copy_to_reg ( static_chain ) ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp , ptr_mode , TRAMPOLINE_SIZE - 2 * ptr_mode_size ) ; emit_move_insn ( mem , fnaddr ) ; mem = adjust_address ( m_tramp , ptr_mode , TRAMPOLINE_SIZE - ptr_mode_size ) ; emit_move_insn ( mem , chaddr ) ; begin_addr = force_reg ( Pmode , XEXP ( m_tramp , 0 ) ) ; end_addr = force_reg ( Pmode , plus_constant ( Pmode , XEXP ( m_tramp , 0 ) , TRAMPOLINE_SIZE ) ) ; maybe_emit_call_builtin___clear_cache ( begin_addr , end_addr ) ; } </s>


<s> static void expand_setmem_epilogue_via_loop ( rtx destmem , rtx destptr , rtx value , rtx count , int max_size ) { count = expand_simple_binop ( counter_mode ( count ) , AND , count , GEN_INT ( max_size - 1 ) , count , 1 , OPTAB_DIRECT ) ; expand_set_or_movmem_via_loop ( destmem , NULL , destptr , NULL , gen_lowpart ( QImode , value ) , count , QImode , 1 , max_size / 2 , true ) ; } </s>

Output code to set at most count & ( max_size - 1 ) bytes starting by DEST .


<s> static int s390_register_move_cost ( machine_mode mode , reg_class_t from , reg_class_t to ) { if ( TARGET_Z10 && GET_MODE_SIZE ( mode ) == 8 ) { if ( reg_classes_intersect_p ( from , GENERAL_REGS ) && reg_classes_intersect_p ( to , FP_REGS ) ) return 1 ; if ( reg_classes_intersect_p ( to , GENERAL_REGS ) && reg_classes_intersect_p ( from , FP_REGS ) ) return 3 ; } if ( ( reg_classes_intersect_p ( from , GENERAL_REGS ) && reg_classes_intersect_p ( to , FP_REGS ) ) || ( reg_classes_intersect_p ( from , FP_REGS ) && reg_classes_intersect_p ( to , GENERAL_REGS ) ) ) return 10 ; return 1 ; } </s>


<s> unsigned MBlazeRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; return TFI -> hasFP ( MF ) ? MBlaze :: R19 : MBlaze :: R1 ; } </s>


<s> void function_builder :: add_overloaded_function ( const function_instance & instance , uint64_t required_extensions ) { char * name = get_name ( instance , true ) ; if ( registered_function * * map_value = m_overload_names . get ( name ) ) gcc_assert ( ( * map_value ) -> instance == instance && ( ( * map_value ) -> required_extensions & ~ required_extensions ) == 0 ) ; else { registered_function & rfn = add_function ( instance , name , m_overload_type , NULL_TREE , required_extensions , true ) ; const char * permanent_name = IDENTIFIER_POINTER ( DECL_NAME ( rfn . decl ) ) ; m_overload_names . put ( permanent_name , & rfn ) ; } obstack_free ( & m_string_obstack , name ) ; } </s>

Add one function decl for INSTANCE , to be used with manual overload resolution . REQUIRED_EXTENSIONS are the set of architecture extensions that the function requires . For simplicity , deal with duplicate attempts to add the same function , including cases in which the new function requires more features than the original one did . In that case we 'll check whether the required features are available as part of resolving the function to the relevant unique function .


<s> void X86AsmBackend :: emitInstructionBegin ( MCObjectStreamer & OS , const MCInst & Inst ) { if ( ! needAlign ( OS ) ) return ; if ( hasInterruptDelaySlot ( PrevInst ) ) return ; if ( isPrefix ( PrevInst , * MCII ) ) return ; if ( isRightAfterData ( OS . getCurrentFragment ( ) , PrevInstPosition ) ) return ; if ( ! isMacroFused ( PrevInst , Inst ) ) PendingBoundaryAlign = nullptr ; if ( PendingBoundaryAlign && OS . getCurrentFragment ( ) -> getPrevNode ( ) == PendingBoundaryAlign ) { return ; } if ( needAlignInst ( Inst ) || ( ( AlignBranchType & X86 :: AlignBranchFused ) && isFirstMacroFusibleInst ( Inst , * MCII ) ) ) { OS . insert ( PendingBoundaryAlign = new MCBoundaryAlignFragment ( AlignBoundary ) ) ; } } </s>

Give the target a chance to manipulate state related to instruction alignment ( e.g .


<s> static const char * rl78_strip_nonasm_name_encoding ( const char * sym ) { while ( 1 ) { if ( * sym == '@' && sym [ 2 ] == '.' ) sym += 3 ; else return sym ; } } </s>

Like rl78_strip_name_encoding , but does not strip leading asterisks . This is important if the stripped name is going to be passed to assemble_name ( ) as that handles asterisk prefixed names in a special manner .


<s> const VETargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


<s> virtual const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> bool ARMBaseInstrInfo :: analyzeCompare ( const MachineInstr & MI , unsigned & SrcReg , unsigned & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI . getOpcode ( ) ) { default : break ; case ARM :: CMPri : case ARM :: t2CMPri : case ARM :: tCMPi8 : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 1 ) . getImm ( ) ; return true ; case ARM :: CMPrr : case ARM :: t2CMPrr : case ARM :: tCMPr : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 1 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case ARM :: TSTri : case ARM :: t2TSTri : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = MI . getOperand ( 1 ) . getImm ( ) ; CmpValue = 0 ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> int standard_80387_constant_p ( rtx x ) { machine_mode mode = GET_MODE ( x ) ; REAL_VALUE_TYPE r ; if ( ! ( X87_FLOAT_MODE_P ( mode ) && ( GET_CODE ( x ) == CONST_DOUBLE ) ) ) return - 1 ; if ( x == CONST0_RTX ( mode ) ) return 1 ; if ( x == CONST1_RTX ( mode ) ) return 2 ; REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; if ( mode == XFmode && ( optimize_function_for_size_p ( cfun ) || TARGET_EXT_80387_CONSTANTS ) ) { int i ; if ( ! ext_80387_constants_init ) init_ext_80387_constants ( ) ; for ( i = 0 ; i < 5 ; i ++ ) if ( real_identical ( & r , & ext_80387_constants_table [ i ] ) ) return i + 3 ; } if ( real_isnegzero ( & r ) ) return 8 ; if ( real_identical ( & r , & dconstm1 ) ) return 9 ; return 0 ; } </s>

Return true if the constant is something that can be loaded with a special instruction .


<s> static bool arm_block_set_vect ( rtx dstbase , unsigned HOST_WIDE_INT length , unsigned HOST_WIDE_INT value , unsigned HOST_WIDE_INT align ) { if ( ( ( align & 3 ) != 0 || ( length & 3 ) != 0 ) && ( ! unaligned_access || BYTES_BIG_ENDIAN ) ) return false ; if ( ( align & 3 ) == 0 ) return arm_block_set_aligned_vect ( dstbase , length , value , align ) ; else return arm_block_set_unaligned_vect ( dstbase , length , value , align ) ; } </s>

Set a block of memory using vectorization instructions for both aligned and unaligned cases . We fill the first LENGTH bytes of the memory area starting from DSTBASE with byte constant VALUE . ALIGN is the alignment requirement of memory .


<s> rtx legitimize_pic_address ( rtx orig , enum machine_mode mode ATTRIBUTE_UNUSED , rtx reg ) { if ( GET_CODE ( orig ) == SYMBOL_REF ) { rtx pic_ref , address ; rtx insn ; if ( reg == 0 ) { gcc_assert ( ! reload_in_progress && ! reload_completed ) ; reg = gen_reg_rtx ( Pmode ) ; } if ( flag_pic == 2 ) { rtx temp_reg = ( ( reload_in_progress || reload_completed ) ? reg : gen_reg_rtx ( Pmode ) ) ; if ( TARGET_ARCH64 ) { emit_insn ( gen_movdi_high_pic ( temp_reg , orig ) ) ; emit_insn ( gen_movdi_lo_sum_pic ( temp_reg , temp_reg , orig ) ) ; } else { emit_insn ( gen_movsi_high_pic ( temp_reg , orig ) ) ; emit_insn ( gen_movsi_lo_sum_pic ( temp_reg , temp_reg , orig ) ) ; } address = temp_reg ; } else address = orig ; pic_ref = gen_const_mem ( Pmode , gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , address ) ) ; current_function_uses_pic_offset_table = 1 ; insn = emit_move_insn ( reg , pic_ref ) ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_EQUAL , orig , REG_NOTES ( insn ) ) ; return reg ; } else if ( GET_CODE ( orig ) == CONST ) { rtx base , offset ; if ( GET_CODE ( XEXP ( orig , 0 ) ) == PLUS && XEXP ( XEXP ( orig , 0 ) , 0 ) == pic_offset_table_rtx ) return orig ; if ( reg == 0 ) { gcc_assert ( ! reload_in_progress && ! reload_completed ) ; reg = gen_reg_rtx ( Pmode ) ; } gcc_assert ( GET_CODE ( XEXP ( orig , 0 ) ) == PLUS ) ; base = legitimize_pic_address ( XEXP ( XEXP ( orig , 0 ) , 0 ) , Pmode , reg ) ; offset = legitimize_pic_address ( XEXP ( XEXP ( orig , 0 ) , 1 ) , Pmode , base == reg ? 0 : reg ) ; if ( GET_CODE ( offset ) == CONST_INT ) { if ( SMALL_INT ( offset ) ) return plus_constant ( base , INTVAL ( offset ) ) ; else if ( ! reload_in_progress && ! reload_completed ) offset = force_reg ( Pmode , offset ) ; else gcc_unreachable ( ) ; } return gen_rtx_PLUS ( Pmode , base , offset ) ; } else if ( GET_CODE ( orig ) == LABEL_REF ) current_function_uses_pic_offset_table = 1 ; return orig ; } </s>

Legitimize PIC addresses . If the address is already position-independent , we return ORIG . Newly generated position-independent addresses go into a reg . This is REG if nonzero , otherwise we allocate register ( s ) as necessary .


<s> bool RISCVRegisterInfo :: isConstantPhysReg ( MCRegister PhysReg ) const { return PhysReg == RISCV :: X0 ; } </s>

Returns true if PhysReg is unallocatable and constant throughout the function .


"\nm32c_legitimize_reload_address for mode %s\n"

Implements LEGITIMIZE_RELOAD_ADDRESS . See comment above .


<s> bool SIWholeQuadMode :: runOnMachineFunction ( MachineFunction & MF ) { Instructions . clear ( ) ; Blocks . clear ( ) ; LiveMaskQueries . clear ( ) ; LowerToCopyInstrs . clear ( ) ; LowerToMovInstrs . clear ( ) ; CallingConv = MF . getFunction ( ) . getCallingConv ( ) ; ST = & MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST -> getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; LIS = & getAnalysis < LiveIntervals > ( ) ; char GlobalFlags = analyzeFunction ( MF ) ; unsigned LiveMaskReg = 0 ; unsigned Exec = ST -> isWave32 ( ) ? AMDGPU :: EXEC_LO : AMDGPU :: EXEC ; if ( ! ( GlobalFlags & StateWQM ) ) { lowerLiveMaskQueries ( Exec ) ; if ( ! ( GlobalFlags & StateWWM ) && LowerToCopyInstrs . empty ( ) && LowerToMovInstrs . empty ( ) ) return ! LiveMaskQueries . empty ( ) ; } else { MachineBasicBlock & Entry = MF . front ( ) ; MachineBasicBlock :: iterator EntryMI = Entry . getFirstNonPHI ( ) ; if ( GlobalFlags & StateExact || ! LiveMaskQueries . empty ( ) ) { LiveMaskReg = MRI -> createVirtualRegister ( TRI -> getBoolRC ( ) ) ; MachineInstr * MI = BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( AMDGPU :: COPY ) , LiveMaskReg ) . addReg ( Exec ) ; LIS -> InsertMachineInstrInMaps ( * MI ) ; } lowerLiveMaskQueries ( LiveMaskReg ) ; if ( GlobalFlags == StateWQM ) { BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( ST -> isWave32 ( ) ? AMDGPU :: S_WQM_B32 : AMDGPU :: S_WQM_B64 ) , Exec ) . addReg ( Exec ) ; lowerCopyInstrs ( ) ; return true ; } } LLVM_DEBUG ( printInfo ( ) ) ; lowerCopyInstrs ( ) ; for ( auto BII : Blocks ) processBlock ( * BII . first , LiveMaskReg , BII . first == & * MF . begin ( ) ) ; LIS -> removeRegUnit ( * MCRegUnitIterator ( AMDGPU :: SCC , TRI ) ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool or1k_function_ok_for_sibcall ( tree decl , tree ) { if ( ! flag_pic ) return true ; if ( decl == NULL ) return true ; return targetm . binds_local_p ( decl ) ; } </s>

Worker for TARGET_FUNCTION_OK_FOR_SIBCALL . Returns true if the function declared by DECL is ok for calling as a nested function .


<s> enum aarch64_symbol_type aarch64_classify_symbolic_expression ( rtx x ) { rtx offset ; split_const ( x , & x , & offset ) ; return aarch64_classify_symbol ( x , INTVAL ( offset ) ) ; } </s>

Classify the base of symbolic expression X , given that X appears in context CONTEXT .