<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> static bool reg_offset_addressing_ok_p ( machine_mode mode ) { switch ( mode ) { case V16QImode : case V8HImode : case V4SFmode : case V4SImode : case V2DFmode : case V2DImode : case V1TImode : case TImode : case TFmode : case KFmode : if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) ) return mode_supports_vsx_dform_quad ( mode ) ; break ; case V4HImode : case V2SImode : case V1DImode : case V2SFmode : if ( TARGET_PAIRED_FLOAT ) return false ; break ; case SDmode : if ( TARGET_NO_SDMODE_STACK ) return false ; break ; default : break ; } return true ; } </s>

Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p .


<s> SDValue MSP430TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , unsigned CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_MSP430 ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> HOST_WIDE_INT sparc_compute_frame_size ( HOST_WIDE_INT size , int leaf_function ) { HOST_WIDE_INT frame_size , apparent_frame_size ; int args_size , n_global_fp_regs = 0 ; bool save_local_in_regs_p = false ; unsigned int i ; if ( leaf_function && ! cfun -> calls_alloca ) args_size = 0 ; else args_size = crtl -> outgoing_args_size + REG_PARM_STACK_SPACE ( cfun -> decl ) ; if ( TARGET_ARCH64 ) { for ( i = 0 ; i < 8 ; i ++ ) if ( save_global_or_fp_reg_p ( i , 0 ) ) n_global_fp_regs += 2 ; } else { for ( i = 0 ; i < 8 ; i += 2 ) if ( save_global_or_fp_reg_p ( i , 0 ) || save_global_or_fp_reg_p ( i + 1 , 0 ) ) n_global_fp_regs += 2 ; } if ( TARGET_FLAT ) for ( i = 16 ; i < 32 ; i ++ ) if ( save_local_or_in_reg_p ( i , leaf_function ) ) { save_local_in_regs_p = true ; break ; } for ( i = 32 ; i < ( TARGET_V9 ? 96 : 64 ) ; i += 2 ) if ( save_global_or_fp_reg_p ( i , 0 ) || save_global_or_fp_reg_p ( i + 1 , 0 ) ) n_global_fp_regs += 2 ; if ( size == 0 && n_global_fp_regs == 0 && args_size == 0 && ! save_local_in_regs_p ) frame_size = apparent_frame_size = 0 ; else { apparent_frame_size = ROUND_UP ( size - STARTING_FRAME_OFFSET , 8 ) ; apparent_frame_size += n_global_fp_regs * 4 ; frame_size = apparent_frame_size + ROUND_UP ( args_size , 8 ) ; frame_size += FIRST_PARM_OFFSET ( cfun -> decl ) ; frame_size = SPARC_STACK_ALIGN ( frame_size ) ; } sparc_frame_size = frame_size ; sparc_apparent_frame_size = apparent_frame_size ; sparc_n_global_fp_regs = n_global_fp_regs ; sparc_save_local_in_regs_p = save_local_in_regs_p ; return frame_size ; } </s>

Compute the frame size required by the function . This function is called during the reload pass and also by sparc_expand_prologue .


<s>
SDValue
RISCVTargetLowering
::
PerformDAGCombine
(
SDNode
*
N
,
DAGCombinerInfo
&
DCI
)
const
{
SelectionDAG
&
DAG
=
DCI
.
DAG
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
break
;
case
ISD
::
SHL
:
case
ISD
::
SRL
:
case
ISD
::
SRA
:
{
assert
(
Subtarget
.
getXLen
(
)
==
64
&&
"Combine should be 64-bit only"
)
;
if
(
!
DCI
.
isBeforeLegalize
(
)
)
break
;
SDValue
RHS
=
N
->
getOperand
(
1
)
;
if
(
N
->
getValueType
(
0
)
!=
MVT
::
i32
||
RHS
->
getOpcode
(
)
==
ISD
::
Constant
||
(
RHS
->
getOpcode
(
)
==
ISD
::
AssertZext
&&
cast
<
VTSDNode
>
(
RHS
->
getOperand
(
1
)
)
->
getVT
(
)
.
getSizeInBits
(
)
<=
5
)
)
break
;
SDValue
LHS
=
N
->
getOperand
(
0
)
;
SDLoc
DL
(
N
)
;
SDValue
NewRHS
=
DAG
.
getNode
(
ISD
::
AssertZext
,
DL
,
RHS
.
getValueType
(
)
,
RHS
,
DAG
.
getValueType
(
EVT
::
getIntegerVT
(
*
DAG
.
getContext
(
)
,
5
)
)
)
;
return
DCI
.
CombineTo
(
N
,
DAG
.
getNode
(
N
->
getOpcode
(
)
,
DL
,
LHS
.
getValueType
(
)
,
LHS
,
NewRHS
)
)
;
}
case
ISD
::
ANY_EXTEND
:
{
SDValue
Src
=
N
->
getOperand
(
0
)
;
if
(
N
->
getValueType
(
0
)
!=
MVT
::
i64
||
Src
.
getValueType
(
)
!=
MVT
::
i32
)
break
;
if
(
!
isVariableShift
(
Src
)
&&
!
(
Subtarget
.
hasStdExtM
(
)
&&
isVariableSDivUDivURem
(
Src
)
)
)
break
;
SDLoc
DL
(
N
)
;
return
DCI
.
CombineTo
(
N
,
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
DL
,
MVT
::
i64
,
Src
)
)
;
}
case
RISCVISD
::
SplitF64
:
{
SDValue
Op0
=
N
->
getOperand
(
0
)
;
if
(
Op0
->
getOpcode
(
)
!=
RISCVISD
::
BuildPairF64
)
break
;
return
DCI
.
CombineTo
(
N
,
Op0
.
getOperand
(
0
)
,
Op0
.
getOperand
(
1
)
)
;
}
}
return
SDValue
(
)
;
}
</s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> const MCExpr * ARMElfTargetObjectFile :: getDebugThreadLocalSymbol ( const MCSymbol * Sym ) const { return MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_ARM_TLSLDO , getContext ( ) ) ; } </s>

Describe a TLS variable address within debug info .


<s> const char * PPCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case PPCISD :: FSEL : return "PPCISD::FSEL" ; case PPCISD :: FCFID : return "PPCISD::FCFID" ; case PPCISD :: FCTIDZ : return "PPCISD::FCTIDZ" ; case PPCISD :: FCTIWZ : return "PPCISD::FCTIWZ" ; case PPCISD :: STFIWX : return "PPCISD::STFIWX" ; case PPCISD :: VMADDFP : return "PPCISD::VMADDFP" ; case PPCISD :: VNMSUBFP : return "PPCISD::VNMSUBFP" ; case PPCISD :: VPERM : return "PPCISD::VPERM" ; case PPCISD :: Hi : return "PPCISD::Hi" ; case PPCISD :: Lo : return "PPCISD::Lo" ; case PPCISD :: TOC_ENTRY : return "PPCISD::TOC_ENTRY" ; case PPCISD :: TOC_RESTORE : return "PPCISD::TOC_RESTORE" ; case PPCISD :: LOAD : return "PPCISD::LOAD" ; case PPCISD :: LOAD_TOC : return "PPCISD::LOAD_TOC" ; case PPCISD :: DYNALLOC : return "PPCISD::DYNALLOC" ; case PPCISD :: GlobalBaseReg : return "PPCISD::GlobalBaseReg" ; case PPCISD :: SRL : return "PPCISD::SRL" ; case PPCISD :: SRA : return "PPCISD::SRA" ; case PPCISD :: SHL : return "PPCISD::SHL" ; case PPCISD :: EXTSW_32 : return "PPCISD::EXTSW_32" ; case PPCISD :: STD_32 : return "PPCISD::STD_32" ; case PPCISD :: CALL_SVR4 : return "PPCISD::CALL_SVR4" ; case PPCISD :: CALL_Darwin : return "PPCISD::CALL_Darwin" ; case PPCISD :: NOP : return "PPCISD::NOP" ; case PPCISD :: MTCTR : return "PPCISD::MTCTR" ; case PPCISD :: BCTRL_Darwin : return "PPCISD::BCTRL_Darwin" ; case PPCISD :: BCTRL_SVR4 : return "PPCISD::BCTRL_SVR4" ; case PPCISD :: RET_FLAG : return "PPCISD::RET_FLAG" ; case PPCISD :: MFCR : return "PPCISD::MFCR" ; case PPCISD :: VCMP : return "PPCISD::VCMP" ; case PPCISD :: VCMPo : return "PPCISD::VCMPo" ; case PPCISD :: LBRX : return "PPCISD::LBRX" ; case PPCISD :: STBRX : return "PPCISD::STBRX" ; case PPCISD :: LARX : return "PPCISD::LARX" ; case PPCISD :: STCX : return "PPCISD::STCX" ; case PPCISD :: COND_BRANCH : return "PPCISD::COND_BRANCH" ; case PPCISD :: MFFS : return "PPCISD::MFFS" ; case PPCISD :: MTFSB0 : return "PPCISD::MTFSB0" ; case PPCISD :: MTFSB1 : return "PPCISD::MTFSB1" ; case PPCISD :: FADDRTZ : return "PPCISD::FADDRTZ" ; case PPCISD :: MTFSF : return "PPCISD::MTFSF" ; case PPCISD :: TC_RETURN : return "PPCISD::TC_RETURN" ; } } </s>

getTargetNodeName - This method returns the name of a target specific

PowerPC PPC 0 PPCISD::FSEL "PPCISD::FSEL" PPCISD::FCFID "PPCISD::FCFID" PPCISD::FCTIDZ "PPCISD::FCTIDZ" PPCISD::FCTIWZ "PPCISD::FCTIWZ" PPCISD::STFIWX "PPCISD::STFIWX" PPCISD::VMADDFP "PPCISD::VMADDFP" PPCISD::VNMSUBFP "PPCISD::VNMSUBFP" PPCISD::VPERM "PPCISD::VPERM" PPCISD::Hi "PPCISD::Hi" PPCISD::Lo "PPCISD::Lo" PPCISD::TOC_ENTRY "PPCISD::TOC_ENTRY" PPCISD::TOC_RESTORE "PPCISD::TOC_RESTORE" PPCISD::LOAD "PPCISD::LOAD" PPCISD::LOAD_TOC "PPCISD::LOAD_TOC" PPCISD::DYNALLOC "PPCISD::DYNALLOC" PPCISD::GlobalBaseReg "PPCISD::GlobalBaseReg" PPCISD::SRL "PPCISD::SRL" PPCISD::SRA "PPCISD::SRA" PPCISD::SHL "PPCISD::SHL" PPCISD::EXTSW_32 "PPCISD::EXTSW_32" PPCISD::STD_32 "PPCISD::STD_32" PPCISD::CALL_SVR4 "PPCISD::CALL_SVR4" PPCISD::CALL_Darwin "PPCISD::CALL_Darwin" PPCISD::NOP "PPCISD::NOP" PPCISD::MTCTR "PPCISD::MTCTR" PPCISD::BCTRL_Darwin "PPCISD::BCTRL_Darwin" PPCISD::BCTRL_SVR4 "PPCISD::BCTRL_SVR4" PPCISD::RET_FLAG "PPCISD::RET_FLAG" PPCISD::MFCR "PPCISD::MFCR" PPCISD::VCMP "PPCISD::VCMP" PPCISD::VCMPo "PPCISD::VCMPo" PPCISD::LBRX "PPCISD::LBRX" PPCISD::STBRX "PPCISD::STBRX" PPCISD::LARX "PPCISD::LARX" PPCISD::STCX "PPCISD::STCX" PPCISD::COND_BRANCH "PPCISD::COND_BRANCH" PPCISD::MFFS "PPCISD::MFFS" PPCISD::MTFSB0 "PPCISD::MTFSB0" PPCISD::MTFSB1 "PPCISD::MTFSB1" PPCISD::FADDRTZ "PPCISD::FADDRTZ" PPCISD::MTFSF "PPCISD::MTFSF" PPCISD::TC_RETURN "PPCISD::TC_RETURN"


<s> static std :: unique_ptr < AVROperand > CreateReg ( unsigned RegNum , SMLoc S , SMLoc E ) { return make_unique < AVROperand > ( RegNum , S , E ) ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> static void mips_sim_wait_regs ( struct mips_sim * state , rtx insn ) { mips_sim_insn = insn ; note_uses ( & PATTERN ( insn ) , mips_sim_wait_regs_1 , state ) ; } </s>

Advance simulation state STATE until all of INSN 's register dependencies are satisfied .


<s> void arc_split_move ( rtx * operands ) { machine_mode mode = GET_MODE ( operands [ 0 ] ) ; int i ; int swap = 0 ; rtx xop [ 4 ] ; if ( TARGET_DPFP ) { if ( arc_process_double_reg_moves ( operands ) ) return ; } if ( TARGET_LL64 && ( ( memory_operand ( operands [ 0 ] , mode ) && even_register_operand ( operands [ 1 ] , mode ) ) || ( memory_operand ( operands [ 1 ] , mode ) && even_register_operand ( operands [ 0 ] , mode ) ) ) ) { emit_move_insn ( operands [ 0 ] , operands [ 1 ] ) ; return ; } for ( i = 0 ; i < 2 ; i ++ ) { if ( MEM_P ( operands [ i ] ) && auto_inc_p ( XEXP ( operands [ i ] , 0 ) ) ) { rtx addr = XEXP ( operands [ i ] , 0 ) ; rtx r , o ; enum rtx_code code ; gcc_assert ( ! reg_overlap_mentioned_p ( operands [ 0 ] , addr ) ) ; switch ( GET_CODE ( addr ) ) { case PRE_DEC : o = GEN_INT ( - 8 ) ; goto pre_modify ; case PRE_INC : o = GEN_INT ( 8 ) ; goto pre_modify ; case PRE_MODIFY : o = XEXP ( XEXP ( addr , 1 ) , 1 ) ; pre_modify : code = PRE_MODIFY ; break ; case POST_DEC : o = GEN_INT ( - 8 ) ; goto post_modify ; case POST_INC : o = GEN_INT ( 8 ) ; goto post_modify ; case POST_MODIFY : o = XEXP ( XEXP ( addr , 1 ) , 1 ) ; post_modify : code = POST_MODIFY ; swap = 2 ; break ; default : gcc_unreachable ( ) ; } r = XEXP ( addr , 0 ) ; xop [ 0 + i ] = adjust_automodify_address_nv ( operands [ i ] , SImode , gen_rtx_fmt_ee ( code , Pmode , r , gen_rtx_PLUS ( Pmode , r , o ) ) , 0 ) ; xop [ 2 + i ] = adjust_automodify_address_nv ( operands [ i ] , SImode , plus_constant ( Pmode , r , 4 ) , 4 ) ; } else { xop [ 0 + i ] = operand_subword ( operands [ i ] , 0 , 0 , mode ) ; xop [ 2 + i ] = operand_subword ( operands [ i ] , 1 , 0 , mode ) ; } } if ( reg_overlap_mentioned_p ( xop [ 0 ] , xop [ 3 ] ) ) { swap = 2 ; gcc_assert ( ! reg_overlap_mentioned_p ( xop [ 2 ] , xop [ 1 ] ) ) ; } emit_move_insn ( xop [ 0 + swap ] , xop [ 1 + swap ] ) ; emit_move_insn ( xop [ 2 - swap ] , xop [ 3 - swap ] ) ; } </s>

operands 0 .. 1 are the operands of a 64 bit move instruction . split it into two moves with operands 2/3 and 4/5 .


<s>
MachineBasicBlock
*
ARMTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
const
TargetInstrInfo
*
TII
=
getTargetMachine
(
)
.
getInstrInfo
(
)
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
assert
(
false
&&
"Unexpected instr type to insert"
)
;
case
ARM
::
tMOVCCr
:
{
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
It
=
BB
;
++
It
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
sinkMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
BuildMI
(
BB
,
dl
,
TII
->
get
(
ARM
::
tBcc
)
)
.
addMBB
(
sinkMBB
)
.
addImm
(
MI
->
getOperand
(
3
)
.
getImm
(
)
)
.
addReg
(
MI
->
getOperand
(
4
)
.
getReg
(
)
)
;
F
->
insert
(
It
,
copy0MBB
)
;
F
->
insert
(
It
,
sinkMBB
)
;
for
(
MachineBasicBlock
::
succ_iterator
i
=
BB
->
succ_begin
(
)
,
e
=
BB
->
succ_end
(
)
;
i
!=
e
;
++
i
)
sinkMBB
->
addSuccessor
(
*
i
)
;
while
(
!
BB
->
succ_empty
(
)
)
BB
->
removeSuccessor
(
BB
->
succ_begin
(
)
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
sinkMBB
;
BuildMI
(
BB
,
dl
,
TII
->
get
(
ARM
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
F
->
DeleteMachineInstr
(
MI
)
;
return
BB
;
}
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


"Call frame pseudos should only be used for dynamic stack adjustment"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


"****** Hexagon Hardware Loop Fixup ******\n"

runOnMachineFunction - Emit the function body .


<s> static bool arc_can_follow_jump ( const rtx_insn * follower , const rtx_insn * followee ) { union { const rtx_insn * c ; rtx_insn * r ; } u ; u . c = follower ; if ( CROSSING_JUMP_P ( followee ) ) switch ( get_attr_type ( u . r ) ) { case TYPE_BRANCH : if ( get_attr_length ( u . r ) != 2 ) break ; case TYPE_BRCC : case TYPE_BRCC_NO_DELAY_SLOT : return false ; default : return true ; } return true ; } </s>

Without this , gcc.dg/tree-prof/bb-reorg.c fails to assemble when compiling with -O2 -freorder-blocks-and-partition -fprofile-use -D_PROFILE_USE ; delay branch scheduling then follows a crossing jump to redirect two breqs .


<s> static HOST_WIDE_INT riscv_stack_align ( HOST_WIDE_INT value ) { return RISCV_STACK_ALIGN ( value ) ; } </s>


<s> static void build_all ( function_builder & b , const char * signature , const function_group_info & group , mode_suffix_index mode_suffix_id , bool force_direct_overloads = false ) { for ( unsigned int pi = 0 ; group . preds [ pi ] != NUM_PREDS ; ++ pi ) for ( unsigned int ti = 0 ; ti == 0 || group . types [ ti ] [ 0 ] != NUM_TYPE_SUFFIXES ; ++ ti ) build_one ( b , signature , group , mode_suffix_id , ti , pi , force_direct_overloads ) ; } </s>

Add a function instance for every operand & & predicate & & args combination in GROUP . Take the function base name from GROUP & & operand suffix from operand_suffixes & & mode suffix from type_suffixes & & predication suffix from predication_suffixes . Use apply_predication to add in the predicate .


"Branch-taken block should post-dominate first candidate"

"Error in code produced by branch coalescing"


<s> const RegisterBankInfo :: InstructionMapping & X86RegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto Opc = MI . getOpcode ( ) ; if ( ! isPreISelGenericOpcode ( Opc ) || Opc == TargetOpcode :: G_PHI ) { const InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; } switch ( Opc ) { case TargetOpcode :: G_ADD : case TargetOpcode :: G_SUB : return getSameOperandsMapping ( MI , false ) ; break ; case TargetOpcode :: G_FADD : case TargetOpcode :: G_FSUB : case TargetOpcode :: G_FMUL : case TargetOpcode :: G_FDIV : return getSameOperandsMapping ( MI , true ) ; break ; default : break ; } unsigned NumOperands = MI . getNumOperands ( ) ; SmallVector < PartialMappingIdx , 4 > OpRegBankIdx ( NumOperands ) ; switch ( Opc ) { case TargetOpcode :: G_FPEXT : case TargetOpcode :: G_FCONSTANT : getInstrPartialMappingIdxs ( MI , MRI , true , OpRegBankIdx ) ; break ; case TargetOpcode :: G_TRUNC : case TargetOpcode :: G_ANYEXT : { auto & Op0 = MI . getOperand ( 0 ) ; auto & Op1 = MI . getOperand ( 1 ) ; const LLT Ty0 = MRI . getType ( Op0 . getReg ( ) ) ; const LLT Ty1 = MRI . getType ( Op1 . getReg ( ) ) ; bool isFPTrunc = ( Ty0 . getSizeInBits ( ) == 32 || Ty0 . getSizeInBits ( ) == 64 ) && Ty1 . getSizeInBits ( ) == 128 && Opc == TargetOpcode :: G_TRUNC ; bool isFPAnyExt = Ty0 . getSizeInBits ( ) == 128 && ( Ty1 . getSizeInBits ( ) == 32 || Ty1 . getSizeInBits ( ) == 64 ) && Opc == TargetOpcode :: G_ANYEXT ; getInstrPartialMappingIdxs ( MI , MRI , isFPTrunc || isFPAnyExt , OpRegBankIdx ) ; } break ; default : getInstrPartialMappingIdxs ( MI , MRI , false , OpRegBankIdx ) ; break ; } SmallVector < const ValueMapping * , 8 > OpdsMapping ( NumOperands ) ; if ( ! getInstrValueMapping ( MI , OpRegBankIdx , OpdsMapping ) ) return getInvalidInstructionMapping ( ) ; return getInstructionMapping ( DefaultMappingID , 1 , getOperandsMapping ( OpdsMapping ) , NumOperands ) ; } </s>

Get the mapping of the different operands of MI on the register bank .


"TOY DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


"\t! The vector %02d is a critical isr !\n"

Function to emit isr jump table section .


Relax the instruction in the given fragment to the next wider instruction .


"Can only insert epilog into returning blocks"


"should only be seeing stack pointer offset relative FrameIndex"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> unsigned PPCFastISel :: fastEmitInst_ri ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , uint64_t Imm ) { if ( MachineInstOpcode == PPC :: ADDI ) MRI . setRegClass ( Op0 , & PPC :: GPRC_and_GPRC_NOR0RegClass ) ; else if ( MachineInstOpcode == PPC :: ADDI8 ) MRI . setRegClass ( Op0 , & PPC :: G8RC_and_G8RC_NOX0RegClass ) ; const TargetRegisterClass * UseRC = ( RC == & PPC :: GPRCRegClass ? & PPC :: GPRC_and_GPRC_NOR0RegClass : ( RC == & PPC :: G8RCRegClass ? & PPC :: G8RC_and_G8RC_NOX0RegClass : RC ) ) ; return FastISel :: fastEmitInst_ri ( MachineInstOpcode , UseRC , Op0 , Imm ) ; } </s>

Emit a MachineInstr with a register operand , an immediate , and a result register in the given register class .


<s> bool MipsLongBranch :: runOnMachineFunction ( MachineFunction & F ) { if ( ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) && TM . getSubtarget < MipsSubtarget > ( ) . isABI_O32 ( ) && F . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; bool IsPIC = ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) ; SmallVector < MBBInfo , 16 > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; if ( ! ForceLongBranch ) { int64_t Offset = computeOffset ( I -> Br ) ; if ( ( I -> Br -> isConditionalBranch ( ) || IsPIC ) && isInt < 16 > ( Offset / 4 ) ) continue ; if ( I -> Br -> isUnconditionalBranch ( ) && ! IsPIC && isInt < 26 > ( Offset / 4 ) ) continue ; } expandToLongBranch ( * I ) ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( EverMadeChange ) MF -> RenumberBlocks ( ) ; return true ; } </s>


Create the va_list data type . We keep 3 pointers , and two offsets . Two pointers are to the overflow area , which starts at the CFA . One of these is constant , for addressing into the GPR save area below it . The other is advanced up the stack through the overflow region . The third pointer is to the GPR save area . Since the FPR save area is just below it , we can address FPR slots off this pointer . We also keep two one-byte offsets , which are to be subtracted from the constant pointers to yield addresses in the GPR and FPR save areas . These are downcounted as float or non-float arguments are used , and when they get to zero , the argument must be obtained from the overflow region . If ! EABI_FLOAT_VARARGS_P , then no FPR save area exists , and a single pointer is enough . It 's started at the GPR save area , and is advanced , period . Note that the GPR save area is not constant size , due to optimization in the prologue . Hence , we ca n't use a design with two pointers and two offsets , although we could have designed this with two pointers and three offsets .


<s>
void
ARMAsmBackend
::
relaxInstruction
(
const
MCInst
&
Inst
,
MCInst
&
Res
)
const
{
unsigned
RelaxedOp
=
getRelaxedOpcode
(
Inst
.
getOpcode
(
)
)
;
if
(
RelaxedOp
==
Inst
.
getOpcode
(
)
)
{
SmallString
<
256
>
Tmp
;
raw_svector_ostream
OS
(
Tmp
)
;
Inst
.
dump_pretty
(
OS
)
;
OS
<<
"\n"
;
report_fatal_error
(
"unexpected instruction to relax: "
+
OS
.
str
(
)
)
;
}
Res
=
Inst
;
Res
.
setOpcode
(
RelaxedOp
)
;
}
</s>

ARM
ARM
256
"\n"
"unexpected instruction to relax: "


<s> bool AArch64TTIImpl :: getTgtMemIntrinsic ( IntrinsicInst * Inst , MemIntrinsicInfo & Info ) { switch ( Inst -> getIntrinsicID ( ) ) { default : break ; case Intrinsic :: aarch64_neon_ld2 : case Intrinsic :: aarch64_neon_ld3 : case Intrinsic :: aarch64_neon_ld4 : Info . ReadMem = true ; Info . WriteMem = false ; Info . IsSimple = true ; Info . NumMemRefs = 1 ; Info . PtrVal = Inst -> getArgOperand ( 0 ) ; break ; case Intrinsic :: aarch64_neon_st2 : case Intrinsic :: aarch64_neon_st3 : case Intrinsic :: aarch64_neon_st4 : Info . ReadMem = false ; Info . WriteMem = true ; Info . IsSimple = true ; Info . NumMemRefs = 1 ; Info . PtrVal = Inst -> getArgOperand ( Inst -> getNumArgOperands ( ) - 1 ) ; break ; } switch ( Inst -> getIntrinsicID ( ) ) { default : return false ; case Intrinsic :: aarch64_neon_ld2 : case Intrinsic :: aarch64_neon_st2 : Info . MatchingId = VECTOR_LDST_TWO_ELEMENTS ; break ; case Intrinsic :: aarch64_neon_ld3 : case Intrinsic :: aarch64_neon_st3 : Info . MatchingId = VECTOR_LDST_THREE_ELEMENTS ; break ; case Intrinsic :: aarch64_neon_ld4 : case Intrinsic :: aarch64_neon_st4 : Info . MatchingId = VECTOR_LDST_FOUR_ELEMENTS ; break ; } return true ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> static void nios2_asm_function_prologue ( FILE * file , HOST_WIDE_INT size ATTRIBUTE_UNUSED ) { if ( flag_verbose_asm || flag_debug_asm ) { nios2_compute_frame_layout ( ) ; nios2_dump_frame_layout ( file ) ; } } </s>


<s> bool isToken ( ) const override { return Kind == k_Token ; } </s>


<s> bool PPCTargetLowering :: isZExtFree ( SDValue Val , EVT VT2 ) const { if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( Val ) ) { EVT MemVT = LD -> getMemoryVT ( ) ; if ( ( MemVT == MVT :: i1 || MemVT == MVT :: i8 || MemVT == MVT :: i16 || ( Subtarget . isPPC64 ( ) && MemVT == MVT :: i32 ) ) && ( LD -> getExtensionType ( ) == ISD :: NON_EXTLOAD || LD -> getExtensionType ( ) == ISD :: ZEXTLOAD ) ) return true ; } return TargetLowering :: isZExtFree ( Val , VT2 ) ; } </s>

Return true if zero-extending the specific node Val to type VT2 is free ( either because it 's implicitly zero-extended such as ARM ldrb / ldrh or because it 's folded such as X86 zero-extending loads ) .


"Pseudo instructions must not be bundled!"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
const
char
*
MipsAsmPrinter
::
getCurrentABIString
(
)
const
{
switch
(
Subtarget
->
getTargetABI
(
)
)
{
case
MipsSubtarget
::
O32
:
return
"abi32"
;
case
MipsSubtarget
::
N32
:
return
"abiN32"
;
case
MipsSubtarget
::
N64
:
return
"abi64"
;
case
MipsSubtarget
::
EABI
:
return
"eabi32"
;
default
:
llvm_unreachable
(
"Unknown Mips ABI"
)
;
;
}
}
</s>


<s>
PIC16Section
*
PIC16Section
::
Create
(
StringRef
Name
,
PIC16SectionType
Ty
,
StringRef
Address
,
int
Color
,
MCContext
&
Ctx
)
{
SectionKind
K
;
switch
(
Ty
)
{
default
:
llvm_unreachable
(
"can not create unknown section type"
)
;
case
UDATA_OVR
:
{
K
=
SectionKind
::
getThreadBSS
(
)
;
break
;
}
case
UDATA_SHR
:
case
UDATA
:
{
K
=
SectionKind
::
getBSS
(
)
;
break
;
}
case
ROMDATA
:
case
IDATA
:
{
K
=
SectionKind
::
getMetadata
(
)
;
break
;
}
case
CODE
:
{
K
=
SectionKind
::
getText
(
)
;
break
;
}
}
char
*
NameCopy
=
static_cast
<
char
*
>
(
Ctx
.
Allocate
(
Name
.
size
(
)
,
1
)
)
;
memcpy
(
NameCopy
,
Name
.
data
(
)
,
Name
.
size
(
)
)
;
char
*
AddressCopy
=
static_cast
<
char
*
>
(
Ctx
.
Allocate
(
Address
.
size
(
)
,
1
)
)
;
memcpy
(
AddressCopy
,
Address
.
data
(
)
,
Address
.
size
(
)
)
;
PIC16Section
*
S
=
new
(
Ctx
)
PIC16Section
(
StringRef
(
NameCopy
,
Name
.
size
(
)
)
,
K
,
StringRef
(
AddressCopy
,
Address
.
size
(
)
)
,
Color
)
;
S
->
T
=
Ty
;
return
S
;
}
</s>

Construct a unary instruction , given the opcode and an operand .


"register_move_cost %s from %s to %s = %d\n"

Implements REGISTER_MOVE_COST . We make impossible moves prohibitively expensive , like trying to put QIs in r2/r3 ( there are no opcodes to do that ) . We also discourage use of mem * registers since they 're really memory .


<s> bool AMDGPUTargetLowering :: isCheapToSpeculateCtlz ( ) const { return true ; } </s>

Return true if it is cheap to speculate a call to intrinsic ctlz .


<s>
unsigned
PPCVSXSwapRemoval
::
lookThruCopyLike
(
unsigned
SrcReg
,
unsigned
VecIdx
)
{
MachineInstr
*
MI
=
MRI
->
getVRegDef
(
SrcReg
)
;
if
(
!
MI
->
isCopyLike
(
)
)
return
SrcReg
;
unsigned
CopySrcReg
;
if
(
MI
->
isCopy
(
)
)
CopySrcReg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
else
{
assert
(
MI
->
isSubregToReg
(
)
&&
"bad opcode for lookThruCopyLike"
)
;
CopySrcReg
=
MI
->
getOperand
(
2
)
.
getReg
(
)
;
}
if
(
!
TargetRegisterInfo
::
isVirtualRegister
(
CopySrcReg
)
)
{
SwapVector
[
VecIdx
]
.
MentionsPhysVR
=
1
;
return
CopySrcReg
;
}
return
lookThruCopyLike
(
CopySrcReg
,
VecIdx
)
;
}
</s>

Returns the original SrcReg unless it is the target of a copy-like operation , in which case we chain backwards through all such operations to the ultimate source register .


<s> int X86TTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return ~ 0U ; if ( BitSize > 128 ) return TTI :: TCC_Free ; if ( Imm == 0 ) return TTI :: TCC_Free ; APInt ImmVal = Imm ; if ( BitSize % 64 != 0 ) ImmVal = Imm . sext ( alignTo ( BitSize , 64 ) ) ; int Cost = 0 ; for ( unsigned ShiftVal = 0 ; ShiftVal < BitSize ; ShiftVal += 64 ) { APInt Tmp = ImmVal . ashr ( ShiftVal ) . sextOrTrunc ( 64 ) ; int64_t Val = Tmp . getSExtValue ( ) ; Cost += getIntImmCost ( Val ) ; } return std :: max ( 1 , Cost ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> static opt_machine_mode aarch64_get_mask_mode ( machine_mode mode ) { unsigned int vec_flags = aarch64_classify_vector_mode ( mode ) ; if ( vec_flags & VEC_SVE_DATA ) return aarch64_sve_pred_mode ( mode ) ; return default_get_mask_mode ( mode ) ; } </s>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < HSAILSubtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> const uint16_t * PPCRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( Subtarget . isDarwinABI ( ) ) return Subtarget . isPPC64 ( ) ? CSR_Darwin64_SaveList : CSR_Darwin32_SaveList ; if ( ! Subtarget . isPPC64 ( ) ) CRSpillFrameIdx = 0 ; return Subtarget . isPPC64 ( ) ? CSR_SVR464_SaveList : CSR_SVR432_SaveList ; } </s>


<s> static bool spu_pass_by_reference ( cumulative_args_t cum ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , const_tree type , bool named ATTRIBUTE_UNUSED ) { return type && TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ; } </s>

Variable sized types are passed by reference .


<s> bool SIPeepholeSDWA :: runOnMachineFunction ( MachineFunction & MF ) { const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; if ( ! ST . hasSDWA ( ) || skipFunction ( MF . getFunction ( ) ) ) return false ; MRI = & MF . getRegInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; TII = ST . getInstrInfo ( ) ; bool Ret = false ; for ( MachineBasicBlock & MBB : MF ) { bool Changed = false ; do { matchSDWAOperands ( MBB ) ; for ( const auto & OperandPair : SDWAOperands ) { const auto & Operand = OperandPair . second ; MachineInstr * PotentialMI = Operand -> potentialToConvert ( TII ) ; if ( PotentialMI && ( PotentialMI -> getOpcode ( ) == AMDGPU :: V_ADD_CO_U32_e64 || PotentialMI -> getOpcode ( ) == AMDGPU :: V_SUB_CO_U32_e64 ) ) pseudoOpConvertToVOP2 ( * PotentialMI , ST ) ; } SDWAOperands . clear ( ) ; matchSDWAOperands ( MBB ) ; for ( const auto & OperandPair : SDWAOperands ) { const auto & Operand = OperandPair . second ; MachineInstr * PotentialMI = Operand -> potentialToConvert ( TII ) ; if ( PotentialMI && isConvertibleToSDWA ( * PotentialMI , ST ) ) { PotentialMatches [ PotentialMI ] . push_back ( Operand . get ( ) ) ; } } for ( auto & PotentialPair : PotentialMatches ) { MachineInstr & PotentialMI = * PotentialPair . first ; convertToSDWA ( PotentialMI , PotentialPair . second ) ; } PotentialMatches . clear ( ) ; SDWAOperands . clear ( ) ; Changed = ! ConvertedInstructions . empty ( ) ; if ( Changed ) Ret = true ; while ( ! ConvertedInstructions . empty ( ) ) legalizeScalarOperands ( * ConvertedInstructions . pop_back_val ( ) , ST ) ; } while ( Changed ) ; } return Ret ; } </s>


"Can only insert epilog into returning blocks"


<s> X86TargetLowering :: ConstraintType X86TargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'R' : case 'q' : case 'Q' : case 'f' : case 't' : case 'u' : case 'y' : case 'x' : case 'Y' : case 'l' : return C_RegisterClass ; case 'a' : case 'b' : case 'c' : case 'd' : case 'S' : case 'D' : case 'A' : return C_Register ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'G' : case 'C' : case 'e' : case 'Z' : return C_Other ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


"switch -mcpu=%s conflicts with -march=%s switch"

"assembler does not support -mabi=ilp32"

"return address signing is only supported for -mabi=lp64"


<s> void HexagonInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ) ; if ( Hexagon :: IntRegsRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: S2_storeri_io ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( Hexagon :: DoubleRegsRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: S2_storerd_io ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( Hexagon :: PredRegsRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: STriw_pred ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else { llvm_unreachable ( "Unimplemented" ) ; } } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> void WasmPEI :: assignCalleeSavedSpillSlots ( MachineFunction & F , const BitVector & SavedRegs ) { MinCSFrameIndex = INT_MAX ; MaxCSFrameIndex = 0 ; if ( SavedRegs . empty ( ) ) return ; const TargetRegisterInfo * RegInfo = F . getSubtarget ( ) . getRegisterInfo ( ) ; const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( & F ) ; std :: vector < CalleeSavedInfo > CSI ; for ( unsigned i = 0 ; CSRegs [ i ] ; ++ i ) { unsigned Reg = CSRegs [ i ] ; if ( SavedRegs . test ( Reg ) ) CSI . push_back ( CalleeSavedInfo ( Reg ) ) ; } const TargetFrameLowering * TFI = F . getSubtarget ( ) . getFrameLowering ( ) ; MachineFrameInfo * MFI = F . getFrameInfo ( ) ; if ( ! TFI -> assignCalleeSavedSpillSlots ( F , RegInfo , CSI ) ) { if ( CSI . empty ( ) ) return ; unsigned NumFixedSpillSlots ; const TargetFrameLowering :: SpillSlot * FixedSpillSlots = TFI -> getCalleeSavedSpillSlots ( NumFixedSpillSlots ) ; for ( std :: vector < CalleeSavedInfo > :: iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { unsigned Reg = I -> getReg ( ) ; const TargetRegisterClass * RC = RegInfo -> getMinimalPhysRegClass ( Reg ) ; int FrameIdx ; if ( RegInfo -> hasReservedSpillSlot ( F , Reg , FrameIdx ) ) { I -> setFrameIdx ( FrameIdx ) ; continue ; } const TargetFrameLowering :: SpillSlot * FixedSlot = FixedSpillSlots ; while ( FixedSlot != FixedSpillSlots + NumFixedSpillSlots && FixedSlot -> Reg != Reg ) ++ FixedSlot ; if ( FixedSlot == FixedSpillSlots + NumFixedSpillSlots ) { unsigned Align = RC -> getAlignment ( ) ; unsigned StackAlign = TFI -> getStackAlignment ( ) ; Align = std :: min ( Align , StackAlign ) ; FrameIdx = MFI -> CreateStackObject ( RC -> getSize ( ) , Align , true ) ; if ( ( unsigned ) FrameIdx < MinCSFrameIndex ) MinCSFrameIndex = FrameIdx ; if ( ( unsigned ) FrameIdx > MaxCSFrameIndex ) MaxCSFrameIndex = FrameIdx ; } else { FrameIdx = MFI -> CreateFixedSpillStackObject ( RC -> getSize ( ) , FixedSlot -> Offset ) ; } I -> setFrameIdx ( FrameIdx ) ; } } MFI -> setCalleeSavedInfo ( CSI ) ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> std :: unique_ptr < SICacheControl > SICacheControl :: create ( const GCNSubtarget & ST ) { GCNSubtarget :: Generation Generation = ST . getGeneration ( ) ; if ( Generation <= AMDGPUSubtarget :: SOUTHERN_ISLANDS ) return std :: make_unique < SIGfx6CacheControl > ( ST ) ; if ( Generation < AMDGPUSubtarget :: GFX10 ) return std :: make_unique < SIGfx7CacheControl > ( ST ) ; return std :: make_unique < SIGfx10CacheControl > ( ST , ST . isCuModeEnabled ( ) ) ; } </s>


<s> bool isImm ( ) const { return Kind == k_Immediate ; } </s>


<s> static rtx generate_set_vrsave ( rtx reg , rs6000_stack_t * info , int epiloguep ) { int nclobs , i ; rtx insn , clobs [ TOTAL_ALTIVEC_REGS + 1 ] ; rtx vrsave = gen_rtx_REG ( SImode , VRSAVE_REGNO ) ; clobs [ 0 ] = gen_rtx_SET ( vrsave , gen_rtx_UNSPEC_VOLATILE ( SImode , gen_rtvec ( 2 , reg , vrsave ) , UNSPECV_SET_VRSAVE ) ) ; nclobs = 1 ; for ( i = FIRST_ALTIVEC_REGNO ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( info -> vrsave_mask & ALTIVEC_REG_BIT ( i ) ) { if ( ! epiloguep || call_used_regs [ i ] ) clobs [ nclobs ++ ] = gen_hard_reg_clobber ( V4SImode , i ) ; else { rtx reg = gen_rtx_REG ( V4SImode , i ) ; clobs [ nclobs ++ ] = gen_rtx_SET ( reg , gen_rtx_UNSPEC ( V4SImode , gen_rtvec ( 1 , reg ) , 27 ) ) ; } } insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nclobs ) ) ; for ( i = 0 ; i < nclobs ; ++ i ) XVECEXP ( insn , 0 , i ) = clobs [ i ] ; return insn ; } </s>

Returns an insn that has a vrsave set operation with the appropriate CLOBBERs .


<s> static void mips_block_move_straight ( rtx dest , rtx src , HOST_WIDE_INT length ) { HOST_WIDE_INT offset , delta ; unsigned HOST_WIDE_INT bits ; int i ; machine_mode mode ; rtx * regs ; if ( ! ISA_HAS_LWL_LWR ) bits = MIN ( BITS_PER_WORD , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) ) ; else { if ( MEM_ALIGN ( src ) == BITS_PER_WORD / 2 && MEM_ALIGN ( dest ) == BITS_PER_WORD / 2 ) bits = BITS_PER_WORD / 2 ; else bits = BITS_PER_WORD ; } mode = int_mode_for_size ( bits , 0 ) . require ( ) ; delta = bits / BITS_PER_UNIT ; regs = XALLOCAVEC ( rtx , length / delta ) ; for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) { regs [ i ] = gen_reg_rtx ( mode ) ; if ( MEM_ALIGN ( src ) >= bits ) mips_emit_move ( regs [ i ] , adjust_address ( src , mode , offset ) ) ; else { rtx part = adjust_address ( src , BLKmode , offset ) ; set_mem_size ( part , delta ) ; if ( ! mips_expand_ext_as_unaligned_load ( regs [ i ] , part , bits , 0 , 0 ) ) gcc_unreachable ( ) ; } } for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) if ( MEM_ALIGN ( dest ) >= bits ) mips_emit_move ( adjust_address ( dest , mode , offset ) , regs [ i ] ) ; else { rtx part = adjust_address ( dest , BLKmode , offset ) ; set_mem_size ( part , delta ) ; if ( ! mips_expand_ins_as_unaligned_store ( part , regs [ i ] , bits , 0 ) ) gcc_unreachable ( ) ; } if ( offset < length ) { src = adjust_address ( src , BLKmode , offset ) ; dest = adjust_address ( dest , BLKmode , offset ) ; move_by_pieces ( dest , src , length - offset , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) , RETURN_BEGIN ) ; } } </s>

Emit straight-line code to move LENGTH bytes from SRC to DEST . Assume that the areas do not overlap .


<s> void AMDGPUHSATargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; TextSection = AMDGPU :: getHSATextSection ( Ctx ) ; } </s>

This method must be called before any actual lowering is done .


<s> unsigned getNumFixupKinds ( ) const override { return 1 ; } </s>

Get the number of target specific fixup kinds .


<s> void X86InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB . getParent ( ) ; bool isAligned = ( RI . getStackAlignment ( ) >= 16 ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , TM ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) , DestReg ) , FrameIdx ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> void SparcFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


<s>
void
A57ChainingConstraint
::
apply
(
PBQPRAGraph
&
G
)
{
const
MachineFunction
&
MF
=
G
.
getMetadata
(
)
.
MF
;
LiveIntervals
&
LIs
=
G
.
getMetadata
(
)
.
LIS
;
TRI
=
MF
.
getTarget
(
)
.
getSubtargetImpl
(
)
->
getRegisterInfo
(
)
;
DEBUG
(
MF
.
dump
(
)
)
;
for
(
const
auto
&
MBB
:
MF
)
{
Chains
.
clear
(
)
;
for
(
const
auto
&
MI
:
MBB
)
{
for
(
auto
r
:
Chains
)
{
SmallVector
<
unsigned
,
8
>
toDel
;
if
(
regJustKilledBefore
(
LIs
,
r
,
MI
)
)
{
DEBUG
(
dbgs
(
)
<<
"Killing chain "
<<
PrintReg
(
r
,
TRI
)
<<
" at "
;
MI
.
print
(
dbgs
(
)
)
;
)
;
toDel
.
push_back
(
r
)
;
}
while
(
!
toDel
.
empty
(
)
)
{
Chains
.
remove
(
toDel
.
back
(
)
)
;
toDel
.
pop_back
(
)
;
}
}
switch
(
MI
.
getOpcode
(
)
)
{
case
AArch64
::
FMSUBSrrr
:
case
AArch64
::
FMADDSrrr
:
case
AArch64
::
FNMSUBSrrr
:
case
AArch64
::
FNMADDSrrr
:
case
AArch64
::
FMSUBDrrr
:
case
AArch64
::
FMADDDrrr
:
case
AArch64
::
FNMSUBDrrr
:
case
AArch64
::
FNMADDDrrr
:
{
unsigned
Rd
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
unsigned
Ra
=
MI
.
getOperand
(
3
)
.
getReg
(
)
;
if
(
addIntraChainConstraint
(
G
,
Rd
,
Ra
)
)
addInterChainConstraint
(
G
,
Rd
,
Ra
)
;
break
;
}
case
AArch64
::
FMLAv2f32
:
case
AArch64
::
FMLSv2f32
:
{
unsigned
Rd
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
addInterChainConstraint
(
G
,
Rd
,
Rd
)
;
break
;
}
default
:
break
;
}
}
}
}
</s>

Apply the profile inference algorithm for a given function .


<s> bool AlphaTargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createAlphaBranchSelectionPass ( ) ) ; return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void AMDGPUPromoteKernelArguments :: enqueueUsers ( Value * Ptr ) { SmallVector < User * > PtrUsers ( Ptr -> users ( ) ) ; while ( ! PtrUsers . empty ( ) ) { Instruction * U = dyn_cast < Instruction > ( PtrUsers . pop_back_val ( ) ) ; if ( ! U ) continue ; switch ( U -> getOpcode ( ) ) { default : break ; case Instruction :: Load : { LoadInst * LD = cast < LoadInst > ( U ) ; if ( LD -> getPointerOperand ( ) -> stripInBoundsOffsets ( ) == Ptr && ! AMDGPU :: isClobberedInFunction ( LD , MSSA , AA ) ) Ptrs . push_back ( LD ) ; break ; } case Instruction :: GetElementPtr : case Instruction :: AddrSpaceCast : case Instruction :: BitCast : if ( U -> getOperand ( 0 ) -> stripInBoundsOffsets ( ) == Ptr ) PtrUsers . append ( U -> user_begin ( ) , U -> user_end ( ) ) ; break ; } } } </s>

Enqueue the users of this instruction in the visit worklist .

AMDGPU AMDGPU AMDGPU::isClobberedInFunction 0


<s> bool mayNeedRelaxation ( MCInst const & Inst , MCSubtargetInfo const & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


"ARM64 Collect Linker Optimization Hint (LOH)"

getPassName - Return a nice clean name for a pass .


<s> inline set_of_reg rx_find_set_of_reg ( rtx reg , rtx_insn * insn , F stepfunc , bool ignore_reg_reg_copies = false ) { set_of_reg result ; result . insn = insn ; result . set_rtx = NULL_RTX ; result . set_src = NULL_RTX ; if ( ! REG_P ( reg ) || insn == NULL_RTX ) return result ; for ( rtx_insn * i = stepfunc ( insn ) ; i != NULL_RTX ; i = stepfunc ( i ) ) { if ( BARRIER_P ( i ) ) break ; if ( ! INSN_P ( i ) || DEBUG_INSN_P ( i ) ) continue ; if ( reg_set_p ( reg , i ) ) { if ( CALL_P ( i ) ) break ; result . insn = i ; result . set_rtx = set_of ( reg , i ) ; if ( result . set_rtx == NULL_RTX || GET_CODE ( result . set_rtx ) != SET ) break ; result . set_src = XEXP ( result . set_rtx , 1 ) ; if ( ignore_reg_reg_copies && REG_P ( result . set_src ) ) { reg = result . set_src ; continue ; } if ( ignore_reg_reg_copies && SUBREG_P ( result . set_src ) && REG_P ( SUBREG_REG ( result . set_src ) ) ) { reg = SUBREG_REG ( result . set_src ) ; continue ; } break ; } } if ( result . set_src != NULL && result . set_rtx == NULL ) result . set_src = NULL ; return result ; } </s>

FIXME : Copy-pasta from SH . Move to rtl.h . Given a reg rtx and a start insn , try to find the insn that sets the specified reg by using the specified insn stepping function , such as 'prev_nonnote_nondebug_insn_bb ' . When the insn is found , try to extract the rtx of the reg set .


<s> static unsigned getHashValue ( const SlotWithTag & V ) { return hash_combine ( DenseMapInfo < int > :: getHashValue ( V . FI ) , DenseMapInfo < int > :: getHashValue ( V . Tag ) ) ; } </s>

Using name and line to get hash value . It should already be mostly unique .


"-malign-loops=%d is not between 1 and %d"

"-malign-jumps=%d is not between 1 and %d"

"-malign-functions=%d is not between 1 and %d"

Set global variables as needed for the options enabled .


<s> SDValue LanaiSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; if ( ! ConstantSize ) return SDValue ( ) ; return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .


<s> bool AArch64FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( MF . hasEHFunclets ( ) ) return true ; if ( MFI . hasCalls ( ) && MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) return true ; if ( MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || RegInfo -> needsStackRealignment ( MF ) ) return true ; if ( ! MFI . isMaxCallFrameSizeComputed ( ) || MFI . getMaxCallFrameSize ( ) > DefaultSafeSPDisplacement ) return true ; if ( MF . hasLocalEscape ( ) ) return true ; return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool ARMBaseTargetMachine :: addPreSched2 ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt :: None ) { if ( ! Subtarget . isThumb1Only ( ) ) PM . add ( createARMLoadStoreOptimizationPass ( ) ) ; if ( Subtarget . hasNEON ( ) ) PM . add ( createNEONMoveFixPass ( ) ) ; } PM . add ( createARMExpandPseudoPass ( ) ) ; if ( OptLevel != CodeGenOpt :: None ) { if ( ! Subtarget . isThumb1Only ( ) ) PM . add ( createIfConverterPass ( ) ) ; } if ( Subtarget . isThumb2 ( ) ) PM . add ( createThumb2ITBlockPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> bool shouldInsertFencesForAtomic ( const Instruction * I ) const override { return true ; } </s>

Helper functions for atomic operations .


<s> bool aarch64_member_type_forces_blk ( const_tree field_or_array , machine_mode mode ) { const_tree type = TREE_TYPE ( field_or_array ) ; unsigned int num_zr , num_pr ; if ( aarch64_sve :: builtin_type_p ( type , & num_zr , & num_pr ) && num_pr != 0 ) { if ( TREE_CODE ( field_or_array ) == ARRAY_TYPE ) return ! simple_cst_equal ( TYPE_SIZE ( field_or_array ) , TYPE_SIZE ( type ) ) ; return mode == VOIDmode ; } return default_member_type_forces_blk ( field_or_array , mode ) ; } </s>


<s> virtual EVT getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( VT . isVector ( ) ) return MVT :: getVectorVT ( MVT :: i1 , VT . getVectorNumElements ( ) ) ; return MVT :: i1 ; } </s>

Return the value type to use for ISD : :SETCC .


<s> unsigned SIRegisterInfo :: getRegPressureSetLimit ( const MachineFunction & MF , unsigned Idx ) const { const AMDGPUSubtarget & STI = MF . getSubtarget < AMDGPUSubtarget > ( ) ; unsigned SGPRLimit = getNumSGPRsAllowed ( STI . getGeneration ( ) , STI . getMaxWavesPerCU ( ) ) ; unsigned VGPRLimit = getNumVGPRsAllowed ( STI . getMaxWavesPerCU ( ) ) ; for ( regclass_iterator I = regclass_begin ( ) , E = regclass_end ( ) ; I != E ; ++ I ) { unsigned NumSubRegs = std :: max ( ( int ) ( * I ) -> getSize ( ) / 4 , 1 ) ; unsigned Limit ; if ( isSGPRClass ( * I ) ) { Limit = SGPRLimit / NumSubRegs ; } else { Limit = VGPRLimit / NumSubRegs ; } const int * Sets = getRegClassPressureSets ( * I ) ; assert ( Sets ) ; for ( unsigned i = 0 ; Sets [ i ] != - 1 ; ++ i ) { if ( Sets [ i ] == ( int ) Idx ) return Limit ; } } return 256 ; } </s>

Get the register unit pressure limit for this dimension .


<s> bool M680x0FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) && ! MF . getInfo < M680x0MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> void MBlazeInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; BuildMI ( MBB , I , DL , get ( MBlaze :: SWI ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addImm ( 0 ) . addFrameIndex ( FI ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"DCPU16 Assembly Printer"
;
}
</s>


<s> void assignValueToReg ( Register ValVReg , Register PhysReg , CCValAssign & VA ) override { MIB . addUse ( PhysReg ) ; MIRBuilder . buildCopy ( PhysReg , ValVReg ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> bool HexagonAsmParser :: isLabel ( AsmToken & Token ) { MCAsmLexer & Lexer = getLexer ( ) ; AsmToken const & Second = Lexer . getTok ( ) ; AsmToken Third = Lexer . peekTok ( ) ; StringRef String = Token . getString ( ) ; if ( Token . is ( AsmToken :: TokenKind :: LCurly ) || Token . is ( AsmToken :: TokenKind :: RCurly ) ) return false ; if ( String . lower ( ) == "vwhist256" && Second . is ( AsmToken :: Colon ) && Third . getString ( ) . lower ( ) == "sat" ) return false ; if ( ! Token . is ( AsmToken :: TokenKind :: Identifier ) ) return true ; if ( ! matchRegister ( String . lower ( ) ) ) return true ; assert ( Second . is ( AsmToken :: Colon ) ) ; StringRef Raw ( String . data ( ) , Third . getString ( ) . data ( ) - String . data ( ) + Third . getString ( ) . size ( ) ) ; std :: string Collapsed = std :: string ( Raw ) ; llvm :: erase_if ( Collapsed , isSpace ) ; StringRef Whole = Collapsed ; std :: pair < StringRef , StringRef > DotSplit = Whole . split ( '.' ) ; if ( ! matchRegister ( DotSplit . first . lower ( ) ) ) return true ; return false ; } </s>

Returns true if the MachineInstr represents a label .


<s> static int get_reservation_flags ( enum attr_units units ) { switch ( units ) { case UNITS_D : case UNITS_D_ADDR : return RESERVATION_FLAG_D ; case UNITS_L : return RESERVATION_FLAG_L ; case UNITS_S : return RESERVATION_FLAG_S ; case UNITS_M : return RESERVATION_FLAG_M ; case UNITS_LS : return RESERVATION_FLAG_LS ; case UNITS_DL : return RESERVATION_FLAG_DL ; case UNITS_DS : return RESERVATION_FLAG_DS ; case UNITS_DLS : return RESERVATION_FLAG_DLS ; default : return 0 ; } } </s>

Translate UNITS into a bitmask of units we can reserve for this insn .


<s> static bool chain_already_loaded ( rtx_insn * last ) { for ( ; last != NULL ; last = PREV_INSN ( last ) ) { if ( NONJUMP_INSN_P ( last ) ) { rtx patt = PATTERN ( last ) ; if ( GET_CODE ( patt ) == SET ) { rtx lhs = XEXP ( patt , 0 ) ; if ( REG_P ( lhs ) && REGNO ( lhs ) == STATIC_CHAIN_REGNUM ) return true ; } } } return false ; } </s>

Return TRUE iff the sequence ending in LAST sets the static chain .


<s> int double_memory_operand ( rtx op , machine_mode mode ) { rtx addr ; if ( GET_CODE ( op ) != MEM || ! memory_operand ( op , mode ) ) { if ( reload_in_progress && GET_CODE ( op ) == REG && REGNO ( op ) >= FIRST_PSEUDO_REGISTER && reg_renumber [ REGNO ( op ) ] < 0 && reg_equiv_mem ( REGNO ( op ) ) != 0 && double_memory_operand ( reg_equiv_mem ( REGNO ( op ) ) , mode ) ) return 1 ; return 0 ; } addr = XEXP ( op , 0 ) ; if ( CONSTANT_ADDRESS_P ( addr ) ) return 1 ; return memory_address_p ( ( GET_MODE_CLASS ( mode ) == MODE_INT ? SImode : SFmode ) , plus_constant ( Pmode , addr , 4 ) ) ; } </s>

Return nonzero for a memory address that can be used to load or store a doubleword .


<s>
void
PPCAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
MCInst
TmpInst
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
TargetOpcode
::
DBG_VALUE
:
{
if
(
!
isVerbose
(
)
||
!
OutStreamer
.
hasRawTextSupport
(
)
)
return
;
SmallString
<
32
>
Str
;
raw_svector_ostream
O
(
Str
)
;
unsigned
NOps
=
MI
->
getNumOperands
(
)
;
assert
(
NOps
==
4
)
;
O
<<
'\t'
<<
MAI
->
getCommentString
(
)
<<
"DEBUG_VALUE: "
;
DIVariable
V
(
const_cast
<
MDNode
*
>
(
MI
->
getOperand
(
NOps
1
)
.
getMetadata
(
)
)
)
;
O
<<
V
.
getName
(
)
;
O
<<
" <- "
;
assert
(
MI
->
getOperand
(
0
)
.
isReg
(
)
&&
MI
->
getOperand
(
1
)
.
isImm
(
)
)
;
O
<<
'['
;
printOperand
(
MI
,
0
,
O
)
;
O
<<
'+'
;
printOperand
(
MI
,
1
,
O
)
;
O
<<
']'
;
O
<<
"+"
;
printOperand
(
MI
,
NOps
2
,
O
)
;
OutStreamer
.
EmitRawText
(
O
.
str
(
)
)
;
return
;
}
case
PPC
::
MovePCtoLR
:
case
PPC
::
MovePCtoLR8
:
{
MCSymbol
*
PICBase
=
MF
->
getPICBaseSymbol
(
)
;
TmpInst
.
setOpcode
(
PPC
::
BL_Darwin
)
;
TmpInst
.
addOperand
(
MCOperand
::
CreateExpr
(
MCSymbolRefExpr
::
Create
(
PICBase
,
OutContext
)
)
)
;
OutStreamer
.
EmitInstruction
(
TmpInst
)
;
OutStreamer
.
EmitLabel
(
PICBase
)
;
return
;
}
case
PPC
::
LDtoc
:
{
LowerPPCMachineInstrToMCInst
(
MI
,
TmpInst
,
*
this
)
;
TmpInst
.
setOpcode
(
PPC
::
LD
)
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
1
)
;
assert
(
MO
.
isGlobal
(
)
)
;
MCSymbol
*
&
TOCEntry
=
TOC
[
Mang
->
getSymbol
(
MO
.
getGlobal
(
)
)
]
;
if
(
TOCEntry
==
0
)
TOCEntry
=
GetTempSymbol
(
"C"
,
TOCLabelID
++
)
;
const
MCExpr
*
Exp
=
MCSymbolRefExpr
::
Create
(
TOCEntry
,
MCSymbolRefExpr
::
VK_PPC_TOC
,
OutContext
)
;
TmpInst
.
getOperand
(
1
)
=
MCOperand
::
CreateExpr
(
Exp
)
;
OutStreamer
.
EmitInstruction
(
TmpInst
)
;
return
;
}
case
PPC
::
MFCRpseud
:
OutStreamer
.
AddComment
(
PPCInstPrinter
::
getRegisterName
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
)
;
TmpInst
.
setOpcode
(
PPC
::
MFCR
)
;
TmpInst
.
addOperand
(
MCOperand
::
CreateReg
(
MI
->
getOperand
(
0
)
.
getReg
(
)
)
)
;
OutStreamer
.
EmitInstruction
(
TmpInst
)
;
return
;
}
LowerPPCMachineInstrToMCInst
(
MI
,
TmpInst
,
*
this
)
;
OutStreamer
.
EmitInstruction
(
TmpInst
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void TL45InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { BuildMI ( MBB , MI , DL , get ( TL45 :: ADD ) ) . addReg ( DestReg ) . addReg ( SrcReg ) . addReg ( TL45 :: r0 ) ; } </s>


<s> SDValue PIC16TargetLowering :: LowerReturn ( SDValue Chain , unsigned CallConv , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , DebugLoc dl , SelectionDAG & DAG ) { unsigned NumRet = Outs . size ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function * F = MF . getFunction ( ) ; std :: string FuncName = F -> getName ( ) ; const char * tmpName = createESName ( PAN :: getFrameLabel ( FuncName ) ) ; SDVTList VTs = DAG . getVTList ( MVT :: i8 , MVT :: Other ) ; SDValue ES = DAG . getTargetExternalSymbol ( tmpName , MVT :: i8 ) ; SDValue BS = DAG . getConstant ( 1 , MVT :: i8 ) ; SDValue RetVal ; for ( unsigned i = 0 ; i < NumRet ; ++ i ) { RetVal = Outs [ i ] . Val ; Chain = DAG . getNode ( PIC16ISD :: PIC16Store , dl , MVT :: Other , Chain , RetVal , ES , BS , DAG . getConstant ( i , MVT :: i8 ) ) ; } return DAG . getNode ( PIC16ISD :: RET , dl , MVT :: Other , Chain ) ; } </s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s>
virtual
const
X86InstrInfo
*
getInstrInfo
(
)
const
{
llvm_unreachable
(
"getInstrInfo not implemented"
)
;
}
</s>


<s> bool arm_sat_operator_match ( rtx lo_bound , rtx hi_bound , int * mask , bool * signed_sat ) { int log = exact_log2 ( INTVAL ( hi_bound ) + 1 ) ; if ( log == - 1 ) return false ; if ( INTVAL ( lo_bound ) == 0 ) { if ( mask ) * mask = log ; if ( signed_sat ) * signed_sat = false ; return true ; } if ( INTVAL ( lo_bound ) == - INTVAL ( hi_bound ) - 1 ) { if ( mask ) * mask = log + 1 ; if ( signed_sat ) * signed_sat = true ; return true ; } return false ; } </s>

Match pair of min/max operators that can be implemented via usat/ssat .


<s> bool SITypeRewriter :: runOnFunction ( Function & F ) { AttributeSet Set = F . getAttributes ( ) ; Attribute A = Set . getAttribute ( AttributeSet :: FunctionIndex , "ShaderType" ) ; unsigned ShaderType = ShaderType :: COMPUTE ; if ( A . isStringAttribute ( ) ) { StringRef Str = A . getValueAsString ( ) ; Str . getAsInteger ( 0 , ShaderType ) ; } if ( ShaderType != ShaderType :: COMPUTE ) { visit ( F ) ; } visit ( F ) ; return false ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s>
void
X86AvoidSFBPass
::
buildCopy
(
MachineInstr
*
LoadInst
,
unsigned
NLoadOpcode
,
int64_t
LoadDisp
,
MachineInstr
*
StoreInst
,
unsigned
NStoreOpcode
,
int64_t
StoreDisp
,
unsigned
Size
,
int64_t
LMMOffset
,
int64_t
SMMOffset
)
{
MachineOperand
&
LoadBase
=
getBaseOperand
(
LoadInst
)
;
MachineOperand
&
StoreBase
=
getBaseOperand
(
StoreInst
)
;
MachineBasicBlock
*
MBB
=
LoadInst
->
getParent
(
)
;
MachineMemOperand
*
LMMO
=
*
LoadInst
->
memoperands_begin
(
)
;
MachineMemOperand
*
SMMO
=
*
StoreInst
->
memoperands_begin
(
)
;
Register
Reg1
=
MRI
->
createVirtualRegister
(
TII
->
getRegClass
(
TII
->
get
(
NLoadOpcode
)
,
0
,
TRI
,
*
(
MBB
->
getParent
(
)
)
)
)
;
MachineInstr
*
NewLoad
=
BuildMI
(
*
MBB
,
LoadInst
,
LoadInst
->
getDebugLoc
(
)
,
TII
->
get
(
NLoadOpcode
)
,
Reg1
)
.
add
(
LoadBase
)
.
addImm
(
1
)
.
addReg
(
X86
::
NoRegister
)
.
addImm
(
LoadDisp
)
.
addReg
(
X86
::
NoRegister
)
.
addMemOperand
(
MBB
->
getParent
(
)
->
getMachineMemOperand
(
LMMO
,
LMMOffset
,
Size
)
)
;
if
(
LoadBase
.
isReg
(
)
)
getBaseOperand
(
NewLoad
)
.
setIsKill
(
false
)
;
LLVM_DEBUG
(
NewLoad
->
dump
(
)
)
;
MachineInstr
*
StInst
=
StoreInst
;
auto
PrevInstrIt
=
prev_nodbg
(
MachineBasicBlock
::
instr_iterator
(
StoreInst
)
,
MBB
->
instr_begin
(
)
)
;
if
(
PrevInstrIt
.
getNodePtr
(
)
==
LoadInst
)
StInst
=
LoadInst
;
MachineInstr
*
NewStore
=
BuildMI
(
*
MBB
,
StInst
,
StInst
->
getDebugLoc
(
)
,
TII
->
get
(
NStoreOpcode
)
)
.
add
(
StoreBase
)
.
addImm
(
1
)
.
addReg
(
X86
::
NoRegister
)
.
addImm
(
StoreDisp
)
.
addReg
(
X86
::
NoRegister
)
.
addReg
(
Reg1
)
.
addMemOperand
(
MBB
->
getParent
(
)
->
getMachineMemOperand
(
SMMO
,
SMMOffset
,
Size
)
)
;
if
(
StoreBase
.
isReg
(
)
)
getBaseOperand
(
NewStore
)
.
setIsKill
(
false
)
;
MachineOperand
&
StoreSrcVReg
=
StoreInst
->
getOperand
(
X86
::
AddrNumOperands
)
;
assert
(
StoreSrcVReg
.
isReg
(
)
&&
"Expected virtual register"
)
;
NewStore
->
getOperand
(
X86
::
AddrNumOperands
)
.
setIsKill
(
StoreSrcVReg
.
isKill
(
)
)
;
LLVM_DEBUG
(
NewStore
->
dump
(
)
)
;
}
</s>


<s> static inline bool pdp11_saved_regno ( unsigned regno ) { return ! call_used_or_fixed_reg_p ( regno ) && df_regs_ever_live_p ( regno ) ; } </s>

A helper function to determine if REGNO should be saved in the current function 's stack frame .


<s> static tree aarch64_preferred_else_value ( unsigned , tree , unsigned int nops , tree * ops ) { return nops == 3 ? ops [ 2 ] : ops [ 0 ] ; } </s>

Implement TARGET_PREFERRED_ELSE_VALUE . For binary operations , prefer to use the first arithmetic operand as the else value if the else value does n't matter , since that exactly matches the SVE destructive merging form . For ternary operations we could either pick the first operand and use FMAD-like instructions or the last operand and use FMLA-like instructions ; the latter seems more natural .


<s> bool shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const override { return true ; } </s>

Returns true if it is beneficial to convert a load of a constant to just the constant itself .


<s>
MachineBasicBlock
*
MOSTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
MBB
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Bad opcode."
)
;
case
MOS
::
SelectImm
:
return
emitSelectImm
(
MI
,
MBB
)
;
case
MOS
::
IncMB
:
case
MOS
::
DecMB
:
return
emitIncDecMB
(
MI
,
MBB
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .

MOS
MOS
"Bad opcode."
MOS::SelectImm
MOS::IncMB
MOS::DecMB


<s> static bool mips_refers_to_kernel_reg_p ( const_rtx x ) { subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , x , NONCONST ) if ( REG_P ( * iter ) && KERNEL_REG_P ( REGNO ( * iter ) ) ) return true ; return false ; } </s>

Return true if X contains a kernel register .


<s> bool ARCRegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> LoadInst * X86TargetLowering :: lowerIdempotentRMWIntoFencedLoad ( AtomicRMWInst * AI ) const { unsigned NativeWidth = Subtarget . is64Bit ( ) ? 64 : 32 ; Type * MemType = AI -> getType ( ) ; if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) return nullptr ; if ( auto * C = dyn_cast < ConstantInt > ( AI -> getValOperand ( ) ) ) if ( AI -> getOperation ( ) == AtomicRMWInst :: Or && C -> isZero ( ) && AI -> use_empty ( ) ) return nullptr ; auto Builder = IRBuilder < > ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SSID = AI -> getSyncScopeID ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; if ( SSID == SyncScope :: SingleThread ) return nullptr ; if ( ! Subtarget . hasMFence ( ) ) return nullptr ; Function * MFence = llvm :: Intrinsic :: getDeclaration ( M , Intrinsic :: x86_sse2_mfence ) ; Builder . CreateCall ( MFence , { } ) ; LoadInst * Loaded = Builder . CreateAlignedLoad ( AI -> getType ( ) , AI -> getPointerOperand ( ) , AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ) ; Loaded -> setAtomic ( Order , SSID ) ; AI -> replaceAllUsesWith ( Loaded ) ; AI -> eraseFromParent ( ) ; return Loaded ; } </s>

On some platforms , an AtomicRMW that never actually modifies the value ( such as fetch_add of 0 ) can be turned into a fence followed by an atomic load .


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: AND : return LowerANDOR ( Op , DAG ) ; case ISD :: BRCOND : return LowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return LowerConstantPool ( Op , DAG ) ; case ISD :: DYNAMIC_STACKALLOC : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case ISD :: FP_TO_SINT : return LowerFP_TO_SINT ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: BlockAddress : return LowerBlockAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return LowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( Op , DAG ) ; case ISD :: OR : return LowerANDOR ( Op , DAG ) ; case ISD :: SELECT : return LowerSELECT ( Op , DAG ) ; case ISD :: SETCC : return LowerSETCC ( Op , DAG ) ; case ISD :: VASTART : return LowerVASTART ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::AND ISD::BRCOND ISD::ConstantPool ISD::DYNAMIC_STACKALLOC ISD::FP_TO_SINT ISD::GlobalAddress ISD::BlockAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::OR ISD::SELECT ISD::SETCC ISD::VASTART


<s> void ARMELFStreamer :: reset ( ) { MCTargetStreamer & TS = * getTargetStreamer ( ) ; ARMTargetStreamer & ATS = static_cast < ARMTargetStreamer & > ( TS ) ; ATS . reset ( ) ; MappingSymbolCounter = 0 ; MCELFStreamer :: reset ( ) ; LastMappingSymbols . clear ( ) ; LastEMSInfo . reset ( ) ; getAssembler ( ) . setELFHeaderEFlags ( ELF :: EF_ARM_EABI_VER5 ) ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"AMDGPU Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void SparcFrameInfo :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const SparcInstrInfo & TII = * static_cast < const SparcInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; NumBytes += 92 ; NumBytes = ( NumBytes + 7 ) & ~ 7 ; NumBytes = - NumBytes ; if ( NumBytes >= - 4096 ) { BuildMI ( MBB , MBBI , dl , TII . get ( SP :: SAVEri ) , SP :: O6 ) . addReg ( SP :: O6 ) . addImm ( NumBytes ) ; } else { unsigned OffHi = ( unsigned ) NumBytes >> 10U ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: SETHIi ) , SP :: G1 ) . addImm ( OffHi ) ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: ORri ) , SP :: G1 ) . addReg ( SP :: G1 ) . addImm ( NumBytes & ( ( 1 << 10 ) - 1 ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: SAVErr ) , SP :: O6 ) . addReg ( SP :: O6 ) . addReg ( SP :: G1 ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> unsigned getNumFixupKinds ( ) const override { return Nyuzi :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


PowerPC
PPC
PPC
PPC
PPC
"AnyReg unimplemented on 32-bit AIX."
PPC::X2
"Cold calling unimplemented on AIX."
PPC
PPC
PPC
PPC
PPC
PPC


<s> void VideocoreInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { int opc ; if ( VC :: LowRegRegClass . contains ( SrcReg ) && VC :: LowRegRegClass . contains ( DestReg ) ) opc = VC :: MOVqq ; else opc = VC :: MOVrr ; BuildMI ( MBB , I , DL , get ( opc ) ) . addReg ( DestReg ) . addReg ( SrcReg ) ; } </s>

Videocore Videocore VC::LowRegRegClass VC::LowRegRegClass VC::MOVqq VC::MOVrr


<s> int mcore_num_arg_regs ( enum machine_mode mode , tree type ) { int size ; if ( targetm . calls . must_pass_in_stack ( mode , type ) ) return 0 ; if ( type && mode == BLKmode ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; return ROUND_ADVANCE ( size ) ; } </s>

Compute the number of word sized registers needed to hold a function argument of mode MODE and type TYPE .


<s> void X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const X86Subtarget & STI = MF . getSubtarget < X86Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; const X86RegisterInfo & RegInfo = * STI . getRegisterInfo ( ) ; unsigned StackPtr = RegInfo . getStackRegister ( ) ; bool reserveCallFrame = hasReservedCallFrame ( MF ) ; int Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; bool IsLP64 = STI . isTarget64BitLP64 ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t InternalAmt = ( isDestroy || Amount ) ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { if ( Amount == 0 ) return ; unsigned StackAlign = STI . getFrameLowering ( ) -> getStackAlignment ( ) ; Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = nullptr ; Amount -= InternalAmt ; if ( Amount ) { if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( IsLP64 , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; unsigned Opc = getADDriOpcode ( IsLP64 , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } return ; } if ( Opcode == TII . getCallFrameDestroyOpcode ( ) && InternalAmt ) { unsigned Opc = getSUBriOpcode ( IsLP64 , InternalAmt ) ; MachineInstr * New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( InternalAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! std :: prev ( I ) -> isCall ( ) ) -- I ; MBB . insert ( I , New ) ; } } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> int mips_trampoline_code_size ( void ) { if ( TARGET_USE_PIC_FN_ADDR_REG ) return 4 * 4 ; else if ( ptr_mode == DImode ) return 8 * 4 ; else if ( ISA_HAS_LOAD_DELAY ) return 6 * 4 ; else return 4 * 4 ; } </s>

Return the size in bytes of the trampoline code , padded to TRAMPOLINE_ALIGNMENT bits . The static chain pointer and target function address immediately follow .


<s> int ix86_secondary_memory_needed ( enum reg_class class1 , enum reg_class class2 , enum machine_mode mode , int strict ) { if ( MAYBE_FLOAT_CLASS_P ( class1 ) != FLOAT_CLASS_P ( class1 ) || MAYBE_FLOAT_CLASS_P ( class2 ) != FLOAT_CLASS_P ( class2 ) || MAYBE_SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class1 ) || MAYBE_SSE_CLASS_P ( class2 ) != SSE_CLASS_P ( class2 ) || MAYBE_MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class1 ) || MAYBE_MMX_CLASS_P ( class2 ) != MMX_CLASS_P ( class2 ) ) { gcc_assert ( ! strict ) ; return true ; } if ( FLOAT_CLASS_P ( class1 ) != FLOAT_CLASS_P ( class2 ) ) return true ; if ( MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class2 ) ) return true ; if ( SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class2 ) ) { if ( ! TARGET_SSE2 ) return true ; if ( ! TARGET_INTER_UNIT_MOVES && ! optimize_size ) return true ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) return true ; if ( mode == SFmode || mode == DFmode ) return true ; } return false ; } </s>

If we are copying between general and FP registers , we need a memory location . The same is true for SSE and MMX registers . The macro ca n't work reliably when one of the CLASSES is class containing registers from multiple units ( SSE , MMX , integer ) . We avoid this by never combining those units in single alternative in the machine description . Ensure that this constraint holds to avoid unexpected surprises . When STRICT is false , we are being called from REGISTER_MOVE_COST , so do not enforce these sanity checks .


<s> virtual void * getAdjustedAnalysisPointer ( const void * ID ) { if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo * ) this ; return this ; } </s>

getAdjustedAnalysisPointer - This method is used when a pass implements an analysis interface through multiple inheritance .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
OpKind
::
Token
:
OS
<<
"Tok: "
<<
Token
.
Data
;
break
;
case
OpKind
::
Reg
:
OS
<<
"Reg: "
<<
TPCInstPrinter
::
getRegisterName
(
Reg
.
Num
)
;
break
;
case
OpKind
::
Imm
:
if
(
Imm
.
Expr
)
OS
<<
"ImmExpr: "
<<
Imm
.
Expr
;
else
OS
<<
"Imm: "
<<
Imm
.
Val
;
break
;
case
OpKind
::
MemRI
:
OS
<<
"Offset: "
<<
MemRI
.
Offset
<<
", Reg: "
<<
TPCInstPrinter
::
getRegisterName
(
MemRI
.
Reg
)
;
break
;
case
OpKind
::
DataType
:
{
static
const
StringRef
OpTypes
[
]
=
{
"f32"
,
"bf16"
,
"i32"
,
"u32"
,
"i8"
,
"u8"
,
"b"
,
"i16"
,
"u16"
,
"f16"
}
;
assert
(
DataType
<=
TPCII
::
OpType
::
Max
)
;
OS
<<
"DataType: "
<<
OpTypes
[
DataType
]
;
break
;
}
case
OpKind
::
DimMask
:
assert
(
DimMask
<
32
)
;
OS
<<
"DimMask: "
<<
std
::
bitset
<
5
>
(
DimMask
)
.
to_string
(
)
;
break
;
case
OpKind
::
SwitchSet
:
OS
<<
"SwitchSet: "
<<
SwitchSet
;
break
;
case
OpKind
::
Comparison
:
OS
<<
LoopCompareText
[
static_cast
<
unsigned
>
(
CompInfo
)
]
;
break
;
case
OpKind
::
Accumulator
:
OS
<<
"Acc "
;
break
;
case
OpKind
::
SwitchLutPtr
:
OS
<<
"SwitchSet with LutPtr: "
<<
SwitchSet
;
break
;
case
OpKind
::
SwitchAll
:
OS
<<
"SwitchSet with All: "
<<
SwitchSet
;
break
;
case
OpKind
::
Predicate
:
OS
<<
"Pred: "
;
if
(
Pred
.
Polarity
)
OS
<<
"!"
;
OS
<<
TPCInstPrinter
::
getRegisterName
(
Pred
.
RegNum
)
;
break
;
case
OpKind
::
GroupDesc
:
OS
<<
"GroupDesc: "
<<
GroupDesc
.
Val
;
break
;
case
OpKind
::
RoundMode
:
OS
<<
"RoundMode: "
<<
RoundMode
.
Name
;
break
;
case
OpKind
::
Rhu
:
OS
<<
"RHU: "
<<
Rhu
.
Val
;
break
;
case
OpKind
::
RhazRs
:
OS
<<
"RHAZ_RS: "
<<
RhazRs
.
Val
;
break
;
case
OpKind
::
DualGroup
:
case
OpKind
::
WR
:
case
OpKind
::
SDG
:
case
OpKind
::
WEG
:
OS
<<
MovDualGroup
.
Name
<<
"="
<<
MovDualGroup
.
Val
;
break
;
case
OpKind
::
RegSelFrom
:
OS
<<
"RegSelFrom: "
<<
RegSelFrom
.
Name
;
break
;
case
OpKind
::
RegSelTo
:
OS
<<
"RegSelTo: "
<<
RegSelTo
.
Name
;
break
;
case
OpKind
::
BothDivMod
:
OS
<<
"BothDivMod: "
<<
BothDivMod
.
Val
;
break
;
case
OpKind
::
X2
:
OS
<<
"X2: "
<<
X2
.
Val
;
break
;
case
OpKind
::
MovDGAll
:
OS
<<
"MovDGAll: "
<<
MovDGAll
.
Val
;
break
;
case
OpKind
::
MovDGPack
:
OS
<<
"MovDGPack: "
<<
MovDGPack
.
Val
;
break
;
case
OpKind
::
MovDGUnpack
:
OS
<<
"MovDGUnpack: "
<<
MovDGUnpack
.
Val
;
break
;
default
:
llvm_unreachable
(
"Invalid operand kind"
)
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

TPC
"Tok: "
"Reg: "
TPC
"ImmExpr: "
"Imm: "
"Offset: "
", Reg: "
TPC
"f32"
"bf16"
"i32"
"u32"
"i8"
"u8"
"b"
"i16"
"u16"
"f16"
TPC
"DataType: "
32
"DimMask: "
5
"SwitchSet: "
"Acc "
"SwitchSet with LutPtr: "
"SwitchSet with All: "
"Pred: "
"!"
TPC
"GroupDesc: "
"RoundMode: "
"RHU: "
"RHAZ_RS: "
"="
"RegSelFrom: "
"RegSelTo: "
"BothDivMod: "
"X2: "
"MovDGAll: "
"MovDGPack: "
"MovDGUnpack: "
"Invalid operand kind"


<s> SDValue SICTargetLowering :: getTargetNode ( JumpTableSDNode * N , EVT Ty , SelectionDAG & DAG , unsigned Flag ) const { return DAG . getTargetJumpTable ( N -> getIndex ( ) , Ty , Flag ) ; } </s>

Retrieve the target node this edge connects to .


<s> int mcore_is_dead ( rtx_insn * first , rtx reg ) { rtx_insn * insn ; if ( GET_CODE ( reg ) == SUBREG ) reg = SUBREG_REG ( reg ) ; if ( dead_or_set_p ( first , reg ) ) return 1 ; for ( insn = NEXT_INSN ( first ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( JUMP_P ( insn ) ) return 0 ; else if ( CALL_P ( insn ) ) { if ( reg_referenced_p ( reg , PATTERN ( insn ) ) || find_reg_fusage ( insn , USE , reg ) ) return 0 ; else if ( dead_or_set_p ( insn , reg ) ) return 1 ; } else if ( NONJUMP_INSN_P ( insn ) ) { if ( reg_referenced_p ( reg , PATTERN ( insn ) ) ) return 0 ; else if ( dead_or_set_p ( insn , reg ) ) return 1 ; } } return 0 ; } </s>

Check whether reg is dead at first . This is done by searching ahead for either the next use ( i.e. , reg is live ) , a death note , or a set of reg . Do n't just use dead_or_set_p ( ) since reload does not always mark deaths ( especially if PRESERVE_DEATH_NOTES_REGNO_P is not defined ) . We can ignore subregs by extracting the actual register . BRC


<s> bool RISCVAsmBackend :: mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const { return getRelaxedOpcode ( Inst . getOpcode ( ) ) != Inst . getOpcode ( ) ; } </s>

Check whether the given instruction may need relaxation .


<s>
SUnit
*
SystemZPostRASchedStrategy
::
pickNode
(
bool
&
IsTopNode
)
{
IsTopNode
=
true
;
if
(
Available
.
empty
(
)
)
return
nullptr
;
if
(
Available
.
size
(
)
==
1
)
{
DEBUG
(
dbgs
(
)
<<
"+++ Only one: "
;
HazardRec
.
dumpSU
(
*
Available
.
begin
(
)
,
dbgs
(
)
)
;
dbgs
(
)
<<
"\n"
;
)
;
return
*
Available
.
begin
(
)
;
}
DEBUG
(
dbgs
(
)
<<
"+++ Available: "
;
Available
.
dump
(
HazardRec
)
;
)
;
Candidate
Best
;
for
(
auto
*
SU
:
Available
)
{
Candidate
c
(
SU
,
HazardRec
)
;
if
(
Best
.
SU
==
nullptr
||
c
<
Best
)
{
Best
=
c
;
DEBUG
(
dbgs
(
)
<<
"+++ Best sofar: "
;
HazardRec
.
dumpSU
(
Best
.
SU
,
dbgs
(
)
)
;
if
(
Best
.
GroupingCost
!=
0
)
dbgs
(
)
<<
"\tGrouping cost:"
<<
Best
.
GroupingCost
;
if
(
Best
.
ResourcesCost
!=
0
)
dbgs
(
)
<<
" Resource cost:"
<<
Best
.
ResourcesCost
;
dbgs
(
)
<<
" Height:"
<<
Best
.
SU
->
getHeight
(
)
;
dbgs
(
)
<<
"\n"
;
)
;
}
if
(
!
SU
->
isScheduleHigh
&&
Best
.
noCost
(
)
)
break
;
}
assert
(
Best
.
SU
!=
nullptr
)
;
return
Best
.
SU
;
}
</s>

Pick the next node to schedule , or return NULL .

SystemZ
SystemZ
1
"+++ Only one: "
"\n"
"+++ Available: "
"+++ Best sofar: "
0
"\tGrouping cost:"
0
" Resource cost:"
" Height:"
"\n"


<s> static void mips_function_rodata_section ( tree decl ) { if ( ! TARGET_ABICALLS || TARGET_GPWORD ) default_function_rodata_section ( decl ) ; else if ( decl && DECL_SECTION_NAME ( decl ) ) { const char * name = TREE_STRING_POINTER ( DECL_SECTION_NAME ( decl ) ) ; if ( DECL_ONE_ONLY ( decl ) && strncmp ( name , ".gnu.linkonce.t." , 16 ) == 0 ) { char * rname = ASTRDUP ( name ) ; rname [ 14 ] = 'd' ; named_section_real ( rname , SECTION_LINKONCE | SECTION_WRITE , decl ) ; } else if ( flag_function_sections && flag_data_sections && strncmp ( name , ".text." , 6 ) == 0 ) { char * rname = ASTRDUP ( name ) ; memcpy ( rname + 1 , "data" , 4 ) ; named_section_flags ( rname , SECTION_WRITE ) ; } else data_section ( ) ; } else data_section ( ) ; } </s>

Implement TARGET_ASM_FUNCTION_RODATA_SECTION . The complication here is that , with the combination TARGET_ABICALLS & & ! TARGET_GPWORD , jump tables will use absolute addresses , and should therefore not be included in the read-only part of a DSO . Handle such cases by selecting a normal data section instead of a read-only one . The logic apes that in default_function_rodata_section .


Return the cache size in bytes for the given level of cache .


<s> static void riscv_set_current_function ( tree decl ) { if ( decl == NULL_TREE || current_function_decl == NULL_TREE || current_function_decl == error_mark_node || ! cfun -> machine ) return ; cfun -> machine -> naked_p = riscv_naked_function_p ( decl ) ; } </s>

Sanity cheching for above function attributes .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool PPCTTIImpl :: isHardwareLoopProfitable ( Loop * L , ScalarEvolution & SE , AssumptionCache & AC , TargetLibraryInfo * LibInfo , HardwareLoopInfo & HWLoopInfo ) { const PPCTargetMachine & TM = ST -> getTargetMachine ( ) ; TargetSchedModel SchedModel ; SchedModel . init ( ST ) ; unsigned ConstTripCount = SE . getSmallConstantTripCount ( L ) ; if ( ConstTripCount && ConstTripCount < SmallCTRLoopThreshold ) { SmallPtrSet < const Value * , 32 > EphValues ; CodeMetrics :: collectEphemeralValues ( L , & AC , EphValues ) ; CodeMetrics Metrics ; for ( BasicBlock * BB : L -> blocks ( ) ) Metrics . analyzeBasicBlock ( BB , * this , EphValues ) ; if ( Metrics . NumInsts <= ( 6 * SchedModel . getIssueWidth ( ) ) ) return false ; } SmallPtrSet < const Value * , 4 > Visited ; for ( Loop :: block_iterator I = L -> block_begin ( ) , IE = L -> block_end ( ) ; I != IE ; ++ I ) if ( mightUseCTR ( * I , LibInfo , Visited ) ) return false ; SmallVector < BasicBlock * , 4 > ExitingBlocks ; L -> getExitingBlocks ( ExitingBlocks ) ; for ( auto & BB : ExitingBlocks ) { Instruction * TI = BB -> getTerminator ( ) ; if ( ! TI ) continue ; if ( BranchInst * BI = dyn_cast < BranchInst > ( TI ) ) { uint64_t TrueWeight = 0 , FalseWeight = 0 ; if ( ! BI -> isConditional ( ) || ! BI -> extractProfMetadata ( TrueWeight , FalseWeight ) ) continue ; bool TrueIsExit = ! L -> contains ( BI -> getSuccessor ( 0 ) ) ; if ( ( TrueIsExit && FalseWeight < TrueWeight ) || ( ! TrueIsExit && FalseWeight > TrueWeight ) ) return false ; } } SmallVector < BasicBlock * , 4 > ExitBlocks ; L -> getExitBlocks ( ExitBlocks ) ; for ( auto & BB : ExitBlocks ) { for ( auto & PHI : BB -> phis ( ) ) { for ( int Idx = 0 , EndIdx = PHI . getNumIncomingValues ( ) ; Idx < EndIdx ; Idx ++ ) { const BasicBlock * IncomingBB = PHI . getIncomingBlock ( Idx ) ; const Value * IncomingValue = PHI . getIncomingValue ( Idx ) ; if ( L -> contains ( IncomingBB ) && memAddrUsesCTR ( IncomingValue , TM , Visited ) ) return false ; } } } LLVMContext & C = L -> getHeader ( ) -> getContext ( ) ; HWLoopInfo . CountType = TM . isPPC64 ( ) ? Type :: getInt64Ty ( C ) : Type :: getInt32Ty ( C ) ; HWLoopInfo . LoopDecrement = ConstantInt :: get ( HWLoopInfo . CountType , 1 ) ; return true ; } </s>

Query the target whether it would be profitable to convert the given loop into a hardware loop .


<s> void BPFAsmBackend :: applyFixup ( const MCFixup & Fixup , MutableArrayRef < char > Data , uint64_t Value , bool IsPCRel , MCContext & Ctx ) const { if ( Fixup . getKind ( ) == FK_SecRel_4 || Fixup . getKind ( ) == FK_SecRel_8 ) { assert ( Value == 0 ) ; } else if ( Fixup . getKind ( ) == FK_Data_4 || Fixup . getKind ( ) == FK_Data_8 ) { unsigned Size = Fixup . getKind ( ) == FK_Data_4 ? 4 : 8 ; for ( unsigned i = 0 ; i != Size ; ++ i ) { unsigned Idx = IsLittleEndian ? i : Size - i - 1 ; Data [ Fixup . getOffset ( ) + Idx ] = uint8_t ( Value >> ( i * 8 ) ) ; } } else { assert ( Fixup . getKind ( ) == FK_PCRel_2 ) ; Value = ( uint16_t ) ( ( Value - 8 ) / 8 ) ; if ( IsLittleEndian ) { Data [ Fixup . getOffset ( ) + 2 ] = Value & 0xFF ; Data [ Fixup . getOffset ( ) + 3 ] = Value >> 8 ; } else { Data [ Fixup . getOffset ( ) + 2 ] = Value >> 8 ; Data [ Fixup . getOffset ( ) + 3 ] = Value & 0xFF ; } } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineTraceMetrics > ( ) ; AU . addPreserved < MachineTraceMetrics > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> bool LM32PassConfig :: addInstSelector ( ) { addPass ( createLM32ISelDag ( getLM32TargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Local Dynamic TLS Access Clean-up"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"Virtual function multiversioning not supported"

Generate the dispatching code body to dispatch multi-versioned function DECL . The target hook is called to process the `` target '' attributes and provide the code to dispatch the right function at run-time . NODE points to the dispatcher decl whose body will be created .


<s> bool nds32_n8_load_to_ii_p ( rtx_insn * producer , rtx_insn * consumer ) { if ( post_update_insn_p ( producer ) ) return false ; rtx def_reg = SET_DEST ( PATTERN ( producer ) ) ; return n8_consumed_by_addr_in_p ( consumer , def_reg ) ; } </s>


<s> static const FunctionType * getType ( LLVMContext & Context , unsigned id ) { const Type * ResultTy = NULL ; std :: vector < const Type * > ArgTys ; bool IsVarArg = false ; return FunctionType :: get ( ResultTy , ArgTys , IsVarArg ) ; } </s>

Overload to return most specific vector type .


<s> unsigned ARMBaseRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; const ARMFrameLowering * TFI = getFrameLowering ( MF ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case ARM :: tGPRRegClassID : { bool HasFP = MF . getFrameInfo ( ) . isMaxCallFrameSizeComputed ( ) ? TFI -> hasFP ( MF ) : true ; return 5 - HasFP ; } case ARM :: GPRRegClassID : { bool HasFP = MF . getFrameInfo ( ) . isMaxCallFrameSizeComputed ( ) ? TFI -> hasFP ( MF ) : true ; return 10 - HasFP - STI . getNumGPRegistersReserved ( ) ; } case ARM :: SPRRegClassID : case ARM :: DPRRegClassID : return 32 - 10 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s>
unsigned
ARMBaseInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
getLastNonDebugInstr
(
)
;
if
(
I
==
MBB
.
end
(
)
)
return
0
;
if
(
!
isUncondBranchOpcode
(
I
->
getOpcode
(
)
)
&&
!
isCondBranchOpcode
(
I
->
getOpcode
(
)
)
)
return
0
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
if
(
I
==
MBB
.
begin
(
)
)
return
1
;
I
;
if
(
!
isCondBranchOpcode
(
I
->
getOpcode
(
)
)
)
return
1
;
I
->
eraseFromParent
(
)
;
return
2
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s> bool AArch64AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , const char * ExtraCode , raw_ostream & O ) { const MachineOperand & MO = MI -> getOperand ( OpNum ) ; if ( ! AsmPrinter :: PrintAsmOperand ( MI , OpNum , ExtraCode , O ) ) return false ; if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'w' : case 'x' : if ( MO . isReg ( ) ) return printAsmMRegister ( MO , ExtraCode [ 0 ] , O ) ; if ( MO . isImm ( ) && MO . getImm ( ) == 0 ) { unsigned Reg = ExtraCode [ 0 ] == 'w' ? AArch64 :: WZR : AArch64 :: XZR ; O << AArch64InstPrinter :: getRegisterName ( Reg ) ; return false ; } printOperand ( MI , OpNum , O ) ; return false ; case 'b' : case 'h' : case 's' : case 'd' : case 'q' : case 'z' : if ( MO . isReg ( ) ) { const TargetRegisterClass * RC ; switch ( ExtraCode [ 0 ] ) { case 'b' : RC = & AArch64 :: FPR8RegClass ; break ; case 'h' : RC = & AArch64 :: FPR16RegClass ; break ; case 's' : RC = & AArch64 :: FPR32RegClass ; break ; case 'd' : RC = & AArch64 :: FPR64RegClass ; break ; case 'q' : RC = & AArch64 :: FPR128RegClass ; break ; case 'z' : RC = & AArch64 :: ZPRRegClass ; break ; default : return true ; } return printAsmRegInClass ( MO , RC , AArch64 :: NoRegAltName , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } } if ( MO . isReg ( ) ) { Register Reg = MO . getReg ( ) ; if ( AArch64 :: GPR32allRegClass . contains ( Reg ) || AArch64 :: GPR64allRegClass . contains ( Reg ) ) return printAsmMRegister ( MO , 'x' , O ) ; if ( AArch64 :: GPR64x8ClassRegClass . contains ( Reg ) ) return printAsmMRegister ( MO , 't' , O ) ; unsigned AltName = AArch64 :: NoRegAltName ; const TargetRegisterClass * RegClass ; if ( AArch64 :: ZPRRegClass . contains ( Reg ) ) { RegClass = & AArch64 :: ZPRRegClass ; } else if ( AArch64 :: PPRRegClass . contains ( Reg ) ) { RegClass = & AArch64 :: PPRRegClass ; } else { RegClass = & AArch64 :: FPR128RegClass ; AltName = AArch64 :: vreg ; } return printAsmRegInClass ( MO , RegClass , AltName , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> DecodeStatus HexagonDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & os , raw_ostream & cs ) const { DecodeStatus Result = DecodeStatus :: Success ; bool Complete = false ; Size = 0 ; * CurrentBundle = & MI ; MI . setOpcode ( Hexagon :: BUNDLE ) ; MI . addOperand ( MCOperand :: createImm ( 0 ) ) ; while ( Result == Success && Complete == false ) { if ( Bytes . size ( ) < HEXAGON_INSTR_SIZE ) return MCDisassembler :: Fail ; MCInst * Inst = new ( getContext ( ) ) MCInst ; Result = getSingleInstruction ( * Inst , MI , Bytes , Address , os , cs , Complete ) ; MI . addOperand ( MCOperand :: createInst ( Inst ) ) ; Size += HEXAGON_INSTR_SIZE ; Bytes = Bytes . slice ( HEXAGON_INSTR_SIZE ) ; } return Result ; } </s>

Returns the disassembly of a single instruction .


"insertBranch must not be told to insert a fallthrough"

"MCS51 branch conditions have one component!"

"Unconditional branch with multiple successors!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> virtual const IA64RegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> SDNode * PTXDAGToDAGISel :: Select ( SDNode * Node ) { if ( Node -> getOpcode ( ) == PTXISD :: READ_PARAM ) return SelectREAD_PARAM ( Node ) ; else return SelectCode ( Node ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> static int loongarch_fp_div_cost ( machine_mode mode ) { return mode == DFmode ? loongarch_cost -> fp_div_df : loongarch_cost -> fp_div_sf ; } </s>

Return the cost of floating-point divisions of mode MODE .


<s> std :: unique_ptr < PBQPRAConstraint > AArch64Subtarget :: getCustomPBQPConstraints ( ) const { if ( ! isCortexA57 ( ) ) return nullptr ; return llvm :: make_unique < A57ChainingConstraint > ( ) ; } </s>

Return PBQPConstraint ( s ) for the target .


"stack limit expression is not supported"

Emit the correct code for allocating stack space , as insns . If COPY_R12 , make sure a copy of the old frame is left in r12 . The generated code may use hard register 0 as a temporary .


"the ABI for returning a value containing "

"zero-width bit-fields but otherwise an aggregate "

"with only one or two floating-point fields was "

"the ABI for returning a value with C++17 empty "

"bases but otherwise an aggregate with only one or "

"two floating-point fields was changed in GCC "

Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE . For normal calls , VALTYPE is the return type and MODE is VOIDmode . For libcalls , VALTYPE is null and MODE is the mode of the return value .


<s> enum reg_class mips_preferred_reload_class ( rtx x , enum reg_class class ) { if ( mips_dangerous_for_la25_p ( x ) && reg_class_subset_p ( LEA_REGS , class ) ) return LEA_REGS ; if ( TARGET_HARD_FLOAT && FLOAT_MODE_P ( GET_MODE ( x ) ) && reg_class_subset_p ( FP_REGS , class ) ) return FP_REGS ; if ( reg_class_subset_p ( GR_REGS , class ) ) class = GR_REGS ; if ( TARGET_MIPS16 && reg_class_subset_p ( M16_REGS , class ) ) class = M16_REGS ; return class ; } </s>


<s> SDValue XCoreSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { unsigned SizeBitWidth = Size . getValueType ( ) . getSizeInBits ( ) ; if ( ! AlwaysInline && ( Align & 3 ) == 0 && DAG . MaskedValueIsZero ( Size , APInt ( SizeBitWidth , 3 ) ) ) { const TargetLowering & TLI = * DAG . getTarget ( ) . getTargetLowering ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = TLI . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; Entry . Node = Src ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , 0 , TLI . getLibcallCallingConv ( RTLIB :: MEMCPY ) , false , false , false , DAG . getExternalSymbol ( "__memcpy_4" , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .


"*** Found COPY instruction from VSETVL"

runOnMachineFunction - Emit the function body .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Hexagon Store Widening"
;
}
</s>


<s> unsigned getPointerSize ( ) const { return 8 ; } </s>

Layout pointer size in bytes , rounded up to a whole number of bytes .


<s> bool SICRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( EnableSVEIntrinsicOpts && TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( createSVEIntrinsicOptsPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( 1 , true , true , false , true ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; addPass ( createAArch64StackTaggingPass ( TM -> getOptLevel ( ) == CodeGenOpt :: None ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedLoadCombinePass ( ) ) ; addPass ( createInterleavedAccessPass ( ) ) ; } if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardCheckPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> void gen_conditional_branch ( rtx operands [ ] , machine_mode mode ) { enum rtx_code test_code = GET_CODE ( operands [ 0 ] ) ; rtx cmp0 = operands [ 1 ] ; rtx cmp1 = operands [ 2 ] ; rtx reg ; int invert ; rtx label1 , label2 ; invert = 0 ; reg = gen_int_relational ( test_code , NULL_RTX , cmp0 , cmp1 , & invert ) ; if ( reg ) { cmp0 = reg ; cmp1 = const0_rtx ; test_code = NE ; } else if ( GET_CODE ( cmp1 ) == CONST_INT && INTVAL ( cmp1 ) != 0 ) cmp1 = force_reg ( mode , cmp1 ) ; label1 = gen_rtx_LABEL_REF ( VOIDmode , operands [ 3 ] ) ; label2 = pc_rtx ; if ( invert ) { label2 = label1 ; label1 = pc_rtx ; } emit_jump_insn ( gen_rtx_SET ( pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( test_code , VOIDmode , cmp0 , cmp1 ) , label1 , label2 ) ) ) ; } </s>

Emit the common code for doing conditional branches . operand [ 0 ] is the label to jump to . The comparison operands are saved away by cmp { si , di , sf , df } .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Lanai load / store optimization pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .

Lanai
"Lanai load / store optimization pass"


<s>
void
Mips16FrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
const
Mips16InstrInfo
&
TII
=
*
static_cast
<
const
Mips16InstrInfo
*
>
(
STI
.
getInstrInfo
(
)
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
dl
;
uint64_t
StackSize
=
MFI
.
getStackSize
(
)
;
if
(
StackSize
==
0
&&
!
MFI
.
adjustsStack
(
)
)
return
;
MachineModuleInfo
&
MMI
=
MF
.
getMMI
(
)
;
const
MCRegisterInfo
*
MRI
=
MMI
.
getContext
(
)
.
getRegisterInfo
(
)
;
MachineLocation
DstML
,
SrcML
;
TII
.
makeFrame
(
Mips
::
SP
,
StackSize
,
MBB
,
MBBI
)
;
unsigned
CFIIndex
=
MF
.
addFrameInst
(
MCCFIInstruction
::
createDefCfaOffset
(
nullptr
,
StackSize
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
TargetOpcode
::
CFI_INSTRUCTION
)
)
.
addCFIIndex
(
CFIIndex
)
;
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
.
getCalleeSavedInfo
(
)
;
if
(
!
CSI
.
empty
(
)
)
{
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
.
getCalleeSavedInfo
(
)
;
for
(
std
::
vector
<
CalleeSavedInfo
>
::
const_iterator
I
=
CSI
.
begin
(
)
,
E
=
CSI
.
end
(
)
;
I
!=
E
;
++
I
)
{
int64_t
Offset
=
MFI
.
getObjectOffset
(
I
->
getFrameIdx
(
)
)
;
unsigned
Reg
=
I
->
getReg
(
)
;
unsigned
DReg
=
MRI
->
getDwarfRegNum
(
Reg
,
true
)
;
unsigned
CFIIndex
=
MF
.
addFrameInst
(
MCCFIInstruction
::
createOffset
(
nullptr
,
DReg
,
Offset
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
TargetOpcode
::
CFI_INSTRUCTION
)
)
.
addCFIIndex
(
CFIIndex
)
;
}
}
if
(
hasFP
(
MF
)
)
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Mips
::
MoveR3216
)
,
Mips
::
S0
)
.
addReg
(
Mips
::
SP
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Mips
Mips
"Shrink-wrapping not yet supported"
Mips
Mips
0
Mips::SP
Mips::MoveR3216
Mips::S0
Mips::SP


<s> static bool vax_mode_dependent_address_p ( const_rtx x , addr_space_t as ATTRIBUTE_UNUSED ) { rtx xfoo0 , xfoo1 ; if ( GET_CODE ( x ) != PLUS ) return false ; xfoo0 = XEXP ( x , 0 ) ; xfoo1 = XEXP ( x , 1 ) ; if ( CONST_INT_P ( xfoo0 ) && REG_P ( xfoo1 ) ) return false ; if ( CONST_INT_P ( xfoo1 ) && REG_P ( xfoo0 ) ) return false ; if ( ! flag_pic && CONSTANT_ADDRESS_P ( xfoo0 ) && REG_P ( xfoo1 ) ) return false ; if ( ! flag_pic && CONSTANT_ADDRESS_P ( xfoo1 ) && REG_P ( xfoo0 ) ) return false ; return true ; } </s>

Return 1 if x ( a legitimate address expression ) has an effect that depends on the machine mode it is used for . On the VAX , the predecrement and postincrement address depend thus ( the amount of decrement or increment being the length of the operand ) and all indexed address depend thus ( because the index scale factor is the length of the operand ) .


<s> rtx legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , enum machine_mode mode ) { rtx orig_x = x ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 0 ) ) == MULT ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , 1 ) , force_operand ( XEXP ( x , 0 ) , NULL_RTX ) ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 1 ) ) == MULT ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , 0 ) , force_operand ( XEXP ( x , 1 ) , NULL_RTX ) ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 0 ) ) == PLUS ) x = gen_rtx_PLUS ( Pmode , force_operand ( XEXP ( x , 0 ) , NULL_RTX ) , XEXP ( x , 1 ) ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 1 ) ) == PLUS ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , 0 ) , force_operand ( XEXP ( x , 1 ) , NULL_RTX ) ) ; if ( x != orig_x && legitimate_address_p ( mode , x , FALSE ) ) return x ; if ( SPARC_SYMBOL_REF_TLS_P ( x ) ) x = legitimize_tls_address ( x ) ; else if ( flag_pic ) x = legitimize_pic_address ( x , mode , 0 ) ; else if ( GET_CODE ( x ) == PLUS && CONSTANT_ADDRESS_P ( XEXP ( x , 1 ) ) ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , 0 ) , copy_to_mode_reg ( Pmode , XEXP ( x , 1 ) ) ) ; else if ( GET_CODE ( x ) == PLUS && CONSTANT_ADDRESS_P ( XEXP ( x , 0 ) ) ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , 1 ) , copy_to_mode_reg ( Pmode , XEXP ( x , 0 ) ) ) ; else if ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == CONST || GET_CODE ( x ) == LABEL_REF ) x = copy_to_suggested_reg ( x , NULL_RTX , Pmode ) ; return x ; } </s>

Try machine-dependent ways of modifying an illegitimate address X to be legitimate . If we find one , return the new , valid address . OLDX is the address as it was before break_out_memory_refs was called . In some cases it is useful to look at this to decide what needs to be done . MODE is the mode of the operand pointed to by X .