<s> void SITargetLowering :: AdjustInstrPostInstrSelection ( MachineInstr * MI , SDNode * Node ) const { const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; TII -> legalizeOperands ( MI ) ; if ( TII -> isMIMG ( MI -> getOpcode ( ) ) ) { unsigned VReg = MI -> getOperand ( 0 ) . getReg ( ) ; unsigned Writemask = MI -> getOperand ( 1 ) . getImm ( ) ; unsigned BitsSet = 0 ; for ( unsigned i = 0 ; i < 4 ; ++ i ) BitsSet += Writemask & ( 1 << i ) ? 1 : 0 ; const TargetRegisterClass * RC ; switch ( BitsSet ) { default : return ; case 1 : RC = & AMDGPU :: VGPR_32RegClass ; break ; case 2 : RC = & AMDGPU :: VReg_64RegClass ; break ; case 3 : RC = & AMDGPU :: VReg_96RegClass ; break ; } unsigned NewOpcode = TII -> getMaskedMIMGOp ( MI -> getOpcode ( ) , BitsSet ) ; MI -> setDesc ( TII -> get ( NewOpcode ) ) ; MRI . setRegClass ( VReg , RC ) ; return ; } int NoRetAtomicOp = AMDGPU :: getAtomicNoRetOp ( MI -> getOpcode ( ) ) ; if ( NoRetAtomicOp != - 1 ) { if ( ! Node -> hasAnyUseOfValue ( 0 ) ) { MI -> setDesc ( TII -> get ( NoRetAtomicOp ) ) ; MI -> RemoveOperand ( 0 ) ; } return ; } } </s>

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s>
static
void
visium_option_override
(
void
)
{
if
(
flag_pic
==
1
)
warning
(
OPT_fpic
,
"%<-fpic%> is not supported"
)
;
if
(
flag_pic
==
2
)
warning
(
OPT_fPIC
,
"%<-fPIC%> is not supported"
)
;
target_flags
|=
MASK_MCM
;
if
(
(
target_flags_explicit
&
MASK_FPU
)
==
0
)
target_flags
|=
MASK_FPU
;
if
(
(
target_flags_explicit
&
MASK_SV_MODE
)
==
0
)
target_flags
|=
MASK_SV_MODE
;
if
(
visium_cpu_and_features
==
PROCESSOR_GR6
)
{
target_flags
|=
MASK_BMI
;
if
(
target_flags
&
MASK_FPU
)
target_flags
|=
MASK_FPU_IEEE
;
}
if
(
!
global_options_set
.
x_visium_cpu
)
visium_cpu
=
visium_cpu_and_features
;
if
(
flag_align_functions
&&
!
str_align_functions
)
{
if
(
visium_cpu
==
PROCESSOR_GR6
)
str_align_functions
=
"64"
;
else
str_align_functions
=
"256"
;
maybe_set_param_value
(
PARAM_INLINE_UNIT_GROWTH
,
100
,
global_options
.
x_param_values
,
global_options_set
.
x_param_values
)
;
}
if
(
flag_align_loops
&&
!
str_align_loops
)
{
if
(
visium_cpu
==
PROCESSOR_GR6
)
str_align_loops
=
"64"
;
else
{
str_align_loops
=
"256:32:8"
;
}
}
if
(
flag_align_jumps
&&
!
str_align_jumps
)
{
if
(
visium_cpu
==
PROCESSOR_GR6
)
str_align_jumps
=
"64"
;
else
str_align_jumps
=
"8"
;
}
}
</s>


<s> void MOSMCCodeEmitter :: emitInstruction ( uint64_t Val , unsigned Size , const MCSubtargetInfo & STI , raw_ostream & OS ) const { for ( int64_t I = 0 ; I < Size ; ++ I ) { OS << ( char ) ( Val & 0xff ) ; Val = Val >> 8 ; } } </s>

Targets should implement this to emit instructions .


<s> static opt_machine_mode aarch64_get_mask_mode ( poly_uint64 nunits , poly_uint64 nbytes ) { if ( TARGET_SVE && known_eq ( nbytes , BYTES_PER_SVE_VECTOR ) ) { unsigned int elem_nbytes = vector_element_size ( nbytes , nunits ) ; machine_mode pred_mode ; if ( aarch64_sve_pred_mode ( elem_nbytes ) . exists ( & pred_mode ) ) return pred_mode ; } return default_get_mask_mode ( nunits , nbytes ) ; } </s>


<s> bool SystemZTargetLowering :: hasInlineStackProbe ( MachineFunction & MF ) const { if ( MF . getFunction ( ) . hasFnAttribute ( "probe-stack" ) ) return MF . getFunction ( ) . getFnAttribute ( "probe-stack" ) . getValueAsString ( ) == "inline-asm" ; return false ; } </s>

Returns true if stack probing through inline assembly is requested .

SystemZ SystemZ "probe-stack" "probe-stack" "inline-asm"


<s> bool isIncomingArgumentHandler ( ) const override { return true ; } </s>

Returns true if the handler is dealing with incoming arguments , i.e .


<s>
void
X86AsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
X86MCInstLower
MCInstLowering
(
Mang
,
*
MF
,
*
this
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
TargetOpcode
::
DBG_VALUE
:
if
(
isVerbose
(
)
&&
OutStreamer
.
hasRawTextSupport
(
)
)
{
std
::
string
TmpStr
;
raw_string_ostream
OS
(
TmpStr
)
;
PrintDebugValueComment
(
MI
,
OS
)
;
OutStreamer
.
EmitRawText
(
StringRef
(
OS
.
str
(
)
)
)
;
}
return
;
case
X86
::
Int_MemBarrier
:
if
(
OutStreamer
.
hasRawTextSupport
(
)
)
OutStreamer
.
EmitRawText
(
StringRef
(
"\t#MEMBARRIER"
)
)
;
return
;
case
X86
::
EH_RETURN
:
case
X86
::
EH_RETURN64
:
{
unsigned
Reg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
OutStreamer
.
AddComment
(
StringRef
(
"eh_return, addr: %"
)
+
X86ATTInstPrinter
::
getRegisterName
(
Reg
)
)
;
break
;
}
case
X86
::
TAILJMPr
:
case
X86
::
TAILJMPd
:
case
X86
::
TAILJMPd64
:
OutStreamer
.
AddComment
(
"TAILCALL"
)
;
break
;
case
X86
::
TLS_addr32
:
case
X86
::
TLS_addr64
:
case
X86
::
TLS_base_addr32
:
case
X86
::
TLS_base_addr64
:
return
LowerTlsAddr
(
OutStreamer
,
MCInstLowering
,
*
MI
)
;
case
X86
::
MOVPC32r
:
{
MCSymbol
*
PICBase
=
MF
->
getPICBaseSymbol
(
)
;
OutStreamer
.
EmitInstruction
(
MCInstBuilder
(
getSubtarget
(
)
.
isTargetNaCl
(
)
X86
::
NACL_CALL32d
:
X86
::
CALLpcrel32
)
.
addExpr
(
MCSymbolRefExpr
::
Create
(
PICBase
,
OutContext
)
)
)
;
OutStreamer
.
EmitLabel
(
PICBase
)
;
OutStreamer
.
EmitInstruction
(
MCInstBuilder
(
X86
::
POP32r
)
.
addReg
(
MI
->
getOperand
(
0
)
.
getReg
(
)
)
)
;
return
;
}
case
X86
::
ADD32ri
:
{
if
(
MI
->
getOperand
(
2
)
.
getTargetFlags
(
)
!=
X86II
::
MO_GOT_ABSOLUTE_ADDRESS
)
break
;
MCSymbol
*
DotSym
=
OutContext
.
CreateTempSymbol
(
)
;
OutStreamer
.
EmitLabel
(
DotSym
)
;
MCSymbol
*
OpSym
=
MCInstLowering
.
GetSymbolFromOperand
(
MI
->
getOperand
(
2
)
)
;
const
MCExpr
*
DotExpr
=
MCSymbolRefExpr
::
Create
(
DotSym
,
OutContext
)
;
const
MCExpr
*
PICBase
=
MCSymbolRefExpr
::
Create
(
MF
->
getPICBaseSymbol
(
)
,
OutContext
)
;
DotExpr
=
MCBinaryExpr
::
CreateSub
(
DotExpr
,
PICBase
,
OutContext
)
;
DotExpr
=
MCBinaryExpr
::
CreateAdd
(
MCSymbolRefExpr
::
Create
(
OpSym
,
OutContext
)
,
DotExpr
,
OutContext
)
;
OutStreamer
.
EmitInstruction
(
MCInstBuilder
(
X86
::
ADD32ri
)
.
addReg
(
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addExpr
(
DotExpr
)
)
;
return
;
}
}
MCInst
TmpInst
;
MCInstLowering
.
Lower
(
MI
,
TmpInst
)
;
OutStreamer
.
EmitInstruction
(
TmpInst
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool TMS320C64XTargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( ! Subtarget . enablePostRAScheduler ( ) ) PM . add ( createTMS320C64XDelaySlotFillerPass ( * this ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static void i386_pe_seh_fini ( FILE * f ) { if ( ! TARGET_SEH ) return ; if ( cfun -> is_thunk ) return ; fputs ( "\t.seh_endproc\n" , f ) ; } </s>

Emit an assembler directive for the end of the function .


<s> static int sparc_tls_symbol_ref_1 ( rtx * x , void * data ATTRIBUTE_UNUSED ) { return SPARC_SYMBOL_REF_TLS_P ( * x ) ; } </s>

Return 1 if * X is a thread-local symbol .


"  Skipping pass: no machine model present.\n"

runOnMachineFunction - Emit the function body .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s>
unsigned
int
sh_cbranch_distance
(
rtx_insn
*
_cbranch_insn
,
unsigned
int
max_dist
)
{
rtx_jump_insn
*
cbranch_insn
=
safe_as_a
<
rtx_jump_insn
*
>
(
_cbranch_insn
)
;
if
(
dump_file
)
{
fprintf
(
dump_file
,
"sh_cbranch_distance insn = \n"
)
;
print_rtl_single
(
dump_file
,
cbranch_insn
)
;
}
unsigned
int
dist
=
0
;
for
(
rtx_insn
*
i
=
next_nonnote_insn
(
cbranch_insn
)
;
i
!=
&&
dist
<
max_dist
;
i
=
next_nonnote_insn
(
i
)
)
{
const
unsigned
int
i_len
=
get_attr_length
(
i
)
;
dist
+=
i_len
;
if
(
dump_file
)
fprintf
(
dump_file
,
"  insn %d  length = %u  dist = %u\n"
,
INSN_UID
(
i
)
,
i_len
,
dist
)
;
if
(
rtx_code_label
*
l
=
dyn_cast
<
rtx_code_label
*
>
(
i
)
)
{
if
(
l
==
cbranch_insn
->
jump_target
(
)
)
{
if
(
dump_file
)
fprintf
(
dump_file
,
"  cbranch dist = %u\n"
,
dist
)
;
return
dist
;
}
break
;
}
}
if
(
dump_file
)
fprintf
(
dump_file
,
"  cbranch dist = unknown\n"
)
;
return
unknown_cbranch_distance
;
}
</s>

Try to calculate the branch distance of a conditional branch in bytes . FIXME : Because of PR 59189 we ca n't use the CFG here . Instead just walk from this insn into the next ( fall-through ) basic block and see if we hit the label .

sh
"sh_cbranch_distance insn = \n"
0
"  insn %d  length = %u  dist = %u\n"
"  cbranch dist = %u\n"
"  cbranch dist = unknown\n"


<s> static unsigned int h8300_displacement_length ( rtx addr , int size ) { rtx offset ; offset = XEXP ( addr , 1 ) ; if ( register_operand ( XEXP ( addr , 0 ) , VOIDmode ) && GET_CODE ( offset ) == CONST_INT && ( INTVAL ( offset ) == size || INTVAL ( offset ) == size * 2 || INTVAL ( offset ) == size * 3 ) ) return 0 ; return h8300_constant_length ( offset ) ; } </s>

Return the size of a displacement field in address ADDR , which should have the form ( plus X constant ) . SIZE is the number of bytes being accessed .


<s> SDValue ARMTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : return PerformADDCombine ( N , DCI , Subtarget ) ; case ISD :: SUB : return PerformSUBCombine ( N , DCI ) ; case ISD :: MUL : return PerformMULCombine ( N , DCI , Subtarget ) ; case ISD :: OR : return PerformORCombine ( N , DCI , Subtarget ) ; case ISD :: XOR : return PerformXORCombine ( N , DCI , Subtarget ) ; case ISD :: AND : return PerformANDCombine ( N , DCI , Subtarget ) ; case ARMISD :: BFI : return PerformBFICombine ( N , DCI ) ; case ARMISD :: VMOVRRD : return PerformVMOVRRDCombine ( N , DCI ) ; case ARMISD :: VMOVDRR : return PerformVMOVDRRCombine ( N , DCI . DAG ) ; case ISD :: STORE : return PerformSTORECombine ( N , DCI ) ; case ISD :: BUILD_VECTOR : return PerformBUILD_VECTORCombine ( N , DCI ) ; case ISD :: INSERT_VECTOR_ELT : return PerformInsertEltCombine ( N , DCI ) ; case ISD :: VECTOR_SHUFFLE : return PerformVECTOR_SHUFFLECombine ( N , DCI . DAG ) ; case ARMISD :: VDUPLANE : return PerformVDUPLANECombine ( N , DCI ) ; case ISD :: FP_TO_SINT : case ISD :: FP_TO_UINT : return PerformVCVTCombine ( N , DCI , Subtarget ) ; case ISD :: FDIV : return PerformVDIVCombine ( N , DCI , Subtarget ) ; case ISD :: INTRINSIC_WO_CHAIN : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DCI . DAG , Subtarget ) ; case ISD :: SIGN_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: ANY_EXTEND : return PerformExtendCombine ( N , DCI . DAG , Subtarget ) ; case ISD :: SELECT_CC : return PerformSELECT_CCCombine ( N , DCI . DAG , Subtarget ) ; case ARMISD :: CMOV : return PerformCMOVCombine ( N , DCI . DAG ) ; case ARMISD :: VLD2DUP : case ARMISD :: VLD3DUP : case ARMISD :: VLD4DUP : return CombineBaseUpdate ( N , DCI ) ; case ISD :: INTRINSIC_VOID : case ISD :: INTRINSIC_W_CHAIN : switch ( cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) -> getZExtValue ( ) ) { case Intrinsic :: arm_neon_vld1 : case Intrinsic :: arm_neon_vld2 : case Intrinsic :: arm_neon_vld3 : case Intrinsic :: arm_neon_vld4 : case Intrinsic :: arm_neon_vld2lane : case Intrinsic :: arm_neon_vld3lane : case Intrinsic :: arm_neon_vld4lane : case Intrinsic :: arm_neon_vst1 : case Intrinsic :: arm_neon_vst2 : case Intrinsic :: arm_neon_vst3 : case Intrinsic :: arm_neon_vst4 : case Intrinsic :: arm_neon_vst2lane : case Intrinsic :: arm_neon_vst3lane : case Intrinsic :: arm_neon_vst4lane : return CombineBaseUpdate ( N , DCI ) ; default : break ; } break ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < TargetPassConfig > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; AU . addRequired < ScalarEvolutionWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool SPIRVInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { TBB = nullptr ; FBB = nullptr ; if ( MBB . empty ( ) ) return false ; auto MI = MBB . getLastNonDebugInstr ( ) ; if ( ! MI . isValid ( ) ) return false ; if ( MI -> getOpcode ( ) == SPIRV :: OpBranch ) { TBB = MI -> getOperand ( 0 ) . getMBB ( ) ; return false ; } else if ( MI -> getOpcode ( ) == SPIRV :: OpBranchConditional ) { Cond . push_back ( MI -> getOperand ( 0 ) ) ; TBB = MI -> getOperand ( 1 ) . getMBB ( ) ; if ( MI -> getNumOperands ( ) == 3 ) { FBB = MI -> getOperand ( 2 ) . getMBB ( ) ; } return false ; } else { return true ; } } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> bool SparcTargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createSparcISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


"No DAG nodes should be reachable from ExitSU"

Apply the profile inference algorithm for a given function .


<s>
void
SystemZAsmPrinter
::
emitFunctionEntryLabel
(
)
{
const
SystemZSubtarget
&
Subtarget
=
static_cast
<
const
SystemZSubtarget
&
>
(
MF
->
getSubtarget
(
)
)
;
if
(
Subtarget
.
getTargetTriple
(
)
.
isOSzOS
(
)
)
{
MCContext
&
OutContext
=
OutStreamer
->
getContext
(
)
;
MCSymbol
*
EPMarkerSym
=
OutContext
.
createTempSymbol
(
"CM_"
,
true
)
;
const
MachineFrameInfo
&
MFFrame
=
MF
->
getFrameInfo
(
)
;
bool
IsUsingAlloca
=
MFFrame
.
hasVarSizedObjects
(
)
;
uint8_t
Flags
=
0
;
if
(
IsUsingAlloca
)
Flags
|=
0x04
;
uint32_t
DSASize
=
MFFrame
.
getStackSize
(
)
;
uint32_t
DSAAndFlags
=
DSASize
&
0xFFFFFFE0
;
DSAAndFlags
|=
Flags
;
OutStreamer
->
AddComment
(
"XPLINK Routine Layout Entry"
)
;
OutStreamer
->
emitLabel
(
EPMarkerSym
)
;
OutStreamer
->
AddComment
(
"Eyecatcher 0x00C300C500C500"
)
;
OutStreamer
->
emitIntValueInHex
(
0x00C300C500C500
,
7
)
;
OutStreamer
->
AddComment
(
"Mark Type C'1'"
)
;
OutStreamer
->
emitInt8
(
0xF1
)
;
if
(
OutStreamer
->
isVerboseAsm
(
)
)
{
OutStreamer
->
AddComment
(
"DSA Size 0x"
+
Twine
::
utohexstr
(
DSASize
)
)
;
OutStreamer
->
AddComment
(
"Entry Flags"
)
;
if
(
Flags
&
0x04
)
OutStreamer
->
AddComment
(
"  Bit 2: 1 = Uses alloca"
)
;
else
OutStreamer
->
AddComment
(
"  Bit 2: 0 = Does not use alloca"
)
;
}
OutStreamer
->
emitInt32
(
DSAAndFlags
)
;
}
AsmPrinter
::
emitFunctionEntryLabel
(
)
;
}
</s>

EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function .


<s> tree function_resolver :: get_argument_type ( unsigned int i ) { tree arg = m_arglist [ i ] ; return arg == error_mark_node ? arg : TREE_TYPE ( arg ) ; } </s>

Return the type of argument I , or error_mark_node if it is n't well-formed .


Allocate ORIG_SIZE bytes on the stack and probe the newly allocated space every STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes . COPY_REG , if non-null , should contain a copy of the original stack pointer at exit from this function . This is subtly different than the Ada probing in that it tries hard to prevent attacks that jump the stack guard . Thus it is never allowed to allocate more than STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes of stack space without a suitable probe .


<s> const CSKYMCExpr * CSKYMCExpr :: create ( const MCExpr * Expr , VariantKind Kind , MCContext & Ctx ) { return new ( Ctx ) CSKYMCExpr ( Kind , Expr ) ; } </s>


<s>
unsigned
ARMTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"sp"
,
ARM
::
SP
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
Twine
(
"Invalid register name \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;
}
</s>

Return the register ID of the name passed in .

ARM
ARM
"sp"
ARM::SP
0
"Invalid register name \""
"\"."


<s> void ARMAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( EnableMCInst ) { printInstructionThroughMCStreamer ( MI ) ; } else { int Opc = MI -> getOpcode ( ) ; if ( Opc == ARM :: CONSTPOOL_ENTRY ) EmitAlignment ( 2 ) ; printInstruction ( MI ) ; OutStreamer . AddBlankLine ( ) ; } } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void ARMMachOTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileMachO :: Initialize ( Ctx , TM ) ; LSDASection = getMachOSection ( "__TEXT" , "__gcc_except_tab" , 0 , SectionKind :: getReadOnlyWithRel ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s> const TargetRegisterClass * R600RegisterInfo :: getCFGStructurizerRegClass ( MVT VT ) const { switch ( VT . SimpleTy ) { default : case MVT :: i32 : return & R600 :: R600_TReg32RegClass ; } } </s>

get the register class of the specified type to use in the CFGStructurizer


<s> static bool hasIndex ( const MachineInstr & MI , const MCRegisterInfo & RI ) { for ( const MachineOperand & Op : MI . explicit_operands ( ) ) if ( isIndex ( Op , RI ) ) return true ; return false ; } </s>

Returns true if the given machine instr is mapped to an index , otherwise returns false .


<s>
void
mmix_asm_output_addr_vec_elt
(
FILE
*
stream
,
int
value
)
{
fprintf
(
stream
,
"\tOCTA L:%d\n"
,
value
)
;
}
</s>


<s> bool enableMachineScheduler ( ) const override { return true ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Hexagon Copy-To-Combine Pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
const
RegisterBank
&
AArch64RegisterBankInfo
::
getRegBankFromRegClass
(
const
TargetRegisterClass
&
RC
)
const
{
switch
(
RC
.
getID
(
)
)
{
case
AArch64
::
FPR8RegClassID
:
case
AArch64
::
FPR16RegClassID
:
case
AArch64
::
FPR32RegClassID
:
case
AArch64
::
FPR64RegClassID
:
case
AArch64
::
FPR128RegClassID
:
case
AArch64
::
FPR128_loRegClassID
:
case
AArch64
::
DDRegClassID
:
case
AArch64
::
DDDRegClassID
:
case
AArch64
::
DDDDRegClassID
:
case
AArch64
::
QQRegClassID
:
case
AArch64
::
QQQRegClassID
:
case
AArch64
::
QQQQRegClassID
:
return
getRegBank
(
AArch64
::
FPRRegBankID
)
;
case
AArch64
::
GPR32commonRegClassID
:
case
AArch64
::
GPR32RegClassID
:
case
AArch64
::
GPR32spRegClassID
:
case
AArch64
::
GPR32sponlyRegClassID
:
case
AArch64
::
GPR32allRegClassID
:
case
AArch64
::
GPR64commonRegClassID
:
case
AArch64
::
GPR64RegClassID
:
case
AArch64
::
GPR64spRegClassID
:
case
AArch64
::
GPR64sponlyRegClassID
:
case
AArch64
::
GPR64allRegClassID
:
case
AArch64
::
GPR64noipRegClassID
:
case
AArch64
::
GPR64common_and_GPR64noipRegClassID
:
case
AArch64
::
GPR64noip_and_tcGPR64RegClassID
:
case
AArch64
::
tcGPR64RegClassID
:
case
AArch64
::
WSeqPairsClassRegClassID
:
case
AArch64
::
XSeqPairsClassRegClassID
:
return
getRegBank
(
AArch64
::
GPRRegBankID
)
;
case
AArch64
::
CCRRegClassID
:
return
getRegBank
(
AArch64
::
CCRegBankID
)
;
default
:
llvm_unreachable
(
"Register class not supported"
)
;
}
}
</s>


<s> static bool nvptx_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) { return pass_in_memory ( arg . mode , arg . type , false ) ; } </s>

Types with a mode other than those supported by the machine are passed by reference in memory .


"getRegForInlineAsmConstraint Unhandled data type"

Given a physical register constraint ( e.g .


<s> void nvptx_record_needed_fndecl ( tree decl ) { if ( nvptx_record_fndecl ( decl ) ) return ; tree * slot = needed_fndecls_htab -> find_slot ( decl , INSERT ) ; if ( * slot == NULL ) * slot = decl ; } </s>

Record that we need to emit a ptx decl for DECL . Either do it now , or record it for later in case we have no argument information at this point .


<s> static int spu_naked_function_p ( tree func ) { tree a ; if ( TREE_CODE ( func ) != FUNCTION_DECL ) abort ( ) ; a = lookup_attribute ( "naked" , DECL_ATTRIBUTES ( func ) ) ; return a != NULL_TREE ; } </s>

Return nonzero if FUNC is a naked function .


<s> virtual void print ( raw_ostream & OS ) const { llvm_unreachable ( "unimplemented!" ) ; } </s>

print - Print a debug representation of the operand to the given stream .


<s> void AMDGPUTargetLowering :: AnalyzeFormalArguments ( CCState & State , const SmallVectorImpl < ISD :: InputArg > & Ins ) const { State . AnalyzeFormalArguments ( Ins , CC_AMDGPU ) ; } </s>

AnalyzeFormalArguments - Analyze an array of argument values , incorporating info about the formals into this state .


<s> SDValue X86TargetLowering :: getNegatedExpression ( SDValue Op , SelectionDAG & DAG , bool LegalOperations , bool ForCodeSize , unsigned Depth ) const { if ( SDValue Arg = isFNEG ( DAG , Op . getNode ( ) , Depth ) ) return DAG . getBitcast ( Op . getValueType ( ) , Arg ) ; EVT VT = Op . getValueType ( ) ; EVT SVT = VT . getScalarType ( ) ; unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { case ISD :: FMA : case X86ISD :: FMSUB : case X86ISD :: FNMADD : case X86ISD :: FNMSUB : case X86ISD :: FMADD_RND : case X86ISD :: FMSUB_RND : case X86ISD :: FNMADD_RND : case X86ISD :: FNMSUB_RND : { if ( ! Op . hasOneUse ( ) || ! Subtarget . hasAnyFMA ( ) || ! isTypeLegal ( VT ) || ! ( SVT == MVT :: f32 || SVT == MVT :: f64 ) || ! isOperationLegal ( ISD :: FMA , VT ) ) break ; SmallVector < SDValue , 4 > NewOps ( Op . getNumOperands ( ) , SDValue ( ) ) ; for ( int i = 0 ; i != 3 ; ++ i ) { NegatibleCost V = getNegatibleCost ( Op . getOperand ( i ) , DAG , LegalOperations , ForCodeSize , Depth + 1 ) ; if ( V == NegatibleCost :: Cheaper ) NewOps [ i ] = getNegatedExpression ( Op . getOperand ( i ) , DAG , LegalOperations , ForCodeSize , Depth + 1 ) ; } bool NegA = ! ! NewOps [ 0 ] ; bool NegB = ! ! NewOps [ 1 ] ; bool NegC = ! ! NewOps [ 2 ] ; unsigned NewOpc = negateFMAOpcode ( Opc , NegA != NegB , NegC , true ) ; for ( int i = 0 , e = Op . getNumOperands ( ) ; i != e ; ++ i ) if ( ! NewOps [ i ] ) NewOps [ i ] = Op . getOperand ( i ) ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , VT , NewOps ) ; } case X86ISD :: FRCP : return DAG . getNode ( Opc , SDLoc ( Op ) , VT , getNegatedExpression ( Op . getOperand ( 0 ) , DAG , LegalOperations , ForCodeSize , Depth + 1 ) ) ; } return TargetLowering :: getNegatedExpression ( Op , DAG , LegalOperations , ForCodeSize , Depth ) ; } </s>

Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate that if it is cheaper or neutral to do the negation .


<s> bool HexagonFrameLowering :: hasTailCall ( MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; unsigned RetOpcode = MBBI -> getOpcode ( ) ; return RetOpcode == Hexagon :: TCRETURNtg || RetOpcode == Hexagon :: TCRETURNtext ; } </s>

Returns true if the function contains a tail call .

Hexagon Hexagon Hexagon::TCRETURNtg Hexagon::TCRETURNtext


<s> void SystemZTargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { return LowerOperationWrapper ( N , Results , DAG ) ; } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> void ConvergingVLIWScheduler :: releaseTopNode ( SUnit * SU ) { if ( SU -> isScheduled ) return ; for ( const SDep & PI : SU -> Preds ) { unsigned PredReadyCycle = PI . getSUnit ( ) -> TopReadyCycle ; unsigned MinLatency = PI . getLatency ( ) ; Top . MaxMinLatency = std :: max ( MinLatency , Top . MaxMinLatency ) ; if ( SU -> TopReadyCycle < PredReadyCycle + MinLatency ) SU -> TopReadyCycle = PredReadyCycle + MinLatency ; } Top . releaseNode ( SU , SU -> TopReadyCycle ) ; } </s>

SU has had all predecessor dependencies resolved .


<s> SDValue AMDGPUTargetLowering :: SplitVectorLoad ( const SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; if ( VT . getVectorNumElements ( ) == 2 ) return ScalarizeVectorLoad ( Op , DAG ) ; LoadSDNode * Load = cast < LoadSDNode > ( Op ) ; SDValue BasePtr = Load -> getBasePtr ( ) ; EVT PtrVT = BasePtr . getValueType ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; SDLoc SL ( Op ) ; const MachinePointerInfo & SrcValue = Load -> getMemOperand ( ) -> getPointerInfo ( ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Op , SL , LoVT , HiVT ) ; unsigned Size = LoMemVT . getStoreSize ( ) ; unsigned BaseAlign = Load -> getAlignment ( ) ; unsigned HiAlign = MinAlign ( BaseAlign , Size ) ; SDValue LoLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , LoVT , Load -> getChain ( ) , BasePtr , SrcValue , LoMemVT , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> isInvariant ( ) , BaseAlign ) ; SDValue HiPtr = DAG . getNode ( ISD :: ADD , SL , PtrVT , BasePtr , DAG . getConstant ( Size , SL , PtrVT ) ) ; SDValue HiLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , HiVT , Load -> getChain ( ) , HiPtr , SrcValue . getWithOffset ( LoMemVT . getStoreSize ( ) ) , HiMemVT , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> isInvariant ( ) , HiAlign ) ; SDValue Ops [ ] = { DAG . getNode ( ISD :: CONCAT_VECTORS , SL , VT , LoLoad , HiLoad ) , DAG . getNode ( ISD :: TokenFactor , SL , MVT :: Other , LoLoad . getValue ( 1 ) , HiLoad . getValue ( 1 ) ) } ; return DAG . getMergeValues ( Ops , SL ) ; } </s>

Split a vector load into 2 loads of half the vector .


<s> static tree rs6000_builtin_reciprocal ( tree fndecl ) { switch ( DECL_FUNCTION_CODE ( fndecl ) ) { case VSX_BUILTIN_XVSQRTDP : if ( ! RS6000_RECIP_AUTO_RSQRTE_P ( V2DFmode ) ) return NULL_TREE ; return rs6000_builtin_decls [ VSX_BUILTIN_RSQRT_2DF ] ; case VSX_BUILTIN_XVSQRTSP : if ( ! RS6000_RECIP_AUTO_RSQRTE_P ( V4SFmode ) ) return NULL_TREE ; return rs6000_builtin_decls [ VSX_BUILTIN_RSQRT_4SF ] ; default : return NULL_TREE ; } } </s>

Returns a code for a target-specific builtin that implements reciprocal of the function , or NULL_TREE if not available .


"internal compiler error.  Incorrect shift:"

8bit arithmetic shift right ( ( signed char ) x > > i )


<s>
static
void
arm_unwind_emit
(
FILE
*
out_file
,
rtx_insn
*
insn
)
{
rtx
note
,
pat
;
bool
handled_one
=
false
;
if
(
arm_except_unwind_info
(
&
global_options
)
!=
UI_TARGET
)
return
;
if
(
!
(
flag_unwind_tables
||
crtl
->
uses_eh_lsda
)
&&
(
TREE_NOTHROW
(
current_function_decl
)
||
crtl
->
all_throwers_are_sibcalls
)
)
return
;
if
(
NOTE_P
(
insn
)
||
!
RTX_FRAME_RELATED_P
(
insn
)
)
return
;
for
(
note
=
REG_NOTES
(
insn
)
;
note
;
note
=
XEXP
(
note
,
1
)
)
{
switch
(
REG_NOTE_KIND
(
note
)
)
{
case
REG_FRAME_RELATED_EXPR
:
pat
=
XEXP
(
note
,
0
)
;
goto
found
;
case
REG_CFA_REGISTER
:
pat
=
XEXP
(
note
,
0
)
;
if
(
pat
==
)
{
pat
=
PATTERN
(
insn
)
;
if
(
GET_CODE
(
pat
)
==
PARALLEL
)
pat
=
XVECEXP
(
pat
,
0
,
0
)
;
}
{
rtx
dest
,
src
;
unsigned
reg
;
src
=
SET_SRC
(
pat
)
;
dest
=
SET_DEST
(
pat
)
;
gcc_assert
(
src
==
stack_pointer_rtx
)
;
reg
=
REGNO
(
dest
)
;
asm_fprintf
(
out_file
,
"\t.unwind_raw 0, 0x%x @ vsp = r%d\n"
,
reg
+
0x90
,
reg
)
;
}
handled_one
=
true
;
break
;
case
REG_CFA_DEF_CFA
:
case
REG_CFA_ADJUST_CFA
:
case
REG_CFA_RESTORE
:
return
;
case
REG_CFA_EXPRESSION
:
case
REG_CFA_OFFSET
:
gcc_unreachable
(
)
;
default
:
break
;
}
}
if
(
handled_one
)
return
;
pat
=
PATTERN
(
insn
)
;
found
:
switch
(
GET_CODE
(
pat
)
)
{
case
SET
:
arm_unwind_emit_set
(
out_file
,
pat
)
;
break
;
case
SEQUENCE
:
arm_unwind_emit_sequence
(
out_file
,
pat
)
;
break
;
default
:
abort
(
)
;
}
}
</s>

Emit unwind directives for the given insn .


<s> static bool nds32_rtx_costs ( rtx x , machine_mode mode , int outer_code , int opno , int * total , bool speed ) { return nds32_rtx_costs_impl ( x , mode , outer_code , opno , total , speed ) ; } </s>

This target hook describes the relative costs of RTL expressions . Return 'true ' when all subexpressions of x have been processed . Return 'false ' to sum the costs of sub-rtx , plus cost of this operation . Refer to gcc/rtlanal.cc for more information .


<s>
static
const
char
*
avr_out_movhi_r_mr_reg_no_disp_tiny
(
rtx
op
[
]
,
int
*
plen
)
{
rtx
dest
=
op
[
0
]
;
rtx
src
=
op
[
1
]
;
rtx
base
=
XEXP
(
src
,
0
)
;
int
reg_dest
=
true_regnum
(
dest
)
;
int
reg_base
=
true_regnum
(
base
)
;
if
(
reg_dest
==
reg_base
)
return
avr_asm_len
(
"ld __tmp_reg__,%1+"
CR_TAB
"ld %B0,%1"
CR_TAB
"mov %A0,__tmp_reg__"
,
op
,
plen
,
3
)
;
return
avr_asm_len
(
"ld %A0,%1"
CR_TAB
TINY_ADIW
(
%
E1
,
%
F1
,
1
)
CR_TAB
"ld %B0,%1"
CR_TAB
TINY_SBIW
(
%
E1
,
%
F1
,
1
)
,
op
,
plen
,
6
)
;
}
</s>

Same as movhi_r_mr , but TINY does not have ADIW , SBIW and LDD


"Can only insert epilog into returning blocks"


<s> void aarch64_split_compare_and_swap ( rtx operands [ ] ) { rtx rval , mem , oldval , newval , scratch ; machine_mode mode ; bool is_weak ; rtx_code_label * label1 , * label2 ; rtx x , cond ; enum memmodel model ; rtx model_rtx ; rval = operands [ 0 ] ; mem = operands [ 1 ] ; oldval = operands [ 2 ] ; newval = operands [ 3 ] ; is_weak = ( operands [ 4 ] != const0_rtx ) ; model_rtx = operands [ 5 ] ; scratch = operands [ 7 ] ; mode = GET_MODE ( mem ) ; model = memmodel_from_int ( INTVAL ( model_rtx ) ) ; label1 = NULL ; if ( ! is_weak ) { label1 = gen_label_rtx ( ) ; emit_label ( label1 ) ; } label2 = gen_label_rtx ( ) ; if ( is_mm_sync ( model ) ) aarch64_emit_load_exclusive ( mode , rval , mem , GEN_INT ( MEMMODEL_RELAXED ) ) ; else aarch64_emit_load_exclusive ( mode , rval , mem , model_rtx ) ; cond = aarch64_gen_compare_reg ( NE , rval , oldval ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; aarch64_emit_store_exclusive ( mode , scratch , mem , newval , model_rtx ) ; if ( ! is_weak ) { x = gen_rtx_NE ( VOIDmode , scratch , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label1 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } else { cond = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_COMPARE ( CCmode , scratch , const0_rtx ) ; emit_insn ( gen_rtx_SET ( cond , x ) ) ; } emit_label ( label2 ) ; if ( is_mm_sync ( model ) ) aarch64_emit_post_barrier ( model ) ; } </s>


<s> bool WebAssemblySubtarget :: useAA ( ) const { return true ; } </s>

Enable use of alias analysis during code generation ( during MI scheduling , DAGCombine , etc . ) .


<s> static void aarch64_emit_atomic_load_op ( enum aarch64_atomic_load_op_code code , machine_mode mode , rtx dst , rtx src , rtx mem , rtx model ) { typedef rtx ( * aarch64_atomic_load_op_fn ) ( rtx , rtx , rtx , rtx ) ; const aarch64_atomic_load_op_fn plus [ ] = { gen_aarch64_atomic_loadaddqi , gen_aarch64_atomic_loadaddhi , gen_aarch64_atomic_loadaddsi , gen_aarch64_atomic_loadadddi } ; const aarch64_atomic_load_op_fn eor [ ] = { gen_aarch64_atomic_loadeorqi , gen_aarch64_atomic_loadeorhi , gen_aarch64_atomic_loadeorsi , gen_aarch64_atomic_loadeordi } ; const aarch64_atomic_load_op_fn ior [ ] = { gen_aarch64_atomic_loadsetqi , gen_aarch64_atomic_loadsethi , gen_aarch64_atomic_loadsetsi , gen_aarch64_atomic_loadsetdi } ; const aarch64_atomic_load_op_fn bic [ ] = { gen_aarch64_atomic_loadclrqi , gen_aarch64_atomic_loadclrhi , gen_aarch64_atomic_loadclrsi , gen_aarch64_atomic_loadclrdi } ; aarch64_atomic_load_op_fn gen ; int idx = 0 ; switch ( mode ) { case QImode : idx = 0 ; break ; case HImode : idx = 1 ; break ; case SImode : idx = 2 ; break ; case DImode : idx = 3 ; break ; default : gcc_unreachable ( ) ; } switch ( code ) { case AARCH64_LDOP_PLUS : gen = plus [ idx ] ; break ; case AARCH64_LDOP_XOR : gen = eor [ idx ] ; break ; case AARCH64_LDOP_OR : gen = ior [ idx ] ; break ; case AARCH64_LDOP_BIC : gen = bic [ idx ] ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( dst , mem , src , model ) ) ; } </s>


<s> MachineBasicBlock :: iterator XCoreInstrInfo :: loadImmediate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned Reg , uint64_t Value ) const { DebugLoc dl ; if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) dl = MI -> getDebugLoc ( ) ; if ( isImmMskBitp ( Value ) ) { int N = Log2_32 ( Value ) + 1 ; return BuildMI ( MBB , MI , dl , get ( XCore :: MKMSK_rus ) , Reg ) . addImm ( N ) . getInstr ( ) ; } if ( isImmU16 ( Value ) ) { int Opcode = isImmU6 ( Value ) ? XCore :: LDC_ru6 : XCore :: LDC_lru6 ; return BuildMI ( MBB , MI , dl , get ( Opcode ) , Reg ) . addImm ( Value ) . getInstr ( ) ; } MachineConstantPool * ConstantPool = MBB . getParent ( ) -> getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) . getContext ( ) ) , Value ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; return BuildMI ( MBB , MI , dl , get ( XCore :: LDWCP_lru6 ) , Reg ) . addConstantPoolIndex ( Idx ) . getInstr ( ) ; } </s>

Emit a series of instructions to load an immediate .


"Missing call preserved mask for calling convention"

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


<s> unsigned SIInstrInfo :: getNumWaitStates ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { default : return 1 ; case AMDGPU :: S_NOP : return MI . getOperand ( 0 ) . getImm ( ) + 1 ; } } </s>

Return the number of wait states that result from executing this instruction .


<s> void NVPTXInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot ) { printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


"LVI load hardening is only supported on 64-bit"

runOnMachineFunction - Emit the function body .


<s> const TargetMachine & getTarget ( ) const { return TM ; } </s>

getTarget - Return the target machine this machine code is compiled with


<s> bool X86InstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Cond , unsigned DstReg , unsigned TrueReg , unsigned FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( ! Subtarget . hasCMov ( ) ) return false ; if ( Cond . size ( ) != 1 ) return false ; if ( ( X86 :: CondCode ) Cond [ 0 ] . getImm ( ) > X86 :: LAST_VALID_COND ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( X86 :: GR16RegClass . hasSubClassEq ( RC ) || X86 :: GR32RegClass . hasSubClassEq ( RC ) || X86 :: GR64RegClass . hasSubClassEq ( RC ) ) { CondCycles = 2 ; TrueCycles = 2 ; FalseCycles = 2 ; return true ; } return false ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> static rtx nvptx_get_drap_rtx ( void ) { return NULL_RTX ; } </s>

Return Dynamic ReAlignment Pointer RTX . For PTX there is n't any .


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override { if ( Count == 0 ) { return true ; } return false ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> bool SparcAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == ".byte" ) return parseDirectiveWord ( 1 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".half" ) return parseDirectiveWord ( 2 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".word" ) return parseDirectiveWord ( 4 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".nword" ) return parseDirectiveWord ( is64Bit ( ) ? 8 : 4 , DirectiveID . getLoc ( ) ) ; if ( is64Bit ( ) && IDVal == ".xword" ) return parseDirectiveWord ( 8 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".register" ) { Parser . eatToEndOfStatement ( ) ; return false ; } return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool nds32_n13_last_two_load_to_e1_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx last_two_def_reg = extract_nth_access_reg ( producer , - 2 ) ; if ( last_two_def_reg == NULL_RTX ) return false ; return n13_consumed_by_e1_dep_p ( consumer , last_two_def_reg ) ; } </s>

Check dependencies from LMW ( N , N-1 ) to E2 .


<s> bool XCoreAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { printOperand ( MI , OpNo ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s>
bool
MipsOs16
::
runOnModule
(
Module
&
M
)
{
bool
usingMask
=
Mips32FunctionMask
.
length
(
)
>
0
;
bool
doneUsingMask
=
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Run on Module MipsOs16 \n"
<<
Mips32FunctionMask
<<
"\n"
)
;
if
(
usingMask
)
LLVM_DEBUG
(
dbgs
(
)
<<
"using mask \n"
<<
Mips32FunctionMask
<<
"\n"
)
;
unsigned
int
functionIndex
=
0
;
bool
modified
=
false
;
for
(
auto
&
F
:
M
)
{
if
(
F
.
isDeclaration
(
)
)
continue
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Working on "
<<
F
.
getName
(
)
<<
"\n"
)
;
if
(
usingMask
)
{
if
(
!
doneUsingMask
)
{
if
(
functionIndex
==
Mips32FunctionMask
.
length
(
)
)
functionIndex
=
0
;
switch
(
Mips32FunctionMask
[
functionIndex
]
)
{
case
'1'
:
LLVM_DEBUG
(
dbgs
(
)
<<
"mask forced mips32: "
<<
F
.
getName
(
)
<<
"\n"
)
;
F
.
addFnAttr
(
"nomips16"
)
;
break
;
case
'.'
:
doneUsingMask
=
true
;
break
;
default
:
break
;
}
functionIndex
++
;
}
}
else
{
if
(
needsFP
(
F
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"os16 forced mips32: "
<<
F
.
getName
(
)
<<
"\n"
)
;
F
.
addFnAttr
(
"nomips16"
)
;
}
else
{
LLVM_DEBUG
(
dbgs
(
)
<<
"os16 forced mips16: "
<<
F
.
getName
(
)
<<
"\n"
)
;
F
.
addFnAttr
(
"mips16"
)
;
}
}
}
return
modified
;
}
</s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .

Mips
Mips
Mips
0
"Run on Module MipsOs16 \n"
Mips
"\n"
"using mask \n"
Mips
"\n"
0
"Working on "
"\n"
Mips
0
Mips
"mask forced mips32: "
"\n"
"nomips16"
"os16 forced mips32: "
"\n"
"nomips16"
"os16 forced mips16: "
"\n"
"mips16"


<s> std :: pair < const TargetRegisterClass * , uint8_t > ARMTargetLowering :: findRepresentativeClass ( EVT VT ) const { const TargetRegisterClass * RRC = 0 ; uint8_t Cost = 1 ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( VT ) ; case MVT :: f32 : case MVT :: f64 : case MVT :: v8i8 : case MVT :: v4i16 : case MVT :: v2i32 : case MVT :: v1i64 : case MVT :: v2f32 : RRC = ARM :: DPRRegisterClass ; break ; case MVT :: v16i8 : case MVT :: v8i16 : case MVT :: v4i32 : case MVT :: v2i64 : case MVT :: v4f32 : case MVT :: v2f64 : RRC = ARM :: DPRRegisterClass ; Cost = 2 ; break ; case MVT :: v4i64 : RRC = ARM :: DPRRegisterClass ; Cost = 4 ; break ; case MVT :: v8i64 : RRC = ARM :: DPRRegisterClass ; Cost = 8 ; break ; } return std :: make_pair ( RRC , Cost ) ; } </s>

Return the largest legal super-reg register class of the register class for the specified type and its associated `` cost '' .


<s> static tree ix86_builtin_decl ( unsigned code , bool ) { if ( code >= IX86_BUILTIN_MAX ) return error_mark_node ; return ix86_builtins [ code ] ; } </s>


<s> bool AArch64InstrInfo :: getMemOperandsWithOffsetWidth ( const MachineInstr & LdSt , SmallVectorImpl < const MachineOperand * > & BaseOps , int64_t & Offset , bool & OffsetIsScalable , unsigned & Width , const TargetRegisterInfo * TRI ) const { if ( ! LdSt . mayLoadOrStore ( ) ) return false ; const MachineOperand * BaseOp ; if ( ! getMemOperandWithOffsetWidth ( LdSt , BaseOp , Offset , OffsetIsScalable , Width , TRI ) ) return false ; BaseOps . push_back ( BaseOp ) ; return true ; } </s>

Get zero or more base operands and the byte offset of an instruction that reads/writes memory .


<s> void X86TargetLowering :: initializeSplitCSR ( MachineBasicBlock * Entry ) const { if ( ! Subtarget . is64Bit ( ) ) return ; X86MachineFunctionInfo * AFI = Entry -> getParent ( ) -> getInfo < X86MachineFunctionInfo > ( ) ; AFI -> setIsSplitCSR ( true ) ; } </s>

Perform necessary initialization to handle a subset of CSRs explicitly via copies .


<s> bool SystemZLDCleanup :: runOnMachineFunction ( MachineFunction & F ) { TII = static_cast < const SystemZInstrInfo * > ( F . getSubtarget ( ) . getInstrInfo ( ) ) ; MF = & F ; SystemZMachineFunctionInfo * MFI = F . getInfo < SystemZMachineFunctionInfo > ( ) ; if ( MFI -> getNumLocalDynamicTLSAccesses ( ) < 2 ) { return false ; } MachineDominatorTree * DT = & getAnalysis < MachineDominatorTree > ( ) ; return VisitNode ( DT -> getRootNode ( ) , 0 ) ; } </s>

SystemZ SystemZ SystemZ SystemZ SystemZ 2 0


<s>
void
WebAssemblyFrameLowering
::
emitEpilogue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
llvm_unreachable
(
"TODO: implement emitEpilogue"
)
;
}
</s>

WebAssembly
WebAssembly
"TODO: implement emitEpilogue"


<s> void LC3AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static unsigned int aarch64_autovectorize_vector_modes ( vector_modes * modes , bool ) { static const machine_mode sve_modes [ ] = { VNx16QImode , VNx8QImode , VNx4QImode , VNx2QImode } ; static const machine_mode advsimd_modes [ ] = { V16QImode , V8QImode , V4HImode , V2SImode } ; unsigned int sve_i = TARGET_SVE ? 0 : ARRAY_SIZE ( sve_modes ) ; unsigned int advsimd_i = 0 ; while ( advsimd_i < ARRAY_SIZE ( advsimd_modes ) ) { if ( sve_i < ARRAY_SIZE ( sve_modes ) && maybe_gt ( GET_MODE_NUNITS ( sve_modes [ sve_i ] ) , GET_MODE_NUNITS ( advsimd_modes [ advsimd_i ] ) ) ) modes -> safe_push ( sve_modes [ sve_i ++ ] ) ; else modes -> safe_push ( advsimd_modes [ advsimd_i ++ ] ) ; } while ( sve_i < ARRAY_SIZE ( sve_modes ) ) modes -> safe_push ( sve_modes [ sve_i ++ ] ) ; unsigned int flags = 0 ; if ( TARGET_SVE && aarch64_sve_compare_costs ) flags |= VECT_COMPARE_COSTS ; return flags ; } </s>

Return a list of possible vector sizes for the vectorizer to iterate over .


<s> void loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const override { loadRegFromStack ( MBB , MBBI , DestReg , FrameIndex , RC , TRI , 0 ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> static void ia64_sysv4_init_libfuncs ( void ) { ia64_init_libfuncs ( ) ; set_optab_libfunc ( eq_optab , TFmode , "_U_Qfeq" ) ; set_optab_libfunc ( ne_optab , TFmode , "_U_Qfne" ) ; set_optab_libfunc ( gt_optab , TFmode , "_U_Qfgt" ) ; set_optab_libfunc ( ge_optab , TFmode , "_U_Qfge" ) ; set_optab_libfunc ( lt_optab , TFmode , "_U_Qflt" ) ; set_optab_libfunc ( le_optab , TFmode , "_U_Qfle" ) ; } </s>

Rename the TFmode libfuncs available from soft-fp in glibc using the HPUX conventions .


<s> static rtx mep_legitimize_arg ( const struct insn_operand_data * operand , rtx arg , int unsigned_p ) { if ( GET_CODE ( arg ) == CONST_INT ) { if ( GET_MODE_CLASS ( operand -> mode ) != MODE_INT ) return 0 ; } else if ( GET_CODE ( arg ) == CONST_DOUBLE ) ; else if ( GET_MODE_SIZE ( GET_MODE ( arg ) ) != GET_MODE_SIZE ( operand -> mode ) ) { if ( GET_MODE_CLASS ( operand -> mode ) != GET_MODE_CLASS ( GET_MODE ( arg ) ) ) return 0 ; if ( operand -> constraint [ 0 ] != '=' ) arg = convert_to_mode ( operand -> mode , arg , unsigned_p ) ; } if ( operand -> constraint [ 0 ] == '=' && ( ! REG_P ( arg ) || ! ( CONTROL_REGNO_P ( REGNO ( arg ) ) || CCR_REGNO_P ( REGNO ( arg ) ) || CR_REGNO_P ( REGNO ( arg ) ) ) ) ) return gen_reg_rtx ( operand -> mode ) ; arg = mep_convert_arg ( operand -> mode , arg ) ; if ( operand -> predicate ( arg , operand -> mode ) ) return arg ; if ( GET_CODE ( arg ) == CONST_INT || GET_CODE ( arg ) == CONST_DOUBLE ) arg = force_reg ( operand -> mode , arg ) ; else arg = mep_convert_arg ( operand -> mode , force_reg ( GET_MODE ( arg ) , arg ) ) ; if ( operand -> predicate ( arg , operand -> mode ) ) return arg ; return 0 ; } </s>

Try to make intrinsic argument ARG match the given operand . UNSIGNED_P is true if the argument has an unsigned type .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < TargetPassConfig > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool NVPTXAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , O ) ; case 'r' : break ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>


<s> SDValue PPCTargetLowering :: LowerCall ( TargetLowering :: CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const { SelectionDAG & DAG = CLI . DAG ; SDLoc & dl = CLI . DL ; SmallVector < ISD :: OutputArg , 32 > & Outs = CLI . Outs ; SmallVector < SDValue , 32 > & OutVals = CLI . OutVals ; SmallVector < ISD :: InputArg , 32 > & Ins = CLI . Ins ; SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; bool & isTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool isVarArg = CLI . IsVarArg ; if ( isTailCall ) isTailCall = IsEligibleForTailCallOptimization ( Callee , CallConv , isVarArg , Ins , DAG ) ; if ( PPCSubTarget . isSVR4ABI ( ) ) { if ( PPCSubTarget . isPPC64 ( ) ) return LowerCall_64SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; else return LowerCall_32SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; } return LowerCall_Darwin ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; } </s>

This hook must be implemented to lower calls into the specified DAG .

PowerPC PPC ISD::OutputArg 32 32 ISD::InputArg 32 PPC PPC PPC


Emit target-specific code that performs a memcpy .


<s> int eligible_for_sibcall_delay ( rtx trial ) { rtx pat ; if ( GET_CODE ( trial ) != INSN || GET_CODE ( PATTERN ( trial ) ) != SET ) return 0 ; if ( get_attr_length ( trial ) != 1 ) return 0 ; pat = PATTERN ( trial ) ; if ( sparc_leaf_function_p ) { if ( LEAF_SIBCALL_SLOT_RESERVED_P ) return 0 ; if ( reg_mentioned_p ( gen_rtx_REG ( Pmode , 1 ) , pat ) ) return 0 ; return 1 ; } if ( GET_CODE ( SET_DEST ( pat ) ) != REG || ( REGNO ( SET_DEST ( pat ) ) >= 8 && REGNO ( SET_DEST ( pat ) ) < 24 ) || REGNO ( SET_DEST ( pat ) ) >= 32 ) return 0 ; if ( reg_mentioned_p ( gen_rtx_REG ( Pmode , 15 ) , pat ) ) return 0 ; return eligible_for_restore_insn ( trial , false ) ; } </s>

Return nonzero if TRIAL can go into the sibling call 's delay slot .


<s>
bool
TPCInstrCompress
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
MF
=
&
Fn
;
TII
=
Fn
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
ItinData
=
Fn
.
getSubtarget
(
)
.
getInstrItineraryData
(
)
;
TRI
=
Fn
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
TRI
=
Fn
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
return
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"\n*** TPC Inst Compression\n"
)
;
prevMI
=
nullptr
;
for
(
auto
&
MBB
:
Fn
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Processing BB#"
<<
MBB
.
getNumber
(
)
<<
"\n"
)
;
if
(
MBB
.
empty
(
)
)
{
continue
;
}
processBB
(
MBB
)
;
}
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .

TPC
TPC
"\n*** TPC Inst Compression\n"
"Processing BB#"
"\n"


<s> bool runOnMachineFunction ( MachineFunction & F ) { bool Changed = false ; F . getRegInfo ( ) . invalidateLiveness ( ) ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; return Changed ; } </s>


<s> const char * ARCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case ARCISD :: BL : return "ARCISD::BL" ; case ARCISD :: CMOV : return "ARCISD::CMOV" ; case ARCISD :: CMP : return "ARCISD::CMP" ; case ARCISD :: BRcc : return "ARCISD::BRcc" ; case ARCISD :: RET : return "ARCISD::RET" ; case ARCISD :: GAWRAPPER : return "ARCISD::GAWRAPPER" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

ARC ARC ARCISD::BL "ARCISD::BL" ARCISD::CMOV "ARCISD::CMOV" ARCISD::CMP "ARCISD::CMP" ARCISD::BRcc "ARCISD::BRcc" ARCISD::RET "ARCISD::RET" ARCISD::GAWRAPPER "ARCISD::GAWRAPPER"


<s> void AArch64PassConfig :: addPreEmitPass ( ) { if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Aggressive && EnableLoadStoreOpt ) addPass ( createAArch64LoadStoreOptimizationPass ( ) ) ; if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Aggressive && EnableAArch64CopyPropagation ) addPass ( createMachineCopyPropagationPass ( true ) ) ; addPass ( createAArch64A53Fix835769 ( ) ) ; if ( EnableBranchTargets ) addPass ( createAArch64BranchTargetsPass ( ) ) ; if ( BranchRelaxation ) addPass ( & BranchRelaxationPassID ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) { addPass ( createCFGuardLongjmpPass ( ) ) ; addPass ( createEHContGuardCatchretPass ( ) ) ; } if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCompressJumpTables ) addPass ( createAArch64CompressJumpTablesPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
bool
processBlock
(
MachineBasicBlock
&
MBB
)
{
bool
Changed
=
false
;
bool
Is64Bit
=
MBB
.
getParent
(
)
->
getSubtarget
<
PPCSubtarget
>
(
)
.
isPPC64
(
)
;
for
(
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
,
IE
=
MBB
.
end
(
)
;
I
!=
IE
;
)
{
MachineInstr
&
MI
=
*
I
;
if
(
MI
.
getOpcode
(
)
!=
PPC
::
ADDItlsgdLADDR
&&
MI
.
getOpcode
(
)
!=
PPC
::
ADDItlsldLADDR
&&
MI
.
getOpcode
(
)
!=
PPC
::
ADDItlsgdLADDR32
&&
MI
.
getOpcode
(
)
!=
PPC
::
ADDItlsldLADDR32
)
{
++
I
;
continue
;
}
DEBUG
(
dbgs
(
)
<<
"TLS Dynamic Call Fixup:\n    "
<<
MI
)
;
unsigned
OutReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
unsigned
InReg
=
MI
.
getOperand
(
1
)
.
getReg
(
)
;
DebugLoc
DL
=
MI
.
getDebugLoc
(
)
;
unsigned
GPR3
=
Is64Bit
PPC
::
X3
:
PPC
::
R3
;
unsigned
Opc1
,
Opc2
;
const
unsigned
OrigRegs
[
]
=
{
OutReg
,
InReg
,
GPR3
}
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Opcode inconsistency error"
)
;
case
PPC
::
ADDItlsgdLADDR
:
Opc1
=
PPC
::
ADDItlsgdL
;
Opc2
=
PPC
::
GETtlsADDR
;
break
;
case
PPC
::
ADDItlsldLADDR
:
Opc1
=
PPC
::
ADDItlsldL
;
Opc2
=
PPC
::
GETtlsldADDR
;
break
;
case
PPC
::
ADDItlsgdLADDR32
:
Opc1
=
PPC
::
ADDItlsgdL32
;
Opc2
=
PPC
::
GETtlsADDR32
;
break
;
case
PPC
::
ADDItlsldLADDR32
:
Opc1
=
PPC
::
ADDItlsldL32
;
Opc2
=
PPC
::
GETtlsldADDR32
;
break
;
}
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
PPC
::
ADJCALLSTACKDOWN
)
)
.
addImm
(
0
)
;
MachineInstr
*
Addi
=
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
Opc1
)
,
GPR3
)
.
addReg
(
InReg
)
;
Addi
->
addOperand
(
MI
.
getOperand
(
2
)
)
;
MachineBasicBlock
::
iterator
First
=
I
;
First
;
MachineInstr
*
Call
=
(
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
Opc2
)
,
GPR3
)
.
addReg
(
GPR3
)
)
;
Call
->
addOperand
(
MI
.
getOperand
(
3
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
PPC
::
ADJCALLSTACKUP
)
)
.
addImm
(
0
)
.
addImm
(
0
)
;
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
TargetOpcode
::
COPY
)
,
OutReg
)
.
addReg
(
GPR3
)
;
MachineBasicBlock
::
iterator
Last
=
I
;
Last
;
++
I
;
MI
.
removeFromParent
(
)
;
LIS
->
repairIntervalsInRange
(
&
MBB
,
First
,
Last
,
OrigRegs
)
;
Changed
=
true
;
}
return
Changed
;
}
</s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s> int SIInstrInfo :: pseudoToMCOpcode ( int Opcode ) const { SIEncodingFamily Gen = subtargetEncodingFamily ( ST ) ; if ( ( get ( Opcode ) . TSFlags & SIInstrFlags :: renamedInGFX9 ) != 0 && ST . getGeneration ( ) == AMDGPUSubtarget :: GFX9 ) Gen = SIEncodingFamily :: GFX9 ; if ( ST . hasUnpackedD16VMem ( ) && ( get ( Opcode ) . TSFlags & SIInstrFlags :: D16Buf ) ) Gen = SIEncodingFamily :: GFX80 ; if ( get ( Opcode ) . TSFlags & SIInstrFlags :: SDWA ) { switch ( ST . getGeneration ( ) ) { default : Gen = SIEncodingFamily :: SDWA ; break ; case AMDGPUSubtarget :: GFX9 : Gen = SIEncodingFamily :: SDWA9 ; break ; case AMDGPUSubtarget :: GFX10 : Gen = SIEncodingFamily :: SDWA10 ; break ; } } if ( isMAI ( Opcode ) ) { int MFMAOp = AMDGPU :: getMFMAEarlyClobberOp ( Opcode ) ; if ( MFMAOp != - 1 ) Opcode = MFMAOp ; } int MCOp = AMDGPU :: getMCOpcode ( Opcode , Gen ) ; if ( MCOp == - 1 ) return Opcode ; if ( ST . hasGFX90AInsts ( ) ) { uint16_t NMCOp = ( uint16_t ) - 1 ; if ( ST . hasGFX940Insts ( ) ) NMCOp = AMDGPU :: getMCOpcode ( Opcode , SIEncodingFamily :: GFX940 ) ; if ( NMCOp == ( uint16_t ) - 1 ) NMCOp = AMDGPU :: getMCOpcode ( Opcode , SIEncodingFamily :: GFX90A ) ; if ( NMCOp == ( uint16_t ) - 1 ) NMCOp = AMDGPU :: getMCOpcode ( Opcode , SIEncodingFamily :: GFX9 ) ; if ( NMCOp != ( uint16_t ) - 1 ) MCOp = NMCOp ; } if ( MCOp == ( uint16_t ) - 1 ) return - 1 ; if ( isAsmOnlyOpcode ( MCOp ) ) return - 1 ; return MCOp ; } </s>

Return a target-specific opcode if Opcode is a pseudo instruction .


<s> static void ix86_emit_leave ( void ) { struct machine_function * m = cfun -> machine ; rtx insn = emit_insn ( ix86_gen_leave ( ) ) ; ix86_add_queued_cfa_restore_notes ( insn ) ; gcc_assert ( m -> fs . fp_valid ) ; m -> fs . sp_valid = true ; m -> fs . sp_offset = m -> fs . fp_offset - UNITS_PER_WORD ; m -> fs . fp_valid = false ; if ( m -> fs . cfa_reg == hard_frame_pointer_rtx ) { m -> fs . cfa_reg = stack_pointer_rtx ; m -> fs . cfa_offset = m -> fs . sp_offset ; add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , stack_pointer_rtx , m -> fs . sp_offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } ix86_add_cfa_restore_note ( insn , hard_frame_pointer_rtx , m -> fs . fp_offset ) ; } </s>

Emit code and notes for the LEAVE instruction .


<s> bool HexagonDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { SDValue Inp = Op , Res ; switch ( ConstraintID ) { default : return true ; case InlineAsm :: Constraint_o : case InlineAsm :: Constraint_v : case InlineAsm :: Constraint_m : if ( SelectAddrFI ( Inp , Res ) ) OutOps . push_back ( Res ) ; else OutOps . push_back ( Inp ) ; break ; } OutOps . push_back ( CurDAG -> getTargetConstant ( 0 , SDLoc ( Op ) , MVT :: i32 ) ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


"We have a different number of location and args?!"

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> static bool xtensa_mode_dependent_address_p ( const_rtx addr , addr_space_t as ATTRIBUTE_UNUSED ) { return constantpool_address_p ( addr ) ; } </s>

Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P . Treat constant-pool references as `` mode dependent '' since they can only be accessed with SImode loads . This works around a bug in the combiner where a constant pool reference is temporarily converted to an HImode load , which is then assumed to zero-extend based on our definition of LOAD_EXTEND_OP . This is wrong because the high bits of a 16-bit value in the constant pool are now sign-extended by default .


<s>
bool
TPCResourceModel
::
reserveResources
(
SUnit
*
SU
)
{
bool
startNewCycle
=
false
;
if
(
!
SU
)
{
ResourcesModel
->
clearResources
(
)
;
savePacket
(
)
;
Packet
.
clear
(
)
;
TotalPackets
++
;
return
false
;
}
if
(
!
isResourceAvailable
(
SU
)
)
{
ResourcesModel
->
clearResources
(
)
;
savePacket
(
)
;
Packet
.
clear
(
)
;
TotalPackets
++
;
startNewCycle
=
true
;
}
if
(
!
SU
->
getInstr
(
)
->
isPseudo
(
)
)
{
ResourcesModel
->
reserveResources
(
*
SU
->
getInstr
(
)
)
;
Packet
.
push_back
(
SU
)
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Packet["
<<
TotalPackets
<<
"]:\n"
)
;
for
(
unsigned
i
=
0
,
e
=
Packet
.
size
(
)
;
i
!=
e
;
++
i
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"\t["
<<
i
<<
"] SU("
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
Packet
[
i
]
->
NodeNum
<<
")\t"
)
;
LLVM_DEBUG
(
Packet
[
i
]
->
getInstr
(
)
->
dump
(
)
)
;
}
if
(
Packet
.
size
(
)
>=
4
)
{
ResourcesModel
->
clearResources
(
)
;
savePacket
(
)
;
Packet
.
clear
(
)
;
TotalPackets
++
;
startNewCycle
=
true
;
}
return
startNewCycle
;
}
</s>


<s> bool isReg ( ) const { return false ; } </s>


<s> bool ARMCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto DL = MIRBuilder . getMF ( ) . getDataLayout ( ) ; auto & TLI = * getTLI < ARMTargetLowering > ( ) ; auto & Args = F . getArgumentList ( ) ; unsigned ArgIdx = 0 ; for ( auto & Arg : Args ) { ArgIdx ++ ; if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( ArgIdx > 4 && Arg . getType ( ) -> getIntegerBitWidth ( ) != 32 ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; SmallVector < ArgInfo , 8 > ArgInfos ; unsigned Idx = 0 ; for ( auto & Arg : Args ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + 1 , DL , F ) ; ArgInfos . push_back ( AInfo ) ; Idx ++ ; } FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) ) ; return handleAssignments ( MIRBuilder , AssignFn , ArgInfos , ArgHandler ) ; } </s>


<s> SDValue SITargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( N ) ; EVT VT = N -> getValueType ( 0 ) ; switch ( N -> getOpcode ( ) ) { default : return AMDGPUTargetLowering :: PerformDAGCombine ( N , DCI ) ; case ISD :: SETCC : { SDValue Arg0 = N -> getOperand ( 0 ) ; SDValue Arg1 = N -> getOperand ( 1 ) ; SDValue CC = N -> getOperand ( 2 ) ; ConstantSDNode * C = nullptr ; ISD :: CondCode CCOp = dyn_cast < CondCodeSDNode > ( CC ) -> get ( ) ; if ( VT == MVT :: i1 && Arg0 . getOpcode ( ) == ISD :: SIGN_EXTEND && Arg0 . getOperand ( 0 ) . getValueType ( ) == MVT :: i1 && ( C = dyn_cast < ConstantSDNode > ( Arg1 ) ) && C -> isNullValue ( ) && CCOp == ISD :: SETNE ) { return SimplifySetCC ( VT , Arg0 . getOperand ( 0 ) , DAG . getConstant ( 0 , MVT :: i1 ) , CCOp , true , DCI , DL ) ; } break ; } case AMDGPUISD :: CVT_F32_UBYTE0 : case AMDGPUISD :: CVT_F32_UBYTE1 : case AMDGPUISD :: CVT_F32_UBYTE2 : case AMDGPUISD :: CVT_F32_UBYTE3 : { unsigned Offset = N -> getOpcode ( ) - AMDGPUISD :: CVT_F32_UBYTE0 ; SDValue Src = N -> getOperand ( 0 ) ; APInt Demanded = APInt :: getBitsSet ( 32 , 8 * Offset , 8 * Offset + 8 ) ; APInt KnownZero , KnownOne ; TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( ) , ! DCI . isBeforeLegalizeOps ( ) ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLO . ShrinkDemandedConstant ( Src , Demanded ) || TLI . SimplifyDemandedBits ( Src , Demanded , KnownZero , KnownOne , TLO ) ) { DCI . CommitTargetLoweringOpt ( TLO ) ; } break ; } case ISD :: UINT_TO_FP : { return performUCharToFloatCombine ( N , DCI ) ; } } return AMDGPUTargetLowering :: PerformDAGCombine ( N , DCI ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


"Only base registers and frame indices are supported."

Returns true if the two given memory operations should be scheduled adjacent .


<s> static constexpr ArgDescriptor createRegister ( Register Reg , unsigned Mask = ~ 0u ) { return ArgDescriptor ( Reg , Mask , false , true ) ; } </s>

.cfi_register Previous value of Register1 is saved in register Register2 .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"SI Load / Store Optimizer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static rtx aarch64_gen_loadwb_pair ( machine_mode mode , rtx base , rtx reg , rtx reg2 , HOST_WIDE_INT adjustment ) { switch ( mode ) { case DImode : return gen_loadwb_pairdi_di ( base , base , reg , reg2 , GEN_INT ( adjustment ) , GEN_INT ( UNITS_PER_WORD ) ) ; case DFmode : return gen_loadwb_pairdf_di ( base , base , reg , reg2 , GEN_INT ( adjustment ) , GEN_INT ( UNITS_PER_WORD ) ) ; default : gcc_unreachable ( ) ; } } </s>

Load the pair of register REG , REG2 of mode MODE from stack location BASE , adjusting it by ADJUSTMENT afterwards .


<s> std :: pair < unsigned , const TargetRegisterClass * > HexagonTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : switch ( VT . SimpleTy ) { default : return { 0u , nullptr } ; case MVT :: i1 : case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : case MVT :: f32 : return { 0u , & Hexagon :: IntRegsRegClass } ; case MVT :: i64 : case MVT :: f64 : return { 0u , & Hexagon :: DoubleRegsRegClass } ; } break ; case 'a' : if ( VT != MVT :: i32 ) return { 0u , nullptr } ; return { 0u , & Hexagon :: ModRegsRegClass } ; case 'q' : switch ( VT . getSizeInBits ( ) ) { default : return { 0u , nullptr } ; case 512 : case 1024 : return { 0u , & Hexagon :: HvxQRRegClass } ; } break ; case 'v' : switch ( VT . getSizeInBits ( ) ) { default : return { 0u , nullptr } ; case 512 : return { 0u , & Hexagon :: HvxVRRegClass } ; case 1024 : if ( Subtarget . hasV60Ops ( ) && Subtarget . useHVX128BOps ( ) ) return { 0u , & Hexagon :: HvxVRRegClass } ; return { 0u , & Hexagon :: HvxWRRegClass } ; case 2048 : return { 0u , & Hexagon :: HvxWRRegClass } ; } break ; default : return { 0u , nullptr } ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> unsigned getMaxCallFrameSize ( ) const { return MaxCallFrameSize ; } </s>

Return the maximum size of a call frame that must be allocated for an outgoing function call .


"failed to spill SGPR to VGPR when allocated"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> TargetPassConfig * Z80oldTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new Z80oldPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> static void frv_optimize_membar ( void ) { basic_block bb ; struct frv_io * first_io ; rtx * last_membar ; compute_bb_for_insn ( ) ; first_io = xcalloc ( last_basic_block , sizeof ( struct frv_io ) ) ; last_membar = xcalloc ( last_basic_block , sizeof ( rtx ) ) ; FOR_EACH_BB ( bb ) frv_optimize_membar_local ( bb , & first_io [ bb -> index ] , & last_membar [ bb -> index ] ) ; FOR_EACH_BB ( bb ) if ( last_membar [ bb -> index ] != 0 ) frv_optimize_membar_global ( bb , first_io , last_membar [ bb -> index ] ) ; free ( first_io ) ; free ( last_membar ) ; } </s>

Remove redundant membars from the current function .


<s> rtx loongarch_prefetch_cookie ( rtx write , rtx locality ) { if ( INTVAL ( locality ) <= 0 ) return GEN_INT ( INTVAL ( write ) + 4 ) ; if ( INTVAL ( locality ) <= 2 ) return write ; return GEN_INT ( INTVAL ( write ) + 6 ) ; } </s>

Given that we have an rtx of the form ( prefetch ... WRITE LOCALITY ) , return the first operand of the associated PREF or PREFX insn .


<s> static void csky_output_pic_addr_const ( FILE * stream , rtx x , int code ) { if ( GET_CODE ( x ) != UNSPEC ) return ; if ( UNSPEC_TLS == XINT ( x , 1 ) ) { return ; } csky_print_operand ( stream , XVECEXP ( x , 0 , 0 ) , code ) ; switch ( XINT ( x , 1 ) ) { case UNSPEC_PIC_SYMBOL_GOTOFF : fputs ( "@GOTOFF" , stream ) ; break ; case UNSPEC_PIC_SYMBOL_PLT : fputs ( "@PLT" , stream ) ; break ; case UNSPEC_PIC_SYMBOL_GOT : fputs ( "@GOT" , stream ) ; break ; case UNSPEC_PIC_SYMBOL_GOTPC : fputs ( "@GOTPC" , stream ) ; break ; case UNSPEC_PIC_SYMBOL_BSR : break ; default : break ; } } </s>

Print the UNSPEC operand in X to the STREAM .


<s> void DCPU16FrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; DCPU16MachineFunctionInfo * DCPU16FI = MF . getInfo < DCPU16MachineFunctionInfo > ( ) ; const DCPU16InstrInfo & TII = * static_cast < const DCPU16InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; uint64_t NumBytes = StackSize - DCPU16FI -> getCalleeSavedFrameSize ( ) ; if ( hasFP ( MF ) ) { MFI -> setOffsetAdjustment ( - NumBytes ) ; BuildMI ( MBB , MBBI , DL , TII . get ( DCPU16 :: PUSH16r ) ) . addReg ( DCPU16 :: J , RegState :: Kill ) ; BuildMI ( MBB , MBBI , DL , TII . get ( DCPU16 :: MOV16rr ) , DCPU16 :: J ) . addReg ( DCPU16 :: SP ) ; for ( MachineFunction :: iterator I = llvm :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( DCPU16 :: J ) ; } while ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == DCPU16 :: PUSH16r ) ) ++ MBBI ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes ) { if ( NumBytes ) { MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( DCPU16 :: SUB16ri ) , DCPU16 :: SP ) . addReg ( DCPU16 :: SP ) . addImm ( NumBytes ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; } } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> void MOSMCELFStreamer :: initSections ( bool NoExecStack , const MCSubtargetInfo & STI ) { MCContext & Ctx = getContext ( ) ; SwitchSection ( Ctx . getObjectFileInfo ( ) -> getTextSection ( ) ) ; emitCodeAlignment ( 1 , & STI ) ; if ( NoExecStack ) SwitchSection ( Ctx . getAsmInfo ( ) -> getNonexecutableStackSection ( Ctx ) ) ; } </s>

Create the default sections and set the initial one .


<s> bool RISCVTargetLowering :: decomposeMulByConstant ( LLVMContext & Context , EVT VT , SDValue C ) const { if ( VT . isScalarInteger ( ) ) { if ( ! Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) ) return false ; if ( auto * ConstNode = dyn_cast < ConstantSDNode > ( C . getNode ( ) ) ) { if ( ConstNode -> getAPIntValue ( ) . getBitWidth ( ) > 8 * sizeof ( int64_t ) ) return false ; int64_t Imm = ConstNode -> getSExtValue ( ) ; if ( isPowerOf2_64 ( Imm + 1 ) || isPowerOf2_64 ( Imm - 1 ) || isPowerOf2_64 ( 1 - Imm ) || isPowerOf2_64 ( - 1 - Imm ) ) return true ; } } return false ; } </s>

Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds .


<s> const TargetRegisterClass * X86InstructionSelector :: getRegClass ( LLT Ty , unsigned Reg , MachineRegisterInfo & MRI ) const { const RegisterBank & RegBank = * RBI . getRegBank ( Reg , MRI , TRI ) ; return getRegClass ( Ty , RegBank ) ; } </s>

Given a machine instruction descriptor , returns the register class constraint for OpNum , or NULL .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { initialize ( MF ) ; return simplifyCode ( ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return createRISCVObjectWriter ( OS , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> struct rtx_def * clipper_builtin_saveregs ( ) { rtx block , addr , r0_addr , r1_addr , f0_addr , f1_addr , mem ; int set = get_varargs_alias_set ( ) ; block = assign_stack_local ( BLKmode , 6 * UNITS_PER_WORD , 2 * BITS_PER_WORD ) ; RTX_UNCHANGING_P ( block ) = 1 ; RTX_UNCHANGING_P ( XEXP ( block , 0 ) ) = 1 ; addr = XEXP ( block , 0 ) ; r0_addr = addr ; r1_addr = plus_constant ( addr , 4 ) ; f0_addr = plus_constant ( addr , 8 ) ; f1_addr = plus_constant ( addr , 16 ) ; mem = gen_rtx_MEM ( SImode , r0_addr ) ; set_mem_alias_set ( mem , set ) ; emit_move_insn ( mem , gen_rtx_REG ( SImode , 0 ) ) ; mem = gen_rtx_MEM ( SImode , r1_addr ) ; set_mem_alias_set ( mem , set ) ; emit_move_insn ( mem , gen_rtx_REG ( SImode , 1 ) ) ; mem = gen_rtx_MEM ( DFmode , f0_addr ) ; set_mem_alias_set ( mem , set ) ; emit_move_insn ( mem , gen_rtx_REG ( DFmode , 16 ) ) ; mem = gen_rtx_MEM ( DFmode , f1_addr ) ; set_mem_alias_set ( mem , set ) ; emit_move_insn ( mem , gen_rtx_REG ( DFmode , 17 ) ) ; return addr ; } </s>

Dump the argument register to the stack ; return the location of the block .


<s> bool ARMTargetMachine :: addInstSelector ( PassManagerBase & PM , bool Fast ) { PM . add ( createARMISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool X86InstrInfo :: areLoadsFromSameBasePtr ( SDNode * Load1 , SDNode * Load2 , int64_t & Offset1 , int64_t & Offset2 ) const { if ( ! Load1 -> isMachineOpcode ( ) || ! Load2 -> isMachineOpcode ( ) ) return false ; unsigned Opc1 = Load1 -> getMachineOpcode ( ) ; unsigned Opc2 = Load2 -> getMachineOpcode ( ) ; switch ( Opc1 ) { default : return false ; case X86 :: MOV8rm : case X86 :: MOV16rm : case X86 :: MOV32rm : case X86 :: MOV64rm : case X86 :: LD_Fp32m : case X86 :: LD_Fp64m : case X86 :: LD_Fp80m : case X86 :: MOVSSrm : case X86 :: MOVSDrm : case X86 :: MMX_MOVD64rm : case X86 :: MMX_MOVQ64rm : case X86 :: FsMOVAPSrm : case X86 :: FsMOVAPDrm : case X86 :: MOVAPSrm : case X86 :: MOVUPSrm : case X86 :: MOVUPSrm_Int : case X86 :: MOVAPDrm : case X86 :: MOVDQArm : case X86 :: MOVDQUrm : case X86 :: MOVDQUrm_Int : break ; } switch ( Opc2 ) { default : return false ; case X86 :: MOV8rm : case X86 :: MOV16rm : case X86 :: MOV32rm : case X86 :: MOV64rm : case X86 :: LD_Fp32m : case X86 :: LD_Fp64m : case X86 :: LD_Fp80m : case X86 :: MOVSSrm : case X86 :: MOVSDrm : case X86 :: MMX_MOVD64rm : case X86 :: MMX_MOVQ64rm : case X86 :: FsMOVAPSrm : case X86 :: FsMOVAPDrm : case X86 :: MOVAPSrm : case X86 :: MOVUPSrm : case X86 :: MOVUPSrm_Int : case X86 :: MOVAPDrm : case X86 :: MOVDQArm : case X86 :: MOVDQUrm : case X86 :: MOVDQUrm_Int : break ; } if ( Load1 -> getOperand ( 0 ) != Load2 -> getOperand ( 0 ) || Load1 -> getOperand ( 5 ) != Load2 -> getOperand ( 5 ) ) return false ; if ( Load1 -> getOperand ( 4 ) != Load2 -> getOperand ( 4 ) ) return false ; if ( Load1 -> getOperand ( 1 ) == Load2 -> getOperand ( 1 ) && Load1 -> getOperand ( 2 ) == Load2 -> getOperand ( 2 ) ) { if ( cast < ConstantSDNode > ( Load1 -> getOperand ( 1 ) ) -> getZExtValue ( ) != 1 ) return false ; if ( isa < ConstantSDNode > ( Load1 -> getOperand ( 3 ) ) && isa < ConstantSDNode > ( Load2 -> getOperand ( 3 ) ) ) { Offset1 = cast < ConstantSDNode > ( Load1 -> getOperand ( 3 ) ) -> getSExtValue ( ) ; Offset2 = cast < ConstantSDNode > ( Load2 -> getOperand ( 3 ) ) -> getSExtValue ( ) ; return true ; } } return false ; } </s>

areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address .


<s> void RISCVInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned LoadOpcode , StoreOpcode ; getLoadStoreOpcodes ( RC , LoadOpcode , StoreOpcode ) ; addFrameReference ( BuildMI ( MBB , MBBI , DL , get ( LoadOpcode ) , DestReg ) , FrameIdx ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> void Thumb2InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { if ( ! ARM :: GPRRegClass . contains ( DestReg , SrcReg ) ) return ARMBaseInstrInfo :: copyPhysReg ( MBB , I , DL , DestReg , SrcReg , KillSrc ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: tMOVr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ) ; } </s>


<s> bool e8_consumed_by_addr_in_p ( rtx_insn * consumer , rtx def_reg ) { return n8_consumed_by_addr_in_p ( consumer , def_reg ) ; } </s>

Check the dependency between the producer defining DEF_REG and CONSUMER requiring input operand at AG ( II ) .


<s>
void
dump
(
const
TargetRegisterInfo
*
TRI
,
int
depth
=
0
)
override
{
dumpDepth
(
depth
)
;
dbgs
(
)
<<
"Region: "
<<
(
void
*
)
Region
;
dbgs
(
)
<<
" In: "
<<
PrintReg
(
getBBSelectRegIn
(
)
,
TRI
)
;
dbgs
(
)
<<
", Out: "
<<
PrintReg
(
getBBSelectRegOut
(
)
,
TRI
)
<<
"\n"
;
dumpDepth
(
depth
)
;
if
(
getSucc
(
)
)
dbgs
(
)
<<
"Succ: "
<<
getSucc
(
)
->
getNumber
(
)
<<
"\n"
;
else
dbgs
(
)
<<
"Succ: none \n"
;
for
(
auto
MRTI
:
Children
)
{
MRTI
->
dump
(
TRI
,
depth
+
1
)
;
}
}
</s>

Dump the plan to stderr ( for debugging ) .

AMDGPU
0
"Region: "
" In: "
", Out: "
"\n"
"Succ: "
"\n"
"Succ: none \n"
1


"unable to compute real location of stacked parameter"

Handle a special case when computing the offset of an argument from the frame pointer .


<s> bool useAA ( ) const override { return UseAA ; } </s>

Enable use of alias analysis during code generation ( during MI scheduling , DAGCombine , etc . ) .


<s> VariantKind getKind ( ) const { return Kind ; } </s>


<s>
void
replaceSuccessorWith
(
TerminatorInst
*
Terminator
,
BasicBlock
*
OriginalBB
,
BasicBlock
*
NewBB
)
{
assert
(
Terminator
&&
OriginalBB
&&
NewBB
)
;
if
(
auto
*
Branch
=
dyn_cast
<
BranchInst
>
(
Terminator
)
)
{
if
(
Branch
->
getSuccessor
(
0
)
==
OriginalBB
)
{
Branch
->
setSuccessor
(
0
,
NewBB
)
;
return
;
}
assert
(
Branch
->
isConditional
(
)
&&
"OriginalBB missing"
)
;
assert
(
Branch
->
getSuccessor
(
1
)
==
OriginalBB
&&
"OriginalBB is missing"
)
;
Branch
->
setSuccessor
(
1
,
NewBB
)
;
return
;
}
llvm_unreachable
(
"Not implemented"
)
;
}
</s>

Replace specified successor OldBB to point at the provided block .


"custom instruction opcode must be a compile-time "

"constant in the range 0-255 for %<__builtin_custom_%s%>"

Helper function for expanding custom builtins .


<s>
bool
A15SDOptimizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
if
(
skipFunction
(
Fn
.
getFunction
(
)
)
)
return
false
;
const
ARMSubtarget
&
STI
=
Fn
.
getSubtarget
<
ARMSubtarget
>
(
)
;
if
(
!
(
STI
.
isCortexA15
(
)
&&
STI
.
hasNEON
(
)
)
)
return
false
;
TII
=
STI
.
getInstrInfo
(
)
;
TRI
=
STI
.
getRegisterInfo
(
)
;
MRI
=
&
Fn
.
getRegInfo
(
)
;
bool
Modified
=
false
;
DEBUG
(
dbgs
(
)
<<
"Running on function "
<<
Fn
.
getName
(
)
<<
"\n"
)
;
DeadInstr
.
clear
(
)
;
Replacements
.
clear
(
)
;
for
(
MachineBasicBlock
&
MBB
:
Fn
)
{
for
(
MachineInstr
&
MI
:
MBB
)
{
Modified
|=
runOnInstruction
(
&
MI
)
;
}
}
for
(
MachineInstr
*
MI
:
DeadInstr
)
{
MI
->
eraseFromParent
(
)
;
}
return
Modified
;
}
</s>


<s> static rtx spu_addr_space_convert ( rtx op , tree from_type , tree to_type ) { addr_space_t from_as = TYPE_ADDR_SPACE ( TREE_TYPE ( from_type ) ) ; addr_space_t to_as = TYPE_ADDR_SPACE ( TREE_TYPE ( to_type ) ) ; gcc_assert ( from_as == ADDR_SPACE_GENERIC || from_as == ADDR_SPACE_EA ) ; gcc_assert ( to_as == ADDR_SPACE_GENERIC || to_as == ADDR_SPACE_EA ) ; if ( to_as == ADDR_SPACE_GENERIC && from_as == ADDR_SPACE_EA ) { rtx result , ls ; ls = gen_const_mem ( DImode , gen_rtx_SYMBOL_REF ( Pmode , "__ea_local_store" ) ) ; set_mem_align ( ls , 128 ) ; result = gen_reg_rtx ( Pmode ) ; ls = force_reg ( Pmode , convert_modes ( Pmode , DImode , ls , 1 ) ) ; op = force_reg ( Pmode , convert_modes ( Pmode , EAmode , op , 1 ) ) ; ls = emit_conditional_move ( ls , NE , op , const0_rtx , Pmode , ls , const0_rtx , Pmode , 1 ) ; emit_insn ( gen_subsi3 ( result , op , ls ) ) ; return result ; } else if ( to_as == ADDR_SPACE_EA && from_as == ADDR_SPACE_GENERIC ) { rtx result , ls ; ls = gen_const_mem ( DImode , gen_rtx_SYMBOL_REF ( Pmode , "__ea_local_store" ) ) ; set_mem_align ( ls , 128 ) ; result = gen_reg_rtx ( EAmode ) ; ls = force_reg ( EAmode , convert_modes ( EAmode , DImode , ls , 1 ) ) ; op = force_reg ( Pmode , op ) ; ls = emit_conditional_move ( ls , NE , op , const0_rtx , Pmode , ls , const0_rtx , EAmode , 1 ) ; op = force_reg ( EAmode , convert_modes ( EAmode , Pmode , op , 1 ) ) ; if ( EAmode == SImode ) emit_insn ( gen_addsi3 ( result , op , ls ) ) ; else emit_insn ( gen_adddi3 ( result , op , ls ) ) ; return result ; } else gcc_unreachable ( ) ; } </s>

Convert from one address space to another .


"instruction use requires an option to be enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> const OR1KRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void AMDGPUTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { Known . resetAll ( ) ; KnownBits Known2 ; unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { default : break ; case AMDGPUISD :: CARRY : case AMDGPUISD :: BORROW : { Known . Zero = APInt :: getHighBitsSet ( 32 , 31 ) ; break ; } case AMDGPUISD :: BFE_I32 : case AMDGPUISD :: BFE_U32 : { ConstantSDNode * CWidth = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ; if ( ! CWidth ) return ; uint32_t Width = CWidth -> getZExtValue ( ) & 0x1f ; if ( Opc == AMDGPUISD :: BFE_U32 ) Known . Zero = APInt :: getHighBitsSet ( 32 , 32 - Width ) ; break ; } case AMDGPUISD :: FP_TO_FP16 : case AMDGPUISD :: FP16_ZEXT : { unsigned BitWidth = Known . getBitWidth ( ) ; Known . Zero = APInt :: getHighBitsSet ( BitWidth , BitWidth - 16 ) ; break ; } } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> static rtx sh_legitimize_address ( rtx x , rtx oldx , machine_mode mode ) { if ( flag_pic ) x = legitimize_pic_address ( oldx , mode , NULL_RTX ) ; if ( ( TARGET_FPU_DOUBLE && mode == DFmode ) || ( TARGET_SH2E && mode == SFmode ) ) return x ; if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , 1 ) ) && BASE_REGISTER_RTX_P ( XEXP ( x , 0 ) ) ) { struct disp_adjust adj = sh_find_mov_disp_adjust ( mode , INTVAL ( XEXP ( x , 1 ) ) ) ; if ( adj . offset_adjust != NULL_RTX && adj . mov_disp != NULL_RTX ) { rtx sum = expand_binop ( Pmode , add_optab , XEXP ( x , 0 ) , adj . offset_adjust , NULL_RTX , 0 , OPTAB_LIB_WIDEN ) ; return gen_rtx_PLUS ( Pmode , sum , adj . mov_disp ) ; } } return x ; } </s>

Try to modify an illegitimate address and make it legitimate . If we find one , return the new , valid address . Otherwise , return the original address .


<s> static inline void aarch64_add_sp ( int scratchreg , HOST_WIDE_INT delta , bool emit_move_imm ) { aarch64_add_constant_internal ( Pmode , SP_REGNUM , scratchreg , delta , true , emit_move_imm ) ; } </s>

Add DELTA to the stack pointer , marking the instructions frame-related . TEMP1 is available as a temporary if nonnull . EMIT_MOVE_IMM is false if TEMP1 already contains abs ( DELTA ) .


Returns the description of caches on AIX .


<s> virtual const InstrItineraryData * getInstrItineraryData ( ) const { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> rtx extract_movd44_odd_reg ( rtx_insn * insn ) { gcc_assert ( movd44_insn_p ( insn ) ) ; rtx def_reg = SET_DEST ( PATTERN ( insn ) ) ; machine_mode mode ; gcc_assert ( REG_P ( def_reg ) || GET_CODE ( def_reg ) == SUBREG ) ; switch ( GET_MODE ( def_reg ) ) { case E_DImode : mode = SImode ; break ; case E_DFmode : mode = SFmode ; break ; default : gcc_unreachable ( ) ; } return gen_highpart ( mode , def_reg ) ; } </s>

Extract the second result ( odd reg ) of a movd44 insn .


<s> bool NVPTXAsmPrinter :: doFinalization ( Module & M ) { bool HasDebugInfo = MMI && MMI -> hasDebugInfo ( ) ; if ( ! GlobalsEmitted ) { emitGlobals ( M ) ; GlobalsEmitted = true ; } Module :: GlobalListType & global_list = M . getGlobalList ( ) ; int i , n = global_list . size ( ) ; GlobalVariable * * gv_array = new GlobalVariable * [ n ] ; i = 0 ; for ( Module :: global_iterator I = global_list . begin ( ) , E = global_list . end ( ) ; I != E ; ++ I ) gv_array [ i ++ ] = & * I ; while ( ! global_list . empty ( ) ) global_list . remove ( global_list . begin ( ) ) ; bool ret = AsmPrinter :: doFinalization ( M ) ; for ( i = 0 ; i < n ; i ++ ) global_list . insert ( global_list . end ( ) , gv_array [ i ] ) ; clearAnnotationCache ( & M ) ; delete [ ] gv_array ; if ( HasDebugInfo ) OutStreamer -> EmitRawText ( "//\t}" ) ; return ret ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> MVT X86TargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT == MVT :: v32i1 && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return MVT :: v32i8 ; return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
Sparc
::
NumTargetFixupKinds
]
=
{
{
"fixup_sparc_call30"
,
2
,
30
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_br22"
,
10
,
22
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_br19"
,
13
,
19
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_br16_2"
,
10
,
2
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_br16_14"
,
18
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_hi22"
,
10
,
22
,
0
}
,
{
"fixup_sparc_lo10"
,
22
,
10
,
0
}
,
{
"fixup_sparc_h44"
,
10
,
22
,
0
}
,
{
"fixup_sparc_m44"
,
22
,
10
,
0
}
,
{
"fixup_sparc_l44"
,
20
,
12
,
0
}
,
{
"fixup_sparc_hh"
,
10
,
22
,
0
}
,
{
"fixup_sparc_hm"
,
22
,
10
,
0
}
,
{
"fixup_sparc_pc22"
,
10
,
22
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_pc10"
,
22
,
10
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_got22"
,
10
,
22
,
0
}
,
{
"fixup_sparc_got10"
,
22
,
10
,
0
}
,
{
"fixup_sparc_wplt30"
,
2
,
30
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_tls_gd_hi22"
,
10
,
22
,
0
}
,
{
"fixup_sparc_tls_gd_lo10"
,
22
,
10
,
0
}
,
{
"fixup_sparc_tls_gd_add"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_gd_call"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_ldm_hi22"
,
10
,
22
,
0
}
,
{
"fixup_sparc_tls_ldm_lo10"
,
22
,
10
,
0
}
,
{
"fixup_sparc_tls_ldm_add"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_ldm_call"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_ldo_hix22"
,
10
,
22
,
0
}
,
{
"fixup_sparc_tls_ldo_lox10"
,
22
,
10
,
0
}
,
{
"fixup_sparc_tls_ldo_add"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_ie_hi22"
,
10
,
22
,
0
}
,
{
"fixup_sparc_tls_ie_lo10"
,
22
,
10
,
0
}
,
{
"fixup_sparc_tls_ie_ld"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_ie_ldx"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_ie_add"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_le_hix22"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_le_lox10"
,
0
,
0
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> static int arm_issue_rate ( void ) { switch ( arm_tune ) { case xgene1 : return 4 ; case cortexa15 : case cortexa57 : case exynosm1 : return 3 ; case cortexm7 : case cortexr4 : case cortexr4f : case cortexr5 : case genericv7a : case cortexa5 : case cortexa7 : case cortexa8 : case cortexa9 : case cortexa12 : case cortexa17 : case cortexa53 : case fa726te : case marvell_pj4 : return 2 ; default : return 1 ; } } </s>

Most ARM cores are single issue , but some newer ones can dual issue . The scheduler descriptions rely on this being correct .


<s> unsigned SparcInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . getOpcode ( ) == SP :: STri || MI . getOpcode ( ) == SP :: STXri || MI . getOpcode ( ) == SP :: STFri || MI . getOpcode ( ) == SP :: STDFri || MI . getOpcode ( ) == SP :: STQFri ) { if ( MI . getOperand ( 0 ) . isFI ( ) && MI . getOperand ( 1 ) . isImm ( ) && MI . getOperand ( 1 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 0 ) . getIndex ( ) ; return MI . getOperand ( 2 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
ARM
::
NumTargetFixupKinds
]
=
{
{
"fixup_arm_ldst_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_ldst_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_pcrel_10"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_pcrel_10"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_thumb_adr_pcrel_10"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_adr_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_adr_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_condbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_uncondbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_condbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_uncondbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_br"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_bl"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_blx"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cb"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cp"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_bcc"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> unsigned R600MCCodeEmitter :: getHWRegChan ( unsigned reg ) const { return MRI . getEncodingValue ( reg ) >> HW_CHAN_SHIFT ; } </s>

get the HW encoding for a register 's channel .


<s> static void gcn_goacc_reduction_init ( gcall * call ) { gimple_stmt_iterator gsi = gsi_for_stmt ( call ) ; tree lhs = gimple_call_lhs ( call ) ; tree var = gimple_call_arg ( call , 2 ) ; int level = TREE_INT_CST_LOW ( gimple_call_arg ( call , 3 ) ) ; enum tree_code rcode = ( enum tree_code ) TREE_INT_CST_LOW ( gimple_call_arg ( call , 4 ) ) ; tree init = omp_reduction_init_op ( gimple_location ( call ) , rcode , TREE_TYPE ( var ) ) ; gimple_seq seq = NULL ; push_gimplify_context ( true ) ; if ( level == GOMP_DIM_GANG ) { tree ref_to_res = gimple_call_arg ( call , 1 ) ; if ( integer_zerop ( ref_to_res ) ) init = var ; } if ( lhs ) gimplify_assign ( lhs , init , & seq ) ; pop_gimplify_context ( NULL ) ; gsi_replace_with_seq ( & gsi , seq , true ) ; } </s>


<s>
bool
ARMBaseInstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
TBB
=
nullptr
;
FBB
=
nullptr
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
if
(
I
==
MBB
.
begin
(
)
)
return
false
;
I
;
while
(
isPredicated
(
*
I
)
||
I
->
isTerminator
(
)
||
I
->
isDebugValue
(
)
)
{
bool
CantAnalyze
=
false
;
while
(
I
->
isDebugInstr
(
)
||
!
I
->
isTerminator
(
)
)
{
if
(
I
==
MBB
.
begin
(
)
)
return
false
;
I
;
}
if
(
isIndirectBranchOpcode
(
I
->
getOpcode
(
)
)
||
isJumpTableBranchOpcode
(
I
->
getOpcode
(
)
)
)
{
CantAnalyze
=
true
;
}
else
if
(
isUncondBranchOpcode
(
I
->
getOpcode
(
)
)
)
{
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
}
else
if
(
isCondBranchOpcode
(
I
->
getOpcode
(
)
)
)
{
if
(
!
Cond
.
empty
(
)
)
return
true
;
assert
(
!
FBB
&&
"FBB should have been null."
)
;
FBB
=
TBB
;
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
Cond
.
push_back
(
I
->
getOperand
(
1
)
)
;
Cond
.
push_back
(
I
->
getOperand
(
2
)
)
;
}
else
if
(
I
->
isReturn
(
)
)
{
CantAnalyze
=
!
isPredicated
(
*
I
)
;
}
else
{
return
true
;
}
if
(
!
isPredicated
(
*
I
)
&&
(
isUncondBranchOpcode
(
I
->
getOpcode
(
)
)
||
isIndirectBranchOpcode
(
I
->
getOpcode
(
)
)
||
isJumpTableBranchOpcode
(
I
->
getOpcode
(
)
)
||
I
->
isReturn
(
)
)
)
{
Cond
.
clear
(
)
;
FBB
=
nullptr
;
if
(
AllowModify
)
{
MachineBasicBlock
::
iterator
DI
=
std
::
next
(
I
)
;
while
(
DI
!=
MBB
.
end
(
)
)
{
MachineInstr
&
InstToDelete
=
*
DI
;
++
DI
;
InstToDelete
.
eraseFromParent
(
)
;
}
}
}
if
(
CantAnalyze
)
return
true
;
if
(
I
==
MBB
.
begin
(
)
)
return
false
;
I
;
}
return
false
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> static rtx riscv_split_integer ( HOST_WIDE_INT val , machine_mode mode ) { unsigned HOST_WIDE_INT loval = sext_hwi ( val , 32 ) ; unsigned HOST_WIDE_INT hival = sext_hwi ( ( val - loval ) >> 32 , 32 ) ; rtx hi = gen_reg_rtx ( mode ) , lo = gen_reg_rtx ( mode ) ; riscv_move_integer ( hi , hi , hival ) ; riscv_move_integer ( lo , lo , loval ) ; hi = gen_rtx_fmt_ee ( ASHIFT , mode , hi , GEN_INT ( 32 ) ) ; hi = force_reg ( mode , hi ) ; return gen_rtx_fmt_ee ( PLUS , mode , hi , lo ) ; } </s>

Try to split a 64b integer into 32b parts , then reassemble .


<s> bool WDC65816PassConfig :: addPreEmitPass ( ) { return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool M68kAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { MMFI = MF . getInfo < M68kMachineFunctionInfo > ( ) ; MCInstLowering = std :: make_unique < M68kMCInstLower > ( MF , * this ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> static int loongarch_fp_mult_cost ( machine_mode mode ) { return mode == DFmode ? loongarch_cost -> fp_mult_df : loongarch_cost -> fp_mult_sf ; } </s>

Return the cost of floating-point multiplications of mode MODE .


<s> static const char * get_trap_mode_suffix ( void ) { enum attr_trap_suffix s = get_attr_trap_suffix ( current_output_insn ) ; switch ( s ) { case TRAP_SUFFIX_NONE : return NULL ; case TRAP_SUFFIX_SU : if ( alpha_fptm >= ALPHA_FPTM_SU ) return "su" ; return NULL ; case TRAP_SUFFIX_SUI : if ( alpha_fptm >= ALPHA_FPTM_SUI ) return "sui" ; return NULL ; case TRAP_SUFFIX_V_SV : switch ( alpha_fptm ) { case ALPHA_FPTM_N : return NULL ; case ALPHA_FPTM_U : return "v" ; case ALPHA_FPTM_SU : case ALPHA_FPTM_SUI : return "sv" ; default : gcc_unreachable ( ) ; } case TRAP_SUFFIX_V_SV_SVI : switch ( alpha_fptm ) { case ALPHA_FPTM_N : return NULL ; case ALPHA_FPTM_U : return "v" ; case ALPHA_FPTM_SU : return "sv" ; case ALPHA_FPTM_SUI : return "svi" ; default : gcc_unreachable ( ) ; } break ; case TRAP_SUFFIX_U_SU_SUI : switch ( alpha_fptm ) { case ALPHA_FPTM_N : return NULL ; case ALPHA_FPTM_U : return "u" ; case ALPHA_FPTM_SU : return "su" ; case ALPHA_FPTM_SUI : return "sui" ; default : gcc_unreachable ( ) ; } break ; default : gcc_unreachable ( ) ; } gcc_unreachable ( ) ; } </s>

Return the trap mode suffix applicable to the current instruction , or NULL .

alpha "su" "sui" "v" "sv" "v" "sv" "svi" "u" "su" "sui"


<s> static bool aarch64_evpc_sve_tbl ( struct expand_vec_perm_d * d ) { unsigned HOST_WIDE_INT nelt ; if ( ! d -> one_vector_p && ! d -> perm . length ( ) . is_constant ( & nelt ) ) return false ; if ( d -> testing_p ) return true ; machine_mode sel_mode = related_int_vector_mode ( d -> vmode ) . require ( ) ; rtx sel = vec_perm_indices_to_rtx ( sel_mode , d -> perm ) ; if ( d -> one_vector_p ) emit_unspec2 ( d -> target , UNSPEC_TBL , d -> op0 , force_reg ( sel_mode , sel ) ) ; else aarch64_expand_sve_vec_perm ( d -> target , d -> op0 , d -> op1 , sel ) ; return true ; } </s>

Try to implement D using an SVE TBL instruction .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> static bool fa726te_sched_adjust_cost ( rtx_insn * insn , int dep_type , rtx_insn * dep , int * cost ) { if ( dep_type == REG_DEP_TRUE && recog_memoized ( insn ) >= 0 && recog_memoized ( dep ) >= 0 && get_attr_conds ( dep ) == CONDS_SET ) { if ( get_attr_conds ( insn ) == CONDS_USE && get_attr_type ( insn ) != TYPE_BRANCH ) { * cost = 3 ; return false ; } if ( GET_CODE ( PATTERN ( insn ) ) == COND_EXEC || get_attr_conds ( insn ) == CONDS_USE ) { * cost = 0 ; return false ; } } return true ; } </s>


<s> StringRef getPassName ( ) const override { return COREV_EXPAND_HWLP_PSEUDO_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> bool X86TargetLowering :: isCtlzFast ( ) const { return Subtarget . hasFastLZCNT ( ) ; } </s>

Return true if ctlz instruction is fast .


<s>
void
Mips16FrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
const
Mips16InstrInfo
&
TII
=
*
static_cast
<
const
Mips16InstrInfo
*
>
(
STI
.
getInstrInfo
(
)
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
dl
;
uint64_t
StackSize
=
MFI
->
getStackSize
(
)
;
if
(
StackSize
==
0
&&
!
MFI
->
adjustsStack
(
)
)
return
;
MachineModuleInfo
&
MMI
=
MF
.
getMMI
(
)
;
const
MCRegisterInfo
*
MRI
=
MMI
.
getContext
(
)
.
getRegisterInfo
(
)
;
MachineLocation
DstML
,
SrcML
;
TII
.
makeFrame
(
Mips
::
SP
,
StackSize
,
MBB
,
MBBI
)
;
unsigned
CFIIndex
=
MMI
.
addFrameInst
(
MCCFIInstruction
::
createDefCfaOffset
(
nullptr
,
StackSize
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
TargetOpcode
::
CFI_INSTRUCTION
)
)
.
addCFIIndex
(
CFIIndex
)
;
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
->
getCalleeSavedInfo
(
)
;
if
(
CSI
.
size
(
)
)
{
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
->
getCalleeSavedInfo
(
)
;
for
(
std
::
vector
<
CalleeSavedInfo
>
::
const_iterator
I
=
CSI
.
begin
(
)
,
E
=
CSI
.
end
(
)
;
I
!=
E
;
++
I
)
{
int64_t
Offset
=
MFI
->
getObjectOffset
(
I
->
getFrameIdx
(
)
)
;
unsigned
Reg
=
I
->
getReg
(
)
;
unsigned
DReg
=
MRI
->
getDwarfRegNum
(
Reg
,
true
)
;
unsigned
CFIIndex
=
MMI
.
addFrameInst
(
MCCFIInstruction
::
createOffset
(
nullptr
,
DReg
,
Offset
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
TargetOpcode
::
CFI_INSTRUCTION
)
)
.
addCFIIndex
(
CFIIndex
)
;
}
}
if
(
hasFP
(
MF
)
)
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Mips
::
MoveR3216
)
,
Mips
::
S0
)
.
addReg
(
Mips
::
SP
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Mips
Mips
"Shrink-wrapping not yet supported"
Mips
Mips
0
Mips::SP
Mips::MoveR3216
Mips::S0
Mips::SP


<s> static machine_mode counter_mode ( rtx count_exp ) { if ( GET_MODE ( count_exp ) != VOIDmode ) return GET_MODE ( count_exp ) ; if ( ! CONST_INT_P ( count_exp ) ) return Pmode ; if ( TARGET_64BIT && ( INTVAL ( count_exp ) & ~ 0xffffffff ) ) return DImode ; return SImode ; } </s>

Return mode for the memcpy/memset loop counter . Prefer SImode over DImode for constant loop counts .


<s> bool ix86_hardreg_mov_ok ( rtx dst , rtx src ) { if ( REG_P ( dst ) && HARD_REGISTER_P ( dst ) && ! REG_P ( src ) && ! MEM_P ( src ) && ! ( VECTOR_MODE_P ( GET_MODE ( dst ) ) ? standard_sse_constant_p ( src , GET_MODE ( dst ) ) : x86_64_immediate_operand ( src , GET_MODE ( dst ) ) ) && ix86_class_likely_spilled_p ( REGNO_REG_CLASS ( REGNO ( dst ) ) ) && ! reload_completed ) return false ; return true ; } </s>

Return true if a set of DST by the expression SRC should be allowed . This prevents complex sets of likely_spilled hard regs before reload .


<s> bool AMDGPUAnnotateKernelFeatures :: runOnModule ( Module & M ) { Triple TT ( M . getTargetTriple ( ) ) ; static const StringRef IntrinsicToAttr [ ] [ 2 ] = { { "llvm.amdgcn.workitem.id.y" , "amdgpu-work-item-id-y" } , { "llvm.amdgcn.workitem.id.z" , "amdgpu-work-item-id-z" } , { "llvm.amdgcn.workgroup.id.y" , "amdgpu-work-group-id-y" } , { "llvm.amdgcn.workgroup.id.z" , "amdgpu-work-group-id-z" } , { "llvm.r600.read.tgid.y" , "amdgpu-work-group-id-y" } , { "llvm.r600.read.tgid.z" , "amdgpu-work-group-id-z" } , { "llvm.r600.read.tidig.y" , "amdgpu-work-item-id-y" } , { "llvm.r600.read.tidig.z" , "amdgpu-work-item-id-z" } } ; static const StringRef HSAIntrinsicToAttr [ ] [ 2 ] = { { "llvm.amdgcn.dispatch.ptr" , "amdgpu-dispatch-ptr" } } ; bool Changed = addAttrsForIntrinsics ( M , IntrinsicToAttr ) ; if ( TT . getOS ( ) == Triple :: AMDHSA ) Changed |= addAttrsForIntrinsics ( M , HSAIntrinsicToAttr ) ; return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> bool LinearizedRegion :: isLiveOut ( unsigned Reg ) { return LiveOuts . contains ( Reg ) ; } </s>

isLiveOut - Determine if Reg is live out from MBB , when not considering PHI nodes .