<s> static void avr_conditional_register_usage ( void ) { if ( AVR_TINY ) { const int tiny_reg_alloc_order [ ] = { 24 , 25 , 22 , 23 , 30 , 31 , 26 , 27 , 28 , 29 , 21 , 20 , 19 , 18 , 16 , 17 , 32 , 33 , 34 , 35 , 15 , 14 , 13 , 12 , 11 , 10 , 9 , 8 , 7 , 6 , 5 , 4 , 3 , 2 , 1 , 0 } ; for ( size_t i = 0 ; i <= 17 ; i ++ ) { fixed_regs [ i ] = 1 ; call_used_regs [ i ] = 1 ; } for ( size_t i = 18 ; i <= LAST_CALLEE_SAVED_REG ; i ++ ) { call_used_regs [ i ] = 0 ; } for ( size_t i = 0 ; i < ARRAY_SIZE ( tiny_reg_alloc_order ) ; i ++ ) { reg_alloc_order [ i ] = tiny_reg_alloc_order [ i ] ; } CLEAR_HARD_REG_SET ( reg_class_contents [ ( int ) ADDW_REGS ] ) ; CLEAR_HARD_REG_SET ( reg_class_contents [ ( int ) NO_LD_REGS ] ) ; } } </s>

Implement ` TARGET_CONDITIONAL_REGISTER_USAGE ' .


<s> static tree ix86_builtin_tm_store ( tree type ) { if ( TREE_CODE ( type ) == VECTOR_TYPE ) { switch ( tree_to_uhwi ( TYPE_SIZE ( type ) ) ) { case 64 : return builtin_decl_explicit ( BUILT_IN_TM_STORE_M64 ) ; case 128 : return builtin_decl_explicit ( BUILT_IN_TM_STORE_M128 ) ; case 256 : return builtin_decl_explicit ( BUILT_IN_TM_STORE_M256 ) ; } } return NULL_TREE ; } </s>

Return the builtin decl needed to store a vector of TYPE .


"The function works only with LEA instructions"


<s> static enum flt_eval_method ix86_get_excess_precision ( enum excess_precision_type type ) { switch ( type ) { case EXCESS_PRECISION_TYPE_FAST : return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ; case EXCESS_PRECISION_TYPE_STANDARD : case EXCESS_PRECISION_TYPE_IMPLICIT : if ( ! TARGET_80387 ) return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ; else if ( ! TARGET_MIX_SSE_I387 ) { if ( ! ( TARGET_SSE && TARGET_SSE_MATH ) ) return FLT_EVAL_METHOD_PROMOTE_TO_LONG_DOUBLE ; else if ( TARGET_SSE2 ) return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ; } return ( type == EXCESS_PRECISION_TYPE_STANDARD ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT : FLT_EVAL_METHOD_UNPREDICTABLE ) ; default : gcc_unreachable ( ) ; } return FLT_EVAL_METHOD_UNPREDICTABLE ; } </s>

Set the value of FLT_EVAL_METHOD in float.h . When using only the FPU , assume that the fpcw is set to extended precision ; when using only SSE , rounding is correct ; when using both SSE and the FPU , the rounding precision is indeterminate , since either may be chosen apparently at random .


<s> bool SystemZAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == ".insn" ) return ParseDirectiveInsn ( DirectiveID . getLoc ( ) ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s>
void
print
(
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"  iteration "
<<
IterCnt
<<
'\n'
;
)
;
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> static void loongarch_emit_int_compare ( enum rtx_code * code , rtx * op0 , rtx * op1 ) { static const enum rtx_code mag_comparisons [ ] [ 2 ] = { { LEU , LTU } , { GTU , GEU } , { LE , LT } , { GT , GE } } ; if ( splittable_const_int_operand ( * op1 , VOIDmode ) ) { HOST_WIDE_INT rhs = INTVAL ( * op1 ) ; if ( * code == EQ || * code == NE ) { if ( IMM12_OPERAND ( - rhs ) ) { * op0 = loongarch_force_binary ( GET_MODE ( * op0 ) , PLUS , * op0 , GEN_INT ( - rhs ) ) ; * op1 = const0_rtx ; } } else { for ( size_t i = 0 ; i < ARRAY_SIZE ( mag_comparisons ) ; i ++ ) { HOST_WIDE_INT new_rhs ; bool increment = * code == mag_comparisons [ i ] [ 0 ] ; bool decrement = * code == mag_comparisons [ i ] [ 1 ] ; if ( ! increment && ! decrement ) continue ; if ( ( increment && rhs == HOST_WIDE_INT_MAX ) || ( decrement && rhs == HOST_WIDE_INT_MIN ) ) break ; new_rhs = rhs + ( increment ? 1 : - 1 ) ; if ( loongarch_integer_cost ( new_rhs ) < loongarch_integer_cost ( rhs ) ) { * op1 = GEN_INT ( new_rhs ) ; * code = mag_comparisons [ i ] [ increment ] ; } break ; } } } loongarch_extend_comparands ( * code , op0 , op1 ) ; * op0 = force_reg ( word_mode , * op0 ) ; if ( * op1 != const0_rtx ) * op1 = force_reg ( word_mode , * op1 ) ; } </s>

Convert a comparison into something that can be used in a branch . On entry , * OP0 and * OP1 are the values being compared and * CODE is the code used to compare them . Update them to describe the final comparison .


<s> bool TPCMCInstrInfo :: isPredicated ( MCInstrInfo const & MCII , MCInst const & MCI ) { return TPCII :: getIsPredicated ( getDesc ( MCII , MCI ) ) ; } </s>

Returns true if the instruction is already predicated .


<s> void Z80oldFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MI = MBB . begin ( ) ; DebugLoc DL ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; int StackSize = - int ( MFI . getStackSize ( ) ) ; unsigned ScratchReg = Z80old :: HL ; while ( MI != MBB . end ( ) && MI -> getFlag ( MachineInstr :: FrameSetup ) ) { ++ MI ; } int FPOffset = - 1 ; if ( hasFP ( MF ) ) { if ( MF . getFunction ( ) . getAttributes ( ) . hasAttribute ( AttributeList :: FunctionIndex , Attribute :: OptimizeForSize ) ) { if ( StackSize ) { BuildMI ( MBB , MI , DL , TII . get ( Z80old :: LD16ri ) , ScratchReg ) . addImm ( StackSize ) ; BuildMI ( MBB , MI , DL , TII . get ( Z80old :: CALL16i ) ) . addExternalSymbol ( "_frameset" ) . addReg ( ScratchReg , RegState :: ImplicitKill ) ; return ; } BuildMI ( MBB , MI , DL , TII . get ( Z80old :: CALL16i ) ) . addExternalSymbol ( "_frameset0" ) ; return ; } unsigned FrameReg = TRI -> getFrameRegister ( MF ) ; BuildMI ( MBB , MI , DL , TII . get ( Z80old :: PUSH16r ) ) . addReg ( FrameReg ) ; BuildMI ( MBB , MI , DL , TII . get ( Z80old :: LD16ri ) , FrameReg ) . addImm ( 0 ) ; BuildMI ( MBB , MI , DL , TII . get ( Z80old :: ADD16SP ) , FrameReg ) . addReg ( FrameReg ) ; FPOffset = 0 ; } BuildStackAdjustment ( MF , MBB , MI , DL , ScratchReg , StackSize , FPOffset ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static rtx save_gprs ( rtx base , int offset , int first , int last ) { rtx addr , insn , note ; int i ; addr = plus_constant ( base , offset ) ; addr = gen_rtx_MEM ( Pmode , addr ) ; set_mem_alias_set ( addr , get_frame_alias_set ( ) ) ; if ( first == last ) { if ( TARGET_64BIT ) insn = gen_movdi ( addr , gen_rtx_REG ( Pmode , first ) ) ; else insn = gen_movsi ( addr , gen_rtx_REG ( Pmode , first ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; return insn ; } insn = gen_store_multiple ( addr , gen_rtx_REG ( Pmode , first ) , GEN_INT ( last - first + 1 ) ) ; if ( first <= 6 && current_function_stdarg ) for ( i = 0 ; i < XVECLEN ( PATTERN ( insn ) , 0 ) ; i ++ ) { rtx mem = XEXP ( XVECEXP ( PATTERN ( insn ) , 0 , i ) , 0 ) ; if ( first + i <= 6 ) set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; } if ( first >= 6 ) { rtx pat = PATTERN ( insn ) ; for ( i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) if ( GET_CODE ( XVECEXP ( pat , 0 , i ) ) == SET ) RTX_FRAME_RELATED_P ( XVECEXP ( pat , 0 , i ) ) = 1 ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } else if ( last >= 6 ) { addr = plus_constant ( base , offset + ( 6 - first ) * UNITS_PER_WORD ) ; note = gen_store_multiple ( gen_rtx_MEM ( Pmode , addr ) , gen_rtx_REG ( Pmode , 6 ) , GEN_INT ( last - 6 + 1 ) ) ; note = PATTERN ( note ) ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , note , REG_NOTES ( insn ) ) ; for ( i = 0 ; i < XVECLEN ( note , 0 ) ; i ++ ) if ( GET_CODE ( XVECEXP ( note , 0 , i ) ) == SET ) RTX_FRAME_RELATED_P ( XVECEXP ( note , 0 , i ) ) = 1 ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } return insn ; } </s>

Generate insn to save registers FIRST to LAST into the register save area located at offset OFFSET relative to register BASE .


<s> bool AMDGPUInstrInfo :: SubsumesPredicate ( const SmallVectorImpl < MachineOperand > & Pred1 , const SmallVectorImpl < MachineOperand > & Pred2 ) const { return false ; } </s>

Returns true if the first specified predicate subsumes the second , e.g .


<s> static int cr16_memory_move_cost ( machine_mode mode , reg_class_t rclass ATTRIBUTE_UNUSED , bool in ATTRIBUTE_UNUSED ) { if ( reg_classes_intersect_p ( rclass , GENERAL_REGS ) ) return ( 4 * HARD_REGNO_NREGS ( 0 , mode ) ) ; else return ( 100 ) ; } </s>

Return the cost of moving data of mode MODE between a register of class CLASS and memory ; IN is zero if the value is to be written to memory , nonzero if it is to be read in . This cost is relative to those in REGISTER_MOVE_COST .


<s> static void vector_init_bshuffle ( rtx target , rtx elt , machine_mode mode , machine_mode inner_mode ) { rtx t1 , final_insn , sel ; int bmask ; t1 = gen_reg_rtx ( mode ) ; elt = convert_modes ( SImode , inner_mode , elt , true ) ; emit_move_insn ( gen_lowpart ( SImode , t1 ) , elt ) ; switch ( mode ) { case V2SImode : final_insn = gen_bshufflev2si_vis ( target , t1 , t1 ) ; bmask = 0x45674567 ; break ; case V4HImode : final_insn = gen_bshufflev4hi_vis ( target , t1 , t1 ) ; bmask = 0x67676767 ; break ; case V8QImode : final_insn = gen_bshufflev8qi_vis ( target , t1 , t1 ) ; bmask = 0x77777777 ; break ; default : gcc_unreachable ( ) ; } sel = force_reg ( SImode , GEN_INT ( bmask ) ) ; emit_insn ( gen_bmasksi_vis ( gen_rtx_REG ( SImode , 0 ) , sel , const0_rtx ) ) ; emit_insn ( final_insn ) ; } </s>

Subroutine of sparc_expand_vector_init . Emit code to initialize all fields of TARGET to ELT by means of VIS2 BSHUFFLE insn . MODE and INNER_MODE are the modes describing TARGET .


<s> bool HexagonTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Alignment , MachineMemOperand :: Flags Flags , bool * Fast ) const { MVT SVT = VT . getSimpleVT ( ) ; if ( Subtarget . isHVXVectorType ( SVT , true ) ) return allowsHvxMisalignedMemoryAccesses ( SVT , Flags , Fast ) ; if ( Fast ) * Fast = false ; return false ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"MIPS Os16 Optimization"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"Cannot store this register to stack slot!"

Load the specified register of the given register class from the specified stack frame index .


<s> static rtx emit_frame_insn ( rtx x ) { x = emit_insn ( x ) ; RTX_FRAME_RELATED_P ( x ) = 1 ; return x ; } </s>

Wrapper around emit_insn that sets RTX_FRAME_RELATED_P on the insn .


<s> StringRef getPassName ( ) const override { return AARCH64_EXPAND_PSEUDO_NAME ; } </s>


<s> bool MipsSEInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock & MBB = * MI -> getParent ( ) ; switch ( MI -> getDesc ( ) . getOpcode ( ) ) { default : return false ; case Mips :: RetRA : expandRetRA ( MBB , MI , Mips :: RET ) ; break ; case Mips :: PseudoMFHI : expandPseudoMFHiLo ( MBB , MI , Mips :: MFHI ) ; break ; case Mips :: PseudoMFLO : expandPseudoMFHiLo ( MBB , MI , Mips :: MFLO ) ; break ; case Mips :: PseudoMFHI64 : expandPseudoMFHiLo ( MBB , MI , Mips :: MFHI64 ) ; break ; case Mips :: PseudoMFLO64 : expandPseudoMFHiLo ( MBB , MI , Mips :: MFLO64 ) ; break ; case Mips :: PseudoMTLOHI : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO , Mips :: MTHI , false ) ; break ; case Mips :: PseudoMTLOHI64 : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO64 , Mips :: MTHI64 , false ) ; break ; case Mips :: PseudoMTLOHI_DSP : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO_DSP , Mips :: MTHI_DSP , true ) ; break ; case Mips :: PseudoCVT_S_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_D32_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_D32_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_S_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_L , Mips :: DMTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_W , Mips :: MTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_L , Mips :: DMTC1 , true ) ; break ; case Mips :: BuildPairF64 : expandBuildPairF64 ( MBB , MI , false ) ; break ; case Mips :: BuildPairF64_64 : expandBuildPairF64 ( MBB , MI , true ) ; break ; case Mips :: ExtractElementF64 : expandExtractElementF64 ( MBB , MI , false ) ; break ; case Mips :: ExtractElementF64_64 : expandExtractElementF64 ( MBB , MI , true ) ; break ; case Mips :: MIPSeh_return32 : case Mips :: MIPSeh_return64 : expandEhReturn ( MBB , MI ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> static int mt_function_arg_slotno ( const CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int named ATTRIBUTE_UNUSED , int incoming_p ATTRIBUTE_UNUSED , int * pregno ) { int regbase = FIRST_ARG_REGNUM ; int slotno = * cum ; if ( mode == VOIDmode || targetm . calls . must_pass_in_stack ( mode , type ) ) return - 1 ; if ( slotno >= MT_NUM_ARG_REGS ) return - 1 ; * pregno = regbase + slotno ; return slotno ; } </s>

Compute the slot number to pass an argument in . Returns the slot number or -1 if passing on the stack . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . INCOMING_P is zero for FUNCTION_ARG , nonzero for FUNCTION_INCOMING_ARG . * PREGNO records the register number to use if scalar type .


<s> rtx ix86_memtag_untagged_pointer ( rtx tagged_pointer , rtx target ) { rtx tag_mask = gen_int_mode ( ( ( HOST_WIDE_INT_1U << IX86_HWASAN_SHIFT ) + ( HOST_WIDE_INT_1U << 63 ) - 1 ) , Pmode ) ; rtx untagged_base = expand_simple_binop ( Pmode , AND , tagged_pointer , tag_mask , target , true , OPTAB_DIRECT ) ; gcc_assert ( untagged_base ) ; return untagged_base ; } </s>

The default implementation of TARGET_MEMTAG_UNTAGGED_POINTER .


<s>
unsigned
AArch64TargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
SelectionDAG
&
DAG
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"sp"
,
AArch64
::
SP
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
Twine
(
"Invalid register name \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;
}
</s>

Return the register ID of the name passed in .


<s>
static
avr_map_op_t
avr_map_decompose
(
unsigned
int
f
,
const
avr_map_op_t
*
g
,
bool
val_const_p
)
{
bool
val_used_p
=
avr_map_metric
(
f
,
MAP_MASK_PREIMAGE_F
)
!=
0
;
avr_map_op_t
f_ginv
=
*
g
;
unsigned
int
ginv
=
g
->
ginv
;
f_ginv
.
cost
=
1
;
for
(
int
i
=
7
;
i
>=
0
;
i
)
{
int
x
=
avr_map
(
f
,
i
)
;
if
(
x
<=
7
)
{
x
=
avr_map
(
ginv
,
x
)
;
if
(
x
>
7
)
return
f_ginv
;
}
f_ginv
.
map
=
(
f_ginv
.
map
<<
4
)
+
x
;
}
if
(
avr_map_metric
(
f_ginv
.
map
,
MAP_NONFIXED_0_7
)
==
0
)
f_ginv
.
cost
=
2
+
(
val_used_p
&&
!
val_const_p
)
;
else
{
rtx
xop
[
4
]
;
xop
[
0
]
=
all_regs_rtx
[
24
]
;
xop
[
1
]
=
gen_int_mode
(
f_ginv
.
map
,
SImode
)
;
xop
[
2
]
=
all_regs_rtx
[
25
]
;
xop
[
3
]
=
val_used_p
xop
[
0
]
:
const0_rtx
;
avr_out_insert_bits
(
xop
,
&
f_ginv
.
cost
)
;
f_ginv
.
cost
+=
val_const_p
&&
val_used_p
1
:
0
;
}
f_ginv
.
cost
+=
g
->
cost
;
if
(
avr_log
.
builtin
)
avr_edump
(
" %s%d=%d"
,
g
->
str
,
g
->
arg
,
f_ginv
.
cost
)
;
return
f_ginv
;
}
</s>

Try to decompose F as F = ( F o G^-1 ) o G as described above . The result is a struct representing F o G^-1 and G. If result.cost < 0 then such a decomposition does not exist .


<s> static void rs6000_darwin64_record_arg_recurse ( CUMULATIVE_ARGS * cum , tree type , HOST_WIDE_INT startbitpos , rtx rvec [ ] , int * k ) { tree f ; for ( f = TYPE_FIELDS ( type ) ; f ; f = TREE_CHAIN ( f ) ) if ( TREE_CODE ( f ) == FIELD_DECL ) { HOST_WIDE_INT bitpos = startbitpos ; tree ftype = TREE_TYPE ( f ) ; enum machine_mode mode = TYPE_MODE ( ftype ) ; if ( DECL_SIZE ( f ) != 0 && host_integerp ( bit_position ( f ) , 1 ) ) bitpos += int_bit_position ( f ) ; if ( TREE_CODE ( ftype ) == RECORD_TYPE ) rs6000_darwin64_record_arg_recurse ( cum , ftype , bitpos , rvec , k ) ; else if ( cum -> named && USE_FP_FOR_ARG_P ( cum , mode , ftype ) ) { switch ( mode ) { case SCmode : mode = SFmode ; break ; case DCmode : mode = DFmode ; break ; case TCmode : mode = TFmode ; break ; default : break ; } rs6000_darwin64_record_arg_flush ( cum , bitpos , rvec , k ) ; rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , cum -> fregno ++ ) , GEN_INT ( bitpos / BITS_PER_UNIT ) ) ; if ( mode == TFmode ) cum -> fregno ++ ; } else if ( cum -> named && USE_ALTIVEC_FOR_ARG_P ( cum , mode , ftype , 1 ) ) { rs6000_darwin64_record_arg_flush ( cum , bitpos , rvec , k ) ; rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , cum -> vregno ++ ) , GEN_INT ( bitpos / BITS_PER_UNIT ) ) ; } else if ( cum -> intoffset == - 1 ) cum -> intoffset = bitpos ; } } </s>


<s>
int
SystemZRegisterInfo
::
getDwarfRegNum
(
unsigned
RegNum
,
bool
isEH
)
const
{
assert
(
0
&&
"What is the dwarf register number"
)
;
return
1
;
}
</s>

Map a target register to an equivalent dwarf register number .


runOnMachineFunction - Emit the function body .


<s> void xstormy16_expand_arith ( machine_mode mode , enum rtx_code code , rtx dest , rtx src0 , rtx src1 ) { int num_words = GET_MODE_BITSIZE ( mode ) / BITS_PER_WORD ; int i ; int firstloop = 1 ; if ( code == NEG ) emit_move_insn ( src0 , const0_rtx ) ; for ( i = 0 ; i < num_words ; i ++ ) { rtx w_src0 , w_src1 , w_dest ; rtx insn ; w_src0 = simplify_gen_subreg ( word_mode , src0 , mode , i * UNITS_PER_WORD ) ; w_src1 = simplify_gen_subreg ( word_mode , src1 , mode , i * UNITS_PER_WORD ) ; w_dest = simplify_gen_subreg ( word_mode , dest , mode , i * UNITS_PER_WORD ) ; switch ( code ) { case PLUS : if ( firstloop && CONST_INT_P ( w_src1 ) && INTVAL ( w_src1 ) == 0 ) continue ; if ( firstloop ) insn = gen_addchi4 ( w_dest , w_src0 , w_src1 ) ; else insn = gen_addchi5 ( w_dest , w_src0 , w_src1 ) ; break ; case NEG : case MINUS : case COMPARE : if ( code == COMPARE && i == num_words - 1 ) { rtx branch , sub , clobber , sub_1 ; sub_1 = gen_rtx_MINUS ( HImode , w_src0 , gen_rtx_ZERO_EXTEND ( HImode , gen_rtx_REG ( BImode , CARRY_REGNUM ) ) ) ; sub = gen_rtx_SET ( VOIDmode , w_dest , gen_rtx_MINUS ( HImode , sub_1 , w_src1 ) ) ; clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( BImode , CARRY_REGNUM ) ) ; branch = gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_EQ ( HImode , sub_1 , w_src1 ) , pc_rtx , pc_rtx ) ) ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 3 , branch , sub , clobber ) ) ; } else if ( firstloop && code != COMPARE && CONST_INT_P ( w_src1 ) && INTVAL ( w_src1 ) == 0 ) continue ; else if ( firstloop ) insn = gen_subchi4 ( w_dest , w_src0 , w_src1 ) ; else insn = gen_subchi5 ( w_dest , w_src0 , w_src1 ) ; break ; case IOR : case XOR : case AND : if ( CONST_INT_P ( w_src1 ) && INTVAL ( w_src1 ) == - ( code == AND ) ) continue ; insn = gen_rtx_SET ( VOIDmode , w_dest , gen_rtx_fmt_ee ( code , mode , w_src0 , w_src1 ) ) ; break ; case NOT : insn = gen_rtx_SET ( VOIDmode , w_dest , gen_rtx_NOT ( mode , w_src0 ) ) ; break ; default : gcc_unreachable ( ) ; } firstloop = 0 ; emit ( insn ) ; } if ( firstloop ) emit ( gen_nop ( ) ) ; } </s>

Expander for arithmetic operations ; emit insns to compute ( set DEST ( CODE : MODE SRC0 SRC1 ) ) using CARRY as a temporary . When CODE is COMPARE , a branch template is generated ( this saves duplicating code in xstormy16_split_cbranch ) .


<s> bool ARMSubtarget :: enableMachineScheduler ( ) const { return getSchedModel ( ) . isOutOfOrder ( ) && isSwift ( ) ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Hexagon Branch Relaxation"
;
}
</s>


<s>
const
MCFixupKindInfo
&
WebAssemblyAsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
WebAssembly
::
NumTargetFixupKinds
]
=
{
{
"fixup_code_sleb128_i32"
,
0
,
5
*
8
,
0
}
,
{
"fixup_code_sleb128_i64"
,
0
,
10
*
8
,
0
}
,
{
"fixup_code_uleb128_i32"
,
0
,
5
*
8
,
0
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> bool ARMPreAllocLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { TD = Fn . getTarget ( ) . getTargetData ( ) ; TII = Fn . getTarget ( ) . getInstrInfo ( ) ; TRI = Fn . getTarget ( ) . getRegisterInfo ( ) ; STI = & Fn . getTarget ( ) . getSubtarget < ARMSubtarget > ( ) ; MRI = & Fn . getRegInfo ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) Modified |= RescheduleLoadStoreInstrs ( MFI ) ; return Modified ; } </s>


<s> static int ix86_mode_needed ( int entity , rtx_insn * insn ) { switch ( entity ) { case X86_DIRFLAG : return ix86_dirflag_mode_needed ( insn ) ; case AVX_U128 : return ix86_avx_u128_mode_needed ( insn ) ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : case I387_MASK_PM : return ix86_i387_mode_needed ( entity , insn ) ; default : gcc_unreachable ( ) ; } return 0 ; } </s>

Return needed mode for entity in optimize_mode_switching pass .


"passing %qT to argument %d of %qE, but"

Like require_vector_type , but TYPE is inferred from previous arguments rather than being a fixed part of the function signature . This changes the nature of the error messages .


<s> bool MBlazeAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s>
void
AArch64AsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsPCRel
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
Ctx
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
unsigned
FulleSizeInBytes
=
getFixupKindContainereSizeInBytes
(
Fixup
.
getKind
(
)
)
;
if
(
FulleSizeInBytes
==
0
)
{
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
else
{
assert
(
(
Offset
+
FulleSizeInBytes
)
<=
Data
.
size
(
)
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FulleSizeInBytes
&&
"Invalid fixup size!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
FulleSizeInBytes
1
i
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool csky_split_ior ( rtx * operands ) { HOST_WIDE_INT mask = INTVAL ( operands [ 2 ] ) ; int i ; if ( mask == 0 ) { emit_move_insn ( operands [ 0 ] , operands [ 1 ] ) ; return true ; } if ( mask == - 1 ) { emit_move_insn ( operands [ 0 ] , gen_int_mode ( - 1 , SImode ) ) ; return true ; } if ( CSKY_ISA_FEATURE ( E2 ) && csky_literal_I_operand ( operands [ 2 ] , SImode ) ) return false ; if ( popcount_hwi ( mask & 0xffffffff ) <= ( reload_completed && ! CSKY_ISA_FEATURE ( E2 ) ? 1 : 2 ) ) { rtx input = operands [ 1 ] ; if ( ! CSKY_ISA_FEATURE ( E2 ) ) { emit_move_insn ( operands [ 0 ] , input ) ; input = operands [ 0 ] ; } for ( i = 0 ; i < 32 ; i ++ ) if ( mask & ( 1 << i ) ) { emit_insn ( gen_bseti ( operands [ 0 ] , input , GEN_INT ( i ) ) ) ; input = operands [ 0 ] ; } return true ; } if ( reload_completed ) { emit_move_insn ( operands [ 0 ] , operands [ 2 ] ) ; operands [ 2 ] = operands [ 1 ] ; operands [ 1 ] = operands [ 0 ] ; } else operands [ 2 ] = copy_to_mode_reg ( SImode , operands [ 2 ] ) ; return false ; } </s>

Split operands for an IOR expression when OPERANDS [ 2 ] is a constant . Note operands [ 0 ] is marked earlyclobber in this case and can be overwritten . Return true if `` DONE '' , false otherwise .


<s> bool PPCPassConfig :: addPreISel ( ) { if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCCTRLoops ( getPPCTargetMachine ( ) ) ) ; return false ; } </s>


<s> static bool pdp11_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { return ( TYPE_MODE ( type ) == DImode || ( FLOAT_MODE_P ( TYPE_MODE ( type ) ) && ! TARGET_AC0 ) || TREE_CODE ( type ) == VECTOR_TYPE || COMPLEX_MODE_P ( TYPE_MODE ( type ) ) ) ; } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


<s>
StringRef
getPassName
(
)
const
override
{
return
"ARC Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static bool expand_vselect ( rtx target , rtx op0 , const unsigned char * perm , unsigned nelt ) { rtx rperm [ MAX_VECT_LEN ] , x ; unsigned i ; for ( i = 0 ; i < nelt ; ++ i ) rperm [ i ] = GEN_INT ( perm [ i ] ) ; x = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( nelt , rperm ) ) ; x = gen_rtx_VEC_SELECT ( GET_MODE ( target ) , op0 , x ) ; x = gen_rtx_SET ( VOIDmode , target , x ) ; rtx_insn * insn = emit_insn ( x ) ; if ( recog_memoized ( insn ) < 0 ) { remove_insn ( insn ) ; return false ; } return true ; } </s>

Construct ( set target ( vec_select op0 ( parallel perm ) ) ) and return true if that 's a valid instruction in the active ISA .


<s> bool X86MCInstrAnalysis :: isDependencyBreaking ( const MCSubtargetInfo & STI , const MCInst & Inst ) const { if ( STI . getCPU ( ) == "btver2" ) { switch ( Inst . getOpcode ( ) ) { default : return false ; case X86 :: SUB32rr : case X86 :: SUB64rr : case X86 :: SBB32rr : case X86 :: SBB64rr : case X86 :: XOR32rr : case X86 :: XOR64rr : case X86 :: XORPSrr : case X86 :: XORPDrr : case X86 :: VXORPSrr : case X86 :: VXORPDrr : case X86 :: ANDNPSrr : case X86 :: VANDNPSrr : case X86 :: ANDNPDrr : case X86 :: VANDNPDrr : case X86 :: PXORrr : case X86 :: VPXORrr : case X86 :: PANDNrr : case X86 :: VPANDNrr : case X86 :: PSUBBrr : case X86 :: PSUBWrr : case X86 :: PSUBDrr : case X86 :: PSUBQrr : case X86 :: VPSUBBrr : case X86 :: VPSUBWrr : case X86 :: VPSUBDrr : case X86 :: VPSUBQrr : case X86 :: PCMPEQBrr : case X86 :: PCMPEQWrr : case X86 :: PCMPEQDrr : case X86 :: PCMPEQQrr : case X86 :: VPCMPEQBrr : case X86 :: VPCMPEQWrr : case X86 :: VPCMPEQDrr : case X86 :: VPCMPEQQrr : case X86 :: PCMPGTBrr : case X86 :: PCMPGTWrr : case X86 :: PCMPGTDrr : case X86 :: PCMPGTQrr : case X86 :: VPCMPGTBrr : case X86 :: VPCMPGTWrr : case X86 :: VPCMPGTDrr : case X86 :: VPCMPGTQrr : case X86 :: MMX_PXORirr : case X86 :: MMX_PANDNirr : case X86 :: MMX_PSUBBirr : case X86 :: MMX_PSUBDirr : case X86 :: MMX_PSUBQirr : case X86 :: MMX_PSUBWirr : case X86 :: MMX_PCMPGTBirr : case X86 :: MMX_PCMPGTDirr : case X86 :: MMX_PCMPGTWirr : case X86 :: MMX_PCMPEQBirr : case X86 :: MMX_PCMPEQDirr : case X86 :: MMX_PCMPEQWirr : return Inst . getOperand ( 1 ) . getReg ( ) == Inst . getOperand ( 2 ) . getReg ( ) ; case X86 :: CMP32rr : case X86 :: CMP64rr : return Inst . getOperand ( 0 ) . getReg ( ) == Inst . getOperand ( 1 ) . getReg ( ) ; } } return false ; } </s>

Returns true if MI is a dependency breaking instruction for the subtarget .


<s> static void sparc_asm_function_prologue ( FILE * file , HOST_WIDE_INT size ATTRIBUTE_UNUSED ) { if ( ! TARGET_FLAT ) gcc_assert ( sparc_leaf_function_p == crtl -> uses_only_leaf_regs ) ; sparc_output_scratch_registers ( file ) ; } </s>

This function generates the assembly code for function entry , which boils down to emitting the necessary .register directives .


<s> type_suffix_index function_resolver :: infer_vector_type ( unsigned int argno ) { return infer_vector_or_tuple_type ( argno , 1 ) ; } </s>

Require argument ARGNO to have some form of vector type . Return the associated type suffix on success , using TYPE_SUFFIX_b for predicates . Report an error and return NUM_TYPE_SUFFIXES on failure .


<s> bool SIInstrInfo :: shouldClusterMemOps ( MachineInstr & FirstLdSt , MachineInstr & SecondLdSt , unsigned NumLoads ) const { const MachineOperand * FirstDst = nullptr ; const MachineOperand * SecondDst = nullptr ; if ( ( isMUBUF ( FirstLdSt ) && isMUBUF ( SecondLdSt ) ) || ( isMTBUF ( FirstLdSt ) && isMTBUF ( SecondLdSt ) ) || ( isFLAT ( FirstLdSt ) && isFLAT ( SecondLdSt ) ) ) { FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: vdata ) ; SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: vdata ) ; } else if ( isSMRD ( FirstLdSt ) && isSMRD ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: sdst ) ; SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: sdst ) ; } else if ( isDS ( FirstLdSt ) && isDS ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: vdst ) ; SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: vdst ) ; } if ( ! FirstDst || ! SecondDst ) return false ; unsigned LoadClusterThreshold = 16 ; const MachineRegisterInfo & MRI = FirstLdSt . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * DstRC = MRI . getRegClass ( FirstDst -> getReg ( ) ) ; return ( NumLoads * ( RI . getRegSizeInBits ( * DstRC ) / 8 ) ) <= LoadClusterThreshold ; } </s>

Returns true if the two given memory operations should be scheduled adjacent .

AMDGPU SI AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName 16 8


<s>
void
BlackfinInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
I
!=
MBB
.
end
(
)
I
->
getDebugLoc
(
)
:
DebugLoc
::
getUnknownLoc
(
)
;
if
(
inClass
(
BF
::
DPRegClass
,
SrcReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
STORE32fi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
if
(
inClass
(
BF
::
D16RegClass
,
SrcReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
STORE16fi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
if
(
inClass
(
BF
::
AnyCCRegClass
,
SrcReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
STORE8fi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
llvm_unreachable
(
(
std
::
string
(
"Cannot store regclass to stack slot: "
)
+
RC
->
getName
(
)
)
.
c_str
(
)
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: ADDRSPACECAST : return lowerADDRSPACECAST ( Op , DAG ) ; case ISD :: BRCOND : return lowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return lowerConstantPool ( Op , DAG ) ; case ISD :: GlobalAddress : return lowerGlobalAddress ( Op , DAG ) ; case ISD :: BlockAddress : return lowerBlockAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return lowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return lowerJumpTable ( Op , DAG ) ; case ISD :: SELECT : return lowerSELECT ( Op , DAG ) ; case ISD :: SETCC : return lowerSETCC ( Op , DAG ) ; case ISD :: VASTART : return lowerVASTART ( Op , DAG ) ; case ISD :: VAARG : return lowerVAARG ( Op , DAG ) ; case ISD :: VACOPY : return lowerVACOPY ( Op , DAG ) ; case ISD :: FCOPYSIGN : return lowerFCOPYSIGN ( Op , DAG ) ; case ISD :: FABS : return lowerFABS ( Op , DAG ) ; case ISD :: FRAMEADDR : return lowerFRAMEADDR ( Op , DAG ) ; case ISD :: RETURNADDR : return lowerRETURNADDR ( Op , DAG ) ; case ISD :: EH_RETURN : return lowerEH_RETURN ( Op , DAG ) ; case ISD :: ATOMIC_FENCE : return lowerATOMIC_FENCE ( Op , DAG ) ; case ISD :: SHL_PARTS : return lowerShiftLeftParts ( Op , DAG ) ; case ISD :: SRA_PARTS : return lowerShiftRightParts ( Op , DAG , true ) ; case ISD :: SRL_PARTS : return lowerShiftRightParts ( Op , DAG , false ) ; case ISD :: LOAD : return lowerLOAD ( Op , DAG ) ; case ISD :: STORE : return lowerSTORE ( Op , DAG ) ; case ISD :: EH_DWARF_CFA : return lowerEH_DWARF_CFA ( Op , DAG ) ; case ISD :: FP_TO_SINT : return lowerFP_TO_SINT ( Op , DAG ) ; case ISD :: BR_JT : return lowerBR_JT ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::ADDRSPACECAST ISD::BRCOND ISD::ConstantPool ISD::GlobalAddress ISD::BlockAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::SELECT ISD::SETCC ISD::VASTART ISD::VAARG ISD::VACOPY ISD::FCOPYSIGN ISD::FABS ISD::FRAMEADDR ISD::RETURNADDR ISD::EH_RETURN ISD::ATOMIC_FENCE ISD::SHL_PARTS ISD::SRA_PARTS ISD::SRL_PARTS ISD::LOAD ISD::STORE ISD::EH_DWARF_CFA ISD::FP_TO_SINT ISD::BR_JT


<s> static HOST_WIDE_INT microblaze_starting_frame_offset ( void ) { return ( crtl -> outgoing_args_size + FIRST_PARM_OFFSET ( FNDECL ) ) ; } </s>


<s> bool ResourceAssignment :: Schedule ( SUnit * SU ) { if ( isPseudo ( SU ) ) return true ; return ScheduleOnSide ( SU , TMS320C64XInstrInfo :: getSide ( SU -> getInstr ( ) ) ) ; } </s>

Schedule - Order nodes according to selected style , filling in the Sequence member .


<s> bool X86TargetLowering :: isCommutativeBinOp ( unsigned Opcode ) const { switch ( Opcode ) { case X86ISD :: AVG : case X86ISD :: PCMPEQ : case X86ISD :: PMULDQ : case X86ISD :: PMULUDQ : case X86ISD :: FMAXC : case X86ISD :: FMINC : case X86ISD :: FAND : case X86ISD :: FOR : case X86ISD :: FXOR : return true ; } return TargetLoweringBase :: isCommutativeBinOp ( Opcode ) ; } </s>

Returns true if the opcode is a commutative binary operation .


Wrapper around the output_probe_stack_range routines .


<s> static void reset_origins ( int * rp , int * age ) { int i ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { rp [ i ] = i ; age [ i ] = 0 ; } } </s>

Helper function to reset the origins in RP and the age in AGE for all registers .


<s> SDValue LEGTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InGlue , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { assert ( ! isVarArg && "Unsupported" ) ; SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_LEG ) ; for ( auto & Loc : RVLocs ) { Chain = DAG . getCopyFromReg ( Chain , dl , Loc . getLocReg ( ) , Loc . getValVT ( ) , InGlue ) . getValue ( 1 ) ; InGlue = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


Output assembly language to define a symbol as COMMON from a DECL , possibly with visibility .


<s> bool ARMFrameInfo :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; unsigned CFSize = FFI -> getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( 1 << 12 ) - 1 ) / 2 ) return false ; return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> SMLoc getEndLoc ( ) const { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> bool PTXTargetMachine :: addPostRegAlloc ( PassManagerBase & PM ) { return false ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


"Odd number of callee-saved regs to spill!"

"Expected GPR64 callee-saved register pair!"

"Expected FPR64 callee-saved register pair!"

"Offset out of bounds for STP immediate"

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> void riscv_move_integer ( rtx temp , rtx dest , HOST_WIDE_INT value ) { struct riscv_integer_op codes [ RISCV_MAX_INTEGER_OPS ] ; enum machine_mode mode ; int i , num_ops ; rtx x ; mode = GET_MODE ( dest ) ; num_ops = riscv_build_integer ( codes , value , mode ) ; if ( can_create_pseudo_p ( ) && num_ops > 2 && num_ops >= riscv_split_integer_cost ( value ) ) x = riscv_split_integer ( value , mode ) ; else { x = GEN_INT ( codes [ 0 ] . value ) ; for ( i = 1 ; i < num_ops ; i ++ ) { if ( ! can_create_pseudo_p ( ) ) x = riscv_emit_set ( temp , x ) ; else x = force_reg ( mode , x ) ; x = gen_rtx_fmt_ee ( codes [ i ] . code , mode , x , GEN_INT ( codes [ i ] . value ) ) ; } } riscv_emit_set ( dest , x ) ; } </s>

Load VALUE into DEST . TEMP is as for riscv_force_temporary .


<s> void assignValueToAddress ( Register ValVReg , Register Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant , Size , 1 ) ; MIRBuilder . buildLoad ( ValVReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> static HOST_WIDE_INT sparc_compute_frame_size ( HOST_WIDE_INT size , int leaf_function ) { HOST_WIDE_INT frame_size , apparent_frame_size ; int args_size , n_global_fp_regs = 0 ; bool save_local_in_regs_p = false ; unsigned int i ; if ( leaf_function && ! cfun -> calls_alloca ) args_size = 0 ; else args_size = crtl -> outgoing_args_size + REG_PARM_STACK_SPACE ( cfun -> decl ) ; if ( TARGET_ARCH64 ) { for ( i = 0 ; i < 8 ; i ++ ) if ( save_global_or_fp_reg_p ( i , 0 ) ) n_global_fp_regs += 2 ; } else { for ( i = 0 ; i < 8 ; i += 2 ) if ( save_global_or_fp_reg_p ( i , 0 ) || save_global_or_fp_reg_p ( i + 1 , 0 ) ) n_global_fp_regs += 2 ; } if ( TARGET_FLAT ) for ( i = 16 ; i < 32 ; i ++ ) if ( save_local_or_in_reg_p ( i , leaf_function ) ) { save_local_in_regs_p = true ; break ; } for ( i = 32 ; i < ( TARGET_V9 ? 96 : 64 ) ; i += 2 ) if ( save_global_or_fp_reg_p ( i , 0 ) || save_global_or_fp_reg_p ( i + 1 , 0 ) ) n_global_fp_regs += 2 ; if ( size == 0 && n_global_fp_regs == 0 && args_size == 0 && ! save_local_in_regs_p ) frame_size = apparent_frame_size = 0 ; else { apparent_frame_size = ROUND_UP ( size , 8 ) + n_global_fp_regs * 4 ; frame_size = apparent_frame_size + ROUND_UP ( args_size , 8 ) ; frame_size += FIRST_PARM_OFFSET ( cfun -> decl ) ; frame_size = SPARC_STACK_ALIGN ( frame_size ) ; } sparc_frame_size = frame_size ; sparc_apparent_frame_size = apparent_frame_size ; sparc_n_global_fp_regs = n_global_fp_regs ; sparc_save_local_in_regs_p = save_local_in_regs_p ; return frame_size ; } </s>

Compute the frame size required by the function . This function is called during the reload pass and also by sparc_expand_prologue .


<s>
MachineBasicBlock
::
iterator
ARMBaseInstrInfo
::
insertOutlinedCall
(
Module
&
M
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
&
It
,
MachineFunction
&
MF
,
const
outliner
::
Candidate
&
C
)
const
{
MachineInstrBuilder
MIB
;
MachineBasicBlock
::
iterator
CallPt
;
unsigned
Opc
;
bool
isThumb
=
Subtarget
.
isThumb
(
)
;
if
(
C
.
CallConstructionID
==
MachineOutlinerTailCall
)
{
Opc
=
isThumb
Subtarget
.
isTargetMachO
(
)
ARM
::
tTAILJMPd
:
ARM
::
tTAILJMPdND
:
ARM
::
TAILJMPd
;
MIB
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
Opc
)
)
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
;
if
(
isThumb
)
MIB
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
It
=
MBB
.
insert
(
It
,
MIB
)
;
return
It
;
}
Opc
=
isThumb
ARM
::
tBL
:
ARM
::
BL
;
MachineInstrBuilder
CallMIB
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
Opc
)
)
;
if
(
isThumb
)
CallMIB
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
CallMIB
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
;
if
(
C
.
CallConstructionID
==
MachineOutlinerNoLRSave
||
C
.
CallConstructionID
==
MachineOutlinerThunk
)
{
It
=
MBB
.
insert
(
It
,
CallMIB
)
;
return
It
;
}
const
ARMFunctionInfo
&
AFI
=
*
C
.
getMF
(
)
->
getInfo
<
ARMFunctionInfo
>
(
)
;
if
(
C
.
CallConstructionID
==
MachineOutlinerRegSave
)
{
unsigned
Reg
=
findRegisterToSaveLRTo
(
C
)
;
assert
(
Reg
!=
0
&&
"No callee-saved register available?"
)
;
copyPhysReg
(
MBB
,
It
,
DebugLoc
(
)
,
Reg
,
ARM
::
LR
,
true
)
;
if
(
!
AFI
.
isLRSpilled
(
)
)
emitCFIForLRSaveToReg
(
MBB
,
It
,
Reg
)
;
CallPt
=
MBB
.
insert
(
It
,
CallMIB
)
;
copyPhysReg
(
MBB
,
It
,
DebugLoc
(
)
,
ARM
::
LR
,
Reg
,
true
)
;
if
(
!
AFI
.
isLRSpilled
(
)
)
emitCFIForLRRestoreFromReg
(
MBB
,
It
)
;
It
;
return
CallPt
;
}
saveLROnStack
(
MBB
,
It
)
;
if
(
!
AFI
.
isLRSpilled
(
)
)
emitCFIForLRSaveOnStack
(
MBB
,
It
)
;
CallPt
=
MBB
.
insert
(
It
,
CallMIB
)
;
restoreLRFromStack
(
MBB
,
It
)
;
if
(
!
AFI
.
isLRSpilled
(
)
)
emitCFIForLRRestoreFromStack
(
MBB
,
It
)
;
It
;
return
CallPt
;
}
</s>

Insert a call to an outlined function into the program .

ARM
ARM
ARM::tTAILJMPd
ARM::tTAILJMPdND
ARM::TAILJMPd
ARMCC::AL
ARM::tBL
ARM::BL
ARMCC::AL
ARM
ARM
0
"No callee-saved register available?"
ARM::LR
ARM::LR


<s> static unsigned selectBinaryOp ( unsigned GenericOpc , unsigned RegBankID , unsigned OpSize ) { switch ( RegBankID ) { case AArch64 :: GPRRegBankID : if ( OpSize == 32 ) { switch ( GenericOpc ) { case TargetOpcode :: G_SHL : return AArch64 :: LSLVWr ; case TargetOpcode :: G_LSHR : return AArch64 :: LSRVWr ; case TargetOpcode :: G_ASHR : return AArch64 :: ASRVWr ; default : return GenericOpc ; } } else if ( OpSize == 64 ) { switch ( GenericOpc ) { case TargetOpcode :: G_GEP : return AArch64 :: ADDXrr ; case TargetOpcode :: G_SHL : return AArch64 :: LSLVXr ; case TargetOpcode :: G_LSHR : return AArch64 :: LSRVXr ; case TargetOpcode :: G_ASHR : return AArch64 :: ASRVXr ; default : return GenericOpc ; } } case AArch64 :: FPRRegBankID : switch ( OpSize ) { case 32 : switch ( GenericOpc ) { case TargetOpcode :: G_FADD : return AArch64 :: FADDSrr ; case TargetOpcode :: G_FSUB : return AArch64 :: FSUBSrr ; case TargetOpcode :: G_FMUL : return AArch64 :: FMULSrr ; case TargetOpcode :: G_FDIV : return AArch64 :: FDIVSrr ; default : return GenericOpc ; } case 64 : switch ( GenericOpc ) { case TargetOpcode :: G_FADD : return AArch64 :: FADDDrr ; case TargetOpcode :: G_FSUB : return AArch64 :: FSUBDrr ; case TargetOpcode :: G_FMUL : return AArch64 :: FMULDrr ; case TargetOpcode :: G_FDIV : return AArch64 :: FDIVDrr ; case TargetOpcode :: G_OR : return AArch64 :: ORRv8i8 ; default : return GenericOpc ; } } } ; return GenericOpc ; } </s>

Select and emit code for a binary operator instruction , which has an opcode which directly corresponds to the given ISD opcode .


<s> static rtx m68k_wrap_symbol ( rtx x , enum m68k_reloc reloc , rtx base_reg , rtx temp_reg ) { bool use_x_p ; use_x_p = ( base_reg == pic_offset_table_rtx ) ? TARGET_XGOT : TARGET_XTLS ; if ( TARGET_COLDFIRE && use_x_p ) { x = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 2 , x , GEN_INT ( reloc ) ) , UNSPEC_RELOC32 ) ; x = gen_rtx_CONST ( Pmode , x ) ; if ( temp_reg == NULL ) { gcc_assert ( can_create_pseudo_p ( ) ) ; temp_reg = gen_reg_rtx ( Pmode ) ; } emit_move_insn ( temp_reg , x ) ; emit_insn ( gen_addsi3 ( temp_reg , temp_reg , base_reg ) ) ; x = temp_reg ; } else { x = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 2 , x , GEN_INT ( reloc ) ) , UNSPEC_RELOC16 ) ; x = gen_rtx_CONST ( Pmode , x ) ; x = gen_rtx_PLUS ( Pmode , base_reg , x ) ; } return x ; } </s>

Wrap symbol X into unspec representing relocation RELOC . BASE_REG - register that should be added to the result . TEMP_REG - if non-null , temporary register .


<s> void AlphaRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { MachineInstr * Old = I ; uint64_t Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { unsigned Align = TFI -> getStackAlignment ( ) ; Amount = ( Amount + Align - 1 ) / Align * Align ; MachineInstr * New ; if ( Old -> getOpcode ( ) == Alpha :: ADJUSTSTACKDOWN ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Alpha :: LDA ) , Alpha :: R30 ) . addImm ( - Amount ) . addReg ( Alpha :: R30 ) ; } else { assert ( Old -> getOpcode ( ) == Alpha :: ADJUSTSTACKUP ) ; New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Alpha :: LDA ) , Alpha :: R30 ) . addImm ( Amount ) . addReg ( Alpha :: R30 ) ; } MBB . insert ( I , New ) ; } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static unsigned int insn_is_store_p ( rtx insn ) { rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) == SET && MEM_P ( SET_DEST ( body ) ) ) return 1 ; if ( GET_CODE ( body ) != PARALLEL ) return 0 ; rtx set = XVECEXP ( body , 0 , 0 ) ; if ( GET_CODE ( set ) == SET && MEM_P ( SET_DEST ( set ) ) ) return 1 ; return 0 ; } </s>

Return 1 iff INSN is a store insn , including permuting stores that represent an stvxd2x instruction ; else return 0 .


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { bool HasAVX = TM . getSubtarget < X86Subtarget > ( ) . hasAVX ( ) ; if ( CC == CallingConv :: Intel_OCL_BI ) { if ( IsWin64 && HasAVX ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( Is64Bit && HasAVX ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; } if ( CC == CallingConv :: GHC ) return CSR_NoRegs_RegMask ; if ( ! Is64Bit ) return CSR_32_RegMask ; if ( IsWin64 ) return CSR_Win64_RegMask ; return CSR_64_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> SDValue MipsSETargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; SDValue Val ; switch ( N -> getOpcode ( ) ) { case ISD :: ADDE : return performADDECombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SUBE : return performSUBECombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SHL : return performSHLCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SRA : return performSRACombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SRL : return performSRLCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: VSELECT : return performVSELECTCombine ( N , DAG ) ; case ISD :: SETCC : { Val = performSETCCCombine ( N , DAG ) ; break ; } } if ( Val . getNode ( ) ) return Val ; return MipsTargetLowering :: PerformDAGCombine ( N , DCI ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips Mips ISD::ADDE ISD::SUBE ISD::SHL ISD::SRA ISD::SRL ISD::VSELECT ISD::SETCC Mips


<s>
bool
X86InstrInfo
::
classifyLEAReg
(
MachineInstr
&
MI
,
const
MachineOperand
&
Src
,
unsigned
Opc
,
bool
AllowSP
,
unsigned
&
NewSrc
,
bool
&
isKill
,
MachineOperand
&
ImplicitOp
,
LiveVariables
*
LV
)
const
{
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
const
TargetRegisterClass
*
RC
;
if
(
AllowSP
)
{
RC
=
Opc
!=
X86
::
LEA32r
&
X86
::
GR64RegClass
:
&
X86
::
GR32RegClass
;
}
else
{
RC
=
Opc
!=
X86
::
LEA32r
&
X86
::
GR64_NOSPRegClass
:
&
X86
::
GR32_NOSPRegClass
;
}
unsigned
SrcReg
=
Src
.
getReg
(
)
;
if
(
Opc
!=
X86
::
LEA64_32r
)
{
NewSrc
=
SrcReg
;
isKill
=
Src
.
isKill
(
)
;
assert
(
!
Src
.
isUndef
(
)
&&
"Undef op doesn't need optimization"
)
;
if
(
TargetRegisterInfo
::
isVirtualRegister
(
NewSrc
)
&&
!
MF
.
getRegInfo
(
)
.
constrainRegClass
(
NewSrc
,
RC
)
)
return
false
;
return
true
;
}
if
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
)
{
ImplicitOp
=
Src
;
ImplicitOp
.
setImplicit
(
)
;
NewSrc
=
getX86SubSuperRegister
(
Src
.
getReg
(
)
,
64
)
;
isKill
=
Src
.
isKill
(
)
;
assert
(
!
Src
.
isUndef
(
)
&&
"Undef op doesn't need optimization"
)
;
}
else
{
NewSrc
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
RC
)
;
MachineInstr
*
Copy
=
BuildMI
(
*
MI
.
getParent
(
)
,
MI
,
MI
.
getDebugLoc
(
)
,
get
(
TargetOpcode
::
COPY
)
)
.
addReg
(
NewSrc
,
RegState
::
Define
|
RegState
::
Undef
,
X86
::
sub_32bit
)
.
add
(
Src
)
;
isKill
=
true
;
if
(
LV
)
LV
->
replaceKillInstruction
(
SrcReg
,
MI
,
*
Copy
)
;
}
return
true
;
}
</s>

Given an operand within a MachineInstr , insert preceding code to put it into the right format for a particular kind of LEA instruction .


<s> void Thumb2RegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , unsigned PredReg ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: t2LDRpci ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( ( int64_t ) ARMCC :: AL ) . addReg ( 0 ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s> void init_cumulative_args ( CUMULATIVE_ARGS * cum , int incoming ) { cum -> arg_words = 0 ; cum -> incoming = incoming ; } </s>

Handle the INIT_CUMULATIVE_ARGS macro . Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is 0 .


<s>
void
PPCHazardRecognizer970
::
EmitInstruction
(
SUnit
*
SU
)
{
const
SDNode
*
Node
=
SU
->
getNode
(
)
->
getFlaggedMachineNode
(
)
;
bool
isFirst
,
isSingle
,
isCracked
,
isLoad
,
isStore
;
PPCII
::
PPC970_Unit
InstrType
=
GetInstrType
(
Node
->
getOpcode
(
)
,
isFirst
,
isSingle
,
isCracked
,
isLoad
,
isStore
)
;
if
(
InstrType
==
PPCII
::
PPC970_Pseudo
)
return
;
unsigned
Opcode
=
Node
->
getMachineOpcode
(
)
;
if
(
Opcode
==
PPC
::
MTCTR
)
HasCTRSet
=
true
;
if
(
isStore
)
{
unsigned
ThisStoreSize
;
switch
(
Opcode
)
{
default
:
llvm_unreachable
(
"Unknown store instruction!"
)
;
case
PPC
::
STB
:
case
PPC
::
STB8
:
case
PPC
::
STBU
:
case
PPC
::
STBU8
:
case
PPC
::
STBX
:
case
PPC
::
STBX8
:
case
PPC
::
STVEBX
:
ThisStoreSize
=
1
;
break
;
case
PPC
::
STH
:
case
PPC
::
STH8
:
case
PPC
::
STHU
:
case
PPC
::
STHU8
:
case
PPC
::
STHX
:
case
PPC
::
STHX8
:
case
PPC
::
STVEHX
:
case
PPC
::
STHBRX
:
ThisStoreSize
=
2
;
break
;
case
PPC
::
STFS
:
case
PPC
::
STFSU
:
case
PPC
::
STFSX
:
case
PPC
::
STWX
:
case
PPC
::
STWX8
:
case
PPC
::
STWUX
:
case
PPC
::
STW
:
case
PPC
::
STW8
:
case
PPC
::
STWU
:
case
PPC
::
STVEWX
:
case
PPC
::
STFIWX
:
case
PPC
::
STWBRX
:
ThisStoreSize
=
4
;
break
;
case
PPC
::
STD_32
:
case
PPC
::
STDX_32
:
case
PPC
::
STD
:
case
PPC
::
STDU
:
case
PPC
::
STFD
:
case
PPC
::
STFDX
:
case
PPC
::
STDX
:
case
PPC
::
STDUX
:
ThisStoreSize
=
8
;
break
;
case
PPC
::
STVX
:
case
PPC
::
STVXL
:
ThisStoreSize
=
16
;
break
;
}
StoreSize
[
NumStores
]
=
ThisStoreSize
;
StorePtr1
[
NumStores
]
=
Node
->
getOperand
(
1
)
;
StorePtr2
[
NumStores
]
=
Node
->
getOperand
(
2
)
;
++
NumStores
;
}
if
(
InstrType
==
PPCII
::
PPC970_BRU
||
isSingle
)
NumIssued
=
4
;
++
NumIssued
;
if
(
isCracked
)
++
NumIssued
;
if
(
NumIssued
==
5
)
EndDispatchGroup
(
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void X86TTI :: getUnrollingPreferences ( Loop * L , UnrollingPreferences & UP ) const { if ( ! UsePartialUnrolling ) return ; unsigned MaxBranches , MaxOps ; if ( PartialUnrollingThreshold . getNumOccurrences ( ) > 0 ) { MaxBranches = PartialUnrollingMaxBranches ; MaxOps = PartialUnrollingThreshold ; } else if ( ST -> isAtom ( ) ) { MaxBranches = 2 ; MaxOps = 10 ; } else if ( ST -> hasFSGSBase ( ) && ST -> hasXOP ( ) ) { MaxBranches = 16 ; MaxOps = 40 ; } else if ( ST -> hasFMA4 ( ) ) { return ; } else if ( ST -> hasAVX ( ) || ST -> hasSSE42 ( ) ) { MaxBranches = 8 ; MaxOps = 28 ; } else if ( ST -> hasSSSE3 ( ) ) { MaxBranches = 4 ; MaxOps = 18 ; } else { return ; } unsigned MaxDepth = 0 ; for ( df_iterator < BasicBlock * > DI = df_begin ( L -> getHeader ( ) ) , DE = df_end ( L -> getHeader ( ) ) ; DI != DE ; ) { if ( ! L -> contains ( * DI ) ) { DI . skipChildren ( ) ; continue ; } MaxDepth = std :: max ( MaxDepth , DI . getPathLength ( ) ) ; if ( MaxDepth > MaxBranches ) return ; for ( BasicBlock :: iterator I = DI -> begin ( ) , IE = DI -> end ( ) ; I != IE ; ++ I ) if ( isa < CallInst > ( I ) || isa < InvokeInst > ( I ) ) { ImmutableCallSite CS ( I ) ; if ( const Function * F = CS . getCalledFunction ( ) ) { if ( ! isLoweredToCall ( F ) ) continue ; } return ; } ++ DI ; } UP . Partial = UP . Runtime = true ; UP . PartialThreshold = UP . PartialOptSizeThreshold = MaxOps ; if ( MaxDepth > 1 ) UP . MaxCount = ( MaxBranches - 1 ) / ( MaxDepth - 1 ) ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> static enum rtx_code ix86_prepare_sse_fp_compare_args ( rtx dest , enum rtx_code code , rtx * pop0 , rtx * pop1 ) { rtx tmp ; switch ( code ) { case LTGT : case UNEQ : return UNKNOWN ; case LT : case LE : case UNGT : case UNGE : break ; case EQ : case NE : case UNORDERED : case ORDERED : if ( ! dest || ! rtx_equal_p ( dest , * pop1 ) ) break ; case GE : case GT : case UNLE : case UNLT : tmp = * pop0 ; * pop0 = * pop1 ; * pop1 = tmp ; code = swap_condition ( code ) ; break ; default : gcc_unreachable ( ) ; } return code ; } </s>

Swap , force into registers , or otherwise massage the two operands to an sse comparison with a mask result . Thus we differ a bit from ix86_prepare_fp_compare_args which expects to produce a flags result . The DEST operand exists to help determine whether to commute commutative operators . The POP0/POP1 operands are updated in place . The new comparison code is returned , or UNKNOWN if not implementable .


<s> bool MipsConstantIslands :: runOnMachineFunction ( MachineFunction & F ) { return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> static void prevent_branch_around_nothing ( void ) { rtx_insn * seen_label = NULL ; for ( rtx_insn * insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( INSN_P ( insn ) && condjump_p ( insn ) ) { seen_label = label_ref_label ( nvptx_condjump_label ( insn , false ) ) ; continue ; } if ( seen_label == NULL ) continue ; if ( NOTE_P ( insn ) || DEBUG_INSN_P ( insn ) ) continue ; if ( INSN_P ( insn ) ) switch ( recog_memoized ( insn ) ) { case CODE_FOR_nvptx_fork : case CODE_FOR_nvptx_forked : case CODE_FOR_nvptx_joining : case CODE_FOR_nvptx_join : case CODE_FOR_nop : continue ; case - 1 : if ( GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT || GET_CODE ( PATTERN ( insn ) ) == ASM_OPERANDS || ( GET_CODE ( PATTERN ( insn ) ) == PARALLEL && asm_noperands ( PATTERN ( insn ) ) >= 0 ) ) continue ; default : seen_label = NULL ; continue ; } if ( LABEL_P ( insn ) && insn == seen_label ) emit_insn_before ( gen_fake_nop ( ) , insn ) ; seen_label = NULL ; } } </s>

Insert a dummy ptx insn when encountering a branch to a label with no ptx insn inbetween the branch and the label . This works around a JIT bug observed at driver version 384.111 , at -O0 for sm_50 .


<s> bool SystemZTargetLowering :: isFMAFasterThanFMulAndFAdd ( EVT VT ) const { VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f32 : case MVT :: f64 : return true ; case MVT :: f128 : return Subtarget . hasVectorEnhancements1 ( ) ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s>
bool
M680x0InstrInfo
::
ExpandMOVSZX_RM
(
MachineInstrBuilder
&
MIB
,
bool
isSigned
,
const
MCInstrDesc
&
Desc
,
MVT
MVTDst
,
MVT
MVTSrc
)
const
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Expand "
<<
*
MIB
.
getInstr
(
)
<<
" to LOAD and "
)
;
unsigned
Dst
=
MIB
->
getOperand
(
0
)
.
getReg
(
)
;
unsigned
SubDst
=
RI
.
getSubReg
(
Dst
,
MVTSrc
==
MVT
::
i8
M680x0
::
MxSubRegIndex8Lo
:
M680x0
::
MxSubRegIndex16Lo
)
;
assert
(
SubDst
&&
"No viable SUB register available"
)
;
MIB
->
setDesc
(
Desc
)
;
MIB
->
getOperand
(
0
)
.
setReg
(
SubDst
)
;
MachineBasicBlock
::
iterator
I
=
MIB
.
getInstr
(
)
;
I
++
;
MachineBasicBlock
&
MBB
=
*
MIB
->
getParent
(
)
;
DebugLoc
DL
=
MIB
->
getDebugLoc
(
)
;
if
(
isSigned
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Sign Extend"
<<
'\n'
)
;
AddSExt
(
MBB
,
I
,
DL
,
Dst
,
MVTSrc
,
MVTDst
)
;
}
else
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Zero Extend"
<<
'\n'
)
;
AddZExt
(
MBB
,
I
,
DL
,
Dst
,
MVTSrc
,
MVTDst
)
;
}
return
true
;
}
</s>


<s> int proper_comparison_operator ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { enum rtx_code code ; if ( ! COMPARISON_P ( op ) ) return 0 ; code = GET_CODE ( op ) ; if ( GET_MODE ( XEXP ( op , 0 ) ) == CCZNmode ) return ( code == EQ || code == NE ) ; if ( GET_MODE ( XEXP ( op , 0 ) ) == CCZNCmode ) return ( code == EQ || code == NE || code == LTU || code == GEU || code == GTU || code == LEU ) ; return 1 ; } </s>

Return 1 if OP is a comparison operator valid for the mode of CC . This allows the use of MATCH_OPERATOR to recognize all the branch insns . Some insns only set a few bits in the condition code . So only allow those comparisons that use the bits that are valid .


<s> bool ARMCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { auto & TLI = * getTLI < ARMTargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb1Only ( ) ) return false ; if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; auto DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasByValOrInAllocaAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , 8 > ArgInfos ; SmallVector < unsigned , 4 > SplitRegs ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; SplitRegs . clear ( ) ; splitToValueTypes ( AInfo , ArgInfos , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { SplitRegs . push_back ( Reg ) ; } ) ; if ( ! SplitRegs . empty ( ) ) MIRBuilder . buildMerge ( VRegs [ Idx ] , SplitRegs ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> static void aarch64_add_offset_1 ( scalar_int_mode mode , rtx dest , rtx src , HOST_WIDE_INT offset , rtx temp1 , bool frame_related_p , bool emit_move_imm ) { gcc_assert ( emit_move_imm || temp1 != NULL_RTX ) ; gcc_assert ( temp1 == NULL_RTX || ! reg_overlap_mentioned_p ( temp1 , src ) ) ; HOST_WIDE_INT moffset = abs_hwi ( offset ) ; rtx_insn * insn ; if ( ! moffset ) { if ( ! rtx_equal_p ( dest , src ) ) { insn = emit_insn ( gen_rtx_SET ( dest , src ) ) ; RTX_FRAME_RELATED_P ( insn ) = frame_related_p ; } return ; } if ( aarch64_uimm12_shift ( moffset ) ) { insn = emit_insn ( gen_add3_insn ( dest , src , GEN_INT ( offset ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = frame_related_p ; return ; } if ( moffset < 0x1000000 && ( ( ! temp1 && ! can_create_pseudo_p ( ) ) || ! aarch64_move_imm ( moffset , mode ) ) ) { HOST_WIDE_INT low_off = moffset & 0xfff ; low_off = offset < 0 ? - low_off : low_off ; insn = emit_insn ( gen_add3_insn ( dest , src , GEN_INT ( low_off ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = frame_related_p ; insn = emit_insn ( gen_add2_insn ( dest , GEN_INT ( offset - low_off ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = frame_related_p ; return ; } if ( emit_move_imm ) { gcc_assert ( temp1 != NULL_RTX || can_create_pseudo_p ( ) ) ; temp1 = aarch64_force_temporary ( mode , temp1 , GEN_INT ( moffset ) ) ; } insn = emit_insn ( offset < 0 ? gen_sub3_insn ( dest , src , temp1 ) : gen_add3_insn ( dest , src , temp1 ) ) ; if ( frame_related_p ) { RTX_FRAME_RELATED_P ( insn ) = frame_related_p ; rtx adj = plus_constant ( mode , src , offset ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( dest , adj ) ) ; } } </s>

A subroutine of aarch64_add_offset . Set DEST to SRC + OFFSET for a non-polynomial OFFSET . MODE is the mode of the addition . FRAME_RELATED_P is true if the RTX_FRAME_RELATED flag should be set and CFA adjustments added to the generated instructions . TEMP1 , if nonnull , is a register of mode MODE that can be used as a temporary if register allocation is already complete . This temporary register may overlap DEST but must not overlap SRC . If TEMP1 is known to hold abs ( OFFSET ) , EMIT_MOVE_IMM can be set to false to avoid emitting the immediate again . Since this function may be used to adjust the stack pointer , we must ensure that it can not cause transient stack deallocation ( for example by first incrementing SP and then decrementing when adjusting by a large immediate ) .


<s>
bool
SIFoldOperands
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
const
SIInstrInfo
*
TII
=
static_cast
<
const
SIInstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
const
SIRegisterInfo
&
TRI
=
TII
->
getRegisterInfo
(
)
;
for
(
MachineFunction
::
iterator
BI
=
MF
.
begin
(
)
,
BE
=
MF
.
end
(
)
;
BI
!=
BE
;
++
BI
)
{
MachineBasicBlock
&
MBB
=
*
BI
;
MachineBasicBlock
::
iterator
I
,
Next
;
for
(
I
=
MBB
.
begin
(
)
;
I
!=
MBB
.
end
(
)
;
I
=
Next
)
{
Next
=
std
::
next
(
I
)
;
MachineInstr
&
MI
=
*
I
;
if
(
!
isSafeToFold
(
MI
.
getOpcode
(
)
)
)
continue
;
unsigned
OpSize
=
TII
->
getOpSize
(
MI
,
1
)
;
MachineOperand
&
OpToFold
=
MI
.
getOperand
(
1
)
;
bool
FoldingImm
=
OpToFold
.
isImm
(
)
;
if
(
!
FoldingImm
&&
!
OpToFold
.
isReg
(
)
)
continue
;
if
(
FoldingImm
&&
!
TII
->
isInlineConstant
(
OpToFold
,
OpSize
)
&&
!
MRI
.
hasOneUse
(
MI
.
getOperand
(
0
)
.
getReg
(
)
)
)
continue
;
if
(
OpToFold
.
isReg
(
)
&&
(
!
TargetRegisterInfo
::
isVirtualRegister
(
OpToFold
.
getReg
(
)
)
||
OpToFold
.
getSubReg
(
)
)
)
continue
;
SmallVector
<
MachineInstr
*
,
4
>
CopiesToReplace
;
std
::
vector
<
FoldCandidate
>
FoldList
;
for
(
MachineRegisterInfo
::
use_iterator
Use
=
MRI
.
use_begin
(
MI
.
getOperand
(
0
)
.
getReg
(
)
)
,
E
=
MRI
.
use_end
(
)
;
Use
!=
E
;
++
Use
)
{
MachineInstr
*
UseMI
=
Use
->
getParent
(
)
;
foldOperand
(
OpToFold
,
UseMI
,
Use
.
getOperandNo
(
)
,
FoldList
,
CopiesToReplace
,
TII
,
TRI
,
MRI
)
;
}
for
(
MachineInstr
*
Copy
:
CopiesToReplace
)
Copy
->
addImplicitDefUseOperands
(
MF
)
;
for
(
FoldCandidate
&
Fold
:
FoldList
)
{
if
(
updateOperand
(
Fold
,
TRI
)
)
{
if
(
!
Fold
.
isImm
(
)
)
{
assert
(
Fold
.
OpToFold
&&
Fold
.
OpToFold
->
isReg
(
)
)
;
Fold
.
OpToFold
->
setIsKill
(
false
)
;
}
DEBUG
(
dbgs
(
)
<<
"Folded source from "
<<
MI
<<
" into OpNo "
<<
Fold
.
UseOpNo
<<
" of "
<<
*
Fold
.
UseMI
<<
'\n'
)
;
}
}
}
}
return
false
;
}
</s>


<s> bool MSP430FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool HexagonMCInstrInfo :: isVector ( MCInstrInfo const & MCII , MCInst const & MCI ) { const uint64_t F = HexagonMCInstrInfo :: getDesc ( MCII , MCI ) . TSFlags ; return ( F >> HexagonII :: isCVIPos ) & HexagonII :: isCVIMask ; } </s>

Vector instructions are instructions that must fill all instruction slots within an instruction group .

Hexagon Hexagon Hexagon HexagonII::isCVIPos HexagonII::isCVIMask


<s> static void rs6000_emit_prologue_components ( sbitmap components ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; rtx ptr_reg = gen_rtx_REG ( Pmode , frame_pointer_needed ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ) ; machine_mode reg_mode = Pmode ; int reg_size = TARGET_32BIT ? 4 : 8 ; machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode ; int fp_reg_size = 8 ; if ( bitmap_bit_p ( components , 0 ) ) { rtx lr = gen_rtx_REG ( reg_mode , LR_REGNO ) ; rtx reg = gen_rtx_REG ( reg_mode , 0 ) ; rtx_insn * insn = emit_move_insn ( reg , lr ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_REGISTER , gen_rtx_SET ( reg , lr ) ) ; int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; rtx mem = copy_rtx ( SET_DEST ( single_set ( insn ) ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , gen_rtx_SET ( mem , lr ) ) ; } if ( bitmap_bit_p ( components , 2 ) ) { rtx reg = gen_rtx_REG ( reg_mode , TOC_REGNUM ) ; rtx sp_reg = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; emit_insn ( gen_frame_store ( reg , sp_reg , RS6000_TOC_SAVE_SLOT ) ) ; } int offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_gp_reg_save ; i < 32 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; rtx set = copy_rtx ( single_set ( insn ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , set ) ; } offset += reg_size ; } offset = info -> fp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_fp_reg_save ; i < 64 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( fp_reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; rtx set = copy_rtx ( single_set ( insn ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , set ) ; } offset += fp_reg_size ; } } </s>


<s> bool toc_hasher :: equal ( toc_hash_struct * h1 , toc_hash_struct * h2 ) { rtx r1 = h1 -> key ; rtx r2 = h2 -> key ; if ( h1 -> key_mode != h2 -> key_mode ) return 0 ; return rtx_equal_p ( r1 , r2 ) ; } </s>


<s> bool ARCOptAddrMode :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; AST = & MF . getSubtarget < ARCSubtarget > ( ) ; AII = AST -> getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; bool Changed = false ; for ( auto & MBB : MF ) Changed |= processBasicBlock ( MBB ) ; return Changed ; } </s>


<s> SDValue AMDGPUTargetLowering :: loadStackInputValue ( SelectionDAG & DAG , EVT VT , const SDLoc & SL , int64_t Offset ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; int FI = getOrCreateFixedStackObject ( MFI , VT . getStoreSize ( ) , Offset ) ; auto SrcPtrInfo = MachinePointerInfo :: getStack ( MF , Offset ) ; SDValue Ptr = DAG . getFrameIndex ( FI , MVT :: i32 ) ; return DAG . getLoad ( VT , SL , DAG . getEntryNode ( ) , Ptr , SrcPtrInfo , 4 , MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; } </s>

Similar to CreateLiveInRegister , except value maybe loaded from a stack slot rather than passed in a register .


<s> void NVPTXRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) + MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( getFrameRegister ( MF ) , false ) ; MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> void i386_pe_declare_function_type ( FILE * file , const char * name , int pub ) { fprintf ( file , "\t.def\t" ) ; assemble_name ( file , name ) ; fprintf ( file , ";\t.scl\t%d;\t.type\t%d;\t.endef\n" , pub ? ( int ) C_EXT : ( int ) C_STAT , ( int ) DT_FCN << N_BTSHFT ) ; } </s>

Mark a function appropriately . This should only be called for functions for which we are not emitting COFF debugging information . FILE is the assembler output file , NAME is the name of the function , and PUBLIC is nonzero if the function is globally visible .


initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool runOnMachineFunction ( MachineFunction & F ) { bool Changed = false ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; return Changed ; } </s>


<s> bool X86TTIImpl :: isLegalMaskedLoad ( Type * DataTy ) { Type * ScalarTy = DataTy -> getScalarType ( ) ; int DataWidth = ScalarTy -> getPrimitiveSizeInBits ( ) ; return ( DataWidth >= 32 && ST -> hasAVX2 ( ) ) ; } </s>

Return true if the target supports masked load .


"Patmos Single-Path Mark (machine code)"

getPassName - Return a nice clean name for a pass .


Typical stack layout should looks like this after the function 's prologue : | | -- ^ | | \ | | | arguments saved | Increasing | | on the stack | addresses PARENT arg pointer - > | | / -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - | | - space for argument split between regs & stack -- CHILD | | \ < -- ( return address here ) | | other call | | saved registers | | / -- frame pointer - > | | \ ___ | | local | | | variables |f | | / |r -- |a | | \ |m | | outgoing |e | | arguments | | Decreasing ( hard ) frame pointer | | / | | addresses and stack pointer - > | | / _|_ | -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- V


"warning: some functions compiled with BTI and some compiled "

"warning: not setting BTI in feature flags\n"

This virtual method can be overridden by targets that want to emit something at the start of their file .


<s>
void
HexagonInstPrinter
::
printInst
(
const
HexagonMCInst
*
MI
,
raw_ostream
&
O
,
StringRef
Annot
)
{
const
char
startPacket
=
'{'
,
endPacket
=
'}'
;
if
(
MI
->
getOpcode
(
)
==
Hexagon
::
ENDLOOP0
)
{
assert
(
MI
->
isPacketEnd
(
)
&&
"Loop-end must also end the packet"
)
;
if
(
MI
->
isPacketBegin
(
)
)
{
HexagonMCInst
Nop
(
Hexagon
::
NOP
)
;
StringRef
NoAnnot
;
Nop
.
setPacketBegin
(
MI
->
isPacketBegin
(
)
)
;
printInst
(
&
Nop
,
O
,
NoAnnot
)
;
}
if
(
MI
->
isPacketEnd
(
)
)
O
<<
PacketPadding
<<
endPacket
;
printInstruction
(
MI
,
O
)
;
}
else
{
if
(
MI
->
isPacketBegin
(
)
)
O
<<
PacketPadding
<<
startPacket
<<
'\n'
;
printInstruction
(
MI
,
O
)
;
if
(
MI
->
isPacketEnd
(
)
)
O
<<
'\n'
<<
PacketPadding
<<
endPacket
;
}
printAnnotation
(
O
,
Annot
)
;
}
</s>

Print the specified MCInst to the specified raw_ostream .

Hexagon
Hexagon
Hexagon
Hexagon::ENDLOOP0
"Loop-end must also end the packet"
Hexagon
Hexagon::NOP


<s> void LM32TargetLowering :: HandleByVal ( CCState * State , unsigned & Size , unsigned Align ) const { static const uint16_t ArgRegList [ ] = { LM32 :: R1 , LM32 :: R2 , LM32 :: R3 , LM32 :: R4 , LM32 :: R5 , LM32 :: R6 , LM32 :: R7 , LM32 :: R8 } ; unsigned NumWords = ( Size + 3 ) / 4 ; unsigned NewSize = 0 ; for ( unsigned i = 0 ; i < NumWords ; ++ i ) { if ( ! State -> AllocateReg ( ArgRegList , 8 ) ) { NewSize = NumWords * 4 ; break ; } } Size = NewSize ; } </s>

Target-specific cleanup for formal ByVal parameters .


<s>
void
HexagonMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
MCInst
&
HMB
=
const_cast
<
MCInst
&
>
(
MI
)
;
assert
(
HexagonMCInstrInfo
::
isBundle
(
HMB
)
)
;
DEBUG
(
dbgs
(
)
<<
"Encoding bundle\n"
;
)
;
*
Addend
=
0
;
*
Extended
=
false
;
*
CurrentBundle
=
&
MI
;
*
CurrentIndex
=
0
;
size_t
Last
=
HexagonMCInstrInfo
::
bundleSize
(
HMB
)
1
;
for
(
auto
&
I
:
HexagonMCInstrInfo
::
bundleInstructions
(
HMB
)
)
{
MCInst
&
HMI
=
const_cast
<
MCInst
&
>
(
*
I
.
getInst
(
)
)
;
verifyInstructionPredicates
(
HMI
,
computeAvailableFeatures
(
STI
.
getFeatureBits
(
)
)
)
;
EncodeSingleInstruction
(
HMI
,
OS
,
Fixups
,
STI
,
parseBits
(
Last
,
HMB
,
HMI
)
)
;
*
Extended
=
HexagonMCInstrInfo
::
isImmext
(
HMI
)
;
*
Addend
+=
HEXAGON_INSTR_SIZE
;
++
*
CurrentIndex
;
}
return
;
}
</s>

Encode the given Inst to bytes and append to CB .

Hexagon
Hexagon
Hexagon
"Encoding bundle\n"
0
0
Hexagon
1
Hexagon
Hexagon


<s> static unsigned int insn_is_swap_p ( rtx insn ) { rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) != SET ) return 0 ; rtx rhs = SET_SRC ( body ) ; if ( GET_CODE ( rhs ) != VEC_SELECT ) return 0 ; rtx parallel = XEXP ( rhs , 1 ) ; if ( GET_CODE ( parallel ) != PARALLEL ) return 0 ; unsigned int len = XVECLEN ( parallel , 0 ) ; if ( len != 2 && len != 4 && len != 8 && len != 16 ) return 0 ; for ( unsigned int i = 0 ; i < len / 2 ; ++ i ) { rtx op = XVECEXP ( parallel , 0 , i ) ; if ( GET_CODE ( op ) != CONST_INT || INTVAL ( op ) != len / 2 + i ) return 0 ; } for ( unsigned int i = len / 2 ; i < len ; ++ i ) { rtx op = XVECEXP ( parallel , 0 , i ) ; if ( GET_CODE ( op ) != CONST_INT || INTVAL ( op ) != i - len / 2 ) return 0 ; } return 1 ; } </s>

Return 1 iff INSN swaps doublewords . This may be a reg-reg swap , a permuting load , or a permuting store .


<s>
bool
R600ClauseMergePass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
*
MF
.
getFunction
(
)
)
)
return
false
;
const
R600Subtarget
&
ST
=
MF
.
getSubtarget
<
R600Subtarget
>
(
)
;
TII
=
ST
.
getInstrInfo
(
)
;
for
(
MachineFunction
::
iterator
BB
=
MF
.
begin
(
)
,
BB_E
=
MF
.
end
(
)
;
BB
!=
BB_E
;
++
BB
)
{
MachineBasicBlock
&
MBB
=
*
BB
;
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
,
E
=
MBB
.
end
(
)
;
MachineBasicBlock
::
iterator
LatestCFAlu
=
E
;
while
(
I
!=
E
)
{
MachineInstr
&
MI
=
*
I
++
;
if
(
(
!
TII
->
canBeConsideredALU
(
MI
)
&&
!
isCFAlu
(
MI
)
)
||
TII
->
mustBeLastInClause
(
MI
.
getOpcode
(
)
)
)
LatestCFAlu
=
E
;
if
(
!
isCFAlu
(
MI
)
)
continue
;
cleanPotentialDisabledCFAlu
(
MI
)
;
if
(
LatestCFAlu
!=
E
&&
mergeIfPossible
(
*
LatestCFAlu
,
MI
)
)
{
MI
.
eraseFromParent
(
)
;
}
else
{
assert
(
MI
.
getOperand
(
8
)
.
getImm
(
)
&&
"CF ALU instruction disabled"
)
;
LatestCFAlu
=
MI
;
}
}
}
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


"failed to spill SGPR to VGPR when allocated"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> static rtx_insn * emit_nop_after ( int cycles , rtx_insn * after ) { rtx_insn * insn ; if ( cycles == 10 ) cycles -- ; gcc_assert ( cycles < 10 ) ; insn = emit_insn_after ( gen_nop_count ( GEN_INT ( cycles ) ) , after ) ; PUT_MODE ( insn , TImode ) ; return insn ; } </s>

Emit a NOP instruction for CYCLES cycles after insn AFTER . Return it .


<s> SDValue AArch64TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: AND : return PerformANDCombine ( N , DCI ) ; case ISD :: OR : return PerformORCombine ( N , DCI , getSubtarget ( ) ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DCI , getSubtarget ( ) ) ; case ISD :: INTRINSIC_WO_CHAIN : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case ISD :: INTRINSIC_VOID : case ISD :: INTRINSIC_W_CHAIN : switch ( cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) -> getZExtValue ( ) ) { case Intrinsic :: arm_neon_vld1 : case Intrinsic :: arm_neon_vld2 : case Intrinsic :: arm_neon_vld3 : case Intrinsic :: arm_neon_vld4 : case Intrinsic :: arm_neon_vst1 : case Intrinsic :: arm_neon_vst2 : case Intrinsic :: arm_neon_vst3 : case Intrinsic :: arm_neon_vst4 : return CombineBaseUpdate ( N , DCI ) ; default : break ; } } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) -> findAssociatedFragment ( ) ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s> bool SIInstrInfo :: shouldClusterMemOps ( MachineInstr & FirstLdSt , MachineInstr & SecondLdSt , unsigned NumLoads ) const { const MachineOperand * FirstDst = nullptr ; const MachineOperand * SecondDst = nullptr ; if ( isDS ( FirstLdSt ) && isDS ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: vdst ) ; SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: vdst ) ; } if ( isSMRD ( FirstLdSt ) && isSMRD ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: sdst ) ; SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: sdst ) ; } if ( ( isMUBUF ( FirstLdSt ) && isMUBUF ( SecondLdSt ) ) || ( isMTBUF ( FirstLdSt ) && isMTBUF ( SecondLdSt ) ) ) { FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: vdata ) ; SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: vdata ) ; } if ( ! FirstDst || ! SecondDst ) return false ; unsigned LoadClusterThreshold = 16 ; const MachineRegisterInfo & MRI = FirstLdSt . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * DstRC = MRI . getRegClass ( FirstDst -> getReg ( ) ) ; return ( NumLoads * DstRC -> getSize ( ) ) <= LoadClusterThreshold ; } </s>

Returns true if the two given memory operations should be scheduled adjacent .

AMDGPU SI AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName 16


<s> virtual const InstrItineraryData * getInstrItineraryData ( ) const { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s>
SDValue
ARCTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SIGN_EXTEND_INREG
:
return
LowerSIGN_EXTEND_INREG
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

ARC
ARC
ISD::GlobalAddress
ISD::FRAMEADDR
ISD::SELECT_CC
ISD::BR_CC
ISD::SIGN_EXTEND_INREG
ISD::JumpTable
ISD::VASTART
"unimplemented operand"


<s>
void
AArch64RegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected"
)
;
MachineInstr
&
MI
=
*
II
;
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
AArch64InstrInfo
*
TII
=
MF
.
getSubtarget
<
AArch64Subtarget
>
(
)
.
getInstrInfo
(
)
;
const
AArch64FrameLowering
*
TFI
=
static_cast
<
const
AArch64FrameLowering
*
>
(
MF
.
getSubtarget
(
)
.
getFrameLowering
(
)
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
unsigned
FrameReg
;
int
Offset
;
if
(
MI
.
isDebugValue
(
)
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
STACKMAP
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
PATCHPOINT
)
{
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
,
true
)
;
Offset
+=
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
)
;
return
;
}
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
)
;
if
(
rewriteAArch64FrameIndex
(
MI
,
FIOperandNum
,
FrameReg
,
Offset
,
TII
)
)
return
;
assert
(
(
!
RS
||
!
RS
->
isScavengingFrameIndex
(
FrameIndex
)
)
&&
"Emergency spill slot is out of reach"
)
;
unsigned
ScratchReg
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
&
AArch64
::
GPR64RegClass
)
;
emitFrameOffset
(
MBB
,
II
,
MI
.
getDebugLoc
(
)
,
ScratchReg
,
FrameReg
,
Offset
,
TII
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
ScratchReg
,
false
,
false
,
true
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createARM64ELFObjectWriter ( OS , OSABI , IsLittleEndian ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> bool OptimizeLEAPass :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; if ( ! EnableX86LEAOpt || ! MF . getFunction ( ) -> optForSize ( ) ) return false ; MRI = & MF . getRegInfo ( ) ; TII = MF . getSubtarget < X86Subtarget > ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget < X86Subtarget > ( ) . getRegisterInfo ( ) ; for ( auto & MBB : MF ) { SmallVector < MachineInstr * , 16 > LEAs ; InstrPos . clear ( ) ; findLEAs ( MBB , LEAs ) ; if ( LEAs . empty ( ) ) continue ; if ( MF . getFunction ( ) -> optForMinSize ( ) ) Changed |= removeRedundantLEAs ( LEAs ) ; Changed |= removeRedundantAddrCalc ( LEAs ) ; } return Changed ; } </s>


<s>
void
i386_pe_seh_cold_init
(
FILE
*
f
,
const
char
*
name
)
{
struct
seh_frame_state
*
seh
;
HOST_WIDE_INT
alloc_offset
,
offset
;
if
(
!
TARGET_SEH
)
return
;
if
(
cfun
->
is_thunk
)
return
;
seh
=
cfun
->
machine
->
seh
;
fputs
(
"\t.seh_proc\t"
,
f
)
;
assemble_name
(
f
,
name
)
;
fputc
(
'\n'
,
f
)
;
offset
=
seh
->
sp_offset
INCOMING_FRAME_SP_OFFSET
;
if
(
offset
<
SEH_MAX_FRAME_SIZE
&&
!
crtl
->
accesses_prior_frames
)
alloc_offset
=
seh
->
sp_offset
;
else
alloc_offset
=
MIN
(
seh
->
cfa_offset
+
240
,
seh
->
sp_offset
)
;
offset
=
alloc_offset
INCOMING_FRAME_SP_OFFSET
;
if
(
offset
>
0
)
fprintf
(
f
,
"\t.seh_stackalloc\t"
HOST_WIDE_INT_PRINT_DEC
"\n"
,
offset
)
;
for
(
int
regno
=
0
;
regno
<
FIRST_PSEUDO_REGISTER
;
regno
++
)
if
(
seh
->
reg_offset
[
regno
]
>
0
&&
seh
->
reg_offset
[
regno
]
<=
alloc_offset
)
{
if
(
SSE_REGNO_P
(
regno
)
)
fputs
(
"\t.seh_savexmm\t"
,
f
)
;
else
if
(
GENERAL_REGNO_P
(
regno
)
)
fputs
(
"\t.seh_savereg\t"
,
f
)
;
else
gcc_unreachable
(
)
;
print_reg
(
gen_rtx_REG
(
DImode
,
regno
)
,
0
,
f
)
;
fprintf
(
f
,
", "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
alloc_offset
seh
->
reg_offset
[
regno
]
)
;
}
if
(
seh
->
cfa_reg
!=
stack_pointer_rtx
)
{
offset
=
alloc_offset
seh
->
cfa_offset
;
gcc_assert
(
(
offset
&
15
)
==
0
)
;
gcc_assert
(
IN_RANGE
(
offset
,
0
,
240
)
)
;
fputs
(
"\t.seh_setframe\t"
,
f
)
;
print_reg
(
seh
->
cfa_reg
,
0
,
f
)
;
fprintf
(
f
,
", "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
offset
)
;
}
if
(
alloc_offset
!=
seh
->
sp_offset
)
{
offset
=
seh
->
sp_offset
alloc_offset
;
if
(
offset
>
0
&&
offset
<
SEH_MAX_FRAME_SIZE
)
fprintf
(
f
,
"\t.seh_stackalloc\t"
HOST_WIDE_INT_PRINT_DEC
"\n"
,
offset
)
;
for
(
int
regno
=
0
;
regno
<
FIRST_PSEUDO_REGISTER
;
regno
++
)
if
(
seh
->
reg_offset
[
regno
]
>
alloc_offset
)
{
if
(
SSE_REGNO_P
(
regno
)
)
fputs
(
"\t.seh_savexmm\t"
,
f
)
;
else
if
(
GENERAL_REGNO_P
(
regno
)
)
fputs
(
"\t.seh_savereg\t"
,
f
)
;
else
gcc_unreachable
(
)
;
print_reg
(
gen_rtx_REG
(
DImode
,
regno
)
,
0
,
f
)
;
fprintf
(
f
,
", "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
seh
->
sp_offset
seh
->
reg_offset
[
regno
]
)
;
}
}
fputs
(
"\t.seh_endprologue\n"
,
f
)
;
}
</s>

Emit assembler directives to reconstruct the SEH state .


<s> void avr_pass_pre_proep :: compute_maybe_gasisr ( function * fun ) { for ( rtx_insn * insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( CALL_P ( insn ) ) return ; if ( AVR_HAVE_JMP_CALL && JUMP_TABLE_DATA_P ( insn ) ) return ; if ( JUMP_P ( insn ) && find_reg_note ( insn , REG_NON_LOCAL_GOTO , NULL_RTX ) ) return ; } fun -> machine -> gasisr . maybe = 1 ; } </s>

Set fun- > machine- > gasisr.maybe provided we do n't find anything that prohibits GAS generating parts of ISR prologues / epilogues for us .


<s> static int spu_builtin_vectorization_cost ( enum vect_cost_for_stmt type_of_cost , tree vectype , int misalign ATTRIBUTE_UNUSED ) { unsigned elements ; switch ( type_of_cost ) { case scalar_stmt : case vector_stmt : case vector_load : case vector_store : case vec_to_scalar : case scalar_to_vec : case cond_branch_not_taken : case vec_perm : case vec_promote_demote : return 1 ; case scalar_store : return 10 ; case scalar_load : return 2 ; case unaligned_load : return 2 ; case cond_branch_taken : return 6 ; case vec_construct : elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; return elements / 2 + 1 ; default : gcc_unreachable ( ) ; } } </s>


<s> static bool set_to_load_agen ( rtx_insn * out_insn , rtx_insn * in_insn ) { rtx out_set , in_set ; out_set = single_set ( out_insn ) ; if ( out_set ) { in_set = single_set ( in_insn ) ; if ( in_set ) return reg_mentioned_p ( SET_DEST ( out_set ) , SET_SRC ( in_set ) ) ; } return false ; } </s>

The function returns true if out_inst sets a value that is used in the address generation computation of in_insn


<s> static tree mips_builtin_decl ( unsigned int code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= ARRAY_SIZE ( mips_builtins ) ) return error_mark_node ; return mips_builtin_decls [ code ] ; } </s>


<s>
MachineBasicBlock
::
iterator
ARCInstrInfo
::
loadImmediate
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
Reg
,
uint64_t
Value
)
const
{
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
if
(
isInt
<
12
>
(
Value
)
)
{
return
BuildMI
(
MBB
,
MI
,
DL
,
get
(
ARC
::
MOV_rs12
)
,
Reg
)
.
addImm
(
Value
)
.
getInstr
(
)
;
}
llvm_unreachable
(
"Need Arc long immediate instructions."
)
;
}
</s>

Emit a series of instructions to load an immediate .


<s> virtual const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> bool GCNTTIImpl :: isAlwaysUniform ( const Value * V ) const { if ( const IntrinsicInst * Intrinsic = dyn_cast < IntrinsicInst > ( V ) ) { switch ( Intrinsic -> getIntrinsicID ( ) ) { default : return false ; case Intrinsic :: amdgcn_readfirstlane : case Intrinsic :: amdgcn_readlane : return true ; } } return false ; } </s>

Whether Val will always return a uniform value regardless of its operands .


<s> void calculate ( ) { BlockVector WorkList ; BlockSet AddedToWorkList ; Blocks . insert ( Entry ) ; for ( auto * Pred : Entry -> predecessors ( ) ) { if ( ! Enterers . count ( Pred ) ) { WorkList . push_back ( Pred ) ; AddedToWorkList . insert ( Pred ) ; } } while ( ! WorkList . empty ( ) ) { auto * MBB = WorkList . pop_back_val ( ) ; assert ( ! Enterers . count ( MBB ) ) ; if ( Blocks . insert ( MBB ) . second ) { for ( auto * Pred : MBB -> predecessors ( ) ) { if ( ! AddedToWorkList . count ( Pred ) ) { WorkList . push_back ( Pred ) ; AddedToWorkList . insert ( Pred ) ; } } } } } </s>

calculate - compute block frequency info for the given function .


<s> const MachineOperand * getNamedOperand ( const MachineInstr & MI , unsigned OpName ) const { return getNamedOperand ( const_cast < MachineInstr & > ( MI ) , OpName ) ; } </s>


<s> void R600InstrInfo :: addFlag ( MachineInstr * MI , unsigned Operand , unsigned Flag ) const { unsigned TargetFlags = get ( MI -> getOpcode ( ) ) . TSFlags ; if ( Flag == 0 ) { return ; } if ( HAS_NATIVE_OPERANDS ( TargetFlags ) ) { MachineOperand & FlagOp = getFlagOp ( MI , Operand , Flag ) ; if ( Flag == MO_FLAG_NOT_LAST ) { clearFlag ( MI , Operand , MO_FLAG_LAST ) ; } else if ( Flag == MO_FLAG_MASK ) { clearFlag ( MI , Operand , Flag ) ; } else { FlagOp . setImm ( 1 ) ; } } else { MachineOperand & FlagOp = getFlagOp ( MI , Operand ) ; FlagOp . setImm ( FlagOp . getImm ( ) | ( Flag << ( NUM_MO_FLAGS * Operand ) ) ) ; } } </s>

Add one of the MO_FLAG * flags to the specified Operand .


<s> unsigned char X86Subtarget :: classifyGlobalReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return X86II :: MO_NO_FLAG ; if ( GV && GV -> isAbsoluteSymbolRef ( ) ) return X86II :: MO_NO_FLAG ; if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return classifyLocalReference ( GV ) ; if ( isTargetCOFF ( ) ) return X86II :: MO_DLLIMPORT ; if ( is64Bit ( ) ) return X86II :: MO_GOTPCREL ; if ( isTargetDarwin ( ) ) { if ( ! isPositionIndependent ( ) ) return X86II :: MO_DARWIN_NONLAZY ; return X86II :: MO_DARWIN_NONLAZY_PIC_BASE ; } return X86II :: MO_GOT ; } </s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s> static void mep_setup_incoming_varargs ( cumulative_args_t cum , machine_mode mode ATTRIBUTE_UNUSED , tree type ATTRIBUTE_UNUSED , int * pretend_size , int second_time ATTRIBUTE_UNUSED ) { int nsave = 4 - ( get_cumulative_args ( cum ) -> nregs + 1 ) ; if ( nsave > 0 ) cfun -> machine -> arg_regs_to_save = nsave ; * pretend_size = nsave * 4 ; } </s>


<s> int rl78_hard_regno_nregs ( int regno , machine_mode mode ) { int rs = register_sizes [ regno ] ; if ( rs < 1 ) rs = 1 ; return ( ( GET_MODE_SIZE ( mode ) + rs - 1 ) / rs ) ; } </s>


<s>
const
MCPhysReg
*
X86RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"MachineFunction required"
)
;
const
X86Subtarget
&
Subtarget
=
MF
->
getSubtarget
<
X86Subtarget
>
(
)
;
bool
HasSSE
=
Subtarget
.
hasSSE1
(
)
;
bool
HasAVX
=
Subtarget
.
hasAVX
(
)
;
bool
HasAVX512
=
Subtarget
.
hasAVX512
(
)
;
bool
CallsEHReturn
=
MF
->
callsEHReturn
(
)
;
switch
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
)
{
case
CallingConv
::
GHC
:
case
CallingConv
::
HiPE
:
return
CSR_NoRegs_SaveList
;
case
CallingConv
::
AnyReg
:
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
return
CSR_64_AllRegs_SaveList
;
case
CallingConv
::
PreserveMost
:
return
CSR_64_RT_MostRegs_SaveList
;
case
CallingConv
::
PreserveAll
:
if
(
HasAVX
)
return
CSR_64_RT_AllRegs_AVX_SaveList
;
return
CSR_64_RT_AllRegs_SaveList
;
case
CallingConv
::
CXX_FAST_TLS
:
if
(
Is64Bit
)
return
MF
->
getInfo
<
X86MachineFunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_64_CXX_TLS_Darwin_PE_SaveList
:
CSR_64_TLS_Darwin_SaveList
;
break
;
case
CallingConv
::
Intel_OCL_BI
:
{
if
(
HasAVX512
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX512
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX_SaveList
;
if
(
HasAVX
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX_SaveList
;
if
(
!
HasAVX
&&
!
IsWin64
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_SaveList
;
break
;
}
case
CallingConv
::
HHVM
:
return
CSR_64_HHVM_SaveList
;
case
CallingConv
::
X86_RegCall
:
if
(
Is64Bit
)
{
if
(
IsWin64
)
{
return
(
HasSSE
CSR_Win64_RegCall_SaveList
:
CSR_Win64_RegCall_NoSSE_SaveList
)
;
}
else
{
return
(
HasSSE
CSR_SysV64_RegCall_SaveList
:
CSR_SysV64_RegCall_NoSSE_SaveList
)
;
}
}
else
{
return
(
HasSSE
CSR_32_RegCall_SaveList
:
CSR_32_RegCall_NoSSE_SaveList
)
;
}
case
CallingConv
::
Cold
:
if
(
Is64Bit
)
return
CSR_64_MostRegs_SaveList
;
break
;
case
CallingConv
::
X86_64_Win64
:
if
(
!
HasSSE
)
return
CSR_Win64_NoSSE_SaveList
;
return
CSR_Win64_SaveList
;
case
CallingConv
::
X86_64_SysV
:
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
case
CallingConv
::
X86_INTR
:
if
(
Is64Bit
)
{
if
(
HasAVX512
)
return
CSR_64_AllRegs_AVX512_SaveList
;
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
return
CSR_64_AllRegs_SaveList
;
}
else
{
if
(
HasAVX512
)
return
CSR_32_AllRegs_AVX512_SaveList
;
if
(
HasAVX
)
return
CSR_32_AllRegs_AVX_SaveList
;
if
(
HasSSE
)
return
CSR_32_AllRegs_SSE_SaveList
;
return
CSR_32_AllRegs_SaveList
;
}
default
:
break
;
}
if
(
Is64Bit
)
{
if
(
IsWin64
)
{
if
(
!
HasSSE
)
return
CSR_Win64_NoSSE_SaveList
;
return
CSR_Win64_SaveList
;
}
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
if
(
Subtarget
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
->
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_64_SwiftError_SaveList
;
return
CSR_64_SaveList
;
}
if
(
CallsEHReturn
)
return
CSR_32EHRet_SaveList
;
return
CSR_32_SaveList
;
}
</s>


<s> unsigned size ( ) const { return Uses . size ( ) ; } </s>

The number of name/type pairs is returned .


<s> static int avr_operand_rtx_cost ( rtx x , machine_mode mode , enum rtx_code outer , int opno , bool speed ) { enum rtx_code code = GET_CODE ( x ) ; int total ; switch ( code ) { case REG : case SUBREG : return 0 ; case CONST_INT : case CONST_FIXED : case CONST_DOUBLE : return COSTS_N_INSNS ( GET_MODE_SIZE ( mode ) ) ; default : break ; } total = 0 ; avr_rtx_costs ( x , code , outer , opno , & total , speed ) ; return total ; } </s>

Mutually recursive subroutine of avr_rtx_cost for calculating the cost of an RTX operand given its context . X is the rtx of the operand , MODE is its mode , and OUTER is the rtx_code of this operand 's parent operator .


<s> int valid_dbcc_comparison_p_2 ( rtx x , machine_mode mode ATTRIBUTE_UNUSED ) { switch ( GET_CODE ( x ) ) { case EQ : case NE : case GTU : case LTU : case GEU : case LEU : return 1 ; case GT : case LT : case GE : case LE : return ! ( cc_prev_status . flags & CC_NO_OVERFLOW ) ; default : return 0 ; } } </s>

Return true if X is a valid comparison operator for the dbcc instruction . Note it rejects floating point comparison operators . ( In the future we could use Fdbcc ) . It also rejects some comparisons when CC_NO_OVERFLOW is set .


<s> static tree ix86_stack_protect_guard ( void ) { if ( TARGET_SSP_TLS_GUARD ) { tree type_node = lang_hooks . types . type_for_mode ( ptr_mode , 1 ) ; int qual = ENCODE_QUAL_ADDR_SPACE ( ix86_stack_protector_guard_reg ) ; tree type = build_qualified_type ( type_node , qual ) ; tree t ; if ( OPTION_SET_P ( ix86_stack_protector_guard_symbol_str ) ) { t = ix86_tls_stack_chk_guard_decl ; if ( t == NULL ) { rtx x ; t = build_decl ( UNKNOWN_LOCATION , VAR_DECL , get_identifier ( ix86_stack_protector_guard_symbol_str ) , type ) ; TREE_STATIC ( t ) = 1 ; TREE_PUBLIC ( t ) = 1 ; DECL_EXTERNAL ( t ) = 1 ; TREE_USED ( t ) = 1 ; TREE_THIS_VOLATILE ( t ) = 1 ; DECL_ARTIFICIAL ( t ) = 1 ; DECL_IGNORED_P ( t ) = 1 ; x = DECL_RTL ( t ) ; RTX_FLAG ( x , used ) = 1 ; ix86_tls_stack_chk_guard_decl = t ; } } else { tree asptrtype = build_pointer_type ( type ) ; t = build_int_cst ( asptrtype , ix86_stack_protector_guard_offset ) ; t = build2 ( MEM_REF , asptrtype , t , build_int_cst ( asptrtype , 0 ) ) ; TREE_THIS_VOLATILE ( t ) = 1 ; } return t ; } return default_stack_protect_guard ( ) ; } </s>

If using TLS guards , do n't waste time creating and expanding __stack_chk_guard decl and MEM as we are going to ignore it .


"Unexpected register class in CSRsViaCopy!"

"Function should be nounwind in insertCopiesSplitCSR!"

Insert explicit copies in entry and exit blocks .


<s> inline void function_expander :: add_scalar_move_mask_operand ( machine_mode mode ) { add_input_operand ( mode , gen_scalar_move_mask ( mode ) ) ; } </s>

Add mask operand for scalar move instruction .


<s> uint32_t AMDGPUDevice :: getStackAlignment ( ) const { return 16 ; } </s>

Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget .


"Should be saving %r15 and something else"

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> std :: pair < uint16_t , uint16_t > X86InstrInfo :: getExecutionDomain ( const MachineInstr & MI ) const { uint16_t domain = ( MI . getDesc ( ) . TSFlags >> X86II :: SSEDomainShift ) & 3 ; unsigned opcode = MI . getOpcode ( ) ; uint16_t validDomains = 0 ; if ( domain ) { validDomains = getExecutionDomainCustom ( MI ) ; if ( validDomains ) return std :: make_pair ( domain , validDomains ) ; if ( lookup ( opcode , domain , ReplaceableInstrs ) ) { validDomains = 0xe ; } else if ( lookup ( opcode , domain , ReplaceableInstrsAVX2 ) ) { validDomains = Subtarget . hasAVX2 ( ) ? 0xe : 0x6 ; } else if ( lookup ( opcode , domain , ReplaceableInstrsFP ) ) { validDomains = 0x6 ; } else if ( lookup ( opcode , domain , ReplaceableInstrsAVX2InsertExtract ) ) { if ( ! Subtarget . hasAVX2 ( ) ) return std :: make_pair ( 0 , 0 ) ; validDomains = 0xe ; } else if ( lookupAVX512 ( opcode , domain , ReplaceableInstrsAVX512 ) ) { validDomains = 0xe ; } else if ( Subtarget . hasDQI ( ) && lookupAVX512 ( opcode , domain , ReplaceableInstrsAVX512DQ ) ) { validDomains = 0xe ; } else if ( Subtarget . hasDQI ( ) ) { if ( const uint16_t * table = lookupAVX512 ( opcode , domain , ReplaceableInstrsAVX512DQMasked ) ) { if ( domain == 1 || ( domain == 3 && table [ 3 ] == opcode ) ) validDomains = 0xa ; else validDomains = 0xc ; } } } return std :: make_pair ( domain , validDomains ) ; } </s>

Return the current execution domain and bit mask of possible domains for instruction .


"Cannot store this register to stack slot!"

Store the specified register of the given register class to the specified stack frame index .


<s> static void ix86_emit_support_tinfos ( emit_support_tinfos_callback callback ) { extern tree ix86_float16_type_node ; extern tree ix86_bf16_type_node ; if ( ! TARGET_SSE2 ) { gcc_checking_assert ( ! float16_type_node && ! bfloat16_type_node ) ; float16_type_node = ix86_float16_type_node ; bfloat16_type_node = ix86_bf16_type_node ; callback ( float16_type_node ) ; callback ( bfloat16_type_node ) ; float16_type_node = NULL_TREE ; bfloat16_type_node = NULL_TREE ; } } </s>

Create C++ tinfo symbols for only conditionally available fundamental types .