<s> unsigned AMDGPURegisterBankInfo :: copyCost ( const RegisterBank & Dst , const RegisterBank & Src , unsigned Size ) const { if ( Dst . getID ( ) == AMDGPU :: SGPRRegBankID && isVectorRegisterBank ( Src ) ) { return std :: numeric_limits < unsigned > :: max ( ) ; } if ( Size == 1 && ( Dst . getID ( ) == AMDGPU :: SCCRegBankID || Dst . getID ( ) == AMDGPU :: SGPRRegBankID ) && ( isVectorRegisterBank ( Src ) || Src . getID ( ) == AMDGPU :: SGPRRegBankID || Src . getID ( ) == AMDGPU :: VCCRegBankID ) ) return std :: numeric_limits < unsigned > :: max ( ) ; if ( Dst . getID ( ) == AMDGPU :: SCCRegBankID && Src . getID ( ) == AMDGPU :: VCCRegBankID ) return std :: numeric_limits < unsigned > :: max ( ) ; if ( Dst . getID ( ) == AMDGPU :: AGPRRegBankID && Src . getID ( ) == AMDGPU :: AGPRRegBankID ) return 4 ; return RegisterBankInfo :: copyCost ( Dst , Src , Size ) ; } </s>

Get the cost of a copy from B to A , or put differently , get the cost of A = COPY B .

AMDGPU AMDGPU AMDGPU::SGPRRegBankID 1 AMDGPU::SCCRegBankID AMDGPU::SGPRRegBankID AMDGPU::SGPRRegBankID AMDGPU::VCCRegBankID AMDGPU::SCCRegBankID AMDGPU::VCCRegBankID AMDGPU::AGPRRegBankID AMDGPU::AGPRRegBankID 4


<s> bool PPCPassConfig :: addILPOpts ( ) { addPass ( & EarlyIfConverterID ) ; if ( EnableMachineCombinerPass ) addPass ( & MachineCombinerID ) ; return true ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .


<s> virtual const NVPTXSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool ARMTTIImpl :: areInlineCompatible ( const Function * Caller , const Function * Callee ) const { const TargetMachine & TM = getTLI ( ) -> getTargetMachine ( ) ; const FeatureBitset & CallerBits = TM . getSubtargetImpl ( * Caller ) -> getFeatureBits ( ) ; const FeatureBitset & CalleeBits = TM . getSubtargetImpl ( * Callee ) -> getFeatureBits ( ) ; bool MatchExact = ( CallerBits & ~ InlineFeaturesAllowed ) == ( CalleeBits & ~ InlineFeaturesAllowed ) ; bool MatchSubset = ( ( CallerBits & CalleeBits ) & InlineFeaturesAllowed ) == ( CalleeBits & InlineFeaturesAllowed ) ; return MatchExact && MatchSubset ; } </s>

Determine whether a callee with the given TLI can be inlined into caller with this TLI , based on 'nobuiltin ' attributes .


<s> bool MipsCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; return false ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> bool HexagonInstrInfo :: isSchedulingBoundary ( const MachineInstr * MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( MI -> isDebugValue ( ) ) return false ; if ( MI -> getDesc ( ) . isTerminator ( ) || MI -> isPosition ( ) || MI -> isInlineAsm ( ) ) return true ; return false ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> unsigned getSlotSize ( ) const { return SlotSize ; } </s>

getSlotSize - Stack slot size in bytes .


<s> static int available_regs ( ) { static int n = - 1 ; int i ; if ( n >= 0 ) return n ; for ( i = n = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ , n ++ ) if ( ( fixed_regs [ i ] && n != 0 ) || i == HARD_FRAME_POINTER_REGNUM || i == PIC_SOMETHING_REGNUM || i == STATIC_CHAIN_REGNUM ) break ; return n ; } </s>

Return the number of registers available for -mregparm , -mreturn-regs , and -mcall-clobbered .


<s> static void tilepro_print_operand_address ( FILE * file , machine_mode mode , rtx addr ) { if ( GET_CODE ( addr ) == POST_DEC || GET_CODE ( addr ) == POST_INC ) { int offset = GET_MODE_SIZE ( mode ) ; gcc_assert ( mode != VOIDmode ) ; if ( output_memory_autoinc_first ) fprintf ( file , "%s" , reg_names [ REGNO ( XEXP ( addr , 0 ) ) ] ) ; else fprintf ( file , "%d" , GET_CODE ( addr ) == POST_DEC ? - offset : offset ) ; } else if ( GET_CODE ( addr ) == POST_MODIFY ) { gcc_assert ( mode != VOIDmode ) ; gcc_assert ( GET_CODE ( XEXP ( addr , 1 ) ) == PLUS ) ; if ( output_memory_autoinc_first ) fprintf ( file , "%s" , reg_names [ REGNO ( XEXP ( addr , 0 ) ) ] ) ; else fprintf ( file , HOST_WIDE_INT_PRINT_DEC , INTVAL ( XEXP ( XEXP ( addr , 1 ) , 1 ) ) ) ; } else tilepro_print_operand ( file , addr , 'r' ) ; } </s>


<s> bool writeNopData ( raw_ostream & OS , uint64_t Count ) const override { if ( Count % 4 != 0 ) return false ; uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) support :: endian :: write < uint32_t > ( OS , 0x01000000 , Endian ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> static unsigned HOST_WIDE_INT aarch64_replicate_bitmask_imm ( unsigned HOST_WIDE_INT val , machine_mode mode ) { unsigned int size = GET_MODE_UNIT_PRECISION ( mode ) ; while ( size < 64 ) { val &= ( HOST_WIDE_INT_1U << size ) - 1 ; val |= val << size ; size *= 2 ; } return val ; } </s>

VAL is a value with the inner mode of MODE . Replicate it to fill a 64-bit ( DImode ) integer .


<s> bool ARMTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( Subtarget -> isThumb1Only ( ) ) return false ; EVT VT ; SDValue Ptr ; Align Alignment ; bool isSEXTLoad = false ; bool IsMasked = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; Alignment = LD -> getAlign ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == ISD :: SEXTLOAD ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Alignment = ST -> getAlign ( ) ; } else if ( MaskedLoadSDNode * LD = dyn_cast < MaskedLoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; Alignment = LD -> getAlign ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == ISD :: SEXTLOAD ; IsMasked = true ; } else if ( MaskedStoreSDNode * ST = dyn_cast < MaskedStoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Alignment = ST -> getAlign ( ) ; IsMasked = true ; } else return false ; bool isInc ; bool isLegal = false ; if ( VT . isVector ( ) ) isLegal = Subtarget -> hasMVEIntegerOps ( ) && getMVEIndexedAddressParts ( Ptr . getNode ( ) , VT , Alignment , isSEXTLoad , IsMasked , Subtarget -> isLittle ( ) , Base , Offset , isInc , DAG ) ; else { if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = getARMIndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; } if ( ! isLegal ) return false ; AM = isInc ? ISD :: PRE_INC : ISD :: PRE_DEC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .

ARM ARM ISD::MemIndexedMode ISD::SEXTLOAD ISD::SEXTLOAD ARM ISD::PRE_INC ISD::PRE_DEC


<s> void SITypeRewriter :: visitCallInst ( CallInst & I ) { IRBuilder < > Builder ( & I ) ; SmallVector < Value * , 8 > Args ; SmallVector < Type * , 8 > Types ; bool NeedToReplace = false ; Function * F = I . getCalledFunction ( ) ; std :: string Name = F -> getName ( ) . str ( ) ; for ( unsigned i = 0 , e = I . getNumArgOperands ( ) ; i != e ; ++ i ) { Value * Arg = I . getArgOperand ( i ) ; if ( Arg -> getType ( ) == v16i8 ) { Args . push_back ( Builder . CreateBitCast ( Arg , v4i32 ) ) ; Types . push_back ( v4i32 ) ; NeedToReplace = true ; Name = Name + ".v4i32" ; } else if ( Arg -> getType ( ) -> isVectorTy ( ) && Arg -> getType ( ) -> getVectorNumElements ( ) == 1 && Arg -> getType ( ) -> getVectorElementType ( ) == Type :: getInt32Ty ( I . getContext ( ) ) ) { Type * ElementTy = Arg -> getType ( ) -> getVectorElementType ( ) ; std :: string TypeName = "i32" ; InsertElementInst * Def = cast < InsertElementInst > ( Arg ) ; Args . push_back ( Def -> getOperand ( 1 ) ) ; Types . push_back ( ElementTy ) ; std :: string VecTypeName = "v1" + TypeName ; Name = Name . replace ( Name . find ( VecTypeName ) , VecTypeName . length ( ) , TypeName ) ; NeedToReplace = true ; } else { Args . push_back ( Arg ) ; Types . push_back ( Arg -> getType ( ) ) ; } } if ( ! NeedToReplace ) { return ; } Function * NewF = Mod -> getFunction ( Name ) ; if ( ! NewF ) { NewF = Function :: Create ( FunctionType :: get ( F -> getReturnType ( ) , Types , false ) , GlobalValue :: ExternalLinkage , Name , Mod ) ; NewF -> setAttributes ( F -> getAttributes ( ) ) ; } I . replaceAllUsesWith ( Builder . CreateCall ( NewF , Args ) ) ; I . eraseFromParent ( ) ; } </s>


<s> static inline bool is_brk_interrupt_func ( const_tree decl ) { return has_func_attr ( decl , "brk_interrupt" ) ; } </s>

Returns true if the provided function has the `` brk_interrupt '' attribute .


<s> SMLoc getLoc ( ) const { return getParser ( ) . getTok ( ) . getLoc ( ) ; } </s>

Get the source location of the point where the field was defined .


<s> unsigned ARMBaseRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; const ARMFrameLowering * TFI = getFrameLowering ( MF ) ; if ( TFI -> hasFP ( MF ) ) return getFramePointerReg ( STI ) ; return ARM :: SP ; } </s>


<s> static SDValue getTruncateOrZeroExtend ( SDValue V , SelectionDAG & DAG , MVT ToVT ) { SDNodeTreeBuilder b ( V , & DAG ) ; MVT VT = V . getSimpleValueType ( ) ; if ( VT . bitsLT ( ToVT ) ) return b . ZERO_EXTEND ( V , ToVT ) ; else if ( VT . bitsGT ( ToVT ) ) return b . TRUNCATE ( V , ToVT ) ; return V ; } </s>

Return a SCEV corresponding to a conversion of the input value to the specified type .


"%qE attribute have effect only on public objects"

Handle a `` nodirect_extern_access '' attribute ; arguments as in struct attribute_spec.handler .


<s> bool HexagonTargetLowering :: isShuffleMaskLegal ( ArrayRef < int > Mask , EVT VT ) const { return true ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> static int ix86_flags_dependant ( rtx insn , rtx dep_insn , enum attr_type insn_type ) { rtx set , set2 ; if ( insn_type != TYPE_SETCC && insn_type != TYPE_ICMOV && insn_type != TYPE_FCMOV && insn_type != TYPE_IBR ) return 0 ; if ( ( set = single_set ( dep_insn ) ) != 0 ) { set = SET_DEST ( set ) ; set2 = NULL_RTX ; } else if ( GET_CODE ( PATTERN ( dep_insn ) ) == PARALLEL && XVECLEN ( PATTERN ( dep_insn ) , 0 ) == 2 && GET_CODE ( XVECEXP ( PATTERN ( dep_insn ) , 0 , 0 ) ) == SET && GET_CODE ( XVECEXP ( PATTERN ( dep_insn ) , 0 , 1 ) ) == SET ) { set = SET_DEST ( XVECEXP ( PATTERN ( dep_insn ) , 0 , 0 ) ) ; set2 = SET_DEST ( XVECEXP ( PATTERN ( dep_insn ) , 0 , 0 ) ) ; } else return 0 ; if ( GET_CODE ( set ) != REG || REGNO ( set ) != FLAGS_REG ) return 0 ; if ( ! reg_overlap_mentioned_p ( set , PATTERN ( insn ) ) ) return 0 ; if ( set2 && reg_overlap_mentioned_p ( set2 , PATTERN ( insn ) ) ) return 0 ; return 1 ; } </s>

A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set by DEP_INSN and nothing set by DEP_INSN .


<s> bool PTXAsmPrinter :: doFinalization ( Module & M ) { Module :: GlobalListType & global_list = M . getGlobalList ( ) ; int i , n = global_list . size ( ) ; GlobalVariable * * gv_array = new GlobalVariable * [ n ] ; i = 0 ; for ( Module :: global_iterator I = global_list . begin ( ) , E = global_list . end ( ) ; I != E ; ++ I ) gv_array [ i ++ ] = & * I ; while ( ! global_list . empty ( ) ) global_list . remove ( global_list . begin ( ) ) ; bool ret = AsmPrinter :: doFinalization ( M ) ; for ( i = 0 ; i < n ; i ++ ) global_list . insert ( global_list . end ( ) , gv_array [ i ] ) ; delete [ ] gv_array ; return ret ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s>
SDValue
X86TargetLowering
::
BuildSDIVPow2
(
SDNode
*
N
,
const
APInt
&
Divisor
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDNode
*
>
&
Created
)
const
{
AttributeList
Attr
=
DAG
.
getMachineFunction
(
)
.
getFunction
(
)
.
getAttributes
(
)
;
if
(
isIntDivCheap
(
N
->
getValueType
(
0
)
,
Attr
)
)
return
SDValue
(
N
,
0
)
;
assert
(
(
Divisor
.
isPowerOf2
(
)
||
(
Divisor
)
.
isPowerOf2
(
)
)
&&
"Unexpected divisor!"
)
;
if
(
!
Subtarget
.
hasCMov
(
)
)
return
SDValue
(
)
;
EVT
VT
=
N
->
getValueType
(
0
)
;
if
(
VT
!=
MVT
::
i16
&&
VT
!=
MVT
::
i32
&&
!
(
Subtarget
.
is64Bit
(
)
&&
VT
==
MVT
::
i64
)
)
return
SDValue
(
)
;
unsigned
Lg2
=
Divisor
.
countTrailingZeros
(
)
;
if
(
Lg2
==
1
)
return
SDValue
(
)
;
SDLoc
DL
(
N
)
;
SDValue
N0
=
N
->
getOperand
(
0
)
;
SDValue
Zero
=
DAG
.
getConstant
(
0
,
DL
,
VT
)
;
APInt
Lg2Mask
=
APInt
::
getLowBitsSet
(
VT
.
getSizeInBits
(
)
,
Lg2
)
;
SDValue
Pow2MinusOne
=
DAG
.
getConstant
(
Lg2Mask
,
DL
,
VT
)
;
SDValue
Cmp
=
DAG
.
getSetCC
(
DL
,
MVT
::
i8
,
N0
,
Zero
,
ISD
::
SETLT
)
;
SDValue
Add
=
DAG
.
getNode
(
ISD
::
ADD
,
DL
,
VT
,
N0
,
Pow2MinusOne
)
;
SDValue
CMov
=
DAG
.
getNode
(
ISD
::
SELECT
,
DL
,
VT
,
Cmp
,
Add
,
N0
)
;
Created
.
push_back
(
Cmp
.
getNode
(
)
)
;
Created
.
push_back
(
Add
.
getNode
(
)
)
;
Created
.
push_back
(
CMov
.
getNode
(
)
)
;
SDValue
SRA
=
DAG
.
getNode
(
ISD
::
SRA
,
DL
,
VT
,
CMov
,
DAG
.
getConstant
(
Lg2
,
DL
,
MVT
::
i64
)
)
;
if
(
Divisor
.
isNonNegative
(
)
)
return
SRA
;
Created
.
push_back
(
SRA
.
getNode
(
)
)
;
return
DAG
.
getNode
(
ISD
::
SUB
,
DL
,
VT
,
Zero
,
SRA
)
;
}
</s>

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators .


<s> bool RISCVTargetLowering :: isShuffleMaskLegal ( ArrayRef < int > M , EVT VT ) const { if ( ShuffleVectorSDNode :: isSplatMask ( M . data ( ) , VT ) ) return true ; return false ; } </s>


<s> TargetTransformInfo HexagonTargetMachine :: getTargetTransformInfo ( const Function & F ) const { return TargetTransformInfo ( HexagonTTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> bool invalid_e500_subreg ( rtx op , machine_mode mode ) { if ( TARGET_E500_DOUBLE ) { if ( GET_CODE ( op ) == SUBREG && ( mode == SImode || mode == DImode || mode == TImode || mode == DDmode || mode == TDmode || mode == PTImode ) && REG_P ( SUBREG_REG ( op ) ) && ( GET_MODE ( SUBREG_REG ( op ) ) == DFmode || GET_MODE ( SUBREG_REG ( op ) ) == TFmode || GET_MODE ( SUBREG_REG ( op ) ) == IFmode || GET_MODE ( SUBREG_REG ( op ) ) == KFmode ) ) return true ; if ( GET_CODE ( op ) == SUBREG && ( mode == DFmode || mode == TFmode || mode == IFmode || mode == KFmode ) && REG_P ( SUBREG_REG ( op ) ) && ( GET_MODE ( SUBREG_REG ( op ) ) == DImode || GET_MODE ( SUBREG_REG ( op ) ) == TImode || GET_MODE ( SUBREG_REG ( op ) ) == PTImode || GET_MODE ( SUBREG_REG ( op ) ) == DDmode || GET_MODE ( SUBREG_REG ( op ) ) == TDmode ) ) return true ; } if ( TARGET_SPE && GET_CODE ( op ) == SUBREG && mode == SImode && REG_P ( SUBREG_REG ( op ) ) && SPE_VECTOR_MODE ( GET_MODE ( SUBREG_REG ( op ) ) ) ) return true ; return false ; } </s>

Return TRUE if OP is an invalid SUBREG operation on the e500 .


<s> bool FISCPassConfig :: addPreISel ( ) { return false ; } </s>


<s> MachineBasicBlock :: iterator XCoreInstrInfo :: loadImmediate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned Reg , uint64_t Value ) const { DebugLoc dl ; if ( MI != MBB . end ( ) && ! MI -> isDebugValue ( ) ) dl = MI -> getDebugLoc ( ) ; if ( isImmMskBitp ( Value ) ) { int N = Log2_32 ( Value ) + 1 ; return BuildMI ( MBB , MI , dl , get ( XCore :: MKMSK_rus ) , Reg ) . addImm ( N ) . getInstr ( ) ; } if ( isImmU16 ( Value ) ) { int Opcode = isImmU6 ( Value ) ? XCore :: LDC_ru6 : XCore :: LDC_lru6 ; return BuildMI ( MBB , MI , dl , get ( Opcode ) , Reg ) . addImm ( Value ) . getInstr ( ) ; } MachineConstantPool * ConstantPool = MBB . getParent ( ) -> getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) . getContext ( ) ) , Value ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; return BuildMI ( MBB , MI , dl , get ( XCore :: LDWCP_lru6 ) , Reg ) . addConstantPoolIndex ( Idx ) . getInstr ( ) ; } </s>

Emit a series of instructions to load an immediate .


<s> void ix86_expand_vector_logical_operator ( enum rtx_code code , machine_mode mode , rtx operands [ ] ) { rtx op1 = NULL_RTX , op2 = NULL_RTX ; if ( SUBREG_P ( operands [ 1 ] ) ) { op1 = operands [ 1 ] ; op2 = operands [ 2 ] ; } else if ( SUBREG_P ( operands [ 2 ] ) ) { op1 = operands [ 2 ] ; op2 = operands [ 1 ] ; } if ( op1 && ! TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL && ( SUBREG_P ( op2 ) || GET_CODE ( op2 ) == CONST_VECTOR ) && GET_MODE_CLASS ( GET_MODE ( SUBREG_REG ( op1 ) ) ) == MODE_VECTOR_FLOAT && GET_MODE_SIZE ( GET_MODE ( SUBREG_REG ( op1 ) ) ) == GET_MODE_SIZE ( mode ) && SUBREG_BYTE ( op1 ) == 0 && ( GET_CODE ( op2 ) == CONST_VECTOR || ( GET_MODE ( SUBREG_REG ( op1 ) ) == GET_MODE ( SUBREG_REG ( op2 ) ) && SUBREG_BYTE ( op2 ) == 0 ) ) && can_create_pseudo_p ( ) ) { rtx dst ; switch ( GET_MODE ( SUBREG_REG ( op1 ) ) ) { case V4SFmode : case V8SFmode : case V16SFmode : case V2DFmode : case V4DFmode : case V8DFmode : dst = gen_reg_rtx ( GET_MODE ( SUBREG_REG ( op1 ) ) ) ; if ( GET_CODE ( op2 ) == CONST_VECTOR ) { op2 = gen_lowpart ( GET_MODE ( dst ) , op2 ) ; op2 = force_reg ( GET_MODE ( dst ) , op2 ) ; } else { op1 = operands [ 1 ] ; op2 = SUBREG_REG ( operands [ 2 ] ) ; if ( ! vector_operand ( op2 , GET_MODE ( dst ) ) ) op2 = force_reg ( GET_MODE ( dst ) , op2 ) ; } op1 = SUBREG_REG ( op1 ) ; if ( ! vector_operand ( op1 , GET_MODE ( dst ) ) ) op1 = force_reg ( GET_MODE ( dst ) , op1 ) ; emit_insn ( gen_rtx_SET ( dst , gen_rtx_fmt_ee ( code , GET_MODE ( dst ) , op1 , op2 ) ) ) ; emit_move_insn ( operands [ 0 ] , gen_lowpart ( mode , dst ) ) ; return ; default : break ; } } if ( ! vector_operand ( operands [ 1 ] , mode ) ) operands [ 1 ] = force_reg ( mode , operands [ 1 ] ) ; if ( ! vector_operand ( operands [ 2 ] , mode ) ) operands [ 2 ] = force_reg ( mode , operands [ 2 ] ) ; ix86_fixup_binary_operands_no_copy ( code , mode , operands ) ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , gen_rtx_fmt_ee ( code , mode , operands [ 1 ] , operands [ 2 ] ) ) ) ; } </s>

Expand vector logical operation CODE ( AND , IOR , XOR ) in MODE with the given OPERANDS .


<s>
unsigned
MipsCodeEmitter
::
getBranchTargetOpValueMM
(
const
MachineInstr
&
MI
,
unsigned
OpNo
)
const
{
llvm_unreachable
(
"Unimplemented function."
)
;
return
0
;
}
</s>

getBranchTargetOpValue - Return binary encoding of the microMIPS branch target operand .


<s> const TargetRegisterClass * X86RegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { if ( RC == & X86 :: GR8_NOREXRegClass ) return RC ; const X86Subtarget & Subtarget = MF . getSubtarget < X86Subtarget > ( ) ; const TargetRegisterClass * Super = RC ; TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case X86 :: FR32RegClassID : case X86 :: FR64RegClassID : if ( ! Subtarget . hasAVX512 ( ) && getRegSizeInBits ( * Super ) == getRegSizeInBits ( * RC ) ) return Super ; break ; case X86 :: VR128RegClassID : case X86 :: VR256RegClassID : if ( ! Subtarget . hasVLX ( ) && getRegSizeInBits ( * Super ) == getRegSizeInBits ( * RC ) ) return Super ; break ; case X86 :: VR128XRegClassID : case X86 :: VR256XRegClassID : if ( Subtarget . hasVLX ( ) && getRegSizeInBits ( * Super ) == getRegSizeInBits ( * RC ) ) return Super ; break ; case X86 :: FR32XRegClassID : case X86 :: FR64XRegClassID : if ( Subtarget . hasAVX512 ( ) && getRegSizeInBits ( * Super ) == getRegSizeInBits ( * RC ) ) return Super ; break ; case X86 :: GR8RegClassID : case X86 :: GR16RegClassID : case X86 :: GR32RegClassID : case X86 :: GR64RegClassID : case X86 :: RFP32RegClassID : case X86 :: RFP64RegClassID : case X86 :: RFP80RegClassID : case X86 :: VR512_0_15RegClassID : case X86 :: VR512RegClassID : if ( getRegSizeInBits ( * Super ) == getRegSizeInBits ( * RC ) ) return Super ; } Super = * I ++ ; } while ( Super ) ; return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .


"  Preloading operand for insn %d into r%d\n"

Convert operand OP in INSN . We should handle memory operands and uninitialized registers . All other register uses are converted during registers conversion .


<s> int emit_cbcond_nop ( rtx insn ) { rtx next = next_active_insn ( insn ) ; if ( ! next ) return 1 ; if ( NONJUMP_INSN_P ( next ) && GET_CODE ( PATTERN ( next ) ) == SEQUENCE ) next = XVECEXP ( PATTERN ( next ) , 0 , 0 ) ; else if ( CALL_P ( next ) && GET_CODE ( PATTERN ( next ) ) == PARALLEL ) { rtx delay = XVECEXP ( PATTERN ( next ) , 0 , 1 ) ; if ( GET_CODE ( delay ) == RETURN ) { if ( sparc_leaf_function_p || TARGET_FLAT ) return 0 ; } } if ( NONJUMP_INSN_P ( next ) ) return 0 ; return 1 ; } </s>

Return nonzero if we should emit a nop after a cbcond instruction . The cbcond instruction does not have a delay slot , however there is a severe performance penalty if a control transfer appears right after a cbcond . Therefore we emit a nop when we detect this situation .


<s>
unsigned
MipsSEInstrInfo
::
getOppositeBranchOpc
(
unsigned
Opc
)
const
{
switch
(
Opc
)
{
default
:
llvm_unreachable
(
"Illegal opcode!"
)
;
case
Mips
::
BEQ
:
return
Mips
::
BNE
;
case
Mips
::
BNE
:
return
Mips
::
BEQ
;
case
Mips
::
BGTZ
:
return
Mips
::
BLEZ
;
case
Mips
::
BGEZ
:
return
Mips
::
BLTZ
;
case
Mips
::
BLTZ
:
return
Mips
::
BGEZ
;
case
Mips
::
BLEZ
:
return
Mips
::
BGTZ
;
case
Mips
::
BEQ64
:
return
Mips
::
BNE64
;
case
Mips
::
BNE64
:
return
Mips
::
BEQ64
;
case
Mips
::
BGTZ64
:
return
Mips
::
BLEZ64
;
case
Mips
::
BGEZ64
:
return
Mips
::
BLTZ64
;
case
Mips
::
BLTZ64
:
return
Mips
::
BGEZ64
;
case
Mips
::
BLEZ64
:
return
Mips
::
BGTZ64
;
case
Mips
::
BC1T
:
return
Mips
::
BC1F
;
case
Mips
::
BC1F
:
return
Mips
::
BC1T
;
case
Mips
::
BEQZC_MM
:
return
Mips
::
BNEZC_MM
;
case
Mips
::
BNEZC_MM
:
return
Mips
::
BEQZC_MM
;
}
}
</s>

getOppositeBranchOpc - Return the inverse of the specified opcode , e.g .


"getJumpTargetOpValue expects only expressions or an immediate"

getJumpTargetOpValue - Return binary encoding of the jump target operand .


<s> bool isMem ( ) const override { return Kind == k_Memory ; } </s>


<s> std :: pair < const TargetRegisterClass * , uint8_t > ARMTargetLowering :: findRepresentativeClass ( const TargetRegisterInfo * TRI , MVT VT ) const { const TargetRegisterClass * RRC = nullptr ; uint8_t Cost = 1 ; switch ( VT . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( TRI , VT ) ; case MVT :: f32 : case MVT :: f64 : case MVT :: v8i8 : case MVT :: v4i16 : case MVT :: v2i32 : case MVT :: v1i64 : case MVT :: v2f32 : RRC = & ARM :: DPRRegClass ; if ( Subtarget -> useNEONForSinglePrecisionFP ( ) ) Cost = 2 ; break ; case MVT :: v16i8 : case MVT :: v8i16 : case MVT :: v4i32 : case MVT :: v2i64 : case MVT :: v4f32 : case MVT :: v2f64 : RRC = & ARM :: DPRRegClass ; Cost = 2 ; break ; case MVT :: v4i64 : RRC = & ARM :: DPRRegClass ; Cost = 4 ; break ; case MVT :: v8i64 : RRC = & ARM :: DPRRegClass ; Cost = 8 ; break ; } return std :: make_pair ( RRC , Cost ) ; } </s>

Return the largest legal super-reg register class of the register class for the specified type and its associated `` cost '' .


<s> unsigned OR1KMachineFunctionInfo :: getGlobalBaseReg ( ) { if ( GlobalBaseReg ) return GlobalBaseReg ; return GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( & OR1K :: GPRRegClass ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static rtx_insn * thumb1_emit_multi_reg_push ( unsigned long mask , unsigned long real_regs ) { unsigned long regno ; rtx par [ 10 ] , tmp , reg ; rtx_insn * insn ; int i , j ; for ( i = 0 ; mask ; ++ i , mask &= mask - 1 ) { regno = ctz_hwi ( mask ) ; reg = gen_rtx_REG ( SImode , regno ) ; if ( i == 0 ) tmp = gen_rtx_UNSPEC ( BLKmode , gen_rtvec ( 1 , reg ) , UNSPEC_PUSH_MULT ) ; else tmp = gen_rtx_USE ( VOIDmode , reg ) ; par [ i ] = tmp ; } tmp = plus_constant ( Pmode , stack_pointer_rtx , - 4 * i ) ; tmp = gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , tmp ) ; tmp = gen_frame_mem ( BLKmode , tmp ) ; tmp = gen_rtx_SET ( tmp , par [ 0 ] ) ; par [ 0 ] = tmp ; tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( i , par ) ) ; insn = emit_insn ( tmp ) ; tmp = plus_constant ( Pmode , stack_pointer_rtx , - 4 * i ) ; tmp = gen_rtx_SET ( stack_pointer_rtx , tmp ) ; par [ 0 ] = tmp ; for ( j = 0 ; real_regs ; ++ j , real_regs &= real_regs - 1 ) { regno = ctz_hwi ( real_regs ) ; reg = gen_rtx_REG ( SImode , regno ) ; tmp = plus_constant ( Pmode , stack_pointer_rtx , j * 4 ) ; tmp = gen_frame_mem ( SImode , tmp ) ; tmp = gen_rtx_SET ( tmp , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; par [ j + 1 ] = tmp ; } if ( j == 0 ) tmp = par [ 0 ] ; else { RTX_FRAME_RELATED_P ( par [ 0 ] ) = 1 ; tmp = gen_rtx_SEQUENCE ( VOIDmode , gen_rtvec_v ( j + 1 , par ) ) ; } add_reg_note ( insn , REG_FRAME_RELATED_EXPR , tmp ) ; return insn ; } </s>

Like emit_multi_reg_push , but allowing for a different set of registers to be described as saved . MASK is the set of registers to be saved ; REAL_REGS is the set of registers to be described as saved . If REAL_REGS is 0 , only describe the stack adjustment .


<s> static rtx create_temp_reg_if_possible ( machine_mode mode , rtx default_reg ) { return can_create_pseudo_p ( ) ? gen_reg_rtx ( mode ) : default_reg ; } </s>

Create a temporary variable to hold a partial result , to enable CSE .


<s> void LanaiFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const LanaiRegisterInfo * LRI = static_cast < const LanaiRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; int Offset = - 4 ; MFI -> CreateFixedObject ( 4 , Offset , true ) ; Offset -= 4 ; MFI -> CreateFixedObject ( 4 , Offset , true ) ; Offset -= 4 ; if ( LRI -> hasBasePointer ( MF ) ) { MFI -> CreateFixedObject ( 4 , Offset , true ) ; SavedRegs . reset ( LRI -> getBaseRegister ( ) ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> const M68kSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static rtx function_arg_union_value ( int size , machine_mode mode , int slotno , int regno ) { int nwords = ROUND_ADVANCE ( size ) , i ; rtx regs ; if ( nwords == 0 ) return gen_rtx_REG ( mode , regno ) ; if ( slotno == SPARC_INT_ARG_MAX - 1 ) nwords = 1 ; regs = gen_rtx_PARALLEL ( mode , rtvec_alloc ( nwords ) ) ; for ( i = 0 ; i < nwords ; i ++ ) { XVECEXP ( regs , 0 , i ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( word_mode , regno ) , GEN_INT ( UNITS_PER_WORD * i ) ) ; regno ++ ; } return regs ; } </s>

Used by function_arg and sparc_function_value_1 to implement the conventions of the 64-bit ABI for passing and returning unions . Return an expression valid as a return value for the FUNCTION_ARG and TARGET_FUNCTION_VALUE . SIZE is the size in bytes of the union . MODE is the argument 's machine mode . REGNO is the hard register the union will be passed in .


<s>
static
void
macho_branch_islands
(
void
)
{
char
tmp_buf
[
512
]
;
while
(
!
vec_safe_is_empty
(
branch_islands
)
)
{
branch_island
*
bi
=
&
branch_islands
->
last
(
)
;
const
char
*
label
=
IDENTIFIER_POINTER
(
bi
->
label_name
)
;
const
char
*
name
=
IDENTIFIER_POINTER
(
bi
->
function_name
)
;
char
name_buf
[
512
]
;
if
(
name
[
0
]
==
'*'
||
name
[
0
]
==
'&'
)
strcpy
(
name_buf
,
name
+
1
)
;
else
{
name_buf
[
0
]
=
'_'
;
strcpy
(
name_buf
+
1
,
name
)
;
}
strcpy
(
tmp_buf
,
"\n"
)
;
strcat
(
tmp_buf
,
label
)
;
if
(
write_symbols
==
DBX_DEBUG
||
write_symbols
==
XCOFF_DEBUG
)
dbxout_stabd
(
N_SLINE
,
bi
->
line_number
)
;
if
(
flag_pic
)
{
if
(
TARGET_LINK_STACK
)
{
char
name
[
32
]
;
get_ppc476_thunk_name
(
name
)
;
strcat
(
tmp_buf
,
":\n\tmflr r0\n\tbl "
)
;
strcat
(
tmp_buf
,
name
)
;
strcat
(
tmp_buf
,
"\n"
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic:\n\tmflr r11\n"
)
;
}
else
{
strcat
(
tmp_buf
,
":\n\tmflr r0\n\tbcl 20,31,"
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic\n"
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic:\n\tmflr r11\n"
)
;
}
strcat
(
tmp_buf
,
"\taddis r11,r11,ha16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
" - "
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic)\n"
)
;
strcat
(
tmp_buf
,
"\tmtlr r0\n"
)
;
strcat
(
tmp_buf
,
"\taddi r12,r11,lo16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
" - "
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic)\n"
)
;
strcat
(
tmp_buf
,
"\tmtctr r12\n\tbctr\n"
)
;
}
else
{
strcat
(
tmp_buf
,
":\nlis r12,hi16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
")\n\tori r12,r12,lo16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
")\n\tmtctr r12\n\tbctr"
)
;
}
output_asm_insn
(
tmp_buf
,
0
)
;
if
(
write_symbols
==
DBX_DEBUG
||
write_symbols
==
XCOFF_DEBUG
)
dbxout_stabd
(
N_SLINE
,
bi
->
line_number
)
;
branch_islands
->
pop
(
)
;
}
}
</s>

Generate far-jump branch islands for everything on the branch_island_list . Invoked immediately after the last instruction of the epilogue has been emitted ; the branch-islands must be appended to , and contiguous with , the function body . Mach-O stubs are generated in machopic_output_stub ( ) .


<s>
static
tree
h8300_handle_tiny_data_attribute
(
tree
*
node
,
tree
name
,
tree
args
ATTRIBUTE_UNUSED
,
int
flags
ATTRIBUTE_UNUSED
,
bool
*
no_add_attrs
)
{
tree
decl
=
*
node
;
if
(
TREE_STATIC
(
decl
)
||
DECL_EXTERNAL
(
decl
)
)
{
set_decl_section_name
(
decl
,
".tiny"
)
;
}
else
{
warning
(
OPT_Wattributes
,
"%qE attribute ignored"
,
name
)
;
*
no_add_attrs
=
true
;
}
return
NULL_TREE
;
}
</s>

Handle an `` tiny_data '' attribute ; arguments as in struct attribute_spec.handler .


<s> void build ( function_builder & b , const function_group_info & group ) const OVERRIDE { b . add_overloaded_functions ( group , MODE_none ) ; build_all ( b , "v0,vu0" , group , MODE_none ) ; } </s>

Build new chain starting from insn INSN_UID recursively adding all dependent uses and definitions . Return true if OK , false if the chain discovery was aborted .


<s>
void
AVRInstPrinter
::
printPCRelImm
(
const
MCInst
*
MI
,
unsigned
OpNo
,
raw_ostream
&
O
)
{
const
MCOperand
&
Op
=
MI
->
getOperand
(
OpNo
)
;
if
(
Op
.
isImm
(
)
)
{
int64_t
Imm
=
Op
.
getImm
(
)
;
O
<<
'.'
;
if
(
Imm
>=
0
)
O
<<
'+'
;
O
<<
Imm
;
}
else
{
assert
(
Op
.
isExpr
(
)
&&
"Unknown pcrel immediate operand"
)
;
O
<<
*
Op
.
getExpr
(
)
;
}
}
</s>

AVR
AVR
0
"Unknown pcrel immediate operand"


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , RM , CM ) , Subtarget ( TT , CPU , FS , is64bit ) , DataLayout ( Subtarget . getDataLayout ( ) ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrInfo ( Subtarget ) , FrameLowering ( Subtarget ) { } </s>


<s>
void
ARMAsmPrinter
::
emitMachineConstantPoolValue
(
MachineConstantPoolValue
*
MCPV
)
{
const
DataLayout
&
DL
=
getDataLayout
(
)
;
int
Size
=
DL
.
getTypeAllocSize
(
MCPV
->
getType
(
)
)
;
ARMConstantPoolValue
*
ACPV
=
static_cast
<
ARMConstantPoolValue
*
>
(
MCPV
)
;
if
(
ACPV
->
isPromotedGlobal
(
)
)
{
auto
*
ACPC
=
cast
<
ARMConstantPoolConstant
>
(
ACPV
)
;
for
(
const
auto
*
GV
:
ACPC
->
promotedGlobals
(
)
)
{
if
(
!
EmittedPromotedGlobalLabels
.
count
(
GV
)
)
{
MCSymbol
*
GVSym
=
getSymbol
(
GV
)
;
OutStreamer
->
emitLabel
(
GVSym
)
;
EmittedPromotedGlobalLabels
.
insert
(
GV
)
;
}
}
return
emitGlobalConstant
(
DL
,
ACPC
->
getPromotedGlobalInit
(
)
)
;
}
MCSymbol
*
MCSym
;
if
(
ACPV
->
isLSDA
(
)
)
{
MCSym
=
getCurExceptionSym
(
)
;
}
else
if
(
ACPV
->
isBlockAddress
(
)
)
{
const
BlockAddress
*
BA
=
cast
<
ARMConstantPoolConstant
>
(
ACPV
)
->
getBlockAddress
(
)
;
MCSym
=
GetBlockAddressSymbol
(
BA
)
;
}
else
if
(
ACPV
->
isGlobalValue
(
)
)
{
const
GlobalValue
*
GV
=
cast
<
ARMConstantPoolConstant
>
(
ACPV
)
->
getGV
(
)
;
unsigned
char
TF
=
Subtarget
->
isTargetMachO
(
)
ARMII
::
MO_NONLAZY
:
0
;
MCSym
=
GetARMGVSymbol
(
GV
,
TF
)
;
}
else
if
(
ACPV
->
isMachineBasicBlock
(
)
)
{
const
MachineBasicBlock
*
MBB
=
cast
<
ARMConstantPoolMBB
>
(
ACPV
)
->
getMBB
(
)
;
MCSym
=
MBB
->
getSymbol
(
)
;
}
else
{
assert
(
ACPV
->
isExtSymbol
(
)
&&
"unrecognized constant pool value"
)
;
auto
Sym
=
cast
<
ARMConstantPoolSymbol
>
(
ACPV
)
->
getSymbol
(
)
;
MCSym
=
GetExternalSymbolSymbol
(
Sym
)
;
}
const
MCExpr
*
Expr
=
MCSymbolRefExpr
::
create
(
MCSym
,
getModifierVariantKind
(
ACPV
->
getModifier
(
)
)
,
OutContext
)
;
if
(
ACPV
->
getPCAdjustment
(
)
)
{
MCSymbol
*
PCLabel
=
getPICLabel
(
DL
.
getPrivateGlobalPrefix
(
)
,
getFunctionNumber
(
)
,
ACPV
->
getLabelId
(
)
,
OutContext
)
;
const
MCExpr
*
PCRelExpr
=
MCSymbolRefExpr
::
create
(
PCLabel
,
OutContext
)
;
PCRelExpr
=
MCBinaryExpr
::
createAdd
(
PCRelExpr
,
MCConstantExpr
::
create
(
ACPV
->
getPCAdjustment
(
)
,
OutContext
)
,
OutContext
)
;
if
(
ACPV
->
mustAddCurrentAddress
(
)
)
{
MCSymbol
*
DotSym
=
OutContext
.
createTempSymbol
(
)
;
OutStreamer
->
emitLabel
(
DotSym
)
;
const
MCExpr
*
DotExpr
=
MCSymbolRefExpr
::
create
(
DotSym
,
OutContext
)
;
PCRelExpr
=
MCBinaryExpr
::
createSub
(
PCRelExpr
,
DotExpr
,
OutContext
)
;
}
Expr
=
MCBinaryExpr
::
createSub
(
Expr
,
PCRelExpr
,
OutContext
)
;
}
OutStreamer
->
emitValue
(
Expr
,
Size
)
;
}
</s>

EmitMachineConstantPoolValue - Print a machine constantpool value to the .s file .

ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARMII::MO_NONLAZY
0
ARM
ARM
"unrecognized constant pool value"
ARM


<s> const char * mips_msa_output_division ( const char * division , rtx * operands ) { const char * s ; s = division ; if ( TARGET_CHECK_ZERO_DIV ) { output_asm_insn ( "%(bnz.%v0\t%w2,1f" , operands ) ; output_asm_insn ( s , operands ) ; s = "break\t7%)\n1:" ; } return s ; } </s>

Return the assembly code for MSA DIV_ { S , U } .DF or MOD_ { S , U } .DF instructions , which has the operands given by OPERANDS . Add in a divide-by-zero check if needed .


<s> virtual bool enableMachineScheduler ( ) const { return true ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


<s> static int n_regs_saved_by_prologue ( void ) { e_funkind fkind = funkind ( TREE_TYPE ( current_function_decl ) ) ; bool is_inthandler = fkind != SUBROUTINE ; tree attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ; bool all = ( lookup_attribute ( "saveall" , attrs ) != NULL_TREE || ( is_inthandler && ! crtl -> is_leaf ) ) ; int ndregs = all ? 8 : n_dregs_to_save ( is_inthandler , false ) ; int npregs = all ? 6 : n_pregs_to_save ( is_inthandler , false ) ; int n = ndregs + npregs ; int i ; if ( all || stack_frame_needed_p ( ) ) n += 2 ; else { if ( must_save_fp_p ( ) ) n ++ ; if ( must_save_rets_p ( ) ) n ++ ; } if ( fkind != SUBROUTINE || all ) { n ++ ; if ( ! crtl -> is_leaf || cfun -> machine -> has_hardware_loops || cfun -> machine -> has_loopreg_clobber ) { n += 6 ; } } if ( fkind != SUBROUTINE ) { if ( lookup_attribute ( "nesting" , attrs ) ) n ++ ; } for ( i = REG_P7 + 1 ; i < REG_CC ; i ++ ) if ( all || ( fkind != SUBROUTINE && ( df_regs_ever_live_p ( i ) || ( ! leaf_function_p ( ) && call_used_or_fixed_reg_p ( i ) ) ) ) ) n += i == REG_A0 || i == REG_A1 ? 2 : 1 ; return n ; } </s>

Return the number of registers pushed during the prologue .


<s> int frv_emit_cond_branch ( rtx operands [ ] ) { rtx test_rtx ; rtx label_ref ; rtx if_else ; enum rtx_code test = GET_CODE ( operands [ 0 ] ) ; rtx cc_reg = frv_emit_comparison ( test , operands [ 1 ] , operands [ 2 ] ) ; machine_mode cc_mode = GET_MODE ( cc_reg ) ; label_ref = gen_rtx_LABEL_REF ( VOIDmode , operands [ 3 ] ) ; test_rtx = gen_rtx_fmt_ee ( test , cc_mode , cc_reg , const0_rtx ) ; if_else = gen_rtx_IF_THEN_ELSE ( cc_mode , test_rtx , label_ref , pc_rtx ) ; emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , if_else ) ) ; return TRUE ; } </s>

Emit code for a conditional branch . The comparison operands were previously stored in frv_compare_op0 and frv_compare_op1 . XXX : I originally wanted to add a clobber of a CCR register to use in conditional execution , but that confuses the rest of the compiler .


<s> bool PPCTTIImpl :: canSaveCmp ( Loop * L , BranchInst * * BI , ScalarEvolution * SE , LoopInfo * LI , DominatorTree * DT , AssumptionCache * AC , TargetLibraryInfo * LibInfo ) { for ( Loop * I : * L ) if ( canSaveCmp ( I , BI , SE , LI , DT , AC , LibInfo ) ) return false ; HardwareLoopInfo HWLoopInfo ( L ) ; if ( ! HWLoopInfo . canAnalyze ( * LI ) ) return false ; if ( ! isHardwareLoopProfitable ( L , * SE , * AC , LibInfo , HWLoopInfo ) ) return false ; if ( ! HWLoopInfo . isHardwareLoopCandidate ( * SE , * LI , * DT ) ) return false ; * BI = HWLoopInfo . ExitBranch ; return true ; } </s>

Return true if the target can save a compare for loop count , for example hardware loop saves a compare .


<s> bool RISCVDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { switch ( ConstraintID ) { case InlineAsm :: Constraint_m : OutOps . push_back ( Op ) ; return false ; case InlineAsm :: Constraint_A : OutOps . push_back ( Op ) ; return false ; default : break ; } return true ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> MCLOHType getKind ( ) const { return Kind ; } </s>


<s> static rtx m68hc11_struct_value_rtx ( tree fntype ATTRIBUTE_UNUSED , int incoming ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( Pmode , HARD_D_REGNUM ) ; } </s>

Worker function for TARGET_STRUCT_VALUE_RTX .


<s> unsigned getMachineCSELookAheadLimit ( ) const override { return 500 ; } </s>

Return the value to use for the MachineCSE 's LookAheadLimit , which is a heuristic used for CSE'ing phys reg defs .


<s> unsigned TeeRISCInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { assert ( 0 ) ; if ( MI -> getOpcode ( ) == TeeRISC :: LD ) { if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> static void pru_reorg ( void ) { rtx_insn * insns = get_insns ( ) ; compute_bb_for_insn ( ) ; df_analyze ( ) ; shorten_branches ( get_insns ( ) ) ; pru_reorg_loop ( insns ) ; df_finish_pass ( false ) ; } </s>


"rs6000_builtin_md_vectorized_function (%s, %s, %s)\n"


<s> void LanaiAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( static_cast < unsigned > ( Kind ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize = 4 ; uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; CurVal |= static_cast < uint64_t > ( static_cast < uint8_t > ( Data [ Offset + Idx ] ) ) << ( i * 8 ) ; } uint64_t Mask = ( static_cast < uint64_t > ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = static_cast < uint8_t > ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> int RISCVFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const auto * RVFI = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; const auto & CSI = getNonLibcallCSI ( MFI . getCalleeSavedInfo ( ) ) ; int MinCSFI = 0 ; int MaxCSFI = - 1 ; int Offset = MFI . getObjectOffset ( FI ) - getOffsetOfLocalArea ( ) + MFI . getOffsetAdjustment ( ) ; uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( CSI . size ( ) ) { MinCSFI = CSI [ 0 ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - 1 ] . getFrameIdx ( ) ; } if ( FI >= MinCSFI && FI <= MaxCSFI ) { FrameReg = RISCV :: X2 ; if ( FirstSPAdjustAmount ) Offset += FirstSPAdjustAmount ; else Offset += MFI . getStackSize ( ) ; } else if ( RI -> needsStackRealignment ( MF ) && ! MFI . isFixedObjectIndex ( FI ) ) { if ( hasBP ( MF ) ) FrameReg = RISCVABI :: getBPReg ( ) ; else FrameReg = RISCV :: X2 ; Offset += MFI . getStackSize ( ) ; if ( FI < 0 ) Offset += RVFI -> getLibCallStackSize ( ) ; } else { FrameReg = RI -> getFrameRegister ( MF ) ; if ( hasFP ( MF ) ) { Offset += RVFI -> getVarArgsSaveSize ( ) ; if ( FI >= 0 ) Offset -= RVFI -> getLibCallStackSize ( ) ; } else { Offset += MFI . getStackSize ( ) ; if ( FI < 0 ) Offset += RVFI -> getLibCallStackSize ( ) ; } } return Offset ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s>
static
uint16_t
name
(
struct
InternalInstruction
*
insn
,
\
OperandType
type
,
\
uint8_t
index
,
\
uint8_t
*
valid
)
{
\
*
valid
=
1
;
\
switch
(
type
)
{
\
default
:
\
debug
(
"Unhandled register type"
)
;
\
*
valid
=
0
;
\
return
0
;
\
case
TYPE_Rv
:
\
return
base
+
index
;
\
case
TYPE_R8
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
if
(
insn
->
rexPrefix
&&
\
index
>=
4
&&
index
<=
7
)
{
\
return
prefix
##
_SPL
+
(
index
4
)
;
\
}
else
{
\
return
prefix
##
_AL
+
index
;
\
}
\
case
TYPE_R16
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
return
prefix
##
_AX
+
index
;
\
case
TYPE_R32
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
return
prefix
##
_EAX
+
index
;
\
case
TYPE_R64
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
return
prefix
##
_RAX
+
index
;
\
case
TYPE_ZMM
:
\
return
prefix
##
_ZMM0
+
index
;
\
case
TYPE_YMM
:
\
return
prefix
##
_YMM0
+
index
;
\
case
TYPE_XMM
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_VK
:
\
index
&=
0xf
;
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_K0
+
index
;
\
case
TYPE_MM64
:
\
return
prefix
##
_MM0
+
(
index
&
0x7
)
;
\
case
TYPE_SEGMENTREG
:
\
if
(
(
index
&
7
)
>
5
)
\
*
valid
=
0
;
\
return
prefix
##
_ES
+
(
index
&
7
)
;
\
case
TYPE_DEBUGREG
:
\
return
prefix
##
_DR0
+
index
;
\
case
TYPE_CONTROLREG
:
\
return
prefix
##
_CR0
+
index
;
\
case
TYPE_BNDR
:
\
if
(
index
>
3
)
\
*
valid
=
0
;
\
return
prefix
##
_BND0
+
index
;
\
case
TYPE_MVSIBX
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_MVSIBY
:
\
return
prefix
##
_YMM0
+
index
;
\
case
TYPE_MVSIBZ
:
\
return
prefix
##
_ZMM0
+
index
;
\
}
\
}
</s>

Gets the name of the pass we are mixed into .


<s> unsigned getNumFixupKinds ( ) const { return Z80 :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> static bool expand_vselect_vconcat ( rtx target , rtx op0 , rtx op1 , const unsigned char * perm , unsigned nelt , bool testing_p ) { machine_mode v2mode ; rtx x ; bool ok ; if ( vselect_insn == NULL_RTX ) init_vselect_insn ( ) ; if ( ! GET_MODE_2XWIDER_MODE ( GET_MODE ( op0 ) ) . exists ( & v2mode ) ) return false ; x = XEXP ( SET_SRC ( PATTERN ( vselect_insn ) ) , 0 ) ; PUT_MODE ( x , v2mode ) ; XEXP ( x , 0 ) = op0 ; XEXP ( x , 1 ) = op1 ; ok = expand_vselect ( target , x , perm , nelt , testing_p ) ; XEXP ( x , 0 ) = const0_rtx ; XEXP ( x , 1 ) = const0_rtx ; return ok ; } </s>

Similar , but generate a vec_concat from op0 and op1 as well .


<s> static rtx ix86_validate_address_register ( rtx op ) { machine_mode mode = GET_MODE ( op ) ; if ( mode != SImode && mode != DImode ) return NULL_RTX ; if ( REG_P ( op ) ) return op ; else if ( GET_CODE ( op ) == SUBREG ) { rtx reg = SUBREG_REG ( op ) ; if ( ! REG_P ( reg ) ) return NULL_RTX ; mode = GET_MODE ( reg ) ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) return NULL_RTX ; if ( register_no_elim_operand ( reg , mode ) ) return reg ; } return NULL_RTX ; } </s>

Determine if op is suitable RTX for an address register . Return naked register if a register or a register subreg is found , otherwise return NULL_RTX .


<s>
void
AArch64RegisterInfo
::
getOffsetOpcodes
(
const
StackOffset
&
Offset
,
SmallVectorImpl
<
uint64_t
>
&
Ops
)
const
{
assert
(
Offset
.
getScalable
(
)
%
2
==
0
&&
"Invalid frame offset"
)
;
DIExpression
::
appendOffset
(
Ops
,
Offset
.
getFixed
(
)
)
;
unsigned
VG
=
getDwarfRegNum
(
AArch64
::
VG
,
true
)
;
int64_t
VGSized
=
Offset
.
getScalable
(
)
/
2
;
if
(
VGSized
>
0
)
{
Ops
.
push_back
(
dwarf
::
DW_OP_constu
)
;
Ops
.
push_back
(
VGSized
)
;
Ops
.
append
(
{
dwarf
::
DW_OP_bregx
,
VG
,
0ULL
}
)
;
Ops
.
push_back
(
dwarf
::
DW_OP_mul
)
;
Ops
.
push_back
(
dwarf
::
DW_OP_plus
)
;
}
else
if
(
VGSized
<
0
)
{
Ops
.
push_back
(
dwarf
::
DW_OP_constu
)
;
Ops
.
push_back
(
VGSized
)
;
Ops
.
append
(
{
dwarf
::
DW_OP_bregx
,
VG
,
0ULL
}
)
;
Ops
.
push_back
(
dwarf
::
DW_OP_mul
)
;
Ops
.
push_back
(
dwarf
::
DW_OP_minus
)
;
}
}
</s>

Gets the DWARF expression opcodes for Offset .


<s> bool MipsTargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ; if ( Kind . isMergeable1ByteCString ( ) ) return false ; const Type * Ty = GV -> getType ( ) -> getElementType ( ) ; return IsInSmallSection ( TM . getTargetData ( ) -> getTypeAllocSize ( Ty ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> bool PPCTTIImpl :: getTgtMemIntrinsic ( IntrinsicInst * Inst , MemIntrinsicInfo & Info ) { switch ( Inst -> getIntrinsicID ( ) ) { case Intrinsic :: ppc_altivec_lvx : case Intrinsic :: ppc_altivec_lvxl : case Intrinsic :: ppc_altivec_lvebx : case Intrinsic :: ppc_altivec_lvehx : case Intrinsic :: ppc_altivec_lvewx : case Intrinsic :: ppc_vsx_lxvd2x : case Intrinsic :: ppc_vsx_lxvw4x : case Intrinsic :: ppc_vsx_lxvd2x_be : case Intrinsic :: ppc_vsx_lxvw4x_be : case Intrinsic :: ppc_vsx_lxvl : case Intrinsic :: ppc_vsx_lxvll : case Intrinsic :: ppc_vsx_lxvp : { Info . PtrVal = Inst -> getArgOperand ( 0 ) ; Info . ReadMem = true ; Info . WriteMem = false ; return true ; } case Intrinsic :: ppc_altivec_stvx : case Intrinsic :: ppc_altivec_stvxl : case Intrinsic :: ppc_altivec_stvebx : case Intrinsic :: ppc_altivec_stvehx : case Intrinsic :: ppc_altivec_stvewx : case Intrinsic :: ppc_vsx_stxvd2x : case Intrinsic :: ppc_vsx_stxvw4x : case Intrinsic :: ppc_vsx_stxvd2x_be : case Intrinsic :: ppc_vsx_stxvw4x_be : case Intrinsic :: ppc_vsx_stxvl : case Intrinsic :: ppc_vsx_stxvll : case Intrinsic :: ppc_vsx_stxvp : { Info . PtrVal = Inst -> getArgOperand ( 1 ) ; Info . ReadMem = false ; Info . WriteMem = true ; return true ; } default : break ; } return false ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> StringRef getPassName ( ) const override { return FIXUPBW_DESC ; } </s>

getPassName - Return a nice clean name for a pass .


<s> BitVector R600RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const R600MachineFunctionInfo * MFI = MF . getInfo < R600MachineFunctionInfo > ( ) ; Reserved . set ( AMDGPU :: ZERO ) ; Reserved . set ( AMDGPU :: HALF ) ; Reserved . set ( AMDGPU :: ONE ) ; Reserved . set ( AMDGPU :: ONE_INT ) ; Reserved . set ( AMDGPU :: NEG_HALF ) ; Reserved . set ( AMDGPU :: NEG_ONE ) ; Reserved . set ( AMDGPU :: PV_X ) ; Reserved . set ( AMDGPU :: ALU_LITERAL_X ) ; Reserved . set ( AMDGPU :: PREDICATE_BIT ) ; Reserved . set ( AMDGPU :: PRED_SEL_OFF ) ; Reserved . set ( AMDGPU :: PRED_SEL_ZERO ) ; Reserved . set ( AMDGPU :: PRED_SEL_ONE ) ; for ( TargetRegisterClass :: iterator I = AMDGPU :: R600_CReg32RegClass . begin ( ) , E = AMDGPU :: R600_CReg32RegClass . end ( ) ; I != E ; ++ I ) { Reserved . set ( * I ) ; } for ( std :: vector < unsigned > :: const_iterator I = MFI -> ReservedRegs . begin ( ) , E = MFI -> ReservedRegs . end ( ) ; I != E ; ++ I ) { Reserved . set ( * I ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
void
RISCVMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
unsigned
Size
=
Desc
.
getSize
(
)
;
switch
(
Size
)
{
default
:
llvm_unreachable
(
"Unhandled encodeInstruction length!"
)
;
case
2
:
{
uint16_t
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
support
::
endian
::
Writer
<
support
::
little
>
(
OS
)
.
write
<
uint16_t
>
(
Bits
)
;
break
;
}
case
4
:
{
uint32_t
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
support
::
endian
::
Writer
<
support
::
little
>
(
OS
)
.
write
(
Bits
)
;
break
;
}
}
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .

RISCV
RISCV
"Unhandled encodeInstruction length!"
2
support::endian
support::little
4
support::endian
support::little


"invalid argument to built-in function %s"


<s> bool PatmosFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( MF . getFunction ( ) -> hasFnAttribute ( Attribute :: Naked ) ) return false ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> const DataLayout * getDataLayout ( ) const override { return getSubtargetImpl ( ) -> getDataLayout ( ) ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetOptions & Options ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , ARMProcClass ( None ) , stackAlignment ( 4 ) , CPUString ( CPU ) , TargetTriple ( TT ) , Options ( Options ) , TargetABI ( ARM_ABI_UNKNOWN ) { initializeEnvironment ( ) ; resetSubtargetFeatures ( CPU , FS ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


Hook to validate the current # pragma GCC target and set the state , and update the macros based on what was changed . If ARGS is NULL , then POP_TARGET is used to reset the options .


<s>
SDValue
CSKYTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
CSKYLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
CSKYLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
CCAssignFnForReturn
(
CallConv
,
IsVarArg
)
)
;
SDValue
Glue
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
CSKYLocs
.
size
(
)
;
i
<
e
;
++
i
)
{
SDValue
Val
=
OutVals
[
i
]
;
CCValAssign
&
VA
=
CSKYLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
bool
IsF64OnCSKY
=
VA
.
getLocVT
(
)
==
MVT
::
i32
&&
VA
.
getValVT
(
)
==
MVT
::
f64
;
if
(
IsF64OnCSKY
)
{
assert
(
VA
.
isRegLoc
(
)
&&
"Expected return via registers"
)
;
SDValue
Split64
=
DAG
.
getNode
(
CSKYISD
::
BITCAST_TO_LOHI
,
DL
,
DAG
.
getVTList
(
MVT
::
i32
,
MVT
::
i32
)
,
Val
)
;
SDValue
Lo
=
Split64
.
getValue
(
0
)
;
SDValue
Hi
=
Split64
.
getValue
(
1
)
;
Register
RegLo
=
VA
.
getLocReg
(
)
;
assert
(
RegLo
<
CSKY
::
R31
&&
"Invalid register pair"
)
;
Register
RegHi
=
RegLo
+
1
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
RegLo
,
Lo
,
Glue
)
;
Glue
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
RegLo
,
MVT
::
i32
)
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
RegHi
,
Hi
,
Glue
)
;
Glue
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
RegHi
,
MVT
::
i32
)
)
;
}
else
{
Val
=
convertValVTToLocVT
(
DAG
,
Val
,
VA
,
DL
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
Val
,
Glue
)
;
Glue
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
}
RetOps
[
0
]
=
Chain
;
if
(
Glue
.
getNode
(
)
)
{
RetOps
.
push_back
(
Glue
)
;
}
if
(
DAG
.
getMachineFunction
(
)
.
getFunction
(
)
.
hasFnAttribute
(
"interrupt"
)
)
return
DAG
.
getNode
(
CSKYISD
::
NIR
,
DL
,
MVT
::
Other
,
RetOps
)
;
return
DAG
.
getNode
(
CSKYISD
::
RET
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> unsigned ARMFastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return ARMMaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return ARMMaterializeGV ( GV , VT ) ; else if ( isa < ConstantInt > ( C ) ) return ARMMaterializeInt ( C , VT ) ; return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s> void addUse ( long pos ) { uses . set ( pos ) ; } </s>


<s> void RV16KFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const RV16KRegisterInfo * RI = STI . getRegisterInfo ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; uint64_t StackAlign = RI -> needsStackRealignment ( MF ) ? MFI . getMaxAlignment ( ) : getStackAlignment ( ) ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI . setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s> bool shouldTrackPressure ( ) const override { return false ; } </s>

PostRA scheduling does not track pressure .


<s> bool AArch64TargetLowering :: isShuffleMaskLegal ( ArrayRef < int > M , EVT VT ) const { if ( useSVEForFixedLengthVectorVT ( VT ) ) return false ; if ( VT . getVectorNumElements ( ) == 4 && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ 4 ] ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { if ( M [ i ] < 0 ) PFIndexes [ i ] = 8 ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ 0 ] * 9 * 9 * 9 + PFIndexes [ 1 ] * 9 * 9 + PFIndexes [ 2 ] * 9 + PFIndexes [ 3 ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> 30 ) ; if ( Cost <= 4 ) return true ; } bool DummyBool ; int DummyInt ; unsigned DummyUnsigned ; return ( ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isREVMask ( M , VT , 64 ) || isREVMask ( M , VT , 32 ) || isREVMask ( M , VT , 16 ) || isEXTMask ( M , VT , DummyBool , DummyUnsigned ) || isTRNMask ( M , VT , DummyUnsigned ) || isUZPMask ( M , VT , DummyUnsigned ) || isZIPMask ( M , VT , DummyUnsigned ) || isTRN_v_undef_Mask ( M , VT , DummyUnsigned ) || isUZP_v_undef_Mask ( M , VT , DummyUnsigned ) || isZIP_v_undef_Mask ( M , VT , DummyUnsigned ) || isINSMask ( M , VT . getVectorNumElements ( ) , DummyBool , DummyInt ) || isConcatMask ( M , VT , VT . getSizeInBits ( ) == 128 ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> bool ARMBaseInstrInfo :: PredicateInstruction ( MachineInstr * MI , const SmallVectorImpl < MachineOperand > & Pred ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( isUncondBranchOpcode ( Opc ) ) { MI -> setDesc ( get ( getMatchingCondBranchOpcode ( Opc ) ) ) ; MI -> addOperand ( MachineOperand :: CreateImm ( Pred [ 0 ] . getImm ( ) ) ) ; MI -> addOperand ( MachineOperand :: CreateReg ( Pred [ 1 ] . getReg ( ) , false ) ) ; return true ; } int PIdx = MI -> findFirstPredOperandIdx ( ) ; if ( PIdx != - 1 ) { MachineOperand & PMO = MI -> getOperand ( PIdx ) ; PMO . setImm ( Pred [ 0 ] . getImm ( ) ) ; MI -> getOperand ( PIdx + 1 ) . setReg ( Pred [ 1 ] . getReg ( ) ) ; return true ; } return false ; } </s>

Convert the instruction into a predicated instruction .


<s>
void
MOSMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
verifyInstructionPredicates
(
MI
,
computeAvailableFeatures
(
STI
.
getFeatureBits
(
)
)
)
;
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
unsigned
Size
=
Desc
.
getSize
(
)
;
assert
(
Size
>
0
&&
"Instruction size cannot be zero"
)
;
uint64_t
BinaryOpCode
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
emitInstruction
(
BinaryOpCode
,
Size
,
STI
,
OS
)
;
}
</s>

MOS
MOS
0
"Instruction size cannot be zero"


<s> bool TPCAsmBackend :: mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> bool contains ( const MachineBasicBlock * MBB ) const override { return Unit -> contains ( MBB ) ; } </s>

contains - Returns true if this trace contains the given basic block .


<s> MVT :: SimpleValueType X86TargetLowering :: getSetCCResultType ( EVT VT ) const { return MVT :: i8 ; } </s>

Return the value type to use for ISD : :SETCC .


<s>
static
void
print_multi_reg
(
FILE
*
stream
,
const
char
*
instr
,
unsigned
reg
,
unsigned
long
mask
)
{
unsigned
i
;
bool
not_first
=
FALSE
;
fputc
(
'\t'
,
stream
)
;
asm_fprintf
(
stream
,
instr
,
reg
)
;
fputs
(
", {"
,
stream
)
;
for
(
i
=
0
;
i
<=
LAST_ARM_REGNUM
;
i
++
)
if
(
mask
&
(
1
<<
i
)
)
{
if
(
not_first
)
fprintf
(
stream
,
", "
)
;
asm_fprintf
(
stream
,
"%r"
,
i
)
;
not_first
=
TRUE
;
}
fprintf
(
stream
,
"}\n"
)
;
}
</s>

Output the operands of a LDM/STM instruction to STREAM . MASK is the ARM register set mask of which only bits 0-15 are important . REG is the base register , either the frame pointer or the stack pointer , INSTR is the possibly suffixed load or store instruction .


<s> void MipsTargetELFStreamer :: finish ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; const MCObjectFileInfo & OFI = * MCA . getContext ( ) . getObjectFileInfo ( ) ; MCSection & TextSection = * OFI . getTextSection ( ) ; MCA . registerSection ( TextSection ) ; MCSection & DataSection = * OFI . getDataSection ( ) ; MCA . registerSection ( DataSection ) ; MCSection & BSSSection = * OFI . getBSSSection ( ) ; MCA . registerSection ( BSSSection ) ; TextSection . setAlignment ( Align ( std :: max ( 16u , TextSection . getAlignment ( ) ) ) ) ; DataSection . setAlignment ( Align ( std :: max ( 16u , DataSection . getAlignment ( ) ) ) ) ; BSSSection . setAlignment ( Align ( std :: max ( 16u , BSSSection . getAlignment ( ) ) ) ) ; if ( RoundSectionSizes ) { MCStreamer & OS = getStreamer ( ) ; for ( MCSection & S : MCA ) { MCSectionELF & Section = static_cast < MCSectionELF & > ( S ) ; unsigned Alignment = Section . getAlignment ( ) ; if ( Alignment ) { OS . SwitchSection ( & Section ) ; if ( Section . UseCodeAlign ( ) ) OS . emitCodeAlignment ( Alignment , Alignment ) ; else OS . emitValueToAlignment ( Alignment , 0 , 1 , Alignment ) ; } } } const FeatureBitset & Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI_O32 ; else if ( getABI ( ) . IsN32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI2 ; if ( Features [ Mips :: FeatureGP64Bit ] ) { if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_32BITMODE ; } else if ( Features [ Mips :: FeatureMips64r2 ] || Features [ Mips :: FeatureMips64 ] ) EFlags |= ELF :: EF_MIPS_32BITMODE ; if ( ! Features [ Mips :: FeatureNoABICalls ] ) EFlags |= ELF :: EF_MIPS_CPIC ; if ( Pic ) EFlags |= ELF :: EF_MIPS_PIC | ELF :: EF_MIPS_CPIC ; MCA . setELFHeaderEFlags ( EFlags ) ; MipsELFStreamer & MEF = static_cast < MipsELFStreamer & > ( Streamer ) ; MEF . EmitMipsOptionRecords ( ) ; emitMipsAbiFlags ( ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> static int m32r_issue_rate ( void ) { return ( ( TARGET_LOW_ISSUE_RATE ) ? 1 : 2 ) ; } </s>

Indicate how many instructions can be issued at the same time . This is sort of a lie . The m32r can issue only 1 long insn at once , but it can issue 2 short insns . The default therefore is set at 2 , but this can be overridden by the command line option -missue-rate=1


<s>
void
X86InstrInfo
::
replaceBranchWithTailCall
(
MachineBasicBlock
&
MBB
,
SmallVectorImpl
<
MachineOperand
>
&
BranchCond
,
const
MachineInstr
&
TailCall
)
const
{
assert
(
canMakeTailCallConditional
(
BranchCond
,
TailCall
)
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
!
I
->
isBranch
(
)
)
assert
(
0
&&
"Can't find the branch to replace!"
)
;
X86
::
CondCode
CC
=
getCondFromBranchOpc
(
I
->
getOpcode
(
)
)
;
assert
(
BranchCond
.
size
(
)
==
1
)
;
if
(
CC
!=
BranchCond
[
0
]
.
getImm
(
)
)
continue
;
break
;
}
unsigned
Opc
=
TailCall
.
getOpcode
(
)
==
X86
::
TCRETURNdi
X86
::
TCRETURNdicc
:
X86
::
TCRETURNdi64cc
;
auto
MIB
=
BuildMI
(
MBB
,
I
,
MBB
.
findDebugLoc
(
I
)
,
get
(
Opc
)
)
;
MIB
->
addOperand
(
TailCall
.
getOperand
(
0
)
)
;
MIB
.
addImm
(
0
)
;
MIB
->
addOperand
(
BranchCond
[
0
]
)
;
MIB
.
copyImplicitOps
(
TailCall
)
;
I
->
eraseFromParent
(
)
;
}
</s>

Replace the conditional branch in MBB with a conditional tail call .


<s> InstructionCost AArch64TTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * DataTy , const Value * Ptr , bool VariableMask , Align Alignment , TTI :: TargetCostKind CostKind , const Instruction * I ) { if ( useNeonVector ( DataTy ) ) return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , CostKind , I ) ; auto * VT = cast < VectorType > ( DataTy ) ; auto LT = TLI -> getTypeLegalizationCost ( DL , DataTy ) ; if ( ! LT . first . isValid ( ) ) return InstructionCost :: getInvalid ( ) ; if ( cast < VectorType > ( DataTy ) -> getElementCount ( ) == ElementCount :: getScalable ( 1 ) ) return InstructionCost :: getInvalid ( ) ; ElementCount LegalVF = LT . second . getVectorElementCount ( ) ; InstructionCost MemOpCost = getMemoryOpCost ( Opcode , VT -> getElementType ( ) , Alignment , 0 , CostKind , I ) ; return LT . first * MemOpCost * getMaxNumElements ( LegalVF ) ; } </s>

Calculate the cost of Gather / Scatter operation .


<s> void altivec_expand_stvx_be ( rtx op0 , rtx op1 , machine_mode mode , unsigned unspec ) { rtx tmp = gen_reg_rtx ( mode ) ; rtx store = gen_rtx_SET ( op0 , tmp ) ; rtx stvx = gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , const0_rtx ) , unspec ) ; rtx par = gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , store , stvx ) ) ; rtx sel = swap_selector_for_mode ( mode ) ; rtx vperm ; gcc_assert ( REG_P ( op1 ) ) ; vperm = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , op1 , op1 , sel ) , UNSPEC_VPERM ) ; emit_insn ( gen_rtx_SET ( tmp , vperm ) ) ; emit_insn ( par ) ; } </s>

Generate code for a `` stvx '' or `` stvxl '' built-in for a little endian target with -maltivec=be specified . Issue the store preceded by an element-reversing permute .


<s>
StringRef
getPassName
(
)
const
override
{
return
"GCN RegBank Reassign"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void M680x0InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << "%" << StringRef ( getRegisterName ( RegNo ) ) ; } </s>


<s> SMLoc getStartLoc ( ) const { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> unsigned X86TTIImpl :: getNumberOfRegisters ( bool Vector ) { if ( Vector && ! ST -> hasSSE1 ( ) ) return 0 ; if ( ST -> is64Bit ( ) ) { if ( Vector && ST -> hasAVX512 ( ) ) return 32 ; return 16 ; } return 8 ; } </s>


<s> static void vr4130_avoid_branch_rt_conflict ( rtx insn ) { rtx first , second ; first = SEQ_BEGIN ( insn ) ; second = SEQ_END ( insn ) ; if ( JUMP_P ( first ) && NONJUMP_INSN_P ( second ) && GET_CODE ( PATTERN ( first ) ) == SET && GET_CODE ( SET_DEST ( PATTERN ( first ) ) ) == PC && GET_CODE ( SET_SRC ( PATTERN ( first ) ) ) == IF_THEN_ELSE ) { rtx cond = XEXP ( SET_SRC ( PATTERN ( first ) ) , 0 ) ; if ( ( GET_CODE ( cond ) == EQ || GET_CODE ( cond ) == NE ) && REG_P ( XEXP ( cond , 0 ) ) && REG_P ( XEXP ( cond , 1 ) ) && reg_referenced_p ( XEXP ( cond , 1 ) , PATTERN ( second ) ) && ! reg_referenced_p ( XEXP ( cond , 0 ) , PATTERN ( second ) ) ) { rtx tmp = XEXP ( cond , 0 ) ; XEXP ( cond , 0 ) = XEXP ( cond , 1 ) ; XEXP ( cond , 1 ) = tmp ; } } } </s>

The VR4130 pipeline issues aligned pairs of instructions together , but it stalls the second instruction if it depends on the first . In order to cut down the amount of logic required , this dependence check is not based on a full instruction decode . Instead , any non-SPECIAL instruction is assumed to modify the register specified by bits 20-16 ( which is usually the `` rt '' field ) . In beq , beql , bne and bnel instructions , the rt field is actually an input , so we can end up with a false dependence between the branch and its delay slot . If this situation occurs in instruction INSN , try to avoid it by swapping rs and rt .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>


<s> static void emit_store_conditional ( enum machine_mode mode , rtx res , rtx mem , rtx val ) { rtx ( * fn ) ( rtx , rtx , rtx ) = NULL ; if ( mode == SImode ) fn = gen_store_conditional_si ; else if ( mode == DImode ) fn = gen_store_conditional_di ; if ( PPC405_ERRATUM77 ) emit_insn ( gen_memory_barrier ( ) ) ; emit_insn ( fn ( res , mem , val ) ) ; } </s>

A subroutine of the atomic operation splitters . Emit a store-conditional instruction in MODE .


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { if ( CommentStream ) HasCustomInstComment = EmitAnyX86InstComments ( MI , * CommentStream , MII ) ; printInstFlags ( MI , OS ) ; if ( MI -> getOpcode ( ) == X86 :: CALLpcrel32 && ( STI . getFeatureBits ( ) [ X86 :: Mode64Bit ] ) ) { OS << "\tcallq\t" ; printPCRelImm ( MI , 0 , OS ) ; } else if ( MI -> getOpcode ( ) == X86 :: DATA16_PREFIX && STI . getFeatureBits ( ) [ X86 :: Mode16Bit ] ) { OS << "\tdata32" ; } else if ( ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> int fp_high_losum_p ( rtx op ) { if ( GET_CODE ( op ) == CONST_DOUBLE ) { long i ; REAL_VALUE_TO_TARGET_SINGLE ( * CONST_DOUBLE_REAL_VALUE ( op ) , i ) ; return ! SPARC_SIMM13_P ( i ) && ! SPARC_SETHI_P ( i ) ; } return 0 ; } </s>

Nonzero if OP is a floating point constant which can be loaded into an integer register using a high/losum instruction sequence .


<s> bool CJGFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> int arith_operand ( rtx op , enum machine_mode mode ) { if ( GET_CODE ( op ) == CONST_INT && SMALL_INT ( op ) ) return 1 ; return register_operand ( op , mode ) ; } </s>

Return true if OP is a register , or is a CONST_INT that can fit in a signed 13 bit immediate field . This is an acceptable SImode operand for most 3 address instructions .


<s>
bool
AMDGPULegalizerInfo
::
legalizeCustom
(
MachineInstr
&
MI
,
MachineRegisterInfo
&
MRI
,
MachineIRBuilder
&
MIRBuilder
,
GISelChangeObserver
&
Observer
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
case
TargetOpcode
::
G_ADDRSPACE_CAST
:
return
legalizeAddrSpaceCast
(
MI
,
MRI
,
MIRBuilder
)
;
case
TargetOpcode
::
G_FRINT
:
return
legalizeFrint
(
MI
,
MRI
,
MIRBuilder
)
;
case
TargetOpcode
::
G_FCEIL
:
return
legalizeFceil
(
MI
,
MRI
,
MIRBuilder
)
;
case
TargetOpcode
::
G_INTRINSIC_TRUNC
:
return
legalizeIntrinsicTrunc
(
MI
,
MRI
,
MIRBuilder
)
;
case
TargetOpcode
::
G_SITOFP
:
return
legalizeITOFP
(
MI
,
MRI
,
MIRBuilder
,
true
)
;
case
TargetOpcode
::
G_UITOFP
:
return
legalizeITOFP
(
MI
,
MRI
,
MIRBuilder
,
false
)
;
default
:
return
false
;
}
llvm_unreachable
(
"expected switch to return"
)
;
}
</s>

Called for instructions with the Custom LegalizationAction .

AMDGPU
AMDGPU
SI
SI
"expected switch to return"


<s>
SDValue
ARMTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom lower this!"
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
Subtarget
->
isTargetDarwin
(
)
LowerGlobalAddressDarwin
(
Op
,
DAG
)
:
LowerGlobalAddressELF
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
LowerSELECT
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
BR_JT
:
return
LowerBR_JT
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
MEMBARRIER
:
return
LowerMEMBARRIER
(
Op
,
DAG
,
Subtarget
)
;
case
ISD
::
SINT_TO_FP
:
case
ISD
::
UINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
)
;
case
ISD
::
FCOPYSIGN
:
return
LowerFCOPYSIGN
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
return
LowerGLOBAL_OFFSET_TABLE
(
Op
,
DAG
)
;
case
ISD
::
EH_SJLJ_SETJMP
:
return
LowerEH_SJLJ_SETJMP
(
Op
,
DAG
)
;
case
ISD
::
EH_SJLJ_LONGJMP
:
return
LowerEH_SJLJ_LONGJMP
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
,
Subtarget
)
;
case
ISD
::
BIT_CONVERT
:
return
ExpandBIT_CONVERT
(
Op
.
getNode
(
)
,
DAG
)
;
case
ISD
::
SHL
:
case
ISD
::
SRL
:
case
ISD
::
SRA
:
return
LowerShift
(
Op
.
getNode
(
)
,
DAG
,
Subtarget
)
;
case
ISD
::
SHL_PARTS
:
return
LowerShiftLeftParts
(
Op
,
DAG
)
;
case
ISD
::
SRL_PARTS
:
case
ISD
::
SRA_PARTS
:
return
LowerShiftRightParts
(
Op
,
DAG
)
;
case
ISD
::
CTTZ
:
return
LowerCTTZ
(
Op
.
getNode
(
)
,
DAG
,
Subtarget
)
;
case
ISD
::
VSETCC
:
return
LowerVSETCC
(
Op
,
DAG
)
;
case
ISD
::
BUILD_VECTOR
:
return
LowerBUILD_VECTOR
(
Op
,
DAG
,
Subtarget
)
;
case
ISD
::
VECTOR_SHUFFLE
:
return
LowerVECTOR_SHUFFLE
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_VECTOR_ELT
:
return
LowerEXTRACT_VECTOR_ELT
(
Op
,
DAG
)
;
case
ISD
::
CONCAT_VECTORS
:
return
LowerCONCAT_VECTORS
(
Op
,
DAG
)
;
case
ISD
::
FLT_ROUNDS_
:
return
LowerFLT_ROUNDS_
(
Op
,
DAG
)
;
case
ISD
::
MUL
:
return
LowerMUL
(
Op
,
DAG
)
;
}
return
SDValue
(
)
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s>
bool
TVMLoopPrepare
::
runOnFunction
(
Function
&
F
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"runnning TVMLoopPrepare on "
<<
F
.
getName
(
)
<<
"\n"
)
;
const
LoopInfo
&
LI
=
getAnalysis
<
LoopInfoWrapperPass
>
(
)
.
getLoopInfo
(
)
;
DenseMap
<
Loop
*
,
bool
>
LoopsProcessed
;
bool
Changed
=
false
;
for
(
auto
&
BB
:
F
)
{
Loop
*
L
=
LI
.
getLoopFor
(
&
BB
)
;
if
(
!
L
||
LoopsProcessed
[
L
]
)
continue
;
LoopsProcessed
[
L
]
=
true
;
BasicBlock
*
Predecessor
=
L
->
getLoopPredecessor
(
)
;
assert
(
Predecessor
&&
"Unexpected shape of a loop"
)
;
Instruction
*
Term
=
Predecessor
->
getTerminator
(
)
;
if
(
auto
*
Br
=
dyn_cast
<
BranchInst
>
(
Term
)
)
Changed
|=
canonicalizeTerminator
(
Br
,
*
L
)
;
BasicBlock
*
Latch
=
L
->
getLoopLatch
(
)
;
assert
(
Latch
)
;
Term
=
Latch
->
getTerminator
(
)
;
if
(
auto
*
Br
=
dyn_cast
<
BranchInst
>
(
Term
)
)
Changed
|=
canonicalizeTerminator
(
Br
,
*
L
)
;
}
return
Changed
;
}
</s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .

TVM
TVM
"runnning TVMLoopPrepare on "
"\n"
"Unexpected shape of a loop"


<s> bool RISCVTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( ! Subtarget . hasNonStdExtPulp ( ) ) return false ; if ( Op -> getOpcode ( ) != ISD :: ADD ) return false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Base = LD -> getBasePtr ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Base = ST -> getBasePtr ( ) ; } else { return false ; } if ( Base == Op -> getOperand ( 0 ) ) { Offset = Op -> getOperand ( 1 ) ; } else if ( Base == Op -> getOperand ( 1 ) ) { Offset = Op -> getOperand ( 0 ) ; } else { return false ; } AM = ISD :: POST_INC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .


<s> enum reg_class crx_secondary_reload_class ( enum reg_class class , enum machine_mode mode ATTRIBUTE_UNUSED , rtx x ATTRIBUTE_UNUSED ) { if ( reg_classes_intersect_p ( class , HILO_REGS ) && true_regnum ( x ) == - 1 ) return GENERAL_REGS ; return NO_REGS ; } </s>

Transfer between HILO_REGS and memory via secondary reloading .


<s> bool LC2200InstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: reverse_iterator I = MBB . rbegin ( ) , REnd = MBB . rend ( ) ; while ( I != REnd && I -> isDebugInstr ( ) ) ++ I ; if ( I == REnd || ! isUnpredicatedTerminator ( * I ) ) { TBB = FBB = nullptr ; return false ; } SmallVector < MachineInstr * , 4 > BranchInstrs ; MachineInstr * LastInst = & * I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; BranchInstrs . push_back ( LastInst ) ; if ( ! getAnalyzableBrOpc ( LastOpc ) ) return true ; unsigned SecondLastOpc = 0 ; MachineInstr * SecondLastInst = nullptr ; ++ I ; while ( I != REnd && I -> isDebugInstr ( ) ) ++ I ; if ( I != REnd ) { SecondLastInst = & * I ; SecondLastOpc = SecondLastInst -> getOpcode ( ) ; if ( isUnpredicatedTerminator ( * SecondLastInst ) && ! getAnalyzableBrOpc ( SecondLastOpc ) ) return true ; } if ( ! SecondLastOpc || ( SecondLastOpc != LC2200 :: JMP && SecondLastOpc != LC2200 :: CMP_JMP && SecondLastOpc != LC2200 :: GOTO ) ) { if ( LastInst -> isUnconditionalBranch ( ) ) { TBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } AnalyzeCondBr ( LastInst , LastOpc , TBB , Cond ) ; return false ; } if ( ++ I != REnd && isUnpredicatedTerminator ( * I ) ) return true ; BranchInstrs . insert ( BranchInstrs . begin ( ) , SecondLastInst ) ; if ( SecondLastInst -> isUnconditionalBranch ( ) ) { if ( ! AllowModify ) { return true ; } TBB = SecondLastInst -> getOperand ( 0 ) . getMBB ( ) ; LastInst -> eraseFromParent ( ) ; BranchInstrs . pop_back ( ) ; return false ; } if ( ! LastInst -> isUnconditionalBranch ( ) ) return true ; AnalyzeCondBr ( SecondLastInst , SecondLastOpc , TBB , Cond ) ; FBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s>
static
unsigned
getType
(
const
TargetRegisterClass
*
RC
)
{
if
(
RC
==
&
WebAssembly
::
I32RegClass
)
return
unsigned
(
WebAssembly
::
ExprType
::
I32
)
;
if
(
RC
==
&
WebAssembly
::
I64RegClass
)
return
unsigned
(
WebAssembly
::
ExprType
::
I64
)
;
if
(
RC
==
&
WebAssembly
::
F32RegClass
)
return
unsigned
(
WebAssembly
::
ExprType
::
F32
)
;
if
(
RC
==
&
WebAssembly
::
F64RegClass
)
return
unsigned
(
WebAssembly
::
ExprType
::
F64
)
;
llvm_unreachable
(
"Unexpected register class"
)
;
}
</s>

Overload to return most specific vector type .


<s>
CCAssignFn
*
ARMFastISel
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
Return
)
{
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
(
void
)
RetFastCC_ARM_APCS
;
(
void
)
FastCC_ARM_APCS
;
case
CallingConv
::
C
:
if
(
Subtarget
->
isAAPCS_ABI
(
)
)
{
if
(
Subtarget
->
hasVFP2
(
)
&&
FloatABIType
==
FloatABI
::
Hard
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
else
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
}
else
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
case
CallingConv
::
ARM_AAPCS_VFP
:
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
case
CallingConv
::
ARM_AAPCS
:
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
case
CallingConv
::
ARM_APCS
:
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
case
CallingConv
::
GHC
:
if
(
Return
)
llvm_unreachable
(
"Can't return in GHC call convention"
)
;
else
return
CC_ARM_APCS_GHC
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .

ARM
ARM
"Unsupported calling convention"
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
"Can't return in GHC call convention"
ARM


<s> static void crx_compute_save_regs ( void ) { unsigned int regno ; last_reg_to_save = - 1 ; if ( FUNC_IS_NORETURN_P ( current_function_decl ) ) return ; sum_regs = 0 ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) { if ( fixed_regs [ regno ] ) { save_regs [ regno ] = 0 ; continue ; } if ( crx_interrupt_function_p ( ) ) { if ( ! current_function_is_leaf && call_used_regs [ regno ] ) save_regs [ regno ] = 1 ; else if ( regs_ever_live [ regno ] ) save_regs [ regno ] = 1 ; else save_regs [ regno ] = 0 ; } else { if ( regs_ever_live [ regno ] && ( ! call_used_regs [ regno ] || regno == RETURN_ADDRESS_REGNUM ) ) save_regs [ regno ] = 1 ; else save_regs [ regno ] = 0 ; } } for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( save_regs [ regno ] == 1 ) { last_reg_to_save = regno ; sum_regs += UNITS_PER_WORD ; } } </s>

Compute values for the array save_regs and the variable sum_regs . The index * of save_regs is numbers of register , each will get 1 if we need to save it * in the current function , 0 if not . sum_regs is the total sum of the * registers being saved .


<s> MachineBasicBlock :: iterator Thumb1FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const Thumb1InstrInfo & TII = * static_cast < const Thumb1InstrInfo * > ( STI . getInstrInfo ( ) ) ; const ThumbRegisterInfo * RegInfo = static_cast < const ThumbRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr & Old = * I ; DebugLoc dl = Old . getDebugLoc ( ) ; unsigned Amount = TII . getFrameSize ( Old ) ; if ( Amount != 0 ) { Amount = alignTo ( Amount , getStackAlignment ( ) ) ; unsigned Opc = Old . getOpcode ( ) ; if ( Opc == ARM :: ADJCALLSTACKDOWN || Opc == ARM :: tADJCALLSTACKDOWN ) { emitSPUpdate ( MBB , I , TII , dl , * RegInfo , - Amount ) ; } else { assert ( Opc == ARM :: ADJCALLSTACKUP || Opc == ARM :: tADJCALLSTACKUP ) ; emitSPUpdate ( MBB , I , TII , dl , * RegInfo , Amount ) ; } } } return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

ARM 0 ARM::ADJCALLSTACKDOWN ARM::tADJCALLSTACKDOWN ARM::ADJCALLSTACKUP ARM::tADJCALLSTACKUP


<s>
std
::
string
MBlazeIntrinsicInfo
::
getName
(
unsigned
IntrID
,
const
Type
*
*
Tys
,
unsigned
numTys
)
const
{
static
const
char
*
const
names
[
]
=
{
}
;
assert
(
!
isOverloaded
(
IntrID
)
&&
"MBlaze intrinsics are not overloaded"
)
;
if
(
IntrID
<
Intrinsic
::
num_intrinsics
)
return
0
;
assert
(
IntrID
<
mblazeIntrinsic
::
num_mblaze_intrinsics
&&
"Invalid intrinsic ID"
)
;
std
::
string
Result
(
names
[
IntrID
Intrinsic
::
num_intrinsics
]
)
;
return
Result
;
}
</s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> MCSection * X86WindowsTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , unsigned & Align ) const { if ( Kind . isMergeableConst ( ) && C ) { const unsigned Characteristics = COFF :: IMAGE_SCN_CNT_INITIALIZED_DATA | COFF :: IMAGE_SCN_MEM_READ | COFF :: IMAGE_SCN_MEM_WRITE | COFF :: IMAGE_SCN_LNK_COMDAT ; std :: string COMDATSymName ; if ( Kind . isMergeableConst4 ( ) ) { if ( Align <= 4 ) { COMDATSymName = "__real@" + scalarConstantToHexString ( C ) ; Align = 4 ; } } else if ( Kind . isMergeableConst8 ( ) ) { if ( Align <= 8 ) { COMDATSymName = "__real@" + scalarConstantToHexString ( C ) ; Align = 8 ; } } else if ( Kind . isMergeableConst16 ( ) ) { if ( Align <= 16 ) { COMDATSymName = "__xmm@" + scalarConstantToHexString ( C ) ; Align = 16 ; } } else if ( Kind . isMergeableConst32 ( ) ) { if ( Align <= 32 ) { COMDATSymName = "__ymm@" + scalarConstantToHexString ( C ) ; Align = 32 ; } } if ( ! COMDATSymName . empty ( ) ) return getContext ( ) . getCOFFSection ( "sgxg_pub" , Characteristics , Kind , COMDATSymName , COFF :: IMAGE_COMDAT_SELECT_ANY ) ; } return TargetLoweringObjectFile :: getSectionForConstant ( DL , Kind , C , Align ) ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> rtx assign_386_stack_local ( machine_mode mode , enum ix86_stack_slot n ) { struct stack_local_entry * s ; gcc_assert ( n < MAX_386_STACK_LOCALS ) ; for ( s = ix86_stack_locals ; s ; s = s -> next ) if ( s -> mode == mode && s -> n == n ) return validize_mem ( copy_rtx ( s -> rtl ) ) ; s = ggc_alloc < stack_local_entry > ( ) ; s -> n = n ; s -> mode = mode ; s -> rtl = assign_stack_local ( mode , GET_MODE_SIZE ( mode ) , 0 ) ; s -> next = ix86_stack_locals ; ix86_stack_locals = s ; return validize_mem ( copy_rtx ( s -> rtl ) ) ; } </s>

Return a MEM corresponding to a stack slot with mode MODE . Allocate a new slot if necessary . The RTL for a function can have several slots available : N is which slot to use .


<s> bool SIInstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Cond , unsigned TrueReg , unsigned FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { switch ( Cond [ 0 ] . getImm ( ) ) { case VCCNZ : case VCCZ : { const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = MRI . getRegClass ( TrueReg ) ; assert ( MRI . getRegClass ( FalseReg ) == RC ) ; int NumInsts = AMDGPU :: getRegBitWidth ( RC -> getID ( ) ) / 32 ; CondCycles = TrueCycles = FalseCycles = NumInsts ; return ! RI . isSGPRClass ( RC ) && NumInsts <= 6 ; } case SCC_TRUE : case SCC_FALSE : { const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = MRI . getRegClass ( TrueReg ) ; assert ( MRI . getRegClass ( FalseReg ) == RC ) ; int NumInsts = AMDGPU :: getRegBitWidth ( RC -> getID ( ) ) / 32 ; if ( NumInsts % 2 == 0 ) NumInsts /= 2 ; CondCycles = TrueCycles = FalseCycles = NumInsts ; return RI . isSGPRClass ( RC ) ; } default : return false ; } } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


"Instr doesn't have FrameIndex operand!"

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s> static bool loongarch_pass_by_reference ( cumulative_args_t cum_v , const function_arg_info & arg ) { HOST_WIDE_INT size = arg . type_size_in_bytes ( ) ; struct loongarch_arg_info info ; CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( cum != NULL ) { loongarch_get_arg_info ( & info , cum , arg . mode , arg . type , arg . named , false ) ; if ( info . num_fprs ) return false ; } return ! IN_RANGE ( size , 0 , 2 * UNITS_PER_WORD ) ; } </s>


<s>
SDValue
SPUTargetLowering
::
LowerReturn
(
SDValue
Chain
,
unsigned
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_SPU
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
Outs
[
i
]
.
Val
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
SPUISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
else
return
DAG
.
getNode
(
SPUISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static void h8300_file_end ( void ) { fputs ( "\t.end\n" , asm_out_file ) ; } </s>

Output assembly language code for the end of file .


<s> std :: pair < unsigned , const TargetRegisterClass * > MBlazeTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , MBlaze :: GPRRegisterClass ) ; case 'f' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , MBlaze :: GPRRegisterClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> void JVMInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & ) { printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> void mips_emit_save_slot_move ( rtx dest , rtx src , rtx temp ) { unsigned int regno ; rtx mem ; if ( REG_P ( src ) ) { regno = REGNO ( src ) ; mem = dest ; } else { regno = REGNO ( dest ) ; mem = src ; } if ( regno == cfun -> machine -> global_pointer && ! mips_must_initialize_gp_p ( ) ) { if ( TARGET_64BIT ) emit_insn ( gen_move_gpdi ( dest , src ) ) ; else emit_insn ( gen_move_gpsi ( dest , src ) ) ; return ; } if ( regno == HI_REGNUM ) { if ( REG_P ( dest ) ) { mips_emit_move ( temp , src ) ; if ( TARGET_64BIT ) emit_insn ( gen_mthisi_di ( gen_rtx_REG ( TImode , MD_REG_FIRST ) , temp , gen_rtx_REG ( DImode , LO_REGNUM ) ) ) ; else emit_insn ( gen_mthisi_di ( gen_rtx_REG ( DImode , MD_REG_FIRST ) , temp , gen_rtx_REG ( SImode , LO_REGNUM ) ) ) ; } else { if ( TARGET_64BIT ) emit_insn ( gen_mfhidi_ti ( temp , gen_rtx_REG ( TImode , MD_REG_FIRST ) ) ) ; else emit_insn ( gen_mfhisi_di ( temp , gen_rtx_REG ( DImode , MD_REG_FIRST ) ) ) ; mips_emit_move ( dest , temp ) ; } } else if ( mips_direct_save_slot_move_p ( regno , mem , mem == src ) ) mips_emit_move ( dest , src ) ; else { gcc_assert ( ! reg_overlap_mentioned_p ( dest , temp ) ) ; mips_emit_move ( temp , src ) ; mips_emit_move ( dest , temp ) ; } if ( MEM_P ( dest ) ) mips_set_frame_expr ( mips_frame_set ( dest , src ) ) ; } </s>

Emit a move from SRC to DEST , given that one of them is a register save slot and that the other is a register . TEMP is a temporary GPR of the same mode that is available if need be .


<s> bool LSRWithInstrQueries ( ) { return true ; } </s>

Return true if the loop strength reduce pass should make Instruction * based TTI queries to isLegalAddressingMode ( ) .


<s> bool isMem ( ) const override { return false ; } </s>


<s> void PPCRegisterInfo :: lowerCRSpilling ( MachineBasicBlock :: iterator II , unsigned FrameIndex , int SPAdj , RegScavenger * RS ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; ( void ) SPAdj ; ( void ) RS ; bool LP64 = Subtarget . isPPC64 ( ) ; unsigned Reg = LP64 ? PPC :: X0 : PPC :: R0 ; unsigned SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: MFCR8pseud : PPC :: MFCRpseud ) , Reg ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( 0 ) . isKill ( ) ) ) ; if ( SrcReg != PPC :: CR0 ) BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: RLWINM8 : PPC :: RLWINM ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( getPPCRegisterNumbering ( SrcReg ) * 4 ) . addImm ( 0 ) . addImm ( 31 ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: STW8 : PPC :: STW ) ) . addReg ( Reg , getKillRegState ( MI . getOperand ( 1 ) . getImm ( ) ) ) , FrameIndex ) ; MBB . erase ( II ) ; } </s>

lowerCRSpilling - Generate the code for spilling a CR register .


<s> void EmitInstruction ( const MachineInstr * MI ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; printInstruction ( MI , OS ) ; OutStreamer . EmitRawText ( OS . str ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> LLT AArch64TargetLowering :: getOptimalMemOpLLT ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , const AttributeList & FuncAttributes ) const { bool CanImplicitFloat = ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; bool CanUseNEON = Subtarget -> hasNEON ( ) && CanImplicitFloat ; bool CanUseFP = Subtarget -> hasFPARMv8 ( ) && CanImplicitFloat ; bool IsSmallMemset = IsMemset && Size < 32 ; auto AlignmentIsAcceptable = [ & ] ( EVT VT , unsigned AlignCheck ) { if ( memOpAlign ( SrcAlign , DstAlign , AlignCheck ) ) return true ; bool Fast ; return allowsMisalignedMemoryAccesses ( VT , 0 , 1 , MachineMemOperand :: MONone , & Fast ) && Fast ; } ; if ( CanUseNEON && IsMemset && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: v2i64 , 16 ) ) return LLT :: vector ( 2 , 64 ) ; if ( CanUseFP && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: f128 , 16 ) ) return LLT :: scalar ( 128 ) ; if ( Size >= 8 && AlignmentIsAcceptable ( MVT :: i64 , 8 ) ) return LLT :: scalar ( 64 ) ; if ( Size >= 4 && AlignmentIsAcceptable ( MVT :: i32 , 4 ) ) return LLT :: scalar ( 32 ) ; return LLT ( ) ; } </s>


<s> bool shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) override { return false ; } </s>

Hook to check if a relocation is needed for some target specific reason .


"unknown core architecture %qs specified with %qs"

Set ` avr_arch ' as specified by ` -mmcu= ' . Return true on success .


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const PPCFrameLowering * PPCFI = static_cast < const PPCFrameLowering * > ( MF . getTarget ( ) . getFrameLowering ( ) ) ; Reserved . set ( PPC :: ZERO ) ; Reserved . set ( PPC :: ZERO8 ) ; Reserved . set ( PPC :: FP ) ; Reserved . set ( PPC :: FP8 ) ; Reserved . set ( PPC :: CTR ) ; Reserved . set ( PPC :: CTR8 ) ; Reserved . set ( PPC :: R1 ) ; Reserved . set ( PPC :: LR ) ; Reserved . set ( PPC :: LR8 ) ; Reserved . set ( PPC :: RM ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: R2 ) ; Reserved . set ( PPC :: R13 ) ; } if ( Subtarget . isPPC64 ( ) ) { Reserved . set ( PPC :: R13 ) ; Reserved . set ( PPC :: X1 ) ; Reserved . set ( PPC :: X13 ) ; if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: X31 ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: X2 ) ; } } if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: R31 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
std
::
string
AMDGPUIntrinsicInfo
::
getName
(
unsigned
IntrID
,
Type
*
*
Tys
,
unsigned
numTys
)
const
{
static
const
char
*
const
names
[
]
=
{
}
;
if
(
IntrID
<
Intrinsic
::
num_intrinsics
)
{
return
nullptr
;
}
assert
(
IntrID
<
AMDGPUIntrinsic
::
num_AMDGPU_intrinsics
&&
"Invalid intrinsic ID"
)
;
std
::
string
Result
(
names
[
IntrID
Intrinsic
::
num_intrinsics
]
)
;
return
Result
;
}
</s>


runOnMachineFunction - Emit the function body .


<s> static int branch_dest ( rtx branch ) { rtx dest = SET_SRC ( PATTERN ( branch ) ) ; int dest_uid ; if ( GET_CODE ( dest ) == IF_THEN_ELSE ) dest = XEXP ( dest , 1 ) ; dest = XEXP ( dest , 0 ) ; dest_uid = INSN_UID ( dest ) ; return INSN_ADDRESSES ( dest_uid ) ; } </s>

Return the destination address of BRANCH . We need to use this instead of get_attr_length , because the cbranch_with_nops pattern conservatively sets its length to 6 , and we still prefer to use shorter sequences .


<s> static rtx frv_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( mode , RETURN_VALUE_REGNUM ) ; } </s>


<s> bool ARCompactInstrInfo :: SubsumesPredicate ( const SmallVectorImpl < MachineOperand > & Pred1 , const SmallVectorImpl < MachineOperand > & Pred2 ) const { if ( Pred1 . size ( ) > 2 || Pred2 . size ( ) > 2 ) { return false ; } ARCCC :: CondCodes CC1 = ( ARCCC :: CondCodes ) Pred1 [ 0 ] . getImm ( ) ; ARCCC :: CondCodes CC2 = ( ARCCC :: CondCodes ) Pred2 [ 0 ] . getImm ( ) ; if ( CC1 == CC2 ) { return true ; } switch ( CC1 ) { case ARCCC :: COND_AL : return true ; case ARCCC :: COND_HS : return CC2 == ARCCC :: COND_HI ; case ARCCC :: COND_LS : return CC2 == ARCCC :: COND_LO || CC2 == ARCCC :: COND_EQ ; case ARCCC :: COND_GE : return CC2 == ARCCC :: COND_GT ; case ARCCC :: COND_LE : return CC2 == ARCCC :: COND_LT ; default : return false ; } } </s>

Returns true if the first specified predicate subsumes the second , e.g .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"SI Shrink Instructions"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> unsigned RISCVInstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { if ( BytesRemoved ) * BytesRemoved = 0 ; MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return 0 ; if ( ! I -> getDesc ( ) . isUnconditionalBranch ( ) && ! I -> getDesc ( ) . isConditionalBranch ( ) ) return 0 ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return 1 ; -- I ; if ( ! I -> getDesc ( ) . isConditionalBranch ( ) ) return 1 ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ; return 2 ; } </s>

Remove the branching code at the end of the specific MBB .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> void ARMTTIImpl :: getPeelingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: PeelingPreferences & PP ) { BaseT :: getPeelingPreferences ( L , SE , PP ) ; } </s>

Get target-customized preferences for the generic loop peeling transformation .


<s> static void ia64_add_bundle_selector_before ( int template0 , rtx_insn * insn ) { rtx b = gen_bundle_selector ( GEN_INT ( template0 ) ) ; ia64_emit_insn_before ( b , insn ) ; if ( ( template0 == 4 || template0 == 5 ) && ia64_except_unwind_info ( & global_options ) == UI_TARGET ) { int i ; rtx note = NULL_RTX ; insn = PREV_INSN ( insn ) ; for ( i = 0 ; i < 3 ; i ++ ) { do insn = next_active_insn ( insn ) ; while ( NONJUMP_INSN_P ( insn ) && get_attr_empty ( insn ) == EMPTY_YES ) ; if ( CALL_P ( insn ) ) note = find_reg_note ( insn , REG_EH_REGION , NULL_RTX ) ; else if ( note ) { int code ; gcc_assert ( ( code = recog_memoized ( insn ) ) == CODE_FOR_nop || code == CODE_FOR_nop_b ) ; if ( find_reg_note ( insn , REG_EH_REGION , NULL_RTX ) ) note = NULL_RTX ; else add_reg_note ( insn , REG_EH_REGION , XEXP ( note , 0 ) ) ; } } } } </s>

Add a bundle selector TEMPLATE0 before INSN .


<s> unsigned GBZ80MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; if ( MO . isFPImm ( ) ) return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( 32 ) . getLimitedValue ( ) ) ; assert ( MO . isExpr ( ) ) ; return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s>
void
RISCVRegisterInfo
::
getOffsetOpcodes
(
const
StackOffset
&
Offset
,
SmallVectorImpl
<
uint64_t
>
&
Ops
)
const
{
assert
(
Offset
.
getScalable
(
)
%
8
==
0
&&
"Invalid frame offset"
)
;
DIExpression
::
appendOffset
(
Ops
,
Offset
.
getFixed
(
)
)
;
unsigned
VLENB
=
getDwarfRegNum
(
RISCV
::
VLENB
,
true
)
;
int64_t
VLENBSized
=
Offset
.
getScalable
(
)
/
8
;
if
(
VLENBSized
>
0
)
{
Ops
.
push_back
(
dwarf
::
DW_OP_constu
)
;
Ops
.
push_back
(
VLENBSized
)
;
Ops
.
append
(
{
dwarf
::
DW_OP_bregx
,
VLENB
,
0ULL
}
)
;
Ops
.
push_back
(
dwarf
::
DW_OP_mul
)
;
Ops
.
push_back
(
dwarf
::
DW_OP_plus
)
;
}
else
if
(
VLENBSized
<
0
)
{
Ops
.
push_back
(
dwarf
::
DW_OP_constu
)
;
Ops
.
push_back
(
VLENBSized
)
;
Ops
.
append
(
{
dwarf
::
DW_OP_bregx
,
VLENB
,
0ULL
}
)
;
Ops
.
push_back
(
dwarf
::
DW_OP_mul
)
;
Ops
.
push_back
(
dwarf
::
DW_OP_minus
)
;
}
}
</s>

Gets the DWARF expression opcodes for Offset .