<s> static int distance_non_agu_define ( unsigned int regno1 , unsigned int regno2 , rtx_insn * insn ) { basic_block bb = BLOCK_FOR_INSN ( insn ) ; int distance = 0 ; bool found = false ; if ( insn != BB_HEAD ( bb ) ) distance = distance_non_agu_define_in_bb ( regno1 , regno2 , insn , distance , PREV_INSN ( insn ) , & found ) ; if ( ! found && distance < LEA_SEARCH_THRESHOLD ) { edge e ; edge_iterator ei ; bool simple_loop = false ; FOR_EACH_EDGE ( e , ei , bb -> preds ) if ( e -> src == bb ) { simple_loop = true ; break ; } if ( simple_loop ) distance = distance_non_agu_define_in_bb ( regno1 , regno2 , insn , distance , BB_END ( bb ) , & found ) ; else { int shortest_dist = - 1 ; bool found_in_bb = false ; FOR_EACH_EDGE ( e , ei , bb -> preds ) { int bb_dist = distance_non_agu_define_in_bb ( regno1 , regno2 , insn , distance , BB_END ( e -> src ) , & found_in_bb ) ; if ( found_in_bb ) { if ( shortest_dist < 0 ) shortest_dist = bb_dist ; else if ( bb_dist > 0 ) shortest_dist = MIN ( bb_dist , shortest_dist ) ; found = true ; } } distance = shortest_dist ; } } if ( ! found ) return - 1 ; return distance >> 1 ; } </s>

Search backward for non-agu definition of register number REGNO1 or register number REGNO2 in INSN 's basic block until 1 . Pass LEA_SEARCH_THRESHOLD instructions , or 2 . Reach neighbour BBs boundary , or 3 . Reach agu definition . Returns the distance between the non-agu definition point and INSN . If no definition point , returns -1 .


<s> static machine_mode mips_dwarf_frame_reg_mode ( int regno ) { machine_mode mode = default_dwarf_frame_reg_mode ( regno ) ; if ( FP_REG_P ( regno ) && mips_abi == ABI_32 && TARGET_FLOAT64 ) mode = SImode ; return mode ; } </s>


<s> void SparcInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { if ( ! printAliasInstr ( MI , STI , O ) && ! printSparcAliasInstr ( MI , STI , O ) ) printInstruction ( MI , STI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> void aarch64_split_add_offset ( scalar_int_mode mode , rtx dest , rtx src , rtx offset_rtx , rtx temp1 , rtx temp2 ) { aarch64_add_offset ( mode , dest , src , rtx_to_poly_int64 ( offset_rtx ) , temp1 , temp2 , false ) ; } </s>

Like aarch64_add_offset , but the offset is given as an rtx rather than a poly_int64 .


<s> SDValue R600TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; R600MachineFunctionInfo * MFI = MF . getInfo < R600MachineFunctionInfo > ( ) ; SmallVector < ISD :: InputArg , 8 > LocalIns ; getOriginalFunctionArgs ( DAG , MF . getFunction ( ) , Ins , LocalIns ) ; AnalyzeFormalArguments ( CCInfo , LocalIns ) ; for ( unsigned i = 0 , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const ISD :: InputArg & In = Ins [ i ] ; EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector ( ) ) { MemVT = MemVT . getVectorElementType ( ) ; } if ( MFI -> getShaderType ( ) != ShaderType :: COMPUTE ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & AMDGPU :: R600_Reg128RegClass ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , AMDGPUAS :: CONSTANT_BUFFER_0 ) ; ISD :: LoadExtType Ext = ISD :: NON_EXTLOAD ; if ( MemVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) { Ext = ISD :: SEXTLOAD ; } unsigned ValBase = ArgLocs [ In . getOrigArgIndex ( ) ] . getLocMemOffset ( ) ; unsigned PartOffset = VA . getLocMemOffset ( ) ; unsigned Offset = 36 + VA . getLocMemOffset ( ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) , PartOffset - ValBase ) ; SDValue Arg = DAG . getLoad ( ISD :: UNINDEXED , Ext , VT , DL , Chain , DAG . getConstant ( Offset , DL , MVT :: i32 ) , DAG . getUNDEF ( MVT :: i32 ) , PtrInfo , MemVT , false , true , true , 4 ) ; InVals . push_back ( Arg ) ; MFI -> ABIArgOffset = Offset + MemVT . getStoreSize ( ) ; } return Chain ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> bool TeakTargetLowering :: allowsMemoryAccess ( LLVMContext & Context , const DataLayout & DL , EVT VT , unsigned AddrSpace , unsigned Alignment , MachineMemOperand :: Flags Flags , bool * Fast ) const { if ( VT . getSizeInBits ( ) != 16 && VT . getSizeInBits ( ) != 32 ) return false ; return TargetLowering :: allowsMemoryAccess ( Context , DL , VT , AddrSpace , Alignment , Flags , Fast ) ; } </s>

This function returns true if the memory access is aligned or if the target allows this specific unaligned memory access .


<s> unsigned rvexRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return ( rvex :: R1 ) ; } </s>


<s> static rtx emit_multi_reg_push ( unsigned long mask , unsigned long dwarf_regs_mask ) { int num_regs = 0 ; int num_dwarf_regs = 0 ; int i , j ; rtx par ; rtx dwarf ; int dwarf_par_index ; rtx tmp , reg ; dwarf_regs_mask &= ~ ( 1 << PC_REGNUM ) ; for ( i = 0 ; i <= LAST_ARM_REGNUM ; i ++ ) { if ( mask & ( 1 << i ) ) num_regs ++ ; if ( dwarf_regs_mask & ( 1 << i ) ) num_dwarf_regs ++ ; } gcc_assert ( num_regs && num_regs <= 16 ) ; gcc_assert ( ( dwarf_regs_mask & ~ mask ) == 0 ) ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs ) ) ; dwarf = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( num_dwarf_regs + 1 ) ) ; dwarf_par_index = 1 ; for ( i = 0 ; i <= LAST_ARM_REGNUM ; i ++ ) { if ( mask & ( 1 << i ) ) { reg = gen_rtx_REG ( SImode , i ) ; XVECEXP ( par , 0 , 0 ) = gen_rtx_SET ( VOIDmode , gen_frame_mem ( BLKmode , gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - 4 * num_regs ) ) ) , gen_rtx_UNSPEC ( BLKmode , gen_rtvec ( 1 , reg ) , UNSPEC_PUSH_MULT ) ) ; if ( dwarf_regs_mask & ( 1 << i ) ) { tmp = gen_rtx_SET ( VOIDmode , gen_frame_mem ( SImode , stack_pointer_rtx ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , dwarf_par_index ++ ) = tmp ; } break ; } } for ( j = 1 , i ++ ; j < num_regs ; i ++ ) { if ( mask & ( 1 << i ) ) { reg = gen_rtx_REG ( SImode , i ) ; XVECEXP ( par , 0 , j ) = gen_rtx_USE ( VOIDmode , reg ) ; if ( dwarf_regs_mask & ( 1 << i ) ) { tmp = gen_rtx_SET ( VOIDmode , gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , 4 * j ) ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , dwarf_par_index ++ ) = tmp ; } j ++ ; } } par = emit_insn ( par ) ; tmp = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - 4 * num_regs ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , 0 ) = tmp ; add_reg_note ( par , REG_FRAME_RELATED_EXPR , dwarf ) ; return par ; } </s>

Generate and emit an insn that we will recognize as a push_multi . Unfortunately , since this insn does not reflect very well the actual semantics of the operation , we need to annotate the insn for the benefit of DWARF2 frame unwind information .


"WebAssembly doesn't support non-C calling conventions"

"WebAssembly hasn't implemented inalloca arguments"

"WebAssembly hasn't implemented nest arguments"

"WebAssembly hasn't implemented cons regs arguments"

"WebAssembly hasn't implemented cons regs last arguments"


<s> bool Error ( SMLoc L , const Twine & Msg , ArrayRef < SMRange > Ranges = ArrayRef < SMRange > ( ) , bool matchingInlineAsm = false ) { if ( matchingInlineAsm ) return true ; return Parser . Error ( L , Msg , Ranges ) ; } </s>

Return an error at the location L , with the message Msg .


<s> bool AArch64TargetLowering :: isZExtFree ( SDValue Val , EVT VT2 ) const { EVT VT1 = Val . getValueType ( ) ; if ( isZExtFree ( VT1 , VT2 ) ) { return true ; } if ( Val . getOpcode ( ) != ISD :: LOAD ) return false ; return ( VT1 . isSimple ( ) && ! VT1 . isVector ( ) && VT1 . isInteger ( ) && VT2 . isSimple ( ) && ! VT2 . isVector ( ) && VT2 . isInteger ( ) && VT1 . getSizeInBits ( ) <= 32 ) ; } </s>

Return true if zero-extending the specific node Val to type VT2 is free ( either because it 's implicitly zero-extended such as ARM ldrb / ldrh or because it 's folded such as X86 zero-extending loads ) .


<s> int adjacent_mem_locations ( rtx a , rtx b ) { if ( volatile_refs_p ( a ) || volatile_refs_p ( b ) ) return 0 ; if ( ( REG_P ( XEXP ( a , 0 ) ) || ( GET_CODE ( XEXP ( a , 0 ) ) == PLUS && CONST_INT_P ( XEXP ( XEXP ( a , 0 ) , 1 ) ) ) ) && ( REG_P ( XEXP ( b , 0 ) ) || ( GET_CODE ( XEXP ( b , 0 ) ) == PLUS && CONST_INT_P ( XEXP ( XEXP ( b , 0 ) , 1 ) ) ) ) ) { HOST_WIDE_INT val0 = 0 , val1 = 0 ; rtx reg0 , reg1 ; int val_diff ; if ( GET_CODE ( XEXP ( a , 0 ) ) == PLUS ) { reg0 = XEXP ( XEXP ( a , 0 ) , 0 ) ; val0 = INTVAL ( XEXP ( XEXP ( a , 0 ) , 1 ) ) ; } else reg0 = XEXP ( a , 0 ) ; if ( GET_CODE ( XEXP ( b , 0 ) ) == PLUS ) { reg1 = XEXP ( XEXP ( b , 0 ) , 0 ) ; val1 = INTVAL ( XEXP ( XEXP ( b , 0 ) , 1 ) ) ; } else reg1 = XEXP ( b , 0 ) ; if ( ! const_ok_for_op ( val0 , PLUS ) || ! const_ok_for_op ( val1 , PLUS ) ) return 0 ; if ( arm_eliminable_register ( reg0 ) ) return 0 ; val_diff = val1 - val0 ; if ( arm_ld_sched ) { return ( optimize_size && ( REGNO ( reg0 ) == REGNO ( reg1 ) ) && ( val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4 ) && ( val_diff == 4 || val_diff == - 4 ) ) ; } return ( ( REGNO ( reg0 ) == REGNO ( reg1 ) ) && ( val_diff == 4 || val_diff == - 4 ) ) ; } return 0 ; } </s>

If the target storage locations of arguments MEM1 and MEM2 are adjacent , then return the argument that has the lower address . Otherwise , return NULL_RTX .


<s> bool AArch64InstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( TargetInstrInfo :: isSchedulingBoundary ( MI , MBB , MF ) ) return true ; switch ( MI . getOpcode ( ) ) { case AArch64 :: HINT : if ( MI . getOperand ( 0 ) . getImm ( ) == 0x14 ) return true ; break ; case AArch64 :: DSB : case AArch64 :: ISB : return true ; default : ; } return isSEHInstruction ( MI ) ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> SDValue TL45TargetLowering :: getAddr ( NodeTy * N , SelectionDAG & DAG , bool IsLocal ) const { SDLoc DL ( N ) ; EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue r0 = DAG . getRegister ( TL45 :: r0 , MVT :: i32 ) ; SDValue Addr = getTargetNode ( N , DL , Ty , DAG , 0 ) ; return SDValue ( DAG . getMachineNode ( TL45 :: ADDI , DL , Ty , r0 , Addr ) , 0 ) ; } </s>

Return the address accessed by this recipe .


<s> int num_insns_constant ( rtx op , machine_mode mode ) { HOST_WIDE_INT low , high ; switch ( GET_CODE ( op ) ) { case CONST_INT : if ( ( INTVAL ( op ) >> 31 ) != 0 && ( INTVAL ( op ) >> 31 ) != - 1 && rs6000_is_valid_and_mask ( op , mode ) ) return 2 ; else return num_insns_constant_wide ( INTVAL ( op ) ) ; case CONST_WIDE_INT : { int i ; int ins = CONST_WIDE_INT_NUNITS ( op ) - 1 ; for ( i = 0 ; i < CONST_WIDE_INT_NUNITS ( op ) ; i ++ ) ins += num_insns_constant_wide ( CONST_WIDE_INT_ELT ( op , i ) ) ; return ins ; } case CONST_DOUBLE : if ( mode == SFmode || mode == SDmode ) { long l ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) REAL_VALUE_TO_TARGET_DECIMAL32 ( * CONST_DOUBLE_REAL_VALUE ( op ) , l ) ; else REAL_VALUE_TO_TARGET_SINGLE ( * CONST_DOUBLE_REAL_VALUE ( op ) , l ) ; return num_insns_constant_wide ( ( HOST_WIDE_INT ) l ) ; } long l [ 2 ] ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) REAL_VALUE_TO_TARGET_DECIMAL64 ( * CONST_DOUBLE_REAL_VALUE ( op ) , l ) ; else REAL_VALUE_TO_TARGET_DOUBLE ( * CONST_DOUBLE_REAL_VALUE ( op ) , l ) ; high = l [ WORDS_BIG_ENDIAN == 0 ] ; low = l [ WORDS_BIG_ENDIAN != 0 ] ; if ( TARGET_32BIT ) return ( num_insns_constant_wide ( low ) + num_insns_constant_wide ( high ) ) ; else { if ( ( high == 0 && low >= 0 ) || ( high == - 1 && low < 0 ) ) return num_insns_constant_wide ( low ) ; else if ( rs6000_is_valid_and_mask ( op , mode ) ) return 2 ; else if ( low == 0 ) return num_insns_constant_wide ( high ) + 1 ; else return ( num_insns_constant_wide ( high ) + num_insns_constant_wide ( low ) + 1 ) ; } default : gcc_unreachable ( ) ; } } </s>

Return the number of instructions it takes to form a constant in as many gprs are needed for MODE .


<s> const TargetRegisterClass * TeeRISCRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & TeeRISC :: IntRegsRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> static rtx ia64_function_arg ( cumulative_args_t cum , machine_mode mode , const_tree type , bool named ) { return ia64_function_arg_1 ( cum , mode , type , named , false ) ; } </s>

Implement TARGET_FUNCION_ARG target hook .


<s> void R600InstrInfo :: reserveIndirectRegisters ( BitVector & Reserved , const MachineFunction & MF ) const { const AMDGPUFrameLowering * TFL = static_cast < const AMDGPUFrameLowering * > ( MF . getSubtarget ( ) . getFrameLowering ( ) ) ; unsigned StackWidth = TFL -> getStackWidth ( MF ) ; int End = getIndirectIndexEnd ( MF ) ; if ( End == - 1 ) return ; for ( int Index = getIndirectIndexBegin ( MF ) ; Index <= End ; ++ Index ) { unsigned SuperReg = AMDGPU :: R600_Reg128RegClass . getRegister ( Index ) ; Reserved . set ( SuperReg ) ; for ( unsigned Chan = 0 ; Chan < StackWidth ; ++ Chan ) { unsigned Reg = AMDGPU :: R600_TReg32RegClass . getRegister ( ( 4 * Index ) + Chan ) ; Reserved . set ( Reg ) ; } } } </s>

Reserve the registers that may be accessed using indirect addressing .


<s> MipsSubtarget & MipsSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS , const TargetMachine & TM ) { std :: string CPUName = selectMipsCPU ( TargetTriple , CPU ) ; ParseSubtargetFeatures ( CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( InMips16Mode && ! TM . Options . UseSoftFloat ) InMips16HardFloat = true ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> void nds32_cpu_cpp_builtins ( struct cpp_reader * pfile ) { builtin_define ( "__nds32__" ) ; builtin_define ( "__NDS32__" ) ; if ( TARGET_HARD_FLOAT ) builtin_define ( "__NDS32_ABI_2FP_PLUS__" ) ; else builtin_define ( "__NDS32_ABI_2__" ) ; if ( TARGET_ISA_V2 ) builtin_define ( "__NDS32_ISA_V2__" ) ; if ( TARGET_ISA_V3 ) builtin_define ( "__NDS32_ISA_V3__" ) ; if ( TARGET_ISA_V3M ) builtin_define ( "__NDS32_ISA_V3M__" ) ; if ( TARGET_FPU_SINGLE ) builtin_define ( "__NDS32_EXT_FPU_SP__" ) ; if ( TARGET_FPU_DOUBLE ) builtin_define ( "__NDS32_EXT_FPU_DP__" ) ; if ( TARGET_EXT_FPU_FMA ) builtin_define ( "__NDS32_EXT_FPU_FMA__" ) ; if ( NDS32_EXT_FPU_DOT_E ) builtin_define ( "__NDS32_EXT_FPU_DOT_E__" ) ; if ( TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE ) { switch ( nds32_fp_regnum ) { case 0 : case 4 : builtin_define ( "__NDS32_EXT_FPU_CONFIG_0__" ) ; break ; case 1 : case 5 : builtin_define ( "__NDS32_EXT_FPU_CONFIG_1__" ) ; break ; case 2 : case 6 : builtin_define ( "__NDS32_EXT_FPU_CONFIG_2__" ) ; break ; case 3 : case 7 : builtin_define ( "__NDS32_EXT_FPU_CONFIG_3__" ) ; break ; default : abort ( ) ; } } if ( TARGET_BIG_ENDIAN ) builtin_define ( "__NDS32_EB__" ) ; else builtin_define ( "__NDS32_EL__" ) ; if ( TARGET_REDUCED_REGS ) builtin_define ( "__NDS32_REDUCED_REGS__" ) ; if ( TARGET_CMOV ) builtin_define ( "__NDS32_CMOV__" ) ; if ( TARGET_EXT_PERF ) builtin_define ( "__NDS32_EXT_PERF__" ) ; if ( TARGET_EXT_PERF2 ) builtin_define ( "__NDS32_EXT_PERF2__" ) ; if ( TARGET_EXT_STRING ) builtin_define ( "__NDS32_EXT_STRING__" ) ; if ( TARGET_16_BIT ) builtin_define ( "__NDS32_16_BIT__" ) ; if ( TARGET_GP_DIRECT ) builtin_define ( "__NDS32_GP_DIRECT__" ) ; if ( TARGET_VH ) builtin_define ( "__NDS32_VH__" ) ; if ( TARGET_BIG_ENDIAN ) builtin_define ( "__big_endian__" ) ; builtin_assert ( "cpu=nds32" ) ; builtin_assert ( "machine=nds32" ) ; if ( TARGET_HARD_FLOAT ) builtin_define ( "__NDS32_ABI_2FP_PLUS" ) ; else builtin_define ( "__NDS32_ABI_2" ) ; } </s>


<s> static void microblaze_machine_dependent_reorg ( void ) { if ( TARGET_PREFETCH ) { compute_bb_for_insn ( ) ; loop_optimizer_init ( AVOID_CFG_MODIFICATIONS ) ; shorten_branches ( get_insns ( ) ) ; insert_wic ( ) ; loop_optimizer_finalize ( ) ; free_bb_for_insn ( ) ; return ; } } </s>

The reorg function defined through the macro TARGET_MACHINE_DEPENDENT_REORG .


<s>
bool
AArch64InstrInfo
::
isFPRCopy
(
const
MachineInstr
*
MI
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
TargetOpcode
::
COPY
:
{
unsigned
DstReg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
return
(
AArch64
::
FPR64RegClass
.
contains
(
DstReg
)
||
AArch64
::
FPR128RegClass
.
contains
(
DstReg
)
)
;
}
case
AArch64
::
ORRv16i8
:
if
(
MI
->
getOperand
(
1
)
.
getReg
(
)
==
MI
->
getOperand
(
2
)
.
getReg
(
)
)
{
assert
(
MI
->
getDesc
(
)
.
getNumOperands
(
)
==
3
&&
MI
->
getOperand
(
0
)
.
isReg
(
)
&&
"invalid ORRv16i8 operands"
)
;
return
true
;
}
}
return
false
;
}
</s>

Does this instruction rename an FPR without modifying bits ?


<s> static void moxie_print_operand_address ( FILE * file , machine_mode , rtx x ) { switch ( GET_CODE ( x ) ) { case REG : fprintf ( file , "(%s)" , reg_names [ REGNO ( x ) ] ) ; break ; case PLUS : switch ( GET_CODE ( XEXP ( x , 1 ) ) ) { case CONST_INT : fprintf ( file , "%ld(%s)" , INTVAL ( XEXP ( x , 1 ) ) , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; break ; case SYMBOL_REF : output_addr_const ( file , XEXP ( x , 1 ) ) ; fprintf ( file , "(%s)" , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; break ; case CONST : { rtx plus = XEXP ( XEXP ( x , 1 ) , 0 ) ; if ( GET_CODE ( XEXP ( plus , 0 ) ) == SYMBOL_REF && CONST_INT_P ( XEXP ( plus , 1 ) ) ) { output_addr_const ( file , XEXP ( plus , 0 ) ) ; fprintf ( file , "+%ld(%s)" , INTVAL ( XEXP ( plus , 1 ) ) , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; } else abort ( ) ; } break ; default : abort ( ) ; } break ; default : output_addr_const ( file , x ) ; break ; } } </s>


<s> bool AMDGPUTargetLowering :: isLoadBitCastBeneficial ( EVT LoadTy , EVT CastTy , const SelectionDAG & DAG , const MachineMemOperand & MMO ) const { assert ( LoadTy . getSizeInBits ( ) == CastTy . getSizeInBits ( ) ) ; if ( LoadTy . getScalarType ( ) == MVT :: i32 ) return false ; unsigned LScalarSize = LoadTy . getScalarSizeInBits ( ) ; unsigned CastScalarSize = CastTy . getScalarSizeInBits ( ) ; if ( ( LScalarSize >= CastScalarSize ) && ( CastScalarSize < 32 ) ) return false ; bool Fast = false ; return allowsMemoryAccessForAlignment ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , CastTy , MMO , & Fast ) && Fast ; } </s>

Return true if the following transform is beneficial : fold ( conv ( load x ) ) - > ( load ( conv * ) x ) On architectures that do n't natively support some vector loads efficiently , casting the load to a smaller vector of larger types and loading is more efficient , however , this can be undone by optimizations in dag combiner .


<s> BitVector Cpu0RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t ReservedCPURegs [ ] = { Cpu0 :: ZERO , Cpu0 :: AT , Cpu0 :: SP , Cpu0 :: LR , Cpu0 :: PC } ; BitVector Reserved ( getNumRegs ( ) ) ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; if ( MF . getSubtarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) ) { Reserved . set ( Cpu0 :: FP ) ; } const Cpu0FunctionInfo * Cpu0FI = MF . getInfo < Cpu0FunctionInfo > ( ) ; if ( Cpu0FI -> globalBaseRegFixed ( ) ) Reserved . set ( Cpu0 :: GP ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool RISCVTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; Optional < unsigned > FirstMaskArgument ; if ( Subtarget . hasVInstructions ( ) ) FirstMaskArgument = preAssignMask ( Outs ) ; for ( unsigned i = 0 , e = Outs . size ( ) ; i != e ; ++ i ) { MVT VT = Outs [ i ] . VT ; ISD :: ArgFlagsTy ArgFlags = Outs [ i ] . Flags ; RISCVABI :: ABI ABI = MF . getSubtarget < RISCVSubtarget > ( ) . getTargetABI ( ) ; if ( CC_RISCV ( MF . getDataLayout ( ) , ABI , i , VT , VT , CCValAssign :: Full , ArgFlags , CCInfo , true , true , nullptr , * this , FirstMaskArgument ) ) return false ; } return true ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .

RISCV RISCV ISD::OutputArg 16 0 ISD::ArgFlagsTy RISCVABI::ABI RISCV RISCV


<s> void GCNPassConfig :: addOptimizedRegAlloc ( ) { if ( OptExecMaskPreRA ) { insertPass ( & MachineSchedulerID , & SIOptimizeExecMaskingPreRAID ) ; insertPass ( & SIOptimizeExecMaskingPreRAID , & SIFormMemoryClausesID ) ; } else { insertPass ( & MachineSchedulerID , & SIFormMemoryClausesID ) ; } insertPass ( & PHIEliminationID , & SILowerControlFlowID , false ) ; insertPass ( & SILowerControlFlowID , & SIFixWWMLivenessID , false ) ; TargetPassConfig :: addOptimizedRegAlloc ( ) ; } </s>

addOptimizedRegAlloc - Add passes related to register allocation .


<s> static bool xstormy16_can_eliminate ( const int from , const int to ) { return ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true ) ; } </s>

Worker function for TARGET_CAN_ELIMINATE .


<s>
void
print
(
raw_ostream
&
OS
)
const
{
OS
<<
"MinSrc:"
<<
MinSrc
<<
", MaxSrc:"
<<
MaxSrc
<<
" {"
;
for
(
int
M
:
Mask
)
OS
<<
' '
<<
M
;
OS
<<
" }"
;
}
</s>

print - Print a debug representation of the operand to the given stream .


"%qs attribute only applies to functions"

Handle an `` trap_exit '' attribute ; arguments as in struct attribute_spec.handler .


"End of block construct with no start: "

"Block construct type mismatch, expected: "


<s>
MCOperand
M88kMCInstLower
::
lowerOperand
(
const
MachineOperand
&
MO
)
const
{
switch
(
MO
.
getType
(
)
)
{
case
MachineOperand
::
MO_Register
:
return
MCOperand
::
createReg
(
MO
.
getReg
(
)
)
;
case
MachineOperand
::
MO_Immediate
:
return
MCOperand
::
createImm
(
MO
.
getImm
(
)
)
;
case
MachineOperand
::
MO_MachineBasicBlock
:
case
MachineOperand
::
MO_GlobalAddress
:
case
MachineOperand
::
MO_ExternalSymbol
:
case
MachineOperand
::
MO_MCSymbol
:
case
MachineOperand
::
MO_JumpTableIndex
:
case
MachineOperand
::
MO_ConstantPoolIndex
:
case
MachineOperand
::
MO_BlockAddress
:
return
lowerSymbolOperand
(
MO
)
;
default
:
report_fatal_error
(
"Unexpected MachineOperand type."
)
;
}
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> bool NyuziDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintCode ) { default : return true ; case InlineAsm :: Constraint_m : if ( ! SelectADDRri ( Op , Op0 , Op1 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> void aarch64_split_compare_and_swap ( rtx operands [ ] ) { gcc_assert ( epilogue_completed ) ; rtx rval , mem , oldval , newval , scratch , x , model_rtx ; machine_mode mode ; bool is_weak ; rtx_code_label * label1 , * label2 ; enum memmodel model ; rval = operands [ 0 ] ; mem = operands [ 1 ] ; oldval = operands [ 2 ] ; newval = operands [ 3 ] ; is_weak = ( operands [ 4 ] != const0_rtx ) ; model_rtx = operands [ 5 ] ; scratch = operands [ 7 ] ; mode = GET_MODE ( mem ) ; model = memmodel_from_int ( INTVAL ( model_rtx ) ) ; bool strong_zero_p = ( ! is_weak && ! aarch64_track_speculation && oldval == const0_rtx && mode != TImode ) ; label1 = NULL ; if ( ! is_weak ) { label1 = gen_label_rtx ( ) ; emit_label ( label1 ) ; } label2 = gen_label_rtx ( ) ; if ( is_mm_sync ( model ) ) aarch64_emit_load_exclusive ( mode , rval , mem , GEN_INT ( MEMMODEL_RELAXED ) ) ; else aarch64_emit_load_exclusive ( mode , rval , mem , model_rtx ) ; if ( strong_zero_p ) x = gen_rtx_NE ( VOIDmode , rval , const0_rtx ) ; else { rtx cc_reg = aarch64_gen_compare_reg_maybe_ze ( NE , rval , oldval , mode ) ; x = gen_rtx_NE ( VOIDmode , cc_reg , const0_rtx ) ; } x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; aarch64_emit_store_exclusive ( mode , scratch , mem , newval , model_rtx ) ; if ( ! is_weak ) { if ( aarch64_track_speculation ) { rtx cc_reg = aarch64_gen_compare_reg ( NE , scratch , const0_rtx ) ; x = gen_rtx_NE ( GET_MODE ( cc_reg ) , cc_reg , const0_rtx ) ; } else x = gen_rtx_NE ( VOIDmode , scratch , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label1 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } else aarch64_gen_compare_reg ( NE , scratch , const0_rtx ) ; emit_label ( label2 ) ; if ( strong_zero_p ) aarch64_gen_compare_reg ( NE , rval , const0_rtx ) ; if ( is_mm_sync ( model ) ) aarch64_emit_post_barrier ( model ) ; } </s>


<s> DecodeStatus SystemZDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CS ) const { Size = 0 ; if ( Bytes . size ( ) < 2 ) return MCDisassembler :: Fail ; const uint8_t * Table ; if ( Bytes [ 0 ] < 0x40 ) { Size = 2 ; Table = DecoderTable16 ; } else if ( Bytes [ 0 ] < 0xc0 ) { Size = 4 ; Table = DecoderTable32 ; } else { Size = 6 ; Table = DecoderTable48 ; } if ( Bytes . size ( ) < Size ) return MCDisassembler :: Fail ; uint64_t Inst = 0 ; for ( uint64_t I = 0 ; I < Size ; ++ I ) Inst = ( Inst << 8 ) | Bytes [ I ] ; return decodeInstruction ( Table , MI , Inst , Address , this , STI ) ; } </s>

Returns the disassembly of a single instruction .


<s> const TargetRegisterClass * HexagonRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & Hexagon :: IntRegsRegClass ; } </s>


<s> const uint32_t * AArch64RegisterInfo :: getNoPreservedMask ( ) const { return CSR_AArch64_NoRegs_RegMask ; } </s>

Return a register mask that clobbers everything .


<s> static unsigned HOST_WIDE_INT s390_shift_truncation_mask ( machine_mode mode ) { return mode == DImode || mode == SImode ? 63 : 0 ; } </s>

Implement TARGET_SHIFT_TRUNCATION_MASK for integer shifts .


<s> static rtx riscv_split_integer ( HOST_WIDE_INT val , enum machine_mode mode ) { unsigned HOST_WIDE_INT loval = sext_hwi ( val , 32 ) ; unsigned HOST_WIDE_INT hival = sext_hwi ( ( val - loval ) >> 32 , 32 ) ; rtx hi = gen_reg_rtx ( mode ) , lo = gen_reg_rtx ( mode ) ; riscv_move_integer ( hi , hi , hival ) ; riscv_move_integer ( lo , lo , loval ) ; hi = gen_rtx_fmt_ee ( ASHIFT , mode , hi , GEN_INT ( 32 ) ) ; hi = force_reg ( mode , hi ) ; return gen_rtx_fmt_ee ( PLUS , mode , hi , lo ) ; } </s>

Try to split a 64b integer into 32b parts , then reassemble .


<s> SDValue MipsSETargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: LOAD : return lowerLOAD ( Op , DAG ) ; case ISD :: STORE : return lowerSTORE ( Op , DAG ) ; case ISD :: SMUL_LOHI : return lowerMulDiv ( Op , MipsISD :: Mult , true , true , DAG ) ; case ISD :: UMUL_LOHI : return lowerMulDiv ( Op , MipsISD :: Multu , true , true , DAG ) ; case ISD :: MULHS : return lowerMulDiv ( Op , MipsISD :: Mult , false , true , DAG ) ; case ISD :: MULHU : return lowerMulDiv ( Op , MipsISD :: Multu , false , true , DAG ) ; case ISD :: MUL : return lowerMulDiv ( Op , MipsISD :: Mult , true , false , DAG ) ; case ISD :: SDIVREM : return lowerMulDiv ( Op , MipsISD :: DivRem , true , true , DAG ) ; case ISD :: UDIVREM : return lowerMulDiv ( Op , MipsISD :: DivRemU , true , true , DAG ) ; case ISD :: INTRINSIC_WO_CHAIN : return lowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case ISD :: INTRINSIC_W_CHAIN : return lowerINTRINSIC_W_CHAIN ( Op , DAG ) ; case ISD :: INTRINSIC_VOID : return lowerINTRINSIC_VOID ( Op , DAG ) ; } return MipsTargetLowering :: LowerOperation ( Op , DAG ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::LOAD ISD::STORE ISD::SMUL_LOHI MipsISD::Mult ISD::UMUL_LOHI MipsISD::Multu ISD::MULHS MipsISD::Mult ISD::MULHU MipsISD::Multu ISD::MUL MipsISD::Mult ISD::SDIVREM MipsISD::DivRem ISD::UDIVREM MipsISD::DivRemU ISD::INTRINSIC_WO_CHAIN ISD::INTRINSIC_W_CHAIN ISD::INTRINSIC_VOID Mips


<s> SDValue AMDGPUTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( N ) ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: MUL : { EVT VT = N -> getValueType ( 0 ) ; SDValue N0 = N -> getOperand ( 0 ) ; SDValue N1 = N -> getOperand ( 1 ) ; SDValue Mul ; if ( VT . isVector ( ) || VT . getSizeInBits ( ) > 32 ) break ; if ( Subtarget -> hasMulU24 ( ) && isU24 ( N0 , DAG ) && isU24 ( N1 , DAG ) ) { N0 = DAG . getZExtOrTrunc ( N0 , DL , MVT :: i32 ) ; N1 = DAG . getZExtOrTrunc ( N1 , DL , MVT :: i32 ) ; Mul = DAG . getNode ( AMDGPUISD :: MUL_U24 , DL , MVT :: i32 , N0 , N1 ) ; } else if ( Subtarget -> hasMulI24 ( ) && isI24 ( N0 , DAG ) && isI24 ( N1 , DAG ) ) { N0 = DAG . getSExtOrTrunc ( N0 , DL , MVT :: i32 ) ; N1 = DAG . getSExtOrTrunc ( N1 , DL , MVT :: i32 ) ; Mul = DAG . getNode ( AMDGPUISD :: MUL_I24 , DL , MVT :: i32 , N0 , N1 ) ; } else { break ; } SDValue Reg = DAG . getSExtOrTrunc ( Mul , DL , VT ) ; return Reg ; } case AMDGPUISD :: MUL_I24 : case AMDGPUISD :: MUL_U24 : { SDValue N0 = N -> getOperand ( 0 ) ; SDValue N1 = N -> getOperand ( 1 ) ; simplifyI24 ( N0 , DCI ) ; simplifyI24 ( N1 , DCI ) ; return SDValue ( ) ; } } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> void aarch64_expand_vector_init ( rtx target , rtx vals ) { machine_mode mode = GET_MODE ( target ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; int n_elts = GET_MODE_NUNITS ( mode ) ; int n_var = 0 , one_var = - 1 ; bool all_same = true ; rtx x , mem ; int i ; x = XVECEXP ( vals , 0 , 0 ) ; if ( ! CONST_INT_P ( x ) && ! CONST_DOUBLE_P ( x ) ) n_var = 1 , one_var = 0 ; for ( i = 1 ; i < n_elts ; ++ i ) { x = XVECEXP ( vals , 0 , i ) ; if ( ! CONST_INT_P ( x ) && ! CONST_DOUBLE_P ( x ) ) ++ n_var , one_var = i ; if ( ! rtx_equal_p ( x , XVECEXP ( vals , 0 , 0 ) ) ) all_same = false ; } if ( n_var == 0 ) { rtx constant = aarch64_simd_make_constant ( vals ) ; if ( constant != NULL_RTX ) { emit_move_insn ( target , constant ) ; return ; } } if ( all_same ) { x = copy_to_mode_reg ( inner_mode , XVECEXP ( vals , 0 , 0 ) ) ; aarch64_emit_move ( target , gen_rtx_VEC_DUPLICATE ( mode , x ) ) ; return ; } if ( n_var == 1 ) { rtx copy = copy_rtx ( vals ) ; rtx index = GEN_INT ( one_var ) ; enum insn_code icode ; XVECEXP ( copy , 0 , one_var ) = XVECEXP ( vals , 0 , one_var ^ 1 ) ; aarch64_expand_vector_init ( target , copy ) ; x = copy_to_mode_reg ( inner_mode , XVECEXP ( vals , 0 , one_var ) ) ; icode = optab_handler ( vec_set_optab , mode ) ; gcc_assert ( icode != CODE_FOR_nothing ) ; emit_insn ( GEN_FCN ( icode ) ( target , x , index ) ) ; return ; } mem = assign_stack_temp ( mode , GET_MODE_SIZE ( mode ) ) ; for ( i = 0 ; i < n_elts ; i ++ ) emit_move_insn ( adjust_address_nv ( mem , inner_mode , i * GET_MODE_SIZE ( inner_mode ) ) , XVECEXP ( vals , 0 , i ) ) ; emit_move_insn ( target , mem ) ; } </s>

Expand a vector initialisation sequence , such that TARGET is initialised to contain VALS .


<s> static inline int andcosts ( rtx x ) { int i ; if ( GET_CODE ( XEXP ( x , 1 ) ) != CONST_INT ) return 1 ; i = INTVAL ( XEXP ( x , 1 ) ) ; if ( TARGET_SHMEDIA ) { if ( ( GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT && CONST_OK_FOR_I16 ( INTVAL ( XEXP ( x , 1 ) ) ) ) || EXTRA_CONSTRAINT_C16 ( XEXP ( x , 1 ) ) ) return 1 ; else return 2 ; } if ( i == 0xff || i == 0xffff ) return 1 ; if ( CONST_OK_FOR_K08 ( i ) ) return 2 ; if ( CONST_OK_FOR_I08 ( i ) ) return 2 ; return 3 ; } </s>


<s> bool RISCVFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
static
const
char
*
avr_out_movhi_r_mr_reg_no_disp_tiny
(
rtx_insn
*
insn
,
rtx
op
[
]
,
int
*
plen
)
{
rtx
dest
=
op
[
0
]
;
rtx
src
=
op
[
1
]
;
rtx
base
=
XEXP
(
src
,
0
)
;
int
reg_dest
=
true_regnum
(
dest
)
;
int
reg_base
=
true_regnum
(
base
)
;
if
(
reg_dest
==
reg_base
)
return
avr_asm_len
(
"ld __tmp_reg__,%1+"
CR_TAB
"ld %B0,%1"
CR_TAB
"mov %A0,__tmp_reg__"
,
op
,
plen
,
3
)
;
avr_asm_len
(
"ld %A0,%1+"
CR_TAB
"ld %B0,%1"
,
op
,
plen
,
2
)
;
if
(
!
reg_unused_after
(
insn
,
base
)
)
avr_asm_len
(
TINY_SBIW
(
%
E1
,
%
F1
,
1
)
,
op
,
plen
,
2
)
;
return
""
;
}
</s>

Same as movhi_r_mr , but TINY does not have ADIW , SBIW and LDD


<s> void TPCInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << StringRef ( getRegisterName ( RegNo ) ) . lower ( ) ; } </s>


<s> bool isToken ( ) const { return Kind == k_Token ; } </s>


<s> bool Z80RegisterInfo :: needsFrameBaseReg ( MachineInstr * MI , int64_t Offset ) const { const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; return ! isFrameOffsetLegal ( MI , getFrameRegister ( MF ) , Offset ) ; } </s>

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


"expand_builtin_saveregs: offset from ap = %d\n"

If defined , is a C expression that produces the machine-specific code for a call to ` __builtin_saveregs ' . This code will be moved to the very beginning of the function , before any parameter access are made . The return value of this function should be an RTX that contains the value to use as the return of ` __builtin_saveregs ' . If this macro is not defined , the compiler will output an ordinary call to the library function ` __builtin_saveregs ' .


"Alloca should always return a pointer."

Emit an alloca address in a register using target-specific logic .


<s> bool shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) override { switch ( ( VE :: Fixups ) Fixup . getKind ( ) ) { default : return false ; case VE :: fixup_ve_tls_gd_hi32 : case VE :: fixup_ve_tls_gd_lo32 : case VE :: fixup_ve_tpoff_hi32 : case VE :: fixup_ve_tpoff_lo32 : return true ; } } </s>

Hook to check if a relocation is needed for some target specific reason .


Check whether or not the given MBB can be used as a epilogue for the target .


<s> bool PPCTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { if ( ! VT . isSimple ( ) || ! Subtarget . hasVSX ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case MVT :: f32 : case MVT :: f64 : if ( Subtarget . hasPrefixInstrs ( ) ) { APFloat APFloatOfImm = Imm ; return convertToNonDenormSingle ( APFloatOfImm ) ; } LLVM_FALLTHROUGH ; case MVT :: ppcf128 : return Imm . isPosZero ( ) ; } } </s>

Returns true if the target can instruction select the specified FP immediate natively .


Output indirect call insns . WHICH is 0 for tocsave , 1 for plt16_ha , 2 for plt16_lo , 3 for mtctr .


<s> bool enableMachineScheduler ( ) const override { return true ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Z80 Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool DirectXTargetMachine :: addPassesToEmitFile ( PassManagerBase & PM , raw_pwrite_stream & Out , raw_pwrite_stream * DwoOut , CodeGenFileType FileType , bool DisableVerify , MachineModuleInfoWrapperPass * MMIWP ) { PM . add ( createDXILPrepareModulePass ( ) ) ; switch ( FileType ) { case CGFT_AssemblyFile : PM . add ( createPrintModulePass ( Out , "" , true ) ) ; break ; case CGFT_ObjectFile : PM . add ( createBitcodeWriterPass ( Out , true , false , false ) ) ; break ; case CGFT_Null : break ; } return false ; } </s>

Add passes to the specified pass manager to get the specified file emitted .


runOnMachineFunction - Emit the function body .


<s> bool KudeyarTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { EVT VT ; if ( N -> getOpcode ( ) == ISD :: LOAD ) { LoadSDNode * LD = cast < LoadSDNode > ( N ) ; VT = LD -> getMemoryVT ( ) ; } else if ( N -> getOpcode ( ) == ISD :: STORE ) { StoreSDNode * ST = cast < StoreSDNode > ( N ) ; VT = ST -> getMemoryVT ( ) ; } else return false ; if ( VT != MVT :: i8 && VT != MVT :: i16 && VT != MVT :: i32 ) return false ; if ( Op -> getOpcode ( ) != ISD :: ADD ) return false ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ) { uint64_t RHSC = RHS -> getZExtValue ( ) ; if ( ( VT == MVT :: i32 && RHSC != 4 ) || ( VT == MVT :: i16 && RHSC != 2 ) || ( VT == MVT :: i8 && RHSC != 1 ) ) return false ; Base = Op -> getOperand ( 0 ) ; Offset = DAG . getConstant ( RHSC , VT ) ; AM = ISD :: POST_INC ; return true ; } return false ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .


<s> static HARD_REG_SET sparc_zero_call_used_regs ( HARD_REG_SET need_zeroed_hardregs ) { for ( unsigned int regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( TEST_HARD_REG_BIT ( need_zeroed_hardregs , regno ) ) { if ( regno >= SPARC_FCC_REG || ( regno >= SPARC_FIRST_FP_REG && ! TARGET_VIS ) ) CLEAR_HARD_REG_BIT ( need_zeroed_hardregs , regno ) ; else if ( regno >= SPARC_FIRST_V9_FP_REG && ( regno & 1 ) ) ; else { machine_mode mode ; rtx reg ; if ( regno < SPARC_FIRST_FP_REG ) { reg = regno_reg_rtx [ regno ] ; mode = GET_MODE ( reg ) ; } else { mode = regno < SPARC_FIRST_V9_FP_REG ? SFmode : DFmode ; reg = gen_raw_REG ( mode , regno ) ; } emit_move_insn ( reg , CONST0_RTX ( mode ) ) ; } } return need_zeroed_hardregs ; } </s>

Implement TARGET_ZERO_CALL_USED_REGS . Generate a sequence of instructions that zero registers specified by NEED_ZEROED_HARDREGS . Return the ZEROED_HARDREGS that are actually zeroed .


<s> static bool branch_needs_nop_p ( rtx_insn * insn ) { rtx_insn * jump_insn ; if ( dbr_sequence_length ( ) ) return FALSE ; jump_insn = next_active_insn ( JUMP_LABEL ( insn ) ) ; while ( insn ) { insn = next_active_insn ( insn ) ; if ( ! insn || jump_insn == insn ) return TRUE ; if ( ! ( GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT || extract_asm_operands ( PATTERN ( insn ) ) != NULL_RTX ) && get_attr_length ( insn ) > 0 ) break ; } return FALSE ; } </s>

Return TRUE if INSN , a forward jump insn , needs a nop in its delay slot . This occurs when INSN has an unfilled delay slot and is followed by an asm . Disaster can occur if the asm is empty and the jump branches into the delay slot . So , we add a nop in the delay slot when this occurs .


<s> virtual const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> void ARMAsmPrinter :: emitEndOfAsmFile ( Module & M ) { const Triple & TT = TM . getTargetTriple ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; emitAlignment ( Align ( 4 ) ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( * OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } Stubs = MMIMacho . GetThreadLocalGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFMacho . getThreadLocalPointerSection ( ) ) ; emitAlignment ( Align ( 4 ) ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( * OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } OutStreamer -> emitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } MCTargetStreamer & TS = * OutStreamer -> getTargetStreamer ( ) ; ARMTargetStreamer & ATS = static_cast < ARMTargetStreamer & > ( TS ) ; if ( OptimizationGoals > 0 && ( Subtarget -> isTargetAEABI ( ) || Subtarget -> isTargetGNUAEABI ( ) || Subtarget -> isTargetMuslAEABI ( ) ) ) ATS . emitAttribute ( ARMBuildAttrs :: ABI_optimization_goals , OptimizationGoals ) ; OptimizationGoals = - 1 ; ATS . finishAttributeSection ( ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> bool PTXAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { SetupMachineFunction ( MF ) ; EmitFunctionDeclaration ( ) ; EmitFunctionBody ( ) ; return false ; } </s>


<s> int arc_adjust_insn_length ( rtx_insn * insn , int len , bool ) { if ( ! INSN_P ( insn ) ) return len ; if ( GET_CODE ( PATTERN ( insn ) ) == SEQUENCE ) return len ; if ( TARGET_PAD_RETURN && JUMP_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) != ADDR_VEC && GET_CODE ( PATTERN ( insn ) ) != ADDR_DIFF_VEC && get_attr_type ( insn ) == TYPE_RETURN ) { rtx_insn * prev = prev_active_insn ( insn ) ; if ( ! prev || ! ( prev = prev_active_insn ( prev ) ) || ( ( NONJUMP_INSN_P ( prev ) && GET_CODE ( PATTERN ( prev ) ) == SEQUENCE ) ? CALL_ATTR ( as_a < rtx_sequence * > ( PATTERN ( prev ) ) -> insn ( 0 ) , NON_SIBCALL ) : CALL_ATTR ( prev , NON_SIBCALL ) ) ) return len + 4 ; } if ( TARGET_ARC600 ) { rtx_insn * succ = next_real_insn ( insn ) ; if ( succ && INSN_P ( succ ) ) len += arc600_corereg_hazard ( insn , succ ) ; } extract_constrain_insn_cached ( insn ) ; return len ; } </s>


"FP elimination on a non-leaf function is not supported"


<s> void BPFPassConfig :: addMachineSSAOptimization ( ) { TargetPassConfig :: addMachineSSAOptimization ( ) ; const BPFSubtarget * Subtarget = getBPFTargetMachine ( ) . getSubtargetImpl ( ) ; if ( Subtarget -> getHasAlu32 ( ) && ! DisableMIPeephole ) addPass ( createBPFMIPeepholePass ( ) ) ; } </s>

Methods with trivial inline returns are convenient points in the common codegen pass pipeline where targets may insert passes .


"option %s is not supported together with %<-fopenacc%>"

Issue a diagnostic when option OPTNAME is enabled ( as indicated by OPTVAL ) and -fopenacc is also enabled .


<s> static bool aarch64_evpc_rev_global ( struct expand_vec_perm_d * d ) { poly_uint64 nelt = d -> perm . length ( ) ; if ( ! d -> one_vector_p || d -> vec_flags == VEC_ADVSIMD ) return false ; if ( ! d -> perm . series_p ( 0 , 1 , nelt - 1 , - 1 ) ) return false ; if ( d -> testing_p ) return true ; rtx src = gen_rtx_UNSPEC ( d -> vmode , gen_rtvec ( 1 , d -> op0 ) , UNSPEC_REV ) ; emit_set_insn ( d -> target , src ) ; return true ; } </s>

Recognize patterns for the REV insn , which reverses elements within a full vector .


<s> static void xstormy16_encode_section_info ( tree decl , rtx r , int first ) { default_encode_section_info ( decl , r , first ) ; if ( TREE_CODE ( decl ) == VAR_DECL && ( lookup_attribute ( "below100" , DECL_ATTRIBUTES ( decl ) ) || lookup_attribute ( "BELOW100" , DECL_ATTRIBUTES ( decl ) ) ) ) { rtx symbol = XEXP ( r , 0 ) ; gcc_assert ( GET_CODE ( symbol ) == SYMBOL_REF ) ; SYMBOL_REF_FLAGS ( symbol ) |= SYMBOL_FLAG_XSTORMY16_BELOW100 ; } } </s>


<s> void PIC16RegisterInfo :: emitPrologue ( MachineFunction & MF ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> uint64_t getFeatures ( ) const { return Features ; } </s>

Returns the vector of individual subtarget features .


<s>
bool
SIInstrInfo
::
isInlineConstant
(
const
MachineOperand
&
MO
,
uint8_t
OperandType
)
const
{
if
(
!
MO
.
isImm
(
)
||
OperandType
<
AMDGPU
::
OPERAND_SRC_FIRST
||
OperandType
>
AMDGPU
::
OPERAND_SRC_LAST
)
return
false
;
int64_t
Imm
=
MO
.
getImm
(
)
;
switch
(
OperandType
)
{
case
AMDGPU
::
OPERAND_REG_IMM_INT32
:
case
AMDGPU
::
OPERAND_REG_IMM_FP32
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_INT32
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_FP32
:
{
int32_t
Trunc
=
static_cast
<
int32_t
>
(
Imm
)
;
return
Trunc
==
Imm
&&
AMDGPU
::
isInlinableLiteral32
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
case
AMDGPU
::
OPERAND_REG_IMM_INT64
:
case
AMDGPU
::
OPERAND_REG_IMM_FP64
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_INT64
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_FP64
:
{
return
AMDGPU
::
isInlinableLiteral64
(
MO
.
getImm
(
)
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
case
AMDGPU
::
OPERAND_REG_IMM_INT16
:
case
AMDGPU
::
OPERAND_REG_IMM_FP16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_INT16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_FP16
:
{
if
(
isInt
<
16
>
(
Imm
)
||
isUInt
<
16
>
(
Imm
)
)
{
int16_t
Trunc
=
static_cast
<
int16_t
>
(
Imm
)
;
return
ST
.
has16BitInsts
(
)
&&
AMDGPU
::
isInlinableLiteral16
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
return
false
;
}
case
AMDGPU
::
OPERAND_REG_INLINE_C_V2INT16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_V2FP16
:
{
uint32_t
Trunc
=
static_cast
<
uint32_t
>
(
Imm
)
;
return
AMDGPU
::
isInlinableLiteralV216
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
default
:
llvm_unreachable
(
"invalid bitwidth"
)
;
}
}
</s>

returns true if the operand OpIdx in MI is a valid inline immediate .


<s> unsigned HexagonRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const HexagonFrameLowering * TFI = getFrameLowering ( MF ) ; if ( TFI -> hasFP ( MF ) ) return Hexagon :: R30 ; return Hexagon :: R29 ; } </s>


<s> void TVMPassConfig :: addPreRegAlloc ( ) { addPass ( createTVMContinuationsHoist ( ) ) ; TargetPassConfig :: addPreRegAlloc ( ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


"For each split Type there should be exactly one VReg."

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


"SVE requires vector length in multiples of 128!"

"Minimum SVE vector size should not be larger than its maximum!"

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


This is just a placeholder to make linking work without having to add this to the generic Darwin EXTRA_SECTIONS . If -mcall-aix is ever needed for Darwin ( not too likely ! ) this would have to get a real definition .


<s> bool SIInstrInfo :: usesConstantBus ( const MachineRegisterInfo & MRI , const MachineOperand & MO , unsigned OpSize ) const { if ( isLiteralConstant ( MO , OpSize ) ) return true ; if ( ! MO . isReg ( ) || ! MO . isUse ( ) ) return false ; if ( TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) return RI . isSGPRClass ( MRI . getRegClass ( MO . getReg ( ) ) ) ; if ( ! MO . isImplicit ( ) && ( MO . getReg ( ) == AMDGPU :: FLAT_SCR ) ) return true ; if ( ! MO . isImplicit ( ) && MO . getReg ( ) == AMDGPU :: EXEC ) return true ; if ( MO . getReg ( ) == AMDGPU :: M0 || MO . getReg ( ) == AMDGPU :: VCC || ( ! MO . isImplicit ( ) && ( AMDGPU :: SGPR_32RegClass . contains ( MO . getReg ( ) ) || AMDGPU :: SGPR_64RegClass . contains ( MO . getReg ( ) ) ) ) ) { return true ; } return false ; } </s>

Returns true if this operand uses the constant bus .


<s> bool isStack ( ) const { return type == RAInfo :: LocType :: Stack ; } </s>


<s>
void
arm_output_multireg_pop
(
rtx
*
operands
,
bool
return_pc
,
rtx
cond
,
bool
reverse
,
bool
update
)
{
int
i
;
char
pattern
[
100
]
;
int
offset
;
const
char
*
conditional
;
int
num_saves
=
XVECLEN
(
operands
[
0
]
,
0
)
;
unsigned
int
regno
;
unsigned
int
regno_base
=
REGNO
(
operands
[
1
]
)
;
offset
=
0
;
offset
+=
update
1
:
0
;
offset
+=
return_pc
1
:
0
;
for
(
i
=
offset
;
i
<
num_saves
;
i
++
)
{
regno
=
REGNO
(
XEXP
(
XVECEXP
(
operands
[
0
]
,
0
,
i
)
,
0
)
)
;
gcc_assert
(
(
regno
!=
SP_REGNUM
)
||
(
regno_base
==
SP_REGNUM
)
)
;
if
(
regno
==
regno_base
)
gcc_assert
(
!
update
)
;
}
conditional
=
reverse
"%?%D0"
:
"%?%d0"
;
if
(
(
regno_base
==
SP_REGNUM
)
&&
update
)
{
sprintf
(
pattern
,
"pop%s\t{"
,
conditional
)
;
}
else
{
if
(
regno_base
==
SP_REGNUM
)
sprintf
(
pattern
,
"ldmfd%s"
,
conditional
)
;
if
(
update
)
sprintf
(
pattern
,
"ldmia%s\t"
,
conditional
)
;
else
sprintf
(
pattern
,
"ldm%s\t"
,
conditional
)
;
strcat
(
pattern
,
reg_names
[
regno_base
]
)
;
if
(
update
)
strcat
(
pattern
,
"!, {"
)
;
else
strcat
(
pattern
,
", {"
)
;
}
strcat
(
pattern
,
reg_names
[
REGNO
(
XEXP
(
XVECEXP
(
operands
[
0
]
,
0
,
offset
)
,
0
)
)
]
)
;
for
(
i
=
offset
+
1
;
i
<
num_saves
;
i
++
)
{
strcat
(
pattern
,
", "
)
;
strcat
(
pattern
,
reg_names
[
REGNO
(
XEXP
(
XVECEXP
(
operands
[
0
]
,
0
,
i
)
,
0
)
)
]
)
;
}
strcat
(
pattern
,
"}"
)
;
if
(
IS_INTERRUPT
(
arm_current_func_type
(
)
)
&&
return_pc
)
strcat
(
pattern
,
"^"
)
;
output_asm_insn
(
pattern
,
&
cond
)
;
}
</s>

OPERANDS [ 0 ] is the entire list of insns that constitute pop , OPERANDS [ 1 ] is the base register , RETURN_PC is true iff return insn is in the list , UPDATE is true iff the list contains explicit update of base register .


<s> static void arm_add_cfa_adjust_cfa_note ( rtx insn , int size , rtx dest , rtx src ) { rtx dwarf ; RTX_FRAME_RELATED_P ( insn ) = 1 ; dwarf = gen_rtx_SET ( VOIDmode , dest , plus_constant ( Pmode , src , size ) ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , dwarf ) ; } </s>

Add a REG_CFA_ADJUST_CFA REG note to INSN . SIZE is the offset to be adjusted . DEST and SRC might be stack_pointer_rtx or hard_frame_pointer_rtx .


<s> InstructionCost getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: TargetCostKind CostKind = TTI :: TCK_RecipThroughput , TTI :: OperandValueKind Opd1Info = TTI :: OK_AnyValue , TTI :: OperandValueKind Opd2Info = TTI :: OK_AnyValue , TTI :: OperandValueProperties Opd1PropInfo = TTI :: OP_None , TTI :: OperandValueProperties Opd2PropInfo = TTI :: OP_None , ArrayRef < const Value * > Args = ArrayRef < const Value * > ( ) , const Instruction * CxtI = nullptr ) { int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( ISD == ISD :: ADD && CostKind == TTI :: TCK_RecipThroughput ) return SCEVCheapExpansionBudget . getValue ( ) + 1 ; return BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; } </s>

This is an approximation of reciprocal throughput of a math/logic op .


"Unrecognized Hexagon processor version"

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> unsigned AArch64TargetLowering :: getVaListSizeInBits ( const DataLayout & DL ) const { if ( Subtarget -> isTargetDarwin ( ) || Subtarget -> isTargetWindows ( ) ) return getPointerTy ( DL ) . getSizeInBits ( ) ; return 3 * getPointerTy ( DL ) . getSizeInBits ( ) + 2 * 32 ; } </s>

Returns the size of the platform 's va_list object .


<s> unsigned SNESRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { return SNES :: Y ; } return SNES :: SP ; } </s>


"********* Hexagon Hardware Loops *********\n"

runOnMachineFunction - Emit the function body .


<s> bool GCNPassConfig :: addPreISel ( ) { AMDGPUPassConfig :: addPreISel ( ) ; const AMDGPUTargetMachine & TM = getAMDGPUTargetMachine ( ) ; addPass ( createAMDGPUAnnotateKernelFeaturesPass ( & TM ) ) ; addPass ( createStructurizeCFGPass ( true ) ) ; addPass ( createSinkingPass ( ) ) ; addPass ( createSITypeRewriter ( ) ) ; addPass ( createAMDGPUAnnotateUniformValues ( ) ) ; addPass ( createSIAnnotateControlFlowPass ( ) ) ; return false ; } </s>

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU SI AMDGPU SI


<s> static void rs6000_emit_prologue_move_from_cr ( rtx reg ) { if ( DEFAULT_ABI == ABI_ELFv2 && TARGET_MFCRF ) { int i , cr_reg [ 8 ] , count = 0 ; for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) cr_reg [ count ++ ] = i ; if ( count == 1 ) { rtvec p = rtvec_alloc ( 1 ) ; rtvec r = rtvec_alloc ( 2 ) ; RTVEC_ELT ( r , 0 ) = gen_rtx_REG ( CCmode , CR0_REGNO + cr_reg [ 0 ] ) ; RTVEC_ELT ( r , 1 ) = GEN_INT ( 1 << ( 7 - cr_reg [ 0 ] ) ) ; RTVEC_ELT ( p , 0 ) = gen_rtx_SET ( reg , gen_rtx_UNSPEC ( SImode , r , UNSPEC_MOVESI_FROM_CR ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , p ) ) ; return ; } } emit_insn ( gen_prologue_movesi_from_cr ( reg ) ) ; } </s>

Emit prologue code to store CR fields that need to be saved into REG . This function should only be called when moving the non-volatile CRs to REG , it is not a general purpose routine to move the entire set of CRs to REG . Specifically , gen_prologue_movesi_from_cr ( ) does not contain uses of the volatile CRs .


<s> void R600InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { unsigned VectorComponents = 0 ; if ( ( AMDGPU :: R600_Reg128RegClass . contains ( DestReg ) || AMDGPU :: R600_Reg128VerticalRegClass . contains ( DestReg ) ) && ( AMDGPU :: R600_Reg128RegClass . contains ( SrcReg ) || AMDGPU :: R600_Reg128VerticalRegClass . contains ( SrcReg ) ) ) { VectorComponents = 4 ; } else if ( ( AMDGPU :: R600_Reg64RegClass . contains ( DestReg ) || AMDGPU :: R600_Reg64VerticalRegClass . contains ( DestReg ) ) && ( AMDGPU :: R600_Reg64RegClass . contains ( SrcReg ) || AMDGPU :: R600_Reg64VerticalRegClass . contains ( SrcReg ) ) ) { VectorComponents = 2 ; } if ( VectorComponents > 0 ) { for ( unsigned I = 0 ; I < VectorComponents ; I ++ ) { unsigned SubRegIndex = RI . getSubRegFromChannel ( I ) ; buildDefaultInstruction ( MBB , MI , AMDGPU :: MOV , RI . getSubReg ( DestReg , SubRegIndex ) , RI . getSubReg ( SrcReg , SubRegIndex ) ) . addReg ( DestReg , RegState :: Define | RegState :: Implicit ) ; } } else { MachineInstr * NewMI = buildDefaultInstruction ( MBB , MI , AMDGPU :: MOV , DestReg , SrcReg ) ; NewMI -> getOperand ( getOperandIdx ( * NewMI , AMDGPU :: OpName :: src0 ) ) . setIsKill ( KillSrc ) ; } } </s>


<s> static void emit_load_locked ( machine_mode mode , rtx reg , rtx mem ) { gcc_assert ( mode == SImode ) ; emit_insn ( gen_load_locked_si ( reg , mem ) ) ; } </s>

A subroutine of the atomic operation splitters . Emit a load-locked instruction in MODE . For QI/HImode , possibly use a pattern than includes the zero_extend operation .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { ForCodeSize = MF . getFunction ( ) -> hasFnAttribute ( Attribute :: OptimizeForSize ) || MF . getFunction ( ) -> hasFnAttribute ( Attribute :: MinSize ) ; Subtarget = & MF . getSubtarget < WebAssemblySubtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>


<s> unsigned ARMBaseInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case ARM :: LDRrs : case ARM :: t2LDRs : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isReg ( ) && MI -> getOperand ( 3 ) . isImm ( ) && MI -> getOperand ( 2 ) . getReg ( ) == 0 && MI -> getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: LDRi12 : case ARM :: t2LDRi12 : case ARM :: tLDRspi : case ARM :: VLDRD : case ARM :: VLDRS : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VLD1q64Pseudo : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VLDMQIA : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> static bool arm_slowmul_rtx_costs ( rtx x , enum rtx_code code , enum rtx_code outer_code , int * total , bool speed ) { machine_mode mode = GET_MODE ( x ) ; if ( TARGET_THUMB ) { * total = thumb1_rtx_costs ( x , code , outer_code ) ; return true ; } switch ( code ) { case MULT : if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || mode == DImode ) { * total = COSTS_N_INSNS ( 20 ) ; return false ; } if ( CONST_INT_P ( XEXP ( x , 1 ) ) ) { unsigned HOST_WIDE_INT i = ( INTVAL ( XEXP ( x , 1 ) ) & ( unsigned HOST_WIDE_INT ) 0xffffffff ) ; int cost , const_ok = const_ok_for_arm ( i ) ; int j , booth_unit_size ; cost = const_ok ? 4 : 8 ; booth_unit_size = 2 ; for ( j = 0 ; i && j < 32 ; j += booth_unit_size ) { i >>= booth_unit_size ; cost ++ ; } * total = COSTS_N_INSNS ( cost ) ; * total += rtx_cost ( XEXP ( x , 0 ) , code , 0 , speed ) ; return true ; } * total = COSTS_N_INSNS ( 20 ) ; return false ; default : return arm_rtx_costs_1 ( x , outer_code , total , speed ) ; ; } } </s>

RTX costs for cores with a slow MUL implementation . Thumb-2 is not supported on any `` slowmul '' cores , so it can be ignored .


<s> bool SIInstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { return TargetInstrInfo :: isSchedulingBoundary ( MI , MBB , MF ) || MI . modifiesRegister ( AMDGPU :: EXEC , & RI ) || MI . getOpcode ( ) == AMDGPU :: S_SETREG_IMM32_B32 || MI . getOpcode ( ) == AMDGPU :: S_SETREG_B32 || MI . getOpcode ( ) == AMDGPU :: S_DENORM_MODE || changesVGPRIndexingMode ( MI ) ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasV8_1aOps ( false ) , HasFPARMv8 ( false ) , HasNEON ( false ) , HasCrypto ( false ) , HasCRC ( false ) , HasPerfMon ( false ) , HasZeroCycleRegMove ( false ) , HasZeroCycleZeroing ( false ) , StrictAlign ( false ) , ReserveX18 ( TT . isOSDarwin ( ) ) , IsLittle ( LittleEndian ) , CPUString ( CPU ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS ) ) , TSInfo ( ) , TLInfo ( TM , * this ) { } </s>

This constructor initializes the data members to match that of the specified triple .


<s> static void alpha_canonicalize_comparison ( int * code , rtx * op0 , rtx * op1 , bool op0_preserve_value ) { if ( ! op0_preserve_value && ( * code == GE || * code == GT || * code == GEU || * code == GTU ) && ( REG_P ( * op1 ) || * op1 == const0_rtx ) ) { std :: swap ( * op0 , * op1 ) ; * code = ( int ) swap_condition ( ( enum rtx_code ) * code ) ; } if ( ( * code == LT || * code == LTU ) && CONST_INT_P ( * op1 ) && INTVAL ( * op1 ) == 256 ) { * code = * code == LT ? LE : LEU ; * op1 = GEN_INT ( 255 ) ; } } </s>

Canonicalize a comparison from one we do n't have to one we do have .


"Basic block should contain at least a RET but is empty"


<s> enum nds32_16bit_address_type nds32_mem_format ( rtx op ) { machine_mode mode_test ; int val ; int regno ; if ( ! TARGET_16_BIT ) return ADDRESS_NOT_16BIT_FORMAT ; mode_test = GET_MODE ( op ) ; op = XEXP ( op , 0 ) ; if ( GET_CODE ( op ) == REG && ( mode_test == SImode ) ) return ADDRESS_REG ; if ( GET_CODE ( op ) == REG && ( REGNO ( op ) < R8_REGNUM ) ) return ADDRESS_LO_REG_IMM3U ; if ( ( GET_CODE ( op ) == POST_INC ) && ( mode_test == SImode ) ) { regno = REGNO ( XEXP ( op , 0 ) ) ; if ( regno < 8 ) return ADDRESS_POST_INC_LO_REG_IMM3U ; } if ( ( GET_CODE ( op ) == POST_MODIFY ) && ( mode_test == SImode ) && ( REG_P ( XEXP ( XEXP ( op , 1 ) , 0 ) ) ) && ( CONST_INT_P ( XEXP ( XEXP ( op , 1 ) , 1 ) ) ) ) { regno = REGNO ( XEXP ( XEXP ( op , 1 ) , 0 ) ) ; val = INTVAL ( XEXP ( XEXP ( op , 1 ) , 1 ) ) ; if ( regno < 8 && val < 32 ) return ADDRESS_POST_INC_LO_REG_IMM3U ; } if ( ( GET_CODE ( op ) == PLUS ) && ( GET_CODE ( XEXP ( op , 0 ) ) == REG ) && ( GET_CODE ( XEXP ( op , 1 ) ) == CONST_INT ) ) { val = INTVAL ( XEXP ( op , 1 ) ) ; regno = REGNO ( XEXP ( op , 0 ) ) ; if ( regno > 7 && regno != SP_REGNUM && regno != FP_REGNUM ) return ADDRESS_NOT_16BIT_FORMAT ; switch ( mode_test ) { case QImode : if ( val >= 0 && val < 8 && regno < 8 ) return ADDRESS_LO_REG_IMM3U ; break ; case HImode : if ( val >= 0 && val < 16 && ( val % 2 == 0 ) && regno < 8 ) return ADDRESS_LO_REG_IMM3U ; break ; case SImode : case SFmode : case DFmode : if ( ( regno == FP_REGNUM ) && ( val >= 0 && val < 512 && ( val % 4 == 0 ) ) ) return ADDRESS_FP_IMM7U ; else if ( ( regno == SP_REGNUM ) && ( val >= 0 && val < 512 && ( val % 4 == 0 ) ) ) return ADDRESS_SP_IMM7U ; else if ( val >= 0 && val < 32 && ( val % 4 == 0 ) && regno < 8 ) return ADDRESS_LO_REG_IMM3U ; break ; default : break ; } } return ADDRESS_NOT_16BIT_FORMAT ; } </s>

A helper function to return memory format .


<s> void RISCVFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; const TargetRegisterClass * RC = & RISCV :: GPRRegClass ; for ( int FI = MFI . getObjectIndexBegin ( ) , EFI = MFI . getObjectIndexEnd ( ) ; FI < EFI ; FI ++ ) { if ( MFI . getStackID ( FI ) == TargetStackID :: RISCVVector && ! MFI . isDeadObjectIndex ( FI ) ) RVFI -> setHasSpillVRs ( ) ; } if ( ! isInt < 11 > ( MFI . estimateStackSize ( MF ) ) ) { int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RegScavFI ) ; } } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .

RISCV RISCV RISCV RISCV::GPRRegClass RISCV 11


Generate RTL for 128-bit ( TImode ) subtraction with overflow . OP0 represents the TImode destination operand 0 LOW_DEST represents the low half ( DImode ) of TImode operand 0 LOW_IN1 represents the low half ( DImode ) of TImode operand 1 LOW_IN2 represents the low half ( DImode ) of TImode operand 2 HIGH_DEST represents the high half ( DImode ) of TImode operand 0 HIGH_IN1 represents the high half ( DImode ) of TImode operand 1 HIGH_IN2 represents the high half ( DImode ) of TImode operand 2 UNSIGNED_P is true if the operation is being performed on unsigned values .


<s> void mips_order_regs_for_local_alloc ( ) { register int i ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) reg_alloc_order [ i ] = i ; if ( TARGET_MIPS16 ) { reg_alloc_order [ 0 ] = 24 ; reg_alloc_order [ 24 ] = 0 ; } } </s>

On the mips16 , we want to allocate $ 24 ( T_REG ) before other registers for instructions for which it is possible . This helps avoid shuffling registers around in order to set up for an xor , encouraging the compiler to use a cmp instead .


<s> static const char * csky_mangle_type ( const_tree type ) { if ( TYPE_NAME ( type ) && TREE_CODE ( TYPE_NAME ( type ) ) == TYPE_DECL && DECL_NAME ( TYPE_NAME ( type ) ) && ! strcmp ( IDENTIFIER_POINTER ( DECL_NAME ( TYPE_NAME ( type ) ) ) , "__fp16" ) ) return "__fp16" ; return NULL ; } </s>


<s> void rs6000_call_darwin_1 ( rtx value , rtx func_desc , rtx tlsarg , rtx cookie , bool sibcall ) { rtx func = func_desc ; rtx func_addr ; rtx call [ 3 ] ; rtx insn ; int cookie_val = INTVAL ( cookie ) ; bool make_island = false ; if ( ( cookie_val & CALL_LONG ) != 0 && GET_CODE ( func_desc ) == SYMBOL_REF ) { if ( darwin_symbol_stubs && TARGET_32BIT ) make_island = true ; else { func = rs6000_longcall_ref ( func_desc , NULL_RTX ) ; cookie_val &= ~ CALL_LONG ; } } if ( GET_CODE ( func ) != SYMBOL_REF ) { func = force_reg ( Pmode , func ) ; func_addr = gen_rtx_REG ( Pmode , CTR_REGNO ) ; emit_move_insn ( func_addr , func ) ; } else func_addr = func ; call [ 0 ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_addr ) , tlsarg ) ; if ( value != NULL_RTX ) call [ 0 ] = gen_rtx_SET ( value , call [ 0 ] ) ; call [ 1 ] = gen_rtx_USE ( VOIDmode , GEN_INT ( cookie_val ) ) ; if ( sibcall ) call [ 2 ] = simple_return_rtx ; else call [ 2 ] = gen_hard_reg_clobber ( Pmode , LR_REGNO ) ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( 3 , call ) ) ; insn = emit_call_insn ( insn ) ; if ( make_island ) { tree funname = get_identifier ( XSTR ( func_desc , 0 ) ) ; if ( no_previous_def ( funname ) ) { rtx label_rtx = gen_label_rtx ( ) ; char * label_buf , temp_buf [ 256 ] ; ASM_GENERATE_INTERNAL_LABEL ( temp_buf , "L" , CODE_LABEL_NUMBER ( label_rtx ) ) ; label_buf = temp_buf [ 0 ] == '*' ? temp_buf + 1 : temp_buf ; tree labelname = get_identifier ( label_buf ) ; add_compiler_branch_island ( labelname , funname , insn_line ( ( const rtx_insn * ) insn ) ) ; } } } </s>

Expand code to perform a call under the Darwin ABI . Modulo handling of mlongcall , this is much the same as sysv . if/when the longcall optimisation is removed , we could drop this code and use the sysv case ( taking care to avoid the tls stuff ) . We can use this for sibcalls too , if needed .


<s> const MCPhysReg * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const ARMSubtarget & STI = MF -> getSubtarget < ARMSubtarget > ( ) ; bool UseSplitPush = STI . splitFramePushPop ( * MF ) ; const MCPhysReg * RegList = STI . isTargetDarwin ( ) ? CSR_iOS_SaveList : ( UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList ) ; const Function & F = MF -> getFunction ( ) ; if ( F . getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F . getCallingConv ( ) == CallingConv :: CFGuard_Check ) { return CSR_Win_AAPCS_CFGuard_Check_SaveList ; } else if ( F . hasFnAttribute ( "interrupt" ) ) { if ( STI . isMClass ( ) ) { return UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList ; } else if ( F . getFnAttribute ( "interrupt" ) . getValueAsString ( ) == "FIQ" ) { return CSR_FIQ_SaveList ; } else { return CSR_GenericInt_SaveList ; } } if ( STI . getTargetLowering ( ) -> supportSwiftError ( ) && F . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) { if ( STI . isTargetDarwin ( ) ) return CSR_iOS_SwiftError_SaveList ; return UseSplitPush ? CSR_AAPCS_SplitPush_SwiftError_SaveList : CSR_AAPCS_SwiftError_SaveList ; } if ( STI . isTargetDarwin ( ) && F . getCallingConv ( ) == CallingConv :: CXX_FAST_TLS ) return MF -> getInfo < ARMFunctionInfo > ( ) -> isSplitCSR ( ) ? CSR_iOS_CXX_TLS_PE_SaveList : CSR_iOS_CXX_TLS_SaveList ; return RegList ; } </s>

ARM ARM ARM ARM "interrupt" "interrupt" "FIQ" ARM


"scheduler moved pseudo-terminator instruction"


"WebAssembly hasn't implemented computed gotos"

"WebAssembly hasn't implemented __builtin_return_address"

LowerOperation - Provide custom lowering hooks for some operations .


<s> unsigned WebAssemblyTTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo ) { unsigned Cost = BasicTTIImplBase < WebAssemblyTTIImpl > :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( VectorType * VTy = dyn_cast < VectorType > ( Ty ) ) { switch ( Opcode ) { case Instruction :: LShr : case Instruction :: AShr : case Instruction :: Shl : if ( Opd2Info != TTI :: OK_UniformValue && Opd2Info != TTI :: OK_UniformConstantValue ) Cost = VTy -> getNumElements ( ) * ( TargetTransformInfo :: TCC_Basic + getArithmeticInstrCost ( Opcode , VTy -> getElementType ( ) ) + TargetTransformInfo :: TCC_Basic ) ; break ; } } return Cost ; } </s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> static void arm_setup_incoming_varargs ( CUMULATIVE_ARGS * cum , enum machine_mode mode ATTRIBUTE_UNUSED , tree type ATTRIBUTE_UNUSED , int * pretend_size , int second_time ATTRIBUTE_UNUSED ) { cfun -> machine -> uses_anonymous_args = 1 ; if ( cum -> nregs < NUM_ARG_REGS ) * pretend_size = ( NUM_ARG_REGS - cum -> nregs ) * UNITS_PER_WORD ; } </s>

Worker function for TARGET_SETUP_INCOMING_VARARGS . On the ARM , PRETEND_SIZE is set in order to have the prologue push the last named arg and all anonymous args onto the stack . XXX I know the prologue should n't be pushing registers , but it is faster that way .


<s> unsigned VEInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . getOpcode ( ) == VE :: LDrii || MI . getOpcode ( ) == VE :: LDLSXrii || MI . getOpcode ( ) == VE :: LDUrii || MI . getOpcode ( ) == VE :: LDQrii ) { if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 && MI . getOperand ( 3 ) . isImm ( ) && MI . getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>


<s> void PPCScoreboardHazardRecognizer :: Reset ( ) { ScoreboardHazardRecognizer :: Reset ( ) ; } </s>


<s> static rtx rs6000_function_value ( const_tree valtype , const_tree fn_decl_or_type ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode mode ; unsigned int regno ; machine_mode elt_mode ; int n_elts ; if ( TARGET_MACHO && rs6000_darwin64_struct_check_p ( TYPE_MODE ( valtype ) , valtype ) ) { CUMULATIVE_ARGS valcum ; rtx valret ; valcum . words = 0 ; valcum . fregno = FP_ARG_MIN_REG ; valcum . vregno = ALTIVEC_ARG_MIN_REG ; valret = rs6000_darwin64_record_arg ( & valcum , valtype , true , true ) ; if ( valret ) return valret ; } mode = TYPE_MODE ( valtype ) ; if ( rs6000_discover_homogeneous_aggregate ( mode , valtype , & elt_mode , & n_elts ) ) { int first_reg , n_regs ; if ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( elt_mode ) ) { first_reg = ( elt_mode == TDmode ) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN ; n_regs = ( GET_MODE_SIZE ( elt_mode ) + 7 ) >> 3 ; } else { first_reg = ALTIVEC_ARG_RETURN ; n_regs = 1 ; } return rs6000_parallel_return ( mode , n_elts , elt_mode , first_reg , n_regs ) ; } if ( TARGET_32BIT && TARGET_POWERPC64 ) switch ( mode ) { default : break ; case E_DImode : case E_SCmode : case E_DCmode : case E_TCmode : int count = GET_MODE_SIZE ( mode ) / 4 ; return rs6000_parallel_return ( mode , count , SImode , GP_ARG_RETURN , 1 ) ; } if ( ( INTEGRAL_TYPE_P ( valtype ) && GET_MODE_BITSIZE ( mode ) < ( TARGET_32BIT ? 32 : 64 ) ) || POINTER_TYPE_P ( valtype ) ) mode = TARGET_32BIT ? SImode : DImode ; if ( DECIMAL_FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT ) regno = ( mode == TDmode ) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN ; else if ( SCALAR_FLOAT_TYPE_P ( valtype ) && TARGET_HARD_FLOAT && ! FLOAT128_VECTOR_P ( mode ) ) regno = FP_ARG_RETURN ; else if ( TREE_CODE ( valtype ) == COMPLEX_TYPE && targetm . calls . split_complex_arg ) return rs6000_complex_function_value ( mode ) ; else if ( ( TREE_CODE ( valtype ) == VECTOR_TYPE || VECTOR_ALIGNMENT_P ( mode ) ) && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI && ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) ) regno = ALTIVEC_ARG_RETURN ; else regno = GP_ARG_RETURN ; return gen_rtx_REG ( mode , regno ) ; } </s>

Define how to find the value returned by a function . VALTYPE is the data type of the value ( as a tree ) . If the precise function being called is known , FUNC is its FUNCTION_DECL ; otherwise , FUNC is 0 . On the SPE , both FPs and vectors are returned in r3 . On RS/6000 an integer value is in r3 and a floating-point value is in fp1 , unless -msoft-float .


<s> bool microblaze_expand_block_move ( rtx dest , rtx src , rtx length , rtx align_rtx ) { if ( GET_CODE ( length ) == CONST_INT ) { unsigned HOST_WIDE_INT bytes = UINTVAL ( length ) ; unsigned int align = UINTVAL ( align_rtx ) ; if ( align > UNITS_PER_WORD ) { align = UNITS_PER_WORD ; } else if ( align < UNITS_PER_WORD ) { if ( UINTVAL ( length ) <= MAX_MOVE_BYTES ) { move_by_pieces ( dest , src , bytes , align , RETURN_BEGIN ) ; return true ; } else return false ; } if ( UINTVAL ( length ) <= 2 * MAX_MOVE_BYTES ) { microblaze_block_move_straight ( dest , src , UINTVAL ( length ) ) ; return true ; } else if ( optimize ) { microblaze_block_move_loop ( dest , src , UINTVAL ( length ) ) ; return true ; } } return false ; } </s>


<s> static bool is_load_insn ( rtx insn , rtx * load_mem ) { if ( ! insn || ! INSN_P ( insn ) ) return false ; if ( CALL_P ( insn ) ) return false ; return is_load_insn1 ( PATTERN ( insn ) , load_mem ) ; } </s>


<s> static void compute_zdepdi_operands ( unsigned HOST_WIDE_INT imm , unsigned * op ) { int lsb , len , maxlen ; maxlen = MIN ( HOST_BITS_PER_WIDE_INT , 64 ) ; for ( lsb = 0 ; lsb < maxlen ; lsb ++ ) { if ( ( imm & 1 ) != 0 ) break ; imm >>= 1 ; } if ( ( imm & 0x10 ) == 0 ) len = ( lsb <= maxlen - 4 ) ? 4 : maxlen - lsb ; else { for ( len = 5 ; len < maxlen - lsb ; len ++ ) { if ( ( imm & ( ( unsigned HOST_WIDE_INT ) 1 << len ) ) == 0 ) break ; } if ( HOST_BITS_PER_WIDE_INT == 32 && len == maxlen - lsb ) len += 32 ; imm = ( imm & 0xf ) - 0x10 ; } op [ 0 ] = imm ; op [ 1 ] = 63 - lsb ; op [ 2 ] = len ; } </s>

Compute position ( in OP [ 1 ] ) and width ( in OP [ 2 ] ) useful for copying IMM to a register using the depdi , z instructions . Store the immediate value to insert in OP [ 0 ] .


<s> bool MipsCallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < Register > VRegs , FunctionLoweringInfo & FLI ) const { MachineInstrBuilder Ret = MIRBuilder . buildInstrNoInsert ( Mips :: RetRA ) ; if ( Val != nullptr && ! isSupportedReturnType ( Val -> getType ( ) ) ) return false ; if ( ! VRegs . empty ( ) ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const MipsTargetLowering & TLI = * getTLI < MipsTargetLowering > ( ) ; SmallVector < ArgInfo , 8 > RetInfos ; ArgInfo ArgRetInfo ( VRegs , * Val , 0 ) ; setArgFlags ( ArgRetInfo , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( ArgRetInfo , RetInfos , DL , F . getCallingConv ( ) ) ; SmallVector < CCValAssign , 16 > ArgLocs ; SmallVector < ISD :: OutputArg , 8 > Outs ; MipsCCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; MipsOutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , Ret ) ; std :: string FuncName = F . getName ( ) . str ( ) ; MipsOutgoingValueAssigner Assigner ( TLI . CCAssignFnForReturn ( ) , FuncName . c_str ( ) , true ) ; if ( ! determineAssignments ( Assigner , RetInfos , CCInfo ) ) return false ; if ( ! handleAssignments ( RetHandler , RetInfos , CCInfo , ArgLocs , MIRBuilder ) ) return false ; } MIRBuilder . insertInstr ( Ret ) ; return true ; } </s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .

Mips Mips Mips::RetRA Mips Mips 8 0 16 ISD::OutputArg 8 Mips Mips Mips


<s> const LanaiInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


"AArch64 FastISel doesn't support types larger than i64"

This is a wrapper around getRegForValue that also takes care of truncating or sign-extending the given getelementptr index value .


<s>
void
AArch64Operand
::
print
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
k_FPImm
:
OS
<<
"<fpimm "
<<
getFPImm
(
)
<<
"("
<<
AArch64_AM
::
getFPImmFloat
(
getFPImm
(
)
)
<<
") >"
;
break
;
case
k_Barrier
:
{
StringRef
Name
=
getBarrierName
(
)
;
if
(
!
Name
.
empty
(
)
)
OS
<<
"<barrier "
<<
Name
<<
">"
;
else
OS
<<
"<barrier invalid #"
<<
getBarrier
(
)
<<
">"
;
break
;
}
case
k_Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
k_ShiftedImm
:
{
unsigned
Shift
=
getShiftedImmShift
(
)
;
OS
<<
"<shiftedimm "
;
OS
<<
*
getShiftedImmVal
(
)
;
OS
<<
", lsl #"
<<
AArch64_AM
::
getShiftValue
(
Shift
)
<<
">"
;
break
;
}
case
k_CondCode
:
OS
<<
"<condcode "
<<
getCondCode
(
)
<<
">"
;
break
;
case
k_Register
:
OS
<<
"<register "
<<
getReg
(
)
<<
">"
;
break
;
case
k_VectorList
:
{
OS
<<
"<vectorlist "
;
unsigned
Reg
=
getVectorListStart
(
)
;
for
(
unsigned
i
=
0
,
e
=
getVectorListCount
(
)
;
i
!=
e
;
++
i
)
OS
<<
Reg
+
i
<<
" "
;
OS
<<
">"
;
break
;
}
case
k_VectorIndex
:
OS
<<
"<vectorindex "
<<
getVectorIndex
(
)
<<
">"
;
break
;
case
k_SysReg
:
OS
<<
"<sysreg: "
<<
getSysReg
(
)
<<
'>'
;
break
;
case
k_Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
case
k_SysCR
:
OS
<<
"c"
<<
getSysCR
(
)
;
break
;
case
k_Prefetch
:
{
StringRef
Name
=
getPrefetchName
(
)
;
if
(
!
Name
.
empty
(
)
)
OS
<<
"<prfop "
<<
Name
<<
">"
;
else
OS
<<
"<prfop invalid #"
<<
getPrefetch
(
)
<<
">"
;
break
;
}
case
k_PSBHint
:
{
OS
<<
getPSBHintName
(
)
;
break
;
}
case
k_ShiftExtend
:
{
OS
<<
"<"
<<
AArch64_AM
::
getShiftExtendName
(
getShiftExtendType
(
)
)
<<
" #"
<<
getShiftExtendAmount
(
)
;
if
(
!
hasShiftExtendAmount
(
)
)
OS
<<
"<imp>"
;
OS
<<
'>'
;
break
;
}
}
}
</s>

print - Print a debug representation of the operand to the given stream .

AArch64
AArch64
"<fpimm "
"("
AArch64_AM::getFPImmFloat
") >"
"<barrier "
">"
"<barrier invalid #"
">"
"<shiftedimm "
", lsl #"
AArch64_AM::getShiftValue
">"
"<condcode "
">"
"<register "
">"
"<vectorlist "
0
" "
">"
"<vectorindex "
">"
"<sysreg: "
"'"
"'"
"c"
"<prfop "
">"
"<prfop invalid #"
">"
"<"
AArch64_AM::getShiftExtendName
" #"
"<imp>"


<s> static bool ix86_tieable_integer_mode_p ( machine_mode mode ) { switch ( mode ) { case HImode : case SImode : return true ; case QImode : return TARGET_64BIT || ! TARGET_PARTIAL_REG_STALL ; case DImode : return TARGET_64BIT ; default : return false ; } } </s>

A subroutine of ix86_modes_tieable_p . Return true if MODE is a tieable integer mode .


<s> MachineBasicBlock * SITargetLowering :: EmitInstrWithCustomInserter ( MachineInstr & MI , MachineBasicBlock * BB ) const { switch ( MI . getOpcode ( ) ) { case AMDGPU :: SI_INIT_M0 : { const SIInstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; BuildMI ( * BB , MI . getIterator ( ) , MI . getDebugLoc ( ) , TII -> get ( AMDGPU :: S_MOV_B32 ) , AMDGPU :: M0 ) . addOperand ( MI . getOperand ( 0 ) ) ; MI . eraseFromParent ( ) ; break ; } case AMDGPU :: BRANCH : return BB ; case AMDGPU :: GET_GROUPSTATICSIZE : { const SIInstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; MachineFunction * MF = BB -> getParent ( ) ; SIMachineFunctionInfo * MFI = MF -> getInfo < SIMachineFunctionInfo > ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; BuildMI ( * BB , MI , DL , TII -> get ( AMDGPU :: S_MOV_B32 ) ) . addOperand ( MI . getOperand ( 0 ) ) . addImm ( MFI -> LDSSize ) ; MI . eraseFromParent ( ) ; return BB ; } case AMDGPU :: SI_KILL : return splitKillBlock ( MI , BB ) ; default : return AMDGPUTargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; } return BB ; } </s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> DecodeStatus HexagonDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & os , raw_ostream & cs ) const { Size = 4 ; if ( Bytes . size ( ) < 4 ) return MCDisassembler :: Fail ; uint32_t insn = llvm :: support :: endian :: read < uint32_t , llvm :: support :: little , llvm :: support :: unaligned > ( Bytes . data ( ) ) ; insn &= ~ static_cast < uint32_t > ( HexagonII :: InstParseBits :: INST_PARSE_MASK ) ; DecodeStatus Result = decodeInstruction ( DecoderTable32 , MI , insn , Address , this , STI ) ; HexagonMCInstrInfo :: AppendImplicitOperands ( MI ) ; return Result ; } </s>

Returns the disassembly of a single instruction .

Hexagon Hexagon 4 4 support::endian support::little support::unaligned HexagonII::InstParseBits Hexagon


<s>
void
SystemZPostRASchedStrategy
::
leaveMBB
(
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"** Leaving "
<<
printMBBReference
(
*
MBB
)
<<
"\n"
;
)
;
advanceTo
(
MBB
->
getFirstTerminator
(
)
)
;
}
</s>

Tell the strategy that current MBB is done .


This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> static void rs6000_set_sched_context ( void * _sc ) { rs6000_sched_context_t sc = ( rs6000_sched_context_t ) _sc ; gcc_assert ( sc != NULL ) ; cached_can_issue_more = sc -> cached_can_issue_more ; last_scheduled_insn = sc -> last_scheduled_insn ; load_store_pendulum = sc -> load_store_pendulum ; } </s>

Sets the global scheduling context to the one pointed to by _SC .


<s> uint64_t MipsFrameLowering :: estimateStackSize ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo & TRI = * MF . getTarget ( ) . getRegisterInfo ( ) ; int64_t Offset = 0 ; for ( int I = MFI -> getObjectIndexBegin ( ) ; I != 0 ; ++ I ) Offset = std :: max ( Offset , - MFI -> getObjectOffset ( I ) ) ; for ( const uint16_t * R = TRI . getCalleeSavedRegs ( & MF ) ; * R ; ++ R ) { unsigned Size = TRI . getMinimalPhysRegClass ( * R ) -> getSize ( ) ; Offset = RoundUpToAlignment ( Offset + Size , Size ) ; } unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; assert ( ! MFI -> getObjectIndexEnd ( ) || MaxAlign ) ; for ( unsigned I = 0 , E = MFI -> getObjectIndexEnd ( ) ; I != E ; ++ I ) Offset = RoundUpToAlignment ( Offset + MFI -> getObjectSize ( I ) , MaxAlign ) ; if ( MFI -> adjustsStack ( ) && hasReservedCallFrame ( MF ) ) Offset = RoundUpToAlignment ( Offset + MFI -> getMaxCallFrameSize ( ) , std :: max ( MaxAlign , getStackAlignment ( ) ) ) ; return RoundUpToAlignment ( Offset , getStackAlignment ( ) ) ; } </s>

Estimate and return the size of the stack frame .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"ARM Native Client Rewrite Pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 speculative load hardening"
;
}
</s>


<s> bool ARMTargetLowering :: isExtractSubvectorCheap ( EVT ResVT , unsigned Index ) const { if ( ! isOperationLegalOrCustom ( ISD :: EXTRACT_SUBVECTOR , ResVT ) ) return false ; return ( Index == 0 || Index == ResVT . getVectorNumElements ( ) ) ; } </s>

Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index .


<s> bool runOnFunction ( Function & F ) override { if ( F . hasFnAttribute ( Attribute :: OptimizeNone ) ) { F . removeAttribute ( AttributeList :: FunctionIndex , Attribute :: OptimizeNone ) ; return true ; } return false ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static rtx gen_stack_pointer_inc ( rtx increment ) { return gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , increment ) ) ; } </s>

Generate an increment for the stack pointer .


<s>
unsigned
MipsInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
reverse_iterator
I
=
MBB
.
rbegin
(
)
,
REnd
=
MBB
.
rend
(
)
;
unsigned
removed
=
0
;
while
(
I
!=
REnd
&&
removed
<
2
)
{
if
(
I
->
isDebugValue
(
)
)
{
++
I
;
continue
;
}
if
(
!
getAnalyzableBrOpc
(
I
->
getOpcode
(
)
)
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
rbegin
(
)
;
++
removed
;
}
return
removed
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s>
SDValue
MSP430TargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
unsigned
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
isVarArg
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s>
bool
AMDGPUAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MF
.
setAlignment
(
8
)
;
SetupMachineFunction
(
MF
)
;
MCContext
&
Context
=
getObjFileLowering
(
)
.
getContext
(
)
;
MCSectionELF
*
ConfigSection
=
Context
.
getELFSection
(
".AMDGPU.config"
,
ELF
::
SHT_PROGBITS
,
0
)
;
OutStreamer
->
SwitchSection
(
ConfigSection
)
;
const
AMDGPUSubtarget
&
STM
=
MF
.
getSubtarget
<
AMDGPUSubtarget
>
(
)
;
SIProgramInfo
KernelInfo
;
if
(
STM
.
getGeneration
(
)
>=
AMDGPUSubtarget
::
SOUTHERN_ISLANDS
)
{
getSIProgramInfo
(
KernelInfo
,
MF
)
;
if
(
!
STM
.
isAmdHsaOS
(
)
)
{
EmitProgramInfoSI
(
MF
,
KernelInfo
)
;
}
AMDGPUTargetStreamer
*
TS
=
static_cast
<
AMDGPUTargetStreamer
*
>
(
OutStreamer
->
getTargetStreamer
(
)
)
;
TS
->
EmitDirectiveHSACodeObjectVersion
(
1
,
0
)
;
AMDGPU
::
IsaVersion
ISA
=
STM
.
getIsaVersion
(
)
;
TS
->
EmitDirectiveHSACodeObjectISA
(
ISA
.
Major
,
ISA
.
Minor
,
ISA
.
Stepping
,
"AMD"
,
"AMDGPU"
)
;
}
else
{
EmitProgramInfoR600
(
MF
)
;
}
DisasmLines
.
clear
(
)
;
HexLines
.
clear
(
)
;
DisasmLineMaxLen
=
0
;
EmitFunctionBody
(
)
;
if
(
isVerbose
(
)
)
{
MCSectionELF
*
CommentSection
=
Context
.
getELFSection
(
".AMDGPU.csdata"
,
ELF
::
SHT_PROGBITS
,
0
)
;
OutStreamer
->
SwitchSection
(
CommentSection
)
;
if
(
STM
.
getGeneration
(
)
>=
AMDGPUSubtarget
::
SOUTHERN_ISLANDS
)
{
OutStreamer
->
emitRawComment
(
" Kernel info:"
,
false
)
;
OutStreamer
->
emitRawComment
(
" codeLenInByte = "
+
Twine
(
KernelInfo
.
CodeLen
)
,
false
)
;
OutStreamer
->
emitRawComment
(
" NumSgprs: "
+
Twine
(
KernelInfo
.
NumSGPR
)
,
false
)
;
OutStreamer
->
emitRawComment
(
" NumVgprs: "
+
Twine
(
KernelInfo
.
NumVGPR
)
,
false
)
;
OutStreamer
->
emitRawComment
(
" FloatMode: "
+
Twine
(
KernelInfo
.
FloatMode
)
,
false
)
;
OutStreamer
->
emitRawComment
(
" IeeeMode: "
+
Twine
(
KernelInfo
.
IEEEMode
)
,
false
)
;
OutStreamer
->
emitRawComment
(
" ScratchSize: "
+
Twine
(
KernelInfo
.
ScratchSize
)
,
false
)
;
}
else
{
R600MachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
R600MachineFunctionInfo
>
(
)
;
OutStreamer
->
emitRawComment
(
Twine
(
"SQ_PGM_RESOURCES:STACK_SIZE = "
+
Twine
(
MFI
->
StackSize
)
)
)
;
}
}
if
(
STM
.
dumpCode
(
)
)
{
OutStreamer
->
SwitchSection
(
Context
.
getELFSection
(
".AMDGPU.disasm"
,
ELF
::
SHT_NOTE
,
0
)
)
;
for
(
size_t
i
=
0
;
i
<
DisasmLines
.
size
(
)
;
++
i
)
{
std
::
string
Comment
(
DisasmLineMaxLen
DisasmLines
[
i
]
.
size
(
)
,
' '
)
;
Comment
+=
" ; "
+
HexLines
[
i
]
+
"\n"
;
OutStreamer
->
EmitBytes
(
StringRef
(
DisasmLines
[
i
]
)
)
;
OutStreamer
->
EmitBytes
(
StringRef
(
Comment
)
)
;
}
}
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> void ARMBaseRegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , unsigned PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: LDRcp ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( 0 ) . addImm ( Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s> bool ARMTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , bool * Fast ) const { if ( ! VT . isSimple ( ) ) return false ; bool AllowsUnaligned = Subtarget -> allowsUnalignedMem ( ) ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : { if ( AllowsUnaligned ) { if ( Fast ) * Fast = Subtarget -> hasV7Ops ( ) ; return true ; } return false ; } case MVT :: f64 : case MVT :: v2f64 : { if ( Subtarget -> hasNEON ( ) && ( AllowsUnaligned || Subtarget -> isLittle ( ) ) ) { if ( Fast ) * Fast = true ; return true ; } return false ; } } } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> unsigned getSetRegWaitStates ( ) const { return getGeneration ( ) <= SEA_ISLANDS ? 1 : 2 ; } </s>

Number of hazard wait states for s_setreg_b32/s_setreg_imm32_b32 .


<s> unsigned AArch64AsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { AArch64Operand & Op = static_cast < AArch64Operand & > ( AsmOp ) ; int64_t ExpectedVal ; switch ( Kind ) { default : return Match_InvalidOperand ; case MCK__HASH_0 : ExpectedVal = 0 ; break ; case MCK__HASH_1 : ExpectedVal = 1 ; break ; case MCK__HASH_12 : ExpectedVal = 12 ; break ; case MCK__HASH_16 : ExpectedVal = 16 ; break ; case MCK__HASH_2 : ExpectedVal = 2 ; break ; case MCK__HASH_24 : ExpectedVal = 24 ; break ; case MCK__HASH_3 : ExpectedVal = 3 ; break ; case MCK__HASH_32 : ExpectedVal = 32 ; break ; case MCK__HASH_4 : ExpectedVal = 4 ; break ; case MCK__HASH_48 : ExpectedVal = 48 ; break ; case MCK__HASH_6 : ExpectedVal = 6 ; break ; case MCK__HASH_64 : ExpectedVal = 64 ; break ; case MCK__HASH_8 : ExpectedVal = 8 ; break ; case MCK_MPR : if ( Op . isTokenEqual ( "za" ) ) return Match_Success ; return Match_InvalidOperand ; } if ( ! Op . isImm ( ) ) return Match_InvalidOperand ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ; if ( ! CE ) return Match_InvalidOperand ; if ( CE -> getValue ( ) == ExpectedVal ) return Match_Success ; return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> void HSAILTargetObjectFile :: Initialize ( MCContext & ctx , const TargetMachine & TM ) { TargetLoweringObjectFile :: Initialize ( ctx , TM ) ; TextSection = new HSAILSection ( MCSection :: SV_ELF , SectionKind :: getText ( ) ) ; DataSection = new HSAILSection ( MCSection :: SV_ELF , SectionKind :: getDataRel ( ) ) ; BSSSection = new HSAILSection ( MCSection :: SV_ELF , SectionKind :: getBSS ( ) ) ; ReadOnlySection = new HSAILSection ( MCSection :: SV_ELF , SectionKind :: getReadOnly ( ) ) ; StaticCtorSection = new HSAILSection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; StaticDtorSection = new HSAILSection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; LSDASection = new HSAILSection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; EHFrameSection = new HSAILSection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfAbbrevSection = new HSAILSection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfInfoSection = new HSAILSection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfLineSection = new HSAILSection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfFrameSection = new HSAILSection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfPubTypesSection = new HSAILSection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfDebugInlineSection = new HSAILSection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfStrSection = new HSAILSection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfLocSection = new HSAILSection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfARangesSection = new HSAILSection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfRangesSection = new HSAILSection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; } </s>

This method must be called before any actual lowering is done .

HSAIL HSAIL HSAIL HSAIL HSAIL HSAIL HSAIL HSAIL HSAIL HSAIL HSAIL HSAIL HSAIL HSAIL HSAIL HSAIL HSAIL HSAIL HSAIL HSAIL


<s> bool isReg ( ) const override { return Kind == Register ; } </s>


<s> MachineInstrBuilder MipsInstrInfo :: genInstrWithNewOpc ( unsigned NewOpc , MachineBasicBlock :: iterator I ) const { MachineInstrBuilder MIB ; int ZeroOperandPosition = - 1 ; bool BranchWithZeroOperand = false ; if ( I -> isBranch ( ) && ! I -> isPseudo ( ) ) { auto TRI = I -> getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; ZeroOperandPosition = I -> findRegisterUseOperandIdx ( Mips :: ZERO , false , TRI ) ; BranchWithZeroOperand = ZeroOperandPosition != - 1 ; } if ( BranchWithZeroOperand ) { switch ( NewOpc ) { case Mips :: BEQC : NewOpc = Mips :: BEQZC ; break ; case Mips :: BNEC : NewOpc = Mips :: BNEZC ; break ; case Mips :: BGEC : NewOpc = Mips :: BGEZC ; break ; case Mips :: BLTC : NewOpc = Mips :: BLTZC ; break ; case Mips :: BEQC64 : NewOpc = Mips :: BEQZC64 ; break ; case Mips :: BNEC64 : NewOpc = Mips :: BNEZC64 ; break ; } } MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , get ( NewOpc ) ) ; if ( NewOpc == Mips :: JIC || NewOpc == Mips :: JIALC || NewOpc == Mips :: JIC64 || NewOpc == Mips :: JIALC64 ) { if ( NewOpc == Mips :: JIALC || NewOpc == Mips :: JIALC64 ) MIB -> removeOperand ( 0 ) ; for ( unsigned J = 0 , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { MIB . add ( I -> getOperand ( J ) ) ; } MIB . addImm ( 0 ) ; for ( unsigned J = I -> getDesc ( ) . getNumOperands ( ) , E = I -> getNumOperands ( ) ; J < E ; ++ J ) { const MachineOperand & MO = I -> getOperand ( J ) ; if ( MO . isMCSymbol ( ) && ( MO . getTargetFlags ( ) & MipsII :: MO_JALR ) ) MIB . addSym ( MO . getMCSymbol ( ) , MipsII :: MO_JALR ) ; } } else { for ( unsigned J = 0 , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { if ( BranchWithZeroOperand && ( unsigned ) ZeroOperandPosition == J ) continue ; MIB . add ( I -> getOperand ( J ) ) ; } } MIB . copyImplicitOps ( * I ) ; MIB . cloneMemRefs ( * I ) ; return MIB ; } </s>

Create an instruction which has the same operands and memory operands as MI but has a new opcode .


<s> void addLOHDirective ( MCLOHType Kind , const MILOHArgs & Args ) { LOHContainerSet . push_back ( MILOHDirective ( Kind , Args ) ) ; LOHRelated . insert ( Args . begin ( ) , Args . end ( ) ) ; } </s>

Add a LOH directive of this Kind and this Args .


<s>
void
SIRegisterInfo
::
resolveFrameIndex
(
MachineInstr
&
MI
,
unsigned
BaseReg
,
int64_t
Offset
)
const
{
MachineBasicBlock
*
MBB
=
MI
.
getParent
(
)
;
MachineFunction
*
MF
=
MBB
->
getParent
(
)
;
const
SISubtarget
&
Subtarget
=
MF
->
getSubtarget
<
SISubtarget
>
(
)
;
const
SIInstrInfo
*
TII
=
Subtarget
.
getInstrInfo
(
)
;
bool
SeenFI
=
false
;
for
(
const
MachineOperand
&
MO
:
MI
.
operands
(
)
)
{
if
(
MO
.
isFI
(
)
)
{
if
(
SeenFI
)
llvm_unreachable
(
"should not see multiple frame indices"
)
;
SeenFI
=
true
;
}
}
MachineOperand
*
FIOp
=
TII
->
getNamedOperand
(
MI
,
AMDGPU
::
OpName
::
vaddr
)
;
assert
(
FIOp
&&
FIOp
->
isFI
(
)
&&
"frame index must be address operand"
)
;
assert
(
TII
->
isMUBUF
(
MI
)
)
;
MachineOperand
*
OffsetOp
=
TII
->
getNamedOperand
(
MI
,
AMDGPU
::
OpName
::
offset
)
;
int64_t
NewOffset
=
OffsetOp
->
getImm
(
)
+
Offset
;
if
(
isUInt
<
12
>
(
NewOffset
)
)
{
FIOp
->
ChangeToRegister
(
BaseReg
,
false
)
;
OffsetOp
->
setImm
(
NewOffset
)
;
return
;
}
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
unsigned
NewReg
=
MRI
.
createVirtualRegister
(
&
AMDGPU
::
VGPR_32RegClass
)
;
DebugLoc
DL
=
MI
.
getDebugLoc
(
)
;
assert
(
Offset
!=
0
&&
"Non-zero offset expected"
)
;
unsigned
UnusedCarry
=
MRI
.
createVirtualRegister
(
&
AMDGPU
::
SReg_64RegClass
)
;
BuildMI
(
*
MBB
,
MI
,
DL
,
TII
->
get
(
AMDGPU
::
V_ADD_I32_e64
)
,
NewReg
)
.
addReg
(
UnusedCarry
,
RegState
::
Define
|
RegState
::
Dead
)
.
addImm
(
Offset
)
.
addReg
(
BaseReg
)
;
FIOp
->
ChangeToRegister
(
NewReg
,
false
)
;
}
</s>

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .

AMDGPU
SI
SI
SI
SI
"should not see multiple frame indices"
AMDGPU::OpName
"frame index must be address operand"
AMDGPU::OpName
12
AMDGPU::VGPR_32RegClass
0
"Non-zero offset expected"
AMDGPU::SReg_64RegClass
AMDGPU::V_ADD_I32_e64


<s> bool AMDGPUAAResult :: pointsToConstantMemory ( const MemoryLocation & Loc , bool OrLocal ) { const Value * Base = GetUnderlyingObject ( Loc . Ptr , DL ) ; if ( Base -> getType ( ) -> getPointerAddressSpace ( ) == AS . CONSTANT_ADDRESS ) { return true ; } if ( const GlobalVariable * GV = dyn_cast < GlobalVariable > ( Base ) ) { if ( GV -> isConstant ( ) ) return true ; } else if ( const Argument * Arg = dyn_cast < Argument > ( Base ) ) { const Function * F = Arg -> getParent ( ) ; switch ( F -> getCallingConv ( ) ) { default : return AAResultBase :: pointsToConstantMemory ( Loc , OrLocal ) ; case CallingConv :: AMDGPU_VS : case CallingConv :: AMDGPU_GS : case CallingConv :: AMDGPU_PS : case CallingConv :: AMDGPU_CS : case CallingConv :: AMDGPU_KERNEL : case CallingConv :: SPIR_KERNEL : break ; } unsigned ArgNo = Arg -> getArgNo ( ) ; if ( F -> getAttributes ( ) . hasAttribute ( ArgNo + 1 , Attribute :: NoAlias ) && ( F -> getAttributes ( ) . hasAttribute ( ArgNo + 1 , Attribute :: ReadNone ) || F -> getAttributes ( ) . hasAttribute ( ArgNo + 1 , Attribute :: ReadOnly ) ) ) { return true ; } } return AAResultBase :: pointsToConstantMemory ( Loc , OrLocal ) ; } </s>

A convenience wrapper around the primary pointsToConstantMemory interface .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU 1 1 1


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s>
StringRef
getPassName
(
)
const
override
{
return
"DXIL Metadata Emit"
;
}
</s>

getPassName - Return a nice clean name for a pass .