<s> TargetLowering :: AtomicExpansionKind PPCTargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { unsigned Size = AI -> getPointerOperand ( ) -> getType ( ) -> getPointerElementType ( ) -> getPrimitiveSizeInBits ( ) ; if ( EnableQuadwordAtomics && Subtarget . hasQuadwordAtomics ( ) && Size == 128 ) return AtomicExpansionKind :: MaskedIntrinsic ; return TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AI ) ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> int tilepro_asm_preferred_eh_data_format ( int code ATTRIBUTE_UNUSED , int global ) { return ( global ? DW_EH_PE_indirect : 0 ) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 ; } </s>

Select a format to encode pointers in exception handling data . CODE is 0 for data , 1 for code labels , 2 for function pointers . GLOBAL is true if the symbol may be affected by dynamic relocations .


<s> bool fusion_p9_p ( rtx addis_reg , rtx addis_value , rtx dest , rtx src ) { rtx addr , mem , offset ; machine_mode mode = GET_MODE ( src ) ; if ( ! base_reg_operand ( addis_reg , GET_MODE ( addis_reg ) ) ) return false ; if ( ! fusion_gpr_addis ( addis_value , GET_MODE ( addis_value ) ) ) return false ; if ( GET_CODE ( src ) == FLOAT_EXTEND || GET_CODE ( src ) == ZERO_EXTEND ) src = XEXP ( src , 0 ) ; if ( fpr_reg_operand ( src , mode ) || int_reg_operand ( src , mode ) ) { if ( ! MEM_P ( dest ) ) return false ; mem = dest ; } else if ( MEM_P ( src ) ) { if ( ! fpr_reg_operand ( dest , mode ) && ! int_reg_operand ( dest , mode ) ) return false ; mem = src ; } else return false ; addr = XEXP ( mem , 0 ) ; if ( GET_CODE ( addr ) == PLUS ) { if ( ! rtx_equal_p ( addis_reg , XEXP ( addr , 0 ) ) ) return false ; return satisfies_constraint_I ( XEXP ( addr , 1 ) ) ; } else if ( GET_CODE ( addr ) == LO_SUM ) { if ( ! rtx_equal_p ( addis_reg , XEXP ( addr , 0 ) ) ) return false ; offset = XEXP ( addr , 1 ) ; if ( TARGET_XCOFF || ( TARGET_ELF && TARGET_POWERPC64 ) ) return small_toc_ref ( offset , GET_MODE ( offset ) ) ; else if ( TARGET_ELF && ! TARGET_POWERPC64 ) return CONSTANT_P ( offset ) ; } return false ; } </s>

Return true if the peephole2 can combine a load/store involving a combination of an addis instruction and the memory operation . This was added to the ISA 3.0 ( power9 ) hardware .


<s>
void
HexagonFrameLowering
::
emitPrologue
(
MachineFunction
&
MF
)
const
{
MachineBasicBlock
&
MBB
=
MF
.
front
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
const
HexagonRegisterInfo
*
QRI
=
static_cast
<
const
HexagonRegisterInfo
*
>
(
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
)
;
DebugLoc
dl
=
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
determineFrameLayout
(
MF
)
;
int
NumBytes
=
(
int
)
MFI
->
getStackSize
(
)
;
MachineBasicBlock
::
iterator
InsertPt
=
MBB
.
begin
(
)
;
HexagonMachineFunctionInfo
*
FuncInfo
=
MF
.
getInfo
<
HexagonMachineFunctionInfo
>
(
)
;
const
std
::
vector
<
MachineInstr
*
>
&
AdjustRegs
=
FuncInfo
->
getAllocaAdjustInsts
(
)
;
for
(
std
::
vector
<
MachineInstr
*
>
::
const_iterator
i
=
AdjustRegs
.
begin
(
)
,
e
=
AdjustRegs
.
end
(
)
;
i
!=
e
;
++
i
)
{
MachineInstr
*
MI
=
*
i
;
assert
(
(
MI
->
getOpcode
(
)
==
Hexagon
::
ADJDYNALLOC
)
&&
"Expected adjust alloca node"
)
;
MachineOperand
&
MO
=
MI
->
getOperand
(
2
)
;
assert
(
MO
.
isImm
(
)
&&
"Expected immediate"
)
;
MO
.
setImm
(
MFI
->
getMaxCallFrameSize
(
)
)
;
}
if
(
hasFP
(
MF
)
)
{
const
int
ALLOCFRAME_MAX
=
16384
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
if
(
NumBytes
>=
ALLOCFRAME_MAX
)
{
BuildMI
(
MBB
,
InsertPt
,
dl
,
TII
.
get
(
Hexagon
::
S2_allocframe
)
)
.
addImm
(
0
)
;
BuildMI
(
MBB
,
InsertPt
,
dl
,
TII
.
get
(
Hexagon
::
CONST32_Int_Real
)
,
HEXAGON_RESERVED_REG_1
)
.
addImm
(
NumBytes
)
;
BuildMI
(
MBB
,
InsertPt
,
dl
,
TII
.
get
(
Hexagon
::
A2_sub
)
,
QRI
->
getStackRegister
(
)
)
.
addReg
(
QRI
->
getStackRegister
(
)
)
.
addReg
(
HEXAGON_RESERVED_REG_1
)
;
}
else
{
BuildMI
(
MBB
,
InsertPt
,
dl
,
TII
.
get
(
Hexagon
::
S2_allocframe
)
)
.
addImm
(
NumBytes
)
;
}
}
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> MipsSubtarget :: MipsSubtarget ( const TargetMachine & TM , const Module & M , const std :: string & FS , bool little ) : MipsArchVersion ( Mips1 ) , MipsABI ( O32 ) , IsLittle ( little ) , IsSingleFloat ( false ) , IsFP64bit ( false ) , IsGP64bit ( false ) , HasVFPU ( false ) , HasABICall ( true ) , HasAbsoluteCall ( false ) , IsLinux ( true ) , HasSEInReg ( false ) , HasCondMov ( false ) , HasMulDivAdd ( false ) , HasMinMax ( false ) , HasSwap ( false ) , HasBitCount ( false ) { std :: string CPU = "mips1" ; ParseSubtargetFeatures ( FS , CPU ) ; const std :: string & TT = M . getTargetTriple ( ) ; SSectionThreshold = SSThreshold ; if ( TT . find ( "linux" ) == std :: string :: npos ) IsLinux = false ; if ( TT . find ( "mipsallegrex" ) != std :: string :: npos || TT . find ( "psp" ) != std :: string :: npos ) { MipsABI = EABI ; IsSingleFloat = true ; MipsArchVersion = Mips2 ; HasVFPU = true ; HasSEInReg = true ; HasBitCount = true ; HasSwap = true ; HasCondMov = true ; } if ( NotABICall || isABI_EABI ( ) || ( TM . getRelocationModel ( ) == Reloc :: Static ) ) HasABICall = false ; if ( HasABICall && AbsoluteCall ) HasAbsoluteCall = true ; } </s>

This constructor initializes the data members to match that of the specified triple .

Mips Mips Mips Mips Mips Mips "mips1" "linux" "mipsallegrex" "psp" Mips Mips Mips


<s>
void
Mips16FrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
const
Mips16InstrInfo
&
TII
=
*
static_cast
<
const
Mips16InstrInfo
*
>
(
STI
.
getInstrInfo
(
)
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
dl
=
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
uint64_t
StackSize
=
MFI
->
getStackSize
(
)
;
if
(
StackSize
==
0
&&
!
MFI
->
adjustsStack
(
)
)
return
;
MachineModuleInfo
&
MMI
=
MF
.
getMMI
(
)
;
const
MCRegisterInfo
*
MRI
=
MMI
.
getContext
(
)
.
getRegisterInfo
(
)
;
MachineLocation
DstML
,
SrcML
;
TII
.
makeFrame
(
Mips
::
SP
,
StackSize
,
MBB
,
MBBI
)
;
unsigned
CFIIndex
=
MMI
.
addFrameInst
(
MCCFIInstruction
::
createDefCfaOffset
(
nullptr
,
StackSize
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
TargetOpcode
::
CFI_INSTRUCTION
)
)
.
addCFIIndex
(
CFIIndex
)
;
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
->
getCalleeSavedInfo
(
)
;
if
(
CSI
.
size
(
)
)
{
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
->
getCalleeSavedInfo
(
)
;
for
(
std
::
vector
<
CalleeSavedInfo
>
::
const_iterator
I
=
CSI
.
begin
(
)
,
E
=
CSI
.
end
(
)
;
I
!=
E
;
++
I
)
{
int64_t
Offset
=
MFI
->
getObjectOffset
(
I
->
getFrameIdx
(
)
)
;
unsigned
Reg
=
I
->
getReg
(
)
;
unsigned
DReg
=
MRI
->
getDwarfRegNum
(
Reg
,
true
)
;
unsigned
CFIIndex
=
MMI
.
addFrameInst
(
MCCFIInstruction
::
createOffset
(
nullptr
,
DReg
,
Offset
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
TargetOpcode
::
CFI_INSTRUCTION
)
)
.
addCFIIndex
(
CFIIndex
)
;
}
}
if
(
hasFP
(
MF
)
)
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Mips
::
MoveR3216
)
,
Mips
::
S0
)
.
addReg
(
Mips
::
SP
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
}
</s>

Mips
Mips
"Shrink-wrapping not yet supported"
Mips
Mips
0
Mips::SP
Mips::MoveR3216
Mips::S0
Mips::SP


<s>
const
char
*
getPassName
(
)
const
{
return
"Tile64 VLIW Packetizer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool X86InstrInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; bool is64Bit = TM . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ; bool isWin64 = TM . getSubtarget < X86Subtarget > ( ) . isTargetWin64 ( ) ; unsigned SlotSize = is64Bit ? 8 : 4 ; MachineFunction & MF = * MBB . getParent ( ) ; unsigned FPReg = RI . getFrameRegister ( MF ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned CalleeFrameSize = 0 ; unsigned Opc = is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; const TargetRegisterClass * RegClass = CSI [ i - 1 ] . getRegClass ( ) ; MBB . addLiveIn ( Reg ) ; if ( Reg == FPReg ) continue ; if ( RegClass != & X86 :: VR128RegClass && ! isWin64 ) { CalleeFrameSize += SlotSize ; BuildMI ( MBB , MI , DL , get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) ; } else { storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - 1 ] . getFrameIdx ( ) , RegClass ) ; } } X86FI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ; return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s>
static
void
mmix_output_octa
(
FILE
*
stream
,
int64_t
value
,
int
do_begin_end
)
{
if
(
do_begin_end
)
fprintf
(
stream
,
"\tOCTA "
)
;
if
(
(
value
<
(
int64_t
)
0
&&
value
>
(
int64_t
)
10000
)
||
(
value
>=
(
int64_t
)
0
&&
value
<=
(
int64_t
)
16384
)
)
fprintf
(
stream
,
"%d"
,
(
int
)
value
)
;
else
if
(
value
>
(
int64_t
)
0
&&
value
<
(
(
int64_t
)
1
<<
31
)
*
2
)
fprintf
(
stream
,
"#%x"
,
(
unsigned
int
)
value
)
;
else
if
(
sizeof
(
HOST_WIDE_INT
)
==
sizeof
(
int64_t
)
)
fprintf
(
stream
,
"#"
HOST_WIDE_INT_PRINT_HEX_PURE
,
(
HOST_WIDE_INT
)
value
)
;
else
fprintf
(
stream
,
"%"
PRIu64
,
value
)
;
if
(
do_begin_end
)
fprintf
(
stream
,
"\n"
)
;
}
</s>

Print a 64-bit value , optionally prefixed by assembly pseudo .


<s> static bool ix86_cannot_force_const_mem ( machine_mode mode , rtx x ) { switch ( GET_CODE ( x ) ) { CASE_CONST_ANY : return false ; default : break ; } return ! ix86_legitimate_constant_p ( mode , x ) ; } </s>

Determine if it 's legal to put X into the constant pool . This is not possible for the address of thread-local symbols , which is checked above .


<s>
bool
TPCCostModelEmitter
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
if
(
dontAnalysis
)
{
TPC_DEBUG
(
"Analysis doesn't work"
)
return
EXIT_SUCCESS
;
}
auto
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
auto
&
LI
=
getAnalysis
<
LoopInfoWrapperPass
>
(
)
.
getLoopInfo
(
)
;
auto
&
SE
=
getAnalysis
<
ScalarEvolutionWrapperPass
>
(
)
.
getSE
(
)
;
DominatorTree
&
DT
=
getAnalysis
<
DominatorTreeWrapperPass
>
(
)
.
getDomTree
(
)
;
SCE
=
new
SCEVExpander
(
SE
,
SE
.
getDataLayout
(
)
,
"expander"
)
;
TPC_DEBUG
(
"Init graph presentation:\n"
)
;
CostTree
graph
(
&
Fn
,
LI
,
SE
,
MLI
,
DT
)
;
if
(
!
graph
.
getValid
(
)
)
return
false
;
if
(
printGraphB
)
printGraph
(
"CFG-"
,
graph
)
;
TPC_DEBUG
(
"Graph segmenting:\n"
)
;
graph
.
consumeCircle
(
)
;
if
(
!
graph
.
isValid
(
)
)
{
TPC_DEBUG
(
"not valid model"
)
;
return
false
;
}
if
(
printGraphB
)
printGraph
(
"cfg-cost"
,
graph
)
;
TPC_DEBUG
(
"Graph calculation:\n"
)
;
const
SCEV
*
init
=
graph
.
computeCostTree
(
graph
.
getRoot
(
)
,
DT
)
;
if
(
!
init
)
{
TPC_DEBUG
(
"not valid model"
)
;
return
false
;
}
llvm
::
Module
*
M
=
(
llvm
::
Module
*
)
Fn
.
getFunction
(
)
.
getParent
(
)
;
std
::
vector
<
const
Argument
*
>
argList
;
for
(
auto
&
fArg
:
Fn
.
getFunction
(
)
.
args
(
)
)
{
argList
.
push_back
(
&
fArg
)
;
}
string
val
=
printHelper
(
init
,
argList
)
;
if
(
!
isValidCostModel
)
{
TPC_DEBUG
(
"not valid model"
)
;
return
false
;
}
val
=
"SCEVBEGIN SCEVCOST:"
+
val
+
"#SCEVEND"
;
TPC_DEBUG
(
"print result:"
+
val
+
"\n"
)
;
if
(
TPCResult
)
llvm
::
errs
(
)
<<
"print result: "
+
val
+
"\n"
;
TPC_DEBUG
(
"Writing result to object"
)
;
StringRef
Name
=
"SCEVCost"
;
Type
*
Int8Ty
=
llvm
::
Type
::
getInt8Ty
(
Fn
.
getFunction
(
)
.
getContext
(
)
)
;
vector
<
Constant
*
>
Init
=
createAString
(
val
,
Int8Ty
)
;
ArrayType
*
ATy
=
ArrayType
::
get
(
Int8Ty
,
Init
.
size
(
)
)
;
llvm
::
GlobalVariable
*
GV0
=
new
llvm
::
GlobalVariable
(
*
M
,
ATy
,
false
,
GlobalValue
::
ExternalLinkage
,
ConstantArray
::
get
(
ATy
,
Init
)
,
Name
,
nullptr
)
;
GV0
->
setSection
(
".SCEVCost"
)
;
TPC_DEBUG
(
"Adding new section: .SCEVCost"
)
;
return
EXIT_SUCCESS
;
}
</s>

runOnMachineFunction - Emit the function body .

TPC
TPC
TPC
"Analysis doesn't work"
"expander"
TPC
"Init graph presentation:\n"
"CFG-"
TPC
"Graph segmenting:\n"
TPC
"not valid model"
"cfg-cost"
TPC
"Graph calculation:\n"
TPC
"not valid model"
TPC
"not valid model"
"SCEVBEGIN SCEVCOST:"
"#SCEVEND"
TPC
"print result:"
"\n"
TPC
"print result: "
"\n"
TPC
"Writing result to object"
"SCEVCost"
".SCEVCost"
TPC
"Adding new section: .SCEVCost"


<s> static void mips_macc_chains_reorder ( rtx_insn * * ready , int nready ) { int i , j ; if ( mips_macc_chains_last_hilo != 0 ) for ( i = nready - 1 ; i >= 0 ; i -- ) if ( mips_linked_madd_p ( mips_macc_chains_last_hilo , ready [ i ] ) ) { for ( j = nready - 1 ; j > i ; j -- ) if ( recog_memoized ( ready [ j ] ) >= 0 && get_attr_may_clobber_hilo ( ready [ j ] ) ) { mips_promote_ready ( ready , i , j ) ; break ; } break ; } } </s>

A TUNE_MACC_CHAINS helper function . Search ready queue READY , which has NREADY elements , looking for a multiply-add or multiply-subtract instruction that is cumulative with mips_macc_chains_last_hilo . If there is one , promote it ahead of anything else that might clobber hi or lo .


<s>
SDValue
Tile64TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
GlobalTLSAddress
:
llvm_unreachable
(
"TLS not implemented for Tile64."
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
VAARG
:
return
LowerVAARG
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
,
true
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

Tile64
"Should not custom lower this!"
ISD::GlobalTLSAddress
"TLS not implemented for Tile64."
ISD::GlobalAddress
ISD::ConstantPool
ISD::VASTART
ISD::VAARG
ISD::DYNAMIC_STACKALLOC
ISD::RETURNADDR
ISD::FRAMEADDR


This function is called when the end of a window processing is reached .


<s> int h8300_hard_regno_nregs ( int regno ATTRIBUTE_UNUSED , enum machine_mode mode ) { return ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } </s>

Worker function for HARD_REGNO_NREGS . We pretend the MAC register is 32bits -- we do n't have any data types on the H8 series to handle more than 32bits .


<s> bool AArch64FastISel :: optimizeSelect ( const SelectInst * SI ) { if ( ! SI -> getType ( ) -> isIntegerTy ( 1 ) ) return false ; const Value * Src1Val , * Src2Val ; unsigned Opc = 0 ; bool NeedExtraOp = false ; if ( auto * CI = dyn_cast < ConstantInt > ( SI -> getTrueValue ( ) ) ) { if ( CI -> isOne ( ) ) { Src1Val = SI -> getCondition ( ) ; Src2Val = SI -> getFalseValue ( ) ; Opc = AArch64 :: ORRWrr ; } else { assert ( CI -> isZero ( ) ) ; Src1Val = SI -> getFalseValue ( ) ; Src2Val = SI -> getCondition ( ) ; Opc = AArch64 :: BICWrr ; } } else if ( auto * CI = dyn_cast < ConstantInt > ( SI -> getFalseValue ( ) ) ) { if ( CI -> isOne ( ) ) { Src1Val = SI -> getCondition ( ) ; Src2Val = SI -> getTrueValue ( ) ; Opc = AArch64 :: ORRWrr ; NeedExtraOp = true ; } else { assert ( CI -> isZero ( ) ) ; Src1Val = SI -> getCondition ( ) ; Src2Val = SI -> getTrueValue ( ) ; Opc = AArch64 :: ANDWrr ; } } if ( ! Opc ) return false ; unsigned Src1Reg = getRegForValue ( Src1Val ) ; if ( ! Src1Reg ) return false ; bool Src1IsKill = hasTrivialKill ( Src1Val ) ; unsigned Src2Reg = getRegForValue ( Src2Val ) ; if ( ! Src2Reg ) return false ; bool Src2IsKill = hasTrivialKill ( Src2Val ) ; if ( NeedExtraOp ) { Src1Reg = emitLogicalOp_ri ( ISD :: XOR , MVT :: i32 , Src1Reg , Src1IsKill , 1 ) ; Src1IsKill = true ; } unsigned ResultReg = fastEmitInst_rr ( Opc , & AArch64 :: GPR32spRegClass , Src1Reg , Src1IsKill , Src2Reg , Src2IsKill ) ; updateValueMap ( SI , ResultReg ) ; return true ; } </s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


<s> bool HexagonInstrInfo :: isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumInstrs , const BranchProbability & Probability ) const { return ( NumInstrs <= 4 ) ; } </s>

Return true if it 's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion .


<s> bool SystemZRegisterInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


"immediate value expected for vector index"

tryParseRegister - parse one register if possible


On AArch64 we have an ABI defined safe buffer . This constant is used to determining the probe offset for alloca .


<s> MachineInstr * ARMBaseInstrInfo :: commuteInstruction ( MachineInstr * MI , bool NewMI ) const { switch ( MI -> getOpcode ( ) ) { case ARM :: MOVCCr : case ARM :: t2MOVCCr : { unsigned PredReg = 0 ; ARMCC :: CondCodes CC = getInstrPredicate ( MI , PredReg ) ; if ( CC == ARMCC :: AL || PredReg != ARM :: CPSR ) return NULL ; MI = TargetInstrInfoImpl :: commuteInstruction ( MI , NewMI ) ; if ( ! MI ) return NULL ; MI -> getOperand ( MI -> findFirstPredOperandIdx ( ) ) . setImm ( ARMCC :: getOppositeCondition ( CC ) ) ; return MI ; } } return TargetInstrInfoImpl :: commuteInstruction ( MI , NewMI ) ; } </s>

This method commutes the operands of the given machine instruction MI .

ARM ARM ARM::MOVCCr ARM::t2MOVCCr 0 ARMCC::CondCodes ARMCC::AL ARM::CPSR ARMCC::getOppositeCondition


<s> bool AMDGPUInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock * MBB = MI -> getParent ( ) ; int OffsetOpIdx = AMDGPU :: getNamedOperandIdx ( MI -> getOpcode ( ) , AMDGPU :: OpName :: addr ) ; int RegOpIdx = OffsetOpIdx + 1 ; int ChanOpIdx = AMDGPU :: getNamedOperandIdx ( MI -> getOpcode ( ) , AMDGPU :: OpName :: chan ) ; if ( isRegisterLoad ( * MI ) ) { int DstOpIdx = AMDGPU :: getNamedOperandIdx ( MI -> getOpcode ( ) , AMDGPU :: OpName :: dst ) ; unsigned RegIndex = MI -> getOperand ( RegOpIdx ) . getImm ( ) ; unsigned Channel = MI -> getOperand ( ChanOpIdx ) . getImm ( ) ; unsigned Address = calculateIndirectAddress ( RegIndex , Channel ) ; unsigned OffsetReg = MI -> getOperand ( OffsetOpIdx ) . getReg ( ) ; if ( OffsetReg == AMDGPU :: INDIRECT_BASE_ADDR ) { buildMovInstr ( MBB , MI , MI -> getOperand ( DstOpIdx ) . getReg ( ) , getIndirectAddrRegClass ( ) -> getRegister ( Address ) ) ; } else { buildIndirectRead ( MBB , MI , MI -> getOperand ( DstOpIdx ) . getReg ( ) , Address , OffsetReg ) ; } } else if ( isRegisterStore ( * MI ) ) { int ValOpIdx = AMDGPU :: getNamedOperandIdx ( MI -> getOpcode ( ) , AMDGPU :: OpName :: val ) ; AMDGPU :: getNamedOperandIdx ( MI -> getOpcode ( ) , AMDGPU :: OpName :: dst ) ; unsigned RegIndex = MI -> getOperand ( RegOpIdx ) . getImm ( ) ; unsigned Channel = MI -> getOperand ( ChanOpIdx ) . getImm ( ) ; unsigned Address = calculateIndirectAddress ( RegIndex , Channel ) ; unsigned OffsetReg = MI -> getOperand ( OffsetOpIdx ) . getReg ( ) ; if ( OffsetReg == AMDGPU :: INDIRECT_BASE_ADDR ) { buildMovInstr ( MBB , MI , getIndirectAddrRegClass ( ) -> getRegister ( Address ) , MI -> getOperand ( ValOpIdx ) . getReg ( ) ) ; } else { buildIndirectWrite ( MBB , MI , MI -> getOperand ( ValOpIdx ) . getReg ( ) , calculateIndirectAddress ( RegIndex , Channel ) , OffsetReg ) ; } } else { return false ; } MBB -> erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> void AArch64PassConfig :: addPreEmitPass ( ) { if ( EnableA53Fix835769 ) addPass ( createAArch64A53Fix835769 ( ) ) ; addPass ( createAArch64BranchRelaxation ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && Triple ( TM -> getTargetTriple ( ) ) . isOSBinFormatMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static bool ia64_attribute_takes_identifier_p ( const_tree attr_id ) { if ( is_attribute_p ( "model" , attr_id ) ) return true ; if ( is_attribute_p ( "common_object" , attr_id ) ) return true ; return false ; } </s>

Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain identifier as an argument , so the front end should n't look it up .


<s> static int mips_binary_cost ( rtx x , int single_cost , int double_cost , bool speed ) { int cost ; if ( GET_MODE_SIZE ( GET_MODE ( x ) ) == UNITS_PER_WORD * 2 ) cost = double_cost ; else cost = single_cost ; return ( cost + set_src_cost ( XEXP ( x , 0 ) , speed ) + rtx_cost ( XEXP ( x , 1 ) , GET_CODE ( x ) , 1 , speed ) ) ; } </s>

Return the cost of binary operation X , given that the instruction sequence for a word-sized or smaller operation has cost SINGLE_COST and that the sequence of a double-word operation has cost DOUBLE_COST . If SPEED is true , optimize for speed otherwise optimize for size .


<s> void WebAssemblyTargetWasmStreamer :: emitLocal ( ArrayRef < wasm :: ValType > Types ) { SmallVector < std :: pair < wasm :: ValType , uint32_t > , 4 > Grouped ; for ( auto Type : Types ) { if ( Grouped . empty ( ) || Grouped . back ( ) . first != Type ) Grouped . push_back ( std :: make_pair ( Type , 1 ) ) ; else ++ Grouped . back ( ) . second ; } Streamer . EmitULEB128IntValue ( Grouped . size ( ) ) ; for ( auto Pair : Grouped ) { Streamer . EmitULEB128IntValue ( Pair . second ) ; emitValueType ( Pair . first ) ; } } </s>

WebAssembly WebAssembly wasm::ValType wasm::ValType 4 1


"Thumb1 does not have ldr to high register"

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"AArch64 Conditional Compares"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static const MCAsmInfo * createMCAsmInfo ( const Target & T , StringRef TT ) { Triple TheTriple ( TT ) ; switch ( TheTriple . getOS ( ) ) { case Triple :: Darwin : return new ARMMCAsmInfoDarwin ( ) ; default : return new ARMELFMCAsmInfo ( ) ; } } </s>

createMCAsmInfo - Create a MCAsmInfo implementation for the specified target triple .


<s> const ARMRegisterInfo & getRegisterInfo ( ) const override { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
static
tree
spu_handle_vector_attribute
(
tree
*
node
,
tree
name
,
tree
args
ATTRIBUTE_UNUSED
,
int
flags
ATTRIBUTE_UNUSED
,
bool
*
no_add_attrs
)
{
tree
type
=
*
node
,
result
=
NULL_TREE
;
machine_mode
mode
;
int
unsigned_p
;
while
(
POINTER_TYPE_P
(
type
)
||
TREE_CODE
(
type
)
==
FUNCTION_TYPE
||
TREE_CODE
(
type
)
==
METHOD_TYPE
||
TREE_CODE
(
type
)
==
ARRAY_TYPE
)
type
=
TREE_TYPE
(
type
)
;
mode
=
TYPE_MODE
(
type
)
;
unsigned_p
=
TYPE_UNSIGNED
(
type
)
;
switch
(
mode
)
{
case
E_DImode
:
result
=
(
unsigned_p
unsigned_V2DI_type_node
:
V2DI_type_node
)
;
break
;
case
E_SImode
:
result
=
(
unsigned_p
unsigned_V4SI_type_node
:
V4SI_type_node
)
;
break
;
case
E_HImode
:
result
=
(
unsigned_p
unsigned_V8HI_type_node
:
V8HI_type_node
)
;
break
;
case
E_QImode
:
result
=
(
unsigned_p
unsigned_V16QI_type_node
:
V16QI_type_node
)
;
break
;
case
E_SFmode
:
result
=
V4SF_type_node
;
break
;
case
E_DFmode
:
result
=
V2DF_type_node
;
break
;
default
:
break
;
}
if
(
result
&&
result
!=
type
&&
TYPE_QUALS
(
type
)
)
result
=
build_qualified_type
(
result
,
TYPE_QUALS
(
type
)
)
;
*
no_add_attrs
=
true
;
if
(
!
result
)
warning
(
0
,
"%qE attribute ignored"
,
name
)
;
else
*
node
=
lang_hooks
.
types
.
reconstruct_complex_type
(
*
node
,
result
)
;
return
NULL_TREE
;
}
</s>


<s> const value_var * get ( ) const { return this ; } </s>

Get the generated Value for a given VPValue and given Part and Lane .


<s> static void store_reg_modify ( int base , int reg , HOST_WIDE_INT mod ) { rtx basereg , srcreg , delta ; rtx_insn * insn ; gcc_assert ( VAL_14_BITS_P ( mod ) ) ; basereg = gen_rtx_REG ( Pmode , base ) ; srcreg = gen_rtx_REG ( word_mode , reg ) ; delta = GEN_INT ( mod ) ; insn = emit_insn ( gen_post_store ( basereg , srcreg , delta ) ) ; if ( DO_FRAME_NOTES ) { RTX_FRAME_RELATED_P ( insn ) = 1 ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) ) = 1 ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , 0 , 1 ) ) = 1 ; } } </s>

Emit RTL to store REG at the memory location specified by BASE and then add MOD to BASE . MOD must be < = 8k .


<s> bool mem_operand_gpr ( rtx op , machine_mode mode ) { unsigned HOST_WIDE_INT offset ; int extra ; rtx addr = XEXP ( op , 0 ) ; if ( TARGET_UPDATE && ( GET_CODE ( addr ) == PRE_INC || GET_CODE ( addr ) == PRE_DEC ) && mode_supports_pre_incdec_p ( mode ) && legitimate_indirect_address_p ( XEXP ( addr , 0 ) , false ) ) return true ; if ( address_is_prefixed ( addr , mode , NON_PREFIXED_DS ) ) return true ; if ( TARGET_MACHO && GET_CODE ( addr ) == LO_SUM ) return darwin_rs6000_legitimate_lo_sum_const_p ( XEXP ( addr , 1 ) , mode ) ; if ( ! rs6000_offsettable_memref_p ( op , mode , false ) ) return false ; op = address_offset ( addr ) ; if ( op == NULL_RTX ) return true ; offset = INTVAL ( op ) ; if ( TARGET_POWERPC64 && ( offset & 3 ) != 0 ) return false ; extra = GET_MODE_SIZE ( mode ) - UNITS_PER_WORD ; if ( extra < 0 ) extra = 0 ; if ( GET_CODE ( addr ) == LO_SUM ) offset = ( ( offset & 0xffff ) ^ 0x8000 ) - 0x8000 ; return SIGNED_16BIT_OFFSET_EXTRA_P ( offset , extra ) ; } </s>

Return true if the MEM operand is a memory operand suitable for use with a ( full width , possibly multiple ) gpr load/store . On powerpc64 this means the offset must be divisible by 4 . Implements ' Y ' constraint . Accept direct , indexed , offset , lo_sum and tocref . Since this is a constraint function we know the operand has satisfied a suitable memory predicate . Offsetting a lo_sum should not be allowed , except where we know by alignment that a 32k boundary is not crossed . Note that by `` offsetting '' here we mean a further offset to access parts of the MEM . It 's fine to have a lo_sum where the inner address is offset from a sym , since the same sym+offset will appear in the high part of the address calculation .


<s> inline static bool isMem ( const MachineInstr & MI , unsigned Op ) { if ( MI . getOperand ( Op ) . isFI ( ) ) return true ; return Op + X86 :: AddrNumOperands <= MI . getNumOperands ( ) && MI . getOperand ( Op + X86 :: AddrSegmentReg ) . isReg ( ) && isLeaMem ( MI , Op ) ; } </s>


<s>
unsigned
ARMBaseInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
getLastNonDebugInstr
(
)
;
if
(
I
==
MBB
.
end
(
)
)
return
0
;
if
(
!
isUncondBranchOpcode
(
I
->
getOpcode
(
)
)
&&
!
isCondBranchOpcode
(
I
->
getOpcode
(
)
)
&&
I
->
getOpcode
(
)
!=
ARM
::
t2LoopEnd
)
return
0
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
if
(
I
==
MBB
.
begin
(
)
)
return
1
;
I
;
if
(
!
isCondBranchOpcode
(
I
->
getOpcode
(
)
)
&&
I
->
getOpcode
(
)
!=
ARM
::
t2LoopEnd
)
return
1
;
I
->
eraseFromParent
(
)
;
return
2
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s>
static
int
match_basetype
(
typeinfo
*
typedata
)
{
consume_whitespace
(
)
;
int
oldpos
=
pos
;
char
*
token
=
match_identifier
(
)
;
if
(
!
token
)
{
diag
(
pos
,
"missing base type in return type\n"
)
;
return
0
;
}
if
(
!
strcmp
(
token
,
"char"
)
)
typedata
->
base
=
BT_CHAR
;
else
if
(
!
strcmp
(
token
,
"short"
)
)
typedata
->
base
=
BT_SHORT
;
else
if
(
!
strcmp
(
token
,
"int"
)
)
typedata
->
base
=
BT_INT
;
else
if
(
!
strcmp
(
token
,
"long"
)
)
{
consume_whitespace
(
)
;
oldpos
=
pos
;
char
*
mustbelongordbl
=
match_identifier
(
)
;
if
(
!
mustbelongordbl
)
typedata
->
base
=
BT_LONG
;
else
if
(
!
strcmp
(
mustbelongordbl
,
"long"
)
)
typedata
->
base
=
BT_LONGLONG
;
else
if
(
!
strcmp
(
mustbelongordbl
,
"double"
)
)
typedata
->
base
=
BT_LONGDOUBLE
;
else
{
typedata
->
base
=
BT_LONG
;
pos
=
oldpos
;
}
}
else
if
(
!
strcmp
(
token
,
"float"
)
)
typedata
->
base
=
BT_FLOAT
;
else
if
(
!
strcmp
(
token
,
"double"
)
)
typedata
->
base
=
BT_DOUBLE
;
else
if
(
!
strcmp
(
token
,
"__int128"
)
)
typedata
->
base
=
BT_INT128
;
else
if
(
!
strcmp
(
token
,
"_Float128"
)
)
typedata
->
base
=
BT_FLOAT128
;
else
if
(
!
strcmp
(
token
,
"bool"
)
)
typedata
->
base
=
BT_BOOL
;
else
if
(
!
strcmp
(
token
,
"string"
)
)
typedata
->
base
=
BT_STRING
;
else
if
(
!
strcmp
(
token
,
"_Decimal32"
)
)
typedata
->
base
=
BT_DECIMAL32
;
else
if
(
!
strcmp
(
token
,
"_Decimal64"
)
)
typedata
->
base
=
BT_DECIMAL64
;
else
if
(
!
strcmp
(
token
,
"_Decimal128"
)
)
typedata
->
base
=
BT_DECIMAL128
;
else
if
(
!
strcmp
(
token
,
"__ibm128"
)
)
typedata
->
base
=
BT_IBM128
;
else
{
diag
(
oldpos
,
"unrecognized base type\n"
)
;
return
0
;
}
handle_pointer
(
typedata
)
;
return
1
;
}
</s>

Match one of the allowable base types . Consumes one token unless the token is `` long '' , which must be paired with a second `` long '' . Optionally consumes a following ' * ' token for pointers . Return 1 for success , 0 for failure .


<s> void X86FrameLowering :: orderFrameObjects ( const MachineFunction & MF , SmallVectorImpl < int > & ObjectsToAllocate ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ObjectsToAllocate . empty ( ) ) return ; std :: vector < X86FrameSortingObject > SortingObjects ( MFI . getObjectIndexEnd ( ) ) ; for ( auto & Obj : ObjectsToAllocate ) { SortingObjects [ Obj ] . IsValid = true ; SortingObjects [ Obj ] . ObjectIndex = Obj ; SortingObjects [ Obj ] . ObjectAlignment = MFI . getObjectAlign ( Obj ) ; int ObjectSize = MFI . getObjectSize ( Obj ) ; if ( ObjectSize == 0 ) SortingObjects [ Obj ] . ObjectSize = 4 ; else SortingObjects [ Obj ] . ObjectSize = ObjectSize ; } for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( MI . isDebugInstr ( ) ) continue ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isFI ( ) ) continue ; int Index = MO . getIndex ( ) ; if ( Index >= 0 && Index < MFI . getObjectIndexEnd ( ) && SortingObjects [ Index ] . IsValid ) SortingObjects [ Index ] . ObjectNumUses ++ ; } } } llvm :: stable_sort ( SortingObjects , X86FrameSortingComparator ( ) ) ; int i = 0 ; for ( auto & Obj : SortingObjects ) { if ( ! Obj . IsValid ) break ; ObjectsToAllocate [ i ++ ] = Obj . ObjectIndex ; } if ( ! TRI -> hasStackRealignment ( MF ) && hasFP ( MF ) ) std :: reverse ( ObjectsToAllocate . begin ( ) , ObjectsToAllocate . end ( ) ) ; } </s>


<s> static bool isEqual ( const CSKYTargetStreamer :: SymbolIndex & A , const CSKYTargetStreamer :: SymbolIndex & B ) { return A . sym == B . sym && A . kind == B . kind ; } </s>

isEqual - Compares two trees for structural equality and returns true if they are equal .


<s> void SparcFrameLowering :: emitPrologue ( MachineFunction & MF ) const { SparcMachineFunctionInfo * FuncInfo = MF . getInfo < SparcMachineFunctionInfo > ( ) ; MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const SparcInstrInfo & TII = * static_cast < const SparcInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; unsigned SAVEri = SP :: SAVEri ; unsigned SAVErr = SP :: SAVErr ; if ( FuncInfo -> isLeafProc ( ) ) { if ( NumBytes == 0 ) return ; SAVEri = SP :: ADDri ; SAVErr = SP :: ADDrr ; } NumBytes = - MF . getSubtarget < SparcSubtarget > ( ) . getAdjustedFrameSize ( NumBytes ) ; emitSPAdjustment ( MF , MBB , MBBI , NumBytes , SAVErr , SAVEri ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; unsigned regFP = MRI -> getDwarfRegNum ( SP :: I6 , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , regFP ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createWindowSave ( nullptr ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; unsigned regInRA = MRI -> getDwarfRegNum ( SP :: I7 , true ) ; unsigned regOutRA = MRI -> getDwarfRegNum ( SP :: O7 , true ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createRegister ( nullptr , regOutRA , regInRA ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Sparc Sparc Sparc Sparc Sparc Sparc SP::SAVEri SP::SAVErr 0 SP::ADDri SP::ADDrr Sparc SP SP::I6 SP::I7 SP::O7


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> static void moxie_operand_lossage ( const char * msgid , rtx op ) { debug_rtx ( op ) ; output_operand_lossage ( "%s" , msgid ) ; } </s>

Emit an error message when we 're in an asm , and a fatal error for `` normal '' insns . Formatted output is n't easily implemented , since we use output_operand_lossage to output the actual message and handle the categorization of the error .


initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool PPCAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'c' : printOperand ( MI , OpNo , O ) ; return false ; case 'L' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + 1 == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + 1 ) . isReg ( ) ) return true ; ++ OpNo ; break ; case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << "i" ; return false ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> void ix86_expand_vector_init ( bool mmx_ok , rtx target , rtx vals ) { machine_mode mode = GET_MODE ( target ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; int n_elts = GET_MODE_NUNITS ( mode ) ; int n_var = 0 , one_var = - 1 ; bool all_same = true , all_const_zero = true ; int i ; rtx x ; for ( i = 0 ; i < n_elts ; ++ i ) { x = XVECEXP ( vals , 0 , i ) ; if ( ! ( CONST_SCALAR_INT_P ( x ) || CONST_DOUBLE_P ( x ) || CONST_FIXED_P ( x ) ) ) n_var ++ , one_var = i ; else if ( x != CONST0_RTX ( inner_mode ) ) all_const_zero = false ; if ( i > 0 && ! rtx_equal_p ( x , XVECEXP ( vals , 0 , 0 ) ) ) all_same = false ; } if ( n_var == 0 ) { emit_move_insn ( target , gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , 0 ) ) ) ; return ; } if ( all_same && ix86_expand_vector_init_duplicate ( mmx_ok , mode , target , XVECEXP ( vals , 0 , 0 ) ) ) return ; if ( n_var == 1 ) { if ( all_const_zero && ix86_expand_vector_init_one_nonzero ( mmx_ok , mode , target , XVECEXP ( vals , 0 , one_var ) , one_var ) ) return ; if ( ix86_expand_vector_init_one_var ( mmx_ok , mode , target , vals , one_var ) ) return ; } ix86_expand_vector_init_general ( mmx_ok , mode , target , vals ) ; } </s>

Initialize vector TARGET via VALS . Suppress the use of MMX instructions unless MMX_OK is true .


<s> static bool unsafe_rename_p ( unsigned regno ) { if ( regno <= R8_REGNUM || ( regno >= V0_REGNUM && regno < V8_REGNUM ) ) return true ; switch ( regno ) { case LR_REGNUM : case HARD_FRAME_POINTER_REGNUM : case FRAME_POINTER_REGNUM : case STACK_POINTER_REGNUM : return true ; } return false ; } </s>

Return true if REGNO is not safe to rename .


<s> const MipsRegisterInfo * getRegisterInfo ( ) const override { return getSubtargetImpl ( ) -> getRegisterInfo ( ) ; } </s>


<s> static void * c6x_alloc_sched_context ( void ) { return xmalloc ( sizeof ( struct c6x_sched_context ) ) ; } </s>

Allocate store for new scheduling context .


<s> unsigned PPCFrameLowering :: getTOCSaveOffset ( ) const { return TOCSaveOffset ; } </s>

getTOCSaveOffset - Return the previous frame offset to save the TOC register � ? 64-bit SVR4 ABI only .


<s> void X86AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { X86MCInstLower MCInstLowering ( OutContext , Mang , * this ) ; switch ( MI -> getOpcode ( ) ) { case TargetOpcode :: DBG_VALUE : if ( isVerbose ( ) && OutStreamer . hasRawTextSupport ( ) ) { std :: string TmpStr ; raw_string_ostream OS ( TmpStr ) ; PrintDebugValueComment ( MI , OS ) ; OutStreamer . EmitRawText ( StringRef ( OS . str ( ) ) ) ; } return ; case X86 :: MOVPC32r : { MCInst TmpInst ; MCSymbol * PICBase = MCInstLowering . GetPICBaseSymbol ( ) ; TmpInst . setOpcode ( X86 :: CALLpcrel32 ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( PICBase , OutContext ) ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; OutStreamer . EmitLabel ( PICBase ) ; TmpInst . setOpcode ( X86 :: POP32r ) ; TmpInst . getOperand ( 0 ) = MCOperand :: CreateReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; return ; } case X86 :: ADD32ri : { if ( MI -> getOperand ( 2 ) . getTargetFlags ( ) != X86II :: MO_GOT_ABSOLUTE_ADDRESS ) break ; MCSymbol * DotSym = OutContext . CreateTempSymbol ( ) ; OutStreamer . EmitLabel ( DotSym ) ; MCSymbol * OpSym = MCInstLowering . GetSymbolFromOperand ( MI -> getOperand ( 2 ) ) ; const MCExpr * DotExpr = MCSymbolRefExpr :: Create ( DotSym , OutContext ) ; const MCExpr * PICBase = MCSymbolRefExpr :: Create ( MCInstLowering . GetPICBaseSymbol ( ) , OutContext ) ; DotExpr = MCBinaryExpr :: CreateSub ( DotExpr , PICBase , OutContext ) ; DotExpr = MCBinaryExpr :: CreateAdd ( MCSymbolRefExpr :: Create ( OpSym , OutContext ) , DotExpr , OutContext ) ; MCInst TmpInst ; TmpInst . setOpcode ( X86 :: ADD32ri ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( 1 ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( DotExpr ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; return ; } } MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; OutStreamer . EmitInstruction ( TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


"invalid feature modifier %qs for 'cpu' target %s"

Handle the argument CPU_STR to the cpu= target attribute . PRAGMA_OR_ATTR is used in potential error messages .


<s> bool ARMBaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; const ARMFrameLowering * TFI = getFrameLowering ( MF ) ; if ( MF . getFunction ( ) -> hasFnAttribute ( "no-realign-stack" ) ) return false ; if ( AFI -> isThumb1OnlyFunction ( ) ) return false ; if ( ! MRI -> canReserveReg ( getFramePointerReg ( MF . getSubtarget < ARMSubtarget > ( ) ) ) ) return false ; if ( TFI -> hasReservedCallFrame ( MF ) ) return true ; return MRI -> canReserveReg ( BasePtr ) ; } </s>

True if the stack can be realigned for the target .

ARM ARM ARM ARM ARM "no-realign-stack" ARM


<s> static int ix86_address_cost ( rtx x ) { struct ix86_address parts ; int cost = 1 ; int ok = ix86_decompose_address ( x , & parts ) ; gcc_assert ( ok ) ; if ( parts . base && GET_CODE ( parts . base ) == SUBREG ) parts . base = SUBREG_REG ( parts . base ) ; if ( parts . index && GET_CODE ( parts . index ) == SUBREG ) parts . index = SUBREG_REG ( parts . index ) ; if ( parts . disp && parts . disp != const0_rtx ) cost -- ; if ( parts . seg != SEG_DEFAULT ) cost -- ; if ( ( parts . base && ( ! REG_P ( parts . base ) || REGNO ( parts . base ) >= FIRST_PSEUDO_REGISTER ) ) || ( parts . index && ( ! REG_P ( parts . index ) || REGNO ( parts . index ) >= FIRST_PSEUDO_REGISTER ) ) ) cost ++ ; if ( parts . base && ( ! REG_P ( parts . base ) || REGNO ( parts . base ) >= FIRST_PSEUDO_REGISTER ) && parts . index && ( ! REG_P ( parts . index ) || REGNO ( parts . index ) >= FIRST_PSEUDO_REGISTER ) && parts . base != parts . index ) cost ++ ; if ( TARGET_K6 && ( ( ! parts . disp && parts . base && parts . index && parts . scale != 1 ) || ( parts . disp && ! parts . base && parts . index && parts . scale != 1 ) || ( ! parts . disp && parts . base && parts . index && parts . scale == 1 ) ) ) cost += 10 ; return cost ; } </s>

Return cost of the memory address x . For i386 , it is better to use a complex address than let gcc copy the address into a reg and make a new pseudo . But not if the address requires to two regs - that would mean more pseudos with longer lifetimes .


<s> bool SystemZAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & OS ) { if ( ExtraCode && * ExtraCode == 'n' ) { if ( ! MI -> getOperand ( OpNo ) . isImm ( ) ) return true ; OS << - int64_t ( MI -> getOperand ( OpNo ) . getImm ( ) ) ; } else { SystemZMCInstLower Lower ( Mang , MF -> getContext ( ) , * this ) ; MCOperand MO ( Lower . lowerOperand ( MI -> getOperand ( OpNo ) ) ) ; SystemZInstPrinter :: printOperand ( MO , OS ) ; } return false ; } </s>


<s> void TPCMCCodeEmitter :: EmitInstruction ( APInt & Instruction , unsigned Size , raw_ostream & OS ) const { for ( unsigned Start = 0 ; Start < Size ; ) { unsigned RemainedBits = Size - Start ; if ( RemainedBits >= 64 ) { APInt Chunk = Instruction . lshr ( Start ) . trunc ( 64 ) ; EmitConstant ( Chunk . getZExtValue ( ) , 8 , OS ) ; Start += 64 ; } else { unsigned ChunkSize = RemainedBits / 8 ; assert ( ChunkSize * 8 == RemainedBits ) ; APInt Chunk = Instruction . lshr ( Start ) . trunc ( RemainedBits ) ; EmitConstant ( Chunk . getZExtValue ( ) , ChunkSize , OS ) ; break ; } } curPos += ( Size / 8 ) ; } </s>


<s> bool arm_tls_referenced_p ( rtx x ) { if ( ! TARGET_HAVE_TLS ) return false ; return for_each_rtx ( & x , arm_tls_operand_p_1 , NULL ) ; } </s>

Return TRUE if X contains any TLS symbol references .


<s> const MipsAnalyzeImmediate :: InstSeq & MipsAnalyzeImmediate :: Analyze ( int64_t Imm , unsigned Size , bool LastInstrIsADDiu ) { this -> Size = Size ; if ( Size == 32 ) { ADDiu = Mips :: ADDiu ; ORi = Mips :: ORi ; SLL = Mips :: SLL ; LUi = Mips :: LUi ; } else { ADDiu = Mips :: DADDiu ; ORi = Mips :: ORi64 ; SLL = Mips :: DSLL ; LUi = Mips :: LUi64 ; } InstSeqLs SeqLs ; if ( LastInstrIsADDiu | ! Imm ) GetInstSeqLsADDiu ( Imm , Size , SeqLs ) ; else GetInstSeqLs ( Imm , Size , SeqLs ) ; GetShortestSeq ( SeqLs , Insts ) ; return Insts ; } </s>

Analyze - Get an instruction sequence to load immediate Imm .

Mips Mips Mips 32 Mips::ADDiu Mips::ORi Mips::SLL Mips::LUi Mips::DADDiu Mips::ORi64 Mips::DSLL Mips::LUi64


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


"***** AArch64SpeculationHardening - track control flow *****\n"

runOnMachineFunction - Emit the function body .


<s>
void
PIC16InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
;
if
(
PIC16
::
FSR16RegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PIC16
::
copy_fsr
;
else
if
(
PIC16
::
GPRRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PIC16
::
copy_w
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> bool csky_emit_compare_float ( enum rtx_code code , rtx op0 , rtx op1 ) { rtx cc_reg = gen_rtx_REG ( CCmode , CSKY_CC_REGNUM ) ; bool invert ; machine_mode mode = GET_MODE ( op1 ) ; if ( op1 != CONST0_RTX ( mode ) ) op1 = force_reg ( mode , op1 ) ; invert = false ; switch ( code ) { case EQ : code = NE ; invert = true ; break ; case GT : case LT : case LE : if ( op1 == CONST0_RTX ( mode ) && ( CSKY_ISA_FEATURE_GET ( fpv2_sf ) || CSKY_ISA_FEATURE_GET ( fpv2_df ) || CSKY_ISA_FEATURE_GET ( fpv2_divd ) ) ) op1 = force_reg ( mode , op1 ) ; break ; case ORDERED : code = UNORDERED ; invert = true ; break ; default : break ; } emit_insn ( gen_rtx_SET ( cc_reg , gen_rtx_fmt_ee ( code , CCmode , op0 , op1 ) ) ) ; return invert ; } </s>

Emit a comparison insn for float values . Return true if the comparison is inverted .


"256-bit vector operations only available in AVX2"

Change the opcode of MI to execute in Domain .


<s> bool ix86_extract_perm_from_pool_constant ( int * perm , rtx mem ) { machine_mode mode = GET_MODE ( mem ) ; int nelt = GET_MODE_NUNITS ( mode ) ; if ( ! INTEGRAL_MODE_P ( mode ) ) return false ; if ( ! ( MEM_P ( mem ) ) || ! SYMBOL_REF_P ( XEXP ( mem , 0 ) ) || ! CONSTANT_POOL_ADDRESS_P ( XEXP ( mem , 0 ) ) ) return false ; rtx constant = get_pool_constant ( XEXP ( mem , 0 ) ) ; if ( GET_CODE ( constant ) != CONST_VECTOR ) return false ; if ( GET_MODE ( constant ) != mode ) { constant = simplify_subreg ( mode , constant , GET_MODE ( constant ) , 0 ) ; if ( constant == nullptr || GET_CODE ( constant ) != CONST_VECTOR ) return false ; } for ( int i = 0 ; i != nelt ; i ++ ) perm [ i ] = UINTVAL ( XVECEXP ( constant , 0 , i ) ) ; return true ; } </s>

Return true if mem is pool constant which contains a const_vector perm index , assign the index to PERM .


<s> unsigned VETargetLowering :: getJumpTableEncoding ( ) const { if ( isPositionIndependent ( ) ) return MachineJumpTableInfo :: EK_Custom32 ; return TargetLowering :: getJumpTableEncoding ( ) ; } </s>

Return the entry encoding for a jump table in the current function .


<s> static void ix86_seh_fixup_eh_fallthru ( void ) { edge e ; edge_iterator ei ; FOR_EACH_EDGE ( e , ei , EXIT_BLOCK_PTR_FOR_FN ( cfun ) -> preds ) { rtx_insn * insn , * next ; for ( insn = BB_END ( e -> src ) ; insn != NULL ; insn = PREV_INSN ( insn ) ) if ( NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_EPILOGUE_BEG ) break ; if ( insn == NULL ) continue ; insn = prev_active_insn ( insn ) ; if ( insn == NULL || ! can_throw_internal ( insn ) ) continue ; for ( next = NEXT_INSN ( insn ) ; next != NULL ; next = NEXT_INSN ( next ) ) if ( NOTE_P ( next ) && NOTE_KIND ( next ) == NOTE_INSN_VAR_LOCATION ) insn = next ; else break ; emit_insn_after ( gen_nops ( const1_rtx ) , insn ) ; } } </s>

Fix up a Windows system unwinder issue . If an EH region falls through into the epilogue , the Windows system unwinder will apply epilogue logic and produce incorrect offsets . This can be avoided by adding a nop between the last insn that can throw and the first insn of the epilogue .


<s> static int loongarch_issue_rate ( void ) { if ( ( unsigned long ) LARCH_ACTUAL_TUNE < N_TUNE_TYPES ) return loongarch_cpu_issue_rate [ LARCH_ACTUAL_TUNE ] ; else return 1 ; } </s>

Return the number of instructions that can be issued per cycle .


<s> static MachineBasicBlock * clone ( MachineBasicBlock * srcBlk ) { MachineFunction * func = srcBlk -> getParent ( ) ; MachineBasicBlock * newBlk = func -> CreateMachineBasicBlock ( ) ; func -> push_back ( newBlk ) ; for ( MachineBasicBlock :: iterator iter = srcBlk -> begin ( ) , iterEnd = srcBlk -> end ( ) ; iter != iterEnd ; ++ iter ) { MachineInstr * instr = func -> CloneMachineInstr ( iter ) ; newBlk -> push_back ( instr ) ; } return newBlk ; } </s>

Make a functionally equivalent copy of this MachineFunctionInfo in MF .


"Alloca should always return a pointer."

Emit an alloca address in a register using target-specific logic .


<s> TargetFrameLowering :: DwarfFrameBase WebAssemblyFrameLowering :: getDwarfFrameBase ( const MachineFunction & MF ) const { DwarfFrameBase Loc ; Loc . Kind = DwarfFrameBase :: WasmFrameBase ; const WebAssemblyFunctionInfo & MFI = * MF . getInfo < WebAssemblyFunctionInfo > ( ) ; if ( needsSP ( MF ) && MFI . isFrameBaseVirtual ( ) ) { unsigned LocalNum = MFI . getFrameBaseLocal ( ) ; Loc . Location . WasmLoc = { WebAssembly :: TI_LOCAL_START , LocalNum } ; } else { Loc . Location . WasmLoc = { WebAssembly :: TI_GLOBAL_START , 0 } ; } return Loc ; } </s>

Return the frame base information to be encoded in the DWARF subprogram debug info .


<s> void SITargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { switch ( N -> getOpcode ( ) ) { case ISD :: INSERT_VECTOR_ELT : { if ( SDValue Res = lowerINSERT_VECTOR_ELT ( SDValue ( N , 0 ) , DAG ) ) Results . push_back ( Res ) ; return ; } case ISD :: EXTRACT_VECTOR_ELT : { if ( SDValue Res = lowerEXTRACT_VECTOR_ELT ( SDValue ( N , 0 ) , DAG ) ) Results . push_back ( Res ) ; return ; } case ISD :: INTRINSIC_WO_CHAIN : { unsigned IID = cast < ConstantSDNode > ( N -> getOperand ( 0 ) ) -> getZExtValue ( ) ; if ( IID == Intrinsic :: amdgcn_cvt_pkrtz ) { SDValue Src0 = N -> getOperand ( 1 ) ; SDValue Src1 = N -> getOperand ( 2 ) ; SDLoc SL ( N ) ; SDValue Cvt = DAG . getNode ( AMDGPUISD :: CVT_PKRTZ_F16_F32 , SL , MVT :: i32 , Src0 , Src1 ) ; Results . push_back ( DAG . getNode ( ISD :: BITCAST , SL , MVT :: v2f16 , Cvt ) ) ; return ; } break ; } case ISD :: INTRINSIC_W_CHAIN : { SDValue Chain ; if ( SDValue Res = lowerIntrinsicWChain_IllegalReturnType ( SDValue ( N , 0 ) , Chain , DAG ) ) { Results . push_back ( Res ) ; Results . push_back ( Chain ) ; return ; } break ; } case ISD :: SELECT : { SDLoc SL ( N ) ; EVT VT = N -> getValueType ( 0 ) ; EVT NewVT = getEquivalentMemType ( * DAG . getContext ( ) , VT ) ; SDValue LHS = DAG . getNode ( ISD :: BITCAST , SL , NewVT , N -> getOperand ( 1 ) ) ; SDValue RHS = DAG . getNode ( ISD :: BITCAST , SL , NewVT , N -> getOperand ( 2 ) ) ; EVT SelectVT = NewVT ; if ( NewVT . bitsLT ( MVT :: i32 ) ) { LHS = DAG . getNode ( ISD :: ANY_EXTEND , SL , MVT :: i32 , LHS ) ; RHS = DAG . getNode ( ISD :: ANY_EXTEND , SL , MVT :: i32 , RHS ) ; SelectVT = MVT :: i32 ; } SDValue NewSelect = DAG . getNode ( ISD :: SELECT , SL , SelectVT , N -> getOperand ( 0 ) , LHS , RHS ) ; if ( NewVT != SelectVT ) NewSelect = DAG . getNode ( ISD :: TRUNCATE , SL , NewVT , NewSelect ) ; Results . push_back ( DAG . getNode ( ISD :: BITCAST , SL , VT , NewSelect ) ) ; return ; } default : break ; } } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> bool isCtlzFast ( ) const override { return true ; } </s>

Return true if ctlz instruction is fast .


<s>
static
void
adjust_xxpermdi
(
rtx_insn
*
insn
)
{
rtx
set
=
PATTERN
(
insn
)
;
rtx
select
=
XEXP
(
set
,
1
)
;
rtx
concat
=
XEXP
(
select
,
0
)
;
rtx
src0
=
XEXP
(
concat
,
0
)
;
XEXP
(
concat
,
0
)
=
XEXP
(
concat
,
1
)
;
XEXP
(
concat
,
1
)
=
src0
;
rtx
parallel
=
XEXP
(
select
,
1
)
;
int
lane0
=
INTVAL
(
XVECEXP
(
parallel
,
0
,
0
)
)
;
int
lane1
=
INTVAL
(
XVECEXP
(
parallel
,
0
,
1
)
)
;
int
new_lane0
=
3
lane1
;
int
new_lane1
=
3
lane0
;
XVECEXP
(
parallel
,
0
,
0
)
=
GEN_INT
(
new_lane0
)
;
XVECEXP
(
parallel
,
0
,
1
)
=
GEN_INT
(
new_lane1
)
;
INSN_CODE
(
insn
)
=
1
;
df_insn_rescan
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Changing lanes for xxpermdi %d\n"
,
INSN_UID
(
insn
)
)
;
}
</s>

Given OP that contains an XXPERMDI operation ( that is not a doubleword swap ) , reverse the order of the source operands and adjust the indices of the source lanes to account for doubleword reversal .


<s> static rtx get_mem_base_reg ( rtx mem ) { const char * fmt ; while ( ! MEM_P ( mem ) ) { if ( GET_RTX_CLASS ( GET_CODE ( mem ) ) != RTX_UNARY || GET_CODE ( mem ) == BSWAP ) return NULL_RTX ; fmt = GET_RTX_FORMAT ( GET_CODE ( mem ) ) ; if ( fmt [ 0 ] != 'e' ) return NULL_RTX ; mem = XEXP ( mem , 0 ) ; if ( mem == NULL_RTX ) return NULL_RTX ; } if ( ! MEM_SIZE_KNOWN_P ( mem ) ) return NULL_RTX ; rtx addr_rtx = ( XEXP ( mem , 0 ) ) ; if ( GET_CODE ( addr_rtx ) == PRE_MODIFY ) addr_rtx = XEXP ( addr_rtx , 1 ) ; while ( GET_CODE ( addr_rtx ) == PLUS && CONST_INT_P ( XEXP ( addr_rtx , 1 ) ) ) addr_rtx = XEXP ( addr_rtx , 0 ) ; if ( ! REG_P ( addr_rtx ) ) return NULL_RTX ; return addr_rtx ; } </s>

Return the register used as the base register of MEM , if the instruction has a pc-relative form . We look for BSWAP to rule out LFIWAX/LFIWZX/STFIWX , and ROTATE/VEC_SELECT are RTX_EXTRA not RTX_UNARY which rules out lxvd2x . This excludes instructions that do not have a pc-relative form .


<s> static void cr16_create_dwarf_for_multi_push ( rtx insn ) { rtx dwarf , reg , tmp ; int i , j , from , to , word_cnt , dwarf_par_index , inc ; machine_mode mode ; int num_regs = 0 , offset = 0 , split_here = 0 , total_push_bytes = 0 ; for ( i = 0 ; i <= current_frame_info . last_reg_to_save ; ++ i ) { if ( current_frame_info . save_regs [ i ] ) { ++ num_regs ; if ( i < CR16_FIRST_DWORD_REGISTER ) total_push_bytes += 2 ; else total_push_bytes += 4 ; } } if ( ! num_regs ) return ; dwarf = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( num_regs + 1 ) ) ; dwarf_par_index = num_regs ; from = current_frame_info . last_reg_to_save + 1 ; to = current_frame_info . last_reg_to_save ; word_cnt = 0 ; for ( i = current_frame_info . last_reg_to_save ; i >= 0 ; ) { if ( ! current_frame_info . save_regs [ i ] || 0 == i || split_here ) { if ( 0 == i && current_frame_info . save_regs [ i ] ) from = 0 ; for ( j = to ; j >= from ; -- j ) { if ( j < CR16_FIRST_DWORD_REGISTER ) { mode = HImode ; inc = 1 ; } else { mode = SImode ; inc = 2 ; } reg = gen_rtx_REG ( mode , j ) ; offset += 2 * inc ; tmp = gen_rtx_SET ( gen_frame_mem ( mode , plus_constant ( Pmode , stack_pointer_rtx , total_push_bytes - offset ) ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , dwarf_par_index -- ) = tmp ; } from = i ; to = -- i ; split_here = 0 ; word_cnt = 0 ; continue ; } if ( i != RETURN_ADDRESS_REGNUM ) { inc = ( i < CR16_FIRST_DWORD_REGISTER ) ? 1 : 2 ; if ( word_cnt + inc >= MAX_COUNT || FRAME_POINTER_REGNUM == i ) { split_here = 1 ; from = i ; continue ; } word_cnt += inc ; } from = i -- ; } tmp = gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( SImode , stack_pointer_rtx , GEN_INT ( - offset ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , 0 ) = tmp ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , dwarf ) ; } </s>

Generate DWARF2 annotation for multi-push instruction .


<s> void nds32_expand_epilogue_v3pop ( bool sibcall_p ) { int sp_adjust ; unsigned Rb , Re ; nds32_compute_stack_frame ( ) ; emit_insn ( gen_blockage ( ) ) ; if ( cfun -> machine -> naked_p ) { if ( ! sibcall_p ) emit_jump_insn ( gen_return_internal ( ) ) ; return ; } Rb = cfun -> machine -> callee_saved_first_gpr_regno ; Re = cfun -> machine -> callee_saved_last_gpr_regno ; sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; if ( satisfies_constraint_Iu08 ( GEN_INT ( sp_adjust ) ) && NDS32_DOUBLE_WORD_ALIGN_P ( sp_adjust ) && ! cfun -> calls_alloca ) { if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { int fpr_position = cfun -> machine -> local_size + cfun -> machine -> out_args_size ; nds32_emit_v3pop_fpr_callee_saved ( fpr_position ) ; } nds32_emit_stack_v3pop ( Rb , Re , sp_adjust ) ; } else { if ( frame_pointer_needed ) { sp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size ; if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { sp_adjust = sp_adjust + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , hard_frame_pointer_rtx , - 1 * sp_adjust ) ; nds32_emit_v3pop_fpr_callee_saved ( 0 ) ; } else { nds32_emit_adjust_frame ( stack_pointer_rtx , hard_frame_pointer_rtx , - 1 * sp_adjust ) ; } } else { sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { sp_adjust = sp_adjust - cfun -> machine -> callee_saved_area_gpr_padding_bytes - cfun -> machine -> callee_saved_fpr_regs_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , sp_adjust ) ; nds32_emit_v3pop_fpr_callee_saved ( 0 ) ; } else { nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , sp_adjust ) ; } } if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { int fpr_space = cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; nds32_emit_stack_v3pop ( Rb , Re , fpr_space ) ; } else { nds32_emit_stack_v3pop ( Rb , Re , 0 ) ; } } emit_jump_insn ( gen_pop25return ( ) ) ; } </s>


<s> bool SIInstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { if ( Cond . size ( ) != 2 ) { return true ; } if ( Cond [ 0 ] . isImm ( ) ) { Cond [ 0 ] . setImm ( - Cond [ 0 ] . getImm ( ) ) ; return false ; } return true ; } </s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> static HOST_WIDE_INT ix86_constant_alignment ( const_tree exp , HOST_WIDE_INT align ) { if ( TREE_CODE ( exp ) == REAL_CST || TREE_CODE ( exp ) == VECTOR_CST || TREE_CODE ( exp ) == INTEGER_CST ) { machine_mode mode = TYPE_MODE ( TREE_TYPE ( exp ) ) ; HOST_WIDE_INT mode_align = ix86_static_rtx_alignment ( mode ) ; return MAX ( mode_align , align ) ; } else if ( ! optimize_size && TREE_CODE ( exp ) == STRING_CST && TREE_STRING_LENGTH ( exp ) >= 31 && align < BITS_PER_WORD ) return BITS_PER_WORD ; return align ; } </s>

Compute the alignment given to a constant that is being placed in memory . EXP is the constant and ALIGN is the alignment that the object would ordinarily have . The value of this function is used instead of that alignment to align the object .


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { if ( Inst . getNumOperands ( ) == 0 || Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ 0 ] . OperandType != MCOI :: OPERAND_PCREL ) return false ; int64_t Imm = Inst . getOperand ( 0 ) . getImm ( ) * 4 ; Target = Addr + Imm ; return true ; } </s>

Given a branch instruction try to get the address the branch targets .


<s>
void
AMDGPUInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
llvm_unreachable
(
"Not Implemented"
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool SystemZTargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { if ( ! CI -> isTailCall ( ) ) return false ; return true ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> static void fr30_function_arg_advance ( cumulative_args_t cum , const function_arg_info & arg ) { if ( arg . named ) * get_cumulative_args ( cum ) += fr30_num_arg_regs ( arg ) ; } </s>

A C statement ( sans semicolon ) to update the summarizer variable CUM to advance past an argument in the argument list . The values MODE , TYPE and NAMED describe that argument . Once this is done , the variable CUM is suitable for analyzing the * following * argument with ` FUNCTION_ARG ' , etc . This macro need not do anything if the argument in question was passed on the stack . The compiler knows how to track the amount of stack space used for arguments without any special help .


<s> const uint16_t * mprocRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { } </s>


<s> void ScheduleDAGPostRA :: releasePredecessors ( SUnit * SU ) { for ( SUnit :: pred_iterator I = SU -> Preds . begin ( ) , E = SU -> Preds . end ( ) ; I != E ; ++ I ) { releasePred ( SU , & * I ) ; } } </s>

releasePredecessors - Call releasePred on each of SU 's predecessors .


<s> static void finish_bundle_state_table ( void ) { delete bundle_state_table ; bundle_state_table = NULL ; } </s>


<s>
void
NVPTXAsmPrinter
::
emitImplicitDef
(
const
MachineInstr
*
MI
)
const
{
unsigned
RegNo
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
if
(
TargetRegisterInfo
::
isVirtualRegister
(
RegNo
)
)
{
OutStreamer
->
AddComment
(
Twine
(
"implicit-def: "
)
+
getVirtualRegisterName
(
RegNo
)
)
;
}
else
{
OutStreamer
->
AddComment
(
Twine
(
"implicit-def: "
)
+
nvptxSubtarget
->
getRegisterInfo
(
)
->
getName
(
RegNo
)
)
;
}
OutStreamer
->
AddBlankLine
(
)
;
}
</s>

Targets can override this to customize the output of IMPLICIT_DEF instructions in verbose mode .

NVPTX
NVPTX
0
"implicit-def: "
"implicit-def: "


<s>
unsigned
SIInstrInfo
::
getInstSizeInBytes
(
const
MachineInstr
&
MI
)
const
{
unsigned
Opc
=
MI
.
getOpcode
(
)
;
const
MCInstrDesc
&
Desc
=
getMCOpcodeFromPseudo
(
Opc
)
;
unsigned
DescSize
=
Desc
.
getSize
(
)
;
if
(
DescSize
!=
0
&&
DescSize
!=
4
)
return
DescSize
;
if
(
isVALU
(
MI
)
||
isSALU
(
MI
)
)
{
if
(
isFixedSize
(
MI
)
)
return
DescSize
;
int
Src0Idx
=
AMDGPU
::
getNamedOperandIdx
(
Opc
,
AMDGPU
::
OpName
::
src0
)
;
if
(
Src0Idx
==
1
)
return
4
;
if
(
isLiteralConstantLike
(
MI
.
getOperand
(
Src0Idx
)
,
Desc
.
OpInfo
[
Src0Idx
]
)
)
return
8
;
int
Src1Idx
=
AMDGPU
::
getNamedOperandIdx
(
Opc
,
AMDGPU
::
OpName
::
src1
)
;
if
(
Src1Idx
==
1
)
return
4
;
if
(
isLiteralConstantLike
(
MI
.
getOperand
(
Src1Idx
)
,
Desc
.
OpInfo
[
Src1Idx
]
)
)
return
8
;
return
4
;
}
if
(
DescSize
==
4
)
return
4
;
switch
(
Opc
)
{
case
TargetOpcode
::
IMPLICIT_DEF
:
case
TargetOpcode
::
KILL
:
case
TargetOpcode
::
DBG_VALUE
:
case
TargetOpcode
::
BUNDLE
:
case
TargetOpcode
::
EH_LABEL
:
return
0
;
case
TargetOpcode
::
INLINEASM
:
{
const
MachineFunction
*
MF
=
MI
.
getParent
(
)
->
getParent
(
)
;
const
char
*
AsmStr
=
MI
.
getOperand
(
0
)
.
getSymbolName
(
)
;
return
getInlineAsmLength
(
AsmStr
,
*
MF
->
getTarget
(
)
.
getMCAsmInfo
(
)
)
;
}
default
:
llvm_unreachable
(
"unable to find instruction size"
)
;
}
}
</s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> bool ix86_function_arg_regno_p ( int regno ) { int i ; enum calling_abi call_abi ; const int * parm_regs ; if ( TARGET_SSE && SSE_REGNO_P ( regno ) && regno < FIRST_SSE_REG + SSE_REGPARM_MAX ) return true ; if ( ! TARGET_64BIT ) return ( regno < REGPARM_MAX || ( TARGET_MMX && MMX_REGNO_P ( regno ) && regno < FIRST_MMX_REG + MMX_REGPARM_MAX ) ) ; call_abi = ix86_cfun_abi ( ) ; if ( call_abi == SYSV_ABI && regno == AX_REG ) return true ; if ( call_abi == MS_ABI ) parm_regs = x86_64_ms_abi_int_parameter_registers ; else parm_regs = x86_64_int_parameter_registers ; for ( i = 0 ; i < ( call_abi == MS_ABI ? X86_64_MS_REGPARM_MAX : X86_64_REGPARM_MAX ) ; i ++ ) if ( regno == parm_regs [ i ] ) return true ; return false ; } </s>

Return true when register may be used to pass function parameters .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 Insert Cache Prefetches"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
static
rtx
loongarch_expand_builtin_insn
(
enum
insn_code
icode
,
unsigned
int
nops
,
struct
expand_operand
*
ops
,
bool
has_target_p
)
{
if
(
!
maybe_expand_insn
(
icode
,
nops
,
ops
)
)
{
error
(
"invalid argument to built-in function"
)
;
return
has_target_p
gen_reg_rtx
(
ops
[
0
]
.
mode
)
:
const0_rtx
;
}
return
has_target_p
ops
[
0
]
.
value
:
const0_rtx
;
}
</s>

Expand instruction ICODE as part of a built-in function sequence . Use the first NOPS elements of OPS as the instruction 's operands . HAS_TARGET_P is true if operand 0 is a target ; it is false if the instruction has no target . Return the target rtx if HAS_TARGET_P , otherwise return const0_rtx .


<s> static void loongarch_rewrite_small_data_1 ( rtx * loc ) { subrtx_ptr_iterator :: array_type array ; FOR_EACH_SUBRTX_PTR ( iter , array , loc , ALL ) { rtx * loc = * iter ; if ( MEM_P ( * loc ) ) { loongarch_rewrite_small_data_1 ( & XEXP ( * loc , 0 ) ) ; iter . skip_subrtxes ( ) ; } } } </s>

Rewrite * LOC so that it refers to small data using explicit relocations .


<s> static enum sched_fusion_type fusion_load_store ( rtx_insn * insn , rtx * base , rtx * offset ) { rtx x , dest , src ; enum sched_fusion_type fusion = SCHED_FUSION_LD ; gcc_assert ( INSN_P ( insn ) ) ; x = PATTERN ( insn ) ; if ( GET_CODE ( x ) != SET ) return SCHED_FUSION_NONE ; src = SET_SRC ( x ) ; dest = SET_DEST ( x ) ; if ( GET_MODE ( dest ) != SImode && GET_MODE ( dest ) != DImode && GET_MODE ( dest ) != SFmode && GET_MODE ( dest ) != DFmode ) return SCHED_FUSION_NONE ; if ( GET_CODE ( src ) == SIGN_EXTEND ) { fusion = SCHED_FUSION_LD_SIGN_EXTEND ; src = XEXP ( src , 0 ) ; if ( GET_CODE ( src ) != MEM || GET_MODE ( src ) != SImode ) return SCHED_FUSION_NONE ; } else if ( GET_CODE ( src ) == ZERO_EXTEND ) { fusion = SCHED_FUSION_LD_ZERO_EXTEND ; src = XEXP ( src , 0 ) ; if ( GET_CODE ( src ) != MEM || GET_MODE ( src ) != SImode ) return SCHED_FUSION_NONE ; } if ( GET_CODE ( src ) == MEM && REG_P ( dest ) ) extract_base_offset_in_addr ( src , base , offset ) ; else if ( GET_CODE ( dest ) == MEM && ( REG_P ( src ) || src == const0_rtx ) ) { fusion = SCHED_FUSION_ST ; extract_base_offset_in_addr ( dest , base , offset ) ; } else return SCHED_FUSION_NONE ; if ( * base == NULL_RTX || * offset == NULL_RTX ) fusion = SCHED_FUSION_NONE ; return fusion ; } </s>

If INSN is a load or store of address in the form of [ base+offset ] , extract the two parts and set to BASE and OFFSET . IS_LOAD is set to TRUE if it 's a load . Return TRUE if INSN is such an instruction , otherwise return FALSE .


<s> rtx s390_back_chain_rtx ( void ) { rtx chain ; gcc_assert ( TARGET_BACKCHAIN ) ; if ( TARGET_PACKED_STACK ) chain = plus_constant ( Pmode , stack_pointer_rtx , STACK_POINTER_OFFSET - UNITS_PER_LONG ) ; else chain = stack_pointer_rtx ; chain = gen_rtx_MEM ( Pmode , chain ) ; return chain ; } </s>

Return an RTL expression representing the back chain stored in the current stack frame .


<s> bool AMDGPUAAResult :: pointsToConstantMemory ( const MemoryLocation & Loc , AAQueryInfo & AAQI , bool OrLocal ) { const Value * Base = GetUnderlyingObject ( Loc . Ptr , DL ) ; unsigned AS = Base -> getType ( ) -> getPointerAddressSpace ( ) ; if ( AS == AMDGPUAS :: CONSTANT_ADDRESS || AS == AMDGPUAS :: CONSTANT_ADDRESS_32BIT ) { return true ; } if ( const GlobalVariable * GV = dyn_cast < GlobalVariable > ( Base ) ) { if ( GV -> isConstant ( ) ) return true ; } else if ( const Argument * Arg = dyn_cast < Argument > ( Base ) ) { const Function * F = Arg -> getParent ( ) ; switch ( F -> getCallingConv ( ) ) { default : return AAResultBase :: pointsToConstantMemory ( Loc , AAQI , OrLocal ) ; case CallingConv :: AMDGPU_LS : case CallingConv :: AMDGPU_HS : case CallingConv :: AMDGPU_ES : case CallingConv :: AMDGPU_GS : case CallingConv :: AMDGPU_VS : case CallingConv :: AMDGPU_PS : case CallingConv :: AMDGPU_CS : case CallingConv :: AMDGPU_KERNEL : case CallingConv :: SPIR_KERNEL : break ; } unsigned ArgNo = Arg -> getArgNo ( ) ; if ( F -> hasParamAttribute ( ArgNo , Attribute :: NoAlias ) && ( F -> hasParamAttribute ( ArgNo , Attribute :: ReadNone ) || F -> hasParamAttribute ( ArgNo , Attribute :: ReadOnly ) ) ) { return true ; } } return AAResultBase :: pointsToConstantMemory ( Loc , AAQI , OrLocal ) ; } </s>

A convenience wrapper around the primary pointsToConstantMemory interface .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU


<s> bool SPUPassConfig :: addPreEmitPass ( ) { typedef llvm :: FunctionPass * ( * BuilderFunc ) ( const char * ) ; BuilderFunc schedulerCreator = ( BuilderFunc ) ( intptr_t ) sys :: DynamicLibrary :: SearchForAddressOfSymbol ( "createTCESchedulerPass" ) ; if ( schedulerCreator != NULL ) PM . add ( schedulerCreator ( "cellspu" ) ) ; PM . add ( createSPUNopFillerPass ( getSPUTargetMachine ( ) ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

CellSPU SPU "createTCESchedulerPass" "cellspu" SPU SPU


<s> int rs6000_darwin64_struct_check_p ( machine_mode mode , const_tree type ) { return rs6000_darwin64_abi && ( ( mode == BLKmode && TREE_CODE ( type ) == RECORD_TYPE && int_size_in_bytes ( type ) > 0 ) || ( type && TREE_CODE ( type ) == RECORD_TYPE && int_size_in_bytes ( type ) == 8 ) ) ? 1 : 0 ; } </s>

Check for an item that needs to be considered specially under the darwin 64 bit ABI . These are record types where the mode is BLK or the structure is 8 bytes in size .


"Asked to disassemble an ARM instruction but Subtarget is in Thumb "

Returns the disassembly of a single instruction .


"Should use MaskedValueIsZero if you don't know whether Op"

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> class VISIBILITY_HIDDEN X86MCInstLower { MCContext & Ctx ; Mangler * Mang ; X86AsmPrinter & AsmPrinter ; const X86Subtarget & getSubtarget ( ) const ; public : X86MCInstLower ( MCContext & ctx , Mangler * mang , X86AsmPrinter & asmprinter ) : Ctx ( ctx ) , Mang ( mang ) , AsmPrinter ( asmprinter ) { } void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCSymbol * GetPICBaseSymbol ( ) const ; MCSymbol * GetSymbolFromOperand ( const MachineOperand & MO ) const ; MCOperand LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym ) const ; private : MachineModuleInfoMachO & getMachOMMI ( ) const ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ 0 ] . OperandType != MCOI :: OPERAND_PCREL ) return false ; int64_t Imm = Inst . getOperand ( 0 ) . getImm ( ) ; Target = Addr + Imm + 8 ; return true ; } </s>

Given a branch instruction try to get the address the branch targets .


<s> MVT WebAssemblyTargetLowering :: getPointerMemTy ( const DataLayout & DL , uint32_t AS ) const { if ( AS == WebAssembly :: WasmAddressSpace :: WASM_ADDRESS_SPACE_EXTERNREF ) return MVT :: externref ; if ( AS == WebAssembly :: WasmAddressSpace :: WASM_ADDRESS_SPACE_FUNCREF ) return MVT :: funcref ; return TargetLowering :: getPointerMemTy ( DL , AS ) ; } </s>

Return the in-memory pointer type for the given address space , defaults to the pointer type from the data layout .

WebAssembly WebAssembly WebAssembly::WasmAddressSpace MVT::externref WebAssembly::WasmAddressSpace MVT::funcref


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> bool VZeroUpperInserter :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getTarget ( ) . getInstrInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool EverMadeChange = false ; bool YMMUsed = false ; const TargetRegisterClass * RC = & X86 :: VR256RegClass ; for ( TargetRegisterClass :: iterator i = RC -> begin ( ) , e = RC -> end ( ) ; i != e ; i ++ ) { if ( ! MRI . reg_nodbg_empty ( * i ) ) { YMMUsed = true ; break ; } } if ( ! YMMUsed ) return EverMadeChange ; FnHasLiveInYmm = checkFnHasLiveInYmm ( MRI ) ; assert ( BBState . empty ( ) ) ; BBState . resize ( MF . getNumBlockIDs ( ) , 0 ) ; BBSolved . resize ( MF . getNumBlockIDs ( ) , 0 ) ; while ( 1 ) { bool MadeChange = false ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) MadeChange |= processBasicBlock ( MF , * I ) ; if ( ! MadeChange ) break ; EverMadeChange = true ; } BBState . clear ( ) ; BBSolved . clear ( ) ; return EverMadeChange ; } </s>

runOnMachineFunction - Emit the function body .


<s>
void
override_options
(
)
{
int
i
;
extern
int
atoi
PARAMS
(
(
const
char
*
)
)
;
for
(
i
=
0
;
i
<
(
int
)
SMALL_MEMORY_max
;
i
++
)
{
if
(
small_memory
[
i
]
.
value
)
{
if
(
!
ISDIGIT
(
*
small_memory
[
i
]
.
value
)
)
error
(
"%s=%s is not numeric"
,
small_memory
[
i
]
.
name
,
small_memory
[
i
]
.
value
)
;
else
{
small_memory
[
i
]
.
max
=
atoi
(
small_memory
[
i
]
.
value
)
;
if
(
small_memory
[
i
]
.
max
>
small_memory
[
i
]
.
physical_max
)
error
(
"%s=%s is too large"
,
small_memory
[
i
]
.
name
,
small_memory
[
i
]
.
value
)
;
}
}
}
}
</s>

Set global variables as needed for the options enabled .


<s>
void
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
override
{
unsigned
Opcode
=
MI
.
getOpcode
(
)
;
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
Opcode
)
;
uint64_t
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
unsigned
Size
=
Desc
.
getSize
(
)
;
switch
(
Size
)
{
case
0
:
break
;
case
4
:
if
(
IsLittleEndian
)
{
support
::
endian
::
Writer
<
support
::
little
>
(
OS
)
.
write
<
uint32_t
>
(
Bits
)
;
}
else
{
support
::
endian
::
Writer
<
support
::
big
>
(
OS
)
.
write
<
uint32_t
>
(
Bits
)
;
}
break
;
case
8
:
if
(
IsLittleEndian
)
{
uint64_t
Swapped
=
(
Bits
<<
32
)
|
(
Bits
>>
32
)
;
support
::
endian
::
Writer
<
support
::
little
>
(
OS
)
.
write
<
uint64_t
>
(
Swapped
)
;
}
else
{
support
::
endian
::
Writer
<
support
::
big
>
(
OS
)
.
write
<
uint64_t
>
(
Bits
)
;
}
break
;
default
:
llvm_unreachable
(
"Invalid instruction size"
)
;
}
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .

PowerPC
0
4
support::endian
support::little
support::endian
support::big
8
32
32
support::endian
support::little
support::endian
support::big
"Invalid instruction size"


<s> SDValue MipsTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SDNode * CallNode , const Type * RetTy ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; MipsCC MipsCCInfo ( CallConv , IsO32 , Subtarget -> isFP64bit ( ) , CCInfo ) ; MipsCCInfo . analyzeCallResult ( Ins , Subtarget -> mipsSEUsesSoftFloat ( ) , CallNode , RetTy ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( 1 ) ; InFlag = Val . getValue ( 2 ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( ISD :: BITCAST , DL , RVLocs [ i ] . getValVT ( ) , Val ) ; InVals . push_back ( Val ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> bool HexagonGenExtract :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; bool Changed ; BasicBlock * Entry = GraphTraits < Function * > :: getEntryNode ( & F ) ; Changed = visitBlock ( Entry ) ; return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> unsigned MipsRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { switch ( RC -> getID ( ) ) { default : return 0 ; case Mips :: GPR32RegClassID : case Mips :: GPR64RegClassID : { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return 60 - TFI -> hasFP ( MF ) ; } case Mips :: DSPRRegClassID : { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return 28 - TFI -> hasFP ( MF ) ; } case Mips :: FGR32RegClassID : return 64 ; case Mips :: AFGR64RegClassID : return 32 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> bool aarch64_sve_cmp_immediate_p ( rtx x , bool signed_p ) { rtx elt ; return ( const_vec_duplicate_p ( x , & elt ) && CONST_INT_P ( elt ) && ( signed_p ? IN_RANGE ( INTVAL ( elt ) , - 16 , 15 ) : IN_RANGE ( INTVAL ( elt ) , 0 , 127 ) ) ) ; } </s>

Return true if X is a valid immediate operand for an SVE CMP instruction . SIGNED_P says whether the operand is signed rather than unsigned .


<s> int msp430_hard_regno_mode_ok ( int regno ATTRIBUTE_UNUSED , machine_mode mode ) { return regno <= ( ARG_POINTER_REGNUM - msp430_hard_regno_nregs ( regno , mode ) ) ; } </s>


<s> static unsigned long arm_compute_func_type ( void ) { unsigned long type = ARM_FT_UNKNOWN ; tree a ; tree attr ; gcc_assert ( TREE_CODE ( current_function_decl ) == FUNCTION_DECL ) ; if ( optimize > 0 && ( TREE_NOTHROW ( current_function_decl ) || ! ( flag_unwind_tables || ( flag_exceptions && arm_except_unwind_info ( & global_options ) != UI_SJLJ ) ) ) && TREE_THIS_VOLATILE ( current_function_decl ) ) type |= ARM_FT_VOLATILE ; if ( cfun -> static_chain_decl != NULL ) type |= ARM_FT_NESTED ; attr = DECL_ATTRIBUTES ( current_function_decl ) ; a = lookup_attribute ( "naked" , attr ) ; if ( a != NULL_TREE ) type |= ARM_FT_NAKED ; a = lookup_attribute ( "isr" , attr ) ; if ( a == NULL_TREE ) a = lookup_attribute ( "interrupt" , attr ) ; if ( a == NULL_TREE ) type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL ; else type |= arm_isr_value ( TREE_VALUE ( a ) ) ; if ( lookup_attribute ( "cmse_nonsecure_entry" , attr ) ) type |= ARM_FT_CMSE_ENTRY ; return type ; } </s>

Computes the type of the current function .

arm 0 "naked" "isr" "interrupt" "cmse_nonsecure_entry"


<s> static rtx_insn * visium_md_asm_adjust ( vec < rtx > & , vec < rtx > & , vec < machine_mode > & , vec < const char * > & , vec < rtx > & clobbers , HARD_REG_SET & clobbered_regs ) { clobbers . safe_push ( gen_rtx_REG ( CCmode , FLAGS_REGNUM ) ) ; SET_HARD_REG_BIT ( clobbered_regs , FLAGS_REGNUM ) ; return NULL ; } </s>

Prepend to CLOBBERS hard registers that are automatically clobbered for an asm We do this for the FLAGS to maintain source compatibility with the original cc0-based compiler .


<s> void MipsAsmPrinter :: emitStartOfAsmFile ( Module & M ) { MipsTargetStreamer & TS = getTargetStreamer ( ) ; TS . setPic ( OutContext . getObjectFileInfo ( ) -> isPositionIndependent ( ) ) ; const Triple & TT = TM . getTargetTriple ( ) ; StringRef CPU = MIPS_MC :: selectMipsCPU ( TT , TM . getTargetCPU ( ) ) ; StringRef FS = TM . getTargetFeatureString ( ) ; const MipsTargetMachine & MTM = static_cast < const MipsTargetMachine & > ( TM ) ; const MipsSubtarget STI ( TT , CPU , FS , MTM . isLittleEndian ( ) , MTM , None ) ; bool IsABICalls = STI . isABICalls ( ) ; const MipsABIInfo & ABI = MTM . getABI ( ) ; if ( IsABICalls ) { TS . emitDirectiveAbiCalls ( ) ; if ( ! isPositionIndependent ( ) && STI . hasSym32 ( ) ) TS . emitDirectiveOptionPic0 ( ) ; } std :: string SectionName = std :: string ( ".mdebug." ) + getCurrentABIString ( ) ; OutStreamer -> SwitchSection ( OutContext . getELFSection ( SectionName , ELF :: SHT_PROGBITS , 0 ) ) ; STI . isNaN2008 ( ) ? TS . emitDirectiveNaN2008 ( ) : TS . emitDirectiveNaNLegacy ( ) ; TS . updateABIInfo ( STI ) ; if ( ( ABI . IsO32 ( ) && ( STI . isABI_FPXX ( ) || STI . isFP64bit ( ) ) ) || STI . useSoftFloat ( ) ) TS . emitDirectiveModuleFP ( ) ; if ( ABI . IsO32 ( ) && ( ! STI . useOddSPReg ( ) || STI . isABI_FPXX ( ) ) ) TS . emitDirectiveModuleOddSPReg ( ) ; OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the start of their file .

Mips Mips Mips MIPS_MC::selectMipsCPU Mips Mips Mips Mips ".mdebug." 0


<s> ScheduleHazardRecognizer * ARMBaseInstrInfo :: CreateTargetHazardRecognizer ( const TargetSubtargetInfo * STI , const ScheduleDAG * DAG ) const { if ( usePreRAHazardRecognizer ( ) ) { const InstrItineraryData * II = static_cast < const ARMSubtarget * > ( STI ) -> getInstrItineraryData ( ) ; return new ScoreboardHazardRecognizer ( II , DAG , "pre-RA-sched" ) ; } return TargetInstrInfo :: CreateTargetHazardRecognizer ( STI , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .


<s>
bool
X86AsmParser
::
ParseDirective
(
AsmToken
DirectiveID
)
{
MCAsmParser
&
Parser
=
getParser
(
)
;
StringRef
IDVal
=
DirectiveID
.
getIdentifier
(
)
;
if
(
IDVal
.
startswith
(
".code"
)
)
return
ParseDirectiveCode
(
IDVal
,
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
.
startswith
(
".att_syntax"
)
)
{
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.att_syntax noprefix' is not "
"supported: registers must have a "
"'%' prefix in .att_syntax"
)
;
}
getParser
(
)
.
setAssemblerDialect
(
0
)
;
return
false
;
}
else
if
(
IDVal
.
startswith
(
".intel_syntax"
)
)
{
getParser
(
)
.
setAssemblerDialect
(
1
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.intel_syntax prefix' is not "
"supported: registers must not have "
"a '%' prefix in .intel_syntax"
)
;
}
return
false
;
}
else
if
(
IDVal
==
".even"
)
return
parseDirectiveEven
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_proc"
)
return
parseDirectiveFPOProc
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_setframe"
)
return
parseDirectiveFPOSetFrame
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_pushreg"
)
return
parseDirectiveFPOPushReg
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_stackalloc"
)
return
parseDirectiveFPOStackAlloc
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_stackalign"
)
return
parseDirectiveFPOStackAlign
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_endprologue"
)
return
parseDirectiveFPOEndPrologue
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_endproc"
)
return
parseDirectiveFPOEndProc
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".seh_pushreg"
)
return
parseDirectiveSEHPushReg
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".seh_setframe"
)
return
parseDirectiveSEHSetFrame
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".seh_savereg"
)
return
parseDirectiveSEHSaveReg
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".seh_savexmm"
)
return
parseDirectiveSEHSaveXMM
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".seh_pushframe"
)
return
parseDirectiveSEHPushFrame
(
DirectiveID
.
getLoc
(
)
)
;
return
true
;
}
</s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> static bool rs6000_optab_supported_p ( int op , machine_mode mode1 , machine_mode , optimization_type opt_type ) { switch ( op ) { case rsqrt_optab : return ( opt_type == OPTIMIZE_FOR_SPEED && RS6000_RECIP_AUTO_RSQRTE_P ( mode1 ) ) ; default : return true ; } } </s>

Implement the TARGET_OPTAB_SUPPORTED_P hook .


<s> const char * msp430_mcu_name ( void ) { if ( target_mcu ) { msp430_extract_mcu_data ( target_mcu ) ; unsigned int i ; unsigned int start_upper ; unsigned int end_upper ; static char mcu_name [ 64 ] ; if ( startswith ( target_mcu , "msp430i" ) ) { snprintf ( mcu_name , sizeof ( mcu_name ) - 1 , "__MSP430i%s__" , target_mcu + 7 ) ; start_upper = 9 ; } else { snprintf ( mcu_name , sizeof ( mcu_name ) - 1 , "__%s__" , target_mcu ) ; start_upper = 2 ; } end_upper = strlen ( mcu_name ) - 2 ; for ( i = start_upper ; i < end_upper ; i ++ ) mcu_name [ i ] = TOUPPER ( mcu_name [ i ] ) ; return mcu_name ; } return msp430x ? "__MSP430XGENERIC__" : "__MSP430GENERIC__" ; } </s>

Generate a C preprocessor symbol based upon the MCU selected by the user . If a specific MCU has not been selected then return a generic symbol instead .


"argument of %qE attribute is not a string constant"

"argument of %qE attribute is not \"ilink1\" or \"ilink2\""

Handle an `` interrupt '' attribute ; arguments as in struct attribute_spec.handler .


Returns the tilepro_multiply_insn_seq for multiplier , or NULL if none exists .


<s> StackOffset CSKYFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const CSKYMachineFunctionInfo * CFI = MF . getInfo < CSKYMachineFunctionInfo > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const auto & CSI = MFI . getCalleeSavedInfo ( ) ; int MinCSFI = 0 ; int MaxCSFI = - 1 ; int Offset = MFI . getObjectOffset ( FI ) + MFI . getOffsetAdjustment ( ) ; if ( CSI . size ( ) ) { MinCSFI = CSI [ 0 ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - 1 ] . getFrameIdx ( ) ; } if ( FI >= MinCSFI && FI <= MaxCSFI ) { FrameReg = CSKY :: R14 ; Offset += CFI -> getVarArgsSaveSize ( ) + CFI -> getCalleeSaveAreaSize ( ) ; } else if ( RI -> hasStackRealignment ( MF ) ) { assert ( hasFP ( MF ) ) ; if ( ! MFI . isFixedObjectIndex ( FI ) ) { FrameReg = hasBP ( MF ) ? getBPReg ( STI ) : CSKY :: R14 ; Offset += MFI . getStackSize ( ) ; } else { FrameReg = getFPReg ( STI ) ; Offset += CFI -> getVarArgsSaveSize ( ) + CFI -> getCalleeSaveAreaSize ( ) ; } } else { if ( MFI . isFixedObjectIndex ( FI ) && hasFP ( MF ) ) { FrameReg = getFPReg ( STI ) ; Offset += CFI -> getVarArgsSaveSize ( ) + CFI -> getCalleeSaveAreaSize ( ) ; } else { FrameReg = hasBP ( MF ) ? getBPReg ( STI ) : CSKY :: R14 ; Offset += MFI . getStackSize ( ) ; } } return StackOffset :: getFixed ( Offset ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> static void sparc32_initialize_trampoline ( rtx m_tramp , rtx fnaddr , rtx cxt ) { emit_move_insn ( adjust_address ( m_tramp , SImode , 0 ) , expand_binop ( SImode , ior_optab , expand_shift ( RSHIFT_EXPR , SImode , fnaddr , 10 , 0 , 1 ) , GEN_INT ( trunc_int_for_mode ( 0x03000000 , SImode ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , 4 ) , expand_binop ( SImode , ior_optab , expand_shift ( RSHIFT_EXPR , SImode , cxt , 10 , 0 , 1 ) , GEN_INT ( trunc_int_for_mode ( 0x05000000 , SImode ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , 8 ) , expand_binop ( SImode , ior_optab , expand_and ( SImode , fnaddr , GEN_INT ( 0x3ff ) , NULL_RTX ) , GEN_INT ( trunc_int_for_mode ( 0x81c06000 , SImode ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , 12 ) , expand_binop ( SImode , ior_optab , expand_and ( SImode , cxt , GEN_INT ( 0x3ff ) , NULL_RTX ) , GEN_INT ( trunc_int_for_mode ( 0x8410a000 , SImode ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ) ; emit_insn ( gen_flush ( SImode , validize_mem ( adjust_address ( m_tramp , SImode , 0 ) ) ) ) ; if ( sparc_cpu != PROCESSOR_ULTRASPARC && sparc_cpu != PROCESSOR_ULTRASPARC3 && sparc_cpu != PROCESSOR_NIAGARA && sparc_cpu != PROCESSOR_NIAGARA2 && sparc_cpu != PROCESSOR_NIAGARA3 && sparc_cpu != PROCESSOR_NIAGARA4 && sparc_cpu != PROCESSOR_NIAGARA7 && sparc_cpu != PROCESSOR_M8 ) emit_insn ( gen_flush ( SImode , validize_mem ( adjust_address ( m_tramp , SImode , 8 ) ) ) ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , "__enable_execute_stack" ) , LCT_NORMAL , VOIDmode , XEXP ( m_tramp , 0 ) , Pmode ) ; } </s>

Emit RTL insns to initialize the variable parts of a trampoline . FNADDR is an RTX for the address of the function 's pure code . CXT is an RTX for the static chain value for the function . This takes 16 insns : 2 shifts & 2 ands ( to split up addresses ) , 4 sethi ( to load in opcodes ) , 4 iors ( to merge address and opcodes ) , and 4 writes ( to store insns ) . This is a bit excessive . Perhaps a different mechanism would be better here . Emit enough FLUSH insns to synchronize the data and instruction caches .


"Can only insert epilog into returning blocks"


<s> static MCAsmInfo * createMCAsmInfo ( const MCRegisterInfo & MRI , StringRef TT ) { Triple TheTriple ( TT ) ; switch ( TheTriple . getOS ( ) ) { default : return new MBlazeMCAsmInfo ( ) ; } } </s>

createMCAsmInfo - Create a MCAsmInfo implementation for the specified target triple .


<s> static void nios2_setup_incoming_varargs ( cumulative_args_t cum_v , const function_arg_info & arg , int * pretend_size , int second_time ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; CUMULATIVE_ARGS local_cum ; cumulative_args_t local_cum_v = pack_cumulative_args ( & local_cum ) ; int regs_to_push ; int pret_size ; cfun -> machine -> uses_anonymous_args = 1 ; local_cum = * cum ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) ) nios2_function_arg_advance ( local_cum_v , arg ) ; regs_to_push = NUM_ARG_REGS - local_cum . regs_used ; if ( ! TARGET_HAS_CDX && ! second_time && regs_to_push > 0 ) { rtx ptr = virtual_incoming_args_rtx ; rtx mem = gen_rtx_MEM ( BLKmode , ptr ) ; emit_insn ( gen_blockage ( ) ) ; move_block_from_reg ( local_cum . regs_used + FIRST_ARG_REGNO , mem , regs_to_push ) ; emit_insn ( gen_blockage ( ) ) ; } pret_size = regs_to_push * UNITS_PER_WORD ; if ( pret_size ) * pretend_size = pret_size ; } </s>

TODO : It may be possible to eliminate the copyback and implement own va_arg type .


<s> void PPCPassConfig :: addIRPasses ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCBoolRetToIntPass ( ) ) ; addPass ( createAtomicExpandPass ( ) ) ; addPass ( createPPCLowerMASSVEntriesPass ( ) ) ; if ( EnablePrefetch . getNumOccurrences ( ) > 0 ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Default && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


"\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n"

Set up the stack and frame pointer ( if desired ) for the function . Note , if this is changed , you need to mirror the changes in m32r_compute_frame_size which calculates the prolog size .


<s> bool X86TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , getTargetMachine ( ) , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_X86 ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> int s390_single_part ( rtx op , machine_mode mode , machine_mode part_mode , int def ) { unsigned HOST_WIDE_INT value = 0 ; int n_parts = GET_MODE_SIZE ( mode ) / GET_MODE_SIZE ( part_mode ) ; unsigned HOST_WIDE_INT part_mask = ( HOST_WIDE_INT_1U << GET_MODE_BITSIZE ( part_mode ) ) - 1 ; int i , part = - 1 ; if ( GET_CODE ( op ) != CONST_INT ) return - 1 ; for ( i = 0 ; i < n_parts ; i ++ ) { if ( i == 0 ) value = UINTVAL ( op ) ; else value >>= GET_MODE_BITSIZE ( part_mode ) ; if ( ( value & part_mask ) != ( def & part_mask ) ) { if ( part != - 1 ) return - 1 ; else part = i ; } } return part == - 1 ? - 1 : n_parts - 1 - part ; } </s>

If OP is an integer constant of mode MODE with exactly one part of mode PART_MODE unequal to DEF , return the number of that part . Otherwise , return -1 .


<s>
const
char
*
pa_singlemove_string
(
rtx
*
operands
)
{
HOST_WIDE_INT
intval
;
if
(
GET_CODE
(
operands
[
0
]
)
==
MEM
)
return
"stw %r1,%0"
;
if
(
GET_CODE
(
operands
[
1
]
)
==
MEM
)
return
"ldw %1,%0"
;
if
(
GET_CODE
(
operands
[
1
]
)
==
CONST_DOUBLE
)
{
long
i
;
REAL_VALUE_TYPE
d
;
gcc_assert
(
GET_MODE
(
operands
[
1
]
)
==
SFmode
)
;
REAL_VALUE_FROM_CONST_DOUBLE
(
d
,
operands
[
1
]
)
;
REAL_VALUE_TO_TARGET_SINGLE
(
d
,
i
)
;
operands
[
1
]
=
GEN_INT
(
i
)
;
}
if
(
GET_CODE
(
operands
[
1
]
)
==
CONST_INT
)
{
intval
=
INTVAL
(
operands
[
1
]
)
;
if
(
VAL_14_BITS_P
(
intval
)
)
return
"ldi %1,%0"
;
else
if
(
(
intval
&
0x7ff
)
==
0
)
return
"ldil L'%1,%0"
;
else
if
(
pa_zdepi_cint_p
(
intval
)
)
return
"{zdepi %Z1,%0|depwi,z %Z1,%0}"
;
else
return
"ldil L'%1,%0\n\tldo R'%1(%0),%0"
;
}
return
"copy %1,%0"
;
}
</s>

Return the best assembler insn template for moving operands [ 1 ] into operands [ 0 ] as a fullword .


<s> bool HexagonTargetLowering :: allowTruncateForTailCall ( Type * Ty1 , Type * Ty2 ) const { if ( ! Ty1 -> isIntegerTy ( ) || ! Ty2 -> isIntegerTy ( ) ) return false ; return Ty1 -> getPrimitiveSizeInBits ( ) <= 32 ; } </s>

Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail position .


<s>
const
ArrayRef
<
MCPhysReg
>
Cpu0ABIInfo
::
GetVarArgRegs
(
)
const
{
if
(
IsO32
(
)
)
return
makeArrayRef
(
O32IntRegs
)
;
if
(
IsS32
(
)
)
return
makeArrayRef
(
S32IntRegs
)
;
llvm_unreachable
(
"Unhandled ABI"
)
;
}
</s>

The registers to use for the variable argument list .


<s> bool ARMBaseRegisterInfo :: hasFP ( const MachineFunction & MF ) const { if ( STI . isTargetDarwin ( ) ) return true ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( ( DisableFramePointerElim ( MF ) && MFI -> hasCalls ( ) ) || needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Unsupported Node Replacement"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> const char * PPCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return nullptr ; case PPCISD :: FSEL : return "PPCISD::FSEL" ; case PPCISD :: FCFID : return "PPCISD::FCFID" ; case PPCISD :: FCTIDZ : return "PPCISD::FCTIDZ" ; case PPCISD :: FCTIWZ : return "PPCISD::FCTIWZ" ; case PPCISD :: FRE : return "PPCISD::FRE" ; case PPCISD :: FRSQRTE : return "PPCISD::FRSQRTE" ; case PPCISD :: STFIWX : return "PPCISD::STFIWX" ; case PPCISD :: VMADDFP : return "PPCISD::VMADDFP" ; case PPCISD :: VNMSUBFP : return "PPCISD::VNMSUBFP" ; case PPCISD :: VPERM : return "PPCISD::VPERM" ; case PPCISD :: Hi : return "PPCISD::Hi" ; case PPCISD :: Lo : return "PPCISD::Lo" ; case PPCISD :: TOC_ENTRY : return "PPCISD::TOC_ENTRY" ; case PPCISD :: LOAD : return "PPCISD::LOAD" ; case PPCISD :: LOAD_TOC : return "PPCISD::LOAD_TOC" ; case PPCISD :: DYNALLOC : return "PPCISD::DYNALLOC" ; case PPCISD :: GlobalBaseReg : return "PPCISD::GlobalBaseReg" ; case PPCISD :: SRL : return "PPCISD::SRL" ; case PPCISD :: SRA : return "PPCISD::SRA" ; case PPCISD :: SHL : return "PPCISD::SHL" ; case PPCISD :: CALL : return "PPCISD::CALL" ; case PPCISD :: CALL_NOP : return "PPCISD::CALL_NOP" ; case PPCISD :: CALL_TLS : return "PPCISD::CALL_TLS" ; case PPCISD :: CALL_NOP_TLS : return "PPCISD::CALL_NOP_TLS" ; case PPCISD :: MTCTR : return "PPCISD::MTCTR" ; case PPCISD :: BCTRL : return "PPCISD::BCTRL" ; case PPCISD :: RET_FLAG : return "PPCISD::RET_FLAG" ; case PPCISD :: EH_SJLJ_SETJMP : return "PPCISD::EH_SJLJ_SETJMP" ; case PPCISD :: EH_SJLJ_LONGJMP : return "PPCISD::EH_SJLJ_LONGJMP" ; case PPCISD :: MFOCRF : return "PPCISD::MFOCRF" ; case PPCISD :: VCMP : return "PPCISD::VCMP" ; case PPCISD :: VCMPo : return "PPCISD::VCMPo" ; case PPCISD :: LBRX : return "PPCISD::LBRX" ; case PPCISD :: STBRX : return "PPCISD::STBRX" ; case PPCISD :: LARX : return "PPCISD::LARX" ; case PPCISD :: STCX : return "PPCISD::STCX" ; case PPCISD :: COND_BRANCH : return "PPCISD::COND_BRANCH" ; case PPCISD :: BDNZ : return "PPCISD::BDNZ" ; case PPCISD :: BDZ : return "PPCISD::BDZ" ; case PPCISD :: MFFS : return "PPCISD::MFFS" ; case PPCISD :: FADDRTZ : return "PPCISD::FADDRTZ" ; case PPCISD :: TC_RETURN : return "PPCISD::TC_RETURN" ; case PPCISD :: CR6SET : return "PPCISD::CR6SET" ; case PPCISD :: CR6UNSET : return "PPCISD::CR6UNSET" ; case PPCISD :: ADDIS_TOC_HA : return "PPCISD::ADDIS_TOC_HA" ; case PPCISD :: LD_TOC_L : return "PPCISD::LD_TOC_L" ; case PPCISD :: ADDI_TOC_L : return "PPCISD::ADDI_TOC_L" ; case PPCISD :: PPC32_GOT : return "PPCISD::PPC32_GOT" ; case PPCISD :: ADDIS_GOT_TPREL_HA : return "PPCISD::ADDIS_GOT_TPREL_HA" ; case PPCISD :: LD_GOT_TPREL_L : return "PPCISD::LD_GOT_TPREL_L" ; case PPCISD :: ADD_TLS : return "PPCISD::ADD_TLS" ; case PPCISD :: ADDIS_TLSGD_HA : return "PPCISD::ADDIS_TLSGD_HA" ; case PPCISD :: ADDI_TLSGD_L : return "PPCISD::ADDI_TLSGD_L" ; case PPCISD :: ADDIS_TLSLD_HA : return "PPCISD::ADDIS_TLSLD_HA" ; case PPCISD :: ADDI_TLSLD_L : return "PPCISD::ADDI_TLSLD_L" ; case PPCISD :: ADDIS_DTPREL_HA : return "PPCISD::ADDIS_DTPREL_HA" ; case PPCISD :: ADDI_DTPREL_L : return "PPCISD::ADDI_DTPREL_L" ; case PPCISD :: VADD_SPLAT : return "PPCISD::VADD_SPLAT" ; case PPCISD :: SC : return "PPCISD::SC" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> HOST_WIDE_INT csky_initial_elimination_offset ( int from , int to ) { int offset ; csky_layout_stack_frame ( ) ; switch ( from ) { case FRAME_POINTER_REGNUM : case HARD_FRAME_POINTER_REGNUM : offset = cfun -> machine -> reg_offset ; break ; case ARG_POINTER_REGNUM : offset = cfun -> machine -> arg_offset ; break ; default : gcc_unreachable ( ) ; } if ( to == FRAME_POINTER_REGNUM || to == HARD_FRAME_POINTER_REGNUM ) offset -= cfun -> machine -> reg_offset ; return offset ; } </s>

Worker function for INITIAL_ELIMINATION_OFFSET macro . Define the offset between two registers , one to be eliminated , and the other its replacement , at the start of a routine .