<s> const char * AMDGPUTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return nullptr ; NODE_NAME_CASE ( CALL ) ; NODE_NAME_CASE ( UMUL ) ; NODE_NAME_CASE ( DIV_INF ) ; NODE_NAME_CASE ( RET_FLAG ) ; NODE_NAME_CASE ( BRANCH_COND ) ; NODE_NAME_CASE ( DWORDADDR ) NODE_NAME_CASE ( FRACT ) NODE_NAME_CASE ( FMAX ) NODE_NAME_CASE ( SMAX ) NODE_NAME_CASE ( UMAX ) NODE_NAME_CASE ( FMIN ) NODE_NAME_CASE ( SMIN ) NODE_NAME_CASE ( UMIN ) NODE_NAME_CASE ( BFE_U32 ) NODE_NAME_CASE ( BFE_I32 ) NODE_NAME_CASE ( BFI ) NODE_NAME_CASE ( BFM ) NODE_NAME_CASE ( MUL_U24 ) NODE_NAME_CASE ( MUL_I24 ) NODE_NAME_CASE ( URECIP ) NODE_NAME_CASE ( DOT4 ) NODE_NAME_CASE ( EXPORT ) NODE_NAME_CASE ( CONST_ADDRESS ) NODE_NAME_CASE ( REGISTER_LOAD ) NODE_NAME_CASE ( REGISTER_STORE ) NODE_NAME_CASE ( LOAD_CONSTANT ) NODE_NAME_CASE ( LOAD_INPUT ) NODE_NAME_CASE ( SAMPLE ) NODE_NAME_CASE ( SAMPLEB ) NODE_NAME_CASE ( SAMPLED ) NODE_NAME_CASE ( SAMPLEL ) NODE_NAME_CASE ( STORE_MSKOR ) NODE_NAME_CASE ( TBUFFER_STORE_FORMAT ) } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> bool PPCInstrInfo :: analyzeCompare ( const MachineInstr * MI , unsigned & SrcReg , unsigned & SrcReg2 , int & Mask , int & Value ) const { unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { default : return false ; case PPC :: CMPWI : case PPC :: CMPLWI : case PPC :: CMPDI : case PPC :: CMPLDI : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; Value = MI -> getOperand ( 2 ) . getImm ( ) ; Mask = 0xFFFF ; return true ; case PPC :: CMPW : case PPC :: CMPLW : case PPC :: CMPD : case PPC :: CMPLD : case PPC :: FCMPUS : case PPC :: FCMPUD : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; SrcReg2 = MI -> getOperand ( 2 ) . getReg ( ) ; return true ; } } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .

PowerPC PPC PPC::CMPWI PPC::CMPLWI PPC::CMPDI PPC::CMPLDI 1 0 2 0xFFFF PPC::CMPW PPC::CMPLW PPC::CMPD PPC::CMPLD PPC::FCMPUS PPC::FCMPUD 1 2


<s>
void
SystemZRegisterInfo
::
emitPrologue
(
MachineFunction
&
MF
)
const
{
MachineBasicBlock
&
MBB
=
MF
.
front
(
)
;
const
TargetFrameInfo
&
TFI
=
*
MF
.
getTarget
(
)
.
getFrameInfo
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
SystemZMachineFunctionInfo
*
SystemZMFI
=
MF
.
getInfo
<
SystemZMachineFunctionInfo
>
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
DL
=
(
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
::
getUnknownLoc
(
)
)
;
uint64_t
StackSize
=
MFI
->
getStackSize
(
)
;
StackSize
-=
SystemZMFI
->
getCalleeSavedFrameSize
(
)
;
uint64_t
NumBytes
=
StackSize
TFI
.
getOffsetOfLocalArea
(
)
;
while
(
MBBI
!=
MBB
.
end
(
)
&&
(
MBBI
->
getOpcode
(
)
==
SystemZ
::
MOV64mr
||
MBBI
->
getOpcode
(
)
==
SystemZ
::
MOV64mrm
)
)
++
MBBI
;
if
(
MBBI
!=
MBB
.
end
(
)
)
DL
=
MBBI
->
getDebugLoc
(
)
;
if
(
StackSize
||
MFI
->
hasCalls
(
)
)
{
assert
(
MF
.
getRegInfo
(
)
.
isPhysRegUsed
(
SystemZ
::
R15D
)
&&
"Invalid stack frame calculation!"
)
;
emitSPUpdate
(
MBB
,
MBBI
,
(
int64_t
)
NumBytes
,
TII
)
;
}
if
(
hasFP
(
MF
)
)
{
BuildMI
(
MBB
,
MBBI
,
DL
,
TII
.
get
(
SystemZ
::
MOV64rr
)
,
SystemZ
::
R11D
)
.
addReg
(
SystemZ
::
R15D
)
;
for
(
MachineFunction
::
iterator
I
=
llvm
::
next
(
MF
.
begin
(
)
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
I
->
addLiveIn
(
SystemZ
::
R11D
)
;
}
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool SIPreEmitPeephole :: runOnMachineFunction ( MachineFunction & MF ) { const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; MachineBasicBlock * EmptyMBBAtEnd = nullptr ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { MachineBasicBlock :: iterator MBBE = MBB . getFirstTerminator ( ) ; MachineBasicBlock :: iterator TermI = MBBE ; if ( TermI != MBB . end ( ) ) { MachineInstr & MI = * TermI ; switch ( MI . getOpcode ( ) ) { case AMDGPU :: S_CBRANCH_VCCZ : case AMDGPU :: S_CBRANCH_VCCNZ : Changed |= optimizeVccBranch ( MI ) ; continue ; default : break ; } } while ( TermI != MBB . end ( ) ) { MachineInstr & MI = * TermI ; if ( MI . getOpcode ( ) == AMDGPU :: SI_RETURN_TO_EPILOG ) { assert ( ! MF . getInfo < SIMachineFunctionInfo > ( ) -> returnsVoid ( ) ) ; if ( & MBB != & MF . back ( ) || & MI != & MBB . back ( ) ) { if ( ! EmptyMBBAtEnd ) { EmptyMBBAtEnd = MF . CreateMachineBasicBlock ( ) ; MF . insert ( MF . end ( ) , EmptyMBBAtEnd ) ; } MBB . addSuccessor ( EmptyMBBAtEnd ) ; BuildMI ( MBB , & MI , MI . getDebugLoc ( ) , TII -> get ( AMDGPU :: S_BRANCH ) ) . addMBB ( EmptyMBBAtEnd ) ; MI . eraseFromParent ( ) ; MBBE = MBB . getFirstTerminator ( ) ; TermI = MBBE ; continue ; } } TermI ++ ; } if ( ! ST . hasVGPRIndexMode ( ) ) continue ; MachineInstr * SetGPRMI = nullptr ; const unsigned Threshold = 20 ; unsigned Count = 0 ; for ( MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; MBBI != MBBE ; ) { MachineInstr & MI = * MBBI ; ++ MBBI ; if ( Count == Threshold ) SetGPRMI = nullptr ; else ++ Count ; if ( MI . getOpcode ( ) != AMDGPU :: S_SET_GPR_IDX_ON ) continue ; Count = 0 ; if ( ! SetGPRMI ) { SetGPRMI = & MI ; continue ; } if ( optimizeSetGPR ( * SetGPRMI , MI ) ) Changed = true ; else SetGPRMI = & MI ; } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool llvm :: isEqual ( const GCNRPTracker :: LiveRegSet & S1 , const GCNRPTracker :: LiveRegSet & S2 ) { if ( S1 . size ( ) != S2 . size ( ) ) return false ; for ( const auto & P : S1 ) { auto I = S2 . find ( P . first ) ; if ( I == S2 . end ( ) || I -> second != P . second ) return false ; } return true ; } </s>

isEqual - Compares two trees for structural equality and returns true if they are equal .


<s> bool WebAssemblyFastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Call : if ( selectCall ( I ) ) return true ; break ; case Instruction :: Select : return selectSelect ( I ) ; case Instruction :: Trunc : return selectTrunc ( I ) ; case Instruction :: ZExt : return selectZExt ( I ) ; case Instruction :: SExt : return selectSExt ( I ) ; case Instruction :: ICmp : return selectICmp ( I ) ; case Instruction :: FCmp : return selectFCmp ( I ) ; case Instruction :: BitCast : return selectBitCast ( I ) ; case Instruction :: Load : return selectLoad ( I ) ; case Instruction :: Store : return selectStore ( I ) ; case Instruction :: Br : return selectBr ( I ) ; case Instruction :: Ret : return selectRet ( I ) ; case Instruction :: Unreachable : return selectUnreachable ( I ) ; default : break ; } return selectOperator ( I , I -> getOpcode ( ) ) ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , JIT , RM ) , getEffectiveCodeModel ( CM , JIT , TT . getArch ( ) == Triple :: x86_64 ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) { if ( ( TT . isOSWindows ( ) && TT . getArch ( ) == Triple :: x86_64 ) || TT . isPS4 ( ) || TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = TT . isOSBinFormatMachO ( ) ; } if ( TT . getArch ( ) == Triple :: x86_64 ) setMachineOutliner ( true ) ; initAsmInfo ( ) ; } </s>


<s> void visitCallInst ( CallInst & I ) { if ( ! I . getCalledFunction ( ) ) return ; StringRef Name = I . getCalledFunction ( ) -> getName ( ) ; if ( Name == "llvm.AMDGPU.tex" ) { ReplaceTexIntrinsic ( I , false , TexSign , "llvm.r600.tex" , "llvm.r600.texc" ) ; return ; } if ( Name == "llvm.AMDGPU.txl" ) { ReplaceTexIntrinsic ( I , true , TexSign , "llvm.r600.txl" , "llvm.r600.txlc" ) ; return ; } if ( Name == "llvm.AMDGPU.txb" ) { ReplaceTexIntrinsic ( I , true , TexSign , "llvm.r600.txb" , "llvm.r600.txbc" ) ; return ; } if ( Name == "llvm.AMDGPU.txf" ) { ReplaceTXF ( I ) ; return ; } if ( Name == "llvm.AMDGPU.txq" ) { ReplaceTexIntrinsic ( I , false , TexQSign , "llvm.r600.txq" , "llvm.r600.txq" ) ; return ; } if ( Name == "llvm.AMDGPU.ddx" ) { ReplaceTexIntrinsic ( I , false , TexSign , "llvm.r600.ddx" , "llvm.r600.ddx" ) ; return ; } if ( Name == "llvm.AMDGPU.ddy" ) { ReplaceTexIntrinsic ( I , false , TexSign , "llvm.r600.ddy" , "llvm.r600.ddy" ) ; return ; } } </s>


<s>
void
Thumb1InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
&
ARM
::
tGPRRegClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
&
ARM
::
tGPRRegClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
,
MachineMemOperand
::
MOStore
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tSTRspi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .

ARM
ARM::tGPRRegClass
ARM
"Unknown regclass!"
ARM::tGPRRegClass
ARM
ARM::tSTRspi
0


<s> void ARMTargetLowering :: HandleByVal ( CCState * State , unsigned & Size , unsigned Align ) const { Align = std :: max ( Align , 4U ) ; unsigned Reg = State -> AllocateReg ( GPRArgRegs ) ; if ( ! Reg ) return ; unsigned AlignInRegs = Align / 4 ; unsigned Waste = ( ARM :: R4 - Reg ) % AlignInRegs ; for ( unsigned i = 0 ; i < Waste ; ++ i ) Reg = State -> AllocateReg ( GPRArgRegs ) ; if ( ! Reg ) return ; unsigned Excess = 4 * ( ARM :: R4 - Reg ) ; const unsigned NSAAOffset = State -> getNextStackOffset ( ) ; if ( NSAAOffset != 0 && Size > Excess ) { while ( State -> AllocateReg ( GPRArgRegs ) ) ; return ; } unsigned ByValRegBegin = Reg ; unsigned ByValRegEnd = std :: min < unsigned > ( Reg + Size / 4 , ARM :: R4 ) ; State -> addInRegsParamInfo ( ByValRegBegin , ByValRegEnd ) ; for ( unsigned i = Reg + 1 ; i != ByValRegEnd ; ++ i ) State -> AllocateReg ( GPRArgRegs ) ; Size = std :: max < int > ( Size - Excess , 0 ) ; } </s>

Target-specific cleanup for formal ByVal parameters .


<s> const std :: string getName ( ) const override { return "AAAMDWorkGroupSize" ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> static bool aarch64_evpc_ext ( struct expand_vec_perm_d * d ) { HOST_WIDE_INT location ; rtx offset ; if ( d -> vec_flags == VEC_SVE_PRED || ! d -> perm [ 0 ] . is_constant ( & location ) || ! d -> perm . series_p ( 0 , 1 , location , 1 ) ) return false ; if ( d -> testing_p ) return true ; if ( BYTES_BIG_ENDIAN && location != 0 && d -> vec_flags == VEC_ADVSIMD ) { std :: swap ( d -> op0 , d -> op1 ) ; location = d -> perm . length ( ) . to_constant ( ) - location ; } offset = GEN_INT ( location ) ; emit_set_insn ( d -> target , gen_rtx_UNSPEC ( d -> vmode , gen_rtvec ( 3 , d -> op0 , d -> op1 , offset ) , UNSPEC_EXT ) ) ; return true ; } </s>


<s>
bool
SystemZInstrInfo
::
PredicateInstruction
(
MachineInstr
&
MI
,
ArrayRef
<
MachineOperand
>
Pred
)
const
{
assert
(
Pred
.
size
(
)
==
2
&&
"Invalid condition"
)
;
unsigned
CCValid
=
Pred
[
0
]
.
getImm
(
)
;
unsigned
CCMask
=
Pred
[
1
]
.
getImm
(
)
;
assert
(
CCMask
>
0
&&
CCMask
<
15
&&
"Invalid predicate"
)
;
unsigned
Opcode
=
MI
.
getOpcode
(
)
;
if
(
STI
.
hasLoadStoreOnCond
(
)
)
{
if
(
unsigned
CondOpcode
=
getConditionalMove
(
Opcode
)
)
{
MI
.
setDesc
(
get
(
CondOpcode
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
}
return
false
;
}
</s>

Convert the instruction into a predicated instruction .


"64-bit code requested on a subtarget that doesn't support it!"

"Segmented stacks are only implemented on ELF."

This constructor initializes the data members to match that of the specified triple .


"Unexpected Kind in getPointerRegClass!"

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> SDValue AArch64SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; ConstantSDNode * SizeValue = dyn_cast < ConstantSDNode > ( Size ) ; const AArch64Subtarget & STI = DAG . getMachineFunction ( ) . getSubtarget < AArch64Subtarget > ( ) ; const char * bzeroName = ( V && V -> isNullValue ( ) ) ? DAG . getTargetLoweringInfo ( ) . getLibcallName ( RTLIB :: BZERO ) : nullptr ; if ( bzeroName && ( ! SizeValue || SizeValue -> getZExtValue ( ) > 256 ) ) { const AArch64TargetLowering & TLI = * STI . getTargetLowering ( ) ; EVT IntPtr = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; Type * IntPtrTy = Type :: getInt8PtrTy ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroName , IntPtr ) , std :: move ( Args ) ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memset .


<s> EVT SparcTargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s>
bool
SystemZAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Operands
.
push_back
(
SystemZOperand
::
createToken
(
Name
,
NameLoc
)
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
parseOperand
(
Operands
,
Name
)
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
true
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
true
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

SystemZ
SystemZ
SystemZ
"unexpected token in argument list"


<s>
void
relaxInstruction
(
const
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
,
MCInst
&
Res
)
const
override
{
llvm_unreachable
(
"Not implemented"
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> WebAssemblyTargetMachine :: WebAssemblyTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT . isArch64Bit ( ) ? "e-m:e-p:64:64-i64:64-n32:64-S128" : "e-m:e-p:32:32-i64:64-n32:64-S128" , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , CM , OL ) , TLOF ( make_unique < WebAssemblyTargetObjectFile > ( ) ) { this -> Options . TrapUnreachable = true ; initAsmInfo ( ) ; } </s>

Create an WebAssembly architecture model .

WebAssembly WebAssembly WebAssembly "e-m:e-p:64:64-i64:64-n32:64-S128" "e-m:e-p:32:32-i64:64-n32:64-S128" WebAssembly


<s> static int mips16_insn_length ( rtx_insn * insn ) { if ( JUMP_TABLE_DATA_P ( insn ) ) { rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) == ADDR_VEC ) return GET_MODE_SIZE ( GET_MODE ( body ) ) * XVECLEN ( body , 0 ) ; else if ( GET_CODE ( body ) == ADDR_DIFF_VEC ) return GET_MODE_SIZE ( GET_MODE ( body ) ) * XVECLEN ( body , 1 ) ; else gcc_unreachable ( ) ; } return get_attr_length ( insn ) ; } </s>


<s>
void
print
(
raw_ostream
&
OS
)
const
{
OS
<<
"{"
;
if
(
!
isValid
(
)
)
OS
<<
"Uninitialized"
;
if
(
isUnknown
(
)
)
OS
<<
"unknown"
;
;
if
(
hasAVLReg
(
)
)
OS
<<
"AVLReg="
<<
(
unsigned
)
AVLReg
;
if
(
hasAVLImm
(
)
)
OS
<<
"AVLImm="
<<
(
unsigned
)
AVLImm
;
OS
<<
", "
<<
"VLMul="
<<
(
unsigned
)
VLMul
<<
", "
<<
"SEW="
<<
(
unsigned
)
SEW
<<
", "
<<
"TailAgnostic="
<<
(
bool
)
TailAgnostic
<<
", "
<<
"MaskAgnostic="
<<
(
bool
)
MaskAgnostic
<<
", "
<<
"MaskRegOp="
<<
(
bool
)
MaskRegOp
<<
", "
<<
"StoreOp="
<<
(
bool
)
StoreOp
<<
", "
<<
"ScalarMovOp="
<<
(
bool
)
ScalarMovOp
<<
", "
<<
"SEWLMULRatioOnly="
<<
(
bool
)
SEWLMULRatioOnly
<<
"}"
;
}
</s>

print - Print a debug representation of the operand to the given stream .

RISCV
"{"
"Uninitialized"
"unknown"
"AVLReg="
"AVLImm="
", "
"VLMul="
", "
"SEW="
", "
"TailAgnostic="
", "
"MaskAgnostic="
", "
"MaskRegOp="
", "
"StoreOp="
", "
"ScalarMovOp="
", "
"SEWLMULRatioOnly="
"}"


<s> std :: pair < unsigned , const TargetRegisterClass * > TLCS900TargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'r' : if ( VT == MVT :: i8 ) return std :: make_pair ( 0U , TLCS900 :: GR8RegisterClass ) ; return std :: make_pair ( 0U , TLCS900 :: GR16RegisterClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> static machine_mode s390_cc_modes_compatible ( machine_mode m1 , machine_mode m2 ) { if ( m1 == m2 ) return m1 ; switch ( m1 ) { case E_CCZmode : if ( m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode ) return m2 ; return VOIDmode ; case E_CCSmode : case E_CCUmode : case E_CCTmode : case E_CCSRmode : case E_CCURmode : case E_CCZ1mode : if ( m2 == CCZmode ) return m1 ; return VOIDmode ; default : return VOIDmode ; } return VOIDmode ; } </s>

If two condition code modes are compatible , return a condition code mode which is compatible with both . Otherwise , return VOIDmode .


<s> bool XCorePassConfig :: addInstSelector ( ) { PM . add ( createXCoreISelDag ( getXCoreTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & FS , bool isThumb ) : ARMArchVersion ( V4T ) , ARMFPUType ( None ) , UseNEONForSinglePrecisionFP ( false ) , IsThumb ( isThumb ) , ThumbMode ( Thumb1 ) , IsR9Reserved ( ReserveR9 ) , stackAlignment ( 4 ) , CPUString ( "generic" ) , TargetType ( isELF ) , TargetABI ( ARM_ABI_APCS ) { if ( FloatABIType == FloatABI :: Default ) FloatABIType = FloatABI :: Soft ; CPUString = ParseSubtargetFeatures ( FS , CPUString ) ; unsigned Len = TT . length ( ) ; unsigned Idx = 0 ; if ( Len >= 5 && TT . substr ( 0 , 4 ) == "armv" ) Idx = 4 ; else if ( Len >= 6 && TT . substr ( 0 , 5 ) == "thumb" ) { IsThumb = true ; if ( Len >= 7 && TT [ 5 ] == 'v' ) Idx = 6 ; } if ( Idx ) { unsigned SubVer = TT [ Idx ] ; if ( SubVer > '4' && SubVer <= '9' ) { if ( SubVer >= '7' ) { ARMArchVersion = V7A ; } else if ( SubVer == '6' ) { ARMArchVersion = V6 ; if ( Len >= Idx + 3 && TT [ Idx + 1 ] == 't' && TT [ Idx + 2 ] == '2' ) ARMArchVersion = V6T2 ; } else if ( SubVer == '5' ) { ARMArchVersion = V5T ; if ( Len >= Idx + 3 && TT [ Idx + 1 ] == 't' && TT [ Idx + 2 ] == 'e' ) ARMArchVersion = V5TE ; } if ( ARMArchVersion >= V6T2 ) ThumbMode = Thumb2 ; } } if ( ARMArchVersion < V6T2 && ThumbMode >= Thumb2 ) ARMArchVersion = V6T2 ; if ( Len >= 10 ) { if ( TT . find ( "-darwin" ) != std :: string :: npos ) TargetType = isDarwin ; } if ( TT . find ( "eabi" ) != std :: string :: npos ) TargetABI = ARM_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = 8 ; if ( isTargetDarwin ( ) ) IsR9Reserved = ReserveR9 | ( ARMArchVersion < V6 ) ; } </s>


<s> bool XCoreFrameInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return true ; MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF -> getTarget ( ) . getInstrInfo ( ) ; XCoreFunctionInfo * XFI = MF -> getInfo < XCoreFunctionInfo > ( ) ; bool emitFrameMoves = XCoreRegisterInfo :: needsFrameMoves ( * MF ) ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator it = CSI . begin ( ) ; it != CSI . end ( ) ; ++ it ) { MBB . addLiveIn ( it -> getReg ( ) ) ; unsigned Reg = it -> getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , it -> getFrameIdx ( ) , RC , TRI ) ; if ( emitFrameMoves ) { MCSymbol * SaveLabel = MF -> getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MI , DL , TII . get ( XCore :: PROLOG_LABEL ) ) . addSym ( SaveLabel ) ; XFI -> getSpillLabels ( ) . push_back ( std :: make_pair ( SaveLabel , * it ) ) ; } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .

XCore XCore XCore XCore XCore XCore::PROLOG_LABEL


"(cinsn 1 (set (mem/v:BLK (0|scratch:DI) [0  A8])\n"

"                (mem/v:BLK (reuse_rtx 0) [0  A8])\n"

"            ] UNSPEC_MEMORY_BLOCKAGE)))\n"

Test dumping an insn with repeated references to the same SCRATCH , to verify the rtx_reuse code .

"                (mem/v:BLK (reuse_rtx 0) [0  A8])\n"

"            ] UNSPEC_MEMORY_BLOCKAGE)))\n"


<s> static void mips_record_lo_sums ( const_rtx x , mips_offset_table * htab ) { subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , x , NONCONST ) if ( GET_CODE ( * iter ) == LO_SUM ) mips_lo_sum_offset_lookup ( htab , XEXP ( * iter , 1 ) , INSERT ) ; } </s>

Search X for LO_SUMs and record them in HTAB .


<s>
unsigned
ARMCodeEmitter
::
getMachineOpValue
(
const
MachineInstr
&
MI
,
const
MachineOperand
&
MO
)
const
{
if
(
MO
.
isReg
(
)
)
return
getARMRegisterNumbering
(
MO
.
getReg
(
)
)
;
else
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
else
if
(
MO
.
isGlobal
(
)
)
emitGlobalAddress
(
MO
.
getGlobal
(
)
,
ARM
::
reloc_arm_branch
,
true
,
false
)
;
else
if
(
MO
.
isSymbol
(
)
)
emitExternalSymbolAddress
(
MO
.
getSymbolName
(
)
,
ARM
::
reloc_arm_branch
)
;
else
if
(
MO
.
isCPI
(
)
)
{
const
TargetInstrDesc
&
TID
=
MI
.
getDesc
(
)
;
unsigned
Reloc
=
(
(
TID
.
TSFlags
&
ARMII
::
FormMask
)
==
ARMII
::
VFPLdStFrm
)
ARM
::
reloc_arm_vfp_cp_entry
:
ARM
::
reloc_arm_cp_entry
;
emitConstPoolAddress
(
MO
.
getIndex
(
)
,
Reloc
)
;
}
else
if
(
MO
.
isJTI
(
)
)
emitJumpTableAddress
(
MO
.
getIndex
(
)
,
ARM
::
reloc_arm_relative
)
;
else
if
(
MO
.
isMBB
(
)
)
emitMachineBasicBlock
(
MO
.
getMBB
(
)
,
ARM
::
reloc_arm_branch
)
;
else
llvm_unreachable
(
"Unable to encode MachineOperand!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> void c4x_optimization_options ( int level ATTRIBUTE_UNUSED , int size ATTRIBUTE_UNUSED ) { flag_schedule_insns = 0 ; } </s>

This is called before c4x_override_options .


<s> bool ARMTargetLowering :: isLegalInterleavedAccessType ( unsigned Factor , FixedVectorType * VecTy , Align Alignment , const DataLayout & DL ) const { unsigned VecSize = DL . getTypeSizeInBits ( VecTy ) ; unsigned ElSize = DL . getTypeSizeInBits ( VecTy -> getElementType ( ) ) ; if ( ! Subtarget -> hasNEON ( ) && ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; if ( Subtarget -> hasNEON ( ) && VecTy -> getElementType ( ) -> isHalfTy ( ) ) return false ; if ( Subtarget -> hasMVEIntegerOps ( ) && Factor == 3 ) return false ; if ( VecTy -> getNumElements ( ) < 2 ) return false ; if ( ElSize != 8 && ElSize != 16 && ElSize != 32 ) return false ; if ( Subtarget -> hasMVEIntegerOps ( ) && Alignment < ElSize / 8 ) return false ; if ( Subtarget -> hasNEON ( ) && VecSize == 64 ) return true ; return VecSize % 128 == 0 ; } </s>

Returns whether or not generating a interleaved load/store intrinsic for this type will be legal .


<s> SDValue AMDGPUTargetLowering :: SplitVectorStore ( SDValue Op , SelectionDAG & DAG ) const { StoreSDNode * Store = cast < StoreSDNode > ( Op ) ; EVT MemEltVT = Store -> getMemoryVT ( ) . getVectorElementType ( ) ; EVT EltVT = Store -> getValue ( ) . getValueType ( ) . getVectorElementType ( ) ; EVT PtrVT = Store -> getBasePtr ( ) . getValueType ( ) ; unsigned NumElts = Store -> getMemoryVT ( ) . getVectorNumElements ( ) ; SDLoc SL ( Op ) ; SmallVector < SDValue , 8 > Chains ; for ( unsigned i = 0 , e = NumElts ; i != e ; ++ i ) { SDValue Val = DAG . getNode ( ISD :: EXTRACT_VECTOR_ELT , SL , EltVT , Store -> getValue ( ) , DAG . getConstant ( i , MVT :: i32 ) ) ; SDValue Ptr = DAG . getNode ( ISD :: ADD , SL , PtrVT , Store -> getBasePtr ( ) , DAG . getConstant ( i * ( MemEltVT . getSizeInBits ( ) / 8 ) , PtrVT ) ) ; Chains . push_back ( DAG . getTruncStore ( Store -> getChain ( ) , SL , Val , Ptr , MachinePointerInfo ( Store -> getMemOperand ( ) -> getValue ( ) ) , MemEltVT , Store -> isVolatile ( ) , Store -> isNonTemporal ( ) , Store -> getAlignment ( ) ) ) ; } return DAG . getNode ( ISD :: TokenFactor , SL , MVT :: Other , Chains ) ; } </s>

Split a vector store into 2 stores of half the vector .


<s> void R600MCCodeEmitter :: Emit ( uint64_t Value , raw_ostream & OS ) const { support :: endian :: Writer < support :: little > ( OS ) . write ( Value ) ; } </s>

AMDGPU R600 support::endian support::little


<s> bool SPUFrameInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MFI -> getStackSize ( ) && ( DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> SDValue AArch64SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; ConstantSDNode * SizeValue = dyn_cast < ConstantSDNode > ( Size ) ; const AArch64Subtarget & STI = DAG . getMachineFunction ( ) . getSubtarget < AArch64Subtarget > ( ) ; const char * bzeroEntry = ( V && V -> isNullValue ( ) ) ? STI . getBZeroEntry ( ) : nullptr ; if ( bzeroEntry && ( ! SizeValue || SizeValue -> getZExtValue ( ) > 256 ) ) { const AArch64TargetLowering & TLI = * STI . getTargetLowering ( ) ; EVT IntPtr = TLI . getPointerTy ( ) ; Type * IntPtrTy = getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroEntry , IntPtr ) , std :: move ( Args ) , 0 ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memset .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> void PPCHazardRecognizer440 :: EmitInstruction ( SUnit * SU ) { const MCInstrDesc * MCID = DAG -> getInstrDesc ( SU ) ; if ( ! MCID ) { return ; } ScoreboardHazardRecognizer :: EmitInstruction ( SU ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void h8300_pr_interrupt ( struct cpp_reader * pfile ATTRIBUTE_UNUSED ) { pragma_interrupt = 1 ; } </s>

Handle machine specific pragmas for compatibility with existing compilers for the H8/300 . pragma saveall generates prolog/epilog code which saves and restores all the registers on function entry . pragma interrupt saves and restores all registers , and exits with an rte instruction rather than an rts . A pointer to a function with this attribute may be safely used in an interrupt vector .


<s> rtx sfunc_uses_reg ( rtx_insn * insn ) { int i ; rtx pattern , part , reg_part , reg ; if ( ! NONJUMP_INSN_P ( insn ) ) return NULL_RTX ; pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) != PARALLEL || get_attr_type ( insn ) != TYPE_SFUNC ) return NULL_RTX ; for ( reg_part = NULL_RTX , i = XVECLEN ( pattern , 0 ) - 1 ; i >= 1 ; i -- ) { part = XVECEXP ( pattern , 0 , i ) ; if ( GET_CODE ( part ) == USE && GET_MODE ( XEXP ( part , 0 ) ) == SImode ) reg_part = part ; } if ( ! reg_part ) return NULL_RTX ; reg = XEXP ( reg_part , 0 ) ; for ( int i = XVECLEN ( pattern , 0 ) - 1 ; i >= 0 ; i -- ) { part = XVECEXP ( pattern , 0 , i ) ; if ( part == reg_part || GET_CODE ( part ) == CLOBBER ) continue ; if ( reg_mentioned_p ( reg , ( ( GET_CODE ( part ) == SET && REG_P ( SET_DEST ( part ) ) ) ? SET_SRC ( part ) : part ) ) ) return NULL_RTX ; } return reg ; } </s>

If the instruction INSN is implemented by a special function , and we can positively find the register that is used to call the sfunc , and this register is not used anywhere else in this instruction - except as the destination of a set , return this register ; else , return 0 .


<s> void MipsAsmPrinter :: emitFrameDirective ( MachineFunction & MF ) { const TargetRegisterInfo & RI = * TM . getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ; O << "\t.frame\t" << '$' << LowercaseString ( RI . get ( stackReg ) . AsmName ) << ',' << stackSize << ',' << '$' << LowercaseString ( RI . get ( returnReg ) . AsmName ) << '\n' ; } </s>


<s> bool MipsCCState :: originalTypeIsVectorFloat ( const Type * Ty ) { if ( Ty -> isVectorTy ( ) && Ty -> isFPOrFPVectorTy ( ) ) return true ; return false ; } </s>

Return true if the original type was vXfXX / vXfXX .


<s> static inline bool save_global_or_fp_reg_p ( unsigned int regno , int leaf_function ATTRIBUTE_UNUSED ) { return ! call_used_or_fixed_reg_p ( regno ) && df_regs_ever_live_p ( regno ) ; } </s>

Return whether REGNO , a global or FP register , must be saved/restored .


<s> static void load_pic_register ( bool delay_pic_helper ) { int orig_flag_pic = flag_pic ; if ( ! pic_helper_symbol_name [ 0 ] ) { ASM_GENERATE_INTERNAL_LABEL ( pic_helper_symbol_name , "LADDPC" , 0 ) ; pic_helper_symbol = gen_rtx_SYMBOL_REF ( Pmode , pic_helper_symbol_name ) ; global_offset_table = gen_rtx_SYMBOL_REF ( Pmode , "_GLOBAL_OFFSET_TABLE_" ) ; } if ( ! delay_pic_helper && ! pic_helper_emitted_p ) emit_pic_helper ( ) ; flag_pic = 0 ; if ( TARGET_ARCH64 ) emit_insn ( gen_load_pcrel_symdi ( pic_offset_table_rtx , global_offset_table , pic_helper_symbol ) ) ; else emit_insn ( gen_load_pcrel_symsi ( pic_offset_table_rtx , global_offset_table , pic_helper_symbol ) ) ; flag_pic = orig_flag_pic ; emit_insn ( gen_rtx_USE ( VOIDmode , pic_offset_table_rtx ) ) ; } </s>


<s> void arc_expand_compare_and_swap ( rtx operands [ ] ) { rtx bval , rval , mem , oldval , newval , is_weak , mod_s , mod_f , x ; machine_mode mode ; bval = operands [ 0 ] ; rval = operands [ 1 ] ; mem = operands [ 2 ] ; oldval = operands [ 3 ] ; newval = operands [ 4 ] ; is_weak = operands [ 5 ] ; mod_s = operands [ 6 ] ; mod_f = operands [ 7 ] ; mode = GET_MODE ( mem ) ; if ( reg_overlap_mentioned_p ( rval , oldval ) ) oldval = copy_to_reg ( oldval ) ; if ( mode == SImode ) { emit_insn ( gen_atomic_compare_and_swapsi_1 ( rval , mem , oldval , newval , is_weak , mod_s , mod_f ) ) ; x = gen_rtx_REG ( CC_Zmode , CC_REG ) ; x = gen_rtx_EQ ( SImode , x , const0_rtx ) ; emit_insn ( gen_rtx_SET ( bval , x ) ) ; } else { arc_expand_compare_and_swap_qh ( bval , rval , mem , oldval , newval , is_weak , mod_s , mod_f ) ; } } </s>

Helper function used by `` atomic_compare_and_swap '' expand pattern .


<s> BitVector TVMRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( TVM :: SP ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> int rs6000_reg_parm_stack_space ( tree fun , bool incoming ) { int reg_parm_stack_space ; switch ( DEFAULT_ABI ) { default : reg_parm_stack_space = 0 ; break ; case ABI_AIX : case ABI_DARWIN : reg_parm_stack_space = TARGET_64BIT ? 64 : 32 ; break ; case ABI_ELFv2 : if ( rs6000_function_parms_need_stack ( fun , incoming ) ) reg_parm_stack_space = TARGET_64BIT ? 64 : 32 ; else reg_parm_stack_space = 0 ; break ; } return reg_parm_stack_space ; } </s>

Return the size of the REG_PARM_STACK_SPACE are for FUN . This is usually a constant depending on the ABI . However , in the ELFv2 ABI the register parameter area is optional when calling a function that has a prototype is scope , has no variable argument list , and passes all parameters in registers .


<s> bool SNESMCExpr :: evaluateAsConstant ( int64_t & Result ) const { MCValue Value ; bool isRelocatable = getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ; if ( ! isRelocatable ) return false ; if ( Value . isAbsolute ( ) ) { Result = evaluateAsInt64 ( Value . getConstant ( ) ) ; return true ; } return false ; } </s>

Evaluates the fixup as a constant value .


"using vector_length (%d), ignoring runtime setting"

Validate compute dimensions of an OpenACC offload or routine , fill in non-unity defaults . FN_LEVEL indicates the level at which a routine might spawn a loop . It is negative for non-routines . If DECL is null , we are validating the default dimensions .


<s> WebAssemblySubtarget & WebAssemblySubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { LLVM_DEBUG ( llvm :: dbgs ( ) << "initializeSubtargetDependencies\n" ) ; if ( CPU . empty ( ) ) CPU = "generic" ; ParseSubtargetFeatures ( CPU , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .

WebAssembly WebAssembly WebAssembly "initializeSubtargetDependencies\n" "generic"


<s> void emitValueImpl ( const MCExpr * Value , unsigned Size , SMLoc Loc ) override { EmitMappingSymbol ( "$d" ) ; MCELFStreamer :: emitValueImpl ( Value , Size , Loc ) ; } </s>

Overriding these functions allows us to dismiss all labels that are candidates for marking as microMIPS when .word/.long/.4byte etc directives are emitted .


<s> static int sh_pr_n_sets ( void ) { return REG_N_SETS ( TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG ) ; } </s>

For use by ALLOCATE_INITIAL_VALUE . Note that sh.md contains some 'special function ' patterns ( type sfunc ) that clobber pr , but that do not look like function calls to leaf_function_p . Hence we must do this extra check .


<s>
unsigned
PPCTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
)
const
{
bool
isPPC64
=
Subtarget
.
isPPC64
(
)
;
bool
isDarwinABI
=
Subtarget
.
isDarwinABI
(
)
;
if
(
(
isPPC64
&&
VT
!=
MVT
::
i64
&&
VT
!=
MVT
::
i32
)
||
(
!
isPPC64
&&
VT
!=
MVT
::
i32
)
)
report_fatal_error
(
"Invalid register global variable type"
)
;
bool
is64Bit
=
isPPC64
&&
VT
==
MVT
::
i64
;
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"r1"
,
is64Bit
PPC
::
X1
:
PPC
::
R1
)
.
Case
(
"r2"
,
isDarwinABI
0
:
(
is64Bit
PPC
::
X2
:
PPC
::
R2
)
)
.
Case
(
"r13"
,
(
!
isPPC64
&&
isDarwinABI
)
0
:
(
is64Bit
PPC
::
X13
:
PPC
::
R13
)
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> static int ia64_spec_check_p ( rtx x ) { x = PATTERN ( x ) ; if ( GET_CODE ( x ) == COND_EXEC ) x = COND_EXEC_CODE ( x ) ; if ( GET_CODE ( x ) == SET ) return ia64_spec_check_src_p ( SET_SRC ( x ) ) ; return 0 ; } </s>

Return nonzero , if X is branchy recovery check .


<s> BitVector AArch64RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const AArch64FrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , AArch64 :: WSP ) ; markSuperRegs ( Reserved , AArch64 :: WZR ) ; if ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) markSuperRegs ( Reserved , AArch64 :: W29 ) ; if ( MF . getSubtarget < AArch64Subtarget > ( ) . isX18Reserved ( ) ) markSuperRegs ( Reserved , AArch64 :: W18 ) ; if ( hasBasePointer ( MF ) ) markSuperRegs ( Reserved , AArch64 :: W19 ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>


<s> bool OptimizeLEAPass :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; if ( ! EnableX86LEAOpt || ! MF . getFunction ( ) -> optForSize ( ) ) return false ; MRI = & MF . getRegInfo ( ) ; TII = MF . getSubtarget < X86Subtarget > ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget < X86Subtarget > ( ) . getRegisterInfo ( ) ; for ( auto & MBB : MF ) { SmallVector < MachineInstr * , 16 > LEAs ; findLEAs ( MBB , LEAs ) ; if ( LEAs . empty ( ) ) continue ; Changed |= removeRedundantAddrCalc ( LEAs ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool hasFP ( const MachineFunction & ) const override { return true ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


"internal compiler error.  Incorrect shift:"

8bit logic shift right ( ( unsigned char ) x > > i )


<s> static rtx emit_memmov ( rtx destmem , rtx * srcmem , rtx destptr , rtx srcptr , HOST_WIDE_INT size_to_move ) { rtx dst = destmem , src = * srcmem , adjust , tempreg ; enum insn_code code ; machine_mode move_mode ; int piece_size , i ; piece_size = 1 << floor_log2 ( size_to_move ) ; move_mode = mode_for_size ( piece_size * BITS_PER_UNIT , MODE_INT , 0 ) ; code = optab_handler ( mov_optab , move_mode ) ; while ( code == CODE_FOR_nothing && piece_size > 1 ) { piece_size >>= 1 ; move_mode = mode_for_size ( piece_size * BITS_PER_UNIT , MODE_INT , 0 ) ; code = optab_handler ( mov_optab , move_mode ) ; } if ( GET_MODE_SIZE ( move_mode ) > GET_MODE_SIZE ( word_mode ) ) { int nunits = GET_MODE_SIZE ( move_mode ) / GET_MODE_SIZE ( word_mode ) ; move_mode = mode_for_vector ( word_mode , nunits ) ; code = optab_handler ( mov_optab , move_mode ) ; if ( code == CODE_FOR_nothing ) { move_mode = word_mode ; piece_size = GET_MODE_SIZE ( move_mode ) ; code = optab_handler ( mov_optab , move_mode ) ; } } gcc_assert ( code != CODE_FOR_nothing ) ; dst = adjust_automodify_address_nv ( dst , move_mode , destptr , 0 ) ; src = adjust_automodify_address_nv ( src , move_mode , srcptr , 0 ) ; gcc_assert ( size_to_move % piece_size == 0 ) ; adjust = GEN_INT ( piece_size ) ; for ( i = 0 ; i < size_to_move ; i += piece_size ) { tempreg = gen_reg_rtx ( move_mode ) ; emit_insn ( GEN_FCN ( code ) ( tempreg , src ) ) ; emit_insn ( GEN_FCN ( code ) ( dst , tempreg ) ) ; emit_move_insn ( destptr , gen_rtx_PLUS ( Pmode , copy_rtx ( destptr ) , adjust ) ) ; emit_move_insn ( srcptr , gen_rtx_PLUS ( Pmode , copy_rtx ( srcptr ) , adjust ) ) ; dst = adjust_automodify_address_nv ( dst , move_mode , destptr , piece_size ) ; src = adjust_automodify_address_nv ( src , move_mode , srcptr , piece_size ) ; } * srcmem = src ; return dst ; } </s>

This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to DESTMEM . SRC is passed by pointer to be updated on return . Return value is updated DST .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { const R600Subtarget & ST = MF . getSubtarget < R600Subtarget > ( ) ; TII = ST . getInstrInfo ( ) ; for ( MachineBasicBlock & MBB : MF ) { MachineBasicBlock :: iterator I = MBB . begin ( ) ; if ( I != MBB . end ( ) && I -> getOpcode ( ) == R600 :: CF_ALU ) continue ; for ( MachineBasicBlock :: iterator E = MBB . end ( ) ; I != E ; ) { if ( isALU ( * I ) ) { auto next = MakeALUClause ( MBB , I ) ; assert ( next != I ) ; I = next ; } else ++ I ; } } return false ; } </s>


<s> static rtx load_cr_save ( int regno , rtx frame_reg_rtx , int offset , bool exit_func ) { rtx mem = gen_frame_mem_offset ( SImode , frame_reg_rtx , offset ) ; rtx reg = gen_rtx_REG ( SImode , regno ) ; rtx_insn * insn = emit_move_insn ( reg , mem ) ; if ( ! exit_func && DEFAULT_ABI == ABI_V4 ) { rtx cr = gen_rtx_REG ( SImode , CR2_REGNO ) ; rtx set = gen_rtx_SET ( reg , cr ) ; add_reg_note ( insn , REG_CFA_REGISTER , set ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } return reg ; } </s>

Restoring cr is a two step process : loading a reg from the frame save , then moving the reg to cr . For ABI_V4 we must let the unwinder know that the stack location is no longer valid at or before the stack deallocation , but we ca n't emit a cfa_restore for cr at the stack deallocation like we do for other registers . The trouble is that it is possible for the move to cr to be scheduled after the stack deallocation . So say exactly where cr is located on each of the two insns .


<s>
BitVector
ARMBaseRegisterInfo
::
getReservedRegs
(
const
MachineFunction
&
MF
)
const
{
const
ARMSubtarget
&
STI
=
MF
.
getSubtarget
<
ARMSubtarget
>
(
)
;
const
ARMFrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
BitVector
Reserved
(
getNumRegs
(
)
)
;
Reserved
.
set
(
ARM
::
SP
)
;
Reserved
.
set
(
ARM
::
PC
)
;
Reserved
.
set
(
ARM
::
FPSCR
)
;
Reserved
.
set
(
ARM
::
APSR_NZCV
)
;
if
(
TFI
->
hasFP
(
MF
)
)
Reserved
.
set
(
getFramePointerReg
(
STI
)
)
;
if
(
hasBasePointer
(
MF
)
)
Reserved
.
set
(
BasePtr
)
;
if
(
STI
.
isR9Reserved
(
)
)
Reserved
.
set
(
ARM
::
R9
)
;
if
(
!
STI
.
hasVFP3
(
)
||
STI
.
hasD16
(
)
)
{
static_assert
(
ARM
::
D31
==
ARM
::
D16
+
15
,
"Register list not consecutive!"
)
;
Reserved
.
set
(
ARM
::
D16
,
ARM
::
D31
+
1
)
;
}
const
TargetRegisterClass
*
RC
=
&
ARM
::
GPRPairRegClass
;
for
(
TargetRegisterClass
::
iterator
I
=
RC
->
begin
(
)
,
E
=
RC
->
end
(
)
;
I
!=
E
;
++
I
)
for
(
MCSubRegIterator
SI
(
*
I
,
this
)
;
SI
.
isValid
(
)
;
++
SI
)
if
(
Reserved
.
test
(
*
SI
)
)
Reserved
.
set
(
*
I
)
;
return
Reserved
;
}
</s>


<s> rtx function_arg ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int named ATTRIBUTE_UNUSED ) { int bytes = avr_num_arg_regs ( mode , type ) ; if ( cum -> nregs && bytes <= cum -> nregs ) return gen_rtx_REG ( mode , cum -> regno - bytes ) ; return NULL_RTX ; } </s>

Return an RTL expression containing the register for the given mode , or 0 if the argument is to be passed on the stack . INCOMING_P is nonzero if this is an incoming argument to the current function .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Mips OptimizePICCall"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static bool rs6000_cannot_force_const_mem ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { if ( GET_CODE ( x ) == HIGH && GET_CODE ( XEXP ( x , 0 ) ) == UNSPEC ) return true ; if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( XEXP ( XEXP ( x , 0 ) , 0 ) ) != 0 ) return true ; return TARGET_ELF && tls_referenced_p ( x ) ; } </s>


<s> const ARM64RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static rtx tilegx_function_arg ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS cum = * get_cumulative_args ( cum_v ) ; int byte_size = arg . promoted_size_in_bytes ( ) ; bool doubleword_aligned_p ; if ( cum >= TILEGX_NUM_ARG_REGS ) return NULL_RTX ; doubleword_aligned_p = tilegx_function_arg_boundary ( arg . mode , arg . type ) > BITS_PER_WORD ; if ( doubleword_aligned_p ) cum += cum & 1 ; if ( ( cum + ( byte_size + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ) > TILEGX_NUM_ARG_REGS ) return NULL_RTX ; return gen_rtx_REG ( arg . mode , cum ) ; } </s>


<s> static bool mips_lx_address_p ( rtx addr , machine_mode mode ) { if ( GET_CODE ( addr ) != PLUS || ! REG_P ( XEXP ( addr , 0 ) ) || ! REG_P ( XEXP ( addr , 1 ) ) ) return false ; if ( ISA_HAS_LBX && mode == QImode ) return true ; if ( ISA_HAS_LHX && mode == HImode ) return true ; if ( ISA_HAS_LWX && mode == SImode ) return true ; if ( ISA_HAS_LDX && mode == DImode ) return true ; if ( MSA_SUPPORTED_MODE_P ( mode ) ) return true ; return false ; } </s>

Return true if ADDR matches the pattern for the L { B , H , W , D } { , U } X load indexed address instruction . Note that such addresses are not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense , because their use is so restricted .


<s> M68kSubtarget & M68kSubtarget :: initializeSubtargetDependencies ( StringRef CPU , Triple TT , StringRef FS , const M68kTargetMachine & TM ) { std :: string CPUName = selectM68kCPU ( TT , CPU ) . str ( ) ; ParseSubtargetFeatures ( CPUName , CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; stackAlignment = 8 ; return * this ; } </s>


<s> const R600Subtarget * R600TargetLowering :: getSubtarget ( ) const { return static_cast < const R600Subtarget * > ( Subtarget ) ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


<s> static unsigned int h8300_binary_length ( rtx_insn * insn , const h8300_length_table * table ) { rtx set ; rtx pattern ; if ( GET_CODE ( insn ) != INSN ) gcc_unreachable ( ) ; pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) == PARALLEL && GET_CODE ( XVECEXP ( pattern , 0 , 0 ) ) == SET && GET_CODE ( SET_SRC ( XVECEXP ( pattern , 0 , 0 ) ) ) == COMPARE ) set = XVECEXP ( pattern , 0 , 1 ) ; else set = single_set ( insn ) ; gcc_assert ( set ) ; if ( BINARY_P ( SET_SRC ( set ) ) ) return h8300_length_from_table ( XEXP ( SET_SRC ( set ) , 0 ) , XEXP ( SET_SRC ( set ) , 1 ) , table ) ; else { gcc_assert ( GET_RTX_CLASS ( GET_CODE ( SET_SRC ( set ) ) ) == RTX_TERNARY ) ; return h8300_length_from_table ( XEXP ( XEXP ( SET_SRC ( set ) , 1 ) , 0 ) , XEXP ( XEXP ( SET_SRC ( set ) , 1 ) , 1 ) , table ) ; } } </s>

Calculate the length of general binary instruction INSN using TABLE .


<s> int nios2_initial_elimination_offset ( int from , int to ) { int offset ; nios2_compute_frame_layout ( ) ; switch ( from ) { case FRAME_POINTER_REGNUM : offset = cfun -> machine -> args_size + cfun -> machine -> var_size ; break ; case ARG_POINTER_REGNUM : offset = cfun -> machine -> total_size ; offset -= crtl -> args . pretend_args_size ; break ; default : gcc_unreachable ( ) ; } if ( to == HARD_FRAME_POINTER_REGNUM ) offset -= ( cfun -> machine -> save_regs_offset + cfun -> machine -> fp_save_offset ) ; return offset ; } </s>

Implement INITIAL_ELIMINATION_OFFSET macro .


<s> void MCS51PassConfig :: addPreSched2 ( ) { addPass ( createMCS51RelaxMemPass ( ) ) ; addPass ( createMCS51ExpandPseudoPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s>
void
AlphaTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
{
DebugLoc
dl
=
N
->
getDebugLoc
(
)
;
assert
(
N
->
getValueType
(
0
)
==
MVT
::
i32
&&
N
->
getOpcode
(
)
==
ISD
::
VAARG
&&
"Unknown node to custom promote!"
)
;
SDValue
Chain
,
DataPtr
;
LowerVAARG
(
N
,
Chain
,
DataPtr
,
DAG
)
;
SDValue
Res
=
DAG
.
getLoad
(
N
->
getValueType
(
0
)
,
dl
,
Chain
,
DataPtr
,
,
0
,
false
,
false
,
0
)
;
Results
.
push_back
(
Res
)
;
Results
.
push_back
(
SDValue
(
Res
.
getNode
(
)
,
1
)
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s>
SDValue
AMDGPUTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
Op
->
print
(
errs
(
)
,
&
DAG
)
;
llvm_unreachable
(
"Custom lowering code for this"
"instruction is not implemented yet!"
)
;
break
;
case
ISD
::
SIGN_EXTEND_INREG
:
return
LowerSIGN_EXTEND_INREG
(
Op
,
DAG
)
;
case
ISD
::
CONCAT_VECTORS
:
return
LowerCONCAT_VECTORS
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_SUBVECTOR
:
return
LowerEXTRACT_SUBVECTOR
(
Op
,
DAG
)
;
case
ISD
::
UDIVREM
:
return
LowerUDIVREM
(
Op
,
DAG
)
;
case
ISD
::
SDIVREM
:
return
LowerSDIVREM
(
Op
,
DAG
)
;
case
ISD
::
FREM
:
return
LowerFREM
(
Op
,
DAG
)
;
case
ISD
::
FCEIL
:
return
LowerFCEIL
(
Op
,
DAG
)
;
case
ISD
::
FTRUNC
:
return
LowerFTRUNC
(
Op
,
DAG
)
;
case
ISD
::
FRINT
:
return
LowerFRINT
(
Op
,
DAG
)
;
case
ISD
::
FNEARBYINT
:
return
LowerFNEARBYINT
(
Op
,
DAG
)
;
case
ISD
::
FROUND
:
return
LowerFROUND
(
Op
,
DAG
)
;
case
ISD
::
FFLOOR
:
return
LowerFFLOOR
(
Op
,
DAG
)
;
case
ISD
::
FLOG
:
return
LowerFLOG
(
Op
,
DAG
,
1.0F
/
numbers
::
log2ef
)
;
case
ISD
::
FLOG10
:
return
LowerFLOG
(
Op
,
DAG
,
numbers
::
ln2f
/
numbers
::
ln10f
)
;
case
ISD
::
FEXP
:
return
lowerFEXP
(
Op
,
DAG
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerSINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
UINT_TO_FP
:
return
LowerUINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_FP16
:
return
LowerFP_TO_FP16
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_SINT
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_UINT
(
Op
,
DAG
)
;
case
ISD
::
CTTZ
:
case
ISD
::
CTTZ_ZERO_UNDEF
:
case
ISD
::
CTLZ
:
case
ISD
::
CTLZ_ZERO_UNDEF
:
return
LowerCTLZ_CTTZ
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
}
return
Op
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool RISCVRegisterInfo :: isAsmClobberable ( const MachineFunction & MF , MCRegister PhysReg ) const { return ! MF . getSubtarget < RISCVSubtarget > ( ) . isRegisterReservedByUser ( PhysReg ) ; } </s>

Returns false if we ca n't guarantee that Physreg , specified as an IR asm clobber constraint , will be preserved across the statement .


<s> bool X86TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_X86 ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> Value * RISCVTargetLowering :: emitMaskedAtomicRMWIntrinsic ( IRBuilderBase & Builder , AtomicRMWInst * AI , Value * AlignedAddr , Value * Incr , Value * Mask , Value * ShiftAmt , AtomicOrdering Ord ) const { unsigned XLen = Subtarget . getXLen ( ) ; Value * Ordering = Builder . getIntN ( XLen , static_cast < uint64_t > ( AI -> getOrdering ( ) ) ) ; Type * Tys [ ] = { AlignedAddr -> getType ( ) } ; Function * LrwOpScwLoop = Intrinsic :: getDeclaration ( AI -> getModule ( ) , getIntrinsicForMaskedAtomicRMWBinOp ( XLen , AI -> getOperation ( ) ) , Tys ) ; if ( XLen == 64 ) { Incr = Builder . CreateSExt ( Incr , Builder . getInt64Ty ( ) ) ; Mask = Builder . CreateSExt ( Mask , Builder . getInt64Ty ( ) ) ; ShiftAmt = Builder . CreateSExt ( ShiftAmt , Builder . getInt64Ty ( ) ) ; } Value * Result ; if ( AI -> getOperation ( ) == AtomicRMWInst :: Min || AI -> getOperation ( ) == AtomicRMWInst :: Max ) { const DataLayout & DL = AI -> getModule ( ) -> getDataLayout ( ) ; unsigned ValWidth = DL . getTypeStoreSizeInBits ( AI -> getValOperand ( ) -> getType ( ) ) ; Value * SextShamt = Builder . CreateSub ( Builder . getIntN ( XLen , XLen - ValWidth ) , ShiftAmt ) ; Result = Builder . CreateCall ( LrwOpScwLoop , { AlignedAddr , Incr , Mask , SextShamt , Ordering } ) ; } else { Result = Builder . CreateCall ( LrwOpScwLoop , { AlignedAddr , Incr , Mask , Ordering } ) ; } if ( XLen == 64 ) Result = Builder . CreateTrunc ( Result , Builder . getInt32Ty ( ) ) ; return Result ; } </s>

Perform a masked atomicrmw using a target-specific intrinsic .


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , int64_t NumBytes , bool Is64Bit , bool UseLEA , const TargetInstrInfo & TII , const TargetRegisterInfo & TRI , DebugLoc DL ) { bool isSub = NumBytes < 0 ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; unsigned Opc ; if ( UseLEA ) Opc = getLEArOpcode ( Is64Bit ) ; else Opc = isSub ? getSUBriOpcode ( Is64Bit , Offset ) : getADDriOpcode ( Is64Bit , Offset ) ; uint64_t Chunk = ( 1LL << 31 ) - 1 ; while ( Offset ) { uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; if ( ThisVal == ( Is64Bit ? 8 : 4 ) ) { unsigned Reg = isSub ? ( unsigned ) ( Is64Bit ? X86 :: RAX : X86 :: EAX ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { Opc = isSub ? ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) : ( Is64Bit ? X86 :: POP64r : X86 :: POP32r ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ; if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; Offset -= ThisVal ; continue ; } } MachineInstr * MI = NULL ; if ( UseLEA ) { MI = addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) , StackPtr , false , isSub ? - ThisVal : ThisVal ) ; } else { MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( ThisVal ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; } if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s>
CCAssignFn
*
ARMFastISel
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
Return
)
{
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
(
void
)
RetFastCC_ARM_APCS
;
(
void
)
FastCC_ARM_APCS
;
case
CallingConv
::
C
:
if
(
Subtarget
->
isAAPCS_ABI
(
)
)
{
if
(
Subtarget
->
hasVFP2
(
)
&&
TM
.
Options
.
FloatABIType
==
FloatABI
::
Hard
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
else
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
}
else
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
case
CallingConv
::
ARM_AAPCS_VFP
:
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
case
CallingConv
::
ARM_AAPCS
:
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
case
CallingConv
::
ARM_APCS
:
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .

ARM
ARM
"Unsupported calling convention"
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM


<s> static void nvptx_goacc_reduction ( gcall * call ) { unsigned code = ( unsigned ) TREE_INT_CST_LOW ( gimple_call_arg ( call , 0 ) ) ; switch ( code ) { case IFN_GOACC_REDUCTION_SETUP : nvptx_goacc_reduction_setup ( call ) ; break ; case IFN_GOACC_REDUCTION_INIT : nvptx_goacc_reduction_init ( call ) ; break ; case IFN_GOACC_REDUCTION_FINI : nvptx_goacc_reduction_fini ( call ) ; break ; case IFN_GOACC_REDUCTION_TEARDOWN : nvptx_goacc_reduction_teardown ( call ) ; break ; default : gcc_unreachable ( ) ; } } </s>


<s> const uint32_t * SystemZRegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { return CSR_SystemZ_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
void
SystemZMCAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
MCFixupKind
Kind
=
Fixup
.
getKind
(
)
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
unsigned
BitSize
=
getFixupKindInfo
(
Kind
)
.
TargetSize
;
unsigned
Size
=
(
BitSize
+
7
)
/
8
;
assert
(
Offset
+
Size
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
Value
=
extractBitsForFixup
(
Kind
,
Value
)
;
if
(
BitSize
<
64
)
Value
&=
(
(
uint64_t
)
1
<<
BitSize
)
1
;
unsigned
ShiftValue
=
(
Size
*
8
)
8
;
for
(
unsigned
I
=
0
;
I
!=
Size
;
++
I
)
{
Data
[
Offset
+
I
]
|=
uint8_t
(
Value
>>
ShiftValue
)
;
ShiftValue
-=
8
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void build_mask64_2_operands ( rtx in , rtx * out ) { unsigned HOST_WIDE_INT c , lsb , m1 , m2 ; int shift ; gcc_assert ( GET_CODE ( in ) == CONST_INT ) ; c = INTVAL ( in ) ; if ( c & 1 ) { c = ~ c ; lsb = c & - c ; m1 = - lsb ; c = ~ c ; c &= - lsb ; lsb = c & - c ; c = ~ c ; c &= - lsb ; shift = 0 ; while ( ( lsb >>= 1 ) != 0 ) shift ++ ; m1 <<= 64 - shift ; m1 = ~ m1 ; m2 = ~ c ; } else { lsb = c & - c ; m2 = - lsb ; c = ~ c ; c &= - lsb ; lsb = c & - c ; c = ~ c ; c &= - lsb ; shift = 0 ; while ( ( lsb >>= 1 ) != 0 ) shift ++ ; m1 = ~ c ; m1 >>= shift ; m1 = ~ m1 ; } out [ 0 ] = GEN_INT ( 64 - shift ) ; out [ 1 ] = GEN_INT ( m1 ) ; out [ 2 ] = GEN_INT ( shift ) ; out [ 3 ] = GEN_INT ( m2 ) ; } </s>

Generates shifts and masks for a pair of rldicl or rldicr insns to implement ANDing by the mask IN .


<s> void sparc_expand_prologue ( void ) { HOST_WIDE_INT size ; rtx_insn * insn ; sparc_leaf_function_p = optimize > 0 && crtl -> is_leaf && only_leaf_regs_used ( ) ; size = sparc_compute_frame_size ( get_frame_size ( ) , sparc_leaf_function_p ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = size ; if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK || flag_stack_clash_protection ) { if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { if ( size > PROBE_INTERVAL && size > get_stack_check_protect ( ) ) sparc_emit_probe_stack_range ( get_stack_check_protect ( ) , size - get_stack_check_protect ( ) ) ; } else if ( size > 0 ) sparc_emit_probe_stack_range ( get_stack_check_protect ( ) , size ) ; } if ( size == 0 ) ; else if ( sparc_leaf_function_p ) { rtx size_int_rtx = GEN_INT ( - size ) ; if ( size <= 4096 ) insn = emit_insn ( gen_stack_pointer_inc ( size_int_rtx ) ) ; else if ( size <= 8192 ) { insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - 4096 ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( 4096 - size ) ) ) ; } else { rtx size_rtx = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( size_rtx , size_int_rtx ) ; insn = emit_insn ( gen_stack_pointer_inc ( size_rtx ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_stack_pointer_inc ( size_int_rtx ) ) ; } RTX_FRAME_RELATED_P ( insn ) = 1 ; } else { rtx size_int_rtx = GEN_INT ( - size ) ; if ( size <= 4096 ) emit_window_save ( size_int_rtx ) ; else if ( size <= 8192 ) { emit_window_save ( GEN_INT ( - 4096 ) ) ; emit_insn ( gen_stack_pointer_inc ( GEN_INT ( 4096 - size ) ) ) ; emit_insn ( gen_frame_blockage ( ) ) ; } else { rtx size_rtx = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( size_rtx , size_int_rtx ) ; emit_window_save ( size_rtx ) ; } } if ( sparc_leaf_function_p ) { sparc_frame_base_reg = stack_pointer_rtx ; sparc_frame_base_offset = size + SPARC_STACK_BIAS ; } else { sparc_frame_base_reg = hard_frame_pointer_rtx ; sparc_frame_base_offset = SPARC_STACK_BIAS ; } if ( sparc_n_global_fp_regs > 0 ) emit_save_or_restore_global_fp_regs ( sparc_frame_base_reg , sparc_frame_base_offset - sparc_apparent_frame_size , SORR_SAVE ) ; sparc_prologue_data_valid_p = true ; } </s>

Expand the function prologue . The prologue is responsible for reserving storage for the frame , saving the call-saved registers and loading the PIC register if needed .


<s>
bool
M88kInstrInfo
::
isBranchOffsetInRange
(
unsigned
BranchOpc
,
int64_t
BrOffset
)
const
{
assert
(
isAnalyzableBranchOpc
(
BranchOpc
)
&&
"Unexpected branch opcode"
)
;
int
Bits
=
(
BranchOpc
==
M88k
::
BR
||
BranchOpc
==
M88k
::
BSR
)
26
:
16
;
return
isIntN
(
Bits
,
BrOffset
/
4
)
;
}
</s>

Determine if the branch target is in range .


<s> bool AArch64AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { OS . write_zeros ( Count % 4 ) ; Count /= 4 ; for ( uint64_t i = 0 ; i != Count ; ++ i ) support :: endian :: write < uint32_t > ( OS , 0xd503201f , Endian ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> bool AArch64CompressJumpTables :: runOnMachineFunction ( MachineFunction & MFIn ) { bool Changed = false ; MF = & MFIn ; const auto & ST = MF -> getSubtarget < AArch64Subtarget > ( ) ; TII = ST . getInstrInfo ( ) ; if ( ST . force32BitJumpTables ( ) && ! MF -> getFunction ( ) . hasMinSize ( ) ) return false ; if ( ! scanFunction ( ) ) return false ; for ( MachineBasicBlock & MBB : * MF ) { int Offset = BlockInfo [ MBB . getNumber ( ) ] ; for ( MachineInstr & MI : MBB ) { Changed |= compressJumpTable ( MI , Offset ) ; Offset += TII -> getInstSizeInBytes ( MI ) ; } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool AArch64TargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , unsigned Intrinsic ) const { switch ( Intrinsic ) { case Intrinsic :: arm_neon_vld1 : case Intrinsic :: arm_neon_vld2 : case Intrinsic :: arm_neon_vld3 : case Intrinsic :: arm_neon_vld4 : { Info . opc = ISD :: INTRINSIC_W_CHAIN ; uint64_t NumElts = getDataLayout ( ) -> getTypeAllocSize ( I . getType ( ) ) / 8 ; Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , MVT :: i64 , NumElts ) ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Value * AlignArg = I . getArgOperand ( I . getNumArgOperands ( ) - 1 ) ; Info . align = cast < ConstantInt > ( AlignArg ) -> getZExtValue ( ) ; Info . vol = false ; Info . readMem = true ; Info . writeMem = false ; return true ; } case Intrinsic :: arm_neon_vst1 : case Intrinsic :: arm_neon_vst2 : case Intrinsic :: arm_neon_vst3 : case Intrinsic :: arm_neon_vst4 : { Info . opc = ISD :: INTRINSIC_VOID ; unsigned NumElts = 0 ; for ( unsigned ArgI = 1 , ArgE = I . getNumArgOperands ( ) ; ArgI < ArgE ; ++ ArgI ) { Type * ArgTy = I . getArgOperand ( ArgI ) -> getType ( ) ; if ( ! ArgTy -> isVectorTy ( ) ) break ; NumElts += getDataLayout ( ) -> getTypeAllocSize ( ArgTy ) / 8 ; } Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , MVT :: i64 , NumElts ) ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Value * AlignArg = I . getArgOperand ( I . getNumArgOperands ( ) - 1 ) ; Info . align = cast < ConstantInt > ( AlignArg ) -> getZExtValue ( ) ; Info . vol = false ; Info . readMem = false ; Info . writeMem = true ; return true ; } default : break ; } return false ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> static bool aarch64_return_in_memory ( const_tree type , const_tree fndecl ATTRIBUTE_UNUSED ) { pure_scalable_type_info pst_info ; switch ( pst_info . analyze ( type ) ) { case pure_scalable_type_info :: IS_PST : return ( pst_info . num_zr ( ) > NUM_FP_ARG_REGS || pst_info . num_pr ( ) > NUM_PR_ARG_REGS ) ; case pure_scalable_type_info :: DOESNT_MATTER : gcc_assert ( aarch64_return_in_memory_1 ( type ) ) ; return true ; case pure_scalable_type_info :: NO_ABI_IDENTITY : case pure_scalable_type_info :: ISNT_PST : return aarch64_return_in_memory_1 ( type ) ; } gcc_unreachable ( ) ; } </s>

Implement TARGET_RETURN_IN_MEMORY . If the type T of the result of a function is such that void func ( T arg ) would require that arg be passed as a value in a register ( or set of registers ) according to the parameter passing rules , then the result is returned in the same registers as would be used for such an argument .


<s> rtx mips_unspec_address ( rtx address , enum mips_symbol_type symbol_type ) { rtx base , offset ; split_const ( address , & base , & offset ) ; return mips_unspec_address_offset ( base , offset , symbol_type ) ; } </s>

Return an UNSPEC address with underlying address ADDRESS and symbol type SYMBOL_TYPE .


<s> void MipsAsmPrinter :: emitFrameDirective ( ) { const TargetRegisterInfo & RI = * TM . getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) -> getStackSize ( ) ; getTargetStreamer ( ) . emitFrame ( stackReg , stackSize , returnReg ) ; } </s>


<s> bool AArch64PassConfig :: addILPOpts ( ) { if ( EnableCondOpt ) addPass ( createAArch64ConditionOptimizerPass ( ) ) ; if ( EnableCCMP ) addPass ( createAArch64ConditionalCompares ( ) ) ; if ( EnableMCR ) addPass ( & MachineCombinerID ) ; if ( EnableCondBrTuning ) addPass ( createAArch64CondBrTuning ( ) ) ; if ( EnableEarlyIfConversion ) addPass ( & EarlyIfConverterID ) ; if ( EnableStPairSuppress ) addPass ( createAArch64StorePairSuppressPass ( ) ) ; addPass ( createAArch64SIMDInstrOptPass ( ) ) ; return true ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .


<s> void MOSFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo & TRI = * MF . getRegInfo ( ) . getTargetRegisterInfo ( ) ; MachineIRBuilder Builder ( MBB , MBB . begin ( ) ) ; int64_t StackSize = MFI . getStackSize ( ) ; if ( isISR ( MF ) ) StackSize += 256 ; if ( StackSize ) offsetSP ( Builder , - StackSize ) ; if ( ! hasFP ( MF ) ) return ; auto MBBI = std :: find_if_not ( Builder . getInsertPt ( ) , MBB . end ( ) , [ ] ( const MachineInstr & MI ) { return MI . getFlag ( MachineInstr :: FrameSetup ) ; } ) ; Builder . setInsertPt ( MBB , MBBI ) ; Builder . buildCopy ( TRI . getFrameRegister ( MF ) , Register ( MOS :: RS0 ) ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


"Unexpected register class in CSRsViaCopy!"

"Function should be nounwind in insertCopiesSplitCSR!"

Insert explicit copies in entry and exit blocks .


<s> void X86FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { const Function * Fn = MF . getFunction ( ) ; if ( ! STI . is64Bit ( ) || ! MF . getMMI ( ) . hasEHFunclets ( ) || classifyEHPersonality ( Fn -> getPersonalityFn ( ) ) != EHPersonality :: MSVC_CXX ) return ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; WinEHFuncInfo & EHInfo = * MF . getWinEHFuncInfo ( ) ; int64_t MinFixedObjOffset = - SlotSize ; for ( int I = MFI . getObjectIndexBegin ( ) ; I < 0 ; ++ I ) MinFixedObjOffset = std :: min ( MinFixedObjOffset , MFI . getObjectOffset ( I ) ) ; for ( WinEHTryBlockMapEntry & TBME : EHInfo . TryBlockMap ) { for ( WinEHHandlerType & H : TBME . HandlerArray ) { int FrameIndex = H . CatchObj . FrameIndex ; if ( FrameIndex != INT_MAX ) { unsigned Align = MFI . getObjectAlignment ( FrameIndex ) ; MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % Align ; MinFixedObjOffset -= MFI . getObjectSize ( FrameIndex ) ; MFI . setObjectOffset ( FrameIndex , MinFixedObjOffset ) ; } } } MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % 8 ; int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize ; int UnwindHelpFI = MFI . CreateFixedObject ( SlotSize , UnwindHelpOffset , false ) ; EHInfo . UnwindHelpFrameIdx = UnwindHelpFI ; MachineBasicBlock & MBB = MF . front ( ) ; auto MBBI = MBB . begin ( ) ; while ( MBBI != MBB . end ( ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) ) ++ MBBI ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; addFrameReference ( BuildMI ( MBB , MBBI , DL , TII . get ( X86 :: MOV64mi32 ) ) , UnwindHelpFI ) . addImm ( - 2 ) ; } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> void ARMBaseInstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , unsigned SubIdx , const MachineInstr * Orig , const TargetRegisterInfo * TRI ) const { if ( SubIdx && TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) { DestReg = TRI -> getSubReg ( DestReg , SubIdx ) ; SubIdx = 0 ; } unsigned Opcode = Orig -> getOpcode ( ) ; switch ( Opcode ) { default : { MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( Orig ) ; MI -> getOperand ( 0 ) . setReg ( DestReg ) ; MBB . insert ( I , MI ) ; break ; } case ARM :: tLDRpci_pic : case ARM :: t2LDRpci_pic : { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CPI = Orig -> getOperand ( 1 ) . getIndex ( ) ; unsigned PCLabelId = duplicateCPV ( MF , CPI ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , Orig -> getDebugLoc ( ) , get ( Opcode ) , DestReg ) . addConstantPoolIndex ( CPI ) . addImm ( PCLabelId ) ; ( * MIB ) . setMemRefs ( Orig -> memoperands_begin ( ) , Orig -> memoperands_end ( ) ) ; break ; } } MachineInstr * NewMI = prior ( I ) ; NewMI -> getOperand ( 0 ) . setSubReg ( SubIdx ) ; } </s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


"VOP* instruction uses the constant bus more than once"

"VOP3 src0 cannot be a literal constant."

"VOP3 src1 cannot be a literal constant."

"VOP3 src2 cannot be a literal constant."

Perform target-specific instruction verification .


<s> bool AArch64AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { OS . write_zeros ( Count % 4 ) ; Count /= 4 ; for ( uint64_t i = 0 ; i != Count ; ++ i ) OS . write ( "\x1f\x20\x03\xd5" , 4 ) ; return true ; } </s>


<s> unsigned getNumFixupKinds ( ) const override { return 1 ; } </s>

Get the number of target specific fixup kinds .


<s> uint64_t VEMCCodeEmitter :: getBranchTargetOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , ( MCFixupKind ) VE :: fixup_ve_pc_lo32 ) ) ; return 0 ; } </s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s> static void mips_sim_issue_nop ( struct mips_sim * state ) { if ( state -> insns_left == 0 ) mips_sim_next_cycle ( state ) ; state -> insns_left -- ; } </s>


<s>
void
arc_final_prescan_insn
(
rtx_insn
*
insn
,
rtx
*
opvec
ATTRIBUTE_UNUSED
,
int
noperands
ATTRIBUTE_UNUSED
)
{
if
(
TARGET_DUMPISIZE
)
fprintf
(
asm_out_file
,
"\n; at %04x\n"
,
INSN_ADDRESSES
(
INSN_UID
(
insn
)
)
)
;
if
(
!
cfun
->
machine
->
prescan_initialized
)
{
memset
(
&
arc_ccfsm_current
,
0
,
sizeof
arc_ccfsm_current
)
;
cfun
->
machine
->
prescan_initialized
=
1
;
}
arc_ccfsm_advance
(
insn
,
&
arc_ccfsm_current
)
;
cfun
->
machine
->
size_reason
=
0
;
}
</s>

The state of the fsm controlling condition codes are : 0 : normal , do nothing special 1 : do n't output this insn 2 : do n't output this insn 3 : make insns conditional 4 : make insns conditional State transitions ( state- > state by whom , under what condition ) : 0 - > 1 final_prescan_insn , if insn is conditional branch 0 - > 2 final_prescan_insn , if the ` target ' is an unconditional branch 1 - > 3 branch patterns , after having not output the conditional branch 2 - > 4 branch patterns , after having not output the conditional branch 3 - > 0 ( * targetm.asm_out.internal_label ) , if the ` target ' label is reached ( the target label has CODE_LABEL_NUMBER equal to arc_ccfsm_target_label ) . 4 - > 0 final_prescan_insn , if ` target ' unconditional branch is reached If the jump clobbers the conditions then we use states 2 and 4 . A similar thing can be done with conditional return insns . We also handle separating branches from sets of the condition code . This is done here because knowledge of the ccfsm state is required , we may not be outputting the branch .


<s> bool LanaiAsmParser :: ParseDirective ( AsmToken DirectiveId ) { return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s>
SDValue
X86TargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
bool
Is64Bit
=
Subtarget
->
is64Bit
(
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_X86
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
CopyVT
=
VA
.
getLocVT
(
)
;
if
(
(
CopyVT
==
MVT
::
f32
||
CopyVT
==
MVT
::
f64
)
&&
(
(
Is64Bit
||
Ins
[
i
]
.
Flags
.
isInReg
(
)
)
&&
!
Subtarget
->
hasSSE1
(
)
)
)
{
report_fatal_error
(
"SSE register return with SSE disabled"
)
;
}
bool
RoundAfterCopy
=
false
;
if
(
(
VA
.
getLocReg
(
)
==
X86
::
FP0
||
VA
.
getLocReg
(
)
==
X86
::
FP1
)
&&
isScalarFPTypeInSSEReg
(
VA
.
getValVT
(
)
)
)
{
CopyVT
=
MVT
::
f80
;
RoundAfterCopy
=
(
CopyVT
!=
VA
.
getLocVT
(
)
)
;
}
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
CopyVT
,
InFlag
)
.
getValue
(
1
)
;
SDValue
Val
=
Chain
.
getValue
(
0
)
;
if
(
RoundAfterCopy
)
Val
=
DAG
.
getNode
(
ISD
::
FP_ROUND
,
dl
,
VA
.
getValVT
(
)
,
Val
,
DAG
.
getIntPtrConstant
(
1
,
dl
)
)
;
if
(
VA
.
isExtInLoc
(
)
&&
VA
.
getValVT
(
)
.
getScalarType
(
)
==
MVT
::
i1
)
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
InFlag
=
Chain
.
getValue
(
2
)
;
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static unsigned getReg ( const void * D , unsigned RC , unsigned RegNo ) { const MipsDisassemblerBase * Dis = static_cast < const MipsDisassemblerBase * > ( D ) ; return * ( Dis -> getRegInfo ( ) -> getRegClass ( RC ) . begin ( ) + RegNo ) ; } </s>

Returns the register associated with this edge .


<s> MCInst const & getDesc ( ) const { return * ID ; } </s>

Returns the target instruction descriptor of this MachineInstr .


<s> void MipsSEInstrInfo :: adjustStackPtr ( unsigned SP , int64_t Amount , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { MipsABIInfo ABI = Subtarget . getABI ( ) ; DebugLoc DL ; unsigned ADDiu = ABI . GetPtrAddiuOp ( ) ; if ( Amount == 0 ) return ; if ( ABI . IsCheriPureCap ( ) ) { if ( isInt < 11 > ( Amount ) ) { BuildMI ( MBB , I , DL , get ( Mips :: CIncOffsetImm ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; } else { unsigned Reg = loadImmediate ( Amount , MBB , I , DL , nullptr ) ; BuildMI ( MBB , I , DL , get ( Mips :: CIncOffset ) , SP ) . addReg ( SP ) . addReg ( Reg , RegState :: Kill ) ; } } else if ( isInt < 16 > ( Amount ) ) { BuildMI ( MBB , I , DL , get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; } else { unsigned Opc = ABI . GetPtrAdduOp ( ) ; if ( Amount < 0 ) { Opc = ABI . GetPtrSubuOp ( ) ; Amount = - Amount ; } unsigned Reg = loadImmediate ( Amount , MBB , I , DL , nullptr ) ; BuildMI ( MBB , I , DL , get ( Opc ) , SP ) . addReg ( SP ) . addReg ( Reg , RegState :: Kill ) ; } } </s>


<s> const Z80oldRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static int mn10300_arg_partial_bytes ( cumulative_args_t cum_v , machine_mode mode , tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int size ; int nregs = 2 ; if ( mode == BLKmode ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; cum -> nbytes = ( cum -> nbytes + 3 ) & ~ 3 ; if ( cum -> nbytes > nregs * UNITS_PER_WORD ) return 0 ; if ( cum -> nbytes + size <= nregs * UNITS_PER_WORD ) return 0 ; if ( type == NULL_TREE && cum -> nbytes + size > nregs * UNITS_PER_WORD ) return 0 ; return nregs * UNITS_PER_WORD - cum -> nbytes ; } </s>

Return the number of bytes of registers to use for an argument passed partially in registers and partially in memory .


<s> bool error ( const Twine & Msg ) { return Parser . Error ( Lexer . getTok ( ) . getLoc ( ) , Msg ) ; } </s>

Convenience method for printing `` error : `` to the given stream .


<s> bool AArch64RegisterInfo :: requiresFrameIndexScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> static void sparc_solaris_elf_asm_named_section ( const char * name , unsigned int flags , tree decl ATTRIBUTE_UNUSED ) { if ( HAVE_COMDAT_GROUP && flags & SECTION_LINKONCE ) { solaris_elf_asm_comdat_section ( name , flags , decl ) ; return ; } fprintf ( asm_out_file , "\t.section\t\"%s\"" , name ) ; if ( ! ( flags & SECTION_DEBUG ) ) fputs ( ",#alloc" , asm_out_file ) ; if ( flags & SECTION_WRITE ) fputs ( ",#write" , asm_out_file ) ; if ( flags & SECTION_TLS ) fputs ( ",#tls" , asm_out_file ) ; if ( flags & SECTION_CODE ) fputs ( ",#execinstr" , asm_out_file ) ; if ( HAVE_AS_SPARC_NOBITS ) { if ( flags & SECTION_BSS ) fputs ( ",#nobits" , asm_out_file ) ; else fputs ( ",#progbits" , asm_out_file ) ; } fputc ( '\n' , asm_out_file ) ; } </s>

Solaris implementation of TARGET_ASM_NAMED_SECTION .

sparc "\t.section\t\"%s\"" ",#alloc" ",#write" ",#tls" ",#execinstr" ",#nobits" ",#progbits"


<s> void R600MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; if ( MI . getOpcode ( ) == AMDGPU :: RETURN || MI . getOpcode ( ) == AMDGPU :: FETCH_CLAUSE || MI . getOpcode ( ) == AMDGPU :: ALU_CLAUSE || MI . getOpcode ( ) == AMDGPU :: BUNDLE || MI . getOpcode ( ) == AMDGPU :: KILL ) { return ; } else if ( IS_VTX ( Desc ) ) { uint64_t InstWord01 = getBinaryCodeForInstr ( MI , Fixups , STI ) ; uint32_t InstWord2 = MI . getOperand ( 2 ) . getImm ( ) ; if ( ! ( STI . getFeatureBits ( ) [ AMDGPU :: FeatureCaymanISA ] ) ) { InstWord2 |= 1 << 19 ; } Emit ( InstWord01 , OS ) ; Emit ( InstWord2 , OS ) ; Emit ( ( uint32_t ) 0 , OS ) ; } else if ( IS_TEX ( Desc ) ) { int64_t Sampler = MI . getOperand ( 14 ) . getImm ( ) ; int64_t SrcSelect [ 4 ] = { MI . getOperand ( 2 ) . getImm ( ) , MI . getOperand ( 3 ) . getImm ( ) , MI . getOperand ( 4 ) . getImm ( ) , MI . getOperand ( 5 ) . getImm ( ) } ; int64_t Offsets [ 3 ] = { MI . getOperand ( 6 ) . getImm ( ) & 0x1F , MI . getOperand ( 7 ) . getImm ( ) & 0x1F , MI . getOperand ( 8 ) . getImm ( ) & 0x1F } ; uint64_t Word01 = getBinaryCodeForInstr ( MI , Fixups , STI ) ; uint32_t Word2 = Sampler << 15 | SrcSelect [ ELEMENT_X ] << 20 | SrcSelect [ ELEMENT_Y ] << 23 | SrcSelect [ ELEMENT_Z ] << 26 | SrcSelect [ ELEMENT_W ] << 29 | Offsets [ 0 ] << 0 | Offsets [ 1 ] << 5 | Offsets [ 2 ] << 10 ; Emit ( Word01 , OS ) ; Emit ( Word2 , OS ) ; Emit ( ( uint32_t ) 0 , OS ) ; } else { uint64_t Inst = getBinaryCodeForInstr ( MI , Fixups , STI ) ; if ( ( STI . getFeatureBits ( ) [ AMDGPU :: FeatureR600ALUInst ] ) && ( ( Desc . TSFlags & R600_InstFlag :: OP1 ) || Desc . TSFlags & R600_InstFlag :: OP2 ) ) { uint64_t ISAOpCode = Inst & ( 0x3FFULL << 39 ) ; Inst &= ~ ( 0x3FFULL << 39 ) ; Inst |= ISAOpCode << 1 ; } Emit ( Inst , OS ) ; } } </s>

Encode the given Inst to bytes and append to CB .


<s> int m32c_extra_address_constraint ( char c , const char * str ATTRIBUTE_UNUSED ) { return c == 'A' ; } </s>

Implements EXTRA_ADDRESS_CONSTRAINT . We reserve ' A ' strings for these , but do n't currently define any .


<s> static bool isAbsolute ( SDValue CmpOp , SDValue Pos , SDValue Neg ) { return ( Neg . getOpcode ( ) == ISD :: SUB && Neg . getOperand ( 0 ) . getOpcode ( ) == ISD :: Constant && cast < ConstantSDNode > ( Neg . getOperand ( 0 ) ) -> getZExtValue ( ) == 0 && Neg . getOperand ( 1 ) == Pos && ( Pos == CmpOp || ( Pos . getOpcode ( ) == ISD :: SIGN_EXTEND && Pos . getOperand ( 0 ) == CmpOp ) ) ) ; } </s>

Is this an absolute ( as opposed to relocatable ) value .


<s> static bool aarch64_hard_regno_mode_ok ( unsigned regno , machine_mode mode ) { if ( GET_MODE_CLASS ( mode ) == MODE_CC ) return regno == CC_REGNUM ; if ( regno == VG_REGNUM ) return mode == DImode ; unsigned int vec_flags = aarch64_classify_vector_mode ( mode ) ; if ( vec_flags & VEC_SVE_PRED ) return PR_REGNUM_P ( regno ) ; if ( PR_REGNUM_P ( regno ) ) return 0 ; if ( regno == SP_REGNUM ) return mode == Pmode || mode == ptr_mode ; if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return mode == Pmode ; if ( GP_REGNUM_P ( regno ) && known_le ( GET_MODE_SIZE ( mode ) , 16 ) ) return true ; if ( FP_REGNUM_P ( regno ) ) { if ( vec_flags & VEC_STRUCT ) return end_hard_regno ( mode , regno ) - 1 <= V31_REGNUM ; else return ! VECTOR_MODE_P ( mode ) || vec_flags != 0 ; } return false ; } </s>


<s> int getExtendResourceLenLimit ( ) const override { return 1 ; } </s>

The limit on resource length extension we accept in MachineCombiner Pass .


<s>
NVPTXSubtarget
::
NVPTXSubtarget
(
const
std
::
string
&
TT
,
const
std
::
string
&
CPU
,
const
std
::
string
&
FS
,
bool
is64Bit
)
:
NVPTXGenSubtargetInfo
(
TT
,
CPU
,
FS
)
,
Is64Bit
(
is64Bit
)
,
PTXVersion
(
0
)
,
SmVersion
(
10
)
{
drvInterface
=
DriverInterface
;
std
::
string
defCPU
=
"sm_10"
;
ParseSubtargetFeatures
(
(
CPU
.
empty
(
)
defCPU
:
CPU
)
,
FS
)
;
if
(
FS
.
empty
(
)
&&
CPU
.
empty
(
)
)
TargetName
=
defCPU
;
else
if
(
!
CPU
.
empty
(
)
)
TargetName
=
CPU
;
else
llvm_unreachable
(
"we are not using FeatureStr"
)
;
if
(
PTXVersion
==
0
)
{
PTXVersion
=
31
;
}
}
</s>

This constructor initializes the data members to match that of the specified module .


<s> bool rvexPassConfig :: addPreEmitPass ( ) { if ( static_cast < rvexTargetMachine * > ( TM ) -> getSubtargetImpl ( ) -> isVLIWEnabled ( ) ) { addPass ( creatervexVLIWPacketizer ( ) ) ; } return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


"Peephole: call to builtin function with "

runOnMachineFunction - Emit the function body .


<s> bool AArch64InstrInfo :: isExtendLikelyToBeFolded ( MachineInstr & ExtMI , MachineRegisterInfo & MRI ) const { assert ( ExtMI . getOpcode ( ) == TargetOpcode :: G_SEXT || ExtMI . getOpcode ( ) == TargetOpcode :: G_ZEXT || ExtMI . getOpcode ( ) == TargetOpcode :: G_ANYEXT ) ; if ( ExtMI . getOpcode ( ) == TargetOpcode :: G_ANYEXT ) return true ; Register DefReg = ExtMI . getOperand ( 0 ) . getReg ( ) ; if ( ! MRI . hasOneNonDBGUse ( DefReg ) ) return false ; auto * UserMI = & * MRI . use_instr_nodbg_begin ( DefReg ) ; return UserMI -> getOpcode ( ) == TargetOpcode :: G_PTR_ADD ; } </s>

Given the generic extension instruction ExtMI , returns true if this extension is a likely candidate for being folded into an another instruction .


<s> bool MipsTargetLowering :: hasBitTest ( SDValue X , SDValue Y ) const { if ( auto * C = dyn_cast < ConstantSDNode > ( Y ) ) return C -> getAPIntValue ( ) . ule ( 15 ) ; return false ; } </s>

Return true if the target has a bit-test instruction : ( X & ( 1 < < Y ) ) ==/ ! = 0 This knowledge can be used to prevent breaking the pattern , or creating it if it could be recognized .


<s> bool Cpu0AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


"should only be seeing frame offset relative FrameIndex"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> RegisterSet & remove ( const RegisterSet & Rs ) { for ( unsigned R = Rs . find_first ( ) ; R ; R = Rs . find_next ( R ) ) remove ( R ) ; return * this ; } </s>

remove - Remove the specified key/value pair from the map , but do not erase it .


<s> void AMDGPUTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , APInt & KnownZero , APInt & KnownOne , const SelectionDAG & DAG , unsigned Depth ) const { KnownZero = KnownOne = APInt ( KnownOne . getBitWidth ( ) , 0 ) ; APInt KnownZero2 ; APInt KnownOne2 ; unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { default : break ; case ISD :: INTRINSIC_WO_CHAIN : { switch ( cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ) { case AMDGPUIntrinsic :: AMDGPU_imax : case AMDGPUIntrinsic :: AMDGPU_umax : case AMDGPUIntrinsic :: AMDGPU_imin : case AMDGPUIntrinsic :: AMDGPU_umin : computeKnownBitsForMinMax ( Op . getOperand ( 1 ) , Op . getOperand ( 2 ) , KnownZero , KnownOne , DAG , Depth ) ; break ; default : break ; } break ; } case AMDGPUISD :: SMAX : case AMDGPUISD :: UMAX : case AMDGPUISD :: SMIN : case AMDGPUISD :: UMIN : computeKnownBitsForMinMax ( Op . getOperand ( 0 ) , Op . getOperand ( 1 ) , KnownZero , KnownOne , DAG , Depth ) ; break ; case AMDGPUISD :: BFE_I32 : case AMDGPUISD :: BFE_U32 : { ConstantSDNode * CWidth = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ; if ( ! CWidth ) return ; unsigned BitWidth = 32 ; uint32_t Width = CWidth -> getZExtValue ( ) & 0x1f ; if ( Width == 0 ) { KnownZero = APInt :: getAllOnesValue ( BitWidth ) ; KnownOne = APInt :: getNullValue ( BitWidth ) ; return ; } if ( Opc == AMDGPUISD :: BFE_I32 ) KnownOne = APInt :: getHighBitsSet ( BitWidth , BitWidth - Width ) ; else KnownZero = APInt :: getHighBitsSet ( BitWidth , BitWidth - Width ) ; break ; } } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> static int ix86_get_modrm_for_rop ( rtx_insn * insn , rtx * operands , int noperands , int * popno0 = 0 , int * popno1 = 0 ) { if ( asm_noperands ( PATTERN ( insn ) ) >= 0 ) return - 1 ; int has_modrm = get_attr_modrm ( insn ) ; if ( ! has_modrm ) return - 1 ; enum attr_modrm_class cls = get_attr_modrm_class ( insn ) ; rtx op0 , op1 ; switch ( cls ) { case MODRM_CLASS_OP02 : gcc_assert ( noperands >= 3 ) ; if ( popno0 ) { * popno0 = 0 ; * popno1 = 2 ; } op0 = operands [ 0 ] ; op1 = operands [ 2 ] ; break ; case MODRM_CLASS_OP01 : gcc_assert ( noperands >= 2 ) ; if ( popno0 ) { * popno0 = 0 ; * popno1 = 1 ; } op0 = operands [ 0 ] ; op1 = operands [ 1 ] ; break ; default : return - 1 ; } if ( REG_P ( op0 ) && REG_P ( op1 ) ) { int enc0 = reg_encoded_number ( op0 ) ; int enc1 = reg_encoded_number ( op1 ) ; return 0xc0 + ( enc1 << 3 ) + enc0 ; } return - 1 ; } </s>

Given an insn INSN with NOPERANDS OPERANDS , return the modr/m byte used in its encoding if it could be relevant for ROP mitigation , otherwise return -1 . If POPNO0 and POPNO1 are nonnull , store the operand numbers used for calculating it into them .


<s> unsigned VideoCore4RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return VideoCore4 :: SP ; } </s>


<s> bool R600InstrInfo :: PredicateInstruction ( MachineInstr * MI , ArrayRef < MachineOperand > Pred ) const { int PIdx = MI -> findFirstPredOperandIdx ( ) ; if ( MI -> getOpcode ( ) == AMDGPU :: CF_ALU ) { MI -> getOperand ( 8 ) . setImm ( 0 ) ; return true ; } if ( MI -> getOpcode ( ) == AMDGPU :: DOT_4 ) { MI -> getOperand ( getOperandIdx ( * MI , AMDGPU :: OpName :: pred_sel_X ) ) . setReg ( Pred [ 2 ] . getReg ( ) ) ; MI -> getOperand ( getOperandIdx ( * MI , AMDGPU :: OpName :: pred_sel_Y ) ) . setReg ( Pred [ 2 ] . getReg ( ) ) ; MI -> getOperand ( getOperandIdx ( * MI , AMDGPU :: OpName :: pred_sel_Z ) ) . setReg ( Pred [ 2 ] . getReg ( ) ) ; MI -> getOperand ( getOperandIdx ( * MI , AMDGPU :: OpName :: pred_sel_W ) ) . setReg ( Pred [ 2 ] . getReg ( ) ) ; MachineInstrBuilder MIB ( * MI -> getParent ( ) -> getParent ( ) , MI ) ; MIB . addReg ( AMDGPU :: PREDICATE_BIT , RegState :: Implicit ) ; return true ; } if ( PIdx != - 1 ) { MachineOperand & PMO = MI -> getOperand ( PIdx ) ; PMO . setReg ( Pred [ 2 ] . getReg ( ) ) ; MachineInstrBuilder MIB ( * MI -> getParent ( ) -> getParent ( ) , MI ) ; MIB . addReg ( AMDGPU :: PREDICATE_BIT , RegState :: Implicit ) ; return true ; } return false ; } </s>

Convert the instruction into a predicated instruction .


"BPF DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> bool SIAnnotateControlFlow :: doInitialization ( Module & M ) { LLVMContext & Context = M . getContext ( ) ; Void = Type :: getVoidTy ( Context ) ; Boolean = Type :: getInt1Ty ( Context ) ; Int64 = Type :: getInt64Ty ( Context ) ; ReturnStruct = StructType :: get ( Boolean , Int64 , ( Type * ) nullptr ) ; BoolTrue = ConstantInt :: getTrue ( Context ) ; BoolFalse = ConstantInt :: getFalse ( Context ) ; BoolUndef = UndefValue :: get ( Boolean ) ; Int64Zero = ConstantInt :: get ( Int64 , 0 ) ; If = M . getOrInsertFunction ( IfIntrinsic , ReturnStruct , Boolean , ( Type * ) nullptr ) ; Else = M . getOrInsertFunction ( ElseIntrinsic , ReturnStruct , Int64 , ( Type * ) nullptr ) ; Break = M . getOrInsertFunction ( BreakIntrinsic , Int64 , Int64 , ( Type * ) nullptr ) ; cast < Function > ( Break ) -> setDoesNotAccessMemory ( ) ; IfBreak = M . getOrInsertFunction ( IfBreakIntrinsic , Int64 , Boolean , Int64 , ( Type * ) nullptr ) ; cast < Function > ( IfBreak ) -> setDoesNotAccessMemory ( ) ; ; ElseBreak = M . getOrInsertFunction ( ElseBreakIntrinsic , Int64 , Int64 , Int64 , ( Type * ) nullptr ) ; cast < Function > ( ElseBreak ) -> setDoesNotAccessMemory ( ) ; Loop = M . getOrInsertFunction ( LoopIntrinsic , Boolean , Int64 , ( Type * ) nullptr ) ; EndCf = M . getOrInsertFunction ( EndCfIntrinsic , Void , Int64 , ( Type * ) nullptr ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> static bool s390_can_inline_p ( tree caller , tree callee ) { const unsigned HOST_WIDE_INT caller_required_masks = MASK_OPT_HTM ; unsigned HOST_WIDE_INT must_match_masks = ( MASK_64BIT | MASK_ZARCH | MASK_HARD_DFP | MASK_SOFT_FLOAT | MASK_LONG_DOUBLE_128 | MASK_OPT_VX ) ; const unsigned HOST_WIDE_INT always_inline_safe_masks = MASK_MVCLE | MASK_BACKCHAIN | MASK_SMALL_EXEC ; const HOST_WIDE_INT all_masks = ( caller_required_masks | must_match_masks | always_inline_safe_masks | MASK_DEBUG_ARG | MASK_PACKED_STACK | MASK_ZVECTOR ) ; tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET ( caller ) ; tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET ( callee ) ; if ( ! callee_tree ) callee_tree = target_option_default_node ; if ( ! caller_tree ) caller_tree = target_option_default_node ; if ( callee_tree == caller_tree ) return true ; struct cl_target_option * caller_opts = TREE_TARGET_OPTION ( caller_tree ) ; struct cl_target_option * callee_opts = TREE_TARGET_OPTION ( callee_tree ) ; gcc_assert ( ! ( caller_opts -> x_target_flags & ~ all_masks ) ) ; gcc_assert ( ! ( callee_opts -> x_target_flags & ~ all_masks ) ) ; bool always_inline = ( DECL_DISREGARD_INLINE_LIMITS ( callee ) && lookup_attribute ( "always_inline" , DECL_ATTRIBUTES ( callee ) ) ) ; if ( ! always_inline ) must_match_masks |= always_inline_safe_masks ; if ( always_inline && ipa_fn_summaries && ! ipa_fn_summaries -> get ( cgraph_node :: get ( callee ) ) -> fp_expressions ) must_match_masks &= ~ ( MASK_HARD_DFP | MASK_SOFT_FLOAT ) ; if ( ( caller_opts -> x_target_flags & must_match_masks ) != ( callee_opts -> x_target_flags & must_match_masks ) ) return false ; if ( ~ ( caller_opts -> x_target_flags & caller_required_masks ) & ( callee_opts -> x_target_flags & caller_required_masks ) ) return false ; if ( caller_opts -> x_s390_arch < callee_opts -> x_s390_arch ) return false ; if ( ! always_inline && caller_opts -> x_s390_tune != callee_opts -> x_s390_tune ) return false ; return true ; } </s>

Hook to determine if one function can safely inline another .


<s>
SDNode
*
MipsDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
return
;
}
std
::
pair
<
bool
,
SDNode
*
>
Ret
=
selectNode
(
Node
)
;
if
(
Ret
.
first
)
return
Ret
.
second
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
return
getGlobalBaseReg
(
)
;
case
ISD
::
LOAD
:
case
ISD
::
STORE
:
assert
(
cast
<
MemSDNode
>
(
Node
)
->
getMemoryVT
(
)
.
getSizeInBits
(
)
/
8
<=
cast
<
MemSDNode
>
(
Node
)
->
getAlignment
(
)
&&
"Unexpected unaligned loads/stores."
)
;
break
;
}
SDNode
*
ResNode
=
SelectCode
(
Node
)
;
DEBUG
(
errs
(
)
<<
"=> "
)
;
if
(
ResNode
==
||
ResNode
==
Node
)
DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
else
DEBUG
(
ResNode
->
dump
(
CurDAG
)
)
;
DEBUG
(
errs
(
)
<<
"\n"
)
;
return
ResNode
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

Mips
Mips
"Selecting: "
"\n"
"== "
"\n"
ISD::GLOBAL_OFFSET_TABLE
ISD::LOAD
ISD::STORE
8
"Unexpected unaligned loads/stores."
"=> "
"\n"


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( Fixup , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { case FK_Data_2 : case Mips :: fixup_Mips_16 : FullSize = 2 ; break ; case FK_Data_8 : case Mips :: fixup_Mips_64 : FullSize = 8 ; break ; case FK_Data_4 : default : FullSize = 4 ; break ; } uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - 1 - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> Value * X86TargetLowering :: getSSPStackGuardCheck ( const Module & M ) const { if ( Subtarget . getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) || Subtarget . getTargetTriple ( ) . isWindowsItaniumEnvironment ( ) ) { return M . getFunction ( "__security_check_cookie" ) ; } return TargetLowering :: getSSPStackGuardCheck ( M ) ; } </s>

If the target has a standard stack protection check function that performs validation and error handling , returns the function .


<s>
static
void
rs6000_debug_reg_print
(
int
first_regno
,
int
last_regno
,
const
char
*
reg_name
)
{
int
r
,
m
;
for
(
r
=
first_regno
;
r
<=
last_regno
;
++
r
)
{
const
char
*
comma
=
""
;
int
len
;
if
(
first_regno
==
last_regno
)
fprintf
(
stderr
,
"%s:\t"
,
reg_name
)
;
else
fprintf
(
stderr
,
"%s%d:\t"
,
reg_name
,
r
first_regno
)
;
len
=
8
;
for
(
m
=
0
;
m
<
NUM_MACHINE_MODES
;
++
m
)
if
(
rs6000_hard_regno_mode_ok_p
[
m
]
[
r
]
&&
rs6000_hard_regno_nregs
[
m
]
[
r
]
)
{
if
(
len
>
70
)
{
fprintf
(
stderr
,
",\n\t"
)
;
len
=
8
;
comma
=
""
;
}
if
(
rs6000_hard_regno_nregs
[
m
]
[
r
]
>
1
)
len
+=
fprintf
(
stderr
,
"%s%s/%d"
,
comma
,
GET_MODE_NAME
(
m
)
,
rs6000_hard_regno_nregs
[
m
]
[
r
]
)
;
else
len
+=
fprintf
(
stderr
,
"%s%s"
,
comma
,
GET_MODE_NAME
(
m
)
)
;
comma
=
", "
;
}
if
(
call_used_regs
[
r
]
)
{
if
(
len
>
70
)
{
fprintf
(
stderr
,
",\n\t"
)
;
len
=
8
;
comma
=
""
;
}
len
+=
fprintf
(
stderr
,
"%s%s"
,
comma
,
"call-used"
)
;
comma
=
", "
;
}
if
(
fixed_regs
[
r
]
)
{
if
(
len
>
70
)
{
fprintf
(
stderr
,
",\n\t"
)
;
len
=
8
;
comma
=
""
;
}
len
+=
fprintf
(
stderr
,
"%s%s"
,
comma
,
"fixed"
)
;
comma
=
", "
;
}
if
(
len
>
70
)
{
fprintf
(
stderr
,
",\n\t"
)
;
comma
=
""
;
}
len
+=
fprintf
(
stderr
,
"%sreg-class = %s"
,
comma
,
reg_class_names
[
(
int
)
rs6000_regno_regclass
[
r
]
]
)
;
comma
=
", "
;
if
(
len
>
70
)
{
fprintf
(
stderr
,
",\n\t"
)
;
comma
=
""
;
}
fprintf
(
stderr
,
"%sregno = %d\n"
,
comma
,
r
)
;
}
}
</s>

Print interesting facts about registers .


<s> void LM32TargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s> static std :: unique_ptr < AMDGPUOperand > CreateReg ( unsigned RegNo , SMLoc S , SMLoc E , const MCRegisterInfo * TRI , const MCSubtargetInfo * STI , bool ForceVOP3 ) { auto Op = llvm :: make_unique < AMDGPUOperand > ( Register ) ; Op -> Reg . RegNo = RegNo ; Op -> Reg . TRI = TRI ; Op -> Reg . STI = STI ; Op -> Reg . Modifiers = 0 ; Op -> Reg . IsForcedVOP3 = ForceVOP3 ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> unsigned ARMTargetLowering :: getMaxSupportedInterleaveFactor ( ) const { if ( Subtarget -> hasNEON ( ) ) return 4 ; if ( Subtarget -> hasMVEIntegerOps ( ) ) return MVEMaxSupportedInterleaveFactor ; return TargetLoweringBase :: getMaxSupportedInterleaveFactor ( ) ; } </s>

Get the maximum supported factor for interleaved memory accesses .


<s> TargetLowering :: AtomicExpansionKind HexagonTargetLowering :: shouldExpandAtomicStoreInIR ( StoreInst * SI ) const { return SI -> getValueOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) > 64 ? AtomicExpansionKind :: Expand : AtomicExpansionKind :: None ; } </s>

Returns how the given ( atomic ) store should be expanded by the IR-level AtomicExpand pass into .