<s> virtual const DataLayout * getDataLayout ( ) const { return & DL ; } </s>


<s> static int arm_cpymemqi_unaligned ( rtx * operands ) { HOST_WIDE_INT length = INTVAL ( operands [ 2 ] ) ; if ( optimize_size ) { bool src_aligned = MEM_ALIGN ( operands [ 1 ] ) >= BITS_PER_WORD ; bool dst_aligned = MEM_ALIGN ( operands [ 0 ] ) >= BITS_PER_WORD ; unsigned int interleave_factor = ( src_aligned || dst_aligned ) ? 2 : 1 ; HOST_WIDE_INT bytes_per_iter = ( src_aligned || dst_aligned ) ? 8 : 4 ; if ( length > 12 ) arm_block_move_unaligned_loop ( operands [ 0 ] , operands [ 1 ] , length , interleave_factor , bytes_per_iter ) ; else arm_block_move_unaligned_straight ( operands [ 0 ] , operands [ 1 ] , length , interleave_factor ) ; } else { if ( length > 32 ) arm_block_move_unaligned_loop ( operands [ 0 ] , operands [ 1 ] , length , 4 , 16 ) ; else arm_block_move_unaligned_straight ( operands [ 0 ] , operands [ 1 ] , length , 4 ) ; } return 1 ; } </s>

Emit a block move when either the source or destination is unaligned ( not aligned to a four-byte boundary ) . This may need further tuning depending on core type , optimize_size setting , etc .


<s> unsigned SystemZInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case SystemZ :: MOV32mr : case SystemZ :: MOV32mry : case SystemZ :: MOV64mr : case SystemZ :: MOV32m8r : case SystemZ :: MOV32m8ry : case SystemZ :: MOV32m16r : case SystemZ :: MOV32m16ry : case SystemZ :: MOV64m8r : case SystemZ :: MOV64m8ry : case SystemZ :: MOV64m16r : case SystemZ :: MOV64m16ry : case SystemZ :: MOV64m32r : case SystemZ :: MOV64m32ry : case SystemZ :: FMOV32mr : case SystemZ :: FMOV32mry : case SystemZ :: FMOV64mr : case SystemZ :: FMOV64mry : case SystemZ :: MOV64Pmr : case SystemZ :: MOV64Pmry : case SystemZ :: MOV128mr : if ( MI -> getOperand ( 0 ) . isFI ( ) && MI -> getOperand ( 1 ) . isImm ( ) && MI -> getOperand ( 2 ) . isReg ( ) && MI -> getOperand ( 1 ) . getImm ( ) == 0 && MI -> getOperand ( 2 ) . getReg ( ) == 0 ) { FrameIndex = MI -> getOperand ( 0 ) . getIndex ( ) ; return MI -> getOperand ( 3 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s>
void
dump
(
)
{
errs
(
)
<<
"TLCS900ISelAddressMode "
<<
this
<<
'\n'
;
if
(
BaseType
==
RegBase
&&
Base
.
Reg
.
getNode
(
)
!=
0
)
{
errs
(
)
<<
"Base.Reg "
;
Base
.
Reg
.
getNode
(
)
->
dump
(
)
;
}
else
if
(
BaseType
==
FrameIndexBase
)
{
errs
(
)
<<
" Base.FrameIndex "
<<
Base
.
FrameIndex
<<
'\n'
;
}
errs
(
)
<<
" Disp "
<<
Disp
<<
'\n'
;
if
(
GV
)
{
errs
(
)
<<
"GV "
;
GV
->
dump
(
)
;
}
else
if
(
CP
)
{
errs
(
)
<<
" CP "
;
CP
->
dump
(
)
;
errs
(
)
<<
" Align"
<<
Align
<<
'\n'
;
}
else
if
(
ES
)
{
errs
(
)
<<
"ES "
;
errs
(
)
<<
ES
<<
'\n'
;
}
else
if
(
JT
!=
1
)
errs
(
)
<<
" JT"
<<
JT
<<
" Align"
<<
Align
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

TLCS900
"TLCS900ISelAddressMode "
0
"Base.Reg "
" Base.FrameIndex "
" Disp "
"GV "
" CP "
" Align"
"ES "
1
" JT"
" Align"


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == 0 ) Inst . addOperand ( MCOperand :: CreateImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ; } </s>


<s> bool X86TargetLowering :: isSplatValueForTargetNode ( SDValue Op , const APInt & DemandedElts , APInt & UndefElts , unsigned Depth ) const { unsigned NumElts = DemandedElts . getBitWidth ( ) ; unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { case X86ISD :: VBROADCAST : case X86ISD :: VBROADCAST_LOAD : if ( isTypeLegal ( Op . getValueType ( ) . getVectorElementType ( ) ) ) { UndefElts = APInt :: getNullValue ( NumElts ) ; return true ; } return false ; } return TargetLowering :: isSplatValueForTargetNode ( Op , DemandedElts , UndefElts , Depth ) ; } </s>

Return true if vector Op has the same value across all DemandedElts , indicating any elements which may be undef in the output UndefElts .


<s> int AMDGPUInstrInfo :: pseudoToMCOpcode ( int Opcode ) const { SIEncodingFamily Gen = subtargetEncodingFamily ( ST ) ; if ( ( get ( Opcode ) . TSFlags & SIInstrFlags :: renamedInGFX9 ) != 0 && ST . getGeneration ( ) >= AMDGPUSubtarget :: GFX9 ) Gen = SIEncodingFamily :: GFX9 ; if ( get ( Opcode ) . TSFlags & SIInstrFlags :: SDWA ) Gen = ST . getGeneration ( ) == AMDGPUSubtarget :: GFX9 ? SIEncodingFamily :: SDWA9 : SIEncodingFamily :: SDWA ; if ( ST . hasUnpackedD16VMem ( ) && ( get ( Opcode ) . TSFlags & SIInstrFlags :: D16 ) && ! ( get ( Opcode ) . TSFlags & SIInstrFlags :: MIMG ) ) Gen = SIEncodingFamily :: GFX80 ; int MCOp = AMDGPU :: getMCOpcode ( Opcode , Gen ) ; if ( MCOp == - 1 ) return Opcode ; if ( MCOp == ( uint16_t ) - 1 ) return - 1 ; return MCOp ; } </s>

Return a target-specific opcode if Opcode is a pseudo instruction .


<s> static void alpha_sa_mask ( unsigned long * imaskP , unsigned long * fmaskP ) { unsigned long imask = 0 ; unsigned long fmask = 0 ; unsigned int i ; if ( current_function_is_thunk ) { * imaskP = 0 ; * fmaskP = 0 ; return ; } if ( TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK ) imask |= ( 1UL << HARD_FRAME_POINTER_REGNUM ) ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( ! fixed_regs [ i ] && ! call_used_regs [ i ] && regs_ever_live [ i ] && i != REG_RA && ( ! TARGET_ABI_UNICOSMK || i != HARD_FRAME_POINTER_REGNUM ) ) { if ( i < 32 ) imask |= ( 1UL << i ) ; else fmask |= ( 1UL << ( i - 32 ) ) ; } if ( current_function_calls_eh_return ) { for ( i = 0 ; ; ++ i ) { unsigned regno = EH_RETURN_DATA_REGNO ( i ) ; if ( regno == INVALID_REGNUM ) break ; imask |= 1UL << regno ; } } if ( imask || fmask || alpha_ra_ever_killed ( ) ) imask |= ( 1UL << REG_RA ) ; * imaskP = imask ; * fmaskP = fmask ; } </s>

Compute register masks for saved registers .


<s> const char * nvptx_section_from_addr_space ( addr_space_t as ) { switch ( as ) { case ADDR_SPACE_CONST : return ".const" ; case ADDR_SPACE_GLOBAL : return ".global" ; case ADDR_SPACE_SHARED : return ".shared" ; case ADDR_SPACE_GENERIC : return "" ; default : gcc_unreachable ( ) ; } } </s>

Convert an address space AS to the corresponding ptx string .


<s> X86GenInstrInfo :: MachineOutlinerInstrType X86InstrInfo :: getOutliningType ( MachineBasicBlock :: iterator & MIT , unsigned Flags ) const { MachineInstr & MI = * MIT ; if ( MI . isDebugInstr ( ) || MI . isIndirectDebugValue ( ) ) return MachineOutlinerInstrType :: Invisible ; if ( MI . isKill ( ) ) return MachineOutlinerInstrType :: Invisible ; if ( isTailCall ( MI ) ) return MachineOutlinerInstrType :: Legal ; if ( MI . isTerminator ( ) || MI . isReturn ( ) ) { if ( MI . getParent ( ) -> succ_empty ( ) ) return MachineOutlinerInstrType :: Legal ; return MachineOutlinerInstrType :: Illegal ; } if ( MI . modifiesRegister ( X86 :: RSP , & RI ) || MI . readsRegister ( X86 :: RSP , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( X86 :: RSP ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( X86 :: RSP ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . readsRegister ( X86 :: RIP , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( X86 :: RIP ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( X86 :: RIP ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . isPosition ( ) ) return MachineOutlinerInstrType :: Illegal ; for ( const MachineOperand & MOP : MI . operands ( ) ) if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return MachineOutlinerInstrType :: Illegal ; return MachineOutlinerInstrType :: Legal ; } </s>

Returns how or if MIT should be outlined .


<s> TargetLowering :: ConstraintType RISCVTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'a' : case 'd' : case 'f' : case 'r' : return C_RegisterClass ; case 'Q' : case 'R' : case 'S' : case 'T' : case 'm' : return C_Memory ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : return C_Other ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> TargetPassConfig * TriCoreTargetMachine :: createPassConfig ( legacy :: PassManagerBase & PM ) { return new TriCorePassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


"No offset range is defined for this opcode. "

"Please define it in the above switch statement!"


<s> inline bool vgpr_2reg_mode_p ( machine_mode mode ) { if ( VECTOR_MODE_P ( mode ) ) mode = GET_MODE_INNER ( mode ) ; return ( mode == DImode || mode == DFmode ) ; } </s>

Return true if MODE is valid for pair of VGPR registers .


"ISelDAG: Can't return aggregate types\n"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> const TargetRegisterClass * PPCRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const auto * DefaultSuperclass = TargetRegisterInfo :: getLargestLegalSuperClass ( RC , MF ) ; if ( Subtarget . hasVSX ( ) ) { if ( TM . isELFv2ABI ( ) || Subtarget . isAIXABI ( ) ) { if ( Subtarget . hasP9Vector ( ) && EnableGPRToVecSpills && RC == & PPC :: G8RCRegClass ) { InflateGP8RC ++ ; return & PPC :: SPILLTOVSRRCRegClass ; } if ( RC == & PPC :: GPRCRegClass && EnableGPRToVecSpills ) InflateGPRC ++ ; } for ( const auto * I = RC -> getSuperClasses ( ) ; * I ; ++ I ) { if ( getRegSizeInBits ( * * I ) != getRegSizeInBits ( * RC ) ) continue ; switch ( ( * I ) -> getID ( ) ) { case PPC :: VSSRCRegClassID : return Subtarget . hasP8Vector ( ) ? * I : DefaultSuperclass ; case PPC :: VSFRCRegClassID : case PPC :: VSRCRegClassID : return * I ; case PPC :: VSRpRCRegClassID : return Subtarget . pairedVectorMemops ( ) ? * I : DefaultSuperclass ; case PPC :: ACCRCRegClassID : case PPC :: UACCRCRegClassID : return Subtarget . hasMMA ( ) ? * I : DefaultSuperclass ; } } } return DefaultSuperclass ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .

PowerPC PPC PPC PPC PPC::G8RCRegClass PPC::SPILLTOVSRRCRegClass PPC::GPRCRegClass PPC::VSSRCRegClassID PPC::VSFRCRegClassID PPC::VSRCRegClassID PPC::VSRpRCRegClassID PPC::ACCRCRegClassID PPC::UACCRCRegClassID


<s> void assignValueToAddress ( const CallLowering :: ArgInfo & Arg , Register Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { unsigned MaxSize = Size * 8 ; if ( ! Arg . IsFixed ) MaxSize = 0 ; assert ( Arg . Regs . size ( ) == 1 ) ; Register ValVReg = VA . getLocInfo ( ) != CCValAssign :: LocInfo :: FPExt ? extendRegister ( Arg . Regs [ 0 ] , VA , MaxSize ) : Arg . Regs [ 0 ] ; const LLT RegTy = MRI . getType ( ValVReg ) ; if ( RegTy . getSizeInBytes ( ) > Size ) Size = RegTy . getSizeInBytes ( ) ; assignValueToAddress ( ValVReg , Addr , Size , MPO , VA ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


"static IO declaration for %q+D needs an address"


<s> bool RISCVAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { MCSubtargetInfo & NewSTI = OutStreamer -> getContext ( ) . getSubtargetCopy ( * TM . getMCSubtargetInfo ( ) ) ; NewSTI . setFeatureBits ( MF . getSubtarget ( ) . getFeatureBits ( ) ) ; STI = & NewSTI ; SetupMachineFunction ( MF ) ; emitFunctionBody ( ) ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool X86AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : break ; case 'P' : printMemReference ( MI , OpNo , O , "no-rip" ) ; return false ; } } printMemReference ( MI , OpNo , O ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s>
void
X86DAGToDAGISel
::
PreprocessISelDAG
(
)
{
OptForSize
=
MF
->
getFunction
(
)
.
optForSize
(
)
;
OptForMinSize
=
MF
->
getFunction
(
)
.
optForMinSize
(
)
;
assert
(
(
!
OptForMinSize
||
OptForSize
)
&&
"OptForMinSize implies OptForSize"
)
;
for
(
SelectionDAG
::
allnodes_iterator
I
=
CurDAG
->
allnodes_begin
(
)
,
E
=
CurDAG
->
allnodes_end
(
)
;
I
!=
E
;
)
{
SDNode
*
N
=
&
*
I
++
;
if
(
OptLevel
!=
CodeGenOpt
::
&&
(
(
N
->
getOpcode
(
)
==
X86ISD
::
CALL
&&
!
Subtarget
->
slowTwoMemOps
(
)
)
||
(
N
->
getOpcode
(
)
==
X86ISD
::
TC_RETURN
&&
(
Subtarget
->
is64Bit
(
)
||
!
getTargetMachine
(
)
.
isPositionIndependent
(
)
)
)
)
)
{
bool
HasCallSeq
=
N
->
getOpcode
(
)
==
X86ISD
::
CALL
;
SDValue
Chain
=
N
->
getOperand
(
0
)
;
SDValue
Load
=
N
->
getOperand
(
1
)
;
if
(
!
isCalleeLoad
(
Load
,
Chain
,
HasCallSeq
)
)
continue
;
moveBelowOrigChain
(
CurDAG
,
Load
,
SDValue
(
N
,
0
)
,
Chain
)
;
++
NumLoadMoved
;
continue
;
}
if
(
N
->
getOpcode
(
)
!=
ISD
::
FP_ROUND
&&
N
->
getOpcode
(
)
!=
ISD
::
FP_EXTEND
)
continue
;
MVT
SrcVT
=
N
->
getOperand
(
0
)
.
getSimpleValueType
(
)
;
MVT
DstVT
=
N
->
getSimpleValueType
(
0
)
;
if
(
SrcVT
.
isVector
(
)
||
DstVT
.
isVector
(
)
)
continue
;
const
X86TargetLowering
*
X86Lowering
=
static_cast
<
const
X86TargetLowering
*
>
(
TLI
)
;
bool
SrcIsSSE
=
X86Lowering
->
isScalarFPTypeInSSEReg
(
SrcVT
)
;
bool
DstIsSSE
=
X86Lowering
->
isScalarFPTypeInSSEReg
(
DstVT
)
;
if
(
SrcIsSSE
&&
DstIsSSE
)
continue
;
if
(
!
SrcIsSSE
&&
!
DstIsSSE
)
{
if
(
N
->
getOpcode
(
)
==
ISD
::
FP_EXTEND
)
continue
;
if
(
N
->
getConstantOperandVal
(
1
)
)
continue
;
}
MVT
MemVT
;
if
(
N
->
getOpcode
(
)
==
ISD
::
FP_ROUND
)
MemVT
=
DstVT
;
else
MemVT
=
SrcIsSSE
SrcVT
:
DstVT
;
SDValue
MemTmp
=
CurDAG
->
CreateStackTemporary
(
MemVT
)
;
SDLoc
dl
(
N
)
;
SDValue
Store
=
CurDAG
->
getTruncStore
(
CurDAG
->
getEntryNode
(
)
,
dl
,
N
->
getOperand
(
0
)
,
MemTmp
,
MachinePointerInfo
(
)
,
MemVT
)
;
SDValue
Result
=
CurDAG
->
getExtLoad
(
ISD
::
EXTLOAD
,
dl
,
DstVT
,
Store
,
MemTmp
,
MachinePointerInfo
(
)
,
MemVT
)
;
I
;
CurDAG
->
ReplaceAllUsesOfValueWith
(
SDValue
(
N
,
0
)
,
Result
)
;
++
I
;
CurDAG
->
DeleteNode
(
N
)
;
}
}
</s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> virtual const AZPRRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static tree ix86_stack_protect_guard ( void ) { if ( TARGET_SSP_TLS_GUARD ) { tree type_node = lang_hooks . types . type_for_mode ( ptr_mode , 1 ) ; int qual = ENCODE_QUAL_ADDR_SPACE ( ix86_stack_protector_guard_reg ) ; tree type = build_qualified_type ( type_node , qual ) ; tree t ; if ( global_options_set . x_ix86_stack_protector_guard_symbol_str ) { t = ix86_tls_stack_chk_guard_decl ; if ( t == NULL ) { rtx x ; t = build_decl ( UNKNOWN_LOCATION , VAR_DECL , get_identifier ( ix86_stack_protector_guard_symbol_str ) , type ) ; TREE_STATIC ( t ) = 1 ; TREE_PUBLIC ( t ) = 1 ; DECL_EXTERNAL ( t ) = 1 ; TREE_USED ( t ) = 1 ; TREE_THIS_VOLATILE ( t ) = 1 ; DECL_ARTIFICIAL ( t ) = 1 ; DECL_IGNORED_P ( t ) = 1 ; x = DECL_RTL ( t ) ; RTX_FLAG ( x , used ) = 1 ; ix86_tls_stack_chk_guard_decl = t ; } } else { tree asptrtype = build_pointer_type ( type ) ; t = build_int_cst ( asptrtype , ix86_stack_protector_guard_offset ) ; t = build2 ( MEM_REF , asptrtype , t , build_int_cst ( asptrtype , 0 ) ) ; } return t ; } return default_stack_protect_guard ( ) ; } </s>

If using TLS guards , do n't waste time creating and expanding __stack_chk_guard decl and MEM as we are going to ignore it .


<s> bool M680x0FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { auto & MRI = * static_cast < const M680x0RegisterInfo * > ( TRI ) ; auto DL = MBB . findDebugLoc ( MI ) ; int FI = 0 ; unsigned Mask = 0 ; for ( size_t i = 0 ; i < CSI . size ( ) ; ++ i ) { FI = std :: max ( FI , CSI [ i ] . getFrameIdx ( ) ) ; unsigned Reg = CSI [ i ] . getReg ( ) ; unsigned Shift = MRI . getSpillRegisterOrder ( Reg ) ; Mask |= 1 << Shift ; } auto I = addFrameReference ( BuildMI ( MBB , MI , DL , TII . get ( M680x0 :: MOVM32mp ) ) . addImm ( Mask ) , FI ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; for ( size_t i = 0 ; i < CSI . size ( ) ; ++ i ) { I . addReg ( CSI [ i ] . getReg ( ) , RegState :: ImplicitDefine ) ; addMemOperand ( I , CSI [ i ] . getFrameIdx ( ) , 0 ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> void PPCTTIImpl :: getUnrollingPreferences ( Loop * L , TTI :: UnrollingPreferences & UP ) { if ( ST -> getDarwinDirective ( ) == PPC :: DIR_A2 ) { UP . Partial = UP . Runtime = true ; UP . AllowExpensiveTripCount = true ; } BaseT :: getUnrollingPreferences ( L , UP ) ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> static struct machine_function * epiphany_init_machine_status ( void ) { struct machine_function * machine ; current_frame_info = zero_frame_info ; machine = ggc_cleared_alloc < machine_function_t > ( ) ; return machine ; } </s>

The usual ; we set up our machine_function data .


"TL45 DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> bool ARMFrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { if ( STI . hasV8_1MMainlineOps ( ) && MF . getInfo < ARMFunctionInfo > ( ) -> isCmseNSEntryFunction ( ) ) { CSI . emplace_back ( ARM :: FPCXTNS ) ; CSI . back ( ) . setRestored ( false ) ; } return false ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> bool IA64TargetMachine :: addInstSelector ( PassManagerBase & PM , bool Fast ) { PM . add ( createIA64DAGToDAGInstructionSelector ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s>
static
const
char
*
rs6000_call_template_1
(
rtx
*
operands
,
unsigned
int
funop
,
bool
sibcall
)
{
gcc_assert
(
funop
<=
MAX_RECOG_OPERANDS
)
;
char
arg
[
12
]
;
arg
[
0
]
=
0
;
if
(
TARGET_TLS_MARKERS
&&
GET_CODE
(
operands
[
funop
+
1
]
)
==
UNSPEC
)
{
if
(
XINT
(
operands
[
funop
+
1
]
,
1
)
==
UNSPEC_TLSGD
)
sprintf
(
arg
,
"(%%%u@tlsgd)"
,
funop
+
1
)
;
else
if
(
XINT
(
operands
[
funop
+
1
]
,
1
)
==
UNSPEC_TLSLD
)
sprintf
(
arg
,
"(%%&@tlsld)"
)
;
else
gcc_unreachable
(
)
;
}
char
z
[
11
]
;
sprintf
(
z
,
"%%z%u%s"
,
funop
,
(
DEFAULT_ABI
==
ABI_V4
&&
TARGET_SECURE_PLT
&&
flag_pic
==
2
"+32768"
:
""
)
)
;
static
char
str
[
32
]
;
if
(
DEFAULT_ABI
==
ABI_AIX
||
DEFAULT_ABI
==
ABI_ELFv2
)
sprintf
(
str
,
"b%s %s%s%s"
,
sibcall
""
:
"l"
,
z
,
arg
,
sibcall
""
:
"\n\tnop"
)
;
else
if
(
DEFAULT_ABI
==
ABI_V4
)
sprintf
(
str
,
"b%s %s%s%s"
,
sibcall
""
:
"l"
,
z
,
arg
,
flag_pic
"@plt"
:
""
)
;
else
if
(
DEFAULT_ABI
==
ABI_DARWIN
)
{
gcc_checking_assert
(
GET_CODE
(
operands
[
funop
+
2
]
)
==
CONST_INT
)
;
int
cookie
=
INTVAL
(
operands
[
funop
+
2
]
)
;
if
(
cookie
&
CALL_LONG
)
{
tree
funname
=
get_identifier
(
XSTR
(
operands
[
funop
]
,
0
)
)
;
tree
labelname
=
get_prev_label
(
funname
)
;
gcc_checking_assert
(
labelname
&&
!
sibcall
)
;
sprintf
(
str
,
"jbsr %%z%u,%.10s"
,
funop
,
IDENTIFIER_POINTER
(
labelname
)
)
;
}
else
sprintf
(
str
,
"b%s %s%s"
,
sibcall
""
:
"l"
,
z
,
arg
)
;
}
else
gcc_unreachable
(
)
;
return
str
;
}
</s>

Return a template string for assembly to emit when making an external call . FUNOP is the call mem argument operand number .


<s> static inline int shiftcosts ( rtx x ) { int value ; if ( TARGET_SHMEDIA ) return 1 ; if ( GET_MODE_SIZE ( GET_MODE ( x ) ) > UNITS_PER_WORD ) { if ( GET_MODE ( x ) == DImode && CONST_INT_P ( XEXP ( x , 1 ) ) && INTVAL ( XEXP ( x , 1 ) ) == 1 ) return 2 ; return - 1 ; } if ( ! CONST_INT_P ( XEXP ( x , 1 ) ) ) return SH_DYNAMIC_SHIFT_COST ; value = INTVAL ( XEXP ( x , 1 ) ) & 31 ; if ( GET_CODE ( x ) == ASHIFTRT ) { int cost = ashiftrt_insns [ value ] ; if ( cost > 1 + SH_DYNAMIC_SHIFT_COST ) cost = 1 + SH_DYNAMIC_SHIFT_COST ; return cost ; } else return ashl_lshr_seq [ value ] . insn_count ; } </s>


<s> static int vax_return_pops_args ( tree fundecl ATTRIBUTE_UNUSED , tree funtype ATTRIBUTE_UNUSED , int size ) { return size > 255 * 4 ? 0 : size ; } </s>

Value is the number of bytes of arguments automatically popped when returning from a subroutine call . FUNDECL is the declaration node of the function ( as a tree ) , FUNTYPE is the data type of the function ( as a tree ) , or for a library call it is an identifier node for the subroutine name . SIZE is the number of bytes of arguments passed on the stack . On the VAX , the RET insn pops a maximum of 255 args for any function .


"constant argument %d for builtin %qF is out of range (0.."

"constant argument %d for builtin %qF is out of range ("

Return true if ARG is appropriate as argument number ARGNUM of builtin DECL . The operand flags from s390-builtins.def have to passed as OP_FLAGS .


<s> NVPTXSubtarget :: NVPTXSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool is64Bit ) : NVPTXGenSubtargetInfo ( TT , CPU , FS ) , Is64Bit ( is64Bit ) , PTXVersion ( 0 ) , SmVersion ( 20 ) , DL ( computeDataLayout ( is64Bit ) ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( ( NVPTXTargetMachine & ) TM ) , TSInfo ( & DL ) , FrameLowering ( * this ) { Triple T ( TT ) ; if ( T . getOS ( ) == Triple :: NVCL ) drvInterface = NVPTX :: NVCL ; else drvInterface = NVPTX :: CUDA ; } </s>

This constructor initializes the data members to match that of the specified module .

NVPTX NVPTX NVPTX NVPTX 0 20 NVPTX NVPTX::NVCL NVPTX::CUDA


<s> static void mips_expand_vi_broadcast ( machine_mode vmode , rtx target , rtx elt ) { struct expand_vec_perm_d d ; rtx t1 ; bool ok ; if ( elt != const0_rtx ) elt = force_reg ( GET_MODE_INNER ( vmode ) , elt ) ; if ( REG_P ( elt ) ) elt = gen_lowpart ( DImode , elt ) ; t1 = gen_reg_rtx ( vmode ) ; switch ( vmode ) { case V8QImode : emit_insn ( gen_loongson_vec_init1_v8qi ( t1 , elt ) ) ; break ; case V4HImode : emit_insn ( gen_loongson_vec_init1_v4hi ( t1 , elt ) ) ; break ; default : gcc_unreachable ( ) ; } memset ( & d , 0 , sizeof ( d ) ) ; d . target = target ; d . op0 = t1 ; d . op1 = t1 ; d . vmode = vmode ; d . nelt = GET_MODE_NUNITS ( vmode ) ; d . one_vector_p = true ; ok = mips_expand_vec_perm_const_1 ( & d ) ; gcc_assert ( ok ) ; } </s>

A subroutine of mips_expand_vec_init , expand via broadcast .


<s> unsigned ARMFastISel :: fastEmitInst_rr ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , unsigned Op1 ) { unsigned ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , 1 ) ; Op1 = constrainOperandRegClass ( II , Op1 , 2 ) ; if ( II . getNumDefs ( ) >= 1 ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 ) . addReg ( Op1 ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 ) . addReg ( Op1 ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ 0 ] ) ) ; } return ResultReg ; } </s>

Emit a MachineInstr with two register operands and a result register in the given register class .


<s> void Cpu0MCInstLower :: Initialize ( MCContext * C ) { Ctx = C ; } </s>

This method must be called before any actual lowering is done .


<s> static rtx altivec_expand_ld_builtin ( tree exp , rtx target , bool * expandedp ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , 0 ) ; unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; tree arg0 ; machine_mode tmode , mode0 ; rtx pat , op0 ; enum insn_code icode ; switch ( fcode ) { case ALTIVEC_BUILTIN_LD_INTERNAL_16qi : icode = CODE_FOR_vector_altivec_load_v16qi ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_8hi : icode = CODE_FOR_vector_altivec_load_v8hi ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_4si : icode = CODE_FOR_vector_altivec_load_v4si ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_4sf : icode = CODE_FOR_vector_altivec_load_v4sf ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_2df : icode = CODE_FOR_vector_altivec_load_v2df ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_2di : icode = CODE_FOR_vector_altivec_load_v2di ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_1ti : icode = CODE_FOR_vector_altivec_load_v1ti ; break ; default : * expandedp = false ; return NULL_RTX ; } * expandedp = true ; arg0 = CALL_EXPR_ARG ( exp , 0 ) ; op0 = expand_normal ( arg0 ) ; tmode = insn_data [ icode ] . operand [ 0 ] . mode ; mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; if ( target == 0 || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>


<s> bool arm_frame_pointer_required ( void ) { if ( SUBTARGET_FRAME_POINTER_REQUIRED ) return true ; if ( cfun -> has_nonlocal_label ) return true ; if ( TARGET_ARM && TARGET_APCS_FRAME && ! crtl -> is_leaf ) return true ; if ( ! IS_INTERRUPT ( arm_current_func_type ( ) ) && ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK || flag_stack_clash_protection ) && arm_except_unwind_info ( & global_options ) == UI_TARGET && cfun -> can_throw_non_call_exceptions ) { HOST_WIDE_INT size = get_frame_size ( ) ; if ( size <= 0 ) return false ; if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { size += 32 * UNITS_PER_WORD ; if ( size > PROBE_INTERVAL && size > get_stack_check_protect ( ) ) return true ; } else return true ; } return false ; } </s>


<s> static unsigned nvptx_process_pars ( parallel * par ) { if ( nvptx_optimize ) nvptx_optimize_inner ( par ) ; unsigned inner_mask = par -> mask ; if ( par -> inner ) { par -> inner_mask = nvptx_process_pars ( par -> inner ) ; inner_mask |= par -> inner_mask ; } bool is_call = ( par -> mask & GOMP_DIM_MASK ( GOMP_DIM_MAX ) ) != 0 ; if ( par -> mask & GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ) { nvptx_wpropagate ( false , is_call , par -> forked_block , par -> forked_insn ) ; bool empty = nvptx_wpropagate ( true , is_call , par -> forked_block , par -> fork_insn ) ; if ( ! empty || ! is_call ) { emit_insn_before ( nvptx_wsync ( false ) , par -> forked_insn ) ; emit_insn_before ( nvptx_wsync ( true ) , par -> join_insn ) ; } } else if ( par -> mask & GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) ) nvptx_vpropagate ( is_call , par -> forked_block , par -> forked_insn ) ; if ( par -> next ) inner_mask |= nvptx_process_pars ( par -> next ) ; return inner_mask ; } </s>

Process the parallel PAR and all its contained parallels . We do everything but the neutering . Return mask of partitioned modes used within this parallel .


<s> void MipsAsmPrinter :: emitFrameDirective ( ) { const TargetRegisterInfo & RI = * TM . getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) -> getStackSize ( ) ; O << "\t.frame\t" << '$' << LowercaseString ( getRegisterName ( stackReg ) ) << ',' << stackSize << ',' << '$' << LowercaseString ( getRegisterName ( returnReg ) ) << '\n' ; } </s>


<s> SDNode * SITargetLowering :: legalizeTargetIndependentNode ( SDNode * Node , SelectionDAG & DAG ) const { if ( Node -> getOpcode ( ) == ISD :: CopyToReg ) { RegisterSDNode * DestReg = cast < RegisterSDNode > ( Node -> getOperand ( 1 ) ) ; SDValue SrcVal = Node -> getOperand ( 2 ) ; if ( SrcVal . getValueType ( ) == MVT :: i1 && TargetRegisterInfo :: isPhysicalRegister ( DestReg -> getReg ( ) ) ) { SDLoc SL ( Node ) ; MachineRegisterInfo & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue VReg = DAG . getRegister ( MRI . createVirtualRegister ( & AMDGPU :: VReg_1RegClass ) , MVT :: i1 ) ; SDNode * Glued = Node -> getGluedNode ( ) ; SDValue ToVReg = DAG . getCopyToReg ( Node -> getOperand ( 0 ) , SL , VReg , SrcVal , SDValue ( Glued , Glued ? Glued -> getNumValues ( ) - 1 : 0 ) ) ; SDValue ToResultReg = DAG . getCopyToReg ( ToVReg , SL , SDValue ( DestReg , 0 ) , VReg , ToVReg . getValue ( 1 ) ) ; DAG . ReplaceAllUsesWith ( Node , ToResultReg . getNode ( ) ) ; DAG . RemoveDeadNode ( Node ) ; return ToResultReg . getNode ( ) ; } } SmallVector < SDValue , 8 > Ops ; for ( unsigned i = 0 ; i < Node -> getNumOperands ( ) ; ++ i ) { if ( ! isFrameIndexOp ( Node -> getOperand ( i ) ) ) { Ops . push_back ( Node -> getOperand ( i ) ) ; continue ; } SDLoc DL ( Node ) ; Ops . push_back ( SDValue ( DAG . getMachineNode ( AMDGPU :: S_MOV_B32 , DL , Node -> getOperand ( i ) . getValueType ( ) , Node -> getOperand ( i ) ) , 0 ) ) ; } return DAG . UpdateNodeOperands ( Node , Ops ) ; } </s>

Legalize target independent instructions ( e.g .


<s>
void
WebAssemblyTargetAsmStreamer
::
emitImportModule
(
const
MCSymbolWasm
*
Sym
,
StringRef
ModuleName
)
{
OS
<<
"\t.import_module\t"
<<
Sym
->
getName
(
)
<<
", "
<<
ModuleName
<<
'\n'
;
}
</s>

WebAssembly
WebAssembly
"\t.import_module\t"
", "


<s> static bool ix86_expand_vector_init_one_var ( bool mmx_ok , machine_mode mode , rtx target , rtx vals , int one_var ) { rtx var = XVECEXP ( vals , 0 , one_var ) ; machine_mode wmode ; rtx const_vec , x ; const_vec = copy_rtx ( vals ) ; XVECEXP ( const_vec , 0 , one_var ) = CONST0_RTX ( GET_MODE_INNER ( mode ) ) ; const_vec = gen_rtx_CONST_VECTOR ( mode , XVEC ( const_vec , 0 ) ) ; switch ( mode ) { case E_V2DFmode : case E_V2DImode : case E_V2SFmode : case E_V2SImode : return false ; case E_V4DImode : if ( ! TARGET_64BIT ) return false ; case E_V4DFmode : case E_V8SFmode : case E_V8SImode : case E_V16HImode : case E_V32QImode : case E_V4SFmode : case E_V4SImode : case E_V8HImode : case E_V4HImode : break ; case E_V16QImode : if ( TARGET_SSE4_1 ) break ; wmode = V8HImode ; goto widen ; case E_V8QImode : wmode = V4HImode ; goto widen ; widen : x = XVECEXP ( vals , 0 , one_var ^ 1 ) ; if ( one_var & 1 ) { var = convert_modes ( HImode , QImode , var , true ) ; var = expand_simple_binop ( HImode , ASHIFT , var , GEN_INT ( 8 ) , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; x = GEN_INT ( INTVAL ( x ) & 0xff ) ; } else { var = convert_modes ( HImode , QImode , var , true ) ; x = gen_int_mode ( UINTVAL ( x ) << 8 , HImode ) ; } if ( x != const0_rtx ) var = expand_simple_binop ( HImode , IOR , var , x , var , 1 , OPTAB_LIB_WIDEN ) ; x = gen_reg_rtx ( wmode ) ; emit_move_insn ( x , gen_lowpart ( wmode , const_vec ) ) ; ix86_expand_vector_set ( mmx_ok , x , var , one_var >> 1 ) ; emit_move_insn ( target , gen_lowpart ( mode , x ) ) ; return true ; default : return false ; } emit_move_insn ( target , const_vec ) ; ix86_expand_vector_set ( mmx_ok , target , var , one_var ) ; return true ; } </s>

A subroutine of ix86_expand_vector_init . Store into TARGET a vector consisting of the values in VALS . It is known that all elements except ONE_VAR are constants . Return true if successful .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
k_Immediate
:
OS
<<
"Imm<"
;
OS
<<
*
Imm
.
Val
;
OS
<<
">"
;
break
;
case
k_Memory
:
OS
<<
"Mem<"
;
Mem
.
Base
->
print
(
OS
)
;
OS
<<
", "
;
OS
<<
*
Mem
.
Off
;
OS
<<
">"
;
break
;
case
k_RegisterIndex
:
OS
<<
"RegIdx<"
<<
RegIdx
.
Index
<<
":"
<<
RegIdx
.
Kind
<<
", "
<<
StringRef
(
RegIdx
.
Tok
.
Data
,
RegIdx
.
Tok
.
Length
)
<<
">"
;
break
;
case
k_Token
:
OS
<<
getToken
(
)
;
break
;
case
k_RegList
:
OS
<<
"RegList< "
;
for
(
auto
Reg
:
(
*
RegList
.
List
)
)
OS
<<
Reg
<<
" "
;
OS
<<
">"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> bool ARMCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const { auto & TLI = * getTLI < ARMTargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb1Only ( ) ) return false ; if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; auto DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasPassPointeeByValueCopyAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , 8 > SplitArgInfos ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArgInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArgInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArgInfo , SplitArgInfos , MF ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgInfos , ArgHandler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> std :: pair < uint16_t , uint16_t > ARMBaseInstrInfo :: getExecutionDomain ( const MachineInstr & MI ) const { if ( Subtarget . hasNEON ( ) ) { if ( MI . getOpcode ( ) == ARM :: VMOVD && ! isPredicated ( MI ) ) return std :: make_pair ( ExeVFP , ( 1 << ExeVFP ) | ( 1 << ExeNEON ) ) ; if ( Subtarget . useNEONForFPMovs ( ) && ! isPredicated ( MI ) && ( MI . getOpcode ( ) == ARM :: VMOVRS || MI . getOpcode ( ) == ARM :: VMOVSR || MI . getOpcode ( ) == ARM :: VMOVS ) ) return std :: make_pair ( ExeVFP , ( 1 << ExeVFP ) | ( 1 << ExeNEON ) ) ; } unsigned Domain = MI . getDesc ( ) . TSFlags & ARMII :: DomainMask ; if ( Domain & ARMII :: DomainNEON ) return std :: make_pair ( ExeNEON , 0 ) ; if ( ( Domain & ARMII :: DomainNEONA8 ) && Subtarget . isCortexA8 ( ) ) return std :: make_pair ( ExeNEON , 0 ) ; if ( Domain & ARMII :: DomainVFP ) return std :: make_pair ( ExeVFP , 0 ) ; return std :: make_pair ( ExeGeneric , 0 ) ; } </s>

Return the current execution domain and bit mask of possible domains for instruction .


<s> void SIFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { SIMachineFunctionInfo * FuncInfo = MF . getInfo < SIMachineFunctionInfo > ( ) ; if ( FuncInfo -> isEntryFunction ( ) ) { emitEntryFunctionPrologue ( MF , MBB ) ; return ; } const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; const SIInstrInfo * TII = ST . getInstrInfo ( ) ; const SIRegisterInfo & TRI = TII -> getRegisterInfo ( ) ; unsigned StackPtrReg = FuncInfo -> getStackPtrOffsetReg ( ) ; unsigned FramePtrReg = FuncInfo -> getFrameOffsetReg ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc DL ; bool NeedFP = hasFP ( MF ) ; uint32_t NumBytes = MFI . getStackSize ( ) ; uint32_t RoundedSize = NumBytes ; const bool NeedsRealignment = TRI . needsStackRealignment ( MF ) ; if ( NeedsRealignment ) { assert ( NeedFP ) ; const unsigned Alignment = MFI . getMaxAlignment ( ) ; RoundedSize += Alignment ; unsigned ScratchSPReg = findScratchNonCalleeSaveRegister ( MBB ) ; assert ( ScratchSPReg != AMDGPU :: NoRegister ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( AMDGPU :: S_ADD_U32 ) , ScratchSPReg ) . addReg ( StackPtrReg ) . addImm ( ( Alignment - 1 ) * ST . getWavefrontSize ( ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( AMDGPU :: S_AND_B32 ) , FramePtrReg ) . addReg ( ScratchSPReg , RegState :: Kill ) . addImm ( - Alignment * ST . getWavefrontSize ( ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; FuncInfo -> setIsStackRealigned ( true ) ; } else if ( NeedFP ) { BuildMI ( MBB , MBBI , DL , TII -> get ( AMDGPU :: COPY ) , FramePtrReg ) . addReg ( StackPtrReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( RoundedSize != 0 && hasSP ( MF ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( AMDGPU :: S_ADD_U32 ) , StackPtrReg ) . addReg ( StackPtrReg ) . addImm ( RoundedSize * ST . getWavefrontSize ( ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( const SIMachineFunctionInfo :: SGPRSpillVGPRCSR & Reg : FuncInfo -> getSGPRSpillVGPRs ( ) ) { if ( ! Reg . FI . hasValue ( ) ) continue ; TII -> storeRegToStackSlot ( MBB , MBBI , Reg . VGPR , true , Reg . FI . getValue ( ) , & AMDGPU :: VGPR_32RegClass , & TII -> getRegisterInfo ( ) ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { int16_t Imm ; if ( isConditionalBranch ( Inst ) ) { Imm = Inst . getOperand ( 2 ) . getImm ( ) ; } else if ( isUnconditionalBranch ( Inst ) ) Imm = Inst . getOperand ( 0 ) . getImm ( ) ; else return false ; Target = Addr + Size + Imm * Size ; return true ; } </s>

Given a branch instruction try to get the address the branch targets .


<s> MCSymbol * X86AsmPrinter :: GetCPISymbol ( unsigned CPID ) const { if ( Subtarget -> isTargetKnownWindowsMSVC ( ) ) { const MachineConstantPoolEntry & CPE = MF -> getConstantPool ( ) -> getConstants ( ) [ CPID ] ; if ( ! CPE . isMachineConstantPoolEntry ( ) ) { const DataLayout & DL = MF -> getDataLayout ( ) ; SectionKind Kind = CPE . getSectionKind ( & DL ) ; const Constant * C = CPE . Val . ConstVal ; if ( const MCSectionCOFF * S = dyn_cast < MCSectionCOFF > ( getObjFileLowering ( ) . getSectionForConstant ( DL , Kind , C ) ) ) { if ( MCSymbol * Sym = S -> getCOMDATSymbol ( ) ) { if ( Sym -> isUndefined ( ) ) OutStreamer -> EmitSymbolAttribute ( Sym , MCSA_Global ) ; return Sym ; } } } } return AsmPrinter :: GetCPISymbol ( CPID ) ; } </s>

Return the symbol for the specified constant pool entry .


<s>
static
void
i386_output_dwarf_dtprel
(
FILE
*
file
,
int
size
,
rtx
x
)
{
fputs
(
ASM_LONG
,
file
)
;
output_addr_const
(
file
,
x
)
;
fputs
(
"@DTPOFF"
,
file
)
;
switch
(
size
)
{
case
4
:
break
;
case
8
:
fputs
(
", 0"
,
file
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
</s>

This is called from dwarf2out.cc via TARGET_ASM_OUTPUT_DWARF_DTPREL . We need to emit DTP-relative relocations .


<s> int ARM64FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { return resolveFrameIndexReference ( MF , FI , FrameReg ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> SDValue SITargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : return AMDGPUTargetLowering :: PerformDAGCombine ( N , DCI ) ; case ISD :: FADD : return performFAddCombine ( N , DCI ) ; case ISD :: FSUB : return performFSubCombine ( N , DCI ) ; case ISD :: SETCC : return performSetCCCombine ( N , DCI ) ; case ISD :: FMAXNUM : case ISD :: FMINNUM : case ISD :: SMAX : case ISD :: SMIN : case ISD :: UMAX : case ISD :: UMIN : case AMDGPUISD :: FMIN_LEGACY : case AMDGPUISD :: FMAX_LEGACY : { if ( DCI . getDAGCombineLevel ( ) >= AfterLegalizeDAG && getTargetMachine ( ) . getOptLevel ( ) > CodeGenOpt :: None ) return performMinMaxCombine ( N , DCI ) ; break ; } case ISD :: LOAD : case ISD :: STORE : case ISD :: ATOMIC_LOAD : case ISD :: ATOMIC_STORE : case ISD :: ATOMIC_CMP_SWAP : case ISD :: ATOMIC_CMP_SWAP_WITH_SUCCESS : case ISD :: ATOMIC_SWAP : case ISD :: ATOMIC_LOAD_ADD : case ISD :: ATOMIC_LOAD_SUB : case ISD :: ATOMIC_LOAD_AND : case ISD :: ATOMIC_LOAD_OR : case ISD :: ATOMIC_LOAD_XOR : case ISD :: ATOMIC_LOAD_NAND : case ISD :: ATOMIC_LOAD_MIN : case ISD :: ATOMIC_LOAD_MAX : case ISD :: ATOMIC_LOAD_UMIN : case ISD :: ATOMIC_LOAD_UMAX : case AMDGPUISD :: ATOMIC_INC : case AMDGPUISD :: ATOMIC_DEC : if ( DCI . isBeforeLegalize ( ) ) break ; return performMemSDNodeCombine ( cast < MemSDNode > ( N ) , DCI ) ; case ISD :: AND : return performAndCombine ( N , DCI ) ; case ISD :: OR : return performOrCombine ( N , DCI ) ; case ISD :: XOR : return performXorCombine ( N , DCI ) ; case AMDGPUISD :: FP_CLASS : return performClassCombine ( N , DCI ) ; case ISD :: FCANONICALIZE : return performFCanonicalizeCombine ( N , DCI ) ; case AMDGPUISD :: FRACT : case AMDGPUISD :: RCP : case AMDGPUISD :: RSQ : case AMDGPUISD :: RCP_LEGACY : case AMDGPUISD :: RSQ_LEGACY : case AMDGPUISD :: RSQ_CLAMP : case AMDGPUISD :: LDEXP : { SDValue Src = N -> getOperand ( 0 ) ; if ( Src . isUndef ( ) ) return Src ; break ; } case ISD :: SINT_TO_FP : case ISD :: UINT_TO_FP : return performUCharToFloatCombine ( N , DCI ) ; case AMDGPUISD :: CVT_F32_UBYTE0 : case AMDGPUISD :: CVT_F32_UBYTE1 : case AMDGPUISD :: CVT_F32_UBYTE2 : case AMDGPUISD :: CVT_F32_UBYTE3 : return performCvtF32UByteNCombine ( N , DCI ) ; case AMDGPUISD :: FMED3 : return performFMed3Combine ( N , DCI ) ; case AMDGPUISD :: CVT_PKRTZ_F16_F32 : return performCvtPkRTZCombine ( N , DCI ) ; } return AMDGPUTargetLowering :: PerformDAGCombine ( N , DCI ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s>
Register
getStackAddress
(
uint64_t
Size
,
int64_t
Offset
,
MachinePointerInfo
&
MPO
)
override
{
assert
(
(
Size
==
1
||
Size
==
2
||
Size
==
4
||
Size
==
8
)
&&
"Unsupported size"
)
;
auto
&
MFI
=
MIRBuilder
.
getMF
(
)
.
getFrameInfo
(
)
;
int
FI
=
MFI
.
CreateFixedObject
(
Size
,
Offset
,
true
)
;
MPO
=
MachinePointerInfo
::
getFixedStack
(
MIRBuilder
.
getMF
(
)
,
FI
)
;
return
MIRBuilder
.
buildFrameIndex
(
LLT
::
pointer
(
MPO
.
getAddrSpace
(
)
,
32
)
,
FI
)
.
getReg
(
0
)
;
}
</s>

Materialize a VReg containing the address of the specified stack-based object .


<s> void tilegx_expand_smuldi3_highpart ( rtx op0 , rtx op1 , rtx op2 ) { tilegx_expand_high_multiply ( op0 , op1 , op2 , true ) ; } </s>


Hook to validate the current # pragma GCC target and set the state , and update the macros based on what was changed . If ARGS is NULL , then POP_TARGET is used to reset the options .


<s> static int rs6000_issue_rate ( void ) { if ( ! reload_completed && ! flag_sched_pressure ) return 1 ; switch ( rs6000_tune ) { case PROCESSOR_RS64A : case PROCESSOR_PPC601 : case PROCESSOR_PPC7450 : return 3 ; case PROCESSOR_PPC440 : case PROCESSOR_PPC603 : case PROCESSOR_PPC750 : case PROCESSOR_PPC7400 : case PROCESSOR_PPC8540 : case PROCESSOR_PPC8548 : case PROCESSOR_CELL : case PROCESSOR_PPCE300C2 : case PROCESSOR_PPCE300C3 : case PROCESSOR_PPCE500MC : case PROCESSOR_PPCE500MC64 : case PROCESSOR_PPCE5500 : case PROCESSOR_PPCE6500 : case PROCESSOR_TITAN : return 2 ; case PROCESSOR_PPC476 : case PROCESSOR_PPC604 : case PROCESSOR_PPC604e : case PROCESSOR_PPC620 : case PROCESSOR_PPC630 : return 4 ; case PROCESSOR_POWER4 : case PROCESSOR_POWER5 : case PROCESSOR_POWER6 : case PROCESSOR_POWER7 : return 5 ; case PROCESSOR_POWER8 : return 7 ; case PROCESSOR_POWER9 : return 6 ; default : return 1 ; } } </s>

Return how many instructions the machine can issue per cycle .


<s>
static
void
write_return_mode
(
std
::
stringstream
&
s
,
bool
for_proto
,
machine_mode
mode
)
{
const
char
*
ptx_type
=
nvptx_ptx_type_from_mode
(
mode
,
false
)
;
const
char
*
pfx
=
"\t.reg"
;
const
char
*
sfx
=
";\n"
;
if
(
for_proto
)
pfx
=
"(.param"
,
sfx
=
"_out) "
;
s
<<
pfx
<<
ptx_type
<<
" "
<<
reg_names
[
NVPTX_RETURN_REGNUM
]
<<
sfx
;
}
</s>

Emit a PTX return as a prototype or function prologue declaration for MODE .

nvptx
"\t.reg"
";\n"
"(.param"
"_out) "
" "


<s> bool DCPU16AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { return true ; } printSrcMemOperand ( MI , OpNo , O ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s>
bool
AMDGPUCallLowering
::
lowerReturn
(
MachineIRBuilder
&
B
,
const
Value
*
Val
,
ArrayRef
<
Register
>
VRegs
,
FunctionLoweringInfo
&
FLI
)
const
{
MachineFunction
&
MF
=
B
.
getMF
(
)
;
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
SIMachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MFI
->
setIfReturnsVoid
(
!
Val
)
;
assert
(
!
Val
==
VRegs
.
empty
(
)
&&
"Return value without a vreg"
)
;
CallingConv
::
ID
CC
=
B
.
getMF
(
)
.
getFunction
(
)
.
getCallingConv
(
)
;
const
bool
IsShader
=
AMDGPU
::
isShader
(
CC
)
;
const
bool
IsWaveEnd
=
(
IsShader
&&
MFI
->
returnsVoid
(
)
)
||
AMDGPU
::
isKernel
(
CC
)
;
if
(
IsWaveEnd
)
{
B
.
buildInstr
(
AMDGPU
::
S_ENDPGM
)
.
addImm
(
0
)
;
return
true
;
}
auto
const
&
ST
=
MF
.
getSubtarget
<
GCNSubtarget
>
(
)
;
unsigned
ReturnOpc
=
IsShader
AMDGPU
::
SI_RETURN_TO_EPILOG
:
AMDGPU
::
S_SETPC_B64_return
;
auto
Ret
=
B
.
buildInstrNoInsert
(
ReturnOpc
)
;
Register
ReturnAddrVReg
;
if
(
ReturnOpc
==
AMDGPU
::
S_SETPC_B64_return
)
{
ReturnAddrVReg
=
MRI
.
createVirtualRegister
(
&
AMDGPU
::
CCR_SGPR_64RegClass
)
;
Ret
.
addUse
(
ReturnAddrVReg
)
;
}
if
(
!
FLI
.
CanLowerReturn
)
insertSRetStores
(
B
,
Val
->
getType
(
)
,
VRegs
,
FLI
.
DemoteRegister
)
;
else
if
(
!
lowerReturnVal
(
B
,
Val
,
VRegs
,
Ret
)
)
return
false
;
if
(
ReturnOpc
==
AMDGPU
::
S_SETPC_B64_return
)
{
const
SIRegisterInfo
*
TRI
=
ST
.
getRegisterInfo
(
)
;
Register
LiveInReturn
=
MF
.
addLiveIn
(
TRI
->
getReturnAddressReg
(
MF
)
,
&
AMDGPU
::
SGPR_64RegClass
)
;
B
.
buildCopy
(
ReturnAddrVReg
,
LiveInReturn
)
;
}
B
.
insertInstr
(
Ret
)
;
return
true
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> void MBlazeInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { llvm :: BuildMI ( MBB , I , DL , get ( MBlaze :: ADDK ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( MBlaze :: R0 ) ; } </s>


<s> bool ARMAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'a' : if ( MI -> getOperand ( OpNum ) . isReg ( ) ) { O << "[" << ARMInstPrinter :: getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << "]" ; return false ; } case 'c' : if ( ! MI -> getOperand ( OpNum ) . isImm ( ) ) return true ; O << MI -> getOperand ( OpNum ) . getImm ( ) ; return false ; case 'P' : case 'q' : printOperand ( MI , OpNum , O ) ; return false ; case 'Q' : case 'R' : case 'H' : return true ; } } printOperand ( MI , OpNum , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s>
void
X86InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
assert
(
MF
.
getFrameInfo
(
)
.
getObjectSize
(
FrameIdx
)
>=
TRI
->
getSpillSize
(
*
RC
)
&&
"Stack slot too small for store"
)
;
unsigned
Alignment
=
std
::
max
<
uint32_t
>
(
TRI
->
getSpillSize
(
*
RC
)
,
16
)
;
bool
isAligned
=
(
Subtarget
.
getFrameLowering
(
)
->
getStackAlignment
(
)
>=
Alignment
)
||
RI
.
canRealignStack
(
MF
)
;
unsigned
Opc
=
getStoreRegOpcode
(
SrcReg
,
RC
,
isAligned
,
Subtarget
)
;
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> SDValue AArch64TargetLowering :: getGOT ( NodeTy * N , SelectionDAG & DAG , unsigned Flags ) const { DEBUG ( dbgs ( ) << "AArch64TargetLowering::getGOT\n" ) ; SDLoc DL ( N ) ; EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue GotAddr = getTargetNode ( N , Ty , DAG , AArch64II :: MO_GOT | Flags ) ; return DAG . getNode ( AArch64ISD :: LOADgot , DL , Ty , GotAddr ) ; } </s>

Return a pseudo source value referencing the global offset table ( or something the like ) .


"getBranchTarget21OpValueMM expects only expressions or immediates"

getBranchTarget21OpValueMM - Return binary encoding of the branch target operand for microMIPS .


<s> static bool mips_valid_pointer_mode ( machine_mode mode ) { return mode == SImode || ( TARGET_64BIT && mode == DImode ) ; } </s>


<s> MachineInstr * SPUInstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , int FrameIndex ) const { if ( Ops . size ( ) != 1 ) return 0 ; unsigned OpNum = Ops [ 0 ] ; unsigned Opc = MI -> getOpcode ( ) ; MachineInstr * NewMI = 0 ; switch ( Opc ) { case SPU :: ORv16i8 : case SPU :: ORv8i16 : case SPU :: ORv4i32 : case SPU :: ORv2i64 : case SPU :: ORr8 : case SPU :: ORr16 : case SPU :: ORr32 : case SPU :: ORr64 : case SPU :: ORf32 : case SPU :: ORf64 : if ( OpNum == 0 ) { unsigned InReg = MI -> getOperand ( 1 ) . getReg ( ) ; bool isKill = MI -> getOperand ( 1 ) . isKill ( ) ; bool isUndef = MI -> getOperand ( 1 ) . isUndef ( ) ; if ( FrameIndex < SPUFrameInfo :: maxFrameOffset ( ) ) { MachineInstrBuilder MIB = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( SPU :: STQDr32 ) ) ; MIB . addReg ( InReg , getKillRegState ( isKill ) | getUndefRegState ( isUndef ) ) ; NewMI = addFrameReference ( MIB , FrameIndex ) ; } } else { unsigned OutReg = MI -> getOperand ( 0 ) . getReg ( ) ; bool isDead = MI -> getOperand ( 0 ) . isDead ( ) ; bool isUndef = MI -> getOperand ( 0 ) . isUndef ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( Opc ) ) ; MIB . addReg ( OutReg , RegState :: Define | getDeadRegState ( isDead ) | getUndefRegState ( isUndef ) ) ; Opc = ( FrameIndex < SPUFrameInfo :: maxFrameOffset ( ) ) ? SPU :: STQDr32 : SPU :: STQXr32 ; NewMI = addFrameReference ( MIB , FrameIndex ) ; break ; } } return NewMI ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s>
SDValue
MipsSETargetLowering
::
PerformDAGCombine
(
SDNode
*
N
,
DAGCombinerInfo
&
DCI
)
const
{
SelectionDAG
&
DAG
=
DCI
.
DAG
;
SDValue
Val
;
switch
(
N
->
getOpcode
(
)
)
{
case
ISD
::
AND
:
Val
=
performANDCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
break
;
case
ISD
::
OR
:
Val
=
performORCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
break
;
case
ISD
::
MUL
:
return
performMULCombine
(
N
,
DAG
,
DCI
,
this
,
Subtarget
)
;
case
ISD
::
SHL
:
Val
=
performSHLCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
break
;
case
ISD
::
SRA
:
return
performSRACombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
case
ISD
::
SRL
:
return
performSRLCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
case
ISD
::
VSELECT
:
return
performVSELECTCombine
(
N
,
DAG
)
;
case
ISD
::
XOR
:
Val
=
performXORCombine
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SETCC
:
Val
=
performSETCCCombine
(
N
,
DAG
)
;
break
;
}
if
(
Val
.
getNode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"\nMipsSE DAG Combine:\n"
;
N
->
printrWithDepth
(
dbgs
(
)
,
&
DAG
)
;
dbgs
(
)
<<
"\n=> \n"
;
Val
.
getNode
(
)
->
printrWithDepth
(
dbgs
(
)
,
&
DAG
)
;
dbgs
(
)
<<
"\n"
)
;
return
Val
;
}
return
MipsTargetLowering
::
PerformDAGCombine
(
N
,
DCI
)
;
}
</s>

Mips
Mips
ISD::AND
ISD::OR
ISD::MUL
ISD::SHL
ISD::SRA
ISD::SRL
ISD::VSELECT
ISD::XOR
ISD::SETCC
"\nMipsSE DAG Combine:\n"
"\n=> \n"
"\n"
Mips


<s> bool AMDGPUCallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < unsigned > VRegs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; MFI -> setIfReturnsVoid ( ! Val ) ; if ( ! Val ) { MIRBuilder . buildInstr ( AMDGPU :: S_ENDPGM ) . addImm ( 0 ) ; return true ; } unsigned VReg = VRegs [ 0 ] ; const Function & F = MF . getFunction ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; if ( ! AMDGPU :: isShader ( F . getCallingConv ( ) ) ) return false ; const AMDGPUTargetLowering & TLI = * getTLI < AMDGPUTargetLowering > ( ) ; SmallVector < EVT , 4 > SplitVTs ; SmallVector < uint64_t , 4 > Offsets ; ArgInfo OrigArg { VReg , Val -> getType ( ) } ; setArgFlags ( OrigArg , AttributeList :: ReturnIndex , DL , F ) ; ComputeValueVTs ( TLI , DL , OrigArg . Ty , SplitVTs , & Offsets , 0 ) ; SmallVector < ArgInfo , 8 > SplitArgs ; CCAssignFn * AssignFn = CCAssignFnForReturn ( F . getCallingConv ( ) , false ) ; for ( unsigned i = 0 , e = Offsets . size ( ) ; i != e ; ++ i ) { Type * SplitTy = SplitVTs [ i ] . getTypeForEVT ( F . getContext ( ) ) ; SplitArgs . push_back ( { VRegs [ i ] , SplitTy , OrigArg . Flags , OrigArg . IsFixed } ) ; } auto RetInstr = MIRBuilder . buildInstrNoInsert ( AMDGPU :: SI_RETURN_TO_EPILOG ) ; OutgoingArgHandler Handler ( MIRBuilder , MRI , RetInstr , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . insertInstr ( RetInstr ) ; return true ; } </s>


<s>
bool
AMDGPULegalizerInfo
::
legalizeCustom
(
LegalizerHelper
&
Helper
,
MachineInstr
&
MI
)
const
{
MachineIRBuilder
&
B
=
Helper
.
MIRBuilder
;
MachineRegisterInfo
&
MRI
=
*
B
.
getMRI
(
)
;
switch
(
MI
.
getOpcode
(
)
)
{
case
TargetOpcode
::
G_ADDRSPACE_CAST
:
return
legalizeAddrSpaceCast
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FRINT
:
return
legalizeFrint
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FCEIL
:
return
legalizeFceil
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FREM
:
return
legalizeFrem
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_INTRINSIC_TRUNC
:
return
legalizeIntrinsicTrunc
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_SITOFP
:
return
legalizeITOFP
(
MI
,
MRI
,
B
,
true
)
;
case
TargetOpcode
::
G_UITOFP
:
return
legalizeITOFP
(
MI
,
MRI
,
B
,
false
)
;
case
TargetOpcode
::
G_FPTOSI
:
return
legalizeFPTOI
(
MI
,
MRI
,
B
,
true
)
;
case
TargetOpcode
::
G_FPTOUI
:
return
legalizeFPTOI
(
MI
,
MRI
,
B
,
false
)
;
case
TargetOpcode
::
G_FMINNUM
:
case
TargetOpcode
::
G_FMAXNUM
:
case
TargetOpcode
::
G_FMINNUM_IEEE
:
case
TargetOpcode
::
G_FMAXNUM_IEEE
:
return
legalizeMinNumMaxNum
(
Helper
,
MI
)
;
case
TargetOpcode
::
G_EXTRACT_VECTOR_ELT
:
return
legalizeExtractVectorElt
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_INSERT_VECTOR_ELT
:
return
legalizeInsertVectorElt
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_SHUFFLE_VECTOR
:
return
legalizeShuffleVector
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FSIN
:
case
TargetOpcode
::
G_FCOS
:
return
legalizeSinCos
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_GLOBAL_VALUE
:
return
legalizeGlobalValue
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_LOAD
:
return
legalizeLoad
(
Helper
,
MI
)
;
case
TargetOpcode
::
G_FMAD
:
return
legalizeFMad
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FDIV
:
return
legalizeFDIV
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_UDIV
:
case
TargetOpcode
::
G_UREM
:
case
TargetOpcode
::
G_UDIVREM
:
return
legalizeUnsignedDIV_REM
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_SDIV
:
case
TargetOpcode
::
G_SREM
:
case
TargetOpcode
::
G_SDIVREM
:
return
legalizeSignedDIV_REM
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_ATOMIC_CMPXCHG
:
return
legalizeAtomicCmpXChg
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_FLOG
:
return
legalizeFlog
(
MI
,
B
,
numbers
::
ln2f
)
;
case
TargetOpcode
::
G_FLOG10
:
return
legalizeFlog
(
MI
,
B
,
numbers
::
ln2f
/
numbers
::
ln10f
)
;
case
TargetOpcode
::
G_FEXP
:
return
legalizeFExp
(
MI
,
B
)
;
case
TargetOpcode
::
G_FPOW
:
return
legalizeFPow
(
MI
,
B
)
;
case
TargetOpcode
::
G_FFLOOR
:
return
legalizeFFloor
(
MI
,
MRI
,
B
)
;
case
TargetOpcode
::
G_BUILD_VECTOR
:
return
legalizeBuildVector
(
MI
,
MRI
,
B
)
;
default
:
return
false
;
}
llvm_unreachable
(
"expected switch to return"
)
;
}
</s>

Called for instructions with the Custom LegalizationAction .

AMDGPU
AMDGPU
SI
SI
SI
SI
"expected switch to return"


<s> DecodeStatus PatmosDisassembler :: getInstruction ( MCInst & instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CStream ) const { uint32_t Insn ; Size = 0 ; DecodeStatus Result = readInstruction32 ( Bytes , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; bool isBundled = ( Insn >> 31 ) ; Insn &= ~ ( 1 << 31 ) ; Result = decodeInstruction ( DecoderTablePatmos32 , instr , Insn , Address , this , STI ) ; if ( Result == MCDisassembler :: Fail ) { if ( ! isBundled ) return MCDisassembler :: Fail ; uint32_t InsnL ; Result = readInstruction32 ( Bytes , Size , InsnL ) ; if ( Result == MCDisassembler :: Fail ) { return MCDisassembler :: Fail ; } uint64_t Insn64 = ( 1ULL << 63 ) | ( ( uint64_t ) Insn << 32 ) | InsnL ; Result = decodeInstruction ( DecoderTablePatmos64 , instr , Insn64 , Address , this , STI ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; isBundled = false ; } instr . addOperand ( MCOperand :: createImm ( isBundled ) ) ; adjustSignedImm ( instr ) ; return Result ; } </s>

Returns the disassembly of a single instruction .


<s> SDValue SystemZTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: SIGN_EXTEND : return combineSIGN_EXTEND ( N , DCI ) ; case SystemZISD :: MERGE_HIGH : case SystemZISD :: MERGE_LOW : return combineMERGE ( N , DCI ) ; case ISD :: STORE : return combineSTORE ( N , DCI ) ; case ISD :: EXTRACT_VECTOR_ELT : return combineEXTRACT_VECTOR_ELT ( N , DCI ) ; case SystemZISD :: JOIN_DWORDS : return combineJOIN_DWORDS ( N , DCI ) ; case ISD :: FP_ROUND : return combineFP_ROUND ( N , DCI ) ; case ISD :: BSWAP : return combineBSWAP ( N , DCI ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : case ISD :: ROTL : return combineSHIFTROT ( N , DCI ) ; } return SDValue ( ) ; } </s>


"VOP* instruction uses the constant bus more than once"

"VOP3 src0 cannot be a literal constant."

"VOP3 src1 cannot be a literal constant."

"VOP3 src2 cannot be a literal constant."

Perform target-specific instruction verification .


<s> static rtx s390_emit_compare_and_swap ( enum rtx_code code , rtx old , rtx mem , rtx cmp , rtx new_rtx , machine_mode ccmode ) { rtx cc ; cc = gen_rtx_REG ( ccmode , CC_REGNUM ) ; switch ( GET_MODE ( mem ) ) { case SImode : emit_insn ( gen_atomic_compare_and_swapsi_internal ( old , mem , cmp , new_rtx , cc ) ) ; break ; case DImode : emit_insn ( gen_atomic_compare_and_swapdi_internal ( old , mem , cmp , new_rtx , cc ) ) ; break ; case TImode : emit_insn ( gen_atomic_compare_and_swapti_internal ( old , mem , cmp , new_rtx , cc ) ) ; break ; case QImode : case HImode : default : gcc_unreachable ( ) ; } return s390_emit_compare ( code , cc , const0_rtx ) ; } </s>

Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD matches CMP . Return the correct condition RTL to be placed in the IF_THEN_ELSE of the conditional branch testing the result .


<s> static void aarch64_emit_store_exclusive ( machine_mode mode , rtx bval , rtx rval , rtx mem , rtx model_rtx ) { rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; switch ( mode ) { case QImode : gen = gen_aarch64_store_exclusiveqi ; break ; case HImode : gen = gen_aarch64_store_exclusivehi ; break ; case SImode : gen = gen_aarch64_store_exclusivesi ; break ; case DImode : gen = gen_aarch64_store_exclusivedi ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( bval , rval , mem , model_rtx ) ) ; } </s>


<s> unsigned getEUsPerCU ( const MCSubtargetInfo * STI ) { return 4 ; } </s>

Number of SIMDs/EUs ( execution units ) per `` CU '' ( `` compute unit '' ) , where the `` CU '' is the unit onto which workgroups are mapped .


"Unexpected data type for Gather/Scatter"

Calculate the cost of Gather / Scatter operation .


<s> static bool arm_cannot_copy_insn_p ( rtx_insn * insn ) { if ( recog_memoized ( insn ) == CODE_FOR_tlscall ) return true ; subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , ALL ) { const_rtx x = * iter ; if ( GET_CODE ( x ) == UNSPEC && ( XINT ( x , 1 ) == UNSPEC_PIC_BASE || XINT ( x , 1 ) == UNSPEC_PIC_UNIFIED ) ) return true ; } rtx set = single_set ( insn ) ; if ( set ) { rtx src = SET_SRC ( set ) ; if ( GET_CODE ( src ) == ZERO_EXTEND ) src = XEXP ( src , 0 ) ; if ( GET_CODE ( src ) == UNSPEC_VOLATILE && ( XINT ( src , 1 ) == VUNSPEC_LL || XINT ( src , 1 ) == VUNSPEC_LAX ) ) return true ; } return false ; } </s>

Must not copy any rtx that uses a pc-relative address .


<s> MCELFStreamer & MSP430TargetELFStreamer :: getStreamer ( ) { return static_cast < MCELFStreamer & > ( Streamer ) ; } </s>

Return the output streamer for the assembler .


<s> void ix86_register_pragmas ( void ) { targetm . target_option . pragma_parse = ix86_pragma_target_parse ; REGISTER_SUBTARGET_PRAGMAS ( ) ; } </s>

Register target pragmas . We need to add the hook for parsing # pragma GCC option here rather than in i386.cc since it will pull in various preprocessor functions , and those are not present in languages like fortran without a preprocessor .


<s>
static
void
segv_crash_handler
(
int
sig
ATTRIBUTE_UNUSED
)
{
internal_error
(
"segmentation fault (code)"
)
;
}
</s>

On Darwin/powerpc , hitting the stack limit turns into a SIGSEGV . This code detects the difference between hitting the stack limit and a true wild pointer dereference by looking at the instruction that faulted ; only a few kinds of instruction are used to access below the previous bottom of the stack .


<s> static void function_arg_record_value_3 ( HOST_WIDE_INT bitpos , struct function_arg_record_value_parms * parms ) { machine_mode mode ; unsigned int regno ; unsigned int startbit , endbit ; int this_slotno , intslots , intoffset ; rtx reg ; if ( parms -> intoffset == - 1 ) return ; intoffset = parms -> intoffset ; parms -> intoffset = - 1 ; startbit = intoffset & - BITS_PER_WORD ; endbit = ( bitpos + BITS_PER_WORD - 1 ) & - BITS_PER_WORD ; intslots = ( endbit - startbit ) / BITS_PER_WORD ; this_slotno = parms -> slotno + intoffset / BITS_PER_WORD ; intslots = MIN ( intslots , SPARC_INT_ARG_MAX - this_slotno ) ; if ( intslots <= 0 ) return ; if ( intoffset % BITS_PER_WORD != 0 ) mode = smallest_mode_for_size ( BITS_PER_WORD - intoffset % BITS_PER_WORD , MODE_INT ) ; else mode = word_mode ; intoffset /= BITS_PER_UNIT ; do { regno = parms -> regbase + this_slotno ; reg = gen_rtx_REG ( mode , regno ) ; XVECEXP ( parms -> ret , 0 , parms -> stack + parms -> nregs ) = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( intoffset ) ) ; this_slotno += 1 ; intoffset = ( intoffset | ( UNITS_PER_WORD - 1 ) ) + 1 ; mode = word_mode ; parms -> nregs += 1 ; intslots -= 1 ; } while ( intslots > 0 ) ; } </s>

A subroutine of function_arg_record_value . Assign the bits of the structure between parms- > intoffset and bitpos to integer registers .


<s> bool XCoreTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty ) const { if ( Ty -> getTypeID ( ) == Type :: VoidTyID ) return AM . Scale == 0 && isImmUs ( AM . BaseOffs ) && isImmUs4 ( AM . BaseOffs ) ; const DataLayout * TD = TM . getDataLayout ( ) ; unsigned Size = TD -> getTypeAllocSize ( Ty ) ; if ( AM . BaseGV ) { return Size >= 4 && ! AM . HasBaseReg && AM . Scale == 0 && AM . BaseOffs % 4 == 0 ; } switch ( Size ) { case 1 : if ( AM . Scale == 0 ) { return isImmUs ( AM . BaseOffs ) ; } return AM . Scale == 1 && AM . BaseOffs == 0 ; case 2 : case 3 : if ( AM . Scale == 0 ) { return isImmUs2 ( AM . BaseOffs ) ; } return AM . Scale == 2 && AM . BaseOffs == 0 ; default : if ( AM . Scale == 0 ) { return isImmUs4 ( AM . BaseOffs ) ; } return AM . Scale == 4 && AM . BaseOffs == 0 ; } } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> TargetTransformInfo LanaiTargetMachine :: getTargetTransformInfo ( const Function & F ) const { return TargetTransformInfo ( LanaiTTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> static FunctionType * getType ( LLVMContext & Context , unsigned id ) { Type * ResultTy = NULL ; SmallVector < Type * , 8 > ArgTys ; bool IsVarArg = false ; return FunctionType :: get ( ResultTy , ArgTys , IsVarArg ) ; } </s>

Overload to return most specific vector type .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"R600 Expand special instructions pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> const ARMMCExpr * ARMMCExpr :: Create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { return new ( Ctx ) ARMMCExpr ( Kind , Expr ) ; } </s>

Construct a unary instruction , given the opcode and an operand .


Output assembler code to FILE to call a profiler hook .


<s> bool LinearizedRegion :: isLiveOut ( unsigned Reg ) { return LiveOuts . count ( Reg ) == 1 ; } </s>

isLiveOut - Determine if Reg is live out from MBB , when not considering PHI nodes .


<s> int legitimate_pic_operand_p ( rtx op ) { if ( ! SYMBOLIC_CONST ( op ) ) return 1 ; return 0 ; } </s>

Return true if OP is a legitimate general operand when generating PIC code . It is given that flag_pic is on and that OP satisfies CONSTANT_P or is a CONST_DOUBLE .


<s> void AAPInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool VZeroUpperInserter :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getTarget ( ) . getInstrInfo ( ) ; bool Changed = false ; for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) Changed |= processBasicBlock ( MF , * BB ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s>
bool
AMDGPUAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
switch
(
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MatchingInlineAsm
)
)
{
default
:
break
;
case
Match_Success
:
Inst
.
setLoc
(
IDLoc
)
;
Out
.
EmitInstruction
(
Inst
,
STI
)
;
return
false
;
case
Match_MissingFeature
:
return
Error
(
IDLoc
,
"instruction not supported on this GPU"
)
;
case
Match_MnemonicFail
:
return
Error
(
IDLoc
,
"unrecognized instruction mnemonic"
)
;
case
Match_InvalidOperand
:
{
SMLoc
ErrorLoc
=
IDLoc
;
if
(
ErrorInfo
!=
~
0ULL
)
{
if
(
ErrorInfo
>=
Operands
.
size
(
)
)
{
if
(
isForcedVOP3
(
)
)
{
AMDGPUOperand
&
LastOp
=
(
(
AMDGPUOperand
&
)
*
Operands
[
Operands
.
size
(
)
1
]
)
;
if
(
LastOp
.
isRegKind
(
)
||
(
LastOp
.
isImm
(
)
&&
LastOp
.
getImmTy
(
)
!=
AMDGPUOperand
::
ImmTyNone
)
)
{
SMLoc
S
=
Parser
.
getTok
(
)
.
getLoc
(
)
;
Operands
.
push_back
(
AMDGPUOperand
::
CreateImm
(
0
,
S
,
AMDGPUOperand
::
ImmTyClamp
)
)
;
Operands
.
push_back
(
AMDGPUOperand
::
CreateImm
(
0
,
S
,
AMDGPUOperand
::
ImmTyOMod
)
)
;
bool
Res
=
MatchAndEmitInstruction
(
IDLoc
,
Opcode
,
Operands
,
Out
,
ErrorInfo
,
MatchingInlineAsm
)
;
if
(
!
Res
)
return
Res
;
}
}
return
Error
(
IDLoc
,
"too few operands for instruction"
)
;
}
ErrorLoc
=
(
(
AMDGPUOperand
&
)
*
Operands
[
ErrorInfo
]
)
.
getStartLoc
(
)
;
if
(
ErrorLoc
==
SMLoc
(
)
)
ErrorLoc
=
IDLoc
;
}
return
Error
(
ErrorLoc
,
"invalid operand for instruction"
)
;
}
}
llvm_unreachable
(
"Implement any new match types added!"
)
;
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> rtx riscv_subword ( rtx op , bool high_p ) { unsigned int byte = ( high_p != BYTES_BIG_ENDIAN ) ? UNITS_PER_WORD : 0 ; machine_mode mode = GET_MODE ( op ) ; if ( mode == VOIDmode ) mode = TARGET_64BIT ? TImode : DImode ; if ( MEM_P ( op ) ) return adjust_address ( op , word_mode , byte ) ; if ( REG_P ( op ) ) gcc_assert ( ! FP_REG_RTX_P ( op ) ) ; return simplify_gen_subreg ( word_mode , op , mode , byte ) ; } </s>

Return one word of double-word value OP . HIGH_P is true to select the high part or false to select the low part .


<s> int xtensa_debugger_regno ( int regno ) { int first = - 1 ; if ( GP_REG_P ( regno ) ) { regno -= GP_REG_FIRST ; first = 0 ; } else if ( BR_REG_P ( regno ) ) { regno -= BR_REG_FIRST ; first = 16 ; } else if ( FP_REG_P ( regno ) ) { regno -= FP_REG_FIRST ; first = 48 ; } else if ( ACC_REG_P ( regno ) ) { first = 0x200 ; regno = 16 ; } if ( first == - 1 ) return 0 ; return first + regno ; } </s>

Return the debugger register number to use for 'regno ' .


<s> static void aarch64_set_handled_components ( sbitmap components ) { for ( unsigned regno = 0 ; regno <= LAST_SAVED_REGNUM ; regno ++ ) if ( bitmap_bit_p ( components , regno ) ) cfun -> machine -> reg_is_wrapped_separately [ regno ] = true ; } </s>


<s> static inline bool mode_supports_dq_form ( machine_mode mode ) { return ( ( reg_addr [ mode ] . addr_mask [ RELOAD_REG_ANY ] & RELOAD_REG_QUAD_OFFSET ) != 0 ) ; } </s>

Return true if we have D-form addressing in VSX registers . This addressing is more limited than normal d-form addressing in that the offset must be aligned on a 16-byte boundary .


<s> int shl_sext_kind ( rtx left_rtx , rtx size_rtx , int * costp ) { int left , size , insize , ext ; int cost = 0 , best_cost ; int kind ; left = INTVAL ( left_rtx ) ; size = INTVAL ( size_rtx ) ; insize = size - left ; gcc_assert ( insize > 0 ) ; kind = 0 ; best_cost = shift_insns [ 32 - insize ] + ashiftrt_insns [ 32 - size ] ; if ( size <= 16 ) { cost = shift_insns [ 16 - insize ] + 1 + ashiftrt_insns [ 16 - size ] ; if ( cost < best_cost ) { kind = 5 ; best_cost = cost ; } } for ( ext = 16 ; ext >= insize ; ext -= 8 ) { if ( ext <= size ) { cost = ext_shift_insns [ ext - insize ] + 1 + shift_insns [ size - ext ] ; if ( cost < best_cost ) { kind = ext / ( unsigned ) 8 ; best_cost = cost ; } } if ( EXT_SHIFT_SIGNED ( size - ext ) ) cost = ext_shift_insns [ ext - insize ] + ext_shift_insns [ size - ext ] + 1 ; else if ( size <= 16 ) cost = ext_shift_insns [ ext - insize ] + 1 + ext_shift_insns [ size > ext ? size - ext : ext - size ] + 1 ; else continue ; if ( cost < best_cost ) { kind = ext / ( unsigned ) 8 + 2 ; best_cost = cost ; } } if ( insize < 8 ) { cost = 3 + shift_insns [ left ] ; if ( cost < best_cost ) { kind = 6 ; best_cost = cost ; } if ( left < 31 ) { cost = 3 + ext_shift_insns [ left + 1 ] + 1 ; if ( cost < best_cost ) { kind = 7 ; best_cost = cost ; } } } if ( TARGET_SH3 ) { cost = shift_insns [ 32 - insize ] + 1 + SH_DYNAMIC_SHIFT_COST ; if ( cost < best_cost ) { kind = 0 ; best_cost = cost ; } } if ( costp ) * costp = cost ; return kind ; } </s>

Try to find a good way to implement the combiner pattern [ ( set ( match_operand : SI 0 `` register_operand '' `` =r '' ) ( sign_extract : SI ( ashift : SI ( match_operand : SI 1 `` register_operand '' `` r '' ) ( match_operand : SI 2 `` const_int_operand '' `` n '' ) ( match_operand : SI 3 `` const_int_operand '' `` n '' ) ( const_int 0 ) ) ) ( clobber ( reg : SI T_REG ) ) ] LEFT_RTX is operand 2 in the above pattern , and SIZE_RTX is operand 3. return 0 for simple left / right shift combination . return 1 for left shift / 8 bit sign extend / left shift . return 2 for left shift / 16 bit sign extend / left shift . return 3 for left shift / 8 bit sign extend / shift / sign extend . return 4 for left shift / 16 bit sign extend / shift / sign extend . return 5 for left shift / 16 bit sign extend / right shift return 6 for < 8 bit sign extend / left shift . return 7 for < 8 bit sign extend / left shift / single right shift . If COSTP is nonzero , assign the calculated cost to * COSTP .


<s> void AnalyzeReturn ( const SmallVectorImpl < ISD :: OutputArg > & Outs , CCAssignFn Fn ) { PreAnalyzeReturnForF128 ( Outs ) ; CCState :: AnalyzeReturn ( Outs , Fn ) ; OriginalArgWasF128 . clear ( ) ; } </s>

AnalyzeReturn - Analyze the returned values of a return , incorporating info about the result values into this state .


<s> bool Z80FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB . getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool UseShadow = shouldUseShadow ( MF ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; if ( UseShadow ) shadowCalleeSavedRegisters ( MBB , MI , DL , MachineInstr :: FrameSetup , CSI ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( UseShadow && ! Z80 :: I24RegClass . contains ( Reg ) && ! Z80 :: I16RegClass . contains ( Reg ) ) continue ; bool isLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! isLiveIn ) MBB . addLiveIn ( Reg ) ; bool CanKill = ! isLiveIn ; if ( CanKill ) { for ( MCRegAliasIterator AReg ( Reg , TRI , false ) ; AReg . isValid ( ) ; ++ AReg ) { if ( MRI . isLiveIn ( * AReg ) ) { CanKill = false ; break ; } } } MachineInstrBuilder MIB ; if ( Reg == Z80 :: AF ) MIB = BuildMI ( MBB , MI , DL , TII . get ( Is24Bit ? Z80 :: PUSH24AF : Z80 :: PUSH16AF ) ) ; else MIB = BuildMI ( MBB , MI , DL , TII . get ( Is24Bit ? Z80 :: PUSH24r : Z80 :: PUSH16r ) ) . addReg ( Reg , getKillRegState ( CanKill ) ) ; MIB . setMIFlag ( MachineInstr :: FrameSetup ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static bool has_vtype_op ( rtx_insn * rinsn ) { return recog_memoized ( rinsn ) >= 0 && get_attr_has_vtype_op ( rinsn ) ; } </s>

Return true if it is an RVV instruction depends on VTYPE global status register .


<s> ScheduleHazardRecognizer :: HazardType GCNHazardRecognizer :: getHazardType ( SUnit * SU , int Stalls ) { MachineInstr * MI = SU -> getInstr ( ) ; if ( MI -> isBundle ( ) ) return NoHazard ; if ( SIInstrInfo :: isSMRD ( * MI ) && checkSMRDHazards ( MI ) > 0 ) return NoopHazard ; if ( ( SIInstrInfo :: isVMEM ( * MI ) || SIInstrInfo :: isFLAT ( * MI ) ) && checkVMEMHazards ( MI ) > 0 ) return NoopHazard ; if ( ST . hasNSAtoVMEMBug ( ) && checkNSAtoVMEMHazard ( MI ) > 0 ) return NoopHazard ; if ( checkFPAtomicToDenormModeHazard ( MI ) > 0 ) return NoopHazard ; if ( ST . hasNoDataDepHazard ( ) ) return NoHazard ; if ( SIInstrInfo :: isVALU ( * MI ) && checkVALUHazards ( MI ) > 0 ) return NoopHazard ; if ( SIInstrInfo :: isDPP ( * MI ) && checkDPPHazards ( MI ) > 0 ) return NoopHazard ; if ( isDivFMas ( MI -> getOpcode ( ) ) && checkDivFMasHazards ( MI ) > 0 ) return NoopHazard ; if ( isRWLane ( MI -> getOpcode ( ) ) && checkRWLaneHazards ( MI ) > 0 ) return NoopHazard ; if ( isSGetReg ( MI -> getOpcode ( ) ) && checkGetRegHazards ( MI ) > 0 ) return NoopHazard ; if ( isSSetReg ( MI -> getOpcode ( ) ) && checkSetRegHazards ( MI ) > 0 ) return NoopHazard ; if ( isRFE ( MI -> getOpcode ( ) ) && checkRFEHazards ( MI ) > 0 ) return NoopHazard ; if ( ST . hasReadM0MovRelInterpHazard ( ) && ( TII . isVINTRP ( * MI ) || isSMovRel ( MI -> getOpcode ( ) ) ) && checkReadM0Hazards ( MI ) > 0 ) return NoopHazard ; if ( ST . hasReadM0SendMsgHazard ( ) && isSendMsgTraceDataOrGDS ( TII , * MI ) && checkReadM0Hazards ( MI ) > 0 ) return NoopHazard ; if ( SIInstrInfo :: isMAI ( * MI ) && checkMAIHazards ( MI ) > 0 ) return NoopHazard ; if ( ( SIInstrInfo :: isVMEM ( * MI ) || SIInstrInfo :: isFLAT ( * MI ) || SIInstrInfo :: isDS ( * MI ) ) && checkMAILdStHazards ( MI ) > 0 ) return NoopHazard ; if ( MI -> isInlineAsm ( ) && checkInlineAsmHazards ( MI ) > 0 ) return NoopHazard ; return NoHazard ; } </s>

getHazardType - Return the hazard type of emitting this node .


<s> bool LC2200PassConfig :: addInstSelector ( ) { addPass ( createLC2200ISelDag ( getLC2200TargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


"eliminateCallFramePseudoInstr size too big: "

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool Z80oldTargetLowering :: shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const { assert ( Ty -> isIntegerTy ( ) ) ; return true ; } </s>

Returns true if it is beneficial to convert a load of a constant to just the constant itself .


<s>
StackOffset
AArch64FrameLowering
::
getFrameIndexReferencePreferSP
(
const
MachineFunction
&
MF
,
int
FI
,
Register
&
FrameReg
,
bool
IgnoreSPUpdates
)
const
{
const
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
if
(
IgnoreSPUpdates
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Offset from the SP for "
<<
FI
<<
" is "
<<
MFI
.
getObjectOffset
(
FI
)
<<
"\n"
)
;
FrameReg
=
AArch64
::
SP
;
return
StackOffset
::
getFixed
(
MFI
.
getObjectOffset
(
FI
)
)
;
}
return
getFrameIndexReference
(
MF
,
FI
,
FrameReg
)
;
}
</s>

Same as getFrameIndexReference , except that the stack pointer ( as opposed to the frame pointer ) will be the preferred value for FrameReg .


<s> bool PPCInstrInfo :: getMachineCombinerPatterns ( MachineInstr & Root , SmallVectorImpl < MachineCombinerPattern > & Patterns ) const { if ( Subtarget . getTargetMachine ( ) . getOptLevel ( ) != CodeGenOpt :: Aggressive ) return false ; return TargetInstrInfo :: getMachineCombinerPatterns ( Root , Patterns ) ; } </s>

Return true when there is potentially a faster code sequence for an instruction chain ending in Root .


<s> bool ARMBaseInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned TCycles , unsigned TExtra , MachineBasicBlock & FMBB , unsigned FCycles , unsigned FExtra , BranchProbability Probability ) const { if ( ! TCycles || ! FCycles ) return false ; const unsigned ScalingUpFactor = 1024 ; unsigned TUnpredCost = Probability . scale ( TCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FCycles * ScalingUpFactor ) ; unsigned UnpredCost = TUnpredCost + FUnpredCost ; UnpredCost += 1 * ScalingUpFactor ; UnpredCost += Subtarget . getMispredictionPenalty ( ) * ScalingUpFactor / 10 ; return ( TCycles + FCycles + TExtra + FExtra ) * ScalingUpFactor <= UnpredCost ; } </s>


"SGPR spill should have been removed in SILowerSGPRSpills"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> static int stackSlotSize ( ) { return 4 ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"A57 FP Anti-dependency breaker"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> LLT AArch64TargetLowering :: getOptimalMemOpLLT ( const MemOp & Op , const AttributeList & FuncAttributes ) const { bool CanImplicitFloat = ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; bool CanUseNEON = Subtarget -> hasNEON ( ) && CanImplicitFloat ; bool CanUseFP = Subtarget -> hasFPARMv8 ( ) && CanImplicitFloat ; bool IsSmallMemset = Op . isMemset ( ) && Op . size ( ) < 32 ; auto AlignmentIsAcceptable = [ & ] ( EVT VT , Align AlignCheck ) { if ( Op . isAligned ( AlignCheck ) ) return true ; bool Fast ; return allowsMisalignedMemoryAccesses ( VT , 0 , Align ( 1 ) , MachineMemOperand :: MONone , & Fast ) && Fast ; } ; if ( CanUseNEON && Op . isMemset ( ) && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: v2i64 , Align ( 16 ) ) ) return LLT :: fixed_vector ( 2 , 64 ) ; if ( CanUseFP && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: f128 , Align ( 16 ) ) ) return LLT :: scalar ( 128 ) ; if ( Op . size ( ) >= 8 && AlignmentIsAcceptable ( MVT :: i64 , Align ( 8 ) ) ) return LLT :: scalar ( 64 ) ; if ( Op . size ( ) >= 4 && AlignmentIsAcceptable ( MVT :: i32 , Align ( 4 ) ) ) return LLT :: scalar ( 32 ) ; return LLT ( ) ; } </s>


<s> void paired_expand_vector_init ( rtx target , rtx vals ) { machine_mode mode = GET_MODE ( target ) ; int n_elts = GET_MODE_NUNITS ( mode ) ; int n_var = 0 ; rtx x , new_rtx , tmp , constant_op , op1 , op2 ; int i ; for ( i = 0 ; i < n_elts ; ++ i ) { x = XVECEXP ( vals , 0 , i ) ; if ( ! ( CONST_SCALAR_INT_P ( x ) || CONST_DOUBLE_P ( x ) || CONST_FIXED_P ( x ) ) ) ++ n_var ; } if ( n_var == 0 ) { emit_move_insn ( target , gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , 0 ) ) ) ; return ; } if ( n_var == 2 ) { new_rtx = gen_rtx_VEC_CONCAT ( V2SFmode , XVECEXP ( vals , 0 , 0 ) , XVECEXP ( vals , 0 , 1 ) ) ; emit_move_insn ( target , new_rtx ) ; return ; } op1 = XVECEXP ( vals , 0 , 0 ) ; op2 = XVECEXP ( vals , 0 , 1 ) ; constant_op = ( CONSTANT_P ( op1 ) ) ? op1 : op2 ; tmp = gen_reg_rtx ( GET_MODE ( constant_op ) ) ; emit_move_insn ( tmp , constant_op ) ; if ( CONSTANT_P ( op1 ) ) new_rtx = gen_rtx_VEC_CONCAT ( V2SFmode , tmp , op2 ) ; else new_rtx = gen_rtx_VEC_CONCAT ( V2SFmode , op1 , tmp ) ; emit_move_insn ( target , new_rtx ) ; } </s>

Initialize TARGET of vector PAIRED to VALS .


<s> void OpenRISCFrameLowering :: emitPrologue ( MachineFunction & MF ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static tree tilepro_builtin_decl ( unsigned code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= TILEPRO_BUILTIN_max ) return error_mark_node ; return tilepro_builtin_info [ code ] . fndecl ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"WebAssembly Store Results"
;
}
</s>


<s> bool X86TTIImpl :: isLegalNTLoad ( Type * DataType , Align Alignment ) { unsigned DataSize = DL . getTypeStoreSize ( DataType ) ; if ( Alignment >= DataSize && ( DataSize == 16 || DataSize == 32 ) ) return DataSize == 16 ? ST -> hasSSE1 ( ) : ST -> hasAVX2 ( ) ; return false ; } </s>

Return true if the target supports nontemporal load .


<s> static int out_set_stack_ptr ( FILE * file , int before , int after ) { int do_sph , do_cli , do_save , do_sei , lock_sph , size ; do_sph = ! TARGET_TINY_STACK ; lock_sph = do_sph && ! TARGET_NO_INTERRUPTS ; do_cli = ( before != 0 && ( after == 0 || lock_sph ) ) ; do_save = ( do_cli && before == - 1 && after == - 1 ) ; do_sei = ( ( do_cli || before != 1 ) && after == 1 ) ; size = 1 ; if ( do_save ) { fprintf ( file , AS2 ( in , __tmp_reg__ , __SREG__ ) CR_TAB ) ; size ++ ; } if ( do_cli ) { fprintf ( file , "cli" CR_TAB ) ; size ++ ; } if ( do_sph ) { fprintf ( file , AS2 ( out , __SP_H__ , r29 ) CR_TAB ) ; size ++ ; } if ( do_save ) { fprintf ( file , AS2 ( out , __SREG__ , __tmp_reg__ ) CR_TAB ) ; size ++ ; } else if ( do_sei ) { fprintf ( file , "sei" CR_TAB ) ; size ++ ; } fprintf ( file , AS2 ( out , __SP_L__ , r28 ) "\n" ) ; return size ; } </s>

Output to FILE the asm instructions to copy r29 : r28 to SPH : SPL , handling various cases of interrupt enable flag state BEFORE and AFTER ( 0=disabled , 1=enabled , -1=unknown/unchanged ) and target_flags . Returns the number of instructions generated .


<s> static inline bool general_or_i64_p ( reg_class_t rclass ) { return ( rclass == GENERAL_REGS || rclass == I64_REGS ) ; } </s>

Return true if CLASS is either GENERAL_REGS or I64_REGS .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> unsigned PPCFastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( DL , C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return PPCMaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return PPCMaterializeGV ( GV , VT ) ; else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( C ) ) return PPCMaterializeInt ( CI , VT , false ) ; return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


"missing name in %<target(\"cpu=\")%> pragma or attribute"

"invalid name (\"%s\") in %<target(\"cpu=\")%> pragma or attribute"

"invalid value (\"%s\") in %<target()%> pragma or attribute"

Handle the argument CPU_STR to the cpu= target attribute . PRAGMA_OR_ATTR is used in potential error messages .


<s> void x86_elf_aligned_common ( FILE * file , const char * name , unsigned HOST_WIDE_INT size , int align ) { if ( ( ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC ) && size > ( unsigned int ) ix86_section_threshold ) fputs ( "\t.largecomm\t" , file ) ; else fputs ( COMMON_ASM_OP , file ) ; assemble_name ( file , name ) ; fprintf ( file , "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n" , size , align / BITS_PER_UNIT ) ; } </s>

This says how to output assembler code to declare an uninitialized external linkage data object . For medium model x86-64 we need to use .largecomm opcode for large objects .


<s> static void * mingw32_gt_pch_get_address ( size_t size , int fd ATTRIBUTE_UNUSED ) { void * res ; size = ( size + va_granularity - 1 ) & ~ ( va_granularity - 1 ) ; if ( size > pch_VA_max_size ) return NULL ; res = VirtualAlloc ( NULL , pch_VA_max_size , MEM_RESERVE | MEM_TOP_DOWN , PAGE_NOACCESS ) ; if ( ! res ) w32_error ( __FUNCTION__ , __FILE__ , __LINE__ , "VirtualAlloc" ) ; else VirtualFree ( res , 0 , MEM_RELEASE ) ; return res ; } </s>

Identify an address that 's likely to be free in a subsequent invocation of the compiler . The area should be able to hold SIZE bytes . FD is an open file descriptor if the host would like to probe with mmap .


<s> int fr30_num_arg_regs ( enum machine_mode mode , tree type ) { int size ; if ( targetm . calls . must_pass_in_stack ( mode , type ) ) return 0 ; if ( type && mode == BLKmode ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; return ( size + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } </s>

Compute the number of word sized registers needed to hold a function argument of mode INT_MODE and tree type TYPE .


<s> bool ARM64TargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { EVT VT ; SDValue Ptr ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; } else return false ; bool IsInc ; if ( ! getIndexedAddressParts ( Ptr . getNode ( ) , Base , Offset , AM , IsInc , DAG ) ) return false ; AM = IsInc ? ISD :: PRE_INC : ISD :: PRE_DEC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .


<s> void ia64_unpack_assemble ( rtx out , rtx lo , rtx hi , bool highp ) { machine_mode vmode = GET_MODE ( lo ) ; unsigned int i , high , nelt = GET_MODE_NUNITS ( vmode ) ; struct expand_vec_perm_d d ; bool ok ; d . target = gen_lowpart ( vmode , out ) ; d . op0 = ( TARGET_BIG_ENDIAN ? hi : lo ) ; d . op1 = ( TARGET_BIG_ENDIAN ? lo : hi ) ; d . vmode = vmode ; d . nelt = nelt ; d . one_operand_p = false ; d . testing_p = false ; high = ( highp ? nelt / 2 : 0 ) ; for ( i = 0 ; i < nelt / 2 ; ++ i ) { d . perm [ i * 2 ] = i + high ; d . perm [ i * 2 + 1 ] = i + high + nelt ; } ok = ia64_expand_vec_perm_const_1 ( & d ) ; gcc_assert ( ok ) ; } </s>

The vectors LO and HI each contain N halves of a double-wide vector . Reassemble either the first N/2 or the second N/2 elements .


<s> EVT TVMTargetLowering :: getOptimalMemOpType ( uint64_t , unsigned , unsigned , bool , bool , bool , MachineFunction & ) const { return MVT :: i257 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> static void register_vector_type ( vector_type_index type ) { tree vectype = abi_vector_types [ type ] ; tree id = get_identifier ( vector_types [ type ] . acle_name ) ; tree decl = build_decl ( input_location , TYPE_DECL , id , vectype ) ; decl = lang_hooks . decls . pushdecl ( decl ) ; if ( decl && TREE_CODE ( decl ) == TYPE_DECL && TYPE_MAIN_VARIANT ( TREE_TYPE ( decl ) ) == vectype ) vectype = TREE_TYPE ( decl ) ; acle_vector_types [ 0 ] [ type ] = vectype ; } </s>

Register vector type TYPE under its risv_vector.h name .


"expected larger existing stack allocation"

Target-specific cleanup for formal ByVal parameters .


<s> unsigned PPCTTIImpl :: getCacheLineSize ( ) const { if ( CacheLineSize . getNumOccurrences ( ) > 0 ) return CacheLineSize ; unsigned Directive = ST -> getCPUDirective ( ) ; if ( Directive == PPC :: DIR_PWR7 || Directive == PPC :: DIR_PWR8 || Directive == PPC :: DIR_PWR9 || Directive == PPC :: DIR_PWR10 || Directive == PPC :: DIR_PWR_FUTURE ) return 128 ; return 64 ; } </s>

Return the target cache line size in bytes .


<s> rtx m68k_libcall_value ( machine_mode mode ) { switch ( mode ) { case SFmode : case DFmode : case XFmode : if ( TARGET_68881 ) return gen_rtx_REG ( mode , FP0_REG ) ; break ; default : break ; } return gen_rtx_REG ( mode , m68k_libcall_value_in_a0_p ? A0_REG : D0_REG ) ; } </s>

Return floating point values in a 68881 register . This makes 68881 code a little bit faster . It also makes -msoft-float code incompatible with hard-float code , so people have to be careful not to mix the two . For ColdFire it was decided the ABI incompatibility is undesirable . If there is need for a hard-float ABI it is probably worth doing it properly and also passing function arguments in FP registers .


"X86-64 PIC uses RIP relative addressing"

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> BitVector DLXRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( DLX :: RA ) ; Reserved . set ( DLX :: FP ) ; Reserved . set ( DLX :: SP ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( getBaseRegister ( ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool runOnFunction ( Function & F ) override { bool C = false ; TargetMachine * TM = & getAnalysis < TargetPassConfig > ( ) . getTM < TargetMachine > ( ) ; TargetLibraryInfo * TLI = & getAnalysis < TargetLibraryInfoWrapperPass > ( ) . getTLI ( F ) ; X86LowerAMXCast LAC ( F ) ; C |= LAC . combineAMXcast ( TLI ) ; C |= LAC . transformAllAMXCast ( ) ; X86LowerAMXType LAT ( F ) ; C |= LAT . visit ( ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: None ) { if ( ! F . hasFnAttribute ( Attribute :: OptimizeNone ) ) { X86VolatileTileData VTD ( F ) ; C = VTD . volatileTileData ( ) || C ; } } return C ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> TargetLoweringBase :: LegalizeTypeAction SITargetLowering :: getPreferredVectorAction ( EVT VT ) const { if ( VT . getVectorNumElements ( ) != 1 && VT . getScalarType ( ) . bitsLE ( MVT :: i16 ) ) return TypeSplitVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { HST = & MF . getSubtarget < HexagonSubtarget > ( ) ; HII = HST -> getInstrInfo ( ) ; HRI = HST -> getRegisterInfo ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; updateAligna ( ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> void msp430_fixup_compare_operands ( machine_mode my_mode , rtx * operands ) { int const_op_idx = 1 ; if ( msp430_reversible_cmp_operator ( operands [ 0 ] , VOIDmode ) ) const_op_idx = 2 ; if ( GET_CODE ( operands [ const_op_idx ] ) != REG && GET_CODE ( operands [ const_op_idx ] ) != MEM ) operands [ const_op_idx ] = copy_to_mode_reg ( my_mode , operands [ const_op_idx ] ) ; } </s>

Called by cbranch < mode > 4 to coerce operands into usable forms .


<s> void SystemZPostRASchedStrategy :: advanceTo ( MachineBasicBlock :: iterator NextBegin ) { MachineBasicBlock :: iterator LastEmittedMI = HazardRec -> getLastEmittedMI ( ) ; MachineBasicBlock :: iterator I = ( ( LastEmittedMI != nullptr && LastEmittedMI -> getParent ( ) == MBB ) ? std :: next ( LastEmittedMI ) : MBB -> begin ( ) ) ; for ( ; I != NextBegin ; ++ I ) { if ( I -> isPosition ( ) || I -> isDebugValue ( ) ) continue ; HazardRec -> emitInstruction ( & * I ) ; } } </s>

advanceTo - Advance the specified iterator to point to the Segment containing the specified position , or end ( ) if the position is past the end of the range .


<s>
bool
SILoadStoreOptimizer
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
const
TargetSubtargetInfo
&
STM
=
MF
.
getSubtarget
(
)
;
TRI
=
static_cast
<
const
SIRegisterInfo
*
>
(
STM
.
getRegisterInfo
(
)
)
;
TII
=
static_cast
<
const
SIInstrInfo
*
>
(
STM
.
getInstrInfo
(
)
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
LIS
=
&
getAnalysis
<
LiveIntervals
>
(
)
;
DEBUG
(
dbgs
(
)
<<
"Running SILoadStoreOptimizer\n"
)
;
assert
(
!
MRI
->
isSSA
(
)
)
;
bool
Modified
=
false
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
Modified
|=
optimizeBlock
(
MBB
)
;
return
Modified
;
}
</s>

R600
SI
SI
SI
"Running SILoadStoreOptimizer\n"


<s> void VideoCore4InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> const char * tilegx_output_cbranch ( rtx_insn * insn , rtx * operands , bool reversed ) { enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; const char * opcode ; const char * rev_opcode ; if ( reversed ) code = reverse_condition ( code ) ; switch ( code ) { case NE : opcode = "bnez" ; rev_opcode = "beqz" ; break ; case EQ : opcode = "beqz" ; rev_opcode = "bnez" ; break ; case GE : opcode = "bgez" ; rev_opcode = "bltz" ; break ; case GT : opcode = "bgtz" ; rev_opcode = "blez" ; break ; case LE : opcode = "blez" ; rev_opcode = "bgtz" ; break ; case LT : opcode = "bltz" ; rev_opcode = "bgez" ; break ; default : gcc_unreachable ( ) ; } return tilegx_output_cbranch_with_opcode ( insn , operands , opcode , rev_opcode , 2 ) ; } </s>

Output assembly code for a conditional branch instruction .

tilegx 1 "bnez" "beqz" "beqz" "bnez" "bgez" "bltz" "bgtz" "blez" "blez" "bgtz" "bltz" "bgez" 2


<s> static void arc_add_jli_section ( rtx pat ) { const char * name ; tree attrs ; arc_jli_section * sec = arc_jli_sections , * new_section ; tree decl = SYMBOL_REF_DECL ( pat ) ; if ( ! pat ) return ; if ( decl ) { attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; if ( lookup_attribute ( "jli_fixed" , attrs ) ) return ; } name = XSTR ( pat , 0 ) ; while ( sec != NULL ) { if ( strcmp ( name , sec -> name ) == 0 ) return ; sec = sec -> next ; } new_section = ( arc_jli_section * ) xmalloc ( sizeof ( arc_jli_section ) ) ; gcc_assert ( new_section != NULL ) ; new_section -> name = name ; new_section -> next = arc_jli_sections ; arc_jli_sections = new_section ; } </s>

Add the given function declaration to emit code in JLI section .


<s> unsigned int AMDGPUIntrinsicInfo :: lookupName ( const char * Name , unsigned int Len ) const { if ( ! StringRef ( Name , Len ) . startswith ( "llvm." ) ) return 0 ; AMDGPUIntrinsic :: ID IntrinsicID = ( AMDGPUIntrinsic :: ID ) Intrinsic :: not_intrinsic ; IntrinsicID = getIntrinsicForGCCBuiltin ( "AMDGPU" , Name ) ; if ( IntrinsicID != ( AMDGPUIntrinsic :: ID ) Intrinsic :: not_intrinsic ) { return IntrinsicID ; } return 0 ; } </s>


<s> bool hasTailCall ( const MachineBasicBlock & MBB ) { MachineBasicBlock :: const_iterator I = MBB . getLastNonDebugInstr ( ) ; unsigned RetOpc = I -> getOpcode ( ) ; return RetOpc == Hexagon :: TCRETURNi || RetOpc == Hexagon :: TCRETURNr ; } </s>

Returns true if the function contains a tail call .


<s> static int epilogue_renumber ( rtx * where , int test ) { const char * fmt ; int i ; enum rtx_code code ; if ( * where == 0 ) return 0 ; code = GET_CODE ( * where ) ; switch ( code ) { case REG : if ( REGNO ( * where ) >= 8 && REGNO ( * where ) < 24 ) return 1 ; if ( ! test && REGNO ( * where ) >= 24 && REGNO ( * where ) < 32 ) * where = gen_rtx_REG ( GET_MODE ( * where ) , OUTGOING_REGNO ( REGNO ( * where ) ) ) ; case SCRATCH : case CC0 : case PC : case CONST_INT : case CONST_WIDE_INT : case CONST_DOUBLE : return 0 ; case PLUS : if ( GET_CODE ( XEXP ( * where , 0 ) ) == REG && REGNO ( XEXP ( * where , 0 ) ) == HARD_FRAME_POINTER_REGNUM && ( GET_CODE ( XEXP ( * where , 1 ) ) != CONST_INT || INTVAL ( XEXP ( * where , 1 ) ) < SPARC_STACK_BIAS ) ) return 1 ; break ; case MEM : if ( SPARC_STACK_BIAS && GET_CODE ( XEXP ( * where , 0 ) ) == REG && REGNO ( XEXP ( * where , 0 ) ) == HARD_FRAME_POINTER_REGNUM ) return 1 ; break ; default : break ; } fmt = GET_RTX_FORMAT ( code ) ; for ( i = GET_RTX_LENGTH ( code ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( * where , i ) - 1 ; j >= 0 ; j -- ) if ( epilogue_renumber ( & ( XVECEXP ( * where , i , j ) ) , test ) ) return 1 ; } else if ( fmt [ i ] == 'e' && epilogue_renumber ( & ( XEXP ( * where , i ) ) , test ) ) return 1 ; } return 0 ; } </s>

Return 1 , if any of the registers of the instruction are % l [ 0-7 ] or % o [ 0-7 ] . Such instructions can not be used in the delay slot of return insn on v9 . If TEST is 0 , also rename all % i [ 0-7 ] registers to their % o [ 0-7 ] counterparts .