<s> bool ARMFastISel :: fastLowerArguments ( ) { if ( ! FuncInfo . CanLowerReturn ) return false ; const Function * F = FuncInfo . Fn ; if ( F -> isVarArg ( ) ) return false ; CallingConv :: ID CC = F -> getCallingConv ( ) ; switch ( CC ) { default : return false ; case CallingConv :: Fast : case CallingConv :: C : case CallingConv :: ARM_AAPCS_VFP : case CallingConv :: ARM_AAPCS : case CallingConv :: ARM_APCS : case CallingConv :: Swift : break ; } unsigned Idx = 1 ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( Idx > 4 ) return false ; if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: SwiftSelf ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: SwiftError ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) ) return false ; Type * ArgTy = I -> getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( DL , ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : break ; default : return false ; } } static const MCPhysReg GPRArgRegs [ ] = { ARM :: R0 , ARM :: R1 , ARM :: R2 , ARM :: R3 } ; const TargetRegisterClass * RC = & ARM :: rGPRRegClass ; Idx = 0 ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { unsigned SrcReg = GPRArgRegs [ Idx ] ; unsigned DstReg = FuncInfo . MF -> addLiveIn ( SrcReg , RC ) ; unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( DstReg , getKillRegState ( true ) ) ; updateValueMap ( & * I , ResultReg ) ; } return true ; } </s>

This method is called by target-independent code to do target- specific argument lowering .


<s>
static
std
::
unique_ptr
<
X86Operand
>
CreateMem
(
unsigned
ModeSize
,
unsigned
SegReg
,
const
MCExpr
*
Disp
,
unsigned
BaseReg
,
unsigned
IndexReg
,
unsigned
Scale
,
SMLoc
StartLoc
,
SMLoc
EndLoc
,
unsigned
Size
=
0
,
unsigned
DefaultBaseReg
=
X86
::
NoRegister
,
StringRef
SymName
=
StringRef
(
)
,
void
*
OpDecl
=
nullptr
,
unsigned
FrontendSize
=
0
)
{
assert
(
(
SegReg
||
BaseReg
||
IndexReg
||
DefaultBaseReg
)
&&
"Invalid memory operand!"
)
;
assert
(
(
(
Scale
==
1
||
Scale
==
2
||
Scale
==
4
||
Scale
==
8
)
)
&&
"Invalid scale!"
)
;
auto
Res
=
std
::
make_unique
<
X86Operand
>
(
Memory
,
StartLoc
,
EndLoc
)
;
Res
->
Mem
.
SegReg
=
SegReg
;
Res
->
Mem
.
Disp
=
Disp
;
Res
->
Mem
.
BaseReg
=
BaseReg
;
Res
->
Mem
.
DefaultBaseReg
=
DefaultBaseReg
;
Res
->
Mem
.
IndexReg
=
IndexReg
;
Res
->
Mem
.
Scale
=
Scale
;
Res
->
Mem
.
Size
=
Size
;
Res
->
Mem
.
ModeSize
=
ModeSize
;
Res
->
Mem
.
FrontendSize
=
FrontendSize
;
Res
->
SymName
=
SymName
;
Res
->
OpDecl
=
OpDecl
;
Res
->
AddressOf
=
false
;
return
Res
;
}
</s>


<s> int nds32_target_alignment ( rtx_insn * label ) { rtx_insn * insn ; if ( ! NDS32_ALIGN_P ( ) ) return 0 ; insn = next_active_insn ( label ) ; if ( insn == 0 || ( get_attr_length ( insn ) == 2 && ! JUMP_P ( insn ) && ! CALL_P ( insn ) ) ) return 0 ; else return 2 ; } </s>

Return align 2 ( log base 2 ) if the next instruction of LABEL is 4 byte .


<s> static bool adjacent_mem_locations ( rtx mem1 , rtx mem2 ) { rtx reg1 , reg2 ; HOST_WIDE_INT off1 , size1 , off2 , size2 ; if ( get_memref_parts ( mem1 , & reg1 , & off1 , & size1 ) && get_memref_parts ( mem2 , & reg2 , & off2 , & size2 ) ) return ( ( REGNO ( reg1 ) == REGNO ( reg2 ) ) && ( ( off1 + size1 == off2 ) || ( off2 + size2 == off1 ) ) ) ; return false ; } </s>

If the target storage locations of arguments MEM1 and MEM2 are adjacent , then return the argument that has the lower address . Otherwise , return NULL_RTX .


<s> bool s390_split_ok_p ( rtx dst , rtx src , machine_mode mode , int first_subword ) { if ( FP_REG_P ( src ) || FP_REG_P ( dst ) || VECTOR_REG_P ( src ) || VECTOR_REG_P ( dst ) ) return false ; if ( ( GET_CODE ( src ) == MEM && ! offsettable_memref_p ( src ) ) || ( GET_CODE ( dst ) == MEM && ! offsettable_memref_p ( dst ) ) ) return false ; if ( register_operand ( dst , mode ) ) { rtx subreg = operand_subword ( dst , first_subword , 0 , mode ) ; if ( reg_overlap_mentioned_p ( subreg , src ) ) return false ; } return true ; } </s>

Check whether we can ( and want to ) split a double-word move in mode MODE from SRC to DST into two single-word moves , moving the subword FIRST_SUBWORD first .


<s> int s390_agen_dep_p ( rtx dep_insn , rtx insn ) { rtx dep_rtx = PATTERN ( dep_insn ) ; int i ; if ( GET_CODE ( dep_rtx ) == SET && addr_generation_dependency_p ( dep_rtx , insn ) ) return 1 ; else if ( GET_CODE ( dep_rtx ) == PARALLEL ) { for ( i = 0 ; i < XVECLEN ( dep_rtx , 0 ) ; i ++ ) { if ( addr_generation_dependency_p ( XVECEXP ( dep_rtx , 0 , i ) , insn ) ) return 1 ; } } return 0 ; } </s>

Return 1 , if dep_insn sets register used in insn in the agen unit .


<s> bool isMem ( ) const override { return isGPRMem ( ) || isMVEMem ( ) ; } </s>


<s> struct xstormy16_stack_layout xstormy16_compute_stack_layout ( void ) { struct xstormy16_stack_layout layout ; int regno ; const int ifun = xstormy16_interrupt_function_p ( ) ; layout . locals_size = get_frame_size ( ) ; layout . register_save_size = 0 ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( REG_NEEDS_SAVE ( regno , ifun ) ) layout . register_save_size += UNITS_PER_WORD ; if ( cfun -> stdarg ) layout . stdarg_save_size = NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD ; else layout . stdarg_save_size = 0 ; layout . frame_size = ( layout . locals_size + layout . register_save_size + layout . stdarg_save_size ) ; if ( crtl -> args . size <= 2048 && crtl -> args . size != - 1 ) { if ( layout . frame_size - INCOMING_FRAME_SP_OFFSET + crtl -> args . size <= 2048 ) layout . fp_minus_ap = layout . frame_size - INCOMING_FRAME_SP_OFFSET ; else layout . fp_minus_ap = 2048 - crtl -> args . size ; } else layout . fp_minus_ap = ( layout . stdarg_save_size + layout . register_save_size - INCOMING_FRAME_SP_OFFSET ) ; layout . sp_minus_fp = ( layout . frame_size - INCOMING_FRAME_SP_OFFSET - layout . fp_minus_ap ) ; layout . first_local_minus_ap = layout . sp_minus_fp - layout . locals_size ; return layout ; } </s>


<s> const Thumb1RegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


"\n========== quad_load_store, return %s\n"

Return true if this is a load or store quad operation . This function does not handle the atomic quad memory instructions .


<s>
MachineBasicBlock
*
KudeyarTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
unsigned
Opc
=
MI
->
getOpcode
(
)
;
const
TargetInstrInfo
&
TII
=
*
getTargetMachine
(
)
.
getInstrInfo
(
)
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
assert
(
(
Opc
==
Kudeyar
::
Select32T
||
Opc
==
Kudeyar
::
Select32F
)
&&
"Unexpected instr type to insert"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
I
=
BB
;
++
I
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
copy1MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
F
->
insert
(
I
,
copy0MBB
)
;
F
->
insert
(
I
,
copy1MBB
)
;
copy1MBB
->
splice
(
copy1MBB
->
begin
(
)
,
BB
,
llvm
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
BB
->
end
(
)
)
;
copy1MBB
->
transferSuccessorsAndUpdatePHIs
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
copy1MBB
)
;
int
br_code
;
switch
(
Opc
)
{
case
Kudeyar
::
Select32T
:
br_code
=
Kudeyar
::
BTs
;
break
;
case
Kudeyar
::
Select32F
:
br_code
=
Kudeyar
::
BFs
;
break
;
default
:
br_code
=
0
;
}
BuildMI
(
BB
,
dl
,
TII
.
get
(
br_code
)
)
.
addMBB
(
copy1MBB
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
copy1MBB
)
;
BB
=
copy1MBB
;
BuildMI
(
*
BB
,
BB
->
begin
(
)
,
dl
,
TII
.
get
(
Kudeyar
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
MI
->
eraseFromParent
(
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> int m32c_eh_return_data_regno ( int n ) { switch ( n ) { case 0 : return A0_REGNO ; case 1 : return A1_REGNO ; default : return INVALID_REGNUM ; } } </s>

Implements EH_RETURN_DATA_REGNO . Choose registers able to hold pointers .


<s> void build_mask64_2_operands ( rtx in , rtx * out ) { unsigned HOST_WIDE_INT c , lsb , m1 , m2 ; int shift ; gcc_assert ( GET_CODE ( in ) == CONST_INT ) ; c = INTVAL ( in ) ; if ( c & 1 ) { c = ~ c ; lsb = c & - c ; m1 = - lsb ; c = ~ c ; c &= - lsb ; lsb = c & - c ; c = ~ c ; c &= - lsb ; shift = 0 ; while ( ( lsb >>= 1 ) != 0 ) shift ++ ; m1 <<= 64 - shift ; m1 = ~ m1 ; m2 = ~ c ; } else { lsb = c & - c ; m2 = - lsb ; c = ~ c ; c &= - lsb ; lsb = c & - c ; c = ~ c ; c &= - lsb ; shift = 0 ; while ( ( lsb >>= 1 ) != 0 ) shift ++ ; m1 = ~ c ; m1 >>= shift ; m1 = ~ m1 ; } out [ 0 ] = GEN_INT ( 64 - shift ) ; out [ 1 ] = GEN_INT ( m1 ) ; out [ 2 ] = GEN_INT ( shift ) ; out [ 3 ] = GEN_INT ( m2 ) ; ( void ) in ; ( void ) out ; gcc_unreachable ( ) ; } </s>

Generates shifts and masks for a pair of rldicl or rldicr insns to implement ANDing by the mask IN .


<s> bool arm_simd_check_vect_par_cnst_half_p ( rtx op , machine_mode mode , bool high ) { rtx ideal = arm_simd_vect_par_cnst_half ( mode , high ) ; HOST_WIDE_INT count_op = XVECLEN ( op , 0 ) ; HOST_WIDE_INT count_ideal = XVECLEN ( ideal , 0 ) ; int i = 0 ; if ( ! VECTOR_MODE_P ( mode ) ) return false ; if ( count_op != count_ideal ) return false ; for ( i = 0 ; i < count_ideal ; i ++ ) { rtx elt_op = XVECEXP ( op , 0 , i ) ; rtx elt_ideal = XVECEXP ( ideal , 0 , i ) ; if ( ! CONST_INT_P ( elt_op ) || INTVAL ( elt_ideal ) != INTVAL ( elt_op ) ) return false ; } return true ; } </s>

Check OP for validity as a PARALLEL RTX vector with elements numbering the lanes of either the high ( HIGH == TRUE ) or low lanes , from the perspective of the architecture . See the diagram above arm_simd_vect_par_cnst_half_p for more details .


"Cannot emit contents before setting section!"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void SparcFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { MachineInstr & MI = * I ; DebugLoc dl = MI . getDebugLoc ( ) ; int Size = MI . getOperand ( 0 ) . getImm ( ) ; if ( MI . getOpcode ( ) == SP :: ADJCALLSTACKDOWN ) Size = - Size ; const SparcInstrInfo & TII = * static_cast < const SparcInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; if ( Size ) BuildMI ( MBB , I , dl , TII . get ( SP :: ADDri ) , SP :: O6 ) . addReg ( SP :: O6 ) . addImm ( Size ) ; MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

Sparc Sparc 0 SP::ADJCALLSTACKDOWN Sparc Sparc SP::ADDri SP::O6 SP::O6


<s> void RISCVPassConfig :: addPreEmitPass ( ) { addPass ( & BranchRelaxationPassID ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static void xtensa_output_mi_thunk ( FILE * file , tree thunk ATTRIBUTE_UNUSED , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { rtx this_rtx ; rtx funexp ; rtx_insn * insn ; int this_reg_no ; rtx temp0 = gen_rtx_REG ( Pmode , A9_REG ) ; const char * fnname = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( thunk ) ) ; reload_completed = 1 ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_reg_no = 3 ; else this_reg_no = 2 ; this_rtx = gen_rtx_REG ( Pmode , A0_REG + this_reg_no ) ; if ( delta ) xtensa_emit_add_imm ( this_rtx , this_rtx , delta , temp0 , false ) ; if ( vcall_offset ) { rtx temp1 = gen_rtx_REG ( Pmode , A0_REG + 10 ) ; rtx addr = temp1 ; emit_move_insn ( temp0 , gen_rtx_MEM ( Pmode , this_rtx ) ) ; if ( xtensa_uimm8x4 ( vcall_offset ) ) addr = plus_constant ( Pmode , temp0 , vcall_offset ) ; else xtensa_emit_add_imm ( temp1 , temp0 , vcall_offset , temp1 , false ) ; emit_move_insn ( temp1 , gen_rtx_MEM ( Pmode , addr ) ) ; emit_insn ( gen_add2_insn ( this_rtx , temp1 ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = 1 ; } funexp = XEXP ( DECL_RTL ( function ) , 0 ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx ) ) ; SIBLING_CALL_P ( insn ) = 1 ; insn = get_insns ( ) ; shorten_branches ( insn ) ; assemble_start_function ( thunk , fnname ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; assemble_end_function ( thunk , fnname ) ; reload_completed = 0 ; } </s>

Output code to add DELTA to the first argument , and then jump to FUNCTION . Used for C++ multiple inheritance .


<s> static void build_sv_index ( function_builder & b , const char * signature , const function_group_info & group ) { build_32_64 ( b , signature , group , MODE_s32index , MODE_s64index ) ; build_32_64 ( b , signature , group , MODE_u32index , MODE_u64index ) ; } </s>

For every type and predicate combination in GROUP , add one function that takes a scalar ( pointer ) base and a signed vector array index , and another that instead takes an unsigned vector array index . The vector array index has the same element size as the first function type suffix . SIGNATURE is as for build_all .


<s> unsigned char X86Subtarget :: classifyGlobalReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return X86II :: MO_NO_FLAG ; if ( GV ) { if ( Optional < ConstantRange > CR = GV -> getAbsoluteSymbolRange ( ) ) { if ( CR -> getUnsignedMax ( ) . ult ( 128 ) ) return X86II :: MO_ABS8 ; else return X86II :: MO_NO_FLAG ; } } if ( shouldAssumeGlobalReferenceLocal ( this , TM , M , GV ) ) return classifyLocalReference ( GV ) ; if ( isTargetCOFF ( ) ) return X86II :: MO_DLLIMPORT ; if ( is64Bit ( ) ) return X86II :: MO_GOTPCREL ; if ( isTargetDarwin ( ) ) { if ( ! isPositionIndependent ( ) ) return X86II :: MO_DARWIN_NONLAZY ; return X86II :: MO_DARWIN_NONLAZY_PIC_BASE ; } return X86II :: MO_GOT ; } </s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s>
const
char
*
output_mov_double_arm_from_fpa
(
rtx
*
operands
)
{
int
arm_reg0
=
REGNO
(
operands
[
0
]
)
;
rtx
ops
[
2
]
;
gcc_assert
(
arm_reg0
!=
IP_REGNUM
)
;
ops
[
0
]
=
gen_rtx_REG
(
SImode
,
arm_reg0
)
;
ops
[
1
]
=
gen_rtx_REG
(
SImode
,
1
+
arm_reg0
)
;
output_asm_insn
(
"stf%?d\t%1, [%|sp, #-8]!"
,
operands
)
;
output_asm_insn
(
"ldm%?fd\t%|sp!, {%0, %1}"
,
ops
)
;
return
""
;
}
</s>

Output a move from an fpa register to arm registers . OPERANDS [ 0 ] is the first registers of an arm register pair . OPERANDS [ 1 ] is an fpa register .


<s>
bool
RISCVInstrInfo
::
verifyInstruction
(
const
MachineInstr
&
MI
,
StringRef
&
ErrInfo
)
const
{
const
MCInstrInfo
*
MCII
=
STI
.
getInstrInfo
(
)
;
MCInstrDesc
const
&
Desc
=
MCII
->
get
(
MI
.
getOpcode
(
)
)
;
for
(
auto
&
OI
:
enumerate
(
Desc
.
operands
(
)
)
)
{
unsigned
OpType
=
OI
.
value
(
)
.
OperandType
;
if
(
OpType
>=
RISCVOp
::
OPERAND_FIRST_RISCV_IMM
&&
OpType
<=
RISCVOp
::
OPERAND_LAST_RISCV_IMM
)
{
const
MachineOperand
&
MO
=
MI
.
getOperand
(
OI
.
index
(
)
)
;
if
(
MO
.
isImm
(
)
)
{
int64_t
Imm
=
MO
.
getImm
(
)
;
bool
Ok
;
switch
(
OpType
)
{
default
:
llvm_unreachable
(
"Unexpected operand type"
)
;
case
RISCVOp
::
OPERAND_UIMM2
:
Ok
=
isUInt
<
2
>
(
Imm
)
;
break
;
case
RISCVOp
::
OPERAND_UIMM3
:
Ok
=
isUInt
<
3
>
(
Imm
)
;
break
;
case
RISCVOp
::
OPERAND_UIMM4
:
Ok
=
isUInt
<
4
>
(
Imm
)
;
break
;
case
RISCVOp
::
OPERAND_UIMM5
:
Ok
=
isUInt
<
5
>
(
Imm
)
;
break
;
case
RISCVOp
::
OPERAND_UIMM7
:
Ok
=
isUInt
<
7
>
(
Imm
)
;
break
;
case
RISCVOp
::
OPERAND_UIMM12
:
Ok
=
isUInt
<
12
>
(
Imm
)
;
break
;
case
RISCVOp
::
OPERAND_SIMM12
:
Ok
=
isInt
<
12
>
(
Imm
)
;
break
;
case
RISCVOp
::
OPERAND_UIMM20
:
Ok
=
isUInt
<
20
>
(
Imm
)
;
break
;
case
RISCVOp
::
OPERAND_UIMMLOG2XLEN
:
if
(
STI
.
getTargetTriple
(
)
.
isArch64Bit
(
)
)
Ok
=
isUInt
<
6
>
(
Imm
)
;
else
Ok
=
isUInt
<
5
>
(
Imm
)
;
break
;
}
if
(
!
Ok
)
{
ErrInfo
=
"Invalid immediate"
;
return
false
;
}
}
}
}
return
true
;
}
</s>

Perform target-specific instruction verification .


<s> bool MipsPassConfig :: addInstSelector ( ) { if ( getMipsSubtarget ( ) . allowMixed16_32 ( ) ) { addPass ( createMipsModuleISelDag ( getMipsTargetMachine ( ) ) ) ; addPass ( createMips16ISelDag ( getMipsTargetMachine ( ) ) ) ; addPass ( createMipsSEISelDag ( getMipsTargetMachine ( ) ) ) ; } else { addPass ( createMipsISelDag ( getMipsTargetMachine ( ) ) ) ; } return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips


<s> virtual SUnit * pickNode ( bool & IsTopNode ) { return 0 ; } </s>

Pick the next node to schedule , or return NULL .


<s> int h8300_eightbit_constant_address_p ( rtx x ) { const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode ( 0xff00 , HImode ) ; const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode ( 0xffff , HImode ) ; const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode ( 0x00ffff00 , SImode ) ; const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode ( 0x00ffffff , SImode ) ; const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode ( 0xffffff00 , SImode ) ; const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode ( 0xffffffff , SImode ) ; unsigned HOST_WIDE_INT addr ; if ( GET_CODE ( x ) == SYMBOL_REF ) return ( SYMBOL_REF_FLAGS ( x ) & SYMBOL_FLAG_EIGHTBIT_DATA ) != 0 ; if ( GET_CODE ( x ) != CONST_INT ) return 0 ; addr = INTVAL ( x ) ; return ( 0 || ( ( TARGET_H8300 || TARGET_NORMAL_MODE ) && IN_RANGE ( addr , n1 , n2 ) ) || ( TARGET_H8300H && IN_RANGE ( addr , h1 , h2 ) ) || ( TARGET_H8300S && IN_RANGE ( addr , s1 , s2 ) ) ) ; } </s>

Nonzero if X is a constant address suitable as an 8-bit absolute , which is a special case of the ' R ' operand .


<s> static rtx mn10300_builtin_saveregs ( void ) { rtx offset , mem ; tree fntype = TREE_TYPE ( current_function_decl ) ; int argadj = ( ( ! ( TYPE_ARG_TYPES ( fntype ) != 0 && ( TREE_VALUE ( tree_last ( TYPE_ARG_TYPES ( fntype ) ) ) != void_type_node ) ) ) ? UNITS_PER_WORD : 0 ) ; int set = get_varargs_alias_set ( ) ; if ( argadj ) offset = plus_constant ( current_function_arg_offset_rtx , argadj ) ; else offset = current_function_arg_offset_rtx ; mem = gen_rtx_MEM ( SImode , current_function_internal_arg_pointer ) ; set_mem_alias_set ( mem , set ) ; emit_move_insn ( mem , gen_rtx_REG ( SImode , 0 ) ) ; mem = gen_rtx_MEM ( SImode , plus_constant ( current_function_internal_arg_pointer , 4 ) ) ; set_mem_alias_set ( mem , set ) ; emit_move_insn ( mem , gen_rtx_REG ( SImode , 1 ) ) ; return copy_to_reg ( expand_binop ( Pmode , add_optab , current_function_internal_arg_pointer , offset , 0 , 0 , OPTAB_LIB_WIDEN ) ) ; } </s>

Flush the argument registers to the stack for a stdarg function ; return the new argument pointer .


<s> void X86InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Alignment = ( RC -> getSize ( ) / 8 ) == 32 ? 32 : 16 ; bool isAligned = ( TM . getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , TM ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) , DestReg ) , FrameIdx ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> bool X86TargetMachine :: addPreEmitPass ( PassManagerBase & PM ) { bool ShouldPrint = false ; if ( getOptLevel ( ) != CodeGenOpt :: None && Subtarget . hasSSE2 ( ) ) { PM . add ( createExecutionDependencyFixPass ( & X86 :: VR128RegClass ) ) ; ShouldPrint = true ; } if ( Subtarget . hasAVX ( ) && UseVZeroUpper ) { PM . add ( createX86IssueVZeroUpperPass ( ) ) ; ShouldPrint = true ; } return ShouldPrint ; } </s>


<s> static unsigned long arm_compute_func_type ( ) { unsigned long type = ARM_FT_UNKNOWN ; tree a ; tree attr ; if ( TREE_CODE ( current_function_decl ) != FUNCTION_DECL ) abort ( ) ; if ( optimize > 0 && current_function_nothrow && TREE_THIS_VOLATILE ( current_function_decl ) ) type |= ARM_FT_VOLATILE ; if ( current_function_needs_context ) type |= ARM_FT_NESTED ; attr = DECL_ATTRIBUTES ( current_function_decl ) ; a = lookup_attribute ( "naked" , attr ) ; if ( a != NULL_TREE ) type |= ARM_FT_NAKED ; if ( cfun -> machine -> eh_epilogue_sp_ofs != NULL_RTX ) type |= ARM_FT_EXCEPTION_HANDLER ; else { a = lookup_attribute ( "isr" , attr ) ; if ( a == NULL_TREE ) a = lookup_attribute ( "interrupt" , attr ) ; if ( a == NULL_TREE ) type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL ; else type |= arm_isr_value ( TREE_VALUE ( a ) ) ; } return type ; } </s>

Computes the type of the current function .


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) -> findAssociatedFragment ( ) ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s> static int sh_symbian_get_strip_length ( int c ) { return ( c == SH_SYMBIAN_FLAG_CHAR [ 0 ] ) ? strlen ( DLL_EXPORT_PREFIX ) : 0 ; } </s>

Return the length of a function name prefix that starts with the character ' c ' .


"calling %qD with SSE caling convention without "

"this is a GCC bug that can be worked around by adding "

Define how to find the value returned by a function . VALTYPE is the data type of the value ( as a tree ) . If the precise function being called is known , FUNC is its FUNCTION_DECL ; otherwise , FUNC is 0 .


<s> bool isReg ( RegisterKind RegKind ) const { return Kind == KindReg && Reg . Kind == RegKind ; } </s>


<s> static bool lm32_legitimate_address_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x , bool strict ) { if ( strict && REG_P ( x ) && STRICT_REG_OK_FOR_BASE_P ( x ) ) return true ; if ( ! strict && REG_P ( x ) && NONSTRICT_REG_OK_FOR_BASE_P ( x ) ) return true ; if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , 0 ) ) && ( ( strict && STRICT_REG_OK_FOR_BASE_P ( XEXP ( x , 0 ) ) ) || ( ! strict && NONSTRICT_REG_OK_FOR_BASE_P ( XEXP ( x , 0 ) ) ) ) && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT && satisfies_constraint_K ( XEXP ( ( x ) , 1 ) ) ) return true ; if ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_SMALL_P ( x ) ) return true ; return false ; } </s>


<s> Node * update ( Node * N ) { assert ( N != nullptr ) ; N -> Height = 1 + std :: max ( height ( N -> Left ) , height ( N -> Right ) ) ; if ( N -> Left ) N -> MaxEnd = std :: max ( N -> MaxEnd , N -> Left -> MaxEnd ) ; if ( N -> Right ) N -> MaxEnd = std :: max ( N -> MaxEnd , N -> Right -> MaxEnd ) ; return N ; } </s>


<s> static void fusion_split_address ( rtx addr , rtx * p_hi , rtx * p_lo ) { rtx hi , lo ; if ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) { hi = XEXP ( addr , 0 ) ; lo = XEXP ( addr , 1 ) ; } else gcc_unreachable ( ) ; * p_hi = hi ; * p_lo = lo ; } </s>

Given an address , convert it into the addis and load offset parts . Addresses created during the peephole2 process look like : ( lo_sum ( high ( unspec [ ( sym ) ] UNSPEC_TOCREL ) ) ( unspec [ ( ... ) ] UNSPEC_TOCREL ) )


<s> void m32c_conditional_register_usage ( void ) { int i ; if ( 0 <= target_memregs && target_memregs <= 16 ) { for ( i = ( target_memregs + 1 ) / 2 ; i < 8 ; i ++ ) { fixed_regs [ MEM0_REGNO + i ] = 1 ; CLEAR_HARD_REG_BIT ( reg_class_contents [ MEM_REGS ] , MEM0_REGNO + i ) ; } } if ( TARGET_A24 ) { call_used_regs [ R1_REGNO ] = 0 ; call_used_regs [ R2_REGNO ] = 0 ; call_used_regs [ R3_REGNO ] = 0 ; call_used_regs [ A0_REGNO ] = 0 ; call_used_regs [ A1_REGNO ] = 0 ; } } </s>

Implements CONDITIONAL_REGISTER_USAGE . We adjust the number of available memregs , and select which registers need to be preserved across calls based on the chip family .


<s> const NVPTXRegisterInfo * getRegisterInfo ( ) const override { return & ( InstrInfo . getRegisterInfo ( ) ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool divmod_p ( rtx_insn * insn ) { gcc_assert ( get_attr_type ( insn ) == TYPE_DIV ) ; if ( INSN_CODE ( insn ) == CODE_FOR_divmodsi4 || INSN_CODE ( insn ) == CODE_FOR_udivmodsi4 ) return true ; return false ; } </s>

Check if the DIV insn needs two write ports .


<s>
StringRef
getPassName
(
)
const
override
{
return
"MIPS Os16 Optimization"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> bool SIAnnotateControlFlow :: doInitialization ( Module & M ) { LLVMContext & Context = M . getContext ( ) ; Void = Type :: getVoidTy ( Context ) ; Boolean = Type :: getInt1Ty ( Context ) ; Int64 = Type :: getInt64Ty ( Context ) ; ReturnStruct = StructType :: get ( Boolean , Int64 , ( Type * ) 0 ) ; BoolTrue = ConstantInt :: getTrue ( Context ) ; BoolFalse = ConstantInt :: getFalse ( Context ) ; BoolUndef = UndefValue :: get ( Boolean ) ; Int64Zero = ConstantInt :: get ( Int64 , 0 ) ; If = M . getOrInsertFunction ( IfIntrinsic , ReturnStruct , Boolean , ( Type * ) 0 ) ; Else = M . getOrInsertFunction ( ElseIntrinsic , ReturnStruct , Int64 , ( Type * ) 0 ) ; Break = M . getOrInsertFunction ( BreakIntrinsic , Int64 , Int64 , ( Type * ) 0 ) ; IfBreak = M . getOrInsertFunction ( IfBreakIntrinsic , Int64 , Boolean , Int64 , ( Type * ) 0 ) ; ElseBreak = M . getOrInsertFunction ( ElseBreakIntrinsic , Int64 , Int64 , Int64 , ( Type * ) 0 ) ; Loop = M . getOrInsertFunction ( LoopIntrinsic , Boolean , Int64 , ( Type * ) 0 ) ; EndCf = M . getOrInsertFunction ( EndCfIntrinsic , Void , Int64 , ( Type * ) 0 ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> static void nvptx_init_builtins ( void ) { ( nvptx_builtin_decls [ NVPTX_BUILTIN_ ## ID ] \ = add_builtin_function ( "__builtin_nvptx_" NAME , \ build_function_type_list T , \ NVPTX_BUILTIN_ ## ID , BUILT_IN_MD , NULL , NULL ) ) DEF ( SHUFFLE , "shuffle" , ( UINT , UINT , UINT , UINT , NULL_TREE ) ) ; DEF ( SHUFFLELL , "shufflell" , ( LLUINT , LLUINT , UINT , UINT , NULL_TREE ) ) ; DEF ( WORKER_ADDR , "worker_addr" , ( PTRVOID , ST , UINT , UINT , NULL_TREE ) ) ; DEF ( VECTOR_ADDR , "vector_addr" , ( PTRVOID , ST , UINT , UINT , NULL_TREE ) ) ; DEF ( CMP_SWAP , "cmp_swap" , ( UINT , PTRVOID , UINT , UINT , NULL_TREE ) ) ; DEF ( CMP_SWAPLL , "cmp_swapll" , ( LLUINT , PTRVOID , LLUINT , LLUINT , NULL_TREE ) ) ; DEF ( MEMBAR_GL , "membar_gl" , ( VOID , VOID , NULL_TREE ) ) ; DEF ( MEMBAR_CTA , "membar_cta" , ( VOID , VOID , NULL_TREE ) ) ; DEF ( BAR_RED_AND , "bar_red_and" , ( UINT , UINT , UINT , UINT , UINT , NULL_TREE ) ) ; DEF ( BAR_RED_OR , "bar_red_or" , ( UINT , UINT , UINT , UINT , UINT , NULL_TREE ) ) ; DEF ( BAR_RED_POPC , "bar_red_popc" , ( UINT , UINT , UINT , UINT , UINT , NULL_TREE ) ) ; } </s>

Set up all builtin functions for this target .


<s> bool PPCFrameLowering :: enableShrinkWrapping ( const MachineFunction & MF ) const { if ( MF . getInfo < PPCFunctionInfo > ( ) -> shrinkWrapDisabled ( ) ) return false ; return ( MF . getSubtarget < PPCSubtarget > ( ) . isSVR4ABI ( ) && MF . getSubtarget < PPCSubtarget > ( ) . isPPC64 ( ) ) ; } </s>

Returns true if the target will correctly handle shrink wrapping .


<s>
SDValue
PPCTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCRetInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCRetInfo
.
AnalyzeCallResult
(
Ins
,
(
Subtarget
.
isSVR4ABI
(
)
&&
CallConv
==
CallingConv
::
Cold
)
RetCC_PPC_Cold
:
RetCC_PPC
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Val
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
,
InFlag
)
;
Chain
=
Val
.
getValue
(
1
)
;
InFlag
=
Val
.
getValue
(
2
)
;
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
AExt
:
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
ZExt
:
Val
=
DAG
.
getNode
(
ISD
::
AssertZext
,
dl
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
SExt
:
Val
=
DAG
.
getNode
(
ISD
::
AssertSext
,
dl
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
}
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .

PowerPC
PPC
ISD::InputArg
16
PPC
PPC
0
"Can only return in registers!"
1
2
"Unknown loc info!"
ISD::TRUNCATE
ISD::AssertZext
ISD::TRUNCATE
ISD::AssertSext
ISD::TRUNCATE


<s> MVT X86TargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i1 && Subtarget . hasAVX512 ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; MVT RegisterVT ; unsigned NumRegisters ; std :: tie ( RegisterVT , NumRegisters ) = handleMaskRegisterForCallingConv ( NumElts , CC , Subtarget ) ; if ( RegisterVT != MVT :: INVALID_SIMPLE_VALUE_TYPE ) return RegisterVT ; } if ( ( VT == MVT :: v32i16 || VT == MVT :: v64i8 ) && ! EnableOldKNLABI && Subtarget . useAVX512Regs ( ) && ! Subtarget . hasBWI ( ) ) return MVT :: v16i32 ; return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


<s> static std :: unique_ptr < MINA32Operand > CreateReg ( unsigned RegNum , SMLoc S , SMLoc E ) { auto Op = std :: make_unique < MINA32Operand > ( k_Register ) ; Op -> Reg . RegNum = RegNum ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> unsigned stackAlignment ( ) const { return isFP64bit ( ) ? 16 : 8 ; } </s>

The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function .


<s> static void sparc_asm_function_prologue ( FILE * file , HOST_WIDE_INT size ATTRIBUTE_UNUSED ) { gcc_assert ( sparc_leaf_function_p == current_function_uses_only_leaf_regs ) ; sparc_output_scratch_registers ( file ) ; } </s>

This function generates the assembly code for function entry , which boils down to emitting the necessary .register directives .


<s> Register CSKYRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? CSKY :: R8 : CSKY :: R14 ; } </s>


<s> static bool avr_scalar_mode_supported_p ( scalar_mode mode ) { if ( ALL_FIXED_POINT_MODE_P ( mode ) ) return true ; if ( PSImode == mode ) return true ; return default_scalar_mode_supported_p ( mode ) ; } </s>

Implement ` TARGET_SCALAR_MODE_SUPPORTED_P ' .


"%qs attribute only applies to functions"

Handle an attribute requiring a FUNCTION_TYPE ; arguments as in struct attribute_spec.handler .


<s> static bool rs6000_scalar_mode_supported_p ( scalar_mode mode ) { if ( TARGET_32BIT && mode == TImode ) return false ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) return default_decimal_float_supported_p ( ) ; else if ( TARGET_FLOAT128_TYPE && ( mode == KFmode || mode == IFmode ) ) return true ; else return default_scalar_mode_supported_p ( mode ) ; } </s>

Target hook for scalar_mode_supported_p .


<s> SDValue AArch64TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : case ISD :: SUB : return performAddSubLongCombine ( N , DCI , DAG ) ; case ISD :: XOR : return performXorCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: MUL : return performMulCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SINT_TO_FP : case ISD :: UINT_TO_FP : return performIntToFpCombine ( N , DAG , Subtarget ) ; case ISD :: OR : return performORCombine ( N , DCI , Subtarget ) ; case ISD :: INTRINSIC_WO_CHAIN : return performIntrinsicCombine ( N , DCI , Subtarget ) ; case ISD :: ANY_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: SIGN_EXTEND : return performExtendCombine ( N , DCI , DAG ) ; case ISD :: BITCAST : return performBitcastCombine ( N , DCI , DAG ) ; case ISD :: CONCAT_VECTORS : return performConcatVectorsCombine ( N , DCI , DAG ) ; case ISD :: SELECT : return performSelectCombine ( N , DAG ) ; case ISD :: VSELECT : return performVSelectCombine ( N , DCI . DAG ) ; case ISD :: STORE : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case AArch64ISD :: BRCOND : return performBRCONDCombine ( N , DCI , DAG ) ; case AArch64ISD :: CSEL : return performCONDCombine ( N , DCI , DAG , 2 , 3 ) ; case AArch64ISD :: DUP : return performPostLD1Combine ( N , DCI , false ) ; case ISD :: INSERT_VECTOR_ELT : return performPostLD1Combine ( N , DCI , true ) ; case ISD :: INTRINSIC_VOID : case ISD :: INTRINSIC_W_CHAIN : switch ( cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) -> getZExtValue ( ) ) { case Intrinsic :: aarch64_neon_ld2 : case Intrinsic :: aarch64_neon_ld3 : case Intrinsic :: aarch64_neon_ld4 : case Intrinsic :: aarch64_neon_ld1x2 : case Intrinsic :: aarch64_neon_ld1x3 : case Intrinsic :: aarch64_neon_ld1x4 : case Intrinsic :: aarch64_neon_ld2lane : case Intrinsic :: aarch64_neon_ld3lane : case Intrinsic :: aarch64_neon_ld4lane : case Intrinsic :: aarch64_neon_ld2r : case Intrinsic :: aarch64_neon_ld3r : case Intrinsic :: aarch64_neon_ld4r : case Intrinsic :: aarch64_neon_st2 : case Intrinsic :: aarch64_neon_st3 : case Intrinsic :: aarch64_neon_st4 : case Intrinsic :: aarch64_neon_st1x2 : case Intrinsic :: aarch64_neon_st1x3 : case Intrinsic :: aarch64_neon_st1x4 : case Intrinsic :: aarch64_neon_st2lane : case Intrinsic :: aarch64_neon_st3lane : case Intrinsic :: aarch64_neon_st4lane : return performNEONPostLDSTCombine ( N , DCI , DAG ) ; default : break ; } } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> static rtx condjump_opposite_condition ( rtx insn ) { rtx pat = PATTERN ( insn ) ; int icode = INSN_CODE ( insn ) ; rtx x = NULL ; if ( icode == CODE_FOR_br_true || icode == CODE_FOR_br_false ) { x = XEXP ( SET_SRC ( pat ) , 0 ) ; if ( icode == CODE_FOR_br_false ) return x ; } if ( GET_CODE ( pat ) == COND_EXEC ) { rtx t = COND_EXEC_CODE ( pat ) ; if ( ( GET_CODE ( t ) == PARALLEL && GET_CODE ( XVECEXP ( t , 0 , 0 ) ) == RETURN ) || ( GET_CODE ( t ) == UNSPEC && XINT ( t , 1 ) == UNSPEC_REAL_JUMP ) || ( GET_CODE ( t ) == SET && SET_DEST ( t ) == pc_rtx ) ) x = COND_EXEC_TEST ( pat ) ; } if ( x != NULL_RTX ) { enum rtx_code code = GET_CODE ( x ) ; x = gen_rtx_fmt_ee ( code == EQ ? NE : EQ , GET_MODE ( x ) , XEXP ( x , 0 ) , XEXP ( x , 1 ) ) ; } return x ; } </s>

Examine INSN , and if it is a conditional jump of any kind , return the opposite of the condition in which it branches . Otherwise , return NULL_RTX .


<s> LLVMContext & getContext ( ) const { return Context ; } </s>

Return the LLVMContext used by the analysis .


<s> bool sh_cannot_change_mode_class ( machine_mode from , machine_mode to , enum reg_class rclass ) { if ( to == SFmode && VECTOR_MODE_P ( from ) && GET_MODE_INNER ( from ) == SFmode ) return optimize ? ( reg_classes_intersect_p ( GENERAL_REGS , rclass ) ) : false ; if ( GET_MODE_SIZE ( from ) != GET_MODE_SIZE ( to ) ) { if ( TARGET_LITTLE_ENDIAN ) { if ( GET_MODE_SIZE ( to ) < 8 || GET_MODE_SIZE ( from ) < 8 ) return reg_classes_intersect_p ( DF_REGS , rclass ) ; } else { if ( GET_MODE_SIZE ( from ) < 8 ) return reg_classes_intersect_p ( DF_REGS , rclass ) ; } } return false ; } </s>

Return the class of registers for which a mode change from FROM to TO is invalid .


<s> bool sh_cannot_change_mode_class ( enum machine_mode from , enum machine_mode to , enum reg_class class ) { if ( to == SFmode && VECTOR_MODE_P ( from ) && GET_MODE_INNER ( from ) == SFmode ) return ( reg_classes_intersect_p ( GENERAL_REGS , class ) ) ; if ( GET_MODE_SIZE ( from ) != GET_MODE_SIZE ( to ) ) { if ( TARGET_LITTLE_ENDIAN ) { if ( GET_MODE_SIZE ( to ) < 8 || GET_MODE_SIZE ( from ) < 8 ) return reg_classes_intersect_p ( DF_REGS , class ) ; } else { if ( GET_MODE_SIZE ( from ) < 8 ) return reg_classes_intersect_p ( DF_HI_REGS , class ) ; } } return 0 ; } </s>


<s> Register OutgoingValueHandler :: getStackAddress ( const CCValAssign & VA , MachineMemOperand * & MMO ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; const TargetFrameLowering * TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; LLT p0 = LLT :: pointer ( 0 , 32 ) ; LLT s32 = LLT :: scalar ( 32 ) ; auto SPReg = MIRBuilder . buildCopy ( p0 , Register ( Mips :: SP ) ) ; unsigned Offset = VA . getLocMemOffset ( ) ; auto OffsetReg = MIRBuilder . buildConstant ( s32 , Offset ) ; auto AddrReg = MIRBuilder . buildPtrAdd ( p0 , SPReg , OffsetReg ) ; MachinePointerInfo MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ; unsigned Size = alignTo ( VA . getValVT ( ) . getSizeInBits ( ) , 8 ) / 8 ; unsigned Align = MinAlign ( TFL -> getStackAlignment ( ) , Offset ) ; MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , Align ) ; return AddrReg . getReg ( 0 ) ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> static rtx nvptx_expand_builtin ( tree exp , rtx target , rtx ARG_UNUSED ( subtarget ) , machine_mode mode , int ignore ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , 0 ) ; switch ( DECL_FUNCTION_CODE ( fndecl ) ) { case NVPTX_BUILTIN_SHUFFLE : case NVPTX_BUILTIN_SHUFFLELL : return nvptx_expand_shuffle ( exp , target , mode , ignore ) ; case NVPTX_BUILTIN_WORKER_ADDR : return nvptx_expand_worker_addr ( exp , target , mode , ignore ) ; case NVPTX_BUILTIN_CMP_SWAP : case NVPTX_BUILTIN_CMP_SWAPLL : return nvptx_expand_cmp_swap ( exp , target , mode , ignore ) ; default : gcc_unreachable ( ) ; } } </s>

Expand an expression EXP that calls a built-in function , with result going to TARGET if that 's convenient ( and in mode MODE if that 's convenient ) . SUBTARGET may be used as the target for computing one of EXP 's operands . IGNORE is nonzero if the value is to be ignored .


<s> static bool ix86_check_avx256_register ( const_rtx exp ) { if ( SUBREG_P ( exp ) ) exp = SUBREG_REG ( exp ) ; return ( REG_P ( exp ) && VALID_AVX256_REG_OR_OI_MODE ( GET_MODE ( exp ) ) ) ; } </s>

Check if a 256bit AVX register is referenced inside of EXP .


<s> SDNode * SITargetLowering :: PostISelFolding ( MachineSDNode * Node , SelectionDAG & DAG ) const { const SIInstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; unsigned Opcode = Node -> getMachineOpcode ( ) ; if ( TII -> isMIMG ( Opcode ) && ! TII -> get ( Opcode ) . mayStore ( ) && ! TII -> isGather4 ( Opcode ) && AMDGPU :: getNamedOperandIdx ( Opcode , AMDGPU :: OpName :: dmask ) != - 1 ) { return adjustWritemask ( Node , DAG ) ; } if ( Opcode == AMDGPU :: INSERT_SUBREG || Opcode == AMDGPU :: REG_SEQUENCE ) { legalizeTargetIndependentNode ( Node , DAG ) ; return Node ; } switch ( Opcode ) { case AMDGPU :: V_DIV_SCALE_F32_e64 : case AMDGPU :: V_DIV_SCALE_F64_e64 : { SDValue Src0 = Node -> getOperand ( 1 ) ; SDValue Src1 = Node -> getOperand ( 3 ) ; SDValue Src2 = Node -> getOperand ( 5 ) ; if ( ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) != AMDGPU :: IMPLICIT_DEF ) && ( Src0 == Src1 || Src0 == Src2 ) ) break ; MVT VT = Src0 . getValueType ( ) . getSimpleVT ( ) ; const TargetRegisterClass * RC = getRegClassFor ( VT , Src0 . getNode ( ) -> isDivergent ( ) ) ; MachineRegisterInfo & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue UndefReg = DAG . getRegister ( MRI . createVirtualRegister ( RC ) , VT ) ; SDValue ImpDef = DAG . getCopyToReg ( DAG . getEntryNode ( ) , SDLoc ( Node ) , UndefReg , Src0 , SDValue ( ) ) ; if ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) == AMDGPU :: IMPLICIT_DEF ) { if ( Src1 . isMachineOpcode ( ) && Src1 . getMachineOpcode ( ) != AMDGPU :: IMPLICIT_DEF ) Src0 = Src1 ; else if ( Src2 . isMachineOpcode ( ) && Src2 . getMachineOpcode ( ) != AMDGPU :: IMPLICIT_DEF ) Src0 = Src2 ; else { assert ( Src1 . getMachineOpcode ( ) == AMDGPU :: IMPLICIT_DEF ) ; Src0 = UndefReg ; Src1 = UndefReg ; } } else break ; SmallVector < SDValue , 9 > Ops ( Node -> op_begin ( ) , Node -> op_end ( ) ) ; Ops [ 1 ] = Src0 ; Ops [ 3 ] = Src1 ; Ops [ 5 ] = Src2 ; Ops . push_back ( ImpDef . getValue ( 1 ) ) ; return DAG . getMachineNode ( Opcode , SDLoc ( Node ) , Node -> getVTList ( ) , Ops ) ; } default : break ; } return Node ; } </s>

Fold the instructions after selecting them .


<s>
bool
ARM64BranchRelaxation
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
MF
=
&
mf
;
if
(
!
BranchRelaxation
)
return
false
;
DEBUG
(
dbgs
(
)
<<
"***** ARM64BranchRelaxation *****\n"
)
;
TII
=
(
const
ARM64InstrInfo
*
)
MF
->
getTarget
(
)
.
getInstrInfo
(
)
;
MF
->
RenumberBlocks
(
)
;
scanFunction
(
)
;
DEBUG
(
dbgs
(
)
<<
"  Basic blocks before relaxation\n"
)
;
DEBUG
(
dumpBBs
(
)
)
;
bool
MadeChange
=
false
;
while
(
relaxBranchInstructions
(
)
)
MadeChange
=
true
;
verify
(
)
;
DEBUG
(
dbgs
(
)
<<
"  Basic blocks after relaxation\n"
)
;
DEBUG
(
dbgs
(
)
<<
'\n'
;
dumpBBs
(
)
)
;
BlockInfo
.
clear
(
)
;
return
MadeChange
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> void WebAssemblyFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { auto * MFI = MF . getFrameInfo ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! needsSP ( MF , * MFI ) || ! needsSPWriteback ( MF , * MFI ) ) return ; const auto * TII = MF . getSubtarget < WebAssemblySubtarget > ( ) . getInstrInfo ( ) ; auto & MRI = MF . getRegInfo ( ) ; auto InsertPt = MBB . getFirstTerminator ( ) ; DebugLoc DL ; if ( InsertPt != MBB . end ( ) ) DL = InsertPt -> getDebugLoc ( ) ; unsigned SPReg = 0 ; MachineBasicBlock :: iterator InsertAddr = InsertPt ; if ( StackSize ) { const TargetRegisterClass * PtrRC = MRI . getTargetRegisterInfo ( ) -> getPointerRegClass ( MF ) ; unsigned OffsetReg = MRI . createVirtualRegister ( PtrRC ) ; InsertAddr = BuildMI ( MBB , InsertPt , DL , TII -> get ( WebAssembly :: CONST_I32 ) , OffsetReg ) . addImm ( StackSize ) ; SPReg = MRI . createVirtualRegister ( PtrRC ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( WebAssembly :: ADD_I32 ) , SPReg ) . addReg ( hasFP ( MF ) ? WebAssembly :: FP32 : WebAssembly :: SP32 ) . addReg ( OffsetReg ) ; } else { SPReg = hasFP ( MF ) ? WebAssembly :: FP32 : WebAssembly :: SP32 ; } writeSPToMemory ( SPReg , MF , MBB , InsertAddr , InsertPt , DL ) ; } </s>


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> void executePostLayoutBinding ( MCAssembler & Asm , const MCAsmLayout & Layout ) override { } </s>

Perform any late binding of symbols ( for example , to assign symbol indices for use when generating relocations ) .


"_reflect function should not have a body"

"_reflect's return type should be integer"

"Wrong number of operands to __nvvm_reflect function"

"Format of __nvvm__reflect function not recognized"

"Format of __nvvm_reflect function not recognized"

"Format of _reflect function not recognized"

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool runOnFunction ( Function & F ) override { Func = & F ; return ProcessFunction ( ) ; } </s>


<s>
void
XCoreFrameInfo
::
emitEpilogue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
prior
(
MBB
.
end
(
)
)
;
const
XCoreInstrInfo
&
TII
=
*
static_cast
<
const
XCoreInstrInfo
*
>
(
MF
.
getTarget
(
)
.
getInstrInfo
(
)
)
;
DebugLoc
dl
=
MBBI
->
getDebugLoc
(
)
;
bool
FP
=
hasFP
(
MF
)
;
if
(
FP
)
{
unsigned
FramePtr
=
XCore
::
R10
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
XCore
::
SETSP_1r
)
)
.
addReg
(
FramePtr
)
;
}
int
FrameSize
=
MFI
->
getStackSize
(
)
;
assert
(
FrameSize
%
4
==
0
&&
"Misaligned frame size"
)
;
FrameSize
/=
4
;
bool
isU6
=
isImmU6
(
FrameSize
)
;
if
(
!
isU6
&&
!
isImmU16
(
FrameSize
)
)
{
report_fatal_error
(
"emitEpilogue Frame size too big: "
+
Twine
(
FrameSize
)
)
;
}
if
(
FrameSize
)
{
XCoreFunctionInfo
*
XFI
=
MF
.
getInfo
<
XCoreFunctionInfo
>
(
)
;
if
(
FP
)
{
int
FPSpillOffset
=
MFI
->
getObjectOffset
(
XFI
->
getFPSpillSlot
(
)
)
;
FPSpillOffset
+=
FrameSize
*
4
;
loadFromStack
(
MBB
,
MBBI
,
XCore
::
R10
,
FPSpillOffset
,
dl
,
TII
)
;
}
bool
restoreLR
=
XFI
->
getUsesLR
(
)
;
if
(
restoreLR
&&
MFI
->
getObjectOffset
(
XFI
->
getLRSpillSlot
(
)
)
!=
0
)
{
int
LRSpillOffset
=
MFI
->
getObjectOffset
(
XFI
->
getLRSpillSlot
(
)
)
;
LRSpillOffset
+=
FrameSize
*
4
;
loadFromStack
(
MBB
,
MBBI
,
XCore
::
LR
,
LRSpillOffset
,
dl
,
TII
)
;
restoreLR
=
false
;
}
if
(
restoreLR
)
{
assert
(
MBBI
->
getOpcode
(
)
==
XCore
::
RETSP_u6
||
MBBI
->
getOpcode
(
)
==
XCore
::
RETSP_lu6
)
;
int
Opcode
=
(
isU6
)
XCore
::
RETSP_u6
:
XCore
::
RETSP_lu6
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Opcode
)
)
.
addImm
(
FrameSize
)
;
MBB
.
erase
(
MBBI
)
;
}
else
{
int
Opcode
=
(
isU6
)
XCore
::
LDAWSP_ru6_RRegs
:
XCore
::
LDAWSP_lru6_RRegs
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Opcode
)
,
XCore
::
SP
)
.
addImm
(
FrameSize
)
;
}
}
}
</s>


<s> static unsigned int rs6000_parm_start ( machine_mode mode , const_tree type , unsigned int nwords ) { unsigned int align ; align = rs6000_function_arg_boundary ( mode , type ) / PARM_BOUNDARY - 1 ; return nwords + ( - ( rs6000_parm_offset ( ) + nwords ) & align ) ; } </s>

For a function parm of MODE and TYPE , return the starting word in the parameter area . NWORDS of the parameter area are already used .


<s> EVT X86TargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return Subtarget -> hasAVX512 ( ) ? MVT :: i1 : MVT :: i8 ; if ( Subtarget -> hasAVX512 ( ) ) switch ( VT . getVectorNumElements ( ) ) { case 8 : return MVT :: v8i1 ; case 16 : return MVT :: v16i1 ; } return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


Return the DataLayout associated with the module this SCEV instance is operating on .


<s> std :: pair < unsigned , const TargetRegisterClass * > SparcTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , & SP :: IntRegsRegClass ) ; } } else if ( ! Constraint . empty ( ) && Constraint . size ( ) <= 5 && Constraint [ 0 ] == '{' && * ( Constraint . end ( ) - 1 ) == '}' ) { StringRef name ( Constraint . data ( ) + 1 , Constraint . size ( ) - 2 ) ; uint64_t intVal = 0 ; if ( name . substr ( 0 , 1 ) . equals ( "r" ) && ! name . substr ( 1 ) . getAsInteger ( 10 , intVal ) && intVal <= 31 ) { const char regTypes [ ] = { 'g' , 'o' , 'l' , 'i' } ; char regType = regTypes [ intVal / 8 ] ; char regIdx = '0' + ( intVal % 8 ) ; char tmp [ ] = { '{' , regType , regIdx , '}' , 0 } ; std :: string newConstraint = std :: string ( tmp ) ; return TargetLowering :: getRegForInlineAsmConstraint ( TRI , newConstraint , VT ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s>
const
char
*
output_adjust_stack_and_probe
(
rtx
reg
)
{
static
int
labelno
=
0
;
char
loop_lab
[
32
]
;
rtx
xops
[
2
]
;
ASM_GENERATE_INTERNAL_LABEL
(
loop_lab
,
"LPSRL"
,
labelno
++
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
loop_lab
)
;
xops
[
0
]
=
stack_pointer_rtx
;
xops
[
1
]
=
GEN_INT
(
PROBE_INTERVAL
)
;
output_asm_insn
(
"sub%z0\t{%1, %0|%0, %1}"
,
xops
)
;
xops
[
1
]
=
const0_rtx
;
output_asm_insn
(
"or%z0\t{%1, (%0)|DWORD PTR [%0], %1}"
,
xops
)
;
xops
[
0
]
=
stack_pointer_rtx
;
xops
[
1
]
=
reg
;
output_asm_insn
(
"cmp%z0\t{%1, %0|%0, %1}"
,
xops
)
;
fputs
(
"\tjne\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
loop_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
return
""
;
}
</s>

Adjust the stack pointer up to REG while probing it .


<s> static section * rs6000_xcoff_select_rtx_section ( machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED ) { if ( ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( x , mode ) ) return toc_section ; else return read_only_private_data_section ; } </s>

Select section for constant in constant pool . On RS/6000 , all constants are in the private read-only data area . However , if this is being placed in the TOC it must be output as a toc entry .


<s> static int dispatch_function_versions ( tree dispatch_decl , void * fndecls_p , basic_block * empty_bb ) { tree default_decl ; gimple ifunc_cpu_init_stmt ; gimple_seq gseq ; int ix ; tree ele ; vec < tree > * fndecls ; unsigned int num_versions = 0 ; unsigned int actual_versions = 0 ; unsigned int i ; struct _function_version_info { tree version_decl ; tree predicate_chain ; unsigned int dispatch_priority ; } * function_version_info ; gcc_assert ( dispatch_decl != NULL && fndecls_p != NULL && empty_bb != NULL ) ; fndecls = static_cast < vec < tree > * > ( fndecls_p ) ; num_versions = fndecls -> length ( ) ; gcc_assert ( num_versions >= 2 ) ; function_version_info = ( struct _function_version_info * ) XNEWVEC ( struct _function_version_info , ( num_versions - 1 ) ) ; default_decl = ( * fndecls ) [ 0 ] ; push_cfun ( DECL_STRUCT_FUNCTION ( dispatch_decl ) ) ; gseq = bb_seq ( * empty_bb ) ; ifunc_cpu_init_stmt = gimple_build_call_vec ( ix86_builtins [ ( int ) IX86_BUILTIN_CPU_INIT ] , vNULL ) ; gimple_seq_add_stmt ( & gseq , ifunc_cpu_init_stmt ) ; gimple_set_bb ( ifunc_cpu_init_stmt , * empty_bb ) ; set_bb_seq ( * empty_bb , gseq ) ; pop_cfun ( ) ; for ( ix = 1 ; fndecls -> iterate ( ix , & ele ) ; ++ ix ) { tree version_decl = ele ; tree predicate_chain = NULL_TREE ; unsigned int priority ; priority = get_builtin_code_for_version ( version_decl , & predicate_chain ) ; if ( predicate_chain == NULL_TREE ) continue ; function_version_info [ actual_versions ] . version_decl = version_decl ; function_version_info [ actual_versions ] . predicate_chain = predicate_chain ; function_version_info [ actual_versions ] . dispatch_priority = priority ; actual_versions ++ ; } qsort ( function_version_info , actual_versions , sizeof ( struct _function_version_info ) , feature_compare ) ; for ( i = 0 ; i < actual_versions ; ++ i ) * empty_bb = add_condition_to_bb ( dispatch_decl , function_version_info [ i ] . version_decl , function_version_info [ i ] . predicate_chain , * empty_bb ) ; * empty_bb = add_condition_to_bb ( dispatch_decl , default_decl , NULL , * empty_bb ) ; free ( function_version_info ) ; return 0 ; } </s>

This function generates the dispatch function for multi-versioned functions . DISPATCH_DECL is the function which will contain the dispatch logic . FNDECLS are the function choices for dispatch , and is a tree chain . EMPTY_BB is the basic block pointer in DISPATCH_DECL in which the dispatch code is generated .


<s> static bool rs6000_reg_live_or_pic_offset_p ( int reg ) { if ( reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ! TARGET_SINGLE_PIC_BASE ) { if ( TARGET_TOC && TARGET_MINIMAL_TOC && ( crtl -> calls_eh_return || df_regs_ever_live_p ( reg ) || get_pool_size ( ) ) ) return true ; if ( ( DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN ) && flag_pic ) return true ; } return ( ( crtl -> calls_eh_return || df_regs_ever_live_p ( reg ) ) && ! call_used_regs [ reg ] ) ; } </s>

Determine whether the gp REG is really used .


<s> static int ix86_widen_mult_cost ( const struct processor_costs * cost , enum machine_mode mode , bool uns_p ) { gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) ; int extra_cost = 0 ; int basic_cost = 0 ; switch ( mode ) { case V8HImode : case V16HImode : if ( ! uns_p || mode == V16HImode ) extra_cost = cost -> sse_op * 2 ; basic_cost = cost -> mulss * 2 + cost -> sse_op * 4 ; break ; case V4SImode : case V8SImode : basic_cost = cost -> mulss * 2 + cost -> sse_op * 2 ; break ; case V2DImode : if ( ! TARGET_SSE4_1 && ! uns_p ) extra_cost = ( cost -> mulss + cost -> addss + cost -> sse_op ) * 4 + cost -> sse_op * 2 ; case V4DImode : basic_cost = cost -> mulss * 2 + cost -> sse_op * 4 ; break ; default : gcc_unreachable ( ) ; } return ix86_vec_cost ( mode , basic_cost + extra_cost ) ; } </s>

Return cost of vec_widen_ < s > mult_hi/lo_ < mode > , vec_widen_ < s > mul_hi/lo_ < mode > is only available for VI124_AVX2 .


"instruction requires a CPU feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


"Cannot store this register to stack slot!"

Store the specified register of the given register class to the specified stack frame index .


<s> static rtx aarch64_strip_shift ( rtx x ) { rtx op = x ; if ( ( GET_CODE ( op ) == ASHIFT || GET_CODE ( op ) == ASHIFTRT || GET_CODE ( op ) == LSHIFTRT || GET_CODE ( op ) == ROTATERT || GET_CODE ( op ) == ROTATE ) && CONST_INT_P ( XEXP ( op , 1 ) ) ) return XEXP ( op , 0 ) ; if ( GET_CODE ( op ) == MULT && CONST_INT_P ( XEXP ( op , 1 ) ) && ( ( unsigned ) exact_log2 ( INTVAL ( XEXP ( op , 1 ) ) ) ) < 64 ) return XEXP ( op , 0 ) ; return x ; } </s>

Helper function for rtx cost calculation . Strip a shift expression from X . Returns the inner operand if successful , or the original expression on failure .


<s> const char * nvptx_section_for_decl ( const_tree decl ) { bool is_const = ( CONSTANT_CLASS_P ( decl ) || TREE_CODE ( decl ) == CONST_DECL || TREE_READONLY ( decl ) ) ; if ( is_const ) return ".const" ; return ".global" ; } </s>

Determine whether DECL goes into .const or .global .


<s> BitVector VideoCore4RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; Reserved . set ( VideoCore4 :: SP ) ; Reserved . set ( VideoCore4 :: PC ) ; Reserved . set ( VideoCore4 :: GP ) ; Reserved . set ( VideoCore4 :: ESP ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( VideoCore4 :: R6 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> TargetPassConfig * DLXTargetMachine :: createPassConfig ( PassManagerBase & PassManager ) { return new DLXPassConfig ( * this , & PassManager ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> TargetLowering :: AtomicExpansionKind SITargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * RMW ) const { switch ( RMW -> getOperation ( ) ) { case AtomicRMWInst :: FAdd : { Type * Ty = RMW -> getType ( ) ; if ( Ty -> isHalfTy ( ) ) return AtomicExpansionKind :: None ; if ( ! Ty -> isFloatTy ( ) ) return AtomicExpansionKind :: CmpXChg ; unsigned AS = RMW -> getPointerAddressSpace ( ) ; if ( AS == AMDGPUAS :: GLOBAL_ADDRESS && Subtarget -> hasAtomicFaddInsts ( ) ) { return RMW -> use_empty ( ) ? AtomicExpansionKind :: None : AtomicExpansionKind :: CmpXChg ; } return ( AS == AMDGPUAS :: LOCAL_ADDRESS && Subtarget -> hasLDSFPAtomics ( ) ) ? AtomicExpansionKind :: None : AtomicExpansionKind :: CmpXChg ; } default : break ; } return AMDGPUTargetLowering :: shouldExpandAtomicRMWInIR ( RMW ) ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> iterator begin ( ) { return Blocks . rbegin ( ) ; } </s>


<s>
SDValue
SystemZTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
return
SDValue
(
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

SystemZ
SystemZ
ISD::BR_CC
ISD::SELECT_CC
ISD::GlobalAddress
ISD::JumpTable
ISD::ConstantPool
"Should not custom lower this!"


<s> unsigned GCNSubtarget :: computeOccupancy ( const MachineFunction & MF , unsigned LDSSize , unsigned NumSGPRs , unsigned NumVGPRs ) const { unsigned Occupancy = std :: min ( getMaxWavesPerEU ( ) , getOccupancyWithLocalMemSize ( LDSSize , MF . getFunction ( ) ) ) ; if ( NumSGPRs ) Occupancy = std :: min ( Occupancy , getOccupancyWithNumSGPRs ( NumSGPRs ) ) ; if ( NumVGPRs ) Occupancy = std :: min ( Occupancy , getOccupancyWithNumVGPRs ( NumVGPRs ) ) ; return Occupancy ; } </s>

Return occupancy for the given function .


<s> SDNode * PPCDAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * PPCSubTarget -> getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; const Module * M = MF -> getFunction ( ) -> getParent ( ) ; DebugLoc dl ; if ( PPCLowering -> getPointerTy ( ) == MVT :: i32 ) { if ( PPCSubTarget -> isTargetELF ( ) ) { GlobalBaseReg = PPC :: R30 ; if ( M -> getPICLevel ( ) == PICLevel :: Small ) { BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MoveGOTtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; MF -> getInfo < PPCFunctionInfo > ( ) -> setUsesPICBase ( true ) ; } else { BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; unsigned TempReg = RegInfo -> createVirtualRegister ( & PPC :: GPRCRegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: UpdateGBR ) ) . addReg ( GlobalBaseReg ) . addReg ( TempReg , RegState :: Define ) . addReg ( GlobalBaseReg ) ; MF -> getInfo < PPCFunctionInfo > ( ) -> setUsesPICBase ( true ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: GPRC_NOR0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: G8RC_NOX0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR8 ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR8 ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , PPCLowering -> getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

PowerPC PPC PPC PPC MVT::i32 PPC PPC::R30 PPC::MoveGOTtoLR PPC::MFLR PPC PPC::MovePCtoLR PPC::MFLR PPC::GPRCRegClass PPC::UpdateGBR PPC PPC::GPRC_NOR0RegClass PPC::MovePCtoLR PPC::MFLR PPC::G8RC_NOX0RegClass PPC::MovePCtoLR8 PPC::MFLR8 PPC


<s> unsigned char X86Subtarget :: classifyLocalReference ( const GlobalValue * GV ) const { if ( is64Bit ( ) ) return X86II :: MO_NO_FLAG ; if ( ! isPositionIndependent ( ) ) return X86II :: MO_NO_FLAG ; if ( isTargetCOFF ( ) ) return X86II :: MO_NO_FLAG ; if ( isTargetDarwin ( ) ) { if ( GV && ( GV -> isDeclarationForLinker ( ) || GV -> hasCommonLinkage ( ) ) ) return X86II :: MO_DARWIN_NONLAZY_PIC_BASE ; return X86II :: MO_PIC_BASE_OFFSET ; } return X86II :: MO_GOTOFF ; } </s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s> static int avr_OS_main_function_p ( tree func ) { return avr_lookup_function_attribute1 ( func , "OS_main" ) ; } </s>

Return nonzero if FUNC is an OS_main function .


<s> SDValue X86TargetLowering :: getRecipEstimate ( SDValue Op , SelectionDAG & DAG , int Enabled , int & RefinementSteps ) const { EVT VT = Op . getValueType ( ) ; if ( ( VT == MVT :: f32 && Subtarget . hasSSE1 ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasSSE1 ( ) ) || ( VT == MVT :: v8f32 && Subtarget . hasAVX ( ) ) || ( VT == MVT :: v16f32 && Subtarget . useAVX512Regs ( ) ) ) { if ( VT == MVT :: f32 && Enabled == ReciprocalEstimate :: Unspecified ) return SDValue ( ) ; if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = 1 ; unsigned Opcode = VT == MVT :: v16f32 ? X86ISD :: RCP14 : X86ISD :: FRCP ; return DAG . getNode ( Opcode , SDLoc ( Op ) , VT , Op ) ; } return SDValue ( ) ; } </s>

Return a reciprocal estimate value for the input operand .


<s> static rtx arm_function_value ( const_tree type , const_tree func , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode mode ; int unsignedp ATTRIBUTE_UNUSED ; rtx r ATTRIBUTE_UNUSED ; mode = TYPE_MODE ( type ) ; if ( TARGET_AAPCS_BASED ) return aapcs_allocate_return_reg ( mode , type , func ) ; if ( INTEGRAL_TYPE_P ( type ) ) mode = arm_promote_function_mode ( type , mode , & unsignedp , func , 1 ) ; if ( arm_return_in_msb ( type ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; if ( size % UNITS_PER_WORD != 0 ) { size += UNITS_PER_WORD - size % UNITS_PER_WORD ; mode = int_mode_for_size ( size * BITS_PER_UNIT , 0 ) . require ( ) ; } } return arm_libcall_value_1 ( mode ) ; } </s>

Define how to find the value returned by a function .


"Unrecognized Hexagon processor version"

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> unsigned getMask ( ) const { return Mask ; } </s>


<s> static bool mep_reg_set_p ( rtx reg , rtx insn ) { if ( INSN_P ( insn ) ) { if ( FIND_REG_INC_NOTE ( insn , reg ) ) return true ; insn = PATTERN ( insn ) ; } if ( GET_CODE ( insn ) == SET && GET_CODE ( XEXP ( insn , 0 ) ) == REG && GET_CODE ( XEXP ( insn , 1 ) ) == REG && REGNO ( XEXP ( insn , 0 ) ) == REGNO ( XEXP ( insn , 1 ) ) ) return false ; return set_of ( reg , insn ) != NULL_RTX ; } </s>


<s> rtx aarch64_mask_from_zextract_ops ( rtx width , rtx pos ) { gcc_assert ( CONST_INT_P ( width ) ) ; gcc_assert ( CONST_INT_P ( pos ) ) ; unsigned HOST_WIDE_INT mask = ( ( unsigned HOST_WIDE_INT ) 1 << UINTVAL ( width ) ) - 1 ; return GEN_INT ( mask << UINTVAL ( pos ) ) ; } </s>

Return the bitmask CONST_INT to select the bits required by a zero extract operation of width WIDTH at bit position POS .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; bool Changed = false ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( MF , B ) ) Changed = true ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


Output a library call to a function called FNAME that has been arranged to be local to any dso .


<s> static void build_v_base ( function_builder & b , const char * signature , const function_group_info & group , bool force_direct_overloads = false ) { build_32_64 ( b , signature , group , MODE_u32base , MODE_u64base , force_direct_overloads ) ; } </s>

For every type and predicate combination in GROUP , add a function that takes a vector base address and no displacement . The vector base has the same element size as the first type suffix . The other arguments are as for build_all .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . setPreservesAll ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static int find_unused_clobbered_reg ( void ) { int i ; for ( i = 0 ; i < 6 ; i ++ ) if ( ! df_regs_ever_live_p ( i ) ) return i ; return 0 ; } </s>

Find first call clobbered register unsused in a function . This could be used as base register in a leaf function or for holding the return address before epilogue .


<s> static bool riscv_warn_func_return ( tree decl ) { return ! riscv_naked_function_p ( decl ) ; } </s>


<s> void RISCVTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { if ( Constraint . length ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'I' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) { uint64_t CVal = C -> getSExtValue ( ) ; if ( isInt < 12 > ( CVal ) ) Ops . push_back ( DAG . getTargetConstant ( CVal , SDLoc ( Op ) , Subtarget . getXLenVT ( ) ) ) ; } return ; case 'J' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( C -> getZExtValue ( ) == 0 ) Ops . push_back ( DAG . getTargetConstant ( 0 , SDLoc ( Op ) , Subtarget . getXLenVT ( ) ) ) ; return ; case 'K' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) { uint64_t CVal = C -> getZExtValue ( ) ; if ( isUInt < 5 > ( CVal ) ) Ops . push_back ( DAG . getTargetConstant ( CVal , SDLoc ( Op ) , Subtarget . getXLenVT ( ) ) ) ; } return ; default : break ; } } TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; } </s>

Lower the specified operand into the Ops vector .


<s> static bool legitimate_reload_fp_constant_p ( rtx op ) { if ( TARGET_Z196 && GET_CODE ( op ) == CONST_DOUBLE && s390_float_const_zero_p ( op ) ) return true ; return false ; } </s>

Returns true if the constant value OP is a legitimate fp operand during and after reload . This function accepts all constants which can be loaded directly into an FPR .


<s>
unsigned
getSubReg
(
)
const
{
assert
(
isReg
(
)
&&
"Wrong CountValue accessor"
)
;
return
Contents
.
R
.
Sub
;
}
</s>

Returns the physical register number of sub-register `` Index '' for physical register RegNo .


<s>
bool
FPS
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
bool
FPIsUsed
=
false
;
assert
(
X86
::
FP6
==
X86
::
FP0
+
6
&&
"Register enums aren't sorted right!"
)
;
for
(
unsigned
i
=
0
;
i
<=
6
;
++
i
)
if
(
MF
.
getRegInfo
(
)
.
isPhysRegUsed
(
X86
::
FP0
+
i
)
)
{
FPIsUsed
=
true
;
break
;
}
if
(
!
FPIsUsed
)
return
false
;
Bundles
=
&
getAnalysis
<
EdgeBundles
>
(
)
;
TII
=
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
bundleCFG
(
MF
)
;
StackTop
=
0
;
SmallPtrSet
<
MachineBasicBlock
*
,
8
>
Processed
;
MachineBasicBlock
*
Entry
=
MF
.
begin
(
)
;
bool
Changed
=
false
;
for
(
MachineBasicBlock
*
BB
:
depth_first_ext
(
Entry
,
Processed
)
)
Changed
|=
processBasicBlock
(
MF
,
*
BB
)
;
if
(
MF
.
size
(
)
!=
Processed
.
size
(
)
)
for
(
MachineFunction
::
iterator
BB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
BB
!=
E
;
++
BB
)
if
(
Processed
.
insert
(
BB
)
)
Changed
|=
processBasicBlock
(
MF
,
*
BB
)
;
LiveBundles
.
clear
(
)
;
return
Changed
;
}
</s>


<s>
void
ARCRegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected"
)
;
MachineInstr
&
MI
=
*
II
;
MachineOperand
&
FrameOp
=
MI
.
getOperand
(
FIOperandNum
)
;
int
FrameIndex
=
FrameOp
.
getIndex
(
)
;
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
const
ARCInstrInfo
&
TII
=
*
MF
.
getSubtarget
<
ARCSubtarget
>
(
)
.
getInstrInfo
(
)
;
const
ARCFrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
int
Offset
=
MF
.
getFrameInfo
(
)
.
getObjectOffset
(
FrameIndex
)
;
int
ObjSize
=
MF
.
getFrameInfo
(
)
.
getObjectSize
(
FrameIndex
)
;
int
StackSize
=
MF
.
getFrameInfo
(
)
.
getStackSize
(
)
;
int
LocalFrameSize
=
MF
.
getFrameInfo
(
)
.
getLocalFrameSize
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"\nFunction         : "
<<
MF
.
getName
(
)
<<
"\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"<--------->\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
MI
<<
"\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"FrameIndex         : "
<<
FrameIndex
<<
"\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ObjSize            : "
<<
ObjSize
<<
"\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"FrameOffset        : "
<<
Offset
<<
"\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"StackSize          : "
<<
StackSize
<<
"\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"LocalFrameSize     : "
<<
LocalFrameSize
<<
"\n"
)
;
(
void
)
LocalFrameSize
;
if
(
MI
.
isDebugValue
(
)
)
{
unsigned
FrameReg
=
getFrameRegister
(
MF
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
)
;
return
;
}
Offset
+=
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Offset             : "
<<
Offset
<<
"\n"
<<
"<--------->\n"
)
;
unsigned
Reg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
assert
(
ARC
::
GPR32RegClass
.
contains
(
Reg
)
&&
"Unexpected register operand"
)
;
if
(
!
TFI
->
hasFP
(
MF
)
)
{
Offset
=
StackSize
+
Offset
;
if
(
FrameIndex
>=
0
)
assert
(
(
Offset
>=
0
&&
Offset
<
StackSize
)
&&
"SP Offset not in bounds."
)
;
}
else
{
if
(
FrameIndex
>=
0
)
{
assert
(
(
Offset
<
0
&&
Offset
<=
StackSize
)
&&
"FP Offset not in bounds."
)
;
}
}
ReplaceFrameIndex
(
II
,
TII
,
Reg
,
getFrameRegister
(
MF
)
,
Offset
,
StackSize
,
ObjSize
,
RS
,
SPAdj
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .

ARC
ARC
0
"Unexpected"
ARC
ARC
ARC
"\nFunction         : "
"\n"
"<--------->\n"
"\n"
"FrameIndex         : "
"\n"
"ObjSize            : "
"\n"
"FrameOffset        : "
"\n"
"StackSize          : "
"\n"
"LocalFrameSize     : "
"\n"
1
1
"Offset             : "
"\n"
"<--------->\n"
0
ARC::GPR32RegClass
"Unexpected register operand"
0
0
"SP Offset not in bounds."
0
0
"FP Offset not in bounds."


<s> bool X86LowerTileCopy :: runOnMachineFunction ( MachineFunction & MF ) { const X86Subtarget & ST = MF . getSubtarget < X86Subtarget > ( ) ; const X86InstrInfo * TII = ST . getInstrInfo ( ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineBasicBlock :: iterator MII = MBB . begin ( ) , MIE = MBB . end ( ) ; MII != MIE ; ) { MachineInstr & MI = * MII ++ ; if ( ! MI . isCopy ( ) ) continue ; MachineOperand & DstMO = MI . getOperand ( 0 ) ; MachineOperand & SrcMO = MI . getOperand ( 1 ) ; Register SrcReg = SrcMO . getReg ( ) ; Register DstReg = DstMO . getReg ( ) ; if ( ! X86 :: TILERegClass . contains ( DstReg , SrcReg ) ) continue ; const TargetRegisterInfo * TRI = ST . getRegisterInfo ( ) ; unsigned Size = TRI -> getSpillSize ( X86 :: TILERegClass ) ; Align Alignment = TRI -> getSpillAlign ( X86 :: TILERegClass ) ; int TileSS = MF . getFrameInfo ( ) . CreateSpillStackObject ( Size , Alignment ) ; Size = TRI -> getSpillSize ( X86 :: GR64RegClass ) ; Alignment = TRI -> getSpillAlign ( X86 :: GR64RegClass ) ; int StrideSS = MF . getFrameInfo ( ) . CreateSpillStackObject ( Size , Alignment ) ; Register GR64Cand = X86 :: RAX ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( MBB , MI , DL , TII -> get ( X86 :: IMPLICIT_DEF ) , GR64Cand ) ; addFrameReference ( BuildMI ( MBB , MI , DL , TII -> get ( X86 :: MOV64mr ) ) , StrideSS ) . addReg ( GR64Cand ) ; BuildMI ( MBB , MI , DL , TII -> get ( X86 :: MOV64ri ) , GR64Cand ) . addImm ( 64 ) ; unsigned Opc = X86 :: TILESTORED ; MachineInstr * NewMI = addFrameReference ( BuildMI ( MBB , MI , DL , TII -> get ( Opc ) ) , TileSS ) . addReg ( SrcReg , getKillRegState ( SrcMO . isKill ( ) ) ) ; MachineOperand & MO = NewMI -> getOperand ( 2 ) ; MO . setReg ( GR64Cand ) ; MO . setIsKill ( true ) ; Opc = X86 :: TILELOADD ; NewMI = addFrameReference ( BuildMI ( MBB , MI , DL , TII -> get ( Opc ) , DstReg ) , TileSS ) ; addFrameReference ( BuildMI ( MBB , MI , DL , TII -> get ( X86 :: MOV64rm ) , GR64Cand ) , StrideSS ) ; MI . eraseFromParent ( ) ; Changed = true ; } } return Changed ; } </s>


<s> static const char * getOpcodeName ( unsigned Opcode ) { const char * Name = "<unknown>" ; switch ( Opcode ) { default : break ; case AArch64 :: B : Name = "AArch64::B" ; break ; case AArch64 :: Bcc : Name = "AArch64::Bcc" ; break ; case AArch64 :: BR : Name = "AArch64::BR" ; break ; case AArch64 :: BRAA : Name = "AArch64::BRAA" ; break ; case AArch64 :: BRAAZ : Name = "AArch64::BRAAZ" ; break ; case AArch64 :: BRAB : Name = "AArch64::BRAB" ; break ; case AArch64 :: BRABZ : Name = "AArch64::BRABZ" ; break ; case AArch64 :: BL : Name = "AArch64::BL" ; break ; case AArch64 :: BLR : Name = "AArch64::BLR" ; break ; case AArch64 :: BLRAA : Name = "AArch64::BLRAA" ; break ; case AArch64 :: BLRAAZ : Name = "AArch64::BLRAAZ" ; break ; case AArch64 :: BLRAB : Name = "AArch64::BLRAB" ; break ; case AArch64 :: BLRABZ : Name = "AArch64::BLRABZ" ; break ; case AArch64 :: CBZW : Name = "AArch64::CBZW" ; break ; case AArch64 :: CBZX : Name = "AArch64::CBZX" ; break ; case AArch64 :: CBNZW : Name = "AArch64::CBNZW" ; break ; case AArch64 :: CBNZX : Name = "AArch64::CBNZX" ; break ; case AArch64 :: CCMPWr : Name = "AArch64::CCMPWr" ; break ; case AArch64 :: CCMPXr : Name = "AArch64::CCMPXr" ; break ; case AArch64 :: G_FCMP : Name = "AArch64::G_FCMP" ; break ; case AArch64 :: G_ICMP : Name = "AArch64::G_ICMP" ; break ; case AArch64 :: TBZW : Name = "AArch64::TBZW" ; break ; case AArch64 :: TBZX : Name = "AArch64::TBZX" ; break ; case AArch64 :: TBNZW : Name = "AArch64::TBNZW" ; break ; case AArch64 :: TBNZX : Name = "AArch64::TBNZX" ; break ; case AArch64 :: RET : Name = "AArch64::RET" ; break ; case AArch64 :: RETAA : Name = "AArch64::RETAA" ; break ; case AArch64 :: RETAB : Name = "AArch64::RETAB" ; break ; case AArch64 :: SVC : Name = "AArch64::SVC" ; break ; } return Name ; } </s>

Return a string representation for an opcode .


<s> poly_int64 pdp11_push_rounding ( poly_int64 bytes ) { return ( bytes + 1 ) & ~ 1 ; } </s>

Implement PUSH_ROUNDING . On the pdp11 , the stack is on an even boundary .


<s>
SDNode
*
DCPU16DAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
DebugLoc
dl
=
Node
->
getDebugLoc
(
)
;
DEBUG
(
errs
(
)
<<
"Selecting: "
)
;
DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
DEBUG
(
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
return
;
}
switch
(
Node
->
getOpcode
(
)
)
{
default
:
break
;
case
ISD
::
FrameIndex
:
{
assert
(
Node
->
getValueType
(
0
)
==
MVT
::
i16
)
;
int
FI
=
cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
MVT
::
i16
)
;
if
(
Node
->
hasOneUse
(
)
)
return
CurDAG
->
SelectNodeTo
(
Node
,
DCPU16
::
ADD16ri
,
MVT
::
i16
,
TFI
,
CurDAG
->
getTargetConstant
(
0
,
MVT
::
i16
)
)
;
return
CurDAG
->
getMachineNode
(
DCPU16
::
ADD16ri
,
dl
,
MVT
::
i16
,
TFI
,
CurDAG
->
getTargetConstant
(
0
,
MVT
::
i16
)
)
;
}
}
SDNode
*
ResNode
=
SelectCode
(
Node
)
;
DEBUG
(
errs
(
)
<<
"=> "
)
;
if
(
ResNode
==
||
ResNode
==
Node
)
DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
else
DEBUG
(
ResNode
->
dump
(
CurDAG
)
)
;
DEBUG
(
errs
(
)
<<
"\n"
)
;
return
ResNode
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> bool MipsTargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const MipsSubtarget & Subtarget = TM . getSubtarget < MipsSubtarget > ( ) ; if ( Subtarget . isLinux ( ) ) return false ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ; if ( Kind . isMergeable1ByteCString ( ) ) return false ; Type * Ty = GV -> getType ( ) -> getElementType ( ) ; return IsInSmallSection ( TM . getTargetData ( ) -> getTypeAllocSize ( Ty ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> void bpf_print_operand ( FILE * file , rtx op , int code ATTRIBUTE_UNUSED ) { switch ( GET_CODE ( op ) ) { case REG : fprintf ( file , "%s" , reg_names [ REGNO ( op ) ] ) ; break ; case MEM : output_address ( GET_MODE ( op ) , XEXP ( op , 0 ) ) ; break ; case CONST_DOUBLE : if ( GET_MODE ( op ) == VOIDmode ) { if ( CONST_DOUBLE_HIGH ( op ) ) fprintf ( file , HOST_WIDE_INT_PRINT_DOUBLE_HEX , CONST_DOUBLE_HIGH ( op ) , CONST_DOUBLE_LOW ( op ) ) ; else if ( CONST_DOUBLE_LOW ( op ) < 0 ) fprintf ( file , HOST_WIDE_INT_PRINT_HEX , CONST_DOUBLE_LOW ( op ) ) ; else fprintf ( file , HOST_WIDE_INT_PRINT_DEC , CONST_DOUBLE_LOW ( op ) ) ; } else { long vals [ 2 ] ; real_to_target ( vals , CONST_DOUBLE_REAL_VALUE ( op ) , GET_MODE ( op ) ) ; vals [ 0 ] &= 0xffffffff ; vals [ 1 ] &= 0xffffffff ; if ( GET_MODE ( op ) == SFmode ) fprintf ( file , "0x%08lx" , vals [ 0 ] ) ; else if ( GET_MODE ( op ) == DFmode ) { if ( WORDS_BIG_ENDIAN ) fprintf ( file , "0x%08lx%08lx" , vals [ 0 ] , vals [ 1 ] ) ; else fprintf ( file , "0x%08lx%08lx" , vals [ 1 ] , vals [ 0 ] ) ; } else gcc_unreachable ( ) ; } break ; default : output_addr_const ( file , op ) ; } } </s>

Print an instruction operand . This function is called in the macro PRINT_OPERAND defined in bpf.h


<s> void MipsPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; addPass ( createAtomicExpandPass ( & getMipsTargetMachine ( ) ) ) ; if ( getMipsSubtarget ( ) . os16 ( ) ) addPass ( createMipsOs16Pass ( getMipsTargetMachine ( ) ) ) ; if ( getMipsSubtarget ( ) . inMips16HardFloat ( ) ) addPass ( createMips16HardFloatPass ( getMipsTargetMachine ( ) ) ) ; if ( DirectToNaCl ) { addPass ( createExpandVarArgsPass ( ) ) ; addPass ( createExpandByValPass ( ) ) ; addPass ( createAddPNaClExternalDeclsPass ( ) ) ; addPass ( createResolvePNaClIntrinsicsPass ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips


<s> virtual void EmitInstruction ( const MachineInstr * MI ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; printInstruction ( MI , OS ) ; OutStreamer . EmitRawText ( OS . str ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> SDValue TPCTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CC , bool Flag , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & Vec , const SDLoc & Loc , SelectionDAG & DAG ) const { return DAG . getNode ( TPCISD :: HALT , Loc , MVT :: Other , Chain ) ; } </s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .

TPC TPC ISD::OutputArg TPCISD::HALT MVT::Other


<s> const uint16_t * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const uint16_t * RegList = ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ; if ( ! MF ) return RegList ; const Function * F = MF -> getFunction ( ) ; if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F -> hasFnAttribute ( "interrupt" ) ) { if ( STI . isMClass ( ) ) { return CSR_AAPCS_SaveList ; } else if ( F -> getFnAttribute ( "interrupt" ) . getValueAsString ( ) == "FIQ" ) { return CSR_FIQ_SaveList ; } else { return CSR_GenericInt_SaveList ; } } return RegList ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 Avoid Store Forwarding Blocks"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
StringRef
getPassName
(
)
const
override
{
return
"M68k Assembly Printer"
;
}
</s>


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesAll ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> TargetLowering :: ConstraintType SystemZTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return C_RegisterClass ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> static bool cortex_a9_sched_adjust_cost ( rtx_insn * insn , rtx link , rtx_insn * dep , int * cost ) { switch ( REG_NOTE_KIND ( link ) ) { case REG_DEP_ANTI : * cost = 0 ; return false ; case REG_DEP_TRUE : case REG_DEP_OUTPUT : if ( recog_memoized ( insn ) >= 0 && recog_memoized ( dep ) >= 0 ) { if ( GET_CODE ( PATTERN ( insn ) ) == SET ) { if ( GET_MODE_CLASS ( GET_MODE ( SET_DEST ( PATTERN ( insn ) ) ) ) == MODE_FLOAT || GET_MODE_CLASS ( GET_MODE ( SET_SRC ( PATTERN ( insn ) ) ) ) == MODE_FLOAT ) { enum attr_type attr_type_insn = get_attr_type ( insn ) ; enum attr_type attr_type_dep = get_attr_type ( dep ) ; if ( REG_P ( SET_DEST ( PATTERN ( insn ) ) ) && REG_P ( SET_DEST ( PATTERN ( dep ) ) ) && reg_overlap_mentioned_p ( SET_DEST ( PATTERN ( insn ) ) , SET_DEST ( PATTERN ( dep ) ) ) ) { if ( ( attr_type_insn == TYPE_FMACS || attr_type_insn == TYPE_FMACD ) && ( attr_type_dep == TYPE_FMACS || attr_type_dep == TYPE_FMACD ) ) { if ( REG_NOTE_KIND ( link ) == REG_DEP_OUTPUT ) * cost = insn_default_latency ( dep ) - 3 ; else * cost = insn_default_latency ( dep ) ; return false ; } else { if ( REG_NOTE_KIND ( link ) == REG_DEP_OUTPUT ) * cost = insn_default_latency ( dep ) + 1 ; else * cost = insn_default_latency ( dep ) ; } return false ; } } } } break ; default : gcc_unreachable ( ) ; } return true ; } </s>


<s> void altivec_expand_stvx_be ( rtx op0 , rtx op1 , machine_mode mode , unsigned unspec ) { rtx tmp = gen_reg_rtx ( mode ) ; rtx store = gen_rtx_SET ( op0 , tmp ) ; rtx stvx = gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , const0_rtx ) , unspec ) ; rtx par = gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , store , stvx ) ) ; rtx sel = swap_selector_for_mode ( mode ) ; rtx vperm ; gcc_assert ( REG_P ( op1 ) ) ; vperm = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , op1 , op1 , sel ) , UNSPEC_VPERM ) ; emit_insn ( gen_rtx_SET ( tmp , vperm ) ) ; emit_insn ( par ) ; } </s>

Generate code for a `` stvx '' or `` stvxl '' built-in for a little endian target with -maltivec=be specified . Issue the store preceded by an element-reversing permute .


<s> unsigned GCNHazardRecognizer :: PreEmitNoops ( MachineInstr * MI ) { IsHazardRecognizerMode = true ; CurrCycleInstr = MI ; unsigned W = PreEmitNoopsCommon ( MI ) ; CurrCycleInstr = nullptr ; return W ; } </s>

PreEmitNoops - This callback is invoked prior to emitting an instruction .


<s> BitVector TeakRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( Teak :: SP ) ; Reserved . set ( Teak :: PC ) ; Reserved . set ( Teak :: R7 ) ; Reserved . set ( Teak :: LC ) ; Reserved . set ( Teak :: EXT0 ) ; Reserved . set ( Teak :: EXT1 ) ; Reserved . set ( Teak :: EXT2 ) ; Reserved . set ( Teak :: EXT3 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static int zero_all_st_registers ( HARD_REG_SET need_zeroed_hardregs ) { if ( ! ( TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ) ) return 0 ; unsigned int num_of_st = 0 ; for ( unsigned int regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ( STACK_REGNO_P ( regno ) || MMX_REGNO_P ( regno ) ) && TEST_HARD_REG_BIT ( need_zeroed_hardregs , regno ) ) { num_of_st ++ ; break ; } if ( num_of_st == 0 ) return 0 ; bool return_with_x87 = false ; return_with_x87 = ( crtl -> return_rtx && ( STACK_REG_P ( crtl -> return_rtx ) ) ) ; bool complex_return = false ; complex_return = ( crtl -> return_rtx && COMPLEX_MODE_P ( GET_MODE ( crtl -> return_rtx ) ) ) ; if ( return_with_x87 ) if ( complex_return ) num_of_st = 6 ; else num_of_st = 7 ; else num_of_st = 8 ; rtx st_reg = gen_rtx_REG ( XFmode , FIRST_STACK_REG ) ; for ( unsigned int i = 0 ; i < num_of_st ; i ++ ) emit_insn ( gen_rtx_SET ( st_reg , CONST0_RTX ( XFmode ) ) ) ; for ( unsigned int i = 0 ; i < num_of_st ; i ++ ) { rtx insn ; insn = emit_insn ( gen_rtx_SET ( st_reg , st_reg ) ) ; add_reg_note ( insn , REG_DEAD , st_reg ) ; } return num_of_st ; } </s>

Generate insns to zero all st registers together . Return true when zeroing instructions are generated . Assume the number of st registers that are zeroed is num_of_st , we will emit the following sequence to zero them together : fldz ; \ fldz ; \ ... fldz ; \ fstp % % st ( 0 ) ; \ fstp % % st ( 0 ) ; \ ... fstp % % st ( 0 ) ; i.e. , num_of_st fldz followed by num_of_st fstp to clear the stack mark stack slots empty . How to compute the num_of_st : There is no direct mapping from stack registers to hard register numbers . If one stack register needs to be cleared , we do n't know where in the stack the value remains . So , if any stack register needs to be cleared , the whole stack should be cleared . However , x87 stack registers that hold the return value should be excluded . x87 returns in the top ( two for complex values ) register , so num_of_st should be 7/6 when x87 returns , otherwise it will be 8 .


<s> static bool decl_has_samegp ( tree decl ) { if ( ! ( * targetm . binds_local_p ) ( decl ) ) return false ; if ( TARGET_EXPLICIT_RELOCS && TARGET_SMALL_DATA ) return true ; return ! TREE_PUBLIC ( decl ) || ! DECL_EXTERNAL ( decl ) ; } </s>

Return true if the function DECL will share the same GP as any function in the current unit of translation .


<s>
void
SIMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
verifyInstructionPredicates
(
MI
,
computeAvailableFeatures
(
STI
.
getFeatureBits
(
)
)
)
;
uint64_t
Encoding
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
unsigned
bytes
=
Desc
.
getSize
(
)
;
for
(
unsigned
i
=
0
;
i
<
bytes
;
i
++
)
{
OS
.
write
(
(
uint8_t
)
(
(
Encoding
>>
(
8
*
i
)
)
&
0xff
)
)
;
}
if
(
bytes
>
4
)
return
;
for
(
unsigned
i
=
0
,
e
=
MI
.
getNumOperands
(
)
;
i
<
e
;
++
i
)
{
if
(
!
AMDGPU
::
isSISrcOperand
(
Desc
,
i
)
)
continue
;
const
MCOperand
&
Op
=
MI
.
getOperand
(
i
)
;
if
(
getLitEncoding
(
Op
,
Desc
.
OpInfo
[
i
]
,
STI
)
!=
255
)
continue
;
int64_t
Imm
=
0
;
if
(
Op
.
isImm
(
)
)
Imm
=
Op
.
getImm
(
)
;
else
if
(
Op
.
isExpr
(
)
)
{
if
(
const
auto
*
C
=
dyn_cast
<
MCConstantExpr
>
(
Op
.
getExpr
(
)
)
)
Imm
=
C
->
getValue
(
)
;
}
else
if
(
!
Op
.
isExpr
(
)
)
llvm_unreachable
(
"Must be immediate or expr"
)
;
for
(
unsigned
j
=
0
;
j
<
4
;
j
++
)
{
OS
.
write
(
(
uint8_t
)
(
(
Imm
>>
(
8
*
j
)
)
&
0xff
)
)
;
}
break
;
}
}
</s>

Encode the given Inst to bytes and append to CB .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Patmos Call Graph Builder"
;
}
</s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


Return an asm sequence to start a noat block and load the address of a label into $ 1 .


<s> static rtx frame_emit_store ( int regno , int regno_note , rtx addr , rtx cfa , int cfa_offset ) { rtx reg = gen_rtx_REG ( DImode , regno ) ; rtx mem = gen_frame_mem ( DImode , addr ) ; rtx mov = gen_movdi ( mem , reg ) ; rtx reg_note = gen_rtx_REG ( DImode , regno_note ) ; rtx cfa_relative_addr = gen_rtx_PLUS ( Pmode , cfa , GEN_INT ( cfa_offset ) ) ; rtx cfa_relative_mem = gen_frame_mem ( DImode , cfa_relative_addr ) ; rtx real = gen_rtx_SET ( VOIDmode , cfa_relative_mem , reg_note ) ; add_reg_note ( mov , REG_CFA_OFFSET , real ) ; return emit_insn ( mov ) ; } </s>

Emit a store in the stack frame to save REGNO at address ADDR , and emit the corresponding REG_CFA_OFFSET note described by CFA and CFA_OFFSET . Return the emitted insn .


<s> bool supportSplitCSR ( MachineFunction * MF ) const override { return MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: CXX_FAST_TLS && MF -> getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) ; } </s>

Return true if the target supports that a subset of CSRs for the given machine function is handled explicitly via copies .


<s> void PPCInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; BuildMI ( MBB , MI , DL , get ( PPC :: NOP ) ) ; } </s>

Insert a noop into the instruction stream at the specified point .


<s> bool AMDGPUUseNativeCalls :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) || UseNative . empty ( ) ) return false ; bool Changed = false ; for ( auto & BB : F ) { for ( BasicBlock :: iterator I = BB . begin ( ) , E = BB . end ( ) ; I != E ; ) { CallInst * CI = dyn_cast < CallInst > ( I ) ; ++ I ; if ( ! CI ) continue ; Function * Callee = CI -> getCalledFunction ( ) ; if ( Callee == 0 ) continue ; if ( Simplifier . useNative ( CI ) ) Changed = true ; } } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void SIScheduleBlock :: releaseSuccessors ( SUnit * SU , bool InOrOutBlock ) { for ( SDep & Succ : SU -> Succs ) { SUnit * SuccSU = Succ . getSUnit ( ) ; if ( SuccSU -> NodeNum >= DAG -> SUnits . size ( ) ) continue ; if ( BC -> isSUInBlock ( SuccSU , ID ) != InOrOutBlock ) continue ; releaseSucc ( SU , & Succ ) ; if ( SuccSU -> NumPredsLeft == 0 && InOrOutBlock ) TopReadySUs . push_back ( SuccSU ) ; } } </s>

releaseSuccessors - Call releaseSucc on each of SU 's successors .


<s> static rtx emit_memset ( rtx destmem , rtx destptr , rtx promoted_val , HOST_WIDE_INT size_to_move ) { rtx dst = destmem ; enum insn_code code ; machine_mode move_mode ; int piece_size , i ; move_mode = GET_MODE ( promoted_val ) ; if ( move_mode == VOIDmode ) move_mode = QImode ; if ( size_to_move < GET_MODE_SIZE ( move_mode ) ) { unsigned int move_bits = size_to_move * BITS_PER_UNIT ; move_mode = int_mode_for_size ( move_bits , 0 ) . require ( ) ; promoted_val = gen_lowpart ( move_mode , promoted_val ) ; } piece_size = GET_MODE_SIZE ( move_mode ) ; code = optab_handler ( mov_optab , move_mode ) ; gcc_assert ( code != CODE_FOR_nothing && promoted_val != NULL_RTX ) ; dst = adjust_automodify_address_nv ( dst , move_mode , destptr , 0 ) ; gcc_assert ( size_to_move % piece_size == 0 ) ; for ( i = 0 ; i < size_to_move ; i += piece_size ) { if ( piece_size <= GET_MODE_SIZE ( word_mode ) ) { emit_insn ( gen_strset ( destptr , dst , promoted_val ) ) ; dst = adjust_automodify_address_nv ( dst , move_mode , destptr , piece_size ) ; continue ; } emit_insn ( GEN_FCN ( code ) ( dst , promoted_val ) ) ; emit_move_insn ( destptr , plus_constant ( Pmode , copy_rtx ( destptr ) , piece_size ) ) ; dst = adjust_automodify_address_nv ( dst , move_mode , destptr , piece_size ) ; } return dst ; } </s>

This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM with value PROMOTED_VAL . SRC is passed by pointer to be updated on return . Return value is updated DST .


<s> virtual unsigned getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { return 50 ; } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> int aarch64_movk_shift ( const wide_int_ref & and_val , const wide_int_ref & ior_val ) { unsigned int precision = and_val . get_precision ( ) ; unsigned HOST_WIDE_INT mask = 0xffff ; for ( unsigned int shift = 0 ; shift < precision ; shift += 16 ) { if ( and_val == ~ mask && ( ior_val & mask ) == ior_val ) return shift ; mask <<= 16 ; } return - 1 ; } </s>

Test whether : X = ( X & AND_VAL ) | IOR_VAL ; can be implemented using : MOVK X , # ( IOR_VAL > > shift ) , LSL # shift Return the shift if so , otherwise return -1 .


"Unexpected instruction for custom inserter!"

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> void AMDGPURegisterBankInfo :: split64BitValueForMapping ( MachineIRBuilder & B , SmallVector < Register , 2 > & Regs , LLT HalfTy , Register Reg ) const { assert ( HalfTy . getSizeInBits ( ) == 32 ) ; MachineRegisterInfo * MRI = B . getMRI ( ) ; Register LoLHS = MRI -> createGenericVirtualRegister ( HalfTy ) ; Register HiLHS = MRI -> createGenericVirtualRegister ( HalfTy ) ; const RegisterBank * Bank = getRegBank ( Reg , * MRI , * TRI ) ; MRI -> setRegBank ( LoLHS , * Bank ) ; MRI -> setRegBank ( HiLHS , * Bank ) ; Regs . push_back ( LoLHS ) ; Regs . push_back ( HiLHS ) ; B . buildInstr ( AMDGPU :: G_UNMERGE_VALUES ) . addDef ( LoLHS ) . addDef ( HiLHS ) . addUse ( Reg ) ; } </s>

Split 64-bit value Reg into two 32-bit halves and populate them into Regs .


<s> DecodeStatus VEDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CStream ) const { uint64_t Insn ; bool isLittleEndian = getContext ( ) . getAsmInfo ( ) -> isLittleEndian ( ) ; DecodeStatus Result = readInstruction64 ( Bytes , Address , Size , Insn , isLittleEndian ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTableVE64 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 8 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> void ix86_emit_i387_round ( rtx op0 , rtx op1 ) { machine_mode inmode = GET_MODE ( op1 ) ; machine_mode outmode = GET_MODE ( op0 ) ; rtx e1 = gen_reg_rtx ( XFmode ) ; rtx e2 = gen_reg_rtx ( XFmode ) ; rtx scratch = gen_reg_rtx ( HImode ) ; rtx flags = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; rtx half = const_double_from_real_value ( dconsthalf , XFmode ) ; rtx res = gen_reg_rtx ( outmode ) ; rtx_code_label * jump_label = gen_label_rtx ( ) ; rtx ( * floor_insn ) ( rtx , rtx ) ; rtx ( * neg_insn ) ( rtx , rtx ) ; rtx_insn * insn ; rtx tmp ; switch ( inmode ) { case E_SFmode : case E_DFmode : tmp = gen_reg_rtx ( XFmode ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_FLOAT_EXTEND ( XFmode , op1 ) ) ) ; op1 = tmp ; break ; case E_XFmode : break ; default : gcc_unreachable ( ) ; } switch ( outmode ) { case E_SFmode : floor_insn = gen_frndintxf2_floor ; neg_insn = gen_negsf2 ; break ; case E_DFmode : floor_insn = gen_frndintxf2_floor ; neg_insn = gen_negdf2 ; break ; case E_XFmode : floor_insn = gen_frndintxf2_floor ; neg_insn = gen_negxf2 ; break ; case E_HImode : floor_insn = gen_lfloorxfhi2 ; neg_insn = gen_neghi2 ; break ; case E_SImode : floor_insn = gen_lfloorxfsi2 ; neg_insn = gen_negsi2 ; break ; case E_DImode : floor_insn = gen_lfloorxfdi2 ; neg_insn = gen_negdi2 ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen_fxamxf2_i387 ( scratch , op1 ) ) ; emit_insn ( gen_absxf2 ( e1 , op1 ) ) ; half = force_reg ( XFmode , half ) ; emit_insn ( gen_rtx_SET ( e2 , gen_rtx_PLUS ( XFmode , e1 , half ) ) ) ; switch ( outmode ) { case E_SFmode : case E_DFmode : { tmp = gen_reg_rtx ( XFmode ) ; emit_insn ( floor_insn ( tmp , e2 ) ) ; emit_insn ( gen_rtx_SET ( res , gen_rtx_UNSPEC ( outmode , gen_rtvec ( 1 , tmp ) , UNSPEC_TRUNC_NOOP ) ) ) ; } break ; default : emit_insn ( floor_insn ( res , e2 ) ) ; } emit_insn ( gen_testqi_ext_1_ccno ( scratch , GEN_INT ( 0x02 ) ) ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_EQ ( VOIDmode , flags , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , jump_label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; predict_jump ( REG_BR_PROB_BASE * 50 / 100 ) ; JUMP_LABEL ( insn ) = jump_label ; emit_insn ( neg_insn ( res , res ) ) ; emit_label ( jump_label ) ; LABEL_NUSES ( jump_label ) = 1 ; emit_move_insn ( op0 , res ) ; } </s>


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> RegisterBankInfo :: InstructionMapping X86RegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto Opc = MI . getOpcode ( ) ; if ( ! isPreISelGenericOpcode ( Opc ) ) { InstructionMapping Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; } switch ( Opc ) { case TargetOpcode :: G_ADD : case TargetOpcode :: G_SUB : return getSameOperandsMapping ( MI , false ) ; break ; case TargetOpcode :: G_FADD : case TargetOpcode :: G_FSUB : case TargetOpcode :: G_FMUL : case TargetOpcode :: G_FDIV : return getSameOperandsMapping ( MI , true ) ; break ; default : break ; } unsigned NumOperands = MI . getNumOperands ( ) ; SmallVector < PartialMappingIdx , 4 > OpRegBankIdx ( NumOperands ) ; getInstrPartialMappingIdxs ( MI , MRI , false , OpRegBankIdx ) ; SmallVector < const ValueMapping * , 8 > OpdsMapping ( NumOperands ) ; if ( ! getInstrValueMapping ( MI , OpRegBankIdx , OpdsMapping ) ) return InstructionMapping ( ) ; return InstructionMapping { DefaultMappingID , 1 , getOperandsMapping ( OpdsMapping ) , NumOperands } ; } </s>

Get the mapping of the different operands of MI on the register bank .


<s> unsigned TOYRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return TOY :: SP ; } </s>