<s> CCAssignFn * X86FastISel :: CCAssignFnForCall ( CallingConv :: ID CC , bool isTaillCall ) { if ( Subtarget -> is64Bit ( ) ) { if ( CC == CallingConv :: GHC ) return CC_X86_64_GHC ; else if ( Subtarget -> isTargetWin64 ( ) ) return CC_X86_Win64_C ; else return CC_X86_64_C ; } if ( CC == CallingConv :: X86_FastCall ) return CC_X86_32_FastCall ; else if ( CC == CallingConv :: Fast ) return CC_X86_32_FastCC ; else if ( CC == CallingConv :: GHC ) return CC_X86_32_GHC ; else return CC_X86_32_C ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> static void nvptx_goacc_reduction_init ( gcall * call ) { gimple_stmt_iterator gsi = gsi_for_stmt ( call ) ; tree lhs = gimple_call_lhs ( call ) ; tree var = gimple_call_arg ( call , 2 ) ; int level = TREE_INT_CST_LOW ( gimple_call_arg ( call , 3 ) ) ; enum tree_code rcode = ( enum tree_code ) TREE_INT_CST_LOW ( gimple_call_arg ( call , 4 ) ) ; tree init = omp_reduction_init_op ( gimple_location ( call ) , rcode , TREE_TYPE ( var ) ) ; gimple_seq seq = NULL ; push_gimplify_context ( true ) ; if ( level == GOMP_DIM_VECTOR ) { tree tid = make_ssa_name ( integer_type_node ) ; tree dim_vector = gimple_call_arg ( call , 3 ) ; gimple * tid_call = gimple_build_call_internal ( IFN_GOACC_DIM_POS , 1 , dim_vector ) ; gimple * cond_stmt = gimple_build_cond ( NE_EXPR , tid , integer_zero_node , NULL_TREE , NULL_TREE ) ; gimple_call_set_lhs ( tid_call , tid ) ; gimple_seq_add_stmt ( & seq , tid_call ) ; gimple_seq_add_stmt ( & seq , cond_stmt ) ; edge init_edge = split_block ( gsi_bb ( gsi ) , call ) ; basic_block init_bb = init_edge -> dest ; basic_block call_bb = init_edge -> src ; init_edge -> flags ^= EDGE_FALLTHRU | EDGE_TRUE_VALUE ; init_edge -> probability = profile_probability :: even ( ) ; gimple_seq init_seq = NULL ; tree init_var = make_ssa_name ( TREE_TYPE ( var ) ) ; gimplify_assign ( init_var , init , & init_seq ) ; gsi = gsi_start_bb ( init_bb ) ; gsi_insert_seq_before ( & gsi , init_seq , GSI_SAME_STMT ) ; gsi_prev ( & gsi ) ; edge inited_edge = split_block ( gsi_bb ( gsi ) , gsi_stmt ( gsi ) ) ; basic_block dst_bb = inited_edge -> dest ; edge nop_edge = make_edge ( call_bb , dst_bb , EDGE_FALSE_VALUE ) ; nop_edge -> probability = profile_probability :: even ( ) ; gphi * phi = create_phi_node ( lhs , dst_bb ) ; add_phi_arg ( phi , init_var , inited_edge , gimple_location ( call ) ) ; add_phi_arg ( phi , var , nop_edge , gimple_location ( call ) ) ; set_immediate_dominator ( CDI_DOMINATORS , dst_bb , call_bb ) ; gsi = gsi_for_stmt ( call ) ; } else { if ( level == GOMP_DIM_GANG ) { tree ref_to_res = gimple_call_arg ( call , 1 ) ; if ( integer_zerop ( ref_to_res ) ) init = var ; } gimplify_assign ( lhs , init , & seq ) ; } pop_gimplify_context ( NULL ) ; gsi_replace_with_seq ( & gsi , seq , true ) ; } </s>

NVPTX implementation of GOACC_REDUCTION_INIT .


<s> static bool mips_truly_noop_truncation ( poly_uint64 outprec , poly_uint64 inprec ) { return ! TARGET_64BIT || inprec <= 32 || outprec > 32 ; } </s>


<s> bool GCNDownwardRPTracker :: reset ( const MachineInstr & MI , const LiveRegSet * LiveRegsCopy ) { MRI = & MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; LastTrackedMI = nullptr ; MBBEnd = MI . getParent ( ) -> end ( ) ; NextMI = & MI ; NextMI = skipDebugInstructionsForward ( NextMI , MBBEnd ) ; if ( NextMI == MBBEnd ) return false ; if ( LiveRegsCopy ) { if ( & LiveRegs != LiveRegsCopy ) LiveRegs = * LiveRegsCopy ; } else { LiveRegs = getLiveRegsBefore ( * NextMI , LIS ) ; } MaxPressure = CurPressure = getRegPressure ( * MRI , LiveRegs ) ; return true ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s> static char * avr_toupper ( char * up , const char * lo ) { char * up0 = up ; for ( ; * lo ; lo ++ , up ++ ) * up = TOUPPER ( * lo ) ; * up = '\0' ; return up0 ; } </s>

Transform LO into uppercase and write the result to UP . You must provide enough space for UP . Return UP .


<s> int ix86_attr_length_address_default ( rtx insn ) { int i ; if ( get_attr_type ( insn ) == TYPE_LEA ) { rtx set = PATTERN ( insn ) ; if ( GET_CODE ( set ) == PARALLEL ) set = XVECEXP ( set , 0 , 0 ) ; gcc_assert ( GET_CODE ( set ) == SET ) ; return memory_address_length ( SET_SRC ( set ) ) ; } extract_insn_cached ( insn ) ; for ( i = recog_data . n_operands - 1 ; i >= 0 ; -- i ) if ( GET_CODE ( recog_data . operand [ i ] ) == MEM ) { return memory_address_length ( XEXP ( recog_data . operand [ i ] , 0 ) ) ; break ; } return 0 ; } </s>

Compute default value for `` length_address '' attribute .


<s> const uint16_t * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( STI . isTargetNaCl ( ) ) return CSR_NaCl_SaveList ; const uint16_t * RegList = ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ; if ( ! MF ) return RegList ; const Function * F = MF -> getFunction ( ) ; if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F -> hasFnAttribute ( "interrupt" ) ) { if ( STI . isMClass ( ) ) { return CSR_AAPCS_SaveList ; } else if ( F -> getFnAttribute ( "interrupt" ) . getValueAsString ( ) == "FIQ" ) { return CSR_FIQ_SaveList ; } else { return CSR_GenericInt_SaveList ; } } return RegList ; } </s>


<s> bool is_fast_interrupt_func ( const_tree decl ) { return has_func_attr ( decl , "fast_interrupt" ) ; } </s>

Returns true if the provided function has the `` fast_interrupt '' attribute .


<s> static bool isConstantSplat ( SDValue Op , APInt & SplatVal ) { APInt UndefElts ; SmallVector < APInt , 16 > EltBits ; if ( getTargetConstantBitsFromNode ( Op , Op . getScalarValueSizeInBits ( ) , UndefElts , EltBits , true , false ) ) { int SplatIndex = - 1 ; for ( int i = 0 , e = EltBits . size ( ) ; i != e ; ++ i ) { if ( UndefElts [ i ] ) continue ; if ( 0 <= SplatIndex && EltBits [ i ] != EltBits [ SplatIndex ] ) { SplatIndex = - 1 ; break ; } SplatIndex = i ; } if ( 0 <= SplatIndex ) { SplatVal = EltBits [ SplatIndex ] ; return true ; } } return false ; } </s>

Check if this is a constant splat , and if so , find the smallest element size that splats the vector .


<s> bool ix86_avoid_lea_for_addr ( rtx_insn * insn , rtx operands [ ] ) { unsigned int regno0 , regno1 , regno2 ; int split_cost ; struct ix86_address parts ; int ok ; if ( REG_P ( operands [ 1 ] ) || ( SImode_address_operand ( operands [ 1 ] , VOIDmode ) && REG_P ( XEXP ( operands [ 1 ] , 0 ) ) ) ) return false ; ok = ix86_decompose_address ( operands [ 1 ] , & parts ) ; gcc_assert ( ok ) ; if ( ( parts . base != NULL_RTX ) + ( parts . index != NULL_RTX ) + ( parts . disp != NULL_RTX ) + ( parts . scale > 1 ) < 2 ) return false ; if ( parts . disp && flag_pic && ! LEGITIMATE_PIC_OPERAND_P ( parts . disp ) ) return false ; regno0 = true_regnum ( operands [ 0 ] ) ; regno1 = INVALID_REGNUM ; regno2 = INVALID_REGNUM ; if ( parts . base ) regno1 = true_regnum ( parts . base ) ; if ( parts . index ) regno2 = true_regnum ( parts . index ) ; if ( ! TARGET_BONNELL && parts . scale == 1 && ( ! parts . disp || parts . disp == const0_rtx ) && ( regno0 == regno1 || regno0 == regno2 ) ) return true ; if ( ! TARGET_AVOID_LEA_FOR_ADDR || optimize_function_for_size_p ( cfun ) ) return false ; split_cost = 0 ; if ( parts . base || parts . index ) { if ( regno1 != regno0 && regno2 != regno0 ) split_cost += 1 ; if ( parts . base && parts . index ) split_cost += 1 ; if ( parts . scale > 1 ) { if ( regno0 != regno1 ) split_cost += 1 ; else if ( regno2 == regno0 ) split_cost += 4 ; else split_cost += parts . scale ; } if ( parts . disp && parts . disp != const0_rtx ) split_cost += 1 ; split_cost -= 1 ; } return ! ix86_lea_outperforms ( insn , regno0 , regno1 , regno2 , split_cost , parts . scale > 1 ) ; } </s>

Return true if we need to split lea into a sequence of instructions to avoid AGU stalls during peephole2 .


<s> static void output_btfext_core_relocs ( bpf_core_section_ref sec ) { size_t i ; bpf_core_reloc_ref bpfcr ; FOR_EACH_VEC_ELT ( * ( sec -> relocs ) , i , bpfcr ) output_asm_btfext_core_reloc ( bpfcr ) ; } </s>

Output all CO-RE relocation records for a section .


<s> int direct_return ( void ) { if ( ! reload_completed ) return FALSE ; if ( ! current_frame_info . initialized ) m32r_compute_frame_size ( get_frame_size ( ) ) ; return current_frame_info . total_size == 0 ; } </s>

Return non-zero if this function is known to have a null epilogue .


<s>
void
AArch64AsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
nullptr
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
unsigned
FulleSizeInBytes
=
getFixupKindContainereSizeInBytes
(
Fixup
.
getKind
(
)
)
;
if
(
FulleSizeInBytes
==
0
)
{
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
else
{
assert
(
(
Offset
+
FulleSizeInBytes
)
<=
DataSize
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FulleSizeInBytes
&&
"Invalid fixup size!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
FulleSizeInBytes
1
i
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static bool sparc_vector_mode_supported_p ( machine_mode mode ) { return TARGET_VIS && VECTOR_MODE_P ( mode ) ? true : false ; } </s>

Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook . Specify whether the vector mode is supported by the hardware .


<s> int arm_apply_result_size ( void ) { int size = 16 ; if ( TARGET_32BIT ) { if ( TARGET_HARD_FLOAT_ABI && TARGET_VFP ) size += 32 ; if ( TARGET_IWMMXT_ABI ) size += 8 ; } return size ; } </s>

Determine the amount of memory needed to store the possible return registers of an untyped call .


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> optForSize ( ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( ( N -> getOpcode ( ) == X86ISD :: CALL && ! Subtarget -> callRegIndirect ( ) ) || ( N -> getOpcode ( ) == X86ISD :: TC_RETURN && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; MVT SrcVT = N -> getOperand ( 0 ) . getSimpleValueType ( ) ; MVT DstVT = N -> getSimpleValueType ( 0 ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const X86TargetLowering * X86Lowering = static_cast < const X86TargetLowering * > ( TLI ) ; bool SrcIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } MVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> MCObjectWriter * OR1KAsmBackend :: createObjectWriter ( raw_ostream & OS ) const { return createOR1KELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI ( OSType ) ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> void initializePass ( ) override { pushTTIStack ( this ) ; } </s>

initializePass - This method may be overriden by immutable passes to allow them to perform various initialization actions they require .


<s> static recpe_type get_recpe_type ( machine_mode mode ) { switch ( mode ) { case SFmode : return ( gen_aarch64_frecpesf ) ; case V2SFmode : return ( gen_aarch64_frecpev2sf ) ; case V4SFmode : return ( gen_aarch64_frecpev4sf ) ; case DFmode : return ( gen_aarch64_frecpedf ) ; case V2DFmode : return ( gen_aarch64_frecpev2df ) ; default : gcc_unreachable ( ) ; } } </s>

Select reciprocal initial estimate insn depending on machine mode .


<s> bool ParseDirective ( AsmToken DirectiveID ) override { return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> static inline bool isIndirectCall ( const MachineInstr & MI ) { int Opc = MI . getOpcode ( ) ; switch ( Opc ) { case ARM :: BLX : case ARM :: BLX_noip : case ARM :: BLX_pred : case ARM :: BLX_pred_noip : case ARM :: BX_CALL : case ARM :: BMOVPCRX_CALL : case ARM :: TCRETURNri : case ARM :: TAILJMPr : case ARM :: TAILJMPr4 : case ARM :: tBLXr : case ARM :: tBLXr_noip : case ARM :: tBLXNSr : case ARM :: tBLXNS_CALL : case ARM :: tBX_CALL : case ARM :: tTAILJMPr : assert ( MI . isCall ( MachineInstr :: IgnoreBundle ) ) ; return true ; case ARM :: BL : case ARM :: BL_pred : case ARM :: BMOVPCB_CALL : case ARM :: BL_PUSHLR : case ARM :: BLXi : case ARM :: TCRETURNdi : case ARM :: TAILJMPd : case ARM :: SVC : case ARM :: HVC : case ARM :: TPsoft : case ARM :: tTAILJMPd : case ARM :: t2SMC : case ARM :: t2HVC : case ARM :: tBL : case ARM :: tBLXi : case ARM :: tBL_PUSHLR : case ARM :: tTAILJMPdND : case ARM :: tSVC : case ARM :: tTPsoft : assert ( MI . isCall ( MachineInstr :: IgnoreBundle ) ) ; return false ; } assert ( ! MI . isCall ( MachineInstr :: IgnoreBundle ) ) ; return false ; } </s>

Return true if the callsite is an indirect call .


<s> int zero_extended_p ( rtx x , int bits , rtx insn ) { HOST_WIDE_INT w ; int i , n ; do { while ( REG_P ( x ) ) { x = pdp10_find_last_value ( x , & insn ) ; if ( x == NULL_RTX ) return 0 ; } switch ( GET_CODE ( x ) ) { case LSHIFTRT : n = INTVAL_OR_ELSE ( XEXP ( x , 1 ) , 0 ) ; x = XEXP ( x , 0 ) ; break ; case ZERO_EXTRACT : n = BITS_PER_WORD - INTVAL_OR_ELSE ( XEXP ( x , 1 ) , BITS_PER_WORD ) ; x = NULL_RTX ; break ; case AND : w = INTVAL_OR_ELSE ( XEXP ( x , 1 ) , HWINT ( - 1 ) ) ; for ( i = BITS_PER_WORD - 1 ; i >= 0 ; i -- ) { if ( w & ( ( HWINT ( 1 ) ) << i ) ) break ; } n = BITS_PER_WORD - i ; x = XEXP ( x , 0 ) ; break ; case SUBREG : n = BITS_PER_WORD - GET_MODE_BITSIZE ( GET_MODE ( x ) ) ; break ; case MEM : n = GET_MODE ( x ) == QImode ? 30 : BITS_PER_WORD - GET_MODE_BITSIZE ( GET_MODE ( x ) ) ; return n >= bits ; case UNSPEC : switch ( XINT ( x , 1 ) ) { case UNSPEC_ADDRESS : return TARGET_EXTENDED ? 0 : 18 ; } default : return 0 ; } if ( n >= bits ) return 1 ; bits -= n ; } while ( x ) ; return 0 ; } </s>

Return nonzero iff the last value X was set to before INSN had BITS zero-extended bits .


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS , bool is64bit ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS , is64bit ) , DataLayout ( Subtarget . getDataLayout ( ) ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrInfo ( Subtarget ) , FrameInfo ( Subtarget ) { } </s>


<s> bool XtensaRegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { return false ; } </s>

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot .


<s> static int autoinc_mode ( rtx x ) { if ( GET_CODE ( x ) != MEM ) return CONST ; x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == PRE_INC || GET_CODE ( x ) == PRE_DEC || GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == POST_DEC ) return GET_CODE ( x ) ; return CONST ; } </s>

Return the increment/decrement mode of a MEM if it is such . Return CONST if it is anything else .


<s> static bool m68k_cannot_force_const_mem ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { return m68k_illegitimate_symbolic_constant_p ( x ) ; } </s>


<s> bool ix86_hard_regno_mode_ok ( int regno , machine_mode mode ) { if ( CC_REGNO_P ( regno ) ) return GET_MODE_CLASS ( mode ) == MODE_CC ; if ( GET_MODE_CLASS ( mode ) == MODE_CC || GET_MODE_CLASS ( mode ) == MODE_RANDOM || GET_MODE_CLASS ( mode ) == MODE_PARTIAL_INT ) return false ; if ( STACK_REGNO_P ( regno ) ) return VALID_FP_MODE_P ( mode ) ; if ( MASK_REGNO_P ( regno ) ) return ( VALID_MASK_REG_MODE ( mode ) || ( TARGET_AVX512BW && VALID_MASK_AVX512BW_MODE ( mode ) ) ) ; if ( BND_REGNO_P ( regno ) ) return VALID_BND_REG_MODE ( mode ) ; if ( SSE_REGNO_P ( regno ) ) { if ( TARGET_AVX512F && ( mode == XImode || VALID_AVX512F_REG_MODE ( mode ) || VALID_AVX512F_SCALAR_MODE ( mode ) ) ) return true ; if ( TARGET_AVX512VL && ( mode == OImode || mode == TImode || VALID_AVX256_REG_MODE ( mode ) || VALID_AVX512VL_128_REG_MODE ( mode ) ) ) return true ; if ( EXT_REX_SSE_REGNO_P ( regno ) ) return false ; return ( ( TARGET_AVX && VALID_AVX256_REG_OR_OI_MODE ( mode ) ) || VALID_SSE_REG_MODE ( mode ) || VALID_SSE2_REG_MODE ( mode ) || VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( MMX_REGNO_P ( regno ) ) { return ( VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( mode == QImode ) { if ( ANY_QI_REGNO_P ( regno ) ) return true ; if ( ! TARGET_PARTIAL_REG_STALL ) return true ; if ( lra_in_progress ) return true ; return ! can_create_pseudo_p ( ) ; } else if ( VALID_INT_MODE_P ( mode ) ) return true ; else if ( VALID_FP_MODE_P ( mode ) ) return true ; else if ( VALID_DFP_MODE_P ( mode ) ) return true ; else if ( VALID_MMX_REG_MODE_3DNOW ( mode ) || VALID_MMX_REG_MODE ( mode ) ) return true ; return false ; } </s>

Return TRUE if hard register REGNO can hold a value of machine-mode MODE .


"-target-abi option != target-abi module flag"

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


"***** Machine Function before Domain Reassignment *****\n"

"***** Machine Function after Domain Reassignment *****\n"

runOnMachineFunction - Emit the function body .


<s>
SDValue
BPFTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
MF
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
if
(
Ins
.
size
(
)
>=
2
)
{
fail
(
DL
,
DAG
,
"only small returns supported"
)
;
for
(
unsigned
i
=
0
,
e
=
Ins
.
size
(
)
;
i
!=
e
;
++
i
)
InVals
.
push_back
(
DAG
.
getConstant
(
0
,
DL
,
Ins
[
i
]
.
VT
)
)
;
return
DAG
.
getCopyFromReg
(
Chain
,
DL
,
1
,
Ins
[
0
]
.
VT
,
InFlag
)
.
getValue
(
1
)
;
}
CCInfo
.
AnalyzeCallResult
(
Ins
,
getHasAlu32
(
)
RetCC_BPF32
:
RetCC_BPF64
)
;
for
(
auto
&
Val
:
RVLocs
)
{
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
DL
,
Val
.
getLocReg
(
)
,
Val
.
getValVT
(
)
,
InFlag
)
.
getValue
(
1
)
;
InFlag
=
Chain
.
getValue
(
2
)
;
InVals
.
push_back
(
Chain
.
getValue
(
0
)
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


Return a register that is zero iff CMP0 and CMP1 are equal . The register will have the same mode as CMP0 .


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( ( unsigned ) Kind , Value ) ; int64_t SymOffset = MipsGetSymAndOffset ( Fixup ) . second ; if ( ! Value && ! SymOffset ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { case Mips :: fixup_Mips_16 : FullSize = 2 ; break ; case Mips :: fixup_Mips_64 : FullSize = 8 ; break ; default : FullSize = 4 ; break ; } uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - 1 - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= ( Value + SymOffset ) & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> virtual const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> bool ARMPassConfig :: addLegalizeMachineIR ( ) { addPass ( new Legalizer ( ) ) ; return false ; } </s>

This method should install a legalize pass , which converts the instruction sequence into one that can be selected by the target .


<s> static void riscv_setup_incoming_varargs ( cumulative_args_t cum , enum machine_mode mode , tree type , int * pretend_size ATTRIBUTE_UNUSED , int no_rtl ) { CUMULATIVE_ARGS local_cum ; int gp_saved ; local_cum = * get_cumulative_args ( cum ) ; riscv_function_arg_advance ( pack_cumulative_args ( & local_cum ) , mode , type , 1 ) ; gp_saved = MAX_ARGS_IN_REGISTERS - local_cum . num_gprs ; if ( ! no_rtl && gp_saved > 0 ) { rtx ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , REG_PARM_STACK_SPACE ( cfun -> decl ) - gp_saved * UNITS_PER_WORD ) ; rtx mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . num_gprs + GP_ARG_FIRST , mem , gp_saved ) ; } if ( REG_PARM_STACK_SPACE ( cfun -> decl ) == 0 ) cfun -> machine -> varargs_size = gp_saved * UNITS_PER_WORD ; } </s>


<s> virtual const InstrItineraryData * getInstrItineraryData ( ) const { return InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> bool X86TTIImpl :: isLegalMaskedStore ( Type * DataType , int Consecutive ) { return isLegalMaskedLoad ( DataType , Consecutive ) ; } </s>

Return true if the target supports masked store .


<s> const AArch64InstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { ARM64FunctionInfo * AFI = MF . getInfo < ARM64FunctionInfo > ( ) ; if ( AFI -> getNumLocalDynamicTLSAccesses ( ) < 2 ) { return false ; } MachineDominatorTree * DT = & getAnalysis < MachineDominatorTree > ( ) ; return VisitNode ( DT -> getRootNode ( ) , 0 ) ; } </s>


<s> static bool renderGraphFromBottomUp ( ) { return true ; } </s>

renderGraphFromBottomUp - If this function returns true , the graph is emitted bottom-up instead of top-down .


<s>
bool
ARMAsmPrinter
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
{
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
&&
MO
.
getReg
(
)
!=
ARM
::
CPSR
)
return
false
;
assert
(
!
MO
.
getSubReg
(
)
&&
"Subregs should be eliminated!"
)
;
MCOp
=
MCOperand
::
CreateReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
CreateImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
CreateExpr
(
MCSymbolRefExpr
::
Create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
OutContext
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
{
MCOp
=
GetSymbolRef
(
MO
,
GetARMGVSymbol
(
MO
.
getGlobal
(
)
,
MO
.
getTargetFlags
(
)
)
)
;
break
;
}
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
GetSymbolRef
(
MO
,
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
MCOp
=
GetSymbolRef
(
MO
,
GetJTISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
MCOp
=
GetSymbolRef
(
MO
,
GetCPISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_BlockAddress
:
MCOp
=
GetSymbolRef
(
MO
,
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
)
;
break
;
case
MachineOperand
::
MO_FPImmediate
:
{
APFloat
Val
=
MO
.
getFPImm
(
)
->
getValueAPF
(
)
;
bool
ignored
;
Val
.
convert
(
APFloat
::
IEEEdouble
,
APFloat
::
rmTowardZero
,
&
ignored
)
;
MCOp
=
MCOperand
::
CreateFPImm
(
Val
.
convertToDouble
(
)
)
;
break
;
}
case
MachineOperand
::
MO_RegisterMask
:
return
false
;
}
return
true
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .

ARM
ARM
"unknown operand type"
ARM::CPSR
"Subregs should be eliminated!"
ARM


<s>
static
void
avr_file_start
(
void
)
{
if
(
avr_asm_only_p
)
error
(
"MCU %qs supported for assembler only"
,
avr_mcu_name
)
;
default_file_start
(
)
;
fprintf
(
asm_out_file
,
"\t.arch %s\n"
,
avr_mcu_name
)
;
fputs
(
"__SREG__ = 0x3f\n"
"__SP_H__ = 0x3e\n"
"__SP_L__ = 0x3d\n"
,
asm_out_file
)
;
fputs
(
"__tmp_reg__ = 0\n"
"__zero_reg__ = 1\n"
,
asm_out_file
)
;
fputs
(
"\t.global __do_copy_data\n"
,
asm_out_file
)
;
fputs
(
"\t.global __do_clear_bss\n"
,
asm_out_file
)
;
commands_in_file
=
0
;
commands_in_prologues
=
0
;
commands_in_epilogues
=
0
;
}
</s>

Outputs some appropriate text to go at the start of an assembler file .

avr
"MCU %qs supported for assembler only"
"\t.arch %s\n"
"__SREG__ = 0x3f\n"
"__SP_H__ = 0x3e\n"
"__SP_L__ = 0x3d\n"
"__tmp_reg__ = 0\n"
"__zero_reg__ = 1\n"
"\t.global __do_copy_data\n"
"\t.global __do_clear_bss\n"
0
0
0


<s> bool PatmosInstrInfo :: isSchedulingBoundary ( const MachineInstr * MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( MI -> isDebugValue ( ) ) return false ; if ( MI -> getDesc ( ) . isTerminator ( ) || MI -> isLabel ( ) ) return true ; return false ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> bool VEAsmParser :: ParseDirective ( AsmToken DirectiveID ) { std :: string IDVal = DirectiveID . getIdentifier ( ) . lower ( ) ; if ( IDVal == ".word" ) return parseLiteralValues ( 4 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".long" ) return parseLiteralValues ( 8 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".llong" ) return parseLiteralValues ( 8 , DirectiveID . getLoc ( ) ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool AMDGPUInstructionSelector :: select ( MachineInstr & I ) { if ( I . isPHI ( ) ) return selectPHI ( I ) ; if ( ! I . isPreISelOpcode ( ) ) { if ( I . isCopy ( ) ) return selectCOPY ( I ) ; return true ; } switch ( I . getOpcode ( ) ) { case TargetOpcode :: G_AND : case TargetOpcode :: G_OR : case TargetOpcode :: G_XOR : if ( selectG_AND_OR_XOR ( I ) ) return true ; return selectImpl ( I , * CoverageInfo ) ; case TargetOpcode :: G_ADD : case TargetOpcode :: G_SUB : if ( selectImpl ( I , * CoverageInfo ) ) return true ; return selectG_ADD_SUB ( I ) ; case TargetOpcode :: G_UADDO : case TargetOpcode :: G_USUBO : case TargetOpcode :: G_UADDE : case TargetOpcode :: G_USUBE : return selectG_UADDO_USUBO_UADDE_USUBE ( I ) ; case TargetOpcode :: G_INTTOPTR : case TargetOpcode :: G_BITCAST : case TargetOpcode :: G_PTRTOINT : return selectCOPY ( I ) ; case TargetOpcode :: G_CONSTANT : case TargetOpcode :: G_FCONSTANT : return selectG_CONSTANT ( I ) ; case TargetOpcode :: G_EXTRACT : return selectG_EXTRACT ( I ) ; case TargetOpcode :: G_MERGE_VALUES : case TargetOpcode :: G_BUILD_VECTOR : case TargetOpcode :: G_CONCAT_VECTORS : return selectG_MERGE_VALUES ( I ) ; case TargetOpcode :: G_UNMERGE_VALUES : return selectG_UNMERGE_VALUES ( I ) ; case TargetOpcode :: G_PTR_ADD : return selectG_PTR_ADD ( I ) ; case TargetOpcode :: G_IMPLICIT_DEF : return selectG_IMPLICIT_DEF ( I ) ; case TargetOpcode :: G_INSERT : return selectG_INSERT ( I ) ; case TargetOpcode :: G_INTRINSIC : return selectG_INTRINSIC ( I ) ; case TargetOpcode :: G_INTRINSIC_W_SIDE_EFFECTS : return selectG_INTRINSIC_W_SIDE_EFFECTS ( I ) ; case TargetOpcode :: G_ICMP : if ( selectG_ICMP ( I ) ) return true ; return selectImpl ( I , * CoverageInfo ) ; case TargetOpcode :: G_LOAD : case TargetOpcode :: G_ATOMIC_CMPXCHG : case TargetOpcode :: G_ATOMICRMW_XCHG : case TargetOpcode :: G_ATOMICRMW_ADD : case TargetOpcode :: G_ATOMICRMW_SUB : case TargetOpcode :: G_ATOMICRMW_AND : case TargetOpcode :: G_ATOMICRMW_OR : case TargetOpcode :: G_ATOMICRMW_XOR : case TargetOpcode :: G_ATOMICRMW_MIN : case TargetOpcode :: G_ATOMICRMW_MAX : case TargetOpcode :: G_ATOMICRMW_UMIN : case TargetOpcode :: G_ATOMICRMW_UMAX : case TargetOpcode :: G_ATOMICRMW_FADD : return selectG_LOAD_ATOMICRMW ( I ) ; case TargetOpcode :: G_SELECT : return selectG_SELECT ( I ) ; case TargetOpcode :: G_STORE : return selectG_STORE ( I ) ; case TargetOpcode :: G_TRUNC : return selectG_TRUNC ( I ) ; case TargetOpcode :: G_SEXT : case TargetOpcode :: G_ZEXT : case TargetOpcode :: G_ANYEXT : return selectG_SZA_EXT ( I ) ; case TargetOpcode :: G_BRCOND : return selectG_BRCOND ( I ) ; case TargetOpcode :: G_FRAME_INDEX : return selectG_FRAME_INDEX ( I ) ; case TargetOpcode :: G_PTR_MASK : return selectG_PTR_MASK ( I ) ; default : return selectImpl ( I , * CoverageInfo ) ; } return false ; } </s>

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s> unsigned X86TTI :: getIntImmCost ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) const { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return ~ 0U ; unsigned ImmIdx = ~ 0U ; switch ( Opcode ) { default : return TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TCC_Basic ; return TCC_Free ; case Instruction :: Store : ImmIdx = 0 ; break ; case Instruction :: Add : case Instruction :: Sub : case Instruction :: Mul : case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : case Instruction :: ICmp : ImmIdx = 1 ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == 1 ) return TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: IntToPtr : case Instruction :: PtrToInt : case Instruction :: BitCast : case Instruction :: PHI : case Instruction :: Call : case Instruction :: Select : case Instruction :: Ret : case Instruction :: Load : break ; } if ( ( Idx == ImmIdx ) && Imm . getBitWidth ( ) <= 64 && isInt < 32 > ( Imm . getSExtValue ( ) ) ) return TCC_Free ; return X86TTI :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> bool TOYInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { return true ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> bool LM32TargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ; if ( Kind . isMergeable1ByteCString ( ) ) return false ; Type * Ty = GV -> getType ( ) -> getElementType ( ) ; return IsInSmallSection ( TM . getSubtargetImpl ( ) -> getDataLayout ( ) -> getTypeAllocSize ( Ty ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> static void loongarch_legitimize_const_move ( machine_mode mode , rtx dest , rtx src ) { rtx base , offset ; if ( splittable_const_int_operand ( src , mode ) ) { loongarch_move_integer ( dest , dest , INTVAL ( src ) ) ; return ; } if ( loongarch_split_symbol ( dest , src , MAX_MACHINE_MODE , & src ) ) { loongarch_emit_set ( dest , src ) ; return ; } if ( loongarch_tls_symbol_p ( src ) ) { loongarch_emit_move ( dest , loongarch_legitimize_tls_address ( src ) ) ; return ; } split_const ( src , & base , & offset ) ; if ( offset != const0_rtx && ( targetm . cannot_force_const_mem ( mode , src ) || ( can_create_pseudo_p ( ) ) ) ) { base = loongarch_force_temporary ( dest , base ) ; loongarch_emit_move ( dest , loongarch_add_offset ( NULL , base , INTVAL ( offset ) ) ) ; return ; } src = force_const_mem ( mode , src ) ; loongarch_emit_move ( dest , src ) ; } </s>

Subroutine of loongarch_legitimize_move . Move constant SRC into register DEST given that SRC satisfies immediate_operand but does n't satisfy move_operand .


<s> bool WebAssemblyTargetLowering :: allowsMisalignedMemoryAccesses ( EVT , unsigned , unsigned , MachineMemOperand :: Flags , bool * Fast ) const { if ( Fast ) * Fast = true ; return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


Define the ` __builtin_va_list ' type for the ABI .


<s> int pa_reloc_needed ( tree exp ) { int reloc = 0 ; switch ( TREE_CODE ( exp ) ) { case ADDR_EXPR : return 1 ; case POINTER_PLUS_EXPR : case PLUS_EXPR : case MINUS_EXPR : reloc = pa_reloc_needed ( TREE_OPERAND ( exp , 0 ) ) ; reloc |= pa_reloc_needed ( TREE_OPERAND ( exp , 1 ) ) ; break ; CASE_CONVERT : case NON_LVALUE_EXPR : reloc = pa_reloc_needed ( TREE_OPERAND ( exp , 0 ) ) ; break ; case CONSTRUCTOR : { tree value ; unsigned HOST_WIDE_INT ix ; FOR_EACH_CONSTRUCTOR_VALUE ( CONSTRUCTOR_ELTS ( exp ) , ix , value ) if ( value ) reloc |= pa_reloc_needed ( value ) ; } break ; case ERROR_MARK : break ; default : break ; } return reloc ; } </s>

Examine EXP and return nonzero if it contains an ADDR_EXPR ( meaning it will need a link/runtime reloc ) .


<s> unsigned getMaximumJumpTableSize ( ) const { return MaxJumpTableSize ; } </s>

Return upper limit for number of entries in a jump table .


<s> void TOYMCInstLower :: Initialize ( Mangler * M , MCContext * C ) { Mang = M ; Ctx = C ; } </s>

This method must be called before any actual lowering is done .


<s> static bool expand_vec_perm_even_odd_trunc ( struct expand_vec_perm_d * d ) { rtx t1 , t2 , t3 , t4 ; unsigned i , odd , nelt = d -> nelt ; if ( ! TARGET_AVX512BW || d -> one_operand_p || d -> vmode != V64QImode ) return false ; odd = d -> perm [ 0 ] ; if ( odd > 1 ) return false ; for ( i = 1 ; i < nelt ; ++ i ) if ( d -> perm [ i ] != 2 * i + odd ) return false ; if ( d -> testing_p ) return true ; if ( odd ) { t1 = gen_reg_rtx ( V32HImode ) ; t2 = gen_reg_rtx ( V32HImode ) ; emit_insn ( gen_lshrv32hi3 ( t1 , gen_lowpart ( V32HImode , d -> op0 ) , GEN_INT ( 8 ) ) ) ; emit_insn ( gen_lshrv32hi3 ( t2 , gen_lowpart ( V32HImode , d -> op1 ) , GEN_INT ( 8 ) ) ) ; } else { t1 = gen_lowpart ( V32HImode , d -> op0 ) ; t2 = gen_lowpart ( V32HImode , d -> op1 ) ; } t3 = gen_reg_rtx ( V32QImode ) ; t4 = gen_reg_rtx ( V32QImode ) ; emit_insn ( gen_avx512bw_truncatev32hiv32qi2 ( t3 , t1 ) ) ; emit_insn ( gen_avx512bw_truncatev32hiv32qi2 ( t4 , t2 ) ) ; emit_insn ( gen_avx_vec_concatv64qi ( d -> target , t3 , t4 ) ) ; return true ; } </s>

A subroutine of expand_vec_perm_even_odd_1 . Implement extract-even and extract-odd permutations of two V64QI operands with two `` shifts '' , two `` truncs '' and one `` concat '' insns for `` odd '' and two `` truncs '' and one concat insn for `` even . '' Have already failed all two instruction sequences .


<s> BitVector RISCVRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; Reserved . set ( RISCV :: zero ) ; Reserved . set ( RISCV :: zero_64 ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( RISCV :: fp ) ; Reserved . set ( RISCV :: s0 ) ; Reserved . set ( RISCV :: fp_64 ) ; Reserved . set ( RISCV :: s0_64 ) ; } Reserved . set ( RISCV :: sp ) ; Reserved . set ( RISCV :: sp_64 ) ; Reserved . set ( RISCV :: tp ) ; Reserved . set ( RISCV :: tp_64 ) ; Reserved . set ( RISCV :: gp ) ; Reserved . set ( RISCV :: gp_64 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
static
GlobalVariable
*
getGlobalVariable
(
Module
&
M
,
Type
*
Ty
,
WebAssemblyTargetMachine
&
TM
,
const
char
*
Name
)
{
auto
*
GV
=
dyn_cast
<
GlobalVariable
>
(
M
.
getOrInsertGlobal
(
Name
,
Ty
)
)
;
if
(
!
GV
)
report_fatal_error
(
Twine
(
"unable to create global: "
)
+
Name
)
;
GV
->
setThreadLocalMode
(
GlobalValue
::
GeneralDynamicTLSModel
)
;
return
GV
;
}
</s>

getGlobalVariable - Look up the specified global variable in the module symbol table .

WebAssembly
WebAssembly
"unable to create global: "


<s> bool GCNDownwardRPTracker :: reset ( const MachineInstr & MI , const LiveRegSet * LiveRegsCopy ) { MRI = & MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; LastTrackedMI = nullptr ; MBBEnd = MI . getParent ( ) -> end ( ) ; NextMI = & MI ; NextMI = skipDebugInstructionsForward ( NextMI , MBBEnd ) ; if ( NextMI == MBBEnd ) return false ; GCNRPTracker :: reset ( * NextMI , LiveRegsCopy , false ) ; return true ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s> static unsigned int compute_vrsave_mask ( void ) { unsigned int i , mask = 0 ; for ( i = FIRST_ALTIVEC_REGNO ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( regs_ever_live [ i ] ) mask |= ALTIVEC_REG_BIT ( i ) ; if ( mask == 0 ) return mask ; for ( i = cfun -> args_info . vregno - 1 ; i >= ALTIVEC_ARG_MIN_REG ; -- i ) mask &= ~ ALTIVEC_REG_BIT ( i ) ; { bool yes = false ; diddle_return_value ( is_altivec_return_reg , & yes ) ; if ( yes ) mask &= ~ ALTIVEC_REG_BIT ( ALTIVEC_ARG_RETURN ) ; } return mask ; } </s>

Return a 32-bit mask of the AltiVec registers we need to set in VRSAVE . Bit n of the return value is 1 if Vn is live . The MSB in the 32-bit word is 0 .


<s>
bool
R600ClauseMergePass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
const
R600Subtarget
&
ST
=
MF
.
getSubtarget
<
R600Subtarget
>
(
)
;
TII
=
ST
.
getInstrInfo
(
)
;
for
(
MachineFunction
::
iterator
BB
=
MF
.
begin
(
)
,
BB_E
=
MF
.
end
(
)
;
BB
!=
BB_E
;
++
BB
)
{
MachineBasicBlock
&
MBB
=
*
BB
;
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
,
E
=
MBB
.
end
(
)
;
MachineBasicBlock
::
iterator
LatestCFAlu
=
E
;
while
(
I
!=
E
)
{
MachineInstr
&
MI
=
*
I
++
;
if
(
(
!
TII
->
canBeConsideredALU
(
MI
)
&&
!
isCFAlu
(
MI
)
)
||
TII
->
mustBeLastInClause
(
MI
.
getOpcode
(
)
)
)
LatestCFAlu
=
E
;
if
(
!
isCFAlu
(
MI
)
)
continue
;
cleanPotentialDisabledCFAlu
(
MI
)
;
if
(
LatestCFAlu
!=
E
&&
mergeIfPossible
(
*
LatestCFAlu
,
MI
)
)
{
MI
.
eraseFromParent
(
)
;
}
else
{
assert
(
MI
.
getOperand
(
8
)
.
getImm
(
)
&&
"CF ALU instruction disabled"
)
;
LatestCFAlu
=
MI
;
}
}
}
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> PreservedAnalyses AMDGPUPromoteKernelArgumentsPass :: run ( Function & F , FunctionAnalysisManager & AM ) { MemorySSA & MSSA = AM . getResult < MemorySSAAnalysis > ( F ) . getMSSA ( ) ; AliasAnalysis & AA = AM . getResult < AAManager > ( F ) ; if ( AMDGPUPromoteKernelArguments ( ) . run ( F , MSSA , AA ) ) { PreservedAnalyses PA ; PA . preserveSet < CFGAnalyses > ( ) ; PA . preserve < MemorySSAAnalysis > ( ) ; return PA ; } return PreservedAnalyses :: all ( ) ; } </s>

Run the analysis pass over a function and produce a dominator tree .


<s> MachineInstrBuilder SIInstrInfo :: getAddNoCarry ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , unsigned DestReg ) const { if ( ST . hasAddNoCarry ( ) ) return BuildMI ( MBB , I , DL , get ( AMDGPU :: V_ADD_U32_e64 ) , DestReg ) ; MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; unsigned UnusedCarry = MRI . createVirtualRegister ( RI . getBoolRC ( ) ) ; MRI . setRegAllocationHint ( UnusedCarry , 0 , RI . getVCC ( ) ) ; return BuildMI ( MBB , I , DL , get ( AMDGPU :: V_ADD_I32_e64 ) , DestReg ) . addReg ( UnusedCarry , RegState :: Define | RegState :: Dead ) ; } </s>

Return a partially built integer add instruction without carry .


"Do not know how to custom type legalize this operation!"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> void GCNPassConfig :: addFastRegAlloc ( FunctionPass * RegAllocPass ) { insertPass ( & PHIEliminationID , & SILowerControlFlowID , false ) ; TargetPassConfig :: addFastRegAlloc ( RegAllocPass ) ; } </s>

addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast register allocation .


<s> void assignValueToAddress ( Register ValVReg , Register Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant , Size , 1 ) ; MIRBuilder . buildLoad ( ValVReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s>
void
print
(
DiagnosticPrinter
&
DP
)
const
override
{
std
::
string
Str
;
raw_string_ostream
OS
(
Str
)
;
if
(
DLoc
.
isUnknown
(
)
==
false
)
{
DILocation
DIL
(
DLoc
.
getAsMDNode
(
Fn
.
getContext
(
)
)
)
;
StringRef
Filename
=
DIL
.
getFilename
(
)
;
unsigned
Line
=
DIL
.
getLineNumber
(
)
;
unsigned
Column
=
DIL
.
getColumnNumber
(
)
;
OS
<<
Filename
<<
':'
<<
Line
<<
':'
<<
Column
<<
' '
;
}
OS
<<
"in function "
<<
Fn
.
getName
(
)
<<
' '
<<
*
Fn
.
getFunctionType
(
)
<<
'\n'
<<
Description
;
if
(
Value
)
Value
->
print
(
OS
)
;
OS
<<
'\n'
;
OS
.
flush
(
)
;
DP
<<
Str
;
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> bool MipsSEInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock & MBB = * MI -> getParent ( ) ; bool isMicroMips = TM . getSubtarget < MipsSubtarget > ( ) . inMicroMipsMode ( ) ; unsigned Opc ; switch ( MI -> getDesc ( ) . getOpcode ( ) ) { default : return false ; case Mips :: RetRA : expandRetRA ( MBB , MI ) ; break ; case Mips :: PseudoMFHI : Opc = isMicroMips ? Mips :: MFHI16_MM : Mips :: MFHI ; expandPseudoMFHiLo ( MBB , MI , Opc ) ; break ; case Mips :: PseudoMFLO : Opc = isMicroMips ? Mips :: MFLO16_MM : Mips :: MFLO ; expandPseudoMFHiLo ( MBB , MI , Opc ) ; break ; case Mips :: PseudoMFHI64 : expandPseudoMFHiLo ( MBB , MI , Mips :: MFHI64 ) ; break ; case Mips :: PseudoMFLO64 : expandPseudoMFHiLo ( MBB , MI , Mips :: MFLO64 ) ; break ; case Mips :: PseudoMTLOHI : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO , Mips :: MTHI , false ) ; break ; case Mips :: PseudoMTLOHI64 : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO64 , Mips :: MTHI64 , false ) ; break ; case Mips :: PseudoMTLOHI_DSP : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO_DSP , Mips :: MTHI_DSP , true ) ; break ; case Mips :: PseudoCVT_S_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_D32_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_D32_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_S_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_L , Mips :: DMTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_W , Mips :: MTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_L , Mips :: DMTC1 , true ) ; break ; case Mips :: BuildPairF64 : expandBuildPairF64 ( MBB , MI , false ) ; break ; case Mips :: BuildPairF64_64 : expandBuildPairF64 ( MBB , MI , true ) ; break ; case Mips :: ExtractElementF64 : expandExtractElementF64 ( MBB , MI , false ) ; break ; case Mips :: ExtractElementF64_64 : expandExtractElementF64 ( MBB , MI , true ) ; break ; case Mips :: MIPSeh_return32 : case Mips :: MIPSeh_return64 : expandEhReturn ( MBB , MI ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> static rtx nvptx_pc_set ( const rtx_insn * insn , bool strict = true ) { rtx pat ; if ( ( strict && ! JUMP_P ( insn ) ) || ( ! strict && ! INSN_P ( insn ) ) ) return NULL_RTX ; pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , 0 , 0 ) ; if ( GET_CODE ( pat ) == SET && GET_CODE ( SET_DEST ( pat ) ) == PC ) return pat ; return NULL_RTX ; } </s>

Variant of pc_set that only requires JUMP_P ( INSN ) if STRICT . This variant is needed in the nvptx target because the branches generated for parititioning are NONJUMP_INSN_P , not JUMP_P .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AsmPrinter :: getAnalysisUsage ( AU ) ; AU . setPreservesAll ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
bool
MSP430AsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
if
(
Name
.
endswith_lower
(
".w"
)
)
Name
=
Name
.
drop_back
(
2
)
;
if
(
!
parseJccInstruction
(
Info
,
Name
,
NameLoc
,
Operands
)
)
return
false
;
Operands
.
push_back
(
MSP430Operand
::
CreateToken
(
Name
,
NameLoc
)
)
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
return
false
;
if
(
ParseOperand
(
Operands
)
)
return
true
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
getLexer
(
)
.
Lex
(
)
;
if
(
ParseOperand
(
Operands
)
)
return
true
;
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
getParser
(
)
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
getParser
(
)
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> bool PPCInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumT , unsigned ExtraT , MachineBasicBlock & FMBB , unsigned NumF , unsigned ExtraF , const BranchProbability & Probability ) const { return ! ( MBBDefinesCTR ( TMBB ) && MBBDefinesCTR ( FMBB ) ) ; } </s>


<s> void AVRPassConfig :: addPreRegAlloc ( ) { addPass ( createAVRDynAllocaSRPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static int stackSlotSize ( ) { return 4 ; } </s>


<s> bool AArch64FastISel :: isTypeLegal ( Type * Ty , MVT & VT ) { EVT evt = TLI . getValueType ( DL , Ty , true ) ; if ( evt == MVT :: Other || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; if ( VT == MVT :: f128 ) return false ; return TLI . isTypeLegal ( VT ) ; } </s>


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const { if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ 0 ] . OperandType != MCOI :: OPERAND_PCREL ) return false ; int64_t Imm = Inst . getOperand ( 0 ) . getImm ( ) ; Target = Addr + Imm + 8 ; return true ; } </s>

Given a branch instruction try to get the address the branch targets .


<s> virtual const TargetRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static bool mips_cfun_call_saved_reg_p ( unsigned int regno ) { if ( global_regs [ regno ] ) return false ; if ( cfun -> machine -> interrupt_handler_p && mips_interrupt_extra_call_saved_reg_p ( regno ) ) return true ; return ( regno == GLOBAL_POINTER_REGNUM ? TARGET_CALL_SAVED_GP : ! call_really_used_regs [ regno ] ) ; } </s>

Return true if the current function should treat register REGNO as call-saved .


<s> bool enableSubRegLiveness ( ) const override { return false ; } </s>

Enable tracking of subregister liveness in register allocator .


<s> MachineInstr * X86InstrInfo :: optimizeLoadInstr ( MachineInstr * MI , const MachineRegisterInfo * MRI , unsigned & FoldAsLoadDefReg , MachineInstr * & DefMI ) const { if ( FoldAsLoadDefReg == 0 ) return nullptr ; if ( MI -> mayLoad ( ) ) { FoldAsLoadDefReg = 0 ; return nullptr ; } DefMI = MRI -> getVRegDef ( FoldAsLoadDefReg ) ; assert ( DefMI ) ; bool SawStore = false ; if ( ! DefMI -> isSafeToMove ( nullptr , SawStore ) ) return nullptr ; unsigned SrcOperandId = 0 ; bool FoundSrcOperand = false ; for ( unsigned i = 0 , e = MI -> getDesc ( ) . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg != FoldAsLoadDefReg ) continue ; if ( MO . getSubReg ( ) || MO . isDef ( ) || FoundSrcOperand ) return nullptr ; SrcOperandId = i ; FoundSrcOperand = true ; } if ( ! FoundSrcOperand ) return nullptr ; if ( MachineInstr * FoldMI = foldMemoryOperand ( MI , SrcOperandId , DefMI ) ) { FoldAsLoadDefReg = 0 ; return FoldMI ; } return nullptr ; } </s>

optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use .


<s> static int h8300_and_costs ( rtx x ) { rtx operands [ 4 ] ; if ( GET_MODE ( x ) == QImode ) return 1 ; if ( GET_MODE ( x ) != HImode && GET_MODE ( x ) != SImode ) return 100 ; operands [ 0 ] = NULL ; operands [ 1 ] = XEXP ( x , 0 ) ; operands [ 2 ] = XEXP ( x , 1 ) ; operands [ 3 ] = x ; return compute_logical_op_length ( GET_MODE ( x ) , AND , operands , NULL ) / 2 ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"J2 Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool X86AsmBackend :: shouldForceRelocation ( const MCAssembler & , const MCFixup & Fixup , const MCValue & ) { return Fixup . getKind ( ) >= FirstLiteralRelocationKind ; } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> TargetLowering :: ConstraintWeight FISCTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'c' : if ( type -> isIntegerTy ( ) ) weight = CW_SpecificReg ; break ; case 'I' : case 'J' : case 'K' : case 'L' : case 'N' : case 'O' : case 'P' : if ( isa < ConstantInt > ( CallOperandVal ) ) weight = CW_Constant ; break ; case 'R' : weight = CW_Memory ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> SDValue PIC16TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { case ISD :: STORE : return PerformStoreCombine ( N , DCI ) ; case PIC16ISD :: PIC16Load : return PerformPIC16LoadCombine ( N , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> const char * HexagonTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( HexagonISD :: NodeType ) Opcode ) { case HexagonISD :: ALLOCA : return "HexagonISD::ALLOCA" ; case HexagonISD :: AT_GOT : return "HexagonISD::AT_GOT" ; case HexagonISD :: AT_PCREL : return "HexagonISD::AT_PCREL" ; case HexagonISD :: BARRIER : return "HexagonISD::BARRIER" ; case HexagonISD :: CALL : return "HexagonISD::CALL" ; case HexagonISD :: CALLnr : return "HexagonISD::CALLnr" ; case HexagonISD :: CALLR : return "HexagonISD::CALLR" ; case HexagonISD :: COMBINE : return "HexagonISD::COMBINE" ; case HexagonISD :: CONST32_GP : return "HexagonISD::CONST32_GP" ; case HexagonISD :: CONST32 : return "HexagonISD::CONST32" ; case HexagonISD :: CP : return "HexagonISD::CP" ; case HexagonISD :: DCFETCH : return "HexagonISD::DCFETCH" ; case HexagonISD :: EH_RETURN : return "HexagonISD::EH_RETURN" ; case HexagonISD :: TSTBIT : return "HexagonISD::TSTBIT" ; case HexagonISD :: EXTRACTU : return "HexagonISD::EXTRACTU" ; case HexagonISD :: INSERT : return "HexagonISD::INSERT" ; case HexagonISD :: JT : return "HexagonISD::JT" ; case HexagonISD :: RET_FLAG : return "HexagonISD::RET_FLAG" ; case HexagonISD :: TC_RETURN : return "HexagonISD::TC_RETURN" ; case HexagonISD :: VASL : return "HexagonISD::VASL" ; case HexagonISD :: VASR : return "HexagonISD::VASR" ; case HexagonISD :: VLSR : return "HexagonISD::VLSR" ; case HexagonISD :: VSPLAT : return "HexagonISD::VSPLAT" ; case HexagonISD :: VEXTRACTW : return "HexagonISD::VEXTRACTW" ; case HexagonISD :: VINSERTW0 : return "HexagonISD::VINSERTW0" ; case HexagonISD :: VROR : return "HexagonISD::VROR" ; case HexagonISD :: READCYCLE : return "HexagonISD::READCYCLE" ; case HexagonISD :: VZERO : return "HexagonISD::VZERO" ; case HexagonISD :: VSPLATW : return "HexagonISD::VSPLATW" ; case HexagonISD :: D2P : return "HexagonISD::D2P" ; case HexagonISD :: P2D : return "HexagonISD::P2D" ; case HexagonISD :: V2Q : return "HexagonISD::V2Q" ; case HexagonISD :: Q2V : return "HexagonISD::Q2V" ; case HexagonISD :: QCAT : return "HexagonISD::QCAT" ; case HexagonISD :: QTRUE : return "HexagonISD::QTRUE" ; case HexagonISD :: QFALSE : return "HexagonISD::QFALSE" ; case HexagonISD :: TYPECAST : return "HexagonISD::TYPECAST" ; case HexagonISD :: VALIGN : return "HexagonISD::VALIGN" ; case HexagonISD :: VALIGNADDR : return "HexagonISD::VALIGNADDR" ; case HexagonISD :: OP_END : break ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

Hexagon Hexagon HexagonISD::NodeType HexagonISD::ALLOCA "HexagonISD::ALLOCA" HexagonISD::AT_GOT "HexagonISD::AT_GOT" HexagonISD::AT_PCREL "HexagonISD::AT_PCREL" HexagonISD::BARRIER "HexagonISD::BARRIER" HexagonISD::CALL "HexagonISD::CALL" HexagonISD::CALLnr "HexagonISD::CALLnr" HexagonISD::CALLR "HexagonISD::CALLR" HexagonISD::COMBINE "HexagonISD::COMBINE" HexagonISD::CONST32_GP "HexagonISD::CONST32_GP" HexagonISD::CONST32 "HexagonISD::CONST32" HexagonISD::CP "HexagonISD::CP" HexagonISD::DCFETCH "HexagonISD::DCFETCH" HexagonISD::EH_RETURN "HexagonISD::EH_RETURN" HexagonISD::TSTBIT "HexagonISD::TSTBIT" HexagonISD::EXTRACTU "HexagonISD::EXTRACTU" HexagonISD::INSERT "HexagonISD::INSERT" HexagonISD::JT "HexagonISD::JT" HexagonISD::RET_FLAG "HexagonISD::RET_FLAG" HexagonISD::TC_RETURN "HexagonISD::TC_RETURN" HexagonISD::VASL "HexagonISD::VASL" HexagonISD::VASR "HexagonISD::VASR" HexagonISD::VLSR "HexagonISD::VLSR" HexagonISD::VSPLAT "HexagonISD::VSPLAT" HexagonISD::VEXTRACTW "HexagonISD::VEXTRACTW" HexagonISD::VINSERTW0 "HexagonISD::VINSERTW0" HexagonISD::VROR "HexagonISD::VROR" HexagonISD::READCYCLE "HexagonISD::READCYCLE" HexagonISD::VZERO "HexagonISD::VZERO" HexagonISD::VSPLATW "HexagonISD::VSPLATW" HexagonISD::D2P "HexagonISD::D2P" HexagonISD::P2D "HexagonISD::P2D" HexagonISD::V2Q "HexagonISD::V2Q" HexagonISD::Q2V "HexagonISD::Q2V" HexagonISD::QCAT "HexagonISD::QCAT" HexagonISD::QTRUE "HexagonISD::QTRUE" HexagonISD::QFALSE "HexagonISD::QFALSE" HexagonISD::TYPECAST "HexagonISD::TYPECAST" HexagonISD::VALIGN "HexagonISD::VALIGN" HexagonISD::VALIGNADDR "HexagonISD::VALIGNADDR" HexagonISD::OP_END


<s> static tree aarch64_builtin_reciprocal ( tree fndecl ) { if ( ! use_rsqrt_p ( ) ) return NULL_TREE ; return aarch64_builtin_rsqrt ( DECL_FUNCTION_CODE ( fndecl ) ) ; } </s>

Function to decide when to use the approximate reciprocal square root builtin .


<s> static int n_pregs_to_save ( bool is_inthandler , bool consecutive ) { int count = 0 ; unsigned i ; for ( i = REG_P5 + 1 ; i -- != REG_P0 ; ) if ( must_save_p ( is_inthandler , i ) ) count ++ ; else if ( consecutive ) return count ; return count ; } </s>

Like n_dregs_to_save , but compute number of PREGS to save .


<s> static int cpat_info ( unsigned char * arr , int size , int * prun , int * pstart ) { int cpat , run , i , start ; cpat = 1 ; run = 0 ; start = - 1 ; for ( i = 0 ; i < size && cpat ; i ++ ) if ( arr [ i ] != i + 16 ) { if ( ! run ) { start = i ; if ( arr [ i ] == 3 ) run = 1 ; else if ( arr [ i ] == 2 && arr [ i + 1 ] == 3 ) run = 2 ; else if ( arr [ i ] == 0 ) { while ( arr [ i + run ] == run && i + run < 16 ) run ++ ; if ( run != 4 && run != 8 ) cpat = 0 ; } else cpat = 0 ; if ( ( i & ( run - 1 ) ) != 0 ) cpat = 0 ; i += run ; } else cpat = 0 ; } if ( cpat && ( run || size < 16 ) ) { if ( run == 0 ) run = 1 ; if ( prun ) * prun = run ; if ( pstart ) * pstart = start == - 1 ? 16 - run : start ; return 1 ; } return 0 ; } </s>

Return true if the first SIZE bytes of arr is a constant that can be generated with cbd , chd , cwd or cdd . When non-NULL , PRUN and PSTART represent the size and offset of the instruction to use .


<s> int cris_fatal ( char * arg ) { internal_error ( arg ) ; return 0 ; } </s>


<s>
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
P2TargetLowering
::
getRegForInlineAsmConstraint
(
const
TargetRegisterInfo
*
TRI
,
StringRef
Constraint
,
MVT
VT
)
const
{
if
(
Constraint
.
size
(
)
==
1
)
{
switch
(
Constraint
[
0
]
)
{
case
'r'
:
if
(
VT
==
MVT
::
i32
||
VT
==
MVT
::
i16
||
VT
==
MVT
::
i8
)
{
return
std
::
make_pair
(
0U
,
&
P2
::
P2GPRRegClass
)
;
}
else
{
llvm_unreachable
(
"Unexpected type for constraint r"
)
;
}
break
;
default
:
llvm_unreachable
(
"Unexpected type."
)
;
}
}
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
R
;
R
=
parseRegForInlineAsmConstraint
(
Constraint
,
VT
)
;
if
(
R
.
second
)
return
R
;
return
TargetLowering
::
getRegForInlineAsmConstraint
(
TRI
,
Constraint
,
VT
)
;
}
</s>

Given a physical register constraint ( e.g .


<s>
static
void
recombine_stvx_pattern
(
rtx_insn
*
insn
,
del_info
*
to_delete
)
{
rtx
body
=
PATTERN
(
insn
)
;
gcc_assert
(
GET_CODE
(
body
)
==
SET
&&
MEM_P
(
SET_DEST
(
body
)
)
&&
GET_CODE
(
SET_SRC
(
body
)
)
==
VEC_SELECT
)
;
rtx
mem
=
SET_DEST
(
body
)
;
rtx
base_reg
=
XEXP
(
mem
,
0
)
;
auto_vec
<
rtx_insn
*
>
and_insns
;
auto_vec
<
rtx
>
and_ops
;
bool
is_any_def_and
=
find_alignment_op
(
insn
,
base_reg
,
&
and_insns
,
&
and_ops
)
;
if
(
is_any_def_and
)
{
gcc_assert
(
and_insns
.
length
(
)
==
and_ops
.
length
(
)
)
;
rtx
src_reg
=
XEXP
(
SET_SRC
(
body
)
,
0
)
;
df_ref
src_use
;
struct
df_insn_info
*
insn_info
=
DF_INSN_INFO_GET
(
insn
)
;
FOR_EACH_INSN_INFO_USE
(
src_use
,
insn_info
)
{
if
(
!
rtx_equal_p
(
DF_REF_REG
(
src_use
)
,
src_reg
)
)
continue
;
struct
df_link
*
link
=
DF_REF_CHAIN
(
src_use
)
;
if
(
!
link
||
link
->
next
)
break
;
rtx_insn
*
swap_insn
=
DF_REF_INSN
(
link
->
ref
)
;
if
(
!
insn_is_swap_p
(
swap_insn
)
||
insn_is_load_p
(
swap_insn
)
||
insn_is_store_p
(
swap_insn
)
)
break
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace
=
true
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace_insn
=
swap_insn
;
rtx
new_reg
=
0
;
rtx
and_mask
=
0
;
for
(
unsigned
i
=
0
;
i
<
and_insns
.
length
(
)
;
i
++
)
{
rtx_insn
*
and_insn
=
and_insns
[
i
]
;
rtx
and_op
=
and_ops
[
i
]
;
rtx
and_base
=
XEXP
(
and_op
,
0
)
;
if
(
!
new_reg
)
{
new_reg
=
gen_reg_rtx
(
GET_MODE
(
and_base
)
)
;
and_mask
=
XEXP
(
and_op
,
1
)
;
}
rtx
copy
=
gen_rtx_SET
(
new_reg
,
and_base
)
;
rtx_insn
*
new_insn
=
emit_insn_after
(
copy
,
and_insn
)
;
set_block_for_insn
(
new_insn
,
BLOCK_FOR_INSN
(
and_insn
)
)
;
df_insn_rescan
(
new_insn
)
;
}
XEXP
(
mem
,
0
)
=
gen_rtx_AND
(
GET_MODE
(
new_reg
)
,
new_reg
,
and_mask
)
;
SET_SRC
(
body
)
=
src_reg
;
INSN_CODE
(
insn
)
=
1
;
df_insn_rescan
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"stvx opportunity found at %d\n"
,
INSN_UID
(
insn
)
)
;
}
}
}
</s>

If INSN is the store for an stvx pattern , put it in canonical form .


<s> static std :: unique_ptr < SparcOperand > CreateReg ( unsigned RegNum , unsigned Kind , SMLoc S , SMLoc E ) { auto Op = make_unique < SparcOperand > ( k_Register ) ; Op -> Reg . RegNum = RegNum ; Op -> Reg . Kind = ( SparcOperand :: RegisterKind ) Kind ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .

Sparc Sparc Sparc SparcOperand::RegisterKind


<s> bool M68kPassConfig :: addRegBankSelect ( ) { addPass ( new RegBankSelect ( ) ) ; return false ; } </s>

This method should install a register bank selector pass , which assigns register banks to virtual registers without a register class or register banks .


"%qE attribute only applies to functions"


<s> static bool sh_return_in_memory ( tree type , tree fndecl ) { if ( TARGET_SH5 ) { if ( TYPE_MODE ( type ) == BLKmode ) return ( ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) ) > 8 ; else return GET_MODE_SIZE ( TYPE_MODE ( type ) ) > 8 ; } else { return ( TYPE_MODE ( type ) == BLKmode || ( ( TARGET_HITACHI || sh_attr_renesas_p ( fndecl ) ) && TREE_CODE ( type ) == RECORD_TYPE ) ) ; } } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


<s> unsigned RISCVInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : { if ( MI . getParent ( ) && MI . getParent ( ) -> getParent ( ) ) { const auto MF = MI . getMF ( ) ; const auto & TM = static_cast < const RISCVTargetMachine & > ( MF -> getTarget ( ) ) ; const MCRegisterInfo & MRI = * TM . getMCRegisterInfo ( ) ; const MCSubtargetInfo & STI = * TM . getMCSubtargetInfo ( ) ; const RISCVSubtarget & ST = MF -> getSubtarget < RISCVSubtarget > ( ) ; if ( isCompressibleInst ( MI , & ST , MRI , STI ) ) return 2 ; } return get ( Opcode ) . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return 0 ; case RISCV :: PseudoCALLReg : case RISCV :: PseudoCALL : case RISCV :: PseudoJump : case RISCV :: PseudoTAIL : case RISCV :: PseudoLLA : case RISCV :: PseudoLA : case RISCV :: PseudoLA_TLS_IE : case RISCV :: PseudoLA_TLS_GD : return 8 ; case RISCV :: PseudoAtomicLoadNand32 : case RISCV :: PseudoAtomicLoadNand64 : return 20 ; case RISCV :: PseudoMaskedAtomicSwap32 : case RISCV :: PseudoMaskedAtomicLoadAdd32 : case RISCV :: PseudoMaskedAtomicLoadSub32 : return 28 ; case RISCV :: PseudoMaskedAtomicLoadNand32 : return 32 ; case RISCV :: PseudoMaskedAtomicLoadMax32 : case RISCV :: PseudoMaskedAtomicLoadMin32 : return 44 ; case RISCV :: PseudoMaskedAtomicLoadUMax32 : case RISCV :: PseudoMaskedAtomicLoadUMin32 : return 36 ; case RISCV :: PseudoCmpXchg32 : case RISCV :: PseudoCmpXchg64 : return 16 ; case RISCV :: PseudoMaskedCmpXchg32 : return 32 ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const auto & TM = static_cast < const RISCVTargetMachine & > ( MF . getTarget ( ) ) ; return getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } case RISCV :: PseudoVSPILL2_M1 : case RISCV :: PseudoVSPILL2_M2 : case RISCV :: PseudoVSPILL2_M4 : case RISCV :: PseudoVSPILL3_M1 : case RISCV :: PseudoVSPILL3_M2 : case RISCV :: PseudoVSPILL4_M1 : case RISCV :: PseudoVSPILL4_M2 : case RISCV :: PseudoVSPILL5_M1 : case RISCV :: PseudoVSPILL6_M1 : case RISCV :: PseudoVSPILL7_M1 : case RISCV :: PseudoVSPILL8_M1 : case RISCV :: PseudoVRELOAD2_M1 : case RISCV :: PseudoVRELOAD2_M2 : case RISCV :: PseudoVRELOAD2_M4 : case RISCV :: PseudoVRELOAD3_M1 : case RISCV :: PseudoVRELOAD3_M2 : case RISCV :: PseudoVRELOAD4_M1 : case RISCV :: PseudoVRELOAD4_M2 : case RISCV :: PseudoVRELOAD5_M1 : case RISCV :: PseudoVRELOAD6_M1 : case RISCV :: PseudoVRELOAD7_M1 : case RISCV :: PseudoVRELOAD8_M1 : { unsigned NF = isRVVSpillForZvlsseg ( Opcode ) -> first ; return 4 * ( 2 * NF - 1 ) ; } } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> void AArch64Operand :: dump ( ) const { print ( errs ( ) ) ; } </s>

Dump the plan to stderr ( for debugging ) .


<s> unsigned AlphaRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return hasFP ( MF ) ? Alpha :: R15 : Alpha :: R30 ; } </s>


<s> unsigned CSKYInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : return 0 ; case CSKY :: LD16B : case CSKY :: LD16H : case CSKY :: LD16W : case CSKY :: LD32B : case CSKY :: LD32BS : case CSKY :: LD32H : case CSKY :: LD32HS : case CSKY :: LD32W : case CSKY :: FLD_S : case CSKY :: FLD_D : case CSKY :: f2FLD_S : case CSKY :: f2FLD_D : case CSKY :: RESTORE_CARRY : break ; } if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> void ScheduleDAGPostRA :: computeDFSResult ( ) { if ( ! DFSResult ) DFSResult = new SchedDFSResult ( true , MinSubtreeSize ) ; DFSResult -> clear ( ) ; ScheduledTrees . clear ( ) ; DFSResult -> resize ( SUnits . size ( ) ) ; DFSResult -> compute ( SUnits ) ; ScheduledTrees . resize ( DFSResult -> getNumSubtrees ( ) ) ; } </s>

Compute a DFSResult after DAG building is complete , and before any queue comparisons .


<s> unsigned getCSRFirstUseCost ( ) const override { return 5 ; } </s>

Allow the target to override the cost of using a callee-saved register for the first time .


<s>
EVT
MipsTargetLowering
::
getOptimalMemOpType
(
const
MemOp
&
Op
,
const
AttributeList
&
FuncAttributes
)
const
{
bool
IsNonZeroMemset
=
Op
.
isMemset
(
)
&&
!
Op
.
isZeroMemset
(
)
;
Align
CapAlign
=
Subtarget
.
isCheri
(
)
Subtarget
.
getCapAlignment
(
)
:
Align
(
)
;
if
(
CapAlign
>
1
&&
Op
.
size
(
)
>=
CapAlign
.
value
(
)
&&
!
IsNonZeroMemset
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
__func__
<<
" Size="
<<
Op
.
size
(
)
<<
" DstAlign="
<<
(
Op
.
isFixedDstAlign
(
)
Op
.
getDstAlign
(
)
.
value
(
)
:
0
)
<<
" SrcAlign="
<<
(
Op
.
isMemset
(
)
0
:
Op
.
getSrcAlign
(
)
.
value
(
)
)
<<
" CapAlign="
<<
CapAlign
.
value
(
)
<<
"\n"
)
;
if
(
Op
.
isAligned
(
CapAlign
)
)
{
return
CapType
;
}
else
if
(
!
Op
.
isMemset
(
)
)
{
return
MVT
::
isVoid
;
}
if
(
Subtarget
.
isGP64bit
(
)
&&
Op
.
isAligned
(
Align
(
8
)
)
)
return
MVT
::
i64
;
if
(
Op
.
isAligned
(
Align
(
4
)
)
)
return
MVT
::
i32
;
if
(
Op
.
isAligned
(
Align
(
2
)
)
)
return
MVT
::
i16
;
return
MVT
::
i8
;
}
if
(
Subtarget
.
isGP64bit
(
)
)
return
MVT
::
i64
;
return
MVT
::
i32
;
}
</s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> MCSymbol * AArch64AsmPrinter :: GetCPISymbol ( unsigned CPID ) const { if ( ! getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) . empty ( ) ) return OutContext . getOrCreateSymbol ( Twine ( getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) ) + "CPI" + Twine ( getFunctionNumber ( ) ) + "_" + Twine ( CPID ) ) ; return OutContext . getOrCreateSymbol ( Twine ( getDataLayout ( ) . getPrivateGlobalPrefix ( ) ) + "CPI" + Twine ( getFunctionNumber ( ) ) + "_" + Twine ( CPID ) ) ; } </s>

Return the symbol for the specified constant pool entry .


"Invalid machine instruction detected, can't predicate!"

Convert the instruction into a predicated instruction .


<s> bool HexagonInstrInfo :: areMemAccessesTriviallyDisjoint ( MachineInstr * MIa , MachineInstr * MIb , AliasAnalysis * AA ) const { int OffsetA = 0 , OffsetB = 0 ; unsigned SizeA = 0 , SizeB = 0 ; if ( MIa -> hasUnmodeledSideEffects ( ) || MIb -> hasUnmodeledSideEffects ( ) || MIa -> hasOrderedMemoryRef ( ) || MIb -> hasOrderedMemoryRef ( ) ) return false ; if ( MIa -> mayLoad ( ) && ! isMemOp ( MIa ) && MIb -> mayLoad ( ) && ! isMemOp ( MIb ) ) return true ; unsigned BaseRegA = getBaseAndOffset ( MIa , OffsetA , SizeA ) ; if ( ! BaseRegA || ! SizeA ) return false ; unsigned BaseRegB = getBaseAndOffset ( MIb , OffsetB , SizeB ) ; if ( ! BaseRegB || ! SizeB ) return false ; if ( BaseRegA != BaseRegB ) return false ; if ( OffsetA > OffsetB ) { uint64_t offDiff = ( uint64_t ) ( ( int64_t ) OffsetA - ( int64_t ) OffsetB ) ; return ( SizeB <= offDiff ) ; } else if ( OffsetA < OffsetB ) { uint64_t offDiff = ( uint64_t ) ( ( int64_t ) OffsetB - ( int64_t ) OffsetA ) ; return ( SizeA <= offDiff ) ; } return false ; } </s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> unsigned AMDGPUSubtarget :: getOccupancyWithLocalMemSize ( uint32_t Bytes ) const { if ( Bytes <= 1638 ) return 10 ; if ( Bytes <= 1820 ) return 9 ; if ( Bytes <= 2048 ) return 8 ; if ( Bytes <= 2340 ) return 7 ; if ( Bytes <= 2730 ) return 6 ; if ( Bytes <= 3276 ) return 5 ; if ( Bytes <= 4096 ) return 4 ; if ( Bytes <= 5461 ) return 3 ; if ( Bytes <= 8192 ) return 2 ; return 1 ; } </s>

Inverse of getMaxLocalMemWithWaveCount .


<s> unsigned ARMBaseRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; const ARMFrameLowering * TFI = getFrameLowering ( MF ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case ARM :: tGPRRegClassID : return TFI -> hasFP ( MF ) ? 4 : 5 ; case ARM :: GPRRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 10 - FP - ( STI . isR9Reserved ( ) ? 1 : 0 ) ; } case ARM :: SPRRegClassID : case ARM :: DPRRegClassID : return 32 - 10 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> static void mmix_conditional_register_usage ( void ) { int i ; if ( TARGET_ABI_GNU ) { static const int gnu_abi_reg_alloc_order [ ] = MMIX_GNU_ABI_REG_ALLOC_ORDER ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) reg_alloc_order [ i ] = gnu_abi_reg_alloc_order [ i ] ; for ( i = 15 ; i <= 30 ; i ++ ) call_used_regs [ i ] = 0 ; for ( i = MMIX_RESERVED_GNU_ARG_0_REGNUM ; i < MMIX_RESERVED_GNU_ARG_0_REGNUM + MMIX_MAX_ARGS_IN_REGS ; i ++ ) fixed_regs [ i ] = 0 ; } if ( ! TARGET_TOPLEVEL_SYMBOLS ) for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( reg_names [ i ] [ 0 ] == ':' ) reg_names [ i ] ++ ; } </s>


<s> bool X86TargetLowering :: isCheapToSpeculateCttz ( ) const { return Subtarget -> hasBMI ( ) ; } </s>

Return true if it is cheap to speculate a call to intrinsic cttz .


<s> static rtx m68k_function_arg ( cumulative_args_t cum ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , const_tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { return NULL_RTX ; } </s>

On the m68k all args are always pushed .


<s> uint64_t VEMCCodeEmitter :: getBranchTargetOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , ( MCFixupKind ) VE :: fixup_ve_srel32 ) ) ; return 0 ; } </s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s> static enum loongarch_symbol_type loongarch_classify_symbolic_expression ( rtx x ) { rtx offset ; split_const ( x , & x , & offset ) ; if ( UNSPEC_ADDRESS_P ( x ) ) return UNSPEC_ADDRESS_TYPE ( x ) ; return loongarch_classify_symbol ( x ) ; } </s>

Classify the base of symbolic expression X , given that X appears in context CONTEXT .


<s> AMDGPUAAResult run ( Function & F , AnalysisManager < Function > & AM ) { return AMDGPUAAResult ( F . getParent ( ) -> getDataLayout ( ) , Triple ( F . getParent ( ) -> getTargetTriple ( ) ) ) ; } </s>

Run the analysis pass over a function and produce a dominator tree .


<s> bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , const BranchProbability & Probability ) const override { return NumCycles == 1 ; } </s>

Return true if it 's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < BPFSubtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> static int loongarch_flatten_aggregate_argument ( const_tree type , loongarch_aggregate_field fields [ 2 ] ) { if ( ! type || TREE_CODE ( type ) != RECORD_TYPE ) return - 1 ; return loongarch_flatten_aggregate_field ( type , fields , 0 , 0 ) ; } </s>

Identify candidate aggregates for passing in floating-point registers . Candidates have at most two fields after flattening .


<s>
EVT
RISCVTargetLowering
::
getOptimalMemOpType
(
const
MemOp
&
Op
,
const
AttributeList
&
FuncAttributes
)
const
{
bool
IsNonZeroMemset
=
Op
.
isMemset
(
)
&&
!
Op
.
isZeroMemset
(
)
;
if
(
Subtarget
.
hasCheri
(
)
&&
!
IsNonZeroMemset
)
{
unsigned
CapSize
=
Subtarget
.
typeForCapabilities
(
)
.
getSizeInBits
(
)
/
8
;
if
(
Op
.
size
(
)
>=
CapSize
)
{
Align
CapAlign
(
CapSize
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
__func__
<<
" Size="
<<
Op
.
size
(
)
<<
" DstAlign="
<<
(
Op
.
isFixedDstAlign
(
)
Op
.
getDstAlign
(
)
.
value
(
)
:
0
)
<<
" SrcAlign="
<<
(
Op
.
isMemset
(
)
0
:
Op
.
getSrcAlign
(
)
.
value
(
)
)
<<
" CapSize="
<<
CapSize
<<
"\n"
)
;
if
(
Op
.
isAligned
(
CapAlign
)
)
{
return
CapType
;
}
else
if
(
!
Op
.
isMemset
(
)
)
{
return
MVT
::
isVoid
;
}
}
}
return
TargetLowering
::
getOptimalMemOpType
(
Op
,
FuncAttributes
)
;
}
</s>

RISCV
RISCV
8
" Size="
" DstAlign="
0
" SrcAlign="
0
" CapSize="
"\n"
MVT::isVoid


<s> static bool expand_vselect ( rtx target , rtx op0 , const unsigned char * perm , unsigned nelt ) { rtx rperm [ MAX_VECT_LEN ] , x ; unsigned i ; for ( i = 0 ; i < nelt ; ++ i ) rperm [ i ] = GEN_INT ( perm [ i ] ) ; x = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( nelt , rperm ) ) ; x = gen_rtx_VEC_SELECT ( GET_MODE ( target ) , op0 , x ) ; x = gen_rtx_SET ( target , x ) ; rtx_insn * insn = emit_insn ( x ) ; if ( recog_memoized ( insn ) < 0 ) { remove_insn ( insn ) ; return false ; } return true ; } </s>

Construct ( set target ( vec_select op0 ( parallel perm ) ) ) and return true if that 's a valid instruction in the active ISA .


<s> static void do_cmpb3 ( rtx dest , rtx src1 , rtx src2 ) { if ( GET_MODE ( dest ) == DImode ) emit_insn ( gen_cmpbdi3 ( dest , src1 , src2 ) ) ; else emit_insn ( gen_cmpbsi3 ( dest , src1 , src2 ) ) ; } </s>

Emit an cmpb of the proper mode for DEST . DEST is the destination register for the cmpb . SRC1 is the first input . SRC2 is the second input . Computes cmpb of SRC1 , SRC2 .


"%qE attribute only applies to variables"

"%qE attribute not allowed with auto storage class"

Handle a `` shared '' attribute ; arguments as in struct attribute_spec.handler .


<s> bool DLXRegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & ) const { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> bool canOpTrap ( unsigned Op , EVT VT ) const override { return false ; } </s>

Returns true if the operation can trap for the value type .


"Running spec function '%s' with %d args\n\n"

"strange device name %qs after %qs: bad character %qc"

Implement spec function ` device-specs-file麓 . Compose -specs= < specs-file-name > % s . If everything went well then argv [ 0 ] is the inflated ( absolute ) specs directory and argv [ 1 ] is a device or core name as supplied by -mmcu= * . When building GCC the path might be relative .


Return a mask of call-preserved registers for the given calling convention on the current function .


<s> FastISel * ARM :: createFastISel ( FunctionLoweringInfo & funcInfo ) { const TargetMachine & TM = funcInfo . MF -> getTarget ( ) ; const ARMSubtarget * Subtarget = & TM . getSubtarget < ARMSubtarget > ( ) ; if ( Subtarget -> isTargetIOS ( ) && ! Subtarget -> isThumb1Only ( ) ) return new ARMFastISel ( funcInfo ) ; return 0 ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> void m32c_conditional_register_usage ( void ) { int memregs ; int i ; if ( 0 <= target_memregs && target_memregs <= 16 ) { for ( i = target_memregs / 2 ; i < 8 ; i ++ ) { fixed_regs [ MEM0_REGNO + i ] = 1 ; CLEAR_HARD_REG_BIT ( reg_class_contents [ MEM_REGS ] , MEM0_REGNO + i ) ; } } if ( TARGET_A24 ) { call_used_regs [ R1_REGNO ] = 0 ; call_used_regs [ R2_REGNO ] = 0 ; call_used_regs [ R3_REGNO ] = 0 ; call_used_regs [ A0_REGNO ] = 0 ; call_used_regs [ A1_REGNO ] = 0 ; } } </s>

Implements CONDITIONAL_REGISTER_USAGE . We adjust the number of available memregs , and select which registers need to be preserved across calls based on the chip family .


<s> int m32c_expand_movcc ( rtx * operands ) { rtx rel = operands [ 1 ] ; if ( GET_CODE ( rel ) != EQ && GET_CODE ( rel ) != NE ) return 1 ; if ( GET_CODE ( operands [ 2 ] ) != CONST_INT || GET_CODE ( operands [ 3 ] ) != CONST_INT ) return 1 ; if ( GET_CODE ( rel ) == NE ) { rtx tmp = operands [ 2 ] ; operands [ 2 ] = operands [ 3 ] ; operands [ 3 ] = tmp ; rel = gen_rtx_EQ ( GET_MODE ( rel ) , XEXP ( rel , 0 ) , XEXP ( rel , 1 ) ) ; } emit_move_insn ( operands [ 0 ] , gen_rtx_IF_THEN_ELSE ( GET_MODE ( operands [ 0 ] ) , rel , operands [ 2 ] , operands [ 3 ] ) ) ; return 0 ; } </s>


<s> unsigned X86TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT == MVT :: v32i1 && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return 1 ; return TargetLowering :: getNumRegistersForCallingConv ( Context , CC , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s> void PPCHazardRecognizer970 :: EmitInstruction ( SUnit * SU ) { MachineInstr * MI = SU -> getInstr ( ) ; if ( MI -> isDebugValue ( ) ) return ; unsigned Opcode = MI -> getOpcode ( ) ; bool isFirst , isSingle , isCracked , isLoad , isStore ; PPCII :: PPC970_Unit InstrType = GetInstrType ( Opcode , isFirst , isSingle , isCracked , isLoad , isStore ) ; if ( InstrType == PPCII :: PPC970_Pseudo ) return ; if ( Opcode == PPC :: MTCTR || Opcode == PPC :: MTCTR8 ) HasCTRSet = true ; if ( isStore && NumStores < 4 && ! MI -> memoperands_empty ( ) ) { MachineMemOperand * MO = * MI -> memoperands_begin ( ) ; StoreSize [ NumStores ] = MO -> getSize ( ) ; StoreOffset [ NumStores ] = MO -> getOffset ( ) ; StoreValue [ NumStores ] = MO -> getValue ( ) ; ++ NumStores ; } if ( InstrType == PPCII :: PPC970_BRU || isSingle ) NumIssued = 4 ; ++ NumIssued ; if ( isCracked ) ++ NumIssued ; if ( NumIssued == 5 ) EndDispatchGroup ( ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


"Do not know how to custom type legalize this operation!"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


"Can only put epilog before 'retl' instruction!"


"X86-64 PIC uses RIP relative addressing"

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s>
lm32_return_addr_rtx
(
count
,
frame
)
{
{
FRAME_POINTER_REGNUM
,
STACK_POINTER_REGNUM
}
,
\
{
ARG_POINTER_REGNUM
,
STACK_POINTER_REGNUM
}
,
\
}
(
OFFSET
)
=
lm32_compute_initial_elimination_offset
(
FROM
,
TO
)
(
CUM
)
=
0
(
(
(
r
)
>=
LM32_FIRST_ARG_REG
)
&&
(
(
r
)
<=
LM32_NUM_ARG_REGS
)
)
gen_rtx_REG
(
(
INTEGRAL_TYPE_P
(
VALTYPE
)
\
&&
TYPE_PRECISION
(
VALTYPE
)
<
BITS_PER_WORD
)
\
word_mode
\
:
TYPE_MODE
(
VALTYPE
)
,
\
RV_REGNUM
)
LM32_NUM_INTS
(
(
MODE
)
==
BLKmode
\
int_size_in_bytes
(
TYPE
)
:
GET_MODE_SIZE
(
MODE
)
)
(
(
GET_CODE
(
X
)
==
LABEL_REF
||
GET_CODE
(
X
)
==
SYMBOL_REF
\
||
GET_CODE
(
X
)
==
CONST_INT
||
GET_CODE
(
X
)
==
HIGH
\
||
(
GET_CODE
(
X
)
==
CONST
)
)
)
(
REGNO_OK_FOR_BASE_P
(
REGNO
(
X
)
)
)
(
G_REG_P
(
REGNO
(
X
)
)
||
!
HARD_REGISTER_NUM_P
(
REGNO
(
X
)
)
)
(
!
(
nonpic_symbol_mentioned_p
(
X
)
)
)
do
{
\
fputc
(
'\t'
,
FILE
)
;
\
assemble_name
(
FILE
,
LABEL1
)
;
\
fputs
(
" = "
,
FILE
)
;
\
assemble_name
(
FILE
,
LABEL2
)
;
\
fputc
(
'\n'
,
FILE
)
;
\
}
while
(
0
)
do
{
\
if
(
(
SIZE
)
<=
(
unsigned
HOST_WIDE_INT
)
g_switch_value
)
\
switch_to_section
(
sbss_section
)
;
\
else
\
switch_to_section
(
bss_section
)
;
\
ASM_OUTPUT_TYPE_DIRECTIVE
(
FILE
,
NAME
,
"object"
)
;
\
if
(
!
flag_inhibit_size_directive
)
\
ASM_OUTPUT_SIZE_DIRECTIVE
(
FILE
,
NAME
,
SIZE
)
;
\
ASM_OUTPUT_ALIGN
(
(
FILE
)
,
exact_log2
(
(
ALIGN
)
/
BITS_PER_UNIT
)
)
;
\
ASM_OUTPUT_LABEL
(
FILE
,
NAME
)
;
\
ASM_OUTPUT_SKIP
(
(
FILE
)
,
(
SIZE
)
(
SIZE
)
:
1
)
;
\
}
while
(
0
)
do
\
{
\
if
(
(
SIZE
)
<=
(
unsigned
HOST_WIDE_INT
)
g_switch_value
)
\
{
\
switch_to_section
(
sbss_section
)
;
\
(
*
targetm
.
asm_out
.
globalize_label
)
(
FILE
,
NAME
)
;
\
ASM_OUTPUT_TYPE_DIRECTIVE
(
FILE
,
NAME
,
"object"
)
;
\
if
(
!
flag_inhibit_size_directive
)
\
ASM_OUTPUT_SIZE_DIRECTIVE
(
FILE
,
NAME
,
SIZE
)
;
\
ASM_OUTPUT_ALIGN
(
(
FILE
)
,
exact_log2
(
(
ALIGN
)
/
BITS_PER_UNIT
)
)
;
\
ASM_OUTPUT_LABEL
(
FILE
,
NAME
)
;
\
ASM_OUTPUT_SKIP
(
(
FILE
)
,
(
SIZE
)
(
SIZE
)
:
1
)
;
\
}
</s>

Support function to determine the return address of the function 'count ' frames back up the stack .


<s> static void swap_reorder ( rtx_insn * * a , int n ) { rtx_insn * insn = a [ n - 1 ] ; int i = n - 2 ; while ( i >= 0 && rank_for_reorder ( a + i , & insn ) >= 0 ) { a [ i + 1 ] = a [ i ] ; i -= 1 ; } a [ i + 1 ] = insn ; } </s>

Resort the array A in which only element at index N may be out of order .


<s> static unsigned getReg ( const MCDisassembler * D , unsigned RC , unsigned RegNo ) { const MCRegisterInfo * RegInfo = D -> getContext ( ) . getRegisterInfo ( ) ; return * ( RegInfo -> getRegClass ( RC ) . begin ( ) + RegNo ) ; } </s>

Returns the register associated with this edge .


<s>
void
AlphaRegisterInfo
::
emitPrologue
(
MachineFunction
&
MF
)
const
{
MachineBasicBlock
&
MBB
=
MF
.
front
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
DebugLoc
dl
=
(
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
(
)
)
;
bool
FP
=
hasFP
(
MF
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
LDAHg
)
,
Alpha
::
R29
)
.
addGlobalAddress
(
MF
.
getFunction
(
)
)
.
addReg
(
Alpha
::
R27
)
.
addImm
(
++
curgpdist
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
LDAg
)
,
Alpha
::
R29
)
.
addGlobalAddress
(
MF
.
getFunction
(
)
)
.
addReg
(
Alpha
::
R29
)
.
addImm
(
curgpdist
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
ALTENT
)
)
.
addGlobalAddress
(
MF
.
getFunction
(
)
)
;
long
NumBytes
=
MFI
->
getStackSize
(
)
;
if
(
FP
)
NumBytes
+=
8
;
if
(
NumBytes
==
0
)
return
;
unsigned
Align
=
MF
.
getTarget
(
)
.
getFrameInfo
(
)
->
getStackAlignment
(
)
;
NumBytes
=
(
NumBytes
+
Align
1
)
/
Align
*
Align
;
MFI
->
setStackSize
(
NumBytes
)
;
NumBytes
=
NumBytes
;
if
(
NumBytes
>=
IMM_LOW
)
{
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
LDA
)
,
Alpha
::
R30
)
.
addImm
(
NumBytes
)
.
addReg
(
Alpha
::
R30
)
;
}
else
if
(
getUpper16
(
NumBytes
)
>=
IMM_LOW
)
{
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
LDAH
)
,
Alpha
::
R30
)
.
addImm
(
getUpper16
(
NumBytes
)
)
.
addReg
(
Alpha
::
R30
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
LDA
)
,
Alpha
::
R30
)
.
addImm
(
getLower16
(
NumBytes
)
)
.
addReg
(
Alpha
::
R30
)
;
}
else
{
report_fatal_error
(
"Too big a stack frame at "
+
Twine
(
NumBytes
)
)
;
}
if
(
FP
)
{
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
STQ
)
)
.
addReg
(
Alpha
::
R15
)
.
addImm
(
0
)
.
addReg
(
Alpha
::
R30
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
BISr
)
,
Alpha
::
R15
)
.
addReg
(
Alpha
::
R30
)
.
addReg
(
Alpha
::
R30
)
;
}
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static bool classof ( const MCExpr * E ) { return E -> getKind ( ) == MCExpr :: Target ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s>
MachineBasicBlock
*
SparcTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
const
TargetInstrInfo
&
TII
=
*
getTargetMachine
(
)
.
getInstrInfo
(
)
;
unsigned
BROpcode
;
unsigned
CC
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown SELECT_CC!"
)
;
case
SP
::
SELECT_CC_Int_ICC
:
case
SP
::
SELECT_CC_FP_ICC
:
case
SP
::
SELECT_CC_DFP_ICC
:
BROpcode
=
SP
::
BCOND
;
break
;
case
SP
::
SELECT_CC_Int_FCC
:
case
SP
::
SELECT_CC_FP_FCC
:
case
SP
::
SELECT_CC_DFP_FCC
:
BROpcode
=
SP
::
FBCOND
;
break
;
}
CC
=
(
SPCC
::
CondCodes
)
MI
->
getOperand
(
3
)
.
getImm
(
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
It
=
BB
;
++
It
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
sinkMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
sinkMBB
->
splice
(
sinkMBB
->
begin
(
)
,
BB
,
llvm
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
BB
->
end
(
)
)
;
sinkMBB
->
transferSuccessorsAndUpdatePHIs
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
sinkMBB
)
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
BROpcode
)
)
.
addMBB
(
sinkMBB
)
.
addImm
(
CC
)
;
F
->
insert
(
It
,
copy0MBB
)
;
F
->
insert
(
It
,
sinkMBB
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
sinkMBB
;
BuildMI
(
*
BB
,
BB
->
begin
(
)
,
dl
,
TII
.
get
(
SP
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
MI
->
eraseFromParent
(
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s>
bool
PIC16AsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
this
->
MF
=
&
MF
;
SetupMachineFunction
(
MF
)
;
const
Function
*
F
=
MF
.
getFunction
(
)
;
CurrentFnName
=
Mang
->
getValueName
(
F
)
;
EmitFunctionFrame
(
MF
)
;
DbgInfo
.
EmitFunctBeginDI
(
F
)
;
EmitAutos
(
CurrentFnName
)
;
const
char
*
codeSection
=
PAN
::
getCodeSectionName
(
CurrentFnName
)
.
c_str
(
)
;
const
Section
*
fCodeSection
=
TAI
->
getNamedSection
(
codeSection
,
SectionFlags
::
Code
)
;
O
<<
"\n"
;
SwitchToSection
(
fCodeSection
)
;
O
<<
"\tretlw  low("
<<
PAN
::
getFrameLabel
(
CurrentFnName
)
<<
")\n"
;
O
<<
"\tretlw  high("
<<
PAN
::
getFrameLabel
(
CurrentFnName
)
<<
")\n"
;
O
<<
CurrentFnName
<<
":\n"
;
unsigned
CurLine
=
0
;
O
<<
"\n"
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
I
!=
MF
.
begin
(
)
)
{
printBasicBlockLabel
(
I
,
true
)
;
O
<<
'\n'
;
}
for
(
MachineBasicBlock
::
const_iterator
II
=
I
->
begin
(
)
,
E
=
I
->
end
(
)
;
II
!=
E
;
++
II
)
{
const
DebugLoc
DL
=
II
->
getDebugLoc
(
)
;
if
(
!
DL
.
isUnknown
(
)
)
{
unsigned
line
=
MF
.
getDebugLocTuple
(
DL
)
.
Line
;
if
(
line
!=
CurLine
)
{
O
<<
"\t.line "
<<
line
<<
"\n"
;
CurLine
=
line
;
}
}
printMachineInstruction
(
II
)
;
}
}
DbgInfo
.
EmitFunctEndDI
(
F
,
CurLine
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool mep_secondary_memory_needed ( enum reg_class rclass1 , enum reg_class rclass2 , machine_mode mode ATTRIBUTE_UNUSED ) { if ( ! mep_have_core_copro_moves_p ) { if ( reg_classes_intersect_p ( rclass1 , CR_REGS ) && reg_classes_intersect_p ( rclass2 , GENERAL_REGS ) ) return true ; if ( reg_classes_intersect_p ( rclass2 , CR_REGS ) && reg_classes_intersect_p ( rclass1 , GENERAL_REGS ) ) return true ; if ( ! mep_have_copro_copro_moves_p && reg_classes_intersect_p ( rclass1 , CR_REGS ) && reg_classes_intersect_p ( rclass2 , CR_REGS ) ) return true ; } return false ; } </s>


<s>
SDValue
DCPU16TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ExternalSymbol
:
return
LowerExternalSymbol
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SIGN_EXTEND
:
return
LowerSIGN_EXTEND
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
ROTL
:
return
LowerROT
(
Op
,
DAG
,
true
)
;
case
ISD
::
ROTR
:
return
LowerROT
(
Op
,
DAG
,
false
)
;
case
ISD
::
SMUL_LOHI
:
return
LowerMUL_LOHI
(
Op
,
DAG
,
true
)
;
case
ISD
::
UMUL_LOHI
:
return
LowerMUL_LOHI
(
Op
,
DAG
,
false
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> static HOST_WIDE_INT lm32_starting_frame_offset ( void ) { return UNITS_PER_WORD ; } </s>


"Cannot align scalable vectors more than 16 bytes"

"There must be a free register after frame setup"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> BitVector XCoreRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( XCore :: CP ) ; Reserved . set ( XCore :: DP ) ; Reserved . set ( XCore :: SP ) ; Reserved . set ( XCore :: LR ) ; if ( hasFP ( MF ) ) { Reserved . set ( XCore :: R10 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .

XCore XCore XCore::CP XCore::DP XCore::SP XCore::LR XCore::R10


<s> void PatmosDAGToDAGISel :: Select ( SDNode * Node ) { if ( Node -> isMachineOpcode ( ) ) return ; switch ( Node -> getOpcode ( ) ) { default : break ; } SelectCode ( Node ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> SMLoc Z80Operand :: getEndLoc ( ) const { return this -> EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> static bool s390_function_arg_float ( enum machine_mode mode , tree type ) { int size = s390_function_arg_size ( mode , type ) ; if ( size > 8 ) return false ; if ( TARGET_SOFT_FLOAT ) return false ; if ( ! type ) return mode == SFmode || mode == DFmode ; while ( TREE_CODE ( type ) == RECORD_TYPE ) { tree field , single = NULL_TREE ; for ( field = TYPE_FIELDS ( type ) ; field ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( single == NULL_TREE ) single = TREE_TYPE ( field ) ; else return false ; } if ( single == NULL_TREE ) return false ; else type = single ; } return TREE_CODE ( type ) == REAL_TYPE ; } </s>

Return true if a function argument of type TYPE and mode MODE is to be passed in a floating-point register , if available .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"X86 Machine Code Emitter"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void LC3bAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( MI -> isDebugValue ( ) ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; PrintDebugValueComment ( MI , OS ) ; return ; } MCInst TmpInst0 ; MCInstLowering . Lower ( MI , TmpInst0 ) ; OutStreamer . EmitInstruction ( TmpInst0 ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


"Can only insert epilog into returning blocks"


<s>
bool
AArch64InstrInfo
::
optimizeCondBranch
(
MachineInstr
*
MI
)
const
{
bool
IsNegativeBranch
=
false
;
bool
IsTestAndBranch
=
false
;
unsigned
TargetBBInMI
=
0
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown branch instruction?"
)
;
case
AArch64
::
Bcc
:
return
false
;
case
AArch64
::
CBZW
:
case
AArch64
::
CBZX
:
TargetBBInMI
=
1
;
break
;
case
AArch64
::
CBNZW
:
case
AArch64
::
CBNZX
:
TargetBBInMI
=
1
;
IsNegativeBranch
=
true
;
break
;
case
AArch64
::
TBZW
:
case
AArch64
::
TBZX
:
TargetBBInMI
=
2
;
IsTestAndBranch
=
true
;
break
;
case
AArch64
::
TBNZW
:
case
AArch64
::
TBNZX
:
TargetBBInMI
=
2
;
IsNegativeBranch
=
true
;
IsTestAndBranch
=
true
;
break
;
}
if
(
IsTestAndBranch
&&
MI
->
getOperand
(
1
)
.
getImm
(
)
)
return
false
;
assert
(
MI
->
getParent
(
)
&&
"Incomplete machine instruciton\n"
)
;
MachineBasicBlock
*
MBB
=
MI
->
getParent
(
)
;
MachineFunction
*
MF
=
MBB
->
getParent
(
)
;
MachineRegisterInfo
*
MRI
=
&
MF
->
getRegInfo
(
)
;
unsigned
VReg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
if
(
!
TargetRegisterInfo
::
isVirtualRegister
(
VReg
)
)
return
false
;
MachineInstr
*
DefMI
=
MRI
->
getVRegDef
(
VReg
)
;
if
(
!
(
DefMI
->
getOpcode
(
)
==
AArch64
::
CSINCWr
&&
DefMI
->
getOperand
(
1
)
.
getReg
(
)
==
AArch64
::
WZR
&&
DefMI
->
getOperand
(
2
)
.
getReg
(
)
==
AArch64
::
WZR
)
&&
!
(
DefMI
->
getOpcode
(
)
==
AArch64
::
CSINCXr
&&
DefMI
->
getOperand
(
1
)
.
getReg
(
)
==
AArch64
::
XZR
&&
DefMI
->
getOperand
(
2
)
.
getReg
(
)
==
AArch64
::
XZR
)
)
return
false
;
if
(
DefMI
->
findRegisterDefOperandIdx
(
AArch64
::
NZCV
,
true
)
!=
1
)
return
false
;
AArch64CC
::
CondCode
CC
=
(
AArch64CC
::
CondCode
)
DefMI
->
getOperand
(
3
)
.
getImm
(
)
;
bool
CheckOnlyCCWrites
=
true
;
if
(
modifiesConditionCode
(
DefMI
,
MI
,
CheckOnlyCCWrites
,
&
getRegisterInfo
(
)
)
)
return
false
;
MachineBasicBlock
&
RefToMBB
=
*
MBB
;
MachineBasicBlock
*
TBB
=
MI
->
getOperand
(
TargetBBInMI
)
.
getMBB
(
)
;
DebugLoc
DL
=
MI
->
getDebugLoc
(
)
;
if
(
IsNegativeBranch
)
CC
=
AArch64CC
::
getInvertedCondCode
(
CC
)
;
BuildMI
(
RefToMBB
,
MI
,
DL
,
get
(
AArch64
::
Bcc
)
)
.
addImm
(
CC
)
.
addMBB
(
TBB
)
;
MI
->
eraseFromParent
(
)
;
return
true
;
}
</s>

Replace csincr-branch sequence by simple conditional branch .


<s> static void do_unlink ( rtx spreg , HOST_WIDE_INT frame_size , bool all ) { frame_size += arg_area_size ( ) ; if ( all || stack_frame_needed_p ( ) ) emit_insn ( gen_unlink ( ) ) ; else { rtx postinc = gen_rtx_MEM ( Pmode , gen_rtx_POST_INC ( Pmode , spreg ) ) ; add_to_sp ( spreg , frame_size , 0 ) ; if ( must_save_fp_p ( ) ) { rtx fpreg = gen_rtx_REG ( Pmode , REG_FP ) ; emit_move_insn ( fpreg , postinc ) ; emit_insn ( gen_rtx_USE ( VOIDmode , fpreg ) ) ; } if ( ! current_function_is_leaf ) { emit_move_insn ( bfin_rets_rtx , postinc ) ; emit_insn ( gen_rtx_USE ( VOIDmode , bfin_rets_rtx ) ) ; } } } </s>

Like do_link , but used for epilogues to deallocate the stack frame .


<s> unsigned RISCVAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { RISCVOperand & Op = static_cast < RISCVOperand & > ( AsmOp ) ; if ( ! Op . isReg ( ) ) return Match_InvalidOperand ; Register Reg = Op . getReg ( ) ; bool IsRegFPR64 = RISCVMCRegisterClasses [ RISCV :: FPR64RegClassID ] . contains ( Reg ) ; bool IsRegFPR64C = RISCVMCRegisterClasses [ RISCV :: FPR64CRegClassID ] . contains ( Reg ) ; if ( ( IsRegFPR64 && Kind == MCK_FPR32 ) || ( IsRegFPR64C && Kind == MCK_FPR32C ) ) { Op . Reg . RegNum = convertFPR64ToFPR32 ( Reg ) ; return Match_Success ; } return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .

RISCV RISCV RISCV RISCV RISCV RISCV::FPR64RegClassID RISCV RISCV::FPR64CRegClassID


<s> bool PPCTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( ! EnablePPCPreinc ) return false ; SDValue Ptr ; EVT VT ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { ST = ST ; Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; } else return false ; if ( VT . isVector ( ) ) return false ; if ( VT != MVT :: i64 ) { if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG ) ) return false ; } else { if ( ! SelectAddressRegImmShift ( Ptr , Offset , Base , DAG ) ) return false ; } if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { if ( LD -> getValueType ( 0 ) == MVT :: i64 && LD -> getMemoryVT ( ) == MVT :: i32 && LD -> getExtensionType ( ) == ISD :: SEXTLOAD && isa < ConstantSDNode > ( Offset ) ) return false ; } AM = ISD :: PRE_INC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .


<s> static rsqrte_type get_rsqrte_type ( machine_mode mode ) { switch ( mode ) { case E_DFmode : return gen_aarch64_rsqrtedf ; case E_SFmode : return gen_aarch64_rsqrtesf ; case E_V2DFmode : return gen_aarch64_rsqrtev2df ; case E_V2SFmode : return gen_aarch64_rsqrtev2sf ; case E_V4SFmode : return gen_aarch64_rsqrtev4sf ; default : gcc_unreachable ( ) ; } } </s>

Select reciprocal square root initial estimate insn depending on machine mode .


<s> int arm_no_early_store_addr_dep ( rtx producer , rtx consumer ) { rtx value = PATTERN ( producer ) ; rtx addr = PATTERN ( consumer ) ; if ( GET_CODE ( value ) == COND_EXEC ) value = COND_EXEC_CODE ( value ) ; if ( GET_CODE ( value ) == PARALLEL ) value = XVECEXP ( value , 0 , 0 ) ; value = XEXP ( value , 0 ) ; if ( GET_CODE ( addr ) == COND_EXEC ) addr = COND_EXEC_CODE ( addr ) ; if ( GET_CODE ( addr ) == PARALLEL ) addr = XVECEXP ( addr , 0 , 0 ) ; addr = XEXP ( addr , 0 ) ; return ! reg_overlap_mentioned_p ( value , addr ) ; } </s>

Return nonzero if the CONSUMER instruction ( a store ) does not need PRODUCER 's value to calculate the address .


"Attempting to lower call as tail call\n"

"... Cannot handle tail calls with swifterror yet.\n"

"... Calling convention cannot be tail called.\n"

"... Cannot tail call from callers with byval, "

"... Cannot tail call externally-defined function "

"Unexpected variadic calling convention"

"... Caller and callee have incompatible calling conventions.\n"

"... Call is eligible for tail call optimization.\n"

Returns true if the call can be lowered as a tail call .