<s> SDNode * SITargetLowering :: PostISelFolding ( MachineSDNode * Node , SelectionDAG & DAG ) const { const SIInstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; unsigned Opcode = Node -> getMachineOpcode ( ) ; if ( TII -> isMIMG ( Opcode ) && ! TII -> get ( Opcode ) . mayStore ( ) && ! TII -> isGather4 ( Opcode ) && AMDGPU :: getNamedOperandIdx ( Opcode , AMDGPU :: OpName :: dmask ) != - 1 ) { return adjustWritemask ( Node , DAG ) ; } if ( Opcode == AMDGPU :: INSERT_SUBREG || Opcode == AMDGPU :: REG_SEQUENCE ) { legalizeTargetIndependentNode ( Node , DAG ) ; return Node ; } switch ( Opcode ) { case AMDGPU :: V_DIV_SCALE_F32 : case AMDGPU :: V_DIV_SCALE_F64 : { SDValue Src0 = Node -> getOperand ( 0 ) ; SDValue Src1 = Node -> getOperand ( 1 ) ; SDValue Src2 = Node -> getOperand ( 2 ) ; if ( ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) != AMDGPU :: IMPLICIT_DEF ) && ( Src0 == Src1 || Src0 == Src2 ) ) break ; MVT VT = Src0 . getValueType ( ) . getSimpleVT ( ) ; const TargetRegisterClass * RC = getRegClassFor ( VT , Src0 . getNode ( ) -> isDivergent ( ) ) ; MachineRegisterInfo & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue UndefReg = DAG . getRegister ( MRI . createVirtualRegister ( RC ) , VT ) ; SDValue ImpDef = DAG . getCopyToReg ( DAG . getEntryNode ( ) , SDLoc ( Node ) , UndefReg , Src0 , SDValue ( ) ) ; if ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) == AMDGPU :: IMPLICIT_DEF ) { if ( Src1 . isMachineOpcode ( ) && Src1 . getMachineOpcode ( ) != AMDGPU :: IMPLICIT_DEF ) Src0 = Src1 ; else if ( Src2 . isMachineOpcode ( ) && Src2 . getMachineOpcode ( ) != AMDGPU :: IMPLICIT_DEF ) Src0 = Src2 ; else { assert ( Src1 . getMachineOpcode ( ) == AMDGPU :: IMPLICIT_DEF ) ; Src0 = UndefReg ; Src1 = UndefReg ; } } else break ; SmallVector < SDValue , 4 > Ops = { Src0 , Src1 , Src2 } ; for ( unsigned I = 3 , N = Node -> getNumOperands ( ) ; I != N ; ++ I ) Ops . push_back ( Node -> getOperand ( I ) ) ; Ops . push_back ( ImpDef . getValue ( 1 ) ) ; return DAG . getMachineNode ( Opcode , SDLoc ( Node ) , Node -> getVTList ( ) , Ops ) ; } default : break ; } return Node ; } </s>

Fold the instructions after selecting them .


<s> bool mips_pad_reg_upward ( enum machine_mode mode , tree type ) { if ( type != 0 ? FLOAT_TYPE_P ( type ) : GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return ! BYTES_BIG_ENDIAN ; return mips_pad_arg_upward ( mode , type ) ; } </s>

Likewise BLOCK_REG_PADDING ( MODE , TYPE , ... ) . Return ! BYTES_BIG_ENDIAN if the least significant byte of the register has useful data . Return the opposite if the most significant byte does .


<s> static inline machine_mode get_mode_wider_vector ( machine_mode o ) { machine_mode n = GET_MODE_WIDER_MODE ( o ) . require ( ) ; gcc_assert ( GET_MODE_NUNITS ( o ) == GET_MODE_NUNITS ( n ) * 2 ) ; gcc_assert ( GET_MODE_SIZE ( o ) == GET_MODE_SIZE ( n ) ) ; return n ; } </s>

Get a vector mode of the same size as the original but with elements twice as wide . This is only guaranteed to apply to integral vectors .


<s>
SDValue
X86TargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
bool
Is64Bit
=
Subtarget
->
is64Bit
(
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_X86
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
CopyVT
=
VA
.
getValVT
(
)
;
if
(
(
CopyVT
==
MVT
::
f32
||
CopyVT
==
MVT
::
f64
)
&&
(
(
Is64Bit
||
Ins
[
i
]
.
Flags
.
isInReg
(
)
)
&&
!
Subtarget
->
hasSSE1
(
)
)
)
{
report_fatal_error
(
"SSE register return with SSE disabled"
)
;
}
if
(
(
VA
.
getLocReg
(
)
==
X86
::
FP0
||
VA
.
getLocReg
(
)
==
X86
::
FP1
)
&&
isScalarFPTypeInSSEReg
(
VA
.
getValVT
(
)
)
)
CopyVT
=
MVT
::
f80
;
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
CopyVT
,
InFlag
)
.
getValue
(
1
)
;
SDValue
Val
=
Chain
.
getValue
(
0
)
;
if
(
CopyVT
!=
VA
.
getValVT
(
)
)
Val
=
DAG
.
getNode
(
ISD
::
FP_ROUND
,
dl
,
VA
.
getValVT
(
)
,
Val
,
DAG
.
getIntPtrConstant
(
1
)
)
;
InFlag
=
Chain
.
getValue
(
2
)
;
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> const LC2200InstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


"MSA requires a 64-bit FPU register file (FR=1 mode). "

This constructor initializes the data members to match that of the specified triple .


<s>
bool
addRegAssignmentFast
(
)
override
{
llvm_unreachable
(
"should not be used"
)
;
}
</s>

Add core register alloator passes which do the actual register assignment and rewriting .


"mips16 and nomips16 specified on the same function"

Reset the subtarget for the Mips target .


<s> bool ok_for_simple_move_operands ( rtx * operands , machine_mode mode ) { if ( ! register_operand ( operands [ 0 ] , mode ) && ! reg_or_0_operand ( operands [ 1 ] , mode ) ) return false ; if ( visium_flags_exposed && gpc_reg_operand ( operands [ 0 ] , mode ) && gpc_reg_operand ( operands [ 1 ] , mode ) ) return false ; return true ; } </s>

Return true if the operands are valid for a simple move insn .


<s> static rtx frv_expand_int_void2arg ( enum insn_code icode , tree call ) { rtx pat ; rtx op0 = frv_read_argument ( call , 0 ) ; rtx op1 = frv_read_argument ( call , 1 ) ; op0 = frv_legitimize_argument ( icode , 1 , op0 ) ; op1 = frv_legitimize_argument ( icode , 1 , op1 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return NULL_RTX ; } </s>

Expand builtins that take two long operands and return void .


" is return block without RETURN instr\n"

Convenience function that returns true if the block ends in a return instruction .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s> Optional < DestSourcePair > RISCVInstrInfo :: isCopyInstrImpl ( const MachineInstr & MI ) const { if ( MI . isMoveReg ( ) ) return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 1 ) } ; switch ( MI . getOpcode ( ) ) { default : break ; case RISCV :: ADDI : if ( MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 1 ) } ; break ; case RISCV :: FSGNJ_D : case RISCV :: FSGNJ_S : if ( MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 2 ) . isReg ( ) && MI . getOperand ( 1 ) . getReg ( ) == MI . getOperand ( 2 ) . getReg ( ) ) return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 1 ) } ; break ; } return None ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


"LR & FP are always handled in emitPrologue"

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> bool TMS320C64XAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { const Function * F = MF . getFunction ( ) ; this -> MF = & MF ; Twine NewLine ( "\n" ) ; SetupMachineFunction ( MF ) ; EmitConstantPool ( ) ; OutStreamer . EmitRawText ( StringRef ( "\n\n" ) ) ; EmitAlignment ( F -> getAlignment ( ) , F ) ; EmitFunctionBodyStart ( ) ; EmitFunctionHeader ( ) ; MachineFunction :: const_iterator MBB ; for ( MBB = MF . begin ( ) ; MBB != MF . end ( ) ; ++ MBB ) { OutStreamer . EmitRawText ( NewLine ) ; printMBBInfo ( MBB ) ; if ( MBB != MF . begin ( ) ) { EmitBasicBlockStart ( MBB ) ; OutStreamer . EmitRawText ( NewLine ) ; } for ( MachineBasicBlock :: const_iterator MI = MBB -> begin ( ) , ME = MBB -> end ( ) ; MI != ME ; ++ MI ) { switch ( MI -> getDesc ( ) . getOpcode ( ) ) { case TMS320C64X :: prolog : emit_prolog ( MI ) ; break ; case TMS320C64X :: epilog : emit_epilog ( MI ) ; break ; default : MI = emit_instructions ( std :: make_pair ( MI , MBB -> end ( ) ) ) ; break ; } } } EmitJumpTableInfo ( ) ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> void TVMPassConfig :: addIRPasses ( ) { addPass ( createTVMLowerIntrinsicsPass ( ) ) ; addPass ( createLowerSwitchPass ( ) ) ; addPass ( createTVMLoopPrepare ( ) ) ; addPass ( createTVMControlFlowPrepare ( ) ) ; addPass ( createTVMDefineUndef ( ) ) ; addPass ( createTVMReFuncPass ( ) ) ; addPass ( createTVMStoreCombine ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


"considering end of repeat loop at insn %d\n"

Figure out where to put LABEL , which is the label for a repeat loop . If INCLUDING , LAST_INSN is the last instruction in the loop , otherwise the loop ends just before LAST_INSN . If SHARED , insns other than the `` repeat '' might use LABEL to jump to the loop 's continuation point . Return the last instruction in the adjusted loop .


<s> MCGNode * getNode ( const char * name ) const { for ( MCGNodes :: const_iterator i ( Nodes . begin ( ) ) , ie ( Nodes . end ( ) ) ; i != ie ; i ++ ) { if ( ! ( * i ) -> isUnknown ( ) && ( * i ) -> getMF ( ) -> getFunction ( ) . getName ( ) == name ) return * i ; } return NULL ; } </s>


<s> bool RISCVFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return true ; MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) DL = MI -> getDebugLoc ( ) ; const char * SpillLibCall = getSpillLibCallName ( * MF , CSI ) ; if ( SpillLibCall ) { BuildMI ( MBB , MI , DL , TII . get ( RISCV :: PseudoCALLReg ) , RISCV :: X5 ) . addExternalSymbol ( SpillLibCall , RISCVII :: MO_CALL ) . setMIFlag ( MachineInstr :: FrameSetup ) ; for ( auto & CS : CSI ) MBB . addLiveIn ( CS . getReg ( ) ) ; } const auto & NonLibcallCSI = getNonLibcallCSI ( CSI ) ; for ( auto & CS : NonLibcallCSI ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>


<s> bool AArch64InstrInfo :: isLdStPairSuppressed ( const MachineInstr & MI ) { return llvm :: any_of ( MI . memoperands ( ) , [ ] ( MachineMemOperand * MMO ) { return MMO -> getFlags ( ) & MOSuppressPair ; } ) ; } </s>

Return true if pairing the given load or store is hinted to be unprofitable .


<s> InstructionCost PPCTTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind , Instruction * Inst ) { if ( DisablePPCConstHoist ) return BaseT :: getIntImmCostInst ( Opcode , Idx , Imm , Ty , CostKind , Inst ) ; assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return ~ 0U ; unsigned ImmIdx = ~ 0U ; bool ShiftedFree = false , RunFree = false , UnsignedFree = false , ZeroFree = false ; switch ( Opcode ) { default : return TTI :: TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: And : RunFree = true ; LLVM_FALLTHROUGH ; case Instruction :: Add : case Instruction :: Or : case Instruction :: Xor : ShiftedFree = true ; LLVM_FALLTHROUGH ; case Instruction :: Sub : case Instruction :: Mul : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : ImmIdx = 1 ; break ; case Instruction :: ICmp : UnsignedFree = true ; ImmIdx = 1 ; LLVM_FALLTHROUGH ; case Instruction :: Select : ZeroFree = true ; break ; case Instruction :: PHI : case Instruction :: Call : case Instruction :: Ret : case Instruction :: Load : case Instruction :: Store : break ; } if ( ZeroFree && Imm == 0 ) return TTI :: TCC_Free ; if ( Idx == ImmIdx && Imm . getBitWidth ( ) <= 64 ) { if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; if ( RunFree ) { if ( Imm . getBitWidth ( ) <= 32 && ( isShiftedMask_32 ( Imm . getZExtValue ( ) ) || isShiftedMask_32 ( ~ Imm . getZExtValue ( ) ) ) ) return TTI :: TCC_Free ; if ( ST -> isPPC64 ( ) && ( isShiftedMask_64 ( Imm . getZExtValue ( ) ) || isShiftedMask_64 ( ~ Imm . getZExtValue ( ) ) ) ) return TTI :: TCC_Free ; } if ( UnsignedFree && isUInt < 16 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( ShiftedFree && ( Imm . getZExtValue ( ) & 0xFFFF ) == 0 ) return TTI :: TCC_Free ; } return PPCTTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> void Cpu0InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static bool isNodeHidden ( const MCGNode * N , const MCallSubGraph G ) { return false ; } </s>

Do not print nodes that are part of a pi-block separately .


<s> const MipsTargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


<s> MachineBasicBlock * HexagonHardwareLoops :: findLoopPreheader ( MachineLoop * L ) const { if ( MachineBasicBlock * PB = L -> getLoopPreheader ( ) ) return PB ; if ( ! SpecPreheader ) return nullptr ; MachineBasicBlock * HB = L -> getHeader ( ) , * LB = L -> getLoopLatch ( ) ; if ( HB -> pred_size ( ) != 2 || HB -> hasAddressTaken ( ) ) return nullptr ; MachineBasicBlock * Preheader = nullptr ; for ( MachineBasicBlock * P : HB -> predecessors ( ) ) { if ( P == LB ) continue ; if ( Preheader ) return nullptr ; Preheader = P ; } for ( MachineBasicBlock * S : Preheader -> successors ( ) ) { if ( S == HB ) continue ; MachineLoop * T = MLI -> getLoopFor ( S ) ; if ( T && T -> getHeader ( ) == S ) return nullptr ; } return Preheader ; } </s>

Find the block that either is the loop preheader , or could speculatively be used as the preheader .


<s>
void
Finish
(
)
{
const
size_t
VendorHeaderSize
=
4
+
CurrentVendor
.
size
(
)
+
1
;
const
size_t
TagHeaderSize
=
1
+
4
;
Streamer
.
EmitIntValue
(
VendorHeaderSize
+
TagHeaderSize
+
ContentsSize
,
4
)
;
Streamer
.
EmitBytes
(
CurrentVendor
)
;
Streamer
.
EmitIntValue
(
0
,
1
)
;
Streamer
.
EmitIntValue
(
ARMBuildAttrs
::
File
,
1
)
;
Streamer
.
EmitIntValue
(
TagHeaderSize
+
ContentsSize
,
4
)
;
for
(
unsigned
int
i
=
0
;
i
<
Contents
.
size
(
)
;
++
i
)
{
AttributeItemType
item
=
Contents
[
i
]
;
Streamer
.
EmitULEB128IntValue
(
item
.
Tag
)
;
switch
(
item
.
Type
)
{
default
:
llvm_unreachable
(
"Invalid attribute type"
)
;
case
AttributeItemType
::
NumericAttribute
:
Streamer
.
EmitULEB128IntValue
(
item
.
IntValue
)
;
break
;
case
AttributeItemType
::
TextAttribute
:
Streamer
.
EmitBytes
(
item
.
StringValue
.
upper
(
)
)
;
Streamer
.
EmitIntValue
(
0
,
1
)
;
break
;
}
}
Contents
.
clear
(
)
;
}
</s>

Finish - Do final processing and write the object to the output stream .


<s>
SDValue
Z80TargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_Z80
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
i
++
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
Z80ISD
::
RET
,
dl
,
MVT
::
Other
,
&
RetOps
[
0
]
,
RetOps
.
size
(
)
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> const Cpu0RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
bool
AArch64InstrInfo
::
reverseBranchCondition
(
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
if
(
Cond
[
0
]
.
getImm
(
)
!=
1
)
{
AArch64CC
::
CondCode
CC
=
(
AArch64CC
::
CondCode
)
(
int
)
Cond
[
0
]
.
getImm
(
)
;
Cond
[
0
]
.
setImm
(
AArch64CC
::
getInvertedCondCode
(
CC
)
)
;
}
else
{
switch
(
Cond
[
1
]
.
getImm
(
)
)
{
default
:
llvm_unreachable
(
"Unknown conditional branch!"
)
;
case
AArch64
::
CBZW
:
Cond
[
1
]
.
setImm
(
AArch64
::
CBNZW
)
;
break
;
case
AArch64
::
CBNZW
:
Cond
[
1
]
.
setImm
(
AArch64
::
CBZW
)
;
break
;
case
AArch64
::
CBZX
:
Cond
[
1
]
.
setImm
(
AArch64
::
CBNZX
)
;
break
;
case
AArch64
::
CBNZX
:
Cond
[
1
]
.
setImm
(
AArch64
::
CBZX
)
;
break
;
case
AArch64
::
TBZW
:
Cond
[
1
]
.
setImm
(
AArch64
::
TBNZW
)
;
break
;
case
AArch64
::
TBNZW
:
Cond
[
1
]
.
setImm
(
AArch64
::
TBZW
)
;
break
;
case
AArch64
::
TBZX
:
Cond
[
1
]
.
setImm
(
AArch64
::
TBNZX
)
;
break
;
case
AArch64
::
TBNZX
:
Cond
[
1
]
.
setImm
(
AArch64
::
TBZX
)
;
break
;
}
}
return
false
;
}
</s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s>
void
dump
(
const
GCNRegBankReassign
*
P
)
const
{
dbgs
(
)
<<
"\nCandidates:\n\n"
;
for
(
auto
&
B
:
*
this
)
{
dbgs
(
)
<<
" Weight "
<<
B
.
first
<<
":\n"
;
for
(
auto
&
C
:
B
.
second
)
C
.
dump
(
P
)
;
}
dbgs
(
)
<<
"\n\n"
;
}
</s>

Dump the plan to stderr ( for debugging ) .

AMDGPU
"\nCandidates:\n\n"
" Weight "
":\n"
"\n\n"


<s> virtual const TOYRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>


<s> rtx function_expander :: map_to_unspecs ( int unspec_for_sint , int unspec_for_uint , int unspec_for_fp , unsigned int merge_argno ) { machine_mode mode = vector_mode ( 0 ) ; int unspec = ( ! type_suffix ( 0 ) . integer_p ? unspec_for_fp : type_suffix ( 0 ) . unsigned_p ? unspec_for_uint : unspec_for_sint ) ; if ( pred == PRED_x ) { insn_code icode = maybe_code_for_aarch64_pred ( unspec , mode ) ; if ( icode != CODE_FOR_nothing ) return use_pred_x_insn ( icode ) ; } if ( pred == PRED_none || pred == PRED_x ) { insn_code icode = maybe_code_for_aarch64_sve ( unspec , mode ) ; if ( icode != CODE_FOR_nothing ) return use_unpred_insn ( icode ) ; } insn_code icode = code_for_cond ( unspec , vector_mode ( 0 ) ) ; return use_cond_insn ( icode , merge_argno ) ; } </s>

Implement the call using one of the following strategies , chosen in order : ( 1 ) `` aarch64_pred_ < optab > < mode > '' for PRED_x functions ; this is a predicated pattern ( 2 ) `` aarch64_sve_ < optab > < mode > '' for PRED_none and PRED_x functions ; this is an unpredicated pattern ( 3 ) `` cond_ < optab > < mode > '' otherwise where < optab > corresponds to : - UNSPEC_FOR_SINT for signed integers - UNSPEC_FOR_UINT for unsigned integers - UNSPEC_FOR_FP for floating-point values MERGE_ARGNO is the argument that provides the values of inactive lanes for _m functions , or DEFAULT_MERGE_ARGNO if we should apply the usual rules .


"Unexpected register class in CSRsViaCopy!"

"Function should be nounwind in insertCopiesSplitCSR!"

Insert explicit copies in entry and exit blocks .


<s> const TargetRegisterClass * SystemZTargetLowering :: getRepRegClassFor ( MVT VT ) const { if ( VT == MVT :: Untyped ) return & SystemZ :: ADDR128BitRegClass ; return TargetLowering :: getRepRegClassFor ( VT ) ; } </s>

Return the 'representative ' register class for the specified value type .

SystemZ SystemZ MVT::Untyped SystemZ::ADDR128BitRegClass


<s> virtual const Cpu0InstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> bool SNESAsmParser :: ParseDirective ( llvm :: AsmToken DirectiveID ) { return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


"NIOS2 DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> void HexagonPassConfig :: addPostRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableRDFOpt ) addPass ( createHexagonRDFOpt ( ) ) ; if ( ! DisableHexagonCFGOpt ) addPass ( createHexagonCFGOptimizer ( ) , false ) ; } } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> int nios2_emit_move_sequence ( rtx * operands , machine_mode mode ) { rtx to = operands [ 0 ] ; rtx from = operands [ 1 ] ; if ( ! register_operand ( to , mode ) && ! reg_or_0_operand ( from , mode ) ) { gcc_assert ( can_create_pseudo_p ( ) ) ; from = copy_to_mode_reg ( mode , from ) ; } if ( GET_CODE ( from ) == SYMBOL_REF || GET_CODE ( from ) == LABEL_REF || ( GET_CODE ( from ) == CONST && GET_CODE ( XEXP ( from , 0 ) ) != UNSPEC ) ) from = nios2_legitimize_constant_address ( from ) ; operands [ 0 ] = to ; operands [ 1 ] = from ; return 0 ; } </s>


<s> static const struct mips_cpu_info * mips_cpu_info_from_opt ( int opt ) { switch ( opt ) { case MIPS_ARCH_OPTION_FROM_ABI : return mips_cpu_info_from_isa ( ABI_NEEDS_32BIT_REGS ? 1 : ABI_NEEDS_64BIT_REGS ? 3 : ( TARGET_64BIT ? 3 : 1 ) ) ; case MIPS_ARCH_OPTION_NATIVE : gcc_unreachable ( ) ; default : return & mips_cpu_info_table [ opt ] ; } } </s>

Return a mips_cpu_info entry determined by an option valued OPT .


<s>
StringRef
getPassName
(
)
const
override
{
return
"AArch64 Stack Tagging PreRA"
;
}
</s>


<s>
void
HexagonRegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOp
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected"
)
;
MachineInstr
&
MI
=
*
II
;
MachineBasicBlock
&
MB
=
*
MI
.
getParent
(
)
;
MachineFunction
&
MF
=
*
MB
.
getParent
(
)
;
auto
&
HST
=
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
;
auto
&
HII
=
*
HST
.
getInstrInfo
(
)
;
auto
&
HFI
=
*
HST
.
getFrameLowering
(
)
;
unsigned
BP
=
0
;
int
FI
=
MI
.
getOperand
(
FIOp
)
.
getIndex
(
)
;
int
Offset
=
HFI
.
getFrameIndexReference
(
MF
,
FI
,
BP
)
;
int
RealOffset
=
Offset
+
MI
.
getOperand
(
FIOp
+
1
)
.
getImm
(
)
;
unsigned
Opc
=
MI
.
getOpcode
(
)
;
switch
(
Opc
)
{
case
Hexagon
::
TFR_FIA
:
MI
.
setDesc
(
HII
.
get
(
Hexagon
::
A2_addi
)
)
;
MI
.
getOperand
(
FIOp
)
.
ChangeToImmediate
(
RealOffset
)
;
MI
.
RemoveOperand
(
FIOp
+
1
)
;
return
;
case
Hexagon
::
TFR_FI
:
MI
.
setDesc
(
HII
.
get
(
Hexagon
::
A2_addi
)
)
;
break
;
}
if
(
HII
.
isValidOffset
(
Opc
,
RealOffset
)
)
{
MI
.
getOperand
(
FIOp
)
.
ChangeToRegister
(
BP
,
false
)
;
MI
.
getOperand
(
FIOp
+
1
)
.
ChangeToImmediate
(
RealOffset
)
;
return
;
}
const
Function
*
F
=
MF
.
getFunction
(
)
;
dbgs
(
)
<<
"In function "
;
if
(
F
)
dbgs
(
)
<<
F
->
getName
(
)
;
else
dbgs
(
)
<<
"<?>"
;
dbgs
(
)
<<
", BB#"
<<
MB
.
getNumber
(
)
<<
"\n"
<<
MI
;
llvm_unreachable
(
"Unhandled instruction"
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


"the layout of aggregates containing vectors with"

" %d-byte alignment has changed in GCC 5"

Previous GCC releases forced all vector types to have 16-byte alignment .


<s> const unsigned * XCoreRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const unsigned CalleeSavedRegs [ ] = { XCore :: R4 , XCore :: R5 , XCore :: R6 , XCore :: R7 , XCore :: R8 , XCore :: R9 , XCore :: R10 , XCore :: LR , 0 } ; return CalleeSavedRegs ; } </s>


"missing or badly formed return type.\n"

"return type: isvoid = %d, isconst = %d, isvector = %d, "

"issigned = %d, isunsigned = %d, isbool = %d, ispixel = %d, "

"ispointer = %d, base = %d, restr = %d, val1 = \"%s\", "

Parse a function prototype . This code is shared by the bif and overload file processing .


<s> MipsTargetLowering :: ConstraintType MipsTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'd' : case 'y' : case 'f' : return C_RegisterClass ; break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> bool WebAssemblyTargetLowering :: isIntDivCheap ( EVT VT , AttributeList Attr ) const { return true ; } </s>

Return true if integer divide is usually cheaper than a sequence of several shifts , adds , and multiplies for this target .


<s> bool PTXPassConfig :: addPreEmitPass ( ) { PM . add ( createPTXMFInfoExtract ( getPTXTargetMachine ( ) , getOptLevel ( ) ) ) ; PM . add ( createPTXFPRoundingModePass ( getPTXTargetMachine ( ) , getOptLevel ( ) ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> int arc_label_align ( rtx label ) { int loop_align = LOOP_ALIGN ( LABEL ) ; if ( loop_align > align_labels_log ) { rtx_insn * prev = prev_nonnote_insn ( label ) ; if ( prev && NONJUMP_INSN_P ( prev ) && GET_CODE ( PATTERN ( prev ) ) == PARALLEL && recog_memoized ( prev ) == CODE_FOR_doloop_begin_i ) return loop_align ; } if ( align_labels_log < 1 ) { rtx_insn * next = next_nonnote_nondebug_insn ( label ) ; if ( INSN_P ( next ) && recog_memoized ( next ) >= 0 ) return 1 ; } return align_labels_log ; } </s>

Oddly enough , sometimes we get a zero overhead loop that branch shortening does n't think is a loop - observed with compile/pr24883.c -O3 -fomit-frame-pointer -funroll-loops . Make sure to include the alignment visible for branch shortening ( we actually align the loop insn before it , but that is equivalent since the loop insn is 4 byte long . )


<s> const Cpu0MCExpr * Cpu0MCExpr :: create ( const MCSymbol * Symbol , Cpu0MCExpr :: Cpu0ExprKind Kind , MCContext & Ctx ) { const MCSymbolRefExpr * MCSym = MCSymbolRefExpr :: create ( Symbol , MCSymbolRefExpr :: VK_None , Ctx ) ; return new ( Ctx ) Cpu0MCExpr ( Kind , MCSym ) ; } </s>


<s> const SparcSubtarget * SparcTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool softFloat = F . hasFnAttribute ( "use-soft-float" ) && F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( softFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < SparcSubtarget > ( TargetTriple , CPU , FS , * this , this -> is64Bit ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

Sparc Sparc Sparc "target-cpu" "target-features" "use-soft-float" "use-soft-float" "true" "+soft-float" ",+soft-float" Sparc


"invalid number in %<-mrgf-banked-regs=%s%> "

Parse -mrgf-banked-regs=NUM option string . Valid values for NUM are 4 , 8 , 16 , or 32 .


<s> const MCExpr * getSubExpr ( ) const { return Expr ; } </s>

getSubExpr - Get the child of this expression .


<s> static int frv_acc_group_1 ( rtx * x , void * data ATTRIBUTE_UNUSED ) { if ( REG_P ( * x ) ) { if ( ACC_P ( REGNO ( * x ) ) ) return ( REGNO ( * x ) - ACC_FIRST ) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN ; if ( ACCG_P ( REGNO ( * x ) ) ) return ( REGNO ( * x ) - ACCG_FIRST ) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN ; } return 0 ; } </s>

A for_each_rtx callback . If X refers to an accumulator , return ACC_GROUP_ODD if the bit 2 of the register number is set and ACC_GROUP_EVEN if it is clear . Return 0 ( ACC_GROUP_NONE ) otherwise .


<s> virtual bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> static rtx ia64_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( mode , ( ( ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) && ( mode ) != TFmode ) ? FR_RET_FIRST : GR_RET_FIRST ) ) ; } </s>

Worker function for TARGET_LIBCALL_VALUE .


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> void SHUXIInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; BuildMI ( MBB , MI , DL , get ( SHUXI :: PUSH ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool CSKYAsmBackend :: mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const { switch ( Inst . getOpcode ( ) ) { default : return false ; case CSKY :: JBR32 : case CSKY :: JBT32 : case CSKY :: JBF32 : case CSKY :: JBSR32 : if ( ! STI . getFeatureBits ( ) [ CSKY :: Has2E3 ] ) return false ; return true ; case CSKY :: JBR16 : case CSKY :: JBT16 : case CSKY :: JBF16 : case CSKY :: LRW16 : case CSKY :: BR16 : return true ; } } </s>

Check whether the given instruction may need relaxation .


<s> static ARMOperand CreateMem ( unsigned BaseRegNum , bool OffsetIsReg , const MCExpr * Offset , unsigned OffsetRegNum , bool OffsetRegShifted , enum ShiftType ShiftType , const MCExpr * ShiftAmount , bool Preindexed , bool Postindexed , bool Negative , bool Writeback ) { ARMOperand Res ; Res . Kind = Memory ; Res . Mem . BaseRegNum = BaseRegNum ; Res . Mem . OffsetIsReg = OffsetIsReg ; Res . Mem . Offset = Offset ; Res . Mem . OffsetRegNum = OffsetRegNum ; Res . Mem . OffsetRegShifted = OffsetRegShifted ; Res . Mem . ShiftType = ShiftType ; Res . Mem . ShiftAmount = ShiftAmount ; Res . Mem . Preindexed = Preindexed ; Res . Mem . Postindexed = Postindexed ; Res . Mem . Negative = Negative ; Res . Mem . Writeback = Writeback ; return Res ; } </s>


<s> bool HexagonRemoveExtendArgs :: runOnFunction ( Function & F ) { unsigned Idx = 1 ; for ( Function :: arg_iterator AI = F . arg_begin ( ) , AE = F . arg_end ( ) ; AI != AE ; ++ AI , ++ Idx ) { if ( F . getParamAttributes ( Idx ) . hasAttribute ( Attributes :: SExt ) ) { Argument * Arg = AI ; if ( ! isa < PointerType > ( Arg -> getType ( ) ) ) { for ( Instruction :: use_iterator UI = Arg -> use_begin ( ) ; UI != Arg -> use_end ( ) ; ) { if ( isa < SExtInst > ( * UI ) ) { Instruction * Use = cast < Instruction > ( * UI ) ; SExtInst * SI = new SExtInst ( Arg , Use -> getType ( ) ) ; assert ( EVT :: getEVT ( SI -> getType ( ) ) == ( EVT :: getEVT ( Use -> getType ( ) ) ) ) ; ++ UI ; Use -> replaceAllUsesWith ( SI ) ; Instruction * First = F . getEntryBlock ( ) . begin ( ) ; SI -> insertBefore ( First ) ; Use -> eraseFromParent ( ) ; } else { ++ UI ; } } } } } return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s>
const
char
*
arm_output_shift
(
rtx
*
operands
,
int
set_flags
)
{
char
pattern
[
100
]
;
static
const
char
flag_chars
[
3
]
=
{
'?'
,
'.'
,
'!'
}
;
const
char
*
shift
;
HOST_WIDE_INT
val
;
char
c
;
c
=
flag_chars
[
set_flags
]
;
if
(
TARGET_UNIFIED_ASM
)
{
shift
=
shift_op
(
operands
[
3
]
,
&
val
)
;
if
(
shift
)
{
if
(
val
!=
1
)
operands
[
2
]
=
GEN_INT
(
val
)
;
sprintf
(
pattern
,
"%s%%%c\t%%0, %%1, %%2"
,
shift
,
c
)
;
}
else
sprintf
(
pattern
,
"mov%%%c\t%%0, %%1"
,
c
)
;
}
else
sprintf
(
pattern
,
"mov%%%c\t%%0, %%1%%S3"
,
c
)
;
output_asm_insn
(
pattern
,
operands
)
;
return
""
;
}
</s>

Output assembly for a shift instruction . SET_FLAGS determines how the instruction modifies the condition codes . 0 - Do not set condition codes . 1 - Set condition codes . 2 - Use smallest instruction .


"Tail call for extern symbol not yet supported."

Targets should implement this to emit instructions .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


"rs6000_get_function_version_priority (%s) => %d\n"

Return the clone id of the target we are compiling code for in a target clone . The clone id is ordered from 0 ( default ) to CLONE_MAX-1 and gives the priority list for the target clones ( ordered from lowest to highest ) .


<s> OperandMatchResultTy VEAsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { const AsmToken Tok = Parser . getTok ( ) ; StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; RegNo = 0 ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Percent ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; RegNo = parseRegisterName ( & MatchRegisterName ) ; if ( RegNo == VE :: NoRegister ) RegNo = parseRegisterName ( & MatchRegisterAltName ) ; if ( RegNo != VE :: NoRegister ) { Parser . Lex ( ) ; return MatchOperand_Success ; } getLexer ( ) . UnLex ( Tok ) ; return MatchOperand_NoMatch ; } </s>

tryParseRegister - parse one register if possible


"Caller should have handled 0-size case"

Emit target-specific code that performs a memcmp/bcmp , in cases where that is faster than a libcall .


<s> bool ARMTTIImpl :: isLoweredToCall ( const Function * F ) { if ( ! F -> isIntrinsic ( ) ) BaseT :: isLoweredToCall ( F ) ; if ( F -> getName ( ) . startswith ( "llvm.arm" ) ) return false ; switch ( F -> getIntrinsicID ( ) ) { default : break ; case Intrinsic :: powi : case Intrinsic :: sin : case Intrinsic :: cos : case Intrinsic :: pow : case Intrinsic :: log : case Intrinsic :: log10 : case Intrinsic :: log2 : case Intrinsic :: exp : case Intrinsic :: exp2 : return true ; case Intrinsic :: sqrt : case Intrinsic :: fabs : case Intrinsic :: copysign : case Intrinsic :: floor : case Intrinsic :: ceil : case Intrinsic :: trunc : case Intrinsic :: rint : case Intrinsic :: nearbyint : case Intrinsic :: round : case Intrinsic :: canonicalize : case Intrinsic :: lround : case Intrinsic :: llround : case Intrinsic :: lrint : case Intrinsic :: llrint : if ( F -> getReturnType ( ) -> isDoubleTy ( ) && ! ST -> hasFP64 ( ) ) return true ; if ( F -> getReturnType ( ) -> isHalfTy ( ) && ! ST -> hasFullFP16 ( ) ) return true ; return ! ST -> hasFPARMv8Base ( ) && ! ST -> hasVFP2Base ( ) ; case Intrinsic :: masked_store : case Intrinsic :: masked_load : case Intrinsic :: masked_gather : case Intrinsic :: masked_scatter : return ! ST -> hasMVEIntegerOps ( ) ; case Intrinsic :: sadd_with_overflow : case Intrinsic :: uadd_with_overflow : case Intrinsic :: ssub_with_overflow : case Intrinsic :: usub_with_overflow : case Intrinsic :: sadd_sat : case Intrinsic :: uadd_sat : case Intrinsic :: ssub_sat : case Intrinsic :: usub_sat : return false ; } return BaseT :: isLoweredToCall ( F ) ; } </s>

Test whether calls to a function lower to actual program function calls .


<s> static bool v850_legitimate_address_p ( machine_mode mode , rtx x , bool strict_p , addr_space_t as ATTRIBUTE_UNUSED ) { gcc_assert ( ADDR_SPACE_GENERIC_P ( as ) ) ; if ( v850_rtx_ok_for_base_p ( x , strict_p ) ) return true ; if ( CONSTANT_ADDRESS_P ( x ) && ( mode == QImode || INTVAL ( x ) % 2 == 0 ) && ( GET_MODE_SIZE ( mode ) <= 4 || INTVAL ( x ) % 4 == 0 ) ) return true ; if ( GET_CODE ( x ) == LO_SUM && REG_P ( XEXP ( x , 0 ) ) && v850_reg_ok_for_base_p ( XEXP ( x , 0 ) , strict_p ) && CONSTANT_P ( XEXP ( x , 1 ) ) && ( ! CONST_INT_P ( XEXP ( x , 1 ) ) || ( ( mode == QImode || INTVAL ( XEXP ( x , 1 ) ) % 2 == 0 ) && constraint_satisfied_p ( XEXP ( x , 1 ) , CONSTRAINT_K ) ) ) && GET_MODE_SIZE ( mode ) <= GET_MODE_SIZE ( word_mode ) ) return true ; if ( special_symbolref_operand ( x , mode ) && ( GET_MODE_SIZE ( mode ) <= GET_MODE_SIZE ( word_mode ) ) ) return true ; if ( GET_CODE ( x ) == PLUS && v850_rtx_ok_for_base_p ( XEXP ( x , 0 ) , strict_p ) && ( constraint_satisfied_p ( XEXP ( x , 1 ) , CONSTRAINT_K ) || ( TARGET_V850E2V3_UP && ( mode == SImode || mode == HImode || mode == QImode ) && constraint_satisfied_p ( XEXP ( x , 1 ) , CONSTRAINT_W ) ) ) && ( ( mode == QImode || INTVAL ( XEXP ( x , 1 ) ) % 2 == 0 ) && CONST_OK_FOR_K ( INTVAL ( XEXP ( x , 1 ) ) + ( GET_MODE_NUNITS ( mode ) * UNITS_PER_WORD ) ) ) ) return true ; return false ; } </s>


<s> enum aarch64_symbol_type aarch64_classify_tls_symbol ( rtx x ) { enum tls_model tls_kind = tls_symbolic_operand_type ( x ) ; switch ( tls_kind ) { case TLS_MODEL_GLOBAL_DYNAMIC : case TLS_MODEL_LOCAL_DYNAMIC : return TARGET_TLS_DESC ? SYMBOL_SMALL_TLSDESC : SYMBOL_SMALL_TLSGD ; case TLS_MODEL_INITIAL_EXEC : return SYMBOL_SMALL_GOTTPREL ; case TLS_MODEL_LOCAL_EXEC : return SYMBOL_SMALL_TPREL ; case TLS_MODEL_EMULATED : case TLS_MODEL_NONE : return SYMBOL_FORCE_TO_MEM ; default : gcc_unreachable ( ) ; } } </s>

Classify a TLS symbol into one of the TLS kinds .


<s> bool ARMTargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return Size <= ( Subtarget -> isMClass ( ) ? 32U : 64U ) ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


"  Adding insn %d into chain's #%d queue\n"


<s> virtual const Z80RegisterInfo * getRegisterInfo ( ) const { return & getInstrInfo ( ) -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


"%<-max-stackframe=%d%> is not usable, "

"unknown CRIS version specification in %<-march=%> or "

"unknown CRIS cpu version specification in %<-mtune=%> : %s"

"%<-fPIC%> and %<-fpic%> are not supported on this target"

The TARGET_OPTION_OVERRIDE worker . As is the norm , this also parses -mfoo=bar type parameters .


<s>
bool
AArch64FrameLowering
::
spillCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
;
SmallVector
<
RegPairInfo
,
8
>
RegPairs
;
bool
NeedShadowCallStackProlog
=
false
;
computeCalleeSaveRegisterPairs
(
MF
,
CSI
,
TRI
,
RegPairs
,
NeedShadowCallStackProlog
)
;
const
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
if
(
NeedShadowCallStackProlog
)
{
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AArch64
::
STRXpost
)
)
.
addReg
(
AArch64
::
X18
,
RegState
::
Define
)
.
addReg
(
AArch64
::
LR
)
.
addReg
(
AArch64
::
X18
)
.
addImm
(
8
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
MBB
.
addLiveIn
(
AArch64
::
X18
)
;
}
for
(
auto
RPII
=
RegPairs
.
rbegin
(
)
,
RPIE
=
RegPairs
.
rend
(
)
;
RPII
!=
RPIE
;
++
RPII
)
{
RegPairInfo
RPI
=
*
RPII
;
unsigned
Reg1
=
RPI
.
Reg1
;
unsigned
Reg2
=
RPI
.
Reg2
;
unsigned
StrOpc
;
if
(
RPI
.
IsGPR
)
StrOpc
=
RPI
.
isPaired
(
)
AArch64
::
STPXi
:
AArch64
::
STRXui
;
else
StrOpc
=
RPI
.
isPaired
(
)
AArch64
::
STPDi
:
AArch64
::
STRDui
;
DEBUG
(
dbgs
(
)
<<
"CSR spill: ("
<<
printReg
(
Reg1
,
TRI
)
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
printReg
(
Reg2
,
TRI
)
;
dbgs
(
)
<<
") -> fi#("
<<
RPI
.
FrameIdx
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
RPI
.
FrameIdx
+
1
;
dbgs
(
)
<<
")\n"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
StrOpc
)
)
;
if
(
!
MRI
.
isReserved
(
Reg1
)
)
MBB
.
addLiveIn
(
Reg1
)
;
if
(
RPI
.
isPaired
(
)
)
{
if
(
!
MRI
.
isReserved
(
Reg2
)
)
MBB
.
addLiveIn
(
Reg2
)
;
MIB
.
addReg
(
Reg2
,
getPrologueDeath
(
MF
,
Reg2
)
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
+
1
)
,
MachineMemOperand
::
MOStore
,
8
,
8
)
)
;
}
MIB
.
addReg
(
Reg1
,
getPrologueDeath
(
MF
,
Reg1
)
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
RPI
.
Offset
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
)
,
MachineMemOperand
::
MOStore
,
8
,
8
)
)
;
}
return
true
;
}
</s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static void register_vector_type ( vector_type_index type ) { tree vectype = abi_vector_types [ type ] ; tree id = get_identifier ( vector_types [ type ] . acle_name ) ; tree decl = build_decl ( input_location , TYPE_DECL , id , vectype ) ; decl = lang_hooks . decls . pushdecl ( decl ) ; if ( decl && TREE_CODE ( decl ) == TYPE_DECL && TREE_TYPE ( decl ) != error_mark_node && TYPE_MAIN_VARIANT ( TREE_TYPE ( decl ) ) == vectype ) vectype = TREE_TYPE ( decl ) ; acle_vector_types [ 0 ] [ type ] = vectype ; } </s>

Register vector type TYPE under its risv_vector.h name .


<s> static bool isBranch ( unsigned Opcode ) { return Opcode == R600 :: BRANCH || Opcode == R600 :: BRANCH_COND_i32 || Opcode == R600 :: BRANCH_COND_f32 ; } </s>

Returns true if this is a conditional , unconditional , or indirect branch .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
TriCore
::
NumTargetFixupKinds
]
=
{
{
"fixup_leg_mov_hi16_pcrel"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_leg_mov_lo16_pcrel"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_call"
,
0
,
24
,
0
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
{
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
}
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> void PPCInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { unsigned Directive = Subtarget . getCPUDirective ( ) ; unsigned Opcode ; switch ( Directive ) { default : Opcode = PPC :: NOP ; break ; case PPC :: DIR_PWR6 : Opcode = PPC :: NOP_GT_PWR6 ; break ; case PPC :: DIR_PWR7 : Opcode = PPC :: NOP_GT_PWR7 ; break ; case PPC :: DIR_PWR8 : Opcode = PPC :: NOP_GT_PWR7 ; break ; case PPC :: DIR_PWR9 : Opcode = PPC :: NOP_GT_PWR7 ; break ; } DebugLoc DL ; BuildMI ( MBB , MI , DL , get ( Opcode ) ) ; } </s>

Insert a noop into the instruction stream at the specified point .


<s>
DecodeStatus
AArch64Disassembler
::
getInstruction
(
MCInst
&
MI
,
uint64_t
&
Size
,
ArrayRef
<
uint8_t
>
Bytes
,
uint64_t
Address
,
raw_ostream
&
CS
)
const
{
CommentStream
=
&
CS
;
Size
=
0
;
if
(
Bytes
.
size
(
)
<
4
)
return
Fail
;
Size
=
4
;
uint32_t
Insn
=
(
Bytes
[
3
]
<<
24
)
|
(
Bytes
[
2
]
<<
16
)
|
(
Bytes
[
1
]
<<
8
)
|
(
Bytes
[
0
]
<<
0
)
;
const
uint8_t
*
Tables
[
]
=
{
DecoderTable32
,
DecoderTableFallback32
}
;
for
(
auto
Table
:
Tables
)
{
DecodeStatus
Result
=
decodeInstruction
(
Table
,
MI
,
Insn
,
Address
,
this
,
STI
)
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
AArch64
::
LDR_ZA
:
case
AArch64
::
STR_ZA
:
{
MI
.
insert
(
MI
.
begin
(
)
,
MCOperand
::
createReg
(
AArch64
::
ZA
)
)
;
const
MCOperand
&
Imm4Op
=
MI
.
getOperand
(
2
)
;
assert
(
Imm4Op
.
isImm
(
)
&&
"Unexpected operand type!"
)
;
MI
.
addOperand
(
Imm4Op
)
;
break
;
}
case
AArch64
::
LD1_MXIPXX_H_B
:
case
AArch64
::
LD1_MXIPXX_V_B
:
case
AArch64
::
ST1_MXIPXX_H_B
:
case
AArch64
::
ST1_MXIPXX_V_B
:
case
AArch64
::
INSERT_MXIPZ_H_B
:
case
AArch64
::
INSERT_MXIPZ_V_B
:
MI
.
insert
(
MI
.
begin
(
)
,
MCOperand
::
createReg
(
AArch64
::
ZAB0
)
)
;
break
;
case
AArch64
::
EXTRACT_ZPMXI_H_B
:
case
AArch64
::
EXTRACT_ZPMXI_V_B
:
MI
.
insert
(
MI
.
begin
(
)
+
2
,
MCOperand
::
createReg
(
AArch64
::
ZAB0
)
)
;
break
;
case
AArch64
::
LD1_MXIPXX_H_Q
:
case
AArch64
::
LD1_MXIPXX_V_Q
:
case
AArch64
::
ST1_MXIPXX_H_Q
:
case
AArch64
::
ST1_MXIPXX_V_Q
:
MI
.
insert
(
MI
.
begin
(
)
+
2
,
MCOperand
::
createImm
(
0
)
)
;
break
;
case
AArch64
::
INSERT_MXIPZ_H_Q
:
case
AArch64
::
INSERT_MXIPZ_V_Q
:
MI
.
insert
(
MI
.
begin
(
)
+
2
,
MCOperand
::
createImm
(
0
)
)
;
break
;
case
AArch64
::
EXTRACT_ZPMXI_H_Q
:
case
AArch64
::
EXTRACT_ZPMXI_V_Q
:
MI
.
addOperand
(
MCOperand
::
createImm
(
0
)
)
;
break
;
case
AArch64
::
SMOVvi8to32_idx0
:
case
AArch64
::
SMOVvi8to64_idx0
:
case
AArch64
::
SMOVvi16to32_idx0
:
case
AArch64
::
SMOVvi16to64_idx0
:
case
AArch64
::
SMOVvi32to64_idx0
:
case
AArch64
::
UMOVvi8_idx0
:
case
AArch64
::
UMOVvi16_idx0
:
case
AArch64
::
UMOVvi32_idx0
:
case
AArch64
::
UMOVvi64_idx0
:
MI
.
addOperand
(
MCOperand
::
createImm
(
0
)
)
;
break
;
}
if
(
Result
!=
MCDisassembler
::
Fail
)
return
Result
;
}
return
MCDisassembler
::
Fail
;
}
</s>

Returns the disassembly of a single instruction .


"Can only insert epilogue into returning blocks"

"Expected to see callee-save register restore code"


<s> AArch64Subtarget & AArch64Subtarget :: initializeSubtargetDependencies ( StringRef FS , StringRef CPUString ) { if ( CPUString . empty ( ) ) CPUString = "generic" ; ParseSubtargetFeatures ( CPUString , FS ) ; initializeProperties ( ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> static void iq2000_select_section ( tree decl , int reloc ATTRIBUTE_UNUSED , unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED ) { if ( TARGET_EMBEDDED_DATA ) { if ( ( TREE_CODE ( decl ) == VAR_DECL && TREE_READONLY ( decl ) && ! TREE_SIDE_EFFECTS ( decl ) && DECL_INITIAL ( decl ) && ( DECL_INITIAL ( decl ) == error_mark_node || TREE_CONSTANT ( DECL_INITIAL ( decl ) ) ) ) || TREE_CODE ( decl ) != VAR_DECL ) readonly_data_section ( ) ; else data_section ( ) ; } else { if ( ( TREE_CODE ( decl ) == VAR_DECL && TREE_READONLY ( decl ) && ! TREE_SIDE_EFFECTS ( decl ) && DECL_INITIAL ( decl ) && ( DECL_INITIAL ( decl ) == error_mark_node || TREE_CONSTANT ( DECL_INITIAL ( decl ) ) ) ) || TREE_CODE ( decl ) != VAR_DECL ) readonly_data_section ( ) ; else data_section ( ) ; } } </s>

Choose the section to use for DECL . RELOC is true if its value contains any relocatable expression . Some of the logic used here needs to be replicated in ENCODE_SECTION_INFO in iq2000.h so that references to these symbols are done correctly .


<s> void FISCPassConfig :: addPreEmitPass ( ) { addPass ( createFISCDelaySlotFillerPass ( getFISCTargetMachine ( ) ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool X86TargetLowering :: isUsedByReturnOnly ( SDNode * N ) const { if ( N -> getNumValues ( ) != 1 ) return false ; if ( ! N -> hasNUsesOfValue ( 1 , 0 ) ) return false ; SDNode * Copy = * N -> use_begin ( ) ; if ( Copy -> getOpcode ( ) == ISD :: CopyToReg ) { if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - 1 ) . getValueType ( ) == MVT :: Glue ) return false ; } else if ( Copy -> getOpcode ( ) != ISD :: FP_EXTEND ) return false ; bool HasRet = false ; for ( SDNode :: use_iterator UI = Copy -> use_begin ( ) , UE = Copy -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != X86ISD :: RET_FLAG ) return false ; HasRet = true ; } return HasRet ; } </s>

Return true if result of the specified node is used by a return node only .


<s> unsigned getNumFixupKinds ( ) const override { return SNES :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> static void alpha_emit_xfloating_libcall ( rtx func , rtx target , rtx operands [ ] , int noperands , rtx equiv ) { rtx usage = NULL_RTX , reg ; int regno = 16 , i ; start_sequence ( ) ; for ( i = 0 ; i < noperands ; ++ i ) { switch ( GET_MODE ( operands [ i ] ) ) { case TFmode : reg = gen_rtx_REG ( TFmode , regno ) ; regno += 2 ; break ; case DFmode : reg = gen_rtx_REG ( DFmode , regno + 32 ) ; regno += 1 ; break ; case VOIDmode : gcc_assert ( CONST_INT_P ( operands [ i ] ) ) ; case DImode : reg = gen_rtx_REG ( DImode , regno ) ; regno += 1 ; break ; default : gcc_unreachable ( ) ; } emit_move_insn ( reg , operands [ i ] ) ; use_reg ( & usage , reg ) ; } switch ( GET_MODE ( target ) ) { case TFmode : reg = gen_rtx_REG ( TFmode , 16 ) ; break ; case DFmode : reg = gen_rtx_REG ( DFmode , 32 ) ; break ; case DImode : reg = gen_rtx_REG ( DImode , 0 ) ; break ; default : gcc_unreachable ( ) ; } rtx mem = gen_rtx_MEM ( QImode , func ) ; rtx_insn * tmp = emit_call_insn ( gen_call_value ( reg , mem , const0_rtx , const0_rtx , const0_rtx ) ) ; CALL_INSN_FUNCTION_USAGE ( tmp ) = usage ; RTL_CONST_CALL_P ( tmp ) = 1 ; tmp = get_insns ( ) ; end_sequence ( ) ; emit_libcall_block ( tmp , target , reg , equiv ) ; } </s>

Emit an X_floating library function call . Note that these functions do not follow normal calling conventions : TFmode arguments are passed in two integer registers ( as opposed to indirect ) ; TFmode return values appear in R16+R17 . FUNC is the function name to call . TARGET is where the output belongs . OPERANDS are the inputs . NOPERANDS is the count of inputs . EQUIV is the expression equivalent for the function .


<s>
void
mmix_asm_output_ascii
(
FILE
*
stream
,
const
char
*
string
,
int
length
)
{
while
(
length
>
0
)
{
int
chunk_size
=
length
>
60
60
:
length
;
fprintf
(
stream
,
"\tBYTE "
)
;
mmix_output_quoted_string
(
stream
,
string
,
chunk_size
)
;
string
+=
chunk_size
;
length
-=
chunk_size
;
fprintf
(
stream
,
"\n"
)
;
}
}
</s>


<s> bool isMem ( ) const { return Kind == Memory ; } </s>


<s> static unsigned long arm_compute_save_reg_mask ( void ) { unsigned int save_reg_mask = 0 ; unsigned long func_type = arm_current_func_type ( ) ; if ( IS_NAKED ( func_type ) ) return 0 ; if ( frame_pointer_needed ) save_reg_mask |= ( 1 << ARM_HARD_FRAME_POINTER_REGNUM ) | ( 1 << IP_REGNUM ) | ( 1 << LR_REGNUM ) | ( 1 << PC_REGNUM ) ; if ( IS_VOLATILE ( func_type ) ) return save_reg_mask ; save_reg_mask |= arm_compute_save_reg0_reg12_mask ( ) ; if ( regs_ever_live [ LR_REGNUM ] || ( save_reg_mask && optimize_size && ARM_FUNC_TYPE ( func_type ) == ARM_FT_NORMAL && ! current_function_calls_eh_return ) ) save_reg_mask |= 1 << LR_REGNUM ; if ( cfun -> machine -> lr_save_eliminated ) save_reg_mask &= ~ ( 1 << LR_REGNUM ) ; if ( TARGET_REALLY_IWMMXT && ( ( bit_count ( save_reg_mask ) + ARM_NUM_INTS ( current_function_pretend_args_size ) ) % 2 ) != 0 ) { unsigned int reg ; for ( reg = 4 ; reg <= 12 ; reg ++ ) if ( ( save_reg_mask & ( 1 << reg ) ) == 0 ) break ; if ( reg <= 12 ) save_reg_mask |= ( 1 << reg ) ; else { cfun -> machine -> sibcall_blocked = 1 ; save_reg_mask |= ( 1 << 3 ) ; } } return save_reg_mask ; } </s>

Compute a bit mask of which registers need to be saved on the stack for the current function . This is used by arm_get_frame_offsets , which may add extra registers .


<s> rtx mn10300_legitimize_pic_address ( rtx orig , rtx reg ) { rtx x ; if ( GET_CODE ( orig ) == LABEL_REF || ( GET_CODE ( orig ) == SYMBOL_REF && ( CONSTANT_POOL_ADDRESS_P ( orig ) || ! MN10300_GLOBAL_P ( orig ) ) ) ) { if ( reg == NULL ) reg = gen_reg_rtx ( Pmode ) ; x = gen_rtx_UNSPEC ( SImode , gen_rtvec ( 1 , orig ) , UNSPEC_GOTOFF ) ; x = gen_rtx_CONST ( SImode , x ) ; emit_move_insn ( reg , x ) ; x = emit_insn ( gen_addsi3 ( reg , reg , pic_offset_table_rtx ) ) ; } else if ( GET_CODE ( orig ) == SYMBOL_REF ) { if ( reg == NULL ) reg = gen_reg_rtx ( Pmode ) ; x = gen_rtx_UNSPEC ( SImode , gen_rtvec ( 1 , orig ) , UNSPEC_GOT ) ; x = gen_rtx_CONST ( SImode , x ) ; x = gen_rtx_PLUS ( SImode , pic_offset_table_rtx , x ) ; x = gen_const_mem ( SImode , x ) ; x = emit_move_insn ( reg , x ) ; } else return orig ; set_unique_reg_note ( x , REG_EQUAL , orig ) ; return reg ; } </s>

Convert a non-PIC address in ` orig ' to a PIC address using @ GOT or @ GOTOFF in ` reg ' .


<s> void reserveBlocks ( unsigned Size ) { Blocks . reserve ( Size ) ; } </s>


<s> bool X86PassConfig :: addPreRewrite ( ) { addPass ( createX86TileConfigPass ( ) ) ; return true ; } </s>

addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is complete , but before virtual registers are rewritten to physical registers .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 Execution Dependency Fix"
;
}
</s>

getPassName - Return a nice clean name for a pass .


runOnMachineFunction - Emit the function body .


<s> EVT ARMTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( ( ! IsMemset || ZeroMemset ) && Subtarget -> hasNEON ( ) && ! F -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { bool Fast ; if ( Size >= 16 && ( memOpAlign ( SrcAlign , DstAlign , 16 ) || ( allowsMisalignedMemoryAccesses ( MVT :: v2f64 , 0 , 1 , & Fast ) && Fast ) ) ) { return MVT :: v2f64 ; } else if ( Size >= 8 && ( memOpAlign ( SrcAlign , DstAlign , 8 ) || ( allowsMisalignedMemoryAccesses ( MVT :: f64 , 0 , 1 , & Fast ) && Fast ) ) ) { return MVT :: f64 ; } } return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> bool X86AsmParser :: MatchAndEmitInstruction ( SMLoc IDLoc , SmallVectorImpl < MCParsedAsmOperand * > & Operands , MCStreamer & Out ) { unsigned Kind ; unsigned Opcode ; unsigned ErrorInfo ; SmallVector < std :: pair < unsigned , std :: string > , 4 > MapAndConstraints ; bool Error = MatchInstruction ( IDLoc , Operands , Out , Kind , Opcode , MapAndConstraints , ErrorInfo ) ; return Error ; } </s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s>
bool
ARMAsmBackend
::
shouldForceRelocation
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
)
{
const
MCSymbolRefExpr
*
A
=
Target
.
getSymA
(
)
;
const
MCSymbol
*
Sym
=
A
&
A
->
getSymbol
(
)
:
nullptr
;
const
unsigned
FixupKind
=
Fixup
.
getKind
(
)
;
if
(
(
unsigned
)
Fixup
.
getKind
(
)
==
ARM
::
fixup_arm_thumb_bl
)
{
assert
(
Sym
&&
"How did we resolve this?"
)
;
if
(
Sym
->
isExternal
(
)
)
return
true
;
}
if
(
Sym
&&
Sym
->
isELF
(
)
)
{
unsigned
Type
=
cast
<
MCSymbolELF
>
(
Sym
)
->
getType
(
)
;
if
(
(
Type
==
ELF
::
STT_FUNC
||
Type
==
ELF
::
STT_GNU_IFUNC
)
)
{
if
(
Asm
.
isThumbFunc
(
Sym
)
&&
(
FixupKind
==
ARM
::
fixup_arm_uncondbranch
)
)
return
true
;
if
(
!
Asm
.
isThumbFunc
(
Sym
)
&&
(
FixupKind
==
ARM
::
fixup_arm_thumb_br
||
FixupKind
==
ARM
::
fixup_arm_thumb_bl
||
FixupKind
==
ARM
::
fixup_t2_condbranch
||
FixupKind
==
ARM
::
fixup_t2_uncondbranch
)
)
return
true
;
}
}
if
(
A
&&
(
FixupKind
==
ARM
::
fixup_arm_thumb_blx
||
FixupKind
==
ARM
::
fixup_arm_blx
||
FixupKind
==
ARM
::
fixup_arm_uncondbl
||
FixupKind
==
ARM
::
fixup_arm_condbl
)
)
return
true
;
return
false
;
}
</s>

Hook to check if a relocation is needed for some target specific reason .


<s> void MSP430AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MSP430MCInstLower MCInstLowering ( OutContext , * this ) ; MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void AMDGPUAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { AMDGPUMCInstLower MCInstLowering ( OutContext ) ; if ( MI -> isBundle ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator I = MI ; ++ I ; while ( I != MBB -> end ( ) && I -> isInsideBundle ( ) ) { MCInst MCBundleInst ; const MachineInstr * BundledInst = I ; MCInstLowering . lower ( BundledInst , MCBundleInst ) ; OutStreamer . EmitInstruction ( MCBundleInst ) ; ++ I ; } } else { MCInst TmpInst ; MCInstLowering . lower ( MI , TmpInst ) ; OutStreamer . EmitInstruction ( TmpInst ) ; } } </s>


<s> const MCRegisterInfo * getMRI ( ) const { return const_cast < AMDGPUAsmParser * > ( this ) -> getContext ( ) . getRegisterInfo ( ) ; } </s>


<s> bool arm_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( GET_MODE_CLASS ( mode1 ) == GET_MODE_CLASS ( mode2 ) ) return true ; if ( TARGET_NEON && ( VALID_NEON_DREG_MODE ( mode1 ) || VALID_NEON_QREG_MODE ( mode1 ) || VALID_NEON_STRUCT_MODE ( mode1 ) ) && ( VALID_NEON_DREG_MODE ( mode2 ) || VALID_NEON_QREG_MODE ( mode2 ) || VALID_NEON_STRUCT_MODE ( mode2 ) ) ) return true ; return false ; } </s>


<s>
bool
HexagonPacketizer
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
DisablePacketizer
)
return
false
;
HII
=
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getInstrInfo
(
)
;
HRI
=
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getRegisterInfo
(
)
;
auto
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
auto
*
AA
=
&
getAnalysis
<
AAResultsWrapperPass
>
(
)
.
getAAResults
(
)
;
auto
*
MBPI
=
&
getAnalysis
<
MachineBranchProbabilityInfo
>
(
)
;
if
(
EnableGenAllInsnClass
)
HII
->
genAllInsnTimingClasses
(
MF
)
;
HexagonPacketizerList
Packetizer
(
MF
,
MLI
,
AA
,
MBPI
)
;
assert
(
Packetizer
.
getResourceTracker
(
)
&&
"Empty DFA table!"
)
;
for
(
auto
&
MB
:
MF
)
{
auto
End
=
MB
.
end
(
)
;
auto
MI
=
MB
.
begin
(
)
;
while
(
MI
!=
End
)
{
auto
NextI
=
std
::
next
(
MI
)
;
if
(
MI
->
isKill
(
)
)
{
MB
.
erase
(
MI
)
;
End
=
MB
.
end
(
)
;
}
MI
=
NextI
;
}
}
for
(
auto
&
MB
:
MF
)
{
auto
Begin
=
MB
.
begin
(
)
,
End
=
MB
.
end
(
)
;
while
(
Begin
!=
End
)
{
MachineBasicBlock
::
iterator
RB
=
Begin
;
while
(
RB
!=
End
&&
HII
->
isSchedulingBoundary
(
RB
,
&
MB
,
MF
)
)
++
RB
;
MachineBasicBlock
::
iterator
RE
=
RB
;
while
(
RE
!=
End
&&
!
HII
->
isSchedulingBoundary
(
RE
,
&
MB
,
MF
)
)
++
RE
;
if
(
RE
!=
End
)
++
RE
;
if
(
RB
!=
End
)
Packetizer
.
PacketizeMIs
(
&
MB
,
RB
,
RE
)
;
Begin
=
RE
;
}
}
Packetizer
.
unpacketizeSoloInstrs
(
MF
)
;
return
true
;
}
</s>

Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
"Empty DFA table!"


<s> static void frv_start_packet_block ( void ) { state_reset ( frv_packet . dfa_state ) ; frv_start_packet ( ) ; } </s>

Likewise for the start of a new basic block .


<s> std :: string getDataLayout ( ) const { const char * p ; p = "e-p:32:32:32" ; return std :: string ( p ) ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> void visium_expand_copysign ( rtx * operands , enum machine_mode mode ) { rtx dest = operands [ 0 ] ; rtx op0 = operands [ 1 ] ; rtx op1 = operands [ 2 ] ; rtx mask = force_reg ( SImode , GEN_INT ( 0x7fffffff ) ) ; rtx x ; gcc_assert ( mode == SFmode ) ; if ( GET_CODE ( op0 ) == CONST_DOUBLE ) { if ( real_isneg ( CONST_DOUBLE_REAL_VALUE ( op0 ) ) ) op0 = simplify_unary_operation ( ABS , mode , op0 , mode ) ; if ( op0 != CONST0_RTX ( mode ) ) { long l ; REAL_VALUE_TYPE rv ; REAL_VALUE_FROM_CONST_DOUBLE ( rv , op0 ) ; REAL_VALUE_TO_TARGET_SINGLE ( rv , l ) ; op0 = force_reg ( SImode , GEN_INT ( trunc_int_for_mode ( l , SImode ) ) ) ; } } else { op0 = copy_to_mode_reg ( SImode , gen_lowpart ( SImode , op0 ) ) ; op0 = force_reg ( SImode , gen_rtx_AND ( SImode , op0 , mask ) ) ; } mask = force_reg ( SImode , gen_rtx_NOT ( SImode , mask ) ) ; op1 = copy_to_mode_reg ( SImode , gen_lowpart ( SImode , op1 ) ) ; op1 = force_reg ( SImode , gen_rtx_AND ( SImode , op1 , mask ) ) ; if ( op0 == CONST0_RTX ( SFmode ) ) x = op1 ; else x = force_reg ( SImode , gen_rtx_IOR ( SImode , op0 , op1 ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , gen_lowpart ( SFmode , x ) ) ) ; } </s>


Implement the TARGET_CPU_CPP_BUILTINS macro


<s> bool isReg ( ) const { return Kind == CV_Register ; } </s>


<s> void LEGMCInstLower :: Initialize ( Mangler * M , MCContext * C ) { Mang = M ; Ctx = C ; } </s>

This method must be called before any actual lowering is done .


<s>
bool
CSKYInstrInfo
::
reverseBranchCondition
(
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
assert
(
(
Cond
.
size
(
)
==
2
)
&&
"Invalid branch condition!"
)
;
Cond
[
0
]
.
setImm
(
getOppositeBranchOpc
(
Cond
[
0
]
.
getImm
(
)
)
)
;
return
false
;
}
</s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> bool X86TargetLowering :: hasAndNot ( SDValue Y ) const { EVT VT = Y . getValueType ( ) ; if ( ! VT . isVector ( ) ) return hasAndNotCompare ( Y ) ; if ( ! Subtarget . hasSSE1 ( ) || VT . getSizeInBits ( ) < 128 ) return false ; if ( VT == MVT :: v4i32 ) return true ; return Subtarget . hasSSE2 ( ) ; } </s>

Return true if the target has a bitwise and-not operation : X = ~A & B This can be used to simplify select or other instructions .


<s> int rl78_hard_regno_mode_ok ( int regno , machine_mode mode ) { int s = GET_MODE_SIZE ( mode ) ; if ( s < 1 ) return 0 ; if ( regno == 23 || regno == ES_REG || regno == CS_REG ) return 0 ; if ( regno == FP_REG && s == 2 ) return 1 ; if ( regno < SP_REG ) { if ( s > 1 && ( regno % 2 ) ) return 0 ; return 1 ; } if ( s == CC_REGNUM ) return ( mode == BImode ) ; if ( s == register_sizes [ regno ] ) return 1 ; return 0 ; } </s>


<s>
bool
SystemZDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
SystemZAddressingMode
::
AddrForm
Form
;
SystemZAddressingMode
::
DispRange
DispRange
;
SDValue
Base
,
Disp
,
Index
;
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
case
InlineAsm
::
Constraint_Q
:
Form
=
SystemZAddressingMode
::
FormBD
;
DispRange
=
SystemZAddressingMode
::
Disp12Only
;
break
;
case
InlineAsm
::
Constraint_R
:
Form
=
SystemZAddressingMode
::
FormBDXNormal
;
DispRange
=
SystemZAddressingMode
::
Disp12Only
;
break
;
case
InlineAsm
::
Constraint_S
:
Form
=
SystemZAddressingMode
::
FormBD
;
DispRange
=
SystemZAddressingMode
::
Disp20Only
;
break
;
case
InlineAsm
::
Constraint_T
:
case
InlineAsm
::
Constraint_m
:
Form
=
SystemZAddressingMode
::
FormBDXNormal
;
DispRange
=
SystemZAddressingMode
::
Disp20Only
;
break
;
}
if
(
selectBDXAddr
(
Form
,
DispRange
,
Op
,
Base
,
Disp
,
Index
)
)
{
const
TargetRegisterClass
*
TRC
=
Subtarget
->
getRegisterInfo
(
)
->
getPointerRegClass
(
*
MF
)
;
SDLoc
DL
(
Base
)
;
SDValue
RC
=
CurDAG
->
getTargetConstant
(
TRC
->
getID
(
)
,
DL
,
MVT
::
i32
)
;
if
(
Base
.
getOpcode
(
)
!=
ISD
::
TargetFrameIndex
&&
Base
.
getOpcode
(
)
!=
ISD
::
Register
)
{
Base
=
SDValue
(
CurDAG
->
getMachineNode
(
TargetOpcode
::
COPY_TO_REGCLASS
,
DL
,
Base
.
getValueType
(
)
,
Base
,
RC
)
,
0
)
;
}
if
(
Index
.
getOpcode
(
)
!=
ISD
::
Register
)
{
Index
=
SDValue
(
CurDAG
->
getMachineNode
(
TargetOpcode
::
COPY_TO_REGCLASS
,
DL
,
Index
.
getValueType
(
)
,
Index
,
RC
)
,
0
)
;
}
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Disp
)
;
OutOps
.
push_back
(
Index
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s>
SDValue
GBZ80TargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
auto
CCFunction
=
CCAssignFnForReturn
(
CallConv
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
CCFunction
)
;
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
unsigned
e
=
RVLocs
.
size
(
)
;
if
(
e
>
1
)
{
std
::
reverse
(
RVLocs
.
begin
(
)
,
RVLocs
.
end
(
)
)
;
}
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
if
(
MF
.
getFunction
(
)
.
getAttributes
(
)
.
hasAttribute
(
AttributeList
::
FunctionIndex
,
Attribute
::
Naked
)
)
{
return
Chain
;
}
unsigned
RetOpc
=
GBISD
::
RET_FLAG
;
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
{
RetOps
.
push_back
(
Flag
)
;
}
return
DAG
.
getNode
(
RetOpc
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s>
MCSymbol
*
KudeyarMCInstLower
::
GetBlockAddressSymbol
(
const
MachineOperand
&
MO
)
const
{
switch
(
MO
.
getTargetFlags
(
)
)
{
default
:
llvm_unreachable
(
"Unknown target flag on GV operand"
)
;
case
0
:
break
;
}
return
Printer
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
;
}
</s>

Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block .

Kudeyar
Kudeyar
"Unknown target flag on GV operand"
0


<s> static rtx_insn * cris_md_asm_adjust ( vec < rtx > & outputs , vec < rtx > & inputs , vec < machine_mode > & , vec < const char * > & constraints , vec < rtx > & clobbers , HARD_REG_SET & clobbered_regs ) { clobbers . safe_push ( gen_rtx_REG ( CCmode , CRIS_CC0_REGNUM ) ) ; SET_HARD_REG_BIT ( clobbered_regs , CRIS_CC0_REGNUM ) ; for ( unsigned i = 0 , n = constraints . length ( ) ; i < n ; ++ i ) if ( strchr ( constraints [ i ] , 'h' ) != NULL ) return NULL ; rtx mof_reg = gen_rtx_REG ( SImode , CRIS_MOF_REGNUM ) ; for ( unsigned i = 0 , n = outputs . length ( ) ; i < n ; ++ i ) if ( reg_overlap_mentioned_p ( mof_reg , outputs [ i ] ) ) return NULL ; for ( unsigned i = 0 , n = inputs . length ( ) ; i < n ; ++ i ) if ( reg_overlap_mentioned_p ( mof_reg , inputs [ i ] ) ) return NULL ; clobbers . safe_push ( mof_reg ) ; SET_HARD_REG_BIT ( clobbered_regs , CRIS_MOF_REGNUM ) ; return NULL ; } </s>

Worker function for TARGET_MD_ASM_ADJUST .


<s> bool SNESDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < SNESSubtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>


"Odd number of callee-saved regs to spill!"

"Expected GPR64 callee-saved register pair!"

"Expected FPR64 callee-saved register pair!"

"Offset out of bounds for LDP immediate"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> void expand_move ( rtx * operands , enum machine_mode mode ) { if ( flag_pic && SYMBOLIC_CONST ( operands [ 1 ] ) ) emit_pic_move ( operands , mode ) ; else if ( ( reload_in_progress | reload_completed ) == 0 && GET_CODE ( operands [ 0 ] ) == MEM && GET_CODE ( operands [ 1 ] ) != REG ) operands [ 1 ] = force_reg ( mode , operands [ 1 ] ) ; } </s>

Expand a move operation in mode MODE . The operands are in OPERANDS .


<s> void arm_load_pic_register ( unsigned long saved_regs ATTRIBUTE_UNUSED ) { rtx l1 , labelno , pic_tmp , pic_tmp2 , pic_rtx ; rtx global_offset_table ; if ( current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE ) return ; gcc_assert ( flag_pic ) ; labelno = GEN_INT ( pic_labelno ++ ) ; l1 = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , labelno ) , UNSPEC_PIC_LABEL ) ; l1 = gen_rtx_CONST ( VOIDmode , l1 ) ; global_offset_table = gen_rtx_SYMBOL_REF ( Pmode , "_GLOBAL_OFFSET_TABLE_" ) ; pic_tmp = plus_constant ( l1 , TARGET_ARM ? 8 : 4 ) ; if ( GOT_PCREL ) pic_tmp2 = gen_rtx_CONST ( VOIDmode , gen_rtx_PLUS ( Pmode , global_offset_table , pc_rtx ) ) ; else pic_tmp2 = gen_rtx_CONST ( VOIDmode , global_offset_table ) ; pic_rtx = gen_rtx_CONST ( Pmode , gen_rtx_MINUS ( Pmode , pic_tmp2 , pic_tmp ) ) ; if ( TARGET_ARM ) { emit_insn ( gen_pic_load_addr_arm ( pic_offset_table_rtx , pic_rtx ) ) ; emit_insn ( gen_pic_add_dot_plus_eight ( pic_offset_table_rtx , pic_offset_table_rtx , labelno ) ) ; } else { if ( REGNO ( pic_offset_table_rtx ) > LAST_LO_REGNUM ) { pic_tmp = gen_rtx_REG ( SImode , thumb_find_work_register ( saved_regs ) ) ; emit_insn ( gen_pic_load_addr_thumb ( pic_tmp , pic_rtx ) ) ; emit_insn ( gen_movsi ( pic_offset_table_rtx , pic_tmp ) ) ; } else emit_insn ( gen_pic_load_addr_thumb ( pic_offset_table_rtx , pic_rtx ) ) ; emit_insn ( gen_pic_add_dot_plus_four ( pic_offset_table_rtx , pic_offset_table_rtx , labelno ) ) ; } emit_insn ( gen_rtx_USE ( VOIDmode , pic_offset_table_rtx ) ) ; } </s>

Generate code to load the PIC register . In thumb mode SCRATCH is a low register .


"\nrs6000_rtx_costs, return = %s, mode = %s, outer_code = %s, "

"opno = %d, total = %d, speed = %s, x:\n"

Debug form of r6000_rtx_costs that is selected if -mdebug=cost .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


"Module has aliases, which NVPTX does not support."

"Module has a nontrivial global ctor, which NVPTX does not support."

"Module has a nontrivial global dtor, which NVPTX does not support."

Set up the AsmPrinter when we are working on a new module .


<s> void X86AsmParser :: EmitInstruction ( MCInst & Inst , OperandVector & Operands , MCStreamer & Out ) { Out . EmitInstruction ( Inst , getSTI ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static void mcore_unique_section ( tree decl , int reloc ATTRIBUTE_UNUSED ) { int len ; const char * name ; char * string ; const char * prefix ; name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; name = ( * targetm . strip_name_encoding ) ( name ) ; if ( TREE_CODE ( decl ) == FUNCTION_DECL ) prefix = ".text$" ; else if ( decl_readonly_section ( decl , 0 ) ) prefix = ".rdata$" ; else prefix = ".data$" ; len = strlen ( name ) + strlen ( prefix ) ; string = XALLOCAVEC ( char , len + 1 ) ; sprintf ( string , "%s%s" , prefix , name ) ; set_decl_section_name ( decl , string ) ; } </s>


<s> bool X86AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < X86Subtarget > ( ) ; SMShadowTracker . startFunction ( MF ) ; CodeEmitter . reset ( TM . getTarget ( ) . createMCCodeEmitter ( * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegisterInfo ( ) , MF . getContext ( ) ) ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Local = MF . getFunction ( ) -> hasLocalLinkage ( ) ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Local ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; emitXRayTable ( ) ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool SystemZAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & OS ) { if ( ExtraCode && * ExtraCode == 'n' ) { if ( ! MI -> getOperand ( OpNo ) . isImm ( ) ) return true ; OS << - int64_t ( MI -> getOperand ( OpNo ) . getImm ( ) ) ; } else { SystemZMCInstLower Lower ( MF -> getContext ( ) , * this ) ; MCOperand MO ( Lower . lowerOperand ( MI -> getOperand ( OpNo ) ) ) ; SystemZInstPrinter :: printOperand ( MO , MAI , OS ) ; } return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static void loongarch_conditional_register_usage ( void ) { if ( ! TARGET_HARD_FLOAT ) accessible_reg_set &= ~ ( reg_class_contents [ FP_REGS ] | reg_class_contents [ FCC_REGS ] ) ; } </s>


<s>
const
RegisterBankInfo
*
AArch64Subtarget
::
getRegBankInfo
(
)
const
{
assert
(
GISel
&&
"Access to GlobalISel APIs not set"
)
;
return
GISel
->
getRegBankInfo
(
)
;
}
</s>

If the information for the register banks is available , return it .


<s> bool SILowerControlFlowPass :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const SIInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; TRI = static_cast < const SIRegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; bool HaveKill = false ; bool NeedM0 = false ; bool NeedWQM = false ; unsigned Depth = 0 ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ; MachineBasicBlock :: iterator I , Next ; for ( I = MBB . begin ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; if ( TII -> isDS ( MI . getOpcode ( ) ) ) { NeedM0 = true ; NeedWQM = true ; } switch ( MI . getOpcode ( ) ) { default : break ; case AMDGPU :: SI_IF : ++ Depth ; If ( MI ) ; break ; case AMDGPU :: SI_ELSE : Else ( MI ) ; break ; case AMDGPU :: SI_BREAK : Break ( MI ) ; break ; case AMDGPU :: SI_IF_BREAK : IfBreak ( MI ) ; break ; case AMDGPU :: SI_ELSE_BREAK : ElseBreak ( MI ) ; break ; case AMDGPU :: SI_LOOP : ++ Depth ; Loop ( MI ) ; break ; case AMDGPU :: SI_END_CF : if ( -- Depth == 0 && HaveKill ) { SkipIfDead ( MI ) ; HaveKill = false ; } EndCf ( MI ) ; break ; case AMDGPU :: SI_KILL : if ( Depth == 0 ) SkipIfDead ( MI ) ; else HaveKill = true ; Kill ( MI ) ; break ; case AMDGPU :: S_BRANCH : Branch ( MI ) ; break ; case AMDGPU :: SI_INDIRECT_SRC : IndirectSrc ( MI ) ; break ; case AMDGPU :: SI_INDIRECT_DST_V1 : case AMDGPU :: SI_INDIRECT_DST_V2 : case AMDGPU :: SI_INDIRECT_DST_V4 : case AMDGPU :: SI_INDIRECT_DST_V8 : case AMDGPU :: SI_INDIRECT_DST_V16 : IndirectDst ( MI ) ; break ; case AMDGPU :: V_INTERP_P1_F32 : case AMDGPU :: V_INTERP_P2_F32 : case AMDGPU :: V_INTERP_MOV_F32 : NeedWQM = true ; break ; } } } if ( NeedM0 ) { MachineBasicBlock & MBB = MF . front ( ) ; InitM0ForLDS ( MBB . getFirstNonPHI ( ) ) ; } if ( NeedWQM && MFI -> ShaderType == ShaderType :: PIXEL ) { MachineBasicBlock & MBB = MF . front ( ) ; BuildMI ( MBB , MBB . getFirstNonPHI ( ) , DebugLoc ( ) , TII -> get ( AMDGPU :: S_WQM_B64 ) , AMDGPU :: EXEC ) . addReg ( AMDGPU :: EXEC ) ; } return true ; } </s>

R600 SI SI SI SI SI 0 SI SI SI SI SI SI SI 0 SI 0 SI SI SI SI SI SI


<s> unsigned Z80InstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( isFrameLoadOpcode ( MI . getOpcode ( ) ) && ! MI . getOperand ( 0 ) . getSubReg ( ) && isFrameOperand ( MI , 1 , FrameIndex ) ) return MI . getOperand ( 0 ) . getReg ( ) ; return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s>
void
SystemZInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
DebugLoc
::
getUnknownLoc
(
)
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
unsigned
Opc
=
0
;
if
(
RC
==
&
SystemZ
::
GR32RegClass
||
RC
==
&
SystemZ
::
ADDR32RegClass
)
Opc
=
SystemZ
::
MOV32mr
;
else
if
(
RC
==
&
SystemZ
::
GR64RegClass
||
RC
==
&
SystemZ
::
ADDR64RegClass
)
{
Opc
=
SystemZ
::
MOV64mr
;
}
else
if
(
RC
==
&
SystemZ
::
FP32RegClass
)
{
Opc
=
SystemZ
::
FMOV32mr
;
}
else
if
(
RC
==
&
SystemZ
::
FP64RegClass
)
{
Opc
=
SystemZ
::
FMOV64mr
;
}
else
if
(
RC
==
&
SystemZ
::
GR64PRegClass
)
{
Opc
=
SystemZ
::
MOV64Pmr
;
}
else
if
(
RC
==
&
SystemZ
::
GR128RegClass
)
{
Opc
=
SystemZ
::
MOV128mr
;
}
else
llvm_unreachable
(
"Unsupported regclass to store"
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
}
</s>


<s> bool NVPTXTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , unsigned Intrinsic ) const { switch ( Intrinsic ) { default : return false ; case Intrinsic :: nvvm_atomic_load_add_f32 : Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: f32 ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . vol = 0 ; Info . readMem = true ; Info . writeMem = true ; Info . align = 0 ; return true ; case Intrinsic :: nvvm_atomic_load_inc_32 : case Intrinsic :: nvvm_atomic_load_dec_32 : Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: i32 ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . vol = 0 ; Info . readMem = true ; Info . writeMem = true ; Info . align = 0 ; return true ; case Intrinsic :: nvvm_ldu_global_i : case Intrinsic :: nvvm_ldu_global_f : case Intrinsic :: nvvm_ldu_global_p : Info . opc = ISD :: INTRINSIC_W_CHAIN ; if ( Intrinsic == Intrinsic :: nvvm_ldu_global_i ) Info . memVT = MVT :: i32 ; else if ( Intrinsic == Intrinsic :: nvvm_ldu_global_p ) Info . memVT = getPointerTy ( ) ; else Info . memVT = MVT :: f32 ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . vol = 0 ; Info . readMem = true ; Info . writeMem = false ; Info . align = 0 ; return true ; } return false ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> unsigned ARMBaseRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) return FramePtr ; return ARM :: SP ; } </s>


<s> BitVector IA64RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( IA64 :: r0 ) ; Reserved . set ( IA64 :: r1 ) ; Reserved . set ( IA64 :: r2 ) ; Reserved . set ( IA64 :: r5 ) ; Reserved . set ( IA64 :: r12 ) ; Reserved . set ( IA64 :: r13 ) ; Reserved . set ( IA64 :: r22 ) ; Reserved . set ( IA64 :: rp ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> MVT X86TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned Align , bool isSrcConst , bool isSrcStr ) const { if ( ! NoImplicitFloat && Subtarget -> getStackAlignment ( ) >= 16 ) { if ( ( isSrcConst || isSrcStr ) && Subtarget -> hasSSE2 ( ) && Size >= 16 ) return MVT :: v4i32 ; if ( ( isSrcConst || isSrcStr ) && Subtarget -> hasSSE1 ( ) && Size >= 16 ) return MVT :: v4f32 ; } if ( Subtarget -> is64Bit ( ) && Size >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s>
bool
processBlock
(
MachineBasicBlock
&
MBB
)
{
bool
Changed
=
false
;
bool
Is64Bit
=
MBB
.
getParent
(
)
->
getSubtarget
<
PPCSubtarget
>
(
)
.
isPPC64
(
)
;
for
(
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
,
IE
=
MBB
.
end
(
)
;
I
!=
IE
;
)
{
MachineInstr
*
MI
=
I
;
if
(
MI
->
getOpcode
(
)
!=
PPC
::
ADDItlsgdLADDR
&&
MI
->
getOpcode
(
)
!=
PPC
::
ADDItlsldLADDR
&&
MI
->
getOpcode
(
)
!=
PPC
::
ADDItlsgdLADDR32
&&
MI
->
getOpcode
(
)
!=
PPC
::
ADDItlsldLADDR32
)
{
++
I
;
continue
;
}
DEBUG
(
dbgs
(
)
<<
"TLS Dynamic Call Fixup:\n    "
<<
*
MI
;
)
;
unsigned
OutReg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
unsigned
InReg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
DebugLoc
DL
=
MI
->
getDebugLoc
(
)
;
unsigned
GPR3
=
Is64Bit
PPC
::
X3
:
PPC
::
R3
;
unsigned
Opc1
,
Opc2
;
const
unsigned
OrigRegs
[
]
=
{
OutReg
,
InReg
,
GPR3
}
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Opcode inconsistency error"
)
;
case
PPC
::
ADDItlsgdLADDR
:
Opc1
=
PPC
::
ADDItlsgdL
;
Opc2
=
PPC
::
GETtlsADDR
;
break
;
case
PPC
::
ADDItlsldLADDR
:
Opc1
=
PPC
::
ADDItlsldL
;
Opc2
=
PPC
::
GETtlsldADDR
;
break
;
case
PPC
::
ADDItlsgdLADDR32
:
Opc1
=
PPC
::
ADDItlsgdL32
;
Opc2
=
PPC
::
GETtlsADDR32
;
break
;
case
PPC
::
ADDItlsldLADDR32
:
Opc1
=
PPC
::
ADDItlsldL32
;
Opc2
=
PPC
::
GETtlsldADDR32
;
break
;
}
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
PPC
::
ADJCALLSTACKDOWN
)
)
.
addImm
(
0
)
;
MachineInstr
*
Addi
=
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
Opc1
)
,
GPR3
)
.
addReg
(
InReg
)
;
Addi
->
addOperand
(
MI
->
getOperand
(
2
)
)
;
MachineBasicBlock
::
iterator
First
=
I
;
First
;
MachineInstr
*
Call
=
(
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
Opc2
)
,
GPR3
)
.
addReg
(
GPR3
)
)
;
Call
->
addOperand
(
MI
->
getOperand
(
3
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
PPC
::
ADJCALLSTACKUP
)
)
.
addImm
(
0
)
.
addImm
(
0
)
;
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
TargetOpcode
::
COPY
)
,
OutReg
)
.
addReg
(
GPR3
)
;
MachineBasicBlock
::
iterator
Last
=
I
;
Last
;
++
I
;
MI
->
removeFromParent
(
)
;
LIS
->
repairIntervalsInRange
(
&
MBB
,
First
,
Last
,
OrigRegs
)
;
Changed
=
true
;
}
return
Changed
;
}
</s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s> MachineBasicBlock :: iterator AArch64InstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , const MachineOutlinerInfo & MInfo ) const { if ( MInfo . CallConstructionID == MachineOutlinerTailCall ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: B ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; return It ; } if ( MInfo . CallConstructionID == MachineOutlinerNoLRSave ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: BL ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; return It ; } MachineInstr * STRXpre = BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: STRXpre ) ) . addReg ( AArch64 :: SP , RegState :: Define ) . addReg ( AArch64 :: LR ) . addReg ( AArch64 :: SP ) . addImm ( - 16 ) ; It = MBB . insert ( It , STRXpre ) ; It ++ ; It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: BL ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; It ++ ; MachineInstr * LDRXpost = BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: LDRXpost ) ) . addReg ( AArch64 :: SP , RegState :: Define ) . addReg ( AArch64 :: LR , RegState :: Define ) . addReg ( AArch64 :: SP ) . addImm ( 16 ) ; It = MBB . insert ( It , LDRXpost ) ; return It ; } </s>

Insert a call to an outlined function into the program .


<s> static tree riscv_d_handle_target_float_abi ( void ) { const char * abi ; switch ( riscv_abi ) { case ABI_ILP32E : case ABI_ILP32 : case ABI_LP64 : abi = "soft" ; break ; case ABI_ILP32F : case ABI_LP64F : abi = "single" ; break ; case ABI_ILP32D : case ABI_LP64D : abi = "double" ; break ; default : abi = "" ; break ; } return build_string_literal ( strlen ( abi ) + 1 , abi ) ; } </s>

Handle a call to ` __traits ( getTargetInfo , `` floatAbi '' ) ' .


<s> static rtx vprop_gen ( rtx reg , propagate_mask pm , unsigned ARG_UNUSED ( count ) , void * ARG_UNUSED ( data ) ) { if ( ! ( pm & PM_read_write ) ) return 0 ; return nvptx_gen_vcast ( reg ) ; } </s>


<s> bool MBlazeAsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { size_t dotLoc = Name . find ( '.' ) ; Operands . push_back ( MBlazeOperand :: CreateToken ( Name . substr ( 0 , dotLoc ) , NameLoc ) ) ; if ( dotLoc < Name . size ( ) ) Operands . push_back ( MBlazeOperand :: CreateToken ( Name . substr ( dotLoc ) , NameLoc ) ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( ! ParseOperand ( Operands ) ) return true ; while ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) && getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( ! ParseOperand ( Operands ) ) return true ; } if ( Name . startswith ( "lw" ) || Name . startswith ( "sw" ) || Name . startswith ( "lh" ) || Name . startswith ( "sh" ) || Name . startswith ( "lb" ) || Name . startswith ( "sb" ) ) return ( ParseMemory ( Operands ) == NULL ) ; return false ; } </s>

ParseInstruction - Parse one assembly instruction .

MBlaze MBlaze MBlaze 0 MBlaze "lw" "sw" "lh" "sh" "lb" "sb"


"Only Linux target is expected to contain LOAD_STACK_GUARD"

"Invalid D-Form Pseudo-ops on non-P9 target."

"D-form op must have register and immediate operands"

This function is called for all pseudo instructions that remain after register allocation .


<s> unsigned X86InstrInfo :: getPartialRegUpdateClearance ( const MachineInstr & MI , unsigned OpNum , const TargetRegisterInfo * TRI ) const { if ( OpNum != 0 || ! hasPartialRegUpdate ( MI . getOpcode ( ) , Subtarget ) ) return 0 ; const MachineOperand & MO = MI . getOperand ( 0 ) ; Register Reg = MO . getReg ( ) ; if ( Register :: isVirtualRegister ( Reg ) ) { if ( MO . readsReg ( ) || MI . readsVirtualRegister ( Reg ) ) return 0 ; } else { if ( MI . readsRegister ( Reg , TRI ) ) return 0 ; } return PartialRegUpdateClearance ; } </s>

Inform the BreakFalseDeps pass how many idle instructions we would like before a partial register update .


"Did not fully process a global variable"

EmitGlobals - Emit all of the global variables to memory , storing their addresses into GlobalAddress .


<s> int small_data_operand ( rtx op ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED ) { rtx sym_ref ; if ( rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA ) return 0 ; if ( DEFAULT_ABI != ABI_V4 ) return 0 ; if ( SYMBOL_REF_P ( op ) ) sym_ref = op ; else if ( GET_CODE ( op ) != CONST || GET_CODE ( XEXP ( op , 0 ) ) != PLUS || ! SYMBOL_REF_P ( XEXP ( XEXP ( op , 0 ) , 0 ) ) || ! CONST_INT_P ( XEXP ( XEXP ( op , 0 ) , 1 ) ) ) return 0 ; else { rtx sum = XEXP ( op , 0 ) ; HOST_WIDE_INT summand ; summand = INTVAL ( XEXP ( sum , 1 ) ) ; if ( summand < 0 || summand > g_switch_value ) return 0 ; sym_ref = XEXP ( sum , 0 ) ; } return SYMBOL_REF_SMALL_P ( sym_ref ) ; return 0 ; } </s>

Return 1 for an operand in small memory on V.4/eabi .


<s> void push ( WeightedLeaf L , bool SeparateConst = true ) { if ( ! HaveConst && SeparateConst && isa < ConstantSDNode > ( L . Value ) ) { if ( Opcode == ISD :: MUL && cast < ConstantSDNode > ( L . Value ) -> getSExtValue ( ) == 1 ) return ; if ( Opcode == ISD :: ADD && cast < ConstantSDNode > ( L . Value ) -> getSExtValue ( ) == 0 ) return ; HaveConst = true ; ConstElt = L ; } else { Q . push_back ( L ) ; std :: push_heap ( Q . begin ( ) , Q . end ( ) , WeightedLeaf :: Compare ) ; } } </s>


<s> bool X86InstrInfo :: analyzeCompare ( const MachineInstr * MI , unsigned & SrcReg , unsigned & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case X86 :: CMP64ri32 : case X86 :: CMP64ri8 : case X86 :: CMP32ri : case X86 :: CMP32ri8 : case X86 :: CMP16ri : case X86 :: CMP16ri8 : case X86 :: CMP8ri : SrcReg = MI -> getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = MI -> getOperand ( 1 ) . getImm ( ) ; return true ; case X86 :: SUB64rm : case X86 :: SUB32rm : case X86 :: SUB16rm : case X86 :: SUB8rm : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case X86 :: SUB64rr : case X86 :: SUB32rr : case X86 :: SUB16rr : case X86 :: SUB8rr : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; SrcReg2 = MI -> getOperand ( 2 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case X86 :: SUB64ri32 : case X86 :: SUB64ri8 : case X86 :: SUB32ri : case X86 :: SUB32ri8 : case X86 :: SUB16ri : case X86 :: SUB16ri8 : case X86 :: SUB8ri : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = MI -> getOperand ( 2 ) . getImm ( ) ; return true ; case X86 :: CMP64rr : case X86 :: CMP32rr : case X86 :: CMP16rr : case X86 :: CMP8rr : SrcReg = MI -> getOperand ( 0 ) . getReg ( ) ; SrcReg2 = MI -> getOperand ( 1 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case X86 :: TEST8rr : case X86 :: TEST16rr : case X86 :: TEST32rr : case X86 :: TEST64rr : SrcReg = MI -> getOperand ( 0 ) . getReg ( ) ; if ( MI -> getOperand ( 1 ) . getReg ( ) != SrcReg ) return false ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> const MCExpr * PPC64LinuxTargetObjectFile :: getDebugThreadLocalSymbol ( const MCSymbol * Sym ) const { const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_DTPREL , getContext ( ) ) ; return MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( 0x8000 , getContext ( ) ) , getContext ( ) ) ; } </s>

Describe a TLS variable address within debug info .


<s> void ARMBaseRegisterInfo :: getRegAllocationHints ( unsigned VirtReg , ArrayRef < MCPhysReg > Order , SmallVectorImpl < MCPhysReg > & Hints , const MachineFunction & MF , const VirtRegMap * VRM , const LiveRegMatrix * Matrix ) const { const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; std :: pair < unsigned , unsigned > Hint = MRI . getRegAllocationHint ( VirtReg ) ; unsigned Odd ; switch ( Hint . first ) { case ARMRI :: RegPairEven : Odd = 0 ; break ; case ARMRI :: RegPairOdd : Odd = 1 ; break ; default : TargetRegisterInfo :: getRegAllocationHints ( VirtReg , Order , Hints , MF , VRM ) ; return ; } unsigned Paired = Hint . second ; if ( Paired == 0 ) return ; unsigned PairedPhys = 0 ; if ( TargetRegisterInfo :: isPhysicalRegister ( Paired ) ) { PairedPhys = Paired ; } else if ( VRM && VRM -> hasPhys ( Paired ) ) { PairedPhys = getPairedGPR ( VRM -> getPhys ( Paired ) , Odd , this ) ; } if ( PairedPhys && std :: find ( Order . begin ( ) , Order . end ( ) , PairedPhys ) != Order . end ( ) ) Hints . push_back ( PairedPhys ) ; for ( unsigned I = 0 , E = Order . size ( ) ; I != E ; ++ I ) { unsigned Reg = Order [ I ] ; if ( Reg == PairedPhys || ( getEncodingValue ( Reg ) & 1 ) != Odd ) continue ; unsigned Paired = getPairedGPR ( Reg , ! Odd , this ) ; if ( ! Paired || MRI . isReserved ( Paired ) ) continue ; Hints . push_back ( Reg ) ; } } </s>

Get a list of 'hint ' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg .


<s>
std
::
vector
<
const
SUnit
*
>
GCNILPScheduler
::
schedule
(
ArrayRef
<
const
SUnit
*
>
BotRoots
,
const
ScheduleDAG
&
DAG
)
{
auto
&
SUnits
=
const_cast
<
ScheduleDAG
&
>
(
DAG
)
.
SUnits
;
std
::
vector
<
SUnit
>
SUSavedCopy
;
SUSavedCopy
.
resize
(
SUnits
.
size
(
)
)
;
for
(
const
SUnit
&
SU
:
SUnits
)
SUSavedCopy
[
SU
.
NodeNum
]
=
SU
;
SUNumbers
.
assign
(
SUnits
.
size
(
)
,
0
)
;
for
(
const
SUnit
&
SU
:
SUnits
)
CalcNodeSethiUllmanNumber
(
&
SU
,
SUNumbers
)
;
for
(
auto
SU
:
BotRoots
)
{
AvailQueue
.
push_back
(
*
new
(
Alloc
.
Allocate
(
)
)
Candidate
(
const_cast
<
SUnit
*
>
(
SU
)
)
)
;
}
releasePredecessors
(
&
DAG
.
ExitSU
)
;
std
::
vector
<
const
SUnit
*
>
Schedule
;
Schedule
.
reserve
(
SUnits
.
size
(
)
)
;
while
(
true
)
{
if
(
AvailQueue
.
empty
(
)
&&
!
PendingQueue
.
empty
(
)
)
{
auto
EarliestSU
=
std
::
min_element
(
PendingQueue
.
begin
(
)
,
PendingQueue
.
end
(
)
,
[
=
]
(
const
Candidate
&
C1
,
const
Candidate
&
C2
)
{
return
C1
.
SU
->
getHeight
(
)
<
C2
.
SU
->
getHeight
(
)
;
}
)
->
SU
;
advanceToCycle
(
std
::
max
(
CurCycle
+
1
,
EarliestSU
->
getHeight
(
)
)
)
;
}
if
(
AvailQueue
.
empty
(
)
)
break
;
LLVM_DEBUG
(
dbgs
(
)
<<
"\n=== Picking candidate\n"
"Ready queue:"
;
for
(
auto
&
C
:
AvailQueue
)
dbgs
(
)
<<
' '
<<
C
.
SU
->
NodeNum
;
dbgs
(
)
<<
'\n'
;
)
;
auto
C
=
pickCandidate
(
)
;
assert
(
C
)
;
AvailQueue
.
remove
(
*
C
)
;
auto
SU
=
C
->
SU
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Selected "
;
DAG
.
dumpNode
(
*
SU
)
)
;
advanceToCycle
(
SU
->
getHeight
(
)
)
;
releasePredecessors
(
SU
)
;
Schedule
.
push_back
(
SU
)
;
SU
->
isScheduled
=
true
;
}
assert
(
SUnits
.
size
(
)
==
Schedule
.
size
(
)
)
;
std
::
reverse
(
Schedule
.
begin
(
)
,
Schedule
.
end
(
)
)
;
for
(
auto
&
SU
:
SUnits
)
SU
=
SUSavedCopy
[
SU
.
NodeNum
]
;
return
Schedule
;
}
</s>

Schedule - This is called back from ScheduleDAGInstrs : :Run ( ) when it 's time to do some work .

AMDGPU
0
1
"\n=== Picking candidate\n"
"Ready queue:"
"Selected "


"Only support MVT::i32 register passing"

"Can only pass arguments as either registers or via the stack"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> bool X86TargetLowering :: isUsedByReturnOnly ( SDNode * N , SDValue & Chain ) const { if ( N -> getNumValues ( ) != 1 || ! N -> hasNUsesOfValue ( 1 , 0 ) ) return false ; SDValue TCChain = Chain ; SDNode * Copy = * N -> use_begin ( ) ; if ( Copy -> getOpcode ( ) == ISD :: CopyToReg ) { if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - 1 ) . getValueType ( ) == MVT :: Glue ) return false ; TCChain = Copy -> getOperand ( 0 ) ; } else if ( Copy -> getOpcode ( ) != ISD :: FP_EXTEND ) return false ; bool HasRet = false ; for ( SDNode :: use_iterator UI = Copy -> use_begin ( ) , UE = Copy -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != X86ISD :: RET_FLAG ) return false ; if ( UI -> getNumOperands ( ) > 4 ) return false ; if ( UI -> getNumOperands ( ) == 4 && UI -> getOperand ( UI -> getNumOperands ( ) - 1 ) . getValueType ( ) != MVT :: Glue ) return false ; HasRet = true ; } if ( ! HasRet ) return false ; Chain = TCChain ; return true ; } </s>

Return true if result of the specified node is used by a return node only .


"PIC16 Does not have any frame register"


<s> static bool expand_vselect_vconcat ( rtx target , rtx op0 , rtx op1 , const unsigned char * perm , unsigned nelt ) { machine_mode v2mode ; rtx x ; v2mode = GET_MODE_2XWIDER_MODE ( GET_MODE ( op0 ) ) ; x = gen_rtx_VEC_CONCAT ( v2mode , op0 , op1 ) ; return expand_vselect ( target , x , perm , nelt ) ; } </s>

Similar , but generate a vec_concat from op0 and op1 as well .


<s>
MipsSubtarget
::
MipsSubtarget
(
const
std
::
string
&
TT
,
const
std
::
string
&
CPU
,
const
std
::
string
&
FS
,
bool
little
,
Reloc
::
Model
RM
)
:
MipsGenSubtargetInfo
(
TT
,
CPU
,
FS
)
,
MipsArchVersion
(
Mips32
)
,
MipsABI
(
UnknownABI
)
,
IsLittle
(
little
)
,
IsSingleFloat
(
false
)
,
IsFP64bit
(
false
)
,
IsGP64bit
(
false
)
,
HasVFPU
(
false
)
,
IsLinux
(
true
)
,
HasSEInReg
(
false
)
,
HasCondMov
(
false
)
,
HasSwap
(
false
)
,
HasBitCount
(
false
)
,
HasFPIdx
(
false
)
,
InMips16Mode
(
false
)
,
HasDSP
(
false
)
,
HasDSPR2
(
false
)
,
IsAndroid
(
false
)
{
std
::
string
CPUName
=
CPU
;
if
(
CPUName
.
empty
(
)
)
CPUName
=
"mips32"
;
ParseSubtargetFeatures
(
CPUName
,
FS
)
;
InstrItins
=
getInstrItineraryForCPU
(
CPUName
)
;
if
(
MipsABI
==
UnknownABI
)
MipsABI
=
hasMips64
(
)
N64
:
O32
;
assert
(
(
(
!
hasMips64
(
)
&&
(
isABI_O32
(
)
||
isABI_EABI
(
)
)
)
||
(
hasMips64
(
)
&&
(
isABI_N32
(
)
||
isABI_N64
(
)
)
)
)
&&
"Invalid  Arch & ABI pair."
)
;
if
(
TT
.
find
(
"linux"
)
==
std
::
string
::
npos
)
IsLinux
=
false
;
UseSmallSection
=
!
IsLinux
&&
(
RM
==
Reloc
::
Static
)
;
}
</s>

This constructor initializes the data members to match that of the specified triple .

Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
"mips32"
Mips
Mips
Mips
Mips
Mips
"Invalid  Arch & ABI pair."
"linux"


<s> static int rs6000_compute_pressure_classes ( enum reg_class * pressure_classes ) { int n ; n = 0 ; pressure_classes [ n ++ ] = GENERAL_REGS ; if ( TARGET_VSX ) pressure_classes [ n ++ ] = VSX_REGS ; else { if ( TARGET_ALTIVEC ) pressure_classes [ n ++ ] = ALTIVEC_REGS ; if ( TARGET_HARD_FLOAT && TARGET_FPRS ) pressure_classes [ n ++ ] = FLOAT_REGS ; } pressure_classes [ n ++ ] = CR_REGS ; pressure_classes [ n ++ ] = SPECIAL_REGS ; return n ; } </s>

Compute register pressure classes . We implement the target hook to avoid IRA picking something like GEN_OR_FLOAT_REGS as a pressure class , which can lead to incorrect estimates of number of available registers and therefor increased register pressure/spill .


<s> static bool find_nearest_reg_def ( rtx_insn * insn , int regno1 , int regno2 ) { rtx_insn * prev = insn ; rtx_insn * start = BB_HEAD ( BLOCK_FOR_INSN ( insn ) ) ; if ( insn == start ) return false ; while ( prev && prev != start ) { if ( ! INSN_P ( prev ) || ! NONDEBUG_INSN_P ( prev ) ) { prev = PREV_INSN ( prev ) ; continue ; } if ( insn_defines_reg ( regno1 , INVALID_REGNUM , prev ) ) return true ; else if ( insn_defines_reg ( regno2 , INVALID_REGNUM , prev ) ) return false ; prev = PREV_INSN ( prev ) ; } return false ; } </s>

Return true if regno1 def is nearest to the insn .


<s> bool isBarrier ( ) const { return Kind == k_Barrier && ! getBarriernXSModifier ( ) ; } </s>

Tests if this is an Order dependence that is marked as a barrier .


<s> const char * GBZ80TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return NULL ; case GBZ80ISD :: WRAPPER : return "GBZ80ISD::WRAPPER" ; case GBZ80ISD :: SCF : return "GBZ80ISD::SCF" ; case GBZ80ISD :: CCF : return "GBZ80ISD::CCF" ; case GBZ80ISD :: RLC : return "GBZ80ISD::RLC" ; case GBZ80ISD :: RRC : return "GBZ80ISD::RRC" ; case GBZ80ISD :: RL : return "GBZ80ISD::RL" ; case GBZ80ISD :: RR : return "GBZ80ISD::RR" ; case GBZ80ISD :: SLA : return "GBZ80ISD::SLA" ; case GBZ80ISD :: SRA : return "GBZ80ISD::SRA" ; case GBZ80ISD :: SLL : return "GBZ80ISD::SLL" ; case GBZ80ISD :: SRL : return "GBZ80ISD::SRL" ; case GBZ80ISD :: SHL : return "GBZ80ISD::SHL" ; case GBZ80ISD :: LSHR : return "GBZ80ISD::LSHR" ; case GBZ80ISD :: ASHR : return "GBZ80ISD::ASHR" ; case GBZ80ISD :: CP : return "GBZ80ISD::CP" ; case GBZ80ISD :: SELECT_CC : return "GBZ80ISD::SELECT_CC" ; case GBZ80ISD :: BR_CC : return "GBZ80ISD::BR_CC" ; case GBZ80ISD :: CALL : return "GBZ80ISD::CALL" ; case GBZ80ISD :: RET : return "GBZ80ISD::RET" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> void tilepro_emit_conditional_branch ( rtx operands [ ] , machine_mode cmp_mode ) { rtx cmp_rtx = tilepro_emit_cc_test ( GET_CODE ( operands [ 0 ] ) , operands [ 1 ] , operands [ 2 ] , cmp_mode , false ) ; rtx branch_rtx = gen_rtx_SET ( pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , cmp_rtx , gen_rtx_LABEL_REF ( VOIDmode , operands [ 3 ] ) , pc_rtx ) ) ; emit_jump_insn ( branch_rtx ) ; } </s>

Generate the comparison for a conditional branch .