<s>
MCSymbol
*
Z80MCInstLower
::
GetExternalSymbolSymbol
(
const
MachineOperand
&
MO
)
const
{
if
(
MO
.
getTargetFlags
(
)
!=
0
)
llvm_unreachable
(
"Unknown target flag on GV operand"
)
;
return
AsmPrinter
.
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
;
}
</s>

Return the MCSymbol for the specified ExternalSymbol .


<s>
MachineBasicBlock
*
CAHPTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
const
TargetInstrInfo
&
TII
=
*
BB
->
getParent
(
)
->
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
=
MI
.
getDebugLoc
(
)
;
assert
(
MI
.
getOpcode
(
)
==
CAHP
::
Select_GPR_Using_CC_GPR
&&
"Unexpected instr type to insert"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
I
=
++
BB
->
getIterator
(
)
;
MachineBasicBlock
*
HeadMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
TailMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
IfFalseMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
F
->
insert
(
I
,
IfFalseMBB
)
;
F
->
insert
(
I
,
TailMBB
)
;
TailMBB
->
splice
(
TailMBB
->
begin
(
)
,
HeadMBB
,
std
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
HeadMBB
->
end
(
)
)
;
TailMBB
->
transferSuccessorsAndUpdatePHIs
(
HeadMBB
)
;
HeadMBB
->
addSuccessor
(
IfFalseMBB
)
;
HeadMBB
->
addSuccessor
(
TailMBB
)
;
unsigned
LHS
=
MI
.
getOperand
(
1
)
.
getReg
(
)
;
unsigned
RHS
=
MI
.
getOperand
(
2
)
.
getReg
(
)
;
auto
CC
=
static_cast
<
ISD
::
CondCode
>
(
MI
.
getOperand
(
3
)
.
getImm
(
)
)
;
unsigned
Opcode
=
getBranchOpcodeForIntCondCode
(
CC
)
;
BuildMI
(
HeadMBB
,
DL
,
TII
.
get
(
Opcode
)
)
.
addReg
(
LHS
)
.
addReg
(
RHS
)
.
addMBB
(
TailMBB
)
;
IfFalseMBB
->
addSuccessor
(
TailMBB
)
;
BuildMI
(
*
TailMBB
,
TailMBB
->
begin
(
)
,
DL
,
TII
.
get
(
CAHP
::
PHI
)
,
MI
.
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
.
getOperand
(
4
)
.
getReg
(
)
)
.
addMBB
(
HeadMBB
)
.
addReg
(
MI
.
getOperand
(
5
)
.
getReg
(
)
)
.
addMBB
(
IfFalseMBB
)
;
MI
.
eraseFromParent
(
)
;
return
TailMBB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s>
void
dump
(
raw_ostream
&
os
,
unsigned
indent
)
const
{
printID
(
os
.
indent
(
indent
)
)
<<
":\n"
;
os
.
indent
(
indent
+
2
)
<<
"Definitions:{"
;
for
(
auto
def
:
Definitions
)
{
os
<<
"("
<<
def
.
predicate
<<
", "
<<
def
.
guard
<<
", "
<<
def
.
useBlock
<<
"), "
;
}
os
<<
"}\n"
;
os
.
indent
(
indent
+
2
)
<<
"ExitTargets:{"
;
for
(
auto
t
:
ExitTargets
)
{
os
<<
t
<<
", "
;
}
os
<<
"}\n"
;
os
.
indent
(
indent
+
2
)
<<
"Successors:{"
;
for
(
auto
t
:
Successors
)
{
os
<<
"("
<<
t
.
first
<<
", "
<<
t
.
second
<<
"), "
;
}
os
<<
"}\n"
;
os
.
indent
(
indent
+
2
)
<<
"Remnants:{"
;
for
(
auto
t
:
Remnants
)
{
os
<<
t
<<
", "
;
}
os
<<
"}\n"
;
printInstructions
(
os
,
indent
+
2
)
;
}
</s>

Dump the plan to stderr ( for debugging ) .


<s> static void rl78_alloc_physical_registers_umul ( rtx_insn * insn ) { rtx_insn * prev = prev_nonnote_nondebug_insn ( insn ) ; rtx first ; int tmp_id ; rtx saved_op1 ; OP ( 0 ) = transcode_memory_rtx ( OP ( 0 ) , BC , insn ) ; OP ( 1 ) = transcode_memory_rtx ( OP ( 1 ) , DE , insn ) ; OP ( 2 ) = transcode_memory_rtx ( OP ( 2 ) , HL , insn ) ; MAYBE_OK ( insn ) ; if ( recog_data . constraints [ 1 ] [ 0 ] == '%' && is_virtual_register ( OP ( 1 ) ) && ! is_virtual_register ( OP ( 2 ) ) && ! CONSTANT_P ( OP ( 2 ) ) ) { rtx tmp = OP ( 1 ) ; OP ( 1 ) = OP ( 2 ) ; OP ( 2 ) = tmp ; } OP ( 0 ) = move_from_acc ( 0 , insn ) ; tmp_id = get_max_insn_count ( ) ; saved_op1 = OP ( 1 ) ; if ( rtx_equal_p ( OP ( 1 ) , OP ( 2 ) ) ) { gcc_assert ( GET_MODE ( OP ( 2 ) ) == QImode ) ; OP ( 2 ) = move_to_x ( 2 , insn ) ; OP ( 1 ) = A ; } else OP ( 1 ) = move_to_acc ( 1 , insn ) ; MAYBE_OK ( insn ) ; if ( tmp_id == get_max_insn_count ( ) ) force_into_acc ( saved_op1 , insn ) ; if ( prev ) first = next_nonnote_nondebug_insn ( prev ) ; else for ( first = insn ; prev_nonnote_nondebug_insn ( first ) ; first = prev_nonnote_nondebug_insn ( first ) ) ; OP ( 2 ) = move_to_x ( 2 , first ) ; MUST_BE_OK ( insn ) ; } </s>


<s> const uint16_t * HSAILRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { 0 } ; return CalleeSavedRegs ; } </s>


<s> const MCPhysReg * Nios2RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_SaveList ; } </s>


<s> bool ir_p ( rtx op ) { if ( GET_CODE ( op ) != MEM ) return false ; return ( REG_P ( XEXP ( op , 0 ) ) && z8k_reg_ok_for_base_p ( XEXP ( op , 0 ) ) ) || ( reload_in_progress && GET_CODE ( XEXP ( op , 0 ) ) == REG && REGNO ( op ) >= FIRST_PSEUDO_REGISTER ) ; } </s>

Also accept ( MEM ( pseudo ) ) here during reload , because the pseudo is guaranteed to be reloaded into a PTR reg .


<s> bool X86CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto DL = MIRBuilder . getMF ( ) . getDataLayout ( ) ; SmallVector < ArgInfo , 8 > ArgInfos ; unsigned Idx = 0 ; for ( auto & Arg : F . getArgumentList ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + 1 , DL , F ) ; ArgInfos . push_back ( AInfo ) ; Idx ++ ; } FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , CC_X86 , DL ) ; return handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> bool arc_raw_symbolic_reference_mentioned_p ( rtx op , bool skip_local ) { register const char * fmt ; register int i ; if ( GET_CODE ( op ) == UNSPEC ) return false ; if ( GET_CODE ( op ) == SYMBOL_REF ) { tree decl = SYMBOL_REF_DECL ( op ) ; return ! skip_local || ! decl || ! default_binds_local_p ( decl ) ; } fmt = GET_RTX_FORMAT ( GET_CODE ( op ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( op ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { register int j ; for ( j = XVECLEN ( op , i ) - 1 ; j >= 0 ; j -- ) if ( arc_raw_symbolic_reference_mentioned_p ( XVECEXP ( op , i , j ) , skip_local ) ) return true ; } else if ( fmt [ i ] == 'e' && arc_raw_symbolic_reference_mentioned_p ( XEXP ( op , i ) , skip_local ) ) return true ; } return false ; } </s>

Return true if OP contains a SYMBOL_REF that is not wrapped in an unspec . If SKIP_LOCAL is true , skip symbols that bind locally . This is used further down in this file , and , without SKIP_LOCAL , in the addsi3 / subsi3 expanders when generating PIC code .


<s> void ix86_expand_sse2_abs ( rtx target , rtx input ) { machine_mode mode = GET_MODE ( target ) ; rtx tmp0 , tmp1 , x ; switch ( mode ) { case E_V4SImode : tmp0 = expand_simple_binop ( mode , ASHIFTRT , input , GEN_INT ( GET_MODE_UNIT_BITSIZE ( mode ) - 1 ) , NULL , 0 , OPTAB_DIRECT ) ; tmp1 = expand_simple_binop ( mode , XOR , tmp0 , input , NULL , 0 , OPTAB_DIRECT ) ; x = expand_simple_binop ( mode , MINUS , tmp1 , tmp0 , target , 0 , OPTAB_DIRECT ) ; break ; case E_V8HImode : tmp0 = expand_unop ( mode , neg_optab , input , NULL_RTX , 0 ) ; x = expand_simple_binop ( mode , SMAX , tmp0 , input , target , 0 , OPTAB_DIRECT ) ; break ; case E_V16QImode : tmp0 = expand_unop ( mode , neg_optab , input , NULL_RTX , 0 ) ; x = expand_simple_binop ( V16QImode , UMIN , tmp0 , input , target , 0 , OPTAB_DIRECT ) ; break ; default : gcc_unreachable ( ) ; } if ( x != target ) emit_move_insn ( target , x ) ; } </s>

Calculate integer abs ( ) using only SSE2 instructions .


".L__stack_usage = %d + __gcc_isr.n_pushed\n"

Output summary at end of function prologue .


<s>
void
rs6000_xcoff_declare_function_name
(
FILE
*
file
,
const
char
*
name
,
tree
decl
)
{
char
*
buffer
=
(
char
*
)
alloca
(
strlen
(
name
)
+
1
)
;
char
*
p
;
int
dollar_inside
=
0
;
struct
declare_alias_data
data
=
{
file
,
false
}
;
strcpy
(
buffer
,
name
)
;
p
=
strchr
(
buffer
,
'$'
)
;
while
(
p
)
{
*
p
=
'_'
;
dollar_inside
++
;
p
=
strchr
(
p
+
1
,
'$'
)
;
}
if
(
TREE_PUBLIC
(
decl
)
)
{
if
(
!
RS6000_WEAK
||
!
DECL_WEAK
(
decl
)
)
{
if
(
dollar_inside
)
{
fprintf
(
file
,
"\t.rename .%s,\".%s\"\n"
,
buffer
,
name
)
;
fprintf
(
file
,
"\t.rename %s,\"%s\"\n"
,
buffer
,
name
)
;
}
fputs
(
"\t.globl ."
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
fputs
(
rs6000_xcoff_visibility
(
decl
)
,
file
)
;
putc
(
'\n'
,
file
)
;
}
}
else
{
if
(
dollar_inside
)
{
fprintf
(
file
,
"\t.rename .%s,\".%s\"\n"
,
buffer
,
name
)
;
fprintf
(
file
,
"\t.rename %s,\"%s\"\n"
,
buffer
,
name
)
;
}
fputs
(
"\t.lglobl ."
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
putc
(
'\n'
,
file
)
;
}
fputs
(
"\t.csect "
,
file
)
;
assemble_name
(
file
,
buffer
)
;
fputs
(
TARGET_32BIT
"\n"
:
",3\n"
,
file
)
;
ASM_OUTPUT_LABEL
(
file
,
buffer
)
;
symtab_node
::
get
(
decl
)
->
call_for_symbol_and_aliases
(
rs6000_declare_alias
,
&
data
,
true
)
;
fputs
(
TARGET_32BIT
"\t.long ."
:
"\t.llong ."
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
fputs
(
", TOC[tc0], 0\n"
,
file
)
;
in_section
=
;
switch_to_section
(
function_section
(
decl
)
)
;
putc
(
'.'
,
file
)
;
ASM_OUTPUT_LABEL
(
file
,
buffer
)
;
data
.
function_descriptor
=
true
;
symtab_node
::
get
(
decl
)
->
call_for_symbol_and_aliases
(
rs6000_declare_alias
,
&
data
,
true
)
;
if
(
!
DECL_IGNORED_P
(
decl
)
)
{
if
(
dwarf_debuginfo_p
(
)
)
{
name
=
(
*
targetm
.
strip_name_encoding
)
(
name
)
;
fprintf
(
file
,
"\t.function .%s,.%s,2,0\n"
,
name
,
name
)
;
}
}
return
;
}
</s>

This macro produces the initial definition of a function name . On the RS/6000 , we need to place an extra ' . ' in the function name and output the function descriptor . Dollar signs are converted to underscores . The csect for the function will have already been created when text_section was selected . We do have to go back to that csect , however . The third and fourth parameters to the .function pseudo-op ( 16 and 044 ) are placeholders which no longer have any use . Because AIX assembler 's .set command has unexpected semantics , we output all aliases as alternative labels in front of the definition .


<s> static int ix86_multiplication_cost ( const struct processor_costs * cost , enum machine_mode mode ) { machine_mode inner_mode = mode ; if ( VECTOR_MODE_P ( mode ) ) inner_mode = GET_MODE_INNER ( mode ) ; if ( SSE_FLOAT_MODE_SSEMATH_OR_HF_P ( mode ) ) return inner_mode == DFmode ? cost -> mulsd : cost -> mulss ; else if ( X87_FLOAT_MODE_P ( mode ) ) return cost -> fmul ; else if ( FLOAT_MODE_P ( mode ) ) return ix86_vec_cost ( mode , inner_mode == DFmode ? cost -> mulsd : cost -> mulss ) ; else if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) { if ( TARGET_AVX512DQ ) return ix86_vec_cost ( mode , cost -> mulss ) ; if ( mode == V16QImode || mode == V32QImode ) { int extra = 11 ; if ( TARGET_XOP && mode == V16QImode ) extra = 5 ; else if ( TARGET_SSSE3 ) extra = 6 ; return ix86_vec_cost ( mode , cost -> mulss * 2 + cost -> sse_op * extra ) ; } else if ( mode == V2DImode || mode == V4DImode ) { if ( TARGET_XOP && mode == V2DImode ) return ix86_vec_cost ( mode , cost -> mulss * 2 + cost -> sse_op * 3 ) ; else return ix86_vec_cost ( mode , cost -> mulss * 3 + cost -> sse_op * 5 ) ; } else if ( mode == V4SImode && ! ( TARGET_SSE4_1 || TARGET_AVX ) ) return ix86_vec_cost ( mode , cost -> mulss * 2 + cost -> sse_op * 5 ) ; else return ix86_vec_cost ( mode , cost -> mulss ) ; } else return ( cost -> mult_init [ MODE_INDEX ( mode ) ] + cost -> mult_bit * 7 ) ; } </s>


<s> static void expand_interrupt_handler_epilogue ( rtx spreg , e_funkind fkind ) { int i ; rtx postinc1 = gen_rtx_POST_INC ( SImode , spreg ) ; rtx postinc = gen_rtx_MEM ( SImode , postinc1 ) ; tree attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ; bool all = lookup_attribute ( "saveall" , attrs ) != NULL_TREE ; MEM_VOLATILE_P ( postinc ) = 1 ; do_unlink ( spreg , get_frame_size ( ) , all ) ; if ( lookup_attribute ( "nesting" , attrs ) ) { rtx srcreg = gen_rtx_REG ( Pmode , ( fkind == EXCPT_HANDLER ? REG_RETX : fkind == NMI_HANDLER ? REG_RETN : REG_RETI ) ) ; emit_move_insn ( srcreg , postinc ) ; } if ( ! current_function_is_leaf ) all = true ; for ( i = REG_CC - 1 ; i > REG_P7 ; i -- ) if ( all || regs_ever_live [ i ] || ( ! leaf_function_p ( ) && call_used_regs [ i ] ) ) { if ( i == REG_A0 || i == REG_A1 ) { rtx mem = gen_rtx_MEM ( PDImode , postinc1 ) ; MEM_VOLATILE_P ( mem ) = 1 ; emit_move_insn ( gen_rtx_REG ( PDImode , i ) , mem ) ; } else emit_move_insn ( gen_rtx_REG ( SImode , i ) , postinc ) ; } expand_epilogue_reg_restore ( spreg , all , true ) ; emit_move_insn ( gen_rtx_REG ( SImode , REG_ASTAT ) , postinc ) ; if ( fkind == EXCPT_HANDLER ) emit_insn ( gen_addsi3 ( spreg , spreg , GEN_INT ( 12 ) ) ) ; emit_jump_insn ( gen_return_internal ( GEN_INT ( fkind ) ) ) ; } </s>

Generate an epilogue suitable for a function of kind FKIND . This is called for interrupt and exception handler epilogues . SPREG contains ( reg : SI REG_SP ) .


<s> bool X86TargetLowering :: isFsqrtCheap ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; if ( VT . getScalarType ( ) == MVT :: f16 ) return true ; if ( DAG . doesNodeExist ( X86ISD :: FRSQRT , DAG . getVTList ( VT ) , Op ) ) return false ; if ( VT . isVector ( ) ) return Subtarget . hasFastVectorFSQRT ( ) ; return Subtarget . hasFastScalarFSQRT ( ) ; } </s>

Return true if SQRT ( X ) should n't be replaced with X * RSQRT ( X ) .


<s> SDValue AArch64TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: AND : return PerformANDCombine ( N , DCI ) ; case ISD :: OR : return PerformORCombine ( N , DCI , getSubtarget ( ) ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DCI , getSubtarget ( ) ) ; case ISD :: INTRINSIC_WO_CHAIN : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case AArch64ISD :: NEON_VDUPLANE : return CombineVLDDUP ( N , DCI ) ; case AArch64ISD :: NEON_LD2DUP : case AArch64ISD :: NEON_LD3DUP : case AArch64ISD :: NEON_LD4DUP : return CombineBaseUpdate ( N , DCI ) ; case ISD :: INTRINSIC_VOID : case ISD :: INTRINSIC_W_CHAIN : switch ( cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) -> getZExtValue ( ) ) { case Intrinsic :: arm_neon_vld1 : case Intrinsic :: arm_neon_vld2 : case Intrinsic :: arm_neon_vld3 : case Intrinsic :: arm_neon_vld4 : case Intrinsic :: arm_neon_vst1 : case Intrinsic :: arm_neon_vst2 : case Intrinsic :: arm_neon_vst3 : case Intrinsic :: arm_neon_vst4 : case Intrinsic :: arm_neon_vld2lane : case Intrinsic :: arm_neon_vld3lane : case Intrinsic :: arm_neon_vld4lane : case Intrinsic :: aarch64_neon_vld1x2 : case Intrinsic :: aarch64_neon_vld1x3 : case Intrinsic :: aarch64_neon_vld1x4 : case Intrinsic :: aarch64_neon_vst1x2 : case Intrinsic :: aarch64_neon_vst1x3 : case Intrinsic :: aarch64_neon_vst1x4 : case Intrinsic :: arm_neon_vst2lane : case Intrinsic :: arm_neon_vst3lane : case Intrinsic :: arm_neon_vst4lane : return CombineBaseUpdate ( N , DCI ) ; default : break ; } } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> unsigned ARMBaseInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { const MachineBasicBlock & MBB = * MI . getParent ( ) ; const MachineFunction * MF = MBB . getParent ( ) ; const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ; const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( MCID . getSize ( ) ) return MCID . getSize ( ) ; if ( MI . getOpcode ( ) == ARM :: INLINEASM ) return getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * MAI ) ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { default : return 0 ; case TargetOpcode :: BUNDLE : return getInstBundleLength ( MI ) ; case ARM :: MOVi16_ga_pcrel : case ARM :: MOVTi16_ga_pcrel : case ARM :: t2MOVi16_ga_pcrel : case ARM :: t2MOVTi16_ga_pcrel : return 4 ; case ARM :: MOVi32imm : case ARM :: t2MOVi32imm : return 8 ; case ARM :: CONSTPOOL_ENTRY : case ARM :: JUMPTABLE_INSTS : case ARM :: JUMPTABLE_ADDRS : case ARM :: JUMPTABLE_TBB : case ARM :: JUMPTABLE_TBH : return MI . getOperand ( 2 ) . getImm ( ) ; case ARM :: Int_eh_sjlj_longjmp : return 16 ; case ARM :: tInt_eh_sjlj_longjmp : return 10 ; case ARM :: tInt_WIN_eh_sjlj_longjmp : return 12 ; case ARM :: Int_eh_sjlj_setjmp : case ARM :: Int_eh_sjlj_setjmp_nofp : return 20 ; case ARM :: tInt_eh_sjlj_setjmp : case ARM :: t2Int_eh_sjlj_setjmp : case ARM :: t2Int_eh_sjlj_setjmp_nofp : return 12 ; case ARM :: SPACE : return MI . getOperand ( 1 ) . getImm ( ) ; } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> int m32c_prepare_move ( rtx * operands , machine_mode mode ) { if ( far_addr_space_p ( operands [ 0 ] ) && CONSTANT_P ( operands [ 1 ] ) ) { operands [ 1 ] = force_reg ( GET_MODE ( operands [ 0 ] ) , operands [ 1 ] ) ; } if ( TARGET_A16 && mode == PSImode ) return m32c_split_move ( operands , mode , 1 ) ; if ( ( GET_CODE ( operands [ 0 ] ) == MEM ) && ( GET_CODE ( XEXP ( operands [ 0 ] , 0 ) ) == PRE_MODIFY ) ) { rtx pmv = XEXP ( operands [ 0 ] , 0 ) ; rtx dest_reg = XEXP ( pmv , 0 ) ; rtx dest_mod = XEXP ( pmv , 1 ) ; emit_insn ( gen_rtx_SET ( dest_reg , dest_mod ) ) ; operands [ 0 ] = gen_rtx_MEM ( mode , dest_reg ) ; } if ( can_create_pseudo_p ( ) && MEM_P ( operands [ 0 ] ) && MEM_P ( operands [ 1 ] ) ) operands [ 1 ] = copy_to_mode_reg ( mode , operands [ 1 ] ) ; return 0 ; } </s>

Used to emit move instructions . We split some moves , and avoid mem-mem moves .


<s> bool isFPVectorizationPotentiallyUnsafe ( ) { return ! ST -> isTargetDarwin ( ) && ! ST -> hasMVEFloatOps ( ) ; } </s>

Indicate that it is potentially unsafe to automatically vectorize floating-point operations because the semantics of vector and scalar floating-point semantics may differ .


<s> RegisterAggr & RegisterAggr :: insert ( const RegisterAggr & RG ) { for ( std :: pair < RegisterId , LaneBitmask > P : RG . Masks ) insert ( RegisterRef ( P . first , P . second ) ) ; return * this ; } </s>

insert - Append entry to the vector if it does n't already exist .


<s> uint64_t BPFAbstractMemberAccess :: getConstant ( const Value * IndexValue ) { const ConstantInt * CV = dyn_cast < ConstantInt > ( IndexValue ) ; assert ( CV ) ; return CV -> getValue ( ) . getZExtValue ( ) ; } </s>

Return the large constant at the given index .


<s>
bool
SIInstrInfo
::
isInlineConstant
(
const
MachineOperand
&
MO
,
uint8_t
OperandType
)
const
{
if
(
!
MO
.
isImm
(
)
||
OperandType
<
AMDGPU
::
OPERAND_SRC_FIRST
||
OperandType
>
AMDGPU
::
OPERAND_SRC_LAST
)
return
false
;
int64_t
Imm
=
MO
.
getImm
(
)
;
switch
(
OperandType
)
{
case
AMDGPU
::
OPERAND_REG_IMM_INT32
:
case
AMDGPU
::
OPERAND_REG_IMM_FP32
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_INT32
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_FP32
:
case
AMDGPU
::
OPERAND_REG_INLINE_AC_INT32
:
case
AMDGPU
::
OPERAND_REG_INLINE_AC_FP32
:
{
int32_t
Trunc
=
static_cast
<
int32_t
>
(
Imm
)
;
return
AMDGPU
::
isInlinableLiteral32
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
case
AMDGPU
::
OPERAND_REG_IMM_INT64
:
case
AMDGPU
::
OPERAND_REG_IMM_FP64
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_INT64
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_FP64
:
return
AMDGPU
::
isInlinableLiteral64
(
MO
.
getImm
(
)
,
ST
.
hasInv2PiInlineImm
(
)
)
;
case
AMDGPU
::
OPERAND_REG_IMM_INT16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_INT16
:
case
AMDGPU
::
OPERAND_REG_INLINE_AC_INT16
:
return
AMDGPU
::
isInlinableIntLiteral
(
Imm
)
;
case
AMDGPU
::
OPERAND_REG_IMM_V2INT16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_V2INT16
:
case
AMDGPU
::
OPERAND_REG_INLINE_AC_V2INT16
:
return
AMDGPU
::
isInlinableIntLiteralV216
(
Imm
)
;
case
AMDGPU
::
OPERAND_REG_IMM_FP16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_FP16
:
case
AMDGPU
::
OPERAND_REG_INLINE_AC_FP16
:
{
if
(
isInt
<
16
>
(
Imm
)
||
isUInt
<
16
>
(
Imm
)
)
{
int16_t
Trunc
=
static_cast
<
int16_t
>
(
Imm
)
;
return
ST
.
has16BitInsts
(
)
&&
AMDGPU
::
isInlinableLiteral16
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
return
false
;
}
case
AMDGPU
::
OPERAND_REG_IMM_V2FP16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_V2FP16
:
case
AMDGPU
::
OPERAND_REG_INLINE_AC_V2FP16
:
{
uint32_t
Trunc
=
static_cast
<
uint32_t
>
(
Imm
)
;
return
AMDGPU
::
isInlinableLiteralV216
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
default
:
llvm_unreachable
(
"invalid bitwidth"
)
;
}
}
</s>

returns true if the operand OpIdx in MI is a valid inline immediate .


<s> void ConvergingVLIWScheduler :: releaseTopNode ( SUnit * SU ) { if ( SU -> isScheduled ) return ; for ( SUnit :: succ_iterator I = SU -> Preds . begin ( ) , E = SU -> Preds . end ( ) ; I != E ; ++ I ) { unsigned PredReadyCycle = I -> getSUnit ( ) -> TopReadyCycle ; unsigned MinLatency = I -> getMinLatency ( ) ; Top . MaxMinLatency = std :: max ( MinLatency , Top . MaxMinLatency ) ; if ( SU -> TopReadyCycle < PredReadyCycle + MinLatency ) SU -> TopReadyCycle = PredReadyCycle + MinLatency ; } Top . releaseNode ( SU , SU -> TopReadyCycle ) ; } </s>

SU has had all predecessor dependencies resolved .


<s> static void ix86_simd_clone_adjust ( struct cgraph_node * node ) { const char * str = NULL ; gcc_assert ( node -> decl == cfun -> decl ) ; switch ( node -> simdclone -> vecsize_mangle ) { case 'b' : if ( ! TARGET_SSE2 ) str = "sse2" ; break ; case 'c' : if ( ! TARGET_AVX ) str = "avx" ; break ; case 'd' : if ( ! TARGET_AVX2 ) str = "avx2" ; break ; case 'e' : if ( ! TARGET_AVX512F ) str = "avx512f" ; break ; default : gcc_unreachable ( ) ; } if ( str == NULL ) return ; push_cfun ( NULL ) ; tree args = build_tree_list ( NULL_TREE , build_string ( strlen ( str ) , str ) ) ; bool ok = ix86_valid_target_attribute_p ( node -> decl , NULL , args , 0 ) ; gcc_assert ( ok ) ; pop_cfun ( ) ; ix86_reset_previous_fndecl ( ) ; ix86_set_current_function ( node -> decl ) ; } </s>

Add target attribute to SIMD clone NODE if needed .


<s>
void
HSAILMCInstLower
::
lower
(
const
MachineInstr
*
MI
,
MCInst
&
OutMI
)
const
{
OutMI
.
setOpcode
(
MI
->
getOpcode
(
)
)
;
for
(
const
MachineOperand
&
MO
:
MI
->
explicit_operands
(
)
)
{
MCOperand
MCOp
;
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_FPImmediate
:
{
const
APFloat
&
FloatValue
=
MO
.
getFPImm
(
)
->
getValueAPF
(
)
;
if
(
&
FloatValue
.
getSemantics
(
)
==
&
APFloat
::
IEEEsingle
)
MCOp
=
MCOperand
::
createFPImm
(
FloatValue
.
convertToFloat
(
)
)
;
else
if
(
&
FloatValue
.
getSemantics
(
)
==
&
APFloat
::
IEEEdouble
)
MCOp
=
MCOperand
::
createFPImm
(
FloatValue
.
convertToDouble
(
)
)
;
else
llvm_unreachable
(
"Unhandled floating point type"
)
;
break
;
}
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
createImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_Register
:
MCOp
=
MCOperand
::
createReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
createExpr
(
MCSymbolRefExpr
::
create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
Ctx
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
SmallString
<
256
>
Name
;
AP
.
getHSAILMangledName
(
Name
,
GV
)
;
MCSymbol
*
Sym
=
Ctx
.
getOrCreateSymbol
(
Name
)
;
MCOp
=
MCOperand
::
createExpr
(
MCSymbolRefExpr
::
create
(
Sym
,
Ctx
)
)
;
break
;
}
case
MachineOperand
::
MO_ExternalSymbol
:
{
MCSymbol
*
Sym
=
Ctx
.
getOrCreateSymbol
(
Twine
(
'%'
)
+
MO
.
getSymbolName
(
)
)
;
MCOp
=
MCOperand
::
createExpr
(
MCSymbolRefExpr
::
create
(
Sym
,
Ctx
)
)
;
break
;
}
case
MachineOperand
::
MO_MCSymbol
:
{
MCSymbol
*
Sym
=
MO
.
getMCSymbol
(
)
;
MCOp
=
MCOperand
::
createExpr
(
MCSymbolRefExpr
::
create
(
Sym
,
Ctx
)
)
;
break
;
}
case
MachineOperand
::
MO_TargetIndex
:
{
llvm_unreachable
(
"Don't know how to lower target index"
)
;
break
;
}
}
OutMI
.
addOperand
(
MCOp
)
;
}
}
</s>

HSAIL
HSAIL
"unknown operand type"
"Unhandled floating point type"
256
HSAIL
"Don't know how to lower target index"


<s> static void ix86_init_large_pic_reg ( unsigned int tmp_regno ) { rtx_code_label * label ; rtx tmp_reg ; gcc_assert ( Pmode == DImode ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; LABEL_PRESERVE_P ( label ) = 1 ; tmp_reg = gen_rtx_REG ( Pmode , tmp_regno ) ; gcc_assert ( REGNO ( pic_offset_table_rtx ) != tmp_regno ) ; emit_insn ( gen_set_rip_rex64 ( pic_offset_table_rtx , label ) ) ; emit_insn ( gen_set_got_offset_rex64 ( tmp_reg , label ) ) ; emit_insn ( ix86_gen_add3 ( pic_offset_table_rtx , pic_offset_table_rtx , tmp_reg ) ) ; } </s>


<s> void PTXMCAsmStreamer :: Finish ( ) { } </s>

Finish - Do final processing and write the object to the output stream .


<s> static void emit_unlikely_jump ( rtx cond , rtx label ) { rtx x = gen_rtx_IF_THEN_ELSE ( VOIDmode , cond , label , pc_rtx ) ; rtx_insn * insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , x ) ) ; add_reg_br_prob_note ( insn , profile_probability :: very_unlikely ( ) ) ; } </s>

Mark the previous jump instruction as unlikely .


"Frame indices can only appear as a debug operand in a DBG_VALUE*"

runOnMachineFunction - Emit the function body .


<s> rtx alpha_legitimize_reload_address ( rtx x , machine_mode mode ATTRIBUTE_UNUSED , int opnum , int type , int ind_levels ATTRIBUTE_UNUSED ) { if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && REG_P ( XEXP ( XEXP ( x , 0 ) , 0 ) ) && CONST_INT_P ( XEXP ( XEXP ( x , 0 ) , 1 ) ) && CONST_INT_P ( XEXP ( x , 1 ) ) ) { push_reload ( XEXP ( x , 0 ) , NULL_RTX , & XEXP ( x , 0 ) , NULL , BASE_REG_CLASS , GET_MODE ( x ) , VOIDmode , 0 , 0 , opnum , ( enum reload_type ) type ) ; return x ; } if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , 0 ) ) && REGNO ( XEXP ( x , 0 ) ) < FIRST_PSEUDO_REGISTER && REGNO_OK_FOR_BASE_P ( REGNO ( XEXP ( x , 0 ) ) ) && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) { HOST_WIDE_INT val = INTVAL ( XEXP ( x , 1 ) ) ; HOST_WIDE_INT low = ( ( val & 0xffff ) ^ 0x8000 ) - 0x8000 ; HOST_WIDE_INT high = ( ( ( val - low ) & 0xffffffff ) ^ 0x80000000 ) - 0x80000000 ; if ( high + low != val ) return NULL_RTX ; x = gen_rtx_PLUS ( GET_MODE ( x ) , gen_rtx_PLUS ( GET_MODE ( x ) , XEXP ( x , 0 ) , GEN_INT ( high ) ) , GEN_INT ( low ) ) ; push_reload ( XEXP ( x , 0 ) , NULL_RTX , & XEXP ( x , 0 ) , NULL , BASE_REG_CLASS , GET_MODE ( x ) , VOIDmode , 0 , 0 , opnum , ( enum reload_type ) type ) ; return x ; } return NULL_RTX ; } </s>

Try a machine-dependent way of reloading an illegitimate address operand . If we find one , push the reload and return the new rtx .


<s> static bool mips_symbol_binds_local_p ( const_rtx x ) { return ( SYMBOL_REF_DECL ( x ) ? targetm . binds_local_p ( SYMBOL_REF_DECL ( x ) ) : SYMBOL_REF_LOCAL_P ( x ) ) ; } </s>

Return true if SYMBOL_REF X binds locally .


<s> void VideoCore4FrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned alignment = MF . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; unsigned SLsize = MFI -> getStackSize ( ) ; unsigned Asize = MFI -> getMaxCallFrameSize ( ) ; if ( MFI -> hasVarSizedObjects ( ) ) Asize = RoundUpToAlignment ( Asize , alignment ) ; MFI -> setMaxCallFrameSize ( Asize ) ; unsigned SLAsize = SLsize + Asize ; SLAsize = RoundUpToAlignment ( SLAsize , alignment ) ; MFI -> setStackSize ( SLAsize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s> unsigned char M68kSubtarget :: classifyGlobalFunctionReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return M68kII :: MO_NO_FLAG ; auto * F = dyn_cast_or_null < Function > ( GV ) ; if ( F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) ) { return M68kII :: MO_GOTPCREL ; } return M68kII :: MO_PLT ; } </s>

Classify a global function reference for the current subtarget .


<s> bool SystemZInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { switch ( MI -> getOpcode ( ) ) { case SystemZ :: L128 : splitMove ( MI , SystemZ :: LG ) ; return true ; case SystemZ :: ST128 : splitMove ( MI , SystemZ :: STG ) ; return true ; case SystemZ :: LX : splitMove ( MI , SystemZ :: LD ) ; return true ; case SystemZ :: STX : splitMove ( MI , SystemZ :: STD ) ; return true ; case SystemZ :: ADJDYNALLOC : splitAdjDynAlloc ( MI ) ; return true ; default : return false ; } } </s>

This function is called for all pseudo instructions that remain after register allocation .

SystemZ SystemZ SystemZ::L128 SystemZ::LG SystemZ::ST128 SystemZ::STG SystemZ::LX SystemZ::LD SystemZ::STX SystemZ::STD SystemZ::ADJDYNALLOC


<s> static void workaround_arc_anomaly ( void ) { rtx_insn * insn , * succ0 ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { succ0 = next_real_insn ( insn ) ; if ( arc_hazard ( insn , succ0 ) ) { emit_insn_before ( gen_nopv ( ) , succ0 ) ; } } } </s>

The same functionality as arc_hazard . It is called in machine reorg before any other optimization . Hence , the NOP size is taken into account when doing branch shortening .


<s> bool ARMTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , getTargetMachine ( ) , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , CCAssignFnForNode ( CallConv , true , isVarArg ) ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> void addInst ( MachineBasicBlock :: iterator I , unsigned SPAdjust , bool BeforeFPSet = false ) { InstInfo Info = { I , SPAdjust , BeforeFPSet } ; Insts . push_back ( Info ) ; } </s>


<s>
void
PPCDispatchGroupSBHazardRecognizer
::
RecedeCycle
(
)
{
llvm_unreachable
(
"Bottom-up scheduling not supported"
)
;
}
</s>

RecedeCycle - This callback is invoked whenever the next bottom-up instruction to be scheduled can not issue in the current cycle , either because of latency or resource conflicts .

PowerPC
PPC
"Bottom-up scheduling not supported"


<s> static void rs6000_finish_atomic_subword ( rtx narrow , rtx wide , rtx shift ) { wide = expand_simple_binop ( SImode , LSHIFTRT , wide , shift , wide , 1 , OPTAB_LIB_WIDEN ) ; emit_move_insn ( narrow , gen_lowpart ( GET_MODE ( narrow ) , wide ) ) ; } </s>

A subroutine of the various atomic expanders . For sub-word operands , extract WIDE to NARROW via SHIFT .


<s> bool ARMTargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { if ( ! Subtarget -> supportsTailCall ( ) ) return false ; auto Attr = CI -> getParent ( ) -> getParent ( ) -> getFnAttribute ( "disable-tail-calls" ) ; if ( ! CI -> isTailCall ( ) || Attr . getValueAsString ( ) == "true" ) return false ; return ! Subtarget -> isThumb1Only ( ) ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> bool PatmosInstrInfo :: isPredicated ( const MachineInstr & MI ) const { if ( MI . isBundle ( ) ) { auto II = MI . getIterator ( ) ; while ( II -> isBundledWithSucc ( ) ) { ++ II ; if ( isPredicated ( * II ) ) return true ; } return false ; } int i = MI . findFirstPredOperandIdx ( ) ; if ( i != - 1 ) { unsigned preg = MI . getOperand ( i ) . getReg ( ) ; int flag = MI . getOperand ( i + 1 ) . getImm ( ) ; return ( preg != Patmos :: NoRegister && preg != Patmos :: P0 ) || flag ; } return false ; } </s>

Returns true if the instruction is already predicated .


<s>
MCSymbol
*
MBlazeMCInstLower
::
GetBlockAddressSymbol
(
const
MachineOperand
&
MO
)
const
{
switch
(
MO
.
getTargetFlags
(
)
)
{
default
:
assert
(
0
&&
"Unknown target flag on GV operand"
)
;
case
0
:
break
;
}
return
Printer
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
;
}
</s>

Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block .


<s> bool SparcFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> void c4x_external_ref ( const char * name ) { struct name_list * p ; p = extern_head ; while ( p ) { if ( strcmp ( p -> name , name ) == 0 ) return ; p = p -> next ; } p = global_head ; while ( p ) { if ( strcmp ( p -> name , name ) == 0 ) return ; p = p -> next ; } p = ( struct name_list * ) xmalloc ( sizeof * p ) ; p -> next = extern_head ; p -> name = name ; extern_head = p ; } </s>


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


"Cannot store this register to stack slot!"

Store the specified register of the given register class to the specified stack frame index .


<s> static bool csky_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { if ( to == FRAME_POINTER_REGNUM ) return from != ARG_POINTER_REGNUM ; if ( to == STACK_POINTER_REGNUM ) return ! frame_pointer_needed ; return true ; } </s>


<s> std :: pair < unsigned , const TargetRegisterClass * > BlackfinTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { typedef std :: pair < unsigned , const TargetRegisterClass * > Pair ; using namespace BF ; if ( Constraint . size ( ) != 1 ) return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; switch ( Constraint [ 0 ] ) { case 'r' : return Pair ( 0U , VT == MVT :: i16 ? D16RegisterClass : DPRegisterClass ) ; case 'a' : return Pair ( 0U , PRegisterClass ) ; case 'd' : return Pair ( 0U , DRegisterClass ) ; case 'e' : return Pair ( 0U , AccuRegisterClass ) ; case 'A' : return Pair ( A0 , AccuRegisterClass ) ; case 'B' : return Pair ( A1 , AccuRegisterClass ) ; case 'b' : return Pair ( 0U , IRegisterClass ) ; case 'v' : return Pair ( 0U , BRegisterClass ) ; case 'f' : return Pair ( 0U , MRegisterClass ) ; case 'C' : return Pair ( CC , JustCCRegisterClass ) ; case 'x' : return Pair ( 0U , GRRegisterClass ) ; case 'w' : return Pair ( 0U , ALLRegisterClass ) ; case 'Z' : return Pair ( P3 , PRegisterClass ) ; case 'Y' : return Pair ( P1 , PRegisterClass ) ; case 'z' : return Pair ( 0U , zConsRegisterClass ) ; case 'D' : return Pair ( 0U , DConsRegisterClass ) ; case 'W' : return Pair ( 0U , WConsRegisterClass ) ; case 'c' : return Pair ( 0U , cConsRegisterClass ) ; case 't' : return Pair ( 0U , tConsRegisterClass ) ; case 'u' : return Pair ( 0U , uConsRegisterClass ) ; case 'k' : return Pair ( 0U , kConsRegisterClass ) ; case 'y' : return Pair ( 0U , yConsRegisterClass ) ; } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> bool writeNopData ( raw_ostream & OS , uint64_t Count ) const override { OS . write_zeros ( Count ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> bool NVPTXLowerAggrCopies :: runOnFunction ( Function & F ) { SmallVector < LoadInst * , 4 > AggrLoads ; SmallVector < MemIntrinsic * , 4 > MemCalls ; const DataLayout & DL = F . getParent ( ) -> getDataLayout ( ) ; LLVMContext & Context = F . getParent ( ) -> getContext ( ) ; const TargetTransformInfo & TTI = getAnalysis < TargetTransformInfoWrapperPass > ( ) . getTTI ( F ) ; for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { if ( LoadInst * LI = dyn_cast < LoadInst > ( & I ) ) { if ( ! LI -> hasOneUse ( ) ) continue ; if ( DL . getTypeStoreSize ( LI -> getType ( ) ) < MaxAggrCopySize ) continue ; if ( StoreInst * SI = dyn_cast < StoreInst > ( LI -> user_back ( ) ) ) { if ( SI -> getOperand ( 0 ) != LI ) continue ; AggrLoads . push_back ( LI ) ; } } else if ( MemIntrinsic * IntrCall = dyn_cast < MemIntrinsic > ( & I ) ) { if ( ConstantInt * LenCI = dyn_cast < ConstantInt > ( IntrCall -> getLength ( ) ) ) { if ( LenCI -> getZExtValue ( ) >= MaxAggrCopySize ) { MemCalls . push_back ( IntrCall ) ; } } else { MemCalls . push_back ( IntrCall ) ; } } } } if ( AggrLoads . size ( ) == 0 && MemCalls . size ( ) == 0 ) { return false ; } for ( LoadInst * LI : AggrLoads ) { auto * SI = cast < StoreInst > ( * LI -> user_begin ( ) ) ; Value * SrcAddr = LI -> getOperand ( 0 ) ; Value * DstAddr = SI -> getOperand ( 1 ) ; unsigned NumLoads = DL . getTypeStoreSize ( LI -> getType ( ) ) ; ConstantInt * CopyLen = ConstantInt :: get ( Type :: getInt32Ty ( Context ) , NumLoads ) ; createMemCpyLoopKnownSize ( SI , SrcAddr , DstAddr , CopyLen , LI -> getAlign ( ) , SI -> getAlign ( ) , LI -> isVolatile ( ) , SI -> isVolatile ( ) , TTI ) ; SI -> eraseFromParent ( ) ; LI -> eraseFromParent ( ) ; } for ( MemIntrinsic * MemCall : MemCalls ) { if ( MemCpyInst * Memcpy = dyn_cast < MemCpyInst > ( MemCall ) ) { expandMemCpyAsLoop ( Memcpy , TTI ) ; } else if ( MemMoveInst * Memmove = dyn_cast < MemMoveInst > ( MemCall ) ) { expandMemMoveAsLoop ( Memmove ) ; } else if ( MemSetInst * Memset = dyn_cast < MemSetInst > ( MemCall ) ) { expandMemSetAsLoop ( Memset ) ; } MemCall -> eraseFromParent ( ) ; } return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static void AnalyzeArguments ( CCState & State , SmallVectorImpl < CCValAssign > & ArgLocs , const SmallVectorImpl < ArgT > & Args ) { static const MCPhysReg RegList [ ] = { MSP430 :: R15W , MSP430 :: R14W , MSP430 :: R13W , MSP430 :: R12W } ; static const unsigned NbRegs = array_lengthof ( RegList ) ; if ( State . isVarArg ( ) ) { AnalyzeVarArgs ( State , Args ) ; return ; } SmallVector < unsigned , 4 > ArgsParts ; ParseFunctionArgs ( Args , ArgsParts ) ; unsigned RegsLeft = NbRegs ; bool UseStack = false ; unsigned ValNo = 0 ; for ( unsigned i = 0 , e = ArgsParts . size ( ) ; i != e ; i ++ ) { MVT ArgVT = Args [ ValNo ] . VT ; ISD :: ArgFlagsTy ArgFlags = Args [ ValNo ] . Flags ; MVT LocVT = ArgVT ; CCValAssign :: LocInfo LocInfo = CCValAssign :: Full ; if ( LocVT == MVT :: i8 ) { LocVT = MVT :: i16 ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } if ( ArgFlags . isByVal ( ) ) { State . HandleByVal ( ValNo ++ , ArgVT , LocVT , LocInfo , 2 , 2 , ArgFlags ) ; continue ; } unsigned Parts = ArgsParts [ i ] ; if ( ! UseStack && Parts <= RegsLeft ) { unsigned FirstVal = ValNo ; for ( unsigned j = 0 ; j < Parts ; j ++ ) { unsigned Reg = State . AllocateReg ( RegList , NbRegs ) ; State . addLoc ( CCValAssign :: getReg ( ValNo ++ , ArgVT , Reg , LocVT , LocInfo ) ) ; RegsLeft -- ; } SmallVectorImpl < CCValAssign > :: iterator B = ArgLocs . begin ( ) + FirstVal ; std :: reverse ( B , B + Parts ) ; } else { UseStack = true ; for ( unsigned j = 0 ; j < Parts ; j ++ ) CC_MSP430_AssignStack ( ValNo ++ , ArgVT , LocVT , LocInfo , ArgFlags , State ) ; } } } </s>

The function will invoke AnalyzeCallOperands .


"AVR dynalloca stack pointer save/restore"

getPassName - Return a nice clean name for a pass .


<s> virtual bool trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> void ix86_override_options_after_change ( void ) { ix86_default_align ( & global_options ) ; ix86_recompute_optlev_based_flags ( & global_options , & global_options_set ) ; if ( ( OPTION_SET_P ( flag_unroll_loops ) ) || ( OPTION_SET_P ( flag_unroll_all_loops ) && flag_unroll_all_loops ) ) { if ( ! OPTION_SET_P ( ix86_unroll_only_small_loops ) ) ix86_unroll_only_small_loops = 0 ; if ( ! OPTION_SET_P ( flag_web ) ) flag_web = flag_unroll_loops ; if ( ! OPTION_SET_P ( flag_rename_registers ) ) flag_rename_registers = flag_unroll_loops ; if ( ! OPTION_SET_P ( flag_cunroll_grow_size ) ) flag_cunroll_grow_size = flag_unroll_loops || flag_peel_loops || optimize >= 3 ; } else { if ( ! OPTION_SET_P ( flag_cunroll_grow_size ) ) flag_cunroll_grow_size = flag_peel_loops || optimize >= 3 ; } } </s>

Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE hook .


<s>
bool
AArch64A53Fix835769
::
runOnMachineFunction
(
MachineFunction
&
F
)
{
const
TargetMachine
&
TM
=
F
.
getTarget
(
)
;
bool
Changed
=
false
;
DEBUG
(
dbgs
(
)
<<
"***** AArch64A53Fix835769 *****\n"
)
;
TII
=
TM
.
getSubtarget
<
AArch64Subtarget
>
(
)
.
getInstrInfo
(
)
;
for
(
auto
&
MBB
:
F
)
{
Changed
|=
runOnBasicBlock
(
MBB
)
;
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


"READCYCLECOUNTER only has custom type legalization on riscv32"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


"Dangerous instruction in branch delay slot!"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static bool mep_store_find_set ( const_rtx x , const rtx_insn * prev ) { subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , x , NONCONST ) if ( REG_P ( x ) && reg_set_p ( x , prev ) ) return true ; return false ; } </s>

Return true if X contains a register that is set by insn PREV .


<s> bool GCNTTIImpl :: areInlineCompatible ( const Function * Caller , const Function * Callee ) const { const TargetMachine & TM = getTLI ( ) -> getTargetMachine ( ) ; const GCNSubtarget * CallerST = static_cast < const GCNSubtarget * > ( TM . getSubtargetImpl ( * Caller ) ) ; const GCNSubtarget * CalleeST = static_cast < const GCNSubtarget * > ( TM . getSubtargetImpl ( * Callee ) ) ; const FeatureBitset & CallerBits = CallerST -> getFeatureBits ( ) ; const FeatureBitset & CalleeBits = CalleeST -> getFeatureBits ( ) ; FeatureBitset RealCallerBits = CallerBits & ~ InlineFeatureIgnoreList ; FeatureBitset RealCalleeBits = CalleeBits & ~ InlineFeatureIgnoreList ; if ( ( RealCallerBits & RealCalleeBits ) != RealCalleeBits ) return false ; AMDGPU :: SIModeRegisterDefaults CallerMode ( * Caller ) ; AMDGPU :: SIModeRegisterDefaults CalleeMode ( * Callee ) ; return CallerMode . isInlineCompatible ( CalleeMode ) ; } </s>

Determine whether a callee with the given TLI can be inlined into caller with this TLI , based on 'nobuiltin ' attributes .


<s> const uint32_t * PPCRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; if ( CC == CallingConv :: AnyReg ) { if ( Subtarget . hasVSX ( ) ) return CSR_64_AllRegs_VSX_RegMask ; if ( Subtarget . hasAltivec ( ) ) return CSR_64_AllRegs_Altivec_RegMask ; return CSR_64_AllRegs_RegMask ; } if ( Subtarget . isDarwinABI ( ) ) return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_RegMask : CSR_Darwin64_RegMask ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_RegMask : CSR_Darwin32_RegMask ) ; if ( CC == CallingConv :: Cold ) { return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_SVR64_ColdCC_Altivec_RegMask : CSR_SVR64_ColdCC_RegMask ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR32_ColdCC_Altivec_RegMask : CSR_SVR32_ColdCC_RegMask ) ; } return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_SVR464_Altivec_RegMask : CSR_SVR464_RegMask ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR432_Altivec_RegMask : CSR_SVR432_RegMask ) ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void ix86_emit_fp_unordered_jump ( rtx label ) { rtx reg = gen_reg_rtx ( HImode ) ; rtx temp ; emit_insn ( gen_x86_fnstsw_1 ( reg ) ) ; if ( TARGET_SAHF && ( TARGET_USE_SAHF || optimize_insn_for_size_p ( ) ) ) { emit_insn ( gen_x86_sahf_1 ( reg ) ) ; temp = gen_rtx_REG ( CCmode , FLAGS_REG ) ; temp = gen_rtx_UNORDERED ( VOIDmode , temp , const0_rtx ) ; } else { emit_insn ( gen_testqi_ext_1_ccno ( reg , GEN_INT ( 0x04 ) ) ) ; temp = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; temp = gen_rtx_NE ( VOIDmode , temp , const0_rtx ) ; } temp = gen_rtx_IF_THEN_ELSE ( VOIDmode , temp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; temp = gen_rtx_SET ( pc_rtx , temp ) ; emit_jump_insn ( temp ) ; predict_jump ( REG_BR_PROB_BASE * 10 / 100 ) ; } </s>

Output code to perform a conditional jump to LABEL , if C2 flag in FP status register is set .


<s> void HexagonRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOp , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; MachineBasicBlock & MB = * MI . getParent ( ) ; MachineFunction & MF = * MB . getParent ( ) ; auto & HST = MF . getSubtarget < HexagonSubtarget > ( ) ; auto & HII = * HST . getInstrInfo ( ) ; auto & HFI = * HST . getFrameLowering ( ) ; unsigned BP = 0 ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; int Offset = HFI . getFrameIndexReference ( MF , FI , BP ) ; int RealOffset = Offset + MI . getOperand ( FIOp + 1 ) . getImm ( ) ; bool IsKill = false ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case Hexagon :: TFR_FIA : MI . setDesc ( HII . get ( Hexagon :: A2_addi ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + 1 ) ; return ; case Hexagon :: TFR_FI : MI . setDesc ( HII . get ( Hexagon :: A2_addi ) ) ; break ; } if ( ! HII . isValidOffset ( Opc , RealOffset ) ) { auto & MRI = MF . getRegInfo ( ) ; unsigned TmpR = MRI . createVirtualRegister ( & Hexagon :: IntRegsRegClass ) ; DebugLoc DL = MI . getDebugLoc ( ) ; BuildMI ( MB , II , DL , HII . get ( Hexagon :: A2_addi ) , TmpR ) . addReg ( BP ) . addImm ( RealOffset ) ; BP = TmpR ; RealOffset = 0 ; IsKill = true ; } MI . getOperand ( FIOp ) . ChangeToRegister ( BP , false , false , IsKill ) ; MI . getOperand ( FIOp + 1 ) . ChangeToImmediate ( RealOffset ) ; } </s>


<s> void RISCVPassConfig :: addPreSched2 ( ) { } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> TargetPassConfig * AVRTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new AVRPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> bool operands_ok_ldrd_strd ( rtx rt , rtx rt2 , rtx rn , HOST_WIDE_INT offset , bool wback , bool load ) { unsigned int t , t2 , n ; if ( ! reload_completed ) return true ; if ( ! offset_ok_for_ldrd_strd ( offset ) ) return false ; t = REGNO ( rt ) ; t2 = REGNO ( rt2 ) ; n = REGNO ( rn ) ; if ( ( TARGET_THUMB2 ) && ( ( wback && ( n == t || n == t2 ) ) || ( t == SP_REGNUM ) || ( t == PC_REGNUM ) || ( t2 == SP_REGNUM ) || ( t2 == PC_REGNUM ) || ( ! load && ( n == PC_REGNUM ) ) || ( load && ( t == t2 ) ) || ( ! wback && load && fix_cm3_ldrd && ( n == t ) ) ) ) return false ; if ( ( TARGET_ARM ) && ( ( wback && ( n == t || n == t2 ) ) || ( t2 == PC_REGNUM ) || ( t % 2 != 0 ) || ( t2 != t + 1 ) || ( n == PC_REGNUM ) ) ) return false ; return true ; } </s>

Checks whether the operands are valid for use in an LDRD/STRD instruction . Assumes that RT , RT2 , and RN are REG . This is guaranteed by the patterns . Assumes that the address in the base register RN is word aligned . Pattern guarantees that both memory accesses use the same base register , the offsets are constants within the range , and the gap between the offsets is 4 . If preload complete then check that registers are legal . WBACK indicates whether address is updated . LOAD indicates whether memory access is load or store .


<s>
void
ScheduleDAGPostRA
::
releaseSucc
(
SUnit
*
SU
,
SDep
*
SuccEdge
)
{
SUnit
*
SuccSU
=
SuccEdge
->
getSUnit
(
)
;
if
(
SuccEdge
->
isWeak
(
)
)
{
SuccSU
->
WeakPredsLeft
;
return
;
}
if
(
SuccSU
->
NumPredsLeft
==
0
)
{
dbgs
(
)
<<
"*** Scheduling failed! ***\n"
;
SuccSU
->
dumpAttributes
(
)
;
dbgs
(
)
<<
" has been released too many times!\n"
;
llvm_unreachable
(
0
)
;
}
SuccSU
->
NumPredsLeft
;
if
(
SuccSU
->
NumPredsLeft
==
0
&&
SuccSU
!=
&
ExitSU
)
SchedImpl
->
releaseTopNode
(
SuccSU
)
;
}
</s>

ReleaseSucc - Decrement the NumPredsLeft count of a successor .


"expression value must be representiable in 32 bits"

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> static rtx mips_force_temporary ( rtx dest , rtx value ) { if ( can_create_pseudo_p ( ) ) return force_reg ( Pmode , value ) ; else { mips_emit_move ( dest , value ) ; return dest ; } } </s>

Copy VALUE to a register and return that register . If new psuedos are allowed , copy it into a new register , otherwise use DEST .


<s> static bool aarch64_mode_valid_for_sched_fusion_p ( machine_mode mode ) { return mode == SImode || mode == DImode || mode == SFmode || mode == DFmode || ( aarch64_vector_mode_supported_p ( mode ) && ( known_eq ( GET_MODE_SIZE ( mode ) , 8 ) || ( known_eq ( GET_MODE_SIZE ( mode ) , 16 ) && ( aarch64_tune_params . extra_tuning_flags & AARCH64_EXTRA_TUNE_NO_LDP_STP_QREGS ) == 0 ) ) ) ; } </s>

Return true if MODE is one of the modes for which we support LDP/STP operations .


<s> static MipsOperand * CreateMem ( unsigned Base , const MCExpr * Off , SMLoc S , SMLoc E ) { MipsOperand * Op = new MipsOperand ( k_Memory ) ; Op -> Mem . Base = Base ; Op -> Mem . Off = Off ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>


<s>
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
AVRTargetLowering
::
getRegForInlineAsmConstraint
(
const
TargetRegisterInfo
*
TRI
,
StringRef
Constraint
,
MVT
VT
)
const
{
if
(
Constraint
.
size
(
)
==
1
)
{
switch
(
Constraint
[
0
]
)
{
case
'a'
:
return
std
::
make_pair
(
0U
,
&
AVR
::
LD8loRegClass
)
;
case
'b'
:
return
std
::
make_pair
(
0U
,
&
AVR
::
PTRDISPREGSRegClass
)
;
case
'd'
:
return
std
::
make_pair
(
0U
,
&
AVR
::
LD8RegClass
)
;
case
'l'
:
return
std
::
make_pair
(
0U
,
&
AVR
::
GPR8loRegClass
)
;
case
'e'
:
return
std
::
make_pair
(
0U
,
&
AVR
::
PTRREGSRegClass
)
;
case
'q'
:
return
std
::
make_pair
(
0U
,
&
AVR
::
GPRSPRegClass
)
;
case
'r'
:
if
(
VT
==
MVT
::
i8
)
return
std
::
make_pair
(
0U
,
&
AVR
::
GPR8RegClass
)
;
assert
(
VT
==
MVT
::
i16
&&
"inline asm constraint too large"
)
;
return
std
::
make_pair
(
0U
,
&
AVR
::
DREGSRegClass
)
;
case
't'
:
return
std
::
make_pair
(
unsigned
(
AVR
::
R0
)
,
&
AVR
::
GPR8RegClass
)
;
case
'w'
:
return
std
::
make_pair
(
0U
,
&
AVR
::
IWREGSRegClass
)
;
case
'x'
:
case
'X'
:
return
std
::
make_pair
(
unsigned
(
AVR
::
R27R26
)
,
&
AVR
::
PTRREGSRegClass
)
;
case
'y'
:
case
'Y'
:
return
std
::
make_pair
(
unsigned
(
AVR
::
R29R28
)
,
&
AVR
::
PTRREGSRegClass
)
;
case
'z'
:
case
'Z'
:
return
std
::
make_pair
(
unsigned
(
AVR
::
R31R30
)
,
&
AVR
::
PTRREGSRegClass
)
;
default
:
break
;
}
}
return
TargetLowering
::
getRegForInlineAsmConstraint
(
Subtarget
.
getRegisterInfo
(
)
,
Constraint
,
VT
)
;
}
</s>

Given a physical register constraint ( e.g .


<s> SDValue PPCTargetLowering :: getSqrtInputTest ( SDValue Op , SelectionDAG & DAG , const DenormalMode & Mode ) const { EVT VT = Op . getValueType ( ) ; if ( ! isTypeLegal ( MVT :: i1 ) || ( VT != MVT :: f64 && ( ( VT != MVT :: v2f64 && VT != MVT :: v4f32 ) || ! Subtarget . hasVSX ( ) ) ) ) return TargetLowering :: getSqrtInputTest ( Op , DAG , Mode ) ; SDLoc DL ( Op ) ; SDValue FTSQRT = DAG . getNode ( PPCISD :: FTSQRT , DL , MVT :: i32 , Op ) ; SDValue SRIdxVal = DAG . getTargetConstant ( PPC :: sub_eq , DL , MVT :: i32 ) ; return SDValue ( DAG . getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , MVT :: i1 , FTSQRT , SRIdxVal ) , 0 ) ; } </s>

Return a target-dependent comparison result if the input operand is suitable for use with a square root estimate calculation .


<s> virtual MVT getShiftAmountTy ( EVT LHSTy ) const { return MVT :: i32 ; } </s>

Returns the type for the shift amount of a shift opcode .


<s>
SDValue
PPCTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCRetInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCRetInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_PPC
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
VT
=
VA
.
getValVT
(
)
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
VT
,
InFlag
)
.
getValue
(
1
)
;
InVals
.
push_back
(
Chain
.
getValue
(
0
)
)
;
InFlag
=
Chain
.
getValue
(
2
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


"Cannot handle this call frame pseudo instruction"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static bool mips_vectorize_vec_perm_const_ok ( machine_mode vmode , const unsigned char * sel ) { struct expand_vec_perm_d d ; unsigned int i , nelt , which ; bool ret ; d . vmode = vmode ; d . nelt = nelt = GET_MODE_NUNITS ( d . vmode ) ; d . testing_p = true ; memcpy ( d . perm , sel , nelt ) ; for ( i = which = 0 ; i < nelt ; ++ i ) { unsigned char e = d . perm [ i ] ; gcc_assert ( e < 2 * nelt ) ; which |= ( e < nelt ? 1 : 2 ) ; } if ( which == 2 ) for ( i = 0 ; i < nelt ; ++ i ) d . perm [ i ] -= nelt ; d . one_vector_p = ( which != 3 ) ; d . target = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 1 ) ; d . op1 = d . op0 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 2 ) ; if ( ! d . one_vector_p ) d . op1 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 3 ) ; start_sequence ( ) ; ret = mips_expand_vec_perm_const_1 ( & d ) ; end_sequence ( ) ; return ret ; } </s>


<s> void GCNPassConfig :: addPreEmitPass ( ) { addPass ( & PostRAHazardRecognizerID ) ; addPass ( createSIMemoryLegalizerPass ( ) ) ; if ( EnableSIInsertWaitcntsPass ) addPass ( createSIInsertWaitcntsPass ( ) ) ; else addPass ( createSIInsertWaitsPass ( ) ) ; addPass ( createSIShrinkInstructionsPass ( ) ) ; addPass ( & SIInsertSkipsPassID ) ; addPass ( createSIDebuggerInsertNopsPass ( ) ) ; addPass ( & BranchRelaxationPassID ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool mn10300_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( REGNO_REG_CLASS ( regno ) == FP_REGS || REGNO_REG_CLASS ( regno ) == FP_ACC_REGS ) return GET_MODE_CLASS ( mode ) == MODE_FLOAT && ( ( regno & 1 ) == 0 ) ; if ( ! TARGET_AM33 && REGNO_REG_CLASS ( regno ) == EXTENDED_REGS ) return false ; if ( ( ( regno ) & 1 ) == 0 || GET_MODE_SIZE ( mode ) == 4 ) return true ; if ( REGNO_REG_CLASS ( regno ) == DATA_REGS || ( TARGET_AM33 && REGNO_REG_CLASS ( regno ) == ADDRESS_REGS ) || REGNO_REG_CLASS ( regno ) == EXTENDED_REGS ) return GET_MODE_SIZE ( mode ) <= 4 ; return false ; } </s>


<s> bool MipsSEDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & static_cast < const MipsSubtarget & > ( MF . getSubtarget ( ) ) ; if ( Subtarget -> inMips16Mode ( ) ) return false ; return MipsDAGToDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool MSP430PassConfig :: addInstSelector ( ) { addPass ( createMSP430ISelDag ( getMSP430TargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static tree ix86_veclibabi_svml ( enum built_in_function fn , tree type_out , tree type_in ) { char name [ 20 ] ; tree fntype , new_fndecl , args ; unsigned arity ; const char * bname ; machine_mode el_mode , in_mode ; int n , in_n ; if ( ! flag_unsafe_math_optimizations ) return NULL_TREE ; el_mode = TYPE_MODE ( TREE_TYPE ( type_out ) ) ; n = TYPE_VECTOR_SUBPARTS ( type_out ) ; in_mode = TYPE_MODE ( TREE_TYPE ( type_in ) ) ; in_n = TYPE_VECTOR_SUBPARTS ( type_in ) ; if ( el_mode != in_mode || n != in_n ) return NULL_TREE ; switch ( fn ) { case BUILT_IN_EXP : case BUILT_IN_LOG : case BUILT_IN_LOG10 : case BUILT_IN_POW : case BUILT_IN_TANH : case BUILT_IN_TAN : case BUILT_IN_ATAN : case BUILT_IN_ATAN2 : case BUILT_IN_ATANH : case BUILT_IN_CBRT : case BUILT_IN_SINH : case BUILT_IN_SIN : case BUILT_IN_ASINH : case BUILT_IN_ASIN : case BUILT_IN_COSH : case BUILT_IN_COS : case BUILT_IN_ACOSH : case BUILT_IN_ACOS : if ( el_mode != DFmode || n != 2 ) return NULL_TREE ; break ; case BUILT_IN_EXPF : case BUILT_IN_LOGF : case BUILT_IN_LOG10F : case BUILT_IN_POWF : case BUILT_IN_TANHF : case BUILT_IN_TANF : case BUILT_IN_ATANF : case BUILT_IN_ATAN2F : case BUILT_IN_ATANHF : case BUILT_IN_CBRTF : case BUILT_IN_SINHF : case BUILT_IN_SINF : case BUILT_IN_ASINHF : case BUILT_IN_ASINF : case BUILT_IN_COSHF : case BUILT_IN_COSF : case BUILT_IN_ACOSHF : case BUILT_IN_ACOSF : if ( el_mode != SFmode || n != 4 ) return NULL_TREE ; break ; default : return NULL_TREE ; } bname = IDENTIFIER_POINTER ( DECL_NAME ( builtin_decl_implicit ( fn ) ) ) ; if ( fn == BUILT_IN_LOGF ) strcpy ( name , "vmlsLn4" ) ; else if ( fn == BUILT_IN_LOG ) strcpy ( name , "vmldLn2" ) ; else if ( n == 4 ) { sprintf ( name , "vmls%s" , bname + 10 ) ; name [ strlen ( name ) - 1 ] = '4' ; } else sprintf ( name , "vmld%s2" , bname + 10 ) ; name [ 4 ] &= ~ 0x20 ; arity = 0 ; for ( args = DECL_ARGUMENTS ( builtin_decl_implicit ( fn ) ) ; args ; args = TREE_CHAIN ( args ) ) arity ++ ; if ( arity == 1 ) fntype = build_function_type_list ( type_out , type_in , NULL ) ; else fntype = build_function_type_list ( type_out , type_in , type_in , NULL ) ; new_fndecl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , fntype ) ; TREE_PUBLIC ( new_fndecl ) = 1 ; DECL_EXTERNAL ( new_fndecl ) = 1 ; DECL_IS_NOVOPS ( new_fndecl ) = 1 ; TREE_READONLY ( new_fndecl ) = 1 ; return new_fndecl ; } </s>

Handler for an SVML-style interface to a library with vectorized intrinsics .


<s> unsigned getSpillSize ( const TargetRegisterClass & RC ) const override { return 4 ; } </s>

Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class RC .


<s> int hppa_can_use_return_insn_p ( void ) { return ( reload_completed && ( compute_frame_size ( get_frame_size ( ) , 0 ) ? 0 : 1 ) && ! regs_ever_live [ 2 ] && ! frame_pointer_needed ) ; } </s>

This is only valid once reload has completed because it depends on knowing exactly how much ( if any ) frame there is and ... It 's only valid if there is no frame marker to de-allocate and ... It 's only valid if % r2 has n't been saved into the caller 's frame ( we 're not profiling and % r2 is n't live anywhere ) .


<s> bool RISCVCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs ) const { if ( F . arg_empty ( ) ) return true ; return false ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> static bool aarch64_evpc_rev_local ( struct expand_vec_perm_d * d ) { HOST_WIDE_INT diff ; unsigned int i , size , unspec ; machine_mode pred_mode ; if ( d -> vec_flags == VEC_SVE_PRED || ! d -> one_vector_p || ! d -> perm [ 0 ] . is_constant ( & diff ) ) return false ; size = ( diff + 1 ) * GET_MODE_UNIT_SIZE ( d -> vmode ) ; if ( size == 8 ) { unspec = UNSPEC_REV64 ; pred_mode = VNx2BImode ; } else if ( size == 4 ) { unspec = UNSPEC_REV32 ; pred_mode = VNx4BImode ; } else if ( size == 2 ) { unspec = UNSPEC_REV16 ; pred_mode = VNx8BImode ; } else return false ; unsigned int step = diff + 1 ; for ( i = 0 ; i < step ; ++ i ) if ( ! d -> perm . series_p ( i , step , diff - i , step ) ) return false ; if ( d -> testing_p ) return true ; if ( d -> vec_flags == VEC_SVE_DATA ) { machine_mode int_mode = aarch64_sve_int_mode ( pred_mode ) ; rtx target = gen_reg_rtx ( int_mode ) ; if ( BYTES_BIG_ENDIAN ) emit_insn ( gen_aarch64_sve_reinterpret ( int_mode , target , d -> op0 ) ) ; else { int unspec = aarch64_sve_rev_unspec ( d -> vmode ) ; rtx pred = aarch64_ptrue_reg ( pred_mode ) ; emit_insn ( gen_aarch64_pred ( unspec , int_mode , target , pred , gen_lowpart ( int_mode , d -> op0 ) ) ) ; } emit_move_insn ( d -> target , gen_lowpart ( d -> vmode , target ) ) ; return true ; } rtx src = gen_rtx_UNSPEC ( d -> vmode , gen_rtvec ( 1 , d -> op0 ) , unspec ) ; emit_set_insn ( d -> target , src ) ; return true ; } </s>

Recognize patterns for the REV { 64,32,16 } insns , which reverse elements within each 64-bit , 32-bit or 16-bit granule .


<s> void Mips16FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( STI . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( ! StackSize ) return ; if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: Move32R16 ) , Mips :: SP ) . addReg ( Mips :: S0 ) ; TII . restoreFrame ( Mips :: SP , StackSize , MBB , MBBI ) ; } </s>

Mips Mips Mips Mips Mips::Move32R16 Mips::SP Mips::S0 Mips::SP


Internal method for ix86_init_builtins .


<s> static bool alpha_mode_dependent_address_p ( const_rtx addr , addr_space_t as ATTRIBUTE_UNUSED ) { return GET_CODE ( addr ) == AND ; } </s>

Return true if ADDR has an effect that depends on the machine mode it is used for . On the Alpha this is true only for the unaligned modes . We can simplify the test since we know that the address must be valid .


<s> void Thumb2InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( ARM :: GPRRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( ARM :: t2STRi12 ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; return ; } if ( ARM :: GPRPairRegClass . hasSubClassEq ( RC ) ) { if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( SrcReg , & ARM :: GPRPair_with_gsub_1_in_rGPRRegClass ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( ARM :: t2STRDi8 ) ) ; AddDReg ( MIB , SrcReg , ARM :: gsub_0 , getKillRegState ( isKill ) , TRI ) ; AddDReg ( MIB , SrcReg , ARM :: gsub_1 , 0 , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; return ; } ARMBaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg , isKill , FI , RC , TRI ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool AArch64PassConfig :: addLegalizeMachineIR ( ) { addPass ( new MachineLegalizePass ( ) ) ; return false ; } </s>

This method should install a legalize pass , which converts the instruction sequence into one that can be selected by the target .


<s> bool Error ( SMLoc L , const Twine & Msg ) { return Parser . Error ( L , Msg ) ; } </s>

Return an error at the location L , with the message Msg .


<s> bool AArch64InstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , const SmallVectorImpl < MachineOperand > & Cond , unsigned TrueReg , unsigned FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; unsigned ExtraCondLat = Cond . size ( ) != 1 ; if ( AArch64 :: GPR64allRegClass . hasSubClassEq ( RC ) || AArch64 :: GPR32allRegClass . hasSubClassEq ( RC ) ) { CondCycles = 1 + ExtraCondLat ; TrueCycles = FalseCycles = 1 ; if ( canFoldIntoCSel ( MRI , TrueReg ) ) TrueCycles = 0 ; else if ( canFoldIntoCSel ( MRI , FalseReg ) ) FalseCycles = 0 ; return true ; } if ( AArch64 :: FPR64RegClass . hasSubClassEq ( RC ) || AArch64 :: FPR32RegClass . hasSubClassEq ( RC ) ) { CondCycles = 5 + ExtraCondLat ; TrueCycles = FalseCycles = 2 ; return true ; } return false ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> bool isReg ( ) const { return Kind == k_Register ; } </s>


<s> bool DagAssign :: runOnMachineFunction ( MachineFunction & Fn ) { const MachineLoopInfo & MLI = getAnalysis < MachineLoopInfo > ( ) ; const MachineDominatorTree & MDT = getAnalysis < MachineDominatorTree > ( ) ; AliasAnalysis * AA = & getAnalysis < AliasAnalysis > ( ) ; TMS320C64XMachineFunctionInfo * MFI = Fn . getInfo < TMS320C64XMachineFunctionInfo > ( ) ; std :: queue < MachineBasicBlock * > ScheduleQ ; std :: vector < unsigned > PredsVisited ( Fn . size ( ) , 0 ) ; std :: set < MachineBasicBlock * > Scheduled ; typedef std :: map < MachineBasicBlock * , MachineSuperBlock * > EntryMSBMap ; EntryMSBMap Entries ; unsigned sumCycles = 0 ; MachineSuperBlockMapTy MSBs = SuperblockFormation :: getSuperblocks ( ) ; AssignmentState State ; Scheduler = createClusterDAG ( Algo , Fn , MLI , MDT , AA , & State ) ; ResourceAssignment * RA = TMS320C64XInstrInfo :: CreateFunctionalUnitScheduler ( & TM ) ; Scheduler -> setFunctionalUnitScheduler ( RA ) ; for ( MachineSuperBlockMapTy :: iterator MSBI = MSBs . begin ( ) , MSBE = MSBs . end ( ) ; MSBI != MSBE ; ++ MSBI ) { MachineSuperBlock * MSB = MSBI -> second ; Entries . insert ( std :: make_pair ( MSB -> getEntry ( ) , MSB ) ) ; } ScheduleQ . push ( & Fn . front ( ) ) ; while ( ! ScheduleQ . empty ( ) ) { MachineBasicBlock * MBB = ScheduleQ . front ( ) ; ScheduleQ . pop ( ) ; if ( Scheduled . count ( MBB ) ) continue ; MachineSuperBlock * MSB ; std :: auto_ptr < MachineSuperBlock > ownedMSB ; EntryMSBMap :: iterator it ; if ( ( it = Entries . find ( MBB ) ) != Entries . end ( ) ) { MSB = it -> second ; } else { if ( ! MBB -> size ( ) ) continue ; ownedMSB = std :: auto_ptr < MachineSuperBlock > ( new MachineSuperBlock ( Fn , * MBB ) ) ; MSB = ownedMSB . get ( ) ; } assignPHIs ( & State , MBB ) ; Scheduler -> Run ( MSB ) ; Scheduled . insert ( MSB -> begin ( ) , MSB -> end ( ) ) ; sumCycles += Scheduler -> getCycles ( ) ; for ( MachineSuperBlock :: iterator MBBI = MSB -> begin ( ) , MBBE = MSB -> end ( ) ; MBBI != MBBE ; ++ MBBI ) { for ( MachineBasicBlock :: succ_iterator SI = ( * MBBI ) -> succ_begin ( ) , SE = ( * MBBI ) -> succ_end ( ) ; SI != SE ; ++ SI ) { MachineBasicBlock * Succ = * SI ; ScheduleQ . push ( Succ ) ; } } } MFI -> setScheduledCyclesPre ( sumCycles ) ; delete Scheduler ; delete RA ; return true ; } </s>


<s> bool isToken ( ) const override { return Kind == Token ; } </s>


<s> bool shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) override { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : return false ; case FK_NONE : return true ; case PPC :: fixup_ppc_br24 : case PPC :: fixup_ppc_br24abs : if ( const MCSymbolRefExpr * A = Target . getSymA ( ) ) { if ( const auto * S = dyn_cast < MCSymbolELF > ( & A -> getSymbol ( ) ) ) { unsigned Other = S -> getOther ( ) << 2 ; if ( ( Other & ELF :: STO_PPC64_LOCAL_MASK ) != 0 ) return true ; } } return false ; } } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> bool mn10300_function_value_regno_p ( const unsigned int regno ) { return ( regno == FIRST_DATA_REGNUM || regno == FIRST_ADDRESS_REGNUM ) ; } </s>


"unexpected inline assembly memory operand"

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> uint64_t MipsGOTPLT :: emit ( MemoryRegion & pRegion ) { uint32_t * buffer = reinterpret_cast < uint32_t * > ( pRegion . begin ( ) ) ; uint64_t result = 0 ; for ( iterator it = begin ( ) , ie = end ( ) ; it != ie ; ++ it , ++ buffer ) { GOTPLTEntry * got = & ( llvm :: cast < GOTPLTEntry > ( ( * it ) ) ) ; * buffer = static_cast < uint32_t > ( got -> getValue ( ) ) ; result += got -> size ( ) ; } return result ; } </s>

Output the remark via the diagnostic handler and to the optimization record file .


<s> static int arc_return_address_register ( unsigned int fn_type ) { int regno = 0 ; if ( ARC_INTERRUPT_P ( fn_type ) ) { if ( ( fn_type & ( ARC_FUNCTION_ILINK1 | ARC_FUNCTION_FIRQ ) ) != 0 ) regno = ILINK1_REG ; else if ( ( fn_type & ARC_FUNCTION_ILINK2 ) != 0 ) regno = ILINK2_REG ; else gcc_unreachable ( ) ; } else if ( ARC_NORMAL_P ( fn_type ) || ARC_NAKED_P ( fn_type ) ) regno = RETURN_ADDR_REGNUM ; gcc_assert ( regno != 0 ) ; return regno ; } </s>

Return the register number of the register holding the return address for a function of type TYPE .


<s> std :: pair < unsigned , const TargetRegisterClass * > PPCTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'b' : if ( VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RC_NOX0RegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRC_NOR0RegClass ) ; case 'r' : if ( VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RCRegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRCRegClass ) ; case 'f' : if ( VT == MVT :: f32 || VT == MVT :: i32 ) return std :: make_pair ( 0U , & PPC :: F4RCRegClass ) ; if ( VT == MVT :: f64 || VT == MVT :: i64 ) return std :: make_pair ( 0U , & PPC :: F8RCRegClass ) ; break ; case 'v' : return std :: make_pair ( 0U , & PPC :: VRRCRegClass ) ; case 'y' : return std :: make_pair ( 0U , & PPC :: CRRCRegClass ) ; } } else if ( Constraint == "wc" ) { return std :: make_pair ( 0U , & PPC :: CRBITRCRegClass ) ; } else if ( Constraint == "wa" || Constraint == "wd" || Constraint == "wf" || Constraint == "ws" ) { return std :: make_pair ( 0U , & PPC :: VSRCRegClass ) ; } std :: pair < unsigned , const TargetRegisterClass * > R = TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; if ( R . first && VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) && PPC :: GPRCRegClass . contains ( R . first ) ) { const TargetRegisterInfo * TRI = getTargetMachine ( ) . getRegisterInfo ( ) ; return std :: make_pair ( TRI -> getMatchingSuperReg ( R . first , PPC :: sub_32 , & PPC :: G8RCRegClass ) , & PPC :: G8RCRegClass ) ; } return R ; } </s>

Given a physical register constraint ( e.g .


<s> static rtx loongarch_force_binary ( machine_mode mode , enum rtx_code code , rtx op0 , rtx op1 ) { rtx reg ; reg = gen_reg_rtx ( mode ) ; loongarch_emit_binary ( code , reg , op0 , op1 ) ; return reg ; } </s>

Compute ( CODE OP0 OP1 ) and store the result in a new register of mode MODE . Return that new register .


"argument of type %qT not permitted with -mgeneral-regs-only"

Return true if an argument whose type is TYPE , or mode is MODE , is suitable for passing or returning in VFP registers for the PCS variant selected . If it is , then * BASE_MODE is updated to contain a machine mode describing each element of the argument 's type and * COUNT to hold the number of such elements .


<s>
static
void
nds32_asm_function_end_prologue
(
FILE
*
file
)
{
fprintf
(
file
,
"\t! END PROLOGUE\n"
)
;
}
</s>

After rtl prologue has been expanded , this function is used .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LiveIntervals > ( ) ; AU . addPreserved < SlotIndexes > ( ) ; AU . addPreserved < LiveIntervals > ( ) ; AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> const MCPhysReg * SIRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { CallingConv :: ID CC = MF -> getFunction ( ) . getCallingConv ( ) ; switch ( CC ) { case CallingConv :: C : case CallingConv :: Fast : case CallingConv :: Cold : return CSR_AMDGPU_HighRegs_SaveList ; default : { static const MCPhysReg NoCalleeSavedReg = AMDGPU :: NoRegister ; return & NoCalleeSavedReg ; } } } </s>


<s> machreg_t inet_netof ( machreg_t in ) { return _inet_netof ( in << SHIFT_BITS ) ; } </s>

< arpa/inet.h > has unsigned long inet_netof ( struct in_addr ) ; ( IRIX 6.2 ) in_addr_t inet_netof ( struct in_addr ) ; ( IRIX 6.5 )


<s> uint16_t getAttrs ( ) const { return Attrs ; } </s>

Return the attributes of any kind in AKs existing in the IR at a position that will affect this one .


<s> bool AArch64CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) == 0 ) continue ; ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; bool Split = false ; LLT Ty = MRI . getType ( VRegs [ i ] ) ; unsigned Dst = VRegs [ i ] ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , F . getCallingConv ( ) , [ & ] ( unsigned Reg , uint64_t Offset ) { if ( ! Split ) { Split = true ; Dst = MRI . createGenericVirtualRegister ( Ty ) ; MIRBuilder . buildUndef ( Dst ) ; } unsigned Tmp = MRI . createGenericVirtualRegister ( Ty ) ; MIRBuilder . buildInsert ( Tmp , Dst , Reg , Offset ) ; Dst = Tmp ; } ) ; if ( Dst != VRegs [ i ] ) MIRBuilder . buildCopy ( VRegs [ i ] , Dst ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; if ( F . isVarArg ( ) ) { if ( ! MF . getSubtarget < AArch64Subtarget > ( ) . isTargetDarwin ( ) ) { return false ; } uint64_t StackOffset = alignTo ( Handler . StackUsed , 8 ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; AArch64FunctionInfo * FuncInfo = MF . getInfo < AArch64FunctionInfo > ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( 4 , StackOffset , true ) ) ; } MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> bool PPCInstrInfo :: isCoalescableExtInstr ( const MachineInstr & MI , Register & SrcReg , Register & DstReg , unsigned & SubIdx ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case PPC :: EXTSW : case PPC :: EXTSW_32 : case PPC :: EXTSW_32_64 : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; DstReg = MI . getOperand ( 0 ) . getReg ( ) ; SubIdx = PPC :: sub_32 ; return true ; } } </s>

isCoalescableExtInstr - Return true if the instruction is a `` coalescable '' extension instruction .


<s> void ia64_split_tmode_move ( rtx operands [ ] ) { rtx in [ 2 ] , out [ 2 ] , insn ; rtx fixup [ 2 ] ; bool dead = false ; bool reversed = false ; if ( GET_CODE ( operands [ 1 ] ) == MEM && reg_overlap_mentioned_p ( operands [ 0 ] , operands [ 1 ] ) ) { rtx base = XEXP ( operands [ 1 ] , 0 ) ; while ( GET_CODE ( base ) != REG ) base = XEXP ( base , 0 ) ; if ( REGNO ( base ) == REGNO ( operands [ 0 ] ) ) reversed = true ; if ( refers_to_regno_p ( REGNO ( operands [ 0 ] ) , REGNO ( operands [ 0 ] ) + 2 , base , 0 ) ) dead = true ; } if ( GET_CODE ( operands [ 0 ] ) == REG && GET_CODE ( operands [ 1 ] ) == REG && REGNO ( operands [ 0 ] ) == REGNO ( operands [ 1 ] ) + 1 ) reversed = true ; fixup [ 0 ] = ia64_split_tmode ( in , operands [ 1 ] , reversed , dead ) ; fixup [ 1 ] = ia64_split_tmode ( out , operands [ 0 ] , reversed , dead ) ; if ( GET_CODE ( EXP ) == MEM \ && ( GET_CODE ( XEXP ( EXP , 0 ) ) == POST_MODIFY \ || GET_CODE ( XEXP ( EXP , 0 ) ) == POST_INC \ || GET_CODE ( XEXP ( EXP , 0 ) ) == POST_DEC ) ) \ add_reg_note ( insn , REG_INC , XEXP ( XEXP ( EXP , 0 ) , 0 ) ) insn = emit_insn ( gen_rtx_SET ( VOIDmode , out [ 0 ] , in [ 0 ] ) ) ; MAYBE_ADD_REG_INC_NOTE ( insn , in [ 0 ] ) ; MAYBE_ADD_REG_INC_NOTE ( insn , out [ 0 ] ) ; insn = emit_insn ( gen_rtx_SET ( VOIDmode , out [ 1 ] , in [ 1 ] ) ) ; MAYBE_ADD_REG_INC_NOTE ( insn , in [ 1 ] ) ; MAYBE_ADD_REG_INC_NOTE ( insn , out [ 1 ] ) ; if ( fixup [ 0 ] ) emit_insn ( fixup [ 0 ] ) ; if ( fixup [ 1 ] ) emit_insn ( fixup [ 1 ] ) ; } </s>

Split a TImode or TFmode move instruction after reload . This is used by * movtf_internal and * movti_internal .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> static bool frv_cannot_force_const_mem ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ATTRIBUTE_UNUSED ) { return TARGET_FDPIC ; } </s>

Decide whether we can force certain constants to memory . If we decide we ca n't , the caller should be able to cope with it in another way . We never allow constants to be forced into memory for TARGET_FDPIC . This is necessary for several reasons : 1 . Since LEGITIMATE_CONSTANT_P rejects constant pool addresses , the target-independent code will try to force them into the constant pool , thus leading to infinite recursion . 2 . We can never introduce new constant pool references during reload . Any such reference would require use of the pseudo FDPIC register . 3 . We ca n't represent a constant added to a function pointer ( which is not the same as a pointer to a function+constant ) . 4 . In many cases , it 's more efficient to calculate the constant in-line .


"Can only insert epilog into returning blocks"


<s>
static
void
cris_print_operand_address
(
FILE
*
file
,
rtx
x
)
{
putc
(
'['
,
file
)
;
if
(
CONSTANT_ADDRESS_P
(
x
)
)
cris_output_addr_const
(
file
,
x
)
;
else
if
(
cris_base_or_autoincr_p
(
x
,
true
)
)
cris_print_base
(
x
,
file
)
;
else
if
(
GET_CODE
(
x
)
==
PLUS
)
{
rtx
x1
,
x2
;
x1
=
XEXP
(
x
,
0
)
;
x2
=
XEXP
(
x
,
1
)
;
if
(
cris_base_p
(
x1
,
true
)
)
{
cris_print_base
(
x1
,
file
)
;
cris_print_index
(
x2
,
file
)
;
}
else
if
(
cris_base_p
(
x2
,
true
)
)
{
cris_print_base
(
x2
,
file
)
;
cris_print_index
(
x1
,
file
)
;
}
else
LOSE_AND_RETURN
(
"unrecognized address"
,
x
)
;
}
else
if
(
MEM_P
(
x
)
)
{
putc
(
'['
,
file
)
;
cris_print_base
(
XEXP
(
x
,
0
)
,
file
)
;
putc
(
']'
,
file
)
;
}
else
LOSE_AND_RETURN
(
"unrecognized address"
,
x
)
;
putc
(
']'
,
file
)
;
}
</s>


<s> MachineBasicBlock :: iterator XCoreInstrInfo :: loadImmediate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned Reg , uint64_t Value ) const { DebugLoc dl ; if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) dl = MI -> getDebugLoc ( ) ; if ( isImmMskBitp ( Value ) ) { int N = Log2_32 ( Value ) + 1 ; return BuildMI ( MBB , MI , dl , get ( XCore :: MKMSK_rus ) , Reg ) . addImm ( N ) . getInstr ( ) ; } if ( isImmU16 ( Value ) ) { int Opcode = isImmU6 ( Value ) ? XCore :: LDC_ru6 : XCore :: LDC_lru6 ; return BuildMI ( MBB , MI , dl , get ( Opcode ) , Reg ) . addImm ( Value ) . getInstr ( ) ; } MachineConstantPool * ConstantPool = MBB . getParent ( ) -> getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) . getContext ( ) ) , Value ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , Align ( 4 ) ) ; return BuildMI ( MBB , MI , dl , get ( XCore :: LDWCP_lru6 ) , Reg ) . addConstantPoolIndex ( Idx ) . getInstr ( ) ; } </s>

Emit a series of instructions to load an immediate .


<s> void emitAssignment ( MCSymbol * Symbol , const MCExpr * Value ) override { if ( Value -> getKind ( ) != MCExpr :: SymbolRef ) return ; const MCSymbol & RhsSym = static_cast < const MCSymbolRefExpr * > ( Value ) -> getSymbol ( ) ; MCSymbolData & Data = getStreamer ( ) . getOrCreateSymbolData ( & RhsSym ) ; MCSymbolData & SymbolData = getStreamer ( ) . getOrCreateSymbolData ( Symbol ) ; unsigned Other = MCELF :: getOther ( SymbolData ) << 2 ; Other &= ~ ELF :: STO_PPC64_LOCAL_MASK ; Other |= ( MCELF :: getOther ( Data ) << 2 ) & ELF :: STO_PPC64_LOCAL_MASK ; MCELF :: setOther ( SymbolData , Other >> 2 ) ; } </s>


<s> bool ARMPassConfig :: addPreEmitPass ( ) { if ( getARMSubtarget ( ) . isThumb2 ( ) ) { if ( ! getARMSubtarget ( ) . prefers32BitThumb ( ) ) addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( & UnpackMachineBundlesID ) ; } if ( getARMSubtarget ( ) . useConstIslands ( ) ) addPass ( createARMConstantIslandPass ( ) ) ; if ( getARMSubtarget ( ) . isTargetNaCl ( ) ) { addPass ( createARMNaClRewritePass ( ) ) ; } return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


Output a BSR instruction suitable for PIC code .


<s> static int distance_agu_use_in_bb ( unsigned int regno , rtx_insn * insn , int distance , rtx_insn * start , bool * found , bool * redefined ) { basic_block bb = NULL ; rtx_insn * next = start ; rtx_insn * prev = NULL ; * found = false ; * redefined = false ; if ( start != NULL_RTX ) { bb = BLOCK_FOR_INSN ( start ) ; if ( start != BB_HEAD ( bb ) ) prev = insn ; } while ( next && next != insn && distance < LEA_SEARCH_THRESHOLD ) { if ( NONDEBUG_INSN_P ( next ) && NONJUMP_INSN_P ( next ) ) { distance = increase_distance ( prev , next , distance ) ; if ( insn_uses_reg_mem ( regno , next ) ) { * found = true ; return distance ; } if ( insn_defines_reg ( regno , INVALID_REGNUM , next ) ) { * redefined = true ; return - 1 ; } prev = next ; } if ( next == BB_END ( bb ) ) break ; next = NEXT_INSN ( next ) ; } return distance ; } </s>

Return the distance in half-cycles between INSN and the next insn that uses register number REGNO in memory address added to DISTANCE . Return -1 if REGNO0 is set . Put true value into * FOUND if register usage was found and false otherwise . Put true value into * REDEFINED if register redefinition was found and false otherwise .


<s> bool SILowerControlFlow :: runOnMachineFunction ( MachineFunction & MF ) { const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; LIS = getAnalysisIfAvailable < LiveIntervals > ( ) ; MRI = & MF . getRegInfo ( ) ; MachineFunction :: iterator NextBB ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; BI = NextBB ) { NextBB = std :: next ( BI ) ; MachineBasicBlock & MBB = * BI ; MachineBasicBlock :: iterator I , Next , Last ; for ( I = MBB . begin ( ) , Last = MBB . end ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; switch ( MI . getOpcode ( ) ) { case AMDGPU :: SI_IF : emitIf ( MI ) ; break ; case AMDGPU :: SI_ELSE : emitElse ( MI ) ; break ; case AMDGPU :: SI_BREAK : emitBreak ( MI ) ; break ; case AMDGPU :: SI_IF_BREAK : emitIfBreak ( MI ) ; break ; case AMDGPU :: SI_ELSE_BREAK : emitElseBreak ( MI ) ; break ; case AMDGPU :: SI_LOOP : emitLoop ( MI ) ; break ; case AMDGPU :: SI_END_CF : emitEndCf ( MI ) ; break ; case AMDGPU :: S_AND_B64 : case AMDGPU :: S_OR_B64 : combineMasks ( MI ) ; Last = I ; continue ; default : Last = I ; continue ; } Next = ( Last == MBB . end ( ) ) ? MBB . begin ( ) : Last ; } } return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool VLIWResourceModel :: isResourceAvailable ( SUnit * SU , bool IsTop ) { if ( ! SU || ! SU -> getInstr ( ) ) return false ; switch ( SU -> getInstr ( ) -> getOpcode ( ) ) { default : if ( ! ResourcesModel -> canReserveResources ( * SU -> getInstr ( ) ) ) return false ; case TargetOpcode :: EXTRACT_SUBREG : case TargetOpcode :: INSERT_SUBREG : case TargetOpcode :: SUBREG_TO_REG : case TargetOpcode :: REG_SEQUENCE : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: COPY : case TargetOpcode :: INLINEASM : break ; } MachineBasicBlock * MBB = SU -> getInstr ( ) -> getParent ( ) ; auto & QST = MBB -> getParent ( ) -> getSubtarget < HexagonSubtarget > ( ) ; const auto & QII = * QST . getInstrInfo ( ) ; if ( IsTop ) { for ( unsigned i = 0 , e = Packet . size ( ) ; i != e ; ++ i ) if ( hasDependence ( Packet [ i ] , SU , QII ) ) return false ; } else { for ( unsigned i = 0 , e = Packet . size ( ) ; i != e ; ++ i ) if ( hasDependence ( SU , Packet [ i ] , QII ) ) return false ; } return true ; } </s>

Check if scheduling of this SU is possible in the current packet .


"Only Linux target is expected to contain LOAD_STACK_GUARD"

This function is called for all pseudo instructions that remain after register allocation .


<s> bool ARMAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { const uint16_t Thumb1_16bitNopEncoding = 0x46c0 ; const uint16_t Thumb2_16bitNopEncoding = 0xbf00 ; const uint32_t ARMv4_NopEncoding = 0xe1a00000 ; const uint32_t ARMv6T2_NopEncoding = 0xe320f000 ; if ( isThumb ( ) ) { const uint16_t nopEncoding = hasNOP ( STI ) ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding ; uint64_t NumNops = Count / 2 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) support :: endian :: write ( OS , nopEncoding , Endian ) ; if ( Count & 1 ) OS << '\0' ; return true ; } const uint32_t nopEncoding = hasNOP ( STI ) ? ARMv6T2_NopEncoding : ARMv4_NopEncoding ; uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) support :: endian :: write ( OS , nopEncoding , Endian ) ; switch ( Count % 4 ) { default : break ; case 1 : OS << '\0' ; break ; case 2 : OS . write ( "\0\0" , 2 ) ; break ; case 3 : OS . write ( "\0\0\xa0" , 3 ) ; break ; } return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> bool RISCVTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { if ( VT == MVT :: f32 && ! Subtarget . hasStdExtF ( ) ) return false ; if ( VT == MVT :: f64 && ! Subtarget . hasStdExtD ( ) ) return false ; if ( Imm . isNegZero ( ) ) return false ; return Imm . isZero ( ) ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> const char * MSP430TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return nullptr ; case MSP430ISD :: RET_FLAG : return "MSP430ISD::RET_FLAG" ; case MSP430ISD :: RETI_FLAG : return "MSP430ISD::RETI_FLAG" ; case MSP430ISD :: RRA : return "MSP430ISD::RRA" ; case MSP430ISD :: RLA : return "MSP430ISD::RLA" ; case MSP430ISD :: RRC : return "MSP430ISD::RRC" ; case MSP430ISD :: CALL : return "MSP430ISD::CALL" ; case MSP430ISD :: Wrapper : return "MSP430ISD::Wrapper" ; case MSP430ISD :: BR_CC : return "MSP430ISD::BR_CC" ; case MSP430ISD :: CMP : return "MSP430ISD::CMP" ; case MSP430ISD :: SELECT_CC : return "MSP430ISD::SELECT_CC" ; case MSP430ISD :: SHL : return "MSP430ISD::SHL" ; case MSP430ISD :: SRA : return "MSP430ISD::SRA" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> int h8300_shift_needs_scratch_p ( int count , machine_mode mode ) { enum h8_cpu cpu ; int a , lr , ar ; if ( GET_MODE_BITSIZE ( mode ) <= count ) return 1 ; if ( TARGET_H8300 ) cpu = H8_300 ; else if ( TARGET_H8300S ) cpu = H8_S ; else cpu = H8_300H ; switch ( mode ) { case QImode : a = shift_alg_qi [ cpu ] [ SHIFT_ASHIFT ] [ count ] ; lr = shift_alg_qi [ cpu ] [ SHIFT_LSHIFTRT ] [ count ] ; ar = shift_alg_qi [ cpu ] [ SHIFT_ASHIFTRT ] [ count ] ; break ; case HImode : a = shift_alg_hi [ cpu ] [ SHIFT_ASHIFT ] [ count ] ; lr = shift_alg_hi [ cpu ] [ SHIFT_LSHIFTRT ] [ count ] ; ar = shift_alg_hi [ cpu ] [ SHIFT_ASHIFTRT ] [ count ] ; break ; case SImode : a = shift_alg_si [ cpu ] [ SHIFT_ASHIFT ] [ count ] ; lr = shift_alg_si [ cpu ] [ SHIFT_LSHIFTRT ] [ count ] ; ar = shift_alg_si [ cpu ] [ SHIFT_ASHIFTRT ] [ count ] ; break ; default : gcc_unreachable ( ) ; } return ( a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP || ( TARGET_H8300H && mode == SImode && count == 8 ) ) ; } </s>

Given COUNT and MODE of a shift , return 1 if a scratch reg may be needed for some shift with COUNT and MODE . Return 0 otherwise .


<s>
const
char
*
nvptx_output_set_softstack
(
unsigned
src_regno
)
{
if
(
cfun
->
machine
->
has_softstack
&&
!
crtl
->
is_leaf
)
{
fprintf
(
asm_out_file
,
"\tst.shared.u%d\t[%s], "
,
POINTER_SIZE
,
reg_names
[
SOFTSTACK_SLOT_REGNUM
]
)
;
output_reg
(
asm_out_file
,
src_regno
,
VOIDmode
)
;
fprintf
(
asm_out_file
,
";\n"
)
;
}
return
""
;
}
</s>

Output instruction that sets soft stack pointer in shared memory to the value in register given by SRC_REGNO .

nvptx
"\tst.shared.u%d\t[%s], "
";\n"
""


<s> int short_immediate_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { if ( GET_CODE ( op ) != CONST_INT ) return 0 ; return SMALL_INT ( INTVAL ( op ) ) ; } </s>

Return true if OP is a short immediate ( shimm ) value .


<s> void copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , MCRegister DstReg , MCRegister SrcReg , bool KillSrc ) const override { copyPhysReg ( MBB , MBBI , DL , DstReg , SrcReg , KillSrc , MachineInstr :: NoFlags ) ; } </s>


<s> bool X86PassConfig :: addRegBankSelect ( ) { return false ; } </s>

This method should install a register bank selector pass , which assigns register banks to virtual registers without a register class or register banks .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Tile Register Configure"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool runOnModule ( Module & M ) { DEBUG ( dbgs ( ) << getPassName ( ) << '\n' ) ; bool Changed = false ; for ( auto & MF : M ) { Changed |= runOnFunction ( MF ) ; } return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> bool isImm ( ) const override { return Kind == k_Immediate ; } </s>


<s> void func_fma_steering :: analyze ( ) { int i , n_blocks , * bb_dfs_preorder ; basic_block bb ; rtx_insn * insn ; bb_dfs_preorder = XNEWVEC ( int , last_basic_block_for_fn ( cfun ) ) ; n_blocks = pre_and_rev_post_order_compute ( bb_dfs_preorder , NULL , false ) ; for ( i = 0 ; i < n_blocks ; i ++ ) { bb = BASIC_BLOCK_FOR_FN ( cfun , bb_dfs_preorder [ i ] ) ; FOR_BB_INSNS ( bb , insn ) { operand_rr_info * dest_op_info ; struct du_chain * chain ; unsigned dest_regno ; fma_forest * forest ; du_head_p head ; int i ; if ( ! is_fmul_fmac_insn ( insn , true ) ) continue ; dest_op_info = insn_rr [ INSN_UID ( insn ) ] . op_info ; dest_regno = REGNO ( SET_DEST ( PATTERN ( insn ) ) ) ; for ( i = 0 ; i < dest_op_info -> n_chains ; i ++ ) { if ( dest_op_info -> heads [ i ] -> regno != dest_regno ) continue ; head = dest_op_info -> heads [ i ] ; if ( ! head -> first ) head = regrename_chain_from_id ( head -> id ) ; forest = NULL ; for ( chain = head -> first ; chain ; chain = chain -> next_use ) { fma_node * * fma_slot ; if ( ! is_fmul_fmac_insn ( chain -> insn , true ) ) continue ; if ( chain -> loc != & SET_DEST ( PATTERN ( chain -> insn ) ) ) continue ; if ( chain -> insn == insn ) break ; fma_slot = this -> m_insn_fma_head_map -> get ( chain -> insn ) ; if ( fma_slot && ( * fma_slot ) -> get_children ( ) ) forest = ( * fma_slot ) -> get_forest ( ) ; } if ( chain ) break ; } gcc_assert ( i < dest_op_info -> n_chains ) ; this -> analyze_fma_fmul_insn ( forest , chain , head ) ; } } free ( bb_dfs_preorder ) ; if ( dump_file ) this -> dfs ( dump_forest_info , dump_tree_root_info , dump_tree_node_info , false ) ; } </s>

Count how many times each regno is referenced as base address for a memory access .


<s>
static
int
write_arg_mode
(
std
::
stringstream
&
s
,
int
for_reg
,
int
argno
,
machine_mode
mode
)
{
const
char
*
ptx_type
=
nvptx_ptx_type_from_mode
(
mode
,
false
)
;
if
(
for_reg
<
0
)
{
s
<<
(
argno
", "
:
" ("
)
;
s
<<
".param"
<<
ptx_type
<<
" %in_ar"
<<
argno
;
}
else
{
s
<<
"\t.reg"
<<
ptx_type
<<
" "
;
if
(
for_reg
)
s
<<
reg_names
[
for_reg
]
;
else
s
<<
"%ar"
<<
argno
;
s
<<
";\n"
;
if
(
argno
>=
0
)
{
s
<<
"\tld.param"
<<
ptx_type
<<
" "
;
if
(
for_reg
)
s
<<
reg_names
[
for_reg
]
;
else
s
<<
"%ar"
<<
argno
;
s
<<
", [%in_ar"
<<
argno
<<
"];\n"
;
}
}
return
argno
+
1
;
}
</s>

Helper for write_arg . Emit a single PTX argument of MODE , either in a prototype , or as copy in a function prologue . ARGNO is the index of this argument in the PTX function . FOR_REG is negative , if we 're emitting the PTX prototype . It is zero if we 're copying to an argument register and it is greater than zero if we 're copying to a specific hard register .


"argument to %qs must be a 2-bit unsigned literal"


<s> bool HSAILPassConfig :: addPreISel ( ) { addPass ( createLCSSAPass ( ) ) ; return true ; } </s>


<s> bool AMDGPUMCAsmInfo :: shouldOmitSectionDirective ( StringRef SectionName ) const { return SectionName == ".hsatext" || SectionName == ".hsadata_global_agent" || SectionName == ".hsadata_global_program" || SectionName == ".hsarodata_readonly_agent" || MCAsmInfo :: shouldOmitSectionDirective ( SectionName ) ; } </s>

Return true if the .section directive should be omitted when emitting SectionName .


<s> static bool arc_enter_leave_p ( unsigned int gmask ) { int regno ; unsigned int rmask = 0 ; if ( ! gmask ) return false ; for ( regno = ENTER_LEAVE_START_REG ; regno <= ENTER_LEAVE_END_REG && ( gmask & ( 1L << regno ) ) ; regno ++ ) rmask |= 1L << regno ; if ( rmask ^ gmask ) return false ; return true ; } </s>

Check if we have a continous range to be save/restored with the help of enter/leave instructions . A vaild register range starts from $ r13 and is up to ( including ) $ r26 .


<s> static bool arm_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( GET_MODE_CLASS ( mode ) == MODE_CC ) return ( regno == CC_REGNUM || ( TARGET_VFP_BASE && regno == VFPCC_REGNUM ) ) ; if ( regno == CC_REGNUM && GET_MODE_CLASS ( mode ) != MODE_CC ) return false ; if ( IS_VPR_REGNUM ( regno ) ) return mode == HImode || mode == V16BImode || mode == V8BImode || mode == V4BImode ; if ( TARGET_THUMB1 ) return ( ARM_NUM_REGS ( mode ) < 2 ) || ( regno < LAST_LO_REGNUM ) ; if ( TARGET_VFP_BASE && IS_VFP_REGNUM ( regno ) ) { if ( mode == DFmode || mode == DImode ) return VFP_REGNO_OK_FOR_DOUBLE ( regno ) ; if ( mode == HFmode || mode == BFmode || mode == HImode || mode == SFmode || mode == SImode ) return VFP_REGNO_OK_FOR_SINGLE ( regno ) ; if ( TARGET_NEON ) return ( VALID_NEON_DREG_MODE ( mode ) && VFP_REGNO_OK_FOR_DOUBLE ( regno ) ) || ( VALID_NEON_QREG_MODE ( mode ) && NEON_REGNO_OK_FOR_QUAD ( regno ) ) || ( mode == TImode && NEON_REGNO_OK_FOR_NREGS ( regno , 2 ) ) || ( mode == EImode && NEON_REGNO_OK_FOR_NREGS ( regno , 3 ) ) || ( mode == OImode && NEON_REGNO_OK_FOR_NREGS ( regno , 4 ) ) || ( mode == CImode && NEON_REGNO_OK_FOR_NREGS ( regno , 6 ) ) || ( mode == XImode && NEON_REGNO_OK_FOR_NREGS ( regno , 8 ) ) ; if ( TARGET_HAVE_MVE ) return ( ( VALID_MVE_MODE ( mode ) && NEON_REGNO_OK_FOR_QUAD ( regno ) ) || ( mode == OImode && NEON_REGNO_OK_FOR_NREGS ( regno , 4 ) ) || ( mode == XImode && NEON_REGNO_OK_FOR_NREGS ( regno , 8 ) ) ) ; return false ; } if ( TARGET_REALLY_IWMMXT ) { if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return mode == SImode ; if ( IS_IWMMXT_REGNUM ( regno ) ) return VALID_IWMMXT_REG_MODE ( mode ) ; } if ( regno <= LAST_ARM_REGNUM ) { if ( ARM_NUM_REGS ( mode ) > 4 ) return false ; if ( TARGET_THUMB2 && ! ( TARGET_HAVE_MVE || TARGET_CDE ) ) return true ; return ! ( ( TARGET_LDRD || TARGET_CDE ) && GET_MODE_SIZE ( mode ) > 4 && ( regno & 1 ) != 0 ) ; } if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return GET_MODE_CLASS ( mode ) == MODE_INT ; return false ; } </s>

Returns true if REGNO is a valid register for holding a quantity of type MODE .


"function attributes %qs, %qs and %qs are mutually"

"%qs appears to be a misspelled %s handler"

Sanity cheching for above function attributes .


<s> bool AMDGPUPropagateAttributesLate :: runOnModule ( Module & M ) { if ( ! TM ) return false ; return AMDGPUPropagateAttributes ( TM , true ) . process ( M ) ; } </s>


<s> static bool mips_vector_mode_supported_p ( machine_mode mode ) { switch ( mode ) { case V2SFmode : return TARGET_PAIRED_SINGLE_FLOAT ; case V2HImode : case V4QImode : case V2HQmode : case V2UHQmode : case V2HAmode : case V2UHAmode : case V4QQmode : case V4UQQmode : return TARGET_DSP ; case V2SImode : case V4HImode : case V8QImode : return TARGET_LOONGSON_VECTORS ; default : return false ; } } </s>

Target hook for vector_mode_supported_p .


<s> void NVPTXFrameLowering :: emitPrologue ( MachineFunction & MF ) const { if ( MF . getFrameInfo ( ) -> hasStackObjects ( ) ) { MachineBasicBlock & MBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = DebugLoc ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( is64bit ) { unsigned LocalReg = MRI . createVirtualRegister ( & NVPTX :: Int64RegsRegClass ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , dl , tm . getInstrInfo ( ) -> get ( NVPTX :: cvta_local_yes_64 ) , NVPTX :: VRFrame ) . addReg ( LocalReg ) ; BuildMI ( MBB , MI , dl , tm . getInstrInfo ( ) -> get ( NVPTX :: MOV_DEPOT_ADDR_64 ) , LocalReg ) . addImm ( MF . getFunctionNumber ( ) ) ; } else { unsigned LocalReg = MRI . createVirtualRegister ( & NVPTX :: Int32RegsRegClass ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , dl , tm . getInstrInfo ( ) -> get ( NVPTX :: cvta_local_yes ) , NVPTX :: VRFrame ) . addReg ( LocalReg ) ; BuildMI ( MBB , MI , dl , tm . getInstrInfo ( ) -> get ( NVPTX :: MOV_DEPOT_ADDR ) , LocalReg ) . addImm ( MF . getFunctionNumber ( ) ) ; } } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> virtual ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const { return createVLIWMachineSched ( C ) ; } </s>

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level .