<s> bool runOnMachineFunction ( MachineFunction & MF ) override { ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( AFI -> getGlobalBaseReg ( ) == 0 ) return false ; const ARMSubtarget & STI = static_cast < const ARMSubtarget & > ( MF . getSubtarget ( ) ) ; if ( STI . isThumb1Only ( ) ) return false ; const TargetMachine & TM = MF . getTarget ( ) ; if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) return false ; LLVMContext * Context = & MF . getFunction ( ) -> getContext ( ) ; unsigned ARMPCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = STI . isThumb ( ) ? 4 : 8 ; ARMConstantPoolValue * CPV = ARMConstantPoolSymbol :: Create ( * Context , "_GLOBAL_OFFSET_TABLE_" , ARMPCLabelIndex , PCAdj ) ; unsigned Align = MF . getDataLayout ( ) . getPrefTypeAlignment ( Type :: getInt32PtrTy ( * Context ) ) ; unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned TempReg = MF . getRegInfo ( ) . createVirtualRegister ( & ARM :: rGPRRegClass ) ; unsigned Opc = STI . isThumb2 ( ) ? ARM :: t2LDRpci : ARM :: LDRcp ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , TempReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == ARM :: LDRcp ) MIB . addImm ( 0 ) ; AddDefaultPred ( MIB ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; Opc = STI . isThumb2 ( ) ? ARM :: tPICADD : ARM :: PICADD ; MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addReg ( TempReg ) . addImm ( ARMPCLabelIndex ) ; if ( Opc == ARM :: PICADD ) AddDefaultPred ( MIB ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .

ARM ARM ARM 0 ARM ARM ARM 4 8 ARM ARM "_GLOBAL_OFFSET_TABLE_" ARM ARM::rGPRRegClass ARM::t2LDRpci ARM::LDRcp ARM::LDRcp 0 ARM::tPICADD ARM::PICADD ARM ARM::PICADD


<s> unsigned getNumFixupKinds ( ) const override { return MMIX :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> bool NVPTXFavorNonGenericAddrSpaces :: runOnFunction ( Function & F ) { if ( DisableFavorNonGeneric ) return false ; bool Changed = false ; for ( Function :: iterator B = F . begin ( ) , BE = F . end ( ) ; B != BE ; ++ B ) { for ( BasicBlock :: iterator I = B -> begin ( ) , IE = B -> end ( ) ; I != IE ; ++ I ) { if ( isa < LoadInst > ( I ) ) { Changed |= optimizeMemoryInstruction ( I , 0 ) ; } else if ( isa < StoreInst > ( I ) ) { Changed |= optimizeMemoryInstruction ( I , 1 ) ; } } } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool SPIRVEmitIntrinsics :: runOnFunction ( Function & Func ) { if ( Func . isDeclaration ( ) ) return false ; F = & Func ; IRB = new IRBuilder < > ( Func . getContext ( ) ) ; AggrConsts . clear ( ) ; AggrStores . clear ( ) ; for ( auto & I : instructions ( Func ) ) { StoreInst * SI = dyn_cast < StoreInst > ( & I ) ; if ( ! SI ) continue ; Type * ElTy = SI -> getValueOperand ( ) -> getType ( ) ; PointerType * PTy = cast < PointerType > ( SI -> getOperand ( 1 ) -> getType ( ) ) ; if ( ElTy -> isAggregateType ( ) || ElTy -> isVectorTy ( ) || ! PTy -> isOpaqueOrPointeeTypeMatches ( ElTy ) ) AggrStores . insert ( & I ) ; } IRB -> SetInsertPoint ( & Func . getEntryBlock ( ) . front ( ) ) ; for ( auto & GV : Func . getParent ( ) -> globals ( ) ) processGlobalValue ( GV ) ; preprocessCompositeConstants ( ) ; SmallVector < Instruction * > Worklist ; for ( auto & I : instructions ( Func ) ) Worklist . push_back ( & I ) ; for ( auto & I : Worklist ) insertAssignTypeIntrs ( I ) ; for ( auto * I : Worklist ) { TrackConstants = true ; if ( ! I -> getType ( ) -> isVoidTy ( ) || isa < StoreInst > ( I ) ) IRB -> SetInsertPoint ( I -> getNextNode ( ) ) ; I = visit ( * I ) ; processInstrAfterVisit ( I ) ; } return true ; } </s>


<s>
bool
AArch64A53Fix835769
::
runOnMachineFunction
(
MachineFunction
&
F
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"***** AArch64A53Fix835769 *****\n"
)
;
auto
&
STI
=
F
.
getSubtarget
<
AArch64Subtarget
>
(
)
;
if
(
!
STI
.
fixCortexA53_835769
(
)
)
return
false
;
bool
Changed
=
false
;
TII
=
STI
.
getInstrInfo
(
)
;
for
(
auto
&
MBB
:
F
)
{
Changed
|=
runOnBasicBlock
(
MBB
)
;
}
return
Changed
;
}
</s>


<s> StringRef getPassName ( ) const override { return FIXUPLEA_DESC ; } </s>

getPassName - Return a nice clean name for a pass .


<s> static struct machine_function * msp430_init_machine_status ( void ) { struct machine_function * m ; m = ggc_cleared_alloc < machine_function > ( ) ; return m ; } </s>

This is our init_machine_status , as set in msp_option_override .


<s>
TargetTransformInfo
::
PopcntSupportKind
PPCTTIImpl
::
getPopcntSupport
(
unsigned
TyWidth
)
{
assert
(
isPowerOf2_32
(
TyWidth
)
&&
"Ty width must be power of 2"
)
;
if
(
ST
->
hasPOPCNTD
(
)
!=
PPCSubtarget
::
POPCNTD_Unavailable
&&
TyWidth
<=
64
)
return
ST
->
hasPOPCNTD
(
)
==
PPCSubtarget
::
POPCNTD_Slow
TTI
::
PSK_SlowHardware
:
TTI
::
PSK_FastHardware
;
return
TTI
::
PSK_Software
;
}
</s>

Return hardware support for population count .

PowerPC
PPC
"Ty width must be power of 2"
PPC
64
PPC


<s> bool X86InstrInfo :: isCopyInstrImpl ( const MachineInstr & MI , const MachineOperand * & Src , const MachineOperand * & Dest ) const { if ( MI . isMoveReg ( ) ) { Dest = & MI . getOperand ( 0 ) ; Src = & MI . getOperand ( 1 ) ; return true ; } return false ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


<s> static int ix86_vec_cost ( machine_mode mode , int cost ) { if ( ! VECTOR_MODE_P ( mode ) ) return cost ; if ( GET_MODE_BITSIZE ( mode ) == 128 && TARGET_SSE_SPLIT_REGS ) return cost * 2 ; if ( GET_MODE_BITSIZE ( mode ) > 128 && TARGET_AVX128_OPTIMAL ) return cost * GET_MODE_BITSIZE ( mode ) / 128 ; return cost ; } </s>

Return cost of vector operation in MODE given that scalar version has COST . If PARALLEL is true assume that CPU has more than one unit performing the operation .


<s> static unsigned int arc_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( GET_MODE_SIZE ( mode ) == 16 && regno >= ARC_FIRST_SIMD_VR_REG && regno <= ARC_LAST_SIMD_VR_REG ) return 1 ; return CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ; } </s>


<s> param_iterator arg_end ( ) const { return ArgumentParams . end ( ) ; } </s>

Return the iterator pointing to the end of the argument list .


<s> BitVector AArch64RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const AArch64FrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , AArch64 :: WSP ) ; markSuperRegs ( Reserved , AArch64 :: WZR ) ; if ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) markSuperRegs ( Reserved , AArch64 :: W29 ) ; for ( size_t i = 0 ; i < AArch64 :: GPR32commonRegClass . getNumRegs ( ) ; ++ i ) { if ( MF . getSubtarget < AArch64Subtarget > ( ) . isXRegisterReserved ( i ) ) markSuperRegs ( Reserved , AArch64 :: GPR32commonRegClass . getRegister ( i ) ) ; } if ( hasBasePointer ( MF ) ) markSuperRegs ( Reserved , AArch64 :: W19 ) ; if ( MF . getFunction ( ) . hasFnAttribute ( Attribute :: SpeculativeLoadHardening ) ) markSuperRegs ( Reserved , AArch64 :: W16 ) ; if ( PACStack :: hasPACStackAttribute ( MF ) ) markSuperRegs ( Reserved , PACStack :: CRSub ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
static
tree
spu_handle_vector_attribute
(
tree
*
node
,
tree
name
,
tree
args
ATTRIBUTE_UNUSED
,
int
flags
ATTRIBUTE_UNUSED
,
bool
*
no_add_attrs
)
{
tree
type
=
*
node
,
result
=
NULL_TREE
;
machine_mode
mode
;
int
unsigned_p
;
while
(
POINTER_TYPE_P
(
type
)
||
TREE_CODE
(
type
)
==
FUNCTION_TYPE
||
TREE_CODE
(
type
)
==
METHOD_TYPE
||
TREE_CODE
(
type
)
==
ARRAY_TYPE
)
type
=
TREE_TYPE
(
type
)
;
mode
=
TYPE_MODE
(
type
)
;
unsigned_p
=
TYPE_UNSIGNED
(
type
)
;
switch
(
mode
)
{
case
DImode
:
result
=
(
unsigned_p
unsigned_V2DI_type_node
:
V2DI_type_node
)
;
break
;
case
SImode
:
result
=
(
unsigned_p
unsigned_V4SI_type_node
:
V4SI_type_node
)
;
break
;
case
HImode
:
result
=
(
unsigned_p
unsigned_V8HI_type_node
:
V8HI_type_node
)
;
break
;
case
QImode
:
result
=
(
unsigned_p
unsigned_V16QI_type_node
:
V16QI_type_node
)
;
break
;
case
SFmode
:
result
=
V4SF_type_node
;
break
;
case
DFmode
:
result
=
V2DF_type_node
;
break
;
default
:
break
;
}
if
(
result
&&
result
!=
type
&&
TYPE_QUALS
(
type
)
)
result
=
build_qualified_type
(
result
,
TYPE_QUALS
(
type
)
)
;
*
no_add_attrs
=
true
;
if
(
!
result
)
warning
(
0
,
"%qE attribute ignored"
,
name
)
;
else
*
node
=
lang_hooks
.
types
.
reconstruct_complex_type
(
*
node
,
result
)
;
return
NULL_TREE
;
}
</s>


<s> static void emit_v9_brxx_insn ( enum rtx_code code , rtx op0 , rtx label ) { emit_jump_insn ( gen_rtx_SET ( pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ) ) ; } </s>

Emit a conditional jump insn for the v9 architecture using comparison code CODE and jump target LABEL . This function exists to take advantage of the v9 brxx insns .


"MMIX Internal: This is not a constant:"

Return the bit-value for a const_int or const_double .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < MachinePostDominatorTree > ( ) ; AU . addRequired < MachineBlockFrequencyInfo > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addPreserved < MachinePostDominatorTree > ( ) ; AU . addPreserved < MachineBlockFrequencyInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
void
MipsInstPrinter
::
printInst
(
const
MCInst
*
MI
,
uint64_t
Address
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
,
raw_ostream
&
O
)
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
Mips
::
RDHWR
:
case
Mips
::
RDHWR64
:
O
<<
"\t.set\tpush\n"
;
O
<<
"\t.set\tmips32r2\n"
;
break
;
case
Mips
::
Save16
:
O
<<
"\tsave\t"
;
printSaveRestore
(
MI
,
STI
,
O
)
;
O
<<
" # 16 bit inst\n"
;
return
;
case
Mips
::
SaveX16
:
O
<<
"\tsave\t"
;
printSaveRestore
(
MI
,
STI
,
O
)
;
O
<<
"\n"
;
return
;
case
Mips
::
Restore16
:
O
<<
"\trestore\t"
;
printSaveRestore
(
MI
,
STI
,
O
)
;
O
<<
" # 16 bit inst\n"
;
return
;
case
Mips
::
RestoreX16
:
O
<<
"\trestore\t"
;
printSaveRestore
(
MI
,
STI
,
O
)
;
O
<<
"\n"
;
return
;
}
if
(
!
printAliasInstr
(
MI
,
Address
,
STI
,
O
)
&&
!
printAlias
(
*
MI
,
Address
,
STI
,
O
)
)
printInstruction
(
MI
,
Address
,
STI
,
O
)
;
printAnnotation
(
O
,
Annot
)
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
Mips
::
RDHWR
:
case
Mips
::
RDHWR64
:
O
<<
"\n\t.set\tpop"
;
}
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s>
void
AMDGPUAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
)
const
{
switch
(
(
unsigned
)
Fixup
.
getKind
(
)
)
{
case
AMDGPU
::
fixup_si_sopp_br
:
{
uint16_t
*
Dst
=
(
uint16_t
*
)
(
Data
+
Fixup
.
getOffset
(
)
)
;
*
Dst
=
(
Value
4
)
/
4
;
break
;
}
case
AMDGPU
::
fixup_si_rodata
:
{
uint32_t
*
Dst
=
(
uint32_t
*
)
(
Data
+
Fixup
.
getOffset
(
)
)
;
*
Dst
=
Value
+
4
;
break
;
}
default
:
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> const char * MSP430TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( MSP430ISD :: NodeType ) Opcode ) { case MSP430ISD :: FIRST_NUMBER : break ; case MSP430ISD :: RET_FLAG : return "MSP430ISD::RET_FLAG" ; case MSP430ISD :: RETI_FLAG : return "MSP430ISD::RETI_FLAG" ; case MSP430ISD :: RRA : return "MSP430ISD::RRA" ; case MSP430ISD :: RLA : return "MSP430ISD::RLA" ; case MSP430ISD :: RRC : return "MSP430ISD::RRC" ; case MSP430ISD :: RRCL : return "MSP430ISD::RRCL" ; case MSP430ISD :: CALL : return "MSP430ISD::CALL" ; case MSP430ISD :: Wrapper : return "MSP430ISD::Wrapper" ; case MSP430ISD :: BR_CC : return "MSP430ISD::BR_CC" ; case MSP430ISD :: CMP : return "MSP430ISD::CMP" ; case MSP430ISD :: SETCC : return "MSP430ISD::SETCC" ; case MSP430ISD :: SELECT_CC : return "MSP430ISD::SELECT_CC" ; case MSP430ISD :: DADD : return "MSP430ISD::DADD" ; case MSP430ISD :: RRAM : return "MSP430ISD::RRAM" ; case MSP430ISD :: RRUM : return "MSP430ISD::RRUM" ; case MSP430ISD :: RLAM : return "MSP430ISD::RLAM" ; case MSP430ISD :: RRAX : return "MSP430ISD::RRAX" ; case MSP430ISD :: RLAX : return "MSP430ISD::RLAX" ; case MSP430ISD :: RRUX : return "MSP430ISD::RRUX" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> unsigned AMDGPURegisterBankInfo :: copyCost ( const RegisterBank & Dst , const RegisterBank & Src , unsigned Size ) const { if ( Dst . getID ( ) == AMDGPU :: SGPRRegBankID && isVectorRegisterBank ( Src ) ) { return std :: numeric_limits < unsigned > :: max ( ) ; } if ( Size == 1 && ( Dst . getID ( ) == AMDGPU :: SGPRRegBankID ) && ( isVectorRegisterBank ( Src ) || Src . getID ( ) == AMDGPU :: SGPRRegBankID || Src . getID ( ) == AMDGPU :: VCCRegBankID ) ) return std :: numeric_limits < unsigned > :: max ( ) ; if ( Src . getID ( ) == AMDGPU :: VCCRegBankID ) return std :: numeric_limits < unsigned > :: max ( ) ; if ( Dst . getID ( ) == AMDGPU :: AGPRRegBankID && Src . getID ( ) == AMDGPU :: AGPRRegBankID ) return 4 ; return RegisterBankInfo :: copyCost ( Dst , Src , Size ) ; } </s>

Get the cost of a copy from B to A , or put differently , get the cost of A = COPY B .

AMDGPU AMDGPU AMDGPU::SGPRRegBankID 1 AMDGPU::SGPRRegBankID AMDGPU::SGPRRegBankID AMDGPU::VCCRegBankID AMDGPU::VCCRegBankID AMDGPU::AGPRRegBankID AMDGPU::AGPRRegBankID 4


<s>
bool
PPCCTRLoopsVerify
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
for
(
MachineFunction
::
iterator
I
=
MF
.
begin
(
)
,
IE
=
MF
.
end
(
)
;
I
!=
IE
;
++
I
)
{
MachineBasicBlock
*
MBB
=
I
;
if
(
!
MDT
->
isReachableFromEntry
(
MBB
)
)
continue
;
for
(
MachineBasicBlock
::
iterator
MII
=
MBB
->
getFirstTerminator
(
)
,
MIIE
=
MBB
->
end
(
)
;
MII
!=
MIIE
;
++
MII
)
{
unsigned
Opc
=
MII
->
getOpcode
(
)
;
if
(
Opc
==
PPC
::
BDNZ8
||
Opc
==
PPC
::
BDNZ
||
Opc
==
PPC
::
BDZ8
||
Opc
==
PPC
::
BDZ
)
if
(
!
verifyCTRBranch
(
MBB
,
MII
)
)
llvm_unreachable
(
"Invalid PPC CTR loop!"
)
;
}
}
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .

PowerPC
PPC
PPC::BDNZ8
PPC::BDNZ
PPC::BDZ8
PPC::BDZ
"Invalid PPC CTR loop!"


<s> bool WebAssemblyTargetLowering :: allowsMisalignedMemoryAccesses ( EVT , unsigned , unsigned , bool * Fast ) const { if ( Fast ) * Fast = true ; return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> void WebAssemblyPassConfig :: addPreSched2 ( ) { } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> void ARMPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createMVETPAndVPTOptimisationsPass ( ) ) ; addPass ( createMLxExpansionPass ( ) ) ; if ( EnableARMLoadStoreOpt ) addPass ( createARMLoadStoreOptimizationPass ( true ) ) ; if ( ! DisableA15SDOptimization ) addPass ( createA15SDOptimizerPass ( ) ) ; } } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
PPC
::
NumTargetFixupKinds
]
=
{
{
"fixup_ppc_br24"
,
6
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_brcond14"
,
16
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_lo16"
,
16
,
16
,
0
}
,
{
"fixup_ppc_ha16"
,
16
,
16
,
0
}
,
{
"fixup_ppc_lo14"
,
16
,
14
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> static bool s390_scalar_mode_supported_p ( scalar_mode mode ) { if ( ! TARGET_64BIT && TARGET_ZARCH && mode == TImode ) return false ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) return default_decimal_float_supported_p ( ) ; return default_scalar_mode_supported_p ( mode ) ; } </s>

Return true if the back end supports mode MODE .


<s> void function_builder :: add_unique_function ( const function_instance & instance , tree return_type , vec < tree > & argument_types , aarch64_feature_flags required_extensions , bool force_direct_overloads ) { char * name = get_name ( instance , false ) ; tree fntype = build_function_type_array ( return_type , argument_types . length ( ) , argument_types . address ( ) ) ; tree attrs = get_attributes ( instance ) ; registered_function & rfn = add_function ( instance , name , fntype , attrs , required_extensions , false , false ) ; hashval_t hash = instance . hash ( ) ; registered_function * * rfn_slot = function_table -> find_slot_with_hash ( instance , hash , INSERT ) ; gcc_assert ( ! * rfn_slot ) ; * rfn_slot = & rfn ; char * overload_name = get_name ( instance , true ) ; if ( strcmp ( name , overload_name ) != 0 ) { tree attrs = get_attributes ( instance ) ; bool placeholder_p = ! ( m_direct_overloads || force_direct_overloads ) ; add_function ( instance , overload_name , fntype , attrs , required_extensions , false , placeholder_p ) ; } obstack_free ( & m_string_obstack , name ) ; } </s>

Add a built-in function for INSTANCE , with the argument types given by ARGUMENT_TYPES and the return type given by RETURN_TYPE . NAME is the `` full '' name for C function . OVERLOAD_NAME is the `` short '' name for C++ overloaded function . OVERLOAD_NAME can be nullptr because some instance does n't have C++ overloaded function .


<s>
SDValue
VETargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
assert
(
!
IsVarArg
&&
"TODO implement var args"
)
;
assert
(
Outs
.
empty
(
)
&&
"TODO implement return values"
)
;
assert
(
OutVals
.
empty
(
)
&&
"TODO implement return values"
)
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
RetOps
[
0
]
=
Chain
;
return
DAG
.
getNode
(
VEISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


"Only base registers and frame indices are supported."

Returns true if the two given memory operations should be scheduled adjacent .


<s>
static
bool
aarch64_rtx_costs_wrapper
(
rtx
x
,
machine_mode
mode
,
int
outer
,
int
param
,
int
*
cost
,
bool
speed
)
{
bool
result
=
aarch64_rtx_costs
(
x
,
mode
,
outer
,
param
,
cost
,
speed
)
;
if
(
dump_file
&&
flag_aarch64_verbose_cost
)
{
print_rtl_single
(
dump_file
,
x
)
;
fprintf
(
dump_file
,
"\n%s cost: %d (%s)\n"
,
speed
"Hot"
:
"Cold"
,
*
cost
,
result
"final"
:
"partial"
)
;
}
return
result
;
}
</s>

Wrapper around aarch64_rtx_costs , dumps the partial , or total cost calculated for X . This cost is stored in * COST . Returns true if the total cost of X was calculated .

aarch64
"\n%s cost: %d (%s)\n"
"Hot"
"Cold"
"final"
"partial"


<s> bool CSKYPassConfig :: addInstSelector ( ) { addPass ( createCSKYISelDag ( getCSKYTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool AMDGPUArgumentUsageInfo :: doInitialization ( Module & M ) { return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> BitVector XNCMRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( XNCM :: IP ) ; Reserved . set ( XNCM :: SP ) ; Reserved . set ( XNCM :: LR ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void M88kFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; if ( MFFrame . hasCalls ( ) ) SavedRegs . set ( M88k :: R1 ) ; if ( hasFP ( MF ) ) SavedRegs . set ( M88k :: R30 ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> bool isReg ( ) const override { return Kind == k_Register ; } </s>


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: CreateImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ; } </s>


<s> void mprocRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , RegScavenger * RS ) const { } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> const OR1KSubtarget * getSubtargetImpl ( const Function & F ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool Thumb2SizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { const TargetMachine & TM = MF . getTarget ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; STI = & TM . getSubtarget < ARMSubtarget > ( ) ; AttributeSet FnAttrs = MF . getFunction ( ) -> getAttributes ( ) ; OptimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; MinimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; ReversePostOrderTraversal < MachineFunction * > RPOT ( & MF ) ; bool Modified = false ; for ( ReversePostOrderTraversal < MachineFunction * > :: rpo_iterator I = RPOT . begin ( ) , E = RPOT . end ( ) ; I != E ; ++ I ) Modified |= ReduceMBB ( * * I ) ; return Modified ; } </s>


<s> bool HexagonRegisterAliasInfo :: covers ( const RegisterSet & RRs , RegisterRef RR ) const { if ( RRs . count ( RR ) ) return true ; if ( ! TargetRegisterInfo :: isPhysicalRegister ( RR . Reg ) ) { assert ( TargetRegisterInfo :: isVirtualRegister ( RR . Reg ) ) ; bool HasLo = RRs . count ( { RR . Reg , Hexagon :: subreg_loreg } ) ; bool HasHi = RRs . count ( { RR . Reg , Hexagon :: subreg_hireg } ) ; if ( HasLo && HasHi ) return true ; } if ( RR . Sub == 0 ) { unsigned Lo = TRI . getSubReg ( RR . Reg , Hexagon :: subreg_loreg ) ; unsigned Hi = TRI . getSubReg ( RR . Reg , Hexagon :: subreg_hireg ) ; if ( RRs . count ( { Lo , 0 } ) && RRs . count ( { Hi , 0 } ) ) return true ; } return RegisterAliasInfo :: covers ( RRs , RR ) ; } </s>

Check whether this register bank covers RC .


<s> int i386_pe_dllexport_name_p ( const char * symbol ) { return ( strncmp ( DLL_EXPORT_PREFIX , symbol , strlen ( DLL_EXPORT_PREFIX ) ) == 0 ) ; } </s>

Return nonzero if SYMBOL is marked as being dllexport 'd .


<s> const TargetRegisterInfo * getRegisterInfo ( ) const { return subtarget . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static bool s390_pass_by_reference ( cumulative_args_t ca ATTRIBUTE_UNUSED , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { int size = s390_function_arg_size ( mode , type ) ; if ( s390_function_arg_vector ( mode , type ) ) return false ; if ( size > 8 ) return true ; if ( type ) { if ( AGGREGATE_TYPE_P ( type ) && exact_log2 ( size ) < 0 ) return true ; if ( TREE_CODE ( type ) == COMPLEX_TYPE || TREE_CODE ( type ) == VECTOR_TYPE ) return true ; } return false ; } </s>

Return 1 if a function argument of type TYPE and mode MODE is to be passed by reference . The ABI specifies that only structures of size 1 , 2 , 4 , or 8 bytes are passed by value , all other structures ( and complex numbers ) are passed by reference .


"fixed register %s used to pass parameter to function"

Update the summarizer variable CUM to advance past an argument in the argument list .


<s>
CCAssignFn
*
AArch64TargetLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
const
{
switch
(
CC
)
{
default
:
report_fatal_error
(
"Unsupported calling convention."
)
;
case
CallingConv
::
WebKit_JS
:
return
CC_AArch64_WebKit_JS
;
case
CallingConv
::
GHC
:
return
CC_AArch64_GHC
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
case
CallingConv
::
PreserveMost
:
case
CallingConv
::
CXX_FAST_TLS
:
case
CallingConv
::
Swift
:
if
(
Subtarget
->
isTargetWindows
(
)
&&
IsVarArg
)
return
CC_AArch64_Win64_VarArg
;
if
(
!
Subtarget
->
isTargetDarwin
(
)
)
return
CC_AArch64_AAPCS
;
if
(
!
IsVarArg
)
return
CC_AArch64_DarwinPCS
;
return
Subtarget
->
isTargetILP32
(
)
CC_AArch64_DarwinPCS_ILP32_VarArg
:
CC_AArch64_DarwinPCS_VarArg
;
case
CallingConv
::
Win64
:
return
IsVarArg
CC_AArch64_Win64_VarArg
:
CC_AArch64_AAPCS
;
case
CallingConv
::
CFGuard_Check
:
return
CC_AArch64_Win64_CFGuard_Check
;
case
CallingConv
::
AArch64_VectorCall
:
return
CC_AArch64_AAPCS
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .


"ADJSTACKDOWN and ADJSTACKUP should be no-ops"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


"CPU0 DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s>
StringRef
getPassName
(
)
const
override
{
return
"TVM Lower Intrinsics"
;
}
</s>


<s> bool CSKYAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { if ( ! AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , OS ) ) return false ; const MachineOperand & MO = MI -> getOperand ( OpNo ) ; if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'R' : if ( MO . getType ( ) == MachineOperand :: MO_Register ) { OS << CSKYInstPrinter :: getRegisterName ( MO . getReg ( ) + 1 ) ; return false ; } } } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate : OS << MO . getImm ( ) ; return false ; case MachineOperand :: MO_Register : if ( MO . getReg ( ) == CSKY :: C ) return false ; OS << CSKYInstPrinter :: getRegisterName ( MO . getReg ( ) ) ; return false ; case MachineOperand :: MO_GlobalAddress : PrintSymbolOperand ( MO , OS ) ; return false ; case MachineOperand :: MO_BlockAddress : { MCSymbol * Sym = GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; Sym -> print ( OS , MAI ) ; return false ; } default : break ; } return true ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s>
void
CSKYDAGToDAGISel
::
Select
(
SDNode
*
N
)
{
if
(
N
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
N
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;
N
->
setNodeId
(
1
)
;
return
;
}
SDLoc
Dl
(
N
)
;
unsigned
Opcode
=
N
->
getOpcode
(
)
;
bool
IsSelected
=
false
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
ADDCARRY
:
IsSelected
=
selectAddCarry
(
N
)
;
break
;
case
ISD
::
SUBCARRY
:
IsSelected
=
selectSubCarry
(
N
)
;
break
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
{
Register
GP
=
Subtarget
->
getInstrInfo
(
)
->
getGlobalBaseReg
(
*
MF
)
;
ReplaceNode
(
N
,
CurDAG
->
getRegister
(
GP
,
N
->
getValueType
(
0
)
)
.
getNode
(
)
)
;
IsSelected
=
true
;
break
;
}
case
ISD
::
FrameIndex
:
{
SDValue
Imm
=
CurDAG
->
getTargetConstant
(
0
,
Dl
,
MVT
::
i32
)
;
int
FI
=
cast
<
FrameIndexSDNode
>
(
N
)
->
getIndex
(
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
MVT
::
i32
)
;
ReplaceNode
(
N
,
CurDAG
->
getMachineNode
(
Subtarget
->
hasE2
(
)
CSKY
::
ADDI32
:
CSKY
::
ADDI16XZ
,
Dl
,
MVT
::
i32
,
TFI
,
Imm
)
)
;
IsSelected
=
true
;
break
;
}
}
if
(
IsSelected
)
return
;
SelectCode
(
N
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> SDValue R600TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned ShaderType = MF . getInfo < R600MachineFunctionInfo > ( ) -> getShaderType ( ) ; SmallVector < ISD :: InputArg , 8 > LocalIns ; getOriginalFunctionArgs ( DAG , MF . getFunction ( ) , Ins , LocalIns ) ; AnalyzeFormalArguments ( CCInfo , LocalIns ) ; for ( unsigned i = 0 , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; EVT VT = Ins [ i ] . VT ; EVT MemVT = LocalIns [ i ] . VT ; if ( ShaderType != ShaderType :: COMPUTE ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & AMDGPU :: R600_Reg128RegClass ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , AMDGPUAS :: CONSTANT_BUFFER_0 ) ; ISD :: LoadExtType Ext = ISD :: SEXTLOAD ; SDValue Arg = DAG . getExtLoad ( Ext , DL , VT , Chain , DAG . getConstant ( 36 + VA . getLocMemOffset ( ) , MVT :: i32 ) , MachinePointerInfo ( UndefValue :: get ( PtrTy ) ) , MemVT , false , false , 4 ) ; InVals . push_back ( Arg ) ; } return Chain ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> int unqualifiedInlineAsmVariant ( ) const override { return 1 ; } </s>

The default variant to use in unqualified asm instructions .


<s> static bool rs6000_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( mode1 == PTImode ) return mode2 == PTImode ; if ( mode2 == PTImode ) return false ; if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode1 ) ) return ALTIVEC_OR_VSX_VECTOR_MODE ( mode2 ) ; if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode2 ) ) return false ; if ( SCALAR_FLOAT_MODE_P ( mode1 ) ) return SCALAR_FLOAT_MODE_P ( mode2 ) ; if ( SCALAR_FLOAT_MODE_P ( mode2 ) ) return false ; if ( GET_MODE_CLASS ( mode1 ) == MODE_CC ) return GET_MODE_CLASS ( mode2 ) == MODE_CC ; if ( GET_MODE_CLASS ( mode2 ) == MODE_CC ) return false ; if ( PAIRED_VECTOR_MODE ( mode1 ) ) return PAIRED_VECTOR_MODE ( mode2 ) ; if ( PAIRED_VECTOR_MODE ( mode2 ) ) return false ; return true ; } </s>

Implement TARGET_MODES_TIEABLE_P . PTImode can not tie with other modes because PTImode is restricted to even GPR registers , and TImode can go in any GPR as well as VSX registers ( PR 57744 ) . Similarly , do n't allow OOmode ( vector pair , restricted to even VSX registers ) or XOmode ( vector quad , restricted to FPR registers divisible by 4 ) to tie with other modes . Altivec/VSX vector tests were moved ahead of scalar float mode , so that IEEE 128-bit floating point on VSX systems ties with other vectors .


<s> static bool rs6000_is_costly_dependence ( dep_t dep , int cost , int distance ) { rtx insn ; rtx next ; rtx load_mem , str_mem ; if ( rs6000_sched_costly_dep == no_dep_costly ) return false ; if ( rs6000_sched_costly_dep == all_deps_costly ) return true ; insn = DEP_PRO ( dep ) ; next = DEP_CON ( dep ) ; if ( rs6000_sched_costly_dep == store_to_load_dep_costly && is_load_insn ( next , & load_mem ) && is_store_insn ( insn , & str_mem ) ) return true ; if ( rs6000_sched_costly_dep == true_store_to_load_dep_costly && is_load_insn ( next , & load_mem ) && is_store_insn ( insn , & str_mem ) && DEP_TYPE ( dep ) == REG_DEP_TRUE && mem_locations_overlap ( str_mem , load_mem ) ) return true ; if ( rs6000_sched_costly_dep <= max_dep_latency && ( ( cost - distance ) >= ( int ) rs6000_sched_costly_dep ) ) return true ; return false ; } </s>

Returns whether the dependence between INSN and NEXT is considered costly by the given target .


<s>
const
char
*
output_condmove_single
(
rtx
operands
[
]
,
rtx
insn
)
{
rtx
dest
=
operands
[
2
]
;
rtx
src
=
operands
[
3
]
;
if
(
GET_CODE
(
dest
)
==
REG
)
{
int
dest_regno
=
REGNO
(
dest
)
;
machine_mode
mode
=
GET_MODE
(
dest
)
;
if
(
GPR_P
(
dest_regno
)
)
{
if
(
GET_CODE
(
src
)
==
REG
)
{
int
src_regno
=
REGNO
(
src
)
;
if
(
GPR_P
(
src_regno
)
)
return
"cmov %z3, %2, %1, %e0"
;
else
if
(
FPR_P
(
src_regno
)
)
return
"cmovfg %3, %2, %1, %e0"
;
}
else
if
(
GET_CODE
(
src
)
==
MEM
)
{
switch
(
mode
)
{
default
:
break
;
case
QImode
:
return
"cldsb%I3%U3 %M3, %2, %1, %e0"
;
case
HImode
:
return
"cldsh%I3%U3 %M3, %2, %1, %e0"
;
case
SImode
:
case
SFmode
:
return
"cld%I3%U3 %M3, %2, %1, %e0"
;
}
}
else
if
(
ZERO_P
(
src
)
)
return
"cmov %., %2, %1, %e0"
;
}
else
if
(
FPR_P
(
dest_regno
)
)
{
if
(
GET_CODE
(
src
)
==
REG
)
{
int
src_regno
=
REGNO
(
src
)
;
if
(
GPR_P
(
src_regno
)
)
return
"cmovgf %3, %2, %1, %e0"
;
else
if
(
FPR_P
(
src_regno
)
)
{
if
(
TARGET_HARD_FLOAT
)
return
"cfmovs %3,%2,%1,%e0"
;
else
return
"cmor %3, %3, %2, %1, %e0"
;
}
}
else
if
(
GET_CODE
(
src
)
==
MEM
)
{
if
(
mode
==
SImode
||
mode
==
SFmode
)
return
"cldf%I3%U3 %M3, %2, %1, %e0"
;
}
else
if
(
ZERO_P
(
src
)
)
return
"cmovgf %., %2, %1, %e0"
;
}
}
else
if
(
GET_CODE
(
dest
)
==
MEM
)
{
if
(
GET_CODE
(
src
)
==
REG
)
{
int
src_regno
=
REGNO
(
src
)
;
machine_mode
mode
=
GET_MODE
(
dest
)
;
if
(
GPR_P
(
src_regno
)
)
{
switch
(
mode
)
{
default
:
break
;
case
QImode
:
return
"cstb%I2%U2 %3, %M2, %1, %e0"
;
case
HImode
:
return
"csth%I2%U2 %3, %M2, %1, %e0"
;
case
SImode
:
case
SFmode
:
return
"cst%I2%U2 %3, %M2, %1, %e0"
;
}
}
else
if
(
FPR_P
(
src_regno
)
&&
(
mode
==
SImode
||
mode
==
SFmode
)
)
return
"cstf%I2%U2 %3, %M2, %1, %e0"
;
}
else
if
(
ZERO_P
(
src
)
)
{
machine_mode
mode
=
GET_MODE
(
dest
)
;
switch
(
mode
)
{
default
:
break
;
case
QImode
:
return
"cstb%I2%U2 %., %M2, %1, %e0"
;
case
HImode
:
return
"csth%I2%U2 %., %M2, %1, %e0"
;
case
SImode
:
case
SFmode
:
return
"cst%I2%U2 %., %M2, %1, %e0"
;
}
}
}
fatal_insn
(
"bad output_condmove_single operand"
,
insn
)
;
return
""
;
}
</s>

Return a string to output a single word conditional move . Operand0 -- EQ/NE of ccr register and 0 Operand1 -- CCR register Operand2 -- destination Operand3 -- source


<s> bool alpha_legitimate_constant_p ( machine_mode mode , rtx x ) { HOST_WIDE_INT i0 ; switch ( GET_CODE ( x ) ) { case LABEL_REF : case HIGH : return true ; case CONST : if ( GET_CODE ( XEXP ( x , 0 ) ) == PLUS && CONST_INT_P ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ) x = XEXP ( XEXP ( x , 0 ) , 0 ) ; else return true ; if ( GET_CODE ( x ) != SYMBOL_REF ) return true ; case SYMBOL_REF : return SYMBOL_REF_TLS_MODEL ( x ) == 0 ; case CONST_WIDE_INT : if ( TARGET_BUILD_CONSTANTS ) return true ; if ( x == CONST0_RTX ( mode ) ) return true ; mode = DImode ; gcc_assert ( CONST_WIDE_INT_NUNITS ( x ) == 2 ) ; i0 = CONST_WIDE_INT_ELT ( x , 1 ) ; if ( alpha_emit_set_const_1 ( NULL_RTX , mode , i0 , 3 , true ) == NULL ) return false ; i0 = CONST_WIDE_INT_ELT ( x , 0 ) ; goto do_integer ; case CONST_DOUBLE : if ( x == CONST0_RTX ( mode ) ) return true ; return false ; case CONST_VECTOR : if ( x == CONST0_RTX ( mode ) ) return true ; if ( GET_MODE_CLASS ( mode ) != MODE_VECTOR_INT ) return false ; if ( GET_MODE_SIZE ( mode ) != 8 ) return false ; case CONST_INT : if ( TARGET_BUILD_CONSTANTS ) return true ; i0 = alpha_extract_integer ( x ) ; do_integer : return alpha_emit_set_const_1 ( NULL_RTX , mode , i0 , 3 , true ) != NULL ; default : return false ; } } </s>

Implement LEGITIMATE_CONSTANT_P . This is all constants for which we are willing to load the value into a register via a move pattern . Normally this is all symbolic constants , integral constants that take three or fewer instructions , and floating-point zero .


<s> unsigned SIInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const MCInstrDesc & Desc = getMCOpcodeFromPseudo ( Opc ) ; unsigned DescSize = Desc . getSize ( ) ; if ( isFixedSize ( MI ) ) { unsigned Size = DescSize ; if ( MI . isBranch ( ) && ST . hasOffset3fBug ( ) ) Size += 4 ; return Size ; } if ( isVALU ( MI ) || isSALU ( MI ) ) { int Src0Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src0 ) ; if ( Src0Idx == - 1 ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src0Idx ) , Desc . OpInfo [ Src0Idx ] ) ) return isVOP3 ( MI ) ? 12 : ( DescSize + 4 ) ; int Src1Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src1 ) ; if ( Src1Idx == - 1 ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src1Idx ) , Desc . OpInfo [ Src1Idx ] ) ) return isVOP3 ( MI ) ? 12 : ( DescSize + 4 ) ; int Src2Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src2 ) ; if ( Src2Idx == - 1 ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src2Idx ) , Desc . OpInfo [ Src2Idx ] ) ) return isVOP3 ( MI ) ? 12 : ( DescSize + 4 ) ; return DescSize ; } if ( isMIMG ( MI ) ) { int VAddr0Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: vaddr0 ) ; if ( VAddr0Idx < 0 ) return 8 ; int RSrcIdx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: srsrc ) ; return 8 + 4 * ( ( RSrcIdx - VAddr0Idx + 2 ) / 4 ) ; } switch ( Opc ) { case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : case TargetOpcode :: EH_LABEL : return 0 ; case TargetOpcode :: BUNDLE : return getInstBundleSize ( MI ) ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) , & ST ) ; } default : return DescSize ; } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> int fma_node :: get_parity ( ) { return this -> m_head -> regno % 2 ; } </s>

Return the parity of the destination register of the instruction represented by this node .


<s> static int rs6000_use_sched_lookahead ( void ) { if ( rs6000_cpu_attr == CPU_PPC8540 ) return 4 ; return 0 ; } </s>

Return how many instructions to look ahead for better insn scheduling .


<s> unsigned RISCVInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : return 0 ; case RISCV :: LB : case RISCV :: LBU : case RISCV :: LH : case RISCV :: LHU : case RISCV :: LW : case RISCV :: FLW : case RISCV :: LWU : case RISCV :: LD : case RISCV :: FLD : break ; } if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> bool HexagonInstrInfo :: analyzeCompare ( const MachineInstr & MI , unsigned & SrcReg , unsigned & SrcReg2 , int & Mask , int & Value ) const { unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case Hexagon :: C2_cmpeq : case Hexagon :: C2_cmpeqp : case Hexagon :: C2_cmpgt : case Hexagon :: C2_cmpgtp : case Hexagon :: C2_cmpgtu : case Hexagon :: C2_cmpgtup : case Hexagon :: C4_cmpneq : case Hexagon :: C4_cmplte : case Hexagon :: C4_cmplteu : case Hexagon :: C2_cmpeqi : case Hexagon :: C2_cmpgti : case Hexagon :: C2_cmpgtui : case Hexagon :: C4_cmpneqi : case Hexagon :: C4_cmplteui : case Hexagon :: C4_cmpltei : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; Mask = ~ 0 ; break ; case Hexagon :: A4_cmpbeq : case Hexagon :: A4_cmpbgt : case Hexagon :: A4_cmpbgtu : case Hexagon :: A4_cmpbeqi : case Hexagon :: A4_cmpbgti : case Hexagon :: A4_cmpbgtui : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; Mask = 0xFF ; break ; case Hexagon :: A4_cmpheq : case Hexagon :: A4_cmphgt : case Hexagon :: A4_cmphgtu : case Hexagon :: A4_cmpheqi : case Hexagon :: A4_cmphgti : case Hexagon :: A4_cmphgtui : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; Mask = 0xFFFF ; break ; } switch ( Opc ) { case Hexagon :: C2_cmpeq : case Hexagon :: C2_cmpeqp : case Hexagon :: C2_cmpgt : case Hexagon :: C2_cmpgtp : case Hexagon :: C2_cmpgtu : case Hexagon :: C2_cmpgtup : case Hexagon :: A4_cmpbeq : case Hexagon :: A4_cmpbgt : case Hexagon :: A4_cmpbgtu : case Hexagon :: A4_cmpheq : case Hexagon :: A4_cmphgt : case Hexagon :: A4_cmphgtu : case Hexagon :: C4_cmpneq : case Hexagon :: C4_cmplte : case Hexagon :: C4_cmplteu : SrcReg2 = MI . getOperand ( 2 ) . getReg ( ) ; return true ; case Hexagon :: C2_cmpeqi : case Hexagon :: C2_cmpgtui : case Hexagon :: C2_cmpgti : case Hexagon :: C4_cmpneqi : case Hexagon :: C4_cmplteui : case Hexagon :: C4_cmpltei : case Hexagon :: A4_cmpbeqi : case Hexagon :: A4_cmpbgti : case Hexagon :: A4_cmpbgtui : case Hexagon :: A4_cmpheqi : case Hexagon :: A4_cmphgti : case Hexagon :: A4_cmphgtui : SrcReg2 = 0 ; Value = MI . getOperand ( 2 ) . getImm ( ) ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s>
SDValue
ARCTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SIGN_EXTEND_INREG
:
return
LowerSIGN_EXTEND_INREG
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
READCYCLECOUNTER
:
assert
(
Op
.
getSimpleValueType
(
)
==
MVT
::
i32
)
;
return
Op
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

ARC
ARC
ISD::GlobalAddress
ISD::FRAMEADDR
ISD::SELECT_CC
ISD::BR_CC
ISD::SIGN_EXTEND_INREG
ISD::JumpTable
ISD::VASTART
ISD::READCYCLECOUNTER
MVT::i32
"unimplemented operand"


<s> void HexagonInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ) ; if ( Hexagon :: IntRegsRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: S2_storeri_io ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( Hexagon :: DoubleRegsRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: S2_storerd_io ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( Hexagon :: PredRegsRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: STriw_pred ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else { llvm_unreachable ( "Unimplemented" ) ; } } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> static bool store_insn_p ( rtx_insn * insn ) { if ( GET_CODE ( PATTERN ( insn ) ) != SET ) return false ; switch ( get_attr_type ( insn ) ) { case TYPE_STORE : case TYPE_FPSTORE : return true ; default : return false ; } } </s>


"ADJSTACKDOWN and ADJSTACKUP should be no-ops"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static bool tilepro_cannot_force_const_mem ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ATTRIBUTE_UNUSED ) { return true ; } </s>


<s> bool X86CallFrameOptimization :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; MRI = & MF . getRegInfo ( ) ; if ( ! shouldPerformTransformation ( MF ) ) return false ; int FrameSetupOpcode = TII -> getCallFrameSetupOpcode ( ) ; bool Changed = false ; for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ++ I ) if ( I -> getOpcode ( ) == FrameSetupOpcode ) Changed |= adjustCallSequence ( MF , * BB , I ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool Error ( SMLoc L , const Twine & Msg ) { return Parser . Error ( L , Msg ) ; } </s>

Return an error at the location L , with the message Msg .


<s> bool enablePostRAScheduler ( ) const override { return true ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s>
bool
SNESAsmBackend
::
writeNopData
(
uint64_t
Count
,
MCObjectWriter
*
OW
)
const
{
assert
(
(
Count
%
2
)
==
0
&&
"NOP instructions must be 2 bytes"
)
;
OW
->
WriteZeros
(
Count
)
;
return
true
;
}
</s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> bool RISCVAsmBackend :: shouldInsertFixupForCodeAlign ( MCAssembler & Asm , const MCAsmLayout & Layout , MCAlignFragment & AF ) { const MCSubtargetInfo * STI = AF . getSubtargetInfo ( ) ; if ( ! STI -> getFeatureBits ( ) [ RISCV :: FeatureRelax ] ) return false ; unsigned Count ; if ( ! shouldInsertExtraNopBytesForCodeAlign ( AF , Count ) || ( Count == 0 ) ) return false ; MCContext & Ctx = Asm . getContext ( ) ; const MCExpr * Dummy = MCConstantExpr :: create ( 0 , Ctx ) ; MCFixup Fixup = MCFixup :: create ( 0 , Dummy , MCFixupKind ( RISCV :: fixup_riscv_align ) , SMLoc ( ) ) ; uint64_t FixedValue = 0 ; MCValue NopBytes = MCValue :: get ( Count ) ; Asm . getWriter ( ) . recordRelocation ( Asm , Layout , & AF , Fixup , NopBytes , FixedValue ) ; return true ; } </s>

Hook which indicates if the target requires a fixup to be generated when handling an align directive in an executable section .


<s>
bool
X86AsmParser
::
ParseDirective
(
AsmToken
DirectiveID
)
{
MCAsmParser
&
Parser
=
getParser
(
)
;
StringRef
IDVal
=
DirectiveID
.
getIdentifier
(
)
;
if
(
IDVal
.
startswith
(
".code"
)
)
return
ParseDirectiveCode
(
IDVal
,
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
.
startswith
(
".att_syntax"
)
)
{
getParser
(
)
.
setParsingInlineAsm
(
false
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.att_syntax noprefix' is not "
"supported: registers must have a "
"'%' prefix in .att_syntax"
)
;
}
getParser
(
)
.
setAssemblerDialect
(
0
)
;
return
false
;
}
else
if
(
IDVal
.
startswith
(
".intel_syntax"
)
)
{
getParser
(
)
.
setAssemblerDialect
(
1
)
;
getParser
(
)
.
setParsingInlineAsm
(
true
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.intel_syntax prefix' is not "
"supported: registers must not have "
"a '%' prefix in .intel_syntax"
)
;
}
return
false
;
}
else
if
(
IDVal
==
".even"
)
return
parseDirectiveEven
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_proc"
)
return
parseDirectiveFPOProc
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_setframe"
)
return
parseDirectiveFPOSetFrame
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_pushreg"
)
return
parseDirectiveFPOPushReg
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_stackalloc"
)
return
parseDirectiveFPOStackAlloc
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_stackalign"
)
return
parseDirectiveFPOStackAlign
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_endprologue"
)
return
parseDirectiveFPOEndPrologue
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_endproc"
)
return
parseDirectiveFPOEndProc
(
DirectiveID
.
getLoc
(
)
)
;
return
true
;
}
</s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> InstructionCost HexagonTTIImpl :: getCallInstrCost ( Function * F , Type * RetTy , ArrayRef < Type * > Tys , TTI :: TargetCostKind CostKind ) { return BaseT :: getCallInstrCost ( F , RetTy , Tys , CostKind ) ; } </s>

Compute a cost of the given call instruction .


<s> MachineBasicBlock :: iterator X86InstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , const outliner :: Candidate & C ) const { if ( C . CallConstructionID == MachineOutlinerTailCall ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( X86 :: JMP_1 ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; } else { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( X86 :: CALL64pcrel32 ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; } return It ; } </s>

Insert a call to an outlined function into the program .


<s> bool PPCTTIImpl :: enableAggressiveInterleaving ( bool LoopHasReductions ) { return LoopHasReductions ; } </s>

Do n't restrict interleaved unrolling to small loops .


<s> rtx nds32_expand_load_multiple ( int base_regno , int count , rtx base_addr , rtx basemem ) { int par_index ; int offset ; rtx result ; rtx new_addr , mem , reg ; result = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; for ( par_index = 0 ; par_index < count ; par_index ++ ) { offset = par_index * 4 ; new_addr = plus_constant ( Pmode , base_addr , offset ) ; mem = adjust_automodify_address_nv ( basemem , SImode , new_addr , offset ) ; reg = gen_rtx_REG ( SImode , base_regno + par_index ) ; XVECEXP ( result , 0 , par_index ) = gen_rtx_SET ( VOIDmode , reg , mem ) ; } return result ; } </s>

Functions to expand load_multiple and store_multiple . They are auxiliary extern functions to help create rtx template . Check nds32-multiple.md file for the patterns .


"Attempting to lower call as tail call\n"

"... Cannot handle tail calls with swifterror yet.\n"

"... Calling convention cannot be tail called.\n"

"... Cannot tail call from callers with byval, "

"... Cannot tail call externally-defined function "

"Unexpected variadic calling convention"

"... Caller and callee have incompatible calling conventions.\n"

"... Call is eligible for tail call optimization.\n"

Returns true if the call can be lowered as a tail call .


<s>
bool
X86CallLowering
::
lowerReturn
(
MachineIRBuilder
&
MIRBuilder
,
const
Value
*
Val
,
unsigned
VReg
)
const
{
assert
(
(
(
Val
&&
VReg
)
||
(
!
Val
&&
!
VReg
)
)
&&
"Return value without a vreg"
)
;
auto
MIB
=
MIRBuilder
.
buildInstrNoInsert
(
X86
::
RET
)
.
addImm
(
0
)
;
if
(
VReg
)
{
MachineFunction
&
MF
=
MIRBuilder
.
getMF
(
)
;
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
auto
&
DL
=
MF
.
getDataLayout
(
)
;
const
Function
&
F
=
*
MF
.
getFunction
(
)
;
ArgInfo
OrigArg
{
VReg
,
Val
->
getType
(
)
}
;
setArgFlags
(
OrigArg
,
AttributeSet
::
ReturnIndex
,
DL
,
F
)
;
SmallVector
<
ArgInfo
,
8
>
SplitArgs
;
splitToValueTypes
(
OrigArg
,
SplitArgs
,
DL
,
MRI
,
[
&
]
(
ArrayRef
<
unsigned
>
Regs
,
ArrayRef
<
uint64_t
>
Offsets
)
{
MIRBuilder
.
buildExtract
(
Regs
,
Offsets
,
VReg
)
;
}
)
;
FuncReturnHandler
Handler
(
MIRBuilder
,
MRI
,
MIB
,
RetCC_X86
)
;
if
(
!
handleAssignments
(
MIRBuilder
,
SplitArgs
,
Handler
)
)
return
false
;
}
MIRBuilder
.
insertInstr
(
MIB
)
;
return
true
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


" is return block without RETURN instr\n"

Convenience function that returns true if the block ends in a return instruction .


<s> EVT X86TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool NonScalarIntSafe , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( NonScalarIntSafe && ! F -> hasFnAttr ( Attribute :: NoImplicitFloat ) ) { if ( Size >= 16 && ( Subtarget -> isUnalignedMemAccessFast ( ) || ( ( DstAlign == 0 || DstAlign >= 16 ) && ( SrcAlign == 0 || SrcAlign >= 16 ) ) ) && Subtarget -> getStackAlignment ( ) >= 16 ) { if ( Subtarget -> hasAVX ( ) && Subtarget -> getStackAlignment ( ) >= 32 ) return MVT :: v8f32 ; if ( Subtarget -> hasXMMInt ( ) ) return MVT :: v4i32 ; if ( Subtarget -> hasXMM ( ) ) return MVT :: v4f32 ; } else if ( ! MemcpyStrSrc && Size >= 8 && ! Subtarget -> is64Bit ( ) && Subtarget -> getStackAlignment ( ) >= 8 && Subtarget -> hasXMMInt ( ) ) { return MVT :: f64 ; } } if ( Subtarget -> is64Bit ( ) && Size >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> void AMDGPUInliner :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < TargetTransformInfoWrapperPass > ( ) ; LegacyInlinerBase :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> const HexagonSubtarget * getSubtargetImpl ( ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
void
tilegx_function_profiler
(
FILE
*
file
,
int
labelno
ATTRIBUTE_UNUSED
)
{
if
(
tilegx_in_bundle
)
{
fprintf
(
file
,
"\t}\n"
)
;
}
if
(
flag_pic
)
{
fprintf
(
file
,
"\t{\n"
"\tmove\tr10, lr\n"
"\tjal\tplt(%s)\n"
"\t}\n"
,
MCOUNT_NAME
)
;
}
else
{
fprintf
(
file
,
"\t{\n"
"\tmove\tr10, lr\n"
"\tjal\t%s\n"
"\t}\n"
,
MCOUNT_NAME
)
;
}
tilegx_in_bundle
=
false
;
}
</s>

Output assembler code to FILE to increment profiler label # LABELNO for profiling a function entry .


<s> void ix86_expand_round_sse4 ( rtx op0 , rtx op1 ) { machine_mode mode = GET_MODE ( op0 ) ; rtx e1 , e2 , res , half ; const struct real_format * fmt ; REAL_VALUE_TYPE pred_half , half_minus_pred_half ; rtx ( * gen_copysign ) ( rtx , rtx , rtx ) ; rtx ( * gen_round ) ( rtx , rtx , rtx ) ; switch ( mode ) { case SFmode : gen_copysign = gen_copysignsf3 ; gen_round = gen_sse4_1_roundsf2 ; break ; case DFmode : gen_copysign = gen_copysigndf3 ; gen_round = gen_sse4_1_rounddf2 ; break ; default : gcc_unreachable ( ) ; } fmt = REAL_MODE_FORMAT ( mode ) ; real_2expN ( & half_minus_pred_half , - ( fmt -> p ) - 1 , mode ) ; REAL_ARITHMETIC ( pred_half , MINUS_EXPR , dconsthalf , half_minus_pred_half ) ; half = const_double_from_real_value ( pred_half , mode ) ; e1 = gen_reg_rtx ( mode ) ; emit_insn ( gen_copysign ( e1 , half , op1 ) ) ; e2 = expand_simple_binop ( mode , PLUS , op1 , e1 , NULL_RTX , 0 , OPTAB_DIRECT ) ; res = gen_reg_rtx ( mode ) ; emit_insn ( gen_round ( res , e2 , GEN_INT ( ROUND_TRUNC ) ) ) ; emit_move_insn ( op0 , res ) ; } </s>

Expand SSE sequence for computing round from OP1 storing into OP0 using sse4 round insn .


<s> void ARMPassConfig :: addPreEmitPass ( ) { addPass ( createThumb2SizeReductionPass ( ) ) ; if ( getARMSubtarget ( ) . isThumb2 ( ) ) addPass ( & UnpackMachineBundlesID ) ; addPass ( createARMOptimizeBarriersPass ( ) ) ; if ( getARMSubtarget ( ) . useConstIslands ( ) ) addPass ( createARMConstantIslandPass ( ) ) ; if ( getARMSubtarget ( ) . isTargetNaCl ( ) ) { addPass ( createARMNaClRewritePass ( ) ) ; } } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool X86OptimizeLEAPass :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; if ( DisableX86LEAOpt || skipFunction ( MF . getFunction ( ) ) ) return false ; MRI = & MF . getRegInfo ( ) ; TII = MF . getSubtarget < X86Subtarget > ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget < X86Subtarget > ( ) . getRegisterInfo ( ) ; for ( auto & MBB : MF ) { MemOpMap LEAs ; InstrPos . clear ( ) ; findLEAs ( MBB , LEAs ) ; if ( LEAs . empty ( ) ) continue ; Changed |= removeRedundantLEAs ( LEAs ) ; if ( MF . getFunction ( ) . hasOptSize ( ) ) Changed |= removeRedundantAddrCalc ( LEAs ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool s390_rel_address_ok_p ( rtx symbol_ref ) { tree decl ; if ( symbol_ref == s390_got_symbol ( ) || CONSTANT_POOL_ADDRESS_P ( symbol_ref ) ) return true ; decl = SYMBOL_REF_DECL ( symbol_ref ) ; if ( ! flag_pic || SYMBOL_REF_LOCAL_P ( symbol_ref ) ) return ( s390_pic_data_is_text_relative || ( decl && TREE_CODE ( decl ) == FUNCTION_DECL ) ) ; return false ; } </s>

Return true if it ok to use SYMBOL_REF in a relative address .


<s> static bool classof ( const AbstractAttribute * AA ) { return ( AA -> getIdAddr ( ) == & ID ) ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> void X86PassConfig :: addPostRegAlloc ( ) { if ( CustomRegAlloc ) addPass ( createX86RegisterAllocator ( ) ) ; addPass ( createX86FloatingPointStackifierPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s>
void
setReg
(
unsigned
Reg
)
{
assert
(
isRegBase
(
)
&&
"Invalid base register access!"
)
;
Base
.
Reg
=
Reg
;
}
</s>

Assigns the associated register for this edge .


<s> machine_mode function_expander :: mask_mode ( void ) const { vector_type_index mask_type_index = function_types [ type . index ] . type_indexes [ RVV_BASE_mask ] ; return TYPE_MODE ( builtin_types [ mask_type_index ] . vector ) ; } </s>

Return the machine_mode of the corresponding mask type .


<s> bool X86TTIImpl :: areInlineCompatible ( const Function * Caller , const Function * Callee ) const { const TargetMachine & TM = getTLI ( ) -> getTargetMachine ( ) ; const FeatureBitset & CallerBits = TM . getSubtargetImpl ( * Caller ) -> getFeatureBits ( ) ; const FeatureBitset & CalleeBits = TM . getSubtargetImpl ( * Callee ) -> getFeatureBits ( ) ; FeatureBitset RealCallerBits = CallerBits & ~ InlineFeatureIgnoreList ; FeatureBitset RealCalleeBits = CalleeBits & ~ InlineFeatureIgnoreList ; return ( RealCallerBits & RealCalleeBits ) == RealCalleeBits ; } </s>

Determine whether a callee with the given TLI can be inlined into caller with this TLI , based on 'nobuiltin ' attributes .


<s> SDValue AArch64TargetLowering :: BuildSDIVPow2 ( SDNode * N , const APInt & Divisor , SelectionDAG & DAG , SmallVectorImpl < SDNode * > & Created ) const { AttributeList Attr = DAG . getMachineFunction ( ) . getFunction ( ) . getAttributes ( ) ; if ( isIntDivCheap ( N -> getValueType ( 0 ) , Attr ) ) return SDValue ( N , 0 ) ; EVT VT = N -> getValueType ( 0 ) ; if ( VT . isScalableVector ( ) || Subtarget -> useSVEForFixedLengthVectors ( ) ) return SDValue ( N , 0 ) ; if ( ( VT != MVT :: i32 && VT != MVT :: i64 ) || ! ( Divisor . isPowerOf2 ( ) || Divisor . isNegatedPowerOf2 ( ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( 0 ) ; unsigned Lg2 = Divisor . countTrailingZeros ( ) ; SDValue Zero = DAG . getConstant ( 0 , DL , VT ) ; SDValue Pow2MinusOne = DAG . getConstant ( ( 1ULL << Lg2 ) - 1 , DL , VT ) ; SDValue CCVal ; SDValue Cmp = getAArch64Cmp ( N0 , Zero , ISD :: SETLT , CCVal , DAG , DL ) ; SDValue Add = DAG . getNode ( ISD :: ADD , DL , VT , N0 , Pow2MinusOne ) ; SDValue CSel = DAG . getNode ( AArch64ISD :: CSEL , DL , VT , Add , N0 , CCVal , Cmp ) ; Created . push_back ( Cmp . getNode ( ) ) ; Created . push_back ( Add . getNode ( ) ) ; Created . push_back ( CSel . getNode ( ) ) ; SDValue SRA = DAG . getNode ( ISD :: SRA , DL , VT , CSel , DAG . getConstant ( Lg2 , DL , MVT :: i64 ) ) ; if ( Divisor . isNonNegative ( ) ) return SRA ; Created . push_back ( SRA . getNode ( ) ) ; return DAG . getNode ( ISD :: SUB , DL , VT , DAG . getConstant ( 0 , DL , VT ) , SRA ) ; } </s>

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators .


<s> bool PPCSubtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { if ( DarwinDirective == PPC :: DIR_440 || DarwinDirective == PPC :: DIR_A2 ) Mode = TargetSubtargetInfo :: ANTIDEP_ALL ; else Mode = TargetSubtargetInfo :: ANTIDEP_CRITICAL ; CriticalPathRCs . clear ( ) ; if ( isPPC64 ( ) ) CriticalPathRCs . push_back ( & PPC :: G8RCRegClass ) ; else CriticalPathRCs . push_back ( & PPC :: GPRCRegClass ) ; return OptLevel >= CodeGenOpt :: Default ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s> static void msp430_encode_section_info ( tree decl , rtx rtl , int first ) { rtx symbol ; default_encode_section_info ( decl , rtl , first ) ; if ( ! MEM_P ( rtl ) ) return ; symbol = XEXP ( rtl , 0 ) ; if ( GET_CODE ( symbol ) != SYMBOL_REF ) return ; if ( VAR_P ( decl ) && ( TREE_STATIC ( decl ) || DECL_EXTERNAL ( decl ) ) && msp430_var_in_low_mem ( decl ) ) SYMBOL_REF_FLAGS ( symbol ) = SYMBOL_FLAG_LOW_MEM ; } </s>

Encode whether a SYMBOL_REF is definitely in the lower memory region .


<s> PreservedAnalyses BPFPreserveDITypePass :: run ( Function & F , FunctionAnalysisManager & AM ) { return BPFPreserveDITypeImpl ( F ) ? PreservedAnalyses :: none ( ) : PreservedAnalyses :: all ( ) ; } </s>

Run the analysis pass over a function and produce a dominator tree .


"%qs attribute only applies to interrupt functions"

Generate 'handle_interrupt ' attribute for decls


<s>
const
MCPhysReg
*
AArch64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_AArch64_NoRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_AArch64_AllRegs_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetDarwin
(
)
)
return
getDarwinCalleeSavedRegs
(
MF
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
CFGuard_Check
)
return
CSR_Win_AArch64_CFGuard_Check_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetWindows
(
)
)
return
CSR_Win_AArch64_AAPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_VectorCall
)
return
CSR_AArch64_AAVPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_SVE_VectorCall
)
return
CSR_AArch64_SVE_AAPCS_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
.
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_AArch64_AAPCS_SwiftError_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
PreserveMost
)
return
CSR_AArch64_RT_MostRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
Win64
)
return
CSR_AArch64_AAPCS_X18_SaveList
;
return
CSR_AArch64_AAPCS_SaveList
;
}
</s>


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const override { StringRef CPU ( "HexagonV4" ) ; return createHexagonELFObjectWriter ( OS , OSABI , CPU ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s>
void
AVRMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
unsigned
Size
=
Desc
.
getSize
(
)
;
assert
(
Size
>
0
&&
"Instruction size cannot be zero"
)
;
uint64_t
BinaryOpCode
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
emitInstruction
(
BinaryOpCode
,
Size
,
STI
,
OS
)
;
}
</s>

Encode the given Inst to bytes and append to CB .

AVR
AVR
0
"Instruction size cannot be zero"


<s> rtx aarch64_expand_builtin ( tree exp , rtx target , rtx subtarget ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , int ignore ATTRIBUTE_UNUSED ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , 0 ) ; int fcode = DECL_FUNCTION_CODE ( fndecl ) ; int icode ; rtx pat , op0 ; tree arg0 ; switch ( fcode ) { case AARCH64_BUILTIN_GET_FPCR : case AARCH64_BUILTIN_SET_FPCR : case AARCH64_BUILTIN_GET_FPSR : case AARCH64_BUILTIN_SET_FPSR : if ( ( fcode == AARCH64_BUILTIN_GET_FPCR ) || ( fcode == AARCH64_BUILTIN_GET_FPSR ) ) { icode = ( fcode == AARCH64_BUILTIN_GET_FPSR ) ? CODE_FOR_get_fpsr : CODE_FOR_get_fpcr ; target = gen_reg_rtx ( SImode ) ; pat = GEN_FCN ( icode ) ( target ) ; } else { target = NULL_RTX ; icode = ( fcode == AARCH64_BUILTIN_SET_FPSR ) ? CODE_FOR_set_fpsr : CODE_FOR_set_fpcr ; arg0 = CALL_EXPR_ARG ( exp , 0 ) ; op0 = force_reg ( SImode , expand_normal ( arg0 ) ) ; pat = GEN_FCN ( icode ) ( op0 ) ; } emit_insn ( pat ) ; return target ; case AARCH64_PAUTH_BUILTIN_AUTIA1716 : case AARCH64_PAUTH_BUILTIN_PACIA1716 : case AARCH64_PAUTH_BUILTIN_XPACLRI : arg0 = CALL_EXPR_ARG ( exp , 0 ) ; op0 = force_reg ( Pmode , expand_normal ( arg0 ) ) ; if ( ! target ) target = gen_reg_rtx ( Pmode ) ; else target = force_reg ( Pmode , target ) ; emit_move_insn ( target , op0 ) ; if ( fcode == AARCH64_PAUTH_BUILTIN_XPACLRI ) { rtx lr = gen_rtx_REG ( Pmode , R30_REGNUM ) ; icode = CODE_FOR_xpaclri ; emit_move_insn ( lr , op0 ) ; emit_insn ( GEN_FCN ( icode ) ( ) ) ; emit_move_insn ( target , lr ) ; } else { tree arg1 = CALL_EXPR_ARG ( exp , 1 ) ; rtx op1 = force_reg ( Pmode , expand_normal ( arg1 ) ) ; icode = ( fcode == AARCH64_PAUTH_BUILTIN_PACIA1716 ? CODE_FOR_paci1716 : CODE_FOR_auti1716 ) ; rtx x16_reg = gen_rtx_REG ( Pmode , R16_REGNUM ) ; rtx x17_reg = gen_rtx_REG ( Pmode , R17_REGNUM ) ; emit_move_insn ( x17_reg , op0 ) ; emit_move_insn ( x16_reg , op1 ) ; emit_insn ( GEN_FCN ( icode ) ( ) ) ; emit_move_insn ( target , x17_reg ) ; } return target ; } if ( fcode >= AARCH64_SIMD_BUILTIN_BASE && fcode <= AARCH64_SIMD_BUILTIN_MAX ) return aarch64_simd_expand_builtin ( fcode , exp , target ) ; else if ( fcode >= AARCH64_CRC32_BUILTIN_BASE && fcode <= AARCH64_CRC32_BUILTIN_MAX ) return aarch64_crc32_expand_builtin ( fcode , exp , target ) ; if ( fcode == AARCH64_BUILTIN_RSQRT_DF || fcode == AARCH64_BUILTIN_RSQRT_SF || fcode == AARCH64_BUILTIN_RSQRT_V2DF || fcode == AARCH64_BUILTIN_RSQRT_V2SF || fcode == AARCH64_BUILTIN_RSQRT_V4SF ) return aarch64_expand_builtin_rsqrt ( fcode , exp , target ) ; gcc_unreachable ( ) ; } </s>


<s> static void aarch64_emit_post_barrier ( enum memmodel model ) { const enum memmodel base_model = memmodel_base ( model ) ; if ( is_mm_sync ( model ) && ( base_model == MEMMODEL_ACQUIRE || base_model == MEMMODEL_ACQ_REL || base_model == MEMMODEL_SEQ_CST ) ) { emit_insn ( gen_mem_thread_fence ( GEN_INT ( MEMMODEL_SEQ_CST ) ) ) ; } } </s>

Emit a barrier , that is appropriate for memory model MODEL , at the end of a sequence implementing an atomic operation .


<s> void R600PassConfig :: addPreEmitPass ( ) { addPass ( createR600MachineCFGStructurizerPass ( ) ) ; addPass ( createR600ExpandSpecialInstrsPass ( ) ) ; addPass ( & FinalizeMachineBundlesID ) ; addPass ( createR600Packetizer ( ) ) ; addPass ( createR600ControlFlowFinalizer ( ) ) ; } </s>


"Callee should be an llvm::Function object."

"failed to perform tail call elimination on a call "

This hook must be implemented to lower calls into the specified DAG .


<s> bool RISCVInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { TBB = FBB = nullptr ; Cond . clear ( ) ; MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) || ! isUnpredicatedTerminator ( * I ) ) return false ; MachineBasicBlock :: iterator FirstUncondOrIndirectBr = MBB . end ( ) ; int NumTerminators = 0 ; for ( auto J = I . getReverse ( ) ; J != MBB . rend ( ) && isUnpredicatedTerminator ( * J ) ; J ++ ) { NumTerminators ++ ; if ( J -> getDesc ( ) . isUnconditionalBranch ( ) || J -> getDesc ( ) . isIndirectBranch ( ) ) { FirstUncondOrIndirectBr = J . getReverse ( ) ; } } if ( AllowModify && FirstUncondOrIndirectBr != MBB . end ( ) ) { while ( std :: next ( FirstUncondOrIndirectBr ) != MBB . end ( ) ) { std :: next ( FirstUncondOrIndirectBr ) -> eraseFromParent ( ) ; NumTerminators -- ; } I = FirstUncondOrIndirectBr ; } if ( I -> getDesc ( ) . isIndirectBranch ( ) ) return true ; if ( NumTerminators > 2 ) return true ; if ( NumTerminators == 1 && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { TBB = getBranchDestBlock ( * I ) ; return false ; } if ( NumTerminators == 1 && I -> getDesc ( ) . isConditionalBranch ( ) ) { parseCondBranch ( * I , TBB , Cond ) ; return false ; } if ( NumTerminators == 2 && std :: prev ( I ) -> getDesc ( ) . isConditionalBranch ( ) && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { parseCondBranch ( * std :: prev ( I ) , TBB , Cond ) ; FBB = getBranchDestBlock ( * I ) ; return false ; } return true ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> bool DLXDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 , AluOp ; switch ( ConstraintCode ) { default : return true ; case InlineAsm :: Constraint_m : if ( ! selectAddrRr ( Op , Op0 , Op1 , AluOp ) && ! selectAddrRi ( Op , Op0 , Op1 , AluOp ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; OutOps . push_back ( AluOp ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> bool RISCVMCAsmBackend :: mayNeedRelaxation ( const MCInst & Inst ) const { return getRelaxedOpcode ( Inst . getOpcode ( ) ) != 0 ; } </s>

Check whether the given instruction may need relaxation .


<s>
void
RISCVDAGToDAGISel
::
PreprocessISelDAG
(
)
{
for
(
SelectionDAG
::
allnodes_iterator
I
=
CurDAG
->
allnodes_begin
(
)
,
E
=
CurDAG
->
allnodes_end
(
)
;
I
!=
E
;
)
{
SDNode
*
N
=
&
*
I
++
;
if
(
N
->
getOpcode
(
)
!=
RISCVISD
::
SPLAT_VECTOR_SPLIT_I64_VL
)
continue
;
assert
(
N
->
getNumOperands
(
)
==
3
&&
"Unexpected number of operands"
)
;
MVT
VT
=
N
->
getSimpleValueType
(
0
)
;
SDValue
Lo
=
N
->
getOperand
(
0
)
;
SDValue
Hi
=
N
->
getOperand
(
1
)
;
SDValue
VL
=
N
->
getOperand
(
2
)
;
assert
(
VT
.
getVectorElementType
(
)
==
MVT
::
i64
&&
VT
.
isScalableVector
(
)
&&
Lo
.
getValueType
(
)
==
MVT
::
i32
&&
Hi
.
getValueType
(
)
==
MVT
::
i32
&&
"Unexpected VTs!"
)
;
MachineFunction
&
MF
=
CurDAG
->
getMachineFunction
(
)
;
RISCVMachineFunctionInfo
*
FuncInfo
=
MF
.
getInfo
<
RISCVMachineFunctionInfo
>
(
)
;
SDLoc
DL
(
N
)
;
int
FI
=
FuncInfo
->
getMoveF64FrameIndex
(
MF
)
;
MachinePointerInfo
MPI
=
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
;
const
TargetLowering
&
TLI
=
CurDAG
->
getTargetLoweringInfo
(
)
;
SDValue
StackSlot
=
CurDAG
->
getFrameIndex
(
FI
,
TLI
.
getPointerTy
(
CurDAG
->
getDataLayout
(
)
,
CurDAG
->
getDataLayout
(
)
.
getAllocaAddrSpace
(
)
)
)
;
SDValue
Chain
=
CurDAG
->
getEntryNode
(
)
;
Lo
=
CurDAG
->
getStore
(
Chain
,
DL
,
Lo
,
StackSlot
,
MPI
,
Align
(
8
)
)
;
SDValue
OffsetSlot
=
CurDAG
->
getMemBasePlusOffset
(
StackSlot
,
TypeSize
::
Fixed
(
4
)
,
DL
)
;
Hi
=
CurDAG
->
getStore
(
Chain
,
DL
,
Hi
,
OffsetSlot
,
MPI
.
getWithOffset
(
4
)
,
Align
(
8
)
)
;
Chain
=
CurDAG
->
getNode
(
ISD
::
TokenFactor
,
DL
,
MVT
::
Other
,
Lo
,
Hi
)
;
SDVTList
VTs
=
CurDAG
->
getVTList
(
{
VT
,
MVT
::
Other
}
)
;
SDValue
IntID
=
CurDAG
->
getTargetConstant
(
Intrinsic
::
riscv_vlse
,
DL
,
MVT
::
i64
)
;
SDValue
Ops
[
]
=
{
Chain
,
IntID
,
StackSlot
,
CurDAG
->
getRegister
(
RISCV
::
X0
,
MVT
::
i64
)
,
VL
}
;
SDValue
Result
=
CurDAG
->
getMemIntrinsicNode
(
ISD
::
INTRINSIC_W_CHAIN
,
DL
,
VTs
,
Ops
,
MVT
::
i64
,
MPI
,
Align
(
8
)
,
MachineMemOperand
::
MOLoad
)
;
I
;
CurDAG
->
ReplaceAllUsesOfValueWith
(
SDValue
(
N
,
0
)
,
Result
)
;
++
I
;
CurDAG
->
DeleteNode
(
N
)
;
}
}
</s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> bool AMDGPULowerKernelAttributes :: runOnModule ( Module & M ) { StringRef DispatchPtrName = Intrinsic :: getName ( Intrinsic :: amdgcn_dispatch_ptr ) ; Function * DispatchPtr = M . getFunction ( DispatchPtrName ) ; if ( ! DispatchPtr ) return false ; bool MadeChange = false ; SmallPtrSet < Instruction * , 4 > HandledUses ; for ( auto * U : DispatchPtr -> users ( ) ) { CallInst * CI = cast < CallInst > ( U ) ; if ( HandledUses . insert ( CI ) . second ) { if ( processUse ( CI ) ) MadeChange = true ; } } return MadeChange ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> const MCExpr * getSubExpr ( ) const { return Expr ; } </s>

getSubExpr - Get the child of this expression .


<s>
const
char
*
avr_out_xload
(
rtx_insn
*
insn
ATTRIBUTE_UNUSED
,
rtx
*
op
,
int
*
plen
)
{
rtx
xop
[
4
]
;
xop
[
0
]
=
op
[
0
]
;
xop
[
1
]
=
op
[
1
]
;
xop
[
2
]
=
lpm_addr_reg_rtx
;
xop
[
3
]
=
AVR_HAVE_LPMX
op
[
0
]
:
lpm_reg_rtx
;
avr_asm_len
(
AVR_HAVE_LPMX
"lpm %3,%a2"
:
"lpm"
,
xop
,
plen
,
1
)
;
avr_asm_len
(
"sbrc %1,7"
CR_TAB
"ld %3,%a2"
,
xop
,
plen
,
2
)
;
if
(
REGNO
(
xop
[
0
]
)
!=
REGNO
(
xop
[
3
]
)
)
avr_asm_len
(
"mov %0,%3"
,
xop
,
plen
,
1
)
;
return
""
;
}
</s>


<s> bool XCoreRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return hasFP ( MF ) ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s>
void
thumb1_final_prescan_insn
(
rtx_insn
*
insn
)
{
if
(
flag_print_asm_name
)
asm_fprintf
(
asm_out_file
,
"%@ 0x%04x\n"
,
INSN_ADDRESSES
(
INSN_UID
(
insn
)
)
)
;
if
(
INSN_CODE
(
insn
)
!=
CODE_FOR_cbranchsi4_insn
)
{
enum
attr_conds
conds
;
if
(
cfun
->
machine
->
thumb1_cc_insn
)
{
if
(
modified_in_p
(
cfun
->
machine
->
thumb1_cc_op0
,
insn
)
||
modified_in_p
(
cfun
->
machine
->
thumb1_cc_op1
,
insn
)
)
CC_STATUS_INIT
;
}
conds
=
get_attr_conds
(
insn
)
;
if
(
conds
==
CONDS_SET
)
{
rtx
set
=
single_set
(
insn
)
;
cfun
->
machine
->
thumb1_cc_insn
=
insn
;
cfun
->
machine
->
thumb1_cc_op0
=
SET_DEST
(
set
)
;
cfun
->
machine
->
thumb1_cc_op1
=
const0_rtx
;
cfun
->
machine
->
thumb1_cc_mode
=
CC_NOOVmode
;
if
(
INSN_CODE
(
insn
)
==
CODE_FOR_thumb1_subsi3_insn
)
{
rtx
src1
=
XEXP
(
SET_SRC
(
set
)
,
1
)
;
if
(
src1
==
const0_rtx
)
cfun
->
machine
->
thumb1_cc_mode
=
CCmode
;
}
else
if
(
REG_P
(
SET_DEST
(
set
)
)
&&
REG_P
(
SET_SRC
(
set
)
)
)
{
cfun
->
machine
->
thumb1_cc_op0
=
SET_SRC
(
set
)
;
}
}
else
if
(
conds
!=
CONDS_NOCOND
)
cfun
->
machine
->
thumb1_cc_insn
=
NULL_RTX
;
}
if
(
cfun
->
machine
->
lr_save_eliminated
&&
get_attr_far_jump
(
insn
)
==
FAR_JUMP_YES
)
internal_error
(
"Unexpected thumb1 far jump"
)
;
}
</s>

Scan INSN just before assembler is output for it . For Thumb-1 , we track the status of the condition codes ; this information is used in the cbranchsi4_insn pattern .

arm
"%@ 0x%04x\n"
1
"Unexpected thumb1 far jump"


<s> static rtx mips16e_build_save_restore ( bool restore_p , unsigned int * mask_ptr , HOST_WIDE_INT * offset_ptr , unsigned int nargs , HOST_WIDE_INT size ) { rtx pattern , set ; HOST_WIDE_INT offset , top_offset ; unsigned int i , regno ; int n ; gcc_assert ( cfun -> machine -> frame . num_fp == 0 ) ; n = 1 + nargs ; for ( i = 0 ; i < ARRAY_SIZE ( mips16e_save_restore_regs ) ; i ++ ) if ( BITSET_P ( * mask_ptr , mips16e_save_restore_regs [ i ] ) ) n ++ ; pattern = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( n ) ) ; n = 0 ; set = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , restore_p ? size : - size ) ) ; RTX_FRAME_RELATED_P ( set ) = 1 ; XVECEXP ( pattern , 0 , n ++ ) = set ; top_offset = restore_p ? size : 0 ; for ( i = 0 ; i < nargs ; i ++ ) { offset = top_offset + i * UNITS_PER_WORD ; set = mips16e_save_restore_reg ( restore_p , true , offset , GP_ARG_FIRST + i ) ; XVECEXP ( pattern , 0 , n ++ ) = set ; } offset = top_offset ; for ( i = 0 ; i < ARRAY_SIZE ( mips16e_save_restore_regs ) ; i ++ ) { regno = mips16e_save_restore_regs [ i ] ; if ( BITSET_P ( * mask_ptr , regno ) ) { offset -= UNITS_PER_WORD ; set = mips16e_save_restore_reg ( restore_p , false , offset , regno ) ; XVECEXP ( pattern , 0 , n ++ ) = set ; * mask_ptr &= ~ ( 1 << regno ) ; } } * offset_ptr = size + ( offset - top_offset ) ; gcc_assert ( n == XVECLEN ( pattern , 0 ) ) ; return pattern ; } </s>

Return RTL for a MIPS16e SAVE or RESTORE instruction ; RESTORE_P says which . The instruction must : - Allocate or deallocate SIZE bytes in total ; SIZE is known to be nonzero . - Save or restore as many registers in * MASK_PTR as possible . The instruction saves the first registers at the top of the allocated area , with the other registers below it . - Save NARGS argument registers above the allocated area . ( NARGS is always zero if RESTORE_P . ) The SAVE and RESTORE instructions can not save and restore all general registers , so there may be some registers left over for the caller to handle . Destructively modify * MASK_PTR so that it contains the registers that still need to be saved or restored . The caller can save these registers in the memory immediately below * OFFSET_PTR , which is a byte offset from the bottom of the allocated stack area .


<s> static bool rl78_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { int s = GET_MODE_SIZE ( mode ) ; if ( s < 1 ) return false ; if ( regno == 23 || regno == ES_REG || regno == CS_REG ) return false ; if ( regno == FP_REG && s == 2 ) return true ; if ( regno < SP_REG ) { if ( s > 1 && ( regno % 2 ) ) return false ; return true ; } if ( s == CC_REGNUM ) return ( mode == BImode ) ; if ( s == register_sizes [ regno ] ) return true ; return false ; } </s>


<s> static bool rs6000_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE ( mode ) ) return true ; if ( TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) return true ; else if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) ) return true ; else return false ; } </s>

Target hook for vector_mode_supported_p .


<s> bool GCNTTIImpl :: collectFlatAddressOperands ( SmallVectorImpl < int > & OpIndexes , Intrinsic :: ID IID ) const { switch ( IID ) { case Intrinsic :: amdgcn_atomic_inc : case Intrinsic :: amdgcn_atomic_dec : case Intrinsic :: amdgcn_ds_fadd : case Intrinsic :: amdgcn_ds_fmin : case Intrinsic :: amdgcn_ds_fmax : OpIndexes . push_back ( 0 ) ; return true ; default : return false ; } } </s>

Return any intrinsic address operand indexes which may be rewritten if they use a flat address space pointer .


<s> static void ultra_flush_pipeline ( ) { ultra_cur_hist = ( ultra_cur_hist + 1 ) & ( ULTRA_NUM_HIST - 1 ) ; ultra_cycles_elapsed += 1 ; memset ( ( char * ) & ultra_pipe , 0 , sizeof ultra_pipe ) ; ultra_pipe . free_slot_mask = 0xf ; } </s>


<s> bool aarch64_use_pseudo_pic_reg ( void ) { return aarch64_cmodel == AARCH64_CMODEL_SMALL_SPIC ; } </s>

Return 1 if pseudo register should be created and used to hold GOT address for PIC code .


<s> static const char * rs6000_mangle_type ( const_tree type ) { type = TYPE_MAIN_VARIANT ( type ) ; if ( TREE_CODE ( type ) != VOID_TYPE && TREE_CODE ( type ) != BOOLEAN_TYPE && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE && TREE_CODE ( type ) != OPAQUE_TYPE ) return NULL ; if ( type == bool_char_type_node ) return "U6__boolc" ; if ( type == bool_short_type_node ) return "U6__bools" ; if ( type == pixel_type_node ) return "u7__pixel" ; if ( type == bool_int_type_node ) return "U6__booli" ; if ( type == bool_long_long_type_node ) return "U6__boolx" ; if ( SCALAR_FLOAT_TYPE_P ( type ) && FLOAT128_IBM_P ( TYPE_MODE ( type ) ) ) return "g" ; if ( SCALAR_FLOAT_TYPE_P ( type ) && FLOAT128_IEEE_P ( TYPE_MODE ( type ) ) ) return "u9__ieee128" ; if ( type == vector_pair_type_node ) return "u13__vector_pair" ; if ( type == vector_quad_type_node ) return "u13__vector_quad" ; return NULL ; } </s>

AltiVec defines five built-in scalar types that serve as vector elements ; we must teach the compiler how to mangle them . The 128-bit floating point mangling is target-specific as well . MMA defines two built-in types to be used as opaque vector types .


"-m64 requires PowerPC64 architecture, enabling"

The Darwin version of SUBTARGET_OVERRIDE_OPTIONS .


<s> static bool rs6000_use_blocks_for_decl_p ( const_tree decl ) { return ! DECL_THREAD_LOCAL_P ( decl ) ; } </s>

Do not place thread-local symbols refs in the object blocks .


<s>
bool
runOnMachineFunction
(
MachineFunction
&
MF
)
override
{
Subtarget
=
&
MF
.
getSubtarget
<
X86Subtarget
>
(
)
;
IndirectTlsSegRefs
=
MF
.
getFunction
(
)
.
hasFnAttribute
(
"indirect-tls-seg-refs"
)
;
OptForSize
=
MF
.
getFunction
(
)
.
optForSize
(
)
;
OptForMinSize
=
MF
.
getFunction
(
)
.
optForMinSize
(
)
;
assert
(
(
!
OptForMinSize
||
OptForSize
)
&&
"OptForMinSize implies OptForSize"
)
;
SelectionDAGISel
::
runOnMachineFunction
(
MF
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static void avr_adjust_type_node ( tree * node , machine_mode mode , int sat_p ) { * node = make_node ( FIXED_POINT_TYPE ) ; TYPE_SATURATING ( * node ) = sat_p ; TYPE_UNSIGNED ( * node ) = UNSIGNED_FIXED_POINT_MODE_P ( mode ) ; TYPE_IBIT ( * node ) = GET_MODE_IBIT ( mode ) ; TYPE_FBIT ( * node ) = GET_MODE_FBIT ( mode ) ; TYPE_PRECISION ( * node ) = GET_MODE_BITSIZE ( mode ) ; SET_TYPE_ALIGN ( * node , 8 ) ; SET_TYPE_MODE ( * node , mode ) ; layout_type ( * node ) ; } </s>


<s> virtual bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const LLVM_OVERRIDE { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> inline bool libcall_hasher :: equal ( const rtx_def * p1 , const rtx_def * p2 ) { return rtx_equal_p ( p1 , p2 ) ; } </s>


<s> Optional < RegImmPair > ARMBaseInstrInfo :: isAddImmediate ( const MachineInstr & MI , Register Reg ) const { int Sign = 1 ; unsigned Opcode = MI . getOpcode ( ) ; int64_t Offset = 0 ; const MachineOperand & Op0 = MI . getOperand ( 0 ) ; if ( ! Op0 . isReg ( ) || Reg != Op0 . getReg ( ) ) return None ; if ( Opcode == ARM :: SUBri ) Sign = - 1 ; else if ( Opcode != ARM :: ADDri ) return None ; if ( ! MI . getOperand ( 1 ) . isReg ( ) || ! MI . getOperand ( 2 ) . isImm ( ) ) return None ; Offset = MI . getOperand ( 2 ) . getImm ( ) * Sign ; return RegImmPair { MI . getOperand ( 1 ) . getReg ( ) , Offset } ; } </s>

If the specific machine instruction is an instruction that adds an immediate value and a register , and stores the result in the given register Reg , return a pair of the source register and the offset which has been added .


<s> bool XCoreTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , const Type * Ty ) const { if ( Ty -> getTypeID ( ) == Type :: VoidTyID ) return false ; const TargetData * TD = TM . getTargetData ( ) ; unsigned Size = TD -> getTypeAllocSize ( Ty ) ; if ( AM . BaseGV ) { return Size >= 4 && ! AM . HasBaseReg && AM . Scale == 0 && AM . BaseOffs % 4 == 0 ; } switch ( Size ) { case 1 : if ( AM . Scale == 0 ) { return isImmUs ( AM . BaseOffs ) ; } return AM . Scale == 1 && AM . BaseOffs == 0 ; case 2 : case 3 : if ( AM . Scale == 0 ) { return isImmUs2 ( AM . BaseOffs ) ; } return AM . Scale == 2 && AM . BaseOffs == 0 ; default : if ( AM . Scale == 0 ) { return isImmUs4 ( AM . BaseOffs ) ; } return AM . Scale == 4 && AM . BaseOffs == 0 ; } return false ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> enum reg_class eco32_reg_class ( int regno ) { if ( is_ECO32_GENERAL_REG ( regno ) ) { return GENERAL_REGS ; } if ( is_ECO32_REG ( regno ) ) { return ALL_REGS ; } return NO_REGS ; } </s>


<s>
void
bpf_print_operand_address
(
FILE
*
file
,
rtx
addr
)
{
switch
(
GET_CODE
(
addr
)
)
{
case
REG
:
fprintf
(
file
,
"[%s+0]"
,
reg_names
[
REGNO
(
addr
)
]
)
;
break
;
case
PLUS
:
{
rtx
op0
=
XEXP
(
addr
,
0
)
;
rtx
op1
=
XEXP
(
addr
,
1
)
;
if
(
GET_CODE
(
op0
)
==
REG
&&
GET_CODE
(
op1
)
==
CONST_INT
)
{
fprintf
(
file
,
"[%s+"
,
reg_names
[
REGNO
(
op0
)
]
)
;
output_addr_const
(
file
,
op1
)
;
fputs
(
"]"
,
file
)
;
}
else
fatal_insn
(
"invalid address in operand"
,
addr
)
;
break
;
}
case
MEM
:
case
LABEL_REF
:
fatal_insn
(
"unsupported operand"
,
addr
)
;
break
;
default
:
output_addr_const
(
file
,
addr
)
;
break
;
}
}
</s>

Print an operand which is an address . This function should handle any legit address , as accepted by bpf_legitimate_address_p , and also addresses that are valid in CALL instructions . This function is called in the PRINT_OPERAND_ADDRESS macro defined in bpf.h


<s> bool ShouldShrinkFPConstant ( EVT VT ) const override { return VT != MVT :: f128 ; } </s>

If true , then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime .


<s>
SDValue
AMDGPUTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
Op
->
print
(
errs
(
)
,
&
DAG
)
;
llvm_unreachable
(
"Custom lowering code for this"
"instruction is not implemented yet!"
)
;
break
;
case
ISD
::
SIGN_EXTEND_INREG
:
return
LowerSIGN_EXTEND_INREG
(
Op
,
DAG
)
;
case
ISD
::
CONCAT_VECTORS
:
return
LowerCONCAT_VECTORS
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_SUBVECTOR
:
return
LowerEXTRACT_SUBVECTOR
(
Op
,
DAG
)
;
case
ISD
::
UDIVREM
:
return
LowerUDIVREM
(
Op
,
DAG
)
;
case
ISD
::
SDIVREM
:
return
LowerSDIVREM
(
Op
,
DAG
)
;
case
ISD
::
FREM
:
return
LowerFREM
(
Op
,
DAG
)
;
case
ISD
::
FCEIL
:
return
LowerFCEIL
(
Op
,
DAG
)
;
case
ISD
::
FTRUNC
:
return
LowerFTRUNC
(
Op
,
DAG
)
;
case
ISD
::
FRINT
:
return
LowerFRINT
(
Op
,
DAG
)
;
case
ISD
::
FNEARBYINT
:
return
LowerFNEARBYINT
(
Op
,
DAG
)
;
case
ISD
::
FROUND
:
return
LowerFROUND
(
Op
,
DAG
)
;
case
ISD
::
FFLOOR
:
return
LowerFFLOOR
(
Op
,
DAG
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerSINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
UINT_TO_FP
:
return
LowerUINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_FP16
:
return
LowerFP_TO_FP16
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_SINT
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_UINT
(
Op
,
DAG
)
;
case
ISD
::
CTLZ
:
case
ISD
::
CTLZ_ZERO_UNDEF
:
return
LowerCTLZ
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
}
return
Op
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> void setName ( StringRef N ) { SectionName = N ; } </s>

Change the name of this type to the specified name , or to a name with a suffix if there is a collision .


<s> static rtx ix86_expand_vec_set_builtin ( tree arglist ) { enum machine_mode tmode , mode1 ; tree arg0 , arg1 , arg2 ; int elt ; rtx op0 , op1 ; arg0 = TREE_VALUE ( arglist ) ; arg1 = TREE_VALUE ( TREE_CHAIN ( arglist ) ) ; arg2 = TREE_VALUE ( TREE_CHAIN ( TREE_CHAIN ( arglist ) ) ) ; tmode = TYPE_MODE ( TREE_TYPE ( arg0 ) ) ; mode1 = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( arg0 ) ) ) ; gcc_assert ( VECTOR_MODE_P ( tmode ) ) ; op0 = expand_expr ( arg0 , NULL_RTX , tmode , 0 ) ; op1 = expand_expr ( arg1 , NULL_RTX , mode1 , 0 ) ; elt = get_element_number ( TREE_TYPE ( arg0 ) , arg2 ) ; if ( GET_MODE ( op1 ) != mode1 && GET_MODE ( op1 ) != VOIDmode ) op1 = convert_modes ( mode1 , GET_MODE ( op1 ) , op1 , true ) ; op0 = force_reg ( tmode , op0 ) ; op1 = force_reg ( mode1 , op1 ) ; ix86_expand_vector_set ( true , op0 , op1 , elt ) ; return op0 ; } </s>

A subroutine of ix86_expand_builtin . These builtins are a wrapper around ix86_expand_vector_set . They would be redundant ( for non-MMX ) if we had a language-level syntax for referencing vector elements .


<s> MachineBasicBlock :: iterator begin ( ) { assert ( Begin != nullptr ) ; return Begin ; } </s>


"insertBranch must not be told to insert a fallthrough"

"CSKY branch conditions have two components!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> bool SITargetLowering :: enableAggressiveFMAFusion ( EVT VT ) const { return true ; } </s>

Return true if target always benefits from combining into FMA for a given value type .


<s> bool MipsSETargetLowering :: isEligibleForTailCallOptimization ( const CCState & CCInfo , unsigned NextStackOffset , const MipsFunctionInfo & FI ) const { if ( ! UseMipsTailCalls ) return false ; if ( FI . isISR ( ) ) return false ; if ( CCInfo . getInRegsParamsCount ( ) > 0 || FI . hasByvalArg ( ) ) return false ; return NextStackOffset <= FI . getIncomingArgSize ( ) ; } </s>

Returns true if the call can be lowered as a tail call .


<s>
SDValue
Z80TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
ZERO_EXTEND
:
return
LowerZExt
(
Op
,
DAG
)
;
case
ISD
::
SIGN_EXTEND
:
return
LowerSExt
(
Op
,
DAG
)
;
case
ISD
::
SUB
:
case
ISD
::
SUBC
:
return
LowerSUB
(
Op
,
DAG
)
;
case
ISD
::
SRL
:
case
ISD
::
SHL
:
case
ISD
::
SRA
:
case
ISD
::
ROTL
:
case
ISD
::
ROTR
:
return
LowerShifts
(
Op
,
DAG
)
;
case
ISD
::
AND
:
case
ISD
::
OR
:
case
ISD
::
XOR
:
return
LowerBinaryOp
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSelectCC
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBrCC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
STORE
:
return
LowerStore
(
Op
,
DAG
)
;
case
ISD
::
LOAD
:
return
LowerLoad
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operation"
)
;
}
}
</s>

Z80
Z80
ISD::ZERO_EXTEND
ISD::SIGN_EXTEND
ISD::SUB
ISD::SUBC
ISD::SRL
ISD::SHL
ISD::SRA
ISD::ROTL
ISD::ROTR
ISD::AND
ISD::OR
ISD::XOR
ISD::SELECT_CC
ISD::BR_CC
ISD::GlobalAddress
ISD::STORE
ISD::LOAD
"unimplemented operation"


<s> static unsigned bit_count ( unsigned HOST_WIDE_INT value ) { unsigned count = 0 ; while ( value ) { count ++ ; value &= value - 1 ; } return count ; } </s>

Typical stack layout should looks like this after the function 's prologue : | | -- ^ | | \ | | | arguments saved | Increasing | | on the stack | addresses PARENT arg pointer - > | | / -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - CHILD |ret | return address -- | | \ | | call saved | | registers | | / -- | | \ | | local | | variables frame pointer - > | | / -- | | \ | | outgoing | Decreasing | | arguments | addresses current stack pointer - > | | / | -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- V | |


<s> bool sh_cfun_interrupt_handler_p ( void ) { return ( lookup_attribute ( "interrupt_handler" , DECL_ATTRIBUTES ( current_function_decl ) ) != NULL_TREE ) ; } </s>

Returns true if the current function has the `` interrupt_handler '' attribute set .


<s> const TargetRegisterClass * X86RegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { if ( RC == & X86 :: GR8_NOREXRegClass ) return RC ; const X86Subtarget & Subtarget = MF . getSubtarget < X86Subtarget > ( ) ; const TargetRegisterClass * Super = RC ; TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case X86 :: FR32RegClassID : case X86 :: FR64RegClassID : if ( ! Subtarget . hasAVX512 ( ) && Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; break ; case X86 :: VR128RegClassID : case X86 :: VR256RegClassID : if ( ! Subtarget . hasVLX ( ) && Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; break ; case X86 :: FR32XRegClassID : case X86 :: FR64XRegClassID : if ( ! Subtarget . hasVLX ( ) ) break ; case X86 :: VR128XRegClassID : case X86 :: VR256XRegClassID : if ( ! Subtarget . hasAVX512 ( ) ) break ; case X86 :: GR8RegClassID : case X86 :: GR16RegClassID : case X86 :: GR32RegClassID : case X86 :: GR64RegClassID : case X86 :: RFP32RegClassID : case X86 :: RFP64RegClassID : case X86 :: RFP80RegClassID : case X86 :: VR512RegClassID : if ( Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; } Super = * I ++ ; } while ( Super ) ; return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .


<s>
char
*
xstormy16_output_cbranch_hi
(
rtx
op
,
const
char
*
label
,
int
reversed
,
rtx_insn
*
insn
)
{
static
char
string
[
64
]
;
int
need_longbranch
=
(
op
!=
NULL_RTX
get_attr_length
(
insn
)
==
8
:
get_attr_length
(
insn
)
==
4
)
;
int
really_reversed
=
reversed
^
need_longbranch
;
const
char
*
ccode
;
const
char
*
templ
;
const
char
*
operands
;
enum
rtx_code
code
;
if
(
!
op
)
{
if
(
need_longbranch
)
ccode
=
"jmpf"
;
else
ccode
=
"br"
;
sprintf
(
string
,
"%s %s"
,
ccode
,
label
)
;
return
string
;
}
code
=
GET_CODE
(
op
)
;
if
(
!
REG_P
(
XEXP
(
op
,
0
)
)
)
{
code
=
swap_condition
(
code
)
;
operands
=
"%3,%2"
;
}
else
operands
=
"%2,%3"
;
if
(
really_reversed
)
code
=
reverse_condition
(
code
)
;
switch
(
code
)
{
case
EQ
:
ccode
=
"z"
;
break
;
case
NE
:
ccode
=
"nz"
;
break
;
case
GE
:
ccode
=
"ge"
;
break
;
case
LT
:
ccode
=
"lt"
;
break
;
case
GT
:
ccode
=
"gt"
;
break
;
case
LE
:
ccode
=
"le"
;
break
;
case
GEU
:
ccode
=
"nc"
;
break
;
case
LTU
:
ccode
=
"c"
;
break
;
case
GTU
:
ccode
=
"hi"
;
break
;
case
LEU
:
ccode
=
"ls"
;
break
;
default
:
gcc_unreachable
(
)
;
}
if
(
need_longbranch
)
templ
=
"b%s %s,.+8 | jmpf %s"
;
else
templ
=
"b%s %s,%s"
;
sprintf
(
string
,
templ
,
ccode
,
operands
,
label
)
;
return
string
;
}
</s>

Return the string to output a conditional branch to LABEL , which is the operand number of the label . OP is the conditional expression , or NULL for branch-always . REVERSED is non-zero if we should reverse the sense of the comparison . INSN is the insn .


<s> bool MipsLongBranch :: runOnMachineFunction ( MachineFunction & F ) { const MipsInstrInfo * TII = static_cast < const MipsInstrInfo * > ( TM . getInstrInfo ( ) ) ; if ( TM . getSubtarget < MipsSubtarget > ( ) . inMips16Mode ( ) ) return false ; if ( ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) && TM . getSubtarget < MipsSubtarget > ( ) . isABI_O32 ( ) && F . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; if ( ! ForceLongBranch && isInt < 16 > ( computeOffset ( I -> Br ) / 4 ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * 4 ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { uint64_t Address = 0 ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ; } for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) if ( I -> HasLongBranch ) expandToLongBranch ( * I ) ; MF -> RenumberBlocks ( ) ; return true ; } </s>

Mips Mips Mips Mips Mips Mips Mips Mips 16 4 4 0


"Tiny codesize model not supported on X86"

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s> SDValue SparcTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , SDLoc DL , SelectionDAG & DAG ) const { if ( Subtarget -> is64Bit ( ) ) return LowerReturn_64 ( Chain , CallConv , IsVarArg , Outs , OutVals , DL , DAG ) ; return LowerReturn_32 ( Chain , CallConv , IsVarArg , Outs , OutVals , DL , DAG ) ; } </s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool AArch64TargetLowering :: isLegalICmpImmediate ( int64_t Immed ) const { return isLegalAddImmediate ( Immed ) ; } </s>

Return true if the specified immediate is legal icmp immediate , that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register .


<s> EVT ARMTargetLowering :: getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const { if ( ( Op . isMemcpy ( ) || Op . isZeroMemset ( ) ) && Subtarget -> hasNEON ( ) && ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { bool Fast ; if ( Op . size ( ) >= 16 && ( Op . isAligned ( Align ( 16 ) ) || ( allowsMisalignedMemoryAccesses ( MVT :: v2f64 , 0 , 1 , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) { return MVT :: v2f64 ; } else if ( Op . size ( ) >= 8 && ( Op . isAligned ( Align ( 8 ) ) || ( allowsMisalignedMemoryAccesses ( MVT :: f64 , 0 , 1 , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) { return MVT :: f64 ; } } return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> bool mips_mem_fits_mode_p ( machine_mode mode , rtx x ) { return ( MEM_P ( x ) && MEM_SIZE_KNOWN_P ( x ) && MEM_SIZE ( x ) == GET_MODE_SIZE ( mode ) ) ; } </s>

Return true if X is a MEM with the same size as MODE .