<s>
static
int
rs6000_sched_reorder2
(
FILE
*
dump
,
int
sched_verbose
,
rtx_insn
*
*
ready
,
int
*
pn_ready
,
int
clock_var
ATTRIBUTE_UNUSED
)
{
if
(
sched_verbose
)
fprintf
(
dump
,
"// rs6000_sched_reorder2 :\n"
)
;
if
(
rs6000_tune
==
PROCESSOR_POWER6
&&
last_scheduled_insn
)
return
power6_sched_reorder2
(
ready
,
*
pn_ready
1
)
;
if
(
rs6000_tune
==
PROCESSOR_POWER9
&&
last_scheduled_insn
&&
recog_memoized
(
last_scheduled_insn
)
>=
0
)
return
power9_sched_reorder2
(
ready
,
*
pn_ready
1
)
;
if
(
rs6000_tune
==
PROCESSOR_POWER10
&&
last_scheduled_insn
)
return
power10_sched_reorder
(
ready
,
*
pn_ready
1
)
;
return
cached_can_issue_more
;
}
</s>

Like rs6000_sched_reorder , but called after issuing each insn .


<s> bool SparcFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void WebAssemblyFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { auto & MFI = MF . getFrameInfo ( ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( ! needsSP ( MF , MFI ) || ! needsSPWriteback ( MF , MFI ) ) return ; const auto * TII = MF . getSubtarget < WebAssemblySubtarget > ( ) . getInstrInfo ( ) ; auto & MRI = MF . getRegInfo ( ) ; auto InsertPt = MBB . getFirstTerminator ( ) ; DebugLoc DL ; if ( InsertPt != MBB . end ( ) ) DL = InsertPt -> getDebugLoc ( ) ; unsigned SPReg = 0 ; MachineBasicBlock :: iterator InsertAddr = InsertPt ; if ( hasBP ( MF ) ) { auto FI = MF . getInfo < WebAssemblyFunctionInfo > ( ) ; SPReg = FI -> getBasePointerVreg ( ) ; } else if ( StackSize ) { const TargetRegisterClass * PtrRC = MRI . getTargetRegisterInfo ( ) -> getPointerRegClass ( MF ) ; unsigned OffsetReg = MRI . createVirtualRegister ( PtrRC ) ; InsertAddr = BuildMI ( MBB , InsertPt , DL , TII -> get ( WebAssembly :: CONST_I32 ) , OffsetReg ) . addImm ( StackSize ) ; SPReg = MRI . createVirtualRegister ( PtrRC ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( WebAssembly :: ADD_I32 ) , SPReg ) . addReg ( hasFP ( MF ) ? WebAssembly :: FP32 : WebAssembly :: SP32 ) . addReg ( OffsetReg ) ; } else { SPReg = hasFP ( MF ) ? WebAssembly :: FP32 : WebAssembly :: SP32 ; } writeSPToMemory ( SPReg , MF , MBB , InsertAddr , InsertPt , DL ) ; } </s>


<s> rtx extract_base_reg ( rtx_insn * insn ) { int post_update_rtx_index ; rtx mem_rtx ; rtx plus_rtx ; switch ( get_attr_type ( insn ) ) { case TYPE_LOAD_MULTIPLE : post_update_rtx_index = find_post_update_rtx ( insn ) ; if ( post_update_rtx_index != - 1 ) return SET_DEST ( parallel_element ( insn , post_update_rtx_index ) ) ; mem_rtx = SET_SRC ( parallel_element ( insn , 0 ) ) ; break ; case TYPE_STORE_MULTIPLE : post_update_rtx_index = find_post_update_rtx ( insn ) ; if ( post_update_rtx_index != - 1 ) return SET_DEST ( parallel_element ( insn , post_update_rtx_index ) ) ; mem_rtx = SET_DEST ( parallel_element ( insn , 0 ) ) ; break ; case TYPE_LOAD : case TYPE_FLOAD : case TYPE_STORE : case TYPE_FSTORE : mem_rtx = extract_mem_rtx ( insn ) ; break ; default : gcc_unreachable ( ) ; } gcc_assert ( MEM_P ( mem_rtx ) ) ; if ( REG_P ( XEXP ( mem_rtx , 0 ) ) ) return XEXP ( mem_rtx , 0 ) ; plus_rtx = XEXP ( mem_rtx , 0 ) ; if ( GET_CODE ( plus_rtx ) == SYMBOL_REF || GET_CODE ( plus_rtx ) == CONST ) return NULL_RTX ; gcc_assert ( GET_CODE ( plus_rtx ) == PLUS || GET_CODE ( plus_rtx ) == POST_INC || GET_CODE ( plus_rtx ) == POST_DEC || GET_CODE ( plus_rtx ) == POST_MODIFY ) ; gcc_assert ( REG_P ( XEXP ( plus_rtx , 0 ) ) ) ; return XEXP ( plus_rtx , 0 ) ; } </s>

Extract the base register from load/store insns . The function returns NULL_RTX if the address is not consist of any registers .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addRequired < ScalarEvolutionWrapperPass > ( ) ; AU . addRequired < AssumptionCacheTracker > ( ) ; AU . addRequired < TargetTransformInfoWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void XCoreTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , APInt & KnownZero , APInt & KnownOne , const SelectionDAG & DAG , unsigned Depth ) const { KnownZero = KnownOne = APInt ( KnownZero . getBitWidth ( ) , 0 ) ; switch ( Op . getOpcode ( ) ) { default : break ; case XCoreISD :: LADD : case XCoreISD :: LSUB : if ( Op . getResNo ( ) == 1 ) { KnownZero = APInt :: getHighBitsSet ( KnownZero . getBitWidth ( ) , KnownZero . getBitWidth ( ) - 1 ) ; } break ; case ISD :: INTRINSIC_W_CHAIN : { unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) -> getZExtValue ( ) ; switch ( IntNo ) { case Intrinsic :: xcore_getts : KnownZero = APInt :: getHighBitsSet ( KnownZero . getBitWidth ( ) , KnownZero . getBitWidth ( ) - 16 ) ; break ; case Intrinsic :: xcore_int : case Intrinsic :: xcore_inct : KnownZero = APInt :: getHighBitsSet ( KnownZero . getBitWidth ( ) , KnownZero . getBitWidth ( ) - 8 ) ; break ; case Intrinsic :: xcore_testct : KnownZero = APInt :: getHighBitsSet ( KnownZero . getBitWidth ( ) , KnownZero . getBitWidth ( ) - 1 ) ; break ; case Intrinsic :: xcore_testwct : KnownZero = APInt :: getHighBitsSet ( KnownZero . getBitWidth ( ) , KnownZero . getBitWidth ( ) - 3 ) ; break ; } } break ; } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s>
const
char
*
mips_output_order_conditional_branch
(
rtx_insn
*
insn
,
rtx
*
operands
,
bool
inverted_p
)
{
const
char
*
branch
[
2
]
;
if
(
operands
[
3
]
!=
const0_rtx
)
{
if
(
REGNO
(
operands
[
2
]
)
==
REGNO
(
operands
[
3
]
)
)
{
switch
(
GET_CODE
(
operands
[
1
]
)
)
{
case
LT
:
case
LTU
:
inverted_p
=
!
inverted_p
;
case
GE
:
case
GEU
:
branch
[
!
inverted_p
]
=
MIPS_BRANCH_C
(
"b"
,
"%0"
)
;
branch
[
inverted_p
]
=
"%*\t\t# branch never"
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
else
{
branch
[
!
inverted_p
]
=
MIPS_BRANCH_C
(
"b%C1"
,
"%2,%3,%0"
)
;
branch
[
inverted_p
]
=
MIPS_BRANCH_C
(
"b%N1"
,
"%2,%3,%0"
)
;
}
}
else
{
switch
(
GET_CODE
(
operands
[
1
]
)
)
{
case
LEU
:
inverted_p
=
!
inverted_p
;
case
GTU
:
if
(
TARGET_CB_MAYBE
)
{
branch
[
!
inverted_p
]
=
MIPS_BRANCH_C
(
"bnez"
,
"%2,%0"
)
;
branch
[
inverted_p
]
=
MIPS_BRANCH_C
(
"beqz"
,
"%2,%0"
)
;
}
else
{
branch
[
!
inverted_p
]
=
MIPS_BRANCH
(
"bne"
,
"%2,%.,%0"
)
;
branch
[
inverted_p
]
=
MIPS_BRANCH
(
"beq"
,
"%2,%.,%0"
)
;
}
break
;
case
LTU
:
inverted_p
=
!
inverted_p
;
case
GEU
:
if
(
TARGET_CB_MAYBE
)
{
branch
[
!
inverted_p
]
=
MIPS_BRANCH_C
(
"b"
,
"%0"
)
;
branch
[
inverted_p
]
=
"%*\t\t# branch never"
;
}
else
{
branch
[
!
inverted_p
]
=
MIPS_BRANCH
(
"beq"
,
"%.,%.,%0"
)
;
branch
[
inverted_p
]
=
MIPS_BRANCH
(
"bne"
,
"%.,%.,%0"
)
;
}
break
;
default
:
if
(
TARGET_CB_MAYBE
)
{
branch
[
!
inverted_p
]
=
MIPS_BRANCH_C
(
"b%C1z"
,
"%2,%0"
)
;
branch
[
inverted_p
]
=
MIPS_BRANCH_C
(
"b%N1z"
,
"%2,%0"
)
;
}
else
{
branch
[
!
inverted_p
]
=
MIPS_BRANCH
(
"b%C1z"
,
"%2,%0"
)
;
branch
[
inverted_p
]
=
MIPS_BRANCH
(
"b%N1z"
,
"%2,%0"
)
;
}
break
;
}
}
return
mips_output_conditional_branch
(
insn
,
operands
,
branch
[
1
]
,
branch
[
0
]
)
;
}
</s>

Return the assembly code for INSN , which branches to OPERANDS [ 0 ] if some ordering condition is true . The condition is given by OPERANDS [ 1 ] if ! INVERTED_P , otherwise it is the inverse of OPERANDS [ 1 ] . OPERANDS [ 2 ] is the comparison 's first operand ; its second is always zero .


<s> void frv_expand_prologue ( void ) { frv_stack_t * info = frv_stack_info ( ) ; rtx sp = stack_pointer_rtx ; rtx fp = frame_pointer_rtx ; frv_frame_accessor_t accessor ; if ( TARGET_DEBUG_STACK ) frv_debug_stack ( info ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = info -> total_size ; if ( info -> total_size == 0 ) return ; accessor . op = FRV_STORE ; if ( frame_pointer_needed && info -> total_size > 2048 ) { accessor . base = gen_rtx_REG ( Pmode , OLD_SP_REGNO ) ; accessor . base_offset = info -> total_size ; emit_insn ( gen_movsi ( accessor . base , sp ) ) ; } else { accessor . base = stack_pointer_rtx ; accessor . base_offset = 0 ; } { rtx asm_offset = frv_frame_offset_rtx ( - info -> total_size ) ; rtx dwarf_offset = GEN_INT ( - info -> total_size ) ; frv_frame_insn ( gen_stack_adjust ( sp , sp , asm_offset ) , gen_rtx_SET ( sp , gen_rtx_PLUS ( Pmode , sp , dwarf_offset ) ) ) ; } if ( frame_pointer_needed ) { int fp_offset = info -> reg_offset [ FRAME_POINTER_REGNUM ] ; rtx asm_src = plus_constant ( Pmode , accessor . base , fp_offset - accessor . base_offset ) ; rtx dwarf_src = plus_constant ( Pmode , sp , fp_offset ) ; frv_frame_access ( & accessor , fp , fp_offset ) ; frv_frame_insn ( gen_rtx_SET ( fp , asm_src ) , gen_rtx_SET ( fp , dwarf_src ) ) ; accessor . base = fp ; accessor . base_offset = fp_offset ; } frv_frame_access_multi ( & accessor , info , STACK_REGS_STRUCT ) ; frv_frame_access_multi ( & accessor , info , STACK_REGS_LR ) ; frv_frame_access_multi ( & accessor , info , STACK_REGS_STDARG ) ; frv_frame_access_standard_regs ( FRV_STORE , info ) ; if ( info -> stdarg_size > 0 ) emit_insn ( gen_blockage ( ) ) ; if ( ! TARGET_FDPIC && flag_pic && crtl -> uses_pic_offset_table ) emit_insn ( gen_pic_prologue ( gen_rtx_REG ( Pmode , PIC_REGNO ) , gen_rtx_REG ( Pmode , LR_REGNO ) , gen_rtx_REG ( SImode , OFFSET_REGNO ) ) ) ; } </s>

Called after register allocation to add any instructions needed for the prologue . Using a prologue insn is favored compared to putting all of the instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook , since it allows the scheduler to intermix instructions with the saves of the caller saved registers . In some cases , it might be necessary to emit a barrier instruction as the last insn to prevent such scheduling . Also any insns generated here should have RTX_FRAME_RELATED_P ( insn ) = 1 so that the debug info generation code can handle them properly .


runOnMachineFunction - Emit the function body .


<s> static tree find_sole_member ( tree type ) { tree field , member = NULL_TREE ; for ( field = TYPE_FIELDS ( type ) ; field ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( ! DECL_SIZE ( field ) ) return NULL_TREE ; if ( integer_zerop ( DECL_SIZE ( field ) ) ) continue ; if ( member ) return NULL_TREE ; member = field ; } return member ; } </s>

TYPE is a RECORD_TYPE . If there is only a single non-zero-sized member , return it .


<s> unsigned MipsTargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT . isVector ( ) ) return divideCeil ( VT . getSizeInBits ( ) , Subtarget . isABI_O32 ( ) ? 32 : 64 ) ; return MipsTargetLowering :: getNumRegisters ( Context , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s>
SDValue
MBlazeTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_MBlaze
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
unsigned
Ret
=
(
CallConv
==
CallingConv
::
MBLAZE_INTR
)
MBlazeISD
::
IRet
:
MBlazeISD
::
Ret
;
unsigned
Reg
=
(
CallConv
==
CallingConv
::
MBLAZE_INTR
)
MBlaze
::
R14
:
MBlaze
::
R15
;
RetOps
.
push_back
(
DAG
.
getRegister
(
Reg
,
MVT
::
i32
)
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
Ret
,
dl
,
MVT
::
Other
,
&
RetOps
[
0
]
,
RetOps
.
size
(
)
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void X86InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC ) const { const MachineFunction & MF = * MBB . getParent ( ) ; bool isAligned = ( RI . getStackAlignment ( ) >= 16 ) || RI . needsStackRealignment ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , TM ) ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) , DestReg ) , FrameIdx ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addPreservedID ( MachineLoopInfoID ) ; AU . addPreservedID ( MachineDominatorsID ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> static tree altivec_build_resolved_builtin ( tree * args , int n , const struct altivec_builtin_types * desc ) { tree impl_fndecl = rs6000_builtin_decls [ desc -> overloaded_code ] ; tree ret_type = rs6000_builtin_type ( desc -> ret_type ) ; tree argtypes = TYPE_ARG_TYPES ( TREE_TYPE ( impl_fndecl ) ) ; tree arg_type [ 3 ] ; tree call ; int i ; for ( i = 0 ; i < n ; i ++ ) arg_type [ i ] = TREE_VALUE ( argtypes ) , argtypes = TREE_CHAIN ( argtypes ) ; if ( desc -> code == ALTIVEC_BUILTIN_VEC_VCMPGE_P && desc -> overloaded_code != ALTIVEC_BUILTIN_VCMPGEFP_P && desc -> overloaded_code != VSX_BUILTIN_XVCMPGEDP_P ) { tree t ; t = args [ 2 ] , args [ 2 ] = args [ 1 ] , args [ 1 ] = t ; t = arg_type [ 2 ] , arg_type [ 2 ] = arg_type [ 1 ] , arg_type [ 1 ] = t ; args [ 0 ] = fold_build2 ( BIT_XOR_EXPR , TREE_TYPE ( args [ 0 ] ) , args [ 0 ] , build_int_cst ( NULL_TREE , 2 ) ) ; } switch ( n ) { case 0 : call = build_call_expr ( impl_fndecl , 0 ) ; break ; case 1 : call = build_call_expr ( impl_fndecl , 1 , fully_fold_convert ( arg_type [ 0 ] , args [ 0 ] ) ) ; break ; case 2 : call = build_call_expr ( impl_fndecl , 2 , fully_fold_convert ( arg_type [ 0 ] , args [ 0 ] ) , fully_fold_convert ( arg_type [ 1 ] , args [ 1 ] ) ) ; break ; case 3 : call = build_call_expr ( impl_fndecl , 3 , fully_fold_convert ( arg_type [ 0 ] , args [ 0 ] ) , fully_fold_convert ( arg_type [ 1 ] , args [ 1 ] ) , fully_fold_convert ( arg_type [ 2 ] , args [ 2 ] ) ) ; break ; default : gcc_unreachable ( ) ; } return fold_convert ( ret_type , call ) ; } </s>

Build a tree for a function call to an Altivec non-overloaded builtin . The overloaded builtin that matched the types and args is described by DESC . The N arguments are given in ARGS , respectively . Actually the only thing it does is calling fold_convert on ARGS , with a small exception for vec_ { all , any } _ { ge , le } predicates .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> bool GCNPreRAOptimizations :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; LIS = & getAnalysis < LiveIntervals > ( ) ; const SIRegisterInfo * TRI = ST . getRegisterInfo ( ) ; bool Changed = false ; for ( unsigned I = 0 , E = MRI -> getNumVirtRegs ( ) ; I != E ; ++ I ) { Register Reg = Register :: index2VirtReg ( I ) ; if ( ! LIS -> hasInterval ( Reg ) ) continue ; const TargetRegisterClass * RC = MRI -> getRegClass ( Reg ) ; if ( RC -> MC -> getSizeInBits ( ) != 64 || ! TRI -> isSGPRClass ( RC ) ) continue ; Changed |= processReg ( Reg ) ; } return Changed ; } </s>


<s> const MCExpr * X86_64MachoTargetObjectFile :: getTTypeGlobalReference ( const GlobalValue * GV , unsigned Encoding , Mangler & Mang , const TargetMachine & TM , MachineModuleInfo * MMI , MCStreamer & Streamer ) const { if ( Encoding & ( DW_EH_PE_indirect | DW_EH_PE_pcrel ) ) { const MCSymbol * Sym = TM . getSymbol ( GV , Mang ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_GOTPCREL , getContext ( ) ) ; const MCExpr * Four = MCConstantExpr :: Create ( 4 , getContext ( ) ) ; return MCBinaryExpr :: CreateAdd ( Res , Four , getContext ( ) ) ; } return TargetLoweringObjectFileMachO :: getTTypeGlobalReference ( GV , Encoding , Mang , TM , MMI , Streamer ) ; } </s>

The mach-o version of this method defaults to returning a stub reference .


<s> bool HexagonGenInsert :: removeDeadCode ( MachineDomTreeNode * N ) { bool Changed = false ; for ( auto * DTN : children < MachineDomTreeNode * > ( N ) ) Changed |= removeDeadCode ( DTN ) ; MachineBasicBlock * B = N -> getBlock ( ) ; std :: vector < MachineInstr * > Instrs ; for ( auto I = B -> rbegin ( ) , E = B -> rend ( ) ; I != E ; ++ I ) Instrs . push_back ( & * I ) ; for ( auto I = Instrs . begin ( ) , E = Instrs . end ( ) ; I != E ; ++ I ) { MachineInstr * MI = * I ; unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == TargetOpcode :: LIFETIME_START || Opc == TargetOpcode :: LIFETIME_END ) continue ; bool Store = false ; if ( MI -> isInlineAsm ( ) || ! MI -> isSafeToMove ( nullptr , Store ) ) continue ; bool AllDead = true ; SmallVector < unsigned , 2 > Regs ; for ( const MachineOperand & MO : MI -> operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; Register R = MO . getReg ( ) ; if ( ! Register :: isVirtualRegister ( R ) || ! MRI -> use_nodbg_empty ( R ) ) { AllDead = false ; break ; } Regs . push_back ( R ) ; } if ( ! AllDead ) continue ; B -> erase ( MI ) ; for ( unsigned I = 0 , N = Regs . size ( ) ; I != N ; ++ I ) MRI -> markUsesInDebugValueAsUndef ( Regs [ I ] ) ; Changed = true ; } return Changed ; } </s>

Remove all dead instructions between the I and E .


<s> bool HexagonInstrInfo :: canExecuteInBundle ( const MachineInstr & First , const MachineInstr & Second ) const { if ( DisableNVSchedule ) return false ; if ( mayBeNewStore ( Second ) ) { const MachineOperand & Stored = Second . getOperand ( Second . getNumOperands ( ) - 1 ) ; if ( ! Stored . isReg ( ) ) return false ; for ( unsigned i = 0 , e = First . getNumOperands ( ) ; i < e ; ++ i ) { const MachineOperand & Op = First . getOperand ( i ) ; if ( Op . isReg ( ) && Op . isDef ( ) && Op . getReg ( ) == Stored . getReg ( ) ) return true ; } } return false ; } </s>

Can these instructions execute at the same time in a bundle .


<s> static const MachineOperand & getLdStBaseOp ( const MachineInstr * MI ) { return MI -> getOperand ( 1 ) ; } </s>

Returns the base register operator of a load/store .


"Custom lowering not defined for operation"

LowerOperation - Provide custom lowering hooks for some operations .


<s> static rtx ix86_static_chain ( const_tree fndecl_or_type , bool incoming_p ) { unsigned regno ; if ( DECL_P ( fndecl_or_type ) && ! DECL_STATIC_CHAIN ( fndecl_or_type ) ) return NULL ; if ( TARGET_64BIT ) { regno = R10_REG ; } else { const_tree fntype , fndecl ; unsigned int ccvt ; regno = CX_REG ; if ( TREE_CODE ( fndecl_or_type ) == FUNCTION_DECL ) { fntype = TREE_TYPE ( fndecl_or_type ) ; fndecl = fndecl_or_type ; } else { fntype = fndecl_or_type ; fndecl = NULL ; } ccvt = ix86_get_callcvt ( fntype ) ; if ( ( ccvt & IX86_CALLCVT_FASTCALL ) != 0 ) { regno = AX_REG ; } else if ( ( ccvt & IX86_CALLCVT_THISCALL ) != 0 ) { regno = AX_REG ; } else if ( ix86_function_regparm ( fntype , fndecl ) == 3 ) { if ( incoming_p ) { if ( fndecl == current_function_decl ) ix86_static_chain_on_stack = true ; return gen_frame_mem ( SImode , plus_constant ( Pmode , arg_pointer_rtx , - 8 ) ) ; } regno = SI_REG ; } } return gen_rtx_REG ( Pmode , regno ) ; } </s>

Find a location for the static chain incoming to a nested function . This is a register , unless all free registers are used by arguments .


<s> const char * VETargetLowering :: getTargetNodeName ( unsigned Opcode ) const { case VEISD :: NAME : \ return "VEISD::" # NAME ; switch ( ( VEISD :: NodeType ) Opcode ) { case VEISD :: FIRST_NUMBER : break ; TARGET_NODE_CASE ( CALL ) TARGET_NODE_CASE ( GETFUNPLT ) TARGET_NODE_CASE ( GETSTACKTOP ) TARGET_NODE_CASE ( GETTLSADDR ) TARGET_NODE_CASE ( GLOBAL_BASE_REG ) TARGET_NODE_CASE ( Hi ) TARGET_NODE_CASE ( Lo ) TARGET_NODE_CASE ( MEMBARRIER ) TARGET_NODE_CASE ( RET_FLAG ) TARGET_NODE_CASE ( TS1AM ) TARGET_NODE_CASE ( VEC_BROADCAST ) } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

VE VE VEISD::NAME "VEISD::" VEISD::NodeType VEISD::FIRST_NUMBER VE


<s> bool contains ( const MachineBasicBlock * MBB ) const override { return Region -> contains ( MBB ) ; } </s>

contains - Returns true if this trace contains the given basic block .


<s> ARMRelocator :: Result unsupported ( Relocation & pReloc , ARMRelocator & pParent ) { return Relocator :: Unsupported ; } </s>


<s> MipsSubtarget & MipsSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS , const TargetMachine * TM ) { std :: string CPUName = selectMipsCPU ( TargetTriple , CPU ) ; ParseSubtargetFeatures ( CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( InMips16Mode && ! TM -> Options . UseSoftFloat ) { TM -> Options . UseSoftFloat = true ; TM -> Options . FloatABIType = FloatABI :: Soft ; InMips16HardFloat = true ; } return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


"/* This table has been generated by divtab-sh4.cc.  */"

"\ /* 1/-128 .. 1/127, normalized.  There is an implicit leading 1 in bit 32,\n\ or in bit 33 for powers of two.  */\n\ .balign 4"

Main program to convert flat files into built-in initialization code .


"  Skipping pass: no machine model present.\n"


<s> bool AArch64CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) == 0 ) continue ; ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , F . getCallingConv ( ) ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; if ( F . isVarArg ( ) ) { if ( ! MF . getSubtarget < AArch64Subtarget > ( ) . isTargetDarwin ( ) ) { return false ; } uint64_t StackOffset = alignTo ( Handler . StackUsed , 8 ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; AArch64FunctionInfo * FuncInfo = MF . getInfo < AArch64FunctionInfo > ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( 4 , StackOffset , true ) ) ; } auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; if ( Subtarget . hasCustomCallingConv ( ) ) Subtarget . getRegisterInfo ( ) -> UpdateCustomCalleeSavedRegs ( MF ) ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> bool LanaiTargetObjectFile :: isGlobalInSmallSection ( const GlobalObject * GO , const TargetMachine & TM , SectionKind Kind ) const { return ( isGlobalInSmallSectionImpl ( GO , TM ) && ( Kind . isData ( ) || Kind . isBSS ( ) || Kind . isCommon ( ) ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> const uint16_t * AVRRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { CallingConv :: ID CC = MF -> getFunction ( ) -> getCallingConv ( ) ; return ( ( CC == CallingConv :: AVR_INTR || CC == CallingConv :: AVR_SIGNAL ) ? CSR_Interrupts_SaveList : CSR_Normal_SaveList ) ; } </s>


<s> void AMDGPUInstructionSelector :: setupMF ( MachineFunction & MF , GISelKnownBits & KB , CodeGenCoverage & CoverageInfo ) { MRI = & MF . getRegInfo ( ) ; Subtarget = & MF . getSubtarget < GCNSubtarget > ( ) ; InstructionSelector :: setupMF ( MF , KB , CoverageInfo ) ; } </s>


<s> bool n8_consumed_by_ex_p ( rtx_insn * consumer , rtx def_reg ) { rtx use_rtx ; switch ( get_attr_type ( consumer ) ) { case TYPE_ALU : if ( movd44_even_dep_p ( consumer , def_reg ) ) return true ; use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_MUL : use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_MAC : use_rtx = extract_mac_non_acc_rtx ( consumer ) ; break ; case TYPE_DIV : if ( divmod_p ( consumer ) ) use_rtx = SET_SRC ( parallel_element ( consumer , 0 ) ) ; else use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_BRANCH : use_rtx = extract_branch_condition_rtx ( consumer ) ; break ; case TYPE_STORE : if ( ! post_update_insn_p ( consumer ) && ! immed_offset_p ( extract_mem_rtx ( consumer ) ) ) return false ; use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_STORE_MULTIPLE : use_rtx = extract_nth_access_rtx ( consumer , 0 ) ; break ; default : gcc_unreachable ( ) ; } return reg_overlap_p ( def_reg , use_rtx ) ; } </s>

Check the dependency between the producer defining DEF_REG and CONSUMER requiring input operand at EX .


<s> bool ARMPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None && ! getARMSubtarget ( ) . isThumb1Only ( ) ) addPass ( createARMLoadStoreOptimizationPass ( true ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None && getARMSubtarget ( ) . isLikeA9 ( ) ) addPass ( createMLxExpansionPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s>
LLVM_DUMP_METHOD
void
RangeTree
::
dump
(
const
Node
*
N
)
const
{
dbgs
(
)
<<
"Node: "
<<
N
<<
'\n'
;
dbgs
(
)
<<
"  Height: "
<<
N
->
Height
<<
'\n'
;
dbgs
(
)
<<
"  Count: "
<<
N
->
Count
<<
'\n'
;
dbgs
(
)
<<
"  MaxEnd: "
<<
N
->
MaxEnd
<<
'\n'
;
dbgs
(
)
<<
"  Range: "
<<
N
->
Range
<<
'\n'
;
dbgs
(
)
<<
"  Left: "
<<
N
->
Left
<<
'\n'
;
dbgs
(
)
<<
"  Right: "
<<
N
->
Right
<<
"\n\n"
;
if
(
N
->
Left
)
dump
(
N
->
Left
)
;
if
(
N
->
Right
)
dump
(
N
->
Right
)
;
}
</s>

Dump the plan to stderr ( for debugging ) .

Hexagon
"Node: "
"  Height: "
"  Count: "
"  MaxEnd: "
"  Range: "
"  Left: "
"  Right: "
"\n\n"


<s> TargetIRAnalysis AMDGPUTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( Function & F ) { return TargetTransformInfo ( AMDGPUTTIImpl ( this ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


<s> ARMConstantPoolMBB * ARMConstantPoolMBB :: Create ( LLVMContext & C , const MachineBasicBlock * mbb , unsigned ID , unsigned char PCAdj ) { return new ARMConstantPoolMBB ( C , mbb , ID , PCAdj , ARMCP :: no_modifier , false ) ; } </s>

Construct a unary instruction , given the opcode and an operand .


<s> bool X86TargetLowering :: isCommutativeBinOp ( unsigned Opcode ) const { switch ( Opcode ) { case X86ISD :: PMULUDQ : return true ; } return TargetLoweringBase :: isCommutativeBinOp ( Opcode ) ; } </s>

Returns true if the opcode is a commutative binary operation .


<s> PreservedAnalyses AMDGPULowerKernelAttributesPass :: run ( Function & F , FunctionAnalysisManager & AM ) { StringRef DispatchPtrName = Intrinsic :: getName ( Intrinsic :: amdgcn_dispatch_ptr ) ; Function * DispatchPtr = F . getParent ( ) -> getFunction ( DispatchPtrName ) ; if ( ! DispatchPtr ) return PreservedAnalyses :: all ( ) ; for ( Instruction & I : instructions ( F ) ) { if ( CallInst * CI = dyn_cast < CallInst > ( & I ) ) { if ( CI -> getCalledFunction ( ) == DispatchPtr ) processUse ( CI ) ; } } return PreservedAnalyses :: all ( ) ; } </s>

Run the analysis pass over a function and produce a dominator tree .

AMDGPU AMDGPU Intrinsic::getName Intrinsic::amdgcn_dispatch_ptr


<s> enum riscv_symbol_type riscv_classify_symbolic_expression ( rtx x ) { rtx offset ; split_const ( x , & x , & offset ) ; if ( UNSPEC_ADDRESS_P ( x ) ) return UNSPEC_ADDRESS_TYPE ( x ) ; return riscv_classify_symbol ( x ) ; } </s>

Classify the base of symbolic expression X .


<s> void riscv_expand_prologue ( void ) { struct riscv_frame_info * frame = & cfun -> machine -> frame ; HOST_WIDE_INT size = frame -> total_size ; unsigned mask = frame -> mask ; rtx insn ; if ( flag_stack_usage_info ) current_function_static_stack_size = size ; if ( cfun -> machine -> naked_p ) return ; if ( riscv_use_save_libcall ( frame ) ) { rtx dwarf = NULL_RTX ; dwarf = riscv_adjust_libcall_cfi_prologue ( ) ; size -= frame -> save_libcall_adjustment ; insn = emit_insn ( riscv_gen_gpr_save_insn ( frame ) ) ; frame -> mask = 0 ; RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = dwarf ; } if ( ( frame -> mask | frame -> fmask ) != 0 ) { HOST_WIDE_INT step1 = MIN ( size , riscv_first_stack_step ( frame ) ) ; insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = 1 ; size -= step1 ; riscv_for_each_saved_reg ( size , riscv_save_reg , false , false ) ; } frame -> mask = mask ; if ( frame_pointer_needed ) { insn = gen_add3_insn ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( frame -> hard_frame_pointer_offset - size ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = 1 ; riscv_emit_stack_tie ( ) ; } if ( size > 0 ) { if ( SMALL_OPERAND ( - size ) ) { insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - size ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = 1 ; } else { riscv_emit_move ( RISCV_PROLOGUE_TEMP ( Pmode ) , GEN_INT ( - size ) ) ; emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , RISCV_PROLOGUE_TEMP ( Pmode ) ) ) ; insn = plus_constant ( Pmode , stack_pointer_rtx , - size ) ; insn = gen_rtx_SET ( stack_pointer_rtx , insn ) ; riscv_set_frame_expr ( insn ) ; } } } </s>


<s>
static
int
avr_address_cost
(
rtx
x
,
machine_mode
mode
ATTRIBUTE_UNUSED
,
addr_space_t
as
ATTRIBUTE_UNUSED
,
bool
speed
ATTRIBUTE_UNUSED
)
{
int
cost
=
4
;
if
(
GET_CODE
(
x
)
==
PLUS
&&
CONST_INT_P
(
XEXP
(
x
,
1
)
)
&&
(
REG_P
(
XEXP
(
x
,
0
)
)
||
GET_CODE
(
XEXP
(
x
,
0
)
)
==
SUBREG
)
)
{
if
(
INTVAL
(
XEXP
(
x
,
1
)
)
>=
61
)
cost
=
18
;
}
else
if
(
CONSTANT_ADDRESS_P
(
x
)
)
{
if
(
optimize
>
0
&&
io_address_operand
(
x
,
QImode
)
)
cost
=
2
;
}
if
(
avr_log
.
address_cost
)
avr_edump
(
"\n%?: %d = %r\n"
,
cost
,
x
)
;
return
cost
;
}
</s>

Calculate the cost of a memory address .


<s> static bool nios2_valid_compare_const_p ( enum rtx_code code , rtx op ) { switch ( code ) { case EQ : case NE : case GE : case LT : return SMALL_INT ( INTVAL ( op ) ) ; case GEU : case LTU : return SMALL_INT_UNSIGNED ( INTVAL ( op ) ) ; default : return false ; } } </s>

Return true if the constant comparison is supported by nios2 .


<s>
unsigned
char
X86Subtarget
::
ClassifyGlobalReference
(
const
GlobalValue
*
GV
,
const
TargetMachine
&
TM
)
const
{
if
(
GV
->
hasDLLImportLinkage
(
)
)
return
X86II
::
MO_DLLIMPORT
;
bool
isDecl
=
GV
->
hasAvailableExternallyLinkage
(
)
;
if
(
GV
->
isDeclaration
(
)
&&
!
GV
->
isMaterializable
(
)
)
isDecl
=
true
;
if
(
isPICStyleRIPRel
(
)
)
{
if
(
TM
.
getCodeModel
(
)
==
CodeModel
::
Large
)
return
X86II
::
MO_NO_FLAG
;
if
(
isTargetDarwin
(
)
)
{
if
(
GV
->
hasDefaultVisibility
(
)
&&
(
isDecl
||
GV
->
isWeakForLinker
(
)
)
)
return
X86II
::
MO_GOTPCREL
;
}
else
if
(
!
isTargetWin64
(
)
)
{
assert
(
isTargetELF
(
)
&&
"Unknown rip-relative target"
)
;
if
(
!
GV
->
hasLocalLinkage
(
)
&&
GV
->
hasDefaultVisibility
(
)
)
return
X86II
::
MO_GOTPCREL
;
}
return
X86II
::
MO_NO_FLAG
;
}
if
(
isPICStyleGOT
(
)
)
{
if
(
GV
->
hasLocalLinkage
(
)
||
GV
->
hasHiddenVisibility
(
)
)
return
X86II
::
MO_GOTOFF
;
return
X86II
::
MO_GOT
;
}
if
(
isPICStyleStubPIC
(
)
)
{
if
(
!
isDecl
&&
!
GV
->
isWeakForLinker
(
)
)
return
X86II
::
MO_PIC_BASE_OFFSET
;
if
(
!
GV
->
hasHiddenVisibility
(
)
)
return
X86II
::
MO_DARWIN_NONLAZY_PIC_BASE
;
if
(
isDecl
||
GV
->
hasCommonLinkage
(
)
)
{
return
X86II
::
MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE
;
}
return
X86II
::
MO_PIC_BASE_OFFSET
;
}
if
(
isPICStyleStubNoDynamic
(
)
)
{
if
(
!
isDecl
&&
!
GV
->
isWeakForLinker
(
)
)
return
X86II
::
MO_NO_FLAG
;
if
(
!
GV
->
hasHiddenVisibility
(
)
)
return
X86II
::
MO_DARWIN_NONLAZY
;
return
X86II
::
MO_NO_FLAG
;
}
return
X86II
::
MO_NO_FLAG
;
}
</s>

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be referenced for the current subtarget .


"Disassembly not yet supported for subtarget"

Returns the disassembly of a single instruction .


<s> unsigned SIInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const MCInstrDesc & Desc = getMCOpcodeFromPseudo ( Opc ) ; unsigned DescSize = Desc . getSize ( ) ; if ( isFixedSize ( MI ) ) return DescSize ; if ( isVALU ( MI ) || isSALU ( MI ) ) { int Src0Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src0 ) ; if ( Src0Idx == - 1 ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src0Idx ) , Desc . OpInfo [ Src0Idx ] ) ) return DescSize + 4 ; int Src1Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src1 ) ; if ( Src1Idx == - 1 ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src1Idx ) , Desc . OpInfo [ Src1Idx ] ) ) return DescSize + 4 ; int Src2Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src2 ) ; if ( Src2Idx == - 1 ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src2Idx ) , Desc . OpInfo [ Src2Idx ] ) ) return DescSize + 4 ; return DescSize ; } switch ( Opc ) { case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : case TargetOpcode :: EH_LABEL : return 0 ; case TargetOpcode :: BUNDLE : return getInstBundleSize ( MI ) ; case TargetOpcode :: INLINEASM : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } default : return DescSize ; } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


"%<-fexcess-precision=16%> is not supported on this target"

Implement TARGET_C_EXCESS_PRECISION to maintain historic behavior with older glibc versions For historical reasons , float_t and double_t had been typedef'ed to double on s390 , causing operations on float_t to operate in a higher precision than is necessary . However , it is not the case that SFmode operations have implicit excess precision , and we generate more optimal code if we let the compiler know no implicit extra precision is added . With a glibc with that `` historic '' definition , configure will enable this hook to set FLT_EVAL_METHOD to 1 for -fexcess-precision=standard ( e.g. , as implied by -std=cXY ) . That means when we are compiling with -fexcess-precision=fast , the value we set for FLT_EVAL_METHOD will be out of line with the actual precision of float_t . Newer versions of glibc will be modified to derive the definition of float_t from FLT_EVAL_METHOD on s390x , as on many other architectures . There , configure will disable this hook by default , so that we defer to the default of FLT_EVAL_METHOD_PROMOTE_TO_FLOAT and a resulting typedef of float_t to float . Note that in that scenario , float_t and FLT_EVAL_METHOD will be in line independent of -fexcess-precision .


<s> EVT M68kTargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & Context , EVT VT ) const { return MVT :: i8 ; } </s>

Return the value type to use for ISD : :SETCC .


<s> std :: pair < unsigned , const TargetRegisterClass * > BPFTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , & BPF :: GPRRegClass ) ; default : break ; } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> bool builtin_type_p ( const_tree type , unsigned int * num_zr , unsigned int * num_pr ) { if ( tree attr = lookup_sve_type_attribute ( type ) ) { tree num_zr_node = TREE_VALUE ( attr ) ; tree num_pr_node = TREE_CHAIN ( num_zr_node ) ; * num_zr = tree_to_uhwi ( TREE_VALUE ( num_zr_node ) ) ; * num_pr = tree_to_uhwi ( TREE_VALUE ( num_pr_node ) ) ; return true ; } return false ; } </s>

Return true if TYPE is a built-in SVE type defined by the ABI or ACLE . If so , store the number of constituent SVE vectors in * NUM_ZR and the number of constituent SVE predicates in * NUM_PR .


<s> std :: pair < unsigned , const TargetRegisterClass * > MSP430TargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'r' : if ( VT == MVT :: i8 ) return std :: make_pair ( 0U , & MSP430 :: GR8RegClass ) ; return std :: make_pair ( 0U , & MSP430 :: GR16RegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>


<s> void updateDebugInfo ( MachineInstr * MI , const DILocation * Loc ) { DebugLoc DL ( Loc ) ; MI -> setDebugLoc ( DL ) ; } </s>

Called to update debug info associated with the instruction .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> static rtx riscv_pass_fpr_single ( enum machine_mode type_mode , unsigned regno , enum machine_mode value_mode ) { rtx x = gen_rtx_REG ( value_mode , regno ) ; if ( type_mode != value_mode ) { x = gen_rtx_EXPR_LIST ( VOIDmode , x , const0_rtx ) ; x = gen_rtx_PARALLEL ( type_mode , gen_rtvec ( 1 , x ) ) ; } return x ; } </s>

Return the representation of an argument passed or returned in an FPR when the value has mode VALUE_MODE and the type has TYPE_MODE . The two modes may be different for structures like : struct __attribute__ ( ( packed ) ) foo { float f ; } where the SFmode value `` f '' is passed in REGNO but the struct itself has mode BLKmode .


<s> bool MipsSETargetLowering :: isEligibleForTailCallOptimization ( const MipsCC & MipsCCInfo , unsigned NextStackOffset , const MipsFunctionInfo & FI ) const { if ( ! EnableMipsTailCalls ) return false ; if ( MipsCCInfo . hasByValArg ( ) || FI . hasByvalArg ( ) ) return false ; return NextStackOffset <= FI . getIncomingArgSize ( ) ; } </s>

Returns true if the call can be lowered as a tail call .


<s> static int riscv_register_move_cost ( enum machine_mode mode , reg_class_t from , reg_class_t to ) { return SECONDARY_MEMORY_NEEDED ( from , to , mode ) ? 8 : 2 ; } </s>


<s> const MCExpr * X86_64MachoTargetObjectFile :: getIndirectSymViaGOTPCRel ( const MCSymbol * Sym , const MCValue & MV , int64_t Offset , MachineModuleInfo * MMI , MCStreamer & Streamer ) const { unsigned FinalOff = Offset + MV . getConstant ( ) + 4 ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_GOTPCREL , getContext ( ) ) ; const MCExpr * Off = MCConstantExpr :: Create ( FinalOff , getContext ( ) ) ; return MCBinaryExpr :: CreateAdd ( Res , Off , getContext ( ) ) ; } </s>

Get the target specific PC relative GOT entry relocation .


"Searching for mode conversion candidates...\n"

"There are no candidates for optimization.\n"

"Chain #%d conversion is not profitable\n"

Main STV pass function . Find and convert scalar instructions into vector mode when profitable .


<s> int mips_class_max_nregs ( enum reg_class rclass , machine_mode mode ) { int size ; HARD_REG_SET left ; size = 0x8000 ; COPY_HARD_REG_SET ( left , reg_class_contents [ ( int ) rclass ] ) ; if ( hard_reg_set_intersect_p ( left , reg_class_contents [ ( int ) ST_REGS ] ) ) { if ( HARD_REGNO_MODE_OK ( ST_REG_FIRST , mode ) ) size = MIN ( size , 4 ) ; AND_COMPL_HARD_REG_SET ( left , reg_class_contents [ ( int ) ST_REGS ] ) ; } if ( hard_reg_set_intersect_p ( left , reg_class_contents [ ( int ) FP_REGS ] ) ) { if ( HARD_REGNO_MODE_OK ( FP_REG_FIRST , mode ) ) size = MIN ( size , UNITS_PER_FPREG ) ; AND_COMPL_HARD_REG_SET ( left , reg_class_contents [ ( int ) FP_REGS ] ) ; } if ( ! hard_reg_set_empty_p ( left ) ) size = MIN ( size , UNITS_PER_WORD ) ; return ( GET_MODE_SIZE ( mode ) + size - 1 ) / size ; } </s>

Implement CLASS_MAX_NREGS . Usually all registers are word-sized . The only supported exception is -mgp64 -msingle-float , which has 64-bit words but 32-bit float registers . A word-based calculation is correct even in that case , since -msingle-float disallows multi-FPR values . The FP status registers are an exception to this rule . They are always 4 bytes wide as they only hold condition code modes , and CCmode is always considered to be 4 bytes wide .


<s> static void s390_register_info_arg_gpr ( ) { int i ; int min_stdarg_gpr = INT_MAX , max_stdarg_gpr = - 1 ; int min_preserve_gpr = INT_MAX , max_preserve_gpr = - 1 ; int min_gpr , max_gpr ; if ( cfun -> stdarg && cfun -> va_list_gpr_size && crtl -> args . info . gprs < GP_ARG_NUM_REG ) { min_stdarg_gpr = crtl -> args . info . gprs ; max_stdarg_gpr = min_stdarg_gpr + cfun -> va_list_gpr_size - 1 ; if ( max_stdarg_gpr >= GP_ARG_NUM_REG ) max_stdarg_gpr = GP_ARG_NUM_REG - 1 ; min_stdarg_gpr += GPR2_REGNUM ; max_stdarg_gpr += GPR2_REGNUM ; } if ( s390_preserve_args_p && crtl -> args . info . gprs ) { min_preserve_gpr = GPR2_REGNUM ; max_preserve_gpr = MIN ( GPR6_REGNUM , GPR2_REGNUM + crtl -> args . info . gprs - 1 ) ; } min_gpr = MIN ( min_stdarg_gpr , min_preserve_gpr ) ; max_gpr = MAX ( max_stdarg_gpr , max_preserve_gpr ) ; if ( max_gpr == - 1 ) return ; if ( FP_REGNO_P ( cfun_gpr_save_slot ( GPR6_REGNUM ) ) && min_gpr <= GPR6_REGNUM && max_gpr >= GPR6_REGNUM ) { if ( cfun_frame_layout . first_restore_gpr == - 1 || cfun_frame_layout . first_restore_gpr > GPR6_REGNUM ) cfun_frame_layout . first_restore_gpr = GPR6_REGNUM ; if ( cfun_frame_layout . last_restore_gpr == - 1 || cfun_frame_layout . last_restore_gpr < GPR6_REGNUM ) cfun_frame_layout . last_restore_gpr = GPR6_REGNUM ; } if ( cfun_frame_layout . first_save_gpr == - 1 || cfun_frame_layout . first_save_gpr > min_gpr ) cfun_frame_layout . first_save_gpr = min_gpr ; if ( cfun_frame_layout . last_save_gpr == - 1 || cfun_frame_layout . last_save_gpr < max_gpr ) cfun_frame_layout . last_save_gpr = max_gpr ; for ( i = min_gpr ; i <= max_gpr ; i ++ ) cfun_gpr_save_slot ( i ) = SAVE_SLOT_STACK ; } </s>

Reserve the GPR save slots for GPRs which need to be saved due to stdarg or -mpreserve-args . This is a helper routine for s390_register_info .


<s> void PPCAIXAsmPrinter :: emitFunctionBodyEnd ( ) { if ( ! TM . getXCOFFTracebackTable ( ) ) return ; emitTracebackTable ( ) ; } </s>

Targets can override this to emit stuff after the last basic block in the function .


<s>
bool
AArch64PostLegalizerCombiner
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
MF
.
getProperties
(
)
.
hasProperty
(
MachineFunctionProperties
::
Property
::
FailedISel
)
)
return
false
;
assert
(
MF
.
getProperties
(
)
.
hasProperty
(
MachineFunctionProperties
::
Property
::
Legalized
)
&&
"Expected a legalized function?"
)
;
auto
*
TPC
=
&
getAnalysis
<
TargetPassConfig
>
(
)
;
const
Function
&
F
=
MF
.
getFunction
(
)
;
bool
EnableOpt
=
MF
.
getTarget
(
)
.
getOptLevel
(
)
!=
CodeGenOpt
::
&&
!
skipFunction
(
F
)
;
GISelKnownBits
*
KB
=
&
getAnalysis
<
GISelKnownBitsAnalysis
>
(
)
.
get
(
MF
)
;
MachineDominatorTree
*
MDT
=
IsOptNone
nullptr
:
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
AArch64PostLegalizerCombinerInfo
PCInfo
(
EnableOpt
,
F
.
hasOptSize
(
)
,
F
.
hasMinSize
(
)
,
KB
,
MDT
)
;
GISelCSEAnalysisWrapper
&
Wrapper
=
getAnalysis
<
GISelCSEAnalysisWrapperPass
>
(
)
.
getCSEWrapper
(
)
;
auto
*
CSEInfo
=
&
Wrapper
.
get
(
TPC
->
getCSEConfig
(
)
)
;
Combiner
C
(
PCInfo
,
TPC
)
;
return
C
.
combineMachineInstrs
(
MF
,
CSEInfo
)
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static void init_alignment_context ( struct alignment_context * ac , rtx mem ) { machine_mode mode = GET_MODE ( mem ) ; rtx byteoffset = NULL_RTX ; bool aligned = ( MEM_ALIGN ( mem ) >= GET_MODE_BITSIZE ( SImode ) ) ; if ( aligned ) ac -> memsi = adjust_address ( mem , SImode , 0 ) ; else { rtx addr , align ; addr = force_reg ( Pmode , XEXP ( mem , 0 ) ) ; align = expand_simple_binop ( Pmode , AND , addr , GEN_INT ( - GET_MODE_SIZE ( SImode ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ; ac -> memsi = gen_rtx_MEM ( SImode , align ) ; MEM_VOLATILE_P ( ac -> memsi ) = MEM_VOLATILE_P ( mem ) ; set_mem_alias_set ( ac -> memsi , ALIAS_SET_MEMORY_BARRIER ) ; set_mem_align ( ac -> memsi , GET_MODE_BITSIZE ( SImode ) ) ; byteoffset = expand_simple_binop ( Pmode , AND , addr , GEN_INT ( GET_MODE_SIZE ( SImode ) - 1 ) , NULL_RTX , 1 , OPTAB_DIRECT ) ; } if ( TARGET_BIG_ENDIAN ) { ac -> shift = GEN_INT ( GET_MODE_SIZE ( SImode ) - GET_MODE_SIZE ( mode ) ) ; if ( ! aligned ) ac -> shift = expand_simple_binop ( SImode , MINUS , ac -> shift , byteoffset , NULL_RTX , 1 , OPTAB_DIRECT ) ; } else { if ( aligned ) ac -> shift = NULL_RTX ; else ac -> shift = byteoffset ; } if ( ac -> shift != NULL_RTX ) { gcc_assert ( exact_log2 ( BITS_PER_UNIT ) >= 0 ) ; ac -> shift = expand_simple_binop ( SImode , ASHIFT , ac -> shift , GEN_INT ( exact_log2 ( BITS_PER_UNIT ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ; ac -> modemask = expand_simple_binop ( SImode , ASHIFT , GEN_INT ( GET_MODE_MASK ( mode ) ) , ac -> shift , NULL_RTX , 1 , OPTAB_DIRECT ) ; } else ac -> modemask = GEN_INT ( GET_MODE_MASK ( mode ) ) ; ac -> modemaski = expand_simple_unop ( SImode , NOT , ac -> modemask , NULL_RTX , 1 ) ; } </s>

Initialize structure AC for word access to HI and QI mode memory .


<s> static tree aarch64_embedded_comparison_type ( stmt_vec_info stmt_info ) { if ( auto * assign = dyn_cast < gassign * > ( stmt_info -> stmt ) ) if ( gimple_assign_rhs_code ( assign ) == COND_EXPR ) { tree cond = gimple_assign_rhs1 ( assign ) ; if ( COMPARISON_CLASS_P ( cond ) ) return TREE_TYPE ( TREE_OPERAND ( cond , 0 ) ) ; } return NULL_TREE ; } </s>

If STMT_INFO is a COND_EXPR that includes an embedded comparison , return the scalar type of the values being compared . Return null otherwise .


<s> StringRef getPassName ( ) const override { return EVEX2VEX_DESC ; } </s>

getPassName - Return a nice clean name for a pass .


<s> const RegisterBankInfo * AArch64Subtarget :: getRegBankInfo ( ) const { return RegBankInfo . get ( ) ; } </s>

If the information for the register banks is available , return it .


<s> static bool nios2_pragma_target_parse ( tree args , tree pop_target ) { tree cur_tree ; if ( ! args ) { cur_tree = ( ( pop_target ) ? pop_target : target_option_default_node ) ; cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( cur_tree ) ) ; } else { cur_tree = nios2_valid_target_attribute_tree ( args ) ; if ( ! cur_tree ) return false ; } target_option_current_node = cur_tree ; return true ; } </s>

Hook to validate the current # pragma GCC target and set the FPU custom code option state . If ARGS is NULL , then POP_TARGET is used to reset the options .


<s>
void
machopic_output_stub
(
FILE
*
file
,
const
char
*
symb
,
const
char
*
stub
)
{
unsigned
int
length
;
char
*
symbol_name
,
*
lazy_ptr_name
;
char
*
local_label_0
;
static
int
label
=
0
;
symb
=
(
*
targetm
.
strip_name_encoding
)
(
symb
)
;
length
=
strlen
(
symb
)
;
symbol_name
=
XALLOCAVEC
(
char
,
length
+
32
)
;
GEN_SYMBOL_NAME_FOR_SYMBOL
(
symbol_name
,
symb
,
length
)
;
lazy_ptr_name
=
XALLOCAVEC
(
char
,
length
+
32
)
;
GEN_LAZY_PTR_NAME_FOR_SYMBOL
(
lazy_ptr_name
,
symb
,
length
)
;
if
(
flag_pic
==
2
)
switch_to_section
(
darwin_sections
[
machopic_picsymbol_stub1_section
]
)
;
else
switch_to_section
(
darwin_sections
[
machopic_symbol_stub1_section
]
)
;
if
(
flag_pic
==
2
)
{
fprintf
(
file
,
"\t.align 5\n"
)
;
fprintf
(
file
,
"%s:\n"
,
stub
)
;
fprintf
(
file
,
"\t.indirect_symbol %s\n"
,
symbol_name
)
;
label
++
;
local_label_0
=
XALLOCAVEC
(
char
,
sizeof
(
"\"L00000000000$spb\""
)
)
;
sprintf
(
local_label_0
,
"\"L%011d$spb\""
,
label
)
;
fprintf
(
file
,
"\tmflr r0\n"
)
;
if
(
TARGET_LINK_STACK
)
{
char
name
[
32
]
;
get_ppc476_thunk_name
(
name
)
;
fprintf
(
file
,
"\tbl %s\n"
,
name
)
;
fprintf
(
file
,
"%s:\n\tmflr r11\n"
,
local_label_0
)
;
}
else
{
fprintf
(
file
,
"\tbcl 20,31,%s\n"
,
local_label_0
)
;
fprintf
(
file
,
"%s:\n\tmflr r11\n"
,
local_label_0
)
;
}
fprintf
(
file
,
"\taddis r11,r11,ha16(%s-%s)\n"
,
lazy_ptr_name
,
local_label_0
)
;
fprintf
(
file
,
"\tmtlr r0\n"
)
;
fprintf
(
file
,
"\t%s r12,lo16(%s-%s)(r11)\n"
,
(
TARGET_64BIT
"ldu"
:
"lwzu"
)
,
lazy_ptr_name
,
local_label_0
)
;
fprintf
(
file
,
"\tmtctr r12\n"
)
;
fprintf
(
file
,
"\tbctr\n"
)
;
}
else
{
fprintf
(
file
,
"\t.align 4\n"
)
;
fprintf
(
file
,
"%s:\n"
,
stub
)
;
fprintf
(
file
,
"\t.indirect_symbol %s\n"
,
symbol_name
)
;
fprintf
(
file
,
"\tlis r11,ha16(%s)\n"
,
lazy_ptr_name
)
;
fprintf
(
file
,
"\t%s r12,lo16(%s)(r11)\n"
,
(
TARGET_64BIT
"ldu"
:
"lwzu"
)
,
lazy_ptr_name
)
;
fprintf
(
file
,
"\tmtctr r12\n"
)
;
fprintf
(
file
,
"\tbctr\n"
)
;
}
switch_to_section
(
darwin_sections
[
machopic_lazy_symbol_ptr_section
]
)
;
fprintf
(
file
,
"%s:\n"
,
lazy_ptr_name
)
;
fprintf
(
file
,
"\t.indirect_symbol %s\n"
,
symbol_name
)
;
fprintf
(
file
,
"%sdyld_stub_binding_helper\n"
,
(
TARGET_64BIT
DOUBLE_INT_ASM_OP
:
"\t.long\t"
)
)
;
}
</s>

Generate external symbol indirection stubs ( PIC and non-PIC ) .


<s> static inline int extract_17 ( unsigned word ) { return sign_extend ( GET_FIELD ( word , 19 , 28 ) | GET_FIELD ( word , 29 , 29 ) << 10 | GET_FIELD ( word , 11 , 15 ) << 11 | ( word & 0x1 ) << 16 , 17 ) ; } </s>

Extract a 17-bit signed constant from branch instructions .


<s> unsigned mmix_local_alignment ( tree type ATTRIBUTE_UNUSED , unsigned basic_align ) { if ( basic_align < 32 ) return 32 ; return basic_align ; } </s>


<s> bool mep_can_eliminate ( const int from , const int to ) { return ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true ) ; } </s>

Worker function for TARGET_CAN_ELIMINATE .


<s> const unsigned * PIC16RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const unsigned CalleeSavedRegs [ ] = { 0 } ; return CalleeSavedRegs ; } </s>


<s> bool fr30_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { return ( to == FRAME_POINTER_REGNUM || ! frame_pointer_needed ) ; } </s>


<s> void PPCRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( PerformTailCallOpt && I -> getOpcode ( ) == PPC :: ADJCALLSTACKUP ) { if ( int CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { bool is64Bit = Subtarget . isPPC64 ( ) ; CalleeAmt *= - 1 ; unsigned StackReg = is64Bit ? PPC :: X1 : PPC :: R1 ; unsigned TmpReg = is64Bit ? PPC :: X0 : PPC :: R0 ; unsigned ADDIInstr = is64Bit ? PPC :: ADDI8 : PPC :: ADDI ; unsigned ADDInstr = is64Bit ? PPC :: ADD8 : PPC :: ADD4 ; unsigned LISInstr = is64Bit ? PPC :: LIS8 : PPC :: LIS ; unsigned ORIInstr = is64Bit ? PPC :: ORI8 : PPC :: ORI ; MachineInstr * MI = I ; DebugLoc dl = MI -> getDebugLoc ( ) ; if ( isInt16 ( CalleeAmt ) ) { BuildMI ( MBB , I , dl , TII . get ( ADDIInstr ) , StackReg ) . addReg ( StackReg ) . addImm ( CalleeAmt ) ; } else { MachineBasicBlock :: iterator MBBI = I ; BuildMI ( MBB , MBBI , dl , TII . get ( LISInstr ) , TmpReg ) . addImm ( CalleeAmt >> 16 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ORIInstr ) , TmpReg ) . addReg ( TmpReg , RegState :: Kill ) . addImm ( CalleeAmt & 0xFFFF ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ADDInstr ) ) . addReg ( StackReg ) . addReg ( StackReg ) . addReg ( TmpReg ) ; } } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> void TOYPassConfig :: addPreEmitPass ( ) { return ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


"passing %qT to argument %d of %qE, which expects"

Require argument ARGNO to be a 32-bit or 64-bit scalar integer type . Return the associated type suffix on success , otherwise report an error and return NUM_TYPE_SUFFIXES .


<s> MCSymbol * WebAssemblyMCInstLower :: GetExternalSymbolSymbol ( const MachineOperand & MO ) const { const char * Name = MO . getSymbolName ( ) ; auto * WasmSym = cast < MCSymbolWasm > ( Printer . GetExternalSymbolSymbol ( Name ) ) ; const WebAssemblySubtarget & Subtarget = Printer . getSubtarget ( ) ; if ( strcmp ( Name , "__stack_pointer" ) == 0 || strcmp ( Name , "__tls_base" ) == 0 || strcmp ( Name , "__memory_base" ) == 0 || strcmp ( Name , "__table_base" ) == 0 || strcmp ( Name , "__tls_size" ) == 0 ) { bool Mutable = strcmp ( Name , "__stack_pointer" ) == 0 || strcmp ( Name , "__tls_base" ) == 0 ; WasmSym -> setType ( wasm :: WASM_SYMBOL_TYPE_GLOBAL ) ; WasmSym -> setGlobalType ( wasm :: WasmGlobalType { uint8_t ( Subtarget . hasAddr64 ( ) ? wasm :: WASM_TYPE_I64 : wasm :: WASM_TYPE_I32 ) , Mutable } ) ; return WasmSym ; } SmallVector < wasm :: ValType , 4 > Returns ; SmallVector < wasm :: ValType , 4 > Params ; if ( strcmp ( Name , "__cpp_exception" ) == 0 ) { WasmSym -> setType ( wasm :: WASM_SYMBOL_TYPE_EVENT ) ; WasmSym -> setEventType ( { wasm :: WASM_EVENT_ATTRIBUTE_EXCEPTION , 0 } ) ; WasmSym -> setWeak ( true ) ; WasmSym -> setExternal ( true ) ; Params . push_back ( Subtarget . hasAddr64 ( ) ? wasm :: ValType :: I64 : wasm :: ValType :: I32 ) ; } else { WasmSym -> setType ( wasm :: WASM_SYMBOL_TYPE_FUNCTION ) ; getLibcallSignature ( Subtarget , Name , Returns , Params ) ; } auto Signature = make_unique < wasm :: WasmSignature > ( std :: move ( Returns ) , std :: move ( Params ) ) ; WasmSym -> setSignature ( Signature . get ( ) ) ; Printer . addSignature ( std :: move ( Signature ) ) ; return WasmSym ; } </s>

Return the MCSymbol for the specified ExternalSymbol .


<s> bool emitSymbolAttribute ( MCSymbol * Symbol , MCSymbolAttr Attribute ) override { bool Val = MCELFStreamer :: emitSymbolAttribute ( Symbol , Attribute ) ; if ( ! IsThumb ) return Val ; unsigned Type = cast < MCSymbolELF > ( Symbol ) -> getType ( ) ; if ( ( Type == ELF :: STT_FUNC || Type == ELF :: STT_GNU_IFUNC ) && Symbol -> isDefined ( ) ) getAssembler ( ) . setIsThumbFunc ( Symbol ) ; return Val ; } </s>


<s> unsigned ARMBaseInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { const MachineBasicBlock & MBB = * MI . getParent ( ) ; const MachineFunction * MF = MBB . getParent ( ) ; const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ; const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( MCID . getSize ( ) ) return MCID . getSize ( ) ; switch ( MI . getOpcode ( ) ) { default : return 0 ; case TargetOpcode :: BUNDLE : return getInstBundleLength ( MI ) ; case ARM :: MOVi16_ga_pcrel : case ARM :: MOVTi16_ga_pcrel : case ARM :: t2MOVi16_ga_pcrel : case ARM :: t2MOVTi16_ga_pcrel : return 4 ; case ARM :: MOVi32imm : case ARM :: t2MOVi32imm : return 8 ; case ARM :: CONSTPOOL_ENTRY : case ARM :: JUMPTABLE_INSTS : case ARM :: JUMPTABLE_ADDRS : case ARM :: JUMPTABLE_TBB : case ARM :: JUMPTABLE_TBH : return MI . getOperand ( 2 ) . getImm ( ) ; case ARM :: Int_eh_sjlj_longjmp : return 16 ; case ARM :: tInt_eh_sjlj_longjmp : return 10 ; case ARM :: tInt_WIN_eh_sjlj_longjmp : return 12 ; case ARM :: Int_eh_sjlj_setjmp : case ARM :: Int_eh_sjlj_setjmp_nofp : return 20 ; case ARM :: tInt_eh_sjlj_setjmp : case ARM :: t2Int_eh_sjlj_setjmp : case ARM :: t2Int_eh_sjlj_setjmp_nofp : return 12 ; case ARM :: SPACE : return MI . getOperand ( 1 ) . getImm ( ) ; case ARM :: INLINEASM : case ARM :: INLINEASM_BR : { unsigned Size = getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * MAI ) ; if ( ! MF -> getInfo < ARMFunctionInfo > ( ) -> isThumbFunction ( ) ) Size = alignTo ( Size , 4 ) ; return Size ; } } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> bool JVMFrameLowering :: hasFP ( const MachineFunction & MF ) const { return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> std :: pair < unsigned , const TargetRegisterClass * > SITargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( ! isTypeLegal ( VT ) ) return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 's' : case 'r' : switch ( VT . getSizeInBits ( ) ) { default : return std :: make_pair ( 0U , nullptr ) ; case 32 : case 16 : return std :: make_pair ( 0U , & AMDGPU :: SReg_32_XM0RegClass ) ; case 64 : return std :: make_pair ( 0U , & AMDGPU :: SGPR_64RegClass ) ; case 128 : return std :: make_pair ( 0U , & AMDGPU :: SReg_128RegClass ) ; case 256 : return std :: make_pair ( 0U , & AMDGPU :: SReg_256RegClass ) ; case 512 : return std :: make_pair ( 0U , & AMDGPU :: SReg_512RegClass ) ; } case 'v' : switch ( VT . getSizeInBits ( ) ) { default : return std :: make_pair ( 0U , nullptr ) ; case 32 : case 16 : return std :: make_pair ( 0U , & AMDGPU :: VGPR_32RegClass ) ; case 64 : return std :: make_pair ( 0U , & AMDGPU :: VReg_64RegClass ) ; case 96 : return std :: make_pair ( 0U , & AMDGPU :: VReg_96RegClass ) ; case 128 : return std :: make_pair ( 0U , & AMDGPU :: VReg_128RegClass ) ; case 256 : return std :: make_pair ( 0U , & AMDGPU :: VReg_256RegClass ) ; case 512 : return std :: make_pair ( 0U , & AMDGPU :: VReg_512RegClass ) ; } } } if ( Constraint . size ( ) > 1 ) { const TargetRegisterClass * RC = nullptr ; if ( Constraint [ 1 ] == 'v' ) { RC = & AMDGPU :: VGPR_32RegClass ; } else if ( Constraint [ 1 ] == 's' ) { RC = & AMDGPU :: SGPR_32RegClass ; } if ( RC ) { uint32_t Idx ; bool Failed = Constraint . substr ( 2 ) . getAsInteger ( 10 , Idx ) ; if ( ! Failed && Idx < RC -> getNumRegs ( ) ) return std :: make_pair ( RC -> getRegister ( Idx ) , RC ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


getTargetNodeName - This method returns the name of a target specific


<s> bool PPCPassConfig :: addILPOpts ( ) { addPass ( & EarlyIfConverterID ) ; return true ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .


<s>
unsigned
SNESTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
SelectionDAG
&
DAG
)
const
{
unsigned
Reg
;
if
(
VT
==
MVT
::
i8
)
{
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"X"
,
SNES
::
X
)
.
Case
(
"Y"
,
SNES
::
Y
)
.
Case
(
"A"
,
SNES
::
A
)
.
Default
(
0
)
;
}
else
{
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"X"
,
SNES
::
X
)
.
Case
(
"Y"
,
SNES
::
Y
)
.
Case
(
"A"
,
SNES
::
A
)
.
Default
(
0
)
;
}
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .

SNES
SNES
MVT::i8
"X"
SNES::X
"Y"
SNES::Y
"A"
SNES::A
0
"X"
SNES::X
"Y"
SNES::Y
"A"
SNES::A
0
"Invalid register name global variable"


<s> const MCSection * SystemZMCAsmInfo :: getNonexecutableStackSection ( MCContext & Ctx ) const { return Ctx . getELFSection ( ".note.GNU-stack" , ELF :: SHT_PROGBITS , 0 , SectionKind :: getMetadata ( ) ) ; } </s>

Targets can implement this method to specify a section to switch to if the translation unit does n't have any trampolines that require an executable stack .


"JIT relocation model must be set to static or default!"

runOnMachineFunction - Emit the function body .


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( Count % 4 != 0 ) return false ; uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> Write32 ( 0x01000000 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> SDValue OpenRISCTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_OpenRISC ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> SDNode * TeeRISCDAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = TM . getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI -> getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> const std :: string & ARMToARMStub :: name ( ) const { return m_Name ; } </s>

Gets the name of the pass we are mixed into .


<s> static tree aarch64_get_attributes ( unsigned int f , machine_mode mode ) { tree attrs = NULL_TREE ; if ( ! aarch64_modifies_global_state_p ( f , mode ) ) { if ( aarch64_reads_global_state_p ( f , mode ) ) attrs = aarch64_add_attribute ( "pure" , attrs ) ; else attrs = aarch64_add_attribute ( "const" , attrs ) ; } if ( ! flag_non_call_exceptions || ! aarch64_could_trap_p ( f , mode ) ) attrs = aarch64_add_attribute ( "nothrow" , attrs ) ; return aarch64_add_attribute ( "leaf" , attrs ) ; } </s>

Return the appropriate function attributes .


<s>
StringRef
getPassName
(
)
const
override
{
return
"AArch64 Promote Constant"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void thumb1_gen_const_int_rtl ( rtx dst , HOST_WIDE_INT op1 ) { thumb1_const_rtl t ( dst ) ; thumb1_gen_const_int_1 ( t , op1 ) ; } </s>

Proxies for thumb1.md , since the thumb1_const_print and thumb1_const_rtl classes are not exported .


<s> int X86TTIImpl :: getIntrinsicInstrCost ( Intrinsic :: ID IID , Type * RetTy , ArrayRef < Type * > Tys , FastMathFlags FMF ) { static const CostTblEntry XOPCostTbl [ ] = { { ISD :: BITREVERSE , MVT :: v4i64 , 4 } , { ISD :: BITREVERSE , MVT :: v8i32 , 4 } , { ISD :: BITREVERSE , MVT :: v16i16 , 4 } , { ISD :: BITREVERSE , MVT :: v32i8 , 4 } , { ISD :: BITREVERSE , MVT :: v2i64 , 1 } , { ISD :: BITREVERSE , MVT :: v4i32 , 1 } , { ISD :: BITREVERSE , MVT :: v8i16 , 1 } , { ISD :: BITREVERSE , MVT :: v16i8 , 1 } , { ISD :: BITREVERSE , MVT :: i64 , 3 } , { ISD :: BITREVERSE , MVT :: i32 , 3 } , { ISD :: BITREVERSE , MVT :: i16 , 3 } , { ISD :: BITREVERSE , MVT :: i8 , 3 } } ; unsigned ISD = ISD :: DELETED_NODE ; switch ( IID ) { default : break ; case Intrinsic :: bitreverse : ISD = ISD :: BITREVERSE ; break ; } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; MVT MTy = LT . second ; if ( ST -> hasXOP ( ) ) if ( const auto * Entry = CostTableLookup ( XOPCostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ; return BaseT :: getIntrinsicInstrCost ( IID , RetTy , Tys , FMF ) ; } </s>


<s> unsigned NVPTXTTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo ) { std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Ty ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: ADD : case ISD :: MUL : case ISD :: XOR : case ISD :: OR : case ISD :: AND : if ( LT . second . SimpleTy == MVT :: i64 ) return 2 * LT . first ; return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .

NVPTX NVPTX ISD::ADD ISD::MUL ISD::XOR ISD::OR ISD::AND MVT::i64 2


<s> AVRTargetLowering :: ConstraintType AVRTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'a' : case 'b' : case 'd' : case 'l' : case 'e' : case 'q' : case 'r' : case 'w' : return C_RegisterClass ; case 't' : case 'x' : case 'X' : case 'y' : case 'Y' : case 'z' : case 'Z' : return C_Register ; case 'Q' : return C_Memory ; case 'G' : case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'O' : case 'P' : case 'R' : return C_Other ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> void Nios2PassConfig :: addCodeGenPrepare ( ) { TargetPassConfig :: addCodeGenPrepare ( ) ; } </s>

Add pass to prepare the LLVM IR for code generation .


<s> Value * X86TargetLowering :: getSafeStackPointerLocation ( IRBuilder < > & IRB ) const { if ( Subtarget . getTargetTriple ( ) . isOSContiki ( ) ) return getDefaultSafeStackPointerLocation ( IRB , false ) ; if ( ! Subtarget . isTargetAndroid ( ) ) return TargetLowering :: getSafeStackPointerLocation ( IRB ) ; unsigned AddressSpace , Offset ; Offset = ( Subtarget . is64Bit ( ) ) ? 0x48 : 0x24 ; AddressSpace = getAddressSpace ( ) ; return ConstantExpr :: getIntToPtr ( ConstantInt :: get ( Type :: getInt32Ty ( IRB . getContext ( ) ) , Offset ) , Type :: getInt8PtrTy ( IRB . getContext ( ) ) -> getPointerTo ( AddressSpace ) ) ; } </s>

Return true if the target stores SafeStack pointer at a fixed offset in some non-standard address space , and populates the address space and offset as appropriate .


"***** Machine Function before Domain Reassignment *****\n"

"***** Machine Function after Domain Reassignment *****\n"


<s>
bool
AMDGPUAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
switch
(
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MatchingInlineAsm
)
)
{
default
:
break
;
case
Match_Success
:
Inst
.
setLoc
(
IDLoc
)
;
Out
.
EmitInstruction
(
Inst
,
STI
)
;
return
false
;
case
Match_MissingFeature
:
return
Error
(
IDLoc
,
"missing feature"
)
;
case
Match_MnemonicFail
:
return
Error
(
IDLoc
,
"unrecognized instruction mnemonic"
)
;
case
Match_InvalidOperand
:
{
SMLoc
ErrorLoc
=
IDLoc
;
if
(
ErrorInfo
!=
~
0ULL
)
{
if
(
ErrorInfo
>=
Operands
.
size
(
)
)
{
return
Error
(
IDLoc
,
"too few operands for instruction"
)
;
}
ErrorLoc
=
(
(
AMDGPUOperand
&
)
*
Operands
[
ErrorInfo
]
)
.
getStartLoc
(
)
;
if
(
ErrorLoc
==
SMLoc
(
)
)
ErrorLoc
=
IDLoc
;
}
return
Error
(
ErrorLoc
,
"invalid operand for instruction"
)
;
}
}
llvm_unreachable
(
"Implement any new match types added!"
)
;
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .

R600
"missing feature"
"unrecognized instruction mnemonic"
0ULL
"too few operands for instruction"
"invalid operand for instruction"
"Implement any new match types added!"


<s> static void expand_block_move_2 ( rtx dst , rtx dst_reg , rtx src , rtx src_reg , rtx bytes_rtx ) { unsigned HOST_WIDE_INT bytes = UINTVAL ( bytes_rtx ) ; unsigned int rem = bytes % 2 ; emit_library_call ( wrd_memcpy_libfunc , LCT_NORMAL , VOIDmode , dst_reg , Pmode , src_reg , Pmode , convert_to_mode ( TYPE_MODE ( sizetype ) , GEN_INT ( bytes >> 1 ) , TYPE_UNSIGNED ( sizetype ) ) , TYPE_MODE ( sizetype ) ) ; if ( rem == 0 ) return ; dst = replace_equiv_address_nv ( dst , dst_reg ) ; src = replace_equiv_address_nv ( src , src_reg ) ; bytes -= rem ; emit_move_insn ( adjust_address_nv ( dst , QImode , bytes ) , adjust_address_nv ( src , QImode , bytes ) ) ; } </s>

Generate a call to a library function to move BYTES_RTX bytes from SRC with address SRC_REG to DST with address DST_REG in 2-bytes chunks .


"LowerFormalArguments Unhandled argument type: "

"LowerFormalArguments unhandled argument type: "

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> enum machine_mode s390_tm_ccmode ( rtx op1 , rtx op2 , bool mixed ) { int bit0 , bit1 ; if ( GET_CODE ( op1 ) != CONST_INT || GET_CODE ( op2 ) != CONST_INT ) return VOIDmode ; if ( INTVAL ( op2 ) == 0 ) return CCTmode ; if ( INTVAL ( op2 ) == INTVAL ( op1 ) ) return CCT3mode ; if ( mixed ) { bit1 = exact_log2 ( INTVAL ( op2 ) ) ; bit0 = exact_log2 ( INTVAL ( op1 ) ^ INTVAL ( op2 ) ) ; if ( bit0 != - 1 && bit1 != - 1 ) return bit0 > bit1 ? CCT1mode : CCT2mode ; } return VOIDmode ; } </s>

If a test-under-mask instruction can be used to implement ( compare ( and ... OP1 ) OP2 ) , return the CC mode required to do that . Otherwise , return VOIDmode . MIXED is true if the instruction can distinguish between CC1 and CC2 for mixed selected bits ( TMxx ) , it is false if the instruction can not ( TM ) .


<s> bool X86WinAllocaExpander :: runOnMachineFunction ( MachineFunction & MF ) { if ( ! MF . getInfo < X86MachineFunctionInfo > ( ) -> hasWinAlloca ( ) ) return false ; MRI = & MF . getRegInfo ( ) ; STI = & MF . getSubtarget < X86Subtarget > ( ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; StackPtr = TRI -> getStackRegister ( ) ; SlotSize = TRI -> getSlotSize ( ) ; StackProbeSize = 4096 ; if ( MF . getFunction ( ) . hasFnAttribute ( "stack-probe-size" ) ) { MF . getFunction ( ) . getFnAttribute ( "stack-probe-size" ) . getValueAsString ( ) . getAsInteger ( 0 , StackProbeSize ) ; } LoweringMap Lowerings ; computeLowerings ( MF , Lowerings ) ; for ( auto & P : Lowerings ) lower ( P . first , P . second ) ; return true ; } </s>


Choose the order in which to allocate hard registers for pseudo-registers local to a basic block . Store the desired register order in the array ` reg_alloc_order ' . Element 0 should be the register to allocate first ; element 1 , the next register ; and so on .


<s> SparcTargetLowering :: ConstraintType SparcTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'r' : return C_RegisterClass ; case 'I' : return C_Other ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>


<s> bool SITargetLowering :: isEligibleForTailCallOptimization ( SDValue Callee , CallingConv :: ID CalleeCC , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SmallVectorImpl < ISD :: InputArg > & Ins , SelectionDAG & DAG ) const { if ( ! mayTailCallThisCC ( CalleeCC ) ) return false ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function * CallerF = MF . getFunction ( ) ; CallingConv :: ID CallerCC = CallerF -> getCallingConv ( ) ; const SIRegisterInfo * TRI = getSubtarget ( ) -> getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( ! CallerPreserved ) return false ; bool CCMatch = CallerCC == CalleeCC ; if ( DAG . getTarget ( ) . Options . GuaranteedTailCallOpt ) { if ( canGuaranteeTCO ( CalleeCC ) && CCMatch ) return true ; return false ; } if ( IsVarArg ) return false ; for ( const Argument & Arg : CallerF -> args ( ) ) { if ( Arg . hasByValAttr ( ) ) return false ; } LLVMContext & Ctx = * DAG . getContext ( ) ; if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , Ctx , Ins , CCAssignFnForCall ( CalleeCC , IsVarArg ) , CCAssignFnForCall ( CallerCC , IsVarArg ) ) ) return false ; if ( ! CCMatch ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } if ( Outs . empty ( ) ) return true ; SmallVector < CCValAssign , 16 > ArgLocs ; CCState CCInfo ( CalleeCC , IsVarArg , MF , ArgLocs , Ctx ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , IsVarArg ) ) ; const SIMachineFunctionInfo * FuncInfo = MF . getInfo < SIMachineFunctionInfo > ( ) ; if ( CCInfo . getNextStackOffset ( ) > FuncInfo -> getBytesInStackArgArea ( ) ) return false ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; return parametersInCSRMatch ( MRI , CallerPreserved , ArgLocs , OutVals ) ; } </s>

Returns true if the call can be lowered as a tail call .

AMDGPU SI ISD::OutputArg ISD::InputArg SI 16 SI SI


<s> bool aarch64_pad_reg_upward ( machine_mode mode , const_tree type , bool first ATTRIBUTE_UNUSED ) { if ( BYTES_BIG_ENDIAN && aarch64_composite_type_p ( type , mode ) ) { HOST_WIDE_INT size ; if ( type ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) . to_constant ( ) ; if ( size < 2 * UNITS_PER_WORD ) { pure_scalable_type_info pst_info ; if ( pst_info . analyze_registers ( type ) ) return false ; return true ; } } return ! BYTES_BIG_ENDIAN ; } </s>

Similarly , for use by BLOCK_REG_PADDING ( MODE , TYPE , FIRST ) . It specifies padding for the last ( may also be the only ) element of a block move between registers and memory . If assuming the block is in the memory , padding upward means that the last element is padded after its highest significant byte , while in downward padding , the last element is padded at the its least significant byte side . Small aggregates and small complex types are always padded upwards . We do n't need to worry about homogeneous floating-point or short-vector aggregates ; their move is not affected by the padding direction determined here . Regardless of endianness , each element of such an aggregate is put in the least significant bits of a fp/simd register . Return ! BYTES_BIG_ENDIAN if the least significant byte of the register has useful data , and return the opposite if the most significant byte does .


<s>
bool
R600VectorRegMerger
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
TII
=
static_cast
<
const
R600InstrInfo
*
>
(
Fn
.
getTarget
(
)
.
getInstrInfo
(
)
)
;
MRI
=
&
(
Fn
.
getRegInfo
(
)
)
;
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
MachineBasicBlock
*
MB
=
MBB
;
PreviousRegSeq
.
clear
(
)
;
PreviousRegSeqByReg
.
clear
(
)
;
PreviousRegSeqByUndefCount
.
clear
(
)
;
for
(
MachineBasicBlock
::
iterator
MII
=
MB
->
begin
(
)
,
MIIE
=
MB
->
end
(
)
;
MII
!=
MIIE
;
++
MII
)
{
MachineInstr
*
MI
=
MII
;
if
(
MI
->
getOpcode
(
)
!=
AMDGPU
::
REG_SEQUENCE
)
{
if
(
TII
->
get
(
MI
->
getOpcode
(
)
)
.
TSFlags
&
R600_InstFlag
::
TEX_INST
)
{
unsigned
Reg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
for
(
MachineRegisterInfo
::
def_instr_iterator
It
=
MRI
->
def_instr_begin
(
Reg
)
,
E
=
MRI
->
def_instr_end
(
)
;
It
!=
E
;
++
It
)
{
RemoveMI
(
&
(
*
It
)
)
;
}
}
continue
;
}
RegSeqInfo
RSI
(
*
MRI
,
MI
)
;
unsigned
Reg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
if
(
!
areAllUsesSwizzeable
(
Reg
)
)
continue
;
DEBUG
(
dbgs
(
)
<<
"Trying to optimize "
;
MI
->
dump
(
)
;
)
;
RegSeqInfo
CandidateRSI
;
std
::
vector
<
std
::
pair
<
unsigned
,
unsigned
>
>
RemapChan
;
DEBUG
(
dbgs
(
)
<<
"Using common slots...\n"
;
)
;
if
(
tryMergeUsingCommonSlot
(
RSI
,
CandidateRSI
,
RemapChan
)
)
{
RemoveMI
(
CandidateRSI
.
Instr
)
;
MII
=
RebuildVector
(
&
RSI
,
&
CandidateRSI
,
RemapChan
)
;
trackRSI
(
RSI
)
;
continue
;
}
DEBUG
(
dbgs
(
)
<<
"Using free slots...\n"
;
)
;
RemapChan
.
clear
(
)
;
if
(
tryMergeUsingFreeSlot
(
RSI
,
CandidateRSI
,
RemapChan
)
)
{
RemoveMI
(
CandidateRSI
.
Instr
)
;
MII
=
RebuildVector
(
&
RSI
,
&
CandidateRSI
,
RemapChan
)
;
trackRSI
(
RSI
)
;
continue
;
}
trackRSI
(
RSI
)
;
}
}
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .

R600
R600_InstFlag::TEX_INST
1
SI
0
"Trying to optimize "
SI
"Using common slots...\n"
SI
SI
SI
SI
SI
SI
SI
"Using free slots...\n"
SI
SI
SI
SI
SI
SI
SI
SI
SI


"MOSInstrInfo::findCommutedOpIndices() can't handle bundles"

"Unexpected opcode; don't know how to commute."

Returns true iff the routine could find two commutable operands in the given machine instruction .


<s> Function * ARMTargetLowering :: getSSPStackGuardCheck ( const Module & M ) const { if ( Subtarget -> getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) ) return M . getFunction ( "__security_check_cookie" ) ; return TargetLowering :: getSSPStackGuardCheck ( M ) ; } </s>

If the target has a standard stack protection check function that performs validation and error handling , returns the function .


<s> void SHUXIInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> int ia32_multipass_dfa_lookahead ( void ) { if ( reload_completed ) return ix86_issue_rate ( ) ; return 0 ; } </s>

How many alternative schedules to try . This should be as wide as the scheduling freedom in the DFA , but no wider . Making this value too large results extra work for the scheduler .


<s> bool runOnFunction ( Function & F ) override { TargetMachine * TM = & getAnalysis < TargetPassConfig > ( ) . getTM < TargetMachine > ( ) ; X86LowerAMXType LAT ( F , TM ) ; bool C = LAT . visit ( ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: None ) { if ( ! F . hasFnAttribute ( Attribute :: OptimizeNone ) ) { X86VolatileTileData VTD ( F ) ; C = VTD . volatileTileData ( ) || C ; } } return C ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool isCheapToSpeculateCtlz ( ) const override { return true ; } </s>

Return true if it is cheap to speculate a call to intrinsic ctlz .


<s> void HexagonPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) { addPass ( createConstantPropagationPass ( ) ) ; addPass ( createDeadCodeEliminationPass ( ) ) ; } addPass ( createAtomicExpandPass ( ) ) ; if ( ! NoOpt ) { if ( EnableLoopPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableCommGEP ) addPass ( createHexagonCommonGEP ( ) ) ; if ( EnableGenExtract ) addPass ( createHexagonGenExtract ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static inline tree def_builtin ( HOST_WIDE_INT mask , const char * name , enum ix86_builtin_func_type tcode , enum ix86_builtins code ) { tree decl = NULL_TREE ; if ( ! ( mask & OPTION_MASK_ISA_64BIT ) || TARGET_64BIT ) { ix86_builtins_isa [ ( int ) code ] . isa = mask ; if ( mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512VL ) mask &= ~ OPTION_MASK_ISA_AVX512VL ; mask &= ~ OPTION_MASK_ISA_64BIT ; if ( mask == 0 || ( mask & ix86_isa_flags ) != 0 || ( lang_hooks . builtin_function == lang_hooks . builtin_function_ext_scope ) ) { tree type = ix86_get_builtin_func_type ( tcode ) ; decl = add_builtin_function ( name , type , code , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ ( int ) code ] = decl ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = false ; } else { deferred_isa_values |= mask ; ix86_builtins [ ( int ) code ] = NULL_TREE ; ix86_builtins_isa [ ( int ) code ] . tcode = tcode ; ix86_builtins_isa [ ( int ) code ] . name = name ; ix86_builtins_isa [ ( int ) code ] . leaf_p = false ; ix86_builtins_isa [ ( int ) code ] . nothrow_p = false ; ix86_builtins_isa [ ( int ) code ] . const_p = false ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = true ; } } return decl ; } </s>

Add a SPARC builtin function with NAME , ICODE , CODE and TYPE . Return the function decl or NULL_TREE if the builtin was not added .


<s>
bool
RISCVInstrInfo
::
isBranchOffsetInRange
(
unsigned
BranchOp
,
int64_t
BrOffset
)
const
{
unsigned
XLen
=
STI
.
getXLen
(
)
;
switch
(
BranchOp
)
{
default
:
llvm_unreachable
(
"Unexpected opcode!"
)
;
case
RISCV
::
BEQ
:
case
RISCV
::
BNE
:
case
RISCV
::
BLT
:
case
RISCV
::
BGE
:
case
RISCV
::
BLTU
:
case
RISCV
::
BGEU
:
return
isIntN
(
13
,
BrOffset
)
;
case
RISCV
::
JAL
:
case
RISCV
::
PseudoBR
:
return
isIntN
(
21
,
BrOffset
)
;
case
RISCV
::
PseudoJump
:
return
isIntN
(
32
,
SignExtend64
(
BrOffset
+
0x800
,
XLen
)
)
;
}
}
</s>

Determine if the branch target is in range .

RISCV
RISCV
"Unexpected opcode!"
RISCV::BEQ
RISCV::BNE
RISCV::BLT
RISCV::BGE
RISCV::BLTU
RISCV::BGEU
13
RISCV::JAL
RISCV::PseudoBR
21
RISCV::PseudoJump
32
0x800


<s> SDValue BPFSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; if ( ! ConstantSize ) return SDValue ( ) ; unsigned CopyLen = ConstantSize -> getZExtValue ( ) ; unsigned StoresNumEstimate = alignTo ( CopyLen , Align ) >> Log2_32 ( Align ) ; if ( StoresNumEstimate > getCommonMaxStoresPerMemFunc ( ) ) return SDValue ( ) ; SDVTList VTs = DAG . getVTList ( MVT :: Other , MVT :: Glue ) ; Dst = DAG . getNode ( BPFISD :: MEMCPY , dl , VTs , Chain , Dst , Src , DAG . getConstant ( CopyLen , dl , MVT :: i64 ) , DAG . getConstant ( Align , dl , MVT :: i64 ) ) ; return Dst . getValue ( 0 ) ; } </s>

Emit target-specific code that performs a memcpy .


<s> void AMDGPUStructurizeCFG :: analyzeLoop ( BasicBlock * BB , unsigned & LoopIdx ) { BranchInst * Term = cast < BranchInst > ( BB -> getTerminator ( ) ) ; for ( unsigned i = 0 , e = Term -> getNumSuccessors ( ) ; i != e ; ++ i ) { BasicBlock * Succ = Term -> getSuccessor ( i ) ; if ( ! Visited . count ( Succ ) ) continue ; buildPredicate ( Term , i , LoopPred , true ) ; LoopEnd = BB ; if ( Visited [ Succ ] < LoopIdx ) { LoopIdx = Visited [ Succ ] ; LoopStart = Succ ; } } } </s>

Analyze the loop code , return true if it can not be understood .


<s> bool CJGFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) BuildMI ( MBB , MI , DL , TII . get ( CJG :: POP ) , CSI [ i ] . getReg ( ) ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool Thumb2SizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { const TargetMachine & TM = MF . getTarget ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( TM . getInstrInfo ( ) ) ; bool Modified = false ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) Modified |= ReduceMBB ( * I ) ; return Modified ; } </s>


<s> static bool exact_dependency_1 ( rtx addr , rtx insn ) { enum rtx_code code ; const char * format_ptr ; int i , j ; code = GET_CODE ( insn ) ; switch ( code ) { case MEM : if ( rtx_equal_p ( addr , insn ) ) return true ; break ; case REG : CASE_CONST_ANY : case SYMBOL_REF : case CODE_LABEL : case PC : case CC0 : case EXPR_LIST : return false ; default : break ; } format_ptr = GET_RTX_FORMAT ( code ) ; for ( i = 0 ; i < GET_RTX_LENGTH ( code ) ; i ++ ) { switch ( * format_ptr ++ ) { case 'e' : if ( exact_dependency_1 ( addr , XEXP ( insn , i ) ) ) return true ; break ; case 'E' : for ( j = 0 ; j < XVECLEN ( insn , i ) ; j ++ ) if ( exact_dependency_1 ( addr , XVECEXP ( insn , i , j ) ) ) return true ; break ; } } return false ; } </s>

Helper function for exact_store_load_dependency . Return true if addr is found in insn .


<s> rtx neon_make_constant ( rtx vals , bool generate ) { machine_mode mode = GET_MODE ( vals ) ; rtx target ; rtx const_vec = NULL_RTX ; int n_elts = GET_MODE_NUNITS ( mode ) ; int n_const = 0 ; int i ; if ( GET_CODE ( vals ) == CONST_VECTOR ) const_vec = vals ; else if ( GET_CODE ( vals ) == PARALLEL ) { for ( i = 0 ; i < n_elts ; ++ i ) { rtx x = XVECEXP ( vals , 0 , i ) ; if ( CONST_INT_P ( x ) || CONST_DOUBLE_P ( x ) ) n_const ++ ; } if ( n_const == n_elts ) const_vec = gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , 0 ) ) ; } else gcc_unreachable ( ) ; if ( const_vec != NULL && simd_immediate_valid_for_move ( const_vec , mode , NULL , NULL ) ) return const_vec ; else if ( TARGET_HAVE_MVE && ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL ) ) return mve_bool_vec_to_const ( const_vec ) ; else if ( ( target = neon_vdup_constant ( vals , generate ) ) != NULL_RTX ) return target ; else if ( const_vec != NULL_RTX ) return arm_disable_literal_pool ? NULL_RTX : const_vec ; else return NULL_RTX ; } </s>

Generate code to load VALS , which is a PARALLEL containing only constants ( for vec_init ) or CONST_VECTOR , efficiently into a register . Returns an RTX to copy into the register , or NULL_RTX for a PARALLEL that can not be converted into a CONST_VECTOR .


<s> static void replace_mov_pcrel_step2 ( rtx_insn * insn ) { rtx pattern = PATTERN ( insn ) ; rtx unspec ; rtx addr ; rtx opnds [ 3 ] ; rtx_insn * new_insns ; rtx got_rtx = tilegx_got_rtx ( ) ; gcc_assert ( GET_CODE ( pattern ) == SET ) ; opnds [ 0 ] = SET_DEST ( pattern ) ; unspec = SET_SRC ( pattern ) ; gcc_assert ( GET_CODE ( unspec ) == UNSPEC ) ; gcc_assert ( XINT ( unspec , 1 ) == UNSPEC_INSN_ADDR_SHL16INSLI ) ; opnds [ 1 ] = XVECEXP ( unspec , 0 , 0 ) ; addr = XVECEXP ( unspec , 0 , 1 ) ; gcc_assert ( GET_CODE ( addr ) == CONST ) ; unspec = XEXP ( addr , 0 ) ; gcc_assert ( GET_CODE ( unspec ) == UNSPEC ) ; gcc_assert ( XINT ( unspec , 1 ) == UNSPEC_HW0_PCREL ) ; opnds [ 2 ] = XVECEXP ( unspec , 0 , 0 ) ; if ( GET_CODE ( opnds [ 2 ] ) != SYMBOL_REF ) return ; start_sequence ( ) ; if ( flag_pic == 1 ) { if ( TARGET_32BIT ) emit_insn ( gen_add_got16_32bit ( opnds [ 0 ] , got_rtx , opnds [ 2 ] ) ) ; else emit_insn ( gen_add_got16 ( opnds [ 0 ] , got_rtx , opnds [ 2 ] ) ) ; } else { if ( TARGET_32BIT ) emit_insn ( gen_mov_got32_step2_32bit ( opnds [ 0 ] , opnds [ 1 ] , opnds [ 2 ] ) ) ; else emit_insn ( gen_mov_got32_step2 ( opnds [ 0 ] , opnds [ 1 ] , opnds [ 2 ] ) ) ; } new_insns = get_insns ( ) ; end_sequence ( ) ; replace_insns ( insn , new_insns ) ; } </s>

Do the second replacement step in tilegx_fixup_pcrel_references .


<s> Value * AArch64TargetLowering :: emitLoadLinked ( IRBuilder < > & Builder , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Type * ValTy = cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ; bool IsAcquire = isAtLeastAcquire ( Ord ) ; if ( ValTy -> getPrimitiveSizeInBits ( ) == 128 ) { Intrinsic :: ID Int = IsAcquire ? Intrinsic :: aarch64_ldaxp : Intrinsic :: aarch64_ldxp ; Function * Ldxr = llvm :: Intrinsic :: getDeclaration ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldxr , Addr , "lohi" ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ; Lo = Builder . CreateZExt ( Lo , ValTy , "lo64" ) ; Hi = Builder . CreateZExt ( Hi , ValTy , "hi64" ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , 64 ) ) , "val64" ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; Intrinsic :: ID Int = IsAcquire ? Intrinsic :: aarch64_ldaxr : Intrinsic :: aarch64_ldxr ; Function * Ldxr = llvm :: Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateTruncOrBitCast ( Builder . CreateCall ( Ldxr , Addr ) , cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ) ; } </s>

Perform a load-linked operation on Addr , returning a `` Value * '' with the corresponding pointee type .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> void loongarch_expand_scc ( rtx operands [ ] ) { rtx target = operands [ 0 ] ; enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; rtx op0 = operands [ 2 ] ; rtx op1 = operands [ 3 ] ; loongarch_extend_comparands ( code , & op0 , & op1 ) ; op0 = force_reg ( word_mode , op0 ) ; gcc_assert ( GET_MODE_CLASS ( GET_MODE ( op0 ) ) == MODE_INT ) ; if ( code == EQ || code == NE ) { rtx zie = loongarch_zero_if_equal ( op0 , op1 ) ; loongarch_emit_binary ( code , target , zie , const0_rtx ) ; } else loongarch_emit_int_order_test ( code , 0 , target , op0 , op1 ) ; } </s>

Try performing the comparison in OPERANDS [ 1 ] , whose arms are OPERANDS [ 2 ] and OPERAND [ 3 ] . Store the result in OPERANDS [ 0 ] . On 64-bit targets , the mode of the comparison and target will always be SImode , thus possibly narrower than that of the comparison 's operands .


<s> void ARMPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableARMLoadStoreOpt ) addPass ( createARMLoadStoreOptimizationPass ( ) ) ; addPass ( new ARMExecutionDomainFix ( ) ) ; addPass ( createBreakFalseDeps ( ) ) ; } addPass ( createARMExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createThumb2SizeReductionPass ( [ this ] ( const Function & F ) { return this -> TM -> getSubtarget < ARMSubtarget > ( F ) . restrictIT ( ) ; } ) ) ; addPass ( createIfConverter ( [ ] ( const MachineFunction & MF ) { return ! MF . getSubtarget < ARMSubtarget > ( ) . isThumb1Only ( ) ; } ) ) ; } addPass ( createMVEVPTBlockPass ( ) ) ; addPass ( createThumb2ITBlockPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & PostMachineSchedulerID ) ; addPass ( & PostRASchedulerID ) ; } } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> static enum aarch64_parse_opt_result aarch64_parse_cpu ( const char * to_parse , const struct processor * * res , unsigned long * isa_flags , std :: string * invalid_extension ) { const char * ext ; const struct processor * cpu ; size_t len ; ext = strchr ( to_parse , '+' ) ; if ( ext != NULL ) len = ext - to_parse ; else len = strlen ( to_parse ) ; if ( len == 0 ) return AARCH64_PARSE_MISSING_ARG ; for ( cpu = all_cores ; cpu -> name != NULL ; cpu ++ ) { if ( strlen ( cpu -> name ) == len && strncmp ( cpu -> name , to_parse , len ) == 0 ) { unsigned long isa_temp = cpu -> flags ; if ( ext != NULL ) { enum aarch64_parse_opt_result ext_res = aarch64_parse_extension ( ext , & isa_temp , invalid_extension ) ; if ( ext_res != AARCH64_PARSE_OK ) return ext_res ; } * res = cpu ; * isa_flags = isa_temp ; return AARCH64_PARSE_OK ; } } return AARCH64_PARSE_INVALID_ARG ; } </s>

Parse the TO_PARSE string and put the result tuning in RES and the architecture flags in ISA_FLAGS . Return an aarch64_parse_opt_result describing the parse result . If there is an error parsing , RES and ISA_FLAGS are left unchanged .


<s> BitVector SIRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AMDGPU :: INDIRECT_BASE_ADDR ) ; reserveRegisterTuples ( Reserved , AMDGPU :: EXEC ) ; reserveRegisterTuples ( Reserved , AMDGPU :: FLAT_SCR ) ; reserveRegisterTuples ( Reserved , AMDGPU :: M0 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_SHARED_BASE ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_SHARED_LIMIT ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_PRIVATE_BASE ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_PRIVATE_LIMIT ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TBA ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TMA ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP0_TTMP1 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP2_TTMP3 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP4_TTMP5 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP6_TTMP7 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP8_TTMP9 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP10_TTMP11 ) ; const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; unsigned MaxNumSGPRs = ST . getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = AMDGPU :: SGPR_32RegClass . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = AMDGPU :: SGPR_32RegClass . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } unsigned MaxNumVGPRs = ST . getMaxNumVGPRs ( MF ) ; unsigned TotalNumVGPRs = AMDGPU :: VGPR_32RegClass . getNumRegs ( ) ; for ( unsigned i = MaxNumVGPRs ; i < TotalNumVGPRs ; ++ i ) { unsigned Reg = AMDGPU :: VGPR_32RegClass . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } const SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , ScratchWaveOffsetReg ) ; } unsigned ScratchRSrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRSrcReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , ScratchRSrcReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , ScratchWaveOffsetReg ) ) ; } unsigned StackPtrReg = MFI -> getStackPtrOffsetReg ( ) ; if ( StackPtrReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , StackPtrReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , StackPtrReg ) ) ; } unsigned FrameReg = MFI -> getFrameOffsetReg ( ) ; if ( FrameReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , FrameReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , FrameReg ) ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> const Comet2InstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> static unsigned addLiveIn ( MachineFunction & MF , unsigned PReg , const TargetRegisterClass * RC ) { unsigned VReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MF . getRegInfo ( ) . addLiveIn ( PReg , VReg ) ; return VReg ; } </s>

addLiveIn - Add the specified register as a live-in .


<s>
void
R600SchedStrategy
::
releaseTopNode
(
SUnit
*
SU
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Top Releasing "
;
SU
->
dump
(
DAG
)
;
)
;
}
</s>

SU has had all predecessor dependencies resolved .


<s> bool MachineModulePass :: runOnModule ( Module & M ) { bool Changed = runOnMachineModule ( M ) ; return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> static inline bool mode_supports_pre_incdec_p ( machine_mode mode ) { return ( ( reg_addr [ mode ] . addr_mask [ RELOAD_REG_ANY ] & RELOAD_REG_PRE_INCDEC ) != 0 ) ; } </s>

Helper function to say whether a mode supports PRE_INC or PRE_DEC .


<s>
bool
SystemZShortenInst
::
processBlock
(
MachineBasicBlock
&
MBB
)
{
bool
Changed
=
false
;
unsigned
LiveLow
=
0
;
unsigned
LiveHigh
=
0
;
for
(
auto
SI
=
MBB
.
succ_begin
(
)
,
SE
=
MBB
.
succ_end
(
)
;
SI
!=
SE
;
++
SI
)
{
for
(
auto
LI
=
(
*
SI
)
->
livein_begin
(
)
,
LE
=
(
*
SI
)
->
livein_end
(
)
;
LI
!=
LE
;
++
LI
)
{
unsigned
Reg
=
*
LI
;
assert
(
Reg
<
SystemZ
::
NUM_TARGET_REGS
&&
"Invalid register number"
)
;
LiveLow
|=
LowGPRs
[
Reg
]
;
LiveHigh
|=
HighGPRs
[
Reg
]
;
}
}
for
(
auto
MBBI
=
MBB
.
rbegin
(
)
,
MBBE
=
MBB
.
rend
(
)
;
MBBI
!=
MBBE
;
++
MBBI
)
{
MachineInstr
&
MI
=
*
MBBI
;
unsigned
Opcode
=
MI
.
getOpcode
(
)
;
if
(
Opcode
==
SystemZ
::
IILF
)
Changed
|=
shortenIIF
(
MI
,
LowGPRs
,
LiveHigh
,
SystemZ
::
LLILL
,
SystemZ
::
LLILH
)
;
else
if
(
Opcode
==
SystemZ
::
IIHF
)
Changed
|=
shortenIIF
(
MI
,
HighGPRs
,
LiveLow
,
SystemZ
::
LLIHL
,
SystemZ
::
LLIHH
)
;
unsigned
UsedLow
=
0
;
unsigned
UsedHigh
=
0
;
for
(
auto
MOI
=
MI
.
operands_begin
(
)
,
MOE
=
MI
.
operands_end
(
)
;
MOI
!=
MOE
;
++
MOI
)
{
MachineOperand
&
MO
=
*
MOI
;
if
(
MO
.
isReg
(
)
)
{
if
(
unsigned
Reg
=
MO
.
getReg
(
)
)
{
assert
(
Reg
<
SystemZ
::
NUM_TARGET_REGS
&&
"Invalid register number"
)
;
if
(
MO
.
isDef
(
)
)
{
LiveLow
&=
~
LowGPRs
[
Reg
]
;
LiveHigh
&=
~
HighGPRs
[
Reg
]
;
}
else
if
(
!
MO
.
isUndef
(
)
)
{
UsedLow
|=
LowGPRs
[
Reg
]
;
UsedHigh
|=
HighGPRs
[
Reg
]
;
}
}
}
}
LiveLow
|=
UsedLow
;
LiveHigh
|=
UsedHigh
;
}
return
Changed
;
}
</s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .