<s> SDNode * SITargetLowering :: PostISelFolding ( MachineSDNode * Node , SelectionDAG & DAG ) const { const SIInstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; unsigned Opcode = Node -> getMachineOpcode ( ) ; if ( TII -> isMIMG ( Opcode ) && ! TII -> get ( Opcode ) . mayStore ( ) && ! TII -> isGather4 ( Opcode ) && ! TII -> isD16 ( Opcode ) ) { return adjustWritemask ( Node , DAG ) ; } if ( Opcode == AMDGPU :: INSERT_SUBREG || Opcode == AMDGPU :: REG_SEQUENCE ) { legalizeTargetIndependentNode ( Node , DAG ) ; return Node ; } switch ( Opcode ) { case AMDGPU :: V_DIV_SCALE_F32 : case AMDGPU :: V_DIV_SCALE_F64 : { SDValue Src0 = Node -> getOperand ( 0 ) ; SDValue Src1 = Node -> getOperand ( 1 ) ; SDValue Src2 = Node -> getOperand ( 2 ) ; if ( ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) != AMDGPU :: IMPLICIT_DEF ) && ( Src0 == Src1 || Src0 == Src2 ) ) break ; MVT VT = Src0 . getValueType ( ) . getSimpleVT ( ) ; const TargetRegisterClass * RC = getRegClassFor ( VT ) ; MachineRegisterInfo & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue UndefReg = DAG . getRegister ( MRI . createVirtualRegister ( RC ) , VT ) ; SDValue ImpDef = DAG . getCopyToReg ( DAG . getEntryNode ( ) , SDLoc ( Node ) , UndefReg , Src0 , SDValue ( ) ) ; if ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) == AMDGPU :: IMPLICIT_DEF ) { if ( Src1 . isMachineOpcode ( ) && Src1 . getMachineOpcode ( ) != AMDGPU :: IMPLICIT_DEF ) Src0 = Src1 ; else if ( Src2 . isMachineOpcode ( ) && Src2 . getMachineOpcode ( ) != AMDGPU :: IMPLICIT_DEF ) Src0 = Src2 ; else { assert ( Src1 . getMachineOpcode ( ) == AMDGPU :: IMPLICIT_DEF ) ; Src0 = UndefReg ; Src1 = UndefReg ; } } else break ; SmallVector < SDValue , 4 > Ops = { Src0 , Src1 , Src2 } ; for ( unsigned I = 3 , N = Node -> getNumOperands ( ) ; I != N ; ++ I ) Ops . push_back ( Node -> getOperand ( I ) ) ; Ops . push_back ( ImpDef . getValue ( 1 ) ) ; return DAG . getMachineNode ( Opcode , SDLoc ( Node ) , Node -> getVTList ( ) , Ops ) ; } default : break ; } return Node ; } </s>

Fold the instructions after selecting them .


<s>
SDValue
VECustomDAG
::
getUnpack
(
EVT
DestVT
,
SDValue
Vec
,
PackElem
Part
,
SDValue
AVL
)
const
{
assert
(
getAnnotatedNodeAVL
(
AVL
)
.
second
&&
"Expected a pack-legalized AVL"
)
;
unsigned
OC
=
(
Part
==
PackElem
::
Lo
)
VEISD
::
VEC_UNPACK_LO
:
VEISD
::
VEC_UNPACK_HI
;
return
DAG
.
getNode
(
OC
,
DL
,
DestVT
,
Vec
,
AVL
)
;
}
</s>


<s> SDValue PPCTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { if ( Subtarget . isSVR4ABI ( ) ) { if ( Subtarget . isPPC64 ( ) ) return LowerFormalArguments_64SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; else return LowerFormalArguments_32SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } else { return LowerFormalArguments_Darwin ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> void WebAssemblyPassConfig :: addIRPasses ( ) { if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( TM ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createWebAssemblyOptimizeReturned ( ) ) ; if ( EnableEmException || EnableEmSjLj ) addPass ( createWebAssemblyLowerEmscriptenEHSjLj ( EnableEmException , EnableEmSjLj ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

WebAssembly WebAssembly WebAssembly WebAssembly


"Object file emission is not supported with PTX"

Add passes to the specified pass manager to get the specified file emitted .


"JVM doesn't support non-C calling conventions"

"JVM hasn't implemented inalloca arguments"

"JVM hasn't implemented cons regs arguments"

"JVM hasn't implemented cons regs last arguments"


"XtensaInstrInfo::copyPhysReg not yet implemented"


<s> static bool nios2_symbol_binds_local_p ( const_rtx x ) { return ( SYMBOL_REF_DECL ( x ) ? targetm . binds_local_p ( SYMBOL_REF_DECL ( x ) ) : SYMBOL_REF_LOCAL_P ( x ) ) ; } </s>

Return true if SYMBOL_REF X binds locally .


<s> static void mips_sim_wait_regs_1 ( rtx * x , void * data ) { subrtx_var_iterator :: array_type array ; FOR_EACH_SUBRTX_VAR ( iter , array , * x , NONCONST ) if ( REG_P ( * iter ) ) mips_sim_wait_reg ( ( struct mips_sim * ) data , mips_sim_insn , * iter ) ; } </s>

Call mips_sim_wait_regs_2 ( R , DATA ) for each register R mentioned in * X .


<s> static bool rs6000_cannot_force_const_mem ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { if ( GET_CODE ( x ) == HIGH ) return true ; if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && SYMBOL_REF_P ( XEXP ( XEXP ( x , 0 ) , 0 ) ) && SYMBOL_REF_TLS_MODEL ( XEXP ( XEXP ( x , 0 ) , 0 ) ) != 0 ) return true ; return TARGET_ELF && tls_referenced_p ( x ) ; } </s>


<s> static void expand_block_move_1 ( rtx dst_reg , rtx src_reg , rtx bytes_rtx ) { emit_library_call ( byt_memcpy_libfunc , LCT_NORMAL , VOIDmode , dst_reg , Pmode , src_reg , Pmode , convert_to_mode ( TYPE_MODE ( sizetype ) , bytes_rtx , TYPE_UNSIGNED ( sizetype ) ) , TYPE_MODE ( sizetype ) ) ; } </s>

Generate a call to a library function to move BYTES_RTX bytes from address SRC_REG to address DST_REG in 1-byte chunks .


<s>
void
rs6000_xcoff_declare_function_name
(
FILE
*
file
,
const
char
*
name
,
tree
decl
)
{
char
*
buffer
=
(
char
*
)
alloca
(
strlen
(
name
)
+
1
)
;
char
*
p
;
int
dollar_inside
=
0
;
struct
declare_alias_data
data
=
{
file
,
false
}
;
strcpy
(
buffer
,
name
)
;
p
=
strchr
(
buffer
,
'$'
)
;
while
(
p
)
{
*
p
=
'_'
;
dollar_inside
++
;
p
=
strchr
(
p
+
1
,
'$'
)
;
}
if
(
TREE_PUBLIC
(
decl
)
)
{
if
(
!
RS6000_WEAK
||
!
DECL_WEAK
(
decl
)
)
{
if
(
dollar_inside
)
{
fprintf
(
file
,
"\t.rename .%s,\".%s\"\n"
,
buffer
,
name
)
;
fprintf
(
file
,
"\t.rename %s,\"%s\"\n"
,
buffer
,
name
)
;
}
fputs
(
"\t.globl ."
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
putc
(
'\n'
,
file
)
;
}
}
else
{
if
(
dollar_inside
)
{
fprintf
(
file
,
"\t.rename .%s,\".%s\"\n"
,
buffer
,
name
)
;
fprintf
(
file
,
"\t.rename %s,\"%s\"\n"
,
buffer
,
name
)
;
}
fputs
(
"\t.lglobl ."
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
putc
(
'\n'
,
file
)
;
}
fputs
(
"\t.csect "
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
fputs
(
TARGET_32BIT
"[DS]\n"
:
"[DS],3\n"
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
fputs
(
":\n"
,
file
)
;
symtab_node
::
get
(
decl
)
->
call_for_symbol_and_aliases
(
rs6000_declare_alias
,
&
data
,
true
)
;
fputs
(
TARGET_32BIT
"\t.long ."
:
"\t.llong ."
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
fputs
(
", TOC[tc0], 0\n"
,
file
)
;
in_section
=
;
switch_to_section
(
function_section
(
decl
)
)
;
putc
(
'.'
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
fputs
(
":\n"
,
file
)
;
data
.
function_descriptor
=
true
;
symtab_node
::
get
(
decl
)
->
call_for_symbol_and_aliases
(
rs6000_declare_alias
,
&
data
,
true
)
;
if
(
write_symbols
!=
NO_DEBUG
&&
!
DECL_IGNORED_P
(
decl
)
)
xcoffout_declare_function
(
file
,
decl
,
buffer
)
;
return
;
}
</s>

This macro produces the initial definition of a function name . On the RS/6000 , we need to place an extra ' . ' in the function name and output the function descriptor . Dollar signs are converted to underscores . The csect for the function will have already been created when text_section was selected . We do have to go back to that csect , however . The third and fourth parameters to the .function pseudo-op ( 16 and 044 ) are placeholders which no longer have any use . Because AIX assembler 's .set command has unexpected semantics , we output all aliases as alternative labels in front of the definition .


<s>
Register
SparcTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
const
MachineFunction
&
MF
)
const
{
Register
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"i0"
,
SP
::
I0
)
.
Case
(
"i1"
,
SP
::
I1
)
.
Case
(
"i2"
,
SP
::
I2
)
.
Case
(
"i3"
,
SP
::
I3
)
.
Case
(
"i4"
,
SP
::
I4
)
.
Case
(
"i5"
,
SP
::
I5
)
.
Case
(
"i6"
,
SP
::
I6
)
.
Case
(
"i7"
,
SP
::
I7
)
.
Case
(
"o0"
,
SP
::
O0
)
.
Case
(
"o1"
,
SP
::
O1
)
.
Case
(
"o2"
,
SP
::
O2
)
.
Case
(
"o3"
,
SP
::
O3
)
.
Case
(
"o4"
,
SP
::
O4
)
.
Case
(
"o5"
,
SP
::
O5
)
.
Case
(
"o6"
,
SP
::
O6
)
.
Case
(
"o7"
,
SP
::
O7
)
.
Case
(
"l0"
,
SP
::
L0
)
.
Case
(
"l1"
,
SP
::
L1
)
.
Case
(
"l2"
,
SP
::
L2
)
.
Case
(
"l3"
,
SP
::
L3
)
.
Case
(
"l4"
,
SP
::
L4
)
.
Case
(
"l5"
,
SP
::
L5
)
.
Case
(
"l6"
,
SP
::
L6
)
.
Case
(
"l7"
,
SP
::
L7
)
.
Case
(
"g0"
,
SP
::
G0
)
.
Case
(
"g1"
,
SP
::
G1
)
.
Case
(
"g2"
,
SP
::
G2
)
.
Case
(
"g3"
,
SP
::
G3
)
.
Case
(
"g4"
,
SP
::
G4
)
.
Case
(
"g5"
,
SP
::
G5
)
.
Case
(
"g6"
,
SP
::
G6
)
.
Case
(
"g7"
,
SP
::
G7
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> bool loongarch_symbolic_constant_p ( rtx x , enum loongarch_symbol_type * symbol_type ) { rtx offset ; split_const ( x , & x , & offset ) ; if ( UNSPEC_ADDRESS_P ( x ) ) { * symbol_type = UNSPEC_ADDRESS_TYPE ( x ) ; x = UNSPEC_ADDRESS ( x ) ; } else if ( SYMBOL_REF_P ( x ) || LABEL_REF_P ( x ) ) { * symbol_type = loongarch_classify_symbol ( x ) ; if ( * symbol_type == SYMBOL_TLS ) return true ; } else return false ; if ( offset == const0_rtx ) return true ; switch ( * symbol_type ) { case SYMBOL_TLS_IE : case SYMBOL_TLS_LE : case SYMBOL_TLSGD : case SYMBOL_TLSLDM : case SYMBOL_PCREL : case SYMBOL_PCREL64 : return sext_hwi ( INTVAL ( offset ) , 32 ) == INTVAL ( offset ) ; case SYMBOL_GOT_DISP : case SYMBOL_TLS : return false ; } gcc_unreachable ( ) ; } </s>

Return true if X is a symbolic constant . If it is , store the type of the symbol in * SYMBOL_TYPE .


<s> static bool ix86_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t regclass ) { if ( from == to ) return true ; if ( MAYBE_FLOAT_CLASS_P ( regclass ) ) return false ; if ( MAYBE_SSE_CLASS_P ( regclass ) || MAYBE_MMX_CLASS_P ( regclass ) ) { int mov_size = MAYBE_SSE_CLASS_P ( regclass ) && TARGET_SSE2 ? 2 : 4 ; if ( GET_MODE_SIZE ( from ) < mov_size ) return false ; } return true ; } </s>


<s> int R600FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const R600RegisterInfo * RI = MF . getSubtarget < R600Subtarget > ( ) . getRegisterInfo ( ) ; FrameReg = RI -> getFrameRegister ( MF ) ; unsigned OffsetBytes = 2 * ( getStackWidth ( MF ) * 4 ) ; int UpperBound = FI == - 1 ? MFI . getNumObjects ( ) : FI ; for ( int i = MFI . getObjectIndexBegin ( ) ; i < UpperBound ; ++ i ) { OffsetBytes = alignTo ( OffsetBytes , MFI . getObjectAlign ( i ) ) ; OffsetBytes += MFI . getObjectSize ( i ) ; OffsetBytes = alignTo ( OffsetBytes , Align ( 4 ) ) ; } if ( FI != - 1 ) OffsetBytes = alignTo ( OffsetBytes , MFI . getObjectAlign ( FI ) ) ; return OffsetBytes / ( getStackWidth ( MF ) * 4 ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s>
void
i386_pe_file_end
(
void
)
{
struct
extern_list
*
p
;
for
(
p
=
extern_head
;
p
!=
;
p
=
p
->
next
)
{
tree
decl
;
decl
=
p
->
decl
;
if
(
!
TREE_ASM_WRITTEN
(
decl
)
&&
TREE_SYMBOL_REFERENCED
(
DECL_ASSEMBLER_NAME
(
decl
)
)
)
{
const
char
*
realsym
=
i386_find_on_wrapper_list
(
p
->
name
)
;
if
(
realsym
)
i386_pe_declare_function_type
(
asm_out_file
,
concat
(
"__real_"
,
realsym
,
)
,
TREE_PUBLIC
(
decl
)
)
;
TREE_ASM_WRITTEN
(
decl
)
=
1
;
i386_pe_declare_function_type
(
asm_out_file
,
p
->
name
,
TREE_PUBLIC
(
decl
)
)
;
}
}
if
(
export_head
)
{
struct
export_list
*
q
;
drectve_section
(
)
;
for
(
q
=
export_head
;
q
!=
;
q
=
q
->
next
)
{
fprintf
(
asm_out_file
,
"\t.ascii \" -export:\\\"%s\\\"%s\"\n"
,
default_strip_name_encoding
(
q
->
name
)
,
(
q
->
is_data
",data"
:
""
)
)
;
}
}
if
(
stub_head
)
{
struct
stub_list
*
q
;
for
(
q
=
stub_head
;
q
!=
;
q
=
q
->
next
)
{
const
char
*
name
=
q
->
name
;
const
char
*
oname
;
if
(
name
[
0
]
==
'*'
)
++
name
;
oname
=
name
;
if
(
name
[
0
]
==
'.'
)
++
name
;
if
(
!
startswith
(
name
,
"refptr."
)
)
continue
;
name
+=
7
;
fprintf
(
asm_out_file
,
"\t.section\t.rdata$%s, \"dr\"\n"
"\t.globl\t%s\n"
"\t.linkonce\tdiscard\n"
,
oname
,
oname
)
;
fprintf
(
asm_out_file
,
"%s:\n\t.quad\t%s\n"
,
oname
,
name
)
;
}
}
}
</s>

This is called at the end of assembly . For each external function which has not been defined , we output a declaration now . We also output the .drectve section .


<s> bool SIRegisterInfo :: needsFrameBaseReg ( MachineInstr * MI , int64_t Offset ) const { if ( ! MI -> mayLoadOrStore ( ) ) return false ; int64_t FullOffset = Offset + getMUBUFInstrOffset ( MI ) ; return ! isUInt < 12 > ( FullOffset ) ; } </s>

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


"64-bit code requested on a subtarget that doesn't support it!"

This constructor initializes the data members to match that of the specified triple .


<s>
void
SIInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
Register
DestReg
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
SIMachineFunctionInfo
*
MFI
=
MF
->
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MachineFrameInfo
&
FrameInfo
=
MF
->
getFrameInfo
(
)
;
const
DebugLoc
&
DL
=
MBB
.
findDebugLoc
(
MI
)
;
unsigned
SpillSize
=
TRI
->
getSpillSize
(
*
RC
)
;
MachinePointerInfo
PtrInfo
=
MachinePointerInfo
::
getFixedStack
(
*
MF
,
FrameIndex
)
;
MachineMemOperand
*
MMO
=
MF
->
getMachineMemOperand
(
PtrInfo
,
MachineMemOperand
::
MOLoad
,
FrameInfo
.
getObjectSize
(
FrameIndex
)
,
FrameInfo
.
getObjectAlign
(
FrameIndex
)
)
;
if
(
RI
.
isSGPRClass
(
RC
)
)
{
MFI
->
setHasSpilledSGPRs
(
)
;
assert
(
DestReg
!=
AMDGPU
::
M0
&&
"m0 should not be reloaded into"
)
;
assert
(
DestReg
!=
AMDGPU
::
EXEC_LO
&&
DestReg
!=
AMDGPU
::
EXEC_HI
&&
DestReg
!=
AMDGPU
::
EXEC
&&
"exec should not be spilled"
)
;
const
MCInstrDesc
&
OpDesc
=
get
(
getSGPRSpillRestoreOpcode
(
SpillSize
)
)
;
if
(
DestReg
.
isVirtual
(
)
&&
SpillSize
==
4
)
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
MRI
.
constrainRegClass
(
DestReg
,
&
AMDGPU
::
SReg_32_XM0_XEXECRegClass
)
;
}
if
(
RI
.
spillSGPRToVGPR
(
)
)
FrameInfo
.
setStackID
(
FrameIndex
,
TargetStackID
::
SGPRSpill
)
;
BuildMI
(
MBB
,
MI
,
DL
,
OpDesc
,
DestReg
)
.
addFrameIndex
(
FrameIndex
)
.
addMemOperand
(
MMO
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
,
RegState
::
Implicit
)
;
return
;
}
unsigned
Opcode
=
RI
.
isVectorSuperClass
(
RC
)
getAVSpillRestoreOpcode
(
SpillSize
)
:
RI
.
isAGPRClass
(
RC
)
getAGPRSpillRestoreOpcode
(
SpillSize
)
:
getVGPRSpillRestoreOpcode
(
SpillSize
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opcode
)
,
DestReg
)
.
addFrameIndex
(
FrameIndex
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> bool isToken ( ) const override { return Kind == KindToken ; } </s>


<s> void FISCInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( FISC :: MOVrr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } </s>


<s> static void arm_encode_section_info ( tree decl , rtx rtl , int first ) { if ( optimize > 0 && TREE_CONSTANT ( decl ) ) SYMBOL_REF_FLAG ( XEXP ( rtl , 0 ) ) = 1 ; default_encode_section_info ( decl , rtl , first ) ; } </s>

Symbols in the text segment can be accessed without indirecting via the constant pool ; it may take an extra binary operation , but this is still faster than indirecting via memory . Do n't do this when not optimizing , since we wo n't be calculating al of the offsets necessary to do this simplification .


<s>
uint32_t
AMDGPUTargetLowering
::
getImplicitParameterOffset
(
const
AMDGPUMachineFunction
*
MFI
,
const
ImplicitParameter
Param
)
const
{
uint64_t
ArgOffset
=
MFI
->
getABIArgOffset
(
)
;
switch
(
Param
)
{
case
GRID_DIM
:
return
ArgOffset
;
case
GRID_OFFSET
:
return
ArgOffset
+
4
;
}
llvm_unreachable
(
"unexpected implicit parameter type"
)
;
}
</s>

Helper function that returns the byte offset of the given type of implicit parameter .

AMDGPU
AMDGPU
AMDGPU
4
"unexpected implicit parameter type"


<s> static bool expand_vec_perm_vpshufb2_vpermq ( struct expand_vec_perm_d * d ) { rtx rperm [ 2 ] [ 32 ] , vperm , l , h , hp , op , m128 ; unsigned int i , nelt , eltsz ; if ( ! TARGET_AVX2 || ! d -> one_operand_p || ( d -> vmode != V32QImode && d -> vmode != V16HImode ) ) return false ; if ( d -> testing_p ) return true ; nelt = d -> nelt ; eltsz = GET_MODE_SIZE ( GET_MODE_INNER ( d -> vmode ) ) ; m128 = GEN_INT ( - 128 ) ; for ( i = 0 ; i < nelt ; ++ i ) { unsigned j , e = d -> perm [ i ] & ( nelt / 2 - 1 ) ; unsigned which = ( ( d -> perm [ i ] ^ i ) & ( nelt / 2 ) ) * eltsz ; for ( j = 0 ; j < eltsz ; ++ j ) { rperm [ ! ! which ] [ ( i * eltsz + j ) ^ which ] = GEN_INT ( e * eltsz + j ) ; rperm [ ! which ] [ ( i * eltsz + j ) ^ ( which ^ 16 ) ] = m128 ; } } vperm = gen_rtx_CONST_VECTOR ( V32QImode , gen_rtvec_v ( 32 , rperm [ 1 ] ) ) ; vperm = force_reg ( V32QImode , vperm ) ; h = gen_reg_rtx ( V32QImode ) ; op = gen_lowpart ( V32QImode , d -> op0 ) ; emit_insn ( gen_avx2_pshufbv32qi3 ( h , op , vperm ) ) ; hp = gen_reg_rtx ( V4DImode ) ; op = gen_lowpart ( V4DImode , h ) ; emit_insn ( gen_avx2_permv4di_1 ( hp , op , const2_rtx , GEN_INT ( 3 ) , const0_rtx , const1_rtx ) ) ; vperm = gen_rtx_CONST_VECTOR ( V32QImode , gen_rtvec_v ( 32 , rperm [ 0 ] ) ) ; vperm = force_reg ( V32QImode , vperm ) ; l = gen_reg_rtx ( V32QImode ) ; op = gen_lowpart ( V32QImode , d -> op0 ) ; emit_insn ( gen_avx2_pshufbv32qi3 ( l , op , vperm ) ) ; op = d -> target ; if ( d -> vmode != V32QImode ) op = gen_reg_rtx ( V32QImode ) ; emit_insn ( gen_iorv32qi3 ( op , l , gen_lowpart ( V32QImode , hp ) ) ) ; if ( op != d -> target ) emit_move_insn ( d -> target , gen_lowpart ( d -> vmode , op ) ) ; return true ; } </s>

Implement arbitrary permutation of one V32QImode and V16QImode operand with two vpshufb insns , vpermq and vpor . We should have already failed all two or three instruction sequences .


<s> unsigned SIRegisterInfo :: findUnusedRegister ( const MachineRegisterInfo & MRI , const TargetRegisterClass * RC ) const { for ( TargetRegisterClass :: iterator I = RC -> begin ( ) , E = RC -> end ( ) ; I != E ; ++ I ) { if ( ! MRI . isPhysRegUsed ( * I ) ) return * I ; } return AMDGPU :: NoRegister ; } </s>

Returns a lowest register that is not used at any point in the function .


<s> const uint16_t * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { bool ghcCall = false ; if ( MF ) { const Function * F = MF -> getFunction ( ) ; ghcCall = ( F ? F -> getCallingConv ( ) == CallingConv :: GHC : false ) ; } if ( ghcCall ) return CSR_GHC_SaveList ; else return ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ; } </s>


<s> static rtx m68k_wrap_symbol_into_got_ref ( rtx x , enum m68k_reloc reloc , rtx temp_reg ) { x = m68k_wrap_symbol ( x , reloc , m68k_get_gp ( ) , temp_reg ) ; x = gen_rtx_MEM ( Pmode , x ) ; MEM_READONLY_P ( x ) = 1 ; return x ; } </s>

Does the same as m68k_wrap_symbol , but returns a memory reference to GOT slot .


<s> void ix86_function_specific_restore ( struct gcc_options * opts , struct gcc_options * , struct cl_target_option * ptr ) { enum processor_type old_tune = ix86_tune ; enum processor_type old_arch = ix86_arch ; unsigned HOST_WIDE_INT ix86_arch_mask ; int i ; opts -> x_flag_pic = flag_pic ; ix86_arch = ( enum processor_type ) ptr -> arch ; ix86_schedule = ( enum attr_cpu ) ptr -> schedule ; ix86_tune = ( enum processor_type ) ptr -> tune ; ix86_prefetch_sse = ptr -> prefetch_sse ; ix86_tune_defaulted = ptr -> tune_defaulted ; ix86_arch_specified = ptr -> arch_specified ; opts -> x_ix86_isa_flags_explicit = ptr -> x_ix86_isa_flags_explicit ; opts -> x_ix86_isa_flags2_explicit = ptr -> x_ix86_isa_flags2_explicit ; opts -> x_recip_mask_explicit = ptr -> x_recip_mask_explicit ; opts -> x_ix86_arch_string = ptr -> x_ix86_arch_string ; opts -> x_ix86_tune_string = ptr -> x_ix86_tune_string ; opts -> x_ix86_abi = ptr -> x_ix86_abi ; opts -> x_ix86_asm_dialect = ptr -> x_ix86_asm_dialect ; opts -> x_ix86_branch_cost = ptr -> x_ix86_branch_cost ; opts -> x_ix86_dump_tunes = ptr -> x_ix86_dump_tunes ; opts -> x_ix86_force_align_arg_pointer = ptr -> x_ix86_force_align_arg_pointer ; opts -> x_ix86_force_drap = ptr -> x_ix86_force_drap ; opts -> x_ix86_recip_name = ptr -> x_ix86_recip_name ; opts -> x_ix86_section_threshold = ptr -> x_ix86_section_threshold ; opts -> x_ix86_sse2avx = ptr -> x_ix86_sse2avx ; opts -> x_ix86_stack_protector_guard = ptr -> x_ix86_stack_protector_guard ; opts -> x_ix86_stringop_alg = ptr -> x_ix86_stringop_alg ; opts -> x_ix86_tls_dialect = ptr -> x_ix86_tls_dialect ; opts -> x_ix86_tune_ctrl_string = ptr -> x_ix86_tune_ctrl_string ; opts -> x_ix86_tune_memcpy_strategy = ptr -> x_ix86_tune_memcpy_strategy ; opts -> x_ix86_tune_memset_strategy = ptr -> x_ix86_tune_memset_strategy ; opts -> x_ix86_tune_no_default = ptr -> x_ix86_tune_no_default ; ix86_tune_cost = processor_cost_table [ ix86_tune ] ; if ( opts -> x_optimize_size ) ix86_cost = & ix86_size_cost ; else ix86_cost = ix86_tune_cost ; if ( old_arch != ix86_arch ) { ix86_arch_mask = HOST_WIDE_INT_1U << ix86_arch ; for ( i = 0 ; i < X86_ARCH_LAST ; ++ i ) ix86_arch_features [ i ] = ! ! ( initial_ix86_arch_features [ i ] & ix86_arch_mask ) ; } if ( old_tune != ix86_tune ) set_ix86_tune_features ( opts , ix86_tune , false ) ; } </s>


<s>
SDValue
AAPTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
ExternalSymbol
:
return
LowerExternalSymbol
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
}
llvm_unreachable
(
"unimplemented operand"
)
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

AAP
AAP
ISD::GlobalAddress
ISD::ExternalSymbol
ISD::BlockAddress
ISD::BR_CC
ISD::SELECT_CC
ISD::VASTART
ISD::RETURNADDR
"unimplemented operand"


<s> const uint32_t * ARMBaseRegisterInfo :: getCallPreservedMask ( CallingConv :: ID ) const { return ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


"Could not generate addis value for fusion"

Emit the addis instruction that will be part of a fused instruction sequence .


"********** MI Converging Scheduling VLIW BB#"

"** VLIWMachineScheduler::schedule picking next node\n"

Schedule - This is called back from ScheduleDAGInstrs : :Run ( ) when it 's time to do some work .


<s> static void mips_prepare_pch_save ( void ) { mips_set_compression_mode ( 0 ) ; mips16_globals = 0 ; } </s>


<s> void MetadataStreamer :: begin ( const Module & Mod ) { emitVersion ( ) ; emitPrintf ( Mod ) ; } </s>


<s> void HexagonPassConfig :: addPreEmitPass ( ) { bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) addPass ( createHexagonNewValueJump ( ) , false ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( createHexagonFixupHwLoops ( ) , false ) ; if ( EnableGenMux ) addPass ( createHexagonGenMux ( ) , false ) ; addPass ( createHexagonPacketizer ( ) , false ) ; } addPass ( createHexagonCallFrameInformation ( ) , false ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon


<s> bool MipsSEFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * EntryBlock = & MF -> front ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == Mips :: RA || Reg == Mips :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; bool IsLOHI = ( Reg == Mips :: LO0 || Reg == Mips :: LO0_64 || Reg == Mips :: HI0 || Reg == Mips :: HI0_64 ) ; const Function * Func = MBB . getParent ( ) -> getFunction ( ) ; if ( IsLOHI && Func -> hasFnAttribute ( "interrupt" ) ) { DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Op = 0 ; if ( ! STI . getABI ( ) . ArePtrs64bit ( ) ) { Op = ( Reg == Mips :: HI0 ) ? Mips :: MFHI : Mips :: MFLO ; Reg = Mips :: K0 ; } else { Op = ( Reg == Mips :: HI0 ) ? Mips :: MFHI64 : Mips :: MFLO64 ; Reg = Mips :: K0_64 ; } BuildMI ( MBB , MI , DL , TII . get ( Op ) , Mips :: K0 ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


"\nrs6000_legitimate_address_p: return = %s, mode = %s, "

Debug version of rs6000_legitimate_address_p .


<s> bool runOnModule ( Module & M ) override { AttributeMask AttrMask ; for ( Attribute :: AttrKind I = Attribute :: None ; I != Attribute :: EndAttrKinds ; I = Attribute :: AttrKind ( I + 1 ) ) { if ( ! isValidForDXIL ( I ) ) AttrMask . addAttribute ( I ) ; } for ( auto & F : M . functions ( ) ) { F . removeFnAttrs ( AttrMask ) ; F . removeRetAttrs ( AttrMask ) ; for ( size_t Idx = 0 ; Idx < F . arg_size ( ) ; ++ Idx ) F . removeParamAttrs ( Idx , AttrMask ) ; for ( auto & BB : F ) { IRBuilder < > Builder ( & BB ) ; for ( auto & I : make_early_inc_range ( BB ) ) { if ( I . getOpcode ( ) == Instruction :: FNeg ) { Builder . SetInsertPoint ( & I ) ; Value * In = I . getOperand ( 0 ) ; Value * Zero = ConstantFP :: get ( In -> getType ( ) , - 0.0 ) ; I . replaceAllUsesWith ( Builder . CreateFSub ( Zero , In ) ) ; I . eraseFromParent ( ) ; } } } } return true ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s>
SDValue
LanaiTargetLowering
::
LowerCall
(
TargetLowering
::
CallLoweringInfo
&
CLI
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SelectionDAG
&
DAG
=
CLI
.
DAG
;
SDLoc
&
DL
=
CLI
.
DL
;
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
=
CLI
.
Outs
;
SmallVectorImpl
<
SDValue
>
&
OutVals
=
CLI
.
OutVals
;
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
=
CLI
.
Ins
;
SDValue
Chain
=
CLI
.
Chain
;
SDValue
Callee
=
CLI
.
Callee
;
bool
&
IsTailCall
=
CLI
.
IsTailCall
;
CallingConv
::
ID
CallConv
=
CLI
.
CallConv
;
bool
IsVarArg
=
CLI
.
IsVarArg
;
IsTailCall
=
false
;
switch
(
CallConv
)
{
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
IsVarArg
,
IsTailCall
,
Outs
,
OutVals
,
Ins
,
DL
,
DAG
,
InVals
)
;
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .

Lanai
Lanai
ISD::OutputArg
ISD::InputArg
"Unsupported calling convention"


<s> unsigned RISCVInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : { return get ( Opcode ) . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return 0 ; case RISCV :: PseudoCALL : case RISCV :: PseudoTAIL : case RISCV :: PseudoLLA : return 8 ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const auto & TM = static_cast < const RISCVTargetMachine & > ( MF . getTarget ( ) ) ; return getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .

RISCV RISCV 0 RISCV::PseudoCALL RISCV::PseudoTAIL RISCV::PseudoLLA 8 RISCV 0


<s> static void nvptx_print_address_operand ( FILE * file , rtx x , machine_mode ) { rtx off ; if ( GET_CODE ( x ) == CONST ) x = XEXP ( x , 0 ) ; switch ( GET_CODE ( x ) ) { case PLUS : off = XEXP ( x , 1 ) ; output_address ( XEXP ( x , 0 ) ) ; fprintf ( file , "+" ) ; output_address ( off ) ; break ; case SYMBOL_REF : case LABEL_REF : output_addr_const ( file , x ) ; break ; default : gcc_assert ( GET_CODE ( x ) != MEM ) ; nvptx_print_operand ( file , x , 0 ) ; break ; } } </s>

Subroutine of nvptx_print_operand ; used to print a memory reference X to FILE .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> rtx nds32_legitimize_pic_address ( rtx x ) { rtx addr = x ; rtx reg = gen_reg_rtx ( Pmode ) ; rtx pat ; int relax_group_id = nds32_alloc_relax_group_id ( ) ; if ( GET_CODE ( x ) == LABEL_REF || ( GET_CODE ( x ) == SYMBOL_REF && ( CONSTANT_POOL_ADDRESS_P ( x ) || SYMBOL_REF_LOCAL_P ( x ) ) ) ) { addr = gen_rtx_UNSPEC ( SImode , gen_rtvec ( 1 , x ) , UNSPEC_GOTOFF ) ; addr = gen_rtx_CONST ( SImode , addr ) ; emit_insn ( gen_sym_got ( reg , addr , GEN_INT ( relax_group_id ) ) ) ; x = gen_rtx_PLUS ( Pmode , reg , pic_offset_table_rtx ) ; } else if ( GET_CODE ( x ) == SYMBOL_REF ) { addr = gen_rtx_UNSPEC ( SImode , gen_rtvec ( 1 , x ) , UNSPEC_GOT ) ; addr = gen_rtx_CONST ( SImode , addr ) ; emit_insn ( gen_sym_got ( reg , addr , GEN_INT ( relax_group_id ) ) ) ; x = gen_const_mem ( SImode , gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , reg ) ) ; } else if ( GET_CODE ( x ) == CONST ) { addr = XEXP ( x , 0 ) ; gcc_assert ( GET_CODE ( addr ) == PLUS ) ; rtx op0 = XEXP ( addr , 0 ) ; rtx op1 = XEXP ( addr , 1 ) ; if ( ( GET_CODE ( op0 ) == LABEL_REF || ( GET_CODE ( op0 ) == SYMBOL_REF && ( CONSTANT_POOL_ADDRESS_P ( op0 ) || SYMBOL_REF_LOCAL_P ( op0 ) ) ) ) && GET_CODE ( op1 ) == CONST_INT ) { pat = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , op0 ) , UNSPEC_GOTOFF ) ; pat = gen_rtx_PLUS ( Pmode , pat , op1 ) ; pat = gen_rtx_CONST ( Pmode , pat ) ; emit_insn ( gen_sym_got ( reg , pat , GEN_INT ( relax_group_id ) ) ) ; x = gen_rtx_PLUS ( Pmode , reg , pic_offset_table_rtx ) ; } else if ( GET_CODE ( op0 ) == SYMBOL_REF && GET_CODE ( op1 ) == CONST_INT ) { addr = gen_rtx_UNSPEC ( SImode , gen_rtvec ( 1 , op0 ) , UNSPEC_GOT ) ; addr = gen_rtx_CONST ( SImode , addr ) ; emit_insn ( gen_sym_got ( reg , addr , GEN_INT ( relax_group_id ) ) ) ; addr = gen_const_mem ( SImode , gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , reg ) ) ; emit_move_insn ( reg , addr ) ; if ( satisfies_constraint_Is15 ( op1 ) ) x = gen_rtx_PLUS ( Pmode , reg , op1 ) ; else { rtx tmp_reg = gen_reg_rtx ( SImode ) ; emit_insn ( gen_movsi ( tmp_reg , op1 ) ) ; x = gen_rtx_PLUS ( Pmode , reg , tmp_reg ) ; } } else { debug_rtx ( x ) ; gcc_unreachable ( ) ; } } return x ; } </s>

Expand PIC code for @ GOTOFF and @ GOT . Example for @ GOTOFF : la $ r0 , symbol @ GOTOFF - > sethi $ ta , hi20 ( symbol @ GOTOFF ) ori $ ta , $ ta , lo12 ( symbol @ GOTOFF ) add $ r0 , $ ta , $ gp Example for @ GOT : la $ r0 , symbol @ GOT - > sethi $ ta , hi20 ( symbol @ GOT ) ori $ ta , $ ta , lo12 ( symbol @ GOT ) lw $ r0 , [ $ ta + $ gp ]


<s> static rtx spu_addr_space_legitimize_address ( rtx x , rtx oldx , machine_mode mode , addr_space_t as ) { if ( as != ADDR_SPACE_GENERIC ) return x ; return spu_legitimize_address ( x , oldx , mode ) ; } </s>

Like spu_legitimate_address , except with named address support .


<s> void pa_output_global_address ( FILE * file , rtx x , int round_constant ) { if ( GET_CODE ( x ) == HIGH ) x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == SYMBOL_REF && read_only_operand ( x , VOIDmode ) ) output_addr_const ( file , x ) ; else if ( GET_CODE ( x ) == SYMBOL_REF && ! flag_pic ) { output_addr_const ( file , x ) ; fputs ( "-$global$" , file ) ; } else if ( GET_CODE ( x ) == CONST ) { const char * sep = "" ; int offset = 0 ; rtx base = NULL_RTX ; switch ( GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) ) { case SYMBOL_REF : base = XEXP ( XEXP ( x , 0 ) , 0 ) ; output_addr_const ( file , base ) ; break ; case CONST_INT : offset = INTVAL ( XEXP ( XEXP ( x , 0 ) , 0 ) ) ; break ; default : gcc_unreachable ( ) ; } switch ( GET_CODE ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ) { case SYMBOL_REF : base = XEXP ( XEXP ( x , 0 ) , 1 ) ; output_addr_const ( file , base ) ; break ; case CONST_INT : offset = INTVAL ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ; break ; default : gcc_unreachable ( ) ; } if ( round_constant ) offset = ( ( offset + 0x1000 ) & ~ 0x1fff ) ; switch ( GET_CODE ( XEXP ( x , 0 ) ) ) { case PLUS : if ( offset < 0 ) { offset = - offset ; sep = "-" ; } else sep = "+" ; break ; case MINUS : gcc_assert ( GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == SYMBOL_REF ) ; sep = "-" ; break ; default : gcc_unreachable ( ) ; } if ( ! read_only_operand ( base , VOIDmode ) && ! flag_pic ) fputs ( "-$global$" , file ) ; if ( offset ) fprintf ( file , "%s%d" , sep , offset ) ; } else output_addr_const ( file , x ) ; } </s>

output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF .


<s> void DLXMCCodeEmitter :: encodeInstruction ( const MCInst & Inst , raw_ostream & Ostream , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & SubtargetInfo ) const { unsigned Value = getBinaryCodeForInstr ( Inst , Fixups , SubtargetInfo ) ; ++ MCNumEmitted ; for ( int i = ( 4 - 1 ) * 8 ; i >= 0 ; i -= 8 ) Ostream << static_cast < char > ( ( Value >> i ) & 0xff ) ; } </s>

Encode the given Inst to bytes and append to CB .


<s> const ARMBaseInstrInfo * getInstrInfo ( ) const override { return InstrInfo . get ( ) ; } </s>


<s> bool isEqualityCmpFoldedWithSignedCmp ( ) const override { return false ; } </s>

Return true if instruction generated for equality comparison is folded with instruction generated for signed comparison .


"frame pointer should not have been eliminated"


<s>
const
MCFixupKindInfo
&
SystemZMCAsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
SystemZ
::
NumTargetFixupKinds
]
=
{
{
"FK_390_PC16DBL"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"FK_390_PC32DBL"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"FK_390_TLS_CALL"
,
0
,
0
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> static void aarch64_disqualify_components ( sbitmap , edge , sbitmap , bool ) { } </s>


<s> static int ix86_function_regparm ( const_tree type , const_tree decl ) { tree attr ; int regparm ; unsigned int ccvt ; if ( TARGET_64BIT ) return ( ix86_function_type_abi ( type ) == SYSV_ABI ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX ) ; ccvt = ix86_get_callcvt ( type ) ; regparm = ix86_regparm ; if ( ( ccvt & IX86_CALLCVT_REGPARM ) != 0 ) { attr = lookup_attribute ( "regparm" , TYPE_ATTRIBUTES ( type ) ) ; if ( attr ) { regparm = TREE_INT_CST_LOW ( TREE_VALUE ( TREE_VALUE ( attr ) ) ) ; return regparm ; } } else if ( ( ccvt & IX86_CALLCVT_FASTCALL ) != 0 ) return 2 ; else if ( ( ccvt & IX86_CALLCVT_THISCALL ) != 0 ) return 1 ; if ( decl && TREE_CODE ( decl ) == FUNCTION_DECL ) { cgraph_node * target = cgraph_node :: get ( decl ) ; if ( target ) target = target -> function_symbol ( ) ; if ( target && opt_for_fn ( target -> decl , optimize ) && ! ( profile_flag && ! flag_fentry ) ) { cgraph_local_info * i = & target -> local ; if ( i && i -> local && i -> can_change_signature ) { int local_regparm , globals = 0 , regno ; for ( local_regparm = 0 ; local_regparm < REGPARM_MAX ; local_regparm ++ ) if ( fixed_regs [ local_regparm ] ) break ; if ( local_regparm == 3 && DECL_STATIC_CHAIN ( target -> decl ) ) local_regparm = 2 ; if ( local_regparm == 3 && flag_split_stack ) local_regparm = 2 ; for ( regno = AX_REG ; regno <= DI_REG ; regno ++ ) if ( fixed_regs [ regno ] ) globals ++ ; local_regparm = globals < local_regparm ? local_regparm - globals : 0 ; if ( local_regparm > regparm ) regparm = local_regparm ; } } } return regparm ; } </s>

Return the regparm value for a function with the indicated TYPE and DECL . DECL may be NULL when calling function indirectly or considering a libcall .


<s> bool haveRoundOpsF64 ( ) const { return CIInsts ; } </s>


<s> void MachineModulePass :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addPreserved < AAResultsWrapperPass > ( ) ; AU . addPreserved ( "scalar-evolution" ) ; AU . addPreserved ( "iv-users" ) ; AU . addPreserved ( "memdep" ) ; AU . addPreserved ( "live-values" ) ; AU . addPreserved ( "domtree" ) ; AU . addPreserved ( "domfrontier" ) ; AU . addPreserved ( "loops" ) ; AU . addPreserved ( "lda" ) ; ModulePass :: getAnalysisUsage ( AU ) ; } </s>

Patmos "scalar-evolution" "iv-users" "memdep" "live-values" "domtree" "domfrontier" "loops" "lda"


<s> virtual void EmitInstruction ( const MachineInstr * MI ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; printInstruction ( MI , OS ) ; WDC65816TargetStreamer & streamer = getTargetStreamer ( ) ; streamer . EmitInstruction ( OS . str ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; AArch64FunctionInfo * AFI = MF . getInfo < AArch64FunctionInfo > ( ) ; if ( AFI -> getNumLocalDynamicTLSAccesses ( ) < 2 ) { return false ; } MachineDominatorTree * DT = & getAnalysis < MachineDominatorTree > ( ) ; return VisitNode ( DT -> getRootNode ( ) , 0 ) ; } </s>

runOnMachineFunction - Emit the function body .


<s>
SDValue
VideocoreTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_VC4
)
;
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Arg
=
OutVals
[
i
]
;
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
AExt
:
Arg
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Arg
)
;
break
;
case
CCValAssign
::
ZExt
:
Arg
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Arg
)
;
break
;
case
CCValAssign
::
SExt
:
Arg
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Arg
)
;
break
;
}
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
Arg
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
VCISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
else
return
DAG
.
getNode
(
VCISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> unsigned ARM64TTI :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , OperandValueKind Opd1Info , OperandValueKind Opd2Info ) const { std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Ty ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return TargetTransformInfo :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info ) ; case ISD :: ADD : case ISD :: MUL : case ISD :: XOR : case ISD :: OR : case ISD :: AND : return 1 * LT . first ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> void AArch64TargetELFStreamer :: emitDirectiveVariantPCS ( MCSymbol * Symbol ) { getStreamer ( ) . getAssembler ( ) . registerSymbol ( * Symbol ) ; cast < MCSymbolELF > ( Symbol ) -> setOther ( ELF :: STO_AARCH64_VARIANT_PCS ) ; } </s>

Callback used to implement the .variant_pcs directive .


<s>
void
add
(
TransformItem
*
TI
)
{
assert
(
mayAdd
(
TI
)
)
;
if
(
Items
.
empty
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"new item\n"
)
;
}
else
{
LLVM_DEBUG
(
dbgs
(
)
<<
"merged to:\n"
;
Items
.
back
(
)
->
dump
(
)
)
;
}
Mask
|=
(
1
<<
TI
->
getIndex
(
)
)
;
Items
.
push_back
(
TI
)
;
}
</s>


<s> static bool c6x_pass_by_reference ( cumulative_args_t cum_v ATTRIBUTE_UNUSED , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { int size = - 1 ; if ( type ) size = int_size_in_bytes ( type ) ; else if ( mode != VOIDmode ) size = GET_MODE_SIZE ( mode ) ; return size > 2 * UNITS_PER_WORD || size == - 1 ; } </s>

Types larger than 64 bit , and variable sized types , are passed by reference . The callee must copy them ; see c6x_callee_copies .


<s>
void
MCS51MCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
unsigned
Size
=
Desc
.
getSize
(
)
;
assert
(
Size
>
0
&&
"Instruction size cannot be zero"
)
;
uint64_t
BinaryOpCode
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
emitInstruction
(
BinaryOpCode
,
Size
,
STI
,
OS
)
;
}
</s>


<s> bool has_merge_operand_p ( ) const override { if ( UNSPEC == UNSPEC_VSLIDEUP ) return false ; return true ; } </s>

We choose to return true by default since most of the intrinsics use has merge operand .


<s> bool useAA ( ) const override { return isCortexA53 ( ) ; } </s>

Enable use of alias analysis during code generation ( during MI scheduling , DAGCombine , etc . ) .


<s> void SystemZMCInstLower :: lower ( const MachineInstr * MI , MCInst & OutMI ) const { OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( unsigned I = 0 , E = MI -> getNumOperands ( ) ; I != E ; ++ I ) { const MachineOperand & MO = MI -> getOperand ( I ) ; if ( ! MO . isReg ( ) || ! MO . isImplicit ( ) ) OutMI . addOperand ( lowerOperand ( MO ) ) ; } } </s>


<s> static bool aarch64_evpc_sve_tbl ( struct expand_vec_perm_d * d ) { unsigned HOST_WIDE_INT nelt ; if ( ! d -> one_vector_p && ! d -> perm . length ( ) . is_constant ( & nelt ) ) return false ; if ( d -> testing_p ) return true ; machine_mode sel_mode = mode_for_int_vector ( d -> vmode ) . require ( ) ; rtx sel = vec_perm_indices_to_rtx ( sel_mode , d -> perm ) ; aarch64_expand_sve_vec_perm ( d -> target , d -> op0 , d -> op1 , sel ) ; return true ; } </s>

Try to implement D using an SVE TBL instruction .


<s>
bool
runOnMachineFunction
(
MachineFunction
&
MF
)
override
{
LLVM_DEBUG
(
dbgs
(
)
<<
"********** ISelDAGToDAG **********\n"
"********** Function: "
<<
MF
.
getName
(
)
<<
'\n'
)
;
ForCodeSize
=
MF
.
getFunction
(
)
.
hasOptSize
(
)
;
Subtarget
=
&
MF
.
getSubtarget
<
WebAssemblySubtarget
>
(
)
;
return
SelectionDAGISel
::
runOnMachineFunction
(
MF
)
;
}
</s>

WebAssembly
"********** ISelDAGToDAG **********\n"
"********** Function: "
WebAssembly


<s> bool MSP430FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , MutableArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; for ( const CalleeSavedInfo & I : CSI ) BuildMI ( MBB , MI , DL , TII . get ( MSP430 :: POP16r ) , I . getReg ( ) ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> void emitAssignment ( MCSymbol * S , const MCExpr * Value ) override { auto * Symbol = cast < MCSymbolELF > ( S ) ; if ( Value -> getKind ( ) != MCExpr :: SymbolRef ) return ; const auto & RhsSym = cast < MCSymbolELF > ( static_cast < const MCSymbolRefExpr * > ( Value ) -> getSymbol ( ) ) ; unsigned Other = Symbol -> getOther ( ) ; Other &= ~ ELF :: STO_PPC64_LOCAL_MASK ; Other |= RhsSym . getOther ( ) & ELF :: STO_PPC64_LOCAL_MASK ; Symbol -> setOther ( Other ) ; } </s>


<s> static void output_movsi ( rtx operands [ 2 ] ) { output_asm_insn ( singlemove_string ( operands ) , operands ) ; } </s>

Output the best assembler insn for moving operands [ 1 ] into operands [ 0 ] as a fullword .


<s> SDValue ARMTargetLowering :: PerformCMOVCombine ( SDNode * N , SelectionDAG & DAG ) const { SDValue Cmp = N -> getOperand ( 4 ) ; if ( Cmp . getOpcode ( ) != ARMISD :: CMPZ ) return SDValue ( ) ; EVT VT = N -> getValueType ( 0 ) ; SDLoc dl ( N ) ; SDValue LHS = Cmp . getOperand ( 0 ) ; SDValue RHS = Cmp . getOperand ( 1 ) ; SDValue FalseVal = N -> getOperand ( 0 ) ; SDValue TrueVal = N -> getOperand ( 1 ) ; SDValue ARMcc = N -> getOperand ( 2 ) ; ARMCC :: CondCodes CC = ( ARMCC :: CondCodes ) cast < ConstantSDNode > ( ARMcc ) -> getZExtValue ( ) ; if ( ! Subtarget -> isThumb1Only ( ) && Subtarget -> hasV6T2Ops ( ) ) { SDValue R = PerformCMOVToBFICombine ( N , DAG ) ; if ( R ) return R ; } SDValue Res ; if ( CC == ARMCC :: NE && FalseVal == RHS && FalseVal != LHS ) { Res = DAG . getNode ( ARMISD :: CMOV , dl , VT , LHS , TrueVal , ARMcc , N -> getOperand ( 3 ) , Cmp ) ; } else if ( CC == ARMCC :: EQ && TrueVal == RHS ) { SDValue ARMcc ; SDValue NewCmp = getARMCmp ( LHS , RHS , ISD :: SETNE , ARMcc , DAG , dl ) ; Res = DAG . getNode ( ARMISD :: CMOV , dl , VT , LHS , FalseVal , ARMcc , N -> getOperand ( 3 ) , NewCmp ) ; } if ( Res . getNode ( ) ) { APInt KnownZero , KnownOne ; DAG . computeKnownBits ( SDValue ( N , 0 ) , KnownZero , KnownOne ) ; if ( KnownZero == 0xfffffffe ) Res = DAG . getNode ( ISD :: AssertZext , dl , MVT :: i32 , Res , DAG . getValueType ( MVT :: i1 ) ) ; else if ( KnownZero == 0xffffff00 ) Res = DAG . getNode ( ISD :: AssertZext , dl , MVT :: i32 , Res , DAG . getValueType ( MVT :: i8 ) ) ; else if ( KnownZero == 0xffff0000 ) Res = DAG . getNode ( ISD :: AssertZext , dl , MVT :: i32 , Res , DAG . getValueType ( MVT :: i16 ) ) ; } return Res ; } </s>

PerformCMOVCombine - Target-specific DAG combining for ARMISD : :CMOV .


<s> void ix86_add_new_builtins ( HOST_WIDE_INT isa , HOST_WIDE_INT isa2 ) { isa &= ~ OPTION_MASK_ISA_64BIT ; if ( ( isa & deferred_isa_values ) == 0 && ( isa2 & deferred_isa_values2 ) == 0 && ( ( deferred_isa_values & OPTION_MASK_ISA_MMX ) == 0 || ! ( TARGET_64BIT && ( isa & OPTION_MASK_ISA_SSE2 ) != 0 ) ) ) return ; deferred_isa_values &= ~ isa ; deferred_isa_values2 &= ~ isa2 ; if ( TARGET_64BIT && ( isa & OPTION_MASK_ISA_SSE2 ) != 0 ) deferred_isa_values &= ~ OPTION_MASK_ISA_MMX ; int i ; tree saved_current_target_pragma = current_target_pragma ; current_target_pragma = NULL_TREE ; for ( i = 0 ; i < ( int ) IX86_BUILTIN_MAX ; i ++ ) { if ( ( ( ix86_builtins_isa [ i ] . isa & isa ) != 0 || ( ix86_builtins_isa [ i ] . isa2 & isa2 ) != 0 || ( ( ix86_builtins_isa [ i ] . isa & OPTION_MASK_ISA_MMX ) != 0 && TARGET_64BIT && ( isa & OPTION_MASK_ISA_SSE2 ) != 0 ) ) && ix86_builtins_isa [ i ] . set_and_not_built_p ) { tree decl , type ; ix86_builtins_isa [ i ] . set_and_not_built_p = false ; type = ix86_get_builtin_func_type ( ix86_builtins_isa [ i ] . tcode ) ; decl = add_builtin_function_ext_scope ( ix86_builtins_isa [ i ] . name , type , i , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ i ] = decl ; if ( ix86_builtins_isa [ i ] . const_p ) TREE_READONLY ( decl ) = 1 ; } } current_target_pragma = saved_current_target_pragma ; } </s>

Add any new builtin functions for a given ISA that may not have been declared . This saves a bit of space compared to adding all of the declarations to the tree , even if we did n't use them .


<s>
void
ARMAsmPrinter
::
PrintSymbolOperand
(
const
MachineOperand
&
MO
,
raw_ostream
&
O
)
{
assert
(
MO
.
isGlobal
(
)
&&
"caller should check MO.isGlobal"
)
;
unsigned
TF
=
MO
.
getTargetFlags
(
)
;
if
(
TF
&
ARMII
::
MO_LO16
)
O
<<
":lower16:"
;
else
if
(
TF
&
ARMII
::
MO_HI16
)
O
<<
":upper16:"
;
GetARMGVSymbol
(
MO
.
getGlobal
(
)
,
TF
)
->
print
(
O
,
MAI
)
;
printOffset
(
MO
.
getOffset
(
)
,
O
)
;
}
</s>


<s> bool avr_mem_flash_p ( rtx x ) { return ( MEM_P ( x ) && ! ADDR_SPACE_GENERIC_P ( MEM_ADDR_SPACE ( x ) ) ) ; } </s>

Return TRUE if X is a MEM rtx located in flash and FALSE , otherwise .


<s> void Thumb2InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( RC == & ARM :: GPRRegClass || RC == & ARM :: tGPRRegClass || RC == & ARM :: tcGPRRegClass || RC == & ARM :: rGPRRegClass || RC == & ARM :: GPRnopcRegClass ) { BuildMI ( MBB , I , DL , get ( ARM :: t2STRi12 ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; return ; } if ( ARM :: GPRPairRegClass . hasSubClassEq ( RC ) ) { if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( SrcReg , & ARM :: GPRPair_with_gsub_1_in_rGPRRegClass ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( ARM :: t2STRDi8 ) ) ; AddDReg ( MIB , SrcReg , ARM :: gsub_0 , getKillRegState ( isKill ) , TRI ) ; AddDReg ( MIB , SrcReg , ARM :: gsub_1 , 0 , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; return ; } ARMBaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg , isKill , FI , RC , TRI ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> rtx_insn * s390_load_got ( void ) { rtx_insn * insns ; rtx got_rtx = gen_rtx_REG ( Pmode , 12 ) ; start_sequence ( ) ; if ( TARGET_CPU_ZARCH ) { emit_move_insn ( got_rtx , s390_got_symbol ( ) ) ; } else { rtx offset ; offset = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , s390_got_symbol ( ) ) , UNSPEC_LTREL_OFFSET ) ; offset = gen_rtx_CONST ( Pmode , offset ) ; offset = force_const_mem ( Pmode , offset ) ; emit_move_insn ( got_rtx , offset ) ; offset = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , XEXP ( offset , 0 ) ) , UNSPEC_LTREL_BASE ) ; offset = gen_rtx_PLUS ( Pmode , got_rtx , offset ) ; emit_move_insn ( got_rtx , offset ) ; } insns = get_insns ( ) ; end_sequence ( ) ; return insns ; } </s>

Return insn sequence to load the GOT register .


<s> SDValue R600TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; R600MachineFunctionInfo * MFI = MF . getInfo < R600MachineFunctionInfo > ( ) ; SmallVector < ISD :: InputArg , 8 > LocalIns ; if ( AMDGPU :: isShader ( CallConv ) ) { AnalyzeFormalArguments ( CCInfo , Ins ) ; } else { analyzeFormalArgumentsCompute ( CCInfo , Ins ) ; } for ( unsigned i = 0 , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const ISD :: InputArg & In = Ins [ i ] ; EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector ( ) ) { MemVT = MemVT . getVectorElementType ( ) ; } if ( AMDGPU :: isShader ( CallConv ) ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & AMDGPU :: R600_Reg128RegClass ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , AMDGPUAS :: CONSTANT_BUFFER_0 ) ; ISD :: LoadExtType Ext = ISD :: NON_EXTLOAD ; if ( MemVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) { Ext = ISD :: SEXTLOAD ; } unsigned ValBase = ArgLocs [ In . getOrigArgIndex ( ) ] . getLocMemOffset ( ) ; unsigned PartOffset = VA . getLocMemOffset ( ) ; unsigned Offset = Subtarget -> getExplicitKernelArgOffset ( MF ) + VA . getLocMemOffset ( ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) , PartOffset - ValBase ) ; SDValue Arg = DAG . getLoad ( ISD :: UNINDEXED , Ext , VT , DL , Chain , DAG . getConstant ( Offset , DL , MVT :: i32 ) , DAG . getUNDEF ( MVT :: i32 ) , PtrInfo , MemVT , 4 , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; InVals . push_back ( Arg ) ; MFI -> setABIArgOffset ( Offset + MemVT . getStoreSize ( ) ) ; } return Chain ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s>
Value
*
HexagonTargetLowering
::
emitLoadLinked
(
IRBuilder
<
>
&
Builder
,
Value
*
Addr
,
AtomicOrdering
Ord
)
const
{
BasicBlock
*
BB
=
Builder
.
GetInsertBlock
(
)
;
Module
*
M
=
BB
->
getParent
(
)
->
getParent
(
)
;
auto
PT
=
cast
<
PointerType
>
(
Addr
->
getType
(
)
)
;
Type
*
Ty
=
PT
->
getElementType
(
)
;
unsigned
SZ
=
Ty
->
getPrimitiveSizeInBits
(
)
;
assert
(
(
SZ
==
32
||
SZ
==
64
)
&&
"Only 32/64-bit atomic loads supported"
)
;
Intrinsic
::
ID
IntID
=
(
SZ
==
32
)
Intrinsic
::
hexagon_L2_loadw_locked
:
Intrinsic
::
hexagon_L4_loadd_locked
;
PointerType
*
NewPtrTy
=
Builder
.
getIntNTy
(
SZ
)
->
getPointerTo
(
PT
->
getAddressSpace
(
)
)
;
Addr
=
Builder
.
CreateBitCast
(
Addr
,
NewPtrTy
)
;
Value
*
Fn
=
Intrinsic
::
getDeclaration
(
M
,
IntID
)
;
Value
*
Call
=
Builder
.
CreateCall
(
Fn
,
Addr
,
"larx"
)
;
return
Builder
.
CreateBitCast
(
Call
,
Ty
)
;
}
</s>

Perform a load-linked operation on Addr , returning a `` Value * '' with the corresponding pointee type .


"Relocation required in an instruction that we cannot encode!"

getMachineOpValue - Return binary encoding of operand .


<s> bool runOnFunction ( Function & F ) override { DominatorTree & DT = getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; AssumptionCache & AC = getAnalysis < AssumptionCacheTracker > ( ) . getAssumptionCache ( F ) ; return promoteMemoryToRegister ( F , DT , AC ) ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s>
StringRef
getPassName
(
)
const
override
{
return
"TPC Hardware Loops"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool hasMinSize ( ) const { return OptMinSize ; } </s>

Optimize this function for minimum size ( -Oz ) .


<s>
void
AArch64FrameLowering
::
emitEpilogue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
getLastNonDebugInstr
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
const
AArch64Subtarget
&
Subtarget
=
MF
.
getSubtarget
<
AArch64Subtarget
>
(
)
;
const
TargetInstrInfo
*
TII
=
Subtarget
.
getInstrInfo
(
)
;
DebugLoc
DL
;
bool
IsTailCallReturn
=
false
;
if
(
MBB
.
end
(
)
!=
MBBI
)
{
DL
=
MBBI
->
getDebugLoc
(
)
;
unsigned
RetOpcode
=
MBBI
->
getOpcode
(
)
;
IsTailCallReturn
=
RetOpcode
==
AArch64
::
TCRETURNdi
||
RetOpcode
==
AArch64
::
TCRETURNri
;
}
int
NumBytes
=
MFI
->
getStackSize
(
)
;
const
AArch64FunctionInfo
*
AFI
=
MF
.
getInfo
<
AArch64FunctionInfo
>
(
)
;
if
(
MF
.
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
;
uint64_t
ArgumentPopSize
=
0
;
if
(
IsTailCallReturn
)
{
MachineOperand
&
StackAdjust
=
MBBI
->
getOperand
(
1
)
;
ArgumentPopSize
=
StackAdjust
.
getImm
(
)
;
}
else
{
ArgumentPopSize
=
AFI
->
getArgumentStackToRestore
(
)
;
}
MachineBasicBlock
::
iterator
LastPopI
=
MBB
.
getFirstTerminator
(
)
;
MachineBasicBlock
::
iterator
Begin
=
MBB
.
begin
(
)
;
while
(
LastPopI
!=
Begin
)
{
LastPopI
;
if
(
!
LastPopI
->
getFlag
(
MachineInstr
::
FrameDestroy
)
)
{
++
LastPopI
;
break
;
}
}
NumBytes
-=
AFI
->
getCalleeSavedStackSize
(
)
;
assert
(
NumBytes
>=
0
&&
"Negative stack allocation size!?"
)
;
if
(
!
hasFP
(
MF
)
)
{
bool
RedZone
=
canUseRedZone
(
MF
)
;
if
(
RedZone
&&
ArgumentPopSize
==
0
)
return
;
bool
NoCalleeSaveRestore
=
AFI
->
getCalleeSavedStackSize
(
)
==
0
;
int
StackRestoreBytes
=
RedZone
0
:
NumBytes
;
if
(
NoCalleeSaveRestore
)
StackRestoreBytes
+=
ArgumentPopSize
;
emitFrameOffset
(
MBB
,
LastPopI
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
StackRestoreBytes
,
TII
,
MachineInstr
::
FrameDestroy
)
;
if
(
NoCalleeSaveRestore
||
ArgumentPopSize
==
0
)
return
;
NumBytes
=
0
;
}
if
(
NumBytes
||
MFI
->
hasVarSizedObjects
(
)
)
emitFrameOffset
(
MBB
,
LastPopI
,
DL
,
AArch64
::
SP
,
AArch64
::
FP
,
AFI
->
getCalleeSavedStackSize
(
)
+
16
,
TII
,
MachineInstr
::
FrameDestroy
)
;
if
(
ArgumentPopSize
)
emitFrameOffset
(
MBB
,
MBB
.
getFirstTerminator
(
)
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
ArgumentPopSize
,
TII
,
MachineInstr
::
FrameDestroy
)
;
}
</s>


<s> static bool arm_evpc_neon_vrev ( struct expand_vec_perm_d * d ) { unsigned int i , j , diff , nelt = d -> perm . length ( ) ; rtx ( * gen ) ( rtx , rtx ) ; if ( ! d -> one_vector_p ) return false ; diff = d -> perm [ 0 ] ; switch ( diff ) { case 7 : switch ( d -> vmode ) { case E_V16QImode : gen = gen_neon_vrev64v16qi ; break ; case E_V8QImode : gen = gen_neon_vrev64v8qi ; break ; default : return false ; } break ; case 3 : switch ( d -> vmode ) { case E_V16QImode : gen = gen_neon_vrev32v16qi ; break ; case E_V8QImode : gen = gen_neon_vrev32v8qi ; break ; case E_V8HImode : gen = gen_neon_vrev64v8hi ; break ; case E_V4HImode : gen = gen_neon_vrev64v4hi ; break ; case E_V8HFmode : gen = gen_neon_vrev64v8hf ; break ; case E_V4HFmode : gen = gen_neon_vrev64v4hf ; break ; default : return false ; } break ; case 1 : switch ( d -> vmode ) { case E_V16QImode : gen = gen_neon_vrev16v16qi ; break ; case E_V8QImode : gen = gen_neon_vrev16v8qi ; break ; case E_V8HImode : gen = gen_neon_vrev32v8hi ; break ; case E_V4HImode : gen = gen_neon_vrev32v4hi ; break ; case E_V4SImode : gen = gen_neon_vrev64v4si ; break ; case E_V2SImode : gen = gen_neon_vrev64v2si ; break ; case E_V4SFmode : gen = gen_neon_vrev64v4sf ; break ; case E_V2SFmode : gen = gen_neon_vrev64v2sf ; break ; default : return false ; } break ; default : return false ; } for ( i = 0 ; i < nelt ; i += diff + 1 ) for ( j = 0 ; j <= diff ; j += 1 ) { gcc_assert ( i + j < nelt ) ; if ( d -> perm [ i + j ] != i + diff - j ) return false ; } if ( d -> testing_p ) return true ; emit_insn ( gen ( d -> target , d -> op0 ) ) ; return true ; } </s>


<s> const Nios2InstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> static short find_insn_regmode_weight ( rtx insn , machine_mode mode ) { short reg_weight = 0 ; rtx x ; x = PATTERN ( insn ) ; reg_weight += find_set_regmode_weight ( x , mode ) ; if ( GET_CODE ( x ) == PARALLEL ) { int j ; for ( j = XVECLEN ( x , 0 ) - 1 ; j >= 0 ; j -- ) { x = XVECEXP ( PATTERN ( insn ) , 0 , j ) ; reg_weight += find_set_regmode_weight ( x , mode ) ; } } for ( x = REG_NOTES ( insn ) ; x ; x = XEXP ( x , 1 ) ) { if ( REG_NOTE_KIND ( x ) == REG_DEAD || REG_NOTE_KIND ( x ) == REG_UNUSED ) { rtx note = XEXP ( x , 0 ) ; if ( REG_P ( note ) && GET_MODE ( note ) == mode ) reg_weight -- ; } } return reg_weight ; } </s>


<s>
void
HexagonCommonGEP
::
collect
(
)
{
ValueVect
BO
;
getBlockTraversalOrder
(
Fn
->
begin
(
)
,
BO
)
;
ValueToNodeMap
NM
;
for
(
ValueVect
::
iterator
I
=
BO
.
begin
(
)
,
E
=
BO
.
end
(
)
;
I
!=
E
;
++
I
)
{
BasicBlock
*
B
=
cast
<
BasicBlock
>
(
*
I
)
;
for
(
BasicBlock
::
iterator
J
=
B
->
begin
(
)
,
F
=
B
->
end
(
)
;
J
!=
F
;
++
J
)
{
if
(
!
isa
<
GetElementPtrInst
>
(
J
)
)
continue
;
GetElementPtrInst
*
GepI
=
cast
<
GetElementPtrInst
>
(
J
)
;
if
(
isHandledGepForm
(
GepI
)
)
processGepInst
(
GepI
,
NM
)
;
}
}
DEBUG
(
dbgs
(
)
<<
"Gep nodes after initial collection:\n"
<<
Nodes
)
;
}
</s>

Analyze the given instruction MI and fill in the Uses , Defs and DeadDefs list based on the MachineOperand flags .

Hexagon
Hexagon
"Gep nodes after initial collection:\n"


<s> void RISCVPassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> unsigned AAPMachineFunctionInfo :: getGlobalBaseReg ( ) { if ( GlobalBaseReg ) return GlobalBaseReg ; return GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( & AAP :: GR64RegClass ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> rtx rs6000_longcall_ref ( rtx call_ref ) { const char * call_name ; tree node ; if ( GET_CODE ( call_ref ) != SYMBOL_REF ) return call_ref ; call_name = XSTR ( call_ref , 0 ) ; if ( * call_name == '.' ) { while ( * call_name == '.' ) call_name ++ ; node = get_identifier ( call_name ) ; call_ref = gen_rtx_SYMBOL_REF ( VOIDmode , IDENTIFIER_POINTER ( node ) ) ; } return force_reg ( Pmode , call_ref ) ; } </s>

Return a reference suitable for calling a function with the longcall attribute .


<s> bool ARMSubtarget :: enableMachineScheduler ( ) const { if ( isMClass ( ) && hasMinSize ( ) ) return false ; return useMachineScheduler ( ) ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


" was Pass-through, is now Dirty-out.\n"

runOnMachineFunction - Emit the function body .


<s>
unsigned
VEMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
assert
(
MO
.
isExpr
(
)
)
;
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
if
(
const
VEMCExpr
*
SExpr
=
dyn_cast
<
VEMCExpr
>
(
Expr
)
)
{
MCFixupKind
Kind
=
(
MCFixupKind
)
SExpr
->
getFixupKind
(
)
;
Fixups
.
push_back
(
MCFixup
::
create
(
0
,
Expr
,
Kind
)
)
;
return
0
;
}
int64_t
Res
;
if
(
Expr
->
evaluateAsAbsolute
(
Res
)
)
return
Res
;
llvm_unreachable
(
"Unhandled expression!"
)
;
return
0
;
}
</s>


<s> bool AMDGPUPrintfRuntimeBinding :: runOnModule ( Module & M ) { auto GetDT = [ this ] ( Function & F ) -> DominatorTree & { return this -> getAnalysis < DominatorTreeWrapperPass > ( F ) . getDomTree ( ) ; } ; auto GetTLI = [ this ] ( Function & F ) -> TargetLibraryInfo & { return this -> getAnalysis < TargetLibraryInfoWrapperPass > ( ) . getTLI ( F ) ; } ; return AMDGPUPrintfRuntimeBindingImpl ( GetDT , GetTLI ) . run ( M ) ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool X86AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < X86Subtarget > ( ) ; SMShadowTracker . startFunction ( MF ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Intrn = MF . getFunction ( ) -> hasInternalLinkage ( ) ; OutStreamer . BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer . EmitCOFFSymbolStorageClass ( Intrn ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer . EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer . EndCOFFSymbolDef ( ) ; } EmitFunctionHeader ( ) ; EmitFunctionBody ( ) ; return false ; } </s>


<s> bool ARMTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { EVT VT = getValueType ( DL , Ty , true ) ; if ( ! isLegalAddressImmediate ( AM . BaseOffs , VT , Subtarget ) ) return false ; if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( Subtarget -> isThumb1Only ( ) ) return false ; LLVM_FALLTHROUGH ; default : if ( AM . BaseOffs ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( Subtarget -> isThumb2 ( ) ) return isLegalT2ScaledAddressingMode ( AM , VT ) ; int Scale = AM . Scale ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case MVT :: i1 : case MVT :: i8 : case MVT :: i32 : if ( Scale < 0 ) Scale = - Scale ; if ( Scale == 1 ) return true ; return isPowerOf2_32 ( Scale & ~ 1 ) ; case MVT :: i16 : case MVT :: i64 : if ( ( ( unsigned ) AM . HasBaseReg + Scale ) <= 2 ) return true ; return false ; case MVT :: isVoid : if ( Scale & 1 ) return false ; return isPowerOf2_32 ( Scale ) ; } } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s>
void
XCoreRegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected"
)
;
MachineInstr
&
MI
=
*
II
;
MachineOperand
&
FrameOp
=
MI
.
getOperand
(
FIOperandNum
)
;
int
FrameIndex
=
FrameOp
.
getIndex
(
)
;
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
const
XCoreInstrInfo
&
TII
=
*
static_cast
<
const
XCoreInstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
const
XCoreFrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
int
Offset
=
MF
.
getFrameInfo
(
)
.
getObjectOffset
(
FrameIndex
)
;
int
StackSize
=
MF
.
getFrameInfo
(
)
.
getStackSize
(
)
;
LLVM_DEBUG
(
errs
(
)
<<
"\nFunction         : "
<<
MF
.
getName
(
)
<<
"\n"
)
;
LLVM_DEBUG
(
errs
(
)
<<
"<--------->\n"
)
;
LLVM_DEBUG
(
MI
.
print
(
errs
(
)
)
)
;
LLVM_DEBUG
(
errs
(
)
<<
"FrameIndex         : "
<<
FrameIndex
<<
"\n"
)
;
LLVM_DEBUG
(
errs
(
)
<<
"FrameOffset        : "
<<
Offset
<<
"\n"
)
;
LLVM_DEBUG
(
errs
(
)
<<
"StackSize          : "
<<
StackSize
<<
"\n"
)
;
Offset
+=
StackSize
;
Register
FrameReg
=
getFrameRegister
(
MF
)
;
if
(
MI
.
isDebugValue
(
)
)
{
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
)
;
return
;
}
Offset
+=
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
0
)
;
assert
(
Offset
%
4
==
0
&&
"Misaligned stack offset"
)
;
LLVM_DEBUG
(
errs
(
)
<<
"Offset             : "
<<
Offset
<<
"\n"
<<
"<--------->\n"
)
;
Offset
/=
4
;
Register
Reg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
assert
(
XCore
::
GRRegsRegClass
.
contains
(
Reg
)
&&
"Unexpected register operand"
)
;
if
(
TFI
->
hasFP
(
MF
)
)
{
if
(
isImmUs
(
Offset
)
)
InsertFPImmInst
(
II
,
TII
,
Reg
,
FrameReg
,
Offset
)
;
else
InsertFPConstInst
(
II
,
TII
,
Reg
,
FrameReg
,
Offset
,
RS
)
;
}
else
{
if
(
isImmU16
(
Offset
)
)
InsertSPImmInst
(
II
,
TII
,
Reg
,
Offset
)
;
else
InsertSPConstInst
(
II
,
TII
,
Reg
,
Offset
,
RS
)
;
}
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
MBB
.
erase
(
II
)
;
}
</s>

XCore
XCore
0
"Unexpected"
XCore
XCore
XCore
"\nFunction         : "
"\n"
"<--------->\n"
"FrameIndex         : "
"\n"
"FrameOffset        : "
"\n"
"StackSize          : "
"\n"
1
1
1
0
4
0
"Misaligned stack offset"
"Offset             : "
"\n"
"<--------->\n"
4
0
XCore::GRRegsRegClass
"Unexpected register operand"


<s> static unsigned int mips_arg_regno ( const struct mips_arg_info * info , bool hard_float_p ) { if ( ! info -> fpr_p || ! hard_float_p ) return GP_ARG_FIRST + info -> reg_offset ; else if ( mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info -> reg_offset > 0 ) return FP_ARG_FIRST + 2 ; else return FP_ARG_FIRST + info -> reg_offset ; } </s>

INFO describes a register argument that has the normal format for the argument 's mode . Return the register it uses , assuming that FPRs are available if HARD_FLOAT_P .


"value of -mfixed-range must have form REG1-REG2"

Parse the -mfixed-range= option string .


"Unexpected Kind in getPointerRegClass!"

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> const uint32_t * AArch64RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return CSR_AArch64_NoRegs_RegMask ; if ( CC == CallingConv :: AnyReg ) return CSR_AArch64_AllRegs_RegMask ; if ( CC == CallingConv :: CXX_FAST_TLS ) return CSR_AArch64_CXX_TLS_Darwin_RegMask ; if ( CC == CallingConv :: PreserveMost ) return CSR_AArch64_RT_MostRegs_RegMask ; else return CSR_AArch64_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> SparcSubtarget & SparcSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { UseSoftMulDiv = false ; IsV9 = false ; IsLeon = false ; V8DeprecatedInsts = false ; IsVIS = false ; HasHardQuad = false ; UsePopc = false ; UseSoftFloat = false ; HasNoFSMULD = false ; HasNoFMULS = false ; HasLeonCasa = false ; HasUmacSmac = false ; PerformSDIVReplace = false ; InsertNOPLoad = false ; FixAllFDIVSQRT = false ; DetectRoundChange = false ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? "v9" : "v8" ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( ! IsV9 ) UsePopc = false ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool PTXPassConfig :: addPreEmitPass ( ) { PM -> add ( createPTXMFInfoExtract ( getPTXTargetMachine ( ) , getOptLevel ( ) ) ) ; PM -> add ( createPTXFPRoundingModePass ( getPTXTargetMachine ( ) , getOptLevel ( ) ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> PPCTargetLowering :: ConstraintType PPCTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'b' : case 'r' : case 'f' : case 'v' : case 'y' : return C_RegisterClass ; case 'Z' : return C_Memory ; } } else if ( Constraint == "wc" ) { return C_RegisterClass ; } else if ( Constraint == "wa" || Constraint == "wd" || Constraint == "wf" || Constraint == "ws" ) { return C_RegisterClass ; } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .

PowerPC PPC PPC 1 0 "wc" "wa" "wd" "wf" "ws"


<s> static bool ix86_tieable_integer_mode_p ( enum machine_mode mode ) { switch ( mode ) { case HImode : case SImode : return true ; case QImode : return TARGET_64BIT || ! TARGET_PARTIAL_REG_STALL ; case DImode : return TARGET_64BIT ; default : return false ; } } </s>

A subroutine of ix86_modes_tieable_p . Return true if MODE is a tieable integer mode .


<s>
static
void
riscv_print_operand
(
FILE
*
file
,
rtx
op
,
int
letter
)
{
machine_mode
mode
=
GET_MODE
(
op
)
;
enum
rtx_code
code
=
GET_CODE
(
op
)
;
switch
(
letter
)
{
case
'h'
:
if
(
code
==
HIGH
)
op
=
XEXP
(
op
,
0
)
;
riscv_print_operand_reloc
(
file
,
op
,
true
)
;
break
;
case
'R'
:
riscv_print_operand_reloc
(
file
,
op
,
false
)
;
break
;
case
'C'
:
fputs
(
GET_RTX_NAME
(
code
)
,
file
)
;
break
;
case
'A'
:
if
(
riscv_memmodel_needs_amo_acquire
(
(
enum
memmodel
)
INTVAL
(
op
)
)
)
fputs
(
".aq"
,
file
)
;
break
;
case
'F'
:
if
(
riscv_memmodel_needs_release_fence
(
(
enum
memmodel
)
INTVAL
(
op
)
)
)
fputs
(
"fence iorw,ow; "
,
file
)
;
break
;
case
'i'
:
if
(
code
!=
REG
)
fputs
(
"i"
,
file
)
;
break
;
case
'S'
:
{
rtx
newop
=
GEN_INT
(
ctz_hwi
(
INTVAL
(
op
)
)
)
;
output_addr_const
(
file
,
newop
)
;
break
;
}
case
'T'
:
{
rtx
newop
=
GEN_INT
(
ctz_hwi
(
~
INTVAL
(
op
)
)
)
;
output_addr_const
(
file
,
newop
)
;
break
;
}
default
:
switch
(
code
)
{
case
REG
:
if
(
letter
&&
letter
!=
'z'
)
output_operand_lossage
(
"invalid use of '%%%c'"
,
letter
)
;
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
op
)
]
)
;
break
;
case
MEM
:
if
(
letter
&&
letter
!=
'z'
)
output_operand_lossage
(
"invalid use of '%%%c'"
,
letter
)
;
else
output_address
(
mode
,
XEXP
(
op
,
0
)
)
;
break
;
default
:
if
(
letter
==
'z'
&&
op
==
CONST0_RTX
(
GET_MODE
(
op
)
)
)
fputs
(
reg_names
[
GP_REG_FIRST
]
,
file
)
;
else
if
(
letter
&&
letter
!=
'z'
)
output_operand_lossage
(
"invalid use of '%%%c'"
,
letter
)
;
else
output_addr_const
(
file
,
riscv_strip_unspec_address
(
op
)
)
;
break
;
}
}
}
</s>

Implement TARGET_PRINT_OPERAND . The RISCV-specific operand codes are : ' h' Print the high-part relocation associated with OP , after stripping any outermost HIGH . ' R' Print the low-part relocation associated with OP . ' C' Print the integer branch condition for comparison OP . ' A' Print the atomic operation suffix for memory model OP . ' F' Print a FENCE if the memory model requires a release . ' z' Print x0 if OP is zero , otherwise print OP normally .

riscv
0
".aq"
"fence iorw,ow; "
"i"
"invalid use of '%%%c'"
"%s"
"invalid use of '%%%c'"
0
"invalid use of '%%%c'"


<s>
bool
FPS
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
bool
FPIsUsed
=
false
;
static_assert
(
X86
::
FP6
==
X86
::
FP0
+
6
,
"Register enums aren't sorted right!"
)
;
const
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
for
(
unsigned
i
=
0
;
i
<=
6
;
++
i
)
if
(
!
MRI
.
reg_nodbg_empty
(
X86
::
FP0
+
i
)
)
{
FPIsUsed
=
true
;
break
;
}
if
(
!
FPIsUsed
)
return
false
;
Bundles
=
&
getAnalysis
<
EdgeBundles
>
(
)
;
TII
=
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
bundleCFG
(
MF
)
;
StackTop
=
0
;
SmallPtrSet
<
MachineBasicBlock
*
,
8
>
Processed
;
MachineBasicBlock
*
Entry
=
MF
.
begin
(
)
;
bool
Changed
=
false
;
for
(
MachineBasicBlock
*
BB
:
depth_first_ext
(
Entry
,
Processed
)
)
Changed
|=
processBasicBlock
(
MF
,
*
BB
)
;
if
(
MF
.
size
(
)
!=
Processed
.
size
(
)
)
for
(
MachineFunction
::
iterator
BB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
BB
!=
E
;
++
BB
)
if
(
Processed
.
insert
(
BB
)
.
second
)
Changed
|=
processBasicBlock
(
MF
,
*
BB
)
;
LiveBundles
.
clear
(
)
;
return
Changed
;
}
</s>


<s> SDValue getUNDEF ( EVT VT ) const { return DAG . getUNDEF ( VT ) ; } </s>

Return an UNDEF node . UNDEF does not have a useful SDLoc .


<s> void HexagonInstPrinter :: printRegName ( raw_ostream & O , unsigned RegNo ) const { O << getRegisterName ( RegNo ) ; } </s>


<s> bool riscv_expand_conditional_move ( rtx dest , rtx op , rtx cons , rtx alt ) { machine_mode mode = GET_MODE ( dest ) ; rtx_code code = GET_CODE ( op ) ; rtx op0 = XEXP ( op , 0 ) ; rtx op1 = XEXP ( op , 1 ) ; if ( TARGET_XTHEADCONDMOV && GET_MODE_CLASS ( mode ) == MODE_INT && reg_or_0_operand ( cons , mode ) && reg_or_0_operand ( alt , mode ) && GET_MODE ( op ) == mode && GET_MODE ( op0 ) == mode && GET_MODE ( op1 ) == mode && ( code == EQ || code == NE ) ) { riscv_expand_conditional_move_onesided ( dest , cons , alt , code , op0 , op1 ) ; return true ; } else if ( TARGET_SFB_ALU && mode == word_mode ) { riscv_emit_int_compare ( & code , & op0 , & op1 ) ; rtx cond = gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 , op1 ) ; cons = force_reg ( GET_MODE ( dest ) , cons ) ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_IF_THEN_ELSE ( GET_MODE ( dest ) , cond , cons , alt ) ) ) ; return true ; } return false ; } </s>

Emit a cond move : If OP holds , move CONS to DEST ; else move ALT to DEST . Return 0 if expansion failed .


<s> Value * ARMTargetLowering :: emitLoadLinked ( IRBuilder < > & Builder , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Type * ValTy = cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ; bool IsAcquire = isAtLeastAcquire ( Ord ) ; if ( ValTy -> getPrimitiveSizeInBits ( ) == 64 ) { Intrinsic :: ID Int = IsAcquire ? Intrinsic :: arm_ldaexd : Intrinsic :: arm_ldrexd ; Function * Ldrex = llvm :: Intrinsic :: getDeclaration ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldrex , Addr , "lohi" ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Lo = Builder . CreateZExt ( Lo , ValTy , "lo64" ) ; Hi = Builder . CreateZExt ( Hi , ValTy , "hi64" ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , 32 ) ) , "val64" ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; Intrinsic :: ID Int = IsAcquire ? Intrinsic :: arm_ldaex : Intrinsic :: arm_ldrex ; Function * Ldrex = llvm :: Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateTruncOrBitCast ( Builder . CreateCall ( Ldrex , Addr ) , cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ) ; } </s>

Perform a load-linked operation on Addr , returning a `` Value * '' with the corresponding pointee type .


<s> bool legitimate_pic_operand_p ( rtx x ) { if ( pic_address_needs_scratch ( x ) ) return false ; if ( SPARC_SYMBOL_REF_TLS_P ( x ) || ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && SPARC_SYMBOL_REF_TLS_P ( XEXP ( XEXP ( x , 0 ) , 0 ) ) ) ) return false ; return true ; } </s>

Return true if OP is a legitimate general operand when generating PIC code . It is given that flag_pic is on and that OP satisfies CONSTANT_P or is a CONST_DOUBLE .


<s> int bfin_register_move_cost ( enum machine_mode mode ATTRIBUTE_UNUSED , enum reg_class class1 , enum reg_class class2 ) { if ( optimize_size ) return 2 ; if ( class1 == DREGS && class2 != DREGS ) return 2 * 2 ; return 2 ; } </s>

Return the cost of moving data from a register in class CLASS1 to one in class CLASS2 . A cost of 2 is the default .


<s> void RISCVFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterClass * RC = & RISCV :: GPRRegClass ; auto * RVFI = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; int64_t RVVStackSize = assignRVVStackObjectOffsets ( MFI ) ; RVFI -> setRVVStackSize ( RVVStackSize ) ; if ( ! isInt < 11 > ( MFI . estimateStackSize ( MF ) ) || RVVStackSize != 0 ) { int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RegScavFI ) ; if ( RVVStackSize != 0 ) { int RVVRegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RVVRegScavFI ) ; } } if ( MFI . getCalleeSavedInfo ( ) . empty ( ) || RVFI -> useSaveRestoreLibCalls ( MF ) ) { RVFI -> setCalleeSavedStackSize ( 0 ) ; return ; } unsigned Size = 0 ; for ( const auto & Info : MFI . getCalleeSavedInfo ( ) ) { int FrameIdx = Info . getFrameIdx ( ) ; if ( MFI . getStackID ( FrameIdx ) != TargetStackID :: Default ) continue ; Size += MFI . getObjectSize ( FrameIdx ) ; } RVFI -> setCalleeSavedStackSize ( Size ) ; if ( RVVStackSize && ! hasFP ( MF ) && Size % 8 != 0 ) { RVFI -> setRVVPadding ( getStackAlign ( ) . value ( ) ) ; } } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> SDValue AArch64TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: AND : return PerformANDCombine ( N , DCI ) ; case ISD :: OR : return PerformORCombine ( N , DCI , getSubtarget ( ) ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DCI , getSubtarget ( ) ) ; case ISD :: VSELECT : return PerformVSelectCombine ( N , DCI . DAG ) ; case ISD :: SIGN_EXTEND : return PerformSignExtendCombine ( N , DCI . DAG ) ; case ISD :: INTRINSIC_WO_CHAIN : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case AArch64ISD :: NEON_VDUPLANE : return CombineVLDDUP ( N , DCI ) ; case AArch64ISD :: NEON_LD2DUP : case AArch64ISD :: NEON_LD3DUP : case AArch64ISD :: NEON_LD4DUP : return CombineBaseUpdate ( N , DCI ) ; case ISD :: INTRINSIC_VOID : case ISD :: INTRINSIC_W_CHAIN : switch ( cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) -> getZExtValue ( ) ) { case Intrinsic :: arm_neon_vld1 : case Intrinsic :: arm_neon_vld2 : case Intrinsic :: arm_neon_vld3 : case Intrinsic :: arm_neon_vld4 : case Intrinsic :: arm_neon_vst1 : case Intrinsic :: arm_neon_vst2 : case Intrinsic :: arm_neon_vst3 : case Intrinsic :: arm_neon_vst4 : case Intrinsic :: arm_neon_vld2lane : case Intrinsic :: arm_neon_vld3lane : case Intrinsic :: arm_neon_vld4lane : case Intrinsic :: aarch64_neon_vld1x2 : case Intrinsic :: aarch64_neon_vld1x3 : case Intrinsic :: aarch64_neon_vld1x4 : case Intrinsic :: aarch64_neon_vst1x2 : case Intrinsic :: aarch64_neon_vst1x3 : case Intrinsic :: aarch64_neon_vst1x4 : case Intrinsic :: arm_neon_vst2lane : case Intrinsic :: arm_neon_vst3lane : case Intrinsic :: arm_neon_vst4lane : return CombineBaseUpdate ( N , DCI ) ; default : break ; } } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> void assignValueToAddress ( Register ValVReg , Register Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { if ( VA . getLocInfo ( ) == CCValAssign :: LocInfo :: AExt ) { Size = VA . getLocVT ( ) . getSizeInBits ( ) / 8 ; ValVReg = MIRBuilder . buildAnyExt ( LLT :: scalar ( Size * 8 ) , ValVReg ) . getReg ( 0 ) ; } MachineFunction & MF = MIRBuilder . getMF ( ) ; unsigned Align = inferAlignmentFromPtrInfo ( MF , MPO ) ; auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , Align ) ; MIRBuilder . buildStore ( ValVReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> static void mcore_print_operand_address ( FILE * stream , machine_mode , rtx x ) { switch ( GET_CODE ( x ) ) { case REG : fprintf ( stream , "(%s)" , reg_names [ REGNO ( x ) ] ) ; break ; case PLUS : { rtx base = XEXP ( x , 0 ) ; rtx index = XEXP ( x , 1 ) ; if ( GET_CODE ( base ) != REG ) { rtx temp = base ; base = index ; index = temp ; } switch ( GET_CODE ( index ) ) { case CONST_INT : fprintf ( stream , "(%s," HOST_WIDE_INT_PRINT_DEC ")" , reg_names [ REGNO ( base ) ] , INTVAL ( index ) ) ; break ; default : gcc_unreachable ( ) ; } } break ; default : output_addr_const ( stream , x ) ; break ; } } </s>

Print the operand address in x to the stream .


<s> bool aarch64_split_128bit_move_p ( rtx dst , rtx src ) { if ( FP_REGNUM_P ( REGNO ( dst ) ) ) return REG_P ( src ) && ! FP_REGNUM_P ( REGNO ( src ) ) ; return true ; } </s>

Return true if we should split a move from 128-bit value SRC to 128-bit register DEST .


<s>
Register
MipsTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
const
MachineFunction
&
MF
)
const
{
if
(
Subtarget
.
isGP64bit
(
)
)
{
Register
Reg
=
StringSwitch
<
Register
>
(
RegName
)
.
Case
(
"$28"
,
Mips
::
GP_64
)
.
Default
(
Register
(
)
)
;
if
(
Reg
)
return
Reg
;
}
else
{
Register
Reg
=
StringSwitch
<
Register
>
(
RegName
)
.
Case
(
"$28"
,
Mips
::
GP
)
.
Default
(
Register
(
)
)
;
if
(
Reg
)
return
Reg
;
}
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , LittleEndian ) , DL ( Subtarget . isTargetMachO ( ) ? "e-m:o-i64:64-i128:128-n32:64-S128" : ( LittleEndian ? "e-m:e-i64:64-i128:128-n32:64-S128" : "E-m:e-i64:64-i128:128-n32:64-S128" ) ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , FrameLowering ( * this , Subtarget ) , TSInfo ( * this ) { initAsmInfo ( ) ; } </s>


"max branch displacement must be enough to jump"

Determine if the branch target is in range .


<s> static bool r10k_safe_mem_expr_p ( tree expr , unsigned HOST_WIDE_INT offset ) { HOST_WIDE_INT bitoffset , bitsize ; tree inner , var_offset ; machine_mode mode ; int unsigned_p , reverse_p , volatile_p ; inner = get_inner_reference ( expr , & bitsize , & bitoffset , & var_offset , & mode , & unsigned_p , & reverse_p , & volatile_p , false ) ; if ( ! DECL_P ( inner ) || ! DECL_SIZE_UNIT ( inner ) || var_offset ) return false ; offset += bitoffset / BITS_PER_UNIT ; return offset < tree_to_uhwi ( DECL_SIZE_UNIT ( inner ) ) ; } </s>

Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is an in-range access to an automatic variable , or to an object with a link-time-constant address .


<s> enum reg_class xstormy16_preferred_reload_class ( rtx x , enum reg_class class ) { if ( class == GENERAL_REGS && GET_CODE ( x ) == MEM ) return EIGHT_REGS ; return class ; } </s>

Worker function for TARGET_PREFERRED_RELOAD_CLASS and TARGET_PREFERRED_OUTPUT_RELOAD_CLASS .


<s> SDValue R600TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; SmallVector < ISD :: InputArg , 8 > LocalIns ; getOriginalFunctionArgs ( DAG , DAG . getMachineFunction ( ) . getFunction ( ) , Ins , LocalIns ) ; AnalyzeFormalArguments ( CCInfo , LocalIns ) ; for ( unsigned i = 0 , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; EVT VT = Ins [ i ] . VT ; EVT MemVT = LocalIns [ i ] . VT ; PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , AMDGPUAS :: CONSTANT_BUFFER_0 ) ; SDValue Arg = DAG . getExtLoad ( ISD :: SEXTLOAD , DL , VT , Chain , DAG . getConstant ( 36 + VA . getLocMemOffset ( ) , MVT :: i32 ) , MachinePointerInfo ( UndefValue :: get ( PtrTy ) ) , MemVT , false , false , 4 ) ; InVals . push_back ( Arg ) ; } return Chain ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> LLT getStackValueStoreType ( const DataLayout & DL , const CCValAssign & VA , ISD :: ArgFlagsTy Flags ) const override { if ( Flags . isPointer ( ) ) return CallLowering :: ValueHandler :: getStackValueStoreType ( DL , VA , Flags ) ; return getStackValueStoreTypeHack ( VA ) ; } </s>

Return the in-memory size to write for the argument at VA .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , computeDefaultCPU ( TT , CPU ) , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveAArch64CodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } if ( getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) { this -> Options . TrapUnreachable = true ; } if ( this -> Options . TLSSize == 0 ) this -> Options . TLSSize = 24 ; if ( ( getCodeModel ( ) == CodeModel :: Small || getCodeModel ( ) == CodeModel :: Kernel ) && this -> Options . TLSSize > 32 ) this -> Options . TLSSize = 32 ; else if ( getCodeModel ( ) == CodeModel :: Tiny && this -> Options . TLSSize > 24 ) this -> Options . TLSSize = 24 ; if ( getOptLevel ( ) <= EnableGlobalISelAtO && TT . getArch ( ) != Triple :: aarch64_32 && ! ( getCodeModel ( ) == CodeModel :: Large && TT . isOSBinFormatMachO ( ) ) ) { setGlobalISel ( true ) ; setGlobalISelAbort ( GlobalISelAbortMode :: Disable ) ; } setMachineOutliner ( true ) ; setSupportsDefaultOutlining ( true ) ; setSupportsDebugEntryValues ( true ) ; } </s>


<s> bool SIInstrInfo :: isSchedulingBoundary ( const MachineInstr * MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( MI -> modifiesRegister ( AMDGPU :: EXEC , TRI ) ) return true ; return AMDGPUInstrInfo :: isSchedulingBoundary ( MI , MBB , MF ) ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> std :: unique_ptr < SICacheControl > SICacheControl :: create ( const GCNSubtarget & ST ) { GCNSubtarget :: Generation Generation = ST . getGeneration ( ) ; if ( Generation <= AMDGPUSubtarget :: SOUTHERN_ISLANDS ) return make_unique < SIGfx6CacheControl > ( ST ) ; if ( Generation < AMDGPUSubtarget :: GFX10 ) return make_unique < SIGfx7CacheControl > ( ST ) ; return make_unique < SIGfx10CacheControl > ( ST , ST . isCuModeEnabled ( ) ) ; } </s>


<s> void ix86_expand_floorceil ( rtx operand0 , rtx operand1 , bool do_floor ) { machine_mode mode = GET_MODE ( operand0 ) ; rtx xa , xi , TWO52 , tmp , one , res , mask ; rtx_code_label * label ; TWO52 = ix86_gen_TWO52 ( mode ) ; res = gen_reg_rtx ( mode ) ; emit_move_insn ( res , operand1 ) ; xa = ix86_expand_sse_fabs ( res , & mask ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; xi = gen_reg_rtx ( mode == DFmode ? DImode : SImode ) ; expand_fix ( xi , res , 0 ) ; expand_float ( xa , xi , 0 ) ; one = force_reg ( mode , const_double_from_real_value ( dconst1 , mode ) ) ; tmp = ix86_expand_sse_compare_mask ( UNGT , xa , res , ! do_floor ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , gen_rtx_AND ( mode , one , tmp ) ) ) ; tmp = expand_simple_binop ( mode , do_floor ? MINUS : PLUS , xa , tmp , NULL_RTX , 0 , OPTAB_DIRECT ) ; emit_move_insn ( res , tmp ) ; if ( HONOR_SIGNED_ZEROS ( mode ) ) ix86_sse_copysign_to_positive ( res , res , force_reg ( mode , operand1 ) , mask ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; emit_move_insn ( operand0 , res ) ; } </s>

Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing into OPERAND0 .


"Unpredicated consumer depending on predicated producer"

getMachineOpValue - Return binary encoding of operand .


"Not expecting bundled instructions here"

Replace a StackProbe inline-stub with the actual probe code inline .


<s> static unsigned long rs6000_arg_size ( machine_mode mode , const_tree type ) { unsigned long size ; if ( mode != BLKmode ) size = GET_MODE_SIZE ( mode ) ; else size = int_size_in_bytes ( type ) ; if ( TARGET_32BIT ) return ( size + 3 ) >> 2 ; else return ( size + 7 ) >> 3 ; } </s>

Compute the size ( in words ) of a function argument .


<s>
uint32_t
AArch64MCCodeEmitter
::
getBranchTargetOpValue
(
const
MCInst
&
MI
,
unsigned
OpIdx
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCOperand
&
MO
=
MI
.
getOperand
(
OpIdx
)
;
if
(
MO
.
isImm
(
)
)
return
MO
.
getImm
(
)
;
assert
(
MO
.
isExpr
(
)
&&
"Unexpected ADR target type!"
)
;
MCFixupKind
Kind
=
MI
.
getOpcode
(
)
==
AArch64
::
BL
MCFixupKind
(
AArch64
::
fixup_aarch64_pcrel_call26
)
:
MCFixupKind
(
AArch64
::
fixup_aarch64_pcrel_branch26
)
;
Fixups
.
push_back
(
MCFixup
::
create
(
0
,
MO
.
getExpr
(
)
,
Kind
,
MI
.
getLoc
(
)
)
)
;
++
MCNumFixups
;
return
0
;
}
</s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s>
void
AArch64TargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this"
)
;
case
ISD
::
FP_TO_UINT
:
case
ISD
::
FP_TO_SINT
:
assert
(
N
->
getValueType
(
0
)
==
MVT
::
i128
&&
"unexpected illegal conversion"
)
;
return
;
}
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> bool Inserter :: runOnMachineFunction ( MachineFunction & F ) { if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) return false ; bool Changed = false ; int FI = F . getInfo < MipsFunctionInfo > ( ) -> getGPFI ( ) ; for ( MachineFunction :: iterator MFI = F . begin ( ) , MFE = F . end ( ) ; MFI != MFE ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; MachineBasicBlock :: iterator I = MFI -> begin ( ) ; if ( MBB . isLandingPad ( ) ) { for ( ; I -> getOpcode ( ) != TargetOpcode :: EH_LABEL ; ++ I ) ; ++ I ; DebugLoc dl = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; BuildMI ( MBB , I , dl , TII -> get ( Mips :: LW ) , Mips :: GP ) . addFrameIndex ( FI ) . addImm ( 0 ) ; Changed = true ; } while ( I != MFI -> end ( ) ) { if ( I -> getOpcode ( ) != Mips :: JALR ) { ++ I ; continue ; } DebugLoc dl = I -> getDebugLoc ( ) ; BuildMI ( MBB , ++ I , dl , TII -> get ( Mips :: LW ) , Mips :: GP ) . addFrameIndex ( FI ) . addImm ( 0 ) ; Changed = true ; } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .

Mips Mips Mips::LW Mips::GP 0 Mips::JALR Mips::LW Mips::GP 0


<s> bool ARMPreAllocLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { TD = & Fn . getDataLayout ( ) ; STI = & static_cast < const ARMSubtarget & > ( Fn . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; MF = & Fn ; bool Modified = false ; for ( MachineBasicBlock & MFI : Fn ) Modified |= RescheduleLoadStoreInstrs ( & MFI ) ; return Modified ; } </s>


<s> SDNode * SITargetLowering :: PostISelFolding ( MachineSDNode * Node , SelectionDAG & DAG ) const { const SIInstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; unsigned Opcode = Node -> getMachineOpcode ( ) ; if ( TII -> isMIMG ( Opcode ) && ! TII -> get ( Opcode ) . mayStore ( ) ) adjustWritemask ( Node , DAG ) ; if ( Opcode == AMDGPU :: INSERT_SUBREG || Opcode == AMDGPU :: REG_SEQUENCE ) { legalizeTargetIndependentNode ( Node , DAG ) ; return Node ; } return Node ; } </s>

Fold the instructions after selecting them .


<s>
void
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
)
const
{
unsigned
NumBytes
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
.
TargetSize
/
8
;
Value
=
adjustFixupValue
(
Fixup
.
getKind
(
)
,
Value
)
;
if
(
!
Value
)
return
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


"64-bit code requested on a subtarget that doesn't support it!"

This constructor initializes the data members to match that of the specified triple .


<s>
bool
ARMBaseInstrInfo
::
getInsertSubregLikeInputs
(
const
MachineInstr
&
MI
,
unsigned
DefIdx
,
RegSubRegPair
&
BaseReg
,
RegSubRegPairAndIdx
&
InsertedReg
)
const
{
assert
(
DefIdx
<
MI
.
getDesc
(
)
.
getNumDefs
(
)
&&
"Invalid definition index"
)
;
assert
(
MI
.
isInsertSubregLike
(
)
&&
"Invalid kind of instruction"
)
;
switch
(
MI
.
getOpcode
(
)
)
{
case
ARM
::
VSETLNi32
:
const
MachineOperand
&
MOBaseReg
=
MI
.
getOperand
(
1
)
;
const
MachineOperand
&
MOInsertedReg
=
MI
.
getOperand
(
2
)
;
if
(
MOInsertedReg
.
isUndef
(
)
)
return
false
;
const
MachineOperand
&
MOIndex
=
MI
.
getOperand
(
3
)
;
BaseReg
.
Reg
=
MOBaseReg
.
getReg
(
)
;
BaseReg
.
SubReg
=
MOBaseReg
.
getSubReg
(
)
;
InsertedReg
.
Reg
=
MOInsertedReg
.
getReg
(
)
;
InsertedReg
.
SubReg
=
MOInsertedReg
.
getSubReg
(
)
;
InsertedReg
.
SubIdx
=
MOIndex
.
getImm
(
)
==
0
ARM
::
ssub_0
:
ARM
::
ssub_1
;
return
true
;
}
llvm_unreachable
(
"Target dependent opcode missing"
)
;
}
</s>

Target-dependent implementation of getInsertSubregInputs .


<s> MachineInstrBuilder emitInst ( unsigned Opc , unsigned DstReg ) { return BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DstReg ) ; } </s>

Callback used to implement the .inst directive .


<s> void AVRAsmPrinter :: emitInstruction ( const MachineInstr * MI ) { AVRMCInstLower MCInstLowering ( OutContext , * this ) ; MCInst I ; MCInstLowering . lowerInstruction ( * MI , I ) ; EmitToStreamer ( * OutStreamer , I ) ; } </s>

Targets should implement this to emit instructions .