<s> static void tilepro_asm_output_mi_thunk ( FILE * file , tree thunk_fndecl ATTRIBUTE_UNUSED , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { rtx this_rtx , funexp ; rtx_insn * insn ; reload_completed = 1 ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , 1 ) ; else this_rtx = gen_rtx_REG ( Pmode , 0 ) ; emit_insn ( gen_addsi3 ( this_rtx , this_rtx , GEN_INT ( delta ) ) ) ; if ( vcall_offset ) { rtx tmp ; tmp = gen_rtx_REG ( Pmode , 29 ) ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , this_rtx ) ) ; emit_insn ( gen_addsi3 ( tmp , tmp , GEN_INT ( vcall_offset ) ) ) ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , tmp ) ) ; emit_insn ( gen_addsi3 ( this_rtx , this_rtx , tmp ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = 1 ; } funexp = XEXP ( DECL_RTL ( function ) , 0 ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx ) ) ; SIBLING_CALL_P ( insn ) = 1 ; insn = get_insns ( ) ; shorten_branches ( insn ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; reload_completed = 0 ; } </s>


<s> void TPCAsmParser :: flushPendingInstructions ( MCStreamer & Out ) { if ( CurrentSlot != SlotParser :: Unknown ) outputBundle ( Out , SMLoc ( ) , true ) ; AC -> flushPendingInstructions ( Out , getSTI ( ) ) ; if ( TPCHeader ) { Out . PushSection ( ) ; MCSectionELF * MetadataSection = getContext ( ) . getELFSection ( BinaryTPCMetadataSectionName , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; MetadataSection -> getFragmentList ( ) . clear ( ) ; MCDataFragment * Fragment = new MCDataFragment ( MetadataSection ) ; const TPCMetadataSection & Header = TPCHeader . getValue ( ) ; std :: vector < uint8_t > BinaryValue = bianrySerializeTPCProgramHeader ( Header ) ; Fragment -> getContents ( ) . append ( BinaryValue . begin ( ) , BinaryValue . end ( ) ) ; Fragment -> setAlignToBundleEnd ( true ) ; Out . SwitchSection ( MetadataSection ) ; Out . PopSection ( ) ; } std :: string RootFileName = getContext ( ) . getMainFileName ( ) ; if ( ! RootFileName . empty ( ) ) { Out . PushSection ( ) ; MCSectionELF * KernelInfoSection = getContext ( ) . getELFSection ( KernelInfoSectionName , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; KernelInfoSection -> getFragmentList ( ) . clear ( ) ; MCDataFragment * Fragment = new MCDataFragment ( KernelInfoSection ) ; StringRef BareFileName = llvm :: sys :: path :: stem ( RootFileName ) ; std :: string KernelInfo = GenerateKernelInfo ( BareFileName ) ; Fragment -> getContents ( ) . append ( KernelInfo . begin ( ) , KernelInfo . end ( ) ) ; Fragment -> setAlignToBundleEnd ( true ) ; Out . SwitchSection ( KernelInfoSection ) ; Out . PopSection ( ) ; } if ( IndexMap ) { Out . PushSection ( ) ; MCSectionELF * IndexMapSection = getContext ( ) . getELFSection ( IndexMapSectionName , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; IndexMapSection -> getFragmentList ( ) . clear ( ) ; MCDataFragment * Fragment = new MCDataFragment ( IndexMapSection ) ; Fragment -> getContents ( ) . append ( IndexMap -> begin ( ) , IndexMap -> end ( ) ) ; Fragment -> setAlignToBundleEnd ( true ) ; Out . SwitchSection ( IndexMapSection ) ; Out . PopSection ( ) ; } } </s>

Ensure that all previously parsed instructions have been emitted to the output streamer , if the target does not emit them immediately .


<s> static rtx riscv_unspec_offset_high ( rtx temp , rtx addr , enum riscv_symbol_type symbol_type ) { addr = gen_rtx_HIGH ( Pmode , riscv_unspec_address ( addr , symbol_type ) ) ; return riscv_force_temporary ( temp , addr ) ; } </s>

If riscv_unspec_address ( ADDR , SYMBOL_TYPE ) is a 32-bit value , add the high part to BASE and return the result . Just return BASE otherwise . TEMP is as for riscv_force_temporary . The returned expression can be used as the first operand to a LO_SUM .


"Didn't find MI in its own basic block?"

getOffsetOf - Return the current offset of the specified machine instruction from the start of the function .


<s> bool AlphaFrameInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MFI -> hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> StringRef getPassName ( ) const override { return SYSTEMZ_EXPAND_PSEUDO_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> unsigned MipsRegisterInfo :: getRARegister ( ) const { return Mips :: RA ; } </s>

This method should return the register where the return address can be found .


<s> unsigned ARMBaseInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case ARM :: STRrs : case ARM :: t2STRs : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isReg ( ) && MI -> getOperand ( 3 ) . isImm ( ) && MI -> getOperand ( 2 ) . getReg ( ) == 0 && MI -> getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: STRi12 : case ARM :: t2STRi12 : case ARM :: tSpill : case ARM :: VSTRD : case ARM :: VSTRS : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VST1q64Pseudo : if ( MI -> getOperand ( 0 ) . isFI ( ) && MI -> getOperand ( 2 ) . getSubReg ( ) == 0 ) { FrameIndex = MI -> getOperand ( 0 ) . getIndex ( ) ; return MI -> getOperand ( 2 ) . getReg ( ) ; } break ; case ARM :: VSTMQIA : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> static bool isF128SoftLibCall ( const char * CallSym ) { const char * const LibCalls [ ] = { "__addtf3" , "__divtf3" , "__eqtf2" , "__extenddftf2" , "__extendsftf2" , "__fixtfdi" , "__fixtfsi" , "__fixtfti" , "__fixunstfdi" , "__fixunstfsi" , "__fixunstfti" , "__floatditf" , "__floatsitf" , "__floattitf" , "__floatunditf" , "__floatunsitf" , "__floatuntitf" , "__getf2" , "__gttf2" , "__letf2" , "__lttf2" , "__multf3" , "__netf2" , "__powitf2" , "__subtf3" , "__trunctfdf2" , "__trunctfsf2" , "__unordtf2" , "ceill" , "copysignl" , "cosl" , "exp2l" , "expl" , "floorl" , "fmal" , "fmodl" , "log10l" , "log2l" , "logl" , "nearbyintl" , "powl" , "rintl" , "sinl" , "sqrtl" , "truncl" } ; const char * const * End = LibCalls + array_lengthof ( LibCalls ) ; MipsTargetLowering :: LTStr Comp ; for ( const char * const * I = LibCalls ; I < End - 1 ; ++ I ) assert ( Comp ( * I , * ( I + 1 ) ) ) ; return std :: binary_search ( LibCalls , End , CallSym , Comp ) ; } </s>

This function returns true if CallSym is a long double emulation routine .


<s> SDValue AMDGPUTargetLowering :: getSqrtEstimate ( SDValue Operand , SelectionDAG & DAG , int Enabled , int & RefinementSteps , bool & UseOneConstNR , bool Reciprocal ) const { EVT VT = Operand . getValueType ( ) ; if ( VT == MVT :: f32 ) { RefinementSteps = 0 ; return DAG . getNode ( AMDGPUISD :: RSQ , SDLoc ( Operand ) , VT , Operand ) ; } return SDValue ( ) ; } </s>

Hooks for building estimates in place of slower divisions and square roots .


<s> bool RISCVDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { switch ( ConstraintID ) { case InlineAsm :: Constraint_i : case InlineAsm :: Constraint_m : OutOps . push_back ( Op ) ; return false ; default : break ; } return true ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> BitVector XCoreRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; Reserved . set ( XCore :: CP ) ; Reserved . set ( XCore :: DP ) ; Reserved . set ( XCore :: SP ) ; Reserved . set ( XCore :: LR ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( XCore :: R10 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .

XCore XCore XCore::CP XCore::DP XCore::SP XCore::LR XCore::R10


<s> const uint32_t * SystemZRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const SystemZSubtarget & Subtarget = MF . getSubtarget < SystemZSubtarget > ( ) ; if ( CC == CallingConv :: AnyReg ) return Subtarget . hasVector ( ) ? CSR_SystemZ_AllRegs_Vector_RegMask : CSR_SystemZ_AllRegs_RegMask ; if ( MF . getSubtarget ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_SystemZ_SwiftError_RegMask ; return CSR_SystemZ_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .

SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ


<s> static void aarch64_output_mi_thunk ( FILE * file , tree thunk ATTRIBUTE_UNUSED , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { int this_regno = R0_REGNUM ; rtx this_rtx , temp0 , temp1 , addr , funexp ; rtx_insn * insn ; reload_completed = 1 ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; this_rtx = gen_rtx_REG ( Pmode , this_regno ) ; temp0 = gen_rtx_REG ( Pmode , IP0_REGNUM ) ; temp1 = gen_rtx_REG ( Pmode , IP1_REGNUM ) ; if ( vcall_offset == 0 ) aarch64_add_offset ( Pmode , this_rtx , this_rtx , delta , temp1 , temp0 , false ) ; else { gcc_assert ( ( vcall_offset & ( POINTER_BYTES - 1 ) ) == 0 ) ; addr = this_rtx ; if ( delta != 0 ) { if ( delta >= - 256 && delta < 256 ) addr = gen_rtx_PRE_MODIFY ( Pmode , this_rtx , plus_constant ( Pmode , this_rtx , delta ) ) ; else aarch64_add_offset ( Pmode , this_rtx , this_rtx , delta , temp1 , temp0 , false ) ; } if ( Pmode == ptr_mode ) aarch64_emit_move ( temp0 , gen_rtx_MEM ( ptr_mode , addr ) ) ; else aarch64_emit_move ( temp0 , gen_rtx_ZERO_EXTEND ( Pmode , gen_rtx_MEM ( ptr_mode , addr ) ) ) ; if ( vcall_offset >= - 256 && vcall_offset < 4096 * POINTER_BYTES ) addr = plus_constant ( Pmode , temp0 , vcall_offset ) ; else { aarch64_internal_mov_immediate ( temp1 , GEN_INT ( vcall_offset ) , true , Pmode ) ; addr = gen_rtx_PLUS ( Pmode , temp0 , temp1 ) ; } if ( Pmode == ptr_mode ) aarch64_emit_move ( temp1 , gen_rtx_MEM ( ptr_mode , addr ) ) ; else aarch64_emit_move ( temp1 , gen_rtx_SIGN_EXTEND ( Pmode , gen_rtx_MEM ( ptr_mode , addr ) ) ) ; emit_insn ( gen_add2_insn ( this_rtx , temp1 ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = 1 ; } funexp = XEXP ( DECL_RTL ( function ) , 0 ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx , NULL_RTX ) ) ; SIBLING_CALL_P ( insn ) = 1 ; insn = get_insns ( ) ; shorten_branches ( insn ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; reload_completed = 0 ; } </s>

Output code to add DELTA to the first argument , and then jump to FUNCTION . Used for C++ multiple inheritance .


<s> AtomicExpansionKind shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const override { return AtomicExpansionKind :: LLSC ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> MCSymbol * WebAssemblyMCInstLower :: GetExternalSymbolSymbol ( const MachineOperand & MO ) const { const char * Name = MO . getSymbolName ( ) ; auto * WasmSym = cast < MCSymbolWasm > ( Printer . GetExternalSymbolSymbol ( Name ) ) ; const WebAssemblySubtarget & Subtarget = Printer . getSubtarget ( ) ; if ( strcmp ( Name , "__stack_pointer" ) == 0 || strcmp ( Name , "__tls_base" ) == 0 || strcmp ( Name , "__memory_base" ) == 0 || strcmp ( Name , "__table_base" ) == 0 || strcmp ( Name , "__tls_size" ) == 0 || strcmp ( Name , "__tls_align" ) == 0 ) { bool Mutable = strcmp ( Name , "__stack_pointer" ) == 0 || strcmp ( Name , "__tls_base" ) == 0 ; WasmSym -> setType ( wasm :: WASM_SYMBOL_TYPE_GLOBAL ) ; WasmSym -> setGlobalType ( wasm :: WasmGlobalType { uint8_t ( Subtarget . hasAddr64 ( ) ? wasm :: WASM_TYPE_I64 : wasm :: WASM_TYPE_I32 ) , Mutable } ) ; return WasmSym ; } SmallVector < wasm :: ValType , 4 > Returns ; SmallVector < wasm :: ValType , 4 > Params ; if ( strcmp ( Name , "__cpp_exception" ) == 0 ) { WasmSym -> setType ( wasm :: WASM_SYMBOL_TYPE_EVENT ) ; WasmSym -> setEventType ( { wasm :: WASM_EVENT_ATTRIBUTE_EXCEPTION , 0 } ) ; WasmSym -> setWeak ( true ) ; WasmSym -> setExternal ( true ) ; Params . push_back ( Subtarget . hasAddr64 ( ) ? wasm :: ValType :: I64 : wasm :: ValType :: I32 ) ; } else { WasmSym -> setType ( wasm :: WASM_SYMBOL_TYPE_FUNCTION ) ; getLibcallSignature ( Subtarget , Name , Returns , Params ) ; } auto Signature = make_unique < wasm :: WasmSignature > ( std :: move ( Returns ) , std :: move ( Params ) ) ; WasmSym -> setSignature ( Signature . get ( ) ) ; Printer . addSignature ( std :: move ( Signature ) ) ; return WasmSym ; } </s>

Return the MCSymbol for the specified ExternalSymbol .


<s> static bool mips_near_type_p ( const_tree type ) { return lookup_attribute ( "near" , TYPE_ATTRIBUTES ( type ) ) != NULL ; } </s>

Predicates to test for presence of `` near '' and `` far '' / '' long_call '' attributes on the given TYPE .


<s> bool PPCLowerMASSVEntries :: runOnModule ( Module & M ) { bool Changed = false ; auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return Changed ; auto & TM = TPC -> getTM < PPCTargetMachine > ( ) ; const PPCSubtarget * Subtarget ; for ( Function & Func : M ) { if ( ! Func . isDeclaration ( ) ) continue ; if ( ! isMASSVFunc ( Func . getName ( ) ) ) continue ; SmallVector < User * , 4 > MASSVUsers ( Func . users ( ) ) ; for ( auto * User : MASSVUsers ) { auto * CI = dyn_cast < CallInst > ( User ) ; if ( ! CI ) continue ; Subtarget = & TM . getSubtarget < PPCSubtarget > ( * CI -> getParent ( ) -> getParent ( ) ) ; Changed |= lowerMASSVCall ( CI , Func , M , Subtarget ) ; } } return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override { llvm_unreachable ( "unimplemented" ) ; } </s>

Similar to createMachineScheduler but used when postRA machine scheduling is enabled .


<s> void addDef ( long pos ) { defs . set ( pos ) ; } </s>

Add a virtual register definition operand .


<s>
static
void
visium_print_operand_address
(
FILE
*
file
,
machine_mode
mode
,
rtx
addr
)
{
switch
(
GET_CODE
(
addr
)
)
{
case
REG
:
case
SUBREG
:
fprintf
(
file
,
"(%s)"
,
reg_names
[
true_regnum
(
addr
)
]
)
;
break
;
case
PLUS
:
{
rtx
x
=
XEXP
(
addr
,
0
)
,
y
=
XEXP
(
addr
,
1
)
;
switch
(
GET_CODE
(
x
)
)
{
case
REG
:
case
SUBREG
:
if
(
CONST_INT_P
(
y
)
)
{
unsigned
int
regno
=
true_regnum
(
x
)
;
HOST_WIDE_INT
val
=
INTVAL
(
y
)
;
switch
(
mode
)
{
case
E_SImode
:
case
E_DImode
:
case
E_SFmode
:
case
E_DFmode
:
val
>>=
2
;
break
;
case
E_HImode
:
val
>>=
1
;
break
;
case
E_QImode
:
default
:
break
;
}
fprintf
(
file
,
HOST_WIDE_INT_PRINT_DEC
"(%s)"
,
val
,
reg_names
[
regno
]
)
;
}
else
fatal_insn
(
"illegal operand address (1)"
,
addr
)
;
break
;
default
:
if
(
CONSTANT_P
(
x
)
&&
CONSTANT_P
(
y
)
)
output_addr_const
(
file
,
addr
)
;
else
fatal_insn
(
"illegal operand address (2)"
,
addr
)
;
break
;
}
}
break
;
case
LABEL_REF
:
case
SYMBOL_REF
:
case
CONST_INT
:
case
CONST
:
output_addr_const
(
file
,
addr
)
;
break
;
case
NOTE
:
if
(
NOTE_KIND
(
addr
)
!=
NOTE_INSN_DELETED_LABEL
)
fatal_insn
(
"illegal operand address (3)"
,
addr
)
;
break
;
case
CODE_LABEL
:
asm_fprintf
(
file
,
"%LL%d"
,
CODE_LABEL_NUMBER
(
addr
)
)
;
break
;
default
:
fatal_insn
(
"illegal operand address (4)"
,
addr
)
;
break
;
}
}
</s>

Implement TARGET_PRINT_OPERAND_ADDRESS . Output to stdio stream FILE the assembler syntax for an instruction operand that is a memory reference whose address is ADDR .

visium
"(%s)"
0
1
2
1
"(%s)"
"illegal operand address (1)"
"illegal operand address (2)"
"illegal operand address (3)"
"%LL%d"
"illegal operand address (4)"


<s>
Register
LanaiTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
LLT
,
const
MachineFunction
&
)
const
{
Register
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"pc"
,
Lanai
::
PC
)
.
Case
(
"sp"
,
Lanai
::
SP
)
.
Case
(
"fp"
,
Lanai
::
FP
)
.
Case
(
"rr1"
,
Lanai
::
RR1
)
.
Case
(
"r10"
,
Lanai
::
R10
)
.
Case
(
"rr2"
,
Lanai
::
RR2
)
.
Case
(
"r11"
,
Lanai
::
R11
)
.
Case
(
"rca"
,
Lanai
::
RCA
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s>
static
std
::
string
getEdgeAttributes
(
NodeRef
,
ChildIteratorType
E
,
GraphType
*
)
{
int
EdgeVal
=
(
*
E
.
getCurrent
(
)
)
.
getValue
(
)
;
return
EdgeVal
>=
0
"label = "
+
std
::
to_string
(
EdgeVal
)
:
"color = red, style = \"dashed\""
;
}
</s>

If you want to override the dot attributes printed for a particular edge , override this method .


"density %d%%, cost %d exceeds threshold, penalizing "

Test for likely overcommitment of vector hardware resources . If a loop iteration is relatively large , and too large a percentage of instructions in the loop are vectorized , the cost model may not adequately reflect delays from unavailable vector resources . Penalize the loop body cost for this case .


<s> static void replace_constant_pool_ref ( rtx * x , rtx ref , rtx offset ) { int i , j ; const char * fmt ; gcc_assert ( * x != ref ) ; if ( GET_CODE ( * x ) == UNSPEC && XINT ( * x , 1 ) == UNSPEC_LTREF && XVECEXP ( * x , 0 , 0 ) == ref ) { * x = gen_rtx_PLUS ( Pmode , XVECEXP ( * x , 0 , 1 ) , offset ) ; return ; } if ( GET_CODE ( * x ) == PLUS && GET_CODE ( XEXP ( * x , 1 ) ) == CONST_INT && GET_CODE ( XEXP ( * x , 0 ) ) == UNSPEC && XINT ( XEXP ( * x , 0 ) , 1 ) == UNSPEC_LTREF && XVECEXP ( XEXP ( * x , 0 ) , 0 , 0 ) == ref ) { rtx addr = gen_rtx_PLUS ( Pmode , XVECEXP ( XEXP ( * x , 0 ) , 0 , 1 ) , offset ) ; * x = plus_constant ( addr , INTVAL ( XEXP ( * x , 1 ) ) ) ; return ; } fmt = GET_RTX_FORMAT ( GET_CODE ( * x ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( * x ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'e' ) { replace_constant_pool_ref ( & XEXP ( * x , i ) , ref , offset ) ; } else if ( fmt [ i ] == 'E' ) { for ( j = 0 ; j < XVECLEN ( * x , i ) ; j ++ ) replace_constant_pool_ref ( & XVECEXP ( * x , i , j ) , ref , offset ) ; } } } </s>

Replace every reference to the annotated literal pool symbol REF in X by its base plus OFFSET .


<s> static bool branch_to_delay_slot_p ( rtx_insn * insn ) { rtx_insn * jump_insn ; if ( dbr_sequence_length ( ) ) return FALSE ; jump_insn = next_active_insn ( JUMP_LABEL_AS_INSN ( insn ) ) ; while ( insn ) { insn = next_active_insn ( insn ) ; if ( jump_insn == insn ) return TRUE ; if ( ! insn || GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT || asm_noperands ( PATTERN ( insn ) ) >= 0 || get_attr_length ( insn ) > 0 ) break ; } return FALSE ; } </s>

Return TRUE if INSN , a jump insn , has an unfilled delay slot and it branches into the delay slot . Otherwise , return FALSE .


<s> static int mips_address_cost ( rtx addr ) { return mips_address_insns ( addr , SImode ) ; } </s>

Provide the costs of an addressing mode that contains ADDR . If ADDR is not a valid address , its cost is irrelevant .


<s> bool GCNTTIImpl :: getTgtMemIntrinsic ( IntrinsicInst * Inst , MemIntrinsicInfo & Info ) const { switch ( Inst -> getIntrinsicID ( ) ) { case Intrinsic :: amdgcn_atomic_inc : case Intrinsic :: amdgcn_atomic_dec : case Intrinsic :: amdgcn_ds_fadd : case Intrinsic :: amdgcn_ds_fmin : case Intrinsic :: amdgcn_ds_fmax : { auto * Ordering = dyn_cast < ConstantInt > ( Inst -> getArgOperand ( 2 ) ) ; auto * Volatile = dyn_cast < ConstantInt > ( Inst -> getArgOperand ( 4 ) ) ; if ( ! Ordering || ! Volatile ) return false ; unsigned OrderingVal = Ordering -> getZExtValue ( ) ; if ( OrderingVal > static_cast < unsigned > ( AtomicOrdering :: SequentiallyConsistent ) ) return false ; Info . PtrVal = Inst -> getArgOperand ( 0 ) ; Info . Ordering = static_cast < AtomicOrdering > ( OrderingVal ) ; Info . ReadMem = true ; Info . WriteMem = true ; Info . IsVolatile = ! Volatile -> isNullValue ( ) ; return true ; } default : return false ; } } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> static bool csky_legitimate_constant_p ( machine_mode mode , rtx x ) { return ( ! csky_cannot_force_const_mem ( mode , x ) && CONSTANT_P ( x ) ) ; } </s>

Implement TARGET_LEGITIMATE_CONSTANT_P . Returns nonzero if the constant value X is a legitimate general operand . It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE .


<s> MachineBasicBlock * mprocTargetLowering :: EmitInstrWithCustomInserter ( MachineInstr * MI , MachineBasicBlock * BB ) const { } </s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


"MMIX Internal: This is not a constant:"

Return the bit-value for a const_int or const_double .


<s> bool AMDGPUAAResult :: pointsToConstantMemory ( const MemoryLocation & Loc , AAQueryInfo & AAQI , bool OrLocal ) { unsigned AS = Loc . Ptr -> getType ( ) -> getPointerAddressSpace ( ) ; if ( AS == AMDGPUAS :: CONSTANT_ADDRESS || AS == AMDGPUAS :: CONSTANT_ADDRESS_32BIT ) return true ; const Value * Base = getUnderlyingObject ( Loc . Ptr ) ; AS = Base -> getType ( ) -> getPointerAddressSpace ( ) ; if ( AS == AMDGPUAS :: CONSTANT_ADDRESS || AS == AMDGPUAS :: CONSTANT_ADDRESS_32BIT ) return true ; if ( const GlobalVariable * GV = dyn_cast < GlobalVariable > ( Base ) ) { if ( GV -> isConstant ( ) ) return true ; } else if ( const Argument * Arg = dyn_cast < Argument > ( Base ) ) { const Function * F = Arg -> getParent ( ) ; switch ( F -> getCallingConv ( ) ) { default : return AAResultBase :: pointsToConstantMemory ( Loc , AAQI , OrLocal ) ; case CallingConv :: AMDGPU_LS : case CallingConv :: AMDGPU_HS : case CallingConv :: AMDGPU_ES : case CallingConv :: AMDGPU_GS : case CallingConv :: AMDGPU_VS : case CallingConv :: AMDGPU_PS : case CallingConv :: AMDGPU_CS : case CallingConv :: AMDGPU_KERNEL : case CallingConv :: SPIR_KERNEL : break ; } unsigned ArgNo = Arg -> getArgNo ( ) ; if ( F -> hasParamAttribute ( ArgNo , Attribute :: NoAlias ) && ( F -> hasParamAttribute ( ArgNo , Attribute :: ReadNone ) || F -> hasParamAttribute ( ArgNo , Attribute :: ReadOnly ) ) ) { return true ; } } return AAResultBase :: pointsToConstantMemory ( Loc , AAQI , OrLocal ) ; } </s>

A convenience wrapper around the primary pointsToConstantMemory interface .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU


<s> const MCSymbolRefExpr * getSymbolExpr ( ) const { return SymExpr ; } </s>

getOpcode - Get the kind of this expression .


<s> static void pru_compute_frame_layout ( void ) { int regno ; HARD_REG_SET * save_mask ; int total_size ; int var_size ; int out_args_size ; int save_reg_size ; gcc_assert ( ! cfun -> machine -> initialized ) ; save_mask = & cfun -> machine -> save_mask ; CLEAR_HARD_REG_SET ( * save_mask ) ; var_size = PRU_STACK_ALIGN ( ( HOST_WIDE_INT ) get_frame_size ( ) ) ; out_args_size = PRU_STACK_ALIGN ( ( HOST_WIDE_INT ) crtl -> outgoing_args_size ) ; total_size = var_size + out_args_size ; save_reg_size = 0 ; for ( regno = 0 ; regno <= LAST_GP_REGNUM ; regno ++ ) if ( prologue_saved_reg_p ( regno ) ) { SET_HARD_REG_BIT ( * save_mask , regno ) ; save_reg_size += 1 ; } save_reg_size = PRU_STACK_ALIGN ( save_reg_size ) ; total_size += save_reg_size ; total_size += PRU_STACK_ALIGN ( crtl -> args . pretend_args_size ) ; cfun -> machine -> total_size = total_size ; cfun -> machine -> var_size = var_size ; cfun -> machine -> out_args_size = out_args_size ; cfun -> machine -> save_reg_size = save_reg_size ; cfun -> machine -> initialized = reload_completed ; cfun -> machine -> save_regs_offset = out_args_size + var_size ; } </s>


<s>
const
MCPhysReg
*
RISCVRegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
auto
&
Subtarget
=
MF
->
getSubtarget
<
RISCVSubtarget
>
(
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_NoRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
hasFnAttribute
(
"interrupt"
)
)
{
if
(
Subtarget
.
hasStdExtD
(
)
)
return
Subtarget
.
hasCheri
(
)
CSR_XLEN_CLEN_F64_Interrupt_SaveList
:
CSR_XLEN_F64_Interrupt_SaveList
;
if
(
Subtarget
.
hasStdExtF
(
)
)
return
Subtarget
.
hasCheri
(
)
CSR_XLEN_CLEN_F32_Interrupt_SaveList
:
CSR_XLEN_F32_Interrupt_SaveList
;
return
Subtarget
.
hasCheri
(
)
CSR_XLEN_CLEN_Interrupt_SaveList
:
CSR_Interrupt_SaveList
;
}
switch
(
Subtarget
.
getTargetABI
(
)
)
{
default
:
llvm_unreachable
(
"Unrecognized ABI"
)
;
case
RISCVABI
::
ABI_ILP32
:
case
RISCVABI
::
ABI_LP64
:
return
CSR_ILP32_LP64_SaveList
;
case
RISCVABI
::
ABI_IL32PC64
:
case
RISCVABI
::
ABI_L64PC128
:
return
CSR_IL32PC64_L64PC128_SaveList
;
case
RISCVABI
::
ABI_ILP32F
:
case
RISCVABI
::
ABI_LP64F
:
return
CSR_ILP32F_LP64F_SaveList
;
case
RISCVABI
::
ABI_IL32PC64F
:
case
RISCVABI
::
ABI_L64PC128F
:
return
CSR_IL32PC64F_L64PC128F_SaveList
;
case
RISCVABI
::
ABI_ILP32D
:
case
RISCVABI
::
ABI_LP64D
:
return
CSR_ILP32D_LP64D_SaveList
;
case
RISCVABI
::
ABI_IL32PC64D
:
case
RISCVABI
::
ABI_L64PC128D
:
return
CSR_IL32PC64D_L64PC128D_SaveList
;
}
}
</s>


<s> BlockSet & getBlocks ( ) { return Blocks ; } </s>

Get a list of the basic blocks which make up this loop .


<s> static void tilegx_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int byte_size = arg . promoted_size_in_bytes ( ) ; int word_size = ( byte_size + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; bool doubleword_aligned_p ; doubleword_aligned_p = tilegx_function_arg_boundary ( arg . mode , arg . type ) > BITS_PER_WORD ; if ( doubleword_aligned_p ) * cum += * cum & 1 ; if ( * cum < TILEGX_NUM_ARG_REGS && * cum + word_size > TILEGX_NUM_ARG_REGS ) * cum = TILEGX_NUM_ARG_REGS ; * cum += word_size ; } </s>


"Invalid opcode for custom legalization."

Called for instructions with the Custom LegalizationAction .


<s> rtx csky_return_addr ( int count , rtx frame ATTRIBUTE_UNUSED ) { if ( count != 0 ) return NULL_RTX ; return get_hard_reg_initial_val ( Pmode , CSKY_LR_REGNUM ) ; } </s>

Return an RTX indicating where the return address to the calling function can be found .


<s> bool SparcAsmPrinter :: isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { if ( MBB -> isLandingPad ( ) || MBB -> pred_empty ( ) ) return false ; MachineBasicBlock :: const_pred_iterator PI = MBB -> pred_begin ( ) , PI2 = PI ; ++ PI2 ; if ( PI2 != MBB -> pred_end ( ) ) return false ; const MachineBasicBlock * Pred = * PI ; if ( ! Pred -> isLayoutSuccessor ( MBB ) ) return false ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> isTerminator ( ) ) ; return I == Pred -> end ( ) || ! I -> isBarrier ( ) ; } </s>

isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


<s> void aarch64_init_fcmla_laneq_builtins ( void ) { unsigned int i = 0 ; for ( i = 0 ; i < ARRAY_SIZE ( aarch64_fcmla_lane_builtin_data ) ; ++ i ) { aarch64_fcmla_laneq_builtin_datum * d = & aarch64_fcmla_lane_builtin_data [ i ] ; tree argtype = aarch64_lookup_simd_builtin_type ( d -> mode , qualifier_none ) ; machine_mode quadmode = GET_MODE_2XWIDER_MODE ( d -> mode ) . require ( ) ; tree quadtype = aarch64_lookup_simd_builtin_type ( quadmode , qualifier_none ) ; tree lanetype = aarch64_simd_builtin_std_type ( SImode , qualifier_lane_pair_index ) ; tree ftype = build_function_type_list ( argtype , argtype , argtype , quadtype , lanetype , NULL_TREE ) ; tree fndecl = add_builtin_function ( d -> name , ftype , d -> fcode , BUILT_IN_MD , NULL , NULL_TREE ) ; aarch64_builtin_decls [ d -> fcode ] = fndecl ; } } </s>

Due to the architecture not providing lane variant of the lane instructions for fcmla we ca n't use the standard simd builtin expansion code , but we still want the majority of the validation that would normally be done .


"Can't return value from vararg function in memory"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s>
void
XCoreFrameLowering
::
processFunctionBeforeFrameFinalized
(
MachineFunction
&
MF
,
RegScavenger
*
RS
)
const
{
assert
(
RS
&&
"requiresRegisterScavenging failed"
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
const
TargetRegisterClass
*
RC
=
&
XCore
::
GRRegsRegClass
;
XCoreFunctionInfo
*
XFI
=
MF
.
getInfo
<
XCoreFunctionInfo
>
(
)
;
if
(
XFI
->
isLargeFrame
(
MF
)
||
hasFP
(
MF
)
)
RS
->
addScavengingFrameIndex
(
MFI
->
CreateStackObject
(
RC
->
getSize
(
)
,
RC
->
getAlignment
(
)
,
false
)
)
;
if
(
XFI
->
isLargeFrame
(
MF
)
&&
!
hasFP
(
MF
)
)
RS
->
addScavengingFrameIndex
(
MFI
->
CreateStackObject
(
RC
->
getSize
(
)
,
RC
->
getAlignment
(
)
,
false
)
)
;
}
</s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .

XCore
XCore
"requiresRegisterScavenging failed"
XCore::GRRegsRegClass
XCore
XCore


<s> static bool aarch64_output_addr_const_extra ( FILE * file , rtx x ) { if ( GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNSPEC_SALT_ADDR ) { output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; return true ; } return false ; } </s>


<s> static bool sh_can_follow_jump ( const rtx_insn * branch1 , const rtx_insn * branch2 ) { if ( TARGET_SH1 && flag_reorder_blocks_and_partition && simplejump_p ( branch2 ) && CROSSING_JUMP_P ( branch2 ) ) return false ; if ( flag_expensive_optimizations && simplejump_p ( branch2 ) ) { rtx dest = XEXP ( SET_SRC ( single_set ( branch2 ) ) , 0 ) ; rtx_insn * insn ; int distance ; for ( distance = 0 , insn = NEXT_INSN ( branch1 ) ; insn && distance < 256 ; insn = PREV_INSN ( insn ) ) { if ( insn == dest ) return true ; else distance += get_attr_length ( insn ) ; } for ( distance = 0 , insn = NEXT_INSN ( branch1 ) ; insn && distance < 256 ; insn = NEXT_INSN ( insn ) ) { if ( insn == dest ) return true ; else distance += get_attr_length ( insn ) ; } } return false ; } </s>

Return true if it 's possible to redirect BRANCH1 to the destination of an unconditional jump BRANCH2 . We only want to do this if the resulting branch will have a short displacement .


<s> int lm32_can_use_return ( void ) { if ( ! reload_completed ) return 0 ; if ( df_regs_ever_live_p ( RA_REGNUM ) || crtl -> profile ) return 0 ; if ( lm32_compute_frame_size ( get_frame_size ( ) ) != 0 ) return 0 ; return 1 ; } </s>

Return nonzero if this function is known to have a null epilogue . This allows the optimizer to omit jumps to jumps if no stack was created .


<s> static const char * gen_prefix ( tree decl ) { if ( DECL_ONE_ONLY ( decl ) ) return NULL ; if ( has_attr ( "section" , decl ) ) return NULL ; if ( has_attr ( ATTR_LOWER , decl ) ) return lower_prefix ; if ( ! msp430x ) return NULL ; if ( has_attr ( ATTR_UPPER , decl ) ) return upper_prefix ; if ( has_attr ( ATTR_EITHER , decl ) ) return either_prefix ; if ( TREE_CODE ( decl ) == FUNCTION_DECL ) { if ( msp430_code_region == MSP430_REGION_LOWER ) return lower_prefix ; if ( msp430_code_region == MSP430_REGION_UPPER ) return upper_prefix ; if ( msp430_code_region == MSP430_REGION_EITHER ) return either_prefix ; } else { if ( msp430_data_region == MSP430_REGION_LOWER ) return lower_prefix ; if ( msp430_data_region == MSP430_REGION_UPPER ) return upper_prefix ; if ( msp430_data_region == MSP430_REGION_EITHER ) return either_prefix ; } return NULL ; } </s>

Generate a prefix for a section name , based upon the region into which the object should be placed .


<s> void clear ( ) { Chain . clear ( ) ; } </s>


<s> static unsigned int insn_is_load_p ( rtx insn ) { rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) == SET ) { if ( MEM_P ( SET_SRC ( body ) ) ) return 1 ; if ( GET_CODE ( SET_SRC ( body ) ) == VEC_SELECT && MEM_P ( XEXP ( SET_SRC ( body ) , 0 ) ) ) return 1 ; if ( pattern_is_rotate64 ( body ) && MEM_P ( XEXP ( SET_SRC ( body ) , 0 ) ) ) return 1 ; return 0 ; } if ( GET_CODE ( body ) != PARALLEL ) return 0 ; rtx set = XVECEXP ( body , 0 , 0 ) ; if ( GET_CODE ( set ) == SET && MEM_P ( SET_SRC ( set ) ) ) return 1 ; return 0 ; } </s>

Return 1 iff INSN is a load insn , including permuting loads that represent an lvxd2x instruction ; else return 0 .


<s>
void
mips_output_external
(
FILE
*
file
,
tree
decl
,
const
char
*
name
)
{
default_elf_asm_output_external
(
file
,
decl
,
name
)
;
if
(
TREE_SYMBOL_REFERENCED
(
DECL_ASSEMBLER_NAME
(
decl
)
)
)
{
if
(
!
TARGET_EXPLICIT_RELOCS
&&
mips_in_small_data_p
(
decl
)
)
{
fputs
(
"\t.extern\t"
,
file
)
;
assemble_name
(
file
,
name
)
;
fprintf
(
file
,
", "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
int_size_in_bytes
(
TREE_TYPE
(
decl
)
)
)
;
}
}
}
</s>

When using assembler macros , keep track of all of small-data externs so that mips_file_end can emit the appropriate declarations for them . In most cases it would be safe ( though pointless ) to emit .externs for other symbols too . One exception is when an object is within the -G limit but declared by the user to be in a section other than .sbss or .sdata .


<s> Value * ARMTargetLowering :: emitStoreConditional ( IRBuilder < > & Builder , Value * Val , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == 64 ) { Intrinsic :: ID Int = IsRelease ? Intrinsic :: arm_stlexd : Intrinsic :: arm_strexd ; Function * Strex = Intrinsic :: getDeclaration ( M , Int ) ; Type * Int32Ty = Type :: getInt32Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int32Ty , "lo" ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , 32 ) , Int32Ty , "hi" ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall3 ( Strex , Lo , Hi , Addr ) ; } Intrinsic :: ID Int = IsRelease ? Intrinsic :: arm_stlex : Intrinsic :: arm_strex ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Strex = Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateCall2 ( Strex , Builder . CreateZExtOrBitCast ( Val , Strex -> getFunctionType ( ) -> getParamType ( 0 ) ) , Addr ) ; } </s>

Perform a store-conditional operation to Addr .


<s> bool AMDGPUTargetLowering :: isCheapToSpeculateCttz ( ) const { return true ; } </s>

Return true if it is cheap to speculate a call to intrinsic cttz .


<s>
void
ARMAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
IsPCRel
,
nullptr
,
IsLittleEndian
)
;
if
(
!
Value
)
return
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
unsigned
FullSizeBytes
;
if
(
!
IsLittleEndian
)
FullSizeBytes
=
getFixupKindContainerSizeBytes
(
Fixup
.
getKind
(
)
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
IsLittleEndian
i
:
(
FullSizeBytes
1
i
)
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool AMDGPUTargetLowering :: isTruncateFree ( Type * Source , Type * Dest ) const { return Dest -> getPrimitiveSizeInBits ( ) < Source -> getPrimitiveSizeInBits ( ) && ( Dest -> getPrimitiveSizeInBits ( ) % 32 == 0 ) ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s> bool PPCPassConfig :: addInstSelector ( ) { PM -> add ( createPPCISelDag ( getPPCTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static bool ix86_optab_supported_p ( int op , machine_mode mode1 , machine_mode , optimization_type opt_type ) { switch ( op ) { case asin_optab : case acos_optab : case log1p_optab : case exp_optab : case exp10_optab : case exp2_optab : case expm1_optab : case ldexp_optab : case scalb_optab : case round_optab : return opt_type == OPTIMIZE_FOR_SPEED ; case rint_optab : if ( SSE_FLOAT_MODE_P ( mode1 ) && TARGET_SSE_MATH && ! flag_trapping_math && ! TARGET_ROUND ) return opt_type == OPTIMIZE_FOR_SPEED ; return true ; case floor_optab : case ceil_optab : case btrunc_optab : if ( SSE_FLOAT_MODE_P ( mode1 ) && TARGET_SSE_MATH && ! flag_trapping_math && TARGET_ROUND ) return true ; return opt_type == OPTIMIZE_FOR_SPEED ; case rsqrt_optab : return opt_type == OPTIMIZE_FOR_SPEED && use_rsqrt_p ( ) ; default : return true ; } } </s>

Implement the TARGET_OPTAB_SUPPORTED_P hook .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


"insertBranch must not be told to insert a fallthrough"

Insert branch code into the end of the specified MachineBasicBlock .


<s> bool PPCTargetLowering :: SelectAddressRegReg ( SDValue N , SDValue & Base , SDValue & Index , SelectionDAG & DAG ) const { int16_t imm = 0 ; if ( N . getOpcode ( ) == ISD :: ADD ) { if ( isIntS16Immediate ( N . getOperand ( 1 ) , imm ) ) return false ; if ( N . getOperand ( 1 ) . getOpcode ( ) == PPCISD :: Lo ) return false ; Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } else if ( N . getOpcode ( ) == ISD :: OR ) { if ( isIntS16Immediate ( N . getOperand ( 1 ) , imm ) ) return false ; KnownBits LHSKnown , RHSKnown ; DAG . computeKnownBits ( N . getOperand ( 0 ) , LHSKnown ) ; if ( LHSKnown . Zero . getBoolValue ( ) ) { DAG . computeKnownBits ( N . getOperand ( 1 ) , RHSKnown ) ; if ( ~ ( LHSKnown . Zero | RHSKnown . Zero ) == 0 ) { Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } } } return false ; } </s>

SelectAddressRegReg - Given the specified addressed , check to see if it can be more efficiently represented as [ r+imm ] .


"Sparc branch conditions should have one component!"

"Unconditional branch with multiple successors!"


<s>
void
NVPTXAsmPrinter
::
emitHeader
(
Module
&
M
,
raw_ostream
&
O
)
{
O
<<
"//\n"
;
O
<<
"// Generated by LLVM NVPTX Back-End\n"
;
O
<<
"//\n"
;
O
<<
"\n"
;
O
<<
".version 3.0\n"
;
O
<<
".target "
;
O
<<
nvptxSubtarget
.
getTargetName
(
)
;
if
(
nvptxSubtarget
.
getDrvInterface
(
)
==
NVPTX
::
NVCL
)
O
<<
", texmode_independent"
;
if
(
nvptxSubtarget
.
getDrvInterface
(
)
==
NVPTX
::
CUDA
)
{
if
(
!
nvptxSubtarget
.
hasDouble
(
)
)
O
<<
", map_f64_to_f32"
;
}
if
(
MAI
->
doesSupportDebugInformation
(
)
)
O
<<
", debug"
;
O
<<
"\n"
;
O
<<
".address_size "
;
if
(
nvptxSubtarget
.
is64Bit
(
)
)
O
<<
"64"
;
else
O
<<
"32"
;
O
<<
"\n"
;
O
<<
"\n"
;
}
</s>

Emit the header for this unit , not including the initial length field .

NVPTX
NVPTX
"//\n"
"// Generated by LLVM NVPTX Back-End\n"
"//\n"
"\n"
".version 3.0\n"
".target "
NVPTX::NVCL
", texmode_independent"
NVPTX::CUDA
", map_f64_to_f32"
", debug"
"\n"
".address_size "
"64"
"32"
"\n"
"\n"


<s> MCSection * getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C ) const override { return ReadOnlySection ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s>
Register
OutgoingValueHandler
::
extendRegister
(
Register
ValReg
,
const
CCValAssign
&
VA
)
{
LLT
LocTy
{
VA
.
getLocVT
(
)
}
;
switch
(
VA
.
getLocInfo
(
)
)
{
case
CCValAssign
::
SExt
:
{
Register
ExtReg
=
MRI
.
createGenericVirtualRegister
(
LocTy
)
;
MIRBuilder
.
buildSExt
(
ExtReg
,
ValReg
)
;
return
ExtReg
;
}
case
CCValAssign
::
ZExt
:
{
Register
ExtReg
=
MRI
.
createGenericVirtualRegister
(
LocTy
)
;
MIRBuilder
.
buildZExt
(
ExtReg
,
ValReg
)
;
return
ExtReg
;
}
case
CCValAssign
::
AExt
:
{
Register
ExtReg
=
MRI
.
createGenericVirtualRegister
(
LocTy
)
;
MIRBuilder
.
buildAnyExt
(
ExtReg
,
ValReg
)
;
return
ExtReg
;
}
case
CCValAssign
::
Full
:
return
ValReg
;
default
:
break
;
}
llvm_unreachable
(
"unable to extend register"
)
;
}
</s>

Extend a register to the location type given in VA , capped at extending to at most MaxSize bits .


<s> Optional < Value * > GCNTTIImpl :: simplifyDemandedVectorEltsIntrinsic ( InstCombiner & IC , IntrinsicInst & II , APInt DemandedElts , APInt & UndefElts , APInt & UndefElts2 , APInt & UndefElts3 , std :: function < void ( Instruction * , unsigned , APInt , APInt & ) > SimplifyAndSetOp ) const { switch ( II . getIntrinsicID ( ) ) { case Intrinsic :: amdgcn_buffer_load : case Intrinsic :: amdgcn_buffer_load_format : case Intrinsic :: amdgcn_raw_buffer_load : case Intrinsic :: amdgcn_raw_buffer_load_format : case Intrinsic :: amdgcn_raw_tbuffer_load : case Intrinsic :: amdgcn_s_buffer_load : case Intrinsic :: amdgcn_struct_buffer_load : case Intrinsic :: amdgcn_struct_buffer_load_format : case Intrinsic :: amdgcn_struct_tbuffer_load : case Intrinsic :: amdgcn_tbuffer_load : return simplifyAMDGCNMemoryIntrinsicDemanded ( IC , II , DemandedElts ) ; default : { if ( getAMDGPUImageDMaskIntrinsic ( II . getIntrinsicID ( ) ) ) { return simplifyAMDGCNMemoryIntrinsicDemanded ( IC , II , DemandedElts , 0 ) ; } break ; } } return None ; } </s>

Can be used to implement target-specific instruction combining .


<s>
bool
AArch64InstrInfo
::
isFPRCopy
(
const
MachineInstr
&
MI
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
TargetOpcode
::
COPY
:
{
unsigned
DstReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
return
(
AArch64
::
FPR64RegClass
.
contains
(
DstReg
)
||
AArch64
::
FPR128RegClass
.
contains
(
DstReg
)
)
;
}
case
AArch64
::
ORRv16i8
:
if
(
MI
.
getOperand
(
1
)
.
getReg
(
)
==
MI
.
getOperand
(
2
)
.
getReg
(
)
)
{
assert
(
MI
.
getDesc
(
)
.
getNumOperands
(
)
==
3
&&
MI
.
getOperand
(
0
)
.
isReg
(
)
&&
"invalid ORRv16i8 operands"
)
;
return
true
;
}
break
;
}
return
false
;
}
</s>

Does this instruction rename an FPR without modifying bits ?


"JIT relocation model must be set to static or default!"

runOnMachineFunction - Emit the function body .


<s> const MCPhysReg * SystemZRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const MCPhysReg CalleeSavedRegs [ ] = { SystemZ :: R6D , SystemZ :: R7D , SystemZ :: R8D , SystemZ :: R9D , SystemZ :: R10D , SystemZ :: R11D , SystemZ :: R12D , SystemZ :: R13D , SystemZ :: R14D , SystemZ :: R15D , SystemZ :: F8D , SystemZ :: F9D , SystemZ :: F10D , SystemZ :: F11D , SystemZ :: F12D , SystemZ :: F13D , SystemZ :: F14D , SystemZ :: F15D , 0 } ; return CalleeSavedRegs ; } </s>


"Unknown opcode to check as cheap as a move!"

Return true if the instruction is as cheap as a move instruction .


<s> static inline tree def_builtin ( HOST_WIDE_INT mask , const char * name , enum ix86_builtin_func_type tcode , enum ix86_builtins code ) { tree decl = NULL_TREE ; if ( ! ( mask & OPTION_MASK_ISA_64BIT ) || TARGET_64BIT ) { ix86_builtins_isa [ ( int ) code ] . isa = mask ; mask &= ~ OPTION_MASK_ISA_64BIT ; if ( ( mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512VL ) && mask != OPTION_MASK_ISA_AVX512VL ) mask &= ~ OPTION_MASK_ISA_AVX512VL ; if ( ( mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512BW ) && mask != OPTION_MASK_ISA_AVX512BW ) mask &= ~ OPTION_MASK_ISA_AVX512BW ; if ( mask == 0 || ( mask & ix86_isa_flags ) != 0 || ( lang_hooks . builtin_function == lang_hooks . builtin_function_ext_scope ) ) { tree type = ix86_get_builtin_func_type ( tcode ) ; decl = add_builtin_function ( name , type , code , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ ( int ) code ] = decl ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = false ; } else { deferred_isa_values |= mask ; ix86_builtins [ ( int ) code ] = NULL_TREE ; ix86_builtins_isa [ ( int ) code ] . tcode = tcode ; ix86_builtins_isa [ ( int ) code ] . name = name ; ix86_builtins_isa [ ( int ) code ] . leaf_p = false ; ix86_builtins_isa [ ( int ) code ] . nothrow_p = false ; ix86_builtins_isa [ ( int ) code ] . const_p = false ; ix86_builtins_isa [ ( int ) code ] . pure_p = false ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = true ; } } return decl ; } </s>

Add a SPARC builtin function with NAME , ICODE , CODE and TYPE . Return the function decl or NULL_TREE if the builtin was not added .


<s> unsigned JVMInstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { unsigned Count = 0 ; for ( auto ritr = MBB . instr_rbegin ( ) ; ritr != MBB . instr_rend ( ) ; ritr ++ ) { MachineInstr & MI = * ritr ; if ( ! MI . isBranch ( ) ) break ; MI . eraseFromParent ( ) ; Count ++ ; } return Count ; } </s>

Remove the branching code at the end of the specific MBB .


<s> static HOST_WIDE_INT get_csky_jump_table_size ( rtx insn ) { if ( JUMP_TABLES_IN_TEXT_SECTION || readonly_data_section == text_section ) { rtx body = PATTERN ( insn ) ; int elt = GET_CODE ( body ) == ADDR_DIFF_VEC ? 1 : 0 ; HOST_WIDE_INT size ; HOST_WIDE_INT modesize ; modesize = GET_MODE_SIZE ( GET_MODE ( body ) ) ; size = modesize * XVECLEN ( body , elt ) ; switch ( modesize ) { case 1 : size = ( size + 1 ) & ~ ( HOST_WIDE_INT ) 1 ; break ; case 2 : break ; case 4 : break ; default : gcc_unreachable ( ) ; } return size ; } return 0 ; } </s>

Compute the size of a vector jump table .


<s> MVT :: SimpleValueType MBlazeTargetLowering :: getSetCCResultType ( EVT VT ) const { return MVT :: i32 ; } </s>

Return the value type to use for ISD : :SETCC .

MBlaze MVT::SimpleValueType MBlaze MVT::i32


<s> const MCExpr * AArch64_MachoTargetObjectFile :: getTTypeGlobalReference ( const GlobalValue * GV , unsigned Encoding , const TargetMachine & TM , MachineModuleInfo * MMI , MCStreamer & Streamer ) const { if ( Encoding & ( DW_EH_PE_indirect | DW_EH_PE_pcrel ) ) { const MCSymbol * Sym = TM . getSymbol ( GV ) ; const MCExpr * Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_GOT , getContext ( ) ) ; MCSymbol * PCSym = getContext ( ) . createTempSymbol ( ) ; Streamer . EmitLabel ( PCSym ) ; const MCExpr * PC = MCSymbolRefExpr :: create ( PCSym , getContext ( ) ) ; return MCBinaryExpr :: createSub ( Res , PC , getContext ( ) ) ; } return TargetLoweringObjectFileMachO :: getTTypeGlobalReference ( GV , Encoding , TM , MMI , Streamer ) ; } </s>

The mach-o version of this method defaults to returning a stub reference .


<s> bool SIRegisterInfo :: requiresFrameIndexReplacementScavenging ( const MachineFunction & MF ) const { return MF . getFrameInfo ( ) . hasStackObjects ( ) && MF . getSubtarget < GCNSubtarget > ( ) . hasScalarStores ( ) && MF . getInfo < SIMachineFunctionInfo > ( ) -> hasSpilledSGPRs ( ) ; } </s>

Returns true if the target requires using the RegScavenger directly for frame elimination despite using requiresFrameIndexScavenging .


<s>
void
X86AsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
X86MCInstLower
MCInstLowering
(
Mang
,
*
MF
,
*
this
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
TargetOpcode
::
DBG_VALUE
:
if
(
isVerbose
(
)
&&
OutStreamer
.
hasRawTextSupport
(
)
)
{
std
::
string
TmpStr
;
raw_string_ostream
OS
(
TmpStr
)
;
PrintDebugValueComment
(
MI
,
OS
)
;
OutStreamer
.
EmitRawText
(
StringRef
(
OS
.
str
(
)
)
)
;
}
return
;
case
X86
::
Int_MemBarrier
:
if
(
OutStreamer
.
hasRawTextSupport
(
)
)
OutStreamer
.
EmitRawText
(
StringRef
(
"\t#MEMBARRIER"
)
)
;
return
;
case
X86
::
EH_RETURN
:
case
X86
::
EH_RETURN64
:
{
unsigned
Reg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
OutStreamer
.
AddComment
(
StringRef
(
"eh_return, addr: %"
)
+
X86ATTInstPrinter
::
getRegisterName
(
Reg
)
)
;
break
;
}
case
X86
::
TAILJMPr
:
case
X86
::
TAILJMPd
:
case
X86
::
TAILJMPd64
:
OutStreamer
.
AddComment
(
"TAILCALL"
)
;
break
;
case
X86
::
TLS_addr32
:
case
X86
::
TLS_addr64
:
case
X86
::
TLS_base_addr32
:
case
X86
::
TLS_base_addr64
:
return
LowerTlsAddr
(
OutStreamer
,
MCInstLowering
,
*
MI
)
;
case
X86
::
MOVPC32r
:
{
MCSymbol
*
PICBase
=
MF
->
getPICBaseSymbol
(
)
;
OutStreamer
.
EmitInstruction
(
MCInstBuilder
(
X86
::
CALLpcrel32
)
.
addExpr
(
MCSymbolRefExpr
::
Create
(
PICBase
,
OutContext
)
)
)
;
OutStreamer
.
EmitLabel
(
PICBase
)
;
OutStreamer
.
EmitInstruction
(
MCInstBuilder
(
X86
::
POP32r
)
.
addReg
(
MI
->
getOperand
(
0
)
.
getReg
(
)
)
)
;
return
;
}
case
X86
::
ADD32ri
:
{
if
(
MI
->
getOperand
(
2
)
.
getTargetFlags
(
)
!=
X86II
::
MO_GOT_ABSOLUTE_ADDRESS
)
break
;
MCSymbol
*
DotSym
=
OutContext
.
CreateTempSymbol
(
)
;
OutStreamer
.
EmitLabel
(
DotSym
)
;
MCSymbol
*
OpSym
=
MCInstLowering
.
GetSymbolFromOperand
(
MI
->
getOperand
(
2
)
)
;
const
MCExpr
*
DotExpr
=
MCSymbolRefExpr
::
Create
(
DotSym
,
OutContext
)
;
const
MCExpr
*
PICBase
=
MCSymbolRefExpr
::
Create
(
MF
->
getPICBaseSymbol
(
)
,
OutContext
)
;
DotExpr
=
MCBinaryExpr
::
CreateSub
(
DotExpr
,
PICBase
,
OutContext
)
;
DotExpr
=
MCBinaryExpr
::
CreateAdd
(
MCSymbolRefExpr
::
Create
(
OpSym
,
OutContext
)
,
DotExpr
,
OutContext
)
;
OutStreamer
.
EmitInstruction
(
MCInstBuilder
(
X86
::
ADD32ri
)
.
addReg
(
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addExpr
(
DotExpr
)
)
;
return
;
}
}
MCInst
TmpInst
;
MCInstLowering
.
Lower
(
MI
,
TmpInst
)
;
OutStreamer
.
EmitInstruction
(
TmpInst
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool constant_address_p ( rtx x ) { return CONSTANT_P ( x ) && legitimate_address_p ( Pmode , x , 1 ) ; } </s>

Determine if a given RTX is a valid constant address .


<s> bool isToken ( ) const override { return Kind == k_Token ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 insert wait instruction"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void HexagonAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst MCB = HexagonMCInstrInfo :: createBundle ( ) ; const MCInstrInfo & MCII = * Subtarget -> getInstrInfo ( ) ; if ( MI -> isBundle ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI -> getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( ! MII -> isDebugValue ( ) && ! MII -> isImplicitDef ( ) ) HexagonLowerToMC ( MCII , & * MII , MCB , * this ) ; } else HexagonLowerToMC ( MCII , MI , MCB , * this ) ; bool Ok = HexagonMCInstrInfo :: canonicalizePacket ( MCII , * Subtarget , OutStreamer -> getContext ( ) , MCB , nullptr ) ; assert ( Ok ) ; ( void ) Ok ; if ( HexagonMCInstrInfo :: bundleSize ( MCB ) == 0 ) return ; OutStreamer -> EmitInstruction ( MCB , getSubtargetInfo ( ) ) ; } </s>

Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon 0


<s> static void mips_emit_loadgp ( void ) { if ( TARGET_ABICALLS && TARGET_NEWABI && cfun -> machine -> global_pointer > 0 ) { rtx addr , offset , incoming_address ; addr = XEXP ( DECL_RTL ( current_function_decl ) , 0 ) ; offset = mips_unspec_address ( addr , SYMBOL_GOTOFF_LOADGP ) ; incoming_address = gen_rtx_REG ( Pmode , PIC_FUNCTION_ADDR_REGNUM ) ; emit_insn ( gen_loadgp ( offset , incoming_address ) ) ; if ( ! TARGET_EXPLICIT_RELOCS ) emit_insn ( gen_loadgp_blockage ( ) ) ; } } </s>

If we 're generating n32 or n64 abicalls , emit instructions to set up the global pointer .


<s> static bool flow_dependent_p ( rtx_insn * insn , rtx_insn * dep_insn ) { rtx tmp = PATTERN ( insn ) ; note_stores ( dep_insn , flow_dependent_p_1 , & tmp ) ; return tmp == NULL_RTX ; } </s>

Check if INSN is flow-dependent on DEP_INSN . Can also be used to check if DEP_INSN is anti-flow dependent on INSN .


<s>
StringRef
getPassName
(
)
const
override
{
return
"PULP Hardware Loops"
;
}
</s>


<s>
static
void
x86_print_call_or_nop
(
FILE
*
file
,
const
char
*
target
)
{
if
(
flag_nop_mcount
||
!
strcmp
(
target
,
"nop"
)
)
fprintf
(
file
,
"1:"
ASM_BYTE
"0x0f, 0x1f, 0x44, 0x00, 0x00\n"
)
;
else
fprintf
(
file
,
"1:\tcall\t%s\n"
,
target
)
;
}
</s>


<s> HOST_WIDE_INT ia64_initial_elimination_offset ( int from , int to ) { HOST_WIDE_INT offset ; ia64_compute_frame_size ( get_frame_size ( ) ) ; switch ( from ) { case FRAME_POINTER_REGNUM : switch ( to ) { case HARD_FRAME_POINTER_REGNUM : if ( current_function_is_leaf ) offset = - current_frame_info . total_size ; else offset = - ( current_frame_info . total_size - current_function_outgoing_args_size - 16 ) ; break ; case STACK_POINTER_REGNUM : if ( current_function_is_leaf ) offset = 0 ; else offset = 16 + current_function_outgoing_args_size ; break ; default : gcc_unreachable ( ) ; } break ; case ARG_POINTER_REGNUM : switch ( to ) { case HARD_FRAME_POINTER_REGNUM : offset = 16 - current_function_pretend_args_size ; break ; case STACK_POINTER_REGNUM : offset = ( current_frame_info . total_size + 16 - current_function_pretend_args_size ) ; break ; default : gcc_unreachable ( ) ; } break ; default : gcc_unreachable ( ) ; } return offset ; } </s>

Compute the initial difference between the specified pair of registers .


<s> DecodeStatus ECLairDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & OS , raw_ostream & CS ) const { DecodeStatus status ; uint8_t opcode = support :: endian :: read < uint8_t , support :: endianness :: big > ( Bytes . data ( ) ) ; uint16_t arg = support :: endian :: read16be ( Bytes . data ( ) + 1 ) ; uint32_t bigInst = opcode << 16 | arg ; status = decodeInstruction ( DecoderTable24 , MI , bigInst , Address , this , STI ) ; if ( status == Success ) { Size = 3 ; return Success ; } uint16_t shortInst = support :: endian :: read16be ( Bytes . data ( ) ) ; status = decodeInstruction ( DecoderTable16 , MI , shortInst , Address , this , STI ) ; if ( status == Success ) { Size = 2 ; return Success ; } uint8_t byteInst = support :: endian :: read < uint8_t , support :: endianness :: big > ( Bytes . data ( ) ) ; status = decodeInstruction ( DecoderTable8 , MI , byteInst , Address , this , STI ) ; if ( status == Success ) { Size = 1 ; return Success ; } Size = 0 ; return status ; } </s>

Returns the disassembly of a single instruction .


<s> void MipsPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; addPass ( createAtomicExpandPass ( & getMipsTargetMachine ( ) ) ) ; if ( getMipsSubtarget ( ) . os16 ( ) ) addPass ( createMipsOs16 ( getMipsTargetMachine ( ) ) ) ; if ( getMipsSubtarget ( ) . inMips16HardFloat ( ) ) addPass ( createMips16HardFloat ( getMipsTargetMachine ( ) ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips


<s> void DigitalTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; this -> TM = & static_cast < const DigitalTargetMachine & > ( TM ) ; } </s>

This method must be called before any actual lowering is done .


"Should use MaskedValueIsZero if you don't know whether Op"

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


"ABI for flattened struct with zero-length "

See whether TYPE is a record whose fields should be returned in one or two floating-point registers . If so , populate FIELDS accordingly .


<s> unsigned getNumFixupKinds ( ) const { return 1 ; } </s>

Get the number of target specific fixup kinds .


<s> bool isMem ( ) const { return Kind == Memory ; } </s>


<s> bool HSAILTargetLowering :: isDesirableToTransformToIntegerOp ( unsigned Opc , EVT VT ) const { return ( Opc == ISD :: LOAD || Opc == ISD :: STORE ) && ( VT . getSimpleVT ( ) == MVT :: f32 || VT . getSimpleVT ( ) == MVT :: f64 ) ; } </s>

Return true if it is profitable for dag combiner to transform a floating point op of specified opcode to a equivalent op of an integer type .

HSAIL HSAIL ISD::LOAD ISD::STORE MVT::f32 MVT::f64


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { unsigned OpId ; switch ( Inst . getOpcode ( ) ) { default : OpId = 0 ; break ; case ARM :: t2WLS : case ARM :: t2LEUpdate : OpId = 2 ; break ; case ARM :: t2LE : OpId = 1 ; break ; } if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ OpId ] . OperandType != MCOI :: OPERAND_PCREL ) return false ; Target = Addr + Inst . getOperand ( OpId ) . getImm ( ) + 4 ; return true ; } </s>

Given a branch instruction try to get the address the branch targets .


<s>
StringRef
getPassName
(
)
const
override
{
return
"SPIRV OCL Regularizer"
;
}
</s>


<s> EVT getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , const AttributeList & FuncAttributes ) const override { return Size >= 8 ? MVT :: i64 : MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> int AArch64FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { return resolveFrameIndexReference ( MF , FI , FrameReg , MF . getFunction ( ) . hasFnAttribute ( Attribute :: SanitizeHWAddress ) , false ) . getBytes ( ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> TargetLowering :: AtomicExpansionKind PPCTargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( shouldInlineQuadwordAtomics ( ) && Size == 128 ) return AtomicExpansionKind :: MaskedIntrinsic ; return TargetLowering :: shouldExpandAtomicRMWInIR ( AI ) ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> void initialize ( Attributor & A ) override { Function * F = getAssociatedFunction ( ) ; auto & InfoCache = static_cast < AMDGPUInformationCache & > ( A . getInfoCache ( ) ) ; unsigned MinGroupSize , MaxGroupSize ; std :: tie ( MinGroupSize , MaxGroupSize ) = InfoCache . getFlatWorkGroupSizes ( * F ) ; intersectKnown ( ConstantRange ( APInt ( 32 , MinGroupSize ) , APInt ( 32 , MaxGroupSize + 1 ) ) ) ; if ( AMDGPU :: isEntryFunctionCC ( F -> getCallingConv ( ) ) ) indicatePessimisticFixpoint ( ) ; } </s>

Initialize the strategy after building the DAG for a new region .


<s> bool SIRegisterInfo :: isFrameOffsetLegal ( const MachineInstr * MI , Register BaseReg , int64_t Offset ) const { if ( ! SIInstrInfo :: isMUBUF ( * MI ) && ! SIInstrInfo :: isFLATScratch ( * MI ) ) return false ; int64_t NewOffset = Offset + getScratchInstrOffset ( MI ) ; if ( SIInstrInfo :: isMUBUF ( * MI ) ) return SIInstrInfo :: isLegalMUBUFImmOffset ( NewOffset ) ; const SIInstrInfo * TII = ST . getInstrInfo ( ) ; return TII -> isLegalFLATOffset ( NewOffset , AMDGPUAS :: PRIVATE_ADDRESS , true ) ; } </s>

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s>
void
AMDGPUAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
)
const
{
switch
(
(
unsigned
)
Fixup
.
getKind
(
)
)
{
default
:
llvm_unreachable
(
"Unknown fixup kind"
)
;
case
AMDGPU
::
fixup_si_sopp_br
:
{
uint16_t
*
Dst
=
(
uint16_t
*
)
(
Data
+
Fixup
.
getOffset
(
)
)
;
*
Dst
=
(
Value
4
)
/
4
;
break
;
}
case
AMDGPU
::
fixup_si_rodata
:
{
uint32_t
*
Dst
=
(
uint32_t
*
)
(
Data
+
Fixup
.
getOffset
(
)
)
;
*
Dst
=
Value
;
break
;
}
case
AMDGPU
::
fixup_si_end_of_text
:
{
uint32_t
*
Dst
=
(
uint32_t
*
)
(
Data
+
Fixup
.
getOffset
(
)
)
;
*
Dst
=
Value
+
4
;
break
;
}
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static rtx aarch64_replace_reg_mode ( rtx x , machine_mode mode ) { if ( GET_MODE ( x ) == mode ) return x ; x = shallow_copy_rtx ( x ) ; set_mode_and_regno ( x , mode , REGNO ( x ) ) ; return x ; } </s>

Return a copy of X with mode MODE , without changing its other attributes . Unlike gen_lowpart , this does n't care whether the mode change is valid .


<s> std :: pair < const TargetRegisterClass * , uint8_t > PIC16TargetLowering :: findRepresentativeClass ( EVT VT ) const { switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( VT ) ; case MVT :: i16 : return std :: make_pair ( PIC16 :: FSR16RegisterClass , 1 ) ; } } </s>

Return the largest legal super-reg register class of the register class for the specified type and its associated `` cost '' .


"cannot return value in vector register because"

" altivec instructions are disabled, use %qs"

Handle the INIT_CUMULATIVE_ARGS macro . Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is 0 .


<s> static void rs6000_emit_move_from_cr ( rtx reg ) { if ( DEFAULT_ABI == ABI_ELFv2 && TARGET_MFCRF ) { int i , cr_reg [ 8 ] , count = 0 ; for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) cr_reg [ count ++ ] = i ; if ( count == 1 ) { rtvec p = rtvec_alloc ( 1 ) ; rtvec r = rtvec_alloc ( 2 ) ; RTVEC_ELT ( r , 0 ) = gen_rtx_REG ( CCmode , CR0_REGNO + cr_reg [ 0 ] ) ; RTVEC_ELT ( r , 1 ) = GEN_INT ( 1 << ( 7 - cr_reg [ 0 ] ) ) ; RTVEC_ELT ( p , 0 ) = gen_rtx_SET ( reg , gen_rtx_UNSPEC ( SImode , r , UNSPEC_MOVESI_FROM_CR ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , p ) ) ; return ; } } emit_insn ( gen_movesi_from_cr ( reg ) ) ; } </s>

Emit code to store CR fields that need to be saved into REG .


runOnMachineFunction - Emit the function body .


<s> inline bool function_base :: apply_vl_p ( ) const { return true ; } </s>

We choose to apply vl operand by default since most of the intrinsics has vl operand .


<s> HOST_WIDE_INT loongarch_debugger_offset ( rtx addr , HOST_WIDE_INT offset ) { rtx offset2 = const0_rtx ; rtx reg = eliminate_constant_term ( addr , & offset2 ) ; if ( offset == 0 ) offset = INTVAL ( offset2 ) ; if ( reg == stack_pointer_rtx || reg == frame_pointer_rtx || reg == hard_frame_pointer_rtx ) { offset -= cfun -> machine -> frame . total_size ; if ( reg == hard_frame_pointer_rtx ) offset += cfun -> machine -> frame . hard_frame_pointer_offset ; } return offset ; } </s>

The LoongArch debug format wants all automatic variables and arguments to be in terms of the virtual frame pointer ( stack pointer before any adjustment in the function ) , while the LoongArch linker wants the frame pointer to be the stack pointer after the initial adjustment . So , we do the adjustment here . The arg pointer ( which is eliminated ) points to the virtual frame pointer , while the frame pointer ( which may be eliminated ) points to the stack pointer after the initial adjustments .


<s> MachineInstr * DLXInstrInfo :: optimizeSelect ( MachineInstr & MI , SmallPtrSetImpl < MachineInstr * > & SeenMIs , bool PreferFalse ) const { return nullptr ; } </s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


<s> bool hasTailCall ( ) const { return HasTailCall ; } </s>

Returns true if the function contains a tail call .


<s> static void rl78_alloc_physical_registers_ro1 ( rtx_insn * insn ) { OP ( 0 ) = transcode_memory_rtx ( OP ( 0 ) , BC , insn ) ; MAYBE_OK ( insn ) ; OP ( 0 ) = move_to_acc ( 0 , insn ) ; MUST_BE_OK ( insn ) ; } </s>

Devirtualize an insn of the form SET ( PC ) ( MEM/REG ) .


<s> bool Thumb2InstrInfo :: isLegalToSplitMBBAt ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) const { while ( MBBI -> isDebugInstr ( ) ) { ++ MBBI ; if ( MBBI == MBB . end ( ) ) return false ; } Register PredReg ; return getITInstrPredicate ( * MBBI , PredReg ) == ARMCC :: AL ; } </s>

Return true if it 's legal to split the given basic block at the specified instruction ( i.e .


<s> bool PatmosSubtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = ANTIDEP_NONE ; return hasPostRAScheduler ( OptLevel ) ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s> unsigned TPCInstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { MachineBasicBlock :: iterator I = MBB . end ( ) ; unsigned Count = 0 ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! I -> isBranch ( ) ) return Count ; MBB . erase ( & MBB . back ( ) ) ; I = MBB . end ( ) ; ++ Count ; } return Count ; } </s>

Remove the branching code at the end of the specific MBB .


<s> bool LanaiInstrInfo :: getMemOperandWithOffsetWidth ( const MachineInstr & LdSt , const MachineOperand * & BaseOp , int64_t & Offset , unsigned & Width , const TargetRegisterInfo * ) const { if ( LdSt . getNumOperands ( ) != 4 ) return false ; if ( ! LdSt . getOperand ( 1 ) . isReg ( ) || ! LdSt . getOperand ( 2 ) . isImm ( ) || ! ( LdSt . getOperand ( 3 ) . isImm ( ) && LdSt . getOperand ( 3 ) . getImm ( ) == LPAC :: ADD ) ) return false ; switch ( LdSt . getOpcode ( ) ) { default : return false ; case Lanai :: LDW_RI : case Lanai :: LDW_RR : case Lanai :: SW_RR : case Lanai :: SW_RI : Width = 4 ; break ; case Lanai :: LDHs_RI : case Lanai :: LDHz_RI : case Lanai :: STH_RI : Width = 2 ; break ; case Lanai :: LDBs_RI : case Lanai :: LDBz_RI : case Lanai :: STB_RI : Width = 1 ; break ; } BaseOp = & LdSt . getOperand ( 1 ) ; Offset = LdSt . getOperand ( 2 ) . getImm ( ) ; if ( ! BaseOp -> isReg ( ) ) return false ; return true ; } </s>

Return true if get the base operand , byte offset of an instruction and the memory width .


<s>
BTFTypeDerived
::
BTFTypeDerived
(
const
DIDerivedType
*
DTy
,
unsigned
Tag
)
:
DTy
(
DTy
)
{
switch
(
Tag
)
{
case
dwarf
::
DW_TAG_pointer_type
:
Kind
=
BTF
::
BTF_KIND_PTR
;
break
;
case
dwarf
::
DW_TAG_const_type
:
Kind
=
BTF
::
BTF_KIND_CONST
;
break
;
case
dwarf
::
DW_TAG_volatile_type
:
Kind
=
BTF
::
BTF_KIND_VOLATILE
;
break
;
case
dwarf
::
DW_TAG_typedef
:
Kind
=
BTF
::
BTF_KIND_TYPEDEF
;
break
;
case
dwarf
::
DW_TAG_restrict_type
:
Kind
=
BTF
::
BTF_KIND_RESTRICT
;
break
;
default
:
llvm_unreachable
(
"Unknown DIDerivedType Tag"
)
;
}
BTFType
.
Info
=
Kind
<<
24
;
}
</s>


<s> const char * nvptx_ptx_type_from_mode ( machine_mode mode , bool promote ) { switch ( mode ) { case BLKmode : return ".b8" ; case BImode : return ".pred" ; case QImode : if ( promote ) return ".u32" ; else return ".u8" ; case HImode : return ".u16" ; case SImode : return ".u32" ; case DImode : return ".u64" ; case SFmode : return ".f32" ; case DFmode : return ".f64" ; default : gcc_unreachable ( ) ; } } </s>

Return a ptx type for MODE . If PROMOTE , then use .u32 for QImode to deal with ptx ideosyncracies .


<s> const TargetRegisterClass * TeakRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { if ( Teak :: ABRegsRegClass . hasSubClassEq ( RC ) ) return & Teak :: ABRegsRegClass ; if ( Teak :: RegNoBRegs16_nohRegClass . hasSubClassEq ( RC ) ) return & Teak :: RegNoBRegs16_nohRegClass ; return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .

Teak Teak Teak::ABRegsRegClass Teak::ABRegsRegClass Teak::RegNoBRegs16_nohRegClass Teak::RegNoBRegs16_nohRegClass


<s> SDValue X86TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: VECTOR_SHUFFLE : return PerformShuffleCombine ( N , DAG , * this ) ; case ISD :: SELECT : return PerformSELECTCombine ( N , DAG , Subtarget ) ; case X86ISD :: CMOV : return PerformCMOVCombine ( N , DAG , DCI ) ; case ISD :: MUL : return PerformMulCombine ( N , DAG , DCI ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DAG , Subtarget ) ; case ISD :: OR : return PerformOrCombine ( N , DAG , Subtarget ) ; case ISD :: STORE : return PerformSTORECombine ( N , DAG , Subtarget ) ; case X86ISD :: FXOR : case X86ISD :: FOR : return PerformFORCombine ( N , DAG ) ; case X86ISD :: FAND : return PerformFANDCombine ( N , DAG ) ; case X86ISD :: BT : return PerformBTCombine ( N , DAG , DCI ) ; case X86ISD :: VZEXT_MOVL : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case ISD :: MEMBARRIER : return PerformMEMBARRIERCombine ( N , DAG ) ; case ISD :: ZERO_EXTEND : return PerformZExtCombine ( N , DAG ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s>
SDValue
XNCMTargetLowering
::
LowerCall
(
SDValue
Chain
,
SDValue
Callee
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
bool
doesNotRet
,
bool
&
isTailCall
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
OutVals
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .

XNCM
XNCM
ISD::OutputArg
ISD::InputArg
"Unsupported calling convention"


<s> bool X86IndirectBranchTrackingPass :: runOnMachineFunction ( MachineFunction & MF ) { const X86Subtarget & SubTarget = MF . getSubtarget < X86Subtarget > ( ) ; auto & MMI = MF . getMMI ( ) ; Metadata * isCFProtectionSupported = MMI . getModule ( ) -> getModuleFlag ( "cf-protection-branch" ) ; Metadata * FineIBT = MMI . getModule ( ) -> getModuleFlag ( "cf-protection-fine" ) ; const X86TargetMachine * TM = static_cast < const X86TargetMachine * > ( & MF . getTarget ( ) ) ; bool isJITwithCET = TM -> isJIT ( ) ; bool isJITwithCET = false ; if ( ! isCFProtectionSupported && ! IndirectBranchTracking && ! isJITwithCET ) return false ; bool Changed = false ; TII = SubTarget . getInstrInfo ( ) ; EndbrOpcode = SubTarget . is64Bit ( ) ? X86 :: ENDBR64 : X86 :: ENDBR32 ; if ( FineIBT ) { Changed |= applyFineIBT ( MF ) ; FixICalls ( MF ) ; FixDCalls ( MF ) ; } else { Changed |= applyCoarseIBT ( MF ) ; } for ( auto & MBB : MF ) { if ( MBB . hasAddressTaken ( ) ) Changed |= addENDBR ( MBB , MBB . begin ( ) ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( I -> isCall ( ) && IsCallReturnTwice ( I -> getOperand ( 0 ) ) ) Changed |= addENDBR ( MBB , std :: next ( I ) ) ; } if ( TM -> Options . ExceptionModel == ExceptionHandling :: SjLj ) { for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( MBB . isEHPad ( ) ) { if ( I -> isDebugInstr ( ) ) continue ; Changed |= addENDBR ( MBB , I ) ; break ; } else if ( I -> isEHLabel ( ) ) { MCSymbol * Sym = I -> getOperand ( 0 ) . getMCSymbol ( ) ; if ( ! MF . hasCallSiteLandingPad ( Sym ) ) continue ; Changed |= addENDBR ( MBB , std :: next ( I ) ) ; break ; } } } else if ( MBB . isEHPad ( ) ) { for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( ! I -> isEHLabel ( ) ) continue ; Changed |= addENDBR ( MBB , std :: next ( I ) ) ; break ; } } } return Changed ; } </s>


<s> void GCNPassConfig :: addOptimizedRegAlloc ( ) { if ( OptExecMaskPreRA ) insertPass ( & MachineSchedulerID , & SIOptimizeExecMaskingPreRAID ) ; insertPass ( & MachineSchedulerID , & SIFormMemoryClausesID ) ; insertPass ( & PHIEliminationID , & SILowerControlFlowID , false ) ; insertPass ( & RegisterCoalescerID , & SIPreAllocateWWMRegsID , false ) ; if ( EnableDCEInRA ) insertPass ( & DetectDeadLanesID , & DeadMachineInstructionElimID ) ; TargetPassConfig :: addOptimizedRegAlloc ( ) ; } </s>

addOptimizedRegAlloc - Add passes related to register allocation .


"Register sequence is not valid. 'r4-r7' expected"

Process a single instruction and collect debug info anchors .


<s>
void
Mips16InstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineMemOperand
*
MMO
=
GetMemOperand
(
MBB
,
FI
,
MachineMemOperand
::
MOLoad
)
;
unsigned
Opc
=
0
;
if
(
Mips
::
CPU16RegsRegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
Mips
::
LwRxSpImmX16
;
assert
(
Opc
&&
"Register class not handled!"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s>
void
M68kAsmBackend
::
relaxInstruction
(
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
)
const
{
unsigned
RelaxedOp
=
getRelaxedOpcode
(
Inst
)
;
if
(
RelaxedOp
==
Inst
.
getOpcode
(
)
)
{
SmallString
<
256
>
Tmp
;
raw_svector_ostream
OS
(
Tmp
)
;
Inst
.
dump_pretty
(
OS
)
;
OS
<<
"\n"
;
report_fatal_error
(
"unexpected instruction to relax: "
+
OS
.
str
(
)
)
;
}
Inst
.
setOpcode
(
RelaxedOp
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> static int do_reorder_for_imul ( rtx_insn * * ready , int n_ready ) { rtx_insn * insn ; rtx set , insn1 , insn2 ; sd_iterator_def sd_it ; dep_t dep ; int index = - 1 ; int i ; if ( ! TARGET_CPU_P ( BONNELL ) ) return index ; insn = ready [ n_ready - 1 ] ; set = single_set ( insn ) ; if ( ! set ) return index ; if ( ! ( GET_CODE ( SET_SRC ( set ) ) == MULT && GET_MODE ( SET_SRC ( set ) ) == SImode ) ) return index ; for ( i = n_ready - 2 ; i >= 0 ; i -- ) { insn = ready [ i ] ; if ( ! NONDEBUG_INSN_P ( insn ) ) continue ; insn2 = PATTERN ( insn ) ; if ( GET_CODE ( insn2 ) == PARALLEL ) insn2 = XVECEXP ( insn2 , 0 , 0 ) ; if ( GET_CODE ( insn2 ) == SET && GET_CODE ( SET_SRC ( insn2 ) ) == MULT && GET_MODE ( SET_SRC ( insn2 ) ) == SImode ) continue ; FOR_EACH_DEP ( insn , SD_LIST_FORW , sd_it , dep ) { rtx con ; con = DEP_CON ( dep ) ; if ( ! NONDEBUG_INSN_P ( con ) ) continue ; insn1 = PATTERN ( con ) ; if ( GET_CODE ( insn1 ) == PARALLEL ) insn1 = XVECEXP ( insn1 , 0 , 0 ) ; if ( GET_CODE ( insn1 ) == SET && GET_CODE ( SET_SRC ( insn1 ) ) == MULT && GET_MODE ( SET_SRC ( insn1 ) ) == SImode ) { sd_iterator_def sd_it1 ; dep_t dep1 ; index = i ; FOR_EACH_DEP ( con , SD_LIST_BACK , sd_it1 , dep1 ) { rtx pro ; pro = DEP_PRO ( dep1 ) ; if ( ! NONDEBUG_INSN_P ( pro ) ) continue ; if ( pro != insn ) index = - 1 ; } if ( index >= 0 ) break ; } } if ( index >= 0 ) break ; } return index ; } </s>

Try to reorder ready list to take advantage of Atom pipelined IMUL execution . It is applied if ( 1 ) IMUL instruction is on the top of list ; ( 2 ) There exists the only producer of independent IMUL instruction in ready list . Return index of IMUL producer if it was found and -1 otherwise .


<s> void tool_cleanup ( bool from_signal ATTRIBUTE_UNUSED ) { if ( ptx_cfile_name ) maybe_unlink ( ptx_cfile_name ) ; if ( ptx_name ) maybe_unlink ( ptx_name ) ; } </s>


<s> bool doInitialization ( Module & M ) override { return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> bool HexagonAsmParser :: parseExpression ( MCExpr const * & Expr ) { SmallVector < AsmToken , 4 > Tokens ; MCAsmLexer & Lexer = getLexer ( ) ; bool Done = false ; static char const * Comma = "," ; do { Tokens . emplace_back ( Lexer . getTok ( ) ) ; Lex ( ) ; switch ( Tokens . back ( ) . getKind ( ) ) { case AsmToken :: TokenKind :: Hash : if ( Tokens . size ( ) > 1 ) if ( ( Tokens . end ( ) - 2 ) -> getKind ( ) == AsmToken :: TokenKind :: Plus ) { Tokens . insert ( Tokens . end ( ) - 2 , AsmToken ( AsmToken :: TokenKind :: Comma , Comma ) ) ; Done = true ; } break ; case AsmToken :: TokenKind :: RCurly : case AsmToken :: TokenKind :: EndOfStatement : case AsmToken :: TokenKind :: Eof : Done = true ; break ; default : break ; } } while ( ! Done ) ; while ( ! Tokens . empty ( ) ) { Lexer . UnLex ( Tokens . back ( ) ) ; Tokens . pop_back ( ) ; } return getParser ( ) . parseExpression ( Expr ) ; } </s>


Hook to validate attribute ( ( target ( `` ... '' ) ) ) .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequiredID ( LoopSimplifyID ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addRequired < TargetTransformInfoWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
void
dump
(
)
{
dbgs
(
)
<<
"X86ISelAddressMode "
<<
this
<<
'\n'
;
dbgs
(
)
<<
"Base_Reg "
;
if
(
Base_Reg
.
getNode
(
)
)
Base_Reg
.
getNode
(
)
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" Base.FrameIndex "
<<
Base_FrameIndex
<<
'\n'
<<
" Scale"
<<
Scale
<<
'\n'
<<
"IndexReg "
;
if
(
IndexReg
.
getNode
(
)
)
IndexReg
.
getNode
(
)
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" Disp "
<<
Disp
<<
'\n'
<<
"GV "
;
if
(
GV
)
GV
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" CP "
;
if
(
CP
)
CP
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
'\n'
<<
"ES "
;
if
(
ES
)
dbgs
(
)
<<
ES
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" MCSym "
;
if
(
MCSym
)
dbgs
(
)
<<
MCSym
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" JT"
<<
JT
<<
" Align"
<<
Align
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

X86
"X86ISelAddressMode "
"Base_Reg "
"nul"
" Base.FrameIndex "
" Scale"
"IndexReg "
"nul"
" Disp "
"GV "
"nul"
" CP "
"nul"
"ES "
"nul"
" MCSym "
"nul"
" JT"
" Align"


<s>
SDValue
XCoreTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
BR_JT
:
return
LowerBR_JT
(
Op
,
DAG
)
;
case
ISD
::
LOAD
:
return
LowerLOAD
(
Op
,
DAG
)
;
case
ISD
::
STORE
:
return
LowerSTORE
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
VAARG
:
return
LowerVAARG
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
SMUL_LOHI
:
return
LowerSMUL_LOHI
(
Op
,
DAG
)
;
case
ISD
::
UMUL_LOHI
:
return
LowerUMUL_LOHI
(
Op
,
DAG
)
;
case
ISD
::
ADD
:
case
ISD
::
SUB
:
return
ExpandADDSUB
(
Op
.
getNode
(
)
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
INIT_TRAMPOLINE
:
return
LowerINIT_TRAMPOLINE
(
Op
,
DAG
)
;
case
ISD
::
ADJUST_TRAMPOLINE
:
return
LowerADJUST_TRAMPOLINE
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> int check_pic ( int i ) { switch ( flag_pic ) { case 1 : gcc_assert ( GET_CODE ( recog_data . operand [ i ] ) != SYMBOL_REF && ( GET_CODE ( recog_data . operand [ i ] ) != CONST || ( GET_CODE ( XEXP ( recog_data . operand [ i ] , 0 ) ) == MINUS && ( XEXP ( XEXP ( recog_data . operand [ i ] , 0 ) , 0 ) == global_offset_table ) && ( GET_CODE ( XEXP ( XEXP ( recog_data . operand [ i ] , 0 ) , 1 ) ) == CONST ) ) ) ) ; case 2 : default : return 1 ; } } </s>

Ensure that we are not using patterns that are not OK with PIC .


<s> bool RISCVTargetLowering :: isTruncateFree ( EVT SrcVT , EVT DstVT ) const { if ( Subtarget . is64Bit ( ) || SrcVT . isVector ( ) || DstVT . isVector ( ) || ! SrcVT . isInteger ( ) || ! DstVT . isInteger ( ) ) return false ; unsigned SrcBits = SrcVT . getSizeInBits ( ) ; unsigned DestBits = DstVT . getSizeInBits ( ) ; return ( SrcBits == 64 && DestBits == 32 ) ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s>
static
void
mips_output_function_prologue
(
FILE
*
file
,
HOST_WIDE_INT
size
ATTRIBUTE_UNUSED
)
{
const
char
*
fnname
;
HOST_WIDE_INT
tsize
=
cfun
->
machine
->
frame
.
total_size
;
if
(
debug_info_level
!=
DINFO_LEVEL_TERSE
&&
write_symbols
==
SDB_DEBUG
)
SDB_OUTPUT_SOURCE_LINE
(
file
,
DECL_SOURCE_LINE
(
current_function_decl
)
)
;
if
(
TARGET_MIPS16
&&
!
TARGET_SOFT_FLOAT
&&
current_function_args_info
.
fp_code
!=
0
)
build_mips16_function_stub
(
file
)
;
if
(
!
FUNCTION_NAME_ALREADY_DECLARED
)
{
fnname
=
XSTR
(
XEXP
(
DECL_RTL
(
current_function_decl
)
,
0
)
,
0
)
;
if
(
!
flag_inhibit_size_directive
)
{
fputs
(
"\t.ent\t"
,
file
)
;
assemble_name
(
file
,
fnname
)
;
fputs
(
"\n"
,
file
)
;
}
assemble_name
(
file
,
fnname
)
;
fputs
(
":\n"
,
file
)
;
}
if
(
TARGET_IRIX
&&
mips_abi
==
ABI_32
)
TREE_ASM_WRITTEN
(
DECL_NAME
(
cfun
->
decl
)
)
=
1
;
if
(
!
flag_inhibit_size_directive
)
{
fprintf
(
file
,
"\t.frame\t%s,"
HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
"# vars= "
HOST_WIDE_INT_PRINT_DEC
", regs= %d/%d"
", args= "
HOST_WIDE_INT_PRINT_DEC
", gp= "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
(
reg_names
[
(
frame_pointer_needed
)
HARD_FRAME_POINTER_REGNUM
:
STACK_POINTER_REGNUM
]
)
,
(
(
frame_pointer_needed
&&
TARGET_MIPS16
)
tsize
cfun
->
machine
->
frame
.
args_size
:
tsize
)
,
reg_names
[
GP_REG_FIRST
+
31
]
,
cfun
->
machine
->
frame
.
var_size
,
cfun
->
machine
->
frame
.
num_gp
,
cfun
->
machine
->
frame
.
num_fp
,
cfun
->
machine
->
frame
.
args_size
,
cfun
->
machine
->
frame
.
cprestore_size
)
;
fprintf
(
file
,
"\t.mask\t0x%08x,"
HOST_WIDE_INT_PRINT_DEC
"\n"
,
cfun
->
machine
->
frame
.
mask
,
cfun
->
machine
->
frame
.
gp_save_offset
)
;
fprintf
(
file
,
"\t.fmask\t0x%08x,"
HOST_WIDE_INT_PRINT_DEC
"\n"
,
cfun
->
machine
->
frame
.
fmask
,
cfun
->
machine
->
frame
.
fp_save_offset
)
;
}
if
(
TARGET_ABICALLS
&&
!
TARGET_NEWABI
&&
cfun
->
machine
->
global_pointer
>
0
)
{
if
(
!
cfun
->
machine
->
all_noreorder_p
)
output_asm_insn
(
"%(.cpload\t%^%)"
,
0
)
;
else
output_asm_insn
(
"%(.cpload\t%^\n\t%<"
,
0
)
;
}
else
if
(
cfun
->
machine
->
all_noreorder_p
)
output_asm_insn
(
"%(%<"
,
0
)
;
mips_output_cplocal
(
)
;
}
</s>

Set up the stack and frame ( if desired ) for the function .


<s>
bool
SystemZXPLINKFrameLowering
::
spillCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MBBI
,
ArrayRef
<
CalleeSavedInfo
>
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
if
(
CSI
.
empty
(
)
)
return
true
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
SystemZMachineFunctionInfo
*
ZFI
=
MF
.
getInfo
<
SystemZMachineFunctionInfo
>
(
)
;
const
SystemZSubtarget
&
Subtarget
=
MF
.
getSubtarget
<
SystemZSubtarget
>
(
)
;
const
TargetInstrInfo
*
TII
=
Subtarget
.
getInstrInfo
(
)
;
auto
&
Regs
=
Subtarget
.
getSpecialRegisters
<
SystemZXPLINK64Registers
>
(
)
;
SystemZ
::
GPRRegs
SpillGPRs
=
ZFI
->
getSpillGPRRegs
(
)
;
DebugLoc
DL
;
if
(
SpillGPRs
.
LowGPR
)
{
assert
(
SpillGPRs
.
LowGPR
!=
SpillGPRs
.
HighGPR
&&
"Should be saving multiple registers"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MBBI
,
DL
,
TII
->
get
(
SystemZ
::
STMG
)
)
;
addSavedGPR
(
MBB
,
MIB
,
SpillGPRs
.
LowGPR
,
false
)
;
addSavedGPR
(
MBB
,
MIB
,
SpillGPRs
.
HighGPR
,
false
)
;
MIB
.
addReg
(
Regs
.
getStackPointerRegister
(
)
)
;
MIB
.
addImm
(
SpillGPRs
.
GPROffset
)
;
auto
&
GRRegClass
=
SystemZ
::
GR64BitRegClass
;
for
(
const
CalleeSavedInfo
&
I
:
CSI
)
{
Register
Reg
=
I
.
getReg
(
)
;
if
(
GRRegClass
.
contains
(
Reg
)
)
addSavedGPR
(
MBB
,
MIB
,
Reg
,
true
)
;
}
}
for
(
const
CalleeSavedInfo
&
I
:
CSI
)
{
Register
Reg
=
I
.
getReg
(
)
;
if
(
SystemZ
::
FP64BitRegClass
.
contains
(
Reg
)
)
{
MBB
.
addLiveIn
(
Reg
)
;
TII
->
storeRegToStackSlot
(
MBB
,
MBBI
,
Reg
,
true
,
I
.
getFrameIdx
(
)
,
&
SystemZ
::
FP64BitRegClass
,
TRI
)
;
}
if
(
SystemZ
::
VR128BitRegClass
.
contains
(
Reg
)
)
{
MBB
.
addLiveIn
(
Reg
)
;
TII
->
storeRegToStackSlot
(
MBB
,
MBBI
,
Reg
,
true
,
I
.
getFrameIdx
(
)
,
&
SystemZ
::
VR128BitRegClass
,
TRI
)
;
}
}
return
true
;
}
</s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .

SystemZ
SystemZ
SystemZ
SystemZ
SystemZ
SystemZ
SystemZ
SystemZ::GPRRegs
"Should be saving multiple registers"
SystemZ::STMG
SystemZ::GR64BitRegClass
SystemZ::FP64BitRegClass
SystemZ::FP64BitRegClass
SystemZ::VR128BitRegClass
SystemZ::VR128BitRegClass


<s>
unsigned
getRegisterType
(
unsigned
Reg
)
const
{
if
(
RegInfo
.
count
(
Reg
)
)
return
RegInfo
.
lookup
(
Reg
)
.
Type
;
else
llvm_unreachable
(
"Unknown register"
)
;
}
</s>

Return the type of registers that this ValueType will eventually require .


<s> SDNode * SITargetLowering :: PostISelFolding ( MachineSDNode * Node , SelectionDAG & DAG ) const { const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; if ( TII -> isMIMG ( Node -> getMachineOpcode ( ) ) ) adjustWritemask ( Node , DAG ) ; if ( Node -> getMachineOpcode ( ) == AMDGPU :: INSERT_SUBREG || Node -> getMachineOpcode ( ) == AMDGPU :: REG_SEQUENCE ) { legalizeTargetIndependentNode ( Node , DAG ) ; return Node ; } return Node ; } </s>

Fold the instructions after selecting them .

AMDGPU SI SI SI AMDGPU::INSERT_SUBREG AMDGPU::REG_SEQUENCE


<s> static bool pru_nongeneric_pointer_addrspace ( tree typ ) { while ( ARRAY_TYPE == TREE_CODE ( typ ) ) typ = TREE_TYPE ( typ ) ; if ( POINTER_TYPE_P ( typ ) ) { addr_space_t as ; tree target = TREE_TYPE ( typ ) ; if ( FUNCTION_TYPE == TREE_CODE ( target ) ) return pru_nongeneric_pointer_addrspace ( TREE_TYPE ( target ) ) ; while ( TREE_CODE ( target ) == ARRAY_TYPE ) target = TREE_TYPE ( target ) ; as = TYPE_ADDR_SPACE ( target ) ; if ( ! ADDR_SPACE_GENERIC_P ( as ) ) return true ; return pru_nongeneric_pointer_addrspace ( target ) ; } return false ; } </s>

Scan type TYP for pointer references to address space other than ADDR_SPACE_GENERIC . Return true if such reference is found . Much of this code was taken from the avr port .


<s> bool RISCVRegisterInfo :: isConstantPhysReg ( unsigned PhysReg ) const { return PhysReg == RISCV :: X0 ; } </s>

Returns true if PhysReg is unallocatable and constant throughout the function .


<s> const SparcMCExpr * SparcMCExpr :: create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { return new ( Ctx ) SparcMCExpr ( Kind , Expr ) ; } </s>


<s> bool PPCTargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createPPCBranchSelectionPass ( ) ) ; return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> std :: pair < const TargetRegisterClass * , uint8_t > X86TargetLowering :: findRepresentativeClass ( MVT VT ) const { const TargetRegisterClass * RRC = 0 ; uint8_t Cost = 1 ; switch ( VT . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( VT ) ; case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : case MVT :: i64 : RRC = Subtarget -> is64Bit ( ) ? ( const TargetRegisterClass * ) & X86 :: GR64RegClass : ( const TargetRegisterClass * ) & X86 :: GR32RegClass ; break ; case MVT :: x86mmx : RRC = & X86 :: VR64RegClass ; break ; case MVT :: f32 : case MVT :: f64 : case MVT :: v16i8 : case MVT :: v8i16 : case MVT :: v4i32 : case MVT :: v2i64 : case MVT :: v4f32 : case MVT :: v2f64 : case MVT :: v32i8 : case MVT :: v8i32 : case MVT :: v4i64 : case MVT :: v8f32 : case MVT :: v4f64 : RRC = & X86 :: VR128RegClass ; break ; } return std :: make_pair ( RRC , Cost ) ; } </s>

Return the largest legal super-reg register class of the register class for the specified type and its associated `` cost '' .


<s>
bool
PPCInstrInfo
::
reverseBranchCondition
(
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
assert
(
Cond
.
size
(
)
==
2
&&
"Invalid PPC branch opcode!"
)
;
if
(
Cond
[
1
]
.
getReg
(
)
==
PPC
::
CTR8
||
Cond
[
1
]
.
getReg
(
)
==
PPC
::
CTR
)
Cond
[
0
]
.
setImm
(
Cond
[
0
]
.
getImm
(
)
==
0
1
:
0
)
;
else
Cond
[
0
]
.
setImm
(
PPC
::
InvertPredicate
(
(
PPC
::
Predicate
)
Cond
[
0
]
.
getImm
(
)
)
)
;
return
false
;
}
</s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


"LoongArch didn't implement copyPhysReg"


<s> bool LanaiMemAluCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( DisableMemAluCombiner ) return false ; TII = MF . getSubtarget < LanaiSubtarget > ( ) . getInstrInfo ( ) ; bool Modified = false ; for ( MfIterator MFI = MF . begin ( ) ; MFI != MF . end ( ) ; ++ MFI ) { Modified |= combineMemAluInBasicBlock ( & * MFI ) ; } return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s>
void
WebAssemblyInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
OS
,
StringRef
Annot
,
const
MCSubtargetInfo
&
)
{
printInstruction
(
MI
,
OS
)
;
const
MCInstrDesc
&
Desc
=
MII
.
get
(
MI
->
getOpcode
(
)
)
;
if
(
Desc
.
isVariadic
(
)
)
for
(
auto
i
=
Desc
.
getNumOperands
(
)
,
e
=
MI
->
getNumOperands
(
)
;
i
<
e
;
++
i
)
{
if
(
i
!=
0
)
OS
<<
", "
;
printOperand
(
MI
,
i
,
OS
)
;
}
printAnnotation
(
OS
,
Annot
)
;
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s> bool nds32_can_use_btgl_p ( HOST_WIDE_INT ival ) { int one_bit_count ; unsigned HOST_WIDE_INT mask = GET_MODE_MASK ( SImode ) ; one_bit_count = popcount_hwi ( ( unsigned HOST_WIDE_INT ) ( ival ) & mask ) ; return ( TARGET_EXT_PERF && ( one_bit_count == 1 ) ) ; } </s>

Function to check if 'btgl ' instruction can be used with IVAL .


"Relocation required in an instruction that we cannot encode!"

getMachineOpValue - Return binary encoding of operand .


<s> StringRef getPassName ( ) const override { return PASS_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> bool SIFoldOperands :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; MRI = & MF . getRegInfo ( ) ; ST = & MF . getSubtarget < AMDGPUSubtarget > ( ) ; TII = ST -> getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; const SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; bool IsIEEEMode = ST -> enableIEEEBit ( MF ) || ! MFI -> hasNoSignedZerosFPMath ( ) ; for ( MachineBasicBlock * MBB : depth_first ( & MF ) ) { MachineBasicBlock :: iterator I , Next ; for ( I = MBB -> begin ( ) ; I != MBB -> end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; tryFoldInst ( TII , & MI ) ; if ( ! TII -> isFoldableCopy ( MI ) ) { if ( IsIEEEMode || ! tryFoldOMod ( MI ) ) tryFoldClamp ( MI ) ; continue ; } MachineOperand & OpToFold = MI . getOperand ( 1 ) ; bool FoldingImm = OpToFold . isImm ( ) || OpToFold . isFI ( ) ; if ( ! FoldingImm && ! OpToFold . isReg ( ) ) continue ; if ( OpToFold . isReg ( ) && ! TargetRegisterInfo :: isVirtualRegister ( OpToFold . getReg ( ) ) ) continue ; MachineOperand & Dst = MI . getOperand ( 0 ) ; if ( Dst . isReg ( ) && ! TargetRegisterInfo :: isVirtualRegister ( Dst . getReg ( ) ) ) continue ; foldInstOperand ( MI , OpToFold ) ; } } return false ; } </s>


<s> void * getAdjustedAnalysisPointer ( const void * ID ) override { if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo * ) this ; return this ; } </s>

getAdjustedAnalysisPointer - This method is used when a pass implements an analysis interface through multiple inheritance .


<s> static int get_base_reg ( rtx x ) { tree decl ; int base_reg ; if ( ! flag_pic || microblaze_tls_symbol_p ( x ) ) base_reg = MB_ABI_BASE_REGNUM ; else if ( flag_pic ) base_reg = MB_ABI_PIC_ADDR_REGNUM ; if ( TARGET_XLGPOPT && GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_SMALL_P ( x ) && ( decl = SYMBOL_REF_DECL ( x ) ) != NULL ) { if ( TREE_READONLY ( decl ) ) base_reg = MB_ABI_GPRO_REGNUM ; else base_reg = MB_ABI_GPRW_REGNUM ; } return base_reg ; } </s>

Get the base register for accessing a value from the memory or Symbol ref . Used for MicroBlaze Small Data Area Pointer Optimization .


<s> static void visium_setup_incoming_varargs ( cumulative_args_t pcum_v , const function_arg_info & arg , int * pretend_size ATTRIBUTE_UNUSED , int no_rtl ) { cumulative_args_t local_args_so_far ; CUMULATIVE_ARGS local_copy ; CUMULATIVE_ARGS * locargs ; int gp_saved , fp_saved , size ; local_args_so_far . p = & local_copy ; locargs = get_cumulative_args ( pcum_v ) ; local_args_so_far . magic = CUMULATIVE_ARGS_MAGIC ; local_copy . grcount = locargs -> grcount ; local_copy . frcount = locargs -> frcount ; local_copy . stack_words = locargs -> stack_words ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) ) TARGET_FUNCTION_ARG_ADVANCE ( local_args_so_far , arg ) ; locargs = get_cumulative_args ( local_args_so_far ) ; gp_saved = MAX_ARGS_IN_GP_REGISTERS - locargs -> grcount ; fp_saved = ( TARGET_FPU ? MAX_ARGS_IN_FP_REGISTERS - locargs -> frcount : 0 ) ; size = ( gp_saved * UNITS_PER_WORD ) + ( fp_saved * UNITS_PER_HWFPVALUE ) ; if ( ! no_rtl && size > 0 ) { rtx ptr = force_reg ( Pmode , plus_constant ( Pmode , virtual_incoming_args_rtx , - size ) ) ; if ( gp_saved > 0 ) { rtx mem = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , ptr , fp_saved * UNITS_PER_HWFPVALUE ) ) ; MEM_NOTRAP_P ( mem ) = 1 ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( locargs -> grcount + GP_ARG_FIRST , mem , gp_saved ) ; } if ( fp_saved > 0 ) { rtx mem = gen_rtx_MEM ( BLKmode , ptr ) ; MEM_NOTRAP_P ( mem ) = 1 ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; gcc_assert ( UNITS_PER_WORD == UNITS_PER_HWFPVALUE ) ; move_block_from_reg ( locargs -> frcount + FP_ARG_FIRST , mem , fp_saved ) ; } } visium_reg_parm_save_area_size = size ; } </s>

Store the anonymous register arguments into the stack so that all the arguments appear to have been passed consecutively on the stack .


<s> bool X86TTIImpl :: enableInterleavedAccessVectorization ( ) { return ! ( ST -> isAtom ( ) || ST -> isSLM ( ) ) ; } </s>

Enable matching of interleaved access groups .


<s> bool PPCInstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Cond , unsigned TrueReg , unsigned FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( ! Subtarget . hasISEL ( ) ) return false ; if ( Cond . size ( ) != 2 ) return false ; if ( Cond [ 1 ] . getReg ( ) == PPC :: CTR || Cond [ 1 ] . getReg ( ) == PPC :: CTR8 ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( ! PPC :: GPRCRegClass . hasSubClassEq ( RC ) && ! PPC :: GPRC_NOR0RegClass . hasSubClassEq ( RC ) && ! PPC :: G8RCRegClass . hasSubClassEq ( RC ) && ! PPC :: G8RC_NOX0RegClass . hasSubClassEq ( RC ) ) return false ; CondCycles = 1 ; TrueCycles = 1 ; FalseCycles = 1 ; return true ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> const TargetRegisterClass * GBZ80RegisterInfo :: getCrossCopyRegClass ( const TargetRegisterClass * RC ) const { if ( RC == & GB :: R8_GPRRegClass ) return & GB :: R8RegClass ; else if ( RC == & GB :: R16_HLRegClass || RC == & GB :: R16_BCDERegClass ) return & GB :: R16RegClass ; return RC ; } </s>

getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or from .


<s> static bool is_cracked_insn ( rtx_insn * insn ) { if ( ! insn || ! NONDEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; if ( rs6000_sched_groups && ( rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5 ) ) { enum attr_type type = get_attr_type ( insn ) ; if ( ( type == TYPE_LOAD && get_attr_sign_extend ( insn ) == SIGN_EXTEND_YES && get_attr_update ( insn ) == UPDATE_NO ) || ( type == TYPE_LOAD && get_attr_sign_extend ( insn ) == SIGN_EXTEND_NO && get_attr_update ( insn ) == UPDATE_YES && get_attr_indexed ( insn ) == INDEXED_NO ) || ( type == TYPE_STORE && get_attr_update ( insn ) == UPDATE_YES && get_attr_indexed ( insn ) == INDEXED_NO ) || ( ( type == TYPE_FPLOAD || type == TYPE_FPSTORE ) && get_attr_update ( insn ) == UPDATE_YES ) || type == TYPE_DELAYED_CR || ( type == TYPE_EXTS && get_attr_dot ( insn ) == DOT_YES ) || ( type == TYPE_SHIFT && get_attr_dot ( insn ) == DOT_YES && get_attr_var_shift ( insn ) == VAR_SHIFT_NO ) || ( type == TYPE_MUL && get_attr_dot ( insn ) == DOT_YES ) || type == TYPE_DIV || ( type == TYPE_INSERT && get_attr_size ( insn ) == SIZE_32 ) ) return true ; } return false ; } </s>

The function returns true if INSN is cracked into 2 instructions by the processor ( and therefore occupies 2 issue slots ) .


<s> const TargetRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


"Can only insert epilog into returning blocks"