<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
]
=
{
{
"reloc_pcrel_4byte"
,
0
,
4
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_pcrel_1byte"
,
0
,
1
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte"
,
0
,
4
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_movq_load"
,
0
,
4
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCCodeEmitter
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> void MBlazeRegisterInfo :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = prior ( MBB . end ( ) ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MBlazeFunctionInfo * MBlazeFI = MF . getInfo < MBlazeFunctionInfo > ( ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; int FPOffset = MBlazeFI -> getFPStackOffset ( ) ; int RAOffset = MBlazeFI -> getRAStackOffset ( ) ; if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( MBlaze :: ADD ) , MBlaze :: R1 ) . addReg ( MBlaze :: R19 ) . addReg ( MBlaze :: R0 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( MBlaze :: LWI ) , MBlaze :: R19 ) . addImm ( FPOffset ) . addReg ( MBlaze :: R1 ) ; } if ( MFI -> adjustsStack ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( MBlaze :: LWI ) , MBlaze :: R15 ) . addImm ( RAOffset ) . addReg ( MBlaze :: R1 ) ; } int StackSize = ( int ) MFI -> getStackSize ( ) ; if ( StackSize < 28 && MFI -> adjustsStack ( ) ) StackSize = 28 ; if ( StackSize ) { BuildMI ( MBB , MBBI , dl , TII . get ( MBlaze :: ADDI ) , MBlaze :: R1 ) . addReg ( MBlaze :: R1 ) . addImm ( StackSize ) ; } } </s>


"Return instruction can only reference SP relative frame objects"

"Requesting 64-bit offset in 32-bit immediate!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> void mt_emit_cbranch ( enum rtx_code code , rtx loc , rtx op0 , rtx op1 ) { rtx condition_rtx , loc_ref ; if ( ! reg_or_0_operand ( op0 , SImode ) ) op0 = copy_to_mode_reg ( SImode , op0 ) ; if ( ! reg_or_0_operand ( op1 , SImode ) ) op1 = copy_to_mode_reg ( SImode , op1 ) ; condition_rtx = mt_generate_compare ( code , op0 , op1 ) ; loc_ref = gen_rtx_LABEL_REF ( VOIDmode , loc ) ; emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , condition_rtx , loc_ref , pc_rtx ) ) ) ; } </s>

Emit a branch of kind CODE to location LOC .


<s> static bool ix86_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( CC_REGNO_P ( regno ) ) return GET_MODE_CLASS ( mode ) == MODE_CC ; if ( GET_MODE_CLASS ( mode ) == MODE_CC || GET_MODE_CLASS ( mode ) == MODE_RANDOM || GET_MODE_CLASS ( mode ) == MODE_PARTIAL_INT ) return false ; if ( STACK_REGNO_P ( regno ) ) return VALID_FP_MODE_P ( mode ) ; if ( MASK_REGNO_P ( regno ) ) return ( VALID_MASK_REG_MODE ( mode ) || ( TARGET_AVX512BW && VALID_MASK_AVX512BW_MODE ( mode ) ) ) ; if ( SSE_REGNO_P ( regno ) ) { if ( TARGET_AVX512F && ( mode == XImode || VALID_AVX512F_REG_MODE ( mode ) || VALID_AVX512F_SCALAR_MODE ( mode ) ) ) return true ; if ( ( TARGET_AVX5124FMAPS || TARGET_AVX5124VNNIW ) && ( mode == V64SFmode || mode == V64SImode ) && MOD4_SSE_REGNO_P ( regno ) ) return true ; if ( TARGET_AVX512VL && ( mode == OImode || mode == TImode || VALID_AVX256_REG_MODE ( mode ) || VALID_AVX512VL_128_REG_MODE ( mode ) ) ) return true ; if ( EXT_REX_SSE_REGNO_P ( regno ) ) return false ; return ( ( TARGET_AVX && VALID_AVX256_REG_OR_OI_MODE ( mode ) ) || VALID_SSE_REG_MODE ( mode ) || VALID_SSE2_REG_MODE ( mode ) || VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( MMX_REGNO_P ( regno ) ) { return ( VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( mode == QImode ) { if ( ANY_QI_REGNO_P ( regno ) ) return true ; if ( ! TARGET_PARTIAL_REG_STALL ) return true ; if ( lra_in_progress ) return true ; return ! can_create_pseudo_p ( ) ; } else if ( VALID_INT_MODE_P ( mode ) ) return true ; else if ( VALID_FP_MODE_P ( mode ) ) return true ; else if ( VALID_DFP_MODE_P ( mode ) ) return true ; else if ( VALID_MMX_REG_MODE_3DNOW ( mode ) || VALID_MMX_REG_MODE ( mode ) ) return true ; return false ; } </s>

Return TRUE if hard register REGNO can hold a value of machine-mode MODE .


<s> static void ix86_emit_save_regs ( void ) { unsigned int regno ; rtx insn ; for ( regno = FIRST_PSEUDO_REGISTER - 1 ; regno -- > 0 ; ) if ( ! SSE_REGNO_P ( regno ) && ix86_save_reg ( regno , true ) ) { insn = emit_insn ( gen_push ( gen_rtx_REG ( word_mode , regno ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } </s>

Emit code to save registers in the prologue .


<s> rtx m68k_legitimize_tls_address ( rtx orig ) { switch ( SYMBOL_REF_TLS_MODEL ( orig ) ) { case TLS_MODEL_GLOBAL_DYNAMIC : orig = m68k_call_tls_get_addr ( orig , orig , RELOC_TLSGD ) ; break ; case TLS_MODEL_LOCAL_DYNAMIC : { rtx eqv ; rtx a0 ; rtx x ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , const0_rtx ) , UNSPEC_RELOC32 ) ; a0 = m68k_call_tls_get_addr ( orig , eqv , RELOC_TLSLDM ) ; x = m68k_wrap_symbol ( orig , RELOC_TLSLDO , a0 , NULL_RTX ) ; if ( can_create_pseudo_p ( ) ) x = m68k_move_to_reg ( x , orig , NULL_RTX ) ; orig = x ; break ; } case TLS_MODEL_INITIAL_EXEC : { rtx a0 ; rtx x ; a0 = m68k_call_m68k_read_tp ( ) ; x = m68k_wrap_symbol_into_got_ref ( orig , RELOC_TLSIE , NULL_RTX ) ; x = gen_rtx_PLUS ( Pmode , x , a0 ) ; if ( can_create_pseudo_p ( ) ) x = m68k_move_to_reg ( x , orig , NULL_RTX ) ; orig = x ; break ; } case TLS_MODEL_LOCAL_EXEC : { rtx a0 ; rtx x ; a0 = m68k_call_m68k_read_tp ( ) ; x = m68k_wrap_symbol ( orig , RELOC_TLSLE , a0 , NULL_RTX ) ; if ( can_create_pseudo_p ( ) ) x = m68k_move_to_reg ( x , orig , NULL_RTX ) ; orig = x ; break ; } default : gcc_unreachable ( ) ; } return orig ; } </s>

Return a legitimized address for accessing TLS SYMBOL_REF X . For explanations on instructions sequences see TLS/NPTL ABI for m68k and ColdFire .


<s> bool HexagonTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { switch ( Intrinsic ) { case Intrinsic :: hexagon_V6_vgathermw : case Intrinsic :: hexagon_V6_vgathermw_128B : case Intrinsic :: hexagon_V6_vgathermh : case Intrinsic :: hexagon_V6_vgathermh_128B : case Intrinsic :: hexagon_V6_vgathermhw : case Intrinsic :: hexagon_V6_vgathermhw_128B : case Intrinsic :: hexagon_V6_vgathermwq : case Intrinsic :: hexagon_V6_vgathermwq_128B : case Intrinsic :: hexagon_V6_vgathermhq : case Intrinsic :: hexagon_V6_vgathermhq_128B : case Intrinsic :: hexagon_V6_vgathermhwq : case Intrinsic :: hexagon_V6_vgathermhwq_128B : { const Module & M = * I . getParent ( ) -> getParent ( ) -> getParent ( ) ; Info . opc = ISD :: INTRINSIC_W_CHAIN ; Type * VecTy = I . getArgOperand ( 1 ) -> getType ( ) ; Info . memVT = MVT :: getVT ( VecTy ) ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . align = M . getDataLayout ( ) . getTypeAllocSizeInBits ( VecTy ) / 8 ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; } default : break ; } return false ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> MachineBasicBlock * SITargetLowering :: EmitInstrWithCustomInserter ( MachineInstr * MI , MachineBasicBlock * BB ) const { MachineBasicBlock :: iterator I = * MI ; const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; switch ( MI -> getOpcode ( ) ) { default : return AMDGPUTargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; case AMDGPU :: BRANCH : return BB ; case AMDGPU :: V_SUB_F64 : { unsigned DestReg = MI -> getOperand ( 0 ) . getReg ( ) ; BuildMI ( * BB , I , MI -> getDebugLoc ( ) , TII -> get ( AMDGPU :: V_ADD_F64 ) , DestReg ) . addImm ( 0 ) . addReg ( MI -> getOperand ( 1 ) . getReg ( ) ) . addImm ( 1 ) . addReg ( MI -> getOperand ( 2 ) . getReg ( ) ) . addImm ( 0 ) . addImm ( 0 ) ; MI -> eraseFromParent ( ) ; break ; } case AMDGPU :: SI_RegisterStorePseudo : { MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; unsigned Reg = MRI . createVirtualRegister ( & AMDGPU :: SReg_64RegClass ) ; MachineInstrBuilder MIB = BuildMI ( * BB , I , MI -> getDebugLoc ( ) , TII -> get ( AMDGPU :: SI_RegisterStore ) , Reg ) ; for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) MIB . addOperand ( MI -> getOperand ( i ) ) ; MI -> eraseFromParent ( ) ; break ; } } return BB ; } </s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> unsigned X86InstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( isFrameLoadOpcode ( MI . getOpcode ( ) ) ) if ( MI . getOperand ( 0 ) . getSubReg ( ) == 0 && isFrameOperand ( MI , 1 , FrameIndex ) ) return MI . getOperand ( 0 ) . getReg ( ) ; return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> bool ARMFastISel :: isTypeLegal ( const Type * Ty , EVT & VT ) { VT = TLI . getValueType ( Ty , true ) ; if ( VT == MVT :: Other || ! VT . isSimple ( ) ) return false ; return TLI . isTypeLegal ( VT ) ; } </s>


<s> static unsigned int pa_function_arg_boundary ( machine_mode mode , const_tree type ) { bool singleword = ( type ? ( integer_zerop ( TYPE_SIZE ( type ) ) || ! TREE_CONSTANT ( TYPE_SIZE ( type ) ) || int_size_in_bytes ( type ) <= UNITS_PER_WORD ) : GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD ) ; return singleword ? PARM_BOUNDARY : MAX_PARM_BOUNDARY ; } </s>

Arguments larger than one word are double word aligned .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"OR1K Delay Slot Filler"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool X86TargetLowering :: shouldFoldMaskToVariableShiftPair ( SDValue Y ) const { EVT VT = Y . getValueType ( ) ; if ( VT . isVector ( ) ) return false ; if ( VT == MVT :: i64 && ! Subtarget . is64Bit ( ) ) return false ; return true ; } </s>

There are two ways to clear extreme bits ( either low or high ) : Mask : x & ( -1 < < y ) ( the instcombine canonical form ) Shifts : x > > y < < y Return true if the variant with 2 variable shifts is preferred .


<s> X86Subtarget :: X86Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const X86TargetMachine & TM , unsigned StackAlignOverride ) : X86GenSubtargetInfo ( TT , CPU , FS ) , X86ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TM ( TM ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , TSInfo ( ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( * this , getStackAlignment ( ) ) { if ( TM . getRelocationModel ( ) == Reloc :: Static ) { setPICStyle ( PICStyles :: None ) ; } else if ( is64Bit ( ) ) { setPICStyle ( PICStyles :: RIPRel ) ; } else if ( isTargetCOFF ( ) ) { setPICStyle ( PICStyles :: None ) ; } else if ( isTargetDarwin ( ) ) { if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( TM . getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( isTargetELF ( ) ) { setPICStyle ( PICStyles :: GOT ) ; } } </s>

This constructor initializes the data members to match that of the specified triple .


<s> std :: unique_ptr < CSEConfigBase > X86PassConfig :: getCSEConfig ( ) const { return getStandardCSEConfigForOpt ( TM -> getOptLevel ( ) ) ; } </s>

Returns the CSEConfig object to use for the current optimization level .


<s> void HexagonFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { auto & HRI = * MF . getSubtarget < HexagonSubtarget > ( ) . getRegisterInfo ( ) ; SavedRegs . resize ( HRI . getNumRegs ( ) ) ; if ( MF . getInfo < HexagonMachineFunctionInfo > ( ) -> hasEHReturn ( ) ) for ( const MCPhysReg * R = HRI . getCalleeSavedRegs ( & MF ) ; * R ; ++ R ) SavedRegs . set ( * R ) ; SmallVector < unsigned , 8 > NewRegs ; expandSpillMacros ( MF , NewRegs ) ; if ( OptimizeSpillSlots && ! isOptNone ( MF ) ) optimizeSpillSlots ( MF , NewRegs ) ; if ( ! NewRegs . empty ( ) || mayOverflowFrameOffset ( MF ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; SetVector < const TargetRegisterClass * > SpillRCs ; SpillRCs . insert ( & Hexagon :: IntRegsRegClass ) ; for ( unsigned VR : NewRegs ) SpillRCs . insert ( MRI . getRegClass ( VR ) ) ; for ( auto * RC : SpillRCs ) { if ( ! needToReserveScavengingSpillSlots ( MF , HRI , RC ) ) continue ; unsigned Num = RC == & Hexagon :: IntRegsRegClass ? NumberScavengerSlots : 1 ; unsigned S = HRI . getSpillSize ( * RC ) , A = HRI . getSpillAlignment ( * RC ) ; for ( unsigned i = 0 ; i < Num ; i ++ ) { int NewFI = MFI . CreateSpillStackObject ( S , A ) ; RS -> addScavengingFrameIndex ( NewFI ) ; } } } TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .

Hexagon Hexagon Hexagon Hexagon 8 Hexagon::IntRegsRegClass Hexagon::IntRegsRegClass 1 0


"This resolveFrameIndex does not support Thumb1!"

"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> M68kTargetLowering :: ConstraintType M68kTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) > 0 ) { switch ( Constraint [ 0 ] ) { case 'a' : case 'd' : return C_RegisterClass ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'O' : case 'P' : return C_Immediate ; case 'C' : if ( Constraint . size ( ) == 2 ) switch ( Constraint [ 1 ] ) { case '0' : case 'i' : case 'j' : return C_Immediate ; default : break ; } break ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> bool X86ATTAsmPrinter :: doInitialization ( Module & M ) { bool Result = AsmPrinter :: doInitialization ( M ) ; if ( TAI -> doesSupportDebugInformation ( ) ) { MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; DW = getAnalysisIfAvailable < DwarfWriter > ( ) ; DW -> BeginModule ( & M , MMI , O , this , TAI ) ; } if ( Subtarget -> isTargetDarwin ( ) ) Mang -> setUseQuotes ( true ) ; return Result ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> const SystemZRegisterInfo * getRegisterInfo ( ) const override { return getSubtargetImpl ( ) -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void PPCFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const PPCRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; PPCFunctionInfo * FI = MF . getInfo < PPCFunctionInfo > ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; SavedRegs . reset ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; bool isPPC64 = Subtarget . isPPC64 ( ) ; bool isDarwinABI = Subtarget . isDarwinABI ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( ) ; FPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int BPSI = FI -> getBasePointerSaveIndex ( ) ; if ( ! BPSI && RegInfo -> hasBasePointer ( MF ) ) { int BPOffset = getBasePointerSaveOffset ( ) ; BPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , BPOffset , true ) ; FI -> setBasePointerSaveIndex ( BPSI ) ; } if ( FI -> usesPICBase ( ) ) { int PBPSI = MFI . CreateFixedObject ( 4 , - 8 , true ) ; FI -> setPICBasePointerSaveIndex ( PBPSI ) ; } if ( needsFP ( MF ) ) SavedRegs . reset ( isPPC64 ? PPC :: X31 : PPC :: R31 ) ; if ( RegInfo -> hasBasePointer ( MF ) ) SavedRegs . reset ( RegInfo -> getBaseRegister ( MF ) ) ; if ( FI -> usesPICBase ( ) ) SavedRegs . reset ( PPC :: R30 ) ; int TCSPDelta = 0 ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < 0 ) { MFI . CreateFixedObject ( - 1 * TCSPDelta , TCSPDelta , true ) ; } if ( ! isPPC64 && ! isDarwinABI && ( SavedRegs . test ( PPC :: CR2 ) || SavedRegs . test ( PPC :: CR3 ) || SavedRegs . test ( PPC :: CR4 ) ) ) { int FrameIdx = MFI . CreateFixedObject ( ( uint64_t ) 4 , ( int64_t ) - 4 , true ) ; FI -> setCRSpillFrameIndex ( FrameIdx ) ; } } </s>


<s> const MCExpr * getSubExpr ( ) const { return Expr ; } </s>

getSubExpr - Get the child of this expression .


<s> void MipsPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) == CodeGenOpt :: None ) addPass ( createMipsOptimizePICCallPass ( getMipsTargetMachine ( ) ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> rtx rs6000_gen_le_vsx_permute ( rtx source , machine_mode mode ) { if ( FLOAT128_VECTOR_P ( mode ) || mode == TImode || mode == V1TImode ) return gen_rtx_ROTATE ( mode , source , GEN_INT ( 64 ) ) ; else { rtx par = gen_rtx_PARALLEL ( VOIDmode , rs6000_const_vec ( mode ) ) ; return gen_rtx_VEC_SELECT ( mode , source , par ) ; } } </s>

Generate a permute rtx that represents an lxvd2x , stxvd2x , or xxpermdi for a VSX load or store operation .


<s> static unsigned int nios2_section_type_flags ( tree decl , const char * name , int reloc ) { unsigned int flags ; flags = default_section_type_flags ( decl , name , reloc ) ; if ( nios2_small_section_name_p ( name ) ) flags |= SECTION_SMALL ; return flags ; } </s>


Emit target-specific code that performs a memcpy .


<s> static bool mips_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { return mips_hard_regno_mode_ok_p [ mode ] [ regno ] ; } </s>


<s> void Mips16FrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( STI . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( StackSize == 0 && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; MachineLocation DstML , SrcML ; TII . makeFrame ( Mips :: SP , StackSize , MBB , MBBI ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - StackSize ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . size ( ) ) { const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; unsigned DReg = MRI -> getDwarfRegNum ( Reg , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DReg , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: MoveR3216 ) , Mips :: S0 ) . addReg ( Mips :: SP ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Mips Mips Mips Mips 0 Mips::SP Mips::MoveR3216 Mips::S0 Mips::SP


<s> void frv_expand_prologue ( void ) { frv_stack_t * info = frv_stack_info ( ) ; rtx sp = stack_pointer_rtx ; rtx fp = frame_pointer_rtx ; frv_frame_accessor_t accessor ; if ( TARGET_DEBUG_STACK ) frv_debug_stack ( info ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = info -> total_size ; if ( info -> total_size == 0 ) return ; accessor . op = FRV_STORE ; if ( frame_pointer_needed && info -> total_size > 2048 ) { accessor . base = gen_rtx_REG ( Pmode , OLD_SP_REGNO ) ; accessor . base_offset = info -> total_size ; emit_insn ( gen_movsi ( accessor . base , sp ) ) ; } else { accessor . base = stack_pointer_rtx ; accessor . base_offset = 0 ; } { rtx asm_offset = frv_frame_offset_rtx ( - info -> total_size ) ; rtx dwarf_offset = GEN_INT ( - info -> total_size ) ; frv_frame_insn ( gen_stack_adjust ( sp , sp , asm_offset ) , gen_rtx_SET ( Pmode , sp , gen_rtx_PLUS ( Pmode , sp , dwarf_offset ) ) ) ; } if ( frame_pointer_needed ) { int fp_offset = info -> reg_offset [ FRAME_POINTER_REGNUM ] ; rtx asm_src = plus_constant ( Pmode , accessor . base , fp_offset - accessor . base_offset ) ; rtx dwarf_src = plus_constant ( Pmode , sp , fp_offset ) ; frv_frame_access ( & accessor , fp , fp_offset ) ; frv_frame_insn ( gen_rtx_SET ( VOIDmode , fp , asm_src ) , gen_rtx_SET ( VOIDmode , fp , dwarf_src ) ) ; accessor . base = fp ; accessor . base_offset = fp_offset ; } frv_frame_access_multi ( & accessor , info , STACK_REGS_STRUCT ) ; frv_frame_access_multi ( & accessor , info , STACK_REGS_LR ) ; frv_frame_access_multi ( & accessor , info , STACK_REGS_STDARG ) ; frv_frame_access_standard_regs ( FRV_STORE , info ) ; if ( info -> stdarg_size > 0 ) emit_insn ( gen_blockage ( ) ) ; if ( ! TARGET_FDPIC && flag_pic && crtl -> uses_pic_offset_table ) emit_insn ( gen_pic_prologue ( gen_rtx_REG ( Pmode , PIC_REGNO ) , gen_rtx_REG ( Pmode , LR_REGNO ) , gen_rtx_REG ( SImode , OFFSET_REGNO ) ) ) ; } </s>

Called after register allocation to add any instructions needed for the prologue . Using a prologue insn is favored compared to putting all of the instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook , since it allows the scheduler to intermix instructions with the saves of the caller saved registers . In some cases , it might be necessary to emit a barrier instruction as the last insn to prevent such scheduling . Also any insns generated here should have RTX_FRAME_RELATED_P ( insn ) = 1 so that the debug info generation code can handle them properly .


<s> rtx alpha_expand_zap_mask ( HOST_WIDE_INT value ) { rtx result ; int i ; if ( HOST_BITS_PER_WIDE_INT >= 64 ) { HOST_WIDE_INT mask = 0 ; for ( i = 7 ; i >= 0 ; -- i ) { mask <<= 8 ; if ( ! ( ( value >> i ) & 1 ) ) mask |= 0xff ; } result = gen_int_mode ( mask , DImode ) ; } else { HOST_WIDE_INT mask_lo = 0 , mask_hi = 0 ; gcc_assert ( HOST_BITS_PER_WIDE_INT == 32 ) ; for ( i = 7 ; i >= 4 ; -- i ) { mask_hi <<= 8 ; if ( ! ( ( value >> i ) & 1 ) ) mask_hi |= 0xff ; } for ( i = 3 ; i >= 0 ; -- i ) { mask_lo <<= 8 ; if ( ! ( ( value >> i ) & 1 ) ) mask_lo |= 0xff ; } result = immed_double_const ( mask_lo , mask_hi , DImode ) ; } return result ; } </s>

Returns a mask so that zap ( x , value ) == x & mask .


<s> static void rs6000_emit_probe_stack_range ( HOST_WIDE_INT first , HOST_WIDE_INT size ) { if ( first + size <= 32768 ) { HOST_WIDE_INT i ; for ( i = PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + i ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + size ) ) ) ; } else { HOST_WIDE_INT rounded_size ; rtx r12 = gen_rtx_REG ( Pmode , 12 ) ; rtx r0 = gen_rtx_REG ( Pmode , 0 ) ; gcc_assert ( first <= 32768 ) ; rounded_size = ROUND_DOWN ( size , PROBE_INTERVAL ) ; emit_insn ( gen_rtx_SET ( r12 , plus_constant ( Pmode , stack_pointer_rtx , - first ) ) ) ; if ( rounded_size > 32768 ) { emit_move_insn ( r0 , GEN_INT ( - rounded_size ) ) ; emit_insn ( gen_rtx_SET ( r0 , gen_rtx_PLUS ( Pmode , r12 , r0 ) ) ) ; } else emit_insn ( gen_rtx_SET ( r0 , plus_constant ( Pmode , r12 , - rounded_size ) ) ) ; if ( TARGET_64BIT ) emit_insn ( gen_probe_stack_rangedi ( r12 , r12 , r0 ) ) ; else emit_insn ( gen_probe_stack_rangesi ( r12 , r12 , r0 ) ) ; if ( size != rounded_size ) emit_stack_probe ( plus_constant ( Pmode , r12 , rounded_size - size ) ) ; } } </s>

Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE , inclusive . These are offsets from the current stack pointer .


<s> bool ARMSubtarget :: ignoreCSRForAllocationOrder ( const MachineFunction & MF , unsigned PhysReg ) const { return isThumb2 ( ) && MF . getFunction ( ) . hasMinSize ( ) && ARM :: GPRRegClass . contains ( PhysReg ) ; } </s>

True if the register allocator should use the allocation orders exactly as written in the tablegen descriptions , false if it should allocate the specified physical register later if is it callee-saved .


<s> static int iamcu_alignment ( tree type , int align ) { machine_mode mode ; if ( align < 32 || TYPE_USER_ALIGN ( type ) ) return align ; type = strip_array_types ( type ) ; if ( TYPE_ATOMIC ( type ) ) return align ; mode = TYPE_MODE ( type ) ; switch ( GET_MODE_CLASS ( mode ) ) { case MODE_INT : case MODE_COMPLEX_INT : case MODE_COMPLEX_FLOAT : case MODE_FLOAT : case MODE_DECIMAL_FLOAT : return 32 ; default : return align ; } } </s>

Compute the alignment for a variable for Intel MCU psABI . TYPE is the data type , and ALIGN is the alignment that the object would ordinarily have .


<s> bool AArch64PassConfig :: addPostRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableDeadRegisterElimination ) addPass ( createAArch64DeadRegisterDefinitions ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && ( TM -> getSubtarget < AArch64Subtarget > ( ) . isCortexA53 ( ) || TM -> getSubtarget < AArch64Subtarget > ( ) . isCortexA57 ( ) ) && usingDefaultRegAlloc ( ) ) addPass ( createAArch64A57FPLoadBalancing ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> bool AArch64TargetLowering :: isLegalInterleavedAccessType ( VectorType * VecTy , const DataLayout & DL , bool & UseScalable ) const { unsigned VecSize = DL . getTypeSizeInBits ( VecTy ) ; unsigned ElSize = DL . getTypeSizeInBits ( VecTy -> getElementType ( ) ) ; unsigned NumElements = cast < FixedVectorType > ( VecTy ) -> getNumElements ( ) ; UseScalable = false ; if ( NumElements < 2 ) return false ; if ( ElSize != 8 && ElSize != 16 && ElSize != 32 && ElSize != 64 ) return false ; if ( Subtarget -> useSVEForFixedLengthVectors ( ) && ( VecSize % Subtarget -> getMinSVEVectorSizeInBits ( ) == 0 || ( VecSize < Subtarget -> getMinSVEVectorSizeInBits ( ) && isPowerOf2_32 ( NumElements ) && VecSize > 128 ) ) ) { UseScalable = true ; return true ; } return VecSize == 64 || VecSize % 128 == 0 ; } </s>

Returns whether or not generating a interleaved load/store intrinsic for this type will be legal .


<s> unsigned X86FastISel :: fastMaterializeFloatZero ( const ConstantFP * CF ) { MVT VT ; if ( ! isTypeLegal ( CF -> getType ( ) , VT ) ) return 0 ; bool HasAVX512 = Subtarget -> hasAVX512 ( ) ; unsigned Opc = 0 ; switch ( VT . SimpleTy ) { default : return 0 ; case MVT :: f32 : if ( X86ScalarSSEf32 ) Opc = HasAVX512 ? X86 :: AVX512_FsFLD0SS : X86 :: FsFLD0SS ; else Opc = X86 :: LD_Fp032 ; break ; case MVT :: f64 : if ( X86ScalarSSEf64 ) Opc = HasAVX512 ? X86 :: AVX512_FsFLD0SD : X86 :: FsFLD0SD ; else Opc = X86 :: LD_Fp064 ; break ; case MVT :: f80 : return 0 ; } Register ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; return ResultReg ; } </s>

Emit the floating-point constant +0.0 in a register using target- specific logic .


<s> static struct machine_function * ix86_init_machine_status ( void ) { struct machine_function * f ; f = ggc_cleared_alloc < machine_function > ( ) ; f -> call_abi = ix86_abi ; f -> stack_frame_required = true ; f -> silent_p = true ; return f ; } </s>

Clear stack slot assignments remembered from previous functions . This is called from INIT_EXPANDERS once before RTL is emitted for each function .


<s> bool AArch64RegisterInfo :: requiresVirtualBaseRegisters ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers used for more efficient stack access .


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
break
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

ARM
ARM
"Don't know how to custom expand this!"
ISD::BITCAST
ISD::SRL
ISD::SRA


<s> static rtx frv_expand_mdpackh_builtin ( tree arglist , rtx target ) { enum insn_code icode = CODE_FOR_mdpackh ; rtx pat , op0 , op1 ; rtx arg1 = frv_read_argument ( & arglist ) ; rtx arg2 = frv_read_argument ( & arglist ) ; rtx arg3 = frv_read_argument ( & arglist ) ; rtx arg4 = frv_read_argument ( & arglist ) ; target = frv_legitimize_target ( icode , target ) ; op0 = gen_reg_rtx ( DImode ) ; op1 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_rtx_CLOBBER ( DImode , op0 ) ) ; emit_insn ( gen_rtx_CLOBBER ( DImode , op1 ) ) ; emit_move_insn ( simplify_gen_subreg ( HImode , op0 , DImode , 2 ) , arg1 ) ; emit_move_insn ( simplify_gen_subreg ( HImode , op0 , DImode , 6 ) , arg2 ) ; emit_move_insn ( simplify_gen_subreg ( HImode , op1 , DImode , 2 ) , arg3 ) ; emit_move_insn ( simplify_gen_subreg ( HImode , op1 , DImode , 6 ) , arg4 ) ; pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return target ; } </s>

Expand the MDPACKH builtin . It takes four unsigned short arguments and each argument forms one word of the two double-word input registers . ARGLIST is a TREE_LIST of the arguments and TARGET , if nonnull , suggests a good place to put the return value .


"Thumb2 instruction size reduction pass"

getPassName - Return a nice clean name for a pass .


<s> void PPCTTI :: getUnrollingPreferences ( Loop * L , UnrollingPreferences & UP ) const { if ( ST -> getDarwinDirective ( ) == PPC :: DIR_A2 ) { UP . Partial = UP . Runtime = true ; } } </s>

Get target-customized preferences for the generic loop unrolling transformation .


"****** PTX FUNCTION LOCAL VAR REG DEF ******\n"

runOnMachineFunction - Emit the function body .


<s> bool sh_split_movrt_negc_to_movt_xor ( rtx_insn * curr_insn , rtx operands [ ] ) { if ( ! can_create_pseudo_p ( ) ) return false ; set_of_reg t_before_negc = sh_find_set_of_reg ( get_t_reg_rtx ( ) , curr_insn , prev_nonnote_nondebug_insn_bb ) ; set_of_reg t_after_negc = sh_find_set_of_reg ( get_t_reg_rtx ( ) , curr_insn , next_nonnote_nondebug_insn_bb ) ; if ( t_before_negc . set_rtx != NULL_RTX && t_after_negc . set_rtx != NULL_RTX && rtx_equal_p ( t_before_negc . set_rtx , t_after_negc . set_rtx ) && ! reg_used_between_p ( get_t_reg_rtx ( ) , curr_insn , t_after_negc . insn ) && ! sh_insn_operands_modified_between_p ( t_before_negc . insn , t_before_negc . insn , t_after_negc . insn ) && ! modified_between_p ( get_t_reg_rtx ( ) , curr_insn , t_after_negc . insn ) && ! sh_unspec_insn_p ( t_after_negc . insn ) && ! volatile_insn_p ( PATTERN ( t_after_negc . insn ) ) && ! side_effects_p ( PATTERN ( t_after_negc . insn ) ) && ! may_trap_or_fault_p ( PATTERN ( t_after_negc . insn ) ) ) { emit_insn ( gen_movrt_xor ( operands [ 0 ] , get_t_reg_rtx ( ) ) ) ; set_insn_deleted ( t_after_negc . insn ) ; return true ; } else return false ; } </s>

Given the current insn , which is assumed to be a movrt_negc insn , try to figure out whether it should be converted into a movt-xor sequence in the movrt_negc splitter . Returns true if insns have been modified and the splitter has succeeded .


<s> static int arm_issue_rate ( void ) { return current_tune -> issue_rate ; } </s>

Most ARM cores are single issue , but some newer ones can dual issue . The scheduler descriptions rely on this being correct .


<s> void MipsAsmPrinter :: emitFrameDirective ( ) { const TargetRegisterInfo & RI = * MF -> getSubtarget ( ) . getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) . getStackSize ( ) ; getTargetStreamer ( ) . emitFrame ( stackReg , stackSize , returnReg ) ; } </s>


<s> void M680x0InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { if ( ! printAliasInstr ( MI , O ) ) { printInstruction ( MI , O ) ; } printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> int csky_memory_move_cost ( machine_mode mode , reg_class_t rclass , bool in ) { return ( 4 + memory_move_secondary_cost ( mode , rclass , in ) ) ; } </s>

Implement TARGET_MEMORY_MOVE_COST : compute the cost of moving data between registers and memory .


<s> bool ARCTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { return AM . Scale == 0 ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> const TargetRegisterClass * Mips16RegisterInfo :: intRegClass ( unsigned Size ) const { assert ( Size == 4 ) ; return & Mips :: CPU16RegsRegClass ; } </s>


<s>
StringRef
RISCVMCExpr
::
getVariantKindName
(
VariantKind
Kind
)
{
switch
(
Kind
)
{
default
:
llvm_unreachable
(
"Invalid ELF symbol kind"
)
;
case
VK_RISCV_LO
:
return
"lo"
;
case
VK_RISCV_HI
:
return
"hi"
;
case
VK_RISCV_PCREL_LO
:
return
"pcrel_lo"
;
case
VK_RISCV_PCREL_HI
:
return
"pcrel_hi"
;
case
VK_RISCV_GOT_HI
:
return
"got_pcrel_hi"
;
case
VK_RISCV_TPREL_LO
:
return
"tprel_lo"
;
case
VK_RISCV_TPREL_HI
:
return
"tprel_hi"
;
case
VK_RISCV_TPREL_ADD
:
return
"tprel_add"
;
case
VK_RISCV_TLS_GOT_HI
:
return
"tls_ie_pcrel_hi"
;
case
VK_RISCV_TLS_GD_HI
:
return
"tls_gd_pcrel_hi"
;
}
}
</s>

Convert the variant kind into an ELF-appropriate modifier ( e.g .


<s> static HOST_WIDE_INT aarch64_clamp_to_uimm12_shift ( HOST_WIDE_INT val ) { gcc_assert ( ( val & 0xffffff ) == val ) ; if ( ( ( val & 0xfff ) << 0 ) == val ) return val ; return val & ( 0xfff << 12 ) ; } </s>

Returns the nearest value to VAL that will fit as a 12-bit unsigned immediate that can be created with a left shift of 0 or 12 .


<s> void ARMBaseRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , Register BaseReg , int FrameIdx , int64_t Offset ) const { ARMFunctionInfo * AFI = MBB -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? ARM :: ADDri : ( AFI -> isThumb1OnlyFunction ( ) ? ARM :: tADDframe : ARM :: t2ADDri ) ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , 0 , this , MF ) ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ; if ( ! AFI -> isThumb1OnlyFunction ( ) ) MIB . add ( predOps ( ARMCC :: AL ) ) . add ( condCodeOp ( ) ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .

ARM ARM ARM ARM ARM::ADDri ARM::tADDframe ARM::t2ADDri 0 ARMCC::AL


<s> void alpha_split_atomic_op ( enum rtx_code code , rtx mem , rtx val , rtx before , rtx after , rtx scratch , enum memmodel model ) { machine_mode mode = GET_MODE ( mem ) ; rtx label , x , cond = gen_rtx_REG ( DImode , REGNO ( scratch ) ) ; alpha_pre_atomic_barrier ( model ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; label = gen_rtx_LABEL_REF ( DImode , label ) ; if ( before == NULL ) before = scratch ; emit_insn ( gen_load_locked ( mode , before , mem ) ) ; if ( code == NOT ) { x = gen_rtx_AND ( mode , before , val ) ; emit_insn ( gen_rtx_SET ( val , x ) ) ; x = gen_rtx_NOT ( mode , val ) ; } else x = gen_rtx_fmt_ee ( code , mode , before , val ) ; if ( after ) emit_insn ( gen_rtx_SET ( after , copy_rtx ( x ) ) ) ; emit_insn ( gen_rtx_SET ( scratch , x ) ) ; emit_insn ( gen_store_conditional ( mode , cond , mem , scratch ) ) ; x = gen_rtx_EQ ( DImode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label ) ; alpha_post_atomic_barrier ( model ) ; } </s>

Expand an an atomic fetch-and-operate pattern . CODE is the binary operation to perform . MEM is the memory on which to operate . VAL is the second operand of the binary operator . BEFORE and AFTER are optional locations to return the value of MEM either before of after the operation . SCRATCH is a scratch register .


<s> static rtx emit_insxl ( machine_mode mode , rtx op1 , rtx op2 ) { rtx ret = gen_reg_rtx ( DImode ) ; rtx ( * fn ) ( rtx , rtx , rtx ) ; switch ( mode ) { case QImode : fn = gen_insbl ; break ; case HImode : fn = gen_inswl ; break ; case SImode : fn = gen_insll ; break ; case DImode : fn = gen_insql ; break ; default : gcc_unreachable ( ) ; } op1 = force_reg ( mode , op1 ) ; emit_insn ( fn ( ret , op1 , op2 ) ) ; return ret ; } </s>

A subroutine of the atomic operation splitters . Emit an insxl instruction in MODE .


<s> bool ix86_d_has_stdcall_convention ( unsigned int * link_system , unsigned int * link_windows ) { if ( ix86_abi == MS_ABI ) { * link_system = 1 ; * link_windows = ( ! TARGET_64BIT ) ? 1 : 0 ; } else { * link_system = 0 ; * link_windows = 0 ; } return true ; } </s>

Implement TARGET_D_HAS_STDCALL_CONVENTION for x86 targets .


<s> unsigned getGlobalBaseReg ( ) const { return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> bool aarch64_fusion_enabled_p ( enum aarch64_fusion_pairs op ) { return ( aarch64_tune_params . fusible_ops & op ) != 0 ; } </s>

Return true iff the instruction fusion described by OP is enabled .


<s> unsigned PPCRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; const unsigned DefaultSafety = 1 ; switch ( RC -> getID ( ) ) { default : return 0 ; case PPC :: G8RCRegClassID : case PPC :: GPRCRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 32 - FP - DefaultSafety ; } case PPC :: F8RCRegClassID : case PPC :: F4RCRegClassID : case PPC :: VRRCRegClassID : return 32 - DefaultSafety ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> static void arc_override_options ( void ) { if ( arc_cpu == PROCESSOR_NONE ) arc_cpu = PROCESSOR_ARC700 ; if ( arc_size_opt_level == 3 ) optimize_size = 1 ; if ( flag_pic ) target_flags |= MASK_NO_SDATA_SET ; if ( flag_no_common == 255 ) flag_no_common = ! TARGET_NO_SDATA_SET ; if ( TARGET_MIXED_CODE ) TARGET_Q_CLASS = 1 ; if ( ! TARGET_Q_CLASS ) TARGET_COMPACT_CASESI = 0 ; if ( TARGET_COMPACT_CASESI ) TARGET_CASE_VECTOR_PC_RELATIVE = 1 ; arc_init ( ) ; } </s>

Check ARC options , generate derived target attributes .


<s> static const char * rs6000_mangle_type ( const_tree type ) { type = TYPE_MAIN_VARIANT ( type ) ; if ( TREE_CODE ( type ) != VOID_TYPE && TREE_CODE ( type ) != BOOLEAN_TYPE && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE ) return NULL ; if ( type == bool_char_type_node ) return "U6__boolc" ; if ( type == bool_short_type_node ) return "U6__bools" ; if ( type == pixel_type_node ) return "u7__pixel" ; if ( type == bool_int_type_node ) return "U6__booli" ; if ( type == bool_long_long_type_node ) return "U6__boolx" ; if ( TARGET_FLOAT128_TYPE ) { if ( type == ieee128_float_type_node ) return "U10__float128" ; if ( TARGET_LONG_DOUBLE_128 ) { if ( type == long_double_type_node ) return ( TARGET_IEEEQUAD ) ? "U10__float128" : "g" ; if ( type == ibm128_float_type_node ) return "g" ; } } if ( TYPE_MAIN_VARIANT ( type ) == long_double_type_node && TARGET_ELF && TARGET_LONG_DOUBLE_128 && ! TARGET_IEEEQUAD ) return "g" ; return NULL ; } </s>

AltiVec defines five built-in scalar types that serve as vector elements ; we must teach the compiler how to mangle them . The 128-bit floating point mangling is target-specific as well . MMA defines two built-in types to be used as opaque vector types .


<s> static machine_mode aarch64_reg_save_mode ( unsigned int regno ) { if ( GP_REGNUM_P ( regno ) ) return DImode ; if ( FP_REGNUM_P ( regno ) ) switch ( crtl -> abi -> id ( ) ) { case ARM_PCS_AAPCS64 : return DFmode ; case ARM_PCS_SIMD : return TFmode ; case ARM_PCS_SVE : if ( aarch64_emit_cfi_for_reg_p ( regno ) ) return VNx2DImode ; return VNx16QImode ; case ARM_PCS_TLSDESC : case ARM_PCS_UNKNOWN : break ; } if ( PR_REGNUM_P ( regno ) ) return VNx16BImode ; gcc_unreachable ( ) ; } </s>

Return the mode a register save/restore should use . DImode for integer registers , DFmode for FP registers in non-SIMD functions ( they only save the bottom half of a 128 bit register ) , or TFmode for FP registers in SIMD functions .


<s> bool RV16KInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { TBB = FBB = nullptr ; assert ( Cond . size ( ) == 0 ) ; MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) || ! isUnpredicatedTerminator ( * I ) ) return false ; MachineBasicBlock :: iterator FirstUncondOrIndirectBr = MBB . end ( ) ; int NumTerminators = 0 ; for ( auto J = I . getReverse ( ) ; J != MBB . rend ( ) && isUnpredicatedTerminator ( * J ) ; J ++ ) { NumTerminators ++ ; if ( J -> getDesc ( ) . isUnconditionalBranch ( ) || J -> getDesc ( ) . isIndirectBranch ( ) ) { FirstUncondOrIndirectBr = J . getReverse ( ) ; } } if ( AllowModify && FirstUncondOrIndirectBr != MBB . end ( ) ) { while ( std :: next ( FirstUncondOrIndirectBr ) != MBB . end ( ) ) { std :: next ( FirstUncondOrIndirectBr ) -> eraseFromParent ( ) ; NumTerminators -- ; } I = FirstUncondOrIndirectBr ; } if ( I -> getDesc ( ) . isIndirectBranch ( ) ) return true ; if ( NumTerminators > 2 ) return true ; if ( NumTerminators == 1 && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { TBB = I -> getOperand ( 0 ) . getMBB ( ) ; return false ; } if ( NumTerminators == 1 && I -> getDesc ( ) . isConditionalBranch ( ) ) { parseCondBranch ( * I , TBB , Cond ) ; return false ; } if ( NumTerminators == 2 && std :: prev ( I ) -> getDesc ( ) . isConditionalBranch ( ) && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { parseCondBranch ( * std :: prev ( I ) , TBB , Cond ) ; FBB = I -> getOperand ( 0 ) . getMBB ( ) ; return false ; } return true ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


" Instructions Emitted in this clause\n"

ScheduleDAGMI has scheduled an instruction - tell HazardRec about it .


<s> static int ia32_multipass_dfa_lookahead ( void ) { switch ( ix86_tune ) { case PROCESSOR_PENTIUM : case PROCESSOR_LAKEMONT : return 2 ; case PROCESSOR_PENTIUMPRO : case PROCESSOR_K6 : return 1 ; case PROCESSOR_BDVER1 : case PROCESSOR_BDVER2 : case PROCESSOR_BDVER3 : case PROCESSOR_BDVER4 : return 4 ; case PROCESSOR_CORE2 : case PROCESSOR_NEHALEM : case PROCESSOR_SANDYBRIDGE : case PROCESSOR_HASWELL : case PROCESSOR_BONNELL : case PROCESSOR_SILVERMONT : case PROCESSOR_KNL : case PROCESSOR_INTEL : if ( reload_completed ) return ix86_issue_rate ( ) ; return 0 ; default : return 0 ; } } </s>

How many alternative schedules to try . This should be as wide as the scheduling freedom in the DFA , but no wider . Making this value too large results extra work for the scheduler .


<s> void WebAssemblyPassConfig :: addPreRegAlloc ( ) { TargetPassConfig :: addPreRegAlloc ( ) ; addPass ( createWebAssemblyStoreResults ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> void MipsRegisterInfo :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = ( MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc :: getUnknownLoc ( ) ) ; bool isPIC = ( MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ; adjustMipsStackFrame ( MF ) ; unsigned StackSize = MFI -> getStackSize ( ) ; if ( StackSize == 0 && ! MFI -> hasCalls ( ) ) return ; int FPOffset = MipsFI -> getFPStackOffset ( ) ; int RAOffset = MipsFI -> getRAStackOffset ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: NOREORDER ) ) ; if ( isPIC && Subtarget . isABI_O32 ( ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: CPLOAD ) ) . addReg ( getPICCallReg ( ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: NOMACRO ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDiu ) , Mips :: SP ) . addReg ( Mips :: SP ) . addImm ( - StackSize ) ; if ( MFI -> hasCalls ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: SW ) ) . addReg ( Mips :: RA ) . addImm ( RAOffset ) . addReg ( Mips :: SP ) ; } if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: SW ) ) . addReg ( Mips :: FP ) . addImm ( FPOffset ) . addReg ( Mips :: SP ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDu ) , Mips :: FP ) . addReg ( Mips :: SP ) . addReg ( Mips :: ZERO ) ; } if ( MipsFI -> needGPSaveRestore ( ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: CPRESTORE ) ) . addImm ( MipsFI -> getGPStackOffset ( ) ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Mips Mips Mips Mips Mips Mips 0 Mips Mips Mips::NOREORDER Mips::CPLOAD Mips::NOMACRO Mips::ADDiu Mips::SP Mips::SP Mips::SW Mips::RA Mips::SP Mips::SW Mips::FP Mips::SP Mips::ADDu Mips::FP Mips::SP Mips::ZERO Mips Mips::CPRESTORE Mips


<s> unsigned R600InstrInfo :: isLegalUpTo ( const std :: vector < std :: vector < std :: pair < int , unsigned >> > & IGSrcs , const std :: vector < R600InstrInfo :: BankSwizzle > & Swz , const std :: vector < std :: pair < int , unsigned >> & TransSrcs , R600InstrInfo :: BankSwizzle TransSwz ) const { int Vector [ 4 ] [ 3 ] ; memset ( Vector , - 1 , sizeof ( Vector ) ) ; for ( unsigned i = 0 , e = IGSrcs . size ( ) ; i < e ; i ++ ) { const std :: vector < std :: pair < int , unsigned >> & Srcs = Swizzle ( IGSrcs [ i ] , Swz [ i ] ) ; for ( unsigned j = 0 ; j < 3 ; j ++ ) { const std :: pair < int , unsigned > & Src = Srcs [ j ] ; if ( Src . first < 0 || Src . first == 255 ) continue ; if ( Src . first == GET_REG_INDEX ( RI . getEncodingValue ( AMDGPU :: OQAP ) ) ) { if ( Swz [ i ] != R600InstrInfo :: ALU_VEC_012_SCL_210 && Swz [ i ] != R600InstrInfo :: ALU_VEC_021_SCL_122 ) { return false ; } continue ; } if ( Vector [ Src . second ] [ j ] < 0 ) Vector [ Src . second ] [ j ] = Src . first ; if ( Vector [ Src . second ] [ j ] != Src . first ) return i ; } } for ( unsigned i = 0 , e = TransSrcs . size ( ) ; i < e ; ++ i ) { const std :: pair < int , unsigned > & Src = TransSrcs [ i ] ; unsigned Cycle = getTransSwizzle ( TransSwz , i ) ; if ( Src . first < 0 ) continue ; if ( Src . first == 255 ) continue ; if ( Vector [ Src . second ] [ Cycle ] < 0 ) Vector [ Src . second ] [ Cycle ] = Src . first ; if ( Vector [ Src . second ] [ Cycle ] != Src . first ) return IGSrcs . size ( ) - 1 ; } return IGSrcs . size ( ) ; } </s>

returns how many MIs ( whose inputs are represented by IGSrcs ) can be packed in the same Instruction Group while meeting read port limitations given a Swz swizzle sequence .


"Unknown ValueType for f-register-type!"

"Unknown ValueType for e-register-type!"

Given a physical register constraint ( e.g .


<s>
bool
HexagonDCE
::
run
(
)
{
bool
Collected
=
collect
(
)
;
if
(
!
Collected
)
return
false
;
const
SetVector
<
NodeId
>
&
DeadNodes
=
getDeadNodes
(
)
;
const
SetVector
<
NodeId
>
&
DeadInstrs
=
getDeadInstrs
(
)
;
using
RefToInstrMap
=
DenseMap
<
NodeId
,
NodeId
>
;
RefToInstrMap
R2I
;
SetVector
<
NodeId
>
PartlyDead
;
DataFlowGraph
&
DFG
=
getDFG
(
)
;
for
(
NodeAddr
<
BlockNode
*
>
BA
:
DFG
.
getFunc
(
)
.
Addr
->
members
(
DFG
)
)
{
for
(
auto
TA
:
BA
.
Addr
->
members_if
(
DFG
.
IsCode
<
NodeAttrs
::
Stmt
>
,
DFG
)
)
{
NodeAddr
<
StmtNode
*
>
SA
=
TA
;
for
(
NodeAddr
<
RefNode
*
>
RA
:
SA
.
Addr
->
members
(
DFG
)
)
{
R2I
.
insert
(
std
::
make_pair
(
RA
.
Id
,
SA
.
Id
)
)
;
if
(
DFG
.
IsDef
(
RA
)
&&
DeadNodes
.
count
(
RA
.
Id
)
)
if
(
!
DeadInstrs
.
count
(
SA
.
Id
)
)
PartlyDead
.
insert
(
SA
.
Id
)
;
}
}
}
SetVector
<
NodeId
>
Remove
=
DeadInstrs
;
bool
Changed
=
false
;
for
(
NodeId
N
:
PartlyDead
)
{
auto
SA
=
DFG
.
addr
<
StmtNode
*
>
(
N
)
;
if
(
trace
(
)
)
dbgs
(
)
<<
"Partly dead: "
<<
*
SA
.
Addr
->
getCode
(
)
;
Changed
|=
rewrite
(
SA
,
Remove
)
;
}
return
erase
(
Remove
)
||
Changed
;
}
</s>

Run the analysis pass over a function and produce a dominator tree .


<s>
void
RISCVAsmBackend
::
relaxInstruction
(
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
)
const
{
MCInst
Res
;
bool
IsCapMode
=
STI
.
getFeatureBits
(
)
[
RISCV
::
FeatureCapMode
]
;
switch
(
Inst
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Opcode not expected!"
)
;
case
RISCV
::
C_BEQZ
:
Res
.
setOpcode
(
RISCV
::
BEQ
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
Res
.
addOperand
(
MCOperand
::
createReg
(
RISCV
::
X0
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
1
)
)
;
break
;
case
RISCV
::
C_BNEZ
:
Res
.
setOpcode
(
RISCV
::
BNE
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
Res
.
addOperand
(
MCOperand
::
createReg
(
RISCV
::
X0
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
1
)
)
;
break
;
case
RISCV
::
C_J
:
Res
.
setOpcode
(
IsCapMode
RISCV
::
CJAL
:
RISCV
::
JAL
)
;
Res
.
addOperand
(
MCOperand
::
createReg
(
IsCapMode
RISCV
::
C0
:
RISCV
::
X0
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
break
;
case
RISCV
::
C_JAL
:
Res
.
setOpcode
(
RISCV
::
JAL
)
;
Res
.
addOperand
(
MCOperand
::
createReg
(
RISCV
::
X1
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
break
;
case
RISCV
::
C_CJAL
:
Res
.
setOpcode
(
RISCV
::
CJAL
)
;
Res
.
addOperand
(
MCOperand
::
createReg
(
RISCV
::
C1
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
break
;
}
Inst
=
std
::
move
(
Res
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> static MCSubtargetInfo * createMCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { return createWebAssemblyMCSubtargetInfoImpl ( TT , CPU , CPU , FS ) ; } </s>

createMCSubtargetInfo - Create a MCSubtargetInfo implementation .


<s> void v850_output_aligned_bss ( FILE * file , tree decl , const char * name , unsigned HOST_WIDE_INT size , int align ) { switch ( v850_get_data_area ( decl ) ) { case DATA_AREA_ZDA : zbss_section ( ) ; break ; case DATA_AREA_SDA : sbss_section ( ) ; break ; case DATA_AREA_TDA : tdata_section ( ) ; default : bss_section ( ) ; break ; } ASM_OUTPUT_ALIGN ( file , floor_log2 ( align / BITS_PER_UNIT ) ) ; last_assemble_variable_decl = decl ; ASM_DECLARE_OBJECT_NAME ( file , name , decl ) ; ASM_OUTPUT_LABEL ( file , name ) ; ASM_OUTPUT_SKIP ( file , size ? size : 1 ) ; } </s>

A version of asm_output_aligned_bss ( ) that copes with the special data areas of the v850 .


<s>
void
assignValueToAddress
(
unsigned
ValVReg
,
unsigned
Addr
,
uint64_t
Size
,
MachinePointerInfo
&
MPO
,
CCValAssign
&
VA
)
override
{
assert
(
(
Size
==
1
||
Size
==
2
||
Size
==
4
||
Size
==
8
)
&&
"Unsupported size"
)
;
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
SExt
||
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExt
)
{
Size
=
4
;
assert
(
MRI
.
getType
(
ValVReg
)
.
isScalar
(
)
&&
"Only scalars supported atm"
)
;
auto
LoadVReg
=
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
32
)
)
;
buildLoad
(
LoadVReg
,
Addr
,
Size
,
0
,
MPO
)
;
MIRBuilder
.
buildTrunc
(
ValVReg
,
LoadVReg
)
;
}
else
{
buildLoad
(
ValVReg
,
Addr
,
Size
,
0
,
MPO
)
;
}
}
</s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> bool MipsTTIImpl :: hasDivRemOp ( Type * DataType , bool IsSigned ) { EVT VT = TLI -> getValueType ( DL , DataType ) ; return TLI -> isOperationLegalOrCustom ( IsSigned ? ISD :: SDIVREM : ISD :: UDIVREM , VT ) ; } </s>

Return true if the target has a unified operation to calculate division and remainder .


<s> const RISCVSubtarget & getSubtarget ( ) const { return Subtarget ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


<s> bool AMDGPUPromoteAlloca :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; if ( auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ) TM = & TPC -> getTM < TargetMachine > ( ) ; else return false ; const Triple & TT = TM -> getTargetTriple ( ) ; IsAMDGCN = TT . getArch ( ) == Triple :: amdgcn ; IsAMDHSA = TT . getOS ( ) == Triple :: AMDHSA ; const AMDGPUCommonSubtarget & ST = AMDGPUCommonSubtarget :: get ( * TM , F ) ; if ( ! ST . isPromoteAllocaEnabled ( ) ) return false ; AS = AMDGPU :: getAMDGPUAS ( * F . getParent ( ) ) ; bool SufficientLDS = hasSufficientLocalMem ( F ) ; bool Changed = false ; BasicBlock & EntryBB = * F . begin ( ) ; for ( auto I = EntryBB . begin ( ) , E = EntryBB . end ( ) ; I != E ; ) { AllocaInst * AI = dyn_cast < AllocaInst > ( I ) ; ++ I ; if ( AI ) Changed |= handleAlloca ( * AI , SufficientLDS ) ; } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU::getAMDGPUAS


<s> bool NEONPreAllocPass :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getTarget ( ) . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= PreAllocNEONRegisters ( MBB ) ; } return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> VariantKind getKind ( ) const { return Kind ; } </s>


"r%d has non convertible def in insn %d\n"

"r%d has non convertible use in insn %d\n"

For a register REGNO , scan instructions for its defs and uses . Put REGNO in REGS if a def or use is n't in CANDIDATES .


<s>
void
WebAssemblyInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
OS
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
)
{
printInstruction
(
MI
,
OS
)
;
const
MCInstrDesc
&
Desc
=
MII
.
get
(
MI
->
getOpcode
(
)
)
;
if
(
Desc
.
isVariadic
(
)
)
for
(
auto
i
=
Desc
.
getNumOperands
(
)
,
e
=
MI
->
getNumOperands
(
)
;
i
<
e
;
++
i
)
{
if
(
i
!=
0
&&
(
MI
->
getOpcode
(
)
!=
WebAssembly
::
CALL_INDIRECT_VOID
||
i
!=
Desc
.
getNumOperands
(
)
)
)
OS
<<
", "
;
printOperand
(
MI
,
i
,
OS
)
;
}
printAnnotation
(
OS
,
Annot
)
;
if
(
CommentStream
)
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
WebAssembly
::
LOOP
:
{
printAnnotation
(
OS
,
"label"
+
utostr
(
ControlFlowCounter
)
+
':'
)
;
ControlFlowStack
.
push_back
(
std
::
make_pair
(
ControlFlowCounter
++
,
true
)
)
;
break
;
}
case
WebAssembly
::
BLOCK
:
ControlFlowStack
.
push_back
(
std
::
make_pair
(
ControlFlowCounter
++
,
false
)
)
;
break
;
case
WebAssembly
::
END_LOOP
:
if
(
!
ControlFlowStack
.
empty
(
)
)
ControlFlowStack
.
pop_back
(
)
;
break
;
case
WebAssembly
::
END_BLOCK
:
if
(
!
ControlFlowStack
.
empty
(
)
)
printAnnotation
(
OS
,
"label"
+
utostr
(
ControlFlowStack
.
pop_back_val
(
)
.
first
)
+
':'
)
;
break
;
}
unsigned
NumFixedOperands
=
Desc
.
NumOperands
;
SmallSet
<
uint64_t
,
8
>
Printed
;
for
(
unsigned
i
=
0
,
e
=
MI
->
getNumOperands
(
)
;
i
<
e
;
++
i
)
{
if
(
!
(
i
<
NumFixedOperands
(
Desc
.
OpInfo
[
i
]
.
OperandType
==
WebAssembly
::
OPERAND_BASIC_BLOCK
)
:
(
Desc
.
TSFlags
&
WebAssemblyII
::
VariableOpImmediateIsLabel
)
)
)
continue
;
uint64_t
Depth
=
MI
->
getOperand
(
i
)
.
getImm
(
)
;
if
(
!
Printed
.
insert
(
Depth
)
.
second
)
continue
;
const
auto
&
Pair
=
ControlFlowStack
.
rbegin
(
)
[
Depth
]
;
printAnnotation
(
OS
,
utostr
(
Depth
)
+
": "
+
(
Pair
.
second
"up"
:
"down"
)
+
" to label"
+
utostr
(
Pair
.
first
)
)
;
}
}
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s> bool PPCCTRLoops :: runOnFunction ( Function & F ) { LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ; LibInfo = TLIP ? & TLIP -> getTLI ( ) : nullptr ; PreserveLCSSA = mustPreserveAnalysisID ( LCSSAID ) ; bool MadeChange = false ; for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) { Loop * L = * I ; if ( ! L -> getParentLoop ( ) ) MadeChange |= convertToCTRLoop ( L ) ; } return MadeChange ; } </s>


<s>
const
uint32_t
*
RISCVRegisterInfo
::
getCallPreservedMask
(
const
MachineFunction
&
MF
,
CallingConv
::
ID
)
const
{
auto
&
Subtarget
=
MF
.
getSubtarget
<
RISCVSubtarget
>
(
)
;
if
(
MF
.
getFunction
(
)
.
hasFnAttribute
(
"interrupt"
)
)
{
if
(
Subtarget
.
hasStdExtD
(
)
)
return
CSR_XLEN_F64_Interrupt_RegMask
;
if
(
Subtarget
.
hasStdExtF
(
)
)
return
CSR_XLEN_F32_Interrupt_RegMask
;
return
CSR_Interrupt_RegMask
;
}
switch
(
Subtarget
.
getTargetABI
(
)
)
{
default
:
llvm_unreachable
(
"Unrecognized ABI"
)
;
case
RISCVABI
::
ABI_ILP32
:
case
RISCVABI
::
ABI_LP64
:
return
CSR_ILP32_LP64_RegMask
;
case
RISCVABI
::
ABI_ILP32F
:
case
RISCVABI
::
ABI_LP64F
:
return
CSR_ILP32F_LP64F_RegMask
;
case
RISCVABI
::
ABI_ILP32D
:
case
RISCVABI
::
ABI_LP64D
:
return
CSR_ILP32D_LP64D_RegMask
;
}
}
</s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> TargetPassConfig * CAHPTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new TargetPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> void i386_pe_maybe_record_exported_symbol ( tree decl , const char * name , int is_data ) { rtx symbol ; struct export_list * p ; if ( ! decl ) return ; symbol = XEXP ( DECL_RTL ( decl ) , 0 ) ; gcc_assert ( GET_CODE ( symbol ) == SYMBOL_REF ) ; if ( ! SYMBOL_REF_DLLEXPORT_P ( symbol ) ) return ; gcc_assert ( TREE_PUBLIC ( decl ) ) ; p = ggc_alloc < export_list > ( ) ; p -> next = export_head ; p -> name = name ; p -> is_data = is_data ; export_head = p ; } </s>

Assemble an export symbol entry . We need to keep a list of these , so that we can output the export list at the end of the assembly . We used to output these export symbols in each function , but that causes problems with GNU ld when the sections are linkonce . Beware , DECL may be NULL if compile_file ( ) is emitting the LTO marker .


<s> EVT X86TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsZeroVal , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( IsZeroVal && ! F -> getFnAttributes ( ) . hasAttribute ( Attributes :: NoImplicitFloat ) ) { if ( Size >= 16 && ( Subtarget -> isUnalignedMemAccessFast ( ) || ( ( DstAlign == 0 || DstAlign >= 16 ) && ( SrcAlign == 0 || SrcAlign >= 16 ) ) ) && Subtarget -> getStackAlignment ( ) >= 16 ) { if ( Subtarget -> getStackAlignment ( ) >= 32 ) { if ( Subtarget -> hasAVX2 ( ) ) return MVT :: v8i32 ; if ( Subtarget -> hasAVX ( ) ) return MVT :: v8f32 ; } if ( Subtarget -> hasSSE2 ( ) ) return MVT :: v4i32 ; if ( Subtarget -> hasSSE1 ( ) ) return MVT :: v4f32 ; } else if ( ! MemcpyStrSrc && Size >= 8 && ! Subtarget -> is64Bit ( ) && Subtarget -> getStackAlignment ( ) >= 8 && Subtarget -> hasSSE2 ( ) ) { return MVT :: f64 ; } } if ( Subtarget -> is64Bit ( ) && Size >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> static bool arm_must_pass_in_stack ( const function_arg_info & arg ) { if ( TARGET_AAPCS_BASED ) return must_pass_in_stack_var_size ( arg ) ; else return must_pass_in_stack_var_size_or_pad ( arg ) ; } </s>

Return true if a type must be passed in memory . For AAPCS , small aggregates ( padded to the size of a word ) should be passed in a register .


<s>
void
assignValueToReg
(
Register
ValVReg
,
Register
PhysReg
,
CCValAssign
&
VA
)
override
{
MIB
.
addUse
(
PhysReg
,
RegState
::
Implicit
)
;
Register
ExtReg
;
unsigned
PhysRegSize
=
MRI
.
getTargetRegisterInfo
(
)
->
getRegSizeInBits
(
PhysReg
,
MRI
)
;
unsigned
ValSize
=
VA
.
getValVT
(
)
.
getSizeInBits
(
)
;
unsigned
LocSize
=
VA
.
getLocVT
(
)
.
getSizeInBits
(
)
;
if
(
PhysRegSize
>
ValSize
&&
LocSize
==
ValSize
)
{
assert
(
(
PhysRegSize
==
128
||
PhysRegSize
==
80
)
&&
"We expect that to be 128 bit"
)
;
ExtReg
=
MIRBuilder
.
buildAnyExt
(
LLT
::
scalar
(
PhysRegSize
)
,
ValVReg
)
.
getReg
(
0
)
;
}
else
ExtReg
=
extendRegister
(
ValVReg
,
VA
)
;
MIRBuilder
.
buildCopy
(
PhysReg
,
ExtReg
)
;
}
</s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> static rtx sparc_function_incoming_arg ( cumulative_args_t cum , const function_arg_info & arg ) { return sparc_function_arg_1 ( cum , arg , true ) ; } </s>

Handle the TARGET_FUNCTION_INCOMING_ARG target hook .


<s> SDValue MipsTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SDNode * CallNode , const Type * RetTy ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; MipsCC MipsCCInfo ( CallConv , Subtarget -> isABI_O32 ( ) , Subtarget -> isFP64bit ( ) , CCInfo ) ; MipsCCInfo . analyzeCallResult ( Ins , Subtarget -> abiUsesSoftFloat ( ) , CallNode , RetTy ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( 1 ) ; InFlag = Val . getValue ( 2 ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( ISD :: BITCAST , DL , RVLocs [ i ] . getValVT ( ) , Val ) ; InVals . push_back ( Val ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static bool riscv_scalar_mode_supported_p ( scalar_mode mode ) { if ( mode == HFmode ) return true ; else return default_scalar_mode_supported_p ( mode ) ; } </s>


<s>
SDValue
PPCTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCRetInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCRetInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_PPC
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
VT
=
VA
.
getValVT
(
)
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
VT
,
InFlag
)
.
getValue
(
1
)
;
InVals
.
push_back
(
Chain
.
getValue
(
0
)
)
;
InFlag
=
Chain
.
getValue
(
2
)
;
}
return
Chain
;
}
</s>


<s> unsigned SystemZInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { return isSimpleMove ( MI , FrameIndex , SystemZII :: SimpleBDXLoad ) ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> static const char * aarch64_get_multilib_abi_name ( void ) { if ( TARGET_BIG_END ) return TARGET_ILP32 ? "aarch64_be_ilp32" : "aarch64_be" ; return TARGET_ILP32 ? "aarch64_ilp32" : "aarch64" ; } </s>


<s> bool SIAnnotateControlFlow :: runOnFunction ( Function & F ) { DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; DA = & getAnalysis < DivergenceAnalysis > ( ) ; for ( df_iterator < BasicBlock * > I = df_begin ( & F . getEntryBlock ( ) ) , E = df_end ( & F . getEntryBlock ( ) ) ; I != E ; ++ I ) { BranchInst * Term = dyn_cast < BranchInst > ( ( * I ) -> getTerminator ( ) ) ; if ( ! Term || Term -> isUnconditional ( ) ) { if ( isTopOfStack ( * I ) ) closeControlFlow ( * I ) ; continue ; } if ( I . nodeVisited ( Term -> getSuccessor ( 1 ) ) ) { if ( isTopOfStack ( * I ) ) closeControlFlow ( * I ) ; handleLoop ( Term ) ; continue ; } if ( isTopOfStack ( * I ) ) { PHINode * Phi = dyn_cast < PHINode > ( Term -> getCondition ( ) ) ; if ( Phi && Phi -> getParent ( ) == * I && isElse ( Phi ) ) { insertElse ( Term ) ; eraseIfUnused ( Phi ) ; continue ; } closeControlFlow ( * I ) ; } openIf ( Term ) ; } assert ( Stack . empty ( ) ) ; return true ; } </s>


"Dangerous instruction in branch delay slot!"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool hasFP ( const MachineFunction & MF ) const { return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool ARMFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , MutableArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; bool isVarArg = AFI -> getArgRegsSaveSize ( ) > 0 ; unsigned NumAlignedDPRCS2Regs = AFI -> getNumAlignedDPRCS2Regs ( ) ; if ( NumAlignedDPRCS2Regs ) emitAlignedDPRCS2Restores ( MBB , MI , NumAlignedDPRCS2Regs , CSI , TRI ) ; unsigned PopOpc = AFI -> isThumbFunction ( ) ? ARM :: t2LDMIA_UPD : ARM :: LDMIA_UPD ; unsigned LdrOpc = AFI -> isThumbFunction ( ) ? ARM :: t2LDR_POST : ARM :: LDR_POST_IMM ; unsigned FltOpc = ARM :: VLDMDIA_UPD ; emitPopInst ( MBB , MI , CSI , FltOpc , 0 , isVarArg , true , & isARMArea3Register , NumAlignedDPRCS2Regs ) ; emitPopInst ( MBB , MI , CSI , PopOpc , LdrOpc , isVarArg , false , & isARMArea2Register , 0 ) ; emitPopInst ( MBB , MI , CSI , PopOpc , LdrOpc , isVarArg , false , & isARMArea1Register , 0 ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool AMDGPUAsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const { return ( ( ( int64_t ( Value ) / 4 ) - 1 ) == 0x3f ) ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> inline hashval_t wrapped_symbol_hasher :: hash ( const value_type * v ) { return htab_hash_string ( v ) ; } </s>

Hash function for builtin functions with up to 3 arguments and a return type .


<s>
void
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
)
const
{
unsigned
NumBytes
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
.
TargetSize
/
8
;
Value
=
adjustFixupValue
(
Fixup
.
getKind
(
)
,
Value
)
;
if
(
!
Value
)
return
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
BTFTypeDerived
::
BTFTypeDerived
(
const
DIDerivedType
*
DTy
,
unsigned
Tag
,
bool
NeedsFixup
)
:
DTy
(
DTy
)
,
NeedsFixup
(
NeedsFixup
)
{
switch
(
Tag
)
{
case
dwarf
::
DW_TAG_pointer_type
:
Kind
=
BTF
::
BTF_KIND_PTR
;
break
;
case
dwarf
::
DW_TAG_const_type
:
Kind
=
BTF
::
BTF_KIND_CONST
;
break
;
case
dwarf
::
DW_TAG_volatile_type
:
Kind
=
BTF
::
BTF_KIND_VOLATILE
;
break
;
case
dwarf
::
DW_TAG_typedef
:
Kind
=
BTF
::
BTF_KIND_TYPEDEF
;
break
;
case
dwarf
::
DW_TAG_restrict_type
:
Kind
=
BTF
::
BTF_KIND_RESTRICT
;
break
;
default
:
llvm_unreachable
(
"Unknown DIDerivedType Tag"
)
;
}
BTFType
.
Info
=
Kind
<<
24
;
}
</s>


<s>
MachineBasicBlock
::
iterator
AVRFrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
)
const
{
const
AVRSubtarget
&
STI
=
MF
.
getSubtarget
<
AVRSubtarget
>
(
)
;
const
AVRInstrInfo
&
TII
=
*
STI
.
getInstrInfo
(
)
;
if
(
hasReservedCallFrame
(
MF
)
)
{
return
MBB
.
erase
(
MI
)
;
}
DebugLoc
DL
=
MI
->
getDebugLoc
(
)
;
unsigned
int
Opcode
=
MI
->
getOpcode
(
)
;
int
Amount
=
TII
.
getFrameSize
(
*
MI
)
;
if
(
Amount
==
0
)
{
return
MBB
.
erase
(
MI
)
;
}
assert
(
getStackAlign
(
)
==
Align
(
1
)
&&
"Unsupported stack alignment"
)
;
if
(
Opcode
==
TII
.
getCallFrameSetupOpcode
(
)
)
{
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
SPREAD
)
,
AVR
::
R31R30
)
.
addReg
(
AVR
::
SP
)
;
MachineInstr
*
New
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
SUBIWRdK
)
,
AVR
::
R31R30
)
.
addReg
(
AVR
::
R31R30
,
RegState
::
Kill
)
.
addImm
(
Amount
)
;
New
->
getOperand
(
3
)
.
setIsDead
(
)
;
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
SPWRITE
)
,
AVR
::
SP
)
.
addReg
(
AVR
::
R31R30
)
;
fixStackStores
(
MBB
,
MI
,
TII
)
;
}
else
{
assert
(
Opcode
==
TII
.
getCallFrameDestroyOpcode
(
)
)
;
unsigned
AddOpcode
;
if
(
isUInt
<
6
>
(
Amount
)
)
{
AddOpcode
=
AVR
::
ADIWRdK
;
}
else
{
AddOpcode
=
AVR
::
SUBIWRdK
;
Amount
=
Amount
;
}
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
SPREAD
)
,
AVR
::
R31R30
)
.
addReg
(
AVR
::
SP
)
;
MachineInstr
*
New
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AddOpcode
)
,
AVR
::
R31R30
)
.
addReg
(
AVR
::
R31R30
,
RegState
::
Kill
)
.
addImm
(
Amount
)
;
New
->
getOperand
(
3
)
.
setIsDead
(
)
;
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
SPWRITE
)
,
AVR
::
SP
)
.
addReg
(
AVR
::
R31R30
,
RegState
::
Kill
)
;
}
return
MBB
.
erase
(
MI
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s>
bool
GCNDPPCombine
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
auto
&
ST
=
MF
.
getSubtarget
<
GCNSubtarget
>
(
)
;
if
(
!
ST
.
hasDPP
(
)
||
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
MRI
=
&
MF
.
getRegInfo
(
)
;
TII
=
ST
.
getInstrInfo
(
)
;
assert
(
MRI
->
isSSA
(
)
&&
"Must be run on SSA"
)
;
bool
Changed
=
false
;
for
(
auto
&
MBB
:
MF
)
{
for
(
auto
I
=
MBB
.
rbegin
(
)
,
E
=
MBB
.
rend
(
)
;
I
!=
E
;
)
{
auto
&
MI
=
*
I
++
;
if
(
MI
.
getOpcode
(
)
==
AMDGPU
::
V_MOV_B32_dpp
&&
combineDPPMov
(
MI
)
)
{
Changed
=
true
;
++
NumDPPMovsCombined
;
}
else
if
(
MI
.
getOpcode
(
)
==
AMDGPU
::
V_MOV_B64_DPP_PSEUDO
)
{
auto
Split
=
TII
->
expandMovDPP64
(
MI
)
;
for
(
auto
M
:
{
Split
.
first
,
Split
.
second
}
)
{
if
(
combineDPPMov
(
*
M
)
)
++
NumDPPMovsCombined
;
}
Changed
=
true
;
}
}
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static rtx rs6000_spe_function_arg ( const CUMULATIVE_ARGS * cum , machine_mode mode , const_tree type ) { int gregno = cum -> sysv_gregno ; if ( TARGET_E500_DOUBLE && ( mode == DFmode || mode == TFmode || mode == DCmode || mode == TCmode ) ) { int n_words = rs6000_arg_size ( mode , type ) ; if ( mode == DFmode ) gregno += ( 1 - gregno ) & 1 ; if ( gregno + n_words - 1 > GP_ARG_MAX_REG ) return NULL_RTX ; return spe_build_register_parallel ( mode , gregno ) ; } if ( cum -> stdarg ) { int n_words = rs6000_arg_size ( mode , type ) ; if ( n_words == 2 && ( gregno & 1 ) == 0 ) gregno += 1 ; if ( gregno + n_words - 1 <= GP_ARG_MAX_REG ) { rtx r1 , r2 ; machine_mode m = SImode ; r1 = gen_rtx_REG ( m , gregno ) ; r1 = gen_rtx_EXPR_LIST ( m , r1 , const0_rtx ) ; r2 = gen_rtx_REG ( m , gregno + 1 ) ; r2 = gen_rtx_EXPR_LIST ( m , r2 , GEN_INT ( 4 ) ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , r1 , r2 ) ) ; } else return NULL_RTX ; } else { if ( gregno <= GP_ARG_MAX_REG ) return gen_rtx_REG ( mode , gregno ) ; else return NULL_RTX ; } } </s>

Determine where to put a SIMD argument on the SPE .


<s> bool RISCVTTIImpl :: isLoweredToCall ( const Function * F ) { if ( F -> getName ( ) . startswith ( "llvm.riscv.pulp" ) ) return false ; return BaseT :: isLoweredToCall ( F ) ; } </s>

Test whether calls to a function lower to actual program function calls .


<s> void SystemZAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { SystemZMCInstLower Lower ( MF -> getContext ( ) , * this ) ; MCInst LoweredMI ; switch ( MI -> getOpcode ( ) ) { case SystemZ :: Return : LoweredMI = MCInstBuilder ( SystemZ :: BR ) . addReg ( SystemZ :: R14D ) ; break ; case SystemZ :: CallBRASL : LoweredMI = MCInstBuilder ( SystemZ :: BRASL ) . addReg ( SystemZ :: R14D ) . addExpr ( Lower . getExpr ( MI -> getOperand ( 0 ) , MCSymbolRefExpr :: VK_PLT ) ) ; break ; case SystemZ :: CallBASR : LoweredMI = MCInstBuilder ( SystemZ :: BASR ) . addReg ( SystemZ :: R14D ) . addReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ; break ; case SystemZ :: CallJG : LoweredMI = MCInstBuilder ( SystemZ :: JG ) . addExpr ( Lower . getExpr ( MI -> getOperand ( 0 ) , MCSymbolRefExpr :: VK_PLT ) ) ; break ; case SystemZ :: CallBR : LoweredMI = MCInstBuilder ( SystemZ :: BR ) . addReg ( SystemZ :: R1D ) ; break ; case SystemZ :: IILF64 : LoweredMI = MCInstBuilder ( SystemZ :: IILF ) . addReg ( SystemZMC :: getRegAsGR32 ( MI -> getOperand ( 0 ) . getReg ( ) ) ) . addImm ( MI -> getOperand ( 2 ) . getImm ( ) ) ; break ; case SystemZ :: IIHF64 : LoweredMI = MCInstBuilder ( SystemZ :: IIHF ) . addReg ( SystemZMC :: getRegAsGRH32 ( MI -> getOperand ( 0 ) . getReg ( ) ) ) . addImm ( MI -> getOperand ( 2 ) . getImm ( ) ) ; break ; case SystemZ :: RISBHH : case SystemZ :: RISBHL : LoweredMI = lowerRIEfLow ( MI , SystemZ :: RISBHG ) ; break ; case SystemZ :: RISBLH : case SystemZ :: RISBLL : LoweredMI = lowerRIEfLow ( MI , SystemZ :: RISBLG ) ; break ; case SystemZ :: NAME ## 64 : LoweredMI = lowerRILow ( MI , SystemZ :: NAME ) ; break LOWER_LOW ( IILL ) ; LOWER_LOW ( IILH ) ; LOWER_LOW ( NILL ) ; LOWER_LOW ( NILH ) ; LOWER_LOW ( NILF ) ; LOWER_LOW ( OILL ) ; LOWER_LOW ( OILH ) ; LOWER_LOW ( OILF ) ; LOWER_LOW ( XILF ) ; case SystemZ :: NAME ## 64 : LoweredMI = lowerRIHigh ( MI , SystemZ :: NAME ) ; break LOWER_HIGH ( IIHL ) ; LOWER_HIGH ( IIHH ) ; LOWER_HIGH ( NIHL ) ; LOWER_HIGH ( NIHH ) ; LOWER_HIGH ( NIHF ) ; LOWER_HIGH ( OIHL ) ; LOWER_HIGH ( OIHH ) ; LOWER_HIGH ( OIHF ) ; LOWER_HIGH ( XIHF ) ; default : Lower . lower ( MI , LoweredMI ) ; break ; } OutStreamer . EmitInstruction ( LoweredMI ) ; } </s>


<s> bool X86AsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const { return int64_t ( Value ) != int64_t ( int8_t ( Value ) ) ; } </s>


<s> static int ia64_hpux_reloc_rw_mask ( void ) { return 3 ; } </s>

For HPUX , it is illegal to have relocations in shared segments .


"%qE attribute is supported only for SH2A"

"%qE attribute only applies to functions"


<s> unsigned X86InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case X86 :: MOV8rm : case X86 :: MOV16rm : case X86 :: MOV16_rm : case X86 :: MOV32rm : case X86 :: MOV32_rm : case X86 :: MOV64rm : case X86 :: LD_Fp64m : case X86 :: MOVSSrm : case X86 :: MOVSDrm : case X86 :: MOVAPSrm : case X86 :: MOVAPDrm : case X86 :: MOVDQArm : case X86 :: MMX_MOVD64rm : case X86 :: MMX_MOVQ64rm : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 3 ) . isReg ( ) && MI -> getOperand ( 4 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 1 && MI -> getOperand ( 3 ) . getReg ( ) == 0 && MI -> getOperand ( 4 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { llvm_unreachable ( "UNIMP" ) ; } </s>


<s> unsigned int ix86_local_alignment ( tree exp , machine_mode mode , unsigned int align ) { tree type , decl ; if ( exp && DECL_P ( exp ) ) { type = TREE_TYPE ( exp ) ; decl = exp ; } else { type = exp ; decl = NULL ; } if ( ! TARGET_64BIT && align == 64 && ix86_preferred_stack_boundary < 64 && ( mode == DImode || ( type && TYPE_MODE ( type ) == DImode ) ) && ( ! type || ! TYPE_USER_ALIGN ( type ) ) && ( ! decl || ! DECL_USER_ALIGN ( decl ) ) ) align = 32 ; if ( ! type ) { if ( mode == XFmode && align < GET_MODE_ALIGNMENT ( DFmode ) ) align = GET_MODE_ALIGNMENT ( DFmode ) ; return align ; } if ( TARGET_64BIT && optimize_function_for_speed_p ( cfun ) && TARGET_SSE ) { if ( AGGREGATE_TYPE_P ( type ) && ( va_list_type_node == NULL_TREE || ( TYPE_MAIN_VARIANT ( type ) != TYPE_MAIN_VARIANT ( va_list_type_node ) ) ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && wi :: geu_p ( TYPE_SIZE ( type ) , 16 ) && align < 128 ) return 128 ; } if ( TREE_CODE ( type ) == ARRAY_TYPE ) { if ( TYPE_MODE ( TREE_TYPE ( type ) ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( type ) ) ) && align < 128 ) return 128 ; } else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) { if ( TYPE_MODE ( type ) == DCmode && align < 64 ) return 64 ; if ( ( TYPE_MODE ( type ) == XCmode || TYPE_MODE ( type ) == TCmode ) && align < 128 ) return 128 ; } else if ( ( TREE_CODE ( type ) == RECORD_TYPE || TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == QUAL_UNION_TYPE ) && TYPE_FIELDS ( type ) ) { if ( DECL_MODE ( TYPE_FIELDS ( type ) ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( DECL_MODE ( TYPE_FIELDS ( type ) ) ) && align < 128 ) return 128 ; } else if ( TREE_CODE ( type ) == REAL_TYPE || TREE_CODE ( type ) == VECTOR_TYPE || TREE_CODE ( type ) == INTEGER_TYPE ) { if ( TYPE_MODE ( type ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( TYPE_MODE ( type ) ) && align < 128 ) return 128 ; } return align ; } </s>

Compute the alignment for a local variable . TYPE is the data type , and ALIGN is the alignment that the object would ordinarily have . The value of this macro is used instead of that alignment to align the object .


<s> InstructionCost NVPTXTTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: TargetCostKind CostKind , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args , const Instruction * CxtI ) { std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: ADD : case ISD :: MUL : case ISD :: XOR : case ISD :: OR : case ISD :: AND : if ( LT . second . SimpleTy == MVT :: i64 ) return 2 * LT . first ; return BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .

NVPTX NVPTX ISD::ADD ISD::MUL ISD::XOR ISD::OR ISD::AND MVT::i64 2


<s> uint64_t SystemZInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { if ( MI . getOpcode ( ) == TargetOpcode :: INLINEASM ) { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } return MI . getDesc ( ) . getSize ( ) ; } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> virtual const InstrItineraryData * getInstrItineraryData ( ) const { return InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


"Operand must be a register when you're"

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static bool call_ABI_of_interest ( tree fndecl ) { if ( rs6000_gnu_attr && symtab -> state == EXPANSION ) { struct cgraph_node * c_node ; if ( fndecl == NULL_TREE ) return true ; if ( DECL_EXTERNAL ( fndecl ) ) return true ; c_node = cgraph_node :: get ( fndecl ) ; c_node = c_node -> ultimate_alias_target ( ) ; return ! c_node -> only_called_directly_p ( ) ; } return false ; } </s>

Return TRUE if a call to function FNDECL may be one that potentially affects the function calling ABI of the object file .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesAll ( ) ; AU . addRequired < PatmosCallGraphBuilder > ( ) ; AU . addRequired < PatmosStackCacheAnalysisInfo > ( ) ; PMLModuleExportPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static bool ix86_legitimate_constant_p ( machine_mode mode , rtx x ) { switch ( GET_CODE ( x ) ) { case CONST : x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == PLUS ) { if ( ! CONST_INT_P ( XEXP ( x , 1 ) ) ) return false ; x = XEXP ( x , 0 ) ; } if ( TARGET_MACHO && darwin_local_data_pic ( x ) ) return true ; if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , 1 ) ) { case UNSPEC_GOT : case UNSPEC_GOTOFF : case UNSPEC_PLTOFF : return TARGET_64BIT ; case UNSPEC_TPOFF : case UNSPEC_NTPOFF : x = XVECEXP ( x , 0 , 0 ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_EXEC ) ; case UNSPEC_DTPOFF : x = XVECEXP ( x , 0 , 0 ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_DYNAMIC ) ; default : return false ; } if ( GET_CODE ( x ) == LABEL_REF ) return true ; if ( GET_CODE ( x ) != SYMBOL_REF ) return false ; case SYMBOL_REF : if ( SYMBOL_REF_TLS_MODEL ( x ) ) return false ; if ( TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P ( x ) ) return false ; if ( MACHO_DYNAMIC_NO_PIC_P ) return machopic_symbol_defined_p ( x ) ; if ( ix86_force_load_from_GOT_p ( x ) ) return false ; break ; CASE_CONST_SCALAR_INT : if ( ix86_endbr_immediate_operand ( x , VOIDmode ) ) return false ; switch ( mode ) { case E_TImode : if ( TARGET_64BIT ) return true ; case E_OImode : case E_XImode : if ( ! standard_sse_constant_p ( x , mode ) && GET_MODE_SIZE ( TARGET_AVX512F ? XImode : ( TARGET_AVX ? OImode : ( TARGET_SSE2 ? TImode : DImode ) ) ) < GET_MODE_SIZE ( mode ) ) return false ; default : break ; } break ; case CONST_VECTOR : if ( ! standard_sse_constant_p ( x , mode ) ) return false ; default : break ; } return true ; } </s>

Determine if a given RTX is a valid constant . We already know this satisfies CONSTANT_P .


<s>
const
uint32_t
*
RISCVRegisterInfo
::
getCallPreservedMask
(
const
MachineFunction
&
MF
,
CallingConv
::
ID
CC
)
const
{
auto
&
Subtarget
=
MF
.
getSubtarget
<
RISCVSubtarget
>
(
)
;
if
(
CC
==
CallingConv
::
GHC
)
return
CSR_NoRegs_RegMask
;
switch
(
Subtarget
.
getTargetABI
(
)
)
{
default
:
llvm_unreachable
(
"Unrecognized ABI"
)
;
case
RISCVABI
::
ABI_ILP32
:
case
RISCVABI
::
ABI_LP64
:
return
CSR_ILP32_LP64_RegMask
;
case
RISCVABI
::
ABI_ILP32F
:
case
RISCVABI
::
ABI_LP64F
:
return
CSR_ILP32F_LP64F_RegMask
;
case
RISCVABI
::
ABI_ILP32D
:
case
RISCVABI
::
ABI_LP64D
:
return
CSR_ILP32D_LP64D_RegMask
;
}
}
</s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> unsigned PPCRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; const unsigned DefaultSafety = 1 ; switch ( RC -> getID ( ) ) { default : return 0 ; case PPC :: G8RCRegClassID : case PPC :: GPRCRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 32 - FP - DefaultSafety ; } case PPC :: F8RCRegClassID : case PPC :: F4RCRegClassID : case PPC :: VRRCRegClassID : return 32 - DefaultSafety ; case PPC :: CRRCRegClassID : return 8 - DefaultSafety ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> bool pass_vsetvl :: forward_demand_fusion ( void ) { bool changed_p = false ; for ( const bb_info * bb : crtl -> ssa -> bbs ( ) ) { basic_block cfg_bb = bb -> cfg_bb ( ) ; const auto & prop = m_vector_manager -> vector_block_infos [ cfg_bb -> index ] . reaching_out ; if ( ! prop . valid_or_dirty_p ( ) ) continue ; if ( cfg_bb == ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) continue ; if ( vsetvl_insn_p ( prop . get_insn ( ) -> rtl ( ) ) ) continue ; edge e ; edge_iterator ei ; FOR_EACH_EDGE ( e , ei , cfg_bb -> succs ) { auto & local_dem = m_vector_manager -> vector_block_infos [ e -> dest -> index ] . local_dem ; auto & reaching_out = m_vector_manager -> vector_block_infos [ e -> dest -> index ] . reaching_out ; if ( e -> dest -> index == cfg_bb -> index ) continue ; if ( e -> flags & EDGE_COMPLEX ) continue ; if ( e -> dest -> index == EXIT_BLOCK_PTR_FOR_FN ( cfun ) -> index ) continue ; if ( ! local_dem . valid_or_dirty_p ( ) ) continue ; if ( local_dem . available_p ( prop ) ) continue ; if ( ! local_dem . compatible_p ( prop ) ) continue ; if ( propagate_avl_across_demands_p ( prop , local_dem ) ) continue ; vector_insn_info new_info = local_dem . merge ( prop , GLOBAL_MERGE ) ; new_info . set_insn ( local_dem . get_insn ( ) ) ; if ( local_dem . dirty_p ( ) ) { gcc_assert ( local_dem == reaching_out ) ; new_info . set_dirty ( local_dem . dirty_with_killed_avl_p ( ) ) ; local_dem = new_info ; reaching_out = local_dem ; } else { if ( reaching_out == local_dem ) reaching_out = new_info ; local_dem = new_info ; change_vsetvl_insn ( local_dem . get_insn ( ) , new_info ) ; } auto & prob = m_vector_manager -> vector_block_infos [ e -> dest -> index ] . probability ; auto & curr_prob = m_vector_manager -> vector_block_infos [ cfg_bb -> index ] . probability ; prob = curr_prob * e -> probability ; changed_p = true ; } } return changed_p ; } </s>


<s> VESubtarget & VESubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "ve" ; ParseSubtargetFeatures ( CPUName , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


This function is used to print CPU tuning information as comment in assembler file . Pointers are not printed for now .


<s> bool isReg ( ) const override { return Kind == k_Register ; } </s>


<s> bool SIRegisterInfo :: shouldCoalesce ( MachineInstr * MI , const TargetRegisterClass * SrcRC , unsigned SubReg , const TargetRegisterClass * DstRC , unsigned DstSubReg , const TargetRegisterClass * NewRC ) const { unsigned SrcSize = SrcRC -> getSize ( ) ; unsigned DstSize = DstRC -> getSize ( ) ; unsigned NewSize = NewRC -> getSize ( ) ; if ( SrcSize <= 4 || DstSize <= 4 ) return true ; return NewSize <= DstSize || NewSize <= SrcSize ; } </s>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { X86MachineFunctionInfo * MFI = MF . getInfo < X86MachineFunctionInfo > ( ) ; if ( MFI -> getNumLocalDynamicTLSAccesses ( ) < 2 ) { return false ; } MachineDominatorTree * DT = & getAnalysis < MachineDominatorTree > ( ) ; return VisitNode ( DT -> getRootNode ( ) , 0 ) ; } </s>


"bad insn to frv_print_operand_address:"

Print a memory address as an operand to reference that memory location .


<s> Register getExceptionSelectorRegister ( const Constant * PersonalityFn ) const override { return ABI . IsN64 ( ) ? Mips :: A1_64 : Mips :: A1 ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .


<s> static void check_store_cacheline_hazard ( void ) { rtx_insn * insn , * succ0 , * insn1 ; bool found = false ; for ( insn = get_insns ( ) ; insn ; insn = arc_active_insn ( insn ) ) { succ0 = arc_active_insn ( insn ) ; if ( ! succ0 ) return ; if ( ! single_set ( insn ) ) continue ; if ( ( get_attr_type ( insn ) != TYPE_STORE ) ) continue ; for ( insn1 = succ0 ; insn1 ; insn1 = arc_active_insn ( insn1 ) ) if ( ! single_set ( insn1 ) || get_attr_type ( insn1 ) != TYPE_STORE ) break ; succ0 = insn1 ; if ( insn1 && single_set ( insn1 ) && ( get_attr_type ( insn1 ) == TYPE_LOAD ) ) { found = true ; emit_insn_before ( gen_nopv ( ) , insn1 ) ; emit_insn_before ( gen_nopv ( ) , insn1 ) ; } else { if ( insn1 && ( get_attr_type ( insn1 ) == TYPE_COMPARE ) ) { add_reg_note ( insn1 , REG_SAVE_NOTE , GEN_INT ( 3 ) ) ; } insn1 = arc_active_insn ( insn1 ) ; if ( insn1 && single_set ( insn1 ) && ( get_attr_type ( insn1 ) == TYPE_LOAD ) ) { found = true ; emit_insn_before ( gen_nopv ( ) , insn1 ) ; } } if ( found ) { insn = insn1 ; found = false ; } else insn = succ0 ; } } </s>

Search for a sequence made out of two stores and a given number of loads , insert a nop if required .


<s> static rtx moxie_function_value ( const_tree valtype , const_tree fntype_or_decl ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( TYPE_MODE ( valtype ) , MOXIE_R0 ) ; } </s>

Define how to find the value returned by a function . VALTYPE is the data type of the value ( as a tree ) . If the precise function being called is known , FUNC is its FUNCTION_DECL ; otherwise , FUNC is 0 . We always return values in register $ r0 for moxie .


<s> bool ThunkInserter < Derived > :: run ( MachineModuleInfo & MMI , MachineFunction & MF ) { if ( ! MF . getName ( ) . startswith ( getDerived ( ) . getThunkPrefix ( ) ) ) { if ( InsertedThunks ) return false ; if ( ! getDerived ( ) . mayUseThunk ( MF ) ) return false ; getDerived ( ) . insertThunks ( MMI ) ; InsertedThunks = true ; return true ; } getDerived ( ) . populateThunk ( MF ) ; return true ; } </s>

Run the analysis pass over a function and produce a dominator tree .


<s> unsigned CFStack :: getLoopDepth ( ) { return LoopStack . size ( ) ; } </s>

Return the loop nesting level of the specified block .


<s> SDValue AMDGPUTargetLowering :: SplitVectorLoad ( const SDValue Op , SelectionDAG & DAG ) const { LoadSDNode * Load = cast < LoadSDNode > ( Op ) ; EVT VT = Op . getValueType ( ) ; SDLoc SL ( Op ) ; if ( VT . getVectorNumElements ( ) == 2 ) { SDValue Ops [ 2 ] ; std :: tie ( Ops [ 0 ] , Ops [ 1 ] ) = scalarizeVectorLoad ( Load , DAG ) ; return DAG . getMergeValues ( Ops , SL ) ; } SDValue BasePtr = Load -> getBasePtr ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; const MachinePointerInfo & SrcValue = Load -> getMemOperand ( ) -> getPointerInfo ( ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = getSplitDestVTs ( VT , DAG ) ; std :: tie ( LoMemVT , HiMemVT ) = getSplitDestVTs ( MemVT , DAG ) ; std :: tie ( Lo , Hi ) = splitVector ( Op , SL , LoVT , HiVT , DAG ) ; unsigned Size = LoMemVT . getStoreSize ( ) ; unsigned BaseAlign = Load -> getAlignment ( ) ; unsigned HiAlign = MinAlign ( BaseAlign , Size ) ; SDValue LoLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , LoVT , Load -> getChain ( ) , BasePtr , SrcValue , LoMemVT , BaseAlign , Load -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue HiPtr = DAG . getObjectPtrOffset ( SL , BasePtr , Size ) ; SDValue HiLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , HiVT , Load -> getChain ( ) , HiPtr , SrcValue . getWithOffset ( LoMemVT . getStoreSize ( ) ) , HiMemVT , HiAlign , Load -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Join ; if ( LoVT == HiVT ) { Join = DAG . getNode ( ISD :: CONCAT_VECTORS , SL , VT , LoLoad , HiLoad ) ; } else { Join = DAG . getNode ( ISD :: INSERT_SUBVECTOR , SL , VT , DAG . getUNDEF ( VT ) , LoLoad , DAG . getVectorIdxConstant ( 0 , SL ) ) ; Join = DAG . getNode ( HiVT . isVector ( ) ? ISD :: INSERT_SUBVECTOR : ISD :: INSERT_VECTOR_ELT , SL , VT , Join , HiLoad , DAG . getVectorIdxConstant ( LoVT . getVectorNumElements ( ) , SL ) ) ; } SDValue Ops [ ] = { Join , DAG . getNode ( ISD :: TokenFactor , SL , MVT :: Other , LoLoad . getValue ( 1 ) , HiLoad . getValue ( 1 ) ) } ; return DAG . getMergeValues ( Ops , SL ) ; } </s>

Split a vector load into 2 loads of half the vector .


<s> void s390_d_register_target_info ( void ) { const struct d_target_info_spec handlers [ ] = { { "floatAbi" , s390_d_handle_target_float_abi } , { NULL , NULL } , } ; d_add_target_info_handlers ( handlers ) ; } </s>


<s> int m32c_reg_ok_for_base_p ( rtx x , int strict ) { if ( GET_CODE ( x ) != REG ) return 0 ; switch ( REGNO ( x ) ) { case A0_REGNO : case A1_REGNO : case SB_REGNO : case FB_REGNO : case SP_REGNO : return 1 ; default : if ( IS_PSEUDO ( x , strict ) ) return 1 ; return 0 ; } } </s>


<s>
static
bool
avr_assemble_integer
(
rtx
x
,
unsigned
int
size
,
int
aligned_p
)
{
if
(
size
==
POINTER_SIZE
/
BITS_PER_UNIT
&&
aligned_p
&&
text_segment_operand
(
x
,
VOIDmode
)
)
{
fputs
(
"\t.word\tgs("
,
asm_out_file
)
;
output_addr_const
(
asm_out_file
,
x
)
;
fputs
(
")\n"
,
asm_out_file
)
;
return
true
;
}
else
if
(
GET_MODE
(
x
)
==
PSImode
)
{
fputs
(
"\t.byte\tlo8("
,
asm_out_file
)
;
output_addr_const
(
asm_out_file
,
x
)
;
fputs
(
")"
ASM_COMMENT_START
"need binutils PR13503\n"
,
asm_out_file
)
;
fputs
(
"\t.byte\thi8("
,
asm_out_file
)
;
output_addr_const
(
asm_out_file
,
x
)
;
fputs
(
")"
ASM_COMMENT_START
"need binutils PR13503\n"
,
asm_out_file
)
;
fputs
(
"\t.byte\thh8("
,
asm_out_file
)
;
output_addr_const
(
asm_out_file
,
x
)
;
fputs
(
")"
ASM_COMMENT_START
"need binutils PR13503\n"
,
asm_out_file
)
;
return
true
;
}
else
if
(
CONST_FIXED_P
(
x
)
)
{
for
(
unsigned
n
=
0
;
n
<
size
;
n
++
)
{
rtx
xn
=
simplify_gen_subreg
(
QImode
,
x
,
GET_MODE
(
x
)
,
n
)
;
default_assemble_integer
(
xn
,
1
,
aligned_p
)
;
}
return
true
;
}
if
(
AVR_TINY
&&
avr_address_tiny_pm_p
(
x
)
)
{
x
=
plus_constant
(
Pmode
,
x
,
AVR_TINY_PM_OFFSET
)
;
}
return
default_assemble_integer
(
x
,
size
,
aligned_p
)
;
}
</s>

Target hook for assembling integer objects . The AVR version needs special handling for references to certain labels .


<s> TPCAAResult run ( Function & F , AnalysisManager < Function > & AM ) { return TPCAAResult ( ) ; } </s>


<s> bool ARM64PassConfig :: addPreSched2 ( ) { addPass ( createARM64ExpandPseudoPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableLoadStoreOpt ) addPass ( createARM64LoadStoreOptimizationPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> static int arm_save_coproc_regs ( void ) { int saved_size = 0 ; unsigned reg ; unsigned start_reg ; rtx insn ; for ( reg = LAST_IWMMXT_REGNUM ; reg >= FIRST_IWMMXT_REGNUM ; reg -- ) if ( df_regs_ever_live_p ( reg ) && ! call_used_regs [ reg ] ) { insn = gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ; insn = gen_rtx_MEM ( V2SImode , insn ) ; insn = emit_set_insn ( insn , gen_rtx_REG ( V2SImode , reg ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; saved_size += 8 ; } if ( TARGET_HARD_FLOAT && TARGET_VFP ) { start_reg = FIRST_VFP_REGNUM ; for ( reg = FIRST_VFP_REGNUM ; reg < LAST_VFP_REGNUM ; reg += 2 ) { if ( ( ! df_regs_ever_live_p ( reg ) || call_used_regs [ reg ] ) && ( ! df_regs_ever_live_p ( reg + 1 ) || call_used_regs [ reg + 1 ] ) ) { if ( start_reg != reg ) saved_size += vfp_emit_fstmd ( start_reg , ( reg - start_reg ) / 2 ) ; start_reg = reg + 2 ; } } if ( start_reg != reg ) saved_size += vfp_emit_fstmd ( start_reg , ( reg - start_reg ) / 2 ) ; } return saved_size ; } </s>

Emit RTL to save coprocessor registers on function entry . Returns the number of bytes pushed .


<s>
void
XtensaInstrInfo
::
insertNoop
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
)
const
{
llvm_unreachable
(
"Unimplemented operand"
)
;
}
</s>

Insert a noop into the instruction stream at the specified point .


<s>
unsigned
AArch64MCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
)
const
{
if
(
MO
.
isReg
(
)
)
{
return
Ctx
.
getRegisterInfo
(
)
.
getEncodingValue
(
MO
.
getReg
(
)
)
;
}
else
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
llvm_unreachable
(
"Unable to encode MCOperand!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> void PPCScoreboardHazardRecognizer :: EmitInstruction ( SUnit * SU ) { const MCInstrDesc * MCID = DAG -> getInstrDesc ( SU ) ; if ( ! MCID ) return ; ScoreboardHazardRecognizer :: EmitInstruction ( SU ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .