<s> SDNode * SparcDAGToDAGISel :: Select ( SDNode * N ) { SDLoc dl ( N ) ; if ( N -> isMachineOpcode ( ) ) { N -> setNodeId ( - 1 ) ; return nullptr ; } switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: INLINEASM : { SDNode * ResNode = SelectInlineAsm ( N ) ; if ( ResNode ) return ResNode ; break ; } case SPISD :: GLOBAL_BASE_REG : return getGlobalBaseReg ( ) ; case ISD :: SDIV : case ISD :: UDIV : { if ( N -> getValueType ( 0 ) == MVT :: i64 ) break ; SDValue DivLHS = N -> getOperand ( 0 ) ; SDValue DivRHS = N -> getOperand ( 1 ) ; SDValue TopPart ; if ( N -> getOpcode ( ) == ISD :: SDIV ) { TopPart = SDValue ( CurDAG -> getMachineNode ( SP :: SRAri , dl , MVT :: i32 , DivLHS , CurDAG -> getTargetConstant ( 31 , dl , MVT :: i32 ) ) , 0 ) ; } else { TopPart = CurDAG -> getRegister ( SP :: G0 , MVT :: i32 ) ; } TopPart = CurDAG -> getCopyToReg ( CurDAG -> getEntryNode ( ) , dl , SP :: Y , TopPart , SDValue ( ) ) . getValue ( 1 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: SDIV ? SP :: SDIVrr : SP :: UDIVrr ; return CurDAG -> SelectNodeTo ( N , Opcode , MVT :: i32 , DivLHS , DivRHS , TopPart ) ; } case ISD :: MULHU : case ISD :: MULHS : { SDValue MulLHS = N -> getOperand ( 0 ) ; SDValue MulRHS = N -> getOperand ( 1 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: MULHU ? SP :: UMULrr : SP :: SMULrr ; SDNode * Mul = CurDAG -> getMachineNode ( Opcode , dl , MVT :: i32 , MVT :: i32 , MulLHS , MulRHS ) ; SDValue ResultHigh = SDValue ( Mul , 1 ) ; ReplaceUses ( SDValue ( N , 0 ) , ResultHigh ) ; return nullptr ; } } return SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> InstructionCost ARMTTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind , Instruction * Inst ) { if ( ( Opcode == Instruction :: SDiv || Opcode == Instruction :: UDiv || Opcode == Instruction :: SRem || Opcode == Instruction :: URem ) && Idx == 1 ) return 0 ; if ( Opcode == Instruction :: GetElementPtr && Idx != 0 ) return 0 ; if ( Opcode == Instruction :: And ) { if ( Imm == 255 || Imm == 65535 ) return 0 ; return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( ~ Imm , Ty , CostKind ) ) ; } if ( Opcode == Instruction :: Add ) return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( - Imm , Ty , CostKind ) ) ; if ( Opcode == Instruction :: ICmp && Imm . isNegative ( ) && Ty -> getIntegerBitWidth ( ) == 32 ) { int64_t NegImm = - Imm . getSExtValue ( ) ; if ( ST -> isThumb2 ( ) && NegImm < 1 << 12 ) return 0 ; if ( ST -> isThumb ( ) && NegImm < 1 << 8 ) return 0 ; } if ( Opcode == Instruction :: Xor && Imm . isAllOnes ( ) ) return 0 ; if ( Inst && ( ( ST -> hasV6Ops ( ) && ! ST -> isThumb ( ) ) || ST -> isThumb2 ( ) ) && Ty -> getIntegerBitWidth ( ) <= 32 ) { if ( isSSATMinMaxPattern ( Inst , Imm ) || ( isa < ICmpInst > ( Inst ) && Inst -> hasOneUse ( ) && isSSATMinMaxPattern ( cast < Instruction > ( * Inst -> user_begin ( ) ) , Imm ) ) ) return 0 ; } if ( Inst && ST -> hasVFP2Base ( ) && isFPSatMinMaxPattern ( Inst , Imm ) ) return 0 ; if ( Inst && Opcode == Instruction :: ICmp && Idx == 1 && Imm . isAllOnesValue ( ) ) { ICmpInst :: Predicate Pred = cast < ICmpInst > ( Inst ) -> getPredicate ( ) ; if ( Pred == ICmpInst :: ICMP_SGT || Pred == ICmpInst :: ICMP_SLE ) return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( Imm + 1 , Ty , CostKind ) ) ; } return getIntImmCost ( Imm , Ty , CostKind ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


"Constant Island pass failed to converge!"

"Branch Fix Up pass failed to converge!"

runOnMachineFunction - Emit the function body .


<s> static void init_alignment_context ( struct alignment_context * ac , rtx mem , machine_mode mode ) { ac -> shift = GEN_INT ( GET_MODE_SIZE ( SImode ) - GET_MODE_SIZE ( mode ) ) ; ac -> aligned = ( MEM_ALIGN ( mem ) >= GET_MODE_BITSIZE ( SImode ) ) ; if ( ac -> aligned ) ac -> memsi = adjust_address ( mem , SImode , 0 ) ; else { rtx byteoffset , addr , align ; addr = force_reg ( Pmode , XEXP ( mem , 0 ) ) ; align = expand_simple_binop ( Pmode , AND , addr , GEN_INT ( - GET_MODE_SIZE ( SImode ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ; ac -> memsi = gen_rtx_MEM ( SImode , align ) ; MEM_VOLATILE_P ( ac -> memsi ) = MEM_VOLATILE_P ( mem ) ; set_mem_alias_set ( ac -> memsi , ALIAS_SET_MEMORY_BARRIER ) ; set_mem_align ( ac -> memsi , GET_MODE_BITSIZE ( SImode ) ) ; byteoffset = expand_simple_binop ( Pmode , AND , addr , GEN_INT ( GET_MODE_SIZE ( SImode ) - 1 ) , NULL_RTX , 1 , OPTAB_DIRECT ) ; ac -> shift = expand_simple_binop ( SImode , MINUS , ac -> shift , byteoffset , NULL_RTX , 1 , OPTAB_DIRECT ) ; } ac -> shift = expand_simple_binop ( SImode , ASHIFT , ac -> shift , GEN_INT ( 3 ) , NULL_RTX , 1 , OPTAB_DIRECT ) ; ac -> modemask = expand_simple_binop ( SImode , ASHIFT , GEN_INT ( GET_MODE_MASK ( mode ) ) , ac -> shift , NULL_RTX , 1 , OPTAB_DIRECT ) ; ac -> modemaski = expand_simple_unop ( SImode , NOT , ac -> modemask , NULL_RTX , 1 ) ; } </s>

Initialize structure AC for word access to HI and QI mode memory .


<s> unsigned AMDGPUCommonSubtarget :: getMaxLocalMemSizeWithWaveCount ( unsigned NWaves , const Function & F ) const { if ( NWaves == 1 ) return getLocalMemorySize ( ) ; unsigned WorkGroupSize = getFlatWorkGroupSizes ( F ) . second ; unsigned WorkGroupsPerCu = getMaxWorkGroupsPerCU ( WorkGroupSize ) ; unsigned MaxWaves = getMaxWavesPerEU ( ) ; return getLocalMemorySize ( ) * MaxWaves / WorkGroupsPerCu / NWaves ; } </s>

Return the amount of LDS that can be used that will not restrict the occupancy lower than WaveCount .


<s> unsigned getReg ( ) const override { return Reg . RegNo ; } </s>

Returns the register associated with this edge .


<s> static void s390_reorg ( void ) { bool pool_overflow = false ; int hw_before , hw_after ; if ( s390_tune == PROCESSOR_2964_Z13 ) s390_adjust_loops ( ) ; split_all_insns_noflow ( ) ; for ( ; ; ) { struct constant_pool * pool = NULL ; if ( ! pool_overflow ) { pool = s390_mainpool_start ( ) ; if ( ! pool ) pool_overflow = true ; } if ( pool_overflow ) pool = s390_chunkify_start ( ) ; if ( ! TARGET_CPU_ZARCH && s390_split_branches ( ) ) { if ( pool_overflow ) s390_chunkify_cancel ( pool ) ; else s390_mainpool_cancel ( pool ) ; continue ; } if ( pool_overflow ) s390_chunkify_finish ( pool ) ; else s390_mainpool_finish ( pool ) ; cfun -> machine -> split_branches_pending_p = false ; break ; } if ( TARGET_CPU_ZARCH ) { rtx_insn * insn , * target ; rtx label ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { label = s390_execute_label ( insn ) ; if ( ! label ) continue ; gcc_assert ( label != const0_rtx ) ; target = emit_label ( XEXP ( label , 0 ) ) ; INSN_ADDRESSES_NEW ( target , - 1 ) ; target = emit_insn ( s390_execute_target ( insn ) ) ; INSN_ADDRESSES_NEW ( target , - 1 ) ; } } s390_optimize_prologue ( ) ; if ( s390_tune >= PROCESSOR_2097_Z10 ) { rtx_insn * insn ; bool insn_added_p = false ; shorten_branches ( get_insns ( ) ) ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( ! INSN_P ( insn ) || INSN_CODE ( insn ) <= 0 ) continue ; if ( JUMP_P ( insn ) ) insn_added_p |= s390_fix_long_loop_prediction ( insn ) ; if ( ( GET_CODE ( PATTERN ( insn ) ) == PARALLEL || GET_CODE ( PATTERN ( insn ) ) == SET ) && s390_tune == PROCESSOR_2097_Z10 ) insn_added_p |= s390_z10_optimize_cmp ( insn ) ; } if ( insn_added_p ) shorten_branches ( get_insns ( ) ) ; } s390_function_num_hotpatch_hw ( current_function_decl , & hw_before , & hw_after ) ; if ( hw_after > 0 ) { rtx_insn * insn ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( active_insn_p ( insn ) || BARRIER_P ( insn ) || LABEL_P ( insn ) ) break ; while ( insn && hw_after > 0 ) { if ( hw_after >= 3 && TARGET_CPU_ZARCH ) { emit_insn_before ( gen_nop_6_byte ( ) , insn ) ; hw_after -= 3 ; } else if ( hw_after >= 2 ) { emit_insn_before ( gen_nop_4_byte ( ) , insn ) ; hw_after -= 2 ; } else { emit_insn_before ( gen_nop_2_byte ( ) , insn ) ; hw_after -= 1 ; } } } } </s>


<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < 512 > Key ; Key . reserve ( CPU . size ( ) + FS . size ( ) ) ; Key += CPU ; Key += FS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) Key += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; FS = Key . substr ( CPU . size ( ) ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < X86Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; X86GISelActualAccessor * GISel = new X86GISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new X86CallLowering ( * I -> getTargetLowering ( ) ) ) ; GISel -> Legalizer . reset ( new X86LegalizerInfo ( * I ) ) ; auto * RBI = new X86RegisterBankInfo ( * I -> getRegisterInfo ( ) ) ; GISel -> RegBankInfo . reset ( RBI ) ; I -> setGISelAccessor ( * GISel ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> unsigned SICRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? ( SIC :: X ) : ( SIC :: X ) ; } </s>


<s> SDNode * MipsTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallSDNode * TheCall , unsigned CallingConv , SelectionDAG & DAG ) { bool isVarArg = TheCall -> isVarArg ( ) ; DebugLoc dl = TheCall -> getDebugLoc ( ) ; SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallingConv , isVarArg , getTargetMachine ( ) , RVLocs ) ; CCInfo . AnalyzeCallResult ( TheCall , RetCC_Mips ) ; SmallVector < SDValue , 8 > ResultVals ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; ResultVals . push_back ( Chain . getValue ( 0 ) ) ; } ResultVals . push_back ( Chain ) ; return DAG . getNode ( ISD :: MERGE_VALUES , dl , TheCall -> getVTList ( ) , & ResultVals [ 0 ] , ResultVals . size ( ) ) . getNode ( ) ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> void MipsELFStreamer :: EmitMipsOptionRecords ( ) { for ( const auto & I : MipsOptionRecords ) I -> EmitMipsOptionRecord ( ) ; } </s>

Emits all the option records stored up until the point it 's called .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"AArch64 Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static int s390_builtin_vectorization_cost ( enum vect_cost_for_stmt type_of_cost , tree vectype , int misalign ATTRIBUTE_UNUSED ) { switch ( type_of_cost ) { case scalar_stmt : case scalar_load : case scalar_store : case vector_stmt : case vector_load : case vector_store : case vec_to_scalar : case scalar_to_vec : case cond_branch_not_taken : case vec_perm : case vec_promote_demote : case unaligned_load : case unaligned_store : return 1 ; case cond_branch_taken : return 3 ; case vec_construct : return TYPE_VECTOR_SUBPARTS ( vectype ) - 1 ; default : gcc_unreachable ( ) ; } } </s>


"A single use instruction with no uses."

Return true if it is profitable to hoist instruction in the then/else to before if .


<s> bool SNESInstrumentFunctions :: runOnFunction ( Function & F ) { if ( ShouldInstrument ( F ) ) { BuildEntryBlock ( F ) ; BuildExitHooks ( F ) ; } return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"WebAssembly Optimize Live Intervals"
;
}
</s>

WebAssembly
"WebAssembly Optimize Live Intervals"


<s> void init_68881_table ( void ) { int i ; REAL_VALUE_TYPE r ; enum machine_mode mode ; mode = SFmode ; for ( i = 0 ; i < 7 ; i ++ ) { if ( i == 6 ) mode = DFmode ; r = REAL_VALUE_ATOF ( strings_68881 [ i ] , mode ) ; values_68881 [ i ] = r ; } inited_68881_table = 1 ; } </s>

Set up values_68881 array by converting the decimal values strings_68881 to binary .


<s> void mips_output_ascii ( FILE * stream , const char * string_param , size_t len , const char * prefix ) { size_t i ; int cur_pos = 17 ; register const unsigned char * string = ( const unsigned char * ) string_param ; fprintf ( stream , "%s\"" , prefix ) ; for ( i = 0 ; i < len ; i ++ ) { register int c = string [ i ] ; if ( ISPRINT ( c ) ) { if ( c == '\\' || c == '\"' ) { putc ( '\\' , stream ) ; cur_pos ++ ; } putc ( c , stream ) ; cur_pos ++ ; } else { fprintf ( stream , "\\%03o" , c ) ; cur_pos += 4 ; } if ( cur_pos > 72 && i + 1 < len ) { cur_pos = 17 ; fprintf ( stream , "\"\n%s\"" , prefix ) ; } } fprintf ( stream , "\"\n" ) ; } </s>

Output an ASCII string , in a space-saving way . PREFIX is the string that should be written before the opening quote , such as `` \t.ascii\t '' for real string data or `` \t # `` for a comment .


<s>
SDValue
LanaiTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
switch
(
CallConv
)
{
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
IsVarArg
,
Ins
,
DL
,
DAG
,
InVals
)
;
default
:
report_fatal_error
(
"Unsupported calling convention"
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .

Lanai
Lanai
ISD::InputArg
"Unsupported calling convention"


"instruction use requires an option to be enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s>
bool
VLIWResourceModel
::
reserveResources
(
SUnit
*
SU
,
bool
IsTop
)
{
bool
startNewCycle
=
false
;
if
(
!
SU
)
{
ResourcesModel
->
clearResources
(
)
;
Packet
.
clear
(
)
;
TotalPackets
++
;
return
false
;
}
if
(
!
isResourceAvailable
(
SU
,
IsTop
)
||
Packet
.
size
(
)
>=
SchedModel
->
getIssueWidth
(
)
)
{
ResourcesModel
->
clearResources
(
)
;
Packet
.
clear
(
)
;
TotalPackets
++
;
startNewCycle
=
true
;
}
switch
(
SU
->
getInstr
(
)
->
getOpcode
(
)
)
{
default
:
ResourcesModel
->
reserveResources
(
*
SU
->
getInstr
(
)
)
;
break
;
case
TargetOpcode
::
EXTRACT_SUBREG
:
case
TargetOpcode
::
INSERT_SUBREG
:
case
TargetOpcode
::
SUBREG_TO_REG
:
case
TargetOpcode
::
REG_SEQUENCE
:
case
TargetOpcode
::
IMPLICIT_DEF
:
case
TargetOpcode
::
KILL
:
case
TargetOpcode
::
CFI_INSTRUCTION
:
case
TargetOpcode
::
EH_LABEL
:
case
TargetOpcode
::
COPY
:
case
TargetOpcode
::
INLINEASM
:
break
;
}
Packet
.
push_back
(
SU
)
;
DEBUG
(
dbgs
(
)
<<
"Packet["
<<
TotalPackets
<<
"]:\n"
)
;
for
(
unsigned
i
=
0
,
e
=
Packet
.
size
(
)
;
i
!=
e
;
++
i
)
{
DEBUG
(
dbgs
(
)
<<
"\t["
<<
i
<<
"] SU("
)
;
DEBUG
(
dbgs
(
)
<<
Packet
[
i
]
->
NodeNum
<<
")\t"
)
;
DEBUG
(
Packet
[
i
]
->
getInstr
(
)
->
dump
(
)
)
;
}
return
startNewCycle
;
}
</s>


<s> static bool arc_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { if ( AGGREGATE_TYPE_P ( type ) || TREE_ADDRESSABLE ( type ) ) return true ; else { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; return ( size == - 1 || size > ( TARGET_V2 ? 16 : 8 ) ) ; } } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


<s> static void ix86_emit_restore_sse_regs_using_mov ( HOST_WIDE_INT cfa_offset , bool maybe_eh_return ) { unsigned int regno ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( SSE_REGNO_P ( regno ) && ix86_save_reg ( regno , maybe_eh_return ) ) { rtx reg = gen_rtx_REG ( V4SFmode , regno ) ; rtx mem ; unsigned int align ; mem = choose_baseaddr ( cfa_offset ) ; mem = gen_rtx_MEM ( V4SFmode , mem ) ; align = MIN ( GET_MODE_ALIGNMENT ( V4SFmode ) , INCOMING_STACK_BOUNDARY ) ; set_mem_align ( mem , align ) ; if ( align < 128 ) { rtx unspec = gen_rtx_UNSPEC ( V4SFmode , gen_rtvec ( 1 , mem ) , UNSPEC_LOADU ) ; emit_insn ( gen_rtx_SET ( reg , unspec ) ) ; } else emit_insn ( gen_rtx_SET ( reg , mem ) ) ; ix86_add_cfa_restore_note ( NULL , reg , cfa_offset ) ; cfa_offset -= GET_MODE_SIZE ( V4SFmode ) ; } } </s>

Emit code to restore saved registers using MOV insns . First register is restored from CFA - CFA_OFFSET .


<s> bool RISCVTargetLowering :: shouldExtendTypeInLibCall ( EVT Type ) const { RISCVABI :: ABI ABI = Subtarget . getTargetABI ( ) ; if ( ( ABI == RISCVABI :: ABI_LP64 || ABI == RISCVABI :: ABI_L64PC128 ) && ( Type == MVT :: f32 ) ) return false ; return true ; } </s>

Returns true if arguments should be extended in lib calls .


<s> void RISCVAsmPrinter :: emitBasicBlockStart ( const MachineBasicBlock & MBB ) { AsmPrinter :: emitBasicBlockStart ( MBB ) ; auto * RVFI = MF -> getInfo < RISCVMachineFunctionInfo > ( ) ; RISCVTargetStreamer & RTS = static_cast < RISCVTargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; if ( RVFI -> isHwlpBasicBlock ( & MBB ) ) { RTS . emitDirectiveOptionPush ( ) ; RTS . emitDirectiveOptionNoRVC ( ) ; } } </s>

Targets can override this to emit stuff at the start of a basic block .


<s> bool X86TargetLowering :: shouldScalarizeBinop ( SDValue VecOp ) const { unsigned Opc = VecOp . getOpcode ( ) ; if ( Opc >= ISD :: BUILTIN_OP_END ) return false ; EVT VecVT = VecOp . getValueType ( ) ; if ( ! isOperationLegalOrCustomOrPromote ( Opc , VecVT ) ) return true ; EVT ScalarVT = VecVT . getScalarType ( ) ; return isOperationLegalOrCustomOrPromote ( Opc , ScalarVT ) ; } </s>

Scalar ops always have equal or better analysis/performance/power than the vector equivalent , so this always makes sense if the scalar op is supported .


<s> static bool arm_block_set_vect_profit_p ( unsigned HOST_WIDE_INT length , unsigned HOST_WIDE_INT align , machine_mode mode ) { int num ; bool unaligned_p = ( ( align & 3 ) != 0 ) ; unsigned int nelt = GET_MODE_NUNITS ( mode ) ; num = 1 ; num += ( length + nelt - 1 ) / nelt ; if ( ! unaligned_p && ( length & 3 ) != 0 ) num ++ ; if ( ! unaligned_p && mode == V16QImode ) num -- ; return ( num <= arm_block_set_max_insns ( ) ) ; } </s>

Return TRUE if it 's profitable to set block of memory for vectorized case . LENGTH is the number of bytes to set . ALIGN is the alignment of destination memory in bytes . MODE is the vector mode used to set the memory .


<s> static void expand_block_set_4 ( rtx dst , rtx dst_reg , rtx value_rtx , rtx bytes_rtx ) { unsigned HOST_WIDE_INT bytes = UINTVAL ( bytes_rtx ) ; unsigned int rem = bytes % 4 ; value_rtx = convert_to_mode ( Pmode , value_rtx , 1 ) ; emit_library_call ( long_int_memset_libfunc , LCT_NORMAL , VOIDmode , dst_reg , Pmode , value_rtx , Pmode , convert_to_mode ( TYPE_MODE ( sizetype ) , GEN_INT ( bytes >> 2 ) , TYPE_UNSIGNED ( sizetype ) ) , TYPE_MODE ( sizetype ) ) ; if ( rem == 0 ) return ; dst = replace_equiv_address_nv ( dst , dst_reg ) ; bytes -= rem ; if ( rem > 1 ) { if ( CONST_INT_P ( value_rtx ) ) { const unsigned HOST_WIDE_INT value = UINTVAL ( value_rtx ) & 0xff ; emit_move_insn ( adjust_address_nv ( dst , HImode , bytes ) , gen_int_mode ( ( value << 8 ) | value , HImode ) ) ; } else { rtx temp = convert_to_mode ( QImode , value_rtx , 1 ) ; emit_move_insn ( adjust_address_nv ( dst , QImode , bytes ) , temp ) ; emit_move_insn ( adjust_address_nv ( dst , QImode , bytes + 1 ) , temp ) ; } bytes += 2 ; rem -= 2 ; } if ( rem > 0 ) emit_move_insn ( adjust_address_nv ( dst , QImode , bytes ) , convert_to_mode ( QImode , value_rtx , 1 ) ) ; } </s>

Generate a call to a library function to set BYTES_RTX bytes of DST with address DST_REG to VALUE_RTX in 4-byte chunks .


<s> bool DirectXTargetMachine :: addPassesToEmitFile ( PassManagerBase & PM , raw_pwrite_stream & Out , raw_pwrite_stream * DwoOut , CodeGenFileType FileType , bool DisableVerify , MachineModuleInfoWrapperPass * MMIWP ) { switch ( FileType ) { case CGFT_AssemblyFile : PM . add ( createPrintModulePass ( Out , "" , true ) ) ; break ; case CGFT_ObjectFile : PM . add ( createBitcodeWriterPass ( Out , true , false , false ) ) ; break ; case CGFT_Null : break ; } return false ; } </s>

Add passes to the specified pass manager to get the specified file emitted .


<s> BitVector HexagonRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( Hexagon :: R29 ) ; Reserved . set ( Hexagon :: R30 ) ; Reserved . set ( Hexagon :: R31 ) ; Reserved . set ( Hexagon :: SA0 ) ; Reserved . set ( Hexagon :: LC0 ) ; Reserved . set ( Hexagon :: SA1 ) ; Reserved . set ( Hexagon :: LC1 ) ; Reserved . set ( Hexagon :: P3_0 ) ; Reserved . set ( Hexagon :: USR ) ; Reserved . set ( Hexagon :: PC ) ; Reserved . set ( Hexagon :: UGP ) ; Reserved . set ( Hexagon :: GP ) ; Reserved . set ( Hexagon :: CS0 ) ; Reserved . set ( Hexagon :: CS1 ) ; Reserved . set ( Hexagon :: UPCYCLELO ) ; Reserved . set ( Hexagon :: UPCYCLEHI ) ; Reserved . set ( Hexagon :: FRAMELIMIT ) ; Reserved . set ( Hexagon :: FRAMEKEY ) ; Reserved . set ( Hexagon :: PKTCOUNTLO ) ; Reserved . set ( Hexagon :: PKTCOUNTHI ) ; Reserved . set ( Hexagon :: UTIMERLO ) ; Reserved . set ( Hexagon :: UTIMERHI ) ; Reserved . set ( Hexagon :: C8 ) ; Reserved . set ( Hexagon :: USR_OVF ) ; for ( int x = Reserved . find_first ( ) ; x >= 0 ; x = Reserved . find_next ( x ) ) markSuperRegs ( Reserved , x ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool supportSplitCSR ( MachineFunction * MF ) const override { return MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: CXX_FAST_TLS && MF -> getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) ; } </s>

Return true if the target supports that a subset of CSRs for the given machine function is handled explicitly via copies .


<s>
void
P2FrameLowering
::
emitEpilogue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Emit Epilogue: "
<<
MF
.
getName
(
)
<<
"\n"
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
getLastNonDebugInstr
(
)
;
const
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
P2FunctionInfo
*
P2FI
=
MF
.
getInfo
<
P2FunctionInfo
>
(
)
;
const
P2InstrInfo
*
TII
=
MF
.
getSubtarget
<
P2Subtarget
>
(
)
.
getInstrInfo
(
)
;
uint64_t
StackSize
=
MFI
.
getStackSize
(
)
4
P2FI
->
getIncomingArgSize
(
)
;
if
(
StackSize
==
0
)
{
LLVM_DEBUG
(
errs
(
)
<<
"No need to de-allocate stack space\n"
)
;
return
;
}
TII
->
adjustStackPtr
(
P2
::
PTRA
,
StackSize
,
MBB
,
MBBI
)
;
}
</s>


<s> EVT X86TargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i8 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> unsigned int call_properties ( const function_instance & ) const override { return CP_READ_MEMORY | CP_WRITE_CSR ; } </s>

Default implementation of function_base : :call_properties , with conservatively correct behavior for floating-point instructions .


<s>
static
void
mn10300_insert_setlb_lcc
(
rtx
label
,
rtx
branch
)
{
rtx
lcc
,
comparison
,
cmp_reg
;
if
(
LABEL_NUSES
(
label
)
>
1
)
{
rtx_insn
*
insn
;
DUMP
(
"Inserting SETLB insn after:"
,
label
)
;
insn
=
emit_insn_after
(
gen_setlb
(
)
,
label
)
;
label
=
gen_label_rtx
(
)
;
emit_label_after
(
label
,
insn
)
;
DUMP
(
"Created new loop-back label:"
,
label
)
;
}
else
{
DUMP
(
"Inserting SETLB insn before:"
,
label
)
;
emit_insn_before
(
gen_setlb
(
)
,
label
)
;
}
comparison
=
XEXP
(
SET_SRC
(
PATTERN
(
branch
)
)
,
0
)
;
cmp_reg
=
XEXP
(
comparison
,
0
)
;
gcc_assert
(
REG_P
(
cmp_reg
)
)
;
gcc_assert
(
REGNO
(
cmp_reg
)
==
CC_REG
)
;
if
(
GET_MODE
(
cmp_reg
)
==
CC_FLOATmode
)
lcc
=
gen_FLcc
(
comparison
,
label
)
;
else
lcc
=
gen_Lcc
(
comparison
,
label
)
;
rtx_insn
*
jump
=
emit_jump_insn_before
(
lcc
,
branch
)
;
mark_jump_label
(
XVECEXP
(
lcc
,
0
,
0
)
,
jump
,
0
)
;
JUMP_LABEL
(
jump
)
=
label
;
DUMP
(
"Replacing branch insn..."
,
branch
)
;
DUMP
(
"... with Lcc insn:"
,
jump
)
;
delete_insn
(
branch
)
;
}
</s>

Replace the BRANCH insn with a Lcc insn that goes to LABEL . Insert a SETLB insn just before LABEL .


<s> bool GCNTTIImpl :: isSourceOfDivergence ( const Value * V ) const { if ( const Argument * A = dyn_cast < Argument > ( V ) ) return ! AMDGPU :: isArgPassedInSGPR ( A ) ; if ( const LoadInst * Load = dyn_cast < LoadInst > ( V ) ) return Load -> getPointerAddressSpace ( ) == AMDGPUAS :: PRIVATE_ADDRESS || Load -> getPointerAddressSpace ( ) == AMDGPUAS :: FLAT_ADDRESS ; if ( isa < AtomicRMWInst > ( V ) || isa < AtomicCmpXchgInst > ( V ) ) return true ; if ( const IntrinsicInst * Intrinsic = dyn_cast < IntrinsicInst > ( V ) ) return AMDGPU :: isIntrinsicSourceOfDivergence ( Intrinsic -> getIntrinsicID ( ) ) ; if ( const CallInst * CI = dyn_cast < CallInst > ( V ) ) { if ( CI -> isInlineAsm ( ) ) return isInlineAsmSourceOfDivergence ( CI ) ; return true ; } if ( isa < InvokeInst > ( V ) ) return true ; return false ; } </s>

Returns whether V is a source of divergence .

AMDGPU AMDGPU::isArgPassedInSGPR AMDGPU AMDGPU AMDGPU::isIntrinsicSourceOfDivergence


<s> bool MVEGatherScatterLowering :: runOnFunction ( Function & F ) { if ( ! EnableMaskedGatherScatters ) return false ; auto & TPC = getAnalysis < TargetPassConfig > ( ) ; auto & TM = TPC . getTM < TargetMachine > ( ) ; auto * ST = & TM . getSubtarget < ARMSubtarget > ( F ) ; if ( ! ST -> hasMVEIntegerOps ( ) ) return false ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SmallVector < IntrinsicInst * , 4 > Gathers ; SmallVector < IntrinsicInst * , 4 > Scatters ; bool Changed = false ; for ( BasicBlock & BB : F ) { Changed |= SimplifyInstructionsInBlock ( & BB ) ; for ( Instruction & I : BB ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & I ) ; if ( II && II -> getIntrinsicID ( ) == Intrinsic :: masked_gather && isa < FixedVectorType > ( II -> getType ( ) ) ) { Gathers . push_back ( II ) ; Changed |= optimiseAddress ( II -> getArgOperand ( 0 ) , II -> getParent ( ) , LI ) ; } else if ( II && II -> getIntrinsicID ( ) == Intrinsic :: masked_scatter && isa < FixedVectorType > ( II -> getArgOperand ( 0 ) -> getType ( ) ) ) { Scatters . push_back ( II ) ; Changed |= optimiseAddress ( II -> getArgOperand ( 1 ) , II -> getParent ( ) , LI ) ; } } } for ( unsigned i = 0 ; i < Gathers . size ( ) ; i ++ ) { IntrinsicInst * I = Gathers [ i ] ; Instruction * L = lowerGather ( I ) ; if ( L == nullptr ) continue ; SimplifyInstructionsInBlock ( L -> getParent ( ) ) ; Changed = true ; } for ( unsigned i = 0 ; i < Scatters . size ( ) ; i ++ ) { IntrinsicInst * I = Scatters [ i ] ; Instruction * S = lowerScatter ( I ) ; if ( S == nullptr ) continue ; SimplifyInstructionsInBlock ( S -> getParent ( ) ) ; Changed = true ; } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool is64bit ) : LLVMTargetMachine ( T , computeDataLayout ( TT , is64bit ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffectiveSparcCodeModel ( CM , getEffectiveRelocModel ( RM ) , is64bit , JIT ) , OL ) , TLOF ( std :: make_unique < SparcELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this , is64bit ) , is64Bit ( is64bit ) { initAsmInfo ( ) ; } </s>


<s> static void arc_init_reg_tables ( ) { int i ; for ( i = 0 ; i < NUM_MACHINE_MODES ; i ++ ) { switch ( GET_MODE_CLASS ( i ) ) { case MODE_INT : case MODE_PARTIAL_INT : case MODE_COMPLEX_INT : if ( GET_MODE_SIZE ( i ) <= 4 ) arc_mode_class [ i ] = 1 << ( int ) S_MODE ; else if ( GET_MODE_SIZE ( i ) == 8 ) arc_mode_class [ i ] = 1 << ( int ) D_MODE ; else if ( GET_MODE_SIZE ( i ) == 16 ) arc_mode_class [ i ] = 1 << ( int ) T_MODE ; else if ( GET_MODE_SIZE ( i ) == 32 ) arc_mode_class [ i ] = 1 << ( int ) O_MODE ; else arc_mode_class [ i ] = 0 ; break ; case MODE_FLOAT : case MODE_COMPLEX_FLOAT : if ( GET_MODE_SIZE ( i ) <= 4 ) arc_mode_class [ i ] = 1 << ( int ) SF_MODE ; else if ( GET_MODE_SIZE ( i ) == 8 ) arc_mode_class [ i ] = 1 << ( int ) DF_MODE ; else if ( GET_MODE_SIZE ( i ) == 16 ) arc_mode_class [ i ] = 1 << ( int ) TF_MODE ; else if ( GET_MODE_SIZE ( i ) == 32 ) arc_mode_class [ i ] = 1 << ( int ) OF_MODE ; else arc_mode_class [ i ] = 0 ; break ; case MODE_CC : default : if ( i == ( int ) CCmode || i == ( int ) CCZNmode || i == ( int ) CCZNCmode ) arc_mode_class [ i ] = 1 << ( int ) C_MODE ; else arc_mode_class [ i ] = 0 ; break ; } } for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { if ( i < 60 ) arc_regno_reg_class [ i ] = GENERAL_REGS ; else if ( i == 60 ) arc_regno_reg_class [ i ] = LPCOUNT_REG ; else if ( i == 61 ) arc_regno_reg_class [ i ] = NO_REGS ; else arc_regno_reg_class [ i ] = NO_REGS ; } } </s>


<s> bool ARMPassConfig :: addInstSelector ( ) { addPass ( createARMISelDag ( getARMTargetMachine ( ) , getOptLevel ( ) ) ) ; if ( Triple ( TM -> getTargetTriple ( ) ) . isOSBinFormatELF ( ) && TM -> Options . EnableFastISel ) addPass ( createARMGlobalBaseRegPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool MMIXAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { if ( ( Count % 4 ) != 0 ) return false ; for ( uint64_t i = 0 ; i < Count ; i += 4 ) OS . write ( "\xfd\0\0\0" , 4 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> enum reg_class mt_secondary_reload_class ( enum reg_class class ATTRIBUTE_UNUSED , enum machine_mode mode , rtx x ) { if ( ( mode == QImode && ( ! TARGET_BYTE_ACCESS ) ) || mode == HImode ) { if ( GET_CODE ( x ) == MEM || ( GET_CODE ( x ) == REG && true_regnum ( x ) == - 1 ) || ( GET_CODE ( x ) == SUBREG && ( GET_CODE ( SUBREG_REG ( x ) ) == MEM || ( GET_CODE ( SUBREG_REG ( x ) ) == REG && true_regnum ( SUBREG_REG ( x ) ) == - 1 ) ) ) ) return GENERAL_REGS ; } return NO_REGS ; } </s>


<s> bool SIRegisterInfo :: requiresVirtualBaseRegisters ( const MachineFunction & ) const { return true ; } </s>

Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers used for more efficient stack access .


<s> bool SIInstrInfo :: usesConstantBus ( const MachineRegisterInfo & MRI , const MachineOperand & MO , const MCOperandInfo & OpInfo ) const { if ( MO . isImm ( ) ) return ! isInlineConstant ( MO , OpInfo ) ; if ( ! MO . isReg ( ) ) return true ; if ( ! MO . isUse ( ) ) return false ; if ( Register :: isVirtualRegister ( MO . getReg ( ) ) ) return RI . isSGPRClass ( MRI . getRegClass ( MO . getReg ( ) ) ) ; if ( MO . getReg ( ) == AMDGPU :: SGPR_NULL ) return false ; if ( MO . isImplicit ( ) ) { return MO . getReg ( ) == AMDGPU :: M0 || MO . getReg ( ) == AMDGPU :: VCC || MO . getReg ( ) == AMDGPU :: VCC_LO ; } else { return AMDGPU :: SReg_32RegClass . contains ( MO . getReg ( ) ) || AMDGPU :: SReg_64RegClass . contains ( MO . getReg ( ) ) ; } } </s>

Returns true if this operand uses the constant bus .


<s> bool runOnMachineFunction ( MachineFunction & F ) { bool Changed = false ; if ( EnableDelJmp ) { MachineFunction :: iterator FJ = F . begin ( ) ; if ( FJ != F . end ( ) ) FJ ++ ; if ( FJ == F . end ( ) ) return Changed ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FJ != FE ; ++ FI , ++ FJ ) Changed |= runOnMachineBasicBlock ( * FI , * FJ ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


Return an array that contains the bitmask target flag values and their names .

ARM ARM ARM "arm-coffstub" "arm-got" "arm-sbrel" "arm-dllimport" "arm-secrel" "arm-nonlazy"


<s> static bool ia64_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { if ( lookup_attribute ( "syscall_linkage" , TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ) ) return false ; return decl && ( * targetm . binds_local_p ) ( decl ) ; } </s>

True if it is OK to do sibling call optimization for the specified call expression EXP . DECL will be the called function , or NULL if this is an indirect call .


<s> ArrayRef < MachineBasicBlock * > getBlocks ( ) const { return Blocks ; } </s>

Get a list of the basic blocks which make up this loop .


<s> static void s390_encode_section_info ( tree decl , rtx rtl , int first ) { default_encode_section_info ( decl , rtl , first ) ; if ( TREE_CODE ( decl ) == VAR_DECL ) { if ( DECL_ALIGN ( decl ) == 0 || DECL_ALIGN ( decl ) % 16 ) SYMBOL_FLAG_SET_NOTALIGN2 ( XEXP ( rtl , 0 ) ) ; else if ( DECL_ALIGN ( decl ) % 32 ) SYMBOL_FLAG_SET_NOTALIGN4 ( XEXP ( rtl , 0 ) ) ; else if ( DECL_ALIGN ( decl ) % 64 ) SYMBOL_FLAG_SET_NOTALIGN8 ( XEXP ( rtl , 0 ) ) ; } if ( MEM_P ( rtl ) && GET_CODE ( XEXP ( rtl , 0 ) ) == SYMBOL_REF && TREE_CONSTANT_POOL_ADDRESS_P ( XEXP ( rtl , 0 ) ) ) { if ( MEM_ALIGN ( rtl ) == 0 || MEM_ALIGN ( rtl ) % 16 ) SYMBOL_FLAG_SET_NOTALIGN2 ( XEXP ( rtl , 0 ) ) ; else if ( MEM_ALIGN ( rtl ) % 32 ) SYMBOL_FLAG_SET_NOTALIGN4 ( XEXP ( rtl , 0 ) ) ; else if ( MEM_ALIGN ( rtl ) % 64 ) SYMBOL_FLAG_SET_NOTALIGN8 ( XEXP ( rtl , 0 ) ) ; } } </s>

Encode symbol attributes ( local vs. global , tls model ) of a SYMBOL_REF into its SYMBOL_REF_FLAGS .


<s> bool ARMIndirectThunks :: doInitialization ( Module & M ) { initTIs ( M , TIs ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> MCSymbol * WebAssemblyMCInstLower :: GetExternalSymbolSymbol ( const MachineOperand & MO ) const { const char * Name = MO . getSymbolName ( ) ; MCSymbolWasm * WasmSym = cast < MCSymbolWasm > ( Printer . GetExternalSymbolSymbol ( Name ) ) ; const WebAssemblySubtarget & Subtarget = Printer . getSubtarget ( ) ; if ( strcmp ( Name , "__stack_pointer" ) == 0 ) { WasmSym -> setType ( wasm :: WASM_SYMBOL_TYPE_GLOBAL ) ; WasmSym -> setGlobalType ( wasm :: WasmGlobalType { uint8_t ( Subtarget . hasAddr64 ( ) ? wasm :: WASM_TYPE_I64 : wasm :: WASM_TYPE_I32 ) , true } ) ; return WasmSym ; } SmallVector < wasm :: ValType , 4 > Returns ; SmallVector < wasm :: ValType , 4 > Params ; GetLibcallSignature ( Subtarget , Name , Returns , Params ) ; auto Signature = make_unique < wasm :: WasmSignature > ( std :: move ( Returns ) , std :: move ( Params ) ) ; WasmSym -> setSignature ( Signature . get ( ) ) ; Printer . addSignature ( std :: move ( Signature ) ) ; WasmSym -> setType ( wasm :: WASM_SYMBOL_TYPE_FUNCTION ) ; return WasmSym ; } </s>

Return the MCSymbol for the specified ExternalSymbol .


<s> bool isLegalMaskedGather ( Type * DataType ) { return ST -> hasSVE ( ) ; } </s>

Return true if the target supports masked gather .


<s> static bool rs6000_function_parms_need_stack ( tree fun , bool incoming ) { tree fntype , result ; CUMULATIVE_ARGS args_so_far_v ; cumulative_args_t args_so_far ; if ( ! fun ) return false ; fntype = fun ; if ( ! TYPE_P ( fun ) ) fntype = TREE_TYPE ( fun ) ; if ( ( ! incoming && ! prototype_p ( fntype ) ) || stdarg_p ( fntype ) ) return true ; INIT_CUMULATIVE_INCOMING_ARGS ( args_so_far_v , fntype , NULL_RTX ) ; args_so_far = pack_cumulative_args ( & args_so_far_v ) ; if ( incoming ) { gcc_assert ( DECL_P ( fun ) ) ; result = DECL_RESULT ( fun ) ; } else result = TREE_TYPE ( fntype ) ; if ( result && aggregate_value_p ( result , fntype ) ) { if ( ! TYPE_P ( result ) ) result = TREE_TYPE ( result ) ; result = build_pointer_type ( result ) ; rs6000_parm_needs_stack ( args_so_far , result ) ; } if ( incoming ) { tree parm ; for ( parm = DECL_ARGUMENTS ( fun ) ; parm && parm != void_list_node ; parm = TREE_CHAIN ( parm ) ) if ( rs6000_parm_needs_stack ( args_so_far , TREE_TYPE ( parm ) ) ) return true ; } else { function_args_iterator args_iter ; tree arg_type ; FOREACH_FUNCTION_ARGS ( fntype , arg_type , args_iter ) if ( rs6000_parm_needs_stack ( args_so_far , arg_type ) ) return true ; } return false ; } </s>

Return true if FUN has no prototype , has a variable argument list , or passes any parameter in memory .


<s> static void mips_init_builtins ( void ) { const struct mips_builtin_description * d ; unsigned int i ; for ( i = 0 ; i < ARRAY_SIZE ( mips_builtins ) ; i ++ ) { d = & mips_builtins [ i ] ; if ( d -> avail ( ) ) { mips_builtin_decls [ i ] = add_builtin_function ( d -> name , mips_build_function_type ( d -> function_type ) , i , BUILT_IN_MD , NULL , NULL ) ; if ( mips_builtin_decls [ i ] && d -> is_pure ) DECL_PURE_P ( mips_builtin_decls [ i ] ) = 1 ; mips_get_builtin_decl_index [ d -> icode ] = i ; } } } </s>

Init builtin functions . This is called from TARGET_INIT_BUILTIN .


"SystemZ Local Dynamic TLS Access Clean-up"

getPassName - Return a nice clean name for a pass .


<s> bool RISCVAsmBackend :: shouldInsertFixupForCodeAlign ( MCAssembler & Asm , const MCAsmLayout & Layout , MCAlignFragment & AF ) { if ( ! STI . getFeatureBits ( ) [ RISCV :: FeatureRelax ] ) return false ; unsigned Count ; if ( ! shouldInsertExtraNopBytesForCodeAlign ( AF , Count ) || ( Count == 0 ) ) return false ; MCContext & Ctx = Asm . getContext ( ) ; const MCExpr * Dummy = MCConstantExpr :: create ( 0 , Ctx ) ; MCFixup Fixup = MCFixup :: create ( 0 , Dummy , MCFixupKind ( RISCV :: fixup_riscv_align ) , SMLoc ( ) ) ; uint64_t FixedValue = 0 ; MCValue NopBytes = MCValue :: get ( Count ) ; Asm . getWriter ( ) . recordRelocation ( Asm , Layout , & AF , Fixup , NopBytes , FixedValue ) ; return true ; } </s>

Hook which indicates if the target requires a fixup to be generated when handling an align directive in an executable section .


<s> static rtx move_to_hl ( int opno , rtx_insn * before ) { rtx src = OP ( opno ) ; machine_mode mode = GET_MODE ( src ) ; rtx reg ; if ( mode == VOIDmode ) mode = recog_data . operand_mode [ opno ] ; reg = ( mode == QImode ) ? L : HL ; if ( mode == QImode || ! is_virtual_register ( OP ( opno ) ) ) { OP ( opno ) = move_to_acc ( opno , before ) ; OP ( opno ) = move_acc_to_reg ( OP ( opno ) , L_REG , before ) ; return reg ; } return gen_and_emit_move ( reg , src , before , true ) ; } </s>

Copy OP ( opno ) to H or HL , placing any generated insns before BEFORE . Returns H/HL RTX .


<s> bool PPCRegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , unsigned Reg , int & FrameIdx ) const { if ( Subtarget . isSVR4ABI ( ) && PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ) { if ( Subtarget . isPPC64 ( ) ) FrameIdx = 0 ; else { const PPCFunctionInfo * FI = MF . getInfo < PPCFunctionInfo > ( ) ; FrameIdx = FI -> getCRSpillFrameIndex ( ) ; } return true ; } return false ; } </s>

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register .


<s> bool WinEHStatePass :: runOnFunction ( Function & F ) { if ( F . hasAvailableExternallyLinkage ( ) ) return false ; if ( ! F . hasPersonalityFn ( ) ) return false ; PersonalityFn = dyn_cast < Function > ( F . getPersonalityFn ( ) -> stripPointerCastsSafe ( ) ) ; if ( ! PersonalityFn ) return false ; Personality = classifyEHPersonality ( PersonalityFn ) ; if ( ! isFuncletEHPersonality ( Personality ) ) return false ; bool HasPads = false ; for ( BasicBlock & BB : F ) { if ( BB . isEHPad ( ) ) { HasPads = true ; break ; } } if ( ! HasPads ) return false ; Type * Int8PtrType = Type :: getInt8PtrTy ( TheModule -> getContext ( ) ) ; SetJmp3 = TheModule -> getOrInsertFunction ( "_setjmp3" , FunctionType :: get ( Type :: getInt32Ty ( TheModule -> getContext ( ) ) , { Int8PtrType , Type :: getInt32Ty ( TheModule -> getContext ( ) ) } , true ) ) ; F . addFnAttr ( "no-frame-pointer-elim" , "true" ) ; emitExceptionRegistrationRecord ( & F ) ; WinEHFuncInfo FuncInfo ; addStateStores ( F , FuncInfo ) ; PersonalityFn = nullptr ; Personality = EHPersonality :: Unknown ; UseStackGuard = false ; RegNode = nullptr ; EHGuardNode = nullptr ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const override { return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s>
void
LanaiInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
Position
,
DebugLoc
DL
,
unsigned
DestinationRegister
,
unsigned
SourceRegister
,
bool
KillSource
)
const
{
if
(
!
Lanai
::
GPRRegClass
.
contains
(
DestinationRegister
,
SourceRegister
)
)
{
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
BuildMI
(
MBB
,
Position
,
DL
,
get
(
Lanai
::
OR_I_LO
)
,
DestinationRegister
)
.
addReg
(
SourceRegister
,
getKillRegState
(
KillSource
)
)
.
addImm
(
0
)
;
}
</s>

Lanai
Lanai
Lanai::GPRRegClass
"Impossible reg-to-reg copy"
Lanai::OR_I_LO
0


<s> unsigned ARMBaseInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case ARM :: LDRrs : case ARM :: t2LDRs : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isReg ( ) && MI -> getOperand ( 3 ) . isImm ( ) && MI -> getOperand ( 2 ) . getReg ( ) == 0 && MI -> getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: LDRi12 : case ARM :: t2LDRi12 : case ARM :: tRestore : case ARM :: VLDRD : case ARM :: VLDRS : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VLD1q64Pseudo : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VLDMQIA : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> static bool mips_interrupt_extra_call_saved_reg_p ( unsigned int regno ) { if ( ( ISA_HAS_HILO || TARGET_DSP ) && MD_REG_P ( regno ) ) return true ; if ( TARGET_DSP && DSP_ACC_REG_P ( regno ) ) return true ; if ( GP_REG_P ( regno ) && ! cfun -> machine -> use_shadow_register_set_p ) { if ( regno == GP_REG_FIRST ) return false ; if ( KERNEL_REG_P ( regno ) ) return false ; if ( regno == STACK_POINTER_REGNUM ) return false ; return call_really_used_regs [ regno ] ; } return false ; } </s>

Return true if REGNO is a register that is ordinarily call-clobbered but must nevertheless be preserved by an interrupt handler .


<s> int arm_return_in_memory ( tree type ) { HOST_WIDE_INT size ; if ( ! AGGREGATE_TYPE_P ( type ) && ( TREE_CODE ( type ) != VECTOR_TYPE ) && ! ( TARGET_AAPCS_BASED && TREE_CODE ( type ) == COMPLEX_TYPE ) ) return 0 ; size = int_size_in_bytes ( type ) ; if ( arm_abi != ARM_ABI_APCS ) { return ( size < 0 || size > UNITS_PER_WORD ) ; } if ( TREE_CODE ( type ) == VECTOR_TYPE ) return ( size < 0 || size > ( 4 * UNITS_PER_WORD ) ) ; if ( size < 0 || size > UNITS_PER_WORD ) return 1 ; if ( TREE_CODE ( type ) == RECORD_TYPE ) { tree field ; for ( field = TYPE_FIELDS ( type ) ; field && TREE_CODE ( field ) != FIELD_DECL ; field = TREE_CHAIN ( field ) ) continue ; if ( field == NULL ) return 0 ; if ( FLOAT_TYPE_P ( TREE_TYPE ( field ) ) ) return 1 ; if ( RETURN_IN_MEMORY ( TREE_TYPE ( field ) ) ) return 1 ; for ( field = TREE_CHAIN ( field ) ; field ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( ! DECL_BIT_FIELD_TYPE ( field ) ) return 1 ; } return 0 ; } if ( TREE_CODE ( type ) == UNION_TYPE ) { tree field ; for ( field = TYPE_FIELDS ( type ) ; field ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( FLOAT_TYPE_P ( TREE_TYPE ( field ) ) ) return 1 ; if ( RETURN_IN_MEMORY ( TREE_TYPE ( field ) ) ) return 1 ; } return 0 ; } return 1 ; } </s>

Decide whether a type should be returned in memory ( true ) or in a register ( false ) . This is called by the macro RETURN_IN_MEMORY .


<s> static void thumb1_reorg ( void ) { basic_block bb ; FOR_EACH_BB_FN ( bb , cfun ) { rtx dest , src ; rtx pat , op0 , set = NULL ; rtx_insn * prev , * insn = BB_END ( bb ) ; bool insn_clobbered = false ; while ( insn != BB_HEAD ( bb ) && ! NONDEBUG_INSN_P ( insn ) ) insn = PREV_INSN ( insn ) ; if ( insn == BB_HEAD ( bb ) || INSN_CODE ( insn ) != CODE_FOR_cbranchsi4_insn ) continue ; pat = PATTERN ( insn ) ; op0 = XEXP ( XEXP ( SET_SRC ( pat ) , 0 ) , 0 ) ; gcc_assert ( insn != BB_HEAD ( bb ) ) ; for ( prev = PREV_INSN ( insn ) ; ( ! insn_clobbered && prev != BB_HEAD ( bb ) && ( NOTE_P ( prev ) || DEBUG_INSN_P ( prev ) || ( ( set = single_set ( prev ) ) != NULL && get_attr_conds ( prev ) == CONDS_NOCOND ) ) ) ; prev = PREV_INSN ( prev ) ) { if ( reg_set_p ( op0 , prev ) ) insn_clobbered = true ; } if ( insn_clobbered ) continue ; if ( ! set ) continue ; dest = SET_DEST ( set ) ; src = SET_SRC ( set ) ; if ( ! low_register_operand ( dest , SImode ) || ! low_register_operand ( src , SImode ) ) continue ; if ( REGNO ( op0 ) == REGNO ( src ) || REGNO ( op0 ) == REGNO ( dest ) ) { dest = copy_rtx ( dest ) ; src = copy_rtx ( src ) ; src = gen_rtx_MINUS ( SImode , src , const0_rtx ) ; PATTERN ( prev ) = gen_rtx_SET ( VOIDmode , dest , src ) ; INSN_CODE ( prev ) = - 1 ; XEXP ( XEXP ( SET_SRC ( pat ) , 0 ) , 0 ) = copy_rtx ( dest ) ; INSN_CODE ( insn ) = - 1 ; } } } </s>

Rewrite move insn into subtract of 0 if the condition codes will be useful in next conditional jump insn .


<s> static void riscv_setup_incoming_varargs ( cumulative_args_t cum , const function_arg_info & arg , int * pretend_size ATTRIBUTE_UNUSED , int no_rtl ) { CUMULATIVE_ARGS local_cum ; int gp_saved ; local_cum = * get_cumulative_args ( cum ) ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) ) riscv_function_arg_advance ( pack_cumulative_args ( & local_cum ) , arg ) ; gp_saved = MAX_ARGS_IN_REGISTERS - local_cum . num_gprs ; if ( ! no_rtl && gp_saved > 0 ) { rtx ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , REG_PARM_STACK_SPACE ( cfun -> decl ) - gp_saved * UNITS_PER_WORD ) ; rtx mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . num_gprs + GP_ARG_FIRST , mem , gp_saved ) ; } if ( REG_PARM_STACK_SPACE ( cfun -> decl ) == 0 ) cfun -> machine -> varargs_size = gp_saved * UNITS_PER_WORD ; } </s>


<s> void SPUHazardRecognizer :: AdvanceCycle ( ) { DOUT ( llvm :: dbgs ( ) << "SPUHazardRecognizer::AdvanceCycle\n" ; } </s>

AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled can not issue in the current cycle , either because of latency or resource conflicts .


<s> unsigned long arm_current_func_type ( ) { if ( ARM_FUNC_TYPE ( cfun -> machine -> func_type ) == ARM_FT_UNKNOWN ) cfun -> machine -> func_type = arm_compute_func_type ( ) ; return cfun -> machine -> func_type ; } </s>

Returns the type of the current function .


<s> BitVector RISCVRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; for ( size_t Reg = 0 ; Reg < getNumRegs ( ) ; Reg ++ ) { if ( MF . getSubtarget < RISCVSubtarget > ( ) . isRegisterReservedByUser ( Reg ) ) markSuperRegs ( Reserved , Reg ) ; } markSuperRegs ( Reserved , RISCV :: X0 ) ; markSuperRegs ( Reserved , RISCV :: X2 ) ; markSuperRegs ( Reserved , RISCV :: X3 ) ; markSuperRegs ( Reserved , RISCV :: X4 ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , RISCV :: X8 ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool AArch64FrameLowering :: canUseAsPrologue ( const MachineBasicBlock & MBB ) const { const MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ; const AArch64Subtarget & Subtarget = MF -> getSubtarget < AArch64Subtarget > ( ) ; const AArch64RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; if ( ! RegInfo -> needsStackRealignment ( * MF ) ) return true ; return findScratchNonCalleeSaveRegister ( TmpMBB ) != AArch64 :: NoRegister ; } </s>

Check whether or not the given MBB can be used as a prologue for the target .


<s> bool nds32_expand_movmemsi ( rtx dstmem , rtx srcmem , rtx total_bytes , rtx alignment ) { if ( nds32_expand_movmemsi_unroll ( dstmem , srcmem , total_bytes , alignment ) ) return true ; if ( ! optimize_size && optimize > 2 ) return nds32_expand_movmemsi_loop ( dstmem , srcmem , total_bytes , alignment ) ; return false ; } </s>

Function to move block memory content by using load_multiple and store_multiple . This is auxiliary extern function to help create rtx template . Check nds32-multiple.md file for the patterns .


<s>
SDValue
AMDGPUTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
Op
->
print
(
errs
(
)
,
&
DAG
)
;
llvm_unreachable
(
"Custom lowering code for this "
"instruction is not implemented yet!"
)
;
break
;
case
ISD
::
SIGN_EXTEND_INREG
:
return
LowerSIGN_EXTEND_INREG
(
Op
,
DAG
)
;
case
ISD
::
CONCAT_VECTORS
:
return
LowerCONCAT_VECTORS
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_SUBVECTOR
:
return
LowerEXTRACT_SUBVECTOR
(
Op
,
DAG
)
;
case
ISD
::
UDIVREM
:
return
LowerUDIVREM
(
Op
,
DAG
)
;
case
ISD
::
SDIVREM
:
return
LowerSDIVREM
(
Op
,
DAG
)
;
case
ISD
::
FREM
:
return
LowerFREM
(
Op
,
DAG
)
;
case
ISD
::
FCEIL
:
return
LowerFCEIL
(
Op
,
DAG
)
;
case
ISD
::
FTRUNC
:
return
LowerFTRUNC
(
Op
,
DAG
)
;
case
ISD
::
FRINT
:
return
LowerFRINT
(
Op
,
DAG
)
;
case
ISD
::
FNEARBYINT
:
return
LowerFNEARBYINT
(
Op
,
DAG
)
;
case
ISD
::
FROUND
:
return
LowerFROUND
(
Op
,
DAG
)
;
case
ISD
::
FFLOOR
:
return
LowerFFLOOR
(
Op
,
DAG
)
;
case
ISD
::
FLOG
:
return
LowerFLOG
(
Op
,
DAG
,
numbers
::
ln2f
)
;
case
ISD
::
FLOG10
:
return
LowerFLOG
(
Op
,
DAG
,
numbers
::
ln2f
/
numbers
::
ln10f
)
;
case
ISD
::
FEXP
:
return
lowerFEXP
(
Op
,
DAG
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerSINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
UINT_TO_FP
:
return
LowerUINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_FP16
:
return
LowerFP_TO_FP16
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_SINT
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_UINT
(
Op
,
DAG
)
;
case
ISD
::
CTTZ
:
case
ISD
::
CTTZ_ZERO_UNDEF
:
case
ISD
::
CTLZ
:
case
ISD
::
CTLZ_ZERO_UNDEF
:
return
LowerCTLZ_CTTZ
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
}
return
Op
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s>
void
X86InstrInfo
::
replaceBranchWithTailCall
(
MachineBasicBlock
&
MBB
,
SmallVectorImpl
<
MachineOperand
>
&
BranchCond
,
const
MachineInstr
&
TailCall
)
const
{
assert
(
canMakeTailCallConditional
(
BranchCond
,
TailCall
)
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugInstr
(
)
)
continue
;
if
(
!
I
->
isBranch
(
)
)
assert
(
0
&&
"Can't find the branch to replace!"
)
;
X86
::
CondCode
CC
=
X86
::
getCondFromBranchOpc
(
I
->
getOpcode
(
)
)
;
assert
(
BranchCond
.
size
(
)
==
1
)
;
if
(
CC
!=
BranchCond
[
0
]
.
getImm
(
)
)
continue
;
break
;
}
unsigned
Opc
=
TailCall
.
getOpcode
(
)
==
X86
::
TCRETURNdi
X86
::
TCRETURNdicc
:
X86
::
TCRETURNdi64cc
;
auto
MIB
=
BuildMI
(
MBB
,
I
,
MBB
.
findDebugLoc
(
I
)
,
get
(
Opc
)
)
;
MIB
->
addOperand
(
TailCall
.
getOperand
(
0
)
)
;
MIB
.
addImm
(
0
)
;
MIB
->
addOperand
(
BranchCond
[
0
]
)
;
MIB
.
copyImplicitOps
(
TailCall
)
;
LivePhysRegs
LiveRegs
(
getRegisterInfo
(
)
)
;
LiveRegs
.
addLiveOuts
(
MBB
)
;
SmallVector
<
std
::
pair
<
unsigned
,
const
MachineOperand
*
>
,
8
>
Clobbers
;
LiveRegs
.
stepForward
(
*
MIB
,
Clobbers
)
;
for
(
const
auto
&
C
:
Clobbers
)
{
MIB
.
addReg
(
C
.
first
,
RegState
::
Implicit
)
;
MIB
.
addReg
(
C
.
first
,
RegState
::
Implicit
|
RegState
::
Define
)
;
}
I
->
eraseFromParent
(
)
;
}
</s>

Replace the conditional branch in MBB with a conditional tail call .


<s> static bool rs6000_cannot_change_mode_class ( machine_mode from , machine_mode to , enum reg_class rclass ) { unsigned from_size = GET_MODE_SIZE ( from ) ; unsigned to_size = GET_MODE_SIZE ( to ) ; if ( from_size != to_size ) { enum reg_class xclass = ( TARGET_VSX ) ? VSX_REGS : FLOAT_REGS ; if ( reg_classes_intersect_p ( xclass , rclass ) ) { unsigned to_nregs = hard_regno_nregs [ FIRST_FPR_REGNO ] [ to ] ; unsigned from_nregs = hard_regno_nregs [ FIRST_FPR_REGNO ] [ from ] ; if ( TARGET_IEEEQUAD && ( to == TFmode || from == TFmode ) ) return true ; if ( ! BYTES_BIG_ENDIAN && ( to == TDmode || from == TDmode ) ) return true ; if ( from_size < 8 || to_size < 8 ) return true ; if ( from_size == 8 && ( 8 * to_nregs ) != to_size ) return true ; if ( to_size == 8 && ( 8 * from_nregs ) != from_size ) return true ; return false ; } else return false ; } if ( TARGET_E500_DOUBLE && ( ( ( ( to ) == DFmode ) + ( ( from ) == DFmode ) ) == 1 || ( ( ( to ) == TFmode ) + ( ( from ) == TFmode ) ) == 1 || ( ( ( to ) == DDmode ) + ( ( from ) == DDmode ) ) == 1 || ( ( ( to ) == TDmode ) + ( ( from ) == TDmode ) ) == 1 || ( ( ( to ) == DImode ) + ( ( from ) == DImode ) ) == 1 ) ) return true ; if ( TARGET_VSX && VSX_REG_CLASS_P ( rclass ) ) { unsigned num_regs = ( from_size + 15 ) / 16 ; if ( hard_regno_nregs [ FIRST_FPR_REGNO ] [ to ] > num_regs || hard_regno_nregs [ FIRST_FPR_REGNO ] [ from ] > num_regs ) return true ; return ( from_size != 8 && from_size != 16 ) ; } if ( TARGET_ALTIVEC && rclass == ALTIVEC_REGS && ( ALTIVEC_VECTOR_MODE ( from ) + ALTIVEC_VECTOR_MODE ( to ) ) == 1 ) return true ; if ( TARGET_SPE && ( SPE_VECTOR_MODE ( from ) + SPE_VECTOR_MODE ( to ) ) == 1 && reg_classes_intersect_p ( GENERAL_REGS , rclass ) ) return true ; return false ; } </s>

Return nonzero if for CLASS a mode change from FROM to TO is invalid .


<s> void AMDGPUInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot ) { printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> void MINA32FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


"calling %qD with attribute sseregparm without "

"calling %qT with attribute sseregparm without "

Return 1 or 2 , if we can pass up to SSE_REGPARM_MAX SFmode ( 1 ) and DFmode ( 2 ) arguments in SSE registers for a function with the indicated TYPE and DECL . DECL may be NULL when calling function indirectly or considering a libcall . Otherwise return 0 .


<s> const Comet2RegisterInfo * getRegisterInfo ( ) const override { return & RegInfo ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool RISCVTargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { return CI -> isTailCall ( ) ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> VariantKind getKind ( ) const { return Kind ; } </s>


<s> char * csky_output_call ( rtx * operands , int index ) { static char buffer [ 20 ] ; rtx addr = operands [ index ] ; if ( REG_P ( addr ) ) sprintf ( buffer , "jsr\t%%%d" , index ) ; else if ( flag_pic && ( GET_CODE ( addr ) == UNSPEC ) ) sprintf ( buffer , "bsr\t%%%d" , index ) ; else sprintf ( buffer , "jbsr\t%%%d" , index ) ; return buffer ; } </s>

Functions to output assembly code for a function call .

csky 20 "jsr\t%%%d" "bsr\t%%%d" "jbsr\t%%%d"


<s> void BlackfinDAGToDAGISel :: PostprocessISelDAG ( ) { FixRegisterClasses ( * CurDAG ) ; } </s>

PostprocessISelDAG ( ) - This hook allows the target to hack on the graph right after selection .


<s> bool ARMBaseInstrInfo :: isPredicable ( MachineInstr * MI ) const { if ( ! MI -> isPredicable ( ) ) return false ; ARMFunctionInfo * AFI = MI -> getParent ( ) -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; if ( AFI -> isThumb2Function ( ) ) { if ( getSubtarget ( ) . hasV8Ops ( ) ) return isV8EligibleForIT ( MI ) ; } else { if ( ( MI -> getDesc ( ) . TSFlags & ARMII :: DomainMask ) == ARMII :: DomainNEON ) return false ; } return true ; } </s>

Return true if the specified instruction can be predicated .

ARM ARM ARM ARM ARMII::DomainMask ARMII::DomainNEON


<s> static inline enum insn_code rs6000_htm_spr_icode ( bool nonvoid ) { if ( nonvoid ) return ( TARGET_64BIT ) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si ; else return ( TARGET_64BIT ) ? CODE_FOR_htm_mtspr_di : CODE_FOR_htm_mtspr_si ; } </s>

Return the correct ICODE value depending on whether we are setting or reading the HTM SPRs .


<s> static rtx nvptx_gen_pack ( rtx dst , rtx src0 , rtx src1 ) { rtx res ; switch ( GET_MODE ( dst ) ) { case DImode : res = gen_packsidi2 ( dst , src0 , src1 ) ; break ; case DFmode : res = gen_packsidf2 ( dst , src0 , src1 ) ; break ; default : gcc_unreachable ( ) ; } return res ; } </s>

Generate instruction ( s ) to pack 2 32 bit objects into a 64 bit object .


"Can't store this register to stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> static rtx get_mask_policy_for_pred ( enum predication_type_index pred ) { if ( pred == PRED_TYPE_tumu || pred == PRED_TYPE_mu ) return gen_int_mode ( MASK_UNDISTURBED , Pmode ) ; return gen_int_mode ( get_prefer_mask_policy ( ) , Pmode ) ; } </s>

Get MASK policy for predication . If predication indicates MU , return the MU . Otherwise , return the prefer default configuration .


<s> unsigned GCNHazardRecognizer :: PreEmitNoops ( MachineInstr * MI ) { if ( SIInstrInfo :: isSMRD ( * MI ) ) return std :: max ( 0 , checkSMRDHazards ( MI ) ) ; if ( SIInstrInfo :: isVMEM ( * MI ) ) return std :: max ( 0 , checkVMEMHazards ( MI ) ) ; if ( SIInstrInfo :: isDPP ( * MI ) ) return std :: max ( 0 , checkDPPHazards ( MI ) ) ; return 0 ; } </s>

PreEmitNoops - This callback is invoked prior to emitting an instruction .


"Cannot handle this call frame pseudo instruction"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


Store the specified register of the given register class to the specified stack frame index .


<s> rtx gen_easy_altivec_constant ( rtx op ) { enum machine_mode mode = GET_MODE ( op ) ; int nunits = GET_MODE_NUNITS ( mode ) ; rtx last = CONST_VECTOR_ELT ( op , nunits - 1 ) ; unsigned step = nunits / 4 ; unsigned copies = 1 ; if ( vspltis_constant ( op , step , copies ) ) return gen_rtx_VEC_DUPLICATE ( V4SImode , gen_lowpart ( SImode , last ) ) ; if ( step == 1 ) copies <<= 1 ; else step >>= 1 ; if ( vspltis_constant ( op , step , copies ) ) return gen_rtx_VEC_DUPLICATE ( V8HImode , gen_lowpart ( HImode , last ) ) ; if ( step == 1 ) copies <<= 1 ; else step >>= 1 ; if ( vspltis_constant ( op , step , copies ) ) return gen_rtx_VEC_DUPLICATE ( V16QImode , gen_lowpart ( QImode , last ) ) ; gcc_unreachable ( ) ; } </s>

Generate a VEC_DUPLICATE representing a vspltis [ bhw ] instruction whose result is OP . Abort if it is not possible .


<s>
int64_t
ARMBaseRegisterInfo
::
getFrameIndexInstrOffset
(
const
MachineInstr
*
MI
,
int
Idx
)
const
{
const
MCInstrDesc
&
Desc
=
MI
->
getDesc
(
)
;
unsigned
AddrMode
=
(
Desc
.
TSFlags
&
ARMII
::
AddrModeMask
)
;
int64_t
InstrOffs
=
0
;
int
Scale
=
1
;
unsigned
ImmIdx
=
0
;
switch
(
AddrMode
)
{
case
ARMII
::
AddrModeT2_i8
:
case
ARMII
::
AddrModeT2_i8neg
:
case
ARMII
::
AddrModeT2_i8pos
:
case
ARMII
::
AddrModeT2_i12
:
case
ARMII
::
AddrMode_i12
:
InstrOffs
=
MI
->
getOperand
(
Idx
+
1
)
.
getImm
(
)
;
Scale
=
1
;
break
;
case
ARMII
::
AddrMode5
:
{
const
MachineOperand
&
OffOp
=
MI
->
getOperand
(
Idx
+
1
)
;
InstrOffs
=
ARM_AM
::
getAM5Offset
(
OffOp
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM5Op
(
OffOp
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
Scale
=
4
;
break
;
}
case
ARMII
::
AddrMode2
:
ImmIdx
=
Idx
+
2
;
InstrOffs
=
ARM_AM
::
getAM2Offset
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM2Op
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
break
;
case
ARMII
::
AddrMode3
:
ImmIdx
=
Idx
+
2
;
InstrOffs
=
ARM_AM
::
getAM3Offset
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM3Op
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
break
;
case
ARMII
::
AddrModeT1_s
:
ImmIdx
=
Idx
+
1
;
InstrOffs
=
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
;
Scale
=
4
;
break
;
default
:
llvm_unreachable
(
"Unsupported addressing mode!"
)
;
}
return
InstrOffs
*
Scale
;
}
</s>

Get the offset from the referenced frame index in the instruction , if there is one .


<s> static void process_args ( int * p_argc , char * * argv ) { int i ; for ( i = 1 ; i < * p_argc ; i ++ ) { if ( strlen ( argv [ i ] ) < 2 ) continue ; if ( strncmp ( argv [ i ] , "-L" , 2 ) == 0 ) { char * nbuff , * ptr ; int new_len , search_dirs_len ; ptr = & argv [ i ] [ 2 ] ; new_len = strlen ( ptr ) ; search_dirs_len = strlen ( search_dirs ) ; nbuff = xmalloc ( new_len + 1 ) ; strcpy ( nbuff , ptr ) ; while ( new_len > 1 && nbuff [ new_len - 1 ] == '/' ) { nbuff [ new_len - 1 ] = 0 ; new_len -- ; } search_dirs = xrealloc ( search_dirs , search_dirs_len + new_len + 2 ) ; if ( search_dirs_len > 0 ) strcat ( search_dirs , PATH_SEPARATOR_STR ) ; strcat ( search_dirs , nbuff ) ; free ( nbuff ) ; } else if ( strcmp ( argv [ i ] , "-v" ) == 0 ) verbose = 1 ; else if ( strcmp ( argv [ i ] , "-g0" ) == 0 ) addarg ( "/notraceback" ) ; else if ( strncmp ( argv [ i ] , "-g" , 2 ) == 0 ) { addarg ( "/debug" ) ; debug = 1 ; } else if ( strcmp ( argv [ i ] , "-static" ) == 0 ) staticp = 1 ; else if ( strcmp ( argv [ i ] , "-map" ) == 0 ) { char * buff , * ptr ; buff = xmalloc ( strlen ( exefilename ) + 5 ) ; strcpy ( buff , exefilename ) ; ptr = strchr ( buff , '.' ) ; if ( ptr ) * ptr = 0 ; strcat ( buff , ".map" ) ; addarg ( "/map=" ) ; addarg ( buff ) ; addarg ( "/full" ) ; } else if ( strcmp ( argv [ i ] , "-save-temps" ) == 0 ) save_temps = 1 ; else if ( strcmp ( argv [ i ] , "--noinhibit-exec" ) == 0 ) inhibit_exec = 0 ; } } </s>

Preprocess the number of args ARGC in ARGV . Look for special flags , etc . that must be handled for the VMS linker .


<s> void AArch64Subtarget :: overrideSchedPolicy ( MachineSchedPolicy & Policy , MachineInstr * begin , MachineInstr * end , unsigned NumRegionInstrs ) const { Policy . OnlyTopDown = false ; Policy . OnlyBottomUp = false ; } </s>

Override generic scheduling policy within a region .


<s> static bool canonicalize_perm ( struct expand_vec_perm_d * d ) { int i , which , nelt = d -> nelt ; for ( i = which = 0 ; i < nelt ; ++ i ) which |= ( d -> perm [ i ] < nelt ? 1 : 2 ) ; d -> one_operand_p = true ; switch ( which ) { default : gcc_unreachable ( ) ; case 3 : if ( ! rtx_equal_p ( d -> op0 , d -> op1 ) ) { d -> one_operand_p = false ; break ; } case 2 : for ( i = 0 ; i < nelt ; ++ i ) d -> perm [ i ] &= nelt - 1 ; d -> op0 = d -> op1 ; break ; case 1 : d -> op1 = d -> op0 ; break ; } return ( which == 3 ) ; } </s>

If a permutation only uses one operand , make it clear . Returns true if the permutation references both operands .


<s> void addChild ( MRT * Tree ) { Children . insert ( Tree ) ; } </s>


<s> void assignValueToAddress ( Register ValVReg , Register Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { MachineFunction & MF = MIRBuilder . getMF ( ) ; auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant , Size , inferAlignFromPtrInfo ( MF , MPO ) ) ; MIRBuilder . buildLoad ( ValVReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> static bool reg_offset_addressing_ok_p ( machine_mode mode ) { switch ( mode ) { case V16QImode : case V8HImode : case V4SFmode : case V4SImode : case V2DFmode : case V2DImode : case V1TImode : case TImode : case TFmode : case KFmode : if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) ) return false ; break ; case V4HImode : case V2SImode : case V1DImode : case V2SFmode : if ( TARGET_PAIRED_FLOAT ) return false ; break ; case SDmode : if ( TARGET_NO_SDMODE_STACK ) return false ; break ; default : break ; } return true ; } </s>

Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p .


<s> static void frv_register_nop ( rtx nop ) { rtx_insn * nop_insn = make_insn_raw ( nop ) ; SET_NEXT_INSN ( nop_insn ) = 0 ; SET_PREV_INSN ( nop_insn ) = 0 ; frv_nops [ frv_num_nops ++ ] = nop_insn ; } </s>

Add an instruction with pattern NOP to frv_nops [ ] .


<s> bool n13_consumed_by_e1_dep_p ( rtx_insn * consumer , rtx def_reg ) { rtx use_rtx ; switch ( get_attr_type ( consumer ) ) { case TYPE_ALU : return n13_alu_e1_insn_dep_reg_p ( consumer , def_reg ) ; case TYPE_PBSADA : return pbsada_insn_ra_rb_dep_reg_p ( consumer , def_reg ) ; case TYPE_PBSAD : case TYPE_MUL : use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_MAC : use_rtx = extract_mac_non_acc_rtx ( consumer ) ; break ; case TYPE_DIV : if ( divmod_p ( consumer ) ) use_rtx = SET_SRC ( parallel_element ( consumer , 0 ) ) ; else use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_MMU : if ( GET_CODE ( PATTERN ( consumer ) ) == SET ) use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; else return true ; break ; case TYPE_BRANCH : use_rtx = extract_branch_target_rtx ( consumer ) ; break ; case TYPE_LOAD : case TYPE_STORE : use_rtx = extract_mem_rtx ( consumer ) ; break ; case TYPE_LOAD_MULTIPLE : case TYPE_STORE_MULTIPLE : use_rtx = extract_base_reg ( consumer ) ; break ; default : return false ; } if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; return false ; } </s>

Check the dependency between the producer defining DEF_REG and CONSUMER requiring input operand at E1 . Because the address generation unti is at E1 , the address input should be ready at E1 . Note that the branch target is also a kind of addresses , so we have to check it .


<s> static rtx frame_insn ( rtx x ) { x = emit_insn ( x ) ; RTX_FRAME_RELATED_P ( x ) = 1 ; return x ; } </s>

Emit the specified insn and mark it as frame related . FIXME : Rename this to emit_frame_insn .


<s> int compute_logical_op_cc ( enum machine_mode mode , rtx * operands ) { enum rtx_code code = GET_CODE ( operands [ 3 ] ) ; const unsigned HOST_WIDE_INT intval = ( unsigned HOST_WIDE_INT ) ( ( GET_CODE ( operands [ 2 ] ) == CONST_INT ) && register_operand ( operands [ 1 ] , VOIDmode ) ? INTVAL ( operands [ 2 ] ) : 0x55555555 ) ; const unsigned HOST_WIDE_INT det = ( code != AND ) ? intval : ~ intval ; const unsigned HOST_WIDE_INT b0 = ( det >> 0 ) & 0xff ; const unsigned HOST_WIDE_INT b1 = ( det >> 8 ) & 0xff ; const unsigned HOST_WIDE_INT w0 = ( det >> 0 ) & 0xffff ; const unsigned HOST_WIDE_INT w1 = ( det >> 16 ) & 0xffff ; int lower_half_easy_p = 0 ; int upper_half_easy_p = 0 ; enum attr_cc cc = CC_CLOBBER ; switch ( mode ) { case HImode : if ( ( TARGET_H8300H || TARGET_H8300S ) && b0 != 0 && b1 != 0 ) { cc = CC_SET_ZNV ; } break ; case SImode : if ( TARGET_H8300H || TARGET_H8300S ) { lower_half_easy_p = ( b0 == 0 || b1 == 0 || ( code != IOR && w0 == 0xffff ) ) ; upper_half_easy_p = ( ( code != IOR && w1 == 0xffff ) || ( code == AND && w1 == 0xff00 ) ) ; } if ( ( TARGET_H8300H || TARGET_H8300S ) && w0 != 0 && w1 != 0 && ! ( lower_half_easy_p && upper_half_easy_p ) && ! ( code == IOR && w1 == 0xffff && ( w0 & 0x8000 ) != 0 && lower_half_easy_p ) ) { cc = CC_SET_ZNV ; } else { if ( ( TARGET_H8300H || TARGET_H8300S ) && code == IOR && w1 == 0xffff && ( w0 & 0x8000 ) != 0 ) { cc = CC_SET_ZNV ; } } break ; default : gcc_unreachable ( ) ; } return cc ; } </s>

Compute which flag bits are valid after a logical insn .


<s>
void
JVMInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
llvm_unreachable
(
"Unsupported copyPhysReg."
)
;
}
</s>


<s> void X86TargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( Subtarget . getTargetTriple ( ) . isOSMSVCRT ( ) ) { M . getOrInsertGlobal ( "__security_cookie" , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; auto * SecurityCheckCookie = cast < Function > ( M . getOrInsertFunction ( "__security_check_cookie" , Type :: getVoidTy ( M . getContext ( ) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) , nullptr ) ) ; SecurityCheckCookie -> setCallingConv ( CallingConv :: X86_FastCall ) ; SecurityCheckCookie -> addAttribute ( 1 , Attribute :: AttrKind :: InReg ) ; return ; } if ( hasStackGuardSlotTLS ( Subtarget . getTargetTriple ( ) ) ) return ; TargetLowering :: insertSSPDeclarations ( M ) ; } </s>

Inserts necessary declarations for SSP ( stack protection ) purpose .


<s>
void
ARMConstantIslands
::
verify
(
)
{
for
(
MachineFunction
::
iterator
MBBI
=
MF
->
begin
(
)
,
E
=
MF
->
end
(
)
;
MBBI
!=
E
;
++
MBBI
)
{
MachineBasicBlock
*
MBB
=
MBBI
;
unsigned
MBBId
=
MBB
->
getNumber
(
)
;
assert
(
!
MBBId
||
BBInfo
[
MBBId
1
]
.
postOffset
(
)
<=
BBInfo
[
MBBId
]
.
Offset
)
;
}
DEBUG
(
dbgs
(
)
<<
"Verifying "
<<
CPUsers
.
size
(
)
<<
" CP users.\n"
)
;
for
(
unsigned
i
=
0
,
e
=
CPUsers
.
size
(
)
;
i
!=
e
;
++
i
)
{
CPUser
&
U
=
CPUsers
[
i
]
;
unsigned
UserOffset
=
getUserOffset
(
U
)
;
if
(
isCPEntryInRange
(
U
.
MI
,
UserOffset
,
U
.
CPEMI
,
U
.
getMaxDisp
(
)
+
2
,
U
.
NegOk
,
true
)
)
{
DEBUG
(
dbgs
(
)
<<
"OK\n"
)
;
continue
;
}
DEBUG
(
dbgs
(
)
<<
"Out of range.\n"
)
;
dumpBBs
(
)
;
DEBUG
(
MF
->
dump
(
)
)
;
llvm_unreachable
(
"Constant pool entry out of range!"
)
;
}
}
</s>

ARM
ARM
1
"Verifying "
" CP users.\n"
0
2
"OK\n"
"Out of range.\n"
"Constant pool entry out of range!"


<s> bool targetSchedulesPostRAScheduling ( ) const override { return true ; } </s>

True if subtarget inserts the final scheduling pass on its own .


<s> const char * output_branch ( int logic , rtx insn , rtx * operands ) { switch ( get_attr_length ( insn ) ) { case 6 : if ( ! TARGET_RELAX ) { int label = lf ++ ; rtx op0 = operands [ 0 ] ; if ( final_sequence && ! INSN_ANNULLED_BRANCH_P ( XVECEXP ( final_sequence , 0 , 0 ) ) && get_attr_length ( XVECEXP ( final_sequence , 0 , 1 ) ) ) { asm_fprintf ( asm_out_file , "\tb%s%ss\t%LLF%d\n" , logic ? "f" : "t" , ASSEMBLER_DIALECT ? "/" : "." , label ) ; print_slot ( final_sequence ) ; } else asm_fprintf ( asm_out_file , "\tb%s\t%LLF%d\n" , logic ? "f" : "t" , label ) ; output_asm_insn ( "bra\t%l0" , & op0 ) ; fprintf ( asm_out_file , "\tnop\n" ) ; ( * targetm . asm_out . internal_label ) ( asm_out_file , "LF" , label ) ; return "" ; } case 2 : return logic ? "bt%.\t%l0" : "bf%.\t%l0" ; case 8 : if ( ! TARGET_RELAX ) { int label = lf ++ ; gcc_assert ( ! final_sequence || ! ( INSN_ANNULLED_BRANCH_P ( XVECEXP ( final_sequence , 0 , 0 ) ) ) ) ; asm_fprintf ( asm_out_file , "b%s%ss\t%LLF%d\n" , logic ? "f" : "t" , ASSEMBLER_DIALECT ? "/" : "." , label ) ; fprintf ( asm_out_file , "\tnop\n" ) ; output_asm_insn ( "bra\t%l0" , operands ) ; fprintf ( asm_out_file , "\tnop\n" ) ; ( * targetm . asm_out . internal_label ) ( asm_out_file , "LF" , label ) ; return "" ; } case 4 : { char buffer [ 10 ] ; sprintf ( buffer , "b%s%ss\t%%l0" , logic ? "t" : "f" , ASSEMBLER_DIALECT ? "/" : "." ) ; output_asm_insn ( buffer , & operands [ 0 ] ) ; return "nop" ; } default : gcc_unreachable ( ) ; } } </s>

Output a conditional/unconditional branch to LABEL . COND is the string condition . INSN is the instruction .


<s> inline bool isFPImm ( const APFloat & Val ) { uint32_t Imm8 ; return isFPImm ( Val , Imm8 ) ; } </s>

isFPImm - Tests if this is a MO_FPImmediate operand .


<s>
static
void
cris_asm_output_mi_thunk
(
FILE
*
stream
,
tree
thunkdecl
ATTRIBUTE_UNUSED
,
HOST_WIDE_INT
delta
,
HOST_WIDE_INT
vcall_offset
ATTRIBUTE_UNUSED
,
tree
funcdecl
)
{
final_start_function
(
emit_barrier
(
)
,
stream
,
1
)
;
if
(
delta
>
0
)
fprintf
(
stream
,
"\tadd%s "
HOST_WIDE_INT_PRINT_DEC
",$%s\n"
,
ADDITIVE_SIZE_MODIFIER
(
delta
)
,
delta
,
reg_names
[
CRIS_FIRST_ARG_REG
]
)
;
else
if
(
delta
<
0
)
fprintf
(
stream
,
"\tsub%s "
HOST_WIDE_INT_PRINT_DEC
",$%s\n"
,
ADDITIVE_SIZE_MODIFIER
(
delta
)
,
delta
,
reg_names
[
CRIS_FIRST_ARG_REG
]
)
;
if
(
flag_pic
)
{
const
char
*
name
=
XSTR
(
XEXP
(
DECL_RTL
(
funcdecl
)
,
0
)
,
0
)
;
name
=
(
*
targetm
.
strip_name_encoding
)
(
name
)
;
if
(
TARGET_V32
)
{
fprintf
(
stream
,
"\tba "
)
;
assemble_name
(
stream
,
name
)
;
fprintf
(
stream
,
"%s\n\tnop\n"
,
CRIS_PLT_PCOFFSET_SUFFIX
)
;
}
else
{
fprintf
(
stream
,
"\tadd.d "
)
;
assemble_name
(
stream
,
name
)
;
fprintf
(
stream
,
"%s,$pc\n"
,
CRIS_PLT_PCOFFSET_SUFFIX
)
;
}
}
else
{
fprintf
(
stream
,
"\tjump "
)
;
assemble_name
(
stream
,
XSTR
(
XEXP
(
DECL_RTL
(
funcdecl
)
,
0
)
,
0
)
)
;
fprintf
(
stream
,
"\n"
)
;
if
(
TARGET_V32
)
fprintf
(
stream
,
"\tnop\n"
)
;
}
final_end_function
(
)
;
}
</s>


<s> int alpha_split_conditional_move ( enum rtx_code code , rtx dest , rtx cond , rtx t_rtx , rtx f_rtx ) { HOST_WIDE_INT t , f , diff ; machine_mode mode ; rtx target , subtarget , tmp ; mode = GET_MODE ( dest ) ; t = INTVAL ( t_rtx ) ; f = INTVAL ( f_rtx ) ; diff = t - f ; if ( ( ( code == NE || code == EQ ) && diff < 0 ) || ( code == GE || code == GT ) ) { code = reverse_condition ( code ) ; diff = t , t = f , f = diff ; diff = t - f ; } subtarget = target = dest ; if ( mode != DImode ) { target = gen_lowpart ( DImode , dest ) ; if ( can_create_pseudo_p ( ) ) subtarget = gen_reg_rtx ( DImode ) ; else subtarget = target ; } if ( f == 0 && exact_log2 ( diff ) > 0 && ( diff <= 8 || alpha_tune == PROCESSOR_EV6 ) ) { tmp = gen_rtx_fmt_ee ( code , DImode , cond , const0_rtx ) ; emit_insn ( gen_rtx_SET ( copy_rtx ( subtarget ) , tmp ) ) ; tmp = gen_rtx_ASHIFT ( DImode , copy_rtx ( subtarget ) , GEN_INT ( exact_log2 ( t ) ) ) ; emit_insn ( gen_rtx_SET ( target , tmp ) ) ; } else if ( f == 0 && t == - 1 ) { tmp = gen_rtx_fmt_ee ( code , DImode , cond , const0_rtx ) ; emit_insn ( gen_rtx_SET ( copy_rtx ( subtarget ) , tmp ) ) ; emit_insn ( gen_negdi2 ( target , copy_rtx ( subtarget ) ) ) ; } else if ( diff == 1 || diff == 4 || diff == 8 ) { rtx add_op ; tmp = gen_rtx_fmt_ee ( code , DImode , cond , const0_rtx ) ; emit_insn ( gen_rtx_SET ( copy_rtx ( subtarget ) , tmp ) ) ; if ( diff == 1 ) emit_insn ( gen_adddi3 ( target , copy_rtx ( subtarget ) , GEN_INT ( f ) ) ) ; else { add_op = GEN_INT ( f ) ; if ( sext_add_operand ( add_op , mode ) ) { tmp = gen_rtx_MULT ( DImode , copy_rtx ( subtarget ) , GEN_INT ( diff ) ) ; tmp = gen_rtx_PLUS ( DImode , tmp , add_op ) ; emit_insn ( gen_rtx_SET ( target , tmp ) ) ; } else return 0 ; } } else return 0 ; return 1 ; } </s>

Simplify a conditional move of two constants into a setcc with arithmetic . This is done with a splitter since combine would just undo the work if done during code generation . It also catches cases we would n't have before cse .


"X86-64 PIC uses RIP relative addressing"

runOnMachineFunction - Emit the function body .


"Unable to generate load/store offset for fusion"

Emit a D-form load or store instruction that is the second instruction of a fusion sequence .


<s> const char * output_reload_insisf ( rtx insn ATTRIBUTE_UNUSED , rtx * operands , int * len ) { rtx src = operands [ 1 ] ; int cnst = ( GET_CODE ( src ) == CONST_INT ) ; if ( len ) { if ( cnst ) * len = 4 + ( ( INTVAL ( src ) & 0xff ) != 0 ) + ( ( INTVAL ( src ) & 0xff00 ) != 0 ) + ( ( INTVAL ( src ) & 0xff0000 ) != 0 ) + ( ( INTVAL ( src ) & 0xff000000 ) != 0 ) ; else * len = 8 ; return "" ; } if ( cnst && ( ( INTVAL ( src ) & 0xff ) == 0 ) ) output_asm_insn ( AS2 ( mov , % A0 , __zero_reg__ ) , operands ) ; else { output_asm_insn ( AS2 ( ldi , % 2 , lo8 ( % 1 ) ) , operands ) ; output_asm_insn ( AS2 ( mov , % A0 , % 2 ) , operands ) ; } if ( cnst && ( ( INTVAL ( src ) & 0xff00 ) == 0 ) ) output_asm_insn ( AS2 ( mov , % B0 , __zero_reg__ ) , operands ) ; else { output_asm_insn ( AS2 ( ldi , % 2 , hi8 ( % 1 ) ) , operands ) ; output_asm_insn ( AS2 ( mov , % B0 , % 2 ) , operands ) ; } if ( cnst && ( ( INTVAL ( src ) & 0xff0000 ) == 0 ) ) output_asm_insn ( AS2 ( mov , % C0 , __zero_reg__ ) , operands ) ; else { output_asm_insn ( AS2 ( ldi , % 2 , hlo8 ( % 1 ) ) , operands ) ; output_asm_insn ( AS2 ( mov , % C0 , % 2 ) , operands ) ; } if ( cnst && ( ( INTVAL ( src ) & 0xff000000 ) == 0 ) ) output_asm_insn ( AS2 ( mov , % D0 , __zero_reg__ ) , operands ) ; else { output_asm_insn ( AS2 ( ldi , % 2 , hhi8 ( % 1 ) ) , operands ) ; output_asm_insn ( AS2 ( mov , % D0 , % 2 ) , operands ) ; } return "" ; } </s>

Reload a SI or SF compile time constant OP [ 1 ] into the register OP [ 0 ] . CLOBBER_REG is a QI clobber reg needed to move vast majority of consts into a NO_LD_REGS register . If CLOBBER_REG is NULL_RTX we either do n't need a clobber reg or have to cook one up . LEN == NULL : Output instructions . LEN ! = NULL : Output nothing . Set * LEN to number of words occupied by the insns printed . Return `` '' .


<s> void crx_expand_epilogue ( void ) { rtx return_reg ; int only_popret_RA = ( save_regs [ RETURN_ADDRESS_REGNUM ] && ( sum_regs == UNITS_PER_WORD ) ) ; return_reg = gen_rtx_REG ( Pmode , RETURN_ADDRESS_REGNUM ) ; if ( frame_pointer_needed ) emit_move_insn ( stack_pointer_rtx , frame_pointer_rtx ) ; if ( size_for_adjusting_sp > 0 ) emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( size_for_adjusting_sp ) ) ) ; if ( crx_interrupt_function_p ( ) ) emit_jump_insn ( gen_interrupt_return ( ) ) ; else if ( last_reg_to_save == - 1 ) emit_jump_insn ( gen_indirect_jump_return ( ) ) ; else if ( only_popret_RA ) emit_jump_insn ( gen_popret_RA_return ( ) ) ; else emit_jump_insn ( gen_pop_and_popret_return ( GEN_INT ( sum_regs ) ) ) ; } </s>

Generate insn that updates the stack for local variables and padding for * registers we save . - Generate the appropriate return insn .


<s> static void c6x_compute_frame_layout ( struct c6x_frame * frame ) { HOST_WIDE_INT size = get_frame_size ( ) ; HOST_WIDE_INT offset ; int nregs ; offset = - 4 ; frame -> padding0 = 0 ; nregs = c6x_nsaved_regs ( ) ; frame -> push_rts = false ; frame -> b3_offset = 0 ; if ( use_push_rts_p ( nregs ) ) { frame -> push_rts = true ; frame -> b3_offset = ( TARGET_BIG_ENDIAN ? - 12 : - 13 ) * 4 ; nregs = 14 ; } else if ( c6x_save_reg ( REG_B3 ) ) { int idx ; for ( idx = N_SAVE_ORDER - 1 ; reg_save_order [ idx ] != REG_B3 ; idx -- ) { if ( c6x_save_reg ( reg_save_order [ idx ] ) ) frame -> b3_offset -= 4 ; } } frame -> nregs = nregs ; if ( size == 0 && nregs == 0 ) { frame -> padding0 = 4 ; frame -> padding1 = frame -> padding2 = 0 ; frame -> frame_pointer_offset = frame -> to_allocate = 0 ; frame -> outgoing_arguments_size = 0 ; return ; } if ( ! frame -> push_rts ) offset += frame -> nregs * 4 ; if ( offset == 0 && size == 0 && crtl -> outgoing_args_size == 0 && ! crtl -> is_leaf ) frame -> padding0 = frame -> padding1 = 4 ; else if ( offset & 4 ) frame -> padding1 = 4 ; else frame -> padding1 = 0 ; offset += frame -> padding0 + frame -> padding1 ; frame -> frame_pointer_offset = offset ; offset += size ; frame -> outgoing_arguments_size = crtl -> outgoing_args_size ; offset += frame -> outgoing_arguments_size ; if ( ( offset & 4 ) == 0 ) frame -> padding2 = 8 ; else frame -> padding2 = 4 ; frame -> to_allocate = offset + frame -> padding2 ; } </s>

Compute the layout of the stack frame and store it in FRAME .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override { TargetTransformInfo :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> unsigned ARMBaseInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case ARM :: LDR : case ARM :: t2LDRs : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isReg ( ) && MI -> getOperand ( 3 ) . isImm ( ) && MI -> getOperand ( 2 ) . getReg ( ) == 0 && MI -> getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: t2LDRi12 : case ARM :: tRestore : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: FLDD : case ARM :: FLDS : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> bool PPCInstrInfo :: getMachineCombinerPatterns ( MachineInstr & Root , SmallVectorImpl < MachineCombinerPattern :: MC_PATTERN > & Patterns ) const { if ( Subtarget . getTargetMachine ( ) . getOptLevel ( ) != CodeGenOpt :: Aggressive ) return false ; if ( ! Root . getParent ( ) -> getParent ( ) -> getTarget ( ) . Options . UnsafeFPMath ) return false ; bool Commute ; if ( isReassocCandidate ( Root , Commute ) ) { if ( Commute ) { Patterns . push_back ( MachineCombinerPattern :: MC_REASSOC_AX_YB ) ; Patterns . push_back ( MachineCombinerPattern :: MC_REASSOC_XA_YB ) ; } else { Patterns . push_back ( MachineCombinerPattern :: MC_REASSOC_AX_BY ) ; Patterns . push_back ( MachineCombinerPattern :: MC_REASSOC_XA_BY ) ; } return true ; } return false ; } </s>

Return true when there is potentially a faster code sequence for an instruction chain ending in Root .


<s> void vms_c_register_includes ( const char * sysroot , const char * iprefix ATTRIBUTE_UNUSED , int stdinc ) { static const char dir_separator_str [ ] = { DIR_SEPARATOR , 0 } ; struct cpp_dir * dir ; if ( ! stdinc ) return ; for ( dir = get_added_cpp_dirs ( INC_SYSTEM ) ; dir != NULL ; dir = dir -> next ) { const char * const * lib ; for ( lib = vms_std_modules ; * lib != NULL ; lib ++ ) { char * path ; struct stat st ; if ( sysroot != NULL ) path = concat ( sysroot , dir -> name , dir_separator_str , * lib , NULL ) ; else path = concat ( dir -> name , dir_separator_str , * lib , NULL ) ; if ( stat ( path , & st ) == 0 && S_ISDIR ( st . st_mode ) ) { cpp_dir * p ; p = XNEW ( cpp_dir ) ; p -> next = NULL ; p -> name = path ; p -> sysp = 1 ; p -> construct = vms_construct_include_filename ; p -> user_supplied_p = 0 ; add_cpp_dir_path ( p , INC_SYSTEM ) ; } else free ( path ) ; } } } </s>

Find include modules in the include path .


<s> void RISCVFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { const RISCVRegisterInfo * RegInfo = MF . getSubtarget < RISCVSubtarget > ( ) . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterClass * RC = & RISCV :: GPRRegClass ; auto * RVFI = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; int64_t RVVStackSize ; Align RVVStackAlign ; std :: tie ( RVVStackSize , RVVStackAlign ) = assignRVVStackObjectOffsets ( MFI ) ; RVFI -> setRVVStackSize ( RVVStackSize ) ; RVFI -> setRVVStackAlign ( RVVStackAlign ) ; MFI . ensureMaxAlignment ( RVVStackAlign ) ; const RISCVInstrInfo & TII = * MF . getSubtarget < RISCVSubtarget > ( ) . getInstrInfo ( ) ; if ( ! isInt < 11 > ( MFI . estimateStackSize ( MF ) ) || hasRVVSpillWithFIs ( MF , TII ) ) { int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RegScavFI ) ; if ( RVVStackSize != 0 ) { int RVVRegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RVVRegScavFI ) ; } } if ( MFI . getCalleeSavedInfo ( ) . empty ( ) || RVFI -> useSaveRestoreLibCalls ( MF ) ) { RVFI -> setCalleeSavedStackSize ( 0 ) ; return ; } unsigned Size = 0 ; for ( const auto & Info : MFI . getCalleeSavedInfo ( ) ) { int FrameIdx = Info . getFrameIdx ( ) ; if ( MFI . getStackID ( FrameIdx ) != TargetStackID :: Default ) continue ; Size += MFI . getObjectSize ( FrameIdx ) ; } RVFI -> setCalleeSavedStackSize ( Size ) ; } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .

RISCV RISCV RISCV RISCV RISCV::GPRRegClass RISCV RISCV RISCV 11 0 0 0


<s> const ThumbRegisterInfo & getRegisterInfo ( ) const override { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> std :: pair < unsigned , const TargetRegisterClass * > MSP430TargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'r' : if ( VT == MVT :: i8 ) return std :: make_pair ( 0U , & MSP430 :: GR8RegClass ) ; return std :: make_pair ( 0U , & MSP430 :: GR16RegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> static rtx get_jump_target ( rtx branch ) { if ( CALL_P ( branch ) ) { rtx call ; call = PATTERN ( branch ) ; if ( GET_CODE ( call ) == PARALLEL ) call = XVECEXP ( call , 0 , 0 ) ; if ( GET_CODE ( call ) == SET ) call = SET_SRC ( call ) ; if ( GET_CODE ( call ) == CALL ) return XEXP ( XEXP ( call , 0 ) , 0 ) ; } return 0 ; } </s>


<s> bool mips_signed_immediate_p ( unsigned HOST_WIDE_INT x , int bits , int shift = 0 ) { x += 1 << ( bits + shift - 1 ) ; return mips_unsigned_immediate_p ( x , bits , shift ) ; } </s>

Return true if X fits within a signed field of BITS bits that is shifted left SHIFT bits before being used .


<s> unsigned WebAssemblyRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { static const unsigned Regs [ 2 ] [ 2 ] = { { WebAssembly :: SP32 , WebAssembly :: SP64 } , { WebAssembly :: FP32 , WebAssembly :: FP64 } } ; const WebAssemblyFrameLowering * TFI = getFrameLowering ( MF ) ; return Regs [ TFI -> hasFP ( MF ) ] [ TT . isArch64Bit ( ) ] ; } </s>


<s> PLTEntryBase * MipsPLT :: create ( ) { return new MipsPLTA ( * m_pSectionData ) ; } </s>


<s> bool isImm ( ) const override { return Kind == Integer || Kind == Symbol ; } </s>


<s> bool Cpu0AsmParser :: ParseDirective ( AsmToken DirectiveID ) { if ( DirectiveID . getString ( ) == ".ent" ) { Parser . Lex ( ) ; return false ; } if ( DirectiveID . getString ( ) == ".end" ) { Parser . Lex ( ) ; return false ; } if ( DirectiveID . getString ( ) == ".frame" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( DirectiveID . getString ( ) == ".set" ) { return parseDirectiveSet ( ) ; } if ( DirectiveID . getString ( ) == ".fmask" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( DirectiveID . getString ( ) == ".mask" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( DirectiveID . getString ( ) == ".gpword" ) { Parser . eatToEndOfStatement ( ) ; return false ; } return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> static bool th_mempair_operand_p ( rtx mem , machine_mode mode ) { if ( ! MEM_SIZE_KNOWN_P ( mem ) ) return false ; gcc_assert ( mode == SImode || mode == DImode ) ; auto mem_sz = MEM_SIZE ( mem ) ; auto mode_sz = GET_MODE_SIZE ( mode ) ; if ( ! known_eq ( mem_sz , mode_sz ) ) return false ; machine_mode mem_mode = GET_MODE ( mem ) ; unsigned shamt = ( mem_mode == DImode ) ? 4 : 3 ; rtx base ; HOST_WIDE_INT offset ; split_plus ( XEXP ( mem , 0 ) , & base , & offset ) ; HOST_WIDE_INT imm2 = offset >> shamt ; if ( imm2 < 0 || imm2 >= 4 ) return false ; if ( ( imm2 << shamt ) != offset ) return false ; return true ; } </s>

Check if the given MEM can be used to define the address of a mempair instruction .


<s> void PPCInstrInfo :: genAlternativeCodeSequence ( MachineInstr & Root , MachineCombinerPattern Pattern , SmallVectorImpl < MachineInstr * > & InsInstrs , SmallVectorImpl < MachineInstr * > & DelInstrs , DenseMap < unsigned , unsigned > & InstrIdxForVirtReg ) const { switch ( Pattern ) { case MachineCombinerPattern :: REASSOC_XY_AMM_BMM : case MachineCombinerPattern :: REASSOC_XMM_AMM_BMM : case MachineCombinerPattern :: REASSOC_XY_BCA : case MachineCombinerPattern :: REASSOC_XY_BAC : reassociateFMA ( Root , Pattern , InsInstrs , DelInstrs , InstrIdxForVirtReg ) ; break ; default : TargetInstrInfo :: genAlternativeCodeSequence ( Root , Pattern , InsInstrs , DelInstrs , InstrIdxForVirtReg ) ; break ; } } </s>

When getMachineCombinerPatterns ( ) finds potential patterns , this function generates the instructions that could replace the original code sequence .


<s> static bool ix86_class_likely_spilled_p ( reg_class_t rclass ) { switch ( rclass ) { case AREG : case DREG : case CREG : case BREG : case AD_REGS : case SIREG : case DIREG : case SSE_FIRST_REG : case FP_TOP_REG : case FP_SECOND_REG : return true ; default : break ; } return false ; } </s>


<s> bool AArch64TargetLowering :: useLoadStackGuardNode ( ) const { if ( Subtarget -> isTargetAndroid ( ) || Subtarget -> isTargetFuchsia ( ) ) return TargetLowering :: useLoadStackGuardNode ( ) ; return true ; } </s>

If this function returns true , SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic : :stackprotector .


<s>
static
bool
rename_single_chain
(
du_head_p
head
,
HARD_REG_SET
*
unavailable
)
{
int
best_new_reg
;
int
n_uses
=
0
;
struct
du_chain
*
tmp
;
int
reg
=
head
->
regno
;
enum
reg_class
super_class
=
NO_REGS
;
if
(
head
->
cannot_rename
)
return
false
;
if
(
fixed_regs
[
reg
]
||
global_regs
[
reg
]
||
(
frame_pointer_needed
&&
reg
==
HARD_FRAME_POINTER_REGNUM
)
)
return
false
;
for
(
tmp
=
head
->
first
;
tmp
;
tmp
=
tmp
->
next_use
)
{
if
(
DEBUG_INSN_P
(
tmp
->
insn
)
)
continue
;
n_uses
++
;
IOR_COMPL_HARD_REG_SET
(
*
unavailable
,
reg_class_contents
[
tmp
->
cl
]
)
;
super_class
=
reg_class_superunion
[
(
int
)
super_class
]
[
(
int
)
tmp
->
cl
]
;
}
if
(
n_uses
<
1
)
return
false
;
best_new_reg
=
find_rename_reg
(
head
,
super_class
,
unavailable
,
reg
,
false
)
;
if
(
dump_file
)
{
fprintf
(
dump_file
,
"Register %s in insn %d"
,
reg_names
[
reg
]
,
INSN_UID
(
head
->
first
->
insn
)
)
;
if
(
head
->
need_caller_save_reg
)
fprintf
(
dump_file
,
" crosses a call"
)
;
}
if
(
best_new_reg
==
reg
)
{
if
(
dump_file
)
fprintf
(
dump_file
,
"; no available better choice\n"
)
;
return
false
;
}
if
(
regrename_do_replace
(
head
,
best_new_reg
)
)
{
if
(
dump_file
)
fprintf
(
dump_file
,
", renamed as %s\n"
,
reg_names
[
best_new_reg
]
)
;
df_set_regs_ever_live
(
best_new_reg
,
true
)
;
}
else
{
if
(
dump_file
)
fprintf
(
dump_file
,
", renaming as %s failed\n"
,
reg_names
[
best_new_reg
]
)
;
return
false
;
}
return
true
;
}
</s>

Rename the register HEAD- > regno in all the insns in the chain HEAD to any register not in the set UNAVAILABLE . Adapted from rename_chains in regrename.c .


<s> static bool arm_block_set_unaligned_vect ( rtx dstbase , unsigned HOST_WIDE_INT length , unsigned HOST_WIDE_INT value , unsigned HOST_WIDE_INT align ) { unsigned int i , j , nelt_v16 , nelt_v8 , nelt_mode ; rtx dst , mem ; rtx val_elt , val_vec , reg ; rtx rval [ MAX_VECT_LEN ] ; rtx ( * gen_func ) ( rtx , rtx ) ; machine_mode mode ; unsigned HOST_WIDE_INT v = value ; gcc_assert ( ( align & 0x3 ) != 0 ) ; nelt_v8 = GET_MODE_NUNITS ( V8QImode ) ; nelt_v16 = GET_MODE_NUNITS ( V16QImode ) ; if ( length >= nelt_v16 ) { mode = V16QImode ; gen_func = gen_movmisalignv16qi ; } else { mode = V8QImode ; gen_func = gen_movmisalignv8qi ; } nelt_mode = GET_MODE_NUNITS ( mode ) ; gcc_assert ( length >= nelt_mode ) ; if ( ! arm_block_set_vect_profit_p ( length , align , mode ) ) return false ; dst = copy_addr_to_reg ( XEXP ( dstbase , 0 ) ) ; mem = adjust_automodify_address ( dstbase , mode , dst , 0 ) ; v = sext_hwi ( v , BITS_PER_WORD ) ; val_elt = GEN_INT ( v ) ; for ( j = 0 ; j < nelt_mode ; j ++ ) rval [ j ] = val_elt ; reg = gen_reg_rtx ( mode ) ; val_vec = gen_rtx_CONST_VECTOR ( mode , gen_rtvec_v ( nelt_mode , rval ) ) ; emit_move_insn ( reg , val_vec ) ; for ( i = 0 ; ( i + nelt_mode <= length ) ; i += nelt_mode ) { emit_insn ( ( * gen_func ) ( mem , reg ) ) ; if ( i + 2 * nelt_mode <= length ) emit_insn ( gen_add2_insn ( dst , GEN_INT ( nelt_mode ) ) ) ; } gcc_assert ( ( i + nelt_v8 ) > length || mode == V16QImode ) ; if ( i + nelt_v8 < length ) { emit_insn ( gen_add2_insn ( dst , GEN_INT ( length - i ) ) ) ; if ( ( length & 1 ) != 0 && align >= 2 ) set_mem_align ( mem , BITS_PER_UNIT ) ; emit_insn ( gen_movmisalignv16qi ( mem , reg ) ) ; } else if ( i < length && i + nelt_v8 >= length ) { if ( mode == V16QImode ) { reg = gen_lowpart ( V8QImode , reg ) ; mem = adjust_automodify_address ( dstbase , V8QImode , dst , 0 ) ; } emit_insn ( gen_add2_insn ( dst , GEN_INT ( ( length - i ) + ( nelt_mode - nelt_v8 ) ) ) ) ; if ( ( length & 1 ) != 0 && align >= 2 ) set_mem_align ( mem , BITS_PER_UNIT ) ; emit_insn ( gen_movmisalignv8qi ( mem , reg ) ) ; } return true ; } </s>

Set a block of memory using vectorization instructions for the unaligned case . We fill the first LENGTH bytes of the memory area starting from DSTBASE with byte constant VALUE . ALIGN is the alignment requirement of memory . Return TRUE if succeeded .


<s> virtual const InstrItineraryData * getInstrItineraryData ( ) const { return Subtarget . inMips16Mode ( ) ? 0 : & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> static unsigned parse_env_var ( const char * str , char * * * pvalues ) { const char * curval , * nextval ; char * * values ; unsigned num = 1 , i ; curval = strchr ( str , ':' ) ; while ( curval ) { num ++ ; curval = strchr ( curval + 1 , ':' ) ; } values = ( char * * ) xmalloc ( num * sizeof ( char * ) ) ; curval = str ; nextval = strchr ( curval , ':' ) ; if ( nextval == NULL ) nextval = strchr ( curval , '\0' ) ; for ( i = 0 ; i < num ; i ++ ) { int l = nextval - curval ; values [ i ] = ( char * ) xmalloc ( l + 1 ) ; memcpy ( values [ i ] , curval , l ) ; values [ i ] [ l ] = 0 ; curval = nextval + 1 ; nextval = strchr ( curval , ':' ) ; if ( nextval == NULL ) nextval = strchr ( curval , '\0' ) ; } * pvalues = values ; return num ; } </s>

Parse STR , saving found tokens into PVALUES and return their number . Tokens are assumed to be delimited by ' : ' .


<s> unsigned RISCVAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { RISCVOperand & Op = static_cast < RISCVOperand & > ( AsmOp ) ; if ( ! Op . isReg ( ) ) return Match_InvalidOperand ; unsigned Reg = Op . getReg ( ) ; bool IsRegFPR32 = RISCVMCRegisterClasses [ RISCV :: FPR32RegClassID ] . contains ( Reg ) ; bool IsRegFPR32C = RISCVMCRegisterClasses [ RISCV :: FPR32CRegClassID ] . contains ( Reg ) ; if ( ( IsRegFPR32 && Kind == MCK_FPR64 ) || ( IsRegFPR32C && Kind == MCK_FPR64C ) ) { Op . Reg . RegNum = convertFPR32ToFPR64 ( Reg ) ; return Match_Success ; } return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .

RISCV RISCV RISCV RISCV RISCV RISCV::FPR32RegClassID RISCV RISCV::FPR32CRegClassID


"Patmos Single-Path Scheduler (machine code)"

getPassName - Return a nice clean name for a pass .


<s> const MCFixup * RISCVMCExpr :: getPCRelHiFixup ( const MCFragment * * DFOut ) const { MCValue AUIPCLoc ; if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( AUIPCLoc , nullptr , nullptr ) ) return nullptr ; const MCSymbolRefExpr * AUIPCSRE = AUIPCLoc . getSymA ( ) ; if ( ! AUIPCSRE ) return nullptr ; const MCSymbol * AUIPCSymbol = & AUIPCSRE -> getSymbol ( ) ; const auto * DF = dyn_cast_or_null < MCDataFragment > ( AUIPCSymbol -> getFragment ( ) ) ; if ( ! DF ) return nullptr ; uint64_t Offset = AUIPCSymbol -> getOffset ( ) ; if ( DF -> getContents ( ) . size ( ) == Offset ) { DF = dyn_cast_or_null < MCDataFragment > ( DF -> getNextNode ( ) ) ; if ( ! DF ) return nullptr ; Offset = 0 ; } for ( const MCFixup & F : DF -> getFixups ( ) ) { if ( F . getOffset ( ) != Offset ) continue ; switch ( ( unsigned ) F . getKind ( ) ) { default : continue ; case RISCV :: fixup_riscv_got_hi20 : case RISCV :: fixup_riscv_tls_got_hi20 : case RISCV :: fixup_riscv_tls_gd_hi20 : case RISCV :: fixup_riscv_pcrel_hi20 : case RISCV :: fixup_riscv_captab_pcrel_hi20 : case RISCV :: fixup_riscv_tls_ie_captab_pcrel_hi20 : case RISCV :: fixup_riscv_tls_gd_captab_pcrel_hi20 : if ( DFOut ) * DFOut = DF ; return & F ; } } return nullptr ; } </s>

Get the corresponding PC-relative HI fixup that a VK_RISCV_PCREL_LO points to , and optionally the fragment containing it .