<s> bool MipsCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) { return false ; } for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( Arg . getType ( ) ) ) return false ; } MachineFunction & MF = MIRBuilder . getMF ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const MipsTargetLowering & TLI = * getTLI < MipsTargetLowering > ( ) ; SmallVector < ArgInfo , 8 > ArgInfos ; SmallVector < unsigned , 8 > OrigArgIndices ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ i ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , i + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( AInfo , i , ArgInfos , OrigArgIndices ) ; ++ i ; } SmallVector < ISD :: InputArg , 8 > Ins ; subTargetRegTypeForCallingConv ( MIRBuilder , ArgInfos , OrigArgIndices , [ & ] ( ISD :: ArgFlagsTy flags , EVT vt , EVT argvt , bool used , unsigned origIdx , unsigned partOffs ) { Ins . emplace_back ( flags , vt , argvt , used , origIdx , partOffs ) ; } ) ; SmallVector < CCValAssign , 16 > ArgLocs ; MipsCCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , TLI . CCAssignFnForCall ( ) ) ; IncomingValueHandler Handler ( MIRBuilder , MF . getRegInfo ( ) ) ; if ( ! Handler . handle ( ArgLocs , ArgInfos ) ) return false ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> void rs6000_split_logical ( rtx operands [ 3 ] , enum rtx_code code , bool complement_final_p , bool complement_op1_p , bool complement_op2_p ) { machine_mode mode = GET_MODE ( operands [ 0 ] ) ; machine_mode sub_mode ; rtx op0 , op1 , op2 ; int sub_size , regno0 , regno1 , nregs , i ; if ( mode == DImode && ! TARGET_POWERPC64 ) { rs6000_split_logical_di ( operands , code , complement_final_p , complement_op1_p , complement_op2_p ) ; return ; } op0 = operands [ 0 ] ; op1 = operands [ 1 ] ; op2 = ( code == NOT ) ? NULL_RTX : operands [ 2 ] ; sub_mode = ( TARGET_POWERPC64 ) ? DImode : SImode ; sub_size = GET_MODE_SIZE ( sub_mode ) ; regno0 = REGNO ( op0 ) ; regno1 = REGNO ( op1 ) ; gcc_assert ( reload_completed ) ; gcc_assert ( IN_RANGE ( regno0 , FIRST_GPR_REGNO , LAST_GPR_REGNO ) ) ; gcc_assert ( IN_RANGE ( regno1 , FIRST_GPR_REGNO , LAST_GPR_REGNO ) ) ; nregs = rs6000_hard_regno_nregs [ ( int ) mode ] [ regno0 ] ; gcc_assert ( nregs > 1 ) ; if ( op2 && REG_P ( op2 ) ) gcc_assert ( IN_RANGE ( REGNO ( op2 ) , FIRST_GPR_REGNO , LAST_GPR_REGNO ) ) ; for ( i = 0 ; i < nregs ; i ++ ) { int offset = i * sub_size ; rtx sub_op0 = simplify_subreg ( sub_mode , op0 , mode , offset ) ; rtx sub_op1 = simplify_subreg ( sub_mode , op1 , mode , offset ) ; rtx sub_op2 = ( ( code == NOT ) ? NULL_RTX : simplify_subreg ( sub_mode , op2 , mode , offset ) ) ; rs6000_split_logical_inner ( sub_op0 , sub_op1 , sub_op2 , code , sub_mode , complement_final_p , complement_op1_p , complement_op2_p ) ; } return ; } </s>

Split the insns that make up boolean operations operating on multiple GPR registers . The boolean MD patterns ensure that the inputs either are exactly the same as the output registers , or there is no overlap . OPERANDS is an array containing the destination and two input operands . CODE is the base operation ( AND , IOR , XOR , NOT ) . If COMPLEMENT_FINAL_P is true , wrap the whole operation with NOT . If COMPLEMENT_OP1_P is true , wrap operand1 with NOT . If COMPLEMENT_OP2_P is true , wrap operand2 with NOT .


"rs6000_secondary_reload_inner:%d, type = %s\n"

Better tracing for rs6000_secondary_reload_inner .


<s>
StringRef
getPassName
(
)
const
override
{
return
"AArch64 Compress Jump Tables"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"********** Prepare For LiveIntervals **********\n"

"LiveIntervals shouldn't be active yet!"

runOnMachineFunction - Emit the function body .


<s> const CallLowering * RISCVSubtarget :: getCallLowering ( ) const { return CallLoweringInfo . get ( ) ; } </s>


<s> bool Warning ( SMLoc L , const Twine & Msg , ArrayRef < SMRange > Ranges = ArrayRef < SMRange > ( ) ) { return Parser . Warning ( L , Msg , Ranges ) ; } </s>

Emit a warning at the location L , with the message Msg .


<s> bool isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const override { return true ; } </s>

Returns true if a cast between SrcAS and DestAS is a noop .


<s> unsigned SITargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( CC != CallingConv :: AMDGPU_KERNEL && VT . isVector ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; EVT ScalarVT = VT . getScalarType ( ) ; unsigned Size = ScalarVT . getSizeInBits ( ) ; if ( Size == 32 ) return NumElts ; if ( Size == 64 ) return 2 * NumElts ; if ( Size == 16 && Subtarget -> has16BitInsts ( ) ) return ( VT . getVectorNumElements ( ) + 1 ) / 2 ; } return TargetLowering :: getNumRegistersForCallingConv ( Context , CC , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
auto
PrintImmValue
=
[
&
]
(
const
MCExpr
*
Val
,
const
char
*
VName
)
{
if
(
Val
->
getKind
(
)
==
MCExpr
::
Constant
)
{
if
(
auto
Imm
=
cast
<
MCConstantExpr
>
(
Val
)
->
getValue
(
)
)
OS
<<
VName
<<
Imm
;
}
else
if
(
Val
->
getKind
(
)
==
MCExpr
::
SymbolRef
)
{
if
(
auto
*
SRE
=
dyn_cast
<
MCSymbolRefExpr
>
(
Val
)
)
{
const
MCSymbol
&
Sym
=
SRE
->
getSymbol
(
)
;
if
(
const
char
*
SymNameStr
=
Sym
.
getName
(
)
.
data
(
)
)
OS
<<
VName
<<
SymNameStr
;
}
}
}
;
switch
(
Kind
)
{
case
Token
:
OS
<<
Tok
.
Data
;
break
;
case
Register
:
OS
<<
"Reg:"
<<
X86IntelInstPrinter
::
getRegisterName
(
Reg
.
RegNo
)
;
break
;
case
DXRegister
:
OS
<<
"DXReg"
;
break
;
case
Immediate
:
PrintImmValue
(
Imm
.
Val
,
"Imm:"
)
;
break
;
case
Prefix
:
OS
<<
"Prefix:"
<<
Pref
.
Prefixes
;
break
;
case
Memory
:
OS
<<
"Memory: ModeSize="
<<
Mem
.
ModeSize
;
if
(
Mem
.
Size
)
OS
<<
",Size="
<<
Mem
.
Size
;
if
(
Mem
.
BaseReg
)
OS
<<
",BaseReg="
<<
X86IntelInstPrinter
::
getRegisterName
(
Mem
.
BaseReg
)
;
if
(
Mem
.
IndexReg
)
OS
<<
",IndexReg="
<<
X86IntelInstPrinter
::
getRegisterName
(
Mem
.
IndexReg
)
;
if
(
Mem
.
Scale
)
OS
<<
",Scale="
<<
Mem
.
Scale
;
if
(
Mem
.
Disp
)
PrintImmValue
(
Mem
.
Disp
,
",Disp="
)
;
if
(
Mem
.
SegReg
)
OS
<<
",SegReg="
<<
X86IntelInstPrinter
::
getRegisterName
(
Mem
.
SegReg
)
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

X86
"Reg:"
X86
"DXReg"
"Imm:"
"Prefix:"
"Memory: ModeSize="
",Size="
",BaseReg="
X86
",IndexReg="
X86
",Scale="
",Disp="
",SegReg="
X86


"getJumpTargetOpValue expects only expressions"

getJumpTargetOpValue - Return binary encoding of the jump target operand .


<s>
void
TOYDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
DEBUG
(
dbgs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
dbgs
(
)
<<
"== custom Opcode "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;
return
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

TOY
TOY
"Selecting: "
"\n"
"== custom Opcode "
"\n"


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> std :: unique_ptr < CSEConfigBase > AArch64PassConfig :: getCSEConfig ( ) const { return getStandardCSEConfigForOpt ( TM -> getOptLevel ( ) ) ; } </s>

Returns the CSEConfig object to use for the current optimization level .


<s> static recps_type get_recps_type ( machine_mode mode ) { switch ( mode ) { case SFmode : return ( gen_aarch64_frecpssf ) ; case V2SFmode : return ( gen_aarch64_frecpsv2sf ) ; case V4SFmode : return ( gen_aarch64_frecpsv4sf ) ; case DFmode : return ( gen_aarch64_frecpsdf ) ; case V2DFmode : return ( gen_aarch64_frecpsv2df ) ; default : gcc_unreachable ( ) ; } } </s>

Select reciprocal series step insn depending on machine mode .


<s>
const
char
*
output_fp_compare
(
rtx_insn
*
insn
,
rtx
*
operands
,
bool
eflags_p
,
bool
unordered_p
)
{
int
stack_top_dies
;
rtx
cmp_op0
,
cmp_op1
;
int
is_sse
=
SSE_REG_P
(
operands
[
0
]
)
||
SSE_REG_P
(
operands
[
1
]
)
;
if
(
eflags_p
)
{
cmp_op0
=
operands
[
0
]
;
cmp_op1
=
operands
[
1
]
;
}
else
{
cmp_op0
=
operands
[
1
]
;
cmp_op1
=
operands
[
2
]
;
}
if
(
is_sse
)
{
if
(
GET_MODE
(
operands
[
0
]
)
==
SFmode
)
if
(
unordered_p
)
return
"%vucomiss\t{%1, %0|%0, %1}"
;
else
return
"%vcomiss\t{%1, %0|%0, %1}"
;
else
if
(
unordered_p
)
return
"%vucomisd\t{%1, %0|%0, %1}"
;
else
return
"%vcomisd\t{%1, %0|%0, %1}"
;
}
gcc_assert
(
STACK_TOP_P
(
cmp_op0
)
)
;
stack_top_dies
=
find_regno_note
(
insn
,
REG_DEAD
,
FIRST_STACK_REG
)
!=
0
;
if
(
cmp_op1
==
CONST0_RTX
(
GET_MODE
(
cmp_op1
)
)
)
{
if
(
stack_top_dies
)
{
output_asm_insn
(
"ftst\n\tfnstsw\t%0"
,
operands
)
;
return
output_387_ffreep
(
operands
,
1
)
;
}
else
return
"ftst\n\tfnstsw\t%0"
;
}
if
(
STACK_REG_P
(
cmp_op1
)
&&
stack_top_dies
&&
find_regno_note
(
insn
,
REG_DEAD
,
REGNO
(
cmp_op1
)
)
&&
REGNO
(
cmp_op1
)
!=
FIRST_STACK_REG
)
{
if
(
eflags_p
)
{
if
(
unordered_p
)
output_asm_insn
(
"fucomip\t{%y1, %0|%0, %y1}"
,
operands
)
;
else
output_asm_insn
(
"fcomip\t{%y1, %0|%0, %y1}"
,
operands
)
;
return
output_387_ffreep
(
operands
,
0
)
;
}
else
{
if
(
unordered_p
)
return
"fucompp\n\tfnstsw\t%0"
;
else
return
"fcompp\n\tfnstsw\t%0"
;
}
}
else
{
static
const
char
*
const
alt
[
16
]
=
{
"fcom%Z2\t%y2\n\tfnstsw\t%0"
,
"fcomp%Z2\t%y2\n\tfnstsw\t%0"
,
"fucom%Z2\t%y2\n\tfnstsw\t%0"
,
"fucomp%Z2\t%y2\n\tfnstsw\t%0"
,
"ficom%Z2\t%y2\n\tfnstsw\t%0"
,
"ficomp%Z2\t%y2\n\tfnstsw\t%0"
,
,
,
"fcomi\t{%y1, %0|%0, %y1}"
,
"fcomip\t{%y1, %0|%0, %y1}"
,
"fucomi\t{%y1, %0|%0, %y1}"
,
"fucomip\t{%y1, %0|%0, %y1}"
,
,
,
,
}
;
int
mask
;
const
char
*
ret
;
mask
=
eflags_p
<<
3
;
mask
|=
(
GET_MODE_CLASS
(
GET_MODE
(
cmp_op1
)
)
==
MODE_INT
)
<<
2
;
mask
|=
unordered_p
<<
1
;
mask
|=
stack_top_dies
;
gcc_assert
(
mask
<
16
)
;
ret
=
alt
[
mask
]
;
gcc_assert
(
ret
)
;
return
ret
;
}
}
</s>

Output code for INSN to compare OPERANDS . EFLAGS_P is 1 when fcomi should be used and 2 when fnstsw should be used . UNORDERED_P is true when fucom should be used .


<s> const TargetRegisterClass * F2003fRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & F2003f :: RegRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


Return an array that contains the direct target flag values and their names .


<s> int pa_attr_length_call ( rtx_insn * insn , int sibcall ) { int local_call ; rtx call , call_dest ; tree call_decl ; int length = 0 ; rtx pat = PATTERN ( insn ) ; unsigned long distance = - 1 ; gcc_assert ( CALL_P ( insn ) ) ; if ( INSN_ADDRESSES_SET_P ( ) ) { unsigned long total ; total = IN_NAMED_SECTION_P ( cfun -> decl ) ? 0 : total_code_bytes ; distance = ( total + insn_current_reference_address ( insn ) ) ; if ( distance < total ) distance = - 1 ; } gcc_assert ( GET_CODE ( pat ) == PARALLEL ) ; call = XVECEXP ( pat , 0 , 0 ) ; if ( GET_CODE ( call ) == SET ) call = SET_SRC ( call ) ; gcc_assert ( GET_CODE ( call ) == CALL ) ; call_dest = XEXP ( XEXP ( call , 0 ) , 0 ) ; call_decl = SYMBOL_REF_DECL ( call_dest ) ; local_call = call_decl && targetm . binds_local_p ( call_decl ) ; if ( ! TARGET_LONG_CALLS && ( ( TARGET_PA_20 && ! sibcall && distance < 7600000 ) || distance < MAX_PCREL17F_OFFSET ) ) length += 8 ; else if ( TARGET_64BIT && ! local_call ) length += sibcall ? 28 : 24 ; else if ( ( TARGET_LONG_ABS_CALL || local_call ) && ! flag_pic ) length += 12 ; else if ( TARGET_LONG_PIC_SDIFF_CALL || ( TARGET_GAS && ! TARGET_SOM && ( TARGET_LONG_PIC_PCREL_CALL || local_call ) ) ) { length += 20 ; if ( ! TARGET_PA_20 && ! TARGET_NO_SPACE_REGS && ( ! local_call || flag_pic ) ) length += 8 ; } else { length += 32 ; if ( TARGET_SOM ) length += length_fp_args ( insn ) ; if ( flag_pic ) length += 4 ; if ( ! TARGET_PA_20 ) { if ( ! sibcall ) length += 8 ; if ( ! TARGET_NO_SPACE_REGS && ( ! local_call || flag_pic ) ) length += 8 ; } } return length ; } </s>

Return the attribute length of the call instruction INSN . The SIBCALL flag indicates whether INSN is a regular call or a sibling call . The length returned must be longer than the code actually generated by pa_output_call . Since branch shortening is done before delay branch sequencing , there is no way to determine whether or not the delay slot will be filled during branch shortening . Even when the delay slot is filled , we may have to add a nop if the delay slot contains a branch that ca n't reach its target . Thus , we always have to include the delay slot in the length estimate . This used to be done in pa_adjust_insn_length but we do it here now as some sequences always fill the delay slot and we can save four bytes in the estimate for these sequences .


<s>
const
char
*
getPassName
(
)
const
{
return
"R600 Eliminate Symbolic Operand"
;
}
</s>


<s> unsigned X86TTIImpl :: getNumberOfRegisters ( unsigned ClassID ) const { bool Vector = ( ClassID == 1 ) ; if ( Vector && ! ST -> hasSSE1 ( ) ) return 0 ; if ( ST -> is64Bit ( ) ) { if ( Vector && ST -> hasAVX512 ( ) ) return 32 ; return 16 ; } return 8 ; } </s>


<s> static SDValue WidenVector ( SDValue V64Reg , SelectionDAG & DAG ) { EVT VT = V64Reg . getValueType ( ) ; unsigned NarrowSize = VT . getVectorNumElements ( ) ; MVT EltTy = VT . getVectorElementType ( ) . getSimpleVT ( ) ; MVT WideTy = MVT :: getVectorVT ( EltTy , 2 * NarrowSize ) ; SDLoc DL ( V64Reg ) ; return DAG . getNode ( ISD :: INSERT_SUBVECTOR , DL , WideTy , DAG . getUNDEF ( WideTy ) , V64Reg , DAG . getConstant ( 0 , DL , MVT :: i64 ) ) ; } </s>

Widen the vector up to the next power of two using INSERT_SUBVECTOR .


"// ia64_dfa_sched_reorder (type %d):\n"

We are about to being issuing insns for this clock cycle . Override the default sort algorithm to better slot instructions .


<s> const X86_64GOT & X86_64GNULDBackend :: getGOT ( ) const { assert ( m_pGOT != NULL ) ; return * m_pGOT ; } </s>

Return a pseudo source value referencing the global offset table ( or something the like ) .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s>
SDValue
AMDGPUTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
Op
->
print
(
errs
(
)
,
&
DAG
)
;
llvm_unreachable
(
"Custom lowering code for this"
"instruction is not implemented yet!"
)
;
break
;
case
ISD
::
SIGN_EXTEND_INREG
:
return
LowerSIGN_EXTEND_INREG
(
Op
,
DAG
)
;
case
ISD
::
CONCAT_VECTORS
:
return
LowerCONCAT_VECTORS
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_SUBVECTOR
:
return
LowerEXTRACT_SUBVECTOR
(
Op
,
DAG
)
;
case
ISD
::
UDIVREM
:
return
LowerUDIVREM
(
Op
,
DAG
)
;
case
ISD
::
SDIVREM
:
return
LowerSDIVREM
(
Op
,
DAG
)
;
case
ISD
::
FREM
:
return
LowerFREM
(
Op
,
DAG
)
;
case
ISD
::
FCEIL
:
return
LowerFCEIL
(
Op
,
DAG
)
;
case
ISD
::
FTRUNC
:
return
LowerFTRUNC
(
Op
,
DAG
)
;
case
ISD
::
FRINT
:
return
LowerFRINT
(
Op
,
DAG
)
;
case
ISD
::
FNEARBYINT
:
return
LowerFNEARBYINT
(
Op
,
DAG
)
;
case
ISD
::
FROUND
:
return
LowerFROUND
(
Op
,
DAG
)
;
case
ISD
::
FFLOOR
:
return
LowerFFLOOR
(
Op
,
DAG
)
;
case
ISD
::
FLOG
:
return
LowerFLOG
(
Op
,
DAG
,
1
/
AMDGPU_LOG2E_F
)
;
case
ISD
::
FLOG10
:
return
LowerFLOG
(
Op
,
DAG
,
AMDGPU_LN2_F
/
AMDGPU_LN10_F
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerSINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
UINT_TO_FP
:
return
LowerUINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_FP16
:
return
LowerFP_TO_FP16
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_SINT
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_UINT
(
Op
,
DAG
)
;
case
ISD
::
CTTZ
:
case
ISD
::
CTTZ_ZERO_UNDEF
:
case
ISD
::
CTLZ
:
case
ISD
::
CTLZ_ZERO_UNDEF
:
return
LowerCTLZ_CTTZ
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
}
return
Op
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> void assignValueToAddress ( Register ValVReg , Register Addr , LLT MemTy , MachinePointerInfo & MPO , CCValAssign & VA ) override { MachineFunction & MF = MIRBuilder . getMF ( ) ; LLT ValTy ( VA . getValVT ( ) ) ; LLT LocTy ( VA . getLocVT ( ) ) ; if ( VA . getValVT ( ) == MVT :: i8 || VA . getValVT ( ) == MVT :: i16 ) std :: swap ( ValTy , LocTy ) ; else { assert ( LocTy . getSizeInBits ( ) == MemTy . getSizeInBits ( ) ) ; LocTy = MemTy ; } auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant , LocTy , inferAlignFromPtrInfo ( MF , MPO ) ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: LocInfo :: ZExt : MIRBuilder . buildLoadInstr ( TargetOpcode :: G_ZEXTLOAD , ValVReg , Addr , * MMO ) ; return ; case CCValAssign :: LocInfo :: SExt : MIRBuilder . buildLoadInstr ( TargetOpcode :: G_SEXTLOAD , ValVReg , Addr , * MMO ) ; return ; default : MIRBuilder . buildLoad ( ValVReg , Addr , * MMO ) ; return ; } } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> void WebAssemblyTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { switch ( Op . getOpcode ( ) ) { default : break ; case ISD :: INTRINSIC_WO_CHAIN : { unsigned IntNo = Op . getConstantOperandVal ( 0 ) ; switch ( IntNo ) { default : break ; case Intrinsic :: wasm_bitmask : { unsigned BitWidth = Known . getBitWidth ( ) ; EVT VT = Op . getOperand ( 1 ) . getSimpleValueType ( ) ; unsigned PossibleBits = VT . getVectorNumElements ( ) ; APInt ZeroMask = APInt :: getHighBitsSet ( BitWidth , BitWidth - PossibleBits ) ; Known . Zero |= ZeroMask ; break ; } } } } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s>
void
ARMTTIImpl
::
getUnrollingPreferences
(
Loop
*
L
,
ScalarEvolution
&
SE
,
TTI
::
UnrollingPreferences
&
UP
)
{
if
(
!
ST
->
isMClass
(
)
)
return
BasicTTIImplBase
::
getUnrollingPreferences
(
L
,
SE
,
UP
)
;
UP
.
OptSizeThreshold
=
0
;
UP
.
PartialOptSizeThreshold
=
0
;
if
(
L
->
getHeader
(
)
->
getParent
(
)
->
optForSize
(
)
)
return
;
if
(
!
ST
->
isThumb2
(
)
)
return
;
SmallVector
<
BasicBlock
*
,
4
>
ExitingBlocks
;
L
->
getExitingBlocks
(
ExitingBlocks
)
;
DEBUG
(
dbgs
(
)
<<
"Loop has:\n"
<<
"Blocks: "
<<
L
->
getNumBlocks
(
)
<<
"\n"
<<
"Exit blocks: "
<<
ExitingBlocks
.
size
(
)
<<
"\n"
)
;
if
(
ExitingBlocks
.
size
(
)
>
2
)
return
;
if
(
ST
->
hasBranchPredictor
(
)
&&
L
->
getNumBlocks
(
)
>
4
)
return
;
unsigned
Cost
=
0
;
for
(
auto
*
BB
:
L
->
getBlocks
(
)
)
{
for
(
auto
&
I
:
*
BB
)
{
if
(
isa
<
CallInst
>
(
I
)
||
isa
<
InvokeInst
>
(
I
)
)
{
ImmutableCallSite
CS
(
&
I
)
;
if
(
const
Function
*
F
=
CS
.
getCalledFunction
(
)
)
{
if
(
!
isLoweredToCall
(
F
)
)
continue
;
}
return
;
}
SmallVector
<
const
Value
*
,
4
>
Operands
(
I
.
value_op_begin
(
)
,
I
.
value_op_end
(
)
)
;
Cost
+=
getUserCost
(
&
I
,
Operands
)
;
}
}
DEBUG
(
dbgs
(
)
<<
"Cost of loop: "
<<
Cost
<<
"\n"
)
;
UP
.
Partial
=
true
;
UP
.
Runtime
=
true
;
UP
.
UnrollRemainder
=
true
;
UP
.
DefaultUnrollRuntimeCount
=
4
;
if
(
Cost
<
12
)
UP
.
Force
=
true
;
}
</s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> bool ARMBaseInstrInfo :: hasLowDefLatency ( const InstrItineraryData * ItinData , const MachineInstr * DefMI , unsigned DefIdx ) const { if ( ! ItinData || ItinData -> isEmpty ( ) ) return false ; unsigned DDomain = DefMI -> getDesc ( ) . TSFlags & ARMII :: DomainMask ; if ( DDomain == ARMII :: DomainGeneral ) { unsigned DefClass = DefMI -> getDesc ( ) . getSchedClass ( ) ; int DefCycle = ItinData -> getOperandCycle ( DefClass , DefIdx ) ; return ( DefCycle != - 1 && DefCycle <= 2 ) ; } return false ; } </s>

Compute operand latency of a def of 'Reg ' .

ARM ARM ARMII::DomainMask ARMII::DomainGeneral 1 2


<s> unsigned HexagonMCInstrInfo :: getType ( MCInstrInfo const & MCII , MCInst const & MCI ) { const uint64_t F = HexagonMCInstrInfo :: getDesc ( MCII , MCI ) . TSFlags ; return ( ( F >> HexagonII :: TypePos ) & HexagonII :: TypeMask ) ; } </s>

Overload to return most specific vector type .

Hexagon Hexagon Hexagon HexagonII::TypePos HexagonII::TypeMask


<s> static void ix86_lower_local_decl_alignment ( tree decl ) { unsigned int new_align = ix86_local_alignment ( decl , VOIDmode , DECL_ALIGN ( decl ) , true ) ; if ( new_align < DECL_ALIGN ( decl ) ) SET_DECL_ALIGN ( decl , new_align ) ; } </s>


<s> static void query ( const MachineInstr & MI , AliasAnalysis & AA , bool & Read , bool & Write , bool & Effects , bool & StackPointer ) { assert ( ! MI . isTerminator ( ) ) ; if ( MI . isDebugInstr ( ) || MI . isPosition ( ) ) return ; if ( MI . mayLoad ( ) && ! MI . isDereferenceableInvariantLoad ( & AA ) ) Read = true ; if ( MI . mayStore ( ) ) { Write = true ; } else if ( MI . hasOrderedMemoryRef ( ) ) { switch ( MI . getOpcode ( ) ) { case WebAssembly :: DIV_S_I32 : case WebAssembly :: DIV_S_I64 : case WebAssembly :: REM_S_I32 : case WebAssembly :: REM_S_I64 : case WebAssembly :: DIV_U_I32 : case WebAssembly :: DIV_U_I64 : case WebAssembly :: REM_U_I32 : case WebAssembly :: REM_U_I64 : case WebAssembly :: I32_TRUNC_S_F32 : case WebAssembly :: I64_TRUNC_S_F32 : case WebAssembly :: I32_TRUNC_S_F64 : case WebAssembly :: I64_TRUNC_S_F64 : case WebAssembly :: I32_TRUNC_U_F32 : case WebAssembly :: I64_TRUNC_U_F32 : case WebAssembly :: I32_TRUNC_U_F64 : case WebAssembly :: I64_TRUNC_U_F64 : break ; default : if ( ! MI . isCall ( ) ) { Write = true ; Effects = true ; } break ; } } if ( MI . hasUnmodeledSideEffects ( ) ) { switch ( MI . getOpcode ( ) ) { case WebAssembly :: DIV_S_I32 : case WebAssembly :: DIV_S_I64 : case WebAssembly :: REM_S_I32 : case WebAssembly :: REM_S_I64 : case WebAssembly :: DIV_U_I32 : case WebAssembly :: DIV_U_I64 : case WebAssembly :: REM_U_I32 : case WebAssembly :: REM_U_I64 : case WebAssembly :: I32_TRUNC_S_F32 : case WebAssembly :: I64_TRUNC_S_F32 : case WebAssembly :: I32_TRUNC_S_F64 : case WebAssembly :: I64_TRUNC_S_F64 : case WebAssembly :: I32_TRUNC_U_F32 : case WebAssembly :: I64_TRUNC_U_F32 : case WebAssembly :: I32_TRUNC_U_F64 : case WebAssembly :: I64_TRUNC_U_F64 : break ; default : Effects = true ; break ; } } if ( MI . getOpcode ( ) == WebAssembly :: GLOBAL_SET_I32 && strcmp ( MI . getOperand ( 0 ) . getSymbolName ( ) , "__stack_pointer" ) == 0 ) StackPointer = true ; if ( MI . isCall ( ) ) { unsigned CalleeOpNo = WebAssembly :: getCalleeOpNo ( MI ) ; queryCallee ( MI , CalleeOpNo , Read , Write , Effects , StackPointer ) ; } } </s>

Query a line of the assigned virtual register matrix directly .


<s> bool RISCVAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( ( Count % 4 ) != 0 ) return false ; for ( uint64_t i = 0 ; i < Count ; i += 4 ) OW -> write32 ( 0x13 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> bool SIRegisterInfo :: requiresFrameIndexScavenging ( const MachineFunction & MF ) const { return MF . getFrameInfo ( ) -> hasStackObjects ( ) ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> SDValue PPCTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { if ( Subtarget . is64BitELFABI ( ) ) return LowerFormalArguments_64SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; else if ( Subtarget . is32BitELFABI ( ) ) return LowerFormalArguments_32SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; return LowerFormalArguments_Darwin ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> bool AMDGPUAlwaysInline :: runOnModule ( Module & M ) { std :: vector < Function * > FuncsToClone ; for ( Function & F : M ) { if ( ! F . hasLocalLinkage ( ) && ! F . isDeclaration ( ) && ! F . use_empty ( ) && ! F . hasFnAttribute ( Attribute :: NoInline ) ) FuncsToClone . push_back ( & F ) ; } for ( Function * F : FuncsToClone ) { ValueToValueMapTy VMap ; Function * NewFunc = CloneFunction ( F , VMap ) ; NewFunc -> setLinkage ( GlobalValue :: InternalLinkage ) ; F -> replaceAllUsesWith ( NewFunc ) ; } for ( Function & F : M ) { if ( F . hasLocalLinkage ( ) && ! F . hasFnAttribute ( Attribute :: NoInline ) ) { F . addFnAttr ( Attribute :: AlwaysInline ) ; } } return false ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> static bool csky_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { return ( GET_MODE_SIZE ( from ) == GET_MODE_SIZE ( to ) || ! reg_classes_intersect_p ( V_REGS , rclass ) ) ; } </s>

Implement TARGET_CAN_CHANGE_MODE_CLASS . V_REG registers ca n't do subreg as all values are reformatted to internal precision .


<s> const TargetRegisterClass * GBZ80RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & GB :: R16RegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


runOnMachineFunction - Emit the function body .


<s> static void s300_set_up_by_prologue ( hard_reg_set_container * regs ) { if ( cfun -> machine -> base_reg && ! call_really_used_regs [ REGNO ( cfun -> machine -> base_reg ) ] ) SET_HARD_REG_BIT ( regs -> set , REGNO ( cfun -> machine -> base_reg ) ) ; } </s>


<s> static inline bool getConstantValue ( SDValue N , uint32_t & Out ) { if ( N . isUndef ( ) ) { Out = 0 ; return true ; } if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N ) ) { Out = C -> getAPIntValue ( ) . getSExtValue ( ) ; return true ; } if ( const ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( N ) ) { Out = C -> getValueAPF ( ) . bitcastToAPInt ( ) . getSExtValue ( ) ; return true ; } return false ; } </s>

Converts a Constant * into a GenericValue , including handling of ConstantExpr values .


<s>
SDValue
ARCompactTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
default
:
assert
(
0
&&
"Unimplemented operation!"
)
;
return
SDValue
(
)
;
}
}
</s>


<s> bool X86TTIImpl :: isLegalMaskedCompressStore ( Type * DataTy ) { return isLegalMaskedExpandLoad ( DataTy ) ; } </s>

Return true if the target supports masked compress store .


<s> bool LinearizedRegion :: contains ( MachineBasicBlock * MBB ) { return MBBs . contains ( MBB ) ; } </s>

contains - Returns true if this trace contains the given basic block .


<s> void WebAssemblyTTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP ) const { for ( BasicBlock * BB : L -> blocks ( ) ) for ( Instruction & I : * BB ) if ( isa < CallInst > ( I ) || isa < InvokeInst > ( I ) ) if ( const Function * F = cast < CallBase > ( I ) . getCalledFunction ( ) ) if ( isLoweredToCall ( F ) ) return ; UP . Partial = UP . Runtime = UP . UpperBound = true ; UP . PartialThreshold = 30 ; UP . OptSizeThreshold = 0 ; UP . PartialOptSizeThreshold = 0 ; UP . BEInsns = 2 ; } </s>


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ReserveX18 ( TT . isOSDarwin ( ) ) , IsLittle ( LittleEndian ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS , CPU ) ) , TSInfo ( ) , TLInfo ( TM , * this ) , GISel ( ) { } </s>

This constructor initializes the data members to match that of the specified triple .


<s> bool AMDGPUAlwaysInline :: runOnModule ( Module & M ) { return alwaysInlineImpl ( M , GlobalOpt ) ; } </s>


<s> static bool mips_expand_vpc_loongson_pshufh ( struct expand_vec_perm_d * d ) { unsigned i , mask ; rtx rmask ; if ( ! ( TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS ) ) return false ; if ( d -> vmode != V4HImode ) return false ; if ( d -> testing_p ) return true ; for ( i = mask = 0 ; i < 4 ; i ++ ) mask |= ( d -> perm [ i ] & 3 ) << ( i * 2 ) ; rmask = force_reg ( SImode , GEN_INT ( mask ) ) ; if ( d -> one_vector_p ) emit_insn ( gen_loongson_pshufh ( d -> target , d -> op0 , rmask ) ) ; else { rtx t0 , t1 , x , merge , rmerge [ 4 ] ; t0 = gen_reg_rtx ( V4HImode ) ; t1 = gen_reg_rtx ( V4HImode ) ; emit_insn ( gen_loongson_pshufh ( t1 , d -> op1 , rmask ) ) ; emit_insn ( gen_loongson_pshufh ( t0 , d -> op0 , rmask ) ) ; for ( i = 0 ; i < 4 ; ++ i ) rmerge [ i ] = ( d -> perm [ i ] & 4 ? constm1_rtx : const0_rtx ) ; merge = gen_rtx_CONST_VECTOR ( V4HImode , gen_rtvec_v ( 4 , rmerge ) ) ; merge = force_reg ( V4HImode , merge ) ; x = gen_rtx_AND ( V4HImode , merge , t1 ) ; emit_insn ( gen_rtx_SET ( t1 , x ) ) ; x = gen_rtx_NOT ( V4HImode , merge ) ; x = gen_rtx_AND ( V4HImode , x , t0 ) ; emit_insn ( gen_rtx_SET ( t0 , x ) ) ; x = gen_rtx_IOR ( V4HImode , t0 , t1 ) ; emit_insn ( gen_rtx_SET ( d -> target , x ) ) ; } return true ; } </s>

Recognize patterns for the Loongson PSHUFH instruction .


<s> void xstormy16_expand_move ( machine_mode mode , rtx dest , rtx src ) { if ( MEM_P ( dest ) && ( GET_CODE ( XEXP ( dest , 0 ) ) == PRE_MODIFY ) ) { rtx pmv = XEXP ( dest , 0 ) ; rtx dest_reg = XEXP ( pmv , 0 ) ; rtx dest_mod = XEXP ( pmv , 1 ) ; rtx set = gen_rtx_SET ( Pmode , dest_reg , dest_mod ) ; rtx clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( BImode , CARRY_REGNUM ) ) ; dest = gen_rtx_MEM ( mode , dest_reg ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set , clobber ) ) ) ; } else if ( MEM_P ( src ) && ( GET_CODE ( XEXP ( src , 0 ) ) == PRE_MODIFY ) ) { rtx pmv = XEXP ( src , 0 ) ; rtx src_reg = XEXP ( pmv , 0 ) ; rtx src_mod = XEXP ( pmv , 1 ) ; rtx set = gen_rtx_SET ( Pmode , src_reg , src_mod ) ; rtx clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( BImode , CARRY_REGNUM ) ) ; src = gen_rtx_MEM ( mode , src_reg ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set , clobber ) ) ) ; } if ( ! reload_in_progress && ! reload_completed && MEM_P ( dest ) && ( ! CONST_INT_P ( XEXP ( dest , 0 ) ) || ! xstormy16_legitimate_address_p ( mode , XEXP ( dest , 0 ) , 0 ) ) && ! xstormy16_below100_operand ( dest , mode ) && ! REG_P ( src ) && GET_CODE ( src ) != SUBREG ) src = copy_to_mode_reg ( mode , src ) ; if ( reload_completed && mode != HImode && mode != QImode ) { xstormy16_split_move ( mode , dest , src ) ; return ; } emit_insn ( gen_rtx_SET ( VOIDmode , dest , src ) ) ; } </s>

Expander for the 'move ' patterns . Emit insns to copy a value of mode MODE from SRC to DEST .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < TargetPassConfig > ( ) ; AU . setPreservesAll ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool aarch64_sve_ld1ro_operand_p ( rtx op , scalar_mode elem_mode ) { return aarch64_sve_ld1rq_ld1ro_operand_p ( op , OImode , elem_mode ) ; } </s>

Return true if OP is a valid MEM operand for an SVE LD1RO instruction for accessing a vector where the element size is specified by ` elem_mode ` .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"R600 Emit Clause Markers Pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static void s390_code_end ( void ) { int i ; for ( i = 1 ; i < 16 ; i ++ ) { if ( indirect_branch_z10thunk_mask & ( 1 << i ) ) s390_output_indirect_thunk_function ( i , true ) ; if ( indirect_branch_prez10thunk_mask & ( 1 << i ) ) s390_output_indirect_thunk_function ( i , false ) ; } if ( TARGET_INDIRECT_BRANCH_TABLE ) { int o ; int i ; for ( o = 0 ; o < INDIRECT_BRANCH_NUM_OPTIONS ; o ++ ) { if ( indirect_branch_table_label_no [ o ] == 0 ) continue ; switch_to_section ( get_section ( indirect_branch_table_name [ o ] , 0 , NULL_TREE ) ) ; for ( i = 0 ; i < indirect_branch_table_label_no [ o ] ; i ++ ) { char label_start [ 32 ] ; ASM_GENERATE_INTERNAL_LABEL ( label_start , indirect_branch_table_label [ o ] , i ) ; fputs ( "\t.long\t" , asm_out_file ) ; assemble_name_raw ( asm_out_file , label_start ) ; fputs ( "-.\n" , asm_out_file ) ; } } } } </s>

Implement the asm.code_end target hook .


<s>
SDValue
MipsDAGToDAGISel
::
getGlobalBaseReg
(
)
{
MachineFunction
*
MF
=
BB
->
getParent
(
)
;
unsigned
GP
=
0
;
for
(
MachineRegisterInfo
::
livein_iterator
ii
=
MF
->
getRegInfo
(
)
.
livein_begin
(
)
,
ee
=
MF
->
getRegInfo
(
)
.
livein_end
(
)
;
ii
!=
ee
;
++
ii
)
if
(
ii
->
first
==
Mips
::
GP
)
{
GP
=
ii
->
second
;
break
;
}
assert
(
GP
&&
"GOT PTR not in liveins"
)
;
return
CurDAG
->
getCopyFromReg
(
CurDAG
->
getEntryNode
(
)
,
DebugLoc
::
getUnknownLoc
(
)
,
GP
,
MVT
::
i32
)
;
}
</s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

Mips
Mips
0
Mips::GP
"GOT PTR not in liveins"
MVT::i32


<s> bool cris_cc0_user_requires_cmp ( rtx_insn * insn ) { rtx_insn * cc0_user = NULL ; rtx body ; rtx set ; gcc_assert ( insn != NULL ) ; if ( ! TARGET_V32 ) return false ; cc0_user = next_cc0_user ( insn ) ; if ( cc0_user == NULL ) return false ; body = PATTERN ( cc0_user ) ; set = single_set ( cc0_user ) ; if ( JUMP_P ( cc0_user ) && GET_CODE ( body ) == SET && SET_DEST ( body ) == pc_rtx && GET_CODE ( SET_SRC ( body ) ) == IF_THEN_ELSE && XEXP ( XEXP ( SET_SRC ( body ) , 0 ) , 0 ) == cc0_rtx ) { return GET_CODE ( XEXP ( SET_SRC ( body ) , 0 ) ) == GT || GET_CODE ( XEXP ( SET_SRC ( body ) , 0 ) ) == LE ; } else if ( set ) { return GET_CODE ( SET_SRC ( body ) ) == GT || GET_CODE ( SET_SRC ( body ) ) == LE ; } gcc_unreachable ( ) ; } </s>

Whether next_cc0_user of insn is LE or GT or requires a real compare insn for other reasons .


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> const char * WebAssemblyAsmPrinter :: toString ( MVT VT ) const { return WebAssembly :: TypeToString ( VT ) ; } </s>

Convert to a decimal representation in a string .


<s> static rtx visium_function_arg ( cumulative_args_t pcum_v , machine_mode mode , const_tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { int size ; CUMULATIVE_ARGS * ca = get_cumulative_args ( pcum_v ) ; size = ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; if ( mode == VOIDmode ) return GEN_INT ( 0 ) ; if ( TARGET_FPU && ( ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && GET_MODE_SIZE ( mode ) <= UNITS_PER_HWFPVALUE ) || ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT && GET_MODE_SIZE ( mode ) <= UNITS_PER_HWFPVALUE * 2 ) ) ) { if ( ca -> frcount + size <= MAX_ARGS_IN_FP_REGISTERS ) return gen_rtx_REG ( mode , FP_ARG_FIRST + ca -> frcount ) ; else return NULL_RTX ; } if ( ca -> grcount + size <= MAX_ARGS_IN_GP_REGISTERS ) return gen_rtx_REG ( mode , ca -> grcount + GP_ARG_FIRST ) ; return NULL_RTX ; } </s>

Define how arguments are passed . A range of general registers and floating registers is available for passing arguments . When the class of registers which an argument would normally use is exhausted , that argument , is passed in the overflow region of the stack . No argument is split between registers and stack . Arguments of type float or _Complex float go in FP registers if FP hardware is available . If there is no FP hardware , arguments of type float go in general registers . All other arguments are passed in general registers .


<s> bool MipsOptimizePICCall :: runOnMachineFunction ( MachineFunction & F ) { if ( static_cast < const MipsSubtarget & > ( F . getSubtarget ( ) ) . inMips16Mode ( ) ) return false ; MachineDominatorTree * MDT = & getAnalysis < MachineDominatorTree > ( ) ; bool Changed = false ; SmallVector < MBBInfo , 8 > WorkList ( 1 , MBBInfo ( MDT -> getRootNode ( ) ) ) ; while ( ! WorkList . empty ( ) ) { MBBInfo & MBBI = WorkList . back ( ) ; if ( MBBI . isVisited ( ) ) { MBBI . postVisit ( ) ; WorkList . pop_back ( ) ; continue ; } MBBI . preVisit ( ScopedHT ) ; Changed |= visitNode ( MBBI ) ; const MachineDomTreeNode * Node = MBBI . getNode ( ) ; WorkList . append ( Node -> begin ( ) , Node -> end ( ) ) ; } return Changed ; } </s>


<s> bool AMDGPUAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( isHsaAbiVersion3 ( & getSTI ( ) ) ) { if ( IDVal == ".amdgcn_target" ) return ParseDirectiveAMDGCNTarget ( ) ; if ( IDVal == ".amdhsa_kernel" ) return ParseDirectiveAMDHSAKernel ( ) ; if ( IDVal == AMDGPU :: HSAMD :: V3 :: AssemblerDirectiveBegin ) return ParseDirectiveHSAMetadata ( ) ; } else { if ( IDVal == ".hsa_code_object_version" ) return ParseDirectiveHSACodeObjectVersion ( ) ; if ( IDVal == ".hsa_code_object_isa" ) return ParseDirectiveHSACodeObjectISA ( ) ; if ( IDVal == ".amd_kernel_code_t" ) return ParseDirectiveAMDKernelCodeT ( ) ; if ( IDVal == ".amdgpu_hsa_kernel" ) return ParseDirectiveAMDGPUHsaKernel ( ) ; if ( IDVal == ".amd_amdgpu_isa" ) return ParseDirectiveISAVersion ( ) ; if ( IDVal == AMDGPU :: HSAMD :: AssemblerDirectiveBegin ) return ParseDirectiveHSAMetadata ( ) ; } if ( IDVal == ".amdgpu_lds" ) return ParseDirectiveAMDGPULDS ( ) ; if ( IDVal == PALMD :: AssemblerDirectiveBegin ) return ParseDirectivePALMetadataBegin ( ) ; if ( IDVal == PALMD :: AssemblerDirective ) return ParseDirectivePALMetadata ( ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> std :: pair < SDValue , SDValue > SystemZSelectionDAGInfo :: EmitTargetCodeForStrcmp ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Src1 , SDValue Src2 , MachinePointerInfo Op1PtrInfo , MachinePointerInfo Op2PtrInfo ) const { SDVTList VTs = DAG . getVTList ( Src1 . getValueType ( ) , MVT :: Other , MVT :: Glue ) ; SDValue Unused = DAG . getNode ( SystemZISD :: STRCMP , DL , VTs , Chain , Src1 , Src2 , DAG . getConstant ( 0 , DL , MVT :: i32 ) ) ; Chain = Unused . getValue ( 1 ) ; SDValue Glue = Chain . getValue ( 2 ) ; return std :: make_pair ( addIPMSequence ( DL , Glue , DAG ) , Chain ) ; } </s>

Emit target-specific code that performs a strcmp , in cases where that is faster than a libcall .


<s>
unsigned
BPFInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
I
->
getOpcode
(
)
!=
BPF
::
JMP
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .

BPF
BPF
"code size not handled"
0
BPF::JMP


<s>
bool
MipsAsmParser
::
ParseDirective
(
AsmToken
DirectiveID
)
{
StringRef
IDVal
=
DirectiveID
.
getString
(
)
;
if
(
IDVal
==
".ent"
)
{
Parser
.
Lex
(
)
;
return
false
;
}
if
(
IDVal
==
".end"
)
{
Parser
.
Lex
(
)
;
return
false
;
}
if
(
IDVal
==
".frame"
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
false
;
}
if
(
IDVal
==
".set"
)
{
return
parseDirectiveSet
(
)
;
}
if
(
IDVal
==
".fmask"
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
false
;
}
if
(
IDVal
==
".mask"
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
false
;
}
if
(
IDVal
==
".gpword"
)
{
parseDirectiveGpWord
(
)
;
return
false
;
}
if
(
IDVal
==
".word"
)
{
parseDirectiveWord
(
4
,
DirectiveID
.
getLoc
(
)
)
;
return
false
;
}
if
(
IDVal
==
".option"
)
return
parseDirectiveOption
(
)
;
if
(
IDVal
==
".abicalls"
)
{
getTargetStreamer
(
)
.
emitDirectiveAbiCalls
(
)
;
if
(
Parser
.
getTok
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
Error
(
Parser
.
getTok
(
)
.
getLoc
(
)
,
"unexpected token in directive"
)
;
Parser
.
eatToEndOfStatement
(
)
;
}
return
false
;
}
return
true
;
}
</s>


<s> bool TOYRegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { return false ; } </s>

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot .


<s> static void nvptx_end_call_args ( void ) { cfun -> machine -> doing_call = false ; free_EXPR_LIST_list ( & cfun -> machine -> call_args ) ; } </s>

Implement the corresponding END_CALL_ARGS hook . Clear and free the information we recorded .


<s> void or1k_expand_epilogue ( void ) { HOST_WIDE_INT reg_offset , sp_offset ; rtx insn , cfa_restores = NULL ; sp_offset = cfun -> machine -> total_size ; if ( sp_offset == 0 ) return ; reg_offset = cfun -> machine -> local_vars_size + cfun -> machine -> args_size ; if ( sp_offset >= 32768 || cfun -> calls_alloca ) { if ( frame_pointer_needed ) { sp_offset -= reg_offset ; reg_offset = 0 ; insn = emit_insn ( gen_frame_addsi3 ( stack_pointer_rtx , hard_frame_pointer_rtx , GEN_INT ( - sp_offset ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , stack_pointer_rtx , sp_offset ) ) ; } else if ( sp_offset >= 3 * 32768 ) { rtx tmp = gen_rtx_REG ( Pmode , PE_TMP_REGNUM ) ; emit_move_insn ( tmp , GEN_INT ( reg_offset ) ) ; insn = emit_insn ( gen_frame_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , tmp ) ) ; sp_offset -= reg_offset ; reg_offset = 0 ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , stack_pointer_rtx , sp_offset ) ) ; } else { do { HOST_WIDE_INT this_offset = MIN ( reg_offset , 32764 ) ; reg_offset -= this_offset ; sp_offset -= this_offset ; insn = emit_insn ( gen_frame_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( this_offset ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , stack_pointer_rtx , sp_offset ) ) ; } while ( sp_offset >= 32768 ) ; } } for ( int regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( regno != HARD_FRAME_POINTER_REGNUM && regno != LR_REGNUM && callee_saved_regno_p ( regno ) ) { cfa_restores = or1k_restore_reg ( regno , reg_offset , cfa_restores ) ; reg_offset += UNITS_PER_WORD ; } if ( callee_saved_regno_p ( HARD_FRAME_POINTER_REGNUM ) ) { cfa_restores = or1k_restore_reg ( HARD_FRAME_POINTER_REGNUM , reg_offset , cfa_restores ) ; reg_offset += UNITS_PER_WORD ; } if ( callee_saved_regno_p ( LR_REGNUM ) ) { cfa_restores = or1k_restore_reg ( LR_REGNUM , reg_offset , cfa_restores ) ; reg_offset += UNITS_PER_WORD ; } gcc_assert ( reg_offset == sp_offset ) ; insn = emit_insn ( gen_frame_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( sp_offset ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = cfa_restores ; add_reg_note ( insn , REG_CFA_DEF_CFA , stack_pointer_rtx ) ; if ( crtl -> calls_eh_return ) emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , EH_RETURN_STACKADJ_RTX ) ) ; } </s>


<s> MachineInstr * SystemZInstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr & MI , ArrayRef < unsigned > Ops , MachineBasicBlock :: iterator InsertPt , MachineInstr & LoadMI , LiveIntervals * LIS ) const { return nullptr ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> static reg_class_t ix86_preferred_output_reload_class ( rtx x , reg_class_t regclass ) { machine_mode mode = GET_MODE ( x ) ; mode = GET_MODE ( x ) ; if ( SSE_FLOAT_MODE_P ( mode ) && TARGET_SSE_MATH ) return MAYBE_SSE_CLASS_P ( regclass ) ? ALL_SSE_REGS : NO_REGS ; if ( IS_STACK_MODE ( mode ) ) { if ( regclass == FP_TOP_SSE_REGS ) return FP_TOP_REG ; else if ( regclass == FP_SECOND_SSE_REGS ) return FP_SECOND_REG ; else return FLOAT_CLASS_P ( regclass ) ? regclass : NO_REGS ; } return regclass ; } </s>

Discourage putting floating-point values in SSE registers unless SSE math is being used , and likewise for the 387 registers .


<s> void load_got_register ( void ) { if ( ! got_register_rtx ) got_register_rtx = gen_rtx_REG ( Pmode , GLOBAL_OFFSET_TABLE_REGNUM ) ; if ( TARGET_VXWORKS_RTP ) emit_insn ( gen_vxworks_load_got ( ) ) ; else { if ( ! got_helper_rtx ) { char name [ 32 ] ; get_pc_thunk_name ( name , GLOBAL_OFFSET_TABLE_REGNUM ) ; got_helper_rtx = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( name ) ) ; } emit_insn ( gen_load_pcrel_sym ( got_register_rtx , sparc_got ( ) , got_helper_rtx ) ) ; } } </s>


Change register usage conditional on target flags .


<s> bool isLabel ( ) const { if ( ! isImm ( ) ) return false ; if ( dyn_cast < MCSymbolRefExpr > ( Imm . Val ) ) { return true ; } else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Imm . Val ) ) { int64_t Val = CE -> getValue ( ) ; int64_t Min = - ( scale * ( 1LL << ( field_width - 1 ) ) ) ; int64_t Max = scale * ( ( 1LL << ( field_width - 1 ) ) - 1 ) ; return ( Val % scale ) == 0 && Val >= Min && Val <= Max ; } return false ; } </s>

Returns true if the MachineInstr represents a label .


<s> const char * VETargetLowering :: getTargetNodeName ( unsigned Opcode ) const { case VEISD :: NAME : \ return "VEISD::" # NAME ; switch ( ( VEISD :: NodeType ) Opcode ) { case VEISD :: FIRST_NUMBER : break ; TARGET_NODE_CASE ( CALL ) TARGET_NODE_CASE ( EH_SJLJ_LONGJMP ) TARGET_NODE_CASE ( EH_SJLJ_SETJMP ) TARGET_NODE_CASE ( EH_SJLJ_SETUP_DISPATCH ) TARGET_NODE_CASE ( GETFUNPLT ) TARGET_NODE_CASE ( GETSTACKTOP ) TARGET_NODE_CASE ( GETTLSADDR ) TARGET_NODE_CASE ( GLOBAL_BASE_REG ) TARGET_NODE_CASE ( Hi ) TARGET_NODE_CASE ( Lo ) TARGET_NODE_CASE ( MEMBARRIER ) TARGET_NODE_CASE ( RET_FLAG ) TARGET_NODE_CASE ( TS1AM ) TARGET_NODE_CASE ( VEC_BROADCAST ) TARGET_NODE_CASE ( REPL_I32 ) TARGET_NODE_CASE ( REPL_F32 ) } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

VE VE VEISD::NAME "VEISD::" VEISD::NodeType VEISD::FIRST_NUMBER VE


<s> static poly_int64 vax_return_pops_args ( tree fundecl ATTRIBUTE_UNUSED , tree funtype ATTRIBUTE_UNUSED , poly_int64 size ) { return size > 255 * 4 ? 0 : ( HOST_WIDE_INT ) size ; } </s>

Value is the number of bytes of arguments automatically popped when returning from a subroutine call . FUNDECL is the declaration node of the function ( as a tree ) , FUNTYPE is the data type of the function ( as a tree ) , or for a library call it is an identifier node for the subroutine name . SIZE is the number of bytes of arguments passed on the stack . On the VAX , the RET insn pops a maximum of 255 args for any function .


<s>
static
void
gr5_avoid_hazard
(
rtx_insn
*
insn
,
unsigned
int
*
last_reg
,
bool
*
last_insn_call
)
{
unsigned
int
dest_reg
=
0
;
rtx
set
;
switch
(
GET_CODE
(
insn
)
)
{
case
CALL_INSN
:
*
last_reg
=
0
;
*
last_insn_call
=
true
;
return
;
case
JUMP_INSN
:
if
(
!
empty_asm_p
(
insn
)
)
{
*
last_reg
=
0
;
*
last_insn_call
=
false
;
}
return
;
case
INSN
:
if
(
empty_asm_p
(
insn
)
)
return
;
break
;
default
:
return
;
}
set
=
single_set_and_flags
(
insn
)
;
if
(
set
!=
NULL_RTX
)
{
rtx
dest
=
SET_DEST
(
set
)
;
const
bool
double_p
=
GET_MODE_SIZE
(
GET_MODE
(
dest
)
)
>
UNITS_PER_WORD
;
rtx
memrtx
=
;
if
(
GET_CODE
(
SET_SRC
(
set
)
)
==
MEM
)
{
memrtx
=
XEXP
(
SET_SRC
(
set
)
,
0
)
;
if
(
GET_CODE
(
dest
)
==
STRICT_LOW_PART
)
dest
=
XEXP
(
dest
,
0
)
;
if
(
REG_P
(
dest
)
)
dest_reg
=
REGNO
(
dest
)
;
if
(
double_p
)
{
unsigned
int
base_reg
;
if
(
GET_CODE
(
memrtx
)
==
PLUS
)
base_reg
=
REGNO
(
XEXP
(
memrtx
,
0
)
)
;
else
base_reg
=
REGNO
(
memrtx
)
;
if
(
dest_reg
!=
base_reg
)
dest_reg
++
;
}
}
else
if
(
GET_CODE
(
dest
)
==
MEM
)
memrtx
=
XEXP
(
dest
,
0
)
;
else
if
(
GET_MODE_CLASS
(
GET_MODE
(
dest
)
)
!=
MODE_CC
)
{
if
(
GET_CODE
(
dest
)
==
STRICT_LOW_PART
||
GET_CODE
(
dest
)
==
ZERO_EXTRACT
)
dest
=
XEXP
(
dest
,
0
)
;
dest_reg
=
REGNO
(
dest
)
;
if
(
GET_CODE
(
SET_SRC
(
set
)
)
==
REG
)
{
unsigned
int
srcreg
=
REGNO
(
SET_SRC
(
set
)
)
;
if
(
srcreg
==
dest_reg
)
return
;
if
(
double_p
&&
dest_reg
!=
srcreg
+
1
)
dest_reg
++
;
}
}
if
(
*
last_insn_call
)
dest_reg
=
0
;
if
(
*
last_reg
!=
0
&&
memrtx
!=
NULL_RTX
)
{
unsigned
int
reg
=
0
;
if
(
GET_CODE
(
memrtx
)
==
PLUS
)
reg
=
REGNO
(
XEXP
(
memrtx
,
0
)
)
;
else
if
(
TARGET_MCM
||
(
double_p
&&
REGNO
(
memrtx
)
==
dest_reg
)
)
reg
=
REGNO
(
memrtx
)
;
if
(
reg
==
*
last_reg
)
{
if
(
dump_file
)
fprintf
(
dump_file
,
"inserting nop before insn %d\n"
,
INSN_UID
(
insn
)
)
;
emit_insn_after
(
gen_hazard_nop
(
)
,
prev_active_insn
(
insn
)
)
;
emit_insn_after
(
gen_blockage
(
)
,
insn
)
;
}
}
*
last_reg
=
dest_reg
;
}
*
last_insn_call
=
false
;
}
</s>

Insert a NOP immediately before INSN wherever there is a pipeline hazard . LAST_REG records the register set in the last insn and LAST_INSN_CALL records whether the last insn was a call insn .


<s> static unsigned int rs6000_xcoff_section_type_flags ( tree decl , const char * name , int reloc ) { unsigned int align ; unsigned int flags = default_section_type_flags ( decl , name , reloc ) ; if ( ( flags & SECTION_CODE ) != 0 || ! decl || ! DECL_P ( decl ) ) align = MIN_UNITS_PER_WORD ; else align = MAX ( ( DECL_ALIGN ( decl ) / BITS_PER_UNIT ) , int_size_in_bytes ( TREE_TYPE ( decl ) ) > MIN_UNITS_PER_WORD ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD ) ; return flags | ( exact_log2 ( align ) & SECTION_ENTSIZE ) ; } </s>

Section attributes . AIX is always PIC .


<s> void X86AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { X86MCInstLower MCInstLowering ( Mang , * MF , * this ) ; switch ( MI -> getOpcode ( ) ) { case TargetOpcode :: DBG_VALUE : if ( isVerbose ( ) && OutStreamer . hasRawTextSupport ( ) ) { std :: string TmpStr ; raw_string_ostream OS ( TmpStr ) ; PrintDebugValueComment ( MI , OS ) ; OutStreamer . EmitRawText ( StringRef ( OS . str ( ) ) ) ; } return ; case X86 :: Int_MemBarrier : if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( StringRef ( "\t#MEMBARRIER" ) ) ; return ; case X86 :: TAILJMPr : case X86 :: TAILJMPd : case X86 :: TAILJMPd64 : OutStreamer . AddComment ( "TAILCALL" ) ; break ; case X86 :: MOVPC32r : { MCInst TmpInst ; MCSymbol * PICBase = MCInstLowering . GetPICBaseSymbol ( ) ; TmpInst . setOpcode ( X86 :: CALLpcrel32 ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( PICBase , OutContext ) ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; OutStreamer . EmitLabel ( PICBase ) ; TmpInst . setOpcode ( X86 :: POP32r ) ; TmpInst . getOperand ( 0 ) = MCOperand :: CreateReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; return ; } case X86 :: ADD32ri : { if ( MI -> getOperand ( 2 ) . getTargetFlags ( ) != X86II :: MO_GOT_ABSOLUTE_ADDRESS ) break ; MCSymbol * DotSym = OutContext . CreateTempSymbol ( ) ; OutStreamer . EmitLabel ( DotSym ) ; MCSymbol * OpSym = MCInstLowering . GetSymbolFromOperand ( MI -> getOperand ( 2 ) ) ; const MCExpr * DotExpr = MCSymbolRefExpr :: Create ( DotSym , OutContext ) ; const MCExpr * PICBase = MCSymbolRefExpr :: Create ( MCInstLowering . GetPICBaseSymbol ( ) , OutContext ) ; DotExpr = MCBinaryExpr :: CreateSub ( DotExpr , PICBase , OutContext ) ; DotExpr = MCBinaryExpr :: CreateAdd ( MCSymbolRefExpr :: Create ( OpSym , OutContext ) , DotExpr , OutContext ) ; MCInst TmpInst ; TmpInst . setOpcode ( X86 :: ADD32ri ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( 1 ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( DotExpr ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; return ; } } MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; OutStreamer . EmitInstruction ( TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool SystemZInstrInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; SystemZMachineFunctionInfo * MFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; unsigned CalleeFrameSize = 0 ; unsigned LowReg = 0 , HighReg = 0 , StartOffset = - 1U , EndOffset = 0 ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! SystemZ :: FP64RegClass . contains ( Reg ) ) { unsigned Offset = RegSpillOffsets [ Reg ] ; CalleeFrameSize += 8 ; if ( StartOffset > Offset ) { LowReg = Reg ; StartOffset = Offset ; } if ( EndOffset < Offset ) { HighReg = Reg ; EndOffset = RegSpillOffsets [ Reg ] ; } } } MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ; MFI -> setLowReg ( LowReg ) ; MFI -> setHighReg ( HighReg ) ; if ( StartOffset ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( ( LowReg == HighReg ? SystemZ :: MOV64mr : SystemZ :: MOV64mrm ) ) ) ; MIB . addReg ( SystemZ :: R15D ) . addImm ( StartOffset ) ; if ( LowReg == HighReg ) MIB . addReg ( 0 ) ; MIB . addReg ( LowReg , RegState :: Kill ) ; if ( LowReg != HighReg ) MIB . addReg ( HighReg , RegState :: Kill ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; if ( Reg != LowReg && Reg != HighReg ) MIB . addReg ( Reg , RegState :: ImplicitKill ) ; } } for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( SystemZ :: FP64RegClass . contains ( Reg ) ) { MBB . addLiveIn ( Reg ) ; storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i ] . getFrameIdx ( ) , & SystemZ :: FP64RegClass , & RI ) ; } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU R600 AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override { TargetTransformInfo :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void X86TTI :: getUnrollingPreferences ( Loop * L , UnrollingPreferences & UP ) const { if ( ! UsePartialUnrolling ) return ; unsigned MaxOps ; if ( PartialUnrollingThreshold . getNumOccurrences ( ) > 0 ) { MaxOps = PartialUnrollingThreshold ; } else if ( ST -> isAtom ( ) ) { MaxOps = 10 ; } else if ( ST -> hasFSGSBase ( ) && ST -> hasXOP ( ) ) { MaxOps = 40 ; } else if ( ST -> hasFMA4 ( ) ) { return ; } else if ( ST -> hasAVX ( ) || ST -> hasSSE42 ( ) ) { MaxOps = 28 ; } else if ( ST -> hasSSSE3 ( ) ) { MaxOps = 18 ; } else { return ; } for ( Loop :: block_iterator I = L -> block_begin ( ) , E = L -> block_end ( ) ; I != E ; ++ I ) { BasicBlock * BB = * I ; for ( BasicBlock :: iterator J = BB -> begin ( ) , JE = BB -> end ( ) ; J != JE ; ++ J ) if ( isa < CallInst > ( J ) || isa < InvokeInst > ( J ) ) { ImmutableCallSite CS ( J ) ; if ( const Function * F = CS . getCalledFunction ( ) ) { if ( ! isLoweredToCall ( F ) ) continue ; } return ; } } UP . Partial = UP . Runtime = true ; UP . PartialThreshold = UP . PartialOptSizeThreshold = MaxOps ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> HOST_WIDE_INT riscv_initial_elimination_offset ( int from , int to ) { HOST_WIDE_INT src , dest ; riscv_compute_frame_info ( ) ; if ( to == HARD_FRAME_POINTER_REGNUM ) dest = cfun -> machine -> frame . hard_frame_pointer_offset ; else if ( to == STACK_POINTER_REGNUM ) dest = 0 ; else gcc_unreachable ( ) ; if ( from == FRAME_POINTER_REGNUM ) src = cfun -> machine -> frame . frame_pointer_offset ; else if ( from == ARG_POINTER_REGNUM ) src = cfun -> machine -> frame . arg_pointer_offset ; else gcc_unreachable ( ) ; return src - dest ; } </s>

Implement INITIAL_ELIMINATION_OFFSET . FROM is either the frame pointer or argument pointer . TO is either the stack pointer or hard frame pointer .


<s> void timode_scalar_chain :: fix_debug_reg_uses ( rtx reg ) { if ( ! flag_var_tracking ) return ; df_ref ref , next ; for ( ref = DF_REG_USE_CHAIN ( REGNO ( reg ) ) ; ref ; ref = next ) { rtx_insn * insn = DF_REF_INSN ( ref ) ; next = DF_REF_NEXT_REG ( ref ) ; while ( next && DF_REF_INSN ( next ) == insn ) next = DF_REF_NEXT_REG ( next ) ; if ( DEBUG_INSN_P ( insn ) ) { bool changed = false ; for ( ; ref != next ; ref = DF_REF_NEXT_REG ( ref ) ) { rtx * loc = DF_REF_LOC ( ref ) ; if ( REG_P ( * loc ) && GET_MODE ( * loc ) == V1TImode ) { * loc = gen_rtx_SUBREG ( TImode , * loc , 0 ) ; changed = true ; } } if ( changed ) df_insn_rescan ( insn ) ; } } } </s>

Fix uses of converted REG in debug insns .


<s> void NVPTXTargetMachine :: registerPassBuilderCallbacks ( PassBuilder & PB ) { PB . registerPipelineParsingCallback ( [ ] ( StringRef PassName , FunctionPassManager & PM , ArrayRef < PassBuilder :: PipelineElement > ) { if ( PassName == "nvvm-reflect" ) { PM . addPass ( NVVMReflectPass ( ) ) ; return true ; } if ( PassName == "nvvm-intr-range" ) { PM . addPass ( NVVMIntrRangePass ( ) ) ; return true ; } return false ; } ) ; PB . registerPipelineStartEPCallback ( [ this ] ( ModulePassManager & PM , PassBuilder :: OptimizationLevel Level ) { FunctionPassManager FPM ; FPM . addPass ( NVVMReflectPass ( Subtarget . getSmVersion ( ) ) ) ; PM . addPass ( createModuleToFunctionPassAdaptor ( std :: move ( FPM ) ) ) ; } ) ; } </s>

Invoke the PassBuilder callback registration .

NVPTX NVPTX "nvvm-reflect" "nvvm-intr-range"


<s> SDNode * PPCDAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * TM . getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc dl ; if ( PPCLowering -> getPointerTy ( ) == MVT :: i32 ) { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: GPRC_NOR0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: G8RC_NOX0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR8 ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR8 ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , PPCLowering -> getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


"Code generation for MIPS-I is not implemented"

"Code generation for MIPS-V is not implemented"

"MSA requires a 64-bit FPU register file (FR=1 mode). "

"-mattr=+nooddspreg requires the O32 ABI."

"FPXX is not permitted for the N32/N64 ABI's."

"position-independent code requires '-mabicalls'"

"warning: cannot use small-data accesses for '-mabicalls'"

This constructor initializes the data members to match that of the specified triple .


<s> unsigned getPrefFunctionAlignment ( ) const { return PrefFunctionAlignment ; } </s>

Return the preferred function alignment .


<s> static int arm_get_strip_length ( char c ) { switch ( c ) { ARM_NAME_ENCODING_LENGTHS default : return 0 ; } } </s>

Return the length of a function name prefix that starts with the character ' c ' .


<s> bool toc_relative_expr_p ( const_rtx op , bool strict ) { if ( ! TARGET_TOC ) return false ; if ( TARGET_CMODEL != CMODEL_SMALL ) { if ( GET_CODE ( op ) == LO_SUM && REG_P ( XEXP ( op , 0 ) ) && INT_REG_OK_FOR_BASE_P ( XEXP ( op , 0 ) , strict ) ) op = XEXP ( op , 1 ) ; else if ( strict ) return false ; } tocrel_base = op ; tocrel_offset = const0_rtx ; if ( GET_CODE ( op ) == PLUS && add_cint_operand ( XEXP ( op , 1 ) , GET_MODE ( op ) ) ) { tocrel_base = XEXP ( op , 0 ) ; tocrel_offset = XEXP ( op , 1 ) ; } return ( GET_CODE ( tocrel_base ) == UNSPEC && XINT ( tocrel_base , 1 ) == UNSPEC_TOCREL ) ; } </s>

Return true if OP is a toc pointer relative address ( the output of create_TOC_reference ) . If STRICT , do not match high part or non-split -mcmodel=large/medium toc pointer relative addresses .


<s> void AMDGPUPassConfig :: addCodeGenPrepare ( ) { if ( TM -> getTargetTriple ( ) . getArch ( ) == Triple :: amdgcn ) addPass ( createAMDGPUAnnotateKernelFeaturesPass ( ) ) ; if ( TM -> getTargetTriple ( ) . getArch ( ) == Triple :: amdgcn && EnableLowerKernelArguments ) addPass ( createAMDGPULowerKernelArgumentsPass ( ) ) ; addPass ( & AMDGPUPerfHintAnalysisID ) ; TargetPassConfig :: addCodeGenPrepare ( ) ; if ( EnableLoadStoreVectorizer ) addPass ( createLoadStoreVectorizerPass ( ) ) ; } </s>

Add pass to prepare the LLVM IR for code generation .


<s>
MCSymbol
*
mprocMCInstLower
::
GetExternalSymbolSymbol
(
const
MachineOperand
&
MO
)
const
{
switch
(
MO
.
getTargetFlags
(
)
)
{
default
:
llvm_unreachable
(
"Unknown target flag on GV operand"
)
;
case
0
:
break
;
}
return
Printer
.
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
;
}
</s>

Return the MCSymbol for the specified ExternalSymbol .

mproc
mproc
"Unknown target flag on GV operand"
0


AMDGPU SI SI SI SI AMDGPU::VGPR_32RegClass


<s> uint64_t R600MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixup , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) { if ( HAS_NATIVE_OPERANDS ( MCII . get ( MI . getOpcode ( ) ) . TSFlags ) ) return MRI . getEncodingValue ( MO . getReg ( ) ) ; return getHWReg ( MO . getReg ( ) ) ; } assert ( MO . isImm ( ) ) ; return MO . getImm ( ) ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> void AArch64TargetStreamer :: emitInst ( uint32_t Inst ) { char Buffer [ 4 ] ; for ( unsigned I = 0 ; I < 4 ; ++ I ) { Buffer [ I ] = uint8_t ( Inst ) ; Inst >>= 8 ; } getStreamer ( ) . emitBytes ( StringRef ( Buffer , 4 ) ) ; } </s>

Callback used to implement the .inst directive .


<s> void MipsTargetELFStreamer :: finish ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; const MCObjectFileInfo & OFI = * MCA . getContext ( ) . getObjectFileInfo ( ) ; MCSection & TextSection = * OFI . getTextSection ( ) ; MCA . registerSection ( TextSection ) ; MCSection & DataSection = * OFI . getDataSection ( ) ; MCA . registerSection ( DataSection ) ; MCSection & BSSSection = * OFI . getBSSSection ( ) ; MCA . registerSection ( BSSSection ) ; TextSection . setAlignment ( Align ( std :: max ( 16u , TextSection . getAlignment ( ) ) ) ) ; DataSection . setAlignment ( Align ( std :: max ( 16u , DataSection . getAlignment ( ) ) ) ) ; BSSSection . setAlignment ( Align ( std :: max ( 16u , BSSSection . getAlignment ( ) ) ) ) ; if ( RoundSectionSizes ) { MCStreamer & OS = getStreamer ( ) ; for ( MCSection & S : MCA ) { MCSectionELF & Section = static_cast < MCSectionELF & > ( S ) ; unsigned Alignment = Section . getAlignment ( ) ; if ( Alignment ) { OS . SwitchSection ( & Section ) ; if ( Section . UseCodeAlign ( ) ) OS . emitCodeAlignment ( Alignment , Alignment ) ; else OS . emitValueToAlignment ( Alignment , 0 , 1 , Alignment ) ; } } } const FeatureBitset & Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI_O32 ; else if ( getABI ( ) . IsN32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI2 ; if ( Features [ Mips :: FeatureGP64Bit ] ) { if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_32BITMODE ; } else if ( Features [ Mips :: FeatureMips64r2 ] || Features [ Mips :: FeatureMips64 ] ) EFlags |= ELF :: EF_MIPS_32BITMODE ; if ( ! Features [ Mips :: FeatureNoABICalls ] ) EFlags |= ELF :: EF_MIPS_CPIC ; if ( Pic ) EFlags |= ELF :: EF_MIPS_PIC | ELF :: EF_MIPS_CPIC ; if ( getABI ( ) . IsCheriPureCap ( ) ) EFlags |= ELF :: EF_MIPS_ABI_CHERIABI ; MCA . setELFHeaderEFlags ( EFlags ) ; MipsELFStreamer & MEF = static_cast < MipsELFStreamer & > ( Streamer ) ; MEF . EmitMipsOptionRecords ( ) ; emitMipsAbiFlags ( ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> static rtx gen_push ( rtx arg ) { struct machine_function * m = cfun -> machine ; if ( m -> fs . cfa_reg == stack_pointer_rtx ) m -> fs . cfa_offset += UNITS_PER_WORD ; m -> fs . sp_offset += UNITS_PER_WORD ; if ( REG_P ( arg ) && GET_MODE ( arg ) != word_mode ) arg = gen_rtx_REG ( word_mode , REGNO ( arg ) ) ; return gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( word_mode , gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ) , arg ) ; } </s>

Code to generate prologue and epilogue sequences


<s>
static
void
begin_decl_field
(
void
)
{
if
(
decl_offset
==
decl_chunk_size
)
fprintf
(
asm_out_file
,
" = { "
)
;
else
fprintf
(
asm_out_file
,
", "
)
;
}
</s>

Write the necessary separator string to begin a new initializer value .


<s> const TargetIntrinsicInfo * getIntrinsicInfo ( ) const { return & IntrinsicInfo ; } </s>

If intrinsic information is available , return it . If not , return null .


"Unable to get the legal offset for nil instruction."

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s>
CCAssignFn
*
AMDGPUCallLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
{
switch
(
CC
)
{
case
CallingConv
::
AMDGPU_KERNEL
:
case
CallingConv
::
SPIR_KERNEL
:
llvm_unreachable
(
"kernels should not be handled here"
)
;
case
CallingConv
::
AMDGPU_VS
:
case
CallingConv
::
AMDGPU_GS
:
case
CallingConv
::
AMDGPU_PS
:
case
CallingConv
::
AMDGPU_CS
:
case
CallingConv
::
AMDGPU_HS
:
case
CallingConv
::
AMDGPU_ES
:
case
CallingConv
::
AMDGPU_LS
:
return
CC_AMDGPU
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
case
CallingConv
::
Cold
:
return
CC_AMDGPU_Func
;
default
:
report_fatal_error
(
"Unsupported calling convention."
)
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .

AMDGPU
AMDGPU
AMDGPU
"kernels should not be handled here"
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
"Unsupported calling convention."


<s> static bool aarch64_emit_cfi_for_reg_p ( unsigned int regno ) { return ( GP_REGNUM_P ( regno ) || ! default_function_abi . clobbers_full_reg_p ( regno ) ) ; } </s>

Return true if we should emit CFI for register REGNO .


"rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n"

A C expression returning the cost of moving data from a register of class CLASS1 to one of CLASS2 .


<s>
bool
ARMAsmParser
::
ParseInstruction
(
StringRef
Name
,
SMLoc
NameLoc
,
SmallVectorImpl
<
MCParsedAsmOperand
*
>
&
Operands
)
{
size_t
Start
=
0
,
Next
=
Name
.
find
(
'.'
)
;
StringRef
Head
=
Name
.
slice
(
Start
,
Next
)
;
unsigned
PredicationCode
;
unsigned
ProcessorIMod
;
bool
CarrySetting
;
Head
=
SplitMnemonic
(
Head
,
PredicationCode
,
CarrySetting
,
ProcessorIMod
)
;
Operands
.
push_back
(
ARMOperand
::
CreateToken
(
Head
,
NameLoc
)
)
;
bool
CanAcceptCarrySet
,
CanAcceptPredicationCode
;
GetMnemonicAcceptInfo
(
Head
,
CanAcceptCarrySet
,
CanAcceptPredicationCode
)
;
if
(
CanAcceptCarrySet
)
{
Operands
.
push_back
(
ARMOperand
::
CreateCCOut
(
CarrySetting
ARM
::
CPSR
:
0
,
NameLoc
)
)
;
}
else
{
}
if
(
CanAcceptPredicationCode
)
{
Operands
.
push_back
(
ARMOperand
::
CreateCondCode
(
ARMCC
::
CondCodes
(
PredicationCode
)
,
NameLoc
)
)
;
}
else
{
}
if
(
ProcessorIMod
)
{
Operands
.
push_back
(
ARMOperand
::
CreateImm
(
MCConstantExpr
::
Create
(
ProcessorIMod
,
getContext
(
)
)
,
NameLoc
,
NameLoc
)
)
;
}
else
{
}
while
(
Next
!=
StringRef
::
npos
)
{
Start
=
Next
;
Next
=
Name
.
find
(
'.'
,
Start
+
1
)
;
StringRef
ExtraToken
=
Name
.
slice
(
Start
,
Next
)
;
Operands
.
push_back
(
ARMOperand
::
CreateToken
(
ExtraToken
,
NameLoc
)
)
;
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
ParseOperand
(
Operands
,
Head
)
)
{
Parser
.
EatToEndOfStatement
(
)
;
return
true
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
ParseOperand
(
Operands
,
Head
)
)
{
Parser
.
EatToEndOfStatement
(
)
;
return
true
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
Parser
.
EatToEndOfStatement
(
)
;
return
TokError
(
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

ARM
ARM
0
ARM
ARM
ARM::CPSR
0
ARM
ARMCC::CondCodes
ARM
1
ARM
"unexpected token in argument list"


<s> SMLoc getEndLoc ( ) const { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> static bool thumb_force_lr_save ( void ) { return ! cfun -> machine -> lr_save_eliminated && ( ! crtl -> is_leaf || thumb_far_jump_used_p ( ) || df_regs_ever_live_p ( LR_REGNUM ) ) ; } </s>

Return true if the current function needs to save/restore LR .


"Instr doesn't have FrameIndex operand!"


<s>
const
MCPhysReg
*
AArch64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetDarwin
(
)
)
return
getDarwinCalleeSavedRegs
(
MF
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
CFGuard_Check
)
return
CSR_Win_AArch64_CFGuard_Check_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetWindows
(
)
)
return
CSR_Win_AArch64_AAPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_AArch64_NoRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_AArch64_AllRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_VectorCall
)
return
CSR_AArch64_AAVPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_SVE_VectorCall
)
return
CSR_AArch64_SVE_AAPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
CXX_FAST_TLS
)
return
MF
->
getInfo
<
AArch64FunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_AArch64_CXX_TLS_Darwin_PE_SaveList
:
CSR_AArch64_CXX_TLS_Darwin_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
.
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_AArch64_AAPCS_SwiftError_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
PreserveMost
)
return
CSR_AArch64_RT_MostRegs_SaveList
;
return
CSR_AArch64_AAPCS_SaveList
;
}
</s>


<s> static void pa_init_libfuncs ( void ) { if ( HPUX_LONG_DOUBLE_LIBRARY ) { set_optab_libfunc ( add_optab , TFmode , "_U_Qfadd" ) ; set_optab_libfunc ( sub_optab , TFmode , "_U_Qfsub" ) ; set_optab_libfunc ( smul_optab , TFmode , "_U_Qfmpy" ) ; set_optab_libfunc ( sdiv_optab , TFmode , "_U_Qfdiv" ) ; set_optab_libfunc ( smin_optab , TFmode , "_U_Qmin" ) ; set_optab_libfunc ( smax_optab , TFmode , "_U_Qfmax" ) ; set_optab_libfunc ( sqrt_optab , TFmode , "_U_Qfsqrt" ) ; set_optab_libfunc ( abs_optab , TFmode , "_U_Qfabs" ) ; set_optab_libfunc ( neg_optab , TFmode , "_U_Qfneg" ) ; set_optab_libfunc ( eq_optab , TFmode , "_U_Qfeq" ) ; set_optab_libfunc ( ne_optab , TFmode , "_U_Qfne" ) ; set_optab_libfunc ( gt_optab , TFmode , "_U_Qfgt" ) ; set_optab_libfunc ( ge_optab , TFmode , "_U_Qfge" ) ; set_optab_libfunc ( lt_optab , TFmode , "_U_Qflt" ) ; set_optab_libfunc ( le_optab , TFmode , "_U_Qfle" ) ; set_optab_libfunc ( unord_optab , TFmode , "_U_Qfunord" ) ; set_conv_libfunc ( sext_optab , TFmode , SFmode , "_U_Qfcnvff_sgl_to_quad" ) ; set_conv_libfunc ( sext_optab , TFmode , DFmode , "_U_Qfcnvff_dbl_to_quad" ) ; set_conv_libfunc ( trunc_optab , SFmode , TFmode , "_U_Qfcnvff_quad_to_sgl" ) ; set_conv_libfunc ( trunc_optab , DFmode , TFmode , "_U_Qfcnvff_quad_to_dbl" ) ; set_conv_libfunc ( sfix_optab , SImode , TFmode , TARGET_64BIT ? "__U_Qfcnvfxt_quad_to_sgl" : "_U_Qfcnvfxt_quad_to_sgl" ) ; set_conv_libfunc ( sfix_optab , DImode , TFmode , "_U_Qfcnvfxt_quad_to_dbl" ) ; set_conv_libfunc ( ufix_optab , SImode , TFmode , "_U_Qfcnvfxt_quad_to_usgl" ) ; set_conv_libfunc ( ufix_optab , DImode , TFmode , "_U_Qfcnvfxt_quad_to_udbl" ) ; set_conv_libfunc ( sfloat_optab , TFmode , SImode , "_U_Qfcnvxf_sgl_to_quad" ) ; set_conv_libfunc ( sfloat_optab , TFmode , DImode , "_U_Qfcnvxf_dbl_to_quad" ) ; set_conv_libfunc ( ufloat_optab , TFmode , SImode , "_U_Qfcnvxf_usgl_to_quad" ) ; set_conv_libfunc ( ufloat_optab , TFmode , DImode , "_U_Qfcnvxf_udbl_to_quad" ) ; } if ( TARGET_SYNC_LIBCALL ) init_sync_libfuncs ( 8 ) ; } </s>

Initialize optabs to point to emulation routines .


<s> Register RISCVTargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) const { return RISCV :: X11 ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .


"Pseudo flag setting opcodes only exist in Selection DAG"

"Non-flag-setting Thumb1 mov is v6-only"

"Unsupported register in Thumb1 push/pop"

Perform target-specific instruction verification .


<s> static int arm_comp_type_attributes ( tree type1 , tree type2 ) { int l1 , l2 , s1 , s2 ; if ( TREE_CODE ( type1 ) != FUNCTION_TYPE ) return 1 ; l1 = lookup_attribute ( "long_call" , TYPE_ATTRIBUTES ( type1 ) ) != NULL ; l2 = lookup_attribute ( "long_call" , TYPE_ATTRIBUTES ( type2 ) ) != NULL ; s1 = lookup_attribute ( "short_call" , TYPE_ATTRIBUTES ( type1 ) ) != NULL ; s2 = lookup_attribute ( "short_call" , TYPE_ATTRIBUTES ( type2 ) ) != NULL ; if ( l1 | l2 | s1 | s2 ) { if ( ( l1 != l2 ) || ( s1 != s2 ) ) return 0 ; if ( ( l1 & s2 ) || ( l2 & s1 ) ) return 0 ; } l1 = lookup_attribute ( "isr" , TYPE_ATTRIBUTES ( type1 ) ) != NULL ; if ( ! l1 ) l1 = lookup_attribute ( "interrupt" , TYPE_ATTRIBUTES ( type1 ) ) != NULL ; l2 = lookup_attribute ( "isr" , TYPE_ATTRIBUTES ( type2 ) ) != NULL ; if ( ! l2 ) l1 = lookup_attribute ( "interrupt" , TYPE_ATTRIBUTES ( type2 ) ) != NULL ; if ( l1 != l2 ) return 0 ; return 1 ; } </s>

Return 0 if the attributes for two types are incompatible , 1 if they are compatible , and 2 if they are nearly compatible ( which causes a warning to be generated ) .


<s>
SDValue
BPFTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
DL
,
SelectionDAG
&
DAG
)
const
{
unsigned
Opc
=
BPFISD
::
RET_FLAG
;
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
MF
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
if
(
MF
.
getFunction
(
)
->
getReturnType
(
)
->
isAggregateType
(
)
)
{
fail
(
DL
,
DAG
,
"only integer returns supported"
)
;
return
DAG
.
getNode
(
Opc
,
DL
,
MVT
::
Other
,
Chain
)
;
}
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_BPF64
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
Opc
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void MipsTargetStreamer :: emitGPRestore ( int Offset , SMLoc IDLoc , const MCSubtargetInfo * STI ) { emitLoadWithImmOffset ( Mips :: LW , Mips :: GP , Mips :: SP , Offset , Mips :: GP , IDLoc , STI ) ; } </s>

Emit the $ gp restore operation for .cprestore .

Mips Mips Mips::LW Mips::GP Mips::SP Mips::GP


<s> static void i386_pe_seh_fini ( FILE * f , bool cold ) { struct seh_frame_state * seh ; if ( ! TARGET_SEH ) return ; if ( cfun -> is_thunk ) return ; seh = cfun -> machine -> seh ; if ( cold != seh -> in_cold_section ) return ; XDELETE ( seh ) ; cfun -> machine -> seh = NULL ; fputs ( "\t.seh_endproc\n" , f ) ; } </s>

Emit an assembler directive for the end of the function .


<s> unsigned int mips_sync_loop_insns ( rtx_insn * insn , rtx * operands ) { mips_branch_likely = TARGET_FIX_R10000 ; mips_process_sync_loop ( insn , operands ) ; return mips_multi_num_insns ; } </s>

Return the number of individual instructions in sync loop INSN , which has the operands given by OPERANDS .


<s> void RISCVPassConfig :: addPreEmitPass ( ) { addPass ( & BranchRelaxationPassID ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static bool xstormy16_function_value_regno_p ( const unsigned int regno ) { return ( regno == RETURN_VALUE_REGNUM ) ; } </s>

Worker function for TARGET_FUNCTION_VALUE_REGNO_P .


<s>
void
HexagonEarlyIfConversion
::
removeBlock
(
MachineBasicBlock
*
B
)
{
DEBUG
(
dbgs
(
)
<<
"Removing block "
<<
PrintMB
(
B
)
<<
"\n"
)
;
MachineDomTreeNode
*
N
=
MDT
->
getNode
(
B
)
;
MachineDomTreeNode
*
IDN
=
N
->
getIDom
(
)
;
if
(
IDN
)
{
MachineBasicBlock
*
IDB
=
IDN
->
getBlock
(
)
;
typedef
GraphTraits
<
MachineDomTreeNode
*
>
GTN
;
typedef
SmallVector
<
MachineDomTreeNode
*
,
4
>
DTNodeVectType
;
DTNodeVectType
Cn
(
GTN
::
child_begin
(
N
)
,
GTN
::
child_end
(
N
)
)
;
for
(
DTNodeVectType
::
iterator
I
=
Cn
.
begin
(
)
,
E
=
Cn
.
end
(
)
;
I
!=
E
;
++
I
)
{
MachineBasicBlock
*
SB
=
(
*
I
)
->
getBlock
(
)
;
MDT
->
changeImmediateDominator
(
SB
,
IDB
)
;
}
}
while
(
B
->
succ_size
(
)
>
0
)
B
->
removeSuccessor
(
B
->
succ_begin
(
)
)
;
for
(
auto
I
=
B
->
pred_begin
(
)
,
E
=
B
->
pred_end
(
)
;
I
!=
E
;
++
I
)
(
*
I
)
->
removeSuccessor
(
B
)
;
Deleted
.
insert
(
B
)
;
MDT
->
eraseNode
(
B
)
;
MFN
->
erase
(
B
->
getIterator
(
)
)
;
}
</s>

This method completely removes BB from all data structures , including all of the Loop objects it is nested in and our mapping from MachineBasicBlocks to loops .

Hexagon
Hexagon
"Removing block "
"\n"
4
0


<s> void SIInstrInfo :: swapOperands ( MachineInstr & Inst ) const { assert ( Inst . getNumExplicitOperands ( ) == 3 ) ; MachineOperand Op1 = Inst . getOperand ( 1 ) ; Inst . RemoveOperand ( 1 ) ; Inst . addOperand ( Op1 ) ; } </s>

Exchange the two operands to this instruction in such a way that it does not modify the semantics of the instruction .


<s>
void
SIInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
SIMachineFunctionInfo
*
MFI
=
MBB
.
getParent
(
)
->
getInfo
<
SIMachineFunctionInfo
>
(
)
;
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
unsigned
KillFlag
=
isKill
RegState
::
Kill
:
0
;
MachineRegisterInfo
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
if
(
TRI
->
getCommonSubClass
(
RC
,
&
AMDGPU
::
SGPR_32RegClass
)
)
{
unsigned
Lane
=
MFI
->
SpillTracker
.
reserveLanes
(
MRI
,
MBB
.
getParent
(
)
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
AMDGPU
::
V_WRITELANE_B32
)
,
MFI
->
SpillTracker
.
LaneVGPR
)
.
addReg
(
SrcReg
,
KillFlag
)
.
addImm
(
Lane
)
;
MFI
->
SpillTracker
.
addSpilledReg
(
FrameIndex
,
MFI
->
SpillTracker
.
LaneVGPR
,
Lane
)
;
}
else
if
(
RI
.
isSGPRClass
(
RC
)
)
{
unsigned
NumSubRegs
=
RC
->
getSize
(
)
/
4
;
unsigned
FirstLane
=
MFI
->
SpillTracker
.
reserveLanes
(
MRI
,
MBB
.
getParent
(
)
,
NumSubRegs
)
;
MFI
->
SpillTracker
.
addSpilledReg
(
FrameIndex
,
MFI
->
SpillTracker
.
LaneVGPR
,
FirstLane
)
;
unsigned
Opcode
;
switch
(
RC
->
getSize
(
)
*
8
)
{
case
64
:
Opcode
=
AMDGPU
::
SI_SPILL_S64_SAVE
;
break
;
case
128
:
Opcode
=
AMDGPU
::
SI_SPILL_S128_SAVE
;
break
;
case
256
:
Opcode
=
AMDGPU
::
SI_SPILL_S256_SAVE
;
break
;
case
512
:
Opcode
=
AMDGPU
::
SI_SPILL_S512_SAVE
;
break
;
default
:
llvm_unreachable
(
"Cannot spill register class"
)
;
}
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opcode
)
,
MFI
->
SpillTracker
.
LaneVGPR
)
.
addReg
(
SrcReg
)
.
addImm
(
FrameIndex
)
;
}
else
{
llvm_unreachable
(
"VGPR spilling not supported"
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool useAA ( ) const override { return true ; } </s>

Enable use of alias analysis during code generation ( during MI scheduling , DAGCombine , etc . ) .


<s> DecodeStatus HexagonDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & cs ) const { DecodeStatus Result = DecodeStatus :: Success ; bool Complete = false ; Size = 0 ; * CurrentBundle = & MI ; MI . setOpcode ( Hexagon :: BUNDLE ) ; MI . addOperand ( MCOperand :: createImm ( 0 ) ) ; while ( Result == Success && ! Complete ) { if ( Bytes . size ( ) < HEXAGON_INSTR_SIZE ) return MCDisassembler :: Fail ; MCInst * Inst = getContext ( ) . createMCInst ( ) ; Result = getSingleInstruction ( * Inst , MI , Bytes , Address , cs , Complete ) ; MI . addOperand ( MCOperand :: createInst ( Inst ) ) ; Size += HEXAGON_INSTR_SIZE ; Bytes = Bytes . slice ( HEXAGON_INSTR_SIZE ) ; } if ( Result == MCDisassembler :: Fail ) return Result ; if ( Size > HEXAGON_MAX_PACKET_SIZE ) return MCDisassembler :: Fail ; const auto ArchSTI = Hexagon_MC :: getArchSubtarget ( & STI ) ; const auto STI_ = ( ArchSTI != nullptr ) ? * ArchSTI : STI ; HexagonMCChecker Checker ( getContext ( ) , * MCII , STI_ , MI , * getContext ( ) . getRegisterInfo ( ) , false ) ; if ( ! Checker . check ( ) ) return MCDisassembler :: Fail ; remapInstruction ( MI ) ; return MCDisassembler :: Success ; } </s>

Returns the disassembly of a single instruction .

Hexagon Hexagon 0 Hexagon::BUNDLE 0 Hexagon Hexagon


<s> EVT X86TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function & F = MF . getFunction ( ) ; if ( ! F . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { if ( Size >= 16 && ( ! Subtarget . isUnalignedMem16Slow ( ) || ( ( DstAlign == 0 || DstAlign >= 16 ) && ( SrcAlign == 0 || SrcAlign >= 16 ) ) ) ) { if ( Size >= 32 && Subtarget . hasAVX ( ) ) { return MVT :: v32i8 ; } if ( Subtarget . hasSSE2 ( ) ) return MVT :: v16i8 ; if ( Subtarget . hasSSE1 ( ) && ( Subtarget . is64Bit ( ) || Subtarget . hasX87 ( ) ) ) return MVT :: v4f32 ; } else if ( ( ! IsMemset || ZeroMemset ) && ! MemcpyStrSrc && Size >= 8 && ! Subtarget . is64Bit ( ) && Subtarget . hasSSE2 ( ) ) { return MVT :: f64 ; } } if ( Subtarget . is64Bit ( ) && Size >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> bool ix86_function_arg_regno_p ( int regno ) { int i ; enum calling_abi call_abi ; const int * parm_regs ; if ( TARGET_MPX && BND_REGNO_P ( regno ) ) return true ; if ( ! TARGET_64BIT ) { if ( TARGET_MACHO ) return ( regno < REGPARM_MAX || ( TARGET_SSE && SSE_REGNO_P ( regno ) && ! fixed_regs [ regno ] ) ) ; else return ( regno < REGPARM_MAX || ( TARGET_MMX && MMX_REGNO_P ( regno ) && ( regno < FIRST_MMX_REG + MMX_REGPARM_MAX ) ) || ( TARGET_SSE && SSE_REGNO_P ( regno ) && ( regno < FIRST_SSE_REG + SSE_REGPARM_MAX ) ) ) ; } if ( TARGET_SSE && SSE_REGNO_P ( regno ) && ( regno < FIRST_SSE_REG + SSE_REGPARM_MAX ) ) return true ; call_abi = ix86_cfun_abi ( ) ; if ( call_abi == SYSV_ABI && regno == AX_REG ) return true ; if ( call_abi == MS_ABI ) parm_regs = x86_64_ms_abi_int_parameter_registers ; else parm_regs = x86_64_int_parameter_registers ; for ( i = 0 ; i < ( call_abi == MS_ABI ? X86_64_MS_REGPARM_MAX : X86_64_REGPARM_MAX ) ; i ++ ) if ( regno == parm_regs [ i ] ) return true ; return false ; } </s>

Return true when register may be used to pass function parameters .


<s> static rtx arm_expand_neon_builtin ( int fcode , tree exp , rtx target ) { neon_builtin_datum * d = & neon_builtin_data [ fcode - ARM_BUILTIN_NEON_BASE ] ; enum insn_code icode = d -> code ; builtin_arg args [ SIMD_MAX_BUILTIN_ARGS ] ; int num_args = insn_data [ d -> code ] . n_operands ; int is_void = 0 ; int k ; is_void = ! ! ( d -> qualifiers [ 0 ] & qualifier_void ) ; num_args += is_void ; for ( k = 1 ; k < num_args ; k ++ ) { int qualifiers_k = k ; int operands_k = k - is_void ; int expr_args_k = k - 1 ; if ( d -> qualifiers [ qualifiers_k ] & qualifier_immediate ) args [ k ] = NEON_ARG_CONSTANT ; else if ( d -> qualifiers [ qualifiers_k ] & qualifier_maybe_immediate ) { rtx arg = expand_normal ( CALL_EXPR_ARG ( exp , ( expr_args_k ) ) ) ; bool op_const_int_p = ( CONST_INT_P ( arg ) && ( * insn_data [ icode ] . operand [ operands_k ] . predicate ) ( arg , insn_data [ icode ] . operand [ operands_k ] . mode ) ) ; args [ k ] = op_const_int_p ? NEON_ARG_CONSTANT : NEON_ARG_COPY_TO_REG ; } else if ( d -> qualifiers [ qualifiers_k ] & qualifier_pointer ) args [ k ] = NEON_ARG_MEMORY ; else args [ k ] = NEON_ARG_COPY_TO_REG ; } args [ k ] = NEON_ARG_STOP ; return arm_expand_neon_args ( target , d -> mode , fcode , icode , ! is_void , exp , args [ 1 ] , args [ 2 ] , args [ 3 ] , args [ 4 ] , NEON_ARG_STOP ) ; } </s>

Expand a Neon builtin , i.e . those registered only if TARGET_NEON holds . Most of these are `` special '' because they do n't have symbolic constants defined per-instruction or per instruction-variant . Instead , the required info is looked up in the table neon_builtin_data .


<s> int h8300_eightbit_data_p ( tree decl ) { tree a ; if ( TREE_CODE ( decl ) != VAR_DECL ) return 0 ; a = lookup_attribute ( "eightbit_data" , DECL_ATTRIBUTES ( decl ) ) ; return a != NULL_TREE ; } </s>

Return nonzero if DECL is a variable that 's in the eight bit data area .


<s> int cris_cfun_uses_pic_table ( void ) { return crtl -> uses_pic_offset_table ; } </s>

Return current_function_uses_pic_offset_table . For use in cris.md , since some generated files do not include function.h .


<s> void F2003fMCAsmStreamer :: reset ( ) { LabelToEmit . clear ( ) ; ExplicitCommentToEmit . clear ( ) ; CommentToEmit . clear ( ) ; Symbols . clear ( ) ; CurrentAlignmentToValue = 1 ; ValueBuffer . clear ( ) ; MCStreamer :: reset ( ) ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCRelaxableFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
override
{
llvm_unreachable
(
"RelaxInstruction() unimplemented"
)
;
return
false
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> static void emitSPUpdate ( bool isARM , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , const ARMBaseInstrInfo & TII , int NumBytes , ARMCC :: CondCodes Pred = ARMCC :: AL , unsigned PredReg = 0 ) { if ( isARM ) emitARMRegPlusImmediate ( MBB , MBBI , dl , ARM :: SP , ARM :: SP , NumBytes , Pred , PredReg , TII ) ; else emitT2RegPlusImmediate ( MBB , MBBI , dl , ARM :: SP , ARM :: SP , NumBytes , Pred , PredReg , TII ) ; } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .

ARM ARM ARM ARMCC::CondCodes ARMCC::AL 0 ARM ARM ARM::SP ARM::SP ARM::SP ARM::SP


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


"No ISEL instructions in this function\n"

runOnMachineFunction - Emit the function body .


<s> tree rs6000_builtin_reciprocal ( tree fndecl ) { switch ( DECL_MD_FUNCTION_CODE ( fndecl ) ) { case RS6000_BIF_XVSQRTDP : if ( ! RS6000_RECIP_AUTO_RSQRTE_P ( V2DFmode ) ) return NULL_TREE ; return rs6000_builtin_decls [ RS6000_BIF_RSQRT_2DF ] ; case RS6000_BIF_XVSQRTSP : if ( ! RS6000_RECIP_AUTO_RSQRTE_P ( V4SFmode ) ) return NULL_TREE ; return rs6000_builtin_decls [ RS6000_BIF_RSQRT_4SF ] ; default : return NULL_TREE ; } } </s>

Returns a code for a target-specific builtin that implements reciprocal of the function , or NULL_TREE if not available .


<s> static struct machine_function * iq2000_init_machine_status ( void ) { struct machine_function * f ; f = ggc_alloc_cleared ( sizeof ( struct machine_function ) ) ; return f ; } </s>

Allocate a chunk of memory for per-function machine-dependent data .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
VE
::
NumTargetFixupKinds
]
=
{
{
"fixup_ve_reflong"
,
0
,
32
,
0
}
,
{
"fixup_ve_srel32"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ve_hi32"
,
0
,
32
,
0
}
,
{
"fixup_ve_lo32"
,
0
,
32
,
0
}
,
{
"fixup_ve_pc_hi32"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ve_pc_lo32"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ve_got_hi32"
,
0
,
32
,
0
}
,
{
"fixup_ve_got_lo32"
,
0
,
32
,
0
}
,
{
"fixup_ve_gotoff_hi32"
,
0
,
32
,
0
}
,
{
"fixup_ve_gotoff_lo32"
,
0
,
32
,
0
}
,
{
"fixup_ve_plt_hi32"
,
0
,
32
,
0
}
,
{
"fixup_ve_plt_lo32"
,
0
,
32
,
0
}
,
{
"fixup_ve_tls_gd_hi32"
,
0
,
32
,
0
}
,
{
"fixup_ve_tls_gd_lo32"
,
0
,
32
,
0
}
,
{
"fixup_ve_tpoff_hi32"
,
0
,
32
,
0
}
,
{
"fixup_ve_tpoff_lo32"
,
0
,
32
,
0
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> static bool avr_decl_flash_p ( tree decl ) { if ( TREE_CODE ( decl ) != VAR_DECL || TREE_TYPE ( decl ) == error_mark_node ) { return false ; } return ! ADDR_SPACE_GENERIC_P ( TYPE_ADDR_SPACE ( TREE_TYPE ( decl ) ) ) ; } </s>

Return TRUE if DECL is a VAR_DECL located in flash and FALSE , otherwise .


<s> void DCPU16InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { unsigned Opc = DCPU16 :: MOV16rr ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } </s>


<s> bool M88kCallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < Register > VRegs , FunctionLoweringInfo & FLI , Register SwiftErrorVReg ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const M88kSubtarget & STI = MF . getSubtarget < M88kSubtarget > ( ) ; const M88kInstrInfo & TII = * STI . getInstrInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; Register ReturnAddrVReg = getFunctionLiveInPhysReg ( MF , TII , M88k :: R1 , M88k :: GPRRCRegClass , MIRBuilder . getDebugLoc ( ) ) ; MRI . setType ( ReturnAddrVReg , LLT :: pointer ( 0 , 32 ) ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( M88k :: RET ) ; bool Success = true ; if ( ! VRegs . empty ( ) ) { SmallVector < ArgInfo , 8 > SplitArgs ; ArgInfo OrigArg { VRegs , Val -> getType ( ) , 0 } ; setArgFlags ( OrigArg , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , F . getCallingConv ( ) ) ; OutgoingValueAssigner ArgAssigner ( RetCC_M88k ) ; OutgoingArgHandler ArgHandler ( MIRBuilder , MRI , MIB ) ; Success = determineAndHandleAssignments ( ArgHandler , ArgAssigner , SplitArgs , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ; } MIRBuilder . buildCopy ( M88k :: R1 , ReturnAddrVReg ) ; MIRBuilder . insertInstr ( MIB ) ; return Success ; } </s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> void PPCInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { unsigned Directive = Subtarget . getDarwinDirective ( ) ; unsigned Opcode ; switch ( Directive ) { default : Opcode = PPC :: NOP ; break ; case PPC :: DIR_PWR6 : Opcode = PPC :: NOP_GT_PWR6 ; break ; case PPC :: DIR_PWR7 : Opcode = PPC :: NOP_GT_PWR7 ; break ; case PPC :: DIR_PWR8 : Opcode = PPC :: NOP_GT_PWR7 ; break ; case PPC :: DIR_PWR9 : Opcode = PPC :: NOP_GT_PWR7 ; break ; } DebugLoc DL ; BuildMI ( MBB , MI , DL , get ( Opcode ) ) ; } </s>

Insert a noop into the instruction stream at the specified point .


<s> static rtx rs6000_longcall_ref ( rtx call_ref , rtx arg ) { const char * call_name = XSTR ( call_ref , 0 ) ; if ( * call_name == '.' ) { while ( * call_name == '.' ) call_name ++ ; tree node = get_identifier ( call_name ) ; call_ref = gen_rtx_SYMBOL_REF ( VOIDmode , IDENTIFIER_POINTER ( node ) ) ; } if ( TARGET_PLTSEQ ) { rtx base = const0_rtx ; int regno ; if ( DEFAULT_ABI == ABI_ELFv2 ) { base = gen_rtx_REG ( Pmode , TOC_REGISTER ) ; regno = 12 ; } else { if ( flag_pic ) base = gen_rtx_REG ( Pmode , RS6000_PIC_OFFSET_TABLE_REGNUM ) ; regno = 11 ; } rtx reg = gen_rtx_REG ( Pmode , regno ) ; rtx hi = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 3 , base , call_ref , arg ) , UNSPEC_PLT16_HA ) ; rtx lo = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 3 , reg , call_ref , arg ) , UNSPEC_PLT16_LO ) ; emit_insn ( gen_rtx_SET ( reg , hi ) ) ; emit_insn ( gen_rtx_SET ( reg , lo ) ) ; return reg ; } return force_reg ( Pmode , call_ref ) ; } </s>

Return a reference suitable for calling a function with the longcall attribute .


"Asked to disassemble an ARM instruction but Subtarget is in Thumb "

Returns the disassembly of a single instruction .


<s>
StringRef
getPassName
(
)
const
override
{
return
"AArch64 Instruction Selection"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static rtx mep_convert_arg ( machine_mode mode , rtx arg ) { if ( GET_MODE ( arg ) != mode && register_operand ( arg , VOIDmode ) && GET_MODE_SIZE ( GET_MODE ( arg ) ) == GET_MODE_SIZE ( mode ) ) return simplify_gen_subreg ( mode , arg , GET_MODE ( arg ) , 0 ) ; return arg ; } </s>

If ARG is a register operand that is the same size as MODE , convert it to MODE using a subreg . Otherwise return ARG as-is .


<s> bool aarch64_sve_ldr_operand_p ( rtx op ) { struct aarch64_address_info addr ; return ( MEM_P ( op ) && aarch64_classify_address ( & addr , XEXP ( op , 0 ) , GET_MODE ( op ) , false , ADDR_QUERY_ANY ) && addr . type == ADDRESS_REG_IMM ) ; } </s>

Return true if OP is a valid MEM operand for an SVE LDR instruction . The conditions for STR are the same .


<s> BitVector MipsRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const unsigned ReservedCPURegs [ ] = { Mips :: ZERO , Mips :: AT , Mips :: K0 , Mips :: K1 , Mips :: GP , Mips :: SP , Mips :: FP , Mips :: RA } ; static const unsigned ReservedCPU64Regs [ ] = { Mips :: ZERO_64 , Mips :: AT_64 , Mips :: K0_64 , Mips :: K1_64 , Mips :: GP_64 , Mips :: SP_64 , Mips :: FP_64 , Mips :: RA_64 } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: iterator RegIter ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; if ( Subtarget . hasMips64 ( ) ) { for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPU64Regs ) ; ++ I ) Reserved . set ( ReservedCPU64Regs [ I ] ) ; for ( RegIter Reg = Mips :: AFGR64RegisterClass -> begin ( ) ; Reg != Mips :: AFGR64RegisterClass -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ; } else { for ( RegIter Reg = Mips :: CPU64RegsRegisterClass -> begin ( ) ; Reg != Mips :: CPU64RegsRegisterClass -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ; for ( RegIter Reg = Mips :: FGR64RegisterClass -> begin ( ) ; Reg != Mips :: FGR64RegisterClass -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static bool spu_vector_alignment_reachable ( const_tree type ATTRIBUTE_UNUSED , bool is_packed ) { if ( is_packed ) return false ; return true ; } </s>

Return true iff , data reference of TYPE can reach vector alignment ( 16 ) after applying N number of iterations . This routine does not determine how may iterations are required to reach desired alignment .


<s> static rtx nvptx_function_arg ( cumulative_args_t , const function_arg_info & arg ) { if ( arg . end_marker_p ( ) || ! arg . named ) return NULL_RTX ; return gen_reg_rtx ( arg . mode ) ; } </s>


<s> bool sh2a_function_vector_p ( tree func ) { tree list ; if ( TREE_CODE ( func ) != FUNCTION_DECL ) return false ; list = SH_ATTRIBUTES ( func ) ; while ( list ) { if ( is_attribute_p ( "function_vector" , TREE_PURPOSE ( list ) ) ) return true ; list = TREE_CHAIN ( list ) ; } return false ; } </s>

Returns true if FUNC has been assigned the attribute `` function_vector '' .


<s> enum reg_class arm_mode_base_reg_class ( machine_mode mode ) { if ( TARGET_HAVE_MVE && ( mode == E_V8QImode || mode == E_V4QImode || mode == E_V4HImode ) ) return LO_REGS ; return MODE_BASE_REG_REG_CLASS ( mode ) ; } </s>

If given mode matches , load from memory to LO_REGS . ( i.e [ Rn ] , Rn < = LO_REGS ) .


<s> const X86TargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .