<s> const char * Z80oldTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( Z80oldISD :: NodeType ) Opcode ) { case Z80oldISD :: FIRST_NUMBER : break ; case Z80oldISD :: Wrapper : return "Z80oldISD::Wrapper" ; case Z80oldISD :: RLC : return "Z80oldISD::RLC" ; case Z80oldISD :: RRC : return "Z80oldISD::RRC" ; case Z80oldISD :: RL : return "Z80oldISD::RL" ; case Z80oldISD :: RR : return "Z80oldISD::RR" ; case Z80oldISD :: SLA : return "Z80oldISD::SLA" ; case Z80oldISD :: SRA : return "Z80oldISD::SRA" ; case Z80oldISD :: SRL : return "Z80oldISD::SRL" ; case Z80oldISD :: INC : return "Z80oldISD::INC" ; case Z80oldISD :: DEC : return "Z80oldISD::DEC" ; case Z80oldISD :: ADD : return "Z80oldISD::ADD" ; case Z80oldISD :: ADC : return "Z80oldISD::ADC" ; case Z80oldISD :: SUB : return "Z80oldISD::SUB" ; case Z80oldISD :: SBC : return "Z80oldISD::SBC" ; case Z80oldISD :: AND : return "Z80oldISD::AND" ; case Z80oldISD :: XOR : return "Z80oldISD::XOR" ; case Z80oldISD :: OR : return "Z80oldISD::OR" ; case Z80oldISD :: CP : return "Z80oldISD::CP" ; case Z80oldISD :: TST : return "Z80oldISD::TST" ; case Z80oldISD :: MLT : return "Z80oldISD::MLT" ; case Z80oldISD :: SEXT : return "Z80oldISD::SEXT" ; case Z80oldISD :: CALL : return "Z80oldISD::CALL" ; case Z80oldISD :: RET_FLAG : return "Z80oldISD::RET_FLAG" ; case Z80oldISD :: RETN_FLAG : return "Z80oldISD::RETN_FLAG" ; case Z80oldISD :: RETI_FLAG : return "Z80oldISD::RETI_FLAG" ; case Z80oldISD :: TC_RETURN : return "Z80oldISD::TC_RETURN" ; case Z80oldISD :: BRCOND : return "Z80oldISD::BRCOND" ; case Z80oldISD :: SELECT : return "Z80oldISD::SELECT" ; case Z80oldISD :: POP : return "Z80oldISD::POP" ; case Z80oldISD :: PUSH : return "Z80oldISD::PUSH" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> bool find ( const SPIRV :: SpecialTypeDescriptor & TD , const MachineFunction * MF , Register & R ) { return ST . find ( TD , MF , R ) ; } </s>

Search for the first string Str in the string .


<s> param_iterator arg_begin ( ) const { return ArgumentParams . begin ( ) ; } </s>

Return the iterator pointing to the beginning of the argument list .


<s>
const
MCFixupKindInfo
&
X86AsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
X86
::
NumTargetFixupKinds
]
=
{
{
"reloc_riprel_4byte"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_movq_load"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_relax"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_relax_rex"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_signed_4byte"
,
0
,
32
,
0
}
,
{
"reloc_signed_4byte_relax"
,
0
,
32
,
0
}
,
{
"reloc_global_offset_table"
,
0
,
32
,
0
}
,
{
"reloc_global_offset_table8"
,
0
,
64
,
0
}
,
{
"reloc_branch_4byte_pcrel"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
>=
FirstLiteralRelocationKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
FK_NONE
)
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
assert
(
Infos
[
Kind
FirstTargetFixupKind
]
.
Name
&&
"Empty fixup name!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> bool isReg ( ) const { return Kind == CV_Register ; } </s>


<s> const MCPhysReg * R600RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * ) const { return & CalleeSavedReg ; } </s>


<s>
bool
AArch64LegalizerInfo
::
legalizeCustom
(
LegalizerHelper
&
Helper
,
MachineInstr
&
MI
)
const
{
MachineIRBuilder
&
MIRBuilder
=
Helper
.
MIRBuilder
;
MachineRegisterInfo
&
MRI
=
*
MIRBuilder
.
getMRI
(
)
;
GISelChangeObserver
&
Observer
=
Helper
.
Observer
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
return
false
;
case
TargetOpcode
::
G_VAARG
:
return
legalizeVaArg
(
MI
,
MRI
,
MIRBuilder
)
;
case
TargetOpcode
::
G_LOAD
:
case
TargetOpcode
::
G_STORE
:
return
legalizeLoadStore
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
case
TargetOpcode
::
G_SHL
:
case
TargetOpcode
::
G_ASHR
:
case
TargetOpcode
::
G_LSHR
:
return
legalizeShlAshrLshr
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
case
TargetOpcode
::
G_GLOBAL_VALUE
:
return
legalizeSmallCMGlobalValue
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
case
TargetOpcode
::
G_TRUNC
:
return
legalizeVectorTrunc
(
MI
,
Helper
)
;
}
llvm_unreachable
(
"expected switch to return"
)
;
}
</s>

Called for instructions with the Custom LegalizationAction .


<s> void TOYInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << '$' << StringRef ( getRegisterName ( RegNo ) ) . lower ( ) ; } </s>


<s> void AMDGPUTargetELFStreamer :: finish ( ) { std :: string Blob ; const char * Vendor = getPALMetadata ( ) -> getVendor ( ) ; unsigned Type = getPALMetadata ( ) -> getType ( ) ; getPALMetadata ( ) -> toBlob ( Type , Blob ) ; if ( Blob . empty ( ) ) return ; EmitNote ( Vendor , MCConstantExpr :: create ( Blob . size ( ) , getContext ( ) ) , Type , [ & ] ( MCELFStreamer & OS ) { OS . emitBytes ( Blob ) ; } ) ; getPALMetadata ( ) -> reset ( ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s>
std
::
string
HSAILIntrinsicInfo
::
getName
(
unsigned
int
IntrID
,
Type
*
*
Tys
,
unsigned
int
numTys
)
const
{
static
const
char
*
const
names
[
]
=
{
}
;
if
(
IntrID
<
Intrinsic
::
num_intrinsics
)
{
return
0
;
}
assert
(
IntrID
<
HSAILIntrinsic
::
num_HSAIL_intrinsics
&&
"Invalid intrinsic ID"
)
;
std
::
string
Result
(
names
[
IntrID
Intrinsic
::
num_intrinsics
]
)
;
return
Result
;
}
</s>

Return a string with the name of the plan and the applicable VFs and UFs .


"Constant Island pass failed to converge!"

"Branch Fix Up pass failed to converge!"

runOnMachineFunction - Emit the function body .


"passing %qT to argument %d of %qE, which"

Require argument ARGNO to be a vector or scalar argument . Return true if it is , otherwise report an appropriate error .


"Stack object offsets should be 0 before frame finalized"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> static void avr_reorg ( void ) { rtx insn , pattern ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( ! ( GET_CODE ( insn ) == INSN || GET_CODE ( insn ) == CALL_INSN || GET_CODE ( insn ) == JUMP_INSN ) || ! single_set ( insn ) ) continue ; pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) == PARALLEL ) pattern = XVECEXP ( pattern , 0 , 0 ) ; if ( GET_CODE ( pattern ) == SET && SET_DEST ( pattern ) == cc0_rtx && compare_diff_p ( insn ) ) { if ( GET_CODE ( SET_SRC ( pattern ) ) == COMPARE ) { pattern = SET_SRC ( pattern ) ; if ( true_regnum ( XEXP ( pattern , 0 ) ) >= 0 && true_regnum ( XEXP ( pattern , 1 ) ) >= 0 ) { rtx x = XEXP ( pattern , 0 ) ; rtx next = next_real_insn ( insn ) ; rtx pat = PATTERN ( next ) ; rtx src = SET_SRC ( pat ) ; rtx t = XEXP ( src , 0 ) ; PUT_CODE ( t , swap_condition ( GET_CODE ( t ) ) ) ; XEXP ( pattern , 0 ) = XEXP ( pattern , 1 ) ; XEXP ( pattern , 1 ) = x ; INSN_CODE ( next ) = - 1 ; } else if ( true_regnum ( XEXP ( pattern , 0 ) ) >= 0 && GET_CODE ( XEXP ( pattern , 1 ) ) == CONST_INT ) { rtx x = XEXP ( pattern , 1 ) ; rtx next = next_real_insn ( insn ) ; rtx pat = PATTERN ( next ) ; rtx src = SET_SRC ( pat ) ; rtx t = XEXP ( src , 0 ) ; enum machine_mode mode = GET_MODE ( XEXP ( pattern , 0 ) ) ; if ( avr_simplify_comparison_p ( mode , GET_CODE ( t ) , x ) ) { XEXP ( pattern , 1 ) = gen_int_mode ( INTVAL ( x ) + 1 , mode ) ; PUT_CODE ( t , avr_normalize_condition ( GET_CODE ( t ) ) ) ; INSN_CODE ( next ) = - 1 ; INSN_CODE ( insn ) = - 1 ; } } } else if ( true_regnum ( SET_SRC ( pattern ) ) >= 0 ) { rtx next = next_real_insn ( insn ) ; rtx pat = PATTERN ( next ) ; rtx src = SET_SRC ( pat ) ; rtx t = XEXP ( src , 0 ) ; PUT_CODE ( t , swap_condition ( GET_CODE ( t ) ) ) ; SET_SRC ( pattern ) = gen_rtx_NEG ( GET_MODE ( SET_SRC ( pattern ) ) , SET_SRC ( pattern ) ) ; INSN_CODE ( next ) = - 1 ; INSN_CODE ( insn ) = - 1 ; } } } } </s>

This function optimizes conditional jumps .


"\t.section .directive, \"SM\", @progbits, 1\n"

Output the start of the assembler file .


<s> static bool rs6000_expand_vec_perm_const_1 ( rtx target , rtx op0 , rtx op1 , unsigned char perm0 , unsigned char perm1 ) { rtx x ; if ( ( perm0 & 2 ) == ( perm1 & 2 ) ) { if ( perm0 & 2 ) op0 = op1 ; else op1 = op0 ; } if ( rtx_equal_p ( op0 , op1 ) ) { perm0 = perm0 & 1 ; perm1 = ( perm1 & 1 ) + 2 ; } else if ( perm0 & 2 ) { if ( perm1 & 2 ) return false ; perm0 -= 2 ; perm1 += 2 ; std :: swap ( op0 , op1 ) ; } else if ( ( perm1 & 2 ) == 0 ) return false ; if ( target != NULL ) { machine_mode vmode , dmode ; rtvec v ; vmode = GET_MODE ( target ) ; gcc_assert ( GET_MODE_NUNITS ( vmode ) == 2 ) ; dmode = mode_for_vector ( GET_MODE_INNER ( vmode ) , 4 ) ; x = gen_rtx_VEC_CONCAT ( dmode , op0 , op1 ) ; v = gen_rtvec ( 2 , GEN_INT ( perm0 ) , GEN_INT ( perm1 ) ) ; x = gen_rtx_VEC_SELECT ( vmode , x , gen_rtx_PARALLEL ( VOIDmode , v ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , x ) ) ; } return true ; } </s>

Expand a Paired Single or VSX Permute Doubleword constant permutation . Return true if we match an efficient implementation .


<s> unsigned AArch64InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case AArch64 :: LDRWui : case AArch64 :: LDRXui : case AArch64 :: LDRBui : case AArch64 :: LDRHui : case AArch64 :: LDRSui : case AArch64 :: LDRDui : case AArch64 :: LDRQui : case AArch64 :: LDR_PXI : case AArch64 :: LDR_ZXI : case AArch64 :: LDR_ZZXI : case AArch64 :: LDR_ZZZXI : case AArch64 :: LDR_ZZZZXI : if ( MI -> getOperand ( 0 ) . getSubReg ( ) == 0 && MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


"Pseudo opcode found in EmitInstruction()"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> int cr16_interrupt_function_p ( void ) { tree attributes ; attributes = TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ; return ( lookup_attribute ( "interrupt" , attributes ) != NULL_TREE ) ; } </s>

Return nonzero if the current function being compiled is an interrupt function as specified by the `` interrupt '' attribute .


<s> bool NVPTXTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( AM . BaseGV ) { return ! AM . BaseOffs && ! AM . HasBaseReg && ! AM . Scale ; } switch ( AM . Scale ) { case 0 : break ; case 1 : if ( AM . HasBaseReg ) return false ; break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> bool HexagonInstrInfo :: areMemAccessesTriviallyDisjoint ( const MachineInstr & MIa , const MachineInstr & MIb , AliasAnalysis * AA ) const { if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) || MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; if ( MIa . mayLoad ( ) && ! isMemOp ( MIa ) && MIb . mayLoad ( ) && ! isMemOp ( MIb ) ) return true ; unsigned BasePosA , OffsetPosA ; if ( ! getBaseAndOffsetPosition ( MIa , BasePosA , OffsetPosA ) ) return false ; const MachineOperand & BaseA = MIa . getOperand ( BasePosA ) ; Register BaseRegA = BaseA . getReg ( ) ; unsigned BaseSubA = BaseA . getSubReg ( ) ; unsigned BasePosB , OffsetPosB ; if ( ! getBaseAndOffsetPosition ( MIb , BasePosB , OffsetPosB ) ) return false ; const MachineOperand & BaseB = MIb . getOperand ( BasePosB ) ; Register BaseRegB = BaseB . getReg ( ) ; unsigned BaseSubB = BaseB . getSubReg ( ) ; if ( BaseRegA != BaseRegB || BaseSubA != BaseSubB ) return false ; unsigned SizeA = getMemAccessSize ( MIa ) ; unsigned SizeB = getMemAccessSize ( MIb ) ; const MachineOperand & OffA = MIa . getOperand ( OffsetPosA ) ; const MachineOperand & OffB = MIb . getOperand ( OffsetPosB ) ; if ( ! MIa . getOperand ( OffsetPosA ) . isImm ( ) || ! MIb . getOperand ( OffsetPosB ) . isImm ( ) ) return false ; int OffsetA = isPostIncrement ( MIa ) ? 0 : OffA . getImm ( ) ; int OffsetB = isPostIncrement ( MIb ) ? 0 : OffB . getImm ( ) ; if ( OffsetA > OffsetB ) { uint64_t OffDiff = ( uint64_t ) ( ( int64_t ) OffsetA - ( int64_t ) OffsetB ) ; return SizeB <= OffDiff ; } if ( OffsetA < OffsetB ) { uint64_t OffDiff = ( uint64_t ) ( ( int64_t ) OffsetB - ( int64_t ) OffsetA ) ; return SizeA <= OffDiff ; } return false ; } </s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> unsigned getTOCSaveOffset ( ) const { return TOCSaveOffset ; } </s>

getTOCSaveOffset - Return the previous frame offset to save the TOC register � ? 64-bit SVR4 ABI only .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static size_t cygwin_gt_pch_alloc_granularity ( void ) { return va_granularity ; } </s>

Return the alignment required for allocating virtual memory .


<s> void TGSIFrameLowering :: emitEpilogue ( MachineFunction & mf , MachineBasicBlock & mbb ) const { MachineBasicBlock :: iterator mbbi = mbb . getLastNonDebugInstr ( ) ; MachineFrameInfo & mfi = mf . getFrameInfo ( ) ; const TGSIInstrInfo & tii = * static_cast < const TGSIInstrInfo * > ( mf . getSubtarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl ; int frame_sz = mfi . getStackSize ( ) ; if ( frame_sz == 0 ) return ; BuildMI ( mbb , mbbi , dl , tii . get ( TGSI :: UADDs ) , TGSI :: TEMP0x ) . addReg ( TGSI :: TEMP0x ) . addImm ( - frame_sz ) ; } </s>


<s>
static
void
rs6000_darwin_file_start
(
void
)
{
static
const
struct
{
const
char
*
arg
;
const
char
*
name
;
int
if_set
;
}
mapping
[
]
=
{
{
"ppc64"
,
"ppc64"
,
MASK_64BIT
}
,
{
"970"
,
"ppc970"
,
MASK_PPC_GPOPT
|
MASK_MFCRF
|
MASK_POWERPC64
}
,
{
"power4"
,
"ppc970"
,
0
}
,
{
"G5"
,
"ppc970"
,
0
}
,
{
"7450"
,
"ppc7450"
,
0
}
,
{
"7400"
,
"ppc7400"
,
MASK_ALTIVEC
}
,
{
"G4"
,
"ppc7400"
,
0
}
,
{
"750"
,
"ppc750"
,
0
}
,
{
"740"
,
"ppc750"
,
0
}
,
{
"G3"
,
"ppc750"
,
0
}
,
{
"604e"
,
"ppc604e"
,
0
}
,
{
"604"
,
"ppc604"
,
0
}
,
{
"603e"
,
"ppc603"
,
0
}
,
{
"603"
,
"ppc603"
,
0
}
,
{
"601"
,
"ppc601"
,
0
}
,
{
,
"ppc"
,
0
}
}
;
const
char
*
cpu_id
=
""
;
size_t
i
;
rs6000_file_start
(
)
;
for
(
i
=
0
;
i
<
ARRAY_SIZE
(
rs6000_select
)
;
i
++
)
if
(
rs6000_select
[
i
]
.
set_arch_p
&&
rs6000_select
[
i
]
.
string
&&
rs6000_select
[
i
]
.
string
[
0
]
!=
'\0'
)
cpu_id
=
rs6000_select
[
i
]
.
string
;
i
=
0
;
while
(
mapping
[
i
]
.
arg
!=
&&
strcmp
(
mapping
[
i
]
.
arg
,
cpu_id
)
!=
0
&&
(
mapping
[
i
]
.
if_set
&
target_flags
)
==
0
)
i
++
;
fprintf
(
asm_out_file
,
"\t.machine %s\n"
,
mapping
[
i
]
.
name
)
;
}
</s>

Output a .machine directive for the Darwin assembler , and call the generic start_file routine .


<s>
void
eco32_print_operand
(
FILE
*
file
,
rtx
x
,
int
code
)
{
rtx
operand
=
x
;
switch
(
code
)
{
case
0
:
break
;
case
'H'
:
if
(
GET_CODE
(
x
)
==
REG
)
{
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
x
)
+
1
]
)
;
return
;
}
default
:
LOSE_AND_RETURN
(
"invalid operand modifier letter"
,
x
)
;
}
switch
(
GET_CODE
(
operand
)
)
{
case
REG
:
if
(
REGNO
(
operand
)
>=
FIRST_PSEUDO_REGISTER
)
internal_error
(
"internal error: bad register: %d"
,
REGNO
(
operand
)
)
;
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
operand
)
]
)
;
return
;
case
MEM
:
PRINT_OPERAND_ADDRESS
(
file
,
XEXP
(
operand
,
0
)
)
;
return
;
default
:
if
(
CONSTANT_P
(
operand
)
)
{
output_addr_const
(
file
,
operand
)
;
return
;
}
LOSE_AND_RETURN
(
"unexpected operand"
,
x
)
;
}
}
</s>


"all ColorKinds should be handled by the switch above"

Dump the plan to stderr ( for debugging ) .


<s> unsigned getMachineCSELookAheadLimit ( ) const override { return 500 ; } </s>

Return the value to use for the MachineCSE 's LookAheadLimit , which is a heuristic used for CSE'ing phys reg defs .


<s> unsigned RISCVInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : return 0 ; case RISCV :: SB : case RISCV :: SH : case RISCV :: SW : case RISCV :: FSH : case RISCV :: FSW : case RISCV :: SD : case RISCV :: FSD : break ; } if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> BitVector MSP430RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; Reserved . set ( MSP430 :: PCB ) ; Reserved . set ( MSP430 :: SPB ) ; Reserved . set ( MSP430 :: SRB ) ; Reserved . set ( MSP430 :: CGB ) ; Reserved . set ( MSP430 :: PC ) ; Reserved . set ( MSP430 :: SP ) ; Reserved . set ( MSP430 :: SR ) ; Reserved . set ( MSP430 :: CG ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( MSP430 :: FPB ) ; Reserved . set ( MSP430 :: FP ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
static
bool
m32c_can_change_mode_class
(
machine_mode
from
,
machine_mode
to
,
reg_class_t
rclass
)
{
int
rn
;
fprintf
(
stderr
,
"can change from %s to %s in %s\n"
,
mode_name
[
from
]
,
mode_name
[
to
]
,
class_names
[
rclass
]
)
;
for
(
rn
=
0
;
rn
<
FIRST_PSEUDO_REGISTER
;
rn
++
)
if
(
class_contents
[
rclass
]
[
0
]
&
(
1
<<
rn
)
)
if
(
!
m32c_hard_regno_mode_ok
(
rn
,
to
)
)
return
false
;
if
(
to
==
QImode
)
return
(
class_contents
[
rclass
]
[
0
]
&
0x1ffa
)
==
0
;
if
(
class_contents
[
rclass
]
[
0
]
&
0x0005
&&
GET_MODE_SIZE
(
from
)
>
1
)
return
true
;
if
(
GET_MODE_SIZE
(
from
)
>
2
)
return
true
;
return
false
;
}
</s>

Implements TARGET_CAN_CHANGE_MODE_CLASS . Only r0 and r1 can change to QI ( r0l , r1l ) because the chip does n't support QI ops on other registers ( well , it does on a0/a1 but if we let gcc do that , reload suffers ) . Otherwise , we allow changes to larger modes .


<s> void PPCRegisterInfo :: lowerCRSpilling ( MachineBasicBlock :: iterator II , unsigned FrameIndex , int SPAdj , RegScavenger * RS ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; const TargetRegisterClass * G8RC = & PPC :: G8RCRegClass ; const TargetRegisterClass * GPRC = & PPC :: GPRCRegClass ; const TargetRegisterClass * RC = Subtarget . isPPC64 ( ) ? G8RC : GPRC ; unsigned Reg = findScratchRegister ( II , RS , RC , SPAdj ) ; if ( ! MI . getOperand ( 0 ) . isKill ( ) ) BuildMI ( MBB , II , dl , TII . get ( PPC :: MFCR ) , Reg ) ; else BuildMI ( MBB , II , dl , TII . get ( PPC :: MFCR ) , Reg ) . addReg ( MI . getOperand ( 0 ) . getReg ( ) , false , true , true ) ; unsigned SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; if ( SrcReg != PPC :: CR0 ) BuildMI ( MBB , II , dl , TII . get ( PPC :: RLWINM ) , Reg ) . addReg ( Reg , false , false , true ) . addImm ( PPCRegisterInfo :: getRegisterNumbering ( SrcReg ) * 4 ) . addImm ( 0 ) . addImm ( 31 ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( PPC :: STW ) ) . addReg ( Reg , false , false , MI . getOperand ( 1 ) . getImm ( ) ) , FrameIndex ) ; MBB . erase ( II ) ; } </s>

lowerCRSpilling - Generate the code for spilling a CR register .


<s> static void mcore_unique_section ( tree decl , int reloc ATTRIBUTE_UNUSED ) { int len ; const char * name ; char * string ; const char * prefix ; name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; name = ( * targetm . strip_name_encoding ) ( name ) ; if ( TREE_CODE ( decl ) == FUNCTION_DECL ) prefix = ".text$" ; else if ( decl_readonly_section ( decl , 0 ) ) prefix = ".rdata$" ; else prefix = ".data$" ; len = strlen ( name ) + strlen ( prefix ) ; string = alloca ( len + 1 ) ; sprintf ( string , "%s%s" , prefix , name ) ; DECL_SECTION_NAME ( decl ) = build_string ( len , string ) ; } </s>


<s> int arc_check_millicode ( rtx op , int offset , int load_p ) { int len = XVECLEN ( op , 0 ) - offset ; int i ; if ( load_p == 2 ) { if ( len < 2 || len > 13 ) return 0 ; load_p = 1 ; } else { rtx elt = XVECEXP ( op , 0 , -- len ) ; if ( GET_CODE ( elt ) != CLOBBER || ! REG_P ( XEXP ( elt , 0 ) ) || REGNO ( XEXP ( elt , 0 ) ) != RETURN_ADDR_REGNUM || len < 3 || len > 13 ) return 0 ; } for ( i = 1 ; i < len ; i ++ ) { rtx elt = XVECEXP ( op , 0 , i + offset ) ; rtx reg , mem , addr ; if ( GET_CODE ( elt ) != SET ) return 0 ; mem = XEXP ( elt , load_p ) ; reg = XEXP ( elt , 1 - load_p ) ; if ( ! REG_P ( reg ) || REGNO ( reg ) != 13U + i || ! MEM_P ( mem ) ) return 0 ; addr = XEXP ( mem , 0 ) ; if ( GET_CODE ( addr ) != PLUS || ! rtx_equal_p ( stack_pointer_rtx , XEXP ( addr , 0 ) ) || ! CONST_INT_P ( XEXP ( addr , 1 ) ) || INTVAL ( XEXP ( addr , 1 ) ) != i * 4 ) return 0 ; } return 1 ; } </s>

Check if OP is a proper parallel of a millicode call pattern . OFFSET indicates a number of elements to ignore - that allows to have a sibcall pattern that starts with ( return ) . LOAD_P is zero for store multiple ( for prologues ) , and one for load multiples ( for epilogues ) , and two for load multiples where no final clobber of blink is required . We also skip the first load / store element since this is supposed to be checked in the instruction pattern .


<s> static bool arm_function_value_regno_p ( const unsigned int regno ) { if ( regno == ARG_REGISTER ( 1 ) || ( TARGET_32BIT && TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT && regno == FIRST_VFP_REGNUM ) || ( TARGET_IWMMXT_ABI && regno == FIRST_IWMMXT_REGNUM ) ) return true ; return false ; } </s>


<s> bool X86Subtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = TargetSubtargetInfo :: ANTIDEP_CRITICAL ; CriticalPathRCs . clear ( ) ; return PostRAScheduler && OptLevel >= CodeGenOpt :: Default ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s> const RegisterBankInfo :: ValueMapping * AMDGPURegisterBankInfo :: getValueMappingForPtr ( const MachineRegisterInfo & MRI , Register PtrReg ) const { LLT PtrTy = MRI . getType ( PtrReg ) ; unsigned Size = PtrTy . getSizeInBits ( ) ; if ( Subtarget . useFlatForGlobal ( ) || ! AMDGPU :: isFlatGlobalAddrSpace ( PtrTy . getAddressSpace ( ) ) ) return AMDGPU :: getValueMapping ( AMDGPU :: VGPRRegBankID , Size ) ; const RegisterBank * PtrBank = getRegBank ( PtrReg , MRI , * TRI ) ; return AMDGPU :: getValueMapping ( PtrBank -> getID ( ) , Size ) ; } </s>

Return the mapping for a pointer argument .

AMDGPU AMDGPU AMDGPU::isFlatGlobalAddrSpace AMDGPU::getValueMapping AMDGPU::VGPRRegBankID AMDGPU::getValueMapping


<s> unsigned SIInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const MCInstrDesc & Desc = getMCOpcodeFromPseudo ( Opc ) ; unsigned DescSize = Desc . getSize ( ) ; if ( isFixedSize ( MI ) ) return DescSize ; if ( isVALU ( MI ) || isSALU ( MI ) ) { int Src0Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src0 ) ; if ( Src0Idx == - 1 ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src0Idx ) , Desc . OpInfo [ Src0Idx ] ) ) return isVOP3 ( MI ) ? 12 : ( DescSize + 4 ) ; int Src1Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src1 ) ; if ( Src1Idx == - 1 ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src1Idx ) , Desc . OpInfo [ Src1Idx ] ) ) return isVOP3 ( MI ) ? 12 : ( DescSize + 4 ) ; int Src2Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src2 ) ; if ( Src2Idx == - 1 ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src2Idx ) , Desc . OpInfo [ Src2Idx ] ) ) return isVOP3 ( MI ) ? 12 : ( DescSize + 4 ) ; return DescSize ; } if ( isMIMG ( MI ) ) { int VAddr0Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: vaddr0 ) ; if ( VAddr0Idx < 0 ) return 8 ; int RSrcIdx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: srsrc ) ; return 8 + 4 * ( ( RSrcIdx - VAddr0Idx + 2 ) / 4 ) ; } switch ( Opc ) { case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : case TargetOpcode :: EH_LABEL : return 0 ; case TargetOpcode :: BUNDLE : return getInstBundleSize ( MI ) ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) , & ST ) ; } default : return DescSize ; } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> static bool cbranch_predicted_p ( rtx_insn * insn ) { rtx x = find_reg_note ( insn , REG_BR_PROB , 0 ) ; if ( x ) { return profile_probability :: from_reg_br_prob_note ( XINT ( x , 0 ) ) >= profile_probability :: even ( ) ; } return false ; } </s>

Return true if INSN is annotated with a REG_BR_PROB note that indicates it 's a branch that 's predicted taken .


<s> bool isMem ( ) const override { return false ; } </s>


<s> static bool s390_hard_fp_reg_p ( rtx x ) { if ( ! ( REG_P ( x ) && HARD_REGISTER_P ( x ) && REG_ATTRS ( x ) ) ) return false ; tree decl = REG_EXPR ( x ) ; if ( ! ( HAS_DECL_ASSEMBLER_NAME_P ( decl ) && DECL_ASSEMBLER_NAME_SET_P ( decl ) ) ) return false ; const char * name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; return name [ 0 ] == '*' && name [ 1 ] == 'f' ; } </s>

Return TRUE iff X is a hard floating-point ( and not a vector ) register .


<s> static rtx microblaze_function_arg ( cumulative_args_t cum_v , machine_mode mode , const_tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; rtx ret ; int regbase = - 1 ; int * arg_words = & cum -> arg_words ; cum -> last_arg_fp = 0 ; switch ( mode ) { case E_SFmode : case E_DFmode : case E_VOIDmode : case E_QImode : case E_HImode : case E_SImode : case E_DImode : case E_TImode : regbase = GP_ARG_FIRST ; break ; default : gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_INT || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) ; case E_BLKmode : regbase = GP_ARG_FIRST ; break ; } if ( * arg_words >= MAX_ARGS_IN_REGISTERS ) ret = 0 ; else { gcc_assert ( regbase != - 1 ) ; ret = gen_rtx_REG ( mode , regbase + * arg_words ) ; } if ( mode == VOIDmode ) { if ( cum -> num_adjusts > 0 ) ret = gen_rtx_PARALLEL ( ( machine_mode ) cum -> fp_code , gen_rtvec_v ( cum -> num_adjusts , cum -> adjust ) ) ; } return ret ; } </s>

Return an RTL expression containing the register for the given mode , or 0 if the argument is to be passed on the stack .


<s>
void
ia64_start_function
(
FILE
*
file
,
const
char
*
fnname
,
tree
decl
ATTRIBUTE_UNUSED
)
{
vms_start_function
(
fnname
)
;
fputs
(
"\t.proc "
,
file
)
;
assemble_name
(
file
,
fnname
)
;
fputc
(
'\n'
,
file
)
;
ASM_OUTPUT_LABEL
(
file
,
fnname
)
;
}
</s>

Output the textual info surrounding the prologue .


<s>
bool
SITargetLowering
::
isLegalAddressingMode
(
const
DataLayout
&
DL
,
const
AddrMode
&
AM
,
Type
*
Ty
,
unsigned
AS
,
Instruction
*
I
)
const
{
if
(
AM
.
BaseGV
)
return
false
;
if
(
AS
==
AMDGPUASI
.
GLOBAL_ADDRESS
)
return
isLegalGlobalAddressingMode
(
AM
)
;
if
(
AS
==
AMDGPUASI
.
CONSTANT_ADDRESS
||
AS
==
AMDGPUASI
.
CONSTANT_ADDRESS_32BIT
)
{
if
(
AM
.
BaseOffs
%
4
!=
0
)
return
isLegalMUBUFAddressingMode
(
AM
)
;
if
(
Ty
->
isSized
(
)
&&
DL
.
getTypeStoreSize
(
Ty
)
<
4
)
return
isLegalGlobalAddressingMode
(
AM
)
;
if
(
Subtarget
->
getGeneration
(
)
==
AMDGPUSubtarget
::
SOUTHERN_ISLANDS
)
{
if
(
!
isUInt
<
8
>
(
AM
.
BaseOffs
/
4
)
)
return
false
;
}
else
if
(
Subtarget
->
getGeneration
(
)
==
AMDGPUSubtarget
::
SEA_ISLANDS
)
{
if
(
!
isUInt
<
32
>
(
AM
.
BaseOffs
/
4
)
)
return
false
;
}
else
if
(
Subtarget
->
getGeneration
(
)
>=
AMDGPUSubtarget
::
VOLCANIC_ISLANDS
)
{
if
(
!
isUInt
<
20
>
(
AM
.
BaseOffs
)
)
return
false
;
}
else
llvm_unreachable
(
"unhandled generation"
)
;
if
(
AM
.
Scale
==
0
)
return
true
;
if
(
AM
.
Scale
==
1
&&
AM
.
HasBaseReg
)
return
true
;
return
false
;
}
else
if
(
AS
==
AMDGPUASI
.
PRIVATE_ADDRESS
)
{
return
isLegalMUBUFAddressingMode
(
AM
)
;
}
else
if
(
AS
==
AMDGPUASI
.
LOCAL_ADDRESS
||
AS
==
AMDGPUASI
.
REGION_ADDRESS
)
{
if
(
!
isUInt
<
16
>
(
AM
.
BaseOffs
)
)
return
false
;
if
(
AM
.
Scale
==
0
)
return
true
;
if
(
AM
.
Scale
==
1
&&
AM
.
HasBaseReg
)
return
true
;
return
false
;
}
else
if
(
AS
==
AMDGPUASI
.
FLAT_ADDRESS
||
AS
==
AMDGPUASI
.
UNKNOWN_ADDRESS_SPACE
)
{
return
isLegalFlatAddressingMode
(
AM
)
;
}
else
{
llvm_unreachable
(
"unhandled address space"
)
;
}
}
</s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> bool AArch64FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * RegInfo , std :: vector < CalleeSavedInfo > & CSI , unsigned & MinCSFrameIndex , unsigned & MaxCSFrameIndex ) const { bool NeedsWinCFI = needsWinCFI ( MF ) ; if ( NeedsWinCFI ) std :: reverse ( CSI . begin ( ) , CSI . end ( ) ) ; if ( CSI . empty ( ) ) return true ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto AFI = MF . getInfo < AArch64FunctionInfo > ( ) ; for ( auto & CS : CSI ) { unsigned Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = RegInfo -> getMinimalPhysRegClass ( Reg ) ; int FrameIdx ; unsigned Size = RegInfo -> getSpillSize ( * RC ) ; Align Alignment ( RegInfo -> getSpillAlignment ( * RC ) ) ; FrameIdx = MFI . CreateStackObject ( Size , Alignment , true ) ; CS . setFrameIdx ( FrameIdx ) ; if ( ( unsigned ) FrameIdx < MinCSFrameIndex ) MinCSFrameIndex = FrameIdx ; if ( ( unsigned ) FrameIdx > MaxCSFrameIndex ) MaxCSFrameIndex = FrameIdx ; if ( hasFP ( MF ) && AFI -> hasSwiftAsyncContext ( ) && Reg == AArch64 :: FP ) { FrameIdx = MFI . CreateStackObject ( 8 , Alignment , true ) ; AFI -> setSwiftAsyncContextFrameIdx ( FrameIdx ) ; if ( ( unsigned ) FrameIdx < MinCSFrameIndex ) MinCSFrameIndex = FrameIdx ; if ( ( unsigned ) FrameIdx > MaxCSFrameIndex ) MaxCSFrameIndex = FrameIdx ; } } return true ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> int xstormy16_interrupt_function_p ( void ) { tree attributes ; if ( ! cfun ) return 0 ; attributes = TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ; return lookup_attribute ( "interrupt" , attributes ) != NULL_TREE ; } </s>

Return nonzero if the function is an interrupt function .


Do whatever processing is required at the end of a file .


<s> bool ARMFrameLowering :: enableShrinkWrapping ( const MachineFunction & MF ) const { if ( MF . getFunction ( ) . hasMinSize ( ) ) return false ; return true ; } </s>

Returns true if the target will correctly handle shrink wrapping .


<s> static bool rs6000_maybe_emit_fp_cmove ( rtx dest , rtx op , rtx true_cond , rtx false_cond ) { enum rtx_code code = GET_CODE ( op ) ; rtx op0 = XEXP ( op , 0 ) ; rtx op1 = XEXP ( op , 1 ) ; machine_mode result_mode = GET_MODE ( dest ) ; rtx compare_rtx ; rtx cmove_rtx ; rtx clobber_rtx ; if ( ! can_create_pseudo_p ( ) ) return 0 ; switch ( code ) { case EQ : case GE : case GT : break ; case NE : case LT : case LE : code = swap_condition ( code ) ; std :: swap ( op0 , op1 ) ; break ; default : return false ; } compare_rtx = gen_rtx_fmt_ee ( code , CCFPmode , op0 , op1 ) ; cmove_rtx = gen_rtx_SET ( dest , gen_rtx_IF_THEN_ELSE ( result_mode , compare_rtx , true_cond , false_cond ) ) ; clobber_rtx = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_SCRATCH ( V2DImode ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , cmove_rtx , clobber_rtx ) ) ) ; return true ; } </s>

Possibly emit a floating point conditional move by generating a compare that sets a mask instruction and a XXSEL select instruction . Move TRUE_COND to DEST if OP of the operands of the last comparison is nonzero/true , FALSE_COND if it is zero/false . Return false if the operation can not be generated , and true if we could generate the instruction .


<s>
StringRef
AArch64MCExpr
::
getVariantKindName
(
)
const
{
switch
(
static_cast
<
uint32_t
>
(
getKind
(
)
)
)
{
case
VK_CALL
:
return
""
;
case
VK_LO12
:
return
":lo12:"
;
case
VK_ABS_G3
:
return
":abs_g3:"
;
case
VK_ABS_G2
:
return
":abs_g2:"
;
case
VK_ABS_G2_S
:
return
":abs_g2_s:"
;
case
VK_ABS_G2_NC
:
return
":abs_g2_nc:"
;
case
VK_ABS_G1
:
return
":abs_g1:"
;
case
VK_ABS_G1_S
:
return
":abs_g1_s:"
;
case
VK_ABS_G1_NC
:
return
":abs_g1_nc:"
;
case
VK_ABS_G0
:
return
":abs_g0:"
;
case
VK_ABS_G0_S
:
return
":abs_g0_s:"
;
case
VK_ABS_G0_NC
:
return
":abs_g0_nc:"
;
case
VK_PREL_G3
:
return
":prel_g3:"
;
case
VK_PREL_G2
:
return
":prel_g2:"
;
case
VK_PREL_G2_NC
:
return
":prel_g2_nc:"
;
case
VK_PREL_G1
:
return
":prel_g1:"
;
case
VK_PREL_G1_NC
:
return
":prel_g1_nc:"
;
case
VK_PREL_G0
:
return
":prel_g0:"
;
case
VK_PREL_G0_NC
:
return
":prel_g0_nc:"
;
case
VK_DTPREL_G2
:
return
":dtprel_g2:"
;
case
VK_DTPREL_G1
:
return
":dtprel_g1:"
;
case
VK_DTPREL_G1_NC
:
return
":dtprel_g1_nc:"
;
case
VK_DTPREL_G0
:
return
":dtprel_g0:"
;
case
VK_DTPREL_G0_NC
:
return
":dtprel_g0_nc:"
;
case
VK_DTPREL_HI12
:
return
":dtprel_hi12:"
;
case
VK_DTPREL_LO12
:
return
":dtprel_lo12:"
;
case
VK_DTPREL_LO12_NC
:
return
":dtprel_lo12_nc:"
;
case
VK_TPREL_G2
:
return
":tprel_g2:"
;
case
VK_TPREL_G1
:
return
":tprel_g1:"
;
case
VK_TPREL_G1_NC
:
return
":tprel_g1_nc:"
;
case
VK_TPREL_G0
:
return
":tprel_g0:"
;
case
VK_TPREL_G0_NC
:
return
":tprel_g0_nc:"
;
case
VK_TPREL_HI12
:
return
":tprel_hi12:"
;
case
VK_TPREL_LO12
:
return
":tprel_lo12:"
;
case
VK_TPREL_LO12_NC
:
return
":tprel_lo12_nc:"
;
case
VK_TLSDESC_LO12
:
return
":tlsdesc_lo12:"
;
case
VK_ABS_PAGE
:
return
""
;
case
VK_ABS_PAGE_NC
:
return
":pg_hi21_nc:"
;
case
VK_GOT
:
return
":got:"
;
case
VK_GOT_PAGE
:
return
":got:"
;
case
VK_GOT_LO12
:
return
":got_lo12:"
;
case
VK_GOTTPREL
:
return
":gottprel:"
;
case
VK_GOTTPREL_PAGE
:
return
":gottprel:"
;
case
VK_GOTTPREL_LO12_NC
:
return
":gottprel_lo12:"
;
case
VK_GOTTPREL_G1
:
return
":gottprel_g1:"
;
case
VK_GOTTPREL_G0_NC
:
return
":gottprel_g0_nc:"
;
case
VK_TLSDESC
:
return
""
;
case
VK_TLSDESC_PAGE
:
return
":tlsdesc:"
;
case
VK_SECREL_LO12
:
return
":secrel_lo12:"
;
case
VK_SECREL_HI12
:
return
":secrel_hi12:"
;
default
:
llvm_unreachable
(
"Invalid ELF symbol kind"
)
;
}
}
</s>

Convert the variant kind into an ELF-appropriate modifier ( e.g .


<s> unsigned stackAlignment ( ) const { return hasMips64 ( ) ? 16 : 8 ; } </s>

The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function .


<s> void i386_pe_record_exported_symbol ( const char * name , int is_data ) { struct export_list * p ; p = ( struct export_list * ) ggc_alloc ( sizeof * p ) ; p -> next = export_head ; p -> name = name ; p -> is_data = is_data ; export_head = p ; } </s>

Assemble an export symbol entry . We need to keep a list of these , so that we can output the export list at the end of the assembly . We used to output these export symbols in each function , but that causes problems with GNU ld when the sections are linkonce .


<s> void riscv_expand_float_scc ( rtx target , enum rtx_code code , rtx op0 , rtx op1 ) { riscv_emit_float_compare ( & code , & op0 , & op1 ) ; rtx cmp = riscv_force_binary ( word_mode , code , op0 , op1 ) ; riscv_emit_set ( target , lowpart_subreg ( SImode , cmp , word_mode ) ) ; } </s>

Like riscv_expand_int_scc , but for floating-point comparisons .


<s> bool aarch64_mask_and_shift_for_ubfiz_p ( scalar_int_mode mode , rtx mask , rtx shft_amnt ) { return CONST_INT_P ( mask ) && CONST_INT_P ( shft_amnt ) && INTVAL ( mask ) > 0 && UINTVAL ( shft_amnt ) < GET_MODE_BITSIZE ( mode ) && exact_log2 ( ( UINTVAL ( mask ) >> UINTVAL ( shft_amnt ) ) + 1 ) >= 0 && ( UINTVAL ( mask ) & ( ( HOST_WIDE_INT_1U << UINTVAL ( shft_amnt ) ) - 1 ) ) == 0 ; } </s>

Return true if the mask and a shift amount from an RTX of the form ( x < < SHFT_AMNT ) & MASK are valid to combine into a UBFIZ instruction of mode MODE . See the * andim_ashift < mode > _bfiz pattern .


<s> bool aarch64_stepped_int_parallel_p ( rtx op , int step ) { if ( GET_CODE ( op ) != PARALLEL || ! CONST_INT_P ( XVECEXP ( op , 0 , 0 ) ) ) return false ; unsigned HOST_WIDE_INT base = UINTVAL ( XVECEXP ( op , 0 , 0 ) ) ; for ( int i = 1 ; i < XVECLEN ( op , 0 ) ; ++ i ) if ( ! CONST_INT_P ( XVECEXP ( op , 0 , i ) ) || UINTVAL ( XVECEXP ( op , 0 , i ) ) != base + i * step ) return false ; return true ; } </s>

Return true if OP is a PARALLEL of CONST_INTs that form a linear series with step STEP .


<s> void HexagonAsmInstPrinter :: printRegName ( raw_ostream & O , unsigned RegNo ) const { RawPrinter -> printRegName ( O , RegNo ) ; } </s>


<s> static rtx promote_duplicated_reg ( machine_mode mode , rtx val ) { machine_mode valmode = GET_MODE ( val ) ; rtx tmp ; int nops = mode == DImode ? 3 : 2 ; gcc_assert ( mode == SImode || mode == DImode || val == const0_rtx ) ; if ( val == const0_rtx ) return copy_to_mode_reg ( mode , CONST0_RTX ( mode ) ) ; if ( CONST_INT_P ( val ) ) { HOST_WIDE_INT v = INTVAL ( val ) & 255 ; v |= v << 8 ; v |= v << 16 ; if ( mode == DImode ) v |= ( v << 16 ) << 16 ; return copy_to_mode_reg ( mode , gen_int_mode ( v , mode ) ) ; } if ( valmode == VOIDmode ) valmode = QImode ; if ( valmode != QImode ) val = gen_lowpart ( QImode , val ) ; if ( mode == QImode ) return val ; if ( ! TARGET_PARTIAL_REG_STALL ) nops -- ; if ( ix86_cost -> mult_init [ mode == DImode ? 3 : 2 ] + ix86_cost -> mult_bit * ( mode == DImode ? 8 : 4 ) <= ( ix86_cost -> shift_const + ix86_cost -> add ) * nops + ( COSTS_N_INSNS ( TARGET_PARTIAL_REG_STALL == 0 ) ) ) { rtx reg = convert_modes ( mode , QImode , val , true ) ; tmp = promote_duplicated_reg ( mode , const1_rtx ) ; return expand_simple_binop ( mode , MULT , reg , tmp , NULL , 1 , OPTAB_DIRECT ) ; } else { rtx reg = convert_modes ( mode , QImode , val , true ) ; if ( ! TARGET_PARTIAL_REG_STALL ) emit_insn ( gen_insv_1 ( mode , reg , reg ) ) ; else { tmp = expand_simple_binop ( mode , ASHIFT , reg , GEN_INT ( 8 ) , NULL , 1 , OPTAB_DIRECT ) ; reg = expand_simple_binop ( mode , IOR , reg , tmp , reg , 1 , OPTAB_DIRECT ) ; } tmp = expand_simple_binop ( mode , ASHIFT , reg , GEN_INT ( 16 ) , NULL , 1 , OPTAB_DIRECT ) ; reg = expand_simple_binop ( mode , IOR , reg , tmp , reg , 1 , OPTAB_DIRECT ) ; if ( mode == SImode ) return reg ; tmp = expand_simple_binop ( mode , ASHIFT , reg , GEN_INT ( 32 ) , NULL , 1 , OPTAB_DIRECT ) ; reg = expand_simple_binop ( mode , IOR , reg , tmp , reg , 1 , OPTAB_DIRECT ) ; return reg ; } } </s>

Helper function for memcpy . For QImode value 0xXY produce 0xXYXYXYXY of wide specified by MODE . This is essentially a * 0x10101010 , but we can do slightly better than synth_mult by unwinding the sequence by hand on CPUs with slow multiply .


<s> Register MINA32RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? MINA32 :: R11 : MINA32 :: SP ; } </s>


<s>
void
m32c_output_reg_push
(
FILE
*
s
,
int
regno
)
{
if
(
regno
==
FLG_REGNO
)
fprintf
(
s
,
"\tpushc\tflg\n"
)
;
else
fprintf
(
s
,
"\tpush.%c\t%s\n"
,
" bwll"
[
reg_push_size
(
regno
)
]
,
reg_names
[
regno
]
)
;
}
</s>

Implements ASM_OUTPUT_REG_PUSH . Control registers are pushed differently than general registers .


<s> bool LanaiInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { return false ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createMipsELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI ( OSType ) , IsLittle , Is64Bit ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> bool rx_fuse_in_memory_bitop ( rtx * operands , rtx_insn * curr_insn , rtx ( * gen_insn ) ( rtx , rtx ) ) { rtx op2_reg = SUBREG_P ( operands [ 2 ] ) ? SUBREG_REG ( operands [ 2 ] ) : operands [ 2 ] ; set_of_reg op2_def = rx_find_set_of_reg ( op2_reg , curr_insn , prev_nonnote_nondebug_insn_bb ) ; if ( op2_def . set_src == NULL_RTX || ! MEM_P ( op2_def . set_src ) || GET_MODE ( op2_def . set_src ) != QImode || ! rx_is_restricted_memory_address ( XEXP ( op2_def . set_src , 0 ) , GET_MODE ( op2_def . set_src ) ) || reg_used_between_p ( operands [ 2 ] , op2_def . insn , curr_insn ) || ! rx_reg_dead_or_unused_after_insn ( curr_insn , REGNO ( op2_reg ) ) ) return false ; rtx mem = op2_def . set_src ; if ( GET_CODE ( XEXP ( mem , 0 ) ) == POST_INC || GET_CODE ( XEXP ( mem , 0 ) ) == PRE_INC || GET_CODE ( XEXP ( mem , 0 ) ) == POST_DEC || GET_CODE ( XEXP ( mem , 0 ) ) == PRE_DEC ) return false ; rtx_insn * op0_use = rx_find_use_of_reg ( operands [ 0 ] , curr_insn , next_nonnote_nondebug_insn_bb ) ; if ( op0_use == NULL || ! ( GET_CODE ( PATTERN ( op0_use ) ) == SET && RX_REG_P ( XEXP ( PATTERN ( op0_use ) , 1 ) ) && reg_overlap_mentioned_p ( operands [ 0 ] , XEXP ( PATTERN ( op0_use ) , 1 ) ) && rtx_equal_p ( mem , XEXP ( PATTERN ( op0_use ) , 0 ) ) ) || ! rx_reg_dead_or_unused_after_insn ( op0_use , REGNO ( operands [ 0 ] ) ) || reg_set_between_p ( operands [ 2 ] , curr_insn , op0_use ) ) return false ; for ( rtx_insn * i = next_nonnote_nondebug_insn_bb ( op2_def . insn ) ; i != NULL && i != op0_use ; i = next_nonnote_nondebug_insn_bb ( i ) ) if ( volatile_insn_p ( PATTERN ( i ) ) || CALL_P ( i ) ) return false ; emit_insn ( gen_insn ( mem , gen_lowpart ( QImode , operands [ 1 ] ) ) ) ; set_insn_deleted ( op2_def . insn ) ; set_insn_deleted ( op0_use ) ; return true ; } </s>

Try to fuse the current bit-operation insn with the surrounding memory load and store .


<s> void sparc_d_target_versions ( void ) { if ( TARGET_64BIT ) d_add_builtin_version ( "SPARC64" ) ; else d_add_builtin_version ( "SPARC" ) ; if ( TARGET_V8PLUS ) d_add_builtin_version ( "SPARC_V8Plus" ) ; if ( TARGET_FPU ) { d_add_builtin_version ( "D_HardFloat" ) ; d_add_builtin_version ( "SPARC_HardFloat" ) ; } else { d_add_builtin_version ( "D_SoftFloat" ) ; d_add_builtin_version ( "SPARC_SoftFloat" ) ; } } </s>

Implement TARGET_D_CPU_VERSIONS for SPARC targets .


<s> int m32c_preferred_output_reload_class ( rtx x , int rclass ) { return m32c_preferred_reload_class ( x , rclass ) ; } </s>


<s> void aarch64_split_compare_and_swap ( rtx operands [ ] ) { rtx rval , mem , oldval , newval , scratch ; machine_mode mode ; bool is_weak ; rtx_code_label * label1 , * label2 ; rtx x , cond ; enum memmodel model ; rtx model_rtx ; rval = operands [ 0 ] ; mem = operands [ 1 ] ; oldval = operands [ 2 ] ; newval = operands [ 3 ] ; is_weak = ( operands [ 4 ] != const0_rtx ) ; model_rtx = operands [ 5 ] ; scratch = operands [ 7 ] ; mode = GET_MODE ( mem ) ; model = memmodel_from_int ( INTVAL ( model_rtx ) ) ; bool strong_zero_p = ! is_weak && oldval == const0_rtx ; label1 = NULL ; if ( ! is_weak ) { label1 = gen_label_rtx ( ) ; emit_label ( label1 ) ; } label2 = gen_label_rtx ( ) ; if ( is_mm_sync ( model ) ) aarch64_emit_load_exclusive ( mode , rval , mem , GEN_INT ( MEMMODEL_RELAXED ) ) ; else aarch64_emit_load_exclusive ( mode , rval , mem , model_rtx ) ; if ( strong_zero_p ) { if ( aarch64_track_speculation ) { rtx cc_reg = aarch64_gen_compare_reg ( NE , rval , const0_rtx ) ; x = gen_rtx_NE ( GET_MODE ( cc_reg ) , cc_reg , const0_rtx ) ; } else x = gen_rtx_NE ( VOIDmode , rval , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } else { cond = aarch64_gen_compare_reg_maybe_ze ( NE , rval , oldval , mode ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } aarch64_emit_store_exclusive ( mode , scratch , mem , newval , model_rtx ) ; if ( ! is_weak ) { if ( aarch64_track_speculation ) { rtx cc_reg = aarch64_gen_compare_reg ( NE , scratch , const0_rtx ) ; x = gen_rtx_NE ( GET_MODE ( cc_reg ) , cc_reg , const0_rtx ) ; } else x = gen_rtx_NE ( VOIDmode , scratch , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label1 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } else { cond = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_COMPARE ( CCmode , scratch , const0_rtx ) ; emit_insn ( gen_rtx_SET ( cond , x ) ) ; } emit_label ( label2 ) ; if ( strong_zero_p ) { cond = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_COMPARE ( CCmode , rval , const0_rtx ) ; emit_insn ( gen_rtx_SET ( cond , x ) ) ; } if ( is_mm_sync ( model ) ) aarch64_emit_post_barrier ( model ) ; } </s>


<s> tree loongarch_builtin_decl ( unsigned int code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= ARRAY_SIZE ( loongarch_builtins ) ) return error_mark_node ; return loongarch_builtin_decls [ code ] ; } </s>


<s>
static
bool
aarch64_validate_mtune
(
const
char
*
str
,
const
struct
processor
*
*
res
)
{
enum
aarch64_parse_opt_result
parse_res
=
aarch64_parse_tune
(
str
,
res
)
;
if
(
parse_res
==
AARCH64_PARSE_OK
)
return
true
;
switch
(
parse_res
)
{
case
AARCH64_PARSE_MISSING_ARG
:
error
(
"missing cpu name in -mtune=%qs"
,
str
)
;
break
;
case
AARCH64_PARSE_INVALID_ARG
:
error
(
"unknown value %qs for -mtune"
,
str
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
return
false
;
}
</s>

Validate a command-line -mtune option . Parse the cpu specified in STR and throw errors if appropriate . Put the result , if it is valid , in RES . Return whether the option is valid .

aarch64
"missing cpu name in -mtune=%qs"
"unknown value %qs for -mtune"


<s> void OpenRISCInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool ARM64TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( VT . getVectorNumElements ( ) == 4 && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ 4 ] ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { if ( M [ i ] < 0 ) PFIndexes [ i ] = 8 ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ 0 ] * 9 * 9 * 9 + PFIndexes [ 1 ] * 9 * 9 + PFIndexes [ 2 ] * 9 + PFIndexes [ 3 ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> 30 ) ; if ( Cost <= 4 ) return true ; } bool DummyBool ; int DummyInt ; unsigned DummyUnsigned ; return ( ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isREVMask ( M , VT , 64 ) || isREVMask ( M , VT , 32 ) || isREVMask ( M , VT , 16 ) || isEXTMask ( M , VT , DummyBool , DummyUnsigned ) || isTRNMask ( M , VT , DummyUnsigned ) || isUZPMask ( M , VT , DummyUnsigned ) || isZIPMask ( M , VT , DummyUnsigned ) || isTRN_v_undef_Mask ( M , VT , DummyUnsigned ) || isUZP_v_undef_Mask ( M , VT , DummyUnsigned ) || isZIP_v_undef_Mask ( M , VT , DummyUnsigned ) || isINSMask ( M , VT . getVectorNumElements ( ) , DummyBool , DummyInt ) || isConcatMask ( M , VT , VT . getSizeInBits ( ) == 128 ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> bool isMem ( ) const override { return false ; } </s>


<s> bool SIInstrInfo :: hasUnwantedEffectsWhenEXECEmpty ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( MI . mayStore ( ) && isSMRD ( MI ) ) return true ; if ( MI . isReturn ( ) ) return true ; if ( Opcode == AMDGPU :: S_SENDMSG || Opcode == AMDGPU :: S_SENDMSGHALT || Opcode == AMDGPU :: EXP || Opcode == AMDGPU :: EXP_DONE || Opcode == AMDGPU :: DS_ORDERED_COUNT || Opcode == AMDGPU :: S_TRAP || Opcode == AMDGPU :: DS_GWS_INIT || Opcode == AMDGPU :: DS_GWS_BARRIER ) return true ; if ( MI . isCall ( ) || MI . isInlineAsm ( ) ) return true ; if ( modifiesModeRegister ( MI ) ) return true ; if ( Opcode == AMDGPU :: V_READFIRSTLANE_B32 || Opcode == AMDGPU :: V_READLANE_B32 || Opcode == AMDGPU :: V_WRITELANE_B32 ) return true ; return false ; } </s>

Whether we must prevent this instruction from executing with EXEC = 0 .


<s> bool OR1KAsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> static void setup_incoming_varargs ( cumulative_args_t cum , machine_mode mode ATTRIBUTE_UNUSED , tree type ATTRIBUTE_UNUSED , int * pretend_size , int no_rtl ) { rtx mem ; int i ; if ( no_rtl ) return ; for ( i = get_cumulative_args ( cum ) -> words + 1 ; i < max_arg_registers ; i ++ ) { mem = gen_rtx_MEM ( Pmode , plus_constant ( Pmode , arg_pointer_rtx , ( i * UNITS_PER_WORD ) ) ) ; emit_move_insn ( mem , gen_rtx_REG ( Pmode , i ) ) ; } * pretend_size = 0 ; } </s>

Perform any needed actions needed for a function that is receiving a variable number of arguments . CUM is as above . MODE and TYPE are the mode and type of the current parameter . PRETEND_SIZE is a variable that should be set to the amount of stack that must be pushed by the prolog to pretend that our caller pushed it . Normally , this macro will push all remaining incoming registers on the stack and set PRETEND_SIZE to the length of the registers pushed .


"PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG."

"PRINT_OPERAND_ADDRESS, invalid insn #2"

"PRINT_OPERAND_ADDRESS, invalid insn #1"

A C compound statement to output to stdio stream STREAM the assembler syntax for an instruction operand that is a memory reference whose address is ADDR . ADDR is an RTL expression .


<s> AArch64TargetLowering :: ConstraintType AArch64TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'x' : case 'w' : case 'y' : return C_RegisterClass ; case 'Q' : return C_Memory ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'Y' : case 'Z' : return C_Immediate ; case 'z' : case 'S' : return C_Other ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> unsigned X86TTI :: getNumberOfRegisters ( bool Vector ) const { if ( Vector && ! ST -> hasSSE1 ( ) ) return 0 ; if ( ST -> is64Bit ( ) ) { if ( Vector && ST -> hasAVX512 ( ) ) return 32 ; return 16 ; } return 8 ; } </s>


<s> int use_return_insn ( int iscond , rtx sibling ) { int regno ; unsigned int func_type ; unsigned long saved_int_regs ; unsigned HOST_WIDE_INT stack_adjust ; arm_stack_offsets * offsets ; if ( ! reload_completed ) return 0 ; func_type = arm_current_func_type ( ) ; if ( func_type & ( ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN ) ) return 0 ; if ( IS_INTERRUPT ( func_type ) && ( frame_pointer_needed || TARGET_THUMB ) ) return 0 ; if ( TARGET_LDRD && current_tune -> prefer_ldrd_strd && ! optimize_function_for_size_p ( cfun ) ) return 0 ; offsets = arm_get_frame_offsets ( ) ; stack_adjust = offsets -> outgoing_args - offsets -> saved_regs ; if ( crtl -> args . pretend_args_size || cfun -> machine -> uses_anonymous_args || crtl -> calls_eh_return || cfun -> calls_alloca || ! ( stack_adjust == 0 || ( TARGET_APCS_FRAME && frame_pointer_needed && stack_adjust == 4 ) ) || ( ! ( TARGET_APCS_FRAME && frame_pointer_needed ) && arm_compute_static_chain_stack_bytes ( ) != 0 ) ) return 0 ; saved_int_regs = offsets -> saved_regs_mask ; if ( stack_adjust == 4 && ! arm_arch5t && TARGET_ARM ) { if ( ! call_used_regs [ 3 ] ) return 0 ; if ( arm_size_return_regs ( ) >= ( 4 * UNITS_PER_WORD ) ) return 0 ; if ( sibling ) { gcc_assert ( CALL_P ( sibling ) ) ; if ( find_regno_fusage ( sibling , USE , 3 ) ) return 0 ; } if ( saved_int_regs & 0x7 ) return 0 ; } if ( TARGET_INTERWORK && saved_int_regs != 0 && ! IS_INTERRUPT ( func_type ) ) return 0 ; if ( iscond && arm_tune_strongarm ) { if ( saved_int_regs != 0 && saved_int_regs != ( 1 << LR_REGNUM ) ) return 0 ; if ( flag_pic && arm_pic_register != INVALID_REGNUM && df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) ) return 0 ; } if ( saved_int_regs && IS_CMSE_ENTRY ( func_type ) ) return 0 ; if ( saved_int_regs && ! ( saved_int_regs & ( 1 << LR_REGNUM ) ) ) return 0 ; if ( TARGET_HARD_FLOAT ) for ( regno = FIRST_VFP_REGNUM ; regno <= LAST_VFP_REGNUM ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) return 0 ; if ( TARGET_REALLY_IWMMXT ) for ( regno = FIRST_IWMMXT_REGNUM ; regno <= LAST_IWMMXT_REGNUM ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) return 0 ; return 1 ; } </s>

Return true if this function 's epilogue can be output as RTL .


<s> bool HexagonTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( AM . BaseOffs <= - ( 1LL << 13 ) || AM . BaseOffs >= ( 1LL << 13 ) - 1 ) return false ; if ( AM . BaseGV ) return false ; int Scale = AM . Scale ; if ( Scale < 0 ) Scale = - Scale ; switch ( Scale ) { case 0 : break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s>
static
void
ia64_output_function_prologue
(
FILE
*
file
)
{
int
mask
,
grsave
,
grsave_prev
;
if
(
current_frame_info
.
need_regstk
)
fprintf
(
file
,
"\t.regstk %d, %d, %d, %d\n"
,
current_frame_info
.
n_input_regs
,
current_frame_info
.
n_local_regs
,
current_frame_info
.
n_output_regs
,
current_frame_info
.
n_rotate_regs
)
;
if
(
ia64_except_unwind_info
(
&
global_options
)
!=
UI_TARGET
)
return
;
mask
=
0
;
grsave
=
grsave_prev
=
0
;
if
(
current_frame_info
.
r
[
reg_save_b0
]
!=
0
)
{
mask
|=
8
;
grsave
=
grsave_prev
=
current_frame_info
.
r
[
reg_save_b0
]
;
}
if
(
current_frame_info
.
r
[
reg_save_ar_pfs
]
!=
0
&&
(
grsave_prev
==
0
||
current_frame_info
.
r
[
reg_save_ar_pfs
]
==
grsave_prev
+
1
)
)
{
mask
|=
4
;
if
(
grsave_prev
==
0
)
grsave
=
current_frame_info
.
r
[
reg_save_ar_pfs
]
;
grsave_prev
=
current_frame_info
.
r
[
reg_save_ar_pfs
]
;
}
if
(
current_frame_info
.
r
[
reg_fp
]
!=
0
&&
(
grsave_prev
==
0
||
current_frame_info
.
r
[
reg_fp
]
==
grsave_prev
+
1
)
)
{
mask
|=
2
;
if
(
grsave_prev
==
0
)
grsave
=
HARD_FRAME_POINTER_REGNUM
;
grsave_prev
=
current_frame_info
.
r
[
reg_fp
]
;
}
if
(
current_frame_info
.
r
[
reg_save_pr
]
!=
0
&&
(
grsave_prev
==
0
||
current_frame_info
.
r
[
reg_save_pr
]
==
grsave_prev
+
1
)
)
{
mask
|=
1
;
if
(
grsave_prev
==
0
)
grsave
=
current_frame_info
.
r
[
reg_save_pr
]
;
}
if
(
mask
&&
TARGET_GNU_AS
)
fprintf
(
file
,
"\t.prologue %d, %d\n"
,
mask
,
ia64_dbx_register_number
(
grsave
)
)
;
else
fputs
(
"\t.prologue\n"
,
file
)
;
if
(
current_frame_info
.
spill_cfa_off
!=
16
)
fprintf
(
file
,
"\t.spill %ld\n"
,
(
long
)
(
current_frame_info
.
spill_cfa_off
+
current_frame_info
.
spill_size
)
)
;
}
</s>


<s> TargetPassConfig * ARM64TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new ARM64PassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> static void spu_output_mi_thunk ( FILE * file , tree thunk ATTRIBUTE_UNUSED , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { rtx op [ 8 ] ; final_start_function ( emit_barrier ( ) , file , 1 ) ; op [ 0 ] = XEXP ( DECL_RTL ( function ) , 0 ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) op [ 1 ] = gen_rtx_REG ( Pmode , FIRST_ARG_REGNUM + 1 ) ; else op [ 1 ] = gen_rtx_REG ( Pmode , FIRST_ARG_REGNUM ) ; op [ 2 ] = GEN_INT ( trunc_int_for_mode ( delta , HImode ) ) ; op [ 3 ] = GEN_INT ( trunc_int_for_mode ( delta >> 16 , HImode ) ) ; op [ 4 ] = GEN_INT ( trunc_int_for_mode ( vcall_offset , HImode ) ) ; op [ 5 ] = GEN_INT ( trunc_int_for_mode ( vcall_offset >> 16 , HImode ) ) ; op [ 6 ] = gen_rtx_REG ( Pmode , 79 ) ; op [ 7 ] = gen_rtx_REG ( Pmode , 78 ) ; if ( delta ) { if ( delta >= - 0x200 && delta < 0x200 ) output_asm_insn ( "ai\t%1,%1,%2" , op ) ; else if ( delta >= - 0x8000 && delta < 0x8000 ) { output_asm_insn ( "il\t%6,%2" , op ) ; output_asm_insn ( "a\t%1,%1,%6" , op ) ; } else { output_asm_insn ( "ilhu\t%6,%3" , op ) ; output_asm_insn ( "iohl\t%6,%2" , op ) ; output_asm_insn ( "a\t%1,%1,%6" , op ) ; } } if ( vcall_offset ) { output_asm_insn ( "lqd\t%7,0(%1)" , op ) ; output_asm_insn ( "rotqby\t%7,%7,%1" , op ) ; if ( vcall_offset >= - 0x200 && vcall_offset < 0x200 ) output_asm_insn ( "ai\t%7,%7,%4" , op ) ; else if ( vcall_offset >= - 0x8000 && vcall_offset < 0x8000 ) { output_asm_insn ( "il\t%6,%4" , op ) ; output_asm_insn ( "a\t%7,%7,%6" , op ) ; } else { output_asm_insn ( "ilhu\t%6,%5" , op ) ; output_asm_insn ( "iohl\t%6,%4" , op ) ; output_asm_insn ( "a\t%7,%7,%6" , op ) ; } output_asm_insn ( "lqd\t%6,0(%7)" , op ) ; output_asm_insn ( "rotqby\t%6,%6,%7" , op ) ; output_asm_insn ( "a\t%1,%1,%6" , op ) ; } output_asm_insn ( "br\t%0" , op ) ; final_end_function ( ) ; } </s>

Output thunk to FILE that implements a C++ virtual function call ( with multiple inheritance ) to FUNCTION . The thunk adjusts the this pointer by DELTA , and unless VCALL_OFFSET is zero , applies an additional adjustment stored at VCALL_OFFSET in the vtable whose address is located at offset 0 relative to the resulting this pointer .


<s> static int aarch64_reduc_type ( vec_info * vinfo , stmt_vec_info stmt_info ) { if ( loop_vec_info loop_vinfo = dyn_cast < loop_vec_info > ( vinfo ) ) if ( STMT_VINFO_REDUC_DEF ( stmt_info ) ) { stmt_vec_info reduc_info = info_for_reduction ( loop_vinfo , stmt_info ) ; return int ( STMT_VINFO_REDUC_TYPE ( reduc_info ) ) ; } return - 1 ; } </s>

If STMT_INFO describes a reduction , return the type of reduction it describes , otherwise return -1 .


<s>
StringRef
getPassName
(
)
const
override
{
return
"AAP Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static bool arm_mem_costs ( rtx x , const struct cpu_cost_table * extra_cost , int * cost , bool speed_p ) { machine_mode mode = GET_MODE ( x ) ; * cost = COSTS_N_INSNS ( 1 ) ; if ( flag_pic && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && will_be_in_index_register ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ) * cost += COSTS_N_INSNS ( 1 ) ; if ( speed_p ) { arm_addr_mode_op op_type ; switch ( GET_CODE ( XEXP ( x , 0 ) ) ) { default : case REG : op_type = AMO_DEFAULT ; break ; case MINUS : case PLUS : op_type = AMO_NO_WB ; break ; case PRE_INC : case PRE_DEC : case POST_INC : case POST_DEC : case PRE_MODIFY : case POST_MODIFY : op_type = AMO_WB ; break ; } if ( VECTOR_MODE_P ( mode ) ) * cost += current_tune -> addr_mode_costs -> vector [ op_type ] ; else if ( FLOAT_MODE_P ( mode ) ) * cost += current_tune -> addr_mode_costs -> fp [ op_type ] ; else * cost += current_tune -> addr_mode_costs -> integer [ op_type ] ; } if ( speed_p ) { if ( FLOAT_MODE_P ( mode ) ) { if ( GET_MODE_SIZE ( mode ) == 8 ) * cost += extra_cost -> ldst . loadd ; else * cost += extra_cost -> ldst . loadf ; } else if ( VECTOR_MODE_P ( mode ) ) * cost += extra_cost -> ldst . loadv ; else { if ( GET_MODE_SIZE ( mode ) == 8 ) * cost += extra_cost -> ldst . ldrd ; else * cost += extra_cost -> ldst . load ; } } return true ; } </s>

Helper function for arm_rtx_costs_internal . Calculates the cost of a MEM , considering the costs of the addressing mode and memory access separately .


<s> unsigned getExplicitKernelArgOffset ( const MachineFunction & MF ) const { return 36 ; } </s>

Returns the offset in bytes from the start of the input buffer of the first explicit kernel argument .


<s> bool AArch64CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; bool Split = false ; LLT Ty = MRI . getType ( VRegs [ i ] ) ; unsigned Dst = VRegs [ i ] ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( unsigned Reg , uint64_t Offset ) { if ( ! Split ) { Split = true ; Dst = MRI . createGenericVirtualRegister ( Ty ) ; MIRBuilder . buildUndef ( Dst ) ; } unsigned Tmp = MRI . createGenericVirtualRegister ( Ty ) ; MIRBuilder . buildInsert ( Tmp , Dst , Reg , Offset ) ; Dst = Tmp ; } ) ; if ( Dst != VRegs [ i ] ) MIRBuilder . buildCopy ( VRegs [ i ] , Dst ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; if ( F . isVarArg ( ) ) { if ( ! MF . getSubtarget < AArch64Subtarget > ( ) . isTargetDarwin ( ) ) { return false ; } uint64_t StackOffset = alignTo ( Handler . StackUsed , 8 ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; AArch64FunctionInfo * FuncInfo = MF . getInfo < AArch64FunctionInfo > ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( 4 , StackOffset , true ) ) ; } MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> virtual unsigned getCycles ( ) const { return NumCycles ; } </s>

Returns the number of cycles the stage is occupied .


<s> static bool sh_legitimize_address_displacement ( rtx * disp , rtx * offs , machine_mode mode ) { if ( TARGET_SHMEDIA ) return false ; if ( ( ( TARGET_SH4 || TARGET_SH2A_DOUBLE ) && mode == DFmode ) || ( TARGET_SH2E && mode == SFmode ) ) return false ; struct disp_adjust adj = sh_find_mov_disp_adjust ( mode , INTVAL ( * disp ) ) ; if ( adj . offset_adjust != NULL_RTX && adj . mov_disp != NULL_RTX ) { * disp = adj . mov_disp ; * offs = adj . offset_adjust ; return true ; } return false ; } </s>

Return true if DISP can be legitimized .


<s> const char * host_detect_local_cpu ( int argc , const char * * argv ) { const char * cpu = NULL ; char * buf = NULL ; kstat_ctl_t * kc ; kstat_t * ksp ; kstat_named_t * brand = NULL ; char buf [ 128 ] ; FILE * f ; int i ; if ( argc < 1 ) return NULL ; if ( strcmp ( argv [ 0 ] , "cpu" ) && strcmp ( argv [ 0 ] , "tune" ) ) return NULL ; kc = kstat_open ( ) ; if ( kc != NULL ) { ksp = kstat_lookup ( kc , CONST_CAST2 ( char * , const char * , "cpu_info" ) , - 1 , NULL ) ; if ( ksp != NULL && kstat_read ( kc , ksp , NULL ) != - 1 && ksp -> ks_type == KSTAT_TYPE_NAMED ) brand = ( kstat_named_t * ) kstat_data_lookup ( ksp , CONST_CAST2 ( char * , const char * , "brand" ) ) ; if ( brand == NULL ) brand = ( kstat_named_t * ) kstat_data_lookup ( ksp , CONST_CAST2 ( char * , const char * , "implementation" ) ) ; if ( brand != NULL && brand -> data_type == KSTAT_DATA_STRING ) buf = KSTAT_NAMED_STR_PTR ( brand ) ; if ( brand != NULL && brand -> data_type == KSTAT_DATA_CHAR ) buf = brand -> value . c ; } kstat_close ( kc ) ; for ( i = 0 ; cpu_names [ i ] . name != NULL ; i ++ ) if ( strcmp ( buf , cpu_names [ i ] . name ) == 0 ) cpu = cpu_names [ i ] . cpu ; f = fopen ( "/proc/cpuinfo" , "r" ) ; if ( f == NULL ) return NULL ; while ( fgets ( buf , sizeof ( buf ) , f ) != NULL ) if ( strncmp ( buf , "cpu\t\t:" , sizeof ( "cpu\t\t:" ) - 1 ) == 0 ) { for ( i = 0 ; cpu_names [ i ] . name ; i ++ ) if ( strstr ( buf , cpu_names [ i ] . name ) != NULL ) { cpu = cpu_names [ i ] . cpu ; break ; } break ; } fclose ( f ) ; if ( cpu == NULL ) return NULL ; return concat ( "-m" , argv [ 0 ] , "=" , cpu , NULL ) ; } </s>

This will be called by the spec parser in gcc.cc when it sees a % : local_cpu_detect ( args ) construct . Currently it will be called with either `` cpu '' or `` tune '' as argument depending on if -mcpu=native or -mtune=native is to be substituted . It returns a string containing new command line parameters to be put at the place of the above two options , depending on what CPU this is executed . E.g . `` -mcpu=ultrasparc3 '' on an UltraSPARC III for -mcpu=native . If the routine ca n't detect a known processor , the -mcpu or -mtune option is discarded . ARGC and ARGV are set depending on the actual arguments given in the spec .


<s>
TargetTransformInfo
::
PopcntSupportKind
WebAssemblyTTIImpl
::
getPopcntSupport
(
unsigned
TyWidth
)
{
assert
(
isPowerOf2_32
(
TyWidth
)
&&
"Ty width must be power of 2"
)
;
return
TTI
::
PSK_Software
;
}
</s>

Return hardware support for population count .

WebAssembly
WebAssembly
"Ty width must be power of 2"


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> bool lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) const { return MCInstLowering . lowerOperand ( MO , MCOp ) ; } </s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> void XCoreInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = * MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ; BuildMI ( MBB , I , DL , get ( XCore :: STWFI ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) . addMemOperand ( MMO ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool HexagonAsmParser :: parseExpression ( MCExpr const * & Expr ) { llvm :: SmallVector < AsmToken , 4 > Tokens ; MCAsmLexer & Lexer = getLexer ( ) ; bool Done = false ; static char const * Comma = "," ; do { Tokens . emplace_back ( Lexer . getTok ( ) ) ; Lexer . Lex ( ) ; switch ( Tokens . back ( ) . getKind ( ) ) { case AsmToken :: TokenKind :: Hash : if ( Tokens . size ( ) > 1 ) if ( ( Tokens . end ( ) - 2 ) -> getKind ( ) == AsmToken :: TokenKind :: Plus ) { Tokens . insert ( Tokens . end ( ) - 2 , AsmToken ( AsmToken :: TokenKind :: Comma , Comma ) ) ; Done = true ; } break ; case AsmToken :: TokenKind :: RCurly : case AsmToken :: TokenKind :: EndOfStatement : case AsmToken :: TokenKind :: Eof : Done = true ; break ; default : break ; } } while ( ! Done ) ; while ( ! Tokens . empty ( ) ) { Lexer . UnLex ( Tokens . back ( ) ) ; Tokens . pop_back ( ) ; } return getParser ( ) . parseExpression ( Expr ) ; } </s>


<s>
CCAssignFn
*
R600TargetLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
const
{
switch
(
CC
)
{
case
CallingConv
::
AMDGPU_KERNEL
:
case
CallingConv
::
SPIR_KERNEL
:
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
case
CallingConv
::
Cold
:
return
CC_R600_Kernel
;
case
CallingConv
::
AMDGPU_VS
:
case
CallingConv
::
AMDGPU_GS
:
case
CallingConv
::
AMDGPU_PS
:
case
CallingConv
::
AMDGPU_CS
:
case
CallingConv
::
AMDGPU_HS
:
case
CallingConv
::
AMDGPU_ES
:
case
CallingConv
::
AMDGPU_LS
:
return
CC_R600
;
default
:
report_fatal_error
(
"Unsupported calling convention."
)
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .

AMDGPU
R600
AMDGPU
R600
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
R600
"Unsupported calling convention."


<s> unsigned MipsTargetLowering :: getJumpTableEncoding ( ) const { if ( ABI . IsCheriPureCap ( ) ) return MachineJumpTableInfo :: EK_LabelDifference32 ; if ( ABI . IsN64 ( ) && isPositionIndependent ( ) ) return MachineJumpTableInfo :: EK_GPRel64BlockAddress ; return TargetLowering :: getJumpTableEncoding ( ) ; } </s>

Return the entry encoding for a jump table in the current function .


<s> unsigned Mips16InstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> int mem_min_alignment ( rtx mem , int desired ) { rtx addr , base , offset ; if ( GET_CODE ( mem ) != MEM ) return 0 ; if ( ! TARGET_UNALIGNED_DOUBLES && MEM_ALIGN ( mem ) / BITS_PER_UNIT >= ( unsigned ) desired ) return 1 ; addr = XEXP ( mem , 0 ) ; base = offset = NULL_RTX ; if ( GET_CODE ( addr ) == PLUS ) { if ( GET_CODE ( XEXP ( addr , 0 ) ) == REG ) { base = XEXP ( addr , 0 ) ; if ( GET_CODE ( XEXP ( addr , 1 ) ) == CONST_INT ) offset = XEXP ( addr , 1 ) ; else offset = const0_rtx ; } } else if ( GET_CODE ( addr ) == REG ) { base = addr ; offset = const0_rtx ; } if ( base != NULL_RTX ) { int regno = REGNO ( base ) ; if ( regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM ) { if ( ( ( cfun != 0 && REGNO_POINTER_ALIGN ( regno ) >= desired * BITS_PER_UNIT ) || ( optimize && reload_completed ) ) && ( INTVAL ( offset ) & ( desired - 1 ) ) == 0 ) return 1 ; } else { if ( ( ( INTVAL ( offset ) - SPARC_STACK_BIAS ) & ( desired - 1 ) ) == 0 ) return 1 ; } } else if ( ! TARGET_UNALIGNED_DOUBLES || CONSTANT_P ( addr ) || GET_CODE ( addr ) == LO_SUM ) { return 1 ; } return 0 ; } </s>

Return 1 if RTX is a MEM which is known to be aligned to at least a DESIRED byte boundary .


<s> const CAHPRegisterInfo * getRegisterInfo ( ) const override { return & RegInfo ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> AMDGPUMCObjectWriter * AMDGPUAsmBackend :: createObjectWriter ( raw_ostream & OS ) const { return new AMDGPUMCObjectWriter ( OS ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> AArch64Subtarget & AArch64Subtarget :: initializeSubtargetDependencies ( StringRef FS , StringRef CPUString ) { if ( CPUString . empty ( ) ) CPUString = "generic" ; ParseSubtargetFeatures ( CPUString , CPUString , FS ) ; initializeProperties ( ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool Nios2AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> ARMConstantPoolSymbol * ARMConstantPoolSymbol :: Create ( LLVMContext & C , StringRef s , ARMCP :: ARMCPModifier Modifier ) { return new ARMConstantPoolSymbol ( C , s , 0 , 0 , Modifier , false ) ; } </s>

Construct a unary instruction , given the opcode and an operand .

ARM ARM ARM ARMCP::ARMCPModifier ARM 0 0


<s> const CSKYInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> void expand ( enum insn_code icode , bool temporary_volatile_p = false ) { if ( temporary_volatile_p ) { temporary_volatile_ok v ( true ) ; expand_insn ( icode , m_opno , m_ops ) ; } else expand_insn ( icode , m_opno , m_ops ) ; } </s>


<s> bool HexagonBitSimplify :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; auto & HST = MF . getSubtarget < HexagonSubtarget > ( ) ; auto & HRI = * HST . getRegisterInfo ( ) ; auto & HII = * HST . getInstrInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool Changed ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) ; const HexagonEvaluator HE ( HRI , MRI , HII , MF ) ; BitTracker BT ( HE , MF ) ; DEBUG ( BT . trace ( true ) ) ; BT . run ( ) ; MachineBasicBlock & Entry = MF . front ( ) ; RegisterSet AIG ; ConstGeneration ImmG ( BT , HII , MRI ) ; Changed |= visitBlock ( Entry , ImmG , AIG ) ; RegisterSet ARE ; RedundantInstrElimination RIE ( BT , HII , MRI ) ; bool Ried = visitBlock ( Entry , RIE , ARE ) ; if ( Ried ) { Changed = true ; BT . run ( ) ; } RegisterSet ACG ; CopyGeneration CopyG ( BT , HII , MRI ) ; Changed |= visitBlock ( Entry , CopyG , ACG ) ; RegisterSet ACP ; CopyPropagation CopyP ( HRI , MRI ) ; Changed |= visitBlock ( Entry , CopyP , ACP ) ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) || Changed ; BT . run ( ) ; RegisterSet ABS ; BitSimplification BitS ( BT , HII , MRI ) ; Changed |= visitBlock ( Entry , BitS , ABS ) ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) || Changed ; if ( Changed ) { for ( auto & B : MF ) for ( auto & I : B ) I . clearKillInfo ( ) ; DeadCodeElimination ( MF , * MDT ) . run ( ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool PPCTargetLowering :: SelectAddressRegImm34 ( SDValue N , SDValue & Disp , SDValue & Base , SelectionDAG & DAG ) const { if ( N . getValueType ( ) != MVT :: i64 ) return false ; SDLoc dl ( N ) ; int64_t Imm = 0 ; if ( N . getOpcode ( ) == ISD :: ADD ) { if ( ! isIntS34Immediate ( N . getOperand ( 1 ) , Imm ) ) return false ; Disp = DAG . getTargetConstant ( Imm , dl , N . getValueType ( ) ) ; if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( N . getOperand ( 0 ) ) ) Base = DAG . getTargetFrameIndex ( FI -> getIndex ( ) , N . getValueType ( ) ) ; else Base = N . getOperand ( 0 ) ; return true ; } if ( N . getOpcode ( ) == ISD :: OR ) { if ( ! isIntS34Immediate ( N . getOperand ( 1 ) , Imm ) ) return false ; KnownBits LHSKnown = DAG . computeKnownBits ( N . getOperand ( 0 ) ) ; if ( ( LHSKnown . Zero . getZExtValue ( ) | ~ ( uint64_t ) Imm ) != ~ 0ULL ) return false ; if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( N . getOperand ( 0 ) ) ) Base = DAG . getTargetFrameIndex ( FI -> getIndex ( ) , N . getValueType ( ) ) ; else Base = N . getOperand ( 0 ) ; Disp = DAG . getTargetConstant ( Imm , dl , N . getValueType ( ) ) ; return true ; } if ( isIntS34Immediate ( N , Imm ) ) { Disp = DAG . getTargetConstant ( Imm , dl , N . getValueType ( ) ) ; Base = DAG . getRegister ( PPC :: ZERO8 , N . getValueType ( ) ) ; return true ; } return false ; } </s>

Similar to the 16-bit case but for instructions that take a 34-bit displacement field ( prefixed loads/stores ) .


<s> BitVector SIRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AMDGPU :: INDIRECT_BASE_ADDR ) ; reserveRegisterTuples ( Reserved , AMDGPU :: EXEC ) ; reserveRegisterTuples ( Reserved , AMDGPU :: FLAT_SCR ) ; if ( MF . getSubtarget < AMDGPUSubtarget > ( ) . hasSGPRInitBug ( ) ) { unsigned NumSGPRs = AMDGPU :: SGPR_32RegClass . getNumRegs ( ) ; unsigned Limit = AMDGPUSubtarget :: FIXED_SGPR_COUNT_FOR_INIT_BUG - 4 ; for ( unsigned i = Limit ; i < NumSGPRs ; ++ i ) { unsigned Reg = AMDGPU :: SGPR_32RegClass . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
SDValue
AAPTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_AAP
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
AAPRegisterInfo
::
getLinkRegister
(
)
,
MVT
::
i16
)
)
;
MachineRegisterInfo
&
MRI
=
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
MRI
.
disableCalleeSavedRegister
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
AAPISD
::
RET_FLAG
,
DL
,
{
MVT
::
Other
,
MVT
::
i16
}
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool AArch64TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Align , bool * Fast ) const { if ( Subtarget -> requiresStrictAlign ( ) ) return false ; if ( Fast ) { * Fast = ! Subtarget -> isCyclone ( ) || VT . getStoreSize ( ) != 16 || Align <= 2 || VT == MVT :: v2i64 ; } return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> MCELFStreamer & MipsTargetELFStreamer :: getStreamer ( ) { return static_cast < MCELFStreamer & > ( * Streamer ) ; } </s>

Return the output streamer for the assembler .


<s> MachineBasicBlock :: iterator RISCVInstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , const outliner :: Candidate & C ) const { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( RISCV :: PseudoCALLReg ) , RISCV :: X5 ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) , 0 , RISCVII :: MO_CALL ) ) ; return It ; } </s>

Insert a call to an outlined function into the program .


<s> bool m32r_can_eliminate ( const int from , const int to ) { return ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true ) ; } </s>

Worker function for TARGET_CAN_ELIMINATE .


<s> const unsigned * SPURegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const unsigned SPU_CalleeSaveRegs [ ] = { SPU :: R80 , SPU :: R81 , SPU :: R82 , SPU :: R83 , SPU :: R84 , SPU :: R85 , SPU :: R86 , SPU :: R87 , SPU :: R88 , SPU :: R89 , SPU :: R90 , SPU :: R91 , SPU :: R92 , SPU :: R93 , SPU :: R94 , SPU :: R95 , SPU :: R96 , SPU :: R97 , SPU :: R98 , SPU :: R99 , SPU :: R100 , SPU :: R101 , SPU :: R102 , SPU :: R103 , SPU :: R104 , SPU :: R105 , SPU :: R106 , SPU :: R107 , SPU :: R108 , SPU :: R109 , SPU :: R110 , SPU :: R111 , SPU :: R112 , SPU :: R113 , SPU :: R114 , SPU :: R115 , SPU :: R116 , SPU :: R117 , SPU :: R118 , SPU :: R119 , SPU :: R120 , SPU :: R121 , SPU :: R122 , SPU :: R123 , SPU :: R124 , SPU :: R125 , SPU :: R126 , SPU :: R127 , SPU :: R2 , SPU :: R1 , SPU :: R0 , 0 } ; return SPU_CalleeSaveRegs ; } </s>


<s> static bool mn10300_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) { unsigned HOST_WIDE_INT size = arg . type_size_in_bytes ( ) ; return ( size > 8 || size == 0 ) ; } </s>

Return true when a parameter should be passed by reference .


<s>
bool
FixupLEAPass
::
runOnMachineFunction
(
MachineFunction
&
Func
)
{
if
(
skipFunction
(
*
Func
.
getFunction
(
)
)
)
return
false
;
MF
=
&
Func
;
const
X86Subtarget
&
ST
=
Func
.
getSubtarget
<
X86Subtarget
>
(
)
;
OptIncDec
=
!
ST
.
slowIncDec
(
)
||
Func
.
getFunction
(
)
->
optForMinSize
(
)
;
OptLEA
=
ST
.
LEAusesAG
(
)
||
ST
.
slowLEA
(
)
;
if
(
!
OptLEA
&&
!
OptIncDec
)
return
false
;
TII
=
ST
.
getInstrInfo
(
)
;
DEBUG
(
dbgs
(
)
<<
"Start X86FixupLEAs\n"
;
)
;
for
(
MachineFunction
::
iterator
I
=
Func
.
begin
(
)
,
E
=
Func
.
end
(
)
;
I
!=
E
;
++
I
)
processBasicBlock
(
Func
,
I
)
;
DEBUG
(
dbgs
(
)
<<
"End X86FixupLEAs\n"
;
)
;
return
true
;
}
</s>


"Unexpected instruction type for reassociation"

"Must have dead EFLAGS operand in reassociable instruction"

"Unexpected operand in reassociable instruction"

This is an architecture-specific helper function of reassociateOps .


<s>
const
char
*
thumb2_output_casesi
(
rtx
*
operands
)
{
rtx
diff_vec
=
PATTERN
(
NEXT_INSN
(
as_a
<
rtx_insn
*
>
(
operands
[
2
]
)
)
)
;
gcc_assert
(
GET_CODE
(
diff_vec
)
==
ADDR_DIFF_VEC
)
;
output_asm_insn
(
"cmp\t%0, %1"
,
operands
)
;
output_asm_insn
(
"bhi\t%l3"
,
operands
)
;
switch
(
GET_MODE
(
diff_vec
)
)
{
case
QImode
:
return
"tbb\t[%|pc, %0]"
;
case
HImode
:
return
"tbh\t[%|pc, %0, lsl #1]"
;
case
SImode
:
if
(
flag_pic
)
{
output_asm_insn
(
"adr\t%4, %l2"
,
operands
)
;
output_asm_insn
(
"ldr\t%5, [%4, %0, lsl #2]"
,
operands
)
;
output_asm_insn
(
"add\t%4, %4, %5"
,
operands
)
;
return
"bx\t%4"
;
}
else
{
output_asm_insn
(
"adr\t%4, %l2"
,
operands
)
;
return
"ldr\t%|pc, [%4, %0, lsl #2]"
;
}
default
:
gcc_unreachable
(
)
;
}
}
</s>


<s> RISCVSubtarget & RISCVSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) { CPUName = "" ; } ParseSubtargetFeatures ( CPUName , FS ) ; return * this ; } </s>


<s> void init_cumulative_args ( struct sparc_args * cum , tree fntype , rtx libname ATTRIBUTE_UNUSED , tree fndecl ATTRIBUTE_UNUSED ) { cum -> words = 0 ; cum -> prototype_p = fntype && TYPE_ARG_TYPES ( fntype ) ; cum -> libcall_p = fntype == 0 ; } </s>

Handle the INIT_CUMULATIVE_ARGS macro . Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is 0 .


<s> bool X86RegisterInfo :: isFixedRegister ( const MachineFunction & MF , MCRegister PhysReg ) const { const X86Subtarget & ST = MF . getSubtarget < X86Subtarget > ( ) ; const TargetRegisterInfo & TRI = * ST . getRegisterInfo ( ) ; if ( TRI . isSuperOrSubRegisterEq ( X86 :: RSP , PhysReg ) ) return true ; const X86FrameLowering & TFI = * getFrameLowering ( MF ) ; if ( TFI . hasFP ( MF ) && TRI . isSuperOrSubRegisterEq ( X86 :: RBP , PhysReg ) ) return true ; return X86GenRegisterInfo :: isFixedRegister ( MF , PhysReg ) ; } </s>

Returns true if PhysReg is a fixed register .


<s> unsigned MOSInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : return 0 ; case MOS :: LDAbs : if ( ! MI . getOperand ( 0 ) . isFI ( ) ) return 0 ; FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; case MOS :: LDStk : FrameIndex = MI . getOperand ( 2 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s>
bool
ARM64AdvSIMDScalar
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
if
(
!
AdvSIMDScalar
)
return
false
;
bool
Changed
=
false
;
DEBUG
(
dbgs
(
)
<<
"***** ARM64AdvSIMDScalar *****\n"
)
;
const
TargetMachine
&
TM
=
mf
.
getTarget
(
)
;
MRI
=
&
mf
.
getRegInfo
(
)
;
TII
=
static_cast
<
const
ARM64InstrInfo
*
>
(
TM
.
getInstrInfo
(
)
)
;
for
(
MachineFunction
::
iterator
I
=
mf
.
begin
(
)
,
E
=
mf
.
end
(
)
;
I
!=
E
;
++
I
)
if
(
processMachineBasicBlock
(
I
)
)
Changed
=
true
;
return
Changed
;
}
</s>


<s> rtx function_arg ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int named ) { static const char * const hand_list [ ] = { "__main" , "__cmpsi2" , "__divhi3" , "__modhi3" , "__udivhi3" , "__umodhi3" , "__divsi3" , "__modsi3" , "__udivsi3" , "__umodsi3" , "__mulhi3" , "__mulsi3" , "__reg_memcpy" , "__reg_memset" , "__ucmpsi2" , 0 , } ; rtx result = NULL_RTX ; const char * fname ; int regpass = 0 ; if ( ! named ) return NULL_RTX ; if ( TARGET_QUICKCALL ) regpass = 3 ; if ( cum -> libcall ) { const char * const * p ; fname = XSTR ( cum -> libcall , 0 ) ; for ( p = hand_list ; * p && strcmp ( * p , fname ) != 0 ; p ++ ) ; if ( * p ) regpass = 4 ; } if ( regpass ) { int size ; if ( mode == BLKmode ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; if ( size + cum -> nbytes <= regpass * UNITS_PER_WORD && cum -> nbytes / UNITS_PER_WORD <= 3 ) result = gen_rtx_REG ( mode , cum -> nbytes / UNITS_PER_WORD ) ; } return result ; } </s>

Return an RTL expression containing the register for the given mode , or 0 if the argument is to be passed on the stack . INCOMING_P is nonzero if this is an incoming argument to the current function .


<s> bool expand_move ( rtx * operands , machine_mode mode ) { rtx dest = operands [ 0 ] ; rtx op = operands [ 1 ] ; if ( ( reload_in_progress | reload_completed ) == 0 && GET_CODE ( dest ) == MEM && GET_CODE ( op ) != REG ) operands [ 1 ] = force_reg ( mode , op ) ; else if ( mode == SImode && symbolic_operand ( op , SImode ) ) { if ( flag_pic ) { if ( sdata_symbolic_operand ( op , SImode ) ) { emit_insn ( gen_load_sdata_pic ( dest , pic_offset_table_rtx , op ) ) ; crtl -> uses_pic_offset_table = 1 ; return true ; } else { rtx temp = ( reload_completed || reload_in_progress ? dest : gen_reg_rtx ( Pmode ) ) ; operands [ 1 ] = legitimize_pic_address ( op , temp , pic_offset_table_rtx ) ; } } else if ( reload_completed && ! sdata_symbolic_operand ( op , SImode ) ) { emit_insn ( gen_movsi_high ( dest , op ) ) ; emit_insn ( gen_movsi_lo_sum ( dest , dest , op ) ) ; return true ; } } return false ; } </s>

Expand a move operation in mode MODE . The operands are in OPERANDS .


<s> unsigned getNumFixupKinds ( ) const override { return P2 :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> void gen_conditional_move ( rtx * operands ) { enum rtx_code code ; rtx op0 , op1 ; code = GET_CODE ( operands [ 1 ] ) ; mips_emit_compare ( & code , & op0 , & op1 , true ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , gen_rtx_IF_THEN_ELSE ( GET_MODE ( operands [ 0 ] ) , gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 , op1 ) , operands [ 2 ] , operands [ 3 ] ) ) ) ; } </s>

Emit the common code for conditional moves . OPERANDS is the array of operands passed to the conditional move define_expand .


<s> static bool m68k_tls_symbol_p ( rtx x ) { if ( ! TARGET_HAVE_TLS ) return false ; if ( GET_CODE ( x ) != SYMBOL_REF ) return false ; return SYMBOL_REF_TLS_MODEL ( x ) != 0 ; } </s>


<s> bool symbolic_reference_mentioned_p ( rtx op ) { const char * fmt ; int i ; if ( GET_CODE ( op ) == SYMBOL_REF || GET_CODE ( op ) == LABEL_REF ) return true ; fmt = GET_RTX_FORMAT ( GET_CODE ( op ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( op ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( op , i ) - 1 ; j >= 0 ; j -- ) if ( symbolic_reference_mentioned_p ( XVECEXP ( op , i , j ) ) ) return true ; } else if ( fmt [ i ] == 'e' && symbolic_reference_mentioned_p ( XEXP ( op , i ) ) ) return true ; } return false ; } </s>

Return true if OP contains a symbol reference


<s> void sh_init_cumulative_args ( CUMULATIVE_ARGS * pcum , tree fntype , rtx libname ATTRIBUTE_UNUSED , tree fndecl , signed int n_named_args , machine_mode mode ) { pcum -> arg_count [ ( int ) SH_ARG_FLOAT ] = 0 ; pcum -> free_single_fp_reg = 0 ; pcum -> outgoing = n_named_args != - 1 ; pcum -> renesas_abi = sh_attr_renesas_p ( fntype ) ; if ( fntype ) { pcum -> force_mem = ( ( TARGET_HITACHI || pcum -> renesas_abi ) && aggregate_value_p ( TREE_TYPE ( fntype ) , fndecl ) ) ; pcum -> prototype_p = prototype_p ( fntype ) ; pcum -> arg_count [ ( int ) SH_ARG_INT ] = false ; } else { pcum -> arg_count [ ( int ) SH_ARG_INT ] = 0 ; pcum -> prototype_p = false ; if ( mode != VOIDmode ) { pcum -> force_mem = ( TARGET_DEFAULT & MASK_HITACHI ) && ( mode == BLKmode || ( GET_MODE_SIZE ( mode ) > 4 && ! ( mode == DFmode && TARGET_FPU_DOUBLE ) ) ) ; } else pcum -> force_mem = false ; } } </s>

Initialize the CUMULATIVE_ARGS structure .


<s> static void expand_block_move_1 ( rtx dst_reg , rtx src_reg , rtx bytes_rtx ) { emit_library_call ( byt_memcpy_libfunc , LCT_NORMAL , VOIDmode , 3 , dst_reg , Pmode , src_reg , Pmode , convert_to_mode ( TYPE_MODE ( sizetype ) , bytes_rtx , TYPE_UNSIGNED ( sizetype ) ) , TYPE_MODE ( sizetype ) ) ; } </s>

Generate a call to a library function to move BYTES_RTX bytes from address SRC_REG to address DST_REG in 1-byte chunks .


<s>
bool
AMDGPUAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Name
=
parseMnemonicSuffix
(
Name
)
;
Operands
.
push_back
(
AMDGPUOperand
::
CreateToken
(
Name
,
NameLoc
)
)
;
while
(
!
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
{
AMDGPUAsmParser
::
OperandMatchResultTy
Res
=
parseOperand
(
Operands
,
Name
)
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
Parser
.
Lex
(
)
;
switch
(
Res
)
{
case
MatchOperand_Success
:
break
;
case
MatchOperand_ParseFail
:
Error
(
getLexer
(
)
.
getLoc
(
)
,
"failed parsing operand."
)
;
while
(
!
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
{
Parser
.
Lex
(
)
;
}
return
true
;
case
MatchOperand_NoMatch
:
Error
(
getLexer
(
)
.
getLoc
(
)
,
"not a valid operand."
)
;
while
(
!
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
{
Parser
.
Lex
(
)
;
}
return
true
;
}
}
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

AMDGPU
AMDGPU
AMDGPU
AMDGPU
"failed parsing operand."
"not a valid operand."


<s>
static
rtx
arm_expand_vfp_builtin
(
int
fcode
,
tree
exp
,
rtx
target
)
{
if
(
fcode
>=
ARM_BUILTIN_VFP_BASE
&&
!
TARGET_HARD_FLOAT
)
{
fatal_error
(
input_location
,
"You must enable VFP instructions"
" to use these intrinsics."
)
;
return
const0_rtx
;
}
arm_builtin_datum
*
d
=
&
vfp_builtin_data
[
fcode
ARM_BUILTIN_VFP_PATTERN_START
]
;
return
arm_expand_builtin_1
(
fcode
,
exp
,
target
,
d
)
;
}
</s>

Expand a VFP builtin . These builtins are treated like neon builtins except that the data is looked up in table VFP_BUILTIN_DATA .

arm
"You must enable VFP instructions"
" to use these intrinsics."


<s>
const
char
*
ix86_output_function_return
(
bool
long_p
)
{
output_return_instrumentation
(
)
;
if
(
cfun
->
machine
->
function_return_type
!=
indirect_branch_keep
)
{
char
thunk_name
[
32
]
;
enum
indirect_thunk_prefix
need_prefix
=
indirect_thunk_need_prefix
(
current_output_insn
)
;
if
(
cfun
->
machine
->
function_return_type
!=
indirect_branch_thunk_inline
)
{
bool
need_thunk
=
(
cfun
->
machine
->
function_return_type
==
indirect_branch_thunk
)
;
indirect_thunk_name
(
thunk_name
,
INVALID_REGNUM
,
need_prefix
,
true
)
;
indirect_return_needed
|=
need_thunk
;
fprintf
(
asm_out_file
,
"\tjmp\t"
)
;
assemble_name
(
asm_out_file
,
thunk_name
)
;
putc
(
'\n'
,
asm_out_file
)
;
}
else
output_indirect_thunk
(
INVALID_REGNUM
)
;
return
""
;
}
output_asm_insn
(
long_p
"rep%; ret"
:
"ret"
,
nullptr
)
;
return
(
ix86_harden_sls
&
harden_sls_return
)
"int3"
:
""
;
}
</s>

Output function return . CALL_OP is the jump target . Add a REP prefix to RET if LONG_P is true and function return is kept .


<s> const X86_64GNULDBackend & getTarget ( ) const { return m_Target ; } </s>

getTarget - Return the target machine this machine code is compiled with


<s> static std :: unique_ptr < AArch64Operand > CreateReg ( unsigned RegNum , RegKind Kind , SMLoc S , SMLoc E , MCContext & Ctx , AArch64_AM :: ShiftExtendType ExtTy = AArch64_AM :: LSL , unsigned ShiftAmount = 0 , unsigned HasExplicitAmount = false ) { auto Op = make_unique < AArch64Operand > ( k_Register , Ctx ) ; Op -> Reg . RegNum = RegNum ; Op -> Reg . Kind = Kind ; Op -> Reg . ElementWidth = 0 ; Op -> Reg . ShiftExtend . Type = ExtTy ; Op -> Reg . ShiftExtend . Amount = ShiftAmount ; Op -> Reg . ShiftExtend . HasExplicitAmount = HasExplicitAmount ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


"-mdiv requires -march to subsume the %<M%> extension"

"requested ABI requires -march to subsume the %qc extension"

"-mpreferred-stack-boundary=%d must be between %d and %d"


<s>
SDValue
TL45TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
report_fatal_error
(
"unimplemented operand"
)
;
case
ISD
::
BR_CC
:
return
lowerBrCc
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
lowerSELECT
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
lowerSelectCc
(
Op
,
DAG
)
;
case
ISD
::
AND
:
return
lowerAnd
(
Op
,
DAG
)
;
case
ISD
::
OR
:
return
lowerOr
(
Op
,
DAG
)
;
case
ISD
::
XOR
:
return
lowerXor
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
lowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
lowerGlobalAddress
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s>
Register
getStackAddress
(
uint64_t
Size
,
int64_t
Offset
,
MachinePointerInfo
&
MPO
,
ISD
::
ArgFlagsTy
Flags
)
override
{
assert
(
(
Size
==
1
||
Size
==
2
||
Size
==
4
||
Size
==
8
)
&&
"Unsupported size"
)
;
auto
&
MFI
=
MIRBuilder
.
getMF
(
)
.
getFrameInfo
(
)
;
const
bool
IsImmutable
=
!
Flags
.
isByVal
(
)
;
int
FI
=
MFI
.
CreateFixedObject
(
Size
,
Offset
,
IsImmutable
)
;
MPO
=
MachinePointerInfo
::
getFixedStack
(
MIRBuilder
.
getMF
(
)
,
FI
)
;
return
MIRBuilder
.
buildFrameIndex
(
LLT
::
pointer
(
MPO
.
getAddrSpace
(
)
,
32
)
,
FI
)
.
getReg
(
0
)
;
}
</s>

Materialize a VReg containing the address of the specified stack-based object .


Finalize stack_realign_needed flag , which will guide prologue/epilogue to be generated in correct form .


<s> bool R600InstrInfo :: isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , BranchProbability Probability ) const { return true ; } </s>

Return true if it 's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion .


<s> static bool bpf_hard_regno_mode_ok ( unsigned int regno ATTRIBUTE_UNUSED , enum machine_mode mode ) { switch ( mode ) { case E_SImode : case E_DImode : case E_HImode : case E_QImode : case E_TImode : case E_SFmode : case E_DFmode : return true ; default : return false ; } } </s>

Return true if it is permissible to store a value of mode MODE in hard register number REGNO , or in several registers starting with that one .


"%s instructions aren%'t allowed in a function with "

Establish appropriate back-end context for processing the function FNDECL . The argument might be NULL to indicate processing at top level , outside of any function scope .


getTargetNodeName - This method returns the name of a target specific


<s> bool UPTInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case UPT :: MOVi32 : { DebugLoc DL = MI . getDebugLoc ( ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; const unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ; const bool DstIsDead = MI . getOperand ( 0 ) . isDead ( ) ; const MachineOperand & MO = MI . getOperand ( 1 ) ; auto LO16 = BuildMI ( MBB , MI , DL , get ( UPT :: MOVLOi16 ) , DstReg ) ; auto HI16 = BuildMI ( MBB , MI , DL , get ( UPT :: MOVHIi16 ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; const GlobalValue * GV = MO . getGlobal ( ) ; const unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | UPTII :: MO_LO16 ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | UPTII :: MO_HI16 ) ; MBB . erase ( MI ) ; return true ; } } } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> bool isReg ( ) const override { return false ; } </s>


<s>
SDValue
XCoreTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
BR_JT
:
return
LowerBR_JT
(
Op
,
DAG
)
;
case
ISD
::
LOAD
:
return
LowerLOAD
(
Op
,
DAG
)
;
case
ISD
::
STORE
:
return
LowerSTORE
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
VAARG
:
return
LowerVAARG
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
SMUL_LOHI
:
return
LowerSMUL_LOHI
(
Op
,
DAG
)
;
case
ISD
::
UMUL_LOHI
:
return
LowerUMUL_LOHI
(
Op
,
DAG
)
;
case
ISD
::
ADD
:
case
ISD
::
SUB
:
return
ExpandADDSUB
(
Op
.
getNode
(
)
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
INIT_TRAMPOLINE
:
return
LowerINIT_TRAMPOLINE
(
Op
,
DAG
)
;
case
ISD
::
ADJUST_TRAMPOLINE
:
return
LowerADJUST_TRAMPOLINE
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
return
SDValue
(
)
;
}
}
</s>

XCore
XCore
ISD::GlobalAddress
ISD::GlobalTLSAddress
ISD::BlockAddress
ISD::ConstantPool
ISD::BR_JT
ISD::LOAD
ISD::STORE
ISD::SELECT_CC
ISD::VAARG
ISD::VASTART
ISD::SMUL_LOHI
ISD::UMUL_LOHI
ISD::ADD
ISD::SUB
ISD::FRAMEADDR
ISD::INIT_TRAMPOLINE
ISD::ADJUST_TRAMPOLINE
"unimplemented operand"


<s>
static
void
mcore_asm_trampoline_template
(
FILE
*
f
)
{
fprintf
(
f
,
"\t.short	0x7102\n"
)
;
fprintf
(
f
,
"\t.short	0x7d02\n"
)
;
fprintf
(
f
,
"\t.short	0x00cd\n"
)
;
fprintf
(
f
,
"\t.short	0x1e00\n"
)
;
fprintf
(
f
,
"\t.long	0\n"
)
;
fprintf
(
f
,
"\t.long	0\n"
)
;
}
</s>

Worker function for TARGET_ASM_TRAMPOLINE_TEMPLATE . Output assembler code for a block containing the constant parts of a trampoline , leaving space for the variable parts . On the MCore , the trampoline looks like : lrw r1 , function lrw r13 , area jmp r13 or r0 , r0 .literals

mcore
"\t.short	0x7102\n"
"\t.short	0x7d02\n"
"\t.short	0x00cd\n"
"\t.short	0x1e00\n"
"\t.long	0\n"
"\t.long	0\n"