<s>
bool
Emitter
<
CodeEmitter
>
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MMI
=
&
getAnalysis
<
MachineModuleInfo
>
(
)
;
MCE
.
setModuleInfo
(
MMI
)
;
II
=
TM
.
getInstrInfo
(
)
;
TD
=
TM
.
getTargetData
(
)
;
Is64BitMode
=
TM
.
getSubtarget
<
X86Subtarget
>
(
)
.
is64Bit
(
)
;
IsPIC
=
TM
.
getRelocationModel
(
)
==
Reloc
::
PIC_
;
do
{
DEBUG
(
dbgs
(
)
<<
"JITTing function '"
<<
MF
.
getFunction
(
)
->
getName
(
)
<<
"'\n"
)
;
MCE
.
startFunction
(
MF
)
;
for
(
MachineFunction
::
iterator
MBB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBB
!=
E
;
++
MBB
)
{
MCE
.
StartMachineBasicBlock
(
MBB
)
;
for
(
MachineBasicBlock
::
iterator
I
=
MBB
->
begin
(
)
,
E
=
MBB
->
end
(
)
;
I
!=
E
;
++
I
)
{
const
MCInstrDesc
&
Desc
=
I
->
getDesc
(
)
;
emitInstruction
(
*
I
,
&
Desc
)
;
if
(
Desc
.
getOpcode
(
)
==
X86
::
MOVPC32r
)
emitInstruction
(
*
I
,
&
II
->
get
(
X86
::
POP32r
)
)
;
++
NumEmitted
;
}
}
}
while
(
MCE
.
finishFunction
(
MF
)
)
;
return
false
;
}
</s>


<s> static int loongarch_adjust_cost ( rtx_insn * , int dep_type , rtx_insn * , int cost , unsigned int ) { if ( dep_type != 0 && ( dep_type != REG_DEP_OUTPUT ) ) return 0 ; return cost ; } </s>

Implement TARGET_SCHED_ADJUST_COST . We assume that anti and output dependencies have no cost .


<s>
StringRef
getPassName
(
)
const
override
{
return
"BPF Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static void insert_hbrp ( void ) { rtx_insn * insn ; if ( TARGET_SAFE_HINTS ) { shorten_branches ( get_insns ( ) ) ; insn = next_active_insn ( get_insns ( ) ) ; if ( insn ) insert_hbrp_for_ilb_runout ( insn ) ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( ( LABEL_P ( insn ) && HINTED_P ( insn ) ) || CALL_P ( insn ) ) insert_hbrp_for_ilb_runout ( next_active_insn ( insn ) ) ; } } </s>

The SPU might hang when it executes 48 inline instructions after a hinted branch jumps to its hinted target . The beginning of a function and the return from a call might have been hinted , and must be handled as well . To prevent a hang we insert 2 hbrps . The first should be within 6 insns of the branch target . The second should be within 22 insns of the branch target . When determining if hbrps are necessary , we look for only 32 inline instructions , because up to 12 nops and 4 hbrps could be inserted . Similarily , when inserting new hbrps , we insert them within 4 and 16 insns of the target .


<s> static __inline__ struct quot_rem do_31div ( unsigned long a , unsigned long b ) { long extra = 0 ; int quot_digits = 0 ; if ( b == 0 ) { struct quot_rem ret ; ret . quot = 0xffffffff ; ret . rem = 0xffffffff ; return ret ; } if ( a < b ) return ( struct quot_rem ) { 0 , a } ; if ( b <= a ) { quot_digits = LZ ( b ) - LZ ( a ) ; quot_digits += ( a >= ( b << quot_digits ) ) ; b <<= quot_digits ; } while ( b <= a ) { b <<= 1 ; quot_digits ++ ; } if ( a & 0x40000000 ) { b >>= 1 ; if ( a >= b ) { a -= b ; extra = 1 << ( quot_digits - 1 ) ; } else { a -= b >> 1 ; extra = 1 << quot_digits ; } quot_digits -- ; } b -- ; switch ( quot_digits ) { case 32 : DS ; case 31 : DS ; case 30 : DS ; case 29 : DS ; case 28 : DS ; case 27 : DS ; case 26 : DS ; case 25 : DS ; case 24 : DS ; case 23 : DS ; case 22 : DS ; case 21 : DS ; case 20 : DS ; case 19 : DS ; case 18 : DS ; case 17 : DS ; case 16 : DS ; case 15 : DS ; case 14 : DS ; case 13 : DS ; case 12 : DS ; case 11 : DS ; case 10 : DS ; case 9 : DS ; case 8 : DS ; case 7 : DS ; case 6 : DS ; case 5 : DS ; case 4 : DS ; case 3 : DS ; case 2 : DS ; case 1 : DS ; case 0 : ; } { struct quot_rem ret ; ret . quot = ( a & ( ( 1 << quot_digits ) - 1 ) ) + extra ; ret . rem = a >> quot_digits ; return ret ; } } </s>

This is the worker function for div and mod . It is inlined into the respective library function .


<s> static rtx_code_label * add_constant ( rtx x , machine_mode mode , rtx last_value ) { rtx_code_label * lab , * new_rtx ; label_ref_list_t ref , newref ; for ( int i = 0 ; i < pool_size ; i ++ ) { if ( x -> code == pool_vector [ i ] . value -> code && mode == pool_vector [ i ] . mode ) { if ( x -> code == CODE_LABEL ) { if ( XINT ( x , 3 ) != XINT ( pool_vector [ i ] . value , 3 ) ) continue ; } if ( rtx_equal_p ( x , pool_vector [ i ] . value ) ) { lab = new_rtx = 0 ; if ( ! last_value || ! i || ! rtx_equal_p ( last_value , pool_vector [ i - 1 ] . value ) ) { new_rtx = gen_label_rtx ( ) ; LABEL_REFS ( new_rtx ) = pool_vector [ i ] . label ; pool_vector [ i ] . label = lab = new_rtx ; } if ( lab && pool_window_label ) { newref = label_ref_list_d_pool . allocate ( ) ; newref -> label = pool_window_label ; ref = pool_vector [ pool_window_last ] . wend ; newref -> next = ref ; pool_vector [ pool_window_last ] . wend = newref ; } if ( new_rtx ) pool_window_label = new_rtx ; pool_window_last = i ; return lab ; } } } pool_vector [ pool_size ] . value = x ; if ( last_value && rtx_equal_p ( last_value , pool_vector [ pool_size - 1 ] . value ) ) { lab = 0 ; pool_vector [ pool_size - 1 ] . part_of_sequence_p = true ; } else lab = gen_label_rtx ( ) ; pool_vector [ pool_size ] . mode = mode ; pool_vector [ pool_size ] . label = lab ; pool_vector [ pool_size ] . wend = NULL ; pool_vector [ pool_size ] . part_of_sequence_p = ( lab == 0 ) ; if ( lab && pool_window_label ) { newref = label_ref_list_d_pool . allocate ( ) ; newref -> label = pool_window_label ; ref = pool_vector [ pool_window_last ] . wend ; newref -> next = ref ; pool_vector [ pool_window_last ] . wend = newref ; } if ( lab ) pool_window_label = lab ; pool_window_last = pool_size ; pool_size ++ ; return lab ; } </s>

Add a constant to the pool and return its label .


<s> bool X86FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || TRI -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasOpaqueSPAdjustment ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> hasPreallocatedCall ( ) || MF . callsUnwindInit ( ) || MF . hasEHFunclets ( ) || MF . callsEHReturn ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || ( isWin64Prologue ( MF ) && MFI . hasCopyImplyingStackAdjustment ( ) ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void frv_final_prescan_insn ( rtx insn , rtx * opvec , int noperands ATTRIBUTE_UNUSED ) { if ( INSN_P ( insn ) ) { if ( frv_insn_packing_flag >= 0 ) { frv_insn_operands = opvec ; frv_insn_packing_flag = PACKING_FLAG_P ( insn ) ; } else if ( recog_memoized ( insn ) >= 0 && get_attr_acc_group ( insn ) == ACC_GROUP_ODD ) fprintf ( asm_out_file , "\tmnop.p\n" ) ; } } </s>

Set up the packing bit for the current output insn . Note that this function is not called for asm insns .


"Do not know how to custom type legalize this operation!"

"Unexpected result type for CTR decrement intrinsic"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> void NyuziFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { assert ( & MF . front ( ) == & MBB ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const NyuziInstrInfo & TII = * static_cast < const NyuziInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; const MCRegisterInfo * MRI = MF . getMMI ( ) . getContext ( ) . getRegisterInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc DL ; int StackSize = alignTo ( MFI . getStackSize ( ) , getStackAlignment ( ) ) ; if ( StackSize == 0 && ! MFI . adjustsStack ( ) ) return ; TII . adjustStackPointer ( MBB , MBBI , DL , - StackSize ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - StackSize ) ) ; BuildMI ( MBB , MBBI , DL , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; if ( CSI . size ( ) ) { for ( unsigned i = 0 ; i < CSI . size ( ) ; ++ i ) ++ MBBI ; for ( const auto & I : CSI ) { int64_t Offset = MFI . getObjectOffset ( I . getFrameIdx ( ) ) ; unsigned Reg = I . getReg ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( Reg , 1 ) , Offset ) ) ; BuildMI ( MBB , MBBI , DL , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( Nyuzi :: MOVESS ) ) . addReg ( Nyuzi :: FP_REG ) . addReg ( Nyuzi :: SP_REG ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , MRI -> getDwarfRegNum ( Nyuzi :: FP_REG , true ) ) ) ; BuildMI ( MBB , MBBI , DL , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> enum indirect_thunk_prefix indirect_thunk_need_prefix ( rtx_insn * insn ) { enum indirect_thunk_prefix need_prefix ; if ( ( cfun -> machine -> indirect_branch_type == indirect_branch_thunk_extern ) && ix86_notrack_prefixed_insn_p ( insn ) ) { need_prefix = indirect_thunk_prefix_nt ; } else need_prefix = indirect_thunk_prefix_none ; return need_prefix ; } </s>

Return the prefix needed for an indirect branch INSN .


<s> void SystemZHazardRecognizer :: copyState ( SystemZHazardRecognizer * Incoming ) { CurrGroupSize = Incoming -> CurrGroupSize ; DEBUG ( CurGroupDbg = Incoming -> CurGroupDbg ; ) ; ProcResourceCounters = Incoming -> ProcResourceCounters ; CriticalResourceIdx = Incoming -> CriticalResourceIdx ; LastFPdOpCycleIdx = Incoming -> LastFPdOpCycleIdx ; GrpCount = Incoming -> GrpCount ; } </s>

Copy counters from end of single predecessor .


"expected larger existing stack allocation"

Target-specific cleanup for formal ByVal parameters .


<s> BaseKind getKind ( ) const { return Kind ; } </s>


<s> void SIRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const SIInstrInfo * TII = ST . getInstrInfo ( ) ; if ( Offset == 0 ) { BuildMI ( * MBB , Ins , DL , TII -> get ( AMDGPU :: V_MOV_B32_e32 ) , BaseReg ) . addFrameIndex ( FrameIdx ) ; return ; } MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; Register OffsetReg = MRI . createVirtualRegister ( & AMDGPU :: SReg_32_XM0RegClass ) ; Register FIReg = MRI . createVirtualRegister ( & AMDGPU :: VGPR_32RegClass ) ; BuildMI ( * MBB , Ins , DL , TII -> get ( AMDGPU :: S_MOV_B32 ) , OffsetReg ) . addImm ( Offset ) ; BuildMI ( * MBB , Ins , DL , TII -> get ( AMDGPU :: V_MOV_B32_e32 ) , FIReg ) . addFrameIndex ( FrameIdx ) ; TII -> getAddNoCarry ( * MBB , Ins , DL , BaseReg ) . addReg ( OffsetReg , RegState :: Kill ) . addReg ( FIReg ) . addImm ( 0 ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .


<s> SDValue MBlazeTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) { switch ( Op . getOpcode ( ) ) { case ISD :: ConstantPool : return LowerConstantPool ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return LowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( Op , DAG ) ; case ISD :: SELECT_CC : return LowerSELECT_CC ( Op , DAG ) ; case ISD :: VASTART : return LowerVASTART ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

MBlaze MBlaze ISD::ConstantPool ISD::GlobalAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::SELECT_CC ISD::VASTART


<s> bool MipsAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & TM . getSubtarget < MipsSubtarget > ( ) ; const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) NaClAlignIndirectJumpTargets ( MF ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s>
void
R600SchedStrategy
::
initialize
(
ScheduleDAGMI
*
dag
)
{
assert
(
dag
->
hasVRegLiveness
(
)
&&
"R600SchedStrategy needs vreg liveness"
)
;
DAG
=
static_cast
<
ScheduleDAGMILive
*
>
(
dag
)
;
const
R600Subtarget
&
ST
=
DAG
->
MF
.
getSubtarget
<
R600Subtarget
>
(
)
;
TII
=
static_cast
<
const
R600InstrInfo
*
>
(
DAG
->
TII
)
;
TRI
=
static_cast
<
const
R600RegisterInfo
*
>
(
DAG
->
TRI
)
;
VLIW5
=
!
ST
.
hasCaymanISA
(
)
;
MRI
=
&
DAG
->
MRI
;
CurInstKind
=
IDOther
;
CurEmitted
=
0
;
OccupiedSlotsMask
=
31
;
InstKindLimit
[
IDAlu
]
=
TII
->
getMaxAlusPerClause
(
)
;
InstKindLimit
[
IDOther
]
=
32
;
InstKindLimit
[
IDFetch
]
=
ST
.
getTexVTXClauseSize
(
)
;
AluInstCount
=
0
;
FetchInstCount
=
0
;
}
</s>

Initialize the strategy after building the DAG for a new region .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < PPCSubtarget > ( ) ; return AsmPrinter :: runOnMachineFunction ( MF ) ; } </s>


<s> bool preferred_la_operand_p ( rtx op1 , rtx op2 ) { struct s390_address addr ; if ( op2 != const0_rtx ) op1 = gen_rtx_PLUS ( Pmode , op1 , op2 ) ; if ( ! s390_decompose_address ( op1 , & addr ) ) return false ; if ( addr . base && ! REG_OK_FOR_BASE_STRICT_P ( addr . base ) ) return false ; if ( addr . indx && ! REG_OK_FOR_INDEX_STRICT_P ( addr . indx ) ) return false ; if ( ! TARGET_64BIT && ! addr . pointer ) return false ; if ( addr . pointer ) return true ; if ( ( addr . base && REG_P ( addr . base ) && REG_POINTER ( addr . base ) ) || ( addr . indx && REG_P ( addr . indx ) && REG_POINTER ( addr . indx ) ) ) return true ; return false ; } </s>

Return true if it is valid * and * preferable to use LA to compute the sum of OP1 and OP2 .


<s> void SIInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { insertNoops ( MBB , MI , 1 ) ; } </s>

Insert a noop into the instruction stream at the specified point .


<s> static const simd_vec_cost * aarch64_simd_vec_costs ( tree vectype ) { const cpu_vector_cost * costs = aarch64_tune_params . vec_costs ; if ( vectype != NULL && aarch64_sve_mode_p ( TYPE_MODE ( vectype ) ) && costs -> sve != NULL ) return costs -> sve ; return costs -> advsimd ; } </s>

Return the appropriate SIMD costs for vectors of type VECTYPE .


<s>
bool
FixupLEAPass
::
runOnMachineFunction
(
MachineFunction
&
Func
)
{
MF
=
&
Func
;
TM
=
&
Func
.
getTarget
(
)
;
const
X86Subtarget
&
ST
=
TM
->
getSubtarget
<
X86Subtarget
>
(
)
;
if
(
!
ST
.
LEAusesAG
(
)
&&
!
ST
.
slowLEA
(
)
)
return
false
;
TII
=
ST
.
getInstrInfo
(
)
;
DEBUG
(
dbgs
(
)
<<
"Start X86FixupLEAs\n"
;
)
;
for
(
MachineFunction
::
iterator
I
=
Func
.
begin
(
)
,
E
=
Func
.
end
(
)
;
I
!=
E
;
++
I
)
processBasicBlock
(
Func
,
I
)
;
DEBUG
(
dbgs
(
)
<<
"End X86FixupLEAs\n"
;
)
;
return
true
;
}
</s>


<s> static int nvptx_simt_vf ( ) { return PTX_VECTOR_LENGTH ; } </s>

Implement TARGET_SIMT_VF target hook : number of threads in a warp .


<s> bool ARMFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; unsigned PushOpc = AFI -> isThumbFunction ( ) ? ARM :: t2STMDB_UPD : ARM :: STMDB_UPD ; unsigned PushOneOpc = AFI -> isThumbFunction ( ) ? ARM :: t2STR_PRE : ARM :: STR_PRE_IMM ; unsigned FltOpc = ARM :: VSTMDDB_UPD ; unsigned NumAlignedDPRCS2Regs = AFI -> getNumAlignedDPRCS2Regs ( ) ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & isARMArea1Register , 0 , MachineInstr :: FrameSetup ) ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & isARMArea2Register , 0 , MachineInstr :: FrameSetup ) ; emitPushInst ( MBB , MI , CSI , FltOpc , 0 , true , & isARMArea3Register , NumAlignedDPRCS2Regs , MachineInstr :: FrameSetup ) ; if ( NumAlignedDPRCS2Regs ) emitAlignedDPRCS2Spills ( MBB , MI , NumAlignedDPRCS2Regs , CSI , TRI ) ; return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> TargetLoweringBase :: LegalizeTypeAction NVPTXTargetLowering :: getPreferredVectorAction ( EVT VT ) const { if ( VT . getVectorNumElements ( ) != 1 && VT . getScalarType ( ) == MVT :: i1 ) return TypeSplitVector ; if ( VT == MVT :: v2f16 ) return TypeLegal ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s> const AMDGPUSubtarget * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> MachineInstr * SIInstrInfo :: commuteInstruction ( MachineInstr * MI , bool NewMI ) const { if ( MI -> getNumOperands ( ) < 3 || ! MI -> getOperand ( 1 ) . isReg ( ) || ! MI -> getOperand ( 2 ) . isReg ( ) ) return 0 ; MI = TargetInstrInfo :: commuteInstruction ( MI , NewMI ) ; if ( MI ) MI -> setDesc ( get ( commuteOpcode ( MI -> getOpcode ( ) ) ) ) ; return MI ; } </s>

This method commutes the operands of the given machine instruction MI .


"' has frame pointer, incrementing stack frame size by ptr_size.\n"

Determine the frame layout but do not update the machine function .


<s> void notice_update_cc ( rtx body ATTRIBUTE_UNUSED , rtx insn ) { rtx set ; switch ( get_attr_cc ( insn ) ) { case CC_NONE : break ; case CC_SET_N : CC_STATUS_INIT ; break ; case CC_SET_ZN : set = single_set ( insn ) ; CC_STATUS_INIT ; if ( set ) { cc_status . flags |= CC_NO_OVERFLOW ; cc_status . value1 = SET_DEST ( set ) ; } break ; case CC_SET_CZN : set = single_set ( insn ) ; CC_STATUS_INIT ; if ( set ) { cc_status . value1 = SET_DEST ( set ) ; cc_status . flags |= CC_OVERFLOW_UNUSABLE ; } break ; case CC_COMPARE : set = single_set ( insn ) ; CC_STATUS_INIT ; if ( set ) cc_status . value1 = SET_SRC ( set ) ; break ; case CC_CLOBBER : CC_STATUS_INIT ; set = single_set ( insn ) ; if ( set ) { rtx src = SET_SRC ( set ) ; if ( GET_CODE ( src ) == ASHIFTRT && GET_MODE ( src ) == QImode ) { rtx x = XEXP ( src , 1 ) ; if ( GET_CODE ( x ) == CONST_INT && INTVAL ( x ) > 0 && INTVAL ( x ) != 6 ) { cc_status . value1 = SET_DEST ( set ) ; cc_status . flags |= CC_OVERFLOW_UNUSABLE ; } } } break ; } } </s>

On the 68000 , all the insns to store in an address register fail to set the cc 's . However , in some cases these instructions can make it possibly invalid to use the saved cc 's . In those cases we clear out some or all of the saved cc 's so they wo n't be used .


Find a spare low register to use during the prolog of a function .


<s> bool AGCAsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> enum reg_class avr_reg_class_from_letter ( int c ) { switch ( c ) { case 't' : return R0_REG ; case 'b' : return BASE_POINTER_REGS ; case 'e' : return POINTER_REGS ; case 'w' : return ADDW_REGS ; case 'd' : return LD_REGS ; case 'l' : return NO_LD_REGS ; case 'a' : return SIMPLE_LD_REGS ; case 'x' : return POINTER_X_REGS ; case 'y' : return POINTER_Y_REGS ; case 'z' : return POINTER_Z_REGS ; case 'q' : return STACK_REG ; default : break ; } return NO_REGS ; } </s>

A C expression which defines the machine-dependent operand constraint letters for register classes . If C is such a letter , the value should be the register class corresponding to it . Otherwise , the value should be ` NO_REGS ' . The register letter ` r ' , corresponding to class ` GENERAL_REGS ' , will not be passed to this macro ; you do not need to handle it .


<s> static int rs6000_hard_regno_nregs_internal ( int regno , machine_mode mode ) { unsigned HOST_WIDE_INT reg_size ; if ( FP_REGNO_P ( regno ) ) reg_size = ( VECTOR_MEM_VSX_P ( mode ) || FLOAT128_VECTOR_P ( mode ) ? UNITS_PER_VSX_WORD : UNITS_PER_FP_WORD ) ; else if ( SPE_SIMD_REGNO_P ( regno ) && TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) reg_size = UNITS_PER_SPE_WORD ; else if ( ALTIVEC_REGNO_P ( regno ) ) reg_size = UNITS_PER_ALTIVEC_WORD ; else if ( TARGET_E500_DOUBLE && FLOAT_MODE_P ( mode ) && mode != SCmode && ! DECIMAL_FLOAT_MODE_P ( mode ) && SPE_SIMD_REGNO_P ( regno ) ) reg_size = UNITS_PER_FP_WORD ; else reg_size = UNITS_PER_WORD ; return ( GET_MODE_SIZE ( mode ) + reg_size - 1 ) / reg_size ; } </s>

Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE . This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers . POWER and PowerPC GPRs hold 32 bits worth ; PowerPC64 GPRs and FPRs point register holds 64 bits worth .


"Wrong register class for memory operand."

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> const TargetRegisterClass * getPointerRegClass ( const MachineFunction & MF , unsigned Kind = 0 ) const override { return & TL45 :: GRRegsRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> static rtx visium_libcall_value ( enum machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return visium_function_value_1 ( mode ) ; } </s>

Return an RTX representing the place where the library function result will be returned .


<s> const uint16_t * WDC65816RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_NoRegs_SaveList ; } </s>


<s> static void splitBlock ( MachineBasicBlock & MBB , MachineInstr & MI , MachineDominatorTree * MDT ) { MachineBasicBlock * SplitBB = MBB . splitAt ( MI , true ) ; using DomTreeT = DomTreeBase < MachineBasicBlock > ; SmallVector < DomTreeT :: UpdateType , 16 > DTUpdates ; for ( MachineBasicBlock * Succ : SplitBB -> successors ( ) ) { DTUpdates . push_back ( { DomTreeT :: Insert , SplitBB , Succ } ) ; DTUpdates . push_back ( { DomTreeT :: Delete , & MBB , Succ } ) ; } DTUpdates . push_back ( { DomTreeT :: Insert , & MBB , SplitBB } ) ; MDT -> getBase ( ) . applyUpdates ( DTUpdates ) ; } </s>

splitBlock - BB is split and now it has one successor .


<s> TargetPassConfig * AGCTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new AGCPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool X86TTIImpl :: areInlineCompatible ( const Function * Caller , const Function * Callee ) const { const TargetMachine & TM = getTLI ( ) -> getTargetMachine ( ) ; const FeatureBitset & CallerBits = TM . getSubtargetImpl ( * Caller ) -> getFeatureBits ( ) ; const FeatureBitset & CalleeBits = TM . getSubtargetImpl ( * Callee ) -> getFeatureBits ( ) ; FeatureBitset RealCallerBits = CallerBits & ~ InlineFeatureIgnoreList ; FeatureBitset RealCalleeBits = CalleeBits & ~ InlineFeatureIgnoreList ; if ( RealCallerBits == RealCalleeBits ) return true ; if ( ( RealCallerBits & RealCalleeBits ) != RealCalleeBits ) return false ; for ( const Instruction & I : instructions ( Callee ) ) { if ( const auto * CB = dyn_cast < CallBase > ( & I ) ) { SmallVector < Type * , 8 > Types ; for ( Value * Arg : CB -> args ( ) ) Types . push_back ( Arg -> getType ( ) ) ; if ( ! CB -> getType ( ) -> isVoidTy ( ) ) Types . push_back ( CB -> getType ( ) ) ; auto IsSimpleTy = [ ] ( Type * Ty ) { return ! Ty -> isVectorTy ( ) && ! Ty -> isAggregateType ( ) ; } ; if ( all_of ( Types , IsSimpleTy ) ) continue ; if ( Function * NestedCallee = CB -> getCalledFunction ( ) ) { if ( NestedCallee -> isIntrinsic ( ) ) continue ; if ( ! areTypesABICompatible ( Caller , NestedCallee , Types ) ) return false ; } else { return false ; } } } return true ; } </s>

Determine whether a callee with the given TLI can be inlined into caller with this TLI , based on 'nobuiltin ' attributes .


<s> int SPURegisterInfo :: getDwarfRegNum ( unsigned RegNum , bool isEH ) const { return SPUGenRegisterInfo :: getDwarfRegNumFull ( RegNum , 0 ) ; } </s>

Map a target register to an equivalent dwarf register number .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 DAG->DAG Instruction Selection"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static void rename_fma_node ( fma_forest * forest , fma_node * node ) { node -> rename ( forest ) ; } </s>

Wrapper around fma_node : :dump_info for use as parameter of function pointer type in func_fma_steering : :dfs .


<s> uint32_t ARMMCCodeEmitter :: getBranchTargetOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { if ( isThumb2 ( ) ) return :: getBranchTargetOpValue ( MI , OpIdx , ARM :: fixup_t2_condbranch , Fixups ) ; return getARMBranchTargetOpValue ( MI , OpIdx , Fixups ) ; } </s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s> bool PPCTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( DisablePPCPreinc ) return false ; SDValue Ptr ; EVT VT ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; } else return false ; if ( VT . isVector ( ) ) return false ; if ( SelectAddressRegReg ( Ptr , Offset , Base , DAG ) ) { AM = ISD :: PRE_INC ; return true ; } if ( VT != MVT :: i64 ) { if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG ) ) return false ; } else { if ( ! SelectAddressRegImmShift ( Ptr , Offset , Base , DAG ) ) return false ; } if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { if ( LD -> getValueType ( 0 ) == MVT :: i64 && LD -> getMemoryVT ( ) == MVT :: i32 && LD -> getExtensionType ( ) == ISD :: SEXTLOAD && isa < ConstantSDNode > ( Offset ) ) return false ; } AM = ISD :: PRE_INC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .


<s> const char * PPCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case PPCISD :: FSEL : return "PPCISD::FSEL" ; case PPCISD :: FCFID : return "PPCISD::FCFID" ; case PPCISD :: FCTIDZ : return "PPCISD::FCTIDZ" ; case PPCISD :: FCTIWZ : return "PPCISD::FCTIWZ" ; case PPCISD :: STFIWX : return "PPCISD::STFIWX" ; case PPCISD :: VMADDFP : return "PPCISD::VMADDFP" ; case PPCISD :: VNMSUBFP : return "PPCISD::VNMSUBFP" ; case PPCISD :: VPERM : return "PPCISD::VPERM" ; case PPCISD :: Hi : return "PPCISD::Hi" ; case PPCISD :: Lo : return "PPCISD::Lo" ; case PPCISD :: TOC_ENTRY : return "PPCISD::TOC_ENTRY" ; case PPCISD :: TOC_RESTORE : return "PPCISD::TOC_RESTORE" ; case PPCISD :: LOAD : return "PPCISD::LOAD" ; case PPCISD :: LOAD_TOC : return "PPCISD::LOAD_TOC" ; case PPCISD :: DYNALLOC : return "PPCISD::DYNALLOC" ; case PPCISD :: GlobalBaseReg : return "PPCISD::GlobalBaseReg" ; case PPCISD :: SRL : return "PPCISD::SRL" ; case PPCISD :: SRA : return "PPCISD::SRA" ; case PPCISD :: SHL : return "PPCISD::SHL" ; case PPCISD :: EXTSW_32 : return "PPCISD::EXTSW_32" ; case PPCISD :: STD_32 : return "PPCISD::STD_32" ; case PPCISD :: CALL_SVR4 : return "PPCISD::CALL_SVR4" ; case PPCISD :: CALL_NOP_SVR4 : return "PPCISD::CALL_NOP_SVR4" ; case PPCISD :: CALL_Darwin : return "PPCISD::CALL_Darwin" ; case PPCISD :: NOP : return "PPCISD::NOP" ; case PPCISD :: MTCTR : return "PPCISD::MTCTR" ; case PPCISD :: BCTRL_Darwin : return "PPCISD::BCTRL_Darwin" ; case PPCISD :: BCTRL_SVR4 : return "PPCISD::BCTRL_SVR4" ; case PPCISD :: RET_FLAG : return "PPCISD::RET_FLAG" ; case PPCISD :: MFCR : return "PPCISD::MFCR" ; case PPCISD :: VCMP : return "PPCISD::VCMP" ; case PPCISD :: VCMPo : return "PPCISD::VCMPo" ; case PPCISD :: LBRX : return "PPCISD::LBRX" ; case PPCISD :: STBRX : return "PPCISD::STBRX" ; case PPCISD :: LARX : return "PPCISD::LARX" ; case PPCISD :: STCX : return "PPCISD::STCX" ; case PPCISD :: COND_BRANCH : return "PPCISD::COND_BRANCH" ; case PPCISD :: MFFS : return "PPCISD::MFFS" ; case PPCISD :: MTFSB0 : return "PPCISD::MTFSB0" ; case PPCISD :: MTFSB1 : return "PPCISD::MTFSB1" ; case PPCISD :: FADDRTZ : return "PPCISD::FADDRTZ" ; case PPCISD :: MTFSF : return "PPCISD::MTFSF" ; case PPCISD :: TC_RETURN : return "PPCISD::TC_RETURN" ; case PPCISD :: CR6SET : return "PPCISD::CR6SET" ; case PPCISD :: CR6UNSET : return "PPCISD::CR6UNSET" ; case PPCISD :: ADDIS_TOC_HA : return "PPCISD::ADDIS_TOC_HA" ; case PPCISD :: LD_TOC_L : return "PPCISD::LD_TOC_L" ; case PPCISD :: ADDI_TOC_L : return "PPCISD::ADDI_TOC_L" ; case PPCISD :: ADDIS_GOT_TPREL_HA : return "PPCISD::ADDIS_GOT_TPREL_HA" ; case PPCISD :: LD_GOT_TPREL_L : return "PPCISD::LD_GOT_TPREL_L" ; case PPCISD :: ADD_TLS : return "PPCISD::ADD_TLS" ; case PPCISD :: ADDIS_TLSGD_HA : return "PPCISD::ADDIS_TLSGD_HA" ; case PPCISD :: ADDI_TLSGD_L : return "PPCISD::ADDI_TLSGD_L" ; case PPCISD :: GET_TLS_ADDR : return "PPCISD::GET_TLS_ADDR" ; case PPCISD :: ADDIS_TLSLD_HA : return "PPCISD::ADDIS_TLSLD_HA" ; case PPCISD :: ADDI_TLSLD_L : return "PPCISD::ADDI_TLSLD_L" ; case PPCISD :: GET_TLSLD_ADDR : return "PPCISD::GET_TLSLD_ADDR" ; case PPCISD :: ADDIS_DTPREL_HA : return "PPCISD::ADDIS_DTPREL_HA" ; case PPCISD :: ADDI_DTPREL_L : return "PPCISD::ADDI_DTPREL_L" ; case PPCISD :: VADD_SPLAT : return "PPCISD::VADD_SPLAT" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static rtx nvptx_gen_pack ( rtx dst , rtx src0 , rtx src1 ) { rtx res ; switch ( GET_MODE ( dst ) ) { case E_DImode : res = gen_packsidi2 ( dst , src0 , src1 ) ; break ; case E_DFmode : res = gen_packsidf2 ( dst , src0 , src1 ) ; break ; default : gcc_unreachable ( ) ; } return res ; } </s>

Generate instruction ( s ) to pack 2 32 bit objects into a 64 bit object .


<s> static rtx vax_function_arg ( cumulative_args_t , const function_arg_info & ) { return NULL_RTX ; } </s>


<s> bool MipsSEFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == Mips :: RA || Reg == Mips :: RA_64 ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) MBB . addLiveIn ( Reg ) ; bool IsLOHI = ( Reg == Mips :: LO0 || Reg == Mips :: LO0_64 || Reg == Mips :: HI0 || Reg == Mips :: HI0_64 ) ; const Function & Func = MBB . getParent ( ) -> getFunction ( ) ; if ( IsLOHI && Func . hasFnAttribute ( "interrupt" ) ) { DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Op = 0 ; if ( ! STI . getABI ( ) . ArePtrs64bit ( ) ) { Op = ( Reg == Mips :: HI0 ) ? Mips :: MFHI : Mips :: MFLO ; Reg = Mips :: K0 ; } else { Op = ( Reg == Mips :: HI0 ) ? Mips :: MFHI64 : Mips :: MFLO64 ; Reg = Mips :: K0_64 ; } BuildMI ( MBB , MI , DL , TII . get ( Op ) , Mips :: K0 ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"WDC65816 Assembly Printer"
;
}
</s>


<s> void reset ( ) { Packet . clear ( ) ; ResourcesModel -> clearResources ( ) ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s> int sh_attr_renesas_p ( tree td ) { if ( TARGET_HITACHI ) return 1 ; if ( td == 0 ) return 0 ; if ( DECL_P ( td ) ) td = TREE_TYPE ( td ) ; if ( td == error_mark_node ) return 0 ; return ( lookup_attribute ( "renesas" , TYPE_ATTRIBUTES ( td ) ) != NULL_TREE ) ; } </s>

True if __attribute__ ( ( renesas ) ) or -mrenesas .


"argument to %qs must be a 2-bit unsigned literal"


<s>
void
VEFrameLowering
::
determineCalleeSaves
(
MachineFunction
&
MF
,
BitVector
&
SavedRegs
,
RegScavenger
*
RS
)
const
{
TargetFrameLowering
::
determineCalleeSaves
(
MF
,
SavedRegs
,
RS
)
;
assert
(
isLeafProc
(
MF
)
&&
"TODO implement for non-leaf procs"
)
;
}
</s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .

VE
VE
"TODO implement for non-leaf procs"


<s> static void dump_forest_info ( fma_forest * forest ) { forest -> dump_info ( ) ; } </s>

Wrapper around fma_forest : :dump_info for use as parameter of function pointer type in func_fma_steering : :dfs .


<s> int xtensa_emit_move_sequence ( rtx * operands , machine_mode mode ) { rtx src = operands [ 1 ] ; if ( CONSTANT_P ( src ) && ( GET_CODE ( src ) != CONST_INT || ! xtensa_simm12b ( INTVAL ( src ) ) ) ) { rtx dst = operands [ 0 ] ; if ( xtensa_tls_referenced_p ( src ) ) { rtx addend = NULL ; if ( GET_CODE ( src ) == CONST && GET_CODE ( XEXP ( src , 0 ) ) == PLUS ) { addend = XEXP ( XEXP ( src , 0 ) , 1 ) ; src = XEXP ( XEXP ( src , 0 ) , 0 ) ; } src = xtensa_legitimize_tls_address ( src ) ; if ( addend ) { src = gen_rtx_PLUS ( mode , src , addend ) ; src = force_operand ( src , dst ) ; } emit_move_insn ( dst , src ) ; return 1 ; } if ( ! TARGET_AUTO_LITPOOLS && ! TARGET_CONST16 ) { if ( optimize_size && mode == SImode && CONST_INT_P ( src ) && register_operand ( dst , mode ) ) { HOST_WIDE_INT srcval = INTVAL ( src ) ; int shift = ctz_hwi ( srcval ) ; if ( xtensa_simm12b ( srcval >> shift ) ) { emit_move_insn ( dst , GEN_INT ( srcval >> shift ) ) ; emit_insn ( gen_ashlsi3_internal ( dst , dst , GEN_INT ( shift ) ) ) ; return 1 ; } } src = force_const_mem ( SImode , src ) ; operands [ 1 ] = src ; } if ( mode != SImode ) { if ( register_operand ( dst , mode ) ) { emit_move_insn ( simplify_gen_subreg ( SImode , dst , mode , 0 ) , src ) ; return 1 ; } else { src = force_reg ( SImode , src ) ; src = gen_lowpart_SUBREG ( mode , src ) ; operands [ 1 ] = src ; } } } if ( ! ( reload_in_progress | reload_completed ) && ! xtensa_valid_move ( mode , operands ) ) operands [ 1 ] = force_reg ( mode , operands [ 1 ] ) ; operands [ 1 ] = xtensa_copy_incoming_a7 ( operands [ 1 ] ) ; if ( reload_in_progress ) { operands [ 0 ] = fixup_subreg_mem ( operands [ 0 ] ) ; operands [ 1 ] = fixup_subreg_mem ( operands [ 1 ] ) ; } return 0 ; } </s>

Emit insns to move operands [ 1 ] into operands [ 0 ] . Return 1 if we have written out everything that needs to be done to do the move . Otherwise , return 0 and the caller will emit the move normally .


"MIPS: Optimize calls to math library functions."


<s> int ix86_expand_fp_movcc ( rtx operands [ ] ) { enum machine_mode mode = GET_MODE ( operands [ 0 ] ) ; enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; rtx tmp , compare_op , second_test , bypass_test ; if ( TARGET_SSE_MATH && SSE_FLOAT_MODE_P ( mode ) ) { enum machine_mode cmode ; cmode = GET_MODE ( ix86_compare_op0 ) ; if ( cmode == VOIDmode ) cmode = GET_MODE ( ix86_compare_op1 ) ; if ( cmode != mode ) return 0 ; code = ix86_prepare_sse_fp_compare_args ( operands [ 0 ] , code , & ix86_compare_op0 , & ix86_compare_op1 ) ; if ( code == UNKNOWN ) return 0 ; if ( ix86_expand_sse_fp_minmax ( operands [ 0 ] , code , ix86_compare_op0 , ix86_compare_op1 , operands [ 2 ] , operands [ 3 ] ) ) return 1 ; tmp = ix86_expand_sse_cmp ( operands [ 0 ] , code , ix86_compare_op0 , ix86_compare_op1 , operands [ 2 ] , operands [ 3 ] ) ; ix86_expand_sse_movcc ( operands [ 0 ] , tmp , operands [ 2 ] , operands [ 3 ] ) ; return 1 ; } compare_op = ix86_expand_compare ( code , & second_test , & bypass_test ) ; if ( ! fcmov_comparison_operator ( compare_op , VOIDmode ) ) { gcc_assert ( ! second_test && ! bypass_test ) ; tmp = gen_reg_rtx ( QImode ) ; ix86_expand_setcc ( code , tmp ) ; code = NE ; ix86_compare_op0 = tmp ; ix86_compare_op1 = const0_rtx ; compare_op = ix86_expand_compare ( code , & second_test , & bypass_test ) ; } if ( bypass_test && reg_overlap_mentioned_p ( operands [ 0 ] , operands [ 3 ] ) ) { tmp = gen_reg_rtx ( mode ) ; emit_move_insn ( tmp , operands [ 3 ] ) ; operands [ 3 ] = tmp ; } if ( second_test && reg_overlap_mentioned_p ( operands [ 0 ] , operands [ 2 ] ) ) { tmp = gen_reg_rtx ( mode ) ; emit_move_insn ( tmp , operands [ 2 ] ) ; operands [ 2 ] = tmp ; } emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , gen_rtx_IF_THEN_ELSE ( mode , compare_op , operands [ 2 ] , operands [ 3 ] ) ) ) ; if ( bypass_test ) emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , gen_rtx_IF_THEN_ELSE ( mode , bypass_test , operands [ 3 ] , operands [ 0 ] ) ) ) ; if ( second_test ) emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , gen_rtx_IF_THEN_ELSE ( mode , second_test , operands [ 2 ] , operands [ 0 ] ) ) ) ; return 1 ; } </s>

Expand a floating-point conditional move . Return true if successful .


<s> static void load_pic_register ( bool delay_pic_helper ATTRIBUTE_UNUSED ) { int orig_flag_pic = flag_pic ; rtx got_symbol = tilegx_got_symbol ( ) ; rtx text_label_symbol = tilegx_text_label_symbol ( ) ; rtx text_label_rtx = tilegx_text_label_rtx ( ) ; flag_pic = 0 ; if ( TARGET_32BIT ) { emit_insn ( gen_insn_lnk_and_label_32bit ( text_label_rtx , text_label_symbol ) ) ; } else { emit_insn ( gen_insn_lnk_and_label ( text_label_rtx , text_label_symbol ) ) ; } tilegx_compute_pcrel_address ( tilegx_got_rtx ( ) , got_symbol ) ; flag_pic = orig_flag_pic ; emit_use ( tilegx_got_rtx ( ) ) ; } </s>


<s> unsigned PPCTargetLowering :: getByValTypeAlignment ( Type * Ty , const DataLayout & DL ) const { if ( Subtarget . isDarwin ( ) ) return 4 ; unsigned Align = Subtarget . isPPC64 ( ) ? 8 : 4 ; if ( Subtarget . hasAltivec ( ) || Subtarget . hasQPX ( ) ) getMaxByValAlign ( Ty , Align , Subtarget . hasQPX ( ) ? 32 : 16 ) ; return Align ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


<s> const TargetRegisterClass * NyuziRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & Nyuzi :: GPR32RegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> bool MipsLongBranch :: runOnMachineFunction ( MachineFunction & F ) { if ( ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) && TM . getSubtarget < MipsSubtarget > ( ) . isABI_O32 ( ) && F . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; SmallVector < MBBInfo , 16 > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; if ( ! ForceLongBranch && isInt < 16 > ( computeOffset ( I -> Br ) / 4 ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * 4 ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { uint64_t Address = 0 ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ; } for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) if ( I -> HasLongBranch ) expandToLongBranch ( * I ) ; MF -> RenumberBlocks ( ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool RISCVTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( AM . BaseGV ) return false ; if ( ! isInt < 12 > ( AM . BaseOffs ) ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( ! AM . HasBaseReg ) break ; return false ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> int ix86_can_use_return_insn_p ( void ) { struct ix86_frame frame ; if ( ! reload_completed || frame_pointer_needed ) return 0 ; if ( current_function_pops_args && current_function_args_size >= 32768 ) return 0 ; ix86_compute_frame_layout ( & frame ) ; return frame . to_allocate == 0 && frame . nregs == 0 ; } </s>

Return 1 if it is appropriate to emit ` ret ' instructions in the body of a function . Do this only if the epilogue is simple , needing a couple of insns . Prior to reloading , we ca n't tell how many registers must be saved , so return 0 then . Return 0 if there is no frame marker to de-allocate .


<s> static unsigned int aarch64_classify_vector_mode ( machine_mode mode ) { if ( aarch64_advsimd_struct_mode_p ( mode ) ) return VEC_ADVSIMD | VEC_STRUCT ; if ( aarch64_sve_pred_mode_p ( mode ) ) return VEC_SVE_PRED ; scalar_mode inner = GET_MODE_INNER ( mode ) ; if ( VECTOR_MODE_P ( mode ) && ( inner == QImode || inner == HImode || inner == HFmode || inner == SImode || inner == SFmode || inner == DImode || inner == DFmode ) ) { if ( TARGET_SVE ) { if ( known_eq ( GET_MODE_BITSIZE ( mode ) , BITS_PER_SVE_VECTOR ) ) return VEC_SVE_DATA ; if ( known_eq ( GET_MODE_BITSIZE ( mode ) , BITS_PER_SVE_VECTOR * 2 ) || known_eq ( GET_MODE_BITSIZE ( mode ) , BITS_PER_SVE_VECTOR * 3 ) || known_eq ( GET_MODE_BITSIZE ( mode ) , BITS_PER_SVE_VECTOR * 4 ) ) return VEC_SVE_DATA | VEC_STRUCT ; } if ( TARGET_SIMD && ( known_eq ( GET_MODE_BITSIZE ( mode ) , 64 ) || known_eq ( GET_MODE_BITSIZE ( mode ) , 128 ) ) ) return VEC_ADVSIMD ; } return 0 ; } </s>

Return a set of flags describing the vector properties of mode MODE . Ignore modes that are not supported by the current target .


<s> void addFastRegAlloc ( ) override { addPass ( createTPCExpandHWRegCopies ( ) ) ; addPass ( & LiveVariablesID , false ) ; addPass ( & PHIEliminationID , false ) ; addPass ( & TwoAddressInstructionPassID , false ) ; addPass ( & RegisterCoalescerID ) ; addPass ( createRegAllocPass ( true ) ) ; addPreRewrite ( ) ; addPass ( & VirtRegRewriterID ) ; } </s>

addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast register allocation .


<s> bool SystemZMCAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { for ( uint64_t I = 0 ; I != Count ; ++ I ) OS << '\x7' ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> bool AArch64AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( Count % 4 != 0 ) return false ; uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> Write32 ( 0xd503201f ) ; return true ; } </s>


<s> bool NVPTXAsmPrinter :: doFinalization ( Module & M ) { Module :: GlobalListType & global_list = M . getGlobalList ( ) ; int i , n = global_list . size ( ) ; GlobalVariable * * gv_array = new GlobalVariable * [ n ] ; i = 0 ; for ( Module :: global_iterator I = global_list . begin ( ) , E = global_list . end ( ) ; I != E ; ++ I ) gv_array [ i ++ ] = & * I ; while ( ! global_list . empty ( ) ) global_list . remove ( global_list . begin ( ) ) ; bool ret = AsmPrinter :: doFinalization ( M ) ; for ( i = 0 ; i < n ; i ++ ) global_list . insert ( global_list . end ( ) , gv_array [ i ] ) ; delete [ ] gv_array ; return ret ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> bool PPCTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( DisablePPCPreinc ) return false ; bool isLoad = true ; SDValue Ptr ; EVT VT ; unsigned Alignment ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; Alignment = LD -> getAlignment ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Alignment = ST -> getAlignment ( ) ; isLoad = false ; } else return false ; if ( VT . isVector ( ) ) { if ( ! Subtarget . hasQPX ( ) || ( VT != MVT :: v4f64 && VT != MVT :: v4f32 ) ) { return false ; } else if ( SelectAddressRegRegOnly ( Ptr , Offset , Base , DAG ) ) { AM = ISD :: PRE_INC ; return true ; } } if ( SelectAddressRegReg ( Ptr , Base , Offset , DAG ) ) { bool Swap = false ; if ( isa < FrameIndexSDNode > ( Base ) || isa < RegisterSDNode > ( Base ) ) Swap = true ; else if ( ! isLoad ) { SDValue Val = cast < StoreSDNode > ( N ) -> getValue ( ) ; if ( Val == Base || Base . getNode ( ) -> isPredecessorOf ( Val . getNode ( ) ) ) Swap = true ; } if ( Swap ) std :: swap ( Base , Offset ) ; AM = ISD :: PRE_INC ; return true ; } if ( VT != MVT :: i64 ) { if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , false ) ) return false ; } else { if ( Alignment < 4 ) return false ; if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , true ) ) return false ; } if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { if ( LD -> getValueType ( 0 ) == MVT :: i64 && LD -> getMemoryVT ( ) == MVT :: i32 && LD -> getExtensionType ( ) == ISD :: SEXTLOAD && isa < ConstantSDNode > ( Offset ) ) return false ; } AM = ISD :: PRE_INC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .


<s> bool ARMOptimizeBarriersPass :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; std :: vector < MachineInstr * > ToRemove ; int64_t DMBType = - 1 ; for ( auto & MBB : MF ) { bool IsRemovableNextDMB = false ; for ( auto & MI : MBB ) { if ( MI . getOpcode ( ) == ARM :: DMB ) { if ( IsRemovableNextDMB ) { if ( MI . getOperand ( 0 ) . getImm ( ) == DMBType ) { ToRemove . push_back ( & MI ) ; } else { DMBType = MI . getOperand ( 0 ) . getImm ( ) ; } } else { IsRemovableNextDMB = true ; DMBType = MI . getOperand ( 0 ) . getImm ( ) ; } } else if ( ! CanMovePastDMB ( & MI ) ) { IsRemovableNextDMB = false ; } } } for ( auto MI : ToRemove ) { MI -> eraseFromParent ( ) ; ++ NumDMBsRemoved ; } return NumDMBsRemoved > 0 ; } </s>


<s> rtx nds32_legitimize_tls_address ( rtx x ) { rtx tmp_reg ; rtx tp_reg = gen_rtx_REG ( Pmode , TP_REGNUM ) ; rtx pat , insns , reg0 ; int relax_group_id = nds32_alloc_relax_group_id ( ) ; if ( GET_CODE ( x ) == SYMBOL_REF ) switch ( SYMBOL_REF_TLS_MODEL ( x ) ) { case TLS_MODEL_GLOBAL_DYNAMIC : case TLS_MODEL_LOCAL_DYNAMIC : if ( SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_GLOBAL_DYNAMIC ) pat = gen_rtx_UNSPEC ( SImode , gen_rtvec ( 1 , x ) , UNSPEC_TLSGD ) ; else pat = gen_rtx_UNSPEC ( SImode , gen_rtvec ( 1 , x ) , UNSPEC_TLSLD ) ; pat = gen_rtx_CONST ( SImode , pat ) ; reg0 = gen_rtx_REG ( Pmode , 0 ) ; insns = emit_call_insn ( gen_tls_desc ( pat , GEN_INT ( relax_group_id ) ) ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insns ) , pic_offset_table_rtx ) ; RTL_CONST_CALL_P ( insns ) = 1 ; tmp_reg = gen_reg_rtx ( SImode ) ; emit_move_insn ( tmp_reg , reg0 ) ; x = tmp_reg ; break ; case TLS_MODEL_INITIAL_EXEC : pat = gen_rtx_UNSPEC ( SImode , gen_rtvec ( 1 , x ) , UNSPEC_TLSIE ) ; tmp_reg = gen_reg_rtx ( SImode ) ; pat = gen_rtx_CONST ( SImode , pat ) ; emit_insn ( gen_tls_ie ( tmp_reg , pat , GEN_INT ( relax_group_id ) ) ) ; if ( flag_pic ) emit_use ( pic_offset_table_rtx ) ; x = gen_rtx_PLUS ( Pmode , tmp_reg , tp_reg ) ; break ; case TLS_MODEL_LOCAL_EXEC : tmp_reg = gen_reg_rtx ( SImode ) ; pat = gen_rtx_UNSPEC ( SImode , gen_rtvec ( 1 , x ) , UNSPEC_TLSLE ) ; pat = gen_rtx_CONST ( SImode , pat ) ; emit_insn ( gen_tls_le ( tmp_reg , pat , GEN_INT ( relax_group_id ) ) ) ; x = gen_rtx_PLUS ( Pmode , tmp_reg , tp_reg ) ; break ; default : gcc_unreachable ( ) ; } else if ( GET_CODE ( x ) == CONST ) { rtx base , addend ; split_const ( x , & base , & addend ) ; if ( SYMBOL_REF_TLS_MODEL ( base ) == TLS_MODEL_LOCAL_EXEC ) { tmp_reg = gen_reg_rtx ( SImode ) ; pat = gen_rtx_UNSPEC ( SImode , gen_rtvec ( 1 , base ) , UNSPEC_TLSLE ) ; pat = gen_rtx_PLUS ( SImode , pat , addend ) ; pat = gen_rtx_CONST ( SImode , pat ) ; emit_insn ( gen_tls_le ( tmp_reg , pat , GEN_INT ( relax_group_id ) ) ) ; x = gen_rtx_PLUS ( Pmode , tmp_reg , tp_reg ) ; } } return x ; } </s>

ADDR contains a thread-local SYMBOL_REF . Generate code to compute this ( thread-local ) address .


<s> static int compare_sign_p ( rtx insn ) { RTX_CODE cond = compare_condition ( insn ) ; return ( cond == GE || cond == LT ) ; } </s>

Returns nonzero if INSN is a tst insn that only tests the sign .


<s> rtx arm_function_value ( tree type , tree func ATTRIBUTE_UNUSED ) { enum machine_mode mode ; int unsignedp ATTRIBUTE_UNUSED ; rtx r ATTRIBUTE_UNUSED ; mode = TYPE_MODE ( type ) ; if ( INTEGRAL_TYPE_P ( type ) ) PROMOTE_FUNCTION_MODE ( mode , unsignedp , type ) ; if ( arm_return_in_msb ( type ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; if ( size % UNITS_PER_WORD != 0 ) { size += UNITS_PER_WORD - size % UNITS_PER_WORD ; mode = mode_for_size ( size * BITS_PER_UNIT , MODE_INT , 0 ) ; } } return LIBCALL_VALUE ( mode ) ; } </s>

Define how to find the value returned by a function .


"Instruction should be in a basic block!"

"Generic instruction has unexpected implicit operands\n"

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s>
bool
FalkorHWPFFix
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
auto
&
ST
=
static_cast
<
const
AArch64Subtarget
&
>
(
Fn
.
getSubtarget
(
)
)
;
if
(
ST
.
getProcFamily
(
)
!=
AArch64Subtarget
::
Falkor
)
return
false
;
if
(
skipFunction
(
*
Fn
.
getFunction
(
)
)
)
return
false
;
TII
=
static_cast
<
const
AArch64InstrInfo
*
>
(
ST
.
getInstrInfo
(
)
)
;
TRI
=
ST
.
getRegisterInfo
(
)
;
assert
(
TRI
->
trackLivenessAfterRegAlloc
(
Fn
)
&&
"Register liveness not available!"
)
;
MachineLoopInfo
&
LI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
Modified
=
false
;
for
(
MachineLoop
*
I
:
LI
)
for
(
auto
L
=
df_begin
(
I
)
,
LE
=
df_end
(
I
)
;
L
!=
LE
;
++
L
)
if
(
L
->
empty
(
)
)
runOnLoop
(
*
*
L
,
Fn
)
;
return
Modified
;
}
</s>


<s> SDNode * LEGDAGToDAGISel :: Select ( SDNode * N ) { switch ( N -> getOpcode ( ) ) { case ISD :: Constant : return SelectMoveImmediate ( N ) ; case ISD :: BR_CC : return SelectConditionalBranch ( N ) ; } return SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> virtual const PTXInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> static void asm_print_register ( FILE * file , int regno ) { const char * name = reg_names [ regno ] ; if ( TARGET_NO_DIRECT_MODE && name [ 0 ] == '*' ) name ++ ; fprintf ( file , "%s" , name ) ; } </s>

Print the name of register 'regno ' in the assembly file .


"Instr doesn't have FrameIndex operand!"

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s> const ELFNote * getNext ( const ELFNote & N ) { return reinterpret_cast < const ELFNote * > ( N . getDesc ( ) . data ( ) + alignTo ( N . descsz , ELFNote :: ALIGN ) ) ; } </s>


<s> virtual const BlackfinInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> bool ARMBaseInstrInfo :: areLoadsFromSameBasePtr ( SDNode * Load1 , SDNode * Load2 , int64_t & Offset1 , int64_t & Offset2 ) const { if ( Subtarget . isThumb1Only ( ) ) return false ; if ( ! Load1 -> isMachineOpcode ( ) || ! Load2 -> isMachineOpcode ( ) ) return false ; switch ( Load1 -> getMachineOpcode ( ) ) { default : return false ; case ARM :: LDRi12 : case ARM :: LDRBi12 : case ARM :: LDRD : case ARM :: LDRH : case ARM :: LDRSB : case ARM :: LDRSH : case ARM :: VLDRD : case ARM :: VLDRS : case ARM :: t2LDRi8 : case ARM :: t2LDRDi8 : case ARM :: t2LDRSHi8 : case ARM :: t2LDRi12 : case ARM :: t2LDRSHi12 : break ; } switch ( Load2 -> getMachineOpcode ( ) ) { default : return false ; case ARM :: LDRi12 : case ARM :: LDRBi12 : case ARM :: LDRD : case ARM :: LDRH : case ARM :: LDRSB : case ARM :: LDRSH : case ARM :: VLDRD : case ARM :: VLDRS : case ARM :: t2LDRi8 : case ARM :: t2LDRDi8 : case ARM :: t2LDRSHi8 : case ARM :: t2LDRi12 : case ARM :: t2LDRSHi12 : break ; } if ( Load1 -> getOperand ( 0 ) != Load2 -> getOperand ( 0 ) || Load1 -> getOperand ( 4 ) != Load2 -> getOperand ( 4 ) ) return false ; if ( Load1 -> getOperand ( 3 ) != Load2 -> getOperand ( 3 ) ) return false ; if ( isa < ConstantSDNode > ( Load1 -> getOperand ( 1 ) ) && isa < ConstantSDNode > ( Load2 -> getOperand ( 1 ) ) ) { Offset1 = cast < ConstantSDNode > ( Load1 -> getOperand ( 1 ) ) -> getSExtValue ( ) ; Offset2 = cast < ConstantSDNode > ( Load2 -> getOperand ( 1 ) ) -> getSExtValue ( ) ; return true ; } return false ; } </s>

areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address .


<s>
bool
FixupLEAPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
const
X86Subtarget
&
ST
=
MF
.
getSubtarget
<
X86Subtarget
>
(
)
;
bool
IsSlowLEA
=
ST
.
slowLEA
(
)
;
bool
IsSlow3OpsLEA
=
ST
.
slow3OpsLEA
(
)
;
bool
LEAUsesAG
=
ST
.
LEAusesAG
(
)
;
bool
OptIncDec
=
!
ST
.
slowIncDec
(
)
||
MF
.
getFunction
(
)
.
hasOptSize
(
)
;
bool
UseLEAForSP
=
ST
.
useLeaForSP
(
)
;
TSM
.
init
(
&
ST
)
;
TII
=
ST
.
getInstrInfo
(
)
;
TRI
=
ST
.
getRegisterInfo
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Start X86FixupLEAs\n"
;
)
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
for
(
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
;
I
!=
MBB
.
end
(
)
;
++
I
)
{
if
(
!
isLEA
(
I
->
getOpcode
(
)
)
)
continue
;
if
(
optTwoAddrLEA
(
I
,
MBB
,
OptIncDec
,
UseLEAForSP
)
)
continue
;
if
(
IsSlowLEA
)
processInstructionForSlowLEA
(
I
,
MBB
)
;
else
if
(
IsSlow3OpsLEA
)
processInstrForSlow3OpLEA
(
I
,
MBB
,
OptIncDec
)
;
}
if
(
LEAUsesAG
)
{
for
(
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
;
I
!=
MBB
.
end
(
)
;
++
I
)
processInstruction
(
I
,
MBB
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
"End X86FixupLEAs\n"
;
)
;
return
true
;
}
</s>


<s> AArch64TargetLowering :: ConstraintType AArch64TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'x' : case 'w' : return C_RegisterClass ; case 'Q' : return C_Memory ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'Y' : case 'Z' : return C_Immediate ; case 'z' : case 'S' : return C_Other ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s>
const
MCPhysReg
*
AArch64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_AArch64_NoRegs_LR_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_AArch64_AllRegs_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetDarwin
(
)
)
return
getDarwinCalleeSavedRegs
(
MF
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
CFGuard_Check
)
return
CSR_Win_AArch64_CFGuard_Check_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetWindows
(
)
)
return
CSR_Win_AArch64_AAPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_VectorCall
)
return
CSR_AArch64_AAVPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_SVE_VectorCall
)
return
CSR_AArch64_SVE_AAPCS_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
.
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_AArch64_AAPCS_SwiftError_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
SwiftTail
)
return
CSR_AArch64_AAPCS_SwiftTail_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
PreserveMost
)
return
CSR_AArch64_RT_MostRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
Win64
)
return
CSR_AArch64_AAPCS_X18_SaveList
;
if
(
hasSVEArgsOrReturn
(
MF
)
)
return
CSR_AArch64_SVE_AAPCS_SaveList
;
return
CSR_AArch64_AAPCS_SaveList
;
}
</s>


<s> static void mips_print_operand_address ( FILE * file , machine_mode , rtx x ) { struct mips_address_info addr ; if ( mips_classify_address ( & addr , x , word_mode , true ) ) switch ( addr . type ) { case ADDRESS_REG : mips_print_operand ( file , addr . offset , 0 ) ; fprintf ( file , "(%s)" , reg_names [ REGNO ( addr . reg ) ] ) ; return ; case ADDRESS_LO_SUM : mips_print_operand_reloc ( file , addr . offset , SYMBOL_CONTEXT_MEM , mips_lo_relocs ) ; fprintf ( file , "(%s)" , reg_names [ REGNO ( addr . reg ) ] ) ; return ; case ADDRESS_CONST_INT : output_addr_const ( file , x ) ; fprintf ( file , "(%s)" , reg_names [ GP_REG_FIRST ] ) ; return ; case ADDRESS_SYMBOLIC : output_addr_const ( file , mips_strip_unspec_address ( x ) ) ; return ; } gcc_unreachable ( ) ; } </s>


<s> bool nios2_legitimate_pic_operand_p ( rtx x ) { if ( nios2_large_unspec_reloc_p ( x ) ) return true ; return ! ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF || GET_CODE ( x ) == CONST ) ; } </s>

Nonzero if the constant value X is a legitimate general operand when generating PIC code . It is given that flag_pic is on and that X satisfies CONSTANT_P or is a CONST_DOUBLE .


<s> Liveness ( MachineRegisterInfo & mri , const DataFlowGraph & g ) : DFG ( g ) , TRI ( g . getTRI ( ) ) , MDT ( g . getDT ( ) ) , MDF ( g . getDF ( ) ) , MRI ( mri ) , LiveMap ( g . getTRI ( ) ) , Empty ( ) , NoRegs ( g . getTRI ( ) ) , Trace ( false ) { } </s>

During our initial pass over the program , we determine that things are either alive or maybe alive . More ...


<s> static bool areOnlyUsersOf ( SDNode * N , ArrayRef < SDValue > ValidUsers ) { for ( SDNode :: use_iterator I = N -> use_begin ( ) , E = N -> use_end ( ) ; I != E ; ++ I ) if ( llvm :: all_of ( ValidUsers , [ & I ] ( SDValue V ) { return V . getNode ( ) != * I ; } ) ) return false ; return true ; } </s>

Return true if all the users of N are contained in Nodes .


<s> static void save_reg ( int regno , unsigned offset ) { rtx reg = gen_rtx_REG ( SImode , regno ) ; rtx addr = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , gen_int_mode ( offset , Pmode ) ) ; rtx insn = emit_move_insn ( gen_frame_mem ( Pmode , addr ) , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Generate save/restore of register REGNO at SP + OFFSET . Used by the prologue/epilogue expand routines .


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , CM , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , Subtarget ( TT , CPU , FS , * this , Options . StackAlignmentOverride ) { if ( Subtarget . isTargetWin64 ( ) || Subtarget . isTargetPS4 ( ) ) this -> Options . TrapUnreachable = true ; this -> Options . Reciprocals . setDefaults ( "sqrtf" , true , 1 ) ; this -> Options . Reciprocals . setDefaults ( "divf" , false , 1 ) ; this -> Options . Reciprocals . setDefaults ( "vec-sqrtf" , true , 1 ) ; this -> Options . Reciprocals . setDefaults ( "vec-divf" , true , 1 ) ; initAsmInfo ( ) ; } </s>


<s> bool RISCVMCAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { for ( uint64_t I = 0 ; I != Count ; ++ I ) OW -> write8 ( 7 ) ; return true ; } </s>


<s> void aarch64_split_simd_combine ( rtx dst , rtx src1 , rtx src2 ) { machine_mode src_mode = GET_MODE ( src1 ) ; machine_mode dst_mode = GET_MODE ( dst ) ; gcc_assert ( VECTOR_MODE_P ( dst_mode ) ) ; if ( REG_P ( dst ) && REG_P ( src1 ) && REG_P ( src2 ) ) { rtx ( * gen ) ( rtx , rtx , rtx ) ; switch ( src_mode ) { case V8QImode : gen = gen_aarch64_simd_combinev8qi ; break ; case V4HImode : gen = gen_aarch64_simd_combinev4hi ; break ; case V2SImode : gen = gen_aarch64_simd_combinev2si ; break ; case V2SFmode : gen = gen_aarch64_simd_combinev2sf ; break ; case DImode : gen = gen_aarch64_simd_combinedi ; break ; case DFmode : gen = gen_aarch64_simd_combinedf ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( dst , src1 , src2 ) ) ; return ; } } </s>


"SIInstrInfo::loadRegFromStackSlot - Do not know how to"

Load the specified register of the given register class from the specified stack frame index .


<s> bool Mips16FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * EntryBlock = & MF -> front ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == Mips :: RA ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> bool mayAlias ( const MachineFrameInfo * ) const override { return false ; } </s>

Returns true if this instruction 's memory access aliases the memory access of Other .


<s>
void
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
override
{
unsigned
Size
=
1
<<
getFixupKindLog2Size
(
Fixup
.
getKind
(
)
)
;
assert
(
Fixup
.
getOffset
(
)
+
Size
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
assert
(
isIntN
(
Size
*
8
+
1
,
Value
)
&&
"Value does not fit in the Fixup field"
)
;
for
(
unsigned
i
=
0
;
i
!=
Size
;
++
i
)
Data
[
Fixup
.
getOffset
(
)
+
i
]
=
uint8_t
(
Value
>>
(
i
*
8
)
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> int expand_block_clear ( rtx operands [ ] ) { rtx orig_dest = operands [ 0 ] ; rtx bytes_rtx = operands [ 1 ] ; rtx align_rtx = operands [ 3 ] ; bool constp = ( GET_CODE ( bytes_rtx ) == CONST_INT ) ; HOST_WIDE_INT align ; HOST_WIDE_INT bytes ; int offset ; int clear_bytes ; int clear_step ; if ( ! constp ) return 0 ; gcc_assert ( GET_CODE ( align_rtx ) == CONST_INT ) ; align = INTVAL ( align_rtx ) * BITS_PER_UNIT ; bytes = INTVAL ( bytes_rtx ) ; if ( bytes <= 0 ) return 1 ; if ( TARGET_ALTIVEC && align >= 128 ) clear_step = 16 ; else if ( TARGET_POWERPC64 && align >= 32 ) clear_step = 8 ; else clear_step = 4 ; if ( optimize_size && bytes > 3 * clear_step ) return 0 ; if ( ! optimize_size && bytes > 8 * clear_step ) return 0 ; for ( offset = 0 ; bytes > 0 ; offset += clear_bytes , bytes -= clear_bytes ) { enum machine_mode mode = BLKmode ; rtx dest ; if ( bytes >= 16 && TARGET_ALTIVEC && align >= 128 ) { clear_bytes = 16 ; mode = V4SImode ; } else if ( bytes >= 8 && TARGET_POWERPC64 && ( align >= 64 || ( ! STRICT_ALIGNMENT && align >= 32 ) ) ) { clear_bytes = 8 ; mode = DImode ; } else if ( bytes >= 4 && ( align >= 32 || ! STRICT_ALIGNMENT ) ) { clear_bytes = 4 ; mode = SImode ; } else if ( bytes >= 2 && ( align >= 16 || ! STRICT_ALIGNMENT ) ) { clear_bytes = 2 ; mode = HImode ; } else { clear_bytes = 1 ; mode = QImode ; } dest = adjust_address ( orig_dest , mode , offset ) ; emit_move_insn ( dest , CONST0_RTX ( mode ) ) ; } return 1 ; } </s>

Expand a block clear operation , and return 1 if successful . Return 0 if we should let the compiler generate normal code . operands [ 0 ] is the destination operands [ 1 ] is the length operands [ 3 ] is the alignment


<s> static rtx frv_expand_prefetches ( enum insn_code icode , tree arglist ) { rtx pat ; rtx op0 = frv_read_argument ( & arglist ) ; pat = GEN_FCN ( icode ) ( force_reg ( Pmode , op0 ) ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return 0 ; } </s>

Expand prefetch builtins . These take a single address as argument .


<s> unsigned SIRegisterInfo :: getRegPressureSetLimit ( unsigned Idx ) const { unsigned SGPRLimit = getNumSGPRsAllowed ( ST . getMaxWavesPerCU ( ) ) ; unsigned VGPRLimit = getNumVGPRsAllowed ( ST . getMaxWavesPerCU ( ) ) ; for ( regclass_iterator I = regclass_begin ( ) , E = regclass_end ( ) ; I != E ; ++ I ) { unsigned NumSubRegs = std :: max ( ( int ) ( * I ) -> getSize ( ) / 4 , 1 ) ; unsigned Limit ; if ( isSGPRClass ( * I ) ) { Limit = SGPRLimit / NumSubRegs ; } else { Limit = VGPRLimit / NumSubRegs ; } const int * Sets = getRegClassPressureSets ( * I ) ; assert ( Sets ) ; for ( unsigned i = 0 ; Sets [ i ] != - 1 ; ++ i ) { if ( Sets [ i ] == ( int ) Idx ) return Limit ; } } return 256 ; } </s>

Get the register unit pressure limit for this dimension .


"\nGCNUpwardRPTracker error: Tracked and"

"GCNUpwardRPTracker error: Pressure sets different\nTracked: "

Returns true if this iterator is still pointing at a valid entry .


<s>
const
char
*
nvptx_output_mov_insn
(
rtx
dst
,
rtx
src
)
{
machine_mode
dst_mode
=
GET_MODE
(
dst
)
;
machine_mode
dst_inner
=
(
GET_CODE
(
dst
)
==
SUBREG
GET_MODE
(
XEXP
(
dst
,
0
)
)
:
dst_mode
)
;
machine_mode
src_inner
=
(
GET_CODE
(
src
)
==
SUBREG
GET_MODE
(
XEXP
(
src
,
0
)
)
:
dst_mode
)
;
rtx
sym
=
src
;
if
(
GET_CODE
(
sym
)
==
CONST
)
sym
=
XEXP
(
XEXP
(
sym
,
0
)
,
0
)
;
if
(
SYMBOL_REF_P
(
sym
)
)
{
if
(
SYMBOL_DATA_AREA
(
sym
)
!=
DATA_AREA_GENERIC
)
return
"%.\tcvta%D1%t0\t%0, %1;"
;
nvptx_maybe_record_fnsym
(
sym
)
;
}
if
(
src_inner
==
dst_inner
)
return
"%.\tmov%t0\t%0, %1;"
;
if
(
CONSTANT_P
(
src
)
)
return
(
GET_MODE_CLASS
(
dst_inner
)
==
MODE_INT
&&
GET_MODE_CLASS
(
src_inner
)
!=
MODE_FLOAT
"%.\tmov%t0\t%0, %1;"
:
"%.\tmov.b%T0\t%0, %1;"
)
;
if
(
GET_MODE_SIZE
(
dst_inner
)
==
GET_MODE_SIZE
(
src_inner
)
)
return
"%.\tmov.b%T0\t%0, %1;"
;
return
"%.\tcvt%t0%t1\t%0, %1;"
;
}
</s>

Output a pattern for a move instruction .


<s> Liveness ( MachineRegisterInfo & mri , const DataFlowGraph & g ) : DFG ( g ) , TRI ( g . getTRI ( ) ) , PRI ( g . getPRI ( ) ) , MDT ( g . getDT ( ) ) , MDF ( g . getDF ( ) ) , LiveMap ( g . getPRI ( ) ) , Empty ( ) , NoRegs ( g . getPRI ( ) ) , Trace ( false ) { } </s>


<s> const char * getSymbol ( ) const { return S ; } </s>

Get the target address and flags for the named symbol .


<s>
void
xstormy16_asm_output_aligned_common
(
FILE
*
stream
,
tree
decl
,
const
char
*
name
,
int
size
,
int
align
,
int
global
)
{
rtx
mem
=
decl
==
NULL_TREE
NULL_RTX
:
DECL_RTL
(
decl
)
;
rtx
symbol
;
if
(
mem
!=
NULL_RTX
&&
MEM_P
(
mem
)
&&
GET_CODE
(
symbol
=
XEXP
(
mem
,
0
)
)
==
SYMBOL_REF
&&
SYMBOL_REF_FLAGS
(
symbol
)
&
SYMBOL_FLAG_XSTORMY16_BELOW100
)
{
const
char
*
name2
;
int
p2align
=
0
;
switch_to_section
(
bss100_section
)
;
while
(
align
>
8
)
{
align
/=
2
;
p2align
++
;
}
name2
=
default_strip_name_encoding
(
name
)
;
if
(
global
)
fprintf
(
stream
,
"\t.globl\t%s\n"
,
name2
)
;
if
(
p2align
)
fprintf
(
stream
,
"\t.p2align %d\n"
,
p2align
)
;
fprintf
(
stream
,
"\t.type\t%s, @object\n"
,
name2
)
;
fprintf
(
stream
,
"\t.size\t%s, %d\n"
,
name2
,
size
)
;
fprintf
(
stream
,
"%s:\n\t.space\t%d\n"
,
name2
,
size
)
;
return
;
}
if
(
!
global
)
{
fprintf
(
stream
,
"\t.local\t"
)
;
assemble_name
(
stream
,
name
)
;
fprintf
(
stream
,
"\n"
)
;
}
fprintf
(
stream
,
"\t.comm\t"
)
;
assemble_name
(
stream
,
name
)
;
fprintf
(
stream
,
",%u,%u\n"
,
size
,
align
/
BITS_PER_UNIT
)
;
}
</s>

The purpose of this function is to override the default behavior of BSS objects . Normally , they go into .bss or .sbss via `` .common '' directives , but we need to override that and put them in .bss_below100 . We ca n't just use a section override ( like we do for .data_below100 ) , because that makes them initialized rather than uninitialized .


<s> const unsigned * ARMRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const unsigned CalleeSavedRegs [ ] = { ARM :: LR , ARM :: R11 , ARM :: R10 , ARM :: R9 , ARM :: R8 , ARM :: R7 , ARM :: R6 , ARM :: R5 , ARM :: R4 , ARM :: D15 , ARM :: D14 , ARM :: D13 , ARM :: D12 , ARM :: D11 , ARM :: D10 , ARM :: D9 , ARM :: D8 , 0 } ; static const unsigned DarwinCalleeSavedRegs [ ] = { ARM :: LR , ARM :: R7 , ARM :: R6 , ARM :: R5 , ARM :: R4 , ARM :: R11 , ARM :: R10 , ARM :: R9 , ARM :: R8 , ARM :: D15 , ARM :: D14 , ARM :: D13 , ARM :: D12 , ARM :: D11 , ARM :: D10 , ARM :: D9 , ARM :: D8 , 0 } ; return STI . isTargetDarwin ( ) ? DarwinCalleeSavedRegs : CalleeSavedRegs ; } </s>


<s> static bool s390_adjust_loop_scan_osc ( struct loop * loop ) { HARD_REG_SET modregs , newregs ; rtx_insn * insn , * store_insn = NULL ; rtx set ; struct s390_address addr_store , addr_load ; subrtx_iterator :: array_type array ; int insn_count ; CLEAR_HARD_REG_SET ( modregs ) ; insn_count = 0 ; FOR_BB_INSNS_REVERSE ( loop -> latch , insn ) { if ( ! INSN_P ( insn ) || INSN_CODE ( insn ) <= 0 ) continue ; insn_count ++ ; if ( insn_count > S390_OSC_SCAN_INSN_NUM ) return false ; find_all_hard_reg_sets ( insn , & newregs , true ) ; modregs |= newregs ; set = single_set ( insn ) ; if ( ! set ) continue ; if ( MEM_P ( SET_DEST ( set ) ) && s390_decompose_address ( XEXP ( SET_DEST ( set ) , 0 ) , & addr_store ) ) { store_insn = insn ; break ; } } if ( store_insn == NULL_RTX ) return false ; insn_count = 0 ; FOR_BB_INSNS ( loop -> header , insn ) { if ( ! INSN_P ( insn ) || INSN_CODE ( insn ) <= 0 ) continue ; if ( insn == store_insn ) return false ; insn_count ++ ; if ( insn_count > S390_OSC_SCAN_INSN_NUM ) return false ; find_all_hard_reg_sets ( insn , & newregs , true ) ; modregs |= newregs ; set = single_set ( insn ) ; if ( ! set ) continue ; if ( MEM_P ( SET_DEST ( set ) ) && s390_decompose_address ( XEXP ( SET_DEST ( set ) , 0 ) , NULL ) ) return false ; FOR_EACH_SUBRTX ( iter , array , SET_SRC ( set ) , NONCONST ) if ( MEM_P ( * iter ) && s390_decompose_address ( XEXP ( * iter , 0 ) , & addr_load ) && rtx_equal_p ( addr_load . base , addr_store . base ) && rtx_equal_p ( addr_load . indx , addr_store . indx ) && rtx_equal_p ( addr_load . disp , addr_store . disp ) ) { if ( ( addr_load . base != NULL_RTX && TEST_HARD_REG_BIT ( modregs , REGNO ( addr_load . base ) ) ) || ( addr_load . indx != NULL_RTX && TEST_HARD_REG_BIT ( modregs , REGNO ( addr_load . indx ) ) ) ) return true ; } } return false ; } </s>

Scan LOOP for static OSC collisions and return true if a osc_break should be issued for this loop .


<s> unsigned SITargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( CC == CallingConv :: AMDGPU_KERNEL ) return TargetLowering :: getNumRegistersForCallingConv ( Context , CC , VT ) ; if ( VT . isVector ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; EVT ScalarVT = VT . getScalarType ( ) ; unsigned Size = ScalarVT . getSizeInBits ( ) ; if ( Size == 16 && Subtarget -> has16BitInsts ( ) ) return ( NumElts + 1 ) / 2 ; if ( Size <= 32 ) return NumElts ; if ( Size > 32 ) return NumElts * ( ( Size + 31 ) / 32 ) ; } else if ( VT . getSizeInBits ( ) > 32 ) return ( VT . getSizeInBits ( ) + 31 ) / 32 ; return TargetLowering :: getNumRegistersForCallingConv ( Context , CC , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s>
SDValue
TLCS900TargetLowering
::
LowerCall
(
SDValue
Chain
,
SDValue
Callee
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
bool
doesNotRet
,
bool
&
isTailCall
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
OutVals
,
Ins
,
dl
,
DAG
,
InVals
)
;
case
CallingConv
::
TLCS900_INTR
:
report_fatal_error
(
"ISRs cannot be called directly"
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .


<s> int arm_const_double_inline_cost ( rtx val ) { rtx lowpart , highpart ; machine_mode mode ; mode = GET_MODE ( val ) ; if ( mode == VOIDmode ) mode = DImode ; gcc_assert ( GET_MODE_SIZE ( mode ) == 8 ) ; lowpart = gen_lowpart ( SImode , val ) ; highpart = gen_highpart_mode ( SImode , mode , val ) ; gcc_assert ( CONST_INT_P ( lowpart ) ) ; gcc_assert ( CONST_INT_P ( highpart ) ) ; return ( arm_gen_constant ( SET , SImode , NULL_RTX , INTVAL ( lowpart ) , NULL_RTX , NULL_RTX , 0 , 0 ) + arm_gen_constant ( SET , SImode , NULL_RTX , INTVAL ( highpart ) , NULL_RTX , NULL_RTX , 0 , 0 ) ) ; } </s>

Return the cost of synthesizing a 64-bit constant VAL inline . Returns the number of insns needed , or 99 if we do n't know how to do it .


<s> EVT getSetCCResultType ( const DataLayout & DL , LLVMContext & Context , EVT VT ) const override { return MVT :: i257 ; } </s>

Return the value type to use for ISD : :SETCC .


<s> bool MVELaneInterleaving :: runOnFunction ( Function & F ) { if ( ! EnableInterleave ) return false ; auto & TPC = getAnalysis < TargetPassConfig > ( ) ; auto & TM = TPC . getTM < TargetMachine > ( ) ; auto * ST = & TM . getSubtarget < ARMSubtarget > ( F ) ; if ( ! ST -> hasMVEIntegerOps ( ) ) return false ; bool Changed = false ; SmallPtrSet < Instruction * , 16 > Visited ; for ( Instruction & I : reverse ( instructions ( F ) ) ) { if ( I . getType ( ) -> isVectorTy ( ) && ( isa < TruncInst > ( I ) || isa < FPTruncInst > ( I ) ) && ! Visited . count ( & I ) ) Changed |= tryInterleave ( & I , Visited ) ; } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> int symbolic_memory_operand ( rtx op , enum machine_mode mode ) { switch ( GET_CODE ( op ) ) { case SYMBOL_REF : case LABEL_REF : return 1 ; case CONST : op = XEXP ( op , 0 ) ; return ( ( GET_CODE ( XEXP ( op , 0 ) ) == SYMBOL_REF || GET_CODE ( XEXP ( op , 0 ) ) == LABEL_REF ) && GET_CODE ( XEXP ( op , 1 ) ) == CONST_INT ) ; case CONST_DOUBLE : return GET_MODE ( op ) == mode ; case PLUS : return symbolic_memory_operand ( XEXP ( op , 0 ) , mode ) && symbolic_memory_operand ( XEXP ( op , 1 ) , mode ) ; default : return 0 ; } } </s>

Returns 1 if OP is a memory reference involving a symbolic constant that is not in the constant pool .


<s>
bool
X86RegisterAllocator
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
outs
(
)
<<
"\n"
<<
"=====================\n"
<<
MF
.
getName
(
)
<<
"()\n====================="
<<
"\n"
;
MachineRegisterInfo
&
regInfo
=
MF
.
getRegInfo
(
)
;
for
(
auto
&
MBB
:
MF
)
{
reloop
:
for
(
auto
&
MI
:
MBB
)
{
const
TargetInstrInfo
*
TII
=
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
auto
mi
=
&
MI
;
if
(
mi
->
isInsertSubreg
(
)
)
{
unsigned
SubIdx
=
mi
->
getOperand
(
3
)
.
getImm
(
)
;
mi
->
RemoveOperand
(
3
)
;
assert
(
mi
->
getOperand
(
0
)
.
getSubReg
(
)
==
0
&&
"Unexpected subreg idx"
)
;
mi
->
getOperand
(
0
)
.
setSubReg
(
SubIdx
)
;
mi
->
getOperand
(
0
)
.
setIsUndef
(
mi
->
getOperand
(
1
)
.
isUndef
(
)
)
;
mi
->
RemoveOperand
(
1
)
;
mi
->
setDesc
(
TII
->
get
(
TargetOpcode
::
COPY
)
)
;
(
getIterForMI
(
MI
)
)
->
eraseFromParent
(
)
;
goto
reloop
;
}
}
outs
(
)
<<
"Contents of MachineBasicBlock:\n"
;
outs
(
)
<<
MBB
<<
"\n"
;
outs
(
)
.
flush
(
)
;
}
spilledRegisters
.
clear
(
)
;
BEGINNING
:
for
(
LiveRange
*
LR
:
interferenceGraph
)
{
delete
LR
;
}
interferenceGraph
.
clear
(
)
;
interferenceGraphRetrieval
.
clear
(
)
;
livenessInformation
.
clear
(
)
;
phiNodes
.
clear
(
)
;
calcGlobalLivenessInfo
(
MF
,
regInfo
)
;
if
(
interferenceGraph
.
size
(
)
>
0
&&
color
(
MF
,
regInfo
)
==
EXIT_STATUS_T
::
SPILLED
)
{
goto
BEGINNING
;
}
for
(
MachineInstr
*
MI
:
getPhiNodes
(
)
)
{
MI
->
eraseFromParent
(
)
;
}
MF
.
getProperties
(
)
.
set
(
MachineFunctionProperties
::
Property
::
NoPHIs
)
;
MF
.
getProperties
(
)
.
set
(
MachineFunctionProperties
::
Property
::
NoVRegs
)
;
outs
(
)
<<
"\n\n"
;
for
(
auto
&
MBB
:
MF
)
{
outs
(
)
<<
"Contents of MachineBasicBlock:\n"
;
outs
(
)
<<
MBB
<<
"\n"
;
outs
(
)
.
flush
(
)
;
}
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> void SIFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


<s> static rtx ix86_function_arg ( cumulative_args_t cum_v , machine_mode omode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; machine_mode mode = omode ; HOST_WIDE_INT bytes , words ; rtx arg ; if ( ( type && POINTER_BOUNDS_TYPE_P ( type ) ) || POINTER_BOUNDS_MODE_P ( mode ) ) { if ( cum -> bnds_in_bt ) arg = NULL ; else if ( cum -> bnd_regno <= LAST_BND_REG ) arg = gen_rtx_REG ( BNDmode , cum -> bnd_regno ) ; else arg = GEN_INT ( cum -> bnd_regno - LAST_BND_REG - 1 ) ; return arg ; } if ( mode == BLKmode ) bytes = int_size_in_bytes ( type ) ; else bytes = GET_MODE_SIZE ( mode ) ; words = CEIL ( bytes , UNITS_PER_WORD ) ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) mode = type_natural_mode ( type , cum , false ) ; if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) arg = function_arg_ms_64 ( cum , mode , omode , named , bytes ) ; else arg = function_arg_64 ( cum , mode , omode , type , named ) ; } else arg = function_arg_32 ( cum , mode , omode , type , bytes , words ) ; return arg ; } </s>

Return where to put the arguments to a function . Return zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument . It is null for libcalls where that information may not be available . CUM gives information about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) .


<s> bool isFPImm ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int Val = ARM_AM :: getFP32Imm ( APInt ( 32 , CE -> getValue ( ) ) ) ; return Val != - 1 ; } </s>

isFPImm - Tests if this is a MO_FPImmediate operand .


<s> static bool arm_have_conditional_execution ( void ) { bool has_cond_exec , enable_ifcvt_trans ; has_cond_exec = ! TARGET_THUMB1 ; enable_ifcvt_trans = TARGET_COND_ARITH && ! reload_completed ; return has_cond_exec && ! enable_ifcvt_trans ; } </s>

Implement the TARGET_HAVE_CONDITIONAL_EXECUTION hook . All modes except THUMB1 have conditional execution . If we have conditional arithmetic , return false before reload to enable some ifcvt transformations .


<s> bool rl78_regno_mode_code_ok_for_base_p ( int regno , machine_mode mode ATTRIBUTE_UNUSED , addr_space_t address_space ATTRIBUTE_UNUSED , int outer_code ATTRIBUTE_UNUSED , int index_code ) { if ( regno <= SP_REG && regno >= 16 ) return true ; if ( index_code == REG ) return ( regno == HL_REG ) ; if ( regno == C_REG || regno == B_REG || regno == E_REG || regno == L_REG ) return true ; return false ; } </s>


<s> SDValue AMDGPUTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , DebugLoc DL , SelectionDAG & DAG ) const { return DAG . getNode ( AMDGPUISD :: RET_FLAG , DL , MVT :: Other , Chain ) ; } </s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static bool ix86_legitimate_constant_p ( machine_mode mode , rtx x ) { if ( POINTER_BOUNDS_MODE_P ( GET_MODE ( x ) ) ) return false ; switch ( GET_CODE ( x ) ) { case CONST : x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == PLUS ) { if ( ! CONST_INT_P ( XEXP ( x , 1 ) ) ) return false ; x = XEXP ( x , 0 ) ; } if ( TARGET_MACHO && darwin_local_data_pic ( x ) ) return true ; if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , 1 ) ) { case UNSPEC_GOT : case UNSPEC_GOTOFF : case UNSPEC_PLTOFF : return TARGET_64BIT ; case UNSPEC_TPOFF : case UNSPEC_NTPOFF : x = XVECEXP ( x , 0 , 0 ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_EXEC ) ; case UNSPEC_DTPOFF : x = XVECEXP ( x , 0 , 0 ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_DYNAMIC ) ; default : return false ; } if ( GET_CODE ( x ) == LABEL_REF ) return true ; if ( GET_CODE ( x ) != SYMBOL_REF ) return false ; case SYMBOL_REF : if ( SYMBOL_REF_TLS_MODEL ( x ) ) return false ; if ( TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P ( x ) ) return false ; if ( MACHO_DYNAMIC_NO_PIC_P ) return machopic_symbol_defined_p ( x ) ; if ( ix86_force_load_from_GOT_p ( x ) ) return false ; break ; CASE_CONST_SCALAR_INT : switch ( mode ) { case TImode : if ( TARGET_64BIT ) return true ; case OImode : case XImode : if ( ! standard_sse_constant_p ( x , mode ) ) return false ; default : break ; } break ; case CONST_VECTOR : if ( ! standard_sse_constant_p ( x , mode ) ) return false ; default : break ; } return true ; } </s>

Determine if a given RTX is a valid constant . We already know this satisfies CONSTANT_P .


<s>
bool
HexagonCommonGEP
::
runOnFunction
(
Function
&
F
)
{
if
(
skipFunction
(
F
)
)
return
false
;
for
(
Function
::
iterator
A
=
F
.
begin
(
)
,
Z
=
F
.
end
(
)
;
A
!=
Z
;
++
A
)
for
(
BasicBlock
::
iterator
I
=
A
->
begin
(
)
,
E
=
A
->
end
(
)
;
I
!=
E
;
++
I
)
if
(
isa
<
InvokeInst
>
(
I
)
||
isa
<
LandingPadInst
>
(
I
)
)
return
false
;
Fn
=
&
F
;
DT
=
&
getAnalysis
<
DominatorTreeWrapperPass
>
(
)
.
getDomTree
(
)
;
PDT
=
&
getAnalysis
<
PostDominatorTreeWrapperPass
>
(
)
.
getPostDomTree
(
)
;
LI
=
&
getAnalysis
<
LoopInfoWrapperPass
>
(
)
.
getLoopInfo
(
)
;
Ctx
=
&
F
.
getContext
(
)
;
Nodes
.
clear
(
)
;
Uses
.
clear
(
)
;
NodeOrder
.
clear
(
)
;
SpecificBumpPtrAllocator
<
GepNode
>
Allocator
;
Mem
=
&
Allocator
;
collect
(
)
;
common
(
)
;
NodeToValueMap
Loc
;
computeNodePlacement
(
Loc
)
;
materialize
(
Loc
)
;
removeDeadCode
(
)
;
if
(
verifyFunction
(
F
,
&
dbgs
(
)
)
)
report_fatal_error
(
"Broken function"
)
;
return
true
;
}
</s>


<s> static void ix86_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; HOST_WIDE_INT bytes , words ; int nregs ; if ( mode == BLKmode ) bytes = int_size_in_bytes ( type ) ; else bytes = GET_MODE_SIZE ( mode ) ; words = ( bytes + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; if ( type ) mode = type_natural_mode ( type , NULL , false ) ; if ( ( type && POINTER_BOUNDS_TYPE_P ( type ) ) || POINTER_BOUNDS_MODE_P ( mode ) ) { if ( cum -> bnds_in_bt ) { cum -> bnds_in_bt -- ; return ; } if ( cum -> force_bnd_pass ) cum -> force_bnd_pass -- ; cum -> bnd_regno ++ ; return ; } cum -> bnds_in_bt = 0 ; if ( cum -> force_bnd_pass ) { cum -> bnd_regno += cum -> force_bnd_pass ; cum -> force_bnd_pass = 0 ; } if ( TARGET_64BIT && ( cum ? cum -> call_abi : ix86_abi ) == MS_ABI ) nregs = function_arg_advance_ms_64 ( cum , bytes , words ) ; else if ( TARGET_64BIT ) nregs = function_arg_advance_64 ( cum , mode , type , words , named ) ; else nregs = function_arg_advance_32 ( cum , mode , type , bytes , words ) ; if ( cum -> stdarg ) cum -> force_bnd_pass = nregs ; if ( ! nregs ) cum -> bnds_in_bt = chkp_type_bounds_count ( type ) ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> static void s390_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( s390_function_arg_float ( mode , type ) ) { cum -> fprs += 1 ; } else if ( s390_function_arg_integer ( mode , type ) ) { int size = s390_function_arg_size ( mode , type ) ; cum -> gprs += ( ( size + UNITS_PER_LONG - 1 ) / UNITS_PER_LONG ) ; } else gcc_unreachable ( ) ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available. ) . The boolean NAMED specifies whether the argument is a named argument ( as opposed to an unnamed argument matching an ellipsis ) .


<s> void function_builder :: register_function_group ( const function_group_info & group ) { ( * group . shape ) -> build ( * this , group ) ; } </s>


<s> bool AArch64InstrInfo :: shouldOutlineFromFunctionByDefault ( MachineFunction & MF ) const { return MF . getFunction ( ) . optForMinSize ( ) ; } </s>

Return true if the function should be outlined from by default .


<s> bool ia64_expand_load_address ( rtx dest , rtx src ) { gcc_assert ( GET_CODE ( dest ) == REG ) ; if ( GET_MODE ( dest ) != Pmode ) dest = gen_rtx_REG_offset ( dest , Pmode , REGNO ( dest ) , byte_lowpart_offset ( Pmode , GET_MODE ( dest ) ) ) ; if ( TARGET_NO_PIC ) return false ; if ( small_addr_symbolic_operand ( src , VOIDmode ) ) return false ; if ( TARGET_AUTO_PIC ) emit_insn ( gen_load_gprel64 ( dest , src ) ) ; else if ( GET_CODE ( src ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( src ) ) emit_insn ( gen_load_fptr ( dest , src ) ) ; else if ( sdata_symbolic_operand ( src , VOIDmode ) ) emit_insn ( gen_load_gprel ( dest , src ) ) ; else if ( local_symbolic_operand64 ( src , VOIDmode ) ) { emit_insn ( gen_load_gprel64 ( dest , src ) ) ; } else { HOST_WIDE_INT addend = 0 ; rtx tmp ; if ( GET_CODE ( src ) == CONST ) { HOST_WIDE_INT hi , lo ; hi = INTVAL ( XEXP ( XEXP ( src , 0 ) , 1 ) ) ; lo = ( ( hi & 0x3fff ) ^ 0x2000 ) - 0x2000 ; hi = hi - lo ; if ( lo != 0 ) { addend = lo ; src = plus_constant ( Pmode , XEXP ( XEXP ( src , 0 ) , 0 ) , hi ) ; } } tmp = gen_rtx_HIGH ( Pmode , src ) ; tmp = gen_rtx_PLUS ( Pmode , tmp , pic_offset_table_rtx ) ; emit_insn ( gen_rtx_SET ( dest , tmp ) ) ; tmp = gen_rtx_LO_SUM ( Pmode , gen_const_mem ( Pmode , dest ) , src ) ; emit_insn ( gen_rtx_SET ( dest , tmp ) ) ; if ( addend ) { tmp = gen_rtx_PLUS ( Pmode , dest , GEN_INT ( addend ) ) ; emit_insn ( gen_rtx_SET ( dest , tmp ) ) ; } } return true ; } </s>


<s> bool isToken ( ) const { return Kind == k_Token ; } </s>


<s> bool RISCVTargetMachine :: parseMachineFunctionInfo ( const yaml :: MachineFunctionInfo & MFI , PerFunctionMIParsingState & PFS , SMDiagnostic & Error , SMRange & SourceRange ) const { const auto & YamlMFI = static_cast < const yaml :: RISCVMachineFunctionInfo & > ( MFI ) ; PFS . MF . getInfo < RISCVMachineFunctionInfo > ( ) -> initializeBaseYamlFields ( YamlMFI ) ; return false ; } </s>

Parse out the target 's MachineFunctionInfo from the YAML reprsentation .


<s> static bool quad_aligned_load_p ( swap_web_entry * insn_entry , rtx_insn * insn ) { unsigned uid = INSN_UID ( insn ) ; if ( ! insn_entry [ uid ] . is_swap || insn_entry [ uid ] . is_load ) return false ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref use = DF_INSN_INFO_USES ( insn_info ) ; struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( ! def_link || ! def_link -> ref || DF_REF_IS_ARTIFICIAL ( def_link -> ref ) || def_link -> next ) return false ; rtx def_insn = DF_REF_INSN ( def_link -> ref ) ; unsigned uid2 = INSN_UID ( def_insn ) ; if ( ! insn_entry [ uid2 ] . is_load || ! insn_entry [ uid2 ] . is_swap ) return false ; rtx body = PATTERN ( def_insn ) ; if ( GET_CODE ( body ) != SET || ! ( GET_CODE ( SET_SRC ( body ) ) == VEC_SELECT || pattern_is_rotate64 ( body ) ) || ! MEM_P ( XEXP ( SET_SRC ( body ) , 0 ) ) ) return false ; rtx mem = XEXP ( SET_SRC ( body ) , 0 ) ; rtx base_reg = XEXP ( mem , 0 ) ; return ( ( REG_P ( base_reg ) || rs6000_sum_of_two_registers_p ( base_reg ) ) && MEM_ALIGN ( mem ) >= 128 ) ? true : false ; } </s>

Return TRUE if INSN represents a swap of a swapped load from memory and the memory address is quad-word aligned .


"Don't know how to custom type legalize this operation!"

"READCYCLECOUNTER only has custom type legalization on riscv32"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> void ARMPassConfig :: addPreEmitPass2 ( ) { addPass ( createARMBranchTargetsPass ( ) ) ; addPass ( createARMConstantIslandPass ( ) ) ; addPass ( createARMLowOverheadLoopsPass ( ) ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) { addPass ( createCFGuardLongjmpPass ( ) ) ; addPass ( createEHContGuardCatchretPass ( ) ) ; } } </s>

Targets may add passes immediately before machine code is emitted in this callback .


<s> rtx function_expander :: get_nonoverlapping_reg_target ( ) { if ( possible_target && overlaps_input_p ( possible_target ) ) possible_target = NULL_RTX ; return get_reg_target ( ) ; } </s>

As for get_reg_target , but make sure that the returned REG does not overlap any inputs .


<s> bool legitimate_constant_pool_address_p ( const_rtx x , machine_mode mode , bool strict ) { return ( toc_relative_expr_p ( x , strict ) && ( TARGET_CMODEL != CMODEL_MEDIUM || constant_pool_expr_p ( XVECEXP ( tocrel_base , 0 , 0 ) ) || mode == QImode || offsettable_ok_by_alignment ( XVECEXP ( tocrel_base , 0 , 0 ) , INTVAL ( tocrel_offset ) , mode ) ) ) ; } </s>

Return true if X is a constant pool address , and also for cmodel=medium if X is a toc-relative address known to be offsettable within MODE .


<s> static void csky_function_arg_advance ( cumulative_args_t pcum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * pcum = get_cumulative_args ( pcum_v ) ; int param_size = csky_num_arg_regs ( mode , type ) ; if ( * pcum + param_size > CSKY_NPARM_REGS ) * pcum = CSKY_NPARM_REGS ; else * pcum += param_size ; } </s>


<s> unsigned SparcRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return SP :: I6 ; } </s>


<s> MachineBasicBlock * SITargetLowering :: EmitInstrWithCustomInserter ( MachineInstr * MI , MachineBasicBlock * BB ) const { switch ( MI -> getOpcode ( ) ) { case AMDGPU :: SI_INIT_M0 : { const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; BuildMI ( * BB , MI -> getIterator ( ) , MI -> getDebugLoc ( ) , TII -> get ( AMDGPU :: S_MOV_B32 ) , AMDGPU :: M0 ) . addOperand ( MI -> getOperand ( 0 ) ) ; MI -> eraseFromParent ( ) ; break ; } case AMDGPU :: BRANCH : return BB ; case AMDGPU :: GET_GROUPSTATICSIZE : { const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; MachineFunction * MF = BB -> getParent ( ) ; SIMachineFunctionInfo * MFI = MF -> getInfo < SIMachineFunctionInfo > ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; BuildMI ( * BB , MI , DL , TII -> get ( AMDGPU :: S_MOVK_I32 ) ) . addOperand ( MI -> getOperand ( 0 ) ) . addImm ( MFI -> LDSSize ) ; MI -> eraseFromParent ( ) ; return BB ; } default : return AMDGPUTargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; } return BB ; } </s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static bool split_mode_p ( machine_mode mode ) { return maybe_split_mode ( mode ) != VOIDmode ; } </s>

Return true if mode should be treated as two registers .


<s> static bool or1k_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) { if ( arg . aggregate_type_p ( ) ) return true ; HOST_WIDE_INT size = arg . type_size_in_bytes ( ) ; return size < 0 || size > 8 ; } </s>

Worker for TARGET_PASS_BY_REFERENCE . Returns true if an argument of TYPE in MODE should be passed by reference as required by the OpenRISC ABI . On OpenRISC structures , unions and arguments larger than 64-bits are passed by reference .


<s> const char * mips16e_output_save_restore ( rtx pattern , HOST_WIDE_INT adjust ) { static char buffer [ 300 ] ; struct mips16e_save_restore_info info ; unsigned int i , end ; char * s ; if ( ! mips16e_save_restore_pattern_p ( pattern , adjust , & info ) ) gcc_unreachable ( ) ; s = strcpy ( buffer , adjust > 0 ? "restore\t" : "save\t" ) ; s += strlen ( s ) ; if ( info . nargs > 1 ) s += sprintf ( s , "%s-%s," , reg_names [ GP_ARG_FIRST ] , reg_names [ GP_ARG_FIRST + info . nargs - 1 ] ) ; else if ( info . nargs == 1 ) s += sprintf ( s , "%s," , reg_names [ GP_ARG_FIRST ] ) ; s += sprintf ( s , "%d" , ( int ) info . size ) ; if ( BITSET_P ( info . mask , 16 ) ) s += sprintf ( s , ",%s" , reg_names [ GP_REG_FIRST + 16 ] ) ; if ( BITSET_P ( info . mask , 17 ) ) s += sprintf ( s , ",%s" , reg_names [ GP_REG_FIRST + 17 ] ) ; end = ARRAY_SIZE ( mips16e_s2_s8_regs ) ; i = mips16e_find_first_register ( info . mask , mips16e_s2_s8_regs , end ) ; if ( i < end ) s = mips16e_add_register_range ( s , mips16e_s2_s8_regs [ end - 1 ] , mips16e_s2_s8_regs [ i ] ) ; end = ARRAY_SIZE ( mips16e_a0_a3_regs ) ; i = mips16e_find_first_register ( info . mask , mips16e_a0_a3_regs , end ) ; if ( i < end ) s = mips16e_add_register_range ( s , mips16e_a0_a3_regs [ i ] , mips16e_a0_a3_regs [ end - 1 ] ) ; if ( BITSET_P ( info . mask , RETURN_ADDR_REGNUM ) ) s += sprintf ( s , ",%s" , reg_names [ RETURN_ADDR_REGNUM ] ) ; return buffer ; } </s>

Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction . PATTERN and ADJUST are as for mips16e_save_restore_pattern_p .


<s>
const
MCPhysReg
*
X86RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
bool
HasAVX
=
TM
.
getSubtarget
<
X86Subtarget
>
(
)
.
hasAVX
(
)
;
bool
HasAVX512
=
TM
.
getSubtarget
<
X86Subtarget
>
(
)
.
hasAVX512
(
)
;
assert
(
MF
&&
"MachineFunction required"
)
;
switch
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
)
{
case
CallingConv
::
GHC
:
case
CallingConv
::
HiPE
:
return
CSR_NoRegs_SaveList
;
case
CallingConv
::
AnyReg
:
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
return
CSR_64_AllRegs_SaveList
;
case
CallingConv
::
PreserveMost
:
return
CSR_64_RT_MostRegs_SaveList
;
case
CallingConv
::
PreserveAll
:
if
(
HasAVX
)
return
CSR_64_RT_AllRegs_AVX_SaveList
;
return
CSR_64_RT_AllRegs_SaveList
;
case
CallingConv
::
Intel_OCL_BI
:
{
if
(
HasAVX512
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX512
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX_SaveList
;
if
(
HasAVX
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX_SaveList
;
if
(
!
HasAVX
&&
!
IsWin64
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_SaveList
;
break
;
}
case
CallingConv
::
Cold
:
if
(
Is64Bit
)
return
CSR_64_MostRegs_SaveList
;
break
;
default
:
break
;
}
bool
CallsEHReturn
=
MF
->
getMMI
(
)
.
callsEHReturn
(
)
;
if
(
Is64Bit
)
{
if
(
IsWin64
)
return
CSR_Win64_SaveList
;
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
}
if
(
CallsEHReturn
)
return
CSR_32EHRet_SaveList
;
return
CSR_32_SaveList
;
}
</s>


<s> bool get_ma ( ) const { return m_ma ; } </s>

Get ma according to operand [ mask_op_idx ] .


<s> bool MSP430FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> const RegisterBank & M68kRegisterBankInfo :: getRegBankFromRegClass ( const TargetRegisterClass & RC , LLT ) const { return getRegBank ( M68k :: GPRRegBankID ) ; } </s>


<s> InstructionCost GCNTTIImpl :: getMinMaxReductionCost ( VectorType * Ty , VectorType * CondTy , bool IsUnsigned , TTI :: TargetCostKind CostKind ) { EVT OrigTy = TLI -> getValueType ( DL , Ty ) ; if ( ! ST -> hasVOP3PInsts ( ) || OrigTy . getScalarSizeInBits ( ) != 16 ) return BaseT :: getMinMaxReductionCost ( Ty , CondTy , IsUnsigned , CostKind ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; return LT . first * getHalfRateInstrCost ( CostKind ) ; } </s>

Try to calculate op costs for min/max reduction operations .


<s> unsigned int getNumFixupKinds ( ) const { return AArch64 :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> rtx tilepro_simd_int ( rtx num , machine_mode mode ) { HOST_WIDE_INT n = 0 ; gcc_assert ( CONST_INT_P ( num ) ) ; n = INTVAL ( num ) ; switch ( mode ) { case E_QImode : n = 0x01010101 * ( n & 0x000000FF ) ; break ; case E_HImode : n = 0x00010001 * ( n & 0x0000FFFF ) ; break ; case E_SImode : break ; case E_DImode : break ; default : gcc_unreachable ( ) ; } return gen_int_si ( n ) ; } </s>

Return the simd variant of the constant NUM of mode MODE , by replicating it to fill an interger of mode SImode . NUM is first truncated to fit in MODE .


<s> bool ARMPreAllocLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { TD = Fn . getSubtarget ( ) . getDataLayout ( ) ; TII = Fn . getSubtarget ( ) . getInstrInfo ( ) ; TRI = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; STI = & Fn . getTarget ( ) . getSubtarget < ARMSubtarget > ( ) ; MRI = & Fn . getRegInfo ( ) ; MF = & Fn ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) Modified |= RescheduleLoadStoreInstrs ( MFI ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Patmos Stack Cache Analysis"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"WebAssembly Argument Move"
;
}
</s>