<s> bool HexagonInstrInfo :: canExecuteInBundle ( const MachineInstr & First , const MachineInstr & Second ) const { if ( Second . mayStore ( ) && First . getOpcode ( ) == Hexagon :: S2_allocframe ) { const MachineOperand & Op = Second . getOperand ( 0 ) ; if ( Op . isReg ( ) && Op . isUse ( ) && Op . getReg ( ) == Hexagon :: R29 ) return true ; } if ( DisableNVSchedule ) return false ; if ( mayBeNewStore ( Second ) ) { const MachineOperand & Stored = Second . getOperand ( Second . getNumOperands ( ) - 1 ) ; if ( ! Stored . isReg ( ) ) return false ; for ( unsigned i = 0 , e = First . getNumOperands ( ) ; i < e ; ++ i ) { const MachineOperand & Op = First . getOperand ( i ) ; if ( Op . isReg ( ) && Op . isDef ( ) && Op . getReg ( ) == Stored . getReg ( ) ) return true ; } } return false ; } </s>

Can these instructions execute at the same time in a bundle .


<s> static void arc_finalize_pic ( void ) { rtx pat ; rtx baseptr_rtx = gen_rtx_REG ( Pmode , PIC_OFFSET_TABLE_REGNUM ) ; if ( crtl -> uses_pic_offset_table == 0 ) return ; gcc_assert ( flag_pic != 0 ) ; pat = gen_rtx_SYMBOL_REF ( Pmode , "_DYNAMIC" ) ; pat = arc_unspec_offset ( pat , ARC_UNSPEC_GOT ) ; pat = gen_rtx_SET ( baseptr_rtx , pat ) ; emit_insn ( pat ) ; } </s>

If the function has any GOTOFF relocations , then the GOTBASE register has to be setup in the prologue The instruction needed at the function start for setting up the GOTBASE register is add rdest , pc , -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The rtl to be emitted for this should be : set ( reg basereg ) ( plus ( reg pc ) ( const ( unspec ( symref _DYNAMIC ) 3 ) ) ) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --


<s> static unsigned getReg ( const void * D , unsigned RC , unsigned RegNo ) { const TriCoreDisassembler * Dis = static_cast < const TriCoreDisassembler * > ( D ) ; const MCRegisterInfo * RegInfo = Dis -> getContext ( ) . getRegisterInfo ( ) ; return * ( RegInfo -> getRegClass ( RC ) . begin ( ) + RegNo ) ; } </s>

Returns the register associated with this edge .


<s>
void
mmix_override_options
(
)
{
if
(
flag_pic
)
{
warning
(
"-f%s not supported: ignored"
,
(
flag_pic
>
1
)
"PIC"
:
"pic"
)
;
flag_pic
=
0
;
}
ggc_add_rtx_root
(
&
mmix_compare_op0
,
1
)
;
ggc_add_rtx_root
(
&
mmix_compare_op1
,
1
)
;
}
</s>


<s> bool mips_split_symbol ( rtx temp , rtx addr , machine_mode mode , rtx * low_out ) { enum mips_symbol_context context ; enum mips_symbol_type symbol_type ; rtx high ; context = ( mode == MAX_MACHINE_MODE ? SYMBOL_CONTEXT_LEA : SYMBOL_CONTEXT_MEM ) ; if ( GET_CODE ( addr ) == HIGH && context == SYMBOL_CONTEXT_LEA ) { addr = XEXP ( addr , 0 ) ; if ( mips_symbolic_constant_p ( addr , context , & symbol_type ) && mips_symbol_insns ( symbol_type , mode ) > 0 && mips_split_hi_p [ symbol_type ] ) { if ( low_out ) switch ( symbol_type ) { case SYMBOL_GOT_PAGE_OFST : * low_out = mips_got_load ( temp , addr , SYMBOL_GOTOFF_PAGE ) ; break ; default : gcc_unreachable ( ) ; } return true ; } } else { if ( mips_symbolic_constant_p ( addr , context , & symbol_type ) && mips_symbol_insns ( symbol_type , mode ) > 0 && mips_split_p [ symbol_type ] ) { if ( low_out ) switch ( symbol_type ) { case SYMBOL_GOT_DISP : * low_out = mips_got_load ( temp , addr , SYMBOL_GOTOFF_DISP ) ; break ; case SYMBOL_GP_RELATIVE : high = mips_pic_base_register ( temp ) ; * low_out = gen_rtx_LO_SUM ( Pmode , high , addr ) ; break ; default : high = gen_rtx_HIGH ( Pmode , copy_rtx ( addr ) ) ; high = mips_force_temporary ( temp , high ) ; * low_out = gen_rtx_LO_SUM ( Pmode , high , addr ) ; break ; } return true ; } } return false ; } </s>

Return a LO_SUM expression for ADDR . TEMP is as for mips_force_temporary and is used to load the high part into a register .


<s> rtx legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , enum machine_mode mode ATTRIBUTE_UNUSED ) { if ( flag_pic && ! legitimate_pic_operand_p ( x ) ) x = legitimize_pic_address ( oldx , NULL_RTX ) ; if ( GET_CODE ( x ) == PLUS && symbolic_operand ( XEXP ( x , 1 ) , VOIDmode ) ) { rtx regx1 , regy1 , regy2 , y ; y = XEXP ( x , 1 ) ; if ( GET_CODE ( y ) == CONST ) y = XEXP ( y , 0 ) ; if ( GET_CODE ( y ) == PLUS || GET_CODE ( y ) == MINUS ) { regx1 = force_reg ( Pmode , force_operand ( XEXP ( x , 0 ) , 0 ) ) ; regy1 = force_reg ( Pmode , force_operand ( XEXP ( y , 0 ) , 0 ) ) ; regy2 = force_reg ( Pmode , force_operand ( XEXP ( y , 1 ) , 0 ) ) ; regx1 = force_reg ( Pmode , gen_rtx_fmt_ee ( GET_CODE ( y ) , Pmode , regx1 , regy2 ) ) ; return force_reg ( Pmode , gen_rtx_PLUS ( Pmode , regx1 , regy1 ) ) ; } } return x ; } </s>

Try machine-dependent ways of modifying an illegitimate address X to be legitimate . If we find one , return the new , valid address . OLDX is the address as it was before break_out_memory_refs was called . In some cases it is useful to look at this to decide what needs to be done . MODE is the mode of the operand pointed to by X .


<s> bool MSP430InstrInfo :: isUnpredicatedTerminator ( const MachineInstr * MI ) const { if ( ! MI -> isTerminator ( ) ) return false ; if ( MI -> isBranch ( ) && ! MI -> isBarrier ( ) ) return true ; if ( ! MI -> isPredicable ( ) ) return true ; return ! isPredicated ( MI ) ; } </s>

Returns true if the instruction is a terminator instruction that has not been predicated .


<s>
const
char
*
output_call_mem
(
rtx
*
operands
)
{
if
(
TARGET_INTERWORK
&&
!
arm_arch5
)
{
output_asm_insn
(
"ldr%?\t%|ip, %0"
,
operands
)
;
output_asm_insn
(
"mov%?\t%|lr, %|pc"
,
operands
)
;
output_asm_insn
(
"bx%?\t%|ip"
,
operands
)
;
}
else
if
(
regno_use_in
(
LR_REGNUM
,
operands
[
0
]
)
)
{
output_asm_insn
(
"ldr%?\t%|ip, %0"
,
operands
)
;
if
(
arm_arch5
)
output_asm_insn
(
"blx%?\t%|ip"
,
operands
)
;
else
{
output_asm_insn
(
"mov%?\t%|lr, %|pc"
,
operands
)
;
if
(
arm_arch4t
)
output_asm_insn
(
"bx%?\t%|ip"
,
operands
)
;
else
output_asm_insn
(
"mov%?\t%|pc, %|ip"
,
operands
)
;
}
}
else
{
output_asm_insn
(
"mov%?\t%|lr, %|pc"
,
operands
)
;
output_asm_insn
(
"ldr%?\t%|pc, %0"
,
operands
)
;
}
return
""
;
}
</s>

Output a 'call ' insn that is a reference in memory . This is disabled for ARMv5 and we prefer a blx instead because otherwise there 's a significant performance overhead .


<s> ArrayRef < const Metadata * > getMDStrings ( ) const { return makeArrayRef ( MDs ) . slice ( NumModuleMDs , NumMDStrings ) ; } </s>

Get the MDString metadata for this block .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> void HexagonInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { if ( Hexagon :: IntRegsRegClass . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: TFR ) , DestReg ) . addReg ( SrcReg ) ; return ; } if ( Hexagon :: DoubleRegsRegClass . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: TFR_64 ) , DestReg ) . addReg ( SrcReg ) ; return ; } if ( Hexagon :: PredRegsRegClass . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: OR_pp ) , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg ) ; return ; } if ( Hexagon :: DoubleRegsRegClass . contains ( DestReg ) && Hexagon :: IntRegsRegClass . contains ( SrcReg ) ) { if ( SrcReg == RI . getSubReg ( DestReg , Hexagon :: subreg_loreg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: TFRI ) , ( RI . getSubReg ( DestReg , Hexagon :: subreg_hireg ) ) ) . addImm ( 0 ) ; } else { BuildMI ( MBB , I , DL , get ( Hexagon :: TFR ) , ( RI . getSubReg ( DestReg , Hexagon :: subreg_loreg ) ) ) . addReg ( SrcReg ) ; BuildMI ( MBB , I , DL , get ( Hexagon :: TFRI ) , ( RI . getSubReg ( DestReg , Hexagon :: subreg_hireg ) ) ) . addImm ( 0 ) ; } return ; } if ( Hexagon :: CRRegsRegClass . contains ( DestReg ) && Hexagon :: IntRegsRegClass . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: TFCR ) , DestReg ) . addReg ( SrcReg ) ; return ; } llvm_unreachable ( "Unimplemented" ) ; } </s>


<s> bool RISCVTargetLowering :: IsEligibleForTailCallOptimization ( CCState & CCInfo , CallLoweringInfo & CLI , MachineFunction & MF , const SmallVector < CCValAssign , 16 > & ArgLocs ) const { auto & Callee = CLI . Callee ; auto CalleeCC = CLI . CallConv ; auto IsVarArg = CLI . IsVarArg ; auto & Outs = CLI . Outs ; auto & Caller = MF . getFunction ( ) ; auto CallerCC = Caller . getCallingConv ( ) ; if ( Caller . getFnAttribute ( "disable-tail-calls" ) . getValueAsString ( ) == "true" ) return false ; if ( Caller . hasFnAttribute ( "interrupt" ) ) return false ; if ( IsVarArg ) return false ; if ( CCInfo . getNextStackOffset ( ) != 0 ) return false ; for ( auto & VA : ArgLocs ) if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; auto IsCallerStructRet = Caller . hasStructRetAttr ( ) ; auto IsCalleeStructRet = Outs . empty ( ) ? false : Outs [ 0 ] . Flags . isSRet ( ) ; if ( IsCallerStructRet || IsCalleeStructRet ) return false ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; if ( GV -> hasExternalWeakLinkage ( ) ) return false ; } const RISCVRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( CalleeCC != CallerCC ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } for ( auto & Arg : Outs ) if ( Arg . Flags . isByVal ( ) ) return false ; return true ; } </s>

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization .

RISCV RISCV 16 "disable-tail-calls" "true" "interrupt" 0 0 RISCV


"Alloca should always return a pointer."

Emit an alloca address in a register using target-specific logic .


<s>
void
AArch64Operand
::
print
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
k_FPImm
:
OS
<<
"<fpimm "
<<
getFPImm
(
)
<<
"("
<<
AArch64_AM
::
getFPImmFloat
(
getFPImm
(
)
)
<<
") >"
;
break
;
case
k_Barrier
:
{
StringRef
Name
=
getBarrierName
(
)
;
if
(
!
Name
.
empty
(
)
)
OS
<<
"<barrier "
<<
Name
<<
">"
;
else
OS
<<
"<barrier invalid #"
<<
getBarrier
(
)
<<
">"
;
break
;
}
case
k_Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
k_ShiftedImm
:
{
unsigned
Shift
=
getShiftedImmShift
(
)
;
OS
<<
"<shiftedimm "
;
OS
<<
*
getShiftedImmVal
(
)
;
OS
<<
", lsl #"
<<
AArch64_AM
::
getShiftValue
(
Shift
)
<<
">"
;
break
;
}
case
k_CondCode
:
OS
<<
"<condcode "
<<
getCondCode
(
)
<<
">"
;
break
;
case
k_Register
:
OS
<<
"<register "
<<
getReg
(
)
<<
">"
;
break
;
case
k_VectorList
:
{
OS
<<
"<vectorlist "
;
unsigned
Reg
=
getVectorListStart
(
)
;
for
(
unsigned
i
=
0
,
e
=
getVectorListCount
(
)
;
i
!=
e
;
++
i
)
OS
<<
Reg
+
i
<<
" "
;
OS
<<
">"
;
break
;
}
case
k_VectorIndex
:
OS
<<
"<vectorindex "
<<
getVectorIndex
(
)
<<
">"
;
break
;
case
k_SysReg
:
OS
<<
"<sysreg: "
<<
getSysReg
(
)
<<
'>'
;
break
;
case
k_Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
case
k_SysCR
:
OS
<<
"c"
<<
getSysCR
(
)
;
break
;
case
k_Prefetch
:
{
StringRef
Name
=
getPrefetchName
(
)
;
if
(
!
Name
.
empty
(
)
)
OS
<<
"<prfop "
<<
Name
<<
">"
;
else
OS
<<
"<prfop invalid #"
<<
getPrefetch
(
)
<<
">"
;
break
;
}
case
k_PSBHint
:
OS
<<
getPSBHintName
(
)
;
break
;
case
k_ShiftExtend
:
OS
<<
"<"
<<
AArch64_AM
::
getShiftExtendName
(
getShiftExtendType
(
)
)
<<
" #"
<<
getShiftExtendAmount
(
)
;
if
(
!
hasShiftExtendAmount
(
)
)
OS
<<
"<imp>"
;
OS
<<
'>'
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

AArch64
AArch64
"<fpimm "
"("
AArch64_AM::getFPImmFloat
") >"
"<barrier "
">"
"<barrier invalid #"
">"
"<shiftedimm "
", lsl #"
AArch64_AM::getShiftValue
">"
"<condcode "
">"
"<register "
">"
"<vectorlist "
0
" "
">"
"<vectorindex "
">"
"<sysreg: "
"'"
"'"
"c"
"<prfop "
">"
"<prfop invalid #"
">"
"<"
AArch64_AM::getShiftExtendName
" #"
"<imp>"


<s> bool R600PassConfig :: addPreISel ( ) { AMDGPUPassConfig :: addPreISel ( ) ; if ( EnableR600StructurizeCFG ) addPass ( createStructurizeCFGPass ( ) ) ; addPass ( createR600TextureIntrinsicsReplacer ( ) ) ; return false ; } </s>


<s> bool GCNPassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( getOptLevel ( ) ) ) ; return false ; } </s>

This method should install a ( global ) instruction selector pass , which converts possibly generic instructions to fully target-specific instructions , thereby constraining all generic virtual registers to register classes .


<s> EVT ARMTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( ( ! IsMemset || ZeroMemset ) && Subtarget -> hasNEON ( ) && ! F -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { bool Fast ; if ( Size >= 16 && ( memOpAlign ( SrcAlign , DstAlign , 16 ) || ( allowsMisalignedMemoryAccesses ( MVT :: v2f64 , 0 , 1 , & Fast ) && Fast ) ) ) { return MVT :: v2f64 ; } else if ( Size >= 8 && ( memOpAlign ( SrcAlign , DstAlign , 8 ) || ( allowsMisalignedMemoryAccesses ( MVT :: f64 , 0 , 1 , & Fast ) && Fast ) ) ) { return MVT :: f64 ; } } if ( Size >= 4 ) return MVT :: i32 ; else if ( Size >= 2 ) return MVT :: i16 ; return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> void RISCVPassConfig :: addPreRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createRISCVMergeBaseOffsetOptPass ( ) ) ; addPass ( createRISCVCleanupVSETVLIPass ( ) ) ; } } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> void AMDGPUPassConfig :: addIRPasses ( ) { addPass ( createAMDGPUAlwaysInlinePass ( ) ) ; addPass ( createAlwaysInlinerPass ( ) ) ; addPass ( createBarrierNoopPass ( ) ) ; addPass ( createAMDGPUOpenCLImageTypeLoweringPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> VariantKind getKind ( ) const { return Kind ; } </s>


<s> bool ARMBaseInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned TCycles , unsigned TExtra , MachineBasicBlock & FMBB , unsigned FCycles , unsigned FExtra , float Probability , float Confidence ) const { if ( ! TCycles || ! FCycles ) return false ; float UnpredCost = Probability * TCycles + ( 1.0 - Probability ) * FCycles ; UnpredCost += 1.0 ; UnpredCost += ( 1.0 - Confidence ) * Subtarget . getMispredictionPenalty ( ) ; return ( float ) ( TCycles + FCycles + TExtra + FExtra ) < UnpredCost ; } </s>


<s> MCRegister getRegister ( ) const { assert ( ! IsStack ) ; return Reg ; } </s>

Return the specified register in the class .


<s>
static
const
char
*
output_inline_const
(
enum
machine_mode
mode
,
rtx
operands
[
]
)
{
int
x
=
0
,
y
=
0
;
int
trick_no
;
rtx
out_operands
[
3
]
;
char
buf
[
256
]
;
char
load_op
[
256
]
;
const
char
*
dst_fmt
;
int
value
;
value
=
INTVAL
(
operands
[
1
]
)
;
trick_no
=
try_constant_tricks
(
value
,
&
x
,
&
y
)
;
gcc_assert
(
trick_no
!=
0
)
;
if
(
trick_no
==
1
)
x
=
value
;
out_operands
[
0
]
=
operands
[
0
]
;
out_operands
[
1
]
=
GEN_INT
(
x
)
;
if
(
trick_no
>
2
)
out_operands
[
2
]
=
GEN_INT
(
y
)
;
if
(
mode
==
DImode
&&
(
!
TARGET_LITTLE_END
)
)
dst_fmt
=
"%R0"
;
else
dst_fmt
=
"%0"
;
if
(
x
>=
0
&&
x
<=
127
)
sprintf
(
load_op
,
"movi\t%s,%%1"
,
dst_fmt
)
;
else
if
(
(
x
&
(
x
1
)
)
==
0
)
sprintf
(
load_op
,
"bgeni\t%s,%%P1"
,
dst_fmt
)
;
else
if
(
(
x
&
(
x
+
1
)
)
==
0
)
sprintf
(
load_op
,
"bmaski\t%s,%%N1"
,
dst_fmt
)
;
else
sprintf
(
load_op
,
"BADMOVI\t%s,%%1"
,
dst_fmt
)
;
switch
(
trick_no
)
{
case
1
:
strcpy
(
buf
,
load_op
)
;
break
;
case
2
:
sprintf
(
buf
,
"%s\n\tnot\t%s\t// %d 0x%x"
,
load_op
,
dst_fmt
,
value
,
value
)
;
break
;
case
3
:
sprintf
(
buf
,
"%s\n\taddi\t%s,%%2\t// %d 0x%x"
,
load_op
,
dst_fmt
,
value
,
value
)
;
break
;
case
4
:
sprintf
(
buf
,
"%s\n\tsubi\t%s,%%2\t// %d 0x%x"
,
load_op
,
dst_fmt
,
value
,
value
)
;
break
;
case
5
:
sprintf
(
buf
,
"%s\n\trsubi\t%s,%%2\t// %d 0x%x"
,
load_op
,
dst_fmt
,
value
,
value
)
;
break
;
case
6
:
sprintf
(
buf
,
"%s\n\tbseti\t%s,%%P2\t// %d 0x%x"
,
load_op
,
dst_fmt
,
value
,
value
)
;
break
;
case
7
:
sprintf
(
buf
,
"%s\n\tbclri\t%s,%%Q2\t// %d 0x%x"
,
load_op
,
dst_fmt
,
value
,
value
)
;
break
;
case
8
:
sprintf
(
buf
,
"%s\n\trotli\t%s,%%2\t// %d 0x%x"
,
load_op
,
dst_fmt
,
value
,
value
)
;
break
;
case
9
:
sprintf
(
buf
,
"%s\n\tlsli\t%s,%%2\t// %d 0x%x"
,
load_op
,
dst_fmt
,
value
,
value
)
;
break
;
case
10
:
sprintf
(
buf
,
"%s\n\tixh\t%s,%s\t// %d 0x%x"
,
load_op
,
dst_fmt
,
dst_fmt
,
value
,
value
)
;
break
;
case
11
:
sprintf
(
buf
,
"%s\n\tixw\t%s,%s\t// %d 0x%x"
,
load_op
,
dst_fmt
,
dst_fmt
,
value
,
value
)
;
break
;
default
:
return
""
;
}
output_asm_insn
(
buf
,
out_operands
)
;
return
""
;
}
</s>


<s>
void
VEInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
MCRegister
DestReg
,
MCRegister
SrcReg
,
bool
KillSrc
)
const
{
if
(
IsAliasOfSX
(
SrcReg
)
&&
IsAliasOfSX
(
DestReg
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
VE
::
ORri
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
0
)
;
}
else
if
(
VE
::
V64RegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
Register
TmpReg
=
VE
::
SX16
;
Register
SubTmp
=
TRI
->
getSubReg
(
TmpReg
,
VE
::
sub_i32
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
VE
::
LEAzii
)
,
TmpReg
)
.
addImm
(
0
)
.
addImm
(
0
)
.
addImm
(
256
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
I
,
DL
,
get
(
VE
::
VORmvl
)
,
DestReg
)
.
addImm
(
M1
(
0
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addReg
(
SubTmp
,
getKillRegState
(
true
)
)
;
MIB
.
getInstr
(
)
->
addRegisterKilled
(
TmpReg
,
TRI
,
true
)
;
}
else
if
(
VE
::
VMRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
VE
::
ANDMmm
)
,
DestReg
)
.
addReg
(
VE
::
VM0
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
else
if
(
VE
::
VM512RegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
const
unsigned
SubRegIdx
[
]
=
{
VE
::
sub_vm_even
,
VE
::
sub_vm_odd
}
;
unsigned
int
NumSubRegs
=
2
;
copyPhysSubRegs
(
MBB
,
I
,
DL
,
DestReg
,
SrcReg
,
KillSrc
,
get
(
VE
::
ANDMmm
)
,
NumSubRegs
,
SubRegIdx
,
&
getRegisterInfo
(
)
)
;
}
else
if
(
VE
::
F128RegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
const
unsigned
SubRegIdx
[
]
=
{
VE
::
sub_even
,
VE
::
sub_odd
}
;
unsigned
int
NumSubRegs
=
2
;
copyPhysSubRegs
(
MBB
,
I
,
DL
,
DestReg
,
SrcReg
,
KillSrc
,
get
(
VE
::
ORri
)
,
NumSubRegs
,
SubRegIdx
,
&
getRegisterInfo
(
)
)
;
}
else
{
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
dbgs
(
)
<<
"Impossible reg-to-reg copy from "
<<
printReg
(
SrcReg
,
TRI
)
<<
" to "
<<
printReg
(
DestReg
,
TRI
)
<<
"\n"
;
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
}
</s>


<s> unsigned MandarinInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { MI -> dump ( ) ; return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> void AnalyzeReturn ( const SmallVectorImpl < ISD :: OutputArg > & Outs , CCAssignFn Fn ) { PreAnalyzeReturnForF128 ( Outs ) ; CCState :: AnalyzeReturn ( Outs , Fn ) ; OriginalArgWasFloat . clear ( ) ; OriginalArgWasF128 . clear ( ) ; } </s>

AnalyzeReturn - Analyze the returned values of a return , incorporating info about the result values into this state .


<s> void AMDGPUUnifyDivergentExitNodes :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < PostDominatorTreeWrapperPass > ( ) ; AU . addRequired < LegacyDivergenceAnalysis > ( ) ; AU . addPreserved < LegacyDivergenceAnalysis > ( ) ; AU . addPreservedID ( BreakCriticalEdgesID ) ; AU . addPreservedID ( LowerSwitchID ) ; FunctionPass :: getAnalysisUsage ( AU ) ; AU . addRequired < TargetTransformInfoWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> const JVMSubtarget * JVMTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < JVMSubtarget > ( TargetTriple , CPU , FS , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

JVM JVM JVM "target-cpu" "target-features" JVM


<s> BitVector AAPRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; Reserved . set ( getLinkRegister ( ) ) ; Reserved . set ( getStackPtrRegister ( ) ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( getFramePtrRegister ( ) ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void mips_split_128bit_move ( rtx dest , rtx src ) { int byte , index ; rtx low_dest , low_src , d , s ; if ( FP_REG_RTX_P ( dest ) ) { gcc_assert ( ! MEM_P ( src ) ) ; rtx new_dest = dest ; if ( ! TARGET_64BIT ) { if ( GET_MODE ( dest ) != V4SImode ) new_dest = simplify_gen_subreg ( V4SImode , dest , GET_MODE ( dest ) , 0 ) ; } else { if ( GET_MODE ( dest ) != V2DImode ) new_dest = simplify_gen_subreg ( V2DImode , dest , GET_MODE ( dest ) , 0 ) ; } for ( byte = 0 , index = 0 ; byte < GET_MODE_SIZE ( TImode ) ; byte += UNITS_PER_WORD , index ++ ) { s = mips_subword_at_byte ( src , byte ) ; if ( ! TARGET_64BIT ) emit_insn ( gen_msa_insert_w ( new_dest , s , new_dest , GEN_INT ( 1 << index ) ) ) ; else emit_insn ( gen_msa_insert_d ( new_dest , s , new_dest , GEN_INT ( 1 << index ) ) ) ; } } else if ( FP_REG_RTX_P ( src ) ) { gcc_assert ( ! MEM_P ( dest ) ) ; rtx new_src = src ; if ( ! TARGET_64BIT ) { if ( GET_MODE ( src ) != V4SImode ) new_src = simplify_gen_subreg ( V4SImode , src , GET_MODE ( src ) , 0 ) ; } else { if ( GET_MODE ( src ) != V2DImode ) new_src = simplify_gen_subreg ( V2DImode , src , GET_MODE ( src ) , 0 ) ; } for ( byte = 0 , index = 0 ; byte < GET_MODE_SIZE ( TImode ) ; byte += UNITS_PER_WORD , index ++ ) { d = mips_subword_at_byte ( dest , byte ) ; if ( ! TARGET_64BIT ) emit_insn ( gen_msa_copy_s_w ( d , new_src , GEN_INT ( index ) ) ) ; else emit_insn ( gen_msa_copy_s_d ( d , new_src , GEN_INT ( index ) ) ) ; } } else { low_dest = mips_subword_at_byte ( dest , 0 ) ; low_src = mips_subword_at_byte ( src , 0 ) ; gcc_assert ( REG_P ( low_dest ) && REG_P ( low_src ) ) ; if ( REGNO ( low_dest ) <= REGNO ( low_src ) ) { for ( byte = 0 ; byte < GET_MODE_SIZE ( TImode ) ; byte += UNITS_PER_WORD ) { d = mips_subword_at_byte ( dest , byte ) ; s = mips_subword_at_byte ( src , byte ) ; mips_emit_move ( d , s ) ; } } else { for ( byte = GET_MODE_SIZE ( TImode ) - UNITS_PER_WORD ; byte >= 0 ; byte -= UNITS_PER_WORD ) { d = mips_subword_at_byte ( dest , byte ) ; s = mips_subword_at_byte ( src , byte ) ; mips_emit_move ( d , s ) ; } } } } </s>


"%qs attribute only applies to functions"

"%qs attribute argument not a string constant"

Handle an `` sp_switch '' attribute ; arguments as in struct attribute_spec.handler .


<s>
RangeTree
::
Node
*
RangeTree
::
remove
(
Node
*
N
,
const
Node
*
D
)
{
assert
(
N
!=
nullptr
)
;
if
(
N
!=
D
)
{
assert
(
N
->
Range
!=
D
->
Range
&&
"N and D should not be equal"
)
;
if
(
D
->
Range
<
N
->
Range
)
N
->
Left
=
remove
(
N
->
Left
,
D
)
;
else
N
->
Right
=
remove
(
N
->
Right
,
D
)
;
return
rebalance
(
update
(
N
)
)
;
}
if
(
N
->
Left
==
nullptr
||
N
->
Right
==
nullptr
)
return
(
N
->
Left
==
nullptr
)
N
->
Right
:
N
->
Left
;
Node
*
M
=
N
->
Left
;
while
(
M
->
Right
)
M
=
M
->
Right
;
M
->
Left
=
remove
(
N
->
Left
,
M
)
;
M
->
Right
=
N
->
Right
;
return
rebalance
(
update
(
M
)
)
;
}
</s>

remove - Remove the specified key/value pair from the map , but do not erase it .


<s> SICExprKind getKind ( ) const { return Kind ; } </s>


<s> int compute_a_shift_cc ( rtx insn ATTRIBUTE_UNUSED , rtx * operands ) { rtx shift = operands [ 3 ] ; enum machine_mode mode = GET_MODE ( shift ) ; enum rtx_code code = GET_CODE ( shift ) ; enum shift_type shift_type ; enum shift_mode shift_mode ; struct shift_info info ; int n ; switch ( mode ) { case QImode : shift_mode = QIshift ; break ; case HImode : shift_mode = HIshift ; break ; case SImode : shift_mode = SIshift ; break ; default : gcc_unreachable ( ) ; } switch ( code ) { case ASHIFTRT : shift_type = SHIFT_ASHIFTRT ; break ; case LSHIFTRT : shift_type = SHIFT_LSHIFTRT ; break ; case ASHIFT : shift_type = SHIFT_ASHIFT ; break ; default : gcc_unreachable ( ) ; } gcc_assert ( GET_CODE ( operands [ 2 ] ) == CONST_INT ) ; n = INTVAL ( operands [ 2 ] ) ; if ( n < 0 ) n = 0 ; else if ( ( unsigned int ) n > GET_MODE_BITSIZE ( mode ) ) n = GET_MODE_BITSIZE ( mode ) ; get_shift_alg ( shift_type , shift_mode , n , & info ) ; switch ( info . alg ) { case SHIFT_SPECIAL : if ( info . remainder == 0 ) return info . cc_special ; case SHIFT_INLINE : return info . cc_inline ; case SHIFT_ROT_AND : return CC_SET_ZNV ; case SHIFT_LOOP : if ( info . shift2 != NULL ) { if ( n % 2 ) return info . cc_inline ; } return CC_CLOBBER ; default : gcc_unreachable ( ) ; } } </s>

Compute which flag bits are valid after a shift insn .


<s> bool AMDGPUAsmPrinter :: doFinalization ( Module & M ) { CallGraphResourceInfo . clear ( ) ; return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s>
void
pa_asm_output_aligned_local
(
FILE
*
stream
,
const
char
*
name
,
unsigned
HOST_WIDE_INT
size
,
unsigned
int
align
)
{
bss_section
(
)
;
fprintf
(
stream
,
"\t.align %u\n"
,
align
/
BITS_PER_UNIT
)
;
fprintf
(
stream
,
"%s"
,
LOCAL_ASM_OP
)
;
assemble_name
(
stream
,
name
)
;
fprintf
(
stream
,
"\n"
)
;
ASM_OUTPUT_LABEL
(
stream
,
name
)
;
fprintf
(
stream
,
"\t.block "
HOST_WIDE_INT_PRINT_UNSIGNED
"\n"
,
size
)
;
}
</s>

We ca n't use .comm for local common storage as the SOM linker effectively treats the symbol as universal and uses the same storage for local symbols with the same name in different object files . The .block directive reserves an uninitialized block of storage . However , it 's not common storage . Fortunately , GCC never requests common storage with the same name in any given translation unit .

pa
"\t.align %u\n"
"%s"
"\n"
"\t.block "
"\n"


<s> unsigned getPointerSize ( ) const { return 4 ; } </s>

Layout pointer size in bytes , rounded up to a whole number of bytes .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , RM , CM , OL ) , Subtarget ( TT , CPU , FS ) , JITInfo ( ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) { if ( FloatABIType == FloatABI :: Default ) FloatABIType = FloatABI :: Soft ; } </s>


<s> bool M88kMCAsmBackend :: mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> const uint16_t * XCoreRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { XCore :: R4 , XCore :: R5 , XCore :: R6 , XCore :: R7 , XCore :: R8 , XCore :: R9 , XCore :: R10 , 0 } ; static const uint16_t CalleeSavedRegsFP [ ] = { XCore :: R4 , XCore :: R5 , XCore :: R6 , XCore :: R7 , XCore :: R8 , XCore :: R9 , 0 } ; const TargetFrameLowering * TFI = MF -> getTarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( * MF ) ) return CalleeSavedRegsFP ; return CalleeSavedRegs ; } </s>


<s> static bool isShiftedMask ( uint64_t I , uint64_t & Pos , uint64_t & Size ) { if ( ! isShiftedMask_64 ( I ) ) return false ; Size = countPopulation ( I ) ; Pos = countTrailingZeros ( I ) ; return true ; } </s>

Return true if this APInt value contains a non-empty sequence of ones with the remainder zero .


Write PATCH_AREA_SIZE NOPs into the asm outfile FILE around a function entry . If RECORD_P is true and the target supports named sections , the location of the NOPs will be recorded in a special object section called `` __patchable_function_entries '' . This routine may be called twice per function to put NOPs before and after the function entry .


<s>
void
dump
(
SelectionDAG
*
DAG
=
nullptr
)
{
dbgs
(
)
<<
"X86ISelAddressMode "
<<
this
<<
'\n'
;
dbgs
(
)
<<
"Base_Reg "
;
if
(
Base_Reg
.
getNode
(
)
)
Base_Reg
.
getNode
(
)
->
dump
(
DAG
)
;
else
dbgs
(
)
<<
"nul\n"
;
if
(
BaseType
==
FrameIndexBase
)
dbgs
(
)
<<
" Base.FrameIndex "
<<
Base_FrameIndex
<<
'\n'
;
dbgs
(
)
<<
" Scale "
<<
Scale
<<
'\n'
<<
"IndexReg "
;
if
(
IndexReg
.
getNode
(
)
)
IndexReg
.
getNode
(
)
->
dump
(
DAG
)
;
else
dbgs
(
)
<<
"nul\n"
;
dbgs
(
)
<<
" Disp "
<<
Disp
<<
'\n'
<<
"GV "
;
if
(
GV
)
GV
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" CP "
;
if
(
CP
)
CP
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
'\n'
<<
"ES "
;
if
(
ES
)
dbgs
(
)
<<
ES
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" MCSym "
;
if
(
MCSym
)
dbgs
(
)
<<
MCSym
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" JT"
<<
JT
<<
" Align"
<<
Align
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

X86
"X86ISelAddressMode "
"Base_Reg "
"nul\n"
" Base.FrameIndex "
" Scale "
"IndexReg "
"nul\n"
" Disp "
"GV "
"nul"
" CP "
"nul"
"ES "
"nul"
" MCSym "
"nul"
" JT"
" Align"


<s> static rtx riscv_expand_builtin_direct ( enum insn_code icode , rtx target , tree exp , bool has_target_p ) { struct expand_operand ops [ MAX_RECOG_OPERANDS ] ; int opno = 0 ; if ( has_target_p ) create_output_operand ( & ops [ opno ++ ] , target , TYPE_MODE ( TREE_TYPE ( exp ) ) ) ; gcc_assert ( opno + call_expr_nargs ( exp ) == insn_data [ icode ] . n_generator_args ) ; for ( int argno = 0 ; argno < call_expr_nargs ( exp ) ; argno ++ ) riscv_prepare_builtin_arg ( & ops [ opno ++ ] , exp , argno ) ; return riscv_expand_builtin_insn ( icode , opno , ops , has_target_p ) ; } </s>

Expand a RISCV_BUILTIN_DIRECT or RISCV_BUILTIN_DIRECT_NO_TARGET function ; HAS_TARGET_P says which . EXP is the CALL_EXPR that calls the function and ICODE is the code of the associated .md pattern . TARGET , if nonnull , suggests a good place to put the result .


<s> virtual unsigned int execute ( function * fun ) { return rs6000_analyze_swaps ( fun ) ; } </s>


"SVE requires vector length in multiples of 128!"

"Minimum SVE vector size should not be larger than its maximum!"


<s> static void pop ( int rn ) { rtx reg = gen_rtx_REG ( word_mode , rn ) ; rtx x ; if ( TARGET_H8300 ) x = gen_pop_h8300 ( reg ) ; else if ( ! TARGET_NORMAL_MODE ) x = gen_pop_h8300hs_advanced ( reg ) ; else x = gen_pop_h8300hs_normal ( reg ) ; x = emit_insn ( x ) ; REG_NOTES ( x ) = gen_rtx_EXPR_LIST ( REG_INC , stack_pointer_rtx , 0 ) ; } </s>

Output RTL to pop register RN from the stack .


<s> void M68kELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; this -> TM = & static_cast < const M68kTargetMachine & > ( TM ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; } </s>

This method must be called before any actual lowering is done .


<s> static rtx s390_prologue_plus_offset ( rtx target , rtx reg , rtx offset , bool frame_related_p ) { rtx_insn * insn ; rtx orig_offset = offset ; gcc_assert ( REG_P ( target ) ) ; gcc_assert ( REG_P ( reg ) ) ; gcc_assert ( CONST_INT_P ( offset ) ) ; if ( offset == const0_rtx ) { insn = emit_move_insn ( target , reg ) ; } else if ( DISP_IN_RANGE ( INTVAL ( offset ) ) ) { insn = emit_move_insn ( target , gen_rtx_PLUS ( Pmode , reg , offset ) ) ; } else { if ( ! satisfies_constraint_K ( offset ) && ( ! TARGET_EXTIMM || ( ! satisfies_constraint_Op ( offset ) && ! satisfies_constraint_On ( offset ) ) ) ) offset = force_const_mem ( Pmode , offset ) ; if ( target != reg ) { insn = emit_move_insn ( target , reg ) ; RTX_FRAME_RELATED_P ( insn ) = frame_related_p ? 1 : 0 ; } insn = emit_insn ( gen_add2_insn ( target , offset ) ) ; if ( ! CONST_INT_P ( offset ) ) { annotate_constant_pool_refs ( insn ) ; if ( frame_related_p ) add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( target , gen_rtx_PLUS ( Pmode , target , orig_offset ) ) ) ; } } RTX_FRAME_RELATED_P ( insn ) = frame_related_p ? 1 : 0 ; if ( flag_stack_clash_protection && target == stack_pointer_rtx ) add_reg_note ( insn , REG_STACK_CHECK , const0_rtx ) ; return insn ; } </s>

Calculate TARGET = REG + OFFSET as s390_emit_prologue would do it . - push too big immediates to the literal pool and annotate the refs - emit frame related notes for stack pointer changes .


<s> bool Cpu0PassConfig :: addPreEmitPass ( ) { Cpu0TargetMachine & TM = getCpu0TargetMachine ( ) ; addPass ( createCpu0DelJmpPass ( TM ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


"Unknown register class to store to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> std :: pair < unsigned , const TargetRegisterClass * > AArch64TargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & AArch64 :: GPR64commonRegClass ) ; return std :: make_pair ( 0U , & AArch64 :: GPR32commonRegClass ) ; case 'w' : if ( VT . getSizeInBits ( ) == 32 ) return std :: make_pair ( 0U , & AArch64 :: FPR32RegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & AArch64 :: FPR64RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & AArch64 :: FPR128RegClass ) ; break ; case 'x' : if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & AArch64 :: FPR128_loRegClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( AArch64 :: NZCV ) , & AArch64 :: CCRRegClass ) ; std :: pair < unsigned , const TargetRegisterClass * > Res ; Res = TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; if ( ! Res . second ) { unsigned Size = Constraint . size ( ) ; if ( ( Size == 4 || Size == 5 ) && Constraint [ 0 ] == '{' && tolower ( Constraint [ 1 ] ) == 'v' && Constraint [ Size - 1 ] == '}' ) { int RegNo ; bool Failed = Constraint . slice ( 2 , Size - 1 ) . getAsInteger ( 10 , RegNo ) ; if ( ! Failed && RegNo >= 0 && RegNo <= 31 ) { if ( VT != MVT :: Other && VT . getSizeInBits ( ) == 64 ) { Res . first = AArch64 :: FPR64RegClass . getRegister ( RegNo ) ; Res . second = & AArch64 :: FPR64RegClass ; } else { Res . first = AArch64 :: FPR128RegClass . getRegister ( RegNo ) ; Res . second = & AArch64 :: FPR128RegClass ; } } } } return Res ; } </s>

Given a physical register constraint ( e.g .


<s> static rtx_insn * pdp11_md_asm_adjust ( vec < rtx > & , vec < rtx > & , vec < machine_mode > & , vec < const char * > & , vec < rtx > & clobbers , HARD_REG_SET & clobbered_regs ) { clobbers . safe_push ( gen_rtx_REG ( CCmode , CC_REGNUM ) ) ; SET_HARD_REG_BIT ( clobbered_regs , CC_REGNUM ) ; if ( TARGET_FPU ) { clobbers . safe_push ( gen_rtx_REG ( CCmode , FCC_REGNUM ) ) ; SET_HARD_REG_BIT ( clobbered_regs , FCC_REGNUM ) ; } return NULL ; } </s>

Prepend to CLOBBERS hard registers that are automatically clobbered for an asm We do this for CC_REGNUM and FCC_REGNUM ( on FPU target ) to maintain source compatibility with the original cc0-based compiler .


<s> static void aarch64_option_restore ( struct gcc_options * opts , struct cl_target_option * ptr ) { opts -> x_explicit_tune_core = ptr -> x_explicit_tune_core ; selected_tune = aarch64_get_tune_cpu ( ptr -> x_explicit_tune_core ) ; opts -> x_explicit_arch = ptr -> x_explicit_arch ; selected_arch = aarch64_get_arch ( ptr -> x_explicit_arch ) ; opts -> x_aarch64_override_tune_string = ptr -> x_aarch64_override_tune_string ; opts -> x_aarch64_branch_protection_string = ptr -> x_aarch64_branch_protection_string ; if ( opts -> x_aarch64_branch_protection_string ) { aarch64_parse_branch_protection ( opts -> x_aarch64_branch_protection_string , NULL ) ; } aarch64_override_options_internal ( opts ) ; } </s>

Implements TARGET_OPTION_RESTORE . Restore the backend codegen decisions using the information saved in PTR .


<s> static rtx swap_selector_for_mode ( machine_mode mode ) { unsigned int swap2 [ 16 ] = { 7 , 6 , 5 , 4 , 3 , 2 , 1 , 0 , 15 , 14 , 13 , 12 , 11 , 10 , 9 , 8 } ; unsigned int swap4 [ 16 ] = { 3 , 2 , 1 , 0 , 7 , 6 , 5 , 4 , 11 , 10 , 9 , 8 , 15 , 14 , 13 , 12 } ; unsigned int swap8 [ 16 ] = { 1 , 0 , 3 , 2 , 5 , 4 , 7 , 6 , 9 , 8 , 11 , 10 , 13 , 12 , 15 , 14 } ; unsigned int swap16 [ 16 ] = { 0 , 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 } ; unsigned int * swaparray , i ; rtx perm [ 16 ] ; switch ( mode ) { case E_V2DFmode : case E_V2DImode : swaparray = swap2 ; break ; case E_V4SFmode : case E_V4SImode : swaparray = swap4 ; break ; case E_V8HImode : swaparray = swap8 ; break ; case E_V16QImode : swaparray = swap16 ; break ; default : gcc_unreachable ( ) ; } for ( i = 0 ; i < 16 ; ++ i ) perm [ i ] = GEN_INT ( swaparray [ i ] ) ; return force_reg ( V16QImode , gen_rtx_CONST_VECTOR ( V16QImode , gen_rtvec_v ( 16 , perm ) ) ) ; } </s>

Return a constant vector for use as a little-endian permute control vector to reverse the order of elements of the given vector mode .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < MachinePostDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool X86RegisterInfo :: hasReservedSpillSlot ( MachineFunction & MF , unsigned Reg , int & FrameIdx ) const { if ( Reg == FramePtr && hasFP ( MF ) ) { FrameIdx = MF . getFrameInfo ( ) -> getObjectIndexBegin ( ) ; return true ; } return false ; } </s>

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register .


<s> bool isPredicated ( const MachineInstr * MI ) const { int PIdx = MI -> findFirstPredOperandIdx ( ) ; return PIdx != - 1 && MI -> getOperand ( PIdx ) . getImm ( ) != ARMCC :: AL ; } </s>

Returns true if the instruction is already predicated .


<s> enum reg_class mmix_preferred_reload_class ( rtx x ATTRIBUTE_UNUSED , enum reg_class class ) { return GET_CODE ( x ) == MOD && GET_MODE ( x ) == DImode ? REMAINDER_REG : class ; } </s>

PREFERRED_RELOAD_CLASS . We need to extend the reload class of REMAINDER_REG and HIMULT_REG .


<s> bool SNESFrameLowering :: hasFP ( const MachineFunction & MF ) const { const SNESMachineFunctionInfo * FuncInfo = MF . getInfo < SNESMachineFunctionInfo > ( ) ; return ( FuncInfo -> getHasSpills ( ) || FuncInfo -> getHasAllocas ( ) || FuncInfo -> getHasStackArgs ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool AArch64LoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { const TargetMachine & TM = Fn . getTarget ( ) ; TII = static_cast < const AArch64InstrInfo * > ( TM . getInstrInfo ( ) ) ; TRI = TM . getRegisterInfo ( ) ; bool Modified = false ; for ( auto & MBB : Fn ) Modified |= optimizeBlock ( MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool AArch64PassConfig :: addInstSelector ( ) { addPass ( createAArch64ISelDag ( getAArch64TargetMachine ( ) , getOptLevel ( ) ) ) ; if ( Triple ( TM -> getTargetTriple ( ) ) . isOSBinFormatELF ( ) && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createAArch64CleanupLocalDynamicTLSPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> virtual const MipsInstrInfo * getInstrInfo ( ) const { return InstrInfo ; } </s>


<s> bool nds32_isr_function_critical_p ( tree func ) { tree t_intr ; tree t_excp ; tree t_critical ; tree attrs ; if ( TREE_CODE ( func ) != FUNCTION_DECL ) abort ( ) ; attrs = DECL_ATTRIBUTES ( func ) ; t_intr = lookup_attribute ( "interrupt" , attrs ) ; t_excp = lookup_attribute ( "exception" , attrs ) ; t_critical = lookup_attribute ( "critical" , attrs ) ; if ( ( t_intr == NULL_TREE ) && ( t_excp == NULL_TREE ) ) return false ; if ( t_critical != NULL_TREE ) return true ; if ( t_intr != NULL_TREE || t_excp != NULL_TREE ) { char target_str [ 100 ] ; char * critical_str ; tree t_check ; tree string_arg ; t_check = t_intr ? t_intr : t_excp ; if ( TREE_CODE ( TREE_VALUE ( TREE_VALUE ( t_check ) ) ) == STRING_CST ) { string_arg = TREE_VALUE ( TREE_VALUE ( t_check ) ) ; strcpy ( target_str , TREE_STRING_POINTER ( string_arg ) ) ; critical_str = strstr ( target_str , "critical" ) ; if ( critical_str ) return true ; } } return false ; } </s>

Return true if FUNC is a isr function with critical attribute .

nds32 "interrupt" "exception" "critical" 100 "critical"


"TRUE - Frame size is too large for D-Form.\n"

"TRUE - Not fixed frame object that requires "

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> bool X86TargetLowering :: IsEligibleForTailCallOptimization ( SDValue Callee , unsigned CalleeCC , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned CallerCC = MF . getFunction ( ) -> getCallingConv ( ) ; return CalleeCC == CallingConv :: Fast && CallerCC == CalleeCC ; } </s>

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization .


<s> bool mips_expand_vec_perm_const ( rtx operands [ 4 ] ) { struct expand_vec_perm_d d ; int i , nelt , which ; unsigned char orig_perm [ MAX_VECT_LEN ] ; rtx sel ; bool ok ; d . target = operands [ 0 ] ; d . op0 = operands [ 1 ] ; d . op1 = operands [ 2 ] ; sel = operands [ 3 ] ; d . vmode = GET_MODE ( d . target ) ; gcc_assert ( VECTOR_MODE_P ( d . vmode ) ) ; d . nelt = nelt = GET_MODE_NUNITS ( d . vmode ) ; d . testing_p = false ; memset ( orig_perm , 0 , MAX_VECT_LEN ) ; for ( i = which = 0 ; i < nelt ; ++ i ) { rtx e = XVECEXP ( sel , 0 , i ) ; int ei = INTVAL ( e ) & ( 2 * nelt - 1 ) ; which |= ( ei < nelt ? 1 : 2 ) ; orig_perm [ i ] = ei ; } memcpy ( d . perm , orig_perm , MAX_VECT_LEN ) ; switch ( which ) { default : gcc_unreachable ( ) ; case 3 : d . one_vector_p = false ; if ( ! rtx_equal_p ( d . op0 , d . op1 ) ) break ; case 2 : for ( i = 0 ; i < nelt ; ++ i ) d . perm [ i ] &= nelt - 1 ; d . op0 = d . op1 ; d . one_vector_p = true ; break ; case 1 : d . op1 = d . op0 ; d . one_vector_p = true ; break ; } ok = mips_expand_vec_perm_const_1 ( & d ) ; if ( ! ok && which == 3 ) { d . op0 = operands [ 1 ] ; d . op1 = operands [ 2 ] ; d . one_vector_p = false ; memcpy ( d . perm , orig_perm , MAX_VECT_LEN ) ; ok = mips_expand_vec_perm_const_1 ( & d ) ; } return ok ; } </s>


<s> bool visium_can_use_return_insn_p ( void ) { return reload_completed && visium_frame_size == 0 && ! visium_interrupt_function_p ( ) ; } </s>

Return true if it is appropriate to emit ` return ' instructions in the body of a function .


<s> static rtx adjust_operand ( rtx op , HOST_WIDE_INT * start ) { machine_mode mode ; int op_size ; if ( GET_CODE ( op ) == SUBREG && ( GET_MODE_BITSIZE ( GET_MODE ( op ) ) > GET_MODE_BITSIZE ( GET_MODE ( SUBREG_REG ( op ) ) ) ) ) { if ( start ) * start -= GET_MODE_BITSIZE ( GET_MODE ( op ) ) - GET_MODE_BITSIZE ( GET_MODE ( SUBREG_REG ( op ) ) ) ; op = SUBREG_REG ( op ) ; } op_size = GET_MODE_BITSIZE ( GET_MODE ( op ) ) ; if ( op_size < 32 ) { if ( start ) * start += 32 - op_size ; op_size = 32 ; } mode = mode_for_size ( op_size , MODE_INT , 0 ) ; if ( mode != GET_MODE ( op ) ) op = gen_rtx_SUBREG ( mode , op , 0 ) ; return op ; } </s>

When insv and ext [ sz ] v ar passed a TI SUBREG , we want to strip it off and adjust the start offset .


<s>
void
J2MCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
uint32_t
Binary
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
unsigned
Size
=
Desc
.
getSize
(
)
;
if
(
!
Size
)
llvm_unreachable
(
"Desc.getSize() returns 0"
)
;
EmitInstruction
(
Binary
,
Size
,
STI
,
OS
)
;
}
</s>

Encode the given Inst to bytes and append to CB .


<s> bool shouldTransformSignedTruncationCheck ( EVT XVT , unsigned KeptBits ) const override { if ( XVT . isVector ( ) ) return false ; auto VTIsOk = [ ] ( EVT VT ) -> bool { return VT == MVT :: i8 || VT == MVT :: i16 || VT == MVT :: i32 || VT == MVT :: i64 ; } ; MVT KeptBitsVT = MVT :: getIntegerVT ( KeptBits ) ; return VTIsOk ( XVT ) && VTIsOk ( KeptBitsVT ) ; } </s>

Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be truncating or not : ( add x , ( 1 < < ( KeptBits-1 ) ) ) srccond ( 1 < < KeptBits ) Into it 's more traditional form : ( ( x < < C ) a > > C ) dstcond x Return true if we should transform .


<s>
void
M68kDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
SDLoc
DL
(
Node
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
switch
(
Opcode
)
{
default
:
break
;
case
M68kISD
::
GLOBAL_BASE_REG
:
ReplaceNode
(
Node
,
getGlobalBaseReg
(
)
)
;
return
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> RegisterBankInfo :: InstructionMapping ARMRegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { auto Opc = MI . getOpcode ( ) ; if ( ! isPreISelGenericOpcode ( Opc ) ) { InstructionMapping Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; } using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & ARM :: ValueMappings [ 0 ] ; switch ( Opc ) { case G_ADD : case G_LOAD : OperandsMapping = & ARM :: ValueMappings [ 0 ] ; break ; case G_FRAME_INDEX : OperandsMapping = getOperandsMapping ( { & ARM :: ValueMappings [ 0 ] , nullptr } ) ; break ; default : return InstructionMapping { } ; } return InstructionMapping { DefaultMappingID , 1 , OperandsMapping , NumOperands } ; } </s>

Get the mapping of the different operands of MI on the register bank .


<s>
void
AArch64InstrInfo
::
decomposeStackOffsetForFrameOffsets
(
const
StackOffset
&
Offset
,
int64_t
&
NumBytes
,
int64_t
&
NumPredicateVectors
,
int64_t
&
NumDataVectors
)
{
assert
(
Offset
.
getScalable
(
)
%
2
==
0
&&
"Invalid frame offset"
)
;
NumBytes
=
Offset
.
getFixed
(
)
;
NumDataVectors
=
0
;
NumPredicateVectors
=
Offset
.
getScalable
(
)
/
2
;
if
(
NumPredicateVectors
%
8
==
0
||
NumPredicateVectors
<
64
||
NumPredicateVectors
>
62
)
{
NumDataVectors
=
NumPredicateVectors
/
8
;
NumPredicateVectors
-=
NumDataVectors
*
8
;
}
}
</s>

Returns the offset in parts to which this frame offset can be decomposed for the purpose of describing a frame offset .


<s> void ARMAsmPrinter :: emitStartOfAsmFile ( Module & M ) { const Triple & TT = TM . getTargetTriple ( ) ; OutStreamer -> emitAssemblerFlag ( MCAF_SyntaxUnified ) ; if ( TT . isOSBinFormatELF ( ) ) emitAttributes ( ) ; if ( ! M . getModuleInlineAsm ( ) . empty ( ) && TT . isThumb ( ) ) OutStreamer -> emitAssemblerFlag ( MCAF_Code16 ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the start of their file .


<s> bool PPCTargetLowering :: SelectAddressRegReg ( SDValue N , SDValue & Base , SDValue & Index , SelectionDAG & DAG ) const { short imm = 0 ; if ( N . getOpcode ( ) == ISD :: ADD ) { if ( isIntS16Immediate ( N . getOperand ( 1 ) , imm ) ) return false ; if ( N . getOperand ( 1 ) . getOpcode ( ) == PPCISD :: Lo ) return false ; Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } else if ( N . getOpcode ( ) == ISD :: OR ) { if ( isIntS16Immediate ( N . getOperand ( 1 ) , imm ) ) return false ; APInt LHSKnownZero , LHSKnownOne ; APInt RHSKnownZero , RHSKnownOne ; DAG . ComputeMaskedBits ( N . getOperand ( 0 ) , LHSKnownZero , LHSKnownOne ) ; if ( LHSKnownZero . getBoolValue ( ) ) { DAG . ComputeMaskedBits ( N . getOperand ( 1 ) , RHSKnownZero , RHSKnownOne ) ; if ( ~ ( LHSKnownZero | RHSKnownZero ) == 0 ) { Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } } } return false ; } </s>

SelectAddressRegReg - Given the specified addressed , check to see if it can be more efficiently represented as [ r+imm ] .


<s> static rtx bfin_function_arg ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int bytes = ( mode == BLKmode ) ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ; if ( mode == VOIDmode ) return GEN_INT ( cum -> call_cookie ) ; if ( bytes == - 1 ) return NULL_RTX ; if ( cum -> nregs ) return gen_rtx_REG ( mode , * ( cum -> arg_regs ) ) ; return NULL_RTX ; } </s>

Define where to put the arguments to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) .


<s>
bool
SystemZAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
;
unsigned
Dialect
=
getMAIAssemblerDialect
(
)
;
FeatureBitset
MissingFeatures
;
MatchResult
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MissingFeatures
,
MatchingInlineAsm
,
Dialect
)
;
switch
(
MatchResult
)
{
case
Match_Success
:
Inst
.
setLoc
(
IDLoc
)
;
Out
.
emitInstruction
(
Inst
,
getSTI
(
)
)
;
return
false
;
case
Match_MissingFeature
:
{
assert
(
MissingFeatures
.
any
(
)
&&
"Unknown missing feature!"
)
;
std
::
string
Msg
=
"instruction requires:"
;
for
(
unsigned
I
=
0
,
E
=
MissingFeatures
.
size
(
)
;
I
!=
E
;
++
I
)
{
if
(
MissingFeatures
[
I
]
)
{
Msg
+=
" "
;
Msg
+=
getSubtargetFeatureName
(
I
)
;
}
}
return
Error
(
IDLoc
,
Msg
)
;
}
case
Match_InvalidOperand
:
{
SMLoc
ErrorLoc
=
IDLoc
;
if
(
ErrorInfo
!=
~
0ULL
)
{
if
(
ErrorInfo
>=
Operands
.
size
(
)
)
return
Error
(
IDLoc
,
"too few operands for instruction"
)
;
ErrorLoc
=
(
(
SystemZOperand
&
)
*
Operands
[
ErrorInfo
]
)
.
getStartLoc
(
)
;
if
(
ErrorLoc
==
SMLoc
(
)
)
ErrorLoc
=
IDLoc
;
}
return
Error
(
ErrorLoc
,
"invalid operand for instruction"
)
;
}
case
Match_MnemonicFail
:
{
FeatureBitset
FBS
=
ComputeAvailableFeatures
(
getSTI
(
)
.
getFeatureBits
(
)
)
;
std
::
string
Suggestion
=
SystemZMnemonicSpellCheck
(
(
(
SystemZOperand
&
)
*
Operands
[
0
]
)
.
getToken
(
)
,
FBS
,
Dialect
)
;
return
Error
(
IDLoc
,
"invalid instruction"
+
Suggestion
,
(
(
SystemZOperand
&
)
*
Operands
[
0
]
)
.
getLocRange
(
)
)
;
}
}
llvm_unreachable
(
"Unexpected match type"
)
;
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .

SystemZ
SystemZ
"Unknown missing feature!"
"instruction requires:"
0
" "
0ULL
"too few operands for instruction"
SystemZ
"invalid operand for instruction"
SystemZ
SystemZ
0
"invalid instruction"
SystemZ
0
"Unexpected match type"


<s> static tree tilepro_gimplify_va_arg_expr ( tree valist , tree type , gimple_seq * pre_p , gimple_seq * post_p ATTRIBUTE_UNUSED ) { tree f_args , f_skip ; tree args , skip ; HOST_WIDE_INT size , rsize ; tree addr , tmp ; bool pass_by_reference_p ; f_args = TYPE_FIELDS ( va_list_type_node ) ; f_skip = TREE_CHAIN ( f_args ) ; args = build3 ( COMPONENT_REF , TREE_TYPE ( f_args ) , valist , f_args , NULL_TREE ) ; skip = build3 ( COMPONENT_REF , TREE_TYPE ( f_skip ) , valist , f_skip , NULL_TREE ) ; addr = create_tmp_var ( ptr_type_node , "va_arg" ) ; pass_by_reference_p = pass_by_reference ( NULL , TYPE_MODE ( type ) , type , false ) ; if ( pass_by_reference_p ) type = build_pointer_type ( type ) ; size = int_size_in_bytes ( type ) ; rsize = ( ( size + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ) * UNITS_PER_WORD ; if ( TYPE_ALIGN ( type ) > PARM_BOUNDARY ) { gcc_assert ( STACK_BOUNDARY == PARM_BOUNDARY * 2 ) ; tmp = build2 ( BIT_AND_EXPR , sizetype , fold_convert ( sizetype , unshare_expr ( args ) ) , size_int ( PARM_BOUNDARY / 8 ) ) ; tmp = build2 ( POINTER_PLUS_EXPR , ptr_type_node , unshare_expr ( args ) , tmp ) ; gimplify_assign ( unshare_expr ( args ) , tmp , pre_p ) ; } tmp = fold_build_pointer_plus_hwi ( unshare_expr ( args ) , rsize ) ; tmp = build2 ( TRUTH_AND_EXPR , boolean_type_node , build2 ( GT_EXPR , boolean_type_node , tmp , unshare_expr ( skip ) ) , build2 ( LE_EXPR , boolean_type_node , unshare_expr ( args ) , unshare_expr ( skip ) ) ) ; tmp = build3 ( COND_EXPR , ptr_type_node , tmp , build2 ( POINTER_PLUS_EXPR , ptr_type_node , unshare_expr ( skip ) , size_int ( STACK_POINTER_OFFSET ) ) , unshare_expr ( args ) ) ; gimplify_assign ( addr , tmp , pre_p ) ; tmp = fold_build_pointer_plus_hwi ( addr , rsize ) ; gimplify_assign ( unshare_expr ( args ) , tmp , pre_p ) ; addr = fold_convert ( build_pointer_type ( type ) , addr ) ; if ( pass_by_reference_p ) addr = build_va_arg_indirect_ref ( addr ) ; return build_va_arg_indirect_ref ( addr ) ; } </s>

Implement TARGET_GIMPLIFY_VA_ARG_EXPR . Gimplify va_arg by updating the va_list structure VALIST as required to retrieve an argument of type TYPE , and returning that argument . ret = va_arg ( VALIST , TYPE ) ; generates code equivalent to : paddedsize = ( sizeof ( TYPE ) + 3 ) & -4 ; if ( ( VALIST.__args + paddedsize > VALIST.__skip ) & ( VALIST.__args < = VALIST.__skip ) ) addr = VALIST.__skip + STACK_POINTER_OFFSET ; else addr = VALIST.__args ; VALIST.__args = addr + paddedsize ; ret = * ( TYPE * ) addr ;


<s> bool isToken ( ) const { return Kind == k_Tok ; } </s>


<s> unsigned SIInstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { MachineBasicBlock :: iterator I = MBB . getFirstTerminator ( ) ; unsigned Count = 0 ; unsigned RemovedSize = 0 ; while ( I != MBB . end ( ) ) { MachineBasicBlock :: iterator Next = std :: next ( I ) ; if ( I -> isBranch ( ) || I -> isReturn ( ) ) { RemovedSize += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ; ++ Count ; } I = Next ; } if ( BytesRemoved ) * BytesRemoved = RemovedSize ; return Count ; } </s>

Remove the branching code at the end of the specific MBB .


<s> bool WebAssemblyAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { for ( uint64_t I = 0 ; I < Count ; ++ I ) OS << char ( WebAssembly :: Nop ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .

WebAssembly WebAssembly 0 WebAssembly::Nop


<s> static void rs6000_eliminate_indexed_memrefs ( rtx operands [ 2 ] ) { if ( GET_CODE ( operands [ 0 ] ) == MEM && GET_CODE ( XEXP ( operands [ 0 ] , 0 ) ) != REG && ! legitimate_constant_pool_address_p ( XEXP ( operands [ 0 ] , 0 ) , GET_MODE ( operands [ 0 ] ) , false ) ) operands [ 0 ] = replace_equiv_address ( operands [ 0 ] , copy_addr_to_reg ( XEXP ( operands [ 0 ] , 0 ) ) ) ; if ( GET_CODE ( operands [ 1 ] ) == MEM && GET_CODE ( XEXP ( operands [ 1 ] , 0 ) ) != REG && ! legitimate_constant_pool_address_p ( XEXP ( operands [ 1 ] , 0 ) , GET_MODE ( operands [ 1 ] ) , false ) ) operands [ 1 ] = replace_equiv_address ( operands [ 1 ] , copy_addr_to_reg ( XEXP ( operands [ 1 ] , 0 ) ) ) ; } </s>

Helper for the following . Get rid of [ r+r ] memory refs in cases where it wo n't work ( TImode , TFmode ) .


<s> bool RISCVTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( ! Subtarget . hasExtXCoreVMem ( ) ) return false ; if ( Op -> getOpcode ( ) != ISD :: ADD ) return false ; if ( LSBaseSDNode * LS = dyn_cast < LSBaseSDNode > ( N ) ) { Base = LS -> getBasePtr ( ) ; } else { return false ; } if ( Base == Op -> getOperand ( 0 ) ) { Offset = Op -> getOperand ( 1 ) ; } else if ( Base == Op -> getOperand ( 1 ) ) { Offset = Op -> getOperand ( 0 ) ; } else { return false ; } AM = ISD :: POST_INC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .


<s> int register_ok_for_ldd ( rtx reg ) { if ( GET_CODE ( reg ) != REG ) return 0 ; if ( REGNO ( reg ) < FIRST_PSEUDO_REGISTER ) return ( REGNO ( reg ) % 2 == 0 ) ; else return 1 ; } </s>

Return 1 if reg is a pseudo , or is the first register in a hard register pair . This makes it a candidate for use in ldd and std insns .


Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calling convention CallConv .


<s> virtual const BlackfinRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
SDValue
MipsTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
DL
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
,
TargetLowering
::
CallLoweringInfo
&
CLI
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
MipsCCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_Mips
,
CLI
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Val
=
DAG
.
getCopyFromReg
(
Chain
,
DL
,
RVLocs
[
i
]
.
getLocReg
(
)
,
RVLocs
[
i
]
.
getLocVT
(
)
,
InFlag
)
;
Chain
=
Val
.
getValue
(
1
)
;
InFlag
=
Val
.
getValue
(
2
)
;
if
(
VA
.
isUpperBitsInLoc
(
)
)
{
unsigned
ValSizeInBits
=
Ins
[
i
]
.
ArgVT
.
getSizeInBits
(
)
;
unsigned
LocSizeInBits
=
VA
.
getLocVT
(
)
.
getSizeInBits
(
)
;
unsigned
Shift
=
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExtUpper
ISD
::
SRL
:
ISD
::
SRA
;
Val
=
DAG
.
getNode
(
Shift
,
DL
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getConstant
(
LocSizeInBits
ValSizeInBits
,
VA
.
getLocVT
(
)
)
)
;
}
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
BCvt
:
Val
=
DAG
.
getNode
(
ISD
::
BITCAST
,
DL
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
AExt
:
case
CCValAssign
::
AExtUpper
:
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
DL
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
ZExt
:
case
CCValAssign
::
ZExtUpper
:
Val
=
DAG
.
getNode
(
ISD
::
AssertZext
,
DL
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
DL
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
SExt
:
case
CCValAssign
::
SExtUpper
:
Val
=
DAG
.
getNode
(
ISD
::
AssertSext
,
DL
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
DL
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
}
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .

Mips
Mips
ISD::InputArg
16
Mips
Mips
0
"Can only return in registers!"
1
2
ISD::SRL
ISD::SRA
"Unknown loc info!"
ISD::BITCAST
ISD::TRUNCATE
ISD::AssertZext
ISD::TRUNCATE
ISD::AssertSext
ISD::TRUNCATE


<s> void flush ( ) { OS . flush ( ) ; } </s>

Flush the updater state to LR so it is valid and contains all added segments .


<s> static rtx riscv_shorten_lw_offset ( rtx base , HOST_WIDE_INT offset ) { rtx addr , high ; high = GEN_INT ( offset & ~ CSW_MAX_OFFSET ) ; offset &= CSW_MAX_OFFSET ; if ( ! SMALL_OPERAND ( INTVAL ( high ) ) ) high = force_reg ( Pmode , high ) ; base = force_reg ( Pmode , gen_rtx_PLUS ( Pmode , high , base ) ) ; addr = plus_constant ( Pmode , base , offset ) ; return addr ; } </s>

Modify base + offset so that offset fits within a compressed load/store insn and the excess is added to base .


<s> bool WebAssemblyTargetLowering :: isVectorLoadExtDesirable ( SDValue ExtVal ) const { MVT ExtT = ExtVal . getSimpleValueType ( ) ; MVT MemT = cast < LoadSDNode > ( ExtVal -> getOperand ( 0 ) ) -> getSimpleValueType ( 0 ) ; return ( ExtT == MVT :: v8i16 && MemT == MVT :: v8i8 ) || ( ExtT == MVT :: v4i32 && MemT == MVT :: v4i16 ) || ( ExtT == MVT :: v2i64 && MemT == MVT :: v2i32 ) ; } </s>

Return true if folding a vector load into ExtVal ( a sign , zero , or any extend node ) is profitable .


<s> static int mergeSPUpdates ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , bool doMergeWithPrevious ) { if ( ( doMergeWithPrevious && MBBI == MBB . begin ( ) ) || ( ! doMergeWithPrevious && MBBI == MBB . end ( ) ) ) return 0 ; MachineBasicBlock :: iterator PI = doMergeWithPrevious ? std :: prev ( MBBI ) : MBBI ; MachineBasicBlock :: iterator NI = doMergeWithPrevious ? nullptr : std :: next ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = 0 ; if ( ( Opc == X86 :: ADD64ri32 || Opc == X86 :: ADD64ri8 || Opc == X86 :: ADD32ri || Opc == X86 :: ADD32ri8 || Opc == X86 :: LEA32r || Opc == X86 :: LEA64_32r ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { Offset += PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == X86 :: SUB64ri32 || Opc == X86 :: SUB64ri8 || Opc == X86 :: SUB32ri || Opc == X86 :: SUB32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { Offset -= PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } return Offset ; } </s>

Check the instruction before/after the passed instruction .


<s> bool TLCS900PassConfig :: addPreEmitPass ( ) { PM -> add ( createTLCS900BranchSelectionPass ( ) ) ; return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool ix86_expand_int_vcond ( rtx operands [ ] ) { machine_mode data_mode = GET_MODE ( operands [ 0 ] ) ; machine_mode mode = GET_MODE ( operands [ 4 ] ) ; enum rtx_code code = GET_CODE ( operands [ 3 ] ) ; bool negate = false ; rtx x , cop0 , cop1 ; cop0 = operands [ 4 ] ; cop1 = operands [ 5 ] ; if ( ( code == LT || code == GE ) && data_mode == mode && cop1 == CONST0_RTX ( mode ) && operands [ 1 + ( code == LT ) ] == CONST0_RTX ( data_mode ) && GET_MODE_UNIT_SIZE ( data_mode ) > 1 && GET_MODE_UNIT_SIZE ( data_mode ) <= 8 && ( GET_MODE_SIZE ( data_mode ) == 16 || ( TARGET_AVX2 && GET_MODE_SIZE ( data_mode ) == 32 ) ) ) { rtx negop = operands [ 2 - ( code == LT ) ] ; int shift = GET_MODE_UNIT_BITSIZE ( data_mode ) - 1 ; if ( negop == CONST1_RTX ( data_mode ) ) { rtx res = expand_simple_binop ( mode , LSHIFTRT , cop0 , GEN_INT ( shift ) , operands [ 0 ] , 1 , OPTAB_DIRECT ) ; if ( res != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , res ) ; return true ; } else if ( GET_MODE_INNER ( data_mode ) != DImode && vector_all_ones_operand ( negop , data_mode ) ) { rtx res = expand_simple_binop ( mode , ASHIFTRT , cop0 , GEN_INT ( shift ) , operands [ 0 ] , 0 , OPTAB_DIRECT ) ; if ( res != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , res ) ; return true ; } } if ( ! nonimmediate_operand ( cop1 , mode ) ) cop1 = force_reg ( mode , cop1 ) ; if ( ! general_operand ( operands [ 1 ] , data_mode ) ) operands [ 1 ] = force_reg ( data_mode , operands [ 1 ] ) ; if ( ! general_operand ( operands [ 2 ] , data_mode ) ) operands [ 2 ] = force_reg ( data_mode , operands [ 2 ] ) ; x = ix86_expand_int_sse_cmp ( operands [ 0 ] , code , cop0 , cop1 , operands [ 1 ] , operands [ 2 ] , & negate ) ; if ( ! x ) return false ; ix86_expand_sse_movcc ( operands [ 0 ] , x , operands [ 1 + negate ] , operands [ 2 - negate ] ) ; return true ; } </s>

Expand a signed integral vector conditional move .


<s> unsigned getPrefetchDistance ( ) { return 2000 ; } </s>

Return the preferred prefetch distance in terms of instructions .


<s> static tree rx_decl_for_addr ( rtx op ) { if ( GET_CODE ( op ) == MEM ) op = XEXP ( op , 0 ) ; if ( GET_CODE ( op ) == CONST ) op = XEXP ( op , 0 ) ; while ( GET_CODE ( op ) == PLUS ) op = XEXP ( op , 0 ) ; if ( GET_CODE ( op ) == SYMBOL_REF ) return SYMBOL_REF_DECL ( op ) ; return NULL_TREE ; } </s>

Find a SYMBOL_REF in a `` standard '' MEM address and return its decl .


<s> TargetLowering :: LegalizeAction VETargetLowering :: getCustomOperationAction ( SDNode & Op ) const { if ( isPackingSupportOpcode ( Op . getOpcode ( ) ) ) return Legal ; if ( isVVPOrVEC ( Op . getOpcode ( ) ) ) return Custom ; return Legal ; } </s>


"the ABI of passing aggregates with %d-byte alignment"

If defined , a C expression that gives the alignment boundary , in bits , of an argument with the specified mode and type . If it is not defined , PARM_BOUNDARY is used for all arguments . V.4 wants long longs and doubles to be double word aligned . Just testing the mode size is a boneheaded way to do this as it means that other types such as complex int are also double word aligned . However , we 're stuck with this because changing the ABI might break existing library interfaces . Quadword align Altivec/VSX vectors . Quadword align large synthetic vector types .


<s> static int arc600_corereg_hazard ( rtx_insn * pred , rtx_insn * succ ) { if ( ! TARGET_ARC600 ) return 0 ; if ( recog_memoized ( succ ) == CODE_FOR_doloop_end_i && LABEL_P ( prev_nonnote_insn ( succ ) ) ) return 0 ; if ( recog_memoized ( succ ) == CODE_FOR_doloop_begin_i ) return 0 ; if ( GET_CODE ( PATTERN ( pred ) ) == SEQUENCE ) pred = as_a < rtx_sequence * > ( PATTERN ( pred ) ) -> insn ( 1 ) ; if ( GET_CODE ( PATTERN ( succ ) ) == SEQUENCE ) succ = as_a < rtx_sequence * > ( PATTERN ( succ ) ) -> insn ( 0 ) ; if ( recog_memoized ( pred ) == CODE_FOR_mulsi_600 || recog_memoized ( pred ) == CODE_FOR_umul_600 || recog_memoized ( pred ) == CODE_FOR_mac_600 || recog_memoized ( pred ) == CODE_FOR_mul64_600 || recog_memoized ( pred ) == CODE_FOR_mac64_600 || recog_memoized ( pred ) == CODE_FOR_umul64_600 || recog_memoized ( pred ) == CODE_FOR_umac64_600 ) return 0 ; subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , PATTERN ( pred ) , NONCONST ) { const_rtx x = * iter ; switch ( GET_CODE ( x ) ) { case SET : case POST_INC : case POST_DEC : case PRE_INC : case PRE_DEC : break ; default : continue ; } rtx dest = XEXP ( x , 0 ) ; if ( REG_P ( dest ) && REGNO ( dest ) >= 32 && REGNO ( dest ) < 61 && ( refers_to_regno_p ( REGNO ( dest ) , REGNO ( dest ) + ( GET_MODE_SIZE ( GET_MODE ( dest ) ) + 3 ) / 4U , PATTERN ( succ ) , 0 ) ) ) return 4 ; } return 0 ; } </s>

Return length adjustment for INSN . For ARC600 : A write to a core reg greater or equal to 32 must not be immediately followed by a use . Anticipate the length requirement to insert a nop between PRED and SUCC to prevent a hazard .


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( CommentStream ) HasCustomInstComment = EmitAnyX86InstComments ( MI , * CommentStream , MII , getRegisterName ) ; unsigned Flags = MI -> getFlags ( ) ; if ( ( TSFlags & X86II :: LOCK ) || ( Flags & X86 :: IP_HAS_LOCK ) ) OS << "\tlock\t" ; if ( ( TSFlags & X86II :: NOTRACK ) || ( Flags & X86 :: IP_HAS_NOTRACK ) ) OS << "\tnotrack\t" ; if ( Flags & X86 :: IP_HAS_REPEAT_NE ) OS << "\trepne\t" ; else if ( Flags & X86 :: IP_HAS_REPEAT ) OS << "\trep\t" ; if ( MI -> getOpcode ( ) == X86 :: CALLpcrel32 && ( STI . getFeatureBits ( ) [ X86 :: Mode64Bit ] ) ) { OS << "\tcallq\t" ; printPCRelImm ( MI , 0 , OS ) ; } else if ( MI -> getOpcode ( ) == X86 :: DATA16_PREFIX && ( STI . getFeatureBits ( ) [ X86 :: Mode16Bit ] ) ) { MCInst Data32MI ( * MI ) ; Data32MI . setOpcode ( X86 :: DATA32_PREFIX ) ; printInstruction ( & Data32MI , OS ) ; } else if ( ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s>
bool
FPS
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
bool
FPIsUsed
=
false
;
assert
(
X86
::
FP6
==
X86
::
FP0
+
6
&&
"Register enums aren't sorted right!"
)
;
for
(
unsigned
i
=
0
;
i
<=
6
;
++
i
)
if
(
MF
.
getRegInfo
(
)
.
isPhysRegUsed
(
X86
::
FP0
+
i
)
)
{
FPIsUsed
=
true
;
break
;
}
if
(
!
FPIsUsed
)
return
false
;
TII
=
MF
.
getTarget
(
)
.
getInstrInfo
(
)
;
bundleCFG
(
MF
)
;
StackTop
=
0
;
SmallPtrSet
<
MachineBasicBlock
*
,
8
>
Processed
;
MachineBasicBlock
*
Entry
=
MF
.
begin
(
)
;
bool
Changed
=
false
;
for
(
df_ext_iterator
<
MachineBasicBlock
*
,
SmallPtrSet
<
MachineBasicBlock
*
,
8
>
>
I
=
df_ext_begin
(
Entry
,
Processed
)
,
E
=
df_ext_end
(
Entry
,
Processed
)
;
I
!=
E
;
++
I
)
Changed
|=
processBasicBlock
(
MF
,
*
*
I
)
;
if
(
MF
.
size
(
)
!=
Processed
.
size
(
)
)
for
(
MachineFunction
::
iterator
BB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
BB
!=
E
;
++
BB
)
if
(
Processed
.
insert
(
BB
)
)
Changed
|=
processBasicBlock
(
MF
,
*
BB
)
;
BlockBundle
.
clear
(
)
;
LiveBundles
.
clear
(
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool needsAlignedVGPRs ( ) const { return GFX90AInsts ; } </s>

Return if operations acting on VGPR tuples require even alignment .


<s> bool mips_get_pic_call_symbol ( rtx * operands , int args_size_opno ) { rtx args_size , symbol ; if ( ! TARGET_RELAX_PIC_CALLS || args_size_opno == - 1 ) return false ; args_size = operands [ args_size_opno ] ; if ( GET_CODE ( args_size ) != UNSPEC ) return false ; gcc_assert ( XINT ( args_size , 1 ) == UNSPEC_CALL_ATTR ) ; symbol = XVECEXP ( args_size , 0 , 1 ) ; gcc_assert ( GET_CODE ( symbol ) == SYMBOL_REF ) ; operands [ args_size_opno ] = symbol ; return true ; } </s>

OPERANDS [ ARGS_SIZE_OPNO ] is the arg_size operand of a CALL expression . See if instead of the arg_size argument it contains the call attributes . If yes return true along with setting OPERANDS [ ARGS_SIZE_OPNO ] to the function symbol from the call attributes . Also return false if ARGS_SIZE_OPNO is -1 .


<s> bool SNESRelaxMem :: runOnMachineFunction ( MachineFunction & MF ) { bool Modified = false ; const SNESSubtarget & STI = MF . getSubtarget < SNESSubtarget > ( ) ; TII = STI . getInstrInfo ( ) ; for ( Block & MBB : MF ) { bool BlockModified = runOnBasicBlock ( MBB ) ; Modified |= BlockModified ; } return Modified ; } </s>


<s> bool SPUTargetMachine :: addInstSelector ( PassManagerBase & PM , bool Fast ) { PM . add ( createSPUISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static SDNode * getInt64 ( SelectionDAG * CurDAG , SDLoc dl , int64_t Imm ) { unsigned Count = getInt64CountDirect ( Imm ) ; if ( Count == 1 ) return getInt64Direct ( CurDAG , dl , Imm ) ; unsigned RMin = 0 ; int64_t MatImm ; unsigned MaskEnd ; for ( unsigned r = 1 ; r < 63 ; ++ r ) { uint64_t RImm = Rot64 ( Imm , r ) ; unsigned RCount = getInt64CountDirect ( RImm ) + 1 ; if ( RCount < Count ) { Count = RCount ; RMin = r ; MatImm = RImm ; MaskEnd = 63 ; } unsigned LS = findLastSet ( RImm ) ; if ( LS != r - 1 ) continue ; uint64_t OnesMask = - ( int64_t ) ( UINT64_C ( 1 ) << ( LS + 1 ) ) ; uint64_t RImmWithOnes = RImm | OnesMask ; RCount = getInt64CountDirect ( RImmWithOnes ) + 1 ; if ( RCount < Count ) { Count = RCount ; RMin = r ; MatImm = RImmWithOnes ; MaskEnd = LS ; } } if ( ! RMin ) return getInt64Direct ( CurDAG , dl , Imm ) ; auto getI32Imm = [ CurDAG , dl ] ( unsigned Imm ) { return CurDAG -> getTargetConstant ( Imm , dl , MVT :: i32 ) ; } ; SDValue Val = SDValue ( getInt64Direct ( CurDAG , dl , MatImm ) , 0 ) ; return CurDAG -> getMachineNode ( PPC :: RLDICR , dl , MVT :: i64 , Val , getI32Imm ( 64 - RMin ) , getI32Imm ( MaskEnd ) ) ; } </s>


<s> bool aarch64_expand_sve_vec_cmp_float ( rtx target , rtx_code code , rtx op0 , rtx op1 , bool can_invert_p ) { machine_mode pred_mode = GET_MODE ( target ) ; machine_mode data_mode = GET_MODE ( op0 ) ; rtx ptrue = force_reg ( pred_mode , CONSTM1_RTX ( pred_mode ) ) ; switch ( code ) { case UNORDERED : op1 = force_reg ( data_mode , op1 ) ; aarch64_emit_unspec_cond ( target , code , pred_mode , ptrue , op0 , op1 ) ; return false ; case LT : case LE : case GT : case GE : case EQ : case NE : aarch64_emit_unspec_cond ( target , code , pred_mode , ptrue , op0 , op1 ) ; return false ; case ORDERED : op1 = force_reg ( data_mode , op1 ) ; aarch64_emit_inverted_unspec_cond ( target , UNORDERED , pred_mode , ptrue , ptrue , op0 , op1 , can_invert_p ) ; return can_invert_p ; case LTGT : aarch64_emit_unspec_cond_or ( target , LT , GT , pred_mode , ptrue , op0 , op1 ) ; return false ; case UNEQ : if ( ! flag_trapping_math ) { op1 = force_reg ( data_mode , op1 ) ; aarch64_emit_unspec_cond_or ( target , UNORDERED , EQ , pred_mode , ptrue , op0 , op1 ) ; return false ; } case UNLT : case UNLE : case UNGT : case UNGE : { rtx ordered = ptrue ; if ( flag_trapping_math ) { ordered = gen_reg_rtx ( pred_mode ) ; op1 = force_reg ( data_mode , op1 ) ; aarch64_emit_inverted_unspec_cond ( ordered , UNORDERED , pred_mode , ptrue , ptrue , op0 , op1 , false ) ; } if ( code == UNEQ ) code = NE ; else code = reverse_condition_maybe_unordered ( code ) ; aarch64_emit_inverted_unspec_cond ( target , code , pred_mode , ptrue , ordered , op0 , op1 , can_invert_p ) ; return can_invert_p ; } default : gcc_unreachable ( ) ; } } </s>

Expand an SVE floating-point comparison : TARGET = CODE ( OP0 , OP1 ) If CAN_INVERT_P is true , the caller can also handle inverted results ; return true if the result is in fact inverted .


<s> unsigned MipsTargetLowering :: getJumpTableEncoding ( ) const { if ( Subtarget . isABI_N64 ( ) ) return MachineJumpTableInfo :: EK_GPRel64BlockAddress ; return TargetLowering :: getJumpTableEncoding ( ) ; } </s>

Return the entry encoding for a jump table in the current function .


Emit code to initialize OpenACC worker broadcast and synchronization registers .


<s>
unsigned
PPCTTI
::
getArithmeticInstrCost
(
unsigned
Opcode
,
Type
*
Ty
,
OperandValueKind
Op1Info
,
OperandValueKind
Op2Info
,
OperandValueProperties
Opd1PropInfo
,
OperandValueProperties
Opd2PropInfo
)
const
{
assert
(
TLI
->
InstructionOpcodeToISD
(
Opcode
)
&&
"Invalid opcode"
)
;
return
TargetTransformInfo
::
getArithmeticInstrCost
(
Opcode
,
Ty
,
Op1Info
,
Op2Info
,
Opd1PropInfo
,
Opd2PropInfo
)
;
}
</s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> static int loongarch_multipass_dfa_lookahead ( void ) { if ( ( unsigned long ) LARCH_ACTUAL_TUNE < N_ARCH_TYPES ) return loongarch_cpu_multipass_dfa_lookahead [ LARCH_ACTUAL_TUNE ] ; else return 0 ; } </s>


<s> bool SIFoldOperands :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; MRI = & MF . getRegInfo ( ) ; ST = & MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST -> getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; bool IsIEEEMode = MFI -> getMode ( ) . IEEE ; bool HasNSZ = MFI -> hasNoSignedZerosFPMath ( ) ; for ( MachineBasicBlock * MBB : depth_first ( & MF ) ) { MachineBasicBlock :: iterator I , Next ; MachineOperand * CurrentKnownM0Val = nullptr ; for ( I = MBB -> begin ( ) ; I != MBB -> end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; tryFoldInst ( TII , & MI ) ; if ( ! TII -> isFoldableCopy ( MI ) ) { if ( IsIEEEMode || ( ! HasNSZ && ! MI . getFlag ( MachineInstr :: FmNsz ) ) || ! tryFoldOMod ( MI ) ) tryFoldClamp ( MI ) ; if ( CurrentKnownM0Val && MI . modifiesRegister ( AMDGPU :: M0 , TRI ) ) CurrentKnownM0Val = nullptr ; continue ; } if ( MI . getOperand ( 0 ) . getReg ( ) == AMDGPU :: M0 ) { MachineOperand & NewM0Val = MI . getOperand ( 1 ) ; if ( CurrentKnownM0Val && CurrentKnownM0Val -> isIdenticalTo ( NewM0Val ) ) { MI . eraseFromParent ( ) ; continue ; } CurrentKnownM0Val = ( NewM0Val . isReg ( ) && NewM0Val . getReg ( ) . isPhysical ( ) ) ? nullptr : & NewM0Val ; continue ; } MachineOperand & OpToFold = MI . getOperand ( 1 ) ; bool FoldingImm = OpToFold . isImm ( ) || OpToFold . isFI ( ) || OpToFold . isGlobal ( ) ; if ( ! FoldingImm && ! OpToFold . isReg ( ) ) continue ; if ( OpToFold . isReg ( ) && ! Register :: isVirtualRegister ( OpToFold . getReg ( ) ) ) continue ; MachineOperand & Dst = MI . getOperand ( 0 ) ; if ( Dst . isReg ( ) && ! Register :: isVirtualRegister ( Dst . getReg ( ) ) ) continue ; foldInstOperand ( MI , OpToFold ) ; } } return false ; } </s>


<s> rtx gen_split_move_double ( rtx operands [ ] ) { machine_mode mode = GET_MODE ( operands [ 0 ] ) ; rtx dest = operands [ 0 ] ; rtx src = operands [ 1 ] ; rtx val ; if ( GET_CODE ( dest ) == SUBREG ) alter_subreg ( & dest , true ) ; if ( GET_CODE ( src ) == SUBREG ) alter_subreg ( & src , true ) ; start_sequence ( ) ; if ( REG_P ( dest ) ) { int dregno = REGNO ( dest ) ; if ( REG_P ( src ) ) { int sregno = REGNO ( src ) ; int reverse = ( dregno == sregno + 1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operand_subword ( dest , reverse , TRUE , mode ) , operand_subword ( src , reverse , TRUE , mode ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operand_subword ( dest , ! reverse , TRUE , mode ) , operand_subword ( src , ! reverse , TRUE , mode ) ) ) ; } else if ( CONST_INT_P ( src ) || GET_CODE ( src ) == CONST_DOUBLE ) { rtx words [ 2 ] ; split_double ( src , & words [ 0 ] , & words [ 1 ] ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operand_subword ( dest , 0 , TRUE , mode ) , words [ 0 ] ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operand_subword ( dest , 1 , TRUE , mode ) , words [ 1 ] ) ) ; } else if ( MEM_P ( src ) ) { int reverse = refers_to_regno_p ( dregno , XEXP ( src , 0 ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operand_subword ( dest , reverse , TRUE , mode ) , adjust_address ( src , SImode , reverse * UNITS_PER_WORD ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operand_subword ( dest , ! reverse , TRUE , mode ) , adjust_address ( src , SImode , ! reverse * UNITS_PER_WORD ) ) ) ; } else gcc_unreachable ( ) ; } else if ( MEM_P ( dest ) && REG_P ( src ) ) { emit_insn ( gen_rtx_SET ( VOIDmode , adjust_address ( dest , SImode , 0 ) , operand_subword ( src , 0 , TRUE , mode ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , adjust_address ( dest , SImode , UNITS_PER_WORD ) , operand_subword ( src , 1 , TRUE , mode ) ) ) ; } else gcc_unreachable ( ) ; val = get_insns ( ) ; end_sequence ( ) ; return val ; } </s>

Split a 2 word move ( DI or DF ) into component parts .


<s> bool hasReservedCallFrame ( const MachineFunction & MF ) const override { return true ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> void mips_expand_conditional_branch ( rtx * operands ) { enum rtx_code code = GET_CODE ( operands [ 0 ] ) ; rtx op0 = operands [ 1 ] ; rtx op1 = operands [ 2 ] ; rtx condition ; mips_emit_compare ( & code , & op0 , & op1 , TARGET_MIPS16 ) ; condition = gen_rtx_fmt_ee ( code , VOIDmode , op0 , op1 ) ; emit_jump_insn ( gen_condjump ( condition , operands [ 3 ] ) ) ; } </s>

Compare OPERANDS [ 1 ] with OPERANDS [ 2 ] using comparison code CODE and jump to OPERANDS [ 3 ] if the condition holds .


<s> bool isToken ( ) const override { return Kind == k_Token ; } </s>


<s> bool RISCVTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , Align Alignment , MachineMemOperand :: Flags Flags , bool * Fast ) const { if ( ! VT . isScalableVector ( ) ) return false ; EVT ElemVT = VT . getVectorElementType ( ) ; if ( Alignment >= ElemVT . getStoreSize ( ) ) { if ( Fast ) * Fast = true ; return true ; } return false ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> bool RISCVTargetLowering :: isSExtCheaperThanZExt ( EVT SrcVT , EVT DstVT ) const { return Subtarget . is64Bit ( ) && SrcVT == MVT :: i32 && DstVT == MVT :: i64 ; } </s>

Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension .


<s> bool AArch64TargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { if ( ! CI -> isTailCall ( ) ) return false ; return true ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> unsigned SITargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( CC != CallingConv :: AMDGPU_KERNEL && VT . isVector ( ) && VT . getVectorNumElements ( ) == 3 ) { EVT ScalarVT = VT . getScalarType ( ) ; if ( ScalarVT . getSizeInBits ( ) == 32 ) return 3 ; } return TargetLowering :: getNumRegistersForCallingConv ( Context , CC , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s>
Register
SystemZTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
LLT
VT
,
const
MachineFunction
&
MF
)
const
{
Register
Reg
=
StringSwitch
<
Register
>
(
RegName
)
.
Case
(
"r15"
,
SystemZ
::
R15D
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> unsigned AMDGPUSubtarget :: getMaxWorkitemID ( const Function & Kernel , unsigned Dimension ) const { unsigned ReqdSize = getReqdWorkGroupSize ( Kernel , Dimension ) ; if ( ReqdSize != std :: numeric_limits < unsigned > :: max ( ) ) return ReqdSize - 1 ; return getFlatWorkGroupSizes ( Kernel ) . second - 1 ; } </s>

Return the maximum workitem ID value in the function , for the given ( 0 , 1 , 2 ) dimension .


<s> bool AArch64TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( AM . BaseGV ) return false ; if ( AM . HasBaseReg && AM . BaseOffs && AM . Scale ) return false ; if ( isa < ScalableVectorType > ( Ty ) ) return AM . HasBaseReg && ! AM . BaseOffs && ! AM . Scale ; uint64_t NumBytes = 0 ; if ( Ty -> isSized ( ) ) { uint64_t NumBits = DL . getTypeSizeInBits ( Ty ) ; NumBytes = NumBits / 8 ; if ( ! isPowerOf2_64 ( NumBits ) ) NumBytes = 0 ; } if ( ! AM . Scale ) { int64_t Offset = AM . BaseOffs ; if ( isInt < 9 > ( Offset ) ) return true ; unsigned shift = Log2_64 ( NumBytes ) ; if ( NumBytes && Offset > 0 && ( Offset / NumBytes ) <= ( 1LL << 12 ) - 1 && ( Offset >> shift ) << shift == Offset ) return true ; return false ; } return AM . Scale == 1 || ( AM . Scale > 0 && ( uint64_t ) AM . Scale == NumBytes ) ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s>
static
const
char
*
write_fn_proto
(
std
::
stringstream
&
s
,
bool
is_defn
,
const
char
*
name
,
const_tree
decl
)
{
if
(
is_defn
)
name
=
write_fn_proto
(
s
,
false
,
name
,
decl
)
;
else
{
name
=
nvptx_name_replacement
(
name
)
;
if
(
name
[
0
]
==
'*'
)
name
++
;
}
write_fn_marker
(
s
,
is_defn
,
TREE_PUBLIC
(
decl
)
,
name
)
;
if
(
DECL_EXTERNAL
(
decl
)
)
s
<<
".extern "
;
else
if
(
TREE_PUBLIC
(
decl
)
)
s
<<
(
DECL_WEAK
(
decl
)
".weak "
:
".visible "
)
;
s
<<
(
write_as_kernel
(
DECL_ATTRIBUTES
(
decl
)
)
".entry "
:
".func "
)
;
tree
fntype
=
TREE_TYPE
(
decl
)
;
tree
result_type
=
TREE_TYPE
(
fntype
)
;
bool
return_in_mem
=
write_return_type
(
s
,
true
,
result_type
)
;
s
<<
name
;
int
argno
=
0
;
if
(
return_in_mem
)
argno
=
write_arg_type
(
s
,
1
,
argno
,
ptr_type_node
,
true
)
;
tree
args
=
TYPE_ARG_TYPES
(
fntype
)
;
bool
prototyped
=
true
;
if
(
!
args
)
{
args
=
DECL_ARGUMENTS
(
decl
)
;
prototyped
=
false
;
}
for
(
;
args
;
args
=
TREE_CHAIN
(
args
)
)
{
tree
type
=
prototyped
TREE_VALUE
(
args
)
:
TREE_TYPE
(
args
)
;
argno
=
write_arg_type
(
s
,
1
,
argno
,
type
,
prototyped
)
;
}
if
(
stdarg_p
(
fntype
)
)
argno
=
write_arg_type
(
s
,
1
,
argno
,
ptr_type_node
,
true
)
;
if
(
DECL_STATIC_CHAIN
(
decl
)
)
argno
=
write_arg_type
(
s
,
1
,
argno
,
ptr_type_node
,
true
)
;
if
(
!
argno
&&
strcmp
(
name
,
"main"
)
==
0
)
{
argno
=
write_arg_type
(
s
,
1
,
argno
,
integer_type_node
,
true
)
;
argno
=
write_arg_type
(
s
,
1
,
argno
,
ptr_type_node
,
true
)
;
}
if
(
argno
)
s
<<
")"
;
s
<<
(
is_defn
"\n"
:
";\n"
)
;
return
name
;
}
</s>

Write a .func or .kernel declaration or definition along with a helper comment for use by ld . S is the stream to write to , DECL the decl for the function with name NAME . For definitions , emit a declaration too .


<s> std :: pair < unsigned , const TargetRegisterClass * > MBlazeTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , & MBlaze :: GPRRegClass ) ; case 'd' : case 'y' : case 'f' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , & MBlaze :: GPRRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> bool RISCVFrameLowering :: canUseAsPrologue ( const MachineBasicBlock & MBB ) const { MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ; const MachineFunction * MF = MBB . getParent ( ) ; const auto * RVFI = MF -> getInfo < RISCVMachineFunctionInfo > ( ) ; if ( ! RVFI -> useSaveRestoreLibCalls ( * MF ) ) return true ; RegScavenger RS ; RS . enterBasicBlock ( * TmpMBB ) ; return ! RS . isRegUsed ( RISCV :: X5 ) ; } </s>

Check whether or not the given MBB can be used as a prologue for the target .


<s> static rtx aarch64_expand_sve_const_pred_1 ( rtx target , rtx_vector_builder & builder , bool allow_recurse_p ) { if ( builder . encoded_nelts ( ) == 1 ) return aarch64_emit_set_immediate ( target , builder ) ; unsigned int elt_size = aarch64_widest_sve_pred_elt_size ( builder ) ; if ( int vl = aarch64_partial_ptrue_length ( builder , elt_size ) ) { machine_mode mode = aarch64_sve_pred_mode ( elt_size ) . require ( ) ; if ( aarch64_svpattern_for_vl ( mode , vl ) != AARCH64_NUM_SVPATTERNS ) return aarch64_emit_set_immediate ( target , builder ) ; return aarch64_sve_move_pred_via_while ( target , mode , vl ) ; } if ( ! allow_recurse_p ) return NULL_RTX ; if ( INTVAL ( builder . elt ( 0 ) ) == 0 ) if ( rtx res = aarch64_expand_sve_const_pred_eor ( target , builder , elt_size ) ) return res ; for ( unsigned int i = elt_size ; i <= 8 ; i *= 2 ) if ( rtx res = aarch64_expand_sve_const_pred_trn ( target , builder , elt_size , i ) ) return res ; return NULL_RTX ; } </s>

Subroutine of aarch64_expand_sve_const_pred . Try to load the VNx16BI constant in BUILDER into an SVE predicate register . Return the register on success , otherwise return null . Use TARGET for the register if nonnull and convenient . ALLOW_RECURSE_P is true if we can use methods that would call this function recursively .


<s> bool BlackfinTargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createBlackfinISelDag ( * this , OptLevel ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool X86TargetLowering :: hasAndNot ( SDValue Y ) const { EVT VT = Y . getValueType ( ) ; if ( ! VT . isVector ( ) ) return ! isa < ConstantSDNode > ( Y ) && hasAndNotCompare ( Y ) ; if ( ! Subtarget . hasSSE1 ( ) || VT . getSizeInBits ( ) < 128 ) return false ; if ( VT == MVT :: v4i32 ) return true ; return Subtarget . hasSSE2 ( ) ; } </s>

Return true if the target has a bitwise and-not operation : X = ~A & B This can be used to simplify select or other instructions .


<s> bool SPUPassConfig :: addPreEmitPass ( ) { typedef llvm :: FunctionPass * ( * BuilderFunc ) ( const char * ) ; BuilderFunc schedulerCreator = ( BuilderFunc ) ( intptr_t ) sys :: DynamicLibrary :: SearchForAddressOfSymbol ( "createTCESchedulerPass" ) ; if ( schedulerCreator != NULL ) PM -> add ( schedulerCreator ( "cellspu" ) ) ; PM -> add ( createSPUNopFillerPass ( getSPUTargetMachine ( ) ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

CellSPU SPU "createTCESchedulerPass" "cellspu" SPU SPU


<s> void R600InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { unsigned VectorComponents = 0 ; if ( ( AMDGPU :: R600_Reg128RegClass . contains ( DestReg ) || AMDGPU :: R600_Reg128VerticalRegClass . contains ( DestReg ) ) && ( AMDGPU :: R600_Reg128RegClass . contains ( SrcReg ) || AMDGPU :: R600_Reg128VerticalRegClass . contains ( SrcReg ) ) ) { VectorComponents = 4 ; } else if ( ( AMDGPU :: R600_Reg64RegClass . contains ( DestReg ) || AMDGPU :: R600_Reg64VerticalRegClass . contains ( DestReg ) ) && ( AMDGPU :: R600_Reg64RegClass . contains ( SrcReg ) || AMDGPU :: R600_Reg64VerticalRegClass . contains ( SrcReg ) ) ) { VectorComponents = 2 ; } if ( VectorComponents > 0 ) { for ( unsigned I = 0 ; I < VectorComponents ; I ++ ) { unsigned SubRegIndex = RI . getSubRegFromChannel ( I ) ; buildDefaultInstruction ( MBB , MI , AMDGPU :: MOV , RI . getSubReg ( DestReg , SubRegIndex ) , RI . getSubReg ( SrcReg , SubRegIndex ) ) . addReg ( DestReg , RegState :: Define | RegState :: Implicit ) ; } } else { MachineInstr * NewMI = buildDefaultInstruction ( MBB , MI , AMDGPU :: MOV , DestReg , SrcReg ) ; NewMI -> getOperand ( getOperandIdx ( * NewMI , AMDGPU :: OpName :: src0 ) ) . setIsKill ( KillSrc ) ; } } </s>


<s> void Cpu0PassConfig :: addPreEmitPass ( ) { Cpu0TargetMachine & TM = getCpu0TargetMachine ( ) ; addPass ( createCpu0LongBranchPass ( TM ) ) ; return ; } </s>


<s> static bool frv_issues_to_branch_unit_p ( rtx_insn * insn ) { return frv_unit_groups [ frv_insn_unit ( insn ) ] == GROUP_B ; } </s>

Return true if INSN issues to a branch unit .


<s> rtx frv_split_scc ( rtx dest , rtx test , rtx cc_reg , rtx cr_reg , HOST_WIDE_INT value ) { rtx ret ; start_sequence ( ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cr_reg , gen_rtx_fmt_ee ( GET_CODE ( test ) , GET_MODE ( cr_reg ) , cc_reg , const0_rtx ) ) ) ; emit_move_insn ( dest , GEN_INT ( value ) ) ; emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_EQ ( GET_MODE ( cr_reg ) , cr_reg , const0_rtx ) , gen_rtx_SET ( VOIDmode , dest , const0_rtx ) ) ) ; ret = get_insns ( ) ; end_sequence ( ) ; return ret ; } </s>

Split a SCC instruction into component parts , returning a SEQUENCE to hold the separate insns .


<s> static rtx s390_emit_compare_and_swap ( enum rtx_code code , rtx old , rtx mem , rtx cmp , rtx new_rtx , machine_mode ccmode ) { rtx cc ; mem = s390_legitimize_cs_operand ( mem ) ; cc = gen_rtx_REG ( ccmode , CC_REGNUM ) ; switch ( GET_MODE ( mem ) ) { case E_SImode : emit_insn ( gen_atomic_compare_and_swapsi_internal ( old , mem , cmp , new_rtx , cc ) ) ; break ; case E_DImode : emit_insn ( gen_atomic_compare_and_swapdi_internal ( old , mem , cmp , new_rtx , cc ) ) ; break ; case E_TImode : emit_insn ( gen_atomic_compare_and_swapti_internal ( old , mem , cmp , new_rtx , cc ) ) ; break ; case E_QImode : case E_HImode : default : gcc_unreachable ( ) ; } return s390_emit_compare ( code , cc , const0_rtx ) ; } </s>

Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD matches CMP . Return the correct condition RTL to be placed in the IF_THEN_ELSE of the conditional branch testing the result .


Choose the order in which to allocate hard registers for pseudo-registers local to a basic block . Store the desired register order in the array ` reg_alloc_order ' . Element 0 should be the register to allocate first ; element 1 , the next register ; and so on .


<s>
MCSection
*
HexagonTargetObjectFile
::
getExplicitSectionGlobal
(
const
GlobalObject
*
GO
,
SectionKind
Kind
,
const
TargetMachine
&
TM
)
const
{
TRACE
(
"[getExplicitSectionGlobal] GO("
<<
GO
->
getName
(
)
<<
") from("
<<
GO
->
getSection
(
)
<<
") "
)
;
TRACE
(
(
GO
->
hasPrivateLinkage
(
)
"private_linkage "
:
""
)
<<
(
GO
->
hasLocalLinkage
(
)
"local_linkage "
:
""
)
<<
(
GO
->
hasInternalLinkage
(
)
"internal "
:
""
)
<<
(
GO
->
hasExternalLinkage
(
)
"external "
:
""
)
<<
(
GO
->
hasCommonLinkage
(
)
"common_linkage "
:
""
)
<<
(
GO
->
hasCommonLinkage
(
)
"common "
:
""
)
<<
(
Kind
.
isCommon
(
)
"kind_common "
:
""
)
<<
(
Kind
.
isBSS
(
)
"kind_bss "
:
""
)
<<
(
Kind
.
isBSSLocal
(
)
"kind_bss_local "
:
""
)
)
;
if
(
GO
->
hasSection
(
)
)
{
StringRef
Section
=
GO
->
getSection
(
)
;
if
(
Section
.
contains
(
".access.text.group"
)
)
return
getContext
(
)
.
getELFSection
(
GO
->
getSection
(
)
,
ELF
::
SHT_PROGBITS
,
ELF
::
SHF_ALLOC
|
ELF
::
SHF_EXECINSTR
)
;
if
(
Section
.
contains
(
".access.data.group"
)
)
return
getContext
(
)
.
getELFSection
(
GO
->
getSection
(
)
,
ELF
::
SHT_PROGBITS
,
ELF
::
SHF_WRITE
|
ELF
::
SHF_ALLOC
)
;
}
if
(
isGlobalInSmallSection
(
GO
,
TM
)
)
return
selectSmallSectionForGlobal
(
GO
,
Kind
,
TM
)
;
TRACE
(
"default_ELF_section\n"
)
;
return
TargetLoweringObjectFileELF
::
getExplicitSectionGlobal
(
GO
,
Kind
,
TM
)
;
}
</s>

Targets should implement this method to assign a section to globals with an explicit section specfied .

Hexagon
Hexagon
"[getExplicitSectionGlobal] GO("
") from("
") "
"private_linkage "
""
"local_linkage "
""
"internal "
""
"external "
""
"common_linkage "
""
"common "
""
"kind_common "
""
"kind_bss "
""
"kind_bss_local "
""
".access.text.group"
".access.data.group"
"default_ELF_section\n"


<s> virtual bool ShouldShrinkFPConstant ( EVT VT ) const { return ! X86ScalarSSEf64 || VT == MVT :: f80 ; } </s>

If true , then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime .


<s> static bool get_memref_parts ( rtx mem , rtx * base , HOST_WIDE_INT * offset , HOST_WIDE_INT * size ) { rtx addr_rtx ; if MEM_SIZE_KNOWN_P ( mem ) * size = MEM_SIZE ( mem ) ; else return false ; addr_rtx = ( XEXP ( mem , 0 ) ) ; if ( GET_CODE ( addr_rtx ) == PRE_MODIFY ) addr_rtx = XEXP ( addr_rtx , 1 ) ; * offset = 0 ; while ( GET_CODE ( addr_rtx ) == PLUS && CONST_INT_P ( XEXP ( addr_rtx , 1 ) ) ) { * offset += INTVAL ( XEXP ( addr_rtx , 1 ) ) ; addr_rtx = XEXP ( addr_rtx , 0 ) ; } if ( ! REG_P ( addr_rtx ) ) return false ; * base = addr_rtx ; return true ; } </s>

Try to determine base/offset/size parts of the given MEM . Return true if successful , false if all the values could n't be determined . This function only looks for REG or REG+CONST address forms . REG+REG address form will return false .


<s> int use_return_insn ( int iscond , rtx sibling ) { int regno ; unsigned int func_type ; unsigned long saved_int_regs ; unsigned HOST_WIDE_INT stack_adjust ; arm_stack_offsets * offsets ; if ( ! reload_completed ) return 0 ; func_type = arm_current_func_type ( ) ; if ( func_type & ( ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN ) ) return 0 ; if ( IS_INTERRUPT ( func_type ) && ( frame_pointer_needed || TARGET_THUMB ) ) return 0 ; if ( TARGET_LDRD && current_tune -> prefer_ldrd_strd && ! optimize_function_for_size_p ( cfun ) ) return 0 ; offsets = arm_get_frame_offsets ( ) ; stack_adjust = offsets -> outgoing_args - offsets -> saved_regs ; if ( crtl -> args . pretend_args_size || cfun -> machine -> uses_anonymous_args || crtl -> calls_eh_return || cfun -> calls_alloca || ! ( stack_adjust == 0 || ( TARGET_APCS_FRAME && frame_pointer_needed && stack_adjust == 4 ) ) || ( ! ( TARGET_APCS_FRAME && frame_pointer_needed ) && arm_compute_static_chain_stack_bytes ( ) != 0 ) ) return 0 ; saved_int_regs = offsets -> saved_regs_mask ; if ( stack_adjust == 4 && ! arm_arch5 && TARGET_ARM ) { if ( ! call_used_regs [ 3 ] ) return 0 ; if ( arm_size_return_regs ( ) >= ( 4 * UNITS_PER_WORD ) ) return 0 ; if ( sibling ) { gcc_assert ( CALL_P ( sibling ) ) ; if ( find_regno_fusage ( sibling , USE , 3 ) ) return 0 ; } if ( saved_int_regs & 0x7 ) return 0 ; } if ( TARGET_INTERWORK && saved_int_regs != 0 && ! IS_INTERRUPT ( func_type ) ) return 0 ; if ( iscond && arm_tune_strongarm ) { if ( saved_int_regs != 0 && saved_int_regs != ( 1 << LR_REGNUM ) ) return 0 ; if ( flag_pic && arm_pic_register != INVALID_REGNUM && df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) ) return 0 ; } if ( saved_int_regs && IS_CMSE_ENTRY ( func_type ) ) return 0 ; if ( saved_int_regs && ! ( saved_int_regs & ( 1 << LR_REGNUM ) ) ) return 0 ; if ( TARGET_HARD_FLOAT ) for ( regno = FIRST_VFP_REGNUM ; regno <= LAST_VFP_REGNUM ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) return 0 ; if ( TARGET_REALLY_IWMMXT ) for ( regno = FIRST_IWMMXT_REGNUM ; regno <= LAST_IWMMXT_REGNUM ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) return 0 ; return 1 ; } </s>

Return true if this function 's epilogue can be output as RTL .