<s>
bool
X86AsmParser
::
processInstruction
(
MCInst
&
Inst
,
const
OperandVector
&
Ops
)
{
const
MCRegisterInfo
*
MRI
=
getContext
(
)
.
getRegisterInfo
(
)
;
switch
(
Inst
.
getOpcode
(
)
)
{
default
:
return
false
;
case
X86
::
VMOVZPQILo2PQIrr
:
case
X86
::
VMOVAPDrr
:
case
X86
::
VMOVAPDYrr
:
case
X86
::
VMOVAPSrr
:
case
X86
::
VMOVAPSYrr
:
case
X86
::
VMOVDQArr
:
case
X86
::
VMOVDQAYrr
:
case
X86
::
VMOVDQUrr
:
case
X86
::
VMOVDQUYrr
:
case
X86
::
VMOVUPDrr
:
case
X86
::
VMOVUPDYrr
:
case
X86
::
VMOVUPSrr
:
case
X86
::
VMOVUPSYrr
:
{
if
(
ForcedVEXEncoding
==
VEXEncoding_VEX3
||
MRI
->
getEncodingValue
(
Inst
.
getOperand
(
0
)
.
getReg
(
)
)
>=
8
||
MRI
->
getEncodingValue
(
Inst
.
getOperand
(
1
)
.
getReg
(
)
)
<
8
)
return
false
;
unsigned
NewOpc
;
switch
(
Inst
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Invalid opcode"
)
;
case
X86
::
VMOVZPQILo2PQIrr
:
NewOpc
=
X86
::
VMOVPQI2QIrr
;
break
;
case
X86
::
VMOVAPDrr
:
NewOpc
=
X86
::
VMOVAPDrr_REV
;
break
;
case
X86
::
VMOVAPDYrr
:
NewOpc
=
X86
::
VMOVAPDYrr_REV
;
break
;
case
X86
::
VMOVAPSrr
:
NewOpc
=
X86
::
VMOVAPSrr_REV
;
break
;
case
X86
::
VMOVAPSYrr
:
NewOpc
=
X86
::
VMOVAPSYrr_REV
;
break
;
case
X86
::
VMOVDQArr
:
NewOpc
=
X86
::
VMOVDQArr_REV
;
break
;
case
X86
::
VMOVDQAYrr
:
NewOpc
=
X86
::
VMOVDQAYrr_REV
;
break
;
case
X86
::
VMOVDQUrr
:
NewOpc
=
X86
::
VMOVDQUrr_REV
;
break
;
case
X86
::
VMOVDQUYrr
:
NewOpc
=
X86
::
VMOVDQUYrr_REV
;
break
;
case
X86
::
VMOVUPDrr
:
NewOpc
=
X86
::
VMOVUPDrr_REV
;
break
;
case
X86
::
VMOVUPDYrr
:
NewOpc
=
X86
::
VMOVUPDYrr_REV
;
break
;
case
X86
::
VMOVUPSrr
:
NewOpc
=
X86
::
VMOVUPSrr_REV
;
break
;
case
X86
::
VMOVUPSYrr
:
NewOpc
=
X86
::
VMOVUPSYrr_REV
;
break
;
}
Inst
.
setOpcode
(
NewOpc
)
;
return
true
;
}
case
X86
::
VMOVSDrr
:
case
X86
::
VMOVSSrr
:
{
if
(
ForcedVEXEncoding
==
VEXEncoding_VEX3
||
MRI
->
getEncodingValue
(
Inst
.
getOperand
(
0
)
.
getReg
(
)
)
>=
8
||
MRI
->
getEncodingValue
(
Inst
.
getOperand
(
2
)
.
getReg
(
)
)
<
8
)
return
false
;
unsigned
NewOpc
;
switch
(
Inst
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Invalid opcode"
)
;
case
X86
::
VMOVSDrr
:
NewOpc
=
X86
::
VMOVSDrr_REV
;
break
;
case
X86
::
VMOVSSrr
:
NewOpc
=
X86
::
VMOVSSrr_REV
;
break
;
}
Inst
.
setOpcode
(
NewOpc
)
;
return
true
;
}
}
}
</s>

Process a single instruction and collect debug info anchors .


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == & ARM :: GPRRegClass || RC == & ARM :: tGPRRegClass || RC == & ARM :: tcGPRRegClass || RC == & ARM :: rGPRRegClass || RC == & ARM :: GPRnopcRegClass ) { BuildMI ( MBB , I , DL , get ( ARM :: t2LDRi12 ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; return ; } if ( ARM :: GPRPairRegClass . hasSubClassEq ( RC ) ) { if ( TargetRegisterInfo :: isVirtualRegister ( DestReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( DestReg , & ARM :: GPRPair_with_gsub_1_in_rGPRRegClass ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( ARM :: t2LDRDi8 ) ) ; AddDReg ( MIB , DestReg , ARM :: gsub_0 , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , ARM :: gsub_1 , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; } ARMBaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC , TRI ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> void CompositeHandler :: visitCallInst ( CallInst & I ) { for ( Value * Arg : I . arg_operands ( ) ) { visitValue ( Arg , Arg -> getType ( ) ) ; } } </s>


<s> tree arm_valid_target_attribute_tree ( tree args , struct gcc_options * opts , struct gcc_options * opts_set ) { if ( ! arm_valid_target_attribute_rec ( args , opts ) ) return NULL_TREE ; arm_option_override_internal ( opts , opts_set ) ; return build_target_option_node ( opts ) ; } </s>

Return a TARGET_OPTION_NODE tree of the target options listed or NULL .


<s> void TPCPassConfig :: addPreRegAlloc ( ) { addPass ( createTPCScalarSink ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addBlockPlacement ( ) ; if ( getOptLevel ( ) >= CodeGenOpt :: Default ) { addPass ( createTPCImmToReg ( ) ) ; addPass ( createTPCAddrOpt ( ) ) ; addPass ( createTPCRegisterBalancer ( ) ) ; addPass ( & DeadMachineInstructionElimID ) ; addPass ( createTPCHardwareLoops ( ) , false ) ; addPass ( createTPCPipeliner ( ) , false ) ; addPass ( & DeadMachineInstructionElimID ) ; addPass ( createTPCSubregInitElimination ( ) ) ; } if ( getOptLevel ( ) == CodeGenOpt :: None ) addPass ( createTPCHWWAGeneral ( ) ) ; addPass ( createTPCHWWA2 ( ) ) ; addPass ( createTPCPreRAHwWorkarounds ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .

TPC TPC TPC TPC TPC TPC TPC TPC TPC TPC TPC TPC


<s> static const char * pru_comparison_str ( enum rtx_code cond ) { switch ( cond ) { case NE : return "ne" ; case EQ : return "eq" ; case GEU : return "ge" ; case GTU : return "gt" ; case LEU : return "le" ; case LTU : return "lt" ; default : gcc_unreachable ( ) ; } } </s>

Map rtx_code to unsigned PRU branch op suffix . Callers must handle sign comparison themselves for signed operations .


<s> MachineInstr * AMDGPUInstrInfo :: convertToThreeAddress ( MachineFunction :: iterator & MFI , MachineBasicBlock :: iterator & MBBI , LiveVariables * LV ) const { return NULL ; } </s>

convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag .


<s> void AMDGPUDAGToDAGISel :: PreprocessISelDAG ( ) { MachineFrameInfo * MFI = CurDAG -> getMachineFunction ( ) . getFrameInfo ( ) ; for ( int I = MFI -> getObjectIndexBegin ( ) , E = MFI -> getObjectIndexEnd ( ) ; I != E ; ++ I ) { SDValue FI = CurDAG -> getTargetFrameIndex ( I , MVT :: i32 ) ; if ( FI . use_empty ( ) ) continue ; SDValue EffectiveFI = FI ; auto It = FI -> use_begin ( ) ; if ( It -> getOpcode ( ) == ISD :: AssertZext && FI -> hasOneUse ( ) ) { EffectiveFI = SDValue ( * It , 0 ) ; It = EffectiveFI -> use_begin ( ) ; } for ( auto It = EffectiveFI -> use_begin ( ) ; ! It . atEnd ( ) ; ) { SDUse & Use = It . getUse ( ) ; SDNode * User = Use . getUser ( ) ; unsigned OpIdx = It . getOperandNo ( ) ; ++ It ; if ( MemSDNode * M = dyn_cast < MemSDNode > ( User ) ) { unsigned PtrIdx = M -> getOpcode ( ) == ISD :: STORE ? 2 : 1 ; if ( OpIdx == PtrIdx ) continue ; unsigned OpN = M -> getNumOperands ( ) ; SDValue NewOps [ 8 ] ; assert ( OpN < array_lengthof ( NewOps ) ) ; for ( unsigned Op = 0 ; Op != OpN ; ++ Op ) { if ( Op != OpIdx ) { NewOps [ Op ] = M -> getOperand ( Op ) ; continue ; } MachineSDNode * Mov = CurDAG -> getMachineNode ( AMDGPU :: V_MOV_B32_e32 , SDLoc ( M ) , MVT :: i32 , FI ) ; NewOps [ Op ] = SDValue ( Mov , 0 ) ; } CurDAG -> UpdateNodeOperands ( M , makeArrayRef ( NewOps , OpN ) ) ; } } } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> static bool mips_load_call_address ( enum mips_call_type type , rtx dest , rtx addr ) { if ( TARGET_EXPLICIT_RELOCS && ! ( type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP ) && mips_ok_for_lazy_binding_p ( addr ) ) { addr = mips_got_load ( dest , addr , SYMBOL_GOTOFF_CALL ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , addr ) ) ; return true ; } else { mips_emit_move ( dest , addr ) ; return false ; } } </s>

Load function address ADDR into register DEST . SIBCALL_P is true if the address is needed for a sibling call .


<s> MCGNodes & getNodes ( ) { return MCG . getNodes ( ) ; } </s>

Get the list of nodes in this pi-block .


<s> bool rvexTargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const rvexSubtarget & Subtarget = TM . getSubtarget < rvexSubtarget > ( ) ; if ( Subtarget . isLinux ( ) ) return false ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ; if ( Kind . isMergeable1ByteCString ( ) ) return false ; Type * Ty = GV -> getType ( ) -> getElementType ( ) ; return IsInSmallSection ( TM . getDataLayout ( ) -> getTypeAllocSize ( Ty ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


"Instruction should be in a basic block!"

"Generic instruction has unexpected implicit operands\n"

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s> RISCVProcFamilyEnum getProcFamily ( ) const { return RISCVProcFamily ; } </s>


Implement TARGET_MAX_NOCE_IFCVT_SEQ_COST . Like the default implementation , but returns a lower bound .


<s> InstructionCost getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: TargetCostKind CostKind , TTI :: OperandValueKind Opd1Info = TTI :: OK_AnyValue , TTI :: OperandValueKind Opd2Info = TTI :: OK_AnyValue , TTI :: OperandValueProperties Opd1PropInfo = TTI :: OP_None , TTI :: OperandValueProperties Opd2PropInfo = TTI :: OP_None , ArrayRef < const Value * > Args = ArrayRef < const Value * > ( ) , const Instruction * CxtI = nullptr ) { int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( ISD == ISD :: ADD && CostKind == TTI :: TCK_RecipThroughput ) return SCEVCheapExpansionBudget . getValue ( ) + 1 ; return BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; } </s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> bool X86PassConfig :: addPreEmitPass ( ) { bool ShouldPrint = false ; if ( getOptLevel ( ) != CodeGenOpt :: None && getX86Subtarget ( ) . hasSSE2 ( ) ) { addPass ( createExecutionDependencyFixPass ( & X86 :: VR128RegClass ) ) ; ShouldPrint = true ; } if ( UseVZeroUpper ) { addPass ( createX86IssueVZeroUpperPass ( ) ) ; ShouldPrint = true ; } if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86PadShortFunctions ( ) ) ; addPass ( createX86FixupLEAs ( ) ) ; ShouldPrint = true ; } if ( getX86Subtarget ( ) . isTargetNaCl ( ) ) { addPass ( createX86NaClRewritePass ( ) ) ; ShouldPrint = true ; } return ShouldPrint ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


Return the alignment for LABEL . We default to the -falign-labels value except for the literal pool base label .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Hexagon optimize vextract"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static reg_class_t loongarch_preferred_reload_class ( rtx x , reg_class_t rclass ) { if ( reg_class_subset_p ( FP_REGS , rclass ) && loongarch_mode_ok_for_mov_fmt_p ( GET_MODE ( x ) ) ) return FP_REGS ; if ( reg_class_subset_p ( GR_REGS , rclass ) ) rclass = GR_REGS ; return rclass ; } </s>


<s> int visium_expand_block_set ( rtx * operands ) { rtx dst = operands [ 0 ] ; rtx bytes_rtx = operands [ 1 ] ; rtx value_rtx = operands [ 2 ] ; rtx align_rtx = operands [ 3 ] ; const int align = INTVAL ( align_rtx ) ; rtx dst_reg ; tree dst_expr ; if ( ! CONST_INT_P ( bytes_rtx ) || INTVAL ( bytes_rtx ) <= 0 ) return 0 ; dst_reg = copy_addr_to_reg ( XEXP ( dst , 0 ) ) ; if ( align >= 4 ) expand_block_set_4 ( dst , dst_reg , value_rtx , bytes_rtx ) ; else if ( align >= 2 ) expand_block_set_2 ( dst , dst_reg , value_rtx , bytes_rtx ) ; else expand_block_set_1 ( dst_reg , value_rtx , bytes_rtx ) ; dst_expr = MEM_EXPR ( dst ) ; if ( dst_expr ) mark_addressable ( dst_expr ) ; return 1 ; } </s>

Expand string/block set operations . operands [ 0 ] is the pointer to the destination . operands [ 1 ] is the number of bytes to set . operands [ 2 ] is the source value . operands [ 3 ] is the alignment . Return 1 upon success , 0 otherwise .


<s> void X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const X86Subtarget & STI = MF . getSubtarget < X86Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; const X86RegisterInfo & RegInfo = * STI . getRegisterInfo ( ) ; unsigned StackPtr = RegInfo . getStackRegister ( ) ; bool reserveCallFrame = hasReservedCallFrame ( MF ) ; int Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; bool IsLP64 = STI . isTarget64BitLP64 ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t InternalAmt = ( isDestroy || Amount ) ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { if ( Amount == 0 ) return ; unsigned StackAlign = getStackAlignment ( ) ; Amount = RoundUpToAlignment ( Amount , StackAlign ) ; MachineInstr * New = nullptr ; Amount -= InternalAmt ; if ( Amount ) { if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( IsLP64 , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; unsigned Opc = getADDriOpcode ( IsLP64 , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } return ; } if ( Opcode == TII . getCallFrameDestroyOpcode ( ) && InternalAmt ) { unsigned Opc = getSUBriOpcode ( IsLP64 , InternalAmt ) ; MachineInstr * New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( InternalAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! std :: prev ( I ) -> isCall ( ) ) -- I ; MBB . insert ( I , New ) ; } } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> void NVPTXPassConfig :: addIRPasses ( ) { disablePass ( & PrologEpilogCodeInserterID ) ; disablePass ( & MachineCopyPropagationID ) ; disablePass ( & TailDuplicateID ) ; disablePass ( & StackMapLivenessID ) ; disablePass ( & LiveDebugValuesID ) ; disablePass ( & PostRAMachineSinkingID ) ; disablePass ( & PostRASchedulerID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & PatchableFunctionID ) ; disablePass ( & ShrinkWrapID ) ; const NVPTXSubtarget & ST = * getTM < NVPTXTargetMachine > ( ) . getSubtargetImpl ( ) ; addPass ( createNVVMReflectPass ( ST . getSmVersion ( ) ) ) ; if ( getTM < NVPTXTargetMachine > ( ) . getTargetTriple ( ) . getOS ( ) == Triple :: CUDA ) { addPass ( createGlobalOffsetPass ( ) ) ; addPass ( createLocalAccessorToSharedMemoryPass ( ) ) ; } if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createNVPTXImageOptimizerPass ( ) ) ; addPass ( createNVPTXAssignValidGlobalNamesPass ( ) ) ; addPass ( createGenericToNVVMPass ( ) ) ; addPass ( createNVPTXLowerArgsPass ( & getNVPTXTargetMachine ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addAddressSpaceInferencePasses ( ) ; addStraightLineScalarOptimizationPasses ( ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addEarlyCSEOrGVNPass ( ) ; if ( ! DisableLoadStoreVectorizer ) addPass ( createLoadStoreVectorizerPass ( ) ) ; addPass ( createSROAPass ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX


<s> static bool tilepro_scalar_mode_supported_p ( machine_mode mode ) { switch ( mode ) { case QImode : case HImode : case SImode : case DImode : return true ; case SFmode : case DFmode : return true ; default : return false ; } } </s>


<s> int uns_arith_operand ( rtx op , enum machine_mode mode ) { if ( GET_CODE ( op ) == CONST_INT && SMALL_INT_UNSIGNED ( op ) ) return 1 ; return register_operand ( op , mode ) ; } </s>

Return truth value of whether OP can be used as an operands where a register or 16 bit unsigned integer is needed .


<s> bool AArch64PassConfig :: addPreEmitPass ( ) { if ( EnableA53Fix835769 ) addPass ( createAArch64A53Fix835769 ( ) ) ; addPass ( createAArch64BranchRelaxation ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getSubtarget < AArch64Subtarget > ( ) . isTargetMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; return true ; } </s>


Return the output template for emitting a dbra type insn . Note it may perform some output operations on its own before returning the final output string .


<s> uint32_t ARMMCCodeEmitter :: getBranchTargetOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const ARMSubtarget & Subtarget = TM . getSubtarget < ARMSubtarget > ( ) ; if ( Subtarget . isThumb2 ( ) ) return :: getBranchTargetOpValue ( MI , OpIdx , ARM :: fixup_t2_branch , Fixups ) ; return :: getBranchTargetOpValue ( MI , OpIdx , ARM :: fixup_arm_branch , Fixups ) ; } </s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .

ARM ARM ARM ARM ARM::fixup_t2_branch ARM::fixup_arm_branch


<s>
MachineInstrBuilder
R600InstrInfo
::
buildIndirectWrite
(
MachineBasicBlock
*
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
ValueReg
,
unsigned
Address
,
unsigned
OffsetReg
,
unsigned
AddrChan
)
const
{
unsigned
AddrReg
;
switch
(
AddrChan
)
{
default
:
llvm_unreachable
(
"Invalid Channel"
)
;
case
0
:
AddrReg
=
AMDGPU
::
R600_AddrRegClass
.
getRegister
(
Address
)
;
break
;
case
1
:
AddrReg
=
AMDGPU
::
R600_Addr_YRegClass
.
getRegister
(
Address
)
;
break
;
case
2
:
AddrReg
=
AMDGPU
::
R600_Addr_ZRegClass
.
getRegister
(
Address
)
;
break
;
case
3
:
AddrReg
=
AMDGPU
::
R600_Addr_WRegClass
.
getRegister
(
Address
)
;
break
;
}
MachineInstr
*
MOVA
=
buildDefaultInstruction
(
*
MBB
,
I
,
AMDGPU
::
MOVA_INT_eg
,
AMDGPU
::
AR_X
,
OffsetReg
)
;
setImmOperand
(
MOVA
,
AMDGPU
::
OpName
::
write
,
0
)
;
MachineInstrBuilder
Mov
=
buildDefaultInstruction
(
*
MBB
,
I
,
AMDGPU
::
MOV
,
AddrReg
,
ValueReg
)
.
addReg
(
AMDGPU
::
AR_X
,
RegState
::
Implicit
|
RegState
::
Kill
)
;
setImmOperand
(
Mov
,
AMDGPU
::
OpName
::
dst_rel
,
1
)
;
return
Mov
;
}
</s>

Build instruction ( s ) for an indirect register write .


<s>
void
DiagnosticInfoUnsupported
::
print
(
DiagnosticPrinter
&
DP
)
const
{
DP
<<
"unsupported "
<<
getDescription
(
)
<<
" in "
<<
Fn
.
getName
(
)
;
}
</s>

print - Print a debug representation of the operand to the given stream .


"\t# pre-label NOPs for hotpatch (%d halfwords)\n"

"\t# post-label NOPs for hotpatch (%d halfwords)\n"

Write the extra assembler code needed to declare a function properly .


<s>
bool
FixupBWInstPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
!
FixupBWInsts
||
skipFunction
(
*
MF
.
getFunction
(
)
)
)
return
false
;
this
->
MF
=
&
MF
;
TII
=
MF
.
getSubtarget
<
X86Subtarget
>
(
)
.
getInstrInfo
(
)
;
OptForSize
=
MF
.
getFunction
(
)
->
optForSize
(
)
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
LiveRegs
.
init
(
&
TII
->
getRegisterInfo
(
)
)
;
DEBUG
(
dbgs
(
)
<<
"Start X86FixupBWInsts\n"
;
)
;
for
(
auto
&
MBB
:
MF
)
processBasicBlock
(
MF
,
MBB
)
;
DEBUG
(
dbgs
(
)
<<
"End X86FixupBWInsts\n"
;
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool function_checker :: require_immediate_one_of ( unsigned int rel_argno , HOST_WIDE_INT value0 , HOST_WIDE_INT value1 , HOST_WIDE_INT value2 , HOST_WIDE_INT value3 ) { unsigned int argno = m_base_arg + rel_argno ; if ( ! argument_exists_p ( argno ) ) return true ; HOST_WIDE_INT actual ; if ( ! require_immediate ( argno , actual ) ) return false ; if ( actual != value0 && actual != value1 && actual != value2 && actual != value3 ) { report_not_one_of ( location , fndecl , argno , actual , value0 , value1 , value2 , value3 ) ; return false ; } return true ; } </s>

Check that argument REL_ARGNO is an integer constant expression that has one of the given values .


<s>
bool
TVMControlFlowPrepare
::
runOnFunction
(
Function
&
F
)
{
bool
Changed
=
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"runnning TVMControlFlowPrepare on "
<<
F
.
getName
(
)
<<
"\n"
)
;
std
::
vector
<
BasicBlock
*
>
OriginalBBs
;
llvm
::
transform
(
F
,
std
::
back_inserter
(
OriginalBBs
)
,
[
]
(
BasicBlock
&
BB
)
{
return
&
BB
;
}
)
;
for
(
auto
*
BB
:
OriginalBBs
)
{
if
(
pred_size
(
BB
)
>
1
)
{
insertCleanupBBs
(
BB
)
;
Changed
=
true
;
}
}
return
Changed
;
}
</s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .

TVM
TVM
"runnning TVMControlFlowPrepare on "
"\n"
1


<s> bool Nios2AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> static bool frv_pack_insn_p ( rtx insn ) { if ( frv_packet . num_insns == frv_packet . issue_rate ) return false ; if ( frv_packet . num_insns > 0 && GET_CODE ( insn ) == INSN && GET_MODE ( insn ) == TImode && GET_CODE ( PATTERN ( insn ) ) != COND_EXEC ) return false ; if ( get_attr_type ( insn ) != TYPE_SETLO ) if ( frv_registers_conflict_p ( PATTERN ( insn ) ) ) return false ; return state_transition ( frv_packet . dfa_state , insn ) < 0 ; } </s>

Return true if INSN can be added to the current packet . Update the DFA state on success .


<s> InstructionCost GCNTTIImpl :: getIntrinsicInstrCost ( const IntrinsicCostAttributes & ICA , TTI :: TargetCostKind CostKind ) { if ( ICA . getID ( ) == Intrinsic :: fabs ) return 0 ; if ( ! intrinsicHasPackedVectorBenefit ( ICA . getID ( ) ) ) return BaseT :: getIntrinsicInstrCost ( ICA , CostKind ) ; Type * RetTy = ICA . getReturnType ( ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; unsigned NElts = LT . second . isVector ( ) ? LT . second . getVectorNumElements ( ) : 1 ; MVT :: SimpleValueType SLT = LT . second . getScalarType ( ) . SimpleTy ; if ( SLT == MVT :: f64 ) return LT . first * NElts * get64BitInstrCost ( CostKind ) ; if ( ( ST -> has16BitInsts ( ) && SLT == MVT :: f16 ) || ( ST -> hasPackedFP32Ops ( ) && SLT == MVT :: f32 ) ) NElts = ( NElts + 1 ) / 2 ; unsigned InstRate = getQuarterRateInstrCost ( CostKind ) ; switch ( ICA . getID ( ) ) { case Intrinsic :: fma : InstRate = ST -> hasFastFMAF32 ( ) ? getHalfRateInstrCost ( CostKind ) : getQuarterRateInstrCost ( CostKind ) ; break ; case Intrinsic :: uadd_sat : case Intrinsic :: usub_sat : case Intrinsic :: sadd_sat : case Intrinsic :: ssub_sat : static const auto ValidSatTys = { MVT :: v2i16 , MVT :: v4i16 } ; if ( any_of ( ValidSatTys , [ & LT ] ( MVT M ) { return M == LT . second ; } ) ) NElts = 1 ; break ; } return LT . first * NElts * InstRate ; } </s>


<s> unsigned int UPTInstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL , int * BytesAdded ) const { unsigned NumInserted = 0 ; if ( ! Cond . empty ( ) ) { BuildMI ( MBB , MBB . end ( ) , DL , get ( UPT :: Bcc ) ) . add ( Cond [ 0 ] ) . addMBB ( TBB ) ; NumInserted ++ ; } if ( Cond . empty ( ) || FBB ) { BuildMI ( MBB , MBB . end ( ) , DL , get ( UPT :: JMP ) ) . addMBB ( Cond . empty ( ) ? TBB : FBB ) ; NumInserted ++ ; } return NumInserted ; } </s>

Insert branch code into the end of the specified MachineBasicBlock .


<s>
bool
X86TargetMachine
::
isNoopAddrSpaceCast
(
unsigned
SrcAS
,
unsigned
DestAS
)
const
{
assert
(
SrcAS
!=
DestAS
&&
"Expected different address spaces!"
)
;
if
(
getPointerSize
(
SrcAS
)
!=
getPointerSize
(
DestAS
)
)
return
false
;
return
SrcAS
<
256
&&
DestAS
<
256
;
}
</s>

Returns true if a cast between SrcAS and DestAS is a noop .


<s> bool RISCVFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> bool Z80oldTargetLowering :: isNarrowingProfitable ( EVT VT1 , EVT VT2 ) const { return ! ( VT1 == MVT :: i24 && VT2 == MVT :: i16 ) ; } </s>

Return true if it 's profitable to narrow operations of type SrcVT to DestVT .


<s> static void sh_print_operand_address ( FILE * stream , machine_mode , rtx x ) { switch ( GET_CODE ( x ) ) { case REG : case SUBREG : fprintf ( stream , "@%s" , reg_names [ true_regnum ( x ) ] ) ; break ; case PLUS : { rtx base = XEXP ( x , 0 ) ; rtx index = XEXP ( x , 1 ) ; switch ( GET_CODE ( index ) ) { case CONST_INT : fprintf ( stream , "@(%d,%s)" , ( int ) INTVAL ( index ) , reg_names [ true_regnum ( base ) ] ) ; break ; case REG : case SUBREG : { int base_num = true_regnum ( base ) ; int index_num = true_regnum ( index ) ; if ( base_num == 0 && index_num != 0 ) std :: swap ( base_num , index_num ) ; fprintf ( stream , "@(%s,%s)" , reg_names [ index_num ] , reg_names [ base_num ] ) ; break ; } default : gcc_unreachable ( ) ; } } break ; case PRE_DEC : fprintf ( stream , "@-%s" , reg_names [ true_regnum ( XEXP ( x , 0 ) ) ] ) ; break ; case POST_INC : fprintf ( stream , "@%s+" , reg_names [ true_regnum ( XEXP ( x , 0 ) ) ] ) ; break ; default : x = mark_constant_pool_use ( x ) ; output_addr_const ( stream , x ) ; break ; } } </s>

Print the operand address in x to the stream .


"Relocation required in an instruction that we cannot encode!"

getMachineOpValue - Return binary encoding of operand .


<s>
static
const
char
*
rs6000_invalid_within_doloop
(
rtx
insn
)
{
if
(
CALL_P
(
insn
)
)
return
"Function call in the loop."
;
if
(
JUMP_P
(
insn
)
&&
(
GET_CODE
(
PATTERN
(
insn
)
)
==
ADDR_DIFF_VEC
||
GET_CODE
(
PATTERN
(
insn
)
)
==
ADDR_VEC
)
)
return
"Computed branch in the loop."
;
return
;
}
</s>

NULL if INSN insn is valid within a low-overhead loop . Otherwise return why doloop can not be applied . PowerPC uses the COUNT register for branch on table instructions .

rs6000
"Function call in the loop."
"Computed branch in the loop."


<s> const TargetRegisterClass * ARMBaseRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { const TargetRegisterClass * Super = RC ; TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case ARM :: GPRRegClassID : case ARM :: SPRRegClassID : case ARM :: DPRRegClassID : case ARM :: GPRPairRegClassID : return Super ; case ARM :: QPRRegClassID : case ARM :: QQPRRegClassID : case ARM :: QQQQPRRegClassID : if ( MF . getSubtarget < ARMSubtarget > ( ) . hasNEON ( ) ) return Super ; } Super = * I ++ ; } while ( Super ) ; return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .

ARM ARM ARM::GPRRegClassID ARM::SPRRegClassID ARM::DPRRegClassID ARM::GPRPairRegClassID ARM::QPRRegClassID ARM::QQPRRegClassID ARM::QQQQPRRegClassID ARM


<s> std :: pair < unsigned , unsigned > HexagonInstrInfo :: decomposeMachineOperandsTargetFlags ( unsigned TF ) const { return std :: make_pair ( TF & ~ HexagonII :: MO_Bitmasks , TF & HexagonII :: MO_Bitmasks ) ; } </s>

Decompose the machine operand 's target flags into two values - the direct target flag value and any of bit flags that are applied .


<s> static void msp430_print_operand_addr ( FILE * file , rtx addr ) { switch ( GET_CODE ( addr ) ) { case PLUS : msp430_print_operand_raw ( file , XEXP ( addr , 1 ) ) ; gcc_assert ( REG_P ( XEXP ( addr , 0 ) ) ) ; fprintf ( file , "(%s)" , reg_names [ REGNO ( XEXP ( addr , 0 ) ) ] ) ; return ; case REG : fprintf ( file , "@" ) ; break ; case CONST : case CONST_INT : case SYMBOL_REF : case LABEL_REF : fprintf ( file , "&" ) ; break ; default : break ; } msp430_print_operand_raw ( file , addr ) ; } </s>

Output to stdio stream FILE the assembler syntax for an instruction operand that is a memory reference whose address is ADDR .


"********** AArch64 Conditional Compares **********\n"


<s> bool Thumb1InstrInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( CSI . empty ( ) ) return false ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > 0 ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( ARM :: tPOP ) ) ; AddDefaultPred ( MIB ) ; bool NumRegs = false ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( Reg == ARM :: LR ) { if ( isVarArg ) continue ; Reg = ARM :: PC ; ( * MIB ) . setDesc ( get ( ARM :: tPOP_RET ) ) ; MI = MBB . erase ( MI ) ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; NumRegs = true ; } if ( NumRegs ) MBB . insert ( MI , & * MIB ) ; else MF . DeleteMachineInstr ( MIB ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s>
MachineBasicBlock
*
LM32TargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
MBB
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
assert
(
false
&&
"Unexpected instr type to insert"
)
;
case
LM32
::
SelectCC_Opc
:
return
EmitCustomSelect
(
MI
,
MBB
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> bool AMDGPUCodeGenPrepare :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; const AMDGPUTargetMachine & TM = TPC -> getTM < AMDGPUTargetMachine > ( ) ; ST = & TM . getSubtarget < GCNSubtarget > ( F ) ; DA = & getAnalysis < DivergenceAnalysis > ( ) ; HasUnsafeFPMath = hasUnsafeFPMath ( F ) ; AMDGPUASI = TM . getAMDGPUAS ( ) ; bool MadeChange = false ; for ( BasicBlock & BB : F ) { BasicBlock :: iterator Next ; for ( BasicBlock :: iterator I = BB . begin ( ) , E = BB . end ( ) ; I != E ; I = Next ) { Next = std :: next ( I ) ; MadeChange |= visit ( * I ) ; } } return MadeChange ; } </s>


<s> bool KudeyarFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; if ( CSI . size ( ) > 1 ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( Kudeyar :: POPA ) ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MIB . addReg ( Reg , getDefRegState ( true ) ) ; } } else { unsigned Reg = CSI [ 0 ] . getReg ( ) ; BuildMI ( MBB , MI , DL , TII . get ( Kudeyar :: POP_R ) , Reg ) ; } for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) BuildMI ( MBB , MI , DL , TII . get ( Kudeyar :: POP_R ) , CSI [ i ] . getReg ( ) ) ; return true ; } </s>


<s>
void
avr_output_addr_vec_elt
(
FILE
*
stream
,
int
value
)
{
if
(
AVR_HAVE_JMP_CALL
)
fprintf
(
stream
,
"\t.word gs(.L%d)\n"
,
value
)
;
else
fprintf
(
stream
,
"\trjmp .L%d\n"
,
value
)
;
}
</s>

Worker function for ` ASM_OUTPUT_ADDR_VEC_ELT ' .

avr
"\t.word gs(.L%d)\n"
"\trjmp .L%d\n"


<s> static bool msp430_check_index_not_high_mem ( rtx op ) { if ( CONST_INT_P ( op ) && IN_RANGE ( INTVAL ( op ) , HOST_WIDE_INT_M1U << 15 , ( 1 << 15 ) - 1 ) ) return true ; return false ; } </s>

We can only allow signed 15-bit indexes i.e . +/-32K .


<s> static tree sparc_gimplify_va_arg ( tree valist , tree type , tree * pre_p , tree * post_p ) { HOST_WIDE_INT size , rsize , align ; tree addr , incr ; bool indirect ; tree ptrtype = build_pointer_type ( type ) ; if ( pass_by_reference ( NULL , TYPE_MODE ( type ) , type , false ) ) { indirect = true ; size = rsize = UNITS_PER_WORD ; align = 0 ; } else { indirect = false ; size = int_size_in_bytes ( type ) ; rsize = ( size + UNITS_PER_WORD - 1 ) & - UNITS_PER_WORD ; align = 0 ; if ( TARGET_ARCH64 ) { if ( TYPE_ALIGN ( type ) >= 2 * ( unsigned ) BITS_PER_WORD ) align = 2 * UNITS_PER_WORD ; if ( AGGREGATE_TYPE_P ( type ) ) { if ( size == 0 ) size = rsize = UNITS_PER_WORD ; else size = rsize ; } } } incr = valist ; if ( align ) { incr = fold ( build2 ( PLUS_EXPR , ptr_type_node , incr , ssize_int ( align - 1 ) ) ) ; incr = fold ( build2 ( BIT_AND_EXPR , ptr_type_node , incr , ssize_int ( - align ) ) ) ; } gimplify_expr ( & incr , pre_p , post_p , is_gimple_val , fb_rvalue ) ; addr = incr ; if ( BYTES_BIG_ENDIAN && size < rsize ) addr = fold ( build2 ( PLUS_EXPR , ptr_type_node , incr , ssize_int ( rsize - size ) ) ) ; if ( indirect ) { addr = fold_convert ( build_pointer_type ( ptrtype ) , addr ) ; addr = build_va_arg_indirect_ref ( addr ) ; } else if ( align == 0 && TYPE_ALIGN ( type ) > BITS_PER_WORD ) { tree tmp = create_tmp_var ( type , "va_arg_tmp" ) ; tree dest_addr = build_fold_addr_expr ( tmp ) ; tree copy = build_function_call_expr ( implicit_built_in_decls [ BUILT_IN_MEMCPY ] , tree_cons ( NULL_TREE , dest_addr , tree_cons ( NULL_TREE , addr , tree_cons ( NULL_TREE , size_int ( rsize ) , NULL_TREE ) ) ) ) ; gimplify_and_add ( copy , pre_p ) ; addr = dest_addr ; } else addr = fold_convert ( ptrtype , addr ) ; incr = fold ( build2 ( PLUS_EXPR , ptr_type_node , incr , ssize_int ( rsize ) ) ) ; incr = build2 ( MODIFY_EXPR , ptr_type_node , valist , incr ) ; gimplify_and_add ( incr , post_p ) ; return build_va_arg_indirect_ref ( addr ) ; } </s>


<s> bool AMDGPUPromoteAllocaToVector :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) || DisablePromoteAllocaToVector ) return false ; bool Changed = false ; BasicBlock & EntryBB = * F . begin ( ) ; SmallVector < AllocaInst * , 16 > Allocas ; for ( Instruction & I : EntryBB ) { if ( AllocaInst * AI = dyn_cast < AllocaInst > ( & I ) ) Allocas . push_back ( AI ) ; } for ( AllocaInst * AI : Allocas ) { if ( handleAlloca ( * AI ) ) Changed = true ; } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s>
void
ARMInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
DebugLoc
::
getUnknownLoc
(
)
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
if
(
RC
==
ARM
::
GPRRegisterClass
)
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
ARMFunctionInfo
*
AFI
=
MF
.
getInfo
<
ARMFunctionInfo
>
(
)
;
assert
(
!
AFI
->
isThumbFunction
(
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
LDR
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addReg
(
0
)
.
addImm
(
0
)
)
;
}
else
if
(
RC
==
ARM
::
tGPRRegisterClass
)
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
ARMFunctionInfo
*
AFI
=
MF
.
getInfo
<
ARMFunctionInfo
>
(
)
;
assert
(
AFI
->
isThumbFunction
(
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tRestore
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
}
else
if
(
RC
==
ARM
::
DPRRegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
FLDD
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
)
;
}
else
{
assert
(
RC
==
ARM
::
SPRRegisterClass
&&
"Unknown regclass!"
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
FLDS
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
)
;
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .

ARM
ARM
ARM::GPRRegisterClass
ARM
ARM
ARM::LDR
0
0
ARM::tGPRRegisterClass
ARM
ARM
ARM::tRestore
0
ARM::DPRRegisterClass
ARM::FLDD
0
ARM::SPRRegisterClass
"Unknown regclass!"
ARM::FLDS
0


"Only half, single and double precision supported"

isFPImm - Tests if this is a MO_FPImmediate operand .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> EVT ARMTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsZeroVal , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( IsZeroVal && ! F -> getFnAttributes ( ) . hasAttribute ( Attributes :: NoImplicitFloat ) && Subtarget -> hasNEON ( ) ) { if ( memOpAlign ( SrcAlign , DstAlign , 16 ) && Size >= 16 ) { return MVT :: v4i32 ; } else if ( memOpAlign ( SrcAlign , DstAlign , 8 ) && Size >= 8 ) { return MVT :: v2i32 ; } } if ( Size >= 4 ) { return MVT :: i32 ; } else if ( Size >= 2 ) { return MVT :: i16 ; } return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> int rs6000_trampoline_size ( void ) { int ret = 0 ; switch ( DEFAULT_ABI ) { default : gcc_unreachable ( ) ; case ABI_AIX : ret = ( TARGET_32BIT ) ? 12 : 24 ; break ; case ABI_DARWIN : case ABI_V4 : ret = ( TARGET_32BIT ) ? 40 : 48 ; break ; } return ret ; } </s>

Length in units of the trampoline for entering a nested function .


<s> int SIInstrInfo :: pseudoToMCOpcode ( int Opcode ) const { SIEncodingFamily Gen = subtargetEncodingFamily ( ST ) ; if ( ( get ( Opcode ) . TSFlags & SIInstrFlags :: renamedInGFX9 ) != 0 && ST . getGeneration ( ) == AMDGPUSubtarget :: GFX9 ) Gen = SIEncodingFamily :: GFX9 ; if ( ST . hasUnpackedD16VMem ( ) && ( get ( Opcode ) . TSFlags & SIInstrFlags :: D16Buf ) ) Gen = SIEncodingFamily :: GFX80 ; if ( get ( Opcode ) . TSFlags & SIInstrFlags :: SDWA ) { switch ( ST . getGeneration ( ) ) { default : Gen = SIEncodingFamily :: SDWA ; break ; case AMDGPUSubtarget :: GFX9 : Gen = SIEncodingFamily :: SDWA9 ; break ; case AMDGPUSubtarget :: GFX10 : Gen = SIEncodingFamily :: SDWA10 ; break ; } } if ( isMAI ( Opcode ) ) { int MFMAOp = AMDGPU :: getMFMAEarlyClobberOp ( Opcode ) ; if ( MFMAOp != - 1 ) Opcode = MFMAOp ; } int MCOp = AMDGPU :: getMCOpcode ( Opcode , Gen ) ; if ( MCOp == - 1 ) return Opcode ; if ( ST . hasGFX90AInsts ( ) ) { uint16_t NMCOp = ( uint16_t ) - 1 ; NMCOp = AMDGPU :: getMCOpcode ( Opcode , SIEncodingFamily :: GFX90A ) ; if ( NMCOp == ( uint16_t ) - 1 ) NMCOp = AMDGPU :: getMCOpcode ( Opcode , SIEncodingFamily :: GFX9 ) ; if ( NMCOp != ( uint16_t ) - 1 ) MCOp = NMCOp ; } if ( MCOp == ( uint16_t ) - 1 ) return - 1 ; if ( isAsmOnlyOpcode ( MCOp ) ) return - 1 ; return MCOp ; } </s>

Return a target-specific opcode if Opcode is a pseudo instruction .


<s> static rtx sparc_tls_got ( void ) { rtx temp ; if ( flag_pic ) { current_function_uses_pic_offset_table = 1 ; return pic_offset_table_rtx ; } if ( ! global_offset_table ) global_offset_table = gen_rtx_SYMBOL_REF ( Pmode , "_GLOBAL_OFFSET_TABLE_" ) ; temp = gen_reg_rtx ( Pmode ) ; emit_move_insn ( temp , global_offset_table ) ; return temp ; } </s>

Return the Global Offset Table to be used in TLS mode .


<s> bool AArch64InstrInfo :: analyzeCompare ( const MachineInstr & MI , unsigned & SrcReg , unsigned & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI . getOpcode ( ) ) { default : break ; case AArch64 :: SUBSWrr : case AArch64 :: SUBSWrs : case AArch64 :: SUBSWrx : case AArch64 :: SUBSXrr : case AArch64 :: SUBSXrs : case AArch64 :: SUBSXrx : case AArch64 :: ADDSWrr : case AArch64 :: ADDSWrs : case AArch64 :: ADDSWrx : case AArch64 :: ADDSXrr : case AArch64 :: ADDSXrs : case AArch64 :: ADDSXrx : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 2 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case AArch64 :: SUBSWri : case AArch64 :: ADDSWri : case AArch64 :: SUBSXri : case AArch64 :: ADDSXri : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 2 ) . getImm ( ) != 0 ; return true ; case AArch64 :: ANDSWri : case AArch64 :: ANDSXri : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = AArch64_AM :: decodeLogicalImmediate ( MI . getOperand ( 2 ) . getImm ( ) , MI . getOpcode ( ) == AArch64 :: ANDSWri ? 32 : 64 ) != 0 ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> void HexagonPassConfig :: addPreSched2 ( ) { const HexagonTargetMachine & TM = getHexagonTargetMachine ( ) ; addPass ( createHexagonCopyToCombine ( ) , false ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & IfConverterID , false ) ; addPass ( createHexagonSplitConst32AndConst64 ( TM ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .

Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon


<s> virtual const MSP430Subtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> const MachineOperand * getNamedOperand ( const MachineInstr & MI , unsigned OpName ) const { return getNamedOperand ( const_cast < MachineInstr & > ( MI ) , OpName ) ; } </s>


<s> const GBZ80InstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> bool ARMTargetLowering :: isLegalT1ScaledAddressingMode ( const AddrMode & AM , EVT VT ) const { const int Scale = AM . Scale ; if ( Scale < 0 ) return false ; return ( Scale == 1 ) || ( ! AM . HasBaseReg && Scale == 2 ) ; } </s>

Returns true if the addressing mode representing by AM is legal for the Thumb1 target , for a load/store of the specified type .


<s> void HexagonPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableCExtOpt ) addPass ( createHexagonConstExtenders ( ) ) ; if ( EnableExpandCondsets ) insertPass ( & RegisterCoalescerID , & HexagonExpandCondsetsID ) ; if ( ! DisableStoreWidening ) addPass ( createHexagonStoreWidening ( ) ) ; if ( ! DisableHardwareLoops ) addPass ( createHexagonHardwareLoops ( ) ) ; } if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Default ) addPass ( & MachinePipelinerID ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static bool rs6000_vectorize_vec_perm_const ( machine_mode vmode , rtx target , rtx op0 , rtx op1 , const vec_perm_indices & sel ) { bool testing_p = ! target ; if ( TARGET_ALTIVEC && testing_p ) return true ; if ( ( vmode == V2SFmode && TARGET_PAIRED_FLOAT ) || ( ( vmode == V2DFmode || vmode == V2DImode ) && VECTOR_MEM_VSX_P ( vmode ) ) ) { if ( testing_p ) { op0 = gen_raw_REG ( vmode , LAST_VIRTUAL_REGISTER + 1 ) ; op1 = gen_raw_REG ( vmode , LAST_VIRTUAL_REGISTER + 2 ) ; } if ( rs6000_expand_vec_perm_const_1 ( target , op0 , op1 , sel [ 0 ] , sel [ 1 ] ) ) return true ; } if ( TARGET_ALTIVEC ) { if ( vmode != V16QImode ) return false ; if ( altivec_expand_vec_perm_const ( target , op0 , op1 , sel ) ) return true ; } return false ; } </s>


<s> const Triple & getTargetTriple ( ) const { return TargetTriple ; } </s>

Get the target triple which is a string describing the target host .


<s> static inline int regno_or_subregno ( rtx op ) { if ( REG_P ( op ) ) return REGNO ( op ) ; else if ( SUBREG_P ( op ) ) return subreg_regno ( op ) ; else gcc_unreachable ( ) ; } </s>

Helper function to return the register number of a RTX .


<s> virtual SDNode * PostISelFolding ( MachineSDNode * N , SelectionDAG & DAG ) const { return N ; } </s>

Fold the instructions after selecting them .


<s> void emitTBSSSymbol ( MCSection * Section , MCSymbol * Symbol , uint64_t Size , unsigned ByteAlignment = 0 ) override { } </s>

Emit a thread local bss ( .tbss ) symbol .


<s> static int loongarch_binary_cost ( rtx x , int single_cost , int double_cost , bool speed ) { int cost ; if ( GET_MODE_SIZE ( GET_MODE ( x ) ) == UNITS_PER_WORD * 2 ) cost = double_cost ; else cost = single_cost ; return ( cost + set_src_cost ( XEXP ( x , 0 ) , GET_MODE ( x ) , speed ) + rtx_cost ( XEXP ( x , 1 ) , GET_MODE ( x ) , GET_CODE ( x ) , 1 , speed ) ) ; } </s>

Return the cost of binary operation X , given that the instruction sequence for a word-sized or smaller operation has cost SINGLE_COST and that the sequence of a double-word operation has cost DOUBLE_COST . If SPEED is true , optimize for speed otherwise optimize for size .


<s> void F2003fInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdx ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; BuildMI ( MBB , MI , DL , get ( F2003f :: KRZrm ) ) . addReg ( DestReg , getDefRegState ( true ) ) . addFrameIndex ( FrameIdx ) . addReg ( 0 ) . addImm ( 0 ) . addMemOperand ( MMO ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> bool HexagonTargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( Kind . isBSS ( ) || Kind . isData ( ) || Kind . isCommon ( ) ) { Type * Ty = GV -> getValueType ( ) ; return IsInSmallSection ( GV -> getParent ( ) -> getDataLayout ( ) . getTypeAllocSize ( Ty ) ) ; } return false ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> const uint32_t * Comet2RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { return CSR_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static inline const MachineInstrBuilder & addMemOperand ( const MachineInstrBuilder & MIB , int FI , int Offset = 0 ) { MachineInstr * MI = MIB ; MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; auto Flags = MachineMemOperand :: MONone ; if ( MCID . mayLoad ( ) ) Flags |= MachineMemOperand :: MOLoad ; if ( MCID . mayStore ( ) ) Flags |= MachineMemOperand :: MOStore ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI , Offset ) , Flags , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; return MIB . addMemOperand ( MMO ) ; } </s>

Add a MachineMemOperand to the machine instruction .


<s>
static
bool
arm_rtx_costs
(
rtx
x
,
machine_mode
mode
ATTRIBUTE_UNUSED
,
int
outer_code
,
int
opno
ATTRIBUTE_UNUSED
,
int
*
total
,
bool
speed
)
{
bool
result
;
int
code
=
GET_CODE
(
x
)
;
if
(
TARGET_OLD_RTX_COSTS
||
(
!
current_tune
->
insn_extra_cost
&&
!
TARGET_NEW_GENERIC_COSTS
)
)
{
if
(
!
speed
)
result
=
arm_size_rtx_costs
(
x
,
(
enum
rtx_code
)
code
,
(
enum
rtx_code
)
outer_code
,
total
)
;
else
result
=
current_tune
->
rtx_costs
(
x
,
(
enum
rtx_code
)
code
,
(
enum
rtx_code
)
outer_code
,
total
,
speed
)
;
}
else
{
if
(
current_tune
->
insn_extra_cost
)
result
=
arm_new_rtx_costs
(
x
,
(
enum
rtx_code
)
code
,
(
enum
rtx_code
)
outer_code
,
current_tune
->
insn_extra_cost
,
total
,
speed
)
;
else
result
=
arm_new_rtx_costs
(
x
,
(
enum
rtx_code
)
code
,
(
enum
rtx_code
)
outer_code
,
&
generic_extra_costs
,
total
,
speed
)
;
}
if
(
dump_file
&&
(
dump_flags
&
TDF_DETAILS
)
)
{
print_rtl_single
(
dump_file
,
x
)
;
fprintf
(
dump_file
,
"\n%s cost: %d (%s)\n"
,
speed
"Hot"
:
"Cold"
,
*
total
,
result
"final"
:
"partial"
)
;
}
return
result
;
}
</s>

arm
"\n%s cost: %d (%s)\n"
"Hot"
"Cold"
"final"
"partial"


<s> void MipsPassConfig :: addPreEmitPass ( ) { addPass ( createMicroMipsSizeReductionPass ( ) ) ; addPass ( createMipsDelaySlotFillerPass ( ) ) ; addPass ( createMipsBranchExpansion ( ) ) ; addPass ( createMipsConstantIslandPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> int m32r_expand_block_move ( rtx operands [ ] ) { rtx orig_dst = operands [ 0 ] ; rtx orig_src = operands [ 1 ] ; rtx bytes_rtx = operands [ 2 ] ; rtx align_rtx = operands [ 3 ] ; int constp = GET_CODE ( bytes_rtx ) == CONST_INT ; HOST_WIDE_INT bytes = constp ? INTVAL ( bytes_rtx ) : 0 ; int align = INTVAL ( align_rtx ) ; int leftover ; rtx src_reg ; rtx dst_reg ; if ( constp && bytes <= 0 ) return 1 ; dst_reg = copy_addr_to_reg ( XEXP ( orig_dst , 0 ) ) ; src_reg = copy_addr_to_reg ( XEXP ( orig_src , 0 ) ) ; if ( align > UNITS_PER_WORD ) align = UNITS_PER_WORD ; if ( optimize_size || ! constp || align != UNITS_PER_WORD ) { block_move_call ( dst_reg , src_reg , bytes_rtx ) ; return 0 ; } leftover = bytes % MAX_MOVE_BYTES ; bytes -= leftover ; if ( bytes ) { rtx label = NULL_RTX ; rtx final_src = NULL_RTX ; rtx at_a_time = GEN_INT ( MAX_MOVE_BYTES ) ; rtx rounded_total = GEN_INT ( bytes ) ; rtx new_dst_reg = gen_reg_rtx ( SImode ) ; rtx new_src_reg = gen_reg_rtx ( SImode ) ; if ( bytes > MAX_MOVE_BYTES ) { final_src = gen_reg_rtx ( Pmode ) ; if ( INT16_P ( bytes ) ) emit_insn ( gen_addsi3 ( final_src , src_reg , rounded_total ) ) ; else { emit_insn ( gen_movsi ( final_src , rounded_total ) ) ; emit_insn ( gen_addsi3 ( final_src , final_src , src_reg ) ) ; } label = gen_label_rtx ( ) ; emit_label ( label ) ; } emit_insn ( gen_movmemsi_internal ( dst_reg , src_reg , at_a_time , new_dst_reg , new_src_reg ) ) ; emit_move_insn ( dst_reg , new_dst_reg ) ; emit_move_insn ( src_reg , new_src_reg ) ; emit_insn ( gen_addsi3 ( dst_reg , dst_reg , GEN_INT ( 4 ) ) ) ; if ( bytes > MAX_MOVE_BYTES ) { emit_insn ( gen_cmpsi ( src_reg , final_src ) ) ; emit_jump_insn ( gen_bne ( label ) ) ; } } if ( leftover ) emit_insn ( gen_movmemsi_internal ( dst_reg , src_reg , GEN_INT ( leftover ) , gen_reg_rtx ( SImode ) , gen_reg_rtx ( SImode ) ) ) ; return 1 ; } </s>

Expand string/block move operations . operands [ 0 ] is the pointer to the destination . operands [ 1 ] is the pointer to the source . operands [ 2 ] is the number of bytes to move . operands [ 3 ] is the alignment .


"it would convert a WLS from forward to a "

Checks if loop has a backwards branching WLS , and if possible , fixes it .


<s> bool SPIRVPreLegalizer :: runOnMachineFunction ( MachineFunction & MF ) { const SPIRVSubtarget & ST = MF . getSubtarget < SPIRVSubtarget > ( ) ; SPIRVGlobalRegistry * GR = ST . getSPIRVGlobalRegistry ( ) ; GR -> setCurrentFunc ( MF ) ; MachineIRBuilder MIB ( MF ) ; foldConstantsIntoIntrinsics ( MF ) ; insertBitcasts ( MF , GR , MIB ) ; generateAssignInstrs ( MF , GR , MIB ) ; processInstrsWithTypeFolding ( MF , GR , MIB ) ; processSwitches ( MF , GR , MIB ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> static void cr16_create_dwarf_for_multi_push ( rtx insn ) { rtx dwarf , reg , tmp ; int i , j , from , to , word_cnt , dwarf_par_index , inc ; machine_mode mode ; int num_regs = 0 , offset = 0 , split_here = 0 , total_push_bytes = 0 ; for ( i = 0 ; i <= current_frame_info . last_reg_to_save ; ++ i ) { if ( current_frame_info . save_regs [ i ] ) { ++ num_regs ; if ( i < CR16_FIRST_DWORD_REGISTER ) total_push_bytes += 2 ; else total_push_bytes += 4 ; } } if ( ! num_regs ) return ; dwarf = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( num_regs + 1 ) ) ; dwarf_par_index = num_regs ; from = current_frame_info . last_reg_to_save + 1 ; to = current_frame_info . last_reg_to_save ; word_cnt = 0 ; for ( i = current_frame_info . last_reg_to_save ; i >= 0 ; ) { if ( ! current_frame_info . save_regs [ i ] || 0 == i || split_here ) { if ( 0 == i && current_frame_info . save_regs [ i ] ) from = 0 ; for ( j = to ; j >= from ; -- j ) { if ( j < CR16_FIRST_DWORD_REGISTER ) { mode = HImode ; inc = 1 ; } else { mode = SImode ; inc = 2 ; } reg = gen_rtx_REG ( mode , j ) ; offset += 2 * inc ; tmp = gen_rtx_SET ( VOIDmode , gen_frame_mem ( mode , plus_constant ( Pmode , stack_pointer_rtx , total_push_bytes - offset ) ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , dwarf_par_index -- ) = tmp ; } from = i ; to = -- i ; split_here = 0 ; word_cnt = 0 ; continue ; } if ( i != RETURN_ADDRESS_REGNUM ) { inc = ( i < CR16_FIRST_DWORD_REGISTER ) ? 1 : 2 ; if ( word_cnt + inc >= MAX_COUNT || FRAME_POINTER_REGNUM == i ) { split_here = 1 ; from = i ; continue ; } word_cnt += inc ; } from = i -- ; } tmp = gen_rtx_SET ( SImode , stack_pointer_rtx , gen_rtx_PLUS ( SImode , stack_pointer_rtx , GEN_INT ( - offset ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , 0 ) = tmp ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , dwarf ) ; } </s>

Generate DWARF2 annotation for multi-push instruction .


<s> bool MipsAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < MipsSubtarget > ( ) ; MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; if ( Subtarget -> inMips16Mode ( ) ) for ( std :: map < const char * , const llvm :: Mips16HardFloatInfo :: FuncSignature * > :: const_iterator it = MipsFI -> StubsNeeded . begin ( ) ; it != MipsFI -> StubsNeeded . end ( ) ; ++ it ) { const char * Symbol = it -> first ; const llvm :: Mips16HardFloatInfo :: FuncSignature * Signature = it -> second ; if ( StubsNeeded . find ( Symbol ) == StubsNeeded . end ( ) ) StubsNeeded [ Symbol ] = Signature ; } MCP = MF . getConstantPool ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) NaClAlignIndirectJumpTargets ( MF ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>

Mips Mips Mips Mips Mips Mips Mips16HardFloatInfo::FuncSignature Mips Mips Mips16HardFloatInfo::FuncSignature


<s> unsigned getNumFixupKinds ( ) const override { return PPC :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> bool SIWholeQuadMode :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getFunction ( ) -> getCallingConv ( ) != CallingConv :: AMDGPU_PS ) return false ; Instructions . clear ( ) ; Blocks . clear ( ) ; LiveMaskQueries . clear ( ) ; const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; LIS = & getAnalysis < LiveIntervals > ( ) ; char GlobalFlags = analyzeFunction ( MF ) ; if ( ! ( GlobalFlags & StateWQM ) ) { lowerLiveMaskQueries ( AMDGPU :: EXEC ) ; return ! LiveMaskQueries . empty ( ) ; } unsigned LiveMaskReg = 0 ; { MachineBasicBlock & Entry = MF . front ( ) ; MachineBasicBlock :: iterator EntryMI = Entry . getFirstNonPHI ( ) ; if ( GlobalFlags & StateExact || ! LiveMaskQueries . empty ( ) ) { LiveMaskReg = MRI -> createVirtualRegister ( & AMDGPU :: SReg_64RegClass ) ; MachineInstr * MI = BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( AMDGPU :: COPY ) , LiveMaskReg ) . addReg ( AMDGPU :: EXEC ) ; LIS -> InsertMachineInstrInMaps ( * MI ) ; } if ( GlobalFlags == StateWQM ) { BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( AMDGPU :: S_WQM_B64 ) , AMDGPU :: EXEC ) . addReg ( AMDGPU :: EXEC ) ; lowerLiveMaskQueries ( LiveMaskReg ) ; return true ; } } DEBUG ( printInfo ( ) ) ; lowerLiveMaskQueries ( LiveMaskReg ) ; for ( auto BII : Blocks ) processBlock ( * BII . first , LiveMaskReg , BII . first == & * MF . begin ( ) ) ; LIS -> removeRegUnit ( * MCRegUnitIterator ( AMDGPU :: SCC , TRI ) ) ; return true ; } </s>

AMDGPU SI AMDGPU SI SI AMDGPU::EXEC 0 AMDGPU::SReg_64RegClass AMDGPU::COPY AMDGPU::EXEC AMDGPU::S_WQM_B64 AMDGPU::EXEC AMDGPU::EXEC AMDGPU::SCC


<s> const X86TargetMachine & getTargetMachine ( ) { return static_cast < const X86TargetMachine & > ( TM ) ; } </s>

Return the target machine ( if available ) .


<s> static void mips_init_builtins ( void ) { const struct mips_builtin_description * d ; unsigned int i ; for ( i = 0 ; i < ARRAY_SIZE ( mips_builtins ) ; i ++ ) { d = & mips_builtins [ i ] ; if ( d -> avail ( ) ) mips_builtin_decls [ i ] = add_builtin_function ( d -> name , mips_build_function_type ( d -> function_type ) , i , BUILT_IN_MD , NULL , NULL ) ; } } </s>

Init builtin functions . This is called from TARGET_INIT_BUILTIN .


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { GlobalBaseReg = 0 ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; InsertVRSaveCode ( MF ) ; return true ; } </s>


<s> static int csky_sched_adjust_cost ( rtx_insn * insn , int dep_type , rtx_insn * dep , int cost , unsigned int dw ATTRIBUTE_UNUSED ) { if ( dep_type == REG_DEP_ANTI || dep_type == REG_DEP_OUTPUT ) return 0 ; else if ( recog_memoized ( insn ) >= 0 && recog_memoized ( dep ) >= 0 ) { enum attr_type insn_type = get_attr_type ( insn ) ; if ( CSKY_TARGET_ARCH ( CK803 ) ) { if ( insn_type == TYPE_LOAD || insn_type == TYPE_STORE ) { rtx pattern = PATTERN ( insn ) ; gcc_assert ( GET_CODE ( pattern ) == SET ) ; rtx addr = ( insn_type == TYPE_LOAD ? SET_SRC ( pattern ) : SET_DEST ( pattern ) ) ; enum rtx_code code = GET_CODE ( addr ) ; if ( code == ZERO_EXTEND || code == SIGN_EXTEND ) addr = XEXP ( addr , 0 ) ; gcc_assert ( GET_CODE ( addr ) == MEM ) ; rtx base = XEXP ( addr , 0 ) ; rtx reg = NULL_RTX ; if ( REG_P ( base ) ) reg = base ; if ( GET_CODE ( base ) == PLUS && GET_CODE ( XEXP ( base , 0 ) ) == REG ) reg = XEXP ( base , 0 ) ; if ( ( reg != NULL_RTX ) && reg_set_p ( reg , PATTERN ( dep ) ) ) return 2 ; } } else if ( CSKY_TARGET_ARCH ( CK802 ) ) { if ( ( insn_type == TYPE_CALL_JSR || insn_type == TYPE_BRANCH_JMP ) && get_attr_type ( dep ) != TYPE_LOAD ) return 1 ; if ( insn_type == TYPE_LOAD || insn_type == TYPE_STORE ) { rtx pattern = PATTERN ( insn ) ; gcc_assert ( GET_CODE ( pattern ) == SET ) ; rtx addr = ( insn_type == TYPE_LOAD ? SET_SRC ( pattern ) : SET_DEST ( pattern ) ) ; enum rtx_code code = GET_CODE ( addr ) ; if ( code == ZERO_EXTEND || code == SIGN_EXTEND ) addr = XEXP ( addr , 0 ) ; gcc_assert ( GET_CODE ( addr ) == MEM ) ; rtx base = XEXP ( addr , 0 ) ; rtx reg = NULL_RTX ; if ( REG_P ( base ) ) reg = base ; if ( GET_CODE ( base ) == PLUS && GET_CODE ( XEXP ( base , 0 ) ) == REG ) reg = XEXP ( base , 0 ) ; if ( ( reg != NULL_RTX ) && reg_set_p ( reg , PATTERN ( dep ) ) && get_attr_type ( dep ) != TYPE_LOAD ) return 1 ; if ( insn_type == TYPE_STORE && reg_referenced_p ( SET_SRC ( pattern ) , PATTERN ( dep ) ) ) return 1 ; } } } return cost ; } </s>

This function implements the target macro TARGET_SCHED_ADJUST_COST . It corrects the value of COST based on the relationship between INSN and DEP through the dependence DEP_TYPE . It returns the new value .


<s> bool ARMTargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( VT . getVectorNumElements ( ) == 4 && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ 4 ] ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { if ( M [ i ] < 0 ) PFIndexes [ i ] = 8 ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ 0 ] * 9 * 9 * 9 + PFIndexes [ 1 ] * 9 * 9 + PFIndexes [ 2 ] * 9 + PFIndexes [ 3 ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> 30 ) ; if ( Cost <= 4 ) return true ; } bool ReverseVEXT ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) ; return ( EltSize >= 32 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isVREVMask ( M , VT , 64 ) || isVREVMask ( M , VT , 32 ) || isVREVMask ( M , VT , 16 ) || isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTBLMask ( M , VT ) || isVTRNMask ( M , VT , WhichResult ) || isVUZPMask ( M , VT , WhichResult ) || isVZIPMask ( M , VT , WhichResult ) || isVTRN_v_undef_Mask ( M , VT , WhichResult ) || isVUZP_v_undef_Mask ( M , VT , WhichResult ) || isVZIP_v_undef_Mask ( M , VT , WhichResult ) || ( ( VT == MVT :: v8i16 || VT == MVT :: v16i8 ) && isReverseMask ( M , VT ) ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> unsigned ARMBaseInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case ARM :: LDR : case ARM :: t2LDRs : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isReg ( ) && MI -> getOperand ( 3 ) . isImm ( ) && MI -> getOperand ( 2 ) . getReg ( ) == 0 && MI -> getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: t2LDRi12 : case ARM :: tRestore : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VLDRD : case ARM :: VLDRS : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s>
void
PIC16TargetObjectFile
::
Initialize
(
MCContext
&
Ctx
,
const
TargetMachine
&
tm
)
{
TargetLoweringObjectFile
::
Initialize
(
Ctx
,
tm
)
;
TM
=
&
tm
;
BSSSection
=
getPIC16Section
(
"udata.# UDATA"
,
SectionKind
::
getBSS
(
)
)
;
ReadOnlySection
=
getPIC16Section
(
"romdata.# ROMDATA"
,
SectionKind
::
getReadOnly
(
)
)
;
DataSection
=
getPIC16Section
(
"idata.# IDATA"
,
SectionKind
::
getDataRel
(
)
)
;
TextSection
=
getPIC16Section
(
""
,
SectionKind
::
getText
(
)
)
;
ROSections
.
push_back
(
new
PIC16Section
(
(
MCSectionPIC16
*
)
ReadOnlySection
)
)
;
ExternalVarDecls
=
new
PIC16Section
(
getPIC16Section
(
"ExternalVarDecls"
,
SectionKind
::
getMetadata
(
)
)
)
;
ExternalVarDefs
=
new
PIC16Section
(
getPIC16Section
(
"ExternalVarDefs"
,
SectionKind
::
getMetadata
(
)
)
)
;
}
</s>

This method must be called before any actual lowering is done .


<s> static bool classof ( const DiagnosticInfo * DI ) { return DI -> getKind ( ) == DK_MisalignedTrap ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s>
const
char
*
ix86_output_indirect_function_return
(
rtx
ret_op
)
{
if
(
cfun
->
machine
->
function_return_type
!=
indirect_branch_keep
)
{
char
thunk_name
[
32
]
;
enum
indirect_thunk_prefix
need_prefix
=
indirect_thunk_need_prefix
(
current_output_insn
)
;
unsigned
int
regno
=
REGNO
(
ret_op
)
;
gcc_assert
(
regno
==
CX_REG
)
;
if
(
cfun
->
machine
->
function_return_type
!=
indirect_branch_thunk_inline
)
{
bool
need_thunk
=
(
cfun
->
machine
->
function_return_type
==
indirect_branch_thunk
)
;
indirect_thunk_name
(
thunk_name
,
regno
,
need_prefix
,
true
)
;
if
(
need_prefix
==
indirect_thunk_prefix_bnd
)
{
if
(
need_thunk
)
{
indirect_return_via_cx_bnd
=
true
;
indirect_thunks_bnd_used
|=
1
<<
CX_REG
;
}
fprintf
(
asm_out_file
,
"\tbnd jmp\t%s\n"
,
thunk_name
)
;
}
else
{
if
(
need_thunk
)
{
indirect_return_via_cx
=
true
;
indirect_thunks_used
|=
1
<<
CX_REG
;
}
fprintf
(
asm_out_file
,
"\tjmp\t%s\n"
,
thunk_name
)
;
}
}
else
output_indirect_thunk
(
need_prefix
,
regno
)
;
return
""
;
}
else
return
"%!jmp\t%A0"
;
}
</s>

Output indirect function return . RET_OP is the function return target .


<s> static void ix86_emit_save_sse_regs_using_mov ( HOST_WIDE_INT cfa_offset ) { unsigned int regno ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( SSE_REGNO_P ( regno ) && ix86_save_reg ( regno , true ) ) { ix86_emit_save_reg_using_mov ( V4SFmode , regno , cfa_offset ) ; cfa_offset -= GET_MODE_SIZE ( V4SFmode ) ; } } </s>

Emit code to save SSE registers using MOV insns . First register is stored at CFA - CFA_OFFSET .


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ! Subtarget -> isTargetNaCl ( ) && ( N -> getOpcode ( ) == X86ISD :: CALL || ( N -> getOpcode ( ) == X86ISD :: TC_RETURN && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; EVT SrcVT = N -> getOperand ( 0 ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( 0 ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; bool SrcIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> bool RISCVTargetLowering :: isShuffleMaskLegal ( ArrayRef < int > M , EVT VT ) const { if ( ShuffleVectorSDNode :: isSplatMask ( M . data ( ) , VT ) ) return true ; if ( ! isTypeLegal ( VT ) ) return false ; MVT SVT = VT . getSimpleVT ( ) ; bool SwapSources ; int LoSrc , HiSrc ; return ( isElementRotate ( LoSrc , HiSrc , M ) > 0 ) || isInterleaveShuffle ( M , SVT , SwapSources , Subtarget ) ; } </s>


<s>
static
void
ix86_code_end
(
void
)
{
rtx
xops
[
2
]
;
int
regno
;
for
(
regno
=
AX_REG
;
regno
<=
SP_REG
;
regno
++
)
{
char
name
[
32
]
;
tree
decl
;
if
(
!
(
pic_labels_used
&
(
1
<<
regno
)
)
)
continue
;
get_pc_thunk_name
(
name
,
regno
)
;
decl
=
build_decl
(
BUILTINS_LOCATION
,
FUNCTION_DECL
,
get_identifier
(
name
)
,
build_function_type_list
(
void_type_node
,
NULL_TREE
)
)
;
DECL_RESULT
(
decl
)
=
build_decl
(
BUILTINS_LOCATION
,
RESULT_DECL
,
NULL_TREE
,
void_type_node
)
;
TREE_PUBLIC
(
decl
)
=
1
;
TREE_STATIC
(
decl
)
=
1
;
DECL_IGNORED_P
(
decl
)
=
1
;
if
(
TARGET_MACHO
)
{
switch_to_section
(
darwin_sections
[
text_coal_section
]
)
;
fputs
(
"\t.weak_definition\t"
,
asm_out_file
)
;
assemble_name
(
asm_out_file
,
name
)
;
fputs
(
"\n\t.private_extern\t"
,
asm_out_file
)
;
assemble_name
(
asm_out_file
,
name
)
;
putc
(
'\n'
,
asm_out_file
)
;
ASM_OUTPUT_LABEL
(
asm_out_file
,
name
)
;
DECL_WEAK
(
decl
)
=
1
;
}
else
if
(
USE_HIDDEN_LINKONCE
)
{
cgraph_node
::
create
(
decl
)
->
set_comdat_group
(
DECL_ASSEMBLER_NAME
(
decl
)
)
;
targetm
.
asm_out
.
unique_section
(
decl
,
0
)
;
switch_to_section
(
get_named_section
(
decl
,
,
0
)
)
;
targetm
.
asm_out
.
globalize_label
(
asm_out_file
,
name
)
;
fputs
(
"\t.hidden\t"
,
asm_out_file
)
;
assemble_name
(
asm_out_file
,
name
)
;
putc
(
'\n'
,
asm_out_file
)
;
ASM_DECLARE_FUNCTION_NAME
(
asm_out_file
,
name
,
decl
)
;
}
else
{
switch_to_section
(
text_section
)
;
ASM_OUTPUT_LABEL
(
asm_out_file
,
name
)
;
}
DECL_INITIAL
(
decl
)
=
make_node
(
BLOCK
)
;
current_function_decl
=
decl
;
allocate_struct_function
(
decl
,
false
)
;
init_function_start
(
decl
)
;
first_function_block_is_cold
=
false
;
final_start_function
(
emit_barrier
(
)
,
asm_out_file
,
1
)
;
if
(
TARGET_PAD_SHORT_FUNCTION
)
{
int
i
=
8
;
while
(
i
)
fputs
(
"\tnop\n"
,
asm_out_file
)
;
}
xops
[
0
]
=
gen_rtx_REG
(
Pmode
,
regno
)
;
xops
[
1
]
=
gen_rtx_MEM
(
Pmode
,
stack_pointer_rtx
)
;
output_asm_insn
(
"mov%z0\t{%1, %0|%0, %1}"
,
xops
)
;
output_asm_insn
(
"%!ret"
,
)
;
final_end_function
(
)
;
init_insn_lengths
(
)
;
free_after_compilation
(
cfun
)
;
set_cfun
(
)
;
current_function_decl
=
;
}
if
(
flag_split_stack
)
file_end_indicate_split_stack
(
)
;
}
</s>

This function generates code for -fpic that loads % ebx with the return address of the caller and then returns .


<s> static bool tilepro_current_function_is_leaf ( void ) { return crtl -> is_leaf && ! cfun -> machine -> calls_tls_get_addr ; } </s>

Return whether the current function is leaf . This takes into account whether the function calls tls_get_addr .


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
READCYCLECOUNTER
:
ReplaceREADCYCLECOUNTER
(
N
,
Results
,
DAG
,
Subtarget
)
;
return
;
case
ISD
::
ATOMIC_STORE
:
case
ISD
::
ATOMIC_LOAD
:
case
ISD
::
ATOMIC_LOAD_ADD
:
case
ISD
::
ATOMIC_LOAD_AND
:
case
ISD
::
ATOMIC_LOAD_NAND
:
case
ISD
::
ATOMIC_LOAD_OR
:
case
ISD
::
ATOMIC_LOAD_SUB
:
case
ISD
::
ATOMIC_LOAD_XOR
:
case
ISD
::
ATOMIC_SWAP
:
case
ISD
::
ATOMIC_CMP_SWAP
:
case
ISD
::
ATOMIC_LOAD_MIN
:
case
ISD
::
ATOMIC_LOAD_UMIN
:
case
ISD
::
ATOMIC_LOAD_MAX
:
case
ISD
::
ATOMIC_LOAD_UMAX
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
)
;
return
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> VETargetMachine :: VETargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( createTLOF ( ) ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo ( ) ; } </s>

Create an Aurora VE architecture model .


<s> static bool sparc_mode_dependent_address_p ( const_rtx addr , addr_space_t as ATTRIBUTE_UNUSED ) { if ( flag_pic && GET_CODE ( addr ) == PLUS ) { rtx op0 = XEXP ( addr , 0 ) ; rtx op1 = XEXP ( addr , 1 ) ; if ( op0 == pic_offset_table_rtx && symbolic_operand ( op1 , VOIDmode ) ) return true ; } return false ; } </s>

Return true if ADDR ( a legitimate address expression ) has an effect that depends on the machine mode it is used for . In PIC mode , ( mem : HI [ % l7+a ] ) is not equivalent to ( mem : QI [ % l7+a ] ) ( mem : QI [ % l7+a+1 ] ) because [ % l7+a+1 ] is interpreted as the address of ( a+1 ) .


<s> static void aarch64_pop_regs ( unsigned regno1 , unsigned regno2 , HOST_WIDE_INT adjustment , rtx * cfi_ops ) { machine_mode mode = aarch64_reg_save_mode ( cfun -> decl , regno1 ) ; rtx reg1 = gen_rtx_REG ( mode , regno1 ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg1 , * cfi_ops ) ; if ( regno2 == INVALID_REGNUM ) { rtx mem = plus_constant ( Pmode , stack_pointer_rtx , adjustment ) ; mem = gen_rtx_POST_MODIFY ( Pmode , stack_pointer_rtx , mem ) ; emit_move_insn ( reg1 , gen_frame_mem ( mode , mem ) ) ; } else { rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg2 , * cfi_ops ) ; emit_insn ( aarch64_gen_loadwb_pair ( mode , stack_pointer_rtx , reg1 , reg2 , adjustment ) ) ; } } </s>

Pop the two registers numbered REGNO1 , REGNO2 from the stack , adjusting it afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes into CFI_OPS .


<s> bool PatmosInstrInfo :: findCommutedOpIndices ( const MachineInstr & MI , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { unsigned op1 , op2 ; switch ( MI . getOpcode ( ) ) { case Patmos :: ADDr : case Patmos :: ADDr_ow : case Patmos :: ORr : case Patmos :: ORr_ow : case Patmos :: ANDr : case Patmos :: ANDr_ow : case Patmos :: XORr : case Patmos :: XORr_ow : case Patmos :: NORr : case Patmos :: NORr_ow : op1 = 3 ; op2 = 4 ; break ; case Patmos :: MUL : case Patmos :: MULU : op1 = 2 ; op2 = 3 ; break ; default : return false ; } if ( ! fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , op1 , op2 ) || ! MI . getOperand ( SrcOpIdx1 ) . isReg ( ) || ! MI . getOperand ( SrcOpIdx2 ) . isReg ( ) ) { return false ; } return true ; } </s>

Returns true iff the routine could find two commutable operands in the given machine instruction .


<s> static void mips_set_frame_expr ( rtx frame_pattern ) { rtx insn ; insn = get_last_insn ( ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = alloc_EXPR_LIST ( REG_FRAME_RELATED_EXPR , frame_pattern , REG_NOTES ( insn ) ) ; } </s>

Make the last instruction frame related and note that it performs the operation described by FRAME_PATTERN .


<s> unsigned PPCAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { int64_t ImmVal ; switch ( Kind ) { case MCK_0 : ImmVal = 0 ; break ; case MCK_1 : ImmVal = 1 ; break ; case MCK_2 : ImmVal = 2 ; break ; case MCK_3 : ImmVal = 3 ; break ; case MCK_4 : ImmVal = 4 ; break ; case MCK_5 : ImmVal = 5 ; break ; case MCK_6 : ImmVal = 6 ; break ; case MCK_7 : ImmVal = 7 ; break ; default : return Match_InvalidOperand ; } PPCOperand & Op = static_cast < PPCOperand & > ( AsmOp ) ; if ( Op . isU3Imm ( ) && Op . getImm ( ) == ImmVal ) return Match_Success ; return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> static int thumb1_extra_regs_pushed ( arm_stack_offsets * offsets , bool for_prologue ) { HOST_WIDE_INT amount ; unsigned long live_regs_mask = offsets -> saved_regs_mask ; unsigned long l_mask = live_regs_mask & ( for_prologue ? 0x40ff : 0xff ) ; unsigned long high_regs_pushed = bit_count ( live_regs_mask & 0x0f00 ) ; int n_free , reg_base , size ; if ( ! for_prologue && frame_pointer_needed ) amount = offsets -> locals_base - offsets -> saved_regs ; else amount = offsets -> outgoing_args - offsets -> saved_regs ; if ( ! optimize_size && amount != 512 ) return 0 ; if ( high_regs_pushed != 0 ) return 0 ; if ( l_mask == 0 && ( for_prologue || TARGET_BACKTRACE || ( live_regs_mask & 1 << LR_REGNUM ) == 0 || TARGET_INTERWORK || crtl -> args . pretend_args_size != 0 ) ) return 0 ; if ( for_prologue && ( ( flag_pic && arm_pic_register != INVALID_REGNUM ) || ( ! frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0 ) ) ) return 0 ; reg_base = 0 ; n_free = 0 ; if ( ! for_prologue ) { size = arm_size_return_regs ( ) ; reg_base = ARM_NUM_INTS ( size ) ; live_regs_mask >>= reg_base ; } while ( reg_base + n_free < 8 && ! ( live_regs_mask & 1 ) && ( for_prologue || call_used_or_fixed_reg_p ( reg_base + n_free ) ) ) { live_regs_mask >>= 1 ; n_free ++ ; } if ( n_free == 0 ) return 0 ; gcc_assert ( amount / 4 * 4 == amount ) ; if ( amount >= 512 && ( amount - n_free * 4 ) < 512 ) return ( amount - 508 ) / 4 ; if ( amount <= n_free * 4 ) return amount / 4 ; return 0 ; } </s>

Given the stack offsets and register mask in OFFSETS , decide how many additional registers to push instead of subtracting a constant from SP . For epilogues the principle is the same except we use pop . FOR_PROLOGUE indicates which we 're generating .


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool is64bit ) : LLVMTargetMachine ( T , computeDataLayout ( TT , is64bit ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffectiveSparcCodeModel ( CM , getEffectiveRelocModel ( RM ) , is64bit , JIT ) , OL ) , TLOF ( make_unique < SparcELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this , is64bit ) , is64Bit ( is64bit ) { initAsmInfo ( ) ; } </s>


<s> static void riscv_emit_int_order_test ( enum rtx_code code , bool * invert_ptr , rtx target , rtx cmp0 , rtx cmp1 ) { enum machine_mode mode ; mode = GET_MODE ( cmp0 ) ; if ( riscv_canonicalize_int_order_test ( & code , & cmp1 , mode ) ) riscv_emit_binary ( code , target , cmp0 , cmp1 ) ; else { enum rtx_code inv_code = reverse_condition ( code ) ; if ( ! riscv_canonicalize_int_order_test ( & inv_code , & cmp1 , mode ) ) { cmp1 = force_reg ( mode , cmp1 ) ; riscv_emit_int_order_test ( code , invert_ptr , target , cmp0 , cmp1 ) ; } else if ( invert_ptr == 0 ) { rtx inv_target = riscv_force_binary ( GET_MODE ( target ) , inv_code , cmp0 , cmp1 ) ; riscv_emit_binary ( XOR , target , inv_target , const1_rtx ) ; } else { * invert_ptr = ! * invert_ptr ; riscv_emit_binary ( inv_code , target , cmp0 , cmp1 ) ; } } } </s>

Compare CMP0 and CMP1 using ordering test CODE and store the result in TARGET . CMP0 and TARGET are register_operands . If INVERT_PTR is nonnull , it 's OK to set TARGET to the inverse of the result and flip * INVERT_PTR instead .


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( TM ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static bool m32r_pass_by_reference ( cumulative_args_t ca ATTRIBUTE_UNUSED , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { int size ; if ( type ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; return ( size < 0 || size > 8 ) ; } </s>

Return nonzero if TYPE must be passed by indirect reference .


<s>
bool
processBlock
(
MachineBasicBlock
&
MBB
)
{
bool
Changed
=
false
;
bool
Is64Bit
=
MBB
.
getParent
(
)
->
getSubtarget
<
PPCSubtarget
>
(
)
.
isPPC64
(
)
;
for
(
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
,
IE
=
MBB
.
end
(
)
;
I
!=
IE
;
)
{
MachineInstr
&
MI
=
*
I
;
if
(
MI
.
getOpcode
(
)
!=
PPC
::
ADDItlsgdLADDR
&&
MI
.
getOpcode
(
)
!=
PPC
::
ADDItlsldLADDR
&&
MI
.
getOpcode
(
)
!=
PPC
::
ADDItlsgdLADDR32
&&
MI
.
getOpcode
(
)
!=
PPC
::
ADDItlsldLADDR32
)
{
++
I
;
continue
;
}
DEBUG
(
dbgs
(
)
<<
"TLS Dynamic Call Fixup:\n    "
<<
MI
)
;
unsigned
OutReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
unsigned
InReg
=
MI
.
getOperand
(
1
)
.
getReg
(
)
;
DebugLoc
DL
=
MI
.
getDebugLoc
(
)
;
unsigned
GPR3
=
Is64Bit
PPC
::
X3
:
PPC
::
R3
;
unsigned
Opc1
,
Opc2
;
const
unsigned
OrigRegs
[
]
=
{
OutReg
,
InReg
,
GPR3
}
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Opcode inconsistency error"
)
;
case
PPC
::
ADDItlsgdLADDR
:
Opc1
=
PPC
::
ADDItlsgdL
;
Opc2
=
PPC
::
GETtlsADDR
;
break
;
case
PPC
::
ADDItlsldLADDR
:
Opc1
=
PPC
::
ADDItlsldL
;
Opc2
=
PPC
::
GETtlsldADDR
;
break
;
case
PPC
::
ADDItlsgdLADDR32
:
Opc1
=
PPC
::
ADDItlsgdL32
;
Opc2
=
PPC
::
GETtlsADDR32
;
break
;
case
PPC
::
ADDItlsldLADDR32
:
Opc1
=
PPC
::
ADDItlsldL32
;
Opc2
=
PPC
::
GETtlsldADDR32
;
break
;
}
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
PPC
::
ADJCALLSTACKDOWN
)
)
.
addImm
(
0
)
.
addImm
(
0
)
;
MachineInstr
*
Addi
=
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
Opc1
)
,
GPR3
)
.
addReg
(
InReg
)
;
Addi
->
addOperand
(
MI
.
getOperand
(
2
)
)
;
MachineBasicBlock
::
iterator
First
=
I
;
First
;
MachineInstr
*
Call
=
(
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
Opc2
)
,
GPR3
)
.
addReg
(
GPR3
)
)
;
Call
->
addOperand
(
MI
.
getOperand
(
3
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
PPC
::
ADJCALLSTACKUP
)
)
.
addImm
(
0
)
.
addImm
(
0
)
;
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
TargetOpcode
::
COPY
)
,
OutReg
)
.
addReg
(
GPR3
)
;
MachineBasicBlock
::
iterator
Last
=
I
;
Last
;
++
I
;
MI
.
removeFromParent
(
)
;
LIS
->
repairIntervalsInRange
(
&
MBB
,
First
,
Last
,
OrigRegs
)
;
Changed
=
true
;
}
return
Changed
;
}
</s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s> void ARMPassConfig :: addPreEmitPass ( ) { addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( createUnpackMachineBundles ( [ ] ( const MachineFunction & MF ) { return MF . getSubtarget < ARMSubtarget > ( ) . isThumb2 ( ) ; } ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createARMBlockPlacementPass ( ) ) ; addPass ( createARMOptimizeBarriersPass ( ) ) ; } } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static machine_mode ix86_cc_modes_compatible ( machine_mode m1 , machine_mode m2 ) { if ( m1 == m2 ) return m1 ; if ( GET_MODE_CLASS ( m1 ) != MODE_CC || GET_MODE_CLASS ( m2 ) != MODE_CC ) return VOIDmode ; if ( ( m1 == CCGCmode && m2 == CCGOCmode ) || ( m1 == CCGOCmode && m2 == CCGCmode ) ) return CCGCmode ; if ( m1 == CCZmode && ( m2 == CCGCmode || m2 == CCGOCmode ) ) return m2 ; else if ( m2 == CCZmode && ( m1 == CCGCmode || m1 == CCGOCmode ) ) return m1 ; switch ( m1 ) { default : gcc_unreachable ( ) ; case CCmode : case CCGCmode : case CCGOCmode : case CCNOmode : case CCAmode : case CCCmode : case CCOmode : case CCPmode : case CCSmode : case CCZmode : switch ( m2 ) { default : return VOIDmode ; case CCmode : case CCGCmode : case CCGOCmode : case CCNOmode : case CCAmode : case CCCmode : case CCOmode : case CCPmode : case CCSmode : case CCZmode : return CCmode ; } case CCFPmode : case CCFPUmode : return VOIDmode ; } } </s>

If two condition code modes are compatible , return a condition code mode which is compatible with both . Otherwise , return VOIDmode .


<s> static rtx aarch64_progress_pointer ( rtx pointer ) { return aarch64_move_pointer ( pointer , GET_MODE_SIZE ( GET_MODE ( pointer ) ) ) ; } </s>

Return a new RTX holding the result of moving POINTER forward by the size of the mode it points to .


<s> SDValue XCoreTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_XCore ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


"Do not know how to lower this BUILD_VECTOR"

Main hook for targets to transform nodes into machine nodes .


<s> bool GCNPassConfig :: addPreISel ( ) { AMDGPUPassConfig :: addPreISel ( ) ; addPass ( createAMDGPUAnnotateKernelFeaturesPass ( ) ) ; addPass ( & AMDGPUUnifyDivergentExitNodesID ) ; if ( ! LateCFGStructurize ) { addPass ( createStructurizeCFGPass ( true ) ) ; } addPass ( createSinkingPass ( ) ) ; addPass ( createAMDGPUAnnotateUniformValues ( ) ) ; if ( ! LateCFGStructurize ) { addPass ( createSIAnnotateControlFlowPass ( ) ) ; } return false ; } </s>


<s> const char * AMDGPUTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; NODE_NAME_CASE ( CALL ) ; NODE_NAME_CASE ( UMUL ) ; NODE_NAME_CASE ( DIV_INF ) ; NODE_NAME_CASE ( RET_FLAG ) ; NODE_NAME_CASE ( BRANCH_COND ) ; NODE_NAME_CASE ( DWORDADDR ) NODE_NAME_CASE ( FRACT ) NODE_NAME_CASE ( FMAX ) NODE_NAME_CASE ( SMAX ) NODE_NAME_CASE ( UMAX ) NODE_NAME_CASE ( FMIN ) NODE_NAME_CASE ( SMIN ) NODE_NAME_CASE ( UMIN ) NODE_NAME_CASE ( BFE_U32 ) NODE_NAME_CASE ( BFE_I32 ) NODE_NAME_CASE ( URECIP ) NODE_NAME_CASE ( DOT4 ) NODE_NAME_CASE ( EXPORT ) NODE_NAME_CASE ( CONST_ADDRESS ) NODE_NAME_CASE ( REGISTER_LOAD ) NODE_NAME_CASE ( REGISTER_STORE ) NODE_NAME_CASE ( LOAD_CONSTANT ) NODE_NAME_CASE ( LOAD_INPUT ) NODE_NAME_CASE ( SAMPLE ) NODE_NAME_CASE ( SAMPLEB ) NODE_NAME_CASE ( SAMPLED ) NODE_NAME_CASE ( SAMPLEL ) NODE_NAME_CASE ( STORE_MSKOR ) NODE_NAME_CASE ( TBUFFER_STORE_FORMAT ) } } </s>

getTargetNodeName - This method returns the name of a target specific


<s>
static
void
process_cfa_register
(
FILE
*
out_file
,
rtx
pat
,
bool
unwind
)
{
rtx
dest
=
SET_DEST
(
pat
)
;
rtx
src
=
SET_SRC
(
pat
)
;
int
dest_regno
=
REGNO
(
dest
)
;
int
src_regno
;
if
(
src
==
pc_rtx
)
{
if
(
unwind
)
fprintf
(
out_file
,
"\t.save rp, r%d\n"
,
ia64_dbx_register_number
(
dest_regno
)
)
;
return
;
}
src_regno
=
REGNO
(
src
)
;
switch
(
src_regno
)
{
case
PR_REG
(
0
)
:
gcc_assert
(
dest_regno
==
current_frame_info
.
r
[
reg_save_pr
]
)
;
if
(
unwind
)
fprintf
(
out_file
,
"\t.save pr, r%d\n"
,
ia64_dbx_register_number
(
dest_regno
)
)
;
break
;
case
AR_UNAT_REGNUM
:
gcc_assert
(
dest_regno
==
current_frame_info
.
r
[
reg_save_ar_unat
]
)
;
if
(
unwind
)
fprintf
(
out_file
,
"\t.save ar.unat, r%d\n"
,
ia64_dbx_register_number
(
dest_regno
)
)
;
break
;
case
AR_LC_REGNUM
:
gcc_assert
(
dest_regno
==
current_frame_info
.
r
[
reg_save_ar_lc
]
)
;
if
(
unwind
)
fprintf
(
out_file
,
"\t.save ar.lc, r%d\n"
,
ia64_dbx_register_number
(
dest_regno
)
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
</s>

This function processes a SET pattern for REG_CFA_REGISTER .

ia64
"\t.save rp, r%d\n"
0
"\t.save pr, r%d\n"
"\t.save ar.unat, r%d\n"
"\t.save ar.lc, r%d\n"


<s> void X86FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { const Function * Fn = MF . getFunction ( ) ; if ( ! STI . is64Bit ( ) || ! Fn -> hasPersonalityFn ( ) || classifyEHPersonality ( MF . getFunction ( ) -> getPersonalityFn ( ) ) != EHPersonality :: MSVC_CXX ) return ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int64_t MinFixedObjOffset = 0 ; for ( int I = MFI -> getObjectIndexBegin ( ) ; I < 0 ; ++ I ) MinFixedObjOffset = std :: min ( MinFixedObjOffset , MFI -> getObjectOffset ( I ) ) ; int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize ; int UnwindHelpFI = MFI -> CreateFixedObject ( SlotSize , UnwindHelpOffset , false ) ; MF . getMMI ( ) . getWinEHFuncInfo ( Fn ) . UnwindHelpFrameIdx = UnwindHelpFI ; MachineBasicBlock & MBB = MF . front ( ) ; auto MBBI = MBB . begin ( ) ; while ( MBBI != MBB . end ( ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) ) ++ MBBI ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; addFrameReference ( BuildMI ( MBB , MBBI , DL , TII . get ( X86 :: MOV64mi32 ) ) , UnwindHelpFI ) . addImm ( - 2 ) ; } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> unsigned MCS51InstrInfo :: insertIndirectBranch ( MachineBasicBlock & MBB , MachineBasicBlock & NewDestBB , const DebugLoc & DL , int64_t BrOffset , RegScavenger * RS ) const { auto & MI = * BuildMI ( & MBB , DL , get ( MCS51 :: JMPk ) ) . addMBB ( & NewDestBB ) ; return getInstSizeInBytes ( MI ) ; } </s>

Insert an unconditional indirect branch at the end of MBB to NewDestBB .


<s> bool isKMasked ( ) const { return ( Attributes & ( KMergeMasked | KZeroMasked ) ) != 0 ; } </s>

Returns true iff the group of FMA opcodes holds any of k-masked opcodes .


<s> rtx legitimize_address ( rtx x ATTRIBUTE_UNUSED , rtx oldx ATTRIBUTE_UNUSED , enum machine_mode mode ATTRIBUTE_UNUSED ) { return NULL_RTX ; } </s>

Try machine-dependent ways of modifying an illegitimate address X to be legitimate . If we find one , return the new , valid address . OLDX is the address as it was before break_out_memory_refs was called . In some cases it is useful to look at this to decide what needs to be done . MODE is the mode of the operand pointed to by X .


<s> static bool s390_legitimate_address_p ( machine_mode mode , rtx addr , bool strict ) { struct s390_address ad ; if ( TARGET_Z10 && larl_operand ( addr , VOIDmode ) && ( mode == VOIDmode || s390_check_symref_alignment ( addr , GET_MODE_SIZE ( mode ) ) ) ) return true ; if ( ! s390_decompose_address ( addr , & ad ) ) return false ; if ( strict ) { if ( ad . base && ! REGNO_OK_FOR_BASE_P ( REGNO ( ad . base ) ) ) return false ; if ( ad . indx && ! REGNO_OK_FOR_INDEX_P ( REGNO ( ad . indx ) ) ) return false ; } else { if ( ad . base && ! ( REGNO ( ad . base ) >= FIRST_PSEUDO_REGISTER || REGNO_REG_CLASS ( REGNO ( ad . base ) ) == ADDR_REGS ) ) return false ; if ( ad . indx && ! ( REGNO ( ad . indx ) >= FIRST_PSEUDO_REGISTER || REGNO_REG_CLASS ( REGNO ( ad . indx ) ) == ADDR_REGS ) ) return false ; } return true ; } </s>

Return true if ADDR is a valid memory address . STRICT specifies whether strict register checking applies .


<s> void MipsSEDAGToDAGISel :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < DominatorTreeWrapperPass > ( ) ; SelectionDAGISel :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool aarch64_split_128bit_move_p ( rtx dst , rtx src ) { return ( ! REG_P ( src ) || ! ( FP_REGNUM_P ( REGNO ( dst ) ) && FP_REGNUM_P ( REGNO ( src ) ) ) ) ; } </s>

Return true if we should split a move from 128-bit value SRC to 128-bit register DEST .


<s> ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const override { return createPatmosVLIWMachineSched ( C ) ; } </s>

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level .


<s> const TargetRegisterClass * X86RegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { if ( RC == & X86 :: GR8_NOREXRegClass ) return RC ; const X86Subtarget & Subtarget = MF . getSubtarget < X86Subtarget > ( ) ; const TargetRegisterClass * Super = RC ; TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case X86 :: FR32RegClassID : case X86 :: FR64RegClassID : if ( ! Subtarget . hasAVX512 ( ) && Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; break ; case X86 :: VR128RegClassID : case X86 :: VR256RegClassID : if ( ! Subtarget . hasVLX ( ) && Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; break ; case X86 :: FR32XRegClassID : case X86 :: FR64XRegClassID : if ( ! Subtarget . hasVLX ( ) ) break ; LLVM_FALLTHROUGH ; case X86 :: VR128XRegClassID : case X86 :: VR256XRegClassID : if ( ! Subtarget . hasAVX512 ( ) ) break ; LLVM_FALLTHROUGH ; case X86 :: GR8RegClassID : case X86 :: GR16RegClassID : case X86 :: GR32RegClassID : case X86 :: GR64RegClassID : case X86 :: RFP32RegClassID : case X86 :: RFP64RegClassID : case X86 :: RFP80RegClassID : case X86 :: VR512RegClassID : if ( Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; } Super = * I ++ ; } while ( Super ) ; return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .


<s> static rtx frv_volatile_memref ( enum machine_mode mode , rtx arg ) { rtx mem ; mem = gen_rtx_MEM ( mode , memory_address ( mode , arg ) ) ; MEM_VOLATILE_P ( mem ) = 1 ; return mem ; } </s>

Return a volatile memory reference of mode MODE whose address is ARG .


<s>
bool
AArch64InstrInfo
::
areMemAccessesTriviallyDisjoint
(
const
MachineInstr
&
MIa
,
const
MachineInstr
&
MIb
)
const
{
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
const
MachineOperand
*
BaseOpA
=
nullptr
,
*
BaseOpB
=
nullptr
;
int64_t
OffsetA
=
0
,
OffsetB
=
0
;
unsigned
WidthA
=
0
,
WidthB
=
0
;
bool
OffsetAIsScalable
=
false
,
OffsetBIsScalable
=
false
;
assert
(
MIa
.
mayLoadOrStore
(
)
&&
"MIa must be a load or store."
)
;
assert
(
MIb
.
mayLoadOrStore
(
)
&&
"MIb must be a load or store."
)
;
if
(
MIa
.
hasUnmodeledSideEffects
(
)
||
MIb
.
hasUnmodeledSideEffects
(
)
||
MIa
.
hasOrderedMemoryRef
(
)
||
MIb
.
hasOrderedMemoryRef
(
)
)
return
false
;
if
(
getMemOperandWithOffsetWidth
(
MIa
,
BaseOpA
,
OffsetA
,
OffsetAIsScalable
,
WidthA
,
TRI
)
&&
getMemOperandWithOffsetWidth
(
MIb
,
BaseOpB
,
OffsetB
,
OffsetBIsScalable
,
WidthB
,
TRI
)
)
{
if
(
BaseOpA
->
isIdenticalTo
(
*
BaseOpB
)
&&
OffsetAIsScalable
==
OffsetBIsScalable
)
{
int
LowOffset
=
OffsetA
<
OffsetB
OffsetA
:
OffsetB
;
int
HighOffset
=
OffsetA
<
OffsetB
OffsetB
:
OffsetA
;
int
LowWidth
=
(
LowOffset
==
OffsetA
)
WidthA
:
WidthB
;
if
(
LowOffset
+
LowWidth
<=
HighOffset
)
return
true
;
}
}
return
false
;
}
</s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s>
void
HexagonMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
MCInst
&
HMB
=
const_cast
<
MCInst
&
>
(
MI
)
;
assert
(
HexagonMCInstrInfo
::
isBundle
(
HMB
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Encoding bundle\n"
;
)
;
State
.
Addend
=
0
;
State
.
Extended
=
false
;
State
.
Bundle
=
&
MI
;
State
.
Index
=
0
;
size_t
Last
=
HexagonMCInstrInfo
::
bundleSize
(
HMB
)
1
;
FeatureBitset
Features
=
computeAvailableFeatures
(
STI
.
getFeatureBits
(
)
)
;
for
(
auto
&
I
:
HexagonMCInstrInfo
::
bundleInstructions
(
HMB
)
)
{
MCInst
&
HMI
=
const_cast
<
MCInst
&
>
(
*
I
.
getInst
(
)
)
;
verifyInstructionPredicates
(
HMI
,
Features
)
;
EncodeSingleInstruction
(
HMI
,
OS
,
Fixups
,
STI
,
parseBits
(
Last
,
HMB
,
HMI
)
)
;
State
.
Extended
=
HexagonMCInstrInfo
::
isImmext
(
HMI
)
;
State
.
Addend
+=
HEXAGON_INSTR_SIZE
;
++
State
.
Index
;
}
}
</s>

Encode the given Inst to bytes and append to CB .

Hexagon
Hexagon
Hexagon
"Encoding bundle\n"
0
0
Hexagon
1
Hexagon
Hexagon


<s> bool SIAnnotateControlFlow :: doInitialization ( Module & M ) { LLVMContext & Context = M . getContext ( ) ; Void = Type :: getVoidTy ( Context ) ; Boolean = Type :: getInt1Ty ( Context ) ; Int64 = Type :: getInt64Ty ( Context ) ; ReturnStruct = StructType :: get ( Boolean , Int64 , ( Type * ) nullptr ) ; BoolTrue = ConstantInt :: getTrue ( Context ) ; BoolFalse = ConstantInt :: getFalse ( Context ) ; BoolUndef = UndefValue :: get ( Boolean ) ; Int64Zero = ConstantInt :: get ( Int64 , 0 ) ; If = Intrinsic :: getDeclaration ( & M , Intrinsic :: amdgcn_if ) ; Else = Intrinsic :: getDeclaration ( & M , Intrinsic :: amdgcn_else ) ; Break = Intrinsic :: getDeclaration ( & M , Intrinsic :: amdgcn_break ) ; IfBreak = Intrinsic :: getDeclaration ( & M , Intrinsic :: amdgcn_if_break ) ; ElseBreak = Intrinsic :: getDeclaration ( & M , Intrinsic :: amdgcn_else_break ) ; Loop = Intrinsic :: getDeclaration ( & M , Intrinsic :: amdgcn_loop ) ; EndCf = Intrinsic :: getDeclaration ( & M , Intrinsic :: amdgcn_end_cf ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> inline hashval_t registered_function_hasher :: hash ( value_type value ) { return value -> instance . hash ( ) ; } </s>

Hash function for builtin functions with up to 3 arguments and a return type .


<s> SDValue VideocoreTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { return Chain ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s>
void
SPIRVMCInstLower
::
lower
(
const
MachineInstr
*
MI
,
MCInst
&
OutMI
,
SPIRV
::
ModuleAnalysisInfo
*
MAI
)
const
{
OutMI
.
setOpcode
(
MI
->
getOpcode
(
)
)
;
const
MachineFunction
*
MF
=
MI
->
getMF
(
)
;
for
(
unsigned
i
=
0
,
e
=
MI
->
getNumOperands
(
)
;
i
!=
e
;
++
i
)
{
const
MachineOperand
&
MO
=
MI
->
getOperand
(
i
)
;
MCOperand
MCOp
;
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_GlobalAddress
:
{
Register
FuncReg
=
MAI
->
getFuncReg
(
MO
.
getGlobal
(
)
->
getGlobalIdentifier
(
)
)
;
assert
(
FuncReg
.
isValid
(
)
&&
"Cannot find function Id"
)
;
MCOp
=
MCOperand
::
createReg
(
FuncReg
)
;
break
;
}
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
createReg
(
MAI
->
getOrCreateMBBRegister
(
*
MO
.
getMBB
(
)
)
)
;
break
;
case
MachineOperand
::
MO_Register
:
{
Register
NewReg
=
MAI
->
getRegisterAlias
(
MF
,
MO
.
getReg
(
)
)
;
MCOp
=
MCOperand
::
createReg
(
NewReg
.
isValid
(
)
NewReg
:
MO
.
getReg
(
)
)
;
break
;
}
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
createImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_FPImmediate
:
MCOp
=
MCOperand
::
createDFPImm
(
MO
.
getFPImm
(
)
->
getValueAPF
(
)
.
convertToFloat
(
)
)
;
break
;
}
OutMI
.
addOperand
(
MCOp
)
;
}
}
</s>

SPIRV
SPIRV
SPIRV::ModuleAnalysisInfo
0
"unknown operand type"
"Cannot find function Id"


<s> Register getExceptionSelectorRegister ( const Constant * PersonalityFn ) const override { return AArch64 :: X1 ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .