<s>
const
char
*
output_move_double
(
rtx
operands
[
]
,
rtx
insn
)
{
rtx
dest
=
operands
[
0
]
;
rtx
src
=
operands
[
1
]
;
enum
machine_mode
mode
=
GET_MODE
(
dest
)
;
if
(
GET_CODE
(
dest
)
==
REG
)
{
int
dest_regno
=
REGNO
(
dest
)
;
if
(
GPR_P
(
dest_regno
)
)
{
if
(
GET_CODE
(
src
)
==
REG
)
{
int
src_regno
=
REGNO
(
src
)
;
if
(
GPR_P
(
src_regno
)
)
return
"#"
;
else
if
(
FPR_P
(
src_regno
)
)
{
if
(
(
(
dest_regno
GPR_FIRST
)
&
1
)
==
0
&&
(
(
src_regno
FPR_FIRST
)
&
1
)
==
0
)
return
"movfgd %1, %0"
;
return
"#"
;
}
}
else
if
(
GET_CODE
(
src
)
==
MEM
)
{
if
(
dbl_memory_one_insn_operand
(
src
,
mode
)
)
return
"ldd%I1%U1 %M1, %0"
;
return
"#"
;
}
else
if
(
GET_CODE
(
src
)
==
CONST_INT
||
GET_CODE
(
src
)
==
CONST_DOUBLE
)
return
"#"
;
}
else
if
(
FPR_P
(
dest_regno
)
)
{
if
(
GET_CODE
(
src
)
==
REG
)
{
int
src_regno
=
REGNO
(
src
)
;
if
(
GPR_P
(
src_regno
)
)
{
if
(
(
(
dest_regno
FPR_FIRST
)
&
1
)
==
0
&&
(
(
src_regno
GPR_FIRST
)
&
1
)
==
0
)
return
"movgfd %1, %0"
;
return
"#"
;
}
else
if
(
FPR_P
(
src_regno
)
)
{
if
(
TARGET_DOUBLE
&&
(
(
dest_regno
FPR_FIRST
)
&
1
)
==
0
&&
(
(
src_regno
FPR_FIRST
)
&
1
)
==
0
)
return
"fmovd %1, %0"
;
return
"#"
;
}
}
else
if
(
GET_CODE
(
src
)
==
MEM
)
{
if
(
dbl_memory_one_insn_operand
(
src
,
mode
)
)
return
"lddf%I1%U1 %M1, %0"
;
return
"#"
;
}
else
if
(
ZERO_P
(
src
)
)
return
"#"
;
}
}
else
if
(
GET_CODE
(
dest
)
==
MEM
)
{
if
(
GET_CODE
(
src
)
==
REG
)
{
int
src_regno
=
REGNO
(
src
)
;
if
(
GPR_P
(
src_regno
)
)
{
if
(
(
(
src_regno
GPR_FIRST
)
&
1
)
==
0
&&
dbl_memory_one_insn_operand
(
dest
,
mode
)
)
return
"std%I0%U0 %1, %M0"
;
return
"#"
;
}
if
(
FPR_P
(
src_regno
)
)
{
if
(
(
(
src_regno
FPR_FIRST
)
&
1
)
==
0
&&
dbl_memory_one_insn_operand
(
dest
,
mode
)
)
return
"stdf%I0%U0 %1, %M0"
;
return
"#"
;
}
}
else
if
(
ZERO_P
(
src
)
)
{
if
(
dbl_memory_one_insn_operand
(
dest
,
mode
)
)
return
"std%I0%U0 %., %M0"
;
return
"#"
;
}
}
fatal_insn
(
"bad output_move_double operand"
,
insn
)
;
return
""
;
}
</s>

Return appropriate code to load up an 8 byte integer or floating point value


<s> void NVPTXTargetStreamer :: emitRawBytes ( StringRef Data ) { MCTargetStreamer :: emitRawBytes ( Data ) ; const MCAsmInfo * MAI = Streamer . getContext ( ) . getAsmInfo ( ) ; const char * Directive = MAI -> getData8bitsDirective ( ) ; unsigned NumElements = Data . size ( ) ; const unsigned MaxLen = 40 ; unsigned NumChunks = 1 + ( ( NumElements - 1 ) / MaxLen ) ; for ( unsigned I = 0 ; I < NumChunks ; ++ I ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; const char * Label = Directive ; for ( auto It = std :: next ( Data . bytes_begin ( ) , I * MaxLen ) , End = ( I == NumChunks - 1 ) ? Data . bytes_end ( ) : std :: next ( Data . bytes_begin ( ) , ( I + 1 ) * MaxLen ) ; It != End ; ++ It ) { OS << Label << ( unsigned ) * It ; if ( Label == Directive ) Label = "," ; } Streamer . EmitRawText ( OS . str ( ) ) ; } } </s>

Emit the bytes in Data into the output .


<s> static const char * detect_processor_freebsd ( void ) { return "powerpc" ; } </s>


<s> bool HexagonInstrInfo :: getBaseAndOffsetPosition ( const MachineInstr * MI , unsigned & BasePos , unsigned & OffsetPos ) const { if ( isMemOp ( MI ) ) { BasePos = 0 ; OffsetPos = 1 ; } else if ( MI -> mayStore ( ) ) { BasePos = 0 ; OffsetPos = 1 ; } else if ( MI -> mayLoad ( ) ) { BasePos = 1 ; OffsetPos = 2 ; } else return false ; if ( isPredicated ( * MI ) ) { BasePos ++ ; OffsetPos ++ ; } if ( isPostIncrement ( MI ) ) { BasePos ++ ; OffsetPos ++ ; } if ( ! MI -> getOperand ( BasePos ) . isReg ( ) || ! MI -> getOperand ( OffsetPos ) . isImm ( ) ) return false ; return true ; } </s>

Return true if the instruction contains a base register and offset .


<s> bool ARMFastISel :: fastLowerArguments ( ) { if ( ! FuncInfo . CanLowerReturn ) return false ; const Function * F = FuncInfo . Fn ; if ( F -> isVarArg ( ) ) return false ; CallingConv :: ID CC = F -> getCallingConv ( ) ; switch ( CC ) { default : return false ; case CallingConv :: Fast : case CallingConv :: C : case CallingConv :: ARM_AAPCS_VFP : case CallingConv :: ARM_AAPCS : case CallingConv :: ARM_APCS : case CallingConv :: Swift : break ; } for ( const Argument & Arg : F -> args ( ) ) { if ( Arg . getArgNo ( ) >= 4 ) return false ; if ( Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: ByVal ) ) return false ; Type * ArgTy = Arg . getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( DL , ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : break ; default : return false ; } } static const MCPhysReg GPRArgRegs [ ] = { ARM :: R0 , ARM :: R1 , ARM :: R2 , ARM :: R3 } ; const TargetRegisterClass * RC = & ARM :: rGPRRegClass ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I ) { unsigned ArgNo = I -> getArgNo ( ) ; unsigned SrcReg = GPRArgRegs [ ArgNo ] ; unsigned DstReg = FuncInfo . MF -> addLiveIn ( SrcReg , RC ) ; unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( DstReg , getKillRegState ( true ) ) ; updateValueMap ( & * I , ResultReg ) ; } return true ; } </s>

This method is called by target-independent code to do target- specific argument lowering .


<s> rtx spu_gen_subreg ( machine_mode mode , rtx x ) { if ( GET_CODE ( x ) == SUBREG ) x = SUBREG_REG ( x ) ; if ( GET_MODE ( x ) == mode ) return x ; return gen_rtx_SUBREG ( mode , x , 0 ) ; } </s>

Make a subreg , stripping any existing subreg . We could possibly just call simplify_subreg , but in this case we know what we want .


"switch %<-mcustom-%s%> is required for double "

"switch %<-mcustom-%s%> has no effect unless "

"conflicting use of -mcustom switches, target attributes, "

Check and signal some warnings/errors on FPU insn options .


<s> const SystemZSubtarget * SystemZTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool softFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsBool ( ) ; if ( softFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < SystemZSubtarget > ( TargetTriple , CPU , FS , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

SystemZ SystemZ SystemZ "target-cpu" "target-features" "use-soft-float" "+soft-float" ",+soft-float" SystemZ


<s> static type_suffix_index find_type_suffix_for_scalar_type ( const_tree type ) { for ( unsigned int suffix_i = 0 ; suffix_i < NUM_TYPE_SUFFIXES ; ++ suffix_i ) if ( ! type_suffixes [ suffix_i ] . bool_p ) { vector_type_index vector_i = type_suffixes [ suffix_i ] . vector_type ; if ( matches_type_p ( scalar_types [ vector_i ] , type ) ) return type_suffix_index ( suffix_i ) ; } return NUM_TYPE_SUFFIXES ; } </s>

If TYPE is a valid SVE element type , return the corresponding type suffix , otherwise return NUM_TYPE_SUFFIXES .


<s> void Thumb1RegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , unsigned PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: tLDRpci ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s>
void
WebAssemblyDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
EVT
VT
=
Node
->
getValueType
(
0
)
;
switch
(
Node
->
getOpcode
(
)
)
{
default
:
break
;
(
void
)
VT
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> bool TL45PassConfig :: addInstSelector ( ) { addPass ( createTL45ISelDag ( getTL45TargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> unsigned BlackfinRegisterInfo :: getFrameRegister ( MachineFunction & MF ) const { return hasFP ( MF ) ? BF :: FP : BF :: SP ; } </s>


<s> void or1k_expand_compare ( rtx * operands ) { rtx sr_f = gen_rtx_REG ( BImode , SR_F_REGNUM ) ; if ( ! TARGET_SFIMM ) XEXP ( operands [ 0 ] , 1 ) = force_reg ( SImode , XEXP ( operands [ 0 ] , 1 ) ) ; PUT_MODE ( operands [ 0 ] , BImode ) ; emit_insn ( gen_rtx_SET ( sr_f , operands [ 0 ] ) ) ; operands [ 0 ] = gen_rtx_NE ( VOIDmode , sr_f , const0_rtx ) ; operands [ 1 ] = sr_f ; operands [ 2 ] = const0_rtx ; } </s>

Used to expand patterns `` movsicc '' , `` movqicc '' , `` movhicc '' , `` cstoresi4 '' and `` cbranchsi4 '' . Expands a comparison where OPERANDS is an array of RTX describing the comparison . The first argument OPERANDS [ 0 ] is the operator and OPERANDS [ 1 ] and OPERANDS [ 2 ] are the operands . Split out the compare into SR [ F ] and return a new operation in OPERANDS [ 0 ] . The inputs OPERANDS [ 1 ] and OPERANDS [ 2 ] are not directly used , only overridden .


<s> int microblaze_is_interrupt_variant ( void ) { return ( interrupt_handler || fast_interrupt ) ; } </s>

Return whether function is tagged with 'interrupt_handler ' or 'fast_interrupt ' attribute . Return true if function should use return from interrupt rather than normal function return .


<s> static int find_r0_life_regions ( basic_block b ) { bool live ; int set ; int death = 0 ; if ( REGNO_REG_SET_P ( df_get_live_in ( b ) , R0_REG ) ) { set = 1 ; live = true ; } else { set = 0 ; live = false ; } rtx_insn * insn = BB_HEAD ( b ) ; rtx_insn * end = BB_END ( b ) ; rtx r0_reg = gen_rtx_REG ( SImode , R0_REG ) ; while ( 1 ) { if ( INSN_P ( insn ) ) { if ( find_regno_note ( insn , REG_DEAD , R0_REG ) ) { death ++ ; live = false ; } rtx pset ; if ( ! live && ( pset = single_set ( insn ) ) && reg_overlap_mentioned_p ( r0_reg , SET_DEST ( pset ) ) && ! find_regno_note ( insn , REG_UNUSED , R0_REG ) ) { set ++ ; live = true ; } } if ( insn == end ) break ; insn = NEXT_INSN ( insn ) ; } return set - death ; } </s>


<s> static void rs6000_split_logical_inner ( rtx dest , rtx op1 , rtx op2 , enum rtx_code code , machine_mode mode , bool complement_final_p , bool complement_op1_p , bool complement_op2_p ) { rtx bool_rtx ; if ( op2 && GET_CODE ( op2 ) == CONST_INT && ( mode == SImode || ( mode == DImode && TARGET_POWERPC64 ) ) && ! complement_final_p && ! complement_op1_p && ! complement_op2_p ) { HOST_WIDE_INT mask = GET_MODE_MASK ( mode ) ; HOST_WIDE_INT value = INTVAL ( op2 ) & mask ; if ( code == AND ) { if ( value == 0 ) { emit_insn ( gen_rtx_SET ( dest , const0_rtx ) ) ; return ; } else if ( value == mask ) { if ( ! rtx_equal_p ( dest , op1 ) ) emit_insn ( gen_rtx_SET ( dest , op1 ) ) ; return ; } } else if ( code == IOR || code == XOR ) { if ( value == 0 ) { if ( ! rtx_equal_p ( dest , op1 ) ) emit_insn ( gen_rtx_SET ( dest , op1 ) ) ; return ; } } } if ( code == AND && mode == SImode && ! complement_final_p && ! complement_op1_p && ! complement_op2_p ) { emit_insn ( gen_andsi3 ( dest , op1 , op2 ) ) ; return ; } if ( complement_op1_p ) op1 = gen_rtx_NOT ( mode , op1 ) ; if ( complement_op2_p ) op2 = gen_rtx_NOT ( mode , op2 ) ; if ( ! complement_op1_p && complement_op2_p ) std :: swap ( op1 , op2 ) ; bool_rtx = ( ( code == NOT ) ? gen_rtx_NOT ( mode , op1 ) : gen_rtx_fmt_ee ( code , mode , op1 , op2 ) ) ; if ( complement_final_p ) bool_rtx = gen_rtx_NOT ( mode , bool_rtx ) ; emit_insn ( gen_rtx_SET ( dest , bool_rtx ) ) ; } </s>

Helper function for rs6000_split_logical to emit a logical instruction after spliting the operation to single GPR registers . DEST is the destination register . OP1 and OP2 are the input source registers . CODE is the base operation ( AND , IOR , XOR , NOT ) . MODE is the machine mode . If COMPLEMENT_FINAL_P is true , wrap the whole operation with NOT . If COMPLEMENT_OP1_P is true , wrap operand1 with NOT . If COMPLEMENT_OP2_P is true , wrap operand2 with NOT .


<s> static RegDomain getDomain ( const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) { if ( isGPR ( RC ) ) return GPRDomain ; if ( isMask ( RC , TRI ) ) return MaskDomain ; return OtherDomain ; } </s>

Get the MDNode for this AliasScopeNode 's domain .


<s> int pdp11_initial_elimination_offset ( int from , int to ) { if ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) return get_frame_size ( ) ; else if ( from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM ) return pdp11_reg_save_size ( ) + 2 ; else if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) return pdp11_reg_save_size ( ) + 2 + get_frame_size ( ) ; else gcc_assert ( 0 ) ; } </s>

Return the offset between two registers , one to be eliminated , and the other its replacement , at the start of a routine .


<s>
SDValue
BPFTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
unsigned
Opc
=
BPFISD
::
RET_FLAG
;
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
MF
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
if
(
MF
.
getFunction
(
)
->
getReturnType
(
)
->
isAggregateType
(
)
)
{
fail
(
DL
,
DAG
,
"only integer returns supported"
)
;
return
DAG
.
getNode
(
Opc
,
DL
,
MVT
::
Other
,
Chain
)
;
}
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_BPF64
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
Opc
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s>
unsigned
getReg
(
)
const
override
{
if
(
Kind
==
k_RegisterIndex
&&
RegIdx
.
Index
==
0
&&
RegIdx
.
Kind
&
RegKind_GPR
)
return
getGPR32Reg
(
)
;
assert
(
Kind
==
k_PhysRegister
&&
"Invalid access!"
)
;
return
PhysReg
.
Num
;
}
</s>

Returns the register associated with this edge .


<s> void GCNMaxOccupancySchedStrategy :: initialize ( ScheduleDAGMI * DAG ) { GenericScheduler :: initialize ( DAG ) ; const SIRegisterInfo * SRI = static_cast < const SIRegisterInfo * > ( TRI ) ; const int ErrorMargin = 3 ; SGPRExcessLimit = Context -> RegClassInfo -> getNumAllocatableRegs ( & AMDGPU :: SGPR_32RegClass ) - ErrorMargin ; VGPRExcessLimit = Context -> RegClassInfo -> getNumAllocatableRegs ( & AMDGPU :: VGPR_32RegClass ) - ErrorMargin ; SGPRCriticalLimit = SRI -> getRegPressureSetLimit ( DAG -> MF , SRI -> getSGPRPressureSet ( ) ) - ErrorMargin ; VGPRCriticalLimit = SRI -> getRegPressureSetLimit ( DAG -> MF , SRI -> getVGPRPressureSet ( ) ) - ErrorMargin ; } </s>

Initialize the strategy after building the DAG for a new region .


<s> void SparcPassConfig :: addPreEmitPass ( ) { addPass ( createSparcDelaySlotFillerPass ( ) ) ; if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> insertNOPLoad ( ) ) { addPass ( new InsertNOPLoad ( ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> detectRoundChange ( ) ) { addPass ( new DetectRoundChange ( ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> fixAllFDIVSQRT ( ) ) { addPass ( new FixAllFDIVSQRT ( ) ) ; } } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
void
X86ATTInstPrinter
::
printPCRelImm
(
const
MCInst
*
MI
,
unsigned
OpNo
,
raw_ostream
&
O
)
{
const
MCOperand
&
Op
=
MI
->
getOperand
(
OpNo
)
;
if
(
Op
.
isImm
(
)
)
O
<<
Op
.
getImm
(
)
;
else
{
assert
(
Op
.
isExpr
(
)
&&
"unknown pcrel immediate operand"
)
;
const
MCConstantExpr
*
BranchTarget
=
dyn_cast
<
MCConstantExpr
>
(
Op
.
getExpr
(
)
)
;
int64_t
Address
;
if
(
BranchTarget
&&
BranchTarget
->
EvaluateAsAbsolute
(
Address
)
)
{
O
<<
"0x"
;
O
.
write_hex
(
Address
)
;
}
else
{
O
<<
*
Op
.
getExpr
(
)
;
}
}
}
</s>


<s> static bool c4x_rtx_costs ( rtx x , int code , int outer_code , int * total ) { HOST_WIDE_INT val ; switch ( code ) { case CONST_INT : val = INTVAL ( x ) ; if ( c4x_J_constant ( x ) ) * total = 0 ; else if ( ! TARGET_C3X && outer_code == AND && ( val == 255 || val == 65535 ) ) * total = 0 ; else if ( ! TARGET_C3X && ( outer_code == ASHIFTRT || outer_code == LSHIFTRT ) && ( val == 16 || val == 24 ) ) * total = 0 ; else if ( TARGET_C3X && SHIFT_CODE_P ( outer_code ) ) * total = 3 ; else if ( LOGICAL_CODE_P ( outer_code ) ? c4x_L_constant ( x ) : c4x_I_constant ( x ) ) * total = 2 ; else * total = 4 ; return true ; case CONST : case LABEL_REF : case SYMBOL_REF : * total = 4 ; return true ; case CONST_DOUBLE : if ( c4x_H_constant ( x ) ) * total = 2 ; else if ( GET_MODE ( x ) == QFmode ) * total = 4 ; else * total = 8 ; return true ; case PLUS : case MINUS : case AND : case IOR : case XOR : case ASHIFT : case ASHIFTRT : case LSHIFTRT : * total = COSTS_N_INSNS ( 1 ) ; return true ; case MULT : * total = COSTS_N_INSNS ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT || TARGET_MPYI ? 1 : 14 ) ; return true ; case DIV : case UDIV : case MOD : case UMOD : * total = COSTS_N_INSNS ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ? 15 : 50 ) ; return true ; default : return false ; } } </s>

Compute a ( partial ) cost for rtx X . Return true if the complete cost has been computed , and false if subexpressions should be scanned . In either case , * TOTAL contains the cost result .


Emit target-specific code that performs a memcpy .


<s>
void
MSP430FrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
MSP430MachineFunctionInfo
*
MSP430FI
=
MF
.
getInfo
<
MSP430MachineFunctionInfo
>
(
)
;
const
MSP430InstrInfo
&
TII
=
*
static_cast
<
const
MSP430InstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
DL
=
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
uint64_t
StackSize
=
MFI
->
getStackSize
(
)
;
uint64_t
NumBytes
=
0
;
if
(
hasFP
(
MF
)
)
{
uint64_t
FrameSize
=
StackSize
2
;
NumBytes
=
FrameSize
MSP430FI
->
getCalleeSavedFrameSize
(
)
;
MFI
->
setOffsetAdjustment
(
NumBytes
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
TII
.
get
(
MSP430
::
PUSH16r
)
)
.
addReg
(
MSP430
::
FP
,
RegState
::
Kill
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
TII
.
get
(
MSP430
::
MOV16rr
)
,
MSP430
::
FP
)
.
addReg
(
MSP430
::
SP
)
;
for
(
MachineFunction
::
iterator
I
=
std
::
next
(
MF
.
begin
(
)
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
I
->
addLiveIn
(
MSP430
::
FP
)
;
}
else
NumBytes
=
StackSize
MSP430FI
->
getCalleeSavedFrameSize
(
)
;
while
(
MBBI
!=
MBB
.
end
(
)
&&
(
MBBI
->
getOpcode
(
)
==
MSP430
::
PUSH16r
)
)
++
MBBI
;
if
(
MBBI
!=
MBB
.
end
(
)
)
DL
=
MBBI
->
getDebugLoc
(
)
;
if
(
NumBytes
)
{
if
(
NumBytes
)
{
MachineInstr
*
MI
=
BuildMI
(
MBB
,
MBBI
,
DL
,
TII
.
get
(
MSP430
::
SUB16ri
)
,
MSP430
::
SP
)
.
addReg
(
MSP430
::
SP
)
.
addImm
(
NumBytes
)
;
MI
->
getOperand
(
3
)
.
setIsDead
(
)
;
}
}
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static void arm_emit_vfp_multi_reg_pop ( int first_reg , int num_regs , rtx base_reg ) { int i , j ; rtx par ; rtx dwarf = NULL_RTX ; rtx tmp , reg ; gcc_assert ( num_regs && num_regs <= 32 ) ; if ( num_regs == 2 && ! arm_arch6 ) { if ( first_reg == 15 ) first_reg -- ; num_regs ++ ; } if ( num_regs > 16 ) { arm_emit_vfp_multi_reg_pop ( first_reg , 16 , base_reg ) ; arm_emit_vfp_multi_reg_pop ( first_reg + 16 , num_regs - 16 , base_reg ) ; return ; } par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs + 1 ) ) ; tmp = gen_rtx_SET ( VOIDmode , base_reg , plus_constant ( Pmode , base_reg , 8 * num_regs ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , 0 ) = tmp ; for ( j = 0 , i = first_reg ; j < num_regs ; i += 2 ) { reg = gen_rtx_REG ( DFmode , i ) ; tmp = gen_rtx_SET ( VOIDmode , reg , gen_frame_mem ( DFmode , plus_constant ( Pmode , base_reg , 8 * j ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , j + 1 ) = tmp ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; j ++ ; } par = emit_insn ( par ) ; REG_NOTES ( par ) = dwarf ; if ( TARGET_VFP && REGNO ( base_reg ) == IP_REGNUM ) { RTX_FRAME_RELATED_P ( par ) = 1 ; add_reg_note ( par , REG_CFA_DEF_CFA , hard_frame_pointer_rtx ) ; } else arm_add_cfa_adjust_cfa_note ( par , 2 * UNITS_PER_WORD * num_regs , base_reg , base_reg ) ; } </s>

Generate and emit an insn pattern that we will recognize as a pop_multi of NUM_REGS consecutive VFP regs , starting at FIRST_REG . Unfortunately , since this insn does not reflect very well the actual semantics of the operation , we need to annotate the insn for the benefit of DWARF2 frame unwind information .


<s> bool PPCLinuxAsmPrinter :: doFinalization ( Module & M ) { const DataLayout * TD = TM . getDataLayout ( ) ; bool isPPC64 = TD -> getPointerSizeInBits ( ) == 64 ; PPCTargetStreamer & TS = static_cast < PPCTargetStreamer & > ( * OutStreamer . getTargetStreamer ( ) ) ; if ( ! TOC . empty ( ) ) { const MCSectionELF * Section ; if ( isPPC64 ) Section = OutStreamer . getContext ( ) . getELFSection ( ".toc" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; else Section = OutStreamer . getContext ( ) . getELFSection ( ".got2" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; OutStreamer . SwitchSection ( Section ) ; for ( MapVector < MCSymbol * , MCSymbol * > :: iterator I = TOC . begin ( ) , E = TOC . end ( ) ; I != E ; ++ I ) { OutStreamer . EmitLabel ( I -> second ) ; MCSymbol * S = I -> first ; if ( isPPC64 ) TS . emitTCEntry ( * S ) ; else OutStreamer . EmitSymbolValue ( S , 4 ) ; } } MachineModuleInfoELF & MMIELF = MMI -> getObjFileInfo < MachineModuleInfoELF > ( ) ; MachineModuleInfoELF :: SymbolListTy Stubs = MMIELF . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> void AArch64RegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , Register BaseReg , int FrameIdx , int64_t Offset ) const { MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; const AArch64InstrInfo * TII = MF . getSubtarget < AArch64Subtarget > ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII -> get ( AArch64 :: ADDXri ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; MRI . constrainRegClass ( BaseReg , TII -> getRegClass ( MCID , 0 , this , MF ) ) ; unsigned Shifter = AArch64_AM :: getShifterImm ( AArch64_AM :: LSL , 0 ) ; BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) . addImm ( Shifter ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .


<s> static unsigned getBit ( InsnType insn , int pos ) { return getBits ( insn , pos , 1 ) ; } </s>

Get the Init value of the specified bit .


<s>
const
char
*
getPassName
(
)
const
{
return
"Hexagon Hardware Loop Fixup"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { const R600Subtarget & ST = MF . getSubtarget < R600Subtarget > ( ) ; TII = ST . getInstrInfo ( ) ; for ( MachineFunction :: iterator BB = MF . begin ( ) , BB_E = MF . end ( ) ; BB != BB_E ; ++ BB ) { MachineBasicBlock & MBB = * BB ; MachineBasicBlock :: iterator I = MBB . begin ( ) ; if ( I != MBB . end ( ) && I -> getOpcode ( ) == AMDGPU :: CF_ALU ) continue ; for ( MachineBasicBlock :: iterator E = MBB . end ( ) ; I != E ; ) { if ( isALU ( * I ) ) I = MakeALUClause ( MBB , I ) ; else ++ I ; } } return false ; } </s>

runOnMachineFunction - Emit the function body .


<s>
MachineBasicBlock
*
SparcTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown SELECT_CC!"
)
;
case
SP
::
SELECT_CC_Int_ICC
:
case
SP
::
SELECT_CC_FP_ICC
:
case
SP
::
SELECT_CC_DFP_ICC
:
case
SP
::
SELECT_CC_QFP_ICC
:
return
expandSelectCC
(
MI
,
BB
,
SP
::
BCOND
)
;
case
SP
::
SELECT_CC_Int_FCC
:
case
SP
::
SELECT_CC_FP_FCC
:
case
SP
::
SELECT_CC_DFP_FCC
:
case
SP
::
SELECT_CC_QFP_FCC
:
return
expandSelectCC
(
MI
,
BB
,
SP
::
FBCOND
)
;
case
SP
::
ATOMIC_LOAD_ADD_32
:
return
expandAtomicRMW
(
MI
,
BB
,
SP
::
ADDrr
)
;
case
SP
::
ATOMIC_LOAD_ADD_64
:
return
expandAtomicRMW
(
MI
,
BB
,
SP
::
ADDXrr
)
;
case
SP
::
ATOMIC_LOAD_SUB_32
:
return
expandAtomicRMW
(
MI
,
BB
,
SP
::
SUBrr
)
;
case
SP
::
ATOMIC_LOAD_SUB_64
:
return
expandAtomicRMW
(
MI
,
BB
,
SP
::
SUBXrr
)
;
case
SP
::
ATOMIC_LOAD_AND_32
:
return
expandAtomicRMW
(
MI
,
BB
,
SP
::
ANDrr
)
;
case
SP
::
ATOMIC_LOAD_AND_64
:
return
expandAtomicRMW
(
MI
,
BB
,
SP
::
ANDXrr
)
;
case
SP
::
ATOMIC_LOAD_OR_32
:
return
expandAtomicRMW
(
MI
,
BB
,
SP
::
ORrr
)
;
case
SP
::
ATOMIC_LOAD_OR_64
:
return
expandAtomicRMW
(
MI
,
BB
,
SP
::
ORXrr
)
;
case
SP
::
ATOMIC_LOAD_XOR_32
:
return
expandAtomicRMW
(
MI
,
BB
,
SP
::
XORrr
)
;
case
SP
::
ATOMIC_LOAD_XOR_64
:
return
expandAtomicRMW
(
MI
,
BB
,
SP
::
XORXrr
)
;
case
SP
::
ATOMIC_LOAD_NAND_32
:
return
expandAtomicRMW
(
MI
,
BB
,
SP
::
ANDrr
)
;
case
SP
::
ATOMIC_LOAD_NAND_64
:
return
expandAtomicRMW
(
MI
,
BB
,
SP
::
ANDXrr
)
;
case
SP
::
ATOMIC_SWAP_64
:
return
expandAtomicRMW
(
MI
,
BB
,
0
)
;
case
SP
::
ATOMIC_LOAD_MAX_32
:
return
expandAtomicRMW
(
MI
,
BB
,
SP
::
MOVICCrr
,
SPCC
::
ICC_G
)
;
case
SP
::
ATOMIC_LOAD_MAX_64
:
return
expandAtomicRMW
(
MI
,
BB
,
SP
::
MOVXCCrr
,
SPCC
::
ICC_G
)
;
case
SP
::
ATOMIC_LOAD_MIN_32
:
return
expandAtomicRMW
(
MI
,
BB
,
SP
::
MOVICCrr
,
SPCC
::
ICC_LE
)
;
case
SP
::
ATOMIC_LOAD_MIN_64
:
return
expandAtomicRMW
(
MI
,
BB
,
SP
::
MOVXCCrr
,
SPCC
::
ICC_LE
)
;
case
SP
::
ATOMIC_LOAD_UMAX_32
:
return
expandAtomicRMW
(
MI
,
BB
,
SP
::
MOVICCrr
,
SPCC
::
ICC_GU
)
;
case
SP
::
ATOMIC_LOAD_UMAX_64
:
return
expandAtomicRMW
(
MI
,
BB
,
SP
::
MOVXCCrr
,
SPCC
::
ICC_GU
)
;
case
SP
::
ATOMIC_LOAD_UMIN_32
:
return
expandAtomicRMW
(
MI
,
BB
,
SP
::
MOVICCrr
,
SPCC
::
ICC_LEU
)
;
case
SP
::
ATOMIC_LOAD_UMIN_64
:
return
expandAtomicRMW
(
MI
,
BB
,
SP
::
MOVXCCrr
,
SPCC
::
ICC_LEU
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static void mips_output_32bit_xfer ( char direction , unsigned int gpreg , unsigned int fpreg ) { fprintf ( asm_out_file , "\tm%cc1\t%s,%s\n" , direction , reg_names [ gpreg ] , reg_names [ fpreg ] ) ; } </s>

Write instructions to move a 32-bit value between general register GPREG and floating-point register FPREG . DIRECTION is 't ' to move from GPREG to FPREG and ' f ' to move in the opposite direction .


<s> Optional < DestSourcePair > RISCVInstrInfo :: isCopyInstrImpl ( const MachineInstr & MI ) const { if ( MI . isMoveReg ( ) ) return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 1 ) } ; switch ( MI . getOpcode ( ) ) { default : break ; case RISCV :: ADDI : if ( MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 1 ) } ; break ; case RISCV :: FSGNJ_D : case RISCV :: FSGNJ_S : if ( MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 2 ) . isReg ( ) && MI . getOperand ( 1 ) . getReg ( ) == MI . getOperand ( 2 ) . getReg ( ) ) return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 1 ) } ; break ; } return None ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


"Marking libcall as possibly recursive: "

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s>
bool
PPCInstrInfo
::
SubsumesPredicate
(
const
SmallVectorImpl
<
MachineOperand
>
&
Pred1
,
const
SmallVectorImpl
<
MachineOperand
>
&
Pred2
)
const
{
assert
(
Pred1
.
size
(
)
==
2
&&
"Invalid PPC first predicate"
)
;
assert
(
Pred2
.
size
(
)
==
2
&&
"Invalid PPC second predicate"
)
;
if
(
Pred1
[
1
]
.
getReg
(
)
==
PPC
::
CTR8
||
Pred1
[
1
]
.
getReg
(
)
==
PPC
::
CTR
)
return
false
;
if
(
Pred2
[
1
]
.
getReg
(
)
==
PPC
::
CTR8
||
Pred2
[
1
]
.
getReg
(
)
==
PPC
::
CTR
)
return
false
;
if
(
Pred1
[
1
]
.
getReg
(
)
!=
Pred2
[
1
]
.
getReg
(
)
)
return
false
;
PPC
::
Predicate
P1
=
(
PPC
::
Predicate
)
Pred1
[
0
]
.
getImm
(
)
;
PPC
::
Predicate
P2
=
(
PPC
::
Predicate
)
Pred2
[
0
]
.
getImm
(
)
;
if
(
P1
==
P2
)
return
true
;
if
(
P1
==
PPC
::
PRED_LE
&&
(
P2
==
PPC
::
PRED_LT
||
P2
==
PPC
::
PRED_EQ
)
)
return
true
;
if
(
P1
==
PPC
::
PRED_GE
&&
(
P2
==
PPC
::
PRED_GT
||
P2
==
PPC
::
PRED_EQ
)
)
return
true
;
return
false
;
}
</s>

Returns true if the first specified predicate subsumes the second , e.g .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 Retpoline Thunks"
;
}
</s>


<s> const TPCRegisterInfo * getRegisterInfo ( ) const override { return & getInstrInfo ( ) -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void AArch64TargetStreamer :: emitCurrentConstantPool ( ) { ConstantPools -> emitForCurrentSection ( Streamer ) ; } </s>

Callback used to implement the .ltorg directive .


<s> BitVector SIRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AMDGPU :: EXEC ) ; Reserved . set ( AMDGPU :: EXEC_LO ) ; Reserved . set ( AMDGPU :: EXEC_HI ) ; Reserved . set ( AMDGPU :: INDIRECT_BASE_ADDR ) ; Reserved . set ( AMDGPU :: FLAT_SCR ) ; Reserved . set ( AMDGPU :: FLAT_SCR_LO ) ; Reserved . set ( AMDGPU :: FLAT_SCR_HI ) ; Reserved . set ( AMDGPU :: VGPR255 ) ; Reserved . set ( AMDGPU :: VGPR254 ) ; if ( MF . getSubtarget < AMDGPUSubtarget > ( ) . hasSGPRInitBug ( ) ) { unsigned NumSGPRs = AMDGPU :: SGPR_32RegClass . getNumRegs ( ) ; unsigned Limit = AMDGPUSubtarget :: FIXED_SGPR_COUNT_FOR_INIT_BUG - 4 ; for ( unsigned i = Limit ; i < NumSGPRs ; ++ i ) { unsigned Reg = AMDGPU :: SGPR_32RegClass . getRegister ( i ) ; MCRegAliasIterator R = MCRegAliasIterator ( Reg , this , true ) ; for ( ; R . isValid ( ) ; ++ R ) Reserved . set ( * R ) ; } } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCRelaxableFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
override
{
llvm_unreachable
(
"fixupNeedsRelaxation() unimplemented"
)
;
return
false
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> const MipsInstrInfo * getInstrInfo ( ) const override { return getSubtargetImpl ( ) -> getInstrInfo ( ) ; } </s>


<s> void GCNPassConfig :: addPreEmitPass ( ) { addPass ( createSIMemoryLegalizerPass ( ) ) ; addPass ( createSIInsertWaitcntsPass ( ) ) ; addPass ( createSIShrinkInstructionsPass ( ) ) ; addPass ( & PostRAHazardRecognizerID ) ; addPass ( & SIInsertSkipsPassID ) ; addPass ( createSIDebuggerInsertNopsPass ( ) ) ; addPass ( & BranchRelaxationPassID ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool AMDGPUAsmParser :: isRegister ( ) { return isRegister ( getToken ( ) , peekToken ( ) ) ; } </s>

isRegister - Returns true if this is a normal register use/def slot .


<s> int ARMTTIImpl :: getIntImmCost ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) { if ( ( Opcode == Instruction :: SDiv || Opcode == Instruction :: UDiv || Opcode == Instruction :: SRem || Opcode == Instruction :: URem ) && Idx == 1 ) return 0 ; if ( Opcode == Instruction :: And ) { if ( Imm == 255 || Imm == 65535 ) return 0 ; return std :: min ( getIntImmCost ( Imm , Ty ) , getIntImmCost ( ~ Imm , Ty ) ) ; } if ( Opcode == Instruction :: Add ) return std :: min ( getIntImmCost ( Imm , Ty ) , getIntImmCost ( - Imm , Ty ) ) ; if ( Opcode == Instruction :: ICmp && Imm . isNegative ( ) && Ty -> getIntegerBitWidth ( ) == 32 ) { int64_t NegImm = - Imm . getSExtValue ( ) ; if ( ST -> isThumb2 ( ) && NegImm < 1 << 12 ) return 0 ; if ( ST -> isThumb ( ) && NegImm < 1 << 8 ) return 0 ; } if ( Opcode == Instruction :: Xor && Imm . isAllOnesValue ( ) ) return 0 ; return getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> bool aarch64_emit_approx_div ( rtx quo , rtx num , rtx den ) { machine_mode mode = GET_MODE ( quo ) ; if ( GET_MODE_INNER ( mode ) == HFmode ) return false ; bool use_approx_division_p = ( flag_mlow_precision_div || ( aarch64_tune_params . approx_modes -> division & AARCH64_APPROX_MODE ( mode ) ) ) ; if ( ! flag_finite_math_only || flag_trapping_math || ! flag_unsafe_math_optimizations || optimize_function_for_size_p ( cfun ) || ! use_approx_division_p ) return false ; if ( ! TARGET_SIMD && VECTOR_MODE_P ( mode ) ) return false ; rtx xrcp = gen_reg_rtx ( mode ) ; emit_insn ( gen_aarch64_frecpe ( mode , xrcp , den ) ) ; int iterations = ( GET_MODE_INNER ( mode ) == DFmode ) ? 3 : 2 ; if ( flag_mlow_precision_div ) iterations -- ; rtx xtmp = gen_reg_rtx ( mode ) ; while ( iterations -- ) { emit_insn ( gen_aarch64_frecps ( mode , xtmp , xrcp , den ) ) ; if ( iterations > 0 ) emit_set_insn ( xrcp , gen_rtx_MULT ( mode , xrcp , xtmp ) ) ; } if ( num != CONST1_RTX ( mode ) ) { rtx xnum = force_reg ( mode , num ) ; emit_set_insn ( xrcp , gen_rtx_MULT ( mode , xrcp , xnum ) ) ; } emit_set_insn ( quo , gen_rtx_MULT ( mode , xrcp , xtmp ) ) ; return true ; } </s>

Emit the instruction sequence to compute the approximation for the division of NUM by DEN in QUO and return whether the sequence was emitted or not .


<s>
bool
AAPInstrInfo
::
isBranchOffsetInRange
(
unsigned
BranchOpc
,
int64_t
BrOffset
)
const
{
switch
(
BranchOpc
)
{
default
:
llvm_unreachable
(
"Invalid opcode"
)
;
case
AAP
::
BRA
:
return
AAP
::
isOff22
(
BrOffset
)
;
case
AAP
::
BEQ_
:
case
AAP
::
BNE_
:
case
AAP
::
BLTS_
:
case
AAP
::
BLES_
:
case
AAP
::
BLTU_
:
case
AAP
::
BLEU_
:
return
AAP
::
isOff10
(
BrOffset
)
;
}
}
</s>

Determine if the branch target is in range .


<s> MachineInstrBuilder R600InstrInfo :: buildIndirectWrite ( MachineBasicBlock * MBB , MachineBasicBlock :: iterator I , unsigned ValueReg , unsigned Address , unsigned OffsetReg ) const { unsigned AddrReg = AMDGPU :: R600_AddrRegClass . getRegister ( Address ) ; MachineInstr * MOVA = buildDefaultInstruction ( * MBB , I , AMDGPU :: MOVA_INT_eg , AMDGPU :: AR_X , OffsetReg ) ; setImmOperand ( MOVA , R600Operands :: WRITE , 0 ) ; MachineInstrBuilder Mov = buildDefaultInstruction ( * MBB , I , AMDGPU :: MOV , AddrReg , ValueReg ) . addReg ( AMDGPU :: AR_X , RegState :: Implicit ) ; setImmOperand ( Mov , R600Operands :: DST_REL , 1 ) ; return Mov ; } </s>

Build instruction ( s ) for an indirect register write .


<s> bool loongarch_eh_uses ( unsigned int regno ATTRIBUTE_UNUSED ) { return false ; } </s>


<s> EVT PPCTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool NonScalarIntSafe , bool MemcpyStrSrc , SelectionDAG & DAG ) const { if ( this -> PPCSubTarget . isPPC64 ( ) ) { return MVT :: i64 ; } else { return MVT :: i32 ; } } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> bool SystemZXPLINKFrameLowering :: hasFP ( const MachineFunction & MF ) const { return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
void
SIInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
DestReg
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
SIMachineFunctionInfo
*
MFI
=
MF
->
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MachineFrameInfo
&
FrameInfo
=
MF
->
getFrameInfo
(
)
;
const
DebugLoc
&
DL
=
MBB
.
findDebugLoc
(
MI
)
;
unsigned
Align
=
FrameInfo
.
getObjectAlignment
(
FrameIndex
)
;
unsigned
Size
=
FrameInfo
.
getObjectSize
(
FrameIndex
)
;
unsigned
SpillSize
=
TRI
->
getSpillSize
(
*
RC
)
;
MachinePointerInfo
PtrInfo
=
MachinePointerInfo
::
getFixedStack
(
*
MF
,
FrameIndex
)
;
MachineMemOperand
*
MMO
=
MF
->
getMachineMemOperand
(
PtrInfo
,
MachineMemOperand
::
MOLoad
,
Size
,
Align
)
;
if
(
RI
.
isSGPRClass
(
RC
)
)
{
MFI
->
setHasSpilledSGPRs
(
)
;
const
MCInstrDesc
&
OpDesc
=
get
(
getSGPRSpillRestoreOpcode
(
SpillSize
)
)
;
if
(
TargetRegisterInfo
::
isVirtualRegister
(
DestReg
)
&&
SpillSize
==
4
)
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
MRI
.
constrainRegClass
(
DestReg
,
&
AMDGPU
::
SReg_32_XM0RegClass
)
;
}
FrameInfo
.
setStackID
(
FrameIndex
,
SIStackID
::
SGPR_SPILL
)
;
MachineInstrBuilder
Spill
=
BuildMI
(
MBB
,
MI
,
DL
,
OpDesc
,
DestReg
)
.
addFrameIndex
(
FrameIndex
)
.
addMemOperand
(
MMO
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
,
RegState
::
Implicit
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
,
RegState
::
Implicit
)
;
if
(
ST
.
hasScalarStores
(
)
)
{
Spill
.
addReg
(
AMDGPU
::
M0
,
RegState
::
ImplicitDefine
|
RegState
::
Dead
)
;
}
return
;
}
assert
(
RI
.
hasVGPRs
(
RC
)
&&
"Only VGPR spilling expected"
)
;
unsigned
Opcode
=
getVGPRSpillRestoreOpcode
(
SpillSize
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opcode
)
,
DestReg
)
.
addFrameIndex
(
FrameIndex
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineBranchProbabilityInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool SVEIntrinsicOpts :: runOnModule ( Module & M ) { bool Changed = false ; SmallSetVector < Function * , 4 > Functions ; for ( auto & F : M . getFunctionList ( ) ) { if ( ! F . isDeclaration ( ) ) continue ; switch ( F . getIntrinsicID ( ) ) { case Intrinsic :: experimental_vector_extract : case Intrinsic :: experimental_vector_insert : case Intrinsic :: aarch64_sve_ptrue : for ( User * U : F . users ( ) ) Functions . insert ( cast < Instruction > ( U ) -> getFunction ( ) ) ; break ; default : break ; } } if ( ! Functions . empty ( ) ) Changed |= optimizeFunctions ( Functions ) ; return Changed ; } </s>


<s> static void ix86_emit_save_reg_using_mov ( machine_mode mode , unsigned int regno , HOST_WIDE_INT cfa_offset ) { struct machine_function * m = cfun -> machine ; rtx reg = gen_rtx_REG ( mode , regno ) ; rtx unspec = NULL_RTX ; rtx mem , addr , base , insn ; unsigned int align ; addr = choose_baseaddr ( cfa_offset ) ; mem = gen_frame_mem ( mode , addr ) ; align = MIN ( GET_MODE_ALIGNMENT ( mode ) , INCOMING_STACK_BOUNDARY ) ; set_mem_align ( mem , align ) ; if ( mode == V4SFmode && align < 128 ) unspec = gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , reg ) , UNSPEC_STOREU ) ; insn = emit_insn ( gen_rtx_SET ( mem , unspec ? unspec : reg ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; base = addr ; if ( GET_CODE ( base ) == PLUS ) base = XEXP ( base , 0 ) ; gcc_checking_assert ( REG_P ( base ) ) ; if ( m -> fs . realigned ) { gcc_checking_assert ( stack_realign_drap ) ; if ( regno == REGNO ( crtl -> drap_reg ) ) { gcc_checking_assert ( cfun -> machine -> fs . fp_valid ) ; addr = plus_constant ( Pmode , hard_frame_pointer_rtx , cfun -> machine -> fs . fp_offset - cfa_offset ) ; mem = gen_rtx_MEM ( mode , addr ) ; add_reg_note ( insn , REG_CFA_DEF_CFA , mem ) ; } else { gcc_checking_assert ( cfun -> machine -> fs . fp_valid ) ; addr = plus_constant ( Pmode , hard_frame_pointer_rtx , cfun -> machine -> fs . fp_offset - cfa_offset ) ; mem = gen_rtx_MEM ( mode , addr ) ; add_reg_note ( insn , REG_CFA_EXPRESSION , gen_rtx_SET ( mem , reg ) ) ; } } else if ( base != m -> fs . cfa_reg ) { addr = plus_constant ( Pmode , m -> fs . cfa_reg , m -> fs . cfa_offset - cfa_offset ) ; mem = gen_rtx_MEM ( mode , addr ) ; add_reg_note ( insn , REG_CFA_OFFSET , gen_rtx_SET ( mem , reg ) ) ; } else if ( unspec ) add_reg_note ( insn , REG_CFA_EXPRESSION , gen_rtx_SET ( mem , reg ) ) ; } </s>

Emit a single register save at CFA - CFA_OFFSET .


<s> static int riscv_extend_cost ( rtx op , bool unsigned_p ) { if ( MEM_P ( op ) ) return 0 ; if ( unsigned_p && GET_MODE ( op ) == QImode ) return COSTS_N_INSNS ( 1 ) ; if ( TARGET_ZBA && TARGET_64BIT && unsigned_p && GET_MODE ( op ) == SImode ) return COSTS_N_INSNS ( 1 ) ; if ( TARGET_ZBB ) { if ( ! unsigned_p && GET_MODE ( op ) == QImode ) return COSTS_N_INSNS ( 1 ) ; if ( GET_MODE ( op ) == HImode ) return COSTS_N_INSNS ( 1 ) ; } if ( ! unsigned_p && GET_MODE ( op ) == SImode ) return COSTS_N_INSNS ( 1 ) ; return COSTS_N_INSNS ( 2 ) ; } </s>

Return the cost of sign- or zero-extending OP .


<s> rtx aarch64_simd_gen_const_vector_dup ( machine_mode mode , HOST_WIDE_INT val ) { rtx c = gen_int_mode ( val , GET_MODE_INNER ( mode ) ) ; return gen_const_vec_duplicate ( mode , c ) ; } </s>


<s> static void rl78_alloc_physical_registers_umul ( rtx_insn * insn ) { rtx prev = prev_nonnote_nondebug_insn ( insn ) ; rtx first ; int tmp_id ; rtx saved_op1 ; OP ( 0 ) = transcode_memory_rtx ( OP ( 0 ) , BC , insn ) ; OP ( 1 ) = transcode_memory_rtx ( OP ( 1 ) , DE , insn ) ; OP ( 2 ) = transcode_memory_rtx ( OP ( 2 ) , HL , insn ) ; MAYBE_OK ( insn ) ; if ( recog_data . constraints [ 1 ] [ 0 ] == '%' && is_virtual_register ( OP ( 1 ) ) && ! is_virtual_register ( OP ( 2 ) ) && ! CONSTANT_P ( OP ( 2 ) ) ) { rtx tmp = OP ( 1 ) ; OP ( 1 ) = OP ( 2 ) ; OP ( 2 ) = tmp ; } OP ( 0 ) = move_from_acc ( 0 , insn ) ; tmp_id = get_max_insn_count ( ) ; saved_op1 = OP ( 1 ) ; if ( rtx_equal_p ( OP ( 1 ) , OP ( 2 ) ) ) { gcc_assert ( GET_MODE ( OP ( 2 ) ) == QImode ) ; OP ( 2 ) = move_to_x ( 2 , insn ) ; OP ( 1 ) = A ; } else OP ( 1 ) = move_to_acc ( 1 , insn ) ; MAYBE_OK ( insn ) ; if ( tmp_id == get_max_insn_count ( ) ) force_into_acc ( saved_op1 , insn ) ; if ( prev ) first = next_nonnote_nondebug_insn ( prev ) ; else for ( first = insn ; prev_nonnote_nondebug_insn ( first ) ; first = prev_nonnote_nondebug_insn ( first ) ) ; OP ( 2 ) = move_to_x ( 2 , first ) ; MUST_BE_OK ( insn ) ; } </s>


<s> inline bool wrapped_symbol_hasher :: equal ( const value_type * x , const compare_type * y ) { return ! strcmp ( x , y ) ; } </s>


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Mips Delay Slot Filler"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool enableShrinkWrapping ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target will correctly handle shrink wrapping .


<s> bool AArch64PagerandoOptimizer :: runOnMachineFunction ( MachineFunction & MF ) { auto & F = MF . getFunction ( ) ; if ( ! F . isPagerando ( ) || skipFunction ( F ) ) { return false ; } auto BinPrefix = F . getSectionPrefix ( ) . getValue ( ) ; std :: vector < MachineInstr * > Worklist ; for ( auto & BB : MF ) { for ( auto & MI : BB ) { if ( isIntraBin ( MI , BinPrefix ) ) Worklist . push_back ( & MI ) ; } } for ( auto * MI : Worklist ) optimizeCalls ( MI ) ; return ! Worklist . empty ( ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> static unsigned int tilegx_function_arg_boundary ( machine_mode mode , const_tree type ) { unsigned int alignment ; alignment = type ? TYPE_ALIGN ( type ) : GET_MODE_ALIGNMENT ( mode ) ; if ( alignment < PARM_BOUNDARY ) alignment = PARM_BOUNDARY ; if ( alignment > STACK_BOUNDARY ) alignment = STACK_BOUNDARY ; return alignment ; } </s>


<s> Register getExceptionSelectorRegister ( const Constant * PersonalityFn ) const override { return SP :: I1 ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .


<s> void s390_expand_cs_hqi ( enum machine_mode mode , rtx target , rtx mem , rtx cmp , rtx new ) { struct alignment_context ac ; rtx cmpv , newv , val , resv , cc ; rtx res = gen_reg_rtx ( SImode ) ; rtx csloop = gen_label_rtx ( ) ; rtx csend = gen_label_rtx ( ) ; gcc_assert ( register_operand ( target , VOIDmode ) ) ; gcc_assert ( MEM_P ( mem ) ) ; init_alignment_context ( & ac , mem , mode ) ; if ( ! ( ac . aligned && MEM_P ( cmp ) ) ) cmp = s390_expand_mask_and_shift ( cmp , mode , ac . shift ) ; if ( ! ( ac . aligned && MEM_P ( new ) ) ) new = s390_expand_mask_and_shift ( new , mode , ac . shift ) ; val = expand_simple_binop ( SImode , AND , ac . memsi , ac . modemaski , NULL_RTX , 1 , OPTAB_DIRECT ) ; emit_label ( csloop ) ; if ( ac . aligned && MEM_P ( cmp ) ) { cmpv = force_reg ( SImode , val ) ; store_bit_field ( cmpv , GET_MODE_BITSIZE ( mode ) , 0 , SImode , cmp ) ; } else cmpv = force_reg ( SImode , expand_simple_binop ( SImode , IOR , cmp , val , NULL_RTX , 1 , OPTAB_DIRECT ) ) ; if ( ac . aligned && MEM_P ( new ) ) { newv = force_reg ( SImode , val ) ; store_bit_field ( newv , GET_MODE_BITSIZE ( mode ) , 0 , SImode , new ) ; } else newv = force_reg ( SImode , expand_simple_binop ( SImode , IOR , new , val , NULL_RTX , 1 , OPTAB_DIRECT ) ) ; emit_insn ( gen_sync_compare_and_swap_ccsi ( res , ac . memsi , cmpv , newv ) ) ; s390_emit_jump ( csend , s390_emit_compare ( EQ , cmpv , ac . memsi ) ) ; resv = expand_simple_binop ( SImode , AND , res , ac . modemaski , NULL_RTX , 1 , OPTAB_DIRECT ) ; cc = s390_emit_compare ( NE , resv , val ) ; emit_move_insn ( val , resv ) ; s390_emit_jump ( csloop , cc ) ; emit_label ( csend ) ; convert_move ( target , expand_simple_binop ( SImode , LSHIFTRT , res , ac . shift , NULL_RTX , 1 , OPTAB_DIRECT ) , 1 ) ; } </s>

Expand an atomic compare and swap operation for HImode and QImode . MEM is the memory location , CMP the old value to compare MEM with and NEW the value to set if CMP == MEM . CMP is never in memory for compare_and_swap_cc because expand_bool_compare_and_swap puts it into a register for later compare .


<s> bool SICFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * EntryBlock = & MF -> front ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == SIC :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> void PTXPassConfig :: addOptimizedRegAlloc ( FunctionPass * RegAllocPass ) { addFastRegAlloc ( RegAllocPass ) ; } </s>

addOptimizedRegAlloc - Add passes related to register allocation .


<s> const MCExpr * R600AsmPrinter :: lowerConstant ( const Constant * CV ) { if ( const MCExpr * E = lowerAddrSpaceCast ( TM , CV , OutContext ) ) return E ; return AsmPrinter :: lowerConstant ( CV ) ; } </s>

Lower the specified LLVM Constant to an MCExpr .


<s> unsigned X86TTI :: getIntImmCost ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) const { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TCC_Free ; unsigned ImmIdx = ~ 0U ; switch ( Opcode ) { default : return TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TCC_Basic ; return TCC_Free ; case Instruction :: Store : ImmIdx = 0 ; break ; case Instruction :: Add : case Instruction :: Sub : case Instruction :: Mul : case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : case Instruction :: ICmp : ImmIdx = 1 ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == 1 ) return TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: IntToPtr : case Instruction :: PtrToInt : case Instruction :: BitCast : case Instruction :: PHI : case Instruction :: Call : case Instruction :: Select : case Instruction :: Ret : case Instruction :: Load : break ; } if ( ( Idx == ImmIdx ) && Imm . getBitWidth ( ) <= 64 && isInt < 32 > ( Imm . getSExtValue ( ) ) ) return TCC_Free ; return X86TTI :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s>
static
void
arm_option_print
(
FILE
*
file
,
int
indent
,
struct
cl_target_option
*
ptr
)
{
int
flags
=
ptr
->
x_target_flags
;
const
char
*
fpu_name
;
fpu_name
=
(
ptr
->
x_arm_fpu_index
==
TARGET_FPU_auto
"auto"
:
all_fpus
[
ptr
->
x_arm_fpu_index
]
.
name
)
;
fprintf
(
file
,
"%*sselected arch %s\n"
,
indent
,
""
,
TARGET_THUMB2_P
(
flags
)
"thumb2"
:
TARGET_THUMB_P
(
flags
)
"thumb1"
:
"arm"
)
;
fprintf
(
file
,
"%*sselected fpu %s\n"
,
indent
,
""
,
fpu_name
)
;
}
</s>

arm
"auto"
"%*sselected arch %s\n"
""
"thumb2"
"thumb1"
"arm"
"%*sselected fpu %s\n"
""


<s> bool MMIXPassConfig :: addInstSelector ( ) { addPass ( createMMIXISelDag ( getMMIXTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool AMDGPUAsmParser :: usesConstantBus ( const MCInst & Inst , unsigned OpIdx ) { const MCOperand & MO = Inst . getOperand ( OpIdx ) ; if ( MO . isImm ( ) ) { return ! isInlineConstant ( Inst , OpIdx ) ; } return ! MO . isReg ( ) || isSGPR ( mc2PseudoReg ( MO . getReg ( ) ) ) ; } </s>

Returns true if this operand uses the constant bus .


<s> static bool m68k_save_reg ( unsigned int regno , bool interrupt_handler ) { if ( flag_pic && regno == PIC_REG ) { if ( crtl -> saves_all_registers ) return true ; if ( crtl -> uses_pic_offset_table ) return true ; if ( crtl -> uses_const_pool ) return true ; } if ( crtl -> calls_eh_return ) { unsigned int i ; for ( i = 0 ; ; i ++ ) { unsigned int test = EH_RETURN_DATA_REGNO ( i ) ; if ( test == INVALID_REGNUM ) break ; if ( test == regno ) return true ; } } if ( fixed_regs [ regno ] ) return false ; if ( regno == FRAME_POINTER_REGNUM && frame_pointer_needed ) return false ; if ( interrupt_handler ) { if ( df_regs_ever_live_p ( regno ) ) return true ; if ( ! crtl -> is_leaf && call_used_regs [ regno ] ) return true ; } if ( ! df_regs_ever_live_p ( regno ) ) return false ; return ! call_used_regs [ regno ] ; } </s>

Refer to the array ` regs_ever_live ' to determine which registers to save ; ` regs_ever_live [ I ] ' is nonzero if register number I is ever used in the function . This function is responsible for knowing which registers should not be saved even if used . Return true if we need to save REGNO .


<s>
bool
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
override
{
switch
(
ConstraintID
)
{
default
:
errs
(
)
<<
"ConstraintID: "
<<
ConstraintID
<<
"\n"
;
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_es
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_o
:
case
InlineAsm
::
Constraint_Q
:
case
InlineAsm
::
Constraint_Z
:
case
InlineAsm
::
Constraint_Zy
:
const
TargetRegisterInfo
*
TRI
=
PPCSubTarget
->
getRegisterInfo
(
)
;
const
TargetRegisterClass
*
TRC
=
TRI
->
getPointerRegClass
(
*
MF
,
1
)
;
SDLoc
dl
(
Op
)
;
SDValue
RC
=
CurDAG
->
getTargetConstant
(
TRC
->
getID
(
)
,
dl
,
MVT
::
i32
)
;
SDValue
NewOp
=
SDValue
(
CurDAG
->
getMachineNode
(
TargetOpcode
::
COPY_TO_REGCLASS
,
dl
,
Op
.
getValueType
(
)
,
Op
,
RC
)
,
0
)
;
OutOps
.
push_back
(
NewOp
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s>
static
void
v850_asm_trampoline_template
(
FILE
*
f
)
{
fprintf
(
f
,
"\tjarl .+4,r12\n"
)
;
fprintf
(
f
,
"\tld.w 12[r12],r20\n"
)
;
fprintf
(
f
,
"\tld.w 16[r12],r12\n"
)
;
fprintf
(
f
,
"\tjmp [r12]\n"
)
;
fprintf
(
f
,
"\tnop\n"
)
;
fprintf
(
f
,
"\t.long 0\n"
)
;
fprintf
(
f
,
"\t.long 0\n"
)
;
}
</s>

Worker function for TARGET_ASM_TRAMPOLINE_TEMPLATE .


<s> TargetTransformInfo :: PopcntSupportKind getPopcntSupport ( unsigned TyWidth ) { if ( TyWidth == 32 ) return TTI :: PSK_FastHardware ; return TTI :: PSK_Software ; } </s>

Return hardware support for population count .


<s> bool runOnModule ( Module & M ) override { WriteDXILToFile ( M , OS ) ; return false ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> unsigned ARMFastISel :: fastEmitInst_ri ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , uint64_t Imm ) { Register ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , 1 ) ; if ( II . getNumDefs ( ) >= 1 ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 ) . addImm ( Imm ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 ) . addImm ( Imm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ 0 ] ) ) ; } return ResultReg ; } </s>

Emit a MachineInstr with a register operand , an immediate , and a result register in the given register class .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 Indirect Thunks"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static rtx emit_adjust_base_to_offset ( rtx base , int offset ) { rtx new_base = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( new_base , GEN_INT ( offset ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , new_base , gen_rtx_PLUS ( Pmode , base , new_base ) ) ) ; return new_base ; } </s>

Emit code to adjust BASE to OFFSET . Return the new base .


<s> bool NyuziFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static void mips_save_restore_reg ( enum machine_mode mode , int regno , HOST_WIDE_INT offset , mips_save_restore_fn fn ) { rtx mem ; mem = gen_rtx_MEM ( mode , plus_constant ( stack_pointer_rtx , offset ) ) ; fn ( gen_rtx_REG ( mode , regno ) , mem ) ; } </s>

Use FN to save or restore register REGNO . MODE is the register 's mode and OFFSET is the offset of its save slot from the current stack pointer .


"rs6000_can_change_mode_class, return %s, from = %s, "

Debug version of rs6000_can_change_mode_class .


<s>
void
RISCVMCAsmBackend
::
relaxInstruction
(
const
MCInst
&
Inst
,
MCInst
&
Res
)
const
{
unsigned
Opcode
=
getRelaxedOpcode
(
Inst
.
getOpcode
(
)
)
;
assert
(
Opcode
&&
"Unexpected insn to relax"
)
;
Res
=
Inst
;
Res
.
setOpcode
(
Opcode
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> virtual void Initialize ( MCContext & ctx , const TargetMachine & TM ) { TargetLoweringObjectFile :: Initialize ( ctx , TM ) ; TextSection = new WDC65816Section ( MCSection :: SV_ELF , SectionKind :: getText ( ) ) ; DataSection = new WDC65816Section ( MCSection :: SV_ELF , SectionKind :: getDataRel ( ) ) ; BSSSection = new WDC65816Section ( MCSection :: SV_ELF , SectionKind :: getBSS ( ) ) ; ReadOnlySection = new WDC65816Section ( MCSection :: SV_ELF , SectionKind :: getReadOnly ( ) ) ; StaticCtorSection = new WDC65816Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; StaticDtorSection = new WDC65816Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; LSDASection = new WDC65816Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; EHFrameSection = new WDC65816Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfAbbrevSection = new WDC65816Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfInfoSection = new WDC65816Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfLineSection = new WDC65816Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfFrameSection = new WDC65816Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfPubTypesSection = new WDC65816Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfDebugInlineSection = new WDC65816Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfStrSection = new WDC65816Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfLocSection = new WDC65816Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfARangesSection = new WDC65816Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfRangesSection = new WDC65816Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfMacroInfoSection = new WDC65816Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; } </s>

This method must be called before any actual lowering is done .

WDC65816 WDC WDC WDC WDC WDC WDC WDC WDC WDC WDC WDC WDC WDC WDC WDC WDC WDC WDC WDC


"rs6000_can_inline_p:, caller %s, callee %s, %s inline\n"

Hook to determine if one function can safely inline another .


<s> bool R600InstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { switch ( MI -> getOpcode ( ) ) { default : return AMDGPUInstrInfo :: expandPostRAPseudo ( MI ) ; case AMDGPU :: R600_EXTRACT_ELT_V2 : case AMDGPU :: R600_EXTRACT_ELT_V4 : buildIndirectRead ( MI -> getParent ( ) , MI , MI -> getOperand ( 0 ) . getReg ( ) , RI . getHWRegIndex ( MI -> getOperand ( 1 ) . getReg ( ) ) , MI -> getOperand ( 2 ) . getReg ( ) , RI . getHWRegChan ( MI -> getOperand ( 1 ) . getReg ( ) ) ) ; break ; case AMDGPU :: R600_INSERT_ELT_V2 : case AMDGPU :: R600_INSERT_ELT_V4 : buildIndirectWrite ( MI -> getParent ( ) , MI , MI -> getOperand ( 2 ) . getReg ( ) , RI . getHWRegIndex ( MI -> getOperand ( 1 ) . getReg ( ) ) , MI -> getOperand ( 3 ) . getReg ( ) , RI . getHWRegChan ( MI -> getOperand ( 1 ) . getReg ( ) ) ) ; break ; } MI -> eraseFromParent ( ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> static int alpha_issue_rate ( void ) { return ( alpha_tune == PROCESSOR_EV4 ? 2 : 4 ) ; } </s>

Function to initialize the issue rate used by the scheduler .


<s> enum reg_class secondary_reload_class ( enum reg_class class , enum machine_mode mode , rtx in ) { if ( ( GET_CODE ( in ) == MEM || ( GET_CODE ( in ) == REG && REGNO ( in ) >= FIRST_PSEUDO_REGISTER ) || ( GET_CODE ( in ) == SUBREG && GET_CODE ( SUBREG_REG ( in ) ) == REG && REGNO ( SUBREG_REG ( in ) ) >= FIRST_PSEUDO_REGISTER ) ) && ( mode == QImode || mode == HImode ) && ( class == ADDRESS_REGS || class == SP_REGS || class == SP_OR_ADDRESS_REGS ) ) { if ( TARGET_AM33 ) return DATA_OR_EXTENDED_REGS ; return DATA_REGS ; } if ( class != SP_REGS && class != ADDRESS_REGS && class != SP_OR_ADDRESS_REGS && class != SP_OR_EXTENDED_REGS && class != ADDRESS_OR_EXTENDED_REGS && class != SP_OR_ADDRESS_OR_EXTENDED_REGS && ( in == stack_pointer_rtx || ( GET_CODE ( in ) == PLUS && ( XEXP ( in , 0 ) == stack_pointer_rtx || XEXP ( in , 1 ) == stack_pointer_rtx ) ) ) ) return ADDRESS_REGS ; if ( GET_CODE ( in ) == PLUS && ( XEXP ( in , 0 ) == stack_pointer_rtx || XEXP ( in , 1 ) == stack_pointer_rtx ) ) { if ( TARGET_AM33 ) return DATA_OR_EXTENDED_REGS ; return DATA_REGS ; } if ( TARGET_AM33_2 && class == FP_REGS && GET_CODE ( in ) == MEM && ! OK_FOR_Q ( in ) ) { if ( TARGET_AM33 ) return DATA_OR_EXTENDED_REGS ; return DATA_REGS ; } return NO_REGS ; } </s>

Return the class of any secondary reload register that is needed to move IN into a register in class CLASS using mode MODE . Profiling has showed this routine and its descendants account for a significant amount of compile time ( ~7 % ) . So it has been optimized to reduce redundant computations and eliminate useless function calls . It might be worthwhile to try and make this a leaf function too .


<s> void ARMWinCOFFStreamer :: finishImpl ( ) { emitFrames ( nullptr ) ; MCWinCOFFStreamer :: finishImpl ( ) ; } </s>


<s> void P2InstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & O ) { printInstruction ( MI , Address , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> virtual const AlphaRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void AMDGPUDAGToDAGISel :: PostprocessISelDAG ( ) { const AMDGPUTargetLowering & Lowering = ( ( const AMDGPUTargetLowering & ) TLI ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ++ I ) { MachineSDNode * Node = dyn_cast < MachineSDNode > ( I ) ; if ( ! Node ) continue ; SDNode * ResNode = Lowering . PostISelFolding ( Node , * CurDAG ) ; if ( ResNode != Node ) ReplaceUses ( Node , ResNode ) ; } } </s>

PostprocessISelDAG ( ) - This hook allows the target to hack on the graph right after selection .


<s> bool Mips16RegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { return false ; } </s>

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot .


"code model %s does not support PIC mode"

Adjust target options after streaming them in . This is mainly about reconciling them with global options .


<s> bool MipsExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { STI = & static_cast < const MipsSubtarget & > ( MF . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : MF ) Modified |= expandMBB ( MBB ) ; if ( Modified ) MF . RenumberBlocks ( ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , LittleEndian ) , InstrInfo ( Subtarget ) , DL ( LittleEndian ? "e-m:e-i64:64-i128:128-n32:64-S128" : "E-m:e-i64:64-i128:128-n32:64-S128" ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) { initAsmInfo ( ) ; } </s>


<s> bool HexagonAsmParser :: isLabel ( AsmToken & Token ) { MCAsmLexer & Lexer = getLexer ( ) ; AsmToken const & Second = Lexer . getTok ( ) ; AsmToken Third = Lexer . peekTok ( ) ; StringRef String = Token . getString ( ) ; if ( Token . is ( AsmToken :: TokenKind :: LCurly ) || Token . is ( AsmToken :: TokenKind :: RCurly ) ) return false ; if ( ! Token . is ( AsmToken :: TokenKind :: Identifier ) ) return true ; if ( ! matchRegister ( String . lower ( ) ) ) return true ; ( void ) Second ; assert ( Second . is ( AsmToken :: Colon ) ) ; StringRef Raw ( String . data ( ) , Third . getString ( ) . data ( ) - String . data ( ) + Third . getString ( ) . size ( ) ) ; std :: string Collapsed = Raw ; Collapsed . erase ( std :: remove_if ( Collapsed . begin ( ) , Collapsed . end ( ) , isspace ) , Collapsed . end ( ) ) ; StringRef Whole = Collapsed ; std :: pair < StringRef , StringRef > DotSplit = Whole . split ( '.' ) ; if ( ! matchRegister ( DotSplit . first . lower ( ) ) ) return true ; return false ; } </s>

Returns true if the MachineInstr represents a label .


<s>
bool
HCE
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
if
(
MF
.
getFunction
(
)
.
hasPersonalityFn
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
getPassName
(
)
<<
": skipping "
<<
MF
.
getName
(
)
<<
" due to exception handling\n"
)
;
return
false
;
}
LLVM_DEBUG
(
MF
.
print
(
dbgs
(
)
<<
"Before "
<<
getPassName
(
)
<<
'\n'
,
nullptr
)
)
;
HII
=
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getInstrInfo
(
)
;
HRI
=
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getRegisterInfo
(
)
;
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
AssignmentMap
IMap
;
collect
(
MF
)
;
llvm
::
sort
(
Extenders
,
[
this
]
(
const
ExtDesc
&
A
,
const
ExtDesc
&
B
)
{
ExtValue
VA
(
A
)
,
VB
(
B
)
;
if
(
VA
!=
VB
)
return
VA
<
VB
;
const
MachineInstr
*
MA
=
A
.
UseMI
;
const
MachineInstr
*
MB
=
B
.
UseMI
;
if
(
MA
==
MB
)
{
return
A
.
OpNum
<
B
.
OpNum
;
}
const
MachineBasicBlock
*
BA
=
MA
->
getParent
(
)
;
const
MachineBasicBlock
*
BB
=
MB
->
getParent
(
)
;
assert
(
BA
->
getNumber
(
)
!=
1
&&
BB
->
getNumber
(
)
!=
1
)
;
if
(
BA
!=
BB
)
return
BA
->
getNumber
(
)
<
BB
->
getNumber
(
)
;
return
MDT
->
dominates
(
MA
,
MB
)
;
}
)
;
bool
Changed
=
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Collected "
<<
Extenders
.
size
(
)
<<
" extenders\n"
)
;
for
(
unsigned
I
=
0
,
E
=
Extenders
.
size
(
)
;
I
!=
E
;
)
{
unsigned
B
=
I
;
const
ExtRoot
&
T
=
Extenders
[
B
]
.
getOp
(
)
;
while
(
I
!=
E
&&
ExtRoot
(
Extenders
[
I
]
.
getOp
(
)
)
==
T
)
++
I
;
IMap
.
clear
(
)
;
assignInits
(
T
,
B
,
I
,
IMap
)
;
Changed
|=
replaceExtenders
(
IMap
)
;
}
LLVM_DEBUG
(
{
if
(
Changed
)
MF
.
print
(
dbgs
(
)
<<
"After "
<<
getPassName
(
)
<<
'\n'
,
nullptr
)
;
else
dbgs
(
)
<<
"No changes\n"
;
}
)
;
return
Changed
;
}
</s>

Hexagon
": skipping "
" due to exception handling\n"
"Before "
Hexagon
Hexagon
1
1
"Collected "
" extenders\n"
0
"After "
"No changes\n"


<s> static tree gcn_lockless_update ( location_t loc , gimple_stmt_iterator * gsi , tree ptr , tree var , tree_code op ) { unsigned fn = GCN_BUILTIN_CMP_SWAP ; tree_code code = NOP_EXPR ; tree arg_type = unsigned_type_node ; tree var_type = TREE_TYPE ( var ) ; if ( TREE_CODE ( var_type ) == COMPLEX_TYPE || TREE_CODE ( var_type ) == REAL_TYPE ) code = VIEW_CONVERT_EXPR ; if ( TYPE_SIZE ( var_type ) == TYPE_SIZE ( long_long_unsigned_type_node ) ) { arg_type = long_long_unsigned_type_node ; fn = GCN_BUILTIN_CMP_SWAPLL ; } tree swap_fn = gcn_builtin_decl ( fn , true ) ; gimple_seq init_seq = NULL ; tree init_var = make_ssa_name ( arg_type ) ; tree init_expr = omp_reduction_init_op ( loc , op , var_type ) ; init_expr = fold_build1 ( code , arg_type , init_expr ) ; gimplify_assign ( init_var , init_expr , & init_seq ) ; gimple * init_end = gimple_seq_last ( init_seq ) ; gsi_insert_seq_before ( gsi , init_seq , GSI_SAME_STMT ) ; basic_block pre_bb = gsi_bb ( * gsi ) ; edge pre_edge = split_block ( pre_bb , init_end ) ; basic_block loop_bb = pre_edge -> dest ; pre_bb = pre_edge -> src ; * gsi = gsi_for_stmt ( gsi_stmt ( * gsi ) ) ; tree expect_var = make_ssa_name ( arg_type ) ; tree actual_var = make_ssa_name ( arg_type ) ; tree write_var = make_ssa_name ( arg_type ) ; gimple_seq red_seq = NULL ; tree write_expr = fold_build1 ( code , var_type , expect_var ) ; write_expr = fold_build2 ( op , var_type , write_expr , var ) ; write_expr = fold_build1 ( code , arg_type , write_expr ) ; gimplify_assign ( write_var , write_expr , & red_seq ) ; gsi_insert_seq_before ( gsi , red_seq , GSI_SAME_STMT ) ; gimple_seq latch_seq = NULL ; tree swap_expr = build_call_expr_loc ( loc , swap_fn , 3 , ptr , expect_var , write_var ) ; gimplify_assign ( actual_var , swap_expr , & latch_seq ) ; gcond * cond = gimple_build_cond ( EQ_EXPR , actual_var , expect_var , NULL_TREE , NULL_TREE ) ; gimple_seq_add_stmt ( & latch_seq , cond ) ; gimple * latch_end = gimple_seq_last ( latch_seq ) ; gsi_insert_seq_before ( gsi , latch_seq , GSI_SAME_STMT ) ; edge post_edge = split_block ( loop_bb , latch_end ) ; basic_block post_bb = post_edge -> dest ; loop_bb = post_edge -> src ; * gsi = gsi_for_stmt ( gsi_stmt ( * gsi ) ) ; post_edge -> flags ^= EDGE_TRUE_VALUE | EDGE_FALLTHRU ; edge loop_edge = make_edge ( loop_bb , loop_bb , EDGE_FALSE_VALUE ) ; set_immediate_dominator ( CDI_DOMINATORS , loop_bb , pre_bb ) ; set_immediate_dominator ( CDI_DOMINATORS , post_bb , loop_bb ) ; gphi * phi = create_phi_node ( expect_var , loop_bb ) ; add_phi_arg ( phi , init_var , pre_edge , loc ) ; add_phi_arg ( phi , actual_var , loop_edge , loc ) ; loop * loop = alloc_loop ( ) ; loop -> header = loop_bb ; loop -> latch = loop_bb ; add_loop ( loop , loop_bb -> loop_father ) ; return fold_build1 ( code , var_type , write_var ) ; } </s>

Helper function for gcn_reduction_update . Insert code to locklessly update * PTR with * PTR OP VAR just before GSI . We use a lockless scheme for nearly all case , which looks like : actual = initval ( OP ) ; do { guess = actual ; write = guess OP myval ; actual = cmp & swap ( ptr , guess , write ) } while ( actual bit-different-to guess ) ; return write ; This relies on a cmp & swap instruction , which is available for 32- and 64-bit types . Larger types must use a locking scheme .


"Loop must have more than one incoming edge!"

Check to see if the loop has a canonical induction variable : an integer recurrence that starts at 0 and increments by one each time through the loop .


<s> void AMDGPUInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { OS . flush ( ) ; printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; } </s>


<s>
void
MBlazeOperand
::
print
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
Immediate
:
getImm
(
)
->
print
(
OS
)
;
break
;
case
Register
:
OS
<<
"<register R"
;
OS
<<
getMBlazeRegisterNumbering
(
getReg
(
)
)
<<
">"
;
break
;
case
Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
case
Memory
:
{
OS
<<
"<memory R"
;
OS
<<
getMBlazeRegisterNumbering
(
getMemBase
(
)
)
;
OS
<<
", "
;
unsigned
RegOff
=
getMemOffReg
(
)
;
if
(
RegOff
)
OS
<<
"R"
<<
getMBlazeRegisterNumbering
(
RegOff
)
;
else
OS
<<
getMemOff
(
)
;
OS
<<
">"
;
}
break
;
case
Fsl
:
getFslImm
(
)
->
print
(
OS
)
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

MBlaze
MBlaze
"<register R"
MBlaze
">"
"'"
"'"
"<memory R"
MBlaze
", "
"R"
MBlaze
">"


"Error occured during parse section {0}"

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


"  r%d def in insn %d isn't convertible\n"

"  r%d use in insn %d isn't convertible\n"

Check REF 's chain to add new insns into a queue and find registers requiring conversion . Return true if OK , false if the analysis was aborted .


<s> static void rs6000_finish_atomic_subword ( rtx narrow , rtx wide , rtx shift ) { wide = expand_simple_binop ( SImode , LSHIFTRT , wide , shift , wide , 1 , OPTAB_LIB_WIDEN ) ; emit_move_insn ( narrow , gen_lowpart ( GET_MODE ( narrow ) , wide ) ) ; } </s>

A subroutine of the various atomic expanders . For sub-word operands , extract WIDE to NARROW via SHIFT .


<s> int frv_emit_cond_branch ( rtx operands [ ] ) { rtx test_rtx ; rtx label_ref ; rtx if_else ; enum rtx_code test = GET_CODE ( operands [ 0 ] ) ; rtx cc_reg = frv_emit_comparison ( test , operands [ 1 ] , operands [ 2 ] ) ; machine_mode cc_mode = GET_MODE ( cc_reg ) ; label_ref = gen_rtx_LABEL_REF ( VOIDmode , operands [ 3 ] ) ; test_rtx = gen_rtx_fmt_ee ( test , cc_mode , cc_reg , const0_rtx ) ; if_else = gen_rtx_IF_THEN_ELSE ( cc_mode , test_rtx , label_ref , pc_rtx ) ; emit_jump_insn ( gen_rtx_SET ( pc_rtx , if_else ) ) ; return TRUE ; } </s>

Emit code for a conditional branch . The comparison operands were previously stored in frv_compare_op0 and frv_compare_op1 . XXX : I originally wanted to add a clobber of a CCR register to use in conditional execution , but that confuses the rest of the compiler .


<s> static bool nvptx_function_ok_for_sibcall ( tree , tree ) { return false ; } </s>

Decide whether we can make a sibling call to a function . For ptx , we ca n't .


<s>
const
char
*
MipsAsmPrinter
::
getCurrentABIString
(
)
const
{
switch
(
Subtarget
->
getTargetABI
(
)
)
{
case
MipsSubtarget
::
O32
:
return
"abi32"
;
case
MipsSubtarget
::
N32
:
return
"abiN32"
;
case
MipsSubtarget
::
N64
:
return
"abi64"
;
case
MipsSubtarget
::
EABI
:
return
"eabi32"
;
default
:
break
;
}
llvm_unreachable
(
"Unknown Mips ABI"
)
;
return
;
}
</s>


<s> static bool mmix_rtx_costs ( rtx x ATTRIBUTE_UNUSED , int code ATTRIBUTE_UNUSED , int outer_code ATTRIBUTE_UNUSED , int * total ATTRIBUTE_UNUSED ) { return false ; } </s>


<s> unsigned X86RegisterInfo :: getFrameRegister ( MachineFunction & MF ) const { return hasFP ( MF ) ? FramePtr : StackPtr ; } </s>


<s> void MOSAsmPrinter :: emitJumpTableInfo ( ) { const DataLayout & DL = MF -> getDataLayout ( ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; if ( ! MJTI ) return ; assert ( MJTI -> getEntryKind ( ) == MachineJumpTableInfo :: EK_BlockAddress ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; if ( JT . empty ( ) ) return ; const Function & F = MF -> getFunction ( ) ; const TargetLoweringObjectFile & TLOF = getObjFileLowering ( ) ; bool JTInDiffSection = ! TLOF . shouldPutJumpTableInFunctionSection ( false , F ) ; if ( JTInDiffSection ) { MCSection * ReadOnlySection = TLOF . getSectionForJumpTable ( F , TM ) ; OutStreamer -> SwitchSection ( ReadOnlySection ) ; } emitAlignment ( Align ( MJTI -> getEntryAlignment ( DL ) ) ) ; if ( ! JTInDiffSection ) OutStreamer -> emitDataRegion ( MCDR_DataRegionJT32 ) ; for ( const auto & JTI : enumerate ( JT ) ) { const std :: vector < MachineBasicBlock * > & JTBBs = JTI . value ( ) . MBBs ; if ( JTBBs . empty ( ) ) continue ; MCSymbol * JTISymbol = GetJTISymbol ( JTI . index ( ) ) ; OutStreamer -> emitLabel ( JTISymbol ) ; for ( const MachineBasicBlock * JTBB : JTBBs ) { OutStreamer -> emitValue ( MCSymbolRefExpr :: create ( JTBB -> getSymbol ( ) , MCSymbolRefExpr :: VK_MOS_ADDR16_LO , OutContext ) , 1 ) ; } for ( const MachineBasicBlock * JTBB : JTBBs ) { OutStreamer -> emitValue ( MCSymbolRefExpr :: create ( JTBB -> getSymbol ( ) , MCSymbolRefExpr :: VK_MOS_ADDR16_HI , OutContext ) , 1 ) ; } } if ( ! JTInDiffSection ) OutStreamer -> emitDataRegion ( MCDR_DataRegionEnd ) ; } </s>

Print assembly representations of the jump tables used by the current function to the current output stream .


<s> void arm_init_cumulative_args ( CUMULATIVE_ARGS * pcum , tree fntype , rtx libname , tree fndecl ATTRIBUTE_UNUSED ) { if ( fntype ) pcum -> pcs_variant = arm_get_pcs_model ( fntype , fndecl ) ; else pcum -> pcs_variant = arm_pcs_default ; if ( pcum -> pcs_variant <= ARM_PCS_AAPCS_LOCAL ) { if ( arm_libcall_uses_aapcs_base ( libname ) ) pcum -> pcs_variant = ARM_PCS_AAPCS ; pcum -> aapcs_ncrn = pcum -> aapcs_next_ncrn = 0 ; pcum -> aapcs_reg = NULL_RTX ; pcum -> aapcs_partial = 0 ; pcum -> aapcs_arg_processed = false ; pcum -> aapcs_cprc_slot = - 1 ; pcum -> can_split = true ; if ( pcum -> pcs_variant != ARM_PCS_AAPCS ) { int i ; for ( i = 0 ; i < ARM_NUM_COPROC_SLOTS ; i ++ ) { pcum -> aapcs_cprc_failed [ i ] = false ; aapcs_cp_arg_layout [ i ] . cum_init ( pcum , fntype , libname , fndecl ) ; } } return ; } pcum -> nregs = 0 ; pcum -> iwmmxt_nregs = 0 ; pcum -> can_split = true ; pcum -> named_count = 0 ; pcum -> nargs = 0 ; if ( TARGET_REALLY_IWMMXT && fntype ) { tree fn_arg ; for ( fn_arg = TYPE_ARG_TYPES ( fntype ) ; fn_arg ; fn_arg = TREE_CHAIN ( fn_arg ) ) pcum -> named_count += 1 ; if ( ! pcum -> named_count ) pcum -> named_count = INT_MAX ; } } </s>

Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is NULL .


<s> int ARMTTIImpl :: getIntImmCost ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) { if ( ( Opcode == Instruction :: SDiv || Opcode == Instruction :: UDiv || Opcode == Instruction :: SRem || Opcode == Instruction :: URem ) && Idx == 1 ) return 0 ; return getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> Candidate ( const SUnit * SU_ , int Priority_ = 0 ) : SU ( SU_ ) , Priority ( Priority_ ) { } </s>


<s> static int round_frame_size ( int size ) { return ( ( size + STACK_BOUNDARY / BITS_PER_UNIT - 1 ) & - STACK_BOUNDARY / BITS_PER_UNIT ) ; } </s>


<s> rtx ix86_function_value ( tree valtype , tree fntype_or_decl , bool outgoing ATTRIBUTE_UNUSED ) { enum machine_mode natmode = type_natural_mode ( valtype ) ; if ( TARGET_64BIT ) { rtx ret = construct_container ( natmode , TYPE_MODE ( valtype ) , valtype , 1 , REGPARM_MAX , SSE_REGPARM_MAX , x86_64_int_return_registers , 0 ) ; if ( ! ret ) ret = gen_rtx_REG ( TYPE_MODE ( valtype ) , 0 ) ; return ret ; } else { tree fn = NULL_TREE , fntype ; if ( fntype_or_decl && DECL_P ( fntype_or_decl ) ) fn = fntype_or_decl ; fntype = fn ? TREE_TYPE ( fn ) : fntype_or_decl ; return gen_rtx_REG ( TYPE_MODE ( valtype ) , ix86_value_regno ( natmode , fn , fntype ) ) ; } } </s>

Define how to find the value returned by a function . VALTYPE is the data type of the value ( as a tree ) . If the precise function being called is known , FUNC is its FUNCTION_DECL ; otherwise , FUNC is 0 .


<s> static rtx or1k_delegitimize_address ( rtx x ) { if ( GET_CODE ( x ) == UNSPEC ) { if ( XINT ( x , 1 ) == UNSPEC_GOTOFF ) return XVECEXP ( x , 0 , 0 ) ; } else if ( MEM_P ( x ) ) { rtx addr = XEXP ( x , 0 ) ; if ( GET_CODE ( addr ) == LO_SUM && XEXP ( addr , 0 ) == pic_offset_table_rtx ) { rtx inner = XEXP ( addr , 1 ) ; if ( GET_CODE ( inner ) == UNSPEC && XINT ( inner , 1 ) == UNSPEC_GOT ) return XVECEXP ( inner , 0 , 0 ) ; } } return delegitimize_mem_from_attrs ( x ) ; } </s>

Worker for TARGET_DELEGITIMIZE_ADDRESS . In the name of slightly smaller debug output , and to cater to general assembler lossage , recognize PIC+GOTOFF and turn it back into a direct symbol reference .


<s> std :: pair < const TargetRegisterClass * , uint8_t > AArch64TargetLowering :: findRepresentativeClass ( MVT VT ) const { const TargetRegisterClass * RRC = nullptr ; uint8_t Cost = 1 ; switch ( VT . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( VT ) ; case MVT :: v4i64 : RRC = & AArch64 :: QPairRegClass ; Cost = 2 ; break ; case MVT :: v8i64 : RRC = & AArch64 :: QQuadRegClass ; Cost = 4 ; break ; } return std :: make_pair ( RRC , Cost ) ; } </s>

Return the largest legal super-reg register class of the register class for the specified type and its associated `` cost '' .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; if ( MergeInit ) AU . addRequired < AAResultsWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool shouldInsertFencesForAtomic ( const Instruction * I ) const override { return isa < LoadInst > ( I ) || isa < StoreInst > ( I ) ; } </s>

Helper functions for atomic operations .


<s> BitVector AArch64RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const AArch64FrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AArch64 :: SP ) ; Reserved . set ( AArch64 :: XZR ) ; Reserved . set ( AArch64 :: WSP ) ; Reserved . set ( AArch64 :: WZR ) ; if ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) { Reserved . set ( AArch64 :: FP ) ; Reserved . set ( AArch64 :: W29 ) ; } if ( MF . getSubtarget < AArch64Subtarget > ( ) . isX18Reserved ( ) ) { Reserved . set ( AArch64 :: X18 ) ; Reserved . set ( AArch64 :: W18 ) ; } if ( hasBasePointer ( MF ) ) { Reserved . set ( AArch64 :: X19 ) ; Reserved . set ( AArch64 :: W19 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static bool ix86_expand_sse_fp_minmax ( rtx dest , enum rtx_code code , rtx cmp_op0 , rtx cmp_op1 , rtx if_true , rtx if_false ) { machine_mode mode ; bool is_min ; rtx tmp ; if ( code == LT ) ; else if ( code == UNGE ) std :: swap ( if_true , if_false ) ; else return false ; if ( rtx_equal_p ( cmp_op0 , if_true ) && rtx_equal_p ( cmp_op1 , if_false ) ) is_min = true ; else if ( rtx_equal_p ( cmp_op1 , if_true ) && rtx_equal_p ( cmp_op0 , if_false ) ) is_min = false ; else return false ; mode = GET_MODE ( dest ) ; if ( ! flag_finite_math_only || flag_signed_zeros ) { int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX ; rtvec v ; if_true = force_reg ( mode , if_true ) ; v = gen_rtvec ( 2 , if_true , if_false ) ; tmp = gen_rtx_UNSPEC ( mode , v , u ) ; } else { code = is_min ? SMIN : SMAX ; if ( MEM_P ( if_true ) && MEM_P ( if_false ) ) if_true = force_reg ( mode , if_true ) ; tmp = gen_rtx_fmt_ee ( code , mode , if_true , if_false ) ; } emit_insn ( gen_rtx_SET ( dest , tmp ) ) ; return true ; } </s>

Detect conditional moves that exactly match min/max operational semantics . Note that this is IEEE safe , as long as we do n't interchange the operands . Returns FALSE if this conditional move does n't match a MIN/MAX , and TRUE if the operation is successful and instructions are emitted .


<s>
const
MCPhysReg
*
AArch64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_AArch64_NoRegs_SaveList
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_AArch64_AllRegs_SaveList
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
CXX_FAST_TLS
)
return
MF
->
getInfo
<
AArch64FunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_AArch64_CXX_TLS_Darwin_PE_SaveList
:
CSR_AArch64_CXX_TLS_Darwin_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
->
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_AArch64_AAPCS_SwiftError_SaveList
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
PreserveMost
)
return
CSR_AArch64_RT_MostRegs_SaveList
;
else
return
CSR_AArch64_AAPCS_SaveList
;
}
</s>


<s> void X86PassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( new X86ExecutionDepsFix ( ) ) ; if ( UseVZeroUpper ) addPass ( createX86IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86FixupBWInsts ( ) ) ; addPass ( createX86PadShortFunctions ( ) ) ; addPass ( createX86FixupLEAs ( ) ) ; addPass ( createX86EvexToVexInsts ( ) ) ; } } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
StringRef
getPassName
(
)
const
override
{
return
"WebAssembly late peephole optimizer"
;
}
</s>

getPassName - Return a nice clean name for a pass .

WebAssembly
"WebAssembly late peephole optimizer"


<s> bool MBlazeFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool SystemZAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & OS ) { if ( ExtraCode && * ExtraCode == 'n' ) { if ( ! MI -> getOperand ( OpNo ) . isImm ( ) ) return true ; OS << - int64_t ( MI -> getOperand ( OpNo ) . getImm ( ) ) ; } else { SystemZMCInstLower Lower ( MF -> getContext ( ) , * this ) ; MCOperand MO ( Lower . lowerOperand ( MI -> getOperand ( OpNo ) ) ) ; SystemZInstPrinter :: printOperand ( MO , OS ) ; } return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> void arm_load_pic_register ( unsigned long saved_regs ATTRIBUTE_UNUSED ) { rtx l1 , labelno , pic_tmp , pic_rtx , pic_reg ; if ( crtl -> uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE ) return ; gcc_assert ( flag_pic ) ; pic_reg = cfun -> machine -> pic_reg ; if ( TARGET_VXWORKS_RTP ) { pic_rtx = gen_rtx_SYMBOL_REF ( Pmode , VXWORKS_GOTT_BASE ) ; pic_rtx = gen_rtx_CONST ( Pmode , pic_rtx ) ; emit_insn ( gen_pic_load_addr_32bit ( pic_reg , pic_rtx ) ) ; emit_insn ( gen_rtx_SET ( Pmode , pic_reg , gen_rtx_MEM ( Pmode , pic_reg ) ) ) ; pic_tmp = gen_rtx_SYMBOL_REF ( Pmode , VXWORKS_GOTT_INDEX ) ; emit_insn ( gen_pic_offset_arm ( pic_reg , pic_reg , pic_tmp ) ) ; } else { labelno = GEN_INT ( pic_labelno ++ ) ; l1 = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , labelno ) , UNSPEC_PIC_LABEL ) ; l1 = gen_rtx_CONST ( VOIDmode , l1 ) ; pic_rtx = plus_constant ( Pmode , l1 , TARGET_ARM ? 8 : 4 ) ; pic_rtx = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , pic_rtx ) , UNSPEC_GOTSYM_OFF ) ; pic_rtx = gen_rtx_CONST ( Pmode , pic_rtx ) ; if ( TARGET_32BIT ) { emit_insn ( gen_pic_load_addr_unified ( pic_reg , pic_rtx , labelno ) ) ; } else { if ( arm_pic_register != INVALID_REGNUM && REGNO ( pic_reg ) > LAST_LO_REGNUM ) { pic_tmp = gen_rtx_REG ( SImode , thumb_find_work_register ( saved_regs ) ) ; emit_insn ( gen_pic_load_addr_thumb1 ( pic_tmp , pic_rtx ) ) ; emit_insn ( gen_movsi ( pic_offset_table_rtx , pic_tmp ) ) ; emit_insn ( gen_pic_add_dot_plus_four ( pic_reg , pic_reg , labelno ) ) ; } else if ( arm_pic_register != INVALID_REGNUM && arm_pic_register > LAST_LO_REGNUM && REGNO ( pic_reg ) <= LAST_LO_REGNUM ) { emit_insn ( gen_pic_load_addr_unified ( pic_reg , pic_rtx , labelno ) ) ; emit_move_insn ( gen_rtx_REG ( Pmode , arm_pic_register ) , pic_reg ) ; emit_use ( gen_rtx_REG ( Pmode , arm_pic_register ) ) ; } else emit_insn ( gen_pic_load_addr_unified ( pic_reg , pic_rtx , labelno ) ) ; } } emit_use ( pic_reg ) ; } </s>

Generate code to load the PIC register . In thumb mode SCRATCH is a low register .


"MMIX Internal: This is not a constant:"

Return the bit-value for a const_int or const_double .


<s> static void sparc_init_builtins ( void ) { if ( TARGET_FPU ) sparc_fpu_init_builtins ( ) ; if ( TARGET_VIS ) sparc_vis_init_builtins ( ) ; } </s>

Implement the TARGET_INIT_BUILTINS target hook . Create builtin functions for special SPARC instructions .


<s> void Mips16RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


Determine whether a memory reference takes one ( based off of the GP pointer ) , two ( normal ) , or three ( label + reg ) instructions , and bump the appropriate counter for -mstats .


<s> static void msp430_print_operand_raw ( FILE * file , rtx op ) { HOST_WIDE_INT i ; switch ( GET_CODE ( op ) ) { case REG : fprintf ( file , "%s" , reg_names [ REGNO ( op ) ] ) ; break ; case CONST_INT : i = INTVAL ( op ) ; if ( TARGET_ASM_HEX ) fprintf ( file , "%#" HOST_WIDE_INT_PRINT "x" , i ) ; else fprintf ( file , "%" HOST_WIDE_INT_PRINT "d" , i ) ; break ; case CONST : case PLUS : case MINUS : case SYMBOL_REF : case LABEL_REF : output_addr_const ( file , op ) ; break ; default : print_rtl ( file , op ) ; break ; } } </s>

Common code for msp430_print_operand ...


<s> void AMDGPUAsmBackend :: relaxInstruction ( MCInst & Inst , const MCSubtargetInfo & STI ) const { MCInst Res ; unsigned RelaxedOpcode = AMDGPU :: getSOPPWithRelaxation ( Inst . getOpcode ( ) ) ; Res . setOpcode ( RelaxedOpcode ) ; Res . addOperand ( Inst . getOperand ( 0 ) ) ; Inst = std :: move ( Res ) ; return ; } </s>

Relax the instruction in the given fragment to the next wider instruction .

AMDGPU AMDGPU AMDGPU::getSOPPWithRelaxation 0


"boolean registers required for the floating-point option"

"-f%s is not supported with CONST16 instructions"

"PIC is required but not supported with CONST16 instructions"

Set global variables as needed for the options enabled .


<s>
SDValue
XCoreTargetLowering
::
LowerCall
(
SDValue
Chain
,
SDValue
Callee
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
bool
&
isTailCall
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .

XCore
XCore
ISD::OutputArg
ISD::InputArg
"Unsupported calling convention"


<s> int arm_mac_accumulator_is_mul_result ( rtx producer , rtx consumer ) { rtx mul = PATTERN ( producer ) ; rtx mac = PATTERN ( consumer ) ; rtx mul_result ; rtx mac_op0 , mac_op1 , mac_acc ; if ( GET_CODE ( mul ) == COND_EXEC ) mul = COND_EXEC_CODE ( mul ) ; if ( GET_CODE ( mac ) == COND_EXEC ) mac = COND_EXEC_CODE ( mac ) ; if ( ( GET_CODE ( mul ) != SET || GET_CODE ( XEXP ( mul , 1 ) ) != MULT ) || ( GET_CODE ( mac ) != SET || GET_CODE ( XEXP ( mac , 1 ) ) != PLUS || GET_CODE ( XEXP ( XEXP ( mac , 1 ) , 0 ) ) != MULT ) ) return 0 ; mul_result = XEXP ( mul , 0 ) ; mac_op0 = XEXP ( XEXP ( XEXP ( mac , 1 ) , 0 ) , 0 ) ; mac_op1 = XEXP ( XEXP ( XEXP ( mac , 1 ) , 0 ) , 1 ) ; mac_acc = XEXP ( XEXP ( mac , 1 ) , 1 ) ; return ( reg_overlap_mentioned_p ( mul_result , mac_acc ) && ! reg_overlap_mentioned_p ( mul_result , mac_op0 ) && ! reg_overlap_mentioned_p ( mul_result , mac_op1 ) ) ; } </s>

Return non-zero if the consumer ( a multiply-accumulate instruction ) has an accumulator dependency on the result of the producer ( a multiplication instruction ) and no other dependency on that result .


"********** Prepare For LiveIntervals **********\n"

"LiveIntervals shouldn't be active yet!"

runOnMachineFunction - Emit the function body .


<s> void RISCVFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const RISCVRegisterInfo * RI = STI . getRegisterInfo ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; for ( int ID = MFI . getObjectIndexBegin ( ) , EID = MFI . getObjectIndexEnd ( ) ; ID < EID ; ID ++ ) { if ( MFI . getStackID ( ID ) == TargetStackID :: RISCVVector && ! MFI . isDeadObjectIndex ( ID ) ) { FrameSize = alignTo ( FrameSize , TRI -> getSpillAlignment ( RISCV :: GPRRegClass ) ) ; FrameSize += TRI -> getSpillSize ( RISCV :: GPRRegClass ) ; MFI . setObjectOffset ( ID , - FrameSize ) ; } } Align StackAlign = getStackAlign ( ) ; if ( RI -> needsStackRealignment ( MF ) ) { Align MaxStackAlign = std :: max ( StackAlign , MFI . getMaxAlign ( ) ) ; FrameSize += ( MaxStackAlign . value ( ) - StackAlign . value ( ) ) ; StackAlign = MaxStackAlign ; } uint64_t MaxCallSize = alignTo ( MFI . getMaxCallFrameSize ( ) , StackAlign ) ; MFI . setMaxCallFrameSize ( MaxCallSize ) ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI . setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .

RISCV RISCV RISCV RISCV RISCV::GPRRegClass RISCV::GPRRegClass


<s> void scalar_chain :: emit_conversion_insns ( rtx insns , rtx_insn * after ) { if ( ! control_flow_insn_p ( after ) ) { emit_insn_after ( insns , after ) ; return ; } basic_block bb = BLOCK_FOR_INSN ( after ) ; edge e = find_fallthru_edge ( bb -> succs ) ; gcc_assert ( e ) ; basic_block new_bb = split_edge ( e ) ; emit_insn_after ( insns , BB_HEAD ( new_bb ) ) ; } </s>

Insert generated conversion instruction sequence INSNS after instruction AFTER . New BB may be required in case instruction has EH region attached .


<s> SDNode * PPCDAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * PPCSubTarget -> getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; const Module * M = MF -> getFunction ( ) -> getParent ( ) ; DebugLoc dl ; if ( PPCLowering -> getPointerTy ( CurDAG -> getDataLayout ( ) ) == MVT :: i32 ) { if ( PPCSubTarget -> isTargetELF ( ) ) { GlobalBaseReg = PPC :: R30 ; if ( M -> getPICLevel ( ) == PICLevel :: Small ) { BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MoveGOTtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; MF -> getInfo < PPCFunctionInfo > ( ) -> setUsesPICBase ( true ) ; } else { BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; unsigned TempReg = RegInfo -> createVirtualRegister ( & PPC :: GPRCRegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: UpdateGBR ) , GlobalBaseReg ) . addReg ( TempReg , RegState :: Define ) . addReg ( GlobalBaseReg ) ; MF -> getInfo < PPCFunctionInfo > ( ) -> setUsesPICBase ( true ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: GPRC_NOR0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: G8RC_NOX0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR8 ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR8 ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , PPCLowering -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

PowerPC PPC PPC PPC MVT::i32 PPC PPC::R30 PPC::MoveGOTtoLR PPC::MFLR PPC PPC::MovePCtoLR PPC::MFLR PPC::GPRCRegClass PPC::UpdateGBR PPC PPC::GPRC_NOR0RegClass PPC::MovePCtoLR PPC::MFLR PPC::G8RC_NOX0RegClass PPC::MovePCtoLR8 PPC::MFLR8 PPC


<s> bool AMDGPUAAResult :: pointsToConstantMemory ( const MemoryLocation & Loc , AAQueryInfo & AAQI , bool OrLocal ) { unsigned AS = Loc . Ptr -> getType ( ) -> getPointerAddressSpace ( ) ; if ( AS == AMDGPUAS :: CONSTANT_ADDRESS || AS == AMDGPUAS :: CONSTANT_ADDRESS_32BIT ) return true ; const Value * Base = GetUnderlyingObject ( Loc . Ptr , DL ) ; AS = Base -> getType ( ) -> getPointerAddressSpace ( ) ; if ( AS == AMDGPUAS :: CONSTANT_ADDRESS || AS == AMDGPUAS :: CONSTANT_ADDRESS_32BIT ) return true ; if ( const GlobalVariable * GV = dyn_cast < GlobalVariable > ( Base ) ) { if ( GV -> isConstant ( ) ) return true ; } else if ( const Argument * Arg = dyn_cast < Argument > ( Base ) ) { const Function * F = Arg -> getParent ( ) ; switch ( F -> getCallingConv ( ) ) { default : return AAResultBase :: pointsToConstantMemory ( Loc , AAQI , OrLocal ) ; case CallingConv :: AMDGPU_LS : case CallingConv :: AMDGPU_HS : case CallingConv :: AMDGPU_ES : case CallingConv :: AMDGPU_GS : case CallingConv :: AMDGPU_VS : case CallingConv :: AMDGPU_PS : case CallingConv :: AMDGPU_CS : case CallingConv :: AMDGPU_KERNEL : case CallingConv :: SPIR_KERNEL : break ; } unsigned ArgNo = Arg -> getArgNo ( ) ; if ( F -> hasParamAttribute ( ArgNo , Attribute :: NoAlias ) && ( F -> hasParamAttribute ( ArgNo , Attribute :: ReadNone ) || F -> hasParamAttribute ( ArgNo , Attribute :: ReadOnly ) ) ) { return true ; } } return AAResultBase :: pointsToConstantMemory ( Loc , AAQI , OrLocal ) ; } </s>

A convenience wrapper around the primary pointsToConstantMemory interface .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU


<s> void X86IntelInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { printInstFlags ( MI , OS ) ; if ( MI -> getOpcode ( ) == X86 :: DATA16_PREFIX && STI . getFeatureBits ( ) [ X86 :: Mode16Bit ] ) { OS << "\tdata32" ; } else printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAnyX86InstComments ( MI , * CommentStream , MII ) ; } </s>

Print the specified MCInst to the specified raw_ostream .