<s> static void gcn_goacc_reduction_teardown ( gcall * call ) { gimple_stmt_iterator gsi = gsi_for_stmt ( call ) ; tree lhs = gimple_call_lhs ( call ) ; tree var = gimple_call_arg ( call , 2 ) ; int level = TREE_INT_CST_LOW ( gimple_call_arg ( call , 3 ) ) ; gimple_seq seq = NULL ; push_gimplify_context ( true ) ; if ( level == GOMP_DIM_WORKER ) { tree var_type = TREE_TYPE ( var ) ; tree offset = gimple_call_arg ( call , 5 ) ; tree decl = gcn_goacc_get_worker_red_decl ( var_type , TREE_INT_CST_LOW ( offset ) ) ; var = decl ; } if ( level != GOMP_DIM_GANG ) { tree ref_to_res = gimple_call_arg ( call , 1 ) ; if ( ! integer_zerop ( ref_to_res ) ) gimplify_assign ( build_simple_mem_ref ( ref_to_res ) , var , & seq ) ; } if ( lhs ) gimplify_assign ( lhs , unshare_expr ( var ) , & seq ) ; pop_gimplify_context ( NULL ) ; gsi_replace_with_seq ( & gsi , seq , true ) ; } </s>


<s> static bool xstormy16_return_in_memory ( tree type , tree fntype ATTRIBUTE_UNUSED ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; return ( size == - 1 || size > UNITS_PER_WORD * NUM_ARGUMENT_REGISTERS ) ; } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


<s> MachineBasicBlock :: iterator MINA32FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> const NVPTXRegisterInfo * getRegisterInfo ( ) const override { return getSubtargetImpl ( ) -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool X86InstrInfo :: findCommutedOpIndices ( MachineInstr * MI , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { switch ( MI -> getOpcode ( ) ) { case X86 :: CMPPDrri : case X86 :: CMPPSrri : case X86 :: VCMPPDrri : case X86 :: VCMPPSrri : case X86 :: VCMPPDYrri : case X86 :: VCMPPSYrri : { unsigned Imm = MI -> getOperand ( 3 ) . getImm ( ) & 0x7 ; switch ( Imm ) { case 0x00 : case 0x03 : case 0x04 : case 0x07 : return fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , 1 , 2 ) ; } return false ; } case X86 :: VFMADDPDr231r : case X86 :: VFMADDPSr231r : case X86 :: VFMADDSDr231r : case X86 :: VFMADDSSr231r : case X86 :: VFMSUBPDr231r : case X86 :: VFMSUBPSr231r : case X86 :: VFMSUBSDr231r : case X86 :: VFMSUBSSr231r : case X86 :: VFNMADDPDr231r : case X86 :: VFNMADDPSr231r : case X86 :: VFNMADDSDr231r : case X86 :: VFNMADDSSr231r : case X86 :: VFNMSUBPDr231r : case X86 :: VFNMSUBPSr231r : case X86 :: VFNMSUBSDr231r : case X86 :: VFNMSUBSSr231r : case X86 :: VFMADDPDr231rY : case X86 :: VFMADDPSr231rY : case X86 :: VFMSUBPDr231rY : case X86 :: VFMSUBPSr231rY : case X86 :: VFNMADDPDr231rY : case X86 :: VFNMADDPSr231rY : case X86 :: VFNMSUBPDr231rY : case X86 :: VFNMSUBPSr231rY : return fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , 2 , 3 ) ; default : return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; } return false ; } </s>

Returns true iff the routine could find two commutable operands in the given machine instruction .


<s> bool SIMachineFunctionInfo :: removeDeadFrameIndices ( MachineFrameInfo & MFI , bool ResetSGPRSpillStackIDs ) { for ( auto & R : make_early_inc_range ( SGPRToVGPRSpills ) ) { if ( R . first != FramePointerSaveIndex && R . first != BasePointerSaveIndex ) { MFI . RemoveStackObject ( R . first ) ; SGPRToVGPRSpills . erase ( R . first ) ; } } bool HaveSGPRToMemory = false ; if ( ResetSGPRSpillStackIDs ) { for ( int i = MFI . getObjectIndexBegin ( ) , e = MFI . getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( i != FramePointerSaveIndex && i != BasePointerSaveIndex ) { if ( MFI . getStackID ( i ) == TargetStackID :: SGPRSpill ) { MFI . setStackID ( i , TargetStackID :: Default ) ; HaveSGPRToMemory = true ; } } } } for ( auto & R : VGPRToAGPRSpills ) { if ( R . second . IsDead ) MFI . RemoveStackObject ( R . first ) ; } return HaveSGPRToMemory ; } </s>

If ResetSGPRSpillStackIDs is true , reset the stack ID from sgpr-spill to the default stack .


<s> static unsigned findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const M68kRegisterInfo * TRI ) { const MachineFunction * MF = MBB . getParent ( ) ; if ( MF -> callsEHReturn ( ) ) return 0 ; const TargetRegisterClass & AvailableRegs = * TRI -> getRegsForTailCall ( * MF ) ; if ( MBBI == MBB . end ( ) ) return 0 ; switch ( MBBI -> getOpcode ( ) ) { default : return 0 ; case TargetOpcode :: PATCHABLE_RET : case M68k :: RET : { SmallSet < uint16_t , 8 > Uses ; for ( unsigned i = 0 , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } for ( auto CS : AvailableRegs ) if ( ! Uses . count ( CS ) ) return CS ; } } return 0 ; } </s>

findDeadCallerSavedReg - Return a caller-saved register that is n't live when it reaches the `` return '' instruction .


<s> bool csky_inlinable_constant ( HOST_WIDE_INT value ) { HOST_WIDE_INT x , y ; return ( ! ( CSKY_TARGET_ARCH ( CK802 ) || CSKY_TARGET_ARCH ( CK801 ) ) && try_csky_constant_tricks ( value , & x , & y ) ) ; } </s>

This is a helper function for the Uo constraint for movsi patterns .


<s> bool X86TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , bool * Fast ) const { if ( Fast ) { switch ( VT . getSizeInBits ( ) ) { default : * Fast = true ; break ; case 128 : * Fast = ! Subtarget . isUnalignedMem16Slow ( ) ; break ; case 256 : * Fast = ! Subtarget . isUnalignedMem32Slow ( ) ; break ; } } return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> unsigned X86InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex , unsigned & MemBytes ) const { if ( isFrameStoreOpcode ( MI . getOpcode ( ) , MemBytes ) ) if ( MI . getOperand ( X86 :: AddrNumOperands ) . getSubReg ( ) == 0 && isFrameOperand ( MI , 0 , FrameIndex ) ) return MI . getOperand ( X86 :: AddrNumOperands ) . getReg ( ) ; return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> static void add_to_dispatch_window ( rtx_insn * insn ) { int byte_len ; dispatch_windows * window_list ; dispatch_windows * next_list ; dispatch_windows * window0_list ; enum insn_path path ; enum dispatch_group insn_group ; bool insn_fits ; int num_insn ; int num_uops ; int window_num ; int insn_num_uops ; int sum ; if ( INSN_CODE ( insn ) < 0 ) return ; byte_len = ix86_min_insn_size ( insn ) ; window_list = dispatch_window_list ; next_list = window_list -> next ; path = get_insn_path ( insn ) ; insn_group = get_insn_group ( insn ) ; if ( next_list ) window_list = dispatch_window_list -> next ; if ( path == path_single ) insn_num_uops = 1 ; else if ( path == path_double ) insn_num_uops = 2 ; else insn_num_uops = ( int ) path ; num_insn = window_list -> num_insn ; num_uops = window_list -> num_uops ; window_num = window_list -> window_num ; insn_fits = fits_dispatch_window ( insn ) ; if ( num_insn >= MAX_INSN || num_uops + insn_num_uops > MAX_INSN || ! ( insn_fits ) ) { window_num = ~ window_num & 1 ; window_list = allocate_next_window ( window_num ) ; } if ( window_num == 0 ) { add_insn_window ( insn , window_list , insn_num_uops ) ; if ( window_list -> num_insn >= MAX_INSN && insn_group == disp_branch ) { process_end_window ( ) ; return ; } } else if ( window_num == 1 ) { window0_list = window_list -> prev ; sum = window0_list -> window_size + window_list -> window_size ; if ( sum == 32 || ( byte_len + sum ) >= 48 ) { process_end_window ( ) ; window_list = dispatch_window_list ; } add_insn_window ( insn , window_list , insn_num_uops ) ; } else gcc_unreachable ( ) ; if ( is_end_basic_block ( insn_group ) ) { process_end_window ( ) ; return ; } } </s>

Adds a scheduled instruction , INSN , to the current dispatch window . If the total bytes of instructions or the number of instructions in the window exceed allowable , it allocates a new window .


<s> bool AArch64AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { OS . write_zeros ( Count % 4 ) ; Count /= 4 ; for ( uint64_t i = 0 ; i != Count ; ++ i ) support :: endian :: write < uint32_t > ( OS , 0xd503201f , Endian ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


"invalid argument given to %<-mharden-sls=%>"

"%<%s%> must be by itself for %<-mharden-sls=%>"

"invalid argument %<%s%> for %<-mharden-sls=%>"

As of yet we only allow setting these options globally , in the future we may allow setting them per function .


<s> MSP430Subtarget & MSP430Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { ParseSubtargetFeatures ( "generic" , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> static char * vms_construct_include_filename ( const char * fname , cpp_dir * dir ) { size_t dlen , flen ; char * path ; const char * fbasename = lbasename ( fname ) ; size_t i ; dlen = dir -> len ; flen = strlen ( fbasename ) + 2 ; path = XNEWVEC ( char , dlen + 1 + flen + 1 ) ; memcpy ( path , dir -> name , dlen ) ; if ( dlen && ! IS_DIR_SEPARATOR ( path [ dlen - 1 ] ) ) path [ dlen ++ ] = '/' ; for ( i = 0 ; i < flen ; i ++ ) if ( fbasename [ i ] == '.' ) break ; else path [ dlen + i ] = TOLOWER ( fbasename [ i ] ) ; path [ dlen + i + 0 ] = '.' ; path [ dlen + i + 1 ] = 'h' ; path [ dlen + i + 2 ] = 0 ; return path ; } </s>

Canonicalize the filename ( remove directory prefix , force the .h extension ) , and append it to the directory to create the path , but do n't turn / into // or // into /// ; // may be a namespace escape .


<s> const char * NVPTXTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case NVPTXISD :: CALL : return "NVPTXISD::CALL" ; case NVPTXISD :: RET_FLAG : return "NVPTXISD::RET_FLAG" ; case NVPTXISD :: Wrapper : return "NVPTXISD::Wrapper" ; case NVPTXISD :: NVBuiltin : return "NVPTXISD::NVBuiltin" ; case NVPTXISD :: DeclareParam : return "NVPTXISD::DeclareParam" ; case NVPTXISD :: DeclareScalarParam : return "NVPTXISD::DeclareScalarParam" ; case NVPTXISD :: DeclareRet : return "NVPTXISD::DeclareRet" ; case NVPTXISD :: DeclareRetParam : return "NVPTXISD::DeclareRetParam" ; case NVPTXISD :: PrintCall : return "NVPTXISD::PrintCall" ; case NVPTXISD :: LoadParam : return "NVPTXISD::LoadParam" ; case NVPTXISD :: StoreParam : return "NVPTXISD::StoreParam" ; case NVPTXISD :: StoreParamS32 : return "NVPTXISD::StoreParamS32" ; case NVPTXISD :: StoreParamU32 : return "NVPTXISD::StoreParamU32" ; case NVPTXISD :: MoveToParam : return "NVPTXISD::MoveToParam" ; case NVPTXISD :: CallArgBegin : return "NVPTXISD::CallArgBegin" ; case NVPTXISD :: CallArg : return "NVPTXISD::CallArg" ; case NVPTXISD :: LastCallArg : return "NVPTXISD::LastCallArg" ; case NVPTXISD :: CallArgEnd : return "NVPTXISD::CallArgEnd" ; case NVPTXISD :: CallVoid : return "NVPTXISD::CallVoid" ; case NVPTXISD :: CallVal : return "NVPTXISD::CallVal" ; case NVPTXISD :: CallSymbol : return "NVPTXISD::CallSymbol" ; case NVPTXISD :: Prototype : return "NVPTXISD::Prototype" ; case NVPTXISD :: MoveParam : return "NVPTXISD::MoveParam" ; case NVPTXISD :: MoveRetval : return "NVPTXISD::MoveRetval" ; case NVPTXISD :: MoveToRetval : return "NVPTXISD::MoveToRetval" ; case NVPTXISD :: StoreRetval : return "NVPTXISD::StoreRetval" ; case NVPTXISD :: PseudoUseParam : return "NVPTXISD::PseudoUseParam" ; case NVPTXISD :: RETURN : return "NVPTXISD::RETURN" ; case NVPTXISD :: CallSeqBegin : return "NVPTXISD::CallSeqBegin" ; case NVPTXISD :: CallSeqEnd : return "NVPTXISD::CallSeqEnd" ; case NVPTXISD :: LoadV2 : return "NVPTXISD::LoadV2" ; case NVPTXISD :: LoadV4 : return "NVPTXISD::LoadV4" ; case NVPTXISD :: LDGV2 : return "NVPTXISD::LDGV2" ; case NVPTXISD :: LDGV4 : return "NVPTXISD::LDGV4" ; case NVPTXISD :: LDUV2 : return "NVPTXISD::LDUV2" ; case NVPTXISD :: LDUV4 : return "NVPTXISD::LDUV4" ; case NVPTXISD :: StoreV2 : return "NVPTXISD::StoreV2" ; case NVPTXISD :: StoreV4 : return "NVPTXISD::StoreV4" ; } } </s>

getTargetNodeName - This method returns the name of a target specific

NVPTX NVPTX 0 NVPTXISD::CALL "NVPTXISD::CALL" NVPTXISD::RET_FLAG "NVPTXISD::RET_FLAG" NVPTXISD::Wrapper "NVPTXISD::Wrapper" NVPTXISD::NVBuiltin "NVPTXISD::NVBuiltin" NVPTXISD::DeclareParam "NVPTXISD::DeclareParam" NVPTXISD::DeclareScalarParam "NVPTXISD::DeclareScalarParam" NVPTXISD::DeclareRet "NVPTXISD::DeclareRet" NVPTXISD::DeclareRetParam "NVPTXISD::DeclareRetParam" NVPTXISD::PrintCall "NVPTXISD::PrintCall" NVPTXISD::LoadParam "NVPTXISD::LoadParam" NVPTXISD::StoreParam "NVPTXISD::StoreParam" NVPTXISD::StoreParamS32 "NVPTXISD::StoreParamS32" NVPTXISD::StoreParamU32 "NVPTXISD::StoreParamU32" NVPTXISD::MoveToParam "NVPTXISD::MoveToParam" NVPTXISD::CallArgBegin "NVPTXISD::CallArgBegin" NVPTXISD::CallArg "NVPTXISD::CallArg" NVPTXISD::LastCallArg "NVPTXISD::LastCallArg" NVPTXISD::CallArgEnd "NVPTXISD::CallArgEnd" NVPTXISD::CallVoid "NVPTXISD::CallVoid" NVPTXISD::CallVal "NVPTXISD::CallVal" NVPTXISD::CallSymbol "NVPTXISD::CallSymbol" NVPTXISD::Prototype "NVPTXISD::Prototype" NVPTXISD::MoveParam "NVPTXISD::MoveParam" NVPTXISD::MoveRetval "NVPTXISD::MoveRetval" NVPTXISD::MoveToRetval "NVPTXISD::MoveToRetval" NVPTXISD::StoreRetval "NVPTXISD::StoreRetval" NVPTXISD::PseudoUseParam "NVPTXISD::PseudoUseParam" NVPTXISD::RETURN "NVPTXISD::RETURN" NVPTXISD::CallSeqBegin "NVPTXISD::CallSeqBegin" NVPTXISD::CallSeqEnd "NVPTXISD::CallSeqEnd" NVPTXISD::LoadV2 "NVPTXISD::LoadV2" NVPTXISD::LoadV4 "NVPTXISD::LoadV4" NVPTXISD::LDGV2 "NVPTXISD::LDGV2" NVPTXISD::LDGV4 "NVPTXISD::LDGV4" NVPTXISD::LDUV2 "NVPTXISD::LDUV2" NVPTXISD::LDUV4 "NVPTXISD::LDUV4" NVPTXISD::StoreV2 "NVPTXISD::StoreV2" NVPTXISD::StoreV4 "NVPTXISD::StoreV4"


<s> bool RISCVGatherScatterLowering :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; auto & TPC = getAnalysis < TargetPassConfig > ( ) ; auto & TM = TPC . getTM < RISCVTargetMachine > ( ) ; ST = & TM . getSubtarget < RISCVSubtarget > ( F ) ; if ( ! ST -> hasVInstructions ( ) || ! ST -> useRVVForFixedLengthVectors ( ) ) return false ; TLI = ST -> getTargetLowering ( ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SmallVector < IntrinsicInst * , 4 > Gathers ; SmallVector < IntrinsicInst * , 4 > Scatters ; bool Changed = false ; for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & I ) ; if ( II && II -> getIntrinsicID ( ) == Intrinsic :: masked_gather && isa < FixedVectorType > ( II -> getType ( ) ) ) { Gathers . push_back ( II ) ; } else if ( II && II -> getIntrinsicID ( ) == Intrinsic :: masked_scatter && isa < FixedVectorType > ( II -> getArgOperand ( 0 ) -> getType ( ) ) ) { Scatters . push_back ( II ) ; } } } for ( auto * II : Gathers ) Changed |= tryCreateStridedLoadStore ( II , II -> getType ( ) , II -> getArgOperand ( 0 ) , II -> getArgOperand ( 1 ) ) ; for ( auto * II : Scatters ) Changed |= tryCreateStridedLoadStore ( II , II -> getArgOperand ( 0 ) -> getType ( ) , II -> getArgOperand ( 1 ) , II -> getArgOperand ( 2 ) ) ; while ( ! MaybeDeadPHIs . empty ( ) ) { if ( auto * Phi = dyn_cast_or_null < PHINode > ( MaybeDeadPHIs . pop_back_val ( ) ) ) RecursivelyDeleteDeadPHINode ( Phi ) ; } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s>
bool
AArch64FrameLowering
::
spillCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
;
SmallVector
<
RegPairInfo
,
8
>
RegPairs
;
computeCalleeSaveRegisterPairs
(
MF
,
CSI
,
TRI
,
RegPairs
)
;
const
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
for
(
auto
RPII
=
RegPairs
.
rbegin
(
)
,
RPIE
=
RegPairs
.
rend
(
)
;
RPII
!=
RPIE
;
++
RPII
)
{
RegPairInfo
RPI
=
*
RPII
;
unsigned
Reg1
=
RPI
.
Reg1
;
unsigned
Reg2
=
RPI
.
Reg2
;
unsigned
StrOpc
;
if
(
RPI
.
IsGPR
)
StrOpc
=
RPI
.
isPaired
(
)
AArch64
::
STPXi
:
AArch64
::
STRXui
;
else
StrOpc
=
RPI
.
isPaired
(
)
AArch64
::
STPDi
:
AArch64
::
STRDui
;
DEBUG
(
dbgs
(
)
<<
"CSR spill: ("
<<
printReg
(
Reg1
,
TRI
)
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
printReg
(
Reg2
,
TRI
)
;
dbgs
(
)
<<
") -> fi#("
<<
RPI
.
FrameIdx
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
RPI
.
FrameIdx
+
1
;
dbgs
(
)
<<
")\n"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
StrOpc
)
)
;
if
(
!
MRI
.
isReserved
(
Reg1
)
)
MBB
.
addLiveIn
(
Reg1
)
;
if
(
RPI
.
isPaired
(
)
)
{
if
(
!
MRI
.
isReserved
(
Reg2
)
)
MBB
.
addLiveIn
(
Reg2
)
;
MIB
.
addReg
(
Reg2
,
getPrologueDeath
(
MF
,
Reg2
)
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
+
1
)
,
MachineMemOperand
::
MOStore
,
8
,
8
)
)
;
}
MIB
.
addReg
(
Reg1
,
getPrologueDeath
(
MF
,
Reg1
)
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
RPI
.
Offset
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
)
,
MachineMemOperand
::
MOStore
,
8
,
8
)
)
;
}
return
true
;
}
</s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> int ARMTTIImpl :: getIntImmCodeSizeCost ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) { if ( Imm . isNonNegative ( ) && Imm . getLimitedValue ( ) < 256 ) return 0 ; return 1 ; } </s>

Return the expected cost for the given integer when optimising for size .


"\nrs6000_secondary_reload_gpr, type = %s\n"

Convert reloads involving 64-bit gprs and misaligned offset addressing , or multiple 32-bit gprs and offsets that are too large , to use indirect addressing .


<s> unsigned getCacheLineSize ( ) const { return CacheLineSize ; } </s>

Return the target cache line size in bytes .


<s>
void
WebAssemblyInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
auto
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
const
TargetRegisterClass
*
RC
=
TargetRegisterInfo
::
isVirtualRegister
(
DestReg
)
MRI
.
getRegClass
(
DestReg
)
:
MRI
.
getTargetRegisterInfo
(
)
->
getMinimalPhysRegClass
(
DestReg
)
;
unsigned
CopyOpcode
;
if
(
RC
==
&
WebAssembly
::
I32RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_I32
;
else
if
(
RC
==
&
WebAssembly
::
I64RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_I64
;
else
if
(
RC
==
&
WebAssembly
::
F32RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_F32
;
else
if
(
RC
==
&
WebAssembly
::
F64RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_F64
;
else
if
(
RC
==
&
WebAssembly
::
V128RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_V128
;
else
if
(
RC
==
&
WebAssembly
::
EXNREFRegClass
)
CopyOpcode
=
WebAssembly
::
COPY_EXNREF
;
else
llvm_unreachable
(
"Unexpected register class"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
CopyOpcode
)
,
DestReg
)
.
addReg
(
SrcReg
,
KillSrc
RegState
::
Kill
:
0
)
;
}
</s>


<s>
bool
RISCVAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
if
(
!
mnemonicIsValid
(
Name
,
0
)
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
NameLoc
,
"unknown instruction"
)
;
}
Operands
.
push_back
(
RISCVOperand
::
createToken
(
Name
,
NameLoc
)
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
parseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
)
return
true
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LParen
)
&&
parseParenSuffix
(
Name
,
Operands
)
)
return
true
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

RISCV
RISCV
0
"unknown instruction"
RISCV
"unexpected token in argument list"
"unexpected token in argument list"
"unexpected token in argument list"


<s> static void aarch64_add_cfa_expression ( rtx_insn * insn , rtx reg , rtx base , poly_int64 offset ) { rtx mem = gen_frame_mem ( GET_MODE ( reg ) , plus_constant ( Pmode , base , offset ) ) ; add_reg_note ( insn , REG_CFA_EXPRESSION , gen_rtx_SET ( mem , reg ) ) ; } </s>

Add a REG_CFA_EXPRESSION note to INSN to say that register REG is saved at BASE + OFFSET .


Determine whether c6x_output_mi_thunk can succeed .


<s> void assignValueToReg ( unsigned ValVReg , unsigned PhysReg , CCValAssign & VA ) override { MIB . addUse ( PhysReg ) ; MIRBuilder . buildCopy ( PhysReg , ValVReg ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> int MipsAsmParser :: tryParseRegister ( StringRef Mnemonic ) { const AsmToken & Tok = Parser . getTok ( ) ; int RegNum = - 1 ; if ( Tok . is ( AsmToken :: Identifier ) ) { std :: string lowerCase = Tok . getString ( ) . lower ( ) ; RegNum = matchRegisterName ( lowerCase ) ; } else if ( Tok . is ( AsmToken :: Integer ) ) RegNum = matchRegisterByNumber ( static_cast < unsigned > ( Tok . getIntVal ( ) ) , Mnemonic . lower ( ) ) ; else return RegNum ; if ( isMips64 ( ) && RegNum == Mips :: ZERO_64 ) { if ( Mnemonic . find ( "ddiv" ) != StringRef :: npos ) RegNum = Mips :: ZERO ; } return RegNum ; } </s>

tryParseRegister - parse one register if possible

Mips Mips 1 Mips Mips::ZERO_64 "ddiv" Mips::ZERO


<s> bool AMDGPUInstructionSelector :: select ( MachineInstr & I , CodeGenCoverage & CoverageInfo ) const { if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) { if ( I . isCopy ( ) ) return selectCOPY ( I ) ; return true ; } switch ( I . getOpcode ( ) ) { default : return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_ADD : return selectG_ADD ( I ) ; case TargetOpcode :: G_INTTOPTR : case TargetOpcode :: G_BITCAST : return selectCOPY ( I ) ; case TargetOpcode :: G_CONSTANT : case TargetOpcode :: G_FCONSTANT : return selectG_CONSTANT ( I ) ; case TargetOpcode :: G_EXTRACT : return selectG_EXTRACT ( I ) ; case TargetOpcode :: G_GEP : return selectG_GEP ( I ) ; case TargetOpcode :: G_IMPLICIT_DEF : return selectG_IMPLICIT_DEF ( I ) ; case TargetOpcode :: G_INSERT : return selectG_INSERT ( I ) ; case TargetOpcode :: G_INTRINSIC : return selectG_INTRINSIC ( I , CoverageInfo ) ; case TargetOpcode :: G_INTRINSIC_W_SIDE_EFFECTS : return selectG_INTRINSIC_W_SIDE_EFFECTS ( I , CoverageInfo ) ; case TargetOpcode :: G_LOAD : if ( selectImpl ( I , CoverageInfo ) ) return true ; return selectG_LOAD ( I ) ; case TargetOpcode :: G_STORE : return selectG_STORE ( I ) ; } return false ; } </s>

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s> bool Thumb1RegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { DebugLoc DL ; BuildMI ( MBB , I , DL , TII . get ( ARM :: tMOVtgpr2gpr ) ) . addReg ( ARM :: R12 , RegState :: Define ) . addReg ( Reg , RegState :: Kill ) ; bool done = false ; for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { if ( II -> isDebugValue ( ) ) continue ; for ( unsigned i = 0 , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == ARM :: R12 ) { UseMI = II ; done = true ; break ; } } } BuildMI ( MBB , UseMI , DL , TII . get ( ARM :: tMOVgpr2tgpr ) ) . addReg ( Reg , RegState :: Define ) . addReg ( ARM :: R12 , RegState :: Kill ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const PPCFrameLowering * PPCFI = static_cast < const PPCFrameLowering * > ( MF . getTarget ( ) . getFrameLowering ( ) ) ; Reserved . set ( PPC :: ZERO ) ; Reserved . set ( PPC :: ZERO8 ) ; Reserved . set ( PPC :: FP ) ; Reserved . set ( PPC :: FP8 ) ; Reserved . set ( PPC :: CTR ) ; Reserved . set ( PPC :: CTR8 ) ; Reserved . set ( PPC :: R1 ) ; Reserved . set ( PPC :: LR ) ; Reserved . set ( PPC :: LR8 ) ; Reserved . set ( PPC :: RM ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) Reserved . set ( PPC :: VRSAVE ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: R2 ) ; Reserved . set ( PPC :: R13 ) ; } if ( Subtarget . isPPC64 ( ) ) { Reserved . set ( PPC :: R13 ) ; Reserved . set ( PPC :: X1 ) ; Reserved . set ( PPC :: X13 ) ; if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: X31 ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: X2 ) ; } } if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: R31 ) ; if ( ! Subtarget . hasAltivec ( ) ) for ( TargetRegisterClass :: iterator I = PPC :: VRRCRegClass . begin ( ) , IE = PPC :: VRRCRegClass . end ( ) ; I != IE ; ++ I ) Reserved . set ( * I ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


"dynamic alloca in the static alloca map?"

Emit an alloca address in a register using target-specific logic .


<s> unsigned size ( ) const { return List . size ( ) ; } </s>

The number of name/type pairs is returned .


<s> bool ARMTTIImpl :: isLegalMaskedLoad ( Type * DataTy , MaybeAlign Alignment ) { if ( ! EnableMaskedLoadStores || ! ST -> hasMVEIntegerOps ( ) ) return false ; if ( auto * VecTy = dyn_cast < FixedVectorType > ( DataTy ) ) { if ( VecTy -> getNumElements ( ) == 2 ) return false ; unsigned VecWidth = DataTy -> getPrimitiveSizeInBits ( ) ; if ( VecWidth != 128 && VecTy -> getElementType ( ) -> isFloatingPointTy ( ) ) return false ; } unsigned EltWidth = DataTy -> getScalarSizeInBits ( ) ; return ( EltWidth == 32 && ( ! Alignment || * Alignment >= 4 ) ) || ( EltWidth == 16 && ( ! Alignment || * Alignment >= 2 ) ) || ( EltWidth == 8 ) ; } </s>

Return true if the target supports masked load .


<s>
static
void
avr_asm_final_postscan_insn
(
FILE
*
stream
,
rtx_insn
*
insn
,
rtx
*
,
int
)
{
if
(
cfun
->
machine
->
gasisr
.
yes
&&
!
next_real_insn
(
insn
)
)
{
app_disable
(
)
;
fprintf
(
stream
,
"\t__gcc_isr %d,r%d\n"
,
GASISR_Done
,
cfun
->
machine
->
gasisr
.
regno
)
;
}
}
</s>

When GAS generates ( parts of ) ISR prologue / epilogue for us , we must hint GAS about the end of the code to scan . There migh be code located after the last epilogue .


<s> bool AArch64PromoteConstant :: runOnFunction ( Function & F , PromotionCacheTy & PromotionCache ) { SmallVector < UpdateRecord , 64 > Updates ; for ( Instruction & I : instructions ( & F ) ) { for ( Use & U : I . operands ( ) ) { Constant * Cst = dyn_cast < Constant > ( U ) ; if ( ! Cst || isa < GlobalValue > ( Cst ) || isa < ConstantExpr > ( Cst ) ) continue ; if ( ! shouldConvert ( * Cst , PromotionCache ) ) continue ; unsigned OpNo = & U - I . op_begin ( ) ; if ( ! shouldConvertUse ( Cst , & I , OpNo ) ) continue ; Updates . emplace_back ( Cst , & I , OpNo ) ; } } if ( Updates . empty ( ) ) return false ; promoteConstants ( F , Updates , PromotionCache ) ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> const uint32_t * M680x0RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { return CSR_STD_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void AMDGPUUnifyDivergentExitNodes :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < PostDominatorTreeWrapperPass > ( ) ; AU . addRequired < DivergenceAnalysis > ( ) ; AU . addPreserved < DivergenceAnalysis > ( ) ; AU . addPreservedID ( BreakCriticalEdgesID ) ; AU . addPreservedID ( LowerSwitchID ) ; FunctionPass :: getAnalysisUsage ( AU ) ; AU . addRequired < TargetTransformInfoWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
void
PTXInstPrinter
::
printRegName
(
raw_ostream
&
OS
,
unsigned
RegNo
)
const
{
unsigned
RegSpace
=
RegNo
&
0x7
;
unsigned
RegType
=
(
RegNo
>>
3
)
&
0x7
;
unsigned
RegOffset
=
RegNo
>>
6
;
OS
<<
"%"
;
switch
(
RegSpace
)
{
default
:
llvm_unreachable
(
"Unknown register space!"
)
;
case
PTXRegisterSpace
::
Reg
:
switch
(
RegType
)
{
default
:
llvm_unreachable
(
"Unknown register type!"
)
;
case
PTXRegisterType
::
Pred
:
OS
<<
"p"
;
break
;
case
PTXRegisterType
::
B16
:
OS
<<
"rh"
;
break
;
case
PTXRegisterType
::
B32
:
OS
<<
"r"
;
break
;
case
PTXRegisterType
::
B64
:
OS
<<
"rd"
;
break
;
case
PTXRegisterType
::
F32
:
OS
<<
"f"
;
break
;
case
PTXRegisterType
::
F64
:
OS
<<
"fd"
;
break
;
}
break
;
case
PTXRegisterSpace
::
Return
:
OS
<<
"ret"
;
break
;
case
PTXRegisterSpace
::
Argument
:
OS
<<
"arg"
;
break
;
}
OS
<<
RegOffset
;
}
</s>


"immediate is too large for this instruction"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s>
unsigned
WebAssemblyInstrInfo
::
insertBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
TBB
,
MachineBasicBlock
*
FBB
,
ArrayRef
<
MachineOperand
>
Cond
,
const
DebugLoc
&
DL
,
int
*
BytesAdded
)
const
{
assert
(
!
BytesAdded
&&
"code size not handled"
)
;
if
(
Cond
.
empty
(
)
)
{
if
(
!
TBB
)
return
0
;
BuildMI
(
&
MBB
,
DL
,
get
(
WebAssembly
::
BR
)
)
.
addMBB
(
TBB
)
;
return
1
;
}
assert
(
Cond
.
size
(
)
==
2
&&
"Expected a flag and a successor block"
)
;
if
(
Cond
[
0
]
.
getImm
(
)
)
BuildMI
(
&
MBB
,
DL
,
get
(
WebAssembly
::
BR_IF
)
)
.
addMBB
(
TBB
)
.
add
(
Cond
[
1
]
)
;
else
BuildMI
(
&
MBB
,
DL
,
get
(
WebAssembly
::
BR_UNLESS
)
)
.
addMBB
(
TBB
)
.
add
(
Cond
[
1
]
)
;
if
(
!
FBB
)
return
1
;
BuildMI
(
&
MBB
,
DL
,
get
(
WebAssembly
::
BR
)
)
.
addMBB
(
FBB
)
;
return
2
;
}
</s>

Insert branch code into the end of the specified MachineBasicBlock .


<s> static rtx_insn * emit_sp_adjust ( int offset , int * next_scratch_regno , bool frame_related , rtx reg_notes ) { rtx to_add ; rtx imm_rtx = GEN_INT ( offset ) ; rtx pat ; rtx_insn * insn ; if ( satisfies_constraint_J ( imm_rtx ) ) { to_add = imm_rtx ; } else { rtx tmp = gen_rtx_REG ( Pmode , ( * next_scratch_regno ) -- ) ; tilegx_expand_set_const64 ( tmp , imm_rtx ) ; to_add = tmp ; } if ( TARGET_32BIT ) pat = gen_sp_adjust_32bit ( stack_pointer_rtx , stack_pointer_rtx , to_add ) ; else pat = gen_sp_adjust ( stack_pointer_rtx , stack_pointer_rtx , to_add ) ; insn = emit_insn ( pat ) ; REG_NOTES ( insn ) = reg_notes ; if ( frame_related ) { rtx real = gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , imm_rtx ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , real ) ; } return insn ; } </s>

This emits code for 'sp += offset ' . The ABI only allows us to modify 'sp ' in a single 'addi ' or 'addli ' , so the backtracer understands it . Larger amounts can not use those instructions , so are added by placing the offset into a large register and using 'add ' . This happens after reload , so we need to expand it ourselves .


"Unknown fence ordering in emitLeadingFence"


<s> void RISCVAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { RISCVMCInstLower Lower ( MF -> getContext ( ) , * this ) ; MCInst LoweredMI ; Lower . lower ( MI , LoweredMI ) ; EmitToStreamer ( * OutStreamer , LoweredMI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
MCSection
*
XCoreTargetObjectFile
::
getSectionForConstant
(
const
DataLayout
&
DL
,
SectionKind
Kind
,
const
Constant
*
C
)
const
{
if
(
Kind
.
isMergeableConst4
(
)
)
return
MergeableConst4Section
;
if
(
Kind
.
isMergeableConst8
(
)
)
return
MergeableConst8Section
;
if
(
Kind
.
isMergeableConst16
(
)
)
return
MergeableConst16Section
;
assert
(
(
Kind
.
isReadOnly
(
)
||
Kind
.
isReadOnlyWithRel
(
)
)
&&
"Unknown section kind"
)
;
return
ReadOnlySection
;
}
</s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> rtx mmix_eh_return_stackadj_rtx ( ) { return gen_rtx_REG ( Pmode , MMIX_EH_RETURN_STACKADJ_REGNUM ) ; } </s>


<s> static void aarch64_emit_inverted_unspec_cond ( rtx target , rtx_code code , machine_mode pred_mode , rtx ptrue , rtx pred , rtx op0 , rtx op1 , bool can_invert_p ) { if ( can_invert_p ) aarch64_emit_unspec_cond ( target , code , pred_mode , pred , op0 , op1 ) ; else { rtx tmp = gen_reg_rtx ( pred_mode ) ; aarch64_emit_unspec_cond ( tmp , code , pred_mode , pred , op0 , op1 ) ; emit_set_insn ( target , gen_rtx_AND ( pred_mode , gen_rtx_NOT ( pred_mode , tmp ) , ptrue ) ) ; } } </s>

If CAN_INVERT_P , emit an instruction : ( set TARGET ( unspec : PRED_MODE [ PRED OP0 OP1 ] UNSPEC_COND_ < X > ) ) where < X > is the operation associated with comparison CODE . Otherwise emit : ( set TMP ( unspec : PRED_MODE [ PRED OP0 OP1 ] UNSPEC_COND_ < X > ) ) ( set TARGET ( and : PRED_MODE ( not : PRED_MODE TMP ) PTRUE ) ) where the second instructions sets TARGET to the inverse of TMP .


<s> unsigned X86TargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const SelectionDAG & , unsigned Depth ) const { if ( Op . getOpcode ( ) == X86ISD :: SETCC_CARRY ) return Op . getValueType ( ) . getScalarSizeInBits ( ) ; return 1 ; } </s>

Determine the number of bits in the operation that are sign bits .


<s> WebAssemblySubtarget :: WebAssemblySubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : WebAssemblyGenSubtargetInfo ( TT , CPU , FS ) , HasSIMD128 ( false ) , HasAtomics ( false ) , HasNontrappingFPToInt ( false ) , HasSignExt ( false ) , CPUString ( CPU ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS ) ) , TSInfo ( ) , TLInfo ( TM , * this ) { } </s>

This constructor initializes the data members to match that of the specified triple .

WebAssembly WebAssembly WebAssembly WebAssembly


<s> static bool mips_keep_interrupts_masked_p ( tree type ) { return lookup_attribute ( "keep_interrupts_masked" , TYPE_ATTRIBUTES ( type ) ) != NULL ; } </s>

Check if the attribute to keep interrupts masked is set for a function .


<s> std :: unique_ptr < CSEConfigBase > AMDGPUPassConfig :: getCSEConfig ( ) const { return getStandardCSEConfigForOpt ( TM -> getOptLevel ( ) ) ; } </s>

Returns the CSEConfig object to use for the current optimization level .


Return the opcode of the special instruction to be used to load the constant X .


<s> int m32c_special_page_vector_p ( tree func ) { tree list ; if ( TREE_CODE ( func ) != FUNCTION_DECL ) return 0 ; list = M32C_ATTRIBUTES ( func ) ; while ( list ) { if ( is_attribute_p ( "function_vector" , TREE_PURPOSE ( list ) ) ) return 1 ; list = TREE_CHAIN ( list ) ; } return 0 ; } </s>

Returns TRUE if given tree has the `` function_vector '' attribute .


<s> static rtx ix86_expand_vec_set_builtin ( tree exp ) { machine_mode tmode , mode1 ; tree arg0 , arg1 , arg2 ; int elt ; rtx op0 , op1 , target ; arg0 = CALL_EXPR_ARG ( exp , 0 ) ; arg1 = CALL_EXPR_ARG ( exp , 1 ) ; arg2 = CALL_EXPR_ARG ( exp , 2 ) ; tmode = TYPE_MODE ( TREE_TYPE ( arg0 ) ) ; mode1 = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( arg0 ) ) ) ; gcc_assert ( VECTOR_MODE_P ( tmode ) ) ; op0 = expand_expr ( arg0 , NULL_RTX , tmode , EXPAND_NORMAL ) ; op1 = expand_expr ( arg1 , NULL_RTX , mode1 , EXPAND_NORMAL ) ; elt = get_element_number ( TREE_TYPE ( arg0 ) , arg2 ) ; if ( GET_MODE ( op1 ) != mode1 && GET_MODE ( op1 ) != VOIDmode ) op1 = convert_modes ( mode1 , GET_MODE ( op1 ) , op1 , true ) ; op0 = force_reg ( tmode , op0 ) ; op1 = force_reg ( mode1 , op1 ) ; target = gen_reg_rtx ( tmode ) ; emit_move_insn ( target , op0 ) ; ix86_expand_vector_set ( true , target , op1 , elt ) ; return target ; } </s>

A subroutine of ix86_expand_builtin . These builtins are a wrapper around ix86_expand_vector_set . They would be redundant ( for non-MMX ) if we had a language-level syntax for referencing vector elements .


<s> unsigned AArch64FrameLowering :: getWinEHFuncletFrameSize ( const MachineFunction & MF ) const { unsigned CSSize = MF . getInfo < AArch64FunctionInfo > ( ) -> getCalleeSavedStackSize ( ) ; return alignTo ( CSSize + MF . getFrameInfo ( ) . getMaxCallFrameSize ( ) , getStackAlign ( ) ) ; } </s>

Funclets only need to account for space for the callee saved registers , as the locals are accounted for in the parent 's stack frame .


"PPC branch conditions have two components!"

"Cannot insert select on target without ISEL support"

"TrueReg and FalseReg must have overlapping register classes"

Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true , and FalseReg to DstReg when Cond is false .


<s>
int
m32c_preferred_reload_class
(
rtx
x
,
int
rclass
)
{
int
newclass
=
rclass
;
fprintf
(
stderr
,
"\npreferred_reload_class for %s is "
,
class_names
[
rclass
]
)
;
if
(
rclass
==
NO_REGS
)
rclass
=
GET_MODE
(
x
)
==
QImode
HL_REGS
:
R03_REGS
;
if
(
classes_intersect
(
rclass
,
CR_REGS
)
)
{
switch
(
GET_MODE
(
x
)
)
{
case
QImode
:
newclass
=
HL_REGS
;
break
;
default
:
break
;
}
}
else
if
(
newclass
==
QI_REGS
&&
GET_MODE_SIZE
(
GET_MODE
(
x
)
)
>
2
)
newclass
=
SI_REGS
;
else
if
(
GET_MODE_SIZE
(
GET_MODE
(
x
)
)
>
4
&&
~
class_contents
[
rclass
]
[
0
]
&
0x000f
)
newclass
=
DI_REGS
;
rclass
=
reduce_class
(
rclass
,
newclass
,
rclass
)
;
if
(
GET_MODE
(
x
)
==
QImode
)
rclass
=
reduce_class
(
rclass
,
HL_REGS
,
rclass
)
;
fprintf
(
stderr
,
"%s\n"
,
class_names
[
rclass
]
)
;
debug_rtx
(
x
)
;
if
(
GET_CODE
(
x
)
==
MEM
&&
GET_CODE
(
XEXP
(
x
,
0
)
)
==
PLUS
&&
GET_CODE
(
XEXP
(
XEXP
(
x
,
0
)
,
0
)
)
==
PLUS
)
fprintf
(
stderr
,
"Glorm!\n"
)
;
return
rclass
;
}
</s>

Implements PREFERRED_RELOAD_CLASS . In general , prefer general registers of the appropriate size .


<s> void ARMPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableARMLoadStoreOpt ) addPass ( createARMLoadStoreOptimizationPass ( ) ) ; addPass ( createExecutionDependencyFixPass ( & ARM :: DPRRegClass ) ) ; } addPass ( createARMExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createThumb2SizeReductionPass ( [ this ] ( const Function & F ) { return this -> TM -> getSubtarget < ARMSubtarget > ( F ) . restrictIT ( ) ; } ) ) ; addPass ( createIfConverter ( [ ] ( const MachineFunction & MF ) { return ! MF . getSubtarget < ARMSubtarget > ( ) . isThumb1Only ( ) ; } ) ) ; } addPass ( createThumb2ITBlockPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .

ARM ARM ARM ARM ARM::DPRRegClass ARM ARM ARM


<s>
SDValue
SystemZTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
BR_CC
:
return
lowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
lowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
lowerGlobalAddress
(
cast
<
GlobalAddressSDNode
>
(
Op
)
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
lowerGlobalTLSAddress
(
cast
<
GlobalAddressSDNode
>
(
Op
)
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
lowerBlockAddress
(
cast
<
BlockAddressSDNode
>
(
Op
)
,
DAG
)
;
case
ISD
::
JumpTable
:
return
lowerJumpTable
(
cast
<
JumpTableSDNode
>
(
Op
)
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
lowerConstantPool
(
cast
<
ConstantPoolSDNode
>
(
Op
)
,
DAG
)
;
case
ISD
::
BITCAST
:
return
lowerBITCAST
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
lowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
VACOPY
:
return
lowerVACOPY
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
lowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
UMUL_LOHI
:
return
lowerUMUL_LOHI
(
Op
,
DAG
)
;
case
ISD
::
SDIVREM
:
return
lowerSDIVREM
(
Op
,
DAG
)
;
case
ISD
::
UDIVREM
:
return
lowerUDIVREM
(
Op
,
DAG
)
;
case
ISD
::
OR
:
return
lowerOR
(
Op
,
DAG
)
;
case
ISD
::
ATOMIC_SWAP
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_SWAPW
)
;
case
ISD
::
ATOMIC_LOAD_ADD
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_LOADW_ADD
)
;
case
ISD
::
ATOMIC_LOAD_SUB
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_LOADW_SUB
)
;
case
ISD
::
ATOMIC_LOAD_AND
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_LOADW_AND
)
;
case
ISD
::
ATOMIC_LOAD_OR
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_LOADW_OR
)
;
case
ISD
::
ATOMIC_LOAD_XOR
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_LOADW_XOR
)
;
case
ISD
::
ATOMIC_LOAD_NAND
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_LOADW_NAND
)
;
case
ISD
::
ATOMIC_LOAD_MIN
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_LOADW_MIN
)
;
case
ISD
::
ATOMIC_LOAD_MAX
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_LOADW_MAX
)
;
case
ISD
::
ATOMIC_LOAD_UMIN
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_LOADW_UMIN
)
;
case
ISD
::
ATOMIC_LOAD_UMAX
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_LOADW_UMAX
)
;
case
ISD
::
ATOMIC_CMP_SWAP
:
return
lowerATOMIC_CMP_SWAP
(
Op
,
DAG
)
;
case
ISD
::
STACKSAVE
:
return
lowerSTACKSAVE
(
Op
,
DAG
)
;
case
ISD
::
STACKRESTORE
:
return
lowerSTACKRESTORE
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"Unexpected node to lower"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> virtual const MipsInstrInfo * getInstrInfo ( ) const { return InstrInfo . get ( ) ; } </s>


<s> static void m68k_adjust_decorated_operand ( rtx op ) { subrtx_var_iterator :: array_type array ; FOR_EACH_SUBRTX_VAR ( iter , array , op , ALL ) { rtx x = * iter ; if ( m68k_unwrap_symbol ( x , true ) != x ) { rtx plus ; gcc_assert ( GET_CODE ( x ) == CONST ) ; plus = XEXP ( x , 0 ) ; if ( GET_CODE ( plus ) == PLUS || GET_CODE ( plus ) == MINUS ) { rtx unspec ; rtx addend ; unspec = XEXP ( plus , 0 ) ; gcc_assert ( GET_CODE ( unspec ) == UNSPEC ) ; addend = XEXP ( plus , 1 ) ; gcc_assert ( CONST_INT_P ( addend ) ) ; XEXP ( plus , 0 ) = XVECEXP ( unspec , 0 , 0 ) ; XVECEXP ( unspec , 0 , 0 ) = plus ; XEXP ( x , 0 ) = unspec ; } iter . skip_subrtxes ( ) ; } } } </s>

Adjust decorated address operand before outputing assembler for it .


<s> void AMDGPUPassConfig :: addCodeGenPrepare ( ) { const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; addPass ( createAMDGPUPromoteAlloca ( ST ) ) ; addPass ( createSROAPass ( ) ) ; TargetPassConfig :: addCodeGenPrepare ( ) ; } </s>

Add pass to prepare the LLVM IR for code generation .


<s> static rtx frv_expand_mdpackh_builtin ( tree call , rtx target ) { enum insn_code icode = CODE_FOR_mdpackh ; rtx pat , op0 , op1 ; rtx arg1 = frv_read_argument ( call , 0 ) ; rtx arg2 = frv_read_argument ( call , 1 ) ; rtx arg3 = frv_read_argument ( call , 2 ) ; rtx arg4 = frv_read_argument ( call , 3 ) ; target = frv_legitimize_target ( icode , target ) ; op0 = gen_reg_rtx ( DImode ) ; op1 = gen_reg_rtx ( DImode ) ; emit_clobber ( op0 ) ; emit_clobber ( op1 ) ; emit_move_insn ( simplify_gen_subreg ( HImode , op0 , DImode , 2 ) , arg1 ) ; emit_move_insn ( simplify_gen_subreg ( HImode , op0 , DImode , 6 ) , arg2 ) ; emit_move_insn ( simplify_gen_subreg ( HImode , op1 , DImode , 2 ) , arg3 ) ; emit_move_insn ( simplify_gen_subreg ( HImode , op1 , DImode , 6 ) , arg4 ) ; pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return target ; } </s>

Expand the MDPACKH builtin . It takes four unsigned short arguments and each argument forms one word of the two double-word input registers . ARGLIST is a TREE_LIST of the arguments and TARGET , if nonnull , suggests a good place to put the return value .


<s> static const char * aarch64_mangle_type ( const_tree type ) { if ( lang_hooks . types_compatible_p ( CONST_CAST_TREE ( type ) , va_list_type ) ) return "St9__va_list" ; if ( TREE_CODE ( type ) == REAL_TYPE && TYPE_PRECISION ( type ) == 16 ) { if ( TYPE_MODE ( type ) == BFmode ) return "u6__bf16" ; else return "Dh" ; } if ( TYPE_NAME ( type ) != NULL ) { const char * res ; if ( ( res = aarch64_general_mangle_builtin_type ( type ) ) || ( res = aarch64_sve :: mangle_builtin_type ( type ) ) ) return res ; } return NULL ; } </s>


<s> bool HexagonHardwareLoops :: isDead ( const MachineInstr * MI , SmallVectorImpl < MachineInstr * > & DeadPhis ) const { for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( MRI -> use_nodbg_empty ( Reg ) ) continue ; using use_nodbg_iterator = MachineRegisterInfo :: use_nodbg_iterator ; use_nodbg_iterator I = MRI -> use_nodbg_begin ( Reg ) ; use_nodbg_iterator End = MRI -> use_nodbg_end ( ) ; if ( std :: next ( I ) != End || ! I -> getParent ( ) -> isPHI ( ) ) return false ; MachineInstr * OnePhi = I -> getParent ( ) ; for ( unsigned j = 0 , f = OnePhi -> getNumOperands ( ) ; j != f ; ++ j ) { const MachineOperand & OPO = OnePhi -> getOperand ( j ) ; if ( ! OPO . isReg ( ) || ! OPO . isDef ( ) ) continue ; Register OPReg = OPO . getReg ( ) ; use_nodbg_iterator nextJ ; for ( use_nodbg_iterator J = MRI -> use_nodbg_begin ( OPReg ) ; J != End ; J = nextJ ) { nextJ = std :: next ( J ) ; MachineOperand & Use = * J ; MachineInstr * UseMI = Use . getParent ( ) ; if ( MI != UseMI ) return false ; } } DeadPhis . push_back ( OnePhi ) ; } return true ; } </s>

isDead - Returns true if this is a dead def kill slot .


<s> bool legitimate_reload_constant_p ( rtx op ) { if ( GET_CODE ( op ) == CONST_INT && DISP_IN_RANGE ( INTVAL ( op ) ) ) return true ; if ( GET_CODE ( op ) == CONST_INT && ( CONST_OK_FOR_K ( INTVAL ( op ) ) || CONST_OK_FOR_Os ( INTVAL ( op ) ) ) ) return true ; if ( TARGET_ZARCH && GET_CODE ( op ) == CONST_INT && trunc_int_for_mode ( INTVAL ( op ) , word_mode ) == INTVAL ( op ) && s390_single_part ( op , word_mode , HImode , 0 ) >= 0 ) return true ; if ( TARGET_EXTIMM && GET_CODE ( op ) == CONST_INT && trunc_int_for_mode ( INTVAL ( op ) , word_mode ) == INTVAL ( op ) && s390_single_part ( op , word_mode , SImode , 0 ) >= 0 ) return true ; if ( TARGET_CPU_ZARCH && larl_operand ( op , VOIDmode ) ) return true ; if ( GET_CODE ( op ) == CONST_DOUBLE && s390_float_const_zero_p ( op ) && GET_MODE_SIZE ( GET_MODE ( op ) ) <= UNITS_PER_WORD ) return true ; if ( GET_CODE ( op ) == CONST_INT && trunc_int_for_mode ( INTVAL ( op ) , word_mode ) != INTVAL ( op ) ) { machine_mode dword_mode = word_mode == SImode ? DImode : TImode ; rtx hi = operand_subword ( op , 0 , 0 , dword_mode ) ; rtx lo = operand_subword ( op , 1 , 0 , dword_mode ) ; return legitimate_reload_constant_p ( hi ) && legitimate_reload_constant_p ( lo ) ; } return false ; } </s>

Returns true if the constant value OP is a legitimate general operand during and after reload . The difference to legitimate_constant_p is that this function will not accept a constant that would need to be forced to the literal pool before it can be used as operand .


<s> rtx or1k_return_addr ( int , rtx frame ) { return gen_frame_mem ( Pmode , plus_constant ( Pmode , frame , - UNITS_PER_WORD ) ) ; } </s>

Worker for RETURN_ADDR_RTX . Returns the RTX representing the address of where the link register may be stored on the stack .


<s>
MachineBasicBlock
::
iterator
AVRFrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
)
const
{
const
AVRSubtarget
&
STI
=
MF
.
getSubtarget
<
AVRSubtarget
>
(
)
;
const
AVRInstrInfo
&
TII
=
*
STI
.
getInstrInfo
(
)
;
if
(
hasReservedCallFrame
(
MF
)
)
{
fixStackStores
(
MBB
,
MI
,
TII
,
AVR
::
R29R28
)
;
return
MBB
.
erase
(
MI
)
;
}
DebugLoc
DL
=
MI
->
getDebugLoc
(
)
;
unsigned
int
Opcode
=
MI
->
getOpcode
(
)
;
int
Amount
=
TII
.
getFrameSize
(
*
MI
)
;
if
(
Amount
!=
0
)
{
assert
(
getStackAlign
(
)
==
Align
(
1
)
&&
"Unsupported stack alignment"
)
;
if
(
Opcode
==
TII
.
getCallFrameSetupOpcode
(
)
)
{
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
SPREAD
)
,
AVR
::
R31R30
)
.
addReg
(
AVR
::
SP
)
;
MachineInstr
*
New
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
SUBIWRdK
)
,
AVR
::
R31R30
)
.
addReg
(
AVR
::
R31R30
,
RegState
::
Kill
)
.
addImm
(
Amount
)
;
New
->
getOperand
(
3
)
.
setIsDead
(
)
;
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
SPWRITE
)
,
AVR
::
SP
)
.
addReg
(
AVR
::
R31R30
)
;
fixStackStores
(
MBB
,
MI
,
TII
,
AVR
::
R31R30
)
;
}
else
{
assert
(
Opcode
==
TII
.
getCallFrameDestroyOpcode
(
)
)
;
unsigned
addOpcode
;
if
(
isUInt
<
6
>
(
Amount
)
)
{
addOpcode
=
AVR
::
ADIWRdK
;
}
else
{
addOpcode
=
AVR
::
SUBIWRdK
;
Amount
=
Amount
;
}
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
SPREAD
)
,
AVR
::
R31R30
)
.
addReg
(
AVR
::
SP
)
;
MachineInstr
*
New
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
addOpcode
)
,
AVR
::
R31R30
)
.
addReg
(
AVR
::
R31R30
,
RegState
::
Kill
)
.
addImm
(
Amount
)
;
New
->
getOperand
(
3
)
.
setIsDead
(
)
;
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
SPWRITE
)
,
AVR
::
SP
)
.
addReg
(
AVR
::
R31R30
,
RegState
::
Kill
)
;
}
}
return
MBB
.
erase
(
MI
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> unsigned ARMBaseInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case ARM :: LDRrs : case ARM :: t2LDRs : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isReg ( ) && MI . getOperand ( 3 ) . isImm ( ) && MI . getOperand ( 2 ) . getReg ( ) == 0 && MI . getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: LDRi12 : case ARM :: t2LDRi12 : case ARM :: tLDRspi : case ARM :: VLDRD : case ARM :: VLDRS : case ARM :: VLDR_P0_off : case ARM :: MVE_VLDRWU32 : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VLD1q64 : case ARM :: VLD1d8TPseudo : case ARM :: VLD1d16TPseudo : case ARM :: VLD1d32TPseudo : case ARM :: VLD1d64TPseudo : case ARM :: VLD1d8QPseudo : case ARM :: VLD1d16QPseudo : case ARM :: VLD1d32QPseudo : case ARM :: VLD1d64QPseudo : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VLDMQIA : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: MQQPRLoad : case ARM :: MQQQQPRLoad : if ( MI . getOperand ( 1 ) . isFI ( ) ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> virtual const VideocoreRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
TTI
::
PopcntSupportKind
getPopcntSupport
(
unsigned
TyWidth
)
{
assert
(
isPowerOf2_32
(
TyWidth
)
&&
"Ty width must be power of 2"
)
;
return
ST
->
hasBCNT
(
TyWidth
)
TTI
::
PSK_FastHardware
:
TTI
::
PSK_Software
;
}
</s>

Return hardware support for population count .


<s> static void mips_emit_move_or_split ( rtx dest , rtx src , enum mips_split_type split_type ) { if ( mips_split_move_p ( dest , src , split_type ) ) mips_split_move ( dest , src , split_type , NULL ) ; else mips_emit_move ( dest , src ) ; } </s>

Emit a move from SRC to DEST , splitting compound moves into individual instructions . SPLIT_TYPE is the type of split to perform .


<s> bool AMDGPUTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { EVT ScalarVT = VT . getScalarType ( ) ; return ( ScalarVT == MVT :: f32 || ScalarVT == MVT :: f64 ) ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


"%<-mfdpic%> is not supported, please use a bfin-linux-uclibc "

"%<-mshared-library-id=%> specified without "

"%<-fstack-limit-%> options are ignored with %<-mfdpic%>; "

"cannot use multiple stack checking methods together"

"ID shared libraries and FD-PIC mode cannot be used together"

"cannot specify both %<-msep-data%> and %<-mid-shared-library%>"

"%<-mmulticore%> can only be used with BF561"

"%<-mcorea%> should be used with %<-mmulticore%>"

"%<-mcoreb%> should be used with %<-mmulticore%>"

"%<-mcorea%> and %<-mcoreb%> cannot be used together"

Implement the TARGET_OPTION_OVERRIDE hook .


<s> static bool arc_needs_pcl_p ( rtx x ) { register const char * fmt ; register int i , j ; if ( ( GET_CODE ( x ) == UNSPEC ) && ( XVECLEN ( x , 0 ) == 1 ) && ( GET_CODE ( XVECEXP ( x , 0 , 0 ) ) == SYMBOL_REF ) ) switch ( XINT ( x , 1 ) ) { case ARC_UNSPEC_GOT : case ARC_UNSPEC_GOTOFFPC : case UNSPEC_TLS_GD : case UNSPEC_TLS_IE : return true ; default : break ; } fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'e' ) { if ( arc_needs_pcl_p ( XEXP ( x , i ) ) ) return true ; } else if ( fmt [ i ] == 'E' ) for ( j = XVECLEN ( x , i ) - 1 ; j >= 0 ; j -- ) if ( arc_needs_pcl_p ( XVECEXP ( x , i , j ) ) ) return true ; } return false ; } </s>

Helper used by arc_legitimate_pc_offset_p .


"Unexpected register class in CSRsViaCopy!"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> virtual const ARMFrameInfo * getFrameInfo ( ) const { return & FrameInfo ; } </s>

getFrameInfo - Return the frame info object for the current function .


<s> static void rs6000_split_logical_inner ( rtx dest , rtx op1 , rtx op2 , enum rtx_code code , machine_mode mode , bool complement_final_p , bool complement_op1_p , bool complement_op2_p ) { rtx bool_rtx ; if ( op2 && GET_CODE ( op2 ) == CONST_INT && ( mode == SImode || ( mode == DImode && TARGET_POWERPC64 ) ) && ! complement_final_p && ! complement_op1_p && ! complement_op2_p ) { HOST_WIDE_INT mask = GET_MODE_MASK ( mode ) ; HOST_WIDE_INT value = INTVAL ( op2 ) & mask ; if ( code == AND ) { if ( value == 0 ) { emit_insn ( gen_rtx_SET ( dest , const0_rtx ) ) ; return ; } else if ( value == mask ) { if ( ! rtx_equal_p ( dest , op1 ) ) emit_insn ( gen_rtx_SET ( dest , op1 ) ) ; return ; } } else if ( code == IOR || code == XOR ) { if ( value == 0 ) { if ( ! rtx_equal_p ( dest , op1 ) ) emit_insn ( gen_rtx_SET ( dest , op1 ) ) ; return ; } } } if ( code == AND && mode == SImode && ! complement_final_p && ! complement_op1_p && ! complement_op2_p ) { emit_insn ( gen_andsi3 ( dest , op1 , op2 ) ) ; return ; } if ( complement_op1_p ) op1 = gen_rtx_NOT ( mode , op1 ) ; if ( complement_op2_p ) op2 = gen_rtx_NOT ( mode , op2 ) ; if ( ! complement_op1_p && complement_op2_p ) std :: swap ( op1 , op2 ) ; bool_rtx = ( ( code == NOT ) ? gen_rtx_NOT ( mode , op1 ) : gen_rtx_fmt_ee ( code , mode , op1 , op2 ) ) ; if ( complement_final_p ) bool_rtx = gen_rtx_NOT ( mode , bool_rtx ) ; emit_insn ( gen_rtx_SET ( dest , bool_rtx ) ) ; } </s>

Helper function for rs6000_split_logical to emit a logical instruction after spliting the operation to single GPR registers . DEST is the destination register . OP1 and OP2 are the input source registers . CODE is the base operation ( AND , IOR , XOR , NOT ) . MODE is the machine mode . If COMPLEMENT_FINAL_P is true , wrap the whole operation with NOT . If COMPLEMENT_OP1_P is true , wrap operand1 with NOT . If COMPLEMENT_OP2_P is true , wrap operand2 with NOT .


<s> void function_builder :: add_overloaded_function ( const function_instance & instance , aarch64_feature_flags required_extensions ) { char * name = get_name ( instance , true ) ; if ( registered_function * * map_value = m_overload_names . get ( name ) ) { gcc_assert ( ( * map_value ) -> instance == instance && ( ( * map_value ) -> required_extensions & ~ required_extensions ) == 0 ) ; obstack_free ( & m_string_obstack , name ) ; } else { registered_function & rfn = add_function ( instance , name , m_overload_type , NULL_TREE , required_extensions , true , m_direct_overloads ) ; m_overload_names . put ( name , & rfn ) ; } } </s>

Add one function decl for INSTANCE , to be used with manual overload resolution . REQUIRED_EXTENSIONS are the set of architecture extensions that the function requires . For simplicity , deal with duplicate attempts to add the same function , including cases in which the new function requires more features than the original one did . In that case we 'll check whether the required features are available as part of resolving the function to the relevant unique function .


<s> bool AVRPassConfig :: addInstSelector ( ) { return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> rtx create_TOC_reference ( rtx symbol ) { if ( no_new_pseudos ) regs_ever_live [ TOC_REGISTER ] = 1 ; return gen_rtx_PLUS ( Pmode , gen_rtx_REG ( Pmode , TOC_REGISTER ) , gen_rtx_CONST ( Pmode , gen_rtx_MINUS ( Pmode , symbol , gen_rtx_SYMBOL_REF ( Pmode , toc_label_name ) ) ) ) ; } </s>

Create a TOC reference for symbol_ref SYMBOL . If LARGETOC_REG is non-null , use that as the register to put the HIGH value into if register allocation is already done .


<s> static HOST_WIDE_INT rounded_frame_size ( int pushed ) { HOST_WIDE_INT size = get_frame_size ( ) ; HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT ; return ( ( size + pushed + align - 1 ) & - align ) - pushed ; } </s>

PUSHED is the number of bytes that are bing pushed on the stack for register saves . Return the frame size , padded appropriately so that the stack stays properly aligned .


<s> static std :: string toString ( const APFloat & FP ) { if ( FP . isNaN ( ) && ! FP . bitwiseIsEqual ( APFloat :: getQNaN ( FP . getSemantics ( ) ) ) && ! FP . bitwiseIsEqual ( APFloat :: getQNaN ( FP . getSemantics ( ) , true ) ) ) { APInt AI = FP . bitcastToAPInt ( ) ; return std :: string ( AI . isNegative ( ) ? "-" : "" ) + "nan:0x" + utohexstr ( AI . getZExtValue ( ) & ( AI . getBitWidth ( ) == 32 ? INT64_C ( 0x007fffff ) : INT64_C ( 0x000fffffffffffff ) ) , true ) ; } static const size_t BufBytes = 128 ; char buf [ BufBytes ] ; auto Written = FP . convertToHexString ( buf , 0 , false , APFloat :: rmNearestTiesToEven ) ; ( void ) Written ; assert ( Written != 0 ) ; assert ( Written < BufBytes ) ; return buf ; } </s>

Convert to a decimal representation in a string .


<s> const char * fp_immediate_constant ( rtx x ) { REAL_VALUE_TYPE r ; int i ; if ( ! fp_consts_inited ) init_fp_table ( ) ; REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; for ( i = 0 ; i < 8 ; i ++ ) if ( REAL_VALUES_EQUAL ( r , values_fp [ i ] ) ) return strings_fp [ i ] ; gcc_unreachable ( ) ; } </s>

If the rtx is the correct value then return the string of the number . In this way we can ensure that valid double constants are generated even when cross compiling .


<s> void order_regs_for_local_alloc ( ) { static int last_order_nonleaf = 1 ; if ( regs_ever_live [ 15 ] != last_order_nonleaf ) { last_order_nonleaf = ! last_order_nonleaf ; memcpy ( ( char * ) reg_alloc_order , ( const char * ) reg_alloc_orders [ last_order_nonleaf ] , FIRST_PSEUDO_REGISTER * sizeof ( int ) ) ; } } </s>

Choose the order in which to allocate hard registers for pseudo-registers local to a basic block . Store the desired register order in the array ` reg_alloc_order ' . Element 0 should be the register to allocate first ; element 1 , the next register ; and so on .


<s> bool aarch64_sve_same_pred_for_ptest_p ( rtx * pred1 , rtx * pred2 ) { machine_mode mode = GET_MODE ( pred1 [ 0 ] ) ; gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL && mode == GET_MODE ( pred2 [ 0 ] ) && aarch64_sve_ptrue_flag ( pred1 [ 1 ] , SImode ) && aarch64_sve_ptrue_flag ( pred2 [ 1 ] , SImode ) ) ; bool ptrue1_p = ( pred1 [ 0 ] == CONSTM1_RTX ( mode ) || INTVAL ( pred1 [ 1 ] ) == SVE_KNOWN_PTRUE ) ; bool ptrue2_p = ( pred2 [ 0 ] == CONSTM1_RTX ( mode ) || INTVAL ( pred2 [ 1 ] ) == SVE_KNOWN_PTRUE ) ; return ( ptrue1_p && ptrue2_p ) || rtx_equal_p ( pred1 [ 0 ] , pred2 [ 0 ] ) ; } </s>

PRED1 [ 0 ] is a PTEST predicate and PRED1 [ 1 ] is an aarch64_sve_ptrue_flag for it . PRED2 [ 0 ] is the predicate for the instruction whose result is tested by the PTEST and PRED2 [ 1 ] is again an aarch64_sve_ptrue_flag for it . Return true if we can prove that the two predicates are equivalent for PTEST purposes ; that is , if we can replace PRED2 [ 0 ] with PRED1 [ 0 ] without changing behavior .


"Can only insert epilogue into returning blocks"

"Expected to see callee-save register restore code"


<s> rtx microblaze_return_addr ( int count , rtx frame ATTRIBUTE_UNUSED ) { if ( count != 0 ) return NULL_RTX ; return gen_rtx_PLUS ( Pmode , get_hard_reg_initial_val ( Pmode , MB_ABI_SUB_RETURN_ADDR_REGNUM ) , GEN_INT ( 8 ) ) ; } </s>

Return an RTX indicating where the return address to the calling function can be found .


<s> bool xstormy16_splittable_below100_operand ( rtx x , machine_mode mode ) { if ( MEM_P ( x ) && MEM_VOLATILE_P ( x ) ) return 0 ; return xstormy16_below100_operand ( x , mode ) ; } </s>

Likewise , but only for non-volatile MEMs , for patterns where the MEM will get split into smaller sized accesses .


<s> static machine_mode pa_promote_function_mode ( const_tree type ATTRIBUTE_UNUSED , machine_mode mode , int * punsignedp ATTRIBUTE_UNUSED , const_tree fntype ATTRIBUTE_UNUSED , int for_return ) { if ( for_return == 0 ) return mode ; return promote_mode ( type , mode , punsignedp ) ; } </s>

Promote the return value , but not the arguments .


"\nRelevant insns with their flag settings\n\n"


<s> bool ARMBaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( ! MF . getTarget ( ) . Options . RealignStack ) return false ; if ( AFI -> isThumb1OnlyFunction ( ) ) return false ; if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ; if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) ) return true ; if ( ! EnableBasePointer ) return false ; return MRI -> canReserveReg ( BasePtr ) ; } </s>

True if the stack can be realigned for the target .


<s> virtual unsigned int execute ( function * ) { timevar_push ( TV_MACH_DEP ) ; rest_of_insert_endbr_and_patchable_area ( need_endbr , patchable_area_size ) ; timevar_pop ( TV_MACH_DEP ) ; return 0 ; } </s>


<s> void PPCRegisterInfo :: lowerCRSpilling ( MachineBasicBlock :: iterator II , unsigned FrameIndex , int SPAdj , RegScavenger * RS ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; ( void ) SPAdj ; ( void ) RS ; bool LP64 = Subtarget . isPPC64 ( ) ; unsigned Reg = Subtarget . isDarwinABI ( ) ? ( LP64 ? PPC :: X2 : PPC :: R2 ) : ( LP64 ? PPC :: X0 : PPC :: R0 ) ; unsigned SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: MFCR8pseud : PPC :: MFCRpseud ) , Reg ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( 0 ) . isKill ( ) ) ) ; if ( SrcReg != PPC :: CR0 ) BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: RLWINM8 : PPC :: RLWINM ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( getPPCRegisterNumbering ( SrcReg ) * 4 ) . addImm ( 0 ) . addImm ( 31 ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: STW8 : PPC :: STW ) ) . addReg ( Reg , getKillRegState ( MI . getOperand ( 1 ) . getImm ( ) ) ) , FrameIndex ) ; MBB . erase ( II ) ; } </s>

lowerCRSpilling - Generate the code for spilling a CR register .


"Should use MaskedValueIsZero if you don't know whether Op"

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> bool AMDGPUPassConfig :: addInstSelector ( ) { addPass ( createAMDGPUPeepholeOpt ( * TM ) ) ; addPass ( createAMDGPUISelDag ( getAMDGPUTargetMachine ( ) ) ) ; return false ; } </s>


<s> HOST_WIDE_INT bfin_initial_elimination_offset ( int from , int to ) { HOST_WIDE_INT offset = 0 ; if ( from == ARG_POINTER_REGNUM ) offset = n_regs_saved_by_prologue ( ) * 4 ; if ( to == STACK_POINTER_REGNUM ) { if ( current_function_outgoing_args_size >= FIXED_STACK_AREA ) offset += current_function_outgoing_args_size ; else if ( current_function_outgoing_args_size ) offset += FIXED_STACK_AREA ; offset += get_frame_size ( ) ; } return offset ; } </s>

Return the offset between two registers , one to be eliminated , and the other its replacement , at the start of a routine .


<s> static const char * rs6000_xcoff_strip_name_encoding ( const char * name ) { size_t len ; if ( * name == '*' ) name ++ ; len = strlen ( name ) ; if ( name [ len - 1 ] == ']' ) return ggc_alloc_string ( name , len - 4 ) ; else return name ; } </s>

Remove any trailing [ DS ] or the like from the symbol name .


<s>
static
void
rs6000_debug_reg_print
(
int
first_regno
,
int
last_regno
,
const
char
*
reg_name
)
{
int
r
,
m
;
for
(
r
=
first_regno
;
r
<=
last_regno
;
++
r
)
{
const
char
*
comma
=
""
;
int
len
;
if
(
first_regno
==
last_regno
)
fprintf
(
stderr
,
"%s:\t"
,
reg_name
)
;
else
fprintf
(
stderr
,
"%s%d:\t"
,
reg_name
,
r
first_regno
)
;
len
=
8
;
for
(
m
=
0
;
m
<
NUM_MACHINE_MODES
;
++
m
)
if
(
rs6000_hard_regno_mode_ok_p
[
m
]
[
r
]
&&
rs6000_hard_regno_nregs
[
m
]
[
r
]
)
{
if
(
len
>
70
)
{
fprintf
(
stderr
,
",\n\t"
)
;
len
=
8
;
comma
=
""
;
}
if
(
rs6000_hard_regno_nregs
[
m
]
[
r
]
>
1
)
len
+=
fprintf
(
stderr
,
"%s%s/%d"
,
comma
,
GET_MODE_NAME
(
m
)
,
rs6000_hard_regno_nregs
[
m
]
[
r
]
)
;
else
len
+=
fprintf
(
stderr
,
"%s%s"
,
comma
,
GET_MODE_NAME
(
m
)
)
;
comma
=
", "
;
}
if
(
call_used_or_fixed_reg_p
(
r
)
)
{
if
(
len
>
70
)
{
fprintf
(
stderr
,
",\n\t"
)
;
len
=
8
;
comma
=
""
;
}
len
+=
fprintf
(
stderr
,
"%s%s"
,
comma
,
"call-used"
)
;
comma
=
", "
;
}
if
(
fixed_regs
[
r
]
)
{
if
(
len
>
70
)
{
fprintf
(
stderr
,
",\n\t"
)
;
len
=
8
;
comma
=
""
;
}
len
+=
fprintf
(
stderr
,
"%s%s"
,
comma
,
"fixed"
)
;
comma
=
", "
;
}
if
(
len
>
70
)
{
fprintf
(
stderr
,
",\n\t"
)
;
comma
=
""
;
}
len
+=
fprintf
(
stderr
,
"%sreg-class = %s"
,
comma
,
reg_class_names
[
(
int
)
rs6000_regno_regclass
[
r
]
]
)
;
comma
=
", "
;
if
(
len
>
70
)
{
fprintf
(
stderr
,
",\n\t"
)
;
comma
=
""
;
}
fprintf
(
stderr
,
"%sregno = %d\n"
,
comma
,
r
)
;
}
}
</s>

Print interesting facts about registers .


"loadRegFromStackSlot didn't insert any code!"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> void split_adds_subs ( machine_mode mode , rtx * operands ) { HOST_WIDE_INT val = INTVAL ( operands [ 1 ] ) ; rtx reg = operands [ 0 ] ; HOST_WIDE_INT sign = 1 ; HOST_WIDE_INT amount ; rtx ( * gen_add ) ( rtx , rtx , rtx ) ; if ( val < 0 ) { val = - val ; sign = - 1 ; } switch ( mode ) { case HImode : gen_add = gen_addhi3 ; break ; case SImode : gen_add = gen_addsi3 ; break ; default : gcc_unreachable ( ) ; } for ( amount = ( TARGET_H8300H || TARGET_H8300S ) ? 4 : 2 ; amount > 0 ; amount /= 2 ) { for ( ; val >= amount ; val -= amount ) emit_insn ( gen_add ( reg , reg , GEN_INT ( sign * amount ) ) ) ; } return ; } </s>

Split an add of a small constant into two adds/subs insns .


"This eliminateCallFramePseudoInstr does not suppor Thumb1!"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s>
StringRef
R600ClauseMergePass
::
getPassName
(
)
const
{
return
"R600 Merge Clause Markers Pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .

AMDGPU
R600
"R600 Merge Clause Markers Pass"


<s> void OR1KInstPrinter :: printRegName ( raw_ostream & O , unsigned RegNo ) const { O << getRegisterName ( RegNo ) ; } </s>


<s> const uint32_t * PPCRegisterInfo :: getNoPreservedMask ( ) const { if ( ! Subtarget . hasAltivec ( ) ) return CSR_NoRegs_Altivec_RegMask ; if ( Subtarget . isDarwin ( ) ) return CSR_NoRegs_Darwin_RegMask ; return CSR_NoRegs_RegMask ; } </s>

Return a register mask that clobbers everything .


<s> BTFTypeFwd :: BTFTypeFwd ( StringRef Name , bool IsUnion ) : Name ( Name ) { Kind = BTF :: BTF_KIND_FWD ; BTFType . Info = IsUnion << 31 | Kind << 24 ; BTFType . Type = 0 ; } </s>

Represent a struct/union forward declaration .


<s> bool ARMTargetLowering :: useLoadStackGuardNode ( ) const { return Subtarget -> isTargetMachO ( ) ; } </s>

If this function returns true , SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic : :stackprotector .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
CJG
::
NumTargetFixupKinds
]
=
{
{
"fixup_CJG_NONE"
,
0
,
32
,
0
}
,
{
"fixup_CJG_32"
,
0
,
32
,
0
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
{
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
}
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> unsigned XCoreInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { int Opcode = MI . getOpcode ( ) ; if ( Opcode == XCore :: LDWFI ) { if ( ( MI . getOperand ( 1 ) . isFI ( ) ) && ( MI . getOperand ( 2 ) . isImm ( ) ) && ( isZeroImm ( MI . getOperand ( 2 ) ) ) ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> bool DLXInstrInfo :: analyzeSelect ( const MachineInstr & MI , SmallVectorImpl < MachineOperand > & Cond , unsigned & TrueOp , unsigned & FalseOp , bool & Optimizable ) const { return false ; } </s>

Analyze the given select instruction , returning true if it can not be understood .


<s> TargetTransformInfo R600TargetMachine :: getTargetTransformInfo ( const Function & F ) { return TargetTransformInfo ( R600TTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> void MBlazeInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC ) const { DebugLoc dl = DebugLoc :: getUnknownLoc ( ) ; BuildMI ( MBB , I , dl , get ( MBlaze :: SWI ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addImm ( 0 ) . addFrameIndex ( FI ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> void tilepro_emit_conditional_branch ( rtx operands [ ] , machine_mode cmp_mode ) { rtx cmp_rtx = tilepro_emit_cc_test ( GET_CODE ( operands [ 0 ] ) , operands [ 1 ] , operands [ 2 ] , cmp_mode , false ) ; rtx branch_rtx = gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , cmp_rtx , gen_rtx_LABEL_REF ( VOIDmode , operands [ 3 ] ) , pc_rtx ) ) ; emit_jump_insn ( branch_rtx ) ; } </s>

Generate the comparison for a conditional branch .


<s> bool SITargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Align , bool * IsFast ) const { if ( IsFast ) * IsFast = false ; if ( ! VT . isSimple ( ) || VT == MVT :: Other ) return false ; if ( AddrSpace == AMDGPUAS :: LOCAL_ADDRESS ) { return Align % 4 == 0 ; } if ( VT . bitsLT ( MVT :: i32 ) ) return false ; if ( IsFast ) * IsFast = true ; return VT . bitsGT ( MVT :: i32 ) && Align % 4 == 0 ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> rtx rs6000_force_indexed_or_indirect_mem ( rtx x ) { machine_mode mode = GET_MODE ( x ) ; gcc_assert ( MEM_P ( x ) ) ; if ( can_create_pseudo_p ( ) && ! indexed_or_indirect_operand ( x , mode ) ) { rtx addr = XEXP ( x , 0 ) ; if ( GET_CODE ( addr ) == PRE_INC || GET_CODE ( addr ) == PRE_DEC ) { rtx reg = XEXP ( addr , 0 ) ; HOST_WIDE_INT size = GET_MODE_SIZE ( GET_MODE ( x ) ) ; rtx size_rtx = GEN_INT ( ( GET_CODE ( addr ) == PRE_DEC ) ? - size : size ) ; gcc_assert ( REG_P ( reg ) ) ; emit_insn ( gen_add3_insn ( reg , reg , size_rtx ) ) ; addr = reg ; } else if ( GET_CODE ( addr ) == PRE_MODIFY ) { rtx reg = XEXP ( addr , 0 ) ; rtx expr = XEXP ( addr , 1 ) ; gcc_assert ( REG_P ( reg ) ) ; gcc_assert ( GET_CODE ( expr ) == PLUS ) ; emit_insn ( gen_add3_insn ( reg , XEXP ( expr , 0 ) , XEXP ( expr , 1 ) ) ) ; addr = reg ; } x = replace_equiv_address ( x , force_reg ( Pmode , addr ) ) ; } return x ; } </s>

Given a memory reference , if it is not a reg or reg+reg addressing , convert to such a form to deal with memory reference instructions like STFIWX and LDBRX that only take reg+reg addressing .


<s> SMLoc getStartLoc ( ) const override { return Start ; } </s>

getStartLoc - Get the location of the first token of this operand .


"loadRegFromStackSlot didn't insert any code!"


<s> bool isReg ( ) const { return Kind == k_Register && ! Reg . isVector ; } </s>


"Frame offsets outside of the signed 32-bit range not supported"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> rtx c6x_return_addr_rtx ( int count ) { if ( count != 0 ) return const0_rtx ; return get_hard_reg_initial_val ( Pmode , RETURN_ADDR_REGNO ) ; } </s>

Return the value of the return address for the frame COUNT steps up from the current frame , after the prologue . We punt for everything but the current frame by returning const0_rtx .


<s>
StringRef
getPassName
(
)
const
override
{
return
"DLX Delay Slot Filler"
;
}
</s>


<s> MachineBasicBlock :: iterator MSP430FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const MSP430InstrInfo & TII = * static_cast < const MSP430InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; unsigned StackAlign = getStackAlignment ( ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr & Old = * I ; uint64_t Amount = Old . getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = nullptr ; if ( Old . getOpcode ( ) == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( MSP430 :: SUB16ri ) , MSP430 :: SP ) . addReg ( MSP430 :: SP ) . addImm ( Amount ) ; } else { assert ( Old . getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) ; uint64_t CalleeAmt = Old . getOperand ( 1 ) . getImm ( ) ; Amount -= CalleeAmt ; if ( Amount ) New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( MSP430 :: ADD16ri ) , MSP430 :: SP ) . addReg ( MSP430 :: SP ) . addImm ( Amount ) ; } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { MachineInstr & Old = * I ; MachineInstr * New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( MSP430 :: SUB16ri ) , MSP430 :: SP ) . addReg ( MSP430 :: SP ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } return MBB . erase ( I ) ; } </s>


<s> bool PatmosAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; MCInst MCI ; MCInstLowering . Lower ( MI , MCI ) ; PatmosInstPrinter PIP ( * OutContext . getAsmInfo ( ) , * TM . getInstrInfo ( ) , * TM . getRegisterInfo ( ) ) ; PIP . printOperand ( & MCI , OpNo , O , ExtraCode ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> const TargetRegisterClass * HSAILInstrInfo :: getOpRegClass ( const MachineRegisterInfo & MRI , const MachineInstr & MI , unsigned OpNo ) const { const MachineOperand & MO = MI . getOperand ( OpNo ) ; if ( ! MO . isReg ( ) ) return nullptr ; unsigned Reg = MO . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) return MRI . getRegClass ( Reg ) ; return RI . getPhysRegClass ( Reg ) ; } </s>

Return the correct register class for OpNo .


<s> bool X86TargetLowering :: IsDesirableToPromoteOp ( SDValue Op , EVT & PVT ) const { EVT VT = Op . getValueType ( ) ; if ( VT != MVT :: i16 ) return false ; bool Promote = false ; bool Commute = false ; switch ( Op . getOpcode ( ) ) { default : break ; case ISD :: SIGN_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: ANY_EXTEND : Promote = true ; break ; case ISD :: SHL : case ISD :: SRL : { SDValue N0 = Op . getOperand ( 0 ) ; if ( MayFoldLoad ( N0 ) && MayFoldIntoStore ( Op ) ) return false ; Promote = true ; break ; } case ISD :: ADD : case ISD :: MUL : case ISD :: AND : case ISD :: OR : case ISD :: XOR : Commute = true ; LLVM_FALLTHROUGH ; case ISD :: SUB : { SDValue N0 = Op . getOperand ( 0 ) ; SDValue N1 = Op . getOperand ( 1 ) ; if ( ! Commute && MayFoldLoad ( N1 ) ) return false ; if ( MayFoldLoad ( N0 ) && ( ! isa < ConstantSDNode > ( N1 ) || MayFoldIntoStore ( Op ) ) ) return false ; if ( MayFoldLoad ( N1 ) && ( ! isa < ConstantSDNode > ( N0 ) || MayFoldIntoStore ( Op ) ) ) return false ; Promote = true ; } } PVT = MVT :: i32 ; return Promote ; } </s>

Return true if the target has native support for the specified value type and it is 'desirable ' to use the type .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
bool
MipsAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
SmallVectorImpl
<
MCParsedAsmOperand
*
>
&
Operands
)
{
if
(
!
mnemonicIsValid
(
Name
,
0
)
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
NameLoc
,
"Unknown instruction"
)
;
}
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Name
,
NameLoc
)
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Mips
Mips
0
"Unknown instruction"
MipsOperand::CreateToken
"unexpected token in argument list"
"unexpected token in argument list"
"unexpected token in argument list"


<s> bool TL45FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || TRI -> needsStackRealignment ( MF ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


Define the ` __builtin_va_list ' type for the ABI .


<s> bool RISCVCallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < Register > VRegs ) const { MachineInstrBuilder Ret = MIRBuilder . buildInstrNoInsert ( RISCV :: PseudoRET ) ; if ( Val != nullptr ) { return false ; } MIRBuilder . insertInstr ( Ret ) ; return true ; } </s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> bool m32c_illegal_subreg_p ( rtx op ) { int offset ; unsigned int i ; machine_mode src_mode , dest_mode ; if ( GET_CODE ( op ) == MEM && ! m32c_legitimate_address_p ( Pmode , XEXP ( op , 0 ) , false ) ) { return true ; } if ( GET_CODE ( op ) != SUBREG ) return false ; dest_mode = GET_MODE ( op ) ; offset = SUBREG_BYTE ( op ) ; op = SUBREG_REG ( op ) ; src_mode = GET_MODE ( op ) ; if ( GET_MODE_SIZE ( dest_mode ) == GET_MODE_SIZE ( src_mode ) ) return false ; if ( GET_CODE ( op ) != REG ) return false ; if ( REGNO ( op ) >= MEM0_REGNO ) return false ; offset = ( 1 << offset ) ; for ( i = 0 ; i < ARRAY_SIZE ( legal_subregs ) ; i ++ ) if ( legal_subregs [ i ] . outer_mode_size == GET_MODE_SIZE ( dest_mode ) && legal_subregs [ i ] . regno == REGNO ( op ) && legal_subregs [ i ] . inner_mode_size == GET_MODE_SIZE ( src_mode ) && legal_subregs [ i ] . byte_mask & offset ) { switch ( legal_subregs [ i ] . legal_when ) { case 1 : return false ; case 16 : if ( TARGET_A16 ) return false ; break ; case 24 : if ( TARGET_A24 ) return false ; break ; } } return true ; } </s>

Returns TRUE if OP is a subreg of a hard reg which we do n't support . We also bail on MEMs with illegal addresses .


<s> const MCSymbol * MOSAsmPrinter :: getFunctionFrameSymbol ( int FI ) const { if ( MF -> getFrameInfo ( ) . getStackID ( FI ) == TargetStackID :: NoAlloc ) { MOSFunctionInfo & MFI = * MF -> getInfo < MOSFunctionInfo > ( ) ; return getSymbol ( MFI . getStaticStackVariable ( ) ) ; } return AsmPrinter :: getFunctionFrameSymbol ( FI ) ; } </s>

Return symbol for the function pseudo stack if the stack frame is not a register based .


<s> const WebAssemblySubtarget * WebAssemblyTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; resetTargetOptions ( F ) ; return getSubtargetImpl ( CPU , FS ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

WebAssembly WebAssembly WebAssembly "target-cpu" "target-features"


<s> static rtx ix86_function_arg ( cumulative_args_t cum_v , machine_mode omode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; machine_mode mode = omode ; HOST_WIDE_INT bytes , words ; rtx arg ; if ( ( type && POINTER_BOUNDS_TYPE_P ( type ) ) || POINTER_BOUNDS_MODE_P ( mode ) ) { if ( cum -> bnds_in_bt ) arg = NULL ; else if ( cum -> bnd_regno <= LAST_BND_REG ) arg = gen_rtx_REG ( BNDmode , cum -> bnd_regno ) ; else arg = GEN_INT ( cum -> bnd_regno - LAST_BND_REG - 1 ) ; return arg ; } if ( mode == BLKmode ) bytes = int_size_in_bytes ( type ) ; else bytes = GET_MODE_SIZE ( mode ) ; words = ( bytes + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) mode = type_natural_mode ( type , cum , false ) ; if ( TARGET_64BIT && ( cum ? cum -> call_abi : ix86_abi ) == MS_ABI ) arg = function_arg_ms_64 ( cum , mode , omode , named , bytes ) ; else if ( TARGET_64BIT ) arg = function_arg_64 ( cum , mode , omode , type , named ) ; else arg = function_arg_32 ( cum , mode , omode , type , bytes , words ) ; return arg ; } </s>

Return where to put the arguments to a function . Return zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument . It is null for libcalls where that information may not be available . CUM gives information about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) .


<s> static X86Operand * CreateReg ( unsigned RegNo , SMLoc StartLoc , SMLoc EndLoc ) { X86Operand * Res = new X86Operand ( Register , StartLoc , EndLoc ) ; Res -> Reg . RegNo = RegNo ; return Res ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s>
void
X86InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
assert
(
MF
.
getFrameInfo
(
)
.
getObjectSize
(
FrameIdx
)
>=
TRI
->
getSpillSize
(
*
RC
)
&&
"Stack slot too small for store"
)
;
unsigned
Alignment
=
std
::
max
<
uint32_t
>
(
TRI
->
getSpillSize
(
*
RC
)
,
16
)
;
bool
isAligned
=
(
Subtarget
.
getFrameLowering
(
)
->
getStackAlignment
(
)
>=
Alignment
)
||
RI
.
canRealignStack
(
MF
)
;
unsigned
Opc
=
getStoreRegOpcode
(
SrcReg
,
RC
,
isAligned
,
Subtarget
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DebugLoc
(
)
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> void SPUTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , char ConstraintLetter , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { TargetLowering :: LowerAsmOperandForConstraint ( Op , ConstraintLetter , Ops , DAG ) ; } </s>

Lower the specified operand into the Ops vector .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addPreserved < SlotIndexes > ( ) ; AU . addPreserved < LiveIntervals > ( ) ; AU . addPreserved < LiveVariables > ( ) ; AU . addRequired < LiveIntervals > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s>
const
char
*
aarch64_output_probe_sve_stack_clash
(
rtx
base
,
rtx
adjustment
,
rtx
min_probe_threshold
,
rtx
guard_size
)
{
gcc_assert
(
flag_stack_clash_protection
)
;
gcc_assert
(
CONST_INT_P
(
min_probe_threshold
)
&&
CONST_INT_P
(
guard_size
)
)
;
gcc_assert
(
INTVAL
(
guard_size
)
>
INTVAL
(
min_probe_threshold
)
)
;
HOST_WIDE_INT
residual_probe_guard
=
INTVAL
(
min_probe_threshold
)
;
residual_probe_guard
=
aarch64_clamp_to_uimm12_shift
(
residual_probe_guard
)
;
rtx
probe_offset_value_rtx
=
gen_int_mode
(
residual_probe_guard
,
Pmode
)
;
gcc_assert
(
INTVAL
(
min_probe_threshold
)
>=
residual_probe_guard
)
;
gcc_assert
(
aarch64_uimm12_shift
(
residual_probe_guard
)
)
;
static
int
labelno
=
0
;
char
loop_start_lab
[
32
]
;
char
loop_end_lab
[
32
]
;
rtx
xops
[
2
]
;
ASM_GENERATE_INTERNAL_LABEL
(
loop_start_lab
,
"SVLPSPL"
,
labelno
)
;
ASM_GENERATE_INTERNAL_LABEL
(
loop_end_lab
,
"SVLPEND"
,
labelno
++
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
loop_start_lab
)
;
xops
[
0
]
=
adjustment
;
xops
[
1
]
=
probe_offset_value_rtx
;
output_asm_insn
(
"cmp\t%0, %1"
,
xops
)
;
fputs
(
"\tb.lt\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
loop_end_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
xops
[
0
]
=
base
;
xops
[
1
]
=
probe_offset_value_rtx
;
output_asm_insn
(
"sub\t%0, %0, %1"
,
xops
)
;
xops
[
1
]
=
const0_rtx
;
output_asm_insn
(
"str\txzr, [%0, %1]"
,
xops
)
;
xops
[
0
]
=
adjustment
;
xops
[
1
]
=
probe_offset_value_rtx
;
output_asm_insn
(
"sub\t%0, %0, %1"
,
xops
)
;
fputs
(
"\tb\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
loop_start_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
loop_end_lab
)
;
xops
[
0
]
=
base
;
xops
[
1
]
=
adjustment
;
output_asm_insn
(
"sub\t%0, %0, %1"
,
xops
)
;
return
""
;
}
</s>

Emit the probe loop for doing stack clash probes and stack adjustments for SVE . This emits probes from BASE to BASE - ADJUSTMENT based on a guard size of GUARD_SIZE . When a probe is emitted it is done at most MIN_PROBE_THRESHOLD bytes from the current BASE at an interval of at most MIN_PROBE_THRESHOLD . By the end of this function BASE = BASE - ADJUSTMENT .


<s>
bool
X86InstrInfo
::
expandPostRAPseudo
(
MachineBasicBlock
::
iterator
MI
)
const
{
bool
HasAVX
=
TM
.
getSubtarget
<
X86Subtarget
>
(
)
.
hasAVX
(
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
X86
::
V_SET0
:
case
X86
::
FsFLD0SS
:
case
X86
::
FsFLD0SD
:
return
Expand2AddrUndef
(
MI
,
get
(
HasAVX
X86
::
VXORPSrr
:
X86
::
XORPSrr
)
)
;
case
X86
::
AVX_SET0
:
assert
(
HasAVX
&&
"AVX not supported"
)
;
return
Expand2AddrUndef
(
MI
,
get
(
X86
::
VXORPSYrr
)
)
;
case
X86
::
V_SETALLONES
:
return
Expand2AddrUndef
(
MI
,
get
(
HasAVX
X86
::
VPCMPEQDrr
:
X86
::
PCMPEQDrr
)
)
;
case
X86
::
AVX2_SETALLONES
:
return
Expand2AddrUndef
(
MI
,
get
(
X86
::
VPCMPEQDYrr
)
)
;
case
X86
::
TEST8ri_NOREX
:
MI
->
setDesc
(
get
(
X86
::
TEST8ri
)
)
;
return
true
;
}
return
false
;
}
</s>

This function is called for all pseudo instructions that remain after register allocation .


<s> void OutgoingValueHandler :: assignValueToAddress ( unsigned ValVReg , const CCValAssign & VA ) { MachineMemOperand * MMO ; unsigned Addr = getStackAddress ( VA , MMO ) ; unsigned ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildStore ( ExtReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> StackOffset SparcFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const SparcSubtarget & Subtarget = MF . getSubtarget < SparcSubtarget > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const SparcRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; const SparcMachineFunctionInfo * FuncInfo = MF . getInfo < SparcMachineFunctionInfo > ( ) ; bool isFixed = MFI . isFixedObjectIndex ( FI ) ; bool UseFP ; if ( FuncInfo -> isLeafProc ( ) ) { UseFP = false ; } else if ( isFixed ) { UseFP = true ; } else if ( RegInfo -> hasStackRealignment ( MF ) ) { UseFP = false ; } else { UseFP = true ; } int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) + Subtarget . getStackPointerBias ( ) ; if ( UseFP ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return StackOffset :: getFixed ( FrameOffset ) ; } else { FrameReg = SP :: O6 ; return StackOffset :: getFixed ( FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ) ; } } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .

Sparc Sparc Sparc Sparc Sparc Sparc Sparc SP::O6


<s> void J2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DstReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MI != MBB . end ( ) ? MI -> getDebugLoc ( ) : DebugLoc ( ) ; BuildMI ( MBB , MI , DL , get ( J2 :: MOV32mr ) , DstReg ) . addFrameIndex ( FrameIndex ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> unsigned find_next ( unsigned Prev ) const { int Next = BitVector :: find_next ( v2x ( Prev ) ) ; if ( Next < 0 ) return 0 ; return x2v ( Next ) ; } </s>

find_next - Returns the index of the next set bit starting from the `` Curr '' bit .


"********** ARM MVE VPT Optimisations **********\n"

runOnMachineFunction - Emit the function body .


<s> MachineBasicBlock :: iterator Z80oldFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { unsigned Amount = TII . getFrameSize ( * I ) ; if ( I -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) { Amount -= TII . getFramePoppedByCallee ( * I ) ; BuildStackAdjustment ( MF , MBB , I , I -> getDebugLoc ( ) , Amount ) ; } return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


"********** AArch64 Conditional Branch Tuning  **********\n"


<s>
void
final_prescan_insn
(
rtx_insn
*
insn
,
rtx
*
opvec
ATTRIBUTE_UNUSED
,
int
noperands
ATTRIBUTE_UNUSED
)
{
if
(
TARGET_DUMPISIZE
)
fprintf
(
asm_out_file
,
"\n! at %04x\n"
,
INSN_ADDRESSES
(
INSN_UID
(
insn
)
)
)
;
if
(
TARGET_RELAX
)
{
if
(
rtx
note
=
find_reg_note
(
insn
,
REG_LABEL_OPERAND
,
NULL_RTX
)
)
{
rtx
pattern
=
PATTERN
(
insn
)
;
if
(
GET_CODE
(
pattern
)
==
PARALLEL
)
pattern
=
XVECEXP
(
pattern
,
0
,
0
)
;
switch
(
GET_CODE
(
pattern
)
)
{
case
SET
:
if
(
GET_CODE
(
SET_SRC
(
pattern
)
)
!=
CALL
&&
get_attr_type
(
insn
)
!=
TYPE_SFUNC
)
{
targetm
.
asm_out
.
internal_label
(
asm_out_file
,
"L"
,
CODE_LABEL_NUMBER
(
XEXP
(
note
,
0
)
)
)
;
break
;
}
case
CALL
:
asm_fprintf
(
asm_out_file
,
"\t.uses %LL%d\n"
,
CODE_LABEL_NUMBER
(
XEXP
(
note
,
0
)
)
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
}
}
</s>

If defined , a C statement to be executed just prior to the output of assembler code for INSN , to modify the extracted operands so they will be output differently . Here the argument OPVEC is the vector containing the operands extracted from INSN , and NOPERANDS is the number of elements of the vector which contain meaningful data for this insn . The contents of this vector are what will be used to convert the insn template into assembler code , so you can change the assembler output by changing the contents of the vector . We use it to check if the current insn needs a nop in front of it because of load delays , and also to update the delay slot statistics .


<s>
const
char
*
m68k_output_movem
(
rtx
*
operands
,
rtx
pattern
,
HOST_WIDE_INT
automod_offset
,
bool
store_p
)
{
unsigned
int
mask
;
int
i
,
first
;
gcc_assert
(
GET_CODE
(
pattern
)
==
PARALLEL
)
;
mask
=
0
;
first
=
(
automod_offset
!=
0
)
;
for
(
i
=
first
;
i
<
XVECLEN
(
pattern
,
0
)
;
i
++
)
{
unsigned
int
regno
;
gcc_assert
(
MEM_P
(
XEXP
(
XVECEXP
(
pattern
,
0
,
i
)
,
!
store_p
)
)
)
;
gcc_assert
(
REG_P
(
XEXP
(
XVECEXP
(
pattern
,
0
,
i
)
,
store_p
)
)
)
;
regno
=
REGNO
(
XEXP
(
XVECEXP
(
pattern
,
0
,
i
)
,
store_p
)
)
;
if
(
automod_offset
<
0
)
{
if
(
FP_REGNO_P
(
regno
)
)
mask
|=
1
<<
(
regno
FP0_REG
)
;
else
mask
|=
1
<<
(
15
(
regno
D0_REG
)
)
;
}
else
{
if
(
FP_REGNO_P
(
regno
)
)
mask
|=
1
<<
(
7
(
regno
FP0_REG
)
)
;
else
mask
|=
1
<<
(
regno
D0_REG
)
;
}
}
CC_STATUS_INIT
;
if
(
automod_offset
==
0
)
operands
[
0
]
=
XEXP
(
XEXP
(
XVECEXP
(
pattern
,
0
,
first
)
,
!
store_p
)
,
0
)
;
else
if
(
automod_offset
<
0
)
operands
[
0
]
=
gen_rtx_PRE_DEC
(
Pmode
,
SET_DEST
(
XVECEXP
(
pattern
,
0
,
0
)
)
)
;
else
operands
[
0
]
=
gen_rtx_POST_INC
(
Pmode
,
SET_DEST
(
XVECEXP
(
pattern
,
0
,
0
)
)
)
;
operands
[
1
]
=
GEN_INT
(
mask
)
;
if
(
FP_REGNO_P
(
REGNO
(
XEXP
(
XVECEXP
(
pattern
,
0
,
first
)
,
store_p
)
)
)
)
{
if
(
store_p
)
return
"fmovem %1,%a0"
;
else
return
"fmovem %a0,%1"
;
}
else
{
if
(
store_p
)
return
"movem%.l %1,%a0"
;
else
return
"movem%.l %a0,%1"
;
}
}
</s>

Return the assembly code template for a movem or fmovem instruction whose pattern is given by PATTERN . Store the template 's operands in OPERANDS . If the instruction uses post-increment or pre-decrement addressing , AUTOMOD_OFFSET is the total adjustment , otherwise it is 0 . STORE_P is true if this is a store instruction .


<s> static int pa_arg_partial_bytes ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , bool named ATTRIBUTE_UNUSED ) { unsigned int max_arg_words = 8 ; unsigned int offset = 0 ; if ( ! TARGET_64BIT ) return 0 ; if ( FUNCTION_ARG_SIZE ( mode , type ) > 1 && ( cum -> words & 1 ) ) offset = 1 ; if ( cum -> words + offset + FUNCTION_ARG_SIZE ( mode , type ) <= max_arg_words ) return 0 ; else if ( cum -> words + offset >= max_arg_words ) return 0 ; else return ( max_arg_words - cum -> words - offset ) * UNITS_PER_WORD ; } </s>

If this arg would be passed totally in registers or totally on the stack , then this routine should return zero .