<s> SDValue ARMTargetLowering :: PerformBRCONDCombine ( SDNode * N , SelectionDAG & DAG ) const { SDValue Cmp = N -> getOperand ( 4 ) ; if ( Cmp . getOpcode ( ) != ARMISD :: CMPZ ) return SDValue ( ) ; EVT VT = N -> getValueType ( 0 ) ; SDLoc dl ( N ) ; SDValue LHS = Cmp . getOperand ( 0 ) ; SDValue RHS = Cmp . getOperand ( 1 ) ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue BB = N -> getOperand ( 1 ) ; SDValue ARMcc = N -> getOperand ( 2 ) ; ARMCC :: CondCodes CC = ( ARMCC :: CondCodes ) cast < ConstantSDNode > ( ARMcc ) -> getZExtValue ( ) ; if ( CC == ARMCC :: NE && LHS . getOpcode ( ) == ISD :: AND && LHS -> hasOneUse ( ) && LHS -> getOperand ( 0 ) -> getOpcode ( ) == ARMISD :: CMOV && LHS -> getOperand ( 0 ) -> hasOneUse ( ) ) { auto * LHS00C = dyn_cast < ConstantSDNode > ( LHS -> getOperand ( 0 ) -> getOperand ( 0 ) ) ; auto * LHS01C = dyn_cast < ConstantSDNode > ( LHS -> getOperand ( 0 ) -> getOperand ( 1 ) ) ; auto * LHS1C = dyn_cast < ConstantSDNode > ( LHS -> getOperand ( 1 ) ) ; auto * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ; if ( ( LHS00C && LHS00C -> getZExtValue ( ) == 0 ) && ( LHS01C && LHS01C -> getZExtValue ( ) == 1 ) && ( LHS1C && LHS1C -> getZExtValue ( ) == 1 ) && ( RHSC && RHSC -> getZExtValue ( ) == 0 ) ) { return DAG . getNode ( ARMISD :: BRCOND , dl , VT , Chain , BB , LHS -> getOperand ( 0 ) -> getOperand ( 2 ) , LHS -> getOperand ( 0 ) -> getOperand ( 3 ) , LHS -> getOperand ( 0 ) -> getOperand ( 4 ) ) ; } } return SDValue ( ) ; } </s>

PerformBRCONDCombine - Target-specific DAG combining for ARMISD : :BRCOND .


<s> bool Error ( SMLoc L , const Twine & Msg , SMRange Range = None , bool MatchingInlineAsm = false ) { MCAsmParser & Parser = getParser ( ) ; if ( MatchingInlineAsm ) { if ( ! getLexer ( ) . isAtStartOfStatement ( ) ) eatToEndOfLine ( ) ; return false ; } bool Result = Parser . Error ( L , Msg , Range ) ; eatToEndOfLine ( ) ; CurrentSlot = SlotParser :: Unknown ; Bundle . clear ( ) ; Bundle . setOpcode ( 0 ) ; Bundle . setLoc ( SMLoc ( ) ) ; return Result ; } </s>

Return an error at the location L , with the message Msg .


<s> void MipsMCInstLower :: Initialize ( MCContext * C ) { Ctx = C ; } </s>

This method must be called before any actual lowering is done .


<s>
bool
AArch64LegalizerInfo
::
legalizeCustom
(
MachineInstr
&
MI
,
MachineRegisterInfo
&
MRI
,
MachineIRBuilder
&
MIRBuilder
,
GISelChangeObserver
&
Observer
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
return
false
;
case
TargetOpcode
::
G_VAARG
:
return
legalizeVaArg
(
MI
,
MRI
,
MIRBuilder
)
;
case
TargetOpcode
::
G_LOAD
:
case
TargetOpcode
::
G_STORE
:
return
legalizeLoadStore
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
case
TargetOpcode
::
G_SHL
:
case
TargetOpcode
::
G_ASHR
:
case
TargetOpcode
::
G_LSHR
:
return
legalizeShlAshrLshr
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
}
llvm_unreachable
(
"expected switch to return"
)
;
}
</s>

Called for instructions with the Custom LegalizationAction .


<s>
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
WebAssemblyTargetLowering
::
getRegForInlineAsmConstraint
(
const
TargetRegisterInfo
*
TRI
,
StringRef
Constraint
,
MVT
VT
)
const
{
if
(
Constraint
.
size
(
)
==
1
)
{
switch
(
Constraint
[
0
]
)
{
case
'r'
:
assert
(
VT
!=
MVT
::
iPTR
&&
"Pointer MVT not expected here"
)
;
if
(
Subtarget
->
hasSIMD128
(
)
&&
VT
.
isVector
(
)
)
{
if
(
VT
.
getSizeInBits
(
)
==
128
)
return
std
::
make_pair
(
0U
,
&
WebAssembly
::
V128RegClass
)
;
}
if
(
VT
.
isInteger
(
)
&&
!
VT
.
isVector
(
)
)
{
if
(
VT
.
getSizeInBits
(
)
<=
32
)
return
std
::
make_pair
(
0U
,
&
WebAssembly
::
I32RegClass
)
;
if
(
VT
.
getSizeInBits
(
)
<=
64
)
return
std
::
make_pair
(
0U
,
&
WebAssembly
::
I64RegClass
)
;
}
break
;
default
:
break
;
}
}
return
TargetLowering
::
getRegForInlineAsmConstraint
(
TRI
,
Constraint
,
VT
)
;
}
</s>

Given a physical register constraint ( e.g .


<s>
bool
mep_mov_ok
(
rtx
*
operands
,
machine_mode
mode
ATTRIBUTE_UNUSED
)
{
int
i
;
fprintf
(
stderr
,
"mep_mov_ok %s %c=%c\n"
,
mode_name
[
mode
]
,
mep_section_tag
(
operands
[
0
]
)
,
mep_section_tag
(
operands
[
1
]
)
)
;
debug_rtx
(
operands
[
0
]
)
;
debug_rtx
(
operands
[
1
]
)
;
if
(
GET_CODE
(
operands
[
1
]
)
==
HIGH
)
return
false
;
if
(
mep_section_tag
(
operands
[
0
]
)
==
'f'
||
mep_section_tag
(
operands
[
1
]
)
==
'f'
)
{
fprintf
(
stderr
,
" - no, f\n"
)
;
return
false
;
}
i
=
mep_section_tag
(
operands
[
1
]
)
;
if
(
(
i
==
'b'
||
i
==
't'
)
&&
!
reload_completed
&&
!
reload_in_progress
)
{
fprintf
(
stderr
,
" - no, bt\n"
)
;
return
false
;
}
for
(
i
=
0
;
i
<
2
;
i
++
)
{
rtx
x
=
operands
[
i
]
;
if
(
GET_CODE
(
x
)
==
SUBREG
)
x
=
XEXP
(
x
,
0
)
;
if
(
GET_CODE
(
x
)
==
REG
&&
!
MEP_CONTROL_REG
(
x
)
)
{
fprintf
(
stderr
,
" - ok\n"
)
;
return
true
;
}
}
fprintf
(
stderr
,
" - no, no gen reg\n"
)
;
return
false
;
}
</s>

Cases where the pattern ca n't be made to use at all .


<s> bool gpr_or_gpr_p ( rtx op0 , rtx op1 ) { return ( ( REG_P ( op0 ) && INT_REGNO_P ( REGNO ( op0 ) ) ) || ( REG_P ( op1 ) && INT_REGNO_P ( REGNO ( op1 ) ) ) ) ; } </s>

Return true if either operand is a general purpose register .


<s> unsigned HOST_WIDE_INT s390_extract_part ( rtx op , machine_mode mode , int def ) { unsigned HOST_WIDE_INT value = 0 ; int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE ( mode ) ; int part_bits = GET_MODE_BITSIZE ( mode ) ; unsigned HOST_WIDE_INT part_mask = ( HOST_WIDE_INT_1U << part_bits ) - 1 ; int i ; for ( i = 0 ; i < max_parts ; i ++ ) { if ( i == 0 ) value = UINTVAL ( op ) ; else value >>= part_bits ; if ( ( value & part_mask ) != ( def & part_mask ) ) return value & part_mask ; } gcc_unreachable ( ) ; } </s>

Return the part of op which has a value different from def . The size of the part is determined by mode . Use this function only if you already know that op really contains such a part .


<s> static bool rs6000_legitimate_combined_insn ( rtx_insn * insn ) { int icode = INSN_CODE ( insn ) ; if ( icode != CODE_FOR_nothing && ( icode == CODE_FOR_bdz_si || icode == CODE_FOR_bdz_di || icode == CODE_FOR_bdnz_si || icode == CODE_FOR_bdnz_di || icode == CODE_FOR_bdztf_si || icode == CODE_FOR_bdztf_di || icode == CODE_FOR_bdnztf_si || icode == CODE_FOR_bdnztf_di ) ) return false ; return true ; } </s>

Implement the TARGET_LEGITIMATE_COMBINED_INSN hook .


<s> bool hasBranchDivergence ( ) { return true ; } </s>

Return true if branch divergence exists .


<s> void nds32_expand_epilogue_v3pop ( bool sibcall_p ) { int sp_adjust ; rtx Rb , Re ; rtx sp_adjust_insn ; nds32_compute_stack_frame ( ) ; emit_insn ( gen_blockage ( ) ) ; if ( cfun -> machine -> naked_p ) { if ( ! sibcall_p ) emit_jump_insn ( gen_return_internal ( ) ) ; return ; } Rb = gen_rtx_REG ( SImode , cfun -> machine -> callee_saved_first_gpr_regno ) ; Re = gen_rtx_REG ( SImode , cfun -> machine -> callee_saved_last_gpr_regno ) ; sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes ; if ( satisfies_constraint_Iu08 ( GEN_INT ( sp_adjust ) ) && NDS32_DOUBLE_WORD_ALIGN_P ( sp_adjust ) && ! cfun -> calls_alloca ) { nds32_emit_stack_v3pop ( Rb , Re , GEN_INT ( 14 ) , GEN_INT ( sp_adjust ) ) ; } else { if ( frame_pointer_needed ) { sp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size ; sp_adjust_insn = gen_addsi3 ( stack_pointer_rtx , hard_frame_pointer_rtx , GEN_INT ( - 1 * sp_adjust ) ) ; sp_adjust_insn = emit_insn ( sp_adjust_insn ) ; } else { sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes ; sp_adjust = nds32_force_addi_stack_int ( sp_adjust ) ; if ( sp_adjust ) { sp_adjust_insn = gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( sp_adjust ) ) ; sp_adjust_insn = emit_insn ( sp_adjust_insn ) ; } } nds32_emit_stack_v3pop ( Rb , Re , GEN_INT ( 14 ) , GEN_INT ( 0 ) ) ; } emit_jump_insn ( gen_pop25return ( ) ) ; } </s>


<s>
void
SystemZInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MBBI
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
SystemZ
::
GR128BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
copyPhysReg
(
MBB
,
MBBI
,
DL
,
RI
.
getSubReg
(
DestReg
,
SystemZ
::
subreg_h64
)
,
RI
.
getSubReg
(
SrcReg
,
SystemZ
::
subreg_h64
)
,
KillSrc
)
;
copyPhysReg
(
MBB
,
MBBI
,
DL
,
RI
.
getSubReg
(
DestReg
,
SystemZ
::
subreg_l64
)
,
RI
.
getSubReg
(
SrcReg
,
SystemZ
::
subreg_l64
)
,
KillSrc
)
;
return
;
}
if
(
SystemZ
::
GRX32BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
emitGRX32Move
(
MBB
,
MBBI
,
DL
,
DestReg
,
SrcReg
,
SystemZ
::
LR
,
32
,
KillSrc
)
;
return
;
}
unsigned
Opcode
;
if
(
SystemZ
::
GR64BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LGR
;
else
if
(
SystemZ
::
FP32BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
STI
.
hasVector
(
)
SystemZ
::
LDR32
:
SystemZ
::
LER
;
else
if
(
SystemZ
::
FP64BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LDR
;
else
if
(
SystemZ
::
FP128BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LXR
;
else
if
(
SystemZ
::
VR32BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
VLR32
;
else
if
(
SystemZ
::
VR64BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
VLR64
;
else
if
(
SystemZ
::
VR128BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
VLR
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
Opcode
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> bool HexagonTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { return Subtarget -> hasV5TOps ( ) ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s>
bool
HexagonPacketizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
const
TargetInstrInfo
*
TII
=
Fn
.
getTarget
(
)
.
getInstrInfo
(
)
;
MachineLoopInfo
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
MachineDominatorTree
&
MDT
=
getAnalysis
<
MachineDominatorTree
>
(
)
;
const
MachineBranchProbabilityInfo
*
MBPI
=
&
getAnalysis
<
MachineBranchProbabilityInfo
>
(
)
;
HexagonPacketizerList
Packetizer
(
Fn
,
MLI
,
MDT
,
MBPI
)
;
assert
(
Packetizer
.
getResourceTracker
(
)
&&
"Empty DFA table!"
)
;
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
MachineBasicBlock
::
iterator
End
=
MBB
->
end
(
)
;
MachineBasicBlock
::
iterator
MI
=
MBB
->
begin
(
)
;
while
(
MI
!=
End
)
{
if
(
MI
->
isKill
(
)
)
{
MachineBasicBlock
::
iterator
DeleteMI
=
MI
;
++
MI
;
MBB
->
erase
(
DeleteMI
)
;
End
=
MBB
->
end
(
)
;
continue
;
}
++
MI
;
}
}
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
unsigned
RemainingCount
=
MBB
->
size
(
)
;
for
(
MachineBasicBlock
::
iterator
RegionEnd
=
MBB
->
end
(
)
;
RegionEnd
!=
MBB
->
begin
(
)
;
)
{
MachineBasicBlock
::
iterator
I
=
RegionEnd
;
for
(
;
I
!=
MBB
->
begin
(
)
;
I
,
RemainingCount
)
{
if
(
TII
->
isSchedulingBoundary
(
std
::
prev
(
I
)
,
MBB
,
Fn
)
)
break
;
}
I
=
MBB
->
begin
(
)
;
if
(
I
==
RegionEnd
)
{
RegionEnd
=
std
::
prev
(
RegionEnd
)
;
RemainingCount
;
continue
;
}
if
(
I
==
std
::
prev
(
RegionEnd
)
)
{
RegionEnd
=
std
::
prev
(
RegionEnd
)
;
continue
;
}
Packetizer
.
PacketizeMIs
(
MBB
,
I
,
RegionEnd
)
;
RegionEnd
=
I
;
}
}
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .

Hexagon
Hexagon
Hexagon
"Empty DFA table!"


<s> void ARMTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , char Constraint , bool hasMemory , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { SDValue Result ( 0 , 0 ) ; switch ( Constraint ) { default : break ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'O' : ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ; if ( ! C ) return ; int64_t CVal64 = C -> getSExtValue ( ) ; int CVal = ( int ) CVal64 ; if ( CVal != CVal64 ) return ; switch ( Constraint ) { case 'I' : if ( Subtarget -> isThumb ( ) ) { if ( CVal >= 0 && CVal <= 255 ) break ; } else { if ( ARM_AM :: getSOImmVal ( CVal ) != - 1 ) break ; } return ; case 'J' : if ( Subtarget -> isThumb ( ) ) { if ( CVal >= - 255 && CVal <= - 1 ) break ; } else { if ( CVal >= - 4095 && CVal <= 4095 ) break ; } return ; case 'K' : if ( Subtarget -> isThumb ( ) ) { if ( CVal != 0 && ARM_AM :: isThumbImmShiftedVal ( CVal ) ) break ; } else { if ( ARM_AM :: getSOImmVal ( ~ CVal ) != - 1 ) break ; } return ; case 'L' : if ( Subtarget -> isThumb ( ) ) { if ( CVal >= - 7 && CVal < 7 ) break ; } else { if ( ARM_AM :: getSOImmVal ( - CVal ) != - 1 ) break ; } return ; case 'M' : if ( Subtarget -> isThumb ( ) ) { if ( ( CVal >= 0 && CVal <= 1020 ) && ( ( CVal & 3 ) == 0 ) ) break ; } else { if ( ( CVal >= 0 && CVal <= 32 ) || ( ( CVal & ( CVal - 1 ) ) == 0 ) ) break ; } return ; case 'N' : if ( Subtarget -> isThumb ( ) ) { if ( CVal >= 0 && CVal <= 31 ) break ; } return ; case 'O' : if ( Subtarget -> isThumb ( ) ) { if ( ( CVal >= - 508 && CVal <= 508 ) && ( ( CVal & 3 ) == 0 ) ) break ; } return ; } Result = DAG . getTargetConstant ( CVal , Op . getValueType ( ) ) ; break ; } if ( Result . getNode ( ) ) { Ops . push_back ( Result ) ; return ; } return TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , hasMemory , Ops , DAG ) ; } </s>

Lower the specified operand into the Ops vector .


<s> void SIWholeQuadMode :: processBlock ( MachineBasicBlock & MBB , unsigned LiveMaskReg , bool isEntry ) { auto BII = Blocks . find ( & MBB ) ; if ( BII == Blocks . end ( ) ) return ; const BlockInfo & BI = BII -> second ; if ( ! ( BI . InNeeds & StateWQM ) ) return ; if ( ! isEntry && ! ( BI . Needs & StateExact ) && BI . OutNeeds != StateExact ) return ; unsigned SavedWQMReg = 0 ; bool WQMFromExec = isEntry ; char State = isEntry ? StateExact : StateWQM ; auto II = MBB . getFirstNonPHI ( ) , IE = MBB . end ( ) ; while ( II != IE ) { MachineInstr & MI = * II ; ++ II ; if ( MI . getDesc ( ) . TSFlags & ( SIInstrFlags :: SALU | SIInstrFlags :: SMRD ) && ! MI . isBranch ( ) && ! MI . isTerminator ( ) ) continue ; if ( TargetInstrInfo :: isGenericOpcode ( MI . getOpcode ( ) ) ) { if ( MI . getNumExplicitOperands ( ) >= 1 ) { const MachineOperand & Op = MI . getOperand ( 0 ) ; if ( Op . isReg ( ) ) { if ( TRI -> isSGPRReg ( * MRI , Op . getReg ( ) ) ) { continue ; } } } } char Needs = 0 ; char OutNeeds = 0 ; auto InstrInfoIt = Instructions . find ( & MI ) ; if ( InstrInfoIt != Instructions . end ( ) ) { Needs = InstrInfoIt -> second . Needs ; OutNeeds = InstrInfoIt -> second . OutNeeds ; if ( OutNeeds == StateExact && ( MI . isBranch ( ) || MI . isTerminator ( ) ) ) { assert ( Needs == 0 ) ; Needs = StateExact ; } } if ( Needs && State != Needs ) { if ( Needs == StateExact ) { assert ( ! SavedWQMReg ) ; if ( ! WQMFromExec && ( OutNeeds & StateWQM ) ) SavedWQMReg = MRI -> createVirtualRegister ( & AMDGPU :: SReg_64RegClass ) ; toExact ( MBB , & MI , SavedWQMReg , LiveMaskReg ) ; } else { assert ( WQMFromExec == ( SavedWQMReg == 0 ) ) ; toWQM ( MBB , & MI , SavedWQMReg ) ; SavedWQMReg = 0 ; } State = Needs ; } if ( MI . getOpcode ( ) == AMDGPU :: SI_KILL ) WQMFromExec = false ; } if ( ( BI . OutNeeds & StateWQM ) && State != StateWQM ) { assert ( WQMFromExec == ( SavedWQMReg == 0 ) ) ; toWQM ( MBB , MBB . end ( ) , SavedWQMReg ) ; } else if ( BI . OutNeeds == StateExact && State != StateExact ) { toExact ( MBB , MBB . end ( ) , 0 , LiveMaskReg ) ; } } </s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s> static bool moxie_legitimate_address_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x , bool strict_p , addr_space_t as ) { gcc_assert ( ADDR_SPACE_GENERIC_P ( as ) ) ; if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , 0 ) ) && moxie_reg_ok_for_base_p ( XEXP ( x , 0 ) , strict_p ) && CONST_INT_P ( XEXP ( x , 1 ) ) && IN_RANGE ( INTVAL ( XEXP ( x , 1 ) ) , - 32768 , 32767 ) ) return true ; if ( REG_P ( x ) && moxie_reg_ok_for_base_p ( x , strict_p ) ) return true ; if ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF || GET_CODE ( x ) == CONST ) return true ; return false ; } </s>

Worker function for TARGET_LEGITIMATE_ADDRESS_P .


<s> static const char * arm_shift_nmem ( enum rtx_code code ) { switch ( code ) { case ASHIFT : return ARM_LSL_NAME ; case ASHIFTRT : return "asr" ; case LSHIFTRT : return "lsr" ; case ROTATERT : return "ror" ; default : abort ( ) ; } } </s>

Return the name of a shifter operation .


<s> void J2ConstantPoolValue :: print ( raw_ostream & O ) const { O << Value ; } </s>

print - Print a debug representation of the operand to the given stream .


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> std :: pair < const TargetRegisterClass * , uint8_t > ARMTargetLowering :: findRepresentativeClass ( EVT VT ) const { const TargetRegisterClass * RRC = 0 ; uint8_t Cost = 1 ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( VT ) ; case MVT :: f32 : case MVT :: f64 : case MVT :: v8i8 : case MVT :: v4i16 : case MVT :: v2i32 : case MVT :: v1i64 : case MVT :: v2f32 : RRC = ARM :: DPRRegisterClass ; if ( Subtarget -> useNEONForSinglePrecisionFP ( ) ) Cost = 2 ; break ; case MVT :: v16i8 : case MVT :: v8i16 : case MVT :: v4i32 : case MVT :: v2i64 : case MVT :: v4f32 : case MVT :: v2f64 : RRC = ARM :: DPRRegisterClass ; Cost = 2 ; break ; case MVT :: v4i64 : RRC = ARM :: DPRRegisterClass ; Cost = 4 ; break ; case MVT :: v8i64 : RRC = ARM :: DPRRegisterClass ; Cost = 8 ; break ; } return std :: make_pair ( RRC , Cost ) ; } </s>

Return the largest legal super-reg register class of the register class for the specified type and its associated `` cost '' .


<s> static HOST_WIDE_INT rotate_right ( HOST_WIDE_INT n , int count ) { unsigned HOST_WIDE_INT x = n & 0xFFFFFFFFFFFFFFFFULL ; if ( count == 0 ) return x ; return ( ( x >> count ) | ( x << ( 64 - count ) ) ) & 0xFFFFFFFFFFFFFFFFULL ; } </s>


<s> unsigned SparcInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == SP :: STri || MI -> getOpcode ( ) == SP :: STXri || MI -> getOpcode ( ) == SP :: STFri || MI -> getOpcode ( ) == SP :: STDFri ) { if ( MI -> getOperand ( 0 ) . isFI ( ) && MI -> getOperand ( 1 ) . isImm ( ) && MI -> getOperand ( 1 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 0 ) . getIndex ( ) ; return MI -> getOperand ( 2 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"PowerPC Branch Selector"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> std :: unique_ptr < MCObjectWriter > BPFAsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { return createBPFELFObjectWriter ( OS , 0 , IsLittleEndian ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> bool MVEGatherScatterLowering :: runOnFunction ( Function & F ) { if ( ! EnableMaskedGatherScatters ) return false ; auto & TPC = getAnalysis < TargetPassConfig > ( ) ; auto & TM = TPC . getTM < TargetMachine > ( ) ; auto * ST = & TM . getSubtarget < ARMSubtarget > ( F ) ; if ( ! ST -> hasMVEIntegerOps ( ) ) return false ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SmallVector < IntrinsicInst * , 4 > Gathers ; SmallVector < IntrinsicInst * , 4 > Scatters ; bool Changed = false ; for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & I ) ; if ( II && II -> getIntrinsicID ( ) == Intrinsic :: masked_gather && isa < FixedVectorType > ( II -> getType ( ) ) ) { Gathers . push_back ( II ) ; Changed |= optimiseAddress ( II -> getArgOperand ( 0 ) , II -> getParent ( ) , LI ) ; } else if ( II && II -> getIntrinsicID ( ) == Intrinsic :: masked_scatter && isa < FixedVectorType > ( II -> getArgOperand ( 0 ) -> getType ( ) ) ) { Scatters . push_back ( II ) ; Changed |= optimiseAddress ( II -> getArgOperand ( 1 ) , II -> getParent ( ) , LI ) ; } } } for ( unsigned i = 0 ; i < Gathers . size ( ) ; i ++ ) { IntrinsicInst * I = Gathers [ i ] ; Value * L = lowerGather ( I ) ; if ( L == nullptr ) continue ; SimplifyInstructionsInBlock ( cast < Instruction > ( L ) -> getParent ( ) ) ; Changed = true ; } for ( unsigned i = 0 ; i < Scatters . size ( ) ; i ++ ) { IntrinsicInst * I = Scatters [ i ] ; Value * S = lowerScatter ( I ) ; if ( S == nullptr ) continue ; SimplifyInstructionsInBlock ( cast < Instruction > ( S ) -> getParent ( ) ) ; Changed = true ; } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void SIFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const SIMachineFunctionInfo * FuncInfo = MF . getInfo < SIMachineFunctionInfo > ( ) ; if ( FuncInfo -> isEntryFunction ( ) ) return ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const SIInstrInfo * TII = ST . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; DebugLoc DL ; unsigned ScratchExecCopy = AMDGPU :: NoRegister ; for ( const SIMachineFunctionInfo :: SGPRSpillVGPRCSR & Reg : FuncInfo -> getSGPRSpillVGPRs ( ) ) { if ( ! Reg . FI . hasValue ( ) ) continue ; const SIRegisterInfo & TRI = TII -> getRegisterInfo ( ) ; if ( ScratchExecCopy == AMDGPU :: NoRegister ) { LivePhysRegs LiveRegs ( * ST . getRegisterInfo ( ) ) ; LiveRegs . addLiveOuts ( MBB ) ; LiveRegs . stepBackward ( * MBBI ) ; ScratchExecCopy = findScratchNonCalleeSaveRegister ( MF , LiveRegs , * TRI . getWaveMaskRegClass ( ) ) ; const unsigned OrSaveExec = ST . isWave32 ( ) ? AMDGPU :: S_OR_SAVEEXEC_B32 : AMDGPU :: S_OR_SAVEEXEC_B64 ; BuildMI ( MBB , MBBI , DL , TII -> get ( OrSaveExec ) , ScratchExecCopy ) . addImm ( - 1 ) ; } TII -> loadRegFromStackSlot ( MBB , MBBI , Reg . VGPR , Reg . FI . getValue ( ) , & AMDGPU :: VGPR_32RegClass , & TII -> getRegisterInfo ( ) ) ; } if ( ScratchExecCopy != AMDGPU :: NoRegister ) { unsigned ExecMov = ST . isWave32 ( ) ? AMDGPU :: S_MOV_B32 : AMDGPU :: S_MOV_B64 ; unsigned Exec = ST . isWave32 ( ) ? AMDGPU :: EXEC_LO : AMDGPU :: EXEC ; BuildMI ( MBB , MBBI , DL , TII -> get ( ExecMov ) , Exec ) . addReg ( ScratchExecCopy ) ; } const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; uint32_t NumBytes = MFI . getStackSize ( ) ; uint32_t RoundedSize = FuncInfo -> isStackRealigned ( ) ? NumBytes + MFI . getMaxAlignment ( ) : NumBytes ; if ( RoundedSize != 0 && hasFP ( MF ) ) { const unsigned StackPtrReg = FuncInfo -> getStackPtrOffsetReg ( ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( AMDGPU :: S_SUB_U32 ) , StackPtrReg ) . addReg ( StackPtrReg ) . addImm ( RoundedSize * ST . getWavefrontSize ( ) ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } } </s>


<s> bool R600InstrInfo :: isPredicated ( const MachineInstr * MI ) const { int idx = MI -> findFirstPredOperandIdx ( ) ; if ( idx < 0 ) return false ; unsigned Reg = MI -> getOperand ( idx ) . getReg ( ) ; switch ( Reg ) { default : return false ; case AMDGPU :: PRED_SEL_ONE : case AMDGPU :: PRED_SEL_ZERO : case AMDGPU :: PREDICATE_BIT : return true ; } } </s>

Returns true if the instruction is already predicated .


<s> void AVRPassConfig :: addPreSched2 ( ) { addPass ( createAVRRelaxMemPass ( ) ) ; addPass ( createAVRExpandPseudoPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> const char * getPassName ( ) const override { return AARCH64_COLLECT_LOH_NAME ; } </s>


<s> bool AArch64DummyPA :: runOnMachineFunction ( MachineFunction & MF ) { STI = & MF . getSubtarget < AArch64Subtarget > ( ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; bool Changed = false ; for ( auto & MBB : MF ) { for ( auto MBBI = MBB . begin ( ) , End = MBB . end ( ) ; MBBI != End ; ) { auto & MI = * MBBI ++ ; switch ( MI . getOpcode ( ) ) { default : break ; case AArch64 :: PACIA : case AArch64 :: PACIB : case AArch64 :: PACDA : case AArch64 :: PACDB : case AArch64 :: AUTIA : case AArch64 :: AUTIB : case AArch64 :: AUTDA : case AArch64 :: AUTDB : Changed = convertBasicPAInstr ( MBB , MI ) | Changed ; break ; case AArch64 :: PACIASP : case AArch64 :: PACIBSP : case AArch64 :: AUTIASP : case AArch64 :: AUTIBSP : Changed = convertSpPAInstr ( MBB , MI ) | Changed ; break ; case AArch64 :: RETAA : case AArch64 :: RETAB : Changed = convertRetPAInstr ( MBB , MI ) | Changed ; break ; case AArch64 :: PACGA : case AArch64 :: PACDZA : case AArch64 :: PACDZB : case AArch64 :: PACIZA : case AArch64 :: PACIZB : case AArch64 :: PACIA1716 : case AArch64 :: PACIAZ : case AArch64 :: PACIB1716 : case AArch64 :: PACIBZ : case AArch64 :: AUTDZA : case AArch64 :: AUTDZB : case AArch64 :: AUTIZA : case AArch64 :: AUTIZB : case AArch64 :: AUTIA1716 : case AArch64 :: AUTIAZ : case AArch64 :: AUTIB1716 : case AArch64 :: AUTIBZ : llvm_unreachable ( "unsupported" ) ; } } } return Changed ; } </s>


"missing feature modifier in target %s %qs"

"invalid feature modifier in target %s %qs"

Parse an architecture extensions target attribute string specified in STR . For example `` +fp+nosimd '' . Show any errors if needed . Return TRUE if successful . Update aarch64_isa_flags to reflect the ISA features modified . PRAGMA_OR_ATTR is used in potential error messages .


<s> void arm_gen_unlikely_cbranch ( enum rtx_code code , machine_mode cc_mode , rtx label_ref ) { rtx x ; x = gen_rtx_fmt_ee ( code , VOIDmode , gen_rtx_REG ( cc_mode , CC_REGNUM ) , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( VOIDmode , label_ref ) , pc_rtx ) ; emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } </s>

Generate RTL for a conditional branch with rtx comparison CODE in mode CC_MODE . The destination of the unlikely conditional branch is LABEL_REF .


<s> static int elf_dcachebsize ( void ) { int fd ; fd = open ( "/proc/self/auxv" , O_RDONLY ) ; if ( fd != - 1 ) { char buf [ 1024 ] ; ElfW ( auxv_t ) * av ; ssize_t n ; n = read ( fd , buf , sizeof ( buf ) ) ; close ( fd ) ; if ( n > 0 ) { for ( av = ( ElfW ( auxv_t ) * ) buf ; av -> a_type != AT_NULL ; ++ av ) switch ( av -> a_type ) { case AT_DCACHEBSIZE : return av -> a_un . a_val ; default : break ; } } } </s>

Returns AT_DCACHEBSIZE if present , otherwise generic 32 .


<s> TargetPassConfig * RISCVTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new TargetPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> bool SITargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { if ( ! CI -> isTailCall ( ) ) return false ; const Function * ParentFn = CI -> getParent ( ) -> getParent ( ) ; if ( AMDGPU :: isEntryFunctionCC ( ParentFn -> getCallingConv ( ) ) ) return false ; return true ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> unsigned AMDGPUCFGStructurizer :: getLoopDepth ( MachineLoop * LoopRep ) { return LoopRep ? LoopRep -> getLoopDepth ( ) : 0 ; } </s>

Return the loop nesting level of the specified block .


<s>
void
MipsSEInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
=
0
,
ZeroReg
=
0
;
if
(
Mips
::
GPR32RegClass
.
contains
(
DestReg
)
)
{
if
(
Mips
::
GPR32RegClass
.
contains
(
SrcReg
)
)
{
Opc
=
Mips
::
ADDu
,
ZeroReg
=
Mips
::
ZERO
;
}
else
if
(
Mips
::
FGR32RegClass
.
contains
(
SrcReg
)
)
{
Opc
=
Mips
::
MFC1
;
}
}
else
if
(
Mips
::
GPR32RegClass
.
contains
(
SrcReg
)
)
{
if
(
Mips
::
FGR32RegClass
.
contains
(
DestReg
)
)
{
Opc
=
Mips
::
MTC1
;
}
}
else
if
(
Mips
::
FGR32RegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
Opc
=
Mips
::
FMOV_S
;
}
else
if
(
Mips
::
AFGR64RegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
Opc
=
Mips
::
FMOV_D32
;
}
assert
(
Opc
&&
"Cannot copy registers"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
)
;
if
(
DestReg
)
MIB
.
addReg
(
DestReg
,
RegState
::
Define
)
;
if
(
SrcReg
)
MIB
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
if
(
ZeroReg
)
MIB
.
addReg
(
ZeroReg
)
;
}
</s>


<s> const RegisterBankInfo * PPCSubtarget :: getRegBankInfo ( ) const { return RegBankInfo . get ( ) ; } </s>

If the information for the register banks is available , return it .


<s> void PatmosAsmPrinter :: emitFunctionBodyEnd ( ) { OutStreamer -> emitLabel ( CurrCodeEnd ) ; } </s>

Targets can override this to emit stuff after the last basic block in the function .


<s> static rtx_insn * get_next_active_insn ( rtx_insn * insn , rtx_insn * tail ) { if ( insn == NULL_RTX || insn == tail ) return NULL ; while ( 1 ) { insn = NEXT_INSN ( insn ) ; if ( insn == NULL_RTX || insn == tail ) return NULL ; if ( CALL_P ( insn ) || JUMP_P ( insn ) || JUMP_TABLE_DATA_P ( insn ) || ( NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER && INSN_CODE ( insn ) != CODE_FOR_stack_tie ) ) break ; } return insn ; } </s>

Return the next insn after INSN that is found before TAIL is reached , skipping any `` non-active '' insns - insns that will not actually occupy an issue slot . Return NULL_RTX if such an insn is not found .


<s> bool AMDGPUFrameLowering :: hasFP ( const MachineFunction & MF ) const { return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> const MCPhysReg * PPCRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const PPCSubtarget & Subtarget = MF -> getSubtarget < PPCSubtarget > ( ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: AnyReg ) { if ( Subtarget . hasVSX ( ) ) return CSR_64_AllRegs_VSX_SaveList ; if ( Subtarget . hasAltivec ( ) ) return CSR_64_AllRegs_Altivec_SaveList ; return CSR_64_AllRegs_SaveList ; } if ( TM . isPPC64 ( ) && MF -> getInfo < PPCFunctionInfo > ( ) -> isSplitCSR ( ) ) return CSR_SRV464_TLS_PE_SaveList ; bool SaveR2 = MF -> getRegInfo ( ) . isAllocatable ( PPC :: X2 ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: Cold ) { if ( TM . isPPC64 ( ) ) { if ( Subtarget . hasAltivec ( ) ) return SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList : CSR_SVR64_ColdCC_Altivec_SaveList ; return SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList : CSR_SVR64_ColdCC_SaveList ; } if ( Subtarget . hasAltivec ( ) ) return CSR_SVR32_ColdCC_Altivec_SaveList ; else if ( Subtarget . hasSPE ( ) ) return CSR_SVR32_ColdCC_SPE_SaveList ; return CSR_SVR32_ColdCC_SaveList ; } if ( TM . isPPC64 ( ) ) { if ( Subtarget . hasAltivec ( ) ) return SaveR2 ? CSR_SVR464_R2_Altivec_SaveList : CSR_SVR464_Altivec_SaveList ; return SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList ; } if ( Subtarget . hasAltivec ( ) ) return CSR_SVR432_Altivec_SaveList ; else if ( Subtarget . hasSPE ( ) ) return CSR_SVR432_SPE_SaveList ; return CSR_SVR432_SaveList ; } </s>

PowerPC PPC PPC PPC PPC PPC PPC::X2 PPC PPC


<s> bool ARMBaseInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TBB , unsigned TCycles , unsigned TExtra , MachineBasicBlock & FBB , unsigned FCycles , unsigned FExtra , BranchProbability Probability ) const { if ( ! TCycles ) return false ; const unsigned ScalingUpFactor = 1024 ; unsigned PredCost = ( TCycles + FCycles + TExtra + FExtra ) * ScalingUpFactor ; unsigned UnpredCost ; if ( ! Subtarget . hasBranchPredictor ( ) ) { unsigned NotTakenBranchCost = 1 ; unsigned TakenBranchCost = Subtarget . getMispredictionPenalty ( ) ; unsigned TUnpredCycles , FUnpredCycles ; if ( ! FCycles ) { TUnpredCycles = TCycles + NotTakenBranchCost ; FUnpredCycles = TakenBranchCost ; } else { TUnpredCycles = TCycles + TakenBranchCost ; FUnpredCycles = FCycles + NotTakenBranchCost ; } unsigned TUnpredCost = Probability . scale ( TUnpredCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FUnpredCycles * ScalingUpFactor ) ; UnpredCost = TUnpredCost + FUnpredCost ; if ( Subtarget . isThumb2 ( ) && TCycles + FCycles > 4 ) { PredCost += ( ( TCycles + FCycles - 4 ) / 4 ) * ScalingUpFactor ; } } else { unsigned TUnpredCost = Probability . scale ( TCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FCycles * ScalingUpFactor ) ; UnpredCost = TUnpredCost + FUnpredCost ; UnpredCost += 1 * ScalingUpFactor ; UnpredCost += Subtarget . getMispredictionPenalty ( ) * ScalingUpFactor / 10 ; } return PredCost <= UnpredCost ; } </s>


<s> static tree arm_promoted_type ( const_tree t ) { if ( SCALAR_FLOAT_TYPE_P ( t ) && TYPE_PRECISION ( t ) == 16 ) return float_type_node ; return NULL_TREE ; } </s>


<s> MachineInstr * SPUInstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , int FrameIndex ) const { if ( Ops . size ( ) != 1 ) return 0 ; unsigned OpNum = Ops [ 0 ] ; unsigned Opc = MI -> getOpcode ( ) ; MachineInstr * NewMI = 0 ; switch ( Opc ) { case SPU :: ORv16i8 : case SPU :: ORv8i16 : case SPU :: ORv4i32 : case SPU :: ORv2i64 : case SPU :: ORr8 : case SPU :: ORr16 : case SPU :: ORr32 : case SPU :: ORr64 : case SPU :: ORf32 : case SPU :: ORf64 : if ( OpNum == 0 ) { unsigned InReg = MI -> getOperand ( 1 ) . getReg ( ) ; bool isKill = MI -> getOperand ( 1 ) . isKill ( ) ; if ( FrameIndex < SPUFrameInfo :: maxFrameOffset ( ) ) { MachineInstrBuilder MIB = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( SPU :: STQDr32 ) ) ; MIB . addReg ( InReg , false , false , isKill ) ; NewMI = addFrameReference ( MIB , FrameIndex ) ; } } else { unsigned OutReg = MI -> getOperand ( 0 ) . getReg ( ) ; bool isDead = MI -> getOperand ( 0 ) . isDead ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( Opc ) ) ; MIB . addReg ( OutReg , true , false , false , isDead ) ; Opc = ( FrameIndex < SPUFrameInfo :: maxFrameOffset ( ) ) ? SPU :: STQDr32 : SPU :: STQXr32 ; NewMI = addFrameReference ( MIB , FrameIndex ) ; break ; } } return NewMI ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> const MCExpr * WebAssemblyAsmPrinter :: lowerConstant ( const Constant * CV ) { if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( CV ) ) if ( GV -> getValueType ( ) -> isFunctionTy ( ) ) return MCSymbolRefExpr :: create ( getSymbol ( GV ) , MCSymbolRefExpr :: VK_WebAssembly_FUNCTION , OutContext ) ; return AsmPrinter :: lowerConstant ( CV ) ; } </s>

Lower the specified LLVM Constant to an MCExpr .


<s> unsigned AMDGPURegisterBankInfo :: getBreakDownCost ( const ValueMapping & ValMapping , const RegisterBank * CurBank ) const { if ( ValMapping . NumBreakDowns >= 2 || ValMapping . BreakDown [ 0 ] . Length >= 64 ) return 10 ; assert ( ValMapping . NumBreakDowns == 2 && ValMapping . BreakDown [ 0 ] . Length == 32 && ValMapping . BreakDown [ 0 ] . StartIdx == 0 && ValMapping . BreakDown [ 1 ] . Length == 32 && ValMapping . BreakDown [ 1 ] . StartIdx == 32 && ValMapping . BreakDown [ 0 ] . RegBank == ValMapping . BreakDown [ 1 ] . RegBank ) ; return 1 ; } </s>

Get the cost of using ValMapping to decompose a register .


<s> bool AArch64PassConfig :: addPreRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAdvSIMDScalar ) addPass ( createAArch64AdvSIMDScalar ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s>
StringRef
getPassName
(
)
const
override
{
return
"TPC Set Spill Base"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
const
char
*
output_move_vfp
(
rtx
*
operands
)
{
rtx
reg
,
mem
,
addr
,
ops
[
2
]
;
int
load
=
REG_P
(
operands
[
0
]
)
;
int
dp
=
GET_MODE_SIZE
(
GET_MODE
(
operands
[
0
]
)
)
==
8
;
int
integer_p
=
GET_MODE_CLASS
(
GET_MODE
(
operands
[
0
]
)
)
==
MODE_INT
;
const
char
*
templ
;
char
buff
[
50
]
;
machine_mode
mode
;
reg
=
operands
[
!
load
]
;
mem
=
operands
[
load
]
;
mode
=
GET_MODE
(
reg
)
;
gcc_assert
(
REG_P
(
reg
)
)
;
gcc_assert
(
IS_VFP_REGNUM
(
REGNO
(
reg
)
)
)
;
gcc_assert
(
mode
==
SFmode
||
mode
==
DFmode
||
mode
==
SImode
||
mode
==
DImode
||
(
TARGET_NEON
&&
VALID_NEON_DREG_MODE
(
mode
)
)
)
;
gcc_assert
(
MEM_P
(
mem
)
)
;
addr
=
XEXP
(
mem
,
0
)
;
switch
(
GET_CODE
(
addr
)
)
{
case
PRE_DEC
:
templ
=
"v%smdb%%?.%s\t%%0!, {%%%s1}%s"
;
ops
[
0
]
=
XEXP
(
addr
,
0
)
;
ops
[
1
]
=
reg
;
break
;
case
POST_INC
:
templ
=
"v%smia%%?.%s\t%%0!, {%%%s1}%s"
;
ops
[
0
]
=
XEXP
(
addr
,
0
)
;
ops
[
1
]
=
reg
;
break
;
default
:
templ
=
"v%sr%%?.%s\t%%%s0, %%1%s"
;
ops
[
0
]
=
reg
;
ops
[
1
]
=
mem
;
break
;
}
sprintf
(
buff
,
templ
,
load
"ld"
:
"st"
,
dp
"64"
:
"32"
,
dp
"P"
:
""
,
integer_p
"\t%@ int"
:
""
)
;
output_asm_insn
(
buff
,
ops
)
;
return
""
;
}
</s>

Output a VFP load or store instruction .


<s>
static
uint8_t
name
(
struct
InternalInstruction
*
insn
,
\
OperandType
type
,
\
uint8_t
index
,
\
uint8_t
*
valid
)
{
\
*
valid
=
1
;
\
switch
(
type
)
{
\
default
:
\
debug
(
"Unhandled register type"
)
;
\
*
valid
=
0
;
\
return
0
;
\
case
TYPE_Rv
:
\
return
base
+
index
;
\
case
TYPE_R8
:
\
if
(
insn
->
rexPrefix
&&
\
index
>=
4
&&
index
<=
7
)
{
\
return
prefix
##
_SPL
+
(
index
4
)
;
\
}
else
{
\
return
prefix
##
_AL
+
index
;
\
}
\
case
TYPE_R16
:
\
return
prefix
##
_AX
+
index
;
\
case
TYPE_R32
:
\
return
prefix
##
_EAX
+
index
;
\
case
TYPE_R64
:
\
return
prefix
##
_RAX
+
index
;
\
case
TYPE_XMM512
:
\
return
prefix
##
_ZMM0
+
index
;
\
case
TYPE_XMM256
:
\
return
prefix
##
_YMM0
+
index
;
\
case
TYPE_XMM128
:
\
case
TYPE_XMM64
:
\
case
TYPE_XMM32
:
\
case
TYPE_XMM
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_VK1
:
\
case
TYPE_VK8
:
\
case
TYPE_VK16
:
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_K0
+
index
;
\
case
TYPE_MM64
:
\
return
prefix
##
_MM0
+
(
index
&
0x7
)
;
\
case
TYPE_SEGMENTREG
:
\
if
(
index
>
5
)
\
*
valid
=
0
;
\
return
prefix
##
_ES
+
index
;
\
case
TYPE_DEBUGREG
:
\
return
prefix
##
_DR0
+
index
;
\
case
TYPE_CONTROLREG
:
\
return
prefix
##
_CR0
+
index
;
\
}
\
}
</s>

Gets the name of the pass we are mixed into .


<s> bool TeakRegisterInfo :: requiresVirtualBaseRegisters ( const MachineFunction & MF ) const { return false ; } </s>

Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers used for more efficient stack access .


<s> DiagnosticInfoUnsupported ( SDLoc DLoc , const Function & Fn , const Twine & Desc , SDValue Value ) : DiagnosticInfo ( getKindID ( ) , DS_Error ) , DLoc ( DLoc . getDebugLoc ( ) ) , Description ( Desc ) , Fn ( Fn ) , Value ( Value ) { } </s>

Fn is the function where the diagnostic is being emitted .


<s> bool isReg ( ) const override { return Kind == Register ; } </s>


<s> void HexagonPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( ! DisableStoreWidening ) addPass ( createHexagonStoreWidening ( ) , false ) ; if ( ! DisableHardwareLoops ) addPass ( createHexagonHardwareLoops ( ) , false ) ; } } </s>


<s> tree s390_valid_target_attribute_tree ( tree args , struct gcc_options * opts , const struct gcc_options * opts_set , bool force_pragma ) { tree t = NULL_TREE ; struct gcc_options new_opts_set ; memset ( & new_opts_set , 0 , sizeof ( new_opts_set ) ) ; if ( ! s390_valid_target_attribute_inner_p ( args , opts , & new_opts_set , force_pragma ) ) return error_mark_node ; if ( new_opts_set . x_target_flags || new_opts_set . x_s390_arch || new_opts_set . x_s390_tune || new_opts_set . x_s390_stack_guard || new_opts_set . x_s390_stack_size || new_opts_set . x_s390_branch_cost || new_opts_set . x_s390_warn_framesize || new_opts_set . x_s390_warn_dynamicstack_p ) { const unsigned char * src = ( const unsigned char * ) opts_set ; unsigned char * dest = ( unsigned char * ) & new_opts_set ; unsigned int i ; for ( i = 0 ; i < sizeof ( * opts_set ) ; i ++ ) dest [ i ] |= src [ i ] ; s390_option_override_internal ( opts , & new_opts_set ) ; t = build_target_option_node ( opts , & new_opts_set ) ; } return t ; } </s>

Return a TARGET_OPTION_NODE tree of the target options listed or NULL .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { STI = & MF . getSubtarget < M68kSubtarget > ( ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; MFI = MF . getInfo < M68kMachineFunctionInfo > ( ) ; FL = STI -> getFrameLowering ( ) ; bool Modified = false ; MOVEMState State ; unsigned Mask = 0 ; unsigned Reg = 0 ; int Offset = 0 ; for ( auto & MBB : MF ) { auto MI = MBB . begin ( ) , E = MBB . end ( ) ; while ( MI != E ) { auto NMI = std :: next ( MI ) ; switch ( MI -> getOpcode ( ) ) { default : if ( State . hasBase ( ) ) { State . setEnd ( MI ) ; Finish ( MBB , State ) ; Modified = true ; } break ; case M68k :: MOVM32jm : Mask = MI -> getOperand ( 1 ) . getImm ( ) ; Reg = MI -> getOperand ( 0 ) . getReg ( ) ; Offset = 0 ; Modified |= ProcessMI ( MBB , MI , State , Mask , Offset , Reg , true ) ; break ; case M68k :: MOVM32pm : Mask = MI -> getOperand ( 2 ) . getImm ( ) ; Reg = MI -> getOperand ( 1 ) . getReg ( ) ; Offset = MI -> getOperand ( 0 ) . getImm ( ) ; Modified |= ProcessMI ( MBB , MI , State , Mask , Offset , Reg , true ) ; break ; case M68k :: MOVM32mj : Mask = MI -> getOperand ( 0 ) . getImm ( ) ; Reg = MI -> getOperand ( 1 ) . getReg ( ) ; Offset = 0 ; Modified |= ProcessMI ( MBB , MI , State , Mask , Offset , Reg , false ) ; break ; case M68k :: MOVM32mp : Mask = MI -> getOperand ( 0 ) . getImm ( ) ; Reg = MI -> getOperand ( 2 ) . getReg ( ) ; Offset = MI -> getOperand ( 1 ) . getImm ( ) ; Modified |= ProcessMI ( MBB , MI , State , Mask , Offset , Reg , false ) ; break ; } MI = NMI ; } if ( State . hasBase ( ) ) { State . setEnd ( MI ) ; Finish ( MBB , State ) ; } } return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> static machine_mode get_mode_wider_vector ( machine_mode o ) { machine_mode n = GET_MODE_NEXT_MODE ( o ) . require ( ) ; gcc_assert ( GET_MODE_NUNITS ( o ) == GET_MODE_NUNITS ( n ) * 2 ) ; gcc_assert ( GET_MODE_SIZE ( o ) == GET_MODE_SIZE ( n ) ) ; return n ; } </s>

Get a vector mode of the same size as the original but with elements twice as wide . This is only guaranteed to apply to integral vectors .


<s> bool MSP430TargetLowering :: isLegalICmpImmediate ( int64_t Immed ) const { if ( MSP430NoLegalImmediate ) return Immed >= - 32 && Immed < 32 ; return TargetLowering :: isLegalICmpImmediate ( Immed ) ; } </s>

Return true if the specified immediate is legal icmp immediate , that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register .


<s> unsigned X86FastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( DL , C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const auto * CI = dyn_cast < ConstantInt > ( C ) ) return X86MaterializeInt ( CI , VT ) ; else if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return X86MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return X86MaterializeGV ( GV , VT ) ; else if ( isa < UndefValue > ( C ) ) { unsigned Opc = 0 ; switch ( VT . SimpleTy ) { default : break ; case MVT :: f32 : if ( ! X86ScalarSSEf32 ) Opc = X86 :: LD_Fp032 ; break ; case MVT :: f64 : if ( ! X86ScalarSSEf64 ) Opc = X86 :: LD_Fp064 ; break ; case MVT :: f80 : Opc = X86 :: LD_Fp080 ; break ; } if ( Opc ) { Register ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; return ResultReg ; } } return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


"%qE redeclared with conflicting %qs attributes"

Implement TARGET_MERGE_DECL_ATTRIBUTES . We are just using this hook to add some additional error checking to the default behavior . GCC does not provide a target hook for merging the target options , and only correctly handles merging empty vs non-empty option data ; see merge_decls ( ) in c-decl.cc . So here we require either that at least one of the decls has empty target options , or that the target options/data be identical .


<s> std :: pair < unsigned , const TargetRegisterClass * > PPCTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'b' : if ( VT == MVT :: i64 && Subtarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RC_NOX0RegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRC_NOR0RegClass ) ; case 'r' : if ( VT == MVT :: i64 && Subtarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RCRegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRCRegClass ) ; case 'f' : if ( VT == MVT :: f32 || VT == MVT :: i32 ) return std :: make_pair ( 0U , & PPC :: F4RCRegClass ) ; if ( VT == MVT :: f64 || VT == MVT :: i64 ) return std :: make_pair ( 0U , & PPC :: F8RCRegClass ) ; break ; case 'v' : return std :: make_pair ( 0U , & PPC :: VRRCRegClass ) ; case 'y' : return std :: make_pair ( 0U , & PPC :: CRRCRegClass ) ; } } else if ( Constraint == "wc" ) { return std :: make_pair ( 0U , & PPC :: CRBITRCRegClass ) ; } else if ( Constraint == "wa" || Constraint == "wd" || Constraint == "wf" ) { return std :: make_pair ( 0U , & PPC :: VSRCRegClass ) ; } else if ( Constraint == "ws" ) { return std :: make_pair ( 0U , & PPC :: VSFRCRegClass ) ; } std :: pair < unsigned , const TargetRegisterClass * > R = TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; if ( R . first && VT == MVT :: i64 && Subtarget . isPPC64 ( ) && PPC :: GPRCRegClass . contains ( R . first ) ) { const TargetRegisterInfo * TRI = getTargetMachine ( ) . getSubtargetImpl ( ) -> getRegisterInfo ( ) ; return std :: make_pair ( TRI -> getMatchingSuperReg ( R . first , PPC :: sub_32 , & PPC :: G8RCRegClass ) , & PPC :: G8RCRegClass ) ; } return R ; } </s>

Given a physical register constraint ( e.g .


<s> void TeakAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const { unsigned Offset = Fixup . getOffset ( ) ; unsigned Kind = Fixup . getKind ( ) ; switch ( Kind ) { case Teak :: fixup_teak_call_imm18 : write16le ( & Data [ Offset ] , ( read16le ( & Data [ Offset ] ) & ~ 0x30 ) | ( ( ( Value >> 16 ) & 3 ) << 4 ) ) ; write16le ( & Data [ Offset + 2 ] , Value & 0xFFFF ) ; break ; case Teak :: fixup_teak_rel7 : write16le ( & Data [ Offset ] , ( read16le ( & Data [ Offset ] ) & ~ 0x7F0 ) | ( ( ( ( Value >> 1 ) - 1 ) & 0x7F ) << 4 ) ) ; break ; case Teak :: fixup_teak_ptr_imm16 : write16le ( & Data [ Offset + 2 ] , Value ) ; break ; case Teak :: fixup_teak_bkrep_reg : Value -- ; write16le ( & Data [ Offset ] , ( read16le ( & Data [ Offset ] ) & ~ 0x60 ) | ( ( ( Value >> 16 ) & 3 ) << 5 ) ) ; write16le ( & Data [ Offset + 2 ] , Value & 0xFFFF ) ; break ; case Teak :: fixup_teak_bkrep_r6 : Value -- ; write16le ( & Data [ Offset ] , ( read16le ( & Data [ Offset ] ) & ~ 3 ) | ( ( Value >> 16 ) & 3 ) ) ; write16le ( & Data [ Offset + 2 ] , Value & 0xFFFF ) ; break ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static tree c4x_gimplify_va_arg_expr ( tree valist , tree type , tree * pre_p ATTRIBUTE_UNUSED , tree * post_p ATTRIBUTE_UNUSED ) { tree t ; bool indirect ; indirect = pass_by_reference ( NULL , TYPE_MODE ( type ) , type , false ) ; if ( indirect ) type = build_pointer_type ( type ) ; t = build ( PREDECREMENT_EXPR , TREE_TYPE ( valist ) , valist , build_int_cst ( NULL_TREE , int_size_in_bytes ( type ) ) ) ; t = fold_convert ( build_pointer_type ( type ) , t ) ; t = build_va_arg_indirect_ref ( t ) ; if ( indirect ) t = build_va_arg_indirect_ref ( t ) ; return t ; } </s>

C [ 34 ] x arguments grow in weird ways ( downwards ) that the standard varargs stuff ca n't handle ..


<s> static void tilepro_setup_incoming_varargs ( cumulative_args_t cum , machine_mode mode , tree type , int * pretend_args , int no_rtl ) { CUMULATIVE_ARGS local_cum = * get_cumulative_args ( cum ) ; int first_reg ; targetm . calls . function_arg_advance ( pack_cumulative_args ( & local_cum ) , mode , type , true ) ; first_reg = local_cum ; if ( local_cum < TILEPRO_NUM_ARG_REGS ) { * pretend_args = UNITS_PER_WORD * ( TILEPRO_NUM_ARG_REGS - first_reg ) ; if ( ! no_rtl ) { alias_set_type set = get_varargs_alias_set ( ) ; rtx tmp = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , \ virtual_incoming_args_rtx , - STACK_POINTER_OFFSET - UNITS_PER_WORD * ( TILEPRO_NUM_ARG_REGS - first_reg ) ) ) ; MEM_NOTRAP_P ( tmp ) = 1 ; set_mem_alias_set ( tmp , set ) ; move_block_from_reg ( first_reg , tmp , TILEPRO_NUM_ARG_REGS - first_reg ) ; } } else * pretend_args = 0 ; } </s>


<s> PreservedAnalyses NVVMIntrRangePass :: run ( Function & F , FunctionAnalysisManager & AM ) { return runNVVMIntrRange ( F , SmVersion ) ? PreservedAnalyses :: none ( ) : PreservedAnalyses :: all ( ) ; } </s>

Run the analysis pass over a function and produce a dominator tree .


<s> static int h8300_os_task_function_p ( tree func ) { tree a ; if ( TREE_CODE ( func ) != FUNCTION_DECL ) return 0 ; a = lookup_attribute ( "OS_Task" , DECL_ATTRIBUTES ( func ) ) ; return a != NULL_TREE ; } </s>

Return nonzero if FUNC is an OS_Task function as specified by the `` OS_Task '' attribute .


<s> EVT ARMTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function & F = MF . getFunction ( ) ; if ( ( ! IsMemset || ZeroMemset ) && Subtarget -> hasNEON ( ) && ! F . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { bool Fast ; if ( Size >= 16 && ( memOpAlign ( SrcAlign , DstAlign , 16 ) || ( allowsMisalignedMemoryAccesses ( MVT :: v2f64 , 0 , 1 , & Fast ) && Fast ) ) ) { return MVT :: v2f64 ; } else if ( Size >= 8 && ( memOpAlign ( SrcAlign , DstAlign , 8 ) || ( allowsMisalignedMemoryAccesses ( MVT :: f64 , 0 , 1 , & Fast ) && Fast ) ) ) { return MVT :: f64 ; } } return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s>
ScheduleHazardRecognizer
*
PPCInstrInfo
::
CreateTargetPostRAHazardRecognizer
(
const
InstrItineraryData
*
II
,
const
ScheduleDAG
*
DAG
)
const
{
unsigned
Directive
=
TM
.
getSubtarget
<
PPCSubtarget
>
(
)
.
getDarwinDirective
(
)
;
if
(
Directive
!=
PPC
::
DIR_440
&&
Directive
!=
PPC
::
DIR_A2
&&
Directive
!=
PPC
::
DIR_E500mc
&&
Directive
!=
PPC
::
DIR_E5500
)
{
assert
(
TM
.
getInstrInfo
(
)
&&
"No InstrInfo?"
)
;
return
new
PPCHazardRecognizer970
(
TM
)
;
}
return
new
PPCScoreboardHazardRecognizer
(
II
,
DAG
)
;
}
</s>

Allocate and return a hazard recognizer to use for by non-scheduling passes .


<s> static void mips_rewrite_small_data_1 ( rtx * loc , enum mips_symbol_context context ) { subrtx_ptr_iterator :: array_type array ; FOR_EACH_SUBRTX_PTR ( iter , array , loc , ALL ) { rtx * loc = * iter ; if ( MEM_P ( * loc ) ) { mips_rewrite_small_data_1 ( & XEXP ( * loc , 0 ) , SYMBOL_CONTEXT_MEM ) ; iter . skip_subrtxes ( ) ; } else if ( mips_rewrite_small_data_p ( * loc , context ) ) { * loc = gen_rtx_LO_SUM ( Pmode , pic_offset_table_rtx , * loc ) ; iter . skip_subrtxes ( ) ; } else if ( GET_CODE ( * loc ) == LO_SUM ) iter . skip_subrtxes ( ) ; } } </s>

A for_each_rtx callback , used by mips_rewrite_small_data .


<s> void emitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) override { const MCInstrDesc & MID = MII . get ( Inst . getOpcode ( ) ) ; count ++ ; size += MID . getSize ( ) ; call |= MID . isCall ( ) ; } </s>

Targets should implement this to emit instructions .


<s> unsigned LanaiMachineFunctionInfo :: getGlobalBaseReg ( ) { if ( GlobalBaseReg ) return GlobalBaseReg ; return GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( & Lanai :: GPRRegClass ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> bool XCoreRegisterInfo :: needsFrameMoves ( const MachineFunction & MF ) { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineModuleInfo * MMI = MFI -> getMachineModuleInfo ( ) ; return ( MMI && MMI -> hasDebugInfo ( ) ) || ! MF . getFunction ( ) -> doesNotThrow ( ) || UnwindTablesMandatory ; } </s>


Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU R600 AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU


<s> static void microblaze_encode_section_info ( tree decl , rtx rtl , int first ) { default_encode_section_info ( decl , rtl , first ) ; } </s>

Encode info about sections into the RTL based on a symbol 's declaration . The default definition of this hook , default_encode_section_info in ` varasm.cc ' , sets a number of commonly-useful bits in SYMBOL_REF_FLAGS .


<s> static rtx s390_prologue_plus_offset ( rtx target , rtx reg , rtx offset , bool frame_related_p ) { rtx insn ; rtx orig_offset = offset ; gcc_assert ( REG_P ( target ) ) ; gcc_assert ( REG_P ( reg ) ) ; gcc_assert ( CONST_INT_P ( offset ) ) ; if ( offset == const0_rtx ) { insn = emit_move_insn ( target , reg ) ; } else if ( DISP_IN_RANGE ( INTVAL ( offset ) ) ) { insn = emit_move_insn ( target , gen_rtx_PLUS ( Pmode , reg , offset ) ) ; } else { if ( ! satisfies_constraint_K ( offset ) && ( ! TARGET_EXTIMM || ( ! satisfies_constraint_Op ( offset ) && ! satisfies_constraint_On ( offset ) ) ) ) offset = force_const_mem ( Pmode , offset ) ; if ( target != reg ) { insn = emit_move_insn ( target , reg ) ; RTX_FRAME_RELATED_P ( insn ) = frame_related_p ? 1 : 0 ; } insn = emit_insn ( gen_add2_insn ( target , offset ) ) ; if ( ! CONST_INT_P ( offset ) ) { annotate_constant_pool_refs ( & PATTERN ( insn ) ) ; if ( frame_related_p ) add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( target , gen_rtx_PLUS ( Pmode , target , orig_offset ) ) ) ; } } RTX_FRAME_RELATED_P ( insn ) = frame_related_p ? 1 : 0 ; if ( flag_stack_clash_protection && target == stack_pointer_rtx ) add_reg_note ( insn , REG_STACK_CHECK , const0_rtx ) ; return insn ; } </s>

Calculate TARGET = REG + OFFSET as s390_emit_prologue would do it . - push too big immediates to the literal pool and annotate the refs - emit frame related notes for stack pointer changes .


<s> bool ARMFrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { if ( STI . hasV8_1MMainlineOps ( ) && MF . getInfo < ARMFunctionInfo > ( ) -> isCmseNSEntryFunction ( ) ) { CSI . emplace_back ( ARM :: FPCXTNS ) ; CSI . back ( ) . setRestored ( false ) ; } const auto & AFI = * MF . getInfo < ARMFunctionInfo > ( ) ; if ( AFI . shouldSignReturnAddress ( ) ) { CSI . insert ( find_if ( CSI , [ = ] ( const auto & CS ) { Register Reg = CS . getReg ( ) ; return Reg == ARM :: R10 || Reg == ARM :: R11 || Reg == ARM :: R8 || Reg == ARM :: R9 || ARM :: DPRRegClass . contains ( Reg ) ; } ) , CalleeSavedInfo ( ARM :: R12 ) ) ; } return false ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


"variable %qD adjusted for OpenACC privatization level:"

"' adjusted for OpenACC privatization level: '%s'\n"


<s>
const
char
*
getPassName
(
)
const
override
{
return
"WebAssembly late peephole optimizer"
;
}
</s>

getPassName - Return a nice clean name for a pass .

WebAssembly
"WebAssembly late peephole optimizer"


<s> static bool can_use_cdx_ldstw ( int regno , int basereg , int offset ) { if ( CDX_REG_P ( regno ) && CDX_REG_P ( basereg ) && ( offset & 0x3 ) == 0 && 0 <= offset && offset < 0x40 ) return true ; else if ( basereg == SP_REGNO && offset >= 0 && offset < 0x80 && ( offset & 0x3 ) == 0 ) return true ; return false ; } </s>

Helper function : return true if a load/store using REGNO with address BASEREG and offset OFFSET meets the constraints for a 2-byte CDX ldw.n , stw.n , ldwsp.n , or stwsp.n instruction .


"SIInstrInfo::loadRegFromStackSlot - Do not know how to"

Load the specified register of the given register class from the specified stack frame index .


<s> static rtx altivec_expand_vec_ext_builtin ( tree exp , rtx target ) { machine_mode tmode , mode0 ; tree arg0 , arg1 ; rtx op0 ; rtx op1 ; arg0 = CALL_EXPR_ARG ( exp , 0 ) ; arg1 = CALL_EXPR_ARG ( exp , 1 ) ; op0 = expand_normal ( arg0 ) ; op1 = expand_normal ( arg1 ) ; if ( TREE_CODE ( arg1 ) == INTEGER_CST ) { unsigned HOST_WIDE_INT elt ; unsigned HOST_WIDE_INT size = TYPE_VECTOR_SUBPARTS ( TREE_TYPE ( arg0 ) ) ; unsigned int truncated_selector ; elt = TREE_INT_CST_LOW ( arg1 ) ; truncated_selector = elt % size ; op1 = GEN_INT ( truncated_selector ) ; } tmode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( arg0 ) ) ) ; mode0 = TYPE_MODE ( TREE_TYPE ( arg0 ) ) ; gcc_assert ( VECTOR_MODE_P ( mode0 ) ) ; op0 = force_reg ( mode0 , op0 ) ; if ( optimize || ! target || ! register_operand ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; rs6000_expand_vector_extract ( target , op0 , op1 ) ; return target ; } </s>


<s>
void
BT
::
run
(
)
{
reset
(
)
;
assert
(
FlowQ
.
empty
(
)
)
;
using
MachineFlowGraphTraits
=
GraphTraits
<
const
MachineFunction
*
>
;
const
MachineBasicBlock
*
Entry
=
MachineFlowGraphTraits
::
getEntryNode
(
&
MF
)
;
unsigned
MaxBN
=
0
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
assert
(
I
->
getNumber
(
)
>=
0
&&
"Disconnected block"
)
;
unsigned
BN
=
I
->
getNumber
(
)
;
if
(
BN
>
MaxBN
)
MaxBN
=
BN
;
}
BitVector
BlockScanned
(
MaxBN
+
1
)
;
int
EntryN
=
Entry
->
getNumber
(
)
;
FlowQ
.
push
(
CFGEdge
(
1
,
EntryN
)
)
;
while
(
!
FlowQ
.
empty
(
)
)
{
CFGEdge
Edge
=
FlowQ
.
front
(
)
;
FlowQ
.
pop
(
)
;
if
(
EdgeExec
.
count
(
Edge
)
)
continue
;
EdgeExec
.
insert
(
Edge
)
;
ReachedBB
.
insert
(
Edge
.
second
)
;
const
MachineBasicBlock
&
B
=
*
MF
.
getBlockNumbered
(
Edge
.
second
)
;
MachineBasicBlock
::
const_iterator
It
=
B
.
begin
(
)
,
End
=
B
.
end
(
)
;
while
(
It
!=
End
&&
It
->
isPHI
(
)
)
{
const
MachineInstr
&
PI
=
*
It
++
;
InstrExec
.
insert
(
&
PI
)
;
visitPHI
(
PI
)
;
}
if
(
BlockScanned
[
Edge
.
second
]
)
continue
;
BlockScanned
[
Edge
.
second
]
=
true
;
while
(
It
!=
End
&&
!
It
->
isBranch
(
)
)
{
const
MachineInstr
&
MI
=
*
It
++
;
InstrExec
.
insert
(
&
MI
)
;
visitNonBranch
(
MI
)
;
}
if
(
It
==
End
)
{
MachineFunction
::
const_iterator
BIt
=
B
.
getIterator
(
)
;
MachineFunction
::
const_iterator
Next
=
std
::
next
(
BIt
)
;
if
(
Next
!=
MF
.
end
(
)
&&
B
.
isSuccessor
(
&
*
Next
)
)
{
int
ThisN
=
B
.
getNumber
(
)
;
int
NextN
=
Next
->
getNumber
(
)
;
FlowQ
.
push
(
CFGEdge
(
ThisN
,
NextN
)
)
;
}
}
else
{
visitBranchesFrom
(
*
It
)
;
}
}
if
(
Trace
)
print_cells
(
dbgs
(
)
<<
"Cells after propagation:\n"
)
;
}
</s>


<s> rtx aarch64_ptrue_all ( unsigned int elt_size ) { rtx_vector_builder builder ( VNx16BImode , elt_size , 1 ) ; builder . quick_push ( const1_rtx ) ; for ( unsigned int i = 1 ; i < elt_size ; ++ i ) builder . quick_push ( const0_rtx ) ; return builder . build ( ) ; } </s>

Return a VNx16BImode constant in which every sequence of ELT_SIZE bits has the lowest bit set and the upper bits clear . This is the VNx16BImode equivalent of a PTRUE for controlling elements of ELT_SIZE bytes . However , because the constant is VNx16BImode , all bits are significant , even the upper zeros .


<s> TargetTransformInfo WebAssemblyTargetMachine :: getTargetTransformInfo ( const Function & F ) { return TargetTransformInfo ( WebAssemblyTTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> bool SIInstrInfo :: isReallyTriviallyReMaterializable ( const MachineInstr & MI , AAResults * AA ) const { switch ( MI . getOpcode ( ) ) { case AMDGPU :: V_MOV_B32_e32 : case AMDGPU :: V_MOV_B32_e64 : case AMDGPU :: V_MOV_B64_PSEUDO : case AMDGPU :: V_ACCVGPR_READ_B32_e64 : case AMDGPU :: V_ACCVGPR_WRITE_B32_e64 : assert ( MI . getDesc ( ) . getNumOperands ( ) == 2 ) ; assert ( MI . getDesc ( ) . getNumImplicitDefs ( ) == 0 ) ; assert ( MI . getDesc ( ) . getNumImplicitUses ( ) == 1 ) ; return MI . getNumOperands ( ) == 3 ; default : return false ; } } </s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> bool fma_node :: root_p ( ) { return this -> m_root == this ; } </s>


"Some operands reg class are incompatible!"

optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare ; remove Compare if possible .


<s> const uint16_t * NVPTXRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { 0 } ; return CalleeSavedRegs ; } </s>


<s> bool ARMBaseInstrInfo :: shouldSink ( const MachineInstr & MI ) const { if ( isPredicated ( MI ) ) return true ; MachineBasicBlock :: const_iterator Next = & MI ; ++ Next ; Register SrcReg , SrcReg2 ; int64_t CmpMask , CmpValue ; bool IsThumb1 ; if ( Next != MI . getParent ( ) -> end ( ) && analyzeCompare ( * Next , SrcReg , SrcReg2 , CmpMask , CmpValue ) && isRedundantFlagInstr ( & * Next , SrcReg , SrcReg2 , CmpValue , & MI , IsThumb1 ) ) return false ; return true ; } </s>

Return true if the instruction should be sunk by MachineSink .


<s> RegisterAggr & RegisterAggr :: insert ( RegisterRef RR ) { if ( PhysicalRegisterInfo :: isRegMaskId ( RR . Reg ) ) { const uint32_t * MB = PRI . getRegMaskBits ( RR . Reg ) ; for ( unsigned i = 1 , e = PRI . getTRI ( ) . getNumRegs ( ) ; i != e ; ++ i ) { if ( MB [ i / 32 ] & ( 1u << ( i % 32 ) ) ) continue ; insert ( RegisterRef ( i , LaneBitmask :: getAll ( ) ) ) ; } return * this ; } RegisterRef NR = PRI . normalize ( RR ) ; auto F = Masks . find ( NR . Reg ) ; if ( F == Masks . end ( ) ) Masks . insert ( { NR . Reg , NR . Mask } ) ; else F -> second |= NR . Mask ; const TargetRegisterInfo & TRI = PRI . getTRI ( ) ; for ( MCRegUnitIterator U ( RR . Reg , & TRI ) ; U . isValid ( ) ; ++ U ) { MCRegUnitRootIterator R ( * U , & TRI ) ; ++ R ; if ( ! R . isValid ( ) ) continue ; ExpAliasUnits . set ( * U ) ; CheckUnits = true ; } return * this ; } </s>

insert - Append entry to the vector if it does n't already exist .


"%qE attribute only applies to variables"

"address region attributes not allowed with auto storage class"

"address region attributes on pointed-to types ignored"


<s> static bool isSchedulingBoundary ( const MachineInstr * MI , const MachineFunction & MF ) { if ( MI -> isLabel ( ) || MI -> isInlineAsm ( ) ) return true ; if ( MI -> getOpcode ( ) == TMS320C64X :: call_return_label ) return true ; const TargetLowering & TLI = * MF . getTarget ( ) . getTargetLowering ( ) ; if ( MI -> modifiesRegister ( TLI . getStackPointerRegisterToSaveRestore ( ) ) ) return true ; switch ( MI -> getOpcode ( ) ) { case TMS320C64X :: prolog : case TMS320C64X :: epilog : return true ; } return false ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> bool HexagonPacketizerList :: updateOffset ( SUnit * SUI , SUnit * SUJ ) { assert ( SUI -> getInstr ( ) && SUJ -> getInstr ( ) ) ; MachineInstr & MI = * SUI -> getInstr ( ) ; MachineInstr & MJ = * SUJ -> getInstr ( ) ; unsigned BPI , OPI ; if ( ! HII -> getBaseAndOffsetPosition ( MI , BPI , OPI ) ) return false ; unsigned BPJ , OPJ ; if ( ! HII -> getBaseAndOffsetPosition ( MJ , BPJ , OPJ ) ) return false ; Register Reg = MI . getOperand ( BPI ) . getReg ( ) ; if ( Reg != MJ . getOperand ( BPJ ) . getReg ( ) ) return false ; for ( const auto & PI : SUI -> Preds ) if ( PI . getKind ( ) != SDep :: Anti && ( PI . getKind ( ) != SDep :: Data || PI . getReg ( ) != Reg ) ) return false ; int Incr ; if ( ! HII -> getIncrementValue ( MJ , Incr ) ) return false ; int64_t Offset = MI . getOperand ( OPI ) . getImm ( ) ; if ( ! HII -> isValidOffset ( MI . getOpcode ( ) , Offset + Incr , HRI ) ) return false ; MI . getOperand ( OPI ) . setImm ( Offset + Incr ) ; ChangedOffset = Offset ; return true ; } </s>

Return true if we can update the offset in MI so that MI and MJ can be packetized together .


<s> static LLT getPow2VectorType ( LLT Ty ) { unsigned NElts = Ty . getNumElements ( ) ; unsigned Pow2NElts = 1 << Log2_32_Ceil ( NElts ) ; return Ty . changeElementCount ( ElementCount :: getFixed ( Pow2NElts ) ) ; } </s>

Widens the length of the given vector MVT up to the nearest power of 2 and returns that type .


<s> void avr_cpu_cpp_builtins ( struct cpp_reader * pfile ) { builtin_define_std ( "AVR" ) ; if ( avr_arch -> macro ) cpp_define_formatted ( pfile , "__AVR_ARCH__=%s" , avr_arch -> macro ) ; if ( AVR_HAVE_RAMPD ) cpp_define ( pfile , "__AVR_HAVE_RAMPD__" ) ; if ( AVR_HAVE_RAMPX ) cpp_define ( pfile , "__AVR_HAVE_RAMPX__" ) ; if ( AVR_HAVE_RAMPY ) cpp_define ( pfile , "__AVR_HAVE_RAMPY__" ) ; if ( AVR_HAVE_RAMPZ ) cpp_define ( pfile , "__AVR_HAVE_RAMPZ__" ) ; if ( AVR_HAVE_ELPM ) cpp_define ( pfile , "__AVR_HAVE_ELPM__" ) ; if ( AVR_HAVE_ELPMX ) cpp_define ( pfile , "__AVR_HAVE_ELPMX__" ) ; if ( AVR_HAVE_MOVW ) cpp_define ( pfile , "__AVR_HAVE_MOVW__" ) ; if ( AVR_HAVE_LPMX ) cpp_define ( pfile , "__AVR_HAVE_LPMX__" ) ; if ( avr_arch -> asm_only ) cpp_define ( pfile , "__AVR_ASM_ONLY__" ) ; if ( AVR_HAVE_MUL ) { cpp_define ( pfile , "__AVR_ENHANCED__" ) ; cpp_define ( pfile , "__AVR_HAVE_MUL__" ) ; } if ( avr_arch -> have_jmp_call ) { cpp_define ( pfile , "__AVR_MEGA__" ) ; cpp_define ( pfile , "__AVR_HAVE_JMP_CALL__" ) ; } if ( AVR_XMEGA ) cpp_define ( pfile , "__AVR_XMEGA__" ) ; if ( AVR_TINY ) { cpp_define ( pfile , "__AVR_TINY__" ) ; cpp_define_formatted ( pfile , "__AVR_TINY_PM_BASE_ADDRESS__=0x%x" , AVR_TINY_PM_OFFSET ) ; } if ( AVR_HAVE_EIJMP_EICALL ) { cpp_define ( pfile , "__AVR_HAVE_EIJMP_EICALL__" ) ; cpp_define ( pfile , "__AVR_3_BYTE_PC__" ) ; } else { cpp_define ( pfile , "__AVR_2_BYTE_PC__" ) ; } if ( AVR_HAVE_8BIT_SP ) cpp_define ( pfile , "__AVR_HAVE_8BIT_SP__" ) ; else cpp_define ( pfile , "__AVR_HAVE_16BIT_SP__" ) ; if ( AVR_HAVE_SPH ) cpp_define ( pfile , "__AVR_HAVE_SPH__" ) ; else cpp_define ( pfile , "__AVR_SP8__" ) ; if ( TARGET_NO_INTERRUPTS ) cpp_define ( pfile , "__NO_INTERRUPTS__" ) ; if ( TARGET_SKIP_BUG ) { cpp_define ( pfile , "__AVR_ERRATA_SKIP__" ) ; if ( AVR_HAVE_JMP_CALL ) cpp_define ( pfile , "__AVR_ERRATA_SKIP_JMP_CALL__" ) ; } if ( TARGET_RMW ) cpp_define ( pfile , "__AVR_ISA_RMW__" ) ; cpp_define_formatted ( pfile , "__AVR_SFR_OFFSET__=0x%x" , avr_arch -> sfr_offset ) ; cpp_define ( pfile , "__WITH_AVRLIBC__" ) ; if ( lang_GNU_C ( ) ) { for ( int i = 0 ; i < ADDR_SPACE_COUNT ; i ++ ) if ( ! ADDR_SPACE_GENERIC_P ( i ) && avr_addr_space_supported_p ( ( addr_space_t ) i ) ) { const char * name = avr_addrspace [ i ] . name ; char * Name = ( char * ) alloca ( 1 + strlen ( name ) ) ; cpp_define ( pfile , avr_toupper ( Name , name ) ) ; } } cpp_define ( pfile , "__BUILTIN_AVR_" # NAME ) ; cpp_define_formatted ( pfile , "__INT24_MAX__=8388607%s" , INT_TYPE_SIZE == 8 ? "LL" : "L" ) ; cpp_define ( pfile , "__INT24_MIN__=(-__INT24_MAX__-1)" ) ; cpp_define_formatted ( pfile , "__UINT24_MAX__=16777215%s" , INT_TYPE_SIZE == 8 ? "ULL" : "UL" ) ; } </s>

Worker function for TARGET_CPU_CPP_BUILTINS .


<s> static sbitmap riscv_get_separate_components ( void ) { HOST_WIDE_INT offset ; sbitmap components = sbitmap_alloc ( FIRST_PSEUDO_REGISTER ) ; bitmap_clear ( components ) ; if ( riscv_use_save_libcall ( & cfun -> machine -> frame ) || cfun -> machine -> interrupt_handler_p || ! cfun -> machine -> frame . gp_sp_offset . is_constant ( ) ) return components ; offset = cfun -> machine -> frame . gp_sp_offset . to_constant ( ) ; for ( unsigned int regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . mask , regno - GP_REG_FIRST ) ) { if ( SMALL_OPERAND ( offset ) ) bitmap_set_bit ( components , regno ) ; offset -= UNITS_PER_WORD ; } offset = cfun -> machine -> frame . fp_sp_offset . to_constant ( ) ; for ( unsigned int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . fmask , regno - FP_REG_FIRST ) ) { machine_mode mode = TARGET_DOUBLE_FLOAT ? DFmode : SFmode ; if ( SMALL_OPERAND ( offset ) ) bitmap_set_bit ( components , regno ) ; offset -= GET_MODE_SIZE ( mode ) . to_constant ( ) ; } if ( frame_pointer_needed ) bitmap_clear_bit ( components , HARD_FRAME_POINTER_REGNUM ) ; bitmap_clear_bit ( components , RETURN_ADDR_REGNUM ) ; return components ; } </s>


<s> static bool m32r_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { cumulative_args_t dummy = pack_cumulative_args ( NULL ) ; return m32r_pass_by_reference ( dummy , TYPE_MODE ( type ) , type , false ) ; } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


<s> bool P2AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> static rtx riscv_strip_unspec_address ( rtx op ) { rtx base , offset ; split_const ( op , & base , & offset ) ; if ( UNSPEC_ADDRESS_P ( base ) ) op = plus_constant ( Pmode , UNSPEC_ADDRESS ( base ) , INTVAL ( offset ) ) ; return op ; } </s>

If OP is an UNSPEC address , return the address to which it refers , otherwise return OP itself .


<s> static void emit_unlikely_jump ( rtx insn ) { rtx_insn * jump = emit_jump_insn ( insn ) ; add_reg_br_prob_note ( jump , profile_probability :: very_unlikely ( ) ) ; } </s>

Mark the previous jump instruction as unlikely .


<s>
bool
dump_insn_list
(
const
rtx
&
t
,
const
insn_info_list_t
&
insn_info
,
void
*
unused
ATTRIBUTE_UNUSED
)
{
gcc_assert
(
dump_file
)
;
fprintf
(
dump_file
,
"Tag 0x%lx ::\n"
,
INTVAL
(
t
)
)
;
for
(
unsigned
i
=
0
;
i
<
insn_info
.
length
(
)
;
i
++
)
dump_insn_slim
(
dump_file
,
insn_info
[
i
]
->
insn
)
;
fprintf
(
dump_file
,
"\n"
)
;
return
true
;
}
</s>

Callback invoked for each name-value pair ( T , INSN_INFO ) to dump the insn list INSN_INFO for tag T .


<s> static const char * cond_string ( enum rtx_code code ) { switch ( code ) { case NE : return "ne" ; case EQ : return "eq" ; case GE : return "ge" ; case GT : return "gt" ; case LE : return "le" ; case LT : return "lt" ; case GEU : return "hs" ; case GTU : return "hi" ; case LEU : return "ls" ; case LTU : return "lo" ; default : gcc_unreachable ( ) ; } } </s>

Return assembly language string which identifies a comparison type .


<s> void ECLairInstPrinter :: printRegName ( raw_ostream & O , unsigned RegNo ) const { O << getRegisterName ( RegNo ) ; } </s>


<s> void GCNPassConfig :: addPreEmitPass ( ) { addPass ( createSIMemoryLegalizerPass ( ) ) ; addPass ( createSIInsertWaitcntsPass ( ) ) ; addPass ( createSIShrinkInstructionsPass ( ) ) ; addPass ( createSIModeRegisterPass ( ) ) ; addPass ( & PostRAHazardRecognizerID ) ; addPass ( & SIInsertSkipsPassID ) ; addPass ( createSIDebuggerInsertNopsPass ( ) ) ; addPass ( & BranchRelaxationPassID ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
RISCV
::
NumTargetFixupKinds
]
=
{
{
"fixup_riscv_hi20"
,
12
,
20
,
0
}
,
{
"fixup_riscv_lo12_i"
,
20
,
12
,
0
}
,
{
"fixup_riscv_lo12_s"
,
0
,
32
,
0
}
,
{
"fixup_riscv_pcrel_hi20"
,
12
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_riscv_jal"
,
12
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_riscv_branch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_riscv_rvc_jump"
,
2
,
11
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_riscv_rvc_branch"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> int const_ok_for_arm ( HOST_WIDE_INT i ) { int lowbit ; if ( ( i & ~ ( unsigned HOST_WIDE_INT ) 0xffffffff ) != 0 && ( ( i & ~ ( unsigned HOST_WIDE_INT ) 0xffffffff ) != ( ( ~ ( unsigned HOST_WIDE_INT ) 0 ) & ~ ( unsigned HOST_WIDE_INT ) 0xffffffff ) ) ) return FALSE ; i &= ( unsigned HOST_WIDE_INT ) 0xffffffff ; if ( ( i & ~ ( unsigned HOST_WIDE_INT ) 0xff ) == 0 ) return TRUE ; lowbit = ffs ( ( int ) i ) - 1 ; if ( TARGET_ARM ) lowbit &= ~ 1 ; if ( ( i & ~ ( ( ( unsigned HOST_WIDE_INT ) 0xff ) << lowbit ) ) == 0 ) return TRUE ; if ( TARGET_ARM ) { if ( lowbit <= 4 && ( ( i & ~ 0xc000003f ) == 0 || ( i & ~ 0xf000000f ) == 0 || ( i & ~ 0xfc000003 ) == 0 ) ) return TRUE ; } else if ( TARGET_THUMB2 ) { HOST_WIDE_INT v ; v = i & 0xff ; v |= v << 16 ; if ( i == v || i == ( v | ( v << 8 ) ) ) return TRUE ; v = i & 0xff00 ; v |= v << 16 ; if ( i == v ) return TRUE ; } else if ( TARGET_HAVE_MOVT ) { if ( i > 0xffff ) return FALSE ; else return TRUE ; } return FALSE ; } </s>

Return TRUE if int I is a valid immediate ARM constant .


<s> const MipsInstrInfo * getInstrInfo ( ) const override { return InstrInfo . get ( ) ; } </s>


<s>
const
char
*
getPassName
(
)
const
{
return
"TMS320C64X Instruction Selection"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static rtx hwloop_pattern_reg ( rtx_insn * insn ) { rtx reg ; if ( ! JUMP_P ( insn ) || recog_memoized ( insn ) != CODE_FOR_loop_end ) return NULL_RTX ; reg = SET_DEST ( XVECEXP ( PATTERN ( insn ) , 0 , 1 ) ) ; if ( ! REG_P ( reg ) ) return NULL_RTX ; return reg ; } </s>

A callback for the hw-doloop pass . This function examines INSN ; if it is a doloop_end pattern we recognize , return the reg rtx for the loop counter . Otherwise , return NULL_RTX .


<s>
const
TargetRegisterClass
*
ARMBaseRegisterInfo
::
getMatchingSuperRegClass
(
const
TargetRegisterClass
*
A
,
const
TargetRegisterClass
*
B
,
unsigned
SubIdx
)
const
{
switch
(
SubIdx
)
{
default
:
return
0
;
case
1
:
case
2
:
case
3
:
case
4
:
if
(
A
->
getSize
(
)
==
8
)
{
if
(
B
==
&
ARM
::
SPR_8RegClass
)
return
&
ARM
::
DPR_8RegClass
;
assert
(
B
==
&
ARM
::
SPRRegClass
&&
"Expecting SPR register class!"
)
;
if
(
A
==
&
ARM
::
DPR_8RegClass
)
return
A
;
return
&
ARM
::
DPR_VFP2RegClass
;
}
assert
(
A
->
getSize
(
)
==
16
&&
"Expecting a Q register class!"
)
;
if
(
B
==
&
ARM
::
SPR_8RegClass
)
return
&
ARM
::
QPR_8RegClass
;
return
&
ARM
::
QPR_VFP2RegClass
;
case
5
:
case
6
:
if
(
B
==
&
ARM
::
DPR_VFP2RegClass
)
return
&
ARM
::
QPR_VFP2RegClass
;
if
(
B
==
&
ARM
::
DPR_8RegClass
)
return
&
ARM
::
QPR_8RegClass
;
return
A
;
}
return
0
;
}
</s>

getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register in it has a sub-register of the specified sub-register index which is in the specified register class B .


<s> static inline SlotWithTag getEmptyKey ( ) { return { - 2 , - 2 ; } </s>

Empty key : no key should be generated that has no DILocalVariable .


<s> rtx rs6000_longcall_ref ( rtx call_ref ) { const char * call_name ; tree node ; if ( GET_CODE ( call_ref ) != SYMBOL_REF ) return call_ref ; call_name = XSTR ( call_ref , 0 ) ; if ( * call_name == '.' ) { while ( * call_name == '.' ) call_name ++ ; node = get_identifier ( call_name ) ; call_ref = gen_rtx_SYMBOL_REF ( VOIDmode , IDENTIFIER_POINTER ( node ) ) ; } return force_reg ( Pmode , call_ref ) ; } </s>

Return a reference suitable for calling a function with the longcall attribute .


<s> SDValue MBlazeTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_MBlaze ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> TargetPassConfig * NyuziTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new NyuziPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> static bool aarch64_decl_is_long_call_p ( const_tree decl ATTRIBUTE_UNUSED ) { return false ; } </s>

Return true if calls to DECL should be treated as long-calls ( ie called via a register ) .


<s> void ARMRegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned DestReg , int Val , unsigned Pred , unsigned PredReg , const TargetInstrInfo * TII , bool isThumb , DebugLoc dl ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; Constant * C = ConstantInt :: get ( Type :: Int32Ty , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; if ( isThumb ) BuildMI ( MBB , MBBI , dl , TII -> get ( ARM :: tLDRcp ) , DestReg ) . addConstantPoolIndex ( Idx ) ; else BuildMI ( MBB , MBBI , dl , TII -> get ( ARM :: LDRcp ) , DestReg ) . addConstantPoolIndex ( Idx ) . addReg ( 0 ) . addImm ( 0 ) . addImm ( Pred ) . addReg ( PredReg ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


"-misched-topdown incompatible with -misched-bottomup"

Initialize the strategy after building the DAG for a new region .


<s> static void ix86_test_loading_full_dump ( ) { rtl_dump_test t ( SELFTEST_LOCATION , locate_file ( "x86_64/times-two.rtl" ) ) ; ASSERT_STREQ ( "times_two" , IDENTIFIER_POINTER ( DECL_NAME ( cfun -> decl ) ) ) ; rtx_insn * insn_1 = get_insn_by_uid ( 1 ) ; ASSERT_EQ ( NOTE , GET_CODE ( insn_1 ) ) ; rtx_insn * insn_7 = get_insn_by_uid ( 7 ) ; ASSERT_EQ ( INSN , GET_CODE ( insn_7 ) ) ; ASSERT_EQ ( PARALLEL , GET_CODE ( PATTERN ( insn_7 ) ) ) ; rtx_insn * insn_15 = get_insn_by_uid ( 15 ) ; ASSERT_EQ ( INSN , GET_CODE ( insn_15 ) ) ; ASSERT_EQ ( USE , GET_CODE ( PATTERN ( insn_15 ) ) ) ; ASSERT_EQ ( REG , GET_CODE ( crtl -> return_rtx ) ) ; ASSERT_EQ ( 0 , REGNO ( crtl -> return_rtx ) ) ; ASSERT_EQ ( SImode , GET_MODE ( crtl -> return_rtx ) ) ; } </s>

Verify that the RTL loader copes a dump from print_rtx_function . This test is target-specific since the dump contains target-specific hard reg names .


<s> static rtx single_set_pattern ( rtx pattern ) { rtx set ; int i ; if ( GET_CODE ( pattern ) == COND_EXEC ) pattern = COND_EXEC_CODE ( pattern ) ; if ( GET_CODE ( pattern ) == SET ) return pattern ; else if ( GET_CODE ( pattern ) == PARALLEL ) { for ( i = 0 , set = 0 ; i < XVECLEN ( pattern , 0 ) ; i ++ ) { rtx sub = XVECEXP ( pattern , 0 , i ) ; switch ( GET_CODE ( sub ) ) { case USE : case CLOBBER : break ; case SET : if ( set ) return 0 ; else set = sub ; break ; default : return 0 ; } } return set ; } return 0 ; } </s>

Given a PATTERN , return a SET expression if this PATTERN has only a single SET , possibly conditionally executed . It may also have CLOBBERs , USEs .


<s> static void aarch64_emit_probe_stack_range ( HOST_WIDE_INT first , HOST_WIDE_INT size ) { rtx reg1 = gen_rtx_REG ( ptr_mode , PROBE_STACK_FIRST_REG ) ; gcc_assert ( ( first % ARITH_FACTOR ) == 0 ) ; if ( size <= PROBE_INTERVAL ) { const HOST_WIDE_INT base = ROUND_UP ( size , ARITH_FACTOR ) ; emit_set_insn ( reg1 , plus_constant ( ptr_mode , stack_pointer_rtx , - ( first + base ) ) ) ; emit_stack_probe ( plus_constant ( ptr_mode , reg1 , base - size ) ) ; } else if ( size <= 4 * PROBE_INTERVAL ) { HOST_WIDE_INT i , rem ; emit_set_insn ( reg1 , plus_constant ( ptr_mode , stack_pointer_rtx , - ( first + PROBE_INTERVAL ) ) ) ; emit_stack_probe ( reg1 ) ; for ( i = 2 * PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) { emit_set_insn ( reg1 , plus_constant ( ptr_mode , reg1 , - PROBE_INTERVAL ) ) ; emit_stack_probe ( reg1 ) ; } rem = size - ( i - PROBE_INTERVAL ) ; if ( rem > 256 ) { const HOST_WIDE_INT base = ROUND_UP ( rem , ARITH_FACTOR ) ; emit_set_insn ( reg1 , plus_constant ( ptr_mode , reg1 , - base ) ) ; emit_stack_probe ( plus_constant ( ptr_mode , reg1 , base - rem ) ) ; } else emit_stack_probe ( plus_constant ( ptr_mode , reg1 , - rem ) ) ; } else { rtx reg2 = gen_rtx_REG ( ptr_mode , PROBE_STACK_SECOND_REG ) ; HOST_WIDE_INT rounded_size = size & - PROBE_INTERVAL ; emit_set_insn ( reg1 , plus_constant ( ptr_mode , stack_pointer_rtx , - first ) ) ; emit_set_insn ( reg2 , plus_constant ( ptr_mode , stack_pointer_rtx , - ( first + rounded_size ) ) ) ; if ( ptr_mode == DImode ) emit_insn ( gen_probe_stack_range_di ( reg1 , reg1 , reg2 ) ) ; else emit_insn ( gen_probe_stack_range_si ( reg1 , reg1 , reg2 ) ) ; if ( size != rounded_size ) { HOST_WIDE_INT rem = size - rounded_size ; if ( rem > 256 ) { const HOST_WIDE_INT base = ROUND_UP ( rem , ARITH_FACTOR ) ; emit_set_insn ( reg2 , plus_constant ( ptr_mode , reg2 , - base ) ) ; emit_stack_probe ( plus_constant ( ptr_mode , reg2 , base - rem ) ) ; } else emit_stack_probe ( plus_constant ( ptr_mode , reg2 , - rem ) ) ; } } emit_insn ( gen_blockage ( ) ) ; } </s>

Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE , inclusive . These are offsets from the current stack pointer .


<s> static rtx s390_execute_target ( rtx insn ) { rtx pattern = PATTERN ( insn ) ; gcc_assert ( s390_execute_label ( insn ) ) ; if ( XVECLEN ( pattern , 0 ) == 2 ) { pattern = copy_rtx ( XVECEXP ( pattern , 0 , 1 ) ) ; } else { rtvec vec = rtvec_alloc ( XVECLEN ( pattern , 0 ) - 1 ) ; int i ; for ( i = 0 ; i < XVECLEN ( pattern , 0 ) - 1 ; i ++ ) RTVEC_ELT ( vec , i ) = copy_rtx ( XVECEXP ( pattern , 0 , i + 1 ) ) ; pattern = gen_rtx_PARALLEL ( VOIDmode , vec ) ; } return pattern ; } </s>

For an execute INSN , extract the execute target template .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> bool ARMTTIImpl :: isLegalMaskedLoad ( Type * DataTy , MaybeAlign Alignment ) { if ( ! EnableMaskedLoadStores || ! ST -> hasMVEIntegerOps ( ) ) return false ; if ( auto * VecTy = dyn_cast < VectorType > ( DataTy ) ) { if ( VecTy -> getNumElements ( ) == 2 ) return false ; unsigned VecWidth = DataTy -> getPrimitiveSizeInBits ( ) ; if ( VecWidth != 128 && VecTy -> getElementType ( ) -> isFloatingPointTy ( ) ) return false ; } unsigned EltWidth = DataTy -> getScalarSizeInBits ( ) ; return ( EltWidth == 32 && ( ! Alignment || Alignment >= 4 ) ) || ( EltWidth == 16 && ( ! Alignment || Alignment >= 2 ) ) || ( EltWidth == 8 ) ; } </s>

Return true if the target supports masked load .


<s> int ix86_expand_strlen ( rtx out , rtx src , rtx eoschar , rtx align ) { rtx addr , scratch1 , scratch2 , scratch3 , scratch4 ; if ( TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1 && ! TARGET_INLINE_ALL_STRINGOPS && ! optimize_size && ( GET_CODE ( align ) != CONST_INT || INTVAL ( align ) < 4 ) ) return 0 ; addr = force_reg ( Pmode , XEXP ( src , 0 ) ) ; scratch1 = gen_reg_rtx ( Pmode ) ; if ( TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1 && ! optimize_size ) { emit_move_insn ( out , addr ) ; ix86_expand_strlensi_unroll_1 ( out , src , align ) ; if ( TARGET_64BIT ) emit_insn ( gen_subdi3 ( out , out , addr ) ) ; else emit_insn ( gen_subsi3 ( out , out , addr ) ) ; } else { rtx unspec ; scratch2 = gen_reg_rtx ( Pmode ) ; scratch3 = gen_reg_rtx ( Pmode ) ; scratch4 = force_reg ( Pmode , constm1_rtx ) ; emit_move_insn ( scratch3 , addr ) ; eoschar = force_reg ( QImode , eoschar ) ; emit_insn ( gen_cld ( ) ) ; src = replace_equiv_address_nv ( src , scratch3 ) ; unspec = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 4 , src , eoschar , align , scratch4 ) , UNSPEC_SCAS ) ; emit_insn ( gen_strlenqi_1 ( scratch1 , scratch3 , unspec ) ) ; if ( TARGET_64BIT ) { emit_insn ( gen_one_cmpldi2 ( scratch2 , scratch1 ) ) ; emit_insn ( gen_adddi3 ( out , scratch2 , constm1_rtx ) ) ; } else { emit_insn ( gen_one_cmplsi2 ( scratch2 , scratch1 ) ) ; emit_insn ( gen_addsi3 ( out , scratch2 , constm1_rtx ) ) ; } } return 1 ; } </s>


<s> void MipsPassConfig :: addPreRegBankSelect ( ) { bool IsOptNone = getOptLevel ( ) == CodeGenOpt :: None ; addPass ( createMipsPostLegalizeCombiner ( IsOptNone ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before the register bank selection .


"WebAssembly doesn't support language-specific or target-specific "

"WebAssembly doesn't support patch point yet"

"WebAssembly doesn't support tail call yet"

"WebAssembly doesn't support more than 1 returned value yet"

"WebAssembly doesn't support varargs yet"

This hook must be implemented to lower calls into the specified DAG .


<s> static bool tilegx_emit_setcc_internal ( rtx res , enum rtx_code code , rtx op0 , rtx op1 , machine_mode cmp_mode ) { rtx tmp ; bool swap = false ; if ( cmp_mode == SFmode || cmp_mode == DFmode ) return tilegx_emit_fp_setcc ( res , code , cmp_mode , op0 , op1 ) ; switch ( code ) { case EQ : case NE : case LE : case LT : case LEU : case LTU : break ; case GE : case GT : case GEU : case GTU : swap = true ; break ; default : gcc_unreachable ( ) ; } if ( swap ) { code = swap_condition ( code ) ; tmp = op0 , op0 = op1 , op1 = tmp ; } if ( ! reg_or_0_operand ( op0 , cmp_mode ) ) op0 = force_reg ( cmp_mode , op0 ) ; if ( ! CONST_INT_P ( op1 ) && ! register_operand ( op1 , cmp_mode ) ) op1 = force_reg ( cmp_mode , op1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , res , gen_rtx_fmt_ee ( code , DImode , op0 , op1 ) ) ) ; return true ; } </s>

Certain simplifications can be done to make invalid setcc operations valid . Return the final comparison , or NULL if we ca n't work .


<s> static int get_epiphany_condition_code ( rtx comparison ) { switch ( GET_MODE ( XEXP ( comparison , 0 ) ) ) { case CCmode : switch ( GET_CODE ( comparison ) ) { case EQ : return 0 ; case NE : return 1 ; case LTU : return 2 ; case GEU : return 3 ; case GT : return 4 ; case LE : return 5 ; case GE : return 6 ; case LT : return 7 ; case GTU : return 8 ; case LEU : return 9 ; default : gcc_unreachable ( ) ; } case CC_N_NEmode : switch ( GET_CODE ( comparison ) ) { case EQ : return 6 ; case NE : return 7 ; default : gcc_unreachable ( ) ; } case CC_C_LTUmode : switch ( GET_CODE ( comparison ) ) { case GEU : return 2 ; case LTU : return 3 ; default : gcc_unreachable ( ) ; } case CC_C_GTUmode : switch ( GET_CODE ( comparison ) ) { case LEU : return 3 ; case GTU : return 2 ; default : gcc_unreachable ( ) ; } case CC_FPmode : switch ( GET_CODE ( comparison ) ) { case EQ : return 10 ; case NE : return 11 ; case LT : return 12 ; case LE : return 13 ; default : gcc_unreachable ( ) ; } case CC_FP_EQmode : switch ( GET_CODE ( comparison ) ) { case EQ : return 0 ; case NE : return 1 ; default : gcc_unreachable ( ) ; } case CC_FP_GTEmode : switch ( GET_CODE ( comparison ) ) { case EQ : return 0 ; case NE : return 1 ; case GT : return 4 ; case GE : return 6 ; case UNLE : return 5 ; case UNLT : return 7 ; default : gcc_unreachable ( ) ; } case CC_FP_ORDmode : switch ( GET_CODE ( comparison ) ) { case ORDERED : return 9 ; case UNORDERED : return 8 ; default : gcc_unreachable ( ) ; } case CC_FP_UNEQmode : switch ( GET_CODE ( comparison ) ) { case UNEQ : return 9 ; case LTGT : return 8 ; default : gcc_unreachable ( ) ; } default : gcc_unreachable ( ) ; } return ( 42 ) ; } </s>

Returns the index of the EPIPHANY condition code string in ` epiphany_condition_codes ' . COMPARISON should be an rtx like ` ( eq ( ... ) ( ... ) ) ' .


<s> unsigned HexagonRegisterInfo :: getRARegister ( ) const { return Hexagon :: R31 ; } </s>

This method should return the register where the return address can be found .


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BRCOND : return lowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return lowerConstantPool ( Op , DAG ) ; case ISD :: GlobalAddress : return lowerGlobalAddress ( Op , DAG ) ; case ISD :: BlockAddress : return lowerBlockAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return lowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return lowerJumpTable ( Op , DAG ) ; case ISD :: SELECT : return lowerSELECT ( Op , DAG ) ; case ISD :: SETCC : return lowerSETCC ( Op , DAG ) ; case ISD :: VASTART : return lowerVASTART ( Op , DAG ) ; case ISD :: VAARG : return lowerVAARG ( Op , DAG ) ; case ISD :: FCOPYSIGN : return lowerFCOPYSIGN ( Op , DAG ) ; case ISD :: FRAMEADDR : return lowerFRAMEADDR ( Op , DAG ) ; case ISD :: RETURNADDR : return lowerRETURNADDR ( Op , DAG ) ; case ISD :: EH_RETURN : return lowerEH_RETURN ( Op , DAG ) ; case ISD :: ATOMIC_FENCE : return lowerATOMIC_FENCE ( Op , DAG ) ; case ISD :: SHL_PARTS : return lowerShiftLeftParts ( Op , DAG ) ; case ISD :: SRA_PARTS : return lowerShiftRightParts ( Op , DAG , true ) ; case ISD :: SRL_PARTS : return lowerShiftRightParts ( Op , DAG , false ) ; case ISD :: LOAD : return lowerLOAD ( Op , DAG ) ; case ISD :: STORE : return lowerSTORE ( Op , DAG ) ; case ISD :: EH_DWARF_CFA : return lowerEH_DWARF_CFA ( Op , DAG ) ; case ISD :: FP_TO_SINT : return lowerFP_TO_SINT ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::BRCOND ISD::ConstantPool ISD::GlobalAddress ISD::BlockAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::SELECT ISD::SETCC ISD::VASTART ISD::VAARG ISD::FCOPYSIGN ISD::FRAMEADDR ISD::RETURNADDR ISD::EH_RETURN ISD::ATOMIC_FENCE ISD::SHL_PARTS ISD::SRA_PARTS ISD::SRL_PARTS ISD::LOAD ISD::STORE ISD::EH_DWARF_CFA ISD::FP_TO_SINT


<s> unsigned AMDGPUTargetMachine :: getAddressSpaceForPseudoSourceKind ( unsigned Kind ) const { switch ( Kind ) { case PseudoSourceValue :: Stack : case PseudoSourceValue :: FixedStack : return AMDGPUAS :: PRIVATE_ADDRESS ; case PseudoSourceValue :: ConstantPool : case PseudoSourceValue :: GOT : case PseudoSourceValue :: JumpTable : case PseudoSourceValue :: GlobalValueCallEntry : case PseudoSourceValue :: ExternalSymbolCallEntry : case PseudoSourceValue :: TargetCustom : return AMDGPUAS :: CONSTANT_ADDRESS ; } return AMDGPUAS :: FLAT_ADDRESS ; } </s>

getAddressSpaceForPseudoSourceKind - Given the kind of memory ( e.g .


"Relocation required in an instruction that we cannot encode!"

getMachineOpValue - Return binary encoding of operand .


<s>
void
OR1KDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
SDLoc
dl
(
Node
)
;
DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
FrameIndex
:
{
SDValue
imm
=
CurDAG
->
getTargetConstant
(
0
,
dl
,
MVT
::
i32
)
;
int
FI
=
dyn_cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
EVT
VT
=
Node
->
getValueType
(
0
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
VT
)
;
unsigned
Opc
=
OR1K
::
ADDI
;
if
(
Node
->
hasOneUse
(
)
)
CurDAG
->
SelectNodeTo
(
Node
,
Opc
,
VT
,
TFI
,
imm
)
;
else
ReplaceNode
(
Node
,
CurDAG
->
getMachineNode
(
Opc
,
dl
,
VT
,
TFI
,
imm
)
)
;
return
;
}
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> static bool use_skip_p ( rtx_insn * insn ) { rtx_insn * jump_insn = next_active_insn ( JUMP_LABEL_AS_INSN ( insn ) ) ; while ( insn ) { insn = next_active_insn ( insn ) ; if ( ! insn || GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT || asm_noperands ( PATTERN ( insn ) ) >= 0 ) break ; if ( get_attr_length ( insn ) == 4 && jump_insn == next_active_insn ( insn ) ) return TRUE ; if ( get_attr_length ( insn ) > 0 ) break ; } return FALSE ; } </s>

Return TRUE if INSN , a forward jump insn , can use nullification to skip the following instruction . This avoids an extra cycle due to a mis-predicted branch when we fall through .


"Unrecognized Hexagon processor version"

"Behavior is undefined for simultaneous qfloat and ieee hvx codegen..."

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> void GCNPassConfig :: addPreRegAlloc ( ) { addPass ( createSIShrinkInstructionsPass ( ) ) ; if ( EnableSDWAPeephole ) { addPass ( & SIPeepholeSDWAID ) ; addPass ( & DeadMachineInstructionElimID ) ; } addPass ( createSIWholeQuadModePass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s>
bool
HexagonFrameLowering
::
restoreCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
->
getTarget
(
)
.
getInstrInfo
(
)
;
if
(
CSI
.
empty
(
)
)
{
return
false
;
}
bool
ContiguousRegs
=
true
;
for
(
unsigned
i
=
0
;
i
<
CSI
.
size
(
)
;
++
i
)
{
unsigned
Reg
=
CSI
[
i
]
.
getReg
(
)
;
const
unsigned
*
SuperReg
=
TRI
->
getSuperRegisters
(
Reg
)
;
const
TargetRegisterClass
*
SuperRegClass
=
0
;
assert
(
SuperReg
[
0
]
&&
!
SuperReg
[
1
]
&&
"Expected exactly one superreg"
)
;
bool
CanUseDblLoad
=
false
;
if
(
ContiguousRegs
&&
(
i
<
CSI
.
size
(
)
1
)
)
{
const
unsigned
*
SuperRegNext
=
TRI
->
getSuperRegisters
(
CSI
[
i
+
1
]
.
getReg
(
)
)
;
assert
(
SuperRegNext
[
0
]
&&
!
SuperRegNext
[
1
]
&&
"Expected exactly one superreg"
)
;
SuperRegClass
=
TRI
->
getMinimalPhysRegClass
(
SuperReg
[
0
]
)
;
CanUseDblLoad
=
(
SuperRegNext
[
0
]
==
SuperReg
[
0
]
)
;
}
if
(
CanUseDblLoad
)
{
TII
.
loadRegFromStackSlot
(
MBB
,
MI
,
SuperReg
[
0
]
,
CSI
[
i
+
1
]
.
getFrameIdx
(
)
,
SuperRegClass
,
TRI
)
;
MBB
.
addLiveIn
(
SuperReg
[
0
]
)
;
++
i
;
}
else
{
ContiguousRegs
=
false
;
const
TargetRegisterClass
*
RC
=
TRI
->
getMinimalPhysRegClass
(
Reg
)
;
TII
.
loadRegFromStackSlot
(
MBB
,
MI
,
Reg
,
CSI
[
i
]
.
getFrameIdx
(
)
,
RC
,
TRI
)
;
MBB
.
addLiveIn
(
Reg
)
;
}
}
return
true
;
}
</s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s>
unsigned
TOYMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
)
const
{
if
(
MO
.
isReg
(
)
)
{
switch
(
MO
.
getReg
(
)
)
{
case
TOY
::
R0
:
return
0
;
case
TOY
::
R1
:
return
1
;
case
TOY
::
R2
:
return
2
;
case
TOY
::
R3
:
return
3
;
case
TOY
::
ZERO
:
return
4
;
case
TOY
::
SP
:
return
5
;
case
TOY
::
LR
:
return
6
;
case
TOY
::
TMP
:
return
7
;
case
TOY
::
PRED
:
return
8
;
default
:
llvm_unreachable
(
"Unable to encode MachineOperand!"
)
;
}
}
else
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
else
if
(
MO
.
isExpr
(
)
)
{
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
assert
(
Expr
->
getKind
(
)
==
MCExpr
::
SymbolRef
)
;
TOY
::
Fixups
FixupKind
=
TOY
::
Fixups
(
0
)
;
switch
(
cast
<
MCSymbolRefExpr
>
(
Expr
)
->
getKind
(
)
)
{
default
:
llvm_unreachable
(
"Unknown fixup kind!"
)
;
case
MCSymbolRefExpr
::
VK_TOY_CALL
:
FixupKind
=
TOY
::
fixup_TOY_CALL
;
break
;
case
MCSymbolRefExpr
::
VK_TOY_BR
:
FixupKind
=
TOY
::
fixup_TOY_BR
;
break
;
}
Fixups
.
push_back
(
MCFixup
::
Create
(
0
,
MO
.
getExpr
(
)
,
MCFixupKind
(
FixupKind
)
)
)
;
}
else
llvm_unreachable
(
"Unable to encode MachineOperand!"
)
;
return
0
;
}
</s>


<s> const Triple & getTargetTriple ( ) const { return TargetTriple ; } </s>

Get the target triple which is a string describing the target host .


<s> bool addInstSelector ( ) override { addPass ( createPatmosISelDag ( getPatmosTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool X86TargetLowering :: isVectorShiftByScalarCheap ( Type * Ty ) const { unsigned Bits = Ty -> getScalarSizeInBits ( ) ; if ( Bits == 8 ) return false ; if ( Subtarget . hasInt256 ( ) && ( Bits == 32 || Bits == 64 ) ) return false ; return true ; } </s>

This is used to enable splatted operand transforms for vector shifts and vector funnel shifts .


<s> const LC2200RegisterInfo * getRegisterInfo ( ) const override { return & RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> unsigned MipsRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { switch ( RC -> getID ( ) ) { default : return 0 ; case Mips :: GPR32RegClassID : case Mips :: GPR64RegClassID : case Mips :: DSPRRegClassID : { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return 28 - TFI -> hasFP ( MF ) ; } case Mips :: FGR32RegClassID : return 32 ; case Mips :: AFGR64RegClassID : return 16 ; case Mips :: FGR64RegClassID : return 32 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> void clear ( ) { Bits . clear ( ) ; LRU . clear ( ) ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesAll ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool isImm ( int64_t MinValue , int64_t MaxValue ) const { return Kind == KindImm && inRange ( Imm , MinValue , MaxValue ) ; } </s>


<s> static int h8300_register_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t from , reg_class_t to ) { if ( from == MAC_REGS || to == MAC_REG ) return 6 ; else return 3 ; } </s>

Implements TARGET_REGISTER_MOVE_COST . Any SI register-to-register move may need to be reloaded , so inmplement h8300_register_move_cost to return > 2 so that reload never shortcuts .