<s> void SIInstrInfo :: legalizeOpWithMove ( MachineInstr & MI , unsigned OpIdx ) const { MachineBasicBlock :: iterator I = MI ; MachineBasicBlock * MBB = MI . getParent ( ) ; MachineOperand & MO = MI . getOperand ( OpIdx ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; unsigned RCID = get ( MI . getOpcode ( ) ) . OpInfo [ OpIdx ] . RegClass ; const TargetRegisterClass * RC = RI . getRegClass ( RCID ) ; unsigned Opcode = AMDGPU :: V_MOV_B32_e32 ; if ( MO . isReg ( ) ) Opcode = AMDGPU :: COPY ; else if ( RI . isSGPRClass ( RC ) ) Opcode = AMDGPU :: S_MOV_B32 ; const TargetRegisterClass * VRC = RI . getEquivalentVGPRClass ( RC ) ; if ( RI . getCommonSubClass ( & AMDGPU :: VReg_64RegClass , VRC ) ) VRC = & AMDGPU :: VReg_64RegClass ; else VRC = & AMDGPU :: VGPR_32RegClass ; unsigned Reg = MRI . createVirtualRegister ( VRC ) ; DebugLoc DL = MBB -> findDebugLoc ( I ) ; BuildMI ( * MI . getParent ( ) , I , DL , get ( Opcode ) , Reg ) . add ( MO ) ; MO . ChangeToRegister ( Reg , false ) ; } </s>

Legalize the OpIndex operand of this instruction by inserting a MOV .


<s> const uint32_t * AArch64RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return CSR_AArch64_NoRegs_RegMask ; if ( CC == CallingConv :: AnyReg ) return CSR_AArch64_AllRegs_RegMask ; if ( CC == CallingConv :: CXX_FAST_TLS ) return CSR_AArch64_CXX_TLS_Darwin_RegMask ; if ( MF . getSubtarget < AArch64Subtarget > ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_AArch64_AAPCS_SwiftError_RegMask ; if ( CC == CallingConv :: PreserveMost ) return CSR_AArch64_RT_MostRegs_RegMask ; else return CSR_AArch64_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool PPCFastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Load : return SelectLoad ( I ) ; case Instruction :: Store : return SelectStore ( I ) ; case Instruction :: Br : return SelectBranch ( I ) ; case Instruction :: IndirectBr : return SelectIndirectBr ( I ) ; case Instruction :: FPExt : return SelectFPExt ( I ) ; case Instruction :: FPTrunc : return SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return SelectIToFP ( I , true ) ; case Instruction :: UIToFP : return SelectIToFP ( I , false ) ; case Instruction :: FPToSI : return SelectFPToI ( I , true ) ; case Instruction :: FPToUI : return SelectFPToI ( I , false ) ; case Instruction :: Add : return SelectBinaryIntOp ( I , ISD :: ADD ) ; case Instruction :: Or : return SelectBinaryIntOp ( I , ISD :: OR ) ; case Instruction :: Sub : return SelectBinaryIntOp ( I , ISD :: SUB ) ; case Instruction :: Call : return selectCall ( I ) ; case Instruction :: Ret : return SelectRet ( I ) ; case Instruction :: Trunc : return SelectTrunc ( I ) ; case Instruction :: ZExt : case Instruction :: SExt : return SelectIntExt ( I ) ; default : break ; } return false ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> static void nvptx_file_end ( void ) { hash_table < tree_hasher > :: iterator iter ; tree decl ; FOR_EACH_HASH_TABLE_ELEMENT ( * needed_fndecls_htab , decl , tree , iter ) nvptx_record_fndecl ( decl , true ) ; fputs ( func_decls . str ( ) . c_str ( ) , asm_out_file ) ; } </s>

Write out the function declarations we 've collected .


<s> static tree arm_handle_notshared_attribute ( tree * node , tree name ATTRIBUTE_UNUSED , tree args ATTRIBUTE_UNUSED , int flags ATTRIBUTE_UNUSED , bool * no_add_attrs ) { tree decl = TYPE_NAME ( * node ) ; if ( decl ) { DECL_VISIBILITY ( decl ) = VISIBILITY_HIDDEN ; DECL_VISIBILITY_SPECIFIED ( decl ) = 1 ; * no_add_attrs = false ; } return NULL_TREE ; } </s>

Handle the `` notshared '' attribute . This attribute is another way of requesting hidden visibility . ARM 's compiler supports `` __declspec ( notshared ) '' ; we support the same thing via an attribute .


Return an array that contains the MMO target flag values and their names .


<s> bool PPCAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == ".word" ) ParseDirectiveWord ( 2 , DirectiveID ) ; else if ( IDVal == ".llong" ) ParseDirectiveWord ( 8 , DirectiveID ) ; else if ( IDVal == ".tc" ) ParseDirectiveTC ( isPPC64 ( ) ? 8 : 4 , DirectiveID ) ; else if ( IDVal == ".machine" ) ParseDirectiveMachine ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".abiversion" ) ParseDirectiveAbiVersion ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".localentry" ) ParseDirectiveLocalEntry ( DirectiveID . getLoc ( ) ) ; else return true ; return false ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s>
static
bool
isValidOffset
(
RISCVAddressingMode
::
OffRange
OffR
,
int64_t
Val
)
{
assert
(
selectOffset
(
OffR
,
Val
)
&&
"Invalid displacement"
)
;
switch
(
OffR
)
{
case
RISCVAddressingMode
::
Off12Only
:
return
true
;
}
llvm_unreachable
(
"Unhandled displacement range"
)
;
}
</s>

RISCV
RISCVAddressingMode::OffRange
"Invalid displacement"
RISCVAddressingMode::Off12Only
"Unhandled displacement range"


<s> BitVector AVRRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AVR :: R0 ) ; Reserved . set ( AVR :: R1 ) ; Reserved . set ( AVR :: R1R0 ) ; Reserved . set ( AVR :: SPL ) ; Reserved . set ( AVR :: SPH ) ; Reserved . set ( AVR :: SP ) ; if ( MF . getSubtarget < AVRSubtarget > ( ) . hasTinyEncoding ( ) ) { for ( unsigned Reg = AVR :: R2 ; Reg <= AVR :: R17 ; Reg ++ ) Reserved . set ( Reg ) ; for ( unsigned Reg = AVR :: R3R2 ; Reg <= AVR :: R18R17 ; Reg ++ ) Reserved . set ( Reg ) ; } Reserved . set ( AVR :: R28 ) ; Reserved . set ( AVR :: R29 ) ; Reserved . set ( AVR :: R29R28 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void mn10300_override_options ( void ) { if ( TARGET_AM33 ) target_flags &= ~ MASK_MULT_BUG ; } </s>


<s> EVT X86TargetLowering :: getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const { if ( ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { if ( Op . size ( ) >= 16 && ( ! Subtarget . isUnalignedMem16Slow ( ) || Op . isAligned ( Align ( 16 ) ) ) ) { if ( Op . size ( ) >= 64 && Subtarget . hasAVX512 ( ) && ( Subtarget . getPreferVectorWidth ( ) >= 512 ) ) { return Subtarget . hasBWI ( ) ? MVT :: v64i8 : MVT :: v16i32 ; } if ( Op . size ( ) >= 32 && Subtarget . hasAVX ( ) && ( Subtarget . getPreferVectorWidth ( ) >= 256 ) ) { return MVT :: v32i8 ; } if ( Subtarget . hasSSE2 ( ) && ( Subtarget . getPreferVectorWidth ( ) >= 128 ) ) return MVT :: v16i8 ; if ( Subtarget . hasSSE1 ( ) && ( Subtarget . is64Bit ( ) || Subtarget . hasX87 ( ) ) && ( Subtarget . getPreferVectorWidth ( ) >= 128 ) ) return MVT :: v4f32 ; } else if ( ( ( Op . isMemcpy ( ) && ! Op . isMemcpyStrSrc ( ) ) || Op . isZeroMemset ( ) ) && Op . size ( ) >= 8 && ! Subtarget . is64Bit ( ) && Subtarget . hasSSE2 ( ) ) { return MVT :: f64 ; } } if ( Subtarget . is64Bit ( ) && Op . size ( ) >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> static bool arm_evpc_neon_vuzp ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> nelt ; rtx out0 , out1 , in0 , in1 , x ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; if ( d -> perm [ 0 ] == 0 ) odd = 0 ; else if ( d -> perm [ 0 ] == 1 ) odd = 1 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt ; i ++ ) { unsigned elt = ( i * 2 + odd ) & mask ; if ( d -> perm [ i ] != elt ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vuzpv16qi_internal ; break ; case V8QImode : gen = gen_neon_vuzpv8qi_internal ; break ; case V8HImode : gen = gen_neon_vuzpv8hi_internal ; break ; case V4HImode : gen = gen_neon_vuzpv4hi_internal ; break ; case V4SImode : gen = gen_neon_vuzpv4si_internal ; break ; case V2SImode : gen = gen_neon_vuzpv2si_internal ; break ; case V2SFmode : gen = gen_neon_vuzpv2sf_internal ; break ; case V4SFmode : gen = gen_neon_vuzpv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN ) { x = in0 , in0 = in1 , in1 = x ; odd = ! odd ; } out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( odd ) x = out0 , out0 = out1 , out1 = x ; emit_insn ( gen ( out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s> SDValue RISCVTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case RISCVISD :: SplitF64 : { SDValue Op0 = N -> getOperand ( 0 ) ; if ( Op0 -> getOpcode ( ) == RISCVISD :: BuildPairF64 ) return DCI . CombineTo ( N , Op0 . getOperand ( 0 ) , Op0 . getOperand ( 1 ) ) ; SDLoc DL ( N ) ; if ( ! ( Op0 . getOpcode ( ) == ISD :: FNEG || Op0 . getOpcode ( ) == ISD :: FABS ) || ! Op0 . getNode ( ) -> hasOneUse ( ) ) break ; SDValue NewSplitF64 = DAG . getNode ( RISCVISD :: SplitF64 , DL , DAG . getVTList ( MVT :: i32 , MVT :: i32 ) , Op0 . getOperand ( 0 ) ) ; SDValue Lo = NewSplitF64 . getValue ( 0 ) ; SDValue Hi = NewSplitF64 . getValue ( 1 ) ; APInt SignBit = APInt :: getSignMask ( 32 ) ; if ( Op0 . getOpcode ( ) == ISD :: FNEG ) { SDValue NewHi = DAG . getNode ( ISD :: XOR , DL , MVT :: i32 , Hi , DAG . getConstant ( SignBit , DL , MVT :: i32 ) ) ; return DCI . CombineTo ( N , Lo , NewHi ) ; } assert ( Op0 . getOpcode ( ) == ISD :: FABS ) ; SDValue NewHi = DAG . getNode ( ISD :: AND , DL , MVT :: i32 , Hi , DAG . getConstant ( ~ SignBit , DL , MVT :: i32 ) ) ; return DCI . CombineTo ( N , Lo , NewHi ) ; } case RISCVISD :: SLLW : case RISCVISD :: SRAW : case RISCVISD :: SRLW : { SDValue LHS = N -> getOperand ( 0 ) ; SDValue RHS = N -> getOperand ( 1 ) ; APInt LHSMask = APInt :: getLowBitsSet ( LHS . getValueSizeInBits ( ) , 32 ) ; APInt RHSMask = APInt :: getLowBitsSet ( RHS . getValueSizeInBits ( ) , 5 ) ; if ( ( SimplifyDemandedBits ( N -> getOperand ( 0 ) , LHSMask , DCI ) ) || ( SimplifyDemandedBits ( N -> getOperand ( 1 ) , RHSMask , DCI ) ) ) return SDValue ( ) ; break ; } } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> unsigned char AArch64Subtarget :: ClassifyGlobalReference ( const GlobalValue * GV , const TargetMachine & TM ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) ) return AArch64II :: MO_GOT ; Reloc :: Model RM = TM . getRelocationModel ( ) ; if ( ! shouldAssumeDSOLocal ( RM , TargetTriple , * GV -> getParent ( ) , GV ) ) return AArch64II :: MO_GOT ; if ( TM . getCodeModel ( ) == CodeModel :: Small && GV -> hasExternalWeakLinkage ( ) ) return AArch64II :: MO_GOT ; return AArch64II :: MO_NO_FLAG ; } </s>

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be referenced for the current subtarget .


<s>
MachineBasicBlock
::
iterator
SIFrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
int64_t
Amount
=
I
->
getOperand
(
0
)
.
getImm
(
)
;
if
(
Amount
==
0
)
return
MBB
.
erase
(
I
)
;
const
SISubtarget
&
ST
=
MF
.
getSubtarget
<
SISubtarget
>
(
)
;
const
SIInstrInfo
*
TII
=
ST
.
getInstrInfo
(
)
;
const
DebugLoc
&
DL
=
I
->
getDebugLoc
(
)
;
unsigned
Opc
=
I
->
getOpcode
(
)
;
bool
IsDestroy
=
Opc
==
TII
->
getCallFrameDestroyOpcode
(
)
;
uint64_t
CalleePopAmount
=
IsDestroy
I
->
getOperand
(
1
)
.
getImm
(
)
:
0
;
const
TargetFrameLowering
*
TFI
=
MF
.
getSubtarget
(
)
.
getFrameLowering
(
)
;
if
(
!
TFI
->
hasReservedCallFrame
(
MF
)
)
{
unsigned
Align
=
getStackAlignment
(
)
;
Amount
=
alignTo
(
Amount
,
Align
)
;
assert
(
isUInt
<
32
>
(
Amount
)
&&
"exceeded stack address space size"
)
;
const
SIMachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
SIMachineFunctionInfo
>
(
)
;
unsigned
SPReg
=
MFI
->
getStackPtrOffsetReg
(
)
;
unsigned
Op
=
IsDestroy
AMDGPU
::
S_SUB_U32
:
AMDGPU
::
S_ADD_U32
;
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
Op
)
,
SPReg
)
.
addReg
(
SPReg
)
.
addImm
(
Amount
*
ST
.
getWavefrontSize
(
)
)
;
}
else
if
(
CalleePopAmount
!=
0
)
{
llvm_unreachable
(
"is this used?"
)
;
}
return
MBB
.
erase
(
I
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> SMLoc getOffsetOfLoc ( ) const { return OffsetOfLoc ; } </s>

getOffsetOfLoc - Get the location of the offset operator .


<s> virtual const TOYInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s>
void
XCoreTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
return
;
case
ISD
::
ADD
:
case
ISD
::
SUB
:
Results
.
push_back
(
ExpandADDSUB
(
N
,
DAG
)
)
;
return
;
}
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

XCore
XCore
"Don't know how to custom expand this!"
ISD::ADD
ISD::SUB


<s> bool TeakTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; if ( ! CCInfo . CheckReturn ( Outs , RetCC_Teak ) ) { return false ; } if ( CCInfo . getNextStackOffset ( ) != 0 && isVarArg ) { return false ; } return true ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> rtx msp430_return_addr_rtx ( int count ) { int ra_size ; if ( count ) return NULL_RTX ; ra_size = TARGET_LARGE ? 4 : 2 ; if ( crtl -> args . pretend_args_size ) ra_size += 2 ; return gen_rtx_MEM ( Pmode , gen_rtx_PLUS ( Pmode , arg_pointer_rtx , GEN_INT ( - ra_size ) ) ) ; } </s>


<s> unsigned getCSRFirstUseCost ( const MachineFunction & MF ) const override { return 5 ; } </s>

Allow the target to override the cost of using a callee-saved register for the first time .


<s>
MachineBasicBlock
*
Z80TargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
MBB
)
const
{
unsigned
Opc
=
MI
->
getOpcode
(
)
;
switch
(
Opc
)
{
case
Z80
::
SELECT8
:
case
Z80
::
SELECT16
:
return
EmitSelectInstr
(
MI
,
MBB
)
;
case
Z80
::
SHL8
:
case
Z80
::
LSHR8
:
case
Z80
::
ASHR8
:
case
Z80
::
SHL16
:
case
Z80
::
LSHR16
:
case
Z80
::
ASHR16
:
return
EmitShiftInstr
(
MI
,
MBB
)
;
default
:
llvm_unreachable
(
"Invalid Custom Inserter Instruction"
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> inline unsigned int function_base :: call_properties ( const function_instance & instance ) const { unsigned int flags = 0 ; if ( instance . any_type_float_p ( ) ) return flags | CP_READ_FPCR | CP_RAISE_FP_EXCEPTIONS ; return flags ; } </s>

Default implementation of function_base : :call_properties , with conservatively correct behavior for floating-point instructions .


"********** AArch64 Conditional Branch Tuning  **********\n"

runOnMachineFunction - Emit the function body .


<s> void DLXFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const DLXRegisterInfo * LRI = static_cast < const DLXRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; int Offset = - 4 ; MFI . CreateFixedObject ( 4 , Offset , true ) ; Offset -= 4 ; MFI . CreateFixedObject ( 4 , Offset , true ) ; Offset -= 4 ; if ( LRI -> hasBasePointer ( MF ) ) { MFI . CreateFixedObject ( 4 , Offset , true ) ; SavedRegs . reset ( LRI -> getBaseRegister ( ) ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> bool WebAssemblyLateEHPrepare :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getTarget ( ) . getMCAsmInfo ( ) -> getExceptionHandlingType ( ) != ExceptionHandling :: Wasm ) return false ; bool Changed = false ; Changed |= addRethrows ( MF ) ; if ( ! MF . getFunction ( ) . hasPersonalityFn ( ) ) return Changed ; Changed |= replaceFuncletReturns ( MF ) ; Changed |= hoistCatches ( MF ) ; Changed |= addCatchAlls ( MF ) ; Changed |= ensureSingleBBTermPads ( MF ) ; Changed |= mergeTerminatePads ( MF ) ; Changed |= addCatchAllTerminatePads ( MF ) ; return Changed ; } </s>


<s> void aarch64_expand_compare_and_swap ( rtx operands [ ] ) { rtx bval , rval , mem , oldval , newval , is_weak , mod_s , mod_f , x ; machine_mode mode , cmp_mode ; typedef rtx ( * gen_cas_fn ) ( rtx , rtx , rtx , rtx , rtx , rtx , rtx ) ; int idx ; gen_cas_fn gen ; const gen_cas_fn split_cas [ ] = { gen_aarch64_compare_and_swapqi , gen_aarch64_compare_and_swaphi , gen_aarch64_compare_and_swapsi , gen_aarch64_compare_and_swapdi } ; const gen_cas_fn atomic_cas [ ] = { gen_aarch64_compare_and_swapqi_lse , gen_aarch64_compare_and_swaphi_lse , gen_aarch64_compare_and_swapsi_lse , gen_aarch64_compare_and_swapdi_lse } ; bval = operands [ 0 ] ; rval = operands [ 1 ] ; mem = operands [ 2 ] ; oldval = operands [ 3 ] ; newval = operands [ 4 ] ; is_weak = operands [ 5 ] ; mod_s = operands [ 6 ] ; mod_f = operands [ 7 ] ; mode = GET_MODE ( mem ) ; cmp_mode = mode ; if ( is_mm_acquire ( memmodel_from_int ( INTVAL ( mod_f ) ) ) && is_mm_release ( memmodel_from_int ( INTVAL ( mod_s ) ) ) ) mod_s = GEN_INT ( MEMMODEL_ACQ_REL ) ; switch ( mode ) { case E_QImode : case E_HImode : cmp_mode = SImode ; rval = gen_reg_rtx ( SImode ) ; oldval = convert_modes ( SImode , mode , oldval , true ) ; case E_SImode : case E_DImode : if ( ! aarch64_plus_operand ( oldval , mode ) ) oldval = force_reg ( cmp_mode , oldval ) ; break ; default : gcc_unreachable ( ) ; } switch ( mode ) { case E_QImode : idx = 0 ; break ; case E_HImode : idx = 1 ; break ; case E_SImode : idx = 2 ; break ; case E_DImode : idx = 3 ; break ; default : gcc_unreachable ( ) ; } if ( TARGET_LSE ) gen = atomic_cas [ idx ] ; else gen = split_cas [ idx ] ; emit_insn ( gen ( rval , mem , oldval , newval , is_weak , mod_s , mod_f ) ) ; if ( mode == QImode || mode == HImode ) emit_move_insn ( operands [ 1 ] , gen_lowpart ( mode , rval ) ) ; x = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_EQ ( SImode , x , const0_rtx ) ; emit_insn ( gen_rtx_SET ( bval , x ) ) ; } </s>


<s> void M88kPreLegalizerCombiner :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < TargetPassConfig > ( ) ; AU . setPreservesCFG ( ) ; getSelectionDAGFallbackAnalysisUsage ( AU ) ; AU . addRequired < GISelKnownBitsAnalysis > ( ) ; AU . addPreserved < GISelKnownBitsAnalysis > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < GISelCSEAnalysisWrapperPass > ( ) ; AU . addPreserved < GISelCSEAnalysisWrapperPass > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool Z80InstrInfo :: isUnpredicatedTerminator ( const MachineInstr & MI ) const { if ( ! MI . isTerminator ( ) ) return false ; if ( MI . isBranch ( ) && ! MI . isBarrier ( ) ) return true ; if ( ! MI . isPredicable ( ) ) return true ; return ! isPredicated ( MI ) ; } </s>

Returns true if the instruction is a terminator instruction that has not been predicated .


<s> const char * AMDGPUTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; NODE_NAME_CASE ( MAD ) ; NODE_NAME_CASE ( CALL ) ; NODE_NAME_CASE ( UMUL ) ; NODE_NAME_CASE ( DIV_INF ) ; NODE_NAME_CASE ( RET_FLAG ) ; NODE_NAME_CASE ( BRANCH_COND ) ; NODE_NAME_CASE ( DWORDADDR ) NODE_NAME_CASE ( FRACT ) NODE_NAME_CASE ( FMAX ) NODE_NAME_CASE ( SMAX ) NODE_NAME_CASE ( UMAX ) NODE_NAME_CASE ( FMIN ) NODE_NAME_CASE ( SMIN ) NODE_NAME_CASE ( UMIN ) NODE_NAME_CASE ( URECIP ) NODE_NAME_CASE ( INTERP ) NODE_NAME_CASE ( INTERP_P0 ) NODE_NAME_CASE ( EXPORT ) } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static int spu_sched_adjust_cost ( rtx_insn * insn , rtx link , rtx_insn * dep_insn , int cost ) { rtx set ; if ( INSN_CODE ( insn ) == CODE_FOR_blockage || INSN_CODE ( dep_insn ) == CODE_FOR_blockage ) return 0 ; if ( ( INSN_P ( insn ) && get_attr_length ( insn ) == 0 ) || ( INSN_P ( dep_insn ) && get_attr_length ( dep_insn ) == 0 ) ) return 0 ; if ( INSN_CODE ( insn ) == CODE_FOR_iprefetch && INSN_CODE ( dep_insn ) == CODE_FOR_iprefetch ) return 8 ; if ( ( INSN_CODE ( insn ) == CODE_FOR_iprefetch || INSN_CODE ( insn ) == CODE_FOR_hbr ) && ( INSN_CODE ( dep_insn ) == CODE_FOR_iprefetch || INSN_CODE ( dep_insn ) == CODE_FOR_hbr ) ) return 2 ; if ( INSN_CODE ( insn ) == CODE_FOR_iprefetch || INSN_CODE ( dep_insn ) == CODE_FOR_iprefetch ) return 0 ; if ( CALL_P ( insn ) ) { rtx target = get_branch_target ( insn ) ; if ( GET_CODE ( target ) != REG || ! set_of ( target , insn ) ) return cost - 2 ; return cost ; } if ( CALL_P ( dep_insn ) ) return cost - 2 ; if ( INSN_CODE ( insn ) == CODE_FOR__return && ( set = single_set ( dep_insn ) ) && GET_CODE ( SET_DEST ( set ) ) == REG && REGNO ( SET_DEST ( set ) ) == LINK_REGISTER_REGNUM ) return 20 ; if ( JUMP_P ( insn ) && REG_NOTE_KIND ( link ) == REG_DEP_ANTI ) return insn_cost ( dep_insn ) - 3 ; return cost ; } </s>


"variadic functions must use the base AAPCS variant"

Get the PCS variant to use for this call . TYPE is the function 's type specification , DECL is the specific declartion . DECL may be null if the call could be indirect or if this is a library call .


"memset lowering not implemented for PTX yet"

Emit target-specific code that performs a memset .


<s> static bool tail_agnostic_p ( rtx_insn * rinsn ) { extract_insn_cached ( rinsn ) ; int ta = get_attr_ta ( rinsn ) ; return ta == INVALID_ATTRIBUTE ? get_default_ta ( ) : IS_AGNOSTIC ( ta ) ; } </s>


<s> unsigned X86TargetLowering :: getJumpTableEncoding ( ) const { if ( isPositionIndependent ( ) && Subtarget . isPICStyleGOT ( ) ) return MachineJumpTableInfo :: EK_Custom32 ; return TargetLowering :: getJumpTableEncoding ( ) ; } </s>

Return the entry encoding for a jump table in the current function .


<s> bool X86FastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { const Value * Ptr = LI -> getPointerOperand ( ) ; X86AddressMode AM ; if ( ! X86SelectAddress ( Ptr , AM ) ) return false ; const X86InstrInfo & XII = ( const X86InstrInfo & ) TII ; unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; Align Alignment = DL . getValueOrABITypeAlignment ( LI -> getAlign ( ) , LI -> getType ( ) ) ; SmallVector < MachineOperand , 8 > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , * MI , OpNo , AddrOps , FuncInfo . InsertPt , Size , Alignment , true ) ; if ( ! Result ) return false ; unsigned OperandNo = 0 ; for ( MachineInstr :: mop_iterator I = Result -> operands_begin ( ) , E = Result -> operands_end ( ) ; I != E ; ++ I , ++ OperandNo ) { MachineOperand & MO = * I ; if ( ! MO . isReg ( ) || MO . isDef ( ) || MO . getReg ( ) != AM . IndexReg ) continue ; unsigned IndexReg = constrainOperandRegClass ( Result -> getDesc ( ) , MO . getReg ( ) , OperandNo ) ; if ( IndexReg == MO . getReg ( ) ) continue ; MO . setReg ( IndexReg ) ; } Result -> addMemOperand ( * FuncInfo . MF , createMachineMemOperandFor ( LI ) ) ; Result -> cloneInstrSymbols ( * FuncInfo . MF , * MI ) ; MachineBasicBlock :: iterator I ( MI ) ; removeDeadCode ( I , std :: next ( I ) ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> void split_quadword_operands ( rtx * operands , rtx * low , int n ATTRIBUTE_UNUSED ) { int i ; low [ 0 ] = low [ 1 ] = low [ 2 ] = 0 ; for ( i = 0 ; i < 3 ; i ++ ) { if ( low [ i ] ) ; else if ( GET_CODE ( operands [ i ] ) == MEM && ( GET_CODE ( XEXP ( operands [ i ] , 0 ) ) == POST_INC ) ) { rtx addr = XEXP ( operands [ i ] , 0 ) ; operands [ i ] = low [ i ] = gen_rtx_MEM ( SImode , addr ) ; if ( which_alternative == 0 && i == 0 ) { addr = XEXP ( operands [ i ] , 0 ) ; operands [ i + 1 ] = low [ i + 1 ] = gen_rtx_MEM ( SImode , addr ) ; } } else { low [ i ] = operand_subword ( operands [ i ] , 0 , 0 , DImode ) ; operands [ i ] = operand_subword ( operands [ i ] , 1 , 0 , DImode ) ; } } } </s>

This is like nonimmediate_operand with a restriction on the type of MEM .


<s> TargetLoweringBase :: LegalizeTypeAction HexagonTargetLowering :: getPreferredVectorAction ( MVT VT ) const { unsigned VecLen = VT . getVectorNumElements ( ) ; MVT ElemTy = VT . getVectorElementType ( ) ; if ( VecLen == 1 || VT . isScalableVector ( ) ) return TargetLoweringBase :: TypeScalarizeVector ; if ( Subtarget . useHVXOps ( ) ) { unsigned HwLen = Subtarget . getVectorLength ( ) ; ArrayRef < MVT > Tys = Subtarget . getHVXElementTypes ( ) ; if ( llvm :: find ( Tys , ElemTy ) != Tys . end ( ) ) { unsigned HwWidth = 8 * HwLen ; unsigned VecWidth = VT . getSizeInBits ( ) ; if ( VecWidth >= HwWidth / 2 && VecWidth < HwWidth ) return TargetLoweringBase :: TypeWidenVector ; } if ( ElemTy == MVT :: i1 && VecLen == 2 * HwLen ) return TargetLoweringBase :: TypeSplitVector ; } if ( ElemTy == MVT :: i1 ) return TargetLoweringBase :: TypeWidenVector ; return TargetLoweringBase :: TypeSplitVector ; } </s>

Customize the preferred legalization strategy for certain types .


<s> void SystemZTTIImpl :: getUnrollingPreferences ( Loop * L , TTI :: UnrollingPreferences & UP ) { bool HasCall = false ; unsigned NumStores = 0 ; for ( auto & BB : L -> blocks ( ) ) for ( auto & I : * BB ) { if ( isa < CallInst > ( & I ) || isa < InvokeInst > ( & I ) ) { ImmutableCallSite CS ( & I ) ; if ( const Function * F = CS . getCalledFunction ( ) ) { if ( isLoweredToCall ( F ) ) HasCall = true ; if ( F -> getIntrinsicID ( ) == Intrinsic :: memcpy || F -> getIntrinsicID ( ) == Intrinsic :: memset ) NumStores ++ ; } else { HasCall = true ; } } if ( isa < StoreInst > ( & I ) ) { Type * MemAccessTy = I . getOperand ( 0 ) -> getType ( ) ; NumStores += getMemoryOpCost ( Instruction :: Store , MemAccessTy , 0 , 0 ) ; } } unsigned const Max = ( NumStores ? ( 12 / NumStores ) : UINT_MAX ) ; if ( HasCall ) { UP . FullUnrollMaxCount = Max ; UP . MaxCount = 1 ; return ; } UP . MaxCount = Max ; if ( UP . MaxCount <= 1 ) return ; UP . Partial = UP . Runtime = true ; UP . PartialThreshold = 75 ; UP . DefaultUnrollRuntimeCount = 4 ; UP . AllowExpensiveTripCount = true ; UP . Force = true ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> bool RISCVPassConfig :: addIRTranslator ( ) { addPass ( new IRTranslator ( ) ) ; return false ; } </s>

This method should install an IR translator pass , which converts from LLVM code to machine instructions with possibly generic opcodes .


<s> TargetRegisterClass * TMS320C64XLowering :: getRegClassFor ( EVT VT ) const { if ( ST -> enableClusterAssignment ( ) ) return TMS320C64X :: GPRegsRegisterClass ; else return TMS320C64X :: ARegsRegisterClass ; } </s>

Return the register class that should be used for the specified value type .


For stack frames that ca n't be allocated with a single ADDI instruction , compute the best value to initially allocate . It must at a minimum allocate enough space to spill the callee-saved registers .


<s> bool Error ( const StringRef & msg , const AsmToken & tok ) { return Parser . Error ( tok . getLoc ( ) , msg + tok . getString ( ) ) ; } </s>

Return an error at the location L , with the message Msg .


<s> static bool arm_evpc_neon_vrev ( struct expand_vec_perm_d * d ) { unsigned int i , j , diff , nelt = d -> nelt ; rtx ( * gen ) ( rtx , rtx ) ; if ( ! d -> one_vector_p ) return false ; diff = d -> perm [ 0 ] ; switch ( diff ) { case 7 : switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vrev64v16qi ; break ; case V8QImode : gen = gen_neon_vrev64v8qi ; break ; default : return false ; } break ; case 3 : switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vrev32v16qi ; break ; case V8QImode : gen = gen_neon_vrev32v8qi ; break ; case V8HImode : gen = gen_neon_vrev64v8hi ; break ; case V4HImode : gen = gen_neon_vrev64v4hi ; break ; case V8HFmode : gen = gen_neon_vrev64v8hf ; break ; case V4HFmode : gen = gen_neon_vrev64v4hf ; break ; default : return false ; } break ; case 1 : switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vrev16v16qi ; break ; case V8QImode : gen = gen_neon_vrev16v8qi ; break ; case V8HImode : gen = gen_neon_vrev32v8hi ; break ; case V4HImode : gen = gen_neon_vrev32v4hi ; break ; case V4SImode : gen = gen_neon_vrev64v4si ; break ; case V2SImode : gen = gen_neon_vrev64v2si ; break ; case V4SFmode : gen = gen_neon_vrev64v4sf ; break ; case V2SFmode : gen = gen_neon_vrev64v2sf ; break ; default : return false ; } break ; default : return false ; } for ( i = 0 ; i < nelt ; i += diff + 1 ) for ( j = 0 ; j <= diff ; j += 1 ) { gcc_assert ( i + j < nelt ) ; if ( d -> perm [ i + j ] != i + diff - j ) return false ; } if ( d -> testing_p ) return true ; emit_insn ( gen ( d -> target , d -> op0 ) ) ; return true ; } </s>


<s> bool PTXInstrInfo :: isUnpredicatedTerminator ( const MachineInstr * MI ) const { return ! isPredicated ( MI ) && MI -> isTerminator ( ) ; } </s>


<s> void TeakMCInstLower :: Initialize ( Mangler * M , MCContext * C ) { Mang = M ; Ctx = C ; } </s>

This method must be called before any actual lowering is done .


<s> void PPCInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { unsigned Directive = Subtarget . getMcpu ( ) ; unsigned Opcode ; switch ( Directive ) { default : Opcode = PPC :: NOP ; break ; case PPC :: MCPU_PWR6 : Opcode = PPC :: NOP_GT_PWR6 ; break ; case PPC :: MCPU_PWR7 : Opcode = PPC :: NOP_GT_PWR7 ; break ; case PPC :: MCPU_PWR8 : Opcode = PPC :: NOP_GT_PWR7 ; break ; case PPC :: MCPU_PWR9 : Opcode = PPC :: NOP_GT_PWR7 ; break ; } DebugLoc DL ; BuildMI ( MBB , MI , DL , get ( Opcode ) ) ; } </s>

Insert a noop into the instruction stream at the specified point .


<s> void tilegx_expand_movmisalign ( machine_mode mode , rtx * operands ) { if ( MEM_P ( operands [ 1 ] ) ) { rtx tmp ; if ( register_operand ( operands [ 0 ] , mode ) ) tmp = operands [ 0 ] ; else tmp = gen_reg_rtx ( mode ) ; tilegx_expand_unaligned_load ( tmp , operands [ 1 ] , GET_MODE_BITSIZE ( mode ) , 0 , true ) ; if ( tmp != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , tmp ) ; } else if ( MEM_P ( operands [ 0 ] ) ) { if ( ! reg_or_0_operand ( operands [ 1 ] , mode ) ) operands [ 1 ] = force_reg ( mode , operands [ 1 ] ) ; tilegx_expand_unaligned_store ( operands [ 0 ] , operands [ 1 ] , GET_MODE_BITSIZE ( mode ) , 0 ) ; } else gcc_unreachable ( ) ; } </s>

Implement the movmisalign patterns . One of the operands is a memory that is not naturally aligned . Emit instructions to load it .


<s>
const
char
*
output_64bit_ior
(
rtx
*
operands
)
{
unsigned
HOST_WIDE_INT
mask
=
INTVAL
(
operands
[
2
]
)
;
int
bs0
,
bs1
,
p
,
len
;
if
(
INTVAL
(
operands
[
2
]
)
==
0
)
return
"copy %1,%0"
;
for
(
bs0
=
0
;
bs0
<
HOST_BITS_PER_WIDE_INT
;
bs0
++
)
if
(
(
mask
&
(
(
unsigned
HOST_WIDE_INT
)
1
<<
bs0
)
)
!=
0
)
break
;
for
(
bs1
=
bs0
;
bs1
<
HOST_BITS_PER_WIDE_INT
;
bs1
++
)
if
(
(
mask
&
(
(
unsigned
HOST_WIDE_INT
)
1
<<
bs1
)
)
==
0
)
break
;
gcc_assert
(
bs1
==
HOST_BITS_PER_WIDE_INT
||
(
(
unsigned
HOST_WIDE_INT
)
1
<<
bs1
)
>
mask
)
;
p
=
63
bs0
;
len
=
bs1
bs0
;
operands
[
2
]
=
GEN_INT
(
p
)
;
operands
[
3
]
=
GEN_INT
(
len
)
;
return
"depdi -1,%2,%3,%0"
;
}
</s>

Return a string to perform a bitwise-and of operands [ 1 ] with operands [ 2 ] storing the result in operands [ 0 ] .


<s> bool PPCTTIImpl :: getTgtMemIntrinsic ( IntrinsicInst * Inst , MemIntrinsicInfo & Info ) { switch ( Inst -> getIntrinsicID ( ) ) { case Intrinsic :: ppc_altivec_lvx : case Intrinsic :: ppc_altivec_lvxl : case Intrinsic :: ppc_altivec_lvebx : case Intrinsic :: ppc_altivec_lvehx : case Intrinsic :: ppc_altivec_lvewx : case Intrinsic :: ppc_vsx_lxvd2x : case Intrinsic :: ppc_vsx_lxvw4x : case Intrinsic :: ppc_vsx_lxvd2x_be : case Intrinsic :: ppc_vsx_lxvw4x_be : case Intrinsic :: ppc_vsx_lxvl : case Intrinsic :: ppc_vsx_lxvll : { Info . PtrVal = Inst -> getArgOperand ( 0 ) ; Info . ReadMem = true ; Info . WriteMem = false ; return true ; } case Intrinsic :: ppc_altivec_stvx : case Intrinsic :: ppc_altivec_stvxl : case Intrinsic :: ppc_altivec_stvebx : case Intrinsic :: ppc_altivec_stvehx : case Intrinsic :: ppc_altivec_stvewx : case Intrinsic :: ppc_vsx_stxvd2x : case Intrinsic :: ppc_vsx_stxvw4x : case Intrinsic :: ppc_vsx_stxvd2x_be : case Intrinsic :: ppc_vsx_stxvw4x_be : case Intrinsic :: ppc_vsx_stxvl : case Intrinsic :: ppc_vsx_stxvll : { Info . PtrVal = Inst -> getArgOperand ( 1 ) ; Info . ReadMem = false ; Info . WriteMem = true ; return true ; } default : break ; } return false ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> void rs6000_expand_vector_set ( rtx target , rtx val , int elt ) { machine_mode mode = GET_MODE ( target ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx reg = gen_reg_rtx ( mode ) ; rtx mask , mem , x ; int width = GET_MODE_SIZE ( inner_mode ) ; int i ; if ( VECTOR_MEM_VSX_P ( mode ) && ( mode == V2DFmode || mode == V2DImode ) ) { rtx ( * set_func ) ( rtx , rtx , rtx , rtx ) = ( ( mode == V2DFmode ) ? gen_vsx_set_v2df : gen_vsx_set_v2di ) ; emit_insn ( set_func ( target , target , val , GEN_INT ( elt ) ) ) ; return ; } if ( GET_MODE_SIZE ( mode ) == GET_MODE_SIZE ( inner_mode ) && elt == 0 ) { emit_move_insn ( target , gen_lowpart ( mode , val ) ) ; return ; } mem = assign_stack_temp ( mode , GET_MODE_SIZE ( inner_mode ) ) ; emit_move_insn ( adjust_address_nv ( mem , inner_mode , 0 ) , val ) ; x = gen_rtx_UNSPEC ( VOIDmode , gen_rtvec ( 1 , const0_rtx ) , UNSPEC_LVE ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , gen_rtx_SET ( reg , mem ) , x ) ) ) ; mask = gen_rtx_PARALLEL ( V16QImode , rtvec_alloc ( 16 ) ) ; for ( i = 0 ; i < 16 ; ++ i ) XVECEXP ( mask , 0 , i ) = GEN_INT ( i ) ; for ( i = 0 ; i < width ; ++ i ) XVECEXP ( mask , 0 , elt * width + i ) = GEN_INT ( i + 0x10 ) ; x = gen_rtx_CONST_VECTOR ( V16QImode , XVEC ( mask , 0 ) ) ; if ( BYTES_BIG_ENDIAN ) x = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , target , reg , force_reg ( V16QImode , x ) ) , UNSPEC_VPERM ) ; else { rtx notx = gen_rtx_NOT ( V16QImode , force_reg ( V16QImode , x ) ) ; rtx iorx = ( TARGET_P8_VECTOR ? gen_rtx_IOR ( V16QImode , notx , notx ) : gen_rtx_AND ( V16QImode , notx , notx ) ) ; rtx tmp = gen_reg_rtx ( V16QImode ) ; emit_insn ( gen_rtx_SET ( tmp , iorx ) ) ; x = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , reg , target , tmp ) , UNSPEC_VPERM ) ; } emit_insn ( gen_rtx_SET ( target , x ) ) ; } </s>


Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static bool aarch64_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t ) { if ( BYTES_BIG_ENDIAN ) { bool from_sve_p = aarch64_sve_data_mode_p ( from ) ; bool to_sve_p = aarch64_sve_data_mode_p ( to ) ; if ( from_sve_p != to_sve_p ) return false ; if ( from_sve_p && GET_MODE_UNIT_SIZE ( from ) != GET_MODE_UNIT_SIZE ( to ) ) return false ; } return true ; } </s>


<s> void BPFPassConfig :: addIRPasses ( ) { addPass ( createBPFAbstractMemberAccess ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> void assignValueToAddress ( const CallLowering :: ArgInfo & Arg , unsigned ValRegIndex , Register Addr , LLT MemTy , MachinePointerInfo & MPO , CCValAssign & VA ) override { Register ValVReg = VA . getLocInfo ( ) != CCValAssign :: LocInfo :: FPExt ? extendRegister ( Arg . Regs [ ValRegIndex ] , VA ) : Arg . Regs [ ValRegIndex ] ; assignValueToAddress ( ValVReg , Addr , MemTy , MPO , VA ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> const SDValue & getValue ( ) const { return getOperand ( 1 ) ; } </s>


<s> unsigned ARMCodeEmitter :: getMachineOpValue ( const MachineInstr & MI , const MachineOperand & MO ) { if ( MO . isReg ( ) ) return ARMRegisterInfo :: getRegisterNumbering ( MO . getReg ( ) ) ; else if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; else if ( MO . isGlobal ( ) ) emitGlobalAddress ( MO . getGlobal ( ) , ARM :: reloc_arm_branch , true , false ) ; else if ( MO . isSymbol ( ) ) emitExternalSymbolAddress ( MO . getSymbolName ( ) , ARM :: reloc_arm_branch ) ; else if ( MO . isCPI ( ) ) { const TargetInstrDesc & TID = MI . getDesc ( ) ; unsigned Reloc = ( ( TID . TSFlags & ARMII :: FormMask ) == ARMII :: VFPLdStFrm ) ? ARM :: reloc_arm_vfp_cp_entry : ARM :: reloc_arm_cp_entry ; emitConstPoolAddress ( MO . getIndex ( ) , Reloc ) ; } else if ( MO . isJTI ( ) ) emitJumpTableAddress ( MO . getIndex ( ) , ARM :: reloc_arm_relative ) ; else if ( MO . isMBB ( ) ) emitMachineBasicBlock ( MO . getMBB ( ) , ARM :: reloc_arm_branch ) ; else { errs ( ) << MO ; llvm_unreachable ( 0 ) ; } return 0 ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> static int calc_live_regs ( int * count ) { int reg ; int live_regs_mask = 0 ; * count = 0 ; for ( reg = 0 ; reg < FIRST_PSEUDO_REGISTER ; reg ++ ) { if ( df_regs_ever_live_p ( reg ) && ! call_used_regs [ reg ] ) { ( * count ) ++ ; live_regs_mask |= ( 1 << reg ) ; } } return live_regs_mask ; } </s>

Work out the registers which need to be saved , both as a mask and a count


<s>
void
SIRegisterInfo
::
resolveFrameIndex
(
MachineInstr
&
MI
,
unsigned
BaseReg
,
int64_t
Offset
)
const
{
MachineBasicBlock
*
MBB
=
MI
.
getParent
(
)
;
MachineFunction
*
MF
=
MBB
->
getParent
(
)
;
const
SISubtarget
&
Subtarget
=
MF
->
getSubtarget
<
SISubtarget
>
(
)
;
const
SIInstrInfo
*
TII
=
Subtarget
.
getInstrInfo
(
)
;
bool
SeenFI
=
false
;
for
(
const
MachineOperand
&
MO
:
MI
.
operands
(
)
)
{
if
(
MO
.
isFI
(
)
)
{
if
(
SeenFI
)
llvm_unreachable
(
"should not see multiple frame indices"
)
;
SeenFI
=
true
;
}
}
MachineOperand
*
FIOp
=
TII
->
getNamedOperand
(
MI
,
AMDGPU
::
OpName
::
vaddr
)
;
assert
(
FIOp
&&
FIOp
->
isFI
(
)
&&
"frame index must be address operand"
)
;
assert
(
TII
->
isMUBUF
(
MI
)
)
;
MachineOperand
*
OffsetOp
=
TII
->
getNamedOperand
(
MI
,
AMDGPU
::
OpName
::
offset
)
;
int64_t
NewOffset
=
OffsetOp
->
getImm
(
)
+
Offset
;
assert
(
isUInt
<
12
>
(
NewOffset
)
&&
"offset should be legal"
)
;
FIOp
->
ChangeToRegister
(
BaseReg
,
false
)
;
OffsetOp
->
setImm
(
NewOffset
)
;
}
</s>

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .

AMDGPU
SI
SI
SI
SI
"should not see multiple frame indices"
AMDGPU::OpName
"frame index must be address operand"
AMDGPU::OpName
12
"offset should be legal"


<s> static bool isNodeHidden ( const ablock * , const agraph ) { return false ; } </s>

Do not print nodes that are part of a pi-block separately .


<s> bool SystemZElimCompare :: runOnMachineFunction ( MachineFunction & F ) { if ( skipFunction ( * F . getFunction ( ) ) ) return false ; TII = static_cast < const SystemZInstrInfo * > ( F . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = & TII -> getRegisterInfo ( ) ; bool Changed = false ; for ( auto & MBB : F ) Changed |= processBlock ( MBB ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> virtual bool hasRawTextSupport ( ) const { return true ; } </s>

Return true if this asm streamer supports emitting unformatted text to the .s file with EmitRawText .


<s> unsigned OptimizePICCall :: getReg ( ValueType Entry ) { unsigned Reg = ScopedHT . lookup ( Entry ) . second ; assert ( Reg ) ; return Reg ; } </s>

Returns the register associated with this edge .


<s> void emitExportName ( const MCSymbolWasm * , StringRef ) override { } </s>


<s> static rtx_insn * emit_new_cond_insn ( rtx insn , int cond ) { rtx c_insn = 0 ; rtx pat , dst , src ; cond_type num ; if ( ( num = is_cond_candidate ( insn ) ) == COND_NO ) return NULL ; pat = PATTERN ( insn ) ; if ( NONJUMP_INSN_P ( insn ) ) { dst = SET_DEST ( pat ) ; src = SET_SRC ( pat ) ; } else { dst = JUMP_LABEL ( insn ) ; src = NULL_RTX ; } switch ( num ) { case COND_MOV_INSN : case COND_CLR_INSN : if ( cond ) c_insn = gen_movt0 ( dst , src , dst ) ; else c_insn = gen_movt0 ( dst , dst , src ) ; break ; case COND_INC_INSN : if ( cond ) c_insn = gen_incscc ( dst , dst ) ; else c_insn = gen_incscc_false ( dst , dst ) ; break ; case COND_DEC_INSN : if ( cond ) c_insn = gen_decscc ( dst , dst ) ; else c_insn = gen_decscc_false ( dst , dst ) ; break ; case COND_BRANCH_INSN : if ( cond ) c_insn = gen_branch_true ( dst ) ; else c_insn = gen_branch_false ( dst ) ; break ; default : return NULL ; } if ( rtx_length [ GET_CODE ( c_insn ) ] >= 7 && rtx_length [ GET_CODE ( insn ) ] >= 7 ) { REG_NOTES ( c_insn ) = REG_NOTES ( insn ) ; } if ( num == COND_BRANCH_INSN ) { c_insn = emit_jump_insn_before ( c_insn , insn ) ; ++ LABEL_NUSES ( dst ) ; JUMP_LABEL ( c_insn ) = dst ; } else c_insn = emit_insn_after ( c_insn , insn ) ; delete_insn ( insn ) ; return as_a < rtx_insn * > ( c_insn ) ; } </s>

Emit a conditional version of insn and replace the old insn with the new one . Return the new insn if emitted .


<s> bool SITargetLowering :: getAddrModeArguments ( IntrinsicInst * II , SmallVectorImpl < Value * > & Ops , Type * & AccessTy ) const { switch ( II -> getIntrinsicID ( ) ) { case Intrinsic :: amdgcn_atomic_inc : case Intrinsic :: amdgcn_atomic_dec : case Intrinsic :: amdgcn_ds_ordered_add : case Intrinsic :: amdgcn_ds_ordered_swap : case Intrinsic :: amdgcn_ds_append : case Intrinsic :: amdgcn_ds_consume : case Intrinsic :: amdgcn_ds_fadd : case Intrinsic :: amdgcn_ds_fmin : case Intrinsic :: amdgcn_ds_fmax : case Intrinsic :: amdgcn_global_atomic_fadd : case Intrinsic :: amdgcn_flat_atomic_fadd : case Intrinsic :: amdgcn_flat_atomic_fmin : case Intrinsic :: amdgcn_flat_atomic_fmax : case Intrinsic :: amdgcn_global_atomic_csub : { Value * Ptr = II -> getArgOperand ( 0 ) ; AccessTy = II -> getType ( ) ; Ops . push_back ( Ptr ) ; return true ; } default : return false ; } } </s>

CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address .


<s> void BTFTypeArray :: completeType ( BTFDebug & BDebug ) { ArrayInfo . IndexType = BDebug . getArrayIndexTypeId ( ) ; } </s>

Complete BTF type generation after all related DebugInfo types have been visited so their BTF type id 's are available for cross referece .


<s>
bool
P2InstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
LLVM_DEBUG
(
errs
(
)
<<
"Analyze Branch MBB: "
)
;
LLVM_DEBUG
(
MBB
.
dump
(
)
)
;
int
old_br_code
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugInstr
(
)
)
continue
;
if
(
!
isUnpredicatedTerminator
(
*
I
)
)
break
;
if
(
!
I
->
isBranch
(
)
)
return
true
;
if
(
I
->
getOpcode
(
)
==
P2
::
JMPr
)
return
true
;
if
(
I
->
getOpcode
(
)
==
P2
::
JMP
)
{
if
(
!
AllowModify
)
{
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
continue
;
}
while
(
std
::
next
(
I
)
!=
MBB
.
end
(
)
)
std
::
next
(
I
)
->
eraseFromParent
(
)
;
Cond
.
clear
(
)
;
FBB
=
nullptr
;
if
(
MBB
.
isLayoutSuccessor
(
I
->
getOperand
(
0
)
.
getMBB
(
)
)
)
{
TBB
=
nullptr
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
continue
;
}
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
continue
;
}
assert
(
isCondBranchOpcode
(
I
->
getOpcode
(
)
)
&&
"Invalid conditional branch"
)
;
int
BranchCode
=
I
->
getOpcode
(
)
;
if
(
Cond
.
empty
(
)
)
{
FBB
=
TBB
;
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
BranchCode
)
)
;
Cond
.
push_back
(
I
->
getOperand
(
1
)
)
;
old_br_code
=
BranchCode
;
continue
;
}
assert
(
Cond
.
size
(
)
==
1
)
;
assert
(
TBB
)
;
if
(
TBB
!=
I
->
getOperand
(
0
)
.
getMBB
(
)
)
return
true
;
if
(
old_br_code
==
BranchCode
)
continue
;
return
true
;
}
return
false
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> void X86PassConfig :: addPreEmitPass2 ( ) { addPass ( createX86RetpolineThunksPass ( ) ) ; } </s>

Targets may add passes immediately before machine code is emitted in this callback .


Schedule - Order nodes according to selected style , filling in the Sequence member .


"%qE attribute only applies to functions"

"multiple function type attributes specified"

Handle interrupt_handler , exception_handler and nmi_handler function attributes ; arguments as in struct attribute_spec.handler .


<s> static bool aarch64_evpc_uzp ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> nelt ; rtx out , in0 , in1 , x ; rtx ( * gen ) ( rtx , rtx , rtx ) ; machine_mode vmode = d -> vmode ; if ( GET_MODE_UNIT_SIZE ( vmode ) > 8 ) return false ; if ( d -> perm [ 0 ] == 0 ) odd = 0 ; else if ( d -> perm [ 0 ] == 1 ) odd = 1 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt ; i ++ ) { unsigned elt = ( i * 2 + odd ) & mask ; if ( d -> perm [ i ] != elt ) return false ; } if ( d -> testing_p ) return true ; in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN ) { x = in0 , in0 = in1 , in1 = x ; odd = ! odd ; } out = d -> target ; if ( odd ) { switch ( vmode ) { case V16QImode : gen = gen_aarch64_uzp2v16qi ; break ; case V8QImode : gen = gen_aarch64_uzp2v8qi ; break ; case V8HImode : gen = gen_aarch64_uzp2v8hi ; break ; case V4HImode : gen = gen_aarch64_uzp2v4hi ; break ; case V4SImode : gen = gen_aarch64_uzp2v4si ; break ; case V2SImode : gen = gen_aarch64_uzp2v2si ; break ; case V2DImode : gen = gen_aarch64_uzp2v2di ; break ; case V4SFmode : gen = gen_aarch64_uzp2v4sf ; break ; case V2SFmode : gen = gen_aarch64_uzp2v2sf ; break ; case V2DFmode : gen = gen_aarch64_uzp2v2df ; break ; default : return false ; } } else { switch ( vmode ) { case V16QImode : gen = gen_aarch64_uzp1v16qi ; break ; case V8QImode : gen = gen_aarch64_uzp1v8qi ; break ; case V8HImode : gen = gen_aarch64_uzp1v8hi ; break ; case V4HImode : gen = gen_aarch64_uzp1v4hi ; break ; case V4SImode : gen = gen_aarch64_uzp1v4si ; break ; case V2SImode : gen = gen_aarch64_uzp1v2si ; break ; case V2DImode : gen = gen_aarch64_uzp1v2di ; break ; case V4SFmode : gen = gen_aarch64_uzp1v4sf ; break ; case V2SFmode : gen = gen_aarch64_uzp1v2sf ; break ; case V2DFmode : gen = gen_aarch64_uzp1v2df ; break ; default : return false ; } } emit_insn ( gen ( out , in0 , in1 ) ) ; return true ; } </s>

Recognize patterns suitable for the UZP instructions .


<s> SDValue LC3bTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { return Chain ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> static void ia64_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int words = ia64_function_arg_words ( type , mode ) ; int offset = ia64_function_arg_offset ( cum , type , words ) ; machine_mode hfa_mode = VOIDmode ; if ( cum -> words >= MAX_ARGUMENT_SLOTS ) { cum -> words += words + offset ; return ; } cum -> atypes [ cum -> words ] = ia64_arg_type ( mode ) ; cum -> words += words + offset ; if ( TARGET_ABI_OPEN_VMS ) { cum -> int_regs = cum -> words ; cum -> fp_regs = cum -> words ; return ; } if ( type ) hfa_mode = hfa_element_mode ( type , 0 ) ; if ( hfa_mode != VOIDmode && ( ! cum -> prototype || named ) ) { int fp_regs = cum -> fp_regs ; int int_regs = cum -> words - words ; int hfa_size = GET_MODE_SIZE ( hfa_mode ) ; int byte_size ; int args_byte_size ; byte_size = ( ( mode == BLKmode ) ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ) ; args_byte_size = int_regs * UNITS_PER_WORD ; offset = 0 ; for ( ; ( offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS && args_byte_size < ( MAX_ARGUMENT_SLOTS * UNITS_PER_WORD ) ) ; ) { offset += hfa_size ; args_byte_size += hfa_size ; fp_regs ++ ; } cum -> fp_regs = fp_regs ; } else if ( mode == TFmode || mode == TCmode || ( ! FLOAT_MODE_P ( mode ) || cum -> fp_regs == MAX_ARGUMENT_SLOTS ) ) cum -> int_regs = cum -> words ; else if ( cum -> prototype ) { if ( ! named ) cum -> int_regs = cum -> words ; else cum -> fp_regs += ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ? 2 : 1 ) ; } else { cum -> fp_regs += ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ? 2 : 1 ) ; cum -> int_regs = cum -> words ; } } </s>

Update CUM to point after this argument . This is patterned after ia64_function_arg .


"unknown register class in storeRegToStack"

Store the specified register of the given register class to the specified stack frame index .


<s> static section * iq2000_select_rtx_section ( machine_mode mode , rtx x ATTRIBUTE_UNUSED , unsigned HOST_WIDE_INT align ) { return mergeable_constant_section ( mode , align , 0 ) ; } </s>

Choose the section to use for the constant rtx expression X that has mode MODE .


<s> const ARMBaseRegisterInfo * getRegisterInfo ( ) const override { return getSubtargetImpl ( ) -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


"ARM Loops: Failed to find all loop components.\n"

Dump the plan to stderr ( for debugging ) .


<s>
int
SparcSubtarget
::
getAdjustedFrameSize
(
int
frameSize
)
const
{
if
(
is64Bit
(
)
)
{
frameSize
+=
128
;
assert
(
frameSize
%
16
==
0
&&
"Stack size not 16-byte aligned"
)
;
}
else
{
frameSize
+=
92
;
frameSize
=
RoundUpToAlignment
(
frameSize
,
8
)
;
}
return
frameSize
;
}
</s>

Given a actual stack size as determined by FrameInfo , this function returns adjusted framesize which includes space for RSA , return address , and frame poitner .


<s> void aarch64_sls_emit_shared_blr_thunks ( FILE * out_file ) { if ( ! aarch64_sls_shared_thunks_needed ) return ; for ( int regnum = 0 ; regnum < 30 ; ++ regnum ) { tree decl = aarch64_sls_shared_thunks [ regnum ] ; if ( ! decl ) continue ; const char * name = indirect_symbol_names [ regnum ] ; switch_to_section ( get_named_section ( decl , NULL , 0 ) ) ; ASM_OUTPUT_ALIGN ( out_file , 2 ) ; targetm . asm_out . globalize_label ( out_file , name ) ; targetm . asm_out . assemble_visibility ( decl , VISIBILITY_HIDDEN ) ; ASM_OUTPUT_TYPE_DIRECTIVE ( out_file , name , "function" ) ; ASM_OUTPUT_LABEL ( out_file , name ) ; aarch64_sls_emit_function_stub ( out_file , regnum ) ; asm_fprintf ( out_file , "\tdsb\tsy\n\tisb\n" ) ; ASM_DECLARE_FUNCTION_SIZE ( out_file , name , decl ) ; } } </s>

Emit shared BLR stubs for the current compilation unit . Over the course of compiling this unit we may have converted some BLR instructions to a BL to a shared stub function . This is where we emit those stub functions . This function is for the stubs shared between different functions in this compilation unit . We share when optimizing for size instead of speed . This function is called through the TARGET_ASM_FILE_END hook .


<s> static sbitmap aarch64_get_separate_components ( void ) { aarch64_layout_frame ( ) ; sbitmap components = sbitmap_alloc ( LAST_SAVED_REGNUM + 1 ) ; bitmap_clear ( components ) ; for ( unsigned regno = 0 ; regno <= LAST_SAVED_REGNUM ; regno ++ ) if ( aarch64_register_saved_on_entry ( regno ) ) { HOST_WIDE_INT offset = cfun -> machine -> frame . reg_offset [ regno ] ; if ( ! frame_pointer_needed ) offset += cfun -> machine -> frame . frame_size - cfun -> machine -> frame . hard_fp_offset ; if ( offset_12bit_unsigned_scaled_p ( DImode , offset ) ) bitmap_set_bit ( components , regno ) ; } if ( frame_pointer_needed ) bitmap_clear_bit ( components , HARD_FRAME_POINTER_REGNUM ) ; unsigned reg1 = cfun -> machine -> frame . wb_candidate1 ; unsigned reg2 = cfun -> machine -> frame . wb_candidate2 ; if ( reg2 != INVALID_REGNUM ) bitmap_clear_bit ( components , reg2 ) ; if ( reg1 != INVALID_REGNUM ) bitmap_clear_bit ( components , reg1 ) ; bitmap_clear_bit ( components , LR_REGNUM ) ; bitmap_clear_bit ( components , SP_REGNUM ) ; return components ; } </s>


<s> void MipsAsmBackend :: applyFixup ( const MCFixup & Fixup , MutableArrayRef < char > Data , uint64_t Value , bool IsPCRel , MCContext & Ctx ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( Fixup , Value , Ctx ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { case FK_Data_2 : case Mips :: fixup_Mips_16 : case Mips :: fixup_MICROMIPS_PC10_S1 : FullSize = 2 ; break ; case FK_Data_8 : case Mips :: fixup_Mips_64 : FullSize = 8 ; break ; case FK_Data_4 : default : FullSize = 4 ; break ; } uint64_t CurVal = 0 ; bool microMipsLEByteOrder = needsMMLEByteOrder ( ( unsigned ) Kind ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? ( microMipsLEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - 1 - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? ( microMipsLEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
{
switch
(
N
->
getOpcode
(
)
)
{
default
:
assert
(
0
&&
"Don't know how to custom expand this!"
)
;
return
;
case
ISD
::
BIT_CONVERT
:
Results
.
push_back
(
ExpandBIT_CONVERT
(
N
,
DAG
)
)
;
return
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
{
SDValue
Res
=
ExpandSRx
(
N
,
DAG
,
Subtarget
)
;
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
return
;
}
}
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

ARM
ARM
0
"Don't know how to custom expand this!"
ISD::BIT_CONVERT
ISD::SRL
ISD::SRA


<s> static rtx ix86_expand_sse_cmp ( rtx dest , enum rtx_code code , rtx cmp_op0 , rtx cmp_op1 , rtx op_true , rtx op_false ) { machine_mode mode = GET_MODE ( dest ) ; machine_mode cmp_ops_mode = GET_MODE ( cmp_op0 ) ; machine_mode cmp_mode ; bool maskcmp = false ; rtx x ; if ( ix86_use_mask_cmp_p ( mode , cmp_ops_mode , op_true , op_false ) ) { unsigned int nbits = GET_MODE_NUNITS ( cmp_ops_mode ) ; maskcmp = true ; cmp_mode = nbits > 8 ? int_mode_for_size ( nbits , 0 ) . require ( ) : E_QImode ; } else cmp_mode = cmp_ops_mode ; cmp_op0 = force_reg ( cmp_ops_mode , cmp_op0 ) ; bool ( * op1_predicate ) ( rtx , machine_mode ) = VECTOR_MODE_P ( cmp_ops_mode ) ? vector_operand : nonimmediate_operand ; if ( ! op1_predicate ( cmp_op1 , cmp_ops_mode ) ) cmp_op1 = force_reg ( cmp_ops_mode , cmp_op1 ) ; if ( optimize || ( maskcmp && cmp_mode != mode ) || ( op_true && reg_overlap_mentioned_p ( dest , op_true ) ) || ( op_false && reg_overlap_mentioned_p ( dest , op_false ) ) ) dest = gen_reg_rtx ( maskcmp ? cmp_mode : mode ) ; if ( maskcmp ) { bool ok = ix86_expand_mask_vec_cmp ( dest , code , cmp_op0 , cmp_op1 ) ; gcc_assert ( ok ) ; return dest ; } x = gen_rtx_fmt_ee ( code , cmp_mode , cmp_op0 , cmp_op1 ) ; if ( cmp_mode != mode ) { x = force_reg ( cmp_ops_mode , x ) ; convert_move ( dest , x , false ) ; } else emit_insn ( gen_rtx_SET ( dest , x ) ) ; return dest ; } </s>

Expand an sse vector comparison . Return the register with the result .


"Invalid number of NOP bytes requested!"

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> static rtx gen_inlined_tls_plt ( rtx addr ) { rtx retval , dest ; rtx picreg = get_hard_reg_initial_val ( Pmode , FDPIC_REG ) ; dest = gen_reg_rtx ( DImode ) ; if ( flag_pic == 1 ) { emit_insn ( gen_tls_lddi ( dest , addr , picreg ) ) ; } else { rtx reguse = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_tlsoff_hilo ( reguse , addr , GEN_INT ( R_FRV_GOTTLSDESCHI ) ) ) ; emit_insn ( gen_tls_tlsdesc_ldd ( dest , picreg , reguse , addr ) ) ; } retval = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_tls_indirect_call ( retval , addr , dest , picreg ) ) ; return retval ; } </s>

Given an ADDR , generate code to inline the PLT .


<s> const MCPhysReg * MSP430RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const TargetFrameLowering * TFI = MF -> getTarget ( ) . getFrameLowering ( ) ; const Function * F = MF -> getFunction ( ) ; static const MCPhysReg CalleeSavedRegs [ ] = { MSP430 :: FPW , MSP430 :: R5W , MSP430 :: R6W , MSP430 :: R7W , MSP430 :: R8W , MSP430 :: R9W , MSP430 :: R10W , MSP430 :: R11W , 0 } ; static const MCPhysReg CalleeSavedRegsFP [ ] = { MSP430 :: R5W , MSP430 :: R6W , MSP430 :: R7W , MSP430 :: R8W , MSP430 :: R9W , MSP430 :: R10W , MSP430 :: R11W , 0 } ; static const MCPhysReg CalleeSavedRegsIntr [ ] = { MSP430 :: FPW , MSP430 :: R5W , MSP430 :: R6W , MSP430 :: R7W , MSP430 :: R8W , MSP430 :: R9W , MSP430 :: R10W , MSP430 :: R11W , MSP430 :: R12W , MSP430 :: R13W , MSP430 :: R14W , MSP430 :: R15W , 0 } ; static const MCPhysReg CalleeSavedRegsIntrFP [ ] = { MSP430 :: R5W , MSP430 :: R6W , MSP430 :: R7W , MSP430 :: R8W , MSP430 :: R9W , MSP430 :: R10W , MSP430 :: R11W , MSP430 :: R12W , MSP430 :: R13W , MSP430 :: R14W , MSP430 :: R15W , 0 } ; if ( TFI -> hasFP ( * MF ) ) return ( F -> getCallingConv ( ) == CallingConv :: MSP430_INTR ? CalleeSavedRegsIntrFP : CalleeSavedRegsFP ) ; else return ( F -> getCallingConv ( ) == CallingConv :: MSP430_INTR ? CalleeSavedRegsIntr : CalleeSavedRegs ) ; } </s>


<s> StringRef getPassName ( ) const override { return X86_MACHINEINSTR_PRINTER_PASS_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s>
bool
SILoadStoreOptimizer
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
const
TargetSubtargetInfo
&
STM
=
MF
.
getSubtarget
(
)
;
TRI
=
static_cast
<
const
SIRegisterInfo
*
>
(
STM
.
getRegisterInfo
(
)
)
;
TII
=
static_cast
<
const
SIInstrInfo
*
>
(
STM
.
getInstrInfo
(
)
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
LIS
=
&
getAnalysis
<
LiveIntervals
>
(
)
;
DEBUG
(
dbgs
(
)
<<
"Running SILoadStoreOptimizer\n"
)
;
assert
(
!
MRI
->
isSSA
(
)
)
;
bool
Modified
=
false
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
Modified
|=
optimizeBlock
(
MBB
)
;
return
Modified
;
}
</s>

runOnMachineFunction - Emit the function body .

AMDGPU
SI
SI
SI
"Running SILoadStoreOptimizer\n"


<s> void function_expander :: add_ptrue_hint ( unsigned int argno , machine_mode pred_mode ) { rtx pred = gen_lowpart ( pred_mode , args [ argno ] ) ; int hint = ( pred == CONSTM1_RTX ( pred_mode ) ? SVE_KNOWN_PTRUE : SVE_MAYBE_NOT_PTRUE ) ; args . quick_insert ( argno + 1 , gen_int_mode ( hint , SImode ) ) ; } </s>

Add a dummy argument to indicate whether predicate argument ARGNO is all-true when interpreted in mode PRED_MODE . The hint goes immediately after ARGNO .


<s>
unsigned
NyuziInstrInfo
::
insertBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
TBB
,
MachineBasicBlock
*
FBB
,
ArrayRef
<
MachineOperand
>
Cond
,
const
DebugLoc
&
DL
,
int
*
BytesAdded
)
const
{
assert
(
TBB
)
;
assert
(
!
BytesAdded
&&
"code size not handled"
)
;
if
(
FBB
)
{
BuildMI
(
&
MBB
,
DL
,
get
(
Cond
[
0
]
.
getImm
(
)
)
)
.
add
(
Cond
[
1
]
)
.
addMBB
(
TBB
)
;
BuildMI
(
&
MBB
,
DL
,
get
(
Nyuzi
::
B
)
)
.
addMBB
(
FBB
)
;
return
2
;
}
if
(
Cond
.
empty
(
)
)
{
BuildMI
(
&
MBB
,
DL
,
get
(
Nyuzi
::
B
)
)
.
addMBB
(
TBB
)
;
return
1
;
}
BuildMI
(
&
MBB
,
DL
,
get
(
Cond
[
0
]
.
getImm
(
)
)
)
.
add
(
Cond
[
1
]
)
.
addMBB
(
TBB
)
;
return
1
;
}
</s>

Insert branch code into the end of the specified MachineBasicBlock .


" was Pass-through, is now Dirty-out.\n"


<s> void MipsRegisterBankInfo :: applyMappingImpl ( const OperandsMapper & OpdMapper ) const { MachineInstr & MI = OpdMapper . getMI ( ) ; InstListTy NewInstrs ; MachineIRBuilder B ( MI ) ; MachineFunction * MF = MI . getMF ( ) ; MachineRegisterInfo & MRI = OpdMapper . getMRI ( ) ; const LegalizerInfo & LegInfo = * MF -> getSubtarget ( ) . getLegalizerInfo ( ) ; InstManager NewInstrObserver ( NewInstrs ) ; GISelObserverWrapper WrapperObserver ( & NewInstrObserver ) ; LegalizerHelper Helper ( * MF , WrapperObserver , B ) ; LegalizationArtifactCombiner ArtCombiner ( B , MF -> getRegInfo ( ) , LegInfo ) ; switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_LOAD : case TargetOpcode :: G_STORE : case TargetOpcode :: G_PHI : case TargetOpcode :: G_SELECT : case TargetOpcode :: G_IMPLICIT_DEF : { Helper . narrowScalar ( MI , 0 , LLT :: scalar ( 32 ) ) ; while ( ! NewInstrs . empty ( ) ) { MachineInstr * NewMI = NewInstrs . pop_back_val ( ) ; if ( NewMI -> getOpcode ( ) == TargetOpcode :: G_UNMERGE_VALUES ) combineAwayG_UNMERGE_VALUES ( ArtCombiner , * NewMI ) ; else if ( NewMI -> getOpcode ( ) == TargetOpcode :: G_MERGE_VALUES ) continue ; else setRegBank ( * NewMI , MRI ) ; } return ; } case TargetOpcode :: G_UNMERGE_VALUES : combineAwayG_UNMERGE_VALUES ( ArtCombiner , MI ) ; return ; default : break ; } return applyDefaultMapping ( OpdMapper ) ; } </s>


Emit target-specific code that performs a memcpy .


<s> SchedBoundary ( unsigned ID , const Twine & Name ) : DAG ( 0 ) , SchedModel ( 0 ) , Available ( ID , Name + ".A" ) , Pending ( ID << ConvergingVLIWScheduler :: LogMaxQID , Name + ".P" ) , CheckPending ( false ) , HazardRec ( 0 ) , ResourceModel ( 0 ) , CurrCycle ( 0 ) , IssueCount ( 0 ) , MinReadyCycle ( UINT_MAX ) , MaxMinLatency ( 0 ) { } </s>

Pending queues extend the ready queues with the same ID and the PendingFlag set .


<s> void RISCVFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const RISCVRegisterInfo * RI = STI . getRegisterInfo ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; uint64_t StackAlign = RI -> needsStackRealignment ( MF ) ? MFI . getMaxAlignment ( ) : getStackAlignment ( ) ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI . setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


"%s instructions aren't allowed in %s service routine"

"%s instructions aren't allowed in function with "

Establish appropriate back-end context for processing the function FNDECL . The argument might be NULL to indicate processing at top level , outside of any function scope .


<s> const TargetRegisterClass * getLargestLegalSuperClass ( const TargetRegisterClass * RC ) const override { if ( RC == & AArch64 :: tcGPR64RegClass ) return & AArch64 :: GPR64RegClass ; return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .


<s>
int
MipsRegisterInfo
::
getDwarfRegNum
(
unsigned
RegNum
,
bool
isEH
)
const
{
llvm_unreachable
(
"What is the dwarf register number"
)
;
return
1
;
}
</s>

Map a target register to an equivalent dwarf register number .

Mips
Mips
"What is the dwarf register number"
1


<s> static int ix86_fp_comparison_sahf_cost ( enum rtx_code code ) { enum rtx_code bypass_code , first_code , second_code ; if ( ! TARGET_USE_SAHF && ! optimize_size ) return 1024 ; ix86_fp_comparison_codes ( code , & bypass_code , & first_code , & second_code ) ; return ( bypass_code != UNKNOWN || second_code != UNKNOWN ) + 3 ; } </s>

Return cost of comparison done using sahf operation . See ix86_fp_comparison_arithmetics_cost for the metrics .


"-target-abi option != target-abi module flag"

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool hasFPU ( ) const { return HasFPU ; } </s>


<s> unsigned MipsTargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , EVT VT ) const { if ( VT . isVector ( ) ) return std :: max ( ( VT . getSizeInBits ( ) / ( Subtarget . isABI_O32 ( ) ? 32 : 64 ) ) , 1U ) ; return MipsTargetLowering :: getNumRegisters ( Context , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s>
CCAssignFn
*
R600TargetLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
const
{
switch
(
CC
)
{
case
CallingConv
::
AMDGPU_KERNEL
:
case
CallingConv
::
SPIR_KERNEL
:
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
case
CallingConv
::
Cold
:
llvm_unreachable
(
"kernels should not be handled here"
)
;
case
CallingConv
::
AMDGPU_VS
:
case
CallingConv
::
AMDGPU_GS
:
case
CallingConv
::
AMDGPU_PS
:
case
CallingConv
::
AMDGPU_CS
:
case
CallingConv
::
AMDGPU_HS
:
case
CallingConv
::
AMDGPU_ES
:
case
CallingConv
::
AMDGPU_LS
:
return
CC_R600
;
default
:
report_fatal_error
(
"Unsupported calling convention."
)
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .

AMDGPU
R600
AMDGPU
"kernels should not be handled here"
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
R600
"Unsupported calling convention."


"invalid instruction when using jump guards!"

Perform target-specific instruction verification .


For the element-reversing load/store built-ins , produce the correct insn_code depending on the target endianness .


Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calling convention CallConv .


<s> static bool expand_vec_perm_1 ( struct expand_vec_perm_d * d ) { unsigned i , nelt = d -> nelt ; unsigned char perm2 [ MAX_VECT_LEN ] ; if ( d -> one_operand_p ) { if ( expand_vec_perm_identity ( d ) ) return true ; if ( expand_vselect ( d -> target , d -> op0 , d -> perm , nelt ) ) return true ; } if ( expand_vselect_vconcat ( d -> target , d -> op0 , d -> op1 , d -> perm , nelt ) ) return true ; if ( ! d -> one_operand_p ) { for ( i = 0 ; i < nelt ; ++ i ) { unsigned e = d -> perm [ i ] ; if ( e >= nelt ) e -= nelt ; else e += nelt ; perm2 [ i ] = e ; } if ( expand_vselect_vconcat ( d -> target , d -> op1 , d -> op0 , perm2 , nelt ) ) return true ; } if ( expand_vec_perm_shrp ( d ) ) return true ; return false ; } </s>

Try to instantiate D in a single instruction .


<s> unsigned AArch64RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const AArch64FrameLowering * TFI = getFrameLowering ( MF ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case AArch64 :: GPR32RegClassID : case AArch64 :: GPR32spRegClassID : case AArch64 :: GPR32allRegClassID : case AArch64 :: GPR64spRegClassID : case AArch64 :: GPR64allRegClassID : case AArch64 :: GPR64RegClassID : case AArch64 :: GPR32commonRegClassID : case AArch64 :: GPR64commonRegClassID : return 32 - 1 - ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) - MF . getSubtarget < AArch64Subtarget > ( ) . getNumXRegisterReserved ( ) - hasBasePointer ( MF ) - MF . getFunction ( ) . isPagerando ( ) ; case AArch64 :: FPR8RegClassID : case AArch64 :: FPR16RegClassID : case AArch64 :: FPR32RegClassID : case AArch64 :: FPR64RegClassID : case AArch64 :: FPR128RegClassID : return 32 ; case AArch64 :: DDRegClassID : case AArch64 :: DDDRegClassID : case AArch64 :: DDDDRegClassID : case AArch64 :: QQRegClassID : case AArch64 :: QQQRegClassID : case AArch64 :: QQQQRegClassID : return 32 ; case AArch64 :: FPR128_loRegClassID : return 16 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == 0 ) Inst . addOperand ( MCOperand :: CreateImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ; } </s>


<s>
bool
PPCAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
{
if
(
ExtraCode
[
1
]
!=
0
)
return
true
;
switch
(
ExtraCode
[
0
]
)
{
default
:
return
true
;
case
'y'
:
{
const
char
*
RegName
=
"r0"
;
if
(
!
Subtarget
.
isDarwin
(
)
)
RegName
=
stripRegisterPrefix
(
RegName
)
;
O
<<
RegName
<<
", "
;
printOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
}
}
}
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
O
<<
"0("
;
printOperand
(
MI
,
OpNo
,
O
)
;
O
<<
")"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> static void ix86_output_indirect_branch_via_reg ( rtx call_op , bool sibcall_p ) { char thunk_name_buf [ 32 ] ; char * thunk_name ; enum indirect_thunk_prefix need_prefix = indirect_thunk_need_prefix ( current_output_insn ) ; int regno = REGNO ( call_op ) ; if ( cfun -> machine -> indirect_branch_type != indirect_branch_thunk_inline ) { if ( cfun -> machine -> indirect_branch_type == indirect_branch_thunk ) { int i = regno ; if ( i >= FIRST_REX_INT_REG ) i -= ( FIRST_REX_INT_REG - LAST_INT_REG - 1 ) ; indirect_thunks_used |= 1 << i ; } indirect_thunk_name ( thunk_name_buf , regno , need_prefix , false ) ; thunk_name = thunk_name_buf ; } else thunk_name = NULL ; if ( sibcall_p ) { if ( thunk_name != NULL ) fprintf ( asm_out_file , "\tjmp\t%s\n" , thunk_name ) ; else output_indirect_thunk ( regno ) ; } else { if ( thunk_name != NULL ) { fprintf ( asm_out_file , "\tcall\t%s\n" , thunk_name ) ; return ; } char indirectlabel1 [ 32 ] ; char indirectlabel2 [ 32 ] ; ASM_GENERATE_INTERNAL_LABEL ( indirectlabel1 , INDIRECT_LABEL , indirectlabelno ++ ) ; ASM_GENERATE_INTERNAL_LABEL ( indirectlabel2 , INDIRECT_LABEL , indirectlabelno ++ ) ; fputs ( "\tjmp\t" , asm_out_file ) ; assemble_name_raw ( asm_out_file , indirectlabel2 ) ; fputc ( '\n' , asm_out_file ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , indirectlabel1 ) ; if ( thunk_name != NULL ) fprintf ( asm_out_file , "\tjmp\t%s\n" , thunk_name ) ; else output_indirect_thunk ( regno ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , indirectlabel2 ) ; fputs ( "\tcall\t" , asm_out_file ) ; assemble_name_raw ( asm_out_file , indirectlabel1 ) ; fputc ( '\n' , asm_out_file ) ; } } </s>

Output indirect branch via a call and return thunk . CALL_OP is a register which contains the branch target . XASM is the assembly template for CALL_OP . Branch is a tail call if SIBCALL_P is true . A normal call is converted to : call __x86_indirect_thunk_reg and a tail call is converted to : jmp __x86_indirect_thunk_reg


<s> unsigned PPCTTI :: getNumberOfRegisters ( bool Vector ) const { if ( Vector && ! ST -> hasAltivec ( ) ) return 0 ; return ST -> hasVSX ( ) ? 64 : 32 ; } </s>


<s> static bool mips_mode_ok_for_mov_fmt_p ( machine_mode mode ) { switch ( mode ) { case CCFmode : case SFmode : return TARGET_HARD_FLOAT ; case DFmode : return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT ; case V2SFmode : return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT ; default : return MSA_SUPPORTED_MODE_P ( mode ) ; } } </s>

Return true if moves in mode MODE can use the FPU 's mov.fmt instruction .


<s> static int rs6000_issue_rate ( void ) { if ( ! reload_completed && ! flag_sched_pressure ) return 1 ; switch ( rs6000_cpu_attr ) { case CPU_RS64A : case CPU_PPC601 : case CPU_PPC7450 : return 3 ; case CPU_PPC440 : case CPU_PPC603 : case CPU_PPC750 : case CPU_PPC7400 : case CPU_PPC8540 : case CPU_PPC8548 : case CPU_CELL : case CPU_PPCE300C2 : case CPU_PPCE300C3 : case CPU_PPCE500MC : case CPU_PPCE500MC64 : case CPU_PPCE5500 : case CPU_PPCE6500 : case CPU_TITAN : return 2 ; case CPU_PPC476 : case CPU_PPC604 : case CPU_PPC604E : case CPU_PPC620 : case CPU_PPC630 : return 4 ; case CPU_POWER4 : case CPU_POWER5 : case CPU_POWER6 : case CPU_POWER7 : return 5 ; case CPU_POWER8 : return 7 ; case CPU_POWER9 : return 6 ; default : return 1 ; } } </s>

Return how many instructions the machine can issue per cycle .


<s> const XCoreSubtarget * getSubtargetImpl ( ) const override { return & Subtarget ; } </s>


<s> void ix86_expand_convert_sign_didf_sse ( rtx target , rtx input ) { REAL_VALUE_TYPE TWO32r ; rtx fp_lo , fp_hi , x ; fp_lo = gen_reg_rtx ( DFmode ) ; fp_hi = gen_reg_rtx ( DFmode ) ; emit_insn ( gen_floatsidf2 ( fp_hi , gen_highpart ( SImode , input ) ) ) ; real_ldexp ( & TWO32r , & dconst1 , 32 ) ; x = const_double_from_real_value ( TWO32r , DFmode ) ; fp_hi = expand_simple_binop ( DFmode , MULT , fp_hi , x , fp_hi , 0 , OPTAB_DIRECT ) ; ix86_expand_convert_uns_sidf_sse ( fp_lo , gen_lowpart ( SImode , input ) ) ; x = expand_simple_binop ( DFmode , PLUS , fp_hi , fp_lo , target , 0 , OPTAB_DIRECT ) ; if ( x != target ) emit_move_insn ( target , x ) ; } </s>

Convert a signed DImode value into a DFmode . Only used for SSE in 32-bit mode ; otherwise we have a direct convert instruction .


<s> unsigned char X86Subtarget :: classifyGlobalFunctionReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return X86II :: MO_NO_FLAG ; assert ( ! isTargetCOFF ( ) ) ; if ( isTargetELF ( ) ) return X86II :: MO_PLT ; if ( is64Bit ( ) ) { auto * F = dyn_cast_or_null < Function > ( GV ) ; if ( F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) ) return X86II :: MO_GOTPCREL ; return X86II :: MO_NO_FLAG ; } return X86II :: MO_NO_FLAG ; } </s>

Classify a global function reference for the current subtarget .


<s> bool X86TargetLowering :: isBinOp ( unsigned Opcode ) const { switch ( Opcode ) { case X86ISD :: PMULUDQ : case X86ISD :: FMAX : case X86ISD :: FMIN : case X86ISD :: FMAXC : case X86ISD :: FMINC : case X86ISD :: FAND : case X86ISD :: FANDN : case X86ISD :: FOR : case X86ISD :: FXOR : return true ; } return TargetLoweringBase :: isBinOp ( Opcode ) ; } </s>

Add x86-specific opcodes to the default list .


<s> bool HexagonExpandCondsets :: isPredicable ( MachineInstr * MI ) { if ( HII -> isPredicated ( MI ) || ! HII -> isPredicable ( MI ) ) return false ; if ( MI -> hasUnmodeledSideEffects ( ) || MI -> mayStore ( ) ) return false ; bool HasDef = false ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) ) continue ; if ( HasDef ) return false ; HasDef = true ; } for ( auto & Mo : MI -> memoperands ( ) ) if ( Mo -> isVolatile ( ) ) return false ; return true ; } </s>

Return true if the specified instruction can be predicated .


";; loop %d start_label not before loop_end\n"

A callback for the hw-doloop pass . Called to optimize LOOP in a machine-specific fashion ; returns true if successful and false if the hwloop_fail function should be called .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> Value * X86TargetLowering :: getSafeStackPointerLocation ( IRBuilder < > & IRB ) const { if ( ! Subtarget . isTargetAndroid ( ) ) return TargetLowering :: getSafeStackPointerLocation ( IRB ) ; unsigned AddressSpace , Offset ; Offset = ( Subtarget . is64Bit ( ) ) ? 0x48 : 0x24 ; AddressSpace = getAddressSpace ( ) ; return ConstantExpr :: getIntToPtr ( ConstantInt :: get ( Type :: getInt32Ty ( IRB . getContext ( ) ) , Offset ) , Type :: getInt8PtrTy ( IRB . getContext ( ) ) -> getPointerTo ( AddressSpace ) ) ; } </s>

Return true if the target stores SafeStack pointer at a fixed offset in some non-standard address space , and populates the address space and offset as appropriate .


<s>
bool
SIFoldOperands
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
const
SIInstrInfo
*
TII
=
static_cast
<
const
SIInstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
const
SIRegisterInfo
&
TRI
=
TII
->
getRegisterInfo
(
)
;
for
(
MachineFunction
::
iterator
BI
=
MF
.
begin
(
)
,
BE
=
MF
.
end
(
)
;
BI
!=
BE
;
++
BI
)
{
MachineBasicBlock
&
MBB
=
*
BI
;
MachineBasicBlock
::
iterator
I
,
Next
;
for
(
I
=
MBB
.
begin
(
)
;
I
!=
MBB
.
end
(
)
;
I
=
Next
)
{
Next
=
std
::
next
(
I
)
;
MachineInstr
&
MI
=
*
I
;
if
(
!
isSafeToFold
(
MI
.
getOpcode
(
)
)
)
continue
;
unsigned
OpSize
=
TII
->
getOpSize
(
MI
,
1
)
;
MachineOperand
&
OpToFold
=
MI
.
getOperand
(
1
)
;
bool
FoldingImm
=
OpToFold
.
isImm
(
)
;
if
(
!
FoldingImm
&&
!
OpToFold
.
isReg
(
)
)
continue
;
if
(
FoldingImm
&&
!
TII
->
isInlineConstant
(
OpToFold
,
OpSize
)
&&
!
MRI
.
hasOneUse
(
MI
.
getOperand
(
0
)
.
getReg
(
)
)
)
continue
;
if
(
OpToFold
.
isReg
(
)
&&
!
TargetRegisterInfo
::
isVirtualRegister
(
OpToFold
.
getReg
(
)
)
)
continue
;
MachineOperand
&
Dst
=
MI
.
getOperand
(
0
)
;
if
(
Dst
.
isReg
(
)
&&
!
TargetRegisterInfo
::
isVirtualRegister
(
Dst
.
getReg
(
)
)
)
continue
;
SmallVector
<
MachineInstr
*
,
4
>
CopiesToReplace
;
std
::
vector
<
FoldCandidate
>
FoldList
;
for
(
MachineRegisterInfo
::
use_iterator
Use
=
MRI
.
use_begin
(
MI
.
getOperand
(
0
)
.
getReg
(
)
)
,
E
=
MRI
.
use_end
(
)
;
Use
!=
E
;
++
Use
)
{
MachineInstr
*
UseMI
=
Use
->
getParent
(
)
;
foldOperand
(
OpToFold
,
UseMI
,
Use
.
getOperandNo
(
)
,
FoldList
,
CopiesToReplace
,
TII
,
TRI
,
MRI
)
;
}
for
(
MachineInstr
*
Copy
:
CopiesToReplace
)
Copy
->
addImplicitDefUseOperands
(
MF
)
;
for
(
FoldCandidate
&
Fold
:
FoldList
)
{
if
(
updateOperand
(
Fold
,
TRI
)
)
{
if
(
!
Fold
.
isImm
(
)
)
{
assert
(
Fold
.
OpToFold
&&
Fold
.
OpToFold
->
isReg
(
)
)
;
MRI
.
clearKillFlags
(
Fold
.
OpToFold
->
getReg
(
)
)
;
}
DEBUG
(
dbgs
(
)
<<
"Folded source from "
<<
MI
<<
" into OpNo "
<<
Fold
.
UseOpNo
<<
" of "
<<
*
Fold
.
UseMI
<<
'\n'
)
;
}
}
}
}
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const override { bool is64 = getPointerSize ( ) == 8 ; return createPPCELFObjectWriter ( OS , is64 , isLittleEndian ( ) , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> void AMDGPUTTI :: getUnrollingPreferences ( Loop * L , UnrollingPreferences & UP ) const { for ( const BasicBlock * BB : L -> getBlocks ( ) ) { for ( const Instruction & I : * BB ) { const GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( & I ) ; if ( ! GEP || GEP -> getAddressSpace ( ) != AMDGPUAS :: PRIVATE_ADDRESS ) continue ; const Value * Ptr = GEP -> getPointerOperand ( ) ; const AllocaInst * Alloca = dyn_cast < AllocaInst > ( GetUnderlyingObject ( Ptr ) ) ; if ( Alloca ) { UP . Threshold = 500 ; } } } } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s>
void
s390_function_profiler
(
FILE
*
file
,
int
labelno
)
{
rtx
op
[
7
]
;
char
label
[
128
]
;
ASM_GENERATE_INTERNAL_LABEL
(
label
,
"LP"
,
labelno
)
;
fprintf
(
file
,
"# function profiler \n"
)
;
op
[
0
]
=
gen_rtx_REG
(
Pmode
,
RETURN_REGNUM
)
;
op
[
1
]
=
gen_rtx_REG
(
Pmode
,
STACK_POINTER_REGNUM
)
;
op
[
1
]
=
gen_rtx_MEM
(
Pmode
,
plus_constant
(
op
[
1
]
,
UNITS_PER_WORD
)
)
;
op
[
2
]
=
gen_rtx_REG
(
Pmode
,
1
)
;
op
[
3
]
=
gen_rtx_SYMBOL_REF
(
Pmode
,
label
)
;
SYMBOL_REF_FLAGS
(
op
[
3
]
)
=
SYMBOL_FLAG_LOCAL
;
op
[
4
]
=
gen_rtx_SYMBOL_REF
(
Pmode
,
"_mcount"
)
;
if
(
flag_pic
)
{
op
[
4
]
=
gen_rtx_UNSPEC
(
Pmode
,
gen_rtvec
(
1
,
op
[
4
]
)
,
UNSPEC_PLT
)
;
op
[
4
]
=
gen_rtx_CONST
(
Pmode
,
op
[
4
]
)
;
}
if
(
TARGET_64BIT
)
{
output_asm_insn
(
"stg\t%0,%1"
,
op
)
;
output_asm_insn
(
"larl\t%2,%3"
,
op
)
;
output_asm_insn
(
"brasl\t%0,%4"
,
op
)
;
output_asm_insn
(
"lg\t%0,%1"
,
op
)
;
}
else
if
(
!
flag_pic
)
{
op
[
6
]
=
gen_label_rtx
(
)
;
output_asm_insn
(
"st\t%0,%1"
,
op
)
;
output_asm_insn
(
"bras\t%2,%l6"
,
op
)
;
output_asm_insn
(
".long\t%4"
,
op
)
;
output_asm_insn
(
".long\t%3"
,
op
)
;
targetm
.
asm_out
.
internal_label
(
file
,
"L"
,
CODE_LABEL_NUMBER
(
op
[
6
]
)
)
;
output_asm_insn
(
"l\t%0,0(%2)"
,
op
)
;
output_asm_insn
(
"l\t%2,4(%2)"
,
op
)
;
output_asm_insn
(
"basr\t%0,%0"
,
op
)
;
output_asm_insn
(
"l\t%0,%1"
,
op
)
;
}
else
{
op
[
5
]
=
gen_label_rtx
(
)
;
op
[
6
]
=
gen_label_rtx
(
)
;
output_asm_insn
(
"st\t%0,%1"
,
op
)
;
output_asm_insn
(
"bras\t%2,%l6"
,
op
)
;
targetm
.
asm_out
.
internal_label
(
file
,
"L"
,
CODE_LABEL_NUMBER
(
op
[
5
]
)
)
;
output_asm_insn
(
".long\t%4-%l5"
,
op
)
;
output_asm_insn
(
".long\t%3-%l5"
,
op
)
;
targetm
.
asm_out
.
internal_label
(
file
,
"L"
,
CODE_LABEL_NUMBER
(
op
[
6
]
)
)
;
output_asm_insn
(
"lr\t%0,%2"
,
op
)
;
output_asm_insn
(
"a\t%0,0(%2)"
,
op
)
;
output_asm_insn
(
"a\t%2,4(%2)"
,
op
)
;
output_asm_insn
(
"basr\t%0,%0"
,
op
)
;
output_asm_insn
(
"l\t%0,%1"
,
op
)
;
}
}
</s>

Output assembler code to FILE to call a profiler hook .


<s> void LanaiAsmBackend :: applyFixup ( const MCFixup & Fixup , MutableArrayRef < char > Data , uint64_t Value , bool , MCContext & ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( static_cast < unsigned > ( Kind ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize = 4 ; uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; CurVal |= static_cast < uint64_t > ( static_cast < uint8_t > ( Data [ Offset + Idx ] ) ) << ( i * 8 ) ; } uint64_t Mask = ( static_cast < uint64_t > ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = static_cast < uint8_t > ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool x86_extended_reg_mentioned_p ( rtx insn ) { subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , INSN_P ( insn ) ? PATTERN ( insn ) : insn , NONCONST ) { const_rtx x = * iter ; if ( REG_P ( x ) && ( REX_INT_REGNO_P ( REGNO ( x ) ) || REX_SSE_REGNO_P ( REGNO ( x ) ) ) ) return true ; } return false ; } </s>

Return true when INSN mentions register that must be encoded using REX prefix .


This method may be implemented by targets that want to run passes immediately before register allocation .


<s> const SystemZSubtarget * getSubtargetImpl ( ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> void ARMPassConfig :: addIRPasses ( ) { if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( SimplifyCFGOptions ( ) . hoistCommonInsts ( true ) . sinkCommonInsts ( true ) , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < ARMSubtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST . isThumb1Only ( ) ; } ) ) ; addPass ( createMVEGatherScatterLoweringPass ( ) ) ; addPass ( createMVELaneInterleavingPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( createARMParallelDSPPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardCheckPass ( ) ) ; if ( TM -> Options . JMCInstrument ) addPass ( createJMCInstrumenterPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> unsigned getNumFixupKinds ( ) const override { return ARM64 :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
InfosBE
[
PPC
::
NumTargetFixupKinds
]
=
{
{
"fixup_ppc_br24"
,
6
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_brcond14"
,
16
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_br24abs"
,
6
,
24
,
0
}
,
{
"fixup_ppc_brcond14abs"
,
16
,
14
,
0
}
,
{
"fixup_ppc_half16"
,
0
,
16
,
0
}
,
{
"fixup_ppc_half16ds"
,
0
,
14
,
0
}
,
{
"fixup_ppc_nofixup"
,
0
,
0
,
0
}
}
;
const
static
MCFixupKindInfo
InfosLE
[
PPC
::
NumTargetFixupKinds
]
=
{
{
"fixup_ppc_br24"
,
2
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_brcond14"
,
2
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_br24abs"
,
2
,
24
,
0
}
,
{
"fixup_ppc_brcond14abs"
,
2
,
14
,
0
}
,
{
"fixup_ppc_half16"
,
0
,
16
,
0
}
,
{
"fixup_ppc_half16ds"
,
2
,
14
,
0
}
,
{
"fixup_ppc_nofixup"
,
0
,
0
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
(
IsLittleEndian
InfosLE
:
InfosBE
)
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> void validate_condition_mode ( enum rtx_code code , machine_mode mode ) { gcc_assert ( ( GET_RTX_CLASS ( code ) == RTX_COMPARE || GET_RTX_CLASS ( code ) == RTX_COMM_COMPARE ) && GET_MODE_CLASS ( mode ) == MODE_CC ) ; gcc_assert ( ( code != GT && code != LT && code != GE && code != LE ) || mode != CCUNSmode ) ; gcc_assert ( ( code != GTU && code != LTU && code != GEU && code != LEU ) || mode == CCUNSmode ) ; gcc_assert ( mode == CCFPmode || ( code != ORDERED && code != UNORDERED && code != UNEQ && code != LTGT && code != UNGT && code != UNLT && code != UNGE && code != UNLE ) ) ; gcc_assert ( mode != CCFPmode || flag_finite_math_only || ( code != LE && code != GE && code != UNEQ && code != LTGT && code != UNGT && code != UNLT ) ) ; gcc_assert ( mode != CCEQmode || code == EQ || code == NE ) ; } </s>

A validation routine : say whether CODE , a condition code , and MODE match . The other alternatives either do n't make sense or should never be generated .


<s> void aarch64_simd_emit_reg_reg_move ( rtx * operands , machine_mode mode , unsigned int count ) { unsigned int i ; int rdest = REGNO ( operands [ 0 ] ) ; int rsrc = REGNO ( operands [ 1 ] ) ; if ( ! reg_overlap_mentioned_p ( operands [ 0 ] , operands [ 1 ] ) || rdest < rsrc ) for ( i = 0 ; i < count ; i ++ ) emit_move_insn ( gen_rtx_REG ( mode , rdest + i ) , gen_rtx_REG ( mode , rsrc + i ) ) ; else for ( i = 0 ; i < count ; i ++ ) emit_move_insn ( gen_rtx_REG ( mode , rdest + count - i - 1 ) , gen_rtx_REG ( mode , rsrc + count - i - 1 ) ) ; } </s>

Emit a register copy from operand to operand , taking care not to early-clobber source registers in the process . COUNT is the number of components into which the copy needs to be decomposed .


<s> unsigned PPCInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case PPC :: STD : case PPC :: STW : case PPC :: STFS : case PPC :: STFD : case PPC :: SPILL_CR : case PPC :: SPILL_CRBIT : case PPC :: STVX : case PPC :: STXVD2X : case PPC :: QVSTFDX : case PPC :: QVSTFSXs : case PPC :: QVSTFDXb : case PPC :: SPILL_VRSAVE : if ( MI . getOperand ( 1 ) . isImm ( ) && ! MI . getOperand ( 1 ) . getImm ( ) && MI . getOperand ( 2 ) . isFI ( ) ) { FrameIndex = MI . getOperand ( 2 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> SDValue AVRTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; if ( CallConv == CallingConv :: AVR_BUILTIN ) { CCInfo . AnalyzeCallResult ( Ins , RetCC_AVR_BUILTIN ) ; } else { analyzeReturnValues ( Ins , CCInfo ) ; } for ( CCValAssign const & RVLoc : RVLocs ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLoc . getLocReg ( ) , RVLoc . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


"All AArch64 cmps should have 2 operands"

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> unsigned CSKYAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { CSKYOperand & Op = static_cast < CSKYOperand & > ( AsmOp ) ; if ( ! Op . isReg ( ) ) return Match_InvalidOperand ; MCRegister Reg = Op . getReg ( ) ; if ( CSKYMCRegisterClasses [ CSKY :: FPR32RegClassID ] . contains ( Reg ) ) { if ( Kind == MCK_FPR64 || Kind == MCK_sFPR64 ) { Op . Reg . RegNum = convertFPR32ToFPR64 ( Reg ) ; if ( Kind == MCK_sFPR64 && ( Op . Reg . RegNum < CSKY :: F0_64 || Op . Reg . RegNum > CSKY :: F15_64 ) ) return Match_InvalidRegOutOfRange ; if ( Kind == MCK_FPR64 && ( Op . Reg . RegNum < CSKY :: F0_64 || Op . Reg . RegNum > CSKY :: F31_64 ) ) return Match_InvalidRegOutOfRange ; return Match_Success ; } } if ( CSKYMCRegisterClasses [ CSKY :: GPRRegClassID ] . contains ( Reg ) ) { if ( Kind == MCK_GPRPair ) { Op . Reg . RegNum = MRI -> getEncodingValue ( Reg ) + CSKY :: R0_R1 ; return Match_Success ; } } return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s>
static
int
arm_comp_type_attributes
(
const_tree
type1
,
const_tree
type2
)
{
int
l1
,
l2
,
s1
,
s2
;
tree
attrs1
=
lookup_attribute
(
"Advanced SIMD type"
,
TYPE_ATTRIBUTES
(
type1
)
)
;
tree
attrs2
=
lookup_attribute
(
"Advanced SIMD type"
,
TYPE_ATTRIBUTES
(
type2
)
)
;
if
(
bool
(
attrs1
)
!=
bool
(
attrs2
)
)
return
0
;
if
(
attrs1
&&
!
attribute_value_equal
(
attrs1
,
attrs2
)
)
return
0
;
if
(
TREE_CODE
(
type1
)
!=
FUNCTION_TYPE
)
return
1
;
l1
=
lookup_attribute
(
"long_call"
,
TYPE_ATTRIBUTES
(
type1
)
)
!=
;
l2
=
lookup_attribute
(
"long_call"
,
TYPE_ATTRIBUTES
(
type2
)
)
!=
;
s1
=
lookup_attribute
(
"short_call"
,
TYPE_ATTRIBUTES
(
type1
)
)
!=
;
s2
=
lookup_attribute
(
"short_call"
,
TYPE_ATTRIBUTES
(
type2
)
)
!=
;
if
(
l1
|
l2
|
s1
|
s2
)
{
if
(
(
l1
!=
l2
)
||
(
s1
!=
s2
)
)
return
0
;
if
(
(
l1
&
s2
)
||
(
l2
&
s1
)
)
return
0
;
}
l1
=
lookup_attribute
(
"isr"
,
TYPE_ATTRIBUTES
(
type1
)
)
!=
;
if
(
!
l1
)
l1
=
lookup_attribute
(
"interrupt"
,
TYPE_ATTRIBUTES
(
type1
)
)
!=
;
l2
=
lookup_attribute
(
"isr"
,
TYPE_ATTRIBUTES
(
type2
)
)
!=
;
if
(
!
l2
)
l1
=
lookup_attribute
(
"interrupt"
,
TYPE_ATTRIBUTES
(
type2
)
)
!=
;
if
(
l1
!=
l2
)
return
0
;
l1
=
lookup_attribute
(
"cmse_nonsecure_call"
,
TYPE_ATTRIBUTES
(
type1
)
)
!=
;
l2
=
lookup_attribute
(
"cmse_nonsecure_call"
,
TYPE_ATTRIBUTES
(
type2
)
)
!=
;
if
(
l1
!=
l2
)
return
0
;
return
1
;
}
</s>

Return 0 if the attributes for two types are incompatible , 1 if they are compatible , and 2 if they are nearly compatible ( which causes a warning to be generated ) .


<s> static const predefined_function_abi & aarch64_fntype_abi ( const_tree fntype ) { if ( lookup_attribute ( "aarch64_vector_pcs" , TYPE_ATTRIBUTES ( fntype ) ) ) return aarch64_simd_abi ( ) ; if ( aarch64_returns_value_in_sve_regs_p ( fntype ) || aarch64_takes_arguments_in_sve_regs_p ( fntype ) ) return aarch64_sve_abi ( ) ; return default_function_abi ; } </s>


<s> bool aarch64_pad_reg_upward ( machine_mode mode , const_tree type , bool first ATTRIBUTE_UNUSED ) { if ( BYTES_BIG_ENDIAN && aarch64_composite_type_p ( type , mode ) ) { HOST_WIDE_INT size ; if ( type ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) . to_constant ( ) ; if ( size < 2 * UNITS_PER_WORD ) return true ; } return ! BYTES_BIG_ENDIAN ; } </s>

Similarly , for use by BLOCK_REG_PADDING ( MODE , TYPE , FIRST ) . It specifies padding for the last ( may also be the only ) element of a block move between registers and memory . If assuming the block is in the memory , padding upward means that the last element is padded after its highest significant byte , while in downward padding , the last element is padded at the its least significant byte side . Small aggregates and small complex types are always padded upwards . We do n't need to worry about homogeneous floating-point or short-vector aggregates ; their move is not affected by the padding direction determined here . Regardless of endianness , each element of such an aggregate is put in the least significant bits of a fp/simd register . Return ! BYTES_BIG_ENDIAN if the least significant byte of the register has useful data , and return the opposite if the most significant byte does .


<s> static int thumb2_legitimate_address_p ( machine_mode mode , rtx x , int strict_p ) { bool use_ldrd ; enum rtx_code code = GET_CODE ( x ) ; if ( arm_address_register_rtx_p ( x , strict_p ) ) return 1 ; use_ldrd = ( TARGET_LDRD && ( mode == DImode || ( mode == DFmode && ( TARGET_SOFT_FLOAT || TARGET_VFP ) ) ) ) ; if ( code == POST_INC || code == PRE_DEC || ( ( code == PRE_INC || code == POST_DEC ) && ( use_ldrd || GET_MODE_SIZE ( mode ) <= 4 ) ) ) return arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) ; else if ( ( code == POST_MODIFY || code == PRE_MODIFY ) && arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) && GET_CODE ( XEXP ( x , 1 ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( x , 1 ) , 0 ) , XEXP ( x , 0 ) ) ) { rtx addend = XEXP ( XEXP ( x , 1 ) , 1 ) ; HOST_WIDE_INT offset ; if ( ! CONST_INT_P ( addend ) ) return 0 ; offset = INTVAL ( addend ) ; if ( GET_MODE_SIZE ( mode ) <= 4 ) return ( offset > - 256 && offset < 256 ) ; return ( use_ldrd && offset > - 1024 && offset < 1024 && ( offset & 3 ) == 0 ) ; } else if ( reload_completed && ( code == LABEL_REF || ( code == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ) ) ) return 1 ; else if ( mode == TImode || ( TARGET_NEON && VALID_NEON_STRUCT_MODE ( mode ) ) ) return 0 ; else if ( code == PLUS ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; return ( ( arm_address_register_rtx_p ( xop0 , strict_p ) && ( thumb2_legitimate_index_p ( mode , xop1 , strict_p ) || ( ! strict_p && will_be_in_index_register ( xop1 ) ) ) ) || ( arm_address_register_rtx_p ( xop1 , strict_p ) && thumb2_legitimate_index_p ( mode , xop0 , strict_p ) ) ) ; } else if ( arm_disable_literal_pool && code == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) ) return 0 ; else if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && code == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) && ! ( flag_pic && symbol_mentioned_p ( get_pool_constant ( x ) ) && ! pcrel_constant_p ( get_pool_constant ( x ) ) ) ) return 1 ; return 0 ; } </s>

Return nonzero if X is a valid Thumb-2 address operand .


<s> static void nvptx_emit_joining ( unsigned mask , bool is_call ) { mask &= ( GOMP_DIM_MASK ( GOMP_DIM_WORKER ) | GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) ) ; if ( mask ) { rtx op = GEN_INT ( mask | ( is_call << GOMP_DIM_MAX ) ) ; if ( ! is_call ) emit_insn ( gen_nvptx_joining ( op ) ) ; emit_insn ( gen_nvptx_join ( op ) ) ; } } </s>


<s> static bool is_costly_group ( rtx * group_insns , rtx next_insn ) { int i ; rtx link ; int cost ; int issue_rate = rs6000_issue_rate ( ) ; for ( i = 0 ; i < issue_rate ; i ++ ) { rtx insn = group_insns [ i ] ; if ( ! insn ) continue ; for ( link = INSN_DEPEND ( insn ) ; link != 0 ; link = XEXP ( link , 1 ) ) { rtx next = XEXP ( link , 0 ) ; if ( next == next_insn ) { cost = insn_cost ( insn , link , next_insn ) ; if ( rs6000_is_costly_dependence ( insn , next_insn , link , cost , 0 ) ) return true ; } } } return false ; } </s>

Return true if it is recommended to keep NEXT_INSN `` far '' ( in a separate dispatch group ) from the insns in GROUP_INSNS . Return false otherwise .


<s> void PPCInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; BuildMI ( MBB , MI , DL , get ( PPC :: NOP ) ) ; } </s>

Insert a noop into the instruction stream at the specified point .


<s> static bool isSigned ( Kind Cmp ) { return ( Cmp & ( L | G ) && ! ( Cmp & U ) ) ; } </s>

Returns true if all source operands of the recurrence are SExtInsts .


<s> StringRef str ( ) { return OS . str ( ) ; } </s>

Return the twine contents as a std : :string .


<s>
void
emitInst
(
uint32_t
Inst
,
char
Suffix
)
{
unsigned
Size
;
char
Buffer
[
4
]
;
const
bool
LittleEndian
=
getContext
(
)
.
getAsmInfo
(
)
->
isLittleEndian
(
)
;
switch
(
Suffix
)
{
case
'\0'
:
Size
=
4
;
assert
(
!
IsThumb
)
;
EmitARMMappingSymbol
(
)
;
for
(
unsigned
II
=
0
,
IE
=
Size
;
II
!=
IE
;
II
++
)
{
const
unsigned
I
=
LittleEndian
(
Size
II
1
)
:
II
;
Buffer
[
Size
II
1
]
=
uint8_t
(
Inst
>>
I
*
CHAR_BIT
)
;
}
break
;
case
'n'
:
case
'w'
:
Size
=
(
Suffix
==
'n'
2
:
4
)
;
assert
(
IsThumb
)
;
EmitThumbMappingSymbol
(
)
;
for
(
unsigned
II
=
0
,
IE
=
Size
;
II
!=
IE
;
II
=
II
+
2
)
{
const
unsigned
I0
=
LittleEndian
II
+
0
:
II
+
1
;
const
unsigned
I1
=
LittleEndian
II
+
1
:
II
+
0
;
Buffer
[
Size
II
2
]
=
uint8_t
(
Inst
>>
I0
*
CHAR_BIT
)
;
Buffer
[
Size
II
1
]
=
uint8_t
(
Inst
>>
I1
*
CHAR_BIT
)
;
}
break
;
default
:
llvm_unreachable
(
"Invalid Suffix"
)
;
}
MCELFStreamer
::
EmitBytes
(
StringRef
(
Buffer
,
Size
)
)
;
}
</s>

Callback used to implement the .inst directive .


<s> bool enableMachineScheduler ( ) const override { return true ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .