<s> bool CheckReturn ( const SmallVectorImpl < ISD :: OutputArg > & ArgsFlags , CCAssignFn Fn ) { PreAnalyzeReturnForF128 ( ArgsFlags ) ; PreAnalyzeReturnForVectorFloat ( ArgsFlags ) ; bool Return = CCState :: CheckReturn ( ArgsFlags , Fn ) ; OriginalArgWasFloat . clear ( ) ; OriginalArgWasF128 . clear ( ) ; OriginalArgWasFloatVector . clear ( ) ; return Return ; } </s>

CheckReturn - Analyze the return values of a function , returning true if the return can be performed without sret-demotion , and false otherwise .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; AU . addRequired < WebAssemblyExceptionInfo > ( ) ; AU . addPreserved < WebAssemblyExceptionInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> const char * out_tsthi ( rtx insn , int * l ) { if ( compare_sign_p ( insn ) ) { if ( l ) * l = 1 ; return AS1 ( tst , % B0 ) ; } if ( reg_unused_after ( insn , SET_SRC ( PATTERN ( insn ) ) ) && compare_eq_p ( insn ) ) { if ( l ) * l = 1 ; return AS2 ( or , % A0 , % B0 ) ; } if ( test_hard_reg_class ( ADDW_REGS , SET_SRC ( PATTERN ( insn ) ) ) ) { if ( l ) * l = 1 ; return AS2 ( sbiw , % 0 , 0 ) ; } if ( l ) * l = 2 ; return ( AS2 ( cp , % A0 , __zero_reg__ ) CR_TAB AS2 ( cpc , % B0 , __zero_reg__ ) ) ; } </s>


runOnMachineFunction - Emit the function body .


<s> InstructionCost GCNTTIImpl :: getMinMaxReductionCost ( VectorType * Ty , VectorType * CondTy , bool IsPairwise , bool IsUnsigned , TTI :: TargetCostKind CostKind ) { EVT OrigTy = TLI -> getValueType ( DL , Ty ) ; if ( IsPairwise || ! ST -> hasVOP3PInsts ( ) || OrigTy . getScalarSizeInBits ( ) != 16 ) return BaseT :: getMinMaxReductionCost ( Ty , CondTy , IsPairwise , IsUnsigned , CostKind ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; return LT . first * getHalfRateInstrCost ( CostKind ) ; } </s>

Try to calculate op costs for min/max reduction operations .


<s> static struct constant_pool * s390_start_pool ( struct constant_pool * * pool_list , rtx insn ) { struct constant_pool * pool , * * prev ; pool = s390_alloc_pool ( ) ; pool -> first_insn = insn ; for ( prev = pool_list ; * prev ; prev = & ( * prev ) -> next ) ; * prev = pool ; return pool ; } </s>

Create new constant pool covering instructions starting at INSN and chain it to the end of POOL_LIST .


<s>
int64_t
ARMBaseRegisterInfo
::
getFrameIndexInstrOffset
(
const
MachineInstr
*
MI
,
int
Idx
)
const
{
const
MCInstrDesc
&
Desc
=
MI
->
getDesc
(
)
;
unsigned
AddrMode
=
(
Desc
.
TSFlags
&
ARMII
::
AddrModeMask
)
;
int64_t
InstrOffs
=
0
;
;
int
Scale
=
1
;
unsigned
ImmIdx
=
0
;
switch
(
AddrMode
)
{
case
ARMII
::
AddrModeT2_i8
:
case
ARMII
::
AddrModeT2_i12
:
case
ARMII
::
AddrMode_i12
:
InstrOffs
=
MI
->
getOperand
(
Idx
+
1
)
.
getImm
(
)
;
Scale
=
1
;
break
;
case
ARMII
::
AddrMode5
:
{
const
MachineOperand
&
OffOp
=
MI
->
getOperand
(
Idx
+
1
)
;
InstrOffs
=
ARM_AM
::
getAM5Offset
(
OffOp
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM5Op
(
OffOp
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
Scale
=
4
;
break
;
}
case
ARMII
::
AddrMode2
:
{
ImmIdx
=
Idx
+
2
;
InstrOffs
=
ARM_AM
::
getAM2Offset
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM2Op
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
break
;
}
case
ARMII
::
AddrMode3
:
{
ImmIdx
=
Idx
+
2
;
InstrOffs
=
ARM_AM
::
getAM3Offset
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM3Op
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
break
;
}
case
ARMII
::
AddrModeT1_s
:
{
ImmIdx
=
Idx
+
1
;
InstrOffs
=
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
;
Scale
=
4
;
break
;
}
default
:
llvm_unreachable
(
"Unsupported addressing mode!"
)
;
break
;
}
return
InstrOffs
*
Scale
;
}
</s>

Get the offset from the referenced frame index in the instruction , if there is one .


<s>
void
relaxInstruction
(
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
)
const
override
{
llvm_unreachable
(
"relaxInstruction() unimplemented"
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> void HexagonPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableExpandCondsets ) { Pass * Exp = createHexagonExpandCondsets ( ) ; insertPass ( & RegisterCoalescerID , IdentifyingPassPtr ( Exp ) ) ; } if ( ! DisableStoreWidening ) addPass ( createHexagonStoreWidening ( ) , false ) ; if ( ! DisableHardwareLoops ) addPass ( createHexagonHardwareLoops ( ) , false ) ; } if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Default ) addPass ( & MachinePipelinerID ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> MVT PPCTargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , EVT VT ) const { if ( Subtarget . hasSPE ( ) && VT == MVT :: f64 ) return MVT :: i32 ; return PPCTargetLowering :: getRegisterType ( Context , VT ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


<s> unsigned SystemZRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? SystemZ :: R11D : SystemZ :: R15D ; } </s>


<s> static NodeType * getEntryNode ( const MCallSubGraph & G ) { return G . getEntryNode ( ) ? G . getEntryNode ( ) : G . Nodes . front ( ) ; } </s>

Return the token chain corresponding to the entry of the function .


<s> rtx mips_rewrite_small_data ( rtx pattern ) { pattern = copy_insn ( pattern ) ; mips_rewrite_small_data_1 ( & pattern , SYMBOL_CONTEXT_LEA ) ; return pattern ; } </s>

If possible , rewrite OP so that it refers to small data using explicit relocations .


initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool RISCVInstrInfo :: isMBBSafeToOutlineFrom ( MachineBasicBlock & MBB , unsigned & Flags ) const { return TargetInstrInfo :: isMBBSafeToOutlineFrom ( MBB , Flags ) ; } </s>

Optional target hook that returns true if MBB is safe to outline from , and returns any target-specific information in Flags .


<s> bool ix86_check_no_addr_space ( rtx insn ) { subrtx_var_iterator :: array_type array ; FOR_EACH_SUBRTX_VAR ( iter , array , PATTERN ( insn ) , ALL ) { rtx x = * iter ; if ( MEM_P ( x ) && ! ADDR_SPACE_GENERIC_P ( MEM_ADDR_SPACE ( x ) ) ) return false ; } return true ; } </s>

Return false if INSN contains a MEM with a non-default address space .


<s> CCAssignFn * AMDGPUTargetLowering :: CCAssignFnForCall ( CallingConv :: ID CC , bool IsVarArg ) { return AMDGPUCallLowering :: CCAssignFnForCall ( CC , IsVarArg ) ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> bool ARMExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const ARMBaseInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; STI = & MF . getTarget ( ) . getSubtarget < ARMSubtarget > ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= ExpandMBB ( * MFI ) ; return Modified ; } </s>


<s> bool HexagonTargetLowering :: shouldReduceLoadWidth ( SDNode * Load , ISD :: LoadExtType ExtTy , EVT NewVT ) const { if ( ! TargetLoweringBase :: shouldReduceLoadWidth ( Load , ExtTy , NewVT ) ) return false ; auto * L = cast < LoadSDNode > ( Load ) ; std :: pair < SDValue , int > BO = getBaseAndOffset ( L -> getBasePtr ( ) ) ; if ( BO . first . getOpcode ( ) == HexagonISD :: CONST32_GP ) return false ; if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( BO . first ) ) { auto & HTM = static_cast < const HexagonTargetMachine & > ( getTargetMachine ( ) ) ; const auto * GO = dyn_cast_or_null < const GlobalObject > ( GA -> getGlobal ( ) ) ; return ! GO || ! HTM . getObjFileLowering ( ) -> isGlobalInSmallSection ( GO , HTM ) ; } return true ; } </s>

Return true if we believe it is correct and profitable to reduce the load node to a smaller type .

Hexagon Hexagon ISD::LoadExtType HexagonISD::CONST32_GP Hexagon


<s> static int arc_insn_cost ( rtx_insn * insn , bool speed ) { int cost ; if ( recog_memoized ( insn ) < 0 ) return 0 ; if ( ! speed ) return get_attr_length ( insn ) ; cost = get_attr_cost ( insn ) ; if ( cost > 0 ) return cost ; enum attr_type type = get_attr_type ( insn ) ; switch ( type ) { case TYPE_LOAD : case TYPE_STORE : cost = COSTS_N_INSNS ( 2 ) ; break ; default : cost = COSTS_N_INSNS ( 1 ) ; break ; } return cost ; } </s>

Helper for INSN_COST . Per Segher Boessenkool : rtx_costs computes the cost for any rtx ( an insn , a set , a set source , any random piece of one ) . set_src_cost , set_rtx_cost , etc . are helper functions that use that . Those functions do not work for parallels . Also , costs are not additive like this simplified model assumes . Also , more complex backends tend to miss many cases in their rtx_costs function . Many passes that want costs want to know the cost of a full insn . Like combine . That 's why I created insn_cost : it solves all of the above problems .


<s> bool doMBBSchedRegionsTopDown ( ) const override { return true ; } </s>

If this method returns true , handling of the scheduling regions themselves ( in case of a scheduling boundary in MBB ) will be done beginning with the topmost region of MBB .


<s> rtx cris_gen_movem_load ( rtx src , rtx nregs_rtx ) { int nregs = INTVAL ( nregs_rtx ) ; rtvec vec ; int eltno = 1 ; int i ; rtx srcreg = XEXP ( src , 0 ) ; unsigned int regno = nregs - 1 ; int regno_inc = - 1 ; if ( GET_CODE ( srcreg ) == POST_INC ) srcreg = XEXP ( srcreg , 0 ) ; CRIS_ASSERT ( REG_P ( srcreg ) ) ; if ( nregs == 1 ) return gen_movsi ( gen_rtx_REG ( SImode , 0 ) , src ) ; vec = rtvec_alloc ( nregs + ( GET_CODE ( XEXP ( src , 0 ) ) == POST_INC ) ) ; if ( GET_CODE ( XEXP ( src , 0 ) ) == POST_INC ) { RTVEC_ELT ( vec , 1 ) = gen_rtx_SET ( srcreg , plus_constant ( Pmode , srcreg , nregs * 4 ) ) ; eltno ++ ; } src = replace_equiv_address ( src , srcreg ) ; RTVEC_ELT ( vec , 0 ) = gen_rtx_SET ( gen_rtx_REG ( SImode , regno ) , src ) ; regno += regno_inc ; for ( i = 1 ; i < nregs ; i ++ , eltno ++ ) { RTVEC_ELT ( vec , eltno ) = gen_rtx_SET ( gen_rtx_REG ( SImode , regno ) , adjust_address_nv ( src , SImode , i * 4 ) ) ; regno += regno_inc ; } return gen_rtx_PARALLEL ( VOIDmode , vec ) ; } </s>

Worker function for generating movem from mem for load_multiple .


<s>
unsigned
char
M680x0Subtarget
::
classifyGlobalReference
(
const
GlobalValue
*
GV
,
const
Module
&
M
)
const
{
if
(
TM
.
shouldAssumeDSOLocal
(
M
,
GV
)
)
return
classifyLocalReference
(
GV
)
;
switch
(
TM
.
getCodeModel
(
)
)
{
default
:
llvm_unreachable
(
"Unsupported code model"
)
;
case
CodeModel
::
Small
:
case
CodeModel
::
Kernel
:
{
if
(
isPositionIndependent
(
)
)
{
return
M680x0II
::
MO_GOTPCREL
;
}
else
{
return
M680x0II
::
MO_PC_RELATIVE_ADDRESS
;
}
}
case
CodeModel
::
Medium
:
{
if
(
isPositionIndependent
(
)
)
{
return
M680x0II
::
MO_GOTPCREL
;
}
else
{
if
(
IsM68020
)
{
return
M680x0II
::
MO_PC_RELATIVE_ADDRESS
;
}
return
M680x0II
::
MO_ABSOLUTE_ADDRESS
;
}
}
}
}
</s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s> StringRef getPassName ( ) const override { return "MipsPreLegalizerCombiner" ; } </s>

getPassName - Return a nice clean name for a pass .


<s> unsigned PPCFrameLowering :: getBasePointerSaveOffset ( ) const { return BasePointerSaveOffset ; } </s>

getBasePointerSaveOffset - Return the previous frame offset to save the base pointer .


<s>
MachineInstr
*
ARMBaseInstrInfo
::
optimizeSelect
(
MachineInstr
*
MI
,
bool
PreferFalse
)
const
{
assert
(
(
MI
->
getOpcode
(
)
==
ARM
::
MOVCCr
||
MI
->
getOpcode
(
)
==
ARM
::
t2MOVCCr
)
&&
"Unknown select instruction"
)
;
MachineRegisterInfo
&
MRI
=
MI
->
getParent
(
)
->
getParent
(
)
->
getRegInfo
(
)
;
MachineInstr
*
DefMI
=
canFoldIntoMOVCC
(
MI
->
getOperand
(
2
)
.
getReg
(
)
,
MRI
,
this
)
;
bool
Invert
=
!
DefMI
;
if
(
!
DefMI
)
DefMI
=
canFoldIntoMOVCC
(
MI
->
getOperand
(
1
)
.
getReg
(
)
,
MRI
,
this
)
;
if
(
!
DefMI
)
return
nullptr
;
MachineOperand
FalseReg
=
MI
->
getOperand
(
Invert
2
:
1
)
;
unsigned
DestReg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
const
TargetRegisterClass
*
PreviousClass
=
MRI
.
getRegClass
(
FalseReg
.
getReg
(
)
)
;
if
(
!
MRI
.
constrainRegClass
(
DestReg
,
PreviousClass
)
)
return
nullptr
;
MachineInstrBuilder
NewMI
=
BuildMI
(
*
MI
->
getParent
(
)
,
MI
,
MI
->
getDebugLoc
(
)
,
DefMI
->
getDesc
(
)
,
DestReg
)
;
const
MCInstrDesc
&
DefDesc
=
DefMI
->
getDesc
(
)
;
for
(
unsigned
i
=
1
,
e
=
DefDesc
.
getNumOperands
(
)
;
i
!=
e
&&
!
DefDesc
.
OpInfo
[
i
]
.
isPredicate
(
)
;
++
i
)
NewMI
.
addOperand
(
DefMI
->
getOperand
(
i
)
)
;
unsigned
CondCode
=
MI
->
getOperand
(
3
)
.
getImm
(
)
;
if
(
Invert
)
NewMI
.
addImm
(
ARMCC
::
getOppositeCondition
(
ARMCC
::
CondCodes
(
CondCode
)
)
)
;
else
NewMI
.
addImm
(
CondCode
)
;
NewMI
.
addOperand
(
MI
->
getOperand
(
4
)
)
;
if
(
NewMI
->
hasOptionalDef
(
)
)
AddDefaultCC
(
NewMI
)
;
FalseReg
.
setImplicit
(
)
;
NewMI
.
addOperand
(
FalseReg
)
;
NewMI
->
tieOperands
(
0
,
NewMI
->
getNumOperands
(
)
1
)
;
DefMI
->
eraseFromParent
(
)
;
return
NewMI
;
}
</s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


"Trying to obtain non-reserved register \""

Return the register ID of the name passed in .


<s> static void function_arg_record_value_1 ( const_tree type , HOST_WIDE_INT startbitpos , struct function_arg_record_value_parms * parms , bool packed_p ) { tree field ; if ( ! packed_p ) for ( field = TYPE_FIELDS ( type ) ; field ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) == FIELD_DECL && DECL_PACKED ( field ) ) { packed_p = true ; break ; } } for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) == FIELD_DECL ) { HOST_WIDE_INT bitpos = startbitpos ; if ( DECL_SIZE ( field ) != 0 ) { if ( integer_zerop ( DECL_SIZE ( field ) ) ) continue ; if ( tree_fits_uhwi_p ( bit_position ( field ) ) ) bitpos += int_bit_position ( field ) ; } if ( TREE_CODE ( TREE_TYPE ( field ) ) == RECORD_TYPE ) function_arg_record_value_1 ( TREE_TYPE ( field ) , bitpos , parms , packed_p ) ; else if ( ( FLOAT_TYPE_P ( TREE_TYPE ( field ) ) || TREE_CODE ( TREE_TYPE ( field ) ) == VECTOR_TYPE ) && TARGET_FPU && parms -> named && ! packed_p ) { if ( parms -> intoffset != - 1 ) { unsigned int startbit , endbit ; int intslots , this_slotno ; startbit = parms -> intoffset & - BITS_PER_WORD ; endbit = ( bitpos + BITS_PER_WORD - 1 ) & - BITS_PER_WORD ; intslots = ( endbit - startbit ) / BITS_PER_WORD ; this_slotno = parms -> slotno + parms -> intoffset / BITS_PER_WORD ; if ( intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno ) { intslots = MAX ( 0 , SPARC_INT_ARG_MAX - this_slotno ) ; parms -> stack = 1 ; } parms -> nregs += intslots ; parms -> intoffset = - 1 ; } if ( TREE_CODE ( TREE_TYPE ( field ) ) == VECTOR_TYPE && DECL_MODE ( field ) == BLKmode ) parms -> nregs += TYPE_VECTOR_SUBPARTS ( TREE_TYPE ( field ) ) ; else if ( TREE_CODE ( TREE_TYPE ( field ) ) == COMPLEX_TYPE ) parms -> nregs += 2 ; else parms -> nregs += 1 ; } else { if ( parms -> intoffset == - 1 ) parms -> intoffset = bitpos ; } } } } </s>

A subroutine of function_arg_record_value . Traverse the structure recursively and determine how many registers will be required .


<s> bool isReg ( ) const { return Kind == CV_Register ; } </s>


<s>
bool
AVRExpandPseudo
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
bool
Modified
=
false
;
const
AVRSubtarget
&
STI
=
MF
.
getSubtarget
<
AVRSubtarget
>
(
)
;
TRI
=
STI
.
getRegisterInfo
(
)
;
TII
=
STI
.
getInstrInfo
(
)
;
MF
.
getProperties
(
)
.
set
(
MachineFunctionProperties
::
Property
::
TracksLiveness
)
;
for
(
Block
&
MBB
:
MF
)
{
bool
ContinueExpanding
=
true
;
unsigned
ExpandCount
=
0
;
do
{
assert
(
ExpandCount
<
10
&&
"pseudo expand limit reached"
)
;
bool
BlockModified
=
expandMBB
(
MBB
)
;
Modified
|=
BlockModified
;
ExpandCount
++
;
ContinueExpanding
=
BlockModified
;
}
while
(
ContinueExpanding
)
;
}
return
Modified
;
}
</s>

runOnMachineFunction - Emit the function body .

AVR
AVR
AVR
AVR
0
10
"pseudo expand limit reached"


<s> Value * ARMTargetLowering :: emitStoreConditional ( IRBuilder < > & Builder , Value * Val , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == 64 ) { Intrinsic :: ID Int = IsRelease ? Intrinsic :: arm_stlexd : Intrinsic :: arm_strexd ; Function * Strex = Intrinsic :: getDeclaration ( M , Int ) ; Type * Int32Ty = Type :: getInt32Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int32Ty , "lo" ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , 32 ) , Int32Ty , "hi" ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall3 ( Strex , Lo , Hi , Addr ) ; } Intrinsic :: ID Int = IsRelease ? Intrinsic :: arm_stlex : Intrinsic :: arm_strex ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Strex = Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateCall2 ( Strex , Builder . CreateZExtOrBitCast ( Val , Strex -> getFunctionType ( ) -> getParamType ( 0 ) ) , Addr ) ; } </s>

Perform a store-conditional operation to Addr .


<s> std :: pair < unsigned , const TargetRegisterClass * > OR1KTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'r' : return std :: make_pair ( 0U , & OR1K :: GPRRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> bool sh_vector_mode_supported_p ( enum machine_mode mode ) { if ( TARGET_FPU_ANY && ( ( mode == V2SFmode ) || ( mode == V4SFmode ) || ( mode == V16SFmode ) ) ) return true ; else if ( TARGET_SHMEDIA && ( ( mode == V8QImode ) || ( mode == V2HImode ) || ( mode == V4HImode ) || ( mode == V2SImode ) ) ) return true ; return false ; } </s>

Implements target hook vector_mode_supported_p .


"\n======\nmacro TARGET_ADDRESS_COST = %d\n"


<s> int aarch64_simd_attr_length_rglist ( machine_mode mode ) { return ( GET_MODE_SIZE ( mode ) . to_constant ( ) / UNITS_PER_VREG ) * 4 ; } </s>

Compute and return the length of aarch64_simd_reglist < mode > , where < mode > is one of VSTRUCT modes : OI , CI , EI , or XI .


<s> void SITargetLowering :: computeKnownBitsForFrameIndex ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { TargetLowering :: computeKnownBitsForFrameIndex ( Op , Known , DemandedElts , DAG , Depth ) ; Known . Zero . setHighBits ( getSubtarget ( ) -> getKnownHighZeroBitsForFrameIndex ( ) ) ; } </s>

Determine which of the bits of FrameIndex FIOp are known to be 0 .


<s> inline const mode_suffix_info & function_instance :: mode_suffix ( ) const { return mode_suffixes [ mode_suffix_id ] ; } </s>

Return information about the function 's mode suffix .


<s> static bool mips_interrupt_type_p ( tree type ) { return lookup_attribute ( "interrupt" , TYPE_ATTRIBUTES ( type ) ) != NULL ; } </s>

Check if the interrupt attribute is set for a function .


<s> SDValue SITargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : return AMDGPUTargetLowering :: PerformDAGCombine ( N , DCI ) ; case ISD :: FADD : return performFAddCombine ( N , DCI ) ; case ISD :: FSUB : return performFSubCombine ( N , DCI ) ; case ISD :: SETCC : return performSetCCCombine ( N , DCI ) ; case ISD :: FMAXNUM : case ISD :: FMINNUM : case ISD :: SMAX : case ISD :: SMIN : case ISD :: UMAX : case ISD :: UMIN : case AMDGPUISD :: FMIN_LEGACY : case AMDGPUISD :: FMAX_LEGACY : { if ( DCI . getDAGCombineLevel ( ) >= AfterLegalizeDAG && N -> getValueType ( 0 ) != MVT :: f64 && getTargetMachine ( ) . getOptLevel ( ) > CodeGenOpt :: None ) return performMinMaxCombine ( N , DCI ) ; break ; } case ISD :: LOAD : case ISD :: STORE : case ISD :: ATOMIC_LOAD : case ISD :: ATOMIC_STORE : case ISD :: ATOMIC_CMP_SWAP : case ISD :: ATOMIC_CMP_SWAP_WITH_SUCCESS : case ISD :: ATOMIC_SWAP : case ISD :: ATOMIC_LOAD_ADD : case ISD :: ATOMIC_LOAD_SUB : case ISD :: ATOMIC_LOAD_AND : case ISD :: ATOMIC_LOAD_OR : case ISD :: ATOMIC_LOAD_XOR : case ISD :: ATOMIC_LOAD_NAND : case ISD :: ATOMIC_LOAD_MIN : case ISD :: ATOMIC_LOAD_MAX : case ISD :: ATOMIC_LOAD_UMIN : case ISD :: ATOMIC_LOAD_UMAX : case AMDGPUISD :: ATOMIC_INC : case AMDGPUISD :: ATOMIC_DEC : if ( DCI . isBeforeLegalize ( ) ) break ; return performMemSDNodeCombine ( cast < MemSDNode > ( N ) , DCI ) ; case ISD :: AND : return performAndCombine ( N , DCI ) ; case ISD :: OR : return performOrCombine ( N , DCI ) ; case ISD :: XOR : return performXorCombine ( N , DCI ) ; case AMDGPUISD :: FP_CLASS : return performClassCombine ( N , DCI ) ; case ISD :: FCANONICALIZE : return performFCanonicalizeCombine ( N , DCI ) ; case AMDGPUISD :: FRACT : case AMDGPUISD :: RCP : case AMDGPUISD :: RSQ : case AMDGPUISD :: RCP_LEGACY : case AMDGPUISD :: RSQ_LEGACY : case AMDGPUISD :: RSQ_CLAMP : case AMDGPUISD :: LDEXP : { SDValue Src = N -> getOperand ( 0 ) ; if ( Src . isUndef ( ) ) return Src ; break ; } case ISD :: SINT_TO_FP : case ISD :: UINT_TO_FP : return performUCharToFloatCombine ( N , DCI ) ; case AMDGPUISD :: CVT_F32_UBYTE0 : case AMDGPUISD :: CVT_F32_UBYTE1 : case AMDGPUISD :: CVT_F32_UBYTE2 : case AMDGPUISD :: CVT_F32_UBYTE3 : return performCvtF32UByteNCombine ( N , DCI ) ; } return AMDGPUTargetLowering :: PerformDAGCombine ( N , DCI ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> static inline MemOpKey getTombstoneKey ( ) { return MemOpKey ( PtrInfo :: getTombstoneKey ( ) , PtrInfo :: getTombstoneKey ( ) , PtrInfo :: getTombstoneKey ( ) , PtrInfo :: getTombstoneKey ( ) , PtrInfo :: getTombstoneKey ( ) ) ; } </s>

Difference in tombstone is that the Optional is meaningful .


"VTMP producer and consumer not in same block"


"cannot emit unaligned pointers in ptx assembly"

Target hook for assembling integer object X of size SIZE .


<s> void X86AsmParser :: emitInstruction ( MCInst & Inst , OperandVector & Operands , MCStreamer & Out ) { Out . emitInstruction ( Inst , getSTI ( ) ) ; if ( LVIInlineAsmHardening ) { if ( getSTI ( ) . getFeatureBits ( ) [ X86 :: FeatureLVIControlFlowIntegrity ] && applyLVICFIMitigation ( Inst ) ) return ; if ( getSTI ( ) . getFeatureBits ( ) [ X86 :: FeatureLVILoadHardening ] ) applyLVILoadHardeningMitigation ( Inst , Out ) ; } } </s>

Targets should implement this to emit instructions .


<s> unsigned int rs6000_dbx_register_number ( unsigned int regno , unsigned int format ) { if ( ( format == 0 && dwarf_debuginfo_p ( ) ) || format == 1 ) { if ( regno <= 31 ) return regno ; if ( FP_REGNO_P ( regno ) ) return regno - FIRST_FPR_REGNO + 32 ; if ( ALTIVEC_REGNO_P ( regno ) ) return regno - FIRST_ALTIVEC_REGNO + 1124 ; if ( regno == LR_REGNO ) return 108 ; if ( regno == CTR_REGNO ) return 109 ; if ( regno == CA_REGNO ) return 101 ; if ( format == 1 && regno == CR2_REGNO ) return 64 ; if ( CR_REGNO_P ( regno ) ) return regno - CR0_REGNO + 86 ; if ( regno == VRSAVE_REGNO ) return 356 ; if ( regno == VSCR_REGNO ) return 67 ; if ( regno == FRAME_POINTER_REGNUM ) return 111 ; if ( regno == ARG_POINTER_REGNUM ) return 67 ; if ( regno == 64 ) return 100 ; gcc_unreachable ( ) ; } if ( regno <= 31 ) return regno ; if ( FP_REGNO_P ( regno ) ) return regno - FIRST_FPR_REGNO + 32 ; if ( ALTIVEC_REGNO_P ( regno ) ) return regno - FIRST_ALTIVEC_REGNO + 77 ; if ( regno == LR_REGNO ) return 65 ; if ( regno == CTR_REGNO ) return 66 ; if ( regno == CA_REGNO ) return 76 ; if ( CR_REGNO_P ( regno ) ) return regno - CR0_REGNO + 68 ; if ( regno == VRSAVE_REGNO ) return 109 ; if ( regno == VSCR_REGNO ) return 110 ; if ( regno == FRAME_POINTER_REGNUM ) return 111 ; if ( regno == ARG_POINTER_REGNUM ) return 67 ; if ( regno == 64 ) return 64 ; gcc_unreachable ( ) ; } </s>

Map internal gcc register numbers to DWARF2 register numbers .


<s>
StackOffset
X86FrameLowering
::
getFrameIndexReferencePreferSP
(
const
MachineFunction
&
MF
,
int
FI
,
Register
&
FrameReg
,
bool
IgnoreSPUpdates
)
const
{
const
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
const
uint64_t
StackSize
=
MFI
.
getStackSize
(
)
;
if
(
MFI
.
isFixedObjectIndex
(
FI
)
&&
TRI
->
needsStackRealignment
(
MF
)
&&
!
STI
.
isTargetWin64
(
)
)
return
getFrameIndexReference
(
MF
,
FI
,
FrameReg
)
;
if
(
!
IgnoreSPUpdates
&&
!
hasReservedCallFrame
(
MF
)
)
return
getFrameIndexReference
(
MF
,
FI
,
FrameReg
)
;
assert
(
MF
.
getInfo
<
X86MachineFunctionInfo
>
(
)
->
getTCReturnAddrDelta
(
)
>=
0
&&
"we don't handle this case!"
)
;
return
getFrameIndexReferenceSP
(
MF
,
FI
,
FrameReg
,
StackSize
)
;
}
</s>

Same as getFrameIndexReference , except that the stack pointer ( as opposed to the frame pointer ) will be the preferred value for FrameReg .


<s> static rtx rs6000_delegitimize_address ( rtx orig_x ) { rtx x , y , offset ; orig_x = delegitimize_mem_from_attrs ( orig_x ) ; x = orig_x ; if ( MEM_P ( x ) ) x = XEXP ( x , 0 ) ; y = x ; if ( TARGET_CMODEL != CMODEL_SMALL && GET_CODE ( y ) == LO_SUM ) y = XEXP ( y , 1 ) ; offset = NULL_RTX ; if ( GET_CODE ( y ) == PLUS && GET_MODE ( y ) == Pmode && CONST_INT_P ( XEXP ( y , 1 ) ) ) { offset = XEXP ( y , 1 ) ; y = XEXP ( y , 0 ) ; } if ( GET_CODE ( y ) == UNSPEC && XINT ( y , 1 ) == UNSPEC_TOCREL ) { y = XVECEXP ( y , 0 , 0 ) ; if ( TARGET_XCOFF && GET_CODE ( y ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( y ) && rs6000_real_tls_symbol_ref_p ( get_pool_constant ( y ) ) ) return orig_x ; if ( offset != NULL_RTX ) y = gen_rtx_PLUS ( Pmode , y , offset ) ; if ( ! MEM_P ( orig_x ) ) return y ; else return replace_equiv_address_nv ( orig_x , y ) ; } if ( TARGET_MACHO && GET_CODE ( orig_x ) == LO_SUM && GET_CODE ( XEXP ( orig_x , 1 ) ) == CONST ) { y = XEXP ( XEXP ( orig_x , 1 ) , 0 ) ; if ( GET_CODE ( y ) == UNSPEC && XINT ( y , 1 ) == UNSPEC_MACHOPIC_OFFSET ) return XVECEXP ( y , 0 , 0 ) ; } return orig_x ; } </s>

In the name of slightly smaller debug output , and to cater to general assembler lossage , recognize various UNSPEC sequences and turn them back into a direct symbol reference .


<s> Optional < Instruction * > AArch64TTIImpl :: instCombineIntrinsic ( InstCombiner & IC , IntrinsicInst & II ) const { Intrinsic :: ID IID = II . getIntrinsicID ( ) ; switch ( IID ) { default : break ; case Intrinsic :: aarch64_sve_convert_from_svbool : return instCombineConvertFromSVBool ( IC , II ) ; case Intrinsic :: aarch64_sve_dup : return instCombineSVEDup ( IC , II ) ; case Intrinsic :: aarch64_sve_cmpne : case Intrinsic :: aarch64_sve_cmpne_wide : return instCombineSVECmpNE ( IC , II ) ; case Intrinsic :: aarch64_sve_rdffr : return instCombineRDFFR ( IC , II ) ; case Intrinsic :: aarch64_sve_lasta : case Intrinsic :: aarch64_sve_lastb : return instCombineSVELast ( IC , II ) ; case Intrinsic :: aarch64_sve_cntd : return instCombineSVECntElts ( IC , II , 2 ) ; case Intrinsic :: aarch64_sve_cntw : return instCombineSVECntElts ( IC , II , 4 ) ; case Intrinsic :: aarch64_sve_cnth : return instCombineSVECntElts ( IC , II , 8 ) ; case Intrinsic :: aarch64_sve_cntb : return instCombineSVECntElts ( IC , II , 16 ) ; case Intrinsic :: aarch64_sve_ptest_any : case Intrinsic :: aarch64_sve_ptest_first : case Intrinsic :: aarch64_sve_ptest_last : return instCombineSVEPTest ( IC , II ) ; case Intrinsic :: aarch64_sve_mul : case Intrinsic :: aarch64_sve_fmul : return instCombineSVEVectorMul ( IC , II ) ; case Intrinsic :: aarch64_sve_tbl : return instCombineSVETBL ( IC , II ) ; case Intrinsic :: aarch64_sve_uunpkhi : case Intrinsic :: aarch64_sve_uunpklo : case Intrinsic :: aarch64_sve_sunpkhi : case Intrinsic :: aarch64_sve_sunpklo : return instCombineSVEUnpack ( IC , II ) ; } return None ; } </s>

Targets can implement their own combinations for target-specific intrinsics .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
auto
RegName
=
[
]
(
unsigned
Reg
)
{
if
(
Reg
)
return
LoongArchInstPrinter
::
getRegisterName
(
Reg
)
;
else
return
"noreg"
;
}
;
switch
(
Kind
)
{
case
KindTy
::
Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
KindTy
::
Register
:
OS
<<
"<register "
<<
RegName
(
getReg
(
)
)
<<
">"
;
break
;
case
KindTy
::
Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

LoongArch
LoongArch
"noreg"
"<register "
">"
"'"
"'"


<s> bool isPPC64 ( ) const { Triple TT ( getTargetTriple ( ) ) ; return ( TT . getArch ( ) == Triple :: ppc64 || TT . getArch ( ) == Triple :: ppc64le ) ; } </s>

Tests whether the target is 64-bit PowerPC ( little and big endian ) .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool nds32_can_use_bclr_p ( HOST_WIDE_INT ival ) { int one_bit_count ; unsigned HOST_WIDE_INT mask = GET_MODE_MASK ( SImode ) ; one_bit_count = popcount_hwi ( ( unsigned HOST_WIDE_INT ) ( ~ ival ) & mask ) ; return ( TARGET_EXT_PERF && ( one_bit_count == 1 ) ) ; } </s>

Function to check if 'bclr ' instruction can be used with IVAL .


<s>
unsigned
SystemZInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugInstr
(
)
)
continue
;
if
(
!
I
->
isBranch
(
)
)
break
;
if
(
!
getBranchInfo
(
*
I
)
.
hasMBBTarget
(
)
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .

SystemZ
SystemZ
"code size not handled"
0


<s> SDNode * SITargetLowering :: PostISelFolding ( MachineSDNode * Node , SelectionDAG & DAG ) const { const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; if ( TII -> isMIMG ( Node -> getMachineOpcode ( ) ) ) adjustWritemask ( Node , DAG ) ; if ( Node -> getMachineOpcode ( ) == AMDGPU :: INSERT_SUBREG || Node -> getMachineOpcode ( ) == AMDGPU :: REG_SEQUENCE ) { legalizeTargetIndependentNode ( Node , DAG ) ; return Node ; } return Node ; } </s>

Fold the instructions after selecting them .


<s> static void h8300_push_pop ( int regno , int nregs , bool pop_p , bool return_p ) { int i , j ; rtvec vec ; rtx sp , offset , x ; if ( ! return_p && nregs == 1 ) { if ( pop_p ) pop ( regno ) ; else push ( regno , false ) ; return ; } vec = rtvec_alloc ( ( return_p ? 1 : 0 ) + nregs + 1 ) ; sp = stack_pointer_rtx ; i = 0 ; if ( return_p ) { RTVEC_ELT ( vec , i ) = ret_rtx ; i ++ ; } for ( j = 0 ; j < nregs ; j ++ ) { rtx lhs , rhs ; if ( pop_p ) { lhs = gen_rtx_REG ( SImode , regno + j ) ; rhs = gen_rtx_MEM ( SImode , plus_constant ( Pmode , sp , ( nregs - j - 1 ) * 4 ) ) ; } else { lhs = gen_rtx_MEM ( SImode , plus_constant ( Pmode , sp , ( j + 1 ) * - 4 ) ) ; rhs = gen_rtx_REG ( SImode , regno + j ) ; } RTVEC_ELT ( vec , i + j ) = gen_rtx_SET ( VOIDmode , lhs , rhs ) ; } offset = GEN_INT ( ( pop_p ? nregs : - nregs ) * 4 ) ; RTVEC_ELT ( vec , i + j ) = gen_rtx_SET ( VOIDmode , sp , gen_rtx_PLUS ( Pmode , sp , offset ) ) ; x = gen_rtx_PARALLEL ( VOIDmode , vec ) ; if ( ! pop_p ) x = Fpa ( x ) ; if ( return_p ) emit_jump_insn ( x ) ; else emit_insn ( x ) ; } </s>

Emit an instruction to push or pop NREGS consecutive registers starting at register REGNO . POP_P selects a pop rather than a push and RETURN_P is true if the instruction should return . It must be possible to do the requested operation in a single instruction . If NREGS == 1 & & ! RETURN_P , use a normal push or pop insn . Otherwise emit a parallel of the form : ( parallel [ ( return ) ; ; if RETURN_P ( save or restore REGNO ) ( save or restore REGNO + 1 ) ... ( save or restore REGNO + NREGS - 1 ) ( set sp ( plus sp ( const_int adjust ) ) ) ]


<s> static bool nios2_print_operand_punct_valid_p ( unsigned char code ) { return ( code == '.' || code == '!' ) ; } </s>


<s> static bool ix86_cannot_force_const_mem ( machine_mode mode , rtx x ) { switch ( GET_CODE ( x ) ) { case CONST_INT : case CONST_WIDE_INT : case CONST_DOUBLE : case CONST_VECTOR : return false ; default : break ; } return ! ix86_legitimate_constant_p ( mode , x ) ; } </s>

Determine if it 's legal to put X into the constant pool . This is not possible for the address of thread-local symbols , which is checked above .


<s> static void rl78_compute_frame_info ( void ) { int i ; cfun -> machine -> computed = 1 ; cfun -> machine -> framesize_regs = 0 ; cfun -> machine -> framesize_locals = get_frame_size ( ) ; cfun -> machine -> framesize_outgoing = crtl -> outgoing_args_size ; for ( i = 0 ; i < 16 ; i ++ ) if ( need_to_save ( i * 2 ) || need_to_save ( i * 2 + 1 ) ) { cfun -> machine -> need_to_push [ i ] = 1 ; cfun -> machine -> framesize_regs += 2 ; } else cfun -> machine -> need_to_push [ i ] = 0 ; if ( ( cfun -> machine -> framesize_locals + cfun -> machine -> framesize_outgoing ) & 1 ) cfun -> machine -> framesize_locals ++ ; cfun -> machine -> framesize = ( cfun -> machine -> framesize_regs + cfun -> machine -> framesize_locals + cfun -> machine -> framesize_outgoing ) ; } </s>

Compute all the frame-related fields in our machine_function structure .


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { if ( Inst . getNumOperands ( ) == 0 ) return false ; if ( ! isConditionalBranch ( Inst ) && ! isUnconditionalBranch ( Inst ) && ! isCall ( Inst ) ) return false ; if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ 0 ] . OperandType == MCOI :: OPERAND_PCREL ) { int64_t Imm = Inst . getOperand ( 0 ) . getImm ( ) ; Target = Addr + Size + Imm ; return true ; } else { int64_t Imm = Inst . getOperand ( 0 ) . getImm ( ) ; if ( Imm == 0 ) return false ; Target = Imm ; return true ; } } </s>

Given a branch instruction try to get the address the branch targets .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> void rs6000_emit_popcount ( rtx dst , rtx src ) { machine_mode mode = GET_MODE ( dst ) ; rtx tmp1 , tmp2 ; if ( TARGET_POPCNTD ) { if ( mode == SImode ) emit_insn ( gen_popcntdsi2 ( dst , src ) ) ; else emit_insn ( gen_popcntddi2 ( dst , src ) ) ; return ; } tmp1 = gen_reg_rtx ( mode ) ; if ( mode == SImode ) { emit_insn ( gen_popcntbsi2 ( tmp1 , src ) ) ; tmp2 = expand_mult ( SImode , tmp1 , GEN_INT ( 0x01010101 ) , NULL_RTX , 0 ) ; tmp2 = force_reg ( SImode , tmp2 ) ; emit_insn ( gen_lshrsi3 ( dst , tmp2 , GEN_INT ( 24 ) ) ) ; } else { emit_insn ( gen_popcntbdi2 ( tmp1 , src ) ) ; tmp2 = expand_mult ( DImode , tmp1 , GEN_INT ( ( HOST_WIDE_INT ) 0x01010101 << 32 | 0x01010101 ) , NULL_RTX , 0 ) ; tmp2 = force_reg ( DImode , tmp2 ) ; emit_insn ( gen_lshrdi3 ( dst , tmp2 , GEN_INT ( 56 ) ) ) ; } } </s>

Emit popcount intrinsic on TARGET_POPCNTB ( Power5 ) and TARGET_POPCNTD ( Power7 ) targets . DST is the target , and SRC is the argument operand .


<s> bool s390_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( ! TARGET_VX && VECTOR_NOFP_REGNO_P ( regno ) ) return false ; switch ( REGNO_REG_CLASS ( regno ) ) { case VEC_REGS : return ( ( GET_MODE_CLASS ( mode ) == MODE_INT && s390_class_max_nregs ( VEC_REGS , mode ) == 1 ) || mode == DFmode || ( TARGET_VXE && mode == SFmode ) || s390_vector_mode_supported_p ( mode ) ) ; break ; case FP_REGS : if ( TARGET_VX && ( ( GET_MODE_CLASS ( mode ) == MODE_INT && s390_class_max_nregs ( FP_REGS , mode ) == 1 ) || mode == DFmode || s390_vector_mode_supported_p ( mode ) ) ) return true ; if ( REGNO_PAIR_OK ( regno , mode ) ) { if ( mode == SImode || mode == DImode ) return true ; if ( FLOAT_MODE_P ( mode ) && GET_MODE_CLASS ( mode ) != MODE_VECTOR_FLOAT ) return true ; } break ; case ADDR_REGS : if ( FRAME_REGNO_P ( regno ) && mode == Pmode ) return true ; case GENERAL_REGS : if ( REGNO_PAIR_OK ( regno , mode ) ) { if ( TARGET_ZARCH || ( mode != TFmode && mode != TCmode && mode != TDmode ) ) return true ; } break ; case CC_REGS : if ( GET_MODE_CLASS ( mode ) == MODE_CC ) return true ; break ; case ACCESS_REGS : if ( REGNO_PAIR_OK ( regno , mode ) ) { if ( mode == SImode || mode == Pmode ) return true ; } break ; default : return false ; } return false ; } </s>

Return true if it is legal to put a value with MODE into REGNO .


<s> bool AlphaTargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createAlphaBranchSelectionPass ( ) ) ; PM . add ( createAlphaLLRPPass ( * this ) ) ; return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
bool
runOnMachineFunction
(
MachineFunction
&
MF
)
override
{
Subtarget
=
&
MF
.
getSubtarget
<
X86Subtarget
>
(
)
;
IndirectTlsSegRefs
=
MF
.
getFunction
(
)
.
hasFnAttribute
(
"indirect-tls-seg-refs"
)
;
OptForSize
=
MF
.
getFunction
(
)
.
hasOptSize
(
)
;
OptForMinSize
=
MF
.
getFunction
(
)
.
hasMinSize
(
)
;
assert
(
(
!
OptForMinSize
||
OptForSize
)
&&
"OptForMinSize implies OptForSize"
)
;
SelectionDAGISel
::
runOnMachineFunction
(
MF
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static inline CSKYTargetStreamer :: SymbolIndex getTombstoneKey ( ) { return { nullptr , CSKYMCExpr :: VK_CSKY_Invalid } ; } </s>

Difference in tombstone is that the Optional is meaningful .


<s>
virtual
const
char
*
getPassName
(
)
const
override
{
return
"SI Fix SGPR live ranges"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void WebAssemblyPassConfig :: addPreRegAlloc ( ) { } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s>
SUnit
*
ConvergingVLIWScheduler
::
pickNodeBidrectional
(
bool
&
IsTopNode
)
{
if
(
SUnit
*
SU
=
Bot
.
pickOnlyChoice
(
)
)
{
DEBUG
(
dbgs
(
)
<<
"Picked only Bottom\n"
)
;
IsTopNode
=
false
;
return
SU
;
}
if
(
SUnit
*
SU
=
Top
.
pickOnlyChoice
(
)
)
{
DEBUG
(
dbgs
(
)
<<
"Picked only Top\n"
)
;
IsTopNode
=
true
;
return
SU
;
}
SchedCandidate
BotCand
;
CandResult
BotResult
=
pickNodeFromQueue
(
Bot
.
Available
,
DAG
->
getBotRPTracker
(
)
,
BotCand
)
;
assert
(
BotResult
!=
NoCand
&&
"failed to find the first candidate"
)
;
if
(
BotResult
==
SingleExcess
||
BotResult
==
SingleCritical
)
{
DEBUG
(
dbgs
(
)
<<
"Prefered Bottom Node\n"
)
;
IsTopNode
=
false
;
return
BotCand
.
SU
;
}
SchedCandidate
TopCand
;
CandResult
TopResult
=
pickNodeFromQueue
(
Top
.
Available
,
DAG
->
getTopRPTracker
(
)
,
TopCand
)
;
assert
(
TopResult
!=
NoCand
&&
"failed to find the first candidate"
)
;
if
(
TopResult
==
SingleExcess
||
TopResult
==
SingleCritical
)
{
DEBUG
(
dbgs
(
)
<<
"Prefered Top Node\n"
)
;
IsTopNode
=
true
;
return
TopCand
.
SU
;
}
if
(
BotResult
==
SingleMax
)
{
DEBUG
(
dbgs
(
)
<<
"Prefered Bottom Node SingleMax\n"
)
;
IsTopNode
=
false
;
return
BotCand
.
SU
;
}
if
(
TopResult
==
SingleMax
)
{
DEBUG
(
dbgs
(
)
<<
"Prefered Top Node SingleMax\n"
)
;
IsTopNode
=
true
;
return
TopCand
.
SU
;
}
if
(
TopCand
.
SCost
>
BotCand
.
SCost
)
{
DEBUG
(
dbgs
(
)
<<
"Prefered Top Node Cost\n"
)
;
IsTopNode
=
true
;
return
TopCand
.
SU
;
}
DEBUG
(
dbgs
(
)
<<
"Prefered Bottom in Node order\n"
)
;
IsTopNode
=
false
;
return
BotCand
.
SU
;
}
</s>

Pick the best candidate node from either the top or bottom queue .

Hexagon
"Picked only Bottom\n"
"Picked only Top\n"
"failed to find the first candidate"
"Prefered Bottom Node\n"
"failed to find the first candidate"
"Prefered Top Node\n"
"Prefered Bottom Node SingleMax\n"
"Prefered Top Node SingleMax\n"
"Prefered Top Node Cost\n"
"Prefered Bottom in Node order\n"


<s> bool enableIndirectBrExpand ( ) const override { return useRetpolineIndirectBranches ( ) ; } </s>

If we are using indirect thunks , we need to expand indirectbr to avoid it lowering to an actual indirect jump .


<s> unsigned PPCFastISel :: fastEmitInst_rr ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , unsigned Op1 ) { const TargetRegisterClass * UseRC = ( RC == & PPC :: GPRCRegClass ? & PPC :: GPRC_and_GPRC_NOR0RegClass : ( RC == & PPC :: G8RCRegClass ? & PPC :: G8RC_and_G8RC_NOX0RegClass : RC ) ) ; return FastISel :: fastEmitInst_rr ( MachineInstOpcode , UseRC , Op0 , Op1 ) ; } </s>

Emit a MachineInstr with two register operands and a result register in the given register class .


<s> bool AArch64InstrInfo :: isAssociativeAndCommutative ( const MachineInstr & Inst ) const { switch ( Inst . getOpcode ( ) ) { case AArch64 :: FADDDrr : case AArch64 :: FADDSrr : case AArch64 :: FADDv2f32 : case AArch64 :: FADDv2f64 : case AArch64 :: FADDv4f32 : case AArch64 :: FMULDrr : case AArch64 :: FMULSrr : case AArch64 :: FMULX32 : case AArch64 :: FMULX64 : case AArch64 :: FMULXv2f32 : case AArch64 :: FMULXv2f64 : case AArch64 :: FMULXv4f32 : case AArch64 :: FMULv2f32 : case AArch64 :: FMULv2f64 : case AArch64 :: FMULv4f32 : return Inst . getParent ( ) -> getParent ( ) -> getTarget ( ) . Options . UnsafeFPMath ; default : return false ; } } </s>

Return true when \P Inst is both associative and commutative .


<s> bool isTarget64BitILP32 ( ) const { if ( NaClDontBreakABI ) { return In64BitMode && ( TargetTriple . getEnvironment ( ) == Triple :: GNUX32 ) ; } return In64BitMode && ( TargetTriple . getEnvironment ( ) == Triple :: GNUX32 || TargetTriple . isOSNaCl ( ) ) ; } </s>

Is this x86_64 with the ILP32 programming model ( x32 ABI ) ?


<s> static rtx aarch64_expand_sve_const_pred ( rtx target , rtx_vector_builder & builder ) { if ( rtx res = aarch64_expand_sve_const_pred_1 ( target , builder , true ) ) return res ; if ( builder . full_nelts ( ) . is_constant ( ) ) if ( rtx mem = force_const_mem ( VNx16BImode , builder . build ( ) ) ) { target = aarch64_target_reg ( target , VNx16BImode ) ; emit_move_insn ( target , mem ) ; return target ; } rtx_vector_builder int_builder ( VNx16QImode , builder . npatterns ( ) , builder . nelts_per_pattern ( ) ) ; for ( unsigned int i = 0 ; i < builder . encoded_nelts ( ) ; ++ i ) int_builder . quick_push ( INTVAL ( builder . elt ( i ) ) ? constm1_rtx : const0_rtx ) ; return aarch64_convert_sve_data_to_pred ( target , VNx16BImode , int_builder . build ( ) ) ; } </s>

Return an SVE predicate register that contains the VNx16BImode constant in BUILDER , without going through the move expanders . The returned register can have whatever mode seems most natural given the contents of BUILDER . Use TARGET for the result if convenient .


<s> bool SystemZAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { SystemZInstPrinter :: printAddress ( MI -> getOperand ( OpNo ) . getReg ( ) , MI -> getOperand ( OpNo + 1 ) . getImm ( ) , MI -> getOperand ( OpNo + 2 ) . getReg ( ) , OS ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> static bool mips_in_small_data_p ( tree decl ) { HOST_WIDE_INT size ; if ( TREE_CODE ( decl ) == STRING_CST || TREE_CODE ( decl ) == FUNCTION_DECL ) return false ; if ( TARGET_ABICALLS ) return false ; if ( TREE_CODE ( decl ) == VAR_DECL && DECL_SECTION_NAME ( decl ) != 0 ) { const char * name ; name = TREE_STRING_POINTER ( DECL_SECTION_NAME ( decl ) ) ; if ( strcmp ( name , ".sdata" ) != 0 && strcmp ( name , ".sbss" ) != 0 ) return false ; if ( TARGET_EXPLICIT_RELOCS || ! DECL_EXTERNAL ( decl ) ) return true ; } else if ( TARGET_EMBEDDED_DATA ) { if ( TREE_CODE ( decl ) != VAR_DECL ) return false ; if ( TREE_READONLY ( decl ) && ! TREE_SIDE_EFFECTS ( decl ) && ( ! DECL_INITIAL ( decl ) || TREE_CONSTANT ( DECL_INITIAL ( decl ) ) ) ) return false ; } size = int_size_in_bytes ( TREE_TYPE ( decl ) ) ; return ( size > 0 && size <= mips_section_threshold ) ; } </s>

Implement TARGET_IN_SMALL_DATA_P . Return true if it would be safe to access DECL using % gp_rel ( ... ) ( $ gp ) .


<s> unsigned SystemZTTIImpl :: getNumberOfRegisters ( bool Vector ) { if ( ! Vector ) return 14 ; if ( ST -> hasVector ( ) ) return 32 ; return 0 ; } </s>


"****** Hexagon Branch Relaxation ******\n"


<s> void SNESFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static int vfp_emit_fstmd ( int base_reg , int count ) { rtx par ; rtx dwarf ; rtx tmp , reg ; int i ; if ( count == 2 && ! arm_arch6 ) { if ( base_reg == LAST_VFP_REGNUM - 3 ) base_reg -= 2 ; count ++ ; } if ( count > 16 ) { int saved ; saved = vfp_emit_fstmd ( base_reg + 32 , count - 16 ) ; saved += vfp_emit_fstmd ( base_reg , 16 ) ; return saved ; } par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; dwarf = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( count + 1 ) ) ; reg = gen_rtx_REG ( DFmode , base_reg ) ; base_reg += 2 ; XVECEXP ( par , 0 , 0 ) = gen_rtx_SET ( gen_frame_mem ( BLKmode , gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - ( count * 8 ) ) ) ) , gen_rtx_UNSPEC ( BLKmode , gen_rtvec ( 1 , reg ) , UNSPEC_PUSH_MULT ) ) ; tmp = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - ( count * 8 ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , 0 ) = tmp ; tmp = gen_rtx_SET ( gen_frame_mem ( DFmode , stack_pointer_rtx ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , 1 ) = tmp ; for ( i = 1 ; i < count ; i ++ ) { reg = gen_rtx_REG ( DFmode , base_reg ) ; base_reg += 2 ; XVECEXP ( par , 0 , i ) = gen_rtx_USE ( VOIDmode , reg ) ; tmp = gen_rtx_SET ( gen_frame_mem ( DFmode , plus_constant ( Pmode , stack_pointer_rtx , i * 8 ) ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , i + 1 ) = tmp ; } par = emit_insn ( par ) ; add_reg_note ( par , REG_FRAME_RELATED_EXPR , dwarf ) ; RTX_FRAME_RELATED_P ( par ) = 1 ; return count * 8 ; } </s>

Emit RTL to save block of VFP register pairs to the stack . Returns the number of bytes pushed .


<s> bool MVEGatherScatterLowering :: runOnFunction ( Function & F ) { if ( ! EnableMaskedGatherScatters ) return false ; auto & TPC = getAnalysis < TargetPassConfig > ( ) ; auto & TM = TPC . getTM < TargetMachine > ( ) ; auto * ST = & TM . getSubtarget < ARMSubtarget > ( F ) ; if ( ! ST -> hasMVEIntegerOps ( ) ) return false ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SmallVector < IntrinsicInst * , 4 > Gathers ; SmallVector < IntrinsicInst * , 4 > Scatters ; bool Changed = false ; for ( BasicBlock & BB : F ) { Changed |= SimplifyInstructionsInBlock ( & BB ) ; for ( Instruction & I : BB ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & I ) ; if ( II && II -> getIntrinsicID ( ) == Intrinsic :: masked_gather && isa < FixedVectorType > ( II -> getType ( ) ) ) { Gathers . push_back ( II ) ; Changed |= optimiseAddress ( II -> getArgOperand ( 0 ) , II -> getParent ( ) , LI ) ; } else if ( II && II -> getIntrinsicID ( ) == Intrinsic :: masked_scatter && isa < FixedVectorType > ( II -> getArgOperand ( 0 ) -> getType ( ) ) ) { Scatters . push_back ( II ) ; Changed |= optimiseAddress ( II -> getArgOperand ( 1 ) , II -> getParent ( ) , LI ) ; } } } for ( unsigned i = 0 ; i < Gathers . size ( ) ; i ++ ) { IntrinsicInst * I = Gathers [ i ] ; Value * L = lowerGather ( I ) ; if ( L == nullptr ) continue ; SimplifyInstructionsInBlock ( cast < Instruction > ( L ) -> getParent ( ) ) ; Changed = true ; } for ( unsigned i = 0 ; i < Scatters . size ( ) ; i ++ ) { IntrinsicInst * I = Scatters [ i ] ; Value * S = lowerScatter ( I ) ; if ( S == nullptr ) continue ; SimplifyInstructionsInBlock ( cast < Instruction > ( S ) -> getParent ( ) ) ; Changed = true ; } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> VESubtarget & VESubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { EnableVPU = false ; std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) ) CPUName = "generic" ; ParseSubtargetFeatures ( CPUName , CPU , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool ARCPassConfig :: addInstSelector ( ) { addPass ( createARCISelDag ( getARCTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static machine_mode rx_promote_function_mode ( const_tree type ATTRIBUTE_UNUSED , machine_mode mode , int * punsignedp ATTRIBUTE_UNUSED , const_tree funtype ATTRIBUTE_UNUSED , int for_return ) { if ( for_return != 1 || GET_MODE_SIZE ( mode ) >= 4 || COMPLEX_MODE_P ( mode ) || VECTOR_MODE_P ( mode ) || VECTOR_TYPE_P ( type ) || GET_MODE_SIZE ( mode ) < 1 ) return mode ; return SImode ; } </s>

TARGET_PROMOTE_FUNCTION_MODE must behave in the same way with regard to function returns as does TARGET_FUNCTION_VALUE .


<s> static void ix86_emit_move_max ( rtx dst , rtx src ) { ix86_emit_cmove ( dst , src , LTU , dst , src ) ; } </s>

Choose max of DST and SRC and put it to DST .


<s> bool RISCVInstPrinter :: applyTargetSpecificCLOption ( StringRef Opt ) { if ( Opt == "no-aliases" ) { NoAliases = true ; return true ; } if ( Opt == "numeric" ) { ArchRegNames = true ; return true ; } return false ; } </s>

Customize the printer according to a command line option .


<s> static bool alpha_vector_mode_supported_p ( enum machine_mode mode ) { return mode == V8QImode || mode == V4HImode || mode == V2SImode ; } </s>

Alpha implements a couple of integer vector mode operations when TARGET_MAX is enabled . We do not check TARGET_MAX here , however , which allows the vectorizer to operate on e.g . move instructions , or when expand_vector_operations can do something useful .


<s> static bool c6x_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) { int size = - 1 ; if ( arg . type ) size = int_size_in_bytes ( arg . type ) ; else if ( arg . mode != VOIDmode ) size = GET_MODE_SIZE ( arg . mode ) ; return size > 2 * UNITS_PER_WORD || size == - 1 ; } </s>

Types larger than 64 bit , and variable sized types , are passed by reference . The callee must copy them ; see c6x_callee_copies .


getTargetNodeName - This method returns the name of a target specific


<s> unsigned int rs6000_cost_data :: determine_suggested_unroll_factor ( loop_vec_info loop_vinfo ) { class loop * loop = LOOP_VINFO_LOOP ( loop_vinfo ) ; if ( loop -> unroll == 1 || ( OPTION_SET_P ( flag_unroll_loops ) && ! flag_unroll_loops ) || ( OPTION_SET_P ( flag_unroll_all_loops ) && ! flag_unroll_all_loops ) ) return 1 ; unsigned int nstmts_nonldst = m_nstmts - m_nloads - m_nstores ; if ( nstmts_nonldst == 0 ) return 1 ; unsigned int reduc_factor = m_reduc_factor > 1 ? m_reduc_factor : 1 ; unsigned int issue_width = rs6000_vect_unroll_issue ; unsigned int uf = CEIL ( reduc_factor * issue_width , nstmts_nonldst ) ; uf = MIN ( ( unsigned int ) rs6000_vect_unroll_limit , uf ) ; uf = 1 << ceil_log2 ( uf ) ; if ( LOOP_VINFO_NITERS_KNOWN_P ( loop_vinfo ) ) return uf ; if ( reduc_factor > ( unsigned int ) rs6000_vect_unroll_reduc_threshold || m_gather_load ) return uf ; HOST_WIDE_INT est_niter = get_estimated_loop_iterations_int ( loop ) ; unsigned int vf = vect_vf_for_cost ( loop_vinfo ) ; unsigned int unrolled_vf = vf * uf ; if ( est_niter == - 1 || est_niter < unrolled_vf ) return 1 ; else { unsigned int epil_niter_unr = est_niter % unrolled_vf ; unsigned int epil_niter = est_niter % vf ; if ( LOOP_VINFO_CAN_USE_PARTIAL_VECTORS_P ( loop_vinfo ) && epil_niter_unr <= vf ) return uf ; else if ( ! LOOP_VINFO_CAN_USE_PARTIAL_VECTORS_P ( loop_vinfo ) && epil_niter_unr <= epil_niter ) return uf ; } return 1 ; } </s>

Determine suggested unroll factor by considering some below factors : - unroll option/pragma which can disable unrolling for this loop ; - simple hardware resource model for non memory vector insns ; - aggressive heuristics when iteration count is unknown : - reduction case to break cross iteration dependency ; - emulated gather load ; - estimated iteration count when iteration count is unknown ;


<s> static bool loongarch_valid_base_register_p ( rtx x , machine_mode mode , bool strict_p ) { if ( ! strict_p && SUBREG_P ( x ) ) x = SUBREG_REG ( x ) ; return ( REG_P ( x ) && loongarch_regno_mode_ok_for_base_p ( REGNO ( x ) , mode , strict_p ) ) ; } </s>

Return true if X is a valid base register for mode MODE . STRICT_P is true if REG_OK_STRICT is in effect .


"IR compiled to PTX must have nvvm.annotations"

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> static void emit_load_locked ( machine_mode mode , rtx reg , rtx mem ) { rtx ( * fn ) ( rtx , rtx ) = NULL ; switch ( mode ) { case QImode : fn = gen_load_lockedqi ; break ; case HImode : fn = gen_load_lockedhi ; break ; case SImode : if ( GET_MODE ( mem ) == QImode ) fn = gen_load_lockedqi_si ; else if ( GET_MODE ( mem ) == HImode ) fn = gen_load_lockedhi_si ; else fn = gen_load_lockedsi ; break ; case DImode : fn = gen_load_lockeddi ; break ; case TImode : fn = gen_load_lockedti ; break ; default : gcc_unreachable ( ) ; } emit_insn ( fn ( reg , mem ) ) ; } </s>

A subroutine of the atomic operation splitters . Emit a load-locked instruction in MODE . For QI/HImode , possibly use a pattern than includes the zero_extend operation .


<s>
bool
Z80oldDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
SDValue
Op0
,
Op1
;
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_m
:
if
(
!
SelectMem
(
Op
,
Op0
)
)
{
return
true
;
}
OutOps
.
push_back
(
Op0
)
;
return
false
;
case
InlineAsm
::
Constraint_o
:
if
(
!
SelectOff
(
Op
,
Op0
,
Op1
)
)
{
return
true
;
}
OutOps
.
push_back
(
Op0
)
;
OutOps
.
push_back
(
Op1
)
;
return
false
;
}
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> static rtx frv_expand_mwtacc_builtin ( enum insn_code icode , tree arglist ) { rtx pat ; rtx op0 = frv_read_argument ( & arglist ) ; rtx op1 = frv_read_argument ( & arglist ) ; op0 = frv_int_to_acc ( icode , 0 , op0 ) ; if ( ! op0 ) return NULL_RTX ; op1 = frv_legitimize_argument ( icode , 1 , op1 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( pat ) emit_insn ( pat ) ; return NULL_RTX ; } </s>

Expand MWTACC and MWTACCG . These builtins take an accumulator or accumulator guard as their first argument and an SImode value as their second .


<s>
bool
AArch64InstrInfo
::
isGPRCopy
(
const
MachineInstr
&
MI
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
TargetOpcode
::
COPY
:
{
unsigned
DstReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
return
(
AArch64
::
GPR32RegClass
.
contains
(
DstReg
)
||
AArch64
::
GPR64RegClass
.
contains
(
DstReg
)
)
;
}
case
AArch64
::
ORRXrs
:
if
(
MI
.
getOperand
(
1
)
.
getReg
(
)
==
AArch64
::
XZR
)
{
assert
(
MI
.
getDesc
(
)
.
getNumOperands
(
)
==
4
&&
MI
.
getOperand
(
3
)
.
getImm
(
)
==
0
&&
"invalid ORRrs operands"
)
;
return
true
;
}
break
;
case
AArch64
::
ADDXri
:
if
(
MI
.
getOperand
(
2
)
.
getImm
(
)
==
0
)
{
assert
(
MI
.
getDesc
(
)
.
getNumOperands
(
)
==
4
&&
MI
.
getOperand
(
3
)
.
getImm
(
)
==
0
&&
"invalid ADDXri operands"
)
;
return
true
;
}
break
;
}
return
false
;
}
</s>

Does this instruction rename a GPR without modifying bits ?


<s>
SDValue
SparcTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
llvm_unreachable
(
"TLS not implemented for Sparc."
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_SINT
(
Op
,
DAG
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerSINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
,
*
this
)
;
case
ISD
::
VAARG
:
return
LowerVAARG
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

Sparc
Sparc
"Should not custom lower this!"
ISD::RETURNADDR
ISD::FRAMEADDR
ISD::GlobalTLSAddress
"TLS not implemented for Sparc."
ISD::GlobalAddress
ISD::ConstantPool
ISD::FP_TO_SINT
ISD::SINT_TO_FP
ISD::BR_CC
ISD::SELECT_CC
ISD::VASTART
ISD::VAARG
ISD::DYNAMIC_STACKALLOC


<s> BitVector X86RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; Reserved . set ( X86 :: RSP ) ; Reserved . set ( X86 :: ESP ) ; Reserved . set ( X86 :: SP ) ; Reserved . set ( X86 :: SPL ) ; Reserved . set ( X86 :: RIP ) ; Reserved . set ( X86 :: EIP ) ; Reserved . set ( X86 :: IP ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( X86 :: RBP ) ; Reserved . set ( X86 :: EBP ) ; Reserved . set ( X86 :: BP ) ; Reserved . set ( X86 :: BPL ) ; } Reserved . set ( X86 :: ST0 ) ; Reserved . set ( X86 :: ST1 ) ; Reserved . set ( X86 :: ST2 ) ; Reserved . set ( X86 :: ST3 ) ; Reserved . set ( X86 :: ST4 ) ; Reserved . set ( X86 :: ST5 ) ; Reserved . set ( X86 :: ST6 ) ; Reserved . set ( X86 :: ST7 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> int getIORegRAMPZ ( void ) const { return hasELPM ( ) ? 0x3b : - 1 ; } </s>


<s>
CCAssignFn
*
AMDGPUCallLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
{
switch
(
CC
)
{
case
CallingConv
::
AMDGPU_KERNEL
:
case
CallingConv
::
SPIR_KERNEL
:
return
CC_AMDGPU_Kernel
;
case
CallingConv
::
AMDGPU_VS
:
case
CallingConv
::
AMDGPU_GS
:
case
CallingConv
::
AMDGPU_PS
:
case
CallingConv
::
AMDGPU_CS
:
case
CallingConv
::
AMDGPU_HS
:
case
CallingConv
::
AMDGPU_ES
:
case
CallingConv
::
AMDGPU_LS
:
return
CC_AMDGPU
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
case
CallingConv
::
Cold
:
return
CC_AMDGPU_Func
;
default
:
report_fatal_error
(
"Unsupported calling convention."
)
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .

AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
"Unsupported calling convention."


<s> bool MipsPassConfig :: addIRTranslator ( ) { addPass ( new IRTranslator ( ) ) ; return false ; } </s>

This method should install an IR translator pass , which converts from LLVM code to machine instructions with possibly generic opcodes .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { GlobalBaseReg = 0 ; PPCSubTarget = & MF . getSubtarget < PPCSubtarget > ( ) ; Subtarget = & MF . getSubtarget < PPCSubtarget > ( ) ; PPCLowering = Subtarget -> getTargetLowering ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> static section * rx_select_rtx_section ( machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ) { if ( rx_small_data_limit > 0 && GET_MODE_SIZE ( mode ) <= rx_small_data_limit && align <= ( unsigned HOST_WIDE_INT ) rx_small_data_limit * BITS_PER_UNIT ) return sdata_section ; return default_elf_select_rtx_section ( mode , x , align ) ; } </s>

Return a section for X . The only special thing we do here is to honor small data .


<s> static int current_file_function_operand ( rtx sym_ref ) { if ( ENCODED_SHORT_CALL_ATTR_P ( XSTR ( sym_ref , 0 ) ) ) return 1 ; if ( sym_ref == XEXP ( DECL_RTL ( current_function_decl ) , 0 ) && ! DECL_WEAK ( current_function_decl ) ) return 1 ; return 0 ; } </s>

Return 1 if the operand is a SYMBOL_REF for a function known to be in this file and the function is not weakly defined .


<s> bool PPCAsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { if ( getLexer ( ) . is ( AsmToken :: Plus ) ) { getLexer ( ) . Lex ( ) ; char * NewOpcode = new char [ Name . size ( ) + 1 ] ; memcpy ( NewOpcode , Name . data ( ) , Name . size ( ) ) ; NewOpcode [ Name . size ( ) ] = '+' ; Name = StringRef ( NewOpcode , Name . size ( ) + 1 ) ; } if ( getLexer ( ) . is ( AsmToken :: Minus ) ) { getLexer ( ) . Lex ( ) ; char * NewOpcode = new char [ Name . size ( ) + 1 ] ; memcpy ( NewOpcode , Name . data ( ) , Name . size ( ) ) ; NewOpcode [ Name . size ( ) ] = '-' ; Name = StringRef ( NewOpcode , Name . size ( ) + 1 ) ; } size_t Dot = Name . find ( '.' ) ; StringRef Mnemonic = Name . slice ( 0 , Dot ) ; Operands . push_back ( PPCOperand :: CreateToken ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; if ( Dot != StringRef :: npos ) { SMLoc DotLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Dot ) ; StringRef DotStr = Name . slice ( Dot , StringRef :: npos ) ; Operands . push_back ( PPCOperand :: CreateToken ( DotStr , DotLoc , isPPC64 ( ) ) ) ; } if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( ParseOperand ( Operands ) ) return true ; while ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) && getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( ParseOperand ( Operands ) ) return true ; } return false ; } </s>

ParseInstruction - Parse one assembly instruction .


<s> StringRef getPassName ( ) const override { return RISCV_MERGE_BASE_OFFSET_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> const X86InstrInfo * getInstrInfo ( ) const override { return getSubtargetImpl ( ) -> getInstrInfo ( ) ; } </s>


"alias without a base object is not yet supported on AIX"

Set up the AsmPrinter when we are working on a new module .


<s> unsigned getInstSizeInBytes ( const MachineInstr & MI ) const override { return 4U ; } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> void PPCELFStreamer :: emitLabel ( MCSymbol * Symbol , SMLoc Loc ) { LastLabel = Symbol ; LastLabelLoc = Loc ; MCELFStreamer :: emitLabel ( Symbol ) ; } </s>

Emit a label for Symbol into the current section .


"SIInstrInfo::storeRegToStackSlot - Do not know how to"

Store the specified register of the given register class to the specified stack frame index .


<s> unsigned int execute ( function * ) { return nds32_fp_as_gp ( ) ; } </s>


<s> unsigned getNumFixupKinds ( ) const override { return SystemZ :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s>
std
::
vector
<
const
SUnit
*
>
GCNMinRegScheduler
::
schedule
(
ArrayRef
<
const
SUnit
*
>
TopRoots
,
const
ScheduleDAG
&
DAG
)
{
const
auto
&
SUnits
=
DAG
.
SUnits
;
std
::
vector
<
const
SUnit
*
>
Schedule
;
Schedule
.
reserve
(
SUnits
.
size
(
)
)
;
initNumPreds
(
SUnits
)
;
int
StepNo
=
0
;
for
(
auto
SU
:
TopRoots
)
{
RQ
.
push_back
(
*
new
(
Alloc
.
Allocate
(
)
)
Candidate
(
SU
,
StepNo
)
)
;
}
releaseSuccessors
(
&
DAG
.
EntrySU
,
StepNo
)
;
while
(
!
RQ
.
empty
(
)
)
{
DEBUG
(
dbgs
(
)
<<
"\n=== Picking candidate, Step = "
<<
StepNo
<<
"\n"
"Ready queue:"
;
for
(
auto
&
C
:
RQ
)
dbgs
(
)
<<
' '
<<
C
.
SU
->
NodeNum
<<
"(P"
<<
C
.
Priority
<<
')'
;
dbgs
(
)
<<
'\n'
;
)
;
auto
C
=
pickCandidate
(
)
;
assert
(
C
)
;
RQ
.
remove
(
*
C
)
;
auto
SU
=
C
->
SU
;
DEBUG
(
dbgs
(
)
<<
"Selected "
;
SU
->
dump
(
&
DAG
)
)
;
releaseSuccessors
(
SU
,
StepNo
)
;
Schedule
.
push_back
(
SU
)
;
setIsScheduled
(
SU
)
;
if
(
getReadySuccessors
(
SU
)
==
0
)
bumpPredsPriority
(
SU
,
StepNo
)
;
++
StepNo
;
}
assert
(
SUnits
.
size
(
)
==
Schedule
.
size
(
)
)
;
return
Schedule
;
}
</s>

Schedule - This is called back from ScheduleDAGInstrs : :Run ( ) when it 's time to do some work .

AMDGPU
0
"\n=== Picking candidate, Step = "
"\n"
"Ready queue:"
"(P"
"Selected "
0


<s> void TOYFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = computeStackSize ( MF ) ; if ( ! StackSize ) { return ; } unsigned StackReg = TOY :: SP ; unsigned OffsetReg = materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ; if ( OffsetReg ) { BuildMI ( MBB , MBBI , dl , TII . get ( TOY :: SUBrr ) , StackReg ) . addReg ( StackReg ) . addReg ( OffsetReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( TOY :: SUBri ) , StackReg ) . addReg ( StackReg ) . addImm ( StackSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static void mips_start_ll_sc_sync_block ( void ) { if ( ! ISA_HAS_LL_SC ) { output_asm_insn ( ".set\tpush" , 0 ) ; if ( TARGET_64BIT ) output_asm_insn ( ".set\tmips3" , 0 ) ; else output_asm_insn ( ".set\tmips2" , 0 ) ; } } </s>

Start a block of code that needs access to the LL , SC and SYNC instructions .


<s> static int m32c_leaf_function_p ( void ) { rtx saved_first , saved_last ; struct sequence_stack * seq ; int rv ; saved_first = cfun -> emit -> x_first_insn ; saved_last = cfun -> emit -> x_last_insn ; for ( seq = cfun -> emit -> sequence_stack ; seq && seq -> next ; seq = seq -> next ) ; if ( seq ) { cfun -> emit -> x_first_insn = seq -> first ; cfun -> emit -> x_last_insn = seq -> last ; } rv = leaf_function_p ( ) ; cfun -> emit -> x_first_insn = saved_first ; cfun -> emit -> x_last_insn = saved_last ; return rv ; } </s>

Returns TRUE if the current function is a leaf , and thus we can determine which registers an interrupt function really needs to save . The logic below is mostly about finding the insn sequence that 's the function , versus any sequence that might be open for the current insn .


<s> static enum reg_class init_unavailable ( tag_insn_info * insn_info , tag_map_t & tag_map , du_head_p head , HARD_REG_SET * unavailable ) { unsigned dest = head -> regno ; enum reg_class super_class = NO_REGS ; machine_mode mode = GET_MODE ( insn_info -> dest ) ; CLEAR_HARD_REG_SET ( * unavailable ) ; for ( struct du_chain * tmp = head -> first ; tmp ; tmp = tmp -> next_use ) { if ( DEBUG_INSN_P ( tmp -> insn ) ) continue ; IOR_COMPL_HARD_REG_SET ( * unavailable , reg_class_contents [ tmp -> cl ] ) ; super_class = reg_class_superunion [ ( int ) super_class ] [ ( int ) tmp -> cl ] ; } for ( unsigned i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( fixed_regs [ i ] || global_regs [ i ] ) add_to_hard_reg_set ( unavailable , mode , i ) ; arg_pair_t arg = arg_pair_t ( insn_info , unavailable ) ; tag_map . traverse < arg_pair_t * , check_colliding_tags > ( & arg ) ; ignore_all_aliases ( unavailable , mode , dest & 0xf ) ; return super_class ; } </s>

Initialize and build a set of hard register numbers UNAVAILABLE to avoid for renaming . INSN_INFO is the original insn , TAG_MAP is the map of the list of insns indexed by their tags , HEAD is the def/use chain head of the destination register of the original insn . The routine returns the super class of register classes that may be used during the renaming .


<s>
unsigned
MipsABIInfo
::
GetCalleeAllocdArgSizeInBytes
(
CallingConv
::
ID
CC
)
const
{
if
(
IsO32
(
)
)
return
CC
!=
CallingConv
::
Fast
16
:
0
;
if
(
IsN32
(
)
||
IsN64
(
)
)
return
0
;
llvm_unreachable
(
"Unhandled ABI"
)
;
}
</s>

Obtain the size of the area allocated by the callee for arguments .


Output the assembly for a call instruction .


<s> unsigned SIInstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { MachineBasicBlock :: iterator I = MBB . getFirstTerminator ( ) ; unsigned Count = 0 ; unsigned RemovedSize = 0 ; while ( I != MBB . end ( ) ) { MachineBasicBlock :: iterator Next = std :: next ( I ) ; if ( I -> getOpcode ( ) == AMDGPU :: SI_MASK_BRANCH ) { I = Next ; continue ; } RemovedSize += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ; ++ Count ; I = Next ; } if ( BytesRemoved ) * BytesRemoved = RemovedSize ; return Count ; } </s>

Remove the branching code at the end of the specific MBB .


<s> bool AArch64TargetLowering :: shouldReduceLoadWidth ( SDNode * Load , ISD :: LoadExtType ExtTy , EVT NewVT ) const { if ( ! TargetLoweringBase :: shouldReduceLoadWidth ( Load , ExtTy , NewVT ) ) return false ; if ( ExtTy != ISD :: NON_EXTLOAD ) return true ; MemSDNode * Mem = dyn_cast < MemSDNode > ( Load ) ; assert ( Mem ) ; const SDValue & Base = Mem -> getBasePtr ( ) ; if ( Base . getOpcode ( ) == ISD :: ADD && Base . getOperand ( 1 ) . getOpcode ( ) == ISD :: SHL && Base . getOperand ( 1 ) . hasOneUse ( ) && Base . getOperand ( 1 ) . getOperand ( 1 ) . getOpcode ( ) == ISD :: Constant ) { uint64_t ShiftAmount = Base . getOperand ( 1 ) . getConstantOperandVal ( 1 ) ; uint64_t LoadBytes = Mem -> getMemoryVT ( ) . getSizeInBits ( ) / 8 ; if ( ShiftAmount == Log2_32 ( LoadBytes ) ) return false ; } return true ; } </s>

Return true if we believe it is correct and profitable to reduce the load node to a smaller type .


<s> static bool originalEVTTypeIsVectorFloat ( EVT Ty ) { if ( Ty . isVector ( ) && Ty . getVectorElementType ( ) . isFloatingPoint ( ) ) return true ; return false ; } </s>

Return true if the original type was vXfXX .


<s> bool supportSwiftError ( ) const override { return true ; } </s>

Return true if the target supports swifterror attribute .


<s> const uint16_t * MipsRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_SaveList ; else if ( ! Subtarget . hasMips64 ( ) ) return CSR_O32_SaveList ; else if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_SaveList ; assert ( Subtarget . isABI_N64 ( ) ) ; return CSR_N64_SaveList ; } </s>


<s> static void seh_emit_push ( FILE * f , struct seh_frame_state * seh , rtx reg ) { const unsigned int regno = REGNO ( reg ) ; gcc_checking_assert ( GENERAL_REGNO_P ( regno ) ) ; seh -> sp_offset += UNITS_PER_WORD ; seh -> reg_offset [ regno ] = seh -> sp_offset ; if ( seh -> cfa_reg == stack_pointer_rtx ) seh -> cfa_offset += UNITS_PER_WORD ; fputs ( "\t.seh_pushreg\t" , f ) ; print_reg ( reg , 0 , f ) ; fputc ( '\n' , f ) ; } </s>

Emit an assembler directive to save REG via a PUSH .


<s> void MMIXFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; SavedRegs . set ( MMIX :: r253 ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> void TPCPassConfig :: addPreEmitPass ( ) { bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; addPass ( createTPCLutCacheCounter ( ) , false ) ; if ( ! NoOpt ) { addPass ( createTPCPacketizer ( ) , false ) ; } addPass ( createTPCUnHardwareLoops ( ) ) ; addPass ( createTPCLatencyResolver ( ) , false ) ; addPass ( createTPCPipelineRegs ( ) , false ) ; addPass ( createTPCCostModelEmitter ( ) , false ) ; addPass ( createTPCInstrCompress ( ) , false ) ; addPass ( createTPCRegisterCounter ( ) , false ) ; addPass ( createTPCElfSpecSet ( ) , false ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

TPC TPC TPC TPC TPC TPC TPC TPC TPC TPC TPC


<s> static void cris_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain_value ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx mem ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp , SImode , 10 ) ; emit_move_insn ( mem , chain_value ) ; mem = adjust_address ( m_tramp , SImode , 16 ) ; emit_move_insn ( mem , fnaddr ) ; } </s>


<s> bool HexagonExpandCondsets :: isPredicable ( MachineInstr * MI ) { if ( HII -> isPredicated ( * MI ) || ! HII -> isPredicable ( * MI ) ) return false ; if ( MI -> hasUnmodeledSideEffects ( ) || MI -> mayStore ( ) ) return false ; bool HasDef = false ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) ) continue ; if ( HasDef ) return false ; HasDef = true ; } for ( auto & Mo : MI -> memoperands ( ) ) if ( Mo -> isVolatile ( ) ) return false ; return true ; } </s>

Return true if the specified instruction can be predicated .


<s> bool X86TargetLowering :: convertSelectOfConstantsToMath ( EVT VT ) const { if ( VT . isVector ( ) && Subtarget . hasAVX512 ( ) ) return false ; return true ; } </s>

Return true if a select of constants ( select Cond , C1 , C2 ) should be transformed into simple math ops with the condition value .


"constant arithmetic operand out of range"

Detect and error out on out-of-range constants for addhi and subhi .


<s> unsigned char X86Subtarget :: classifyLocalReference ( const GlobalValue * GV ) const { if ( is64Bit ( ) ) return X86II :: MO_NO_FLAG ; if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) return X86II :: MO_NO_FLAG ; if ( isTargetCOFF ( ) ) return X86II :: MO_NO_FLAG ; if ( isTargetDarwin ( ) ) { if ( GV && ( GV -> isDeclarationForLinker ( ) || GV -> hasCommonLinkage ( ) ) ) return X86II :: MO_DARWIN_NONLAZY_PIC_BASE ; return X86II :: MO_PIC_BASE_OFFSET ; } return X86II :: MO_GOTOFF ; } </s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s> unsigned ARMBaseRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; const ARMFrameLowering * TFI = getFrameLowering ( MF ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case ARM :: tGPRRegClassID : { bool HasFP = MF . getFrameInfo ( ) . isMaxCallFrameSizeComputed ( ) ? TFI -> hasFP ( MF ) : true ; return 5 - HasFP ; } case ARM :: GPRRegClassID : { bool HasFP = MF . getFrameInfo ( ) . isMaxCallFrameSizeComputed ( ) ? TFI -> hasFP ( MF ) : true ; bool IsPagerando = MF . getFunction ( ) . isPagerando ( ) ; return 10 - HasFP - ( STI . isR9Reserved ( ) || IsPagerando ? 1 : 0 ) ; } case ARM :: SPRRegClassID : case ARM :: DPRRegClassID : return 32 - 10 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> static rtx frv_expand_voidbinop_builtin ( enum insn_code icode , tree arglist ) { rtx pat ; rtx op0 = frv_read_argument ( & arglist ) ; rtx op1 = frv_read_argument ( & arglist ) ; enum machine_mode mode0 = insn_data [ icode ] . operand [ 0 ] . mode ; rtx addr ; if ( GET_CODE ( op0 ) != MEM ) { rtx reg = op0 ; if ( ! offsettable_address_p ( 0 , mode0 , op0 ) ) { reg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , reg , op0 ) ) ; } op0 = gen_rtx_MEM ( SImode , reg ) ; } addr = XEXP ( op0 , 0 ) ; if ( ! offsettable_address_p ( 0 , mode0 , addr ) ) addr = copy_to_mode_reg ( Pmode , op0 ) ; op0 = change_address ( op0 , V4SImode , addr ) ; op1 = frv_legitimize_argument ( icode , 1 , op1 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return 0 ; } </s>

Expand builtins that take two operands , the first operand being a pointer to ints and return void .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 Atom pad short functions"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool MVEGatherScatterLowering :: runOnFunction ( Function & F ) { if ( ! EnableMaskedGatherScatters ) return false ; auto & TPC = getAnalysis < TargetPassConfig > ( ) ; auto & TM = TPC . getTM < TargetMachine > ( ) ; auto * ST = & TM . getSubtarget < ARMSubtarget > ( F ) ; if ( ! ST -> hasMVEIntegerOps ( ) ) return false ; SmallVector < IntrinsicInst * , 4 > Gathers ; SmallVector < IntrinsicInst * , 4 > Scatters ; LoopInfo & LI = getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & I ) ; if ( II && II -> getIntrinsicID ( ) == Intrinsic :: masked_gather ) Gathers . push_back ( II ) ; else if ( II && II -> getIntrinsicID ( ) == Intrinsic :: masked_scatter ) Scatters . push_back ( II ) ; } } bool Changed = false ; for ( unsigned i = 0 ; i < Gathers . size ( ) ; i ++ ) { IntrinsicInst * I = Gathers [ i ] ; if ( isa < GetElementPtrInst > ( I -> getArgOperand ( 0 ) ) ) optimiseOffsets ( cast < Instruction > ( I -> getArgOperand ( 0 ) ) -> getOperand ( 1 ) , I -> getParent ( ) , & LI ) ; Value * L = lowerGather ( I ) ; if ( L == nullptr ) continue ; SimplifyInstructionsInBlock ( cast < Instruction > ( L ) -> getParent ( ) ) ; Changed = true ; } for ( unsigned i = 0 ; i < Scatters . size ( ) ; i ++ ) { IntrinsicInst * I = Scatters [ i ] ; if ( isa < GetElementPtrInst > ( I -> getArgOperand ( 1 ) ) ) optimiseOffsets ( cast < Instruction > ( I -> getArgOperand ( 1 ) ) -> getOperand ( 1 ) , I -> getParent ( ) , & LI ) ; Value * S = lowerScatter ( I ) ; if ( S == nullptr ) continue ; SimplifyInstructionsInBlock ( cast < Instruction > ( S ) -> getParent ( ) ) ; Changed = true ; } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> ARMSubtarget :: ARMSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const ARMBaseTargetMachine & TM , bool IsLittle ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , UseMulOps ( UseFusedMulOps ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( ARMBaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( ARMBaseInstrInfo * ) new ARMInstrInfo ( * this ) : ( ARMBaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) { CallLoweringInfo . reset ( new ARMCallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new ARMLegalizerInfo ( * this ) ) ; auto * RBI = new ARMRegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( createARMInstructionSelector ( * static_cast < const ARMBaseTargetMachine * > ( & TM ) , * this , * RBI ) ) ; RegBankInfo . reset ( RBI ) ; } </s>

This constructor initializes the data members to match that of the specified triple .

ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM


"Can only insert epilog into returning blocks"


<s> static unsigned getSize ( unsigned Kind ) { switch ( Kind ) { default : return 4 ; case RISCV :: fixup_riscv_rvc_jump : case RISCV :: fixup_riscv_rvc_branch : return 2 ; } } </s>

Return the number of bytes in the encoding of this instruction , or zero if the encoding size can not be known from the opcode .


<s> bool MSP430InstrInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) BuildMI ( MBB , MI , DL , get ( MSP430 :: POP16r ) , CSI [ i ] . getReg ( ) ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


"TGSI Control Flow Graph structurizer Pass"


<s> iterator end ( ) const { return SubExceptions . end ( ) ; } </s>

Get a const_iterator to the end of the symbol table .


<s> SDValue SystemZDAGToDAGISel :: getUNDEF ( const SDLoc & DL , EVT VT ) const { SDNode * N = CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , DL , VT ) ; return SDValue ( N , 0 ) ; } </s>

Return an UNDEF node . UNDEF does not have a useful SDLoc .


<s> MachineBasicBlock * SITargetLowering :: EmitInstrWithCustomInserter ( MachineInstr * MI , MachineBasicBlock * BB ) const { MachineBasicBlock :: iterator I = * MI ; switch ( MI -> getOpcode ( ) ) { default : return AMDGPUTargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; case AMDGPU :: BRANCH : return BB ; case AMDGPU :: SI_ADDR64_RSRC : { const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( getTargetMachine ( ) . getInstrInfo ( ) ) ; MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; unsigned SuperReg = MI -> getOperand ( 0 ) . getReg ( ) ; unsigned SubRegLo = MRI . createVirtualRegister ( & AMDGPU :: SReg_64RegClass ) ; unsigned SubRegHi = MRI . createVirtualRegister ( & AMDGPU :: SReg_64RegClass ) ; unsigned SubRegHiHi = MRI . createVirtualRegister ( & AMDGPU :: SReg_32RegClass ) ; unsigned SubRegHiLo = MRI . createVirtualRegister ( & AMDGPU :: SReg_32RegClass ) ; BuildMI ( * BB , I , MI -> getDebugLoc ( ) , TII -> get ( AMDGPU :: S_MOV_B64 ) , SubRegLo ) . addOperand ( MI -> getOperand ( 1 ) ) ; BuildMI ( * BB , I , MI -> getDebugLoc ( ) , TII -> get ( AMDGPU :: S_MOV_B32 ) , SubRegHiLo ) . addImm ( 0 ) ; BuildMI ( * BB , I , MI -> getDebugLoc ( ) , TII -> get ( AMDGPU :: S_MOV_B32 ) , SubRegHiHi ) . addImm ( RSRC_DATA_FORMAT >> 32 ) ; BuildMI ( * BB , I , MI -> getDebugLoc ( ) , TII -> get ( AMDGPU :: REG_SEQUENCE ) , SubRegHi ) . addReg ( SubRegHiLo ) . addImm ( AMDGPU :: sub0 ) . addReg ( SubRegHiHi ) . addImm ( AMDGPU :: sub1 ) ; BuildMI ( * BB , I , MI -> getDebugLoc ( ) , TII -> get ( AMDGPU :: REG_SEQUENCE ) , SuperReg ) . addReg ( SubRegLo ) . addImm ( AMDGPU :: sub0_sub1 ) . addReg ( SubRegHi ) . addImm ( AMDGPU :: sub2_sub3 ) ; MI -> eraseFromParent ( ) ; break ; } } return BB ; } </s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> void BPFInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool RISCVELFTargetObjectFile :: isConstantInSmallSection ( const DataLayout & DL , const Constant * CN ) const { return isInSmallSection ( DL . getTypeAllocSize ( CN -> getType ( ) ) ) ; } </s>

Return true if this constant should be placed into small data section .


<s> TargetLowering :: ConstraintWeight PPCTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; if ( StringRef ( constraint ) == "wc" && type -> isIntegerTy ( 1 ) ) return CW_Register ; else if ( ( StringRef ( constraint ) == "wa" || StringRef ( constraint ) == "wd" || StringRef ( constraint ) == "wf" ) && type -> isVectorTy ( ) ) return CW_Register ; else if ( StringRef ( constraint ) == "ws" && type -> isDoubleTy ( ) ) return CW_Register ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'b' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; case 'd' : if ( type -> isDoubleTy ( ) ) weight = CW_Register ; break ; case 'v' : if ( type -> isVectorTy ( ) ) weight = CW_Register ; break ; case 'y' : weight = CW_Register ; break ; case 'Z' : weight = CW_Memory ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> static unsigned long csky_isr_value ( tree argument ) { const isr_attribute_entry * ptr ; const char * arg ; if ( argument == NULL_TREE ) return CSKY_FT_ISR ; if ( TREE_VALUE ( argument ) == NULL_TREE || TREE_CODE ( TREE_VALUE ( argument ) ) != STRING_CST ) return CSKY_FT_UNKNOWN ; arg = TREE_STRING_POINTER ( TREE_VALUE ( argument ) ) ; for ( ptr = isr_attribute_map ; ptr -> arg != NULL ; ptr ++ ) if ( strcmp ( arg , ptr -> arg ) == 0 ) return ptr -> return_value ; return CSKY_FT_UNKNOWN ; } </s>

Returns the ( interrupt ) function type of the current function , or CSKY_FT_UNKNOWN if the type can not be determined .


"sh_find_extending_set_of_reg: reg %d is "

"explicitly sign/zero extended in insn %d\n"

Given a reg and the current insn , see if the value of the reg originated from a sign or zero extension and return the discovered information .


<s> const TargetRegisterClass * SIRegisterInfo :: getCFGStructurizerRegClass ( MVT VT ) const { switch ( VT . SimpleTy ) { default : case MVT :: i32 : return & AMDGPU :: VReg_32RegClass ; } } </s>

get the register class of the specified type to use in the CFGStructurizer


<s> void MBlazeAsmPrinter :: emitFrameDirective ( ) { const TargetRegisterInfo & RI = * TM . getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) -> getStackSize ( ) ; O << "\t.frame\t" << getRegisterName ( stackReg ) << ',' << stackSize << ',' << getRegisterName ( returnReg ) << '\n' ; } </s>


<s> bool arc_legitimate_pic_addr_p ( rtx addr ) { if ( GET_CODE ( addr ) == LABEL_REF ) return true ; if ( GET_CODE ( addr ) != CONST ) return false ; addr = XEXP ( addr , 0 ) ; if ( GET_CODE ( addr ) == PLUS ) { if ( GET_CODE ( XEXP ( addr , 1 ) ) != CONST_INT ) return false ; addr = XEXP ( addr , 0 ) ; } if ( GET_CODE ( addr ) != UNSPEC || XVECLEN ( addr , 0 ) != 1 ) return false ; if ( XINT ( addr , 1 ) != ARC_UNSPEC_GOT && XINT ( addr , 1 ) != ARC_UNSPEC_GOTOFF ) return false ; if ( GET_CODE ( XVECEXP ( addr , 0 , 0 ) ) != SYMBOL_REF && GET_CODE ( XVECEXP ( addr , 0 , 0 ) ) != LABEL_REF ) return false ; return true ; } </s>

Return true if ADDR is a valid pic address . A valid pic address on arc should look like const ( unspec ( SYMBOL_REF/LABEL ) ( ARC_UNSPEC_GOTOFF/ARC_UNSPEC_GOT ) )


<s> bool enableAggressiveFMAFusion ( EVT VT ) const override { return true ; } </s>

Return true if target always benefits from combining into FMA for a given value type .


<s>
MCOperand
SystemZMCInstLower
::
lowerOperand
(
const
MachineOperand
&
MO
)
const
{
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
)
return
MCOperand
(
)
;
return
MCOperand
::
CreateReg
(
MO
.
getReg
(
)
)
;
case
MachineOperand
::
MO_Immediate
:
return
MCOperand
::
CreateImm
(
MO
.
getImm
(
)
)
;
case
MachineOperand
::
MO_MachineBasicBlock
:
return
lowerSymbolOperand
(
MO
,
MO
.
getMBB
(
)
->
getSymbol
(
)
,
0
)
;
case
MachineOperand
::
MO_GlobalAddress
:
return
lowerSymbolOperand
(
MO
,
Mang
->
getSymbol
(
MO
.
getGlobal
(
)
)
,
MO
.
getOffset
(
)
)
;
case
MachineOperand
::
MO_ExternalSymbol
:
{
StringRef
Name
=
MO
.
getSymbolName
(
)
;
return
lowerSymbolOperand
(
MO
,
AsmPrinter
.
GetExternalSymbolSymbol
(
Name
)
,
MO
.
getOffset
(
)
)
;
}
case
MachineOperand
::
MO_JumpTableIndex
:
return
lowerSymbolOperand
(
MO
,
AsmPrinter
.
GetJTISymbol
(
MO
.
getIndex
(
)
)
,
0
)
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
return
lowerSymbolOperand
(
MO
,
AsmPrinter
.
GetCPISymbol
(
MO
.
getIndex
(
)
)
,
MO
.
getOffset
(
)
)
;
case
MachineOperand
::
MO_BlockAddress
:
{
const
BlockAddress
*
BA
=
MO
.
getBlockAddress
(
)
;
return
lowerSymbolOperand
(
MO
,
AsmPrinter
.
GetBlockAddressSymbol
(
BA
)
,
MO
.
getOffset
(
)
)
;
}
}
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


Called at aarch64_resolve_overloaded_builtin in aarch64-c.cc .


<s> unsigned ARMScalarTargetTransformImpl :: getIntImmCost ( const APInt & Imm , Type * Ty ) const { assert ( Ty -> isIntegerTy ( ) ) ; unsigned Bits = Ty -> getPrimitiveSizeInBits ( ) ; if ( Bits == 0 || Bits > 32 ) return 4 ; int32_t SImmVal = Imm . getSExtValue ( ) ; uint32_t ZImmVal = Imm . getZExtValue ( ) ; if ( ! Subtarget -> isThumb ( ) ) { if ( ( SImmVal >= 0 && SImmVal < 65536 ) || ( ARM_AM :: getSOImmVal ( ZImmVal ) != - 1 ) || ( ARM_AM :: getSOImmVal ( ~ ZImmVal ) != - 1 ) ) return 1 ; return Subtarget -> hasV6T2Ops ( ) ? 2 : 3 ; } else if ( Subtarget -> isThumb2 ( ) ) { if ( ( SImmVal >= 0 && SImmVal < 65536 ) || ( ARM_AM :: getT2SOImmVal ( ZImmVal ) != - 1 ) || ( ARM_AM :: getT2SOImmVal ( ~ ZImmVal ) != - 1 ) ) return 1 ; return Subtarget -> hasV6T2Ops ( ) ? 2 : 3 ; } else { if ( SImmVal >= 0 && SImmVal < 256 ) return 1 ; if ( ( ~ ZImmVal < 256 ) || ARM_AM :: isThumbImmShiftedVal ( ZImmVal ) ) return 2 ; return 3 ; } return 2 ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> static inline int isa_base_compat_p ( const struct loongarch_isa * set1 , const struct loongarch_isa * set2 ) { switch ( set2 -> base ) { case ISA_BASE_LA64V100 : return ( set1 -> base == ISA_BASE_LA64V100 ) ; default : gcc_unreachable ( ) ; } } </s>


<s> static unsigned int aarch64_unspec_cond_code ( rtx_code code ) { switch ( code ) { case NE : return UNSPEC_COND_NE ; case EQ : return UNSPEC_COND_EQ ; case LT : return UNSPEC_COND_LT ; case GT : return UNSPEC_COND_GT ; case LE : return UNSPEC_COND_LE ; case GE : return UNSPEC_COND_GE ; case LTU : return UNSPEC_COND_LO ; case GTU : return UNSPEC_COND_HI ; case LEU : return UNSPEC_COND_LS ; case GEU : return UNSPEC_COND_HS ; case UNORDERED : return UNSPEC_COND_UO ; default : gcc_unreachable ( ) ; } } </s>

Return the UNSPEC_COND_ * code for comparison CODE .


Return the bytes needed to compute the frame pointer from the current stack pointer . SIZE is the size needed for local variables .


<s>
StringRef
getPassName
(
)
const
override
{
return
"ARM IR optimizations"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> int eligible_for_sibcall_delay ( rtx_insn * trial ) { rtx pat ; if ( get_attr_in_branch_delay ( trial ) == IN_BRANCH_DELAY_FALSE ) return 0 ; if ( ! NONJUMP_INSN_P ( trial ) ) return 0 ; pat = PATTERN ( trial ) ; if ( sparc_leaf_function_p || TARGET_FLAT ) { if ( LEAF_SIBCALL_SLOT_RESERVED_P ) return 0 ; if ( reg_mentioned_p ( gen_rtx_REG ( Pmode , 1 ) , pat ) ) return 0 ; return 1 ; } if ( GET_CODE ( pat ) != SET ) return 0 ; if ( GET_CODE ( SET_DEST ( pat ) ) != REG || ( REGNO ( SET_DEST ( pat ) ) >= 8 && REGNO ( SET_DEST ( pat ) ) < 24 ) || ! SPARC_INT_REG_P ( REGNO ( SET_DEST ( pat ) ) ) ) return 0 ; if ( reg_mentioned_p ( gen_rtx_REG ( Pmode , 15 ) , pat ) ) return 0 ; return eligible_for_restore_insn ( trial , false ) ; } </s>

Return nonzero if TRIAL can go into the sibling call 's delay slot .


<s> static rtx_insn * emit_window_save ( rtx increment ) { rtx_insn * insn = emit_insn ( gen_window_save ( increment ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_REGISTER , gen_rtx_SET ( VOIDmode , gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) , gen_rtx_REG ( Pmode , INCOMING_RETURN_ADDR_REGNUM ) ) ) ; add_reg_note ( insn , REG_CFA_WINDOW_SAVE , const0_rtx ) ; add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , hard_frame_pointer_rtx , INCOMING_FRAME_SP_OFFSET ) ) ; return insn ; } </s>


<s> bool ARMPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None && ! getARMSubtarget ( ) . isThumb1Only ( ) ) PM -> add ( createARMLoadStoreOptimizationPass ( true ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None && getARMSubtarget ( ) . isCortexA9 ( ) ) PM -> add ( createMLxExpansionPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> void Warning ( SMLoc L , const Twine & Msg ) { Parser . Warning ( L , Msg ) ; } </s>

Emit a warning at the location L , with the message Msg .


<s> virtual const Tile64Subtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
MachineInstrBuilder
R600InstrInfo
::
buildIndirectRead
(
MachineBasicBlock
*
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
ValueReg
,
unsigned
Address
,
unsigned
OffsetReg
,
unsigned
AddrChan
)
const
{
unsigned
AddrReg
;
switch
(
AddrChan
)
{
default
:
llvm_unreachable
(
"Invalid Channel"
)
;
case
0
:
AddrReg
=
AMDGPU
::
R600_AddrRegClass
.
getRegister
(
Address
)
;
break
;
case
1
:
AddrReg
=
AMDGPU
::
R600_Addr_YRegClass
.
getRegister
(
Address
)
;
break
;
case
2
:
AddrReg
=
AMDGPU
::
R600_Addr_ZRegClass
.
getRegister
(
Address
)
;
break
;
case
3
:
AddrReg
=
AMDGPU
::
R600_Addr_WRegClass
.
getRegister
(
Address
)
;
break
;
}
MachineInstr
*
MOVA
=
buildDefaultInstruction
(
*
MBB
,
I
,
AMDGPU
::
MOVA_INT_eg
,
AMDGPU
::
AR_X
,
OffsetReg
)
;
setImmOperand
(
MOVA
,
AMDGPU
::
OpName
::
write
,
0
)
;
MachineInstrBuilder
Mov
=
buildDefaultInstruction
(
*
MBB
,
I
,
AMDGPU
::
MOV
,
ValueReg
,
AddrReg
)
.
addReg
(
AMDGPU
::
AR_X
,
RegState
::
Implicit
|
RegState
::
Kill
)
;
setImmOperand
(
Mov
,
AMDGPU
::
OpName
::
src0_rel
,
1
)
;
return
Mov
;
}
</s>

Build instruction ( s ) for an indirect register read .


<s> unsigned int mips_hard_regno_nregs ( int regno , enum machine_mode mode ) { if ( ST_REG_P ( regno ) ) return ( ( GET_MODE_SIZE ( mode ) + 3 ) / 4 ) ; else if ( ! FP_REG_P ( regno ) ) return ( ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ) ; else return ( ( GET_MODE_SIZE ( mode ) + UNITS_PER_FPREG - 1 ) / UNITS_PER_FPREG ) ; } </s>


<s> insn_code function_expander :: direct_optab_handler_for_sign ( optab signed_op , optab unsigned_op , unsigned int suffix_i , machine_mode mode ) { if ( mode == VOIDmode ) mode = vector_mode ( suffix_i ) ; optab op = type_suffix ( suffix_i ) . unsigned_p ? unsigned_op : signed_op ; return :: direct_optab_handler ( op , mode ) ; } </s>

Choose between signed and unsigned direct optabs SIGNED_OP and UNSIGNED_OP based on the signedness of type suffix SUFFIX_I , then pick the appropriate optab handler for the mode . Use MODE as the mode if given , otherwise use the mode of type suffix SUFFIX_I .


<s> bool AArch64O0PreLegalizerCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: FailedISel ) ) return false ; auto & TPC = getAnalysis < TargetPassConfig > ( ) ; const Function & F = MF . getFunction ( ) ; GISelKnownBits * KB = & getAnalysis < GISelKnownBitsAnalysis > ( ) . get ( MF ) ; AArch64O0PreLegalizerCombinerInfo PCInfo ( false , F . hasOptSize ( ) , F . hasMinSize ( ) , KB , nullptr ) ; Combiner C ( PCInfo , & TPC ) ; return C . combineMachineInstrs ( MF , nullptr ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool cris_frame_pointer_required ( void ) { return ! crtl -> sp_is_unchanging ; } </s>

Implement TARGET_FRAME_POINTER_REQUIRED . Really only needed if the stack frame has variable length ( alloca or variable sized local arguments ( GNU C extension ) . See PR39499 and PR38609 for the reason this is n't just 0 .


<s> bool isPredicated ( ) const { return Predicated ; } </s>

Returns true if the instruction is already predicated .


<s> void reset ( ) { s . Error = CHECK_SUCCESS ; s . Warning = CHECK_SUCCESS ; s . ShuffleError = HexagonShuffler :: SHUFFLE_SUCCESS ; s . Register = Hexagon :: NoRegister ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s> static void m68k_override_options_after_change ( void ) { if ( m68k_sched_cpu == CPU_UNKNOWN ) { flag_schedule_insns = 0 ; flag_schedule_insns_after_reload = 0 ; flag_modulo_sched = 0 ; flag_live_range_shrinkage = 0 ; } } </s>


<s>
bool
X86TargetLowering
::
allowTruncateForTailCall
(
Type
*
Ty1
,
Type
*
Ty2
)
const
{
if
(
!
Ty1
->
isIntegerTy
(
)
||
!
Ty2
->
isIntegerTy
(
)
)
return
false
;
if
(
!
isTypeLegal
(
EVT
::
getEVT
(
Ty1
)
)
)
return
false
;
assert
(
Ty1
->
getPrimitiveSizeInBits
(
)
<=
64
&&
"i128 is probably not a noop"
)
;
return
true
;
}
</s>

Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail position .


"Instr doesn't have FrameIndex operand!"

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s> MCSectionXCore * MCSectionXCore :: Create ( const StringRef & Section , unsigned Type , unsigned Flags , SectionKind K , bool isExplicit , MCContext & Ctx ) { return new ( Ctx ) MCSectionXCore ( Section , Type , Flags , K , isExplicit ) ; } </s>

Construct a unary instruction , given the opcode and an operand .


<s> bool X86InstrInfo :: isUnconditionalTailCall ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: TCRETURNmi64 : return true ; default : return false ; } } </s>

Returns true if MI is an unconditional tail call .


<s> static int mips_issue_rate ( void ) { switch ( mips_tune ) { case PROCESSOR_R4130 : case PROCESSOR_R5400 : case PROCESSOR_R5500 : case PROCESSOR_R7000 : case PROCESSOR_R9000 : return 2 ; case PROCESSOR_SB1 : return 3 ; default : return 1 ; } } </s>

Return the number of instructions that can be issued per cycle .


<s> ISD :: NodeType getExtendForAtomicOps ( ) const override { return ISD :: SIGN_EXTEND ; } </s>

Returns how the platform 's atomic operations are extended ( ZERO_EXTEND , SIGN_EXTEND , or ANY_EXTEND ) .