<s> unsigned VEInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . getOpcode ( ) == VE :: LDSri || MI . getOpcode ( ) == VE :: LDLri || MI . getOpcode ( ) == VE :: LDUri ) { if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"WebAssembly Set p2align Operands"
;
}
</s>

getPassName - Return a nice clean name for a pass .

WebAssembly
"WebAssembly Set p2align Operands"


"eliminateCallFramePseudoInstr size too big: "

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static void mcore_setup_incoming_varargs ( cumulative_args_t args_so_far_v , const function_arg_info & arg , int * ptr_pretend_size ATTRIBUTE_UNUSED , int second_time ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * args_so_far = get_cumulative_args ( args_so_far_v ) ; current_function_anonymous_args = 1 ; number_of_regs_before_varargs = * args_so_far ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) ) number_of_regs_before_varargs += mcore_num_arg_regs ( arg . mode , arg . type ) ; number_of_regs_before_varargs = * args_so_far ; if ( number_of_regs_before_varargs > NPARM_REGS ) number_of_regs_before_varargs = NPARM_REGS ; } </s>

Keep track of some information about varargs for the prolog .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const override { return createX86MachObjectWriter ( OS , true , MachO :: CPU_TYPE_X86_64 , Subtype ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> int pa_adjust_insn_length ( rtx insn , int length ) { rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( insn ) == JUMP_INSN && GET_CODE ( pat ) == PARALLEL && get_attr_type ( insn ) == TYPE_BTABLE_BRANCH ) return 4 ; else if ( GET_CODE ( insn ) == INSN && GET_CODE ( pat ) != SEQUENCE && GET_CODE ( pat ) != USE && GET_CODE ( pat ) != CLOBBER && get_attr_type ( insn ) == TYPE_MILLI ) return 4 ; else if ( GET_CODE ( insn ) == INSN && GET_CODE ( pat ) == PARALLEL && GET_CODE ( XVECEXP ( pat , 0 , 0 ) ) == SET && GET_CODE ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 0 ) ) == MEM && GET_CODE ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 1 ) ) == MEM && GET_MODE ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 0 ) ) == BLKmode && GET_MODE ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 1 ) ) == BLKmode ) return compute_movmem_length ( insn ) - 4 ; else if ( GET_CODE ( insn ) == INSN && GET_CODE ( pat ) == PARALLEL && GET_CODE ( XVECEXP ( pat , 0 , 0 ) ) == SET && GET_CODE ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 0 ) ) == MEM && XEXP ( XVECEXP ( pat , 0 , 0 ) , 1 ) == const0_rtx && GET_MODE ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 0 ) ) == BLKmode ) return compute_clrmem_length ( insn ) - 4 ; else if ( GET_CODE ( insn ) == JUMP_INSN && ! simplejump_p ( insn ) ) { if ( GET_CODE ( pat ) == SET && length == 4 && ! forward_branch_p ( insn ) ) return 4 ; else if ( GET_CODE ( pat ) == PARALLEL && get_attr_type ( insn ) == TYPE_PARALLEL_BRANCH && length == 4 ) return 4 ; else if ( GET_CODE ( pat ) == PARALLEL && GET_CODE ( XVECEXP ( pat , 0 , 1 ) ) == SET && GET_CODE ( XEXP ( XVECEXP ( pat , 0 , 1 ) , 0 ) ) == REG && ! FP_REG_P ( XEXP ( XVECEXP ( pat , 0 , 1 ) , 0 ) ) && length == 4 && ! forward_branch_p ( insn ) ) return 4 ; else return 0 ; } return 0 ; } </s>

Return any length adjustment needed by INSN which already has its length computed as LENGTH . Return zero if no adjustment is necessary . For the PA : function calls , millicode calls , and backwards short conditional branches with unfilled delay slots need an adjustment by +1 ( to account for the NOP which will be inserted into the instruction stream ) . Also compute the length of an inline block move here as it is too complicated to express as a length attribute in pa.md .


<s>
unsigned
AlphaRegisterInfo
::
getRARegister
(
)
const
{
llvm_unreachable
(
"What is the return address register"
)
;
return
0
;
}
</s>

This method should return the register where the return address can be found .

Alpha
Alpha
"What is the return address register"
0


"MEMOPw offset is not aligned correctly."

"MEMOPh offset is not aligned correctly."

"No offset range is defined for this opcode. "

"Please define it in the above switch statement!"


Return TRUE if the type , as described by TYPE and MODE , is a short vector type as described in AAPCS64 \S 4.1.2 . See the comment above aarch64_composite_type_p for the notes on MODE .


<s> void xstormy16_expand_andqi3 ( rtx * operands ) { rtx in , out , outsub , val ; out = operands [ 0 ] ; in = operands [ 1 ] ; val = operands [ 2 ] ; if ( xstormy16_onebit_clr_operand ( val , QImode ) ) { if ( ! xstormy16_below100_or_register ( in , QImode ) ) in = copy_to_mode_reg ( QImode , in ) ; if ( ! xstormy16_below100_or_register ( out , QImode ) ) out = gen_reg_rtx ( QImode ) ; emit_insn ( gen_andqi3_internal ( out , in , val ) ) ; if ( out != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , out ) ; return ; } if ( ! REG_P ( in ) ) in = copy_to_mode_reg ( QImode , in ) ; if ( ! REG_P ( val ) && ! CONST_INT_P ( val ) ) val = copy_to_mode_reg ( QImode , val ) ; if ( ! REG_P ( out ) ) out = gen_reg_rtx ( QImode ) ; in = simplify_gen_subreg ( HImode , in , QImode , 0 ) ; outsub = simplify_gen_subreg ( HImode , out , QImode , 0 ) ; if ( ! CONST_INT_P ( val ) ) val = simplify_gen_subreg ( HImode , val , QImode , 0 ) ; emit_insn ( gen_andhi3 ( outsub , in , val ) ) ; if ( out != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , out ) ; } </s>


<s>
void
ARMAsmBackend
::
relaxInstruction
(
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
)
const
{
unsigned
RelaxedOp
=
getRelaxedOpcode
(
Inst
.
getOpcode
(
)
,
STI
)
;
if
(
RelaxedOp
==
Inst
.
getOpcode
(
)
)
{
SmallString
<
256
>
Tmp
;
raw_svector_ostream
OS
(
Tmp
)
;
Inst
.
dump_pretty
(
OS
)
;
OS
<<
"\n"
;
report_fatal_error
(
"unexpected instruction to relax: "
+
OS
.
str
(
)
)
;
}
if
(
(
Inst
.
getOpcode
(
)
==
ARM
::
tCBZ
||
Inst
.
getOpcode
(
)
==
ARM
::
tCBNZ
)
&&
RelaxedOp
==
ARM
::
tHINT
)
{
MCInst
Res
;
Res
.
setOpcode
(
RelaxedOp
)
;
Res
.
addOperand
(
MCOperand
::
createImm
(
0
)
)
;
Res
.
addOperand
(
MCOperand
::
createImm
(
14
)
)
;
Res
.
addOperand
(
MCOperand
::
createReg
(
0
)
)
;
Inst
=
std
::
move
(
Res
)
;
return
;
}
Inst
.
setOpcode
(
RelaxedOp
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> unsigned R600RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return R600 :: NoRegister ; } </s>


<s> static void ia64_file_start ( void ) { ia64_flag_var_tracking = flag_var_tracking ; flag_var_tracking = 0 ; default_file_start ( ) ; emit_safe_across_calls ( ) ; } </s>


<s>
void
X86InstrInfo
::
reMaterialize
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
unsigned
SubIdx
,
const
MachineInstr
*
Orig
,
const
TargetRegisterInfo
&
TRI
)
const
{
bool
ClobbersEFLAGS
=
false
;
for
(
const
MachineOperand
&
MO
:
Orig
->
operands
(
)
)
{
if
(
MO
.
isReg
(
)
&&
MO
.
isDef
(
)
&&
MO
.
getReg
(
)
==
X86
::
EFLAGS
)
{
ClobbersEFLAGS
=
true
;
break
;
}
}
if
(
ClobbersEFLAGS
&&
!
isSafeToClobberEFLAGS
(
MBB
,
I
)
)
{
int
Value
;
switch
(
Orig
->
getOpcode
(
)
)
{
case
X86
::
MOV32r0
:
Value
=
0
;
break
;
case
X86
::
MOV32r1
:
Value
=
1
;
break
;
case
X86
::
MOV32r_1
:
Value
=
1
;
break
;
default
:
llvm_unreachable
(
"Unexpected instruction!"
)
;
}
const
DebugLoc
&
DL
=
Orig
->
getDebugLoc
(
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
X86
::
MOV32ri
)
)
.
addOperand
(
Orig
->
getOperand
(
0
)
)
.
addImm
(
Value
)
;
}
else
{
MachineInstr
*
MI
=
MBB
.
getParent
(
)
->
CloneMachineInstr
(
Orig
)
;
MBB
.
insert
(
I
,
MI
)
;
}
MachineInstr
*
NewMI
=
std
::
prev
(
I
)
;
NewMI
->
substituteRegister
(
Orig
->
getOperand
(
0
)
.
getReg
(
)
,
DestReg
,
SubIdx
,
TRI
)
;
}
</s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s> bool ARM64TargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty ) const { if ( AM . BaseGV ) return false ; if ( AM . HasBaseReg && AM . BaseOffs && AM . Scale ) return false ; uint64_t NumBytes = 0 ; if ( Ty -> isSized ( ) ) { uint64_t NumBits = getDataLayout ( ) -> getTypeSizeInBits ( Ty ) ; NumBytes = NumBits / 8 ; if ( ! isPowerOf2_64 ( NumBits ) ) NumBytes = 0 ; } if ( ! AM . Scale ) { int64_t Offset = AM . BaseOffs ; if ( Offset >= - ( 1LL << 9 ) && Offset <= ( 1LL << 9 ) - 1 ) return true ; unsigned shift = Log2_64 ( NumBytes ) ; if ( NumBytes && Offset > 0 && ( Offset / NumBytes ) <= ( 1LL << 12 ) - 1 && ( Offset >> shift ) << shift == Offset ) return true ; return false ; } if ( ! AM . Scale || AM . Scale == 1 || ( AM . Scale > 0 && ( uint64_t ) AM . Scale == NumBytes ) ) return true ; return false ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> void RISCVTargetStreamer :: emitTargetAttributes ( const MCSubtargetInfo & STI ) { if ( STI . hasFeature ( RISCV :: FeatureRV32E ) ) emitAttribute ( RISCVAttrs :: STACK_ALIGN , RISCVAttrs :: ALIGN_4 ) ; else emitAttribute ( RISCVAttrs :: STACK_ALIGN , RISCVAttrs :: ALIGN_16 ) ; auto ParseResult = RISCVFeatures :: parseFeatureBits ( STI . hasFeature ( RISCV :: Feature64Bit ) , STI . getFeatureBits ( ) ) ; if ( ! ParseResult ) { report_fatal_error ( ParseResult . takeError ( ) ) ; } else { auto & ISAInfo = * ParseResult ; emitTextAttribute ( RISCVAttrs :: ARCH , ISAInfo -> toString ( ) ) ; } } </s>

Emit the build attributes that only depend on the hardware that we expect .


<s> unsigned HexagonMCInst :: getUnits ( HexagonTargetMachine const & TM ) const { const HexagonInstrInfo * QII = TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ; const InstrItineraryData * II = TM . getSubtargetImpl ( ) -> getInstrItineraryData ( ) ; const InstrStage * IS = II -> beginStage ( QII -> get ( this -> getOpcode ( ) ) . getSchedClass ( ) ) ; return ( IS -> getUnits ( ) ) ; } </s>


<s> unsigned MipsMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; unsigned RegNo = Ctx . getRegisterInfo ( ) -> getEncodingValue ( Reg ) ; return RegNo ; } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isDFPImm ( ) ) { return static_cast < unsigned > ( bit_cast < double > ( MO . getDFPImm ( ) ) ) ; } assert ( MO . isExpr ( ) ) ; return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> TargetTransformInfo SystemZTargetMachine :: getTargetTransformInfo ( const Function & F ) { return TargetTransformInfo ( SystemZTTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


Return the DataLayout associated with the module this SCEV instance is operating on .


<s> static HOST_WIDE_INT riscv_constant_alignment ( const_tree exp , HOST_WIDE_INT align ) { if ( ( TREE_CODE ( exp ) == STRING_CST || TREE_CODE ( exp ) == CONSTRUCTOR ) && ( riscv_align_data_type == riscv_align_data_type_xlen ) ) return MAX ( align , BITS_PER_WORD ) ; return align ; } </s>


<s> void MSP430PassConfig :: addPreEmitPass ( ) { addPass ( createMSP430BranchSelectionPass ( ) , false ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static bool c6x_call_saved_register_used ( tree call_expr ) { CUMULATIVE_ARGS cum_v ; cumulative_args_t cum ; HARD_REG_SET call_saved_regset ; tree parameter ; machine_mode mode ; tree type ; rtx parm_rtx ; int i ; INIT_CUMULATIVE_ARGS ( cum_v , NULL , NULL , 0 , 0 ) ; cum = pack_cumulative_args ( & cum_v ) ; COMPL_HARD_REG_SET ( call_saved_regset , call_used_reg_set ) ; for ( i = 0 ; i < call_expr_nargs ( call_expr ) ; i ++ ) { parameter = CALL_EXPR_ARG ( call_expr , i ) ; gcc_assert ( parameter ) ; if ( TREE_CODE ( parameter ) == ERROR_MARK ) return true ; type = TREE_TYPE ( parameter ) ; gcc_assert ( type ) ; mode = TYPE_MODE ( type ) ; gcc_assert ( mode ) ; if ( pass_by_reference ( & cum_v , mode , type , true ) ) { mode = Pmode ; type = build_pointer_type ( type ) ; } parm_rtx = c6x_function_arg ( cum , mode , type , 0 ) ; c6x_function_arg_advance ( cum , mode , type , 0 ) ; if ( ! parm_rtx ) continue ; if ( REG_P ( parm_rtx ) && overlaps_hard_reg_set_p ( call_saved_regset , GET_MODE ( parm_rtx ) , REGNO ( parm_rtx ) ) ) return true ; if ( GET_CODE ( parm_rtx ) == PARALLEL ) { int n = XVECLEN ( parm_rtx , 0 ) ; while ( n -- > 0 ) { rtx x = XEXP ( XVECEXP ( parm_rtx , 0 , n ) , 0 ) ; if ( REG_P ( x ) && overlaps_hard_reg_set_p ( call_saved_regset , GET_MODE ( x ) , REGNO ( x ) ) ) return true ; } } } return false ; } </s>

Checks whether the given CALL_EXPR would use a caller saved register . This is used to decide whether sibling call optimization could be performed on the respective function call .


<s> bool useAA ( ) const override { return UseAA ; } </s>

Enable use of alias analysis during code generation ( during MI scheduling , DAGCombine , etc . ) .


<s> void TMS320C64XFrameLowering :: emitPrologue ( MachineFunction & MF ) const { int frame_size ; MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = ( MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ) ; MBB . addLiveIn ( TMS320C64X :: B3 ) ; frame_size = MFI -> getStackSize ( ) ; frame_size += 8 ; frame_size += 7 ; frame_size &= ~ 7 ; const TMS320C64XInstrInfo & TII = * TM . getInstrInfo ( ) ; TMS320C64XInstrInfo :: addDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( TMS320C64X :: prolog ) ) . addImm ( frame_size ) ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool ARMTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( Subtarget -> isThumb1Only ( ) ) return false ; const bool restrict_addressing_modes_for_nacl = ( ( FlagSfiLoad && N -> getOpcode ( ) == ISD :: LOAD ) || ( FlagSfiStore && N -> getOpcode ( ) == ISD :: STORE ) ) ; if ( restrict_addressing_modes_for_nacl ) { return false ; } EVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == ISD :: SEXTLOAD ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; } else return false ; bool isInc ; bool isLegal = false ; if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = getARMIndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( ! isLegal ) return false ; if ( Ptr != Base ) { if ( Ptr == Offset && Op -> getOpcode ( ) == ISD :: ADD && ! Subtarget -> isThumb2 ( ) ) std :: swap ( Base , Offset ) ; if ( Ptr != Base ) return false ; } AM = isInc ? ISD :: POST_INC : ISD :: POST_DEC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .

ARM ARM ISD::MemIndexedMode ISD::LOAD ISD::STORE ISD::SEXTLOAD ARM ISD::ADD ISD::POST_INC ISD::POST_DEC


"LowerFormalArguments Unhandled argument type: "

"functions with VarArgs or StructRet are not supported"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> static bool base_reg_adjustment_p ( rtx set , rtx * base_reg , rtx * offset ) { if ( GET_CODE ( set ) == SET && REG_P ( SET_DEST ( set ) ) && GET_CODE ( SET_SRC ( set ) ) == PLUS && REG_P ( XEXP ( SET_SRC ( set ) , 0 ) ) && rtx_equal_p ( SET_DEST ( set ) , XEXP ( SET_SRC ( set ) , 0 ) ) && CONST_INT_P ( XEXP ( SET_SRC ( set ) , 1 ) ) ) { * base_reg = XEXP ( SET_SRC ( set ) , 0 ) ; * offset = XEXP ( SET_SRC ( set ) , 1 ) ; return true ; } return false ; } </s>

This routine tests for the base register update SET in load/store multiple RTL insns , used in pop_operation_p and ldstwm_operation_p .


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


"invalid feature modifier in -march=%qs"

Validate a command-line -march option . Parse the arch and extensions ( if any ) specified in STR and throw errors if appropriate . Put the results , if they are valid , in RES and ISA_FLAGS . Return whether the option is valid .


<s> static rtx m68k_get_tls_get_addr ( void ) { if ( m68k_tls_get_addr == NULL_RTX ) m68k_tls_get_addr = init_one_libfunc ( "__tls_get_addr" ) ; return m68k_tls_get_addr ; } </s>


<s> const HexagonRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static bool arm_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( GET_MODE_CLASS ( mode1 ) == GET_MODE_CLASS ( mode2 ) ) return true ; if ( ( TARGET_NEON && ( VALID_NEON_DREG_MODE ( mode1 ) || VALID_NEON_QREG_MODE ( mode1 ) || VALID_NEON_STRUCT_MODE ( mode1 ) ) && ( VALID_NEON_DREG_MODE ( mode2 ) || VALID_NEON_QREG_MODE ( mode2 ) || VALID_NEON_STRUCT_MODE ( mode2 ) ) ) || ( TARGET_HAVE_MVE && ( VALID_MVE_MODE ( mode1 ) || VALID_MVE_STRUCT_MODE ( mode1 ) ) && ( VALID_MVE_MODE ( mode2 ) || VALID_MVE_STRUCT_MODE ( mode2 ) ) ) ) return true ; return false ; } </s>


<s> rtx get_unaligned_address ( rtx ref ) { rtx base ; HOST_WIDE_INT offset = 0 ; gcc_assert ( MEM_P ( ref ) ) ; if ( reload_in_progress ) { base = find_replacement ( & XEXP ( ref , 0 ) ) ; gcc_assert ( memory_address_p ( GET_MODE ( ref ) , base ) ) ; } else base = XEXP ( ref , 0 ) ; if ( GET_CODE ( base ) == PLUS ) offset += INTVAL ( XEXP ( base , 1 ) ) , base = XEXP ( base , 0 ) ; return plus_constant ( Pmode , base , offset ) ; } </s>

Similar , but just get the address . Handle the two reload cases . Add EXTRA_OFFSET to the address we return .


<s> bool SIInstrInfo :: mayReadEXEC ( const MachineRegisterInfo & MRI , const MachineInstr & MI ) const { if ( MI . isMetaInstruction ( ) ) return false ; if ( MI . isCopyLike ( ) ) { if ( ! RI . isSGPRReg ( MRI , MI . getOperand ( 0 ) . getReg ( ) ) ) return true ; return MI . readsRegister ( AMDGPU :: EXEC , & RI ) ; } if ( MI . isCall ( ) ) return true ; if ( ! isTargetSpecificOpcode ( MI . getOpcode ( ) ) ) return true ; return ! isSALU ( MI ) || MI . readsRegister ( AMDGPU :: EXEC , & RI ) ; } </s>

Returns true if the instruction could potentially depend on the value of exec .


<s> bool TVMFrameLowering :: hasFP ( const MachineFunction & MF ) const { return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static int bpf_core_is_maybe_aggregate_access ( tree expr ) { enum tree_code code = TREE_CODE ( expr ) ; if ( code == COMPONENT_REF || code == ARRAY_REF ) return 1 ; if ( code == ADDR_EXPR ) return bpf_core_is_maybe_aggregate_access ( TREE_OPERAND ( expr , 0 ) ) ; return 0 ; } </s>

Return whether EXPR could access some aggregate data structure that BPF CO-RE support needs to know about .


<s> bool SIRegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> bool Mips16FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return true ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> static NodeType * getEntryNode ( const agraph & G ) { return G . Blocks . front ( ) ; } </s>

Return the token chain corresponding to the entry of the function .


<s> static int avr_hregs_split_reg ( HARD_REG_SET * set ) { for ( int regno = 0 ; regno < 32 ; regno ++ ) if ( TEST_HARD_REG_BIT ( * set , regno ) ) { if ( AVR_HAVE_RAMPX && ( REG_X == regno || REG_X + 1 == regno ) && TEST_HARD_REG_BIT ( * set , REG_X ) && TEST_HARD_REG_BIT ( * set , REG_X + 1 ) ) continue ; if ( AVR_HAVE_RAMPY && ! frame_pointer_needed && ( REG_Y == regno || REG_Y + 1 == regno ) && TEST_HARD_REG_BIT ( * set , REG_Y ) && TEST_HARD_REG_BIT ( * set , REG_Y + 1 ) ) continue ; if ( AVR_HAVE_RAMPZ && ( REG_Z == regno || REG_Z + 1 == regno ) && TEST_HARD_REG_BIT ( * set , REG_Z ) && TEST_HARD_REG_BIT ( * set , REG_Z + 1 ) ) continue ; CLEAR_HARD_REG_BIT ( * set , regno ) ; return regno ; } return - 1 ; } </s>

Unset a bit in * SET . If successful , return the respective bit number . Otherwise , return -1 and * SET is unaltered .


<s> static recpe_type get_recpe_type ( machine_mode mode ) { switch ( mode ) { case E_SFmode : return ( gen_aarch64_frecpesf ) ; case E_V2SFmode : return ( gen_aarch64_frecpev2sf ) ; case E_V4SFmode : return ( gen_aarch64_frecpev4sf ) ; case E_DFmode : return ( gen_aarch64_frecpedf ) ; case E_V2DFmode : return ( gen_aarch64_frecpev2df ) ; default : gcc_unreachable ( ) ; } } </s>

Select reciprocal initial estimate insn depending on machine mode .


<s> virtual bool addPassesToEmitMC ( PassManagerBase & , MCContext * & , raw_ostream & , CodeGenOpt :: Level , bool = true ) { return true ; } </s>

Add passes to the specified pass manager to get machine code emitted with the MCJIT .


<s> void bpf_expand_prologue ( void ) { HOST_WIDE_INT size ; size = ( cfun -> machine -> local_vars_size + cfun -> machine -> callee_saved_reg_size ) ; if ( TARGET_XBPF ) { int regno ; int fp_offset = - cfun -> machine -> local_vars_size ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) { if ( ( df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) ) || ( cfun -> calls_alloca && regno == STACK_POINTER_REGNUM ) ) { rtx mem ; if ( ! IN_RANGE ( fp_offset , - 1 - 0x7fff , 0x7fff ) ) break ; else { mem = gen_frame_mem ( DImode , plus_constant ( DImode , hard_frame_pointer_rtx , fp_offset - 8 ) ) ; emit_move_insn ( mem , gen_rtx_REG ( DImode , regno ) ) ; fp_offset -= 8 ; } } } } if ( cfun -> calls_alloca ) { emit_move_insn ( stack_pointer_rtx , hard_frame_pointer_rtx ) ; if ( size > 0 ) { emit_insn ( gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( - size ) ) ) ) ; } } } </s>

Expand to the instructions in a function prologue . This function is called when expanding the 'prologue ' pattern in bpf.md .


<s> unsigned PIC16RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , FrameIndexValue * Value , RegScavenger * RS ) const { return 0 ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool mips_const_vector_same_bytes_p ( rtx op , machine_mode mode ) { int i , bytes ; HOST_WIDE_INT val , first_byte ; rtx first ; if ( ! mips_const_vector_same_val_p ( op , mode ) ) return false ; first = CONST_VECTOR_ELT ( op , 0 ) ; bytes = GET_MODE_UNIT_SIZE ( mode ) ; val = INTVAL ( first ) ; first_byte = val & 0xff ; for ( i = 1 ; i < bytes ; i ++ ) { val >>= 8 ; if ( ( val & 0xff ) != first_byte ) return false ; } return true ; } </s>

Return true if OP is a constant vector with the number of units in MODE , and each unit has the same value as well as replicated bytes in the value .


"Currently only symbol operands are supported"

"Unhandled MCInst for getMachineOpValue"

getMachineOpValue - Return binary encoding of operand .


<s> static void ix86_emit_save_regs_using_mov ( HOST_WIDE_INT cfa_offset ) { unsigned int regno ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( GENERAL_REGNO_P ( regno ) && ix86_save_reg ( regno , true ) ) { ix86_emit_save_reg_using_mov ( word_mode , regno , cfa_offset ) ; cfa_offset -= UNITS_PER_WORD ; } } </s>

Emit code to save registers using MOV insns . First register is restored from POINTER + OFFSET .


<s> const char * AMDGPUTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; NODE_NAME_CASE ( CALL ) ; NODE_NAME_CASE ( UMUL ) ; NODE_NAME_CASE ( DIV_INF ) ; NODE_NAME_CASE ( RET_FLAG ) ; NODE_NAME_CASE ( BRANCH_COND ) ; NODE_NAME_CASE ( DWORDADDR ) NODE_NAME_CASE ( FRACT ) NODE_NAME_CASE ( FMAX ) NODE_NAME_CASE ( SMAX ) NODE_NAME_CASE ( UMAX ) NODE_NAME_CASE ( FMIN ) NODE_NAME_CASE ( SMIN ) NODE_NAME_CASE ( UMIN ) NODE_NAME_CASE ( URECIP ) NODE_NAME_CASE ( EXPORT ) NODE_NAME_CASE ( CONST_ADDRESS ) NODE_NAME_CASE ( REGISTER_LOAD ) NODE_NAME_CASE ( REGISTER_STORE ) NODE_NAME_CASE ( LOAD_CONSTANT ) NODE_NAME_CASE ( LOAD_INPUT ) NODE_NAME_CASE ( SAMPLE ) NODE_NAME_CASE ( SAMPLEB ) NODE_NAME_CASE ( SAMPLED ) NODE_NAME_CASE ( SAMPLEL ) NODE_NAME_CASE ( STORE_MSKOR ) NODE_NAME_CASE ( TBUFFER_STORE_FORMAT ) } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static bool pdp11_handle_option ( size_t code , const char * arg ATTRIBUTE_UNUSED , int value ATTRIBUTE_UNUSED ) { switch ( code ) { case OPT_m10 : target_flags &= ~ ( MASK_40 | MASK_45 ) ; return true ; default : return true ; } } </s>


<s> static bool arm_output_ttype ( rtx x ) { fputs ( "\t.word\t" , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; if ( GET_CODE ( x ) != CONST_INT ) fputs ( "(TARGET2)" , asm_out_file ) ; fputc ( '\n' , asm_out_file ) ; return TRUE ; } </s>

Output a reference from a function exception table to the type_info object X . The EABI specifies that the symbol should be relocated by an R_ARM_TARGET2 relocation .


<s> bool writeNopData ( raw_ostream & OS , uint64_t Count ) const override { uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) support :: endian :: write < uint32_t > ( OS , 0x60000000 , Endian ) ; OS . write_zeros ( Count % 4 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s>
SDValue
VideoCore4TargetLowering
::
LowerCall
(
TargetLowering
::
CallLoweringInfo
&
CLI
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SelectionDAG
&
DAG
=
CLI
.
DAG
;
SDLoc
&
dl
=
CLI
.
DL
;
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
=
CLI
.
Outs
;
SmallVectorImpl
<
SDValue
>
&
OutVals
=
CLI
.
OutVals
;
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
=
CLI
.
Ins
;
SDValue
Chain
=
CLI
.
Chain
;
SDValue
Callee
=
CLI
.
Callee
;
bool
&
isTailCall
=
CLI
.
IsTailCall
;
CallingConv
::
ID
CallConv
=
CLI
.
CallConv
;
bool
isVarArg
=
CLI
.
IsVarArg
;
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
OutVals
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .


<s> static void update_total_code_bytes ( unsigned int nbytes ) { if ( ( TARGET_PORTABLE_RUNTIME || ! TARGET_GAS || ! TARGET_SOM ) && ! IN_NAMED_SECTION_P ( cfun -> decl ) ) { unsigned int old_total = total_code_bytes ; total_code_bytes += nbytes ; if ( old_total > total_code_bytes ) total_code_bytes = UINT_MAX ; } } </s>

Update the total code bytes output to the text section .


<s>
unsigned
NVPTXInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
if
(
I
==
MBB
.
begin
(
)
)
return
0
;
I
;
if
(
I
->
getOpcode
(
)
!=
NVPTX
::
GOTO
&&
I
->
getOpcode
(
)
!=
NVPTX
::
CBranch
)
return
0
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
if
(
I
==
MBB
.
begin
(
)
)
return
1
;
I
;
if
(
I
->
getOpcode
(
)
!=
NVPTX
::
CBranch
)
return
1
;
I
->
eraseFromParent
(
)
;
return
2
;
}
</s>

Remove the branching code at the end of the specific MBB .


"converted opcode should be the same except for cc_out"

"expect uninitialized optional cc_out operand"

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


<s> MachineBasicBlock :: iterator MSP430FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const MSP430InstrInfo & TII = * static_cast < const MSP430InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr & Old = * I ; uint64_t Amount = TII . getFrameSize ( Old ) ; if ( Amount != 0 ) { Amount = alignTo ( Amount , getStackAlign ( ) ) ; MachineInstr * New = nullptr ; if ( Old . getOpcode ( ) == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( MSP430 :: SUB16ri ) , MSP430 :: SP ) . addReg ( MSP430 :: SP ) . addImm ( Amount ) ; } else { assert ( Old . getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) ; Amount -= TII . getFramePoppedByCallee ( Old ) ; if ( Amount ) New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( MSP430 :: ADD16ri ) , MSP430 :: SP ) . addReg ( MSP430 :: SP ) . addImm ( Amount ) ; } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = TII . getFramePoppedByCallee ( * I ) ) { MachineInstr & Old = * I ; MachineInstr * New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( MSP430 :: SUB16ri ) , MSP430 :: SP ) . addReg ( MSP430 :: SP ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> void rs6000_d_target_versions ( void ) { if ( TARGET_64BIT ) d_add_builtin_version ( "PPC64" ) ; else d_add_builtin_version ( "PPC" ) ; if ( TARGET_HARD_FLOAT ) { d_add_builtin_version ( "PPC_HardFloat" ) ; d_add_builtin_version ( "D_HardFloat" ) ; } else if ( TARGET_SOFT_FLOAT ) { d_add_builtin_version ( "PPC_SoftFloat" ) ; d_add_builtin_version ( "D_SoftFloat" ) ; } } </s>

Implement TARGET_D_CPU_VERSIONS for PowerPC targets .


<s> std :: unique_ptr < TargetInstrInfo :: PipelinerLoopInfo > HexagonInstrInfo :: analyzeLoopForPipelining ( MachineBasicBlock * LoopBB ) const { MachineBasicBlock :: iterator I = LoopBB -> getFirstTerminator ( ) ; if ( I != LoopBB -> end ( ) && isEndLoopN ( I -> getOpcode ( ) ) ) { SmallPtrSet < MachineBasicBlock * , 8 > VisitedBBs ; MachineInstr * LoopInst = findLoopInstr ( LoopBB , I -> getOpcode ( ) , I -> getOperand ( 0 ) . getMBB ( ) , VisitedBBs ) ; if ( LoopInst ) return std :: make_unique < HexagonPipelinerLoopInfo > ( LoopInst , & * I ) ; } return nullptr ; } </s>

Analyze loop L , which must be a single-basic-block loop , and if the conditions can be understood enough produce a PipelinerLoopInfo object .


<s> unsigned SIInstrInfo :: getNumWaitStates ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { default : return 1 ; case AMDGPU :: S_NOP : return MI . getOperand ( 0 ) . getImm ( ) + 1 ; } } </s>

Return the number of wait states that result from executing this instruction .


<s> static void microblaze_adjust_block_mem ( rtx mem , HOST_WIDE_INT length , rtx * loop_reg , rtx * loop_mem ) { * loop_reg = copy_addr_to_reg ( XEXP ( mem , 0 ) ) ; * loop_mem = change_address ( mem , BLKmode , * loop_reg ) ; set_mem_align ( * loop_mem , MIN ( ( HOST_WIDE_INT ) MEM_ALIGN ( mem ) , length * BITS_PER_UNIT ) ) ; } </s>

Helper function for doing a loop-based block operation on memory reference MEM . Each iteration of the loop will operate on LENGTH bytes of MEM . Create a new base register for use within the loop and point it to the start of MEM . Create a new memory reference that uses this register . Store them in * LOOP_REG and * LOOP_MEM respectively .


<s> bool HexagonFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; if ( CSI . empty ( ) ) { return false ; } bool ContiguousRegs = true ; for ( unsigned i = 0 ; i < CSI . size ( ) ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; unsigned SuperReg = uniqueSuperReg ( Reg , TRI ) ; const TargetRegisterClass * SuperRegClass = nullptr ; bool CanUseDblLoad = false ; if ( ContiguousRegs && ( i < CSI . size ( ) - 1 ) ) { unsigned SuperRegNext = uniqueSuperReg ( CSI [ i + 1 ] . getReg ( ) , TRI ) ; SuperRegClass = TRI -> getMinimalPhysRegClass ( SuperReg ) ; CanUseDblLoad = ( SuperRegNext == SuperReg ) ; } if ( CanUseDblLoad ) { TII . loadRegFromStackSlot ( MBB , MI , SuperReg , CSI [ i + 1 ] . getFrameIdx ( ) , SuperRegClass , TRI ) ; MBB . addLiveIn ( SuperReg ) ; ++ i ; } else { ContiguousRegs = false ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; MBB . addLiveIn ( Reg ) ; } } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> void X86WinCOFFStreamer :: finishImpl ( ) { emitFrames ( nullptr ) ; emitWindowsUnwindTables ( ) ; MCWinCOFFStreamer :: finishImpl ( ) ; } </s>


"ARM64 pseudo instruction expansion pass"

getPassName - Return a nice clean name for a pass .


<s> static rtx pro_epilogue_adjust_stack ( rtx dest , rtx src , rtx offset , int style , bool set_cfa ) { struct machine_function * m = cfun -> machine ; rtx addend = offset ; rtx insn ; bool add_frame_related_expr = false ; if ( ! x86_64_immediate_operand ( offset , Pmode ) ) { if ( style ) addend = gen_rtx_REG ( Pmode , R11_REG ) ; else { gcc_assert ( src != hard_frame_pointer_rtx && dest != hard_frame_pointer_rtx ) ; addend = hard_frame_pointer_rtx ; } emit_insn ( gen_rtx_SET ( addend , offset ) ) ; if ( style < 0 ) add_frame_related_expr = true ; } insn = emit_insn ( gen_pro_epilogue_adjust_stack_add ( Pmode , dest , src , addend ) ) ; if ( style >= 0 ) ix86_add_queued_cfa_restore_notes ( insn ) ; if ( set_cfa ) { rtx r ; gcc_assert ( m -> fs . cfa_reg == src ) ; m -> fs . cfa_offset += INTVAL ( offset ) ; m -> fs . cfa_reg = dest ; r = gen_rtx_PLUS ( Pmode , src , offset ) ; r = gen_rtx_SET ( dest , r ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , r ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } else if ( style < 0 ) { RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( add_frame_related_expr ) { rtx r = gen_rtx_PLUS ( Pmode , src , offset ) ; r = gen_rtx_SET ( dest , r ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , r ) ; } } if ( dest == stack_pointer_rtx ) { HOST_WIDE_INT ooffset = m -> fs . sp_offset ; bool valid = m -> fs . sp_valid ; bool realigned = m -> fs . sp_realigned ; if ( src == hard_frame_pointer_rtx ) { valid = m -> fs . fp_valid ; realigned = false ; ooffset = m -> fs . fp_offset ; } else if ( src == crtl -> drap_reg ) { valid = m -> fs . drap_valid ; realigned = false ; ooffset = 0 ; } else { gcc_checking_assert ( src == stack_pointer_rtx || offset == const0_rtx ) ; } m -> fs . sp_offset = ooffset - INTVAL ( offset ) ; m -> fs . sp_valid = valid ; m -> fs . sp_realigned = realigned ; } return insn ; } </s>

Expand prologue or epilogue stack adjustment . The pattern exist to put a dependency on all ebp-based memory accesses . STYLE should be negative if instructions should be marked as frame related , zero if % r11 register is live and can not be freely used and positive otherwise .


<s> bool RISCVCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const { if ( F . arg_empty ( ) ) return true ; return false ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s>
bool
CFGStructurizer
<
PassT
>
::
prepare
(
FuncT
&
func
,
PassT
&
pass
,
const
AMDGPURegisterInfo
*
tri
)
{
passRep
=
&
pass
;
funcRep
=
&
func
;
TRI
=
tri
;
bool
changed
=
false
;
if
(
DEBUGME
)
{
errs
(
)
<<
"AMDGPUCFGStructurizer::prepare\n"
;
}
loopInfo
=
CFGTraits
::
getLoopInfo
(
pass
)
;
if
(
DEBUGME
)
{
errs
(
)
<<
"LoopInfo:\n"
;
PrintLoopinfo
(
*
loopInfo
,
errs
(
)
)
;
}
orderBlocks
(
)
;
if
(
DEBUGME
)
{
errs
(
)
<<
"Ordered blocks:\n"
;
printOrderedBlocks
(
errs
(
)
)
;
}
SmallVector
<
BlockT
*
,
DEFAULT_VEC_SLOTS
>
retBlks
;
for
(
typename
LoopInfoT
::
iterator
iter
=
loopInfo
->
begin
(
)
,
iterEnd
=
loopInfo
->
end
(
)
;
iter
!=
iterEnd
;
++
iter
)
{
LoopT
*
loopRep
=
(
*
iter
)
;
BlockTSmallerVector
exitingBlks
;
loopRep
->
getExitingBlocks
(
exitingBlks
)
;
if
(
exitingBlks
.
size
(
)
==
0
)
{
BlockT
*
dummyExitBlk
=
normalizeInfiniteLoopExit
(
loopRep
)
;
if
(
dummyExitBlk
!=
)
retBlks
.
push_back
(
dummyExitBlk
)
;
}
}
for
(
typename
SmallVector
<
BlockT
*
,
DEFAULT_VEC_SLOTS
>
::
const_iterator
iterBlk
=
orderedBlks
.
begin
(
)
,
iterEndBlk
=
orderedBlks
.
end
(
)
;
iterBlk
!=
iterEndBlk
;
++
iterBlk
)
{
BlockT
*
curBlk
=
*
iterBlk
;
removeUnconditionalBranch
(
curBlk
)
;
removeRedundantConditionalBranch
(
curBlk
)
;
if
(
CFGTraits
::
isReturnBlock
(
curBlk
)
)
{
retBlks
.
push_back
(
curBlk
)
;
}
assert
(
curBlk
->
succ_size
(
)
<=
2
)
;
}
if
(
retBlks
.
size
(
)
>=
2
)
{
addDummyExitBlock
(
retBlks
)
;
changed
=
true
;
}
return
changed
;
}
</s>

prepare - Reset state and prepare for a new spill placement computation .


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void rs6000_emit_le_vsx_load ( rtx dest , rtx source , machine_mode mode ) { rtx tmp , permute_mem , permute_reg ; if ( mode == TImode || mode == V1TImode ) { mode = V2DImode ; dest = gen_lowpart ( V2DImode , dest ) ; source = adjust_address ( source , V2DImode , 0 ) ; } tmp = can_create_pseudo_p ( ) ? gen_reg_rtx_and_attrs ( dest ) : dest ; permute_mem = rs6000_gen_le_vsx_permute ( source , mode ) ; permute_reg = rs6000_gen_le_vsx_permute ( tmp , mode ) ; emit_insn ( gen_rtx_SET ( tmp , permute_mem ) ) ; emit_insn ( gen_rtx_SET ( dest , permute_reg ) ) ; } </s>

Emit a little-endian load from vector memory location SOURCE to VSX register DEST in mode MODE . The load is done with two permuting insn 's that represent an lxvd2x and xxpermdi .


"Unexpected Kind in getPointerRegClass!"

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> bool useAA ( ) const override { return true ; } </s>

Enable use of alias analysis during code generation ( during MI scheduling , DAGCombine , etc . ) .


<s> bool ARMTTIImpl :: isLegalMaskedGather ( Type * Ty , MaybeAlign Alignment ) { if ( ! EnableMaskedGatherScatters || ! ST -> hasMVEIntegerOps ( ) ) return false ; if ( isa < VectorType > ( Ty ) ) return false ; unsigned EltWidth = Ty -> getScalarSizeInBits ( ) ; return ( ( EltWidth == 32 && ( ! Alignment || Alignment >= 4 ) ) || ( EltWidth == 16 && ( ! Alignment || Alignment >= 2 ) ) || EltWidth == 8 ) ; } </s>

Return true if the target supports masked gather .


<s>
static
void
output_file_start
(
void
)
{
FILE
*
file
=
asm_out_file
;
int
i
;
fprintf
(
file
,
".file \"%s\";\n"
,
LOCATION_FILE
(
input_location
)
)
;
for
(
i
=
0
;
arg_regs
[
i
]
>=
0
;
i
++
)
;
max_arg_registers
=
i
;
}
</s>

Output to FILE the start of the assembler file .


"getBranchTargetOpValue is not implemented yet"

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s> bool X86AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) && ! Subtarget -> isTargetEnvMacho ( ) ) { bool Intrn = MF . getFunction ( ) -> hasInternalLinkage ( ) ; OutStreamer . BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer . EmitCOFFSymbolStorageClass ( Intrn ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer . EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer . EndCOFFSymbolDef ( ) ; } EmitFunctionHeader ( ) ; EmitFunctionBody ( ) ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> MVT getScalarShiftAmountTy ( EVT LHSTy ) const override { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> void SVEIntrinsicOpts :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . setPreservesCFG ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static void riscv_for_each_saved_reg ( HOST_WIDE_INT sp_offset , riscv_save_restore_fn fn ) { HOST_WIDE_INT offset ; offset = cfun -> machine -> frame . gp_sp_offset - sp_offset ; for ( int regno = GP_REG_FIRST ; regno <= GP_REG_LAST - 1 ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . mask , regno - GP_REG_FIRST ) ) { riscv_save_restore_reg ( word_mode , regno , offset , fn ) ; offset -= UNITS_PER_WORD ; } offset = cfun -> machine -> frame . fp_sp_offset - sp_offset ; for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . fmask , regno - FP_REG_FIRST ) ) { enum machine_mode mode = TARGET_DOUBLE_FLOAT ? DFmode : SFmode ; riscv_save_restore_reg ( mode , regno , offset , fn ) ; offset -= GET_MODE_SIZE ( mode ) ; } } </s>

Call FN for each register that is saved by the current function . SP_OFFSET is the offset of the current stack pointer from the start of the frame .


<s> static bool mips_strict_matching_cpu_name_p ( const char * canonical , const char * given ) { while ( * given != 0 && TOLOWER ( * given ) == TOLOWER ( * canonical ) ) given ++ , canonical ++ ; return ( ( * given == 0 && * canonical == 0 ) || ( strcmp ( canonical , "000" ) == 0 && strcasecmp ( given , "k" ) == 0 ) ) ; } </s>

Return true if GIVEN is the same as CANONICAL , or if it is CANONICAL with a final `` 000 '' replaced by `` k '' . Ignore case . Note : this function is shared between GCC and GAS .


<s> rtx aarch64_return_addr ( int count , rtx frame ATTRIBUTE_UNUSED ) { if ( count != 0 ) return const0_rtx ; return get_hard_reg_initial_val ( Pmode , LR_REGNUM ) ; } </s>

Implement RETURN_ADDR_RTX . We do not support moving back to a previous frame .


<s> bool AMDGPUPassConfig :: addPreISel ( ) { const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; addPass ( createFlattenCFGPass ( ) ) ; if ( ST . IsIRStructurizerEnabled ( ) ) addPass ( createStructurizeCFGPass ( ) ) ; if ( ST . getGeneration ( ) >= AMDGPUSubtarget :: SOUTHERN_ISLANDS ) { addPass ( createSinkingPass ( ) ) ; addPass ( createSITypeRewriter ( ) ) ; addPass ( createSIAnnotateControlFlowPass ( ) ) ; } else { addPass ( createR600TextureIntrinsicsReplacer ( ) ) ; } return false ; } </s>


<s>
void
AArch64TargetLowering
::
computeKnownBitsForTargetNode
(
const
SDValue
Op
,
APInt
&
KnownZero
,
APInt
&
KnownOne
,
const
APInt
&
DemandedElts
,
const
SelectionDAG
&
DAG
,
unsigned
Depth
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
break
;
case
AArch64ISD
::
CSEL
:
{
APInt
KnownZero2
,
KnownOne2
;
DAG
.
computeKnownBits
(
Op
->
getOperand
(
0
)
,
KnownZero
,
KnownOne
,
Depth
+
1
)
;
DAG
.
computeKnownBits
(
Op
->
getOperand
(
1
)
,
KnownZero2
,
KnownOne2
,
Depth
+
1
)
;
KnownZero
&=
KnownZero2
;
KnownOne
&=
KnownOne2
;
break
;
}
case
ISD
::
INTRINSIC_W_CHAIN
:
{
ConstantSDNode
*
CN
=
cast
<
ConstantSDNode
>
(
Op
->
getOperand
(
1
)
)
;
Intrinsic
::
ID
IntID
=
static_cast
<
Intrinsic
::
ID
>
(
CN
->
getZExtValue
(
)
)
;
switch
(
IntID
)
{
default
:
return
;
case
Intrinsic
::
aarch64_ldaxr
:
case
Intrinsic
::
aarch64_ldxr
:
{
unsigned
BitWidth
=
KnownOne
.
getBitWidth
(
)
;
EVT
VT
=
cast
<
MemIntrinsicSDNode
>
(
Op
)
->
getMemoryVT
(
)
;
unsigned
MemBits
=
VT
.
getScalarSizeInBits
(
)
;
KnownZero
|=
APInt
::
getHighBitsSet
(
BitWidth
,
BitWidth
MemBits
)
;
return
;
}
}
break
;
}
case
ISD
::
INTRINSIC_WO_CHAIN
:
case
ISD
::
INTRINSIC_VOID
:
{
unsigned
IntNo
=
cast
<
ConstantSDNode
>
(
Op
.
getOperand
(
0
)
)
->
getZExtValue
(
)
;
switch
(
IntNo
)
{
default
:
break
;
case
Intrinsic
::
aarch64_neon_umaxv
:
case
Intrinsic
::
aarch64_neon_uminv
:
{
MVT
VT
=
Op
.
getOperand
(
1
)
.
getValueType
(
)
.
getSimpleVT
(
)
;
unsigned
BitWidth
=
KnownZero
.
getBitWidth
(
)
;
if
(
VT
==
MVT
::
v8i8
||
VT
==
MVT
::
v16i8
)
{
assert
(
BitWidth
>=
8
&&
"Unexpected width!"
)
;
APInt
Mask
=
APInt
::
getHighBitsSet
(
BitWidth
,
BitWidth
8
)
;
KnownZero
|=
Mask
;
}
else
if
(
VT
==
MVT
::
v4i16
||
VT
==
MVT
::
v8i16
)
{
assert
(
BitWidth
>=
16
&&
"Unexpected width!"
)
;
APInt
Mask
=
APInt
::
getHighBitsSet
(
BitWidth
,
BitWidth
16
)
;
KnownZero
|=
Mask
;
}
break
;
}
break
;
}
}
}
}
</s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s>
const
TargetRegisterClass
*
MipsRegisterInfo
::
getPointerRegClass
(
const
MachineFunction
&
MF
,
unsigned
Kind
)
const
{
MipsABIInfo
ABI
=
MF
.
getSubtarget
<
MipsSubtarget
>
(
)
.
getABI
(
)
;
MipsPtrClass
PtrClassKind
=
static_cast
<
MipsPtrClass
>
(
Kind
)
;
switch
(
PtrClassKind
)
{
case
MipsPtrClass
::
Default
:
return
ABI
.
ArePtrs64bit
(
)
&
Mips
::
GPR64RegClass
:
&
Mips
::
GPR32RegClass
;
case
MipsPtrClass
::
GPR16MM
:
return
&
Mips
::
GPRMM16RegClass
;
case
MipsPtrClass
::
StackPointer
:
return
ABI
.
ArePtrs64bit
(
)
&
Mips
::
SP64RegClass
:
&
Mips
::
SP32RegClass
;
case
MipsPtrClass
::
GlobalPointer
:
return
ABI
.
ArePtrs64bit
(
)
&
Mips
::
GP64RegClass
:
&
Mips
::
GP32RegClass
;
}
llvm_unreachable
(
"Unknown pointer kind"
)
;
}
</s>


<s> Optional < DestSourcePair > RISCVInstrInfo :: isCopyInstrImpl ( const MachineInstr & MI ) const { if ( MI . isMoveReg ( ) ) return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 1 ) } ; switch ( MI . getOpcode ( ) ) { default : break ; case RISCV :: ADDI : if ( MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 1 ) } ; break ; case RISCV :: FSGNJ_D : case RISCV :: FSGNJ_S : case RISCV :: FSGNJ_H : if ( MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 2 ) . isReg ( ) && MI . getOperand ( 1 ) . getReg ( ) == MI . getOperand ( 2 ) . getReg ( ) ) return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 1 ) } ; break ; } return None ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


<s> bool MBlazePassConfig :: addInstSelector ( ) { PM . add ( createMBlazeISelDag ( getMBlazeTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const PPCFrameLowering * TFI = getFrameLowering ( MF ) ; markSuperRegs ( Reserved , PPC :: ZERO ) ; markSuperRegs ( Reserved , PPC :: FP ) ; markSuperRegs ( Reserved , PPC :: BP ) ; markSuperRegs ( Reserved , PPC :: CTR ) ; markSuperRegs ( Reserved , PPC :: CTR8 ) ; markSuperRegs ( Reserved , PPC :: R1 ) ; markSuperRegs ( Reserved , PPC :: LR ) ; markSuperRegs ( Reserved , PPC :: LR8 ) ; markSuperRegs ( Reserved , PPC :: RM ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) markSuperRegs ( Reserved , PPC :: VRSAVE ) ; if ( Subtarget . isSVR4ABI ( ) ) { const PPCFunctionInfo * FuncInfo = MF . getInfo < PPCFunctionInfo > ( ) ; if ( ! TM . isPPC64 ( ) || FuncInfo -> usesTOCBasePtr ( ) || MF . hasInlineAsm ( ) ) markSuperRegs ( Reserved , PPC :: R2 ) ; markSuperRegs ( Reserved , PPC :: R13 ) ; } if ( Subtarget . isAIXABI ( ) ) markSuperRegs ( Reserved , PPC :: R2 ) ; if ( TM . isPPC64 ( ) ) markSuperRegs ( Reserved , PPC :: R13 ) ; if ( TFI -> needsFP ( MF ) ) markSuperRegs ( Reserved , PPC :: R31 ) ; bool IsPositionIndependent = TM . isPositionIndependent ( ) ; if ( hasBasePointer ( MF ) ) { if ( Subtarget . is32BitELFABI ( ) && IsPositionIndependent ) markSuperRegs ( Reserved , PPC :: R29 ) ; else markSuperRegs ( Reserved , PPC :: R30 ) ; } if ( Subtarget . is32BitELFABI ( ) && IsPositionIndependent ) markSuperRegs ( Reserved , PPC :: R30 ) ; if ( ! Subtarget . hasAltivec ( ) ) for ( TargetRegisterClass :: iterator I = PPC :: VRRCRegClass . begin ( ) , IE = PPC :: VRRCRegClass . end ( ) ; I != IE ; ++ I ) markSuperRegs ( Reserved , * I ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> const DLXInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> bool MBlazeTargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ; if ( Kind . isMergeable1ByteCString ( ) ) return false ; Type * Ty = GV -> getType ( ) -> getElementType ( ) ; return IsInSmallSection ( TM . getTargetData ( ) -> getTypeAllocSize ( Ty ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s>
void
RISCVFrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
auto
*
RVFI
=
MF
.
getInfo
<
RISCVMachineFunctionInfo
>
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
unsigned
FPReg
=
getFPReg
(
STI
)
;
unsigned
SPReg
=
getSPReg
(
STI
)
;
DebugLoc
DL
;
if
(
shouldEnableVectorUnit
(
MF
)
)
{
BuildMI
(
MBB
,
MBBI
,
DL
,
STI
.
getInstrInfo
(
)
->
get
(
RISCV
::
VCONFIG
)
)
.
addImm
(
0x60
)
;
}
determineFrameLayout
(
MF
)
;
uint64_t
StackSize
=
MFI
.
getStackSize
(
)
;
if
(
StackSize
==
0
&&
!
MFI
.
adjustsStack
(
)
)
return
;
adjustReg
(
MBB
,
MBBI
,
DL
,
SPReg
,
SPReg
,
StackSize
,
MachineInstr
::
FrameSetup
)
;
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
.
getCalleeSavedInfo
(
)
;
std
::
advance
(
MBBI
,
CSI
.
size
(
)
)
;
if
(
hasFP
(
MF
)
)
adjustReg
(
MBB
,
MBBI
,
DL
,
FPReg
,
SPReg
,
StackSize
RVFI
->
getVarArgsSaveSize
(
)
,
MachineInstr
::
FrameSetup
)
;
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

RISCV
RISCV
"Shrink-wrapping not yet supported"
RISCV
RISCV::VCONFIG
0x60
0


<s> void X86ATTInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << '%' << getRegisterName ( RegNo ) ; } </s>


<s> unsigned SPIRVTargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT . isVector ( ) && VT . getVectorNumElements ( ) == 3 && ( VT . getVectorElementType ( ) == MVT :: i1 || VT . getVectorElementType ( ) == MVT :: i8 ) ) return 1 ; return getNumRegisters ( Context , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s> static inline int shiftcosts ( rtx x ) { int value ; if ( TARGET_SHMEDIA ) return 1 ; if ( GET_MODE_SIZE ( GET_MODE ( x ) ) > UNITS_PER_WORD ) { if ( GET_MODE ( x ) == DImode && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT && INTVAL ( XEXP ( x , 1 ) ) == 1 ) return 2 ; return 10000 ; } if ( GET_CODE ( XEXP ( x , 1 ) ) != CONST_INT ) return SH_DYNAMIC_SHIFT_COST ; value = INTVAL ( XEXP ( x , 1 ) ) ; if ( GET_CODE ( x ) == ASHIFTRT ) { int cost = ashiftrt_insns [ value ] ; if ( cost > 1 + SH_DYNAMIC_SHIFT_COST ) cost = 1 + SH_DYNAMIC_SHIFT_COST ; return cost ; } else return shift_insns [ value ] ; } </s>


<s>
unsigned
ARM64TargetLowering
::
getRegisterByName
(
const
char
*
RegName
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"sp"
,
ARM64
::
SP
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> static bool insn_is_function_arg ( rtx insn , bool * is_spilled ) { rtx dst ; if ( ! NONDEBUG_INSN_P ( insn ) ) return false ; if ( CALL_P ( insn ) ) return false ; insn = PATTERN ( insn ) ; if ( GET_CODE ( insn ) == PARALLEL ) insn = XVECEXP ( insn , 0 , 0 ) ; if ( GET_CODE ( insn ) != SET ) return false ; dst = SET_DEST ( insn ) ; if ( REG_P ( dst ) && HARD_REGISTER_P ( dst ) && ix86_function_arg_regno_p ( REGNO ( dst ) ) ) { if ( ! TEST_HARD_REG_BIT ( fixed_reg_set , REGNO ( dst ) ) && ix86_class_likely_spilled_p ( REGNO_REG_CLASS ( REGNO ( dst ) ) ) ) * is_spilled = true ; return true ; } return false ; } </s>

Returns true if lhs of insn is HW function argument register and set up is_spilled to true if it is likely spilled HW register .


<s> bool MSP430DAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintCode ) { default : return true ; case 'm' : if ( ! SelectAddr ( Op . getNode ( ) , Op , Op0 , Op1 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s>
void
MipsDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
if
(
trySelect
(
Node
)
)
return
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
ReplaceNode
(
Node
,
getGlobalBaseReg
(
)
)
;
return
;
case
ISD
::
LOAD
:
case
ISD
::
STORE
:
assert
(
(
Subtarget
->
systemSupportsUnalignedAccess
(
)
||
cast
<
MemSDNode
>
(
Node
)
->
getMemoryVT
(
)
.
getSizeInBits
(
)
/
8
<=
cast
<
MemSDNode
>
(
Node
)
->
getAlignment
(
)
)
&&
"Unexpected unaligned loads/stores."
)
;
break
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

Mips
Mips
"== "
"\n"
1
ISD::GLOBAL_OFFSET_TABLE
ISD::LOAD
ISD::STORE
8
"Unexpected unaligned loads/stores."


<s> bool mprocFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool Cpu0SETargetLowering :: isEligibleForTailCallOptimization ( const Cpu0CC & Cpu0CCInfo , unsigned NextStackOffset , const Cpu0MachineFunctionInfo & FI ) const { if ( ! EnableCpu0TailCalls ) return false ; if ( Cpu0CCInfo . hasByValArg ( ) || FI . hasByvalArg ( ) ) return false ; return NextStackOffset <= FI . getIncomingArgSize ( ) ; } </s>

Returns true if the call can be lowered as a tail call .


<s> static rtx rs6000_load_constant_and_splat ( machine_mode mode , REAL_VALUE_TYPE dconst ) { rtx reg ; if ( mode == SFmode || mode == DFmode ) { rtx d = const_double_from_real_value ( dconst , mode ) ; reg = force_reg ( mode , d ) ; } else if ( mode == V4SFmode ) { rtx d = const_double_from_real_value ( dconst , SFmode ) ; rtvec v = gen_rtvec ( 4 , d , d , d , d ) ; reg = gen_reg_rtx ( mode ) ; rs6000_expand_vector_init ( reg , gen_rtx_PARALLEL ( mode , v ) ) ; } else if ( mode == V2DFmode ) { rtx d = const_double_from_real_value ( dconst , DFmode ) ; rtvec v = gen_rtvec ( 2 , d , d ) ; reg = gen_reg_rtx ( mode ) ; rs6000_expand_vector_init ( reg , gen_rtx_PARALLEL ( mode , v ) ) ; } else gcc_unreachable ( ) ; return reg ; } </s>

Load up a constant . If the mode is a vector mode , splat the value across all of the vector elements .


<s> int m32r_legitimate_pic_operand_p ( rtx x ) { if ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF ) return 0 ; if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && ( GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == SYMBOL_REF || GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == LABEL_REF ) && ( GET_CODE ( XEXP ( XEXP ( x , 0 ) , 1 ) ) == CONST_INT ) ) return 0 ; return 1 ; } </s>


<s>
bool
X86CmovConverterPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
if
(
!
EnableCmovConverter
)
return
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"********** "
<<
getPassName
(
)
<<
" : "
<<
MF
.
getName
(
)
<<
"**********\n"
)
;
bool
Changed
=
false
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
const
TargetSubtargetInfo
&
STI
=
MF
.
getSubtarget
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
TII
=
STI
.
getInstrInfo
(
)
;
TRI
=
STI
.
getRegisterInfo
(
)
;
TSchedModel
.
init
(
&
STI
)
;
if
(
ForceMemOperand
||
ForceAll
)
{
CmovGroups
AllCmovGroups
;
SmallVector
<
MachineBasicBlock
*
,
4
>
Blocks
;
for
(
auto
&
MBB
:
MF
)
Blocks
.
push_back
(
&
MBB
)
;
if
(
collectCmovCandidates
(
Blocks
,
AllCmovGroups
,
true
)
)
{
for
(
auto
&
Group
:
AllCmovGroups
)
{
if
(
ForceMemOperand
&&
!
ForceAll
&&
llvm
::
none_of
(
Group
,
[
&
]
(
MachineInstr
*
I
)
{
return
I
->
mayLoad
(
)
;
}
)
)
continue
;
Changed
=
true
;
convertCmovInstsToBranches
(
Group
)
;
}
}
if
(
ForceAll
)
return
Changed
;
}
SmallVector
<
MachineLoop
*
,
4
>
Loops
(
MLI
->
begin
(
)
,
MLI
->
end
(
)
)
;
for
(
int
i
=
0
;
i
<
(
int
)
Loops
.
size
(
)
;
++
i
)
for
(
MachineLoop
*
Child
:
Loops
[
i
]
->
getSubLoops
(
)
)
Loops
.
push_back
(
Child
)
;
for
(
MachineLoop
*
CurrLoop
:
Loops
)
{
if
(
!
CurrLoop
->
getSubLoops
(
)
.
empty
(
)
)
continue
;
CmovGroups
CmovInstGroups
;
if
(
!
collectCmovCandidates
(
CurrLoop
->
getBlocks
(
)
,
CmovInstGroups
)
)
continue
;
if
(
!
checkForProfitableCmovCandidates
(
CurrLoop
->
getBlocks
(
)
,
CmovInstGroups
)
)
continue
;
Changed
=
true
;
for
(
auto
&
Group
:
CmovInstGroups
)
convertCmovInstsToBranches
(
Group
)
;
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s>
Function
*
AMDGPUIntrinsicInfo
::
getDeclaration
(
Module
*
M
,
unsigned
IntrID
,
Type
*
*
Tys
,
unsigned
numTys
)
const
{
llvm_unreachable
(
"Not implemented"
)
;
}
</s>

Create or insert an LLVM Function declaration for an intrinsic , and return it .


<s> void WebAssemblyDebugValueManager :: clone ( MachineInstr * Insert , unsigned NewReg ) { MachineBasicBlock * MBB = Insert -> getParent ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; for ( MachineInstr * DBI : reverse ( DbgValues ) ) { MachineInstr * Clone = MF -> CloneMachineInstr ( DBI ) ; for ( auto & MO : Clone -> getDebugOperandsForReg ( CurrentReg ) ) MO . setReg ( NewReg ) ; MBB -> insert ( Insert , Clone ) ; } } </s>

Make a functionally equivalent copy of this MachineFunctionInfo in MF .


<s> bool Z80AsmParser :: ParseDirective ( AsmToken DirectiveID ) { return false ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> void PPCOperand :: print ( raw_ostream & OS ) const { switch ( Kind ) { case Token : OS << "'" << getToken ( ) << "'" ; break ; case Immediate : OS << getImm ( ) ; break ; case Expression : getExpr ( ) -> print ( OS ) ; break ; case TLSRegister : getTLSReg ( ) -> print ( OS ) ; break ; } } </s>

print - Print a debug representation of the operand to the given stream .


<s> static void rs6000_emit_dot_insn ( rtx dst , rtx src , int dot , rtx ccreg ) { if ( dot == 0 ) { emit_move_insn ( dst , src ) ; return ; } if ( cc_reg_not_cr0_operand ( ccreg , CCmode ) ) { emit_move_insn ( dst , src ) ; emit_move_insn ( ccreg , gen_rtx_COMPARE ( CCmode , dst , const0_rtx ) ) ; return ; } rtx ccset = gen_rtx_SET ( ccreg , gen_rtx_COMPARE ( CCmode , src , const0_rtx ) ) ; if ( dot == 1 ) { rtx clobber = gen_rtx_CLOBBER ( VOIDmode , dst ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , ccset , clobber ) ) ) ; } else { rtx set = gen_rtx_SET ( dst , src ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , ccset , set ) ) ) ; } } </s>

Emit a potentially record-form instruction , setting DST from SRC . If DOT is 0 , that is all ; otherwise , set CCREG to the result of the signed comparison of DST with zero . If DOT is 1 , the generated RTL does n't care about the DST result ; if DOT is 2 , it does . If CCREG is CR0 do a single dot insn ( as a PARALLEL ) ; otherwise , do a SET and a separate COMPARE .


<s> bool M68kCallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < Register > VRegs , FunctionLoweringInfo & FLI , Register SwiftErrorVReg ) const { auto MIB = MIRBuilder . buildInstrNoInsert ( M68k :: RTS ) ; bool Success = true ; MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const M68kTargetLowering & TLI = * getTLI < M68kTargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . getCCAssignFn ( F . getCallingConv ( ) , true , F . isVarArg ( ) ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; if ( ! VRegs . empty ( ) ) { SmallVector < ArgInfo , 8 > SplitArgs ; ArgInfo OrigArg { VRegs , Val -> getType ( ) , 0 } ; setArgFlags ( OrigArg , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , F . getCallingConv ( ) ) ; OutgoingValueAssigner ArgAssigner ( AssignFn ) ; M68kOutgoingArgHandler ArgHandler ( MIRBuilder , MRI , MIB ) ; Success = determineAndHandleAssignments ( ArgHandler , ArgAssigner , SplitArgs , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ; } MIRBuilder . insertInstr ( MIB ) ; return Success ; } </s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> static void ix86_avx256_split_vector_move_misalign ( rtx op0 , rtx op1 ) { rtx m ; rtx ( * extract ) ( rtx , rtx , rtx ) ; machine_mode mode ; if ( ( MEM_P ( op1 ) && ! TARGET_AVX256_SPLIT_UNALIGNED_LOAD ) || ( MEM_P ( op0 ) && ! TARGET_AVX256_SPLIT_UNALIGNED_STORE ) ) { emit_insn ( gen_rtx_SET ( op0 , op1 ) ) ; return ; } rtx orig_op0 = NULL_RTX ; mode = GET_MODE ( op0 ) ; switch ( GET_MODE_CLASS ( mode ) ) { case MODE_VECTOR_INT : case MODE_INT : if ( mode != V32QImode ) { if ( ! MEM_P ( op0 ) ) { orig_op0 = op0 ; op0 = gen_reg_rtx ( V32QImode ) ; } else op0 = gen_lowpart ( V32QImode , op0 ) ; op1 = gen_lowpart ( V32QImode , op1 ) ; mode = V32QImode ; } break ; case MODE_VECTOR_FLOAT : break ; default : gcc_unreachable ( ) ; } switch ( mode ) { default : gcc_unreachable ( ) ; case V32QImode : extract = gen_avx_vextractf128v32qi ; mode = V16QImode ; break ; case V8SFmode : extract = gen_avx_vextractf128v8sf ; mode = V4SFmode ; break ; case V4DFmode : extract = gen_avx_vextractf128v4df ; mode = V2DFmode ; break ; } if ( MEM_P ( op1 ) ) { rtx r = gen_reg_rtx ( mode ) ; m = adjust_address ( op1 , mode , 0 ) ; emit_move_insn ( r , m ) ; m = adjust_address ( op1 , mode , 16 ) ; r = gen_rtx_VEC_CONCAT ( GET_MODE ( op0 ) , r , m ) ; emit_move_insn ( op0 , r ) ; } else if ( MEM_P ( op0 ) ) { m = adjust_address ( op0 , mode , 0 ) ; emit_insn ( extract ( m , op1 , const0_rtx ) ) ; m = adjust_address ( op0 , mode , 16 ) ; emit_insn ( extract ( m , copy_rtx ( op1 ) , const1_rtx ) ) ; } else gcc_unreachable ( ) ; if ( orig_op0 ) emit_move_insn ( orig_op0 , gen_lowpart ( GET_MODE ( orig_op0 ) , op0 ) ) ; } </s>

Split 32-byte AVX unaligned load and store if needed .


<s> bool NVPTXAsmPrinter :: runOnMachineFunction ( MachineFunction & F ) { bool Result = AsmPrinter :: runOnMachineFunction ( F ) ; OutStreamer -> EmitRawText ( StringRef ( "}\n" ) ) ; return Result ; } </s>


<s> bool MipsAsmParser :: ParseDirective ( AsmToken DirectiveID ) { if ( DirectiveID . getString ( ) == ".ent" ) { Parser . Lex ( ) ; return false ; } if ( DirectiveID . getString ( ) == ".end" ) { Parser . Lex ( ) ; return false ; } if ( DirectiveID . getString ( ) == ".frame" ) { Parser . EatToEndOfStatement ( ) ; return false ; } if ( DirectiveID . getString ( ) == ".set" ) { return parseDirectiveSet ( ) ; } if ( DirectiveID . getString ( ) == ".fmask" ) { Parser . EatToEndOfStatement ( ) ; return false ; } if ( DirectiveID . getString ( ) == ".mask" ) { Parser . EatToEndOfStatement ( ) ; return false ; } if ( DirectiveID . getString ( ) == ".gpword" ) { Parser . EatToEndOfStatement ( ) ; return false ; } return true ; } </s>


<s> void HSAILPassConfig :: addIRPasses ( ) { addPass ( createHSAILAlwaysInlinePass ( ) ) ; addPass ( createAlwaysInlinerPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"MSP430 Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
char
*
emit_cond_move
(
rtx
*
operands
,
rtx
insn
ATTRIBUTE_UNUSED
)
{
static
char
buffer
[
100
]
;
const
char
*
dest
=
reg_names
[
REGNO
(
operands
[
0
]
)
]
;
buffer
[
0
]
=
0
;
gcc_assert
(
REG_P
(
operands
[
0
]
)
)
;
gcc_assert
(
conditional_move_operand
(
operands
[
2
]
,
SImode
)
)
;
gcc_assert
(
conditional_move_operand
(
operands
[
3
]
,
SImode
)
)
;
if
(
GET_CODE
(
operands
[
1
]
)
==
NE
)
{
rtx
tmp
=
operands
[
2
]
;
operands
[
2
]
=
operands
[
3
]
;
operands
[
3
]
=
tmp
;
}
sprintf
(
buffer
,
"mvfc %s, cbr"
,
dest
)
;
if
(
INTVAL
(
operands
[
2
]
)
==
0
)
sprintf
(
buffer
+
strlen
(
buffer
)
,
"\n\txor3 %s, %s, #1"
,
dest
,
dest
)
;
return
buffer
;
}
</s>

Generate the correct assembler code to handle the conditional loading of a value into a register . It is known that the operands satisfy the conditional_move_operand ( ) function above . The destination is operand [ 0 ] . The condition is operand [ 1 ] . The 'true ' value is operand [ 2 ] and the 'false ' value is operand [ 3 ] .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < MachineBranchProbabilityInfo > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
static
rtx
m32c_function_arg
(
cumulative_args_t
ca_v
,
machine_mode
mode
,
const_tree
type
,
bool
named
)
{
CUMULATIVE_ARGS
*
ca
=
get_cumulative_args
(
ca_v
)
;
rtx
rv
=
NULL_RTX
;
fprintf
(
stderr
,
"func_arg %d (%s, %d)\n"
,
ca
->
parm_num
,
mode_name
[
mode
]
,
named
)
;
debug_tree
(
(
tree
)
type
)
;
if
(
mode
==
VOIDmode
)
return
GEN_INT
(
0
)
;
if
(
ca
->
force_mem
||
!
named
)
{
fprintf
(
stderr
,
"func arg: force %d named %d, mem\n"
,
ca
->
force_mem
,
named
)
;
return
NULL_RTX
;
}
if
(
type
&&
INTEGRAL_TYPE_P
(
type
)
&&
POINTER_TYPE_P
(
type
)
)
return
NULL_RTX
;
if
(
type
&&
AGGREGATE_TYPE_P
(
type
)
)
return
NULL_RTX
;
switch
(
ca
->
parm_num
)
{
case
1
:
if
(
GET_MODE_SIZE
(
mode
)
==
1
||
GET_MODE_SIZE
(
mode
)
==
2
)
rv
=
gen_rtx_REG
(
mode
,
TARGET_A16
R1_REGNO
:
R0_REGNO
)
;
break
;
case
2
:
if
(
TARGET_A16
&&
GET_MODE_SIZE
(
mode
)
==
2
)
rv
=
gen_rtx_REG
(
mode
,
R2_REGNO
)
;
break
;
}
debug_rtx
(
rv
)
;
return
rv
;
}
</s>

Implements FUNCTION_ARG . Arguments are passed partly in registers , partly on stack . If our function returns a struct , a pointer to a buffer for it is at the top of the stack ( last thing pushed ) . The first few real arguments may be in registers as follows : R8C/M16C : arg1 in r1 if it 's QI or HI ( else it 's pushed on stack ) arg2 in r2 if it 's HI ( else pushed on stack ) rest on stack M32C : arg1 in r0 if it 's QI or HI ( else it 's pushed on stack ) rest on stack Structs are not passed in registers , even if they fit . Only integer and pointer types are passed in registers . Note that when arg1 does n't fit in r1 , arg2 may still be passed in r2 if it fits .


<s> bool SIWholeQuadMode :: runOnMachineFunction ( MachineFunction & MF ) { Instructions . clear ( ) ; Blocks . clear ( ) ; LiveMaskQueries . clear ( ) ; LowerToCopyInstrs . clear ( ) ; CallingConv = MF . getFunction ( ) . getCallingConv ( ) ; ST = & MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST -> getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; LIS = & getAnalysis < LiveIntervals > ( ) ; char GlobalFlags = analyzeFunction ( MF ) ; unsigned LiveMaskReg = 0 ; unsigned Exec = ST -> isWave32 ( ) ? AMDGPU :: EXEC_LO : AMDGPU :: EXEC ; if ( ! ( GlobalFlags & StateWQM ) ) { lowerLiveMaskQueries ( Exec ) ; if ( ! ( GlobalFlags & StateWWM ) && LowerToCopyInstrs . empty ( ) ) return ! LiveMaskQueries . empty ( ) ; } else { MachineBasicBlock & Entry = MF . front ( ) ; MachineBasicBlock :: iterator EntryMI = Entry . getFirstNonPHI ( ) ; if ( GlobalFlags & StateExact || ! LiveMaskQueries . empty ( ) ) { LiveMaskReg = MRI -> createVirtualRegister ( TRI -> getBoolRC ( ) ) ; MachineInstr * MI = BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( AMDGPU :: COPY ) , LiveMaskReg ) . addReg ( Exec ) ; LIS -> InsertMachineInstrInMaps ( * MI ) ; } lowerLiveMaskQueries ( LiveMaskReg ) ; if ( GlobalFlags == StateWQM ) { BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( ST -> isWave32 ( ) ? AMDGPU :: S_WQM_B32 : AMDGPU :: S_WQM_B64 ) , Exec ) . addReg ( Exec ) ; lowerCopyInstrs ( ) ; return true ; } } LLVM_DEBUG ( printInfo ( ) ) ; lowerCopyInstrs ( ) ; for ( auto BII : Blocks ) processBlock ( * BII . first , LiveMaskReg , BII . first == & * MF . begin ( ) ) ; LIS -> removeRegUnit ( * MCRegUnitIterator ( AMDGPU :: SCC , TRI ) ) ; return true ; } </s>


"PIC16 Does not have any frame register"


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT VT ) const override { return MVT :: i8 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> void sh_emit_compare_and_branch ( rtx * operands , machine_mode mode ) { enum rtx_code code = GET_CODE ( operands [ 0 ] ) ; enum rtx_code branch_code ; rtx op0 = operands [ 1 ] ; rtx op1 = operands [ 2 ] ; rtx insn ; bool need_ccmpeq = false ; if ( TARGET_SH2E && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { op0 = force_reg ( mode , op0 ) ; op1 = force_reg ( mode , op1 ) ; } else { if ( code != EQ || mode == DImode ) { op0 = force_reg ( mode , op0 ) ; if ( op1 != const0_rtx || code == GTU || code == GEU ) op1 = force_reg ( mode , op1 ) ; } } if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { if ( code == LT || ( code == LE && TARGET_IEEE && TARGET_SH2E ) || ( code == GE && ! ( TARGET_IEEE && TARGET_SH2E ) ) ) { std :: swap ( op0 , op1 ) ; code = swap_condition ( code ) ; } if ( code == GE ) { gcc_assert ( TARGET_IEEE && TARGET_SH2E ) ; need_ccmpeq = true ; code = GT ; } gcc_assert ( code == EQ || code == GT || code == NE || code == LE ) ; } switch ( code ) { case EQ : case GT : case GE : case GTU : case GEU : branch_code = code ; break ; case NE : case LT : case LE : case LTU : case LEU : branch_code = reverse_condition ( code ) ; break ; default : gcc_unreachable ( ) ; } insn = gen_rtx_SET ( get_t_reg_rtx ( ) , gen_rtx_fmt_ee ( branch_code , SImode , op0 , op1 ) ) ; sh_emit_set_t_insn ( insn , mode ) ; if ( need_ccmpeq ) sh_emit_set_t_insn ( gen_ieee_ccmpeqsf_t ( op0 , op1 ) , mode ) ; if ( branch_code == code ) emit_jump_insn ( gen_branch_true ( operands [ 3 ] ) ) ; else emit_jump_insn ( gen_branch_false ( operands [ 3 ] ) ) ; } </s>

Called from the md file , set up the operands of a compare instruction .


"%qs attribute only applies to functions"

"%qE cannot have both %qs and %qs attributes"


<s> bool SIRegisterInfo :: requiresFrameIndexReplacementScavenging ( const MachineFunction & MF ) const { return MF . getFrameInfo ( ) . hasStackObjects ( ) && MF . getSubtarget < SISubtarget > ( ) . hasScalarStores ( ) && MF . getInfo < SIMachineFunctionInfo > ( ) -> hasSpilledSGPRs ( ) ; } </s>

Returns true if the target requires using the RegScavenger directly for frame elimination despite using requiresFrameIndexScavenging .


<s> void X86InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC ) const { const MachineFunction & MF = * MBB . getParent ( ) ; bool isAligned = ( RI . getStackAlignment ( ) >= 16 ) || RI . canRealignStack ( MF ) ; unsigned Opc = getStoreRegOpcode ( SrcReg , RC , isAligned , TM ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) ) , FrameIdx ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool X86FastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { const Value * Ptr = LI -> getPointerOperand ( ) ; X86AddressMode AM ; if ( ! X86SelectAddress ( Ptr , AM ) ) return false ; const X86InstrInfo & XII = ( const X86InstrInfo & ) TII ; unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; unsigned Alignment = LI -> getAlignment ( ) ; if ( Alignment == 0 ) Alignment = DL . getABITypeAlignment ( LI -> getType ( ) ) ; SmallVector < MachineOperand , 8 > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , MI , OpNo , AddrOps , Size , Alignment ) ; if ( ! Result ) return false ; Result -> addMemOperand ( * FuncInfo . MF , createMachineMemOperandFor ( LI ) ) ; FuncInfo . MBB -> insert ( FuncInfo . InsertPt , Result ) ; MI -> eraseFromParent ( ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> static unsigned HOST_WIDE_INT s390_asan_shadow_offset ( void ) { return TARGET_64BIT ? HOST_WIDE_INT_1U << 52 : HOST_WIDE_INT_UC ( 0x20000000 ) ; } </s>

Implement the TARGET_ASAN_SHADOW_OFFSET hook .


<s> rtx visium_dynamic_chain_address ( rtx frame ) { visium_frame_needed = true ; return frame ; } </s>

A C expression whose value is RTL representing the address in a stack frame where the pointer to the caller 's frame is stored . Assume that FRAMEADDR is an RTL expression for the address of the stack frame itself . If you do n't define this macro , the default is to return the value of FRAMEADDR -- that is , the stack frame address is also the address of the stack word that points to the previous frame .


<s> static rtx x86_this_parameter ( tree function ) { tree type = TREE_TYPE ( function ) ; bool aggr = aggregate_value_p ( TREE_TYPE ( type ) , type ) != 0 ; int nregs ; if ( TARGET_64BIT ) { const int * parm_regs ; if ( ix86_function_type_abi ( type ) == MS_ABI ) parm_regs = x86_64_ms_abi_int_parameter_registers ; else parm_regs = x86_64_int_parameter_registers ; return gen_rtx_REG ( Pmode , parm_regs [ aggr ] ) ; } nregs = ix86_function_regparm ( type , function ) ; if ( nregs > 0 && ! stdarg_p ( type ) ) { int regno ; unsigned int ccvt = ix86_get_callcvt ( type ) ; if ( ( ccvt & IX86_CALLCVT_FASTCALL ) != 0 ) regno = aggr ? DX_REG : CX_REG ; else if ( ( ccvt & IX86_CALLCVT_THISCALL ) != 0 ) { regno = CX_REG ; if ( aggr ) return gen_rtx_MEM ( SImode , plus_constant ( Pmode , stack_pointer_rtx , 4 ) ) ; } else { regno = AX_REG ; if ( aggr ) { regno = DX_REG ; if ( nregs == 1 ) return gen_rtx_MEM ( SImode , plus_constant ( Pmode , stack_pointer_rtx , 4 ) ) ; } } return gen_rtx_REG ( SImode , regno ) ; } return gen_rtx_MEM ( SImode , plus_constant ( Pmode , stack_pointer_rtx , aggr ? 8 : 4 ) ) ; } </s>

Returns an expression indicating where the this parameter is located on entry to the FUNCTION .


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> enum reg_class mips_secondary_reload_class ( enum reg_class rclass , machine_mode mode , rtx x , bool ) { int regno ; if ( mips_dangerous_for_la25_p ( x ) ) return reg_class_subset_p ( rclass , LEA_REGS ) ? NO_REGS : LEA_REGS ; regno = true_regnum ( x ) ; if ( TARGET_MIPS16 ) { if ( ! reg_class_subset_p ( rclass , M16_REGS ) && ! M16_REG_P ( regno ) ) return M16_REGS ; return NO_REGS ; } if ( reg_class_subset_p ( rclass , ACC_REGS ) ) return GP_REG_P ( regno ) ? NO_REGS : GR_REGS ; if ( ACC_REG_P ( regno ) ) return reg_class_subset_p ( rclass , GR_REGS ) ? NO_REGS : GR_REGS ; if ( reg_class_subset_p ( rclass , FP_REGS ) ) { if ( regno < 0 || ( MEM_P ( x ) && ( GET_MODE_SIZE ( mode ) == 4 || GET_MODE_SIZE ( mode ) == 8 ) ) ) return NO_REGS ; if ( GP_REG_P ( regno ) || x == CONST0_RTX ( mode ) ) return NO_REGS ; if ( CONSTANT_P ( x ) && ! targetm . cannot_force_const_mem ( mode , x ) ) return NO_REGS ; if ( FP_REG_P ( regno ) && mips_mode_ok_for_mov_fmt_p ( mode ) ) return NO_REGS ; return GR_REGS ; } if ( FP_REG_P ( regno ) ) return reg_class_subset_p ( rclass , GR_REGS ) ? NO_REGS : GR_REGS ; return NO_REGS ; } </s>

This function returns the register class required for a secondary register when copying between one of the registers in CLASS , and X , using MODE . If IN_P is nonzero , the copy is going from X to the register , otherwise the register is the source . A return value of NO_REGS means that no secondary register is required .


<s> int PPCTTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { if ( DisablePPCConstHoist ) return BaseT :: getIntImmCostInst ( Opcode , Idx , Imm , Ty , CostKind ) ; assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return ~ 0U ; unsigned ImmIdx = ~ 0U ; bool ShiftedFree = false , RunFree = false , UnsignedFree = false , ZeroFree = false ; switch ( Opcode ) { default : return TTI :: TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: And : RunFree = true ; LLVM_FALLTHROUGH ; case Instruction :: Add : case Instruction :: Or : case Instruction :: Xor : ShiftedFree = true ; LLVM_FALLTHROUGH ; case Instruction :: Sub : case Instruction :: Mul : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : ImmIdx = 1 ; break ; case Instruction :: ICmp : UnsignedFree = true ; ImmIdx = 1 ; LLVM_FALLTHROUGH ; case Instruction :: Select : ZeroFree = true ; break ; case Instruction :: PHI : case Instruction :: Call : case Instruction :: Ret : case Instruction :: Load : case Instruction :: Store : break ; } if ( ZeroFree && Imm == 0 ) return TTI :: TCC_Free ; if ( Idx == ImmIdx && Imm . getBitWidth ( ) <= 64 ) { if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; if ( RunFree ) { if ( Imm . getBitWidth ( ) <= 32 && ( isShiftedMask_32 ( Imm . getZExtValue ( ) ) || isShiftedMask_32 ( ~ Imm . getZExtValue ( ) ) ) ) return TTI :: TCC_Free ; if ( ST -> isPPC64 ( ) && ( isShiftedMask_64 ( Imm . getZExtValue ( ) ) || isShiftedMask_64 ( ~ Imm . getZExtValue ( ) ) ) ) return TTI :: TCC_Free ; } if ( UnsignedFree && isUInt < 16 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( ShiftedFree && ( Imm . getZExtValue ( ) & 0xFFFF ) == 0 ) return TTI :: TCC_Free ; } return PPCTTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> void s390_expand_cs ( machine_mode mode , rtx btarget , rtx vtarget , rtx mem , rtx cmp , rtx new_rtx , bool is_weak ) { switch ( mode ) { case E_TImode : case E_DImode : case E_SImode : s390_expand_cs_tdsi ( mode , btarget , vtarget , mem , cmp , new_rtx , is_weak ) ; break ; case E_HImode : case E_QImode : s390_expand_cs_hqi ( mode , btarget , vtarget , mem , cmp , new_rtx , is_weak ) ; break ; default : gcc_unreachable ( ) ; } } </s>

Expand an atomic compare and swap operation . MEM is the memory location , CMP the old value to compare MEM with and NEW_RTX the value to set if CMP == MEM .


<s> void handle_arm_neon_h ( void ) { aarch64_simd_switcher simd ; for ( unsigned int i = 0 ; i < ARM_NEON_H_TYPES_LAST ; i ++ ) for ( unsigned int count = 2 ; count <= 4 ; ++ count ) if ( ! aarch64_scalar_builtin_type_p ( aarch64_simd_types [ i ] . type ) ) register_tuple_type ( count , i ) ; aarch64_init_simd_builtin_functions ( true ) ; } </s>

Implement # pragma GCC aarch64 `` arm_neon.h '' . The types and functions defined here need to be available internally during LTO as well .


<s> static bool rs6000_emit_move_si_sf_subreg ( rtx dest , rtx source , machine_mode mode ) { if ( TARGET_DIRECT_MOVE_64BIT && ! lra_in_progress && ! reload_completed && ( ! SUBREG_P ( dest ) || ! sf_subreg_operand ( dest , mode ) ) && SUBREG_P ( source ) && sf_subreg_operand ( source , mode ) ) { rtx inner_source = SUBREG_REG ( source ) ; machine_mode inner_mode = GET_MODE ( inner_source ) ; if ( mode == SImode && inner_mode == SFmode ) { emit_insn ( gen_movsi_from_sf ( dest , inner_source ) ) ; return true ; } if ( mode == SFmode && inner_mode == SImode ) { emit_insn ( gen_movsf_from_si ( dest , inner_source ) ) ; return true ; } } return false ; } </s>

Helper function to change moves with : ( SUBREG : SF ( REG : SI ) ) and ( SUBREG : SI ( REG : SF ) ) into separate UNSPEC insns . In the PowerPC architecture , scalar SFmode values are stored as DFmode values in the VSX registers . We need to convert the bits before we can use a direct move or operate on the bits in the vector register as an integer type . Skip things like ( set ( SUBREG : SI ( ... ) ( SUBREG : SI ( ... ) ) .


<s> static bool v850_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) { if ( ! TARGET_GCC_ABI ) return 0 ; unsigned HOST_WIDE_INT size = arg . type_size_in_bytes ( ) ; return size > 8 ; } </s>

Handle the TARGET_PASS_BY_REFERENCE target hook . Specify whether to pass the argument by reference .


"Should be loading %r15 and something else"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool MSP430TargetLowering :: isTruncateFree ( EVT VT1 , EVT VT2 ) const { if ( ! VT1 . isInteger ( ) || ! VT2 . isInteger ( ) ) return false ; return ( VT1 . getFixedSizeInBits ( ) > VT2 . getFixedSizeInBits ( ) ) ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


"Unmatched number of shufflevectors and indices"

Lower interleaved load ( s ) into target specific instructions/intrinsics .


<s> void cr16_decompose_const ( rtx x , int * code , enum data_model_type * data , bool treat_as_const ) { * code = - 1 ; * data = ILLEGAL_DM ; switch ( GET_CODE ( x ) ) { case SYMBOL_REF : * code = SYMBOL_REF_FUNCTION_P ( x ) ? 2 : 0 ; if ( * code == 0 ) { if ( CR16_TARGET_DATA_NEAR ) * data = DM_DEFAULT ; else if ( CR16_TARGET_DATA_MEDIUM ) * data = DM_FAR ; else if ( CR16_TARGET_DATA_FAR ) { if ( treat_as_const ) * data = DM_FAR ; else * data = ILLEGAL_DM ; } } return ; case LABEL_REF : * code = 1 ; return ; case PLUS : case MINUS : if ( GET_CODE ( XEXP ( x , 0 ) ) == CONST_INT ) cr16_decompose_const ( XEXP ( x , 1 ) , code , data , treat_as_const ) ; else if ( GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) cr16_decompose_const ( XEXP ( x , 0 ) , code , data , treat_as_const ) ; return ; default : return ; } } </s>

Helper functions : Created specifically for decomposing operand of CONST Recursively look into expression x for code or data symbol . The function expects the expression to contain combination of SYMBOL_REF , CONST_INT , ( PLUS or MINUS ) LABEL_REF , CONST_INT , ( PLUS or MINUS ) SYMBOL_REF LABEL_REF All other combinations will result in code = -1 and data = ILLEGAL_DM code data -1 ILLEGAL_DM The expression did not contain SYMBOL_REF or LABEL_REF 0 DM_FAR SYMBOL_REF was found and it was far data reference . 0 DM_DEFAULT SYMBOL_REF was found and it was medium data reference . 1 ILLEGAL_DM LABEL_REF was found . 2 ILLEGAL_DM SYMBOL_REF was found and it was function reference .


<s> size_t AMDGPUPeepholeOpt :: getTypeSize ( OpaqueType * const OT , bool dereferencePtr ) { return 4 ; } </s>

Gets the type size ( in bytes ) for this DIE .


<s>
MachineBasicBlock
*
CSKYTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unexpected instr type to insert"
)
;
case
CSKY
::
FSELS
:
case
CSKY
::
FSELD
:
if
(
Subtarget
.
hasE2
(
)
)
return
emitSelectPseudo
(
MI
,
BB
,
CSKY
::
BT32
)
;
else
return
emitSelectPseudo
(
MI
,
BB
,
CSKY
::
BT16
)
;
case
CSKY
::
ISEL32
:
return
emitSelectPseudo
(
MI
,
BB
,
CSKY
::
BT32
)
;
case
CSKY
::
ISEL16
:
return
emitSelectPseudo
(
MI
,
BB
,
CSKY
::
BT16
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> bool XCoreTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < EVT > & OutTys , const SmallVectorImpl < ISD :: ArgFlagsTy > & ArgsFlags , SelectionDAG & DAG ) { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; return CCInfo . CheckReturn ( OutTys , ArgsFlags , RetCC_XCore ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> static void s390_add_constant ( struct constant_pool * pool , rtx val , enum machine_mode mode ) { struct constant * c ; int i ; for ( i = 0 ; i < NR_C_MODES ; i ++ ) if ( constant_modes [ i ] == mode ) break ; gcc_assert ( i != NR_C_MODES ) ; for ( c = pool -> constants [ i ] ; c != NULL ; c = c -> next ) if ( rtx_equal_p ( val , c -> value ) ) break ; if ( c == NULL ) { c = ( struct constant * ) xmalloc ( sizeof * c ) ; c -> value = val ; c -> label = gen_label_rtx ( ) ; c -> next = pool -> constants [ i ] ; pool -> constants [ i ] = c ; pool -> size += GET_MODE_SIZE ( mode ) ; } } </s>

Add constant VAL of mode MODE to the constant pool POOL .


<s> bool avr_popcount_each_byte ( rtx xval , int n_bytes , int pop_mask ) { int i ; machine_mode mode = GET_MODE ( xval ) ; if ( VOIDmode == mode ) mode = SImode ; for ( i = 0 ; i < n_bytes ; i ++ ) { rtx xval8 = simplify_gen_subreg ( QImode , xval , mode , i ) ; unsigned int val8 = UINTVAL ( xval8 ) & GET_MODE_MASK ( QImode ) ; if ( 0 == ( pop_mask & ( 1 << avr_popcount ( val8 ) ) ) ) return false ; } return true ; } </s>

Constraint helper function . XVAL is a CONST_INT or a CONST_DOUBLE . Return true if the least significant N_BYTES bytes of XVAL all have a popcount in POP_MASK and false , otherwise . POP_MASK represents a subset of integers which contains an integer N iff bit N of POP_MASK is set .


<s> TargetLowering :: AtomicExpansionKind AArch64TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { unsigned Size = LI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size != 128 || isOpSuitableForLDPSTP ( LI ) ) return AtomicExpansionKind :: None ; if ( getTargetMachine ( ) . getOptLevel ( ) == CodeGenOpt :: None ) return AtomicExpansionKind :: CmpXChg ; return AtomicExpansionKind :: LLSC ; } </s>

Returns how the given ( atomic ) load should be expanded by the IR-level AtomicExpand pass .


<s> unsigned X86FrameLowering :: getWinEHFuncletFrameSize ( const MachineFunction & MF ) const { const X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned CSSize = X86FI -> getCalleeSavedFrameSize ( ) ; const auto & WinEHXMMSlotInfo = X86FI -> getWinEHXMMSlotInfo ( ) ; unsigned XMMSize = WinEHXMMSlotInfo . size ( ) * TRI -> getSpillSize ( X86 :: VR128RegClass ) ; unsigned UsedSize ; EHPersonality Personality = classifyEHPersonality ( MF . getFunction ( ) . getPersonalityFn ( ) ) ; if ( Personality == EHPersonality :: CoreCLR ) { UsedSize = getPSPSlotOffsetFromSP ( MF ) + SlotSize ; } else { UsedSize = MF . getFrameInfo ( ) . getMaxCallFrameSize ( ) ; } unsigned FrameSizeMinusRBP = alignTo ( CSSize + UsedSize , getStackAlignment ( ) ) ; return FrameSizeMinusRBP + XMMSize - CSSize ; } </s>

Funclets only need to account for space for the callee saved registers , as the locals are accounted for in the parent 's stack frame .


<s> unsigned PPCInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case PPC :: STD : case PPC :: STW : case PPC :: STFS : case PPC :: STFD : case PPC :: SPILL_CR : case PPC :: SPILL_CRBIT : case PPC :: STVX : case PPC :: STXVD2X : case PPC :: SPILL_VRSAVE : if ( MI -> getOperand ( 1 ) . isImm ( ) && ! MI -> getOperand ( 1 ) . getImm ( ) && MI -> getOperand ( 2 ) . isFI ( ) ) { FrameIndex = MI -> getOperand ( 2 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s>
SDValue
OpenRISCTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_OpenRISC
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
if
(
RVLocs
[
i
]
.
isRegLoc
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
unsigned
Opc
=
OpenRISCISD
::
RET_FLAG
;
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
Opc
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
return
DAG
.
getNode
(
Opc
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool R600InstrInfo :: isPredicated ( const MachineInstr & MI ) const { int idx = MI . findFirstPredOperandIdx ( ) ; if ( idx < 0 ) return false ; unsigned Reg = MI . getOperand ( idx ) . getReg ( ) ; switch ( Reg ) { default : return false ; case R600 :: PRED_SEL_ONE : case R600 :: PRED_SEL_ZERO : case R600 :: PREDICATE_BIT : return true ; } } </s>

Returns true if the instruction is already predicated .


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const PPCFrameLowering * PPCFI = static_cast < const PPCFrameLowering * > ( MF . getTarget ( ) . getFrameLowering ( ) ) ; Reserved . set ( PPC :: ZERO ) ; Reserved . set ( PPC :: ZERO8 ) ; Reserved . set ( PPC :: FP ) ; Reserved . set ( PPC :: FP8 ) ; Reserved . set ( PPC :: BP ) ; Reserved . set ( PPC :: BP8 ) ; Reserved . set ( PPC :: CTR ) ; Reserved . set ( PPC :: CTR8 ) ; Reserved . set ( PPC :: R1 ) ; Reserved . set ( PPC :: LR ) ; Reserved . set ( PPC :: LR8 ) ; Reserved . set ( PPC :: RM ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) Reserved . set ( PPC :: VRSAVE ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: R2 ) ; Reserved . set ( PPC :: R13 ) ; } if ( Subtarget . isPPC64 ( ) ) { Reserved . set ( PPC :: R13 ) ; Reserved . set ( PPC :: X1 ) ; Reserved . set ( PPC :: X13 ) ; if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: X31 ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( PPC :: X30 ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: X2 ) ; } } if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: R31 ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( PPC :: R30 ) ; if ( ! Subtarget . hasAltivec ( ) ) for ( TargetRegisterClass :: iterator I = PPC :: VRRCRegClass . begin ( ) , IE = PPC :: VRRCRegClass . end ( ) ; I != IE ; ++ I ) Reserved . set ( * I ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


Make function pointers for the various linear operators we can apply to compute a multiplicative value .


<s> bool LanaiAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] ) return true ; switch ( ExtraCode [ 0 ] ) { case 'H' : { if ( OpNo == 0 ) return true ; const MachineOperand & FlagsOP = MI -> getOperand ( OpNo - 1 ) ; if ( ! FlagsOP . isImm ( ) ) return true ; unsigned Flags = FlagsOP . getImm ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; if ( NumVals != 2 ) return true ; unsigned RegOp = OpNo + 1 ; if ( RegOp >= MI -> getNumOperands ( ) ) return true ; const MachineOperand & MO = MI -> getOperand ( RegOp ) ; if ( ! MO . isReg ( ) ) return true ; Register Reg = MO . getReg ( ) ; O << LanaiInstPrinter :: getRegisterName ( Reg ) ; return false ; } default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , O ) ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> bool PULPHardwareLoops :: isDead ( const MachineInstr * MI , SmallVectorImpl < MachineInstr * > & DeadPhis ) const { for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( MRI -> use_nodbg_empty ( Reg ) ) continue ; using use_nodbg_iterator = MachineRegisterInfo :: use_nodbg_iterator ; use_nodbg_iterator I = MRI -> use_nodbg_begin ( Reg ) ; use_nodbg_iterator End = MRI -> use_nodbg_end ( ) ; if ( std :: next ( I ) != End || ! I -> getParent ( ) -> isPHI ( ) ) return false ; MachineInstr * OnePhi = I -> getParent ( ) ; for ( unsigned j = 0 , f = OnePhi -> getNumOperands ( ) ; j != f ; ++ j ) { const MachineOperand & OPO = OnePhi -> getOperand ( j ) ; if ( ! OPO . isReg ( ) || ! OPO . isDef ( ) ) continue ; unsigned OPReg = OPO . getReg ( ) ; use_nodbg_iterator nextJ ; for ( use_nodbg_iterator J = MRI -> use_nodbg_begin ( OPReg ) ; J != End ; J = nextJ ) { nextJ = std :: next ( J ) ; MachineOperand & Use = * J ; MachineInstr * UseMI = Use . getParent ( ) ; if ( MI != UseMI ) return false ; } } DeadPhis . push_back ( OnePhi ) ; } return true ; } </s>

isDead - Returns true if this is a dead def kill slot .


<s>
static
void
s390_asm_file_end
(
void
)
{
varpool_node
*
vnode
;
cgraph_node
*
cnode
;
FOR_EACH_VARIABLE
(
vnode
)
if
(
TREE_PUBLIC
(
vnode
->
decl
)
)
s390_check_type_for_vector_abi
(
TREE_TYPE
(
vnode
->
decl
)
,
false
,
false
)
;
FOR_EACH_FUNCTION
(
cnode
)
if
(
TREE_PUBLIC
(
cnode
->
decl
)
)
s390_check_type_for_vector_abi
(
TREE_TYPE
(
cnode
->
decl
)
,
false
,
false
)
;
if
(
s390_vector_abi
!=
0
)
fprintf
(
asm_out_file
,
"\t.gnu_attribute 8, %d\n"
,
s390_vector_abi
)
;
file_end_indicate_exec_stack
(
)
;
if
(
flag_split_stack
)
file_end_indicate_split_stack
(
)
;
}
</s>


<s> SMLoc getStartLoc ( ) const { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> bool X86TargetLowering :: isVectorClearMaskLegal ( const SmallVectorImpl < int > & Mask , EVT VT ) const { unsigned NumElts = VT . getVectorNumElements ( ) ; if ( NumElts == 2 ) return true ; if ( NumElts == 4 && VT . is128BitVector ( ) ) { return ( isMOVLMask ( Mask , VT ) || isCommutedMOVLMask ( Mask , VT , true ) || isSHUFPMask ( Mask , VT , Subtarget -> hasFp256 ( ) ) || isSHUFPMask ( Mask , VT , Subtarget -> hasFp256 ( ) , true ) ) ; } return false ; } </s>


<s> int SystemZTTIImpl :: getIntrinsicInstrCost ( Intrinsic :: ID ID , Type * RetTy , ArrayRef < Type * > Tys , FastMathFlags FMF , unsigned ScalarizationCostPassed ) { int Cost = getVectorIntrinsicInstrCost ( ID , RetTy ) ; if ( Cost != - 1 ) return Cost ; return BaseT :: getIntrinsicInstrCost ( ID , RetTy , Tys , FMF , ScalarizationCostPassed ) ; } </s>


<s> static void init_insn_group_barriers ( void ) { memset ( rws_sum , 0 , sizeof ( rws_sum ) ) ; first_instruction = 1 ; } </s>

Clear out the state for group_barrier_needed_p at the start of a sequence of insns .


<s> static void c6x_set_sched_context ( void * _sc ) { c6x_sched_context_t sc = ( c6x_sched_context_t ) _sc ; gcc_assert ( sc != NULL ) ; ss = * sc ; memcpy ( prev_cycle_state , sc -> prev_cycle_state_ctx , dfa_state_size ) ; } </s>

Sets the global scheduling context to the one pointed to by _SC .


<s> static inline _uw selfrel_offset31 ( const _uw * p ) { _uw offset ; offset = * p ; if ( offset & ( 1 << 30 ) ) offset |= 1u << 31 ; return offset + ( _uw ) p ; } </s>

Calculate the address encoded by a 31-bit self-relative offset at address P .


<s> static void mips_set_architecture ( const struct mips_cpu_info * info ) { if ( info != 0 ) { mips_arch_info = info ; mips_arch = info -> cpu ; mips_isa = info -> isa ; if ( mips_isa < MIPS_ISA_MIPS32 ) mips_isa_rev = 0 ; else mips_isa_rev = ( mips_isa & 31 ) + 1 ; } } </s>

Set up globals to generate code for the ISA or processor described by INFO .


<s> poly_uint64 aarch64_regmode_natural_size ( machine_mode mode ) { if ( ! aarch64_sve_vg . is_constant ( ) ) { unsigned int vec_flags = aarch64_classify_vector_mode ( mode ) ; if ( vec_flags & VEC_SVE_PRED ) return BYTES_PER_SVE_PRED ; if ( vec_flags & VEC_SVE_DATA ) return BYTES_PER_SVE_VECTOR ; } return UNITS_PER_WORD ; } </s>