<s> static Matcher < V > Create ( const char * name , F func ) { static_assert ( NoOverlap < u16 , expected , OperandAtT :: Mask ... > , "Error" ) ; Proxy < typename FilterOperand < OperandAtT ... > :: result > proxy { func } ; constexpr u16 mask = ( ~ OperandAtT :: Mask & ... & 0xFFFF ) ; constexpr bool expanded = ( OperandAtT :: NeedExpansion || ... ) ; return Matcher < V > ( name , mask , expected , expanded , proxy ) ; } </s>

Construct a unary instruction , given the opcode and an operand .


<s> bool Mips16DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & TM . getSubtarget < MipsSubtarget > ( ) ; if ( ! Subtarget -> inMips16Mode ( ) ) return false ; return MipsDAGToDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> static section * mips_function_rodata_section ( tree decl , bool ) { if ( ! TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD ) return default_function_rodata_section ( decl , false ) ; if ( decl && DECL_SECTION_NAME ( decl ) ) { const char * name = DECL_SECTION_NAME ( decl ) ; if ( DECL_COMDAT_GROUP ( decl ) && strncmp ( name , ".gnu.linkonce.t." , 16 ) == 0 ) { char * rname = ASTRDUP ( name ) ; rname [ 14 ] = 'd' ; return get_section ( rname , SECTION_LINKONCE | SECTION_WRITE , decl ) ; } else if ( flag_function_sections && flag_data_sections && strncmp ( name , ".text." , 6 ) == 0 ) { char * rname = ASTRDUP ( name ) ; memcpy ( rname + 1 , "data" , 4 ) ; return get_section ( rname , SECTION_WRITE , decl ) ; } } return data_section ; } </s>

Implement TARGET_ASM_FUNCTION_RODATA_SECTION . The complication here is that , with the combination TARGET_ABICALLS & & ! TARGET_GPWORD , jump tables will use absolute addresses , and should therefore not be included in the read-only part of a DSO . Handle such cases by selecting a normal data section instead of a read-only one . The logic apes that in default_function_rodata_section .


<s> bool lm32_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { return ( to == STACK_POINTER_REGNUM && frame_pointer_needed ) ? false : true ; } </s>


<s> const HSAILRegisterInfo * getRegisterInfo ( ) const override { return & getInstrInfo ( ) -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
void
BTFDebug
::
beginFunctionImpl
(
const
MachineFunction
*
MF
)
{
auto
*
SP
=
MF
->
getFunction
(
)
.
getSubprogram
(
)
;
auto
*
Unit
=
SP
->
getUnit
(
)
;
if
(
Unit
->
getEmissionKind
(
)
==
DICompileUnit
::
NoDebug
)
{
SkipInstruction
=
true
;
return
;
}
SkipInstruction
=
false
;
std
::
unordered_map
<
uint32_t
,
StringRef
>
FuncArgNames
;
for
(
const
DINode
*
DN
:
SP
->
getRetainedNodes
(
)
)
{
if
(
const
auto
*
DV
=
dyn_cast
<
DILocalVariable
>
(
DN
)
)
{
uint32_t
Arg
=
DV
->
getArg
(
)
;
if
(
Arg
)
{
visitTypeEntry
(
DV
->
getType
(
)
.
resolve
(
)
)
;
FuncArgNames
[
Arg
]
=
DV
->
getName
(
)
;
}
}
}
uint32_t
ProtoTypeId
;
visitSubroutineType
(
SP
->
getType
(
)
,
true
,
FuncArgNames
,
ProtoTypeId
)
;
auto
FuncTypeEntry
=
llvm
::
make_unique
<
BTFTypeFunc
>
(
SP
->
getName
(
)
,
ProtoTypeId
)
;
uint32_t
FuncTypeId
=
addType
(
std
::
move
(
FuncTypeEntry
)
)
;
MCSymbol
*
FuncLabel
=
Asm
->
getFunctionBegin
(
)
;
BTFFuncInfo
FuncInfo
;
FuncInfo
.
Label
=
FuncLabel
;
FuncInfo
.
TypeId
=
FuncTypeId
;
if
(
FuncLabel
->
isInSection
(
)
)
{
MCSection
&
Section
=
FuncLabel
->
getSection
(
)
;
const
MCSectionELF
*
SectionELF
=
dyn_cast
<
MCSectionELF
>
(
&
Section
)
;
assert
(
SectionELF
&&
"Null section for Function Label"
)
;
SecNameOff
=
addString
(
SectionELF
->
getSectionName
(
)
)
;
}
else
{
SecNameOff
=
addString
(
".text"
)
;
}
FuncInfoTable
[
SecNameOff
]
.
push_back
(
FuncInfo
)
;
}
</s>

BPF
"Null section for Function Label"
".text"


<s> bool PPCTTIImpl :: enableInterleavedAccessVectorization ( ) { return true ; } </s>

Enable matching of interleaved access groups .


<s> int ix86_issue_rate ( void ) { switch ( ix86_tune ) { case PROCESSOR_PENTIUM : case PROCESSOR_LAKEMONT : case PROCESSOR_BONNELL : case PROCESSOR_SILVERMONT : case PROCESSOR_KNL : case PROCESSOR_KNM : case PROCESSOR_INTEL : case PROCESSOR_K6 : case PROCESSOR_BTVER2 : case PROCESSOR_PENTIUM4 : case PROCESSOR_NOCONA : return 2 ; case PROCESSOR_PENTIUMPRO : case PROCESSOR_ATHLON : case PROCESSOR_K8 : case PROCESSOR_AMDFAM10 : case PROCESSOR_BTVER1 : return 3 ; case PROCESSOR_BDVER1 : case PROCESSOR_BDVER2 : case PROCESSOR_BDVER3 : case PROCESSOR_BDVER4 : case PROCESSOR_ZNVER1 : case PROCESSOR_CORE2 : case PROCESSOR_NEHALEM : case PROCESSOR_SANDYBRIDGE : case PROCESSOR_HASWELL : case PROCESSOR_GENERIC : return 4 ; default : return 1 ; } } </s>

Return the maximum number of instructions a cpu can issue .


<s> static bool rs6000_legitimate_combined_insn ( rtx_insn * insn ) { int icode = INSN_CODE ( insn ) ; if ( icode != CODE_FOR_nothing && ( icode == CODE_FOR_ctrsi_internal1 || icode == CODE_FOR_ctrdi_internal1 || icode == CODE_FOR_ctrsi_internal2 || icode == CODE_FOR_ctrdi_internal2 || icode == CODE_FOR_ctrsi_internal3 || icode == CODE_FOR_ctrdi_internal3 || icode == CODE_FOR_ctrsi_internal4 || icode == CODE_FOR_ctrdi_internal4 ) ) return false ; return true ; } </s>

Implement the TARGET_LEGITIMATE_COMBINED_INSN hook .


"ISelDAG: Can't lower variadic arguments\n"

"Doesn't support custom argument lowering"

"ISelDAG: Too many arguments passed to function\n"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


"insertBranch must not be told to insert a fallthrough"

"SHUXI branch conditions have one component!"

"Unconditional branch with multiple successors!"

Insert branch code into the end of the specified MachineBasicBlock .


"%<-mno-mpy%> supported only for ARC700 or ARCv2"

"%<-mno-dpfp-lrsr%> supported only with %<-mdpfp%>"

"FPX fast and compact options cannot be specified together"

"%<-mspfp_fast%> not available on ARC600 or ARC601"

Called by OVERRIDE_OPTIONS to initialize various things .


<s>
void
assignValueToAddress
(
Register
ValVReg
,
Register
Addr
,
LLT
MemTy
,
MachinePointerInfo
&
MPO
,
CCValAssign
&
VA
)
override
{
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
SExt
||
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExt
)
{
MemTy
=
LLT
::
scalar
(
32
)
;
assert
(
MRI
.
getType
(
ValVReg
)
.
isScalar
(
)
&&
"Only scalars supported atm"
)
;
auto
LoadVReg
=
buildLoad
(
LLT
::
scalar
(
32
)
,
Addr
,
MemTy
,
MPO
)
;
MIRBuilder
.
buildTrunc
(
ValVReg
,
LoadVReg
)
;
}
else
{
buildLoad
(
ValVReg
,
Addr
,
MemTy
,
MPO
)
;
}
}
</s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> void X86AsmParser :: EmitInstruction ( MCInst & Inst , OperandVector & Operands , MCStreamer & Out ) { Instrumentation -> InstrumentAndEmitInstruction ( Inst , Operands , getContext ( ) , MII , Out ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> const AArch64TargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


<s> static rtx mark_constant_pool_use ( rtx x ) { if ( x == NULL_RTX ) return x ; switch ( GET_CODE ( x ) ) { case LABEL_REF : x = XEXP ( x , 0 ) ; case CODE_LABEL : break ; default : return x ; } rtx_insn * lab = as_a < rtx_insn * > ( x ) ; for ( rtx_insn * insn = PREV_INSN ( lab ) ; insn ; insn = PREV_INSN ( insn ) ) { if ( ! LABEL_P ( insn ) || LABEL_REFS ( insn ) != NEXT_INSN ( insn ) ) break ; lab = insn ; } for ( rtx insn = LABEL_REFS ( lab ) ; insn ; insn = LABEL_REFS ( insn ) ) as_a < rtx_insn * > ( insn ) -> set_deleted ( ) ; for ( rtx_insn * insn = NEXT_INSN ( as_a < rtx_insn * > ( x ) ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( ! NONJUMP_INSN_P ( insn ) ) continue ; rtx pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) != UNSPEC_VOLATILE ) continue ; switch ( XINT ( pattern , 1 ) ) { case UNSPECV_CONST2 : case UNSPECV_CONST4 : case UNSPECV_CONST8 : XVECEXP ( pattern , 0 , 1 ) = const1_rtx ; break ; case UNSPECV_WINDOW_END : if ( XVECEXP ( pattern , 0 , 0 ) == x ) return lab ; break ; case UNSPECV_CONST_END : return lab ; default : break ; } } return lab ; } </s>

Mark the use of a constant in the literal table . If the constant has multiple labels , make it unique .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addRequired < EdgeBundles > ( ) ; AU . addPreservedID ( MachineLoopInfoID ) ; AU . addPreservedID ( MachineDominatorsID ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> AArch64Subtarget :: AArch64Subtarget ( StringRef TT , StringRef CPU , StringRef FS , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasFPARMv8 ( false ) , HasNEON ( false ) , HasCrypto ( false ) , TargetTriple ( TT ) , CPUString ( CPU ) , IsLittleEndian ( LittleEndian ) { initializeSubtargetFeatures ( CPU , FS ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


"********** Replace Physical Registers **********\n"

"LiveIntervals shouldn't be active yet!"


"switch -mcpu=%s conflicts with -march=%s switch"

"Assembler does not support -mabi=ilp32"


<s> MVT :: SimpleValueType getCmpLibcallReturnType ( ) const override { return MVT :: i16 ; } </s>

Return the ValueType for comparison libcalls .


<s> MVT RISCVTargetLowering :: getPointerMemTy ( const DataLayout & DL , uint32_t AS ) const { if ( AS == UINT32_MAX ) { AS = 0 ; } return MVT :: getIntegerVT ( DL . getPointerSizeInBits ( AS ) ) ; } </s>

Return the in-memory pointer type for the given address space , defaults to the pointer type from the data layout .


"Wrong register class for memory operand."

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


"WebAssembly Replace Physical Registers"

getPassName - Return a nice clean name for a pass .


<s> const RAInfo :: LocType & getType ( ) const { return type ; } </s>

Overload to return most specific vector type .


<s> static void ix86_emit_save_regs_using_mov ( rtx pointer , HOST_WIDE_INT offset ) { unsigned int regno ; rtx insn ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ix86_save_reg ( regno , true ) ) { insn = emit_move_insn ( adjust_address ( gen_rtx_MEM ( Pmode , pointer ) , Pmode , offset ) , gen_rtx_REG ( Pmode , regno ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; offset += UNITS_PER_WORD ; } } </s>

Emit code to save registers using MOV insns . First register is restored from POINTER + OFFSET .


"instruction requires a WASM feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


"Cannot store this register to stack slot!"

Load the specified register of the given register class from the specified stack frame index .


"FP elimination on a non-leaf function is not supported"

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s>
void
NVPTXFrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
if
(
MF
.
getFrameInfo
(
)
.
hasStackObjects
(
)
)
{
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineInstr
*
MI
=
&
MBB
.
front
(
)
;
MachineRegisterInfo
&
MR
=
MF
.
getRegInfo
(
)
;
DebugLoc
dl
=
DebugLoc
(
)
;
bool
Is64Bit
=
static_cast
<
const
NVPTXTargetMachine
&
>
(
MF
.
getTarget
(
)
)
.
is64Bit
(
)
;
unsigned
CvtaLocalOpcode
=
(
Is64Bit
NVPTX
::
cvta_local_yes_64
:
NVPTX
::
cvta_local_yes
)
;
unsigned
MovDepotOpcode
=
(
Is64Bit
NVPTX
::
MOV_DEPOT_ADDR_64
:
NVPTX
::
MOV_DEPOT_ADDR
)
;
if
(
!
MR
.
use_empty
(
NVPTX
::
VRFrame
)
)
{
MI
=
BuildMI
(
MBB
,
MI
,
dl
,
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
->
get
(
CvtaLocalOpcode
)
,
NVPTX
::
VRFrame
)
.
addReg
(
NVPTX
::
VRFrameLocal
)
;
}
BuildMI
(
MBB
,
MI
,
dl
,
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
->
get
(
MovDepotOpcode
)
,
NVPTX
::
VRFrameLocal
)
.
addImm
(
MF
.
getFunctionNumber
(
)
)
;
}
}
</s>

NVPTX
NVPTX
"Shrink-wrapping not yet supported"
NVPTX
NVPTX::cvta_local_yes_64
NVPTX::cvta_local_yes
NVPTX::MOV_DEPOT_ADDR_64
NVPTX::MOV_DEPOT_ADDR
NVPTX::VRFrame
NVPTX::VRFrame
NVPTX::VRFrameLocal
NVPTX::VRFrameLocal


<s> SDValue AMDGPUTargetLowering :: CreateLiveInRegister ( SelectionDAG & DAG , const TargetRegisterClass * RC , unsigned Reg , EVT VT ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned VirtualRegister ; if ( ! MRI . isLiveIn ( Reg ) ) { VirtualRegister = MRI . createVirtualRegister ( RC ) ; MRI . addLiveIn ( Reg , VirtualRegister ) ; } else { VirtualRegister = MRI . getLiveInVirtReg ( Reg ) ; } return DAG . getRegister ( VirtualRegister , VT ) ; } </s>

Helper function that adds Reg to the LiveIn list of the DAG 's MachineFunction .


<s> static int vax_address_cost_1 ( rtx addr ) { int reg = 0 , indexed = 0 , indir = 0 , offset = 0 , predec = 0 ; rtx plus_op0 = 0 , plus_op1 = 0 ; restart : switch ( GET_CODE ( addr ) ) { case PRE_DEC : predec = 1 ; case REG : case SUBREG : case POST_INC : reg = 1 ; break ; case MULT : case ASHIFT : indexed = 1 ; break ; case CONST_INT : if ( offset == 0 ) offset = ( unsigned HOST_WIDE_INT ) ( INTVAL ( addr ) + 128 ) > 256 ; break ; case CONST : case SYMBOL_REF : offset = 1 ; break ; case LABEL_REF : if ( offset == 0 ) offset = 1 ; break ; case PLUS : if ( plus_op0 ) plus_op1 = XEXP ( addr , 0 ) ; else plus_op0 = XEXP ( addr , 0 ) ; addr = XEXP ( addr , 1 ) ; goto restart ; case MEM : indir = 2 ; addr = XEXP ( addr , 0 ) ; goto restart ; default : break ; } if ( plus_op0 ) { addr = plus_op0 ; plus_op0 = 0 ; goto restart ; } if ( plus_op1 ) { addr = plus_op1 ; plus_op1 = 0 ; goto restart ; } if ( reg && indexed && offset ) return reg + indir + offset + predec ; return reg + indexed + indir + offset + predec ; } </s>

Return the cost in cycles of a memory address , relative to register indirect . Each of the following adds the indicated number of cycles : 1 - symbolic address 1 - pre-decrement 1 - indexing and/or offset ( register ) 2 - indirect


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { AArch64FunctionInfo * AFI = MF . getInfo < AArch64FunctionInfo > ( ) ; if ( AFI -> getNumLocalDynamicTLSAccesses ( ) < 2 ) { return false ; } MachineDominatorTree * DT = & getAnalysis < MachineDominatorTree > ( ) ; return VisitNode ( DT -> getRootNode ( ) , 0 ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> void XCoreMCInstLower :: Initialize ( Mangler * M , MCContext * C ) { Mang = M ; Ctx = C ; } </s>

This method must be called before any actual lowering is done .


<s> const PPCMCExpr * PPCMCExpr :: create ( VariantKind Kind , const MCExpr * Expr , bool IsDarwin , MCContext & Ctx ) { return new ( Ctx ) PPCMCExpr ( Kind , Expr , IsDarwin ) ; } </s>


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { bool HasAVX = TM . getSubtarget < X86Subtarget > ( ) . hasAVX ( ) ; bool HasAVX512 = TM . getSubtarget < X86Subtarget > ( ) . hasAVX512 ( ) ; if ( CC == CallingConv :: Intel_OCL_BI ) { if ( IsWin64 && HasAVX512 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( Is64Bit && HasAVX512 ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( IsWin64 && HasAVX ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( Is64Bit && HasAVX ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; } if ( CC == CallingConv :: GHC || CC == CallingConv :: HiPE ) return CSR_NoRegs_RegMask ; if ( ! Is64Bit ) return CSR_32_RegMask ; if ( CC == CallingConv :: Cold ) return CSR_MostRegs_64_RegMask ; if ( IsWin64 ) return CSR_Win64_RegMask ; return CSR_64_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool X86TargetLowering :: needsFixedCatchObjects ( ) const { return Subtarget . isTargetWin64 ( ) ; } </s>


<s> bool aarch64_float_const_zero_rtx_p ( rtx x ) { if ( GET_MODE ( x ) == VOIDmode ) return false ; if ( REAL_VALUE_MINUS_ZERO ( * CONST_DOUBLE_REAL_VALUE ( x ) ) ) return ! HONOR_SIGNED_ZEROS ( GET_MODE ( x ) ) ; return real_equal ( CONST_DOUBLE_REAL_VALUE ( x ) , & dconst0 ) ; } </s>

Return TRUE if rtx X is immediate constant 0.0


<s> void SIInstrInfo :: legalizeOpWithMove ( MachineInstr * MI , unsigned OpIdx ) const { MachineBasicBlock :: iterator I = MI ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineOperand & MO = MI -> getOperand ( OpIdx ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; unsigned RCID = get ( MI -> getOpcode ( ) ) . OpInfo [ OpIdx ] . RegClass ; const TargetRegisterClass * RC = RI . getRegClass ( RCID ) ; unsigned Opcode = AMDGPU :: V_MOV_B32_e32 ; if ( MO . isReg ( ) ) Opcode = AMDGPU :: COPY ; else if ( RI . isSGPRClass ( RC ) ) Opcode = AMDGPU :: S_MOV_B32 ; const TargetRegisterClass * VRC = RI . getEquivalentVGPRClass ( RC ) ; if ( RI . getCommonSubClass ( & AMDGPU :: VReg_64RegClass , VRC ) ) VRC = & AMDGPU :: VReg_64RegClass ; else VRC = & AMDGPU :: VGPR_32RegClass ; unsigned Reg = MRI . createVirtualRegister ( VRC ) ; DebugLoc DL = MBB -> findDebugLoc ( I ) ; BuildMI ( * MI -> getParent ( ) , I , DL , get ( Opcode ) , Reg ) . addOperand ( MO ) ; MO . ChangeToRegister ( Reg , false ) ; } </s>

Legalize the OpIndex operand of this instruction by inserting a MOV .


<s> unsigned MipsFunctionInfo :: getGlobalBaseReg ( ) { if ( GlobalBaseReg ) return GlobalBaseReg ; const TargetRegisterClass * RC = static_cast < const MipsSubtarget & > ( MF . getSubtarget ( ) ) . inMips16Mode ( ) ? & Mips :: CPU16RegsRegClass : static_cast < const MipsTargetMachine & > ( MF . getTarget ( ) ) . getABI ( ) . IsN64 ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; return GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> const BasicBlock * getBasicBlock ( ) { return BB ; } </s>

Return the LLVM basic block that this instance corresponded to originally .


<s> void PPCPassConfig :: addIRPasses ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCBoolRetToIntPass ( ) ) ; addPass ( createAtomicExpandPass ( & getPPCTargetMachine ( ) ) ) ; bool UsePrefetching = TM -> getTargetTriple ( ) . getVendor ( ) == Triple :: BGQ && getOptLevel ( ) != CodeGenOpt :: None ; if ( EnablePrefetch . getNumOccurrences ( ) > 0 ) UsePrefetching = EnablePrefetch ; if ( UsePrefetching ) addPass ( createPPCLoopDataPrefetchPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static bool nvptx_legitimate_address_p ( machine_mode , rtx x , bool ) { enum rtx_code code = GET_CODE ( x ) ; switch ( code ) { case REG : return true ; case PLUS : if ( REG_P ( XEXP ( x , 0 ) ) && CONST_INT_P ( XEXP ( x , 1 ) ) ) return true ; return false ; case CONST : case SYMBOL_REF : case LABEL_REF : return true ; default : return false ; } } </s>

Returns true if X is a valid address for use in a memory reference .


<s> bool AMDGPUCodeGenPrepare :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; const AMDGPUTargetMachine & TM = TPC -> getTM < AMDGPUTargetMachine > ( ) ; ST = & TM . getSubtarget < GCNSubtarget > ( F ) ; AC = & getAnalysis < AssumptionCacheTracker > ( ) . getAssumptionCache ( F ) ; DA = & getAnalysis < LegacyDivergenceAnalysis > ( ) ; HasUnsafeFPMath = hasUnsafeFPMath ( F ) ; bool MadeChange = false ; for ( BasicBlock & BB : F ) { BasicBlock :: iterator Next ; for ( BasicBlock :: iterator I = BB . begin ( ) , E = BB . end ( ) ; I != E ; I = Next ) { Next = std :: next ( I ) ; MadeChange |= visit ( * I ) ; } } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s>
bool
MipsAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
DEBUG
(
dbgs
(
)
<<
"ParseInstruction\n"
)
;
getTargetStreamer
(
)
.
forbidModuleDirective
(
)
;
if
(
!
mnemonicIsValid
(
Name
,
0
)
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
NameLoc
,
"unknown instruction"
)
;
}
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Name
,
NameLoc
,
*
this
)
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
parseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
&&
parseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
)
{
if
(
parseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
}
else
if
(
getLexer
(
)
.
is
(
AsmToken
::
LParen
)
&&
parseParenSuffix
(
Name
,
Operands
)
)
return
true
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Mips
Mips
"ParseInstruction\n"
0
"unknown instruction"
MipsOperand::CreateToken
"unexpected token in argument list"
"unexpected token in argument list"
"unexpected token in argument list"


<s> static bool ix86_fixed_condition_code_regs ( unsigned int * p1 , unsigned int * p2 ) { * p1 = FLAGS_REG ; * p2 = INVALID_REGNUM ; return true ; } </s>

Return the fixed registers used for condition codes .


"Function has local memory argument.  Promoting to "


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
Nyuzi
::
NumTargetFixupKinds
]
=
{
{
"fixup_Nyuzi_Branch20"
,
5
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_Nyuzi_Branch25"
,
0
,
25
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_Nyuzi_HI19"
,
0
,
32
,
0
}
,
{
"fixup_Nyuzi_IMM_LO13"
,
10
,
13
,
0
}
,
{
"fixup_Nyuzi_GOT"
,
10
,
15
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS , bool is64bit ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS , is64bit ) , DataLayout ( Subtarget . getDataLayout ( ) ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrInfo ( Subtarget ) , FrameInfo ( TargetFrameInfo :: StackGrowsDown , 8 , 0 ) { } </s>


<s> rtx frv_split_minmax ( rtx operands [ ] ) { rtx dest = operands [ 0 ] ; rtx minmax = operands [ 1 ] ; rtx src1 = operands [ 2 ] ; rtx src2 = operands [ 3 ] ; rtx cc_reg = operands [ 4 ] ; rtx cr_reg = operands [ 5 ] ; rtx ret ; enum rtx_code test_code ; machine_mode cr_mode = GET_MODE ( cr_reg ) ; start_sequence ( ) ; switch ( GET_CODE ( minmax ) ) { default : gcc_unreachable ( ) ; case SMIN : test_code = LT ; break ; case SMAX : test_code = GT ; break ; case UMIN : test_code = LTU ; break ; case UMAX : test_code = GTU ; break ; } emit_insn ( gen_rtx_SET ( VOIDmode , cc_reg , gen_rtx_COMPARE ( GET_MODE ( cc_reg ) , src1 , src2 ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cr_reg , gen_rtx_fmt_ee ( test_code , GET_MODE ( cr_reg ) , cc_reg , const0_rtx ) ) ) ; if ( GET_CODE ( src2 ) == CONST_INT && INTVAL ( src2 ) != 0 ) { gcc_assert ( ! rtx_equal_p ( dest , src1 ) ) ; emit_move_insn ( dest , src2 ) ; emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_NE ( cr_mode , cr_reg , const0_rtx ) , gen_rtx_SET ( VOIDmode , dest , src1 ) ) ) ; } else { if ( ! rtx_equal_p ( dest , src1 ) ) emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_NE ( cr_mode , cr_reg , const0_rtx ) , gen_rtx_SET ( VOIDmode , dest , src1 ) ) ) ; if ( ! rtx_equal_p ( dest , src2 ) ) emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_EQ ( cr_mode , cr_reg , const0_rtx ) , gen_rtx_SET ( VOIDmode , dest , src2 ) ) ) ; } ret = get_insns ( ) ; end_sequence ( ) ; return ret ; } </s>

Split a min/max operation returning a SEQUENCE containing all of the insns .


This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly


<s> static tree sh_builtin_decl ( unsigned code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= ARRAY_SIZE ( bdesc ) ) return error_mark_node ; if ( ! bdesc [ code ] . is_enabled ( ) ) return error_mark_node ; return bdesc [ code ] . fndecl ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"AMDGPU Lower Intrinsics"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool ARMTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned Alignment , MachineMemOperand :: Flags , bool * Fast ) const { if ( ! VT . isSimple ( ) ) return false ; bool AllowsUnaligned = Subtarget -> allowsUnalignedMem ( ) ; auto Ty = VT . getSimpleVT ( ) . SimpleTy ; if ( Ty == MVT :: i8 || Ty == MVT :: i16 || Ty == MVT :: i32 ) { if ( AllowsUnaligned ) { if ( Fast ) * Fast = Subtarget -> hasV7Ops ( ) ; return true ; } } if ( Ty == MVT :: f64 || Ty == MVT :: v2f64 ) { if ( Subtarget -> hasNEON ( ) && ( AllowsUnaligned || Subtarget -> isLittle ( ) ) ) { if ( Fast ) * Fast = true ; return true ; } } if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; if ( ( Ty == MVT :: v16i1 || Ty == MVT :: v8i1 || Ty == MVT :: v4i1 ) ) { if ( Fast ) * Fast = true ; return true ; } if ( ( Ty == MVT :: v4i8 || Ty == MVT :: v8i8 || Ty == MVT :: v4i16 ) && Alignment >= VT . getScalarSizeInBits ( ) / 8 ) { if ( Fast ) * Fast = true ; return true ; } if ( Ty == MVT :: v16i8 || Ty == MVT :: v8i16 || Ty == MVT :: v8f16 || Ty == MVT :: v4i32 || Ty == MVT :: v4f32 || Ty == MVT :: v2i64 || Ty == MVT :: v2f64 ) { if ( Fast ) * Fast = true ; return true ; } return false ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addRequired < LegacyDivergenceAnalysis > ( ) ; AU . addRequired < TargetPassConfig > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void SIInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; SIMachineFunctionInfo * MFI = MF -> getInfo < SIMachineFunctionInfo > ( ) ; MachineFrameInfo & FrameInfo = MF -> getFrameInfo ( ) ; const DebugLoc & DL = MBB . findDebugLoc ( MI ) ; unsigned Align = FrameInfo . getObjectAlignment ( FrameIndex ) ; unsigned Size = FrameInfo . getObjectSize ( FrameIndex ) ; unsigned SpillSize = TRI -> getSpillSize ( * RC ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad , Size , Align ) ; if ( RI . isSGPRClass ( RC ) ) { MFI -> setHasSpilledSGPRs ( ) ; const MCInstrDesc & OpDesc = get ( getSGPRSpillRestoreOpcode ( SpillSize ) ) ; if ( Register :: isVirtualRegister ( DestReg ) && SpillSize == 4 ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( DestReg , & AMDGPU :: SReg_32_XM0RegClass ) ; } if ( RI . spillSGPRToVGPR ( ) ) FrameInfo . setStackID ( FrameIndex , TargetStackID :: SGPRSpill ) ; MachineInstrBuilder Spill = BuildMI ( MBB , MI , DL , OpDesc , DestReg ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getStackPtrOffsetReg ( ) , RegState :: Implicit ) ; if ( ST . hasScalarStores ( ) ) { Spill . addReg ( AMDGPU :: M0 , RegState :: ImplicitDefine | RegState :: Dead ) ; } return ; } unsigned Opcode = RI . hasAGPRs ( RC ) ? getAGPRSpillRestoreOpcode ( SpillSize ) : getVGPRSpillRestoreOpcode ( SpillSize ) ; auto MIB = BuildMI ( MBB , MI , DL , get ( Opcode ) , DestReg ) ; if ( RI . hasAGPRs ( RC ) ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; Register Tmp = MRI . createVirtualRegister ( & AMDGPU :: VGPR_32RegClass ) ; MIB . addReg ( Tmp , RegState :: Define ) ; } MIB . addFrameIndex ( FrameIndex ) . addReg ( MFI -> getScratchRSrcReg ( ) ) . addReg ( MFI -> getStackPtrOffsetReg ( ) ) . addImm ( 0 ) . addMemOperand ( MMO ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> int arm_split_constant ( enum rtx_code code , machine_mode mode , rtx insn , HOST_WIDE_INT val , rtx target , rtx source , int subtargets ) { rtx cond ; if ( insn && GET_CODE ( PATTERN ( insn ) ) == COND_EXEC ) cond = COND_EXEC_TEST ( PATTERN ( insn ) ) ; else cond = NULL_RTX ; if ( subtargets || code == SET || ( REG_P ( target ) && REG_P ( source ) && REGNO ( target ) != REGNO ( source ) ) ) { if ( ! cfun -> machine -> after_arm_reorg && ! cond && ( arm_gen_constant ( code , mode , NULL_RTX , val , target , source , 1 , 0 ) > ( arm_constant_limit ( optimize_function_for_size_p ( cfun ) ) + ( code != SET ) ) ) ) { if ( code == SET ) { if ( TARGET_USE_MOVT ) arm_emit_movpair ( target , GEN_INT ( val ) ) ; else emit_set_insn ( target , GEN_INT ( val ) ) ; return 1 ; } else { rtx temp = subtargets ? gen_reg_rtx ( mode ) : target ; if ( TARGET_USE_MOVT ) arm_emit_movpair ( temp , GEN_INT ( val ) ) ; else emit_set_insn ( temp , GEN_INT ( val ) ) ; if ( code == MINUS ) emit_set_insn ( target , gen_rtx_MINUS ( mode , temp , source ) ) ; else emit_set_insn ( target , gen_rtx_fmt_ee ( code , mode , source , temp ) ) ; return 2 ; } } } return arm_gen_constant ( code , mode , cond , val , target , source , subtargets , 1 ) ; } </s>

Emit a sequence of insns to handle a large constant . CODE is the code of the operation required , it can be any of SET , PLUS , IOR , AND , XOR , MINUS ; MODE is the mode in which the operation is being performed ; VAL is the integer to operate on ; SOURCE is the other operand ( a register , or a null-pointer for SET ) ; SUBTARGETS means it is safe to create scratch registers if that will either produce a simpler sequence , or we will want to cse the values . Return value is the number of insns emitted .


<s> int shl_and_scr_length ( rtx insn ) { rtx set_src = SET_SRC ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) ) ; int len = ashl_lshr_seq [ INTVAL ( XEXP ( set_src , 1 ) ) & 31 ] . insn_count ; rtx op = XEXP ( set_src , 0 ) ; len += ashl_lshr_seq [ INTVAL ( XEXP ( op , 1 ) ) & 31 ] . insn_count + 1 ; op = XEXP ( XEXP ( op , 0 ) , 0 ) ; return len + ashl_lshr_seq [ INTVAL ( XEXP ( op , 1 ) ) & 31 ] . insn_count ; } </s>

This is used in length attribute of the and_shl_scratch instruction .


<s> bool nds32_rtx_costs_impl ( rtx x , machine_mode mode ATTRIBUTE_UNUSED , int outer_code , int opno ATTRIBUTE_UNUSED , int * total , bool speed ) { int code = GET_CODE ( x ) ; if ( speed ) goto performance_cost ; else goto size_cost ; performance_cost : switch ( code ) { case SET : return false ; case USE : * total = 0 ; break ; case MULT : * total = COSTS_N_INSNS ( 1 ) ; break ; case DIV : case UDIV : case MOD : case UMOD : * total = COSTS_N_INSNS ( 7 ) ; break ; default : * total = COSTS_N_INSNS ( 1 ) ; break ; } return true ; size_cost : switch ( code ) { case SET : return false ; case USE : * total = 0 ; break ; case CONST_INT : if ( outer_code == SET ) { if ( satisfies_constraint_Is05 ( x ) ) * total = COSTS_N_INSNS ( 1 ) - 2 ; else if ( satisfies_constraint_Is20 ( x ) ) * total = COSTS_N_INSNS ( 1 ) ; else * total = COSTS_N_INSNS ( 2 ) ; } else if ( outer_code == PLUS || outer_code == MINUS ) { if ( satisfies_constraint_Iu05 ( x ) ) * total = COSTS_N_INSNS ( 1 ) - 2 ; else * total = COSTS_N_INSNS ( 1 ) ; } else if ( outer_code == ASHIFT ) { if ( satisfies_constraint_Iu03 ( x ) ) * total = COSTS_N_INSNS ( 1 ) - 2 ; else * total = COSTS_N_INSNS ( 1 ) ; } else if ( outer_code == ASHIFTRT || outer_code == LSHIFTRT ) { if ( satisfies_constraint_Iu05 ( x ) ) * total = COSTS_N_INSNS ( 1 ) - 2 ; else * total = COSTS_N_INSNS ( 1 ) ; } else { * total = COSTS_N_INSNS ( 1 ) ; } break ; case CONST_DOUBLE : * total = COSTS_N_INSNS ( 2 ) ; break ; default : * total = COSTS_N_INSNS ( 1 ) ; break ; } return true ; } </s>

This target hook describes the relative costs of RTL expressions . Return 'true ' when all subexpressions of x have been processed . Return 'false ' to sum the costs of sub-rtx , plus cost of this operation . Refer to gcc/rtlanal.cc for more information .


<s>
void
SystemZInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MBBI
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
SystemZ
::
GR128BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
copyPhysReg
(
MBB
,
MBBI
,
DL
,
RI
.
getSubReg
(
DestReg
,
SystemZ
::
subreg_h64
)
,
RI
.
getSubReg
(
SrcReg
,
SystemZ
::
subreg_h64
)
,
KillSrc
)
;
copyPhysReg
(
MBB
,
MBBI
,
DL
,
RI
.
getSubReg
(
DestReg
,
SystemZ
::
subreg_l64
)
,
RI
.
getSubReg
(
SrcReg
,
SystemZ
::
subreg_l64
)
,
KillSrc
)
;
return
;
}
if
(
SystemZ
::
GRX32BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
emitGRX32Move
(
MBB
,
MBBI
,
DL
,
DestReg
,
SrcReg
,
SystemZ
::
LR
,
32
,
KillSrc
)
;
return
;
}
unsigned
Opcode
;
if
(
SystemZ
::
GR64BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LGR
;
else
if
(
SystemZ
::
FP32BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
STI
.
hasVector
(
)
SystemZ
::
LDR32
:
SystemZ
::
LER
;
else
if
(
SystemZ
::
FP64BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LDR
;
else
if
(
SystemZ
::
FP128BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LXR
;
else
if
(
SystemZ
::
VR32BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
VLR32
;
else
if
(
SystemZ
::
VR64BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
VLR64
;
else
if
(
SystemZ
::
VR128BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
VLR
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
Opcode
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> static bool mips_use_anchors_for_symbol_p ( const_rtx symbol ) { switch ( mips_classify_symbol ( symbol , SYMBOL_CONTEXT_MEM ) ) { case SYMBOL_PC_RELATIVE : case SYMBOL_GP_RELATIVE : return false ; default : return default_use_anchors_for_symbol_p ( symbol ) ; } } </s>

Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P . We do n't want to use anchors for small data : the GP register acts as an anchor in that case . We also do n't want to use them for PC-relative accesses , where the PC acts as an anchor .


<s> void or1k_expand_prologue ( void ) { HOST_WIDE_INT sp_offset = - cfun -> machine -> total_size ; HOST_WIDE_INT reg_offset , this_offset ; rtx insn ; if ( flag_stack_usage_info ) current_function_static_stack_size = - sp_offset ; if ( sp_offset == 0 ) goto fini ; reg_offset = ( sp_offset + cfun -> machine -> local_vars_size + cfun -> machine -> args_size ) ; this_offset = MAX ( sp_offset , - 32764 ) ; reg_offset -= this_offset ; sp_offset -= this_offset ; insn = emit_insn ( gen_frame_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( this_offset ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; for ( int regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( regno != HARD_FRAME_POINTER_REGNUM && regno != LR_REGNUM && callee_saved_regno_p ( regno ) ) { or1k_save_reg ( regno , reg_offset ) ; reg_offset += UNITS_PER_WORD ; } if ( callee_saved_regno_p ( HARD_FRAME_POINTER_REGNUM ) ) { or1k_save_reg ( HARD_FRAME_POINTER_REGNUM , reg_offset ) ; if ( frame_pointer_needed ) { insn = emit_insn ( gen_addsi3 ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( - this_offset ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } reg_offset += UNITS_PER_WORD ; } if ( callee_saved_regno_p ( LR_REGNUM ) ) { or1k_save_reg ( LR_REGNUM , reg_offset ) ; reg_offset += UNITS_PER_WORD ; } gcc_assert ( reg_offset + this_offset == 0 ) ; if ( sp_offset != 0 ) { if ( sp_offset < 2 * - 32768 ) { rtx tmp = gen_rtx_REG ( Pmode , PE_TMP_REGNUM ) ; emit_move_insn ( tmp , GEN_INT ( sp_offset ) ) ; insn = emit_insn ( gen_frame_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , tmp ) ) ; if ( ! frame_pointer_needed ) { RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , sp_offset ) ) ) ; } } else { do { this_offset = MAX ( sp_offset , - 32768 ) ; sp_offset -= this_offset ; insn = emit_insn ( gen_frame_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( this_offset ) ) ) ; if ( ! frame_pointer_needed ) RTX_FRAME_RELATED_P ( insn ) = 1 ; } while ( sp_offset != 0 ) ; } } fini : rtx_insn * set_got_insn = cfun -> machine -> set_got_insn ; if ( crtl -> uses_pic_offset_table ) { rtx reg = SET_DEST ( PATTERN ( set_got_insn ) ) ; rtx_insn * insn = emit_insn_before ( gen_set_got ( reg ) , set_got_insn ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_FLUSH_QUEUE , NULL_RTX ) ; } delete_insn ( set_got_insn ) ; } </s>


<s> const MCPhysReg * PatmosRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const TargetFrameLowering * TFI = MF -> getSubtarget ( ) . getFrameLowering ( ) ; static const uint16_t CalleeSavedRegs [ ] = { Patmos :: S0 , Patmos :: SRB , Patmos :: SRO , Patmos :: R21 , Patmos :: R22 , Patmos :: R23 , Patmos :: R24 , Patmos :: R25 , Patmos :: R26 , Patmos :: R27 , Patmos :: R28 , Patmos :: P1 , Patmos :: P2 , Patmos :: P3 , Patmos :: P4 , Patmos :: P5 , Patmos :: P6 , Patmos :: P7 , 0 } ; static const uint16_t CalleeSavedRegsFP [ ] = { Patmos :: S0 , Patmos :: SRB , Patmos :: SRO , Patmos :: R21 , Patmos :: R22 , Patmos :: R23 , Patmos :: R24 , Patmos :: R25 , Patmos :: R26 , Patmos :: R27 , Patmos :: R28 , Patmos :: RFP , Patmos :: P1 , Patmos :: P2 , Patmos :: P3 , Patmos :: P4 , Patmos :: P5 , Patmos :: P6 , Patmos :: P7 , 0 } ; return ( TFI -> hasFP ( * MF ) ) ? CalleeSavedRegsFP : CalleeSavedRegs ; } </s>


<s> bool MipsLongBranch :: runOnMachineFunction ( MachineFunction & F ) { const MipsInstrInfo * TII = static_cast < const MipsInstrInfo * > ( TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; const MipsSubtarget & STI = TM . getSubtarget < MipsSubtarget > ( ) ; if ( STI . inMips16Mode ( ) || ! STI . enableLongBranchPass ( ) ) return false ; if ( ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) && TM . getSubtarget < MipsSubtarget > ( ) . isABI_O32 ( ) && F . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; int ShVal = TM . getSubtarget < MipsSubtarget > ( ) . inMicroMipsMode ( ) ? 2 : 4 ; int64_t Offset = computeOffset ( I -> Br ) / ShVal ; if ( TM . getSubtarget < MipsSubtarget > ( ) . isTargetNaCl ( ) ) { Offset *= 2 ; } if ( ! ForceLongBranch && isInt < 16 > ( Offset ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * 4 ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { uint64_t Address = 0 ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ; } for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) if ( I -> HasLongBranch ) expandToLongBranch ( * I ) ; MF -> RenumberBlocks ( ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips 2 4 Mips 2 16 4 0


<s> poly_int64 ix86_push_rounding ( poly_int64 bytes ) { return ROUND_UP ( bytes , UNITS_PER_WORD ) ; } </s>

Implement PUSH_ROUNDING . On 386 , we have pushw instruction that decrements by exactly 2 no matter what the position was , there is no pushb . But as CIE data alignment factor on this arch is -4 for 32bit targets and -8 for 64bit targets , we need to make sure all stack pointer adjustments are in multiple of 4 for 32bit targets and 8 for 64bit targets .


<s> void emitFill ( const MCExpr & NumBytes , uint64_t FillValue , SMLoc Loc ) override { emitDataMappingSymbol ( ) ; MCObjectStreamer :: emitFill ( NumBytes , FillValue , Loc ) ; } </s>

Emit Size bytes worth of the value specified by FillValue .


<s> void PPCTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { Known . resetAll ( ) ; switch ( Op . getOpcode ( ) ) { default : break ; case PPCISD :: LBRX : { if ( cast < VTSDNode > ( Op . getOperand ( 2 ) ) -> getVT ( ) == MVT :: i16 ) Known . Zero = 0xFFFF0000 ; break ; } case ISD :: INTRINSIC_WO_CHAIN : { switch ( cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ) { default : break ; case Intrinsic :: ppc_altivec_vcmpbfp_p : case Intrinsic :: ppc_altivec_vcmpeqfp_p : case Intrinsic :: ppc_altivec_vcmpequb_p : case Intrinsic :: ppc_altivec_vcmpequh_p : case Intrinsic :: ppc_altivec_vcmpequw_p : case Intrinsic :: ppc_altivec_vcmpequd_p : case Intrinsic :: ppc_altivec_vcmpequq_p : case Intrinsic :: ppc_altivec_vcmpgefp_p : case Intrinsic :: ppc_altivec_vcmpgtfp_p : case Intrinsic :: ppc_altivec_vcmpgtsb_p : case Intrinsic :: ppc_altivec_vcmpgtsh_p : case Intrinsic :: ppc_altivec_vcmpgtsw_p : case Intrinsic :: ppc_altivec_vcmpgtsd_p : case Intrinsic :: ppc_altivec_vcmpgtsq_p : case Intrinsic :: ppc_altivec_vcmpgtub_p : case Intrinsic :: ppc_altivec_vcmpgtuh_p : case Intrinsic :: ppc_altivec_vcmpgtuw_p : case Intrinsic :: ppc_altivec_vcmpgtud_p : case Intrinsic :: ppc_altivec_vcmpgtuq_p : Known . Zero = ~ 1U ; break ; } } } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> static void emit_store_direct ( rtx block , int offset , int value ) { emit_insn ( gen_store_direct ( adjust_address ( block , SImode , offset ) , force_reg ( SImode , gen_int_mode ( value , SImode ) ) ) ) ; } </s>

Directly store VALUE into memory object BLOCK at OFFSET .


<s> static int comparator ( const void * va , const void * vb ) { const char * a = * ( const char * const * ) va ; const char * b = * ( const char * const * ) vb ; while ( * a && * b ) { if ( letter ( * a ) && digit ( * b ) ) return - 1 ; if ( digit ( * a ) && letter ( * b ) ) return 1 ; if ( * a != * b ) return * a - * b ; a ++ ; b ++ ; } return * a - * b ; } </s>

Compare two MCUs and order them for easy lookup .


<s> bool X86TargetLowering :: isShuffleMaskLegal ( SDValue Mask , MVT VT ) const { if ( VT . getSizeInBits ( ) == 64 ) return false ; return ( Mask . getNode ( ) -> getNumOperands ( ) <= 4 || isIdentityMask ( Mask . getNode ( ) ) || isIdentityMask ( Mask . getNode ( ) , true ) || isSplatMask ( Mask . getNode ( ) ) || X86 :: isPSHUFHWMask ( Mask . getNode ( ) ) || X86 :: isPSHUFLWMask ( Mask . getNode ( ) ) || X86 :: isUNPCKLMask ( Mask . getNode ( ) ) || X86 :: isUNPCKHMask ( Mask . getNode ( ) ) || X86 :: isUNPCKL_v_undef_Mask ( Mask . getNode ( ) ) || X86 :: isUNPCKH_v_undef_Mask ( Mask . getNode ( ) ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> unsigned postOffset ( ) const { return Offset + Size ; } </s>

Compute the offset immediately following this block .


ARCTargetMachine ctor - Create an ILP32 architecture model .


<s> TargetIRAnalysis LanaiTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( const Function & F ) { return TargetTransformInfo ( LanaiTTIImpl ( this , F ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


<s> bool AArch64PassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnablePromoteConstant ) addPass ( createAArch64PromoteConstantPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createGlobalMergePass ( TM ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createAArch64AddressTypePromotionPass ( ) ) ; addPass ( createAtomicExpandLoadLinkedPass ( TM ) ) ; return false ; } </s>


<s> bool arm_const_double_by_parts ( rtx val ) { enum machine_mode mode = GET_MODE ( val ) ; rtx part ; if ( optimize_size || arm_ld_sched ) return true ; if ( mode == VOIDmode ) mode = DImode ; part = gen_highpart_mode ( SImode , mode , val ) ; gcc_assert ( GET_CODE ( part ) == CONST_INT ) ; if ( const_ok_for_arm ( INTVAL ( part ) ) || const_ok_for_arm ( ~ INTVAL ( part ) ) ) return true ; part = gen_lowpart ( SImode , val ) ; gcc_assert ( GET_CODE ( part ) == CONST_INT ) ; if ( const_ok_for_arm ( INTVAL ( part ) ) || const_ok_for_arm ( ~ INTVAL ( part ) ) ) return true ; return false ; } </s>

Return true if it is worthwhile to split a 64-bit constant into two 32-bit operations . This is the case if optimizing for size , or if we have load delay slots , or if one 32-bit part can be done with a single data operation .


<s> bool SystemZLDCleanup :: runOnMachineFunction ( MachineFunction & F ) { if ( skipFunction ( * F . getFunction ( ) ) ) return false ; TII = static_cast < const SystemZInstrInfo * > ( F . getSubtarget ( ) . getInstrInfo ( ) ) ; MF = & F ; SystemZMachineFunctionInfo * MFI = F . getInfo < SystemZMachineFunctionInfo > ( ) ; if ( MFI -> getNumLocalDynamicTLSAccesses ( ) < 2 ) { return false ; } MachineDominatorTree * DT = & getAnalysis < MachineDominatorTree > ( ) ; return VisitNode ( DT -> getRootNode ( ) , 0 ) ; } </s>

SystemZ SystemZ SystemZ SystemZ SystemZ 2 0


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s>
bool
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
override
{
MCInst
Inst
;
Inst
.
setLoc
(
IDLoc
)
;
FeatureBitset
MissingFeatures
;
unsigned
MatchResult
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MissingFeatures
,
MatchingInlineAsm
)
;
switch
(
MatchResult
)
{
case
Match_Success
:
{
ensureLocals
(
Out
)
;
auto
Align
=
WebAssembly
::
GetDefaultP2AlignAny
(
Inst
.
getOpcode
(
)
)
;
if
(
Align
!=
1U
)
{
auto
&
Op0
=
Inst
.
getOperand
(
0
)
;
if
(
Op0
.
getImm
(
)
==
1
)
Op0
.
setImm
(
Align
)
;
}
if
(
is64
)
{
auto
Opc64
=
WebAssembly
::
getWasm64Opcode
(
static_cast
<
uint16_t
>
(
Inst
.
getOpcode
(
)
)
)
;
if
(
Opc64
>=
0
)
{
Inst
.
setOpcode
(
Opc64
)
;
}
}
if
(
!
SkipTypeCheck
&&
TC
.
typeCheck
(
IDLoc
,
Inst
,
Operands
)
)
return
true
;
Out
.
emitInstruction
(
Inst
,
getSTI
(
)
)
;
if
(
CurrentState
==
EndFunction
)
{
onEndOfFunction
(
IDLoc
)
;
}
else
{
CurrentState
=
Instructions
;
}
return
false
;
}
case
Match_MissingFeature
:
{
assert
(
MissingFeatures
.
count
(
)
>
0
&&
"Expected missing features"
)
;
SmallString
<
128
>
Message
;
raw_svector_ostream
OS
(
Message
)
;
OS
<<
"instruction requires:"
;
for
(
unsigned
i
=
0
,
e
=
MissingFeatures
.
size
(
)
;
i
!=
e
;
++
i
)
if
(
MissingFeatures
.
test
(
i
)
)
OS
<<
' '
<<
getSubtargetFeatureName
(
i
)
;
return
Parser
.
Error
(
IDLoc
,
Message
)
;
}
case
Match_MnemonicFail
:
return
Parser
.
Error
(
IDLoc
,
"invalid instruction"
)
;
case
Match_NearMisses
:
return
Parser
.
Error
(
IDLoc
,
"ambiguous instruction"
)
;
case
Match_InvalidTiedOperand
:
case
Match_InvalidOperand
:
{
SMLoc
ErrorLoc
=
IDLoc
;
if
(
ErrorInfo
!=
~
0ULL
)
{
if
(
ErrorInfo
>=
Operands
.
size
(
)
)
return
Parser
.
Error
(
IDLoc
,
"too few operands for instruction"
)
;
ErrorLoc
=
Operands
[
ErrorInfo
]
->
getStartLoc
(
)
;
if
(
ErrorLoc
==
SMLoc
(
)
)
ErrorLoc
=
IDLoc
;
}
return
Parser
.
Error
(
ErrorLoc
,
"invalid operand for instruction"
)
;
}
}
llvm_unreachable
(
"Implement any new match types added!"
)
;
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> bool XCoreAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { return true ; } printOperand ( MI , OpNum , O ) ; O << '[' ; printOperand ( MI , OpNum + 1 , O ) ; O << ']' ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> bool MBlazeTargetMachine :: addPreEmitPass ( PassManagerBase & PM ) { PM . add ( createMBlazeDelaySlotFillerPass ( * this ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static rtx arm_expand_unop_builtin ( enum insn_code icode , tree arglist , rtx target , int do_load ) { rtx pat ; tree arg0 = TREE_VALUE ( arglist ) ; rtx op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , 0 ) ; enum machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; enum machine_mode mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( do_load ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; else { if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; } pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>

Subroutine of arm_expand_builtin to take care of unop insns .


<s> void pop ( ) { Set . erase ( front ( ) ) ; Uses . pop ( ) ; } </s>


<s> TargetLowering :: ConstraintType DCPU16TargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return C_RegisterClass ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static bool avr_reg_ok_for_pgm_addr ( rtx reg , bool strict ) { gcc_assert ( REG_P ( reg ) ) ; if ( strict ) { return REGNO ( reg ) == REG_Z ; } if ( can_create_pseudo_p ( ) && REGNO ( reg ) < REG_Z ) { return false ; } return true ; } </s>


<s> sbitmap rs6000_get_separate_components ( void ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; if ( WORLD_SAVE_P ( info ) ) return NULL ; gcc_assert ( ! ( info -> savres_strategy & SAVE_MULTIPLE ) && ! ( info -> savres_strategy & REST_MULTIPLE ) ) ; cfun -> machine -> n_components = 64 ; sbitmap components = sbitmap_alloc ( cfun -> machine -> n_components ) ; bitmap_clear ( components ) ; int reg_size = TARGET_32BIT ? 4 : 8 ; int fp_reg_size = 8 ; if ( ( info -> savres_strategy & SAVE_INLINE_GPRS ) && ( info -> savres_strategy & REST_INLINE_GPRS ) ) { int offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( unsigned regno = info -> first_gp_reg_save ; regno < 32 ; regno ++ ) { if ( IN_RANGE ( offset , - 0x8000 , 0x7fff ) && save_reg_p ( regno ) ) bitmap_set_bit ( components , regno ) ; offset += reg_size ; } } if ( frame_pointer_needed ) bitmap_clear_bit ( components , HARD_FRAME_POINTER_REGNUM ) ; if ( ( TARGET_TOC && TARGET_MINIMAL_TOC ) || ( flag_pic == 1 && DEFAULT_ABI == ABI_V4 ) || ( flag_pic && DEFAULT_ABI == ABI_DARWIN ) ) bitmap_clear_bit ( components , RS6000_PIC_OFFSET_TABLE_REGNUM ) ; if ( ( info -> savres_strategy & SAVE_INLINE_FPRS ) && ( info -> savres_strategy & REST_INLINE_FPRS ) ) { int offset = info -> fp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( unsigned regno = info -> first_fp_reg_save ; regno < 64 ; regno ++ ) { if ( IN_RANGE ( offset , - 0x8000 , 0x7fff ) && save_reg_p ( regno ) ) bitmap_set_bit ( components , regno ) ; offset += fp_reg_size ; } } if ( info -> lr_save_p && ! ( flag_pic && ( DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN ) ) && ( info -> savres_strategy & SAVE_INLINE_GPRS ) && ( info -> savres_strategy & REST_INLINE_GPRS ) && ( info -> savres_strategy & SAVE_INLINE_FPRS ) && ( info -> savres_strategy & REST_INLINE_FPRS ) && ( info -> savres_strategy & SAVE_INLINE_VRS ) && ( info -> savres_strategy & REST_INLINE_VRS ) ) { int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; if ( IN_RANGE ( offset , - 0x8000 , 0x7fff ) ) bitmap_set_bit ( components , 0 ) ; } if ( cfun -> machine -> save_toc_in_prologue ) bitmap_set_bit ( components , 2 ) ; return components ; } </s>


<s> static bool riscv_classify_address ( struct riscv_address_info * info , rtx x , machine_mode mode , bool strict_p ) { switch ( GET_CODE ( x ) ) { case REG : case SUBREG : info -> type = ADDRESS_REG ; info -> reg = x ; info -> offset = const0_rtx ; return riscv_valid_base_register_p ( info -> reg , mode , strict_p ) ; case PLUS : if ( riscv_v_ext_vector_mode_p ( mode ) ) return false ; info -> type = ADDRESS_REG ; info -> reg = XEXP ( x , 0 ) ; info -> offset = XEXP ( x , 1 ) ; return ( riscv_valid_base_register_p ( info -> reg , mode , strict_p ) && riscv_valid_offset_p ( info -> offset , mode ) ) ; case LO_SUM : if ( riscv_v_ext_vector_mode_p ( mode ) ) return false ; info -> type = ADDRESS_LO_SUM ; info -> reg = XEXP ( x , 0 ) ; info -> offset = XEXP ( x , 1 ) ; info -> symbol_type = riscv_classify_symbolic_expression ( info -> offset ) ; return ( riscv_valid_base_register_p ( info -> reg , mode , strict_p ) && riscv_valid_lo_sum_p ( info -> symbol_type , mode , info -> offset ) ) ; case CONST_INT : if ( riscv_v_ext_vector_mode_p ( mode ) ) return false ; info -> type = ADDRESS_CONST_INT ; return SMALL_OPERAND ( INTVAL ( x ) ) ; default : return false ; } } </s>

Return true if X is a valid address for machine mode MODE . If it is , fill in INFO appropriately . STRICT_P is true if REG_OK_STRICT is in effect .


"ReadCycleWrite is only to be used on riscv32"

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> Value * AArch64TargetLowering :: emitLoadLinked ( IRBuilder < > & Builder , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Type * ValTy = cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ; bool IsAcquire = isAcquireOrStronger ( Ord ) ; if ( ValTy -> getPrimitiveSizeInBits ( ) == 128 ) { Intrinsic :: ID Int = IsAcquire ? Intrinsic :: aarch64_ldaxp : Intrinsic :: aarch64_ldxp ; Function * Ldxr = Intrinsic :: getDeclaration ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldxr , Addr , "lohi" ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ; Lo = Builder . CreateZExt ( Lo , ValTy , "lo64" ) ; Hi = Builder . CreateZExt ( Hi , ValTy , "hi64" ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , 64 ) ) , "val64" ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; Intrinsic :: ID Int = IsAcquire ? Intrinsic :: aarch64_ldaxr : Intrinsic :: aarch64_ldxr ; Function * Ldxr = Intrinsic :: getDeclaration ( M , Int , Tys ) ; Type * EltTy = cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ; const DataLayout & DL = M -> getDataLayout ( ) ; IntegerType * IntEltTy = Builder . getIntNTy ( DL . getTypeSizeInBits ( EltTy ) ) ; Value * Trunc = Builder . CreateTrunc ( Builder . CreateCall ( Ldxr , Addr ) , IntEltTy ) ; return Builder . CreateBitCast ( Trunc , EltTy ) ; } </s>

Perform a load-linked operation on Addr , returning a `` Value * '' with the corresponding pointee type .


<s>
void
AArch64RegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
MBBI
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Cannot deal with nonzero SPAdj yet"
)
;
MachineInstr
&
MI
=
*
MBBI
;
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
const
AArch64FrameLowering
*
TFI
=
static_cast
<
const
AArch64FrameLowering
*
>
(
MF
.
getTarget
(
)
.
getFrameLowering
(
)
)
;
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
->
getCalleeSavedInfo
(
)
;
int
MinCSFI
=
0
;
int
MaxCSFI
=
1
;
if
(
CSI
.
size
(
)
)
{
MinCSFI
=
CSI
[
0
]
.
getFrameIdx
(
)
;
MaxCSFI
=
CSI
[
CSI
.
size
(
)
1
]
.
getFrameIdx
(
)
;
}
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
bool
IsCalleeSaveOp
=
FrameIndex
>=
MinCSFI
&&
FrameIndex
<=
MaxCSFI
;
unsigned
FrameReg
;
int64_t
Offset
;
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
,
SPAdj
,
IsCalleeSaveOp
)
;
bool
HasOffsetOp
=
hasFrameOffset
(
MI
.
getOpcode
(
)
)
;
if
(
HasOffsetOp
)
Offset
+=
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
;
if
(
MI
.
isDebugValue
(
)
)
{
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
)
;
return
;
}
const
AArch64InstrInfo
&
TII
=
*
static_cast
<
const
AArch64InstrInfo
*
>
(
MF
.
getTarget
(
)
.
getInstrInfo
(
)
)
;
int
MinOffset
,
MaxOffset
,
OffsetScale
;
if
(
MI
.
getOpcode
(
)
==
AArch64
::
ADDxxi_lsl0_s
||
!
HasOffsetOp
)
{
MinOffset
=
0
;
MaxOffset
=
0xfff
;
OffsetScale
=
1
;
}
else
{
TII
.
getAddressConstraints
(
MI
,
OffsetScale
,
MinOffset
,
MaxOffset
)
;
}
if
(
(
Offset
%
OffsetScale
!=
0
||
Offset
<
MinOffset
||
Offset
>
MaxOffset
)
||
(
!
HasOffsetOp
&&
Offset
!=
0
)
)
{
unsigned
BaseReg
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
&
AArch64
::
GPR64RegClass
)
;
emitRegUpdate
(
MBB
,
MBBI
,
MBBI
->
getDebugLoc
(
)
,
TII
,
BaseReg
,
FrameReg
,
BaseReg
,
Offset
)
;
FrameReg
=
BaseReg
;
Offset
=
0
;
}
assert
(
Offset
>=
0
&&
"Unexpected negative offset from SP"
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
,
false
,
true
)
;
if
(
HasOffsetOp
)
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
/
OffsetScale
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> const MCSection * X86ELFMCAsmInfo :: getNonexecutableStackSection ( MCContext & Ctx ) const { return Ctx . getELFSection ( ".note.GNU-stack" , ELF :: SHT_PROGBITS , 0 , SectionKind :: getMetadata ( ) ) ; } </s>

Targets can implement this method to specify a section to switch to if the translation unit does n't have any trampolines that require an executable stack .


<s> void MCS51PassConfig :: addPreEmitPass ( ) { addPass ( & BranchRelaxationPassID ) ; } </s>


<s> bool AArch64AsmParser :: ParseDirective ( AsmToken DirectiveID ) { const MCObjectFileInfo :: Environment Format = getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ; bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; StringRef IDVal = DirectiveID . getIdentifier ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == ".arch" ) parseDirectiveArch ( Loc ) ; else if ( IDVal == ".cpu" ) parseDirectiveCPU ( Loc ) ; else if ( IDVal == ".tlsdesccall" ) parseDirectiveTLSDescCall ( Loc ) ; else if ( IDVal == ".ltorg" || IDVal == ".pool" ) parseDirectiveLtorg ( Loc ) ; else if ( IDVal == ".unreq" ) parseDirectiveUnreq ( Loc ) ; else if ( IDVal == ".inst" ) parseDirectiveInst ( Loc ) ; else if ( IDVal == ".cfi_negate_ra_state" ) parseDirectiveCFINegateRAState ( ) ; else if ( IDVal == ".cfi_b_key_frame" ) parseDirectiveCFIBKeyFrame ( ) ; else if ( IDVal == ".arch_extension" ) parseDirectiveArchExtension ( Loc ) ; else if ( IsMachO ) { if ( IDVal == MCLOHDirectiveName ( ) ) parseDirectiveLOH ( IDVal , Loc ) ; else return true ; } else return true ; return false ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> void emitBytes ( StringRef Data ) override { } </s>

Emit the bytes in Data into the output .


<s> void ix86_split_copysign_const ( rtx operands [ ] ) { machine_mode mode , vmode ; rtx dest , op0 , mask , x ; dest = operands [ 0 ] ; op0 = operands [ 1 ] ; mask = operands [ 3 ] ; mode = GET_MODE ( dest ) ; vmode = GET_MODE ( mask ) ; dest = simplify_gen_subreg ( vmode , dest , mode , 0 ) ; x = gen_rtx_AND ( vmode , dest , mask ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , x ) ) ; if ( op0 != CONST0_RTX ( vmode ) ) { x = gen_rtx_IOR ( vmode , dest , op0 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , x ) ) ; } } </s>

Deconstruct a copysign operation into bit masks . Operand 0 is known to be a constant , and so has already been expanded into a vector constant .


<s> CCAssignFn * AArch64FastISel :: CCAssignFnForCall ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: WebKit_JS ) return CC_AArch64_WebKit_JS ; if ( CC == CallingConv :: GHC ) return CC_AArch64_GHC ; if ( CC == CallingConv :: CFGuard_Check ) return CC_AArch64_Win64_CFGuard_Check ; return Subtarget -> isTargetDarwin ( ) ? CC_AArch64_DarwinPCS : CC_AArch64_AAPCS ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> int msp430_hard_regno_nregs_has_padding ( int regno ATTRIBUTE_UNUSED , machine_mode mode ) { if ( mode == PSImode && msp430x ) return 1 ; return ( ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ) ; } </s>


<s> bool R600InstrInfo :: isPredicable ( MachineInstr * MI ) const { if ( MI -> getOpcode ( ) == AMDGPU :: KILLGT ) { return false ; } else { return AMDGPUInstrInfo :: isPredicable ( MI ) ; } } </s>

Return true if the specified instruction can be predicated .


"Requesting 64-bit offset in 32-bit immediate!"


<s> bool xtensa_split1_finished_p ( void ) { return cfun && ( cfun -> curr_properties & PROP_rtl_split_insns ) ; } </s>

Return true after `` split1 '' pass has been finished .


<s> static void cris_function_arg_advance ( cumulative_args_t ca_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * ca = get_cumulative_args ( ca_v ) ; ca -> regs += ( 3 + CRIS_FUNCTION_ARG_SIZE ( mode , type ) ) / 4 ; } </s>

Worker function for TARGET_FUNCTION_ARG_ADVANCE .


<s> bool X86TargetLowering :: IsDesirableToPromoteOp ( SDValue Op , EVT & PVT ) const { EVT VT = Op . getValueType ( ) ; if ( VT != MVT :: i16 ) return false ; auto IsFoldableRMW = [ ] ( SDValue Load , SDValue Op ) { if ( ! Op . hasOneUse ( ) ) return false ; SDNode * User = * Op -> use_begin ( ) ; if ( ! ISD :: isNormalStore ( User ) ) return false ; auto * Ld = cast < LoadSDNode > ( Load ) ; auto * St = cast < StoreSDNode > ( User ) ; return Ld -> getBasePtr ( ) == St -> getBasePtr ( ) ; } ; bool Commute = false ; switch ( Op . getOpcode ( ) ) { default : return false ; case ISD :: SIGN_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: ANY_EXTEND : break ; case ISD :: SHL : case ISD :: SRL : { SDValue N0 = Op . getOperand ( 0 ) ; if ( MayFoldLoad ( N0 ) && IsFoldableRMW ( N0 , Op ) ) return false ; break ; } case ISD :: ADD : case ISD :: MUL : case ISD :: AND : case ISD :: OR : case ISD :: XOR : Commute = true ; LLVM_FALLTHROUGH ; case ISD :: SUB : { SDValue N0 = Op . getOperand ( 0 ) ; SDValue N1 = Op . getOperand ( 1 ) ; if ( MayFoldLoad ( N1 ) && ( ! Commute || ! isa < ConstantSDNode > ( N0 ) || ( Op . getOpcode ( ) != ISD :: MUL && IsFoldableRMW ( N1 , Op ) ) ) ) return false ; if ( MayFoldLoad ( N0 ) && ( ( Commute && ! isa < ConstantSDNode > ( N1 ) ) || ( Op . getOpcode ( ) != ISD :: MUL && IsFoldableRMW ( N0 , Op ) ) ) ) return false ; } } PVT = MVT :: i32 ; return true ; } </s>

Return true if the target has native support for the specified value type and it is 'desirable ' to use the type .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"SystemZ Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool PPCSubtarget :: enablePostRAScheduler ( ) const { return true ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return new MachObjectWriter ( OS , true ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static enum rtx_code ix86_prepare_fp_compare_args ( enum rtx_code code , rtx * pop0 , rtx * pop1 ) { enum machine_mode fpcmp_mode = ix86_fp_compare_mode ( code ) ; rtx op0 = * pop0 , op1 = * pop1 ; enum machine_mode op_mode = GET_MODE ( op0 ) ; int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P ( op_mode ) ; if ( ! is_sse && ( fpcmp_mode == CCFPUmode || ( op_mode == XFmode && ! ( standard_80387_constant_p ( op0 ) == 1 || standard_80387_constant_p ( op1 ) == 1 ) && GET_CODE ( op1 ) != FLOAT ) || ix86_use_fcomi_compare ( code ) ) ) { op0 = force_reg ( op_mode , op0 ) ; op1 = force_reg ( op_mode , op1 ) ; } else { if ( standard_80387_constant_p ( op0 ) == 0 || ( GET_CODE ( op0 ) == MEM && ! ( standard_80387_constant_p ( op1 ) == 0 || GET_CODE ( op1 ) == MEM ) ) ) { rtx tmp ; tmp = op0 , op0 = op1 , op1 = tmp ; code = swap_condition ( code ) ; } if ( GET_CODE ( op0 ) != REG ) op0 = force_reg ( op_mode , op0 ) ; if ( CONSTANT_P ( op1 ) ) { int tmp = standard_80387_constant_p ( op1 ) ; if ( tmp == 0 ) op1 = validize_mem ( force_const_mem ( op_mode , op1 ) ) ; else if ( tmp == 1 ) { if ( TARGET_CMOVE ) op1 = force_reg ( op_mode , op1 ) ; } else op1 = force_reg ( op_mode , op1 ) ; } } if ( ix86_fp_comparison_cost ( code ) > ix86_fp_comparison_cost ( swap_condition ( code ) ) && ( GET_CODE ( op1 ) == REG || ! no_new_pseudos ) ) { rtx tmp ; tmp = op0 , op0 = op1 , op1 = tmp ; code = swap_condition ( code ) ; if ( GET_CODE ( op0 ) != REG ) op0 = force_reg ( op_mode , op0 ) ; } * pop0 = op0 ; * pop1 = op1 ; return code ; } </s>

Swap , force into registers , or otherwise massage the two operands to a fp comparison . The operands are updated in place ; the new comparsion code is returned .


<s> int small_data_operand ( rtx op ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED ) { rtx sym_ref ; if ( rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA ) return 0 ; if ( DEFAULT_ABI != ABI_V4 ) return 0 ; if ( TARGET_SPE && ( SPE_VECTOR_MODE ( mode ) || FLOAT_MODE_P ( mode ) ) ) return 0 ; if ( GET_CODE ( op ) == SYMBOL_REF ) sym_ref = op ; else if ( GET_CODE ( op ) != CONST || GET_CODE ( XEXP ( op , 0 ) ) != PLUS || GET_CODE ( XEXP ( XEXP ( op , 0 ) , 0 ) ) != SYMBOL_REF || GET_CODE ( XEXP ( XEXP ( op , 0 ) , 1 ) ) != CONST_INT ) return 0 ; else { rtx sum = XEXP ( op , 0 ) ; HOST_WIDE_INT summand ; summand = INTVAL ( XEXP ( sum , 1 ) ) ; if ( summand < 0 || summand > g_switch_value ) return 0 ; sym_ref = XEXP ( sum , 0 ) ; } return SYMBOL_REF_SMALL_P ( sym_ref ) ; return 0 ; } </s>

Return 1 for an operand in small memory on V.4/eabi .


<s> unsigned AMDGPUCommonSubtarget :: getOccupancyWithLocalMemSize ( const MachineFunction & MF ) const { const auto * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; return getOccupancyWithLocalMemSize ( MFI -> getLDSSize ( ) , MF . getFunction ( ) ) ; } </s>

Inverse of getMaxLocalMemWithWaveCount .


<s>
static
void
rl78_note_reg_set
(
char
*
dead
,
rtx
d
,
rtx
insn
)
{
int
r
,
i
;
bool
is_dead
;
if
(
GET_CODE
(
d
)
==
MEM
)
rl78_note_reg_uses
(
dead
,
XEXP
(
d
,
0
)
,
insn
)
;
if
(
GET_CODE
(
d
)
!=
REG
)
return
;
r
=
REGNO
(
d
)
;
is_dead
=
true
;
for
(
i
=
0
;
i
<
GET_MODE_SIZE
(
GET_MODE
(
d
)
)
;
i
++
)
if
(
!
dead
[
r
+
i
]
)
is_dead
=
false
;
if
(
is_dead
)
add_reg_note
(
insn
,
REG_UNUSED
,
gen_rtx_REG
(
GET_MODE
(
d
)
,
r
)
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"note set reg %d size %d\n"
,
r
,
GET_MODE_SIZE
(
GET_MODE
(
d
)
)
)
;
for
(
i
=
0
;
i
<
GET_MODE_SIZE
(
GET_MODE
(
d
)
)
;
i
++
)
dead
[
r
+
i
]
=
1
;
}
</s>

Like the previous function , but scan for SETs instead .


<s> bool MSP430AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static void emit_store_conditional ( machine_mode mode , rtx res , rtx mem , rtx val ) { rtx ( * fn ) ( rtx , rtx , rtx ) = NULL ; if ( mode == SImode ) fn = gen_store_conditional_si ; else if ( mode == DImode ) fn = gen_store_conditional_di ; emit_insn ( fn ( res , mem , val ) ) ; } </s>

A subroutine of the atomic operation splitters . Emit a store-conditional instruction in MODE .


<s> MSP430Subtarget & MSP430Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { ExtendedInsts = false ; HWMultMode = NoHWMult ; StringRef CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "msp430" ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( HWMultModeOption != NoHWMult ) HWMultMode = HWMultModeOption ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> static rtx shared_prop_gen ( rtx reg , propagate_mask pm , unsigned rep , void * data_ , bool vector ) { broadcast_data_t * data = ( broadcast_data_t * ) data_ ; if ( pm & PM_loop_begin ) { unsigned align = GET_MODE_ALIGNMENT ( GET_MODE ( reg ) ) / BITS_PER_UNIT ; oacc_bcast_align = MAX ( oacc_bcast_align , align ) ; data -> offset = ROUND_UP ( data -> offset , align ) ; data -> ptr = gen_reg_rtx ( Pmode ) ; return gen_adddi3 ( data -> ptr , data -> base , GEN_INT ( data -> offset ) ) ; } else if ( pm & PM_loop_end ) { rtx clobber = gen_rtx_CLOBBER ( GET_MODE ( data -> ptr ) , data -> ptr ) ; data -> ptr = NULL_RTX ; return clobber ; } else return nvptx_gen_shared_bcast ( reg , pm , rep , data , vector ) ; } </s>


<s> virtual const rvexRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> rtx s390_return_addr_rtx ( int count , rtx frame ATTRIBUTE_UNUSED ) { int offset ; rtx addr ; if ( ! TARGET_BACKCHAIN && count > 0 ) return NULL_RTX ; if ( count == 0 ) { if ( TARGET_CPU_ZARCH ) return get_hard_reg_initial_val ( Pmode , RETURN_REGNUM ) ; else { cfun_frame_layout . save_return_addr_p = true ; return gen_rtx_MEM ( Pmode , return_address_pointer_rtx ) ; } } if ( TARGET_PACKED_STACK ) offset = - 2 * UNITS_PER_LONG ; else offset = RETURN_REGNUM * UNITS_PER_LONG ; addr = plus_constant ( Pmode , frame , offset ) ; addr = memory_address ( Pmode , addr ) ; return gen_rtx_MEM ( Pmode , addr ) ; } </s>

Return an RTL expression representing the value of the return address for the frame COUNT steps up from the current frame . FRAME is the frame pointer of that frame .


<s> bool PPCAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , O ) ; case 'c' : break ; case 'L' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + 1 == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + 1 ) . isReg ( ) ) return true ; ++ OpNo ; break ; case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << "i" ; return false ; case 'x' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) ) return true ; unsigned Reg = MI -> getOperand ( OpNo ) . getReg ( ) ; if ( PPCInstrInfo :: isVRRegister ( Reg ) ) Reg = PPC :: VSX32 + ( Reg - PPC :: V0 ) ; else if ( PPCInstrInfo :: isVFRegister ( Reg ) ) Reg = PPC :: VSX32 + ( Reg - PPC :: VF0 ) ; const char * RegName ; RegName = PPCInstPrinter :: getRegisterName ( Reg ) ; RegName = PPCRegisterInfo :: stripRegisterPrefix ( RegName ) ; O << RegName ; return false ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>


<s>
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
MipsTargetLowering
::
getRegForInlineAsmConstraint
(
const
std
::
string
&
Constraint
,
MVT
VT
)
const
{
if
(
Constraint
.
size
(
)
==
1
)
{
switch
(
Constraint
[
0
]
)
{
case
'd'
:
case
'y'
:
case
'r'
:
if
(
VT
==
MVT
::
i32
||
VT
==
MVT
::
i16
||
VT
==
MVT
::
i8
)
{
if
(
Subtarget
->
inMips16Mode
(
)
)
return
std
::
make_pair
(
0U
,
&
Mips
::
CPU16RegsRegClass
)
;
return
std
::
make_pair
(
0U
,
&
Mips
::
GPR32RegClass
)
;
}
if
(
VT
==
MVT
::
i64
&&
!
HasMips64
)
return
std
::
make_pair
(
0U
,
&
Mips
::
GPR32RegClass
)
;
if
(
VT
==
MVT
::
i64
&&
HasMips64
)
return
std
::
make_pair
(
0U
,
&
Mips
::
GPR64RegClass
)
;
return
std
::
make_pair
(
0u
,
static_cast
<
const
TargetRegisterClass
*
>
(
0
)
)
;
case
'f'
:
if
(
VT
==
MVT
::
f32
)
return
std
::
make_pair
(
0U
,
&
Mips
::
FGR32RegClass
)
;
if
(
(
VT
==
MVT
::
f64
)
&&
(
!
Subtarget
->
isSingleFloat
(
)
)
)
{
if
(
Subtarget
->
isFP64bit
(
)
)
return
std
::
make_pair
(
0U
,
&
Mips
::
FGR64RegClass
)
;
return
std
::
make_pair
(
0U
,
&
Mips
::
AFGR64RegClass
)
;
}
break
;
case
'c'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
(
unsigned
)
Mips
::
T9
,
&
Mips
::
GPR32RegClass
)
;
assert
(
VT
==
MVT
::
i64
&&
"Unexpected type."
)
;
return
std
::
make_pair
(
(
unsigned
)
Mips
::
T9_64
,
&
Mips
::
GPR64RegClass
)
;
case
'l'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
(
unsigned
)
Mips
::
LO
,
&
Mips
::
LORegsRegClass
)
;
return
std
::
make_pair
(
(
unsigned
)
Mips
::
LO64
,
&
Mips
::
LORegs64RegClass
)
;
case
'x'
:
return
std
::
make_pair
(
0u
,
static_cast
<
const
TargetRegisterClass
*
>
(
0
)
)
;
}
}
return
TargetLowering
::
getRegForInlineAsmConstraint
(
Constraint
,
VT
)
;
}
</s>

Given a physical register constraint ( e.g .


<s>
void
PatmosInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
O
,
StringRef
Annot
)
{
printInstPrefix
(
MI
,
O
)
;
printInstruction
(
MI
,
O
)
;
if
(
!
isBundled
(
MI
)
&&
InBundle
)
{
O
<<
" }"
;
InBundle
=
false
;
}
printAnnotation
(
O
,
Annot
)
;
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s> static unsigned findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const X86RegisterInfo * TRI , bool Is64Bit ) { const MachineFunction * MF = MBB . getParent ( ) ; const Function * F = MF -> getFunction ( ) ; if ( ! F || MF -> getMMI ( ) . callsEHReturn ( ) ) return 0 ; const TargetRegisterClass & AvailableRegs = * TRI -> getGPRsForTailCall ( * MF ) ; unsigned Opc = MBBI -> getOpcode ( ) ; switch ( Opc ) { default : return 0 ; case TargetOpcode :: PATCHABLE_RET : case X86 :: RET : case X86 :: RETL : case X86 :: RETQ : case X86 :: RETIL : case X86 :: RETIQ : case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: TCRETURNmi64 : case X86 :: EH_RETURN : case X86 :: EH_RETURN64 : { SmallSet < uint16_t , 8 > Uses ; for ( unsigned i = 0 , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } for ( auto CS : AvailableRegs ) if ( ! Uses . count ( CS ) && CS != X86 :: RIP ) return CS ; } } return 0 ; } </s>

findDeadCallerSavedReg - Return a caller-saved register that is n't live when it reaches the `` return '' instruction .


<s> MachineInstr * SparcInstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , int FI ) const { if ( Ops . size ( ) != 1 ) return NULL ; unsigned OpNum = Ops [ 0 ] ; bool isFloat = false ; MachineInstr * NewMI = NULL ; switch ( MI -> getOpcode ( ) ) { case SP :: ORrr : if ( MI -> getOperand ( 1 ) . isReg ( ) && MI -> getOperand ( 1 ) . getReg ( ) == SP :: G0 && MI -> getOperand ( 0 ) . isReg ( ) && MI -> getOperand ( 2 ) . isReg ( ) ) { if ( OpNum == 0 ) NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( SP :: STri ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( MI -> getOperand ( 2 ) . getReg ( ) ) ; else NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( SP :: LDri ) , MI -> getOperand ( 0 ) . getReg ( ) ) . addFrameIndex ( FI ) . addImm ( 0 ) ; } break ; case SP :: FMOVS : isFloat = true ; case SP :: FMOVD : if ( OpNum == 0 ) { unsigned SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; bool isKill = MI -> getOperand ( 1 ) . isKill ( ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isFloat ? SP :: STFri : SP :: STDFri ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; } else { unsigned DstReg = MI -> getOperand ( 0 ) . getReg ( ) ; bool isDead = MI -> getOperand ( 0 ) . isDead ( ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isFloat ? SP :: LDFri : SP :: LDDFri ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( isDead ) ) . addFrameIndex ( FI ) . addImm ( 0 ) ; } break ; } return NewMI ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> bool X86FrameLowering :: enableShrinkWrapping ( const MachineFunction & MF ) const { return MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoUnwind ) || hasFP ( MF ) ; } </s>

Returns true if the target will correctly handle shrink wrapping .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Fix loop entry to simplify codegen"
;
}
</s>

getPassName - Return a nice clean name for a pass .

TVM
"Fix loop entry to simplify codegen"


<s> bool X86TargetLowering :: isVectorClearMaskLegal ( const SmallVectorImpl < int > & Mask , EVT VT ) const { return isShuffleMaskLegal ( Mask , VT ) ; } </s>


<s> Optional < DestSourcePair > Mips16InstrInfo :: isCopyInstrImpl ( const MachineInstr & MI ) const { if ( MI . isMoveReg ( ) ) return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 1 ) } ; return None ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


<s> bool isMachineVerifierClean ( ) const override { return false ; } </s>

Returns true if the target is expected to pass all machine verifier checks .


<s>
SDValue
VideoCore4TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
EVT
PtrVT
=
getPointerTy
(
)
;
SDLoc
dl
(
Op
)
;
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
VAARG
:
return
LowerVAARG
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
BR_JT
:
return
LowerBR_JT
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
{
const
GlobalValue
*
GV
=
cast
<
GlobalAddressSDNode
>
(
Op
)
->
getGlobal
(
)
;
return
DAG
.
getNode
(
VideoCore4ISD
::
GLOBAL
,
dl
,
PtrVT
,
DAG
.
getTargetGlobalAddress
(
GV
,
dl
,
PtrVT
)
)
;
}
case
ISD
::
FRAMEADDR
:
assert
(
false
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool SIAnnotateControlFlow :: runOnFunction ( Function & F ) { DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; DA = & getAnalysis < DivergenceAnalysis > ( ) ; for ( df_iterator < BasicBlock * > I = df_begin ( & F . getEntryBlock ( ) ) , E = df_end ( & F . getEntryBlock ( ) ) ; I != E ; ++ I ) { BasicBlock * BB = * I ; BranchInst * Term = dyn_cast < BranchInst > ( BB -> getTerminator ( ) ) ; if ( ! Term || Term -> isUnconditional ( ) ) { if ( isTopOfStack ( BB ) ) closeControlFlow ( BB ) ; continue ; } if ( I . nodeVisited ( Term -> getSuccessor ( 1 ) ) ) { if ( isTopOfStack ( BB ) ) closeControlFlow ( BB ) ; handleLoop ( Term ) ; continue ; } if ( isTopOfStack ( BB ) ) { PHINode * Phi = dyn_cast < PHINode > ( Term -> getCondition ( ) ) ; if ( Phi && Phi -> getParent ( ) == BB && isElse ( Phi ) ) { insertElse ( Term ) ; eraseIfUnused ( Phi ) ; continue ; } closeControlFlow ( BB ) ; } openIf ( Term ) ; } assert ( Stack . empty ( ) ) ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s>
void
assignValueToReg
(
Register
ValVReg
,
Register
PhysReg
,
CCValAssign
&
VA
)
override
{
assert
(
VA
.
isRegLoc
(
)
&&
"Value shouldn't be assigned to reg"
)
;
assert
(
VA
.
getLocReg
(
)
==
PhysReg
&&
"Assigning to the wrong reg?"
)
;
auto
ValSize
=
VA
.
getValVT
(
)
.
getSizeInBits
(
)
;
auto
LocSize
=
VA
.
getLocVT
(
)
.
getSizeInBits
(
)
;
assert
(
ValSize
<=
64
&&
"Unsupported value size"
)
;
assert
(
LocSize
<=
64
&&
"Unsupported location size"
)
;
markPhysRegUsed
(
PhysReg
)
;
if
(
ValSize
==
LocSize
)
{
MIRBuilder
.
buildCopy
(
ValVReg
,
PhysReg
)
;
}
else
{
assert
(
ValSize
<
LocSize
&&
"Extensions not supported"
)
;
auto
PhysRegToVReg
=
MIRBuilder
.
buildCopy
(
LLT
::
scalar
(
LocSize
)
,
PhysReg
)
;
MIRBuilder
.
buildTrunc
(
ValVReg
,
PhysRegToVReg
)
;
}
}
</s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .

ARM
"Value shouldn't be assigned to reg"
"Assigning to the wrong reg?"
64
"Unsupported value size"
64
"Unsupported location size"
"Extensions not supported"


<s> bool ARM64FastISel :: isTypeLegal ( Type * Ty , MVT & VT ) { EVT evt = TLI . getValueType ( Ty , true ) ; if ( evt == MVT :: Other || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; if ( VT == MVT :: f128 ) return false ; return TLI . isTypeLegal ( VT ) ; } </s>


<s> bool ARMBaseInstrInfo :: isSchedulingBoundary ( const MachineInstr * MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( MI -> isDebugValue ( ) ) return false ; if ( MI -> isTerminator ( ) || MI -> isLabel ( ) ) return true ; MachineBasicBlock :: const_iterator I = MI ; while ( ++ I != MBB -> end ( ) && I -> isDebugValue ( ) ) ; if ( I != MBB -> end ( ) && I -> getOpcode ( ) == ARM :: t2IT ) return true ; if ( MI -> definesRegister ( ARM :: SP ) ) return true ; return false ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> void HexagonPassConfig :: addPreEmitPass ( ) { bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) addPass ( createHexagonNewValueJump ( ) , false ) ; addPass ( createHexagonExpandPredSpillCode ( ) , false ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( createHexagonFixupHwLoops ( ) , false ) ; if ( EnableGenMux ) addPass ( createHexagonGenMux ( ) , false ) ; addPass ( createHexagonPacketizer ( ) , false ) ; } addPass ( createHexagonCallFrameInformation ( ) , false ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon


<s> void MBlazeInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { DebugLoc DL ; BuildMI ( MBB , MI , DL , get ( MBlaze :: NOP ) ) ; } </s>

Insert a noop into the instruction stream at the specified point .


"Error: check for a non-legal type in this operation\n"


<s>
__inline__
static
float
sh_media_FMAC_S
(
float
fg
,
float
fh
,
float
fq
)
{
float
res
;
__asm__
(
"fmac.s	%1, %2, %0"
:
"=f"
(
res
)
:
"f"
(
fg
)
,
"f"
(
fh
)
,
"0"
(
fq
)
)
;
return
res
;
}
</s>


"JIT relocation model must be set to static or default!"

runOnMachineFunction - Emit the function body .


<s> static rtx frv_legitimize_argument ( enum insn_code icode , int opnum , rtx arg ) { machine_mode mode = insn_data [ icode ] . operand [ opnum ] . mode ; if ( ( * insn_data [ icode ] . operand [ opnum ] . predicate ) ( arg , mode ) ) return arg ; else return copy_to_mode_reg ( mode , arg ) ; } </s>

Given that ARG is being passed as operand OPNUM to instruction ICODE , check whether ARG satisfies the operand 's constraints . If it does n't , copy ARG to a temporary register and return that . Otherwise return ARG itself .


<s> bool TPCMemorySize :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < TPCSubtarget > ( ) ; if ( ! Subtarget -> getTargetLowering ( ) -> getTargetMachine ( ) . Options . LocalVectorMemory ) { for ( auto & BB : MF ) { for ( auto & MI : BB ) { if ( TPCII :: isLookup ( MI . getDesc ( ) ) ) { Subtarget -> getFrameLowering ( ) -> setMaxVectorMemory ( Subtarget -> getDefaultSmallVLMSize ( ) ) ; break ; } } } } setMemorySize ( * MF . getFunction ( ) . getParent ( ) ) ; return true ; } </s>


<s> void ARCPassConfig :: addPreRegAlloc ( ) { addPass ( createARCExpandPseudosPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> bool Cpu0AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Cpu0MFI = MF . getInfo < Cpu0MachineFunctionInfo > ( ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>


<s> inline void X86EncodeLiteralsPass :: buildXor ( MachineInstr & MI , unsigned Index , uint64_t Operand ) { MachineBasicBlock * PMBB = MI . getParent ( ) ; MachineBasicBlock :: instr_iterator Iter = skip ( PMBB , Index ) ; int64_t Offset = MI . getOperand ( 3 ) . getImm ( ) ; unsigned XOROpc = getXorOpc ( MI ) ; addRegOffset ( BuildMI ( * PMBB , Iter , MI . getDebugLoc ( ) , TII -> get ( XOROpc ) ) , X86 :: RBP , true , Offset ) . addImm ( Operand ) ; } </s>

Build and insert Res = G_XOR Op0 , Op1 .


<s> TargetTransformInfo FPGATargetMachine :: getTargetTransformInfo ( const Function & F ) { return TargetTransformInfo ( FPGATTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> static tree ix86_builtin_reciprocal ( tree fndecl ) { switch ( DECL_FUNCTION_CODE ( fndecl ) ) { case IX86_BUILTIN_SQRTPS_NR : return ix86_get_builtin ( IX86_BUILTIN_RSQRTPS_NR ) ; case IX86_BUILTIN_SQRTPS_NR256 : return ix86_get_builtin ( IX86_BUILTIN_RSQRTPS_NR256 ) ; default : return NULL_TREE ; } } </s>

Returns a code for a target-specific builtin that implements reciprocal of the function , or NULL_TREE if not available .


<s> SDValue MipsSETargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; SDValue Val ; switch ( N -> getOpcode ( ) ) { case ISD :: ADDE : return performADDECombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SUBE : return performSUBECombine ( N , DAG , DCI , Subtarget ) ; case ISD :: MUL : return performMULCombine ( N , DAG , DCI , this ) ; case ISD :: SHL : return performSHLCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SRA : return performSRACombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SRL : return performSRLCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: VSELECT : return performVSELECTCombine ( N , DAG ) ; case ISD :: SETCC : { Val = performSETCCCombine ( N , DAG ) ; break ; } } if ( Val . getNode ( ) ) return Val ; return MipsTargetLowering :: PerformDAGCombine ( N , DCI ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips Mips ISD::ADDE ISD::SUBE ISD::MUL ISD::SHL ISD::SRA ISD::SRL ISD::VSELECT ISD::SETCC Mips


<s> static void find_regmode_weight ( basic_block b , machine_mode mode ) { rtx_insn * insn , * next_tail , * head , * tail ; get_ebb_head_tail ( b , b , & head , & tail ) ; next_tail = NEXT_INSN ( tail ) ; for ( insn = head ; insn != next_tail ; insn = NEXT_INSN ( insn ) ) { if ( ! INSN_P ( insn ) ) continue ; if ( mode == SFmode ) INSN_REGMODE_WEIGHT ( insn , mode ) = find_insn_regmode_weight ( insn , mode ) + 2 * find_insn_regmode_weight ( insn , DFmode ) ; else if ( mode == SImode ) INSN_REGMODE_WEIGHT ( insn , mode ) = find_insn_regmode_weight ( insn , mode ) + 2 * find_insn_regmode_weight ( insn , DImode ) ; } } </s>

Calculate regmode weights for all insns of a basic block .


<s> int cr16_hard_regno_mode_ok ( int regno , machine_mode mode ) { if ( ( GET_MODE_SIZE ( mode ) >= 4 ) && ( regno == 11 ) ) return 0 ; if ( mode == DImode || mode == DFmode ) { if ( ( regno > 8 ) || ( regno & 1 ) ) return 0 ; return 1 ; } if ( ( TARGET_INT32 ) && ( ( regno >= 12 ) && ( GET_MODE_SIZE ( mode ) < 4 ) ) ) return 0 ; if ( GET_MODE_CLASS ( mode ) == MODE_CC ) return 0 ; return 1 ; } </s>

Return 1 if hard register REGNO can hold a value of machine-mode MODE .


<s> bool ix86_expand_int_addcc ( rtx operands [ ] ) { enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; rtx flags ; rtx ( * insn ) ( machine_mode , rtx , rtx , rtx , rtx , rtx ) ; rtx compare_op ; rtx val = const0_rtx ; bool fpcmp = false ; machine_mode mode ; rtx op0 = XEXP ( operands [ 1 ] , 0 ) ; rtx op1 = XEXP ( operands [ 1 ] , 1 ) ; if ( operands [ 3 ] != const1_rtx && operands [ 3 ] != constm1_rtx ) return false ; if ( ! ix86_expand_carry_flag_compare ( code , op0 , op1 , & compare_op ) ) return false ; code = GET_CODE ( compare_op ) ; flags = XEXP ( compare_op , 0 ) ; if ( GET_MODE ( flags ) == CCFPmode ) { fpcmp = true ; code = ix86_fp_compare_code_to_integer ( code ) ; } if ( code != LTU ) { val = constm1_rtx ; if ( fpcmp ) PUT_CODE ( compare_op , reverse_condition_maybe_unordered ( GET_CODE ( compare_op ) ) ) ; else PUT_CODE ( compare_op , reverse_condition ( GET_CODE ( compare_op ) ) ) ; } mode = GET_MODE ( operands [ 0 ] ) ; if ( ( code == LTU ) == ( operands [ 3 ] == constm1_rtx ) ) insn = gen_sub3_carry ; else insn = gen_add3_carry ; emit_insn ( insn ( mode , operands [ 0 ] , operands [ 2 ] , val , flags , compare_op ) ) ; return true ; } </s>

Expand conditional increment or decrement using adb/sbb instructions . The default case using setcc followed by the conditional move can be done by generic code .


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , bool IsLittle , const TargetOptions & Options ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , ARMProcClass ( None ) , stackAlignment ( 4 ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( Options ) , TargetABI ( ARM_ABI_UNKNOWN ) { initializeEnvironment ( ) ; resetSubtargetFeatures ( CPU , FS ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> static bool rs6000_maybe_emit_fp_cmove ( rtx dest , rtx op , rtx true_cond , rtx false_cond ) { enum rtx_code code = GET_CODE ( op ) ; rtx op0 = XEXP ( op , 0 ) ; rtx op1 = XEXP ( op , 1 ) ; machine_mode compare_mode = GET_MODE ( op0 ) ; machine_mode result_mode = GET_MODE ( dest ) ; rtx compare_rtx ; rtx cmove_rtx ; rtx clobber_rtx ; if ( ! can_create_pseudo_p ( ) ) return 0 ; if ( ! ( compare_mode == result_mode || ( compare_mode == SFmode && result_mode == DFmode ) || ( compare_mode == DFmode && result_mode == SFmode ) ) ) return false ; switch ( code ) { case EQ : case GE : case GT : break ; case NE : case LT : case LE : code = swap_condition ( code ) ; std :: swap ( op0 , op1 ) ; break ; default : return false ; } compare_rtx = gen_rtx_fmt_ee ( code , CCFPmode , op0 , op1 ) ; cmove_rtx = gen_rtx_SET ( dest , gen_rtx_IF_THEN_ELSE ( result_mode , compare_rtx , true_cond , false_cond ) ) ; clobber_rtx = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_SCRATCH ( V2DImode ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , cmove_rtx , clobber_rtx ) ) ) ; return true ; } </s>

Possibly emit a floating point conditional move by generating a compare that sets a mask instruction and a XXSEL select instruction . Move TRUE_COND to DEST if OP of the operands of the last comparison is nonzero/true , FALSE_COND if it is zero/false . Return false if the operation can not be generated , and true if we could generate the instruction .


<s> RegisterAggr & RegisterAggr :: clear ( RegisterRef RR ) { if ( PhysicalRegisterInfo :: isRegMaskId ( RR . Reg ) ) { const uint32_t * MB = PRI . getRegMaskBits ( RR . Reg ) ; for ( unsigned i = 1 , e = PRI . getTRI ( ) . getNumRegs ( ) ; i != e ; ++ i ) { if ( MB [ i / 32 ] & ( 1u << ( i % 32 ) ) ) continue ; clear ( RegisterRef ( i , LaneBitmask :: getAll ( ) ) ) ; } return * this ; } RegisterRef NR = PRI . normalize ( RR ) ; auto F = Masks . find ( NR . Reg ) ; if ( F == Masks . end ( ) ) return * this ; LaneBitmask NewM = F -> second & ~ NR . Mask ; if ( NewM . none ( ) ) Masks . erase ( F ) ; else F -> second = NewM ; return * this ; } </s>


<s>
static
rtx
m32c_function_arg
(
cumulative_args_t
ca_v
,
const
function_arg_info
&
arg
)
{
CUMULATIVE_ARGS
*
ca
=
get_cumulative_args
(
ca_v
)
;
rtx
rv
=
NULL_RTX
;
fprintf
(
stderr
,
"func_arg %d (%s, %d)\n"
,
ca
->
parm_num
,
mode_name
[
arg
.
mode
]
,
arg
.
named
)
;
debug_tree
(
arg
.
type
)
;
if
(
arg
.
end_marker_p
(
)
)
return
GEN_INT
(
0
)
;
if
(
ca
->
force_mem
||
!
arg
.
named
)
{
fprintf
(
stderr
,
"func arg: force %d named %d, mem\n"
,
ca
->
force_mem
,
arg
.
named
)
;
return
NULL_RTX
;
}
if
(
arg
.
type
&&
INTEGRAL_TYPE_P
(
arg
.
type
)
&&
POINTER_TYPE_P
(
arg
.
type
)
)
return
NULL_RTX
;
if
(
arg
.
aggregate_type_p
(
)
)
return
NULL_RTX
;
switch
(
ca
->
parm_num
)
{
case
1
:
if
(
GET_MODE_SIZE
(
arg
.
mode
)
==
1
||
GET_MODE_SIZE
(
arg
.
mode
)
==
2
)
rv
=
gen_rtx_REG
(
arg
.
mode
,
TARGET_A16
R1_REGNO
:
R0_REGNO
)
;
break
;
case
2
:
if
(
TARGET_A16
&&
GET_MODE_SIZE
(
arg
.
mode
)
==
2
)
rv
=
gen_rtx_REG
(
arg
.
mode
,
R2_REGNO
)
;
break
;
}
debug_rtx
(
rv
)
;
return
rv
;
}
</s>

Implements FUNCTION_ARG . Arguments are passed partly in registers , partly on stack . If our function returns a struct , a pointer to a buffer for it is at the top of the stack ( last thing pushed ) . The first few real arguments may be in registers as follows : R8C/M16C : arg1 in r1 if it 's QI or HI ( else it 's pushed on stack ) arg2 in r2 if it 's HI ( else pushed on stack ) rest on stack M32C : arg1 in r0 if it 's QI or HI ( else it 's pushed on stack ) rest on stack Structs are not passed in registers , even if they fit . Only integer and pointer types are passed in registers . Note that when arg1 does n't fit in r1 , arg2 may still be passed in r2 if it fits .


<s>
void
ARMTTIImpl
::
getUnrollingPreferences
(
Loop
*
L
,
ScalarEvolution
&
SE
,
TTI
::
UnrollingPreferences
&
UP
)
{
if
(
!
ST
->
isMClass
(
)
)
return
BasicTTIImplBase
::
getUnrollingPreferences
(
L
,
SE
,
UP
)
;
UP
.
OptSizeThreshold
=
0
;
UP
.
PartialOptSizeThreshold
=
0
;
if
(
L
->
getHeader
(
)
->
getParent
(
)
->
hasOptSize
(
)
)
return
;
if
(
!
ST
->
isThumb2
(
)
)
return
;
SmallVector
<
BasicBlock
*
,
4
>
ExitingBlocks
;
L
->
getExitingBlocks
(
ExitingBlocks
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Loop has:\n"
<<
"Blocks: "
<<
L
->
getNumBlocks
(
)
<<
"\n"
<<
"Exit blocks: "
<<
ExitingBlocks
.
size
(
)
<<
"\n"
)
;
if
(
ExitingBlocks
.
size
(
)
>
2
)
return
;
if
(
ST
->
hasBranchPredictor
(
)
&&
L
->
getNumBlocks
(
)
>
4
)
return
;
unsigned
Cost
=
0
;
for
(
auto
*
BB
:
L
->
getBlocks
(
)
)
{
for
(
auto
&
I
:
*
BB
)
{
if
(
I
.
getType
(
)
->
isVectorTy
(
)
)
return
;
if
(
isa
<
CallInst
>
(
I
)
||
isa
<
InvokeInst
>
(
I
)
)
{
if
(
const
Function
*
F
=
cast
<
CallBase
>
(
I
)
.
getCalledFunction
(
)
)
{
if
(
!
isLoweredToCall
(
F
)
)
continue
;
}
return
;
}
SmallVector
<
const
Value
*
,
4
>
Operands
(
I
.
value_op_begin
(
)
,
I
.
value_op_end
(
)
)
;
Cost
+=
getUserCost
(
&
I
,
Operands
,
TargetTransformInfo
::
TCK_SizeAndLatency
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Cost of loop: "
<<
Cost
<<
"\n"
)
;
UP
.
Partial
=
true
;
UP
.
Runtime
=
true
;
UP
.
UpperBound
=
true
;
UP
.
UnrollRemainder
=
true
;
UP
.
DefaultUnrollRuntimeCount
=
4
;
UP
.
UnrollAndJam
=
true
;
UP
.
UnrollAndJamInnerLoopThreshold
=
60
;
if
(
Cost
<
12
)
UP
.
Force
=
true
;
}
</s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> static bool isNodeHidden ( const SUnit * Node , const ScheduleDAGPostRA * G ) { return ( Node -> NumPreds > 10 || Node -> NumSuccs > 10 ) ; } </s>

Do not print nodes that are part of a pi-block separately .


<s> bool runOnMachineFunction ( MachineFunction & F ) override { bool Changed = false ; Subtarget = & F . getSubtarget < SparcSubtarget > ( ) ; F . getRegInfo ( ) . invalidateLiveness ( ) ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; return Changed ; } </s>


<s> static void rs6000_print_isa_options ( FILE * file , int indent , const char * string , HOST_WIDE_INT flags ) { rs6000_print_options_internal ( file , indent , string , flags , "-m" , & rs6000_opt_masks [ 0 ] , ARRAY_SIZE ( rs6000_opt_masks ) ) ; } </s>

Helper function to print the current isa options on a line .


<s> void SystemZTTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP ) { bool HasCall = false ; unsigned NumStores = 0 ; for ( auto & BB : L -> blocks ( ) ) for ( auto & I : * BB ) { if ( isa < CallInst > ( & I ) || isa < InvokeInst > ( & I ) ) { if ( const Function * F = cast < CallBase > ( I ) . getCalledFunction ( ) ) { if ( isLoweredToCall ( F ) ) HasCall = true ; if ( F -> getIntrinsicID ( ) == Intrinsic :: memcpy || F -> getIntrinsicID ( ) == Intrinsic :: memset ) NumStores ++ ; } else { HasCall = true ; } } if ( isa < StoreInst > ( & I ) ) { Type * MemAccessTy = I . getOperand ( 0 ) -> getType ( ) ; NumStores += getMemoryOpCost ( Instruction :: Store , MemAccessTy , None , 0 ) ; } } unsigned const Max = ( NumStores ? ( 12 / NumStores ) : UINT_MAX ) ; if ( HasCall ) { UP . FullUnrollMaxCount = Max ; UP . MaxCount = 1 ; return ; } UP . MaxCount = Max ; if ( UP . MaxCount <= 1 ) return ; UP . Partial = UP . Runtime = true ; UP . PartialThreshold = 75 ; UP . DefaultUnrollRuntimeCount = 4 ; UP . AllowExpensiveTripCount = true ; UP . Force = true ; } </s>