<s> rtx get_unaligned_address ( rtx ref , int extra_offset ) { rtx base ; HOST_WIDE_INT offset = 0 ; gcc_assert ( GET_CODE ( ref ) == MEM ) ; if ( reload_in_progress && ! memory_address_p ( GET_MODE ( ref ) , XEXP ( ref , 0 ) ) ) { base = find_replacement ( & XEXP ( ref , 0 ) ) ; gcc_assert ( memory_address_p ( GET_MODE ( ref ) , base ) ) ; } else base = XEXP ( ref , 0 ) ; if ( GET_CODE ( base ) == PLUS ) offset += INTVAL ( XEXP ( base , 1 ) ) , base = XEXP ( base , 0 ) ; return plus_constant ( base , offset + extra_offset ) ; } </s>

Similar , but just get the address . Handle the two reload cases . Add EXTRA_OFFSET to the address we return .


<s> bool aarch64_sve_cnt_immediate_p ( rtx x ) { poly_int64 value ; return poly_int_rtx_p ( x , & value ) && aarch64_sve_cnt_immediate_p ( value ) ; } </s>


<s> inline bool function_base :: has_merge_operand_p ( ) const { return true ; } </s>

We choose to return true by default since most of the intrinsics use has merge operand .


<s> void cris_init_expanders ( ) { } </s>

The INIT_EXPANDERS worker sets the per-function-data initializer and mark functions .


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsPCRel ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { unsigned Idx = IsLittleEndian ? i : 3 - i ; Data [ Offset + Idx ] |= uint8_t ( ( Value >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool pbsada_insn_ra_rb_dep_reg_p ( rtx pbsada_insn , rtx def_reg ) { rtx unspec_rtx = SET_SRC ( PATTERN ( pbsada_insn ) ) ; gcc_assert ( GET_CODE ( unspec_rtx ) == UNSPEC ) ; rtx pbsada_ra = XVECEXP ( unspec_rtx , 0 , 0 ) ; rtx pbsada_rb = XVECEXP ( unspec_rtx , 0 , 1 ) ; if ( rtx_equal_p ( def_reg , pbsada_ra ) || rtx_equal_p ( def_reg , pbsada_rb ) ) return true ; return false ; } </s>

Determine if the latency is occured when the consumer PBSADA_INSN uses the value of DEF_REG in its Ra or Rb fields .


<s> const X86RegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static int m32c_leaf_function_p ( void ) { int rv ; push_topmost_sequence ( ) ; rv = leaf_function_p ( ) ; pop_topmost_sequence ( ) ; return rv ; } </s>

Returns TRUE if the current function is a leaf , and thus we can determine which registers an interrupt function really needs to save . The logic below is mostly about finding the insn sequence that 's the function , versus any sequence that might be open for the current insn .


<s>
void
HexagonInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
OS
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
)
{
assert
(
HexagonMCInstrInfo
::
isBundle
(
*
MI
)
)
;
assert
(
HexagonMCInstrInfo
::
bundleSize
(
*
MI
)
<=
HEXAGON_PACKET_SIZE
)
;
assert
(
HexagonMCInstrInfo
::
bundleSize
(
*
MI
)
>
0
)
;
HasExtender
=
false
;
for
(
auto
const
&
I
:
HexagonMCInstrInfo
::
bundleInstructions
(
*
MI
)
)
{
MCInst
const
&
MCI
=
*
I
.
getInst
(
)
;
if
(
HexagonMCInstrInfo
::
isDuplex
(
MII
,
MCI
)
)
{
printInstruction
(
MCI
.
getOperand
(
1
)
.
getInst
(
)
,
OS
)
;
OS
<<
'\v'
;
HasExtender
=
false
;
printInstruction
(
MCI
.
getOperand
(
0
)
.
getInst
(
)
,
OS
)
;
}
else
printInstruction
(
&
MCI
,
OS
)
;
setExtender
(
MCI
)
;
OS
<<
"\n"
;
}
auto
Separator
=
""
;
if
(
HexagonMCInstrInfo
::
isInnerLoop
(
*
MI
)
)
{
OS
<<
Separator
;
Separator
=
" "
;
MCInst
ME
;
ME
.
setOpcode
(
Hexagon
::
ENDLOOP0
)
;
printInstruction
(
&
ME
,
OS
)
;
}
if
(
HexagonMCInstrInfo
::
isOuterLoop
(
*
MI
)
)
{
OS
<<
Separator
;
Separator
=
" "
;
MCInst
ME
;
ME
.
setOpcode
(
Hexagon
::
ENDLOOP1
)
;
printInstruction
(
&
ME
,
OS
)
;
}
}
</s>

Print the specified MCInst to the specified raw_ostream .

Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
0
Hexagon
Hexagon
1
0
"\n"
""
Hexagon
" "
Hexagon::ENDLOOP0
Hexagon
" "
Hexagon::ENDLOOP1


<s>
void
output_ascii
(
FILE
*
file
,
const
char
*
p
,
int
size
)
{
int
i
;
int
chars_output
;
unsigned
char
partial_output
[
16
]
;
fputs
(
"\t.STRING \""
,
file
)
;
chars_output
=
0
;
for
(
i
=
0
;
i
<
size
;
i
+=
4
)
{
int
co
=
0
;
int
io
=
0
;
for
(
io
=
0
,
co
=
0
;
io
<
MIN
(
4
,
size
i
)
;
io
++
)
{
register
unsigned
int
c
=
(
unsigned
char
)
p
[
i
+
io
]
;
if
(
c
==
'\"'
||
c
==
'\\'
)
partial_output
[
co
++
]
=
'\\'
;
if
(
c
>=
' '
&&
c
<
0177
)
partial_output
[
co
++
]
=
c
;
else
{
unsigned
int
hexd
;
partial_output
[
co
++
]
=
'\\'
;
partial_output
[
co
++
]
=
'x'
;
hexd
=
c
/
16
0
+
'0'
;
if
(
hexd
>
'9'
)
hexd
-=
'9'
'a'
+
1
;
partial_output
[
co
++
]
=
hexd
;
hexd
=
c
%
16
0
+
'0'
;
if
(
hexd
>
'9'
)
hexd
-=
'9'
'a'
+
1
;
partial_output
[
co
++
]
=
hexd
;
}
}
if
(
chars_output
+
co
>
243
)
{
fputs
(
"\"\n\t.STRING \""
,
file
)
;
chars_output
=
0
;
}
fwrite
(
partial_output
,
1
,
(
size_t
)
co
,
file
)
;
chars_output
+=
co
;
co
=
0
;
}
fputs
(
"\"\n"
,
file
)
;
}
</s>

Output an assembler pseudo-op to write an ASCII string of N characters starting at P to FILE . On the RS/6000 , we have to do this using the .byte operation and write out special characters outside the quoted string . Also , the assembler is broken ; very long strings are truncated , so we must artificially break them up early .


<s> static bool str_prefix_p ( const char * str , const char * prefix ) { return 0 == strncmp ( str , prefix , strlen ( prefix ) ) ; } </s>

Return true iff STR starts with PREFIX .


<s> bool Thumb1RegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; BuildMI ( MBB , I , DL , TII . get ( ARM :: tMOVtgpr2gpr ) ) . addReg ( ARM :: R12 , RegState :: Define ) . addReg ( Reg , RegState :: Kill ) ; bool done = false ; for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { for ( unsigned i = 0 , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == ARM :: R12 ) { UseMI = II ; done = true ; break ; } } } BuildMI ( MBB , UseMI , DL , TII . get ( ARM :: tMOVgpr2tgpr ) ) . addReg ( Reg , RegState :: Define ) . addReg ( ARM :: R12 , RegState :: Kill ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .


"WebAssembly should not have callee-saved registers"

"Functions needing frame pointers not yet supported"

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


"MIa must load from or modify a memory location"

"MIb must load from or modify a memory location"

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> bool aarch64_madd_needs_nop ( rtx_insn * insn ) { enum attr_type attr_type ; rtx_insn * prev ; rtx body ; if ( ! aarch64_fix_a53_err835769 ) return false ; if ( recog_memoized ( insn ) < 0 ) return false ; attr_type = get_attr_type ( insn ) ; if ( ! is_madd_op ( attr_type ) ) return false ; prev = aarch64_prev_real_insn ( insn ) ; extract_constrain_insn_cached ( insn ) ; if ( ! prev || ! has_memory_op ( prev ) ) return false ; body = single_set ( prev ) ; if ( GET_MODE ( recog_data . operand [ 0 ] ) == DImode && ( ! body || ! dep_between_memop_and_curr ( body ) ) ) return true ; return false ; } </s>

When working around the Cortex-A53 erratum 835769 , given rtx_insn INSN , return true if it is a 64-bit multiply-accumulate instruction and has a preceding memory instruction such that a NOP should be inserted between them .


<s> SDValue HSAILTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , SDLoc dl , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; HSAILMachineFunctionInfo * FuncInfo = MF . getInfo < HSAILMachineFunctionInfo > ( ) ; HSAILParamManager & PM = FuncInfo -> getParamManager ( ) ; const Function * F = MF . getFunction ( ) ; const FunctionType * funcType = F -> getFunctionType ( ) ; SmallVector < SDValue , 6 > RetOps ; RetOps . push_back ( Chain ) ; const DataLayout & DL = F -> getParent ( ) -> getDataLayout ( ) ; Type * type = funcType -> getReturnType ( ) ; if ( ! type -> isVoidTy ( ) ) { Mangler Mang ; const char * SymName = PM . getParamName ( PM . addReturnParam ( type , PM . mangleArg ( & Mang , F -> getName ( ) , DL ) ) ) ; MVT ArgPtrVT = getPointerTy ( DL , HSAILAS :: ARG_ADDRESS ) ; SDValue RetVariable = DAG . getTargetExternalSymbol ( SymName , ArgPtrVT ) ; AAMDNodes MD ; unsigned ArgNo = 0 ; LowerArgument ( Chain , SDValue ( ) , false , nullptr , & Outs , dl , DAG , & RetOps , ArgNo , type , HSAILAS :: ARG_ADDRESS , nullptr , RetVariable , & OutVals , false , MD ) ; Chain = DAG . getNode ( ISD :: TokenFactor , dl , MVT :: Other , RetOps ) ; } return DAG . getNode ( HSAILISD :: RET , dl , MVT :: Other , Chain ) ; } </s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .

HSAIL HSAIL ISD::OutputArg HSAIL HSAIL HSAIL 6 HSAILAS::ARG_ADDRESS 0 HSAILAS::ARG_ADDRESS ISD::TokenFactor MVT::Other HSAILISD::RET MVT::Other


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> MachineBasicBlock :: instr_iterator skip ( MachineBasicBlock * MBB , unsigned Index ) { auto I = MBB -> instr_begin ( ) ; auto E = MBB -> instr_end ( ) ; unsigned Cur = 0 ; while ( I != E && Cur != Index ) ++ I , ++ Cur ; return ++ I ; } </s>

Advance the Cursor position by the given number of bytes .


<s> bool SIInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock & MBB = * MI -> getParent ( ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; switch ( MI -> getOpcode ( ) ) { default : return AMDGPUInstrInfo :: expandPostRAPseudo ( MI ) ; case AMDGPU :: SI_CONSTDATA_PTR : { unsigned Reg = MI -> getOperand ( 0 ) . getReg ( ) ; unsigned RegLo = RI . getSubReg ( Reg , AMDGPU :: sub0 ) ; unsigned RegHi = RI . getSubReg ( Reg , AMDGPU :: sub1 ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: S_GETPC_B64 ) , Reg ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: S_ADD_U32 ) , RegLo ) . addReg ( RegLo ) . addTargetIndex ( AMDGPU :: TI_CONSTDATA_START ) . addReg ( AMDGPU :: SCC , RegState :: Define | RegState :: Implicit ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: S_ADDC_U32 ) , RegHi ) . addReg ( RegHi ) . addImm ( 0 ) . addReg ( AMDGPU :: SCC , RegState :: Define | RegState :: Implicit ) . addReg ( AMDGPU :: SCC , RegState :: Implicit ) ; MI -> eraseFromParent ( ) ; break ; } } return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s>
SDValue
WDC65816TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

WDC65816
WDC
"Should not custom lower this!"
ISD::GlobalAddress


<s> bool AMDGPUAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , O ) ; case 'r' : break ; } } AMDGPUInstPrinter :: printRegOperand ( MI -> getOperand ( OpNo ) . getReg ( ) , O , * TM . getSubtargetImpl ( * MF -> getFunction ( ) ) -> getRegisterInfo ( ) ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static rtx pru_add_to_sp ( int addendum , const enum reg_note kind ) { return pru_add3_frame_adjust ( stack_pointer_rtx , stack_pointer_rtx , addendum , kind ) ; } </s>

Add a const_int to the stack pointer register .


<s> void mt_set_memflags ( rtx ref ) { rtx insn ; int in_struct_p , volatile_p ; if ( GET_CODE ( ref ) != MEM ) return ; in_struct_p = MEM_IN_STRUCT_P ( ref ) ; volatile_p = MEM_VOLATILE_P ( ref ) ; if ( ! in_struct_p && ! volatile_p ) return ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) mt_set_memflags_1 ( insn , in_struct_p , volatile_p ) ; } </s>

Look for any MEMs in the current sequence of insns and set the in-struct , unchanging , and volatile flags from the flags in REF . If REF is not a MEM , do n't do anything .


<s> bool NVPTXTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty ) const { if ( AM . BaseGV ) { if ( AM . BaseOffs || AM . HasBaseReg || AM . Scale ) return false ; return true ; } switch ( AM . Scale ) { case 0 : break ; case 1 : if ( AM . HasBaseReg ) return false ; break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s>
bool
FixupLEAPass
::
runOnMachineFunction
(
MachineFunction
&
Func
)
{
MF
=
&
Func
;
TM
=
&
Func
.
getTarget
(
)
;
const
X86Subtarget
&
ST
=
TM
->
getSubtarget
<
X86Subtarget
>
(
)
;
if
(
!
ST
.
LEAusesAG
(
)
&&
!
ST
.
slowLEA
(
)
)
return
false
;
TII
=
static_cast
<
const
X86InstrInfo
*
>
(
TM
->
getInstrInfo
(
)
)
;
DEBUG
(
dbgs
(
)
<<
"Start X86FixupLEAs\n"
;
)
;
for
(
MachineFunction
::
iterator
I
=
Func
.
begin
(
)
,
E
=
Func
.
end
(
)
;
I
!=
E
;
++
I
)
processBasicBlock
(
Func
,
I
)
;
DEBUG
(
dbgs
(
)
<<
"End X86FixupLEAs\n"
;
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> void SparcPassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( & getSparcTargetMachine ( ) ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> int const_ok_for_arm ( HOST_WIDE_INT i ) { int lowbit ; if ( ( i & ~ ( unsigned HOST_WIDE_INT ) 0xffffffff ) != 0 && ( ( i & ~ ( unsigned HOST_WIDE_INT ) 0xffffffff ) != ( ( ~ ( unsigned HOST_WIDE_INT ) 0 ) & ~ ( unsigned HOST_WIDE_INT ) 0xffffffff ) ) ) return FALSE ; i &= ( unsigned HOST_WIDE_INT ) 0xffffffff ; if ( ( i & ~ ( unsigned HOST_WIDE_INT ) 0xff ) == 0 ) return TRUE ; lowbit = ( ffs ( ( int ) i ) - 1 ) & ~ 1 ; if ( ( i & ~ ( ( ( unsigned HOST_WIDE_INT ) 0xff ) << lowbit ) ) == 0 ) return TRUE ; else if ( lowbit <= 4 && ( ( i & ~ 0xc000003f ) == 0 || ( i & ~ 0xf000000f ) == 0 || ( i & ~ 0xfc000003 ) == 0 ) ) return TRUE ; return FALSE ; } </s>

Return TRUE if int I is a valid immediate ARM constant .


<s> void nds32_asm_file_start_for_isr ( void ) { int i ; for ( i = 0 ; i < NDS32_N_ISR_VECTORS ; i ++ ) { nds32_isr_vectors [ i ] . category = NDS32_ISR_NONE ; strcpy ( nds32_isr_vectors [ i ] . func_name , "" ) ; nds32_isr_vectors [ i ] . save_reg = NDS32_PARTIAL_SAVE ; nds32_isr_vectors [ i ] . nested_type = NDS32_NOT_NESTED ; nds32_isr_vectors [ i ] . total_n_vectors = 0 ; strcpy ( nds32_isr_vectors [ i ] . nmi_name , "" ) ; strcpy ( nds32_isr_vectors [ i ] . warm_name , "" ) ; } } </s>

A helper function to handle isr stuff at the beginning of asm file .


<s> void AArch64AsmPrinter :: emitEndOfAsmFile ( Module & M ) { EmitHwasanMemaccessSymbols ( M ) ; const Triple & TT = TM . getTargetTriple ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; auto Stubs = MMIMacho . getAuthGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( OutContext . getMachOSection ( "__DATA" , "__auth_ptr" , MachO :: S_REGULAR , SectionKind :: getMetadata ( ) ) ) ; emitAlignment ( Align ( 8 ) ) ; for ( auto & Stub : Stubs ) emitAuthenticatedPointer ( * OutStreamer , Stub . first , Stub . second ) ; OutStreamer -> AddBlankLine ( ) ; } OutStreamer -> emitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } emitStackMaps ( SM ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


Emit the relocation to tie the next instruction to a previous instruction that loads up an external address . This is used to do the PCREL_OPT optimization . Note , the label is generated after the PLD of the got pc-relative address to allow for the assembler to insert NOPs before the PLD instruction . The operand is a constant integer that is the label number .


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT ) const override { return MVT :: i8 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s>
static
void
nvptx_init_axis_predicate
(
FILE
*
file
,
int
regno
,
const
char
*
name
)
{
fprintf
(
file
,
"\t{\n"
)
;
fprintf
(
file
,
"\t\t.reg.u32\t%%%s;\n"
,
name
)
;
fprintf
(
file
,
"\t\tmov.u32\t%%%s, %%tid.%s;\n"
,
name
,
name
)
;
fprintf
(
file
,
"\t\tsetp.ne.u32\t%%r%d, %%%s, 0;\n"
,
regno
,
name
)
;
fprintf
(
file
,
"\t}\n"
)
;
}
</s>

Emit code to initialize the REGNO predicate register to indicate whether we are not lane zero on the NAME axis .


<s> void arm_emit_call_insn ( rtx pat , rtx addr , bool sibcall ) { rtx insn ; insn = emit_call_insn ( pat ) ; if ( TARGET_VXWORKS_RTP && flag_pic && ! sibcall && GET_CODE ( addr ) == SYMBOL_REF && ( SYMBOL_REF_DECL ( addr ) ? ! targetm . binds_local_p ( SYMBOL_REF_DECL ( addr ) ) : ! SYMBOL_REF_LOCAL_P ( addr ) ) ) { require_pic_register ( NULL_RTX , false ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , cfun -> machine -> pic_reg ) ; } if ( TARGET_AAPCS_BASED ) { rtx * fusage = & CALL_INSN_FUNCTION_USAGE ( insn ) ; clobber_reg ( fusage , gen_rtx_REG ( word_mode , IP_REGNUM ) ) ; } } </s>

Emit a call instruction with pattern PAT . ADDR is the address of the call target .


<s> virtual SMLoc getStartLoc ( ) const LLVM_OVERRIDE { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> const TargetRegisterClass * ARMTargetLowering :: getRegClassFor ( MVT VT , bool isDivergent ) const { ( void ) isDivergent ; if ( Subtarget -> hasNEON ( ) || Subtarget -> hasMVEIntegerOps ( ) ) { if ( VT == MVT :: v4i64 ) return & ARM :: QQPRRegClass ; if ( VT == MVT :: v8i64 ) return & ARM :: QQQQPRRegClass ; } return TargetLowering :: getRegClassFor ( VT ) ; } </s>

Return the register class that should be used for the specified value type .

ARM ARM MVT::v4i64 ARM::QQPRRegClass MVT::v8i64 ARM::QQQQPRRegClass


<s> EVT X86TargetLowering :: getTypeForExtReturn ( LLVMContext & Context , EVT VT , ISD :: NodeType ExtendKind ) const { MVT ReturnMVT = MVT :: i32 ; bool Darwin = Subtarget . getTargetTriple ( ) . isOSDarwin ( ) ; if ( VT == MVT :: i1 || ( ! Darwin && ( VT == MVT :: i8 || VT == MVT :: i16 ) ) ) { ReturnMVT = MVT :: i8 ; } EVT MinVT = getRegisterType ( Context , ReturnMVT ) ; return VT . bitsLT ( MinVT ) ? MinVT : VT ; } </s>

Return the type that should be used to zero or sign extend a zeroext/signext integer return value .


<s> void MipsTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ; const MipsSubtarget & Subtarget = TM . getSubtarget < MipsSubtarget > ( ) ; if ( Subtarget . isABI_N64 ( ) || Subtarget . isABI_N32 ( ) ) ReginfoSection = getContext ( ) . getELFSection ( ".MIPS.options" , ELF :: SHT_MIPS_OPTIONS , ELF :: SHF_ALLOC | ELF :: SHF_MIPS_NOSTRIP , SectionKind :: getMetadata ( ) ) ; else ReginfoSection = getContext ( ) . getELFSection ( ".reginfo" , ELF :: SHT_MIPS_REGINFO , ELF :: SHF_ALLOC , SectionKind :: getMetadata ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s> void HexagonPassConfig :: addPreEmitPass ( ) { bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) addPass ( createHexagonNewValueJump ( ) ) ; addPass ( createHexagonBranchRelaxation ( ) ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( createHexagonFixupHwLoops ( ) ) ; if ( EnableGenMux ) addPass ( createHexagonGenMux ( ) ) ; } addPass ( createHexagonPacketizer ( NoOpt ) , false ) ; if ( EnableVectorPrint ) addPass ( createHexagonVectorPrint ( ) , false ) ; addPass ( createHexagonCallFrameInformation ( ) , false ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon


"Can only insert epilog into returning blocks"


<s> static bool ix86_unordered_fp_compare ( enum rtx_code code ) { if ( ! TARGET_IEEE_FP ) return false ; switch ( code ) { case LT : case LE : case GT : case GE : case LTGT : return false ; case EQ : case NE : case UNORDERED : case ORDERED : case UNLT : case UNLE : case UNGT : case UNGE : case UNEQ : return true ; default : gcc_unreachable ( ) ; } } </s>

Figure out whether to use unordered fp comparisons .


<s> void pa_output_addr_vec ( rtx lab , rtx body ) { int idx , vlen = XVECLEN ( body , 0 ) ; targetm . asm_out . internal_label ( asm_out_file , "L" , CODE_LABEL_NUMBER ( lab ) ) ; if ( TARGET_GAS ) fputs ( "\t.begin_brtab\n" , asm_out_file ) ; for ( idx = 0 ; idx < vlen ; idx ++ ) { ASM_OUTPUT_ADDR_VEC_ELT ( asm_out_file , CODE_LABEL_NUMBER ( XEXP ( XVECEXP ( body , 0 , idx ) , 0 ) ) ) ; } if ( TARGET_GAS ) fputs ( "\t.end_brtab\n" , asm_out_file ) ; } </s>


<s> void X86RegisterBankInfo :: applyMappingImpl ( const OperandsMapper & OpdMapper ) const { return applyDefaultMapping ( OpdMapper ) ; } </s>


<s> const MCPhysReg * MipsRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_SaveList ; if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_SaveList ; if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_SaveList ; if ( Subtarget . isFP64bit ( ) ) return CSR_O32_FP64_SaveList ; if ( Subtarget . isFPXX ( ) ) return CSR_O32_FPXX_SaveList ; return CSR_O32_SaveList ; } </s>


<s>
void
MipsRegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
MachineInstr
&
MI
=
*
II
;
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
DEBUG
(
errs
(
)
<<
"\nFunction : "
<<
MF
.
getName
(
)
<<
"\n"
;
errs
(
)
<<
"<--------->\n"
<<
MI
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
uint64_t
stackSize
=
MF
.
getFrameInfo
(
)
.
getStackSize
(
)
;
int64_t
spOffset
=
MF
.
getFrameInfo
(
)
.
getObjectOffset
(
FrameIndex
)
;
DEBUG
(
errs
(
)
<<
"FrameIndex : "
<<
FrameIndex
<<
"\n"
<<
"spOffset   : "
<<
spOffset
<<
"\n"
<<
"stackSize  : "
<<
stackSize
<<
"\n"
)
;
eliminateFI
(
MI
,
FIOperandNum
,
FrameIndex
,
stackSize
,
spOffset
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .

Mips
Mips
"\nFunction : "
"\n"
"<--------->\n"
"FrameIndex : "
"\n"
"spOffset   : "
"\n"
"stackSize  : "
"\n"


<s>
MCOperand
PTXAsmPrinter
::
lowerOperand
(
const
MachineOperand
&
MO
)
{
MCOperand
MCOp
;
const
PTXMachineFunctionInfo
*
MFI
=
MF
->
getInfo
<
PTXMachineFunctionInfo
>
(
)
;
const
MCExpr
*
Expr
;
const
char
*
RegSymbolName
;
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"Unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
RegSymbolName
=
MFI
->
getRegisterName
(
MO
.
getReg
(
)
)
;
Expr
=
MCSymbolRefExpr
::
Create
(
RegSymbolName
,
MCSymbolRefExpr
::
VK_None
,
OutContext
)
;
MCOp
=
MCOperand
::
CreateExpr
(
Expr
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
CreateImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
CreateExpr
(
MCSymbolRefExpr
::
Create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
OutContext
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
GetSymbolRef
(
MO
,
Mang
->
getSymbol
(
MO
.
getGlobal
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
GetSymbolRef
(
MO
,
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
)
;
break
;
case
MachineOperand
::
MO_FPImmediate
:
APFloat
Val
=
MO
.
getFPImm
(
)
->
getValueAPF
(
)
;
bool
ignored
;
Val
.
convert
(
APFloat
::
IEEEdouble
,
APFloat
::
rmTowardZero
,
&
ignored
)
;
MCOp
=
MCOperand
::
CreateFPImm
(
Val
.
convertToDouble
(
)
)
;
break
;
}
return
MCOp
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> TargetPassConfig * LC2200TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new LC2200PassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createARMMachObjectWriter ( OS , false , MachO :: CPU_TYPE_ARM , Subtype ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s>
void
microblaze_asm_output_ident
(
const
char
*
string
)
{
const
char
*
section_asm_op
;
int
size
;
char
*
buf
;
if
(
symtab
->
state
!=
PARSING
)
return
;
size
=
strlen
(
string
)
+
1
;
if
(
size
<=
microblaze_section_threshold
)
section_asm_op
=
SDATA2_SECTION_ASM_OP
;
else
section_asm_op
=
READONLY_DATA_SECTION_ASM_OP
;
buf
=
ACONCAT
(
(
section_asm_op
,
"\n\t.ascii \""
,
string
,
"\\0\"\n"
,
)
)
;
symtab
->
finalize_toplevel_asm
(
build_string
(
strlen
(
buf
)
,
buf
)
)
;
}
</s>

Queue an .ident string in the queue of top-level asm statements . If the string size is below the threshold , put it into .sdata2 . If the front-end is done , we must be being called from toplev.cc . In that case , do nothing .


"Alignment not a multiple of the instruction size:"

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> void GCNMaxOccupancySchedStrategy :: pickNodeFromQueue ( SchedBoundary & Zone , const CandPolicy & ZonePolicy , const RegPressureTracker & RPTracker , SchedCandidate & Cand ) { const SIRegisterInfo * SRI = static_cast < const SIRegisterInfo * > ( TRI ) ; ArrayRef < unsigned > Pressure = RPTracker . getRegSetPressureAtPos ( ) ; unsigned SGPRPressure = Pressure [ SRI -> getSGPRPressureSet ( ) ] ; unsigned VGPRPressure = Pressure [ SRI -> getVGPRPressureSet ( ) ] ; ReadyQueue & Q = Zone . Available ; for ( SUnit * SU : Q ) { SchedCandidate TryCand ( ZonePolicy ) ; initCandidate ( TryCand , SU , Zone . isTop ( ) , RPTracker , SRI , SGPRPressure , VGPRPressure ) ; SchedBoundary * ZoneArg = Cand . AtTop == TryCand . AtTop ? & Zone : nullptr ; GenericScheduler :: tryCandidate ( Cand , TryCand , ZoneArg ) ; if ( TryCand . Reason != NoCand ) { if ( TryCand . ResDelta == SchedResourceDelta ( ) ) TryCand . initResourceDelta ( Zone . DAG , SchedModel ) ; Cand . setBest ( TryCand ) ; } } } </s>

Pick the best candidate from the queue .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < JVMSubtarget > ( ) ; MRI = & MF . getRegInfo ( ) ; MFI = MF . getInfo < JVMFunctionInfo > ( ) ; OutStreamer -> SetFunctionInfo ( MFI -> getDescVector ( ) ) ; return AsmPrinter :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { const auto & Desc = Info -> get ( Inst . getOpcode ( ) ) ; for ( unsigned i = 0 , e = Inst . getNumOperands ( ) ; i != e ; i ++ ) { if ( Desc . OpInfo [ i ] . OperandType == MCOI :: OPERAND_PCREL ) { int64_t Imm = Inst . getOperand ( i ) . getImm ( ) * 4 ; Target = Addr + Imm ; return true ; } } return false ; } </s>

Given a branch instruction try to get the address the branch targets .


<s> bool AMDGPUAsmParser :: isToken ( const AsmToken :: TokenKind Kind ) const { return getTokenKind ( ) == Kind ; } </s>


<s> bool ix86_match_ccmode ( rtx insn , machine_mode req_mode ) { rtx set ; machine_mode set_mode ; set = PATTERN ( insn ) ; if ( GET_CODE ( set ) == PARALLEL ) set = XVECEXP ( set , 0 , 0 ) ; gcc_assert ( GET_CODE ( set ) == SET ) ; gcc_assert ( GET_CODE ( SET_SRC ( set ) ) == COMPARE ) ; set_mode = GET_MODE ( SET_DEST ( set ) ) ; switch ( set_mode ) { case CCNOmode : if ( req_mode != CCNOmode && ( req_mode != CCmode || XEXP ( SET_SRC ( set ) , 1 ) != const0_rtx ) ) return false ; break ; case CCmode : if ( req_mode == CCGCmode ) return false ; case CCGCmode : if ( req_mode == CCGOCmode || req_mode == CCNOmode ) return false ; case CCGOCmode : if ( req_mode == CCZmode ) return false ; case CCZmode : break ; case CCAmode : case CCCmode : case CCOmode : case CCPmode : case CCSmode : if ( set_mode != req_mode ) return false ; break ; default : gcc_unreachable ( ) ; } return GET_MODE ( SET_SRC ( set ) ) == set_mode ; } </s>

Return TRUE or FALSE depending on whether the first SET in INSN has source and destination with matching CC modes , and that the CC mode is at least as constrained as REQ_MODE .


<s> MCSymbol * ARMAsmPrinter :: GetCPISymbol ( unsigned CPID ) const { const DataLayout & DL = getDataLayout ( ) ; return OutContext . getOrCreateSymbol ( Twine ( DL . getPrivateGlobalPrefix ( ) ) + "CPI" + Twine ( getFunctionNumber ( ) ) + "_" + Twine ( CPID ) ) ; } </s>

Return the symbol for the specified constant pool entry .


<s> bool MINA32PassConfig :: addInstSelector ( ) { addPass ( createMINA32ISelDag ( getMINA32TargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> SDValue SITargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { default : return AMDGPUTargetLowering :: LowerOperation ( Op , DAG ) ; case ISD :: BRCOND : return LowerBRCOND ( Op , DAG ) ; case ISD :: LOAD : return LowerLOAD ( Op , DAG ) ; case ISD :: SELECT_CC : return LowerSELECT_CC ( Op , DAG ) ; case ISD :: AND : return Loweri1ContextSwitch ( Op , DAG , ISD :: AND ) ; case ISD :: INTRINSIC_WO_CHAIN : { unsigned IntrinsicID = cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ; EVT VT = Op . getValueType ( ) ; switch ( IntrinsicID ) { case AMDGPUIntrinsic :: SI_vs_load_buffer_index : return CreateLiveInRegister ( DAG , & AMDGPU :: VReg_32RegClass , AMDGPU :: VGPR0 , VT ) ; default : return AMDGPUTargetLowering :: LowerOperation ( Op , DAG ) ; } break ; } } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .


"M68k PIC Global Base Reg Initialization"

getPassName - Return a nice clean name for a pass .


<s> unsigned SIRegisterInfo :: reservedPrivateSegmentBufferReg ( const MachineFunction & MF ) const { const AMDGPUSubtarget & ST = MF . getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . hasSGPRInitBug ( ) ) { unsigned BaseIdx = AMDGPUSubtarget :: FIXED_SGPR_COUNT_FOR_INIT_BUG - 8 - 4 ; unsigned BaseReg ( AMDGPU :: SGPR_32RegClass . getRegister ( BaseIdx ) ) ; return getMatchingSuperReg ( BaseReg , AMDGPU :: sub0 , & AMDGPU :: SReg_128RegClass ) ; } if ( ST . getGeneration ( ) >= AMDGPUSubtarget :: VOLCANIC_ISLANDS ) { return AMDGPU :: SGPR92_SGPR93_SGPR94_SGPR95 ; } return AMDGPU :: SGPR96_SGPR97_SGPR98_SGPR99 ; } </s>

Return the end register initially reserved for the scratch buffer in case spilling is needed .


<s> unsigned ARMBaseInstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { const MachineMemOperand * Dummy ; return MI . mayLoad ( ) && hasLoadFromStackSlot ( MI , Dummy , FrameIndex ) ; } </s>

isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s> static void emit_unlikely_jump ( rtx cond , rtx label ) { int very_unlikely = REG_BR_PROB_BASE / 100 - 1 ; rtx x = gen_rtx_IF_THEN_ELSE ( VOIDmode , cond , label , pc_rtx ) ; rtx_insn * insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , x ) ) ; add_int_reg_note ( insn , REG_BR_PROB , very_unlikely ) ; } </s>

Mark the previous jump instruction as unlikely .


<s> bool AArch64PassConfig :: addIRTranslator ( ) { addPass ( new IRTranslator ( ) ) ; return false ; } </s>

This method should install an IR translator pass , which converts from LLVM code to machine instructions with possibly generic opcodes .


"setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n"

Worker function for TARGET_SETUP_INCOMING_VARARGS .


"-misched-topdown incompatible with -misched-bottomup"

Initialize the strategy after building the DAG for a new region .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
Mips
::
NumTargetFixupKinds
]
=
{
{
"fixup_Mips_16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_32"
,
0
,
32
,
0
}
,
{
"fixup_Mips_REL32"
,
0
,
32
,
0
}
,
{
"fixup_Mips_26"
,
0
,
26
,
0
}
,
{
"fixup_Mips_HI16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_LO16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GPREL16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_LITERAL"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GOT_Global"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GOT_Local"
,
0
,
16
,
0
}
,
{
"fixup_Mips_PC16"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_Mips_CALL16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GPREL32"
,
0
,
32
,
0
}
,
{
"fixup_Mips_SHIFT5"
,
6
,
5
,
0
}
,
{
"fixup_Mips_SHIFT6"
,
6
,
5
,
0
}
,
{
"fixup_Mips_64"
,
0
,
64
,
0
}
,
{
"fixup_Mips_TLSGD"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GOTTPREL"
,
0
,
16
,
0
}
,
{
"fixup_Mips_TPREL_HI"
,
0
,
16
,
0
}
,
{
"fixup_Mips_TPREL_LO"
,
0
,
16
,
0
}
,
{
"fixup_Mips_TLSLDM"
,
0
,
16
,
0
}
,
{
"fixup_Mips_DTPREL_HI"
,
0
,
16
,
0
}
,
{
"fixup_Mips_DTPREL_LO"
,
0
,
16
,
0
}
,
{
"fixup_Mips_Branch_PCRel"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_Mips_GPOFF_HI"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GPOFF_LO"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GOT_PAGE"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GOT_OFST"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GOT_DISP"
,
0
,
16
,
0
}
,
{
"fixup_Mips_HIGHER"
,
0
,
16
,
0
}
,
{
"fixup_Mips_HIGHEST"
,
0
,
16
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> void GBZ80InstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , unsigned SubIdx , const MachineInstr & Orig , const TargetRegisterInfo & TRI ) const { MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( & Orig ) ; MBB . insert ( I , MI ) ; MachineInstr & NewMI = * std :: prev ( I ) ; NewMI . substituteRegister ( Orig . getOperand ( 0 ) . getReg ( ) , DestReg , SubIdx , TRI ) ; } </s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s>
void
Nios2DAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> void MOSStaticStackAlloc :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineModuleInfoWrapperPass > ( ) ; AU . addPreserved < MachineModuleInfoWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static struct constant_pool * s390_start_pool ( struct constant_pool * * pool_list , rtx_insn * insn ) { struct constant_pool * pool , * * prev ; pool = s390_alloc_pool ( ) ; pool -> first_insn = insn ; for ( prev = pool_list ; * prev ; prev = & ( * prev ) -> next ) ; * prev = pool ; return pool ; } </s>

Create new constant pool covering instructions starting at INSN and chain it to the end of POOL_LIST .


<s> static tree arm_d_handle_target_float_abi ( void ) { const char * abi ; switch ( arm_float_abi ) { case ARM_FLOAT_ABI_HARD : abi = "hard" ; break ; case ARM_FLOAT_ABI_SOFT : abi = "soft" ; break ; case ARM_FLOAT_ABI_SOFTFP : abi = "softfp" ; break ; default : abi = "" ; break ; } return build_string_literal ( strlen ( abi ) + 1 , abi ) ; } </s>

Handle a call to ` __traits ( getTargetInfo , `` floatAbi '' ) ' .


<s> void emitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) override { EmitMappingSymbol ( "$t" ) ; MCELFStreamer :: emitInstruction ( Inst , STI ) ; } </s>

Targets should implement this to emit instructions .


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override { if ( Count == 0 ) return true ; return false ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> unsigned postKnownBits ( unsigned LogAlign = 0 ) const { return std :: max ( LogAlign , internalKnownBits ( ) ) ; } </s>

Compute the number of known low bits of postOffset .


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == ARM :: GPRRegisterClass ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2LDRi12 ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) ) ; return ; } ARMBaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> bool extract_base_offset_in_addr ( rtx mem , rtx * base , rtx * offset ) { rtx addr ; gcc_assert ( MEM_P ( mem ) ) ; addr = XEXP ( mem , 0 ) ; if ( REG_P ( addr ) ) { * base = addr ; * offset = const0_rtx ; return true ; } if ( GET_CODE ( addr ) == PLUS && REG_P ( XEXP ( addr , 0 ) ) && CONST_INT_P ( XEXP ( addr , 1 ) ) ) { * base = XEXP ( addr , 0 ) ; * offset = XEXP ( addr , 1 ) ; return true ; } * base = NULL_RTX ; * offset = NULL_RTX ; return false ; } </s>

If MEM is in the form of `` base+offset '' , extract the two parts of address and set to BASE and OFFSET , otherwise return false after clearing BASE and OFFSET .


<s> bool MipsCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) { return false ; } for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( Arg . getType ( ) ) ) return false ; } MachineFunction & MF = MIRBuilder . getMF ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const MipsTargetLowering & TLI = * getTLI < MipsTargetLowering > ( ) ; SmallVector < ArgInfo , 8 > ArgInfos ; SmallVector < unsigned , 8 > OrigArgIndices ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ i ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , i + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( AInfo , i , ArgInfos , OrigArgIndices ) ; ++ i ; } SmallVector < ISD :: InputArg , 8 > Ins ; subTargetRegTypeForCallingConv ( MIRBuilder , ArgInfos , OrigArgIndices , [ & ] ( ISD :: ArgFlagsTy flags , EVT vt , EVT argvt , bool used , unsigned origIdx , unsigned partOffs ) { Ins . emplace_back ( flags , vt , argvt , used , origIdx , partOffs ) ; } ) ; SmallVector < CCValAssign , 16 > ArgLocs ; MipsCCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , TLI . CCAssignFnForCall ( ) ) ; IncomingValueHandler Handler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) ) ; if ( ! Handler . handle ( ArgLocs , ArgInfos ) ) return false ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> static bool rs6000_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { unsigned from_size = GET_MODE_SIZE ( from ) ; unsigned to_size = GET_MODE_SIZE ( to ) ; if ( from_size != to_size ) { enum reg_class xclass = ( TARGET_VSX ) ? VSX_REGS : FLOAT_REGS ; if ( reg_classes_intersect_p ( xclass , rclass ) ) { unsigned to_nregs = hard_regno_nregs ( FIRST_FPR_REGNO , to ) ; unsigned from_nregs = hard_regno_nregs ( FIRST_FPR_REGNO , from ) ; bool to_float128_vector_p = FLOAT128_VECTOR_P ( to ) ; bool from_float128_vector_p = FLOAT128_VECTOR_P ( from ) ; if ( to_float128_vector_p && from_float128_vector_p ) return true ; else if ( to_float128_vector_p || from_float128_vector_p ) return false ; if ( ! BYTES_BIG_ENDIAN && ( to == TDmode || from == TDmode ) ) return false ; if ( from_size < 8 || to_size < 8 ) return false ; if ( from_size == 8 && ( 8 * to_nregs ) != to_size ) return false ; if ( to_size == 8 && ( 8 * from_nregs ) != from_size ) return false ; return true ; } else return true ; } if ( TARGET_E500_DOUBLE && ( ( ( ( to ) == DFmode ) + ( ( from ) == DFmode ) ) == 1 || ( ( ( to ) == TFmode ) + ( ( from ) == TFmode ) ) == 1 || ( ( ( to ) == IFmode ) + ( ( from ) == IFmode ) ) == 1 || ( ( ( to ) == KFmode ) + ( ( from ) == KFmode ) ) == 1 || ( ( ( to ) == DDmode ) + ( ( from ) == DDmode ) ) == 1 || ( ( ( to ) == TDmode ) + ( ( from ) == TDmode ) ) == 1 || ( ( ( to ) == DImode ) + ( ( from ) == DImode ) ) == 1 ) ) return false ; if ( TARGET_VSX && VSX_REG_CLASS_P ( rclass ) ) { unsigned num_regs = ( from_size + 15 ) / 16 ; if ( hard_regno_nregs ( FIRST_FPR_REGNO , to ) > num_regs || hard_regno_nregs ( FIRST_FPR_REGNO , from ) > num_regs ) return false ; return ( from_size == 8 || from_size == 16 ) ; } if ( TARGET_ALTIVEC && rclass == ALTIVEC_REGS && ( ALTIVEC_VECTOR_MODE ( from ) + ALTIVEC_VECTOR_MODE ( to ) ) == 1 ) return false ; if ( TARGET_SPE && ( SPE_VECTOR_MODE ( from ) + SPE_VECTOR_MODE ( to ) ) == 1 && reg_classes_intersect_p ( GENERAL_REGS , rclass ) ) return false ; return true ; } </s>


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < CallGraph > ( ) ; } </s>


"Cannot copy accumulator without killing it"


<s> bool ARMBaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( RealignStack && ( ! MFI -> hasVarSizedObjects ( ) || EnableBasePointer ) ) ; } </s>

True if the stack can be realigned for the target .


<s> static rtx gen_ldst ( bool load_p , int regno , rtx base_mem , int offset ) { rtx reg = gen_rtx_REG ( SImode , regno ) ; rtx mem = adjust_address_nv ( base_mem , SImode , offset ) ; return gen_rtx_SET ( load_p ? reg : mem , load_p ? mem : reg ) ; } </s>

Helper for nios2_ldst_parallel , for generating a parallel vector SET element .


<s> bool AArch64TargetLowering :: isProfitableToHoist ( Instruction * I ) const { if ( I -> getOpcode ( ) != Instruction :: FMul ) return true ; if ( I -> getNumUses ( ) != 1 ) return true ; Instruction * User = I -> user_back ( ) ; if ( User && ! ( User -> getOpcode ( ) == Instruction :: FSub || User -> getOpcode ( ) == Instruction :: FAdd ) ) return true ; const TargetOptions & Options = getTargetMachine ( ) . Options ; const DataLayout & DL = I -> getModule ( ) -> getDataLayout ( ) ; EVT VT = getValueType ( DL , User -> getOperand ( 0 ) -> getType ( ) ) ; if ( isFMAFasterThanFMulAndFAdd ( VT ) && isOperationLegalOrCustom ( ISD :: FMA , VT ) && ( Options . AllowFPOpFusion == FPOpFusion :: Fast || Options . UnsafeFPMath ) ) return false ; return true ; } </s>

Return true if it is profitable to hoist instruction in the then/else to before if .


<s> static bool rs6000_cannot_change_mode_class ( machine_mode from , machine_mode to , enum reg_class rclass ) { unsigned from_size = GET_MODE_SIZE ( from ) ; unsigned to_size = GET_MODE_SIZE ( to ) ; if ( from_size != to_size ) { enum reg_class xclass = ( TARGET_VSX ) ? VSX_REGS : FLOAT_REGS ; if ( reg_classes_intersect_p ( xclass , rclass ) ) { unsigned to_nregs = hard_regno_nregs [ FIRST_FPR_REGNO ] [ to ] ; unsigned from_nregs = hard_regno_nregs [ FIRST_FPR_REGNO ] [ from ] ; bool to_float128_vector_p = FLOAT128_VECTOR_P ( to ) ; bool from_float128_vector_p = FLOAT128_VECTOR_P ( from ) ; if ( to_float128_vector_p && from_float128_vector_p ) return false ; else if ( to_float128_vector_p || from_float128_vector_p ) return true ; if ( ! BYTES_BIG_ENDIAN && ( to == TDmode || from == TDmode ) ) return true ; if ( from_size < 8 || to_size < 8 ) return true ; if ( from_size == 8 && ( 8 * to_nregs ) != to_size ) return true ; if ( to_size == 8 && ( 8 * from_nregs ) != from_size ) return true ; return false ; } else return false ; } if ( TARGET_E500_DOUBLE && ( ( ( ( to ) == DFmode ) + ( ( from ) == DFmode ) ) == 1 || ( ( ( to ) == TFmode ) + ( ( from ) == TFmode ) ) == 1 || ( ( ( to ) == IFmode ) + ( ( from ) == IFmode ) ) == 1 || ( ( ( to ) == KFmode ) + ( ( from ) == KFmode ) ) == 1 || ( ( ( to ) == DDmode ) + ( ( from ) == DDmode ) ) == 1 || ( ( ( to ) == TDmode ) + ( ( from ) == TDmode ) ) == 1 || ( ( ( to ) == DImode ) + ( ( from ) == DImode ) ) == 1 ) ) return true ; if ( TARGET_VSX && VSX_REG_CLASS_P ( rclass ) ) { unsigned num_regs = ( from_size + 15 ) / 16 ; if ( hard_regno_nregs [ FIRST_FPR_REGNO ] [ to ] > num_regs || hard_regno_nregs [ FIRST_FPR_REGNO ] [ from ] > num_regs ) return true ; return ( from_size != 8 && from_size != 16 ) ; } if ( TARGET_ALTIVEC && rclass == ALTIVEC_REGS && ( ALTIVEC_VECTOR_MODE ( from ) + ALTIVEC_VECTOR_MODE ( to ) ) == 1 ) return true ; if ( TARGET_SPE && ( SPE_VECTOR_MODE ( from ) + SPE_VECTOR_MODE ( to ) ) == 1 && reg_classes_intersect_p ( GENERAL_REGS , rclass ) ) return true ; return false ; } </s>

Return nonzero if for CLASS a mode change from FROM to TO is invalid .


<s> unsigned int mips_hard_regno_nregs ( int regno , machine_mode mode ) { if ( ST_REG_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + 3 ) / 4 ; if ( FP_REG_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + UNITS_PER_FPREG - 1 ) / UNITS_PER_FPREG ; return ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } </s>


<s> bool MOSRegisterInfo :: shouldCoalesce ( MachineInstr * MI , const TargetRegisterClass * SrcRC , unsigned SubReg , const TargetRegisterClass * DstRC , unsigned DstSubReg , const TargetRegisterClass * NewRC , LiveIntervals & LIS ) const { const auto & MRI = MI -> getMF ( ) -> getRegInfo ( ) ; if ( NewRC == & MOS :: Imag8RegClass || NewRC == & MOS :: Imag16RegClass ) { if ( DstRC == & MOS :: AImag8RegClass && referencedByShiftRotate ( MI -> getOperand ( 0 ) . getReg ( ) , MRI ) && ! isRmwPattern ( MI -> getOperand ( 0 ) . getReg ( ) , MRI ) ) return false ; if ( SrcRC == & MOS :: AImag8RegClass && referencedByShiftRotate ( MI -> getOperand ( 1 ) . getReg ( ) , MRI ) && ! isRmwPattern ( MI -> getOperand ( 1 ) . getReg ( ) , MRI ) ) return false ; if ( DstRC == & MOS :: Anyi8RegClass && referencedByIncDec ( MI -> getOperand ( 0 ) . getReg ( ) , MRI ) && ! isRmwPattern ( MI -> getOperand ( 0 ) . getReg ( ) , MRI ) ) return false ; if ( SrcRC == & MOS :: Anyi8RegClass && referencedByIncDec ( MI -> getOperand ( 1 ) . getReg ( ) , MRI ) && ! isRmwPattern ( MI -> getOperand ( 1 ) . getReg ( ) , MRI ) ) return false ; } if ( NewRC == & MOS :: GPRRegClass ) { if ( DstRC == & MOS :: Anyi8RegClass && referencedByIncDec ( MI -> getOperand ( 0 ) . getReg ( ) , MRI ) ) return false ; if ( SrcRC == & MOS :: Anyi8RegClass && referencedByIncDec ( MI -> getOperand ( 1 ) . getReg ( ) , MRI ) ) return false ; } return true ; } </s>


<s> void setupMF ( MachineFunction & MF , GISelKnownBits * KB , CodeGenCoverage & CoverageInfo , ProfileSummaryInfo * PSI , BlockFrequencyInfo * BFI , AAResults * AA ) override { InstructionSelector :: setupMF ( MF , KB , CoverageInfo , PSI , BFI , AA ) ; MIB . setMF ( MF ) ; ProduceNonFlagSettingCondBr = ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: SpeculativeLoadHardening ) ; MFReturnAddr = Register ( ) ; processPHIs ( MF ) ; } </s>


<s> static rtx csky_dwarf_register_span ( rtx rtl ) { machine_mode mode ; unsigned regno ; rtx parts [ 16 ] ; int nregs ; int i ; regno = REGNO ( rtl ) ; if ( ! CSKY_VREG_P ( regno ) ) return NULL_RTX ; if ( CSKY_VREG_HI_P ( regno ) ) regno += 16 ; mode = GET_MODE ( rtl ) ; if ( GET_MODE_SIZE ( mode ) < 8 ) return NULL_RTX ; if ( TARGET_SINGLE_FPU ) { nregs = GET_MODE_SIZE ( mode ) / 4 ; for ( i = 0 ; i < nregs ; i += 2 ) if ( TARGET_BIG_ENDIAN ) { parts [ i ] = gen_rtx_REG ( SImode , regno + i + 1 ) ; parts [ i + 1 ] = gen_rtx_REG ( SImode , regno + i ) ; } else { parts [ i ] = gen_rtx_REG ( SImode , regno + i ) ; parts [ i + 1 ] = gen_rtx_REG ( SImode , regno + i + 1 ) ; } } else { nregs = GET_MODE_SIZE ( mode ) / 4 ; for ( i = 0 ; i < nregs ; i += 2 ) if ( TARGET_BIG_ENDIAN ) { parts [ i ] = gen_rtx_REG ( SImode , regno + i - 16 ) ; parts [ i + 1 ] = gen_rtx_REG ( SImode , regno + i ) ; } else { parts [ i ] = gen_rtx_REG ( SImode , regno + i ) ; parts [ i + 1 ] = gen_rtx_REG ( SImode , regno + i - 16 ) ; } } return gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( nregs , parts ) ) ; } </s>

Implement TARGET_DWARF_REGISTER_SPAN . Dwarf models VFP registers as 64-bit or 128-bit registers default . GCC models tham as 32-bit registers , so we need to describe this to the DWARF generation code . Other registers can use the default .


<s> int avr_progmem_p ( tree decl , tree attributes ) { tree a ; if ( TREE_CODE ( decl ) != VAR_DECL ) return 0 ; if ( avr_decl_memx_p ( decl ) ) return 2 ; if ( avr_decl_flash_p ( decl ) ) return 1 ; if ( NULL_TREE != lookup_attribute ( "progmem" , attributes ) ) return - 1 ; a = decl ; do a = TREE_TYPE ( a ) ; while ( TREE_CODE ( a ) == ARRAY_TYPE ) ; if ( a == error_mark_node ) return 0 ; if ( NULL_TREE != lookup_attribute ( "progmem" , TYPE_ATTRIBUTES ( a ) ) ) return - 1 ; return 0 ; } </s>

Look for attribute ` progmem ' in DECL if found return 1 , otherwise 0 .


<s> static std :: string getGraphName ( const MCallSubGraph & G ) { return "CallGraph" ; } </s>

Generate a title for the graph in DOT format .


<s> static void push_regs ( int mask ) { int i ; int exregs [ FIRST_PSEUDO_REGISTER ] ; memset ( exregs , 0 , sizeof ( exregs ) ) ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { if ( mask & ( 1 << i ) ) { exregs [ renumber [ i ] ] = 1 ; } } for ( i = 0 ; i < FIRST_PSEUDO_REGISTER - 1 ; i += 2 ) { if ( exregs [ i ] && exregs [ i + 1 ] ) { push ( rev_renumber [ i ] , SImode ) ; } else if ( exregs [ i ] ) { push ( rev_renumber [ i ] , HImode ) ; } else if ( exregs [ i + 1 ] ) { push ( rev_renumber [ i + 1 ] , HImode ) ; } } } </s>

Generate code to push the regs specified in the mask . remember that the mask is of the internal shape of the regs , not the external shape - so go through the renumber vector


<s> static bool h8300_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { return ( TYPE_MODE ( type ) == BLKmode || GET_MODE_SIZE ( TYPE_MODE ( type ) ) > 8 ) ; } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


<s> const uint32_t * MMIXRegisterInfo :: getNoPreservedMask ( ) const { return CSR_NoRegs_RegMask ; } </s>

Return a register mask that clobbers everything .


<s> bool MipsPreLegalizerCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: FailedISel ) ) return false ; auto * TPC = & getAnalysis < TargetPassConfig > ( ) ; MipsPreLegalizerCombinerInfo PCInfo ; Combiner C ( PCInfo , TPC ) ; return C . combineMachineInstrs ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool AArch64InstrInfo :: isWhileOpcode ( unsigned Opc ) const { return get ( Opc ) . TSFlags & AArch64 :: InstrFlagIsWhile ; } </s>

Returns true if the opcode is for an SVE WHILE # # instruction .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < AAResultsWrapperPass > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
bool
IA64AsmPrinter
::
doInitialization
(
Module
&
M
)
{
bool
Result
=
AsmPrinter
::
doInitialization
(
M
)
;
O
<<
"\n.ident \"LLVM-ia64\"\n\n"
<<
"\t.psr    lsb\n"
<<
"\t.radix  C\n"
<<
"\t.psr    abi64\n"
;
return
Result
;
}
</s>

Set up the AsmPrinter when we are working on a new module .

IA64
IA64
"\n.ident \"LLVM-ia64\"\n\n"
"\t.psr    lsb\n"
"\t.radix  C\n"
"\t.psr    abi64\n"


<s> static rtx alpha_lookup_xfloating_lib_func ( enum rtx_code code ) { struct xfloating_op * ops = xfloating_ops ; long n = ARRAY_SIZE ( xfloating_ops ) ; long i ; gcc_assert ( TARGET_HAS_XFLOATING_LIBS ) ; if ( TARGET_FLOAT_VAX && ( code == FLOAT_EXTEND || code == FLOAT_TRUNCATE ) ) { ops = vax_cvt_ops ; n = ARRAY_SIZE ( vax_cvt_ops ) ; } for ( i = 0 ; i < n ; ++ i , ++ ops ) if ( ops -> code == code ) { rtx func = ops -> libcall ; if ( ! func ) { func = init_one_libfunc ( TARGET_ABI_OPEN_VMS ? ops -> vms_func : ops -> osf_func ) ; ops -> libcall = func ; } return func ; } gcc_unreachable ( ) ; } </s>

Look up the function X_floating library function name for the given operation .


<s> static bool bpf_frame_pointer_required ( void ) { return true ; } </s>

Return true if a function must have and use a frame pointer .


<s> SDNode * X86DAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; auto & DL = MF -> getDataLayout ( ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI -> getPointerTy ( DL ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> bool legitimate_reload_constant_p ( rtx op ) { if ( GET_CODE ( op ) == CONST_INT && DISP_IN_RANGE ( INTVAL ( op ) ) ) return true ; if ( GET_CODE ( op ) == CONST_INT && ( CONST_OK_FOR_K ( INTVAL ( op ) ) || CONST_OK_FOR_Os ( INTVAL ( op ) ) ) ) return true ; if ( TARGET_ZARCH && GET_CODE ( op ) == CONST_INT && trunc_int_for_mode ( INTVAL ( op ) , word_mode ) == INTVAL ( op ) && s390_single_part ( op , word_mode , HImode , 0 ) >= 0 ) return true ; if ( TARGET_EXTIMM && GET_CODE ( op ) == CONST_INT && trunc_int_for_mode ( INTVAL ( op ) , word_mode ) == INTVAL ( op ) && s390_single_part ( op , word_mode , SImode , 0 ) >= 0 ) return true ; if ( TARGET_CPU_ZARCH && larl_operand ( op , VOIDmode ) ) return true ; if ( GET_CODE ( op ) == CONST_DOUBLE && s390_float_const_zero_p ( op ) && GET_MODE_SIZE ( GET_MODE ( op ) ) <= UNITS_PER_WORD ) return true ; if ( GET_CODE ( op ) == CONST_WIDE_INT || ( GET_CODE ( op ) == CONST_INT && trunc_int_for_mode ( INTVAL ( op ) , word_mode ) != INTVAL ( op ) ) ) { machine_mode dword_mode = word_mode == SImode ? DImode : TImode ; rtx hi = operand_subword ( op , 0 , 0 , dword_mode ) ; rtx lo = operand_subword ( op , 1 , 0 , dword_mode ) ; return legitimate_reload_constant_p ( hi ) && legitimate_reload_constant_p ( lo ) ; } return false ; } </s>

Returns true if the constant value OP is a legitimate general operand during and after reload . The difference to legitimate_constant_p is that this function will not accept a constant that would need to be forced to the literal pool before it can be used as operand .


<s> static void rs6000_do_expand_vec_perm ( rtx target , rtx op0 , rtx op1 , machine_mode vmode , const vec_perm_builder & perm ) { rtx x = expand_vec_perm_const ( vmode , op0 , op1 , perm , BLKmode , target ) ; if ( x != target ) emit_move_insn ( target , x ) ; } </s>

A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave .


"  rs6000_builtin_decls[(int)RS6000_BIF_%s] = t\n"

"                            NULL, NULL_TREE);\n"

Write code to initialize the built-in function table .

"                            NULL, NULL_TREE);\n"


Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void setFunction ( Function & Func ) { F = & Func ; } </s>

Initialize data structures for specified new function .


<s> void alpha_split_atomic_exchange ( rtx operands [ ] ) { rtx retval , mem , val , scratch ; enum memmodel model ; machine_mode mode ; rtx label , x , cond ; retval = operands [ 0 ] ; mem = operands [ 1 ] ; val = operands [ 2 ] ; model = ( enum memmodel ) INTVAL ( operands [ 3 ] ) ; scratch = operands [ 4 ] ; mode = GET_MODE ( mem ) ; cond = gen_lowpart ( DImode , scratch ) ; alpha_pre_atomic_barrier ( model ) ; label = gen_rtx_LABEL_REF ( DImode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label , 0 ) ) ; emit_load_locked ( mode , retval , mem ) ; emit_move_insn ( scratch , val ) ; emit_store_conditional ( mode , cond , mem , scratch ) ; x = gen_rtx_EQ ( DImode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label ) ; alpha_post_atomic_barrier ( model ) ; } </s>


<s> void loongarch_expand_prologue ( void ) { struct loongarch_frame_info * frame = & cfun -> machine -> frame ; HOST_WIDE_INT size = frame -> total_size ; HOST_WIDE_INT tmp ; rtx insn ; if ( flag_stack_usage_info ) current_function_static_stack_size = size ; if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK || flag_stack_clash_protection ) { if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { if ( size > PROBE_INTERVAL && size > get_stack_check_protect ( ) ) { tmp = size - get_stack_check_protect ( ) ; loongarch_emit_probe_stack_range ( get_stack_check_protect ( ) , tmp ) ; } } else if ( size > 0 ) loongarch_emit_probe_stack_range ( get_stack_check_protect ( ) , size ) ; } if ( ( frame -> mask | frame -> fmask ) != 0 ) { HOST_WIDE_INT step1 = MIN ( size , loongarch_first_stack_step ( frame ) ) ; insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = 1 ; size -= step1 ; loongarch_for_each_saved_reg ( size , loongarch_save_reg ) ; } if ( frame_pointer_needed ) { insn = gen_add3_insn ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( frame -> hard_frame_pointer_offset - size ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = 1 ; loongarch_emit_stack_tie ( ) ; } if ( size > 0 ) { if ( IMM12_OPERAND ( - size ) ) { insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - size ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = 1 ; } else { loongarch_emit_move ( LARCH_PROLOGUE_TEMP ( Pmode ) , GEN_INT ( - size ) ) ; emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , LARCH_PROLOGUE_TEMP ( Pmode ) ) ) ; insn = plus_constant ( Pmode , stack_pointer_rtx , - size ) ; insn = gen_rtx_SET ( stack_pointer_rtx , insn ) ; loongarch_set_frame_expr ( insn ) ; } } } </s>


<s> void RISCVDAGToDAGISel :: PostprocessISelDAG ( ) { doPeepholeLoadStoreADDI ( ) ; } </s>

PostprocessISelDAG ( ) - This hook allows the target to hack on the graph right after selection .


<s>
MachineBasicBlock
*
HexagonTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
case
Hexagon
::
ALLOCA
:
{
MachineFunction
*
MF
=
BB
->
getParent
(
)
;
auto
*
FuncInfo
=
MF
->
getInfo
<
HexagonMachineFunctionInfo
>
(
)
;
FuncInfo
->
addAllocaAdjustInst
(
MI
)
;
return
BB
;
}
default
:
llvm_unreachable
(
"Unexpected instr type to insert"
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .

Hexagon
Hexagon
Hexagon::ALLOCA
Hexagon
"Unexpected instr type to insert"


<s> void VERegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const VEFrameLowering * TFI = getFrameLowering ( MF ) ; Register FrameReg ; int Offset ; Offset = TFI -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) . getFixed ( ) ; Offset += MI . getOperand ( FIOperandNum + 2 ) . getImm ( ) ; if ( MI . getOpcode ( ) == VE :: STQrii ) { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; Register SrcReg = MI . getOperand ( 3 ) . getReg ( ) ; Register SrcHiReg = getSubReg ( SrcReg , VE :: sub_even ) ; Register SrcLoReg = getSubReg ( SrcReg , VE :: sub_odd ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( VE :: STrii ) ) . addReg ( FrameReg ) . addImm ( 0 ) . addImm ( 0 ) . addReg ( SrcLoReg ) ; replaceFI ( MF , II , * StMI , dl , 0 , Offset , FrameReg ) ; MI . setDesc ( TII . get ( VE :: STrii ) ) ; MI . getOperand ( 3 ) . setReg ( SrcHiReg ) ; Offset += 8 ; } else if ( MI . getOpcode ( ) == VE :: LDQrii ) { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; Register DestReg = MI . getOperand ( 0 ) . getReg ( ) ; Register DestHiReg = getSubReg ( DestReg , VE :: sub_even ) ; Register DestLoReg = getSubReg ( DestReg , VE :: sub_odd ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( VE :: LDrii ) , DestLoReg ) . addReg ( FrameReg ) . addImm ( 0 ) . addImm ( 0 ) ; replaceFI ( MF , II , * StMI , dl , 1 , Offset , FrameReg ) ; MI . setDesc ( TII . get ( VE :: LDrii ) ) ; MI . getOperand ( 0 ) . setReg ( DestHiReg ) ; Offset += 8 ; } replaceFI ( MF , II , MI , dl , FIOperandNum , Offset , FrameReg ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> void GCNHazardRecognizer :: AdvanceCycle ( ) { if ( ! CurrCycleInstr ) return ; unsigned NumWaitStates = TII . getNumWaitStates ( * CurrCycleInstr ) ; EmittedInstrs . push_front ( CurrCycleInstr ) ; for ( unsigned i = 1 , e = std :: min ( NumWaitStates , getMaxLookAhead ( ) ) ; i < e ; ++ i ) { EmittedInstrs . push_front ( nullptr ) ; } EmittedInstrs . resize ( getMaxLookAhead ( ) ) ; CurrCycleInstr = nullptr ; } </s>

AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled can not issue in the current cycle , either because of latency or resource conflicts .


<s> unsigned SICFunctionInfo :: getGlobalBaseReg ( ) { return GlobalBaseReg = SIC :: B ; } </s>


<s> machine_mode loongarch_hard_regno_caller_save_mode ( unsigned int regno , unsigned int nregs , machine_mode mode ) { if ( mode == VOIDmode ) return choose_hard_reg_mode ( regno , nregs , NULL ) ; else return mode ; } </s>


<s> static int ia64_sched_reorder ( FILE * dump , int sched_verbose , rtx_insn * * ready , int * pn_ready , int clock_var ) { return ia64_dfa_sched_reorder ( dump , sched_verbose , ready , pn_ready , clock_var , 0 ) ; } </s>

We are about to being issuing insns for this clock cycle . Override the default sort algorithm to better slot instructions .


<s> bool SystemZFrameLowering :: hasFP ( const MachineFunction & MF ) const { return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) || MF . getInfo < SystemZMachineFunctionInfo > ( ) -> getManipulatesSP ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> void MipsInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { DebugLoc DL ; BuildMI ( MBB , MI , DL , get ( Mips :: NOP ) ) ; } </s>

Insert a noop into the instruction stream at the specified point .


<s> bool PTXInstrInfo :: isPredicated ( const MachineInstr * MI ) const { int i = MI -> findFirstPredOperandIdx ( ) ; return i != - 1 && MI -> getOperand ( i ) . getReg ( ) != PTX :: NoRegister ; } </s>

Returns true if the instruction is already predicated .


<s>
static
MCSymbol
*
GetSymbolFromOperand
(
const
MachineOperand
&
MO
,
AsmPrinter
&
AP
)
{
const
TargetMachine
&
TM
=
AP
.
TM
;
Mangler
*
Mang
=
AP
.
Mang
;
const
DataLayout
*
DL
=
TM
.
getSubtargetImpl
(
)
->
getDataLayout
(
)
;
MCContext
&
Ctx
=
AP
.
OutContext
;
bool
isDarwin
=
Triple
(
TM
.
getTargetTriple
(
)
)
.
isOSDarwin
(
)
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
)
{
if
(
isDarwin
)
Suffix
=
"$stub"
;
}
else
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
Suffix
=
"$non_lazy_ptr"
;
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
->
getPrivateGlobalPrefix
(
)
;
unsigned
PrefixLen
=
Name
.
size
(
)
;
if
(
!
MO
.
isGlobal
(
)
)
{
assert
(
MO
.
isSymbol
(
)
&&
"Isn't a symbol reference"
)
;
Mang
->
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
)
;
}
else
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
TM
.
getNameWithPrefix
(
Name
,
GV
,
*
Mang
)
;
}
unsigned
OrigLen
=
Name
.
size
(
)
PrefixLen
;
Name
+=
Suffix
;
MCSymbol
*
Sym
=
Ctx
.
GetOrCreateSymbol
(
Name
.
str
(
)
)
;
StringRef
OrigName
=
StringRef
(
Name
)
.
substr
(
PrefixLen
,
OrigLen
)
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
&&
isDarwin
)
{
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
getMachOMMI
(
AP
)
.
getFnStubEntry
(
Sym
)
;
if
(
StubSym
.
getPointer
(
)
)
return
Sym
;
if
(
MO
.
isGlobal
(
)
)
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
else
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
Ctx
.
GetOrCreateSymbol
(
OrigName
)
,
false
)
;
}
return
Sym
;
}
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
{
MachineModuleInfoMachO
&
MachO
=
getMachOMMI
(
AP
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_HIDDEN_FLAG
)
MachO
.
getHiddenGVStubEntry
(
Sym
)
:
MachO
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
return
Sym
;
}
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


<s> bool SITargetLowering :: getAddrModeArguments ( IntrinsicInst * II , SmallVectorImpl < Value * > & Ops , Type * & AccessTy ) const { switch ( II -> getIntrinsicID ( ) ) { case Intrinsic :: amdgcn_atomic_inc : case Intrinsic :: amdgcn_atomic_dec : case Intrinsic :: amdgcn_ds_ordered_add : case Intrinsic :: amdgcn_ds_ordered_swap : case Intrinsic :: amdgcn_ds_append : case Intrinsic :: amdgcn_ds_consume : case Intrinsic :: amdgcn_ds_fadd : case Intrinsic :: amdgcn_ds_fmin : case Intrinsic :: amdgcn_ds_fmax : case Intrinsic :: amdgcn_global_atomic_fadd : case Intrinsic :: amdgcn_global_atomic_csub : { Value * Ptr = II -> getArgOperand ( 0 ) ; AccessTy = II -> getType ( ) ; Ops . push_back ( Ptr ) ; return true ; } default : return false ; } } </s>

CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> static unsigned int mips_machine_reorg2 ( void ) { mips_reorg_process_insns ( ) ; if ( ! TARGET_MIPS16 && TARGET_EXPLICIT_RELOCS && TUNE_MIPS4130 && TARGET_VR4130_ALIGN ) vr4130_align_insns ( ) ; if ( mips_expand_ghost_gp_insns ( ) ) mips_reorg_process_insns ( ) ; mips16_split_long_branches ( ) ; mips_insert_insn_pseudos ( ) ; return 0 ; } </s>

We use a machine specific pass to do a second machine dependent reorg pass after delay branch scheduling .


<s> static bool arc_use_by_pieces_infrastructure_p ( unsigned HOST_WIDE_INT size , unsigned int align , enum by_pieces_operation op , bool speed_p ) { if ( op == MOVE_BY_PIECES ) return false ; return default_use_by_pieces_infrastructure_p ( size , align , op , speed_p ) ; } </s>


<s> enum aarch64_symbol_type aarch64_classify_symbol ( rtx x , rtx offset , enum aarch64_symbol_context context ATTRIBUTE_UNUSED ) { if ( GET_CODE ( x ) == LABEL_REF ) { switch ( aarch64_cmodel ) { case AARCH64_CMODEL_LARGE : return SYMBOL_FORCE_TO_MEM ; case AARCH64_CMODEL_TINY_PIC : case AARCH64_CMODEL_TINY : return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL_PIC : case AARCH64_CMODEL_SMALL : return SYMBOL_SMALL_ABSOLUTE ; default : gcc_unreachable ( ) ; } } if ( GET_CODE ( x ) == SYMBOL_REF ) { if ( aarch64_cmodel == AARCH64_CMODEL_LARGE ) return SYMBOL_FORCE_TO_MEM ; if ( aarch64_tls_symbol_p ( x ) ) return aarch64_classify_tls_symbol ( x ) ; switch ( aarch64_cmodel ) { case AARCH64_CMODEL_TINY : if ( SYMBOL_REF_WEAK ( x ) || INTVAL ( offset ) < - 1048575 || INTVAL ( offset ) > 1048575 ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL : if ( SYMBOL_REF_WEAK ( x ) || ! IN_RANGE ( INTVAL ( offset ) , HOST_WIDE_INT_C ( - 4294967263 ) , HOST_WIDE_INT_C ( 4294967264 ) ) ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_SMALL_ABSOLUTE ; case AARCH64_CMODEL_TINY_PIC : if ( ! aarch64_symbol_binds_local_p ( x ) ) return SYMBOL_TINY_GOT ; return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL_PIC : if ( ! aarch64_symbol_binds_local_p ( x ) ) return SYMBOL_SMALL_GOT ; return SYMBOL_SMALL_ABSOLUTE ; default : gcc_unreachable ( ) ; } } return SYMBOL_FORCE_TO_MEM ; } </s>

Return the method that should be used to access SYMBOL_REF or LABEL_REF X .


<s>
bool
Mips16HardFloat
::
runOnModule
(
Module
&
M
)
{
DEBUG
(
errs
(
)
<<
"Run on Module Mips16HardFloat\n"
)
;
bool
Modified
=
false
;
for
(
Module
::
iterator
F
=
M
.
begin
(
)
,
E
=
M
.
end
(
)
;
F
!=
E
;
++
F
)
{
if
(
F
->
hasFnAttribute
(
"nomips16"
)
&&
F
->
hasFnAttribute
(
"use-soft-float"
)
)
{
removeUseSoftFloat
(
*
F
)
;
continue
;
}
if
(
F
->
isDeclaration
(
)
||
F
->
hasFnAttribute
(
"mips16_fp_stub"
)
||
F
->
hasFnAttribute
(
"nomips16"
)
)
continue
;
Modified
|=
fixupFPReturnAndCall
(
*
F
,
&
M
,
Subtarget
)
;
FPParamVariant
V
=
whichFPParamVariantNeeded
(
*
F
)
;
if
(
V
!=
NoSig
)
{
Modified
=
true
;
createFPFnStub
(
F
,
&
M
,
V
,
Subtarget
)
;
}
}
return
Modified
;
}
</s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


"\taddl r14 = @ltoff(@fptr(_mcount)), r1\n"

"\tbr.call.sptk.many b0 = _mcount\n\t;;\n"


<s> const NVPTXGenericMCSymbolRefExpr * NVPTXGenericMCSymbolRefExpr :: create ( const MCSymbolRefExpr * SymExpr , MCContext & Ctx ) { return new ( Ctx ) NVPTXGenericMCSymbolRefExpr ( SymExpr ) ; } </s>


<s> void push_back ( T V ) { if ( Set . count ( V ) ) return ; Queue . push ( V ) ; Set . insert ( V ) ; } </s>

Insert a node at the back ; never copies .


<s> bool loongarch_signed_immediate_p ( unsigned HOST_WIDE_INT x , int bits , int shift = 0 ) { x += 1 << ( bits + shift - 1 ) ; return loongarch_unsigned_immediate_p ( x , bits , shift ) ; } </s>

Return true if X fits within a signed field of BITS bits that is shifted left SHIFT bits before being used .


<s> bool RISCVInstrInfo :: isMBBSafeToOutlineFrom ( MachineBasicBlock & MBB , unsigned & Flags ) const { return true ; } </s>

Optional target hook that returns true if MBB is safe to outline from , and returns any target-specific information in Flags .


<s> bool BPFInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . end ( ) ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! isUnpredicatedTerminator ( * I ) ) break ; if ( ! I -> isBranch ( ) ) return true ; if ( I -> getOpcode ( ) == BPF :: JMP ) { if ( ! AllowModify ) { TBB = I -> getOperand ( 0 ) . getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = nullptr ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( 0 ) . getMBB ( ) ) ) { TBB = nullptr ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( 0 ) . getMBB ( ) ; continue ; } return true ; } return false ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s>
unsigned
WebAssemblyInstrInfo
::
insertBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
TBB
,
MachineBasicBlock
*
FBB
,
ArrayRef
<
MachineOperand
>
Cond
,
const
DebugLoc
&
DL
,
int
*
BytesAdded
)
const
{
assert
(
!
BytesAdded
&&
"code size not handled"
)
;
if
(
Cond
.
empty
(
)
)
{
if
(
!
TBB
)
return
0
;
BuildMI
(
&
MBB
,
DL
,
get
(
WebAssembly
::
BR
)
)
.
addMBB
(
TBB
)
;
return
1
;
}
assert
(
Cond
.
size
(
)
==
2
&&
"Expected a flag and a successor block"
)
;
if
(
Cond
[
0
]
.
getImm
(
)
)
{
BuildMI
(
&
MBB
,
DL
,
get
(
WebAssembly
::
BR_IF
)
)
.
addMBB
(
TBB
)
.
add
(
Cond
[
1
]
)
;
}
else
{
BuildMI
(
&
MBB
,
DL
,
get
(
WebAssembly
::
BR_UNLESS
)
)
.
addMBB
(
TBB
)
.
add
(
Cond
[
1
]
)
;
}
if
(
!
FBB
)
return
1
;
BuildMI
(
&
MBB
,
DL
,
get
(
WebAssembly
::
BR
)
)
.
addMBB
(
FBB
)
;
return
2
;
}
</s>

Insert branch code into the end of the specified MachineBasicBlock .


<s> bool aarch64_prepare_sve_int_fma ( rtx * operands , rtx_code code ) { machine_mode mode = GET_MODE ( operands [ 0 ] ) ; if ( rtx shifts = aarch64_convert_mult_to_shift ( operands [ 2 ] , code ) ) { rtx product = expand_binop ( mode , vashl_optab , operands [ 1 ] , shifts , NULL_RTX , true , OPTAB_DIRECT ) ; force_expand_binop ( mode , code == PLUS ? add_optab : sub_optab , operands [ 3 ] , product , operands [ 0 ] , true , OPTAB_DIRECT ) ; return true ; } operands [ 2 ] = force_reg ( mode , operands [ 2 ] ) ; return false ; } </s>

Prepare for an integer SVE multiply-add or multiply-subtract pattern ; CODE is PLUS for the former and MINUS for the latter . OPERANDS is the operands array , in the same order as for fma_optab . Return true if the function emitted all the necessary instructions , false if the caller should generate the pattern normally with the new OPERANDS array .


<s> BitVector MipsRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t ReservedCPURegs [ ] = { Mips :: ZERO , Mips :: K0 , Mips :: K1 , Mips :: SP } ; static const uint16_t ReservedCPU64Regs [ ] = { Mips :: ZERO_64 , Mips :: K0_64 , Mips :: K1_64 , Mips :: SP_64 } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: const_iterator RegIter ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPU64Regs ) ; ++ I ) Reserved . set ( ReservedCPU64Regs [ I ] ) ; if ( Subtarget . hasMips64 ( ) ) { for ( RegIter Reg = Mips :: AFGR64RegClass . begin ( ) , EReg = Mips :: AFGR64RegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } else { for ( RegIter Reg = Mips :: FGR64RegClass . begin ( ) , EReg = Mips :: FGR64RegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) ) { if ( Subtarget . inMips16Mode ( ) ) Reserved . set ( Mips :: S0 ) ; else { Reserved . set ( Mips :: FP ) ; Reserved . set ( Mips :: FP_64 ) ; } } Reserved . set ( Mips :: HWR29 ) ; Reserved . set ( Mips :: HWR29_64 ) ; Reserved . set ( Mips :: DSPPos ) ; Reserved . set ( Mips :: DSPSCount ) ; Reserved . set ( Mips :: DSPCarry ) ; Reserved . set ( Mips :: DSPEFI ) ; Reserved . set ( Mips :: DSPOutFlag ) ; if ( Subtarget . inMips16Mode ( ) ) { Reserved . set ( Mips :: RA ) ; Reserved . set ( Mips :: RA_64 ) ; } if ( Subtarget . useSmallSection ( ) ) { Reserved . set ( Mips :: GP ) ; Reserved . set ( Mips :: GP_64 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool MOSPassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( ) ) ; return false ; } </s>

This method should install a ( global ) instruction selector pass , which converts possibly generic instructions to fully target-specific instructions , thereby constraining all generic virtual registers to register classes .


<s> static fixed_size_mode aarch64_get_reg_raw_mode ( int regno ) { if ( TARGET_SVE && FP_REGNUM_P ( regno ) ) return as_a < fixed_size_mode > ( V16QImode ) ; return default_get_reg_raw_mode ( regno ) ; } </s>


<s> uint64_t RawVectorOstream :: current_pos ( ) const { return static_cast < uint64_t > ( Position ) ; } </s>

Return the current position within the stream , not counting the bytes currently in the buffer .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
Kind
==
Register
&&
"Invalid access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s> void MBlazeTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; SmallDataSection = getELFSection ( ".sdata" , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_WRITE | MCSectionELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getELFSection ( ".sbss" , MCSectionELF :: SHT_NOBITS , MCSectionELF :: SHF_WRITE | MCSectionELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s> rtx gen_df_reg ( rtx reg , int low ) { int regno = REGNO ( reg ) ; if ( ( WORDS_BIG_ENDIAN == 0 ) ^ ( low != 0 ) ) regno += ( TARGET_ARCH64 && SPARC_INT_REG_P ( regno ) ) ? 1 : 2 ; return gen_rtx_REG ( DFmode , regno ) ; } </s>

Generate a DFmode part of a hard TFmode register . REG is the TFmode hard register , LOW is 1 for the low 64bit of the register and 0 otherwise .


<s> unsigned mmix_debugger_regno ( unsigned regno ) { regno = MMIX_OUTPUT_REGNO ( regno ) ; return regno >= 224 ? ( regno - 224 ) : ( regno + 48 ) ; } </s>


<s>
bool
ARCFrameLowering
::
restoreCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Restore callee saved registers: "
<<
MBB
.
getParent
(
)
->
getName
(
)
<<
"\n"
)
;
unsigned
Last
=
determineLastCalleeSave
(
CSI
)
;
if
(
UseSaveRestoreFunclet
&&
Last
>
ARC
::
R14
)
{
return
true
;
}
return
false
;
}
</s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .

ARC
ARC
"Restore callee saved registers: "
"\n"
ARC::R14


<s> void mips_expand_atomic_qihi ( union mips_gen_fn_ptrs generator , rtx result , rtx mem , rtx oldval , rtx newval ) { rtx orig_addr , memsi_addr , memsi , shift , shiftsi , unshifted_mask ; rtx unshifted_mask_reg , mask , inverted_mask , si_op ; rtx res = NULL ; machine_mode mode ; mode = GET_MODE ( mem ) ; orig_addr = force_reg ( Pmode , XEXP ( mem , 0 ) ) ; memsi_addr = mips_force_binary ( Pmode , AND , orig_addr , force_reg ( Pmode , GEN_INT ( - 4 ) ) ) ; memsi = gen_rtx_MEM ( SImode , memsi_addr ) ; set_mem_alias_set ( memsi , ALIAS_SET_MEMORY_BARRIER ) ; MEM_VOLATILE_P ( memsi ) = MEM_VOLATILE_P ( mem ) ; shift = mips_force_binary ( Pmode , AND , orig_addr , GEN_INT ( 3 ) ) ; if ( TARGET_BIG_ENDIAN ) mips_emit_binary ( XOR , shift , shift , GEN_INT ( mode == QImode ? 3 : 2 ) ) ; mips_emit_binary ( ASHIFT , shift , shift , GEN_INT ( 3 ) ) ; shiftsi = force_reg ( SImode , gen_lowpart ( SImode , shift ) ) ; unshifted_mask = GEN_INT ( GET_MODE_MASK ( mode ) ) ; unshifted_mask_reg = force_reg ( SImode , unshifted_mask ) ; mask = mips_force_binary ( SImode , ASHIFT , unshifted_mask_reg , shiftsi ) ; inverted_mask = gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( inverted_mask , gen_rtx_NOT ( SImode , mask ) ) ) ; if ( oldval != const0_rtx ) { oldval = convert_modes ( SImode , mode , oldval , true ) ; oldval = force_reg ( SImode , oldval ) ; oldval = mips_force_binary ( SImode , ASHIFT , oldval , shiftsi ) ; } if ( newval && newval != const0_rtx ) { newval = convert_modes ( SImode , mode , newval , true ) ; newval = force_reg ( SImode , newval ) ; newval = mips_force_binary ( SImode , ASHIFT , newval , shiftsi ) ; } if ( result ) res = gen_reg_rtx ( SImode ) ; if ( newval ) si_op = generator . fn_6 ( res , memsi , mask , inverted_mask , oldval , newval ) ; else if ( result ) si_op = generator . fn_5 ( res , memsi , mask , inverted_mask , oldval ) ; else si_op = generator . fn_4 ( memsi , mask , inverted_mask , oldval ) ; emit_insn ( si_op ) ; if ( result ) { mips_emit_binary ( AND , res , res , mask ) ; mips_emit_binary ( LSHIFTRT , res , res , shiftsi ) ; mips_emit_move ( result , gen_lowpart ( GET_MODE ( result ) , res ) ) ; } } </s>

Expand a QI or HI mode atomic memory operation . GENERATOR contains a pointer to the gen_ * function that generates the SI mode underlying atomic operation using masks that we calculate . RESULT is the return register for the operation . Its value is NULL if unused . MEM is the location of the atomic access . OLDVAL is the first operand for the operation . NEWVAL is the optional second operand for the operation . Its value is NULL if unused .


<s> static bool avr_2word_insn_p ( rtx_insn * insn ) { if ( TARGET_SKIP_BUG || ! insn || get_attr_length ( insn ) != 2 ) { return false ; } switch ( INSN_CODE ( insn ) ) { default : return false ; case CODE_FOR_movqi_insn : case CODE_FOR_movuqq_insn : case CODE_FOR_movqq_insn : { rtx set = single_set ( insn ) ; rtx src = SET_SRC ( set ) ; rtx dest = SET_DEST ( set ) ; if ( MEM_P ( dest ) && ( REG_P ( src ) || src == CONST0_RTX ( GET_MODE ( dest ) ) ) ) { return CONSTANT_ADDRESS_P ( XEXP ( dest , 0 ) ) ; } else if ( REG_P ( dest ) && MEM_P ( src ) ) { return CONSTANT_ADDRESS_P ( XEXP ( src , 0 ) ) ; } return false ; } case CODE_FOR_call_insn : case CODE_FOR_call_value_insn : return true ; } } </s>

Helper for jump_over_one_insn_p : Test if INSN is a 2-word instruction and thus is suitable to be skipped by CPSE , SBRC , etc .


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { const ARMSubtarget & Subtarget = DAG . getTarget ( ) . getSubtarget < ARMSubtarget > ( ) ; if ( Subtarget . isTargetNaCl ( ) || ! EnableARMAEABIFunctions || ! Subtarget . isAAPCS_ABI ( ) || Subtarget . isTargetMachO ( ) || Subtarget . isTargetWindows ( ) ) return SDValue ( ) ; const ARMTargetLowering & TLI = * static_cast < const ARMTargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Type * IntPtrTy = TLI . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( MVT :: i32 ) ) Src = DAG . getNode ( ISD :: TRUNCATE , dl , MVT :: i32 , Src ) ; else Src = DAG . getNode ( ISD :: ZERO_EXTEND , dl , MVT :: i32 , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , std :: move ( Args ) , 0 ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } </s>

Emit target-specific code that performs a memset .


<s> unsigned getNumFixupKinds ( ) const { return TOY :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> static rtx_insn * cris_md_asm_adjust ( vec < rtx > & outputs , vec < rtx > & inputs , vec < machine_mode > & , vec < const char * > & constraints , vec < rtx > & clobbers , HARD_REG_SET & clobbered_regs , location_t ) { clobbers . safe_push ( gen_rtx_REG ( CCmode , CRIS_CC0_REGNUM ) ) ; SET_HARD_REG_BIT ( clobbered_regs , CRIS_CC0_REGNUM ) ; for ( unsigned i = 0 , n = constraints . length ( ) ; i < n ; ++ i ) if ( strchr ( constraints [ i ] , 'h' ) != NULL ) return NULL ; rtx mof_reg = gen_rtx_REG ( SImode , CRIS_MOF_REGNUM ) ; for ( unsigned i = 0 , n = outputs . length ( ) ; i < n ; ++ i ) if ( reg_overlap_mentioned_p ( mof_reg , outputs [ i ] ) ) return NULL ; for ( unsigned i = 0 , n = inputs . length ( ) ; i < n ; ++ i ) if ( reg_overlap_mentioned_p ( mof_reg , inputs [ i ] ) ) return NULL ; clobbers . safe_push ( mof_reg ) ; SET_HARD_REG_BIT ( clobbered_regs , CRIS_MOF_REGNUM ) ; return NULL ; } </s>

Worker function for TARGET_MD_ASM_ADJUST .


<s> static tree nvptx_builtin_decl ( unsigned code , bool ARG_UNUSED ( initialize_p ) ) { if ( code >= NVPTX_BUILTIN_MAX ) return error_mark_node ; return nvptx_builtin_decls [ code ] ; } </s>


<s> InstructionCost AArch64TargetLowering :: getScalingFactorCost ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( isLegalAddressingMode ( DL , AM , Ty , AS ) ) return AM . Scale != 0 && AM . Scale != 1 ; return - 1 ; } </s>

Return the cost of the scaling factor used in the addressing mode represented by AM for this target , for a load/store of the specified type .


<s> bool Thumb2SizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { const TargetMachine & TM = MF . getTarget ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( TM . getInstrInfo ( ) ) ; STI = & TM . getSubtarget < ARMSubtarget > ( ) ; AttributeSet FnAttrs = MF . getFunction ( ) -> getAttributes ( ) ; OptimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; MinimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ; bool Modified = false ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) Modified |= ReduceMBB ( * I ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


"Cannot emit contents before setting section!"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void BTFDebug :: beginInstruction ( const MachineInstr * MI ) { DebugHandlerBase :: beginInstruction ( MI ) ; if ( SkipInstruction || MI -> isMetaInstruction ( ) || MI -> getFlag ( MachineInstr :: FrameSetup ) ) return ; if ( MI -> isInlineAsm ( ) ) { unsigned NumDefs = 0 ; for ( ; MI -> getOperand ( NumDefs ) . isReg ( ) && MI -> getOperand ( NumDefs ) . isDef ( ) ; ++ NumDefs ) ; const char * AsmStr = MI -> getOperand ( NumDefs ) . getSymbolName ( ) ; if ( AsmStr [ 0 ] == 0 ) return ; } if ( MI -> getOpcode ( ) == BPF :: LD_imm64 ) { processReloc ( MI -> getOperand ( 1 ) ) ; } else if ( MI -> getOpcode ( ) == BPF :: CORE_MEM || MI -> getOpcode ( ) == BPF :: CORE_ALU32_MEM || MI -> getOpcode ( ) == BPF :: CORE_SHIFT ) { processReloc ( MI -> getOperand ( 3 ) ) ; } const DebugLoc & DL = MI -> getDebugLoc ( ) ; if ( ! DL || PrevInstLoc == DL ) { if ( LineInfoGenerated == false ) { auto * S = MI -> getMF ( ) -> getFunction ( ) . getSubprogram ( ) ; MCSymbol * FuncLabel = Asm -> getFunctionBegin ( ) ; constructLineInfo ( S , FuncLabel , S -> getLine ( ) , 0 ) ; LineInfoGenerated = true ; } return ; } MCSymbol * LineSym = OS . getContext ( ) . createTempSymbol ( ) ; OS . EmitLabel ( LineSym ) ; auto SP = DL . get ( ) -> getScope ( ) -> getSubprogram ( ) ; constructLineInfo ( SP , LineSym , DL . getLine ( ) , DL . getCol ( ) ) ; LineInfoGenerated = true ; PrevInstLoc = DL ; } </s>


<s> bool isFMAFasterThanFMulAndFAdd ( EVT ) const override { return true ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return this -> TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> LoadInst * getLoad ( ) { return NewLd ; } </s>

Loads are not normal binary operators : their result type is not determined by their operands , and they produce a value AND a token chain .


<s> bool microblaze_legitimate_address_p ( machine_mode mode , rtx x , bool strict ) { struct microblaze_address_info addr ; return microblaze_classify_address ( & addr , x , mode , strict ) ; } </s>

This function is used to implement GO_IF_LEGITIMATE_ADDRESS . It returns a nonzero value if X is a legitimate address for a memory operand of the indicated MODE . STRICT is nonzero if this function is called during reload .


<s> std :: vector < SIScheduleBlock * > getBlocks ( ) { return BlocksScheduled ; } </s>

Get a list of the basic blocks which make up this loop .


<s> bool Thumb2SizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { if ( PredicateFtor && ! PredicateFtor ( MF . getFunction ( ) ) ) return false ; STI = & static_cast < const ARMSubtarget & > ( MF . getSubtarget ( ) ) ; if ( STI -> isThumb1Only ( ) || STI -> prefers32BitThumb ( ) ) return false ; TII = static_cast < const Thumb2InstrInfo * > ( STI -> getInstrInfo ( ) ) ; OptimizeSize = MF . getFunction ( ) . optForSize ( ) ; MinimizeSize = STI -> optForMinSize ( ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; ReversePostOrderTraversal < MachineFunction * > RPOT ( & MF ) ; bool Modified = false ; for ( ReversePostOrderTraversal < MachineFunction * > :: rpo_iterator I = RPOT . begin ( ) , E = RPOT . end ( ) ; I != E ; ++ I ) Modified |= ReduceMBB ( * * I ) ; return Modified ; } </s>


<s> static rtx set_frame_related_p ( ) { rtx seq = gen_sequence ( ) ; end_sequence ( ) ; if ( GET_CODE ( seq ) == SEQUENCE ) { int i = XVECLEN ( seq , 0 ) ; while ( -- i >= 0 ) RTX_FRAME_RELATED_P ( XVECEXP ( seq , 0 , i ) ) = 1 ; return emit_insn ( seq ) ; } else { seq = emit_insn ( seq ) ; RTX_FRAME_RELATED_P ( seq ) = 1 ; return seq ; } } </s>

Helper function to set RTX_FRAME_RELATED_P on instructions , including sequences .


<s> void finishLayout ( MCAssembler const & Asm , MCAsmLayout & Layout ) const override { for ( auto I : Layout . getSectionOrder ( ) ) { auto & Fragments = I -> getFragmentList ( ) ; for ( auto & J : Fragments ) { switch ( J . getKind ( ) ) { default : break ; case MCFragment :: FT_Align : { auto Size = Asm . computeFragmentSize ( Layout , J ) ; for ( auto K = J . getIterator ( ) ; K != Fragments . begin ( ) && Size >= HEXAGON_PACKET_SIZE ; ) { -- K ; switch ( K -> getKind ( ) ) { default : break ; case MCFragment :: FT_Align : { Size = 0 ; break ; } case MCFragment :: FT_Relaxable : { MCContext & Context = Asm . getContext ( ) ; auto & RF = cast < MCRelaxableFragment > ( * K ) ; auto & Inst = const_cast < MCInst & > ( RF . getInst ( ) ) ; while ( Size > 0 && HexagonMCInstrInfo :: bundleSize ( Inst ) < 4 ) { MCInst * Nop = new ( Context ) MCInst ; Nop -> setOpcode ( Hexagon :: A2_nop ) ; Inst . addOperand ( MCOperand :: createInst ( Nop ) ) ; Size -= 4 ; if ( ! HexagonMCChecker ( Context , * MCII , RF . getSubtargetInfo ( ) , Inst , * Context . getRegisterInfo ( ) , false ) . check ( ) ) { Inst . erase ( Inst . end ( ) - 1 ) ; Size = 0 ; } } bool Error = HexagonMCShuffle ( Context , true , * MCII , RF . getSubtargetInfo ( ) , Inst ) ; ( void ) Error ; ReplaceInstruction ( Asm . getEmitter ( ) , RF , Inst ) ; Layout . invalidateFragmentsFrom ( & RF ) ; Size = 0 ; break ; } } } } } } } } </s>

Give backend an opportunity to finish layout after relaxation .


<s> const TargetRegisterClass * PPCRegisterInfo :: getPointerRegClass ( unsigned Kind ) const { if ( Subtarget . isPPC64 ( ) ) return & PPC :: G8RCRegClass ; return & PPC :: GPRCRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .

PowerPC PPC PPC PPC::G8RCRegClass PPC::GPRCRegClass


<s>
const
char
*
output_probe_stack_range
(
rtx
reg1
,
rtx
reg2
)
{
static
int
labelno
=
0
;
char
loop_lab
[
32
]
;
rtx
xops
[
2
]
;
ASM_GENERATE_INTERNAL_LABEL
(
loop_lab
,
"LPSRL"
,
labelno
++
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
loop_lab
)
;
xops
[
0
]
=
reg1
;
xops
[
1
]
=
GEN_INT
(
PROBE_INTERVAL
)
;
output_asm_insn
(
"add\t%0, %1, %0"
,
xops
)
;
xops
[
1
]
=
reg2
;
output_asm_insn
(
"cmp\t%0, %1"
,
xops
)
;
if
(
TARGET_ARCH64
)
fputs
(
"\tbne,pt\t%xcc,"
,
asm_out_file
)
;
else
fputs
(
"\tbne\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
loop_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
xops
[
1
]
=
GEN_INT
(
SPARC_STACK_BIAS
)
;
output_asm_insn
(
" st\t%%g0, [%0+%1]"
,
xops
)
;
return
""
;
}
</s>

Wrapper around the output_probe_stack_range routines .


<s> void GBZ80InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { unsigned Opcode = MI -> getOpcode ( ) ; switch ( Opcode ) { default : if ( ! printAliasInstr ( MI , O ) ) printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; break ; } } </s>

Print the specified MCInst to the specified raw_ostream .


<s> unsigned getExplicitKernelArgOffset ( const MachineFunction & MF ) const { return isAmdCodeObjectV2 ( MF ) ? 0 : 36 ; } </s>

Returns the offset in bytes from the start of the input buffer of the first explicit kernel argument .


<s> bool HexagonBitSimplify :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; auto & HST = MF . getSubtarget < HexagonSubtarget > ( ) ; auto & HRI = * HST . getRegisterInfo ( ) ; auto & HII = * HST . getInstrInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool Changed ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) ; const HexagonEvaluator HE ( HRI , MRI , HII , MF ) ; BitTracker BT ( HE , MF ) ; LLVM_DEBUG ( BT . trace ( true ) ) ; BT . run ( ) ; MachineBasicBlock & Entry = MF . front ( ) ; RegisterSet AIG ; ConstGeneration ImmG ( BT , HII , MRI ) ; Changed |= visitBlock ( Entry , ImmG , AIG ) ; RegisterSet ARE ; RedundantInstrElimination RIE ( BT , HII , HRI , MRI ) ; bool Ried = visitBlock ( Entry , RIE , ARE ) ; if ( Ried ) { Changed = true ; BT . run ( ) ; } RegisterSet ACG ; CopyGeneration CopyG ( BT , HII , HRI , MRI ) ; Changed |= visitBlock ( Entry , CopyG , ACG ) ; RegisterSet ACP ; CopyPropagation CopyP ( HRI , MRI ) ; Changed |= visitBlock ( Entry , CopyP , ACP ) ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) || Changed ; BT . run ( ) ; RegisterSet ABS ; BitSimplification BitS ( BT , * MDT , HII , HRI , MRI , MF ) ; Changed |= visitBlock ( Entry , BitS , ABS ) ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) || Changed ; if ( Changed ) { for ( auto & B : MF ) for ( auto & I : B ) I . clearKillInfo ( ) ; DeadCodeElimination ( MF , * MDT ) . run ( ) ; } return Changed ; } </s>


<s> void WebAssemblyInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { BuildMI ( MBB , I , DL , get ( WebAssembly :: COPY ) , DestReg ) . addReg ( SrcReg , KillSrc ? RegState :: Kill : 0 ) ; } </s>

WebAssembly WebAssembly WebAssembly::COPY 0


<s> bool isReg ( ) const override { return isRegKind ( ) && ! hasModifiers ( ) ; } </s>


<s> const R600RegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> Register SIRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const SIFrameLowering * TFI = ST . getFrameLowering ( ) ; const SIMachineFunctionInfo * FuncInfo = MF . getInfo < SIMachineFunctionInfo > ( ) ; if ( FuncInfo -> isEntryFunction ( ) ) { return TFI -> hasFP ( MF ) ? FuncInfo -> getFrameOffsetReg ( ) : Register ( ) ; } return TFI -> hasFP ( MF ) ? FuncInfo -> getFrameOffsetReg ( ) : FuncInfo -> getStackPtrOffsetReg ( ) ; } </s>


<s>
void
ARMAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsPCRel
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
Value
=
adjustFixupValue
(
Asm
,
Fixup
,
Target
,
Value
,
IsPCRel
,
Ctx
,
IsLittleEndian
,
true
)
;
if
(
!
Value
)
return
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
unsigned
FullSizeBytes
;
if
(
!
IsLittleEndian
)
{
FullSizeBytes
=
getFixupKindContainerSizeBytes
(
Fixup
.
getKind
(
)
)
;
assert
(
(
Offset
+
FullSizeBytes
)
<=
Data
.
size
(
)
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FullSizeBytes
&&
"Invalid fixup size!"
)
;
}
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
IsLittleEndian
i
:
(
FullSizeBytes
1
i
)
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static int m16_check_op ( rtx op , int low , int high , int mask ) { return ( GET_CODE ( op ) == CONST_INT && INTVAL ( op ) >= low && INTVAL ( op ) <= high && ( INTVAL ( op ) & mask ) == 0 ) ; } </s>

We need a lot of little routines to check constant values on the mips16 . These are used to figure out how long the instruction will be . It would be much better to do this using constraints , but there are n't nearly enough letters available .