<s> static bool rs6000_function_ok_for_sibcall ( tree decl , tree exp ) { tree fntype ; if ( decl ) fntype = TREE_TYPE ( decl ) ; else fntype = TREE_TYPE ( TREE_TYPE ( CALL_EXPR_FN ( exp ) ) ) ; if ( TARGET_ALTIVEC_ABI && TARGET_ALTIVEC_VRSAVE && ! ( decl && decl == current_function_decl ) ) { function_args_iterator args_iter ; tree type ; int nvreg = 0 ; FOREACH_FUNCTION_ARGS ( fntype , type , args_iter ) if ( TREE_CODE ( type ) == VECTOR_TYPE && ALTIVEC_OR_VSX_VECTOR_MODE ( TYPE_MODE ( type ) ) ) nvreg ++ ; FOREACH_FUNCTION_ARGS ( TREE_TYPE ( current_function_decl ) , type , args_iter ) if ( TREE_CODE ( type ) == VECTOR_TYPE && ALTIVEC_OR_VSX_VECTOR_MODE ( TYPE_MODE ( type ) ) ) nvreg -- ; if ( nvreg > 0 ) return false ; } if ( DEFAULT_ABI == ABI_DARWIN || ( ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) && decl && ! DECL_EXTERNAL ( decl ) && ( * targetm . binds_local_p ) ( decl ) ) || ( DEFAULT_ABI == ABI_V4 && ( ! TARGET_SECURE_PLT || ! flag_pic || ( decl && ( * targetm . binds_local_p ) ( decl ) ) ) ) ) { tree attr_list = TYPE_ATTRIBUTES ( fntype ) ; if ( ! lookup_attribute ( "longcall" , attr_list ) || lookup_attribute ( "shortcall" , attr_list ) ) return true ; } return false ; } </s>

Say whether a function is a candidate for sibcall handling or not . We do not allow indirect calls to be optimized into sibling calls . Also , we ca n't do it if there are any vector parameters ; there 's nowhere to put the VRsave code so it works ; note that functions with vector parameters are required to have a prototype , so the argument type info must be available here . ( The tail recursion case can work with vector parameters , but there 's no way to distinguish here . )


<s> SDValue X86TargetLowering :: getPICJumpTableRelocBase ( SDValue Table , SelectionDAG & DAG ) const { if ( ! Subtarget . is64Bit ( ) ) return DAG . getNode ( X86ISD :: GlobalBaseReg , SDLoc ( ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; return Table ; } </s>

Returns relocation base for the given PIC jumptable .


<s> static inline bool current_function_saves_lr ( void ) { return current_frame_info . save_lr != 0 ; } </s>

Accessor for current_frame_info.save_lr .


<s>
void
BlockWaitcntBrackets
::
print
(
raw_ostream
&
OS
)
{
OS
<<
'\n'
;
for
(
enum
InstCounterType
T
=
VM_CNT
;
T
<
NUM_INST_CNTS
;
T
=
(
enum
InstCounterType
)
(
T
+
1
)
)
{
int
LB
=
getScoreLB
(
T
)
;
int
UB
=
getScoreUB
(
T
)
;
switch
(
T
)
{
case
VM_CNT
:
OS
<<
"    VM_CNT("
<<
UB
LB
<<
"): "
;
break
;
case
LGKM_CNT
:
OS
<<
"    LGKM_CNT("
<<
UB
LB
<<
"): "
;
break
;
case
EXP_CNT
:
OS
<<
"    EXP_CNT("
<<
UB
LB
<<
"): "
;
break
;
default
:
OS
<<
"    UNKNOWN("
<<
UB
LB
<<
"): "
;
break
;
}
if
(
LB
<
UB
)
{
for
(
int
J
=
0
;
J
<=
getMaxVGPR
(
)
;
J
++
)
{
int
RegScore
=
getRegScore
(
J
,
T
)
;
if
(
RegScore
<=
LB
)
continue
;
int
RelScore
=
RegScore
LB
1
;
if
(
J
<
SQ_MAX_PGM_VGPRS
+
EXTRA_VGPR_LDS
)
{
OS
<<
RelScore
<<
":v"
<<
J
<<
" "
;
}
else
{
OS
<<
RelScore
<<
":ds "
;
}
}
if
(
T
==
LGKM_CNT
)
{
for
(
int
J
=
0
;
J
<=
getMaxSGPR
(
)
;
J
++
)
{
int
RegScore
=
getRegScore
(
J
+
NUM_ALL_VGPRS
,
LGKM_CNT
)
;
if
(
RegScore
<=
LB
)
continue
;
int
RelScore
=
RegScore
LB
1
;
OS
<<
RelScore
<<
":s"
<<
J
<<
" "
;
}
}
}
OS
<<
'\n'
;
}
OS
<<
'\n'
;
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> void init_convex ( ) { int regno ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( A_REGNO_P ( regno ) ) { regno_ok_for_index_p [ regno ] = 1 ; regno_reg_class [ regno ] = INDEX_REGS ; } else { regno_ok_for_index_p [ regno ] = 0 ; regno_reg_class [ regno ] = S_REGS ; } regno_ok_for_index_p [ STACK_POINTER_REGNUM ] = 0 ; regno_reg_class [ STACK_POINTER_REGNUM ] = SP_REGS ; regno_ok_for_index_p [ VIRTUAL_INCOMING_ARGS_REGNUM ] = 1 ; regno_ok_for_index_p [ VIRTUAL_STACK_VARS_REGNUM ] = 1 ; regno_ok_for_index_p [ VIRTUAL_STACK_DYNAMIC_REGNUM ] = 0 ; regno_ok_for_index_p [ VIRTUAL_OUTGOING_ARGS_REGNUM ] = 0 ; regno_ok_for_index_p [ - 1 ] = 0 ; reg_class_from_letter [ 'a' ] = A_REGS ; reg_class_from_letter [ 'A' ] = INDEX_REGS ; reg_class_from_letter [ 'd' ] = S_REGS ; psw_disable_float ( ) ; } </s>

Here from OVERRIDE_OPTIONS at startup . Initialize constant tables .


<s> bool Mips16DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { if ( ! Subtarget -> inMips16Mode ( ) ) return false ; return MipsDAGToDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> unsigned PPCInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == PPC :: INLINEASM ) { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } else if ( Opcode == TargetOpcode :: STACKMAP ) { StackMapOpers Opers ( & MI ) ; return Opers . getNumPatchBytes ( ) ; } else if ( Opcode == TargetOpcode :: PATCHPOINT ) { PatchPointOpers Opers ( & MI ) ; return Opers . getNumPatchBytes ( ) ; } else { const MCInstrDesc & Desc = get ( Opcode ) ; return Desc . getSize ( ) ; } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> bool GCNTTIImpl :: areInlineCompatible ( const Function * Caller , const Function * Callee ) const { const TargetMachine & TM = getTLI ( ) -> getTargetMachine ( ) ; const FeatureBitset & CallerBits = TM . getSubtargetImpl ( * Caller ) -> getFeatureBits ( ) ; const FeatureBitset & CalleeBits = TM . getSubtargetImpl ( * Callee ) -> getFeatureBits ( ) ; FeatureBitset RealCallerBits = CallerBits & ~ InlineFeatureIgnoreList ; FeatureBitset RealCalleeBits = CalleeBits & ~ InlineFeatureIgnoreList ; return ( ( RealCallerBits & RealCalleeBits ) == RealCalleeBits ) ; } </s>

Determine whether a callee with the given TLI can be inlined into caller with this TLI , based on 'nobuiltin ' attributes .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; ModulePass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
SUnit
*
ConvergingVLIWScheduler
::
pickNode
(
bool
&
IsTopNode
)
{
if
(
DAG
->
top
(
)
==
DAG
->
bottom
(
)
)
{
assert
(
Top
.
Available
.
empty
(
)
&&
Top
.
Pending
.
empty
(
)
&&
Bot
.
Available
.
empty
(
)
&&
Bot
.
Pending
.
empty
(
)
&&
"ReadyQ garbage"
)
;
return
nullptr
;
}
SUnit
*
SU
;
if
(
ForceTopDown
)
{
SU
=
Top
.
pickOnlyChoice
(
)
;
if
(
!
SU
)
{
SchedCandidate
TopCand
;
CandResult
TopResult
=
pickNodeFromQueue
(
Top
,
DAG
->
getTopRPTracker
(
)
,
TopCand
)
;
assert
(
TopResult
!=
NoCand
&&
"failed to find the first candidate"
)
;
(
void
)
TopResult
;
SU
=
TopCand
.
SU
;
}
IsTopNode
=
true
;
}
else
if
(
ForceBottomUp
)
{
SU
=
Bot
.
pickOnlyChoice
(
)
;
if
(
!
SU
)
{
SchedCandidate
BotCand
;
CandResult
BotResult
=
pickNodeFromQueue
(
Bot
,
DAG
->
getBotRPTracker
(
)
,
BotCand
)
;
assert
(
BotResult
!=
NoCand
&&
"failed to find the first candidate"
)
;
(
void
)
BotResult
;
SU
=
BotCand
.
SU
;
}
IsTopNode
=
false
;
}
else
{
SU
=
pickNodeBidrectional
(
IsTopNode
)
;
}
if
(
SU
->
isTopReady
(
)
)
Top
.
removeReady
(
SU
)
;
if
(
SU
->
isBottomReady
(
)
)
Bot
.
removeReady
(
SU
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"*** "
<<
(
IsTopNode
"Top"
:
"Bottom"
)
<<
" Scheduling instruction in cycle "
<<
(
IsTopNode
Top
.
CurrCycle
:
Bot
.
CurrCycle
)
<<
" ("
<<
reportPackets
(
)
<<
")\n"
;
DAG
->
dumpNode
(
*
SU
)
)
;
return
SU
;
}
</s>

Pick the next node to schedule , or return NULL .

Hexagon
"ReadyQ garbage"
"failed to find the first candidate"
"failed to find the first candidate"
"*** "
"Top"
"Bottom"
" Scheduling instruction in cycle "
" ("
")\n"


<s> bool ARMTargetLowering :: splitValueIntoRegisterParts ( SelectionDAG & DAG , const SDLoc & DL , SDValue Val , SDValue * Parts , unsigned NumParts , MVT PartVT , Optional < CallingConv :: ID > CC ) const { bool IsABIRegCopy = CC . hasValue ( ) ; EVT ValueVT = Val . getValueType ( ) ; if ( IsABIRegCopy && ( ValueVT == MVT :: f16 || ValueVT == MVT :: bf16 ) && PartVT == MVT :: f32 ) { unsigned ValueBits = ValueVT . getSizeInBits ( ) ; unsigned PartBits = PartVT . getSizeInBits ( ) ; Val = DAG . getNode ( ISD :: BITCAST , DL , MVT :: getIntegerVT ( ValueBits ) , Val ) ; Val = DAG . getNode ( ISD :: ANY_EXTEND , DL , MVT :: getIntegerVT ( PartBits ) , Val ) ; Val = DAG . getNode ( ISD :: BITCAST , DL , PartVT , Val ) ; Parts [ 0 ] = Val ; return true ; } return false ; } </s>

Target-specific splitting of values into parts that fit a register storing a legal type .


<s> static rtx mn10300_function_arg ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; rtx result = NULL_RTX ; int size ; int nregs = 2 ; size = arg . promoted_size_in_bytes ( ) ; cum -> nbytes = ( cum -> nbytes + 3 ) & ~ 3 ; if ( cum -> nbytes > nregs * UNITS_PER_WORD ) return result ; if ( arg . type == NULL_TREE && cum -> nbytes + size > nregs * UNITS_PER_WORD ) return result ; switch ( cum -> nbytes / UNITS_PER_WORD ) { case 0 : result = gen_rtx_REG ( arg . mode , FIRST_ARGUMENT_REGNUM ) ; break ; case 1 : result = gen_rtx_REG ( arg . mode , FIRST_ARGUMENT_REGNUM + 1 ) ; break ; default : break ; } return result ; } </s>

Return an RTX to represent where a value with mode MODE will be returned from a function . If the result is NULL_RTX , the argument is pushed .


<s> bool AMDGPUAsmPrinter :: doFinalization ( Module & M ) { CallGraphResourceInfo . clear ( ) ; if ( AMDGPU :: isGFX10 ( * getGlobalSTI ( ) ) ) { OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; getTargetStreamer ( ) -> EmitCodeEnd ( ) ; } return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> void EmitInstruction ( uint64_t Code , unsigned Size , raw_ostream & OS ) const { for ( unsigned i = 0 ; i < Size ; i ++ ) { EmitByte ( Code , OS ) ; Code >>= 8 ; } } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool rx_match_ccmode ( rtx insn , machine_mode cc_mode ) { rtx op1 , flags ; machine_mode flags_mode ; gcc_checking_assert ( XVECLEN ( PATTERN ( insn ) , 0 ) == 2 ) ; op1 = XVECEXP ( PATTERN ( insn ) , 0 , 0 ) ; gcc_checking_assert ( GET_CODE ( SET_SRC ( op1 ) ) == COMPARE ) ; flags = SET_DEST ( op1 ) ; flags_mode = GET_MODE ( flags ) ; if ( GET_MODE ( SET_SRC ( op1 ) ) != flags_mode ) return false ; if ( GET_MODE_CLASS ( flags_mode ) != MODE_CC ) return false ; if ( flags_from_mode ( flags_mode ) & ~ flags_from_mode ( cc_mode ) ) return false ; return true ; } </s>

A helper function for matching parallels that set the flags .


<s> static tree nvptx_lockless_update ( location_t loc , gimple_stmt_iterator * gsi , tree ptr , tree var , tree_code op ) { unsigned fn = NVPTX_BUILTIN_CMP_SWAP ; tree_code code = NOP_EXPR ; tree arg_type = unsigned_type_node ; tree var_type = TREE_TYPE ( var ) ; if ( TREE_CODE ( var_type ) == COMPLEX_TYPE || TREE_CODE ( var_type ) == REAL_TYPE ) code = VIEW_CONVERT_EXPR ; if ( TYPE_SIZE ( var_type ) == TYPE_SIZE ( long_long_unsigned_type_node ) ) { arg_type = long_long_unsigned_type_node ; fn = NVPTX_BUILTIN_CMP_SWAPLL ; } tree swap_fn = nvptx_builtin_decl ( fn , true ) ; gimple_seq init_seq = NULL ; tree init_var = make_ssa_name ( arg_type ) ; tree init_expr = omp_reduction_init_op ( loc , op , var_type ) ; init_expr = fold_build1 ( code , arg_type , init_expr ) ; gimplify_assign ( init_var , init_expr , & init_seq ) ; gimple * init_end = gimple_seq_last ( init_seq ) ; gsi_insert_seq_before ( gsi , init_seq , GSI_SAME_STMT ) ; basic_block pre_bb = gsi_bb ( * gsi ) ; edge pre_edge = split_block ( pre_bb , init_end ) ; basic_block loop_bb = pre_edge -> dest ; pre_bb = pre_edge -> src ; * gsi = gsi_for_stmt ( gsi_stmt ( * gsi ) ) ; tree expect_var = make_ssa_name ( arg_type ) ; tree actual_var = make_ssa_name ( arg_type ) ; tree write_var = make_ssa_name ( arg_type ) ; gimple_seq red_seq = NULL ; tree write_expr = fold_build1 ( code , var_type , expect_var ) ; write_expr = fold_build2 ( op , var_type , write_expr , var ) ; write_expr = fold_build1 ( code , arg_type , write_expr ) ; gimplify_assign ( write_var , write_expr , & red_seq ) ; gsi_insert_seq_before ( gsi , red_seq , GSI_SAME_STMT ) ; gimple_seq latch_seq = NULL ; tree swap_expr = build_call_expr_loc ( loc , swap_fn , 3 , ptr , expect_var , write_var ) ; gimplify_assign ( actual_var , swap_expr , & latch_seq ) ; gcond * cond = gimple_build_cond ( EQ_EXPR , actual_var , expect_var , NULL_TREE , NULL_TREE ) ; gimple_seq_add_stmt ( & latch_seq , cond ) ; gimple * latch_end = gimple_seq_last ( latch_seq ) ; gsi_insert_seq_before ( gsi , latch_seq , GSI_SAME_STMT ) ; edge post_edge = split_block ( loop_bb , latch_end ) ; basic_block post_bb = post_edge -> dest ; loop_bb = post_edge -> src ; * gsi = gsi_for_stmt ( gsi_stmt ( * gsi ) ) ; post_edge -> flags ^= EDGE_TRUE_VALUE | EDGE_FALLTHRU ; edge loop_edge = make_edge ( loop_bb , loop_bb , EDGE_FALSE_VALUE ) ; set_immediate_dominator ( CDI_DOMINATORS , loop_bb , pre_bb ) ; set_immediate_dominator ( CDI_DOMINATORS , post_bb , loop_bb ) ; gphi * phi = create_phi_node ( expect_var , loop_bb ) ; add_phi_arg ( phi , init_var , pre_edge , loc ) ; add_phi_arg ( phi , actual_var , loop_edge , loc ) ; loop * loop = alloc_loop ( ) ; loop -> header = loop_bb ; loop -> latch = loop_bb ; add_loop ( loop , loop_bb -> loop_father ) ; return fold_build1 ( code , var_type , write_var ) ; } </s>

Insert code to locklessly update * PTR with * PTR OP VAR just before GSI . We use a lockless scheme for nearly all case , which looks like : actual = initval ( OP ) ; do { guess = actual ; write = guess OP myval ; actual = cmp & swap ( ptr , guess , write ) } while ( actual bit-different-to guess ) ; return write ; This relies on a cmp & swap instruction , which is available for 32- and 64-bit types . Larger types must use a locking scheme .


<s>
void
M68kInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
Register
SrcReg
,
bool
IsKill
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
assert
(
MF
.
getFrameInfo
(
)
.
getObjectSize
(
FrameIndex
)
==
4
&&
"Stack slot too small for store"
)
;
unsigned
Opc
=
getStoreRegOpcode
(
SrcReg
,
RC
,
TRI
,
Subtarget
)
;
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
M68k
::
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
)
,
FrameIndex
)
.
addReg
(
SrcReg
,
getKillRegState
(
IsKill
)
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> void CSKYAsmPrinter :: emitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

Targets should implement this to emit instructions .


<s> void TMS320C64XInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned srcReg , bool isKill , int frameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; const TargetRegisterClass * rc ; if ( ! TargetRegisterInfo :: isPhysicalRegister ( srcReg ) ) { assert ( RC ) ; if ( RC == TMS320C64X :: PredRegsRegisterClass ) rc = TMS320C64X :: ARegsRegisterClass ; else rc = RC ; } else rc = findRegisterSide ( srcReg , MBB . getParent ( ) ) ; bool xdata = ( rc == TMS320C64X :: BRegsRegisterClass ) ; addFormOp ( addDefaultPred ( BuildMI ( MBB , MI , DL , get ( TMS320C64X :: word_store_1 ) ) . addReg ( TMS320C64X :: A15 ) . addFrameIndex ( frameIndex ) . addReg ( srcReg , getKillRegState ( isKill ) ) ) , TMS320C64XII :: unit_d , xdata ) ; } </s>


<s> bool AArch64TargetLowering :: isExtFreeImpl ( const Instruction * Ext ) const { if ( isa < FPExtInst > ( Ext ) ) return false ; if ( Ext -> getType ( ) -> isVectorTy ( ) ) return false ; for ( const Use & U : Ext -> uses ( ) ) { const Instruction * Instr = cast < Instruction > ( U . getUser ( ) ) ; switch ( Instr -> getOpcode ( ) ) { case Instruction :: Shl : if ( ! isa < ConstantInt > ( Instr -> getOperand ( 1 ) ) ) return false ; break ; case Instruction :: GetElementPtr : { gep_type_iterator GTI = gep_type_begin ( Instr ) ; std :: advance ( GTI , U . getOperandNo ( ) ) ; Type * IdxTy = * GTI ; uint64_t ShiftAmt = countTrailingZeros ( getDataLayout ( ) -> getTypeStoreSizeInBits ( IdxTy ) ) - 3 ; if ( ShiftAmt == 0 || ShiftAmt > 4 ) return false ; break ; } case Instruction :: Trunc : if ( Instr -> getType ( ) == Ext -> getOperand ( 0 ) -> getType ( ) ) continue ; default : return false ; } } return true ; } </s>

Return true if the extension represented by I is free .


<s>
static
void
rs6000_output_function_prologue
(
FILE
*
file
,
HOST_WIDE_INT
size
ATTRIBUTE_UNUSED
)
{
rs6000_stack_t
*
info
=
rs6000_stack_info
(
)
;
if
(
TARGET_DEBUG_STACK
)
debug_stack_info
(
info
)
;
if
(
info
->
first_fp_reg_save
<
64
&&
!
FP_SAVE_INLINE
(
info
->
first_fp_reg_save
)
)
fprintf
(
file
,
"\t.extern %s%d%s\n\t.extern %s%d%s\n"
,
SAVE_FP_PREFIX
,
info
->
first_fp_reg_save
32
,
SAVE_FP_SUFFIX
,
RESTORE_FP_PREFIX
,
info
->
first_fp_reg_save
32
,
RESTORE_FP_SUFFIX
)
;
if
(
!
TARGET_POWER
&&
!
TARGET_POWERPC
&&
!
common_mode_defined
)
{
fputs
(
"\t.extern __mulh\n"
,
file
)
;
fputs
(
"\t.extern __mull\n"
,
file
)
;
fputs
(
"\t.extern __divss\n"
,
file
)
;
fputs
(
"\t.extern __divus\n"
,
file
)
;
fputs
(
"\t.extern __quoss\n"
,
file
)
;
fputs
(
"\t.extern __quous\n"
,
file
)
;
common_mode_defined
=
1
;
}
if
(
!
HAVE_prologue
)
{
start_sequence
(
)
;
emit_note
(
NOTE_INSN_DELETED
)
;
rs6000_emit_prologue
(
)
;
emit_note
(
NOTE_INSN_DELETED
)
;
{
rtx
insn
;
unsigned
addr
=
0
;
for
(
insn
=
get_insns
(
)
;
insn
!=
0
;
insn
=
NEXT_INSN
(
insn
)
)
{
INSN_ADDRESSES_NEW
(
insn
,
addr
)
;
addr
+=
4
;
}
}
if
(
TARGET_DEBUG_STACK
)
debug_rtx_list
(
get_insns
(
)
,
100
)
;
final
(
get_insns
(
)
,
file
,
FALSE
)
;
end_sequence
(
)
;
}
rs6000_pic_labelno
++
;
}
</s>


<s>
void
maybe_unlink
(
const
char
*
file
)
{
if
(
debug
)
notice
(
"[Leaving %s]\n"
,
file
)
;
else
unlink_if_ordinary
(
file
)
;
}
</s>

Unlink a temporary file unless requested otherwise .


<s> bool ARMTargetLowering :: isMulAddWithConstProfitable ( SDValue AddNode , SDValue ConstNode ) const { const EVT VT = AddNode . getValueType ( ) ; if ( VT . isVector ( ) || VT . getScalarSizeInBits ( ) > 32 ) return true ; const ConstantSDNode * C0Node = cast < ConstantSDNode > ( AddNode . getOperand ( 1 ) ) ; const ConstantSDNode * C1Node = cast < ConstantSDNode > ( ConstNode ) ; const int64_t C0 = C0Node -> getSExtValue ( ) ; APInt CA = C0Node -> getAPIntValue ( ) * C1Node -> getAPIntValue ( ) ; if ( ! isLegalAddImmediate ( C0 ) || isLegalAddImmediate ( CA . getSExtValue ( ) ) ) return true ; if ( ConstantMaterializationCost ( ( unsigned ) CA . getZExtValue ( ) , Subtarget ) > 1 ) return false ; return true ; } </s>

Return true if it may be profitable to transform ( mul ( add x , c1 ) , c2 ) - > ( add ( mul x , c2 ) , c1 * c2 ) .


<s>
unsigned
SparcRegisterInfo
::
getFrameRegister
(
MachineFunction
&
MF
)
const
{
assert
(
0
&&
"What is the frame register"
)
;
return
SP
::
G1
;
}
</s>


<s> int c4x_rptb_nop_p ( rtx insn ) { rtx start_label ; int i ; start_label = XEXP ( XEXP ( SET_SRC ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) ) , 1 ) , 0 ) ; do { insn = previous_insn ( insn ) ; } while ( GET_CODE ( insn ) == NOTE || GET_CODE ( insn ) == USE || GET_CODE ( insn ) == CLOBBER ) ; if ( GET_CODE ( insn ) == CODE_LABEL ) return 1 ; for ( i = 0 ; i < 4 ; i ++ ) { while ( GET_CODE ( insn ) == NOTE || GET_CODE ( insn ) == CODE_LABEL || GET_CODE ( insn ) == USE || GET_CODE ( insn ) == CLOBBER ) { if ( insn == start_label ) return i == 0 ; insn = previous_insn ( insn ) ; } ; if ( GET_CODE ( insn ) == JUMP_INSN ) return 1 ; insn = previous_insn ( insn ) ; } return 0 ; } </s>

The last instruction in a repeat block can not be a Bcond , DBcound , CALL , CALLCond , TRAPcond , RETIcond , RETScond , IDLE , RPTB or RPTS . None of the last four instructions from the bottom of the block can be a BcondD , BRD , DBcondD , RPTBD , LAJ , LAJcond , LATcond , BcondAF , BcondAT or RETIcondD . This routine scans the four previous insns for a jump insn , and if one is found , returns 1 so that we bung in a nop instruction . This simple minded strategy will add a nop , when it may not be required . Say when there is a JUMP_INSN near the end of the block that does n't get converted into a delayed branch . Note that we can not have a call insn , since we do n't generate repeat loops with calls in them ( although I suppose we could , but there 's no benefit . ) ! ! ! FIXME . The rptb_top insn may be sucked into a SEQUENCE .


<s> static unsigned char ix86_class_max_nregs ( reg_class_t rclass , machine_mode mode ) { if ( MAYBE_INTEGER_CLASS_P ( rclass ) ) { if ( mode == XFmode ) return ( TARGET_64BIT ? 2 : 3 ) ; else if ( mode == XCmode ) return ( TARGET_64BIT ? 4 : 6 ) ; else return ( ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ) ; } else { if ( COMPLEX_MODE_P ( mode ) ) return 2 ; else return 1 ; } } </s>

Implement the TARGET_CLASS_MAX_NREGS hook . On the 80386 , this is the size of MODE in words , except in the FP regs , where a single reg is always enough .


<s> bool mprocAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { return true ; } printSrcMemOperand ( MI , OpNo , O ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


"Can't move the target block as it would "

"introduce a new backwards WLS branch\n"

runOnMachineFunction - Emit the function body .


<s> void SIInstrInfo :: legalizeOperandsVOP3 ( MachineRegisterInfo & MRI , MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; int VOP3Idx [ 3 ] = { AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src0 ) , AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src1 ) , AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src2 ) } ; unsigned SGPRReg = findUsedSGPR ( MI , VOP3Idx ) ; for ( unsigned i = 0 ; i < 3 ; ++ i ) { int Idx = VOP3Idx [ i ] ; if ( Idx == - 1 ) break ; MachineOperand & MO = MI . getOperand ( Idx ) ; if ( ! MO . isReg ( ) ) continue ; if ( ! RI . isSGPRClass ( MRI . getRegClass ( MO . getReg ( ) ) ) ) continue ; if ( SGPRReg == AMDGPU :: NoRegister || SGPRReg == MO . getReg ( ) ) { SGPRReg = MO . getReg ( ) ; continue ; } legalizeOpWithMove ( MI , Idx ) ; } } </s>

Fix operands in MI to satisfy constant bus requirements .

AMDGPU SI 3 AMDGPU::getNamedOperandIdx AMDGPU::OpName AMDGPU::getNamedOperandIdx AMDGPU::OpName AMDGPU::getNamedOperandIdx AMDGPU::OpName 0 3 1 AMDGPU::NoRegister


<s> bool RISCVTargetLowering :: isFMAFasterThanFMulAndFAdd ( const MachineFunction & MF , EVT VT ) const { VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f16 : return Subtarget . hasStdExtZfh ( ) ; case MVT :: f32 : return Subtarget . hasStdExtF ( ) ; case MVT :: f64 : return Subtarget . hasStdExtD ( ) ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> bool RISCVRedundantCopyElimination :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) Changed |= optimizeBlock ( MBB ) ; return Changed ; } </s>


<s> SDValue X86TargetLowering :: getNegatedExpression ( SDValue Op , SelectionDAG & DAG , bool LegalOperations , bool ForCodeSize , unsigned Depth ) const { if ( SDValue Arg = isFNEG ( DAG , Op . getNode ( ) , Depth ) ) return DAG . getBitcast ( Op . getValueType ( ) , Arg ) ; EVT VT = Op . getValueType ( ) ; EVT SVT = VT . getScalarType ( ) ; unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { case ISD :: FMA : case X86ISD :: FMSUB : case X86ISD :: FNMADD : case X86ISD :: FNMSUB : case X86ISD :: FMADD_RND : case X86ISD :: FMSUB_RND : case X86ISD :: FNMADD_RND : case X86ISD :: FNMSUB_RND : { if ( ! Op . hasOneUse ( ) || ! Subtarget . hasAnyFMA ( ) || ! isTypeLegal ( VT ) || ! ( SVT == MVT :: f32 || SVT == MVT :: f64 ) || ! LegalOperations ) break ; SmallVector < SDValue , 4 > NewOps ( Op . getNumOperands ( ) , SDValue ( ) ) ; for ( int i = 0 ; i != 3 ; ++ i ) { char V = isNegatibleForFree ( Op . getOperand ( i ) , DAG , LegalOperations , ForCodeSize , Depth + 1 ) ; if ( V == 2 ) NewOps [ i ] = getNegatedExpression ( Op . getOperand ( i ) , DAG , LegalOperations , ForCodeSize , Depth + 1 ) ; } bool NegA = ! ! NewOps [ 0 ] ; bool NegB = ! ! NewOps [ 1 ] ; bool NegC = ! ! NewOps [ 2 ] ; unsigned NewOpc = negateFMAOpcode ( Opc , NegA != NegB , NegC , true ) ; for ( int i = 0 , e = Op . getNumOperands ( ) ; i != e ; ++ i ) if ( ! NewOps [ i ] ) NewOps [ i ] = Op . getOperand ( i ) ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , VT , NewOps ) ; } } return TargetLowering :: getNegatedExpression ( Op , DAG , LegalOperations , ForCodeSize , Depth ) ; } </s>

Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate that if it is cheaper or neutral to do the negation .


<s> static bool shouldExpandVectorDynExt ( SDNode * N ) { SDValue Idx = N -> getOperand ( N -> getNumOperands ( ) - 1 ) ; if ( UseDivergentRegisterIndexing || isa < ConstantSDNode > ( Idx ) ) return false ; SDValue Vec = N -> getOperand ( 0 ) ; EVT VecVT = Vec . getValueType ( ) ; EVT EltVT = VecVT . getVectorElementType ( ) ; unsigned VecSize = VecVT . getSizeInBits ( ) ; unsigned EltSize = EltVT . getSizeInBits ( ) ; unsigned NumElem = VecVT . getVectorNumElements ( ) ; if ( VecSize <= 64 && EltSize < 32 ) return false ; if ( EltSize < 32 ) return true ; if ( Idx -> isDivergent ( ) ) return true ; unsigned NumInsts = NumElem + ( ( EltSize + 31 ) / 32 ) * NumElem ; return NumInsts <= 16 ; } </s>

Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT ( < n x e > , var-idx ) should be expanded into a set of cmp/select instructions .


getTargetNodeName - This method returns the name of a target specific


<s> bool runOnModule ( Module & M ) override { SetVector < Function * > Functions ; AnalysisGetter AG ; for ( Function & F : M ) { if ( ! F . isIntrinsic ( ) ) Functions . insert ( & F ) ; } CallGraphUpdater CGUpdater ; BumpPtrAllocator Allocator ; AMDGPUInformationCache InfoCache ( M , AG , Allocator , nullptr , * TM ) ; DenseSet < const char * > Allowed ( { & AAAMDAttributes :: ID , & AAUniformWorkGroupSize :: ID , & AACallEdges :: ID } ) ; Attributor A ( Functions , InfoCache , CGUpdater , & Allowed ) ; for ( Function & F : M ) { if ( ! F . isIntrinsic ( ) ) { A . getOrCreateAAFor < AAAMDAttributes > ( IRPosition :: function ( F ) ) ; A . getOrCreateAAFor < AAUniformWorkGroupSize > ( IRPosition :: function ( F ) ) ; } } ChangeStatus Change = A . run ( ) ; return Change == ChangeStatus :: CHANGED ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> static int avr_mul_highpart_cost ( rtx x , int ) { if ( AVR_HAVE_MUL && LSHIFTRT == GET_CODE ( x ) && MULT == GET_CODE ( XEXP ( x , 0 ) ) && CONST_INT_P ( XEXP ( x , 1 ) ) ) { machine_mode mode = GET_MODE ( x ) ; if ( HImode == mode || PSImode == mode || SImode == mode ) { return COSTS_N_INSNS ( 2 ) ; } } return 10000 ; } </s>

Cost for mul highpart . X is a LSHIFTRT , i.e . the outer TRUNCATE is already stripped off .


Hook to validate the current # pragma GCC target and set the state , and update the macros based on what was changed . If ARGS is NULL , then POP_TARGET is used to reset the options .


<s> virtual bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> Register HexagonRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const HexagonFrameLowering * TFI = getFrameLowering ( MF ) ; if ( TFI -> hasFP ( MF ) ) return getFrameRegister ( ) ; return getStackRegister ( ) ; } </s>


<s> static void loongarch_emit_probe_stack_range ( HOST_WIDE_INT first , HOST_WIDE_INT size ) { HOST_WIDE_INT rounded_size ; HOST_WIDE_INT interval ; if ( flag_stack_clash_protection ) interval = STACK_CLASH_PROTECTION_GUARD_SIZE ; else interval = PROBE_INTERVAL ; rtx r12 = LARCH_PROLOGUE_TEMP2 ( Pmode ) ; rtx r14 = LARCH_PROLOGUE_TEMP3 ( Pmode ) ; size = size + first ; gcc_assert ( first <= 16384 ) ; rounded_size = ROUND_DOWN ( size , interval ) ; emit_move_insn ( r14 , GEN_INT ( interval ) ) ; if ( rounded_size != 0 ) { if ( rounded_size <= STACK_CLASH_MAX_UNROLL_PAGES * interval ) { for ( HOST_WIDE_INT i = 0 ; i < rounded_size ; i += interval ) { emit_insn ( gen_rtx_SET ( stack_pointer_rtx , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , r14 ) ) ) ; emit_move_insn ( gen_rtx_MEM ( Pmode , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , const0_rtx ) ) , const0_rtx ) ; emit_insn ( gen_blockage ( ) ) ; } dump_stack_clash_frame_info ( PROBE_INLINE , size != rounded_size ) ; } else { emit_move_insn ( r12 , GEN_INT ( rounded_size ) ) ; emit_insn ( gen_rtx_SET ( r12 , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , r12 ) ) ) ; emit_insn ( gen_probe_stack_range ( Pmode , stack_pointer_rtx , stack_pointer_rtx , r12 , r14 ) ) ; emit_insn ( gen_blockage ( ) ) ; dump_stack_clash_frame_info ( PROBE_LOOP , size != rounded_size ) ; } } else dump_stack_clash_frame_info ( NO_PROBE_SMALL_FRAME , true ) ; if ( size != rounded_size ) { if ( size - rounded_size >= 2048 ) { emit_move_insn ( r14 , GEN_INT ( size - rounded_size ) ) ; emit_insn ( gen_rtx_SET ( stack_pointer_rtx , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , r14 ) ) ) ; } else emit_insn ( gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( rounded_size - size ) ) ) ) ; } if ( first ) { emit_move_insn ( r12 , GEN_INT ( first ) ) ; emit_insn ( gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , r12 ) ) ) ; } emit_insn ( gen_blockage ( ) ) ; } </s>

Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE , inclusive . These are offsets from the current stack pointer .


<s> static bool riscv_valid_lo_sum_p ( enum riscv_symbol_type sym_type , machine_mode mode , rtx x ) { int align , size ; if ( riscv_symbol_insns ( sym_type ) == 0 ) return false ; if ( ! riscv_split_symbol_type ( sym_type ) ) return false ; if ( mode == BLKmode ) { rtx offset ; split_const ( x , & x , & offset ) ; if ( ! SYMBOL_REF_P ( x ) ) return false ; align = ( SYMBOL_REF_DECL ( x ) ? DECL_ALIGN ( SYMBOL_REF_DECL ( x ) ) : 1 ) ; size = ( SYMBOL_REF_DECL ( x ) && DECL_SIZE ( SYMBOL_REF_DECL ( x ) ) ? tree_to_uhwi ( DECL_SIZE ( SYMBOL_REF_DECL ( x ) ) ) : 2 * BITS_PER_WORD ) ; } else { align = GET_MODE_ALIGNMENT ( mode ) ; size = GET_MODE_BITSIZE ( mode ) ; } if ( size > BITS_PER_WORD && ( ! TARGET_STRICT_ALIGN || size > align ) ) return false ; return true ; } </s>

Return true if a LO_SUM can address a value of mode MODE when the LO_SUM symbol has type SYM_TYPE .


<s> static void aarch64_pushwb_single_reg ( machine_mode mode , unsigned regno , HOST_WIDE_INT adjustment ) { rtx base_rtx = stack_pointer_rtx ; rtx insn , reg , mem ; reg = gen_rtx_REG ( mode , regno ) ; mem = gen_rtx_PRE_MODIFY ( Pmode , base_rtx , plus_constant ( Pmode , base_rtx , - adjustment ) ) ; mem = gen_rtx_MEM ( mode , mem ) ; insn = emit_move_insn ( mem , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Push the register number REGNO of mode MODE to the stack with write-back adjusting the stack by ADJUSTMENT .


<s> bool PPCDarwinAsmPrinter :: doFinalization ( Module & M ) { bool isPPC64 = getDataLayout ( ) . getPointerSizeInBits ( ) == 64 ; const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; if ( MMI ) { MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; if ( MAI -> doesSupportExceptionHandling ( ) ) { for ( const Function * Personality : MMI -> getPersonalities ( ) ) { if ( Personality ) { MCSymbol * NLPSym = getSymbolWithGlobalValueBase ( Personality , "$non_lazy_ptr" ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMIMacho . getGVStubEntry ( NLPSym ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( Personality ) , true ) ; } } } MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer -> EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer -> EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer -> EmitIntValue ( 0 , isPPC64 ? 8 : 4 ) ; else OutStreamer -> EmitValue ( MCSymbolRefExpr :: create ( MCSym . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 ) ; } Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } } OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s>
SDValue
XCoreTargetLowering
::
LowerCall
(
TargetLowering
::
CallLoweringInfo
&
CLI
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SelectionDAG
&
DAG
=
CLI
.
DAG
;
SDLoc
&
dl
=
CLI
.
DL
;
SmallVector
<
ISD
::
OutputArg
,
32
>
&
Outs
=
CLI
.
Outs
;
SmallVector
<
SDValue
,
32
>
&
OutVals
=
CLI
.
OutVals
;
SmallVector
<
ISD
::
InputArg
,
32
>
&
Ins
=
CLI
.
Ins
;
SDValue
Chain
=
CLI
.
Chain
;
SDValue
Callee
=
CLI
.
Callee
;
bool
&
isTailCall
=
CLI
.
IsTailCall
;
CallingConv
::
ID
CallConv
=
CLI
.
CallConv
;
bool
isVarArg
=
CLI
.
IsVarArg
;
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
OutVals
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .


"inserting int3 after trailing call instruction:\n"

"inserting int3 in trailing empty MBB:\n"


<s> static bool xtensa_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { return xtensa_hard_regno_mode_ok_p [ mode ] [ regno ] ; } </s>


"Unexpected type for the widened instruction"

Called for instructions with the Custom LegalizationAction .


<s> static reg_class_t pdp11_secondary_reload ( bool in_p ATTRIBUTE_UNUSED , rtx x , reg_class_t reload_class , machine_mode reload_mode ATTRIBUTE_UNUSED , secondary_reload_info * sri ATTRIBUTE_UNUSED ) { if ( reload_class != NO_LOAD_FPU_REGS || GET_CODE ( x ) != REG || REGNO_REG_CLASS ( REGNO ( x ) ) == LOAD_FPU_REGS ) return NO_REGS ; return LOAD_FPU_REGS ; } </s>

TARGET_SECONDARY_RELOAD . FPU registers AC4 and AC5 ( class NO_LOAD_FPU_REGS ) require an intermediate register ( AC0-AC3 : LOAD_FPU_REGS ) . Everything else can be loade/stored directly .


<s> bool GCNTTIImpl :: getTgtMemIntrinsic ( IntrinsicInst * Inst , MemIntrinsicInfo & Info ) const { switch ( Inst -> getIntrinsicID ( ) ) { case Intrinsic :: amdgcn_atomic_inc : case Intrinsic :: amdgcn_atomic_dec : case Intrinsic :: amdgcn_ds_ordered_add : case Intrinsic :: amdgcn_ds_ordered_swap : case Intrinsic :: amdgcn_ds_fadd : case Intrinsic :: amdgcn_ds_fmin : case Intrinsic :: amdgcn_ds_fmax : { auto * Ordering = dyn_cast < ConstantInt > ( Inst -> getArgOperand ( 2 ) ) ; auto * Volatile = dyn_cast < ConstantInt > ( Inst -> getArgOperand ( 4 ) ) ; if ( ! Ordering || ! Volatile ) return false ; unsigned OrderingVal = Ordering -> getZExtValue ( ) ; if ( OrderingVal > static_cast < unsigned > ( AtomicOrdering :: SequentiallyConsistent ) ) return false ; Info . PtrVal = Inst -> getArgOperand ( 0 ) ; Info . Ordering = static_cast < AtomicOrdering > ( OrderingVal ) ; Info . ReadMem = true ; Info . WriteMem = true ; Info . IsVolatile = ! Volatile -> isZero ( ) ; return true ; } default : return false ; } } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> virtual int getOperandLatency ( const InstrItineraryData * ItinData , SDNode * DefNode , unsigned DefIdx , SDNode * UseNode , unsigned UseIdx ) const { return PPCGenInstrInfo :: getOperandLatency ( ItinData , DefNode , DefIdx , UseNode , UseIdx ) ; } </s>

Compute and return the use operand latency of a given pair of def and use .


<s> bool PPCTargetMachine :: addPreEmitPass ( PassManagerBase & PM ) { PM . add ( createPPCBranchSelectionPass ( ) ) ; return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static bool tilepro_pass_by_reference ( cumulative_args_t cum ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , const_tree type , bool named ATTRIBUTE_UNUSED ) { return ( type && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) ; } </s>

Implement TARGET_PASS_BY_REFERENCE . Variable sized types are passed by reference .


<s>
StringRef
getPassName
(
)
const
override
{
return
"WebAssembly Optimize Returned"
;
}
</s>

getPassName - Return a nice clean name for a pass .

WebAssembly
"WebAssembly Optimize Returned"


<s> bool Thumb2SizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { if ( PredicateFtor && ! PredicateFtor ( MF . getFunction ( ) ) ) return false ; STI = & static_cast < const ARMSubtarget & > ( MF . getSubtarget ( ) ) ; if ( STI -> isThumb1Only ( ) || STI -> prefers32BitThumb ( ) ) return false ; TII = static_cast < const Thumb2InstrInfo * > ( STI -> getInstrInfo ( ) ) ; OptimizeSize = MF . getFunction ( ) . optForSize ( ) ; MinimizeSize = MF . getFunction ( ) . optForMinSize ( ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; ReversePostOrderTraversal < MachineFunction * > RPOT ( & MF ) ; bool Modified = false ; for ( ReversePostOrderTraversal < MachineFunction * > :: rpo_iterator I = RPOT . begin ( ) , E = RPOT . end ( ) ; I != E ; ++ I ) Modified |= ReduceMBB ( * * I ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s>
MachineInstr
*
RISCVInstrInfo
::
convertToThreeAddress
(
MachineFunction
::
iterator
&
MBB
,
MachineInstr
&
MI
,
LiveVariables
*
LV
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
CASE_WIDEOP_OPCODE_LMULS
(
FWADD_WV
)
:
case
CASE_WIDEOP_OPCODE_LMULS
(
FWSUB_WV
)
:
case
CASE_WIDEOP_OPCODE_LMULS
(
WADD_WV
)
:
case
CASE_WIDEOP_OPCODE_LMULS
(
WADDU_WV
)
:
case
CASE_WIDEOP_OPCODE_LMULS
(
WSUB_WV
)
:
case
CASE_WIDEOP_OPCODE_LMULS
(
WSUBU_WV
)
:
{
unsigned
NewOpc
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unexpected opcode"
)
;
CASE_WIDEOP_CHANGE_OPCODE_LMULS
(
FWADD_WV
)
CASE_WIDEOP_CHANGE_OPCODE_LMULS
(
FWSUB_WV
)
CASE_WIDEOP_CHANGE_OPCODE_LMULS
(
WADD_WV
)
CASE_WIDEOP_CHANGE_OPCODE_LMULS
(
WADDU_WV
)
CASE_WIDEOP_CHANGE_OPCODE_LMULS
(
WSUB_WV
)
CASE_WIDEOP_CHANGE_OPCODE_LMULS
(
WSUBU_WV
)
}
MachineInstrBuilder
MIB
=
BuildMI
(
*
MBB
,
MI
,
MI
.
getDebugLoc
(
)
,
get
(
NewOpc
)
)
.
add
(
MI
.
getOperand
(
0
)
)
.
add
(
MI
.
getOperand
(
1
)
)
.
add
(
MI
.
getOperand
(
2
)
)
.
add
(
MI
.
getOperand
(
3
)
)
.
add
(
MI
.
getOperand
(
4
)
)
;
MIB
.
copyImplicitOps
(
MI
)
;
if
(
LV
)
{
unsigned
NumOps
=
MI
.
getNumOperands
(
)
;
for
(
unsigned
I
=
1
;
I
<
NumOps
;
++
I
)
{
MachineOperand
&
Op
=
MI
.
getOperand
(
I
)
;
if
(
Op
.
isReg
(
)
&&
Op
.
isKill
(
)
)
LV
->
replaceKillInstruction
(
Op
.
getReg
(
)
,
MI
,
*
MIB
)
;
}
}
return
MIB
;
}
}
return
nullptr
;
}
</s>

convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag .


<s>
unsigned
getReg
(
)
const
{
assert
(
Kind
==
k_Register
&&
"Invalid access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s> unsigned OR1KRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? OR1K :: R2 : OR1K :: R1 ; } </s>


<s> bool ARCompactFrameLowering :: hasFP ( const MachineFunction & MF ) const { return ( DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


"mt_final_prescan_insn, invalid insn #1"

The following determines the number of nops that need to be inserted between the previous instructions and current instruction to avoid pipeline hazards on the mt processor . Remember that the function is not called for asm insns .


";; [Local] Removing membar %d since order"

";; [Local] Removing membar %d since the target"

" of %d is used before the I/O operation\n"

Go through block BB looking for membars to remove . There are two cases where intra-block analysis is enough : - a membar is redundant if it occurs between two consecutive I/O operations and if those operations are guaranteed to complete in order . - a membar for a __builtin_read is redundant if the result is used before the next I/O operation is issued . If the last membar in the block could not be removed , and there are guaranteed to be no I/O operations between that membar and the end of the block , store the membar in * LAST_MEMBAR , otherwise store null . Describe the block 's first I/O operation in * NEXT_IO . Describe an unknown operation if the block does n't do any I/O .


<s> static HOST_WIDE_INT pa_starting_frame_offset ( void ) { return 8 ; } </s>

Implement TARGET_STARTING_FRAME_OFFSET . On the 32-bit ports , we reserve one slot for the previous frame pointer and one fill slot . The fill slot is for compatibility with HP compiled programs . On the 64-bit ports , we reserve one slot for the previous frame pointer .


<s>
void
P2DAGToDAGISel
::
Select
(
SDNode
*
N
)
{
LLVM_DEBUG
(
errs
(
)
<<
"<-------->\n"
)
;
LLVM_DEBUG
(
errs
(
)
<<
"Selecting: "
;
N
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
N
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
errs
(
)
<<
"== "
;
N
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
N
->
setNodeId
(
1
)
;
return
;
}
unsigned
Opcode
=
N
->
getOpcode
(
)
;
auto
DL
=
CurDAG
->
getDataLayout
(
)
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
FrameIndex
:
{
LLVM_DEBUG
(
errs
(
)
<<
"frame index node is being selected\n"
)
;
FrameIndexSDNode
*
FIN
=
dyn_cast
<
FrameIndexSDNode
>
(
N
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FIN
->
getIndex
(
)
,
getTargetLowering
(
)
->
getPointerTy
(
DL
)
)
;
CurDAG
->
SelectNodeTo
(
N
,
P2
::
FRMIDX
,
getTargetLowering
(
)
->
getPointerTy
(
DL
)
,
TFI
)
;
return
;
}
case
ISD
::
SMUL_LOHI
:
case
ISD
::
UMUL_LOHI
:
{
selectMultiplication
(
N
)
;
return
;
}
}
SelectCode
(
N
)
;
LLVM_DEBUG
(
errs
(
)
<<
"Done selecting, chose "
;
N
->
dump
(
)
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> unsigned ARMBaseInstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { SmallVector < const MachineMemOperand * , 1 > Accesses ; if ( MI . mayLoad ( ) && hasLoadFromStackSlot ( MI , Accesses ) && Accesses . size ( ) == 1 ) { FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) -> getFrameIndex ( ) ; return true ; } return false ; } </s>

isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s> bool isReg ( ) const override { return Kind == Register ; } </s>


This function tries to implement an atomic exchange operation using a compare_and_swap loop . VAL is written to * MEM . The previous contents of * MEM are returned , using TARGET if possible . No memory model is required since a compare_and_swap loop is seq-cst .


<s>
static
void
arc_file_start
(
void
)
{
default_file_start
(
)
;
fprintf
(
asm_out_file
,
"\t.cpu %s\n"
,
arc_cpu_string
)
;
}
</s>

Set the cpu type and print out other fancy things , at the top of the file .


<s> bool SNESAsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : return false ; case SNES :: fixup_7_pcrel : case SNES :: fixup_13_pcrel : case SNES :: fixup_call : return true ; } } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> BitVector AVRRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AVR :: R0 ) ; Reserved . set ( AVR :: R1 ) ; Reserved . set ( AVR :: R1R0 ) ; Reserved . set ( AVR :: SPL ) ; Reserved . set ( AVR :: SPH ) ; Reserved . set ( AVR :: SP ) ; Reserved . set ( AVR :: R28 ) ; Reserved . set ( AVR :: R29 ) ; Reserved . set ( AVR :: R29R28 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static void union_defs ( swap_web_entry * insn_entry , rtx insn , df_ref use ) { struct df_link * link = DF_REF_CHAIN ( use ) ; if ( ! link ) insn_entry [ INSN_UID ( insn ) ] . is_live_in = 1 ; while ( link ) { if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) insn_entry [ INSN_UID ( insn ) ] . is_live_in = 1 ; if ( DF_REF_INSN_INFO ( link -> ref ) ) { rtx def_insn = DF_REF_INSN ( link -> ref ) ; ( void ) unionfind_union ( insn_entry + INSN_UID ( insn ) , insn_entry + INSN_UID ( def_insn ) ) ; } link = link -> next ; } } </s>

Union INSN with all insns containing definitions that reach USE . Detect whether USE is live-in to the current function .


<s> void init_cumulative_args ( CUMULATIVE_ARGS * cum , tree fntype , rtx libname , tree fndecl ATTRIBUTE_UNUSED ) { cum -> nregs = 18 ; cum -> regno = FIRST_CUM_REG ; if ( ! libname && fntype ) { int stdarg = ( TYPE_ARG_TYPES ( fntype ) != 0 && ( TREE_VALUE ( tree_last ( TYPE_ARG_TYPES ( fntype ) ) ) != void_type_node ) ) ; if ( stdarg ) cum -> nregs = 0 ; } } </s>

Handle the INIT_CUMULATIVE_ARGS macro . Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is 0 .


"Error: You are using the detectroundchange "

"option to detect rounding changes that will "

"cause LEON errata. The only way to fix this "

"is to remove the call to fesetround from "


<s> static bool rs6000_member_type_forces_blk ( const_tree field , machine_mode mode ) { return ( ( TARGET_SPE && TREE_CODE ( TREE_TYPE ( field ) ) == VECTOR_TYPE ) || ( TARGET_E500_DOUBLE && mode == DFmode ) ) ; } </s>

Return true if a structure , union or array containing FIELD should be accessed using ` BLKMODE ' . For the SPE , simd types are V2SI , and gcc can be tempted to put the entire thing in a DI and use subregs to access the internals . store_bit_field ( ) will force ( subreg : DI ( reg : V2SI x ) ) 's to the back-end . Because a single GPR can hold a V2SI , but not a DI , the best thing to do is set structs to BLKmode and avoid Severe Tire Damage . On e500 v2 , DF and DI modes suffer from the same anomaly . DF can fit into 1 , whereas DI still needs two .


<s> static int const_int_cost ( rtx constant ) { switch ( const_method ( constant ) ) { case MOVQ : return 0 ; case MVZ : case MVS : case NOTB : case NOTW : case NEGW : case SWAP : return 1 ; case MOVL : return 2 ; default : gcc_unreachable ( ) ; } } </s>

Return the cost of moving constant I into a data register .


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> static reg_class_t sparc_preferred_reload_class ( rtx x , reg_class_t rclass ) { machine_mode mode = GET_MODE ( x ) ; if ( CONSTANT_P ( x ) ) { if ( FP_REG_CLASS_P ( rclass ) || rclass == GENERAL_OR_FP_REGS || rclass == GENERAL_OR_EXTRA_FP_REGS || ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && ! TARGET_FPU ) || ( mode == TFmode && ! const_zero_operand ( x , mode ) ) ) return NO_REGS ; if ( GET_MODE_CLASS ( mode ) == MODE_INT ) return GENERAL_REGS ; if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) { if ( ! FP_REG_CLASS_P ( rclass ) || ! ( const_zero_operand ( x , mode ) || const_all_ones_operand ( x , mode ) ) ) return NO_REGS ; } } if ( TARGET_VIS3 && ! TARGET_ARCH64 && ( rclass == EXTRA_FP_REGS || rclass == GENERAL_OR_EXTRA_FP_REGS ) ) { int regno = true_regnum ( x ) ; if ( SPARC_INT_REG_P ( regno ) ) return ( rclass == EXTRA_FP_REGS ? FP_REGS : GENERAL_OR_FP_REGS ) ; } return rclass ; } </s>

Implement TARGET_PREFERRED_RELOAD_CLASS : - We ca n't load constants into FP registers . - We ca n't load FP constants into integer registers when soft-float , because there is no soft-float pattern with a r/F constraint . - We ca n't load FP constants into integer registers for TFmode unless it is 0.0L , because there is no movtf pattern with a r/F constraint . - Try and reload integer constants ( symbolic or otherwise ) back into registers directly , rather than having them dumped to memory .


<s> bool isToken ( ) const override { return Kind == k_Token ; } </s>


<s> bool TPCSubregInitElimination :: runOnMachineFunction ( MachineFunction & Func ) { if ( ! EnableTPCSubregInitElimination ) return false ; MF = & Func ; MRI = & MF -> getRegInfo ( ) ; TII = MF -> getSubtarget ( ) . getInstrInfo ( ) ; TRI = MF -> getSubtarget ( ) . getRegisterInfo ( ) ; SubregInstrs . clear ( ) ; bool Changed = false ; for ( auto & BB : Func ) { for ( auto & I : BB ) { if ( unsigned SubregCount = TPCII :: getLanesCount ( I . getDesc ( ) ) ) { if ( removeInitialization ( & I , SubregCount ) ) Changed = true ; } } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> int arm_no_early_alu_shift_dep ( rtx producer , rtx consumer ) { rtx value , op ; rtx early_op ; if ( ! arm_get_set_operands ( producer , consumer , & value , & op ) ) return 0 ; if ( ( early_op = arm_find_shift_sub_rtx ( op ) ) ) return ! reg_overlap_mentioned_p ( value , early_op ) ; return 0 ; } </s>

Return nonzero if the CONSUMER instruction ( an ALU op ) does not have an early register shift value or amount dependency on the result of PRODUCER .


<s> void X86PassConfig :: addPreEmitPass ( ) { addPass ( createCookieSetterPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createExecutionDependencyFixPass ( & X86 :: VR128RegClass ) ) ; if ( UseVZeroUpper ) addPass ( createX86IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86PadShortFunctions ( ) ) ; addPass ( createX86FixupLEAs ( ) ) ; } addPass ( createX86FixupVCalls ( ) ) ; addPass ( createMOVToLEAPass ( ) ) ; addPass ( createEquivSubstPass ( ) ) ; if ( TM -> Options . NOPInsertion ) { addPass ( createNOPInsertionPass ( Is64Bit ) ) ; } } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool AlphaAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s>
static
void
nvptx_record_offload_symbol
(
tree
decl
)
{
switch
(
TREE_CODE
(
decl
)
)
{
case
VAR_DECL
:
fprintf
(
asm_out_file
,
"//:VAR_MAP \"%s\"\n"
,
IDENTIFIER_POINTER
(
DECL_ASSEMBLER_NAME
(
decl
)
)
)
;
break
;
case
FUNCTION_DECL
:
{
tree
attr
=
oacc_get_fn_attrib
(
decl
)
;
tree
dims
=
attr
TREE_VALUE
(
attr
)
:
NULL_TREE
;
fprintf
(
asm_out_file
,
"//:FUNC_MAP \"%s\""
,
IDENTIFIER_POINTER
(
DECL_ASSEMBLER_NAME
(
decl
)
)
)
;
for
(
;
dims
;
dims
=
TREE_CHAIN
(
dims
)
)
{
int
size
=
TREE_INT_CST_LOW
(
TREE_VALUE
(
dims
)
)
;
gcc_assert
(
!
TREE_PURPOSE
(
dims
)
)
;
fprintf
(
asm_out_file
,
", %#x"
,
size
)
;
}
fprintf
(
asm_out_file
,
"\n"
)
;
}
break
;
default
:
gcc_unreachable
(
)
;
}
}
</s>

Record a symbol for mkoffload to enter into the mapping table .


<s> bool HexagonDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintCode ) { case 'o' : case 'v' : default : return true ; case 'm' : if ( ! SelectAddr ( Op . getNode ( ) , Op , Op0 , Op1 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> static char * detect_caches_linux ( void ) { unsigned l1_sizekb , l1_line , l1_assoc , l2_sizekb ; const char * platform ; platform = elf_platform ( ) ; if ( platform != NULL ) { l1_line = 128 ; if ( platform [ 5 ] == '6' ) l1_sizekb = 64 ; else l1_sizekb = 32 ; } else { l1_line = elf_dcachebsize ( ) ; l1_sizekb = 32 ; } l1_assoc = 0 ; l2_sizekb = 512 ; return describe_cache ( l1_sizekb , l1_line , l1_assoc , l2_sizekb ) ; } </s>

Returns the description of caches on Linux .


<s> MCSymbol * WebAssemblyMCInstLower :: GetExternalSymbolSymbol ( const MachineOperand & MO ) const { const char * Name = MO . getSymbolName ( ) ; MCSymbolWasm * WasmSym = cast < MCSymbolWasm > ( Printer . GetExternalSymbolSymbol ( Name ) ) ; const WebAssemblySubtarget & Subtarget = Printer . getSubtarget ( ) ; if ( strcmp ( Name , "__stack_pointer" ) == 0 ) { WasmSym -> setType ( wasm :: WASM_SYMBOL_TYPE_GLOBAL ) ; WasmSym -> setGlobalType ( wasm :: WasmGlobalType { uint8_t ( Subtarget . hasAddr64 ( ) ? wasm :: WASM_TYPE_I64 : wasm :: WASM_TYPE_I32 ) , true } ) ; return WasmSym ; } SmallVector < wasm :: ValType , 4 > Returns ; SmallVector < wasm :: ValType , 4 > Params ; if ( strcmp ( Name , "__cpp_exception" ) == 0 ) { WasmSym -> setType ( wasm :: WASM_SYMBOL_TYPE_EVENT ) ; WasmSym -> setEventType ( { wasm :: WASM_EVENT_ATTRIBUTE_EXCEPTION , 0 } ) ; WasmSym -> setWeak ( true ) ; WasmSym -> setExternal ( true ) ; Params . push_back ( Subtarget . hasAddr64 ( ) ? wasm :: ValType :: I64 : wasm :: ValType :: I32 ) ; } else { WasmSym -> setType ( wasm :: WASM_SYMBOL_TYPE_FUNCTION ) ; GetLibcallSignature ( Subtarget , Name , Returns , Params ) ; } auto Signature = make_unique < wasm :: WasmSignature > ( std :: move ( Returns ) , std :: move ( Params ) ) ; WasmSym -> setSignature ( Signature . get ( ) ) ; Printer . addSignature ( std :: move ( Signature ) ) ; return WasmSym ; } </s>

Return the MCSymbol for the specified ExternalSymbol .


<s> const char * TeakTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return NULL ; case TeakISD :: RET_FLAG : return "RetFlag" ; case TeakISD :: LOAD_SYM : return "LOAD_SYM" ; case TeakISD :: MOVEi32 : return "MOVEi32" ; case TeakISD :: CALL : return "CALL" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


Return appropriate code to load up a 1 , 2 , or 4 integer/floating point value .


<s> static void alpha_output_mi_thunk_osf ( FILE * file , tree thunk_fndecl ATTRIBUTE_UNUSED , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { const char * fnname = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( thunk_fndecl ) ) ; HOST_WIDE_INT hi , lo ; rtx this_rtx , funexp ; rtx_insn * insn ; emit_insn ( gen_prologue_ldgp ( ) ) ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , 17 ) ; else this_rtx = gen_rtx_REG ( Pmode , 16 ) ; lo = ( ( delta & 0xffff ) ^ 0x8000 ) - 0x8000 ; hi = ( ( ( delta - lo ) & 0xffffffff ) ^ 0x80000000 ) - 0x80000000 ; if ( hi + lo == delta ) { if ( hi ) emit_insn ( gen_adddi3 ( this_rtx , this_rtx , GEN_INT ( hi ) ) ) ; if ( lo ) emit_insn ( gen_adddi3 ( this_rtx , this_rtx , GEN_INT ( lo ) ) ) ; } else { rtx tmp = alpha_emit_set_long_const ( gen_rtx_REG ( Pmode , 0 ) , delta ) ; emit_insn ( gen_adddi3 ( this_rtx , this_rtx , tmp ) ) ; } if ( vcall_offset ) { rtx tmp , tmp2 ; tmp = gen_rtx_REG ( Pmode , 0 ) ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , this_rtx ) ) ; lo = ( ( vcall_offset & 0xffff ) ^ 0x8000 ) - 0x8000 ; hi = ( ( ( vcall_offset - lo ) & 0xffffffff ) ^ 0x80000000 ) - 0x80000000 ; if ( hi + lo == vcall_offset ) { if ( hi ) emit_insn ( gen_adddi3 ( tmp , tmp , GEN_INT ( hi ) ) ) ; } else { tmp2 = alpha_emit_set_long_const ( gen_rtx_REG ( Pmode , 1 ) , vcall_offset ) ; emit_insn ( gen_adddi3 ( tmp , tmp , tmp2 ) ) ; lo = 0 ; } if ( lo ) tmp2 = gen_rtx_PLUS ( Pmode , tmp , GEN_INT ( lo ) ) ; else tmp2 = tmp ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , tmp2 ) ) ; emit_insn ( gen_adddi3 ( this_rtx , this_rtx , tmp ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = 1 ; } funexp = XEXP ( DECL_RTL ( function ) , 0 ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx ) ) ; SIBLING_CALL_P ( insn ) = 1 ; insn = get_insns ( ) ; shorten_branches ( insn ) ; assemble_start_function ( thunk_fndecl , fnname ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; assemble_end_function ( thunk_fndecl , fnname ) ; } </s>

Emit a tail call to FUNCTION after adjusting THIS by DELTA . In order to avoid the hordes of differences between generated code with and without TARGET_EXPLICIT_RELOCS , and to avoid duplicating lots of code loading up large constants , generate rtl and emit it instead of going straight to text . Not sure why this idea has n't been explored before ...


<s> static MCAsmInfo * createMCAsmInfo ( const MCRegisterInfo & , const Triple & TT , const MCTargetOptions & Options ) { return new WebAssemblyMCAsmInfo ( TT , Options ) ; } </s>

createMCAsmInfo - Create a MCAsmInfo implementation for the specified target triple .


<s> void arc_initialize_trampoline ( rtx tramp ATTRIBUTE_UNUSED , rtx fnaddr ATTRIBUTE_UNUSED , rtx cxt ATTRIBUTE_UNUSED ) { } </s>

With potentially multiple shared objects loaded , and multiple stacks present for multiple thereds where trampolines might reside , a simple range check will likely not suffice for the profiler to tell if a callee is a trampoline . We a speedier check by making the trampoline start at an address that is not 4-byte aligned . A trampoline looks like this : nop_s 0x78e0entry : ld_s r12 , [ pcl,12 ] 0xd403 ld r11 , [ pcl,12 ] 0x170c 700b j_s [ r12 ] 0x7c00 nop_s 0x78e0 The fastest trampoline to execute for trampolines within +-8KB of CTX would be : add2 r11 , pcl , s12 j [ limm ] 0x20200f80 limm and that would also be faster to write to the stack by computing the offset from CTX to TRAMP at compile time . However , it would really be better to get rid of the high cost of cache invalidation when generating trampolines , which requires that the code part of trampolines stays constant , and additionally either - making sure that no executable code but trampolines is on the stack , no icache entries linger for the area of the stack from when before the stack was allocated , and allocating trampolines in trampoline-only cache lines or - allocate trampolines fram a special pool of pre-allocated trampolines .


<s> pa_asm_output_aligned_local ( FILE , NAME , SIZE , ALIGN ) { rtx addr = ADDR ; \ switch ( GET_CODE ( addr ) ) \ { \ case REG : \ fprintf ( FILE , "0(%s)" , reg_names [ REGNO ( addr ) ] ) ; \ break ; \ case PLUS : \ gcc_assert ( GET_CODE ( XEXP ( addr , 1 ) ) == CONST_INT ) ; \ fprintf ( FILE , "%d(%s)" , ( int ) INTVAL ( XEXP ( addr , 1 ) ) , \ reg_names [ REGNO ( XEXP ( addr , 0 ) ) ] ) ; \ break ; \ case LO_SUM : \ if ( ! symbolic_operand ( XEXP ( addr , 1 ) , VOIDmode ) ) \ fputs ( "R'" , FILE ) ; \ else if ( flag_pic == 0 ) \ fputs ( "RR'" , FILE ) ; \ else \ fputs ( "RT'" , FILE ) ; \ pa_output_global_address ( FILE , XEXP ( addr , 1 ) , 0 ) ; \ fputs ( "(" , FILE ) ; \ output_operand ( XEXP ( addr , 0 ) , 0 ) ; \ fputs ( ")" , FILE ) ; \ break ; \ case CONST_INT : \ fprintf ( FILE , HOST_WIDE_INT_PRINT_DEC "(%%r0)" , INTVAL ( addr ) ) ; \ break ; \ default : \ output_addr_const ( FILE , addr ) ; \ } } </s>

We ca n't use .comm for local common storage as the SOM linker effectively treats the symbol as universal and uses the same storage for local symbols with the same name in different object files . The .block directive reserves an uninitialized block of storage . However , it 's not common storage . Fortunately , GCC never requests common storage with the same name in any given translation unit .


<s> void PPCPassConfig :: addIRPasses ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCBoolRetToIntPass ( ) ) ; addPass ( createAtomicExpandPass ( ) ) ; addPass ( createPPCLowerMASSVEntriesPass ( ) ) ; bool UsePrefetching = TM -> getTargetTriple ( ) . getVendor ( ) == Triple :: BGQ && getOptLevel ( ) != CodeGenOpt :: None ; if ( EnablePrefetch . getNumOccurrences ( ) > 0 ) UsePrefetching = EnablePrefetch ; if ( UsePrefetching ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Default && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s>
static
void
determineFrameLayout
(
MachineFunction
&
MF
)
{
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
MBlazeFunctionInfo
*
MBlazeFI
=
MF
.
getInfo
<
MBlazeFunctionInfo
>
(
)
;
MBlazeFI
->
adjustLoadArgsFI
(
MFI
)
;
MBlazeFI
->
adjustStoreVarArgsFI
(
MFI
)
;
unsigned
FrameSize
=
MFI
->
getStackSize
(
)
;
DEBUG
(
dbgs
(
)
<<
"Original Frame Size: "
<<
FrameSize
<<
"\n"
)
;
unsigned
TargetAlign
=
MF
.
getTarget
(
)
.
getFrameLowering
(
)
->
getStackAlignment
(
)
;
unsigned
AlignMask
=
TargetAlign
1
;
FrameSize
=
(
FrameSize
+
AlignMask
)
&
~
AlignMask
;
MFI
->
setStackSize
(
FrameSize
)
;
DEBUG
(
dbgs
(
)
<<
"Aligned Frame Size: "
<<
FrameSize
<<
"\n"
)
;
}
</s>

Determine the frame layout but do not update the machine function .

MBlaze
MBlaze
MBlaze
MBlaze
MBlaze
MBlaze
"Original Frame Size: "
"\n"
1
"Aligned Frame Size: "
"\n"


<s>
void
xstormy16_output_addr_vec
(
FILE
*
file
,
rtx
label
ATTRIBUTE_UNUSED
,
rtx
table
)
{
int
vlen
,
idx
;
switch_to_section
(
current_function_section
(
)
)
;
vlen
=
XVECLEN
(
table
,
0
)
;
for
(
idx
=
0
;
idx
<
vlen
;
idx
++
)
{
fputs
(
"\tjmpf "
,
file
)
;
output_asm_label
(
XEXP
(
XVECEXP
(
table
,
0
,
idx
)
,
0
)
)
;
fputc
(
'\n'
,
file
)
;
}
}
</s>

Output an ADDR_VEC . It is output as a sequence of 'jmpf ' instructions , without label or alignment or any other special constructs . We know that the previous instruction will be the ` tablejump_pcrel ' output above . TODO : it might be nice to output 'br ' instructions if they could all reach .


<s> void rl78_setup_peep_movhi ( rtx * operands ) { int i ; for ( i = 0 ; i < 2 ; i ++ ) { switch ( GET_CODE ( operands [ i ] ) ) { case REG : operands [ i + 4 ] = gen_rtx_REG ( HImode , REGNO ( operands [ i ] ) ) ; break ; case CONST_INT : operands [ i + 4 ] = GEN_INT ( ( INTVAL ( operands [ i ] ) & 0xff ) + ( ( char ) INTVAL ( operands [ i + 2 ] ) ) * 256 ) ; break ; case MEM : operands [ i + 4 ] = adjust_address ( operands [ i ] , HImode , 0 ) ; break ; default : break ; } } } </s>

Likewise , when a peephole is activated , this function helps compute the new operands .


<s> bool HexagonOptimizeSZextends :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; unsigned Idx = 1 ; for ( auto & Arg : F . args ( ) ) { if ( F . getAttributes ( ) . hasAttribute ( Idx , Attribute :: SExt ) ) { if ( ! isa < PointerType > ( Arg . getType ( ) ) ) { for ( auto UI = Arg . use_begin ( ) ; UI != Arg . use_end ( ) ; ) { if ( isa < SExtInst > ( * UI ) ) { Instruction * Use = cast < Instruction > ( * UI ) ; SExtInst * SI = new SExtInst ( & Arg , Use -> getType ( ) ) ; assert ( EVT :: getEVT ( SI -> getType ( ) ) == ( EVT :: getEVT ( Use -> getType ( ) ) ) ) ; ++ UI ; Use -> replaceAllUsesWith ( SI ) ; Instruction * First = & F . getEntryBlock ( ) . front ( ) ; SI -> insertBefore ( First ) ; Use -> eraseFromParent ( ) ; } else { ++ UI ; } } } } ++ Idx ; } for ( auto & B : F ) { for ( auto & I : B ) { BinaryOperator * Ashr = dyn_cast < BinaryOperator > ( & I ) ; if ( ! ( Ashr && Ashr -> getOpcode ( ) == Instruction :: AShr ) ) continue ; Value * AshrOp1 = Ashr -> getOperand ( 1 ) ; ConstantInt * C = dyn_cast < ConstantInt > ( AshrOp1 ) ; if ( ! ( C && C -> getSExtValue ( ) == 16 ) ) continue ; Instruction * Shl = dyn_cast < Instruction > ( Ashr -> getOperand ( 0 ) ) ; if ( ! ( Shl && Shl -> getOpcode ( ) == Instruction :: Shl ) ) continue ; Value * Intr = Shl -> getOperand ( 0 ) ; Value * ShlOp1 = Shl -> getOperand ( 1 ) ; C = dyn_cast < ConstantInt > ( ShlOp1 ) ; if ( ! ( C && C -> getSExtValue ( ) == 16 ) ) continue ; if ( IntrinsicInst * I = dyn_cast < IntrinsicInst > ( Intr ) ) { if ( ! intrinsicAlreadySextended ( I -> getIntrinsicID ( ) ) ) continue ; for ( auto UI = Ashr -> user_begin ( ) , UE = Ashr -> user_end ( ) ; UI != UE ; ++ UI ) { const Use & TheUse = UI . getUse ( ) ; if ( Instruction * J = dyn_cast < Instruction > ( TheUse . getUser ( ) ) ) { J -> replaceUsesOfWith ( Ashr , I ) ; } } } } } return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> SDValue AArch64TargetLowering :: getRecipEstimate ( SDValue Operand , SelectionDAG & DAG , int Enabled , int & ExtraSteps ) const { if ( Enabled == ReciprocalEstimate :: Enabled ) if ( SDValue Estimate = getEstimate ( Subtarget , AArch64ISD :: FRECPE , Operand , DAG , ExtraSteps ) ) { SDLoc DL ( Operand ) ; EVT VT = Operand . getValueType ( ) ; SDNodeFlags Flags ; Flags . setUnsafeAlgebra ( true ) ; for ( int i = ExtraSteps ; i > 0 ; -- i ) { SDValue Step = DAG . getNode ( AArch64ISD :: FRECPS , DL , VT , Operand , Estimate , Flags ) ; Estimate = DAG . getNode ( ISD :: FMUL , DL , VT , Estimate , Step , Flags ) ; } ExtraSteps = 0 ; return Estimate ; } return SDValue ( ) ; } </s>

Return a reciprocal estimate value for the input operand .


<s> bool ARMTTIImpl :: isLegalMaskedGather ( Type * Ty , MaybeAlign Alignment ) { if ( ! EnableMaskedGatherScatters || ! ST -> hasMVEIntegerOps ( ) ) return false ; if ( isa < VectorType > ( Ty ) ) return false ; unsigned EltWidth = Ty -> getScalarSizeInBits ( ) ; return ( ( EltWidth == 32 && ( ! Alignment || * Alignment >= 4 ) ) || ( EltWidth == 16 && ( ! Alignment || * Alignment >= 2 ) ) || EltWidth == 8 ) ; } </s>

Return true if the target supports masked gather .


<s>
OperandMatchResultTy
LoongArchAsmParser
::
tryParseRegister
(
unsigned
&
RegNo
,
SMLoc
&
StartLoc
,
SMLoc
&
EndLoc
)
{
llvm_unreachable
(
"Unimplemented function."
)
;
}
</s>

tryParseRegister - parse one register if possible

LoongArch
LoongArch
"Unimplemented function."


<s> void tilepro_init_expanders ( void ) { init_machine_status = tilepro_init_machine_status ; if ( cfun && cfun -> machine && flag_pic ) { static int label_num = 0 ; char text_label_name [ 32 ] ; struct machine_function * machine = cfun -> machine ; ASM_GENERATE_INTERNAL_LABEL ( text_label_name , "L_PICLNK" , label_num ++ ) ; machine -> text_label_symbol = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( text_label_name ) ) ; machine -> text_label_rtx = gen_rtx_REG ( Pmode , TILEPRO_PIC_TEXT_LABEL_REGNUM ) ; machine -> got_rtx = gen_rtx_REG ( Pmode , PIC_OFFSET_TABLE_REGNUM ) ; machine -> calls_tls_get_addr = false ; } } </s>

Do anything needed before RTL is emitted for each function .


<s> tree function_resolver :: resolve_uniform_opt_n ( unsigned int nops ) { unsigned int i , nargs ; type_suffix_index type ; if ( ! check_gp_argument ( nops , i , nargs ) || ( type = infer_vector_type ( i ) ) == NUM_TYPE_SUFFIXES ) return error_mark_node ; unsigned int first_arg = i ++ ; for ( ; i < nargs - 1 ; ++ i ) if ( ! require_matching_vector_type ( i , type ) ) return error_mark_node ; return finish_opt_n_resolution ( i , first_arg , type ) ; } </s>

Resolve a ( possibly predicated ) function that offers a choice between taking : - NOPS like-typed vector arguments or - NOPS - 1 like-typed vector arguments followed by a scalar argument Return the function decl of the resolved function on success , otherwise report a suitable error and return error_mark_node .


<s> virtual const mprocInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> static void unicosmk_output_deferred_case_vectors ( FILE * file ) { struct machine_function * machine = cfun -> machine ; rtx t ; if ( machine -> addr_list == NULL_RTX ) return ; data_section ( ) ; for ( t = machine -> addr_list ; t ; t = XEXP ( t , 1 ) ) unicosmk_output_addr_vec ( file , XEXP ( t , 0 ) ) ; } </s>

Output current function 's deferred case vectors .


<s> virtual unsigned int execute ( function * fun ) { return pcrel_opt_pass ( fun ) ; } </s>


<s> static bool classof ( const MCExpr * E ) { return E -> getKind ( ) == MCExpr :: Target ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> static bool riscv_int_order_operand_ok_p ( enum rtx_code code , rtx cmp1 ) { switch ( code ) { case GT : case GTU : return reg_or_0_operand ( cmp1 , VOIDmode ) ; case GE : case GEU : return cmp1 == const1_rtx ; case LT : case LTU : return arith_operand ( cmp1 , VOIDmode ) ; case LE : return sle_operand ( cmp1 , VOIDmode ) ; case LEU : return sleu_operand ( cmp1 , VOIDmode ) ; default : gcc_unreachable ( ) ; } } </s>

Return true if CMP1 is a suitable second operand for integer ordering test CODE . See also the * sCC patterns in riscv.md .


<s> SMLoc getStartLoc ( ) const { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> void MipsTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s> void SystemZELFFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; SystemZMachineFunctionInfo * ZFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; bool BackChain = MF . getFunction ( ) . hasFnAttribute ( "backchain" ) ; if ( ! usePackedStack ( MF ) || BackChain ) getOrCreateFramePointerSaveIndex ( MF ) ; uint64_t StackSize = ( MFFrame . estimateStackSize ( MF ) + SystemZMC :: ELFCallFrameSize ) ; int64_t MaxArgOffset = 0 ; for ( int I = MFFrame . getObjectIndexBegin ( ) ; I != 0 ; ++ I ) if ( MFFrame . getObjectOffset ( I ) >= 0 ) { int64_t ArgOffset = MFFrame . getObjectOffset ( I ) + MFFrame . getObjectSize ( I ) ; MaxArgOffset = std :: max ( MaxArgOffset , ArgOffset ) ; } uint64_t MaxReach = StackSize + MaxArgOffset ; if ( ! isUInt < 12 > ( MaxReach ) ) { RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( 8 , Align ( 8 ) , false ) ) ; RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( 8 , Align ( 8 ) , false ) ) ; } if ( MF . front ( ) . isLiveIn ( SystemZ :: R6D ) && ZFI -> getRestoreGPRRegs ( ) . LowGPR != SystemZ :: R6D ) for ( auto & MO : MRI -> use_nodbg_operands ( SystemZ :: R6D ) ) MO . setIsKill ( false ) ; } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < AssumptionCacheTracker > ( ) ; AU . addRequired < LegacyDivergenceAnalysis > ( ) ; if ( ! ExpandDiv64InIR ) AU . setPreservesAll ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


"Code generation for MIPS-I is not implemented"

"Code generation for MIPS-V is not implemented"

"MSA requires a 64-bit FPU register file (FR=1 mode). "

"-mattr=+nooddspreg requires the O32 ABI."

"FPXX is not permitted for the N32/N64 ABI's."

"position-independent code requires '-mabicalls'"

"warning: cannot use small-data accesses for '-mabicalls'"

This constructor initializes the data members to match that of the specified triple .


<s> static void mn10300_encode_section_info ( tree decl , rtx rtl , int first ) { rtx symbol ; default_encode_section_info ( decl , rtl , first ) ; if ( ! MEM_P ( rtl ) ) return ; symbol = XEXP ( rtl , 0 ) ; if ( GET_CODE ( symbol ) != SYMBOL_REF ) return ; if ( flag_pic ) SYMBOL_REF_FLAG ( symbol ) = ( * targetm . binds_local_p ) ( decl ) ; } </s>

If using PIC , mark a SYMBOL_REF for a non-global symbol so that we may access it using GOTOFF instead of GOT .


<s> int hard_regno_mode_ok ( int regno , machine_mode mode ) { if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) return ( regno & 1 ) == 0 && GPR_P ( regno ) ; else return 1 ; } </s>

Value is 1 if hard register REGNO can hold a value of machine-mode MODE .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == 0 ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s>
virtual
StringRef
getPassName
(
)
const
override
{
return
"Cpu0 Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
bool
ARMBaseInstrInfo
::
expandPostRAPseudo
(
MachineInstr
&
MI
)
const
{
if
(
MI
.
getOpcode
(
)
==
TargetOpcode
::
LOAD_STACK_GUARD
)
{
expandLoadStackGuard
(
MI
)
;
MI
.
getParent
(
)
->
erase
(
MI
)
;
return
true
;
}
if
(
MI
.
getOpcode
(
)
==
ARM
::
MEMCPY
)
{
expandMEMCPY
(
MI
)
;
return
true
;
}
if
(
!
MI
.
isCopy
(
)
||
Subtarget
.
dontWidenVMOVS
(
)
||
!
Subtarget
.
hasFP64
(
)
)
return
false
;
Register
DstRegS
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
Register
SrcRegS
=
MI
.
getOperand
(
1
)
.
getReg
(
)
;
if
(
!
ARM
::
SPRRegClass
.
contains
(
DstRegS
,
SrcRegS
)
)
return
false
;
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
unsigned
DstRegD
=
TRI
->
getMatchingSuperReg
(
DstRegS
,
ARM
::
ssub_0
,
&
ARM
::
DPRRegClass
)
;
unsigned
SrcRegD
=
TRI
->
getMatchingSuperReg
(
SrcRegS
,
ARM
::
ssub_0
,
&
ARM
::
DPRRegClass
)
;
if
(
!
DstRegD
||
!
SrcRegD
)
return
false
;
if
(
!
MI
.
definesRegister
(
DstRegD
,
TRI
)
||
MI
.
readsRegister
(
DstRegD
,
TRI
)
)
return
false
;
if
(
MI
.
getOperand
(
0
)
.
isDead
(
)
)
return
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"widening:    "
<<
MI
)
;
MachineInstrBuilder
MIB
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
;
int
ImpDefIdx
=
MI
.
findRegisterDefOperandIdx
(
DstRegD
)
;
if
(
ImpDefIdx
!=
1
)
MI
.
removeOperand
(
ImpDefIdx
)
;
MI
.
setDesc
(
get
(
ARM
::
VMOVD
)
)
;
MI
.
getOperand
(
0
)
.
setReg
(
DstRegD
)
;
MI
.
getOperand
(
1
)
.
setReg
(
SrcRegD
)
;
MIB
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
MI
.
getOperand
(
1
)
.
setIsUndef
(
)
;
MIB
.
addReg
(
SrcRegS
,
RegState
::
Implicit
)
;
if
(
MI
.
getOperand
(
1
)
.
isKill
(
)
)
{
MI
.
getOperand
(
1
)
.
setIsKill
(
false
)
;
MI
.
addRegisterKilled
(
SrcRegS
,
TRI
,
true
)
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"replaced by: "
<<
MI
)
;
return
true
;
}
</s>

This function is called for all pseudo instructions that remain after register allocation .


<s> bool nonpic_symbol_mentioned_p ( rtx x ) { if ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF || GET_CODE ( x ) == PC ) return true ; if ( GET_CODE ( x ) == CONST_DOUBLE ) return false ; if ( GET_CODE ( x ) == UNSPEC && ( XINT ( x , 1 ) == UNSPEC_PIC || XINT ( x , 1 ) == UNSPEC_GOT || XINT ( x , 1 ) == UNSPEC_GOTOFF || XINT ( x , 1 ) == UNSPEC_GOTPLT || XINT ( x , 1 ) == UNSPEC_GOTTPOFF || XINT ( x , 1 ) == UNSPEC_DTPOFF || XINT ( x , 1 ) == UNSPEC_TPOFF || XINT ( x , 1 ) == UNSPEC_PLT || XINT ( x , 1 ) == UNSPEC_PCREL || XINT ( x , 1 ) == UNSPEC_SYMOFF || XINT ( x , 1 ) == UNSPEC_PCREL_SYMOFF || XINT ( x , 1 ) == UNSPEC_GOTFUNCDESC || XINT ( x , 1 ) == UNSPEC_GOTOFFFUNCDESC ) ) return false ; const char * fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( int i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { for ( int j = XVECLEN ( x , i ) - 1 ; j >= 0 ; j -- ) if ( nonpic_symbol_mentioned_p ( XVECEXP ( x , i , j ) ) ) return true ; } else if ( fmt [ i ] == 'e' && nonpic_symbol_mentioned_p ( XEXP ( x , i ) ) ) return true ; } return false ; } </s>

Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol is n't protected by a PIC unspec .


<s> static bool vspltis_constant ( rtx op , unsigned step , unsigned copies ) { enum machine_mode mode = GET_MODE ( op ) ; enum machine_mode inner = GET_MODE_INNER ( mode ) ; unsigned i ; unsigned nunits = GET_MODE_NUNITS ( mode ) ; unsigned bitsize = GET_MODE_BITSIZE ( inner ) ; unsigned mask = GET_MODE_MASK ( inner ) ; rtx last = CONST_VECTOR_ELT ( op , nunits - 1 ) ; HOST_WIDE_INT val = INTVAL ( last ) ; HOST_WIDE_INT splat_val = val ; HOST_WIDE_INT msb_val = val > 0 ? 0 : - 1 ; for ( i = 2 ; i <= copies ; i *= 2 ) { HOST_WIDE_INT small_val ; bitsize /= 2 ; small_val = splat_val >> bitsize ; mask >>= bitsize ; if ( splat_val != ( ( small_val << bitsize ) | ( small_val & mask ) ) ) return false ; splat_val = small_val ; } if ( EASY_VECTOR_15 ( splat_val ) ) ; else if ( EASY_VECTOR_15_ADD_SELF ( splat_val ) && ( splat_val >= 0 || ( step == 1 && copies == 1 ) ) ) ; else return false ; for ( i = 0 ; i < nunits - 1 ; ++ i ) { HOST_WIDE_INT desired_val ; if ( ( ( i + 1 ) & ( step - 1 ) ) == 0 ) desired_val = val ; else desired_val = msb_val ; if ( desired_val != INTVAL ( CONST_VECTOR_ELT ( op , i ) ) ) return false ; } return true ; } </s>

Return true if OP can be synthesized with a particular vspltisb , vspltish or vspltisw instruction . OP is a CONST_VECTOR . Which instruction is used depends on STEP and COPIES , one of which will be 1 . If COPIES > 1 , all items are set to the same value and contain COPIES replicas of the vsplt 's operand ; if STEP > 1 , one in STEP elements is set to the vsplt 's operand and the others are set to the value of the operand 's msb .


<s> static inline void s390_indirect_branch_attrvalue ( tree attr , enum indirect_branch * val ) { const char * str = TREE_STRING_POINTER ( TREE_VALUE ( TREE_VALUE ( attr ) ) ) ; if ( strcmp ( str , "keep" ) == 0 ) * val = indirect_branch_keep ; else if ( strcmp ( str , "thunk" ) == 0 ) * val = indirect_branch_thunk ; else if ( strcmp ( str , "thunk-inline" ) == 0 ) * val = indirect_branch_thunk_inline ; else if ( strcmp ( str , "thunk-extern" ) == 0 ) * val = indirect_branch_thunk_extern ; } </s>

Set VAL to correct enum value according to the indirect-branch or function-return attribute in ATTR .


<s>
static
void
or1k_print_operand
(
FILE
*
file
,
rtx
x
,
int
code
)
{
rtx
operand
=
x
;
switch
(
code
)
{
case
'#'
:
if
(
final_sequence
==
)
fputs
(
"\n\t l.nop\n"
,
file
)
;
break
;
case
'r'
:
if
(
REG_P
(
x
)
)
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
operand
)
]
)
;
else
if
(
x
==
CONST0_RTX
(
GET_MODE
(
x
)
)
)
fprintf
(
file
,
"r0"
)
;
else
output_operand_lossage
(
"invalid %%r value"
)
;
break
;
case
'H'
:
if
(
REG_P
(
x
)
)
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
operand
)
+
1
]
)
;
else
output_operand_lossage
(
"invalid %%H value"
)
;
break
;
case
'h'
:
print_reloc
(
file
,
x
,
0
,
RKIND_HI
)
;
break
;
case
'L'
:
print_reloc
(
file
,
x
,
0
,
RKIND_LO
)
;
break
;
case
'P'
:
if
(
!
flag_pic
||
SYMBOL_REF_LOCAL_P
(
x
)
)
output_addr_const
(
file
,
x
)
;
else
output_addr_reloc
(
file
,
x
,
0
,
"plt"
)
;
break
;
case
0
:
switch
(
GET_CODE
(
operand
)
)
{
case
REG
:
if
(
REGNO
(
operand
)
>
31
)
internal_error
(
"internal error: bad register: %d"
,
REGNO
(
operand
)
)
;
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
operand
)
]
)
;
break
;
case
MEM
:
output_address
(
GET_MODE
(
XEXP
(
operand
,
0
)
)
,
XEXP
(
operand
,
0
)
)
;
break
;
case
CODE_LABEL
:
case
LABEL_REF
:
output_asm_label
(
operand
)
;
break
;
default
:
if
(
CONSTANT_P
(
operand
)
)
output_addr_const
(
file
,
operand
)
;
else
internal_error
(
"unexpected operand: %d"
,
GET_CODE
(
operand
)
)
;
break
;
}
break
;
default
:
output_operand_lossage
(
"unknown operand letter: '%c'"
,
code
)
;
break
;
}
}
</s>

Worker for TARGET_PRINT_OPERAND . Print operand X , an RTX , to the file FILE . The output is formed as expected by the OpenRISC assember . CODE is the letter following a ' % ' in an instrunction template used to control the RTX output . Example ( s ) : CODE RTX OUTPUT COMMENT 0 ( reg : SI 3 ) r3 output an operand r ( reg : SI 3 ) r3 output a register or const zero H ( reg : SI 3 ) r4 output the high pair register h ( symbol_ref : SI ( `` x '' ) ) ha ( x ) output a signed high relocation L ( symbol_ref : SI ( `` x '' ) ) lo ( x ) output a low relocation Note , ' # ' is a special code used to fill the branch delay slot with an l.nop instruction . The l.nop ( no-op ) instruction is only outputted when the delay slot has not been filled .


<s> unsigned SIInstrInfo :: readlaneVGPRToSGPR ( unsigned SrcReg , MachineInstr & UseMI , MachineRegisterInfo & MRI ) const { const TargetRegisterClass * VRC = MRI . getRegClass ( SrcReg ) ; const TargetRegisterClass * SRC = RI . getEquivalentSGPRClass ( VRC ) ; Register DstReg = MRI . createVirtualRegister ( SRC ) ; unsigned SubRegs = RI . getRegSizeInBits ( * VRC ) / 32 ; if ( RI . hasAGPRs ( VRC ) ) { VRC = RI . getEquivalentVGPRClass ( VRC ) ; Register NewSrcReg = MRI . createVirtualRegister ( VRC ) ; BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) , NewSrcReg ) . addReg ( SrcReg ) ; SrcReg = NewSrcReg ; } if ( SubRegs == 1 ) { BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( AMDGPU :: V_READFIRSTLANE_B32 ) , DstReg ) . addReg ( SrcReg ) ; return DstReg ; } SmallVector < unsigned , 8 > SRegs ; for ( unsigned i = 0 ; i < SubRegs ; ++ i ) { Register SGPR = MRI . createVirtualRegister ( & AMDGPU :: SGPR_32RegClass ) ; BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( AMDGPU :: V_READFIRSTLANE_B32 ) , SGPR ) . addReg ( SrcReg , 0 , RI . getSubRegFromChannel ( i ) ) ; SRegs . push_back ( SGPR ) ; } MachineInstrBuilder MIB = BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( AMDGPU :: REG_SEQUENCE ) , DstReg ) ; for ( unsigned i = 0 ; i < SubRegs ; ++ i ) { MIB . addReg ( SRegs [ i ] ) ; MIB . addImm ( RI . getSubRegFromChannel ( i ) ) ; } return DstReg ; } </s>

Copy a value from a VGPR ( SrcReg ) to SGPR .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { const M68kSubtarget & STI = MF . getSubtarget < M68kSubtarget > ( ) ; M68kMachineFunctionInfo * MxFI = MF . getInfo < M68kMachineFunctionInfo > ( ) ; unsigned GlobalBaseReg = MxFI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg == 0 ) return false ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; const M68kInstrInfo * TII = STI . getInstrInfo ( ) ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( M68k :: LEA32q ) , GlobalBaseReg ) . addExternalSymbol ( "_GLOBAL_OFFSET_TABLE_" , M68kII :: MO_GOTPCREL ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> void RV16KPassConfig :: addPreEmitPass2 ( ) { addPass ( createRV16KExpandPseudoPass ( ) , false , true ) ; } </s>

Targets may add passes immediately before machine code is emitted in this callback .


<s> inline bool vgpr_1reg_mode_p ( machine_mode mode ) { return ( mode == SImode || mode == SFmode || mode == HImode || mode == QImode || mode == V64QImode || mode == V64HImode || mode == V64SImode || mode == V64HFmode || mode == V64SFmode || mode == BImode ) ; } </s>

Return true if MODE is valid for 1 VGPR register .


<s> Optional < MCFixupKind > ARMAsmBackend :: getFixupKind ( StringRef Name ) const { if ( ! STI . getTargetTriple ( ) . isOSBinFormatELF ( ) ) return None ; unsigned Type = llvm :: StringSwitch < unsigned > ( Name ) . Case ( "BFD_RELOC_NONE" , ELF :: R_ARM_NONE ) . Case ( "BFD_RELOC_8" , ELF :: R_ARM_ABS8 ) . Case ( "BFD_RELOC_16" , ELF :: R_ARM_ABS16 ) . Case ( "BFD_RELOC_32" , ELF :: R_ARM_ABS32 ) . Default ( - 1u ) ; if ( Type == - 1u ) return None ; return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s>
bool
AArch64MIPeepholeOpt
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
TII
=
static_cast
<
const
AArch64InstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
TRI
=
static_cast
<
const
AArch64RegisterInfo
*
>
(
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
)
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
assert
(
MRI
->
isSSA
(
)
&&
"Expected to be run on SSA form!"
)
;
bool
Changed
=
false
;
SmallSetVector
<
MachineInstr
*
,
8
>
ToBeRemoved
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
for
(
MachineInstr
&
MI
:
MBB
)
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
AArch64
::
ANDWrr
:
Changed
=
visitAND
<
uint32_t
>
(
AArch64
::
ANDWri
,
MI
,
ToBeRemoved
)
;
break
;
case
AArch64
::
ANDXrr
:
Changed
=
visitAND
<
uint64_t
>
(
AArch64
::
ANDXri
,
MI
,
ToBeRemoved
)
;
break
;
case
AArch64
::
ORRWrs
:
Changed
=
visitORR
(
MI
,
ToBeRemoved
)
;
break
;
case
AArch64
::
ADDWrr
:
Changed
=
visitADDSUB
<
uint32_t
>
(
AArch64
::
ADDWri
,
AArch64
::
SUBWri
,
MI
,
ToBeRemoved
)
;
break
;
case
AArch64
::
SUBWrr
:
Changed
=
visitADDSUB
<
uint32_t
>
(
AArch64
::
SUBWri
,
AArch64
::
ADDWri
,
MI
,
ToBeRemoved
)
;
break
;
case
AArch64
::
ADDXrr
:
Changed
=
visitADDSUB
<
uint64_t
>
(
AArch64
::
ADDXri
,
AArch64
::
SUBXri
,
MI
,
ToBeRemoved
)
;
break
;
case
AArch64
::
SUBXrr
:
Changed
=
visitADDSUB
<
uint64_t
>
(
AArch64
::
SUBXri
,
AArch64
::
ADDXri
,
MI
,
ToBeRemoved
)
;
break
;
case
AArch64
::
ADDSWrr
:
Changed
=
visitADDSSUBS
<
uint32_t
>
(
{
AArch64
::
ADDWri
,
AArch64
::
ADDSWri
}
,
{
AArch64
::
SUBWri
,
AArch64
::
SUBSWri
}
,
MI
,
ToBeRemoved
)
;
break
;
case
AArch64
::
SUBSWrr
:
Changed
=
visitADDSSUBS
<
uint32_t
>
(
{
AArch64
::
SUBWri
,
AArch64
::
SUBSWri
}
,
{
AArch64
::
ADDWri
,
AArch64
::
ADDSWri
}
,
MI
,
ToBeRemoved
)
;
break
;
case
AArch64
::
ADDSXrr
:
Changed
=
visitADDSSUBS
<
uint64_t
>
(
{
AArch64
::
ADDXri
,
AArch64
::
ADDSXri
}
,
{
AArch64
::
SUBXri
,
AArch64
::
SUBSXri
}
,
MI
,
ToBeRemoved
)
;
break
;
case
AArch64
::
SUBSXrr
:
Changed
=
visitADDSSUBS
<
uint64_t
>
(
{
AArch64
::
SUBXri
,
AArch64
::
SUBSXri
}
,
{
AArch64
::
ADDXri
,
AArch64
::
ADDSXri
}
,
MI
,
ToBeRemoved
)
;
break
;
}
}
}
for
(
MachineInstr
*
MI
:
ToBeRemoved
)
MI
->
eraseFromParent
(
)
;
return
Changed
;
}
</s>


<s> static void csky_setup_incoming_varargs ( cumulative_args_t pcum_v , const function_arg_info & arg , int * pretend_size , int second_time ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * pcum = get_cumulative_args ( pcum_v ) ; CUMULATIVE_ARGS local_cum ; cumulative_args_t local_cum_v = pack_cumulative_args ( & local_cum ) ; int regs_to_push ; cfun -> machine -> uses_anonymous_args = 1 ; local_cum = * pcum ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) ) csky_function_arg_advance ( local_cum_v , arg ) ; regs_to_push = CSKY_NPARM_REGS - local_cum . reg ; if ( regs_to_push ) * pretend_size = regs_to_push * UNITS_PER_WORD ; } </s>

Implement TARGET_SETUP_INCOMING_VARARGS . On C-Sky the copy from the argument registers to the stack is emitted by the prologue hooks , so here we just have to note how much stack space to save .


<s>
bool
AArch64AsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNum
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
&&
ExtraCode
[
0
]
!=
'a'
)
return
true
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNum
)
;
assert
(
MO
.
isReg
(
)
&&
"unexpected inline asm memory operand"
)
;
O
<<
"["
<<
AArch64InstPrinter
::
getRegisterName
(
MO
.
getReg
(
)
)
<<
"]"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s>
void
SystemZPostRASchedStrategy
::
leaveMBB
(
)
{
DEBUG
(
dbgs
(
)
<<
"+++ Leaving "
<<
printMBBReference
(
*
MBB
)
<<
"\n"
;
)
;
advanceTo
(
MBB
->
getFirstTerminator
(
)
)
;
}
</s>

Tell the strategy that current MBB is done .


<s> bool addPreISel ( ) override { addPass ( createFlattenCFGPass ( ) ) ; addPass ( createStructurizeCFGPass ( ) ) ; return false ; } </s>


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s>
void
relaxInstruction
(
const
MCInst
&
Inst
,
MCInst
&
Res
)
const
override
{
assert
(
0
&&
"relaxInstruction() unimplemented"
)
;
}
</s>

Sparc
0
"relaxInstruction() unimplemented"


<s> bool isToken ( ) const { return Kind == k_Token ; } </s>


<s> static AMDGPUOperand :: Ptr CreateReg ( const AMDGPUAsmParser * AsmParser , unsigned RegNo , SMLoc S , SMLoc E , bool ForceVOP3 ) { auto Op = llvm :: make_unique < AMDGPUOperand > ( Register , AsmParser ) ; Op -> Reg . RegNo = RegNo ; Op -> Reg . Mods = Modifiers ( ) ; Op -> Reg . IsForcedVOP3 = ForceVOP3 ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


"Inserting vccz bug work-around before: "


<s> static struct bundle_state * get_free_bundle_state ( void ) { struct bundle_state * result ; if ( free_bundle_state_chain != NULL ) { result = free_bundle_state_chain ; free_bundle_state_chain = result -> next ; } else { result = XNEW ( struct bundle_state ) ; result -> dfa_state = xmalloc ( dfa_state_size ) ; result -> allocated_states_chain = allocated_bundle_states_chain ; allocated_bundle_states_chain = result ; } result -> unique_num = bundle_states_num ++ ; return result ; } </s>

The following function returns a free bundle state .


<s> bool Z80AsmBackend :: mayNeedRelaxation ( const MCInst & Inst ) const { llvm_unreachable ( "Unimplemented" ) ; } </s>

Check whether the given instruction may need relaxation .


<s> std :: pair < InstructionCost , MVT > SITargetLowering :: getTypeLegalizationCost ( const DataLayout & DL , Type * Ty ) const { std :: pair < InstructionCost , MVT > Cost = TargetLoweringBase :: getTypeLegalizationCost ( DL , Ty ) ; auto Size = DL . getTypeSizeInBits ( Ty ) ; if ( Size <= 256 ) return Cost ; Cost . first = ( Size + 255 ) / 256 ; return Cost ; } </s>

Estimate the cost of type-legalization and the legalized type .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> int neon_vector_mem_operand ( rtx op , int type , bool strict ) { rtx ind ; if ( ! ( reload_in_progress || reload_completed ) && ( reg_mentioned_p ( frame_pointer_rtx , op ) || reg_mentioned_p ( arg_pointer_rtx , op ) || reg_mentioned_p ( virtual_incoming_args_rtx , op ) || reg_mentioned_p ( virtual_outgoing_args_rtx , op ) || reg_mentioned_p ( virtual_stack_dynamic_rtx , op ) || reg_mentioned_p ( virtual_stack_vars_rtx , op ) ) ) return ! strict ; if ( ! MEM_P ( op ) ) return FALSE ; ind = XEXP ( op , 0 ) ; if ( reload_completed && ( GET_CODE ( ind ) == LABEL_REF || ( GET_CODE ( ind ) == CONST && GET_CODE ( XEXP ( ind , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( ind , 0 ) , 0 ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( ind , 0 ) , 1 ) ) ) ) ) return TRUE ; if ( REG_P ( ind ) ) return arm_address_register_rtx_p ( ind , 0 ) ; if ( ( type != 1 && GET_CODE ( ind ) == POST_INC ) || ( type == 0 && GET_CODE ( ind ) == PRE_DEC ) ) return arm_address_register_rtx_p ( XEXP ( ind , 0 ) , 0 ) ; if ( type == 2 && GET_CODE ( ind ) == POST_MODIFY && GET_CODE ( XEXP ( ind , 1 ) ) == PLUS && REG_P ( XEXP ( XEXP ( ind , 1 ) , 1 ) ) ) return true ; if ( type == 0 && GET_CODE ( ind ) == PLUS && REG_P ( XEXP ( ind , 0 ) ) && REG_MODE_OK_FOR_BASE_P ( XEXP ( ind , 0 ) , VOIDmode ) && CONST_INT_P ( XEXP ( ind , 1 ) ) && INTVAL ( XEXP ( ind , 1 ) ) > - 1024 && ( INTVAL ( XEXP ( ind , 1 ) ) < ( VALID_NEON_QREG_MODE ( GET_MODE ( op ) ) ? 1016 : 1024 ) ) && ( INTVAL ( XEXP ( ind , 1 ) ) & 3 ) == 0 ) return TRUE ; return FALSE ; } </s>

Return TRUE if OP is a memory operand which we can load or store a vector to/from . TYPE is one of the following values : 0 - Vector load/stor ( vldr ) 1 - Core registers ( ldm ) 2 - Element/structure loads ( vld1 )


<s> static inline int rs6000_secondary_reload_toc_costs ( addr_mask_type addr_mask ) { int ret ; if ( TARGET_CMODEL != CMODEL_SMALL ) ret = ( ( addr_mask & RELOAD_REG_OFFSET ) == 0 ) ? 1 : 2 ; else ret = ( TARGET_MINIMAL_TOC ) ? 6 : 3 ; return ret ; } </s>

Helper function to return the cost of adding a TOC entry address .


<s> static tree s390_d_handle_target_float_abi ( void ) { const char * abi ; if ( TARGET_HARD_FLOAT ) abi = "hard" ; else if ( TARGET_SOFT_FLOAT ) abi = "soft" ; else abi = "" ; return build_string_literal ( strlen ( abi ) + 1 , abi ) ; } </s>

Handle a call to ` __traits ( getTargetInfo , `` floatAbi '' ) ' .


<s> LLT AArch64TargetLowering :: getOptimalMemOpLLT ( const MemOp & Op , const AttributeList & FuncAttributes ) const { bool CanImplicitFloat = ! FuncAttributes . hasFnAttr ( Attribute :: NoImplicitFloat ) ; bool CanUseNEON = Subtarget -> hasNEON ( ) && CanImplicitFloat ; bool CanUseFP = Subtarget -> hasFPARMv8 ( ) && CanImplicitFloat ; bool IsSmallMemset = Op . isMemset ( ) && Op . size ( ) < 32 ; auto AlignmentIsAcceptable = [ & ] ( EVT VT , Align AlignCheck ) { if ( Op . isAligned ( AlignCheck ) ) return true ; bool Fast ; return allowsMisalignedMemoryAccesses ( VT , 0 , Align ( 1 ) , MachineMemOperand :: MONone , & Fast ) && Fast ; } ; if ( CanUseNEON && Op . isMemset ( ) && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: v2i64 , Align ( 16 ) ) ) return LLT :: fixed_vector ( 2 , 64 ) ; if ( CanUseFP && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: f128 , Align ( 16 ) ) ) return LLT :: scalar ( 128 ) ; if ( Op . size ( ) >= 8 && AlignmentIsAcceptable ( MVT :: i64 , Align ( 8 ) ) ) return LLT :: scalar ( 64 ) ; if ( Op . size ( ) >= 4 && AlignmentIsAcceptable ( MVT :: i32 , Align ( 4 ) ) ) return LLT :: scalar ( 32 ) ; return LLT ( ) ; } </s>


<s>
static
void
v850_asm_init_sections
(
void
)
{
rosdata_section
=
get_unnamed_section
(
0
,
output_section_asm_op
,
"\t.section .rosdata,\"a\""
)
;
rozdata_section
=
get_unnamed_section
(
0
,
output_section_asm_op
,
"\t.section .rozdata,\"a\""
)
;
tdata_section
=
get_unnamed_section
(
SECTION_WRITE
,
output_section_asm_op
,
"\t.section .tdata,\"aw\""
)
;
zdata_section
=
get_unnamed_section
(
SECTION_WRITE
,
output_section_asm_op
,
"\t.section .zdata,\"aw\""
)
;
zbss_section
=
get_unnamed_section
(
SECTION_WRITE
|
SECTION_BSS
,
output_section_asm_op
,
"\t.section .zbss,\"aw\""
)
;
}
</s>


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
Register
:
OS
<<
"<register "
<<
getReg
(
)
<<
'>'
;
break
;
case
Immediate
:
OS
<<
getImm
(
)
;
break
;
case
Token
:
OS
<<
'\''
<<
getToken
(
)
<<
'\''
;
break
;
case
Expression
:
OS
<<
"<expr "
<<
*
Expr
<<
'>'
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> unsigned AMDGPUTTIImpl :: getNumberOfRegisters ( bool Vec ) const { return getHardwareNumberOfRegisters ( Vec ) >> 3 ; } </s>


<s> bool ARMAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'a' : if ( MI -> getOperand ( OpNum ) . isReg ( ) ) { O << "[" << TRI -> getAsmName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << "]" ; return false ; } case 'c' : if ( ! MI -> getOperand ( OpNum ) . isImm ( ) ) return true ; printNoHashImmediate ( MI , OpNum ) ; return false ; case 'P' : printOperand ( MI , OpNum ) ; return false ; case 'Q' : if ( TM . getTargetData ( ) -> isLittleEndian ( ) ) break ; case 'R' : if ( TM . getTargetData ( ) -> isBigEndian ( ) ) break ; case 'H' : if ( ! MI -> getOperand ( OpNum ) . isReg ( ) || OpNum + 1 == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNum + 1 ) . isReg ( ) ) return true ; ++ OpNum ; } } printOperand ( MI , OpNum ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s>
bool
FixupLEAPass
::
runOnMachineFunction
(
MachineFunction
&
Func
)
{
MF
=
&
Func
;
TM
=
&
Func
.
getTarget
(
)
;
const
X86Subtarget
&
ST
=
TM
->
getSubtarget
<
X86Subtarget
>
(
)
;
if
(
!
ST
.
LEAusesAG
(
)
&&
!
ST
.
slowLEA
(
)
)
return
false
;
TII
=
static_cast
<
const
X86InstrInfo
*
>
(
TM
->
getSubtargetImpl
(
)
->
getInstrInfo
(
)
)
;
DEBUG
(
dbgs
(
)
<<
"Start X86FixupLEAs\n"
;
)
;
for
(
MachineFunction
::
iterator
I
=
Func
.
begin
(
)
,
E
=
Func
.
end
(
)
;
I
!=
E
;
++
I
)
processBasicBlock
(
Func
,
I
)
;
DEBUG
(
dbgs
(
)
<<
"End X86FixupLEAs\n"
;
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> const TargetRegisterClass * SPURegisterInfo :: getPointerRegClass ( ) const { return & SPU :: R32CRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> unsigned M680x0InstrInfo :: getGlobalBaseReg ( MachineFunction * MF ) const { M680x0MachineFunctionInfo * MxFI = MF -> getInfo < M680x0MachineFunctionInfo > ( ) ; unsigned GlobalBaseReg = MxFI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg != 0 ) return GlobalBaseReg ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; GlobalBaseReg = RegInfo . createVirtualRegister ( & M680x0 :: AR32_NOSPRegClass ) ; MxFI -> setGlobalBaseReg ( GlobalBaseReg ) ; return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


"%qE attribute only applies to functions"

"requested %qE attribute is not a comma separated pair of"

" non-negative integer constants or too large (max. %d)"

Check whether the hotpatch attribute is applied to a function and , if it has an argument , the argument is valid .


<s> const AMDGPUInstrInfo * getInstrInfo ( ) const override { return InstrInfo . get ( ) ; } </s>