<s> void scalar_chain :: convert_insn_common ( rtx_insn * insn ) { for ( df_ref ref = DF_INSN_DEFS ( insn ) ; ref ; ref = DF_REF_NEXT_LOC ( ref ) ) if ( bitmap_bit_p ( defs_conv , DF_REF_REGNO ( ref ) ) ) { df_link * use ; for ( use = DF_REF_CHAIN ( ref ) ; use ; use = use -> next ) if ( NONDEBUG_INSN_P ( DF_REF_INSN ( use -> ref ) ) && ( DF_REF_REG_MEM_P ( use -> ref ) || ! bitmap_bit_p ( insns , DF_REF_INSN_UID ( use -> ref ) ) ) ) break ; if ( use ) convert_reg ( insn , DF_REF_REG ( ref ) , * defs_map . get ( regno_reg_rtx [ DF_REF_REGNO ( ref ) ] ) ) ; else if ( MAY_HAVE_DEBUG_BIND_INSNS ) { auto_vec < rtx_insn * , 5 > to_reset_debug_insns ; for ( use = DF_REF_CHAIN ( ref ) ; use ; use = use -> next ) if ( DEBUG_INSN_P ( DF_REF_INSN ( use -> ref ) ) ) { rtx_insn * debug_insn = DF_REF_INSN ( use -> ref ) ; df_link * def ; for ( def = DF_REF_CHAIN ( use -> ref ) ; def ; def = def -> next ) if ( ! bitmap_bit_p ( insns , DF_REF_INSN_UID ( def -> ref ) ) ) break ; if ( def ) to_reset_debug_insns . safe_push ( debug_insn ) ; else { * DF_REF_REAL_LOC ( use -> ref ) = * defs_map . get ( regno_reg_rtx [ DF_REF_REGNO ( ref ) ] ) ; df_insn_rescan ( debug_insn ) ; } } while ( ! to_reset_debug_insns . is_empty ( ) ) { rtx_insn * debug_insn = to_reset_debug_insns . pop ( ) ; INSN_VAR_LOCATION_LOC ( debug_insn ) = gen_rtx_UNKNOWN_VAR_LOC ( ) ; df_insn_rescan_debug_internal ( debug_insn ) ; } } } for ( df_ref ref = DF_INSN_USES ( insn ) ; ref ; ref = DF_REF_NEXT_LOC ( ref ) ) if ( ! DF_REF_REG_MEM_P ( ref ) ) if ( rtx * vreg = defs_map . get ( regno_reg_rtx [ DF_REF_REGNO ( ref ) ] ) ) { rtx note = find_reg_note ( insn , REG_DEAD , DF_REF_REG ( ref ) ) ; if ( note ) XEXP ( note , 0 ) = * vreg ; * DF_REF_REAL_LOC ( ref ) = * vreg ; } } </s>

Helper function for converting INSN to vector mode .


<s> bool SystemZTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { if ( Imm . isZero ( ) || Imm . isNegZero ( ) ) return true ; if ( ! Subtarget . hasVector ( ) ) return false ; const SystemZInstrInfo * TII = static_cast < const SystemZInstrInfo * > ( Subtarget . getInstrInfo ( ) ) ; unsigned Start , End ; return analyzeFPImm ( Imm , VT . getSizeInBits ( ) , Start , End , TII ) ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> static void unicosmk_output_default_externs ( FILE * file ) { static const char * const externs [ ] = { "__T3E_MISMATCH" } ; int i ; int n ; n = ARRAY_SIZE ( externs ) ; for ( i = 0 ; i < n ; i ++ ) fprintf ( file , "\t.extern\t%s\n" , externs [ i ] ) ; } </s>

Output extern declarations which are required for every asm file .


<s> bool SICRegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s>
bool
X86TargetLowering
::
lowerInterleavedStore
(
StoreInst
*
SI
,
ShuffleVectorInst
*
SVI
,
unsigned
Factor
)
const
{
assert
(
Factor
>=
2
&&
Factor
<=
getMaxSupportedInterleaveFactor
(
)
&&
"Invalid interleave factor"
)
;
assert
(
SVI
->
getType
(
)
->
getVectorNumElements
(
)
%
Factor
==
0
&&
"Invalid interleaved store"
)
;
SmallVector
<
unsigned
,
4
>
Indices
;
auto
Mask
=
SVI
->
getShuffleMask
(
)
;
for
(
unsigned
i
=
0
;
i
<
Factor
;
i
++
)
Indices
.
push_back
(
Mask
[
i
]
)
;
ArrayRef
<
ShuffleVectorInst
*
>
Shuffles
=
makeArrayRef
(
SVI
)
;
IRBuilder
<
>
Builder
(
SI
)
;
X86InterleavedAccessGroup
Grp
(
SI
,
Shuffles
,
Indices
,
Factor
,
Subtarget
,
Builder
)
;
return
Grp
.
isSupported
(
)
&&
Grp
.
lowerIntoOptimizedSequence
(
)
;
}
</s>

Lower interleaved store ( s ) into target specific instructions/intrinsics .


<s> bool SICTargetLowering :: isEligibleForTailCallOptimization ( const SICCC & SICCCInfo , unsigned NextStackOffset , const SICFunctionInfo & FI ) const { return false ; if ( SICCCInfo . hasByValArg ( ) || FI . hasByvalArg ( ) ) return false ; return NextStackOffset <= FI . getIncomingArgSize ( ) ; } </s>

Returns true if the call can be lowered as a tail call .


<s> void MetadataStreamer :: begin ( const Module & Mod ) { AMDGPUASI = getAMDGPUAS ( Mod ) ; emitVersion ( ) ; emitPrintf ( Mod ) ; } </s>


<s> int ARMAsmParser :: tryParseRegister ( ) { MCAsmParser & Parser = getParser ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return - 1 ; std :: string lowerCase = Tok . getString ( ) . lower ( ) ; unsigned RegNum = MatchRegisterName ( lowerCase ) ; if ( ! RegNum ) { RegNum = StringSwitch < unsigned > ( lowerCase ) . Case ( "r13" , ARM :: SP ) . Case ( "r14" , ARM :: LR ) . Case ( "r15" , ARM :: PC ) . Case ( "ip" , ARM :: R12 ) . Case ( "a1" , ARM :: R0 ) . Case ( "a2" , ARM :: R1 ) . Case ( "a3" , ARM :: R2 ) . Case ( "a4" , ARM :: R3 ) . Case ( "v1" , ARM :: R4 ) . Case ( "v2" , ARM :: R5 ) . Case ( "v3" , ARM :: R6 ) . Case ( "v4" , ARM :: R7 ) . Case ( "v5" , ARM :: R8 ) . Case ( "v6" , ARM :: R9 ) . Case ( "v7" , ARM :: R10 ) . Case ( "v8" , ARM :: R11 ) . Case ( "sb" , ARM :: R9 ) . Case ( "sl" , ARM :: R10 ) . Case ( "fp" , ARM :: R11 ) . Default ( 0 ) ; } if ( ! RegNum ) { StringMap < unsigned > :: const_iterator Entry = RegisterReqs . find ( lowerCase ) ; if ( Entry == RegisterReqs . end ( ) ) return - 1 ; Parser . Lex ( ) ; return Entry -> getValue ( ) ; } if ( ! hasD32 ( ) && RegNum >= ARM :: D16 && RegNum <= ARM :: D31 ) return - 1 ; Parser . Lex ( ) ; return RegNum ; } </s>

tryParseRegister - parse one register if possible


<s> static bool mips_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { if ( ! TARGET_SIBCALLS ) return false ; if ( mips_interrupt_type_p ( TREE_TYPE ( current_function_decl ) ) ) return false ; if ( decl && const_call_insn_operand ( XEXP ( DECL_RTL ( decl ) , 0 ) , VOIDmode ) && mips_call_may_need_jalx_p ( decl ) ) return false ; if ( decl && TARGET_CALL_SAVED_GP && ! TARGET_ABICALLS_PIC0 && ! targetm . binds_local_p ( decl ) ) return false ; return true ; } </s>

We can handle any sibcall when TARGET_SIBCALLS is true .


<s> bool ARMBaseInstrInfo :: isSwiftFastImmShift ( const MachineInstr * MI ) const { if ( MI -> getNumOperands ( ) < 4 ) return true ; unsigned ShOpVal = MI -> getOperand ( 3 ) . getImm ( ) ; unsigned ShImm = ARM_AM :: getSORegOffset ( ShOpVal ) ; if ( ( ShImm == 1 && ARM_AM :: getSORegShOp ( ShOpVal ) == ARM_AM :: lsr ) || ( ( ShImm == 1 || ShImm == 2 ) && ARM_AM :: getSORegShOp ( ShOpVal ) == ARM_AM :: lsl ) ) return true ; return false ; } </s>

Returns true if the instruction has a shift by immediate that can be executed in one cycle less .


"-misched-topdown incompatible with -misched-bottomup"

Initialize the strategy after building the DAG for a new region .


<s> bool MipsPassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( getOptLevel ( ) ) ) ; return false ; } </s>

This method should install a ( global ) instruction selector pass , which converts possibly generic instructions to fully target-specific instructions , thereby constraining all generic virtual registers to register classes .


<s> static void mips_frame_barrier ( void ) { emit_clobber ( gen_frame_mem ( BLKmode , stack_pointer_rtx ) ) ; } </s>

Emit an optimisation barrier for accesses to the current frame .


<s> bool isVirtualSection ( ) const override { return false ; } </s>

Check whether this section is `` virtual '' , that is has no actual object file contents .


<s> bool isToken ( ) const override { return Kind == k_Token ; } </s>


<s> static machine_mode sparc_cstore_mode ( enum insn_code icode ATTRIBUTE_UNUSED ) { return ( TARGET_ARCH64 ? DImode : SImode ) ; } </s>


<s> bool isShuffleMaskLegal ( const SmallVectorImpl < int > & Mask , EVT VT ) const override { return false ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> std :: unique_ptr < MCObjectWriter > Nios2AsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { return createNios2ELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI ( OSType ) ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> SDValue PPCTargetLowering :: getSqrtEstimate ( SDValue Operand , SelectionDAG & DAG , int Enabled , int & RefinementSteps , bool & UseOneConstNR , bool Reciprocal ) const { EVT VT = Operand . getValueType ( ) ; if ( ( VT == MVT :: f32 && Subtarget . hasFRSQRTES ( ) ) || ( VT == MVT :: f64 && Subtarget . hasFRSQRTE ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasAltivec ( ) ) || ( VT == MVT :: v2f64 && Subtarget . hasVSX ( ) ) ) { if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = getEstimateRefinementSteps ( VT , Subtarget ) ; UseOneConstNR = ! Subtarget . needsTwoConstNR ( ) ; return DAG . getNode ( PPCISD :: FRSQRTE , SDLoc ( Operand ) , VT , Operand ) ; } return SDValue ( ) ; } </s>

Hooks for building estimates in place of slower divisions and square roots .


<s> void PPCPassConfig :: addIRPasses ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCBoolRetToIntPass ( ) ) ; addPass ( createAtomicExpandPass ( ) ) ; addPass ( createPPCLowerMASSVEntriesPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnablePPCGenScalarMASSEntries ) { TM -> Options . PPCGenScalarMASSEntries = EnablePPCGenScalarMASSEntries ; addPass ( createPPCGenScalarMASSEntriesPass ( ) ) ; } if ( EnablePrefetch . getNumOccurrences ( ) > 0 ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Default && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"X86 FP Stackifier"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


"Expected a reg or frame index operand."

Return true if this is a load/store that can be potentially paired/merged .


<s>
const
MCPhysReg
*
X86RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
bool
HasAVX
=
Subtarget
.
hasAVX
(
)
;
bool
HasAVX512
=
Subtarget
.
hasAVX512
(
)
;
assert
(
MF
&&
"MachineFunction required"
)
;
switch
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
)
{
case
CallingConv
::
GHC
:
case
CallingConv
::
HiPE
:
return
CSR_NoRegs_SaveList
;
case
CallingConv
::
AnyReg
:
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
return
CSR_64_AllRegs_SaveList
;
case
CallingConv
::
PreserveMost
:
return
CSR_64_RT_MostRegs_SaveList
;
case
CallingConv
::
PreserveAll
:
if
(
HasAVX
)
return
CSR_64_RT_AllRegs_AVX_SaveList
;
return
CSR_64_RT_AllRegs_SaveList
;
case
CallingConv
::
Intel_OCL_BI
:
{
if
(
HasAVX512
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX512
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX_SaveList
;
if
(
HasAVX
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX_SaveList
;
if
(
!
HasAVX
&&
!
IsWin64
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_SaveList
;
break
;
}
case
CallingConv
::
Cold
:
if
(
Is64Bit
)
return
CSR_64_MostRegs_SaveList
;
break
;
default
:
break
;
}
bool
CallsEHReturn
=
MF
->
getMMI
(
)
.
callsEHReturn
(
)
;
if
(
Is64Bit
)
{
if
(
IsWin64
)
return
CSR_Win64_SaveList
;
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
}
if
(
CallsEHReturn
)
return
CSR_32EHRet_SaveList
;
return
CSR_32_SaveList
;
}
</s>


<s> SDValue MergeValues ( ArrayRef < SDValue > Values ) { return DAG -> getMergeValues ( Values , dl ) ; } </s>

MergeValues - Compute and return the merge of the two specified lattice values .


<s> static bool alpha_print_operand_punct_valid_p ( unsigned char code ) { return ( code == '/' || code == ',' || code == '-' || code == '~' || code == '#' || code == '*' || code == '&' ) ; } </s>


<s> void TMS320C64XHazardRecognizer :: EmitInstruction ( SUnit * SU ) { DEBUG ( dbgs ( ) << "--emit\n" ) ; if ( isPseudo ( SU ) ) return ; if ( emitMove ( SU ) ) return ; Hzd -> book ( getUnitIndex ( SU ) , getExtraUse ( SU ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static void canonicalize_path_dirsep ( char * * path ) { char * t_path = * path ; int len = strlen ( t_path ) ; int i ; for ( i = 0 ; i < len ; i ++ ) if ( IS_DIR_SEPARATOR ( t_path [ i ] ) ) t_path [ i ] = DIR_SEPARATOR ; } </s>

This is to canonicalize the directory separators in the path . On Windows we could have a mix of '/ ' and '\ ' in the path .


<s> static bool ix86_const_not_ok_for_debug_p ( rtx x ) { if ( GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) != UNSPEC_GOTOFF ) return true ; if ( SYMBOL_REF_P ( x ) && strcmp ( XSTR ( x , 0 ) , GOT_SYMBOL_NAME ) == 0 ) return true ; return false ; } </s>

Return true if X should n't be emitted into the debug info . Disallow UNSPECs other than @ gotoff - we ca n't emit _GLOBAL_OFFSET_TABLE_ symbol easily into the .debug_info section , so we need not to delegitimize , but instead assemble as @ gotoff . Disallow _GLOBAL_OFFSET_TABLE_ SYMBOL_REF - the assembler magically assembles that as _GLOBAL_OFFSET_TABLE_- . expression .


<s> void RISCVFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterClass * RC = & RISCV :: GPRRegClass ; if ( ! isInt < 11 > ( MFI . estimateStackSize ( MF ) ) ) { int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlignment ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RegScavFI ) ; } } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> static void rs6000_destroy_cost_data ( void * data ) { free ( data ) ; } </s>


<s>
void
MOSInstPrinter
::
printInst
(
const
MCInst
*
MI
,
uint64_t
Address
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
,
raw_ostream
&
OS
)
{
std
::
string
AiryOperands
;
raw_string_ostream
AiryOperandStream
(
AiryOperands
)
;
auto
MnemonicInfo
=
getMnemonic
(
MI
)
;
assert
(
MnemonicInfo
.
second
&&
"Missing opcode for instruction."
)
;
printInstruction
(
MI
,
Address
,
AiryOperandStream
)
;
AiryOperands
=
AiryOperandStream
.
str
(
)
;
size_t
SpacesSeen
=
0
;
std
::
string
CorrectOperands
;
for
(
const
auto
&
Letter
:
AiryOperands
)
{
if
(
isspace
(
Letter
)
!=
0
)
{
if
(
++
SpacesSeen
<=
2
)
{
CorrectOperands
+=
'\t'
;
}
continue
;
}
CorrectOperands
+=
Letter
;
}
OS
<<
CorrectOperands
;
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s> SPScope :: child_iterator SPScope :: child_begin ( ) const { return Priv -> Subscopes . begin ( ) ; } </s>

nodes_iterator/begin/end - Allow iteration over all nodes in the graph


<s> DecodeStatus LoongArchDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CS ) const { uint32_t Insn ; DecodeStatus Result ; if ( Bytes . size ( ) < 4 ) { Size = 0 ; return MCDisassembler :: Fail ; } Insn = support :: endian :: read32le ( Bytes . data ( ) ) ; Result = decodeInstruction ( DecoderTable32 , MI , Insn , Address , this , STI ) ; Size = 4 ; return Result ; } </s>

Returns the disassembly of a single instruction .


<s> bool isToken ( ) const { return Kind == Token ; } </s>


<s> bool HexagonStoreWidening :: runOnMachineFunction ( MachineFunction & MFn ) { MF = & MFn ; auto & ST = MFn . getSubtarget < HexagonSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; MRI = & MFn . getRegInfo ( ) ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; bool Changed = false ; for ( auto & B : MFn ) Changed |= processBasicBlock ( B ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> LoadInst * X86TargetLowering :: lowerIdempotentRMWIntoFencedLoad ( AtomicRMWInst * AI ) const { unsigned NativeWidth = Subtarget -> is64Bit ( ) ? 64 : 32 ; Type * MemType = AI -> getType ( ) ; if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) return nullptr ; auto Builder = IRBuilder < > ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SynchScope = AI -> getSynchScope ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; auto Ptr = AI -> getPointerOperand ( ) ; if ( SynchScope == SingleThread ) return nullptr ; if ( ! hasMFENCE ( * Subtarget ) ) return nullptr ; Function * MFence = llvm :: Intrinsic :: getDeclaration ( M , Intrinsic :: x86_sse2_mfence ) ; Builder . CreateCall ( MFence , { } ) ; LoadInst * Loaded = Builder . CreateAlignedLoad ( Ptr , AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ) ; Loaded -> setAtomic ( Order , SynchScope ) ; AI -> replaceAllUsesWith ( Loaded ) ; AI -> eraseFromParent ( ) ; return Loaded ; } </s>

On some platforms , an AtomicRMW that never actually modifies the value ( such as fetch_add of 0 ) can be turned into a fence followed by an atomic load .


<s> bool X86RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return TM . getSubtargetImpl ( ) -> postRAScheduler ( ) ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> unsigned PPCTargetLowering :: getPrefLoopAlignment ( MachineLoop * ML ) const { switch ( Subtarget . getDarwinDirective ( ) ) { default : break ; case PPC :: DIR_970 : case PPC :: DIR_PWR4 : case PPC :: DIR_PWR5 : case PPC :: DIR_PWR5X : case PPC :: DIR_PWR6 : case PPC :: DIR_PWR6X : case PPC :: DIR_PWR7 : case PPC :: DIR_PWR8 : { if ( ! ML ) break ; const PPCInstrInfo * TII = Subtarget . getInstrInfo ( ) ; uint64_t LoopSize = 0 ; for ( auto I = ML -> block_begin ( ) , IE = ML -> block_end ( ) ; I != IE ; ++ I ) for ( auto J = ( * I ) -> begin ( ) , JE = ( * I ) -> end ( ) ; J != JE ; ++ J ) { LoopSize += TII -> GetInstSizeInBytes ( J ) ; if ( LoopSize > 32 ) break ; } if ( LoopSize > 16 && LoopSize <= 32 ) return 5 ; break ; } } return TargetLowering :: getPrefLoopAlignment ( ML ) ; } </s>


<s> unsigned ARMBaseInstrInfo :: isStoreToStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { SmallVector < const MachineMemOperand * , 1 > Accesses ; if ( MI . mayStore ( ) && hasStoreToStackSlot ( MI , Accesses ) ) { FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) -> getFrameIndex ( ) ; return true ; } return false ; } </s>

isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s> void x86_order_regs_for_local_alloc ( void ) { int pos = 0 ; int i ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( GENERAL_REGNO_P ( i ) && call_used_regs [ i ] ) reg_alloc_order [ pos ++ ] = i ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( GENERAL_REGNO_P ( i ) && ! call_used_regs [ i ] ) reg_alloc_order [ pos ++ ] = i ; if ( ! TARGET_SSE_MATH ) for ( i = FIRST_STACK_REG ; i <= LAST_STACK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_SSE_REG ; i <= LAST_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_REX_SSE_REG ; i <= LAST_REX_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; if ( TARGET_SSE_MATH ) for ( i = FIRST_STACK_REG ; i <= LAST_STACK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_MMX_REG ; i <= LAST_MMX_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; while ( pos < FIRST_PSEUDO_REGISTER ) reg_alloc_order [ pos ++ ] = 0 ; } </s>

Order the registers for register allocator .


<s> static rtx_insn * get_next_important_insn ( rtx_insn * insn , rtx_insn * tail ) { for ( ; insn && insn != tail ; insn = NEXT_INSN ( insn ) ) if ( important_for_bundling_p ( insn ) ) return insn ; return NULL ; } </s>

The following function returns an insn important for insn bundling followed by INSN and before TAIL .


<s> bool TL45AsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> const AArch64RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool PTXPassConfig :: addInstSelector ( ) { PM . add ( createPTXISelDag ( getPTXTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool mips_cannot_change_mode_class ( machine_mode from , machine_mode to , enum reg_class rclass ) { if ( GET_MODE_SIZE ( from ) == 8 && GET_MODE_SIZE ( to ) == 8 && INTEGRAL_MODE_P ( from ) && INTEGRAL_MODE_P ( to ) ) return false ; if ( MSA_SUPPORTED_MODE_P ( from ) && MSA_SUPPORTED_MODE_P ( to ) ) return false ; return reg_classes_intersect_p ( FP_REGS , rclass ) ; } </s>


<s> void mips_output_aligned_decl_common ( FILE * stream , tree decl , const char * name , unsigned HOST_WIDE_INT size , unsigned int align ) { if ( TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA && TREE_CODE ( decl ) == VAR_DECL && TREE_READONLY ( decl ) && ( DECL_INITIAL ( decl ) == 0 || DECL_INITIAL ( decl ) == error_mark_node ) ) { if ( TREE_PUBLIC ( decl ) && DECL_NAME ( decl ) ) targetm . asm_out . globalize_label ( stream , name ) ; switch_to_section ( readonly_data_section ) ; ASM_OUTPUT_ALIGN ( stream , floor_log2 ( align / BITS_PER_UNIT ) ) ; mips_declare_object ( stream , name , "" , ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n" , size ) ; } else mips_declare_common_object ( stream , name , "\n\t.comm\t" , size , align , true ) ; } </s>

Implement ASM_OUTPUT_ALIGNED_DECL_COMMON . This is usually the same as the elfos.h version , but we also need to handle -muninit-const-in-rodata .


<s> static int mips_set_reg_reg_cost ( machine_mode mode ) { switch ( GET_MODE_CLASS ( mode ) ) { case MODE_CC : return mips_set_reg_reg_piece_cost ( mode , GET_MODE_SIZE ( CCmode ) ) ; case MODE_FLOAT : case MODE_COMPLEX_FLOAT : case MODE_VECTOR_FLOAT : if ( TARGET_HARD_FLOAT ) return mips_set_reg_reg_piece_cost ( mode , UNITS_PER_HWFPVALUE ) ; default : return mips_set_reg_reg_piece_cost ( mode , UNITS_PER_WORD ) ; } } </s>

Return the cost of moving between two registers of mode MODE .


<s> void SystemZXPLINKFrameLowering :: inlineStackProbe ( MachineFunction & MF , MachineBasicBlock & PrologMBB ) const { auto * ZII = static_cast < const SystemZInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; MachineInstr * StackAllocMI = nullptr ; for ( MachineInstr & MI : PrologMBB ) if ( MI . getOpcode ( ) == SystemZ :: XPLINK_STACKALLOC ) { StackAllocMI = & MI ; break ; } if ( StackAllocMI == nullptr ) return ; MachineBasicBlock & MBB = PrologMBB ; const DebugLoc DL = StackAllocMI -> getDebugLoc ( ) ; MachineBasicBlock * NextMBB ; MachineBasicBlock * StackExtMBB = MF . CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF . push_back ( StackExtMBB ) ; BuildMI ( StackExtMBB , DL , ZII -> get ( SystemZ :: LG ) , SystemZ :: R3D ) . addReg ( SystemZ :: R3D ) . addImm ( 72 ) . addReg ( 0 ) ; BuildMI ( StackExtMBB , DL , ZII -> get ( SystemZ :: CallBASR_STACKEXT ) ) . addReg ( SystemZ :: R3D ) ; BuildMI ( MBB , StackAllocMI , DL , ZII -> get ( SystemZ :: LLGT ) , SystemZ :: R3D ) . addReg ( 0 ) . addImm ( 1208 ) . addReg ( 0 ) ; BuildMI ( MBB , StackAllocMI , DL , ZII -> get ( SystemZ :: CG ) ) . addReg ( SystemZ :: R4D ) . addReg ( SystemZ :: R3D ) . addImm ( 64 ) . addReg ( 0 ) ; BuildMI ( MBB , StackAllocMI , DL , ZII -> get ( SystemZ :: BRC ) ) . addImm ( SystemZ :: CCMASK_ICMP ) . addImm ( SystemZ :: CCMASK_CMP_LT ) . addMBB ( StackExtMBB ) ; NextMBB = SystemZ :: splitBlockBefore ( StackAllocMI , & MBB ) ; MBB . addSuccessor ( NextMBB ) ; MBB . addSuccessor ( StackExtMBB ) ; BuildMI ( StackExtMBB , DL , ZII -> get ( SystemZ :: J ) ) . addMBB ( NextMBB ) ; StackExtMBB -> addSuccessor ( NextMBB ) ; StackAllocMI -> eraseFromParent ( ) ; recomputeLiveIns ( * NextMBB ) ; recomputeLiveIns ( * StackExtMBB ) ; } </s>

Replace a StackProbe inline-stub with the actual probe code inline .


<s> static bool rs6000_real_tls_symbol_ref_p ( rtx x ) { return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) >= TLS_MODEL_REAL ) ; } </s>

Return true if X is a symbol that refers to real ( rather than emulated ) TLS .


<s> SDNode * PPCDAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * TM . getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc dl ; if ( PPCLowering -> getPointerTy ( ) == MVT :: i32 ) { if ( PPCSubTarget -> isTargetELF ( ) ) GlobalBaseReg = PPC :: R30 ; else GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: GPRC_NOR0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; if ( PPCSubTarget -> isTargetELF ( ) ) { unsigned TempReg = RegInfo -> createVirtualRegister ( & PPC :: GPRCRegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: GetGBRO ) , TempReg ) . addReg ( GlobalBaseReg ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: UpdateGBR ) ) . addReg ( GlobalBaseReg ) . addReg ( TempReg ) ; MF -> getInfo < PPCFunctionInfo > ( ) -> setUsesPICBase ( true ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: G8RC_NOX0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR8 ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR8 ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , PPCLowering -> getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

PowerPC PPC PPC MVT::i32 PPC PPC::R30 PPC::GPRC_NOR0RegClass PPC::MovePCtoLR PPC::MFLR PPC PPC::GPRCRegClass PPC::GetGBRO PPC::UpdateGBR PPC PPC::G8RC_NOX0RegClass PPC::MovePCtoLR8 PPC::MFLR8 PPC


<s> bool AArch64InstrInfo :: isPTestLikeOpcode ( unsigned Opc ) const { return get ( Opc ) . TSFlags & AArch64 :: InstrFlagIsPTestLike ; } </s>

Returns true if the opcode is for an SVE instruction that sets the condition codes as if it 's results had been fed to a PTEST instruction along with the same general predicate .


"Can only put epilog before 'retl' instruction!"


<s>
static
MCSymbol
*
GetSymbolFromOperand
(
const
MachineOperand
&
MO
,
AsmPrinter
&
AP
)
{
const
TargetMachine
&
TM
=
AP
.
TM
;
Mangler
*
Mang
=
AP
.
Mang
;
const
DataLayout
&
DL
=
AP
.
getDataLayout
(
)
;
MCContext
&
Ctx
=
AP
.
OutContext
;
bool
isDarwin
=
TM
.
getTargetTriple
(
)
.
isOSDarwin
(
)
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
)
{
if
(
isDarwin
)
Suffix
=
"$stub"
;
}
else
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
Suffix
=
"$non_lazy_ptr"
;
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
.
getPrivateGlobalPrefix
(
)
;
unsigned
PrefixLen
=
Name
.
size
(
)
;
if
(
!
MO
.
isGlobal
(
)
)
{
assert
(
MO
.
isSymbol
(
)
&&
"Isn't a symbol reference"
)
;
Mangler
::
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
,
DL
)
;
}
else
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
TM
.
getNameWithPrefix
(
Name
,
GV
,
*
Mang
)
;
}
unsigned
OrigLen
=
Name
.
size
(
)
PrefixLen
;
Name
+=
Suffix
;
MCSymbol
*
Sym
=
Ctx
.
getOrCreateSymbol
(
Name
)
;
StringRef
OrigName
=
StringRef
(
Name
)
.
substr
(
PrefixLen
,
OrigLen
)
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
&&
isDarwin
)
{
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
getMachOMMI
(
AP
)
.
getFnStubEntry
(
Sym
)
;
if
(
StubSym
.
getPointer
(
)
)
return
Sym
;
if
(
MO
.
isGlobal
(
)
)
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
else
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
Ctx
.
getOrCreateSymbol
(
OrigName
)
,
false
)
;
}
return
Sym
;
}
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
{
MachineModuleInfoMachO
&
MachO
=
getMachOMMI
(
AP
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_HIDDEN_FLAG
)
MachO
.
getHiddenGVStubEntry
(
Sym
)
:
MachO
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
return
Sym
;
}
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


<s>
bool
AArch64CallLowering
::
lowerReturn
(
MachineIRBuilder
&
MIRBuilder
,
const
Value
*
Val
,
unsigned
VReg
)
const
{
MachineFunction
&
MF
=
MIRBuilder
.
getMF
(
)
;
const
Function
&
F
=
MF
.
getFunction
(
)
;
auto
MIB
=
MIRBuilder
.
buildInstrNoInsert
(
AArch64
::
RET_ReallyLR
)
;
assert
(
(
(
Val
&&
VReg
)
||
(
!
Val
&&
!
VReg
)
)
&&
"Return value without a vreg"
)
;
bool
Success
=
true
;
if
(
VReg
)
{
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
if
(
MRI
.
getType
(
VReg
)
.
getSizeInBits
(
)
==
1
)
VReg
=
MIRBuilder
.
buildZExt
(
LLT
::
scalar
(
8
)
,
VReg
)
->
getOperand
(
0
)
.
getReg
(
)
;
const
AArch64TargetLowering
&
TLI
=
*
getTLI
<
AArch64TargetLowering
>
(
)
;
CCAssignFn
*
AssignFn
=
TLI
.
CCAssignFnForReturn
(
F
.
getCallingConv
(
)
)
;
auto
&
DL
=
F
.
getParent
(
)
->
getDataLayout
(
)
;
ArgInfo
OrigArg
{
VReg
,
Val
->
getType
(
)
}
;
setArgFlags
(
OrigArg
,
AttributeList
::
ReturnIndex
,
DL
,
F
)
;
SmallVector
<
ArgInfo
,
8
>
SplitArgs
;
splitToValueTypes
(
OrigArg
,
SplitArgs
,
DL
,
MRI
,
F
.
getCallingConv
(
)
,
[
&
]
(
unsigned
Reg
,
uint64_t
Offset
)
{
MIRBuilder
.
buildExtract
(
Reg
,
VReg
,
Offset
)
;
}
)
;
OutgoingArgHandler
Handler
(
MIRBuilder
,
MRI
,
MIB
,
AssignFn
,
AssignFn
)
;
Success
=
handleAssignments
(
MIRBuilder
,
SplitArgs
,
Handler
)
;
}
MIRBuilder
.
insertInstr
(
MIB
)
;
return
Success
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> static int getMemScale ( const MachineInstr & MI ) { return getMemScale ( MI . getOpcode ( ) ) ; } </s>

Scaling factor for ( scaled or unscaled ) load or store .


<s> BitVector Cpu0RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t ReservedCPURegs [ ] = { Cpu0 :: ZERO , Cpu0 :: AT , Cpu0 :: SP , Cpu0 :: LR , Cpu0 :: PC } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: iterator RegIter ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) ) { Reserved . set ( Cpu0 :: FP ) ; } const Cpu0FunctionInfo * Cpu0FI = MF . getInfo < Cpu0FunctionInfo > ( ) ; if ( Cpu0FI -> globalBaseRegFixed ( ) ) Reserved . set ( Cpu0 :: GP ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static void s390_reg_clobbered_rtx ( rtx setreg , const_rtx set_insn ATTRIBUTE_UNUSED , void * data ) { char * regs_ever_clobbered = ( char * ) data ; unsigned int i , regno ; machine_mode mode = GET_MODE ( setreg ) ; if ( GET_CODE ( setreg ) == SUBREG ) { rtx inner = SUBREG_REG ( setreg ) ; if ( ! GENERAL_REG_P ( inner ) && ! FP_REG_P ( inner ) ) return ; regno = subreg_regno ( setreg ) ; } else if ( GENERAL_REG_P ( setreg ) || FP_REG_P ( setreg ) ) regno = REGNO ( setreg ) ; else return ; for ( i = regno ; i < regno + HARD_REGNO_NREGS ( regno , mode ) ; i ++ ) regs_ever_clobbered [ i ] = 1 ; } </s>

Helper function for s390_regs_ever_clobbered . Sets the fields in DATA for all clobbered hard regs in SETREG .


<s> tree memory_scalar_type ( const function_instance & fi ) const override { return fi . scalar_type ( 0 ) ; } </s>

If the function addresses memory , return the type of a single scalar memory element .


<s> unsigned SIInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const MCInstrDesc & Desc = getMCOpcodeFromPseudo ( Opc ) ; unsigned DescSize = Desc . getSize ( ) ; if ( isFixedSize ( MI ) ) { unsigned Size = DescSize ; if ( MI . isBranch ( ) && ST . hasOffset3fBug ( ) ) Size += 4 ; return Size ; } if ( isVALU ( MI ) || isSALU ( MI ) ) { if ( isDPP ( MI ) ) return DescSize ; bool HasLiteral = false ; for ( int I = 0 , E = MI . getNumExplicitOperands ( ) ; I != E ; ++ I ) { if ( isLiteralConstant ( MI , I ) ) { HasLiteral = true ; break ; } } return HasLiteral ? DescSize + 4 : DescSize ; } if ( isMIMG ( MI ) ) { int VAddr0Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: vaddr0 ) ; if ( VAddr0Idx < 0 ) return 8 ; int RSrcIdx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: srsrc ) ; return 8 + 4 * ( ( RSrcIdx - VAddr0Idx + 2 ) / 4 ) ; } switch ( Opc ) { case TargetOpcode :: BUNDLE : return getInstBundleSize ( MI ) ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) , & ST ) ; } default : if ( MI . isMetaInstruction ( ) ) return 0 ; return DescSize ; } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> rtx ix86_expand_adjust_ufix_to_sfix_si ( rtx val , rtx * xorp ) { REAL_VALUE_TYPE TWO31r ; rtx two31r , tmp [ 4 ] ; machine_mode mode = GET_MODE ( val ) ; machine_mode scalarmode = GET_MODE_INNER ( mode ) ; machine_mode intmode = GET_MODE_SIZE ( mode ) == 32 ? V8SImode : V4SImode ; rtx ( * cmp ) ( rtx , rtx , rtx , rtx ) ; int i ; for ( i = 0 ; i < 3 ; i ++ ) tmp [ i ] = gen_reg_rtx ( mode ) ; real_ldexp ( & TWO31r , & dconst1 , 31 ) ; two31r = const_double_from_real_value ( TWO31r , scalarmode ) ; two31r = ix86_build_const_vector ( mode , 1 , two31r ) ; two31r = force_reg ( mode , two31r ) ; switch ( mode ) { case E_V8SFmode : cmp = gen_avx_maskcmpv8sf3 ; break ; case E_V4SFmode : cmp = gen_sse_maskcmpv4sf3 ; break ; case E_V4DFmode : cmp = gen_avx_maskcmpv4df3 ; break ; case E_V2DFmode : cmp = gen_sse2_maskcmpv2df3 ; break ; default : gcc_unreachable ( ) ; } tmp [ 3 ] = gen_rtx_LE ( mode , two31r , val ) ; emit_insn ( cmp ( tmp [ 0 ] , two31r , val , tmp [ 3 ] ) ) ; tmp [ 1 ] = expand_simple_binop ( mode , AND , tmp [ 0 ] , two31r , tmp [ 1 ] , 0 , OPTAB_DIRECT ) ; if ( intmode == V4SImode || TARGET_AVX2 ) * xorp = expand_simple_binop ( intmode , ASHIFT , gen_lowpart ( intmode , tmp [ 0 ] ) , GEN_INT ( 31 ) , NULL_RTX , 0 , OPTAB_DIRECT ) ; else { rtx two31 = gen_int_mode ( HOST_WIDE_INT_1U << 31 , SImode ) ; two31 = ix86_build_const_vector ( intmode , 1 , two31 ) ; * xorp = expand_simple_binop ( intmode , AND , gen_lowpart ( intmode , tmp [ 0 ] ) , two31 , NULL_RTX , 0 , OPTAB_DIRECT ) ; } return expand_simple_binop ( mode , MINUS , val , tmp [ 1 ] , tmp [ 2 ] , 0 , OPTAB_DIRECT ) ; } </s>

Adjust a V * SFmode/V * DFmode value VAL so that * sfix_trunc * resp . fix_trunc * pattern can be used on it instead of fixuns_trunc * . This is done by doing just signed conversion if < 0x1p31 , and otherwise by subtracting 0x1p31 first and xoring in 0x80000000 from * XORP afterwards .


<s> void M88kMCInstLower :: lower ( const MachineInstr * MI , MCInst & OutMI ) const { OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( unsigned I = 0 , E = MI -> getNumOperands ( ) ; I != E ; ++ I ) { const MachineOperand & MO = MI -> getOperand ( I ) ; if ( ( ! MO . isReg ( ) || ! MO . isImplicit ( ) ) && ! MO . isRegMask ( ) ) OutMI . addOperand ( lowerOperand ( MO ) ) ; } } </s>


<s> static const char * gen_prefix ( tree decl ) { if ( DECL_ONE_ONLY ( decl ) ) return NULL ; if ( has_attr ( "section" , decl ) ) return NULL ; if ( has_section_name ( ".lowtext" , decl ) ) return NULL ; if ( ! TARGET_LARGE ) return NULL ; if ( has_attr ( ATTR_LOWER , decl ) ) return lower_prefix ; if ( has_attr ( ATTR_UPPER , decl ) ) return upper_prefix ; if ( has_attr ( ATTR_EITHER , decl ) ) return either_prefix ; if ( TREE_CODE ( decl ) == FUNCTION_DECL ) { if ( ( msp430_code_region == MSP430_REGION_LOWER ) && TARGET_USE_LOWER_REGION_PREFIX ) return lower_prefix ; if ( msp430_code_region == MSP430_REGION_UPPER ) return upper_prefix ; if ( msp430_code_region == MSP430_REGION_EITHER ) return either_prefix ; } else { if ( ( msp430_data_region == MSP430_REGION_LOWER ) && TARGET_USE_LOWER_REGION_PREFIX ) return lower_prefix ; if ( msp430_data_region == MSP430_REGION_UPPER ) return upper_prefix ; if ( msp430_data_region == MSP430_REGION_EITHER ) return either_prefix ; } return NULL ; } </s>

Generate a prefix for a section name , based upon the region into which the object should be placed .


<s> bool isFPImm ( ) const { return Kind == k_FPImm ; } </s>

isFPImm - Tests if this is a MO_FPImmediate operand .


<s>
unsigned
LanaiInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
Instruction
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
Instruction
!=
MBB
.
begin
(
)
)
{
Instruction
;
if
(
Instruction
->
isDebugInstr
(
)
)
continue
;
if
(
Instruction
->
getOpcode
(
)
!=
Lanai
::
BT
&&
Instruction
->
getOpcode
(
)
!=
Lanai
::
BRCC
)
{
break
;
}
Instruction
->
eraseFromParent
(
)
;
Instruction
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .

Lanai
Lanai
"code size not handled"
0
Lanai::BT
Lanai::BRCC


<s> static unsigned int aarch64_in_loop_reduction_latency ( vec_info * vinfo , stmt_vec_info stmt_info , tree vectype , unsigned int vec_flags ) { const cpu_vector_cost * vec_costs = aarch64_tune_params . vec_costs ; const sve_vec_cost * sve_costs = nullptr ; if ( vec_flags & VEC_ANY_SVE ) sve_costs = aarch64_tune_params . vec_costs -> sve ; if ( sve_costs ) { unsigned int latency = aarch64_sve_in_loop_reduction_latency ( vinfo , stmt_info , vectype , sve_costs ) ; if ( latency ) return latency ; } if ( vec_flags == 0 ) { if ( FLOAT_TYPE_P ( vectype ) ) return vec_costs -> scalar_fp_stmt_cost ; return vec_costs -> scalar_int_stmt_cost ; } const simd_vec_cost * simd_costs = aarch64_simd_vec_costs_for_flags ( vec_flags ) ; if ( FLOAT_TYPE_P ( vectype ) ) return simd_costs -> fp_stmt_cost ; return simd_costs -> int_stmt_cost ; } </s>

STMT_INFO describes a loop-carried operation in the original scalar code that we are considering implementing as a reduction . Return one of the following values , depending on VEC_FLAGS : - If VEC_FLAGS is zero , return the loop carry latency of the original scalar operation . - If VEC_FLAGS & VEC_ADVSIMD , return the loop carry latency of the the Advanced SIMD implementation . - If VEC_FLAGS & VEC_ANY_SVE , return the loop carry latency of the SVE implementation . VECTYPE is the type of vector that the vectorizer is considering using for STMT_INFO , which might be different from the type of vector described by VEC_FLAGS .


<s> bool SITargetLowering :: isFMADLegal ( const SelectionDAG & DAG , const SDNode * N ) const { EVT VT = N -> getValueType ( 0 ) ; if ( VT == MVT :: f32 ) return Subtarget -> hasMadMacF32Insts ( ) && ! hasFP32Denormals ( DAG . getMachineFunction ( ) ) ; if ( VT == MVT :: f16 ) { return Subtarget -> hasMadF16 ( ) && ! hasFP64FP16Denormals ( DAG . getMachineFunction ( ) ) ; } return false ; } </s>

Returns true if MI can be combined with another instruction to form TargetOpcode : :G_FMAD .


<s> rtx msp430_subreg ( machine_mode mode , rtx r , machine_mode omode , int byte ) { rtx rv ; if ( GET_CODE ( r ) == SUBREG && SUBREG_BYTE ( r ) == 0 ) { rtx ireg = SUBREG_REG ( r ) ; machine_mode imode = GET_MODE ( ireg ) ; if ( imode == PSImode && mode == HImode && byte == 0 ) rv = gen_rtx_SUBREG ( mode , ireg , byte ) ; else rv = simplify_gen_subreg ( mode , ireg , imode , byte ) ; } else if ( GET_CODE ( r ) == MEM ) rv = adjust_address ( r , mode , byte ) ; else rv = simplify_gen_subreg ( mode , r , omode , byte ) ; if ( ! rv ) gcc_unreachable ( ) ; return rv ; } </s>

Simplify_gen_subreg ( ) does n't handle memory references the way we need it to below , so we use this function for when we must get a valid subreg in a `` natural '' state .


<s> bool ARCTargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { return false ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> unsigned X86InstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { unsigned Dummy ; if ( isFrameLoadOpcode ( MI . getOpcode ( ) , Dummy ) ) { unsigned Reg ; if ( ( Reg = isLoadFromStackSlot ( MI , FrameIndex ) ) ) return Reg ; SmallVector < const MachineMemOperand * , 1 > Accesses ; if ( hasLoadFromStackSlot ( MI , Accesses ) ) { FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) -> getFrameIndex ( ) ; return 1 ; } } return 0 ; } </s>

isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s>
Register
getStackAddress
(
uint64_t
Size
,
int64_t
Offset
,
MachinePointerInfo
&
MPO
)
override
{
assert
(
(
Size
==
1
||
Size
==
2
||
Size
==
4
||
Size
==
8
)
&&
"Unsupported size"
)
;
auto
&
MFI
=
MIRBuilder
.
getMF
(
)
.
getFrameInfo
(
)
;
int
FI
=
MFI
.
CreateFixedObject
(
Size
,
Offset
,
true
)
;
MPO
=
MachinePointerInfo
::
getFixedStack
(
MIRBuilder
.
getMF
(
)
,
FI
)
;
Register
AddrReg
=
MRI
.
createGenericVirtualRegister
(
LLT
::
pointer
(
MPO
.
getAddrSpace
(
)
,
32
)
)
;
MIRBuilder
.
buildFrameIndex
(
AddrReg
,
FI
)
;
return
AddrReg
;
}
</s>

Materialize a VReg containing the address of the specified stack-based object .


<s> static bool x86_can_output_mi_thunk ( const_tree , HOST_WIDE_INT , HOST_WIDE_INT vcall_offset , const_tree function ) { if ( TARGET_64BIT ) return true ; if ( ix86_function_regparm ( TREE_TYPE ( function ) , function ) < 3 ) return true ; if ( vcall_offset ) return false ; if ( flag_pic && ! targetm . binds_local_p ( function ) ) return false ; return true ; } </s>

Determine whether x86_output_mi_thunk can succeed .


<s> static unsigned int cris_postdbr_cmpelim ( ) { rtx_insn * insn ; rtx_insn * next ; rtx_insn * prev_cc_setter = 0 ; rtx_insn * prev_cc_outer = 0 ; rtx dccr = gen_rtx_REG ( CCmode , CRIS_CC0_REGNUM ) ; for ( insn = get_insns ( ) ; insn ; insn = next ) { rtx_insn * outer_insn = insn ; rtx pat = PATTERN ( insn ) ; next = NEXT_INSN ( outer_insn ) ; if ( LABEL_P ( insn ) ) { prev_cc_setter = 0 ; continue ; } if ( ! NONDEBUG_INSN_P ( insn ) ) continue ; if ( GET_CODE ( pat ) == SEQUENCE ) insn = as_a < rtx_insn * > XVECEXP ( pat , 0 , 1 ) ; else if ( prev_cc_setter != 0 && GET_CODE ( pat ) == SET ) { rtx dest = SET_DEST ( pat ) ; rtx src = SET_SRC ( pat ) ; rtx prev_set ; if ( REG_P ( dest ) && REGNO ( dest ) == CRIS_CC0_REGNUM && GET_CODE ( src ) == COMPARE && REG_P ( XEXP ( src , 0 ) ) && XEXP ( src , 1 ) == const0_rtx && ( prev_set = single_set ( prev_cc_setter ) ) != 0 ) { rtx reg = XEXP ( src , 0 ) ; rtx prev_dest = SET_DEST ( prev_set ) ; rtx prev_src = SET_SRC ( prev_set ) ; bool src_same = rtx_equal_p ( prev_src , reg ) ; if ( REG_P ( prev_dest ) && ! reg_set_p ( reg , prev_src ) && ! reg_set_between_p ( reg , prev_cc_outer , outer_insn ) && ( src_same || rtx_equal_p ( prev_dest , reg ) ) ) { machine_mode ccmode = GET_MODE ( src ) ; rtx modeadjusted_dccr = ( ccmode == CCmode ? dccr : gen_rtx_REG ( CCmode , CRIS_CC0_REGNUM ) ) ; rtx compare = ( src_same ? pat : gen_rtx_SET ( modeadjusted_dccr , gen_rtx_COMPARE ( ccmode , copy_rtx ( prev_src ) , const0_rtx ) ) ) ; validate_change ( prev_cc_setter , & XVECEXP ( PATTERN ( prev_cc_setter ) , 0 , 0 ) , compare , true ) ; validate_change ( prev_cc_setter , & XVECEXP ( PATTERN ( prev_cc_setter ) , 0 , 1 ) , prev_set , true ) ; if ( apply_change_group ( ) ) { delete_insn ( insn ) ; prev_cc_setter = 0 ; continue ; } } } } if ( reg_set_p ( dccr , insn ) ) { rtx pat = PATTERN ( insn ) ; prev_cc_setter = 0 ; if ( GET_CODE ( pat ) == PARALLEL && XVECLEN ( pat , 0 ) == 2 && GET_CODE ( XVECEXP ( pat , 0 , 1 ) ) == CLOBBER ) { prev_cc_setter = insn ; prev_cc_outer = outer_insn ; } } } return 0 ; } </s>

`` Cheap version '' of cmpelim , making use of the opportunities opened up by reorg . Go through the insns of a function and look at each actual compare insn ; considering only those that compare a register to 0 . If the previous CC-affecting insn sets the compared register or if a move reads from it , try to change that into a CC-setting move and try to have it recognized . Bail at labels or non-matching insns that clobber the compared register . If successful , delete the compare . Also , reorg is n't up to date regarding data-flow handling , so we ca n't go beyond classic RTL scanning .


<s> void arc_ccfsm_record_branch_deleted ( void ) { ARC_CCFSM_RECORD_BRANCH_DELETED ( & arc_ccfsm_current ) ; } </s>

Record a branch is n't output because subsequent insns can be conditionalized .


<s> static int rs6000_hard_regno_nregs_internal ( int regno , machine_mode mode ) { unsigned HOST_WIDE_INT reg_size ; if ( FP_REGNO_P ( regno ) ) reg_size = ( VECTOR_MEM_VSX_P ( mode ) || VECTOR_ALIGNMENT_P ( mode ) ? UNITS_PER_VSX_WORD : UNITS_PER_FP_WORD ) ; else if ( ALTIVEC_REGNO_P ( regno ) ) reg_size = UNITS_PER_ALTIVEC_WORD ; else reg_size = UNITS_PER_WORD ; return ( GET_MODE_SIZE ( mode ) + reg_size - 1 ) / reg_size ; } </s>

Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE . This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers . POWER and PowerPC GPRs hold 32 bits worth ; PowerPC64 GPRs and FPRs point register holds 64 bits worth .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"X86 vzeroupper inserter"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void vax_notice_update_cc ( rtx exp , rtx insn ATTRIBUTE_UNUSED ) { if ( GET_CODE ( exp ) == SET ) { if ( GET_CODE ( SET_SRC ( exp ) ) == CALL ) CC_STATUS_INIT ; else if ( GET_CODE ( SET_DEST ( exp ) ) != ZERO_EXTRACT && GET_CODE ( SET_DEST ( exp ) ) != PC ) { cc_status . flags = 0 ; switch ( GET_CODE ( SET_SRC ( exp ) ) ) { case NEG : if ( GET_MODE_CLASS ( GET_MODE ( exp ) ) == MODE_FLOAT ) break ; case AND : case IOR : case XOR : case NOT : case MEM : case REG : cc_status . flags = CC_NO_OVERFLOW ; break ; default : break ; } cc_status . value1 = SET_DEST ( exp ) ; cc_status . value2 = SET_SRC ( exp ) ; } } else if ( GET_CODE ( exp ) == PARALLEL && GET_CODE ( XVECEXP ( exp , 0 , 0 ) ) == SET ) { if ( GET_CODE ( SET_SRC ( XVECEXP ( exp , 0 , 0 ) ) ) == CALL ) CC_STATUS_INIT ; else if ( GET_CODE ( SET_DEST ( XVECEXP ( exp , 0 , 0 ) ) ) != PC ) { cc_status . flags = 0 ; cc_status . value1 = SET_DEST ( XVECEXP ( exp , 0 , 0 ) ) ; cc_status . value2 = SET_SRC ( XVECEXP ( exp , 0 , 0 ) ) ; } else CC_STATUS_INIT ; } else CC_STATUS_INIT ; if ( cc_status . value1 && REG_P ( cc_status . value1 ) && cc_status . value2 && reg_overlap_mentioned_p ( cc_status . value1 , cc_status . value2 ) ) cc_status . value2 = 0 ; if ( cc_status . value1 && MEM_P ( cc_status . value1 ) && cc_status . value2 && MEM_P ( cc_status . value2 ) ) cc_status . value2 = 0 ; } </s>


<s> static bool nvptx_goacc_fork_join ( gcall * call , const int dims [ ] , bool ARG_UNUSED ( is_fork ) ) { tree arg = gimple_call_arg ( call , 2 ) ; unsigned axis = TREE_INT_CST_LOW ( arg ) ; if ( axis < GOMP_DIM_WORKER ) return false ; if ( dims [ axis ] == 1 ) return false ; return true ; } </s>

Determine whether fork & joins are needed .


"Disassembly not yet supported for subtarget"

Returns the disassembly of a single instruction .


<s> void BPFAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const { if ( Fixup . getKind ( ) == FK_SecRel_4 || Fixup . getKind ( ) == FK_SecRel_8 ) { assert ( Value <= UINT32_MAX ) ; support :: endian :: write < uint32_t > ( & Data [ Fixup . getOffset ( ) + 4 ] , static_cast < uint32_t > ( Value ) , Endian ) ; } else if ( Fixup . getKind ( ) == FK_Data_4 ) { support :: endian :: write < uint32_t > ( & Data [ Fixup . getOffset ( ) ] , Value , Endian ) ; } else if ( Fixup . getKind ( ) == FK_Data_8 ) { support :: endian :: write < uint64_t > ( & Data [ Fixup . getOffset ( ) ] , Value , Endian ) ; } else if ( Fixup . getKind ( ) == FK_PCRel_4 ) { Value = ( uint32_t ) ( ( Value - 8 ) / 8 ) ; if ( Endian == support :: little ) { Data [ Fixup . getOffset ( ) + 1 ] = 0x10 ; support :: endian :: write32le ( & Data [ Fixup . getOffset ( ) + 4 ] , Value ) ; } else { Data [ Fixup . getOffset ( ) + 1 ] = 0x1 ; support :: endian :: write32be ( & Data [ Fixup . getOffset ( ) + 4 ] , Value ) ; } } else { assert ( Fixup . getKind ( ) == FK_PCRel_2 ) ; Value = ( uint16_t ) ( ( Value - 8 ) / 8 ) ; support :: endian :: write < uint16_t > ( & Data [ Fixup . getOffset ( ) + 2 ] , Value , Endian ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
READ_REGISTER
:
ExpandREAD_REGISTER
(
N
,
Results
,
DAG
)
;
break
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SREM
:
case
ISD
::
UREM
:
Res
=
LowerREM
(
N
,
DAG
)
;
break
;
case
ISD
::
READCYCLECOUNTER
:
ReplaceREADCYCLECOUNTER
(
N
,
Results
,
DAG
,
Subtarget
)
;
return
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

ARM
ARM
"Don't know how to custom expand this!"
ISD::READ_REGISTER
ISD::BITCAST
ISD::SRL
ISD::SRA
ISD::SREM
ISD::UREM
ISD::READCYCLECOUNTER


<s> unsigned ARMBaseRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { if ( hasFP ( MF ) ) return FramePtr ; return ARM :: SP ; } </s>


<s> static unsigned int riscv_dwarf_poly_indeterminate_value ( unsigned int i , unsigned int * factor , int * offset ) { gcc_assert ( i == 1 ) ; * factor = riscv_bytes_per_vector_chunk ; * offset = 1 ; return RISCV_DWARF_VLENB ; } </s>

Implement the TARGET_DWARF_POLY_INDETERMINATE_VALUE hook .


"Byval argument's alignment should be a multiple of"

Target-specific cleanup for formal ByVal parameters .


<s> static void core2i7_first_cycle_multipass_fini ( void * _data ) { ix86_first_cycle_multipass_data_t data = ( ix86_first_cycle_multipass_data_t ) _data ; if ( data -> ready_try_change ) { sbitmap_free ( data -> ready_try_change ) ; data -> ready_try_change = NULL ; data -> ready_try_change_size = 0 ; } } </s>


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineBlockFrequencyInfo > ( ) ; AU . addPreserved < MachineBlockFrequencyInfo > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < TargetLibraryInfoWrapperPass > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


"Slot for J register must be last in order to be found!"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s>
SDValue
LanaiTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
MUL
:
return
LowerMUL
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
case
ISD
::
SETCCE
:
return
LowerSETCCE
(
Op
,
DAG
)
;
case
ISD
::
SHL_PARTS
:
return
LowerSHL_PARTS
(
Op
,
DAG
)
;
case
ISD
::
SRL_PARTS
:
return
LowerSRL_PARTS
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

Lanai
Lanai
ISD::MUL
ISD::BR_CC
ISD::ConstantPool
ISD::GlobalAddress
ISD::BlockAddress
ISD::JumpTable
ISD::SELECT_CC
ISD::SETCC
ISD::SETCCE
ISD::SHL_PARTS
ISD::SRL_PARTS
ISD::VASTART
ISD::DYNAMIC_STACKALLOC
ISD::RETURNADDR
ISD::FRAMEADDR
"unimplemented operand"


<s>
const
char
*
ix86_output_call_insn
(
rtx_insn
*
insn
,
rtx
call_op
)
{
bool
direct_p
=
constant_call_address_operand
(
call_op
,
VOIDmode
)
;
bool
seh_nop_p
=
false
;
const
char
*
xasm
;
if
(
SIBLING_CALL_P
(
insn
)
)
{
if
(
direct_p
)
xasm
=
"%!jmp\t%P0"
;
else
if
(
TARGET_SEH
)
xasm
=
"%!rex.W jmp %A0"
;
else
xasm
=
"%!jmp\t%A0"
;
output_asm_insn
(
xasm
,
&
call_op
)
;
return
""
;
}
if
(
TARGET_SEH
)
{
rtx_insn
*
i
;
for
(
i
=
NEXT_INSN
(
insn
)
;
i
;
i
=
NEXT_INSN
(
i
)
)
{
if
(
INSN_P
(
i
)
)
break
;
if
(
NOTE_P
(
i
)
&&
NOTE_KIND
(
i
)
==
NOTE_INSN_EPILOGUE_BEG
&&
!
flag_non_call_exceptions
&&
!
can_throw_internal
(
insn
)
)
{
seh_nop_p
=
true
;
break
;
}
}
if
(
i
==
)
seh_nop_p
=
true
;
}
if
(
direct_p
)
xasm
=
"%!call\t%P0"
;
else
xasm
=
"%!call\t%A0"
;
output_asm_insn
(
xasm
,
&
call_op
)
;
if
(
seh_nop_p
)
return
"nop"
;
return
""
;
}
</s>

Output the assembly for a call instruction .


"\t%@ Function supports interworking.\n"

"\t%@ Fast Interrupt Service Routine.\n"

"\t%@ Naked Function: prologue and epilogue provided by programmer.\n"

"\t%@ Volatile: function does not return.\n"

"\t%@ Nested: function declared inside another function.\n"

"\t%@ args = %d, pretend = %d, frame = %wd\n"

"\t%@ frame_needed = %d, uses_anonymous_args = %d\n"

Place some comments into the assembler stream describing the current function .


<s> static const char * read_file ( FILE * stream , size_t * plen ) { size_t alloc = 16384 ; size_t base = 0 ; char * buffer ; if ( ! fseek ( stream , 0 , SEEK_END ) ) { long s = ftell ( stream ) ; if ( s >= 0 ) alloc = s + 100 ; fseek ( stream , 0 , SEEK_SET ) ; } buffer = XNEWVEC ( char , alloc ) ; for ( ; ; ) { size_t n = fread ( buffer + base , 1 , alloc - base - 1 , stream ) ; if ( ! n ) break ; base += n ; if ( base + 1 == alloc ) { alloc *= 2 ; buffer = XRESIZEVEC ( char , buffer , alloc ) ; } } buffer [ base ] = 0 ; * plen = base ; return buffer ; } </s>

Read the whole input file . It will be NUL terminated ( but remember , there could be a NUL in the file itself .


<s>
void
MMIXAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
MCFixupKind
Kind
=
Fixup
.
getKind
(
)
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Kind
)
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
if
(
Kind
==
static_cast
<
MCFixupKind
>
(
MMIX
::
fixup_mmix_rel_16
)
||
Kind
==
static_cast
<
MCFixupKind
>
(
MMIX
::
fixup_mmix_rel_24
)
)
Data
[
Offset
]
&=
0xfe
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
Ctx
)
;
if
(
!
Value
)
return
;
Value
<<=
Info
.
TargetOffset
;
unsigned
NumBytes
=
(
Info
.
TargetSize
+
7
)
/
8
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
4
;
++
i
)
{
unsigned
Idx
=
3
i
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>


<s> SDValue DLXSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & , const SDLoc & , SDValue , SDValue , SDValue , SDValue Size , unsigned , bool , bool , MachinePointerInfo , MachinePointerInfo ) const { ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; if ( ! ConstantSize ) return SDValue ( ) ; return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .


<s> static rtx mips_function_value_1 ( const_tree valtype , const_tree fn_decl_or_type , machine_mode mode ) { if ( valtype ) { tree fields [ 2 ] ; int unsigned_p ; const_tree func ; if ( fn_decl_or_type && DECL_P ( fn_decl_or_type ) ) func = fn_decl_or_type ; else func = NULL ; mode = TYPE_MODE ( valtype ) ; unsigned_p = TYPE_UNSIGNED ( valtype ) ; mode = promote_function_mode ( valtype , mode , & unsigned_p , func , 1 ) ; switch ( mips_fpr_return_fields ( valtype , fields ) ) { case 1 : return mips_return_fpr_single ( mode , TYPE_MODE ( TREE_TYPE ( fields [ 0 ] ) ) ) ; case 2 : return mips_return_fpr_pair ( mode , TYPE_MODE ( TREE_TYPE ( fields [ 0 ] ) ) , int_byte_position ( fields [ 0 ] ) , TYPE_MODE ( TREE_TYPE ( fields [ 1 ] ) ) , int_byte_position ( fields [ 1 ] ) ) ; } if ( mips_return_in_msb ( valtype ) ) { HOST_WIDE_INT size = int_size_in_bytes ( valtype ) ; if ( size % UNITS_PER_WORD != 0 ) { size += UNITS_PER_WORD - size % UNITS_PER_WORD ; mode = mode_for_size ( size * BITS_PER_UNIT , MODE_INT , 0 ) ; } } if ( mips_abi != ABI_EABI && ! FLOAT_TYPE_P ( valtype ) ) return gen_rtx_REG ( mode , GP_RETURN ) ; } if ( ! TARGET_MIPS16 ) { if ( mode == TFmode ) return mips_return_fpr_pair ( mode , DImode , 0 , DImode , GET_MODE_SIZE ( mode ) / 2 ) ; if ( mips_return_mode_in_fpr_p ( mode ) ) { if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) return mips_return_fpr_pair ( mode , GET_MODE_INNER ( mode ) , 0 , GET_MODE_INNER ( mode ) , GET_MODE_SIZE ( mode ) / 2 ) ; else return gen_rtx_REG ( mode , FP_RETURN ) ; } } return gen_rtx_REG ( mode , GP_RETURN ) ; } </s>

Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE . For normal calls , VALTYPE is the return type and MODE is VOIDmode . For libcalls , VALTYPE is null and MODE is the mode of the return value .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < TargetPassConfig > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s>
void
arm_output_multireg_pop
(
rtx
*
operands
,
bool
return_pc
,
rtx
cond
,
bool
reverse
,
bool
update
)
{
int
i
;
char
pattern
[
100
]
;
int
offset
;
const
char
*
conditional
;
int
num_saves
=
XVECLEN
(
operands
[
0
]
,
0
)
;
unsigned
int
regno
;
unsigned
int
regno_base
=
REGNO
(
operands
[
1
]
)
;
bool
interrupt_p
=
IS_INTERRUPT
(
arm_current_func_type
(
)
)
;
offset
=
0
;
offset
+=
update
1
:
0
;
offset
+=
return_pc
1
:
0
;
for
(
i
=
offset
;
i
<
num_saves
;
i
++
)
{
regno
=
REGNO
(
XEXP
(
XVECEXP
(
operands
[
0
]
,
0
,
i
)
,
0
)
)
;
gcc_assert
(
(
regno
!=
SP_REGNUM
)
||
(
regno_base
==
SP_REGNUM
)
)
;
if
(
regno
==
regno_base
)
gcc_assert
(
!
update
)
;
}
conditional
=
reverse
"%?%D0"
:
"%?%d0"
;
if
(
(
regno_base
==
SP_REGNUM
)
&&
update
&&
!
(
interrupt_p
&&
return_pc
)
)
sprintf
(
pattern
,
"pop%s\t{"
,
conditional
)
;
else
{
if
(
regno_base
==
SP_REGNUM
)
sprintf
(
pattern
,
"ldmfd%s\t"
,
conditional
)
;
else
if
(
update
)
sprintf
(
pattern
,
"ldmia%s\t"
,
conditional
)
;
else
sprintf
(
pattern
,
"ldm%s\t"
,
conditional
)
;
strcat
(
pattern
,
reg_names
[
regno_base
]
)
;
if
(
update
)
strcat
(
pattern
,
"!, {"
)
;
else
strcat
(
pattern
,
", {"
)
;
}
strcat
(
pattern
,
reg_names
[
REGNO
(
XEXP
(
XVECEXP
(
operands
[
0
]
,
0
,
offset
)
,
0
)
)
]
)
;
for
(
i
=
offset
+
1
;
i
<
num_saves
;
i
++
)
{
strcat
(
pattern
,
", "
)
;
strcat
(
pattern
,
reg_names
[
REGNO
(
XEXP
(
XVECEXP
(
operands
[
0
]
,
0
,
i
)
,
0
)
)
]
)
;
}
strcat
(
pattern
,
"}"
)
;
if
(
interrupt_p
&&
return_pc
)
strcat
(
pattern
,
"^"
)
;
output_asm_insn
(
pattern
,
&
cond
)
;
}
</s>

OPERANDS [ 0 ] is the entire list of insns that constitute pop , OPERANDS [ 1 ] is the base register , RETURN_PC is true iff return insn is in the list , UPDATE is true iff the list contains explicit update of base register .


<s>
void
BT
::
run
(
)
{
reset
(
)
;
assert
(
FlowQ
.
empty
(
)
)
;
typedef
GraphTraits
<
const
MachineFunction
*
>
MachineFlowGraphTraits
;
const
MachineBasicBlock
*
Entry
=
MachineFlowGraphTraits
::
getEntryNode
(
&
MF
)
;
unsigned
MaxBN
=
0
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
assert
(
I
->
getNumber
(
)
>=
0
&&
"Disconnected block"
)
;
unsigned
BN
=
I
->
getNumber
(
)
;
if
(
BN
>
MaxBN
)
MaxBN
=
BN
;
}
BitVector
BlockScanned
(
MaxBN
+
1
)
;
int
EntryN
=
Entry
->
getNumber
(
)
;
FlowQ
.
push
(
CFGEdge
(
1
,
EntryN
)
)
;
while
(
!
FlowQ
.
empty
(
)
)
{
CFGEdge
Edge
=
FlowQ
.
front
(
)
;
FlowQ
.
pop
(
)
;
if
(
EdgeExec
.
count
(
Edge
)
)
continue
;
EdgeExec
.
insert
(
Edge
)
;
const
MachineBasicBlock
&
B
=
*
MF
.
getBlockNumbered
(
Edge
.
second
)
;
MachineBasicBlock
::
const_iterator
It
=
B
.
begin
(
)
,
End
=
B
.
end
(
)
;
while
(
It
!=
End
&&
It
->
isPHI
(
)
)
{
const
MachineInstr
*
PI
=
&
*
It
++
;
InstrExec
.
insert
(
PI
)
;
visitPHI
(
PI
)
;
}
if
(
BlockScanned
[
Edge
.
second
]
)
continue
;
BlockScanned
[
Edge
.
second
]
=
true
;
while
(
It
!=
End
&&
!
It
->
isBranch
(
)
)
{
const
MachineInstr
*
MI
=
&
*
It
++
;
InstrExec
.
insert
(
MI
)
;
visitNonBranch
(
MI
)
;
}
if
(
It
==
End
)
{
MachineFunction
::
const_iterator
BIt
=
B
.
getIterator
(
)
;
MachineFunction
::
const_iterator
Next
=
std
::
next
(
BIt
)
;
if
(
Next
!=
MF
.
end
(
)
&&
B
.
isSuccessor
(
&
*
Next
)
)
{
int
ThisN
=
B
.
getNumber
(
)
;
int
NextN
=
Next
->
getNumber
(
)
;
FlowQ
.
push
(
CFGEdge
(
ThisN
,
NextN
)
)
;
}
}
else
{
visitBranchesFrom
(
It
)
;
}
}
if
(
Trace
)
{
dbgs
(
)
<<
"Cells after propagation:\n"
;
for
(
CellMapType
::
iterator
I
=
Map
.
begin
(
)
,
E
=
Map
.
end
(
)
;
I
!=
E
;
++
I
)
dbgs
(
)
<<
PrintReg
(
I
->
first
,
&
ME
.
TRI
)
<<
" -> "
<<
I
->
second
<<
"\n"
;
}
}
</s>

Run the analysis pass over a function and produce a dominator tree .


"ReadCycleWrite is only to be used on riscv32"

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s>
TargetTransformInfo
::
PopcntSupportKind
SystemZTTIImpl
::
getPopcntSupport
(
unsigned
TyWidth
)
{
assert
(
isPowerOf2_32
(
TyWidth
)
&&
"Type width must be power of 2"
)
;
if
(
ST
->
hasPopulationCount
(
)
&&
TyWidth
<=
64
)
return
TTI
::
PSK_FastHardware
;
return
TTI
::
PSK_Software
;
}
</s>

Return hardware support for population count .

SystemZ
SystemZ
"Type width must be power of 2"
64


<s> StackOffset SparcFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const SparcSubtarget & Subtarget = MF . getSubtarget < SparcSubtarget > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const SparcRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; const SparcMachineFunctionInfo * FuncInfo = MF . getInfo < SparcMachineFunctionInfo > ( ) ; bool isFixed = MFI . isFixedObjectIndex ( FI ) ; bool UseFP ; if ( FuncInfo -> isLeafProc ( ) ) { UseFP = false ; } else if ( isFixed ) { UseFP = true ; } else if ( RegInfo -> needsStackRealignment ( MF ) ) { UseFP = false ; } else { UseFP = true ; } int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) + Subtarget . getStackPointerBias ( ) ; if ( UseFP ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return StackOffset :: getFixed ( FrameOffset ) ; } else { FrameReg = SP :: O6 ; return StackOffset :: getFixed ( FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ) ; } } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .

Sparc Sparc Sparc Sparc Sparc Sparc Sparc SP::O6


<s> unsigned AArch64InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case AArch64 :: STRWui : case AArch64 :: STRXui : case AArch64 :: STRBui : case AArch64 :: STRHui : case AArch64 :: STRSui : case AArch64 :: STRDui : case AArch64 :: STRQui : if ( MI . getOperand ( 0 ) . getSubReg ( ) == 0 && MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> const uint32_t * MINA32RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return nullptr ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> LoadInst * X86TargetLowering :: lowerIdempotentRMWIntoFencedLoad ( AtomicRMWInst * AI ) const { unsigned NativeWidth = Subtarget -> is64Bit ( ) ? 64 : 32 ; const Type * MemType = AI -> getType ( ) ; if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) return nullptr ; auto Builder = IRBuilder < > ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SynchScope = AI -> getSynchScope ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; auto Ptr = AI -> getPointerOperand ( ) ; if ( SynchScope == SingleThread ) { return nullptr ; } else if ( hasMFENCE ( * Subtarget ) ) { Function * MFence = llvm :: Intrinsic :: getDeclaration ( M , Intrinsic :: x86_sse2_mfence ) ; Builder . CreateCall ( MFence ) ; } else { return nullptr ; } LoadInst * Loaded = Builder . CreateAlignedLoad ( Ptr , AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ) ; Loaded -> setAtomic ( Order , SynchScope ) ; AI -> replaceAllUsesWith ( Loaded ) ; AI -> eraseFromParent ( ) ; return Loaded ; } </s>

On some platforms , an AtomicRMW that never actually modifies the value ( such as fetch_add of 0 ) can be turned into a fence followed by an atomic load .


<s> SDValue M68kTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_M68k ) ; for ( unsigned i = 0 , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; EVT CopyVT = VA . getLocVT ( ) ; Chain = DAG . getCopyFromReg ( Chain , DL , VA . getLocReg ( ) , CopyVT , InFlag ) . getValue ( 1 ) ; SDValue Val = Chain . getValue ( 0 ) ; if ( VA . isExtInLoc ( ) && VA . getValVT ( ) . getScalarType ( ) == MVT :: i1 ) Val = DAG . getNode ( ISD :: TRUNCATE , DL , VA . getValVT ( ) , Val ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Val ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> int PPCInstrInfo :: getOperandLatency ( const InstrItineraryData * ItinData , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * UseMI , unsigned UseIdx ) const { int Latency = PPCGenInstrInfo :: getOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ; const MachineOperand & DefMO = DefMI -> getOperand ( DefIdx ) ; unsigned Reg = DefMO . getReg ( ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; bool IsRegCR ; if ( TRI -> isVirtualRegister ( Reg ) ) { const MachineRegisterInfo * MRI = & DefMI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; IsRegCR = MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & PPC :: CRRCRegClass ) || MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & PPC :: CRBITRCRegClass ) ; } else { IsRegCR = PPC :: CRRCRegClass . contains ( Reg ) || PPC :: CRBITRCRegClass . contains ( Reg ) ; } if ( UseMI -> isBranch ( ) && IsRegCR ) { if ( Latency < 0 ) Latency = getInstrLatency ( ItinData , DefMI ) ; unsigned Directive = TM . getSubtarget < PPCSubtarget > ( ) . getDarwinDirective ( ) ; switch ( Directive ) { default : break ; case PPC :: DIR_7400 : case PPC :: DIR_750 : case PPC :: DIR_970 : case PPC :: DIR_E5500 : case PPC :: DIR_PWR4 : case PPC :: DIR_PWR5 : case PPC :: DIR_PWR5X : case PPC :: DIR_PWR6 : case PPC :: DIR_PWR6X : case PPC :: DIR_PWR7 : Latency += 2 ; break ; } } return Latency ; } </s>

Compute and return the use operand latency of a given pair of def and use .


<s> static rtx rs6000_load_constant_and_splat ( machine_mode mode , REAL_VALUE_TYPE dconst ) { rtx reg ; if ( mode == SFmode || mode == DFmode ) { rtx d = CONST_DOUBLE_FROM_REAL_VALUE ( dconst , mode ) ; reg = force_reg ( mode , d ) ; } else if ( mode == V4SFmode ) { rtx d = CONST_DOUBLE_FROM_REAL_VALUE ( dconst , SFmode ) ; rtvec v = gen_rtvec ( 4 , d , d , d , d ) ; reg = gen_reg_rtx ( mode ) ; rs6000_expand_vector_init ( reg , gen_rtx_PARALLEL ( mode , v ) ) ; } else if ( mode == V2DFmode ) { rtx d = CONST_DOUBLE_FROM_REAL_VALUE ( dconst , DFmode ) ; rtvec v = gen_rtvec ( 2 , d , d ) ; reg = gen_reg_rtx ( mode ) ; rs6000_expand_vector_init ( reg , gen_rtx_PARALLEL ( mode , v ) ) ; } else gcc_unreachable ( ) ; return reg ; } </s>

Load up a constant . If the mode is a vector mode , splat the value across all of the vector elements .


<s> tree riscv_builtin_decl ( unsigned int code , bool initialize_p ATTRIBUTE_UNUSED ) { unsigned int subcode = code >> RISCV_BUILTIN_SHIFT ; switch ( code & RISCV_BUILTIN_CLASS ) { case RISCV_BUILTIN_GENERAL : if ( subcode >= ARRAY_SIZE ( riscv_builtins ) ) return error_mark_node ; return riscv_builtin_decls [ subcode ] ; case RISCV_BUILTIN_VECTOR : return riscv_vector :: builtin_decl ( subcode , initialize_p ) ; } return error_mark_node ; } </s>


<s> bool AMDGPUAnnotateUniformValues :: doInitialization ( Module & M ) { AMDGPUASI = AMDGPU :: getAMDGPUAS ( M ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> bool PatmosAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; MCInst MCI ; MCInstLowering . Lower ( MI , MCI ) ; PatmosInstPrinter PIP ( * OutContext . getAsmInfo ( ) , * TM . getMCInstrInfo ( ) , * TM . getMCRegisterInfo ( ) ) ; PIP . printOperand ( & MCI , OpNo , OS ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> const DataLayout * getDataLayout ( ) const override { return getSubtargetImpl ( ) -> getDataLayout ( ) ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> bool HexagonBitSimplify :: runOnMachineFunction ( MachineFunction & MF ) { auto & HST = MF . getSubtarget < HexagonSubtarget > ( ) ; auto & HRI = * HST . getRegisterInfo ( ) ; auto & HII = * HST . getInstrInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool Changed ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) ; const HexagonEvaluator HE ( HRI , MRI , HII , MF ) ; BitTracker BT ( HE , MF ) ; DEBUG ( BT . trace ( true ) ) ; BT . run ( ) ; MachineBasicBlock & Entry = MF . front ( ) ; RegisterSet AIG ; ConstGeneration ImmG ( BT , HII , MRI ) ; Changed |= visitBlock ( Entry , ImmG , AIG ) ; RegisterSet ARE ; RedundantInstrElimination RIE ( BT , HII , MRI ) ; Changed |= visitBlock ( Entry , RIE , ARE ) ; RegisterSet ACG ; CopyGeneration CopyG ( BT , HII , MRI ) ; Changed |= visitBlock ( Entry , CopyG , ACG ) ; RegisterSet ACP ; CopyPropagation CopyP ( HRI , MRI ) ; Changed |= visitBlock ( Entry , CopyP , ACP ) ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) || Changed ; BT . run ( ) ; RegisterSet ABS ; BitSimplification BitS ( BT , HII , MRI ) ; Changed |= visitBlock ( Entry , BitS , ABS ) ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) || Changed ; if ( Changed ) { for ( auto & B : MF ) for ( auto & I : B ) I . clearKillInfo ( ) ; DeadCodeElimination ( MF , * MDT ) . run ( ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool mips_expand_ins_as_unaligned_store ( rtx dest , rtx src , HOST_WIDE_INT width , HOST_WIDE_INT bitpos ) { rtx left , right ; machine_mode mode ; if ( ! mips_get_unaligned_mem ( dest , width , bitpos , & left , & right ) ) return false ; mode = mode_for_size ( width , MODE_INT , 0 ) ; src = gen_lowpart ( mode , src ) ; if ( mode == DImode ) { emit_insn ( gen_mov_sdl ( dest , src , left ) ) ; emit_insn ( gen_mov_sdr ( copy_rtx ( dest ) , copy_rtx ( src ) , right ) ) ; } else { emit_insn ( gen_mov_swl ( dest , src , left ) ) ; emit_insn ( gen_mov_swr ( copy_rtx ( dest ) , copy_rtx ( src ) , right ) ) ; } return true ; } </s>

Try to use left/right stores to expand an `` ins '' pattern . DEST , WIDTH , BITPOS and SRC are the operands passed to the expander ; the operation is the equivalent of : ( set ( zero_extract DEST WIDTH BITPOS ) SRC ) Return true on success .


<s> static bool isConditionalBranch ( unsigned Opc ) { switch ( Opc ) { default : return false ; case AArch64 :: TBZW : case AArch64 :: TBNZW : case AArch64 :: TBZX : case AArch64 :: TBNZX : case AArch64 :: CBZW : case AArch64 :: CBNZW : case AArch64 :: CBZX : case AArch64 :: CBNZX : case AArch64 :: Bcc : return true ; } } </s>

Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block .


<s> static bool get_load_info ( rtx_insn * insn , struct loop * loop , rtx * dest , rtx * base , rtx * offset , bool * pre_post , bool * ldp ) { if ( ! INSN_P ( insn ) || recog_memoized ( insn ) < 0 ) return false ; rtx pat = PATTERN ( insn ) ; unsigned code = GET_CODE ( pat ) ; bool load_pair = ( code == PARALLEL ) ; if ( load_pair ) { pat = XVECEXP ( pat , 0 , 0 ) ; code = GET_CODE ( pat ) ; } if ( code != SET ) return false ; rtx dest_rtx = SET_DEST ( pat ) ; if ( ! REG_P ( dest_rtx ) ) return false ; unsigned regno = REGNO ( dest_rtx ) ; machine_mode mode = GET_MODE ( dest_rtx ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; if ( ! GET_MODE_SIZE ( mode ) . is_constant ( ) ) return false ; if ( GET_MODE_SIZE ( mode ) . to_constant ( ) != GET_MODE_SIZE ( inner_mode ) . to_constant ( ) ) return false ; if ( ( GET_MODE_SIZE ( mode ) . to_constant ( ) << load_pair ) > GET_MODE_SIZE ( OImode ) ) return false ; if ( regno == SP_REGNUM ) return false ; if ( valid_src_p ( SET_SRC ( pat ) , insn , loop , pre_post , base , offset , load_pair ) ) { * dest = dest_rtx ; * ldp = load_pair ; return true ; } return false ; } </s>

Return true if INSN is a strided load in LOOP . If it is a strided load , set the DEST , BASE and OFFSET . Also , if this is a pre/post increment load , set PRE_POST to true . The routine does checks on the destination of the insn and depends on STRIDED_LOAD_P to check the source and fill in the BASE and OFFSET .


<s> static void nvptx_asm_declare_constant_name ( FILE * file , const char * name , const_tree exp , HOST_WIDE_INT obj_size ) { write_var_marker ( file , true , false , name ) ; fprintf ( file , "\t" ) ; tree type = TREE_TYPE ( exp ) ; nvptx_assemble_decl_begin ( file , name , ".const" , type , obj_size , TYPE_ALIGN ( type ) ) ; } </s>

Implement TARGET_ASM_DECLARE_CONSTANT_NAME . Begin the process of writing a constant variable EXP with NAME and SIZE and its initializer to FILE .


<s> X86TargetLowering :: ConstraintType X86TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'R' : case 'q' : case 'Q' : case 'f' : case 't' : case 'u' : case 'y' : case 'x' : case 'v' : case 'Y' : case 'l' : case 'k' : return C_RegisterClass ; case 'a' : case 'b' : case 'c' : case 'd' : case 'S' : case 'D' : case 'A' : return C_Register ; case 'I' : case 'J' : case 'K' : case 'N' : case 'G' : case 'L' : case 'M' : return C_Immediate ; case 'C' : case 'e' : case 'Z' : return C_Other ; default : break ; } } else if ( Constraint . size ( ) == 2 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'Y' : switch ( Constraint [ 1 ] ) { default : break ; case 'z' : case '0' : return C_Register ; case 'i' : case 'm' : case 'k' : case 't' : case '2' : return C_RegisterClass ; } } } else if ( parseConstraintCode ( Constraint ) != X86 :: COND_INVALID ) return C_Other ; return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> void fma_forest :: merge_forest ( fma_forest * other_forest ) { std :: list < fma_root_node * > * other_roots ; std :: list < fma_root_node * > :: iterator other_root_iter ; if ( this == other_forest ) return ; other_roots = other_forest -> m_roots ; for ( other_root_iter = other_roots -> begin ( ) ; other_root_iter != other_roots -> end ( ) ; ++ other_root_iter ) ( * other_root_iter ) -> set_forest ( this ) ; this -> m_globals -> remove_forest ( other_forest ) ; this -> m_roots -> splice ( this -> m_roots -> begin ( ) , * other_roots ) ; this -> m_nb_nodes += other_forest -> m_nb_nodes ; delete other_forest ; } </s>

Merge REF_FOREST and OTHER_FOREST together , making REF_FOREST the canonical fma_forest object to represent both .


<s> void X86PassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86FixupSetCC ( ) ) ; addPass ( createX86OptimizeLEAs ( ) ) ; addPass ( createX86CallFrameOptimization ( ) ) ; } addPass ( createX86WinAllocaExpander ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> bool mips_split_64bit_move_p ( rtx dest , rtx src ) { if ( TARGET_64BIT ) return false ; if ( FP_REG_RTX_P ( src ) && FP_REG_RTX_P ( dest ) ) return false ; if ( mips_isa > 1 ) { if ( FP_REG_RTX_P ( dest ) && MEM_P ( src ) ) return false ; if ( FP_REG_RTX_P ( src ) && MEM_P ( dest ) ) return false ; } return true ; } </s>

Return true if a 64-bit move from SRC to DEST should be split into two .


<s> const KudeyarTargetMachine & getTargetMachine ( ) { return static_cast < const KudeyarTargetMachine & > ( TM ) ; } </s>

Return the target machine ( if available ) .


<s> static rtx tilegx_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( mode , 0 ) ; } </s>


<s> bool SIAnnotateControlFlow :: runOnFunction ( Function & F ) { DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; for ( df_iterator < BasicBlock * > I = df_begin ( & F . getEntryBlock ( ) ) , E = df_end ( & F . getEntryBlock ( ) ) ; I != E ; ++ I ) { BranchInst * Term = dyn_cast < BranchInst > ( ( * I ) -> getTerminator ( ) ) ; if ( ! Term || Term -> isUnconditional ( ) ) { if ( isTopOfStack ( * I ) ) closeControlFlow ( * I ) ; continue ; } if ( I . nodeVisited ( Term -> getSuccessor ( 1 ) ) ) { if ( isTopOfStack ( * I ) ) closeControlFlow ( * I ) ; handleLoop ( Term ) ; continue ; } if ( isTopOfStack ( * I ) ) { PHINode * Phi = dyn_cast < PHINode > ( Term -> getCondition ( ) ) ; if ( Phi && Phi -> getParent ( ) == * I && isElse ( Phi ) ) { insertElse ( Term ) ; eraseIfUnused ( Phi ) ; continue ; } closeControlFlow ( * I ) ; } openIf ( Term ) ; } assert ( Stack . empty ( ) ) ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool RISCVAsmBackend :: shouldInsertExtraNopBytesForCodeAlign ( const MCAlignFragment & AF , unsigned & Size ) { if ( ! STI . getFeatureBits ( ) [ RISCV :: FeatureRelax ] ) return false ; bool HasStdExtC = STI . getFeatureBits ( ) [ RISCV :: FeatureStdExtC ] ; unsigned MinNopLen = HasStdExtC ? 2 : 4 ; if ( AF . getAlignment ( ) <= MinNopLen ) { return false ; } else { Size = AF . getAlignment ( ) - MinNopLen ; return true ; } } </s>

Hook to check if extra nop bytes must be inserted for alignment directive .


<s> void emitBytes ( StringRef Data ) override { emitDataMappingSymbol ( ) ; MCELFStreamer :: emitBytes ( Data ) ; } </s>

Emit the bytes in Data into the output .


<s>
bool
HexagonExpandCondsets
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
*
MF
.
getFunction
(
)
)
)
return
false
;
HII
=
static_cast
<
const
HexagonInstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
LIS
=
&
getAnalysis
<
LiveIntervals
>
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
DEBUG
(
MF
.
print
(
dbgs
(
)
<<
"Before expand-condsets\n"
,
LIS
->
getSlotIndexes
(
)
)
)
;
bool
Changed
=
false
;
Changed
|=
coalesceSegments
(
MF
)
;
for
(
MachineFunction
::
iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
Changed
|=
splitInBlock
(
*
I
)
;
Changed
|=
predicateInBlock
(
*
I
)
;
}
for
(
MachineFunction
::
iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
postprocessUndefImplicitUses
(
*
I
)
;
if
(
Changed
)
DEBUG
(
MF
.
print
(
dbgs
(
)
<<
"After expand-condsets\n"
,
LIS
->
getSlotIndexes
(
)
)
)
;
return
Changed
;
}
</s>

Hexagon
Hexagon
Hexagon
"Before expand-condsets\n"
"After expand-condsets\n"


<s> unsigned MBlazeIntrinsicInfo :: lookupName ( const char * Name , unsigned Len ) const { return 0 ; } </s>


"initialized variable %q+D is marked dllimport"


"Unhandled type for 'r' inline asm constraint"

Given a physical register constraint ( e.g .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { TargetTransformInfo :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool HexagonEarlyIfConversion :: isValid ( const FlowPattern & FP ) const { if ( hasEHLabel ( FP . SplitB ) ) return false ; if ( FP . TrueB && ! isValidCandidate ( FP . TrueB ) ) return false ; if ( FP . FalseB && ! isValidCandidate ( FP . FalseB ) ) return false ; if ( FP . JoinB ) { const MachineBasicBlock & B = * FP . JoinB ; for ( auto & MI : B ) { if ( ! MI . isPHI ( ) ) break ; if ( usesUndefVReg ( & MI ) ) return false ; unsigned DefR = MI . getOperand ( 0 ) . getReg ( ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( DefR ) ; if ( RC == & Hexagon :: PredRegsRegClass ) return false ; } } return true ; } </s>

Returns true if this iterator is still pointing at a valid entry .

Hexagon Hexagon 0 Hexagon::PredRegsRegClass


<s> bool XCoreDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { SDValue Reg ; switch ( ConstraintID ) { default : return true ; case InlineAsm :: Constraint_m : switch ( Op . getOpcode ( ) ) { default : return true ; case XCoreISD :: CPRelativeWrapper : Reg = CurDAG -> getRegister ( XCore :: CP , MVT :: i32 ) ; break ; case XCoreISD :: DPRelativeWrapper : Reg = CurDAG -> getRegister ( XCore :: DP , MVT :: i32 ) ; break ; } } OutOps . push_back ( Reg ) ; OutOps . push_back ( Op . getOperand ( 0 ) ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .

XCore XCore XCoreISD::CPRelativeWrapper XCore::CP MVT::i32 XCoreISD::DPRelativeWrapper XCore::DP MVT::i32 0


<s> static void union_uses ( swap_web_entry * insn_entry , rtx insn , df_ref def ) { struct df_link * link = DF_REF_CHAIN ( def ) ; if ( ! link ) insn_entry [ INSN_UID ( insn ) ] . is_live_out = 1 ; while ( link ) { if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) insn_entry [ INSN_UID ( insn ) ] . is_live_out = 1 ; if ( DF_REF_INSN_INFO ( link -> ref ) ) { rtx use_insn = DF_REF_INSN ( link -> ref ) ; ( void ) unionfind_union ( insn_entry + INSN_UID ( insn ) , insn_entry + INSN_UID ( use_insn ) ) ; } link = link -> next ; } } </s>

Union INSN with all insns containing uses reached from DEF . Detect whether DEF is live-out from the current function .


Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> static rtx nds32_read_argument ( tree exp , unsigned int index ) { return expand_normal ( CALL_EXPR_ARG ( exp , index ) ) ; } </s>

Read the requested argument from the EXP given by INDEX . Return the value as an rtx .


<s>
StringRef
getPassName
(
)
const
override
{
return
"SystemZ Instruction Shortening"
;
}
</s>

getPassName - Return a nice clean name for a pass .

SystemZ
"SystemZ Instruction Shortening"


<s> static rtx arc_call_tls_get_addr ( rtx ti ) { rtx arg = gen_rtx_REG ( Pmode , R0_REG ) ; rtx ret = gen_rtx_REG ( Pmode , R0_REG ) ; rtx fn ; rtx_insn * insn ; if ( ! arc_tls_symbol ) arc_tls_symbol = init_one_libfunc ( "__tls_get_addr" ) ; emit_move_insn ( arg , ti ) ; fn = gen_rtx_MEM ( SImode , arc_tls_symbol ) ; insn = emit_call_insn ( gen_call_value ( ret , fn , const0_rtx ) ) ; RTL_CONST_CALL_P ( insn ) = 1 ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , ret ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , arg ) ; return ret ; } </s>

Emit a call to __tls_get_addr . TI is the argument to this function . RET is an RTX for the return value location . The entire insn sequence is returned .


<s> void AArch64PassConfig :: addPreEmitPass ( ) { if ( EnableA53Fix835769 ) addPass ( createAArch64A53Fix835769 ( ) ) ; addPass ( createAArch64BranchRelaxation ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; addPass ( createUnpackMachineBundles ( nullptr ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


"Found a PhiRef node as a real reached use!!"

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s> Align getAlign ( DataLayout const & DL , const GlobalVariable * GV ) { return DL . getValueOrABITypeAlignment ( GV -> getPointerAlignment ( DL ) , GV -> getValueType ( ) ) ; } </s>

Return the minimum known alignment in bytes of the actual memory reference .


<s> int xtensa_expand_block_move ( rtx * operands ) { static const machine_mode mode_from_align [ ] = { VOIDmode , QImode , HImode , VOIDmode , SImode , } ; rtx dst_mem = operands [ 0 ] ; rtx src_mem = operands [ 1 ] ; HOST_WIDE_INT bytes , align ; int num_pieces , move_ratio ; rtx temp [ 2 ] ; machine_mode mode [ 2 ] ; int amount [ 2 ] ; bool active [ 2 ] ; int phase = 0 ; int next ; int offset_ld = 0 ; int offset_st = 0 ; rtx x ; if ( ! optimize || ( GET_CODE ( operands [ 2 ] ) != CONST_INT ) ) return 0 ; bytes = INTVAL ( operands [ 2 ] ) ; align = INTVAL ( operands [ 3 ] ) ; if ( bytes <= 0 ) return 0 ; if ( align > MOVE_MAX ) align = MOVE_MAX ; move_ratio = 4 ; if ( optimize > 2 ) move_ratio = LARGEST_MOVE_RATIO ; num_pieces = ( bytes / align ) + ( bytes % align ) ; if ( num_pieces > move_ratio ) return 0 ; x = XEXP ( dst_mem , 0 ) ; if ( ! REG_P ( x ) ) { x = force_reg ( Pmode , x ) ; dst_mem = replace_equiv_address ( dst_mem , x ) ; } x = XEXP ( src_mem , 0 ) ; if ( ! REG_P ( x ) ) { x = force_reg ( Pmode , x ) ; src_mem = replace_equiv_address ( src_mem , x ) ; } active [ 0 ] = active [ 1 ] = false ; do { next = phase ; phase ^= 1 ; if ( bytes > 0 ) { int next_amount ; next_amount = ( bytes >= 4 ? 4 : ( bytes >= 2 ? 2 : 1 ) ) ; next_amount = MIN ( next_amount , align ) ; amount [ next ] = next_amount ; mode [ next ] = mode_from_align [ next_amount ] ; temp [ next ] = gen_reg_rtx ( mode [ next ] ) ; x = adjust_address ( src_mem , mode [ next ] , offset_ld ) ; emit_insn ( gen_rtx_SET ( VOIDmode , temp [ next ] , x ) ) ; offset_ld += next_amount ; bytes -= next_amount ; active [ next ] = true ; } if ( active [ phase ] ) { active [ phase ] = false ; x = adjust_address ( dst_mem , mode [ phase ] , offset_st ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x , temp [ phase ] ) ) ; offset_st += amount [ phase ] ; } } while ( active [ next ] ) ; return 1 ; } </s>

Try to expand a block move operation to an RTL block move instruction . If not optimizing or if the block size is not a constant or if the block is small , the expansion fails and GCC falls back to calling memcpy ( ) . operands [ 0 ] is the destination operands [ 1 ] is the source operands [ 2 ] is the length operands [ 3 ] is the alignment


<s> static int translate_unix ( char * name , int type ATTRIBUTE_UNUSED ) { strcpy ( filename_buff , name ) ; return 0 ; } </s>

Action routine called by decc $ to_vms . NAME is a file name or directory name . TYPE is unused .


"Instr doesn't have FrameIndex operand!"

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s>
SDValue
VETargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
getReturnCC
(
CallConv
)
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
OutVal
=
OutVals
[
i
]
;
switch
(
VA
.
getLocInfo
(
)
)
{
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
SExt
:
OutVal
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
DL
,
VA
.
getLocVT
(
)
,
OutVal
)
;
break
;
case
CCValAssign
::
ZExt
:
OutVal
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
DL
,
VA
.
getLocVT
(
)
,
OutVal
)
;
break
;
case
CCValAssign
::
AExt
:
OutVal
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
DL
,
VA
.
getLocVT
(
)
,
OutVal
)
;
break
;
case
CCValAssign
::
BCvt
:
{
assert
(
VA
.
getLocVT
(
)
==
MVT
::
i64
)
;
assert
(
VA
.
getValVT
(
)
==
MVT
::
f32
)
;
SDValue
Undef
=
SDValue
(
DAG
.
getMachineNode
(
TargetOpcode
::
IMPLICIT_DEF
,
DL
,
MVT
::
i64
)
,
0
)
;
SDValue
Sub_f32
=
DAG
.
getTargetConstant
(
VE
::
sub_f32
,
DL
,
MVT
::
i32
)
;
OutVal
=
SDValue
(
DAG
.
getMachineNode
(
TargetOpcode
::
INSERT_SUBREG
,
DL
,
MVT
::
i64
,
Undef
,
OutVal
,
Sub_f32
)
,
0
)
;
break
;
}
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
}
assert
(
!
VA
.
needsCustom
(
)
&&
"Unexpected custom lowering"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
OutVal
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
VEISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s>
TargetTransformInfo
::
PopcntSupportKind
WebAssemblyTTIImpl
::
getPopcntSupport
(
unsigned
TyWidth
)
const
{
assert
(
isPowerOf2_32
(
TyWidth
)
&&
"Ty width must be power of 2"
)
;
return
TargetTransformInfo
::
PSK_FastHardware
;
}
</s>

Return hardware support for population count .

WebAssembly
WebAssembly
"Ty width must be power of 2"


<s> static rtx single_set_and_flags ( rtx_insn * insn ) { if ( multiple_sets ( insn ) ) { rtx pat = PATTERN ( insn ) ; if ( XVECLEN ( pat , 0 ) == 2 && GET_CODE ( XVECEXP ( pat , 0 , 0 ) ) == SET && REG_P ( SET_DEST ( XVECEXP ( pat , 0 , 0 ) ) ) && REGNO ( SET_DEST ( XVECEXP ( pat , 0 , 0 ) ) ) == FLAGS_REGNUM ) return XVECEXP ( pat , 0 , 1 ) ; } return single_set ( insn ) ; } </s>

Wrapper around single_set which returns the first SET of a pair if the second SET is to the flags register .


<s> static inline int rs6000_secondary_reload_toc_costs ( addr_mask_type addr_mask ) { int ret ; if ( TARGET_CMODEL != CMODEL_SMALL ) ret = ( ( addr_mask & RELOAD_REG_OFFSET ) == 0 ) ? 1 : 2 ; else ret = ( TARGET_MINIMAL_TOC ) ? 6 : 3 ; return ret ; } </s>

Helper function to return the cost of adding a TOC entry address .


<s> static bool s390_return_in_memory ( const_tree type , const_tree fundecl ATTRIBUTE_UNUSED ) { if ( INTEGRAL_TYPE_P ( type ) || POINTER_TYPE_P ( type ) || TREE_CODE ( type ) == OFFSET_TYPE || TREE_CODE ( type ) == REAL_TYPE ) return int_size_in_bytes ( type ) > 8 ; if ( AGGREGATE_TYPE_P ( type ) || TREE_CODE ( type ) == COMPLEX_TYPE || TREE_CODE ( type ) == VECTOR_TYPE ) return true ; return true ; } </s>

Return true if return values of type TYPE should be returned in a memory buffer whose address is passed by the caller as hidden first argument .


<s> const AMDGPURegisterInfo * getRegisterInfo ( ) const override { return & getInstrInfo ( ) -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void SITargetLowering :: AdjustInstrPostInstrSelection ( MachineInstr & MI , SDNode * Node ) const { const SIInstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; if ( TII -> isVOP3 ( MI . getOpcode ( ) ) ) { TII -> legalizeOperandsVOP3 ( MRI , MI ) ; return ; } if ( TII -> isMIMG ( MI ) ) { unsigned VReg = MI . getOperand ( 0 ) . getReg ( ) ; const TargetRegisterClass * RC = MRI . getRegClass ( VReg ) ; if ( RC != & AMDGPU :: VReg_128RegClass ) return ; unsigned DmaskIdx = MI . getNumOperands ( ) == 12 ? 3 : 4 ; unsigned Writemask = MI . getOperand ( DmaskIdx ) . getImm ( ) ; unsigned BitsSet = 0 ; for ( unsigned i = 0 ; i < 4 ; ++ i ) BitsSet += Writemask & ( 1 << i ) ? 1 : 0 ; switch ( BitsSet ) { default : return ; case 1 : RC = & AMDGPU :: VGPR_32RegClass ; break ; case 2 : RC = & AMDGPU :: VReg_64RegClass ; break ; case 3 : RC = & AMDGPU :: VReg_96RegClass ; break ; } unsigned NewOpcode = TII -> getMaskedMIMGOp ( MI . getOpcode ( ) , BitsSet ) ; MI . setDesc ( TII -> get ( NewOpcode ) ) ; MRI . setRegClass ( VReg , RC ) ; return ; } int NoRetAtomicOp = AMDGPU :: getAtomicNoRetOp ( MI . getOpcode ( ) ) ; if ( NoRetAtomicOp != - 1 ) { if ( ! Node -> hasAnyUseOfValue ( 0 ) ) { MI . setDesc ( TII -> get ( NoRetAtomicOp ) ) ; MI . RemoveOperand ( 0 ) ; return ; } if ( ( Node -> hasNUsesOfValue ( 1 , 0 ) && Node -> use_begin ( ) -> isMachineOpcode ( ) && Node -> use_begin ( ) -> getMachineOpcode ( ) == AMDGPU :: EXTRACT_SUBREG && ! Node -> use_begin ( ) -> hasAnyUseOfValue ( 0 ) ) ) { unsigned Def = MI . getOperand ( 0 ) . getReg ( ) ; MI . setDesc ( TII -> get ( NoRetAtomicOp ) ) ; MI . RemoveOperand ( 0 ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , TII -> get ( AMDGPU :: IMPLICIT_DEF ) , Def ) ; } return ; } } </s>

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


<s> size_t ARMELFAttributeData :: emit ( char * pBuf ) const { char * buffer = pBuf ; const ELFAttributeValue & attr_conformance = m_Attrs [ Tag_conformance ] ; if ( attr_conformance . shouldEmit ( ) ) { if ( ! ELFAttributeData :: WriteAttribute ( Tag_conformance , attr_conformance , buffer ) ) { return 0 ; } } const ELFAttributeValue & attr_nodefaults = m_Attrs [ Tag_nodefaults ] ; if ( attr_nodefaults . shouldEmit ( ) ) { if ( ! ELFAttributeData :: WriteAttribute ( Tag_nodefaults , attr_nodefaults , buffer ) ) { return 0 ; } } for ( unsigned i = 0 ; i < Tag_nodefaults ; ++ i ) { TagType tag = static_cast < TagType > ( i ) ; const ELFAttributeValue & value = m_Attrs [ tag ] ; if ( value . shouldEmit ( ) && ! ELFAttributeData :: WriteAttribute ( tag , value , buffer ) ) { return 0 ; } } for ( unsigned i = ( Tag_nodefaults + 1 ) ; i <= Tag_Max ; ++ i ) { TagType tag = static_cast < TagType > ( i ) ; const ELFAttributeValue & value = m_Attrs [ tag ] ; if ( value . shouldEmit ( ) && ( i != Tag_conformance ) && ! ELFAttributeData :: WriteAttribute ( tag , value , buffer ) ) { return 0 ; } } for ( UnknownAttrsMap :: const_iterator unknown_attr_it = m_UnknownAttrs . begin ( ) , unknown_attr_end = m_UnknownAttrs . end ( ) ; unknown_attr_it != unknown_attr_end ; ++ unknown_attr_it ) { TagType tag = unknown_attr_it -> first ; const ELFAttributeValue & value = unknown_attr_it -> second ; if ( value . shouldEmit ( ) && ! ELFAttributeData :: WriteAttribute ( tag , value , buffer ) ) { return 0 ; } } return ( buffer - pBuf ) ; } </s>

Output the remark via the diagnostic handler and to the optimization record file .


<s>
static
bool
Check
(
DecodeStatus
&
Out
,
DecodeStatus
In
)
{
switch
(
In
)
{
case
MCDisassembler
::
Success
:
return
true
;
case
MCDisassembler
::
SoftFail
:
Out
=
In
;
return
true
;
case
MCDisassembler
::
Fail
:
Out
=
In
;
return
false
;
}
llvm_unreachable
(
"Invalid DecodeStatus!"
)
;
}
</s>

Matches check string and its `` not strings '' and/or `` dag strings '' .


<s> static rtx s390_function_and_libcall_value ( machine_mode mode , const_tree ret_type , const_tree fntype_or_decl , bool outgoing ATTRIBUTE_UNUSED ) { if ( ret_type ) { int unsignedp = TYPE_UNSIGNED ( ret_type ) ; mode = promote_function_mode ( ret_type , mode , & unsignedp , fntype_or_decl , 1 ) ; } gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_INT || SCALAR_FLOAT_MODE_P ( mode ) ) ; gcc_assert ( GET_MODE_SIZE ( mode ) <= 8 ) ; if ( TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P ( mode ) ) return gen_rtx_REG ( mode , 16 ) ; else if ( GET_MODE_SIZE ( mode ) <= UNITS_PER_LONG || UNITS_PER_LONG == UNITS_PER_WORD ) return gen_rtx_REG ( mode , 2 ) ; else if ( GET_MODE_SIZE ( mode ) == 2 * UNITS_PER_LONG ) { rtvec p = rtvec_alloc ( 2 ) ; RTVEC_ELT ( p , 0 ) = gen_rtx_EXPR_LIST ( SImode , gen_rtx_REG ( SImode , 2 ) , const0_rtx ) ; RTVEC_ELT ( p , 1 ) = gen_rtx_EXPR_LIST ( SImode , gen_rtx_REG ( SImode , 3 ) , GEN_INT ( 4 ) ) ; return gen_rtx_PARALLEL ( mode , p ) ; } gcc_unreachable ( ) ; } </s>

Define where to return a ( scalar ) value of type RET_TYPE . If RET_TYPE is null , define where to return a ( scalar ) value of mode MODE from a libcall .