<s> bool Error ( SMLoc L , const Twine & Msg , ArrayRef < SMRange > Ranges = None , bool MatchingInlineAsm = false ) { if ( MatchingInlineAsm ) return true ; return Parser . Error ( L , Msg , Ranges ) ; } </s>

Return an error at the location L , with the message Msg .


<s>
unsigned
LEGMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
{
return
CTX
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
}
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
assert
(
MO
.
isExpr
(
)
&&
"unknown operand kind in printOperand"
)
;
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
MCExpr
::
ExprKind
Kind
=
Expr
->
getKind
(
)
;
if
(
Kind
==
MCExpr
::
Binary
)
{
Expr
=
static_cast
<
const
MCBinaryExpr
*
>
(
Expr
)
->
getLHS
(
)
;
Kind
=
Expr
->
getKind
(
)
;
}
assert
(
Kind
==
MCExpr
::
SymbolRef
)
;
unsigned
FixupKind
;
switch
(
cast
<
MCSymbolRefExpr
>
(
Expr
)
->
getKind
(
)
)
{
default
:
llvm_unreachable
(
"Unknown fixup kind!"
)
;
case
MCSymbolRefExpr
::
VK_LEG_LO
:
{
FixupKind
=
LEG
::
fixup_leg_mov_lo16_pcrel
;
break
;
}
case
MCSymbolRefExpr
::
VK_LEG_HI
:
{
FixupKind
=
LEG
::
fixup_leg_mov_hi16_pcrel
;
break
;
}
}
Fixups
.
push_back
(
MCFixup
::
create
(
0
,
MO
.
getExpr
(
)
,
MCFixupKind
(
FixupKind
)
)
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


Return the DataLayout associated with the module this SCEV instance is operating on .


<s>
SDValue
X86TargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
unsigned
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
bool
Is64Bit
=
Subtarget
->
is64Bit
(
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_X86
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
CopyVT
=
VA
.
getValVT
(
)
;
if
(
(
CopyVT
==
MVT
::
f32
||
CopyVT
==
MVT
::
f64
)
&&
(
(
Is64Bit
||
Ins
[
i
]
.
Flags
.
isInReg
(
)
)
&&
!
Subtarget
->
hasSSE1
(
)
)
)
{
llvm_report_error
(
"SSE register return with SSE disabled"
)
;
}
if
(
(
VA
.
getLocReg
(
)
==
X86
::
ST0
||
VA
.
getLocReg
(
)
==
X86
::
ST1
)
&&
isScalarFPTypeInSSEReg
(
VA
.
getValVT
(
)
)
)
{
CopyVT
=
MVT
::
f80
;
}
SDValue
Val
;
if
(
Is64Bit
&&
CopyVT
.
isVector
(
)
&&
CopyVT
.
getSizeInBits
(
)
==
64
)
{
if
(
VA
.
getLocReg
(
)
==
X86
::
XMM0
||
VA
.
getLocReg
(
)
==
X86
::
XMM1
)
{
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
MVT
::
v2i64
,
InFlag
)
.
getValue
(
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
Val
=
DAG
.
getNode
(
ISD
::
EXTRACT_VECTOR_ELT
,
dl
,
MVT
::
i64
,
Val
,
DAG
.
getConstant
(
0
,
MVT
::
i64
)
)
;
}
else
{
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
MVT
::
i64
,
InFlag
)
.
getValue
(
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
}
Val
=
DAG
.
getNode
(
ISD
::
BIT_CONVERT
,
dl
,
CopyVT
,
Val
)
;
}
else
{
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
CopyVT
,
InFlag
)
.
getValue
(
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
}
InFlag
=
Chain
.
getValue
(
2
)
;
if
(
CopyVT
!=
VA
.
getValVT
(
)
)
{
Val
=
DAG
.
getNode
(
ISD
::
FP_ROUND
,
dl
,
VA
.
getValVT
(
)
,
Val
,
DAG
.
getIntPtrConstant
(
1
)
)
;
}
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static rtx or1k_adjust_atomic_subword ( rtx orig_mem , rtx * pshift , rtx * pmask ) { rtx addr , align , shift , mask , mem ; machine_mode mode = GET_MODE ( orig_mem ) ; addr = XEXP ( orig_mem , 0 ) ; addr = force_reg ( Pmode , addr ) ; align = expand_binop ( Pmode , and_optab , addr , GEN_INT ( - 4 ) , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; mem = gen_rtx_MEM ( SImode , align ) ; MEM_VOLATILE_P ( mem ) = MEM_VOLATILE_P ( orig_mem ) ; if ( MEM_ALIAS_SET ( orig_mem ) == ALIAS_SET_MEMORY_BARRIER ) set_mem_alias_set ( mem , ALIAS_SET_MEMORY_BARRIER ) ; rtx mode_mask = GEN_INT ( mode == QImode ? 3 : 2 ) ; shift = expand_binop ( SImode , and_optab , gen_lowpart ( SImode , addr ) , mode_mask , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; if ( BYTES_BIG_ENDIAN ) shift = expand_binop ( SImode , xor_optab , shift , mode_mask , shift , 1 , OPTAB_LIB_WIDEN ) ; shift = expand_binop ( SImode , ashl_optab , shift , GEN_INT ( 3 ) , shift , 1 , OPTAB_LIB_WIDEN ) ; * pshift = shift ; mask = expand_binop ( SImode , ashl_optab , GEN_INT ( GET_MODE_MASK ( mode ) ) , shift , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; * pmask = mask ; return mem ; } </s>

A subroutine of the various atomic expanders . For sub-word operations , we must adjust things to operate on SImode . Given the original MEM , return a new aligned memory . Also build and return the quantities by which to shift and mask .


<s> static bool v850_rtx_ok_for_base_p ( const_rtx x , bool strict_p ) { return ( ( REG_P ( x ) && v850_reg_ok_for_base_p ( x , strict_p ) ) || ( SUBREG_P ( x ) && REG_P ( SUBREG_REG ( x ) ) && v850_reg_ok_for_base_p ( SUBREG_REG ( x ) , strict_p ) ) ) ; } </s>

Accept either REG or SUBREG where a register is valid .


<s> int NVPTXFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; FrameReg = NVPTX :: VRDepot ; return MFI . getObjectOffset ( FI ) - getOffsetOfLocalArea ( ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> bool HexagonPassConfig :: addInstSelector ( ) { HexagonTargetMachine & TM = getHexagonTargetMachine ( ) ; bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) addPass ( createHexagonOptimizeSZextends ( ) ) ; addPass ( createHexagonISelDag ( TM , getOptLevel ( ) ) ) ; if ( ! NoOpt ) { if ( EnableVExtractOpt ) addPass ( createHexagonVExtract ( ) ) ; if ( EnableGenPred ) addPass ( createHexagonGenPredicate ( ) ) ; if ( EnableLoopResched ) addPass ( createHexagonLoopRescheduling ( ) ) ; if ( ! DisableHSDR ) addPass ( createHexagonSplitDoubleRegs ( ) ) ; if ( EnableBitSimplify ) addPass ( createHexagonBitSimplify ( ) ) ; addPass ( createHexagonPeephole ( ) ) ; if ( ! DisableHCP ) { addPass ( createHexagonConstPropagationPass ( ) ) ; addPass ( & UnreachableMachineBlockElimID ) ; } if ( EnableGenInsert ) addPass ( createHexagonGenInsert ( ) ) ; if ( EnableEarlyIf ) addPass ( createHexagonEarlyIfConversion ( ) ) ; } return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .

Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon


<s> void get_ppc476_thunk_name ( char name [ 32 ] ) { gcc_assert ( TARGET_LINK_STACK ) ; if ( USE_HIDDEN_LINKONCE ) sprintf ( name , "__ppc476.get_thunk" ) ; else ASM_GENERATE_INTERNAL_LABEL ( name , "LPPC476_" , 0 ) ; } </s>

Fills in the label name that should be used for a 476 link stack thunk .


<s> bool ARMTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , bool * Fast ) const { bool AllowsUnaligned = Subtarget -> allowsUnalignedMem ( ) ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : { if ( AllowsUnaligned ) { if ( Fast ) * Fast = Subtarget -> hasV7Ops ( ) ; return true ; } return false ; } case MVT :: f64 : case MVT :: v2f64 : { if ( Subtarget -> hasNEON ( ) && ( AllowsUnaligned || isLittleEndian ( ) ) ) { if ( Fast ) * Fast = true ; return true ; } return false ; } } } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> SDNode * SITargetLowering :: PostISelFolding ( MachineSDNode * Node , SelectionDAG & DAG ) const { const SIInstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; unsigned Opcode = Node -> getMachineOpcode ( ) ; if ( TII -> isMIMG ( Opcode ) && ! TII -> get ( Opcode ) . mayStore ( ) && ! TII -> isGather4 ( Opcode ) ) adjustWritemask ( Node , DAG ) ; if ( Opcode == AMDGPU :: INSERT_SUBREG || Opcode == AMDGPU :: REG_SEQUENCE ) { legalizeTargetIndependentNode ( Node , DAG ) ; return Node ; } switch ( Opcode ) { case AMDGPU :: V_DIV_SCALE_F32 : case AMDGPU :: V_DIV_SCALE_F64 : { SDValue Src0 = Node -> getOperand ( 0 ) ; SDValue Src1 = Node -> getOperand ( 1 ) ; SDValue Src2 = Node -> getOperand ( 2 ) ; if ( ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) != AMDGPU :: IMPLICIT_DEF ) && ( Src0 == Src1 || Src0 == Src2 ) ) break ; MVT VT = Src0 . getValueType ( ) . getSimpleVT ( ) ; const TargetRegisterClass * RC = getRegClassFor ( VT ) ; MachineRegisterInfo & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue UndefReg = DAG . getRegister ( MRI . createVirtualRegister ( RC ) , VT ) ; SDValue ImpDef = DAG . getCopyToReg ( DAG . getEntryNode ( ) , SDLoc ( Node ) , UndefReg , Src0 , SDValue ( ) ) ; if ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) == AMDGPU :: IMPLICIT_DEF ) { if ( Src1 . isMachineOpcode ( ) && Src1 . getMachineOpcode ( ) != AMDGPU :: IMPLICIT_DEF ) Src0 = Src1 ; else if ( Src2 . isMachineOpcode ( ) && Src2 . getMachineOpcode ( ) != AMDGPU :: IMPLICIT_DEF ) Src0 = Src2 ; else { assert ( Src1 . getMachineOpcode ( ) == AMDGPU :: IMPLICIT_DEF ) ; Src0 = UndefReg ; Src1 = UndefReg ; } } else break ; SmallVector < SDValue , 4 > Ops = { Src0 , Src1 , Src2 } ; for ( unsigned I = 3 , N = Node -> getNumOperands ( ) ; I != N ; ++ I ) Ops . push_back ( Node -> getOperand ( I ) ) ; Ops . push_back ( ImpDef . getValue ( 1 ) ) ; return DAG . getMachineNode ( Opcode , SDLoc ( Node ) , Node -> getVTList ( ) , Ops ) ; } default : break ; } return Node ; } </s>

Fold the instructions after selecting them .


"passing %qT to argument %d of %qE, which"

Require argument ARGNO to be some form of pointer , without being specific about its target type . Return true if the argument has the right form , otherwise report an appropriate error .


<s> const SpillSlot * getCalleeSavedSpillSlots ( unsigned & NumEntries ) const override { static const SpillSlot Offsets [ ] = { { Hexagon :: R17 , - 4 } , { Hexagon :: R16 , - 8 } , { Hexagon :: D8 , - 8 } , { Hexagon :: R19 , - 12 } , { Hexagon :: R18 , - 16 } , { Hexagon :: D9 , - 16 } , { Hexagon :: R21 , - 20 } , { Hexagon :: R20 , - 24 } , { Hexagon :: D10 , - 24 } , { Hexagon :: R23 , - 28 } , { Hexagon :: R22 , - 32 } , { Hexagon :: D11 , - 32 } , { Hexagon :: R25 , - 36 } , { Hexagon :: R24 , - 40 } , { Hexagon :: D12 , - 40 } , { Hexagon :: R27 , - 44 , { Hexagon :: R26 , - 48 , { Hexagon :: D13 , - 48 } } ; NumEntries = array_lengthof ( Offsets ) ; return Offsets ; } bool assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const override ; bool needsAligna ( const MachineFunction & MF ) const ; const MachineInstr * getAlignaInstr ( const MachineFunction & MF ) const ; void insertCFIInstructions ( MachineFunction & MF ) const ; private : typedef std :: vector < CalleeSavedInfo > CSIVect ; void expandAlloca ( MachineInstr * AI , const HexagonInstrInfo & TII , unsigned SP , unsigned CF ) const ; void insertPrologueInBlock ( MachineBasicBlock & MBB ) const ; void insertEpilogueInBlock ( MachineBasicBlock & MBB ) const ; bool insertCSRSpillsInBlock ( MachineBasicBlock & MBB , const CSIVect & CSI , const HexagonRegisterInfo & HRI ) const ; bool insertCSRRestoresInBlock ( MachineBasicBlock & MBB , const CSIVect & CSI , const HexagonRegisterInfo & HRI ) const ; void insertCFIInstructionsAt ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator At ) const ; void adjustForCalleeSavedRegsSpillCall ( MachineFunction & MF ) const ; bool replacePseudoRegTransferCode ( MachineFunction & MF ) const ; bool replaceVecPredRegPseudoSpillCode ( MachineFunction & MF ) const ; void findShrunkPrologEpilog ( MachineFunction & MF , MachineBasicBlock * & PrologB , MachineBasicBlock * & EpilogB ) const ; bool shouldInlineCSR ( llvm :: MachineFunction & MF , const CSIVect & CSI ) const ; bool useSpillFunction ( MachineFunction & MF , const CSIVect & CSI ) const ; bool useRestoreFunction ( MachineFunction & MF , const CSIVect & CSI ) const ; } </s>

getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs , that contains an entry for each callee saved register that must be spilled to a particular stack location if it is spilled .


<s> bool HexagonAsmParser :: parseExpression ( MCExpr const * & Expr ) { SmallVector < AsmToken , 4 > Tokens ; MCAsmLexer & Lexer = getLexer ( ) ; bool Done = false ; static char const * Comma = "," ; do { Tokens . emplace_back ( Lexer . getTok ( ) ) ; Lex ( ) ; switch ( Tokens . back ( ) . getKind ( ) ) { case AsmToken :: TokenKind :: Hash : if ( Tokens . size ( ) > 1 ) if ( ( Tokens . end ( ) - 2 ) -> getKind ( ) == AsmToken :: TokenKind :: Plus ) { Tokens . insert ( Tokens . end ( ) - 2 , AsmToken ( AsmToken :: TokenKind :: Comma , Comma ) ) ; Done = true ; } break ; case AsmToken :: TokenKind :: RCurly : case AsmToken :: TokenKind :: EndOfStatement : case AsmToken :: TokenKind :: Eof : Done = true ; break ; default : break ; } } while ( ! Done ) ; while ( ! Tokens . empty ( ) ) { Lexer . UnLex ( Tokens . back ( ) ) ; Tokens . pop_back ( ) ; } SMLoc Loc = Lexer . getLoc ( ) ; return getParser ( ) . parseExpression ( Expr , Loc ) ; } </s>


<s> static void s390_conditional_register_usage ( void ) { int i ; if ( flag_pic ) { fixed_regs [ PIC_OFFSET_TABLE_REGNUM ] = 1 ; call_used_regs [ PIC_OFFSET_TABLE_REGNUM ] = 1 ; } if ( TARGET_CPU_ZARCH ) { fixed_regs [ BASE_REGNUM ] = 0 ; call_used_regs [ BASE_REGNUM ] = 0 ; fixed_regs [ RETURN_REGNUM ] = 0 ; call_used_regs [ RETURN_REGNUM ] = 0 ; } if ( TARGET_64BIT ) { for ( i = FPR8_REGNUM ; i <= FPR15_REGNUM ; i ++ ) call_used_regs [ i ] = call_really_used_regs [ i ] = 0 ; } else { call_used_regs [ FPR4_REGNUM ] = call_really_used_regs [ FPR4_REGNUM ] = 0 ; call_used_regs [ FPR6_REGNUM ] = call_really_used_regs [ FPR6_REGNUM ] = 0 ; } if ( TARGET_SOFT_FLOAT ) { for ( i = FPR0_REGNUM ; i <= FPR15_REGNUM ; i ++ ) call_used_regs [ i ] = fixed_regs [ i ] = 1 ; } if ( ! TARGET_VX ) { for ( i = VR16_REGNUM ; i <= VR31_REGNUM ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = call_really_used_regs [ i ] = 1 ; } } </s>


<s> bool arm_legitimate_address_p ( machine_mode mode , rtx x , bool strict_p ) { if ( TARGET_ARM ) return arm_legitimate_address_outer_p ( mode , x , SET , strict_p ) ; else if ( TARGET_THUMB2 ) return thumb2_legitimate_address_p ( mode , x , strict_p ) ; else return thumb1_legitimate_address_p ( mode , x , strict_p ) ; } </s>

Return nonzero if X is a valid ARM state address operand .


<s> TargetPassConfig * CJGTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new CJGPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> static void s390_frame_area ( int * area_bottom , int * area_top ) { int b , t ; int i ; b = INT_MAX ; t = INT_MIN ; if ( cfun_frame_layout . first_restore_gpr != - 1 ) { b = ( cfun_frame_layout . gprs_offset + cfun_frame_layout . first_restore_gpr * UNITS_PER_WORD ) ; t = b + ( cfun_frame_layout . last_restore_gpr - cfun_frame_layout . first_restore_gpr + 1 ) * UNITS_PER_WORD ; } if ( TARGET_64BIT && cfun_save_high_fprs_p ) { b = MIN ( b , cfun_frame_layout . f8_offset ) ; t = MAX ( t , ( cfun_frame_layout . f8_offset + cfun_frame_layout . high_fprs * 8 ) ) ; } if ( ! TARGET_64BIT ) for ( i = 2 ; i < 4 ; i ++ ) if ( cfun_fpr_bit_p ( i ) ) { b = MIN ( b , cfun_frame_layout . f4_offset + ( i - 2 ) * 8 ) ; t = MAX ( t , cfun_frame_layout . f4_offset + ( i - 1 ) * 8 ) ; } * area_bottom = b ; * area_top = t ; } </s>

Determine the frame area which actually has to be accessed in the function epilogue . The values are stored at the given pointers AREA_BOTTOM ( address of the lowest used stack address ) and AREA_TOP ( address of the first item which does not belong to the stack frame ) .


<s> static bool ix86_expand_vec_shift_qihi_constant ( enum rtx_code code , rtx dest , rtx op1 , rtx op2 ) { machine_mode qimode , himode ; HOST_WIDE_INT and_constant , xor_constant ; HOST_WIDE_INT shift_amount ; rtx vec_const_and , vec_const_xor ; rtx tmp , op1_subreg ; rtx ( * gen_shift ) ( rtx , rtx , rtx ) ; rtx ( * gen_and ) ( rtx , rtx , rtx ) ; rtx ( * gen_xor ) ( rtx , rtx , rtx ) ; rtx ( * gen_sub ) ( rtx , rtx , rtx ) ; if ( ! CONST_INT_P ( op2 ) ) return false ; qimode = GET_MODE ( dest ) ; shift_amount = INTVAL ( op2 ) ; if ( shift_amount > 7 ) return false ; gcc_assert ( code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT ) ; xor_constant = 1 << ( 8 - shift_amount - 1 ) ; and_constant = ( code == ASHIFT ? 256 - ( 1 << shift_amount ) : ( 1 << ( 8 - shift_amount ) ) - 1 ) ; switch ( qimode ) { case V16QImode : himode = V8HImode ; gen_shift = ( ( code == ASHIFT ) ? gen_ashlv8hi3 : ( code == ASHIFTRT ) ? gen_ashrv8hi3 : gen_lshrv8hi3 ) ; gen_and = gen_andv16qi3 ; gen_xor = gen_xorv16qi3 ; gen_sub = gen_subv16qi3 ; break ; case V32QImode : himode = V16HImode ; gen_shift = ( ( code == ASHIFT ) ? gen_ashlv16hi3 : ( code == ASHIFTRT ) ? gen_ashrv16hi3 : gen_lshrv16hi3 ) ; gen_and = gen_andv32qi3 ; gen_xor = gen_xorv32qi3 ; gen_sub = gen_subv32qi3 ; break ; case V64QImode : himode = V32HImode ; gen_shift = ( ( code == ASHIFT ) ? gen_ashlv32hi3 : ( code == ASHIFTRT ) ? gen_ashrv32hi3 : gen_lshrv32hi3 ) ; gen_and = gen_andv64qi3 ; gen_xor = gen_xorv64qi3 ; gen_sub = gen_subv64qi3 ; break ; default : gcc_unreachable ( ) ; } tmp = gen_reg_rtx ( himode ) ; vec_const_and = gen_reg_rtx ( qimode ) ; op1_subreg = lowpart_subreg ( himode , op1 , qimode ) ; emit_insn ( gen_shift ( tmp , op1_subreg , op2 ) ) ; emit_move_insn ( dest , simplify_gen_subreg ( qimode , tmp , himode , 0 ) ) ; emit_move_insn ( vec_const_and , ix86_build_const_vector ( qimode , true , gen_int_mode ( and_constant , QImode ) ) ) ; emit_insn ( gen_and ( dest , dest , vec_const_and ) ) ; if ( code == ASHIFTRT ) { vec_const_xor = gen_reg_rtx ( qimode ) ; emit_move_insn ( vec_const_xor , ix86_build_const_vector ( qimode , true , gen_int_mode ( xor_constant , QImode ) ) ) ; emit_insn ( gen_xor ( dest , dest , vec_const_xor ) ) ; emit_insn ( gen_sub ( dest , dest , vec_const_xor ) ) ; } return true ; } </s>

Expand a vector operation shift by constant for a V * QImode in terms of the same operation on V * HImode . Return true if success .


<s> bool CSKYDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { switch ( ConstraintID ) { case InlineAsm :: Constraint_m : OutOps . push_back ( Op ) ; return false ; default : break ; } return true ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Hexagon bit simplification"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void AVRPassConfig :: addPreSched2 ( ) { } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> static rtx loongarch_frame_set ( rtx mem , rtx reg ) { rtx set = gen_rtx_SET ( mem , reg ) ; RTX_FRAME_RELATED_P ( set ) = 1 ; return set ; } </s>

Return a frame-related rtx that stores REG at MEM . REG must be a single register .


<s> bool AMDGPUAnnotateKernelFeatures :: runOnModule ( Module & M ) { Triple TT ( M . getTargetTriple ( ) ) ; static const StringRef IntrinsicToAttr [ ] [ 2 ] = { { "llvm.amdgcn.workitem.id.y" , "amdgpu-work-item-id-y" } , { "llvm.amdgcn.workitem.id.z" , "amdgpu-work-item-id-z" } , { "llvm.amdgcn.workgroup.id.y" , "amdgpu-work-group-id-y" } , { "llvm.amdgcn.workgroup.id.z" , "amdgpu-work-group-id-z" } , { "llvm.r600.read.tgid.y" , "amdgpu-work-group-id-y" } , { "llvm.r600.read.tgid.z" , "amdgpu-work-group-id-z" } , { "llvm.r600.read.tidig.y" , "amdgpu-work-item-id-y" } , { "llvm.r600.read.tidig.z" , "amdgpu-work-item-id-z" } } ; static const StringRef HSAIntrinsicToAttr [ ] [ 2 ] = { { "llvm.amdgcn.dispatch.ptr" , "amdgpu-dispatch-ptr" } , { "llvm.amdgcn.queue.ptr" , "amdgpu-queue-ptr" } , { "llvm.amdgcn.dispatch.id" , "amdgpu-dispatch-id" } } ; bool Changed = addAttrsForIntrinsics ( M , IntrinsicToAttr ) ; if ( TT . getOS ( ) == Triple :: AMDHSA || TT . getOS ( ) == Triple :: Mesa3D ) { Changed |= addAttrsForIntrinsics ( M , HSAIntrinsicToAttr ) ; for ( Function & F : M ) { if ( F . hasFnAttribute ( "amdgpu-queue-ptr" ) ) continue ; if ( hasAddrSpaceCast ( F ) ) F . addFnAttr ( "amdgpu-queue-ptr" ) ; } } return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> bool X86TargetMachine :: addInstSelector ( PassManagerBase & PM , bool Fast ) { PM . add ( createX86ISelDag ( * this , Fast ) ) ; if ( EnableFastISel ) PM . add ( createDeadMachineInstructionElimPass ( ) ) ; PM . add ( createX87FPRegKillInserterPass ( ) ) ; return false ; } </s>


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool is64bit ) : LLVMTargetMachine ( T , computeDataLayout ( TT , is64bit ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffectiveSparcCodeModel ( CM , getEffectiveRelocModel ( RM ) , is64bit , JIT ) , OL ) , TLOF ( std :: make_unique < SparcELFTargetObjectFile > ( ) ) , Subtarget ( TT , std :: string ( CPU ) , std :: string ( FS ) , * this , is64bit ) , is64Bit ( is64bit ) { initAsmInfo ( ) ; } </s>


<s> void tilegx_expand_umuldi3_highpart ( rtx op0 , rtx op1 , rtx op2 ) { tilegx_expand_high_multiply ( op0 , op1 , op2 , false ) ; } </s>


"\t1: movhi\tr3, %%hiadj(_gp_got - 1b)\n"


<s> const MSP430InstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> void RV16KPassConfig :: addPreEmitPass ( ) { addPass ( createRV16KUseLWSPSWSPPass ( ) ) ; addPass ( & BranchRelaxationPassID ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> ScheduleHazardRecognizer :: HazardType GCNHazardRecognizer :: getHazardType ( SUnit * SU , int Stalls ) { MachineInstr * MI = SU -> getInstr ( ) ; if ( SIInstrInfo :: isSMRD ( * MI ) && checkSMRDHazards ( MI ) > 0 ) return NoopHazard ; if ( SIInstrInfo :: isVMEM ( * MI ) && checkVMEMHazards ( MI ) > 0 ) return NoopHazard ; if ( SIInstrInfo :: isVALU ( * MI ) && checkVALUHazards ( MI ) > 0 ) return NoopHazard ; if ( SIInstrInfo :: isDPP ( * MI ) && checkDPPHazards ( MI ) > 0 ) return NoopHazard ; if ( isDivFMas ( MI -> getOpcode ( ) ) && checkDivFMasHazards ( MI ) > 0 ) return NoopHazard ; if ( isRWLane ( MI -> getOpcode ( ) ) && checkRWLaneHazards ( MI ) > 0 ) return NoopHazard ; if ( isSGetReg ( MI -> getOpcode ( ) ) && checkGetRegHazards ( MI ) > 0 ) return NoopHazard ; if ( isSSetReg ( MI -> getOpcode ( ) ) && checkSetRegHazards ( MI ) > 0 ) return NoopHazard ; if ( isRFE ( MI -> getOpcode ( ) ) && checkRFEHazards ( MI ) > 0 ) return NoopHazard ; if ( ( isVInterp ( MI -> getOpcode ( ) ) || isSMovRel ( MI -> getOpcode ( ) ) ) && checkReadM0Hazards ( MI ) > 0 ) return NoopHazard ; if ( checkAnyInstHazards ( MI ) > 0 ) return NoopHazard ; return NoHazard ; } </s>

getHazardType - Return the hazard type of emitting this node .


<s> rtx riscv_function_value ( const_tree type , const_tree func , machine_mode mode ) { struct riscv_arg_info info ; CUMULATIVE_ARGS args ; if ( type ) { int unsigned_p = TYPE_UNSIGNED ( type ) ; mode = TYPE_MODE ( type ) ; mode = promote_function_mode ( type , mode , & unsigned_p , func , 1 ) ; } memset ( & args , 0 , sizeof args ) ; return riscv_get_arg_info ( & info , & args , mode , type , true , true ) ; } </s>

Implement FUNCTION_VALUE and LIBCALL_VALUE . For normal calls , VALTYPE is the return type and MODE is VOIDmode . For libcalls , VALTYPE is null and MODE is the mode of the return value .


"Basic block should contain at least a RET but is empty"

runOnMachineFunction - Emit the function body .


<s> void m68hc11_notice_keep_cc ( rtx reg ) { if ( reg == 0 || cc_prev_status . value1 == 0 || rtx_equal_p ( reg , cc_prev_status . value1 ) || ( cc_prev_status . value2 && reg_mentioned_p ( reg , cc_prev_status . value2 ) ) ) CC_STATUS_INIT ; else cc_status = cc_prev_status ; } </s>

The current instruction does not affect the flags but changes the register 'reg ' . See if the previous flags can be kept for the next instruction to avoid a comparison .


<s> bool nds32_can_use_bset_p ( HOST_WIDE_INT ival ) { int one_bit_count ; unsigned HOST_WIDE_INT mask = GET_MODE_MASK ( SImode ) ; one_bit_count = popcount_hwi ( ( unsigned HOST_WIDE_INT ) ( ival ) & mask ) ; return ( TARGET_EXT_PERF && ( one_bit_count == 1 ) ) ; } </s>

Function to check if 'bset ' instruction can be used with IVAL .


"OR1K DAG->DAG Pattern Instruction Selection"


<s> static rtx avr_find_unused_d_reg ( rtx_insn * insn , rtx exclude ) { int regno ; bool isr_p = ( avr_interrupt_function_p ( current_function_decl ) || avr_signal_function_p ( current_function_decl ) ) ; for ( regno = 16 ; regno < 32 ; regno ++ ) { rtx reg = all_regs_rtx [ regno ] ; if ( ( exclude && reg_overlap_mentioned_p ( exclude , reg ) ) || fixed_regs [ regno ] ) { continue ; } if ( ! df_regs_ever_live_p ( regno ) && ( TREE_THIS_VOLATILE ( current_function_decl ) || cfun -> machine -> is_OS_task || cfun -> machine -> is_OS_main || ( ! isr_p && call_used_regs [ regno ] ) ) ) { return reg ; } if ( df_regs_ever_live_p ( regno ) && reg_unused_after ( insn , reg ) ) { return reg ; } } return NULL_RTX ; } </s>

Fixme : This is a hack because secondary reloads do n't works as expected . Find an unused d-register to be used as scratch in INSN . EXCLUDE is either NULL_RTX or some register . In the case where EXCLUDE is a register , skip all possible return values that overlap EXCLUDE . The policy for the returned register is similar to that of ` reg_unused_after ' , i.e . the returned register may overlap the SET_DEST of INSN . Return a QImode d-register or NULL_RTX if nothing found .


"Unrecognized Hexagon processor version"

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> static void frv_insert_nop_in_packet ( rtx insn ) { struct frv_packet_group * packet_group ; rtx last ; packet_group = & frv_packet . groups [ frv_unit_groups [ frv_insn_unit ( insn ) ] ] ; last = frv_packet . insns [ frv_packet . num_insns - 1 ] ; if ( GET_CODE ( last ) != INSN ) { insn = emit_insn_before ( PATTERN ( insn ) , last ) ; frv_packet . insns [ frv_packet . num_insns - 1 ] = insn ; frv_packet . insns [ frv_packet . num_insns ++ ] = last ; } else { insn = emit_insn_after ( PATTERN ( insn ) , last ) ; frv_packet . insns [ frv_packet . num_insns ++ ] = insn ; } packet_group -> insns [ packet_group -> num_insns ++ ] = insn ; } </s>

Insert INSN ( a member of frv_nops [ ] ) into the current packet . If the packet ends in a branch or call , insert the nop before it , otherwise add to the end .


<s> static void mips_block_move_straight ( rtx dest , rtx src , HOST_WIDE_INT length ) { HOST_WIDE_INT offset , delta ; unsigned HOST_WIDE_INT bits ; int i ; machine_mode mode ; rtx * regs ; if ( MEM_ALIGN ( src ) == BITS_PER_WORD / 2 && MEM_ALIGN ( dest ) == BITS_PER_WORD / 2 ) bits = BITS_PER_WORD / 2 ; else bits = BITS_PER_WORD ; mode = mode_for_size ( bits , MODE_INT , 0 ) ; delta = bits / BITS_PER_UNIT ; regs = XALLOCAVEC ( rtx , length / delta ) ; for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) { regs [ i ] = gen_reg_rtx ( mode ) ; if ( MEM_ALIGN ( src ) >= bits ) mips_emit_move ( regs [ i ] , adjust_address ( src , mode , offset ) ) ; else { rtx part = adjust_address ( src , BLKmode , offset ) ; set_mem_size ( part , delta ) ; if ( ! mips_expand_ext_as_unaligned_load ( regs [ i ] , part , bits , 0 , 0 ) ) gcc_unreachable ( ) ; } } for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) if ( MEM_ALIGN ( dest ) >= bits ) mips_emit_move ( adjust_address ( dest , mode , offset ) , regs [ i ] ) ; else { rtx part = adjust_address ( dest , BLKmode , offset ) ; set_mem_size ( part , delta ) ; if ( ! mips_expand_ins_as_unaligned_store ( part , regs [ i ] , bits , 0 ) ) gcc_unreachable ( ) ; } if ( offset < length ) { src = adjust_address ( src , BLKmode , offset ) ; dest = adjust_address ( dest , BLKmode , offset ) ; move_by_pieces ( dest , src , length - offset , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) , 0 ) ; } } </s>

Emit straight-line code to move LENGTH bytes from SRC to DEST . Assume that the areas do not overlap .


<s> bool X86FixupSetCCPass :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; MRI = & MF . getRegInfo ( ) ; TII = MF . getSubtarget < X86Subtarget > ( ) . getInstrInfo ( ) ; SmallVector < MachineInstr * , 4 > ToErase ; for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( MI . getOpcode ( ) != X86 :: SETCCr ) continue ; MachineInstr * ZExt = nullptr ; for ( auto & Use : MRI -> use_instructions ( MI . getOperand ( 0 ) . getReg ( ) ) ) if ( Use . getOpcode ( ) == X86 :: MOVZX32rr8 ) ZExt = & Use ; if ( ! ZExt ) continue ; MachineInstr * FlagsDefMI = findFlagsImpDef ( MI . getParent ( ) , MachineBasicBlock :: reverse_iterator ( & MI ) ) ; if ( ! FlagsDefMI ) continue ; if ( impUsesFlags ( FlagsDefMI ) ) continue ; ++ NumSubstZexts ; Changed = true ; const TargetRegisterClass * RC = MF . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ? & X86 :: GR32RegClass : & X86 :: GR32_ABCDRegClass ; Register ZeroReg = MRI -> createVirtualRegister ( RC ) ; Register InsertReg = MRI -> createVirtualRegister ( RC ) ; BuildMI ( MBB , FlagsDefMI , MI . getDebugLoc ( ) , TII -> get ( X86 :: MOV32r0 ) , ZeroReg ) ; BuildMI ( * ZExt -> getParent ( ) , ZExt , ZExt -> getDebugLoc ( ) , TII -> get ( X86 :: INSERT_SUBREG ) , InsertReg ) . addReg ( ZeroReg ) . addReg ( MI . getOperand ( 0 ) . getReg ( ) ) . addImm ( X86 :: sub_8bit ) ; MRI -> replaceRegWith ( ZExt -> getOperand ( 0 ) . getReg ( ) , InsertReg ) ; ToErase . push_back ( ZExt ) ; } } for ( auto & I : ToErase ) I -> eraseFromParent ( ) ; return Changed ; } </s>


<s> static void aarch64_option_restore ( struct gcc_options * opts , struct gcc_options * , struct cl_target_option * ptr ) { opts -> x_explicit_arch = ptr -> x_explicit_arch ; selected_arch = aarch64_get_arch ( ptr -> x_explicit_arch ) ; opts -> x_explicit_tune_core = ptr -> x_explicit_tune_core ; if ( opts -> x_explicit_tune_core == aarch64_none && opts -> x_explicit_arch != aarch64_no_arch ) selected_tune = & all_cores [ selected_arch -> ident ] ; else selected_tune = aarch64_get_tune_cpu ( ptr -> x_explicit_tune_core ) ; opts -> x_aarch64_override_tune_string = ptr -> x_aarch64_override_tune_string ; opts -> x_aarch64_branch_protection_string = ptr -> x_aarch64_branch_protection_string ; if ( opts -> x_aarch64_branch_protection_string ) { aarch64_parse_branch_protection ( opts -> x_aarch64_branch_protection_string , NULL ) ; } aarch64_override_options_internal ( opts ) ; } </s>

Implements TARGET_OPTION_RESTORE . Restore the backend codegen decisions using the information saved in PTR .


"stack re-alignment, but LLVM couldn't handle it "

"(probably because it has a dynamic alloca)."

"SP has to be saved in order to align variable sized stack object!"

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> void AMDGPUPassConfig :: addIRPasses ( ) { const AMDGPUTargetMachine & TM = getAMDGPUTargetMachine ( ) ; disablePass ( & StackMapLivenessID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & PatchableFunctionID ) ; addPass ( createAMDGPULowerIntrinsicsPass ( ) ) ; if ( TM . getTargetTriple ( ) . getArch ( ) == Triple :: r600 || ! EnableAMDGPUFunctionCalls ) { addPass ( createAMDGPUAlwaysInlinePass ( ) ) ; addPass ( createAlwaysInlinerLegacyPass ( ) ) ; addPass ( createBarrierNoopPass ( ) ) ; } if ( TM . getTargetTriple ( ) . getArch ( ) == Triple :: amdgcn ) { addPass ( createAMDGPUCodeGenPreparePass ( ) ) ; } addPass ( createAMDGPUOpenCLImageTypeLoweringPass ( ) ) ; if ( TM . getOptLevel ( ) > CodeGenOpt :: None ) { addPass ( createInferAddressSpacesPass ( ) ) ; addPass ( createAMDGPUPromoteAlloca ( ) ) ; if ( EnableSROA ) addPass ( createSROAPass ( ) ) ; addStraightLineScalarOptimizationPasses ( ) ; if ( EnableAMDGPUAliasAnalysis ) { addPass ( createAMDGPUAAWrapperPass ( ) ) ; addPass ( createExternalAAWrapperPass ( [ ] ( Pass & P , Function & , AAResults & AAR ) { if ( auto * WrapperPass = P . getAnalysisIfAvailable < AMDGPUAAWrapperPass > ( ) ) AAR . addAAResult ( WrapperPass -> getResult ( ) ) ; } ) ) ; } } TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addEarlyCSEOrGVNPass ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU


<s> bool AArch64TargetLowering :: isIntDivCheap ( EVT VT , AttributeList Attr ) const { bool OptSize = Attr . hasAttribute ( AttributeList :: FunctionIndex , Attribute :: MinSize ) ; return OptSize && ! VT . isVector ( ) ; } </s>

Return true if integer divide is usually cheaper than a sequence of several shifts , adds , and multiplies for this target .


<s> bool s390_bytemask_vector_p ( rtx op , unsigned * mask ) { int i ; unsigned tmp_mask = 0 ; int nunit , unit_size ; if ( ! VECTOR_MODE_P ( GET_MODE ( op ) ) || GET_CODE ( op ) != CONST_VECTOR || ! CONST_INT_P ( XVECEXP ( op , 0 , 0 ) ) ) return false ; nunit = GET_MODE_NUNITS ( GET_MODE ( op ) ) ; unit_size = GET_MODE_UNIT_SIZE ( GET_MODE ( op ) ) ; for ( i = 0 ; i < nunit ; i ++ ) { unsigned HOST_WIDE_INT c ; int j ; if ( ! CONST_INT_P ( XVECEXP ( op , 0 , i ) ) ) return false ; c = UINTVAL ( XVECEXP ( op , 0 , i ) ) ; for ( j = 0 ; j < unit_size ; j ++ ) { if ( ( c & 0xff ) != 0 && ( c & 0xff ) != 0xff ) return false ; tmp_mask |= ( c & 1 ) << ( ( nunit - 1 - i ) * unit_size + j ) ; c = c >> BITS_PER_UNIT ; } } if ( mask != NULL ) * mask = tmp_mask ; return true ; } </s>

Return true if C consists only of byte chunks being either 0 or 0xff . If MASK is ! =NULL a byte mask is generated which is appropriate for the vector generate byte mask instruction .


<s> void XCoreInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) && ! I -> isDebugValue ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = * MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ; BuildMI ( MBB , I , DL , get ( XCore :: LDWFI ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) . addMemOperand ( MMO ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s>
InstructionCost
PPCTTIImpl
::
getArithmeticInstrCost
(
unsigned
Opcode
,
Type
*
Ty
,
TTI
::
TargetCostKind
CostKind
,
TTI
::
OperandValueKind
Op1Info
,
TTI
::
OperandValueKind
Op2Info
,
TTI
::
OperandValueProperties
Opd1PropInfo
,
TTI
::
OperandValueProperties
Opd2PropInfo
,
ArrayRef
<
const
Value
*
>
Args
,
const
Instruction
*
CxtI
)
{
assert
(
TLI
->
InstructionOpcodeToISD
(
Opcode
)
&&
"Invalid opcode"
)
;
if
(
CostKind
!=
TTI
::
TCK_RecipThroughput
)
return
BaseT
::
getArithmeticInstrCost
(
Opcode
,
Ty
,
CostKind
,
Op1Info
,
Op2Info
,
Opd1PropInfo
,
Opd2PropInfo
,
Args
,
CxtI
)
;
InstructionCost
Cost
=
BaseT
::
getArithmeticInstrCost
(
Opcode
,
Ty
,
CostKind
,
Op1Info
,
Op2Info
,
Opd1PropInfo
,
Opd2PropInfo
)
;
return
vectorCostAdjustment
(
Cost
,
Opcode
,
Ty
,
nullptr
)
;
}
</s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> unsigned ARMFastISel :: fastEmitInst_rri ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , bool Op0IsKill , unsigned Op1 , bool Op1IsKill , uint64_t Imm ) { unsigned ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , 1 ) ; Op1 = constrainOperandRegClass ( II , Op1 , 2 ) ; if ( II . getNumDefs ( ) >= 1 ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) . addImm ( Imm ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) . addImm ( Imm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ 0 ] ) ) ; } return ResultReg ; } </s>

Emit a MachineInstr with two register operands , an immediate , and a result register in the given register class .


<s> void GBZ80PassConfig :: addPreSched2 ( ) { addPass ( createGBZ80PostPEIPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> static rtx adjust_vec_address_pcrel ( rtx addr , rtx element_offset , rtx base_tmp ) { rtx new_addr = NULL ; gcc_assert ( CONST_INT_P ( element_offset ) ) ; if ( GET_CODE ( addr ) == CONST ) addr = XEXP ( addr , 0 ) ; if ( GET_CODE ( addr ) == PLUS ) { rtx op0 = XEXP ( addr , 0 ) ; rtx op1 = XEXP ( addr , 1 ) ; if ( CONST_INT_P ( op1 ) ) { HOST_WIDE_INT offset = INTVAL ( XEXP ( addr , 1 ) ) + INTVAL ( element_offset ) ; if ( offset == 0 ) new_addr = op0 ; else { rtx plus = gen_rtx_PLUS ( Pmode , op0 , GEN_INT ( offset ) ) ; new_addr = gen_rtx_CONST ( Pmode , plus ) ; } } else { emit_move_insn ( base_tmp , addr ) ; new_addr = gen_rtx_PLUS ( Pmode , base_tmp , element_offset ) ; } } else if ( SYMBOL_REF_P ( addr ) || LABEL_REF_P ( addr ) ) { rtx plus = gen_rtx_PLUS ( Pmode , addr , element_offset ) ; new_addr = gen_rtx_CONST ( Pmode , plus ) ; } else gcc_unreachable ( ) ; return new_addr ; } </s>

Helper function update PC-relative addresses when we are adjusting a memory address ( ADDR ) to a vector to point to a scalar field within the vector with a constant offset ( ELEMENT_OFFSET ) . If the address is not valid , we can use the base register temporary ( BASE_TMP ) to form the address .


<s> bool RISCVInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { TBB = FBB = nullptr ; Cond . clear ( ) ; auto * RVFI = MBB . getParent ( ) -> getInfo < RISCVMachineFunctionInfo > ( ) ; MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) || ! isUnpredicatedTerminator ( * I ) ) return RVFI -> isHwlpBasicBlock ( MBB . getNextNode ( ) ) ; MachineBasicBlock :: iterator FirstUncondOrIndirectBr = MBB . end ( ) ; int NumTerminators = 0 ; for ( auto J = I . getReverse ( ) ; J != MBB . rend ( ) && isUnpredicatedTerminator ( * J ) ; J ++ ) { NumTerminators ++ ; if ( J -> getDesc ( ) . isUnconditionalBranch ( ) || J -> getDesc ( ) . isIndirectBranch ( ) ) { FirstUncondOrIndirectBr = J . getReverse ( ) ; } } if ( AllowModify && FirstUncondOrIndirectBr != MBB . end ( ) ) { while ( std :: next ( FirstUncondOrIndirectBr ) != MBB . end ( ) ) { std :: next ( FirstUncondOrIndirectBr ) -> eraseFromParent ( ) ; NumTerminators -- ; } I = FirstUncondOrIndirectBr ; } if ( I -> getDesc ( ) . isIndirectBranch ( ) ) return true ; if ( NumTerminators > 2 ) return true ; if ( NumTerminators == 1 && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { TBB = getBranchDestBlock ( * I ) ; return false ; } if ( NumTerminators == 1 && I -> getDesc ( ) . isConditionalBranch ( ) ) { parseCondBranch ( * I , TBB , Cond ) ; return false ; } if ( NumTerminators == 2 && std :: prev ( I ) -> getDesc ( ) . isConditionalBranch ( ) && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { parseCondBranch ( * std :: prev ( I ) , TBB , Cond ) ; FBB = getBranchDestBlock ( * I ) ; return false ; } return true ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


Return insn index for the vector compare instruction for given CODE , and DEST_MODE , OP_MODE . Return -1 if valid insn is not available .


"Hexagon generate \"insert\" instructions"

getPassName - Return a nice clean name for a pass .


<s>
void
R600SchedStrategy
::
releaseBottomNode
(
SUnit
*
SU
)
{
DEBUG
(
dbgs
(
)
<<
"Bottom Releasing "
;
SU
->
dump
(
DAG
)
;
)
;
if
(
isPhysicalRegCopy
(
SU
->
getInstr
(
)
)
)
{
PhysicalRegCopy
.
push_back
(
SU
)
;
return
;
}
int
IK
=
getInstKind
(
SU
)
;
if
(
IK
==
IDOther
)
Available
[
IDOther
]
.
push_back
(
SU
)
;
else
Pending
[
IK
]
.
push_back
(
SU
)
;
}
</s>

Currently only scheduling top-down , so this method is empty .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this , LittleEndian ) , usingPBQP ( false ) { initAsmInfo ( ) ; if ( EnablePBQP && Subtarget . isCortexA57 ( ) && OL != CodeGenOpt :: None ) { usingPBQP = true ; RegisterRegAlloc :: setDefault ( createAArch64A57PBQPRegAlloc ) ; } } </s>


<s>
void
M680x0DAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
SDLoc
DL
(
Node
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
switch
(
Opcode
)
{
default
:
break
;
case
M680x0ISD
::
GlobalBaseReg
:
ReplaceNode
(
Node
,
getGlobalBaseReg
(
)
)
;
return
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> unsigned BlackfinRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return hasFP ( MF ) ? BF :: FP : BF :: SP ; } </s>


<s> bool targetHandlesStackFrameRounding ( ) const override { return true ; } </s>

targetHandlesStackFrameRounding - Returns true if the target is responsible for rounding up the stack frame ( probably at emitPrologue time ) .


<s> unsigned getDstReg ( ) const { return Dst ; } </s>

Get the definition register of the loaded value .


<s> SDValue TeeRISCTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_TeeRISC ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s>
bool
R600AsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MF
.
ensureAlignment
(
8
)
;
SetupMachineFunction
(
MF
)
;
MCContext
&
Context
=
getObjFileLowering
(
)
.
getContext
(
)
;
MCSectionELF
*
ConfigSection
=
Context
.
getELFSection
(
".AMDGPU.config"
,
ELF
::
SHT_PROGBITS
,
0
)
;
OutStreamer
->
SwitchSection
(
ConfigSection
)
;
EmitProgramInfoR600
(
MF
)
;
EmitFunctionBody
(
)
;
if
(
isVerbose
(
)
)
{
MCSectionELF
*
CommentSection
=
Context
.
getELFSection
(
".AMDGPU.csdata"
,
ELF
::
SHT_PROGBITS
,
0
)
;
OutStreamer
->
SwitchSection
(
CommentSection
)
;
R600MachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
R600MachineFunctionInfo
>
(
)
;
OutStreamer
->
emitRawComment
(
Twine
(
"SQ_PGM_RESOURCES:STACK_SIZE = "
+
Twine
(
MFI
->
CFStackSize
)
)
)
;
}
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static rtx ix86_internal_arg_pointer ( void ) { if ( FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN && DECL_NAME ( current_function_decl ) && MAIN_NAME_P ( DECL_NAME ( current_function_decl ) ) && DECL_FILE_SCOPE_P ( current_function_decl ) ) { cfun -> machine -> force_align_arg_pointer = gen_rtx_REG ( Pmode , 2 ) ; return copy_to_reg ( cfun -> machine -> force_align_arg_pointer ) ; } else return virtual_incoming_args_rtx ; } </s>

Handle the TARGET_INTERNAL_ARG_POINTER hook .


<s> bool SITargetLowering :: isFMAFasterThanFMulAndFAdd ( EVT VT ) const { VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f32 : return Subtarget -> hasFP32Denormals ( ) && Subtarget -> hasFastFMAF32 ( ) ; case MVT :: f64 : return true ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> void Z80RegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { MachineFunction & MF = * MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock :: iterator II = MBB -> begin ( ) ; DebugLoc DL = MBB -> findDebugLoc ( II ) ; MRI . setRegClass ( BaseReg , Is24Bit ? & Z80 :: I24RegClass : & Z80 :: I16RegClass ) ; BuildMI ( * MBB , II , DL , TII . get ( Is24Bit ? Z80 :: LEA24ro : Z80 :: LEA16ro ) , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ; return ; unsigned CopyReg = MRI . createVirtualRegister ( Is24Bit ? & Z80 :: I24RegClass : & Z80 :: I16RegClass ) ; unsigned OffsetReg = MRI . createVirtualRegister ( Is24Bit ? & Z80 :: O24RegClass : & Z80 :: O16RegClass ) ; BuildMI ( * MBB , II , DL , TII . get ( TargetOpcode :: COPY ) , CopyReg ) . addReg ( getFrameRegister ( MF ) ) ; BuildMI ( * MBB , II , DL , TII . get ( Is24Bit ? Z80 :: LD24ri : Z80 :: LD16ri ) , OffsetReg ) . addImm ( Offset ) ; BuildMI ( * MBB , II , DL , TII . get ( Is24Bit ? Z80 :: ADD24ao : Z80 :: ADD16ao ) , BaseReg ) . addReg ( CopyReg ) . addReg ( OffsetReg ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .


<s> bool PPCTTIImpl :: shouldBuildRelLookupTables ( ) const { const PPCTargetMachine & TM = ST -> getTargetMachine ( ) ; if ( ! TM . isELFv2ABI ( ) ) return false ; return BaseT :: shouldBuildRelLookupTables ( ) ; } </s>

Return true if lookup tables should be turned into relative lookup tables .


<s> static void emit_and_preserve ( rtx seq , rtx reg , rtx reg2 ) { HOST_WIDE_INT offset = 16 * UNITS_PER_WORD ; HOST_WIDE_INT size = SPARC_STACK_ALIGN ( offset + 2 * UNITS_PER_WORD ) ; rtx slot = gen_rtx_MEM ( word_mode , plus_constant ( Pmode , stack_pointer_rtx , SPARC_STACK_BIAS + offset ) ) ; emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - size ) ) ) ; emit_insn ( gen_rtx_SET ( slot , reg ) ) ; if ( reg2 ) emit_insn ( gen_rtx_SET ( adjust_address ( slot , word_mode , UNITS_PER_WORD ) , reg2 ) ) ; emit_insn ( seq ) ; if ( reg2 ) emit_insn ( gen_rtx_SET ( reg2 , adjust_address ( slot , word_mode , UNITS_PER_WORD ) ) ) ; emit_insn ( gen_rtx_SET ( reg , slot ) ) ; emit_insn ( gen_stack_pointer_inc ( GEN_INT ( size ) ) ) ; } </s>

Emit the sequence of insns SEQ while preserving the registers .


<s> bool AMDGPUPromoteKernelArguments :: runOnFunction ( Function & F ) { MemorySSA & MSSA = getAnalysis < MemorySSAWrapperPass > ( ) . getMSSA ( ) ; return run ( F , MSSA ) ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static std :: unique_ptr < AVROperand > CreateReg ( unsigned RegNum , SMLoc S , SMLoc E ) { return std :: make_unique < AVROperand > ( RegNum , S , E ) ; } </s>

CreateReg - Allocate a single virtual register for the given type .


"argument to %qs must be a 2-bit unsigned literal"


<s> void AArch64InstPrinter :: printImplicitlyTypedVectorList ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { printVectorList ( MI , OpNum , O , "" ) ; } </s>

Print a list of vector registers where the type suffix is implicit ( i.e .


Return a string to perform a load_multiple operation . operands [ 0 ] is the vector . operands [ 1 ] is the source address . operands [ 2 ] is the first destination register .


<s> unsigned Z80oldInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( isFrameLoadOpcode ( MI . getOpcode ( ) ) && ! MI . getOperand ( 0 ) . getSubReg ( ) && isFrameOperand ( MI , 1 , FrameIndex ) ) { return MI . getOperand ( 0 ) . getReg ( ) ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"SSE execution domain fixup"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> virtual const TargetRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> HOST_WIDE_INT compute_frame_size ( HOST_WIDE_INT size ) { int regno ; HOST_WIDE_INT total_size ; HOST_WIDE_INT var_size ; HOST_WIDE_INT args_size ; HOST_WIDE_INT extra_size ; HOST_WIDE_INT gp_reg_rounded ; HOST_WIDE_INT gp_reg_size ; HOST_WIDE_INT fp_reg_size ; long mask ; gp_reg_size = 0 ; fp_reg_size = 0 ; mask = 0 ; extra_size = IQ2000_STACK_ALIGN ( ( 0 ) ) ; var_size = IQ2000_STACK_ALIGN ( size ) ; args_size = IQ2000_STACK_ALIGN ( crtl -> outgoing_args_size ) ; if ( args_size == 0 && cfun -> calls_alloca ) args_size = 4 * UNITS_PER_WORD ; total_size = var_size + args_size + extra_size ; for ( regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) { if ( MUST_SAVE_REGISTER ( regno ) ) { gp_reg_size += GET_MODE_SIZE ( gpr_mode ) ; mask |= 1L << ( regno - GP_REG_FIRST ) ; } } if ( crtl -> calls_eh_return ) { unsigned int i ; for ( i = 0 ; ; ++ i ) { regno = EH_RETURN_DATA_REGNO ( i ) ; if ( regno == ( int ) INVALID_REGNUM ) break ; gp_reg_size += GET_MODE_SIZE ( gpr_mode ) ; mask |= 1L << ( regno - GP_REG_FIRST ) ; } } gp_reg_rounded = IQ2000_STACK_ALIGN ( gp_reg_size ) ; total_size += gp_reg_rounded + IQ2000_STACK_ALIGN ( fp_reg_size ) ; if ( total_size == extra_size && ! profile_flag ) total_size = extra_size = 0 ; total_size += IQ2000_STACK_ALIGN ( crtl -> args . pretend_args_size ) ; cfun -> machine -> total_size = total_size ; cfun -> machine -> var_size = var_size ; cfun -> machine -> args_size = args_size ; cfun -> machine -> extra_size = extra_size ; cfun -> machine -> gp_reg_size = gp_reg_size ; cfun -> machine -> fp_reg_size = fp_reg_size ; cfun -> machine -> mask = mask ; cfun -> machine -> initialized = reload_completed ; cfun -> machine -> num_gp = gp_reg_size / UNITS_PER_WORD ; if ( mask ) { unsigned long offset ; offset = ( args_size + extra_size + var_size + gp_reg_size - GET_MODE_SIZE ( gpr_mode ) ) ; cfun -> machine -> gp_sp_offset = offset ; cfun -> machine -> gp_save_offset = offset - total_size ; } else { cfun -> machine -> gp_sp_offset = 0 ; cfun -> machine -> gp_save_offset = 0 ; } cfun -> machine -> fp_sp_offset = 0 ; cfun -> machine -> fp_save_offset = 0 ; return total_size ; } </s>

Typical stack layout should looks like this after the function 's prologue : | | -- ^ | | \ | | | arguments saved | Increasing | | on the stack | addresses PARENT arg pointer - > | | / -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - | | - space for argument split between regs & stack -- CHILD | | \ < -- ( return address here ) | | other call | | saved registers | | / -- frame pointer - > | | \ ___ | | local | | | variables |f | | / |r -- |a | | \ |m | | outgoing |e | | arguments | | Decreasing ( hard ) frame pointer | | / | | addresses and stack pointer - > | | / _|_ | -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- V


<s>
MCSymbol
*
MBlazeMCInstLower
::
GetExternalSymbolSymbol
(
const
MachineOperand
&
MO
)
const
{
switch
(
MO
.
getTargetFlags
(
)
)
{
default
:
llvm_unreachable
(
"Unknown target flag on GV operand"
)
;
case
0
:
break
;
}
return
Printer
.
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
;
}
</s>

Return the MCSymbol for the specified ExternalSymbol .

MBlaze
MBlaze
"Unknown target flag on GV operand"
0


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { if ( RC == ARM :: GPRRegisterClass || RC == ARM :: tGPRRegisterClass || RC == ARM :: tcGPRRegisterClass || RC == ARM :: rGPRRegisterClass || RC == ARM :: GPRnopcRegisterClass ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2LDRi12 ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } ARMBaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC , TRI ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .

ARM ARM::GPRRegisterClass ARM::tGPRRegisterClass ARM::tcGPRRegisterClass ARM::rGPRRegisterClass ARM::GPRnopcRegisterClass ARM::t2LDRi12 0 ARM


<s> static bool ix86_masked_all_ones ( unsigned HOST_WIDE_INT elems , tree arg_mask ) { if ( TREE_CODE ( arg_mask ) != INTEGER_CST ) return false ; unsigned HOST_WIDE_INT mask = TREE_INT_CST_LOW ( arg_mask ) ; if ( ( mask | ( HOST_WIDE_INT_M1U << elems ) ) != HOST_WIDE_INT_M1U ) return false ; return true ; } </s>

Return true if arg_mask is all ones , ELEMS is elements number of corresponding vector .


<s> void assignValueToAddress ( const CallLowering :: ArgInfo & Arg , unsigned RegIndex , Register Addr , LLT MemTy , MachinePointerInfo & MPO , CCValAssign & VA ) override { unsigned MaxSize = MemTy . getSizeInBytes ( ) * 8 ; if ( ! Arg . IsFixed ) MaxSize = 0 ; Register ValVReg = Arg . Regs [ RegIndex ] ; if ( VA . getLocInfo ( ) != CCValAssign :: LocInfo :: FPExt ) { MVT LocVT = VA . getLocVT ( ) ; MVT ValVT = VA . getValVT ( ) ; if ( VA . getValVT ( ) == MVT :: i8 || VA . getValVT ( ) == MVT :: i16 ) { std :: swap ( ValVT , LocVT ) ; MemTy = LLT ( VA . getValVT ( ) ) ; } ValVReg = extendRegister ( ValVReg , VA , MaxSize ) ; } else { MemTy = LLT ( VA . getValVT ( ) ) ; } assignValueToAddress ( ValVReg , Addr , MemTy , MPO , VA ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> void MipsPostLegalizerCombiner :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < TargetPassConfig > ( ) ; AU . setPreservesCFG ( ) ; getSelectionDAGFallbackAnalysisUsage ( AU ) ; AU . addRequired < GISelKnownBitsAnalysis > ( ) ; AU . addPreserved < GISelKnownBitsAnalysis > ( ) ; if ( ! IsOptNone ) { AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; } MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
void
NVPTXAsmPrinter
::
emitHeader
(
Module
&
M
,
raw_ostream
&
O
)
{
O
<<
"//\n"
;
O
<<
"// Generated by LLVM NVPTX Back-End\n"
;
O
<<
"//\n"
;
O
<<
"\n"
;
unsigned
PTXVersion
=
nvptxSubtarget
.
getPTXVersion
(
)
;
O
<<
".version "
<<
(
PTXVersion
/
10
)
<<
"."
<<
(
PTXVersion
%
10
)
<<
"\n"
;
O
<<
".target "
;
O
<<
nvptxSubtarget
.
getTargetName
(
)
;
if
(
nvptxSubtarget
.
getDrvInterface
(
)
==
NVPTX
::
NVCL
)
O
<<
", texmode_independent"
;
if
(
nvptxSubtarget
.
getDrvInterface
(
)
==
NVPTX
::
CUDA
)
{
if
(
!
nvptxSubtarget
.
hasDouble
(
)
)
O
<<
", map_f64_to_f32"
;
}
if
(
MAI
->
doesSupportDebugInformation
(
)
)
O
<<
", debug"
;
O
<<
"\n"
;
O
<<
".address_size "
;
if
(
nvptxSubtarget
.
is64Bit
(
)
)
O
<<
"64"
;
else
O
<<
"32"
;
O
<<
"\n"
;
O
<<
"\n"
;
}
</s>

Emit the header for this unit , not including the initial length field .

NVPTX
NVPTX
"//\n"
"// Generated by LLVM NVPTX Back-End\n"
"//\n"
"\n"
".version "
10
"."
10
"\n"
".target "
NVPTX::NVCL
", texmode_independent"
NVPTX::CUDA
", map_f64_to_f32"
", debug"
"\n"
".address_size "
"64"
"32"
"\n"
"\n"


<s> static tree bpf_core_walk ( tree * tp , int * walk_subtrees , void * data ) { location_t loc = * ( ( location_t * ) data ) ; if ( TYPE_P ( * tp ) ) { * walk_subtrees = 0 ; return NULL_TREE ; } if ( bpf_core_is_maybe_aggregate_access ( * tp ) ) { tree newdecl = bpf_core_newdecl ( TREE_TYPE ( * tp ) ) ; tree newcall = build_call_expr_loc ( loc , newdecl , 1 , * tp ) ; * tp = newcall ; * walk_subtrees = 0 ; } return NULL_TREE ; } </s>

Callback function used with walk_tree from bpf_resolve_overloaded_builtin .


<s> SDValue WebAssemblySelectionDAGInfo :: EmitTargetCodeForMemmove ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Op1 , SDValue Op2 , SDValue Op3 , Align Alignment , bool IsVolatile , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { return EmitTargetCodeForMemcpy ( DAG , DL , Chain , Op1 , Op2 , Op3 , Alignment , IsVolatile , false , DstPtrInfo , SrcPtrInfo ) ; } </s>

Emit target-specific code that performs a memmove .


<s> void SparcTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { KnownBits Known2 ; Known . resetAll ( ) ; switch ( Op . getOpcode ( ) ) { default : break ; case SPISD :: SELECT_ICC : case SPISD :: SELECT_XCC : case SPISD :: SELECT_FCC : Known = DAG . computeKnownBits ( Op . getOperand ( 1 ) , Depth + 1 ) ; Known2 = DAG . computeKnownBits ( Op . getOperand ( 0 ) , Depth + 1 ) ; Known = KnownBits :: commonBits ( Known , Known2 ) ; break ; } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> const HexagonRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>


<s>
static
void
aarch64_emit_probe_stack_range
(
HOST_WIDE_INT
first
,
poly_int64
poly_size
)
{
HOST_WIDE_INT
size
;
if
(
!
poly_size
.
is_constant
(
&
size
)
)
{
sorry
(
"stack probes for SVE frames"
)
;
return
;
}
rtx
reg1
=
gen_rtx_REG
(
Pmode
,
PROBE_STACK_FIRST_REGNUM
)
;
gcc_assert
(
(
first
%
ARITH_FACTOR
)
==
0
)
;
if
(
size
<=
PROBE_INTERVAL
)
{
const
HOST_WIDE_INT
base
=
ROUND_UP
(
size
,
ARITH_FACTOR
)
;
emit_set_insn
(
reg1
,
plus_constant
(
Pmode
,
stack_pointer_rtx
,
(
first
+
base
)
)
)
;
emit_stack_probe
(
plus_constant
(
Pmode
,
reg1
,
base
size
)
)
;
}
else
if
(
size
<=
4
*
PROBE_INTERVAL
)
{
HOST_WIDE_INT
i
,
rem
;
emit_set_insn
(
reg1
,
plus_constant
(
Pmode
,
stack_pointer_rtx
,
(
first
+
PROBE_INTERVAL
)
)
)
;
emit_stack_probe
(
reg1
)
;
for
(
i
=
2
*
PROBE_INTERVAL
;
i
<
size
;
i
+=
PROBE_INTERVAL
)
{
emit_set_insn
(
reg1
,
plus_constant
(
Pmode
,
reg1
,
PROBE_INTERVAL
)
)
;
emit_stack_probe
(
reg1
)
;
}
rem
=
size
(
i
PROBE_INTERVAL
)
;
if
(
rem
>
256
)
{
const
HOST_WIDE_INT
base
=
ROUND_UP
(
rem
,
ARITH_FACTOR
)
;
emit_set_insn
(
reg1
,
plus_constant
(
Pmode
,
reg1
,
base
)
)
;
emit_stack_probe
(
plus_constant
(
Pmode
,
reg1
,
base
rem
)
)
;
}
else
emit_stack_probe
(
plus_constant
(
Pmode
,
reg1
,
rem
)
)
;
}
else
{
rtx
reg2
=
gen_rtx_REG
(
Pmode
,
PROBE_STACK_SECOND_REGNUM
)
;
HOST_WIDE_INT
rounded_size
=
size
&
PROBE_INTERVAL
;
emit_set_insn
(
reg1
,
plus_constant
(
Pmode
,
stack_pointer_rtx
,
first
)
)
;
HOST_WIDE_INT
adjustment
=
(
first
+
rounded_size
)
;
if
(
!
aarch64_uimm12_shift
(
adjustment
)
)
{
aarch64_internal_mov_immediate
(
reg2
,
GEN_INT
(
adjustment
)
,
true
,
Pmode
)
;
emit_set_insn
(
reg2
,
gen_rtx_PLUS
(
Pmode
,
stack_pointer_rtx
,
reg2
)
)
;
}
else
emit_set_insn
(
reg2
,
plus_constant
(
Pmode
,
stack_pointer_rtx
,
adjustment
)
)
;
emit_insn
(
gen_probe_stack_range
(
reg1
,
reg1
,
reg2
)
)
;
if
(
size
!=
rounded_size
)
{
HOST_WIDE_INT
rem
=
size
rounded_size
;
if
(
rem
>
256
)
{
const
HOST_WIDE_INT
base
=
ROUND_UP
(
rem
,
ARITH_FACTOR
)
;
emit_set_insn
(
reg2
,
plus_constant
(
Pmode
,
reg2
,
base
)
)
;
emit_stack_probe
(
plus_constant
(
Pmode
,
reg2
,
base
rem
)
)
;
}
else
emit_stack_probe
(
plus_constant
(
Pmode
,
reg2
,
rem
)
)
;
}
}
emit_insn
(
gen_blockage
(
)
)
;
}
</s>

Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE , inclusive . These are offsets from the current stack pointer .


<s>
void
XCoreFrameLowering
::
processFunctionBeforeFrameFinalized
(
MachineFunction
&
MF
,
RegScavenger
*
RS
)
const
{
assert
(
RS
&&
"requiresRegisterScavenging failed"
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
const
TargetRegisterClass
&
RC
=
XCore
::
GRRegsRegClass
;
const
TargetRegisterInfo
&
TRI
=
*
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
XCoreFunctionInfo
*
XFI
=
MF
.
getInfo
<
XCoreFunctionInfo
>
(
)
;
unsigned
Size
=
TRI
.
getSpillSize
(
RC
)
;
unsigned
Align
=
TRI
.
getSpillAlignment
(
RC
)
;
if
(
XFI
->
isLargeFrame
(
MF
)
||
hasFP
(
MF
)
)
RS
->
addScavengingFrameIndex
(
MFI
.
CreateStackObject
(
Size
,
Align
,
false
)
)
;
if
(
XFI
->
isLargeFrame
(
MF
)
&&
!
hasFP
(
MF
)
)
RS
->
addScavengingFrameIndex
(
MFI
.
CreateStackObject
(
Size
,
Align
,
false
)
)
;
}
</s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .

XCore
XCore
"requiresRegisterScavenging failed"
XCore::GRRegsRegClass
XCore
XCore


<s> bool isPassEnabled ( const cl :: opt < bool > & Opt , CodeGenOpt :: Level Level = CodeGenOpt :: Default ) const { if ( Opt . getNumOccurrences ( ) ) return Opt ; if ( TM -> getOptLevel ( ) < Level ) return false ; return Opt ; } </s>

Check if a pass is enabled given Opt option .


"unknown core architecture %qs specified with %qs"

Set ` avr_arch ' as specified by ` -mmcu= ' . Return true on success .


<s> bool KudeyarPassConfig :: addInstSelector ( ) { addPass ( createKudeyarISelDag ( getKudeyarTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


"SI optimize exec mask operations pre-RA"

getPassName - Return a nice clean name for a pass .


<s> static rtx ft32_libcall_value ( enum machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( mode , FT32_R0 ) ; } </s>

Define how to find the value returned by a library function . We always return values in register $ r0 for ft32 .


"WebAssembly Lower RefTypes Int-Ptr Conversions"


<s> static bool sparc_function_value_regno_p ( const unsigned int regno ) { return ( regno == 8 || ( TARGET_FPU && regno == 32 ) ) ; } </s>

Handle FUNCTION_VALUE_REGNO_P . On the SPARC , the first `` output '' reg is used for integer values , and the first floating point register is used for floating point values .


"Unaligned memory access not supported: not "

"DSP extension not enabled: not running pass "

"Only supporting little endian: not running pass "

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static void riscv_v_adjust_scalable_frame ( rtx target , poly_int64 offset , bool epilogue ) { rtx tmp = RISCV_PROLOGUE_TEMP ( Pmode ) ; rtx adjust_size = RISCV_PROLOGUE_TEMP2 ( Pmode ) ; rtx insn , dwarf , adjust_frame_rtx ; riscv_legitimize_poly_move ( Pmode , adjust_size , tmp , gen_int_mode ( offset , Pmode ) ) ; if ( epilogue ) insn = gen_add3_insn ( target , target , adjust_size ) ; else insn = gen_sub3_insn ( target , target , adjust_size ) ; insn = emit_insn ( insn ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; adjust_frame_rtx = gen_rtx_SET ( target , plus_constant ( Pmode , target , epilogue ? offset : - offset ) ) ; dwarf = alloc_reg_note ( REG_FRAME_RELATED_EXPR , copy_rtx ( adjust_frame_rtx ) , NULL_RTX ) ; REG_NOTES ( insn ) = dwarf ; } </s>

Adjust scalable frame of vector for prologue & & epilogue .


<s> static bool arc_rewrite_small_data_p ( const_rtx x ) { if ( GET_CODE ( x ) == CONST ) x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == PLUS ) { if ( GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) x = XEXP ( x , 0 ) ; } if ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_SMALL_P ( x ) ) { gcc_assert ( SYMBOL_REF_TLS_MODEL ( x ) == 0 ) ; return true ; } return false ; } </s>

Return true if X is a small data address that can be rewritten as a gp+symref .


<s>
void
Tile64AsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
SmallString
<
128
>
Str
;
raw_svector_ostream
OS
(
Str
)
;
if
(
MI
->
isBundle
(
)
)
{
std
::
vector
<
const
MachineInstr
*
>
BundleMIs
;
unsigned
int
IgnoreCount
=
0
;
MachineBasicBlock
::
const_instr_iterator
MII
=
MI
;
MachineBasicBlock
::
const_instr_iterator
MBBe
=
MI
->
getParent
(
)
->
instr_end
(
)
;
++
MII
;
while
(
MII
!=
MBBe
&&
MII
->
isInsideBundle
(
)
)
{
const
MachineInstr
*
MInst
=
MII
;
if
(
MInst
->
getOpcode
(
)
==
TargetOpcode
::
DBG_VALUE
||
MInst
->
getOpcode
(
)
==
TargetOpcode
::
IMPLICIT_DEF
)
{
IgnoreCount
++
;
}
else
{
BundleMIs
.
push_back
(
MInst
)
;
}
++
MII
;
}
unsigned
Size
=
BundleMIs
.
size
(
)
;
assert
(
(
Size
+
IgnoreCount
)
==
MI
->
getBundleSize
(
)
&&
"Corrupt Bundle!"
)
;
OS
<<
"\t{\n"
;
for
(
unsigned
Index
=
0
;
Index
<
Size
;
++
Index
)
{
const
MachineInstr
*
BMI
=
BundleMIs
[
Index
]
;
OS
<<
"\t"
;
printInstruction
(
BMI
,
OS
)
;
OS
<<
"\n"
;
}
OS
<<
"\t}\n"
;
}
else
{
printInstruction
(
MI
,
OS
)
;
}
OutStreamer
.
EmitRawText
(
OS
.
str
(
)
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


"%qs attribute only applies to functions"

Handle an attribute requiring a FUNCTION_DECL ; arguments as in struct attribute_spec.handler .


<s> unsigned PPCFastISel :: fastEmitInst_ri ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , bool Op0IsKill , uint64_t Imm ) { if ( MachineInstOpcode == PPC :: ADDI ) MRI . setRegClass ( Op0 , & PPC :: GPRC_and_GPRC_NOR0RegClass ) ; else if ( MachineInstOpcode == PPC :: ADDI8 ) MRI . setRegClass ( Op0 , & PPC :: G8RC_and_G8RC_NOX0RegClass ) ; const TargetRegisterClass * UseRC = ( RC == & PPC :: GPRCRegClass ? & PPC :: GPRC_and_GPRC_NOR0RegClass : ( RC == & PPC :: G8RCRegClass ? & PPC :: G8RC_and_G8RC_NOX0RegClass : RC ) ) ; return FastISel :: fastEmitInst_ri ( MachineInstOpcode , UseRC , Op0 , Op0IsKill , Imm ) ; } </s>

Emit a MachineInstr with a register operand , an immediate , and a result register in the given register class .


<s> int h8300_eightbit_constant_address_p ( rtx x ) { const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode ( 0xff00 , HImode ) ; const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode ( 0xffff , HImode ) ; const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode ( 0x00ffff00 , SImode ) ; const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode ( 0x00ffffff , SImode ) ; const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode ( 0xffffff00 , SImode ) ; const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode ( 0xffffffff , SImode ) ; unsigned HOST_WIDE_INT addr ; if ( GET_CODE ( x ) == SYMBOL_REF ) return ( SYMBOL_REF_FLAGS ( x ) & SYMBOL_FLAG_EIGHTBIT_DATA ) != 0 ; if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == SYMBOL_REF && ( SYMBOL_REF_FLAGS ( XEXP ( XEXP ( x , 0 ) , 0 ) ) & SYMBOL_FLAG_EIGHTBIT_DATA ) != 0 ) return 1 ; if ( GET_CODE ( x ) != CONST_INT ) return 0 ; addr = INTVAL ( x ) ; return ( 0 || ( TARGET_NORMAL_MODE && IN_RANGE ( addr , n1 , n2 ) ) || ( TARGET_H8300H && IN_RANGE ( addr , h1 , h2 ) ) || ( TARGET_H8300S && IN_RANGE ( addr , s1 , s2 ) ) ) ; } </s>

Nonzero if X is a constant address suitable as an 8-bit absolute , which is a special case of the ' R ' operand .


<s> const char * AVRMCExpr :: getName ( ) const { const auto & Modifier = llvm :: find_if ( ModifierNames , [ this ] ( ModifierEntry const & Mod ) { return Mod . VariantKind == Kind ; } ) ; if ( Modifier != std :: end ( ModifierNames ) ) { return Modifier -> Spelling ; } return nullptr ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


"********* Hexagon Hardware Loops *********\n"

runOnMachineFunction - Emit the function body .


<s> Optional < Value * > AArch64TTIImpl :: simplifyDemandedVectorEltsIntrinsic ( InstCombiner & IC , IntrinsicInst & II , APInt OrigDemandedElts , APInt & UndefElts , APInt & UndefElts2 , APInt & UndefElts3 , std :: function < void ( Instruction * , unsigned , APInt , APInt & ) > SimplifyAndSetOp ) const { switch ( II . getIntrinsicID ( ) ) { default : break ; case Intrinsic :: aarch64_neon_fcvtxn : case Intrinsic :: aarch64_neon_rshrn : case Intrinsic :: aarch64_neon_sqrshrn : case Intrinsic :: aarch64_neon_sqrshrun : case Intrinsic :: aarch64_neon_sqshrn : case Intrinsic :: aarch64_neon_sqshrun : case Intrinsic :: aarch64_neon_sqxtn : case Intrinsic :: aarch64_neon_sqxtun : case Intrinsic :: aarch64_neon_uqrshrn : case Intrinsic :: aarch64_neon_uqshrn : case Intrinsic :: aarch64_neon_uqxtn : SimplifyAndSetOp ( & II , 0 , OrigDemandedElts , UndefElts ) ; break ; } return None ; } </s>

Can be used to implement target-specific instruction combining .


<s> const TargetRegisterClass * GBZ80RegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( RC == & GB :: R8_GPRRegClass || RC == & GB :: R8RegClass ) { return & GB :: R8RegClass ; } if ( RC == & GB :: R16_HLRegClass || RC == & GB :: R16_BCDERegClass || RC == & GB :: R16RegClass ) { return & GB :: R16RegClass ; } return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .


<s> MVT PPCTargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( Subtarget . hasSPE ( ) && VT == MVT :: f64 ) return MVT :: i32 ; return PPCTargetLowering :: getRegisterType ( Context , VT ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


<s> void AArch64PassConfig :: addPreEmitPass ( ) { if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Aggressive && EnableLoadStoreOpt ) addPass ( createAArch64LoadStoreOptimizationPass ( ) ) ; if ( EnableA53Fix835769 ) addPass ( createAArch64A53Fix835769 ( ) ) ; if ( EnableBranchTargets ) addPass ( createAArch64BranchTargetsPass ( ) ) ; if ( BranchRelaxation ) addPass ( & BranchRelaxationPassID ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardLongjmpPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCompressJumpTables ) addPass ( createAArch64CompressJumpTablesPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> TargetPassConfig * Tile64TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new Tile64PassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> static bool s390_cannot_force_const_mem ( rtx x ) { switch ( GET_CODE ( x ) ) { case CONST_INT : case CONST_DOUBLE : return false ; case LABEL_REF : return flag_pic != 0 ; case SYMBOL_REF : if ( tls_symbolic_operand ( x ) ) return true ; else return flag_pic != 0 ; case CONST : return s390_cannot_force_const_mem ( XEXP ( x , 0 ) ) ; case PLUS : case MINUS : return s390_cannot_force_const_mem ( XEXP ( x , 0 ) ) || s390_cannot_force_const_mem ( XEXP ( x , 1 ) ) ; case UNSPEC : switch ( XINT ( x , 1 ) ) { case UNSPEC_LTREL_OFFSET : case UNSPEC_GOT : case UNSPEC_GOTOFF : case UNSPEC_PLTOFF : case UNSPEC_TLSGD : case UNSPEC_TLSLDM : case UNSPEC_NTPOFF : case UNSPEC_DTPOFF : case UNSPEC_GOTNTPOFF : case UNSPEC_INDNTPOFF : return false ; case UNSPEC_INSN : return TARGET_CPU_ZARCH ; default : return true ; } break ; default : gcc_unreachable ( ) ; } } </s>

Determine if it 's legal to put X into the constant pool . This is not possible if X contains the address of a symbol that is not constant ( TLS ) or not known at final link time ( PIC ) .


<s> static bool ia64_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( FR_REGNO_P ( regno ) ) return ( GET_MODE_CLASS ( mode ) != MODE_CC && mode != BImode && mode != TFmode ) ; if ( PR_REGNO_P ( regno ) ) return mode == BImode || GET_MODE_CLASS ( mode ) == MODE_CC ; if ( GR_REGNO_P ( regno ) ) return mode != XFmode && mode != XCmode && mode != RFmode ; if ( AR_REGNO_P ( regno ) ) return mode == DImode ; if ( BR_REGNO_P ( regno ) ) return mode == DImode ; return false ; } </s>


<s> static bool pru_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { switch ( GET_MODE_SIZE ( mode ) ) { case 1 : return true ; case 2 : return ( regno % 4 ) <= 2 ; case 4 : return ( regno % 4 ) == 0 ; case 8 : return ( regno % 4 ) == 0 ; case 16 : return ( regno % 4 ) == 0 ; case 32 : return ( regno % 4 ) == 0 ; default : gcc_assert ( mode == BLKmode || mode == VOIDmode ) ; return ( regno % 4 ) == 0 ; } } </s>


<s> void X86IntelInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & OS ) { printInstFlags ( MI , OS ) ; if ( MI -> getOpcode ( ) == X86 :: DATA16_PREFIX && STI . getFeatureBits ( ) [ X86 :: Mode16Bit ] ) { OS << "\tdata32" ; } else if ( ! printAliasInstr ( MI , Address , OS ) && ! printVecCompareInstr ( MI , OS ) ) printInstruction ( MI , Address , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAnyX86InstComments ( MI , * CommentStream , MII ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool TL45AsmBackend :: mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> static int thumb2_legitimate_index_p ( machine_mode mode , rtx index , int strict_p ) { enum rtx_code code = GET_CODE ( index ) ; if ( TARGET_HARD_FLOAT && ( mode == SFmode || mode == DFmode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 256 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE ( mode ) ) { if ( ! TARGET_LDRD || mode != DImode ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; } if ( TARGET_NEON && VALID_NEON_QREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1016 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( TARGET_NEON && VALID_NEON_DREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( arm_address_register_rtx_p ( index , strict_p ) && ( GET_MODE_SIZE ( mode ) <= 4 ) ) return 1 ; if ( mode == DImode || mode == DFmode ) { if ( code == CONST_INT ) { HOST_WIDE_INT val = INTVAL ( index ) ; if ( TARGET_LDRD ) return IN_RANGE ( val , - 1020 , 1020 ) && ( val & 3 ) == 0 ; else return IN_RANGE ( val , - 255 , 4095 - 4 ) ; } else return 0 ; } if ( code == MULT ) { rtx xiop0 = XEXP ( index , 0 ) ; rtx xiop1 = XEXP ( index , 1 ) ; return ( ( arm_address_register_rtx_p ( xiop0 , strict_p ) && thumb2_index_mul_operand ( xiop1 ) ) || ( arm_address_register_rtx_p ( xiop1 , strict_p ) && thumb2_index_mul_operand ( xiop0 ) ) ) ; } else if ( code == ASHIFT ) { rtx op = XEXP ( index , 1 ) ; return ( arm_address_register_rtx_p ( XEXP ( index , 0 ) , strict_p ) && CONST_INT_P ( op ) && INTVAL ( op ) > 0 && INTVAL ( op ) <= 3 ) ; } return ( code == CONST_INT && INTVAL ( index ) < 4096 && INTVAL ( index ) > - 256 ) ; } </s>

Return nonzero if INDEX is a valid Thumb-2 address index operand .


<s> static MCSubtargetInfo * createMCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { return createJVMMCSubtargetInfoImpl ( TT , CPU , FS ) ; } </s>

createMCSubtargetInfo - Create a MCSubtargetInfo implementation .


<s> static void write_fn_proto ( std :: stringstream & s , bool is_defn , const char * name , const_tree decl , bool force_public = false ) { const char * replacement = nvptx_name_replacement ( name ) ; char * replaced_dots = NULL ; if ( replacement != name ) name = replacement ; else { replaced_dots = nvptx_replace_dot ( name ) ; if ( replaced_dots ) name = replaced_dots ; } if ( name [ 0 ] == '*' ) name ++ ; if ( is_defn ) write_fn_proto_1 ( s , false , name , decl , force_public ) ; write_fn_proto_1 ( s , is_defn , name , decl , force_public ) ; if ( replaced_dots ) XDELETE ( replaced_dots ) ; } </s>

Write a .func or .kernel declaration or definition along with a helper comment for use by ld . S is the stream to write to , DECL the decl for the function with name NAME . For definitions , emit a declaration too .


<s> void RISCVDAGToDAGISel :: PostprocessISelDAG ( ) { doPeepholeLoadStoreADDI ( ) ; } </s>

PostprocessISelDAG ( ) - This hook allows the target to hack on the graph right after selection .


<s> static rtx get_branch_target ( rtx branch ) { if ( CALL_P ( branch ) ) { rtx call ; call = XVECEXP ( PATTERN ( branch ) , 0 , 0 ) ; if ( GET_CODE ( call ) == SET ) call = SET_SRC ( call ) ; if ( GET_CODE ( call ) != CALL ) gcc_unreachable ( ) ; return XEXP ( XEXP ( call , 0 ) , 0 ) ; } return NULL_RTX ; } </s>

Returns 0 if we do n't want a hint for this branch . Otherwise return the rtx for the branch target .


<s> void BPFPassConfig :: addIRPasses ( ) { addPass ( createBPFCheckAndAdjustIR ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> bool s390_check_symref_alignment ( rtx addr , HOST_WIDE_INT alignment ) { HOST_WIDE_INT addend ; rtx symref ; if ( alignment < 2 || alignment > 8 ) return false ; if ( ! s390_loadrelative_operand_p ( addr , & symref , & addend ) ) return false ; if ( addend & ( alignment - 1 ) ) return false ; if ( GET_CODE ( symref ) == SYMBOL_REF ) { if ( SYMBOL_REF_ANCHOR_P ( symref ) ) { HOST_WIDE_INT block_offset = SYMBOL_REF_BLOCK_OFFSET ( symref ) ; unsigned int block_alignment = ( SYMBOL_REF_BLOCK ( symref ) -> alignment / BITS_PER_UNIT ) ; gcc_assert ( block_offset >= 0 ) ; return ( ( block_offset & ( alignment - 1 ) ) == 0 && block_alignment >= alignment ) ; } switch ( alignment ) { case 8 : return ! SYMBOL_FLAG_NOTALIGN8_P ( symref ) ; case 4 : return ! SYMBOL_FLAG_NOTALIGN4_P ( symref ) ; case 2 : return ! SYMBOL_FLAG_NOTALIGN2_P ( symref ) ; default : return false ; } } if ( GET_CODE ( symref ) == UNSPEC && alignment <= UNITS_PER_LONG ) return true ; return false ; } </s>

Return true if ADDR is SYMBOL_REF + addend with addend being a multiple of ALIGNMENT and the SYMBOL_REF being naturally aligned .


<s> const MCSection * PIC16TargetObjectFile :: getExplicitSectionGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler * Mang , const TargetMachine & TM ) const { assert ( GV -> hasSection ( ) ) ; if ( const GlobalVariable * GVar = cast < GlobalVariable > ( GV ) ) { std :: string SectName = GVar -> getSection ( ) ; std :: string AddrStr = "Address=" ; if ( SectName . compare ( 0 , AddrStr . length ( ) , AddrStr ) == 0 ) { std :: string SectAddr = SectName . substr ( AddrStr . length ( ) ) ; if ( SectAddr . compare ( "NEAR" ) == 0 ) return allocateSHARED ( GVar , Mang ) ; else return allocateAtGivenAddress ( GVar , SectAddr ) ; } return allocateInGivenSection ( GVar ) ; } return getPIC16DataSection ( GV -> getSection ( ) . c_str ( ) , UDATA ) ; } </s>

Targets should implement this method to assign a section to globals with an explicit section specfied .


<s>
void
CAHPMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
if
(
MI
.
getOpcode
(
)
==
CAHP
::
PseudoHLT
)
{
expandHlt
(
MI
,
OS
,
Fixups
,
STI
)
;
MCNumEmitted
+=
2
;
return
;
}
unsigned
Size
=
Desc
.
getSize
(
)
;
switch
(
Size
)
{
default
:
llvm_unreachable
(
"Unhandled encodeInstruction length!"
)
;
case
2
:
{
uint16_t
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
support
::
endian
::
write
<
uint16_t
>
(
OS
,
Bits
,
support
::
little
)
;
break
;
}
case
3
:
{
uint32_t
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
support
::
endian
::
write
<
uint16_t
>
(
OS
,
Bits
&
0xffff
,
support
::
little
)
;
OS
.
write
(
(
Bits
>>
16
)
&
0xff
)
;
break
;
}
}
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .


"  Preloading operand for insn %d into r%d\n"

Convert operand OP in INSN . We should handle memory operands and uninitialized registers . All other register uses are converted during registers conversion .


<s> const ARMSubtarget * ARMBaseTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < ARMSubtarget > ( TargetTriple , CPU , FS , * this , isLittle ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; ARMGISelActualAccessor * GISel = new ARMGISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new ARMCallLowering ( * I -> getTargetLowering ( ) ) ) ; GISel -> Legalizer . reset ( new ARMLegalizerInfo ( * I ) ) ; auto * RBI = new ARMRegisterBankInfo ( * I -> getRegisterInfo ( ) ) ; GISel -> InstSelector . reset ( new ARMInstructionSelector ( * I , * RBI ) ) ; GISel -> RegBankInfo . reset ( RBI ) ; I -> setGISelAccessor ( * GISel ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

ARM ARM ARM "target-cpu" "target-features" "use-soft-float" "true" "+soft-float" ",+soft-float" ARM ARM ARM ARM ARM ARM ARM


<s> static int aarch64_unspec_may_trap_p ( const_rtx x , unsigned flags ) { switch ( XINT ( x , 1 ) ) { case UNSPEC_GOTSMALLPIC : case UNSPEC_GOTSMALLPIC28K : case UNSPEC_GOTTINYPIC : return 0 ; default : break ; } return default_unspec_may_trap_p ( x , flags ) ; } </s>


<s> bool PPCTargetLowering :: shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; return ! ( BitSize == 0 || BitSize > 64 ) ; } </s>

Returns true if it is beneficial to convert a load of a constant to just the constant itself .


<s> bool AArch64TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { if ( Imm . isPosZero ( ) && ( VT == MVT :: f64 || VT == MVT :: f32 || VT == MVT :: f16 ) ) return true ; if ( VT == MVT :: f64 ) return AArch64_AM :: getFP64Imm ( Imm ) != - 1 ; else if ( VT == MVT :: f32 ) return AArch64_AM :: getFP32Imm ( Imm ) != - 1 ; return false ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> bool SIWholeQuadMode :: runOnMachineFunction ( MachineFunction & MF ) { Instructions . clear ( ) ; Blocks . clear ( ) ; LiveMaskQueries . clear ( ) ; LowerToCopyInstrs . clear ( ) ; LowerToMovInstrs . clear ( ) ; CallingConv = MF . getFunction ( ) . getCallingConv ( ) ; ST = & MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST -> getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; LIS = & getAnalysis < LiveIntervals > ( ) ; char GlobalFlags = analyzeFunction ( MF ) ; unsigned LiveMaskReg = 0 ; unsigned Exec = ST -> isWave32 ( ) ? AMDGPU :: EXEC_LO : AMDGPU :: EXEC ; if ( ! ( GlobalFlags & StateWQM ) ) { lowerLiveMaskQueries ( Exec ) ; if ( ! ( GlobalFlags & StateWWM ) && LowerToCopyInstrs . empty ( ) && LowerToMovInstrs . empty ( ) ) return ! LiveMaskQueries . empty ( ) ; } else { MachineBasicBlock & Entry = MF . front ( ) ; MachineBasicBlock :: iterator EntryMI = Entry . getFirstNonPHI ( ) ; if ( GlobalFlags & StateExact || ! LiveMaskQueries . empty ( ) ) { LiveMaskReg = MRI -> createVirtualRegister ( TRI -> getBoolRC ( ) ) ; MachineInstr * MI = BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( AMDGPU :: COPY ) , LiveMaskReg ) . addReg ( Exec ) ; LIS -> InsertMachineInstrInMaps ( * MI ) ; } lowerLiveMaskQueries ( LiveMaskReg ) ; if ( GlobalFlags == StateWQM ) { auto MI = BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( ST -> isWave32 ( ) ? AMDGPU :: S_WQM_B32 : AMDGPU :: S_WQM_B64 ) , Exec ) . addReg ( Exec ) ; LIS -> InsertMachineInstrInMaps ( * MI ) ; lowerCopyInstrs ( ) ; return true ; } } LLVM_DEBUG ( printInfo ( ) ) ; lowerCopyInstrs ( ) ; for ( auto BII : Blocks ) processBlock ( * BII . first , LiveMaskReg , BII . first == & * MF . begin ( ) ) ; if ( LiveMaskReg ) LIS -> createAndComputeVirtRegInterval ( LiveMaskReg ) ; LIS -> removeRegUnit ( * MCRegUnitIterator ( AMDGPU :: SCC , TRI ) ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool arc_legitimate_pic_addr_p ( rtx addr ) { if ( GET_CODE ( addr ) == LABEL_REF ) return true ; if ( GET_CODE ( addr ) != CONST ) return false ; addr = XEXP ( addr , 0 ) ; if ( GET_CODE ( addr ) == PLUS ) { if ( GET_CODE ( XEXP ( addr , 1 ) ) != CONST_INT ) return false ; addr = XEXP ( addr , 0 ) ; } if ( GET_CODE ( addr ) != UNSPEC || XVECLEN ( addr , 0 ) != 1 ) return false ; if ( XINT ( addr , 1 ) != ARC_UNSPEC_GOT && XINT ( addr , 1 ) != ARC_UNSPEC_GOTOFF && XINT ( addr , 1 ) != ARC_UNSPEC_GOTOFFPC && XINT ( addr , 1 ) != UNSPEC_TLS_GD && XINT ( addr , 1 ) != UNSPEC_TLS_IE ) return false ; if ( GET_CODE ( XVECEXP ( addr , 0 , 0 ) ) != SYMBOL_REF && GET_CODE ( XVECEXP ( addr , 0 , 0 ) ) != LABEL_REF ) return false ; return true ; } </s>

Return true if ADDR is a valid pic address . A valid pic address on arc should look like const ( unspec ( SYMBOL_REF/LABEL ) ( ARC_UNSPEC_GOTOFF/ARC_UNSPEC_GOT ) )


<s> virtual bool mayNeedRelaxation ( const MCInst & Inst ) const LLVM_OVERRIDE { return false ; } </s>


<s>
InstructionCost
RISCVTTIImpl
::
getArithmeticReductionCost
(
unsigned
Opcode
,
VectorType
*
VTy
,
Optional
<
FastMathFlags
>
FMF
,
TTI
::
TargetCostKind
CostKind
)
{
if
(
!
isa
<
FixedVectorType
>
(
VTy
)
)
return
BaseT
::
getArithmeticReductionCost
(
Opcode
,
VTy
,
FMF
,
CostKind
)
;
if
(
VTy
->
getElementType
(
)
->
isIntegerTy
(
1
)
)
return
BaseT
::
getArithmeticReductionCost
(
Opcode
,
VTy
,
FMF
,
CostKind
)
;
if
(
!
ST
->
useRVVForFixedLengthVectors
(
)
)
return
BaseT
::
getArithmeticReductionCost
(
Opcode
,
VTy
,
FMF
,
CostKind
)
;
if
(
VTy
->
getScalarSizeInBits
(
)
>
ST
->
getELEN
(
)
)
return
BaseT
::
getArithmeticReductionCost
(
Opcode
,
VTy
,
FMF
,
CostKind
)
;
int
ISD
=
TLI
->
InstructionOpcodeToISD
(
Opcode
)
;
assert
(
ISD
&&
"Invalid opcode"
)
;
if
(
ISD
!=
ISD
::
ADD
&&
ISD
!=
ISD
::
OR
&&
ISD
!=
ISD
::
XOR
&&
ISD
!=
ISD
::
AND
&&
ISD
!=
ISD
::
FADD
)
return
BaseT
::
getArithmeticReductionCost
(
Opcode
,
VTy
,
FMF
,
CostKind
)
;
InstructionCost
BaseCost
=
2
;
unsigned
VL
=
cast
<
FixedVectorType
>
(
VTy
)
->
getNumElements
(
)
;
std
::
pair
<
InstructionCost
,
MVT
>
LT
=
TLI
->
getTypeLegalizationCost
(
DL
,
VTy
)
;
if
(
TTI
::
requiresOrderedReduction
(
FMF
)
)
return
(
LT
.
first
1
)
+
BaseCost
+
VL
;
return
(
LT
.
first
1
)
+
BaseCost
+
Log2_32_Ceil
(
VL
)
;
}
</s>

Calculate the cost of vector reduction intrinsics .

RISCV
RISCV
1
"Invalid opcode"
ISD::ADD
ISD::OR
ISD::XOR
ISD::AND
ISD::FADD
2
1
1


"found bundle end marker without a matching "

"missing separator between operands or instructions"

ParseInstruction - Parse one assembly instruction .


<s> int pa_attr_length_indirect_call ( rtx_insn * insn ) { unsigned long distance = - 1 ; unsigned long total = IN_NAMED_SECTION_P ( cfun -> decl ) ? 0 : total_code_bytes ; if ( INSN_ADDRESSES_SET_P ( ) ) { distance = ( total + insn_current_reference_address ( insn ) ) ; if ( distance < total ) distance = - 1 ; } if ( TARGET_64BIT ) return 12 ; if ( TARGET_FAST_INDIRECT_CALLS ) return 8 ; if ( TARGET_PORTABLE_RUNTIME ) return 16 ; if ( ( TARGET_NO_SPACE_REGS || TARGET_PA_20 ) && ! optimize_size ) return 20 ; if ( ! TARGET_LONG_CALLS && ( ( TARGET_PA_20 && ! TARGET_SOM && distance < 7600000 ) || distance < MAX_PCREL17F_OFFSET ) ) return 8 ; if ( ! flag_pic ) return 12 ; if ( TARGET_NO_SPACE_REGS || TARGET_PA_20 ) return 20 ; if ( ! optimize_size ) return 36 ; return 20 ; } </s>

Return the attribute length of the indirect call instruction INSN . The length must match the code generated by output_indirect call . The returned length includes the delay slot . Currently , the delay slot of an indirect call sequence is not exposed and it is used by the sequence itself .


<s> enum avms_arg_type alpha_arg_type ( machine_mode mode ) { switch ( mode ) { case SFmode : return TARGET_FLOAT_VAX ? FF : FS ; case DFmode : return TARGET_FLOAT_VAX ? FD : FT ; default : return I64 ; } } </s>

Return the VMS argument type corresponding to MODE .


<s> static void frv_function_epilogue ( FILE * ) { frv_stack_cache = ( frv_stack_t * ) 0 ; memset ( & frv_ifcvt . tmp_reg , 0 , sizeof ( frv_ifcvt . tmp_reg ) ) ; BITMAP_FREE ( frv_ifcvt . scratch_insns_bitmap ) ; } </s>

Under frv , all of the work is done via frv_expand_epilogue , but this function provides a convenient place to do cleanup .


<s>
int
m32c_cannot_change_mode_class
(
machine_mode
from
,
machine_mode
to
,
int
rclass
)
{
int
rn
;
fprintf
(
stderr
,
"cannot change from %s to %s in %s\n"
,
mode_name
[
from
]
,
mode_name
[
to
]
,
class_names
[
rclass
]
)
;
for
(
rn
=
0
;
rn
<
FIRST_PSEUDO_REGISTER
;
rn
++
)
if
(
class_contents
[
rclass
]
[
0
]
&
(
1
<<
rn
)
)
if
(
!
m32c_hard_regno_ok
(
rn
,
to
)
)
return
1
;
if
(
to
==
QImode
)
return
(
class_contents
[
rclass
]
[
0
]
&
0x1ffa
)
;
if
(
class_contents
[
rclass
]
[
0
]
&
0x0005
&&
GET_MODE_SIZE
(
from
)
>
1
)
return
0
;
if
(
GET_MODE_SIZE
(
from
)
>
2
)
return
0
;
return
1
;
}
</s>

Implements CANNOT_CHANGE_MODE_CLASS . Only r0 and r1 can change to QI ( r0l , r1l ) because the chip does n't support QI ops on other registers ( well , it does on a0/a1 but if we let gcc do that , reload suffers ) . Otherwise , we allow changes to larger modes .


<s> TargetLowering :: ConstraintWeight ARM64TargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'x' : case 'w' : if ( type -> isFloatingPointTy ( ) || type -> isVectorTy ( ) ) weight = CW_Register ; break ; case 'z' : weight = CW_Constant ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s>
static
const
char
*
ia64_invalid_unary_op
(
int
op
,
const_tree
type
)
{
if
(
TYPE_MODE
(
type
)
==
RFmode
&&
op
!=
CONVERT_EXPR
&&
op
!=
ADDR_EXPR
)
return
N_
(
"invalid operation on %<__fpreg%>"
)
;
return
;
}
</s>

Return the diagnostic message string if the unary operation OP is not permitted on TYPE , NULL otherwise .


<s> void X86LinuxTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; } </s>

This method must be called before any actual lowering is done .


<s> void F2003fAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { F2003fMCInstLower MCInstLowering ( OutContext , * this ) ; MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { MCInst TmpInst ; MCInstLowering . Lower ( & * I , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } while ( ( ++ I != E ) && I -> isInsideBundle ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> SDValue PIC16TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { unsigned NumArgVals = Ins . size ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function * F = MF . getFunction ( ) ; std :: string FuncName = F -> getName ( ) ; ResetTmpOffsetMap ( ) ; InitReservedFrameCount ( F ) ; const char * tmpName = ESNames :: createESName ( PAN :: getArgsLabel ( FuncName ) ) ; SDValue ES = DAG . getTargetExternalSymbol ( tmpName , MVT :: i8 ) ; SDVTList VTs = DAG . getVTList ( MVT :: i8 , MVT :: Other ) ; SDValue BS = DAG . getConstant ( 1 , MVT :: i8 ) ; for ( unsigned i = 0 ; i < NumArgVals ; ++ i ) { SDValue Offset = DAG . getConstant ( i , MVT :: i8 ) ; SDValue PICLoad = DAG . getNode ( PIC16ISD :: PIC16LdArg , dl , VTs , Chain , ES , BS , Offset ) ; Chain = getChain ( PICLoad ) ; InVals . push_back ( PICLoad ) ; } return Chain ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> const TargetRegisterClass * X86RegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { if ( RC == & X86 :: GR8_NOREXRegClass ) return RC ; const X86Subtarget & Subtarget = MF . getSubtarget < X86Subtarget > ( ) ; const TargetRegisterClass * Super = RC ; TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case X86 :: FR32RegClassID : case X86 :: FR64RegClassID : if ( ! Subtarget . hasAVX512 ( ) && Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; break ; case X86 :: VR128RegClassID : case X86 :: VR256RegClassID : if ( ! Subtarget . hasVLX ( ) && Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; break ; case X86 :: VR128XRegClassID : case X86 :: VR256XRegClassID : if ( Subtarget . hasVLX ( ) && Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; break ; case X86 :: FR32XRegClassID : case X86 :: FR64XRegClassID : if ( Subtarget . hasAVX512 ( ) && Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; break ; case X86 :: GR8RegClassID : case X86 :: GR16RegClassID : case X86 :: GR32RegClassID : case X86 :: GR64RegClassID : case X86 :: RFP32RegClassID : case X86 :: RFP64RegClassID : case X86 :: RFP80RegClassID : case X86 :: VR512RegClassID : if ( Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; } Super = * I ++ ; } while ( Super ) ; return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .


<s> bool ComplexPatternFuncMutatesDAG ( ) const override { return true ; } </s>

Return true if complex patterns for this target can mutate the DAG .


<s> SDValue LC3TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InGlue , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { assert ( ! isVarArg && "Unsupported" ) ; SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_LC3 ) ; for ( auto & Loc : RVLocs ) { Chain = DAG . getCopyFromReg ( Chain , dl , Loc . getLocReg ( ) , Loc . getValVT ( ) , InGlue ) . getValue ( 1 ) ; InGlue = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .