<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { MachineFunction & MF = MIRBuilder . getMF ( ) ; LLT p0 = LLT :: pointer ( 0 , 64 ) ; LLT s64 = LLT :: scalar ( 64 ) ; if ( IsTailCall ) { Offset += FPDiff ; int FI = MF . getFrameInfo ( ) . CreateFixedObject ( Size , Offset , true ) ; Register FIReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildFrameIndex ( FIReg , FI ) ; MPO = MachinePointerInfo :: getFixedStack ( MF , FI ) ; return FIReg ; } Register SPReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildCopy ( SPReg , Register ( AArch64 :: SP ) ) ; Register OffsetReg = MRI . createGenericVirtualRegister ( s64 ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; Register AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildPtrAdd ( AddrReg , SPReg , OffsetReg ) ; MPO = MachinePointerInfo :: getStack ( MF , Offset ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> int sh_hard_regno_rename_ok ( unsigned int old_reg ATTRIBUTE_UNUSED , unsigned int new_reg ) { if ( sh_cfun_interrupt_handler_p ( ) && ! regs_ever_live [ new_reg ] ) return 0 ; return 1 ; } </s>

Return nonzero if register old_reg can be renamed to register new_reg .


<s> static MipsOperand * CreateReg ( unsigned RegNum , SMLoc S , SMLoc E ) { MipsOperand * Op = new MipsOperand ( k_Register ) ; Op -> Reg . RegNum = RegNum ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> unsigned getCommonDomains ( unsigned mask ) const { return AvailableDomains & mask ; } </s>

Return bitmask of domains that are available and in mask .


<s> static enum mips_int_mask mips_interrupt_mask ( tree type ) { tree attr = lookup_attribute ( "interrupt" , TYPE_ATTRIBUTES ( type ) ) ; tree args , cst ; const char * str ; if ( attr == NULL ) return INT_MASK_EIC ; args = TREE_VALUE ( attr ) ; if ( args == NULL ) return INT_MASK_EIC ; cst = TREE_VALUE ( args ) ; if ( strcmp ( TREE_STRING_POINTER ( cst ) , "eic" ) == 0 ) return INT_MASK_EIC ; str = TREE_STRING_POINTER ( cst ) ; gcc_assert ( strlen ( str ) == strlen ( "vector=sw0" ) ) ; if ( str [ 7 ] == 's' ) return ( enum mips_int_mask ) ( INT_MASK_SW0 + ( str [ 9 ] - '0' ) ) ; return ( enum mips_int_mask ) ( INT_MASK_HW0 + ( str [ 9 ] - '0' ) ) ; } </s>

Return the mask for the `` interrupt '' attribute .


<s> bool isBlockAddress ( ) const { return Kind == ARMCP :: CPBlockAddress ; } </s>

isBlockAddress - Tests if this is a MO_BlockAddress operand .


<s> rtx rs6000_emit_eqne ( machine_mode mode , rtx op1 , rtx op2 , rtx scratch ) { if ( op2 == const0_rtx ) return op1 ; if ( GET_CODE ( scratch ) == SCRATCH ) scratch = gen_reg_rtx ( mode ) ; if ( logical_operand ( op2 , mode ) ) emit_insn ( gen_rtx_SET ( scratch , gen_rtx_XOR ( mode , op1 , op2 ) ) ) ; else emit_insn ( gen_rtx_SET ( scratch , gen_rtx_PLUS ( mode , op1 , negate_rtx ( mode , op2 ) ) ) ) ; return scratch ; } </s>

Emit RTL that sets a register to zero if OP1 and OP2 are equal . SCRATCH can be used as that dest register . Return the dest register .


<s> bool PPCTargetLowering :: isTruncateFree ( EVT VT1 , EVT VT2 ) const { if ( ! VT1 . isInteger ( ) || ! VT2 . isInteger ( ) ) return false ; unsigned NumBits1 = VT1 . getSizeInBits ( ) ; unsigned NumBits2 = VT2 . getSizeInBits ( ) ; return NumBits1 == 64 && NumBits2 == 32 ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s> void TPCMCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( isLoopInst ( MI ) ) { LLVM_DEBUG ( fprintf ( stderr , "\n" ) ; dumpInstrNames ( MI , MCII ) ; ) ; encodeLoop ( MI , OS , getInstrBits ( MI , Fixups , STI ) , Fixups , STI ) ; return ; } LLVM_DEBUG ( fprintf ( stderr , "\n" ) ; dumpInstrNames ( MI , MCII ) ; ) ; TPCInstrBits Bits ; fillInstrBits ( MI , Fixups , Bits , STI , false , true ) ; emitBits ( OS , & Bits , STI ) ; } </s>

Encode the given Inst to bytes and append to CB .


<s> bool AlphaCodeEmitter :: runOnMachineFunction ( MachineFunction & MF ) { II = ( ( AlphaTargetMachine & ) MF . getTarget ( ) ) . getInstrInfo ( ) ; do { MCE . startFunction ( MF ) ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) emitBasicBlock ( * I ) ; } while ( MCE . finishFunction ( MF ) ) ; return false ; } </s>

runOnMachineFunction - Emit the function body .


"PPC DAG preprocessing replacing:\nOld:    "

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


"PowerPC DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> SDValue AArch64TargetLowering :: BuildSDIVPow2 ( SDNode * N , const APInt & Divisor , SelectionDAG & DAG , std :: vector < SDNode * > * Created ) const { EVT VT = N -> getValueType ( 0 ) ; if ( ( VT != MVT :: i32 && VT != MVT :: i64 ) || ! ( Divisor . isPowerOf2 ( ) || ( - Divisor ) . isPowerOf2 ( ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( 0 ) ; unsigned Lg2 = Divisor . countTrailingZeros ( ) ; SDValue Zero = DAG . getConstant ( 0 , DL , VT ) ; SDValue Pow2MinusOne = DAG . getConstant ( ( 1ULL << Lg2 ) - 1 , DL , VT ) ; SDValue CCVal ; SDValue Cmp = getAArch64Cmp ( N0 , Zero , ISD :: SETLT , CCVal , DAG , DL ) ; SDValue Add = DAG . getNode ( ISD :: ADD , DL , VT , N0 , Pow2MinusOne ) ; SDValue CSel = DAG . getNode ( AArch64ISD :: CSEL , DL , VT , Add , N0 , CCVal , Cmp ) ; if ( Created ) { Created -> push_back ( Cmp . getNode ( ) ) ; Created -> push_back ( Add . getNode ( ) ) ; Created -> push_back ( CSel . getNode ( ) ) ; } SDValue SRA = DAG . getNode ( ISD :: SRA , DL , VT , CSel , DAG . getConstant ( Lg2 , DL , MVT :: i64 ) ) ; if ( Divisor . isNonNegative ( ) ) return SRA ; if ( Created ) Created -> push_back ( SRA . getNode ( ) ) ; return DAG . getNode ( ISD :: SUB , DL , VT , DAG . getConstant ( 0 , DL , VT ) , SRA ) ; } </s>

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators .


<s>
static
const
char
*
toString
(
const
Type
*
Ty
,
bool
hasAddr64
)
{
switch
(
Ty
->
getTypeID
(
)
)
{
default
:
break
;
case
Type
::
PointerTyID
:
return
hasAddr64
"i64"
:
"i32"
;
case
Type
::
FloatTyID
:
return
"f32"
;
case
Type
::
DoubleTyID
:
return
"f64"
;
case
Type
::
IntegerTyID
:
switch
(
Ty
->
getIntegerBitWidth
(
)
)
{
case
8
:
return
"i8"
;
case
16
:
return
"i16"
;
case
32
:
return
"i32"
;
case
64
:
return
"i64"
;
default
:
break
;
}
}
DEBUG
(
dbgs
(
)
<<
"Invalid type "
;
Ty
->
print
(
dbgs
(
)
)
;
dbgs
(
)
<<
'\n'
)
;
llvm_unreachable
(
"invalid type"
)
;
return
"<invalid>"
;
}
</s>

Convert to a decimal representation in a string .


<s> bool AMDGPUInstructionSelector :: select ( MachineInstr & I ) const { if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) return true ; switch ( I . getOpcode ( ) ) { default : break ; case TargetOpcode :: G_ADD : return selectG_ADD ( I ) ; case TargetOpcode :: G_CONSTANT : return selectG_CONSTANT ( I ) ; case TargetOpcode :: G_GEP : return selectG_GEP ( I ) ; case TargetOpcode :: G_LOAD : return selectG_LOAD ( I ) ; case TargetOpcode :: G_STORE : return selectG_STORE ( I ) ; } return false ; } </s>

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s> bool SNESPassConfig :: addInstSelector ( ) { addPass ( createSNESISelDag ( getSNESTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> BitVector Z80RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const Z80FrameLowering * TFI = getFrameLowering ( MF ) ; Reserved . set ( Z80 :: SPS ) ; Reserved . set ( Z80 :: SPL ) ; Reserved . set ( Z80 :: PC ) ; for ( MCSubRegIterator I ( Z80 :: UIX , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> outliner :: OutlinedFunction RISCVInstrInfo :: getOutliningCandidateInfo ( std :: vector < outliner :: Candidate > & RepeatedSequenceLocs ) const { auto CannotInsertCall = [ ] ( outliner :: Candidate & C ) { const TargetRegisterInfo * TRI = C . getMF ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; C . initLRU ( * TRI ) ; LiveRegUnits LRU = C . LRU ; return ! LRU . available ( RISCV :: X5 ) ; } ; llvm :: erase_if ( RepeatedSequenceLocs , CannotInsertCall ) ; if ( RepeatedSequenceLocs . size ( ) < 2 ) return outliner :: OutlinedFunction ( ) ; unsigned SequenceSize = 0 ; auto I = RepeatedSequenceLocs [ 0 ] . front ( ) ; auto E = std :: next ( RepeatedSequenceLocs [ 0 ] . back ( ) ) ; for ( ; I != E ; ++ I ) SequenceSize += getInstSizeInBytes ( * I ) ; unsigned CallOverhead = 8 ; for ( auto & C : RepeatedSequenceLocs ) C . setCallInfo ( MachineOutlinerDefault , CallOverhead ) ; unsigned FrameOverhead = 4 ; if ( RepeatedSequenceLocs [ 0 ] . getMF ( ) -> getSubtarget ( ) . getFeatureBits ( ) [ RISCV :: FeatureStdExtC ] ) FrameOverhead = 2 ; return outliner :: OutlinedFunction ( RepeatedSequenceLocs , SequenceSize , FrameOverhead , MachineOutlinerDefault ) ; } </s>

Returns a outliner : :OutlinedFunction struct containing target-specific information for a set of outlining candidates .


<s> bool expand_a_shift ( machine_mode mode , enum rtx_code code , rtx operands [ ] ) { switch ( h8sx_classify_shift ( mode , code , operands [ 2 ] ) ) { case H8SX_SHIFT_BINARY : operands [ 1 ] = force_reg ( mode , operands [ 1 ] ) ; return false ; case H8SX_SHIFT_UNARY : return false ; case H8SX_SHIFT_NONE : break ; } emit_move_insn ( copy_rtx ( operands [ 0 ] ) , operands [ 1 ] ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , gen_rtx_SET ( VOIDmode , copy_rtx ( operands [ 0 ] ) , gen_rtx_fmt_ee ( code , mode , copy_rtx ( operands [ 0 ] ) , operands [ 2 ] ) ) , gen_rtx_CLOBBER ( VOIDmode , gen_rtx_SCRATCH ( QImode ) ) ) ) ) ; return true ; } </s>

Called from the .md file to emit code to do shifts . Returns a boolean indicating success ( currently this is always TRUE ) .


<s> std :: pair < unsigned , unsigned > AMDGPUSubtarget :: getWavesPerEU ( const Function & F ) const { std :: pair < unsigned , unsigned > Default ( 1 , getMaxWavesPerEU ( ) ) ; std :: pair < unsigned , unsigned > FlatWorkGroupSizes = getFlatWorkGroupSizes ( F ) ; unsigned MinImpliedByFlatWorkGroupSize = getWavesPerEUForWorkGroup ( FlatWorkGroupSizes . second ) ; bool RequestedFlatWorkGroupSize = false ; if ( F . hasFnAttribute ( "amdgpu-flat-work-group-size" ) ) { Default . first = MinImpliedByFlatWorkGroupSize ; RequestedFlatWorkGroupSize = true ; } std :: pair < unsigned , unsigned > Requested = AMDGPU :: getIntegerPairAttribute ( F , "amdgpu-waves-per-eu" , Default , true ) ; if ( Requested . second && Requested . first > Requested . second ) return Default ; if ( Requested . first < getMinWavesPerEU ( ) || Requested . first > getMaxWavesPerEU ( ) ) return Default ; if ( Requested . second > getMaxWavesPerEU ( ) ) return Default ; if ( RequestedFlatWorkGroupSize && Requested . first < MinImpliedByFlatWorkGroupSize ) return Default ; return Requested ; } </s>

Overload which uses the specified values for the flat work group sizes , rather than querying the function itself .

AMDGPU AMDGPU 1 "amdgpu-flat-work-group-size" AMDGPU::getIntegerPairAttribute "amdgpu-waves-per-eu"


<s> static inline bool pdp11_saved_regno ( unsigned regno ) { return ! call_used_regs [ regno ] && df_regs_ever_live_p ( regno ) ; } </s>

A helper function to determine if REGNO should be saved in the current function 's stack frame .


<s> SMLoc getStartLoc ( ) const { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


"InlineAsmMemoryOperand 'v' constraint not handled."

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


"***** Machine Function before Domain Reassignment *****\n"

"***** Machine Function after Domain Reassignment *****\n"


<s> static rtx frv_legitimize_target ( enum insn_code icode , rtx target ) { enum machine_mode mode = insn_data [ icode ] . operand [ 0 ] . mode ; if ( ! target || GET_MODE ( target ) != mode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , mode ) ) return gen_reg_rtx ( mode ) ; else return target ; } </s>

Return a legitimate rtx for instruction ICODE 's return value . Use TARGET if it 's not null , has the right mode , and satisfies operand 0 's predicate .


<s>
static
void
riscv_file_start
(
void
)
{
default_file_start
(
)
;
fprintf
(
asm_out_file
,
"\t.option %spic\n"
,
(
flag_pic
""
:
"no"
)
)
;
if
(
!
riscv_mrelax
)
fprintf
(
asm_out_file
,
"\t.option norelax\n"
)
;
}
</s>

riscv
"\t.option %spic\n"
""
"no"
"\t.option norelax\n"


<s> rtx arm_gen_compare_reg ( enum rtx_code code , rtx x , rtx y , rtx scratch ) { machine_mode mode ; rtx cc_reg ; int dimode_comparison = GET_MODE ( x ) == DImode || GET_MODE ( y ) == DImode ; if ( dimode_comparison && ! REG_P ( x ) ) x = force_reg ( DImode , x ) ; mode = SELECT_CC_MODE ( code , x , y ) ; cc_reg = gen_rtx_REG ( mode , CC_REGNUM ) ; if ( dimode_comparison && mode != CC_CZmode ) { rtx clobber , set ; if ( mode == CC_Zmode && y != const0_rtx ) { gcc_assert ( ! reload_completed ) ; x = expand_binop ( DImode , xor_optab , x , y , NULL_RTX , 0 , OPTAB_WIDEN ) ; y = const0_rtx ; } if ( reload_completed ) gcc_assert ( scratch != NULL && GET_MODE ( scratch ) == SImode ) ; else scratch = gen_rtx_SCRATCH ( SImode ) ; clobber = gen_rtx_CLOBBER ( VOIDmode , scratch ) ; set = gen_rtx_SET ( cc_reg , gen_rtx_COMPARE ( mode , x , y ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set , clobber ) ) ) ; } else emit_set_insn ( cc_reg , gen_rtx_COMPARE ( mode , x , y ) ) ; return cc_reg ; } </s>

X and Y are two things to compare using CODE . Emit the compare insn and return the rtx for register 0 in the proper mode . FP means this is a floating point compare : I do n't think that it is needed on the arm .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < LC2200Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>


<s> bool isToken ( ) const override { return Kind == Token ; } </s>


<s> Value * RISCVTargetLowering :: emitMaskedAtomicRMWIntrinsic ( IRBuilder < > & Builder , AtomicRMWInst * AI , Value * AlignedAddr , Value * Incr , Value * Mask , Value * ShiftAmt , AtomicOrdering Ord ) const { unsigned XLen = Subtarget . getXLen ( ) ; Value * Ordering = Builder . getIntN ( XLen , static_cast < uint64_t > ( AI -> getOrdering ( ) ) ) ; Type * Tys [ ] = { AlignedAddr -> getType ( ) } ; Function * LrwOpScwLoop = Intrinsic :: getDeclaration ( AI -> getModule ( ) , getIntrinsicForMaskedAtomicRMWBinOp ( XLen , AI -> getOperation ( ) ) , Tys ) ; if ( XLen == 64 ) { Incr = Builder . CreateSExt ( Incr , Builder . getInt64Ty ( ) ) ; Mask = Builder . CreateSExt ( Mask , Builder . getInt64Ty ( ) ) ; ShiftAmt = Builder . CreateSExt ( ShiftAmt , Builder . getInt64Ty ( ) ) ; } Value * Result ; if ( AI -> getOperation ( ) == AtomicRMWInst :: Min || AI -> getOperation ( ) == AtomicRMWInst :: Max ) { const DataLayout & DL = AI -> getModule ( ) -> getDataLayout ( ) ; unsigned ValWidth = DL . getTypeStoreSizeInBits ( AI -> getValOperand ( ) -> getType ( ) ) ; Value * SextShamt = Builder . CreateSub ( Builder . getIntN ( XLen , XLen - ValWidth ) , ShiftAmt ) ; Result = Builder . CreateCall ( LrwOpScwLoop , { AlignedAddr , Incr , Mask , SextShamt , Ordering } ) ; } else { Result = Builder . CreateCall ( LrwOpScwLoop , { AlignedAddr , Incr , Mask , Ordering } ) ; } if ( XLen == 64 ) Result = Builder . CreateTrunc ( Result , Builder . getInt32Ty ( ) ) ; return Result ; } </s>

Perform a masked atomicrmw using a target-specific intrinsic .


<s> static tree ix86_canonical_va_list_type ( tree type ) { tree wtype , htype ; if ( TREE_CODE ( type ) == MEM_REF ) type = TREE_TYPE ( type ) ; else if ( POINTER_TYPE_P ( type ) && POINTER_TYPE_P ( TREE_TYPE ( type ) ) ) type = TREE_TYPE ( type ) ; else if ( POINTER_TYPE_P ( type ) && TREE_CODE ( TREE_TYPE ( type ) ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; if ( TARGET_64BIT && va_list_type_node != NULL_TREE ) { wtype = va_list_type_node ; gcc_assert ( wtype != NULL_TREE ) ; htype = type ; if ( TREE_CODE ( wtype ) == ARRAY_TYPE ) { if ( TREE_CODE ( htype ) == ARRAY_TYPE || POINTER_TYPE_P ( htype ) ) { wtype = TREE_TYPE ( wtype ) ; htype = TREE_TYPE ( htype ) ; } } if ( TYPE_MAIN_VARIANT ( wtype ) == TYPE_MAIN_VARIANT ( htype ) ) return va_list_type_node ; wtype = sysv_va_list_type_node ; gcc_assert ( wtype != NULL_TREE ) ; htype = type ; if ( TREE_CODE ( wtype ) == ARRAY_TYPE ) { if ( TREE_CODE ( htype ) == ARRAY_TYPE || POINTER_TYPE_P ( htype ) ) { wtype = TREE_TYPE ( wtype ) ; htype = TREE_TYPE ( htype ) ; } } if ( TYPE_MAIN_VARIANT ( wtype ) == TYPE_MAIN_VARIANT ( htype ) ) return sysv_va_list_type_node ; wtype = ms_va_list_type_node ; gcc_assert ( wtype != NULL_TREE ) ; htype = type ; if ( TREE_CODE ( wtype ) == ARRAY_TYPE ) { if ( TREE_CODE ( htype ) == ARRAY_TYPE || POINTER_TYPE_P ( htype ) ) { wtype = TREE_TYPE ( wtype ) ; htype = TREE_TYPE ( htype ) ; } } if ( TYPE_MAIN_VARIANT ( wtype ) == TYPE_MAIN_VARIANT ( htype ) ) return ms_va_list_type_node ; return NULL_TREE ; } return std_canonical_va_list_type ( type ) ; } </s>

Returns the canonical va_list type specified by TYPE . If there is no valid TYPE provided , it return NULL_TREE .


<s> WebAssemblySubtarget & WebAssemblySubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { LLVM_DEBUG ( llvm :: dbgs ( ) << "initializeSubtargetDependencies\n" ) ; if ( CPU . empty ( ) ) CPU = "generic" ; ParseSubtargetFeatures ( CPU , CPU , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .

WebAssembly WebAssembly WebAssembly "initializeSubtargetDependencies\n" "generic"


<s> static void aarch64_emit_sve_inverted_cond ( rtx target , rtx ptrue , rtx_code code , rtx op0 , rtx op1 ) { machine_mode pred_mode = GET_MODE ( ptrue ) ; rtx tmp = gen_reg_rtx ( pred_mode ) ; aarch64_emit_sve_ptrue_op ( tmp , ptrue , gen_rtx_fmt_ee ( code , pred_mode , op0 , op1 ) ) ; aarch64_emit_unop ( target , one_cmpl_optab , tmp ) ; } </s>

Emit the SVE equivalent of : ( set TMP ( CODE OP0 OP1 ) ) ( set TARGET ( not TMP ) ) PTRUE is an all-true predicate with the same mode as TARGET .


<s> static int sparc_register_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t from , reg_class_t to ) { bool need_memory = false ; if ( from == NO_REGS || to == NO_REGS ) return 100 ; if ( from == FPCC_REGS || to == FPCC_REGS ) need_memory = true ; else if ( ( FP_REG_CLASS_P ( from ) && general_or_i64_p ( to ) ) || ( general_or_i64_p ( from ) && FP_REG_CLASS_P ( to ) ) ) { if ( TARGET_VIS3 ) { int size = GET_MODE_SIZE ( mode ) ; if ( size == 8 || size == 4 ) { if ( ! TARGET_ARCH32 || size == 4 ) return 4 ; else return 6 ; } } need_memory = true ; } if ( need_memory ) { if ( sparc_cpu == PROCESSOR_ULTRASPARC || sparc_cpu == PROCESSOR_ULTRASPARC3 || sparc_cpu == PROCESSOR_NIAGARA || sparc_cpu == PROCESSOR_NIAGARA2 || sparc_cpu == PROCESSOR_NIAGARA3 || sparc_cpu == PROCESSOR_NIAGARA4 || sparc_cpu == PROCESSOR_NIAGARA7 ) return 12 ; return 6 ; } return 2 ; } </s>


<s> bool restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const override { return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool OptimizePICCall :: runOnMachineFunction ( MachineFunction & F ) { if ( F . getTarget ( ) . getSubtarget < MipsSubtarget > ( ) . inMips16Mode ( ) ) return false ; MachineDominatorTree * MDT = & getAnalysis < MachineDominatorTree > ( ) ; bool Changed = false ; SmallVector < MBBInfo , 8 > WorkList ( 1 , MBBInfo ( MDT -> getRootNode ( ) ) ) ; while ( ! WorkList . empty ( ) ) { MBBInfo & MBBI = WorkList . back ( ) ; if ( MBBI . isVisited ( ) ) { MBBI . postVisit ( ) ; WorkList . pop_back ( ) ; continue ; } MBBI . preVisit ( ScopedHT ) ; Changed |= visitNode ( MBBI ) ; const MachineDomTreeNode * Node = MBBI . getNode ( ) ; const std :: vector < MachineDomTreeNode * > & Children = Node -> getChildren ( ) ; WorkList . append ( Children . begin ( ) , Children . end ( ) ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool isMem ( ) const override { return Kind == k_Memri ; } </s>


<s> static bool arm_fdpic_local_funcdesc_p ( rtx fnx ) { tree fn ; enum symbol_visibility vis ; bool ret ; if ( ! TARGET_FDPIC ) return true ; if ( ! SYMBOL_REF_LOCAL_P ( fnx ) ) return false ; fn = SYMBOL_REF_DECL ( fnx ) ; if ( ! fn ) return false ; vis = DECL_VISIBILITY ( fn ) ; if ( vis == VISIBILITY_PROTECTED ) DECL_VISIBILITY ( fn ) = VISIBILITY_DEFAULT ; ret = default_binds_local_p_1 ( fn , flag_pic ) ; DECL_VISIBILITY ( fn ) = vis ; return ret ; } </s>

Test whether a local function descriptor is canonical , i.e. , whether we can use GOTOFFFUNCDESC to compute the address of the function .


<s> static void aarch64_emit_sve_invert_fp_cond ( rtx target , rtx_code code , rtx pred , bool known_ptrue_p , rtx op0 , rtx op1 ) { machine_mode pred_mode = GET_MODE ( pred ) ; rtx tmp = gen_reg_rtx ( pred_mode ) ; aarch64_emit_sve_fp_cond ( tmp , code , pred , known_ptrue_p , op0 , op1 ) ; aarch64_emit_unop ( target , one_cmpl_optab , tmp ) ; } </s>

Emit the SVE equivalent of : ( set TMP ( unspec [ PRED KNOWN_PTRUE_P OP0 OP1 ] UNSPEC_COND_ < X > ) ) ( set TARGET ( not TMP ) ) where < X > is the operation associated with comparison CODE . KNOWN_PTRUE_P is true if PRED is known to be a PTRUE .


"Outgoing arguments should be part of the frame"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static int cris_register_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t from , reg_class_t to ) { if ( reg_classes_intersect_p ( from , SPECIAL_REGS ) && reg_classes_intersect_p ( to , SPECIAL_REGS ) ) return 7 ; if ( reg_classes_intersect_p ( from , SPECIAL_REGS ) || reg_classes_intersect_p ( to , SPECIAL_REGS ) ) return 3 ; return 2 ; } </s>

Worker function for TARGET_REGISTER_MOVE_COST .


<s>
CCAssignFn
*
AArch64TargetLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
const
{
switch
(
CC
)
{
default
:
report_fatal_error
(
"Unsupported calling convention."
)
;
case
CallingConv
::
WebKit_JS
:
return
CC_AArch64_WebKit_JS
;
case
CallingConv
::
GHC
:
return
CC_AArch64_GHC
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
case
CallingConv
::
PreserveMost
:
case
CallingConv
::
CXX_FAST_TLS
:
case
CallingConv
::
Swift
:
if
(
Subtarget
->
isTargetWindows
(
)
&&
IsVarArg
)
return
CC_AArch64_Win64_VarArg
;
if
(
!
Subtarget
->
isTargetDarwin
(
)
)
return
CC_AArch64_AAPCS
;
return
IsVarArg
CC_AArch64_DarwinPCS_VarArg
:
CC_AArch64_DarwinPCS
;
case
CallingConv
::
Win64
:
return
IsVarArg
CC_AArch64_Win64_VarArg
:
CC_AArch64_AAPCS
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> void reset ( ) { ArgType = 0 ; VectorSize = 1 ; PtrKind = 0 ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s> void PPCFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const PPCRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; SavedRegs . reset ( PPC :: VSRp26 ) ; SavedRegs . reset ( PPC :: VSRp27 ) ; SavedRegs . reset ( PPC :: VSRp28 ) ; SavedRegs . reset ( PPC :: VSRp29 ) ; SavedRegs . reset ( PPC :: VSRp30 ) ; SavedRegs . reset ( PPC :: VSRp31 ) ; PPCFunctionInfo * FI = MF . getInfo < PPCFunctionInfo > ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; SavedRegs . reset ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; const bool isPPC64 = Subtarget . isPPC64 ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( ) ; FPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int BPSI = FI -> getBasePointerSaveIndex ( ) ; if ( ! BPSI && RegInfo -> hasBasePointer ( MF ) ) { int BPOffset = getBasePointerSaveOffset ( ) ; BPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , BPOffset , true ) ; FI -> setBasePointerSaveIndex ( BPSI ) ; } if ( FI -> usesPICBase ( ) ) { int PBPSI = MFI . CreateFixedObject ( 4 , - 8 , true ) ; FI -> setPICBasePointerSaveIndex ( PBPSI ) ; } if ( needsFP ( MF ) ) SavedRegs . reset ( isPPC64 ? PPC :: X31 : PPC :: R31 ) ; if ( RegInfo -> hasBasePointer ( MF ) ) SavedRegs . reset ( RegInfo -> getBaseRegister ( MF ) ) ; if ( FI -> usesPICBase ( ) ) SavedRegs . reset ( PPC :: R30 ) ; int TCSPDelta = 0 ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < 0 ) { MFI . CreateFixedObject ( - 1 * TCSPDelta , TCSPDelta , true ) ; } if ( ( SavedRegs . test ( PPC :: CR2 ) || SavedRegs . test ( PPC :: CR3 ) || SavedRegs . test ( PPC :: CR4 ) ) ) { const uint64_t SpillSize = 4 ; const int64_t SpillOffset = Subtarget . isPPC64 ( ) ? 8 : Subtarget . isAIXABI ( ) ? 4 : - 4 ; int FrameIdx = MFI . CreateFixedObject ( SpillSize , SpillOffset , true , false ) ; FI -> setCRSpillFrameIndex ( FrameIdx ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> bool MipsCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) { return false ; } for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( Arg . getType ( ) ) ) return false ; } MachineFunction & MF = MIRBuilder . getMF ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const MipsTargetLowering & TLI = * getTLI < MipsTargetLowering > ( ) ; SmallVector < ArgInfo , 8 > ArgInfos ; SmallVector < unsigned , 8 > OrigArgIndices ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ i ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , i + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( AInfo , i , ArgInfos , OrigArgIndices ) ; ++ i ; } SmallVector < ISD :: InputArg , 8 > Ins ; subTargetRegTypeForCallingConv ( F , ArgInfos , OrigArgIndices , Ins ) ; SmallVector < CCValAssign , 16 > ArgLocs ; MipsCCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; const MipsTargetMachine & TM = static_cast < const MipsTargetMachine & > ( MF . getTarget ( ) ) ; const MipsABIInfo & ABI = TM . getABI ( ) ; CCInfo . AllocateStack ( ABI . GetCalleeAllocdArgSizeInBytes ( F . getCallingConv ( ) ) , 1 ) ; CCInfo . AnalyzeFormalArguments ( Ins , TLI . CCAssignFnForCall ( ) ) ; setLocInfo ( ArgLocs , Ins ) ; IncomingValueHandler Handler ( MIRBuilder , MF . getRegInfo ( ) ) ; if ( ! Handler . handle ( ArgLocs , ArgInfos ) ) return false ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> SMLoc getEndLoc ( ) const { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> SDValue ARMTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : return PerformADDCombine ( N , DCI ) ; case ISD :: SUB : return PerformSUBCombine ( N , DCI ) ; case ARMISD :: VMOVRRD : return PerformVMOVRRDCombine ( N , DCI ) ; case ISD :: INTRINSIC_WO_CHAIN : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DCI . DAG , Subtarget ) ; case ISD :: SIGN_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: ANY_EXTEND : return PerformExtendCombine ( N , DCI . DAG , Subtarget ) ; case ISD :: SELECT_CC : return PerformSELECT_CCCombine ( N , DCI . DAG , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> bool X86TTIImpl :: isLegalMaskedLoad ( Type * DataTy , MaybeAlign Alignment ) { if ( ! ST -> hasAVX ( ) ) return false ; if ( isa < VectorType > ( DataTy ) && cast < VectorType > ( DataTy ) -> getNumElements ( ) == 1 ) return false ; Type * ScalarTy = DataTy -> getScalarType ( ) ; if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == 32 || IntWidth == 64 || ( ( IntWidth == 8 || IntWidth == 16 ) && ST -> hasBWI ( ) ) ; } </s>

Return true if the target supports masked load .


"ATOMIC_FENCE is not yet supported in non-emscripten OSes"

Main hook for targets to transform nodes into machine nodes .


<s>
static
bool
avr_assemble_integer
(
rtx
x
,
unsigned
int
size
,
int
aligned_p
)
{
if
(
size
==
POINTER_SIZE
/
BITS_PER_UNIT
&&
aligned_p
&&
text_segment_operand
(
x
,
VOIDmode
)
)
{
fputs
(
"\t.word\tgs("
,
asm_out_file
)
;
output_addr_const
(
asm_out_file
,
x
)
;
fputs
(
")\n"
,
asm_out_file
)
;
return
true
;
}
else
if
(
GET_MODE
(
x
)
==
PSImode
)
{
fputs
(
"\t.byte\tlo8("
,
asm_out_file
)
;
output_addr_const
(
asm_out_file
,
x
)
;
fputs
(
")"
ASM_COMMENT_START
"need binutils PR13503\n"
,
asm_out_file
)
;
fputs
(
"\t.byte\thi8("
,
asm_out_file
)
;
output_addr_const
(
asm_out_file
,
x
)
;
fputs
(
")"
ASM_COMMENT_START
"need binutils PR13503\n"
,
asm_out_file
)
;
fputs
(
"\t.byte\thh8("
,
asm_out_file
)
;
output_addr_const
(
asm_out_file
,
x
)
;
fputs
(
")"
ASM_COMMENT_START
"need binutils PR13503\n"
,
asm_out_file
)
;
return
true
;
}
else
if
(
CONST_FIXED_P
(
x
)
)
{
for
(
unsigned
n
=
0
;
n
<
size
;
n
++
)
{
rtx
xn
=
simplify_gen_subreg
(
QImode
,
x
,
GET_MODE
(
x
)
,
n
)
;
default_assemble_integer
(
xn
,
1
,
aligned_p
)
;
}
return
true
;
}
if
(
AVR_TINY
&&
avr_address_tiny_pm_p
(
x
)
)
{
x
=
plus_constant
(
Pmode
,
x
,
avr_arch
->
flash_pm_offset
)
;
}
return
default_assemble_integer
(
x
,
size
,
aligned_p
)
;
}
</s>

Target hook for assembling integer objects . The AVR version needs special handling for references to certain labels .


<s>
bool
PPCCallLowering
::
lowerReturn
(
MachineIRBuilder
&
MIRBuilder
,
const
Value
*
Val
,
ArrayRef
<
Register
>
VRegs
,
Register
SwiftErrorVReg
)
const
{
assert
(
(
(
Val
&&
!
VRegs
.
empty
(
)
)
||
(
!
Val
&&
VRegs
.
empty
(
)
)
)
&&
"Return value without a vreg"
)
;
if
(
VRegs
.
size
(
)
>
0
)
return
false
;
MIRBuilder
.
buildInstr
(
PPC
::
BLR8
)
;
return
true
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> static void gcn_goacc_reduction_setup ( gcall * call ) { gimple_stmt_iterator gsi = gsi_for_stmt ( call ) ; tree lhs = gimple_call_lhs ( call ) ; tree var = gimple_call_arg ( call , 2 ) ; int level = TREE_INT_CST_LOW ( gimple_call_arg ( call , 3 ) ) ; gimple_seq seq = NULL ; push_gimplify_context ( true ) ; if ( level != GOMP_DIM_GANG ) { tree ref_to_res = gimple_call_arg ( call , 1 ) ; if ( ! integer_zerop ( ref_to_res ) ) var = build_simple_mem_ref ( ref_to_res ) ; } if ( level == GOMP_DIM_WORKER ) { tree var_type = TREE_TYPE ( var ) ; tree offset = gimple_call_arg ( call , 5 ) ; tree decl = gcn_goacc_get_worker_red_decl ( var_type , TREE_INT_CST_LOW ( offset ) ) ; gimplify_assign ( decl , var , & seq ) ; } if ( lhs ) gimplify_assign ( lhs , var , & seq ) ; pop_gimplify_context ( NULL ) ; gsi_replace_with_seq ( & gsi , seq , true ) ; } </s>


<s> static unsigned int mips_machine_reorg2 ( void ) { mips_reorg_process_insns ( ) ; if ( ! TARGET_MIPS16 && TARGET_EXPLICIT_RELOCS && TUNE_MIPS4130 && TARGET_VR4130_ALIGN ) vr4130_align_insns ( ) ; if ( mips_expand_ghost_gp_insns ( ) ) mips_reorg_process_insns ( ) ; mips16_split_long_branches ( ) ; return 0 ; } </s>

We use a machine specific pass to do a second machine dependent reorg pass after delay branch scheduling .


<s> bool MipsTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( AM . BaseGV ) return false ; if ( isCheriPointer ( AS , & DL ) ) { switch ( AM . Scale ) { case 0 : case 1 : return true ; default : return false ; } } switch ( AM . Scale ) { case 0 : break ; case 1 : if ( ! AM . HasBaseReg ) break ; return false ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> unsigned SPURegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return SPU :: R1 ; } </s>


<s>
void
MipsSEInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineMemOperand
*
MMO
=
GetMemOperand
(
MBB
,
FI
,
MachineMemOperand
::
MOStore
)
;
unsigned
Opc
=
0
;
if
(
Mips
::
CPURegsRegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
IsN64
Mips
::
SW_P8
:
Mips
::
SW
;
else
if
(
Mips
::
CPU64RegsRegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
IsN64
Mips
::
SD_P8
:
Mips
::
SD
;
else
if
(
Mips
::
FGR32RegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
IsN64
Mips
::
SWC1_P8
:
Mips
::
SWC1
;
else
if
(
Mips
::
AFGR64RegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
Mips
::
SDC1
;
else
if
(
Mips
::
FGR64RegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
IsN64
Mips
::
SDC164_P8
:
Mips
::
SDC164
;
assert
(
Opc
&&
"Register class not handled!"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s>
const
MCPhysReg
*
RISCVRegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
auto
&
Subtarget
=
MF
->
getSubtarget
<
RISCVSubtarget
>
(
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_NoRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
hasFnAttribute
(
"interrupt"
)
)
{
if
(
Subtarget
.
hasStdExtD
(
)
)
return
CSR_XLEN_F64_Interrupt_SaveList
;
if
(
Subtarget
.
hasStdExtF
(
)
)
return
CSR_XLEN_F32_Interrupt_SaveList
;
return
CSR_Interrupt_SaveList
;
}
switch
(
Subtarget
.
getTargetABI
(
)
)
{
default
:
llvm_unreachable
(
"Unrecognized ABI"
)
;
case
RISCVABI
::
ABI_ILP32
:
case
RISCVABI
::
ABI_LP64
:
return
CSR_ILP32_LP64_SaveList
;
case
RISCVABI
::
ABI_ILP32F
:
case
RISCVABI
::
ABI_LP64F
:
return
CSR_ILP32F_LP64F_SaveList
;
case
RISCVABI
::
ABI_ILP32D
:
case
RISCVABI
::
ABI_LP64D
:
return
CSR_ILP32D_LP64D_SaveList
;
}
}
</s>


<s> static void print_address_offset ( FILE * file , rtx off , machine_mode mem_mode ) { rtx pat ; if ( c6x_current_insn != NULL_RTX ) { pat = PATTERN ( c6x_current_insn ) ; if ( GET_CODE ( pat ) == COND_EXEC ) pat = COND_EXEC_CODE ( pat ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , 0 , 0 ) ; if ( GET_CODE ( pat ) == SET && GET_CODE ( SET_SRC ( pat ) ) == UNSPEC && XINT ( SET_SRC ( pat ) , 1 ) == UNSPEC_MISALIGNED_ACCESS ) { gcc_assert ( CONST_INT_P ( off ) && ( INTVAL ( off ) & ( GET_MODE_SIZE ( mem_mode ) - 1 ) ) == 0 ) ; fprintf ( file , "[" HOST_WIDE_INT_PRINT_DEC "]" , INTVAL ( off ) / GET_MODE_SIZE ( mem_mode ) ) ; return ; } } fputs ( "(" , file ) ; output_address ( off ) ; fputs ( ")" , file ) ; } </s>

Subroutine of print_address_operand , print a single address offset OFF for a memory access of mode MEM_MODE , choosing between normal form and scaled form depending on the type of the insn . Misaligned memory references must use the scaled form .


<s> bool XCorePassConfig :: addPreISel ( ) { addPass ( createXCoreLowerThreadLocalPass ( ) ) ; return false ; } </s>


<s> static rtx ix86_internal_arg_pointer ( void ) { return virtual_incoming_args_rtx ; } </s>

Handle the TARGET_INTERNAL_ARG_POINTER hook .


<s> void ix86_expand_convert_uns_sidf_sse ( rtx target , rtx input ) { REAL_VALUE_TYPE TWO31r ; rtx x , fp ; x = expand_simple_binop ( SImode , PLUS , input , GEN_INT ( - 2147483647 - 1 ) , NULL , 1 , OPTAB_DIRECT ) ; fp = gen_reg_rtx ( DFmode ) ; emit_insn ( gen_floatsidf2 ( fp , x ) ) ; real_ldexp ( & TWO31r , & dconst1 , 31 ) ; x = const_double_from_real_value ( TWO31r , DFmode ) ; x = expand_simple_binop ( DFmode , PLUS , fp , x , target , 0 , OPTAB_DIRECT ) ; if ( HONOR_SIGNED_ZEROS ( DFmode ) && flag_rounding_math ) x = ix86_expand_sse_fabs ( x , NULL ) ; if ( x != target ) emit_move_insn ( target , x ) ; } </s>

Convert an unsigned SImode value into a DFmode . Only currently used for SSE , but applicable anywhere .


<s> bool X86TargetLowering :: IsDesirableToPromoteOp ( SDValue Op , EVT & PVT ) const { EVT VT = Op . getValueType ( ) ; if ( VT != MVT :: i16 ) return false ; bool Promote = false ; bool Commute = false ; switch ( Op . getOpcode ( ) ) { default : break ; case ISD :: LOAD : { LoadSDNode * LD = cast < LoadSDNode > ( Op ) ; if ( LD -> getExtensionType ( ) == ISD :: NON_EXTLOAD ) { for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = Op . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != ISD :: CopyToReg ) return false ; } } Promote = true ; break ; } case ISD :: SIGN_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: ANY_EXTEND : Promote = true ; break ; case ISD :: SHL : case ISD :: SRL : { SDValue N0 = Op . getOperand ( 0 ) ; if ( MayFoldLoad ( N0 ) && MayFoldIntoStore ( Op ) ) return false ; Promote = true ; break ; } case ISD :: ADD : case ISD :: MUL : case ISD :: AND : case ISD :: OR : case ISD :: XOR : Commute = true ; case ISD :: SUB : { SDValue N0 = Op . getOperand ( 0 ) ; SDValue N1 = Op . getOperand ( 1 ) ; if ( ! Commute && MayFoldLoad ( N1 ) ) return false ; if ( MayFoldLoad ( N0 ) && ( ! isa < ConstantSDNode > ( N1 ) || MayFoldIntoStore ( Op ) ) ) return false ; if ( MayFoldLoad ( N1 ) && ( ! isa < ConstantSDNode > ( N0 ) || MayFoldIntoStore ( Op ) ) ) return false ; Promote = true ; } } PVT = MVT :: i32 ; return Promote ; } </s>

Return true if the target has native support for the specified value type and it is 'desirable ' to use the type .


"Unpredicated consumer depending on predicated producer"

getMachineOpValue - Return binary encoding of operand .


<s> const char * getClearCacheBuiltinName ( ) const override { return nullptr ; } </s>

Intel processors have a unified instruction and data cache .


<s> bool ARMBaseInstrInfo :: isPredicable ( MachineInstr * MI ) const { if ( ! MI -> isPredicable ( ) ) return false ; if ( ! isEligibleForITBlock ( MI ) ) return false ; ARMFunctionInfo * AFI = MI -> getParent ( ) -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; if ( AFI -> isThumb2Function ( ) ) { if ( getSubtarget ( ) . restrictIT ( ) ) return isV8EligibleForIT ( MI ) ; } else { if ( ( MI -> getDesc ( ) . TSFlags & ARMII :: DomainMask ) == ARMII :: DomainNEON ) return false ; } return true ; } </s>

Return true if the specified instruction can be predicated .

ARM ARM ARM ARM ARMII::DomainMask ARMII::DomainNEON


<s> SDValue MipsTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SDNode * CallNode , const Type * RetTy ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; MipsCC MipsCCInfo ( CallConv , IsO32 , CCInfo ) ; MipsCCInfo . analyzeCallResult ( Ins , getTargetMachine ( ) . Options . UseSoftFloat , CallNode , RetTy ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( 1 ) ; InFlag = Val . getValue ( 2 ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( ISD :: BITCAST , DL , RVLocs [ i ] . getValVT ( ) , Val ) ; InVals . push_back ( Val ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> bool rs6000_move_128bit_ok_p ( rtx operands [ ] ) { machine_mode mode = GET_MODE ( operands [ 0 ] ) ; return ( gpc_reg_operand ( operands [ 0 ] , mode ) || gpc_reg_operand ( operands [ 1 ] , mode ) ) ; } </s>


<s> RCPair ARMTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { switch ( Constraint . size ( ) ) { case 1 : switch ( Constraint [ 0 ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: tGPRRegClass ) ; return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'h' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: hGPRRegClass ) ; break ; case 'r' : if ( Subtarget -> isThumb1Only ( ) ) return RCPair ( 0U , & ARM :: tGPRRegClass ) ; return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'w' : if ( VT == MVT :: Other ) break ; if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPRRegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPRRegClass ) ; break ; case 'x' : if ( VT == MVT :: Other ) break ; if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPR_8RegClass ) ; break ; case 't' : if ( VT == MVT :: Other ) break ; if ( VT == MVT :: f32 || VT == MVT :: i32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPR_VFP2RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPR_VFP2RegClass ) ; break ; } break ; case 2 : if ( Constraint [ 0 ] == 'T' ) { switch ( Constraint [ 1 ] ) { default : break ; case 'e' : return RCPair ( 0U , & ARM :: tGPREvenRegClass ) ; case 'o' : return RCPair ( 0U , & ARM :: tGPROddRegClass ) ; } } break ; default : break ; } if ( StringRef ( "{cc}" ) . equals_insensitive ( Constraint ) ) return std :: make_pair ( unsigned ( ARM :: CPSR ) , & ARM :: CCRRegClass ) ; return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s>
char
*
output_e500_flip_gt_bit
(
rtx
dst
,
rtx
src
)
{
static
char
string
[
64
]
;
int
a
,
b
;
gcc_assert
(
GET_CODE
(
dst
)
==
REG
&&
CR_REGNO_P
(
REGNO
(
dst
)
)
&&
GET_CODE
(
src
)
==
REG
&&
CR_REGNO_P
(
REGNO
(
src
)
)
)
;
a
=
4
*
(
REGNO
(
dst
)
CR0_REGNO
)
+
1
;
b
=
4
*
(
REGNO
(
src
)
CR0_REGNO
)
+
1
;
sprintf
(
string
,
"crnot %d,%d"
,
a
,
b
)
;
return
string
;
}
</s>

Return the string to flip the GT bit on a CR .


<s>
int64_t
ARMBaseRegisterInfo
::
getFrameIndexInstrOffset
(
const
MachineInstr
*
MI
,
int
Idx
)
const
{
const
TargetInstrDesc
&
Desc
=
MI
->
getDesc
(
)
;
unsigned
AddrMode
=
(
Desc
.
TSFlags
&
ARMII
::
AddrModeMask
)
;
int64_t
InstrOffs
=
0
;
;
int
Scale
=
1
;
unsigned
ImmIdx
=
0
;
switch
(
AddrMode
)
{
case
ARMII
::
AddrModeT2_i8
:
case
ARMII
::
AddrModeT2_i12
:
case
ARMII
::
AddrMode_i12
:
InstrOffs
=
MI
->
getOperand
(
Idx
+
1
)
.
getImm
(
)
;
Scale
=
1
;
break
;
case
ARMII
::
AddrMode5
:
{
const
MachineOperand
&
OffOp
=
MI
->
getOperand
(
Idx
+
1
)
;
InstrOffs
=
ARM_AM
::
getAM5Offset
(
OffOp
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM5Op
(
OffOp
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
Scale
=
4
;
break
;
}
case
ARMII
::
AddrMode2
:
{
ImmIdx
=
Idx
+
2
;
InstrOffs
=
ARM_AM
::
getAM2Offset
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM2Op
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
break
;
}
case
ARMII
::
AddrMode3
:
{
ImmIdx
=
Idx
+
2
;
InstrOffs
=
ARM_AM
::
getAM3Offset
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM3Op
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
break
;
}
case
ARMII
::
AddrModeT1_s
:
{
ImmIdx
=
Idx
+
1
;
InstrOffs
=
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
;
Scale
=
4
;
break
;
}
default
:
llvm_unreachable
(
"Unsupported addressing mode!"
)
;
break
;
}
return
InstrOffs
*
Scale
;
}
</s>

Get the offset from the referenced frame index in the instruction , if there is one .


<s> void m68hc11_initialize_trampoline ( rtx tramp , rtx fnaddr , rtx cxt ) { const char * static_chain_reg = reg_names [ STATIC_CHAIN_REGNUM ] ; if ( * static_chain_reg == '*' ) static_chain_reg ++ ; if ( TARGET_M6811 ) { emit_move_insn ( gen_rtx_MEM ( HImode , tramp ) , GEN_INT ( 0x18ce ) ) ; emit_move_insn ( gen_rtx_MEM ( HImode , plus_constant ( tramp , 2 ) ) , cxt ) ; emit_move_insn ( gen_rtx_MEM ( HImode , plus_constant ( tramp , 4 ) ) , GEN_INT ( 0x18df ) ) ; emit_move_insn ( gen_rtx_MEM ( QImode , plus_constant ( tramp , 6 ) ) , gen_rtx_CONST ( QImode , gen_rtx_SYMBOL_REF ( Pmode , static_chain_reg ) ) ) ; emit_move_insn ( gen_rtx_MEM ( QImode , plus_constant ( tramp , 7 ) ) , GEN_INT ( 0x7e ) ) ; emit_move_insn ( gen_rtx_MEM ( HImode , plus_constant ( tramp , 8 ) ) , fnaddr ) ; } else { emit_move_insn ( gen_rtx_MEM ( HImode , tramp ) , GEN_INT ( 0x1803 ) ) ; emit_move_insn ( gen_rtx_MEM ( HImode , plus_constant ( tramp , 2 ) ) , cxt ) ; emit_move_insn ( gen_rtx_MEM ( HImode , plus_constant ( tramp , 4 ) ) , gen_rtx_CONST ( HImode , gen_rtx_SYMBOL_REF ( Pmode , static_chain_reg ) ) ) ; emit_move_insn ( gen_rtx_MEM ( QImode , plus_constant ( tramp , 6 ) ) , GEN_INT ( 0x06 ) ) ; emit_move_insn ( gen_rtx_MEM ( HImode , plus_constant ( tramp , 7 ) ) , fnaddr ) ; } } </s>

Emit the code to build the trampoline used to call a nested function . 68HC11 68HC12 ldy # & CXT movw # & CXT , * _.d1 sty * _.d1 jmp FNADDR jmp FNADDR


<s> void Thumb1FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const Thumb1InstrInfo & TII = * static_cast < const Thumb1InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; const Thumb1RegisterInfo * RegInfo = static_cast < const Thumb1RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; DebugLoc dl = Old -> getDebugLoc ( ) ; unsigned Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { unsigned Align = getStackAlignment ( ) ; Amount = ( Amount + Align - 1 ) / Align * Align ; unsigned Opc = Old -> getOpcode ( ) ; if ( Opc == ARM :: ADJCALLSTACKDOWN || Opc == ARM :: tADJCALLSTACKDOWN ) { emitSPUpdate ( MBB , I , TII , dl , * RegInfo , - Amount ) ; } else { assert ( Opc == ARM :: ADJCALLSTACKUP || Opc == ARM :: tADJCALLSTACKUP ) ; emitSPUpdate ( MBB , I , TII , dl , * RegInfo , Amount ) ; } } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s>
void
WebAssemblyAsmPrinter
::
emitGlobalVariable
(
const
GlobalVariable
*
GV
)
{
if
(
!
WebAssembly
::
isWasmVarAddressSpace
(
GV
->
getAddressSpace
(
)
)
)
{
AsmPrinter
::
emitGlobalVariable
(
GV
)
;
return
;
}
assert
(
!
GV
->
isThreadLocal
(
)
)
;
MCSymbolWasm
*
Sym
=
cast
<
MCSymbolWasm
>
(
getSymbol
(
GV
)
)
;
if
(
!
Sym
->
getType
(
)
)
{
const
WebAssemblyTargetLowering
&
TLI
=
*
Subtarget
->
getTargetLowering
(
)
;
SmallVector
<
EVT
,
1
>
VTs
;
ComputeValueVTs
(
TLI
,
GV
->
getParent
(
)
->
getDataLayout
(
)
,
GV
->
getValueType
(
)
,
VTs
)
;
if
(
VTs
.
size
(
)
!=
1
||
TLI
.
getNumRegisters
(
GV
->
getParent
(
)
->
getContext
(
)
,
VTs
[
0
]
)
!=
1
)
report_fatal_error
(
"Aggregate globals not yet implemented"
)
;
MVT
VT
=
TLI
.
getRegisterType
(
GV
->
getParent
(
)
->
getContext
(
)
,
VTs
[
0
]
)
;
bool
Mutable
=
true
;
wasm
::
ValType
Type
=
WebAssembly
::
toValType
(
VT
)
;
Sym
->
setType
(
wasm
::
WASM_SYMBOL_TYPE_GLOBAL
)
;
Sym
->
setGlobalType
(
wasm
::
WasmGlobalType
{
uint8_t
(
Type
)
,
Mutable
}
)
;
}
emitVisibility
(
Sym
,
GV
->
getVisibility
(
)
,
!
GV
->
isDeclaration
(
)
)
;
if
(
GV
->
hasInitializer
(
)
)
{
assert
(
getSymbolPreferLocal
(
*
GV
)
==
Sym
)
;
emitLinkage
(
GV
,
Sym
)
;
getTargetStreamer
(
)
->
emitGlobalType
(
Sym
)
;
OutStreamer
->
emitLabel
(
Sym
)
;
OutStreamer
->
AddBlankLine
(
)
;
}
}
</s>

Emit the specified global variable to the .s file .


<s> bool SparcPassConfig :: addPreEmitPass ( ) { PM -> add ( createSparcFPMoverPass ( getSparcTargetMachine ( ) ) ) ; PM -> add ( createSparcDelaySlotFillerPass ( getSparcTargetMachine ( ) ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
StringRef
getPassName
(
)
const
override
{
return
"AMDGPU Always Inline Pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
void
AMDGPUInstPrinter
::
printOffset
(
const
MCInst
*
MI
,
unsigned
OpNo
,
raw_ostream
&
O
)
{
uint16_t
Imm
=
MI
->
getOperand
(
OpNo
)
.
getImm
(
)
;
if
(
Imm
!=
0
)
{
O
<<
" offset:"
;
printU16ImmDecOperand
(
MI
,
OpNo
,
O
)
;
}
}
</s>

This is just convenient handler for printing offsets .


<s> static unsigned HOST_WIDE_INT mips_shift_truncation_mask ( machine_mode mode ) { if ( TARGET_LOONGSON_MMI && VECTOR_MODE_P ( mode ) ) return 0 ; return GET_MODE_BITSIZE ( mode ) - 1 ; } </s>

Implement TARGET_SHIFT_TRUNCATION_MASK . We want to keep the default behavior of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even when TARGET_LOONGSON_VECTORS is true .


<s>
static
void
process_cfa_adjust_cfa
(
FILE
*
out_file
,
rtx
pat
,
rtx
insn
,
bool
unwind
,
bool
frame
)
{
rtx
dest
=
SET_DEST
(
pat
)
;
rtx
src
=
SET_SRC
(
pat
)
;
if
(
dest
==
stack_pointer_rtx
)
{
if
(
GET_CODE
(
src
)
==
PLUS
)
{
rtx
op0
=
XEXP
(
src
,
0
)
;
rtx
op1
=
XEXP
(
src
,
1
)
;
gcc_assert
(
op0
==
dest
&&
GET_CODE
(
op1
)
==
CONST_INT
)
;
if
(
INTVAL
(
op1
)
<
0
)
{
gcc_assert
(
!
frame_pointer_needed
)
;
if
(
unwind
)
fprintf
(
out_file
,
"\t.fframe "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
INTVAL
(
op1
)
)
;
}
else
process_epilogue
(
out_file
,
insn
,
unwind
,
frame
)
;
}
else
{
gcc_assert
(
src
==
hard_frame_pointer_rtx
)
;
process_epilogue
(
out_file
,
insn
,
unwind
,
frame
)
;
}
}
else
if
(
dest
==
hard_frame_pointer_rtx
)
{
gcc_assert
(
src
==
stack_pointer_rtx
)
;
gcc_assert
(
frame_pointer_needed
)
;
if
(
unwind
)
fprintf
(
out_file
,
"\t.vframe r%d\n"
,
ia64_debugger_regno
(
REGNO
(
dest
)
)
)
;
}
else
gcc_unreachable
(
)
;
}
</s>

This function processes a SET pattern for REG_CFA_ADJUST_CFA .


<s> bool AMDGPUPassConfig :: addPostRegAlloc ( ) { return false ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> unsigned MipsRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? Mips :: FP : Mips :: SP ; } </s>


"invalid use of MMA type %qs as a function return value"

"non-standard ABI extension with no compatibility "

Return a nonzero value to say to return the function value in memory , just as large structures are always returned . TYPE will be the data type of the value , and FNTYPE will be the type of the function doing the returning , or @ code { NULL } for libcalls . The AIX ABI for the RS/6000 specifies that all structures are returned in memory . The Darwin ABI does the same . The SVR4 ABI specifies that structures < = 8 bytes are returned in r3/r4 , but a draft put them in memory , and GCC used to implement the draft instead of the final standard . Therefore , aix_struct_return controls this instead of DEFAULT_ABI ; V.4 targets needing backward compatibility can change DRAFT_V4_STRUCT_RET to override the default , and -m switches get the final word . See rs6000_override_options for more details . The PPC32 SVR4 ABI uses IEEE double extended for long double , if 128-bit long double support is enabled . These values are returned in memory . int_size_in_bytes returns -1 for variable size objects , which go in memory always . The cast to unsigned makes -1 > 8 .


<s> bool RISCVMCExpr :: evaluateAsConstant ( int64_t & Res ) const { MCValue Value ; if ( Kind == VK_RISCV_PCREL_HI || Kind == VK_RISCV_PCREL_LO || Kind == VK_RISCV_GOT_HI || Kind == VK_RISCV_TPREL_HI || Kind == VK_RISCV_TPREL_LO || Kind == VK_RISCV_TPREL_ADD || Kind == VK_RISCV_TLS_GOT_HI || Kind == VK_RISCV_TLS_GD_HI || Kind == VK_RISCV_CALL || Kind == VK_RISCV_CALL_PLT || Kind == VK_RISCV_CAPTAB_PCREL_HI || Kind == VK_RISCV_TPREL_CINCOFFSET || Kind == VK_RISCV_TLS_IE_CAPTAB_PCREL_HI || Kind == VK_RISCV_TLS_GD_CAPTAB_PCREL_HI || Kind == VK_RISCV_CCALL ) return false ; if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ) return false ; if ( ! Value . isAbsolute ( ) ) return false ; Res = evaluateAsInt64 ( Value . getConstant ( ) ) ; return true ; } </s>

Evaluates the fixup as a constant value .

RISCV RISCV RISCV RISCV RISCV RISCV RISCV RISCV RISCV RISCV RISCV RISCV RISCV RISCV RISCV RISCV RISCV


<s> bool ARMAsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const { return reasonForFixupRelaxation ( Fixup , Value ) ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> SDValue MSP430TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; AnalyzeReturnValues ( CCInfo , RVLocs , Ins ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>


<s> std :: unique_ptr < MCObjectWriter > SHUXIAsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { return createSHUXIELFObjectWriter ( OS , false , true , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


Expand a builtin . These builtins are `` special '' because they do n't have symbolic constants defined per-instruction or per instruction-variant . Instead , the required info is looked up in the ARM_BUILTIN_DATA record that is passed into the function .


<s> enum attr_old_cc compute_plussi_cc ( rtx * operands ) { machine_mode mode = GET_MODE ( operands [ 0 ] ) ; gcc_assert ( mode == SImode ) ; if ( GET_CODE ( operands [ 2 ] ) == CONST_INT && register_operand ( operands [ 1 ] , VOIDmode ) ) { HOST_WIDE_INT intval = INTVAL ( operands [ 2 ] ) ; if ( TARGET_H8300SX && ( intval >= 1 && intval <= 7 ) ) return OLD_CC_SET_ZN ; if ( TARGET_H8300SX && ( intval >= - 7 && intval <= - 1 ) ) return OLD_CC_SET_ZN ; switch ( ( unsigned int ) intval & 0xffffffff ) { case 0x00000001 : case 0x00000002 : case 0x00000004 : return OLD_CC_NONE_0HIT ; case 0xffffffff : case 0xfffffffe : case 0xfffffffc : return OLD_CC_NONE_0HIT ; case 0x00010000 : case 0x00020000 : return OLD_CC_CLOBBER ; case 0xffff0000 : case 0xfffe0000 : return OLD_CC_CLOBBER ; } if ( ( intval & 0xffff ) == 0 ) return OLD_CC_CLOBBER ; } return OLD_CC_SET_ZN ; } </s>

Compute which flag bits are valid after an addition insn .


<s> static unsigned int aarch64_autovectorize_vector_sizes ( void ) { return ( 16 | 8 ) ; } </s>

Return a list of possible vector sizes for the vectorizer to iterate over .


<s> static bool fixed_reg_p ( int reg ) { if ( reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ( ( DEFAULT_ABI == ABI_V4 && flag_pic ) || ( DEFAULT_ABI == ABI_DARWIN && flag_pic ) || ( TARGET_TOC && TARGET_MINIMAL_TOC ) ) ) return false ; return fixed_regs [ reg ] ; } </s>

Return whether REG is a global user reg or has been specifed by -ffixed-REG . We should not restore these , and so can not use lmw or out-of-line restore functions if there are any . We also ca n't save them ( well , emit frame notes for them ) , because frame unwinding during exception handling will restore saved registers .


<s>
bool
AVRFrameLowering
::
spillCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
ArrayRef
<
CalleeSavedInfo
>
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
if
(
CSI
.
empty
(
)
)
{
return
false
;
}
unsigned
CalleeFrameSize
=
0
;
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
AVRSubtarget
&
STI
=
MF
.
getSubtarget
<
AVRSubtarget
>
(
)
;
const
TargetInstrInfo
&
TII
=
*
STI
.
getInstrInfo
(
)
;
AVRMachineFunctionInfo
*
AVRFI
=
MF
.
getInfo
<
AVRMachineFunctionInfo
>
(
)
;
for
(
unsigned
i
=
CSI
.
size
(
)
;
i
!=
0
;
i
)
{
unsigned
Reg
=
CSI
[
i
1
]
.
getReg
(
)
;
bool
IsNotLiveIn
=
!
MBB
.
isLiveIn
(
Reg
)
;
assert
(
TRI
->
getRegSizeInBits
(
*
TRI
->
getMinimalPhysRegClass
(
Reg
)
)
==
8
&&
"Invalid register size"
)
;
if
(
IsNotLiveIn
)
{
MBB
.
addLiveIn
(
Reg
)
;
}
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
PUSHRr
)
)
.
addReg
(
Reg
,
getKillRegState
(
IsNotLiveIn
)
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
++
CalleeFrameSize
;
}
AVRFI
->
setCalleeSavedFrameSize
(
CalleeFrameSize
)
;
return
true
;
}
</s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .

AVR
AVR
0
AVR
AVR
AVR
AVR
AVR
0
1
8
"Invalid register size"
AVR::PUSHRr
AVR


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Hexagon NewValueJump"
;
}
</s>


<s> bool X86IndirectBranchTrackingPass :: runOnMachineFunction ( MachineFunction & MF ) { const X86Subtarget & SubTarget = MF . getSubtarget < X86Subtarget > ( ) ; const Module * M = MF . getMMI ( ) . getModule ( ) ; Metadata * isCFProtectionSupported = M -> getModuleFlag ( "cf-protection-branch" ) ; const X86TargetMachine * TM = static_cast < const X86TargetMachine * > ( & MF . getTarget ( ) ) ; bool isJITwithCET = TM -> isJIT ( ) ; bool isJITwithCET = false ; if ( ! isCFProtectionSupported && ! IndirectBranchTracking && ! isJITwithCET ) return false ; bool Changed = false ; TII = SubTarget . getInstrInfo ( ) ; EndbrOpcode = SubTarget . is64Bit ( ) ? X86 :: ENDBR64 : X86 :: ENDBR32 ; if ( needsPrologueENDBR ( MF , M ) ) { auto MBB = MF . begin ( ) ; Changed |= addENDBR ( * MBB , MBB -> begin ( ) ) ; } for ( auto & MBB : MF ) { if ( MBB . hasAddressTaken ( ) ) Changed |= addENDBR ( MBB , MBB . begin ( ) ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( I -> isCall ( ) && I -> getNumOperands ( ) > 0 && IsCallReturnTwice ( I -> getOperand ( 0 ) ) ) { Changed |= addENDBR ( MBB , std :: next ( I ) ) ; } } if ( TM -> Options . ExceptionModel == ExceptionHandling :: SjLj ) { for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( MBB . isEHPad ( ) ) { if ( I -> isDebugInstr ( ) ) continue ; Changed |= addENDBR ( MBB , I ) ; break ; } else if ( I -> isEHLabel ( ) ) { MCSymbol * Sym = I -> getOperand ( 0 ) . getMCSymbol ( ) ; if ( ! MF . hasCallSiteLandingPad ( Sym ) ) continue ; Changed |= addENDBR ( MBB , std :: next ( I ) ) ; break ; } } } else if ( MBB . isEHPad ( ) ) { for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( ! I -> isEHLabel ( ) ) continue ; Changed |= addENDBR ( MBB , std :: next ( I ) ) ; break ; } } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s>
Sparc
::
Fixups
SparcMCExpr
::
getFixupKind
(
SparcMCExpr
::
VariantKind
Kind
)
{
switch
(
Kind
)
{
default
:
assert
(
0
&&
"Unhandled SparcMCExpr::VariantKind"
)
;
case
VK_Sparc_LO
:
return
Sparc
::
fixup_sparc_lo10
;
case
VK_Sparc_HI
:
return
Sparc
::
fixup_sparc_hi22
;
case
VK_Sparc_H44
:
return
Sparc
::
fixup_sparc_h44
;
case
VK_Sparc_M44
:
return
Sparc
::
fixup_sparc_m44
;
case
VK_Sparc_L44
:
return
Sparc
::
fixup_sparc_l44
;
case
VK_Sparc_HH
:
return
Sparc
::
fixup_sparc_hh
;
case
VK_Sparc_HM
:
return
Sparc
::
fixup_sparc_hm
;
case
VK_Sparc_PC22
:
return
Sparc
::
fixup_sparc_pc22
;
case
VK_Sparc_PC10
:
return
Sparc
::
fixup_sparc_pc10
;
case
VK_Sparc_GOT22
:
return
Sparc
::
fixup_sparc_got22
;
case
VK_Sparc_GOT10
:
return
Sparc
::
fixup_sparc_got10
;
case
VK_Sparc_WPLT30
:
return
Sparc
::
fixup_sparc_wplt30
;
case
VK_Sparc_TLS_GD_HI22
:
return
Sparc
::
fixup_sparc_tls_gd_hi22
;
case
VK_Sparc_TLS_GD_LO10
:
return
Sparc
::
fixup_sparc_tls_gd_lo10
;
case
VK_Sparc_TLS_GD_ADD
:
return
Sparc
::
fixup_sparc_tls_gd_add
;
case
VK_Sparc_TLS_GD_CALL
:
return
Sparc
::
fixup_sparc_tls_gd_call
;
case
VK_Sparc_TLS_LDM_HI22
:
return
Sparc
::
fixup_sparc_tls_ldm_hi22
;
case
VK_Sparc_TLS_LDM_LO10
:
return
Sparc
::
fixup_sparc_tls_ldm_lo10
;
case
VK_Sparc_TLS_LDM_ADD
:
return
Sparc
::
fixup_sparc_tls_ldm_add
;
case
VK_Sparc_TLS_LDM_CALL
:
return
Sparc
::
fixup_sparc_tls_ldm_call
;
case
VK_Sparc_TLS_LDO_HIX22
:
return
Sparc
::
fixup_sparc_tls_ldo_hix22
;
case
VK_Sparc_TLS_LDO_LOX10
:
return
Sparc
::
fixup_sparc_tls_ldo_lox10
;
case
VK_Sparc_TLS_LDO_ADD
:
return
Sparc
::
fixup_sparc_tls_ldo_add
;
case
VK_Sparc_TLS_IE_HI22
:
return
Sparc
::
fixup_sparc_tls_ie_hi22
;
case
VK_Sparc_TLS_IE_LO10
:
return
Sparc
::
fixup_sparc_tls_ie_lo10
;
case
VK_Sparc_TLS_IE_LD
:
return
Sparc
::
fixup_sparc_tls_ie_ld
;
case
VK_Sparc_TLS_IE_LDX
:
return
Sparc
::
fixup_sparc_tls_ie_ldx
;
case
VK_Sparc_TLS_IE_ADD
:
return
Sparc
::
fixup_sparc_tls_ie_add
;
case
VK_Sparc_TLS_LE_HIX22
:
return
Sparc
::
fixup_sparc_tls_le_hix22
;
case
VK_Sparc_TLS_LE_LOX10
:
return
Sparc
::
fixup_sparc_tls_le_lox10
;
}
}
</s>

getFixupKind - Get the fixup kind of this expression .


<s> static void s390_chunkify_finish ( struct constant_pool * pool_list ) { struct constant_pool * curr_pool = NULL ; rtx_insn * insn ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { curr_pool = s390_find_pool ( pool_list , insn ) ; if ( ! curr_pool ) continue ; if ( NONJUMP_INSN_P ( insn ) || CALL_P ( insn ) ) { rtx addr , pool_ref = NULL_RTX ; find_constant_pool_ref ( insn , & pool_ref ) ; if ( pool_ref ) { if ( s390_execute_label ( insn ) ) addr = s390_find_execute ( curr_pool , insn ) ; else addr = s390_find_constant ( curr_pool , get_pool_constant ( pool_ref ) , get_pool_mode ( pool_ref ) ) ; replace_constant_pool_ref ( insn , pool_ref , addr ) ; INSN_CODE ( insn ) = - 1 ; } } } for ( curr_pool = pool_list ; curr_pool ; curr_pool = curr_pool -> next ) s390_dump_pool ( curr_pool , 0 ) ; while ( pool_list ) { struct constant_pool * next = pool_list -> next ; s390_free_pool ( pool_list ) ; pool_list = next ; } } </s>

POOL_LIST is a chunk list as prepared by s390_chunkify_start . After we have decided to use this list , finish implementing all changes to the current function as required .


<s> HOST_WIDE_INT rs6000_builtin_mask_calculate ( void ) { return ( ( ( TARGET_ALTIVEC ) ? RS6000_BTM_ALTIVEC : 0 ) | ( ( TARGET_VSX ) ? RS6000_BTM_VSX : 0 ) | ( ( TARGET_SPE ) ? RS6000_BTM_SPE : 0 ) | ( ( TARGET_PAIRED_FLOAT ) ? RS6000_BTM_PAIRED : 0 ) | ( ( TARGET_FRE ) ? RS6000_BTM_FRE : 0 ) | ( ( TARGET_FRES ) ? RS6000_BTM_FRES : 0 ) | ( ( TARGET_FRSQRTE ) ? RS6000_BTM_FRSQRTE : 0 ) | ( ( TARGET_FRSQRTES ) ? RS6000_BTM_FRSQRTES : 0 ) | ( ( TARGET_POPCNTD ) ? RS6000_BTM_POPCNTD : 0 ) | ( ( rs6000_cpu == PROCESSOR_CELL ) ? RS6000_BTM_CELL : 0 ) | ( ( TARGET_P8_VECTOR ) ? RS6000_BTM_P8_VECTOR : 0 ) | ( ( TARGET_P9_VECTOR ) ? RS6000_BTM_P9_VECTOR : 0 ) | ( ( TARGET_P9_MISC ) ? RS6000_BTM_P9_MISC : 0 ) | ( ( TARGET_MODULO ) ? RS6000_BTM_MODULO : 0 ) | ( ( TARGET_64BIT ) ? RS6000_BTM_64BIT : 0 ) | ( ( TARGET_CRYPTO ) ? RS6000_BTM_CRYPTO : 0 ) | ( ( TARGET_HTM ) ? RS6000_BTM_HTM : 0 ) | ( ( TARGET_DFP ) ? RS6000_BTM_DFP : 0 ) | ( ( TARGET_HARD_FLOAT ) ? RS6000_BTM_HARD_FLOAT : 0 ) | ( ( TARGET_LONG_DOUBLE_128 ) ? RS6000_BTM_LDBL128 : 0 ) | ( ( TARGET_FLOAT128_TYPE ) ? RS6000_BTM_FLOAT128 : 0 ) ) ; } </s>

Return the builtin mask of the various options used that could affect which builtins were used . In the past we used target_flags , but we 've run out of bits , and some options like PAIRED are no longer in target_flags .


<s>
void
AArch64FrameLowering
::
emitEpilogue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
getLastNonDebugInstr
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
const
AArch64InstrInfo
*
TII
=
static_cast
<
const
AArch64InstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
const
AArch64RegisterInfo
*
RegInfo
=
static_cast
<
const
AArch64RegisterInfo
*
>
(
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
)
;
DebugLoc
DL
;
bool
IsTailCallReturn
=
false
;
if
(
MBB
.
end
(
)
!=
MBBI
)
{
DL
=
MBBI
->
getDebugLoc
(
)
;
unsigned
RetOpcode
=
MBBI
->
getOpcode
(
)
;
IsTailCallReturn
=
RetOpcode
==
AArch64
::
TCRETURNdi
||
RetOpcode
==
AArch64
::
TCRETURNri
;
}
int
NumBytes
=
MFI
->
getStackSize
(
)
;
const
AArch64FunctionInfo
*
AFI
=
MF
.
getInfo
<
AArch64FunctionInfo
>
(
)
;
if
(
MF
.
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
;
uint64_t
ArgumentPopSize
=
0
;
if
(
IsTailCallReturn
)
{
MachineOperand
&
StackAdjust
=
MBBI
->
getOperand
(
1
)
;
ArgumentPopSize
=
StackAdjust
.
getImm
(
)
;
}
else
{
ArgumentPopSize
=
AFI
->
getArgumentStackToRestore
(
)
;
}
NumBytes
+=
ArgumentPopSize
;
unsigned
NumRestores
=
0
;
MachineBasicBlock
::
iterator
LastPopI
=
MBB
.
getFirstTerminator
(
)
;
const
MCPhysReg
*
CSRegs
=
RegInfo
->
getCalleeSavedRegs
(
&
MF
)
;
if
(
LastPopI
!=
MBB
.
begin
(
)
)
{
do
{
++
NumRestores
;
LastPopI
;
}
while
(
LastPopI
!=
MBB
.
begin
(
)
&&
isCSRestore
(
LastPopI
,
CSRegs
)
)
;
if
(
!
isCSRestore
(
LastPopI
,
CSRegs
)
)
{
++
LastPopI
;
NumRestores
;
}
}
NumBytes
-=
NumRestores
*
16
;
assert
(
NumBytes
>=
0
&&
"Negative stack allocation size!?"
)
;
if
(
!
hasFP
(
MF
)
)
{
if
(
!
canUseRedZone
(
MF
)
)
emitFrameOffset
(
MBB
,
LastPopI
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
NumBytes
,
TII
)
;
return
;
}
if
(
NumBytes
||
MFI
->
hasVarSizedObjects
(
)
)
emitFrameOffset
(
MBB
,
LastPopI
,
DL
,
AArch64
::
SP
,
AArch64
::
FP
,
(
NumRestores
1
)
*
16
,
TII
,
MachineInstr
::
NoFlags
)
;
}
</s>


<s> static void alpha_align_insns ( void ) { if ( alpha_tune == PROCESSOR_EV4 ) alpha_align_insns_1 ( 8 , alphaev4_next_group , alphaev4_next_nop ) ; else if ( alpha_tune == PROCESSOR_EV5 ) alpha_align_insns_1 ( 16 , alphaev5_next_group , alphaev5_next_nop ) ; else gcc_unreachable ( ) ; } </s>

The instruction group alignment main loop .


<s> BitVector LC3bRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t ReservedLC3bRegs [ ] = { LC3b :: R6 , LC3b :: R7 , LC3b :: PC , LC3b :: PSR , LC3b :: IR } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: iterator RegIter ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedLC3bRegs ) ; ++ I ) { Reserved . set ( ReservedLC3bRegs [ I ] ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void Thumb1RegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , unsigned PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: tLDRpci ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s> bool GCNPassConfig :: addILPOpts ( ) { if ( EnableEarlyIfConversion ) addPass ( & EarlyIfConverterID ) ; TargetPassConfig :: addILPOpts ( ) ; return false ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .


<s> static void pa_output_function_prologue ( FILE * file ) { pa_output_function_label ( file ) ; remove_useless_addtr_insns ( 0 ) ; } </s>

On HP-PA , move-double insns between fpu and cpu need an 8-byte block of memory . If any fpu reg is used in the function , we allocate such a block here , at the bottom of the frame , just in case it 's needed . If this function is a leaf procedure , then we may choose not to do a `` save '' insn . The decision about whether or not to do this is made in regclass.c .


<s>
SDValue
PTXTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
if
(
isVarArg
)
llvm_unreachable
(
"PTX does not support varargs"
)
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention."
)
;
case
CallingConv
::
PTX_Kernel
:
assert
(
Outs
.
size
(
)
==
0
&&
"Kernel must return void."
)
;
return
DAG
.
getNode
(
PTXISD
::
EXIT
,
dl
,
MVT
::
Other
,
Chain
)
;
case
CallingConv
::
PTX_Device
:
assert
(
Outs
.
size
(
)
<=
1
&&
"Can at most return one value."
)
;
break
;
}
if
(
Outs
.
size
(
)
==
0
)
return
DAG
.
getNode
(
PTXISD
::
RET
,
dl
,
MVT
::
Other
,
Chain
)
;
assert
(
Outs
[
0
]
.
VT
==
MVT
::
i32
&&
"Can return only basic types"
)
;
SDValue
Flag
;
unsigned
reg
=
PTX
::
R0
;
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
PTXMachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
PTXMachineFunctionInfo
>
(
)
;
MFI
->
setRetReg
(
reg
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
reg
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
reg
,
OutVals
[
0
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
return
DAG
.
getNode
(
PTXISD
::
RET
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .

PTX
PTX
ISD::OutputArg
"PTX does not support varargs"
"Unsupported calling convention."
PTX
0
"Kernel must return void."
PTXISD::EXIT
MVT::Other
PTX
1
"Can at most return one value."
0
PTXISD::RET
MVT::Other
0
MVT::i32
"Can return only basic types"
PTX::R0
PTX
PTX
0
1
PTXISD::RET
MVT::Other


<s> static machine_mode arm_preferred_simd_mode ( machine_mode mode ) { if ( TARGET_NEON ) switch ( mode ) { case SFmode : return TARGET_NEON_VECTORIZE_DOUBLE ? V2SFmode : V4SFmode ; case SImode : return TARGET_NEON_VECTORIZE_DOUBLE ? V2SImode : V4SImode ; case HImode : return TARGET_NEON_VECTORIZE_DOUBLE ? V4HImode : V8HImode ; case QImode : return TARGET_NEON_VECTORIZE_DOUBLE ? V8QImode : V16QImode ; case DImode : if ( ! TARGET_NEON_VECTORIZE_DOUBLE ) return V2DImode ; break ; default : ; } if ( TARGET_REALLY_IWMMXT ) switch ( mode ) { case SImode : return V2SImode ; case HImode : return V4HImode ; case QImode : return V8QImode ; default : ; } return word_mode ; } </s>

Use the option -mvectorize-with-neon-double to override the use of quardword registers when autovectorizing for Neon , at least until multiple vector widths are supported properly by the middle-end .


<s> static rtx rs6000_savres_routine_sym ( rs6000_stack_t * info , int sel ) { int regno = ( ( sel & SAVRES_REG ) == SAVRES_GPR ? info -> first_gp_reg_save : ( sel & SAVRES_REG ) == SAVRES_FPR ? info -> first_fp_reg_save - 32 : ( sel & SAVRES_REG ) == SAVRES_VR ? info -> first_altivec_reg_save - FIRST_ALTIVEC_REGNO : - 1 ) ; rtx sym ; int select = sel ; if ( TARGET_SPE_ABI && ( sel & SAVRES_REG ) == SAVRES_GPR && info -> spe_64bit_regs_used ) select ^= SAVRES_FPR ^ SAVRES_GPR ; gcc_assert ( FIRST_SAVRES_REGISTER <= regno && regno <= LAST_SAVRES_REGISTER && select >= 0 && select <= 12 ) ; sym = savres_routine_syms [ regno - FIRST_SAVRES_REGISTER ] [ select ] ; if ( sym == NULL ) { char * name ; name = rs6000_savres_routine_name ( info , regno , sel ) ; sym = savres_routine_syms [ regno - FIRST_SAVRES_REGISTER ] [ select ] = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( name ) ) ; SYMBOL_REF_FLAGS ( sym ) |= SYMBOL_FLAG_FUNCTION ; } return sym ; } </s>

Return an RTL SYMBOL_REF for an out-of-line register save/restore routine . We are saving/restoring GPRs if GPR is true .


<s> bool ARCExpandPseudos :: runOnMachineFunction ( MachineFunction & MF ) { const ARCSubtarget * STI = & MF . getSubtarget < ARCSubtarget > ( ) ; TII = STI -> getInstrInfo ( ) ; bool Expanded = false ; for ( auto & MBB : MF ) { MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; while ( MBBI != E ) { MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; switch ( MBBI -> getOpcode ( ) ) { case ARC :: ST_FAR : case ARC :: STH_FAR : case ARC :: STB_FAR : expandStore ( MF , MBBI ) ; Expanded = true ; break ; case ARC :: CTLZ : expandCTLZ ( MF , MBBI ) ; Expanded = true ; break ; case ARC :: CTTZ : expandCTTZ ( MF , MBBI ) ; Expanded = true ; break ; default : break ; } MBBI = NMBBI ; } } return Expanded ; } </s>

ARC ARC ARC ARC ARC::ST_FAR ARC::STH_FAR ARC::STB_FAR ARC::CTLZ ARC::CTTZ


<s> bool X86TargetLowering :: ShouldShrinkFPConstant ( EVT VT ) const { return ! Subtarget . hasSSE2 ( ) || VT == MVT :: f80 ; } </s>

If true , then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime .


<s> void MipsSEInstrInfo :: adjustStackPtr ( unsigned SP , int64_t Amount , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const MipsSubtarget & STI = Subtarget ; DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned ADDu = STI . isABI_N64 ( ) ? Mips :: DADDu : Mips :: ADDu ; unsigned ADDiu = STI . isABI_N64 ( ) ? Mips :: DADDiu : Mips :: ADDiu ; if ( Amount == 0 ) return ; if ( isInt < 16 > ( Amount ) ) BuildMI ( MBB , I , DL , get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; else { unsigned Reg = loadImmediate ( Amount , MBB , I , DL , nullptr ) ; BuildMI ( MBB , I , DL , get ( ADDu ) , SP ) . addReg ( SP ) . addReg ( Reg , RegState :: Kill ) ; } } </s>

Mips Mips Mips Mips::DADDu Mips::ADDu Mips::DADDiu Mips::ADDiu 0 16


<s> unsigned NyuziInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . getOpcode ( ) == Nyuzi :: SW || MI . getOpcode ( ) == Nyuzi :: BLOCK_STOREI ) { if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> int mmix_reversible_cc_mode ( enum machine_mode mode ) { return mode != CC_FPmode ; } </s>


<s> virtual const GBZ80RegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCInstFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
{
assert
(
0
&&
"RelaxInstruction() unimplemented"
)
;
return
false
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s>
void
MipsInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
DebugLoc
::
getUnknownLoc
(
)
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
if
(
RC
==
Mips
::
CPURegsRegisterClass
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
LW
)
,
DestReg
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
else
if
(
RC
==
Mips
::
FGR32RegisterClass
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
LWC1
)
,
DestReg
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
else
if
(
RC
==
Mips
::
AFGR64RegisterClass
)
{
if
(
!
TM
.
getSubtarget
<
MipsSubtarget
>
(
)
.
isMips1
(
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
LDC1
)
,
DestReg
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
}
else
{
const
TargetRegisterInfo
*
TRI
=
MBB
.
getParent
(
)
->
getTarget
(
)
.
getRegisterInfo
(
)
;
const
unsigned
*
SubSet
=
TRI
->
getSubRegisters
(
DestReg
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
LWC1
)
,
SubSet
[
0
]
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
LWC1
)
,
SubSet
[
1
]
)
.
addImm
(
4
)
.
addFrameIndex
(
FI
)
;
}
}
else
llvm_unreachable
(
"Register class not handled!"
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> static bool sh_cannot_copy_insn_p ( rtx_insn * insn ) { rtx pat ; if ( ! reload_completed || ! flag_pic ) return false ; if ( ! NONJUMP_INSN_P ( insn ) ) return false ; if ( asm_noperands ( insn ) >= 0 ) return false ; pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) != SET ) return false ; pat = SET_SRC ( pat ) ; if ( unspec_caller_rtx_p ( pat ) ) return true ; return false ; } </s>

Indicate that INSN can not be duplicated . This is true for insn that generates a unique label .


<s> void ARMTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , APInt & KnownZero , APInt & KnownOne , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { unsigned BitWidth = KnownOne . getBitWidth ( ) ; KnownZero = KnownOne = APInt ( BitWidth , 0 ) ; switch ( Op . getOpcode ( ) ) { default : break ; case ARMISD :: ADDC : case ARMISD :: ADDE : case ARMISD :: SUBC : case ARMISD :: SUBE : if ( Op . getResNo ( ) == 0 ) break ; KnownZero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - 1 ) ; break ; case ARMISD :: CMOV : { DAG . computeKnownBits ( Op . getOperand ( 0 ) , KnownZero , KnownOne , Depth + 1 ) ; if ( KnownZero == 0 && KnownOne == 0 ) return ; APInt KnownZeroRHS , KnownOneRHS ; DAG . computeKnownBits ( Op . getOperand ( 1 ) , KnownZeroRHS , KnownOneRHS , Depth + 1 ) ; KnownZero &= KnownZeroRHS ; KnownOne &= KnownOneRHS ; return ; } case ISD :: INTRINSIC_W_CHAIN : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ; Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case Intrinsic :: arm_ldaex : case Intrinsic :: arm_ldrex : { EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; KnownZero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } } case ARMISD :: BFI : { DAG . computeKnownBits ( Op . getOperand ( 0 ) , KnownZero , KnownOne , Depth + 1 ) ; ConstantSDNode * CI = cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ; const APInt & Mask = CI -> getAPIntValue ( ) ; KnownZero &= Mask ; KnownOne &= Mask ; return ; } } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> static rtx sparc_function_arg_1 ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named , bool incoming ) { const CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int regbase = ( incoming ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST ) ; int slotno , regno , padding ; enum mode_class mclass = GET_MODE_CLASS ( mode ) ; slotno = function_arg_slotno ( cum , mode , type , named , incoming , & regno , & padding ) ; if ( slotno == - 1 ) return 0 ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( ( TARGET_ARCH32 && size <= 8 ) || ( TARGET_ARCH64 && size <= 16 ) ) ; if ( mode == BLKmode ) return function_arg_vector_value ( size , SPARC_FP_ARG_FIRST + 2 * slotno ) ; mclass = MODE_FLOAT ; } if ( TARGET_ARCH32 ) return gen_rtx_REG ( mode , regno ) ; if ( type && TREE_CODE ( type ) == RECORD_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; return function_arg_record_value ( type , mode , slotno , named , regbase ) ; } else if ( type && TREE_CODE ( type ) == UNION_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; return function_arg_union_value ( size , mode , slotno , regno ) ; } else if ( ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) && SPARC_FP_REG_P ( regno ) ) { rtx reg = gen_rtx_REG ( mode , regno ) ; if ( cum -> prototype_p || cum -> libcall_p ) return reg ; else { rtx v0 , v1 ; if ( ( regno - SPARC_FP_ARG_FIRST ) < SPARC_INT_ARG_MAX * 2 ) { int intreg ; if ( incoming ) return reg ; intreg = ( SPARC_OUTGOING_INT_ARG_FIRST + ( regno - SPARC_FP_ARG_FIRST ) / 2 ) ; v0 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , intreg ) , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , v0 , v1 ) ) ; } else { v0 = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , v0 , v1 ) ) ; } } } else if ( type && AGGREGATE_TYPE_P ( type ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; mode = int_mode_for_size ( size * BITS_PER_UNIT , 0 ) . else_blk ( ) ; } return gen_rtx_REG ( mode , regno ) ; } </s>

Determine where to put an argument to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . NAMED is true if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . INCOMING_P is false for TARGET_FUNCTION_ARG , true for TARGET_FUNCTION_INCOMING_ARG .


"Hard-float can't be used with current CPU,"

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool isMem ( ) const override { return false ; } </s>


<s> CSKYSubtarget & CSKYSubtarget :: initializeSubtargetDependencies ( const Triple & TT , StringRef CPUName , StringRef TuneCPUName , StringRef FS ) { if ( CPUName . empty ( ) ) CPUName = "generic" ; if ( TuneCPUName . empty ( ) ) TuneCPUName = CPUName ; HasE1 = false ; HasE2 = false ; Has2E3 = false ; HasMP = false ; Has3E3r1 = false ; Has3r1E3r2 = false ; Has3r2E3r3 = false ; Has3E7 = false ; HasMP1E2 = false ; Has7E10 = false ; Has10E60 = false ; ParseSubtargetFeatures ( CPUName , TuneCPUName , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s>
SDValue
TeeRISCTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
assert
(
0
&&
"LowerOperation() is Not implemented"
)
;
return
SDValue
(
)
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

TeeRISC
TeeRISC
0
"LowerOperation() is Not implemented"


<s> unsigned int aarch64_widest_sve_pred_elt_size ( rtx_vector_builder & builder ) { unsigned int mask = GET_MODE_SIZE ( DImode ) ; mask |= builder . npatterns ( ) ; unsigned int nelts = builder . encoded_nelts ( ) ; for ( unsigned int i = 1 ; i < nelts ; ++ i ) if ( INTVAL ( builder . elt ( i ) ) != 0 ) { if ( i & 1 ) return 1 ; mask |= i ; } return mask & - mask ; } </s>

BUILDER contains a predicate constant of mode VNx16BI . Return the widest predicate element size it can have ( that is , the largest size for which each element would still be 0 or 1 ) .


<s> bool CSKYAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { if ( Count % 2 ) return false ; while ( Count >= 4 ) { OS . write ( "\xc4\x00\x48\x20" , 4 ) ; Count -= 4 ; } if ( Count ) OS . write ( "\x6c\x03" , 2 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s>
unsigned
Z80InstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
I
->
getOpcode
(
)
!=
Z80
::
JQ
&&
I
->
getOpcode
(
)
!=
Z80
::
JQCC
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s> static rtx c6x_function_value ( const_tree type , const_tree func ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { if ( TARGET_BIG_ENDIAN && type && AGGREGATE_TYPE_P ( type ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; if ( size > 4 ) { rtx reg1 = gen_rtx_REG ( SImode , REG_A4 + 1 ) ; rtx reg2 = gen_rtx_REG ( SImode , REG_A4 ) ; rtvec vec = gen_rtvec ( 2 , gen_rtx_EXPR_LIST ( VOIDmode , reg1 , const0_rtx ) , gen_rtx_EXPR_LIST ( VOIDmode , reg2 , GEN_INT ( 4 ) ) ) ; return gen_rtx_PARALLEL ( TYPE_MODE ( type ) , vec ) ; } } return gen_rtx_REG ( TYPE_MODE ( type ) , REG_A4 ) ; } </s>

TARGET_FUNCTION_VALUE implementation . Returns an RTX representing the place where function FUNC returns or receives a value of data type TYPE .


<s> bool CSKYAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { OS . write_zeros ( Count ) ; return true ; } </s>


<s> static struct machine_function * arm_init_machine_status ( void ) { struct machine_function * machine ; machine = ggc_cleared_alloc < machine_function > ( ) ; machine -> func_type = ARM_FT_UNKNOWN ; machine -> static_chain_stack_bytes = - 1 ; machine -> pacspval_needed = 0 ; return machine ; } </s>

Functions to save and restore machine-specific function data .


<s> static bool isZero ( Register Reg , MachineRegisterInfo & MRI ) { int64_t C ; return mi_match ( Reg , MRI , m_ICst ( C ) ) && C == 0 ; } </s>

Return true if the expression is a constant zero .


"SIInstrInfo::loadRegFromStackSlot - Do not know how to"


<s>
SDValue
PTXTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unimplemented operand"
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BRCOND
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
}
}
</s>

PTX
PTX
"Unimplemented operand"
ISD::GlobalAddress
ISD::BRCOND


<s>
uint32_t
AArch64MCCodeEmitter
::
getBranchTargetOpValue
(
const
MCInst
&
MI
,
unsigned
OpIdx
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCOperand
&
MO
=
MI
.
getOperand
(
OpIdx
)
;
unsigned
Opcode
=
MI
.
getOpcode
(
)
;
unsigned
NumOperands
=
MI
.
getNumOperands
(
)
;
if
(
MO
.
isImm
(
)
)
return
MO
.
getImm
(
)
;
assert
(
MO
.
isExpr
(
)
&&
"Unexpected ADR target type!"
)
;
MCFixupKind
Kind
=
MI
.
getOpcode
(
)
==
AArch64
::
BL
MCFixupKind
(
AArch64
::
fixup_aarch64_pcrel_call26
)
:
MCFixupKind
(
AArch64
::
fixup_aarch64_pcrel_branch26
)
;
Fixups
.
push_back
(
MCFixup
::
create
(
0
,
MO
.
getExpr
(
)
,
Kind
,
MI
.
getLoc
(
)
)
)
;
++
MCNumFixups
;
return
0
;
}
</s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s>
bool
AArch64FrameLowering
::
restoreCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
;
SmallVector
<
RegPairInfo
,
8
>
RegPairs
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
computeCalleeSaveRegisterPairs
(
MF
,
CSI
,
TRI
,
RegPairs
)
;
for
(
auto
RPII
=
RegPairs
.
begin
(
)
,
RPIE
=
RegPairs
.
end
(
)
;
RPII
!=
RPIE
;
++
RPII
)
{
RegPairInfo
RPI
=
*
RPII
;
unsigned
Reg1
=
RPI
.
Reg1
;
unsigned
Reg2
=
RPI
.
Reg2
;
unsigned
LdrOpc
;
bool
BumpSP
=
RPII
==
std
::
prev
(
RegPairs
.
end
(
)
)
;
if
(
RPI
.
IsGPR
)
{
if
(
BumpSP
)
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPXpost
:
AArch64
::
LDRXpost
;
else
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPXi
:
AArch64
::
LDRXui
;
}
else
{
if
(
BumpSP
)
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPDpost
:
AArch64
::
LDRDpost
;
else
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPDi
:
AArch64
::
LDRDui
;
}
DEBUG
(
dbgs
(
)
<<
"CSR restore: ("
<<
TRI
->
getName
(
Reg1
)
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
TRI
->
getName
(
Reg2
)
;
dbgs
(
)
<<
") -> fi#("
<<
RPI
.
FrameIdx
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
RPI
.
FrameIdx
+
1
;
dbgs
(
)
<<
")\n"
)
;
const
int
Offset
=
RPI
.
Offset
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
LdrOpc
)
)
;
if
(
BumpSP
)
MIB
.
addReg
(
AArch64
::
SP
,
RegState
::
Define
)
;
if
(
RPI
.
isPaired
(
)
)
MIB
.
addReg
(
Reg2
,
getDefRegState
(
true
)
)
.
addReg
(
Reg1
,
getDefRegState
(
true
)
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
Offset
)
.
setMIFlag
(
MachineInstr
::
FrameDestroy
)
;
else
MIB
.
addReg
(
Reg1
,
getDefRegState
(
true
)
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
BumpSP
Offset
*
8
:
Offset
)
.
setMIFlag
(
MachineInstr
::
FrameDestroy
)
;
}
return
true
;
}
</s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> virtual const MCObjectFormat & getObjectFormat ( ) const { return Format ; } </s>


<s> static int ix86_reassociation_width ( unsigned int , machine_mode mode ) { if ( VECTOR_MODE_P ( mode ) ) { if ( TARGET_VECTOR_PARALLEL_EXECUTION ) return 2 ; else return 1 ; } if ( INTEGRAL_MODE_P ( mode ) && TARGET_REASSOC_INT_TO_PARALLEL ) return 2 ; else if ( FLOAT_MODE_P ( mode ) && TARGET_REASSOC_FP_TO_PARALLEL ) return ( ( TARGET_64BIT && ix86_tune == PROCESSOR_HASWELL ) ? 4 : 2 ) ; else return 1 ; } </s>

Implementation of reassociation_width target hook used by reassoc phase to identify parallelism level in reassociated tree . Statements tree_code is passed in OPC . Arguments type is passed in MODE . Currently parallel reassociation is enabled for Atom processors only and we set reassociation width to be 2 because Atom may issue up to 2 instructions per cycle . Return value should be fixed if parallel reassociation is enabled for other processors .


<s> bool ARM64PassConfig :: addPostRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableDeadRegisterElimination ) addPass ( createARM64DeadRegisterDefinitions ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> BitVector R600RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AMDGPU :: ZERO ) ; Reserved . set ( AMDGPU :: HALF ) ; Reserved . set ( AMDGPU :: ONE ) ; Reserved . set ( AMDGPU :: ONE_INT ) ; Reserved . set ( AMDGPU :: NEG_HALF ) ; Reserved . set ( AMDGPU :: NEG_ONE ) ; Reserved . set ( AMDGPU :: PV_X ) ; Reserved . set ( AMDGPU :: ALU_LITERAL_X ) ; Reserved . set ( AMDGPU :: ALU_CONST ) ; Reserved . set ( AMDGPU :: PREDICATE_BIT ) ; Reserved . set ( AMDGPU :: PRED_SEL_OFF ) ; Reserved . set ( AMDGPU :: PRED_SEL_ZERO ) ; Reserved . set ( AMDGPU :: PRED_SEL_ONE ) ; for ( TargetRegisterClass :: iterator I = AMDGPU :: R600_AddrRegClass . begin ( ) , E = AMDGPU :: R600_AddrRegClass . end ( ) ; I != E ; ++ I ) { Reserved . set ( * I ) ; } for ( TargetRegisterClass :: iterator I = AMDGPU :: TRegMemRegClass . begin ( ) , E = AMDGPU :: TRegMemRegClass . end ( ) ; I != E ; ++ I ) { Reserved . set ( * I ) ; } const R600InstrInfo * RII = static_cast < const R600InstrInfo * > ( TM . getInstrInfo ( ) ) ; std :: vector < unsigned > IndirectRegs = RII -> getIndirectReservedRegs ( MF ) ; for ( std :: vector < unsigned > :: iterator I = IndirectRegs . begin ( ) , E = IndirectRegs . end ( ) ; I != E ; ++ I ) { Reserved . set ( * I ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
SDValue
SITargetLowering
::
handleD16VData
(
SDValue
VData
,
SelectionDAG
&
DAG
)
const
{
EVT
StoreVT
=
VData
.
getValueType
(
)
;
if
(
!
StoreVT
.
isVector
(
)
)
return
VData
;
SDLoc
DL
(
VData
)
;
assert
(
(
StoreVT
.
getVectorNumElements
(
)
!=
3
)
&&
"Handle v3f16"
)
;
if
(
Subtarget
->
hasUnpackedD16VMem
(
)
)
{
EVT
IntStoreVT
=
StoreVT
.
changeTypeToInteger
(
)
;
SDValue
IntVData
=
DAG
.
getNode
(
ISD
::
BITCAST
,
DL
,
IntStoreVT
,
VData
)
;
EVT
EquivStoreVT
=
EVT
::
getVectorVT
(
*
DAG
.
getContext
(
)
,
MVT
::
i32
,
StoreVT
.
getVectorNumElements
(
)
)
;
SDValue
ZExt
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
DL
,
EquivStoreVT
,
IntVData
)
;
return
DAG
.
UnrollVectorOp
(
ZExt
.
getNode
(
)
)
;
}
assert
(
isTypeLegal
(
StoreVT
)
)
;
return
VData
;
}
</s>

Handle register layout difference for f16 images for some subtargets .


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) -> findAssociatedFragment ( ) ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LiveIntervals > ( ) ; AU . addPreserved < LiveIntervals > ( ) ; AU . addPreserved < SlotIndexes > ( ) ; AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> unsigned int call_properties ( const function_instance & ) const override { return 0 ; } </s>

Default implementation of function_base : :call_properties , with conservatively correct behavior for floating-point instructions .


<s> const SystemZInstrInfo * getInstrInfo ( ) const { return Subtarget -> getInstrInfo ( ) ; } </s>


"All regions recorded, starting actual scheduling.\n"

"Retrying function scheduling with lowest recorded occupancy "

After the schedule has been formed , call this function to combine the instructions from the different stages/cycles .


<s> void emit_symbolic_move ( rtx * operands ) { rtx temp = no_new_pseudos ? operands [ 0 ] : gen_reg_rtx ( Pmode ) ; if ( GET_CODE ( operands [ 0 ] ) == MEM ) operands [ 1 ] = force_reg ( Pmode , operands [ 1 ] ) ; else if ( TLS_SYMBOLIC_CONST ( operands [ 1 ] ) ) operands [ 1 ] = legitimize_tls_address ( operands [ 1 ] , temp ) ; else if ( flag_pic ) operands [ 1 ] = legitimize_pic_address ( operands [ 1 ] , temp ) ; } </s>

Emit insns to move operands [ 1 ] into operands [ 0 ] .


<s> const RISCVTargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


<s> static bool arc_function_ok_for_sibcall ( tree decl ATTRIBUTE_UNUSED , tree exp ATTRIBUTE_UNUSED ) { if ( ARC_INTERRUPT_P ( arc_compute_function_type ( cfun ) ) ) return false ; return true ; } </s>

Return true if it is ok to make a tail-call to DECL .


<s> static machine_mode mips_get_reg_raw_mode ( int regno ) { if ( TARGET_FLOATXX && FP_REG_P ( regno ) ) return DFmode ; return default_get_reg_raw_mode ( regno ) ; } </s>


<s> void visium_split_cbranch ( enum rtx_code code , rtx op0 , rtx op1 , rtx label ) { enum machine_mode cc_mode = visium_select_cc_mode ( code , op0 , op1 ) ; rtx flags = gen_rtx_REG ( cc_mode , FLAGS_REGNUM ) ; rtx x = gen_rtx_COMPARE ( cc_mode , op0 , op1 ) ; x = gen_rtx_SET ( VOIDmode , flags , x ) ; emit_insn ( x ) ; x = gen_rtx_fmt_ee ( code , VOIDmode , flags , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label ) , pc_rtx ) ; x = gen_rtx_SET ( VOIDmode , pc_rtx , x ) ; emit_jump_insn ( x ) ; visium_flags_exposed = true ; } </s>

Split a compare-and-branch with CODE , operands OP0 and OP1 , and LABEL .


<s> BaseKind getKind ( ) const { return Kind ; } </s>


<s> virtual const TargetRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .