<s> unsigned AMDGPURegisterBankInfo :: copyCost ( const RegisterBank & Dst , const RegisterBank & Src , unsigned Size ) const { if ( Dst . getID ( ) == AMDGPU :: SGPRRegBankID && Src . getID ( ) == AMDGPU :: VGPRRegBankID ) { return std :: numeric_limits < unsigned > :: max ( ) ; } if ( Size == 1 && ( Dst . getID ( ) == AMDGPU :: SCCRegBankID || Dst . getID ( ) == AMDGPU :: SGPRRegBankID ) && ( Src . getID ( ) == AMDGPU :: SGPRRegBankID || Src . getID ( ) == AMDGPU :: VGPRRegBankID || Src . getID ( ) == AMDGPU :: VCCRegBankID ) ) return std :: numeric_limits < unsigned > :: max ( ) ; if ( Dst . getID ( ) == AMDGPU :: SCCRegBankID && Src . getID ( ) == AMDGPU :: VCCRegBankID ) return std :: numeric_limits < unsigned > :: max ( ) ; return RegisterBankInfo :: copyCost ( Dst , Src , Size ) ; } </s>

Get the cost of a copy from B to A , or put differently , get the cost of A = COPY B .

AMDGPU AMDGPU AMDGPU::SGPRRegBankID AMDGPU::VGPRRegBankID 1 AMDGPU::SCCRegBankID AMDGPU::SGPRRegBankID AMDGPU::SGPRRegBankID AMDGPU::VGPRRegBankID AMDGPU::VCCRegBankID AMDGPU::SCCRegBankID AMDGPU::VCCRegBankID


<s>
CCAssignFn
*
AArch64TargetLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
const
{
switch
(
CC
)
{
default
:
report_fatal_error
(
"Unsupported calling convention."
)
;
case
CallingConv
::
WebKit_JS
:
return
CC_AArch64_WebKit_JS
;
case
CallingConv
::
GHC
:
return
CC_AArch64_GHC
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
case
CallingConv
::
PreserveMost
:
case
CallingConv
::
CXX_FAST_TLS
:
case
CallingConv
::
Swift
:
if
(
Subtarget
->
isTargetWindows
(
)
&&
IsVarArg
)
return
CC_AArch64_Win64_VarArg
;
if
(
!
Subtarget
->
isTargetDarwin
(
)
)
return
CC_AArch64_AAPCS
;
if
(
!
IsVarArg
)
return
CC_AArch64_DarwinPCS
;
return
Subtarget
->
isTargetILP32
(
)
CC_AArch64_DarwinPCS_ILP32_VarArg
:
CC_AArch64_DarwinPCS_VarArg
;
case
CallingConv
::
Win64
:
return
IsVarArg
CC_AArch64_Win64_VarArg
:
CC_AArch64_AAPCS
;
case
CallingConv
::
CFGuard_Check
:
return
CC_AArch64_Win64_CFGuard_Check
;
case
CallingConv
::
AArch64_VectorCall
:
case
CallingConv
::
AArch64_SVE_VectorCall
:
return
CC_AArch64_AAPCS
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> static rtx fixup_modeless_constant ( rtx x , machine_mode mode ) { if ( GET_MODE ( x ) == VOIDmode ) x = convert_to_mode ( mode , x , 1 ) ; return x ; } </s>

Fixup modeless constants to fit required mode .


<s> static unsigned int aarch64_sve_container_bits ( machine_mode mode ) { unsigned int vec_flags = aarch64_classify_vector_mode ( mode ) ; poly_uint64 vector_bits = ( vec_flags & ( VEC_PARTIAL | VEC_SVE_PRED ) ? BITS_PER_SVE_VECTOR : GET_MODE_BITSIZE ( mode ) ) ; return vector_element_size ( vector_bits , GET_MODE_NUNITS ( mode ) ) ; } </s>

MODE is some form of SVE vector mode . For data modes , return the number of vector register bits that each element of MODE occupies , such as 64 for both VNx2DImode and VNx2SImode ( where each 32-bit value is stored in a 64-bit container ) . For predicate modes , return the number of data bits controlled by each significant predicate bit .


<s> int mmix_local_regno ( int regno ) { return ( regno <= MMIX_LAST_STACK_REGISTER_REGNUM && ! call_used_or_fixed_reg_p ( regno ) ) ; } </s>

LOCAL_REGNO . All registers that are part of the register stack and that will be saved are local .


<s>
bool
AVRAsmBackend
::
writeNopData
(
raw_ostream
&
OS
,
uint64_t
Count
,
const
MCSubtargetInfo
*
STI
)
const
{
assert
(
(
Count
%
2
)
==
0
&&
"NOP instructions must be 2 bytes"
)
;
OS
.
write_zeros
(
Count
)
;
return
true
;
}
</s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> SDValue getNode ( unsigned MachineOpc , const SDLoc & dl , MVT Ty , ArrayRef < SDValue > Ops , SelectionDAG & DAG ) const { SDNode * N = DAG . getMachineNode ( MachineOpc , dl , Ty , Ops ) ; return SDValue ( N , 0 ) ; } </s>


<s> void AArch64TargetStreamer :: finish ( ) { if ( MarkBTIProperty ) emitNoteSection ( ELF :: GNU_PROPERTY_AARCH64_FEATURE_1_BTI ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> void RISCVMCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { uint32_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; support :: endian :: Writer < support :: little > ( OS ) . write ( Bits ) ; ++ MCNumEmitted ; } </s>

Encode the given Inst to bytes and append to CB .

RISCV RISCV support::endian support::little


"You cannot use the same Regs with MOVX_RR"

"You cannot use the same Reg Classes with MOVX_RR"

Move across register classes without extension .


<s> static bool must_save_p ( bool is_inthandler , unsigned regno ) { if ( D_REGNO_P ( regno ) ) { bool is_eh_return_reg = false ; if ( crtl -> calls_eh_return ) { unsigned j ; for ( j = 0 ; ; j ++ ) { unsigned test = EH_RETURN_DATA_REGNO ( j ) ; if ( test == INVALID_REGNUM ) break ; if ( test == regno ) is_eh_return_reg = true ; } } return ( is_eh_return_reg || ( df_regs_ever_live_p ( regno ) && ! fixed_regs [ regno ] && ( is_inthandler || ! call_used_or_fixed_reg_p ( regno ) ) ) ) ; } else if ( P_REGNO_P ( regno ) ) { return ( ( df_regs_ever_live_p ( regno ) && ! fixed_regs [ regno ] && ( is_inthandler || ! call_used_or_fixed_reg_p ( regno ) ) ) || ( is_inthandler && ( ENABLE_WA_05000283 || ENABLE_WA_05000315 ) && regno == REG_P5 ) || ( ! TARGET_FDPIC && regno == PIC_OFFSET_TABLE_REGNUM && ( crtl -> uses_pic_offset_table || ( TARGET_ID_SHARED_LIBRARY && ! crtl -> is_leaf ) ) ) ) ; } else return ( ( is_inthandler || ! call_used_or_fixed_reg_p ( regno ) ) && ( df_regs_ever_live_p ( regno ) || ( ! leaf_function_p ( ) && call_used_or_fixed_reg_p ( regno ) ) ) ) ; } </s>

For a given REGNO , determine whether it must be saved in the function prologue . IS_INTHANDLER specifies whether we 're generating a normal prologue or an interrupt/exception one .


<s> void SystemZPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; addPass ( createPartiallyInlineLibCallsPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


"Byval argument's alignment should be a multiple of"

Target-specific cleanup for formal ByVal parameters .


<s> static bool s390_match_ccmode_set ( rtx set , enum machine_mode req_mode ) { enum machine_mode set_mode ; gcc_assert ( GET_CODE ( set ) == SET ) ; if ( GET_CODE ( SET_DEST ( set ) ) != REG || ! CC_REGNO_P ( REGNO ( SET_DEST ( set ) ) ) ) return 1 ; set_mode = GET_MODE ( SET_DEST ( set ) ) ; switch ( set_mode ) { case CCSmode : case CCSRmode : case CCUmode : case CCURmode : case CCLmode : case CCL1mode : case CCL2mode : case CCL3mode : case CCT1mode : case CCT2mode : case CCT3mode : if ( req_mode != set_mode ) return 0 ; break ; case CCZmode : if ( req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode && req_mode != CCSRmode && req_mode != CCURmode ) return 0 ; break ; case CCAPmode : case CCANmode : if ( req_mode != CCAmode ) return 0 ; break ; default : gcc_unreachable ( ) ; } return ( GET_MODE ( SET_SRC ( set ) ) == set_mode ) ; } </s>

Return true if SET either does n't set the CC register , or else the source and destination have matching CC modes and that CC mode is at least as constrained as REQ_MODE .


<s> void LM32FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * ) const { } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> std :: pair < unsigned , const TargetRegisterClass * > SystemZTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'd' : case 'r' : if ( VT == MVT :: i64 ) return std :: make_pair ( 0U , & SystemZ :: GR64BitRegClass ) ; else if ( VT == MVT :: i128 ) return std :: make_pair ( 0U , & SystemZ :: GR128BitRegClass ) ; return std :: make_pair ( 0U , & SystemZ :: GR32BitRegClass ) ; case 'a' : if ( VT == MVT :: i64 ) return std :: make_pair ( 0U , & SystemZ :: ADDR64BitRegClass ) ; else if ( VT == MVT :: i128 ) return std :: make_pair ( 0U , & SystemZ :: ADDR128BitRegClass ) ; return std :: make_pair ( 0U , & SystemZ :: ADDR32BitRegClass ) ; case 'h' : return std :: make_pair ( 0U , & SystemZ :: GRH32BitRegClass ) ; case 'f' : if ( VT == MVT :: f64 ) return std :: make_pair ( 0U , & SystemZ :: FP64BitRegClass ) ; else if ( VT == MVT :: f128 ) return std :: make_pair ( 0U , & SystemZ :: FP128BitRegClass ) ; return std :: make_pair ( 0U , & SystemZ :: FP32BitRegClass ) ; } } if ( Constraint [ 0 ] == '{' ) { if ( Constraint [ 1 ] == 'r' ) { if ( VT == MVT :: i32 ) return parseRegisterNumber ( Constraint , & SystemZ :: GR32BitRegClass , SystemZMC :: GR32Regs ) ; if ( VT == MVT :: i128 ) return parseRegisterNumber ( Constraint , & SystemZ :: GR128BitRegClass , SystemZMC :: GR128Regs ) ; return parseRegisterNumber ( Constraint , & SystemZ :: GR64BitRegClass , SystemZMC :: GR64Regs ) ; } if ( Constraint [ 1 ] == 'f' ) { if ( VT == MVT :: f32 ) return parseRegisterNumber ( Constraint , & SystemZ :: FP32BitRegClass , SystemZMC :: FP32Regs ) ; if ( VT == MVT :: f128 ) return parseRegisterNumber ( Constraint , & SystemZ :: FP128BitRegClass , SystemZMC :: FP128Regs ) ; return parseRegisterNumber ( Constraint , & SystemZ :: FP64BitRegClass , SystemZMC :: FP64Regs ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> static void nvptx_init_builtins ( void ) { ( nvptx_builtin_decls [ NVPTX_BUILTIN_ ## ID ] \ = add_builtin_function ( "__builtin_nvptx_" NAME , \ build_function_type_list T , \ NVPTX_BUILTIN_ ## ID , BUILT_IN_MD , NULL , NULL ) ) DEF ( SHUFFLE , "shuffle" , ( UINT , UINT , UINT , UINT , NULL_TREE ) ) ; DEF ( SHUFFLELL , "shufflell" , ( LLUINT , LLUINT , UINT , UINT , NULL_TREE ) ) ; DEF ( WORKER_ADDR , "worker_addr" , ( PTRVOID , ST , UINT , UINT , NULL_TREE ) ) ; DEF ( VECTOR_ADDR , "vector_addr" , ( PTRVOID , ST , UINT , UINT , NULL_TREE ) ) ; DEF ( CMP_SWAP , "cmp_swap" , ( UINT , PTRVOID , UINT , UINT , NULL_TREE ) ) ; DEF ( CMP_SWAPLL , "cmp_swapll" , ( LLUINT , PTRVOID , LLUINT , LLUINT , NULL_TREE ) ) ; DEF ( MEMBAR_GL , "membar_gl" , ( VOID , VOID , NULL_TREE ) ) ; DEF ( MEMBAR_CTA , "membar_cta" , ( VOID , VOID , NULL_TREE ) ) ; } </s>

Set up all builtin functions for this target .


<s> void BTFDebug :: beginInstruction ( const MachineInstr * MI ) { DebugHandlerBase :: beginInstruction ( MI ) ; if ( SkipInstruction || MI -> isMetaInstruction ( ) || MI -> getFlag ( MachineInstr :: FrameSetup ) ) return ; if ( MI -> isInlineAsm ( ) ) { unsigned NumDefs = 0 ; for ( ; MI -> getOperand ( NumDefs ) . isReg ( ) && MI -> getOperand ( NumDefs ) . isDef ( ) ; ++ NumDefs ) ; const char * AsmStr = MI -> getOperand ( NumDefs ) . getSymbolName ( ) ; if ( AsmStr [ 0 ] == 0 ) return ; } if ( MI -> getOpcode ( ) == BPF :: LD_imm64 ) { processReloc ( MI -> getOperand ( 1 ) ) ; } else if ( MI -> getOpcode ( ) == BPF :: CORE_MEM || MI -> getOpcode ( ) == BPF :: CORE_ALU32_MEM || MI -> getOpcode ( ) == BPF :: CORE_SHIFT ) { processReloc ( MI -> getOperand ( 3 ) ) ; } else if ( MI -> getOpcode ( ) == BPF :: JAL ) { const MachineOperand & MO = MI -> getOperand ( 0 ) ; if ( MO . isGlobal ( ) ) { processFuncPrototypes ( dyn_cast < Function > ( MO . getGlobal ( ) ) ) ; } } const DebugLoc & DL = MI -> getDebugLoc ( ) ; if ( ! DL || PrevInstLoc == DL ) { if ( LineInfoGenerated == false ) { auto * S = MI -> getMF ( ) -> getFunction ( ) . getSubprogram ( ) ; MCSymbol * FuncLabel = Asm -> getFunctionBegin ( ) ; constructLineInfo ( S , FuncLabel , S -> getLine ( ) , 0 ) ; LineInfoGenerated = true ; } return ; } MCSymbol * LineSym = OS . getContext ( ) . createTempSymbol ( ) ; OS . emitLabel ( LineSym ) ; auto SP = DL . get ( ) -> getScope ( ) -> getSubprogram ( ) ; constructLineInfo ( SP , LineSym , DL . getLine ( ) , DL . getCol ( ) ) ; LineInfoGenerated = true ; PrevInstLoc = DL ; } </s>


<s> static rtx loongarch_allocate_fcc ( machine_mode mode ) { unsigned int regno , count ; gcc_assert ( TARGET_HARD_FLOAT ) ; if ( mode == FCCmode ) count = 1 ; else gcc_unreachable ( ) ; cfun -> machine -> next_fcc += - cfun -> machine -> next_fcc & ( count - 1 ) ; if ( cfun -> machine -> next_fcc > FCC_REG_LAST - FCC_REG_FIRST ) cfun -> machine -> next_fcc = 0 ; regno = FCC_REG_FIRST + cfun -> machine -> next_fcc ; cfun -> machine -> next_fcc += count ; return gen_rtx_REG ( mode , regno ) ; } </s>

Allocate a floating-point condition-code register of mode MODE .


<s> bool PPCCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const auto & DL = F . getParent ( ) -> getDataLayout ( ) ; auto & TLI = * getTLI < PPCTargetLowering > ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned I = 0 ; for ( const auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) . isZero ( ) ) continue ; ArgInfo OrigArg { VRegs [ I ] , Arg , I } ; setArgFlags ( OrigArg , I + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , F . getCallingConv ( ) ) ; ++ I ; } CCAssignFn * AssignFn = TLI . ccAssignFnForCall ( F . getCallingConv ( ) , false , F . isVarArg ( ) ) ; IncomingValueAssigner ArgAssigner ( AssignFn ) ; FormalArgHandler ArgHandler ( MIRBuilder , MRI ) ; return determineAndHandleAssignments ( ArgHandler , ArgAssigner , SplitArgs , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> unsigned X86FastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const auto * CI = dyn_cast < ConstantInt > ( C ) ) return X86MaterializeInt ( CI , VT ) ; else if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return X86MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return X86MaterializeGV ( GV , VT ) ; return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s> bool isToken ( ) const override { return Kind == Token ; } </s>


<s> unsigned getNumberOfRegisters ( bool Vector ) const override { if ( Vector ) { if ( ST -> hasNEON ( ) ) return 32 ; return 0 ; } return 32 ; } </s>


<s>
SDValue
MSP430TargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
if
(
CallConv
==
CallingConv
::
MSP430_INTR
&&
!
Outs
.
empty
(
)
)
report_fatal_error
(
"ISRs cannot return any value"
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_MSP430
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
unsigned
Opc
=
(
CallConv
==
CallingConv
::
MSP430_INTR
MSP430ISD
::
RETI_FLAG
:
MSP430ISD
::
RET_FLAG
)
;
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
Opc
,
dl
,
MVT
::
Other
,
&
RetOps
[
0
]
,
RetOps
.
size
(
)
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void AMDGPUAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { uint16_t * Dst = ( uint16_t * ) ( Data + Fixup . getOffset ( ) ) ; assert ( Fixup . getKind ( ) == FK_PCRel_4 ) ; * Dst = ( Value - 4 ) / 4 ; } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> std :: unique_ptr < MCObjectWriter > LanaiAsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { return createLanaiELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI ( OSType ) ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot ) { if ( ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; if ( CommentStream ) { printAnnotation ( OS , Annot ) ; EmitAnyX86InstComments ( MI , * CommentStream , getRegisterName ) ; } } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static void c4x_reorg ( void ) { rtx insn ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( INSN_P ( insn ) ) { int insn_code_number ; rtx old ; insn_code_number = recog_memoized ( insn ) ; if ( insn_code_number < 0 ) continue ; if ( insn_code_number == CODE_FOR_rptb_end ) c4x_rptb_insert ( insn ) ; old = insn ; if ( ! INSN_DELETED_P ( old ) ) insn = try_split ( PATTERN ( old ) , old , 1 ) ; if ( INSN_DELETED_P ( old ) ) { PUT_CODE ( old , NOTE ) ; NOTE_LINE_NUMBER ( old ) = NOTE_INSN_DELETED ; NOTE_SOURCE_FILE ( old ) = 0 ; } } } } </s>

We need to use direct addressing for large constants and addresses that can not fit within an instruction . We must check for these after after the final jump optimization pass , since this may introduce a local_move insn for a SYMBOL_REF . This pass must come before delayed branch slot filling since it can generate additional instructions . This function also fixes up RTPB style loops that did n't get RC allocated as the loop counter .


"Odd number of callee-saved regs to spill!"

"Expected GPR64 callee-saved register pair!"

"Expected FPR64 callee-saved register pair!"

"Offset out of bounds for STP immediate"

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


"  Preloading operand for insn %d into r%d\n"

Convert operand OP in INSN . We should handle memory operands and uninitialized registers . All other register uses are converted during registers conversion .


<s> static bool arm_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( GET_MODE_CLASS ( mode1 ) == GET_MODE_CLASS ( mode2 ) ) return true ; if ( TARGET_HAVE_MVE && ( VALID_MVE_PRED_MODE ( mode1 ) && VALID_MVE_PRED_MODE ( mode2 ) ) ) return true ; if ( ( TARGET_NEON && ( VALID_NEON_DREG_MODE ( mode1 ) || VALID_NEON_QREG_MODE ( mode1 ) || VALID_NEON_STRUCT_MODE ( mode1 ) ) && ( VALID_NEON_DREG_MODE ( mode2 ) || VALID_NEON_QREG_MODE ( mode2 ) || VALID_NEON_STRUCT_MODE ( mode2 ) ) ) || ( TARGET_HAVE_MVE && ( VALID_MVE_MODE ( mode1 ) || VALID_MVE_STRUCT_MODE ( mode1 ) ) && ( VALID_MVE_MODE ( mode2 ) || VALID_MVE_STRUCT_MODE ( mode2 ) ) ) ) return true ; return false ; } </s>


<s>
void
nvptx_declare_function_name
(
FILE
*
file
,
const
char
*
name
,
const_tree
decl
)
{
tree
fntype
=
TREE_TYPE
(
decl
)
;
tree
result_type
=
TREE_TYPE
(
fntype
)
;
int
argno
=
0
;
std
::
stringstream
s
;
write_fn_proto
(
s
,
true
,
name
,
decl
)
;
s
<<
"{\n"
;
bool
return_in_mem
=
write_return_type
(
s
,
false
,
result_type
)
;
if
(
return_in_mem
)
argno
=
write_arg_type
(
s
,
0
,
argno
,
ptr_type_node
,
true
)
;
tree
args
=
TYPE_ARG_TYPES
(
fntype
)
;
bool
prototyped
=
true
;
if
(
!
args
)
{
args
=
DECL_ARGUMENTS
(
decl
)
;
prototyped
=
false
;
}
for
(
;
args
!=
NULL_TREE
;
args
=
TREE_CHAIN
(
args
)
)
{
tree
type
=
prototyped
TREE_VALUE
(
args
)
:
TREE_TYPE
(
args
)
;
argno
=
write_arg_type
(
s
,
0
,
argno
,
type
,
prototyped
)
;
}
if
(
stdarg_p
(
fntype
)
)
argno
=
write_arg_type
(
s
,
ARG_POINTER_REGNUM
,
argno
,
ptr_type_node
,
true
)
;
if
(
DECL_STATIC_CHAIN
(
decl
)
||
cfun
->
machine
->
has_chain
)
write_arg_type
(
s
,
STATIC_CHAIN_REGNUM
,
DECL_STATIC_CHAIN
(
decl
)
argno
:
1
,
ptr_type_node
,
true
)
;
fprintf
(
file
,
"%s"
,
s
.
str
(
)
.
c_str
(
)
)
;
if
(
cfun
->
machine
->
has_varadic
)
init_frame
(
file
,
STACK_POINTER_REGNUM
,
UNITS_PER_WORD
,
crtl
->
outgoing_args_size
)
;
HOST_WIDE_INT
sz
=
get_frame_size
(
)
;
if
(
sz
||
cfun
->
machine
->
has_chain
)
init_frame
(
file
,
FRAME_POINTER_REGNUM
,
crtl
->
stack_alignment_needed
/
BITS_PER_UNIT
,
sz
)
;
int
maxregs
=
max_reg_num
(
)
;
for
(
int
i
=
LAST_VIRTUAL_REGISTER
+
1
;
i
<
maxregs
;
i
++
)
{
if
(
regno_reg_rtx
[
i
]
!=
const0_rtx
)
{
machine_mode
mode
=
PSEUDO_REGNO_MODE
(
i
)
;
machine_mode
split
=
maybe_split_mode
(
mode
)
;
if
(
split
!=
VOIDmode
)
mode
=
split
;
fprintf
(
file
,
"\t.reg%s "
,
nvptx_ptx_type_from_mode
(
mode
,
true
)
)
;
output_reg
(
file
,
i
,
split
,
2
)
;
fprintf
(
file
,
";\n"
)
;
}
}
if
(
cfun
->
machine
->
axis_predicate
[
0
]
)
nvptx_init_axis_predicate
(
file
,
REGNO
(
cfun
->
machine
->
axis_predicate
[
0
]
)
,
"y"
)
;
if
(
cfun
->
machine
->
axis_predicate
[
1
]
)
nvptx_init_axis_predicate
(
file
,
REGNO
(
cfun
->
machine
->
axis_predicate
[
1
]
)
,
"x"
)
;
}
</s>

Implement ASM_DECLARE_FUNCTION_NAME . Writes the start of a ptx function , including local var decls and copies from the arguments to local regs .


<s> TargetLowering :: AtomicExpansionKind AArch64TargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size > 128 ) return AtomicExpansionKind :: None ; if ( AI -> getOperation ( ) == AtomicRMWInst :: Nand ) return AtomicExpansionKind :: LLSC ; if ( ( AI -> getOperation ( ) == AtomicRMWInst :: And ) || ( AI -> getOperation ( ) == AtomicRMWInst :: Sub ) ) return AtomicExpansionKind :: LLSC ; return ( Subtarget -> hasLSE ( ) && Size < 128 ) ? AtomicExpansionKind :: None : AtomicExpansionKind :: LLSC ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> MachineInstr * X86FrameLowering :: emitStackProbe ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , bool InProlog ) const { const X86Subtarget & STI = MF . getSubtarget < X86Subtarget > ( ) ; if ( STI . isTargetWindowsCoreCLR ( ) ) { if ( InProlog ) { return emitStackProbeInlineStub ( MF , MBB , MBBI , DL , true ) ; } else { return emitStackProbeInline ( MF , MBB , MBBI , DL , false ) ; } } else { return emitStackProbeCall ( MF , MBB , MBBI , DL , InProlog ) ; } } </s>


<s> static rtx m68k_call_m68k_read_tp ( void ) { rtx a0 ; rtx eqv ; rtx_insn * insns ; rtx dest ; start_sequence ( ) ; m68k_libcall_value_in_a0_p = true ; a0 = emit_library_call_value ( m68k_get_m68k_read_tp ( ) , NULL_RTX , LCT_PURE , Pmode , 0 ) ; m68k_libcall_value_in_a0_p = false ; insns = get_insns ( ) ; end_sequence ( ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , const1_rtx ) , UNSPEC_RELOC32 ) ; gcc_assert ( can_create_pseudo_p ( ) ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , a0 , eqv ) ; return dest ; } </s>

Emit instruction sequence that calls __m68k_read_tp . A pseudo register with result of __m68k_read_tp call is returned .


<s> bool ARMBaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( MF . getFunction ( ) -> hasFnAttribute ( "no-realign-stack" ) ) return false ; if ( AFI -> isThumb1OnlyFunction ( ) ) return false ; if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ; if ( MF . getTarget ( ) . getSubtargetImpl ( ) -> getFrameLowering ( ) -> hasReservedCallFrame ( MF ) ) return true ; return MRI -> canReserveReg ( BasePtr ) ; } </s>

True if the stack can be realigned for the target .


<s> int legitimate_pic_operand_p ( rtx op ) { if ( ! SYMBOLIC_CONST ( op ) ) return 1 ; if ( larl_operand ( op , VOIDmode ) ) return 1 ; return 0 ; } </s>

Return true if OP is a legitimate general operand when generating PIC code . It is given that flag_pic is on and that OP satisfies CONSTANT_P or is a CONST_DOUBLE .


<s> unsigned getNumberOfRegisters ( bool Vector ) { if ( Vector ) { if ( ST -> hasNEON ( ) ) return 16 ; if ( ST -> hasMVEIntegerOps ( ) ) return 8 ; return 0 ; } if ( ST -> isThumb1Only ( ) ) return 8 ; return 13 ; } </s>


<s> static int m68k_sched_issue_rate ( void ) { switch ( m68k_sched_cpu ) { case CPU_CFV1 : case CPU_CFV2 : case CPU_CFV3 : return 1 ; case CPU_CFV4 : return 2 ; default : gcc_unreachable ( ) ; return 0 ; } } </s>

Return maximal number of insns that can be scheduled on a single cycle .


<s> static inline tree def_builtin_pure2 ( HOST_WIDE_INT mask , const char * name , enum ix86_builtin_func_type tcode , enum ix86_builtins code ) { tree decl = def_builtin2 ( mask , name , tcode , code ) ; if ( decl ) DECL_PURE_P ( decl ) = 1 ; else ix86_builtins_isa [ ( int ) code ] . pure_p = true ; return decl ; } </s>

Like def_builtin , but also marks the function decl `` pure '' .


<s> Optional < ParamLoadedValue > AArch64InstrInfo :: describeLoadedValue ( const MachineInstr & MI , Register Reg ) const { const MachineFunction * MF = MI . getMF ( ) ; const TargetRegisterInfo * TRI = MF -> getSubtarget ( ) . getRegisterInfo ( ) ; switch ( MI . getOpcode ( ) ) { case AArch64 :: MOVZWi : case AArch64 :: MOVZXi : { if ( ! TRI -> isSuperRegisterEq ( MI . getOperand ( 0 ) . getReg ( ) , Reg ) ) return None ; if ( ! MI . getOperand ( 1 ) . isImm ( ) ) return None ; int64_t Immediate = MI . getOperand ( 1 ) . getImm ( ) ; int Shift = MI . getOperand ( 2 ) . getImm ( ) ; return ParamLoadedValue ( MachineOperand :: CreateImm ( Immediate << Shift ) , nullptr ) ; } case AArch64 :: ORRWrs : case AArch64 :: ORRXrs : return describeORRLoadedValue ( MI , Reg , this , TRI ) ; } return TargetInstrInfo :: describeLoadedValue ( MI , Reg ) ; } </s>

Produce the expression describing the MI loading a value into the physical register Reg .


<s>
void
Thumb1InstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
DebugLoc
::
getUnknownLoc
(
)
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
assert
(
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
PseudoSourceValue
::
getFixedStack
(
FI
)
,
MachineMemOperand
::
MOLoad
,
0
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tRestore
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .

ARM
ARM::tGPRRegisterClass
ARM
"Unknown regclass!"
ARM::tGPRRegisterClass
ARM
0
ARM::tRestore
0


<s>
static
void
ia64_output_function_prologue
(
FILE
*
file
,
HOST_WIDE_INT
size
ATTRIBUTE_UNUSED
)
{
int
mask
,
grsave
,
grsave_prev
;
if
(
current_frame_info
.
need_regstk
)
fprintf
(
file
,
"\t.regstk %d, %d, %d, %d\n"
,
current_frame_info
.
n_input_regs
,
current_frame_info
.
n_local_regs
,
current_frame_info
.
n_output_regs
,
current_frame_info
.
n_rotate_regs
)
;
if
(
!
flag_unwind_tables
&&
(
!
flag_exceptions
||
USING_SJLJ_EXCEPTIONS
)
)
return
;
mask
=
0
;
grsave
=
grsave_prev
=
0
;
if
(
current_frame_info
.
reg_save_b0
!=
0
)
{
mask
|=
8
;
grsave
=
grsave_prev
=
current_frame_info
.
reg_save_b0
;
}
if
(
current_frame_info
.
reg_save_ar_pfs
!=
0
&&
(
grsave_prev
==
0
||
current_frame_info
.
reg_save_ar_pfs
==
grsave_prev
+
1
)
)
{
mask
|=
4
;
if
(
grsave_prev
==
0
)
grsave
=
current_frame_info
.
reg_save_ar_pfs
;
grsave_prev
=
current_frame_info
.
reg_save_ar_pfs
;
}
if
(
current_frame_info
.
reg_fp
!=
0
&&
(
grsave_prev
==
0
||
current_frame_info
.
reg_fp
==
grsave_prev
+
1
)
)
{
mask
|=
2
;
if
(
grsave_prev
==
0
)
grsave
=
HARD_FRAME_POINTER_REGNUM
;
grsave_prev
=
current_frame_info
.
reg_fp
;
}
if
(
current_frame_info
.
reg_save_pr
!=
0
&&
(
grsave_prev
==
0
||
current_frame_info
.
reg_save_pr
==
grsave_prev
+
1
)
)
{
mask
|=
1
;
if
(
grsave_prev
==
0
)
grsave
=
current_frame_info
.
reg_save_pr
;
}
if
(
mask
&&
TARGET_GNU_AS
)
fprintf
(
file
,
"\t.prologue %d, %d\n"
,
mask
,
ia64_dbx_register_number
(
grsave
)
)
;
else
fputs
(
"\t.prologue\n"
,
file
)
;
if
(
current_frame_info
.
spill_cfa_off
!=
16
)
fprintf
(
file
,
"\t.spill %ld\n"
,
(
long
)
(
current_frame_info
.
spill_cfa_off
+
current_frame_info
.
spill_size
)
)
;
}
</s>


<s> SDValue SITargetLowering :: handleD16VData ( SDValue VData , SelectionDAG & DAG ) const { EVT StoreVT = VData . getValueType ( ) ; if ( ! StoreVT . isVector ( ) ) return VData ; SDLoc DL ( VData ) ; unsigned NumElements = StoreVT . getVectorNumElements ( ) ; if ( Subtarget -> hasUnpackedD16VMem ( ) ) { EVT IntStoreVT = StoreVT . changeTypeToInteger ( ) ; SDValue IntVData = DAG . getNode ( ISD :: BITCAST , DL , IntStoreVT , VData ) ; EVT EquivStoreVT = EVT :: getVectorVT ( * DAG . getContext ( ) , MVT :: i32 , NumElements ) ; SDValue ZExt = DAG . getNode ( ISD :: ZERO_EXTEND , DL , EquivStoreVT , IntVData ) ; return DAG . UnrollVectorOp ( ZExt . getNode ( ) ) ; } else if ( NumElements == 3 ) { EVT IntStoreVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , StoreVT . getStoreSizeInBits ( ) ) ; SDValue IntVData = DAG . getNode ( ISD :: BITCAST , DL , IntStoreVT , VData ) ; EVT WidenedStoreVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StoreVT . getVectorElementType ( ) , NumElements + 1 ) ; EVT WidenedIntVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , WidenedStoreVT . getStoreSizeInBits ( ) ) ; SDValue ZExt = DAG . getNode ( ISD :: ZERO_EXTEND , DL , WidenedIntVT , IntVData ) ; return DAG . getNode ( ISD :: BITCAST , DL , WidenedStoreVT , ZExt ) ; } assert ( isTypeLegal ( StoreVT ) ) ; return VData ; } </s>

Handle register layout difference for f16 images for some subtargets .


<s> bool X86AsmParser :: parsePrimaryExpr ( const MCExpr * & Res , SMLoc & EndLoc ) { MCAsmParser & Parser = getParser ( ) ; if ( Parser . parsePrimaryExpr ( Res , EndLoc ) ) { SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; unsigned RegNo ; bool TryRegParse = getTok ( ) . is ( AsmToken :: Percent ) || ( isParsingIntelSyntax ( ) && getTok ( ) . is ( AsmToken :: Identifier ) ) ; if ( ! TryRegParse || ParseRegister ( RegNo , StartLoc , EndLoc ) ) return true ; Parser . clearPendingErrors ( ) ; Res = X86MCExpr :: create ( RegNo , Parser . getContext ( ) ) ; return false ; } return false ; } </s>


<s> bool PPCFastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { return MI && OpNo && LI && false ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s>
void
AVRAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsPCRel
)
const
{
adjustFixupValue
(
Fixup
,
Target
,
Value
,
&
Asm
.
getContext
(
)
)
;
if
(
Value
==
0
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
auto
NumBits
=
Info
.
TargetSize
+
Info
.
TargetOffset
;
auto
NumBytes
=
(
NumBits
/
8
)
+
(
(
NumBits
%
8
)
==
0
0
:
1
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
<
NumBytes
;
++
i
)
{
uint8_t
mask
=
(
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
)
;
Data
[
Offset
+
i
]
|=
mask
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void cris_conditional_register_usage ( void ) { if ( flag_pic ) fixed_regs [ PIC_OFFSET_TABLE_REGNUM ] = call_used_regs [ PIC_OFFSET_TABLE_REGNUM ] = 1 ; if ( TARGET_HAS_MUL_INSNS ) fixed_regs [ CRIS_MOF_REGNUM ] = 0 ; if ( cris_cpu_version < 8 ) reg_names [ CRIS_CC0_REGNUM ] = "ccr" ; } </s>


<s>
bool
RISCVSExtWRemoval
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
||
DisableSExtWRemoval
)
return
false
;
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
const
RISCVSubtarget
&
ST
=
MF
.
getSubtarget
<
RISCVSubtarget
>
(
)
;
if
(
!
ST
.
is64Bit
(
)
)
return
false
;
SmallPtrSet
<
MachineInstr
*
,
4
>
SExtWRemovalCands
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
for
(
auto
I
=
MBB
.
begin
(
)
,
IE
=
MBB
.
end
(
)
;
I
!=
IE
;
)
{
MachineInstr
*
MI
=
&
*
I
++
;
if
(
MI
->
getOpcode
(
)
!=
RISCV
::
ADDIW
||
!
MI
->
getOperand
(
2
)
.
isImm
(
)
||
MI
->
getOperand
(
2
)
.
getImm
(
)
!=
0
||
!
MI
->
getOperand
(
1
)
.
isReg
(
)
)
continue
;
Register
SrcReg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
if
(
!
SrcReg
.
isVirtual
(
)
)
continue
;
SExtWRemovalCands
.
insert
(
MI
)
;
}
}
bool
MadeChange
=
false
;
for
(
auto
MI
:
SExtWRemovalCands
)
{
SmallPtrSet
<
MachineInstr
*
,
4
>
FixableDef
;
Register
SrcReg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
MachineInstr
&
SrcMI
=
*
MRI
.
getVRegDef
(
SrcReg
)
;
if
(
!
isSignExtendedW
(
SrcMI
,
MRI
,
FixableDef
)
)
continue
;
Register
DstReg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
if
(
!
MRI
.
constrainRegClass
(
SrcReg
,
MRI
.
getRegClass
(
DstReg
)
)
)
continue
;
for
(
MachineInstr
*
Fixable
:
FixableDef
)
{
MachineBasicBlock
&
MBB
=
*
Fixable
->
getParent
(
)
;
const
DebugLoc
&
DL
=
Fixable
->
getDebugLoc
(
)
;
unsigned
Code
=
getWOp
(
Fixable
->
getOpcode
(
)
)
;
MachineInstrBuilder
Replacement
=
BuildMI
(
MBB
,
Fixable
,
DL
,
ST
.
getInstrInfo
(
)
->
get
(
Code
)
)
;
for
(
auto
Op
:
Fixable
->
operands
(
)
)
Replacement
.
add
(
Op
)
;
for
(
auto
Op
:
Fixable
->
memoperands
(
)
)
Replacement
.
addMemOperand
(
Op
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Replacing "
<<
*
Fixable
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"     with "
<<
*
Replacement
)
;
Fixable
->
eraseFromParent
(
)
;
++
NumTransformedToWInstrs
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Removing redundant sign-extension\n"
)
;
MRI
.
replaceRegWith
(
DstReg
,
SrcReg
)
;
MRI
.
clearKillFlags
(
SrcReg
)
;
MI
->
eraseFromParent
(
)
;
++
NumRemovedSExtW
;
MadeChange
=
true
;
}
return
MadeChange
;
}
</s>

runOnMachineFunction - Emit the function body .


<s>
void
GBZ80RegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected SPAdj value"
)
;
MachineInstr
&
MI
=
*
II
;
DebugLoc
dl
=
MI
.
getDebugLoc
(
)
;
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
GBZ80TargetMachine
&
TM
=
(
const
GBZ80TargetMachine
&
)
MF
.
getTarget
(
)
;
const
TargetInstrInfo
&
TII
=
*
TM
.
getSubtargetImpl
(
)
->
getInstrInfo
(
)
;
const
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
const
TargetFrameLowering
*
TFI
=
TM
.
getSubtargetImpl
(
)
->
getFrameLowering
(
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
int
Offset
=
MFI
.
getObjectOffset
(
FrameIndex
)
;
Offset
+=
MFI
.
getStackSize
(
)
TFI
->
getOffsetOfLocalArea
(
)
;
assert
(
MI
.
getOpcode
(
)
==
GB
::
FRMIDX
||
MI
.
getOpcode
(
)
==
GB
::
LD8_FI
||
MI
.
getOpcode
(
)
==
GB
::
ST8_FI
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToImmediate
(
Offset
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static void emit_vrsave_prologue ( rs6000_stack_t * info , int save_regno , HOST_WIDE_INT frame_off , rtx frame_reg_rtx ) { rtx reg = gen_rtx_REG ( SImode , save_regno ) ; rtx vrsave = gen_rtx_REG ( SImode , VRSAVE_REGNO ) ; if ( TARGET_MACHO ) emit_insn ( gen_get_vrsave_internal ( reg ) ) ; else emit_insn ( gen_rtx_SET ( reg , vrsave ) ) ; int offset = info -> vrsave_save_offset + frame_off ; emit_insn ( gen_frame_store ( reg , frame_reg_rtx , offset ) ) ; emit_insn ( gen_iorsi3 ( reg , reg , GEN_INT ( info -> vrsave_mask ) ) ) ; emit_insn ( generate_set_vrsave ( reg , info , 0 ) ) ; } </s>

VRSAVE is a bit vector representing which AltiVec registers are used . The OS uses this to determine which vector registers to save on a context switch . We need to save VRSAVE on the stack frame , add whatever AltiVec registers we used in this function , and do the corresponding magic in the epilogue .


<s> static bool arm_evpc_neon_vzip ( struct expand_vec_perm_d * d ) { unsigned int i , high , mask , nelt = d -> perm . length ( ) ; rtx out0 , out1 , in0 , in1 ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; int first_elem ; bool is_swapped ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; is_swapped = BYTES_BIG_ENDIAN ; first_elem = d -> perm [ neon_endian_lane_map ( d -> vmode , 0 ) ^ is_swapped ] ; high = nelt / 2 ; if ( first_elem == neon_endian_lane_map ( d -> vmode , high ) ) ; else if ( first_elem == neon_endian_lane_map ( d -> vmode , 0 ) ) high = 0 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt / 2 ; i ++ ) { unsigned elt = neon_pair_endian_lane_map ( d -> vmode , i + high ) & mask ; if ( d -> perm [ neon_pair_endian_lane_map ( d -> vmode , 2 * i + is_swapped ) ] != elt ) return false ; elt = neon_pair_endian_lane_map ( d -> vmode , i + nelt + high ) & mask ; if ( d -> perm [ neon_pair_endian_lane_map ( d -> vmode , 2 * i + ! is_swapped ) ] != elt ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case E_V16QImode : gen = gen_neon_vzipv16qi_internal ; break ; case E_V8QImode : gen = gen_neon_vzipv8qi_internal ; break ; case E_V8HImode : gen = gen_neon_vzipv8hi_internal ; break ; case E_V4HImode : gen = gen_neon_vzipv4hi_internal ; break ; case E_V8HFmode : gen = gen_neon_vzipv8hf_internal ; break ; case E_V4HFmode : gen = gen_neon_vzipv4hf_internal ; break ; case E_V4SImode : gen = gen_neon_vzipv4si_internal ; break ; case E_V2SImode : gen = gen_neon_vzipv2si_internal ; break ; case E_V2SFmode : gen = gen_neon_vzipv2sf_internal ; break ; case E_V4SFmode : gen = gen_neon_vzipv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d -> op1 ; if ( is_swapped ) std :: swap ( in0 , in1 ) ; out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( high ) std :: swap ( out0 , out1 ) ; emit_insn ( gen ( out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s>
void
ARCInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
MCRegister
DestReg
,
MCRegister
SrcReg
,
bool
KillSrc
)
const
{
assert
(
ARC
::
GPR32RegClass
.
contains
(
SrcReg
)
&&
"Only GPR32 src copy supported."
)
;
assert
(
ARC
::
GPR32RegClass
.
contains
(
DestReg
)
&&
"Only GPR32 dest copy supported."
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARC
::
MOV_rr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> bool aarch64_use_return_insn_p ( void ) { if ( ! reload_completed ) return false ; if ( crtl -> profile ) return false ; return known_eq ( cfun -> machine -> frame . frame_size , 0 ) ; } </s>

Return TRUE if we can use a simple_return insn . This function checks whether the callee saved stack is empty , which means no restore actions are need . The pro_and_epilogue will use this to check whether shrink-wrapping opt is feasible .


<s> static void nds32_emit_isr_jmptbl_section ( int vector_id ) { char section_name [ 100 ] ; char symbol_name [ 100 ] ; snprintf ( section_name , sizeof ( section_name ) , ".nds32_jmptbl.%02d" , vector_id ) ; snprintf ( symbol_name , sizeof ( symbol_name ) , "_nds32_jmptbl_%02d" , vector_id ) ; nds32_emit_section_head_template ( section_name , symbol_name , 2 , true ) ; fprintf ( asm_out_file , "\t.word\t%s\n" , nds32_isr_vectors [ vector_id ] . func_name ) ; nds32_emit_section_tail_template ( symbol_name ) ; } </s>

Function to emit isr jump table section .


<s>
void
PPCMIPeephole
::
initialize
(
MachineFunction
&
MFParm
)
{
MF
=
&
MFParm
;
MRI
=
&
MF
->
getRegInfo
(
)
;
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
MPDT
=
&
getAnalysis
<
MachinePostDominatorTree
>
(
)
;
MBFI
=
&
getAnalysis
<
MachineBlockFrequencyInfo
>
(
)
;
EntryFreq
=
MBFI
->
getEntryFreq
(
)
;
TII
=
MF
->
getSubtarget
<
PPCSubtarget
>
(
)
.
getInstrInfo
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"*** PowerPC MI peephole pass ***\n\n"
)
;
LLVM_DEBUG
(
MF
->
dump
(
)
)
;
}
</s>

Initialize the strategy after building the DAG for a new region .

PowerPC
PPC
PPC
"*** PowerPC MI peephole pass ***\n\n"


<s> static void emit_pop_byte ( unsigned regno ) { rtx mem , reg ; mem = gen_rtx_PRE_INC ( HImode , stack_pointer_rtx ) ; mem = gen_frame_mem ( QImode , mem ) ; reg = gen_rtx_REG ( QImode , regno ) ; emit_insn ( gen_rtx_SET ( VOIDmode , reg , mem ) ) ; } </s>

Helper for avr_expand_epilogue . Emit a pop of a byte register .


<s> void GCNPassConfig :: addOptimizedRegAlloc ( FunctionPass * RegAllocPass ) { insertPass ( & LiveVariablesID , & SIFixSGPRLiveRangesID , false ) ; TargetPassConfig :: addOptimizedRegAlloc ( RegAllocPass ) ; } </s>

addOptimizedRegAlloc - Add passes related to register allocation .


<s> void MipsSETargetLowering :: getOpndList ( SmallVectorImpl < SDValue > & Ops , std :: deque < std :: pair < unsigned , SDValue > > & RegsToPass , bool IsPICCall , bool GlobalOrExternal , bool InternalLinkage , bool IsCallReloc , CallLoweringInfo & CLI , SDValue Callee , SDValue Chain , unsigned nargs ) const { Ops . push_back ( Callee ) ; MipsTargetLowering :: getOpndList ( Ops , RegsToPass , IsPICCall , GlobalOrExternal , InternalLinkage , IsCallReloc , CLI , Callee , Chain , nargs ) ; } </s>

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


<s> bool AMDGPUTargetLowering :: isFNegFree ( EVT VT ) const { assert ( VT . isFloatingPoint ( ) ) ; return VT == MVT :: f32 ; } </s>

Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation .


<s> static rtx_insn * aarch64_speculation_establish_tracker ( ) { rtx sp = gen_rtx_REG ( DImode , SP_REGNUM ) ; rtx tracker = gen_rtx_REG ( DImode , SPECULATION_TRACKER_REGNUM ) ; start_sequence ( ) ; rtx cc = aarch64_gen_compare_reg ( EQ , sp , const0_rtx ) ; emit_insn ( gen_cstoredi_neg ( tracker , gen_rtx_NE ( CCmode , cc , const0_rtx ) , cc ) ) ; rtx_insn * seq = get_insns ( ) ; end_sequence ( ) ; return seq ; } </s>

Generate a code sequence to establish the tracker variable from the contents of SP .


<s> EVT AArch64TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { bool Fast ; const Function & F = MF . getFunction ( ) ; if ( Subtarget -> hasFPARMv8 ( ) && ! IsMemset && Size >= 16 && ! F . hasFnAttribute ( Attribute :: NoImplicitFloat ) && ( memOpAlign ( SrcAlign , DstAlign , 16 ) || ( allowsMisalignedMemoryAccesses ( MVT :: f128 , 0 , 1 , & Fast ) && Fast ) ) ) return MVT :: f128 ; if ( Size >= 8 && ( memOpAlign ( SrcAlign , DstAlign , 8 ) || ( allowsMisalignedMemoryAccesses ( MVT :: i64 , 0 , 1 , & Fast ) && Fast ) ) ) return MVT :: i64 ; if ( Size >= 4 && ( memOpAlign ( SrcAlign , DstAlign , 4 ) || ( allowsMisalignedMemoryAccesses ( MVT :: i32 , 0 , 1 , & Fast ) && Fast ) ) ) return MVT :: i32 ; return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> void MipsAsmPrinter :: emitFrameDirective ( ) { const TargetRegisterInfo & RI = * MF -> getSubtarget ( ) . getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) -> getStackSize ( ) ; getTargetStreamer ( ) . emitFrame ( stackReg , stackSize , returnReg ) ; } </s>


<s> void sh_expand_prologue ( void ) { int save_flags = target_flags ; tree sp_switch_attr = lookup_attribute ( "sp_switch" , DECL_ATTRIBUTES ( current_function_decl ) ) ; current_function_interrupt = sh_cfun_interrupt_handler_p ( ) ; int pretend_args = crtl -> args . pretend_args_size ; if ( TARGET_VARARGS_PRETEND_ARGS ( current_function_decl ) && ( NPARM_REGS ( SImode ) > crtl -> args . info . arg_count [ ( int ) SH_ARG_INT ] ) ) pretend_args = 0 ; output_stack_adjust ( - pretend_args , stack_pointer_rtx , 0 , NULL , true ) ; int stack_usage = pretend_args ; if ( cfun -> stdarg ) { if ( TARGET_VARARGS_PRETEND_ARGS ( current_function_decl ) ) { for ( int i = 0 ; i < NPARM_REGS ( SImode ) ; i ++ ) { int rn = NPARM_REGS ( SImode ) + FIRST_PARM_REG - i - 1 ; if ( i >= ( NPARM_REGS ( SImode ) - crtl -> args . info . arg_count [ ( int ) SH_ARG_INT ] ) ) break ; push ( rn ) ; stack_usage += GET_MODE_SIZE ( SImode ) ; } } } if ( sp_switch_attr ) { rtx lab , newsrc ; tree arg = TREE_VALUE ( TREE_VALUE ( sp_switch_attr ) ) ; const char * s = ggc_strdup ( TREE_STRING_POINTER ( arg ) ) ; rtx sp_switch = gen_rtx_SYMBOL_REF ( Pmode , s ) ; lab = add_constant ( sp_switch , SImode , 0 ) ; newsrc = gen_rtx_LABEL_REF ( VOIDmode , lab ) ; emit_insn ( gen_sp_switch_1 ( newsrc ) ) ; } HARD_REG_SET live_regs_mask ; int d = calc_live_regs ( & live_regs_mask ) ; if ( target_flags != save_flags && ! current_function_interrupt ) emit_insn ( gen_toggle_sz ( ) ) ; push_regs ( & live_regs_mask , current_function_interrupt ) ; stack_usage += d ; if ( flag_pic && ! TARGET_FDPIC && df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) ) emit_insn ( gen_GOTaddr2picreg ( const0_rtx ) ) ; if ( target_flags != save_flags && ! current_function_interrupt ) emit_insn ( gen_toggle_sz ( ) ) ; target_flags = save_flags ; output_stack_adjust ( - rounded_frame_size ( d ) , stack_pointer_rtx , 0 , NULL , true ) ; stack_usage += rounded_frame_size ( d ) ; if ( frame_pointer_needed ) emit_frame_insn ( GEN_MOV ( hard_frame_pointer_rtx , stack_pointer_rtx ) ) ; if ( crtl -> profile || flag_exceptions || flag_unwind_tables ) emit_insn ( gen_blockage ( ) ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = stack_usage ; } </s>


"InsertBranch must not be told to insert a fallthrough"

"M68k branch conditions have one component!"

"Unconditional branch with multiple successors!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> const TPCInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> bool mayLoad ( ) const { return Load ; } </s>

Return true if this instruction could possibly read memory .


<s> BitVector MSP430RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; Reserved . set ( MSP430 :: PCB ) ; Reserved . set ( MSP430 :: SPB ) ; Reserved . set ( MSP430 :: SRB ) ; Reserved . set ( MSP430 :: CGB ) ; Reserved . set ( MSP430 :: PCW ) ; Reserved . set ( MSP430 :: SPW ) ; Reserved . set ( MSP430 :: SRW ) ; Reserved . set ( MSP430 :: CGW ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( MSP430 :: FPB ) ; Reserved . set ( MSP430 :: FPW ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static rtx ia64_function_incoming_arg ( cumulative_args_t cum , const function_arg_info & arg ) { return ia64_function_arg_1 ( cum , arg , true ) ; } </s>

Implement TARGET_FUNCION_INCOMING_ARG target hook .


<s> bool SIPeepholeSDWA :: runOnMachineFunction ( MachineFunction & MF ) { const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; if ( ! ST . hasSDWA ( ) || ! AMDGPU :: isVI ( ST ) ) { return false ; } MRI = & MF . getRegInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; TII = ST . getInstrInfo ( ) ; std :: unordered_map < MachineInstr * , SDWAOperandsVector > PotentialMatches ; for ( MachineBasicBlock & MBB : MF ) { SDWAOperands . clear ( ) ; matchSDWAOperands ( MBB ) ; PotentialMatches . clear ( ) ; for ( auto & OperandPair : SDWAOperands ) { auto & Operand = OperandPair . second ; MachineInstr * PotentialMI = Operand -> potentialToConvert ( TII ) ; if ( PotentialMI ) { PotentialMatches [ PotentialMI ] . push_back ( std :: move ( Operand ) ) ; } } for ( auto & PotentialPair : PotentialMatches ) { MachineInstr & PotentialMI = * PotentialPair . first ; convertToSDWA ( PotentialMI , PotentialPair . second ) ; } } return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool TPCAAResult :: pointsToConstantMemory ( const MemoryLocation & Loc , AAQueryInfo & QInfo , bool OrLocal ) { return AAResultBase :: pointsToConstantMemory ( Loc , QInfo , OrLocal ) ; } </s>

A convenience wrapper around the primary pointsToConstantMemory interface .


<s> static inline CvtDirection getEmptyKey ( ) { return CvtDirection ( ) ; } </s>

Empty key : no key should be generated that has no DILocalVariable .


<s> unsigned HSAILInstrInfo :: isStoreToStackSlotPostFE ( const MachineInstr * MI , int & FrameIndex ) const { return isStoreToStackSlot ( MI , FrameIndex ) ; } </s>

isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s> void WebAssemblyAsmPrinter :: emitGlobalVariable ( const GlobalVariable * GV ) { if ( ! WebAssembly :: isWasmVarAddressSpace ( GV -> getAddressSpace ( ) ) ) { AsmPrinter :: emitGlobalVariable ( GV ) ; return ; } assert ( ! GV -> isThreadLocal ( ) ) ; MCSymbolWasm * Sym = cast < MCSymbolWasm > ( getSymbol ( GV ) ) ; if ( ! Sym -> getType ( ) ) { const WebAssemblyTargetLowering & TLI = * Subtarget -> getTargetLowering ( ) ; SmallVector < MVT , 1 > VTs ; Type * GlobalVT = GV -> getValueType ( ) ; computeLegalValueVTs ( TLI , GV -> getParent ( ) -> getContext ( ) , GV -> getParent ( ) -> getDataLayout ( ) , GlobalVT , VTs ) ; WebAssembly :: wasmSymbolSetType ( Sym , GlobalVT , VTs ) ; } if ( Sym -> isTable ( ) ) { getTargetStreamer ( ) -> emitTableType ( Sym ) ; return ; } emitVisibility ( Sym , GV -> getVisibility ( ) , ! GV -> isDeclaration ( ) ) ; if ( GV -> hasInitializer ( ) ) { assert ( getSymbolPreferLocal ( * GV ) == Sym ) ; emitLinkage ( GV , Sym ) ; getTargetStreamer ( ) -> emitGlobalType ( Sym ) ; OutStreamer -> emitLabel ( Sym ) ; OutStreamer -> AddBlankLine ( ) ; } } </s>

Emit the specified global variable to the .s file .

WebAssembly WebAssembly WebAssembly::isWasmVarAddressSpace WebAssembly 1 WebAssembly::wasmSymbolSetType


<s> EVT SITargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { return MVT :: i1 ; } </s>

Return the value type to use for ISD : :SETCC .


<s> SDValue GBZ80TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; auto CCFunction = CCAssignFnForReturn ( CallConv ) ; CCInfo . AnalyzeCallResult ( Ins , CCFunction ) ; if ( RVLocs . size ( ) > 1 ) { std :: reverse ( RVLocs . begin ( ) , RVLocs . end ( ) ) ; } for ( CCValAssign const & RVLoc : RVLocs ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLoc . getLocReg ( ) , RVLoc . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static bool c6x_vector_mode_supported_p ( machine_mode mode ) { switch ( mode ) { case V2HImode : case V4QImode : case V2SImode : case V4HImode : case V8QImode : return true ; default : return false ; } } </s>

Implements target hook vector_mode_supported_p .


"OffsetRegShifted must imply OffsetIsReg!"

"Offset must exists unless register offset is used!"

"Cannot have shift amount without shifted register offset!"

"Cannot have expression offset and register offset!"


<s> void GCNIterativeScheduler :: enterRegion ( MachineBasicBlock * BB , MachineBasicBlock :: iterator Begin , MachineBasicBlock :: iterator End , unsigned NumRegionInstrs ) { BaseClass :: enterRegion ( BB , Begin , End , NumRegionInstrs ) ; if ( NumRegionInstrs > 2 ) { Regions . push_back ( new ( Alloc . Allocate ( ) ) Region { Begin , End , NumRegionInstrs , getRegionPressure ( Begin , End ) , nullptr } ) ; } } </s>

Implement the ScheduleDAGInstrs interface for handling the next scheduling region .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> bool TeakTargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const { return Imm >= - 32768 && Imm <= 32767 ; } </s>

Return true if the specified immediate is legal icmp immediate , that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register .


<s> void MipsTargetELFStreamer :: finish ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; const MCObjectFileInfo & OFI = * MCA . getContext ( ) . getObjectFileInfo ( ) ; MCSectionData & TextSectionData = MCA . getOrCreateSectionData ( * OFI . getTextSection ( ) ) ; MCSectionData & DataSectionData = MCA . getOrCreateSectionData ( * OFI . getDataSection ( ) ) ; MCSectionData & BSSSectionData = MCA . getOrCreateSectionData ( * OFI . getBSSSection ( ) ) ; TextSectionData . setAlignment ( std :: max ( 16u , TextSectionData . getAlignment ( ) ) ) ; DataSectionData . setAlignment ( std :: max ( 16u , DataSectionData . getAlignment ( ) ) ) ; BSSSectionData . setAlignment ( std :: max ( 16u , BSSSectionData . getAlignment ( ) ) ) ; MipsELFStreamer & MEF = static_cast < MipsELFStreamer & > ( Streamer ) ; MEF . EmitMipsOptionRecords ( ) ; emitMipsAbiFlags ( ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .

Mips Mips 16u 16u 16u Mips Mips Mips Mips


<s> SCANode * getRoot ( ) const { return Root ; } </s>

Similar to getMemoryRoot , but also flushes PendingConstrainedFP ( Strict ) items .


<s>
const
RegisterBank
&
AArch64RegisterBankInfo
::
getRegBankFromRegClass
(
const
TargetRegisterClass
&
RC
,
LLT
)
const
{
switch
(
RC
.
getID
(
)
)
{
case
AArch64
::
FPR8RegClassID
:
case
AArch64
::
FPR16RegClassID
:
case
AArch64
::
FPR16_loRegClassID
:
case
AArch64
::
FPR32_with_hsub_in_FPR16_loRegClassID
:
case
AArch64
::
FPR32RegClassID
:
case
AArch64
::
FPR64RegClassID
:
case
AArch64
::
FPR64_loRegClassID
:
case
AArch64
::
FPR128RegClassID
:
case
AArch64
::
FPR128_loRegClassID
:
case
AArch64
::
DDRegClassID
:
case
AArch64
::
DDDRegClassID
:
case
AArch64
::
DDDDRegClassID
:
case
AArch64
::
QQRegClassID
:
case
AArch64
::
QQQRegClassID
:
case
AArch64
::
QQQQRegClassID
:
return
getRegBank
(
AArch64
::
FPRRegBankID
)
;
case
AArch64
::
GPR32commonRegClassID
:
case
AArch64
::
GPR32RegClassID
:
case
AArch64
::
GPR32spRegClassID
:
case
AArch64
::
GPR32sponlyRegClassID
:
case
AArch64
::
GPR32argRegClassID
:
case
AArch64
::
GPR32allRegClassID
:
case
AArch64
::
GPR64commonRegClassID
:
case
AArch64
::
GPR64RegClassID
:
case
AArch64
::
GPR64spRegClassID
:
case
AArch64
::
GPR64sponlyRegClassID
:
case
AArch64
::
GPR64argRegClassID
:
case
AArch64
::
GPR64allRegClassID
:
case
AArch64
::
GPR64noipRegClassID
:
case
AArch64
::
GPR64common_and_GPR64noipRegClassID
:
case
AArch64
::
GPR64noip_and_tcGPR64RegClassID
:
case
AArch64
::
tcGPR64RegClassID
:
case
AArch64
::
rtcGPR64RegClassID
:
case
AArch64
::
WSeqPairsClassRegClassID
:
case
AArch64
::
XSeqPairsClassRegClassID
:
case
AArch64
::
MatrixIndexGPR32_12_15RegClassID
:
return
getRegBank
(
AArch64
::
GPRRegBankID
)
;
case
AArch64
::
CCRRegClassID
:
return
getRegBank
(
AArch64
::
CCRegBankID
)
;
default
:
llvm_unreachable
(
"Register class not supported"
)
;
}
}
</s>


<s> int HexagonInstrInfo :: getOperandLatency ( const InstrItineraryData * ItinData , const MachineInstr & DefMI , unsigned DefIdx , const MachineInstr & UseMI , unsigned UseIdx ) const { const HexagonRegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; MachineOperand DefMO = DefMI . getOperand ( DefIdx ) ; if ( HRI . isPhysicalRegister ( DefMO . getReg ( ) ) ) { if ( DefMO . isImplicit ( ) ) { for ( MCSuperRegIterator SR ( DefMO . getReg ( ) , & HRI ) ; SR . isValid ( ) ; ++ SR ) { int Idx = DefMI . findRegisterDefOperandIdx ( * SR , false , false , & HRI ) ; if ( Idx != - 1 ) { DefIdx = Idx ; break ; } } } MachineOperand UseMO = UseMI . getOperand ( UseIdx ) ; if ( UseMO . isImplicit ( ) ) { for ( MCSuperRegIterator SR ( UseMO . getReg ( ) , & HRI ) ; SR . isValid ( ) ; ++ SR ) { int Idx = UseMI . findRegisterUseOperandIdx ( * SR , false , & HRI ) ; if ( Idx != - 1 ) { UseIdx = Idx ; break ; } } } } return TargetInstrInfo :: getOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ; } </s>

Compute and return the use operand latency of a given pair of def and use .


<s> bool NVPTXTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( AM . BaseGV ) { if ( AM . BaseOffs || AM . HasBaseReg || AM . Scale ) return false ; return true ; } switch ( AM . Scale ) { case 0 : break ; case 1 : if ( AM . HasBaseReg ) return false ; break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> SDValue M680x0TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_M680x0 ) ; for ( unsigned i = 0 , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; EVT CopyVT = VA . getLocVT ( ) ; Chain = DAG . getCopyFromReg ( Chain , DL , VA . getLocReg ( ) , CopyVT , InFlag ) . getValue ( 1 ) ; SDValue Val = Chain . getValue ( 0 ) ; if ( VA . isExtInLoc ( ) && VA . getValVT ( ) . getScalarType ( ) == MVT :: i1 ) Val = DAG . getNode ( ISD :: TRUNCATE , DL , VA . getValVT ( ) , Val ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Val ) ; } return Chain ; } </s>


<s> bool isLegalMaskedStore ( Type * DataType , Align Alignment ) { return isLegalMaskedLoadStore ( DataType , Alignment ) ; } </s>

Return true if the target supports masked store .


<s> bool SIInstrInfo :: isLegalRegOperand ( const MachineRegisterInfo & MRI , const MCOperandInfo & OpInfo , const MachineOperand & MO ) const { if ( ! MO . isReg ( ) ) return false ; Register Reg = MO . getReg ( ) ; const TargetRegisterClass * DRC = RI . getRegClass ( OpInfo . RegClass ) ; if ( Reg . isPhysical ( ) ) return DRC -> contains ( Reg ) ; const TargetRegisterClass * RC = MRI . getRegClass ( Reg ) ; if ( MO . getSubReg ( ) ) { const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const TargetRegisterClass * SuperRC = RI . getLargestLegalSuperClass ( RC , * MF ) ; if ( ! SuperRC ) return false ; DRC = RI . getMatchingSuperRegClass ( SuperRC , DRC , MO . getSubReg ( ) ) ; if ( ! DRC ) return false ; } return RC -> hasSuperClassEq ( DRC ) ; } </s>

Check if MO ( a register operand ) is a legal register for the given operand description .


<s> bool AMDGPUPromoteAlloca :: doInitialization ( Module & M ) { if ( ! TM ) return false ; Mod = & M ; MDBuilder MDB ( Mod -> getContext ( ) ) ; MaxWorkGroupSizeRange = MDB . createRange ( APInt ( 32 , 0 ) , APInt ( 32 , 2048 ) ) ; const Triple & TT = TM -> getTargetTriple ( ) ; IsAMDGCN = TT . getArch ( ) == Triple :: amdgcn ; IsAMDHSA = TT . getOS ( ) == Triple :: AMDHSA ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> void CSKYFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const CSKYRegisterInfo * RI = STI . getRegisterInfo ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; Align StackAlign = getStackAlign ( ) ; if ( RI -> hasStackRealignment ( MF ) ) { Align MaxStackAlign = std :: max ( StackAlign , MFI . getMaxAlign ( ) ) ; FrameSize += ( MaxStackAlign . value ( ) - StackAlign . value ( ) ) ; StackAlign = MaxStackAlign ; } uint64_t MaxCallSize = alignTo ( MFI . getMaxCallFrameSize ( ) , StackAlign ) ; MFI . setMaxCallFrameSize ( MaxCallSize ) ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI . setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s> SDValue AArch64TargetLowering :: BuildSDIVPow2 ( SDNode * N , const APInt & Divisor , SelectionDAG & DAG , std :: vector < SDNode * > * Created ) const { EVT VT = N -> getValueType ( 0 ) ; if ( ( VT != MVT :: i32 && VT != MVT :: i64 ) || ! ( Divisor . isPowerOf2 ( ) || ( - Divisor ) . isPowerOf2 ( ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( 0 ) ; unsigned Lg2 = Divisor . countTrailingZeros ( ) ; SDValue Zero = DAG . getConstant ( 0 , VT ) ; SDValue Pow2MinusOne = DAG . getConstant ( ( 1ULL << Lg2 ) - 1 , VT ) ; SDValue CCVal ; SDValue Cmp = getAArch64Cmp ( N0 , Zero , ISD :: SETLT , CCVal , DAG , DL ) ; SDValue Add = DAG . getNode ( ISD :: ADD , DL , VT , N0 , Pow2MinusOne ) ; SDValue CSel = DAG . getNode ( AArch64ISD :: CSEL , DL , VT , Add , N0 , CCVal , Cmp ) ; if ( Created ) { Created -> push_back ( Cmp . getNode ( ) ) ; Created -> push_back ( Add . getNode ( ) ) ; Created -> push_back ( CSel . getNode ( ) ) ; } SDValue SRA = DAG . getNode ( ISD :: SRA , DL , VT , CSel , DAG . getConstant ( Lg2 , MVT :: i64 ) ) ; if ( Divisor . isNonNegative ( ) ) return SRA ; if ( Created ) Created -> push_back ( SRA . getNode ( ) ) ; return DAG . getNode ( ISD :: SUB , DL , VT , DAG . getConstant ( 0 , VT ) , SRA ) ; } </s>

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators .


<s> void X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const X86InstrInfo & TII = * TM . getInstrInfo ( ) ; const X86RegisterInfo & RegInfo = * TM . getRegisterInfo ( ) ; unsigned StackPtr = RegInfo . getStackRegister ( ) ; bool reseveCallFrame = hasReservedCallFrame ( MF ) ; int Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; bool IsLP64 = STI . isTarget64BitLP64 ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reseveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t CalleeAmt = isDestroy ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reseveCallFrame ) { if ( Amount == 0 ) return ; unsigned StackAlign = TM . getFrameLowering ( ) -> getStackAlignment ( ) ; Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = 0 ; if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( IsLP64 , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; Amount -= CalleeAmt ; if ( Amount ) { unsigned Opc = getADDriOpcode ( IsLP64 , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } return ; } if ( Opcode == TII . getCallFrameDestroyOpcode ( ) && CalleeAmt ) { unsigned Opc = getSUBriOpcode ( IsLP64 , CalleeAmt ) ; MachineInstr * New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! llvm :: prior ( I ) -> isCall ( ) ) -- I ; MBB . insert ( I , New ) ; } } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static void nios2_asm_file_end ( void ) { if ( TARGET_LINUX_ABI && trampolines_created ) file_end_indicate_exec_stack ( ) ; } </s>


<s> virtual MVT getShiftAmountTy ( EVT LHSTy ) const { return MVT :: i8 ; } </s>

Returns the type for the shift amount of a shift opcode .


<s> static inline SPIRV :: SpecialTypeDescriptor getTombstoneKey ( ) { return SPIRV :: SpecialTypeDescriptor ( SPIRV :: SpecialTypeDescriptor :: STK_Last ) ; } </s>

Difference in tombstone is that the Optional is meaningful .

SPIRV SPIRV::SpecialTypeDescriptor SPIRV::SpecialTypeDescriptor SPIRV::SpecialTypeDescriptor


<s> void recordRelocation ( MachObjectWriter * Writer , MCAssembler & Asm , const MCAsmLayout & Layout , const MCFragment * Fragment , const MCFixup & Fixup , MCValue Target , uint64_t & FixedValue ) override { if ( Writer -> is64Bit ( ) ) RecordX86_64Relocation ( Writer , Asm , Layout , Fragment , Fixup , Target , FixedValue ) ; else RecordX86Relocation ( Writer , Asm , Layout , Fragment , Fixup , Target , FixedValue ) ; } </s>


"Extending floating point arguments not supported yet"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> unsigned AArch64InstrInfo :: getLoadStoreImmIdx ( unsigned Opc ) { switch ( Opc ) { default : return 2 ; case AArch64 :: LDPXi : case AArch64 :: LDPDi : case AArch64 :: STPXi : case AArch64 :: STPDi : case AArch64 :: LDNPXi : case AArch64 :: LDNPDi : case AArch64 :: STNPXi : case AArch64 :: STNPDi : case AArch64 :: LDPQi : case AArch64 :: STPQi : case AArch64 :: LDNPQi : case AArch64 :: STNPQi : case AArch64 :: LDPWi : case AArch64 :: LDPSi : case AArch64 :: STPWi : case AArch64 :: STPSi : case AArch64 :: LDNPWi : case AArch64 :: LDNPSi : case AArch64 :: STNPWi : case AArch64 :: STNPSi : case AArch64 :: LDG : return 3 ; case AArch64 :: ADDG : case AArch64 :: STGOffset : return 2 ; } } </s>

Returns the index for the immediate for a given instruction .


<s> OperandMatchResultTy M68kAsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { StartLoc = getLexer ( ) . getLoc ( ) ; auto Result = parseRegister ( RegNo ) ; EndLoc = getLexer ( ) . getLoc ( ) ; return Result ; } </s>

tryParseRegister - parse one register if possible


<s> static size_t find_field ( const std :: string & field , const std :: string & key ) { size_t key_pos , sep_pos ; key_pos = field . find ( key ) ; if ( key_pos == std :: string :: npos ) return std :: string :: npos ; sep_pos = field . find ( ":" , key_pos + 1 ) ; if ( sep_pos == std :: string :: npos ) return std :: string :: npos ; return sep_pos ; } </s>

Returns the index of the ' : ' inside the FIELD which must be found after the value of KEY . Returns string : :npos if line does not contain a field .


<s> bool shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const override { return true ; } </s>

Returns true if it is beneficial to convert a load of a constant to just the constant itself .


<s>
bool
X86AsmParser
::
ParseDirective
(
AsmToken
DirectiveID
)
{
StringRef
IDVal
=
DirectiveID
.
getIdentifier
(
)
;
if
(
IDVal
==
".word"
)
return
ParseDirectiveWord
(
2
,
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
.
startswith
(
".code"
)
)
return
ParseDirectiveCode
(
IDVal
,
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
.
startswith
(
".att_syntax"
)
)
{
getParser
(
)
.
setAssemblerDialect
(
0
)
;
return
false
;
}
else
if
(
IDVal
.
startswith
(
".intel_syntax"
)
)
{
getParser
(
)
.
setAssemblerDialect
(
1
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
Parser
.
Lex
(
)
;
}
return
false
;
}
else
if
(
IDVal
.
startswith
(
".dwarf_addr_size"
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
!=
"4"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
".dwarf_addr_size must be 4"
)
;
Parser
.
Lex
(
)
;
return
false
;
}
return
true
;
}
</s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool OR1KDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintCode ) { default : return true ; case 'm' : if ( ! SelectAddr ( Op , Op0 , Op1 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> static int s390_check_qrst_address ( char c , rtx op , bool lit_pool_ok ) { struct s390_address addr ; bool decomposed = false ; if ( s390_loadrelative_operand_p ( op , NULL , NULL ) ) return 0 ; if ( ! lit_pool_ok ) { if ( ! s390_decompose_address ( op , & addr ) ) return 0 ; if ( addr . literal_pool ) return 0 ; decomposed = true ; } if ( lra_in_progress ) { if ( ! decomposed && ! s390_decompose_address ( op , & addr ) ) return 0 ; decomposed = true ; } switch ( c ) { case 'Q' : if ( ! decomposed && ! s390_decompose_address ( op , & addr ) ) return 0 ; if ( addr . indx ) return 0 ; if ( ! s390_short_displacement ( addr . disp ) ) return 0 ; break ; case 'R' : if ( TARGET_LONG_DISPLACEMENT ) { if ( ! decomposed && ! s390_decompose_address ( op , & addr ) ) return 0 ; if ( ! s390_short_displacement ( addr . disp ) ) return 0 ; } break ; case 'S' : if ( ! decomposed && ! s390_decompose_address ( op , & addr ) ) return 0 ; if ( addr . indx ) return 0 ; break ; case 'T' : break ; default : return 0 ; } return 1 ; } </s>

Return true if the address in OP is valid for constraint letter C if wrapped in a MEM rtx . Set LIT_POOL_OK to true if it literal pool MEMs should be accepted . Only the Q , R , S , T constraint letters are allowed for C .


<s> void loongarch_set_return_address ( rtx address , rtx scratch ) { rtx slot_address ; gcc_assert ( BITSET_P ( cfun -> machine -> frame . mask , RETURN_ADDR_REGNUM ) ) ; if ( frame_pointer_needed ) slot_address = loongarch_add_offset ( scratch , hard_frame_pointer_rtx , - UNITS_PER_WORD ) ; else slot_address = loongarch_add_offset ( scratch , stack_pointer_rtx , cfun -> machine -> frame . gp_sp_offset ) ; loongarch_emit_move ( gen_frame_mem ( GET_MODE ( address ) , slot_address ) , address ) ; } </s>

Emit code to change the current function 's return address to ADDRESS . SCRATCH is available as a scratch register , if needed . ADDRESS and SCRATCH are both word-mode GPRs .


"MBlaze DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> static rtx gen_frame_mem_offset ( machine_mode mode , rtx reg , int offset ) { rtx int_rtx , offset_rtx ; int_rtx = GEN_INT ( offset ) ; if ( ( TARGET_SPE_ABI && SPE_VECTOR_MODE ( mode ) && ! SPE_CONST_OFFSET_OK ( offset ) ) || ( TARGET_E500_DOUBLE && mode == DFmode ) ) { offset_rtx = gen_rtx_REG ( Pmode , FIXED_SCRATCH ) ; emit_move_insn ( offset_rtx , int_rtx ) ; } else offset_rtx = int_rtx ; return gen_frame_mem ( mode , gen_rtx_PLUS ( Pmode , reg , offset_rtx ) ) ; } </s>

Emit an offset memory reference suitable for a frame store , while converting to a valid addressing mode .


<s> void PPCDispatchGroupSBHazardRecognizer :: EmitNoop ( ) { unsigned Directive = DAG -> MF . getSubtarget < PPCSubtarget > ( ) . getMcpu ( ) ; if ( Directive == PPC :: MCPU_PWR6 || Directive == PPC :: MCPU_PWR7 || Directive == PPC :: MCPU_PWR8 || Directive == PPC :: MCPU_PWR9 || CurSlots == 6 ) { CurGroup . clear ( ) ; CurSlots = CurBranches = 0 ; } else { CurGroup . push_back ( nullptr ) ; ++ CurSlots ; } } </s>

EmitNoop - This callback is invoked when a noop was added to the instruction stream .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
X86
::
NumTargetFixupKinds
]
=
{
{
"reloc_riprel_4byte"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_movq_load"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_relax"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_relax_rex"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_signed_4byte"
,
0
,
32
,
0
}
,
{
"reloc_signed_4byte_relax"
,
0
,
32
,
0
}
,
{
"reloc_global_offset_table"
,
0
,
32
,
0
}
,
{
"reloc_global_offset_table8"
,
0
,
64
,
0
}
,
{
"reloc_branch_4byte_pcrel"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
assert
(
Infos
[
Kind
FirstTargetFixupKind
]
.
Name
&&
"Empty fixup name!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> void emit_pic_move ( rtx * operands , machine_mode mode ATTRIBUTE_UNUSED ) { rtx temp = reload_in_progress ? operands [ 0 ] : gen_reg_rtx ( Pmode ) ; gcc_assert ( ! TARGET_FDPIC || ! ( reload_in_progress || reload_completed ) ) ; if ( GET_CODE ( operands [ 0 ] ) == MEM && SYMBOLIC_CONST ( operands [ 1 ] ) ) operands [ 1 ] = force_reg ( SImode , operands [ 1 ] ) ; else operands [ 1 ] = legitimize_pic_address ( operands [ 1 ] , temp , TARGET_FDPIC ? OUR_FDPIC_REG : pic_offset_table_rtx ) ; } </s>

Emit insns to move operands [ 1 ] into operands [ 0 ] .


<s> static void hwloop_fail ( hwloop_info loop ) { rtx insn = loop -> loop_end ; if ( DPREG_P ( loop -> iter_reg ) ) { rtx insn , test ; emit_insn_before ( gen_addsi3 ( loop -> iter_reg , loop -> iter_reg , constm1_rtx ) , loop -> loop_end ) ; test = gen_rtx_NE ( VOIDmode , loop -> iter_reg , const0_rtx ) ; insn = emit_jump_insn_before ( gen_cbranchsi4 ( test , loop -> iter_reg , const0_rtx , loop -> start_label ) , loop -> loop_end ) ; JUMP_LABEL ( insn ) = loop -> start_label ; LABEL_NUSES ( loop -> start_label ) ++ ; delete_insn ( loop -> loop_end ) ; } else { splitting_loops = 1 ; try_split ( PATTERN ( insn ) , safe_as_a < rtx_insn * > ( insn ) , 1 ) ; splitting_loops = 0 ; } } </s>

A callback for the hw-doloop pass . Called when a loop we have discovered turns out not to be optimizable ; we have to split the doloop_end pattern into a subtract and a test .


initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool s390_contiguous_bitmask_vector_p ( rtx op , int * start , int * end ) { unsigned HOST_WIDE_INT mask ; int size ; rtx elt ; bool b ; op = gen_lowpart ( related_int_vector_mode ( GET_MODE ( op ) ) . require ( ) , op ) ; gcc_assert ( ! ! start == ! ! end ) ; if ( ! const_vec_duplicate_p ( op , & elt ) || ! CONST_INT_P ( elt ) ) return false ; size = GET_MODE_UNIT_BITSIZE ( GET_MODE ( op ) ) ; if ( size > 64 ) return false ; mask = UINTVAL ( elt ) ; b = s390_contiguous_bitmask_p ( mask , true , size , start , end ) ; if ( b ) { if ( start ) { * start -= ( HOST_BITS_PER_WIDE_INT - size ) ; * end -= ( HOST_BITS_PER_WIDE_INT - size ) ; } return true ; } else return false ; } </s>

Return true if OP contains the same contiguous bitfield in * all * its elements . START and END can be used to obtain the start and end position of the bitfield . START/STOP give the position of the first/last bit of the bitfield counting from the lowest order bit starting with zero . In order to use these values for S/390 instructions this has to be converted to `` bits big endian '' style .


<s> bool HexagonSplitConst32AndConst64 :: runOnMachineFunction ( MachineFunction & Fn ) { const HexagonTargetObjectFile & TLOF = * static_cast < const HexagonTargetObjectFile * > ( Fn . getTarget ( ) . getObjFileLowering ( ) ) ; if ( TLOF . isSmallDataEnabled ( ) ) return true ; const TargetInstrInfo * TII = Fn . getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * TRI = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; for ( MachineBasicBlock & B : Fn ) { for ( auto I = B . begin ( ) , E = B . end ( ) ; I != E ; ) { MachineInstr & MI = * I ; ++ I ; unsigned Opc = MI . getOpcode ( ) ; if ( Opc == Hexagon :: CONST32 ) { unsigned DestReg = MI . getOperand ( 0 ) . getReg ( ) ; uint64_t ImmValue = MI . getOperand ( 1 ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( B , MI , DL , TII -> get ( Hexagon :: A2_tfrsi ) , DestReg ) . addImm ( ImmValue ) ; B . erase ( & MI ) ; } else if ( Opc == Hexagon :: CONST64 ) { unsigned DestReg = MI . getOperand ( 0 ) . getReg ( ) ; int64_t ImmValue = MI . getOperand ( 1 ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; unsigned DestLo = TRI -> getSubReg ( DestReg , Hexagon :: subreg_loreg ) ; unsigned DestHi = TRI -> getSubReg ( DestReg , Hexagon :: subreg_hireg ) ; int32_t LowWord = ( ImmValue & 0xFFFFFFFF ) ; int32_t HighWord = ( ImmValue >> 32 ) & 0xFFFFFFFF ; BuildMI ( B , MI , DL , TII -> get ( Hexagon :: A2_tfrsi ) , DestLo ) . addImm ( LowWord ) ; BuildMI ( B , MI , DL , TII -> get ( Hexagon :: A2_tfrsi ) , DestHi ) . addImm ( HighWord ) ; B . erase ( & MI ) ; } } } return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool ARMTargetLowering :: isShuffleMaskLegal ( ArrayRef < int > M , EVT VT ) const { if ( VT . getVectorNumElements ( ) == 4 && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ 4 ] ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { if ( M [ i ] < 0 ) PFIndexes [ i ] = 8 ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ 0 ] * 9 * 9 * 9 + PFIndexes [ 1 ] * 9 * 9 + PFIndexes [ 2 ] * 9 + PFIndexes [ 3 ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> 30 ) ; if ( Cost <= 4 && ( Subtarget -> hasNEON ( ) || isLegalMVEShuffleOp ( PFEntry ) ) ) return true ; } bool ReverseVEXT , isV_UNDEF ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; if ( EltSize >= 32 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || ShuffleVectorInst :: isIdentityMask ( M ) || isVREVMask ( M , VT , 64 ) || isVREVMask ( M , VT , 32 ) || isVREVMask ( M , VT , 16 ) ) return true ; else if ( Subtarget -> hasNEON ( ) && ( isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTBLMask ( M , VT ) || isNEONTwoResultShuffleMask ( M , VT , WhichResult , isV_UNDEF ) ) ) return true ; else if ( Subtarget -> hasNEON ( ) && ( VT == MVT :: v8i16 || VT == MVT :: v16i8 ) && isReverseMask ( M , VT ) ) return true ; else return false ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


"Pseudo flag setting opcodes only exist in Selection DAG"

"Non-flag-setting Thumb1 mov is v6-only"

"Unsupported register in Thumb1 push/pop"

"Incorrect array index for MVE_VMOV_q_rr"

Perform target-specific instruction verification .


<s> void x86_output_aligned_bss ( FILE * file , tree decl ATTRIBUTE_UNUSED , const char * name , unsigned HOST_WIDE_INT size , int align ) { if ( ( ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC ) && size > ( unsigned int ) ix86_section_threshold ) named_section ( decl , ".lbss" , 0 ) ; else bss_section ( ) ; ASM_OUTPUT_ALIGN ( file , floor_log2 ( align / BITS_PER_UNIT ) ) ; last_assemble_variable_decl = decl ; ASM_DECLARE_OBJECT_NAME ( file , name , decl ) ; ASM_OUTPUT_LABEL ( file , name ) ; ASM_OUTPUT_SKIP ( file , size ? size : 1 ) ; } </s>

Utility function for targets to use in implementing ASM_OUTPUT_ALIGNED_BSS .


<s> unsigned M680x0TargetLowering :: getJumpTableEncoding ( ) const { return Subtarget . getJumpTableEncoding ( ) ; } </s>

Return the entry encoding for a jump table in the current function .


<s>
bool
Mips16HardFloat
::
runOnModule
(
Module
&
M
)
{
auto
&
TM
=
static_cast
<
const
MipsTargetMachine
&
>
(
getAnalysis
<
TargetPassConfig
>
(
)
.
getTM
<
TargetMachine
>
(
)
)
;
DEBUG
(
errs
(
)
<<
"Run on Module Mips16HardFloat\n"
)
;
bool
Modified
=
false
;
for
(
Module
::
iterator
F
=
M
.
begin
(
)
,
E
=
M
.
end
(
)
;
F
!=
E
;
++
F
)
{
if
(
F
->
hasFnAttribute
(
"nomips16"
)
&&
F
->
hasFnAttribute
(
"use-soft-float"
)
)
{
removeUseSoftFloat
(
*
F
)
;
continue
;
}
if
(
F
->
isDeclaration
(
)
||
F
->
hasFnAttribute
(
"mips16_fp_stub"
)
||
F
->
hasFnAttribute
(
"nomips16"
)
)
continue
;
Modified
|=
fixupFPReturnAndCall
(
*
F
,
&
M
,
TM
)
;
FPParamVariant
V
=
whichFPParamVariantNeeded
(
*
F
)
;
if
(
V
!=
NoSig
)
{
Modified
=
true
;
createFPFnStub
(
&
*
F
,
&
M
,
V
,
TM
)
;
}
}
return
Modified
;
}
</s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
k_Register
:
OS
<<
"Reg<"
<<
Reg
.
Num
<<
">"
;
break
;
case
k_Immediate
:
OS
<<
"Imm<"
<<
Imm
.
Val
<<
">"
;
break
;
case
k_Token
:
OS
<<
Tok
.
Data
;
break
;
case
k_Memory
:
OS
<<
"Mem<Reg<"
<<
Mem
.
BaseNum
<<
">, "
<<
Mem
.
Off
<<
">"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> SDValue X86TargetLowering :: getRecipEstimate ( SDValue Op , SelectionDAG & DAG , int Enabled , int & RefinementSteps ) const { EVT VT = Op . getValueType ( ) ; if ( ( VT == MVT :: f32 && Subtarget . hasSSE1 ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasSSE1 ( ) ) || ( VT == MVT :: v8f32 && Subtarget . hasAVX ( ) ) ) { if ( VT == MVT :: f32 && Enabled == ReciprocalEstimate :: Unspecified ) return SDValue ( ) ; if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = 1 ; return DAG . getNode ( X86ISD :: FRCP , SDLoc ( Op ) , VT , Op ) ; } return SDValue ( ) ; } </s>

Return a reciprocal estimate value for the input operand .


<s> static const char * m68k_get_reloc_decoration ( enum m68k_reloc reloc ) { gcc_assert ( MOTOROLA || reloc == RELOC_GOT ) ; switch ( reloc ) { case RELOC_GOT : if ( MOTOROLA ) { if ( flag_pic == 1 && TARGET_68020 ) return "@GOT.w" ; else return "@GOT" ; } else { if ( TARGET_68020 ) { switch ( flag_pic ) { case 1 : return ":w" ; case 2 : return ":l" ; default : return "" ; } } } gcc_unreachable ( ) ; case RELOC_TLSGD : return "@TLSGD" ; case RELOC_TLSLDM : return "@TLSLDM" ; case RELOC_TLSLDO : return "@TLSLDO" ; case RELOC_TLSIE : return "@TLSIE" ; case RELOC_TLSLE : return "@TLSLE" ; default : gcc_unreachable ( ) ; } } </s>

Return string for TLS relocation RELOC .


<s> void ARMBaseRegisterInfo :: getRegAllocationHints ( unsigned VirtReg , ArrayRef < MCPhysReg > Order , SmallVectorImpl < MCPhysReg > & Hints , const MachineFunction & MF , const VirtRegMap * VRM ) const { const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; std :: pair < unsigned , unsigned > Hint = MRI . getRegAllocationHint ( VirtReg ) ; unsigned Odd ; switch ( Hint . first ) { case ARMRI :: RegPairEven : Odd = 0 ; break ; case ARMRI :: RegPairOdd : Odd = 1 ; break ; default : TargetRegisterInfo :: getRegAllocationHints ( VirtReg , Order , Hints , MF , VRM ) ; return ; } unsigned Paired = Hint . second ; if ( Paired == 0 ) return ; unsigned PairedPhys = 0 ; if ( TargetRegisterInfo :: isPhysicalRegister ( Paired ) ) { PairedPhys = Paired ; } else if ( VRM && VRM -> hasPhys ( Paired ) ) { PairedPhys = getPairedGPR ( VRM -> getPhys ( Paired ) , Odd , this ) ; } if ( PairedPhys && std :: find ( Order . begin ( ) , Order . end ( ) , PairedPhys ) != Order . end ( ) ) Hints . push_back ( PairedPhys ) ; for ( unsigned I = 0 , E = Order . size ( ) ; I != E ; ++ I ) { unsigned Reg = Order [ I ] ; if ( Reg == PairedPhys || ( getEncodingValue ( Reg ) & 1 ) != Odd ) continue ; unsigned Paired = getPairedGPR ( Reg , ! Odd , this ) ; if ( ! Paired || MRI . isReserved ( Paired ) ) continue ; Hints . push_back ( Reg ) ; } } </s>

Get a list of 'hint ' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg .


<s> int avr_ret_register ( void ) { return 24 ; } </s>

Returns register number for function return value .


<s> void rs6000_emit_swrsqrt ( rtx dst , rtx src ) { machine_mode mode = GET_MODE ( src ) ; rtx x0 = gen_reg_rtx ( mode ) ; rtx y = gen_reg_rtx ( mode ) ; int passes = ( TARGET_RECIP_PRECISION ) ? 1 : 3 ; if ( mode == DFmode || mode == V2DFmode ) passes ++ ; REAL_VALUE_TYPE dconst3_2 ; int i ; rtx halfthree ; enum insn_code code = optab_handler ( smul_optab , mode ) ; insn_gen_fn gen_mul = GEN_FCN ( code ) ; gcc_assert ( code != CODE_FOR_nothing ) ; real_from_integer ( & dconst3_2 , VOIDmode , 3 , SIGNED ) ; SET_REAL_EXP ( & dconst3_2 , REAL_EXP ( & dconst3_2 ) - 1 ) ; halfthree = rs6000_load_constant_and_splat ( mode , dconst3_2 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , src ) , UNSPEC_RSQRT ) ) ) ; rs6000_emit_msub ( y , src , halfthree , src ) ; for ( i = 0 ; i < passes ; i ++ ) { rtx x1 = gen_reg_rtx ( mode ) ; rtx u = gen_reg_rtx ( mode ) ; rtx v = gen_reg_rtx ( mode ) ; emit_insn ( gen_mul ( u , x0 , x0 ) ) ; rs6000_emit_nmsub ( v , y , u , halfthree ) ; emit_insn ( gen_mul ( x1 , x0 , v ) ) ; x0 = x1 ; } emit_move_insn ( dst , x0 ) ; return ; } </s>

Newton-Raphson approximation of single/double-precision floating point rsqrt . Assumes no trapping math and finite arguments .


<s> bool MLxExpansion :: runOnMachineFunction ( MachineFunction & Fn ) { if ( skipFunction ( Fn . getFunction ( ) ) ) return false ; TII = static_cast < const ARMBaseInstrInfo * > ( Fn . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; const ARMSubtarget * STI = & Fn . getSubtarget < ARMSubtarget > ( ) ; if ( ! STI -> expandMLx ( ) ) return false ; isLikeA9 = STI -> isLikeA9 ( ) || STI -> isSwift ( ) ; isSwift = STI -> isSwift ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : Fn ) Modified |= ExpandFPMLxInstructions ( MBB ) ; return Modified ; } </s>


<s> int HexagonMCInstrInfo :: getMinValue ( MCInstrInfo const & MCII , MCInst const & MCI ) { uint64_t const F = HexagonMCInstrInfo :: getDesc ( MCII , MCI ) . TSFlags ; unsigned isSigned = ( F >> HexagonII :: ExtentSignedPos ) & HexagonII :: ExtentSignedMask ; unsigned bits = ( F >> HexagonII :: ExtentBitsPos ) & HexagonII :: ExtentBitsMask ; if ( isSigned ) return - 1U << ( bits - 1 ) ; else return 0 ; } </s>

Return the minimal unsigned value possible given these KnownBits .

Hexagon Hexagon Hexagon HexagonII::ExtentSignedPos HexagonII::ExtentSignedMask HexagonII::ExtentBitsPos HexagonII::ExtentBitsMask 1U 1 0


<s> bool X86TargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { const IntrinsicData * IntrData = getIntrinsicWithChain ( Intrinsic ) ; if ( ! IntrData ) return false ; Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . flags = MachineMemOperand :: MONone ; Info . offset = 0 ; switch ( IntrData -> Type ) { case TRUNCATE_TO_MEM_VI8 : case TRUNCATE_TO_MEM_VI16 : case TRUNCATE_TO_MEM_VI32 : { Info . ptrVal = I . getArgOperand ( 0 ) ; MVT VT = MVT :: getVT ( I . getArgOperand ( 1 ) -> getType ( ) ) ; MVT ScalarVT = MVT :: INVALID_SIMPLE_VALUE_TYPE ; if ( IntrData -> Type == TRUNCATE_TO_MEM_VI8 ) ScalarVT = MVT :: i8 ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI16 ) ScalarVT = MVT :: i16 ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI32 ) ScalarVT = MVT :: i32 ; Info . memVT = MVT :: getVectorVT ( ScalarVT , VT . getVectorNumElements ( ) ) ; Info . align = 1 ; Info . flags |= MachineMemOperand :: MOStore ; break ; } case GATHER : case GATHER_AVX2 : { Info . ptrVal = nullptr ; MVT DataVT = MVT :: getVT ( I . getType ( ) ) ; MVT IndexVT = MVT :: getVT ( I . getArgOperand ( 2 ) -> getType ( ) ) ; unsigned NumElts = std :: min ( DataVT . getVectorNumElements ( ) , IndexVT . getVectorNumElements ( ) ) ; Info . memVT = MVT :: getVectorVT ( DataVT . getVectorElementType ( ) , NumElts ) ; Info . align = 1 ; Info . flags |= MachineMemOperand :: MOLoad ; break ; } case SCATTER : { Info . ptrVal = nullptr ; MVT DataVT = MVT :: getVT ( I . getArgOperand ( 3 ) -> getType ( ) ) ; MVT IndexVT = MVT :: getVT ( I . getArgOperand ( 2 ) -> getType ( ) ) ; unsigned NumElts = std :: min ( DataVT . getVectorNumElements ( ) , IndexVT . getVectorNumElements ( ) ) ; Info . memVT = MVT :: getVectorVT ( DataVT . getVectorElementType ( ) , NumElts ) ; Info . align = 1 ; Info . flags |= MachineMemOperand :: MOStore ; break ; } default : return false ; } return true ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = 0 ; i != 4 ; ++ i ) Data [ Offset + i ] |= uint8_t ( ( Value >> ( ( 4 - i - 1 ) * 8 ) ) & 0xff ) ; } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static bool ia64_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { return ( GET_MODE_CLASS ( mode1 ) == GET_MODE_CLASS ( mode2 ) && ( ( mode1 == XFmode || mode1 == XCmode || mode1 == RFmode ) == ( mode2 == XFmode || mode2 == XCmode || mode2 == RFmode ) ) && ( mode1 == BImode ) == ( mode2 == BImode ) ) ; } </s>

Implement TARGET_MODES_TIEABLE_P . Do n't tie integer and FP modes , as that causes us to get integer registers allocated for FP instructions . XFmode only supported in FP registers so we ca n't tie it with any other modes .


<s> Candidate ( MachineInstr * mi , unsigned reg , unsigned freebanks , unsigned weight ) : MI ( mi ) , Reg ( reg ) , FreeBanks ( freebanks ) , Weight ( weight ) { } </s>


<s> void AArch64AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( OutStreamer , MI ) ) return ; MCInst TmpInst ; LowerAArch64MachineInstrToMCInst ( MI , TmpInst , * this ) ; EmitToStreamer ( OutStreamer , TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
SDNode
*
FISCDAGToDAGISel
::
Select
(
SDNode
*
N
)
{
DEBUG
(
errs
(
)
<<
">>>>>> Selecting Node: "
;
N
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
switch
(
N
->
getOpcode
(
)
)
{
case
ISD
::
LOAD
:
return
SelectIndexedLoad
(
N
)
;
case
ISD
::
STORE
:
return
SelectIndexedStore
(
N
)
;
case
ISD
::
FrameIndex
:
return
SelectFrameIndex
(
N
)
;
case
ISD
::
Constant
:
return
ConstantToRegisterExpand
(
N
,
SDValue
(
N
,
0
)
)
.
getNode
(
)
;
case
ISD
::
ADD
:
if
(
N
->
getOperand
(
0
)
.
getOpcode
(
)
==
ISD
::
TargetGlobalAddress
)
return
SelectTargetGlobalAddressforADD
(
N
,
N
->
getOperand
(
0
)
.
getNode
(
)
)
;
break
;
case
FISCISD
::
CMP
:
return
SelectCompare
(
N
)
;
case
ISD
::
BR_CC
:
return
SelectConditionalBranch
(
N
)
;
case
ISD
::
CopyToReg
:
if
(
N
->
getOperand
(
2
)
.
getOpcode
(
)
==
ISD
::
TargetGlobalAddress
)
{
GlobalAddressSDNode
*
GA
=
dyn_cast
<
GlobalAddressSDNode
>
(
N
->
getOperand
(
2
)
)
;
const
GlobalValue
*
GV
=
GA
->
getGlobal
(
)
;
unsigned
char
TargetFlags
=
FISCII
::
MO_MOVRZ
;
if
(
GV
->
getValueID
(
)
==
Value
::
FunctionVal
)
TargetFlags
=
FISCII
::
MO_Q1
;
SDValue
TargetGlobalAddr
=
CurDAG
->
getTargetGlobalAddress
(
GV
,
SDLoc
(
N
)
,
MVT
::
i64
,
GA
->
getOffset
(
)
,
TargetFlags
)
;
MachineSDNode
*
Move
=
CurDAG
->
getMachineNode
(
FISC
::
MOVRZ
,
N
,
MVT
::
i64
,
TargetGlobalAddr
,
CurDAG
->
getTargetConstant
(
0
,
N
,
MVT
::
i64
)
)
;
CurDAG
->
ReplaceAllUsesWith
(
N
->
getOperand
(
2
)
,
SDValue
(
Move
,
0
)
)
;
}
break
;
case
FISCISD
::
CALL
:
{
unsigned
int
operand2Opc
=
N
->
getOperand
(
1
)
.
getOpcode
(
)
;
if
(
operand2Opc
==
ISD
::
LOAD
||
operand2Opc
==
ISD
::
CopyFromReg
)
{
return
SelectCallFunctionPointer
(
N
)
;
}
break
;
}
case
ISD
::
SRL
:
return
SelectShifts
(
N
)
;
case
ISD
::
MULHU
:
case
ISD
::
MULHS
:
return
SelectMUL
(
N
)
;
}
return
SelectCode
(
N
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> bool PIC16RegisterInfo :: hasFP ( const MachineFunction & MF ) const { return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> MachineInstr * SparcInstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , int FI ) const { if ( Ops . size ( ) != 1 ) return NULL ; unsigned OpNum = Ops [ 0 ] ; bool isFloat = false ; MachineInstr * NewMI = NULL ; switch ( MI -> getOpcode ( ) ) { case SP :: ORrr : if ( MI -> getOperand ( 1 ) . isReg ( ) && MI -> getOperand ( 1 ) . getReg ( ) == SP :: G0 && MI -> getOperand ( 0 ) . isReg ( ) && MI -> getOperand ( 2 ) . isReg ( ) ) { if ( OpNum == 0 ) NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( SP :: STri ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( MI -> getOperand ( 2 ) . getReg ( ) ) ; else NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( SP :: LDri ) , MI -> getOperand ( 0 ) . getReg ( ) ) . addFrameIndex ( FI ) . addImm ( 0 ) ; } break ; case SP :: FMOVS : isFloat = true ; case SP :: FMOVD : if ( OpNum == 0 ) { unsigned SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; bool isKill = MI -> getOperand ( 1 ) . isKill ( ) ; bool isUndef = MI -> getOperand ( 1 ) . isUndef ( ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isFloat ? SP :: STFri : SP :: STDFri ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , getKillRegState ( isKill ) | getUndefRegState ( isUndef ) ) ; } else { unsigned DstReg = MI -> getOperand ( 0 ) . getReg ( ) ; bool isDead = MI -> getOperand ( 0 ) . isDead ( ) ; bool isUndef = MI -> getOperand ( 0 ) . isUndef ( ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isFloat ? SP :: LDFri : SP :: LDDFri ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( isDead ) | getUndefRegState ( isUndef ) ) . addFrameIndex ( FI ) . addImm ( 0 ) ; } break ; } return NewMI ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> void SystemZFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; uint64_t MaxReach = ( MFFrame . estimateStackSize ( MF ) + SystemZMC :: CallFrameSize * 2 ) ; if ( ! isUInt < 12 > ( MaxReach ) ) { RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( 8 , 8 , false ) ) ; RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( 8 , 8 , false ) ) ; } } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


"getMemOperandWithOffset only supports base "

"operands of type register or frame index."

Return true if get the base operand , byte offset of an instruction and the memory width .


<s> static bool xtensa_function_ok_for_sibcall ( tree decl ATTRIBUTE_UNUSED , tree exp ATTRIBUTE_UNUSED ) { if ( TARGET_WINDOWED_ABI ) return false ; return true ; } </s>


<s>
static
void
initialize_aarch64_code_model
(
struct
gcc_options
*
opts
)
{
if
(
opts
->
x_flag_pic
)
{
switch
(
opts
->
x_aarch64_cmodel_var
)
{
case
AARCH64_CMODEL_TINY
:
aarch64_cmodel
=
AARCH64_CMODEL_TINY_PIC
;
break
;
case
AARCH64_CMODEL_SMALL
:
aarch64_cmodel
=
(
flag_pic
==
2
AARCH64_CMODEL_SMALL_PIC
:
AARCH64_CMODEL_SMALL_SPIC
)
;
aarch64_cmodel
=
AARCH64_CMODEL_SMALL_PIC
;
break
;
case
AARCH64_CMODEL_LARGE
:
sorry
(
"code model %qs with -f%s"
,
"large"
,
opts
->
x_flag_pic
>
1
"PIC"
:
"pic"
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
else
aarch64_cmodel
=
opts
->
x_aarch64_cmodel_var
;
}
</s>

A checking mechanism for the implementation of the various code models .


<s> static rtx nios2_legitimize_constant_address ( rtx addr ) { rtx base , offset ; split_const ( addr , & base , & offset ) ; if ( nios2_tls_symbol_p ( base ) ) base = nios2_legitimize_tls_address ( base ) ; else if ( flag_pic ) base = nios2_load_pic_address ( base , UNSPEC_PIC_SYM , NULL_RTX ) ; else return addr ; if ( offset != const0_rtx ) { gcc_assert ( can_create_pseudo_p ( ) ) ; return gen_rtx_PLUS ( Pmode , force_reg ( Pmode , base ) , ( CONST_INT_P ( offset ) ? ( SMALL_INT ( INTVAL ( offset ) ) ? offset : force_reg ( Pmode , offset ) ) : offset ) ) ; } return base ; } </s>

Legitimize addresses that are CONSTANT_P expressions .


<s> bool ix86_macro_fusion_p ( ) { return TARGET_FUSE_CMP_AND_BRANCH ; } </s>

Return true if target platform supports macro-fusion .


<s>
static
void
riscv_file_start
(
void
)
{
default_file_start
(
)
;
fprintf
(
asm_out_file
,
"\t.option %spic\n"
,
(
flag_pic
""
:
"no"
)
)
;
if
(
!
riscv_mrelax
)
fprintf
(
asm_out_file
,
"\t.option norelax\n"
)
;
if
(
riscv_emit_attribute_p
)
riscv_emit_attribute
(
)
;
}
</s>

riscv
"\t.option %spic\n"
""
"no"
"\t.option norelax\n"