<s>
bool
GBZ80FrameLowering
::
spillCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
if
(
CSI
.
empty
(
)
)
{
return
false
;
}
unsigned
CalleeFrameSize
=
0
;
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
GBZ80Subtarget
&
STI
=
MF
.
getSubtarget
<
GBZ80Subtarget
>
(
)
;
const
TargetInstrInfo
&
TII
=
*
STI
.
getInstrInfo
(
)
;
GBZ80MachineFunctionInfo
*
GBZ80FI
=
MF
.
getInfo
<
GBZ80MachineFunctionInfo
>
(
)
;
for
(
const
CalleeSavedInfo
&
CCSI
:
reverse
(
CSI
)
)
{
unsigned
Reg
=
CCSI
.
getReg
(
)
;
bool
IsNotLiveIn
=
!
MBB
.
isLiveIn
(
Reg
)
;
assert
(
TRI
->
getRegSizeInBits
(
*
TRI
->
getMinimalPhysRegClass
(
Reg
)
)
==
16
&&
"Invalid register size"
)
;
if
(
IsNotLiveIn
)
{
MBB
.
addLiveIn
(
Reg
)
;
}
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
GB
::
PUSH
)
)
.
addReg
(
Reg
,
getKillRegState
(
IsNotLiveIn
)
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
CalleeFrameSize
+=
2
;
}
GBZ80FI
->
setCalleeSavedFrameSize
(
CalleeFrameSize
)
;
return
true
;
}
</s>

GBZ80
GB
0
GB
GB
GB
GB
GB
16
"Invalid register size"
GB::PUSH
2
GB


<s> static int aarch64_sched_adjust_priority ( rtx_insn * insn , int priority ) { rtx x = PATTERN ( insn ) ; if ( GET_CODE ( x ) == SET ) { x = SET_SRC ( x ) ; if ( GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNSPEC_SHA1H ) return priority + 10 ; } return priority ; } </s>

Implement the TARGET_SCHED_ADJUST_PRIORITY hook . Adjust priority of sha1h instructions so they are scheduled before other SHA1 instructions .


<s> unsigned size ( ) const { return Mask . size ( ) ; } </s>

The number of name/type pairs is returned .


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( CommentStream ) HasCustomInstComment = EmitAnyX86InstComments ( MI , * CommentStream , MII ) ; unsigned Flags = MI -> getFlags ( ) ; if ( ( TSFlags & X86II :: LOCK ) || ( Flags & X86 :: IP_HAS_LOCK ) ) OS << "\tlock\t" ; if ( ( TSFlags & X86II :: NOTRACK ) || ( Flags & X86 :: IP_HAS_NOTRACK ) ) OS << "\tnotrack\t" ; if ( Flags & X86 :: IP_HAS_REPEAT_NE ) OS << "\trepne\t" ; else if ( Flags & X86 :: IP_HAS_REPEAT ) OS << "\trep\t" ; if ( MI -> getOpcode ( ) == X86 :: CALLpcrel32 && ( STI . getFeatureBits ( ) [ X86 :: Mode64Bit ] ) ) { OS << "\tcallq\t" ; printPCRelImm ( MI , 0 , OS ) ; } else if ( MI -> getOpcode ( ) == X86 :: DATA16_PREFIX && ( STI . getFeatureBits ( ) [ X86 :: Mode16Bit ] ) ) { MCInst Data32MI ( * MI ) ; Data32MI . setOpcode ( X86 :: DATA32_PREFIX ) ; printInstruction ( & Data32MI , OS ) ; } else if ( ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> int insvdi_rshift_rlwimi_p ( rtx sizeop , rtx startop , rtx shiftop ) { if ( INTVAL ( startop ) > 32 && INTVAL ( startop ) < 64 && INTVAL ( sizeop ) > 1 && INTVAL ( sizeop ) + INTVAL ( startop ) < 64 && INTVAL ( shiftop ) > 0 && INTVAL ( sizeop ) + INTVAL ( shiftop ) < 32 && ( 64 - ( INTVAL ( shiftop ) & 63 ) ) >= INTVAL ( sizeop ) ) return 1 ; return 0 ; } </s>

Return 1 if operands will generate a valid arguments to rlwimiinstruction for insert with right shift in 64-bit mode . The mask maynot start on the first bit or stop on the last bit because wrap-aroundeffects of instruction do not correspond to semantics of RTL insn .


<s> static rtx tilegx_legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , machine_mode mode ) { if ( GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD && symbolic_operand ( x , Pmode ) && tilegx_tls_referenced_p ( x ) ) { return tilegx_legitimize_tls_address ( x ) ; } else if ( flag_pic ) { return tilegx_legitimize_pic_address ( x , mode , 0 ) ; } else return x ; } </s>


<s> void HexagonMCELFStreamer :: EmitInstruction ( const MCInst & MCK , const MCSubtargetInfo & STI ) { MCInst HMI ; HMI . setOpcode ( Hexagon :: BUNDLE ) ; HMI . addOperand ( MCOperand :: createImm ( 0 ) ) ; MCInst * MCB ; if ( MCK . getOpcode ( ) != Hexagon :: BUNDLE ) { HMI . addOperand ( MCOperand :: createInst ( & MCK ) ) ; MCB = & HMI ; } else MCB = const_cast < MCInst * > ( & MCK ) ; HexagonMCInstrInfo :: padEndloop ( * MCB ) ; HexagonMCShuffle ( * MCII , STI , * MCB ) ; assert ( HexagonMCInstrInfo :: bundleSize ( * MCB ) <= HEXAGON_PACKET_SIZE ) ; bool Extended = false ; for ( auto & I : HexagonMCInstrInfo :: bundleInstructions ( * MCB ) ) { MCInst * MCI = const_cast < MCInst * > ( I . getInst ( ) ) ; if ( Extended ) { if ( HexagonMCInstrInfo :: isDuplex ( * MCII , * MCI ) ) { MCInst * SubInst = const_cast < MCInst * > ( MCI -> getOperand ( 1 ) . getInst ( ) ) ; HexagonMCInstrInfo :: clampExtended ( * MCII , * SubInst ) ; } else { HexagonMCInstrInfo :: clampExtended ( * MCII , * MCI ) ; } Extended = false ; } else { Extended = HexagonMCInstrInfo :: isImmext ( * MCI ) ; } } for ( auto const & I : HexagonMCInstrInfo :: bundleInstructions ( * MCB ) ) { MCInst * MCI = const_cast < MCInst * > ( I . getInst ( ) ) ; EmitSymbol ( * MCI ) ; } MCObjectStreamer :: EmitInstruction ( * MCB , STI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .

Hexagon Hexagon Hexagon::BUNDLE 0 Hexagon::BUNDLE Hexagon Hexagon Hexagon Hexagon Hexagon 1 Hexagon Hexagon Hexagon Hexagon


<s> SDValue X86TargetLowering :: getSqrtEstimate ( SDValue Op , SelectionDAG & DAG , int Enabled , int & RefinementSteps , bool & UseOneConstNR , bool Reciprocal ) const { EVT VT = Op . getValueType ( ) ; if ( ( VT == MVT :: f32 && Subtarget . hasSSE1 ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasSSE1 ( ) && Reciprocal ) || ( VT == MVT :: v4f32 && Subtarget . hasSSE2 ( ) && ! Reciprocal ) || ( VT == MVT :: v8f32 && Subtarget . hasAVX ( ) ) ) { if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = 1 ; UseOneConstNR = false ; return DAG . getNode ( X86ISD :: FRSQRT , SDLoc ( Op ) , VT , Op ) ; } return SDValue ( ) ; } </s>

Hooks for building estimates in place of slower divisions and square roots .


<s> void reset ( ) { count = 0 ; size = 0 ; call = false ; } </s>

Reset an existing scalar value for Def and a given Instance .


" was Pass-through, is now Dirty-out.\n"

runOnMachineFunction - Emit the function body .


<s> void HSAILPassConfig :: addPreEmitPass ( ) { } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static int save_fprs_p ( ) { int i ; if ( ! TARGET_64BIT ) return 0 ; for ( i = 24 ; i <= 31 ; i ++ ) { if ( regs_ever_live [ i ] == 1 ) return 1 ; } return 0 ; } </s>

Return true if floating point registers need to be saved .


<s> TargetPassConfig * SystemZTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new SystemZPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> static enum unwind_info_type ia64_debug_unwind_info ( void ) { return UI_TARGET ; } </s>


<s> void arc_expand_prologue ( void ) { int size ; unsigned int gmask = cfun -> machine -> frame_info . gmask ; struct arc_frame_info * frame = & cfun -> machine -> frame_info ; unsigned int frame_size_to_allocate ; int first_offset = 0 ; unsigned int fn_type = arc_compute_function_type ( cfun ) ; bool save_blink = false ; bool save_fp = false ; if ( ARC_NAKED_P ( fn_type ) ) { if ( flag_stack_usage_info ) current_function_static_stack_size = 0 ; return ; } size = arc_compute_frame_size ( ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = size ; frame_size_to_allocate = size ; gcc_assert ( ! ( size == 0 && gmask ) ) ; if ( frame -> pretend_size != 0 ) first_offset = - frame -> pretend_size ; if ( ARC_AUTO_IRQ_P ( fn_type ) && ! ARC_FAST_INTERRUPT_P ( fn_type ) ) { frame_stack_add ( first_offset ) ; first_offset = 0 ; arc_dwarf_emit_irq_save_regs ( ) ; } save_blink = arc_must_save_return_addr ( cfun ) && ! ARC_AUTOBLINK_IRQ_P ( fn_type ) ; save_fp = arc_frame_pointer_needed ( ) && ! ARC_AUTOFP_IRQ_P ( fn_type ) ; if ( TARGET_CODE_DENSITY && TARGET_CODE_DENSITY_FRAME && ! ARC_AUTOFP_IRQ_P ( fn_type ) && ! ARC_AUTOBLINK_IRQ_P ( fn_type ) && ! ARC_INTERRUPT_P ( fn_type ) && arc_enter_leave_p ( gmask ) ) frame_size_to_allocate -= arc_save_callee_enter ( gmask , save_blink , save_fp , first_offset ) ; else if ( frame -> millicode_end_reg > 14 ) frame_size_to_allocate -= arc_save_callee_milli ( gmask , save_blink , save_fp , first_offset , frame -> reg_size ) ; else frame_size_to_allocate -= arc_save_callee_saves ( gmask , save_blink , save_fp , first_offset ) ; if ( frame_size_to_allocate > 0 ) frame_stack_add ( ( HOST_WIDE_INT ) 0 - frame_size_to_allocate ) ; emit_insn ( gen_blockage ( ) ) ; } </s>

Set up the stack and frame pointer ( if desired ) for the function .


<s> SDValue XCoreTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_XCore ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> bool targetHandlesStackFrameRounding ( ) const override { return true ; } </s>

targetHandlesStackFrameRounding - Returns true if the target is responsible for rounding up the stack frame ( probably at emitPrologue time ) .


<s>
void
BT
::
run
(
)
{
reset
(
)
;
assert
(
FlowQ
.
empty
(
)
)
;
using
MachineFlowGraphTraits
=
GraphTraits
<
const
MachineFunction
*
>
;
const
MachineBasicBlock
*
Entry
=
MachineFlowGraphTraits
::
getEntryNode
(
&
MF
)
;
unsigned
MaxBN
=
0
;
for
(
const
MachineBasicBlock
&
B
:
MF
)
{
assert
(
B
.
getNumber
(
)
>=
0
&&
"Disconnected block"
)
;
unsigned
BN
=
B
.
getNumber
(
)
;
if
(
BN
>
MaxBN
)
MaxBN
=
BN
;
}
BitVector
BlockScanned
(
MaxBN
+
1
)
;
int
EntryN
=
Entry
->
getNumber
(
)
;
FlowQ
.
push
(
CFGEdge
(
1
,
EntryN
)
)
;
while
(
!
FlowQ
.
empty
(
)
||
!
UseQ
.
empty
(
)
)
{
runEdgeQueue
(
BlockScanned
)
;
runUseQueue
(
)
;
}
UseQ
.
reset
(
)
;
if
(
Trace
)
print_cells
(
dbgs
(
)
<<
"Cells after propagation:\n"
)
;
}
</s>

Run the analysis pass over a function and produce a dominator tree .


<s> static void sparc_handle_vis_mul8x16 ( vec < tree > * n_elts , enum sparc_builtins fncode , tree inner_type , tree cst0 , tree cst1 ) { unsigned i , num = VECTOR_CST_NELTS ( cst0 ) ; int scale ; switch ( fncode ) { case SPARC_BUILTIN_FMUL8X16 : for ( i = 0 ; i < num ; ++ i ) { int val = sparc_vis_mul8x16 ( TREE_INT_CST_LOW ( VECTOR_CST_ELT ( cst0 , i ) ) , TREE_INT_CST_LOW ( VECTOR_CST_ELT ( cst1 , i ) ) ) ; n_elts -> quick_push ( build_int_cst ( inner_type , val ) ) ; } break ; case SPARC_BUILTIN_FMUL8X16AU : scale = TREE_INT_CST_LOW ( VECTOR_CST_ELT ( cst1 , 0 ) ) ; for ( i = 0 ; i < num ; ++ i ) { int val = sparc_vis_mul8x16 ( TREE_INT_CST_LOW ( VECTOR_CST_ELT ( cst0 , i ) ) , scale ) ; n_elts -> quick_push ( build_int_cst ( inner_type , val ) ) ; } break ; case SPARC_BUILTIN_FMUL8X16AL : scale = TREE_INT_CST_LOW ( VECTOR_CST_ELT ( cst1 , 1 ) ) ; for ( i = 0 ; i < num ; ++ i ) { int val = sparc_vis_mul8x16 ( TREE_INT_CST_LOW ( VECTOR_CST_ELT ( cst0 , i ) ) , scale ) ; n_elts -> quick_push ( build_int_cst ( inner_type , val ) ) ; } break ; default : gcc_unreachable ( ) ; } } </s>

Multiply the vector elements in ELTS0 to the elements in ELTS1 as specified by FNCODE . All of the elements in ELTS0 and ELTS1 lists must be integer constants . A tree list with the results of the multiplications is returned , and each element in the list is of INNER_TYPE .


<s>
bool
LanaiInstrInfo
::
areMemAccessesTriviallyDisjoint
(
MachineInstr
&
MIa
,
MachineInstr
&
MIb
,
AliasAnalysis
*
)
const
{
assert
(
MIa
.
mayLoadOrStore
(
)
&&
"MIa must be a load or store."
)
;
assert
(
MIb
.
mayLoadOrStore
(
)
&&
"MIb must be a load or store."
)
;
if
(
MIa
.
hasUnmodeledSideEffects
(
)
||
MIb
.
hasUnmodeledSideEffects
(
)
||
MIa
.
hasOrderedMemoryRef
(
)
||
MIb
.
hasOrderedMemoryRef
(
)
)
return
false
;
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
MachineOperand
*
BaseOpA
=
nullptr
,
*
BaseOpB
=
nullptr
;
int64_t
OffsetA
=
0
,
OffsetB
=
0
;
unsigned
int
WidthA
=
0
,
WidthB
=
0
;
if
(
getMemOperandWithOffsetWidth
(
MIa
,
BaseOpA
,
OffsetA
,
WidthA
,
TRI
)
&&
getMemOperandWithOffsetWidth
(
MIb
,
BaseOpB
,
OffsetB
,
WidthB
,
TRI
)
)
{
if
(
BaseOpA
->
isIdenticalTo
(
*
BaseOpB
)
)
{
int
LowOffset
=
std
::
min
(
OffsetA
,
OffsetB
)
;
int
HighOffset
=
std
::
max
(
OffsetA
,
OffsetB
)
;
int
LowWidth
=
(
LowOffset
==
OffsetA
)
WidthA
:
WidthB
;
if
(
LowOffset
+
LowWidth
<=
HighOffset
)
return
true
;
}
}
return
false
;
}
</s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> MVT :: SimpleValueType PPCTargetLowering :: getSetCCResultType ( EVT VT ) const { return MVT :: i32 ; } </s>

Return the value type to use for ISD : :SETCC .

PowerPC MVT::SimpleValueType PPC MVT::i32


<s> void ix86_expand_convert_uns_sixf_sse ( rtx , rtx ) { gcc_unreachable ( ) ; } </s>

Not used , but eases macroization of patterns .


"cannot set interrupt attribute: no current function"

"cannot set interrupt attribute: no such identifier"

Set the machine specific 'interrupt ' attribute on the current function .


<s> static bool vspltis_constant ( rtx op , unsigned step , unsigned copies ) { machine_mode mode = GET_MODE ( op ) ; machine_mode inner = GET_MODE_INNER ( mode ) ; unsigned i ; unsigned nunits ; unsigned bitsize ; unsigned mask ; HOST_WIDE_INT val ; HOST_WIDE_INT splat_val ; HOST_WIDE_INT msb_val ; if ( mode == V2DImode || mode == V2DFmode || mode == V1TImode ) return false ; nunits = GET_MODE_NUNITS ( mode ) ; bitsize = GET_MODE_BITSIZE ( inner ) ; mask = GET_MODE_MASK ( inner ) ; val = const_vector_elt_as_int ( op , BYTES_BIG_ENDIAN ? nunits - 1 : 0 ) ; splat_val = val ; msb_val = val >= 0 ? 0 : - 1 ; for ( i = 2 ; i <= copies ; i *= 2 ) { HOST_WIDE_INT small_val ; bitsize /= 2 ; small_val = splat_val >> bitsize ; mask >>= bitsize ; if ( splat_val != ( ( small_val << bitsize ) | ( small_val & mask ) ) ) return false ; splat_val = small_val ; } if ( EASY_VECTOR_15 ( splat_val ) ) ; else if ( EASY_VECTOR_15_ADD_SELF ( splat_val ) && ( splat_val >= 0 || ( step == 1 && copies == 1 ) ) ) ; else if ( EASY_VECTOR_MSB ( splat_val , inner ) ) ; else return false ; for ( i = 1 ; i < nunits ; ++ i ) { HOST_WIDE_INT desired_val ; unsigned elt = BYTES_BIG_ENDIAN ? nunits - 1 - i : i ; if ( ( i & ( step - 1 ) ) == 0 ) desired_val = val ; else desired_val = msb_val ; if ( desired_val != const_vector_elt_as_int ( op , elt ) ) return false ; } return true ; } </s>

Return true if OP can be synthesized with a particular vspltisb , vspltish or vspltisw instruction . OP is a CONST_VECTOR . Which instruction is used depends on STEP and COPIES , one of which will be 1 . If COPIES > 1 , all items are set to the same value and contain COPIES replicas of the vsplt 's operand ; if STEP > 1 , one in STEP elements is set to the vsplt 's operand and the others are set to the value of the operand 's msb .


"********** MI Converging Scheduling VLIW BB#"

Schedule - This is called back from ScheduleDAGInstrs : :Run ( ) when it 's time to do some work .


<s> bool AMDGPUTargetELFStreamer :: EmitHSAMetadata ( const AMDGPU :: HSAMD :: Metadata & HSAMetadata ) { std :: string HSAMetadataString ; if ( HSAMD :: toString ( HSAMetadata , HSAMetadataString ) ) return false ; auto & Context = getContext ( ) ; auto * DescBegin = Context . createTempSymbol ( ) ; auto * DescEnd = Context . createTempSymbol ( ) ; auto * DescSZ = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( DescEnd , Context ) , MCSymbolRefExpr :: create ( DescBegin , Context ) , Context ) ; EmitNote ( ElfNote :: NoteNameV2 , DescSZ , ELF :: NT_AMD_HSA_METADATA , [ & ] ( MCELFStreamer & OS ) { OS . emitLabel ( DescBegin ) ; OS . emitBytes ( HSAMetadataString ) ; OS . emitLabel ( DescEnd ) ; } ) ; return true ; } </s>


<s> bool X86RegisterInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; return ( DisableFramePointerElim ( MF ) || needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool MBlazePassConfig :: addInstSelector ( ) { PM -> add ( createMBlazeISelDag ( getMBlazeTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static rtx or1k_legitimize_address ( rtx x , rtx , machine_mode ) { return or1k_legitimize_address_1 ( x , NULL_RTX ) ; } </s>

Worker for TARGET_LEGITIMIZE_ADDRESS . This delegates implementation to or1k_legitimize_address_1 .


<s> unsigned int mips_case_values_threshold ( void ) { if ( TARGET_MIPS16 && optimize_size ) return 10 ; else return default_case_values_threshold ( ) ; } </s>


<s> bool ix86_call_use_plt_p ( rtx call_op ) { if ( SYMBOL_REF_LOCAL_P ( call_op ) ) { if ( SYMBOL_REF_DECL ( call_op ) && TREE_CODE ( SYMBOL_REF_DECL ( call_op ) ) == FUNCTION_DECL ) { cgraph_node * node = cgraph_node :: get ( SYMBOL_REF_DECL ( call_op ) ) ; if ( node && node -> ifunc_resolver ) return true ; } return false ; } return true ; } </s>

Return true if the function is called via PLT .


<s> static void h8300_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; cum -> nbytes += ( mode != BLKmode ? ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) & - UNITS_PER_WORD : ( int_size_in_bytes ( type ) + UNITS_PER_WORD - 1 ) & - UNITS_PER_WORD ) ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s>
bool
ARMAsmPrinter
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
{
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
&&
MO
.
getReg
(
)
!=
ARM
::
CPSR
)
return
false
;
assert
(
!
MO
.
getSubReg
(
)
&&
"Subregs should be eliminated!"
)
;
MCOp
=
MCOperand
::
createReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
createImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
createExpr
(
MCSymbolRefExpr
::
create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
OutContext
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
{
MCOp
=
GetSymbolRef
(
MO
,
GetARMGVSymbol
(
MO
.
getGlobal
(
)
,
MO
.
getTargetFlags
(
)
)
)
;
break
;
}
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
GetSymbolRef
(
MO
,
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
MCOp
=
GetSymbolRef
(
MO
,
GetJTISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
MCOp
=
GetSymbolRef
(
MO
,
GetCPISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_BlockAddress
:
MCOp
=
GetSymbolRef
(
MO
,
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
)
;
break
;
case
MachineOperand
::
MO_FPImmediate
:
{
APFloat
Val
=
MO
.
getFPImm
(
)
->
getValueAPF
(
)
;
bool
ignored
;
Val
.
convert
(
APFloat
::
IEEEdouble
,
APFloat
::
rmTowardZero
,
&
ignored
)
;
MCOp
=
MCOperand
::
createFPImm
(
Val
.
convertToDouble
(
)
)
;
break
;
}
case
MachineOperand
::
MO_RegisterMask
:
return
false
;
}
return
true
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .

ARM
ARM
"unknown operand type"
ARM::CPSR
"Subregs should be eliminated!"
ARM


<s> void CSKYELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; LSDAEncoding = dwarf :: DW_EH_PE_pcrel | dwarf :: DW_EH_PE_sdata4 ; PersonalityEncoding = dwarf :: DW_EH_PE_indirect | dwarf :: DW_EH_PE_pcrel | dwarf :: DW_EH_PE_sdata4 ; TTypeEncoding = dwarf :: DW_EH_PE_indirect | dwarf :: DW_EH_PE_pcrel | dwarf :: DW_EH_PE_sdata4 ; } </s>

This method must be called before any actual lowering is done .


<s> static void h8300_trampoline_init ( rtx m_tramp , tree fndecl , rtx cxt ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx mem ; if ( Pmode == HImode ) { mem = adjust_address ( m_tramp , HImode , 0 ) ; emit_move_insn ( mem , GEN_INT ( 0x7903 ) ) ; mem = adjust_address ( m_tramp , Pmode , 2 ) ; emit_move_insn ( mem , cxt ) ; mem = adjust_address ( m_tramp , HImode , 4 ) ; emit_move_insn ( mem , GEN_INT ( 0x5a00 ) ) ; mem = adjust_address ( m_tramp , Pmode , 6 ) ; emit_move_insn ( mem , fnaddr ) ; } else { rtx tem ; mem = adjust_address ( m_tramp , HImode , 0 ) ; emit_move_insn ( mem , GEN_INT ( 0x7a03 ) ) ; mem = adjust_address ( m_tramp , Pmode , 2 ) ; emit_move_insn ( mem , cxt ) ; tem = copy_to_reg ( fnaddr ) ; emit_insn ( gen_andsi3 ( tem , tem , GEN_INT ( 0x00ffffff ) ) ) ; emit_insn ( gen_iorsi3 ( tem , tem , GEN_INT ( 0x5a000000 ) ) ) ; mem = adjust_address ( m_tramp , SImode , 6 ) ; emit_move_insn ( mem , tem ) ; } } </s>


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
Register
:
OS
<<
"<register x"
;
OS
<<
getReg
(
)
<<
">"
;
break
;
case
Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s>
static
void
macho_branch_islands
(
void
)
{
char
tmp_buf
[
512
]
;
tree
branch_island
;
for
(
branch_island
=
branch_island_list
;
branch_island
;
branch_island
=
TREE_CHAIN
(
branch_island
)
)
{
const
char
*
label
=
IDENTIFIER_POINTER
(
BRANCH_ISLAND_LABEL_NAME
(
branch_island
)
)
;
const
char
*
name
=
IDENTIFIER_POINTER
(
BRANCH_ISLAND_FUNCTION_NAME
(
branch_island
)
)
;
char
name_buf
[
512
]
;
if
(
name
[
0
]
==
'*'
||
name
[
0
]
==
'&'
)
strcpy
(
name_buf
,
name
+
1
)
;
else
{
name_buf
[
0
]
=
'_'
;
strcpy
(
name_buf
+
1
,
name
)
;
}
strcpy
(
tmp_buf
,
"\n"
)
;
strcat
(
tmp_buf
,
label
)
;
if
(
write_symbols
==
DBX_DEBUG
||
write_symbols
==
XCOFF_DEBUG
)
dbxout_stabd
(
N_SLINE
,
BRANCH_ISLAND_LINE_NUMBER
(
branch_island
)
)
;
if
(
flag_pic
)
{
strcat
(
tmp_buf
,
":\n\tmflr r0\n\tbcl 20,31,"
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic\n"
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic:\n\tmflr r11\n"
)
;
strcat
(
tmp_buf
,
"\taddis r11,r11,ha16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
" - "
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic)\n"
)
;
strcat
(
tmp_buf
,
"\tmtlr r0\n"
)
;
strcat
(
tmp_buf
,
"\taddi r12,r11,lo16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
" - "
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic)\n"
)
;
strcat
(
tmp_buf
,
"\tmtctr r12\n\tbctr\n"
)
;
}
else
{
strcat
(
tmp_buf
,
":\nlis r12,hi16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
")\n\tori r12,r12,lo16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
")\n\tmtctr r12\n\tbctr"
)
;
}
output_asm_insn
(
tmp_buf
,
0
)
;
if
(
write_symbols
==
DBX_DEBUG
||
write_symbols
==
XCOFF_DEBUG
)
dbxout_stabd
(
N_SLINE
,
BRANCH_ISLAND_LINE_NUMBER
(
branch_island
)
)
;
}
branch_island_list
=
0
;
}
</s>

Generate far-jump branch islands for everything on the branch_island_list . Invoked immediately after the last instruction of the epilogue has been emitted ; the branch-islands must be appended to , and contiguous with , the function body . Mach-O stubs are generated in machopic_output_stub ( ) .


<s> MVT PPCTargetLowering :: getSetCCResultType ( MVT VT ) const { return MVT :: i32 ; } </s>


<s> BitVector SICRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t ReservedCPURegs [ ] = { SIC :: X , SIC :: PC } ; BitVector Reserved ( getNumRegs ( ) ) ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
unsigned
SICABIInfo
::
GetCalleeAllocdArgSizeInBytes
(
CallingConv
::
ID
CC
)
const
{
if
(
IsO32
(
)
)
return
CC
!=
0
;
if
(
IsS32
(
)
)
return
0
;
llvm_unreachable
(
"Unhandled ABI"
)
;
}
</s>

Obtain the size of the area allocated by the callee for arguments .


<s> rtx alpha_arg_info_reg_val ( CUMULATIVE_ARGS cum ) { unsigned HOST_WIDE_INT regval = cum . num_args ; int i ; for ( i = 0 ; i < 6 ; i ++ ) regval |= ( ( int ) cum . atypes [ i ] ) << ( i * 3 + 8 ) ; return GEN_INT ( regval ) ; } </s>

Return an rtx for an integer representing the VMS Argument Information register value .


<s> static int vfp3_const_double_index ( rtx x ) { REAL_VALUE_TYPE r , m ; int sign , exponent ; unsigned HOST_WIDE_INT mantissa , mant_hi ; unsigned HOST_WIDE_INT mask ; int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1 ; bool fail ; if ( ! TARGET_VFP3 || ! CONST_DOUBLE_P ( x ) ) return - 1 ; REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; if ( REAL_VALUE_ISINF ( r ) || REAL_VALUE_ISNAN ( r ) || REAL_VALUE_MINUS_ZERO ( r ) ) return - 1 ; sign = REAL_VALUE_NEGATIVE ( r ) ? 1 : 0 ; r = real_value_abs ( & r ) ; exponent = REAL_EXP ( & r ) ; real_ldexp ( & m , & r , point_pos - exponent ) ; wide_int w = real_to_integer ( & m , & fail , HOST_BITS_PER_WIDE_INT * 2 ) ; mantissa = w . elt ( 0 ) ; mant_hi = w . elt ( 1 ) ; if ( mantissa != 0 ) return - 1 ; point_pos -= HOST_BITS_PER_WIDE_INT ; mantissa = mant_hi ; mask = ( ( unsigned HOST_WIDE_INT ) 1 << ( point_pos - 5 ) ) - 1 ; if ( ( mantissa & mask ) != 0 ) return - 1 ; mantissa >>= point_pos - 5 ; if ( mantissa == 0 ) return - 1 ; gcc_assert ( mantissa >= 16 && mantissa <= 31 ) ; exponent = 5 - exponent ; if ( exponent < 0 || exponent > 7 ) return - 1 ; return ( sign << 7 ) | ( ( exponent ^ 3 ) << 4 ) | ( mantissa - 16 ) ; } </s>

Return an integer index for a VFPv3 immediate operand X suitable for the fconst [ sd ] instruction , or -1 if X is n't suitable .


<s> static rtx nios2_load_pic_address ( rtx sym , int unspec , rtx tmp ) { if ( flag_pic == 2 && GET_CODE ( sym ) == SYMBOL_REF && nios2_symbol_binds_local_p ( sym ) ) { rtx offset = nios2_unspec_offset ( sym , UNSPEC_PIC_GOTOFF_SYM ) ; crtl -> uses_pic_offset_table = 1 ; return nios2_large_got_address ( offset , tmp ) ; } if ( unspec == UNSPEC_PIC_CALL_SYM ) return gen_rtx_MEM ( Pmode , nios2_got_address ( sym , unspec ) ) ; else return gen_const_mem ( Pmode , nios2_got_address ( sym , unspec ) ) ; } </s>


<s> bool ARMTargetLowering :: useLoadStackGuardNode ( ) const { return Subtarget -> getTargetTriple ( ) . getObjectFormat ( ) == Triple :: MachO ; } </s>

If this function returns true , SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic : :stackprotector .


<s> int ARMFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { return ResolveFrameIndexReference ( MF , FI , FrameReg , 0 ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"NEON register pre-allocation pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , int64_t NumBytes , bool Is64Bit , bool UseLEA , const TargetInstrInfo & TII , const TargetRegisterInfo & TRI ) { bool isSub = NumBytes < 0 ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; unsigned Opc ; if ( UseLEA ) Opc = getLEArOpcode ( Is64Bit ) ; else Opc = isSub ? getSUBriOpcode ( Is64Bit , Offset ) : getADDriOpcode ( Is64Bit , Offset ) ; uint64_t Chunk = ( 1LL << 31 ) - 1 ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; if ( ThisVal == ( Is64Bit ? 8 : 4 ) ) { unsigned Reg = isSub ? ( unsigned ) ( Is64Bit ? X86 :: RAX : X86 :: EAX ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { Opc = isSub ? ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) : ( Is64Bit ? X86 :: POP64r : X86 :: POP32r ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ; if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; Offset -= ThisVal ; continue ; } } MachineInstr * MI = NULL ; if ( UseLEA ) { MI = addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) , StackPtr , false , isSub ? - ThisVal : ThisVal ) ; } else { MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( ThisVal ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; } if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> const char * thumb_call_via_reg ( rtx reg ) { int regno = REGNO ( reg ) ; rtx * labelp ; gcc_assert ( regno < LR_REGNUM ) ; if ( in_section == text_section ) { thumb_call_reg_needed = 1 ; if ( thumb_call_via_label [ regno ] == NULL ) thumb_call_via_label [ regno ] = gen_label_rtx ( ) ; labelp = thumb_call_via_label + regno ; } else { if ( cfun -> machine -> call_via [ regno ] == NULL ) cfun -> machine -> call_via [ regno ] = gen_label_rtx ( ) ; labelp = cfun -> machine -> call_via + regno ; } output_asm_insn ( "bl\t%a0" , labelp ) ; return "" ; } </s>

Output a call-via instruction for thumb state .


<s> bool HSAILInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MBBI ) const { MachineInstr & MI = * MBBI ; return HSAILGenInstrInfo :: expandPostRAPseudo ( MI ) ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> static int maybe_split_mode ( machine_mode * pmode ) { machine_mode mode = * pmode ; if ( COMPLEX_MODE_P ( mode ) ) { * pmode = GET_MODE_INNER ( mode ) ; return 2 ; } else if ( mode == TImode ) { * pmode = DImode ; return 2 ; } return 1 ; } </s>

Return the number of pieces to use when dealing with a pseudo of * PMODE . Alter * PMODE if we return a number greater than one .


<s>
bool
HexagonPacketizer
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
DisablePacketizer
||
skipFunction
(
*
MF
.
getFunction
(
)
)
)
return
false
;
HII
=
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getInstrInfo
(
)
;
HRI
=
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getRegisterInfo
(
)
;
auto
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
auto
*
AA
=
&
getAnalysis
<
AAResultsWrapperPass
>
(
)
.
getAAResults
(
)
;
auto
*
MBPI
=
&
getAnalysis
<
MachineBranchProbabilityInfo
>
(
)
;
if
(
EnableGenAllInsnClass
)
HII
->
genAllInsnTimingClasses
(
MF
)
;
HexagonPacketizerList
Packetizer
(
MF
,
MLI
,
AA
,
MBPI
)
;
assert
(
Packetizer
.
getResourceTracker
(
)
&&
"Empty DFA table!"
)
;
for
(
auto
&
MB
:
MF
)
{
auto
End
=
MB
.
end
(
)
;
auto
MI
=
MB
.
begin
(
)
;
while
(
MI
!=
End
)
{
auto
NextI
=
std
::
next
(
MI
)
;
if
(
MI
->
isKill
(
)
)
{
MB
.
erase
(
MI
)
;
End
=
MB
.
end
(
)
;
}
MI
=
NextI
;
}
}
for
(
auto
&
MB
:
MF
)
{
auto
Begin
=
MB
.
begin
(
)
,
End
=
MB
.
end
(
)
;
while
(
Begin
!=
End
)
{
MachineBasicBlock
::
iterator
RB
=
Begin
;
while
(
RB
!=
End
&&
HII
->
isSchedulingBoundary
(
RB
,
&
MB
,
MF
)
)
++
RB
;
MachineBasicBlock
::
iterator
RE
=
RB
;
while
(
RE
!=
End
&&
!
HII
->
isSchedulingBoundary
(
RE
,
&
MB
,
MF
)
)
++
RE
;
if
(
RE
!=
End
)
++
RE
;
if
(
RB
!=
End
)
Packetizer
.
PacketizeMIs
(
&
MB
,
RB
,
RE
)
;
Begin
=
RE
;
}
}
Packetizer
.
unpacketizeSoloInstrs
(
MF
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .

Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
"Empty DFA table!"


<s> static const char * rs6000_mangle_type ( const_tree type ) { type = TYPE_MAIN_VARIANT ( type ) ; if ( TREE_CODE ( type ) != VOID_TYPE && TREE_CODE ( type ) != BOOLEAN_TYPE && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE ) return NULL ; if ( type == bool_char_type_node ) return "U6__boolc" ; if ( type == bool_short_type_node ) return "U6__bools" ; if ( type == pixel_type_node ) return "u7__pixel" ; if ( type == bool_int_type_node ) return "U6__booli" ; if ( type == bool_long_type_node ) return "U6__booll" ; if ( TARGET_FLOAT128 ) { if ( type == ieee128_float_type_node ) return "U10__float128" ; if ( type == ibm128_float_type_node ) return "g" ; if ( type == long_double_type_node && TARGET_LONG_DOUBLE_128 ) return ( TARGET_IEEEQUAD ) ? "U10__float128" : "g" ; } if ( TYPE_MAIN_VARIANT ( type ) == long_double_type_node && TARGET_ELF && TARGET_LONG_DOUBLE_128 && ! TARGET_IEEEQUAD ) return "g" ; return NULL ; } </s>

AltiVec defines five built-in scalar types that serve as vector elements ; we must teach the compiler how to mangle them . The 128-bit floating point mangling is target-specific as well . MMA defines two built-in types to be used as opaque vector types .


<s> bool X86FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; unsigned SlotSize = STI . is64Bit ( ) ? 8 : 4 ; unsigned FPReg = TRI -> getFrameRegister ( MF ) ; unsigned CalleeFrameSize = 0 ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned Opc = STI . is64Bit ( ) ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; if ( Reg == FPReg ) continue ; CalleeFrameSize += SlotSize ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) ; } X86FI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - 1 ] . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> const SDValue & getIndex ( ) const { return getOperand ( 4 ) ; } </s>


<s> bool targetSchedulesPostRAScheduling ( ) const override { return true ; } </s>

True if subtarget inserts the final scheduling pass on its own .


"Unexpected register class in CSRsViaCopy!"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s>
void
ARMAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
unsigned
Kind
=
Fixup
.
getKind
(
)
;
if
(
Kind
>=
FirstLiteralRelocationKind
)
return
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
Value
=
adjustFixupValue
(
Asm
,
Fixup
,
Target
,
Value
,
IsResolved
,
Ctx
,
STI
)
;
if
(
!
Value
)
return
;
const
unsigned
NumBytes
=
getFixupKindNumBytes
(
Kind
)
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
unsigned
FullSizeBytes
;
if
(
Endian
==
support
::
big
)
{
FullSizeBytes
=
getFixupKindContainerSizeBytes
(
Kind
)
;
assert
(
(
Offset
+
FullSizeBytes
)
<=
Data
.
size
(
)
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FullSizeBytes
&&
"Invalid fixup size!"
)
;
}
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
Endian
==
support
::
little
i
:
(
FullSizeBytes
1
i
)
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> rtx pure_scalable_type_info :: get_rtx ( machine_mode mode , unsigned int first_zr , unsigned int first_pr ) const { if ( mode == pieces [ 0 ] . mode ) { gcc_assert ( pieces . length ( ) == 1 ) ; return pieces [ 0 ] . get_rtx ( first_zr , first_pr ) ; } rtvec rtxes = rtvec_alloc ( pieces . length ( ) ) ; for ( unsigned int i = 0 ; i < pieces . length ( ) ; ++ i ) { rtx reg = pieces [ i ] . get_rtx ( first_zr , first_pr ) ; rtx offset = gen_int_mode ( pieces [ i ] . offset , Pmode ) ; RTVEC_ELT ( rtxes , i ) = gen_rtx_EXPR_LIST ( VOIDmode , reg , offset ) ; first_zr += pieces [ i ] . num_zr ; first_pr += pieces [ i ] . num_pr ; } return gen_rtx_PARALLEL ( mode , rtxes ) ; } </s>

Return the location of a PST that is known to be passed or returned in registers . FIRST_ZR is the first unused vector argument register and FIRST_PR is the first unused predicate argument register .


<s> bool ARMSubtarget :: useDFAforSMS ( ) const { return false ; } </s>

Default to DFA for resource management , return false when target will use ProcResource in InstrSchedModel instead .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> llvm :: FastISel * AArch64 :: createFastISel ( FunctionLoweringInfo & FuncInfo , const TargetLibraryInfo * LibInfo ) { return new AArch64FastISel ( FuncInfo , LibInfo ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> void sh_emit_scc_to_t ( enum rtx_code code , rtx op0 , rtx op1 ) { rtx t_reg = get_t_reg_rtx ( ) ; enum rtx_code oldcode = code ; switch ( code ) { case NE : gcc_unreachable ( ) ; case LT : code = GT ; break ; case LE : code = GE ; break ; case LTU : code = GTU ; break ; case LEU : code = GEU ; break ; default : break ; } if ( code != oldcode ) std :: swap ( op0 , op1 ) ; machine_mode mode = GET_MODE ( op0 ) ; if ( mode == VOIDmode ) mode = GET_MODE ( op1 ) ; op0 = force_reg ( mode , op0 ) ; if ( ( code != EQ && code != NE && ( op1 != const0_rtx || code == GTU || code == GEU || code == LTU || code == LEU ) ) || ( mode == DImode && op1 != const0_rtx ) || ( TARGET_SH2E && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) ) op1 = force_reg ( mode , op1 ) ; sh_emit_set_t_insn ( gen_rtx_SET ( t_reg , gen_rtx_fmt_ee ( code , SImode , op0 , op1 ) ) , mode ) ; } </s>

Prepare the operands for an scc instruction ; make sure that the compare has been done and the result is in T_REG .


<s> void HexagonInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { if ( Hexagon :: IntRegsRegClass . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: A2_tfr ) , DestReg ) . addReg ( SrcReg ) ; return ; } if ( Hexagon :: DoubleRegsRegClass . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: A2_tfrp ) , DestReg ) . addReg ( SrcReg ) ; return ; } if ( Hexagon :: PredRegsRegClass . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: C2_or ) , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg ) ; return ; } if ( Hexagon :: DoubleRegsRegClass . contains ( DestReg ) && Hexagon :: IntRegsRegClass . contains ( SrcReg ) ) { if ( SrcReg == RI . getSubReg ( DestReg , Hexagon :: subreg_loreg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: A2_tfrsi ) , ( RI . getSubReg ( DestReg , Hexagon :: subreg_hireg ) ) ) . addImm ( 0 ) ; } else { BuildMI ( MBB , I , DL , get ( Hexagon :: A2_tfr ) , ( RI . getSubReg ( DestReg , Hexagon :: subreg_loreg ) ) ) . addReg ( SrcReg ) ; BuildMI ( MBB , I , DL , get ( Hexagon :: A2_tfrsi ) , ( RI . getSubReg ( DestReg , Hexagon :: subreg_hireg ) ) ) . addImm ( 0 ) ; } return ; } if ( Hexagon :: CtrRegsRegClass . contains ( DestReg ) && Hexagon :: IntRegsRegClass . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: A2_tfrrcr ) , DestReg ) . addReg ( SrcReg ) ; return ; } if ( Hexagon :: PredRegsRegClass . contains ( SrcReg ) && Hexagon :: IntRegsRegClass . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: C2_tfrpr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } if ( Hexagon :: IntRegsRegClass . contains ( SrcReg ) && Hexagon :: PredRegsRegClass . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: C2_tfrrp ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } llvm_unreachable ( "Unimplemented" ) ; } </s>


<s>
void
StackPU2MCInstLower
::
lowerInstruction
(
const
MachineInstr
&
MI
,
MCInst
&
OutMI
)
const
{
OutMI
.
setOpcode
(
MI
.
getOpcode
(
)
)
;
for
(
MachineOperand
const
&
MO
:
MI
.
operands
(
)
)
{
MCOperand
MCOp
;
switch
(
MO
.
getType
(
)
)
{
default
:
MI
.
print
(
errs
(
)
)
;
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
)
continue
;
MCOp
=
MCOperand
::
createReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
createImm
(
MO
.
getImm
(
)
)
;
break
;
}
OutMI
.
addOperand
(
MCOp
)
;
}
}
</s>


<s> static void aarch64_save_callee_saves ( machine_mode mode , HOST_WIDE_INT start_offset , unsigned start , unsigned limit , bool skip_wb ) { rtx_insn * insn ; rtx ( * gen_mem_ref ) ( machine_mode , rtx ) = ( frame_pointer_needed ? gen_frame_mem : gen_rtx_MEM ) ; unsigned regno ; unsigned regno2 ; for ( regno = aarch64_next_callee_save ( start , limit ) ; regno <= limit ; regno = aarch64_next_callee_save ( regno + 1 , limit ) ) { rtx reg , mem ; HOST_WIDE_INT offset ; if ( skip_wb && ( regno == cfun -> machine -> frame . wb_candidate1 || regno == cfun -> machine -> frame . wb_candidate2 ) ) continue ; if ( cfun -> machine -> reg_is_wrapped_separately [ regno ] ) continue ; reg = gen_rtx_REG ( mode , regno ) ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno ] ; mem = gen_mem_ref ( mode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; regno2 = aarch64_next_callee_save ( regno + 1 , limit ) ; if ( regno2 <= limit && ! cfun -> machine -> reg_is_wrapped_separately [ regno2 ] && ( ( cfun -> machine -> frame . reg_offset [ regno ] + UNITS_PER_WORD ) == cfun -> machine -> frame . reg_offset [ regno2 ] ) ) { rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; rtx mem2 ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno2 ] ; mem2 = gen_mem_ref ( mode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; insn = emit_insn ( aarch64_gen_store_pair ( mode , mem , reg , mem2 , reg2 ) ) ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , 0 , 1 ) ) = 1 ; regno = regno2 ; } else insn = emit_move_insn ( mem , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } </s>

Emit code to save the callee-saved registers from register number START to LIMIT to the stack at the location starting at offset START_OFFSET , skipping any write-back candidates if SKIP_WB is true .


<s> void NVPTXPassConfig :: addIRPasses ( ) { disablePass ( & PrologEpilogCodeInserterID ) ; disablePass ( & MachineCopyPropagationID ) ; disablePass ( & TailDuplicateID ) ; disablePass ( & StackMapLivenessID ) ; disablePass ( & LiveDebugValuesID ) ; disablePass ( & PostRASchedulerID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & PatchableFunctionID ) ; addPass ( createNVVMReflectPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createNVPTXImageOptimizerPass ( ) ) ; addPass ( createNVPTXAssignValidGlobalNamesPass ( ) ) ; addPass ( createGenericToNVVMPass ( ) ) ; addPass ( createNVPTXLowerArgsPass ( & getNVPTXTargetMachine ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addAddressSpaceInferencePasses ( ) ; if ( ! DisableLoadStoreVectorizer ) addPass ( createLoadStoreVectorizerPass ( ) ) ; addStraightLineScalarOptimizationPasses ( ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addEarlyCSEOrGVNPass ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> bool AMDGPUAnnotateKernelFeatures :: runOnModule ( Module & M ) { Triple TT ( M . getTargetTriple ( ) ) ; AS = AMDGPU :: getAMDGPUAS ( M ) ; static const StringRef IntrinsicToAttr [ ] [ 2 ] = { { "llvm.amdgcn.workitem.id.y" , "amdgpu-work-item-id-y" } , { "llvm.amdgcn.workitem.id.z" , "amdgpu-work-item-id-z" } , { "llvm.amdgcn.workgroup.id.y" , "amdgpu-work-group-id-y" } , { "llvm.amdgcn.workgroup.id.z" , "amdgpu-work-group-id-z" } , { "llvm.r600.read.tgid.y" , "amdgpu-work-group-id-y" } , { "llvm.r600.read.tgid.z" , "amdgpu-work-group-id-z" } , { "llvm.r600.read.tidig.y" , "amdgpu-work-item-id-y" } , { "llvm.r600.read.tidig.z" , "amdgpu-work-item-id-z" } } ; static const StringRef HSAIntrinsicToAttr [ ] [ 2 ] = { { "llvm.amdgcn.dispatch.ptr" , "amdgpu-dispatch-ptr" } , { "llvm.amdgcn.queue.ptr" , "amdgpu-queue-ptr" } , { "llvm.amdgcn.dispatch.id" , "amdgpu-dispatch-id" } , { "llvm.trap" , "amdgpu-queue-ptr" } , { "llvm.debugtrap" , "amdgpu-queue-ptr" } } ; bool Changed = addAttrsForIntrinsics ( M , IntrinsicToAttr ) ; if ( TT . getOS ( ) == Triple :: AMDHSA || TT . getOS ( ) == Triple :: Mesa3D ) { Changed |= addAttrsForIntrinsics ( M , HSAIntrinsicToAttr ) ; for ( Function & F : M ) { if ( F . hasFnAttribute ( "amdgpu-queue-ptr" ) ) continue ; auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; bool HasApertureRegs = TPC && TPC -> getTM < TargetMachine > ( ) . getSubtarget < AMDGPUSubtarget > ( F ) . hasApertureRegs ( ) ; if ( ! HasApertureRegs && hasAddrSpaceCast ( F , AS ) ) F . addFnAttr ( "amdgpu-queue-ptr" ) ; } } return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> static bool spu_addr_space_legitimate_address_p ( machine_mode mode , rtx x , bool reg_ok_strict , addr_space_t as ) { if ( as == ADDR_SPACE_EA ) return ( REG_P ( x ) && ( GET_MODE ( x ) == EAmode ) ) ; else if ( as != ADDR_SPACE_GENERIC ) gcc_unreachable ( ) ; return spu_legitimate_address_p ( mode , x , reg_ok_strict ) ; } </s>

Like spu_legitimate_address_p , except with named addresses .


<s>
bool
HexagonInstrInfo
::
getBaseAndOffsetPosition
(
const
MachineInstr
*
MI
,
unsigned
&
BasePos
,
unsigned
&
OffsetPos
)
const
{
if
(
isMemOp
(
MI
)
)
{
assert
(
MI
->
getOperand
(
0
)
.
isReg
(
)
&&
MI
->
getOperand
(
1
)
.
isImm
(
)
&&
"Bad Memop."
)
;
BasePos
=
0
;
OffsetPos
=
1
;
}
else
if
(
MI
->
mayStore
(
)
)
{
BasePos
=
0
;
OffsetPos
=
1
;
}
else
if
(
MI
->
mayLoad
(
)
)
{
BasePos
=
1
;
OffsetPos
=
2
;
}
else
return
false
;
if
(
isPredicated
(
*
MI
)
)
{
BasePos
++
;
OffsetPos
++
;
}
if
(
isPostIncrement
(
MI
)
)
{
BasePos
++
;
OffsetPos
++
;
}
if
(
!
MI
->
getOperand
(
BasePos
)
.
isReg
(
)
||
!
MI
->
getOperand
(
OffsetPos
)
.
isImm
(
)
)
return
false
;
return
true
;
}
</s>

Return true if the instruction contains a base register and offset .


<s>
bool
AMDGPUAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
setForcedEncodingSize
(
0
)
;
if
(
Name
.
endswith
(
"_e64"
)
)
setForcedEncodingSize
(
64
)
;
else
if
(
Name
.
endswith
(
"_e32"
)
)
setForcedEncodingSize
(
32
)
;
Operands
.
push_back
(
AMDGPUOperand
::
CreateToken
(
Name
,
NameLoc
)
)
;
while
(
!
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
{
AMDGPUAsmParser
::
OperandMatchResultTy
Res
=
parseOperand
(
Operands
,
Name
)
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
Parser
.
Lex
(
)
;
switch
(
Res
)
{
case
MatchOperand_Success
:
break
;
case
MatchOperand_ParseFail
:
return
Error
(
getLexer
(
)
.
getLoc
(
)
,
"failed parsing operand."
)
;
case
MatchOperand_NoMatch
:
return
Error
(
getLexer
(
)
.
getLoc
(
)
,
"not a valid operand."
)
;
}
}
AMDGPUAsmParser
::
OperandMatchResultTy
Res
;
while
(
(
Res
=
parseOperand
(
Operands
,
Name
)
)
!=
MatchOperand_NoMatch
)
{
if
(
Res
!=
MatchOperand_Success
)
return
Error
(
getLexer
(
)
.
getLoc
(
)
,
"failed parsing operand."
)
;
}
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .


<s> static bool s390_can_eliminate ( const int from , const int to ) { if ( from == BASE_REGNUM && to == BASE_REGNUM ) { s390_init_frame_layout ( ) ; return cfun -> machine -> base_reg == NULL_RTX ; } gcc_assert ( to == STACK_POINTER_REGNUM || to == HARD_FRAME_POINTER_REGNUM ) ; gcc_assert ( from == FRAME_POINTER_REGNUM || from == ARG_POINTER_REGNUM || from == RETURN_ADDRESS_POINTER_REGNUM ) ; if ( from == RETURN_ADDRESS_POINTER_REGNUM ) if ( ! crtl -> calls_eh_return && ! cfun -> stdarg && ! cfun_frame_layout . save_return_addr_p ) return false ; return true ; } </s>

Return true if register FROM can be eliminated via register TO .


"Should only have an r11 thunk on 64-bit targets"

runOnMachineFunction - Emit the function body .


<s>
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
MipsTargetLowering
::
getRegForInlineAsmConstraint
(
const
std
::
string
&
Constraint
,
EVT
VT
)
const
{
if
(
Constraint
.
size
(
)
==
1
)
{
switch
(
Constraint
[
0
]
)
{
case
'd'
:
case
'y'
:
case
'r'
:
if
(
VT
==
MVT
::
i32
||
VT
==
MVT
::
i16
||
VT
==
MVT
::
i8
)
{
if
(
Subtarget
->
inMips16Mode
(
)
)
return
std
::
make_pair
(
0U
,
&
Mips
::
CPU16RegsRegClass
)
;
return
std
::
make_pair
(
0U
,
&
Mips
::
CPURegsRegClass
)
;
}
if
(
VT
==
MVT
::
i64
&&
!
HasMips64
)
return
std
::
make_pair
(
0U
,
&
Mips
::
CPURegsRegClass
)
;
if
(
VT
==
MVT
::
i64
&&
HasMips64
)
return
std
::
make_pair
(
0U
,
&
Mips
::
CPU64RegsRegClass
)
;
return
std
::
make_pair
(
0u
,
static_cast
<
const
TargetRegisterClass
*
>
(
0
)
)
;
case
'f'
:
if
(
VT
==
MVT
::
f32
)
return
std
::
make_pair
(
0U
,
&
Mips
::
FGR32RegClass
)
;
if
(
(
VT
==
MVT
::
f64
)
&&
(
!
Subtarget
->
isSingleFloat
(
)
)
)
{
if
(
Subtarget
->
isFP64bit
(
)
)
return
std
::
make_pair
(
0U
,
&
Mips
::
FGR64RegClass
)
;
return
std
::
make_pair
(
0U
,
&
Mips
::
AFGR64RegClass
)
;
}
break
;
case
'c'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
(
unsigned
)
Mips
::
T9
,
&
Mips
::
CPURegsRegClass
)
;
assert
(
VT
==
MVT
::
i64
&&
"Unexpected type."
)
;
return
std
::
make_pair
(
(
unsigned
)
Mips
::
T9_64
,
&
Mips
::
CPU64RegsRegClass
)
;
case
'l'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
(
unsigned
)
Mips
::
LO
,
&
Mips
::
HILORegClass
)
;
return
std
::
make_pair
(
(
unsigned
)
Mips
::
LO64
,
&
Mips
::
HILO64RegClass
)
;
case
'x'
:
return
std
::
make_pair
(
0u
,
static_cast
<
const
TargetRegisterClass
*
>
(
0
)
)
;
}
}
return
TargetLowering
::
getRegForInlineAsmConstraint
(
Constraint
,
VT
)
;
}
</s>

Given a physical register constraint ( e.g .


<s> const char * output_fix_trunc ( rtx_insn * insn , rtx * operands , bool fisttp ) { int stack_top_dies = find_regno_note ( insn , REG_DEAD , FIRST_STACK_REG ) != 0 ; int dimode_p = GET_MODE ( operands [ 0 ] ) == DImode ; int round_mode = get_attr_i387_cw ( insn ) ; if ( ( dimode_p || fisttp ) && ! stack_top_dies ) output_asm_insn ( "fld\t%y1" , operands ) ; gcc_assert ( STACK_TOP_P ( operands [ 1 ] ) ) ; gcc_assert ( MEM_P ( operands [ 0 ] ) ) ; gcc_assert ( GET_MODE ( operands [ 1 ] ) != TFmode ) ; if ( fisttp ) output_asm_insn ( "fisttp%Z0\t%0" , operands ) ; else { if ( round_mode != I387_CW_ANY ) output_asm_insn ( "fldcw\t%3" , operands ) ; if ( stack_top_dies || dimode_p ) output_asm_insn ( "fistp%Z0\t%0" , operands ) ; else output_asm_insn ( "fist%Z0\t%0" , operands ) ; if ( round_mode != I387_CW_ANY ) output_asm_insn ( "fldcw\t%2" , operands ) ; } return "" ; } </s>

Output code for INSN to convert a float to a signed int . OPERANDS are the insn operands . The output may be [ HSD ] Imode and the input operand may be [ SDX ] Fmode .


<s> static tree get_prev_label ( tree function_name ) { branch_island * bi ; unsigned ix ; FOR_EACH_VEC_SAFE_ELT ( branch_islands , ix , bi ) if ( function_name == bi -> function_name ) return bi -> label_name ; return NULL_TREE ; } </s>

GET_PREV_LABEL gets the label name from the previous definition of the function .


<s> Register X86TargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { if ( classifyEHPersonality ( PersonalityFn ) == EHPersonality :: CoreCLR ) return Subtarget . isTarget64BitLP64 ( ) ? X86 :: RDX : X86 :: EDX ; return Subtarget . isTarget64BitLP64 ( ) ? X86 :: RAX : X86 :: EAX ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s> bool M88kFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) return true ; return ( MFI . hasCalls ( ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static bool need_to_save_reg ( unsigned int regno ) { if ( ! call_used_or_fixed_reg_p ( regno ) && df_regs_ever_live_p ( regno ) ) return true ; if ( flag_pic && ( regno == PIC_OFFSET_TABLE_REGNUM || regno == TILEGX_PIC_TEXT_LABEL_REGNUM ) && ( crtl -> uses_pic_offset_table || crtl -> saves_all_registers ) ) return true ; if ( crtl -> calls_eh_return ) { unsigned i ; for ( i = 0 ; EH_RETURN_DATA_REGNO ( i ) != INVALID_REGNUM ; i ++ ) { if ( regno == EH_RETURN_DATA_REGNO ( i ) ) return true ; } } return false ; } </s>

Return whether REGNO needs to be saved in the stack frame .


"Not all fixup kinds added to Infos array"


<s> bool CAHPAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { if ( ( Count % 2 ) != 0 ) return false ; Count /= 2 ; for ( uint64_t i = 0 ; i < Count ; ++ i ) OS . write ( "\0\0" , 2 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> SDNode * HexagonDAGToDAGISel :: Select ( SDNode * N ) { if ( N -> isMachineOpcode ( ) ) { N -> setNodeId ( - 1 ) ; return NULL ; } switch ( N -> getOpcode ( ) ) { case ISD :: Constant : return SelectConstant ( N ) ; case ISD :: ConstantFP : return SelectConstantFP ( N ) ; case ISD :: ADD : return SelectAdd ( N ) ; case ISD :: SHL : return SelectSHL ( N ) ; case ISD :: LOAD : return SelectLoad ( N ) ; case ISD :: STORE : return SelectStore ( N ) ; case ISD :: SELECT : return SelectSelect ( N ) ; case ISD :: TRUNCATE : return SelectTruncate ( N ) ; case ISD :: MUL : return SelectMul ( N ) ; case ISD :: ZERO_EXTEND : return SelectZeroExtend ( N ) ; case ISD :: INTRINSIC_WO_CHAIN : return SelectIntrinsicWOChain ( N ) ; } return SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .

Hexagon Hexagon 1 ISD::Constant ISD::ConstantFP ISD::ADD ISD::SHL ISD::LOAD ISD::STORE ISD::SELECT ISD::TRUNCATE ISD::MUL ISD::ZERO_EXTEND ISD::INTRINSIC_WO_CHAIN


<s> static void vax_file_start ( void ) { default_file_start ( ) ; if ( write_symbols == DBX_DEBUG ) fprintf ( asm_out_file , "___vax_%c_doubles:\n" , ASM_DOUBLE_CHAR ) ; } </s>

When debugging with stabs , we want to output an extra dummy label so that gas can distinguish between D_float and G_float prior to processing the .stabs directive identifying type double .


<s>
static
const
char
*
singlemove_string
(
rtx
*
operands
)
{
if
(
GET_CODE
(
operands
[
1
]
)
==
CONST_INT
)
return
output_move_simode_const
(
operands
)
;
return
"move%.l %1,%0"
;
}
</s>

Return the best assembler insn template for moving operands [ 1 ] into operands [ 0 ] as a fullword .


<s> MCSymbol * WebAssemblyMCInstLower :: GetExternalSymbolSymbol ( const MachineOperand & MO ) const { const char * Name = MO . getSymbolName ( ) ; auto * WasmSym = cast < MCSymbolWasm > ( Printer . GetExternalSymbolSymbol ( Name ) ) ; const WebAssemblySubtarget & Subtarget = Printer . getSubtarget ( ) ; if ( strcmp ( Name , "__stack_pointer" ) == 0 || strcmp ( Name , "__tls_base" ) == 0 || strcmp ( Name , "__memory_base" ) == 0 || strcmp ( Name , "__table_base" ) == 0 || strcmp ( Name , "__tls_size" ) == 0 || strcmp ( Name , "__tls_align" ) == 0 ) { bool Mutable = strcmp ( Name , "__stack_pointer" ) == 0 || strcmp ( Name , "__tls_base" ) == 0 ; WasmSym -> setType ( wasm :: WASM_SYMBOL_TYPE_GLOBAL ) ; WasmSym -> setGlobalType ( wasm :: WasmGlobalType { uint8_t ( Subtarget . hasAddr64 ( ) ? wasm :: WASM_TYPE_I64 : wasm :: WASM_TYPE_I32 ) , Mutable } ) ; return WasmSym ; } SmallVector < wasm :: ValType , 4 > Returns ; SmallVector < wasm :: ValType , 4 > Params ; if ( strcmp ( Name , "__cpp_exception" ) == 0 ) { WasmSym -> setType ( wasm :: WASM_SYMBOL_TYPE_EVENT ) ; WasmSym -> setEventType ( { wasm :: WASM_EVENT_ATTRIBUTE_EXCEPTION , 0 } ) ; WasmSym -> setWeak ( true ) ; WasmSym -> setExternal ( true ) ; Params . push_back ( Subtarget . hasAddr64 ( ) ? wasm :: ValType :: I64 : wasm :: ValType :: I32 ) ; } else { WasmSym -> setType ( wasm :: WASM_SYMBOL_TYPE_FUNCTION ) ; getLibcallSignature ( Subtarget , Name , Returns , Params ) ; } auto Signature = std :: make_unique < wasm :: WasmSignature > ( std :: move ( Returns ) , std :: move ( Params ) ) ; WasmSym -> setSignature ( Signature . get ( ) ) ; Printer . addSignature ( std :: move ( Signature ) ) ; return WasmSym ; } </s>

Return the MCSymbol for the specified ExternalSymbol .


<s> void tilepro_expand_insv ( rtx operands [ 4 ] ) { rtx first_rtx = operands [ 2 ] ; HOST_WIDE_INT first = INTVAL ( first_rtx ) ; HOST_WIDE_INT width = INTVAL ( operands [ 1 ] ) ; rtx v = operands [ 3 ] ; if ( first != 0 ) { if ( CONST_INT_P ( v ) ) { v = gen_int_si ( INTVAL ( v ) << first ) ; } else { rtx tmp = gen_reg_rtx ( SImode ) ; emit_insn ( gen_ashlsi3 ( tmp , v , first_rtx ) ) ; v = tmp ; } } emit_insn ( gen_insn_mm ( operands [ 0 ] , v , operands [ 0 ] , first_rtx , GEN_INT ( first + width - 1 ) ) ) ; } </s>


<s> static bool rs6000_attribute_takes_identifier_p ( const_tree attr_id ) { return is_attribute_p ( "altivec" , attr_id ) ; } </s>

Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain identifier as an argument , so the front end should n't look it up .


<s> static gimple * va_list_skip_additions ( tree lhs ) { gimple * stmt ; for ( ; ; ) { enum tree_code code ; stmt = SSA_NAME_DEF_STMT ( lhs ) ; if ( gimple_code ( stmt ) == GIMPLE_PHI ) return stmt ; if ( ! is_gimple_assign ( stmt ) || gimple_assign_lhs ( stmt ) != lhs ) return NULL ; if ( TREE_CODE ( gimple_assign_rhs1 ( stmt ) ) != SSA_NAME ) return stmt ; code = gimple_assign_rhs_code ( stmt ) ; if ( ! CONVERT_EXPR_CODE_P ( code ) && ( ( code != PLUS_EXPR && code != POINTER_PLUS_EXPR ) || TREE_CODE ( gimple_assign_rhs2 ( stmt ) ) != INTEGER_CST || ! tree_fits_uhwi_p ( gimple_assign_rhs2 ( stmt ) ) ) ) return stmt ; lhs = gimple_assign_rhs1 ( stmt ) ; } } </s>

Helper function for alpha_stdarg_optimize_hook . Skip over casts and constant additions .


<s> static tree rx_builtin_decl ( unsigned code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= RX_BUILTIN_max ) return error_mark_node ; return rx_builtins [ code ] ; } </s>


<s>
static
void
handle_special_swappables
(
swap_web_entry
*
insn_entry
,
unsigned
i
)
{
rtx_insn
*
insn
=
insn_entry
[
i
]
.
insn
;
rtx
body
=
PATTERN
(
insn
)
;
switch
(
insn_entry
[
i
]
.
special_handling
)
{
default
:
gcc_unreachable
(
)
;
case
SH_CONST_VECTOR
:
{
gcc_assert
(
GET_CODE
(
body
)
==
SET
)
;
rtx
rhs
=
SET_SRC
(
body
)
;
swap_const_vector_halves
(
rhs
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Swapping constant halves in insn %d\n"
,
i
)
;
break
;
}
case
SH_SUBREG
:
adjust_subreg_index
(
body
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Adjusting subreg in insn %d\n"
,
i
)
;
break
;
case
SH_NOSWAP_LD
:
permute_load
(
insn
)
;
break
;
case
SH_NOSWAP_ST
:
permute_store
(
insn
)
;
break
;
case
SH_EXTRACT
:
adjust_extract
(
insn
)
;
break
;
case
SH_SPLAT
:
adjust_splat
(
insn
)
;
break
;
}
}
</s>

The insn described by INSN_ENTRY [ I ] can be swapped , but only with special handling . Take care of that here .

rs6000
"Swapping constant halves in insn %d\n"
"Adjusting subreg in insn %d\n"


"%<-fpic%> and %<-fPIC%> not supported without %<-mdsbt%> "


<s> bool X86FastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { const Value * Ptr = LI -> getPointerOperand ( ) ; X86AddressMode AM ; if ( ! X86SelectAddress ( Ptr , AM ) ) return false ; const X86InstrInfo & XII = ( const X86InstrInfo & ) TII ; unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; unsigned Alignment = LI -> getAlignment ( ) ; if ( Alignment == 0 ) Alignment = DL . getABITypeAlignment ( LI -> getType ( ) ) ; SmallVector < MachineOperand , 8 > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , * MI , OpNo , AddrOps , FuncInfo . InsertPt , Size , Alignment , true ) ; if ( ! Result ) return false ; unsigned OperandNo = 0 ; for ( MachineInstr :: mop_iterator I = Result -> operands_begin ( ) , E = Result -> operands_end ( ) ; I != E ; ++ I , ++ OperandNo ) { MachineOperand & MO = * I ; if ( ! MO . isReg ( ) || MO . isDef ( ) || MO . getReg ( ) != AM . IndexReg ) continue ; unsigned IndexReg = constrainOperandRegClass ( Result -> getDesc ( ) , MO . getReg ( ) , OperandNo ) ; if ( IndexReg == MO . getReg ( ) ) continue ; MO . setReg ( IndexReg ) ; } Result -> addMemOperand ( * FuncInfo . MF , createMachineMemOperandFor ( LI ) ) ; MI -> eraseFromParent ( ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> bool can_be_rotated_to_negative_15bits ( HOST_WIDE_INT c ) { int rot = 0 ; bool res = can_be_rotated_to_lowbits ( ~ c , 15 , & rot ) ; return res && rot > 0 ; } </s>

Check if C ( as 64bit integer ) can be rotated to a negative 15bits constant which contains 49bits leading ones and 15bits of any value .


<s> int X86TTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; unsigned ImmIdx = ~ 0U ; switch ( Opcode ) { default : return TTI :: TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: Store : ImmIdx = 0 ; break ; case Instruction :: ICmp : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 ) { uint64_t ImmVal = Imm . getZExtValue ( ) ; if ( ImmVal == 0x100000000ULL || ImmVal == 0xffffffff ) return TTI :: TCC_Free ; } ImmIdx = 1 ; break ; case Instruction :: And : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 && isUInt < 32 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; ImmIdx = 1 ; break ; case Instruction :: Add : case Instruction :: Sub : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 && Imm . getZExtValue ( ) == 0x80000000 ) return TTI :: TCC_Free ; ImmIdx = 1 ; break ; case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : return TTI :: TCC_Free ; case Instruction :: Mul : case Instruction :: Or : case Instruction :: Xor : ImmIdx = 1 ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == 1 ) return TTI :: TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: IntToPtr : case Instruction :: PtrToInt : case Instruction :: BitCast : case Instruction :: PHI : case Instruction :: Call : case Instruction :: Select : case Instruction :: Ret : case Instruction :: Load : break ; } if ( Idx == ImmIdx ) { int NumConstants = divideCeil ( BitSize , 64 ) ; int Cost = X86TTIImpl :: getIntImmCost ( Imm , Ty ) ; return ( Cost <= NumConstants * TTI :: TCC_Basic ) ? static_cast < int > ( TTI :: TCC_Free ) : Cost ; } return X86TTIImpl :: getIntImmCost ( Imm , Ty ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> bool PPCTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , unsigned Intrinsic ) const { switch ( Intrinsic ) { case Intrinsic :: ppc_altivec_lvx : case Intrinsic :: ppc_altivec_lvxl : case Intrinsic :: ppc_altivec_lvebx : case Intrinsic :: ppc_altivec_lvehx : case Intrinsic :: ppc_altivec_lvewx : { EVT VT ; switch ( Intrinsic ) { case Intrinsic :: ppc_altivec_lvebx : VT = MVT :: i8 ; break ; case Intrinsic :: ppc_altivec_lvehx : VT = MVT :: i16 ; break ; case Intrinsic :: ppc_altivec_lvewx : VT = MVT :: i32 ; break ; default : VT = MVT :: v4i32 ; break ; } Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = VT ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = - VT . getStoreSize ( ) + 1 ; Info . size = 2 * VT . getStoreSize ( ) - 1 ; Info . align = 1 ; Info . vol = false ; Info . readMem = true ; Info . writeMem = false ; return true ; } case Intrinsic :: ppc_altivec_stvx : case Intrinsic :: ppc_altivec_stvxl : case Intrinsic :: ppc_altivec_stvebx : case Intrinsic :: ppc_altivec_stvehx : case Intrinsic :: ppc_altivec_stvewx : { EVT VT ; switch ( Intrinsic ) { case Intrinsic :: ppc_altivec_stvebx : VT = MVT :: i8 ; break ; case Intrinsic :: ppc_altivec_stvehx : VT = MVT :: i16 ; break ; case Intrinsic :: ppc_altivec_stvewx : VT = MVT :: i32 ; break ; default : VT = MVT :: v4i32 ; break ; } Info . opc = ISD :: INTRINSIC_VOID ; Info . memVT = VT ; Info . ptrVal = I . getArgOperand ( 1 ) ; Info . offset = - VT . getStoreSize ( ) + 1 ; Info . size = 2 * VT . getStoreSize ( ) - 1 ; Info . align = 1 ; Info . vol = false ; Info . readMem = false ; Info . writeMem = true ; return true ; } default : break ; } return false ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s>
bool
AMDGPULegalizerInfo
::
legalizeCustom
(
MachineInstr
&
MI
,
MachineRegisterInfo
&
MRI
,
MachineIRBuilder
&
MIRBuilder
,
GISelChangeObserver
&
Observer
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
case
TargetOpcode
::
G_ADDRSPACE_CAST
:
return
legalizeAddrSpaceCast
(
MI
,
MRI
,
MIRBuilder
)
;
default
:
return
false
;
}
llvm_unreachable
(
"expected switch to return"
)
;
}
</s>

Called for instructions with the Custom LegalizationAction .

AMDGPU
AMDGPU
"expected switch to return"


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static bool ix86_legitimate_combined_insn ( rtx_insn * insn ) { if ( ( INSN_CODE ( insn ) = recog ( PATTERN ( insn ) , insn , 0 ) ) >= 0 ) { int i ; extract_insn ( insn ) ; preprocess_constraints ( insn ) ; int n_operands = recog_data . n_operands ; int n_alternatives = recog_data . n_alternatives ; for ( i = 0 ; i < n_operands ; i ++ ) { rtx op = recog_data . operand [ i ] ; machine_mode mode = GET_MODE ( op ) ; const operand_alternative * op_alt ; int offset = 0 ; bool win ; int j ; if ( ! TARGET_AVX && VECTOR_MODE_P ( mode ) && misaligned_operand ( op , mode ) ) { unsigned int min_align = get_attr_ssememalign ( insn ) ; if ( min_align == 0 || MEM_ALIGN ( op ) < min_align ) return false ; } if ( UNARY_P ( op ) ) op = XEXP ( op , 0 ) ; if ( SUBREG_P ( op ) ) { if ( REG_P ( SUBREG_REG ( op ) ) && REGNO ( SUBREG_REG ( op ) ) < FIRST_PSEUDO_REGISTER ) offset = subreg_regno_offset ( REGNO ( SUBREG_REG ( op ) ) , GET_MODE ( SUBREG_REG ( op ) ) , SUBREG_BYTE ( op ) , GET_MODE ( op ) ) ; op = SUBREG_REG ( op ) ; } if ( ! ( REG_P ( op ) && HARD_REGISTER_P ( op ) ) ) continue ; op_alt = recog_op_alt ; win = ! n_alternatives ; alternative_mask preferred = get_preferred_alternatives ( insn ) ; for ( j = 0 ; j < n_alternatives ; j ++ , op_alt += n_operands ) { if ( ! TEST_BIT ( preferred , j ) ) continue ; if ( op_alt [ i ] . anything_ok || ( op_alt [ i ] . matches != - 1 && operands_match_p ( recog_data . operand [ i ] , recog_data . operand [ op_alt [ i ] . matches ] ) ) || reg_fits_class_p ( op , op_alt [ i ] . cl , offset , mode ) ) { win = true ; break ; } } if ( ! win ) return false ; } } return true ; } </s>

Implement the TARGET_LEGITIMATE_COMBINED_INSN hook .


"Extract '_init_array' kernel object kernel object"

"Extract '_fini_array' kernel object kernel object"

Read a HSA Code Object ( HSACO ) from file , and load it into the device .


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel , MCContext & Ctx ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittleEndian ? i : ( NumBytes - 1 - i ) ; Data [ Offset + i ] |= uint8_t ( ( Value >> ( Idx * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
const
char
*
getPassName
(
)
const
{
return
"Dead register definitions"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
void
AArch64FrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
const
AArch64InstrInfo
*
TII
=
static_cast
<
const
AArch64InstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
DebugLoc
DL
=
I
->
getDebugLoc
(
)
;
unsigned
Opc
=
I
->
getOpcode
(
)
;
bool
IsDestroy
=
Opc
==
TII
->
getCallFrameDestroyOpcode
(
)
;
uint64_t
CalleePopAmount
=
IsDestroy
I
->
getOperand
(
1
)
.
getImm
(
)
:
0
;
const
TargetFrameLowering
*
TFI
=
MF
.
getSubtarget
(
)
.
getFrameLowering
(
)
;
if
(
!
TFI
->
hasReservedCallFrame
(
MF
)
)
{
unsigned
Align
=
getStackAlignment
(
)
;
int64_t
Amount
=
I
->
getOperand
(
0
)
.
getImm
(
)
;
Amount
=
RoundUpToAlignment
(
Amount
,
Align
)
;
if
(
!
IsDestroy
)
Amount
=
Amount
;
if
(
CalleePopAmount
==
0
)
{
assert
(
Amount
>
0xffffff
&&
Amount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
Amount
,
TII
)
;
}
}
else
if
(
CalleePopAmount
!=
0
)
{
assert
(
CalleePopAmount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
CalleePopAmount
,
TII
)
;
}
MBB
.
erase
(
I
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> int m32r_not_same_reg ( rtx a , rtx b ) { int reg_a = - 1 ; int reg_b = - 2 ; while ( GET_CODE ( a ) == SUBREG ) a = SUBREG_REG ( a ) ; if ( REG_P ( a ) ) reg_a = REGNO ( a ) ; while ( GET_CODE ( b ) == SUBREG ) b = SUBREG_REG ( b ) ; if ( REG_P ( b ) ) reg_b = REGNO ( b ) ; return reg_a != reg_b ; } </s>

Returns true if the registers contained in the two rtl expressions are different .


<s> bool ix86_unary_operator_ok ( enum rtx_code , machine_mode , rtx operands [ 2 ] ) { if ( ( MEM_P ( operands [ 0 ] ) || MEM_P ( operands [ 1 ] ) ) && ! rtx_equal_p ( operands [ 0 ] , operands [ 1 ] ) ) return false ; return true ; } </s>

Return TRUE or FALSE depending on whether the unary operator meets the appropriate constraints .


<s> static rtx nios2_ldst_parallel ( bool load_p , bool reg_inc_p , bool offset_inc_p , rtx base_mem , int base_update , unsigned HOST_WIDE_INT regmask , bool ret_p ) { rtvec p ; int regno , b = 0 , i = 0 , n = 0 , len = popcount_hwi ( regmask ) ; if ( ret_p ) len ++ , i ++ , b ++ ; if ( base_update != 0 ) len ++ , i ++ ; p = rtvec_alloc ( len ) ; for ( regno = ( reg_inc_p ? 0 : 31 ) ; regno != ( reg_inc_p ? 32 : - 1 ) ; regno += ( reg_inc_p ? 1 : - 1 ) ) if ( ( regmask & ( 1 << regno ) ) != 0 ) { int offset = ( offset_inc_p ? 4 : - 4 ) * n ++ ; RTVEC_ELT ( p , i ++ ) = gen_ldst ( load_p , regno , base_mem , offset ) ; } if ( ret_p ) RTVEC_ELT ( p , 0 ) = ret_rtx ; if ( base_update != 0 ) { rtx reg , offset ; if ( ! split_mem_address ( XEXP ( base_mem , 0 ) , & reg , & offset ) ) gcc_unreachable ( ) ; RTVEC_ELT ( p , b ) = gen_rtx_SET ( reg , plus_constant ( Pmode , reg , base_update ) ) ; } return gen_rtx_PARALLEL ( VOIDmode , p ) ; } </s>

A general routine for creating the body RTL pattern of ldwm/stwm/push.n/pop.n insns . LOAD_P : true/false for load/store direction . REG_INC_P : whether registers are incrementing/decrementing in the * RTL vector * ( not necessarily the order defined in the ISA specification ) . OFFSET_INC_P : Same as REG_INC_P , but for the memory offset order . BASE_MEM : starting MEM . BASE_UPDATE : amount to update base register ; zero means no writeback . REGMASK : register mask to load/store . RET_P : true if to tag a ( return ) element at the end . Note that this routine does not do any checking . It 's the job of the caller to do the right thing , and the insn patterns to do the safe-guarding .


<s> static bool th_mempair_check_consecutive_mems ( machine_mode mode , rtx * mem1 , rtx * mem2 , bool * reversed ) { rtx base1 , base2 , offset1 , offset2 ; extract_base_offset_in_addr ( * mem1 , & base1 , & offset1 ) ; extract_base_offset_in_addr ( * mem2 , & base2 , & offset2 ) ; if ( ! base1 || ! base2 ) return false ; if ( rtx_equal_p ( base1 , base2 ) ) { auto size = GET_MODE_SIZE ( mode ) ; if ( known_eq ( UINTVAL ( offset1 ) + size , UINTVAL ( offset2 ) ) ) { * reversed = false ; return true ; } if ( known_eq ( UINTVAL ( offset2 ) + size , UINTVAL ( offset1 ) ) ) { * reversed = true ; return true ; } return false ; } return false ; } </s>

Analyse if a pair of loads/stores MEM1 and MEM2 with given MODE are consecutive so they can be merged into a mempair instruction . RESERVED will be set to true , if a reversal of the accesses is required ( false otherwise ) . Returns true if the accesses can be merged ( even if reversing is necessary ) and false if not .


<s> MachineBasicBlock * SITargetLowering :: EmitInstrWithCustomInserter ( MachineInstr & MI , MachineBasicBlock * BB ) const { switch ( MI . getOpcode ( ) ) { case AMDGPU :: SI_INIT_M0 : { const SIInstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; BuildMI ( * BB , MI . getIterator ( ) , MI . getDebugLoc ( ) , TII -> get ( AMDGPU :: S_MOV_B32 ) , AMDGPU :: M0 ) . addOperand ( MI . getOperand ( 0 ) ) ; MI . eraseFromParent ( ) ; break ; } case AMDGPU :: BRANCH : return BB ; case AMDGPU :: GET_GROUPSTATICSIZE : { const SIInstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; MachineFunction * MF = BB -> getParent ( ) ; SIMachineFunctionInfo * MFI = MF -> getInfo < SIMachineFunctionInfo > ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; BuildMI ( * BB , MI , DL , TII -> get ( AMDGPU :: S_MOVK_I32 ) ) . addOperand ( MI . getOperand ( 0 ) ) . addImm ( MFI -> LDSSize ) ; MI . eraseFromParent ( ) ; return BB ; } case AMDGPU :: SI_KILL : return splitKillBlock ( MI , BB ) ; default : return AMDGPUTargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; } return BB ; } </s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static rtx rs6000_savres_routine_sym ( rs6000_stack_t * info , int sel ) { int regno = ( ( sel & SAVRES_REG ) == SAVRES_GPR ? info -> first_gp_reg_save : ( sel & SAVRES_REG ) == SAVRES_FPR ? info -> first_fp_reg_save - 32 : ( sel & SAVRES_REG ) == SAVRES_VR ? info -> first_altivec_reg_save - FIRST_ALTIVEC_REGNO : - 1 ) ; rtx sym ; int select = sel ; gcc_assert ( FIRST_SAVRES_REGISTER <= regno && regno <= LAST_SAVRES_REGISTER && select >= 0 && select <= 12 ) ; sym = savres_routine_syms [ regno - FIRST_SAVRES_REGISTER ] [ select ] ; if ( sym == NULL ) { char * name ; name = rs6000_savres_routine_name ( regno , sel ) ; sym = savres_routine_syms [ regno - FIRST_SAVRES_REGISTER ] [ select ] = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( name ) ) ; SYMBOL_REF_FLAGS ( sym ) |= SYMBOL_FLAG_FUNCTION ; } return sym ; } </s>

Return an RTL SYMBOL_REF for an out-of-line register save/restore routine . We are saving/restoring GPRs if GPR is true .


<s> int avr_jump_mode ( rtx x , rtx_insn * insn ) { int dest_addr = INSN_ADDRESSES ( INSN_UID ( GET_CODE ( x ) == LABEL_REF ? XEXP ( x , 0 ) : x ) ) ; int cur_addr = INSN_ADDRESSES ( INSN_UID ( insn ) ) ; int jump_distance = cur_addr - dest_addr ; if ( - 63 <= jump_distance && jump_distance <= 62 ) return 1 ; else if ( - 2046 <= jump_distance && jump_distance <= 2045 ) return 2 ; else if ( AVR_HAVE_JMP_CALL ) return 3 ; return 2 ; } </s>

Choose mode for jump insn : 1 - relative jump in range -63 < = x < = 62 ; 2 - relative jump in range -2046 < = x < = 2045 ; 3 - absolute jump ( only for ATmega [ 16 ] 03 ) .


<s> bool MipsPassConfig :: addInstSelector ( ) { PM -> add ( createMipsISelDag ( getMipsTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void convert_int_to_float128 ( rtx * operands , enum rtx_code code ) { rtx dest = operands [ 0 ] ; rtx src = operands [ 1 ] ; rtx tmp = operands [ 2 ] ; rtx cvt ; rtvec cvt_vec ; rtx cvt_unspec ; rtvec move_vec ; rtx move_unspec ; rtx unsigned_flag ; if ( GET_CODE ( tmp ) == SCRATCH ) tmp = gen_reg_rtx ( V2DImode ) ; if ( MEM_P ( src ) ) src = rs6000_address_for_fpconvert ( src ) ; if ( GET_MODE ( src ) == SImode ) { unsigned_flag = ( code == UNSIGNED_FLOAT ) ? const1_rtx : const0_rtx ; move_vec = gen_rtvec ( 2 , src , unsigned_flag ) ; } else move_vec = gen_rtvec ( 1 , src ) ; move_unspec = gen_rtx_UNSPEC ( V2DImode , move_vec , UNSPEC_IEEE128_MOVE ) ; emit_insn ( gen_rtx_SET ( tmp , move_unspec ) ) ; cvt_vec = gen_rtvec ( 1 , tmp ) ; cvt_unspec = gen_rtx_UNSPEC ( DImode , cvt_vec , UNSPEC_IEEE128_CONVERT ) ; cvt = gen_rtx_fmt_e ( code , GET_MODE ( dest ) , cvt_unspec ) ; emit_insn ( gen_rtx_SET ( dest , cvt ) ) ; } </s>

Split a conversion from an integer type to __float128 into separate insns . OPERANDS points to the destination , source , and V2DI temporary register . CODE is either FLOAT or UNSIGNED_FLOAT .


<s>
bool
SIInstrInfo
::
isInlineConstant
(
const
MachineOperand
&
MO
,
uint8_t
OperandType
)
const
{
if
(
!
MO
.
isImm
(
)
||
OperandType
<
MCOI
::
OPERAND_FIRST_TARGET
)
return
false
;
int64_t
Imm
=
MO
.
getImm
(
)
;
switch
(
operandBitWidth
(
OperandType
)
)
{
case
32
:
{
int32_t
Trunc
=
static_cast
<
int32_t
>
(
Imm
)
;
return
Trunc
==
Imm
&&
AMDGPU
::
isInlinableLiteral32
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
case
64
:
{
return
AMDGPU
::
isInlinableLiteral64
(
MO
.
getImm
(
)
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
case
16
:
{
if
(
isInt
<
16
>
(
Imm
)
||
isUInt
<
16
>
(
Imm
)
)
{
int16_t
Trunc
=
static_cast
<
int16_t
>
(
Imm
)
;
return
AMDGPU
::
isInlinableLiteral16
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
return
false
;
}
default
:
llvm_unreachable
(
"invalid bitwidth"
)
;
}
}
</s>

returns true if the operand OpIdx in MI is a valid inline immediate .


<s> const MCExpr * PPCAIXAsmPrinter :: lowerConstant ( const Constant * CV ) { if ( const Function * F = dyn_cast < Function > ( CV ) ) { MCSectionXCOFF * Csect = cast < MCSectionXCOFF > ( F -> isDeclaration ( ) ? getObjFileLowering ( ) . getSectionForExternalReference ( F , TM ) : getObjFileLowering ( ) . getSectionForFunctionDescriptor ( F , TM ) ) ; return MCSymbolRefExpr :: create ( Csect -> getQualNameSymbol ( ) , OutContext ) ; } return PPCAsmPrinter :: lowerConstant ( CV ) ; } </s>

Lower the specified LLVM Constant to an MCExpr .


<s> bool F2003fMCAsmInfo :: isValidUnquotedName ( StringRef Name ) const { if ( Name . empty ( ) ) return false ; if ( Name . size ( ) == 2 ) { if ( Name [ 0 ] == 'f' && Name [ 1 ] >= '0' && Name [ 1 ] <= '7' ) return false ; if ( Name . equals ( "xx" ) ) return false ; } if ( Name [ 0 ] == '\'' ) { return false ; } bool hasNonNumericChar = false ; for ( char C : Name ) { if ( ! hasNonNumericChar && ( C <= '0' || C >= '9' ) ) { hasNonNumericChar = true ; } if ( ! isAcceptableChar ( C ) ) return false ; } return hasNonNumericChar ; } </s>

Return true if the identifier Name does not need quotes to be syntactically correct .


<s> bool SIInstrInfo :: hasModifiers ( unsigned Opcode ) const { return AMDGPU :: getNamedOperandIdx ( Opcode , AMDGPU :: OpName :: src0_modifiers ) != - 1 ; } </s>

Return true if this instruction has any modifiers .

AMDGPU SI AMDGPU::getNamedOperandIdx AMDGPU::OpName 1


"CPUs older than z900 are not supported for -fsplit-stack"

Emit -fsplit-stack prologue , which goes before the regular function prologue .


<s> bool CJGFrameLowering :: hasFP ( const MachineFunction & MF ) const { return true ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
unsigned
getReg
(
)
const
{
assert
(
(
Kind
==
k_Register
)
&&
"Invalid access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s>
void
m68hc11_gen_rotate
(
enum
rtx_code
code
,
rtx
insn
,
rtx
operands
[
]
)
{
int
val
;
if
(
GET_CODE
(
operands
[
2
]
)
!=
CONST_INT
||
(
!
D_REG_P
(
operands
[
0
]
)
&&
!
DA_REG_P
(
operands
[
0
]
)
)
)
fatal_insn
(
"invalid rotate insn"
,
insn
)
;
val
=
INTVAL
(
operands
[
2
]
)
;
if
(
code
==
ROTATERT
)
val
=
GET_MODE_SIZE
(
GET_MODE
(
operands
[
0
]
)
)
*
BITS_PER_UNIT
val
;
if
(
GET_MODE
(
operands
[
0
]
)
!=
QImode
)
CC_STATUS_INIT
;
if
(
val
>=
5
&&
val
<=
11
)
{
if
(
TARGET_M6812
)
output_asm_insn
(
"exg\ta,b"
,
operands
)
;
else
{
output_asm_insn
(
"psha"
,
operands
)
;
output_asm_insn
(
"tba"
,
operands
)
;
output_asm_insn
(
"pulb"
,
operands
)
;
}
val
-=
8
;
}
else
if
(
val
>=
12
)
{
val
=
val
16
;
}
if
(
val
>
0
)
{
while
(
val
>=
0
)
{
if
(
GET_MODE
(
operands
[
0
]
)
!=
QImode
)
{
output_asm_insn
(
"asra"
,
operands
)
;
output_asm_insn
(
"rola"
,
operands
)
;
}
if
(
D_REG_P
(
operands
[
0
]
)
)
output_asm_insn
(
"rolb"
,
operands
)
;
if
(
GET_MODE
(
operands
[
0
]
)
!=
QImode
||
DA_REG_P
(
operands
[
0
]
)
)
output_asm_insn
(
"rola"
,
operands
)
;
}
}
else
{
while
(
++
val
<=
0
)
{
if
(
GET_MODE
(
operands
[
0
]
)
!=
QImode
)
output_asm_insn
(
"tap"
,
operands
)
;
if
(
D_REG_P
(
operands
[
0
]
)
)
output_asm_insn
(
"rorb"
,
operands
)
;
if
(
GET_MODE
(
operands
[
0
]
)
!=
QImode
||
DA_REG_P
(
operands
[
0
]
)
)
output_asm_insn
(
"rora"
,
operands
)
;
}
}
}
</s>

Generate the code for a ROTATE or ROTATERT on a QI or HI mode . The source and destination must be D or A and the shift must be a constant .


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const TargetInstrInfo & TII , DebugLoc dl , const ThumbRegisterInfo & MRI , int NumBytes , unsigned MIFlags = MachineInstr :: NoFlags ) { emitThumbRegPlusImmediate ( MBB , MBBI , dl , ARM :: SP , ARM :: SP , NumBytes , TII , MRI , MIFlags ) ; } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> static unsigned getReturnSaveOffset ( bool LP64 , bool isMacho ) { if ( isMacho ) return LP64 ? 16 : 8 ; return 4 ; } </s>

getReturnSaveOffset - Return the previous frame offset to save the return address .


<s> const ARMBaseRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static bool alpha_legitimate_address_p ( machine_mode mode , rtx x , bool strict ) { if ( mode == DImode && GET_CODE ( x ) == AND && CONST_INT_P ( XEXP ( x , 1 ) ) && INTVAL ( XEXP ( x , 1 ) ) == - 8 ) x = XEXP ( x , 0 ) ; if ( SUBREG_P ( x ) && ( GET_MODE_SIZE ( GET_MODE ( x ) ) < GET_MODE_SIZE ( GET_MODE ( SUBREG_REG ( x ) ) ) ) ) x = SUBREG_REG ( x ) ; if ( REG_P ( x ) && ( strict ? STRICT_REG_OK_FOR_BASE_P ( x ) : NONSTRICT_REG_OK_FOR_BASE_P ( x ) ) ) return true ; if ( CONSTANT_ADDRESS_P ( x ) ) return true ; if ( LINKAGE_SYMBOL_REF_P ( x ) ) return true ; if ( GET_CODE ( x ) == PLUS ) { rtx ofs = XEXP ( x , 1 ) ; x = XEXP ( x , 0 ) ; if ( SUBREG_P ( x ) && ( GET_MODE_SIZE ( GET_MODE ( x ) ) < GET_MODE_SIZE ( GET_MODE ( SUBREG_REG ( x ) ) ) ) ) x = SUBREG_REG ( x ) ; if ( REG_P ( x ) ) { if ( ! strict && NONSTRICT_REG_OK_FP_BASE_P ( x ) && CONST_INT_P ( ofs ) ) return true ; if ( ( strict ? STRICT_REG_OK_FOR_BASE_P ( x ) : NONSTRICT_REG_OK_FOR_BASE_P ( x ) ) && CONSTANT_ADDRESS_P ( ofs ) ) return true ; } } else if ( TARGET_EXPLICIT_RELOCS && GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD ) { if ( small_symbolic_operand ( x , Pmode ) ) return true ; if ( GET_CODE ( x ) == LO_SUM ) { rtx ofs = XEXP ( x , 1 ) ; x = XEXP ( x , 0 ) ; if ( SUBREG_P ( x ) && ( GET_MODE_SIZE ( GET_MODE ( x ) ) < GET_MODE_SIZE ( GET_MODE ( SUBREG_REG ( x ) ) ) ) ) x = SUBREG_REG ( x ) ; if ( ! ( REG_P ( x ) && ( strict ? STRICT_REG_OK_FOR_BASE_P ( x ) : NONSTRICT_REG_OK_FOR_BASE_P ( x ) ) ) ) return false ; if ( local_symbolic_operand ( ofs , Pmode ) || dtp32_symbolic_operand ( ofs , Pmode ) || tp32_symbolic_operand ( ofs , Pmode ) ) return true ; } } return false ; } </s>

legitimate_address_p recognizes an RTL expression that is a valid memory address for an instruction . The MODE argument is the machine mode for the MEM expression that wants to use this address . For Alpha , we have either a constant address or the sum of a register and a constant address , or just a register . For DImode , any of those forms can be surrounded with an AND that clear the low-order three bits ; this is an `` unaligned '' access .


<s> bool AArch64PromoteConstant :: runOnFunction ( Function & F ) { bool LocalChange = false ; SmallSet < Constant * , 8 > AlreadyChecked ; for ( auto & MBB : F ) { for ( auto & MI : MBB ) { for ( unsigned OpIdx = 0 , EndOpIdx = MI . getNumOperands ( ) ; OpIdx != EndOpIdx ; ++ OpIdx ) { Constant * Cst = dyn_cast < Constant > ( MI . getOperand ( OpIdx ) ) ; if ( Cst && ! isa < GlobalValue > ( Cst ) && ! isa < ConstantExpr > ( Cst ) && AlreadyChecked . insert ( Cst ) ) LocalChange |= promoteConstant ( Cst ) ; } } } return LocalChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s>
void
m32c_output_reg_pop
(
FILE
*
s
,
int
regno
)
{
if
(
regno
==
FLG_REGNO
)
fprintf
(
s
,
"\tpopc\tflg\n"
)
;
else
fprintf
(
s
,
"\tpop.%c\t%s\n"
,
" bwll"
[
reg_push_size
(
regno
)
]
,
reg_names
[
regno
]
)
;
}
</s>


<s> static bool v850_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { return GET_MODE_SIZE ( mode ) <= 4 || ( ( regno & 1 ) == 0 && regno != 0 ) ; } </s>


<s> bool SIInstrInfo :: shouldClusterMemOps ( MachineOperand & BaseOp1 , MachineOperand & BaseOp2 , unsigned NumLoads ) const { MachineInstr & FirstLdSt = * BaseOp1 . getParent ( ) ; MachineInstr & SecondLdSt = * BaseOp2 . getParent ( ) ; if ( ! memOpsHaveSameBasePtr ( FirstLdSt , BaseOp1 , SecondLdSt , BaseOp2 ) ) return false ; const MachineOperand * FirstDst = nullptr ; const MachineOperand * SecondDst = nullptr ; if ( ( isMUBUF ( FirstLdSt ) && isMUBUF ( SecondLdSt ) ) || ( isMTBUF ( FirstLdSt ) && isMTBUF ( SecondLdSt ) ) || ( isFLAT ( FirstLdSt ) && isFLAT ( SecondLdSt ) ) ) { const unsigned MaxGlobalLoadCluster = 6 ; if ( NumLoads > MaxGlobalLoadCluster ) return false ; FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: vdata ) ; if ( ! FirstDst ) FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: vdst ) ; SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: vdata ) ; if ( ! SecondDst ) SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: vdst ) ; } else if ( isSMRD ( FirstLdSt ) && isSMRD ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: sdst ) ; SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: sdst ) ; } else if ( isDS ( FirstLdSt ) && isDS ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: vdst ) ; SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: vdst ) ; } if ( ! FirstDst || ! SecondDst ) return false ; unsigned LoadClusterThreshold = 16 ; const MachineRegisterInfo & MRI = FirstLdSt . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * DstRC = MRI . getRegClass ( FirstDst -> getReg ( ) ) ; return ( NumLoads * ( RI . getRegSizeInBits ( * DstRC ) / 8 ) ) <= LoadClusterThreshold ; } </s>

Returns true if the two given memory operations should be scheduled adjacent .

AMDGPU SI 6 AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName 16 8


<s> bool X86TargetLowering :: reduceSelectOfFPConstantLoads ( EVT CmpOpVT ) const { bool IsFPSetCC = CmpOpVT . isFloatingPoint ( ) && CmpOpVT != MVT :: f128 ; return ! IsFPSetCC || ! Subtarget . isTarget64BitLP64 ( ) || ! Subtarget . hasAVX ( ) ; } </s>

Return true if it is profitable to convert a select of FP constants into a constant pool load whose address depends on the select condition .


<s> unsigned AArch64TargetLowering :: getVaListSizeInBits ( const DataLayout & DL , unsigned AS ) const { if ( Subtarget -> isTargetDarwin ( ) || Subtarget -> isTargetWindows ( ) ) return getPointerTy ( DL , AS ) . getSizeInBits ( ) ; return 3 * getPointerTy ( DL , AS ) . getSizeInBits ( ) + 2 * 32 ; } </s>

Returns the size of the platform 's va_list object .


<s>
bool
ARMCallLowering
::
lowerReturn
(
MachineIRBuilder
&
MIRBuilder
,
const
Value
*
Val
,
ArrayRef
<
unsigned
>
VRegs
)
const
{
assert
(
!
Val
==
VRegs
.
empty
(
)
&&
"Return value without a vreg"
)
;
auto
const
&
ST
=
MIRBuilder
.
getMF
(
)
.
getSubtarget
<
ARMSubtarget
>
(
)
;
unsigned
Opcode
=
ST
.
getReturnOpcode
(
)
;
auto
Ret
=
MIRBuilder
.
buildInstrNoInsert
(
Opcode
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
if
(
!
lowerReturnVal
(
MIRBuilder
,
Val
,
VRegs
,
Ret
)
)
return
false
;
MIRBuilder
.
insertInstr
(
Ret
)
;
return
true
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .

ARM
ARM
"Return value without a vreg"
ARM
ARMCC::AL


"Dangerous instruction in branch delay slot!"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool ix86_legitimize_reload_address ( rtx x , machine_mode , int opnum , int type , int ) { if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , 1 ) ) && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && REG_P ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ) { rtx base , index ; bool something_reloaded = false ; base = XEXP ( XEXP ( x , 0 ) , 1 ) ; if ( ! REG_OK_FOR_BASE_STRICT_P ( base ) ) { push_reload ( base , NULL_RTX , & XEXP ( XEXP ( x , 0 ) , 1 ) , NULL , BASE_REG_CLASS , GET_MODE ( x ) , VOIDmode , 0 , 0 , opnum , ( enum reload_type ) type ) ; something_reloaded = true ; } index = XEXP ( x , 1 ) ; if ( ! REG_OK_FOR_INDEX_STRICT_P ( index ) ) { push_reload ( index , NULL_RTX , & XEXP ( x , 1 ) , NULL , INDEX_REG_CLASS , GET_MODE ( x ) , VOIDmode , 0 , 0 , opnum , ( enum reload_type ) type ) ; something_reloaded = true ; } gcc_assert ( something_reloaded ) ; return true ; } return false ; } </s>

Our implementation of LEGITIMIZE_RELOAD_ADDRESS . Returns a value to replace the input X , or the original X if no replacement is called for . The output parameter * WIN is 1 if the calling macro should goto WIN , 0 if it should not .


<s> static bool loongarch_memmodel_needs_rel_acq_fence ( enum memmodel model ) { switch ( model ) { case MEMMODEL_ACQ_REL : case MEMMODEL_SEQ_CST : case MEMMODEL_SYNC_SEQ_CST : case MEMMODEL_RELEASE : case MEMMODEL_SYNC_RELEASE : case MEMMODEL_ACQUIRE : case MEMMODEL_CONSUME : case MEMMODEL_SYNC_ACQUIRE : return true ; case MEMMODEL_RELAXED : return false ; default : gcc_unreachable ( ) ; } } </s>

Return true if a FENCE should be emitted to before a memory access to implement the release portion of memory model MODEL .


<s> const TargetRegisterClass * X86RegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC ) const { if ( RC == & X86 :: GR8_NOREXRegClass ) return RC ; const TargetRegisterClass * Super = RC ; TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case X86 :: GR8RegClassID : case X86 :: GR16RegClassID : case X86 :: GR32RegClassID : case X86 :: GR64RegClassID : case X86 :: FR32RegClassID : case X86 :: FR64RegClassID : case X86 :: RFP32RegClassID : case X86 :: RFP64RegClassID : case X86 :: RFP80RegClassID : case X86 :: VR128RegClassID : case X86 :: VR256RegClassID : if ( Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; } Super = * I ++ ; } while ( Super ) ; return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .


<s> void mips_order_regs_for_local_alloc ( void ) { register int i ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) reg_alloc_order [ i ] = i ; if ( TARGET_MIPS16 ) { reg_alloc_order [ 0 ] = 24 ; reg_alloc_order [ 24 ] = 0 ; } } </s>

On the mips16 , we want to allocate $ 24 ( T_REG ) before other registers for instructions for which it is possible . This helps avoid shuffling registers around in order to set up for an xor , encouraging the compiler to use a cmp instead .


"PPC branch conditions have two components!"

"Cannot insert select on target without ISEL support"

"TrueReg and FalseReg must have overlapping register classes"

Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true , and FalseReg to DstReg when Cond is false .


<s> bool GBZ80AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { bool Error = AsmPrinter :: PrintAsmOperand ( MI , OpNum , AsmVariant , ExtraCode , O ) ; if ( Error ) printOperand ( MI , OpNum , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static unsigned int s390_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { return s390_class_max_nregs ( REGNO_REG_CLASS ( regno ) , mode ) ; } </s>

Implement TARGET_HARD_REGNO_NREGS . Because all registers in a class have the same size , this is equivalent to CLASS_MAX_NREGS .


<s> static int s390_adjust_priority ( rtx insn ATTRIBUTE_UNUSED , int priority ) { if ( ! INSN_P ( insn ) ) return priority ; if ( s390_tune != PROCESSOR_2084_Z990 && s390_tune != PROCESSOR_2094_Z9_109 ) return priority ; switch ( s390_safe_attr_type ( insn ) ) { case TYPE_FSTOREDF : case TYPE_FSTORESF : priority = priority << 3 ; break ; case TYPE_STORE : case TYPE_STM : priority = priority << 1 ; break ; default : break ; } return priority ; } </s>

A C statement ( sans semicolon ) to update the integer scheduling priority INSN_PRIORITY ( INSN ) . Reduce the priority to execute the INSN earlier , increase the priority to execute INSN later . Do not define this macro if you do not need to adjust the scheduling priorities of insns . A LA instruction maybe scheduled later , since the pipeline bypasses the calculated value .


<s> bool ix86_check_movabs ( rtx insn , int opnum ) { rtx set , mem ; set = PATTERN ( insn ) ; if ( GET_CODE ( set ) == PARALLEL ) set = XVECEXP ( set , 0 , 0 ) ; gcc_assert ( GET_CODE ( set ) == SET ) ; mem = XEXP ( set , opnum ) ; while ( GET_CODE ( mem ) == SUBREG ) mem = SUBREG_REG ( mem ) ; gcc_assert ( MEM_P ( mem ) ) ; return volatile_ok || ! MEM_VOLATILE_P ( mem ) ; } </s>

Return nonzero if OPNUM 's MEM should be matched in movabs * patterns .


<s> static rtx_insn * s390_emit_ccraw_jump ( HOST_WIDE_INT mask , enum rtx_code comparison , rtx label ) { rtx temp ; gcc_assert ( comparison == EQ || comparison == NE ) ; gcc_assert ( mask > 0 && mask < 15 ) ; temp = gen_rtx_fmt_ee ( comparison , VOIDmode , gen_rtx_REG ( CCRAWmode , CC_REGNUM ) , GEN_INT ( mask ) ) ; temp = gen_rtx_IF_THEN_ELSE ( VOIDmode , temp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; temp = gen_rtx_SET ( pc_rtx , temp ) ; return emit_jump_insn ( temp ) ; } </s>

Emit a conditional jump to LABEL for condition code mask MASK using comparsion operator COMPARISON . Return the emitted jump insn .


<s> static reg_class_t frv_secondary_reload ( bool in_p , rtx x , reg_class_t reload_class_i , machine_mode reload_mode , secondary_reload_info * sri ) { enum reg_class rclass = NO_REGS ; enum reg_class reload_class = ( enum reg_class ) reload_class_i ; if ( sri -> prev_sri && sri -> prev_sri -> t_icode != CODE_FOR_nothing ) { sri -> icode = sri -> prev_sri -> t_icode ; return NO_REGS ; } rclass = frv_secondary_reload_class ( reload_class , reload_mode , x ) ; if ( rclass != NO_REGS ) { enum insn_code icode = direct_optab_handler ( in_p ? reload_in_optab : reload_out_optab , reload_mode ) ; if ( icode == 0 ) { sri -> t_icode = CODE_FOR_nothing ; return rclass ; } } return default_secondary_reload ( in_p , x , reload_class , reload_mode , sri ) ; } </s>

This hook exists to catch the case where secondary_reload_class ( ) is called from init_reg_autoinc ( ) in regclass.c - before the reload optabs have been initialised .