<s> const TargetRegisterClass * MipsSETargetLowering :: getRepRegClassFor ( MVT VT ) const { if ( VT == MVT :: Untyped ) return Subtarget . hasDSP ( ) ? & Mips :: ACC64DSPRegClass : & Mips :: ACC64RegClass ; return TargetLowering :: getRepRegClassFor ( VT ) ; } </s>

Return the 'representative ' register class for the specified value type .


<s> const MipsTargetLowering * MipsTargetLowering :: create ( MipsTargetMachine & TM , const MipsSubtarget & STI ) { if ( STI . inMips16Mode ( ) ) return llvm :: createMips16TargetLowering ( TM , STI ) ; return llvm :: createMipsSETargetLowering ( TM , STI ) ; } </s>


<s> void avr_notice_update_cc ( rtx body ATTRIBUTE_UNUSED , rtx_insn * insn ) { rtx set ; enum attr_cc cc = get_attr_cc ( insn ) ; switch ( cc ) { default : break ; case CC_PLUS : case CC_LDI : { rtx * op = recog_data . operand ; int len_dummy , icc ; extract_constrain_insn_cached ( insn ) ; switch ( cc ) { default : gcc_unreachable ( ) ; case CC_PLUS : avr_out_plus ( insn , op , & len_dummy , & icc ) ; cc = ( enum attr_cc ) icc ; break ; case CC_LDI : cc = ( op [ 1 ] == CONST0_RTX ( GET_MODE ( op [ 0 ] ) ) && reg_overlap_mentioned_p ( op [ 0 ] , zero_reg_rtx ) ) ? CC_CLOBBER : CC_NONE ; break ; } break ; } } switch ( cc ) { default : gcc_unreachable ( ) ; break ; case CC_NONE : break ; case CC_SET_N : CC_STATUS_INIT ; break ; case CC_SET_ZN : set = single_set ( insn ) ; CC_STATUS_INIT ; if ( set ) { cc_status . flags |= CC_NO_OVERFLOW ; cc_status . value1 = SET_DEST ( set ) ; } break ; case CC_SET_VZN : CC_STATUS_INIT ; break ; case CC_SET_CZN : set = single_set ( insn ) ; CC_STATUS_INIT ; if ( set ) { cc_status . value1 = SET_DEST ( set ) ; cc_status . flags |= CC_OVERFLOW_UNUSABLE ; } break ; case CC_COMPARE : set = single_set ( insn ) ; CC_STATUS_INIT ; if ( set ) cc_status . value1 = SET_SRC ( set ) ; break ; case CC_CLOBBER : CC_STATUS_INIT ; break ; } } </s>


<s> int cr16_initial_elimination_offset ( int from , int to ) { cr16_compute_save_regs ( ) ; cr16_compute_frame ( ) ; if ( ( ( from ) == FRAME_POINTER_REGNUM ) && ( ( to ) == STACK_POINTER_REGNUM ) ) return ( ACCUMULATE_OUTGOING_ARGS ? crtl -> outgoing_args_size : 0 ) ; else if ( ( ( from ) == ARG_POINTER_REGNUM ) && ( ( to ) == FRAME_POINTER_REGNUM ) ) return ( current_frame_info . reg_size + current_frame_info . var_size ) ; else if ( ( ( from ) == ARG_POINTER_REGNUM ) && ( ( to ) == STACK_POINTER_REGNUM ) ) return ( current_frame_info . reg_size + current_frame_info . var_size + ( ACCUMULATE_OUTGOING_ARGS ? crtl -> outgoing_args_size : 0 ) ) ; else gcc_unreachable ( ) ; } </s>

Implements the macro INITIAL_ELIMINATION_OFFSET , return the OFFSET .


<s> MachineInstr * X86InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const { if ( NoFusing ) return NULL ; unsigned Alignment = 0 ; if ( LoadMI -> hasOneMemOperand ( ) ) Alignment = LoadMI -> memoperands_begin ( ) -> getAlignment ( ) ; if ( Alignment < 16 ) { switch ( MI -> getOpcode ( ) ) { default : break ; case X86 :: FsANDNPDrr : case X86 :: FsANDNPSrr : case X86 :: FsANDPDrr : case X86 :: FsANDPSrr : case X86 :: FsORPDrr : case X86 :: FsORPSrr : case X86 :: FsXORPDrr : case X86 :: FsXORPSrr : return NULL ; } } if ( Ops . size ( ) == 2 && Ops [ 0 ] == 0 && Ops [ 1 ] == 1 ) { unsigned NewOpc = 0 ; switch ( MI -> getOpcode ( ) ) { default : return NULL ; case X86 :: TEST8rr : NewOpc = X86 :: CMP8ri ; break ; case X86 :: TEST16rr : NewOpc = X86 :: CMP16ri ; break ; case X86 :: TEST32rr : NewOpc = X86 :: CMP32ri ; break ; case X86 :: TEST64rr : NewOpc = X86 :: CMP64ri32 ; break ; } MI -> setDesc ( get ( NewOpc ) ) ; MI -> getOperand ( 1 ) . ChangeToImmediate ( 0 ) ; } else if ( Ops . size ( ) != 1 ) return NULL ; SmallVector < MachineOperand , 4 > MOs ; if ( LoadMI -> getOpcode ( ) == X86 :: V_SET0 || LoadMI -> getOpcode ( ) == X86 :: V_SETALLONES ) { unsigned PICBase = 0 ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ && ! TM . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ) return false ; MachineConstantPool & MCP = * MF . getConstantPool ( ) ; const VectorType * Ty = VectorType :: get ( Type :: Int32Ty , 4 ) ; Constant * C = LoadMI -> getOpcode ( ) == X86 :: V_SET0 ? ConstantVector :: getNullValue ( Ty ) : ConstantVector :: getAllOnesValue ( Ty ) ; unsigned CPI = MCP . getConstantPoolIndex ( C , 16 ) ; MOs . push_back ( MachineOperand :: CreateReg ( PICBase , false ) ) ; MOs . push_back ( MachineOperand :: CreateImm ( 1 ) ) ; MOs . push_back ( MachineOperand :: CreateReg ( 0 , false ) ) ; MOs . push_back ( MachineOperand :: CreateCPI ( CPI , 0 ) ) ; } else { unsigned NumOps = LoadMI -> getDesc ( ) . getNumOperands ( ) ; for ( unsigned i = NumOps - 4 ; i != NumOps ; ++ i ) MOs . push_back ( LoadMI -> getOperand ( i ) ) ; } return foldMemoryOperandImpl ( MF , MI , Ops [ 0 ] , MOs ) ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> static save_entry * sh5_schedule_saves ( HARD_REG_SET * live_regs_mask , save_schedule * schedule , int offset_base ) { int align , i ; save_entry * entry = schedule -> entries ; int tmpx = 0 ; int offset ; if ( ! current_function_interrupt ) for ( i = FIRST_GENERAL_REG ; tmpx < MAX_TEMPS && i <= LAST_GENERAL_REG ; i ++ ) if ( call_really_used_regs [ i ] && ! fixed_regs [ i ] && i != PR_MEDIA_REG && ! FUNCTION_ARG_REGNO_P ( i ) && i != FIRST_RET_REG && ! ( cfun -> static_chain_decl != NULL && i == STATIC_CHAIN_REGNUM ) && ! ( crtl -> calls_eh_return && ( i == EH_RETURN_STACKADJ_REGNO || ( ( unsigned ) i >= EH_RETURN_DATA_REGNO ( 0 ) && ( unsigned ) i <= EH_RETURN_DATA_REGNO ( 3 ) ) ) ) ) schedule -> temps [ tmpx ++ ] = i ; entry -> reg = - 1 ; entry -> mode = VOIDmode ; entry -> offset = offset_base ; entry ++ ; offset = offset_base ; for ( align = 1 ; align >= 0 ; align -- ) { for ( i = FIRST_PSEUDO_REGISTER - 1 ; i >= 0 ; i -- ) if ( TEST_HARD_REG_BIT ( * live_regs_mask , i ) ) { machine_mode mode = REGISTER_NATURAL_MODE ( i ) ; int reg = i ; if ( current_function_interrupt ) { if ( TARGET_REGISTER_P ( i ) ) continue ; if ( GENERAL_REGISTER_P ( i ) ) mode = DImode ; } if ( mode == SFmode && ( i % 2 ) == 1 && ! TARGET_FPU_SINGLE && FP_REGISTER_P ( i ) && ( TEST_HARD_REG_BIT ( * live_regs_mask , ( i ^ 1 ) ) ) ) { mode = DFmode ; i -- ; reg -- ; } if ( ( GET_MODE_SIZE ( mode ) % ( STACK_BOUNDARY / BITS_PER_UNIT ) == 0 ) != align ) continue ; if ( current_function_interrupt && GENERAL_REGISTER_P ( i ) && tmpx < MAX_TEMPS ) schedule -> temps [ tmpx ++ ] = i ; offset -= GET_MODE_SIZE ( mode ) ; entry -> reg = i ; entry -> mode = mode ; entry -> offset = offset ; entry ++ ; } if ( align && current_function_interrupt ) for ( i = LAST_TARGET_REG ; i >= FIRST_TARGET_REG ; i -- ) if ( TEST_HARD_REG_BIT ( * live_regs_mask , i ) ) { offset -= GET_MODE_SIZE ( DImode ) ; entry -> reg = i ; entry -> mode = DImode ; entry -> offset = offset ; entry ++ ; } } entry -> reg = - 1 ; entry -> mode = VOIDmode ; entry -> offset = offset ; schedule -> temps [ tmpx ] = - 1 ; return entry - 1 ; } </s>

Fill in SCHEDULE according to LIVE_REGS_MASK . If RESTORE is nonzero , use reverse order . Returns the last entry written to ( not counting the delimiter ) . OFFSET_BASE is a number to be added to all offset entries .


<s> static bool xstormy16_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { const HOST_WIDE_INT size = int_size_in_bytes ( type ) ; return ( size == - 1 || size > UNITS_PER_WORD * NUM_ARGUMENT_REGISTERS ) ; } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


"Opcode has no flag setting equivalent!"

Return the opcode that set flags when possible .


<s> ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const override { const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) return createR600MachineScheduler ( C ) ; return nullptr ; } </s>

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level .


<s> bool enablePostRAScheduler ( ) const { return DoILP ; } </s>

True if the subtarget should run a scheduler after register allocation .


Generate external symbol indirection stubs ( PIC and non-PIC ) .


"data-model=far not valid for cr16c architecture"

"invalid data model option %<-mdata-model=%s%>"


<s>
BitVector
ARMBaseRegisterInfo
::
getReservedRegs
(
const
MachineFunction
&
MF
)
const
{
const
ARMSubtarget
&
STI
=
MF
.
getSubtarget
<
ARMSubtarget
>
(
)
;
const
ARMFrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
BitVector
Reserved
(
getNumRegs
(
)
)
;
markSuperRegs
(
Reserved
,
ARM
::
SP
)
;
markSuperRegs
(
Reserved
,
ARM
::
PC
)
;
markSuperRegs
(
Reserved
,
ARM
::
FPSCR
)
;
markSuperRegs
(
Reserved
,
ARM
::
APSR_NZCV
)
;
if
(
TFI
->
hasFP
(
MF
)
)
markSuperRegs
(
Reserved
,
getFramePointerReg
(
STI
)
)
;
if
(
hasBasePointer
(
MF
)
)
markSuperRegs
(
Reserved
,
BasePtr
)
;
if
(
STI
.
isR9Reserved
(
)
)
markSuperRegs
(
Reserved
,
ARM
::
R9
)
;
if
(
!
STI
.
hasVFP3
(
)
||
STI
.
hasD16
(
)
)
{
static_assert
(
ARM
::
D31
==
ARM
::
D16
+
15
,
"Register list not consecutive!"
)
;
for
(
unsigned
R
=
0
;
R
<
16
;
++
R
)
markSuperRegs
(
Reserved
,
ARM
::
D16
+
R
)
;
}
const
TargetRegisterClass
*
RC
=
&
ARM
::
GPRPairRegClass
;
for
(
TargetRegisterClass
::
iterator
I
=
RC
->
begin
(
)
,
E
=
RC
->
end
(
)
;
I
!=
E
;
++
I
)
for
(
MCSubRegIterator
SI
(
*
I
,
this
)
;
SI
.
isValid
(
)
;
++
SI
)
if
(
Reserved
.
test
(
*
SI
)
)
markSuperRegs
(
Reserved
,
*
I
)
;
assert
(
checkAllSuperRegsMarked
(
Reserved
)
)
;
return
Reserved
;
}
</s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


"unknown parameter to option %<-mtune-ctrl%>: %s"

parse -mtune-ctrl= option . When DUMP is true , print the features that are explicitly set .


<s> Register XCoreRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const XCoreFrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? XCore :: R10 : XCore :: SP ; } </s>


<s> SparcSubtarget & SparcSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { UseSoftMulDiv = false ; IsV9 = false ; IsLeon = false ; V8DeprecatedInsts = false ; IsVIS = false ; IsVIS2 = false ; IsVIS3 = false ; HasHardQuad = false ; UsePopc = false ; UseSoftFloat = false ; HasNoFSMULD = false ; HasNoFMULS = false ; HasLeonCasa = false ; HasUmacSmac = false ; PerformSDIVReplace = false ; InsertNOPLoad = false ; FixAllFDIVSQRT = false ; DetectRoundChange = false ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? "v9" : "v8" ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( ! IsV9 ) UsePopc = false ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> int avr_simple_epilogue ( void ) { return ( ! frame_pointer_needed && get_frame_size ( ) == 0 && avr_regs_to_save ( NULL ) == 0 && ! interrupt_function_p ( current_function_decl ) && ! signal_function_p ( current_function_decl ) && ! avr_naked_function_p ( current_function_decl ) && ! MAIN_NAME_P ( DECL_NAME ( current_function_decl ) ) && ! TREE_THIS_VOLATILE ( current_function_decl ) ) ; } </s>

Return 1 if the function epilogue is just a single `` ret '' .


<s>
void
handle_arm_sve_h
(
)
{
if
(
function_table
)
{
error
(
"duplicate definition of %qs"
,
"arm_sve.h"
)
;
return
;
}
sve_switcher
sve
;
for
(
unsigned
int
type_i
=
0
;
type_i
<
NUM_VECTOR_TYPES
;
++
type_i
)
{
vector_type_index
type
=
vector_type_index
(
type_i
)
;
register_vector_type
(
type
)
;
if
(
type
!=
VECTOR_TYPE_svbool_t
)
for
(
unsigned
int
count
=
2
;
count
<=
MAX_TUPLE_SIZE
;
++
count
)
register_tuple_type
(
count
,
type
)
;
}
register_svpattern
(
)
;
register_svprfop
(
)
;
function_table
=
new
hash_table
<
registered_function_hasher
>
(
1023
)
;
function_builder
builder
;
for
(
unsigned
int
i
=
0
;
i
<
ARRAY_SIZE
(
function_groups
)
;
++
i
)
builder
.
register_function_group
(
function_groups
[
i
]
)
;
}
</s>

Implement # pragma GCC aarch64 `` arm_sve.h '' .


<s> SDValue MipsTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; unsigned Opc = N -> getOpcode ( ) ; switch ( Opc ) { default : break ; case ISD :: SDIVREM : case ISD :: UDIVREM : return performDivRemCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SELECT : return performSELECTCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: AND : return performANDCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: OR : return performORCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: ADD : return performADDCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips Mips ISD::SDIVREM ISD::UDIVREM ISD::SELECT ISD::AND ISD::OR ISD::ADD


<s> void VERegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const VEFrameLowering * TFI = getFrameLowering ( MF ) ; unsigned FrameReg ; int Offset ; Offset = TFI -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) ; Offset += MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ; replaceFI ( MF , II , MI , dl , FIOperandNum , Offset , FrameReg ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool RedundantInstrElimination :: processBlock ( MachineBasicBlock & B , const RegisterSet & ) { bool Changed = false ; for ( auto I = B . begin ( ) , E = B . end ( ) , NextI = I ; I != E ; ++ I ) { NextI = std :: next ( I ) ; MachineInstr * MI = & * I ; if ( MI -> getOpcode ( ) == TargetOpcode :: COPY ) continue ; if ( MI -> hasUnmodeledSideEffects ( ) || MI -> isInlineAsm ( ) ) continue ; unsigned NumD = MI -> getDesc ( ) . getNumDefs ( ) ; if ( NumD != 1 ) continue ; BitTracker :: RegisterRef RD = MI -> getOperand ( 0 ) ; if ( ! BT . has ( RD . Reg ) ) continue ; const BitTracker :: RegisterCell & DC = BT . lookup ( RD . Reg ) ; auto At = MI -> isPHI ( ) ? B . getFirstNonPHI ( ) : MachineBasicBlock :: iterator ( MI ) ; for ( auto & Op : MI -> uses ( ) ) { if ( ! Op . isReg ( ) ) continue ; BitTracker :: RegisterRef RS = Op ; if ( ! BT . has ( RS . Reg ) ) continue ; if ( ! HBS :: isTransparentCopy ( RD , RS , MRI ) ) continue ; unsigned BN , BW ; if ( ! HBS :: getSubregMask ( RS , BN , BW , MRI ) ) continue ; const BitTracker :: RegisterCell & SC = BT . lookup ( RS . Reg ) ; if ( ! usedBitsEqual ( RD , RS ) && ! HBS :: isEqual ( DC , 0 , SC , BN , BW ) ) continue ; const DebugLoc & DL = MI -> getDebugLoc ( ) ; const TargetRegisterClass * FRC = HBS :: getFinalVRegClass ( RD , MRI ) ; unsigned NewR = MRI . createVirtualRegister ( FRC ) ; BuildMI ( B , At , DL , HII . get ( TargetOpcode :: COPY ) , NewR ) . addReg ( RS . Reg , 0 , RS . Sub ) ; HBS :: replaceSubWithSub ( RD . Reg , RD . Sub , NewR , 0 , MRI ) ; BT . put ( BitTracker :: RegisterRef ( NewR ) , SC ) ; Changed = true ; break ; } } return Changed ; } </s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s>
bool
SITargetLowering
::
isLegalAddressingMode
(
const
DataLayout
&
DL
,
const
AddrMode
&
AM
,
Type
*
Ty
,
unsigned
AS
,
Instruction
*
I
)
const
{
if
(
AM
.
BaseGV
)
return
false
;
if
(
AS
==
AMDGPUASI
.
GLOBAL_ADDRESS
)
return
isLegalGlobalAddressingMode
(
AM
)
;
if
(
AS
==
AMDGPUASI
.
CONSTANT_ADDRESS
||
AS
==
AMDGPUASI
.
CONSTANT_ADDRESS_32BIT
)
{
if
(
AM
.
BaseOffs
%
4
!=
0
)
return
isLegalMUBUFAddressingMode
(
AM
)
;
if
(
Ty
->
isSized
(
)
&&
DL
.
getTypeStoreSize
(
Ty
)
<
4
)
return
isLegalGlobalAddressingMode
(
AM
)
;
if
(
Subtarget
->
getGeneration
(
)
==
SISubtarget
::
SOUTHERN_ISLANDS
)
{
if
(
!
isUInt
<
8
>
(
AM
.
BaseOffs
/
4
)
)
return
false
;
}
else
if
(
Subtarget
->
getGeneration
(
)
==
SISubtarget
::
SEA_ISLANDS
)
{
if
(
!
isUInt
<
32
>
(
AM
.
BaseOffs
/
4
)
)
return
false
;
}
else
if
(
Subtarget
->
getGeneration
(
)
>=
SISubtarget
::
VOLCANIC_ISLANDS
)
{
if
(
!
isUInt
<
20
>
(
AM
.
BaseOffs
)
)
return
false
;
}
else
llvm_unreachable
(
"unhandled generation"
)
;
if
(
AM
.
Scale
==
0
)
return
true
;
if
(
AM
.
Scale
==
1
&&
AM
.
HasBaseReg
)
return
true
;
return
false
;
}
else
if
(
AS
==
AMDGPUASI
.
PRIVATE_ADDRESS
)
{
return
isLegalMUBUFAddressingMode
(
AM
)
;
}
else
if
(
AS
==
AMDGPUASI
.
LOCAL_ADDRESS
||
AS
==
AMDGPUASI
.
REGION_ADDRESS
)
{
if
(
!
isUInt
<
16
>
(
AM
.
BaseOffs
)
)
return
false
;
if
(
AM
.
Scale
==
0
)
return
true
;
if
(
AM
.
Scale
==
1
&&
AM
.
HasBaseReg
)
return
true
;
return
false
;
}
else
if
(
AS
==
AMDGPUASI
.
FLAT_ADDRESS
||
AS
==
AMDGPUASI
.
UNKNOWN_ADDRESS_SPACE
)
{
return
isLegalFlatAddressingMode
(
AM
)
;
}
else
{
llvm_unreachable
(
"unhandled address space"
)
;
}
}
</s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> void mips_restore_gp_from_cprestore_slot ( rtx temp ) { gcc_assert ( TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed ) ; if ( ! cfun -> machine -> must_restore_gp_when_clobbered_p ) { emit_note ( NOTE_INSN_DELETED ) ; return ; } if ( TARGET_MIPS16 ) { mips_emit_move ( temp , mips_cprestore_slot ( temp , true ) ) ; mips_emit_move ( pic_offset_table_rtx , temp ) ; } else mips_emit_move ( pic_offset_table_rtx , mips_cprestore_slot ( temp , true ) ) ; if ( ! TARGET_EXPLICIT_RELOCS ) emit_insn ( gen_blockage ( ) ) ; } </s>

Restore $ gp from its save slot , using TEMP as a temporary base register if need be . This function is for o32 and o64 abicalls only . See mips_must_initialize_gp_p for details about how we manage the global pointer .


Schedule - Order nodes according to selected style , filling in the Sequence member .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return this -> TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> unsigned getNumFixupKinds ( ) const { return 2 ; } </s>

Get the number of target specific fixup kinds .


<s> void mips_declare_object_name ( FILE * stream , const char * name , tree decl ATTRIBUTE_UNUSED ) { ASM_OUTPUT_TYPE_DIRECTIVE ( stream , name , "object" ) ; size_directive_output = 0 ; if ( ! flag_inhibit_size_directive && DECL_SIZE ( decl ) ) { HOST_WIDE_INT size ; size_directive_output = 1 ; size = int_size_in_bytes ( TREE_TYPE ( decl ) ) ; ASM_OUTPUT_SIZE_DIRECTIVE ( stream , name , size ) ; } mips_declare_object ( stream , name , "" , ":\n" ) ; } </s>

Implement ASM_DECLARE_OBJECT_NAME . This is like most of the standard ELF definitions except that it uses mips_declare_object ( ) to emit the label .


<s> unsigned MipsInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { default : return MI . getDesc ( ) . getSize ( ) ; case TargetOpcode :: INLINEASM : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } case Mips :: CONSTPOOL_ENTRY : return MI . getOperand ( 2 ) . getImm ( ) ; } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> static unsigned getNumInterleavedAccesses ( VectorType * VecTy , const DataLayout & DL ) { return ( DL . getTypeSizeInBits ( VecTy ) + 127 ) / 128 ; } </s>

Returns the number of interleaved accesses that will be generated when lowering accesses of the given type .


<s> X86Subtarget :: X86Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const X86TargetMachine & TM , unsigned StackAlignOverride ) : X86GenSubtargetInfo ( TT , CPU , FS ) , X86ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TM ( TM ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , TSInfo ( ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( * this , getStackAlignment ( ) ) { if ( ! isPositionIndependent ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( is64Bit ( ) ) setPICStyle ( PICStyles :: RIPRel ) ; else if ( isTargetCOFF ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( isTargetDarwin ( ) ) setPICStyle ( PICStyles :: StubPIC ) ; else if ( isTargetELF ( ) ) setPICStyle ( PICStyles :: GOT ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> void PPCAIXAsmPrinter :: emitFunctionBodyEnd ( ) { if ( ! TM . getXCOFFTracebackTable ( ) ) return ; emitTracebackTable ( ) ; if ( ! TargetLoweringObjectFileXCOFF :: ShouldEmitEHBlock ( MF ) && ( getNumberOfVRSaved ( ) > 0 ) ) { OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getCompactUnwindSection ( ) ) ; MCSymbol * EHInfoLabel = TargetLoweringObjectFileXCOFF :: getEHInfoTableSymbol ( MF ) ; OutStreamer -> emitLabel ( EHInfoLabel ) ; OutStreamer -> emitInt32 ( 0 ) ; const DataLayout & DL = MMI -> getModule ( ) -> getDataLayout ( ) ; const unsigned PointerSize = DL . getPointerSize ( ) ; OutStreamer -> emitValueToAlignment ( PointerSize ) ; OutStreamer -> emitIntValue ( 0 , PointerSize ) ; OutStreamer -> emitIntValue ( 0 , PointerSize ) ; OutStreamer -> SwitchSection ( MF -> getSection ( ) ) ; } } </s>

Targets can override this to emit stuff after the last basic block in the function .


<s> void X86PassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( new X86ExecutionDomainFix ( ) ) ; addPass ( createBreakFalseDeps ( ) ) ; } addPass ( createX86IndirectBranchTrackingPass ( ) ) ; if ( UseVZeroUpper ) addPass ( createX86IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86FixupBWInsts ( ) ) ; addPass ( createX86PadShortFunctions ( ) ) ; addPass ( createX86FixupLEAs ( ) ) ; addPass ( createX86EvexToVexInsts ( ) ) ; } addPass ( createX86DiscriminateMemOpsPass ( ) ) ; addPass ( createX86InsertPrefetchPass ( ) ) ; addPass ( createX86InsertX87waitPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> rtx rs6000_address_for_altivec ( rtx x ) { gcc_assert ( MEM_P ( x ) ) ; if ( ! altivec_indexed_or_indirect_operand ( x , GET_MODE ( x ) ) ) { rtx addr = XEXP ( x , 0 ) ; int strict_p = ( reload_in_progress || reload_completed ) ; if ( ! legitimate_indexed_address_p ( addr , strict_p ) && ! legitimate_indirect_address_p ( addr , strict_p ) ) addr = copy_to_mode_reg ( Pmode , addr ) ; addr = gen_rtx_AND ( Pmode , addr , GEN_INT ( - 16 ) ) ; x = change_address ( x , GET_MODE ( x ) , addr ) ; } return x ; } </s>

Given a memory reference , if it is not in the form for altivec memory reference instructions ( i.e . reg or reg+reg addressing with AND of -16 ) , convert to the altivec format .


<s> const F2003fSubtarget * getSubtargetImpl ( const Function & F ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool isMem ( ) const override { return isMemImm ( ) || isMemRegImm ( ) || isMemRegReg ( ) ; } </s>


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Hexagon Expand Condsets"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool X86TargetLowering :: isBinOp ( unsigned Opcode ) const { switch ( Opcode ) { case X86ISD :: ANDNP : case X86ISD :: PCMPGT : case X86ISD :: FMAX : case X86ISD :: FMIN : case X86ISD :: FANDN : return true ; } return TargetLoweringBase :: isBinOp ( Opcode ) ; } </s>

Add x86-specific opcodes to the default list .


<s> static rtx alphaev4_next_group ( rtx insn , int * pin_use , int * plen ) { int len , in_use ; len = in_use = 0 ; if ( ! INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == CLOBBER || GET_CODE ( PATTERN ( insn ) ) == USE ) goto next_and_done ; while ( 1 ) { enum alphaev4_pipe pipe ; pipe = alphaev4_insn_pipe ( insn ) ; switch ( pipe ) { case EV4_STOP : if ( in_use ) goto done ; if ( recog_memoized ( insn ) < 0 ) len = - 1 ; else len = get_attr_length ( insn ) ; goto next_and_done ; case EV4_IBX : if ( in_use & EV4_IB0 ) { if ( in_use & EV4_IB1 ) goto done ; in_use |= EV4_IB1 ; } else in_use |= EV4_IB0 | EV4_IBX ; break ; case EV4_IB0 : if ( in_use & EV4_IB0 ) { if ( ! ( in_use & EV4_IBX ) || ( in_use & EV4_IB1 ) ) goto done ; in_use |= EV4_IB1 ; } in_use |= EV4_IB0 ; break ; case EV4_IB1 : if ( in_use & EV4_IB1 ) goto done ; in_use |= EV4_IB1 ; break ; default : gcc_unreachable ( ) ; } len += 4 ; if ( GET_CODE ( insn ) == JUMP_INSN ) goto next_and_done ; next : insn = next_nonnote_insn ( insn ) ; if ( ! insn || ! INSN_P ( insn ) ) goto done ; if ( GET_MODE ( insn ) == TImode ) goto done ; if ( GET_CODE ( insn ) == CLOBBER || GET_CODE ( insn ) == USE ) goto next ; } next_and_done : insn = next_nonnote_insn ( insn ) ; done : * plen = len ; * pin_use = in_use ; return insn ; } </s>

IN_USE is a mask of the slots currently filled within the insn group . The mask bits come from alphaev4_pipe above . If EV4_IBX is set , then the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1 . LEN is , of course , the length of the group in bytes .


<s> initialize_trampoline ( TRAMP , FNADDR , CXT ) { { ARG_POINTER_REGNUM , STACK_POINTER_REGNUM } , \ { ARG_POINTER_REGNUM , FRAME_POINTER_REGNUM } , \ { FRAME_POINTER_REGNUM , STACK_POINTER_REGNUM } } </s>

Emit RTL insns to initialize the variable parts of a trampoline at TRAMP . FNADDR is an RTX for the address of the function 's pure code . CXT is an RTX for the static chain value for the function .


<s> static void push_csky_minipool_barrier ( rtx_insn * insn , HOST_WIDE_INT address ) { Mfix * fix = ( Mfix * ) obstack_alloc ( & minipool_obstack , sizeof ( * fix ) ) ; fix -> insn = insn ; fix -> address = address ; fix -> next = NULL ; if ( minipool_fix_head != NULL ) minipool_fix_tail -> next = fix ; else minipool_fix_head = fix ; minipool_fix_tail = fix ; } </s>

Record that there is a natural barrier in the insn stream at ADDRESS .


<s> SDValue X86TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: EXTRACT_VECTOR_ELT : return PerformEXTRACT_VECTOR_ELTCombine ( N , DAG , * this ) ; case ISD :: VSELECT : case ISD :: SELECT : return PerformSELECTCombine ( N , DAG , Subtarget ) ; case X86ISD :: CMOV : return PerformCMOVCombine ( N , DAG , DCI ) ; case ISD :: ADD : return PerformAddCombine ( N , DAG , Subtarget ) ; case ISD :: SUB : return PerformSubCombine ( N , DAG , Subtarget ) ; case X86ISD :: ADC : return PerformADCCombine ( N , DAG , DCI ) ; case ISD :: MUL : return PerformMulCombine ( N , DAG , DCI ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DAG , Subtarget ) ; case ISD :: AND : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: OR : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: XOR : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: LOAD : return PerformLOADCombine ( N , DAG , Subtarget ) ; case ISD :: STORE : return PerformSTORECombine ( N , DAG , Subtarget ) ; case ISD :: SINT_TO_FP : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case ISD :: FADD : return PerformFADDCombine ( N , DAG , Subtarget ) ; case ISD :: FSUB : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case X86ISD :: FXOR : case X86ISD :: FOR : return PerformFORCombine ( N , DAG ) ; case X86ISD :: FAND : return PerformFANDCombine ( N , DAG ) ; case X86ISD :: BT : return PerformBTCombine ( N , DAG , DCI ) ; case X86ISD :: VZEXT_MOVL : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case ISD :: ZERO_EXTEND : return PerformZExtCombine ( N , DAG ) ; case X86ISD :: SETCC : return PerformSETCCCombine ( N , DAG ) ; case X86ISD :: SHUFPS : case X86ISD :: SHUFPD : case X86ISD :: PALIGN : case X86ISD :: PUNPCKH : case X86ISD :: UNPCKHP : case X86ISD :: PUNPCKL : case X86ISD :: UNPCKLP : case X86ISD :: MOVHLPS : case X86ISD :: MOVLHPS : case X86ISD :: PSHUFD : case X86ISD :: PSHUFHW : case X86ISD :: PSHUFLW : case X86ISD :: MOVSS : case X86ISD :: MOVSD : case X86ISD :: VPERMILP : case X86ISD :: VPERM2X128 : case ISD :: VECTOR_SHUFFLE : return PerformShuffleCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


"Unexpected instruction type for reassociation"

"Must have dead EFLAGS operand in reassociable instruction"

"Unexpected operand in reassociable instruction"

This is an architecture-specific helper function of reassociateOps .


<s> void DataFlowGraph :: reset ( ) { Memory . clear ( ) ; Func = NodeAddr < FuncNode * > ( ) ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s> bool SIPreEmitPeephole :: runOnMachineFunction ( MachineFunction & MF ) { const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { MachineBasicBlock :: iterator MBBE = MBB . getFirstTerminator ( ) ; if ( MBBE != MBB . end ( ) ) { MachineInstr & MI = * MBBE ; switch ( MI . getOpcode ( ) ) { case AMDGPU :: S_CBRANCH_VCCZ : case AMDGPU :: S_CBRANCH_VCCNZ : Changed |= optimizeVccBranch ( MI ) ; continue ; default : break ; } } if ( ! ST . hasVGPRIndexMode ( ) ) continue ; MachineInstr * SetGPRMI = nullptr ; const unsigned Threshold = 20 ; unsigned Count = 0 ; for ( MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; MBBI != MBBE ; ) { MachineInstr & MI = * MBBI ; ++ MBBI ; if ( Count == Threshold ) SetGPRMI = nullptr ; else ++ Count ; if ( MI . getOpcode ( ) != AMDGPU :: S_SET_GPR_IDX_ON ) continue ; Count = 0 ; if ( ! SetGPRMI ) { SetGPRMI = & MI ; continue ; } if ( optimizeSetGPR ( * SetGPRMI , MI ) ) Changed = true ; else SetGPRMI = & MI ; } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> BitVector HexagonRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( HEXAGON_RESERVED_REG_1 ) ; Reserved . set ( HEXAGON_RESERVED_REG_2 ) ; Reserved . set ( Hexagon :: R29 ) ; Reserved . set ( Hexagon :: R30 ) ; Reserved . set ( Hexagon :: R31 ) ; Reserved . set ( Hexagon :: PC ) ; Reserved . set ( Hexagon :: GP ) ; Reserved . set ( Hexagon :: D14 ) ; Reserved . set ( Hexagon :: D15 ) ; Reserved . set ( Hexagon :: LC0 ) ; Reserved . set ( Hexagon :: LC1 ) ; Reserved . set ( Hexagon :: SA0 ) ; Reserved . set ( Hexagon :: SA1 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> enum reg_class class_likely_spilled_p ( int c ) { return ( c != ALL_REGS && c != ADDW_REGS ) ; } </s>

Return value is nonzero if pseudos that have been assigned to registers of class CLASS would likely be spilled because registers of CLASS are needed for spill registers .


<s> bool SIInstrInfo :: isTriviallyReMaterializable ( const MachineInstr * MI , AliasAnalysis * AA ) const { switch ( MI -> getOpcode ( ) ) { default : return AMDGPUInstrInfo :: isTriviallyReMaterializable ( MI , AA ) ; case AMDGPU :: S_MOV_B32 : case AMDGPU :: S_MOV_B64 : case AMDGPU :: V_MOV_B32_e32 : return MI -> getOperand ( 1 ) . isImm ( ) ; } } </s>

Return true if the instruction is trivially rematerializable , meaning it has no side effects and requires no operands that are n't always available .


<s> static void mmix_emit_sp_add ( HOST_WIDE_INT offset ) { rtx insn ; if ( offset < 0 ) { if ( offset > - 255 ) insn = emit_insn ( gen_adddi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( offset ) ) ) ; else { rtx tmpr = gen_rtx_REG ( DImode , 255 ) ; RTX_FRAME_RELATED_P ( emit_move_insn ( tmpr , GEN_INT ( offset ) ) ) = 1 ; insn = emit_insn ( gen_adddi3 ( stack_pointer_rtx , stack_pointer_rtx , tmpr ) ) ; } RTX_FRAME_RELATED_P ( insn ) = 1 ; } else { if ( insn_const_int_ok_for_constraint ( offset , CONSTRAINT_L ) ) emit_insn ( gen_adddi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( offset ) ) ) ; else { rtx tmpr = gen_rtx_REG ( DImode , 255 ) ; emit_move_insn ( tmpr , GEN_INT ( offset ) ) ; insn = emit_insn ( gen_adddi3 ( stack_pointer_rtx , stack_pointer_rtx , tmpr ) ) ; } } } </s>


<s>
void
MSP430FrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
MSP430MachineFunctionInfo
*
MSP430FI
=
MF
.
getInfo
<
MSP430MachineFunctionInfo
>
(
)
;
const
MSP430InstrInfo
&
TII
=
*
static_cast
<
const
MSP430InstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
DL
=
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
uint64_t
StackSize
=
MFI
.
getStackSize
(
)
;
uint64_t
NumBytes
=
0
;
if
(
hasFP
(
MF
)
)
{
uint64_t
FrameSize
=
StackSize
2
;
NumBytes
=
FrameSize
MSP430FI
->
getCalleeSavedFrameSize
(
)
;
MFI
.
setOffsetAdjustment
(
NumBytes
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
TII
.
get
(
MSP430
::
PUSH16r
)
)
.
addReg
(
MSP430
::
R4
,
RegState
::
Kill
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
TII
.
get
(
MSP430
::
MOV16rr
)
,
MSP430
::
R4
)
.
addReg
(
MSP430
::
SP
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
for
(
MachineBasicBlock
&
MBBJ
:
llvm
::
drop_begin
(
MF
)
)
MBBJ
.
addLiveIn
(
MSP430
::
R4
)
;
}
else
NumBytes
=
StackSize
MSP430FI
->
getCalleeSavedFrameSize
(
)
;
while
(
MBBI
!=
MBB
.
end
(
)
&&
MBBI
->
getFlag
(
MachineInstr
::
FrameSetup
)
)
++
MBBI
;
if
(
MBBI
!=
MBB
.
end
(
)
)
DL
=
MBBI
->
getDebugLoc
(
)
;
if
(
NumBytes
)
{
if
(
NumBytes
)
{
MachineInstr
*
MI
=
BuildMI
(
MBB
,
MBBI
,
DL
,
TII
.
get
(
MSP430
::
SUB16ri
)
,
MSP430
::
SP
)
.
addReg
(
MSP430
::
SP
)
.
addImm
(
NumBytes
)
;
MI
->
getOperand
(
3
)
.
setIsDead
(
)
;
}
}
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> EVT X86TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & Context , EVT VT ) const { if ( ! VT . isVector ( ) ) return Subtarget . hasAVX512 ( ) ? MVT :: i1 : MVT :: i8 ; if ( VT . isSimple ( ) ) { MVT VVT = VT . getSimpleVT ( ) ; const unsigned NumElts = VVT . getVectorNumElements ( ) ; MVT EltVT = VVT . getVectorElementType ( ) ; if ( VVT . is512BitVector ( ) ) { if ( Subtarget . hasAVX512 ( ) ) if ( EltVT == MVT :: i32 || EltVT == MVT :: i64 || EltVT == MVT :: f32 || EltVT == MVT :: f64 ) switch ( NumElts ) { case 8 : return MVT :: v8i1 ; case 16 : return MVT :: v16i1 ; } if ( Subtarget . hasBWI ( ) ) if ( EltVT == MVT :: i8 || EltVT == MVT :: i16 ) switch ( NumElts ) { case 32 : return MVT :: v32i1 ; case 64 : return MVT :: v64i1 ; } } if ( Subtarget . hasBWI ( ) && Subtarget . hasVLX ( ) ) return MVT :: getVectorVT ( MVT :: i1 , NumElts ) ; if ( ! isTypeLegal ( VT ) && getTypeAction ( Context , VT ) == TypePromoteInteger ) { EVT LegalVT = getTypeToTransformTo ( Context , VT ) ; EltVT = LegalVT . getVectorElementType ( ) . getSimpleVT ( ) ; } if ( Subtarget . hasVLX ( ) && EltVT . getSizeInBits ( ) >= 32 ) switch ( NumElts ) { case 2 : return MVT :: v2i1 ; case 4 : return MVT :: v4i1 ; case 8 : return MVT :: v8i1 ; } } return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> static void vax_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; * cum += ( mode != BLKmode ? ( GET_MODE_SIZE ( mode ) + 3 ) & ~ 3 : ( int_size_in_bytes ( type ) + 3 ) & ~ 3 ) ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> WebAssemblySubtarget :: WebAssemblySubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : WebAssemblyGenSubtargetInfo ( TT , CPU , CPU , FS ) , TargetTriple ( TT ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) { } </s>

This constructor initializes the data members to match that of the specified triple .

WebAssembly WebAssembly WebAssembly WebAssembly


<s> unsigned char X86Subtarget :: classifyGlobalReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return X86II :: MO_NO_FLAG ; if ( GV ) { if ( Optional < ConstantRange > CR = GV -> getAbsoluteSymbolRange ( ) ) { if ( CR -> getUnsignedMax ( ) . ult ( 128 ) ) return X86II :: MO_ABS8 ; else return X86II :: MO_NO_FLAG ; } } if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return classifyLocalReference ( GV ) ; if ( isTargetCOFF ( ) ) return X86II :: MO_DLLIMPORT ; if ( is64Bit ( ) ) return X86II :: MO_GOTPCREL ; if ( isTargetDarwin ( ) ) { if ( ! isPositionIndependent ( ) ) return X86II :: MO_DARWIN_NONLAZY ; return X86II :: MO_DARWIN_NONLAZY_PIC_BASE ; } return X86II :: MO_GOT ; } </s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


"SystemZ does do not have assembler relaxation"

Relax the instruction in the given fragment to the next wider instruction .


<s>
SDValue
MipsSETargetLowering
::
PerformDAGCombine
(
SDNode
*
N
,
DAGCombinerInfo
&
DCI
)
const
{
SelectionDAG
&
DAG
=
DCI
.
DAG
;
SDValue
Val
;
switch
(
N
->
getOpcode
(
)
)
{
case
ISD
::
ADDE
:
return
performADDECombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
case
ISD
::
AND
:
Val
=
performANDCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
break
;
case
ISD
::
OR
:
Val
=
performORCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
break
;
case
ISD
::
SUBE
:
return
performSUBECombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
case
ISD
::
MUL
:
return
performMULCombine
(
N
,
DAG
,
DCI
,
this
)
;
case
ISD
::
SHL
:
Val
=
performSHLCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
break
;
case
ISD
::
SRA
:
return
performSRACombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
case
ISD
::
SRL
:
return
performSRLCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
case
ISD
::
VSELECT
:
return
performVSELECTCombine
(
N
,
DAG
)
;
case
ISD
::
XOR
:
Val
=
performXORCombine
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SETCC
:
Val
=
performSETCCCombine
(
N
,
DAG
)
;
break
;
}
if
(
Val
.
getNode
(
)
)
{
DEBUG
(
dbgs
(
)
<<
"\nMipsSE DAG Combine:\n"
;
N
->
printrWithDepth
(
dbgs
(
)
,
&
DAG
)
;
dbgs
(
)
<<
"\n=> \n"
;
Val
.
getNode
(
)
->
printrWithDepth
(
dbgs
(
)
,
&
DAG
)
;
dbgs
(
)
<<
"\n"
)
;
return
Val
;
}
return
MipsTargetLowering
::
PerformDAGCombine
(
N
,
DCI
)
;
}
</s>

Mips
Mips
ISD::ADDE
ISD::AND
ISD::OR
ISD::SUBE
ISD::MUL
ISD::SHL
ISD::SRA
ISD::SRL
ISD::VSELECT
ISD::XOR
ISD::SETCC
"\nMipsSE DAG Combine:\n"
"\n=> \n"
"\n"
Mips


<s> unsigned RISCVTargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { switch ( Op . getOpcode ( ) ) { default : break ; case RISCVISD :: SLLW : case RISCVISD :: SRAW : case RISCVISD :: SRLW : case RISCVISD :: DIVW : case RISCVISD :: DIVUW : case RISCVISD :: REMUW : case RISCVISD :: ROLW : case RISCVISD :: RORW : case RISCVISD :: GREVW : case RISCVISD :: GORCW : case RISCVISD :: FSLW : case RISCVISD :: FSRW : case RISCVISD :: SHFLW : case RISCVISD :: UNSHFLW : case RISCVISD :: BCOMPRESSW : case RISCVISD :: BDECOMPRESSW : return 33 ; case RISCVISD :: SHFL : case RISCVISD :: UNSHFL : { if ( Op . getValueType ( ) == MVT :: i64 && isa < ConstantSDNode > ( Op . getOperand ( 1 ) ) && ( Op . getConstantOperandVal ( 1 ) & 0x10 ) == 0 ) { unsigned Tmp = DAG . ComputeNumSignBits ( Op . getOperand ( 0 ) , Depth + 1 ) ; if ( Tmp > 32 ) return 33 ; } break ; } case RISCVISD :: VMV_X_S : if ( Op . getOperand ( 0 ) . getScalarValueSizeInBits ( ) > Subtarget . getXLen ( ) ) return 1 ; return Subtarget . getXLen ( ) - Op . getOperand ( 0 ) . getScalarValueSizeInBits ( ) + 1 ; } return 1 ; } </s>

Determine the number of bits in the operation that are sign bits .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Patmos Delay Slot Filler"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void AMDGPUInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { OS . flush ( ) ; printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s> void MipsPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; if ( getMipsSubtarget ( ) . os16 ( ) ) addPass ( createMipsOs16 ( getMipsTargetMachine ( ) ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


"Instruction use requires option to be enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> bool PPCCTRLoops :: runOnFunction ( Function & F ) { LI = & getAnalysis < LoopInfo > ( ) ; SE = & getAnalysis < ScalarEvolution > ( ) ; DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; DataLayoutPass * DLP = getAnalysisIfAvailable < DataLayoutPass > ( ) ; DL = DLP ? & DLP -> getDataLayout ( ) : nullptr ; LibInfo = getAnalysisIfAvailable < TargetLibraryInfo > ( ) ; bool MadeChange = false ; for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) { Loop * L = * I ; if ( ! L -> getParentLoop ( ) ) MadeChange |= convertToCTRLoop ( L ) ; } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> ARCSubtarget :: ARCSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : ARCGenSubtargetInfo ( TT , CPU , FS ) , FrameLowering ( * this ) , TLInfo ( TM , * this ) { } </s>


<s> void P2PassConfig :: addPreRegAlloc ( ) { P2TargetMachine & TM = getP2TargetMachine ( ) ; addPass ( createP2ExpandPseudosPass ( TM ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s>
bool
HexagonAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
if
(
!
InBrackets
)
{
MCB
.
clear
(
)
;
MCB
.
addOperand
(
MCOperand
::
createImm
(
0
)
)
;
}
HexagonOperand
&
FirstOperand
=
static_cast
<
HexagonOperand
&
>
(
*
Operands
[
0
]
)
;
if
(
FirstOperand
.
isToken
(
)
&&
FirstOperand
.
getToken
(
)
==
"{"
)
{
assert
(
Operands
.
size
(
)
==
1
&&
"Brackets should be by themselves"
)
;
if
(
InBrackets
)
{
getParser
(
)
.
Error
(
IDLoc
,
"Already in a packet"
)
;
InBrackets
=
false
;
return
true
;
}
InBrackets
=
true
;
return
false
;
}
if
(
FirstOperand
.
isToken
(
)
&&
FirstOperand
.
getToken
(
)
==
"}"
)
{
assert
(
Operands
.
size
(
)
==
1
&&
"Brackets should be by themselves"
)
;
if
(
!
InBrackets
)
{
getParser
(
)
.
Error
(
IDLoc
,
"Not in a packet"
)
;
return
true
;
}
InBrackets
=
false
;
if
(
matchBundleOptions
(
)
)
return
true
;
return
finishBundle
(
IDLoc
,
Out
)
;
}
MCInst
*
SubInst
=
new
(
getParser
(
)
.
getContext
(
)
)
MCInst
;
if
(
matchOneInstruction
(
*
SubInst
,
IDLoc
,
Operands
,
ErrorInfo
,
MatchingInlineAsm
)
)
{
if
(
InBrackets
)
eatToEndOfPacket
(
)
;
return
true
;
}
HexagonMCInstrInfo
::
extendIfNeeded
(
getParser
(
)
.
getContext
(
)
,
MII
,
MCB
,
*
SubInst
)
;
MCB
.
addOperand
(
MCOperand
::
createInst
(
SubInst
)
)
;
if
(
!
InBrackets
)
return
finishBundle
(
IDLoc
,
Out
)
;
return
false
;
}
</s>

Hexagon
Hexagon
0
Hexagon
Hexagon
0
"{"
1
"Brackets should be by themselves"
"Already in a packet"
"}"
1
"Brackets should be by themselves"
"Not in a packet"
Hexagon


"extern const void *const __OFFLOAD_TABLE__;\n"

"extern const void *const __offload_image_intelmic_start;\n"

"extern const void *const __offload_image_intelmic_end;\n\n"

"static const void *const __offload_target_data[] = {\n"

"  &__offload_image_intelmic_start, &__offload_image_intelmic_end\n"

"void GOMP_offload_register (const void *, int, const void *);\n"

"void GOMP_offload_unregister (const void *, int, const void *);\n\n"

"  GOMP_offload_register (&__OFFLOAD_TABLE__, %d, __offload_target_data);\n"

"  GOMP_offload_unregister (&__OFFLOAD_TABLE__, %d, __offload_target_data);\n"

Generates object file with the host side descriptor .


<s>
static
void
macho_branch_islands
(
void
)
{
char
tmp_buf
[
512
]
;
while
(
!
vec_safe_is_empty
(
branch_islands
)
)
{
branch_island
*
bi
=
&
branch_islands
->
last
(
)
;
const
char
*
label
=
IDENTIFIER_POINTER
(
bi
->
label_name
)
;
const
char
*
name
=
IDENTIFIER_POINTER
(
bi
->
function_name
)
;
char
name_buf
[
512
]
;
if
(
name
[
0
]
==
'*'
||
name
[
0
]
==
'&'
)
strcpy
(
name_buf
,
name
+
1
)
;
else
{
name_buf
[
0
]
=
'_'
;
strcpy
(
name_buf
+
1
,
name
)
;
}
strcpy
(
tmp_buf
,
"\n"
)
;
strcat
(
tmp_buf
,
label
)
;
if
(
write_symbols
==
DBX_DEBUG
||
write_symbols
==
XCOFF_DEBUG
)
dbxout_stabd
(
N_SLINE
,
bi
->
line_number
)
;
if
(
flag_pic
)
{
strcat
(
tmp_buf
,
":\n\tmflr r0\n\tbcl 20,31,"
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic\n"
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic:\n\tmflr r11\n"
)
;
strcat
(
tmp_buf
,
"\taddis r11,r11,ha16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
" - "
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic)\n"
)
;
strcat
(
tmp_buf
,
"\tmtlr r0\n"
)
;
strcat
(
tmp_buf
,
"\taddi r12,r11,lo16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
" - "
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic)\n"
)
;
strcat
(
tmp_buf
,
"\tmtctr r12\n\tbctr\n"
)
;
}
else
{
strcat
(
tmp_buf
,
":\n\tlis r12,hi16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
")\n\tori r12,r12,lo16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
")\n\tmtctr r12\n\tbctr"
)
;
}
output_asm_insn
(
tmp_buf
,
0
)
;
if
(
write_symbols
==
DBX_DEBUG
||
write_symbols
==
XCOFF_DEBUG
)
dbxout_stabd
(
N_SLINE
,
bi
->
line_number
)
;
branch_islands
->
pop
(
)
;
}
}
</s>

Generate far-jump branch islands for everything on the branch_island_list . Invoked immediately after the last instruction of the epilogue has been emitted ; the branch-islands must be appended to , and contiguous with , the function body . Mach-O stubs are generated in machopic_output_stub ( ) .


<s> static bool mips_function_ok_for_sibcall ( tree decl ATTRIBUTE_UNUSED , tree exp ATTRIBUTE_UNUSED ) { return TARGET_SIBCALLS ; } </s>

We can handle any sibcall when TARGET_SIBCALLS is true .


"  Copied r%d to a vector register r%d for insn %d\n"

Make vector copies for all register REGNO definitions and replace its uses in a chain .


<s> unsigned CAHPInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : return get ( Opcode ) . getSize ( ) ; case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return 0 ; case TargetOpcode :: INLINEASM : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const auto & TM = static_cast < const CAHPTargetMachine & > ( MF . getTarget ( ) ) ; return getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> void function_expander :: add_input_operand ( insn_code icode , rtx x ) { unsigned int opno = m_ops . length ( ) ; const insn_operand_data & operand = insn_data [ icode ] . operand [ opno ] ; machine_mode mode = operand . mode ; if ( mode == VOIDmode ) { gcc_assert ( operand . predicate == aarch64_any_register_operand ) ; mode = GET_MODE ( x ) ; } else if ( ! VECTOR_MODE_P ( GET_MODE ( x ) ) && VECTOR_MODE_P ( mode ) ) x = expand_vector_broadcast ( mode , x ) ; else if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL ) { gcc_assert ( GET_MODE ( x ) == VNx16BImode ) ; x = gen_lowpart ( mode , x ) ; } m_ops . safe_grow ( m_ops . length ( ) + 1 , true ) ; create_input_operand ( & m_ops . last ( ) , x , mode ) ; } </s>

Create op and add it into M_OPS and increase OPNO .


<s> void GCNHazardRecognizer :: EmitNoop ( ) { EmittedInstrs . push_front ( nullptr ) ; } </s>

EmitNoop - This callback is invoked when a noop was added to the instruction stream .


<s> void addInstruction ( MachineInstr * I ) { Instrs . push_back ( I ) ; } </s>

Record pressure difference induced by the given operand list to node with index Idx .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { MachineFunctionPass :: getAnalysisUsage ( AU ) ; AU . addRequired < MachineBranchProbabilityInfo > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> unsigned AArch64Subtarget :: classifyGlobalFunctionReference ( const GlobalValue * GV , const TargetMachine & TM ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) && ! GV -> hasInternalLinkage ( ) ) return AArch64II :: MO_GOT ; auto * F = dyn_cast < Function > ( GV ) ; if ( UseNonLazyBind && F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) && ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return AArch64II :: MO_GOT ; return AArch64II :: MO_NO_FLAG ; } </s>

Classify a global function reference for the current subtarget .


<s> bool enableEarlyIfConversion ( ) const override { return true ; } </s>

Enable the use of the early if conversion pass .


<s> void AArch64_ELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; SupportDebugThreadLocalLocation = false ; } </s>

This method must be called before any actual lowering is done .


<s> bool GCNPassConfig :: addPreISel ( ) { AMDGPUPassConfig :: addPreISel ( ) ; addPass ( createSinkingPass ( ) ) ; addPass ( createSITypeRewriter ( ) ) ; addPass ( createSIAnnotateControlFlowPass ( ) ) ; return false ; } </s>


<s> SDValue MBlazeTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: ConstantPool : return LowerConstantPool ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return LowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( Op , DAG ) ; case ISD :: SELECT_CC : return LowerSELECT_CC ( Op , DAG ) ; case ISD :: VASTART : return LowerVASTART ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

MBlaze MBlaze ISD::ConstantPool ISD::GlobalAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::SELECT_CC ISD::VASTART


<s> void X86FrameLowering :: orderFrameObjects ( const MachineFunction & MF , SmallVectorImpl < int > & ObjectsToAllocate ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ObjectsToAllocate . empty ( ) ) return ; std :: vector < X86FrameSortingObject > SortingObjects ( MFI . getObjectIndexEnd ( ) ) ; for ( auto & Obj : ObjectsToAllocate ) { SortingObjects [ Obj ] . IsValid = true ; SortingObjects [ Obj ] . ObjectIndex = Obj ; SortingObjects [ Obj ] . ObjectAlignment = MFI . getObjectAlignment ( Obj ) ; int ObjectSize = MFI . getObjectSize ( Obj ) ; if ( ObjectSize == 0 ) SortingObjects [ Obj ] . ObjectSize = 4 ; else SortingObjects [ Obj ] . ObjectSize = ObjectSize ; } for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( MI . isDebugInstr ( ) ) continue ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isFI ( ) ) continue ; int Index = MO . getIndex ( ) ; if ( Index >= 0 && Index < MFI . getObjectIndexEnd ( ) && SortingObjects [ Index ] . IsValid ) SortingObjects [ Index ] . ObjectNumUses ++ ; } } } std :: stable_sort ( SortingObjects . begin ( ) , SortingObjects . end ( ) , X86FrameSortingComparator ( ) ) ; int i = 0 ; for ( auto & Obj : SortingObjects ) { if ( ! Obj . IsValid ) break ; ObjectsToAllocate [ i ++ ] = Obj . ObjectIndex ; } if ( ! TRI -> needsStackRealignment ( MF ) && hasFP ( MF ) ) std :: reverse ( ObjectsToAllocate . begin ( ) , ObjectsToAllocate . end ( ) ) ; } </s>


"RegScavenger required for long branching"

"new block should be inserted for expanding unconditional branch"

Insert an unconditional indirect branch at the end of MBB to NewDestBB .


<s> const char * F2003fTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( F2003fISD :: NodeType ) Opcode ) { case F2003fISD :: FIRST_NUMBER : break ; case F2003fISD :: Wrapper : return "F2003fISD::Wrapper" ; case F2003fISD :: FENXEO : return "F2003fISD::FENXEO" ; case F2003fISD :: DOSNUD : return "F2003fISD::DOSNUD" ; case F2003fISD :: SELECT_CC : return "F2003fISD::SELECT_CC" ; case F2003fISD :: BR_CC : return "F2003fISD::BR_CC" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> bool Mips16TargetLowering :: isEligibleForTailCallOptimization ( const MipsCC & MipsCCInfo , unsigned NextStackOffset , const MipsFunctionInfo & FI ) const { return false ; } </s>

Returns true if the call can be lowered as a tail call .


<s> static rtx frame_emit_store ( int regno , int regno_note , rtx addr , rtx cfa , int cfa_offset ) { rtx reg = gen_rtx_REG ( Pmode , regno ) ; rtx mem = gen_frame_mem ( Pmode , addr ) ; rtx mov = gen_movsi ( mem , reg ) ; rtx reg_note = gen_rtx_REG ( Pmode , regno_note ) ; rtx cfa_relative_addr = gen_rtx_PLUS ( Pmode , cfa , gen_int_si ( cfa_offset ) ) ; rtx cfa_relative_mem = gen_frame_mem ( Pmode , cfa_relative_addr ) ; rtx real = gen_rtx_SET ( VOIDmode , cfa_relative_mem , reg_note ) ; add_reg_note ( mov , REG_CFA_OFFSET , real ) ; return emit_insn ( mov ) ; } </s>

Emit a store in the stack frame to save REGNO at address ADDR , and emit the corresponding REG_CFA_OFFSET note described by CFA and CFA_OFFSET . Return the emitted insn .


<s> int rs6000_store_data_bypass_p ( rtx_insn * out_insn , rtx_insn * in_insn ) { rtx out_set , in_set ; rtx out_pat , in_pat ; rtx out_exp , in_exp ; int i , j ; in_set = single_set ( in_insn ) ; if ( in_set ) { if ( MEM_P ( SET_DEST ( in_set ) ) ) { out_set = single_set ( out_insn ) ; if ( ! out_set ) { out_pat = PATTERN ( out_insn ) ; if ( GET_CODE ( out_pat ) == PARALLEL ) { for ( i = 0 ; i < XVECLEN ( out_pat , 0 ) ; i ++ ) { out_exp = XVECEXP ( out_pat , 0 , i ) ; if ( ( GET_CODE ( out_exp ) == CLOBBER ) || ( GET_CODE ( out_exp ) == USE ) ) continue ; else if ( GET_CODE ( out_exp ) != SET ) return false ; } } } } } else { in_pat = PATTERN ( in_insn ) ; if ( GET_CODE ( in_pat ) != PARALLEL ) return false ; for ( i = 0 ; i < XVECLEN ( in_pat , 0 ) ; i ++ ) { in_exp = XVECEXP ( in_pat , 0 , i ) ; if ( ( GET_CODE ( in_exp ) == CLOBBER ) || ( GET_CODE ( in_exp ) == USE ) ) continue ; else if ( GET_CODE ( in_exp ) != SET ) return false ; if ( MEM_P ( SET_DEST ( in_exp ) ) ) { out_set = single_set ( out_insn ) ; if ( ! out_set ) { out_pat = PATTERN ( out_insn ) ; if ( GET_CODE ( out_pat ) != PARALLEL ) return false ; for ( j = 0 ; j < XVECLEN ( out_pat , 0 ) ; j ++ ) { out_exp = XVECEXP ( out_pat , 0 , j ) ; if ( ( GET_CODE ( out_exp ) == CLOBBER ) || ( GET_CODE ( out_exp ) == USE ) ) continue ; else if ( GET_CODE ( out_exp ) != SET ) return false ; } } } } } return store_data_bypass_p ( out_insn , in_insn ) ; } </s>

Given that there exists at least one variable that is set ( produced ) by OUT_INSN and read ( consumed ) by IN_INSN , return true iff IN_INSN represents one or more memory store operations and none of the variables set by OUT_INSN is used by IN_INSN as the address of a store operation . If either IN_INSN or OUT_INSN does not represent a `` single '' RTL SET expression ( as loosely defined by the implementation of the single_set function ) or a PARALLEL with only SETs , CLOBBERs , and USEs inside , this function returns false . This rs6000-specific version of store_data_bypass_p checks for certain conditions that result in assertion failures ( and internal compiler errors ) in the generic store_data_bypass_p function and returns false rather than calling store_data_bypass_p if one of the problematic conditions is detected .


Return an array that contains the direct target flag values and their names .


<s> TargetPassConfig * SHUXITargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new SHUXIPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s>
bool
NVPTXAsmPrinter
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
{
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
MCOp
=
MCOperand
::
createReg
(
encodeVirtualRegister
(
MO
.
getReg
(
)
)
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
createImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
createExpr
(
MCSymbolRefExpr
::
create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
OutContext
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
GetSymbolRef
(
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
GetSymbolRef
(
getSymbol
(
MO
.
getGlobal
(
)
)
)
;
break
;
case
MachineOperand
::
MO_FPImmediate
:
{
const
ConstantFP
*
Cnt
=
MO
.
getFPImm
(
)
;
const
APFloat
&
Val
=
Cnt
->
getValueAPF
(
)
;
switch
(
Cnt
->
getType
(
)
->
getTypeID
(
)
)
{
default
:
report_fatal_error
(
"Unsupported FP type"
)
;
break
;
case
Type
::
FloatTyID
:
MCOp
=
MCOperand
::
createExpr
(
NVPTXFloatMCExpr
::
createConstantFPSingle
(
Val
,
OutContext
)
)
;
break
;
case
Type
::
DoubleTyID
:
MCOp
=
MCOperand
::
createExpr
(
NVPTXFloatMCExpr
::
createConstantFPDouble
(
Val
,
OutContext
)
)
;
break
;
}
break
;
}
}
return
true
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .

NVPTX
NVPTX
"unknown operand type"
"Unsupported FP type"
NVPTX
NVPTX


<s> static rtx s390_function_arg ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( ! arg . named ) s390_check_type_for_vector_abi ( arg . type , true , false ) ; if ( s390_function_arg_vector ( arg . mode , arg . type ) ) { if ( ! arg . named || ( cum -> vrs + 1 > VEC_ARG_NUM_REG ) ) return NULL_RTX ; return gen_rtx_REG ( arg . mode , cum -> vrs + FIRST_VEC_ARG_REGNO ) ; } else if ( s390_function_arg_float ( arg . mode , arg . type ) ) { if ( cum -> fprs + 1 > FP_ARG_NUM_REG ) return NULL_RTX ; else return gen_rtx_REG ( arg . mode , cum -> fprs + 16 ) ; } else if ( s390_function_arg_integer ( arg . mode , arg . type ) ) { int size = s390_function_arg_size ( arg . mode , arg . type ) ; int n_gprs = ( size + UNITS_PER_LONG - 1 ) / UNITS_PER_LONG ; if ( cum -> gprs + n_gprs > GP_ARG_NUM_REG ) return NULL_RTX ; else if ( n_gprs == 1 || UNITS_PER_WORD == UNITS_PER_LONG ) return gen_rtx_REG ( arg . mode , cum -> gprs + 2 ) ; else if ( n_gprs == 2 ) { rtvec p = rtvec_alloc ( 2 ) ; RTVEC_ELT ( p , 0 ) = gen_rtx_EXPR_LIST ( SImode , gen_rtx_REG ( SImode , cum -> gprs + 2 ) , const0_rtx ) ; RTVEC_ELT ( p , 1 ) = gen_rtx_EXPR_LIST ( SImode , gen_rtx_REG ( SImode , cum -> gprs + 3 ) , GEN_INT ( 4 ) ) ; return gen_rtx_PARALLEL ( arg . mode , p ) ; } } else if ( arg . end_marker_p ( ) ) return const0_rtx ; gcc_unreachable ( ) ; } </s>

Define where to put the arguments to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . On S/390 , we use general purpose registers 2 through 6 to pass integer , pointer , and certain structure arguments , and floating point registers 0 and 2 ( 0 , 2 , 4 , and 6 on 64-bit ) to pass floating point arguments . All remaining arguments are pushed to the stack .


<s>
static
void
rs6000_darwin_file_start
(
void
)
{
static
const
struct
{
const
char
*
arg
;
const
char
*
name
;
HOST_WIDE_INT
if_set
;
}
mapping
[
]
=
{
{
"ppc64"
,
"ppc64"
,
MASK_64BIT
}
,
{
"970"
,
"ppc970"
,
MASK_PPC_GPOPT
|
MASK_MFCRF
|
MASK_POWERPC64
}
,
{
"power4"
,
"ppc970"
,
0
}
,
{
"G5"
,
"ppc970"
,
0
}
,
{
"7450"
,
"ppc7450"
,
0
}
,
{
"7400"
,
"ppc7400"
,
MASK_ALTIVEC
}
,
{
"G4"
,
"ppc7400"
,
0
}
,
{
"750"
,
"ppc750"
,
0
}
,
{
"740"
,
"ppc750"
,
0
}
,
{
"G3"
,
"ppc750"
,
0
}
,
{
"604e"
,
"ppc604e"
,
0
}
,
{
"604"
,
"ppc604"
,
0
}
,
{
"603e"
,
"ppc603"
,
0
}
,
{
"603"
,
"ppc603"
,
0
}
,
{
"601"
,
"ppc601"
,
0
}
,
{
,
"ppc"
,
0
}
}
;
const
char
*
cpu_id
=
""
;
size_t
i
;
rs6000_file_start
(
)
;
darwin_file_start
(
)
;
if
(
rs6000_default_cpu
!=
0
&&
rs6000_default_cpu
[
0
]
!=
'\0'
)
cpu_id
=
rs6000_default_cpu
;
if
(
global_options_set
.
x_rs6000_cpu_index
)
cpu_id
=
processor_target_table
[
rs6000_cpu_index
]
.
name
;
i
=
0
;
while
(
mapping
[
i
]
.
arg
!=
&&
strcmp
(
mapping
[
i
]
.
arg
,
cpu_id
)
!=
0
&&
(
mapping
[
i
]
.
if_set
&
rs6000_isa_flags
)
==
0
)
i
++
;
fprintf
(
asm_out_file
,
"\t.machine %s\n"
,
mapping
[
i
]
.
name
)
;
}
</s>

Output a .machine directive for the Darwin assembler , and call the generic start_file routine .


<s> static int rs6000_builtin_vectorization_cost ( enum vect_cost_for_stmt type_of_cost , tree vectype , int misalign ) { unsigned elements ; tree elem_type ; switch ( type_of_cost ) { case scalar_stmt : case scalar_load : case scalar_store : case vector_stmt : case vector_load : case vector_store : case vec_to_scalar : case scalar_to_vec : case cond_branch_not_taken : return 1 ; case vec_perm : if ( TARGET_VSX ) return 3 ; else return 1 ; case vec_promote_demote : if ( TARGET_VSX ) return 4 ; else return 1 ; case cond_branch_taken : return 3 ; case unaligned_load : if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == 2 ) return 2 ; if ( elements == 4 ) { switch ( misalign ) { case 8 : return 2 ; case - 1 : case 4 : case 12 : return 22 ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return 2 ; case unaligned_store : if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == 2 ) return 2 ; if ( elements == 4 ) { switch ( misalign ) { case 8 : return 2 ; case - 1 : case 4 : case 12 : return 23 ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return 2 ; case vec_construct : elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; elem_type = TREE_TYPE ( vectype ) ; if ( SCALAR_FLOAT_TYPE_P ( elem_type ) && TYPE_PRECISION ( elem_type ) == 32 ) return elements + 1 ; else return elements / 2 + 1 ; default : gcc_unreachable ( ) ; } } </s>


<s> EVT SystemZTargetLowering :: getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const { return Subtarget . hasVector ( ) ? MVT :: v2i64 : MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> void AArch64AsmPrinter :: emitJumpTableInfo ( ) { const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; if ( ! MJTI ) return ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; if ( JT . empty ( ) ) return ; const TargetLoweringObjectFile & TLOF = getObjFileLowering ( ) ; MCSection * ReadOnlySec = TLOF . getSectionForJumpTable ( MF -> getFunction ( ) , TM ) ; OutStreamer -> SwitchSection ( ReadOnlySec ) ; auto AFI = MF -> getInfo < AArch64FunctionInfo > ( ) ; for ( unsigned JTI = 0 , e = JT . size ( ) ; JTI != e ; ++ JTI ) { const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; if ( JTBBs . empty ( ) ) continue ; unsigned Size = AFI -> getJumpTableEntrySize ( JTI ) ; emitAlignment ( Align ( Size ) ) ; OutStreamer -> emitLabel ( GetJTISymbol ( JTI ) ) ; const MCSymbol * BaseSym = AArch64FI -> getJumpTableEntryPCRelSymbol ( JTI ) ; const MCExpr * Base = MCSymbolRefExpr :: create ( BaseSym , OutContext ) ; for ( auto * JTBB : JTBBs ) { const MCExpr * Value = MCSymbolRefExpr :: create ( JTBB -> getSymbol ( ) , OutContext ) ; Value = MCBinaryExpr :: createSub ( Value , Base , OutContext ) ; if ( Size != 4 ) Value = MCBinaryExpr :: createLShr ( Value , MCConstantExpr :: create ( 2 , OutContext ) , OutContext ) ; OutStreamer -> emitValue ( Value , Size ) ; } } } </s>

Print assembly representations of the jump tables used by the current function to the current output stream .


<s> bool WebAssemblyTargetLowering :: isCheapToSpeculateCttz ( ) const { return true ; } </s>

Return true if it is cheap to speculate a call to intrinsic cttz .


<s> virtual void initializePass ( ) { pushTTIStack ( this ) ; } </s>

initializePass - This method may be overriden by immutable passes to allow them to perform various initialization actions they require .


<s> static void load_lr_save ( int regno , rtx frame_reg_rtx , int offset ) { rtx mem = gen_frame_mem_offset ( Pmode , frame_reg_rtx , offset ) ; rtx reg = gen_rtx_REG ( Pmode , regno ) ; emit_move_insn ( reg , mem ) ; } </s>

Like cr , the move to lr instruction can be scheduled after the stack deallocation , but unlike cr , its stack frame save is still valid . So we only need to emit the cfa_restore on the correct instruction .


<s> static bool riscv_valid_offset_p ( rtx x , machine_mode mode ) { if ( ! const_arith_operand ( x , Pmode ) ) return false ; if ( GET_MODE_SIZE ( mode ) . to_constant ( ) > UNITS_PER_WORD && ! SMALL_OPERAND ( INTVAL ( x ) + GET_MODE_SIZE ( mode ) . to_constant ( ) - UNITS_PER_WORD ) ) return false ; return true ; } </s>

Return true if , for every base register BASE_REG , ( plus BASE_REG X ) can address a value of mode MODE .


<s> bool nonpic_symbol_mentioned_p ( rtx x ) { const char * fmt ; int i ; if ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF || GET_CODE ( x ) == PC ) return true ; if ( GET_CODE ( x ) == CONST_DOUBLE ) return false ; if ( GET_CODE ( x ) == UNSPEC && ( XINT ( x , 1 ) == UNSPEC_PIC || XINT ( x , 1 ) == UNSPEC_GOT || XINT ( x , 1 ) == UNSPEC_GOTOFF || XINT ( x , 1 ) == UNSPEC_GOTPLT || XINT ( x , 1 ) == UNSPEC_GOTTPOFF || XINT ( x , 1 ) == UNSPEC_DTPOFF || XINT ( x , 1 ) == UNSPEC_TPOFF || XINT ( x , 1 ) == UNSPEC_PLT || XINT ( x , 1 ) == UNSPEC_SYMOFF || XINT ( x , 1 ) == UNSPEC_PCREL_SYMOFF ) ) return false ; fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( x , i ) - 1 ; j >= 0 ; j -- ) if ( nonpic_symbol_mentioned_p ( XVECEXP ( x , i , j ) ) ) return true ; } else if ( fmt [ i ] == 'e' && nonpic_symbol_mentioned_p ( XEXP ( x , i ) ) ) return true ; } return false ; } </s>

Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol is n't protected by a PIC unspec .


<s> bool isKZeroMasked ( ) const { return ( Attributes & KZeroMasked ) != 0 ; } </s>

Returns true iff the group of FMA opcodes holds k-zero-masked opcodes .


<s> int mips_ldst_scaled_shift ( machine_mode mode ) { int shift = exact_log2 ( GET_MODE_UNIT_SIZE ( mode ) ) ; if ( shift < 0 || shift > 8 ) gcc_unreachable ( ) ; return shift ; } </s>

Return the scale shift that applied to MSA LD/ST address offset .


"LowerFormalArguments Unhandled argument type: "

"functions with VarArgs or StructRet are not supported"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> void SITargetLowering :: AdjustInstrPostInstrSelection ( MachineInstr & MI , SDNode * Node ) const { const SIInstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; if ( TII -> isVOP3 ( MI . getOpcode ( ) ) ) { TII -> legalizeOperandsVOP3 ( MRI , MI ) ; return ; } int NoRetAtomicOp = AMDGPU :: getAtomicNoRetOp ( MI . getOpcode ( ) ) ; if ( NoRetAtomicOp != - 1 ) { if ( ! Node -> hasAnyUseOfValue ( 0 ) ) { MI . setDesc ( TII -> get ( NoRetAtomicOp ) ) ; MI . RemoveOperand ( 0 ) ; return ; } if ( ( Node -> hasNUsesOfValue ( 1 , 0 ) && Node -> use_begin ( ) -> isMachineOpcode ( ) && Node -> use_begin ( ) -> getMachineOpcode ( ) == AMDGPU :: EXTRACT_SUBREG && ! Node -> use_begin ( ) -> hasAnyUseOfValue ( 0 ) ) ) { unsigned Def = MI . getOperand ( 0 ) . getReg ( ) ; MI . setDesc ( TII -> get ( NoRetAtomicOp ) ) ; MI . RemoveOperand ( 0 ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , TII -> get ( AMDGPU :: IMPLICIT_DEF ) , Def ) ; } return ; } } </s>

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


<s> void SIFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const SIMachineFunctionInfo * FuncInfo = MF . getInfo < SIMachineFunctionInfo > ( ) ; if ( FuncInfo -> isEntryFunction ( ) ) return ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const SIInstrInfo * TII = ST . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; for ( const SIMachineFunctionInfo :: SGPRSpillVGPRCSR & Reg : FuncInfo -> getSGPRSpillVGPRs ( ) ) { if ( ! Reg . FI . hasValue ( ) ) continue ; TII -> loadRegFromStackSlot ( MBB , MBBI , Reg . VGPR , Reg . FI . getValue ( ) , & AMDGPU :: VGPR_32RegClass , & TII -> getRegisterInfo ( ) ) ; } unsigned StackPtrReg = FuncInfo -> getStackPtrOffsetReg ( ) ; if ( StackPtrReg == AMDGPU :: NoRegister ) return ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; uint32_t NumBytes = MFI . getStackSize ( ) ; DebugLoc DL ; if ( NumBytes != 0 && hasSP ( MF ) ) { uint32_t RoundedSize = FuncInfo -> isStackRealigned ( ) ? NumBytes + MFI . getMaxAlignment ( ) : NumBytes ; BuildMI ( MBB , MBBI , DL , TII -> get ( AMDGPU :: S_SUB_U32 ) , StackPtrReg ) . addReg ( StackPtrReg ) . addImm ( RoundedSize * ST . getWavefrontSize ( ) ) ; } } </s>

AMDGPU SI SI SI SI SI AMDGPU::VGPR_32RegClass AMDGPU::NoRegister 0 AMDGPU::S_SUB_U32


<s>
StringRef
getPassName
(
)
const
override
{
return
"AGC pseudo instruction expansion pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .

AGC
"AGC pseudo instruction expansion pass"


<s> void msp430_split_movsi ( rtx * operands ) { rtx op00 , op02 , op10 , op12 ; op00 = msp430_subreg ( HImode , operands [ 0 ] , SImode , 0 ) ; op02 = msp430_subreg ( HImode , operands [ 0 ] , SImode , 2 ) ; if ( GET_CODE ( operands [ 1 ] ) == CONST || GET_CODE ( operands [ 1 ] ) == SYMBOL_REF ) { op10 = gen_rtx_ZERO_EXTRACT ( HImode , operands [ 1 ] , GEN_INT ( 16 ) , GEN_INT ( 0 ) ) ; op10 = gen_rtx_CONST ( HImode , op10 ) ; op12 = gen_rtx_ZERO_EXTRACT ( HImode , operands [ 1 ] , GEN_INT ( 16 ) , GEN_INT ( 16 ) ) ; op12 = gen_rtx_CONST ( HImode , op12 ) ; } else { op10 = msp430_subreg ( HImode , operands [ 1 ] , SImode , 0 ) ; op12 = msp430_subreg ( HImode , operands [ 1 ] , SImode , 2 ) ; } if ( rtx_equal_p ( operands [ 0 ] , operands [ 1 ] ) ) { operands [ 2 ] = op02 ; operands [ 4 ] = op12 ; operands [ 3 ] = op00 ; operands [ 5 ] = op10 ; } else if ( rtx_equal_p ( op00 , op12 ) || ( REG_P ( op00 ) && reg_mentioned_p ( op00 , op10 ) ) || ( REG_P ( op10 ) && reg_mentioned_p ( op10 , op00 ) ) ) { operands [ 2 ] = op02 ; operands [ 4 ] = op12 ; operands [ 3 ] = op00 ; operands [ 5 ] = op10 ; } else { operands [ 2 ] = op00 ; operands [ 4 ] = op10 ; operands [ 3 ] = op02 ; operands [ 5 ] = op12 ; } } </s>

Called by movsi_x to generate the HImode operands .


<s> bool TeakRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> int avr_jump_mode ( rtx x , rtx_insn * insn ) { int dest_addr = INSN_ADDRESSES ( INSN_UID ( GET_CODE ( x ) == LABEL_REF ? XEXP ( x , 0 ) : x ) ) ; int cur_addr = INSN_ADDRESSES ( INSN_UID ( insn ) ) ; int jump_distance = cur_addr - dest_addr ; if ( IN_RANGE ( jump_distance , - 63 , 62 ) ) return 1 ; else if ( IN_RANGE ( jump_distance , - 2046 , 2045 ) ) return 2 ; else if ( AVR_HAVE_JMP_CALL ) return 3 ; return 2 ; } </s>

Choose mode for jump insn : 1 - relative jump in range -63 < = x < = 62 ; 2 - relative jump in range -2046 < = x < = 2045 ; 3 - absolute jump ( only for ATmega [ 16 ] 03 ) .


<s> static rtx mn10300_delegitimize_address ( rtx orig_x ) { rtx x = orig_x , ret , addend = NULL ; bool need_mem ; if ( MEM_P ( x ) ) x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) != PLUS || GET_MODE ( x ) != Pmode ) return orig_x ; if ( XEXP ( x , 0 ) == pic_offset_table_rtx ) ; else if ( GET_CODE ( XEXP ( x , 0 ) ) == PLUS ) { rtx x0 = XEXP ( x , 0 ) ; rtx x00 = XEXP ( x0 , 0 ) ; rtx x01 = XEXP ( x0 , 1 ) ; if ( x00 == pic_offset_table_rtx ) addend = x01 ; else if ( x01 == pic_offset_table_rtx ) addend = x00 ; else return orig_x ; } else return orig_x ; x = XEXP ( x , 1 ) ; if ( GET_CODE ( x ) != CONST ) return orig_x ; x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) != UNSPEC ) return orig_x ; ret = XVECEXP ( x , 0 , 0 ) ; if ( XINT ( x , 1 ) == UNSPEC_GOTOFF ) need_mem = false ; else if ( XINT ( x , 1 ) == UNSPEC_GOT ) need_mem = true ; else return orig_x ; gcc_assert ( GET_CODE ( ret ) == SYMBOL_REF ) ; if ( need_mem != MEM_P ( orig_x ) ) return orig_x ; if ( need_mem && addend ) return orig_x ; if ( addend ) ret = gen_rtx_PLUS ( Pmode , addend , ret ) ; return ret ; } </s>

Undo pic address legitimization for the benefit of debug info .


"Disassembly not yet supported for subtarget"

Returns the disassembly of a single instruction .


"ReplaceFMULS: Erratum Fix LBR32: replace FMULS instruction with a "

"routine using conversions/double precision operations to replace "


<s>
static
void
rs6000_debug_reg_print
(
int
first_regno
,
int
last_regno
,
const
char
*
reg_name
)
{
int
r
,
m
;
for
(
r
=
first_regno
;
r
<=
last_regno
;
++
r
)
{
const
char
*
comma
=
""
;
int
len
;
if
(
first_regno
==
last_regno
)
fprintf
(
stderr
,
"%s:\t"
,
reg_name
)
;
else
fprintf
(
stderr
,
"%s%d:\t"
,
reg_name
,
r
first_regno
)
;
len
=
8
;
for
(
m
=
0
;
m
<
NUM_MACHINE_MODES
;
++
m
)
if
(
rs6000_hard_regno_mode_ok_p
[
m
]
[
r
]
&&
rs6000_hard_regno_nregs
[
m
]
[
r
]
)
{
if
(
len
>
70
)
{
fprintf
(
stderr
,
",\n\t"
)
;
len
=
8
;
comma
=
""
;
}
if
(
rs6000_hard_regno_nregs
[
m
]
[
r
]
>
1
)
len
+=
fprintf
(
stderr
,
"%s%s/%d"
,
comma
,
GET_MODE_NAME
(
m
)
,
rs6000_hard_regno_nregs
[
m
]
[
r
]
)
;
else
len
+=
fprintf
(
stderr
,
"%s%s"
,
comma
,
GET_MODE_NAME
(
m
)
)
;
comma
=
", "
;
}
if
(
call_used_regs
[
r
]
)
{
if
(
len
>
70
)
{
fprintf
(
stderr
,
",\n\t"
)
;
len
=
8
;
comma
=
""
;
}
len
+=
fprintf
(
stderr
,
"%s%s"
,
comma
,
"call-used"
)
;
comma
=
", "
;
}
if
(
fixed_regs
[
r
]
)
{
if
(
len
>
70
)
{
fprintf
(
stderr
,
",\n\t"
)
;
len
=
8
;
comma
=
""
;
}
len
+=
fprintf
(
stderr
,
"%s%s"
,
comma
,
"fixed"
)
;
comma
=
", "
;
}
if
(
len
>
70
)
{
fprintf
(
stderr
,
",\n\t"
)
;
comma
=
""
;
}
len
+=
fprintf
(
stderr
,
"%sreg-class = %s"
,
comma
,
reg_class_names
[
(
int
)
rs6000_regno_regclass
[
r
]
]
)
;
comma
=
", "
;
if
(
len
>
70
)
{
fprintf
(
stderr
,
",\n\t"
)
;
comma
=
""
;
}
fprintf
(
stderr
,
"%sregno = %d\n"
,
comma
,
r
)
;
}
}
</s>

Print interesting facts about registers .


<s>
SDValue
MSP430TargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
switch
(
CallConv
)
{
default
:
report_fatal_error
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
isVarArg
,
Ins
,
dl
,
DAG
,
InVals
)
;
case
CallingConv
::
MSP430_INTR
:
if
(
Ins
.
empty
(
)
)
return
Chain
;
report_fatal_error
(
"ISRs cannot have arguments"
)
;
}
}
</s>


"Unexpected instruction to emit with custom inserter"

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> bool sparc_expand_conditional_move ( machine_mode mode , rtx * operands ) { enum rtx_code rc = GET_CODE ( operands [ 1 ] ) ; machine_mode cmp_mode ; rtx cc_reg , dst , cmp ; cmp = operands [ 1 ] ; if ( GET_MODE ( XEXP ( cmp , 0 ) ) == DImode && ! TARGET_ARCH64 ) return false ; if ( GET_MODE ( XEXP ( cmp , 0 ) ) == TFmode && ! TARGET_HARD_QUAD ) cmp = sparc_emit_float_lib_cmp ( XEXP ( cmp , 0 ) , XEXP ( cmp , 1 ) , rc ) ; cmp_mode = GET_MODE ( XEXP ( cmp , 0 ) ) ; rc = GET_CODE ( cmp ) ; dst = operands [ 0 ] ; if ( ! rtx_equal_p ( operands [ 2 ] , dst ) && ! rtx_equal_p ( operands [ 3 ] , dst ) ) { if ( reg_overlap_mentioned_p ( dst , cmp ) ) dst = gen_reg_rtx ( mode ) ; emit_move_insn ( dst , operands [ 3 ] ) ; } else if ( operands [ 2 ] == dst ) { operands [ 2 ] = operands [ 3 ] ; if ( GET_MODE_CLASS ( cmp_mode ) == MODE_FLOAT ) rc = reverse_condition_maybe_unordered ( rc ) ; else rc = reverse_condition ( rc ) ; } if ( XEXP ( cmp , 1 ) == const0_rtx && GET_CODE ( XEXP ( cmp , 0 ) ) == REG && cmp_mode == DImode && v9_regcmp_p ( rc ) ) cc_reg = XEXP ( cmp , 0 ) ; else cc_reg = gen_compare_reg_1 ( rc , XEXP ( cmp , 0 ) , XEXP ( cmp , 1 ) ) ; cmp = gen_rtx_fmt_ee ( rc , GET_MODE ( cc_reg ) , cc_reg , const0_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dst , gen_rtx_IF_THEN_ELSE ( mode , cmp , operands [ 2 ] , dst ) ) ) ; if ( dst != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , dst ) ; return true ; } </s>

Emit code to conditionally move either OPERANDS [ 2 ] or OPERANDS [ 3 ] into OPERANDS [ 0 ] in MODE . OPERANDS [ 1 ] is the operator of the condition .


<s> bool OR1KFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || TRI -> needsStackRealignment ( MF ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void AMDGPUFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


<s> bool isZero ( ) { if ( ! isImm ( ) ) return false ; if ( const auto * ConstExpr = dyn_cast < MCConstantExpr > ( Imm . Val ) ) { int64_t Value = ConstExpr -> getValue ( ) ; return Value == 0 ; } return false ; } </s>

Return true if the expression is a constant zero .


<s> static void pa_output_function_epilogue ( FILE * file ) { rtx_insn * insn = get_last_insn ( ) ; bool extra_nop ; if ( NOTE_P ( insn ) ) insn = prev_real_insn ( insn ) ; if ( insn && NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == SEQUENCE ) insn = as_a < rtx_sequence * > ( PATTERN ( insn ) ) -> insn ( 0 ) ; if ( insn && CALL_P ( insn ) ) { fputs ( "\tnop\n" , file ) ; extra_nop = true ; } else extra_nop = false ; fputs ( "\t.EXIT\n\t.PROCEND\n" , file ) ; if ( TARGET_SOM && TARGET_GAS ) { in_section = NULL ; cfun -> machine -> in_nsubspa = 2 ; } if ( cfun -> is_thunk ) return ; if ( INSN_ADDRESSES_SET_P ( ) ) { last_address = extra_nop ? 4 : 0 ; insn = get_last_nonnote_insn ( ) ; if ( insn ) { last_address += INSN_ADDRESSES ( INSN_UID ( insn ) ) ; if ( INSN_P ( insn ) ) last_address += insn_default_length ( insn ) ; } last_address = ( ( last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1 ) & ~ ( FUNCTION_BOUNDARY / BITS_PER_UNIT - 1 ) ) ; } else last_address = UINT_MAX ; update_total_code_bytes ( last_address ) ; } </s>

This function generates the assembly code for function exit . Args are as for output_function_prologue ( ) . The function epilogue should not depend on the current stack pointer ! It should use the frame pointer only . This is mandatory because of alloca ; we also take advantage of it to omit stack adjustments before returning .


<s> SDValue AMDGPUTargetLowering :: LowerFREM ( SDValue Op , SelectionDAG & DAG ) const { SDLoc SL ( Op ) ; EVT VT = Op . getValueType ( ) ; auto Flags = Op -> getFlags ( ) ; SDValue X = Op . getOperand ( 0 ) ; SDValue Y = Op . getOperand ( 1 ) ; SDValue Div = DAG . getNode ( ISD :: FDIV , SL , VT , X , Y , Flags ) ; SDValue Trunc = DAG . getNode ( ISD :: FTRUNC , SL , VT , Div , Flags ) ; SDValue Neg = DAG . getNode ( ISD :: FNEG , SL , VT , Trunc , Flags ) ; return DAG . getNode ( ISD :: FMA , SL , VT , Neg , Y , X , Flags ) ; } </s>

Split a vector store into multiple scalar stores .

AMDGPU AMDGPU 0 1 ISD::FDIV ISD::FTRUNC ISD::FNEG ISD::FMA


<s> uint64_t MipsFrameLowering :: estimateStackSize ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; int64_t Offset = 0 ; for ( int I = MFI -> getObjectIndexBegin ( ) ; I != 0 ; ++ I ) Offset = std :: max ( Offset , - MFI -> getObjectOffset ( I ) ) ; for ( const MCPhysReg * R = TRI . getCalleeSavedRegs ( & MF ) ; * R ; ++ R ) { unsigned Size = TRI . getMinimalPhysRegClass ( * R ) -> getSize ( ) ; Offset = alignTo ( Offset + Size , Size ) ; } unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; assert ( ! MFI -> getObjectIndexEnd ( ) || MaxAlign ) ; for ( unsigned I = 0 , E = MFI -> getObjectIndexEnd ( ) ; I != E ; ++ I ) Offset = alignTo ( Offset + MFI -> getObjectSize ( I ) , MaxAlign ) ; if ( MFI -> adjustsStack ( ) && hasReservedCallFrame ( MF ) ) Offset = alignTo ( Offset + MFI -> getMaxCallFrameSize ( ) , std :: max ( MaxAlign , getStackAlignment ( ) ) ) ; return alignTo ( Offset , getStackAlignment ( ) ) ; } </s>

Estimate and return the size of the stack frame .


<s> bool tilegx_bitfield_operand_p ( HOST_WIDE_INT n , int * first_bit , int * last_bit ) { int i ; if ( n == 0 ) return false ; for ( i = 0 ; i < 64 ; i ++ ) { unsigned HOST_WIDE_INT x = rotate_right ( n , i ) ; if ( ! ( x & 1 ) ) continue ; if ( ( x & ( x + 1 ) ) == 0 ) { if ( first_bit != NULL ) * first_bit = i ; if ( last_bit != NULL ) * last_bit = ( i + exact_log2 ( x ^ ( x >> 1 ) ) ) & 63 ; return true ; } } return false ; } </s>

Return true iff n contains exactly one contiguous sequence of 1 bits , possibly wrapping around from high bits to low bits .


"NVPTX optimize redundant cvta.to.local instruction"


<s> bool supportSplitCSR ( MachineFunction * MF ) const override { return MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: CXX_FAST_TLS && MF -> getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) ; } </s>

Return true if the target supports that a subset of CSRs for the given machine function is handled explicitly via copies .


<s> const LegalizerInfo * getLegalizerInfo ( ) const override { return Legalizer . get ( ) ; } </s>

Expose LegalizerInfo so the clients can re-use .


<s> void WebAssemblyFrameLowering :: writeSPToGlobal ( unsigned SrcReg , MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & InsertStore , const DebugLoc & DL ) const { const auto * TII = MF . getSubtarget < WebAssemblySubtarget > ( ) . getInstrInfo ( ) ; const char * ES = "__stack_pointer" ; auto * SPSymbol = MF . createExternalSymbolName ( ES ) ; BuildMI ( MBB , InsertStore , DL , TII -> get ( WebAssembly :: SET_GLOBAL_I32 ) ) . addExternalSymbol ( SPSymbol , WebAssemblyII :: MO_SYMBOL_GLOBAL ) . addReg ( SrcReg ) ; } </s>

Write SP back to __stack_pointer global .


<s> bool SPIRVBasicBlockDominance :: runOnFunction ( Function & F ) { DominatorTree & DT = getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; SmallVector < BasicBlock * , 16 > newBBOrder ; bool changedOrder = false ; for ( auto & BB : F ) { bool inserted = false ; for ( unsigned i = 0 ; i < newBBOrder . size ( ) ; ++ i ) { if ( DT . dominates ( & BB , newBBOrder [ i ] ) ) { newBBOrder . insert ( newBBOrder . begin ( ) + i , & BB ) ; inserted = true ; changedOrder = true ; break ; } } if ( ! inserted ) { newBBOrder . push_back ( & BB ) ; } } if ( changedOrder ) { for ( auto BB : newBBOrder ) { BB -> removeFromParent ( ) ; F . getBasicBlockList ( ) . push_back ( BB ) ; } } return changedOrder ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void TOYInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> const MCPhysReg * CSKYRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const CSKYSubtarget & STI = MF -> getSubtarget < CSKYSubtarget > ( ) ; if ( MF -> getFunction ( ) . hasFnAttribute ( "interrupt" ) ) { if ( STI . hasFPUv3DoubleFloat ( ) ) return CSR_GPR_FPR64v3_ISR_SaveList ; if ( STI . hasFPUv3SingleFloat ( ) ) return CSR_GPR_FPR32v3_ISR_SaveList ; if ( STI . hasFPUv2DoubleFloat ( ) ) return CSR_GPR_FPR64_ISR_SaveList ; if ( STI . hasFPUv2SingleFloat ( ) ) return CSR_GPR_FPR32_ISR_SaveList ; return CSR_GPR_ISR_SaveList ; } if ( STI . hasFPUv2DoubleFloat ( ) || STI . hasFPUv3DoubleFloat ( ) ) return CSR_GPR_FPR64_SaveList ; if ( STI . hasFPUv2SingleFloat ( ) || STI . hasFPUv3SingleFloat ( ) ) return CSR_GPR_FPR32_SaveList ; return CSR_I32_SaveList ; } </s>


<s> const TargetRegisterClass * getPointerRegClass ( unsigned Kind = 0 ) const { return & BF :: PRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> bool isMachineVerifierClean ( ) const override { return false ; } </s>

Returns true if the target is expected to pass all machine verifier checks .


<s> void riscv_split_doubleword_move ( rtx dest , rtx src ) { if ( ! TARGET_64BIT && TARGET_XTHEADFMV ) { if ( FP_REG_RTX_P ( dest ) ) { rtx low_src = riscv_subword ( src , false ) ; rtx high_src = riscv_subword ( src , true ) ; emit_insn ( gen_th_fmv_hw_w_x ( dest , high_src , low_src ) ) ; return ; } if ( FP_REG_RTX_P ( src ) ) { rtx low_dest = riscv_subword ( dest , false ) ; rtx high_dest = riscv_subword ( dest , true ) ; emit_insn ( gen_th_fmv_x_w ( low_dest , src ) ) ; emit_insn ( gen_th_fmv_x_hw ( high_dest , src ) ) ; return ; } } rtx low_dest = riscv_subword ( dest , false ) ; if ( REG_P ( low_dest ) && reg_overlap_mentioned_p ( low_dest , src ) ) { riscv_emit_move ( riscv_subword ( dest , true ) , riscv_subword ( src , true ) ) ; riscv_emit_move ( low_dest , riscv_subword ( src , false ) ) ; } else { riscv_emit_move ( low_dest , riscv_subword ( src , false ) ) ; riscv_emit_move ( riscv_subword ( dest , true ) , riscv_subword ( src , true ) ) ; } } </s>

Split a doubleword move from SRC to DEST . On 32-bit targets , this function handles 64-bit moves for which riscv_split_64bit_move_p holds . For 64-bit targets , this function handles 128-bit moves .


<s> SparcSubtarget & SparcSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { IsV9 = false ; IsLeon = false ; V8DeprecatedInsts = false ; IsVIS = false ; HasHardQuad = false ; UsePopc = false ; UseSoftFloat = false ; HasLeonCasa = false ; HasUmacSmac = false ; InsertNOPLoad = false ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? "v9" : "v8" ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( ! IsV9 ) UsePopc = false ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s>
void
AMDGPUPerfHint
::
runOnFunction
(
Function
&
F
)
{
if
(
FIM
.
find
(
&
F
)
!=
FIM
.
end
(
)
)
return
;
const
Module
&
M
=
*
F
.
getParent
(
)
;
DL
=
&
M
.
getDataLayout
(
)
;
visit
(
F
)
;
auto
Loc
=
FIM
.
find
(
&
F
)
;
assert
(
Loc
!=
FIM
.
end
(
)
&&
"No func info"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
F
.
getName
(
)
<<
" MemInst: "
<<
Loc
->
second
.
MemInstCount
<<
'\n'
<<
" IAMInst: "
<<
Loc
->
second
.
IAMInstCount
<<
'\n'
<<
" LSMInst: "
<<
Loc
->
second
.
LSMInstCount
<<
'\n'
<<
" TotalInst: "
<<
Loc
->
second
.
InstCount
<<
'\n'
)
;
auto
&
FI
=
Loc
->
second
;
if
(
isMemBound
(
FI
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
F
.
getName
(
)
<<
" is memory bound\n"
)
;
NumMemBound
++
;
}
if
(
AMDGPU
::
isEntryFunctionCC
(
F
.
getCallingConv
(
)
)
&&
needLimitWave
(
FI
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
F
.
getName
(
)
<<
" needs limit wave\n"
)
;
NumLimitWave
++
;
}
}
</s>

AMDGPU
AMDGPU
"No func info"
" MemInst: "
" IAMInst: "
" LSMInst: "
" TotalInst: "
" is memory bound\n"
AMDGPU::isEntryFunctionCC
" needs limit wave\n"


<s> static bool avr_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( regno == REG_CC ) return mode == CCmode ; if ( GET_MODE_SIZE ( mode ) == 1 ) return true ; if ( GET_MODE_SIZE ( mode ) >= 4 && regno >= REG_X ) return false ; return ! ( regno & 1 ) ; } </s>

Returns 1 if a value of mode MODE can be stored starting with hard register number REGNO . On the enhanced core , anything larger than 1 byte must start in even numbered register for `` movw '' to work ( this way we do n't have to check for odd registers everywhere ) .


<s> bool LEGPassConfig :: addPreISel ( ) { return false ; } </s>


<s> static unsigned int loongarch_build_integer ( struct loongarch_integer_op * codes , HOST_WIDE_INT value ) { unsigned int cost = 0 ; HOST_WIDE_INT low_part = TARGET_64BIT ? value << 32 >> 32 : value ; if ( IMM12_OPERAND ( low_part ) || IMM12_OPERAND_UNSIGNED ( low_part ) ) { codes [ 0 ] . code = UNKNOWN ; codes [ 0 ] . method = METHOD_NORMAL ; codes [ 0 ] . value = low_part ; cost ++ ; } else { codes [ 0 ] . code = UNKNOWN ; codes [ 0 ] . method = METHOD_NORMAL ; codes [ 0 ] . value = low_part & ~ ( IMM_REACH - 1 ) ; cost ++ ; HOST_WIDE_INT iorv = low_part & ( IMM_REACH - 1 ) ; if ( iorv != 0 ) { codes [ 1 ] . code = IOR ; codes [ 1 ] . method = METHOD_NORMAL ; codes [ 1 ] . value = iorv ; cost ++ ; } } if ( TARGET_64BIT ) { bool lu32i [ 2 ] = { ( value & LU32I_B ) == 0 , ( value & LU32I_B ) == LU32I_B } ; bool lu52i [ 2 ] = { ( value & LU52I_B ) == 0 , ( value & LU52I_B ) == LU52I_B } ; int sign31 = ( value & ( 1UL << 31 ) ) >> 31 ; if ( lu32i [ sign31 ] && lu52i [ sign31 ] ) return cost ; else if ( lu32i [ sign31 ] ) { codes [ cost ] . method = METHOD_LU52I ; codes [ cost ] . value = ( value >> 52 ) << 52 ; return cost + 1 ; } codes [ cost ] . method = METHOD_LU32I ; codes [ cost ] . value = ( ( value << 12 ) >> 44 ) << 32 ; cost ++ ; if ( ! lu52i [ ( value & ( 1ULL << 51 ) ) >> 51 ] ) { codes [ cost ] . method = METHOD_LU52I ; codes [ cost ] . value = ( value >> 52 ) << 52 ; cost ++ ; } } gcc_assert ( cost <= LARCH_MAX_INTEGER_OPS ) ; return cost ; } </s>

Fill CODES with a sequence of rtl operations to load VALUE . Return the number of operations needed .


<s> void tilepro_expand_set_const32 ( rtx op0 , rtx op1 ) { machine_mode mode = GET_MODE ( op0 ) ; rtx temp ; if ( CONST_INT_P ( op1 ) ) { expand_set_cint32 ( op0 , op1 ) ; } else { temp = create_temp_reg_if_possible ( mode , op0 ) ; emit_move_insn ( temp , gen_rtx_HIGH ( mode , op1 ) ) ; emit_move_insn ( op0 , gen_rtx_LO_SUM ( mode , temp , op1 ) ) ; } } </s>

Load OP1 , a 32-bit constant , into OP0 , a register . We know it ca n't be done in one insn when we get here , the move expander guarantees this .


"unexpected return calling convention register assignment"

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static bool ix86_fixed_condition_code_regs ( unsigned int * p1 , unsigned int * p2 ) { * p1 = FLAGS_REG ; * p2 = FPSR_REG ; return true ; } </s>

Return the fixed registers used for condition codes .


<s>
bool
RISCVInstrInfo
::
areMemAccessesTriviallyDisjoint
(
const
MachineInstr
&
MIa
,
const
MachineInstr
&
MIb
)
const
{
assert
(
MIa
.
mayLoadOrStore
(
)
&&
"MIa must be a load or store."
)
;
assert
(
MIb
.
mayLoadOrStore
(
)
&&
"MIb must be a load or store."
)
;
if
(
MIa
.
hasUnmodeledSideEffects
(
)
||
MIb
.
hasUnmodeledSideEffects
(
)
||
MIa
.
hasOrderedMemoryRef
(
)
||
MIb
.
hasOrderedMemoryRef
(
)
)
return
false
;
const
TargetRegisterInfo
*
TRI
=
STI
.
getRegisterInfo
(
)
;
const
MachineOperand
*
BaseOpA
=
nullptr
,
*
BaseOpB
=
nullptr
;
int64_t
OffsetA
=
0
,
OffsetB
=
0
;
unsigned
int
WidthA
=
0
,
WidthB
=
0
;
if
(
getMemOperandWithOffsetWidth
(
MIa
,
BaseOpA
,
OffsetA
,
WidthA
,
TRI
)
&&
getMemOperandWithOffsetWidth
(
MIb
,
BaseOpB
,
OffsetB
,
WidthB
,
TRI
)
)
{
if
(
BaseOpA
->
isIdenticalTo
(
*
BaseOpB
)
)
{
int
LowOffset
=
std
::
min
(
OffsetA
,
OffsetB
)
;
int
HighOffset
=
std
::
max
(
OffsetA
,
OffsetB
)
;
int
LowWidth
=
(
LowOffset
==
OffsetA
)
WidthA
:
WidthB
;
if
(
LowOffset
+
LowWidth
<=
HighOffset
)
return
true
;
}
}
return
false
;
}
</s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s>
Register
AVRTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
LLT
VT
,
const
MachineFunction
&
MF
)
const
{
Register
Reg
;
if
(
VT
==
LLT
::
scalar
(
8
)
)
{
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"r0"
,
AVR
::
R0
)
.
Case
(
"r1"
,
AVR
::
R1
)
.
Default
(
0
)
;
}
else
{
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"r0"
,
AVR
::
R1R0
)
.
Case
(
"sp"
,
AVR
::
SP
)
.
Default
(
0
)
;
}
if
(
Reg
)
return
Reg
;
report_fatal_error
(
Twine
(
"Invalid register name \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;
}
</s>

Return the register ID of the name passed in .


<s> unsigned ARM64InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case ARM64 :: STRWui : case ARM64 :: STRXui : case ARM64 :: STRBui : case ARM64 :: STRHui : case ARM64 :: STRSui : case ARM64 :: STRDui : case ARM64 :: STRQui : if ( MI -> getOperand ( 0 ) . getSubReg ( ) == 0 && MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"X86 Machine Code Emitter"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void MandarinFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const MandarinInstrInfo & TII = * static_cast < const MandarinInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr & MI = * I ; int Size = MI . getOperand ( 0 ) . getImm ( ) ; if ( Size ) { if ( MI . getOpcode ( ) == MD :: ADJCALLSTACKDOWN ) { BuildMI ( MF , MI . getDebugLoc ( ) , TII . get ( MD :: SUBri ) , MD :: R30 ) . addReg ( MD :: R30 ) . addImm ( Size ) ; } else { BuildMI ( MF , MI . getDebugLoc ( ) , TII . get ( MD :: ADDri ) , MD :: R30 ) . addReg ( MD :: R30 ) . addImm ( Size ) ; } } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> void ARMPassConfig :: addIRPasses ( ) { if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( TM ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( - 1 , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < ARMSubtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST . isThumb1Only ( ) ; } ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( TM ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> unsigned BlackfinInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case BF :: LOAD32fi : case BF :: LOAD16fi : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> rtx mips_expand_thread_pointer ( rtx tp ) { rtx fn ; if ( TARGET_MIPS16 ) { if ( ! mips16_rdhwr_stub ) mips16_rdhwr_stub = new mips16_rdhwr_one_only_stub ( ) ; fn = mips16_stub_call_address ( mips16_rdhwr_stub ) ; emit_insn ( PMODE_INSN ( gen_tls_get_tp_mips16 , ( tp , fn ) ) ) ; } else emit_insn ( PMODE_INSN ( gen_tls_get_tp , ( tp ) ) ) ; return tp ; } </s>

Return a pseudo register that contains the current thread pointer .