<s>
SDValue
TeakTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
)
const
{
if
(
isVarArg
)
{
report_fatal_error
(
"VarArg not supported"
)
;
}
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_Teak
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
<
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
{
RetOps
.
push_back
(
Flag
)
;
}
return
DAG
.
getNode
(
TeakISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s>
void
AMDGPUInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
DestReg
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
llvm_unreachable
(
"Not Implemented"
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s>
bool
RISCVInstrInfo
::
isBranchOffsetInRange
(
unsigned
BranchOp
,
int64_t
BrOffset
)
const
{
unsigned
XLen
=
STI
.
getXLen
(
)
;
switch
(
BranchOp
)
{
default
:
llvm_unreachable
(
"Unexpected opcode!"
)
;
case
RISCV
::
BEQ
:
case
RISCV
::
BNE
:
case
RISCV
::
BLT
:
case
RISCV
::
BGE
:
case
RISCV
::
BLTU
:
case
RISCV
::
BGEU
:
case
RISCV
::
CV_BEQIMM
:
case
RISCV
::
CV_BNEIMM
:
return
isIntN
(
13
,
BrOffset
)
;
case
RISCV
::
JAL
:
case
RISCV
::
PseudoBR
:
return
isIntN
(
21
,
BrOffset
)
;
case
RISCV
::
PseudoJump
:
return
isIntN
(
32
,
SignExtend64
(
BrOffset
+
0x800
,
XLen
)
)
;
case
RISCV
::
HwlpBranch
:
return
true
;
}
}
</s>

Determine if the branch target is in range .

RISCV
RISCV
"Unexpected opcode!"
RISCV::BEQ
RISCV::BNE
RISCV::BLT
RISCV::BGE
RISCV::BLTU
RISCV::BGEU
RISCV::CV_BEQIMM
RISCV::CV_BNEIMM
13
RISCV::JAL
RISCV::PseudoBR
21
RISCV::PseudoJump
32
0x800
RISCV::HwlpBranch


<s> static const TargetRegisterClass * getRegClass ( const MachineInstr & MI , Register Reg ) { if ( MI . getParent ( ) == nullptr ) return nullptr ; const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; return MF ? MF -> getRegInfo ( ) . getRegClassOrNull ( Reg ) : nullptr ; } </s>

Given a machine instruction descriptor , returns the register class constraint for OpNum , or NULL .


<s> unsigned AVRInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : { const MCInstrDesc & Desc = get ( Opcode ) ; return Desc . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return 0 ; case TargetOpcode :: INLINEASM : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const AVRTargetMachine & TM = static_cast < const AVRTargetMachine & > ( MF -> getTarget ( ) ) ; const TargetInstrInfo & TII = * TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ; return TII . getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> bool SystemZPassConfig :: addInstSelector ( ) { addPass ( createSystemZISelDag ( getSystemZTargetMachine ( ) , getOptLevel ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createSystemZLDCleanupPass ( getSystemZTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .

SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ


<s> void WebAssemblyFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { uint64_t StackSize = MF . getFrameInfo ( ) . getStackSize ( ) ; if ( ! needsSP ( MF ) || ! needsSPWriteback ( MF ) ) return ; auto & ST = MF . getSubtarget < WebAssemblySubtarget > ( ) ; const auto * TII = ST . getInstrInfo ( ) ; auto & MRI = MF . getRegInfo ( ) ; auto InsertPt = MBB . getFirstTerminator ( ) ; DebugLoc DL ; if ( InsertPt != MBB . end ( ) ) DL = InsertPt -> getDebugLoc ( ) ; unsigned SPReg = 0 ; unsigned SPFPReg = hasFP ( MF ) ? getFPReg ( MF ) : getSPReg ( MF ) ; if ( hasBP ( MF ) ) { auto FI = MF . getInfo < WebAssemblyFunctionInfo > ( ) ; SPReg = FI -> getBasePointerVreg ( ) ; } else if ( StackSize ) { const TargetRegisterClass * PtrRC = MRI . getTargetRegisterInfo ( ) -> getPointerRegClass ( MF ) ; Register OffsetReg = MRI . createVirtualRegister ( PtrRC ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( getOpcConst ( MF ) ) , OffsetReg ) . addImm ( StackSize ) ; SPReg = MRI . createVirtualRegister ( PtrRC ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( getOpcAdd ( MF ) ) , SPReg ) . addReg ( SPFPReg ) . addReg ( OffsetReg ) ; } else { SPReg = SPFPReg ; } writeSPToGlobal ( SPReg , MF , MBB , InsertPt , DL ) ; } </s>

WebAssembly WebAssembly WebAssembly 0 WebAssembly


<s> unsigned AMDGPUTargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const SelectionDAG & DAG , unsigned Depth ) const { switch ( Op . getOpcode ( ) ) { case AMDGPUISD :: BFE_I32 : { ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ; if ( ! Width ) return 1 ; unsigned SignBits = 32 - Width -> getZExtValue ( ) + 1 ; if ( ! isNullConstant ( Op . getOperand ( 1 ) ) ) return SignBits ; unsigned Op0SignBits = DAG . ComputeNumSignBits ( Op . getOperand ( 0 ) , Depth + 1 ) ; return std :: max ( SignBits , Op0SignBits ) ; } case AMDGPUISD :: BFE_U32 : { ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ; return Width ? 32 - ( Width -> getZExtValue ( ) & 0x1f ) : 1 ; } case AMDGPUISD :: CARRY : case AMDGPUISD :: BORROW : return 31 ; default : return 1 ; } } </s>

Determine the number of bits in the operation that are sign bits .


<s> void CJGInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; BuildMI ( MBB , MI , DL , get ( CJG :: PUSH ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> void ix86_function_specific_restore ( struct gcc_options * opts , struct gcc_options * , struct cl_target_option * ptr ) { enum processor_type old_tune = ix86_tune ; enum processor_type old_arch = ix86_arch ; unsigned HOST_WIDE_INT ix86_arch_mask ; int i ; opts -> x_flag_pic = flag_pic ; ix86_arch = ( enum processor_type ) ptr -> arch ; ix86_schedule = ( enum attr_cpu ) ptr -> schedule ; ix86_tune = ( enum processor_type ) ptr -> tune ; ix86_prefetch_sse = ptr -> prefetch_sse ; ix86_tune_defaulted = ptr -> tune_defaulted ; ix86_arch_specified = ptr -> arch_specified ; opts -> x_ix86_isa_flags_explicit = ptr -> x_ix86_isa_flags_explicit ; opts -> x_ix86_isa_flags2_explicit = ptr -> x_ix86_isa_flags2_explicit ; opts -> x_recip_mask_explicit = ptr -> x_recip_mask_explicit ; opts -> x_ix86_arch_string = ptr -> x_ix86_arch_string ; opts -> x_ix86_tune_string = ptr -> x_ix86_tune_string ; opts -> x_ix86_asm_dialect = ptr -> x_ix86_asm_dialect ; opts -> x_ix86_branch_cost = ptr -> x_ix86_branch_cost ; opts -> x_ix86_dump_tunes = ptr -> x_ix86_dump_tunes ; opts -> x_ix86_force_align_arg_pointer = ptr -> x_ix86_force_align_arg_pointer ; opts -> x_ix86_force_drap = ptr -> x_ix86_force_drap ; opts -> x_ix86_recip_name = ptr -> x_ix86_recip_name ; opts -> x_ix86_section_threshold = ptr -> x_ix86_section_threshold ; opts -> x_ix86_sse2avx = ptr -> x_ix86_sse2avx ; opts -> x_ix86_stack_protector_guard = ptr -> x_ix86_stack_protector_guard ; opts -> x_ix86_stringop_alg = ptr -> x_ix86_stringop_alg ; opts -> x_ix86_tls_dialect = ptr -> x_ix86_tls_dialect ; opts -> x_ix86_tune_ctrl_string = ptr -> x_ix86_tune_ctrl_string ; opts -> x_ix86_tune_memcpy_strategy = ptr -> x_ix86_tune_memcpy_strategy ; opts -> x_ix86_tune_memset_strategy = ptr -> x_ix86_tune_memset_strategy ; opts -> x_ix86_tune_no_default = ptr -> x_ix86_tune_no_default ; ix86_tune_cost = processor_cost_table [ ix86_tune ] ; if ( opts -> x_optimize_size ) ix86_cost = & ix86_size_cost ; else ix86_cost = ix86_tune_cost ; if ( old_arch != ix86_arch ) { ix86_arch_mask = HOST_WIDE_INT_1U << ix86_arch ; for ( i = 0 ; i < X86_ARCH_LAST ; ++ i ) ix86_arch_features [ i ] = ! ! ( initial_ix86_arch_features [ i ] & ix86_arch_mask ) ; } if ( old_tune != ix86_tune ) set_ix86_tune_features ( opts , ix86_tune , false ) ; } </s>


<s> static bool s390_match_ccmode_set ( rtx set , machine_mode req_mode ) { machine_mode set_mode ; gcc_assert ( GET_CODE ( set ) == SET ) ; gcc_assert ( req_mode != CCVIALLmode && req_mode != CCVIANYmode && req_mode != CCVFALLmode && req_mode != CCVFANYmode ) ; if ( GET_CODE ( SET_DEST ( set ) ) != REG || ! CC_REGNO_P ( REGNO ( SET_DEST ( set ) ) ) ) return 1 ; set_mode = GET_MODE ( SET_DEST ( set ) ) ; switch ( set_mode ) { case CCZ1mode : case CCSmode : case CCSRmode : case CCUmode : case CCURmode : case CCLmode : case CCL1mode : case CCL2mode : case CCL3mode : case CCT1mode : case CCT2mode : case CCT3mode : case CCVEQmode : case CCVIHmode : case CCVIHUmode : case CCVFHmode : case CCVFHEmode : if ( req_mode != set_mode ) return 0 ; break ; case CCZmode : if ( req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode && req_mode != CCSRmode && req_mode != CCURmode && req_mode != CCZ1mode ) return 0 ; break ; case CCAPmode : case CCANmode : if ( req_mode != CCAmode ) return 0 ; break ; default : gcc_unreachable ( ) ; } return ( GET_MODE ( SET_SRC ( set ) ) == set_mode ) ; } </s>

Return true if SET either does n't set the CC register , or else the source and destination have matching CC modes and that CC mode is at least as constrained as REQ_MODE .


<s>
static
uint32_t
getBranchTargetOpValue
(
const
MCInst
&
MI
,
unsigned
OpIdx
,
unsigned
FixupKind
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
{
const
MCOperand
&
MO
=
MI
.
getOperand
(
OpIdx
)
;
if
(
MO
.
isImm
(
)
)
return
MO
.
getImm
(
)
;
assert
(
MO
.
isExpr
(
)
&&
"Unexpected branch target type!"
)
;
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
MCFixupKind
Kind
=
MCFixupKind
(
FixupKind
)
;
Fixups
.
push_back
(
MCFixup
::
create
(
0
,
Expr
,
Kind
,
MI
.
getLoc
(
)
)
)
;
return
0
;
}
</s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s> size_t size ( ) { return Q . size ( ) + HaveConst ; } </s>

The number of name/type pairs is returned .


<s> rtx legitimize_pic_address ( rtx orig , machine_mode mode ATTRIBUTE_UNUSED , rtx reg ) { rtx pic_ref = orig ; if ( GET_CODE ( orig ) == SYMBOL_REF || GET_CODE ( orig ) == LABEL_REF ) { gcc_assert ( reg ) ; pic_ref = m68k_wrap_symbol_into_got_ref ( orig , RELOC_GOT , reg ) ; pic_ref = m68k_move_to_reg ( pic_ref , orig , reg ) ; } else if ( GET_CODE ( orig ) == CONST ) { rtx base ; if ( m68k_unwrap_symbol ( orig , true ) != orig ) return orig ; gcc_assert ( reg ) ; gcc_assert ( GET_CODE ( XEXP ( orig , 0 ) ) == PLUS ) ; base = legitimize_pic_address ( XEXP ( XEXP ( orig , 0 ) , 0 ) , Pmode , reg ) ; orig = legitimize_pic_address ( XEXP ( XEXP ( orig , 0 ) , 1 ) , Pmode , base == reg ? 0 : reg ) ; if ( GET_CODE ( orig ) == CONST_INT ) pic_ref = plus_constant ( Pmode , base , INTVAL ( orig ) ) ; else pic_ref = gen_rtx_PLUS ( Pmode , base , orig ) ; } return pic_ref ; } </s>

Legitimize PIC addresses . If the address is already position-independent , we return ORIG . Newly generated position-independent addresses go into a reg . This is REG if nonzero , otherwise we allocate register ( s ) as necessary .


<s>
SDValue
XCoreTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_XCore
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
RetOps
.
push_back
(
DAG
.
getConstant
(
0
,
MVT
::
i32
)
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
XCoreISD
::
RETSP
,
dl
,
MVT
::
Other
,
&
RetOps
[
0
]
,
RetOps
.
size
(
)
)
;
}
</s>


<s> static void rs6000_setup_reg_addr_masks ( void ) { ssize_t rc , reg , m , nregs ; addr_mask_type any_addr_mask , addr_mask ; for ( m = 0 ; m < NUM_MACHINE_MODES ; ++ m ) { machine_mode m2 = ( machine_mode ) m ; bool complex_p = false ; bool small_int_p = ( m2 == QImode || m2 == HImode || m2 == SImode ) ; size_t msize ; if ( COMPLEX_MODE_P ( m2 ) ) { complex_p = true ; m2 = GET_MODE_INNER ( m2 ) ; } msize = GET_MODE_SIZE ( m2 ) ; bool indexed_only_p = ( m == SDmode && TARGET_NO_SDMODE_STACK ) ; any_addr_mask = 0 ; for ( rc = FIRST_RELOAD_REG_CLASS ; rc <= LAST_RELOAD_REG_CLASS ; rc ++ ) { addr_mask = 0 ; reg = reload_reg_map [ rc ] . reg ; if ( reg >= 0 && rs6000_hard_regno_mode_ok_p [ m ] [ reg ] ) { bool small_int_vsx_p = ( small_int_p && ( rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX ) ) ; nregs = rs6000_hard_regno_nregs [ m ] [ reg ] ; addr_mask |= RELOAD_REG_VALID ; if ( small_int_vsx_p ) addr_mask |= RELOAD_REG_INDEXED ; else if ( nregs > 1 || m == BLKmode || complex_p ) addr_mask |= RELOAD_REG_MULTIPLE ; else addr_mask |= RELOAD_REG_INDEXED ; if ( TARGET_UPDATE && ( rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR ) && msize <= 8 && ! VECTOR_MODE_P ( m2 ) && ! FLOAT128_VECTOR_P ( m2 ) && ! complex_p && ! small_int_vsx_p && ( m2 != DFmode || ! TARGET_UPPER_REGS_DF ) && ( m2 != SFmode || ! TARGET_UPPER_REGS_SF ) && ! ( TARGET_E500_DOUBLE && msize == 8 ) ) { addr_mask |= RELOAD_REG_PRE_INCDEC ; switch ( m ) { default : addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; case E_DImode : if ( TARGET_POWERPC64 ) addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; case E_DFmode : case E_DDmode : if ( TARGET_DF_INSN ) addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; } } } if ( ( addr_mask != 0 ) && ! indexed_only_p && msize <= 8 && ( rc == RELOAD_REG_GPR || ( ( msize == 8 || m2 == SFmode ) && ( rc == RELOAD_REG_FPR || ( rc == RELOAD_REG_VMX && TARGET_P9_DFORM_SCALAR ) ) ) ) ) addr_mask |= RELOAD_REG_OFFSET ; else if ( ( addr_mask != 0 ) && ! indexed_only_p && msize == 16 && TARGET_P9_DFORM_VECTOR && ( ALTIVEC_OR_VSX_VECTOR_MODE ( m2 ) || ( m2 == TImode && TARGET_VSX_TIMODE ) ) ) { addr_mask |= RELOAD_REG_OFFSET ; if ( rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX ) addr_mask |= RELOAD_REG_QUAD_OFFSET ; } if ( rc == RELOAD_REG_VMX && msize == 16 && ( addr_mask & RELOAD_REG_VALID ) != 0 ) addr_mask |= RELOAD_REG_AND_M16 ; reg_addr [ m ] . addr_mask [ rc ] = addr_mask ; any_addr_mask |= addr_mask ; } reg_addr [ m ] . addr_mask [ RELOAD_REG_ANY ] = any_addr_mask ; } } </s>

Update the addr mask bits in reg_addr to help secondary reload and go if legitimate address support to figure out the appropriate addressing to use .


<s> void rx_split_cbranch ( machine_mode cc_mode , enum rtx_code cmp1 , rtx c1 , rtx c2 , rtx label ) { rtx flags , x ; flags = gen_rtx_REG ( cc_mode , CC_REG ) ; x = gen_rtx_COMPARE ( cc_mode , c1 , c2 ) ; x = gen_rtx_SET ( VOIDmode , flags , x ) ; emit_insn ( x ) ; x = gen_rtx_fmt_ee ( cmp1 , VOIDmode , flags , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , label , pc_rtx ) ; x = gen_rtx_SET ( VOIDmode , pc_rtx , x ) ; emit_jump_insn ( x ) ; } </s>

Split the conditional branch . Emit ( COMPARE C1 C2 ) into CC_REG with CC_MODE , and use that in branches based on that compare .


<s> bool PPCPassConfig :: addPreISel ( ) { if ( ! DisableInstrFormPrep && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCLoopInstrFormPrepPass ( getPPCTargetMachine ( ) ) ) ; if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createHardwareLoopsPass ( ) ) ; return false ; } </s>


<s> bool arc_need_delay ( rtx_insn * insn ) { rtx_insn * next ; if ( ! flag_delayed_branch ) return false ; if ( NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == USE && ( ! ( next = next_active_insn ( insn ) ) || ( ( ! NONJUMP_INSN_P ( next ) || GET_CODE ( PATTERN ( next ) ) != SEQUENCE ) && arc_attr_type ( next ) == TYPE_RETURN ) ) && ( ! TARGET_PAD_RETURN || ( prev_active_insn ( insn ) && prev_active_insn ( prev_active_insn ( insn ) ) && prev_active_insn ( prev_active_insn ( prev_active_insn ( insn ) ) ) ) ) ) return true ; if ( NONJUMP_INSN_P ( insn ) ? ( GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER || GET_CODE ( PATTERN ( insn ) ) == SEQUENCE ) : JUMP_P ( insn ) ? ( GET_CODE ( PATTERN ( insn ) ) == ADDR_VEC || GET_CODE ( PATTERN ( insn ) ) == ADDR_DIFF_VEC ) : ! CALL_P ( insn ) ) return false ; return num_delay_slots ( insn ) != 0 ; } </s>

Return true if INSN is an instruction with a delay slot we may want to fill .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"SI Lower i1 Copies"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool WebAssemblyAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { return AsmPrinter :: PrintAsmMemoryOperand ( MI , OpNo , ExtraCode , OS ) ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> bool aarch64_gimple_fold_builtin ( gimple_stmt_iterator * gsi ) { bool changed = false ; gimple stmt = gsi_stmt ( * gsi ) ; tree call = gimple_call_fn ( stmt ) ; tree fndecl ; gimple new_stmt = NULL ; if ( call ) { fndecl = gimple_call_fndecl ( stmt ) ; if ( fndecl ) { int fcode = DECL_FUNCTION_CODE ( fndecl ) ; int nargs = gimple_call_num_args ( stmt ) ; tree * args = ( nargs > 0 ? gimple_call_arg_ptr ( stmt , 0 ) : & error_mark_node ) ; switch ( fcode ) { BUILTIN_VALL ( UNOP , reduc_plus_scal_ , 10 ) new_stmt = gimple_build_assign ( gimple_call_lhs ( stmt ) , REDUC_PLUS_EXPR , args [ 0 ] ) ; break ; BUILTIN_VDQIF ( UNOP , reduc_smax_scal_ , 10 ) BUILTIN_VDQ_BHSI ( UNOPU , reduc_umax_scal_ , 10 ) new_stmt = gimple_build_assign ( gimple_call_lhs ( stmt ) , REDUC_MAX_EXPR , args [ 0 ] ) ; break ; BUILTIN_VDQIF ( UNOP , reduc_smin_scal_ , 10 ) BUILTIN_VDQ_BHSI ( UNOPU , reduc_umin_scal_ , 10 ) new_stmt = gimple_build_assign ( gimple_call_lhs ( stmt ) , REDUC_MIN_EXPR , args [ 0 ] ) ; break ; default : break ; } } } if ( new_stmt ) { gsi_replace ( gsi , new_stmt , true ) ; changed = true ; } return changed ; } </s>


<s> bool MSP430PassConfig :: addPreEmitPass ( ) { PM . add ( createMSP430BranchSelectionPass ( ) ) ; return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> unsigned RISCVInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : { return get ( Opcode ) . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return 0 ; case TargetOpcode :: INLINEASM : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const auto & TM = static_cast < const RISCVTargetMachine & > ( MF . getTarget ( ) ) ; return getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } } } </s>


<s> static bool s390_function_arg_vector ( machine_mode mode , const_tree type ) { if ( ! TARGET_VX_ABI ) return false ; if ( s390_function_arg_size ( mode , type ) > 16 ) return false ; if ( ! type ) return VECTOR_MODE_P ( mode ) ; if ( ! s390_single_field_struct_p ( VECTOR_TYPE , type , true ) ) return false ; return true ; } </s>

Return true if a function argument of type TYPE and mode MODE is to be passed in a vector register , if available .


<s> const MCExpr * getSubExpr ( ) const { return Expr ; } </s>

getSubExpr - Get the child of this expression .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> unsigned char M680x0Subtarget :: classifyBlockAddressReference ( ) const { return M680x0II :: MO_PC_RELATIVE_ADDRESS ; } </s>

Classify a blockaddress reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s>
const
char
*
MipsAsmPrinter
::
getCurrentABIString
(
)
const
{
switch
(
Subtarget
->
getTargetABI
(
)
)
{
case
MipsSubtarget
::
O32
:
return
"abi32"
;
case
MipsSubtarget
::
O64
:
return
"abiO64"
;
case
MipsSubtarget
::
N32
:
return
"abiN32"
;
case
MipsSubtarget
::
N64
:
return
"abi64"
;
case
MipsSubtarget
::
EABI
:
return
"eabi32"
;
default
:
break
;
}
llvm_unreachable
(
"Unknown Mips ABI"
)
;
return
;
}
</s>


<s>
static
void
output_init_frag
(
rtx
sym
)
{
fprintf
(
asm_out_file
,
init_frag
.
started
", "
:
" = { "
)
;
unsigned
HOST_WIDE_INT
val
=
init_frag
.
val
;
init_frag
.
started
=
true
;
init_frag
.
val
=
0
;
init_frag
.
offset
=
0
;
init_frag
.
remaining
;
if
(
sym
)
{
fprintf
(
asm_out_file
,
"generic("
)
;
output_address
(
VOIDmode
,
sym
)
;
fprintf
(
asm_out_file
,
val
") + "
:
")"
)
;
}
if
(
!
sym
||
val
)
fprintf
(
asm_out_file
,
HOST_WIDE_INT_PRINT_DEC
,
val
)
;
}
</s>

The current fragment is full , write it out . SYM may provide a symbolic reference we should output , in which case the fragment value is the addend .


<s> void SystemZInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> SDValue XCoreTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; DebugLoc dl = N -> getDebugLoc ( ) ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: STORE : { StoreSDNode * ST = cast < StoreSDNode > ( N ) ; if ( ! DCI . isBeforeLegalize ( ) || allowsUnalignedMemoryAccesses ( ST -> getMemoryVT ( ) ) || ST -> isVolatile ( ) || ST -> isIndexed ( ) ) { break ; } SDValue Chain = ST -> getChain ( ) ; unsigned StoreBits = ST -> getMemoryVT ( ) . getStoreSizeInBits ( ) ; if ( StoreBits % 8 ) { break ; } unsigned ABIAlignment = getTargetData ( ) -> getABITypeAlignment ( ST -> getMemoryVT ( ) . getTypeForEVT ( * DCI . DAG . getContext ( ) ) ) ; unsigned Alignment = ST -> getAlignment ( ) ; if ( Alignment >= ABIAlignment ) { break ; } if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( ST -> getValue ( ) ) ) { if ( LD -> hasNUsesOfValue ( 1 , 0 ) && ST -> getMemoryVT ( ) == LD -> getMemoryVT ( ) && LD -> getAlignment ( ) == Alignment && ! LD -> isVolatile ( ) && ! LD -> isIndexed ( ) && Chain . reachesChainWithoutSideEffects ( SDValue ( LD , 1 ) ) ) { return DAG . getMemmove ( Chain , dl , ST -> getBasePtr ( ) , LD -> getBasePtr ( ) , DAG . getConstant ( StoreBits / 8 , MVT :: i32 ) , Alignment , ST -> getSrcValue ( ) , ST -> getSrcValueOffset ( ) , LD -> getSrcValue ( ) , LD -> getSrcValueOffset ( ) ) ; } } break ; } } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> virtual unsigned getByValTypeAlignment ( Type * Ty ) const LLVM_OVERRIDE { return 4 ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


<s> void HexagonFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned TargetAlign = MF . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = RoundUpToAlignment ( maxCallFrameSize , TargetAlign ) ; MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = RoundUpToAlignment ( FrameSize , TargetAlign ) ; MFI -> setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s> static void rs6000_darwin64_record_arg_flush ( CUMULATIVE_ARGS * cum , HOST_WIDE_INT bitpos , rtx rvec [ ] , int * k ) { machine_mode mode ; unsigned int regno ; unsigned int startbit , endbit ; int this_regno , intregs , intoffset ; rtx reg ; if ( cum -> intoffset == - 1 ) return ; intoffset = cum -> intoffset ; cum -> intoffset = - 1 ; if ( intoffset % BITS_PER_WORD != 0 ) { unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD ; if ( ! int_mode_for_size ( bits , 0 ) . exists ( & mode ) ) { intoffset = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; mode = word_mode ; } } else mode = word_mode ; startbit = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; endbit = ROUND_UP ( bitpos , BITS_PER_WORD ) ; intregs = ( endbit - startbit ) / BITS_PER_WORD ; this_regno = cum -> words + intoffset / BITS_PER_WORD ; if ( intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno ) cum -> use_stack = 1 ; intregs = MIN ( intregs , GP_ARG_NUM_REG - this_regno ) ; if ( intregs <= 0 ) return ; intoffset /= BITS_PER_UNIT ; do { regno = GP_ARG_MIN_REG + this_regno ; reg = gen_rtx_REG ( mode , regno ) ; rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( intoffset ) ) ; this_regno += 1 ; intoffset = ( intoffset | ( UNITS_PER_WORD - 1 ) ) + 1 ; mode = word_mode ; intregs -= 1 ; } while ( intregs > 0 ) ; } </s>

A subroutine of rs6000_darwin64_record_arg . Assign the bits of the structure between cum- > intoffset and bitpos to integer registers .


<s>
void
ARMTargetLowering
::
emitLeadingFence
(
IRBuilder
<
>
&
Builder
,
AtomicOrdering
Ord
,
bool
IsStore
,
bool
IsLoad
)
const
{
if
(
!
getInsertFencesForAtomic
(
)
)
return
;
switch
(
Ord
)
{
case
NotAtomic
:
case
Unordered
:
llvm_unreachable
(
"Invalid fence: unordered/non-atomic"
)
;
case
Monotonic
:
case
Acquire
:
return
;
case
SequentiallyConsistent
:
if
(
!
IsStore
)
return
;
case
Release
:
case
AcquireRelease
:
if
(
Subtarget
->
isSwift
(
)
)
makeDMB
(
Builder
,
ARM_MB
::
ISHST
)
;
else
makeDMB
(
Builder
,
ARM_MB
::
ISH
)
;
return
;
}
}
</s>


<s>
bool
AArch64InstrInfo
::
isFPRCopy
(
const
MachineInstr
&
MI
)
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
TargetOpcode
::
COPY
:
{
unsigned
DstReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
return
(
AArch64
::
FPR64RegClass
.
contains
(
DstReg
)
||
AArch64
::
FPR128RegClass
.
contains
(
DstReg
)
)
;
}
case
AArch64
::
ORRv16i8
:
if
(
MI
.
getOperand
(
1
)
.
getReg
(
)
==
MI
.
getOperand
(
2
)
.
getReg
(
)
)
{
assert
(
MI
.
getDesc
(
)
.
getNumOperands
(
)
==
3
&&
MI
.
getOperand
(
0
)
.
isReg
(
)
&&
"invalid ORRv16i8 operands"
)
;
return
true
;
}
break
;
}
return
false
;
}
</s>

Does this instruction rename an FPR without modifying bits ?


<s> bool arc_is_shortcall_p ( rtx sym_ref ) { if ( GET_CODE ( sym_ref ) != SYMBOL_REF ) return false ; return ( SYMBOL_REF_SHORT_CALL_P ( sym_ref ) || ( ! TARGET_LONG_CALLS_SET && ! TARGET_MEDIUM_CALLS && ! SYMBOL_REF_LONG_CALL_P ( sym_ref ) && ! SYMBOL_REF_MEDIUM_CALL_P ( sym_ref ) ) ) ; } </s>


<s> void arc_print_operand_address ( FILE * file , rtx addr ) { rtx base , index = 0 ; switch ( GET_CODE ( addr ) ) { case REG : fputs ( reg_names [ REGNO ( addr ) ] , file ) ; break ; case SYMBOL_REF : if ( output_sdata ) fputs ( "gp," , file ) ; output_addr_const ( file , addr ) ; if ( output_sdata ) fputs ( "@sda" , file ) ; output_sdata = 0 ; break ; case PLUS : if ( GET_CODE ( XEXP ( addr , 0 ) ) == MULT ) index = XEXP ( XEXP ( addr , 0 ) , 0 ) , base = XEXP ( addr , 1 ) ; else if ( CONST_INT_P ( XEXP ( addr , 0 ) ) ) index = XEXP ( addr , 0 ) , base = XEXP ( addr , 1 ) ; else base = XEXP ( addr , 0 ) , index = XEXP ( addr , 1 ) ; gcc_assert ( OBJECT_P ( base ) ) ; arc_print_operand_address ( file , base ) ; if ( CONSTANT_P ( base ) && CONST_INT_P ( index ) ) fputc ( '+' , file ) ; else fputc ( ',' , file ) ; gcc_assert ( OBJECT_P ( index ) ) ; arc_print_operand_address ( file , index ) ; break ; case CONST : { rtx c = XEXP ( addr , 0 ) ; if ( ( GET_CODE ( c ) == UNSPEC && ( XINT ( c , 1 ) == UNSPEC_TLS_OFF || XINT ( c , 1 ) == UNSPEC_TLS_IE ) ) || ( GET_CODE ( c ) == PLUS && GET_CODE ( XEXP ( c , 0 ) ) == UNSPEC && ( XINT ( XEXP ( c , 0 ) , 1 ) == UNSPEC_TLS_OFF || XINT ( XEXP ( c , 0 ) , 1 ) == ARC_UNSPEC_GOTOFFPC ) ) ) { arc_output_pic_addr_const ( file , c , 0 ) ; break ; } gcc_assert ( GET_CODE ( c ) == PLUS ) ; gcc_assert ( GET_CODE ( XEXP ( c , 0 ) ) == SYMBOL_REF ) ; gcc_assert ( GET_CODE ( XEXP ( c , 1 ) ) == CONST_INT ) ; output_address ( VOIDmode , XEXP ( addr , 0 ) ) ; break ; } case PRE_INC : case PRE_DEC : gcc_unreachable ( ) ; break ; default : if ( flag_pic ) arc_output_pic_addr_const ( file , addr , 0 ) ; else output_addr_const ( file , addr ) ; break ; } } </s>

Print a memory address as an operand to reference that memory location .


<s> void WebAssemblyExceptionInfo :: releaseMemory ( ) { BBMap . clear ( ) ; DeleteContainerPointers ( TopLevelExceptions ) ; TopLevelExceptions . clear ( ) ; } </s>

releaseMemory ( ) - This member can be implemented by a pass if it wants to be able to release its memory when it is no longer needed .


<s> bool ARMTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( Subtarget -> isThumb1Only ( ) ) return false ; EVT VT ; SDValue Ptr ; unsigned Align ; bool isSEXTLoad = false ; bool IsMasked = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; Align = LD -> getAlignment ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == ISD :: SEXTLOAD ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Align = ST -> getAlignment ( ) ; } else if ( MaskedLoadSDNode * LD = dyn_cast < MaskedLoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; Align = LD -> getAlignment ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == ISD :: SEXTLOAD ; IsMasked = true ; } else if ( MaskedStoreSDNode * ST = dyn_cast < MaskedStoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Align = ST -> getAlignment ( ) ; IsMasked = true ; } else return false ; bool isInc ; bool isLegal = false ; if ( VT . isVector ( ) ) isLegal = Subtarget -> hasMVEIntegerOps ( ) && getMVEIndexedAddressParts ( Ptr . getNode ( ) , VT , Align , isSEXTLoad , IsMasked , Subtarget -> isLittle ( ) , Base , Offset , isInc , DAG ) ; else { if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = getARMIndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; } if ( ! isLegal ) return false ; AM = isInc ? ISD :: PRE_INC : ISD :: PRE_DEC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .

ARM ARM ISD::MemIndexedMode ISD::SEXTLOAD ISD::SEXTLOAD ARM ISD::PRE_INC ISD::PRE_DEC


<s> bool isImm ( ) const override { return Kind == k_Immediate ; } </s>


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> static void mips_init_builtins ( void ) { const struct mips_builtin_description * d ; unsigned int i ; for ( i = 0 ; i < ARRAY_SIZE ( mips_builtins ) ; i ++ ) { d = & mips_builtins [ i ] ; if ( d -> avail ( ) ) { mips_builtin_decls [ i ] = add_builtin_function ( d -> name , mips_build_function_type ( d -> function_type ) , i , BUILT_IN_MD , NULL , NULL ) ; mips_get_builtin_decl_index [ d -> icode ] = i ; } } } </s>

Init builtin functions . This is called from TARGET_INIT_BUILTIN .


"Legal fp imm: materialize 0 using the zero register\n"

Returns true if the target can instruction select the specified FP immediate natively .


<s> bool MipsLongBranch :: runOnMachineFunction ( MachineFunction & F ) { const MipsSubtarget & STI = static_cast < const MipsSubtarget & > ( F . getSubtarget ( ) ) ; const MipsInstrInfo * TII = static_cast < const MipsInstrInfo * > ( STI . getInstrInfo ( ) ) ; LongBranchSeqSize = ! IsPIC ? 2 : ( ABI . IsN64 ( ) ? 10 : ( ! STI . isTargetNaCl ( ) ? 9 : 10 ) ) ; if ( STI . inMips16Mode ( ) || ! STI . enableLongBranchPass ( ) ) return false ; if ( IsPIC && static_cast < const MipsTargetMachine & > ( TM ) . getABI ( ) . IsO32 ( ) && F . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; int ShVal = STI . inMicroMipsMode ( ) ? 2 : 4 ; int64_t Offset = computeOffset ( I -> Br ) / ShVal ; if ( STI . isTargetNaCl ( ) ) { Offset *= 2 ; } if ( ! ForceLongBranch && isInt < 16 > ( Offset ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * 4 ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( IsPIC ) { uint64_t Address = 0 ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ; } for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) if ( I -> HasLongBranch ) expandToLongBranch ( * I ) ; MF -> RenumberBlocks ( ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


"predicated instruction in conditional sequence"

Print condition code to STREAM . Helper function for arm_print_operand .


<s> static void nvptx_output_barrier ( rtx * mem_operand , int memmodel , bool pre_p ) { bool post_p = ! pre_p ; switch ( memmodel ) { case MEMMODEL_RELAXED : return ; case MEMMODEL_CONSUME : case MEMMODEL_ACQUIRE : case MEMMODEL_SYNC_ACQUIRE : if ( post_p ) break ; return ; case MEMMODEL_RELEASE : case MEMMODEL_SYNC_RELEASE : if ( pre_p ) break ; return ; case MEMMODEL_ACQ_REL : case MEMMODEL_SEQ_CST : case MEMMODEL_SYNC_SEQ_CST : if ( pre_p || post_p ) break ; return ; default : gcc_unreachable ( ) ; } output_asm_insn ( "%.\tmembar%B0;" , mem_operand ) ; } </s>

Output a pre/post barrier for MEM_OPERAND according to MEMMODEL .


<s> static void s390_conditional_register_usage ( void ) { int i ; if ( flag_pic ) fixed_regs [ PIC_OFFSET_TABLE_REGNUM ] = 1 ; fixed_regs [ BASE_REGNUM ] = 0 ; fixed_regs [ RETURN_REGNUM ] = 0 ; if ( TARGET_64BIT ) { for ( i = FPR8_REGNUM ; i <= FPR15_REGNUM ; i ++ ) call_used_regs [ i ] = 0 ; } else { call_used_regs [ FPR4_REGNUM ] = 0 ; call_used_regs [ FPR6_REGNUM ] = 0 ; } if ( TARGET_SOFT_FLOAT ) { for ( i = FPR0_REGNUM ; i <= FPR15_REGNUM ; i ++ ) fixed_regs [ i ] = 1 ; } if ( ! TARGET_VX ) { for ( i = VR16_REGNUM ; i <= VR31_REGNUM ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 ; } } </s>


<s> void mips_expand_vec_reduc ( rtx target , rtx in , rtx ( * gen ) ( rtx , rtx , rtx ) ) { machine_mode vmode = GET_MODE ( in ) ; unsigned char perm2 [ 2 ] ; rtx last , next , fold , x ; bool ok ; last = in ; fold = gen_reg_rtx ( vmode ) ; switch ( vmode ) { case E_V2SFmode : perm2 [ 0 ] = 1 ; perm2 [ 1 ] = 2 ; ok = mips_expand_vselect_vconcat ( fold , last , last , perm2 , 2 ) ; gcc_assert ( ok ) ; break ; case E_V2SImode : emit_insn ( gen_loongson_punpckhwd ( fold , last , last ) ) ; break ; case E_V4HImode : emit_insn ( gen_loongson_punpckhwd_hi ( fold , last , last ) ) ; next = gen_reg_rtx ( vmode ) ; emit_insn ( gen ( next , last , fold ) ) ; last = next ; fold = gen_reg_rtx ( vmode ) ; x = force_reg ( SImode , GEN_INT ( 16 ) ) ; emit_insn ( gen_vec_shr_v4hi ( fold , last , x ) ) ; break ; case E_V8QImode : emit_insn ( gen_loongson_punpckhwd_qi ( fold , last , last ) ) ; next = gen_reg_rtx ( vmode ) ; emit_insn ( gen ( next , last , fold ) ) ; last = next ; fold = gen_reg_rtx ( vmode ) ; x = force_reg ( SImode , GEN_INT ( 16 ) ) ; emit_insn ( gen_vec_shr_v8qi ( fold , last , x ) ) ; next = gen_reg_rtx ( vmode ) ; emit_insn ( gen ( next , last , fold ) ) ; last = next ; fold = gen_reg_rtx ( vmode ) ; x = force_reg ( SImode , GEN_INT ( 8 ) ) ; emit_insn ( gen_vec_shr_v8qi ( fold , last , x ) ) ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( target , last , fold ) ) ; } </s>


<s> static void ix86_emit_restore_regs_using_mov ( HOST_WIDE_INT cfa_offset , bool maybe_eh_return ) { struct machine_function * m = cfun -> machine ; unsigned int regno ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ! SSE_REGNO_P ( regno ) && ix86_save_reg ( regno , maybe_eh_return ) ) { rtx reg = gen_rtx_REG ( word_mode , regno ) ; rtx insn , mem ; mem = choose_baseaddr ( cfa_offset ) ; mem = gen_frame_mem ( word_mode , mem ) ; insn = emit_move_insn ( reg , mem ) ; if ( m -> fs . cfa_reg == crtl -> drap_reg && regno == REGNO ( crtl -> drap_reg ) ) { add_reg_note ( insn , REG_CFA_DEF_CFA , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; m -> fs . drap_valid = true ; } else ix86_add_cfa_restore_note ( NULL_RTX , reg , cfa_offset ) ; cfa_offset -= UNITS_PER_WORD ; } } </s>

Emit code to restore saved registers using MOV insns . First register is restored from POINTER + OFFSET .


<s> static int ix86_function_regparm ( const_tree type , const_tree decl ) { tree attr ; int regparm ; unsigned int ccvt ; if ( TARGET_64BIT ) return ( ix86_function_type_abi ( type ) == SYSV_ABI ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX ) ; ccvt = ix86_get_callcvt ( type ) ; regparm = ix86_regparm ; if ( ( ccvt & IX86_CALLCVT_REGPARM ) != 0 ) { attr = lookup_attribute ( "regparm" , TYPE_ATTRIBUTES ( type ) ) ; if ( attr ) { regparm = TREE_INT_CST_LOW ( TREE_VALUE ( TREE_VALUE ( attr ) ) ) ; return regparm ; } } else if ( ( ccvt & IX86_CALLCVT_FASTCALL ) != 0 ) return 2 ; else if ( ( ccvt & IX86_CALLCVT_THISCALL ) != 0 ) return 1 ; if ( decl && TREE_CODE ( decl ) == FUNCTION_DECL ) { cgraph_node * target = cgraph_node :: get ( decl ) ; if ( target ) target = target -> function_symbol ( ) ; if ( target && opt_for_fn ( target -> decl , optimize ) && ! ( profile_flag && ! flag_fentry ) ) { cgraph_local_info * i = & target -> local ; if ( i && i -> local && i -> can_change_signature ) { int local_regparm , globals = 0 , regno ; for ( local_regparm = 0 ; local_regparm < REGPARM_MAX ; local_regparm ++ ) if ( fixed_regs [ local_regparm ] ) break ; if ( local_regparm == 3 && DECL_STATIC_CHAIN ( target -> decl ) ) local_regparm = 2 ; if ( flag_split_stack ) { if ( local_regparm == 3 ) local_regparm = 2 ; else if ( local_regparm == 2 && DECL_STATIC_CHAIN ( target -> decl ) ) local_regparm = 1 ; } for ( regno = AX_REG ; regno <= DI_REG ; regno ++ ) if ( fixed_regs [ regno ] ) globals ++ ; local_regparm = globals < local_regparm ? local_regparm - globals : 0 ; if ( local_regparm > regparm ) regparm = local_regparm ; } } } return regparm ; } </s>

Return the regparm value for a function with the indicated TYPE and DECL . DECL may be NULL when calling function indirectly or considering a libcall .


<s> std :: pair < EVT , EVT > AMDGPUTargetLowering :: getSplitDestVTs ( const EVT & VT , SelectionDAG & DAG ) const { EVT LoVT , HiVT ; EVT EltVT = VT . getVectorElementType ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned LoNumElts = PowerOf2Ceil ( ( NumElts + 1 ) / 2 ) ; LoVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , LoNumElts ) ; HiVT = NumElts - LoNumElts == 1 ? EltVT : EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , NumElts - LoNumElts ) ; return std :: make_pair ( LoVT , HiVT ) ; } </s>


<s> ScheduleHazardRecognizer :: HazardType GCNHazardRecognizer :: getHazardType ( SUnit * SU , int Stalls ) { MachineInstr * MI = SU -> getInstr ( ) ; if ( SIInstrInfo :: isSMRD ( * MI ) && checkSMRDHazards ( MI ) > 0 ) return NoopHazard ; if ( SIInstrInfo :: isVMEM ( * MI ) && checkVMEMHazards ( MI ) > 0 ) return NoopHazard ; if ( SIInstrInfo :: isVALU ( * MI ) && checkVALUHazards ( MI ) > 0 ) return NoopHazard ; if ( SIInstrInfo :: isDPP ( * MI ) && checkDPPHazards ( MI ) > 0 ) return NoopHazard ; if ( isDivFMas ( MI -> getOpcode ( ) ) && checkDivFMasHazards ( MI ) > 0 ) return NoopHazard ; if ( isRWLane ( MI -> getOpcode ( ) ) && checkRWLaneHazards ( MI ) > 0 ) return NoopHazard ; if ( isSGetReg ( MI -> getOpcode ( ) ) && checkGetRegHazards ( MI ) > 0 ) return NoopHazard ; if ( isSSetReg ( MI -> getOpcode ( ) ) && checkSetRegHazards ( MI ) > 0 ) return NoopHazard ; if ( isRFE ( MI -> getOpcode ( ) ) && checkRFEHazards ( MI ) > 0 ) return NoopHazard ; return NoHazard ; } </s>

getHazardType - Return the hazard type of emitting this node .


<s> bool SystemZInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumCyclesT , unsigned ExtraPredCyclesT , MachineBasicBlock & FMBB , unsigned NumCyclesF , unsigned ExtraPredCyclesF , BranchProbability Probability ) const { return false ; } </s>


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Dead register definitions"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"getRegForInlineAsmConstraint Unhandled data type"

"getRegForInlineAsmConstraint Unhandled vector size"

Given a physical register constraint ( e.g .


<s> static int ix86_register_move_cost ( machine_mode mode , reg_class_t class1_i , reg_class_t class2_i ) { enum reg_class class1 = ( enum reg_class ) class1_i ; enum reg_class class2 = ( enum reg_class ) class2_i ; if ( inline_secondary_memory_needed ( mode , class1 , class2 , false ) ) { int cost = 1 ; cost += inline_memory_move_cost ( mode , class1 , 2 ) ; cost += inline_memory_move_cost ( mode , class2 , 2 ) ; if ( GET_MODE_BITSIZE ( mode ) > BITS_PER_WORD && TARGET_MEMORY_MISMATCH_STALL && targetm . class_max_nregs ( class1 , mode ) > targetm . class_max_nregs ( class2 , mode ) ) cost += 20 ; if ( ( MMX_CLASS_P ( class1 ) && MAYBE_FLOAT_CLASS_P ( class2 ) ) || ( MMX_CLASS_P ( class2 ) && MAYBE_FLOAT_CLASS_P ( class1 ) ) ) cost += 20 ; return cost ; } if ( MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class2 ) ) gcc_unreachable ( ) ; if ( SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class2 ) ) return ( SSE_CLASS_P ( class1 ) ? ix86_cost -> hard_register . sse_to_integer : ix86_cost -> hard_register . integer_to_sse ) ; if ( MASK_CLASS_P ( class1 ) != MASK_CLASS_P ( class2 ) ) { return ( MASK_CLASS_P ( class1 ) ? ix86_cost -> hard_register . mask_to_integer : ix86_cost -> hard_register . integer_to_mask ) ; } if ( MASK_CLASS_P ( class1 ) && MASK_CLASS_P ( class2 ) ) return ix86_cost -> hard_register . mask_move ; if ( MAYBE_FLOAT_CLASS_P ( class1 ) ) return ix86_cost -> hard_register . fp_move ; if ( MAYBE_SSE_CLASS_P ( class1 ) ) { if ( GET_MODE_BITSIZE ( mode ) <= 128 ) return ix86_cost -> hard_register . xmm_move ; if ( GET_MODE_BITSIZE ( mode ) <= 256 ) return ix86_cost -> hard_register . ymm_move ; return ix86_cost -> hard_register . zmm_move ; } if ( MAYBE_MMX_CLASS_P ( class1 ) ) return ix86_cost -> hard_register . mmx_move ; return 2 ; } </s>

Return the cost of moving data from a register in class CLASS1 to one in class CLASS2 . It is not required that the cost always equal 2 when FROM is the same as TO ; on some machines it is expensive to move between registers if they are not general registers .


<s> static bool rs6000_output_addr_const_extra ( FILE * file , rtx x ) { if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , 1 ) ) { case UNSPEC_TOCREL : gcc_checking_assert ( SYMBOL_REF_P ( XVECEXP ( x , 0 , 0 ) ) && REG_P ( XVECEXP ( x , 0 , 1 ) ) && REGNO ( XVECEXP ( x , 0 , 1 ) ) == TOC_REGISTER ) ; output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; if ( x == tocrel_base_oac && tocrel_offset_oac != const0_rtx ) { if ( INTVAL ( tocrel_offset_oac ) >= 0 ) fprintf ( file , "+" ) ; output_addr_const ( file , CONST_CAST_RTX ( tocrel_offset_oac ) ) ; } if ( ! TARGET_AIX || ( TARGET_ELF && TARGET_MINIMAL_TOC ) ) { putc ( '-' , file ) ; assemble_name ( file , toc_label_name ) ; need_toc_init = 1 ; } else if ( TARGET_ELF ) fputs ( "@toc" , file ) ; return true ; case UNSPEC_MACHOPIC_OFFSET : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; putc ( '-' , file ) ; machopic_output_function_base_name ( file ) ; return true ; } return false ; } </s>


<s> bool HexagonInstrInfo :: isExtended ( const MachineInstr * MI ) const { const uint64_t F = MI -> getDesc ( ) . TSFlags ; if ( ( F >> HexagonII :: ExtendedPos ) & HexagonII :: ExtendedMask ) return true ; for ( MachineInstr :: const_mop_iterator I = MI -> operands_begin ( ) , E = MI -> operands_end ( ) ; I != E ; ++ I ) { if ( I -> getTargetFlags ( ) && HexagonII :: HMOTF_ConstExtended ) return true ; } return false ; } </s>

Test if the given EVT is extended ( as opposed to being simple ) .

Hexagon Hexagon HexagonII::ExtendedPos HexagonII::ExtendedMask HexagonII::HMOTF_ConstExtended


<s> void cr16_expand_prologue ( void ) { rtx insn ; cr16_compute_frame ( ) ; cr16_compute_save_regs ( ) ; if ( ( current_frame_info . total_size + current_frame_info . reg_size ) == 0 ) return ; if ( current_frame_info . last_reg_to_save != - 1 ) { insn = emit_insn ( gen_push_for_prologue ( GEN_INT ( current_frame_info . reg_size ) ) ) ; cr16_create_dwarf_for_multi_push ( insn ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } if ( current_frame_info . total_size > 0 ) { insn = emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - current_frame_info . total_size ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } if ( frame_pointer_needed ) { insn = emit_move_insn ( frame_pointer_rtx , stack_pointer_rtx ) ; } } </s>

CompactRISC CR16 Architecture stack layout : 0 + -- -- -- -- -- -- -- -- -- -- - | . . | +==================== Sp ( x ) = Ap ( x+1 ) A | Args for functions | | called by X and Dynamically | | Dynamic allocations allocated and | | ( alloca , variable deallocated Stack | length arrays ) . grows + -- -- -- -- -- -- -- -- -- -- Fp ( x ) down| | Local variables of X ward| + -- -- -- -- -- -- -- -- -- -- | | Regs saved for X-1 | +==================== Sp ( x-1 ) = Ap ( x ) | Args for func X | pushed by X-1 + -- -- -- -- -- -- -- -- -- -- Fp ( x-1 ) | | V


<s> bool SystemZInstrInfo :: isPredicable ( MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( STI . hasLoadStoreOnCond ( ) && getConditionalMove ( Opcode ) ) return true ; if ( Opcode == SystemZ :: Return || Opcode == SystemZ :: Trap || Opcode == SystemZ :: CallJG || Opcode == SystemZ :: CallBR ) return true ; return false ; } </s>

Return true if the specified instruction can be predicated .

SystemZ SystemZ SystemZ::Return SystemZ::Trap SystemZ::CallJG SystemZ::CallBR


<s> static void iq2000_option_override ( void ) { target_flags &= ~ MASK_GPOPT ; iq2000_isa = IQ2000_ISA_DEFAULT ; iq2000_print_operand_punct [ '?' ] = 1 ; iq2000_print_operand_punct [ '#' ] = 1 ; iq2000_print_operand_punct [ '&' ] = 1 ; iq2000_print_operand_punct [ '!' ] = 1 ; iq2000_print_operand_punct [ '*' ] = 1 ; iq2000_print_operand_punct [ '@' ] = 1 ; iq2000_print_operand_punct [ '.' ] = 1 ; iq2000_print_operand_punct [ '(' ] = 1 ; iq2000_print_operand_punct [ ')' ] = 1 ; iq2000_print_operand_punct [ '[' ] = 1 ; iq2000_print_operand_punct [ ']' ] = 1 ; iq2000_print_operand_punct [ '<' ] = 1 ; iq2000_print_operand_punct [ '>' ] = 1 ; iq2000_print_operand_punct [ '{' ] = 1 ; iq2000_print_operand_punct [ '}' ] = 1 ; iq2000_print_operand_punct [ '^' ] = 1 ; iq2000_print_operand_punct [ '$' ] = 1 ; iq2000_print_operand_punct [ '+' ] = 1 ; iq2000_print_operand_punct [ '~' ] = 1 ; gpr_mode = SImode ; init_machine_status = iq2000_init_machine_status ; } </s>


<s> static void expand_block_set_2 ( rtx dst , rtx dst_reg , rtx value_rtx , rtx bytes_rtx ) { const rtx sym = gen_rtx_SYMBOL_REF ( Pmode , "__wrd_memset" ) ; unsigned HOST_WIDE_INT bytes = UINTVAL ( bytes_rtx ) ; unsigned int rem = bytes % 2 ; value_rtx = convert_to_mode ( Pmode , value_rtx , 1 ) ; emit_library_call ( sym , LCT_NORMAL , VOIDmode , 3 , dst_reg , Pmode , value_rtx , Pmode , convert_to_mode ( TYPE_MODE ( sizetype ) , GEN_INT ( bytes >> 1 ) , TYPE_UNSIGNED ( sizetype ) ) , TYPE_MODE ( sizetype ) ) ; if ( rem == 0 ) return ; dst = replace_equiv_address_nv ( dst , dst_reg ) ; bytes -= rem ; emit_move_insn ( adjust_address_nv ( dst , QImode , bytes ) , convert_to_mode ( QImode , value_rtx , 1 ) ) ; } </s>

Generate a call to a library function to set BYTES_RTX bytes of DST with address DST_REG to VALUE_RTX in 2-byte chunks .


<s> bool useMachineCombiner ( ) const override { return true ; } </s>

Return true when a target supports MachineCombiner .


<s> size_t Mips64GOT :: getEntrySize ( ) const { return Mips64GOTEntry :: EntrySize ; } </s>

getEntrySize - Return the size of each entry in the jump table .


"Unexpected Kind in getPointerRegClass!"

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s>
unsigned
AVRInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
{
continue
;
}
if
(
I
->
getOpcode
(
)
!=
AVR
::
RJMPk
&&
getCondFromBranchOpc
(
I
->
getOpcode
(
)
)
==
AVRCC
::
COND_INVALID
)
{
break
;
}
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .

AVR
AVR
"code size not handled"
0
AVR::RJMPk
AVRCC::COND_INVALID


<s> static int ix86_nsaved_regs ( void ) { int nregs = 0 ; int regno ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ! SSE_REGNO_P ( regno ) && ix86_save_reg ( regno , true ) ) nregs ++ ; return nregs ; } </s>

Return number of registers to be saved on the stack .


<s> static void * rs6000_alloc_sched_context ( void ) { return xmalloc ( sizeof ( rs6000_sched_context_def ) ) ; } </s>

Allocate store for new scheduling context .


"a nested function is not supported for reduced registers"

"\t! This code fragment will be copied "

"\t! space for saving nested function address\n"


<s> EVT SystemZTargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> static std :: string toString ( const APFloat & FP ) { if ( FP . isNaN ( ) && ! FP . bitwiseIsEqual ( APFloat :: getQNaN ( FP . getSemantics ( ) ) ) && ! FP . bitwiseIsEqual ( APFloat :: getQNaN ( FP . getSemantics ( ) , true ) ) ) { APInt AI = FP . bitcastToAPInt ( ) ; return std :: string ( AI . isNegative ( ) ? "-" : "" ) + "nan:0x" + utohexstr ( AI . getZExtValue ( ) & ( AI . getBitWidth ( ) == 32 ? INT64_C ( 0x007fffff ) : INT64_C ( 0x000fffffffffffff ) ) , true ) ; } static const size_t BufBytes = 128 ; char buf [ BufBytes ] ; auto Written = FP . convertToHexString ( buf , 0 , false , APFloat :: rmNearestTiesToEven ) ; ( void ) Written ; assert ( Written != 0 ) ; assert ( Written < BufBytes ) ; return buf ; } </s>

Convert to a decimal representation in a string .


<s> int pru_can_use_return_insn ( void ) { if ( ! reload_completed || crtl -> profile ) return 0 ; return cfun -> machine -> total_size == 0 ; } </s>

Return nonzero if this function is known to have a null epilogue . This allows the optimizer to omit jumps to jumps if no stack was created .


<s> static inline bool mode_supports_pre_incdec_p ( machine_mode mode ) { return ( ( reg_addr [ mode ] . addr_mask [ RELOAD_REG_ANY ] & RELOAD_REG_PRE_INCDEC ) != 0 ) ; } </s>

Helper function to say whether a mode supports PRE_INC or PRE_DEC .


"MF used frame lowering for wrong subtarget"

Return true if the function has a redzone ( accessible bytes past the frame of the top of stack function ) as part of it 's ABI .


<s> bool AArch64TargetLowering :: isVectorLoadExtDesirable ( SDValue ExtVal ) const { return ExtVal . getValueType ( ) . isScalableVector ( ) || useSVEForFixedLengthVectorVT ( ExtVal . getValueType ( ) , Subtarget -> useSVEForFixedLengthVectors ( ) ) ; } </s>

Return true if folding a vector load into ExtVal ( a sign , zero , or any extend node ) is profitable .


<s> unsigned size ( ) const { return ( Packet . size ( ) ) ; } </s>

The number of name/type pairs is returned .


<s> std :: pair < unsigned , const TargetRegisterClass * > AArch64TargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & AArch64 :: GPR64commonRegClass ) ; return std :: make_pair ( 0U , & AArch64 :: GPR32commonRegClass ) ; case 'w' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , & AArch64 :: FPR32RegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & AArch64 :: FPR64RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & AArch64 :: FPR128RegClass ) ; break ; case 'x' : if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & AArch64 :: FPR128_loRegClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( AArch64 :: NZCV ) , & AArch64 :: CCRRegClass ) ; std :: pair < unsigned , const TargetRegisterClass * > Res ; Res = TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; if ( ! Res . second ) { unsigned Size = Constraint . size ( ) ; if ( ( Size == 4 || Size == 5 ) && Constraint [ 0 ] == '{' && tolower ( Constraint [ 1 ] ) == 'v' && Constraint [ Size - 1 ] == '}' ) { int RegNo ; bool Failed = Constraint . slice ( 2 , Size - 1 ) . getAsInteger ( 10 , RegNo ) ; if ( ! Failed && RegNo >= 0 && RegNo <= 31 ) { if ( VT != MVT :: Other && VT . getSizeInBits ( ) == 64 ) { Res . first = AArch64 :: FPR64RegClass . getRegister ( RegNo ) ; Res . second = & AArch64 :: FPR64RegClass ; } else { Res . first = AArch64 :: FPR128RegClass . getRegister ( RegNo ) ; Res . second = & AArch64 :: FPR128RegClass ; } } } } return Res ; } </s>

Given a physical register constraint ( e.g .


<s> const uint32_t * SparcRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return CSR_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> virtual const InstrItineraryData * getInstrItineraryData ( ) const { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> bool SIInstrInfo :: isReallyTriviallyReMaterializable ( const MachineInstr & MI , AAResults * AA ) const { switch ( MI . getOpcode ( ) ) { case AMDGPU :: V_MOV_B32_e32 : case AMDGPU :: V_MOV_B32_e64 : case AMDGPU :: V_MOV_B64_PSEUDO : case AMDGPU :: V_ACCVGPR_READ_B32_e64 : case AMDGPU :: V_ACCVGPR_WRITE_B32_e64 : return MI . getNumOperands ( ) == MI . getDesc ( ) . getNumOperands ( ) ; default : return false ; } } </s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> const uint32_t * LC3RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { return CC_Save_RegMask ; } </s>


<s>
void
NVPTXTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
switch
(
N
->
getOpcode
(
)
)
{
default
:
report_fatal_error
(
"Unhandled custom legalization"
)
;
case
ISD
::
LOAD
:
ReplaceLoadVector
(
N
,
DAG
,
Results
)
;
return
;
case
ISD
::
INTRINSIC_W_CHAIN
:
ReplaceINTRINSIC_W_CHAIN
(
N
,
DAG
,
Results
)
;
return
;
}
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

NVPTX
NVPTX
"Unhandled custom legalization"
ISD::LOAD
ISD::INTRINSIC_W_CHAIN


<s> bool arc_legitimate_pc_offset_p ( rtx addr ) { if ( GET_CODE ( addr ) != CONST ) return false ; return arc_needs_pcl_p ( addr ) ; } </s>

Return true if ADDR is an address that needs to be expressed as an explicit sum of pcl + offset .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"R600 Packetizer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static inline ChildIteratorType child_begin ( NodeRef N ) { return N -> G -> Edges . lower_bound ( N ) ; } </s>

nodes_iterator/begin/end - Allow iteration over all nodes in the graph


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


"CFProtection used on invalid architecture!"

This virtual method can be overridden by targets that want to emit something at the start of their file .


<s> static base_reg_disp sh_find_base_reg_disp ( rtx_insn * insn , rtx x , disp_t disp = 0 , rtx base_reg = NULL ) { if ( REG_P ( x ) ) { if ( REGNO ( x ) == GBR_REG ) return base_reg_disp ( x , disp ) ; if ( REGNO ( x ) < FIRST_PSEUDO_REGISTER ) return base_reg_disp ( base_reg != NULL ? base_reg : x , disp ) ; rtx_insn * last_i = NULL ; rtx last_set = NULL ; for ( df_ref d = DF_REG_DEF_CHAIN ( REGNO ( x ) ) ; d != NULL ; d = DF_REF_NEXT_REG ( d ) ) { rtx set = const_cast < rtx > ( set_of ( x , DF_REF_INSN ( d ) ) ) ; if ( last_set == NULL || rtx_equal_p ( last_set , set ) ) { last_i = DF_REF_INSN ( d ) ; last_set = set ; } else { last_i = NULL ; last_set = NULL ; break ; } } if ( last_set != NULL && last_i != NULL ) return sh_find_base_reg_disp ( last_i , XEXP ( last_set , 1 ) , disp , XEXP ( last_set , 0 ) ) ; return base_reg_disp ( x , disp ) ; } else if ( GET_CODE ( x ) == PLUS ) { base_reg_disp left_val = sh_find_base_reg_disp ( insn , XEXP ( x , 0 ) ) ; base_reg_disp right_val = sh_find_base_reg_disp ( insn , XEXP ( x , 1 ) ) ; if ( left_val . is_reg ( ) && right_val . is_disp ( ) ) return base_reg_disp ( left_val . reg ( ) , left_val . disp ( ) + right_val . disp ( ) + disp ) ; else if ( right_val . is_reg ( ) && left_val . is_disp ( ) ) return base_reg_disp ( right_val . reg ( ) , right_val . disp ( ) + left_val . disp ( ) + disp ) ; else return base_reg_disp ( base_reg , disp ) ; } else if ( CONST_INT_P ( x ) ) return base_reg_disp ( NULL , disp + INTVAL ( x ) ) ; return base_reg_disp ( base_reg , disp ) ; } </s>

Find the base register and calculate the displacement for a given address rtx ' x ' .


<s> unsigned TPCInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { case TPC :: SPILL_ARF_SAVE : case TPC :: SPILL_DRF_SAVE : case TPC :: SPILL_VRF_SAVE : case TPC :: SPILL_VPRF_SAVE : case TPC :: SPILL_IRF_SAVE : case TPC :: SPILL_SRF_SAVE : case TPC :: SPILL_ZRF_SAVE : case TPC :: SPILL_SPRF_SAVE : FrameIndex = MI . getOperand ( 0 ) . getIndex ( ) ; return MI . getOperand ( 1 ) . getReg ( ) ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> bool MipsSEInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock & MBB = * MI -> getParent ( ) ; switch ( MI -> getDesc ( ) . getOpcode ( ) ) { default : return false ; case Mips :: RetRA : expandRetRA ( MBB , MI ) ; break ; case Mips :: BuildPairF64 : expandBuildPairF64 ( MBB , MI , false ) ; break ; case Mips :: ExtractElementF64 : expandExtractElementF64 ( MBB , MI , false ) ; break ; case Mips :: MIPSeh_return32 : case Mips :: MIPSeh_return64 : expandEhReturn ( MBB , MI ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> static bool read_vl_insn_p ( rtx_insn * rinsn ) { return recog_memoized ( rinsn ) >= 0 && get_attr_type ( rinsn ) == TYPE_RDVL ; } </s>

Return true if the instruction is read vl instruction .


<s>
void
ARMConstantPoolValue
::
dump
(
)
const
{
cerr
<<
"  "
<<
*
this
;
}
</s>

Dump the plan to stderr ( for debugging ) .


<s> static bool mmix_function_value_regno_p ( const unsigned int regno ) { return regno == MMIX_RETURN_VALUE_REGNUM ; } </s>


<s> static reg_class_t aarch64_ira_change_pseudo_allocno_class ( int regno , reg_class_t allocno_class , reg_class_t best_class ) { enum machine_mode mode ; if ( allocno_class != ALL_REGS ) return allocno_class ; if ( best_class != ALL_REGS ) return best_class ; mode = PSEUDO_REGNO_MODE ( regno ) ; return FLOAT_MODE_P ( mode ) || VECTOR_MODE_P ( mode ) ? FP_REGS : GENERAL_REGS ; } </s>

Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS . The register allocator chooses ALL_REGS if FP_REGS and GENERAL_REGS have the same cost even if ALL_REGS has a much larger cost . ALL_REGS is also used if the cost of both FP_REGS and GENERAL_REGS is lower than the memory cost ( in this case the best class is the lowest cost one ) . Using ALL_REGS irrespectively of its cost results in bad allocations with many redundant int < - > FP moves which are expensive on various cores . To avoid this we do n't allow ALL_REGS as the allocno class , but force a decision between FP_REGS and GENERAL_REGS . We use the allocno class if it is n't ALL_REGS . Similarly , use the best class if it is n't ALL_REGS . Otherwise set the allocno class depending on the mode . The result of this is that it is no longer inefficient to have a higher memory move cost than the register move cost .


"List of x86 specific tuning parameter names:\n"

Helper function to set ix86_tune_features . IX86_TUNE is the processor type .


<s> bool DeadCodeElimination :: isDead ( unsigned R ) const { for ( auto I = MRI . use_begin ( R ) , E = MRI . use_end ( ) ; I != E ; ++ I ) { MachineInstr * UseI = I -> getParent ( ) ; if ( UseI -> isDebugValue ( ) ) continue ; if ( UseI -> isPHI ( ) ) { assert ( ! UseI -> getOperand ( 0 ) . getSubReg ( ) ) ; unsigned DR = UseI -> getOperand ( 0 ) . getReg ( ) ; if ( DR == R ) continue ; } return false ; } return true ; } </s>

isDead - Returns true if this is a dead def kill slot .


<s> static void maybe_clobber_cond ( rtx_insn * insn , int clock_var ) { int n , idx ; idx = ss . jump_cycle_index ; for ( n = 0 ; n < 12 ; n ++ , idx ++ ) { rtx cond , link ; int cycle ; if ( idx >= 12 ) idx -= 12 ; cycle = ss . jump_cycles [ idx ] ; if ( cycle <= clock_var ) return ; cond = ss . jump_cond [ idx ] ; if ( cond == NULL_RTX ) continue ; if ( CALL_P ( insn ) ) { ss . jump_cond [ idx ] = NULL_RTX ; continue ; } note_stores ( insn , clobber_cond_1 , ss . jump_cond + idx ) ; for ( link = REG_NOTES ( insn ) ; link ; link = XEXP ( link , 1 ) ) if ( REG_NOTE_KIND ( link ) == REG_INC ) clobber_cond_1 ( XEXP ( link , 0 ) , NULL_RTX , ss . jump_cond + idx ) ; } } </s>

Examine INSN , and if it destroys the conditions have recorded for any of the jumps in flight , clear that condition so that we do n't predicate any more insns . CLOCK_VAR helps us limit the search to only those jumps which are still in flight .


<s> static void rs6000_init_sched_context ( void * _sc , bool clean_p ) { rs6000_sched_context_t sc = ( rs6000_sched_context_t ) _sc ; if ( clean_p ) { sc -> cached_can_issue_more = 0 ; sc -> last_scheduled_insn = NULL_RTX ; sc -> load_store_pendulum = 0 ; } else { sc -> cached_can_issue_more = cached_can_issue_more ; sc -> last_scheduled_insn = last_scheduled_insn ; sc -> load_store_pendulum = load_store_pendulum ; } } </s>

If CLEAN_P is true then initializes _SC with clean data , and from the global context otherwise .


<s>
StringRef
getPassName
(
)
const
override
{
return
"WebAssembly Instruction Selection"
;
}
</s>

WebAssembly
"WebAssembly Instruction Selection"


<s>
SDValue
MipsSETargetLowering
::
PerformDAGCombine
(
SDNode
*
N
,
DAGCombinerInfo
&
DCI
)
const
{
SelectionDAG
&
DAG
=
DCI
.
DAG
;
SDValue
Val
;
switch
(
N
->
getOpcode
(
)
)
{
case
ISD
::
AND
:
Val
=
performANDCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
break
;
case
ISD
::
OR
:
Val
=
performORCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
break
;
case
ISD
::
MUL
:
return
performMULCombine
(
N
,
DAG
,
DCI
,
this
,
Subtarget
)
;
case
ISD
::
SHL
:
Val
=
performSHLCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
break
;
case
ISD
::
SRA
:
return
performSRACombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
case
ISD
::
SRL
:
return
performSRLCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
case
ISD
::
VSELECT
:
return
performVSELECTCombine
(
N
,
DAG
)
;
case
ISD
::
XOR
:
Val
=
performXORCombine
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SETCC
:
Val
=
performSETCCCombine
(
N
,
DAG
)
;
break
;
}
if
(
Val
.
getNode
(
)
)
{
DEBUG
(
dbgs
(
)
<<
"\nMipsSE DAG Combine:\n"
;
N
->
printrWithDepth
(
dbgs
(
)
,
&
DAG
)
;
dbgs
(
)
<<
"\n=> \n"
;
Val
.
getNode
(
)
->
printrWithDepth
(
dbgs
(
)
,
&
DAG
)
;
dbgs
(
)
<<
"\n"
)
;
return
Val
;
}
return
MipsTargetLowering
::
PerformDAGCombine
(
N
,
DCI
)
;
}
</s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips
Mips
ISD::AND
ISD::OR
ISD::MUL
ISD::SHL
ISD::SRA
ISD::SRL
ISD::VSELECT
ISD::XOR
ISD::SETCC
"\nMipsSE DAG Combine:\n"
"\n=> \n"
"\n"
Mips


<s> const AVRSubtarget * AVRTargetMachine :: getSubtargetImpl ( const Function & ) const { return & SubTarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool ARMSubtarget :: enableMachinePipeliner ( ) const { return getSchedModel ( ) . hasInstrSchedModel ( ) && useMachinePipeliner ( ) ; } </s>

True if the subtarget should run MachinePipeliner .


<s> bool XCoreFrameLowering :: hasFP ( const MachineFunction & MF ) const { return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool PPCRegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return requiresRegisterScavenging ( MF ) ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> void SITargetLowering :: finalizeLowering ( MachineFunction & MF ) const { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; SIMachineFunctionInfo * Info = MF . getInfo < SIMachineFunctionInfo > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; const SIRegisterInfo * TRI = ST . getRegisterInfo ( ) ; if ( Info -> isEntryFunction ( ) ) { reservePrivateMemoryRegs ( getTargetMachine ( ) , MF , * TRI , * Info ) ; } bool NeedSP = ! Info -> isEntryFunction ( ) || MFI . hasVarSizedObjects ( ) || MFI . hasCalls ( ) ; if ( NeedSP ) { unsigned ReservedStackPtrOffsetReg = TRI -> reservedStackPtrOffsetReg ( MF ) ; Info -> setStackPtrOffsetReg ( ReservedStackPtrOffsetReg ) ; assert ( Info -> getStackPtrOffsetReg ( ) != Info -> getFrameOffsetReg ( ) ) ; assert ( ! TRI -> isSubRegister ( Info -> getScratchRSrcReg ( ) , Info -> getStackPtrOffsetReg ( ) ) ) ; MRI . replaceRegWith ( AMDGPU :: SP_REG , Info -> getStackPtrOffsetReg ( ) ) ; } MRI . replaceRegWith ( AMDGPU :: PRIVATE_RSRC_REG , Info -> getScratchRSrcReg ( ) ) ; MRI . replaceRegWith ( AMDGPU :: FP_REG , Info -> getFrameOffsetReg ( ) ) ; MRI . replaceRegWith ( AMDGPU :: SCRATCH_WAVE_OFFSET_REG , Info -> getScratchWaveOffsetReg ( ) ) ; TargetLoweringBase :: finalizeLowering ( MF ) ; } </s>

Execute target specific actions to finalize target lowering .


<s> static bool avr_use_by_pieces_infrastructure_p ( unsigned HOST_WIDE_INT size , unsigned int align ATTRIBUTE_UNUSED , enum by_pieces_operation op , bool speed_p ) { if ( op != MOVE_BY_PIECES || ( speed_p && ( size > ( MOVE_MAX_PIECES ) ) ) ) return default_use_by_pieces_infrastructure_p ( size , align , op , speed_p ) ; return size <= ( MOVE_MAX_PIECES ) ; } </s>

Prefer sequence of loads/stores for moves of size upto two - two pairs of load/store instructions are always better than the 5 instruction sequence for a loop ( 1 instruction for loop counter setup , and 4 for the body of the loop ) .


<s> void X86InstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , unsigned SubIdx , const MachineInstr * Orig , const TargetRegisterInfo & TRI ) const { DebugLoc DL = Orig -> getDebugLoc ( ) ; bool Clone = true ; unsigned Opc = Orig -> getOpcode ( ) ; switch ( Opc ) { default : break ; case X86 :: MOV8r0 : case X86 :: MOV16r0 : case X86 :: MOV32r0 : case X86 :: MOV64r0 : { if ( ! isSafeToClobberEFLAGS ( MBB , I ) ) { switch ( Opc ) { default : llvm_unreachable ( "Unreachable!" ) ; case X86 :: MOV8r0 : Opc = X86 :: MOV8ri ; break ; case X86 :: MOV16r0 : Opc = X86 :: MOV16ri ; break ; case X86 :: MOV32r0 : Opc = X86 :: MOV32ri ; break ; case X86 :: MOV64r0 : Opc = X86 :: MOV64ri64i32 ; break ; } Clone = false ; } break ; } } if ( Clone ) { MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( Orig ) ; MBB . insert ( I , MI ) ; } else { BuildMI ( MBB , I , DL , get ( Opc ) ) . addOperand ( Orig -> getOperand ( 0 ) ) . addImm ( 0 ) ; } MachineInstr * NewMI = prior ( I ) ; NewMI -> substituteRegister ( Orig -> getOperand ( 0 ) . getReg ( ) , DestReg , SubIdx , TRI ) ; } </s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


Worker function for TARGET_ASM_CONSTRUCTOR .


<s> bool X86TargetLowering :: shouldExpandAtomicStoreInIR ( StoreInst * SI ) const { return needsCmpXchgNb ( SI -> getValueOperand ( ) -> getType ( ) ) ; } </s>

Returns how the given ( atomic ) store should be expanded by the IR-level AtomicExpand pass into .


<s> static void add_sched_insns_for_speculation ( void ) { rtx_insn * insn ; if ( ! ENABLE_WA_SPECULATIVE_LOADS && ! ENABLE_WA_SPECULATIVE_SYNCS && ! ENABLE_WA_INDIRECT_CALLS ) return ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { rtx pat ; if ( NOTE_P ( insn ) || BARRIER_P ( insn ) || LABEL_P ( insn ) ) continue ; if ( JUMP_TABLE_DATA_P ( insn ) ) continue ; pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == USE || GET_CODE ( pat ) == CLOBBER || GET_CODE ( pat ) == ASM_INPUT || asm_noperands ( pat ) >= 0 ) continue ; if ( JUMP_P ( insn ) ) { if ( any_condjump_p ( insn ) && ! cbranch_predicted_taken_p ( insn ) ) { rtx_insn * n = next_real_insn ( insn ) ; emit_insn_before ( gen_stall ( GEN_INT ( 3 ) ) , n ) ; } } } for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( JUMP_P ( insn ) && any_condjump_p ( insn ) && ( cbranch_predicted_taken_p ( insn ) ) ) { rtx target = JUMP_LABEL ( insn ) ; rtx_insn * next = next_real_insn ( target ) ; if ( GET_CODE ( PATTERN ( next ) ) == UNSPEC_VOLATILE && get_attr_type ( next ) == TYPE_STALL ) continue ; emit_insn_before ( gen_stall ( GEN_INT ( 1 ) ) , next ) ; } } } </s>

Called just before the final scheduling pass . If we need to insert NOPs later on to work around speculative loads , insert special placeholder insns that cause loads to be delayed for as many cycles as necessary ( and possible ) . This reduces the number of NOPs we need to add . The dummy insns we generate are later removed by bfin_gen_bundles .


"Blackfin intrinsics are not overloaded"

Create or insert an LLVM Function declaration for an intrinsic , and return it .


<s> unsigned HexagonTTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: TargetCostKind CostKind , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args , const Instruction * CxtI ) { if ( CostKind != TTI :: TCK_RecipThroughput ) return BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo , Args , CxtI ) ; if ( Ty -> isVectorTy ( ) ) { std :: pair < int , MVT > LT = TLI . getTypeLegalizationCost ( DL , Ty ) ; if ( LT . second . isFloatingPoint ( ) ) return LT . first + FloatFactor * getTypeNumElements ( Ty ) ; } return BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo , Args , CxtI ) ; } </s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> void aarch64_expand_sve_vcond ( machine_mode data_mode , machine_mode cmp_mode , rtx * ops ) { machine_mode pred_mode = aarch64_get_mask_mode ( GET_MODE_NUNITS ( cmp_mode ) , GET_MODE_SIZE ( cmp_mode ) ) . require ( ) ; rtx pred = gen_reg_rtx ( pred_mode ) ; if ( FLOAT_MODE_P ( cmp_mode ) ) { if ( aarch64_expand_sve_vec_cmp_float ( pred , GET_CODE ( ops [ 3 ] ) , ops [ 4 ] , ops [ 5 ] , true ) ) std :: swap ( ops [ 1 ] , ops [ 2 ] ) ; } else aarch64_expand_sve_vec_cmp_int ( pred , GET_CODE ( ops [ 3 ] ) , ops [ 4 ] , ops [ 5 ] ) ; rtvec vec = gen_rtvec ( 3 , pred , ops [ 1 ] , ops [ 2 ] ) ; emit_set_insn ( ops [ 0 ] , gen_rtx_UNSPEC ( data_mode , vec , UNSPEC_SEL ) ) ; } </s>

Expand an SVE vcond pattern with operands OPS . DATA_MODE is the mode of the data being selected and CMP_MODE is the mode of the values being compared .


<s>
rtx_code
m68k_output_compare_qi
(
rtx
op0
,
rtx
op1
,
rtx_code
code
)
{
rtx_code
tmp
=
m68k_find_flags_value
(
op0
,
op1
,
code
)
;
if
(
tmp
!=
UNKNOWN
)
return
tmp
;
remember_compare_flags
(
op0
,
op1
)
;
rtx
ops
[
2
]
;
ops
[
0
]
=
op0
;
ops
[
1
]
=
op1
;
if
(
op1
==
const0_rtx
)
output_asm_insn
(
"tst%.b %d0"
,
ops
)
;
else
if
(
GET_CODE
(
op0
)
==
MEM
&&
GET_CODE
(
op1
)
==
MEM
)
output_asm_insn
(
"cmpm%.b %1,%0"
,
ops
)
;
else
if
(
REG_P
(
op1
)
||
(
!
REG_P
(
op0
)
&&
GET_CODE
(
op0
)
!=
MEM
)
)
{
output_asm_insn
(
"cmp%.b %d0,%d1"
,
ops
)
;
std
::
swap
(
flags_compare_op0
,
flags_compare_op1
)
;
return
swap_condition
(
code
)
;
}
else
output_asm_insn
(
"cmp%.b %d1,%d0"
,
ops
)
;
return
code
;
}
</s>

Emit a comparison between OP0 and OP1 . CODE is the code of the comparison . It is returned , potentially modified if necessary .


<s> static bool fr30_must_pass_in_stack ( enum machine_mode mode , tree type ) { if ( mode == BLKmode ) return true ; if ( type == NULL ) return false ; return AGGREGATE_TYPE_P ( type ) ; } </s>

Return true if we should pass an argument on the stack rather than in registers .


<s> void s390_expand_vec_compare ( rtx target , enum rtx_code cond , rtx cmp_op1 , rtx cmp_op2 ) { machine_mode mode = GET_MODE ( target ) ; bool neg_p = false , swap_p = false ; rtx tmp ; if ( GET_MODE_CLASS ( GET_MODE ( cmp_op1 ) ) == MODE_VECTOR_FLOAT ) { switch ( cond ) { case NE : cond = EQ ; neg_p = true ; break ; case UNGT : cond = GE ; neg_p = true ; swap_p = true ; break ; case UNGE : cond = GT ; neg_p = true ; swap_p = true ; break ; case LE : cond = GE ; swap_p = true ; break ; case UNLE : cond = GT ; neg_p = true ; break ; case LT : cond = GT ; swap_p = true ; break ; case UNLT : cond = GE ; neg_p = true ; break ; case UNEQ : emit_insn ( gen_vec_cmpuneq ( target , cmp_op1 , cmp_op2 ) ) ; return ; case LTGT : emit_insn ( gen_vec_cmpltgt ( target , cmp_op1 , cmp_op2 ) ) ; return ; case ORDERED : emit_insn ( gen_vec_ordered ( target , cmp_op1 , cmp_op2 ) ) ; return ; case UNORDERED : emit_insn ( gen_vec_unordered ( target , cmp_op1 , cmp_op2 ) ) ; return ; default : break ; } } else { switch ( cond ) { case NE : cond = EQ ; neg_p = true ; break ; case GE : cond = GT ; neg_p = true ; swap_p = true ; break ; case GEU : cond = GTU ; neg_p = true ; swap_p = true ; break ; case LE : cond = GT ; neg_p = true ; break ; case LEU : cond = GTU ; neg_p = true ; break ; case LT : cond = GT ; swap_p = true ; break ; case LTU : cond = GTU ; swap_p = true ; break ; default : break ; } } if ( swap_p ) { tmp = cmp_op1 ; cmp_op1 = cmp_op2 ; cmp_op2 = tmp ; } emit_insn ( gen_rtx_SET ( target , gen_rtx_fmt_ee ( cond , mode , cmp_op1 , cmp_op2 ) ) ) ; if ( neg_p ) emit_insn ( gen_rtx_SET ( target , gen_rtx_NOT ( mode , target ) ) ) ; } </s>

Generate a vector comparison COND of CMP_OP1 and CMP_OP2 and store the result in TARGET .


<s> static HOST_WIDE_INT get_label_padding ( rtx label ) { HOST_WIDE_INT align , min_insn_size ; align = 1 << label_to_alignment ( label ) . levels [ 0 ] . log ; min_insn_size = TARGET_THUMB ? 2 : 4 ; return align > min_insn_size ? align - min_insn_size : 0 ; } </s>

Return the maximum amount of padding that will be inserted before label LABEL .


<s> static inline HOST_WIDE_INT htm_spr_regno ( enum rs6000_builtins code ) { if ( code == HTM_BUILTIN_GET_TFHAR || code == HTM_BUILTIN_SET_TFHAR ) return TFHAR_REGNO ; else if ( code == HTM_BUILTIN_GET_TFIAR || code == HTM_BUILTIN_SET_TFIAR ) return TFIAR_REGNO ; gcc_assert ( code == HTM_BUILTIN_GET_TEXASR || code == HTM_BUILTIN_SET_TEXASR || code == HTM_BUILTIN_GET_TEXASRU || code == HTM_BUILTIN_SET_TEXASRU ) ; return TEXASR_REGNO ; } </s>

Return the appropriate SPR regno associated with the given builtin .


"stack re-alignment, but LLVM couldn't handle it "

"(probably because it has a dynamic alloca)."

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static bool mem_locations_overlap ( rtx mem1 , rtx mem2 ) { rtx reg1 , reg2 ; HOST_WIDE_INT off1 , size1 , off2 , size2 ; if ( get_memref_parts ( mem1 , & reg1 , & off1 , & size1 ) && get_memref_parts ( mem2 , & reg2 , & off2 , & size2 ) ) return ( ( REGNO ( reg1 ) == REGNO ( reg2 ) ) && ( ( ( off1 <= off2 ) && ( off1 + size1 > off2 ) ) || ( ( off2 <= off1 ) && ( off2 + size2 > off1 ) ) ) ) ; return false ; } </s>

This function returns true if it can be determined that the two MEM locations overlap by at least 1 byte based on base reg/offset/size .


<s> const Comet2Subtarget * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> SUnit * PPCPostRASchedStrategy :: pickNode ( bool & IsTopNode ) { return PostGenericScheduler :: pickNode ( IsTopNode ) ; } </s>

Pick the next node to schedule , or return NULL .


<s> void X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { bool reserveCallFrame = hasReservedCallFrame ( MF ) ; unsigned Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t InternalAmt = ( isDestroy || Amount ) ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { unsigned StackAlign = getStackAlignment ( ) ; Amount = RoundUpToAlignment ( Amount , StackAlign ) ; bool HasDwarfEHHandlers = ! MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) && ! MF . getMMI ( ) . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < X86MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , I , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == 0 ) return ; Amount -= InternalAmt ; if ( Amount ) { int Offset = isDestroy ? Amount : - Amount ; if ( ! ( MF . getFunction ( ) -> optForMinSize ( ) && adjustStackWithPops ( MBB , I , DL , Offset ) ) ) BuildStackAdjustment ( MBB , I , DL , Offset , false ) ; } return ; } if ( isDestroy && InternalAmt ) { MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! std :: prev ( I ) -> isCall ( ) ) -- I ; BuildStackAdjustment ( MBB , I , DL , - InternalAmt , false ) ; } } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < LiveIntervals > ( ) ; AU . addRequired < MachineBlockFrequencyInfo > ( ) ; AU . addPreserved < MachineBlockFrequencyInfo > ( ) ; AU . addPreservedID ( MachineDominatorsID ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> NVPTXTargetLowering :: ConstraintType NVPTXTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'r' : case 'h' : case 'c' : case 'l' : case 'f' : case 'd' : case '0' : case 'N' : return C_RegisterClass ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s>
LLVM_DUMP_METHOD
void
GCNRegPressure
::
print
(
raw_ostream
&
OS
,
const
SISubtarget
*
ST
)
const
{
OS
<<
"VGPRs: "
<<
getVGRPNum
(
)
;
if
(
ST
)
OS
<<
"(O"
<<
ST
->
getOccupancyWithNumVGPRs
(
getVGRPNum
(
)
)
<<
')'
;
OS
<<
", SGPRs: "
<<
getSGRPNum
(
)
;
if
(
ST
)
OS
<<
"(O"
<<
ST
->
getOccupancyWithNumSGPRs
(
getSGRPNum
(
)
)
<<
')'
;
OS
<<
", LVGPR WT: "
<<
getVGPRTuplesWeight
(
)
<<
", LSGPR WT: "
<<
getSGPRTuplesWeight
(
)
;
if
(
ST
)
OS
<<
" -> Occ: "
<<
getOccupancy
(
*
ST
)
;
OS
<<
'\n'
;
}
</s>

print - Print a debug representation of the operand to the given stream .

AMDGPU
SI
"VGPRs: "
"(O"
", SGPRs: "
"(O"
", LVGPR WT: "
", LSGPR WT: "
" -> Occ: "


<s> static rtx m32c_all_frame_related ( rtx par ) { int len = XVECLEN ( par , 0 ) ; int i ; for ( i = 0 ; i < len ; i ++ ) F ( XVECEXP ( par , 0 , i ) ) ; return par ; } </s>

Mark all the subexpressions of the PARALLEL rtx PAR as frame-related . Return PAR . dwarf2out.cc : dwarf2out_frame_debug_expr ignores sub-expressions of a PARALLEL rtx other than the first if they do not have the FRAME_RELATED flag set on them . So this function is handy for marking up 'enter ' instructions .


<s> bool GCNPassConfig :: addPreISel ( ) { AMDGPUPassConfig :: addPreISel ( ) ; if ( EnableAtomicOptimizations ) { addPass ( createAMDGPUAtomicOptimizerPass ( ) ) ; } addPass ( & AMDGPUUnifyDivergentExitNodesID ) ; if ( ! LateCFGStructurize ) { if ( EnableStructurizerWorkarounds ) { addPass ( createFixIrreduciblePass ( ) ) ; addPass ( createUnifyLoopExitsPass ( ) ) ; } addPass ( createStructurizeCFGPass ( false ) ) ; } addPass ( createSinkingPass ( ) ) ; addPass ( createAMDGPUAnnotateUniformValues ( ) ) ; if ( ! LateCFGStructurize ) { addPass ( createSIAnnotateControlFlowPass ( ) ) ; } addPass ( createLCSSAPass ( ) ) ; return false ; } </s>


<s> static void ix86_emit_save_regs ( void ) { unsigned int regno ; rtx_insn * insn ; for ( regno = FIRST_PSEUDO_REGISTER - 1 ; regno -- > 0 ; ) if ( GENERAL_REGNO_P ( regno ) && ix86_save_reg ( regno , true ) ) { insn = emit_insn ( gen_push ( gen_rtx_REG ( word_mode , regno ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } </s>

Emit code to save registers in the prologue .


<s> bool PPCPassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( getOptLevel ( ) ) ) ; return false ; } </s>

This method should install a ( global ) instruction selector pass , which converts possibly generic instructions to fully target-specific instructions , thereby constraining all generic virtual registers to register classes .


<s> bool Z80oldRegisterInfo :: needsFrameBaseReg ( MachineInstr * MI , int64_t Offset ) const { const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; return ! isFrameOffsetLegal ( MI , getFrameRegister ( MF ) , Offset ) ; } </s>

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s> static int forward_branch_p ( rtx insn ) { rtx label = JUMP_LABEL ( insn ) ; while ( insn ) { if ( insn == label ) break ; else insn = NEXT_INSN ( insn ) ; } return ( insn == label ) ; } </s>

Return 1 if INSN branches forward . Should be using insn_addresses to avoid walking through all the insns ...


Relax the instruction in the given fragment to the next wider instruction .


<s> bool ARMTTIImpl :: isLegalMaskedGather ( Type * Ty , Align Alignment ) { if ( ! EnableMaskedGatherScatters || ! ST -> hasMVEIntegerOps ( ) ) return false ; if ( isa < VectorType > ( Ty ) ) return false ; unsigned EltWidth = Ty -> getScalarSizeInBits ( ) ; return ( ( EltWidth == 32 && Alignment >= 4 ) || ( EltWidth == 16 && Alignment >= 2 ) || EltWidth == 8 ) ; } </s>

Return true if the target supports masked gather .


<s> bool runOnModule ( Module & M ) override { UsedList = AMDGPU :: getUsedList ( M ) ; bool Changed = processUsedLDS ( M ) ; for ( Function & F : M . functions ( ) ) { if ( F . isDeclaration ( ) ) continue ; if ( ! AMDGPU :: isKernel ( F . getCallingConv ( ) ) ) continue ; Changed |= processUsedLDS ( M , & F ) ; } UsedList . clear ( ) ; return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { unsigned NumOps = Inst . getNumOperands ( ) ; if ( isBranch ( Inst ) || Inst . getOpcode ( ) == LoongArch :: BL ) { Target = Addr + Inst . getOperand ( NumOps - 1 ) . getImm ( ) ; return true ; } return false ; } </s>

Given a branch instruction try to get the address the branch targets .


<s> bool SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) override { const TargetRegisterInfo * TRI = PPCSubTarget -> getRegisterInfo ( ) ; const TargetRegisterClass * TRC = TRI -> getPointerRegClass ( * MF , 1 ) ; SDValue RC = CurDAG -> getTargetConstant ( TRC -> getID ( ) , MVT :: i32 ) ; SDValue NewOp = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , SDLoc ( Op ) , Op . getValueType ( ) , Op , RC ) , 0 ) ; OutOps . push_back ( NewOp ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
Videocore
::
NumTargetFixupKinds
]
=
{
{
"fixup_Videocore_16"
,
0
,
16
,
0
}
,
{
"fixup_Videocore_32"
,
0
,
32
,
0
}
,
{
"fixup_Videocore_REL32"
,
0
,
32
,
0
}
,
{
"fixup_Videocore_24"
,
0
,
24
,
0
}
,
{
"fixup_Videocore_HI16"
,
0
,
16
,
0
}
,
{
"fixup_Videocore_LO16"
,
0
,
16
,
0
}
,
{
"fixup_Videocore_GPREL16"
,
0
,
16
,
0
}
,
{
"fixup_Videocore_LITERAL"
,
0
,
16
,
0
}
,
{
"fixup_Videocore_GOT_Global"
,
0
,
16
,
0
}
,
{
"fixup_Videocore_GOT_Local"
,
0
,
16
,
0
}
,
{
"fixup_Videocore_PC24"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_Videocore_CALL16"
,
0
,
16
,
0
}
,
{
"fixup_Videocore_GPREL32"
,
0
,
32
,
0
}
,
{
"fixup_Videocore_SHIFT5"
,
6
,
5
,
0
}
,
{
"fixup_Videocore_SHIFT6"
,
6
,
5
,
0
}
,
{
"fixup_Videocore_64"
,
0
,
64
,
0
}
,
{
"fixup_Videocore_TLSGD"
,
0
,
16
,
0
}
,
{
"fixup_Videocore_GOTTPREL"
,
0
,
16
,
0
}
,
{
"fixup_Videocore_TPREL_HI"
,
0
,
16
,
0
}
,
{
"fixup_Videocore_TPREL_LO"
,
0
,
16
,
0
}
,
{
"fixup_Videocore_TLSLDM"
,
0
,
16
,
0
}
,
{
"fixup_Videocore_DTPREL_HI"
,
0
,
16
,
0
}
,
{
"fixup_Videocore_DTPREL_LO"
,
0
,
16
,
0
}
,
{
"fixup_Videocore_Branch_PCRel"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> bool X86TargetLowering :: isTypeDesirableForOp ( unsigned Opc , EVT VT ) const { if ( ! isTypeLegal ( VT ) ) return false ; if ( Opc == ISD :: SHL && VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i8 ) return false ; if ( ( Opc == ISD :: MUL || Opc == ISD :: SHL ) && VT == MVT :: i8 ) return false ; if ( VT == MVT :: i16 ) { switch ( Opc ) { default : break ; case ISD :: LOAD : case ISD :: SIGN_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: ANY_EXTEND : case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : case ISD :: SUB : case ISD :: ADD : case ISD :: MUL : case ISD :: AND : case ISD :: OR : case ISD :: XOR : return false ; } } return true ; } </s>

Return true if the target has native support for the specified value type and it is 'desirable ' to use the type for the given node type .


<s> static bool arc_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { tree attrs = NULL_TREE ; if ( ARC_INTERRUPT_P ( arc_compute_function_type ( cfun ) ) ) return false ; if ( decl ) { attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; if ( lookup_attribute ( "jli_always" , attrs ) ) return false ; if ( lookup_attribute ( "jli_fixed" , attrs ) ) return false ; if ( lookup_attribute ( "secure_call" , attrs ) ) return false ; } return true ; } </s>

Return true if it is ok to make a tail-call to DECL .


<s>
const
char
*
lshrsi3_out
(
rtx_insn
*
insn
,
rtx
operands
[
]
,
int
*
len
)
{
if
(
GET_CODE
(
operands
[
2
]
)
==
CONST_INT
)
{
int
k
;
int
*
t
=
len
;
if
(
!
len
)
len
=
&
k
;
switch
(
INTVAL
(
operands
[
2
]
)
)
{
default
:
if
(
INTVAL
(
operands
[
2
]
)
<
32
)
break
;
if
(
AVR_HAVE_MOVW
)
return
*
len
=
3
,
(
"clr %D0"
CR_TAB
"clr %C0"
CR_TAB
"movw %A0,%C0"
)
;
*
len
=
4
;
return
(
"clr %D0"
CR_TAB
"clr %C0"
CR_TAB
"clr %B0"
CR_TAB
"clr %A0"
)
;
case
8
:
{
int
reg0
=
true_regnum
(
operands
[
0
]
)
;
int
reg1
=
true_regnum
(
operands
[
1
]
)
;
*
len
=
4
;
if
(
reg0
<=
reg1
)
return
(
"mov %A0,%B1"
CR_TAB
"mov %B0,%C1"
CR_TAB
"mov %C0,%D1"
CR_TAB
"clr %D0"
)
;
else
return
(
"clr %D0"
CR_TAB
"mov %C0,%D1"
CR_TAB
"mov %B0,%C1"
CR_TAB
"mov %A0,%B1"
)
;
}
case
16
:
{
int
reg0
=
true_regnum
(
operands
[
0
]
)
;
int
reg1
=
true_regnum
(
operands
[
1
]
)
;
if
(
reg0
==
reg1
+
2
)
return
*
len
=
2
,
(
"clr %C0"
CR_TAB
"clr %D0"
)
;
if
(
AVR_HAVE_MOVW
)
return
*
len
=
3
,
(
"movw %A0,%C1"
CR_TAB
"clr %C0"
CR_TAB
"clr %D0"
)
;
else
return
*
len
=
4
,
(
"mov %B0,%D1"
CR_TAB
"mov %A0,%C1"
CR_TAB
"clr %C0"
CR_TAB
"clr %D0"
)
;
}
case
24
:
return
*
len
=
4
,
(
"mov %A0,%D1"
CR_TAB
"clr %B0"
CR_TAB
"clr %C0"
CR_TAB
"clr %D0"
)
;
case
31
:
*
len
=
6
;
return
(
"clr %A0"
CR_TAB
"sbrc %D0,7"
CR_TAB
"inc %A0"
CR_TAB
"clr %B0"
CR_TAB
"clr %C0"
CR_TAB
"clr %D0"
)
;
}
len
=
t
;
}
out_shift_with_cnt
(
"lsr %D0"
CR_TAB
"ror %C0"
CR_TAB
"ror %B0"
CR_TAB
"ror %A0"
,
insn
,
operands
,
len
,
4
)
;
return
""
;
}
</s>

32bit logic shift right ( ( unsigned int ) x > > i )


<s>
static
rtx
m32c_subreg
(
enum
machine_mode
outer
,
rtx
x
,
enum
machine_mode
inner
,
int
byte
)
{
int
r
,
nr
=
1
;
if
(
GET_CODE
(
x
)
==
SUBREG
&&
SUBREG_BYTE
(
x
)
==
0
&&
GET_CODE
(
SUBREG_REG
(
x
)
)
==
MEM
&&
(
GET_MODE_SIZE
(
GET_MODE
(
x
)
)
==
GET_MODE_SIZE
(
GET_MODE
(
SUBREG_REG
(
x
)
)
)
)
)
{
rtx
oldx
=
x
;
x
=
gen_rtx_MEM
(
GET_MODE
(
x
)
,
XEXP
(
SUBREG_REG
(
x
)
,
0
)
)
;
MEM_COPY_ATTRIBUTES
(
x
,
SUBREG_REG
(
oldx
)
)
;
}
if
(
GET_CODE
(
x
)
==
MEM
&&
(
GET_CODE
(
XEXP
(
x
,
0
)
)
==
PRE_DEC
||
GET_CODE
(
XEXP
(
x
,
0
)
)
==
POST_INC
)
)
return
gen_rtx_MEM
(
outer
,
XEXP
(
x
,
0
)
)
;
if
(
GET_CODE
(
x
)
==
SUBREG
&&
GET_CODE
(
XEXP
(
x
,
0
)
)
==
MEM
&&
(
GET_CODE
(
XEXP
(
XEXP
(
x
,
0
)
,
0
)
)
==
PRE_DEC
||
GET_CODE
(
XEXP
(
XEXP
(
x
,
0
)
,
0
)
)
==
POST_INC
)
)
return
gen_rtx_MEM
(
outer
,
XEXP
(
XEXP
(
x
,
0
)
,
0
)
)
;
if
(
GET_CODE
(
x
)
!=
REG
)
return
simplify_gen_subreg
(
outer
,
x
,
inner
,
byte
)
;
r
=
REGNO
(
x
)
;
if
(
r
>=
FIRST_PSEUDO_REGISTER
||
r
==
AP_REGNO
)
return
simplify_gen_subreg
(
outer
,
x
,
inner
,
byte
)
;
if
(
IS_MEM_REGNO
(
r
)
)
return
simplify_gen_subreg
(
outer
,
x
,
inner
,
byte
)
;
if
(
byte
==
0
)
nr
=
r
;
else
if
(
outer
==
HImode
)
{
if
(
r
==
R0_REGNO
&&
byte
==
2
)
nr
=
R2_REGNO
;
else
if
(
r
==
R0_REGNO
&&
byte
==
4
)
nr
=
R1_REGNO
;
else
if
(
r
==
R0_REGNO
&&
byte
==
6
)
nr
=
R3_REGNO
;
else
if
(
r
==
R1_REGNO
&&
byte
==
2
)
nr
=
R3_REGNO
;
else
if
(
r
==
A0_REGNO
&&
byte
==
2
)
nr
=
A1_REGNO
;
}
else
if
(
outer
==
SImode
)
{
if
(
r
==
R0_REGNO
&&
byte
==
0
)
nr
=
R0_REGNO
;
else
if
(
r
==
R0_REGNO
&&
byte
==
4
)
nr
=
R1_REGNO
;
}
if
(
nr
==
1
)
{
fprintf
(
stderr
,
"m32c_subreg %s %s %d\n"
,
mode_name
[
outer
]
,
mode_name
[
inner
]
,
byte
)
;
debug_rtx
(
x
)
;
gcc_unreachable
(
)
;
}
return
gen_rtx_REG
(
outer
,
nr
)
;
}
</s>

Subregs are non-orthogonal for us , because our registers are all different sizes .


<s> void releaseBottomNode ( SUnit * SU ) override { } </s>

Currently only scheduling top-down , so this method is empty .


<s> static void register_builtin_tuple_types ( vector_type_index type ) { const vector_type_info * info = & vector_types [ type ] ; if ( scalar_types [ type ] == boolean_type_node || ( info -> requires_float && ! TARGET_HAVE_MVE_FLOAT ) ) return ; const char * vector_type_name = info -> acle_name ; char buffer [ sizeof ( "float32x4x2_t" ) ] ; for ( unsigned int num_vectors = 2 ; num_vectors <= 4 ; num_vectors += 2 ) { snprintf ( buffer , sizeof ( buffer ) , "%.*sx%d_t" , ( int ) strlen ( vector_type_name ) - 2 , vector_type_name , num_vectors ) ; tree vectype = acle_vector_types [ 0 ] [ type ] ; tree arrtype = build_array_type_nelts ( vectype , num_vectors ) ; gcc_assert ( TYPE_MODE_RAW ( arrtype ) == TYPE_MODE ( arrtype ) ) ; tree field = build_decl ( input_location , FIELD_DECL , get_identifier ( "val" ) , arrtype ) ; tree t = lang_hooks . types . simulate_record_decl ( input_location , buffer , make_array_slice ( & field , 1 ) ) ; gcc_assert ( TYPE_MODE_RAW ( t ) == TYPE_MODE ( t ) ) ; acle_vector_types [ num_vectors >> 1 ] [ type ] = TREE_TYPE ( t ) ; } } </s>

Register tuple type TYPE with NUM_VECTORS arity under its arm_mve_types.h name .


<s> static pad_direction rs6000_function_arg_padding ( machine_mode mode , const_tree type ) { if ( ! AGGREGATE_PADDING_FIXED ) { if ( BYTES_BIG_ENDIAN ) { HOST_WIDE_INT size = 0 ; if ( mode == BLKmode ) { if ( type && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST ) size = int_size_in_bytes ( type ) ; } else size = GET_MODE_SIZE ( mode ) ; if ( size == 1 || size == 2 || size == 4 ) return PAD_DOWNWARD ; } return PAD_UPWARD ; } if ( AGGREGATES_PAD_UPWARD_ALWAYS ) { if ( type != 0 && AGGREGATE_TYPE_P ( type ) ) return PAD_UPWARD ; } return default_function_arg_padding ( mode , type ) ; } </s>

Implement TARGET_FUNCTION_ARG_PADDING . For the AIX ABI structs are always stored left shifted in their argument slot .


"\n========== quad_load_store, return %s\n"

Return true if this is a load or store quad operation . This function does not handle the atomic quad memory instructions .


<s> unsigned getExceptionPointerRegister ( const Constant * PersonalityFn ) const override { return XCore :: R0 ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


"********** ARM MVE VPT Optimisations **********\n"

runOnMachineFunction - Emit the function body .


<s> DecodeStatus PPCDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CS ) const { Size = 4 ; if ( Bytes . size ( ) < 4 ) { Size = 0 ; return MCDisassembler :: Fail ; } uint32_t Inst = IsLittleEndian ? support :: endian :: read32le ( Bytes . data ( ) ) : support :: endian :: read32be ( Bytes . data ( ) ) ; if ( STI . getFeatureBits ( ) [ PPC :: FeatureQPX ] ) { DecodeStatus result = decodeInstruction ( DecoderTableQPX32 , MI , Inst , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) return result ; } else if ( STI . getFeatureBits ( ) [ PPC :: FeatureSPE ] ) { DecodeStatus result = decodeInstruction ( DecoderTableSPE32 , MI , Inst , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) return result ; } return decodeInstruction ( DecoderTable32 , MI , Inst , Address , this , STI ) ; } </s>

Returns the disassembly of a single instruction .

PowerPC PPC 4 4 0 support::endian support::endian PPC::FeatureQPX PPC::FeatureSPE


<s> bool SILowerControlFlowPass :: runOnMachineFunction ( MachineFunction & MF ) { bool HaveKill = false ; bool NeedWQM = false ; unsigned Depth = 0 ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , Next = llvm :: next ( I ) ; I != MBB . end ( ) ; I = Next ) { Next = llvm :: next ( I ) ; MachineInstr & MI = * I ; switch ( MI . getOpcode ( ) ) { default : break ; case AMDGPU :: SI_IF : ++ Depth ; If ( MI ) ; break ; case AMDGPU :: SI_ELSE : Else ( MI ) ; break ; case AMDGPU :: SI_BREAK : Break ( MI ) ; break ; case AMDGPU :: SI_IF_BREAK : IfBreak ( MI ) ; break ; case AMDGPU :: SI_ELSE_BREAK : ElseBreak ( MI ) ; break ; case AMDGPU :: SI_LOOP : ++ Depth ; Loop ( MI ) ; break ; case AMDGPU :: SI_END_CF : if ( -- Depth == 0 && HaveKill ) { SkipIfDead ( MI ) ; HaveKill = false ; } EndCf ( MI ) ; break ; case AMDGPU :: SI_KILL : if ( Depth == 0 ) SkipIfDead ( MI ) ; else HaveKill = true ; Kill ( MI ) ; break ; case AMDGPU :: S_BRANCH : Branch ( MI ) ; break ; case AMDGPU :: SI_INDIRECT_SRC : IndirectSrc ( MI ) ; break ; case AMDGPU :: SI_INDIRECT_DST_V2 : case AMDGPU :: SI_INDIRECT_DST_V4 : case AMDGPU :: SI_INDIRECT_DST_V8 : case AMDGPU :: SI_INDIRECT_DST_V16 : IndirectDst ( MI ) ; break ; case AMDGPU :: V_INTERP_P1_F32 : case AMDGPU :: V_INTERP_P2_F32 : case AMDGPU :: V_INTERP_MOV_F32 : NeedWQM = true ; break ; } } } if ( NeedWQM ) { MachineBasicBlock & MBB = MF . front ( ) ; BuildMI ( MBB , MBB . getFirstNonPHI ( ) , DebugLoc ( ) , TII -> get ( AMDGPU :: S_WQM_B64 ) , AMDGPU :: EXEC ) . addReg ( AMDGPU :: EXEC ) ; } return true ; } </s>

R600 SI 0 SI SI SI SI SI SI SI 0 SI 0 SI SI SI SI SI