<s> int SparcFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const SparcSubtarget & Subtarget = MF . getSubtarget < SparcSubtarget > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const SparcRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; const SparcMachineFunctionInfo * FuncInfo = MF . getInfo < SparcMachineFunctionInfo > ( ) ; bool isFixed = MFI . isFixedObjectIndex ( FI ) ; bool UseFP ; if ( FuncInfo -> isLeafProc ( ) ) { UseFP = false ; } else if ( isFixed ) { UseFP = true ; } else if ( RegInfo -> needsStackRealignment ( MF ) ) { UseFP = false ; } else { UseFP = true ; } int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) + Subtarget . getStackPointerBias ( ) ; if ( UseFP ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FrameOffset ; } else { FrameReg = SP :: O6 ; return FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ; } } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .

Sparc Sparc Sparc Sparc Sparc Sparc Sparc SP::O6


<s> MCSection * getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , unsigned & Align ) const override { return ReadOnlySection ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> void HexagonInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ) ; if ( Hexagon :: IntRegsRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: STriw ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( Hexagon :: DoubleRegsRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: STrid ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( Hexagon :: PredRegsRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: STriw_pred ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else { llvm_unreachable ( "Unimplemented" ) ; } } </s>

Store the specified register of the given register class to the specified stack frame index .

Hexagon Hexagon Hexagon::IntRegsRegClass Hexagon::STriw 0 Hexagon::DoubleRegsRegClass Hexagon::STrid 0 Hexagon::PredRegsRegClass Hexagon::STriw_pred 0 "Unimplemented"


"selector must be an integer constant in the range "

Return the integer constant in ARG . Constrain it to be in the range of the subparts of VEC_TYPE ; issue an error if not .


<s> void scalar_chain :: convert_registers ( ) { bitmap_iterator bi ; unsigned id ; EXECUTE_IF_SET_IN_BITMAP ( defs_conv , 0 , id , bi ) { rtx chain_reg = gen_reg_rtx ( smode ) ; defs_map . put ( regno_reg_rtx [ id ] , chain_reg ) ; } EXECUTE_IF_SET_IN_BITMAP ( insns_conv , 0 , id , bi ) for ( df_ref ref = DF_INSN_UID_DEFS ( id ) ; ref ; ref = DF_REF_NEXT_LOC ( ref ) ) if ( bitmap_bit_p ( defs_conv , DF_REF_REGNO ( ref ) ) ) make_vector_copies ( DF_REF_INSN ( ref ) , DF_REF_REAL_REG ( ref ) ) ; } </s>

Generate copies from defs used by the chain but not defined therein . Also populates defs_map which is used later by convert_insn .


<s> static void ATTRIBUTE_UNUSED ix86_encode_section_info ( tree decl , rtx rtl , int first ) { default_encode_section_info ( decl , rtl , first ) ; if ( ix86_in_large_data_p ( decl ) ) SYMBOL_REF_FLAGS ( XEXP ( rtl , 0 ) ) |= SYMBOL_FLAG_FAR_ADDR ; } </s>

Implements target vector targetm.asm.encode_section_info .


<s> unsigned char X86Subtarget :: classifyGlobalReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large && ! isPositionIndependent ( ) ) return X86II :: MO_NO_FLAG ; if ( GV ) { if ( Optional < ConstantRange > CR = GV -> getAbsoluteSymbolRange ( ) ) { if ( CR -> getUnsignedMax ( ) . ult ( 128 ) ) return X86II :: MO_ABS8 ; else return X86II :: MO_NO_FLAG ; } } if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return classifyLocalReference ( GV ) ; if ( isTargetCOFF ( ) ) { if ( GV -> hasDLLImportStorageClass ( ) ) return X86II :: MO_DLLIMPORT ; return X86II :: MO_COFFSTUB ; } if ( isOSWindows ( ) ) return X86II :: MO_NO_FLAG ; if ( is64Bit ( ) ) { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return isTargetELF ( ) ? X86II :: MO_GOT : X86II :: MO_NO_FLAG ; return X86II :: MO_GOTPCREL ; } if ( isTargetDarwin ( ) ) { if ( ! isPositionIndependent ( ) ) return X86II :: MO_DARWIN_NONLAZY ; return X86II :: MO_DARWIN_NONLAZY_PIC_BASE ; } return X86II :: MO_GOT ; } </s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s> unsigned TeakMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { return 0 ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> int mips_idiv_insns ( machine_mode mode ) { int count ; count = 1 ; if ( TARGET_CHECK_ZERO_DIV ) { if ( GENERATE_DIVIDE_TRAPS && ! MSA_SUPPORTED_MODE_P ( mode ) ) count ++ ; else count += 2 ; } if ( TARGET_FIX_R4000 || TARGET_FIX_R4400 ) count ++ ; return count ; } </s>

Return the number of instructions needed for an integer division .


<s>
static
void
s390_output_indirect_thunk_function
(
unsigned
int
regno
,
bool
z10_p
)
{
tree
decl
;
char
thunk_label
[
32
]
;
int
i
;
if
(
z10_p
)
sprintf
(
thunk_label
,
TARGET_INDIRECT_BRANCH_THUNK_NAME_EXRL
,
regno
)
;
else
sprintf
(
thunk_label
,
TARGET_INDIRECT_BRANCH_THUNK_NAME_EX
,
INDIRECT_BRANCH_THUNK_REGNUM
,
regno
)
;
decl
=
build_decl
(
BUILTINS_LOCATION
,
FUNCTION_DECL
,
get_identifier
(
thunk_label
)
,
build_function_type_list
(
void_type_node
,
NULL_TREE
)
)
;
DECL_RESULT
(
decl
)
=
build_decl
(
BUILTINS_LOCATION
,
RESULT_DECL
,
NULL_TREE
,
void_type_node
)
;
TREE_PUBLIC
(
decl
)
=
1
;
TREE_STATIC
(
decl
)
=
1
;
DECL_IGNORED_P
(
decl
)
=
1
;
if
(
USE_HIDDEN_LINKONCE
)
{
cgraph_node
::
create
(
decl
)
->
set_comdat_group
(
DECL_ASSEMBLER_NAME
(
decl
)
)
;
targetm
.
asm_out
.
unique_section
(
decl
,
0
)
;
switch_to_section
(
get_named_section
(
decl
,
,
0
)
)
;
targetm
.
asm_out
.
globalize_label
(
asm_out_file
,
thunk_label
)
;
fputs
(
"\t.hidden\t"
,
asm_out_file
)
;
assemble_name
(
asm_out_file
,
thunk_label
)
;
putc
(
'\n'
,
asm_out_file
)
;
ASM_DECLARE_FUNCTION_NAME
(
asm_out_file
,
thunk_label
,
decl
)
;
}
else
{
switch_to_section
(
text_section
)
;
ASM_OUTPUT_LABEL
(
asm_out_file
,
thunk_label
)
;
}
DECL_INITIAL
(
decl
)
=
make_node
(
BLOCK
)
;
current_function_decl
=
decl
;
allocate_struct_function
(
decl
,
false
)
;
init_function_start
(
decl
)
;
cfun
->
is_thunk
=
true
;
first_function_block_is_cold
=
false
;
final_start_function
(
emit_barrier
(
)
,
asm_out_file
,
1
)
;
if
(
flag_asynchronous_unwind_tables
&&
flag_dwarf2_cfi_asm
)
{
fputs
(
"\t.cfi_signal_frame\n"
,
asm_out_file
)
;
fprintf
(
asm_out_file
,
"\t.cfi_return_column %d\n"
,
regno
)
;
for
(
i
=
0
;
i
<
FPR15_REGNUM
;
i
++
)
fprintf
(
asm_out_file
,
"\t.cfi_same_value %s\n"
,
reg_names
[
i
]
)
;
}
if
(
z10_p
)
{
if
(
!
TARGET_CPU_Z10
)
{
fputs
(
"\t.machine push\n"
,
asm_out_file
)
;
fputs
(
"\t.machine z10\n"
,
asm_out_file
)
;
}
if
(
!
TARGET_ZARCH
)
fputs
(
"\t.machinemode zarch\n"
,
asm_out_file
)
;
fputs
(
"\texrl\t0,1f\n"
,
asm_out_file
)
;
if
(
!
TARGET_ZARCH
)
fputs
(
"\t.machinemode esa\n"
,
asm_out_file
)
;
if
(
!
TARGET_CPU_Z10
)
fputs
(
"\t.machine pop\n"
,
asm_out_file
)
;
}
else
{
fprintf
(
asm_out_file
,
"\tlarl\t%%r%d,1f\n"
,
INDIRECT_BRANCH_THUNK_REGNUM
)
;
fprintf
(
asm_out_file
,
"\tex\t0,0(%%r%d)\n"
,
INDIRECT_BRANCH_THUNK_REGNUM
)
;
}
fputs
(
"0:\tj\t0b\n"
,
asm_out_file
)
;
fprintf
(
asm_out_file
,
"1:\tbr\t%%r%d\n"
,
regno
)
;
final_end_function
(
)
;
init_insn_lengths
(
)
;
free_after_compilation
(
cfun
)
;
set_cfun
(
)
;
current_function_decl
=
;
}
</s>

Output an indirect branch trampoline for target register REGNO .


<s> bool sh_is_logical_t_store_expr ( rtx op , rtx_insn * insn ) { if ( ! logical_operator ( op , SImode ) ) return false ; rtx ops [ 2 ] = { XEXP ( op , 0 ) , XEXP ( op , 1 ) } ; int op_is_t_count = 0 ; for ( int i = 0 ; i < 2 ; ++ i ) { if ( t_reg_operand ( ops [ i ] , VOIDmode ) || negt_reg_operand ( ops [ i ] , VOIDmode ) ) op_is_t_count ++ ; else { set_of_reg op_set = sh_find_set_of_reg ( ops [ i ] , insn , prev_nonnote_nondebug_insn_bb ) ; if ( op_set . set_src == NULL_RTX ) continue ; if ( t_reg_operand ( op_set . set_src , VOIDmode ) || negt_reg_operand ( op_set . set_src , VOIDmode ) || sh_is_logical_t_store_expr ( op_set . set_src , op_set . insn ) ) op_is_t_count ++ ; } } return op_is_t_count == 2 ; } </s>

Given an op rtx and an insn , try to find out whether the result of the specified op consists only of logical operations on T bit stores .


<s> static bool important_for_bundling_p ( rtx_insn * insn ) { return ( INSN_P ( insn ) && ia64_safe_itanium_class ( insn ) != ITANIUM_CLASS_IGNORE && GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER ) ; } </s>

True when INSN is important for bundling .


"unknown architecture specific memory model"

"HLE_ACQUIRE not used with ACQUIRE or stronger memory model"

"HLE_RELEASE not used with RELEASE or stronger memory model"

Validate target specific memory model bits in VAL .


<s> bool SPUTargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createSPUISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s>
StringRef
getPassName
(
)
const
override
{
return
"WebAssembly Memory Intrinsic Results"
;
}
</s>

getPassName - Return a nice clean name for a pass .

WebAssembly
"WebAssembly Memory Intrinsic Results"


<s> static int loongarch_set_reg_reg_cost ( machine_mode mode ) { switch ( GET_MODE_CLASS ( mode ) ) { case MODE_CC : return loongarch_set_reg_reg_piece_cost ( mode , GET_MODE_SIZE ( CCmode ) ) ; case MODE_FLOAT : case MODE_COMPLEX_FLOAT : case MODE_VECTOR_FLOAT : if ( TARGET_HARD_FLOAT ) return loongarch_set_reg_reg_piece_cost ( mode , UNITS_PER_HWFPVALUE ) ; default : return loongarch_set_reg_reg_piece_cost ( mode , UNITS_PER_WORD ) ; } } </s>

Return the cost of moving between two registers of mode MODE .


<s> int AMDGPUInstrInfo :: pseudoToMCOpcode ( int Opcode ) const { SIEncodingFamily Gen = subtargetEncodingFamily ( ST ) ; if ( ( get ( Opcode ) . TSFlags & SIInstrFlags :: renamedInGFX9 ) != 0 && ST . getGeneration ( ) >= AMDGPUSubtarget :: GFX9 ) Gen = SIEncodingFamily :: GFX9 ; if ( get ( Opcode ) . TSFlags & SIInstrFlags :: SDWA ) Gen = ST . getGeneration ( ) == AMDGPUSubtarget :: GFX9 ? SIEncodingFamily :: SDWA9 : SIEncodingFamily :: SDWA ; int MCOp = AMDGPU :: getMCOpcode ( Opcode , Gen ) ; if ( MCOp == - 1 ) return Opcode ; if ( MCOp == ( uint16_t ) - 1 ) return - 1 ; return MCOp ; } </s>

Return a target-specific opcode if Opcode is a pseudo instruction .


<s> rtx extract_branch_target_rtx ( rtx_insn * insn ) { gcc_assert ( CALL_P ( insn ) || JUMP_P ( insn ) ) ; rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) == SET ) { if ( GET_CODE ( SET_SRC ( body ) ) == IF_THEN_ELSE ) return NULL_RTX ; return SET_SRC ( body ) ; } if ( GET_CODE ( body ) == CALL ) return XEXP ( body , 0 ) ; if ( GET_CODE ( body ) == PARALLEL ) { rtx first_rtx = parallel_element ( body , 0 ) ; if ( GET_CODE ( first_rtx ) == SET ) return SET_SRC ( first_rtx ) ; if ( GET_CODE ( first_rtx ) == CALL ) return XEXP ( first_rtx , 0 ) ; } if ( GET_CODE ( body ) == COND_EXEC ) { rtx addr_rtx = XEXP ( body , 1 ) ; if ( GET_CODE ( addr_rtx ) == SET ) return SET_SRC ( addr_rtx ) ; if ( GET_CODE ( addr_rtx ) == PARALLEL ) { rtx first_rtx = parallel_element ( addr_rtx , 0 ) ; if ( GET_CODE ( first_rtx ) == SET ) { rtx call_rtx = SET_SRC ( first_rtx ) ; gcc_assert ( GET_CODE ( call_rtx ) == CALL ) ; return XEXP ( call_rtx , 0 ) ; } if ( GET_CODE ( first_rtx ) == CALL ) return XEXP ( first_rtx , 0 ) ; } } gcc_unreachable ( ) ; } </s>

Extract the rtx representing the branch target to help recognize data hazards .


<s> static bool loongarch_print_operand_punct_valid_p ( unsigned char code ) { return loongarch_print_operand_punct [ code ] ; } </s>


<s> void AArch64AsmPrinter :: emitEndOfAsmFile ( Module & M ) { EmitHwasanMemaccessSymbols ( M ) ; const Triple & TT = TM . getTargetTriple ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; auto Stubs = MMIMacho . getAuthGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( OutContext . getMachOSection ( "__DATA" , "__auth_ptr" , MachO :: S_REGULAR , SectionKind :: getMetadata ( ) ) ) ; emitAlignment ( Align ( 8 ) ) ; for ( auto & Stub : Stubs ) emitAuthenticatedPointer ( * OutStreamer , Stub . first , Stub . second ) ; OutStreamer -> AddBlankLine ( ) ; } OutStreamer -> emitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } emitStackMaps ( SM ) ; FM . serializeToFaultMapSection ( ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> int mcore_num_arg_regs ( machine_mode mode , const_tree type ) { int size ; if ( targetm . calls . must_pass_in_stack ( mode , type ) ) return 0 ; if ( type && mode == BLKmode ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; return ROUND_ADVANCE ( size ) ; } </s>

Compute the number of word sized registers needed to hold a function argument of mode MODE and type TYPE .


<s> bool isFPImm ( ) const { return Kind == k_FPImm && AArch64_AM :: getFP64Imm ( getFPImm ( ) . bitcastToAPInt ( ) ) != - 1 ; } </s>

isFPImm - Tests if this is a MO_FPImmediate operand .


<s>
const
char
*
ret_cond_branch
(
rtx
x
,
int
len
,
int
reverse
)
{
RTX_CODE
cond
=
reverse
reverse_condition
(
GET_CODE
(
x
)
)
:
GET_CODE
(
x
)
;
bool
cc_overflow_unusable
=
false
;
switch
(
cond
)
{
case
GT
:
if
(
cc_overflow_unusable
)
return
(
len
==
1
(
"breq .+2"
CR_TAB
"brpl %0"
)
:
len
==
2
(
"breq .+4"
CR_TAB
"brmi .+2"
CR_TAB
"rjmp %0"
)
:
(
"breq .+6"
CR_TAB
"brmi .+4"
CR_TAB
"jmp %0"
)
)
;
else
return
(
len
==
1
(
"breq .+2"
CR_TAB
"brge %0"
)
:
len
==
2
(
"breq .+4"
CR_TAB
"brlt .+2"
CR_TAB
"rjmp %0"
)
:
(
"breq .+6"
CR_TAB
"brlt .+4"
CR_TAB
"jmp %0"
)
)
;
case
GTU
:
return
(
len
==
1
(
"breq .+2"
CR_TAB
"brsh %0"
)
:
len
==
2
(
"breq .+4"
CR_TAB
"brlo .+2"
CR_TAB
"rjmp %0"
)
:
(
"breq .+6"
CR_TAB
"brlo .+4"
CR_TAB
"jmp %0"
)
)
;
case
LE
:
if
(
cc_overflow_unusable
)
return
(
len
==
1
(
"breq %0"
CR_TAB
"brmi %0"
)
:
len
==
2
(
"breq .+2"
CR_TAB
"brpl .+2"
CR_TAB
"rjmp %0"
)
:
(
"breq .+2"
CR_TAB
"brpl .+4"
CR_TAB
"jmp %0"
)
)
;
else
return
(
len
==
1
(
"breq %0"
CR_TAB
"brlt %0"
)
:
len
==
2
(
"breq .+2"
CR_TAB
"brge .+2"
CR_TAB
"rjmp %0"
)
:
(
"breq .+2"
CR_TAB
"brge .+4"
CR_TAB
"jmp %0"
)
)
;
case
LEU
:
return
(
len
==
1
(
"breq %0"
CR_TAB
"brlo %0"
)
:
len
==
2
(
"breq .+2"
CR_TAB
"brsh .+2"
CR_TAB
"rjmp %0"
)
:
(
"breq .+2"
CR_TAB
"brsh .+4"
CR_TAB
"jmp %0"
)
)
;
default
:
if
(
reverse
)
{
switch
(
len
)
{
case
1
:
return
"br%k1 %0"
;
case
2
:
return
(
"br%j1 .+2"
CR_TAB
"rjmp %0"
)
;
default
:
return
(
"br%j1 .+4"
CR_TAB
"jmp %0"
)
;
}
}
else
{
switch
(
len
)
{
case
1
:
return
"br%j1 %0"
;
case
2
:
return
(
"br%k1 .+2"
CR_TAB
"rjmp %0"
)
;
default
:
return
(
"br%k1 .+4"
CR_TAB
"jmp %0"
)
;
}
}
}
return
""
;
}
</s>

return an AVR condition jump commands . X is a comparison RTX . LEN is a number returned by avr_jump_mode function . if REVERSE nonzero then condition code in X must be reversed .


<s> unsigned HexagonMCInst :: getUnits ( const HexagonTargetMachine * TM ) const { const HexagonInstrInfo * QII = TM -> getSubtargetImpl ( ) -> getInstrInfo ( ) ; const InstrItineraryData * II = TM -> getSubtargetImpl ( ) -> getInstrItineraryData ( ) ; const InstrStage * IS = II -> beginStage ( QII -> get ( this -> getOpcode ( ) ) . getSchedClass ( ) ) ; return ( IS -> getUnits ( ) ) ; } </s>


<s> static unsigned HOST_WIDE_INT aarch64_asan_shadow_offset ( void ) { if ( TARGET_ILP32 ) return ( HOST_WIDE_INT_1 << 29 ) ; else return ( HOST_WIDE_INT_1 << 36 ) ; } </s>

Implement the TARGET_ASAN_SHADOW_OFFSET hook .


<s> static void c4x_external_libcall ( rtx fun ) { c4x_external_ref ( XSTR ( fun , 0 ) ) ; } </s>

Worker function for TARGET_ASM_EXTERNAL_LIBCALL .


<s> TargetIRAnalysis SystemZTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( const Function & F ) { return TargetTransformInfo ( SystemZTTIImpl ( this , F ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


<s> void alpha_split_tfmode_frobsign ( rtx operands [ 3 ] , rtx ( * operation ) ( rtx , rtx , rtx ) ) { rtx high_bit = operands [ 2 ] ; rtx scratch ; int move ; alpha_split_tfmode_pair ( operands ) ; move = 1 ; if ( rtx_equal_p ( operands [ 0 ] , operands [ 2 ] ) ) move = 0 ; else if ( rtx_equal_p ( operands [ 1 ] , operands [ 2 ] ) ) { if ( rtx_equal_p ( operands [ 0 ] , high_bit ) ) move = 2 ; else move = - 1 ; } if ( move < 0 ) emit_move_insn ( operands [ 0 ] , operands [ 2 ] ) ; scratch = operands [ move < 2 ? 1 : 3 ] ; emit_insn ( ( * operation ) ( scratch , high_bit , operands [ 3 ] ) ) ; if ( move > 0 ) { emit_move_insn ( operands [ 0 ] , operands [ 2 ] ) ; if ( move > 1 ) emit_move_insn ( operands [ 1 ] , scratch ) ; } } </s>

Implement negtf2 or abstf2 . Op0 is destination , op1 is source , op2 is a register containing the sign bit , operation is the logical operation to be performed .


<s> void rs6000_d_register_target_info ( void ) { const struct d_target_info_spec handlers [ ] = { { "floatAbi" , rs6000_d_handle_target_float_abi } , { "objectFormat" , rs6000_d_handle_target_object_format } , { NULL , NULL } , } ; d_add_target_info_handlers ( handlers ) ; } </s>


<s> bool ARMConstantPoolValue :: hasSameValue ( ARMConstantPoolValue * ACPV ) { if ( ACPV -> Kind == Kind && ACPV -> CVal == CVal && ACPV -> PCAdjust == PCAdjust && CPV_streq ( ACPV -> S , S ) && ACPV -> Modifier == Modifier ) { if ( ACPV -> LabelId == LabelId ) return true ; if ( Kind == ARMCP :: CPValue || Kind == ARMCP :: CPExtSymbol ) return true ; } return false ; } </s>

hasSameValue - Return true if this ARM constpool value can share the same constantpool entry as another ARM constpool value .

ARM ARM ARM ARMCP::CPValue ARMCP::CPExtSymbol


<s> void XCoreTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; DataSection = MCSectionXCore :: Create ( ".dp.data" , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_ALLOC | MCSectionELF :: SHF_WRITE | MCSectionXCore :: SHF_DP_SECTION , SectionKind :: getDataRel ( ) , false , getContext ( ) ) ; BSSSection = MCSectionXCore :: Create ( ".dp.bss" , MCSectionELF :: SHT_NOBITS , MCSectionELF :: SHF_ALLOC | MCSectionELF :: SHF_WRITE | MCSectionXCore :: SHF_DP_SECTION , SectionKind :: getBSS ( ) , false , getContext ( ) ) ; MergeableConst4Section = MCSectionXCore :: Create ( ".cp.rodata.cst4" , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_ALLOC | MCSectionELF :: SHF_MERGE | MCSectionXCore :: SHF_CP_SECTION , SectionKind :: getMergeableConst4 ( ) , false , getContext ( ) ) ; MergeableConst8Section = MCSectionXCore :: Create ( ".cp.rodata.cst8" , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_ALLOC | MCSectionELF :: SHF_MERGE | MCSectionXCore :: SHF_CP_SECTION , SectionKind :: getMergeableConst8 ( ) , false , getContext ( ) ) ; MergeableConst16Section = MCSectionXCore :: Create ( ".cp.rodata.cst16" , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_ALLOC | MCSectionELF :: SHF_MERGE | MCSectionXCore :: SHF_CP_SECTION , SectionKind :: getMergeableConst16 ( ) , false , getContext ( ) ) ; TLSDataSection = DataSection ; TLSBSSSection = BSSSection ; ReadOnlySection = MCSectionXCore :: Create ( ".cp.rodata" , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_ALLOC | MCSectionXCore :: SHF_CP_SECTION , SectionKind :: getReadOnlyWithRel ( ) , false , getContext ( ) ) ; DataRelSection = DataRelLocalSection = DataSection ; DataRelROSection = DataRelROLocalSection = ReadOnlySection ; } </s>

This method must be called before any actual lowering is done .

XCore XCore XCore ".dp.data" XCore XCore ".dp.bss" XCore XCore ".cp.rodata.cst4" XCore XCore ".cp.rodata.cst8" XCore XCore ".cp.rodata.cst16" XCore XCore ".cp.rodata" XCore


<s> SMLoc getStartLoc ( ) const { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createCpu0ELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI ( OSType ) , IsLittle ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> unsigned MipsAsmParser :: checkTargetMatchPredicate ( MCInst & Inst ) { switch ( Inst . getOpcode ( ) ) { case Mips :: JALR_HB : case Mips :: JALRC_HB_MMR6 : case Mips :: JALRC_MMR6 : if ( Inst . getOperand ( 0 ) . getReg ( ) == Inst . getOperand ( 1 ) . getReg ( ) ) return Match_RequiresDifferentSrcAndDst ; return Match_Success ; case Mips :: LWP_MM : case Mips :: LWP_MMR6 : if ( Inst . getOperand ( 0 ) . getReg ( ) == Inst . getOperand ( 2 ) . getReg ( ) ) return Match_RequiresDifferentSrcAndDst ; return Match_Success ; case Mips :: BLEZC : case Mips :: BGEZC : case Mips :: BGTZC : case Mips :: BLTZC : case Mips :: BEQZC : case Mips :: BNEZC : if ( Inst . getOperand ( 0 ) . getReg ( ) == Mips :: ZERO ) return Match_RequiresNoZeroRegister ; return Match_Success ; case Mips :: BGEC : case Mips :: BLTC : case Mips :: BGEUC : case Mips :: BLTUC : case Mips :: BEQC : case Mips :: BNEC : if ( Inst . getOperand ( 0 ) . getReg ( ) == Mips :: ZERO ) return Match_RequiresNoZeroRegister ; if ( Inst . getOperand ( 1 ) . getReg ( ) == Mips :: ZERO ) return Match_RequiresNoZeroRegister ; if ( Inst . getOperand ( 0 ) . getReg ( ) == Inst . getOperand ( 1 ) . getReg ( ) ) return Match_RequiresDifferentOperands ; return Match_Success ; default : return Match_Success ; } } </s>

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


<s>
bool
SIRegisterInfo
::
eliminateSGPRToVGPRSpillFrameIndex
(
MachineBasicBlock
::
iterator
MI
,
int
FI
,
RegScavenger
*
RS
,
LiveIntervals
*
LIS
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
case
AMDGPU
::
SI_SPILL_S1024_SAVE
:
case
AMDGPU
::
SI_SPILL_S512_SAVE
:
case
AMDGPU
::
SI_SPILL_S256_SAVE
:
case
AMDGPU
::
SI_SPILL_S224_SAVE
:
case
AMDGPU
::
SI_SPILL_S192_SAVE
:
case
AMDGPU
::
SI_SPILL_S160_SAVE
:
case
AMDGPU
::
SI_SPILL_S128_SAVE
:
case
AMDGPU
::
SI_SPILL_S96_SAVE
:
case
AMDGPU
::
SI_SPILL_S64_SAVE
:
case
AMDGPU
::
SI_SPILL_S32_SAVE
:
return
spillSGPR
(
MI
,
FI
,
RS
,
LIS
,
true
)
;
case
AMDGPU
::
SI_SPILL_S1024_RESTORE
:
case
AMDGPU
::
SI_SPILL_S512_RESTORE
:
case
AMDGPU
::
SI_SPILL_S256_RESTORE
:
case
AMDGPU
::
SI_SPILL_S224_RESTORE
:
case
AMDGPU
::
SI_SPILL_S192_RESTORE
:
case
AMDGPU
::
SI_SPILL_S160_RESTORE
:
case
AMDGPU
::
SI_SPILL_S128_RESTORE
:
case
AMDGPU
::
SI_SPILL_S96_RESTORE
:
case
AMDGPU
::
SI_SPILL_S64_RESTORE
:
case
AMDGPU
::
SI_SPILL_S32_RESTORE
:
return
restoreSGPR
(
MI
,
FI
,
RS
,
LIS
,
true
)
;
default
:
llvm_unreachable
(
"not an SGPR spill instruction"
)
;
}
}
</s>


<s> bool SILowerI1Copies :: runOnMachineFunction ( MachineFunction & TheMF ) { MF = & TheMF ; MRI = & MF -> getRegInfo ( ) ; DT = & getAnalysis < MachineDominatorTree > ( ) ; PDT = & getAnalysis < MachinePostDominatorTree > ( ) ; ST = & MF -> getSubtarget < GCNSubtarget > ( ) ; TII = ST -> getInstrInfo ( ) ; IsWave32 = ST -> isWave32 ( ) ; if ( IsWave32 ) { ExecReg = AMDGPU :: EXEC_LO ; MovOp = AMDGPU :: S_MOV_B32 ; AndOp = AMDGPU :: S_AND_B32 ; OrOp = AMDGPU :: S_OR_B32 ; XorOp = AMDGPU :: S_XOR_B32 ; AndN2Op = AMDGPU :: S_ANDN2_B32 ; OrN2Op = AMDGPU :: S_ORN2_B32 ; } else { ExecReg = AMDGPU :: EXEC ; MovOp = AMDGPU :: S_MOV_B64 ; AndOp = AMDGPU :: S_AND_B64 ; OrOp = AMDGPU :: S_OR_B64 ; XorOp = AMDGPU :: S_XOR_B64 ; AndN2Op = AMDGPU :: S_ANDN2_B64 ; OrN2Op = AMDGPU :: S_ORN2_B64 ; } lowerCopiesFromI1 ( ) ; lowerPhis ( ) ; lowerCopiesToI1 ( ) ; for ( unsigned Reg : ConstrainRegs ) MRI -> constrainRegClass ( Reg , & AMDGPU :: SReg_1_XEXECRegClass ) ; ConstrainRegs . clear ( ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> static void s390_register_info ( ) { int i , j ; char clobbered_regs [ 32 ] ; gcc_assert ( ! epilogue_completed ) ; if ( reload_completed ) s390_regs_ever_clobbered ( clobbered_regs ) ; else for ( i = 0 ; i < 32 ; i ++ ) clobbered_regs [ i ] = df_regs_ever_live_p ( i ) ; for ( i = 0 ; i < 32 ; i ++ ) clobbered_regs [ i ] = clobbered_regs [ i ] && ! global_regs [ i ] ; cfun_frame_layout . fpr_bitmap = 0 ; cfun_frame_layout . high_fprs = 0 ; for ( i = FPR0_REGNUM ; i <= FPR15_REGNUM ; i ++ ) if ( clobbered_regs [ i ] && ! call_really_used_regs [ i ] ) { cfun_set_fpr_save ( i ) ; if ( i >= FPR8_REGNUM ) cfun_frame_layout . high_fprs ++ ; } if ( flag_pic ) clobbered_regs [ PIC_OFFSET_TABLE_REGNUM ] |= ! ! df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) ; clobbered_regs [ BASE_REGNUM ] |= ( cfun -> machine -> base_reg && REGNO ( cfun -> machine -> base_reg ) == BASE_REGNUM ) ; clobbered_regs [ HARD_FRAME_POINTER_REGNUM ] |= ! ! frame_pointer_needed ; clobbered_regs [ RETURN_REGNUM ] |= ( ! crtl -> is_leaf || TARGET_TPF_PROFILING || cfun -> machine -> split_branches_pending_p || cfun_frame_layout . save_return_addr_p || crtl -> calls_eh_return ) ; clobbered_regs [ STACK_POINTER_REGNUM ] |= ( ! crtl -> is_leaf || TARGET_TPF_PROFILING || cfun_save_high_fprs_p || get_frame_size ( ) > 0 || ( reload_completed && cfun_frame_layout . frame_size > 0 ) || cfun -> calls_alloca ) ; memset ( cfun_frame_layout . gpr_save_slots , 0 , 16 ) ; for ( i = 6 ; i < 16 ; i ++ ) if ( clobbered_regs [ i ] ) cfun_gpr_save_slot ( i ) = - 1 ; s390_register_info_stdarg_fpr ( ) ; s390_register_info_gprtofpr ( ) ; for ( i = 0 ; i < 16 && cfun_gpr_save_slot ( i ) != - 1 ; i ++ ) ; for ( j = 15 ; j > i && cfun_gpr_save_slot ( j ) != - 1 ; j -- ) ; cfun_frame_layout . first_restore_gpr = ( i == 16 ) ? - 1 : i ; cfun_frame_layout . last_restore_gpr = ( i == 16 ) ? - 1 : j ; s390_register_info_stdarg_gpr ( ) ; for ( i = 0 ; i < 16 && cfun_gpr_save_slot ( i ) != - 1 ; i ++ ) ; for ( j = 15 ; j > i && cfun_gpr_save_slot ( j ) != - 1 ; j -- ) ; cfun_frame_layout . first_save_gpr = ( i == 16 ) ? - 1 : i ; cfun_frame_layout . last_save_gpr = ( i == 16 ) ? - 1 : j ; } </s>

Fill cfun- > machine with info about register usage of current function . Return in CLOBBERED_REGS which GPRs are currently considered set .


<s> MVT X86TargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i1 && Subtarget . hasAVX512 ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; MVT RegisterVT ; unsigned NumRegisters ; std :: tie ( RegisterVT , NumRegisters ) = handleMaskRegisterForCallingConv ( NumElts , CC , Subtarget ) ; if ( RegisterVT != MVT :: INVALID_SIMPLE_VALUE_TYPE ) return RegisterVT ; } return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


<s> unsigned PPCFrameLowering :: determineFrameLayout ( MachineFunction & MF , bool UpdateMF , bool UseEstimate ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = UseEstimate ? MFI -> estimateStackSize ( MF ) : MFI -> getStackSize ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - 1 ; const PPCRegisterInfo * RegInfo = static_cast < const PPCRegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; bool DisableRedZone = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoRedZone ) ; if ( ! DisableRedZone && ( Subtarget . isPPC64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == 0 ) && FrameSize <= 224 && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! RegInfo -> hasBasePointer ( MF ) ) { if ( UpdateMF ) MFI -> setStackSize ( 0 ) ; return 0 ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( Subtarget . isPPC64 ( ) , Subtarget . isDarwinABI ( ) , Subtarget . isELFv2ABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setStackSize ( FrameSize ) ; return FrameSize ; } </s>

Determine the frame layout but do not update the machine function .


<s> bool aarch64_bitmask_imm ( HOST_WIDE_INT val_in , machine_mode mode ) { unsigned HOST_WIDE_INT val , tmp , mask , first_one , next_one ; int bits ; val = ( unsigned HOST_WIDE_INT ) val_in ; tmp = val + ( val & - val ) ; if ( tmp == ( tmp & - tmp ) ) return ( val + 1 ) > 1 ; if ( mode == SImode ) val = ( val << 32 ) | ( val & 0xffffffff ) ; if ( val & 1 ) val = ~ val ; first_one = val & - val ; tmp = val & ( val + first_one ) ; if ( tmp == 0 ) return true ; next_one = tmp & - tmp ; bits = clz_hwi ( first_one ) - clz_hwi ( next_one ) ; mask = val ^ tmp ; if ( ( mask >> bits ) != 0 || bits != ( bits & - bits ) ) return false ; return val == mask * bitmask_imm_mul [ __builtin_clz ( bits ) - 26 ] ; } </s>

Return true if val is a valid bitmask immediate .


<s> unsigned MCS51InstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : { const MCInstrDesc & Desc = get ( Opcode ) ; return Desc . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return 0 ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MCS51TargetMachine & TM = static_cast < const MCS51TargetMachine & > ( MF . getTarget ( ) ) ; const MCS51Subtarget & STI = MF . getSubtarget < MCS51Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; return TII . getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool ARMBaseRegisterInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( NoFramePointerElim || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void M88kTargetELFStreamer :: finish ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( Requires88110 ) EFlags |= ELF :: EF_88K_M88110 ; MCA . setELFHeaderEFlags ( EFlags ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> void EmitInstruction ( uint64_t Val , unsigned Size , raw_ostream & OS ) const { for ( unsigned i = 0 ; i < Size ; ++ i ) { unsigned Shift = ( Size - 1 - i ) * 8 ; EmitByte ( ( Val >> Shift ) & 0xff , OS ) ; } } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


"FixAllFDIVSQRT: Erratum Fix LBR34: fix FDIVS/FDIVD/FSQRTS/FSQRTD instructions with NOPs and floating-point store"

getPassName - Return a nice clean name for a pass .


"Switch should handle all register classes"


<s> static bool aarch64_composite_type_p ( const_tree type , machine_mode mode ) { if ( type && ( AGGREGATE_TYPE_P ( type ) || TREE_CODE ( type ) == COMPLEX_TYPE ) ) return true ; if ( mode == BLKmode || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_INT ) return true ; return false ; } </s>

Return TRUE if the type , as described by TYPE and MODE , is a composite type as described in AAPCS64 \S 4.3 . This includes aggregate , union and array types . The C99 floating-point complex types are also considered as composite types , according to AAPCS64 \S 7.1.1 . The complex integer types , which are GCC extensions and out of the scope of AAPCS64 , are treated as composite types here as well . Note that MODE itself is not sufficient in determining whether a type is such a composite type or not . This is because stor-layout.c : compute_record_mode may have already changed the MODE ( BLKmode ) of a RECORD_TYPE TYPE to some other mode . For example , a structure with only one field may have its MODE set to the mode of the field . Also an integer mode whose size matches the size of the RECORD_TYPE type may be used to substitute the original mode ( i.e . BLKmode ) in certain circumstances . In other words , MODE can not be solely relied on .


<s> void AMDGPUTargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { switch ( N -> getOpcode ( ) ) { case ISD :: SIGN_EXTEND_INREG : return ; case ISD :: LOAD : { SDNode * Node = LowerLOAD ( SDValue ( N , 0 ) , DAG ) . getNode ( ) ; if ( ! Node ) return ; Results . push_back ( SDValue ( Node , 0 ) ) ; Results . push_back ( SDValue ( Node , 1 ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( N , 1 ) , SDValue ( Node , 1 ) ) ; return ; } case ISD :: STORE : { SDValue Lowered = LowerSTORE ( SDValue ( N , 0 ) , DAG ) ; if ( Lowered . getNode ( ) ) Results . push_back ( Lowered ) ; return ; } default : return ; } } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s>
void
AArch64RegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected"
)
;
MachineInstr
&
MI
=
*
II
;
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
AArch64InstrInfo
*
TII
=
MF
.
getSubtarget
<
AArch64Subtarget
>
(
)
.
getInstrInfo
(
)
;
const
AArch64FrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
unsigned
FrameReg
;
int
Offset
;
if
(
MI
.
isDebugValue
(
)
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
STACKMAP
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
PATCHPOINT
)
{
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
,
true
)
;
Offset
+=
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
)
;
return
;
}
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
)
;
if
(
MI
.
getOpcode
(
)
==
TargetOpcode
::
LOCAL_ESCAPE
)
{
MachineOperand
&
FI
=
MI
.
getOperand
(
FIOperandNum
)
;
FI
.
ChangeToImmediate
(
Offset
)
;
return
;
}
if
(
rewriteAArch64FrameIndex
(
MI
,
FIOperandNum
,
FrameReg
,
Offset
,
TII
)
)
return
;
assert
(
(
!
RS
||
!
RS
->
isScavengingFrameIndex
(
FrameIndex
)
)
&&
"Emergency spill slot is out of reach"
)
;
unsigned
ScratchReg
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
&
AArch64
::
GPR64RegClass
)
;
emitFrameOffset
(
MBB
,
II
,
MI
.
getDebugLoc
(
)
,
ScratchReg
,
FrameReg
,
Offset
,
TII
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
ScratchReg
,
false
,
false
,
true
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s>
void
mep_asm_output_opcode
(
FILE
*
file
,
const
char
*
ptr
)
{
int
this_opcode
=
op_none
;
const
char
*
hazard
=
0
;
switch
(
*
ptr
)
{
case
'f'
:
if
(
strncmp
(
ptr
,
"fsft"
,
4
)
==
0
&&
!
ISGRAPH
(
ptr
[
4
]
)
)
this_opcode
=
op_fsft
;
break
;
case
'r'
:
if
(
strncmp
(
ptr
,
"ret"
,
3
)
==
0
&&
!
ISGRAPH
(
ptr
[
3
]
)
)
this_opcode
=
op_ret
;
break
;
case
's'
:
if
(
strncmp
(
ptr
,
"stc"
,
3
)
==
0
&&
!
ISGRAPH
(
ptr
[
3
]
)
)
this_opcode
=
op_stc
;
break
;
}
if
(
prev_opcode
==
op_stc
&&
this_opcode
==
op_fsft
)
hazard
=
"nop"
;
if
(
prev_opcode
==
op_stc
&&
this_opcode
==
op_ret
)
hazard
=
"nop"
;
if
(
hazard
)
fprintf
(
file
,
"%s\t# %s-%s hazard\n\t"
,
hazard
,
opnames
[
prev_opcode
]
,
opnames
[
this_opcode
]
)
;
prev_opcode
=
this_opcode
;
}
</s>

This is n't as optimal as it could be , because we do n't know what control register the STC opcode is storing in . We only need to add the nop if it 's the relevant register , but we add it for irrelevant registers also .


<s> static Optional < unsigned > getTag ( const TargetRegisterInfo * TRI , const MachineInstr & MI , const LoadInfo & LI ) { unsigned Dest = LI . DestReg ? TRI -> getEncodingValue ( LI . DestReg ) : 0 ; unsigned Base = TRI -> getEncodingValue ( LI . BaseReg ) ; unsigned Off ; if ( LI . OffsetOpnd == nullptr ) Off = 0 ; else if ( LI . OffsetOpnd -> isGlobal ( ) || LI . OffsetOpnd -> isSymbol ( ) || LI . OffsetOpnd -> isCPI ( ) ) return None ; else if ( LI . OffsetOpnd -> isReg ( ) ) Off = ( 1 << 5 ) | TRI -> getEncodingValue ( LI . OffsetOpnd -> getReg ( ) ) ; else Off = LI . OffsetOpnd -> getImm ( ) >> 2 ; return makeTag ( Dest , Base , Off ) ; } </s>

getTag - Return an opaque tag representing the current state of the union .


<s> bool SystemZTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { if ( Subtarget . hasVector ( ) ) VerifyVectorTypes ( Outs ) ; for ( auto & Out : Outs ) if ( Out . ArgVT == MVT :: i128 ) return false ; SmallVector < CCValAssign , 16 > RetLocs ; CCState RetCCInfo ( CallConv , isVarArg , MF , RetLocs , Context ) ; return RetCCInfo . CheckReturn ( Outs , RetCC_SystemZ ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .

SystemZ SystemZ ISD::OutputArg MVT::i128 16 SystemZ


<s> bool gw_consumed_by_ex_dep_p ( rtx_insn * consumer , rtx def_reg ) { rtx use_rtx ; switch ( get_attr_type ( consumer ) ) { case TYPE_ALU : case TYPE_PBSAD : case TYPE_MUL : case TYPE_DALU : case TYPE_DALU64 : case TYPE_DMUL : case TYPE_DPACK : case TYPE_DINSB : case TYPE_DCMP : case TYPE_DCLIP : case TYPE_DALUROUND : use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_ALU_SHIFT : use_rtx = extract_shift_reg ( consumer ) ; break ; case TYPE_PBSADA : return pbsada_insn_ra_rb_dep_reg_p ( consumer , def_reg ) ; case TYPE_MAC : case TYPE_DMAC : use_rtx = extract_mac_non_acc_rtx ( consumer ) ; break ; case TYPE_DIV : if ( divmod_p ( consumer ) ) use_rtx = SET_SRC ( parallel_element ( consumer , 0 ) ) ; else use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_DWEXT : return wext_odd_dep_p ( consumer , def_reg ) ; case TYPE_DBPICK : return bpick_ra_rb_dep_p ( consumer , def_reg ) ; case TYPE_MMU : if ( GET_CODE ( PATTERN ( consumer ) ) == SET ) use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; else return true ; break ; case TYPE_LOAD : case TYPE_STORE : use_rtx = extract_mem_rtx ( consumer ) ; break ; case TYPE_LOAD_MULTIPLE : case TYPE_STORE_MULTIPLE : use_rtx = extract_base_reg ( consumer ) ; break ; case TYPE_BRANCH : use_rtx = PATTERN ( consumer ) ; break ; default : gcc_unreachable ( ) ; } if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; return false ; } </s>

Check the dependency between the producer defining DEF_REG and CONSUMER requiring input operand at EX .


<s> bool mprocTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { return false ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .


<s> const MCPhysReg * MipsRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const MipsSubtarget & Subtarget = MF -> getSubtarget < MipsSubtarget > ( ) ; const Function & F = MF -> getFunction ( ) ; if ( F . hasFnAttribute ( "interrupt" ) ) { if ( Subtarget . hasMips64 ( ) ) return Subtarget . hasMips64r6 ( ) ? CSR_Interrupt_64R6_SaveList : CSR_Interrupt_64_SaveList ; else return Subtarget . hasMips32r6 ( ) ? CSR_Interrupt_32R6_SaveList : CSR_Interrupt_32_SaveList ; } if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_SaveList ; if ( Subtarget . isABI_CheriPureCap ( ) ) return CSR_Cheri_Purecap_SaveList ; if ( Subtarget . isCheri ( ) ) return CSR_N64_Cheri_SaveList ; if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_SaveList ; if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_SaveList ; if ( Subtarget . isFP64bit ( ) ) return CSR_O32_FP64_SaveList ; if ( Subtarget . isFPXX ( ) ) return CSR_O32_FPXX_SaveList ; return CSR_O32_SaveList ; } </s>

Mips Mips Mips Mips "interrupt" Mips Mips Mips


<s> SDValue TMS320C64XLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > ret_locs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , ret_locs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_TMS320C64X ) ; for ( unsigned i = 0 ; i < ret_locs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , ret_locs [ i ] . getLocReg ( ) , ret_locs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static rtx frame_move ( rtx dst , rtx src ) { rtx tmp = gen_rtx_SET ( dst , src ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; return frame_insn ( tmp ) ; } </s>


<s> bool SITargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , Align Alignment , MachineMemOperand :: Flags Flags , bool * IsFast ) const { if ( IsFast ) * IsFast = false ; if ( VT == MVT :: Other || ( VT != MVT :: Other && VT . getSizeInBits ( ) > 1024 && VT . getStoreSize ( ) > 16 ) ) { return false ; } bool Allow = allowsMisalignedMemoryAccessesImpl ( VT . getSizeInBits ( ) , AddrSpace , Alignment , Flags , IsFast ) ; if ( Allow && IsFast && Subtarget -> hasUnalignedDSAccessEnabled ( ) && ( AddrSpace == AMDGPUAS :: LOCAL_ADDRESS || AddrSpace == AMDGPUAS :: REGION_ADDRESS ) ) { * IsFast = true ; } return Allow ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .

AMDGPU SI MVT::Other MVT::Other 1024 16 AMDGPU AMDGPU


<s> bool SIFoldOperands :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; MRI = & MF . getRegInfo ( ) ; ST = & MF . getSubtarget < SISubtarget > ( ) ; TII = ST -> getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ; MachineBasicBlock :: iterator I , Next ; for ( I = MBB . begin ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; if ( ! isSafeToFold ( MI ) ) { tryFoldClamp ( MI ) ; continue ; } MachineOperand & OpToFold = MI . getOperand ( 1 ) ; bool FoldingImm = OpToFold . isImm ( ) || OpToFold . isFI ( ) ; if ( ! FoldingImm && ! OpToFold . isReg ( ) ) continue ; if ( OpToFold . isReg ( ) && ! TargetRegisterInfo :: isVirtualRegister ( OpToFold . getReg ( ) ) ) continue ; MachineOperand & Dst = MI . getOperand ( 0 ) ; if ( Dst . isReg ( ) && ! TargetRegisterInfo :: isVirtualRegister ( Dst . getReg ( ) ) ) continue ; foldInstOperand ( MI , OpToFold ) ; } } return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> static unsigned int arc_compute_frame_size ( void ) { int regno ; unsigned int total_size , var_size , args_size , pretend_size , extra_size ; unsigned int reg_size , reg_offset ; unsigned int gmask ; struct arc_frame_info * frame_info ; int size ; if ( cfun -> machine -> frame_info . initialized ) return cfun -> machine -> frame_info . total_size ; frame_info = & cfun -> machine -> frame_info ; size = ARC_STACK_ALIGN ( get_frame_size ( ) ) ; var_size = size ; args_size = crtl -> outgoing_args_size ; reg_size = 0 ; gmask = 0 ; for ( regno = 0 ; regno <= 31 ; regno ++ ) { if ( arc_must_save_register ( regno , cfun ) ) { reg_size += UNITS_PER_WORD ; gmask |= 1L << regno ; } } if ( crtl -> calls_eh_return ) for ( regno = 0 ; EH_RETURN_DATA_REGNO ( regno ) != INVALID_REGNUM ; regno ++ ) { reg_size += UNITS_PER_WORD ; gmask |= 1 << regno ; } frame_info -> save_return_addr = ( ! crtl -> is_leaf || df_regs_ever_live_p ( RETURN_ADDR_REGNUM ) || crtl -> calls_eh_return ) ; if ( optimize_size && ! TARGET_NO_MILLICODE_THUNK_SET && ! crtl -> calls_eh_return ) { if ( arc_compute_millicode_save_restore_regs ( gmask , frame_info ) ) frame_info -> save_return_addr = true ; } extra_size = 0 ; if ( arc_must_save_return_addr ( cfun ) ) extra_size = 4 ; if ( arc_frame_pointer_needed ( ) ) extra_size += 4 ; pretend_size = crtl -> args . pretend_args_size ; { unsigned int extra_plus_reg_size ; unsigned int extra_plus_reg_size_aligned ; extra_plus_reg_size = extra_size + reg_size ; extra_plus_reg_size_aligned = ARC_STACK_ALIGN ( extra_plus_reg_size ) ; reg_size = extra_plus_reg_size_aligned - extra_size ; } total_size = var_size + args_size + extra_size + pretend_size + reg_size ; gcc_assert ( total_size == ARC_STACK_ALIGN ( total_size ) ) ; reg_offset = ( total_size - ( pretend_size + reg_size + extra_size ) + ( arc_frame_pointer_needed ( ) ? 4 : 0 ) ) ; frame_info -> total_size = total_size ; frame_info -> extra_size = extra_size ; frame_info -> pretend_size = pretend_size ; frame_info -> var_size = var_size ; frame_info -> args_size = args_size ; frame_info -> reg_size = reg_size ; frame_info -> reg_offset = reg_offset ; frame_info -> gmask = gmask ; frame_info -> initialized = reload_completed ; return total_size ; } </s>

Return the bytes needed to compute the frame pointer from the current stack pointer . SIZE is the size needed for local variables .


Implement the allocate_stack pattern ( alloca ) .


<s> void SIInstrInfo :: moveToVALU ( MachineInstr & TopInst ) const { SmallVector < MachineInstr * , 128 > Worklist ; Worklist . push_back ( & TopInst ) ; while ( ! Worklist . empty ( ) ) { MachineInstr * Inst = Worklist . pop_back_val ( ) ; unsigned NewOpcode = getVALUOp ( * Inst ) ; if ( NewOpcode == AMDGPU :: INSTRUCTION_LIST_END ) continue ; MachineRegisterInfo & MRI = Inst -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const MCInstrDesc & NewDesc = get ( NewOpcode ) ; Inst -> setDesc ( NewDesc ) ; for ( unsigned i = Inst -> getNumOperands ( ) - 1 ; i > 0 ; -- i ) { MachineOperand & Op = Inst -> getOperand ( i ) ; if ( Op . isReg ( ) && Op . getReg ( ) == AMDGPU :: SCC ) Inst -> RemoveOperand ( i ) ; } if ( NewDesc . ImplicitUses ) { for ( unsigned i = 0 ; NewDesc . ImplicitUses [ i ] ; ++ i ) { unsigned Reg = NewDesc . ImplicitUses [ i ] ; Inst -> addOperand ( MachineOperand :: CreateReg ( Reg , false , true ) ) ; } } if ( NewDesc . ImplicitDefs ) { for ( unsigned i = 0 ; NewDesc . ImplicitDefs [ i ] ; ++ i ) { unsigned Reg = NewDesc . ImplicitDefs [ i ] ; Inst -> addOperand ( MachineOperand :: CreateReg ( Reg , true , true ) ) ; } } legalizeOperands ( Inst ) ; const TargetRegisterClass * NewDstRC = getOpRegClass ( * Inst , 0 ) ; switch ( Inst -> getOpcode ( ) ) { case AMDGPU :: COPY : case AMDGPU :: PHI : case AMDGPU :: REG_SEQUENCE : if ( RI . hasVGPRs ( NewDstRC ) ) continue ; NewDstRC = RI . getEquivalentVGPRClass ( NewDstRC ) ; if ( ! NewDstRC ) continue ; break ; default : break ; } unsigned DstReg = Inst -> getOperand ( 0 ) . getReg ( ) ; unsigned NewDstReg = MRI . createVirtualRegister ( NewDstRC ) ; MRI . replaceRegWith ( DstReg , NewDstReg ) ; for ( MachineRegisterInfo :: use_iterator I = MRI . use_begin ( NewDstReg ) , E = MRI . use_end ( ) ; I != E ; ++ I ) { MachineInstr & UseMI = * I ; if ( ! canReadVGPR ( UseMI , I . getOperandNo ( ) ) ) { Worklist . push_back ( & UseMI ) ; } } } } </s>

Replace the instructions opcode with the equivalent VALU opcode .


<s> static bool xtensa_emit_add_imm ( rtx dst , rtx src , HOST_WIDE_INT imm , rtx scratch , bool need_note ) { bool retval = false ; HOST_WIDE_INT v [ 2 ] ; rtx_insn * insn ; if ( imm == 0 ) return false ; if ( xtensa_simm8 ( imm ) || xtensa_simm8x256 ( imm ) ) insn = emit_insn ( gen_addsi3 ( dst , src , GEN_INT ( imm ) ) ) ; else if ( xtensa_split_imm_two_addends ( imm , v ) ) { if ( ! scratch ) scratch = gen_reg_rtx ( SImode ) ; emit_insn ( gen_addsi3 ( scratch , src , GEN_INT ( v [ 0 ] ) ) ) ; insn = emit_insn ( gen_addsi3 ( dst , scratch , GEN_INT ( v [ 1 ] ) ) ) ; } else { if ( scratch ) emit_move_insn ( scratch , GEN_INT ( imm ) ) ; else scratch = force_reg ( SImode , GEN_INT ( imm ) ) ; retval = true ; insn = emit_insn ( gen_addsi3 ( dst , src , scratch ) ) ; } if ( need_note ) { rtx note_rtx = gen_rtx_SET ( dst , plus_constant ( Pmode , src , imm ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , note_rtx ) ; } return retval ; } </s>

Helper function for integer immediate addition with scratch register as needed , that splits and emits either up to two ADDI/ADDMI machine instructions or an addition by register following an integer immediate load ( which may later be transformed by constantsynth ) . If 'scratch ' is NULL_RTX but still needed , a new pseudo-register will be allocated . Thus , after the reload/LRA pass , the specified scratch register must be a hard one .


<s> SDValue Cpu0TargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BRCOND : return LowerBRCOND ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: VASTART : return LowerVASTART ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> static unsigned getReg ( const MCDisassembler * D , unsigned RC , unsigned RegNo ) { const MCRegisterInfo * RegInfo = D -> getContext ( ) . getRegisterInfo ( ) ; return * ( RegInfo -> getRegClass ( RC ) . begin ( ) + RegNo ) ; } </s>

Returns the register associated with this edge .


<s> virtual uint64_t getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups ) const { return 0 ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s>
static
void
rs6000_print_options_internal
(
FILE
*
file
,
int
indent
,
const
char
*
string
,
HOST_WIDE_INT
flags
,
const
char
*
prefix
,
const
struct
rs6000_opt_mask
*
opts
,
size_t
num_elements
)
{
size_t
i
;
size_t
start_column
=
0
;
size_t
cur_column
;
size_t
max_column
=
120
;
size_t
prefix_len
=
strlen
(
prefix
)
;
size_t
comma_len
=
0
;
const
char
*
comma
=
""
;
if
(
indent
)
start_column
+=
fprintf
(
file
,
"%*s"
,
indent
,
""
)
;
if
(
!
flags
)
{
fprintf
(
stderr
,
DEBUG_FMT_S
,
string
,
"<none>"
)
;
return
;
}
start_column
+=
fprintf
(
stderr
,
DEBUG_FMT_WX
,
string
,
flags
)
;
cur_column
=
start_column
;
for
(
i
=
0
;
i
<
num_elements
;
i
++
)
{
bool
invert
=
opts
[
i
]
.
invert
;
const
char
*
name
=
opts
[
i
]
.
name
;
const
char
*
no_str
=
""
;
HOST_WIDE_INT
mask
=
opts
[
i
]
.
mask
;
size_t
len
=
comma_len
+
prefix_len
+
strlen
(
name
)
;
if
(
!
invert
)
{
if
(
(
flags
&
mask
)
==
0
)
{
no_str
=
"no-"
;
len
+=
sizeof
(
"no-"
)
1
;
}
flags
&=
~
mask
;
}
else
{
if
(
(
flags
&
mask
)
!=
0
)
{
no_str
=
"no-"
;
len
+=
sizeof
(
"no-"
)
1
;
}
flags
|=
mask
;
}
cur_column
+=
len
;
if
(
cur_column
>
max_column
)
{
fprintf
(
stderr
,
", \\\n%*s"
,
(
int
)
start_column
,
""
)
;
cur_column
=
start_column
+
len
;
comma
=
""
;
}
fprintf
(
file
,
"%s%s%s%s"
,
comma
,
prefix
,
no_str
,
name
)
;
comma
=
", "
;
comma_len
=
sizeof
(
", "
)
1
;
}
fputs
(
"\n"
,
file
)
;
}
</s>

Helper function to print the current isa or misc options on a line .


<s> const UPTInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s>
MachineBasicBlock
::
iterator
ARMBaseInstrInfo
::
insertOutlinedCall
(
Module
&
M
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
&
It
,
MachineFunction
&
MF
,
const
outliner
::
Candidate
&
C
)
const
{
MachineInstrBuilder
MIB
;
MachineBasicBlock
::
iterator
CallPt
;
unsigned
Opc
;
bool
isThumb
=
Subtarget
.
isThumb
(
)
;
if
(
C
.
CallConstructionID
==
MachineOutlinerTailCall
)
{
Opc
=
isThumb
Subtarget
.
isTargetMachO
(
)
ARM
::
tTAILJMPd
:
ARM
::
tTAILJMPdND
:
ARM
::
TAILJMPd
;
MIB
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
Opc
)
)
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
;
if
(
isThumb
)
MIB
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
It
=
MBB
.
insert
(
It
,
MIB
)
;
return
It
;
}
Opc
=
isThumb
ARM
::
tBL
:
ARM
::
BL
;
MachineInstrBuilder
CallMIB
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
Opc
)
)
;
if
(
isThumb
)
CallMIB
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
CallMIB
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
;
if
(
C
.
CallConstructionID
==
MachineOutlinerRegSave
)
{
unsigned
Reg
=
findRegisterToSaveLRTo
(
C
)
;
assert
(
Reg
!=
0
&&
"No callee-saved register available?"
)
;
if
(
!
MBB
.
isLiveIn
(
ARM
::
LR
)
)
MBB
.
addLiveIn
(
ARM
::
LR
)
;
copyPhysReg
(
MBB
,
It
,
DebugLoc
(
)
,
Reg
,
ARM
::
LR
,
true
)
;
CallPt
=
MBB
.
insert
(
It
,
CallMIB
)
;
copyPhysReg
(
MBB
,
It
,
DebugLoc
(
)
,
ARM
::
LR
,
Reg
,
true
)
;
It
;
return
CallPt
;
}
It
=
MBB
.
insert
(
It
,
CallMIB
)
;
return
It
;
}
</s>

Insert a call to an outlined function into the program .

ARM
ARM
ARM::tTAILJMPd
ARM::tTAILJMPdND
ARM::TAILJMPd
ARMCC::AL
ARM::tBL
ARM::BL
ARMCC::AL
0
"No callee-saved register available?"
ARM::LR
ARM::LR
ARM::LR
ARM::LR


<s> bool aarch64_operands_ok_for_ldpstp ( rtx * operands , bool load , enum machine_mode mode ) { HOST_WIDE_INT offval_1 , offval_2 , msize ; enum reg_class rclass_1 , rclass_2 ; rtx mem_1 , mem_2 , reg_1 , reg_2 , base_1 , base_2 , offset_1 , offset_2 ; if ( load ) { mem_1 = operands [ 1 ] ; mem_2 = operands [ 3 ] ; reg_1 = operands [ 0 ] ; reg_2 = operands [ 2 ] ; gcc_assert ( REG_P ( reg_1 ) && REG_P ( reg_2 ) ) ; if ( REGNO ( reg_1 ) == REGNO ( reg_2 ) ) return false ; } else { mem_1 = operands [ 0 ] ; mem_2 = operands [ 2 ] ; reg_1 = operands [ 1 ] ; reg_2 = operands [ 3 ] ; } if ( MEM_VOLATILE_P ( mem_1 ) || MEM_VOLATILE_P ( mem_2 ) ) return false ; extract_base_offset_in_addr ( mem_1 , & base_1 , & offset_1 ) ; if ( base_1 == NULL_RTX || offset_1 == NULL_RTX ) return false ; extract_base_offset_in_addr ( mem_2 , & base_2 , & offset_2 ) ; if ( base_2 == NULL_RTX || offset_2 == NULL_RTX ) return false ; if ( ! rtx_equal_p ( base_1 , base_2 ) ) return false ; offval_1 = INTVAL ( offset_1 ) ; offval_2 = INTVAL ( offset_2 ) ; msize = GET_MODE_SIZE ( mode ) ; if ( offval_1 != ( offval_2 + msize ) && offval_2 != ( offval_1 + msize ) ) return false ; if ( load ) { if ( reg_mentioned_p ( reg_1 , mem_1 ) ) return false ; if ( offval_1 > offval_2 && reg_mentioned_p ( reg_2 , mem_2 ) ) return false ; } if ( REG_P ( reg_1 ) && FP_REGNUM_P ( REGNO ( reg_1 ) ) ) rclass_1 = FP_REGS ; else rclass_1 = GENERAL_REGS ; if ( REG_P ( reg_2 ) && FP_REGNUM_P ( REGNO ( reg_2 ) ) ) rclass_2 = FP_REGS ; else rclass_2 = GENERAL_REGS ; if ( rclass_1 != rclass_2 ) return false ; return true ; } </s>

Given OPERANDS of consecutive load/store , check if we can merge them into ldp/stp . LOAD is true if they are load instructions . MODE is the mode of memory operands .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"SI Lower il Copies"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> int nds32_hard_regno_mode_ok ( int regno , machine_mode mode ) { if ( HARD_REGNO_NREGS ( regno , mode ) == 1 || ! ( ( regno ) & 1 ) ) return 1 ; return 0 ; } </s>


<s> static bool ix86_pass_by_reference ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( ( type && POINTER_BOUNDS_TYPE_P ( type ) ) || POINTER_BOUNDS_MODE_P ( mode ) ) return false ; if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) { HOST_WIDE_INT msize = GET_MODE_SIZE ( mode ) ; if ( type ) { if ( TREE_CODE ( type ) == ARRAY_TYPE ) return true ; if ( RECORD_OR_UNION_TYPE_P ( type ) ) { msize = int_size_in_bytes ( type ) ; } } return msize != 1 && msize != 2 && msize != 4 && msize != 8 ; } else if ( type && int_size_in_bytes ( type ) == - 1 ) return true ; } return false ; } </s>

A C expression that indicates when an argument must be passed by reference . If nonzero for an argument , a copy of that argument is made in memory and a pointer to the argument is passed instead of the argument itself . The pointer is passed in whatever way is appropriate for passing a pointer to that type .


<s> static rtx_insn * rs6000_emit_allocate_stack_1 ( HOST_WIDE_INT size_int , rtx orig_sp ) { rtx_insn * insn ; rtx size_rtx = GEN_INT ( - size_int ) ; if ( size_int > 32767 ) { rtx tmp_reg = gen_rtx_REG ( Pmode , 0 ) ; if ( get_last_insn ( ) == NULL_RTX ) emit_note ( NOTE_INSN_DELETED ) ; insn = emit_move_insn ( tmp_reg , size_rtx ) ; try_split ( PATTERN ( insn ) , insn , 0 ) ; size_rtx = tmp_reg ; } if ( Pmode == SImode ) insn = emit_insn ( gen_movsi_update_stack ( stack_pointer_rtx , stack_pointer_rtx , size_rtx , orig_sp ) ) ; else insn = emit_insn ( gen_movdi_di_update_stack ( stack_pointer_rtx , stack_pointer_rtx , size_rtx , orig_sp ) ) ; rtx par = PATTERN ( insn ) ; gcc_assert ( GET_CODE ( par ) == PARALLEL ) ; rtx set = XVECEXP ( par , 0 , 0 ) ; gcc_assert ( GET_CODE ( set ) == SET ) ; rtx mem = SET_DEST ( set ) ; gcc_assert ( MEM_P ( mem ) ) ; MEM_NOTRAP_P ( mem ) = 1 ; set_mem_alias_set ( mem , get_frame_alias_set ( ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( - size_int ) ) ) ) ; if ( flag_stack_clash_protection ) { add_reg_note ( insn , REG_STACK_CHECK , const0_rtx ) ; emit_insn ( gen_blockage ( ) ) ; } return insn ; } </s>

Allocate SIZE_INT bytes on the stack using a store with update style insn and set the appropriate attributes for the generated insn . Return the first insn which adjusts the stack pointer or the last insn before the stack adjustment loop . SIZE_INT is used to create the CFI note for the allocation . SIZE_RTX is an rtx containing the size of the adjustment . Note that since stacks grow to lower addresses its runtime value is -SIZE_INT . ORIG_SP contains the backchain value that must be stored at * sp .


"Stack offset for byval regs doesn't introduced anymore?"

Target-specific cleanup for formal ByVal parameters .


<s> bool X86AsmBackend :: mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const { if ( Inst . getFlags ( ) & X86 :: EXTRA_DO_NOT_RELAX ) return false ; if ( getRelaxedOpcodeBranch ( Inst , false ) != Inst . getOpcode ( ) ) return true ; if ( getRelaxedOpcodeArith ( Inst ) == Inst . getOpcode ( ) ) return false ; unsigned RelaxableOp = Inst . getNumOperands ( ) - 1 ; if ( Inst . getOperand ( RelaxableOp ) . isExpr ( ) ) return true ; return false ; } </s>

Check whether the given instruction may need relaxation .


<s> bool nios2_regno_ok_for_base_p ( int regno , bool strict_p ) { if ( ! HARD_REGISTER_NUM_P ( regno ) ) { if ( ! strict_p ) return true ; if ( ! reg_renumber ) return false ; regno = reg_renumber [ regno ] ; } return ( GP_REG_P ( regno ) || regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) ; } </s>

Return true if register REGNO is a valid base register . STRICT_P is true if REG_OK_STRICT is in effect .


<s> int expand_a_rotate ( rtx operands [ ] ) { rtx dst = operands [ 0 ] ; rtx src = operands [ 1 ] ; rtx rotate_amount = operands [ 2 ] ; enum machine_mode mode = GET_MODE ( dst ) ; if ( h8sx_classify_shift ( mode , ROTATE , rotate_amount ) == H8SX_SHIFT_UNARY ) return false ; emit_move_insn ( dst , src ) ; if ( GET_CODE ( rotate_amount ) != CONST_INT ) { rtx counter = gen_reg_rtx ( QImode ) ; rtx start_label = gen_label_rtx ( ) ; rtx end_label = gen_label_rtx ( ) ; emit_cmp_and_jump_insns ( rotate_amount , const0_rtx , LE , NULL_RTX , QImode , 0 , end_label ) ; emit_move_insn ( counter , rotate_amount ) ; emit_label ( start_label ) ; switch ( mode ) { case QImode : emit_insn ( gen_rotlqi3_1 ( dst , dst , const1_rtx ) ) ; break ; case HImode : emit_insn ( gen_rotlhi3_1 ( dst , dst , const1_rtx ) ) ; break ; case SImode : emit_insn ( gen_rotlsi3_1 ( dst , dst , const1_rtx ) ) ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen_addqi3 ( counter , counter , constm1_rtx ) ) ; emit_cmp_and_jump_insns ( counter , const0_rtx , NE , NULL_RTX , QImode , 1 , start_label ) ; emit_label ( end_label ) ; } else { switch ( mode ) { case QImode : emit_insn ( gen_rotlqi3_1 ( dst , dst , rotate_amount ) ) ; break ; case HImode : emit_insn ( gen_rotlhi3_1 ( dst , dst , rotate_amount ) ) ; break ; case SImode : emit_insn ( gen_rotlsi3_1 ( dst , dst , rotate_amount ) ) ; break ; default : gcc_unreachable ( ) ; } } return 1 ; } </s>

A rotation by a non-constant will cause a loop to be generated , in which a rotation by one bit is used . A rotation by a constant , including the one in the loop , will be taken care of by emit_a_rotate ( ) at the insn emit time .


"ARM fix for Cortex-A57 AES Erratum 1742098"


<s>
unsigned
SparcMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
if
(
MO
.
isImm
(
)
)
return
MO
.
getImm
(
)
;
assert
(
MO
.
isExpr
(
)
)
;
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
if
(
const
SparcMCExpr
*
SExpr
=
dyn_cast
<
SparcMCExpr
>
(
Expr
)
)
{
MCFixupKind
Kind
=
(
MCFixupKind
)
SExpr
->
getFixupKind
(
)
;
Fixups
.
push_back
(
MCFixup
::
create
(
0
,
Expr
,
Kind
)
)
;
return
0
;
}
int64_t
Res
;
if
(
Expr
->
evaluateAsAbsolute
(
Res
)
)
return
Res
;
llvm_unreachable
(
"Unhandled expression!"
)
;
return
0
;
}
</s>


"%qs requires an integer constant expression"

An attribute callback for the `` arm_sve_vector_bits '' attribute .


<s>
static
rtx
mips_expand_builtin_insn
(
enum
insn_code
icode
,
unsigned
int
nops
,
struct
expand_operand
*
ops
,
bool
has_target_p
)
{
if
(
!
maybe_expand_insn
(
icode
,
nops
,
ops
)
)
{
error
(
"invalid argument to built-in function"
)
;
return
has_target_p
gen_reg_rtx
(
ops
[
0
]
.
mode
)
:
const0_rtx
;
}
return
has_target_p
ops
[
0
]
.
value
:
const0_rtx
;
}
</s>

Expand instruction ICODE as part of a built-in function sequence . Use the first NOPS elements of OPS as the instruction 's operands . HAS_TARGET_P is true if operand 0 is a target ; it is false if the instruction has no target . Return the target rtx if HAS_TARGET_P , otherwise return const0_rtx .


<s> Relocator :: Result unsupported ( Relocation & pReloc , HexagonRelocator & pParent ) { return Relocator :: Unsupported ; } </s>


<s> P2TargetLowering :: ConstraintType P2TargetLowering :: getConstraintType ( StringRef Constraint ) const { return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> void rs6000_split_stack_space_check ( rtx size , rtx label ) { rtx sp = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; rtx limit = gen_reg_rtx ( Pmode ) ; rtx requested = gen_reg_rtx ( Pmode ) ; rtx cmp = gen_reg_rtx ( CCUNSmode ) ; rtx jump ; emit_insn ( gen_load_split_stack_limit ( limit ) ) ; if ( CONST_INT_P ( size ) ) emit_insn ( gen_add3_insn ( requested , sp , GEN_INT ( - INTVAL ( size ) ) ) ) ; else { size = force_reg ( Pmode , size ) ; emit_move_insn ( requested , gen_rtx_MINUS ( Pmode , sp , size ) ) ; } emit_insn ( gen_rtx_SET ( cmp , gen_rtx_COMPARE ( CCUNSmode , requested , limit ) ) ) ; jump = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_GEU ( VOIDmode , cmp , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; jump = emit_jump_insn ( gen_rtx_SET ( pc_rtx , jump ) ) ; JUMP_LABEL ( jump ) = label ; } </s>

Emit -fsplit-stack dynamic stack allocation space check .


Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU R600 AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU


<s> bool HexagonAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & OS ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , OS ) ; case 'c' : printOperand ( MI , OpNo , OS ) ; return false ; case 'L' : case 'H' : { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( ! MO . isReg ( ) ) return true ; unsigned RegNumber = MO . getReg ( ) ; if ( Hexagon :: DoubleRegsRegClass . contains ( RegNumber ) ) RegNumber = TRI -> getSubReg ( RegNumber , ExtraCode [ 0 ] == 'L' ? Hexagon :: subreg_loreg : Hexagon :: subreg_hireg ) ; OS << HexagonInstPrinter :: getRegisterName ( RegNumber ) ; return false ; } case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) OS << "i" ; return false ; } } printOperand ( MI , OpNo , OS ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static int riscv_build_integer ( struct riscv_integer_op * codes , HOST_WIDE_INT value , machine_mode mode ) { int cost = riscv_build_integer_1 ( codes , value , mode ) ; if ( value > 0 && cost > 2 ) { struct riscv_integer_op alt_codes [ RISCV_MAX_INTEGER_OPS ] ; int alt_cost , shift = clz_hwi ( value ) ; HOST_WIDE_INT shifted_val ; shifted_val = ( value << shift ) | ( ( ( ( HOST_WIDE_INT ) 1 ) << shift ) - 1 ) ; alt_cost = 1 + riscv_build_integer_1 ( alt_codes , shifted_val , mode ) ; if ( alt_cost < cost ) { alt_codes [ alt_cost - 1 ] . code = LSHIFTRT ; alt_codes [ alt_cost - 1 ] . value = shift ; memcpy ( codes , alt_codes , sizeof ( alt_codes ) ) ; cost = alt_cost ; } shifted_val = value << shift ; alt_cost = 1 + riscv_build_integer_1 ( alt_codes , shifted_val , mode ) ; if ( alt_cost < cost ) { alt_codes [ alt_cost - 1 ] . code = LSHIFTRT ; alt_codes [ alt_cost - 1 ] . value = shift ; memcpy ( codes , alt_codes , sizeof ( alt_codes ) ) ; cost = alt_cost ; } } return cost ; } </s>

Fill CODES with a sequence of rtl operations to load VALUE . Return the number of operations needed .


<s>
const
char
*
output_fp_compare
(
rtx
insn
,
rtx
*
operands
,
int
eflags_p
,
int
unordered_p
)
{
int
stack_top_dies
;
rtx
cmp_op0
,
cmp_op1
;
int
is_sse
=
SSE_REG_P
(
operands
[
0
]
)
||
SSE_REG_P
(
operands
[
1
]
)
;
if
(
eflags_p
)
{
cmp_op0
=
operands
[
0
]
;
cmp_op1
=
operands
[
1
]
;
}
else
{
cmp_op0
=
operands
[
1
]
;
cmp_op1
=
operands
[
2
]
;
}
if
(
is_sse
)
{
if
(
GET_MODE
(
operands
[
0
]
)
==
SFmode
)
if
(
unordered_p
)
return
"ucomiss\t{%1, %0|%0, %1}"
;
else
return
"comiss\t{%1, %0|%0, %1}"
;
else
if
(
unordered_p
)
return
"ucomisd\t{%1, %0|%0, %1}"
;
else
return
"comisd\t{%1, %0|%0, %1}"
;
}
gcc_assert
(
STACK_TOP_P
(
cmp_op0
)
)
;
stack_top_dies
=
find_regno_note
(
insn
,
REG_DEAD
,
FIRST_STACK_REG
)
!=
0
;
if
(
cmp_op1
==
CONST0_RTX
(
GET_MODE
(
cmp_op1
)
)
)
{
if
(
stack_top_dies
)
{
output_asm_insn
(
"ftst\n\tfnstsw\t%0"
,
operands
)
;
return
TARGET_USE_FFREEP
"ffreep\t%y1"
:
"fstp\t%y1"
;
}
else
return
"ftst\n\tfnstsw\t%0"
;
}
if
(
STACK_REG_P
(
cmp_op1
)
&&
stack_top_dies
&&
find_regno_note
(
insn
,
REG_DEAD
,
REGNO
(
cmp_op1
)
)
&&
REGNO
(
cmp_op1
)
!=
FIRST_STACK_REG
)
{
if
(
eflags_p
)
{
if
(
unordered_p
)
output_asm_insn
(
"fucomip\t{%y1, %0|%0, %y1}"
,
operands
)
;
else
output_asm_insn
(
"fcomip\t{%y1, %0|%0, %y1}"
,
operands
)
;
return
TARGET_USE_FFREEP
"ffreep\t%y0"
:
"fstp\t%y0"
;
}
else
{
if
(
unordered_p
)
return
"fucompp\n\tfnstsw\t%0"
;
else
return
"fcompp\n\tfnstsw\t%0"
;
}
}
else
{
static
const
char
*
const
alt
[
16
]
=
{
"fcom%z2\t%y2\n\tfnstsw\t%0"
,
"fcomp%z2\t%y2\n\tfnstsw\t%0"
,
"fucom%z2\t%y2\n\tfnstsw\t%0"
,
"fucomp%z2\t%y2\n\tfnstsw\t%0"
,
"ficom%z2\t%y2\n\tfnstsw\t%0"
,
"ficomp%z2\t%y2\n\tfnstsw\t%0"
,
,
,
"fcomi\t{%y1, %0|%0, %y1}"
,
"fcomip\t{%y1, %0|%0, %y1}"
,
"fucomi\t{%y1, %0|%0, %y1}"
,
"fucomip\t{%y1, %0|%0, %y1}"
,
,
,
,
}
;
int
mask
;
const
char
*
ret
;
mask
=
eflags_p
<<
3
;
mask
|=
(
GET_MODE_CLASS
(
GET_MODE
(
cmp_op1
)
)
==
MODE_INT
)
<<
2
;
mask
|=
unordered_p
<<
1
;
mask
|=
stack_top_dies
;
gcc_assert
(
mask
<
16
)
;
ret
=
alt
[
mask
]
;
gcc_assert
(
ret
)
;
return
ret
;
}
}
</s>

Output code for INSN to compare OPERANDS . EFLAGS_P is 1 when fcomi should be used and 2 when fnstsw should be used . UNORDERED_P is true when fucom should be used .


<s> InstructionCost getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: TargetCostKind CostKind , TTI :: OperandValueKind Opd1Info = TTI :: OK_AnyValue , TTI :: OperandValueKind Opd2Info = TTI :: OK_AnyValue , TTI :: OperandValueProperties Opd1PropInfo = TTI :: OP_None , TTI :: OperandValueProperties Opd2PropInfo = TTI :: OP_None , ArrayRef < const Value * > Args = ArrayRef < const Value * > ( ) , const Instruction * CxtI = nullptr ) { int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: MUL : case ISD :: SDIV : case ISD :: UDIV : case ISD :: UREM : return 64 * BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .

Lanai ISD::MUL ISD::SDIV ISD::UDIV ISD::UREM 64


<s> bool aarch64_emit_approx_sqrt ( rtx dst , rtx src , bool recp ) { machine_mode mode = GET_MODE ( dst ) ; if ( GET_MODE_INNER ( mode ) == HFmode ) { gcc_assert ( ! recp ) ; return false ; } if ( ! recp ) { if ( ! ( flag_mlow_precision_sqrt || ( aarch64_tune_params . approx_modes -> sqrt & AARCH64_APPROX_MODE ( mode ) ) ) ) return false ; if ( flag_finite_math_only || flag_trapping_math || ! flag_unsafe_math_optimizations || optimize_function_for_size_p ( cfun ) ) return false ; } else gcc_assert ( use_rsqrt_p ( mode ) ) ; machine_mode mmsk = mode_for_int_vector ( mode ) . require ( ) ; rtx xmsk = gen_reg_rtx ( mmsk ) ; if ( ! recp ) emit_insn ( gen_rtx_SET ( xmsk , gen_rtx_NEG ( mmsk , gen_rtx_EQ ( mmsk , src , CONST0_RTX ( mode ) ) ) ) ) ; rtx xdst = gen_reg_rtx ( mode ) ; emit_insn ( gen_aarch64_rsqrte ( mode , xdst , src ) ) ; int iterations = ( GET_MODE_INNER ( mode ) == DFmode ) ? 3 : 2 ; if ( ( recp && flag_mrecip_low_precision_sqrt ) || ( ! recp && flag_mlow_precision_sqrt ) ) iterations -- ; rtx x1 = gen_reg_rtx ( mode ) ; while ( iterations -- ) { rtx x2 = gen_reg_rtx ( mode ) ; emit_set_insn ( x2 , gen_rtx_MULT ( mode , xdst , xdst ) ) ; emit_insn ( gen_aarch64_rsqrts ( mode , x1 , src , x2 ) ) ; if ( iterations > 0 ) emit_set_insn ( xdst , gen_rtx_MULT ( mode , xdst , x1 ) ) ; } if ( ! recp ) { rtx xtmp = gen_reg_rtx ( mmsk ) ; emit_set_insn ( xtmp , gen_rtx_AND ( mmsk , gen_rtx_NOT ( mmsk , xmsk ) , gen_rtx_SUBREG ( mmsk , xdst , 0 ) ) ) ; emit_move_insn ( xdst , gen_rtx_SUBREG ( mode , xtmp , 0 ) ) ; emit_set_insn ( xdst , gen_rtx_MULT ( mode , xdst , src ) ) ; } emit_set_insn ( dst , gen_rtx_MULT ( mode , xdst , x1 ) ) ; return true ; } </s>

Emit instruction sequence to compute either the approximate square root or its approximate reciprocal , depending on the flag RECP , and return whether the sequence was emitted or not .


<s> BitVector MipsRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( Mips :: ZERO ) ; Reserved . set ( Mips :: AT ) ; Reserved . set ( Mips :: K0 ) ; Reserved . set ( Mips :: K1 ) ; Reserved . set ( Mips :: GP ) ; Reserved . set ( Mips :: SP ) ; Reserved . set ( Mips :: FP ) ; Reserved . set ( Mips :: RA ) ; if ( ! Subtarget . isSingleFloat ( ) ) for ( unsigned FReg = ( Mips :: F0 ) + 1 ; FReg < Mips :: F30 ; FReg += 2 ) Reserved . set ( FReg ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> SDValue LanaiTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_Lanai32 ) ; for ( unsigned I = 0 ; I != RVLocs . size ( ) ; ++ I ) { Chain = DAG . getCopyFromReg ( Chain , DL , RVLocs [ I ] . getLocReg ( ) , RVLocs [ I ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> void cris_order_for_addsi3 ( rtx * operands , int n ) { if ( MEM_P ( operands [ n ] ) ) { rtx tem = operands [ n ] ; operands [ n ] = operands [ n + 1 ] ; operands [ n + 1 ] = tem ; } } </s>

Make sure operands are in the right order for an addsi3 insn as generated by a define_split . A MEM as the first operand is n't recognized by addsi3 after reload . OPERANDS contains the operands , with the first at OPERANDS [ N ] and the second at OPERANDS [ N+1 ] .


<s> void m32r_expand_prologue ( void ) { int regno ; int frame_size ; unsigned int gmask ; int pic_reg_used = flag_pic && ( current_function_uses_pic_offset_table | current_function_profile ) ; if ( ! current_frame_info . initialized ) m32r_compute_frame_size ( get_frame_size ( ) ) ; gmask = current_frame_info . gmask ; gcc_assert ( current_frame_info . total_size || ! gmask ) ; if ( current_frame_info . pretend_size != 0 ) { HOST_WIDE_INT pretend_size = current_frame_info . pretend_size ; emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - pretend_size ) ) ) ; } if ( current_frame_info . save_fp ) emit_insn ( gen_movsi_push ( stack_pointer_rtx , frame_pointer_rtx ) ) ; gmask &= ~ ( FRAME_POINTER_MASK | RETURN_ADDR_MASK ) ; for ( regno = 0 ; regno <= M32R_MAX_INT_REGS ; ++ regno ) { if ( ( gmask & ( 1 << regno ) ) != 0 ) emit_insn ( gen_movsi_push ( stack_pointer_rtx , gen_rtx_REG ( Pmode , regno ) ) ) ; } if ( current_frame_info . save_lr ) emit_insn ( gen_movsi_push ( stack_pointer_rtx , gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ) ) ; frame_size = ( current_frame_info . total_size - ( current_frame_info . pretend_size + current_frame_info . reg_size ) ) ; if ( frame_size == 0 ) ; else if ( frame_size <= 32768 ) emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - frame_size ) ) ) ; else { rtx tmp = gen_rtx_REG ( Pmode , PROLOGUE_TMP_REGNUM ) ; emit_insn ( gen_movsi ( tmp , GEN_INT ( frame_size ) ) ) ; emit_insn ( gen_subsi3 ( stack_pointer_rtx , stack_pointer_rtx , tmp ) ) ; } if ( frame_pointer_needed ) emit_insn ( gen_movsi ( frame_pointer_rtx , stack_pointer_rtx ) ) ; if ( current_function_profile ) emit_insn ( gen_movsi_push ( stack_pointer_rtx , gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ) ) ; if ( pic_reg_used ) { m32r_load_pic_register ( ) ; m32r_reload_lr ( stack_pointer_rtx , ( current_function_profile ? 0 : frame_size ) ) ; } if ( current_function_profile && ! pic_reg_used ) emit_insn ( gen_blockage ( ) ) ; } </s>

Expand the m32r prologue as a series of insns .


<s> static rtx riscv_force_address ( rtx x , machine_mode mode ) { if ( ! riscv_legitimate_address_p ( mode , x , false ) ) x = force_reg ( Pmode , x ) ; return x ; } </s>

If X is not a valid address for mode MODE , force it into a register .


<s> static void emitSPUpdate ( bool isARM , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const DebugLoc & dl , const ARMBaseInstrInfo & TII , int NumBytes , unsigned MIFlags = MachineInstr :: NoFlags , ARMCC :: CondCodes Pred = ARMCC :: AL , unsigned PredReg = 0 ) { emitRegPlusImmediate ( isARM , MBB , MBBI , dl , TII , ARM :: SP , ARM :: SP , NumBytes , MIFlags , Pred , PredReg ) ; } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .

ARM ARM ARM ARMCC::CondCodes ARMCC::AL 0 ARM ARM::SP ARM::SP


<s> int m68hc11_function_arg_padding ( enum machine_mode mode , tree type ) { if ( type != 0 && AGGREGATE_TYPE_P ( type ) ) return upward ; return DEFAULT_FUNCTION_ARG_PADDING ( mode , type ) ; } </s>

If defined , a C expression which determines whether , and in which direction , to pad out an argument with extra space . The value should be of type ` enum direction ' : either ` upward ' to pad above the argument , ` downward ' to pad below , or ` none ' to inhibit padding . Structures are stored left shifted in their argument slot .


<s> void AMDGPUDAGToDAGISel :: PostprocessISelDAG ( ) { const AMDGPUTargetLowering & Lowering = * static_cast < const AMDGPUTargetLowering * > ( getTargetLowering ( ) ) ; bool IsModified = false ; do { IsModified = false ; SelectionDAG :: allnodes_iterator Position = CurDAG -> allnodes_begin ( ) ; while ( Position != CurDAG -> allnodes_end ( ) ) { SDNode * Node = & * Position ++ ; MachineSDNode * MachineNode = dyn_cast < MachineSDNode > ( Node ) ; if ( ! MachineNode ) continue ; SDNode * ResNode = Lowering . PostISelFolding ( MachineNode , * CurDAG ) ; if ( ResNode != Node ) { if ( ResNode ) ReplaceUses ( Node , ResNode ) ; IsModified = true ; } } CurDAG -> RemoveDeadNodes ( ) ; } while ( IsModified ) ; } </s>

PostprocessISelDAG ( ) - This hook allows the target to hack on the graph right after selection .


<s> void msp430_output_aligned_decl_common ( FILE * stream , const tree decl , const char * name , unsigned HOST_WIDE_INT size , unsigned int align ) { if ( msp430_data_region == ANY ) { fprintf ( stream , COMMON_ASM_OP ) ; assemble_name ( stream , name ) ; fprintf ( stream , "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n" , size , align / BITS_PER_UNIT ) ; } else { section * sec ; if ( decl ) sec = msp430_select_section ( decl , 0 , align ) ; else switch ( msp430_data_region ) { case UPPER : sec = get_named_section ( NULL , ".upper.bss" , 0 ) ; break ; case LOWER : sec = get_named_section ( NULL , ".lower.bss" , 0 ) ; break ; case EITHER : sec = get_named_section ( NULL , ".either.bss" , 0 ) ; break ; default : gcc_unreachable ( ) ; } gcc_assert ( sec != NULL ) ; switch_to_section ( sec ) ; ASM_OUTPUT_ALIGN ( stream , floor_log2 ( align / BITS_PER_UNIT ) ) ; targetm . asm_out . globalize_label ( stream , name ) ; ASM_WEAKEN_LABEL ( stream , name ) ; ASM_OUTPUT_LABEL ( stream , name ) ; ASM_OUTPUT_SKIP ( stream , size ? size : 1 ) ; } } </s>

Emit a declaration of a common symbol . If a data region is in use then put the symbol into the equivalent .bss section instead . If LOCAL is 1 , then DECL is for a local common variable .


<s>
SDNode
*
RISCVDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
SDLoc
DL
(
Node
)
;
DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
return
0
;
}
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
switch
(
Opcode
)
{
case
ISD
::
FrameIndex
:
{
SDValue
imm
=
CurDAG
->
getTargetConstant
(
0
,
DL
,
Subtarget
.
isRV64
(
)
MVT
::
i64
:
MVT
::
i32
)
;
int
FI
=
cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
getTargetLowering
(
)
->
getPointerTy
(
CurDAG
->
getDataLayout
(
)
)
)
;
unsigned
Opc
=
Subtarget
.
isRV64
(
)
RISCV
::
ADDI64
:
RISCV
::
ADDI
;
EVT
VT
=
Subtarget
.
isRV64
(
)
MVT
::
i64
:
MVT
::
i32
;
if
(
Node
->
hasOneUse
(
)
)
return
CurDAG
->
SelectNodeTo
(
Node
,
Opc
,
VT
,
TFI
,
imm
)
;
return
CurDAG
->
getMachineNode
(
Opc
,
DL
,
VT
,
TFI
,
imm
)
;
}
}
SDNode
*
ResNode
=
SelectCode
(
Node
)
;
DEBUG
(
errs
(
)
<<
"=> "
;
if
(
ResNode
==
||
ResNode
==
Node
)
Node
->
dump
(
CurDAG
)
;
else
ResNode
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
;
)
;
return
ResNode
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> void JVMFunctionInfo :: Initialize ( ) { EmitGlobConsts = false ; NumArguments = 0 ; StackLimit = 0 ; LocalsLimit = 0 ; } </s>

This method must be called before any actual lowering is done .


<s>
bool
AArch64TargetLowering
::
isFPImmLegal
(
const
APFloat
&
Imm
,
EVT
VT
,
bool
OptForSize
)
const
{
bool
IsLegal
=
false
;
const
APInt
ImmInt
=
Imm
.
bitcastToAPInt
(
)
;
if
(
VT
==
MVT
::
f64
)
IsLegal
=
AArch64_AM
::
getFP64Imm
(
ImmInt
)
!=
1
||
Imm
.
isPosZero
(
)
;
else
if
(
VT
==
MVT
::
f32
)
IsLegal
=
AArch64_AM
::
getFP32Imm
(
ImmInt
)
!=
1
||
Imm
.
isPosZero
(
)
;
else
if
(
VT
==
MVT
::
f16
&&
Subtarget
->
hasFullFP16
(
)
)
IsLegal
=
AArch64_AM
::
getFP16Imm
(
ImmInt
)
!=
1
||
Imm
.
isPosZero
(
)
;
if
(
!
IsLegal
&&
(
VT
==
MVT
::
f64
||
VT
==
MVT
::
f32
)
)
{
SmallVector
<
AArch64_IMM
::
ImmInsnModel
,
4
>
Insn
;
AArch64_IMM
::
expandMOVImm
(
ImmInt
.
getZExtValue
(
)
,
VT
.
getSizeInBits
(
)
,
Insn
)
;
unsigned
Limit
=
(
OptForSize
1
:
(
Subtarget
->
hasFuseLiterals
(
)
5
:
2
)
)
;
IsLegal
=
Insn
.
size
(
)
<=
Limit
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
(
IsLegal
"Legal "
:
"Illegal "
)
<<
VT
.
getEVTString
(
)
<<
" imm value: "
;
Imm
.
dump
(
)
;
)
;
return
IsLegal
;
}
</s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < TOYSubtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


getTargetNodeName - This method returns the name of a target specific


"Can't return value from vararg function in memory"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static void seh_emit_stackalloc ( FILE * f , struct seh_frame_state * seh , HOST_WIDE_INT offset ) { gcc_assert ( offset < 0 ) ; offset = - offset ; if ( seh -> cfa_reg == stack_pointer_rtx ) seh -> cfa_offset += offset ; seh -> sp_offset += offset ; if ( offset < SEH_MAX_FRAME_SIZE ) fprintf ( f , "\t.seh_stackalloc\t" HOST_WIDE_INT_PRINT_DEC "\n" , offset ) ; } </s>

Emit an assembler directive to adjust RSP by OFFSET .


"Only support MVT::i32 register passing"

"Can only pass arguments as either registers or via the stack"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


"call/return and return/return must be 6 bytes apart to avoid mispredict"

"Long unaligned jump avoids non-delay slot penalty"

We are about to output a return insn . Add padding if necessary to avoid a mispredict . A return could happen immediately after the function start , but after a call we know that there will be at least a blink restore .


<s> void EmitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) override { EmitA64MappingSymbol ( ) ; MCELFStreamer :: EmitInstruction ( Inst , STI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static bool avr_class_likely_spilled_p ( reg_class_t c ) { return ( c != ALL_REGS && ( AVR_TINY ? 1 : c != ADDW_REGS ) ) ; } </s>

Return value is nonzero if pseudos that have been assigned to registers of class CLASS would likely be spilled because registers of CLASS are needed for spill registers .


<s> MachineInstr * ARMBaseInstrInfo :: commuteInstructionImpl ( MachineInstr * MI , bool NewMI , unsigned OpIdx1 , unsigned OpIdx2 ) const { switch ( MI -> getOpcode ( ) ) { case ARM :: MOVCCr : case ARM :: t2MOVCCr : { unsigned PredReg = 0 ; ARMCC :: CondCodes CC = getInstrPredicate ( MI , PredReg ) ; if ( CC == ARMCC :: AL || PredReg != ARM :: CPSR ) return nullptr ; MI = TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1 , OpIdx2 ) ; if ( ! MI ) return nullptr ; MI -> getOperand ( MI -> findFirstPredOperandIdx ( ) ) . setImm ( ARMCC :: getOppositeCondition ( CC ) ) ; return MI ; } } return TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1 , OpIdx2 ) ; } </s>

Commutes the operands in the given instruction by changing the operands order and/or changing the instruction 's opcode and/or the immediate value operand .

ARM ARM ARM::MOVCCr ARM::t2MOVCCr 0 ARMCC::CondCodes ARMCC::AL ARM::CPSR ARMCC::getOppositeCondition


<s>
X86TargetMachine
::
X86TargetMachine
(
const
Target
&
T
,
const
std
::
string
&
TT
,
const
std
::
string
&
FS
,
bool
is64Bit
)
:
LLVMTargetMachine
(
T
,
TT
)
,
Subtarget
(
TT
,
FS
,
is64Bit
)
,
DataLayout
(
Subtarget
.
getDataLayout
(
)
)
,
FrameInfo
(
TargetFrameInfo
::
StackGrowsDown
,
Subtarget
.
getStackAlignment
(
)
,
(
Subtarget
.
isTargetWin64
(
)
40
:
(
Subtarget
.
is64Bit
(
)
8
:
4
)
)
)
,
InstrInfo
(
*
this
)
,
JITInfo
(
*
this
)
,
TLInfo
(
*
this
)
,
ELFWriterInfo
(
*
this
)
{
DefRelocModel
=
getRelocationModel
(
)
;
if
(
getRelocationModel
(
)
==
Reloc
::
Default
)
{
if
(
!
Subtarget
.
isTargetDarwin
(
)
)
setRelocationModel
(
Reloc
::
Static
)
;
else
if
(
Subtarget
.
is64Bit
(
)
)
setRelocationModel
(
Reloc
::
PIC_
)
;
else
setRelocationModel
(
Reloc
::
DynamicNoPIC
)
;
}
assert
(
getRelocationModel
(
)
!=
Reloc
::
Default
&&
"Relocation mode not picked"
)
;
if
(
getRelocationModel
(
)
==
Reloc
::
DynamicNoPIC
)
{
if
(
is64Bit
)
setRelocationModel
(
Reloc
::
PIC_
)
;
else
if
(
!
Subtarget
.
isTargetDarwin
(
)
)
setRelocationModel
(
Reloc
::
Static
)
;
}
if
(
getRelocationModel
(
)
==
Reloc
::
Static
&&
Subtarget
.
isTargetDarwin
(
)
&&
is64Bit
)
setRelocationModel
(
Reloc
::
PIC_
)
;
if
(
getRelocationModel
(
)
==
Reloc
::
Static
)
{
Subtarget
.
setPICStyle
(
PICStyles
::
)
;
}
else
if
(
Subtarget
.
isTargetCygMing
(
)
)
{
Subtarget
.
setPICStyle
(
PICStyles
::
)
;
}
else
if
(
Subtarget
.
isTargetDarwin
(
)
)
{
if
(
Subtarget
.
is64Bit
(
)
)
Subtarget
.
setPICStyle
(
PICStyles
::
RIPRel
)
;
else
if
(
getRelocationModel
(
)
==
Reloc
::
PIC_
)
Subtarget
.
setPICStyle
(
PICStyles
::
StubPIC
)
;
else
{
assert
(
getRelocationModel
(
)
==
Reloc
::
DynamicNoPIC
)
;
Subtarget
.
setPICStyle
(
PICStyles
::
StubDynamicNoPIC
)
;
}
}
else
if
(
Subtarget
.
isTargetELF
(
)
)
{
if
(
Subtarget
.
is64Bit
(
)
)
Subtarget
.
setPICStyle
(
PICStyles
::
RIPRel
)
;
else
Subtarget
.
setPICStyle
(
PICStyles
::
GOT
)
;
}
if
(
Subtarget
.
getPICStyle
(
)
==
PICStyles
::
)
setRelocationModel
(
Reloc
::
Static
)
;
}
</s>


<s> static rtx add_constant ( rtx x , enum machine_mode mode , rtx last_value ) { int i ; rtx lab , new , ref , newref ; for ( i = 0 ; i < pool_size ; i ++ ) { if ( x -> code == pool_vector [ i ] . value -> code && mode == pool_vector [ i ] . mode ) { if ( x -> code == CODE_LABEL ) { if ( XINT ( x , 3 ) != XINT ( pool_vector [ i ] . value , 3 ) ) continue ; } if ( rtx_equal_p ( x , pool_vector [ i ] . value ) ) { lab = new = 0 ; if ( ! last_value || ! i || ! rtx_equal_p ( last_value , pool_vector [ i - 1 ] . value ) ) { new = gen_label_rtx ( ) ; LABEL_REFS ( new ) = pool_vector [ i ] . label ; pool_vector [ i ] . label = lab = new ; } if ( lab && pool_window_label ) { newref = gen_rtx_LABEL_REF ( VOIDmode , pool_window_label ) ; ref = pool_vector [ pool_window_last ] . wend ; LABEL_NEXTREF ( newref ) = ref ; pool_vector [ pool_window_last ] . wend = newref ; } if ( new ) pool_window_label = new ; pool_window_last = i ; return lab ; } } } pool_vector [ pool_size ] . value = x ; if ( last_value && rtx_equal_p ( last_value , pool_vector [ pool_size - 1 ] . value ) ) { lab = 0 ; pool_vector [ pool_size - 1 ] . part_of_sequence_p = true ; } else lab = gen_label_rtx ( ) ; pool_vector [ pool_size ] . mode = mode ; pool_vector [ pool_size ] . label = lab ; pool_vector [ pool_size ] . wend = NULL_RTX ; pool_vector [ pool_size ] . part_of_sequence_p = ( lab == 0 ) ; if ( lab && pool_window_label ) { newref = gen_rtx_LABEL_REF ( VOIDmode , pool_window_label ) ; ref = pool_vector [ pool_window_last ] . wend ; LABEL_NEXTREF ( newref ) = ref ; pool_vector [ pool_window_last ] . wend = newref ; } if ( lab ) pool_window_label = lab ; pool_window_last = pool_size ; pool_size ++ ; return lab ; } </s>

Add a constant to the pool and return its label .


<s>
void
Thumb1InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
Register
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
&
ARM
::
tGPRRegClass
||
(
Register
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
&
ARM
::
tGPRRegClass
||
(
Register
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
,
MachineMemOperand
::
MOStore
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlign
(
FI
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tSTRspi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .

ARM
ARM::tGPRRegClass
ARM
"Unknown regclass!"
ARM::tGPRRegClass
ARM
ARM::tSTRspi
0
ARMCC::AL


<s> std :: pair < unsigned , const TargetRegisterClass * > HexagonTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : switch ( VT . SimpleTy ) { default : return { 0u , nullptr } ; case MVT :: i1 : case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : case MVT :: f32 : return { 0u , & Hexagon :: IntRegsRegClass } ; case MVT :: i64 : case MVT :: f64 : return { 0u , & Hexagon :: DoubleRegsRegClass } ; } break ; case 'a' : if ( VT != MVT :: i32 ) return { 0u , nullptr } ; return { 0u , & Hexagon :: ModRegsRegClass } ; case 'q' : switch ( VT . getSizeInBits ( ) ) { default : return { 0u , nullptr } ; case 512 : case 1024 : return { 0u , & Hexagon :: HvxQRRegClass } ; } break ; case 'v' : switch ( VT . getSizeInBits ( ) ) { default : return { 0u , nullptr } ; case 512 : return { 0u , & Hexagon :: HvxVRRegClass } ; case 1024 : if ( Subtarget . hasV60TOps ( ) && Subtarget . useHVX128BOps ( ) ) return { 0u , & Hexagon :: HvxVRRegClass } ; return { 0u , & Hexagon :: HvxWRRegClass } ; case 2048 : return { 0u , & Hexagon :: HvxWRRegClass } ; } break ; default : return { 0u , nullptr } ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> static void arm_function_arg_advance ( cumulative_args_t pcum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * pcum = get_cumulative_args ( pcum_v ) ; if ( pcum -> pcs_variant <= ARM_PCS_AAPCS_LOCAL ) { aapcs_layout_arg ( pcum , mode , type , named ) ; if ( pcum -> aapcs_cprc_slot >= 0 ) { aapcs_cp_arg_layout [ pcum -> aapcs_cprc_slot ] . advance ( pcum , mode , type ) ; pcum -> aapcs_cprc_slot = - 1 ; } pcum -> aapcs_arg_processed = false ; pcum -> aapcs_ncrn = pcum -> aapcs_next_ncrn ; pcum -> aapcs_reg = NULL_RTX ; pcum -> aapcs_partial = 0 ; } else { pcum -> nargs += 1 ; if ( arm_vector_mode_supported_p ( mode ) && pcum -> named_count > pcum -> nargs && TARGET_IWMMXT_ABI ) pcum -> iwmmxt_nregs += 1 ; else pcum -> nregs += ARM_NUM_REGS2 ( mode , type ) ; } } </s>

Update the data in PCUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
k_Immediate
:
OS
<<
"Imm<"
;
Imm
.
Val
->
print
(
OS
)
;
OS
<<
">"
;
break
;
case
k_Memory
:
OS
<<
"Mem<"
;
Mem
.
Base
->
print
(
OS
)
;
OS
<<
", "
;
Mem
.
Off
->
print
(
OS
)
;
OS
<<
">"
;
break
;
case
k_PhysRegister
:
OS
<<
"PhysReg<"
<<
PhysReg
.
Num
<<
">"
;
break
;
case
k_RegisterIndex
:
OS
<<
"RegIdx<"
<<
RegIdx
.
Index
<<
":"
<<
RegIdx
.
Kind
<<
">"
;
break
;
case
k_Token
:
OS
<<
Tok
.
Data
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> bool Tile64TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , getTargetMachine ( ) , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_Tile64 ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> bool SIInsertSkips :: runOnMachineFunction ( MachineFunction & MF ) { const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; SkipThreshold = SkipThresholdFlag ; bool HaveKill = false ; bool MadeChange = false ; SmallVector < MachineBasicBlock * , 16 > ExecBranchStack ; MachineFunction :: iterator NextBB ; MachineBasicBlock * EmptyMBBAtEnd = nullptr ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; BI = NextBB ) { NextBB = std :: next ( BI ) ; MachineBasicBlock & MBB = * BI ; bool HaveSkipBlock = false ; if ( ! ExecBranchStack . empty ( ) && ExecBranchStack . back ( ) == & MBB ) { ExecBranchStack . pop_back ( ) ; } if ( HaveKill && ExecBranchStack . empty ( ) ) { HaveKill = false ; } MachineBasicBlock :: iterator I , Next ; for ( I = MBB . begin ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; switch ( MI . getOpcode ( ) ) { case AMDGPU :: SI_MASK_BRANCH : ExecBranchStack . push_back ( MI . getOperand ( 0 ) . getMBB ( ) ) ; MadeChange |= skipMaskBranch ( MI , MBB ) ; break ; case AMDGPU :: S_BRANCH : if ( MBB . isLayoutSuccessor ( MI . getOperand ( 0 ) . getMBB ( ) ) ) { MI . eraseFromParent ( ) ; } else if ( HaveSkipBlock ) { MI . eraseFromParent ( ) ; } break ; case AMDGPU :: SI_KILL_TERMINATOR : MadeChange = true ; kill ( MI ) ; if ( ExecBranchStack . empty ( ) ) { if ( skipIfDead ( MI , * NextBB ) ) { HaveSkipBlock = true ; NextBB = std :: next ( BI ) ; BE = MF . end ( ) ; } } else { HaveKill = true ; } MI . eraseFromParent ( ) ; break ; case AMDGPU :: SI_RETURN : assert ( ! MF . getInfo < SIMachineFunctionInfo > ( ) -> returnsVoid ( ) ) ; if ( BI != -- MF . end ( ) || I != MBB . getFirstTerminator ( ) ) { if ( ! EmptyMBBAtEnd ) { EmptyMBBAtEnd = MF . CreateMachineBasicBlock ( ) ; MF . insert ( MF . end ( ) , EmptyMBBAtEnd ) ; } MBB . addSuccessor ( EmptyMBBAtEnd ) ; BuildMI ( * BI , I , MI . getDebugLoc ( ) , TII -> get ( AMDGPU :: S_BRANCH ) ) . addMBB ( EmptyMBBAtEnd ) ; I -> eraseFromParent ( ) ; } break ; default : break ; } } } return MadeChange ; } </s>


<s> bool AMDGPUSymbolizer :: tryAddingSymbolicOperand ( MCInst & Inst , raw_ostream & , int64_t Value , uint64_t , bool IsBranch , uint64_t , uint64_t , uint64_t ) { if ( ! IsBranch ) { return false ; } auto * Symbols = static_cast < SectionSymbolsTy * > ( DisInfo ) ; if ( ! Symbols ) return false ; auto Result = llvm :: find_if ( * Symbols , [ Value ] ( const SymbolInfoTy & Val ) { return Val . Addr == static_cast < uint64_t > ( Value ) && Val . Type == ELF :: STT_NOTYPE ; } ) ; if ( Result != Symbols -> end ( ) ) { auto * Sym = Ctx . getOrCreateSymbol ( Result -> Name ) ; const auto * Add = MCSymbolRefExpr :: create ( Sym , Ctx ) ; Inst . addOperand ( MCOperand :: createExpr ( Add ) ) ; return true ; } ReferencedAddresses . push_back ( static_cast < uint64_t > ( Value ) ) ; return false ; } </s>

Try to add a symbolic operand instead of Value to the MCInst .


<s> TargetPassConfig * GBZ80TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new GBZ80PassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


"rs6000_secondary_memory_needed, return: %s, from_class = %s, "

Debug version of rs6000_secondary_memory_needed .


<s> void MipsAsmPrinter :: emitFunctionBodyStart ( ) { MipsTargetStreamer & TS = getTargetStreamer ( ) ; MCInstLowering . Initialize ( & MF -> getContext ( ) ) ; bool IsNakedFunction = MF -> getFunction ( ) . hasFnAttribute ( Attribute :: Naked ) ; if ( ! IsNakedFunction ) emitFrameDirective ( ) ; if ( ! IsNakedFunction ) printSavedRegsBitmask ( ) ; if ( ! Subtarget -> inMips16Mode ( ) ) { TS . emitDirectiveSetNoReorder ( ) ; TS . emitDirectiveSetNoMacro ( ) ; TS . emitDirectiveSetNoAt ( ) ; } } </s>

Targets can override this to emit stuff before the first basic block in the function .