<s> bool AArch64TargetMachine :: parseMachineFunctionInfo ( const yaml :: MachineFunctionInfo & MFI , PerFunctionMIParsingState & PFS , SMDiagnostic & Error , SMRange & SourceRange ) const { const auto & YamlMFI = static_cast < const yaml :: AArch64FunctionInfo & > ( MFI ) ; MachineFunction & MF = PFS . MF ; MF . getInfo < AArch64FunctionInfo > ( ) -> initializeBaseYamlFields ( YamlMFI ) ; return false ; } </s>

Parse out the target 's MachineFunctionInfo from the YAML reprsentation .


<s> bool PPCSubtarget :: isGVIndirectSymbol ( const GlobalValue * GV ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return true ; if ( TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return false ; return true ; } </s>

True if the GV will be accessed via an indirect symbol .


<s> static tree def_builtin ( const char * name , enum insn_code icode , enum sparc_builtins code , tree type ) { tree t = add_builtin_function ( name , type , code , BUILT_IN_MD , NULL , NULL_TREE ) ; if ( t ) { sparc_builtins [ code ] = t ; sparc_builtins_icode [ code ] = icode ; } return t ; } </s>

Add a SPARC builtin function with NAME , ICODE , CODE and TYPE . Return the function decl or NULL_TREE if the builtin was not added .


<s> bool ix86_expand_fp_vec_cmp ( rtx operands [ ] ) { enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; rtx cmp ; code = ix86_prepare_sse_fp_compare_args ( operands [ 0 ] , code , & operands [ 2 ] , & operands [ 3 ] ) ; if ( code == UNKNOWN ) { rtx temp ; switch ( GET_CODE ( operands [ 1 ] ) ) { case LTGT : temp = ix86_expand_sse_cmp ( operands [ 0 ] , ORDERED , operands [ 2 ] , operands [ 3 ] , NULL , NULL ) ; cmp = ix86_expand_sse_cmp ( operands [ 0 ] , NE , operands [ 2 ] , operands [ 3 ] , NULL , NULL ) ; code = AND ; break ; case UNEQ : temp = ix86_expand_sse_cmp ( operands [ 0 ] , UNORDERED , operands [ 2 ] , operands [ 3 ] , NULL , NULL ) ; cmp = ix86_expand_sse_cmp ( operands [ 0 ] , EQ , operands [ 2 ] , operands [ 3 ] , NULL , NULL ) ; code = IOR ; break ; default : gcc_unreachable ( ) ; } cmp = expand_simple_binop ( GET_MODE ( cmp ) , code , temp , cmp , cmp , 1 , OPTAB_DIRECT ) ; } else cmp = ix86_expand_sse_cmp ( operands [ 0 ] , code , operands [ 2 ] , operands [ 3 ] , NULL , NULL ) ; if ( operands [ 0 ] != cmp ) emit_move_insn ( operands [ 0 ] , cmp ) ; return true ; } </s>


<s> SystemZSubtarget & SystemZSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { StringRef CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "generic" ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( HasSoftFloat ) HasVector = false ; if ( ! HasVector ) { HasVectorEnhancements1 = false ; HasVectorEnhancements2 = false ; HasVectorPackedDecimal = false ; HasVectorPackedDecimalEnhancement = false ; } return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool AArch64RegisterInfo :: isConstantPhysReg ( unsigned PhysReg ) const { return PhysReg == AArch64 :: WZR || PhysReg == AArch64 :: XZR ; } </s>

Returns true if PhysReg is unallocatable and constant throughout the function .


<s> std :: string NVPTXAsmPrinter :: getSymbolName ( const GlobalValue * GV ) const { MCSymbol * Sym = getSymbol ( GV ) ; std :: string OriginalName ; raw_string_ostream OriginalNameStream ( OriginalName ) ; Sym -> print ( OriginalNameStream ) ; OriginalNameStream . flush ( ) ; std :: string CleanName ; raw_string_ostream CleanNameStream ( CleanName ) ; for ( unsigned I = 0 , E = OriginalName . size ( ) ; I != E ; ++ I ) { char C = OriginalName [ I ] ; if ( C == '.' ) { CleanNameStream << "_$_" ; } else if ( C == '@' ) { CleanNameStream << "_%_" ; } else { CleanNameStream << C ; } } return CleanNameStream . str ( ) ; } </s>

Get the name of the symbol at the specified index .


<s> unsigned MipsAsmParser :: checkEarlyTargetMatchPredicate ( MCInst & Inst , const OperandVector & Operands ) { switch ( Inst . getOpcode ( ) ) { default : return Match_Success ; case Mips :: DATI : case Mips :: DAHI : case Mips :: DATI_MM64R6 : case Mips :: DAHI_MM64R6 : if ( static_cast < MipsOperand & > ( * Operands [ 1 ] ) . isValidForTie ( static_cast < MipsOperand & > ( * Operands [ 2 ] ) ) ) return Match_Success ; return Match_RequiresSameSrcAndDst ; } } </s>

Validate the instruction match against any complex target predicates before rendering any operands to it .


<s> static rtx s390_emit_compare_and_swap ( enum rtx_code code , rtx old , rtx mem , rtx cmp , rtx new_rtx , machine_mode ccmode ) { rtx cc ; cc = gen_rtx_REG ( ccmode , CC_REGNUM ) ; switch ( GET_MODE ( mem ) ) { case E_SImode : emit_insn ( gen_atomic_compare_and_swapsi_internal ( old , mem , cmp , new_rtx , cc ) ) ; break ; case E_DImode : emit_insn ( gen_atomic_compare_and_swapdi_internal ( old , mem , cmp , new_rtx , cc ) ) ; break ; case E_TImode : emit_insn ( gen_atomic_compare_and_swapti_internal ( old , mem , cmp , new_rtx , cc ) ) ; break ; case E_QImode : case E_HImode : default : gcc_unreachable ( ) ; } return s390_emit_compare ( code , cc , const0_rtx ) ; } </s>

Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD matches CMP . Return the correct condition RTL to be placed in the IF_THEN_ELSE of the conditional branch testing the result .


<s> bool BPFInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . end ( ) ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugInstr ( ) ) continue ; if ( ! isUnpredicatedTerminator ( * I ) ) break ; if ( ! I -> isBranch ( ) ) return true ; if ( I -> getOpcode ( ) == BPF :: JMP ) { if ( ! AllowModify ) { TBB = I -> getOperand ( 0 ) . getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = nullptr ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( 0 ) . getMBB ( ) ) ) { TBB = nullptr ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( 0 ) . getMBB ( ) ; continue ; } return true ; } return false ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


"ARM PIC Global Base Reg Initialization"

getPassName - Return a nice clean name for a pass .


<s> static bool arm_sets_movw_movt_fusible_p ( rtx prev_set , rtx curr_set ) { rtx set_dest = SET_DEST ( curr_set ) ; if ( GET_MODE ( set_dest ) != SImode ) return false ; if ( GET_CODE ( set_dest ) == ZERO_EXTRACT ) { if ( CONST_INT_P ( SET_SRC ( curr_set ) ) && CONST_INT_P ( SET_SRC ( prev_set ) ) && REG_P ( XEXP ( set_dest , 0 ) ) && REG_P ( SET_DEST ( prev_set ) ) && REGNO ( XEXP ( set_dest , 0 ) ) == REGNO ( SET_DEST ( prev_set ) ) ) return true ; } else if ( GET_CODE ( SET_SRC ( curr_set ) ) == LO_SUM && REG_P ( SET_DEST ( curr_set ) ) && REG_P ( SET_DEST ( prev_set ) ) && GET_CODE ( SET_SRC ( prev_set ) ) == HIGH && REGNO ( SET_DEST ( curr_set ) ) == REGNO ( SET_DEST ( prev_set ) ) ) return true ; return false ; } </s>

Return true if the two back-to-back sets PREV_SET , CURR_SET are suitable for MOVW / MOVT macro fusion .


<s> unsigned SIInstrInfo :: getAddressSpaceForPseudoSourceKind ( unsigned Kind ) const { switch ( Kind ) { case PseudoSourceValue :: Stack : case PseudoSourceValue :: FixedStack : return AMDGPUAS :: PRIVATE_ADDRESS ; case PseudoSourceValue :: ConstantPool : case PseudoSourceValue :: GOT : case PseudoSourceValue :: JumpTable : case PseudoSourceValue :: GlobalValueCallEntry : case PseudoSourceValue :: ExternalSymbolCallEntry : case PseudoSourceValue :: TargetCustom : return AMDGPUAS :: CONSTANT_ADDRESS ; case PseudoSourceValue :: CapTable : return AMDGPUAS :: CONSTANT_ADDRESS ; } return AMDGPUAS :: FLAT_ADDRESS ; } </s>

getAddressSpaceForPseudoSourceKind - Given the kind of memory ( e.g .


<s> static bool is_fmul_fmac_insn ( rtx_insn * insn , bool fmul_ok ) { enum attr_type t ; if ( ! NONDEBUG_INSN_P ( insn ) ) return false ; if ( recog_memoized ( insn ) < 0 ) return false ; t = get_attr_type ( insn ) ; return is_fmac_op ( t ) || ( fmul_ok && is_fmul_op ( t ) ) ; } </s>

Return whether INSN is an FMUL ( if FMUL_OK is true ) or FMADD/FMSUB instruction .


<s> void fma_node :: add_child ( fma_node * child ) { this -> m_children -> push_back ( child ) ; } </s>

Add a child to this node in the list of children .


"the ABI of passing C structures with zero-width bit-fields"

Classify the argument of type TYPE and mode MODE . CLASSES will be filled by the register class used to pass each word of the operand . The number of words is returned . In case the parameter should be passed in memory , 0 is returned . As a special case for zero sized containers , classes [ 0 ] will be NO_CLASS and 1 is returned . BIT_OFFSET is used internally for handling records and specifies offset of the offset in bits modulo 256 to avoid overflow cases . See the x86-64 PS ABI for details .


<s>
Register
TPCTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
LLT
VT
,
const
MachineFunction
&
MF
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"sp0"
,
TPC
::
SP0
)
.
Case
(
"vp0"
,
TPC
::
VP0
)
.
Case
(
"lfsr"
,
TPC
::
LFSR
)
.
Case
(
"lfsr_no_change"
,
TPC
::
LFSR_NO_CHANGE
)
.
Case
(
"s_lfsr"
,
TPC
::
S_LFSR
)
.
Case
(
"s_lfsr_no_change"
,
TPC
::
S_LFSR_NO_CHANGE
)
.
Case
(
"v_lane_id_32"
,
TPC
::
V_LANE_ID_32
)
.
Case
(
"v_lane_id_16"
,
TPC
::
V_LANE_ID_16
)
.
Case
(
"v_lane_id_8"
,
TPC
::
V_LANE_ID_8
)
.
Case
(
"i2"
,
TPC
::
I2
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


"AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "


<s> void AArch64CallLowering :: splitToValueTypes ( const ArgInfo & OrigArg , SmallVectorImpl < ArgInfo > & SplitArgs , const DataLayout & DL , MachineRegisterInfo & MRI , SplitArgTy PerformArgSplit ) const { const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; LLVMContext & Ctx = OrigArg . Ty -> getContext ( ) ; SmallVector < EVT , 4 > SplitVTs ; SmallVector < uint64_t , 4 > Offsets ; ComputeValueVTs ( TLI , DL , OrigArg . Ty , SplitVTs , & Offsets , 0 ) ; if ( SplitVTs . size ( ) == 1 ) { SplitArgs . emplace_back ( OrigArg . Reg , SplitVTs [ 0 ] . getTypeForEVT ( Ctx ) , OrigArg . Flags ) ; return ; } unsigned FirstRegIdx = SplitArgs . size ( ) ; for ( auto SplitVT : SplitVTs ) { Type * SplitTy = SplitVT . getTypeForEVT ( Ctx ) ; SplitArgs . push_back ( ArgInfo { MRI . createGenericVirtualRegister ( LLT { * SplitTy , DL } ) , SplitTy , OrigArg . Flags } ) ; } SmallVector < uint64_t , 4 > BitOffsets ; for ( auto Offset : Offsets ) BitOffsets . push_back ( Offset * 8 ) ; SmallVector < unsigned , 8 > SplitRegs ; for ( auto I = & SplitArgs [ FirstRegIdx ] ; I != SplitArgs . end ( ) ; ++ I ) SplitRegs . push_back ( I -> Reg ) ; PerformArgSplit ( SplitRegs , BitOffsets ) ; } </s>

Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> void NVPTXTargetStreamer :: outputDwarfFileDirectives ( ) { for ( const std :: string & S : DwarfFiles ) getStreamer ( ) . EmitRawText ( S . data ( ) ) ; DwarfFiles . clear ( ) ; } </s>

Outputs the list of the DWARF '.file ' directives to the streamer .


<s> bool PPCFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( ! Subtarget . isSVR4ABI ( ) ) return false ; MachineFunction * MF = MBB . getParent ( ) ; const PPCInstrInfo & TII = * static_cast < const PPCInstrInfo * > ( MF -> getSubtarget ( ) . getInstrInfo ( ) ) ; DebugLoc DL ; bool CRSpilled = false ; MachineInstrBuilder CRMIB ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg == PPC :: VRSAVE && ! Subtarget . isDarwinABI ( ) ) continue ; bool IsCRField = PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ; MBB . addLiveIn ( Reg ) ; if ( CRSpilled && IsCRField ) { CRMIB . addReg ( Reg , RegState :: ImplicitKill ) ; continue ; } if ( IsCRField ) { PPCFunctionInfo * FuncInfo = MF -> getInfo < PPCFunctionInfo > ( ) ; if ( Subtarget . isPPC64 ( ) ) { FuncInfo -> addMustSaveCR ( Reg ) ; } else { CRSpilled = true ; FuncInfo -> setSpillsCR ( ) ; CRMIB = BuildMI ( * MF , DL , TII . get ( PPC :: MFCR ) , PPC :: R12 ) . addReg ( Reg , RegState :: ImplicitKill ) ; MBB . insert ( MI , CRMIB ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( PPC :: STW ) ) . addReg ( PPC :: R12 , getKillRegState ( true ) ) , CSI [ i ] . getFrameIdx ( ) ) ) ; } } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .

PowerPC PPC PPC PPC 0 PPC::VRSAVE PPC::CR2 PPC::CR4 PPC PPC PPC PPC::MFCR PPC::R12 PPC::STW PPC::R12


<s> static bool ix86_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t regclass ) { if ( from == to ) return true ; if ( MAYBE_FLOAT_CLASS_P ( regclass ) ) return false ; if ( MAYBE_SSE_CLASS_P ( regclass ) || MAYBE_MMX_CLASS_P ( regclass ) ) { int mov_size = MAYBE_SSE_CLASS_P ( regclass ) && TARGET_SSE2 ? 2 : 4 ; if ( GET_MODE_SIZE ( from ) < mov_size || GET_MODE_SIZE ( to ) < mov_size ) return false ; } return true ; } </s>


<s> MVT getPointerTy ( const DataLayout & DL , uint32_t AS = 0 ) const override { if ( AS == WasmAddressSpace :: EXTERNREF ) return MVT :: externref ; if ( AS == WasmAddressSpace :: FUNCREF ) return MVT :: funcref ; return TargetLowering :: getPointerTy ( DL , AS ) ; } </s>

Return the pointer type for the given address space , defaults to the pointer type from the data layout .

WebAssembly 0 WasmAddressSpace::EXTERNREF MVT::externref WasmAddressSpace::FUNCREF MVT::funcref


<s> MVT ARM64TargetLowering :: getScalarShiftAmountTy ( EVT LHSTy ) const { return MVT :: i64 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> bool ARMTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , const Type * Ty ) const { MVT VT = getValueType ( Ty , true ) ; if ( ! isLegalAddressImmediate ( AM . BaseOffs , VT , Subtarget ) ) return false ; if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( Subtarget -> isThumb ( ) ) return false ; default : if ( AM . BaseOffs ) return false ; if ( ! VT . isSimple ( ) ) return false ; int Scale = AM . Scale ; switch ( VT . getSimpleVT ( ) ) { default : return false ; case MVT :: i1 : case MVT :: i8 : case MVT :: i32 : case MVT :: i64 : if ( Scale < 0 ) Scale = - Scale ; if ( Scale == 1 ) return true ; return isPowerOf2_32 ( Scale & ~ 1 ) ; case MVT :: i16 : if ( ( ( unsigned ) AM . HasBaseReg + Scale ) <= 2 ) return true ; return false ; case MVT :: isVoid : if ( AM . Scale & 1 ) return false ; return isPowerOf2_32 ( AM . Scale ) ; } break ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> bool PPCRegisterInfo :: requiresFrameIndexScavenging ( const MachineFunction & MF ) const { const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const PPCInstrInfo * InstrInfo = Subtarget . getInstrInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const std :: vector < CalleeSavedInfo > & Info = MFI . getCalleeSavedInfo ( ) ; if ( ! MFI . isCalleeSavedInfoValid ( ) ) return true ; unsigned FrameSize = MFI . getStackSize ( ) ; if ( FrameSize & ~ 0x7FFF ) return true ; for ( unsigned i = 0 ; i < Info . size ( ) ; i ++ ) { int FrIdx = Info [ i ] . getFrameIdx ( ) ; unsigned Reg = Info [ i ] . getReg ( ) ; unsigned Opcode = InstrInfo -> getStoreOpcodeForSpill ( Reg ) ; if ( ! MFI . isFixedObjectIndex ( FrIdx ) ) { if ( offsetMinAlignForOpcode ( Opcode ) > 1 ) return true ; } if ( InstrInfo -> isXFormMemOp ( Opcode ) ) return true ; } return false ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> unsigned TOYInstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { assert ( 0 && "Unimplemented" ) ; return 0 ; } </s>

Remove the branching code at the end of the specific MBB .


<s>
std
::
string
AMDGPUIntrinsicInfo
::
getName
(
unsigned
IntrID
,
Type
*
*
Tys
,
unsigned
numTys
)
const
{
if
(
IntrID
<
Intrinsic
::
num_intrinsics
)
{
return
nullptr
;
}
assert
(
IntrID
<
AMDGPUIntrinsic
::
num_AMDGPU_intrinsics
&&
"Invalid intrinsic ID"
)
;
std
::
string
Result
(
IntrinsicNameTable
[
IntrID
Intrinsic
::
num_intrinsics
]
)
;
return
Result
;
}
</s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s>
void
X86AvoidSFBPass
::
buildCopy
(
MachineInstr
*
LoadInst
,
unsigned
NLoadOpcode
,
int64_t
LoadDisp
,
MachineInstr
*
StoreInst
,
unsigned
NStoreOpcode
,
int64_t
StoreDisp
,
unsigned
Size
,
int64_t
LMMOffset
,
int64_t
SMMOffset
)
{
MachineOperand
&
LoadBase
=
getBaseOperand
(
LoadInst
)
;
MachineOperand
&
StoreBase
=
getBaseOperand
(
StoreInst
)
;
MachineBasicBlock
*
MBB
=
LoadInst
->
getParent
(
)
;
MachineMemOperand
*
LMMO
=
*
LoadInst
->
memoperands_begin
(
)
;
MachineMemOperand
*
SMMO
=
*
StoreInst
->
memoperands_begin
(
)
;
unsigned
Reg1
=
MRI
->
createVirtualRegister
(
TII
->
getRegClass
(
TII
->
get
(
NLoadOpcode
)
,
0
,
TRI
,
*
(
MBB
->
getParent
(
)
)
)
)
;
MachineInstr
*
NewLoad
=
BuildMI
(
*
MBB
,
LoadInst
,
LoadInst
->
getDebugLoc
(
)
,
TII
->
get
(
NLoadOpcode
)
,
Reg1
)
.
add
(
LoadBase
)
.
addImm
(
1
)
.
addReg
(
X86
::
NoRegister
)
.
addImm
(
LoadDisp
)
.
addReg
(
X86
::
NoRegister
)
.
addMemOperand
(
MBB
->
getParent
(
)
->
getMachineMemOperand
(
LMMO
,
LMMOffset
,
Size
)
)
;
if
(
LoadBase
.
isReg
(
)
)
getBaseOperand
(
NewLoad
)
.
setIsKill
(
false
)
;
LLVM_DEBUG
(
NewLoad
->
dump
(
)
)
;
MachineInstr
*
StInst
=
StoreInst
;
auto
PrevInstrIt
=
skipDebugInstructionsBackward
(
std
::
prev
(
MachineBasicBlock
::
instr_iterator
(
StoreInst
)
)
,
MBB
->
instr_begin
(
)
)
;
if
(
PrevInstrIt
.
getNodePtr
(
)
==
LoadInst
)
StInst
=
LoadInst
;
MachineInstr
*
NewStore
=
BuildMI
(
*
MBB
,
StInst
,
StInst
->
getDebugLoc
(
)
,
TII
->
get
(
NStoreOpcode
)
)
.
add
(
StoreBase
)
.
addImm
(
1
)
.
addReg
(
X86
::
NoRegister
)
.
addImm
(
StoreDisp
)
.
addReg
(
X86
::
NoRegister
)
.
addReg
(
Reg1
)
.
addMemOperand
(
MBB
->
getParent
(
)
->
getMachineMemOperand
(
SMMO
,
SMMOffset
,
Size
)
)
;
if
(
StoreBase
.
isReg
(
)
)
getBaseOperand
(
NewStore
)
.
setIsKill
(
false
)
;
MachineOperand
&
StoreSrcVReg
=
StoreInst
->
getOperand
(
X86
::
AddrNumOperands
)
;
assert
(
StoreSrcVReg
.
isReg
(
)
&&
"Expected virtual register"
)
;
NewStore
->
getOperand
(
X86
::
AddrNumOperands
)
.
setIsKill
(
StoreSrcVReg
.
isKill
(
)
)
;
LLVM_DEBUG
(
NewStore
->
dump
(
)
)
;
}
</s>


"density %d%%, cost %d exceeds threshold, penalizing "

Test for likely overcommitment of vector hardware resources . If a loop iteration is relatively large , and too large a percentage of instructions in the loop are vectorized , the cost model may not adequately reflect delays from unavailable vector resources . Penalize the loop body cost for this case .


<s> SDNode * VideocoreDAGToDAGISel :: Select ( SDNode * N ) { if ( N -> isMachineOpcode ( ) ) return NULL ; switch ( N -> getOpcode ( ) ) { default : break ; } return SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> const MCPhysReg * CSKYRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const CSKYSubtarget & STI = MF -> getSubtarget < CSKYSubtarget > ( ) ; if ( MF -> getFunction ( ) . hasFnAttribute ( "interrupt" ) ) { return CSR_GPR_ISR_SaveList ; } return CSR_I32_SaveList ; } </s>


<s> int sh_cfun_attr_renesas_p ( void ) { return sh_attr_renesas_p ( current_function_decl ) ; } </s>

True if __attribute__ ( ( renesas ) ) or -mrenesas , for the current function .


<s> bool ARMLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { const TargetMachine & TM = Fn . getTarget ( ) ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; TII = TM . getInstrInfo ( ) ; TRI = TM . getRegisterInfo ( ) ; RS = new RegScavenger ( ) ; isThumb2 = AFI -> isThumb2Function ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= LoadStoreMultipleOpti ( MBB ) ; if ( TM . getSubtarget < ARMSubtarget > ( ) . hasV5TOps ( ) ) Modified |= MergeReturnIntoLDM ( MBB ) ; } delete RS ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool ARMBaseRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


Return the bytes needed to compute the frame pointer from the current stack pointer .


<s> GCNRegPressure getRegPressure ( const MachineRegisterInfo & MRI , Range && LiveRegs ) { GCNRegPressure Res ; for ( const auto & RM : LiveRegs ) Res . inc ( RM . first , LaneBitmask :: getNone ( ) , RM . second , MRI ) ; return Res ; } </s>

Get register pressure for the entire scheduling region before scheduling .


<s>
SUnit
*
R600SchedStrategy
::
pickNode
(
bool
&
IsTopNode
)
{
SUnit
*
SU
=
nullptr
;
NextInstKind
=
IDOther
;
IsTopNode
=
false
;
bool
AllowSwitchToAlu
=
(
CurEmitted
>=
InstKindLimit
[
CurInstKind
]
)
||
(
Available
[
CurInstKind
]
.
empty
(
)
)
;
bool
AllowSwitchFromAlu
=
(
CurEmitted
>=
InstKindLimit
[
CurInstKind
]
)
&&
(
!
Available
[
IDFetch
]
.
empty
(
)
||
!
Available
[
IDOther
]
.
empty
(
)
)
;
if
(
CurInstKind
==
IDAlu
&&
!
Available
[
IDFetch
]
.
empty
(
)
)
{
float
ALUFetchRationEstimate
=
(
AluInstCount
+
AvailablesAluCount
(
)
+
Pending
[
IDAlu
]
.
size
(
)
)
/
(
FetchInstCount
+
Available
[
IDFetch
]
.
size
(
)
)
;
if
(
ALUFetchRationEstimate
==
0
)
{
AllowSwitchFromAlu
=
true
;
}
else
{
unsigned
NeededWF
=
62.5f
/
ALUFetchRationEstimate
;
LLVM_DEBUG
(
dbgs
(
)
<<
NeededWF
<<
" approx. Wavefronts Required\n"
)
;
unsigned
NearRegisterRequirement
=
2
*
Available
[
IDFetch
]
.
size
(
)
;
if
(
NeededWF
>
getWFCountLimitedByGPR
(
NearRegisterRequirement
)
)
AllowSwitchFromAlu
=
true
;
}
}
if
(
!
SU
&&
(
(
AllowSwitchToAlu
&&
CurInstKind
!=
IDAlu
)
||
(
!
AllowSwitchFromAlu
&&
CurInstKind
==
IDAlu
)
)
)
{
SU
=
pickAlu
(
)
;
if
(
!
SU
&&
!
PhysicalRegCopy
.
empty
(
)
)
{
SU
=
PhysicalRegCopy
.
front
(
)
;
PhysicalRegCopy
.
erase
(
PhysicalRegCopy
.
begin
(
)
)
;
}
if
(
SU
)
{
if
(
CurEmitted
>=
InstKindLimit
[
IDAlu
]
)
CurEmitted
=
0
;
NextInstKind
=
IDAlu
;
}
}
if
(
!
SU
)
{
SU
=
pickOther
(
IDFetch
)
;
if
(
SU
)
NextInstKind
=
IDFetch
;
}
if
(
!
SU
)
{
SU
=
pickOther
(
IDOther
)
;
if
(
SU
)
NextInstKind
=
IDOther
;
}
LLVM_DEBUG
(
if
(
SU
)
{
dbgs
(
)
<<
" ** Pick node **\n"
;
SU
->
dump
(
DAG
)
;
}
else
{
dbgs
(
)
<<
"NO NODE \n"
;
for
(
unsigned
i
=
0
;
i
<
DAG
->
SUnits
.
size
(
)
;
i
++
)
{
const
SUnit
&
S
=
DAG
->
SUnits
[
i
]
;
if
(
!
S
.
isScheduled
)
S
.
dump
(
DAG
)
;
}
}
</s>

Pick the next node to schedule , or return NULL .


<s> const BPFRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


"Branch target immediate cannot be 0 bits!"

Set if this operand is a branch target .


<s> static bool mn10300_legitimate_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { switch ( GET_CODE ( x ) ) { case CONST : x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == PLUS ) { if ( ! CONST_INT_P ( XEXP ( x , 1 ) ) ) return false ; x = XEXP ( x , 0 ) ; } if ( GET_CODE ( x ) == UNSPEC ) { switch ( XINT ( x , 1 ) ) { case UNSPEC_PIC : case UNSPEC_GOT : case UNSPEC_GOTOFF : case UNSPEC_PLT : return true ; default : return false ; } } if ( ! mn10300_symbolic_operand ( x , Pmode ) ) return false ; break ; default : break ; } return true ; } </s>

Implement TARGET_LEGITIMATE_CONSTANT_P . Returns TRUE if X is a valid constant . Note that some `` constants '' are n't valid , such as TLS symbols and unconverted GOT-based references , so we eliminate those here .


<s> static void nds32_setup_incoming_varargs ( cumulative_args_t ca , const function_arg_info & arg , int * pretend_args_size , int second_time ATTRIBUTE_UNUSED ) { unsigned int total_args_regs ; unsigned int num_of_used_regs ; unsigned int remaining_reg_count ; CUMULATIVE_ARGS * cum ; if ( TARGET_HARD_FLOAT ) return ; cum = get_cumulative_args ( ca ) ; total_args_regs = NDS32_MAX_GPR_REGS_FOR_ARGS + NDS32_GPR_ARG_FIRST_REGNUM ; num_of_used_regs = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG ( cum -> gpr_offset , arg . mode , arg . type ) + NDS32_NEED_N_REGS_FOR_ARG ( arg . mode , arg . type ) ; remaining_reg_count = total_args_regs - num_of_used_regs ; * pretend_args_size = remaining_reg_count * UNITS_PER_WORD ; return ; } </s>


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> void R600InstrInfo :: reserveIndirectRegisters ( BitVector & Reserved , const MachineFunction & MF , const R600RegisterInfo & TRI ) const { const R600Subtarget & ST = MF . getSubtarget < R600Subtarget > ( ) ; const R600FrameLowering * TFL = ST . getFrameLowering ( ) ; unsigned StackWidth = TFL -> getStackWidth ( MF ) ; int End = getIndirectIndexEnd ( MF ) ; if ( End == - 1 ) return ; for ( int Index = getIndirectIndexBegin ( MF ) ; Index <= End ; ++ Index ) { for ( unsigned Chan = 0 ; Chan < StackWidth ; ++ Chan ) { unsigned Reg = AMDGPU :: R600_TReg32RegClass . getRegister ( ( 4 * Index ) + Chan ) ; TRI . reserveRegisterTuples ( Reserved , Reg ) ; } } } </s>

Reserve the registers that may be accessed using indirect addressing .


<s> bool ARMCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; auto DL = MF . getDataLayout ( ) ; auto & TLI = * getTLI < ARMTargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb ( ) ) return false ; for ( auto & Arg : F . args ( ) ) if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , 8 > ArgInfos ; SmallVector < unsigned , 4 > SplitRegs ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; SplitRegs . clear ( ) ; splitToValueTypes ( AInfo , ArgInfos , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { SplitRegs . push_back ( Reg ) ; } ) ; if ( ! SplitRegs . empty ( ) ) MIRBuilder . buildMerge ( VRegs [ Idx ] , SplitRegs ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; return handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> unsigned int execute ( function * ) final override { return remove_partial_avx_dependency ( ) ; } </s>


<s> const TriCoreSubtarget * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> void X86InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Alignment = std :: max < uint32_t > ( TRI -> getSpillSize ( * RC ) , 16 ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , Subtarget ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) , DestReg ) , FrameIdx ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s>
void
handle_pragma_vector
(
)
{
if
(
function_table
)
{
error
(
"duplicate definition of %qs"
,
"riscv_vector.h"
)
;
return
;
}
rvv_switcher
rvv
;
for
(
unsigned
int
type_i
=
0
;
type_i
<
NUM_VECTOR_TYPES
;
++
type_i
)
register_vector_type
(
(
enum
vector_type_index
)
type_i
)
;
function_table
=
new
hash_table
<
registered_function_hasher
>
(
1023
)
;
function_builder
builder
;
for
(
unsigned
int
i
=
0
;
i
<
ARRAY_SIZE
(
function_groups
)
;
++
i
)
builder
.
register_function_group
(
function_groups
[
i
]
)
;
}
</s>

Implement # pragma riscv intrinsic vector .


<s> int cris_delay_slots_for_epilogue ( ) { if ( regs_ever_live [ CRIS_SRP_REGNUM ] || cfun -> machine -> needs_return_address_on_stack != 0 ) return 0 ; cris_target_asm_function_epilogue ( NULL , get_frame_size ( ) ) ; if ( * save_last ) return 1 ; return 0 ; } </s>

Return the number of delay-slots in the epilogue : return 1 if it contains `` ret '' , else 0 .


<s> void KudeyarAsmPrinter :: emitFrameDirective ( ) { const TargetRegisterInfo & RI = * TM . getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) -> getStackSize ( ) ; if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( "\t.frame\t$" + StringRef ( KudeyarInstPrinter :: getRegisterName ( stackReg ) ) . lower ( ) + "," + Twine ( stackSize ) ) ; } </s>

Kudeyar Kudeyar "\t.frame\t$" Kudeyar ","


<s> void nios2_adjust_call_address ( rtx * call_op , rtx reg ) { if ( MEM_P ( * call_op ) ) call_op = & XEXP ( * call_op , 0 ) ; rtx addr = * call_op ; if ( flag_pic && CONSTANT_P ( addr ) ) { rtx tmp = reg ? reg : NULL_RTX ; if ( ! reg ) reg = gen_reg_rtx ( Pmode ) ; addr = nios2_load_pic_address ( addr , UNSPEC_PIC_CALL_SYM , tmp ) ; emit_insn ( gen_rtx_SET ( VOIDmode , reg , addr ) ) ; * call_op = reg ; } } </s>

The function with address * ADDR is being called . If the address needs to be loaded from the GOT , emit the instruction to do so and update * ADDR to point to the rtx for the loaded value . If REG ! = NULL_RTX , it is used as the target/scratch register in the GOT address calculation .


<s> Value * RISCVTargetLowering :: emitMaskedAtomicRMWIntrinsic ( IRBuilder < > & Builder , AtomicRMWInst * AI , Value * AlignedAddr , Value * Incr , Value * Mask , Value * ShiftAmt , AtomicOrdering Ord ) const { Value * Ordering = Builder . getInt32 ( static_cast < uint32_t > ( AI -> getOrdering ( ) ) ) ; Type * Tys [ ] = { AlignedAddr -> getType ( ) } ; Function * LrwOpScwLoop = Intrinsic :: getDeclaration ( AI -> getModule ( ) , getIntrinsicForMaskedAtomicRMWBinOp32 ( AI -> getOperation ( ) ) , Tys ) ; if ( AI -> getOperation ( ) == AtomicRMWInst :: Min || AI -> getOperation ( ) == AtomicRMWInst :: Max ) { const DataLayout & DL = AI -> getModule ( ) -> getDataLayout ( ) ; unsigned ValWidth = DL . getTypeStoreSizeInBits ( AI -> getValOperand ( ) -> getType ( ) ) ; Value * SextShamt = Builder . CreateSub ( Builder . getInt32 ( Subtarget . getXLen ( ) - ValWidth ) , ShiftAmt ) ; return Builder . CreateCall ( LrwOpScwLoop , { AlignedAddr , Incr , Mask , SextShamt , Ordering } ) ; } return Builder . CreateCall ( LrwOpScwLoop , { AlignedAddr , Incr , Mask , Ordering } ) ; } </s>

Perform a masked atomicrmw using a target-specific intrinsic .


<s> TargetLoweringBase :: LegalizeTypeAction getPreferredVectorAction ( EVT VT ) const override { if ( VT . getVectorElementType ( ) . getSizeInBits ( ) % 8 == 0 ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


Given the pattern ( X & ( C l > > / < < Y ) ) ==/ ! = 0 return true if it should be transformed into : ( ( X < < /l > > Y ) & C ) ==/ ! = 0 WARNING : if ' X ' is a constant , the fold may deadlock ! FIXME : we could avoid passing XC , but we ca n't use isConstOrConstSplat ( ) here because it can end up being not linked in .


<s> void convert_float128_to_int ( rtx * operands , enum rtx_code code ) { rtx dest = operands [ 0 ] ; rtx src = operands [ 1 ] ; rtx tmp = operands [ 2 ] ; rtx cvt ; rtvec cvt_vec ; rtx cvt_unspec ; rtvec move_vec ; rtx move_unspec ; if ( GET_CODE ( tmp ) == SCRATCH ) tmp = gen_reg_rtx ( V2DImode ) ; if ( MEM_P ( dest ) ) dest = rs6000_address_for_fpconvert ( dest ) ; cvt = gen_rtx_fmt_e ( code , GET_MODE ( dest ) , src ) ; cvt_vec = gen_rtvec ( 1 , cvt ) ; cvt_unspec = gen_rtx_UNSPEC ( V2DImode , cvt_vec , UNSPEC_IEEE128_CONVERT ) ; emit_insn ( gen_rtx_SET ( tmp , cvt_unspec ) ) ; move_vec = gen_rtvec ( 1 , tmp ) ; move_unspec = gen_rtx_UNSPEC ( GET_MODE ( dest ) , move_vec , UNSPEC_IEEE128_MOVE ) ; emit_insn ( gen_rtx_SET ( dest , move_unspec ) ) ; } </s>

Split a conversion from __float128 to an integer type into separate insns . OPERANDS points to the destination , source , and V2DI temporary register . CODE is either FIX or UNSIGNED_FIX .


<s> static bool arm_valid_target_attribute_p ( tree fndecl , tree ARG_UNUSED ( name ) , tree args , int ARG_UNUSED ( flags ) ) { bool ret = true ; struct gcc_options func_options , func_options_set ; tree cur_tree , new_optimize ; gcc_assert ( ( fndecl != NULL_TREE ) && ( args != NULL_TREE ) ) ; tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( ! func_optimize ) func_optimize = optimization_default_node ; memset ( & func_options , 0 , sizeof ( func_options ) ) ; init_options_struct ( & func_options , NULL ) ; lang_hooks . init_options_struct ( & func_options ) ; memset ( & func_options_set , 0 , sizeof ( func_options_set ) ) ; cl_optimization_restore ( & func_options , & func_options_set , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_restore ( & func_options , & func_options_set , TREE_TARGET_OPTION ( target_option_default_node ) ) ; cur_tree = arm_valid_target_attribute_tree ( args , & func_options , & func_options_set ) ; if ( cur_tree == NULL_TREE ) ret = false ; new_optimize = build_optimization_node ( & func_options , & func_options_set ) ; DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = cur_tree ; DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) = new_optimize ; return ret ; } </s>

Hook to validate attribute ( ( target ( `` string '' ) ) ) .


"switch %<-mcustom-%s%> value %d must be between 0 and 255"

Check individual FPU insn options , and register custom code .


<s> static void rs6000_elf_select_rtx_section ( enum machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ) { if ( ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( x , mode ) ) toc_section ( ) ; else default_elf_select_rtx_section ( mode , x , align ) ; } </s>

A C statement or statements to switch to the appropriate section for output of RTX in mode MODE . You can assume that RTX is some kind of constant in RTL . The argument MODE is redundant except in the case of a ` const_int ' rtx . Select the section by calling ` text_section ' or one of the alternatives for other sections . Do not define this macro if you put all constants in the read-only data section .


<s> const MCExpr * WebAssemblyAsmPrinter :: lowerConstant ( const Constant * CV ) { if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( CV ) ) if ( GV -> getValueType ( ) -> isFunctionTy ( ) ) { MCSymbol * Sym = getSymbol ( GV ) ; if ( ! isa < MCSymbolELF > ( Sym ) ) cast < MCSymbolWasm > ( Sym ) -> setIsFunction ( true ) ; return MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_WebAssembly_FUNCTION , OutContext ) ; } return AsmPrinter :: lowerConstant ( CV ) ; } </s>

Lower the specified LLVM Constant to an MCExpr .


<s> SDNode * SparcDAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static void mmix_reorg ( void ) { int regno ; for ( regno = MMIX_LAST_STACK_REGISTER_REGNUM ; regno >= 0 ; regno -- ) if ( ( df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) ) || ( regno == MMIX_FRAME_POINTER_REGNUM && frame_pointer_needed ) ) break ; if ( ! TARGET_ABI_GNU && regno < crtl -> args . info . regs - 1 ) { regno = crtl -> args . info . regs - 1 ; if ( regno > MMIX_RETURN_VALUE_REGNUM - 1 ) regno = MMIX_RETURN_VALUE_REGNUM - 1 ; } cfun -> machine -> highest_saved_stack_register = regno ; } </s>

Implement TARGET_MACHINE_DEPENDENT_REORG . No actual rearrangements done here ; just virtually by calculating the highest saved stack register number used to modify the register numbers at output time .


<s> bool HSAILInstrInfo :: shouldScheduleLoadsNear ( SDNode * Node1 , SDNode * Node2 , int64_t Offset1 , int64_t Offset2 , unsigned NumLoads ) const { if ( ! Node1 -> isMachineOpcode ( ) ) return false ; MachineSDNode * mnode1 = cast < MachineSDNode > ( Node1 ) ; if ( Offset2 - Offset1 <= 4 * ( int64_t ) ( * mnode1 -> memoperands_begin ( ) ) -> getSize ( ) ) return true ; return false ; } </s>

shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine ( in conjunction with areLoadsFromSameBasePtr ) if two loads should be scheduled togther .


<s> void SystemZFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; bool BackChain = MF . getFunction ( ) . hasFnAttribute ( "backchain" ) ; if ( ! usePackedStack ( MF ) || BackChain ) getOrCreateFramePointerSaveIndex ( MF ) ; uint64_t StackSize = ( MFFrame . estimateStackSize ( MF ) + SystemZMC :: CallFrameSize ) ; int64_t MaxArgOffset = 0 ; for ( int I = MFFrame . getObjectIndexBegin ( ) ; I != 0 ; ++ I ) if ( MFFrame . getObjectOffset ( I ) >= 0 ) { int64_t ArgOffset = MFFrame . getObjectOffset ( I ) + MFFrame . getObjectSize ( I ) ; MaxArgOffset = std :: max ( MaxArgOffset , ArgOffset ) ; } uint64_t MaxReach = StackSize + MaxArgOffset ; if ( ! isUInt < 12 > ( MaxReach ) ) { RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( 8 , 8 , false ) ) ; RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( 8 , 8 , false ) ) ; } } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> bool isReg ( ) const override { return is ( k_Register ) ; } </s>


<s> void MipsPassConfig :: addPreEmitPass ( ) { addPass ( createMipsExpandPseudoPass ( ) ) ; addPass ( createMicroMipsSizeReducePass ( ) ) ; addPass ( createMipsDelaySlotFillerPass ( ) ) ; addPass ( createMipsBranchExpansion ( ) ) ; addPass ( createMipsConstantIslandPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> enum reg_class coproc_secondary_reload_class ( machine_mode mode , rtx x , bool wb ) { if ( mode == HFmode ) { if ( ! TARGET_NEON_FP16 && ! TARGET_VFP_FP16INST ) return GENERAL_REGS ; if ( s_register_operand ( x , mode ) || neon_vector_mem_operand ( x , 2 , true ) ) return NO_REGS ; return GENERAL_REGS ; } if ( TARGET_NEON && ( MEM_P ( x ) || GET_CODE ( x ) == CONST_VECTOR ) && ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT || VALID_NEON_STRUCT_MODE ( mode ) ) ) return NO_REGS ; if ( arm_coproc_mem_operand ( x , wb ) || s_register_operand ( x , mode ) ) return NO_REGS ; return GENERAL_REGS ; } </s>

Return GENERAL_REGS if a scratch register required to reload x to/from coprocessor registers . Otherwise return NO_REGS .


<s> static bool or1k_legitimize_address_displacement ( rtx * off1 , rtx * off2 , poly_int64 poly_offset , machine_mode ) { HOST_WIDE_INT orig_offset = poly_offset ; HOST_WIDE_INT lo , hi ; if ( orig_offset >= 0 && orig_offset < 2 * 32767 ) { hi = 32767 ; lo = orig_offset - hi ; } else if ( orig_offset < 0 && orig_offset >= 2 * - 32768 ) { hi = - 32768 ; lo = orig_offset - hi ; } else { lo = sext_hwi ( orig_offset , 16 ) ; hi = orig_offset - lo ; } * off1 = GEN_INT ( hi ) ; * off2 = GEN_INT ( lo ) ; return true ; } </s>

Worker for TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT . Split an out-of-range address displacement into hi and lo parts . The hi part will have to be loaded into a register separately , but the low part will be folded into the memory operand .


<s> const uint32_t * ARMBaseRegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return CSR_NoRegs_RegMask ; return STI . isTargetDarwin ( ) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool aarch64_operands_ok_for_ldpstp ( rtx * operands , bool load , machine_mode mode ) { HOST_WIDE_INT offval_1 , offval_2 , msize ; enum reg_class rclass_1 , rclass_2 ; rtx mem_1 , mem_2 , reg_1 , reg_2 , base_1 , base_2 , offset_1 , offset_2 ; if ( load ) { mem_1 = operands [ 1 ] ; mem_2 = operands [ 3 ] ; reg_1 = operands [ 0 ] ; reg_2 = operands [ 2 ] ; gcc_assert ( REG_P ( reg_1 ) && REG_P ( reg_2 ) ) ; if ( REGNO ( reg_1 ) == REGNO ( reg_2 ) ) return false ; } else { mem_1 = operands [ 0 ] ; mem_2 = operands [ 2 ] ; reg_1 = operands [ 1 ] ; reg_2 = operands [ 3 ] ; } if ( MEM_VOLATILE_P ( mem_1 ) || MEM_VOLATILE_P ( mem_2 ) ) return false ; if ( mode == SImode && ( aarch64_tune_params . extra_tuning_flags & AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW ) && ! optimize_size && MEM_ALIGN ( mem_1 ) < 8 * BITS_PER_UNIT ) return false ; extract_base_offset_in_addr ( mem_1 , & base_1 , & offset_1 ) ; if ( base_1 == NULL_RTX || offset_1 == NULL_RTX ) return false ; extract_base_offset_in_addr ( mem_2 , & base_2 , & offset_2 ) ; if ( base_2 == NULL_RTX || offset_2 == NULL_RTX ) return false ; if ( ! rtx_equal_p ( base_1 , base_2 ) ) return false ; offval_1 = INTVAL ( offset_1 ) ; offval_2 = INTVAL ( offset_2 ) ; msize = GET_MODE_SIZE ( mode ) . to_constant ( ) ; if ( offval_1 != ( offval_2 + msize ) && offval_2 != ( offval_1 + msize ) ) return false ; if ( load ) { if ( reg_mentioned_p ( reg_1 , mem_1 ) ) return false ; if ( offval_1 > offval_2 && reg_mentioned_p ( reg_2 , mem_2 ) ) return false ; } if ( REG_P ( reg_1 ) && FP_REGNUM_P ( REGNO ( reg_1 ) ) ) rclass_1 = FP_REGS ; else rclass_1 = GENERAL_REGS ; if ( REG_P ( reg_2 ) && FP_REGNUM_P ( REGNO ( reg_2 ) ) ) rclass_2 = FP_REGS ; else rclass_2 = GENERAL_REGS ; if ( rclass_1 != rclass_2 ) return false ; return true ; } </s>

Given OPERANDS of consecutive load/store , check if we can merge them into ldp/stp . LOAD is true if they are load instructions . MODE is the mode of memory operands .


<s> bool AArch64PassConfig :: addILPOpts ( ) { if ( EnableCondOpt ) addPass ( createAArch64ConditionOptimizerPass ( ) ) ; if ( EnableCCMP ) addPass ( createAArch64ConditionalCompares ( ) ) ; if ( EnableMCR ) addPass ( & MachineCombinerID ) ; if ( EnableEarlyIfConversion ) addPass ( & EarlyIfConverterID ) ; if ( EnableStPairSuppress ) addPass ( createAArch64StorePairSuppressPass ( ) ) ; addPass ( createAArch64VectorByElementOptPass ( ) ) ; return true ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .


<s> bool doInitialization ( Module & M ) override { SM . reset ( ) ; return AsmPrinter :: doInitialization ( M ) ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; AArch64FunctionInfo * AFI = MF . getInfo < AArch64FunctionInfo > ( ) ; if ( AFI -> getNumLocalDynamicTLSAccesses ( ) < 2 ) { return false ; } MachineDominatorTree * DT = & getAnalysis < MachineDominatorTree > ( ) ; return VisitNode ( DT -> getRootNode ( ) , 0 ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> static void frv_pack_insns ( void ) { if ( frv_for_each_packet ( frv_reorder_packet ) ) frv_insn_packing_flag = 0 ; else frv_insn_packing_flag = - 1 ; } </s>

Divide instructions into packets . Reorder the contents of each packet so that they are in the correct assembly-language order . Since this pass can change the raw meaning of the rtl stream , it must only be called at the last minute , just before the instructions are written out .


<s> static enum insn_code aarch64_constant_pool_reload_icode ( machine_mode mode ) { switch ( mode ) { case SFmode : return CODE_FOR_aarch64_reload_movcpsfdi ; case DFmode : return CODE_FOR_aarch64_reload_movcpdfdi ; case TFmode : return CODE_FOR_aarch64_reload_movcptfdi ; case V8QImode : return CODE_FOR_aarch64_reload_movcpv8qidi ; case V16QImode : return CODE_FOR_aarch64_reload_movcpv16qidi ; case V4HImode : return CODE_FOR_aarch64_reload_movcpv4hidi ; case V8HImode : return CODE_FOR_aarch64_reload_movcpv8hidi ; case V2SImode : return CODE_FOR_aarch64_reload_movcpv2sidi ; case V4SImode : return CODE_FOR_aarch64_reload_movcpv4sidi ; case V2DImode : return CODE_FOR_aarch64_reload_movcpv2didi ; case V2DFmode : return CODE_FOR_aarch64_reload_movcpv2dfdi ; default : gcc_unreachable ( ) ; } gcc_unreachable ( ) ; } </s>

Return the reload icode required for a constant pool in mode .


<s>
void
AGCRegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
report_fatal_error
(
"Subroutines not supported yet"
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s>
static
void
mn10300_insert_setlb_lcc
(
rtx_insn
*
label
,
rtx_insn
*
branch
)
{
rtx
lcc
,
comparison
,
cmp_reg
;
if
(
LABEL_NUSES
(
label
)
>
1
)
{
rtx_insn
*
insn
;
DUMP
(
"Inserting SETLB insn after:"
,
label
)
;
insn
=
emit_insn_after
(
gen_setlb
(
)
,
label
)
;
label
=
gen_label_rtx
(
)
;
emit_label_after
(
label
,
insn
)
;
DUMP
(
"Created new loop-back label:"
,
label
)
;
}
else
{
DUMP
(
"Inserting SETLB insn before:"
,
label
)
;
emit_insn_before
(
gen_setlb
(
)
,
label
)
;
}
comparison
=
XEXP
(
SET_SRC
(
PATTERN
(
branch
)
)
,
0
)
;
cmp_reg
=
XEXP
(
comparison
,
0
)
;
gcc_assert
(
REG_P
(
cmp_reg
)
)
;
gcc_assert
(
REGNO
(
cmp_reg
)
==
CC_REG
)
;
if
(
GET_MODE
(
cmp_reg
)
==
CC_FLOATmode
)
lcc
=
gen_FLcc
(
comparison
,
label
)
;
else
lcc
=
gen_Lcc
(
comparison
,
label
)
;
rtx_insn
*
jump
=
emit_jump_insn_before
(
lcc
,
branch
)
;
mark_jump_label
(
XVECEXP
(
lcc
,
0
,
0
)
,
jump
,
0
)
;
JUMP_LABEL
(
jump
)
=
label
;
DUMP
(
"Replacing branch insn..."
,
branch
)
;
DUMP
(
"... with Lcc insn:"
,
jump
)
;
delete_insn
(
branch
)
;
}
</s>

Replace the BRANCH insn with a Lcc insn that goes to LABEL . Insert a SETLB insn just before LABEL .


<s> bool HexagonTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { return Subtarget . hasV5TOps ( ) ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> void expand_epilogue ( ) { unsigned int size ; unsigned int outgoing_args_size = current_function_outgoing_args_size ; int offset , i , temp_regno ; rtx basereg ; size = total_frame_size ( ) ; if ( DECL_RESULT ( current_function_decl ) && DECL_RTL ( DECL_RESULT ( current_function_decl ) ) && REG_P ( DECL_RTL ( DECL_RESULT ( current_function_decl ) ) ) ) temp_regno = ( REGNO ( DECL_RTL ( DECL_RESULT ( current_function_decl ) ) ) == 4 ? 0 : 4 ) ; else temp_regno = 4 ; if ( out_of_line_epilogue ) { if ( get_frame_size ( ) == 0 && outgoing_args_size == 0 ) { emit_jump_insn ( gen_outline_epilogue_jump ( ) ) ; return ; } if ( outgoing_args_size ) emit_insn ( gen_addpsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( outgoing_args_size ) ) ) ; if ( temp_regno == 0 ) emit_insn ( gen_outline_epilogue_call_d0 ( ) ) ; else if ( temp_regno == 4 ) emit_insn ( gen_outline_epilogue_call_a0 ( ) ) ; if ( get_frame_size ( ) != 0 ) emit_insn ( gen_addpsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( size - outgoing_args_size - 16 ) ) ) ; emit_jump_insn ( gen_return_internal ( ) ) ; return ; } if ( frame_pointer_needed ) { basereg = frame_pointer_rtx ; offset = - ( size - outgoing_args_size ) ; } else { basereg = stack_pointer_rtx ; offset = outgoing_args_size ; } for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { if ( ( regs_ever_live [ i ] && ! call_used_regs [ i ] && ! fixed_regs [ i ] ) || ( i == FRAME_POINTER_REGNUM && frame_pointer_needed ) ) { int regno ; regno = ( ( i == FRAME_POINTER_REGNUM && frame_pointer_needed ) ? temp_regno : i ) ; emit_move_insn ( gen_rtx_REG ( PSImode , regno ) , gen_rtx_MEM ( PSImode , plus_constant ( basereg , offset ) ) ) ; offset += 4 ; } } if ( frame_pointer_needed ) { emit_move_insn ( stack_pointer_rtx , frame_pointer_rtx ) ; emit_move_insn ( frame_pointer_rtx , gen_rtx_REG ( PSImode , temp_regno ) ) ; } else if ( size ) { emit_insn ( gen_addpsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( size ) ) ) ; } if ( current_function_needs_context ) emit_insn ( gen_addpsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( 4 ) ) ) ; if ( size == 0 && ! current_function_needs_context ) emit_jump_insn ( gen_return ( ) ) ; else emit_jump_insn ( gen_return_internal ( ) ) ; } </s>


<s> static rtx aarch64_gen_storewb_pair ( machine_mode mode , rtx base , rtx reg , rtx reg2 , HOST_WIDE_INT adjustment ) { switch ( mode ) { case E_DImode : return gen_storewb_pairdi_di ( base , base , reg , reg2 , GEN_INT ( - adjustment ) , GEN_INT ( UNITS_PER_WORD - adjustment ) ) ; case E_DFmode : return gen_storewb_pairdf_di ( base , base , reg , reg2 , GEN_INT ( - adjustment ) , GEN_INT ( UNITS_PER_WORD - adjustment ) ) ; default : gcc_unreachable ( ) ; } } </s>

Generate and return an instruction to store the pair of registers REG and REG2 of mode MODE to location BASE with write-back adjusting the stack location BASE by ADJUSTMENT .


<s> static rtx sparc_builtin_setjmp_frame_value ( void ) { return hard_frame_pointer_rtx ; } </s>

Return the hard frame pointer directly to bypass the stack bias .


<s> X86DCFunction & getParent ( ) { return static_cast < X86DCFunction & > ( DCBasicBlock :: getParent ( ) ) ; } </s>

getParent - Return the last analyzed interval .


<s> TVMSubtarget & TVMSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { ( void ) FS ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "tvm" ; ParseSubtargetFeatures ( CPUName , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> static rtx move_to_x ( int opno , rtx_insn * before ) { rtx src = OP ( opno ) ; machine_mode mode = GET_MODE ( src ) ; rtx reg ; if ( mode == VOIDmode ) mode = recog_data . operand_mode [ opno ] ; reg = ( mode == QImode ) ? X : AX ; if ( mode == QImode || ! is_virtual_register ( OP ( opno ) ) ) { OP ( opno ) = move_to_acc ( opno , before ) ; OP ( opno ) = move_acc_to_reg ( OP ( opno ) , X_REG , before ) ; return reg ; } return gen_and_emit_move ( reg , src , before , true ) ; } </s>

Copy SRC to X , placing any generated insns before BEFORE . Returns X RTX .


"%<bank_switch%> has no effect on non-interrupt functions"

Emits the prologue . See the frame layout comment earlier in this file . We can reserve up to 256 bytes with the ENTER opcode , beyond that we manually update sp .


Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU R600 AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU


<s> int expand_a_rotate ( rtx operands [ ] ) { rtx dst = operands [ 0 ] ; rtx src = operands [ 1 ] ; rtx rotate_amount = operands [ 2 ] ; machine_mode mode = GET_MODE ( dst ) ; if ( h8sx_classify_shift ( mode , ROTATE , rotate_amount ) == H8SX_SHIFT_UNARY ) return false ; emit_move_insn ( dst , src ) ; if ( GET_CODE ( rotate_amount ) != CONST_INT ) { rtx counter = gen_reg_rtx ( QImode ) ; rtx_code_label * start_label = gen_label_rtx ( ) ; rtx_code_label * end_label = gen_label_rtx ( ) ; emit_cmp_and_jump_insns ( rotate_amount , const0_rtx , LE , NULL_RTX , QImode , 0 , end_label ) ; emit_move_insn ( counter , rotate_amount ) ; emit_label ( start_label ) ; switch ( mode ) { case QImode : emit_insn ( gen_rotlqi3_1 ( dst , dst , const1_rtx ) ) ; break ; case HImode : emit_insn ( gen_rotlhi3_1 ( dst , dst , const1_rtx ) ) ; break ; case SImode : emit_insn ( gen_rotlsi3_1 ( dst , dst , const1_rtx ) ) ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen_addqi3 ( counter , counter , constm1_rtx ) ) ; emit_cmp_and_jump_insns ( counter , const0_rtx , NE , NULL_RTX , QImode , 1 , start_label ) ; emit_label ( end_label ) ; } else { switch ( mode ) { case QImode : emit_insn ( gen_rotlqi3_1 ( dst , dst , rotate_amount ) ) ; break ; case HImode : emit_insn ( gen_rotlhi3_1 ( dst , dst , rotate_amount ) ) ; break ; case SImode : emit_insn ( gen_rotlsi3_1 ( dst , dst , rotate_amount ) ) ; break ; default : gcc_unreachable ( ) ; } } return 1 ; } </s>

A rotation by a non-constant will cause a loop to be generated , in which a rotation by one bit is used . A rotation by a constant , including the one in the loop , will be taken care of by emit_a_rotate ( ) at the insn emit time .


<s>
Register
MipsTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
const
MachineFunction
&
MF
)
const
{
if
(
Subtarget
.
isGP64bit
(
)
)
{
Register
Reg
=
StringSwitch
<
Register
>
(
RegName
)
.
Case
(
"$28"
,
Mips
::
GP_64
)
.
Default
(
Register
(
)
)
;
if
(
Reg
)
return
Reg
;
}
else
{
Register
Reg
=
StringSwitch
<
Register
>
(
RegName
)
.
Case
(
"$28"
,
Mips
::
GP
)
.
Default
(
Register
(
)
)
;
if
(
Reg
)
return
Reg
;
}
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> void function_expander :: add_output_operand ( insn_code icode ) { unsigned int opno = m_ops . length ( ) ; machine_mode mode = insn_data [ icode ] . operand [ opno ] . mode ; m_ops . safe_grow ( opno + 1 ) ; create_output_operand ( & m_ops . last ( ) , possible_target , mode ) ; } </s>

Create output and add it into M_OPS and increase OPNO .


<s> bool AArch64PassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( getOptLevel ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createAArch64PostSelectOptimize ( ) ) ; return false ; } </s>

This method should install a ( global ) instruction selector pass , which converts possibly generic instructions to fully target-specific instructions , thereby constraining all generic virtual registers to register classes .


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCRelaxableFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
override
{
llvm_unreachable
(
"relaxInstruction() unimplemented"
)
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { unsigned Idx = Endian == support :: little ? i : 3 - i ; Data [ Offset + Idx ] |= uint8_t ( ( Value >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool SIInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . getFirstTerminator ( ) ; if ( I == MBB . end ( ) ) return false ; if ( I -> getOpcode ( ) != AMDGPU :: SI_MASK_BRANCH ) return analyzeBranchImpl ( MBB , I , TBB , FBB , Cond , AllowModify ) ; ++ I ; if ( I == MBB . end ( ) ) return true ; if ( analyzeBranchImpl ( MBB , I , TBB , FBB , Cond , AllowModify ) ) return true ; MachineBasicBlock * MaskBrDest = I -> getOperand ( 0 ) . getMBB ( ) ; if ( TBB != MaskBrDest || Cond . empty ( ) ) return true ; auto Pred = Cond [ 0 ] . getImm ( ) ; return ( Pred != EXECZ && Pred != EXECNZ ) ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s>
bool
AArch64AdvSIMDScalar
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
bool
Changed
=
false
;
DEBUG
(
dbgs
(
)
<<
"***** AArch64AdvSIMDScalar *****\n"
)
;
if
(
skipFunction
(
mf
.
getFunction
(
)
)
)
return
false
;
MRI
=
&
mf
.
getRegInfo
(
)
;
TII
=
mf
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
for
(
MachineFunction
::
iterator
I
=
mf
.
begin
(
)
,
E
=
mf
.
end
(
)
;
I
!=
E
;
++
I
)
if
(
processMachineBasicBlock
(
&
*
I
)
)
Changed
=
true
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool ARMAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AFI = MF . getInfo < ARMFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; if ( FlagSfiBranch ) { NaclAlignAllJumpTargetsAndConstantPools ( MF ) ; } return AsmPrinter :: runOnMachineFunction ( MF ) ; } </s>


<s> bool arm_change_mode_p ( tree func ) { if ( TREE_CODE ( func ) != FUNCTION_DECL ) return false ; tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET ( func ) ; if ( ! callee_tree ) callee_tree = target_option_default_node ; struct cl_target_option * callee_opts = TREE_TARGET_OPTION ( callee_tree ) ; int flags = callee_opts -> x_target_flags ; return ( TARGET_THUMB_P ( flags ) != TARGET_THUMB ) ; } </s>

Check that FUNC is called with a different mode .


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT LHSTy ) const override { return LHSTy . getSizeInBits ( ) <= 32 ? MVT :: i32 : MVT :: i64 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> tree function_resolver :: lookup_form ( mode_suffix_index mode , type_suffix_index type0 , type_suffix_index type1 ) { type_suffix_pair types = { type0 , type1 } ; function_instance instance ( base_name , base , shape , mode , types , pred ) ; registered_function * rfn = function_table -> find_with_hash ( instance , instance . hash ( ) ) ; return rfn ? rfn -> decl : NULL_TREE ; } </s>

Silently check whether there is an instance of the function with the mode suffix given by MODE and the type suffixes given by TYPE0 and TYPE1 . Return its function decl if so , otherwise return null .


<s> void order_regs_for_local_alloc ( void ) { static int last_order_nonleaf = 1 ; if ( regs_ever_live [ 15 ] != last_order_nonleaf ) { last_order_nonleaf = ! last_order_nonleaf ; memcpy ( ( char * ) reg_alloc_order , ( const char * ) reg_alloc_orders [ last_order_nonleaf ] , FIRST_PSEUDO_REGISTER * sizeof ( int ) ) ; } } </s>

Choose the order in which to allocate hard registers for pseudo-registers local to a basic block . Store the desired register order in the array ` reg_alloc_order ' . Element 0 should be the register to allocate first ; element 1 , the next register ; and so on .


<s>
void
MipsInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineMemOperand
*
MMO
=
GetMemOperand
(
MBB
,
FI
,
MachineMemOperand
::
MOLoad
)
;
unsigned
Opc
=
0
;
if
(
Mips
::
CPURegsRegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
IsN64
Mips
::
LW_P8
:
Mips
::
LW
;
else
if
(
Mips
::
CPU64RegsRegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
IsN64
Mips
::
LD_P8
:
Mips
::
LD
;
else
if
(
Mips
::
FGR32RegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
IsN64
Mips
::
LWC1_P8
:
Mips
::
LWC1
;
else
if
(
Mips
::
AFGR64RegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
Mips
::
LDC1
;
else
if
(
Mips
::
FGR64RegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
IsN64
Mips
::
LDC164_P8
:
Mips
::
LDC164
;
assert
(
Opc
&&
"Register class not handled!"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> OperandMatchResultTy RISCVAsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { const AsmToken & Tok = getParser ( ) . getTok ( ) ; StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; RegNo = 0 ; StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( matchRegisterNameHelper ( isRV32E ( ) , ( MCRegister & ) RegNo , Name ) ) return MatchOperand_NoMatch ; getParser ( ) . Lex ( ) ; return MatchOperand_Success ; } </s>

tryParseRegister - parse one register if possible


<s> const char * XCoreTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case XCoreISD :: BL : return "XCoreISD::BL" ; case XCoreISD :: PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper" ; case XCoreISD :: DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper" ; case XCoreISD :: CPRelativeWrapper : return "XCoreISD::CPRelativeWrapper" ; case XCoreISD :: STWSP : return "XCoreISD::STWSP" ; case XCoreISD :: RETSP : return "XCoreISD::RETSP" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific

XCore XCore XCoreISD::BL "XCoreISD::BL" XCoreISD::PCRelativeWrapper "XCoreISD::PCRelativeWrapper" XCoreISD::DPRelativeWrapper "XCoreISD::DPRelativeWrapper" XCoreISD::CPRelativeWrapper "XCoreISD::CPRelativeWrapper" XCoreISD::STWSP "XCoreISD::STWSP" XCoreISD::RETSP "XCoreISD::RETSP"


<s> unsigned char X86Subtarget :: classifyGlobalReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return X86II :: MO_NO_FLAG ; Reloc :: Model RM = TM . getRelocationModel ( ) ; if ( shouldAssumeDSOLocal ( RM , TargetTriple , M , GV ) ) return classifyLocalReference ( GV ) ; if ( isTargetCOFF ( ) ) return X86II :: MO_DLLIMPORT ; if ( is64Bit ( ) ) return X86II :: MO_GOTPCREL ; if ( isTargetDarwin ( ) ) { if ( RM != Reloc :: PIC_ ) return X86II :: MO_DARWIN_NONLAZY ; return X86II :: MO_DARWIN_NONLAZY_PIC_BASE ; } return X86II :: MO_GOT ; } </s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s>
static
void
nvptx_dump_pars
(
parallel
*
par
,
unsigned
depth
)
{
fprintf
(
dump_file
,
"%u: mask %d head=%d, tail=%d\n"
,
depth
,
par
->
mask
,
par
->
forked_block
par
->
forked_block
->
index
:
1
,
par
->
join_block
par
->
join_block
->
index
:
1
)
;
fprintf
(
dump_file
,
"    blocks:"
)
;
basic_block
block
;
for
(
unsigned
ix
=
0
;
par
->
blocks
.
iterate
(
ix
,
&
block
)
;
ix
++
)
fprintf
(
dump_file
,
" %d"
,
block
->
index
)
;
fprintf
(
dump_file
,
"\n"
)
;
if
(
par
->
inner
)
nvptx_dump_pars
(
par
->
inner
,
depth
+
1
)
;
if
(
par
->
next
)
nvptx_dump_pars
(
par
->
next
,
depth
)
;
}
</s>

See also 'gcc/omp-oacc-neuter-broadcast.cc : omp_sese_dump_pars ' .


<s>
static
char
*
describe_cache
(
unsigned
l1_sizekb
,
unsigned
l1_line
,
unsigned
l1_assoc
ATTRIBUTE_UNUSED
,
unsigned
l2_sizekb
)
{
char
l1size
[
1000
]
,
line
[
1000
]
,
l2size
[
1000
]
;
sprintf
(
l1size
,
"--param l1-cache-size=%u"
,
l1_sizekb
)
;
sprintf
(
line
,
"--param l1-cache-line-size=%u"
,
l1_line
)
;
sprintf
(
l2size
,
"--param l2-cache-size=%u"
,
l2_sizekb
)
;
return
concat
(
l1size
,
" "
,
line
,
" "
,
l2size
,
" "
,
)
;
}
</s>

Returns parameters that describe L1_ASSOC associative cache of size L1_SIZEKB with lines of size L1_LINE , and L2_SIZEKB .

powerpcspe
1000
1000
1000
"--param l1-cache-size=%u"
"--param l1-cache-line-size=%u"
"--param l2-cache-size=%u"
" "
" "
" "


<s> MachineInstrBuilder SIInstrInfo :: buildIndirectRead ( MachineBasicBlock * MBB , MachineBasicBlock :: iterator I , unsigned ValueReg , unsigned Address , unsigned OffsetReg ) const { const DebugLoc & DL = MBB -> findDebugLoc ( I ) ; unsigned IndirectBaseReg = AMDGPU :: VGPR_32RegClass . getRegister ( getIndirectIndexBegin ( * MBB -> getParent ( ) ) ) ; return BuildMI ( * MBB , I , DL , get ( AMDGPU :: SI_INDIRECT_SRC ) ) . addOperand ( I -> getOperand ( 0 ) ) . addOperand ( I -> getOperand ( 1 ) ) . addReg ( IndirectBaseReg ) . addReg ( OffsetReg ) . addImm ( 0 ) ; } </s>

Build instruction ( s ) for an indirect register read .


<s> bool SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) override { const TargetRegisterInfo * TRI = TM . getRegisterInfo ( ) ; const TargetRegisterClass * TRC = TRI -> getPointerRegClass ( * MF , 1 ) ; SDValue RC = CurDAG -> getTargetConstant ( TRC -> getID ( ) , MVT :: i32 ) ; SDValue NewOp = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , SDLoc ( Op ) , Op . getValueType ( ) , Op , RC ) , 0 ) ; OutOps . push_back ( NewOp ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> void PPCPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { initializePPCVSXFMAMutatePass ( * PassRegistry :: getPassRegistry ( ) ) ; insertPass ( VSXFMAMutateEarly ? & RegisterCoalescerID : & MachineSchedulerID , & PPCVSXFMAMutateID ) ; } if ( getPPCTargetMachine ( ) . isPositionIndependent ( ) ) { addPass ( & LiveVariablesID , false ) ; addPass ( createPPCTLSDynamicCallPass ( ) ) ; } if ( EnableExtraTOCRegDeps ) addPass ( createPPCTOCRegDepsPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> void WebAssemblyPassConfig :: addPostRegAlloc ( ) { disablePass ( & MachineCopyPropagationID ) ; disablePass ( & PostRAMachineSinkingID ) ; disablePass ( & PostRASchedulerID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & StackMapLivenessID ) ; disablePass ( & LiveDebugValuesID ) ; disablePass ( & PatchableFunctionID ) ; disablePass ( & ShrinkWrapID ) ; disablePass ( & MachineBlockPlacementID ) ; TargetPassConfig :: addPostRegAlloc ( ) ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> static bool mayAlias ( MachineInstr * MIa , SmallVectorImpl < MachineInstr * > & MemInsns , const AArch64InstrInfo * TII ) { for ( auto & MIb : MemInsns ) if ( mayAlias ( MIa , MIb , TII ) ) return true ; return false ; } </s>

Returns true if this instruction 's memory access aliases the memory access of Other .


<s> static bool rs6000_secondary_reload_move ( enum rs6000_reg_type to_type , enum rs6000_reg_type from_type , machine_mode mode , secondary_reload_info * sri , bool altivec_p ) { if ( to_type == NO_REG_TYPE || from_type == NO_REG_TYPE ) return false ; if ( ( to_type == PSEUDO_REG_TYPE && from_type == PSEUDO_REG_TYPE ) || ( to_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE ( from_type ) ) || ( from_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE ( to_type ) ) ) return true ; if ( to_type == from_type && IS_STD_REG_TYPE ( to_type ) ) return true ; if ( rs6000_secondary_reload_simple_move ( to_type , from_type , mode ) ) { if ( sri ) { sri -> icode = CODE_FOR_nothing ; sri -> extra_cost = 0 ; } return true ; } return rs6000_secondary_reload_direct_move ( to_type , from_type , mode , sri , altivec_p ) ; } </s>

Return whether a move between two register classes can be done either directly ( simple move ) or via a pattern that uses a single extra temporary ( using power8 's direct move in this case .


<s>
SDValue
MipsTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
DL
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
,
TargetLowering
::
CallLoweringInfo
&
CLI
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
MipsCCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_Mips
,
CLI
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Val
=
DAG
.
getCopyFromReg
(
Chain
,
DL
,
RVLocs
[
i
]
.
getLocReg
(
)
,
RVLocs
[
i
]
.
getLocVT
(
)
,
InFlag
)
;
Chain
=
Val
.
getValue
(
1
)
;
InFlag
=
Val
.
getValue
(
2
)
;
if
(
VA
.
isUpperBitsInLoc
(
)
)
{
unsigned
ValSizeInBits
=
Ins
[
i
]
.
ArgVT
.
getSizeInBits
(
)
;
unsigned
LocSizeInBits
=
VA
.
getLocVT
(
)
.
getSizeInBits
(
)
;
unsigned
Shift
=
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExtUpper
ISD
::
SRL
:
ISD
::
SRA
;
Val
=
DAG
.
getNode
(
Shift
,
DL
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getConstant
(
LocSizeInBits
ValSizeInBits
,
VA
.
getLocVT
(
)
)
)
;
}
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
BCvt
:
Val
=
DAG
.
getNode
(
ISD
::
BITCAST
,
DL
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
AExt
:
case
CCValAssign
::
AExtUpper
:
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
DL
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
ZExt
:
case
CCValAssign
::
ZExtUpper
:
Val
=
DAG
.
getNode
(
ISD
::
AssertZext
,
DL
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
DL
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
SExt
:
case
CCValAssign
::
SExtUpper
:
Val
=
DAG
.
getNode
(
ISD
::
AssertSext
,
DL
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
DL
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
}
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .

Mips
Mips
ISD::InputArg
16
Mips
Mips
0
"Can only return in registers!"
1
2
ISD::SRL
ISD::SRA
"Unknown loc info!"
ISD::BITCAST
ISD::TRUNCATE
ISD::AssertZext
ISD::TRUNCATE
ISD::AssertSext
ISD::TRUNCATE


<s> void rs6000_sibcall_aix ( rtx value , rtx func_desc , rtx flag , rtx cookie ) { rtx call [ 2 ] ; rtx insn ; gcc_assert ( INTVAL ( cookie ) == 0 ) ; call [ 0 ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_desc ) , flag ) ; if ( value != NULL_RTX ) call [ 0 ] = gen_rtx_SET ( value , call [ 0 ] ) ; call [ 1 ] = simple_return_rtx ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( 2 , call ) ) ; insn = emit_call_insn ( insn ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , gen_rtx_REG ( Pmode , TOC_REGNUM ) ) ; } </s>

Expand code to perform a sibling call under the AIX or ELFv2 ABI .


<s> unsigned getOpSize ( const MachineInstr & MI , unsigned OpNo ) const { return getOpRegClass ( MI , OpNo ) -> getSize ( ) ; } </s>

This form should usually be preferred since it handles operands with unknown register classes .


<s> bool X86TTIImpl :: isLegalMaskedGather ( Type * DataTy ) { if ( isa < VectorType > ( DataTy ) && ! isPowerOf2_32 ( DataTy -> getVectorNumElements ( ) ) ) return false ; Type * ScalarTy = DataTy -> getScalarType ( ) ; int DataWidth = isa < PointerType > ( ScalarTy ) ? DL . getPointerSizeInBits ( ) : ScalarTy -> getPrimitiveSizeInBits ( ) ; return ( DataWidth == 32 || DataWidth == 64 ) && ST -> hasAVX512 ( ) ; } </s>

Return true if the target supports masked gather .


<s> bool runOnFunction ( Function & F ) override { visit ( F ) ; return false ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s>
static
int
frv_arg_partial_bytes
(
cumulative_args_t
cum
,
machine_mode
mode
,
tree
type
ATTRIBUTE_UNUSED
,
bool
named
ATTRIBUTE_UNUSED
)
{
machine_mode
xmode
=
(
mode
==
BLKmode
)
SImode
:
mode
;
int
bytes
=
GET_MODE_SIZE
(
xmode
)
;
int
words
=
(
bytes
+
UNITS_PER_WORD
1
)
/
UNITS_PER_WORD
;
int
arg_num
=
*
get_cumulative_args
(
cum
)
;
int
ret
;
ret
=
(
(
arg_num
<=
LAST_ARG_REGNUM
&&
arg_num
+
words
>
LAST_ARG_REGNUM
+
1
)
LAST_ARG_REGNUM
arg_num
+
1
:
0
)
;
ret
*=
UNITS_PER_WORD
;
if
(
TARGET_DEBUG_ARG
&&
ret
)
fprintf
(
stderr
,
"frv_arg_partial_bytes: %d\n"
,
ret
)
;
return
ret
;
}
</s>

A C expression for the number of words , at the beginning of an argument , must be put in registers . The value must be zero for arguments that are passed entirely in registers or that are entirely pushed on the stack . On some machines , certain arguments must be passed partially in registers and partially in memory . On these machines , typically the first N words of arguments are passed in registers , and the rest on the stack . If a multi-word argument ( a ` double ' or a structure ) crosses that boundary , its first few words must be passed in registers and the rest must be pushed . This macro tells the compiler when this occurs , and how many of the words should go in registers . ` FUNCTION_ARG ' for these arguments should return the first register to be used by the caller for this argument ; likewise ` FUNCTION_INCOMING_ARG ' , for the called function .


<s>
SDValue
AVRTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
if
(
CallConv
==
CallingConv
::
AVR_BUILTIN
)
{
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_AVR_BUILTIN
)
;
}
else
{
analyzeReturnValues
(
Outs
,
CCInfo
,
Subtarget
.
hasTinyEncoding
(
)
)
;
}
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
if
(
MF
.
getFunction
(
)
.
getAttributes
(
)
.
hasFnAttr
(
Attribute
::
Naked
)
)
{
return
Chain
;
}
const
AVRMachineFunctionInfo
*
AFI
=
MF
.
getInfo
<
AVRMachineFunctionInfo
>
(
)
;
unsigned
RetOpc
=
AFI
->
isInterruptOrSignalHandler
(
)
AVRISD
::
RETI_FLAG
:
AVRISD
::
RET_FLAG
;
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
{
RetOps
.
push_back
(
Flag
)
;
}
return
DAG
.
getNode
(
RetOpc
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s>
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
MipsTargetLowering
::
getRegForInlineAsmConstraint
(
const
std
::
string
&
Constraint
,
MVT
VT
)
const
{
if
(
Constraint
.
size
(
)
==
1
)
{
switch
(
Constraint
[
0
]
)
{
case
'd'
:
case
'y'
:
case
'r'
:
if
(
VT
==
MVT
::
i32
||
VT
==
MVT
::
i16
||
VT
==
MVT
::
i8
)
{
if
(
Subtarget
.
inMips16Mode
(
)
)
return
std
::
make_pair
(
0U
,
&
Mips
::
CPU16RegsRegClass
)
;
return
std
::
make_pair
(
0U
,
&
Mips
::
GPR32RegClass
)
;
}
if
(
VT
==
MVT
::
i64
&&
!
Subtarget
.
isGP64bit
(
)
)
return
std
::
make_pair
(
0U
,
&
Mips
::
GPR32RegClass
)
;
if
(
VT
==
MVT
::
i64
&&
Subtarget
.
isGP64bit
(
)
)
return
std
::
make_pair
(
0U
,
&
Mips
::
GPR64RegClass
)
;
return
std
::
make_pair
(
0U
,
nullptr
)
;
case
'f'
:
if
(
VT
==
MVT
::
f32
)
return
std
::
make_pair
(
0U
,
&
Mips
::
FGR32RegClass
)
;
else
if
(
(
VT
==
MVT
::
f64
)
&&
(
!
Subtarget
.
isSingleFloat
(
)
)
)
{
return
std
::
make_pair
(
0U
,
&
Mips
::
AFGR64RegClass
)
;
}
break
;
case
'c'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
(
unsigned
)
Mips
::
T9
,
&
Mips
::
GPR32RegClass
)
;
assert
(
VT
==
MVT
::
i64
&&
"Unexpected type."
)
;
return
std
::
make_pair
(
(
unsigned
)
Mips
::
T9_64
,
&
Mips
::
GPR64RegClass
)
;
case
'l'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
(
unsigned
)
Mips
::
LO0
,
&
Mips
::
LO32RegClass
)
;
return
std
::
make_pair
(
(
unsigned
)
Mips
::
LO0_64
,
&
Mips
::
LO64RegClass
)
;
case
'x'
:
return
std
::
make_pair
(
0U
,
nullptr
)
;
}
}
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
R
;
R
=
parseRegForInlineAsmConstraint
(
Constraint
,
VT
)
;
if
(
R
.
second
)
return
R
;
return
TargetLowering
::
getRegForInlineAsmConstraint
(
Constraint
,
VT
)
;
}
</s>

Given a physical register constraint ( e.g .


<s> bool ARMBaseInstrInfo :: isPredicable ( MachineInstr * MI ) const { const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( ! MCID . isPredicable ( ) ) return false ; if ( ( MCID . TSFlags & ARMII :: DomainMask ) == ARMII :: DomainNEON ) { ARMFunctionInfo * AFI = MI -> getParent ( ) -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; return AFI -> isThumb2Function ( ) ; } return true ; } </s>

Return true if the specified instruction can be predicated .

ARM ARM ARMII::DomainMask ARMII::DomainNEON ARM ARM


<s> static rtx find_alignment_op ( rtx_insn * insn , rtx base_reg ) { df_ref base_use ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; rtx and_operation = 0 ; FOR_EACH_INSN_INFO_USE ( base_use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( base_use ) , base_reg ) ) continue ; struct df_link * base_def_link = DF_REF_CHAIN ( base_use ) ; if ( ! base_def_link || base_def_link -> next ) break ; if ( DF_REF_IS_ARTIFICIAL ( base_def_link -> ref ) ) break ; rtx_insn * and_insn = DF_REF_INSN ( base_def_link -> ref ) ; and_operation = alignment_mask ( and_insn ) ; if ( and_operation != 0 ) break ; } return and_operation ; } </s>

Given INSN that 's a load or store based at BASE_REG , check if all of its feeding computations align its address on a 16-byte boundary . If so , return true and add all definition insns into AND_INSNS and their corresponding fully-expanded rtxes for the masking operations into AND_OPS .


<s> bool NVPTXLowerStructArgs :: runOnFunction ( Function & F ) { if ( ! isKernelFunction ( F ) ) return false ; handleStructPtrArgs ( F ) ; return true ; } </s>


<s>
MachineBasicBlock
*
SparcTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown SELECT_CC!"
)
;
case
SP
::
SELECT_CC_Int_ICC
:
case
SP
::
SELECT_CC_FP_ICC
:
case
SP
::
SELECT_CC_DFP_ICC
:
case
SP
::
SELECT_CC_QFP_ICC
:
return
expandSelectCC
(
MI
,
BB
,
SP
::
BCOND
)
;
case
SP
::
SELECT_CC_Int_FCC
:
case
SP
::
SELECT_CC_FP_FCC
:
case
SP
::
SELECT_CC_DFP_FCC
:
case
SP
::
SELECT_CC_QFP_FCC
:
return
expandSelectCC
(
MI
,
BB
,
SP
::
FBCOND
)
;
case
SP
::
EH_SJLJ_SETJMP32ri
:
case
SP
::
EH_SJLJ_SETJMP32rr
:
return
emitEHSjLjSetJmp
(
MI
,
BB
)
;
case
SP
::
EH_SJLJ_LONGJMP32rr
:
case
SP
::
EH_SJLJ_LONGJMP32ri
:
return
emitEHSjLjLongJmp
(
MI
,
BB
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> SMRange getLocRange ( ) const { return SMRange ( StartLoc , EndLoc ) ; } </s>

getLocRange - Get the range between the first and last token of this operand .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Xtensa Instruction Selection"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
MachineInstr
*
ARMBaseInstrInfo
::
optimizeSelect
(
MachineInstr
&
MI
,
SmallPtrSetImpl
<
MachineInstr
*
>
&
SeenMIs
,
bool
PreferFalse
)
const
{
assert
(
(
MI
.
getOpcode
(
)
==
ARM
::
MOVCCr
||
MI
.
getOpcode
(
)
==
ARM
::
t2MOVCCr
)
&&
"Unknown select instruction"
)
;
MachineRegisterInfo
&
MRI
=
MI
.
getParent
(
)
->
getParent
(
)
->
getRegInfo
(
)
;
MachineInstr
*
DefMI
=
canFoldIntoMOVCC
(
MI
.
getOperand
(
2
)
.
getReg
(
)
,
MRI
,
this
)
;
bool
Invert
=
!
DefMI
;
if
(
!
DefMI
)
DefMI
=
canFoldIntoMOVCC
(
MI
.
getOperand
(
1
)
.
getReg
(
)
,
MRI
,
this
)
;
if
(
!
DefMI
)
return
nullptr
;
MachineOperand
FalseReg
=
MI
.
getOperand
(
Invert
2
:
1
)
;
MachineOperand
TrueReg
=
MI
.
getOperand
(
Invert
1
:
2
)
;
Register
DestReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
const
TargetRegisterClass
*
FalseClass
=
MRI
.
getRegClass
(
FalseReg
.
getReg
(
)
)
;
const
TargetRegisterClass
*
TrueClass
=
MRI
.
getRegClass
(
TrueReg
.
getReg
(
)
)
;
if
(
!
MRI
.
constrainRegClass
(
DestReg
,
FalseClass
)
)
return
nullptr
;
if
(
!
MRI
.
constrainRegClass
(
DestReg
,
TrueClass
)
)
return
nullptr
;
MachineInstrBuilder
NewMI
=
BuildMI
(
*
MI
.
getParent
(
)
,
MI
,
MI
.
getDebugLoc
(
)
,
DefMI
->
getDesc
(
)
,
DestReg
)
;
const
MCInstrDesc
&
DefDesc
=
DefMI
->
getDesc
(
)
;
for
(
unsigned
i
=
1
,
e
=
DefDesc
.
getNumOperands
(
)
;
i
!=
e
&&
!
DefDesc
.
OpInfo
[
i
]
.
isPredicate
(
)
;
++
i
)
NewMI
.
add
(
DefMI
->
getOperand
(
i
)
)
;
unsigned
CondCode
=
MI
.
getOperand
(
3
)
.
getImm
(
)
;
if
(
Invert
)
NewMI
.
addImm
(
ARMCC
::
getOppositeCondition
(
ARMCC
::
CondCodes
(
CondCode
)
)
)
;
else
NewMI
.
addImm
(
CondCode
)
;
NewMI
.
add
(
MI
.
getOperand
(
4
)
)
;
if
(
NewMI
->
hasOptionalDef
(
)
)
NewMI
.
add
(
condCodeOp
(
)
)
;
FalseReg
.
setImplicit
(
)
;
NewMI
.
add
(
FalseReg
)
;
NewMI
->
tieOperands
(
0
,
NewMI
->
getNumOperands
(
)
1
)
;
SeenMIs
.
insert
(
NewMI
)
;
SeenMIs
.
erase
(
DefMI
)
;
if
(
DefMI
->
getParent
(
)
!=
MI
.
getParent
(
)
)
NewMI
->
clearKillInfo
(
)
;
DefMI
->
eraseFromParent
(
)
;
return
NewMI
;
}
</s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


<s> EVT AlphaTargetLowering :: getSetCCResultType ( EVT VT ) const { return MVT :: i64 ; } </s>

Return the value type to use for ISD : :SETCC .


<s>
SDValue
WebAssemblyTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"unimplemented operation lowering"
)
;
return
SDValue
(
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
BR_JT
:
return
LowerBR_JT
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

WebAssembly
WebAssembly
"unimplemented operation lowering"
ISD::GlobalAddress
ISD::JumpTable
ISD::BR_JT


<s>
const
char
*
emit_fusion_p9_store
(
rtx
mem
,
rtx
reg
,
rtx
tmp_reg
)
{
machine_mode
mode
=
GET_MODE
(
reg
)
;
rtx
hi
;
rtx
lo
;
rtx
addr
;
const
char
*
store_string
;
int
r
;
if
(
GET_CODE
(
reg
)
==
SUBREG
)
{
gcc_assert
(
SUBREG_BYTE
(
reg
)
==
0
)
;
reg
=
SUBREG_REG
(
reg
)
;
}
if
(
!
REG_P
(
reg
)
)
fatal_insn
(
"emit_fusion_p9_store, bad reg #1"
,
reg
)
;
r
=
REGNO
(
reg
)
;
if
(
FP_REGNO_P
(
r
)
)
{
if
(
mode
==
SFmode
)
store_string
=
"stfs"
;
else
if
(
mode
==
DFmode
)
store_string
=
"stfd"
;
else
gcc_unreachable
(
)
;
}
else
if
(
ALTIVEC_REGNO_P
(
r
)
&&
TARGET_P9_VECTOR
)
{
if
(
mode
==
SFmode
)
store_string
=
"stxssp"
;
else
if
(
mode
==
DFmode
||
mode
==
DImode
)
store_string
=
"stxsd"
;
else
gcc_unreachable
(
)
;
}
else
if
(
INT_REGNO_P
(
r
)
)
{
switch
(
mode
)
{
case
E_QImode
:
store_string
=
"stb"
;
break
;
case
E_HImode
:
store_string
=
"sth"
;
break
;
case
E_SImode
:
case
E_SFmode
:
store_string
=
"stw"
;
break
;
case
E_DImode
:
case
E_DFmode
:
if
(
!
TARGET_POWERPC64
)
gcc_unreachable
(
)
;
store_string
=
"std"
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
else
fatal_insn
(
"emit_fusion_p9_store, bad reg #2"
,
reg
)
;
if
(
!
MEM_P
(
mem
)
)
fatal_insn
(
"emit_fusion_p9_store not MEM"
,
mem
)
;
addr
=
XEXP
(
mem
,
0
)
;
fusion_split_address
(
addr
,
&
hi
,
&
lo
)
;
emit_fusion_addis
(
tmp_reg
,
hi
)
;
emit_fusion_load_store
(
reg
,
tmp_reg
,
lo
,
store_string
)
;
return
""
;
}
</s>

Return a string to fuse an addis instruction with a store using extended fusion . The address that is used is the logical address that was formed during peephole2 : ( lo_sum ( high ) ( low-part ) ) The code is complicated , so we call output_asm_insn directly , and just return `` '' .

rs6000
0
"emit_fusion_p9_store, bad reg #1"
"stfs"
"stfd"
"stxssp"
"stxsd"
"stb"
"sth"
"stw"
"std"
"emit_fusion_p9_store, bad reg #2"
"emit_fusion_p9_store not MEM"
0
""


Decide whether we should reserve space for callee-save target registers , in case target register allocation wants to use them . REGS_SAVED is the space , in bytes , that is already required for register saves . LIVE_REGS_MASK is the register mask calculated by calc_live_regs .


<s> void R600SchedStrategy :: initialize ( ScheduleDAGMI * dag ) { DAG = dag ; TII = static_cast < const R600InstrInfo * > ( DAG -> TII ) ; TRI = static_cast < const R600RegisterInfo * > ( DAG -> TRI ) ; VLIW5 = ! DAG -> MF . getTarget ( ) . getSubtarget < AMDGPUSubtarget > ( ) . hasCaymanISA ( ) ; MRI = & DAG -> MRI ; CurInstKind = IDOther ; CurEmitted = 0 ; OccupedSlotsMask = 31 ; InstKindLimit [ IDAlu ] = TII -> getMaxAlusPerClause ( ) ; InstKindLimit [ IDOther ] = 32 ; const AMDGPUSubtarget & ST = DAG -> TM . getSubtarget < AMDGPUSubtarget > ( ) ; InstKindLimit [ IDFetch ] = ST . getTexVTXClauseSize ( ) ; AluInstCount = 0 ; FetchInstCount = 0 ; } </s>

Initialize the strategy after building the DAG for a new region .


<s> static int ix86_count_insn ( basic_block bb ) { edge e ; edge_iterator ei ; int min_prev_count ; min_prev_count = 4 ; FOR_EACH_EDGE ( e , ei , bb -> preds ) { edge prev_e ; edge_iterator prev_ei ; if ( e -> src == ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) { min_prev_count = 0 ; break ; } FOR_EACH_EDGE ( prev_e , prev_ei , e -> src -> preds ) { if ( prev_e -> src == ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) { int count = ix86_count_insn_bb ( e -> src ) ; if ( count < min_prev_count ) min_prev_count = count ; break ; } } } if ( min_prev_count < 4 ) min_prev_count += ix86_count_insn_bb ( bb ) ; return min_prev_count ; } </s>

Count the minimum number of instructions in code path in BB . Return 4 if the number of instructions > = 4 .


<s> bool HexagonMCChecker :: check ( bool FullCheck ) { bool chkB = checkBranches ( ) ; bool chkP = checkPredicates ( ) ; bool chkNV = checkNewValues ( ) ; bool chkR = checkRegisters ( ) ; bool chkS = checkSolo ( ) ; bool chkSh = true ; if ( FullCheck ) chkSh = checkShuffle ( ) ; bool chkSl = true ; if ( FullCheck ) chkSl = checkSlots ( ) ; bool chk = chkB && chkP && chkNV && chkR && chkS && chkSh && chkSl ; return chk ; } </s>

Check if the constraints are satisfiable .


<s> bool ix86_libc_has_function ( enum function_class fn_class ) { return targetm . libc_has_function ( fn_class , NULL_TREE ) ; } </s>

We add this as a workaround in order to use libc_has_function hook in i386.md .


<s> void SIInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; SIMachineFunctionInfo * MFI = MF -> getInfo < SIMachineFunctionInfo > ( ) ; MachineFrameInfo & FrameInfo = MF -> getFrameInfo ( ) ; const DebugLoc & DL = MBB . findDebugLoc ( MI ) ; unsigned Align = FrameInfo . getObjectAlignment ( FrameIndex ) ; unsigned Size = FrameInfo . getObjectSize ( FrameIndex ) ; unsigned SpillSize = TRI -> getSpillSize ( * RC ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad , Size , Align ) ; if ( RI . isSGPRClass ( RC ) ) { MFI -> setHasSpilledSGPRs ( ) ; const MCInstrDesc & OpDesc = get ( getSGPRSpillRestoreOpcode ( SpillSize ) ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DestReg ) && SpillSize == 4 ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( DestReg , & AMDGPU :: SReg_32_XM0RegClass ) ; } if ( RI . spillSGPRToVGPR ( ) ) FrameInfo . setStackID ( FrameIndex , TargetStackID :: SGPRSpill ) ; MachineInstrBuilder Spill = BuildMI ( MBB , MI , DL , OpDesc , DestReg ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getStackPtrOffsetReg ( ) , RegState :: Implicit ) ; if ( ST . hasScalarStores ( ) ) { Spill . addReg ( AMDGPU :: M0 , RegState :: ImplicitDefine | RegState :: Dead ) ; } return ; } unsigned Opcode = RI . hasAGPRs ( RC ) ? getAGPRSpillRestoreOpcode ( SpillSize ) : getVGPRSpillRestoreOpcode ( SpillSize ) ; auto MIB = BuildMI ( MBB , MI , DL , get ( Opcode ) , DestReg ) ; if ( RI . hasAGPRs ( RC ) ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; unsigned Tmp = MRI . createVirtualRegister ( & AMDGPU :: VGPR_32RegClass ) ; MIB . addReg ( Tmp , RegState :: Define ) ; } MIB . addFrameIndex ( FrameIndex ) . addReg ( MFI -> getScratchRSrcReg ( ) ) . addReg ( MFI -> getStackPtrOffsetReg ( ) ) . addImm ( 0 ) . addMemOperand ( MMO ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> static void tilepro_gen_bundles ( void ) { basic_block bb ; FOR_EACH_BB_FN ( bb , cfun ) { rtx_insn * insn , * next ; rtx_insn * end = NEXT_INSN ( BB_END ( bb ) ) ; for ( insn = next_insn_to_bundle ( BB_HEAD ( bb ) , end ) ; insn ; insn = next ) { next = next_insn_to_bundle ( NEXT_INSN ( insn ) , end ) ; if ( GET_CODE ( PATTERN ( insn ) ) != ASM_INPUT ) { if ( next == NULL_RTX || GET_MODE ( next ) == TImode || CALL_P ( insn ) ) { PUT_MODE ( insn , QImode ) ; } else { PUT_MODE ( insn , SImode ) ; } } } } } </s>

Go through all insns , and use the information generated during scheduling to generate SEQUENCEs to represent bundles of instructions issued simultaneously .


<s> void RISCVTargetStreamer :: emitTargetAttributes ( const MCSubtargetInfo & STI ) { if ( STI . hasFeature ( RISCV :: FeatureRV32E ) ) emitAttribute ( RISCVAttrs :: STACK_ALIGN , RISCVAttrs :: ALIGN_4 ) ; else emitAttribute ( RISCVAttrs :: STACK_ALIGN , RISCVAttrs :: ALIGN_16 ) ; std :: string Arch = "rv32" ; if ( STI . hasFeature ( RISCV :: Feature64Bit ) ) Arch = "rv64" ; if ( STI . hasFeature ( RISCV :: FeatureRV32E ) ) Arch += "e1p9" ; else Arch += "i2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtM ) ) Arch += "_m2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtA ) ) Arch += "_a2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtF ) ) Arch += "_f2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtD ) ) Arch += "_d2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtC ) ) Arch += "_c2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtB ) ) Arch += "_b0p93" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtV ) ) Arch += "_v1p0" ; if ( STI . hasFeature ( RISCV :: FeatureExtZfh ) ) Arch += "_zfh0p1" ; if ( STI . hasFeature ( RISCV :: FeatureExtZba ) ) Arch += "_zba0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbb ) ) Arch += "_zbb0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbc ) ) Arch += "_zbc0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbe ) ) Arch += "_zbe0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbf ) ) Arch += "_zbf0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbm ) ) Arch += "_zbm0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbp ) ) Arch += "_zbp0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbproposedc ) ) Arch += "_zbproposedc0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbr ) ) Arch += "_zbr0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbs ) ) Arch += "_zbs0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbt ) ) Arch += "_zbt0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZvamo ) ) Arch += "_zvamo1p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZvlsseg ) ) Arch += "_zvlsseg1p0" ; emitTextAttribute ( RISCVAttrs :: ARCH , Arch ) ; } </s>

Emit the build attributes that only depend on the hardware that we expect .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < XtensaSubtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool X86PassConfig :: addPreRegAlloc ( ) { addPass ( createX86MaxStackAlignmentHeuristicPass ( ) ) ; return false ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s>
unsigned
PPCTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
)
const
{
bool
isPPC64
=
PPCSubTarget
.
isPPC64
(
)
;
bool
isDarwinABI
=
PPCSubTarget
.
isDarwinABI
(
)
;
if
(
(
isPPC64
&&
VT
!=
MVT
::
i64
&&
VT
!=
MVT
::
i32
)
||
(
!
isPPC64
&&
VT
!=
MVT
::
i32
)
)
report_fatal_error
(
"Invalid register global variable type"
)
;
bool
is64Bit
=
isPPC64
&&
VT
==
MVT
::
i64
;
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"r1"
,
is64Bit
PPC
::
X1
:
PPC
::
R1
)
.
Case
(
"r2"
,
isDarwinABI
0
:
(
is64Bit
PPC
::
X2
:
PPC
::
R2
)
)
.
Case
(
"r13"
,
(
!
isPPC64
&&
isDarwinABI
)
0
:
(
is64Bit
PPC
::
X13
:
PPC
::
R13
)
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s>
void
output_compiler_stub
(
)
{
char
tmp_buf
[
256
]
;
char
label_buf
[
256
]
;
char
*
label
;
tree
tmp_stub
,
stub
;
if
(
!
flag_pic
)
for
(
stub
=
stub_list
;
stub
;
stub
=
TREE_CHAIN
(
stub
)
)
{
fprintf
(
asm_out_file
,
"%s:\n"
,
IDENTIFIER_POINTER
(
STUB_LABEL_NAME
(
stub
)
)
)
;
if
(
write_symbols
==
DBX_DEBUG
||
write_symbols
==
XCOFF_DEBUG
)
fprintf
(
asm_out_file
,
"\t.stabd 68,0,%d\n"
,
STUB_LINE_NUMBER
(
stub
)
)
;
if
(
IDENTIFIER_POINTER
(
STUB_FUNCTION_NAME
(
stub
)
)
[
0
]
==
'*'
)
strcpy
(
label_buf
,
IDENTIFIER_POINTER
(
STUB_FUNCTION_NAME
(
stub
)
)
+
1
)
;
else
{
label_buf
[
0
]
=
'_'
;
strcpy
(
label_buf
+
1
,
IDENTIFIER_POINTER
(
STUB_FUNCTION_NAME
(
stub
)
)
)
;
}
strcpy
(
tmp_buf
,
"lis r12,hi16("
)
;
strcat
(
tmp_buf
,
label_buf
)
;
strcat
(
tmp_buf
,
")\n\tori r12,r12,lo16("
)
;
strcat
(
tmp_buf
,
label_buf
)
;
strcat
(
tmp_buf
,
")\n\tmtctr r12\n\tbctr"
)
;
output_asm_insn
(
tmp_buf
,
0
)
;
if
(
write_symbols
==
DBX_DEBUG
||
write_symbols
==
XCOFF_DEBUG
)
fprintf
(
asm_out_file
,
"\t.stabd 68,0,%d\n"
,
STUB_LINE_NUMBER
(
stub
)
)
;
}
stub_list
=
0
;
}
</s>

OUTPUT_COMPILER_STUB outputs the compiler generated stub for handling procedure calls from the linked list and initializes the linked list .


<s> static rtx nvptx_get_unisimt_master ( ) { rtx & master = cfun -> machine -> unisimt_master ; return master ? master : master = gen_reg_rtx ( SImode ) ; } </s>

Return a SImode `` master lane index '' register for uniform-simt , allocating on first use .


<s> static section * pa_select_section ( tree exp , int reloc , unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED ) { if ( TREE_CODE ( exp ) == VAR_DECL && TREE_READONLY ( exp ) && ! TREE_THIS_VOLATILE ( exp ) && DECL_INITIAL ( exp ) && ( DECL_INITIAL ( exp ) == error_mark_node || TREE_CONSTANT ( DECL_INITIAL ( exp ) ) ) && ! ( reloc & pa_reloc_rw_mask ( ) ) ) { if ( TARGET_SOM && DECL_ONE_ONLY ( exp ) && ! DECL_WEAK ( exp ) ) return som_one_only_readonly_data_section ; else return readonly_data_section ; } else if ( CONSTANT_CLASS_P ( exp ) && ! ( reloc & pa_reloc_rw_mask ( ) ) ) return readonly_data_section ; else if ( TARGET_SOM && TREE_CODE ( exp ) == VAR_DECL && DECL_ONE_ONLY ( exp ) && ! DECL_WEAK ( exp ) ) return som_one_only_data_section ; else return data_section ; } </s>

On hpux10 , the linker will give an error if we have a reference in the read-only data section to a symbol defined in a shared library . Therefore , expressions that might require a reloc can not be placed in the read-only data section .


"TLCS900 DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> std :: pair < unsigned , const TargetRegisterClass * > PPCTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'b' : if ( VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RC_NOX0RegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRC_NOR0RegClass ) ; case 'r' : if ( VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RCRegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRCRegClass ) ; case 'f' : if ( VT == MVT :: f32 || VT == MVT :: i32 ) return std :: make_pair ( 0U , & PPC :: F4RCRegClass ) ; if ( VT == MVT :: f64 || VT == MVT :: i64 ) return std :: make_pair ( 0U , & PPC :: F8RCRegClass ) ; break ; case 'v' : return std :: make_pair ( 0U , & PPC :: VRRCRegClass ) ; case 'y' : return std :: make_pair ( 0U , & PPC :: CRRCRegClass ) ; } } else if ( Constraint == "wc" ) { return std :: make_pair ( 0U , & PPC :: CRBITRCRegClass ) ; } std :: pair < unsigned , const TargetRegisterClass * > R = TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; if ( R . first && VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) && PPC :: GPRCRegClass . contains ( R . first ) ) { const TargetRegisterInfo * TRI = getTargetMachine ( ) . getRegisterInfo ( ) ; return std :: make_pair ( TRI -> getMatchingSuperReg ( R . first , PPC :: sub_32 , & PPC :: G8RCRegClass ) , & PPC :: G8RCRegClass ) ; } return R ; } </s>

Given a physical register constraint ( e.g .


<s> virtual bool addPreRegAlloc ( ) { if ( getOptLevel ( ) == CodeGenOpt :: None ) { addPass ( & DeadMachineInstructionElimID ) ; } return true ; } </s>


<s> ARMELFStreamer & ARMTargetELFStreamer :: getStreamer ( ) { ARMELFStreamer * S = static_cast < ARMELFStreamer * > ( Streamer ) ; return * S ; } </s>

Return the output streamer for the assembler .


<s> RTX_CODE avr_normalize_condition ( RTX_CODE condition ) { switch ( condition ) { case GT : return GE ; case GTU : return GEU ; case LE : return LT ; case LEU : return LTU ; default : gcc_unreachable ( ) ; } } </s>

Convert condition code CONDITION to the valid AVR condition code


<s> const Cpu0TargetMachine & getTargetMachine ( ) { return static_cast < const Cpu0TargetMachine & > ( TM ) ; } </s>

Return the target machine ( if available ) .


"stack frame not a multiple of octabyte: %wd"

Expands the function epilogue into RTX .