<s> void mips_expand_vec_unpack ( rtx operands [ 2 ] , bool unsigned_p , bool high_p ) { machine_mode imode = GET_MODE ( operands [ 1 ] ) ; rtx ( * unpack ) ( rtx , rtx , rtx ) ; rtx ( * cmpFunc ) ( rtx , rtx , rtx ) ; rtx tmp , dest , zero ; if ( MSA_SUPPORTED_MODE_P ( imode ) ) { switch ( imode ) { case E_V4SImode : if ( BYTES_BIG_ENDIAN != high_p ) unpack = gen_msa_ilvl_w ; else unpack = gen_msa_ilvr_w ; cmpFunc = gen_msa_clt_s_w ; break ; case E_V8HImode : if ( BYTES_BIG_ENDIAN != high_p ) unpack = gen_msa_ilvl_h ; else unpack = gen_msa_ilvr_h ; cmpFunc = gen_msa_clt_s_h ; break ; case E_V16QImode : if ( BYTES_BIG_ENDIAN != high_p ) unpack = gen_msa_ilvl_b ; else unpack = gen_msa_ilvr_b ; cmpFunc = gen_msa_clt_s_b ; break ; default : gcc_unreachable ( ) ; break ; } if ( ! unsigned_p ) { tmp = gen_reg_rtx ( imode ) ; emit_insn ( cmpFunc ( tmp , operands [ 1 ] , CONST0_RTX ( imode ) ) ) ; } else tmp = force_reg ( imode , CONST0_RTX ( imode ) ) ; dest = gen_reg_rtx ( imode ) ; emit_insn ( unpack ( dest , operands [ 1 ] , tmp ) ) ; emit_move_insn ( operands [ 0 ] , gen_lowpart ( GET_MODE ( operands [ 0 ] ) , dest ) ) ; return ; } switch ( imode ) { case E_V8QImode : if ( high_p ) unpack = gen_loongson_punpckhbh ; else unpack = gen_loongson_punpcklbh ; cmpFunc = gen_loongson_pcmpgtb ; break ; case E_V4HImode : if ( high_p ) unpack = gen_loongson_punpckhhw ; else unpack = gen_loongson_punpcklhw ; cmpFunc = gen_loongson_pcmpgth ; break ; default : gcc_unreachable ( ) ; } zero = force_reg ( imode , CONST0_RTX ( imode ) ) ; if ( unsigned_p ) tmp = zero ; else { tmp = gen_reg_rtx ( imode ) ; emit_insn ( cmpFunc ( tmp , zero , operands [ 1 ] ) ) ; } dest = gen_reg_rtx ( imode ) ; emit_insn ( unpack ( dest , operands [ 1 ] , tmp ) ) ; emit_move_insn ( operands [ 0 ] , gen_lowpart ( GET_MODE ( operands [ 0 ] ) , dest ) ) ; } </s>

Expand an integral vector unpack operation .


<s> unsigned AMDGPUAsmParser :: checkTargetMatchPredicate ( MCInst & Inst ) { uint64_t TSFlags = MII . get ( Inst . getOpcode ( ) ) . TSFlags ; if ( ( getForcedEncodingSize ( ) == 32 && ( TSFlags & SIInstrFlags :: VOP3 ) ) || ( getForcedEncodingSize ( ) == 64 && ! ( TSFlags & SIInstrFlags :: VOP3 ) ) ) return Match_InvalidOperand ; return Match_Success ; } </s>

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


<s> static unsigned int spu_section_type_flags ( tree decl , const char * name , int reloc ) { if ( strcmp ( name , ".toe" ) == 0 ) return SECTION_BSS ; if ( strcmp ( name , "._ea" ) == 0 ) return SECTION_WRITE | SECTION_DEBUG ; return default_section_type_flags ( decl , name , reloc ) ; } </s>


<s> const MCPhysReg * PPCRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const PPCSubtarget & Subtarget = MF -> getSubtarget < PPCSubtarget > ( ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: AnyReg ) { if ( Subtarget . hasVSX ( ) ) return CSR_64_AllRegs_VSX_SaveList ; if ( Subtarget . hasAltivec ( ) ) return CSR_64_AllRegs_Altivec_SaveList ; return CSR_64_AllRegs_SaveList ; } if ( Subtarget . isDarwinABI ( ) ) return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_SaveList : CSR_Darwin64_SaveList ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_SaveList : CSR_Darwin32_SaveList ) ; if ( TM . isPPC64 ( ) && MF -> getInfo < PPCFunctionInfo > ( ) -> isSplitCSR ( ) ) return CSR_SRV464_TLS_PE_SaveList ; if ( Subtarget . hasSPE ( ) ) return CSR_SVR432_SPE_SaveList ; bool SaveR2 = MF -> getRegInfo ( ) . isAllocatable ( PPC :: X2 ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: Cold ) { return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? ( SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList : CSR_SVR64_ColdCC_Altivec_SaveList ) : ( SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList : CSR_SVR64_ColdCC_SaveList ) ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR32_ColdCC_Altivec_SaveList : CSR_SVR32_ColdCC_SaveList ) ; } return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? ( SaveR2 ? CSR_SVR464_R2_Altivec_SaveList : CSR_SVR464_Altivec_SaveList ) : ( SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList ) ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR432_Altivec_SaveList : CSR_SVR432_SaveList ) ; } </s>

PowerPC PPC PPC PPC PPC PPC PPC PPC::X2 PPC PPC


"internal error: builtin function %s already processed"

Add a SPARC builtin function with NAME , ICODE , CODE and TYPE . Return the function decl or NULL_TREE if the builtin was not added .


<s> unsigned MipsTargetLowering :: getJumpTableEncoding ( ) const { if ( ABI . IsN64 ( ) && isPositionIndependent ( ) ) return MachineJumpTableInfo :: EK_GPRel64BlockAddress ; return TargetLowering :: getJumpTableEncoding ( ) ; } </s>

Return the entry encoding for a jump table in the current function .


<s>
void
RV16KDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
if
(
Node
->
getOpcode
(
)
==
ISD
::
FrameIndex
)
{
int
FI
=
cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
MVT
::
i16
)
;
CurDAG
->
SelectNodeTo
(
Node
,
RV16K
::
FRMIDX
,
MVT
::
i16
,
TFI
,
CurDAG
->
getTargetConstant
(
0
,
SDLoc
(
Node
)
,
MVT
::
i16
)
)
;
return
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


"RegScavenger required for long branching"

"new block should be inserted for expanding unconditional branch"

"Branch offsets outside of the signed 32-bit range not supported"

Insert an unconditional indirect branch at the end of MBB to NewDestBB .


<s> Align PPCTargetLowering :: getPrefLoopAlignment ( MachineLoop * ML ) const { switch ( Subtarget . getCPUDirective ( ) ) { default : break ; case PPC :: DIR_970 : case PPC :: DIR_PWR4 : case PPC :: DIR_PWR5 : case PPC :: DIR_PWR5X : case PPC :: DIR_PWR6 : case PPC :: DIR_PWR6X : case PPC :: DIR_PWR7 : case PPC :: DIR_PWR8 : case PPC :: DIR_PWR9 : case PPC :: DIR_PWR_FUTURE : { if ( ! ML ) break ; if ( ! DisableInnermostLoopAlign32 ) { if ( ML -> getLoopDepth ( ) > 1 && ML -> getSubLoops ( ) . empty ( ) ) return Align ( 32 ) ; } const PPCInstrInfo * TII = Subtarget . getInstrInfo ( ) ; uint64_t LoopSize = 0 ; for ( auto I = ML -> block_begin ( ) , IE = ML -> block_end ( ) ; I != IE ; ++ I ) for ( auto J = ( * I ) -> begin ( ) , JE = ( * I ) -> end ( ) ; J != JE ; ++ J ) { LoopSize += TII -> getInstSizeInBytes ( * J ) ; if ( LoopSize > 32 ) break ; } if ( LoopSize > 16 && LoopSize <= 32 ) return Align ( 32 ) ; break ; } } return TargetLowering :: getPrefLoopAlignment ( ML ) ; } </s>


<s> AMDGPUSubtarget & AMDGPUSubtarget :: initializeSubtargetDependencies ( const Triple & TT , StringRef GPU , StringRef FS ) { SmallString < 256 > FullFS ( "+promote-alloca,+fp64-denormals," ) ; if ( isAmdHsaOS ( ) ) FullFS += "+flat-for-global," ; FullFS += FS ; if ( GPU == "" && TT . getArch ( ) == Triple :: amdgcn ) GPU = "SI" ; ParseSubtargetFeatures ( GPU , FullFS ) ; if ( getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) { FP32Denormals = false ; FP64Denormals = false ; } return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .

AMDGPU AMDGPU AMDGPU 256 "+promote-alloca,+fp64-denormals," "+flat-for-global," "" "SI" AMDGPU


<s> static bool loongarch_in_small_data_p ( const_tree decl ) { int size ; if ( TREE_CODE ( decl ) == STRING_CST || TREE_CODE ( decl ) == FUNCTION_DECL ) return false ; if ( VAR_P ( decl ) && DECL_SECTION_NAME ( decl ) != 0 ) { const char * name ; name = DECL_SECTION_NAME ( decl ) ; if ( strcmp ( name , ".sdata" ) != 0 && strcmp ( name , ".sbss" ) != 0 ) return false ; if ( ! DECL_EXTERNAL ( decl ) ) return true ; } size = int_size_in_bytes ( TREE_TYPE ( decl ) ) ; return size > 0 && size <= g_switch_value ; } </s>


<s>
SDValue
PPCTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCRetInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCRetInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_PPC
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Val
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
,
InFlag
)
;
Chain
=
Val
.
getValue
(
1
)
;
InFlag
=
Val
.
getValue
(
2
)
;
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
AExt
:
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
ZExt
:
Val
=
DAG
.
getNode
(
ISD
::
AssertZext
,
dl
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
SExt
:
Val
=
DAG
.
getNode
(
ISD
::
AssertSext
,
dl
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
}
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .

PowerPC
PPC
ISD::InputArg
16
PPC
0
"Can only return in registers!"
1
2
"Unknown loc info!"
ISD::TRUNCATE
ISD::AssertZext
ISD::TRUNCATE
ISD::AssertSext
ISD::TRUNCATE


<s> static FRV_INLINE int frv_regno_ok_for_base_p ( int regno , int strict_p ) { if ( GPR_P ( regno ) ) return TRUE ; if ( strict_p ) return ( reg_renumber [ regno ] >= 0 && GPR_P ( reg_renumber [ regno ] ) ) ; if ( regno == ARG_POINTER_REGNUM ) return TRUE ; return ( regno >= FIRST_PSEUDO_REGISTER ) ; } </s>

Return true if a register is ok to use as a base or index register .


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { const X86TargetMachine * TM = static_cast < const X86TargetMachine * > ( & MF . getTarget ( ) ) ; const X86RegisterInfo * X86RI = TM -> getRegisterInfo ( ) ; MachineRegisterInfo & RI = MF . getRegInfo ( ) ; X86MachineFunctionInfo * FuncInfo = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned StackAlignment = X86RI -> getStackAlignment ( ) ; for ( unsigned i = 0 , e = RI . getNumVirtRegs ( ) ; i != e ; ++ i ) { unsigned Reg = TargetRegisterInfo :: index2VirtReg ( i ) ; if ( RI . getRegClass ( Reg ) -> getAlignment ( ) > StackAlignment ) { FuncInfo -> setReserveFP ( true ) ; return true ; } } return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> void expand_fusion_p9_load ( rtx * operands ) { rtx tmp_reg = operands [ 0 ] ; rtx addis_value = operands [ 1 ] ; rtx target = operands [ 2 ] ; rtx orig_mem = operands [ 3 ] ; rtx new_addr , new_mem , orig_addr , offset , set , clobber , insn ; enum rtx_code plus_or_lo_sum ; machine_mode target_mode = GET_MODE ( target ) ; machine_mode extend_mode = target_mode ; machine_mode ptr_mode = Pmode ; enum rtx_code extend = UNKNOWN ; if ( GET_CODE ( orig_mem ) == FLOAT_EXTEND || GET_CODE ( orig_mem ) == ZERO_EXTEND ) { extend = GET_CODE ( orig_mem ) ; orig_mem = XEXP ( orig_mem , 0 ) ; target_mode = GET_MODE ( orig_mem ) ; } gcc_assert ( MEM_P ( orig_mem ) ) ; orig_addr = XEXP ( orig_mem , 0 ) ; plus_or_lo_sum = GET_CODE ( orig_addr ) ; gcc_assert ( plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM ) ; offset = XEXP ( orig_addr , 1 ) ; new_addr = gen_rtx_fmt_ee ( plus_or_lo_sum , ptr_mode , addis_value , offset ) ; new_mem = replace_equiv_address_nv ( orig_mem , new_addr , false ) ; if ( extend != UNKNOWN ) new_mem = gen_rtx_fmt_e ( extend , extend_mode , new_mem ) ; new_mem = gen_rtx_UNSPEC ( extend_mode , gen_rtvec ( 1 , new_mem ) , UNSPEC_FUSION_P9 ) ; set = gen_rtx_SET ( target , new_mem ) ; clobber = gen_rtx_CLOBBER ( VOIDmode , tmp_reg ) ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set , clobber ) ) ; emit_insn ( insn ) ; return ; } </s>

During the peephole2 pass , adjust and expand the insns for an extended fusion load sequence . The operands are : operands [ 0 ] register set with addis operands [ 1 ] value set via addis operands [ 2 ] target register being loaded operands [ 3 ] D-form memory reference using operands [ 0 ] . This is similar to the fusion introduced with power8 , except it scales to both loads/stores and does not require the result register to be the same as the base register . At the moment , we only do this if register set with addis is dead .


<s> bool PPCTargetLowering :: isFMAFasterThanFMulAndFAdd ( const Function & F , Type * Ty ) const { switch ( Ty -> getScalarType ( ) -> getTypeID ( ) ) { case Type :: FloatTyID : case Type :: DoubleTyID : return true ; case Type :: FP128TyID : return Subtarget . hasP9Vector ( ) ; default : return false ; } } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> bool X86FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const X86RegisterInfo * RegInfo = static_cast < const X86RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; unsigned SlotSize = RegInfo -> getSlotSize ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned CalleeSavedFrameSize = 0 ; int SpillSlotOffset = getOffsetOfLocalArea ( ) + X86FI -> getTCReturnAddrDelta ( ) ; if ( MF . protectReturnPtr ( ) && ! MF . getName ( ) . equals ( "main" ) ) { SpillSlotOffset -= SlotSize ; MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; } if ( hasFP ( MF ) ) { SpillSlotOffset -= SlotSize ; MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; if ( MF . protectFramePtr ( ) ) { SpillSlotOffset -= SlotSize ; MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; } unsigned FPReg = RegInfo -> getFrameRegister ( MF ) ; for ( unsigned i = 0 ; i < CSI . size ( ) ; ++ i ) { if ( CSI [ i ] . getReg ( ) == FPReg ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } } bool hasGPR = false ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; hasGPR = true ; SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - 1 ] . setFrameIdx ( SlotIndex ) ; } if ( MF . protectCSRs ( ) && hasGPR ) { SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; } X86FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = RegInfo -> getMinimalPhysRegClass ( Reg ) ; SpillSlotOffset -= abs ( SpillSlotOffset ) % RC -> getAlignment ( ) ; SpillSlotOffset -= RC -> getSize ( ) ; int SlotIndex = MFI -> CreateFixedSpillStackObject ( RC -> getSize ( ) , SpillSlotOffset ) ; CSI [ i - 1 ] . setFrameIdx ( SlotIndex ) ; MFI -> ensureMaxAlignment ( RC -> getAlignment ( ) ) ; } return true ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> static int eligible_for_restore_insn ( rtx trial , bool return_p ) { rtx pat = PATTERN ( trial ) ; rtx src = SET_SRC ( pat ) ; if ( GET_MODE_CLASS ( GET_MODE ( src ) ) != MODE_FLOAT && arith_operand ( src , GET_MODE ( src ) ) ) { if ( TARGET_ARCH64 ) return GET_MODE_SIZE ( GET_MODE ( src ) ) <= GET_MODE_SIZE ( DImode ) ; else return GET_MODE_SIZE ( GET_MODE ( src ) ) <= GET_MODE_SIZE ( SImode ) ; } else if ( GET_MODE_CLASS ( GET_MODE ( src ) ) != MODE_FLOAT && arith_double_operand ( src , GET_MODE ( src ) ) ) return GET_MODE_SIZE ( GET_MODE ( src ) ) <= GET_MODE_SIZE ( DImode ) ; else if ( ! TARGET_FPU && register_operand ( src , SFmode ) ) return 1 ; else if ( ! TARGET_FPU && TARGET_ARCH64 && register_operand ( src , DFmode ) ) return 1 ; else if ( return_p && TARGET_V9 && ! epilogue_renumber ( & pat , 1 ) && ( get_attr_in_uncond_branch_delay ( trial ) == IN_UNCOND_BRANCH_DELAY_TRUE ) ) return 1 ; else if ( GET_CODE ( src ) == PLUS && register_operand ( XEXP ( src , 0 ) , SImode ) && arith_operand ( XEXP ( src , 1 ) , SImode ) ) return 1 ; else if ( GET_CODE ( src ) == PLUS && register_operand ( XEXP ( src , 0 ) , DImode ) && arith_double_operand ( XEXP ( src , 1 ) , DImode ) ) return 1 ; else if ( GET_CODE ( src ) == LO_SUM && ! TARGET_CM_MEDMID && ( ( register_operand ( XEXP ( src , 0 ) , SImode ) && immediate_operand ( XEXP ( src , 1 ) , SImode ) ) || ( TARGET_ARCH64 && register_operand ( XEXP ( src , 0 ) , DImode ) && immediate_operand ( XEXP ( src , 1 ) , DImode ) ) ) ) return 1 ; else if ( GET_CODE ( src ) == ASHIFT && ( register_operand ( XEXP ( src , 0 ) , SImode ) || register_operand ( XEXP ( src , 0 ) , DImode ) ) && XEXP ( src , 1 ) == const1_rtx ) return 1 ; return 0 ; } </s>

Return nonzero if TRIAL , an insn , can be combined with a 'restore ' instruction . RETURN_P is true if the v9 variant 'return ' is to be considered in the test too . TRIAL must be a SET whose destination is a REG appropriate for the 'restore ' instruction or , if RETURN_P is true , for the 'return ' instruction .


<s> static bool rs6000_hard_regno_call_part_clobbered ( unsigned int regno , machine_mode mode ) { if ( TARGET_32BIT && TARGET_POWERPC64 && GET_MODE_SIZE ( mode ) > 4 && INT_REGNO_P ( regno ) ) return true ; if ( TARGET_VSX && FP_REGNO_P ( regno ) && GET_MODE_SIZE ( mode ) > 8 && ! FLOAT128_2REG_P ( mode ) ) return true ; return false ; } </s>


<s> unsigned SIInstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL , int * BytesAdded ) const { if ( ! FBB && Cond . empty ( ) ) { BuildMI ( & MBB , DL , get ( AMDGPU :: S_BRANCH ) ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded = ST . hasOffset3fBug ( ) ? 8 : 4 ; return 1 ; } if ( Cond . size ( ) == 1 && Cond [ 0 ] . isReg ( ) ) { BuildMI ( & MBB , DL , get ( AMDGPU :: SI_NON_UNIFORM_BRCOND_PSEUDO ) ) . add ( Cond [ 0 ] ) . addMBB ( TBB ) ; return 1 ; } assert ( TBB && Cond [ 0 ] . isImm ( ) ) ; unsigned Opcode = getBranchOpcode ( static_cast < BranchPredicate > ( Cond [ 0 ] . getImm ( ) ) ) ; if ( ! FBB ) { Cond [ 1 ] . isUndef ( ) ; MachineInstr * CondBr = BuildMI ( & MBB , DL , get ( Opcode ) ) . addMBB ( TBB ) ; preserveCondRegFlags ( CondBr -> getOperand ( 1 ) , Cond [ 1 ] ) ; fixImplicitOperands ( * CondBr ) ; if ( BytesAdded ) * BytesAdded = ST . hasOffset3fBug ( ) ? 8 : 4 ; return 1 ; } assert ( TBB && FBB ) ; MachineInstr * CondBr = BuildMI ( & MBB , DL , get ( Opcode ) ) . addMBB ( TBB ) ; fixImplicitOperands ( * CondBr ) ; BuildMI ( & MBB , DL , get ( AMDGPU :: S_BRANCH ) ) . addMBB ( FBB ) ; MachineOperand & CondReg = CondBr -> getOperand ( 1 ) ; CondReg . setIsUndef ( Cond [ 1 ] . isUndef ( ) ) ; CondReg . setIsKill ( Cond [ 1 ] . isKill ( ) ) ; if ( BytesAdded ) * BytesAdded = ST . hasOffset3fBug ( ) ? 16 : 8 ; return 2 ; } </s>

Insert branch code into the end of the specified MachineBasicBlock .


<s> const Z80Subtarget * Z80TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < 512 > Key ; Key . reserve ( CPU . size ( ) + FS . size ( ) ) ; Key += CPU ; Key += FS ; bool SoftFloat = true ; if ( SoftFloat ) { Key += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; } unsigned CPUFSWidth = Key . size ( ) ; FS = Key . slice ( CPU . size ( ) , CPUFSWidth ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < Z80Subtarget > ( TargetTriple , CPU , FS , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static bool expand_vec_perm_vperm2f128_vblend ( struct expand_vec_perm_d * d ) { struct expand_vec_perm_d dfirst , dsecond ; unsigned i , j , msk , nelt = d -> nelt , nelt2 = nelt / 2 ; rtx_insn * seq ; bool ok ; rtx ( * blend ) ( rtx , rtx , rtx , rtx ) = NULL ; if ( ! TARGET_AVX || TARGET_AVX2 || ( d -> vmode != V8SFmode && d -> vmode != V4DFmode ) || ! d -> one_operand_p ) return false ; dfirst = * d ; for ( i = 0 ; i < nelt ; i ++ ) dfirst . perm [ i ] = 0xff ; for ( i = 0 , msk = 0 ; i < nelt ; i ++ ) { j = ( d -> perm [ i ] & nelt2 ) ? i | nelt2 : i & ~ nelt2 ; if ( dfirst . perm [ j ] != 0xff && dfirst . perm [ j ] != d -> perm [ i ] ) return false ; dfirst . perm [ j ] = d -> perm [ i ] ; if ( j != i ) msk |= ( 1 << i ) ; } for ( i = 0 ; i < nelt ; i ++ ) if ( dfirst . perm [ i ] == 0xff ) dfirst . perm [ i ] = i ; if ( ! d -> testing_p ) dfirst . target = gen_reg_rtx ( dfirst . vmode ) ; start_sequence ( ) ; ok = expand_vec_perm_1 ( & dfirst ) ; seq = get_insns ( ) ; end_sequence ( ) ; if ( ! ok ) return false ; if ( d -> testing_p ) return true ; emit_insn ( seq ) ; dsecond = * d ; dsecond . op0 = dfirst . target ; dsecond . op1 = dfirst . target ; dsecond . one_operand_p = true ; dsecond . target = gen_reg_rtx ( dsecond . vmode ) ; for ( i = 0 ; i < nelt ; i ++ ) dsecond . perm [ i ] = i ^ nelt2 ; ok = expand_vec_perm_1 ( & dsecond ) ; gcc_assert ( ok ) ; blend = d -> vmode == V8SFmode ? gen_avx_blendps256 : gen_avx_blendpd256 ; emit_insn ( blend ( d -> target , dfirst . target , dsecond . target , GEN_INT ( msk ) ) ) ; return true ; } </s>

A subroutine of ix86_expand_vec_perm_builtin_1 . Try to implement a single vector permutation using a single intra-lane vector permutation , vperm2f128 swapping the lanes and vblend * insn blending the non-swapped and swapped vectors together .


<s> void mcore_print_operand ( FILE * stream , rtx x , int code ) { switch ( code ) { case 'N' : if ( INTVAL ( x ) == - 1 ) fprintf ( asm_out_file , "32" ) ; else fprintf ( asm_out_file , "%d" , exact_log2 ( INTVAL ( x ) + 1 ) ) ; break ; case 'P' : fprintf ( asm_out_file , "%d" , exact_log2 ( INTVAL ( x ) ) ) ; break ; case 'Q' : fprintf ( asm_out_file , "%d" , exact_log2 ( ~ INTVAL ( x ) ) ) ; break ; case 'O' : fprintf ( asm_out_file , HOST_WIDE_INT_PRINT_DEC , INTVAL ( x ) ) ; break ; case 'M' : fprintf ( asm_out_file , HOST_WIDE_INT_PRINT_DEC , - INTVAL ( x ) ) ; break ; case 'R' : switch ( GET_CODE ( x ) ) { case REG : fputs ( reg_names [ REGNO ( x ) + 1 ] , ( stream ) ) ; break ; case MEM : mcore_print_operand_address ( stream , XEXP ( adjust_address ( x , SImode , 4 ) , 0 ) ) ; break ; default : gcc_unreachable ( ) ; } break ; case 'U' : fprintf ( asm_out_file , "%s-%s" , reg_names [ REGNO ( x ) ] , reg_names [ REGNO ( x ) + 3 ] ) ; break ; case 'x' : fprintf ( asm_out_file , HOST_WIDE_INT_PRINT_HEX , INTVAL ( x ) ) ; break ; case 'X' : fprintf ( asm_out_file , HOST_WIDE_INT_PRINT_DEC , 3 - INTVAL ( x ) / 8 ) ; break ; default : switch ( GET_CODE ( x ) ) { case REG : fputs ( reg_names [ REGNO ( x ) ] , ( stream ) ) ; break ; case MEM : output_address ( XEXP ( x , 0 ) ) ; break ; default : output_addr_const ( stream , x ) ; break ; } break ; } } </s>

Print operand x ( an rtx ) in assembler syntax to file stream according to modifier code . ' R ' print the next register or memory location along , ie the lsw in a double word value ' O ' print a constant without the # 'M ' print a constant as its negative ' P ' print log2 of a power of two ' Q ' print log2 of an inverse of a power of two ' U ' print register for ldm/stm instruction ' X ' print byte number for xtrbN instruction .


<s> inline rtx function_expander :: expand ( ) { return base -> expand ( * this ) ; } </s>


"********** AArch64 Conditional Compares **********\n"


<s>
CCAssignFn
*
ARMFastISel
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
Return
,
bool
isVarArg
)
{
switch
(
CC
)
{
default
:
report_fatal_error
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
if
(
Subtarget
->
hasVFP2Base
(
)
&&
!
isVarArg
)
{
if
(
!
Subtarget
->
isAAPCS_ABI
(
)
)
return
(
Return
RetFastCC_ARM_APCS
:
FastCC_ARM_APCS
)
;
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
}
LLVM_FALLTHROUGH
;
case
CallingConv
::
C
:
case
CallingConv
::
CXX_FAST_TLS
:
if
(
Subtarget
->
isAAPCS_ABI
(
)
)
{
if
(
Subtarget
->
hasVFP2Base
(
)
&&
TM
.
Options
.
FloatABIType
==
FloatABI
::
Hard
&&
!
isVarArg
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
else
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
}
else
{
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
}
case
CallingConv
::
ARM_AAPCS_VFP
:
case
CallingConv
::
Swift
:
case
CallingConv
::
SwiftTail
:
if
(
!
isVarArg
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
LLVM_FALLTHROUGH
;
case
CallingConv
::
ARM_AAPCS
:
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
case
CallingConv
::
ARM_APCS
:
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
case
CallingConv
::
GHC
:
if
(
Return
)
report_fatal_error
(
"Can't return in GHC call convention"
)
;
else
return
CC_ARM_APCS_GHC
;
case
CallingConv
::
CFGuard_Check
:
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_Win32_CFGuard_Check
)
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .

ARM
ARM
"Unsupported calling convention"
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
"Can't return in GHC call convention"
ARM
ARM
ARM


"SVE type %qT does not have a fixed size"

"SVE type %qT does not have a defined alignment"

"variables of type %qT cannot have thread-local"

"member variables cannot have SVE type %qT"

"array elements cannot have SVE type %qT"

"cannot allocate objects with SVE type %qT"

"cannot delete objects with SVE type %qT"

Implement TARGET_VERIFY_TYPE_CONTEXT for RVV types .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
Kind
==
k_Register
&&
"Invalid access!"
)
;
return
Reg
.
Num
;
}
</s>

Returns the register associated with this edge .


<s> void CAHPFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const CAHPRegisterInfo * RI = STI . getRegisterInfo ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; uint64_t StackAlign = RI -> needsStackRealignment ( MF ) ? MFI . getMaxAlignment ( ) : getStackAlignment ( ) ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI . setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s> static SDValue getTargetNode ( JumpTableSDNode * N , SDLoc DL , EVT Ty , SelectionDAG & DAG , unsigned Flags ) { return DAG . getTargetJumpTable ( N -> getIndex ( ) , Ty , Flags ) ; } </s>

Retrieve the target node this edge connects to .


<s> static void emitSPUpdate ( bool isARM , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , const ARMBaseInstrInfo & TII , int NumBytes , unsigned MIFlags = MachineInstr :: NoFlags ) { if ( isARM ) emitARMRegPlusImmediate ( MBB , MBBI , dl , ARM :: SP , ARM :: SP , NumBytes , ARMCC :: AL , 0 , TII , MIFlags ) ; else emitT2RegPlusImmediate ( MBB , MBBI , dl , ARM :: SP , ARM :: SP , NumBytes , ARMCC :: AL , 0 , TII , MIFlags ) ; } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .

ARM ARM ARM ARM ARM ARM::SP ARM::SP ARMCC::AL 0 ARM::SP ARM::SP ARMCC::AL 0


<s> void XCoreFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; XCoreFunctionInfo * XFI = MF . getInfo < XCoreFunctionInfo > ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool LRUsed = MRI . isPhysRegModified ( XCore :: LR ) ; if ( ! LRUsed && ! MF . getFunction ( ) -> isVarArg ( ) && MF . getFrameInfo ( ) . estimateStackSize ( MF ) ) LRUsed = true ; if ( MF . callsUnwindInit ( ) || MF . callsEHReturn ( ) ) { XFI -> createEHSpillSlot ( MF ) ; LRUsed = true ; } if ( LRUsed ) { SavedRegs . reset ( XCore :: LR ) ; XFI -> createLRSpillSlot ( MF ) ; } if ( hasFP ( MF ) ) XFI -> createFPSpillSlot ( MF ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .

XCore XCore XCore XCore XCore::LR XCore::LR


<s> bool HexagonTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { EVT VT ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; if ( ST -> getValue ( ) . getValueType ( ) == MVT :: i64 && ST -> isTruncatingStore ( ) ) return false ; } else { return false ; } bool IsInc = false ; bool isLegal = getIndexedAddressParts ( Op , VT , Base , Offset , IsInc , DAG ) ; if ( isLegal ) { auto & HII = * Subtarget . getInstrInfo ( ) ; int32_t OffsetVal = cast < ConstantSDNode > ( Offset . getNode ( ) ) -> getSExtValue ( ) ; if ( HII . isValidAutoIncImm ( VT , OffsetVal ) ) { AM = IsInc ? ISD :: POST_INC : ISD :: POST_DEC ; return true ; } } return false ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .


<s> const char * rs6000_xcoff_strip_dollar ( const char * name ) { char * strip , * p ; const char * q ; size_t len ; q = ( const char * ) strchr ( name , '$' ) ; if ( q == 0 || q == name ) return name ; len = strlen ( name ) ; strip = XALLOCAVEC ( char , len + 1 ) ; strcpy ( strip , name ) ; p = strip + ( q - name ) ; while ( p ) { * p = '_' ; p = strchr ( p + 1 , '$' ) ; } return ggc_alloc_string ( strip , len ) ; } </s>

Return a GGC-allocated character string translating dollar signs in input NAME to underscores . Used by XCOFF ASM_OUTPUT_LABELREF .


"Don't know how to custom type legalize this operation!"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s>
static
void
handle_special_swappables
(
swap_web_entry
*
insn_entry
,
unsigned
i
)
{
rtx_insn
*
insn
=
insn_entry
[
i
]
.
insn
;
rtx
body
=
PATTERN
(
insn
)
;
switch
(
insn_entry
[
i
]
.
special_handling
)
{
default
:
gcc_unreachable
(
)
;
case
SH_CONST_VECTOR
:
{
gcc_assert
(
GET_CODE
(
body
)
==
SET
)
;
swap_const_vector_halves
(
&
SET_SRC
(
body
)
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Swapping constant halves in insn %d\n"
,
i
)
;
break
;
}
case
SH_SUBREG
:
adjust_subreg_index
(
body
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Adjusting subreg in insn %d\n"
,
i
)
;
break
;
case
SH_NOSWAP_LD
:
permute_load
(
insn
)
;
break
;
case
SH_NOSWAP_ST
:
permute_store
(
insn
)
;
break
;
case
SH_EXTRACT
:
adjust_extract
(
insn
)
;
break
;
case
SH_SPLAT
:
adjust_splat
(
insn
)
;
break
;
case
SH_XXPERMDI
:
adjust_xxpermdi
(
insn
)
;
break
;
case
SH_CONCAT
:
adjust_concat
(
insn
)
;
break
;
case
SH_VPERM
:
adjust_vperm
(
insn
)
;
break
;
}
}
</s>

The insn described by INSN_ENTRY [ I ] can be swapped , but only with special handling . Take care of that here .

powerpcspe
"Swapping constant halves in insn %d\n"
"Adjusting subreg in insn %d\n"


<s>
const
char
*
SICAsmPrinter
::
getCurrentABIString
(
)
const
{
switch
(
static_cast
<
SICTargetMachine
&
>
(
TM
)
.
getABI
(
)
.
GetEnumValue
(
)
)
{
case
SICABIInfo
::
ABI
::
O32
:
return
"abiO32"
;
case
SICABIInfo
::
ABI
::
S32
:
return
"abiS32"
;
default
:
llvm_unreachable
(
"Unknown SIC ABI"
)
;
}
}
</s>


<s> bool MCS51MCExpr :: evaluateAsConstant ( int64_t & Result ) const { MCValue Value ; bool isRelocatable = getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ; if ( ! isRelocatable ) return false ; if ( Value . isAbsolute ( ) ) { Result = evaluateAsInt64 ( Value . getConstant ( ) ) ; return true ; } return false ; } </s>

Evaluates the fixup as a constant value .


<s> void DLXFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const DLXRegisterInfo * LRI = STI . getRegisterInfo ( ) ; unsigned FrameSize = MFI . getStackSize ( ) ; unsigned StackAlign = LRI -> needsStackRealignment ( MF ) ? MFI . getMaxAlignment ( ) : getStackAlignment ( ) ; unsigned MaxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; if ( MFI . hasVarSizedObjects ( ) ) MaxCallFrameSize = alignTo ( MaxCallFrameSize , StackAlign ) ; MFI . setMaxCallFrameSize ( MaxCallFrameSize ) ; if ( ! ( hasReservedCallFrame ( MF ) && MFI . adjustsStack ( ) ) ) FrameSize += MaxCallFrameSize ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI . setStackSize ( FrameSize ) ; } </s>


<s> void ia64_vms_output_aligned_decl_common ( FILE * file , tree decl , const char * name , unsigned HOST_WIDE_INT size , unsigned int align ) { tree attr = DECL_ATTRIBUTES ( decl ) ; if ( attr ) attr = lookup_attribute ( "common_object" , attr ) ; if ( attr ) { tree id = TREE_VALUE ( TREE_VALUE ( attr ) ) ; const char * name ; if ( TREE_CODE ( id ) == IDENTIFIER_NODE ) name = IDENTIFIER_POINTER ( id ) ; else if ( TREE_CODE ( id ) == STRING_CST ) name = TREE_STRING_POINTER ( id ) ; else abort ( ) ; fprintf ( file , "\t.vms_common\t\"%s\"," , name ) ; } else fprintf ( file , "%s" , COMMON_ASM_OP ) ; assemble_name ( file , name ) ; fprintf ( file , "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u" , size , align / BITS_PER_UNIT ) ; fputc ( '\n' , file ) ; } </s>

Part of the low level implementation of DEC Ada pragma Common_Object .


<s> bool PPCRegisterInfo :: isCallerPreservedPhysReg ( MCRegister PhysReg , const MachineFunction & MF ) const { assert ( Register :: isPhysicalRegister ( PhysReg ) ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! TM . isPPC64 ( ) ) return false ; if ( ! Subtarget . isSVR4ABI ( ) ) return false ; if ( PhysReg == PPC :: X2 ) return ( getReservedRegs ( MF ) . test ( PPC :: X2 ) ) ; if ( StackPtrConst && ( PhysReg == PPC :: X1 ) && ! MFI . hasVarSizedObjects ( ) && ! MFI . hasOpaqueSPAdjustment ( ) ) return true ; return false ; } </s>

Physical registers that may be modified within a function but are guaranteed to be restored before any uses .


<s> static bool bpf_legitimate_address_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x , bool strict ) { switch ( GET_CODE ( x ) ) { case REG : return bpf_address_base_p ( x , strict ) ; case PLUS : { rtx x0 = XEXP ( x , 0 ) ; rtx x1 = XEXP ( x , 1 ) ; if ( bpf_address_base_p ( x0 , strict ) && GET_CODE ( x1 ) == CONST_INT ) return IN_RANGE ( INTVAL ( x1 ) , - 1 - 0x7fff , 0x7fff ) ; break ; } default : break ; } return false ; } </s>

Return true if X ( a RTX ) is a legitimate memory address on the target machine for a memory operand of mode MODE .


"Can only put epilog before 'retl' instruction!"


<s>
static
void
recombine_stvx_pattern
(
rtx_insn
*
insn
,
del_info
*
to_delete
)
{
rtx
body
=
PATTERN
(
insn
)
;
gcc_assert
(
GET_CODE
(
body
)
==
SET
&&
GET_CODE
(
SET_DEST
(
body
)
)
==
MEM
&&
GET_CODE
(
SET_SRC
(
body
)
)
==
VEC_SELECT
)
;
rtx
mem
=
SET_DEST
(
body
)
;
rtx
base_reg
=
XEXP
(
mem
,
0
)
;
rtx
and_operation
=
find_alignment_op
(
insn
,
base_reg
)
;
if
(
and_operation
!=
0
)
{
rtx
src_reg
=
XEXP
(
SET_SRC
(
body
)
,
0
)
;
df_ref
src_use
;
struct
df_insn_info
*
insn_info
=
DF_INSN_INFO_GET
(
insn
)
;
FOR_EACH_INSN_INFO_USE
(
src_use
,
insn_info
)
{
if
(
!
rtx_equal_p
(
DF_REF_REG
(
src_use
)
,
src_reg
)
)
continue
;
struct
df_link
*
link
=
DF_REF_CHAIN
(
src_use
)
;
if
(
!
link
||
link
->
next
)
break
;
rtx_insn
*
swap_insn
=
DF_REF_INSN
(
link
->
ref
)
;
if
(
!
insn_is_swap_p
(
swap_insn
)
||
insn_is_load_p
(
swap_insn
)
||
insn_is_store_p
(
swap_insn
)
)
break
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace
=
true
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace_insn
=
swap_insn
;
XEXP
(
mem
,
0
)
=
and_operation
;
SET_SRC
(
body
)
=
src_reg
;
INSN_CODE
(
insn
)
=
1
;
df_insn_rescan
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"stvx opportunity found at %d\n"
,
INSN_UID
(
insn
)
)
;
}
}
}
</s>

If INSN is the store for an stvx pattern , put it in canonical form .


<s> bool M88kFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; const TargetSubtargetInfo & STI = MF -> getSubtarget ( ) ; const TargetInstrInfo * TII = STI . getInstrInfo ( ) ; const Register RAReg = STI . getRegisterInfo ( ) -> getRARegister ( ) ; for ( auto & CS : CSI ) { Register Reg = CS . getReg ( ) ; if ( ! MBB . isLiveIn ( Reg ) ) MBB . addLiveIn ( Reg ) ; if ( Reg != M88k :: R1 && Reg != M88k :: R30 ) { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ; } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> bool ARCAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { MF . ensureAlignment ( Align ( 4 ) ) ; return AsmPrinter :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool getConstantValue ( SDValue N , uint32_t & Out ) { if ( N . isUndef ( ) ) { Out = 0 ; return true ; } if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N ) ) { Out = C -> getAPIntValue ( ) . getSExtValue ( ) ; return true ; } if ( const ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( N ) ) { Out = C -> getValueAPF ( ) . bitcastToAPInt ( ) . getSExtValue ( ) ; return true ; } return false ; } </s>

Converts a Constant * into a GenericValue , including handling of ConstantExpr values .


<s> static int xbbo_next_reg_cluster ( int regno_start , int * sp_offset , bool do_store ) { int regno , nregs , i ; rtx addr ; rtx_insn * insn ; nregs = 0 ; for ( ; regno_start <= LAST_GP_REGNUM ; ) if ( TEST_HARD_REG_BIT ( cfun -> machine -> save_mask , regno_start ) ) break ; else regno_start ++ ; for ( regno = regno_start ; regno <= LAST_GP_REGNUM ; ) if ( TEST_HARD_REG_BIT ( cfun -> machine -> save_mask , regno ) ) { regno ++ ; nregs ++ ; } else break ; if ( ! nregs ) return - 1 ; gcc_assert ( UBYTE_INT ( * sp_offset ) ) ; addr = plus_constant ( Pmode , stack_pointer_rtx , * sp_offset ) ; if ( do_store ) insn = targetm . gen_store_multiple ( gen_frame_mem ( BLKmode , addr ) , gen_rtx_REG ( QImode , regno_start ) , GEN_INT ( nregs ) ) ; else insn = targetm . gen_load_multiple ( gen_rtx_REG ( QImode , regno_start ) , gen_frame_mem ( BLKmode , addr ) , GEN_INT ( nregs ) ) ; gcc_assert ( reload_completed ) ; gcc_assert ( insn ) ; emit_insn ( insn ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( ! do_store ) { for ( i = regno_start ; i < ( regno_start + nregs ) ; i ++ ) add_reg_note ( insn , REG_CFA_RESTORE , gen_rtx_REG ( QImode , i ) ) ; } * sp_offset += nregs * UNITS_PER_WORD ; return regno_start + nregs ; } </s>

Helper function used during prologue/epilogue . Emits a single LBBO/SBBO instruction for load/store of the next group of consecutive registers .


<s> static bool sparc_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { return to == HARD_FRAME_POINTER_REGNUM || ! sparc_frame_pointer_required ( ) ; } </s>

The way this is structured , we ca n't eliminate SFP in favor of SP if the frame pointer is required : we want to use the SFP- > HFP elimination in that case . But the test in update_eliminables does n't know we are assuming below that we only do the former elimination .


<s> bool ARMLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { const TargetMachine & TM = Fn . getTarget ( ) ; TL = TM . getTargetLowering ( ) ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; TII = TM . getInstrInfo ( ) ; TRI = TM . getRegisterInfo ( ) ; STI = & TM . getSubtarget < ARMSubtarget > ( ) ; RS = new RegScavenger ( ) ; isThumb2 = AFI -> isThumb2Function ( ) ; isThumb1 = AFI -> isThumbFunction ( ) && ! isThumb2 ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= LoadStoreMultipleOpti ( MBB ) ; if ( TM . getSubtarget < ARMSubtarget > ( ) . hasV5TOps ( ) ) Modified |= MergeReturnIntoLDM ( MBB ) ; } delete RS ; return Modified ; } </s>


<s> bool NVPTXTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , unsigned Intrinsic ) const { switch ( Intrinsic ) { default : return false ; case Intrinsic :: nvvm_atomic_load_add_f32 : Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: f32 ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . vol = 0 ; Info . readMem = true ; Info . writeMem = true ; Info . align = 0 ; return true ; case Intrinsic :: nvvm_atomic_load_inc_32 : case Intrinsic :: nvvm_atomic_load_dec_32 : Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: i32 ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . vol = 0 ; Info . readMem = true ; Info . writeMem = true ; Info . align = 0 ; return true ; case Intrinsic :: nvvm_ldu_global_i : case Intrinsic :: nvvm_ldu_global_f : case Intrinsic :: nvvm_ldu_global_p : Info . opc = ISD :: INTRINSIC_W_CHAIN ; if ( Intrinsic == Intrinsic :: nvvm_ldu_global_i ) Info . memVT = MVT :: i32 ; else if ( Intrinsic == Intrinsic :: nvvm_ldu_global_p ) Info . memVT = getPointerTy ( ) ; else Info . memVT = MVT :: f32 ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . vol = 0 ; Info . readMem = true ; Info . writeMem = false ; Info . align = 0 ; return true ; } return false ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> bool M88kMCAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { if ( ( Count % 4 ) != 0 ) return false ; for ( uint64_t I = 0 ; I != Count ; ++ I ) OS << "\xf4\x00\x58\x00" ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> TargetPassConfig * ARMBaseTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new ARMPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> bool shouldBuildLookupTables ( ) const { return false ; } </s>

Return true if switches should be turned into lookup tables for the target .


<s> static bool aarch64_return_in_msb ( const_tree valtype ) { machine_mode dummy_mode ; int dummy_int ; if ( ! BYTES_BIG_ENDIAN ) return false ; if ( ! aarch64_composite_type_p ( valtype , TYPE_MODE ( valtype ) ) || int_size_in_bytes ( valtype ) <= 0 || int_size_in_bytes ( valtype ) > 16 ) return false ; if ( aarch64_vfp_is_call_or_return_candidate ( TYPE_MODE ( valtype ) , valtype , & dummy_mode , & dummy_int , NULL ) ) return false ; return true ; } </s>

Return TRUE if VALTYPE is padded to its least significant bits .


<s> static rtx_insn * mips_epilogue_emit_cfa_restores ( void ) { rtx_insn * insn ; insn = get_last_insn ( ) ; gcc_assert ( insn && ! REG_NOTES ( insn ) ) ; if ( mips_epilogue . cfa_restores ) { RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = mips_epilogue . cfa_restores ; mips_epilogue . cfa_restores = 0 ; } return insn ; } </s>

Attach all pending register saves to the previous instruction . Return that instruction .


<s>
static
MCSymbol
*
GetSymbolFromOperand
(
const
MachineOperand
&
MO
,
AsmPrinter
&
AP
)
{
const
TargetMachine
&
TM
=
AP
.
TM
;
Mangler
&
Mang
=
TM
.
getObjFileLowering
(
)
->
getMangler
(
)
;
const
DataLayout
&
DL
=
AP
.
getDataLayout
(
)
;
MCContext
&
Ctx
=
AP
.
OutContext
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
Suffix
=
"$non_lazy_ptr"
;
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
.
getPrivateGlobalPrefix
(
)
;
if
(
!
MO
.
isGlobal
(
)
)
{
assert
(
MO
.
isSymbol
(
)
&&
"Isn't a symbol reference"
)
;
Mangler
::
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
,
DL
)
;
}
else
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
TM
.
getNameWithPrefix
(
Name
,
GV
,
Mang
)
;
}
Name
+=
Suffix
;
MCSymbol
*
Sym
=
Ctx
.
getOrCreateSymbol
(
Name
)
;
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
{
MachineModuleInfoMachO
&
MachO
=
getMachOMMI
(
AP
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
MachO
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
return
Sym
;
}
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


<s> bool ARMTargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const { if ( ! Subtarget -> isThumb ( ) ) return ARM_AM :: getSOImmVal ( ( uint32_t ) Imm ) != - 1 || ARM_AM :: getSOImmVal ( - ( uint32_t ) Imm ) != - 1 ; if ( Subtarget -> isThumb2 ( ) ) return ARM_AM :: getT2SOImmVal ( ( uint32_t ) Imm ) != - 1 || ARM_AM :: getT2SOImmVal ( - ( uint32_t ) Imm ) != - 1 ; return Imm >= 0 && Imm <= 255 ; } </s>

Return true if the specified immediate is legal icmp immediate , that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register .


<s> rtx mmix_return_addr_rtx ( int count , rtx frame ATTRIBUTE_UNUSED ) { return count == 0 ? ( MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS ? validize_mem ( gen_rtx_MEM ( Pmode , plus_constant ( frame_pointer_rtx , - 16 ) ) ) : get_hard_reg_initial_val ( Pmode , MMIX_INCOMING_RETURN_ADDRESS_REGNUM ) ) : NULL_RTX ; } </s>


<s> BitVector mprocRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> inline hashval_t bundle_state_hasher :: hash ( const bundle_state * state ) { unsigned result , i ; for ( result = i = 0 ; i < dfa_state_size ; i ++ ) result += ( ( ( unsigned char * ) state -> dfa_state ) [ i ] << ( ( i % CHAR_BIT ) * 3 + CHAR_BIT ) ) ; return result + state -> insn_num ; } </s>

Hash function for builtin functions with up to 3 arguments and a return type .


<s> void ARMConstantPoolMBB :: print ( raw_ostream & O ) const { O << printMBBReference ( * MBB ) ; ARMConstantPoolValue :: print ( O ) ; } </s>

print - Print a debug representation of the operand to the given stream .


<s>
bool
AArch64FrameLowering
::
spillCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
;
SmallVector
<
RegPairInfo
,
8
>
RegPairs
;
bool
NeedShadowCallStackProlog
=
false
;
computeCalleeSaveRegisterPairs
(
MF
,
CSI
,
TRI
,
RegPairs
,
NeedShadowCallStackProlog
)
;
const
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
if
(
NeedShadowCallStackProlog
)
{
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AArch64
::
STRXpost
)
)
.
addReg
(
AArch64
::
X18
,
RegState
::
Define
)
.
addReg
(
AArch64
::
LR
)
.
addReg
(
AArch64
::
X18
)
.
addImm
(
8
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
MBB
.
addLiveIn
(
AArch64
::
X18
)
;
}
for
(
auto
RPII
=
RegPairs
.
rbegin
(
)
,
RPIE
=
RegPairs
.
rend
(
)
;
RPII
!=
RPIE
;
++
RPII
)
{
RegPairInfo
RPI
=
*
RPII
;
unsigned
Reg1
=
RPI
.
Reg1
;
unsigned
Reg2
=
RPI
.
Reg2
;
unsigned
StrOpc
;
if
(
RPI
.
IsGPR
)
StrOpc
=
RPI
.
isPaired
(
)
AArch64
::
STPXi
:
AArch64
::
STRXui
;
else
StrOpc
=
RPI
.
isPaired
(
)
AArch64
::
STPDi
:
AArch64
::
STRDui
;
LLVM_DEBUG
(
dbgs
(
)
<<
"CSR spill: ("
<<
printReg
(
Reg1
,
TRI
)
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
printReg
(
Reg2
,
TRI
)
;
dbgs
(
)
<<
") -> fi#("
<<
RPI
.
FrameIdx
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
RPI
.
FrameIdx
+
1
;
dbgs
(
)
<<
")\n"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
StrOpc
)
)
;
if
(
!
MRI
.
isReserved
(
Reg1
)
)
MBB
.
addLiveIn
(
Reg1
)
;
if
(
RPI
.
isPaired
(
)
)
{
if
(
!
MRI
.
isReserved
(
Reg2
)
)
MBB
.
addLiveIn
(
Reg2
)
;
MIB
.
addReg
(
Reg2
,
getPrologueDeath
(
MF
,
Reg2
)
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
+
1
)
,
MachineMemOperand
::
MOStore
,
8
,
8
)
)
;
}
MIB
.
addReg
(
Reg1
,
getPrologueDeath
(
MF
,
Reg1
)
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
RPI
.
Offset
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
)
,
MachineMemOperand
::
MOStore
,
8
,
8
)
)
;
}
return
true
;
}
</s>


"Only register-returns should be created by PCS"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> const CallLowering * getCallLowering ( ) const override { return CL . get ( ) ; } </s>


<s> bool X86CondBrFolding :: analyzeCompare ( const MachineInstr & MI , unsigned & SrcReg , int & CmpValue ) { unsigned SrcRegIndex = 0 ; unsigned ValueIndex = 0 ; switch ( MI . getOpcode ( ) ) { default : return false ; case X86 :: CMP64ri32 : case X86 :: CMP64ri8 : case X86 :: CMP32ri : case X86 :: CMP32ri8 : case X86 :: CMP16ri : case X86 :: CMP16ri8 : case X86 :: CMP8ri : SrcRegIndex = 0 ; ValueIndex = 1 ; break ; case X86 :: SUB64ri32 : case X86 :: SUB64ri8 : case X86 :: SUB32ri : case X86 :: SUB32ri8 : case X86 :: SUB16ri : case X86 :: SUB16ri8 : case X86 :: SUB8ri : SrcRegIndex = 1 ; ValueIndex = 2 ; break ; } SrcReg = MI . getOperand ( SrcRegIndex ) . getReg ( ) ; if ( ! MI . getOperand ( ValueIndex ) . isImm ( ) ) return false ; CmpValue = MI . getOperand ( ValueIndex ) . getImm ( ) ; return true ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> static rtx mips_call_expr_from_insn ( rtx_insn * insn , rtx * second_call ) { rtx x ; rtx x2 ; if ( ! CALL_P ( insn ) ) return NULL_RTX ; x = PATTERN ( insn ) ; if ( GET_CODE ( x ) == PARALLEL ) { x2 = XVECEXP ( x , 0 , 1 ) ; if ( GET_CODE ( x2 ) == SET ) x2 = XEXP ( x2 , 1 ) ; if ( GET_CODE ( x2 ) == CALL ) * second_call = x2 ; x = XVECEXP ( x , 0 , 0 ) ; } if ( GET_CODE ( x ) == SET ) x = XEXP ( x , 1 ) ; gcc_assert ( GET_CODE ( x ) == CALL ) ; return x ; } </s>

If INSN is a call , return the underlying CALL expr . Return NULL_RTX otherwise . If INSN has two call rtx , then store the second one in SECOND_CALL .


<s>
StringRef
getPassName
(
)
const
override
{
return
"R600 OpenCL Image Type Pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> int arm_const_double_rtx ( rtx x ) { REAL_VALUE_TYPE r ; if ( ! fp_consts_inited ) init_fp_table ( ) ; REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; if ( REAL_VALUE_MINUS_ZERO ( r ) ) return 0 ; if ( REAL_VALUES_EQUAL ( r , value_fp0 ) ) return 1 ; return 0 ; } </s>

Return TRUE if rtx X is a valid immediate FP constant .


<s> bool SIPreEmitPeephole :: runOnMachineFunction ( MachineFunction & MF ) { const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; MachineBasicBlock * EmptyMBBAtEnd = nullptr ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { MachineBasicBlock :: iterator MBBE = MBB . getFirstTerminator ( ) ; if ( MBBE != MBB . end ( ) ) { MachineInstr & MI = * MBBE ; switch ( MI . getOpcode ( ) ) { case AMDGPU :: S_CBRANCH_VCCZ : case AMDGPU :: S_CBRANCH_VCCNZ : Changed |= optimizeVccBranch ( MI ) ; continue ; case AMDGPU :: SI_RETURN_TO_EPILOG : assert ( ! MF . getInfo < SIMachineFunctionInfo > ( ) -> returnsVoid ( ) ) ; if ( & MBB != & MF . back ( ) || & MI != & MBB . back ( ) ) { if ( ! EmptyMBBAtEnd ) { EmptyMBBAtEnd = MF . CreateMachineBasicBlock ( ) ; MF . insert ( MF . end ( ) , EmptyMBBAtEnd ) ; } MBB . addSuccessor ( EmptyMBBAtEnd ) ; BuildMI ( MBB , & MI , MI . getDebugLoc ( ) , TII -> get ( AMDGPU :: S_BRANCH ) ) . addMBB ( EmptyMBBAtEnd ) ; MI . eraseFromParent ( ) ; MBBE = MBB . getFirstTerminator ( ) ; } break ; default : break ; } } if ( ! ST . hasVGPRIndexMode ( ) ) continue ; MachineInstr * SetGPRMI = nullptr ; const unsigned Threshold = 20 ; unsigned Count = 0 ; for ( MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; MBBI != MBBE ; ) { MachineInstr & MI = * MBBI ; ++ MBBI ; if ( Count == Threshold ) SetGPRMI = nullptr ; else ++ Count ; if ( MI . getOpcode ( ) != AMDGPU :: S_SET_GPR_IDX_ON ) continue ; Count = 0 ; if ( ! SetGPRMI ) { SetGPRMI = & MI ; continue ; } if ( optimizeSetGPR ( * SetGPRMI , MI ) ) Changed = true ; else SetGPRMI = & MI ; } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool avr_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; HOST_WIDE_INT ret_size_limit = AVR_TINY ? 4 : 8 ; if ( size == - 1 || size > ret_size_limit ) { return true ; } else { return false ; } } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


<s> void UPTInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , get ( UPT :: STR ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


Given a constant with the SectionKind , return a section that it should be placed in .


<s> static bool rs6000_vector_alignment_reachable ( const_tree type ATTRIBUTE_UNUSED , bool is_packed ) { if ( is_packed ) return false ; if ( TARGET_32BIT ) { if ( rs6000_alignment_flags == MASK_ALIGN_NATURAL ) return true ; if ( rs6000_alignment_flags == MASK_ALIGN_POWER ) return true ; return false ; } else { if ( TARGET_MACHO ) return false ; return true ; } } </s>

Return true iff , data reference of TYPE can reach vector alignment ( 16 ) after applying N number of iterations . This routine does not determine how may iterations are required to reach desired alignment .


<s> void BPFDAGToDAGISel :: PreprocessISelDAG ( ) { for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * Node = & * I ++ ; unsigned Opcode = Node -> getOpcode ( ) ; if ( Opcode == ISD :: LOAD ) PreprocessLoad ( Node , I ) ; else if ( Opcode == ISD :: AND ) PreprocessTrunc ( Node , I ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s>
bool
SIOptimizeVGPRLiveRange
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
const
GCNSubtarget
&
ST
=
MF
.
getSubtarget
<
GCNSubtarget
>
(
)
;
TII
=
ST
.
getInstrInfo
(
)
;
TRI
=
&
TII
->
getRegisterInfo
(
)
;
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
Loops
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
LV
=
&
getAnalysis
<
LiveVariables
>
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
bool
MadeChange
=
false
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
for
(
auto
&
MI
:
MBB
.
terminators
(
)
)
{
if
(
MI
.
getOpcode
(
)
==
AMDGPU
::
SI_IF
)
{
MachineBasicBlock
*
IfTarget
=
MI
.
getOperand
(
2
)
.
getMBB
(
)
;
auto
*
Endif
=
getElseTarget
(
IfTarget
)
;
if
(
!
Endif
)
continue
;
SmallSetVector
<
MachineBasicBlock
*
,
16
>
ElseBlocks
;
SmallVector
<
Register
>
CandidateRegs
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Checking IF-ELSE-ENDIF: "
<<
printMBBReference
(
MBB
)
<<
' '
<<
printMBBReference
(
*
IfTarget
)
<<
' '
<<
printMBBReference
(
*
Endif
)
<<
'\n'
)
;
collectElseRegionBlocks
(
IfTarget
,
Endif
,
ElseBlocks
)
;
collectCandidateRegisters
(
&
MBB
,
IfTarget
,
Endif
,
ElseBlocks
,
CandidateRegs
)
;
MadeChange
|=
!
CandidateRegs
.
empty
(
)
;
for
(
auto
Reg
:
CandidateRegs
)
optimizeLiveRange
(
Reg
,
&
MBB
,
IfTarget
,
Endif
,
ElseBlocks
)
;
}
else
if
(
MI
.
getOpcode
(
)
==
AMDGPU
::
SI_WATERFALL_LOOP
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Checking Waterfall loop: "
<<
printMBBReference
(
MBB
)
<<
'\n'
)
;
SmallSetVector
<
Register
,
16
>
CandidateRegs
;
collectWaterfallCandidateRegisters
(
&
MBB
,
CandidateRegs
)
;
MadeChange
|=
!
CandidateRegs
.
empty
(
)
;
for
(
auto
Reg
:
CandidateRegs
)
optimizeWaterfallLiveRange
(
Reg
,
&
MBB
)
;
}
}
}
return
MadeChange
;
}
</s>


<s> unsigned postOffset ( ) const { return Offset + Size ; } </s>

Compute the offset immediately following this block .


<s> unsigned X86TargetLowering :: getByValTypeAlignment ( const Type * Ty ) const { if ( Subtarget -> is64Bit ( ) ) { unsigned TyAlign = TD -> getABITypeAlignment ( Ty ) ; if ( TyAlign > 8 ) return TyAlign ; return 8 ; } unsigned Align = 4 ; if ( Subtarget -> hasXMM ( ) ) getMaxByValAlign ( Ty , Align ) ; return Align ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


<s> static unsigned int ix86_minimum_incoming_stack_boundary ( bool sibcall ) { unsigned int incoming_stack_boundary ; if ( ix86_user_incoming_stack_boundary ) incoming_stack_boundary = ix86_user_incoming_stack_boundary ; else if ( ! sibcall && ! TARGET_64BIT && ix86_force_align_arg_pointer && crtl -> stack_alignment_estimated == 128 ) incoming_stack_boundary = MIN_STACK_BOUNDARY ; else incoming_stack_boundary = ix86_default_incoming_stack_boundary ; if ( incoming_stack_boundary > MIN_STACK_BOUNDARY && lookup_attribute ( ix86_force_align_arg_pointer_string , TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ) ) incoming_stack_boundary = MIN_STACK_BOUNDARY ; if ( incoming_stack_boundary < crtl -> parm_stack_boundary ) incoming_stack_boundary = crtl -> parm_stack_boundary ; if ( incoming_stack_boundary > MAIN_STACK_BOUNDARY && DECL_NAME ( current_function_decl ) && MAIN_NAME_P ( DECL_NAME ( current_function_decl ) ) && DECL_FILE_SCOPE_P ( current_function_decl ) ) incoming_stack_boundary = MAIN_STACK_BOUNDARY ; return incoming_stack_boundary ; } </s>

Return minimum incoming stack alignment .


<s> std :: pair < unsigned , const TargetRegisterClass * > PPCTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'b' : case 'r' : if ( VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) ) return std :: make_pair ( 0U , PPC :: G8RCRegisterClass ) ; return std :: make_pair ( 0U , PPC :: GPRCRegisterClass ) ; case 'f' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , PPC :: F4RCRegisterClass ) ; else if ( VT == MVT :: f64 ) return std :: make_pair ( 0U , PPC :: F8RCRegisterClass ) ; break ; case 'v' : return std :: make_pair ( 0U , PPC :: VRRCRegisterClass ) ; case 'y' : return std :: make_pair ( 0U , PPC :: CRRCRegisterClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> bool SparcAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; O << '[' ; printMemOperand ( MI , OpNo , O ) ; O << ']' ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> static rtx legitimize_pe_coff_symbol ( rtx addr , bool inreg ) { if ( ! TARGET_PECOFF ) return NULL_RTX ; if ( TARGET_DLLIMPORT_DECL_ATTRIBUTES ) { if ( GET_CODE ( addr ) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P ( addr ) ) return legitimize_dllimport_symbol ( addr , inreg ) ; if ( GET_CODE ( addr ) == CONST && GET_CODE ( XEXP ( addr , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) ) { rtx t = legitimize_dllimport_symbol ( XEXP ( XEXP ( addr , 0 ) , 0 ) , inreg ) ; return gen_rtx_PLUS ( Pmode , t , XEXP ( XEXP ( addr , 0 ) , 1 ) ) ; } } if ( ix86_cmodel != CM_LARGE_PIC && ix86_cmodel != CM_MEDIUM_PIC ) return NULL_RTX ; if ( GET_CODE ( addr ) == SYMBOL_REF && ! is_imported_p ( addr ) && SYMBOL_REF_EXTERNAL_P ( addr ) && SYMBOL_REF_DECL ( addr ) ) return legitimize_pe_coff_extern_decl ( addr , inreg ) ; if ( GET_CODE ( addr ) == CONST && GET_CODE ( XEXP ( addr , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) == SYMBOL_REF && ! is_imported_p ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) && SYMBOL_REF_EXTERNAL_P ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) && SYMBOL_REF_DECL ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) ) { rtx t = legitimize_pe_coff_extern_decl ( XEXP ( XEXP ( addr , 0 ) , 0 ) , inreg ) ; return gen_rtx_PLUS ( Pmode , t , XEXP ( XEXP ( addr , 0 ) , 1 ) ) ; } return NULL_RTX ; } </s>

Expand SYMBOL into its corresponding dllimport or refptr symbol . WANT_REG is true if we require the result be a register .


<s> static bool is_cracked_insn ( rtx_insn * insn ) { if ( ! insn || ! NONDEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; if ( rs6000_sched_groups && ( rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5 ) ) { enum attr_type type = get_attr_type ( insn ) ; if ( ( type == TYPE_LOAD && get_attr_sign_extend ( insn ) == SIGN_EXTEND_YES && get_attr_update ( insn ) == UPDATE_NO ) || ( type == TYPE_LOAD && get_attr_sign_extend ( insn ) == SIGN_EXTEND_NO && get_attr_update ( insn ) == UPDATE_YES && get_attr_indexed ( insn ) == INDEXED_NO ) || ( type == TYPE_STORE && get_attr_update ( insn ) == UPDATE_YES && get_attr_indexed ( insn ) == INDEXED_NO ) || ( ( type == TYPE_FPLOAD || type == TYPE_FPSTORE ) && get_attr_update ( insn ) == UPDATE_YES ) || ( type == TYPE_CR_LOGICAL && get_attr_cr_logical_3op ( insn ) == CR_LOGICAL_3OP_YES ) || ( type == TYPE_EXTS && get_attr_dot ( insn ) == DOT_YES ) || ( type == TYPE_SHIFT && get_attr_dot ( insn ) == DOT_YES && get_attr_var_shift ( insn ) == VAR_SHIFT_NO ) || ( type == TYPE_MUL && get_attr_dot ( insn ) == DOT_YES ) || type == TYPE_DIV || ( type == TYPE_INSERT && get_attr_size ( insn ) == SIZE_32 ) ) return true ; } return false ; } </s>

The function returns true if INSN is cracked into 2 instructions by the processor ( and therefore occupies 2 issue slots ) .


<s>
static
void
arc_output_mi_thunk
(
FILE
*
file
,
tree
thunk
ATTRIBUTE_UNUSED
,
HOST_WIDE_INT
delta
,
HOST_WIDE_INT
vcall_offset
,
tree
function
)
{
int
mi_delta
=
delta
;
const
char
*
const
mi_op
=
mi_delta
<
0
"sub"
:
"add"
;
int
shift
=
0
;
int
this_regno
=
aggregate_value_p
(
TREE_TYPE
(
TREE_TYPE
(
function
)
)
,
function
)
1
:
0
;
rtx
fnaddr
;
if
(
mi_delta
<
0
)
mi_delta
=
mi_delta
;
while
(
mi_delta
!=
0
)
{
if
(
(
mi_delta
&
(
3
<<
shift
)
)
==
0
)
shift
+=
2
;
else
{
asm_fprintf
(
file
,
"\t%s\t%s, %s, %d\n"
,
mi_op
,
reg_names
[
this_regno
]
,
reg_names
[
this_regno
]
,
mi_delta
&
(
0xff
<<
shift
)
)
;
mi_delta
&=
~
(
0xff
<<
shift
)
;
shift
+=
8
;
}
}
if
(
vcall_offset
!=
0
)
{
asm_fprintf
(
file
,
"\tld\t%s, [%s]\n"
,
ARC_TEMP_SCRATCH_REG
,
reg_names
[
this_regno
]
)
;
asm_fprintf
(
file
,
"\tadd\t%s, %s, "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
ARC_TEMP_SCRATCH_REG
,
ARC_TEMP_SCRATCH_REG
,
vcall_offset
)
;
asm_fprintf
(
file
,
"\tld\t%s, [%s]\n"
,
ARC_TEMP_SCRATCH_REG
,
ARC_TEMP_SCRATCH_REG
)
;
asm_fprintf
(
file
,
"\tadd\t%s, %s, %s\n"
,
reg_names
[
this_regno
]
,
reg_names
[
this_regno
]
,
ARC_TEMP_SCRATCH_REG
)
;
}
fnaddr
=
XEXP
(
DECL_RTL
(
function
)
,
0
)
;
if
(
arc_is_longcall_p
(
fnaddr
)
)
{
if
(
flag_pic
)
{
asm_fprintf
(
file
,
"\tld\t%s, [pcl, @"
,
ARC_TEMP_SCRATCH_REG
)
;
assemble_name
(
file
,
XSTR
(
fnaddr
,
0
)
)
;
fputs
(
"@gotpc]\n"
,
file
)
;
asm_fprintf
(
file
,
"\tj\t[%s]"
,
ARC_TEMP_SCRATCH_REG
)
;
}
else
{
fputs
(
"\tj\t@"
,
file
)
;
assemble_name
(
file
,
XSTR
(
fnaddr
,
0
)
)
;
}
}
else
{
fputs
(
"\tb\t@"
,
file
)
;
assemble_name
(
file
,
XSTR
(
fnaddr
,
0
)
)
;
if
(
flag_pic
)
fputs
(
"@plt\n"
,
file
)
;
}
fputc
(
'\n'
,
file
)
;
}
</s>

Output code to add DELTA to the first argument , and then jump to FUNCTION . Used for C++ multiple inheritance .


<s>
void
OpenRISCInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
;
if
(
OpenRISC
::
GR32RegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
OpenRISC
::
OR32rr
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> void tilegx_post_atomic_barrier ( enum memmodel model ) { if ( need_atomic_barrier_p ( model , false ) ) emit_insn ( gen_memory_barrier ( ) ) ; } </s>

Emit barrier after an atomic , as needed for the memory MODEL .


<s> static rtx strip_salt ( rtx x ) { rtx search = x ; if ( GET_CODE ( search ) == CONST ) search = XEXP ( search , 0 ) ; if ( GET_CODE ( search ) == UNSPEC && XINT ( search , 1 ) == UNSPEC_SALT_ADDR ) x = XVECEXP ( search , 0 , 0 ) ; return x ; } </s>

If X is an UNSPEC_SALT_ADDR expression , return the address that it wraps , otherwise return X itself .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool PPCTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( DisablePPCPreinc ) return false ; bool isLoad = true ; SDValue Ptr ; EVT VT ; unsigned Alignment ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; Alignment = LD -> getAlignment ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Alignment = ST -> getAlignment ( ) ; isLoad = false ; } else return false ; if ( isLoad && usePartialVectorLoads ( N ) ) { return false ; } if ( VT . isVector ( ) ) { if ( ! Subtarget . hasQPX ( ) || ( VT != MVT :: v4f64 && VT != MVT :: v4f32 ) ) { return false ; } else if ( SelectAddressRegRegOnly ( Ptr , Offset , Base , DAG ) ) { AM = ISD :: PRE_INC ; return true ; } } if ( SelectAddressRegReg ( Ptr , Base , Offset , DAG ) ) { bool Swap = false ; if ( isa < FrameIndexSDNode > ( Base ) || isa < RegisterSDNode > ( Base ) ) Swap = true ; else if ( ! isLoad ) { SDValue Val = cast < StoreSDNode > ( N ) -> getValue ( ) ; if ( Val == Base || Base . getNode ( ) -> isPredecessorOf ( Val . getNode ( ) ) ) Swap = true ; } if ( Swap ) std :: swap ( Base , Offset ) ; AM = ISD :: PRE_INC ; return true ; } if ( VT != MVT :: i64 ) { if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , 0 ) ) return false ; } else { if ( Alignment < 4 ) return false ; if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , 4 ) ) return false ; } if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { if ( LD -> getValueType ( 0 ) == MVT :: i64 && LD -> getMemoryVT ( ) == MVT :: i32 && LD -> getExtensionType ( ) == ISD :: SEXTLOAD && isa < ConstantSDNode > ( Offset ) ) return false ; } AM = ISD :: PRE_INC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .


<s> void s390_cpu_cpp_builtins ( cpp_reader * pfile ) { struct cl_target_option opts ; cpp_assert ( pfile , "cpu=s390" ) ; cpp_assert ( pfile , "machine=s390" ) ; cpp_define ( pfile , "__s390__" ) ; if ( TARGET_ZARCH ) cpp_define ( pfile , "__zarch__" ) ; if ( TARGET_64BIT ) cpp_define ( pfile , "__s390x__" ) ; if ( TARGET_LONG_DOUBLE_128 ) cpp_define ( pfile , "__LONG_DOUBLE_128__" ) ; cl_target_option_save ( & opts , & global_options , & global_options_set ) ; s390_cpu_cpp_builtins_internal ( pfile , & opts , NULL ) ; } </s>


"llvm.clear_cache is not supported on wasm"

Intel processors have a unified instruction and data cache .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"optimise barriers pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
SDValue
BlackfinTargetLowering
::
LowerReturn
(
SDValue
Chain
,
unsigned
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getTarget
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_Blackfin
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Opi
=
Outs
[
i
]
.
Val
;
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
SExt
:
Opi
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Opi
)
;
break
;
case
CCValAssign
::
ZExt
:
Opi
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Opi
)
;
break
;
case
CCValAssign
::
AExt
:
Opi
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Opi
)
;
break
;
}
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
Opi
,
SDValue
(
)
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
{
return
DAG
.
getNode
(
BFISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
}
else
{
return
DAG
.
getNode
(
BFISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


"Cannot load this register from a stack slot!"

Load the specified register of the given register class from the specified stack frame index .


<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < 512 > Key ; Key . reserve ( CPU . size ( ) + FS . size ( ) ) ; Key += CPU ; Key += FS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) Key += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; unsigned CPUFSWidth = Key . size ( ) ; unsigned PreferVectorWidthOverride = 0 ; if ( F . hasFnAttribute ( "prefer-vector-width" ) ) { StringRef Val = F . getFnAttribute ( "prefer-vector-width" ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( 0 , Width ) ) { Key += ",prefer-vector-width=" ; Key += Val ; PreferVectorWidthOverride = Width ; } } unsigned RequiredVectorWidth = UINT32_MAX ; if ( F . hasFnAttribute ( "min-legal-vector-width" ) ) { StringRef Val = F . getFnAttribute ( "min-legal-vector-width" ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( 0 , Width ) ) { Key += ",min-legal-vector-width=" ; Key += Val ; RequiredVectorWidth = Width ; } } FS = Key . slice ( CPU . size ( ) , CPUFSWidth ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < X86Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride , PreferVectorWidthOverride , RequiredVectorWidth ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"LC3b Assembly Printer"
;
}
</s>


<s> static void avoid_func_arg_motion ( rtx_insn * first_arg , rtx_insn * insn ) { rtx set ; rtx tmp ; set = single_set ( insn ) ; if ( ! set ) return ; tmp = SET_DEST ( set ) ; if ( REG_P ( tmp ) ) { add_dependence ( first_arg , insn , REG_DEP_OUTPUT ) ; return ; } add_dependence ( first_arg , insn , REG_DEP_ANTI ) ; } </s>

Add output or anti dependency from insn to first_arg to restrict its code motion .


<s> static void frv_split_iacc_move ( rtx dest , rtx src ) { machine_mode inner ; int i ; inner = GET_MODE ( dest ) ; for ( i = 0 ; i < GET_MODE_SIZE ( inner ) ; i += GET_MODE_SIZE ( SImode ) ) emit_move_insn ( simplify_gen_subreg ( SImode , dest , inner , i ) , simplify_gen_subreg ( SImode , src , inner , i ) ) ; } </s>

Emit a move from SRC to DEST in SImode chunks . This can be used to move DImode values into and out of IACC0 .


<s> static bool arc_in_small_data_p ( const_tree decl ) { HOST_WIDE_INT size ; tree attr ; if ( TREE_CODE ( decl ) != VAR_DECL ) return false ; if ( TARGET_NO_SDATA_SET ) return false ; if ( DECL_WEAK ( decl ) ) return false ; if ( TREE_READONLY ( decl ) ) return false ; if ( ! TARGET_VOLATILE_CACHE_SET && TREE_THIS_VOLATILE ( decl ) ) return false ; attr = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; if ( lookup_attribute ( "uncached" , attr ) ) return false ; attr = DECL_ATTRIBUTES ( decl ) ; if ( lookup_attribute ( "aux" , attr ) ) return false ; if ( DECL_SECTION_NAME ( decl ) != 0 ) { const char * name = DECL_SECTION_NAME ( decl ) ; if ( strcmp ( name , ".sdata" ) == 0 || strcmp ( name , ".sbss" ) == 0 ) return true ; } else if ( TREE_PUBLIC ( decl ) ) { size = int_size_in_bytes ( TREE_TYPE ( decl ) ) ; return ( size > 0 && size <= g_switch_value ) ; } return false ; } </s>

Implement TARGET_IN_SMALL_DATA_P . Return true if it would be safe to access DECL using % gp_rel ( ... ) ( $ gp ) .


<s> bool LEGRegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> static rtx ix86_expand_unop_vec_merge_builtin ( enum insn_code icode , tree exp , rtx target ) { rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , 0 ) ; rtx op1 , op0 = expand_normal ( arg0 ) ; machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; machine_mode mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; if ( optimize || ! target || GET_MODE ( target ) != tmode || ! insn_data [ icode ] . operand [ 0 ] . predicate ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! insn_data [ icode ] . operand [ 1 ] . predicate ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; op1 = op0 ; if ( ! insn_data [ icode ] . operand [ 2 ] . predicate ( op1 , mode0 ) ) op1 = copy_to_mode_reg ( mode0 , op1 ) ; pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>

Subroutine of ix86_expand_args_builtin to take care of scalar unop insns with vec_merge .


<s>
const
char
*
output_64bit_and
(
rtx
*
operands
)
{
if
(
GET_CODE
(
operands
[
2
]
)
==
CONST_INT
&&
INTVAL
(
operands
[
2
]
)
!=
0
)
{
unsigned
HOST_WIDE_INT
mask
=
INTVAL
(
operands
[
2
]
)
;
int
ls0
,
ls1
,
ms0
,
p
,
len
;
for
(
ls0
=
0
;
ls0
<
HOST_BITS_PER_WIDE_INT
;
ls0
++
)
if
(
(
mask
&
(
(
unsigned
HOST_WIDE_INT
)
1
<<
ls0
)
)
==
0
)
break
;
for
(
ls1
=
ls0
;
ls1
<
HOST_BITS_PER_WIDE_INT
;
ls1
++
)
if
(
(
mask
&
(
(
unsigned
HOST_WIDE_INT
)
1
<<
ls1
)
)
!=
0
)
break
;
for
(
ms0
=
ls1
;
ms0
<
HOST_BITS_PER_WIDE_INT
;
ms0
++
)
if
(
(
mask
&
(
(
unsigned
HOST_WIDE_INT
)
1
<<
ms0
)
)
==
0
)
break
;
gcc_assert
(
ms0
==
HOST_BITS_PER_WIDE_INT
)
;
if
(
ls1
==
HOST_BITS_PER_WIDE_INT
)
{
len
=
ls0
;
gcc_assert
(
len
)
;
operands
[
2
]
=
GEN_INT
(
len
)
;
return
"extrd,u %1,63,%2,%0"
;
}
else
{
p
=
63
ls0
;
len
=
ls1
ls0
;
operands
[
2
]
=
GEN_INT
(
p
)
;
operands
[
3
]
=
GEN_INT
(
len
)
;
return
"depdi 0,%2,%3,%0"
;
}
}
else
return
"and %1,%2,%0"
;
}
</s>

Return a string to perform a bitwise-and of operands [ 1 ] with operands [ 2 ] storing the result in operands [ 0 ] .


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , JIT , TT . getArch ( ) == Triple :: x86_64 ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) { if ( ( TT . isOSWindows ( ) && TT . getArch ( ) == Triple :: x86_64 ) || TT . isPS4 ( ) || TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = TT . isOSBinFormatMachO ( ) ; } if ( TT . getArch ( ) == Triple :: x86_64 ) setMachineOutliner ( true ) ; initAsmInfo ( ) ; } </s>


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> hasFnAttr ( Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( N -> getOpcode ( ) == X86ISD :: CALL || N -> getOpcode ( ) == X86ISD :: TC_RETURN ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; EVT SrcVT = N -> getOperand ( 0 ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( 0 ) ; bool SrcIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s>
void
SIInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
Register
SrcReg
,
bool
isKill
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
SIMachineFunctionInfo
*
MFI
=
MF
->
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MachineFrameInfo
&
FrameInfo
=
MF
->
getFrameInfo
(
)
;
const
DebugLoc
&
DL
=
MBB
.
findDebugLoc
(
MI
)
;
MachinePointerInfo
PtrInfo
=
MachinePointerInfo
::
getFixedStack
(
*
MF
,
FrameIndex
)
;
MachineMemOperand
*
MMO
=
MF
->
getMachineMemOperand
(
PtrInfo
,
MachineMemOperand
::
MOStore
,
FrameInfo
.
getObjectSize
(
FrameIndex
)
,
FrameInfo
.
getObjectAlign
(
FrameIndex
)
)
;
unsigned
SpillSize
=
TRI
->
getSpillSize
(
*
RC
)
;
if
(
RI
.
isSGPRClass
(
RC
)
)
{
MFI
->
setHasSpilledSGPRs
(
)
;
assert
(
SrcReg
!=
AMDGPU
::
M0
&&
"m0 should not be spilled"
)
;
const
MCInstrDesc
&
OpDesc
=
get
(
getSGPRSpillSaveOpcode
(
SpillSize
)
)
;
if
(
Register
::
isVirtualRegister
(
SrcReg
)
&&
SpillSize
==
4
)
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
MRI
.
constrainRegClass
(
SrcReg
,
&
AMDGPU
::
SReg_32_XM0RegClass
)
;
}
BuildMI
(
MBB
,
MI
,
DL
,
OpDesc
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIndex
)
.
addMemOperand
(
MMO
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
,
RegState
::
Implicit
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
,
RegState
::
Implicit
)
;
if
(
RI
.
spillSGPRToVGPR
(
)
)
FrameInfo
.
setStackID
(
FrameIndex
,
TargetStackID
::
SGPRSpill
)
;
return
;
}
unsigned
Opcode
=
RI
.
hasAGPRs
(
RC
)
getAGPRSpillSaveOpcode
(
SpillSize
)
:
getVGPRSpillSaveOpcode
(
SpillSize
)
;
MFI
->
setHasSpilledVGPRs
(
)
;
auto
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opcode
)
)
;
if
(
RI
.
hasAGPRs
(
RC
)
)
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
Register
Tmp
=
MRI
.
createVirtualRegister
(
&
AMDGPU
::
VGPR_32RegClass
)
;
MIB
.
addReg
(
Tmp
,
RegState
::
Define
)
;
}
MIB
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIndex
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> void SIRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , Register BaseReg , int FrameIdx , int64_t Offset ) const { MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const SIInstrInfo * TII = ST . getInstrInfo ( ) ; unsigned MovOpc = ST . enableFlatScratch ( ) ? AMDGPU :: S_MOV_B32 : AMDGPU :: V_MOV_B32_e32 ; if ( Offset == 0 ) { BuildMI ( * MBB , Ins , DL , TII -> get ( MovOpc ) , BaseReg ) . addFrameIndex ( FrameIdx ) ; return ; } MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; Register OffsetReg = MRI . createVirtualRegister ( & AMDGPU :: SReg_32_XM0RegClass ) ; Register FIReg = MRI . createVirtualRegister ( ST . enableFlatScratch ( ) ? & AMDGPU :: SReg_32_XM0RegClass : & AMDGPU :: VGPR_32RegClass ) ; BuildMI ( * MBB , Ins , DL , TII -> get ( AMDGPU :: S_MOV_B32 ) , OffsetReg ) . addImm ( Offset ) ; BuildMI ( * MBB , Ins , DL , TII -> get ( MovOpc ) , FIReg ) . addFrameIndex ( FrameIdx ) ; if ( ST . enableFlatScratch ( ) ) { BuildMI ( * MBB , Ins , DL , TII -> get ( AMDGPU :: S_ADD_U32 ) , BaseReg ) . addReg ( OffsetReg , RegState :: Kill ) . addReg ( FIReg ) ; return ; } TII -> getAddNoCarry ( * MBB , Ins , DL , BaseReg ) . addReg ( OffsetReg , RegState :: Kill ) . addReg ( FIReg ) . addImm ( 0 ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .


<s> const char * ARMTargetLowering :: LowerXConstraint ( EVT ConstraintVT ) const { if ( ! Subtarget -> hasVFP2Base ( ) ) return "r" ; if ( ConstraintVT . isFloatingPoint ( ) ) return "w" ; if ( ConstraintVT . isVector ( ) && Subtarget -> hasNEON ( ) && ( ConstraintVT . getSizeInBits ( ) == 64 || ConstraintVT . getSizeInBits ( ) == 128 ) ) return "w" ; return "r" ; } </s>

Try to replace an X constraint , which matches anything , with another that has more specific requirements based on the type of the corresponding operand .


<s> bool isThumb ( ) const { return isThumbMode ; } </s>

Tests whether the target is Thumb ( little and big endian ) .


<s>
bool
SystemZAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
unsigned
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
;
MatchResult
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MatchingInlineAsm
)
;
switch
(
MatchResult
)
{
default
:
break
;
case
Match_Success
:
Inst
.
setLoc
(
IDLoc
)
;
Out
.
EmitInstruction
(
Inst
,
STI
)
;
return
false
;
case
Match_MissingFeature
:
{
assert
(
ErrorInfo
&&
"Unknown missing feature!"
)
;
std
::
string
Msg
=
"instruction requires:"
;
unsigned
Mask
=
1
;
for
(
unsigned
I
=
0
;
I
<
sizeof
(
ErrorInfo
)
*
8
1
;
++
I
)
{
if
(
ErrorInfo
&
Mask
)
{
Msg
+=
" "
;
Msg
+=
getSubtargetFeatureName
(
ErrorInfo
&
Mask
)
;
}
Mask
<<=
1
;
}
return
Error
(
IDLoc
,
Msg
)
;
}
case
Match_InvalidOperand
:
{
SMLoc
ErrorLoc
=
IDLoc
;
if
(
ErrorInfo
!=
~
0U
)
{
if
(
ErrorInfo
>=
Operands
.
size
(
)
)
return
Error
(
IDLoc
,
"too few operands for instruction"
)
;
ErrorLoc
=
(
(
SystemZOperand
&
)
*
Operands
[
ErrorInfo
]
)
.
getStartLoc
(
)
;
if
(
ErrorLoc
==
SMLoc
(
)
)
ErrorLoc
=
IDLoc
;
}
return
Error
(
ErrorLoc
,
"invalid operand for instruction"
)
;
}
case
Match_MnemonicFail
:
return
Error
(
IDLoc
,
"invalid instruction"
)
;
}
llvm_unreachable
(
"Unexpected match type"
)
;
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> void msp430_expand_helper ( rtx * operands , const char * helper_name , bool const_variants ) { rtx c , fusage , fsym ; char * helper_const = NULL ; int arg1 = 12 ; int arg2 = 13 ; int arg1sz = 1 ; machine_mode arg0mode = GET_MODE ( operands [ 0 ] ) ; machine_mode arg1mode = GET_MODE ( operands [ 1 ] ) ; machine_mode arg2mode = GET_MODE ( operands [ 2 ] ) ; int expand_mpy = startswith ( helper_name , "__mspabi_mpy" ) ; gcc_assert ( ! ( expand_mpy && const_variants ) ) ; if ( arg1mode != VOIDmode && arg2mode != VOIDmode ) gcc_assert ( arg1mode == arg2mode ) ; if ( arg1mode == VOIDmode ) arg1mode = arg0mode ; if ( arg2mode == VOIDmode ) arg2mode = arg0mode ; if ( arg1mode == SImode ) { arg2 = 14 ; arg1sz = 2 ; } else if ( arg1mode == DImode ) { arg1 = 8 ; arg1sz = 4 ; arg2 = 12 ; } if ( const_variants && CONST_INT_P ( operands [ 2 ] ) && INTVAL ( operands [ 2 ] ) >= 1 && INTVAL ( operands [ 2 ] ) <= 15 ) { int len = strlen ( helper_name ) + 4 ; helper_const = ( char * ) xmalloc ( len ) ; snprintf ( helper_const , len , "%s_%d" , helper_name , ( int ) INTVAL ( operands [ 2 ] ) ) ; } emit_move_insn ( gen_rtx_REG ( arg1mode , arg1 ) , operands [ 1 ] ) ; if ( ! helper_const ) emit_move_insn ( gen_rtx_REG ( arg2mode , arg2 ) , operands [ 2 ] ) ; if ( expand_mpy ) { if ( msp430_use_f5_series_hwmult ( ) ) fsym = gen_rtx_SYMBOL_REF ( VOIDmode , concat ( helper_name , "_f5hw" , NULL ) ) ; else if ( msp430_use_32bit_hwmult ( ) ) { if ( arg1mode == HImode ) fsym = gen_rtx_SYMBOL_REF ( VOIDmode , concat ( helper_name , "_hw" , NULL ) ) ; else fsym = gen_rtx_SYMBOL_REF ( VOIDmode , concat ( helper_name , "_hw32" , NULL ) ) ; } else if ( msp430_use_16bit_hwmult ( ) ) fsym = gen_rtx_SYMBOL_REF ( VOIDmode , concat ( helper_name , "_hw" , NULL ) ) ; else fsym = gen_rtx_SYMBOL_REF ( VOIDmode , helper_name ) ; } else fsym = gen_rtx_SYMBOL_REF ( VOIDmode , helper_const ? helper_const : helper_name ) ; c = gen_call_value_internal ( gen_rtx_REG ( arg0mode , 12 ) , fsym , GEN_INT ( 0 ) ) ; c = emit_call_insn ( c ) ; RTL_CONST_CALL_P ( c ) = 1 ; fusage = NULL ; use_regs ( & fusage , arg1 , arg1sz ) ; if ( ! helper_const ) { if ( ! expand_mpy ) use_regs ( & fusage , arg2 , 1 ) ; else use_regs ( & fusage , arg2 , arg1sz ) ; } add_function_usage_to ( c , fusage ) ; emit_move_insn ( operands [ 0 ] , gen_rtx_REG ( arg0mode , 12 ) ) ; } </s>

The MSP430 ABI defines a number of helper functions that should be used for , for example , 32-bit shifts . This function is called to emit such a function , using the table above to optimize some cases .


<s> bool AMDGPUAsmPrinter :: doFinalization ( Module & M ) { CallGraphResourceInfo . clear ( ) ; const MCSubtargetInfo & STI = * getGlobalSTI ( ) ; if ( AMDGPU :: isGFX10Plus ( STI ) && ( STI . getTargetTriple ( ) . getOS ( ) == Triple :: AMDHSA || STI . getTargetTriple ( ) . getOS ( ) == Triple :: AMDPAL ) ) { OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; getTargetStreamer ( ) -> EmitCodeEnd ( ) ; } return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> const MCPhysReg * MipsRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const MipsSubtarget & Subtarget = MF -> getSubtarget < MipsSubtarget > ( ) ; const Function & F = MF -> getFunction ( ) ; if ( F . hasFnAttribute ( "interrupt" ) ) { if ( Subtarget . hasMips64 ( ) ) return Subtarget . hasMips64r6 ( ) ? CSR_Interrupt_64R6_SaveList : CSR_Interrupt_64_SaveList ; else return Subtarget . hasMips32r6 ( ) ? CSR_Interrupt_32R6_SaveList : CSR_Interrupt_32_SaveList ; } if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_SaveList ; if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_SaveList ; if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_SaveList ; if ( Subtarget . isFP64bit ( ) ) return CSR_O32_FP64_SaveList ; if ( Subtarget . isFPXX ( ) ) return CSR_O32_FPXX_SaveList ; return CSR_O32_SaveList ; } </s>

Mips Mips Mips Mips "interrupt" Mips Mips Mips


<s> bool PPCFrameLowering :: canUseAsEpilogue ( const MachineBasicBlock & MBB ) const { MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ; return findScratchRegister ( TmpMBB , true ) ; } </s>

Check whether or not the given MBB can be used as a epilogue for the target .


"InsertNOPsLoadStore: Erratum Fix LBR37: insert NOPs between "

"single-precision loads and the store, so the number of "

getPassName - Return a nice clean name for a pass .


<s> bool legitimate_pic_operand_p ( rtx x ) { if ( pic_address_needs_scratch ( x ) ) return false ; if ( sparc_tls_referenced_p ( x ) ) return false ; return true ; } </s>

Return true if OP is a legitimate general operand when generating PIC code . It is given that flag_pic is on and that OP satisfies CONSTANT_P or is a CONST_DOUBLE .


<s>
SDNode
*
OpenRISCDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
DebugLoc
dl
=
Node
->
getDebugLoc
(
)
;
DEBUG
(
errs
(
)
<<
"Selecting: "
)
;
DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
DEBUG
(
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
return
;
}
SDNode
*
ResNode
=
SelectCode
(
Node
)
;
DEBUG
(
errs
(
)
<<
"=> "
)
;
if
(
ResNode
==
||
ResNode
==
Node
)
DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
else
DEBUG
(
ResNode
->
dump
(
CurDAG
)
)
;
DEBUG
(
errs
(
)
<<
"\n"
)
;
return
ResNode
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

OpenRISC
OpenRISC
"Selecting: "
"\n"
"== "
"\n"
"=> "
"\n"


<s> HOST_WIDE_INT sparc_compute_frame_size ( HOST_WIDE_INT size , int leaf_function ) { HOST_WIDE_INT frame_size , apparent_frame_size ; int args_size , n_global_fp_regs = 0 ; bool save_local_in_regs_p = false ; unsigned int i ; if ( leaf_function && ! cfun -> calls_alloca ) args_size = 0 ; else args_size = crtl -> outgoing_args_size + REG_PARM_STACK_SPACE ( cfun -> decl ) ; if ( TARGET_ARCH64 ) for ( i = 0 ; i < 8 ; i ++ ) if ( save_global_or_fp_reg_p ( i , 0 ) ) n_global_fp_regs += 2 ; else for ( i = 0 ; i < 8 ; i += 2 ) if ( save_global_or_fp_reg_p ( i , 0 ) || save_global_or_fp_reg_p ( i + 1 , 0 ) ) n_global_fp_regs += 2 ; if ( TARGET_FLAT ) for ( i = 16 ; i < 32 ; i ++ ) if ( save_local_or_in_reg_p ( i , leaf_function ) ) { save_local_in_regs_p = true ; break ; } for ( i = 32 ; i < ( TARGET_V9 ? 96 : 64 ) ; i += 2 ) if ( save_global_or_fp_reg_p ( i , 0 ) || save_global_or_fp_reg_p ( i + 1 , 0 ) ) n_global_fp_regs += 2 ; if ( size == 0 && n_global_fp_regs == 0 && args_size == 0 && ! save_local_in_regs_p ) frame_size = apparent_frame_size = 0 ; else { apparent_frame_size = ( size - STARTING_FRAME_OFFSET + 7 ) & - 8 ; apparent_frame_size += n_global_fp_regs * 4 ; frame_size = apparent_frame_size + ( ( args_size + 7 ) & - 8 ) ; frame_size += FIRST_PARM_OFFSET ( cfun -> decl ) ; frame_size = SPARC_STACK_ALIGN ( frame_size ) ; } sparc_frame_size = frame_size ; sparc_apparent_frame_size = apparent_frame_size ; sparc_n_global_fp_regs = n_global_fp_regs ; sparc_save_local_in_regs_p = save_local_in_regs_p ; return frame_size ; } </s>

Compute the frame size required by the function . This function is called during the reload pass and also by sparc_expand_prologue .


<s>
bool
PatmosAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
return
true
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNo
)
;
assert
(
MO
.
isReg
(
)
&&
"unexpected inline asm memory operand"
)
;
O
<<
"[$"
<<
PatmosInstPrinter
::
getRegisterName
(
MO
.
getReg
(
)
)
<<
"]"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .

Patmos
Patmos
0
"unexpected inline asm memory operand"
"[$"
Patmos
"]"


<s> bool shouldConvertFpToSat ( unsigned Op , EVT FPVT , EVT VT ) const override { return Op != ISD :: FP_TO_UINT_SAT && isOperationLegalOrCustom ( Op , VT ) ; } </s>

Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min ( max ( fptoi ) ) saturation patterns .


<s> static void sh_symbian_mark_dllexport ( tree decl ) { const char * oldname ; char * newname ; rtx rtlname ; tree idp ; rtlname = XEXP ( DECL_RTL ( decl ) , 0 ) ; if ( GET_CODE ( rtlname ) == MEM ) rtlname = XEXP ( rtlname , 0 ) ; gcc_assert ( GET_CODE ( rtlname ) == SYMBOL_REF ) ; oldname = XSTR ( rtlname , 0 ) ; if ( sh_symbian_dllimport_name_p ( oldname ) ) { oldname += strlen ( DLL_IMPORT_PREFIX ) ; DECL_NON_ADDR_CONST_P ( decl ) = 0 ; } else if ( sh_symbian_dllexport_name_p ( oldname ) ) return ; newname = alloca ( strlen ( DLL_EXPORT_PREFIX ) + strlen ( oldname ) + 1 ) ; sprintf ( newname , "%s%s" , DLL_EXPORT_PREFIX , oldname ) ; idp = get_identifier ( newname ) ; XEXP ( DECL_RTL ( decl ) , 0 ) = gen_rtx_SYMBOL_REF ( Pmode , IDENTIFIER_POINTER ( idp ) ) ; } </s>

Mark a DECL as being dllexport 'd . Note that we override the previous setting ( e.g . : dllimport ) .


<s> SparcTargetLowering :: ConstraintType SparcTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'r' : case 'f' : case 'e' : return C_RegisterClass ; case 'I' : return C_Immediate ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


Return true if destination of IN_INSN is used as add source in OUT_INSN . Both IN_INSN and OUT_INSN are of type fmadd . Example : madd.s dst , x , y , z madd.s a , dst , b , c


<s> static ArrayRef < MCPhysReg > getAllSGPR128 ( ) { return makeArrayRef ( AMDGPU :: SGPR_128RegClass . begin ( ) , AMDGPU :: SGPR_128RegClass . getNumRegs ( ) ) ; } </s>

Return all SGPR128 which satisfy the waves per execution unit requirement of the subtarget .


<s> static void loongarch_output_mi_thunk ( FILE * file , tree thunk_fndecl ATTRIBUTE_UNUSED , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { const char * fnname = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( thunk_fndecl ) ) ; rtx this_rtx , temp1 , temp2 , fnaddr ; rtx_insn * insn ; bool use_sibcall_p ; reload_completed = 1 ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; fnaddr = XEXP ( DECL_RTL ( function ) , 0 ) ; use_sibcall_p = const_call_insn_operand ( fnaddr , Pmode ) ; temp1 = gen_rtx_REG ( Pmode , 12 ) ; temp2 = gen_rtx_REG ( Pmode , 13 ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , GP_ARG_FIRST + 1 ) ; else this_rtx = gen_rtx_REG ( Pmode , GP_ARG_FIRST ) ; if ( delta != 0 ) { rtx offset = GEN_INT ( delta ) ; if ( ! IMM12_OPERAND ( delta ) ) { loongarch_emit_move ( temp1 , offset ) ; offset = temp1 ; } emit_insn ( gen_add3_insn ( this_rtx , this_rtx , offset ) ) ; } if ( vcall_offset != 0 ) { rtx addr ; loongarch_emit_move ( temp1 , gen_rtx_MEM ( Pmode , this_rtx ) ) ; addr = loongarch_add_offset ( temp2 , temp1 , vcall_offset ) ; loongarch_emit_move ( temp1 , gen_rtx_MEM ( Pmode , addr ) ) ; emit_insn ( gen_add3_insn ( this_rtx , this_rtx , temp1 ) ) ; } if ( use_sibcall_p ) { insn = emit_call_insn ( gen_sibcall_internal ( fnaddr , const0_rtx ) ) ; SIBLING_CALL_P ( insn ) = 1 ; } else { loongarch_emit_move ( temp1 , fnaddr ) ; emit_jump_insn ( gen_indirect_jump ( temp1 ) ) ; } insn = get_insns ( ) ; split_all_insns_noflow ( ) ; shorten_branches ( insn ) ; assemble_start_function ( thunk_fndecl , fnname ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; assemble_end_function ( thunk_fndecl , fnname ) ; reload_completed = 0 ; } </s>

Implement TARGET_ASM_OUTPUT_MI_THUNK . Generate rtl rather than asm text in order to avoid duplicating too much logic from elsewhere .