<s> void tilepro_expand_epilogue ( bool sibcall_p ) { rtx reg_save_addr [ ROUND_ROBIN_SIZE ] = { NULL_RTX , NULL_RTX , NULL_RTX , NULL_RTX } ; rtx_insn * last_insn , * insn ; unsigned int which_scratch ; int offset , start_offset , regno ; rtx cfa_restores = NULL_RTX ; int fp_copy_regno = - 1 ; int next_scratch_regno = 29 ; int total_size = compute_total_frame_size ( ) ; last_insn = get_last_insn ( ) ; insn = NULL ; if ( df_regs_ever_live_p ( TILEPRO_LINK_REGNUM ) ) { insn = frame_emit_load ( TILEPRO_LINK_REGNUM , compute_frame_addr ( 0 , & next_scratch_regno ) , & cfa_restores ) ; } if ( total_size == 0 ) { if ( insn ) { RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = cfa_restores ; } goto done ; } start_offset = - crtl -> args . pretend_args_size - UNITS_PER_WORD ; offset = start_offset ; if ( frame_pointer_needed ) fp_copy_regno = next_scratch_regno -- ; which_scratch = 0 ; for ( regno = FIRST_PSEUDO_REGISTER - 1 ; regno >= 0 ; regno -- ) if ( need_to_save_reg ( regno ) ) { rtx r = reg_save_addr [ which_scratch ] ; if ( r == NULL_RTX ) { r = compute_frame_addr ( offset , & next_scratch_regno ) ; reg_save_addr [ which_scratch ] = r ; } else { int stride = ROUND_ROBIN_SIZE * - UNITS_PER_WORD ; rtx p = gen_rtx_PLUS ( Pmode , r , GEN_INT ( stride ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , r , p ) ) ; } if ( fp_copy_regno >= 0 && regno == HARD_FRAME_POINTER_REGNUM ) frame_emit_load ( fp_copy_regno , r , NULL ) ; else frame_emit_load ( regno , r , & cfa_restores ) ; offset -= UNITS_PER_WORD ; which_scratch = ( which_scratch + 1 ) % ROUND_ROBIN_SIZE ; } if ( ! tilepro_current_function_is_leaf ( ) ) cfa_restores = alloc_reg_note ( REG_CFA_RESTORE , stack_pointer_rtx , cfa_restores ) ; emit_insn ( gen_blockage ( ) ) ; if ( frame_pointer_needed ) { insn = emit_insn ( gen_sp_restore ( stack_pointer_rtx , hard_frame_pointer_rtx ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = cfa_restores ; add_reg_note ( insn , REG_CFA_DEF_CFA , stack_pointer_rtx ) ; } else { insn = emit_sp_adjust ( total_size , & next_scratch_regno , true , cfa_restores ) ; } if ( crtl -> calls_eh_return ) emit_insn ( gen_sp_adjust ( stack_pointer_rtx , stack_pointer_rtx , EH_RETURN_STACKADJ_RTX ) ) ; if ( frame_pointer_needed ) { insn = emit_move_insn ( hard_frame_pointer_rtx , gen_rtx_REG ( Pmode , fp_copy_regno ) ) ; add_reg_note ( insn , REG_CFA_RESTORE , hard_frame_pointer_rtx ) ; } if ( flag_pic ) { emit_use ( cfun -> machine -> text_label_rtx ) ; emit_use ( cfun -> machine -> got_rtx ) ; } done : if ( ! sibcall_p ) { emit_jump_insn ( gen__return ( ) ) ; } else { emit_use ( gen_rtx_REG ( Pmode , TILEPRO_LINK_REGNUM ) ) ; } for ( ; last_insn != NULL_RTX ; last_insn = next_insn ( last_insn ) ) RTX_FRAME_RELATED_P ( last_insn ) = 1 ; } </s>

Implement the epilogue and sibcall_epilogue patterns . SIBCALL_P is true for a sibcall_epilogue pattern , and false for an epilogue pattern .


<s> bool MipsLegalizerInfo :: legalizeCustom ( MachineInstr & MI , MachineRegisterInfo & MRI , MachineIRBuilder & MIRBuilder , GISelChangeObserver & Observer ) const { using namespace TargetOpcode ; MIRBuilder . setInstr ( MI ) ; return false ; } </s>

Called for instructions with the Custom LegalizationAction .


<s> static void emit_push_byte ( unsigned regno , bool frame_related_p ) { rtx mem , reg ; rtx_insn * insn ; mem = gen_rtx_POST_DEC ( HImode , stack_pointer_rtx ) ; mem = gen_frame_mem ( QImode , mem ) ; reg = gen_rtx_REG ( QImode , regno ) ; insn = emit_insn ( gen_rtx_SET ( mem , reg ) ) ; if ( frame_related_p ) RTX_FRAME_RELATED_P ( insn ) = 1 ; cfun -> machine -> stack_usage ++ ; } </s>

Helper for expand_prologue . Emit a push of a byte register .


<s>
static
int
crx_address_cost
(
rtx
addr
)
{
enum
crx_addrtype
addrtype
;
struct
crx_address
address
;
int
cost
=
2
;
addrtype
=
crx_decompose_address
(
addr
,
&
address
)
;
gcc_assert
(
addrtype
!=
CRX_INVALID
)
;
if
(
addrtype
==
CRX_ABSOLUTE
)
cost
+=
2
;
if
(
addrtype
==
CRX_POST_INC
)
cost
-=
2
;
if
(
address
.
base
)
cost
++
;
if
(
address
.
index
&&
address
.
scale
==
1
)
cost
+=
5
;
if
(
address
.
disp
&&
!
INT_CST4
(
INTVAL
(
address
.
disp
)
)
)
cost
+=
2
;
if
(
TARGET_DEBUG_ADDR
)
{
fprintf
(
stderr
,
"\n======\nTARGET_ADDRESS_COST = %d\n"
,
cost
)
;
debug_rtx
(
addr
)
;
}
return
cost
;
}
</s>


<s> SDValue X86TargetLowering :: getPICJumpTableRelocBase ( SDValue Table , SelectionDAG & DAG ) const { if ( ! Subtarget -> is64Bit ( ) ) return DAG . getNode ( X86ISD :: GlobalBaseReg , DebugLoc :: getUnknownLoc ( ) , getPointerTy ( ) ) ; return Table ; } </s>

Returns relocation base for the given PIC jumptable .


<s> const MCPhysReg * PPCRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const PPCSubtarget & Subtarget = MF -> getSubtarget < PPCSubtarget > ( ) ; if ( MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: AnyReg ) { if ( Subtarget . hasVSX ( ) ) return CSR_64_AllRegs_VSX_SaveList ; if ( Subtarget . hasAltivec ( ) ) return CSR_64_AllRegs_Altivec_SaveList ; return CSR_64_AllRegs_SaveList ; } if ( Subtarget . isDarwinABI ( ) ) return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_SaveList : CSR_Darwin64_SaveList ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_SaveList : CSR_Darwin32_SaveList ) ; if ( TM . isPPC64 ( ) && MF -> getInfo < PPCFunctionInfo > ( ) -> isSplitCSR ( ) ) return CSR_SRV464_TLS_PE_SaveList ; bool SaveR2 = MF -> getRegInfo ( ) . isAllocatable ( PPC :: X2 ) ; return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? ( SaveR2 ? CSR_SVR464_R2_Altivec_SaveList : CSR_SVR464_Altivec_SaveList ) : ( SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList ) ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR432_Altivec_SaveList : CSR_SVR432_SaveList ) ; } </s>

PowerPC PPC PPC PPC PPC PPC PPC PPC::X2 PPC


<s> bool isShift ( ) const { if ( ! isShiftOrExtend ( ) ) return false ; if ( ShiftExtend . ShiftType != SHKind ) return false ; return is64Bit ? ShiftExtend . Amount <= 63 : ShiftExtend . Amount <= 31 ; } </s>

Determine if the Opcode is one of the shift instructions .


<s> bool HexagonInstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( MI . isDebugValue ( ) ) return false ; if ( MI . isCall ( ) ) { for ( auto I : MBB -> successors ( ) ) if ( I -> isEHPad ( ) ) return true ; } if ( MI . getOpcode ( ) == Hexagon :: CALLv3nr ) return true ; if ( MI . getDesc ( ) . isTerminator ( ) || MI . isPosition ( ) ) return true ; if ( MI . isInlineAsm ( ) && ! ScheduleInlineAsm ) return true ; return false ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> bool ARMPassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge ) PM . add ( createGlobalMergePass ( TM -> getTargetLowering ( ) ) ) ; return false ; } </s>


<s> static bool has_immediate ( rtx insn ) { int num_imm_operand ; int num_imm32_operand ; int num_imm64_operand ; if ( insn ) return get_num_immediates ( insn , & num_imm_operand , & num_imm32_operand , & num_imm64_operand ) ; return false ; } </s>

This function indicates if an operand of an instruction is an immediate .


<s> static bool avr_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { return ( ( frame_pointer_needed && to == FRAME_POINTER_REGNUM ) || ! frame_pointer_needed ) ; } </s>

Return true if register FROM can be eliminated via register TO .


<s> static void ATTRIBUTE_UNUSED x86_64_elf_unique_section ( tree decl , int reloc ) { if ( ix86_in_large_data_p ( decl ) ) { const char * prefix = NULL ; bool one_only = DECL_COMDAT_GROUP ( decl ) && ! HAVE_COMDAT_GROUP ; switch ( categorize_decl_for_section ( decl , reloc ) ) { case SECCAT_DATA : case SECCAT_DATA_REL : case SECCAT_DATA_REL_LOCAL : case SECCAT_DATA_REL_RO : case SECCAT_DATA_REL_RO_LOCAL : prefix = one_only ? ".ld" : ".ldata" ; break ; case SECCAT_BSS : prefix = one_only ? ".lb" : ".lbss" ; break ; case SECCAT_RODATA : case SECCAT_RODATA_MERGE_STR : case SECCAT_RODATA_MERGE_STR_INIT : case SECCAT_RODATA_MERGE_CONST : prefix = one_only ? ".lr" : ".lrodata" ; break ; case SECCAT_SRODATA : case SECCAT_SDATA : case SECCAT_SBSS : gcc_unreachable ( ) ; case SECCAT_TEXT : case SECCAT_TDATA : case SECCAT_TBSS : break ; } if ( prefix ) { const char * name , * linkonce ; char * string ; name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; name = targetm . strip_name_encoding ( name ) ; linkonce = one_only ? ".gnu.linkonce" : "" ; string = ACONCAT ( ( linkonce , prefix , "." , name , NULL ) ) ; set_decl_section_name ( decl , string ) ; return ; } } default_unique_section ( decl , reloc ) ; } </s>

Build up a unique section name , expressed as a STRING_CST node , and assign it to DECL_SECTION_NAME ( decl ) . RELOC indicates whether the initial value of EXP requires link-time relocations .


<s> bool HexagonInstrInfo :: isComplex ( const MachineInstr & MI ) const { return ! isTC1 ( MI ) && ! isTC2Early ( MI ) && ! MI . getDesc ( ) . mayLoad ( ) && ! MI . getDesc ( ) . mayStore ( ) && MI . getDesc ( ) . getOpcode ( ) != Hexagon :: S2_allocframe && MI . getDesc ( ) . getOpcode ( ) != Hexagon :: L2_deallocframe && ! isMemOp ( MI ) && ! MI . isBranch ( ) && ! MI . isReturn ( ) && ! MI . isCall ( ) ; } </s>

Return whether the location is computed on the expression stack , meaning it can not be a simple register location .


<s> virtual SMLoc getEndLoc ( ) const LLVM_OVERRIDE { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s>
void
MipsRegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
MachineInstr
&
MI
=
*
II
;
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
LLVM_DEBUG
(
errs
(
)
<<
"\nFunction : "
<<
MF
.
getName
(
)
<<
"\n"
;
errs
(
)
<<
"<--------->\n"
<<
MI
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
uint64_t
stackSize
=
MF
.
getFrameInfo
(
)
.
getStackSize
(
)
;
int64_t
spOffset
=
MF
.
getFrameInfo
(
)
.
getObjectOffset
(
FrameIndex
)
;
LLVM_DEBUG
(
errs
(
)
<<
"FrameIndex : "
<<
FrameIndex
<<
"\n"
<<
"spOffset   : "
<<
spOffset
<<
"\n"
<<
"stackSize  : "
<<
stackSize
<<
"\n"
<<
"alignment  : "
<<
DebugStr
(
MF
.
getFrameInfo
(
)
.
getObjectAlign
(
FrameIndex
)
)
<<
"\n"
)
;
eliminateFI
(
MI
,
FIOperandNum
,
FrameIndex
,
stackSize
,
spOffset
,
RS
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .

Mips
Mips
"\nFunction : "
"\n"
"<--------->\n"
"FrameIndex : "
"\n"
"spOffset   : "
"\n"
"stackSize  : "
"\n"
"alignment  : "
"\n"


<s> void X86PassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( new X86ExecutionDomainFix ( ) ) ; addPass ( createBreakFalseDeps ( ) ) ; } addPass ( createX86IndirectBranchTrackingPass ( ) ) ; addPass ( createX86IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86FixupBWInsts ( ) ) ; addPass ( createX86PadShortFunctions ( ) ) ; addPass ( createX86FixupLEAs ( ) ) ; } addPass ( createX86EvexToVexInsts ( ) ) ; addPass ( createX86DiscriminateMemOpsPass ( ) ) ; addPass ( createX86InsertPrefetchPass ( ) ) ; addPass ( createX86InsertX87waitPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool SHUXIFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; SHUXIMachineFunctionInfo * MFI = MF . getInfo < SHUXIMachineFunctionInfo > ( ) ; MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( SHUXI :: PUSH ) ) . addReg ( Reg , RegState :: Kill ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s>
SDValue
PTXTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
if
(
isVarArg
)
llvm_unreachable
(
"PTX does not support varargs"
)
;
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
PTXMachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
PTXMachineFunctionInfo
>
(
)
;
lower_argument_func
lower_argument
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
break
;
case
CallingConv
::
PTX_Kernel
:
MFI
->
setKernel
(
)
;
lower_argument
=
lower_kernel_argument
;
break
;
case
CallingConv
::
PTX_Device
:
MFI
->
setKernel
(
false
)
;
lower_argument
=
lower_device_argument
;
break
;
}
for
(
struct
argmap_entry
*
i
=
argmap
,
*
e
=
argmap
+
array_lengthof
(
argmap
)
;
i
!=
e
;
++
i
)
i
->
reset
(
)
;
for
(
int
i
=
0
,
e
=
Ins
.
size
(
)
;
i
!=
e
;
++
i
)
{
MVT
::
SimpleValueType
VT
=
Ins
[
i
]
.
VT
.
SimpleTy
;
struct
argmap_entry
*
entry
=
std
::
find
(
argmap
,
argmap
+
array_lengthof
(
argmap
)
,
VT
)
;
if
(
entry
==
argmap
+
array_lengthof
(
argmap
)
)
llvm_unreachable
(
"Type of argument is not supported"
)
;
unsigned
reg
;
SDValue
arg
=
lower_argument
(
i
,
Chain
,
dl
,
VT
,
entry
,
DAG
,
&
reg
)
;
InVals
.
push_back
(
arg
)
;
if
(
!
MFI
->
isDoneAddArg
(
)
)
MFI
->
addArgReg
(
reg
)
;
}
if
(
!
MFI
->
isDoneAddArg
(
)
)
MFI
->
doneAddArg
(
)
;
return
Chain
;
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .

PTX
PTX
ISD::InputArg
"PTX does not support varargs"
PTX
PTX
"Unsupported calling convention"
PTX
PTX
0
MVT::SimpleValueType
"Type of argument is not supported"


<s> void AlphaInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; if ( RC == Alpha :: F4RCRegisterClass ) BuildMI ( MBB , MI , DL , get ( Alpha :: LDS ) , DestReg ) . addFrameIndex ( FrameIdx ) . addReg ( Alpha :: F31 ) ; else if ( RC == Alpha :: F8RCRegisterClass ) BuildMI ( MBB , MI , DL , get ( Alpha :: LDT ) , DestReg ) . addFrameIndex ( FrameIdx ) . addReg ( Alpha :: F31 ) ; else if ( RC == Alpha :: GPRCRegisterClass ) BuildMI ( MBB , MI , DL , get ( Alpha :: LDQ ) , DestReg ) . addFrameIndex ( FrameIdx ) . addReg ( Alpha :: F31 ) ; else abort ( ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override { return createPPCPostMachineScheduler ( C ) ; } </s>

Similar to createMachineScheduler but used when postRA machine scheduling is enabled .


<s> static rtx rs6000_emit_stack_reset ( rs6000_stack_t * info , rtx frame_reg_rtx , HOST_WIDE_INT frame_off , unsigned updt_regno ) { rtx updt_reg_rtx ; if ( DEFAULT_ABI == ABI_V4 || ( TARGET_SPE_ABI && info -> spe_64bit_regs_used != 0 && info -> first_gp_reg_save != 32 ) ) rs6000_emit_stack_tie ( frame_reg_rtx , frame_pointer_needed ) ; updt_reg_rtx = gen_rtx_REG ( Pmode , updt_regno ) ; if ( frame_off != 0 ) return emit_insn ( gen_add3_insn ( updt_reg_rtx , frame_reg_rtx , GEN_INT ( frame_off ) ) ) ; else if ( REGNO ( frame_reg_rtx ) != updt_regno ) return emit_move_insn ( updt_reg_rtx , frame_reg_rtx ) ; return NULL_RTX ; } </s>

Emit a sequence of insns , including a stack tie if needed , for resetting the stack pointer . If UPDT_REGNO is not 1 , then do n't reset the stack pointer , but move the base of the frame into reg UPDT_REGNO for use by out-of-line register restore routines .


Decide how much space to reserve for callee-save target registers in case target register allocation wants to use them . LIVE_REGS_MASK is the register mask calculated by calc_live_regs .


<s> bool Z80oldInstrInfo :: isReallyTriviallyReMaterializable ( const MachineInstr & MI , AliasAnalysis * AA ) const { switch ( MI . getOpcode ( ) ) { case Z80old :: LD8r0 : return true ; } return false ; } </s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> int frv_frame_pointer_required ( void ) { if ( ! TARGET_LINKED_FP ) return ! current_function_sp_is_unchanging ; if ( ! current_function_is_leaf ) return TRUE ; if ( get_frame_size ( ) != 0 ) return TRUE ; if ( cfun -> stdarg ) return TRUE ; if ( ! current_function_sp_is_unchanging ) return TRUE ; if ( ! TARGET_FDPIC && flag_pic && cfun -> uses_pic_offset_table ) return TRUE ; if ( profile_flag ) return TRUE ; if ( cfun -> machine -> frame_needed ) return TRUE ; return FALSE ; } </s>

On frv , create a frame whenever we need to create stack .


<s> FastISel * X86TargetLowering :: createFastISel ( MachineFunction & mf , MachineModuleInfo * mmo , DwarfWriter * dw , DenseMap < const Value * , unsigned > & vm , DenseMap < const BasicBlock * , MachineBasicBlock * > & bm , DenseMap < const AllocaInst * , int > & am , SmallSet < Instruction * , 8 > & cil ) { return X86 :: createFastISel ( mf , mmo , dw , vm , bm , am , cil ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


"frame pointer should not have been eliminated"

"SecondSPAdjustAmount should be greater than zero"


<s> bool SIDebuggerInsertNops :: runOnMachineFunction ( MachineFunction & MF ) { const AMDGPUSubtarget & ST = MF . getSubtarget < AMDGPUSubtarget > ( ) ; if ( ! ST . debuggerInsertNops ( ) ) return false ; if ( ! MF . getMMI ( ) . hasDebugInfo ( ) ) return false ; const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; DenseSet < unsigned > NopInserted ; for ( auto & MBB : MF ) { for ( auto MI = MBB . begin ( ) ; MI != MBB . end ( ) ; ++ MI ) { if ( MI -> isDebugValue ( ) || ! MI -> getDebugLoc ( ) ) continue ; auto DL = MI -> getDebugLoc ( ) ; if ( NopInserted . find ( DL . getLine ( ) ) == NopInserted . end ( ) ) { BuildMI ( MBB , * MI , DL , TII -> get ( AMDGPU :: S_NOP ) ) . addImm ( 0 ) ; NopInserted . insert ( DL . getLine ( ) ) ; } } } return true ; } </s>

runOnMachineFunction - Emit the function body .

AMDGPU SI AMDGPU AMDGPU SI SI AMDGPU::S_NOP 0


"llvm does not support 'Q', 'R', and 'H' modifiers!"

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> const uint32_t * AArch64RegisterInfo :: getCallPreservedMask ( CallingConv :: ID ) const { return CSR_PCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> VariantKind getKind ( ) const { return Kind ; } </s>


"register number must be a compile-time constant.  "

Returns true if the operands [ opno ] is a valid compile-time constant to be used as register number in the code for builtins . Else it flags an error and returns false .


Output return instrumentation for current function if needed .


<s> static bool sh_cannot_modify_jumps_p ( ) { return ( TARGET_SHMEDIA && ( reload_in_progress || reload_completed ) ) ; } </s>

SHmedia requires registers for branches , so we ca n't generate new branches past reload .


<s> bool ARM64TargetLowering :: isLegalICmpImmediate ( int64_t Immed ) const { if ( Immed < 0 ) Immed *= - 1 ; return isLegalAddImmediate ( Immed ) ; } </s>

Return true if the specified immediate is legal icmp immediate , that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register .


<s> unsigned AVRMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; if ( MO . isDFPImm ( ) ) return static_cast < unsigned > ( bit_cast < double > ( MO . getDFPImm ( ) ) ) ; assert ( MO . isExpr ( ) ) ; return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> bool SITargetLowering :: enableAggressiveFMAFusion ( LLT Ty ) const { return true ; } </s>

Return true if target always benefits from combining into FMA for a given value type .


<s> StringRef NamedImmMapper :: toString ( uint32_t Value , bool & Valid ) const { for ( unsigned i = 0 ; i < NumPairs ; ++ i ) { if ( Pairs [ i ] . Value == Value ) { Valid = true ; return Pairs [ i ] . Name ; } } Valid = false ; return StringRef ( ) ; } </s>

Convert to a decimal representation in a string .


<s> FastISel * X86 :: createFastISel ( FunctionLoweringInfo & funcInfo ) { return new X86FastISel ( funcInfo ) ; } </s>


<s> bool PPCFrameLowering :: canUseAsPrologue ( const MachineBasicBlock & MBB ) const { MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ; return findScratchRegister ( TmpMBB , false , nullptr ) ; } </s>

Check whether or not the given MBB can be used as a prologue for the target .


<s> void emitFill ( const MCExpr & NumBytes , uint64_t FillValue , SMLoc Loc ) override { EmitDataMappingSymbol ( ) ; MCObjectStreamer :: emitFill ( NumBytes , FillValue , Loc ) ; } </s>

Emit Size bytes worth of the value specified by FillValue .


<s> unsigned AArch64RegisterBankInfo :: copyCost ( const RegisterBank & A , const RegisterBank & B ) const { return 0 ; } </s>

Get the cost of a copy from B to A , or put differently , get the cost of A = COPY B .


"feature combination from rest of module.\n"

This virtual method can be overridden by targets that want to emit something at the start of their file .


<s> bool SITypeRewriter :: runOnFunction ( Function & F ) { Attribute A = F . getFnAttribute ( "ShaderType" ) ; unsigned ShaderType = ShaderType :: COMPUTE ; if ( A . isStringAttribute ( ) ) { StringRef Str = A . getValueAsString ( ) ; Str . getAsInteger ( 0 , ShaderType ) ; } if ( ShaderType == ShaderType :: COMPUTE ) return false ; visit ( F ) ; visit ( F ) ; return false ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s>
unsigned
SHUXIInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
I
->
getOpcode
(
)
!=
SHUXI
::
JMP
&&
I
->
getOpcode
(
)
!=
SHUXI
::
JCC
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .

SHUXI
SHUXI
"code size not handled"
0
SHUXI::JMP
SHUXI::JCC


<s> bool X86InstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == X86 :: ENDBR64 || Opcode == X86 :: ENDBR32 || Opcode == X86 :: LDTILECFG ) return true ; return TargetInstrInfo :: isSchedulingBoundary ( MI , MBB , MF ) ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> SDValue DLXTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> bool VETargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { CCAssignFn * RetCC = getReturnCC ( CallConv ) ; SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> PPCSubtarget :: PPCSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const PPCTargetMachine & TM ) : PPCGenSubtargetInfo ( TT , CPU , FS ) , TargetTriple ( TT ) , IsPPC64 ( TargetTriple . getArch ( ) == Triple :: ppc64 || TargetTriple . getArch ( ) == Triple :: ppc64le ) , TM ( TM ) , FrameLowering ( initializeSubtargetDependencies ( CPU , FS ) ) , InstrInfo ( * this ) , TLInfo ( TM , * this ) , TSInfo ( TM . getDataLayout ( ) ) { } </s>

This constructor initializes the data members to match that of the specified triple .


<s>
bool
CSKYAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
const
char
*
ExtraCode
,
raw_ostream
&
OS
)
{
if
(
!
ExtraCode
)
{
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNo
)
;
if
(
!
MO
.
isReg
(
)
)
return
true
;
OS
<<
"("
<<
CSKYInstPrinter
::
getRegisterName
(
MO
.
getReg
(
)
)
<<
", 0)"
;
return
false
;
}
return
AsmPrinter
::
PrintAsmMemoryOperand
(
MI
,
OpNo
,
ExtraCode
,
OS
)
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveAArch64CodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } if ( getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) { this -> Options . TrapUnreachable = true ; } if ( this -> Options . TLSSize == 0 ) this -> Options . TLSSize = 24 ; if ( ( getCodeModel ( ) == CodeModel :: Small || getCodeModel ( ) == CodeModel :: Kernel ) && this -> Options . TLSSize > 32 ) this -> Options . TLSSize = 32 ; else if ( getCodeModel ( ) == CodeModel :: Tiny && this -> Options . TLSSize > 24 ) this -> Options . TLSSize = 24 ; if ( getOptLevel ( ) <= EnableGlobalISelAtO && TT . getArch ( ) != Triple :: aarch64_32 && ! ( getCodeModel ( ) == CodeModel :: Large && TT . isOSBinFormatMachO ( ) ) ) { setGlobalISel ( true ) ; setGlobalISelAbort ( GlobalISelAbortMode :: Disable ) ; } setMachineOutliner ( true ) ; setSupportsDefaultOutlining ( true ) ; setSupportsDebugEntryValues ( true ) ; } </s>


<s> int zero_and_one ( rtx operand1 , rtx operand2 ) { return GET_CODE ( operand1 ) == CONST_INT && GET_CODE ( operand2 ) == CONST_INT && ( ( ( INTVAL ( operand1 ) == 0 ) && ( INTVAL ( operand2 ) == 1 ) ) || ( ( INTVAL ( operand1 ) == 1 ) && ( INTVAL ( operand2 ) == 0 ) ) ) ; } </s>

Return true if the operands are the constants 0 and 1 .


<s> bool X86RegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , unsigned Reg , int & FrameIdx ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; if ( Reg == FramePtr && TFI -> hasFP ( MF ) ) { FrameIdx = MF . getFrameInfo ( ) -> getObjectIndexBegin ( ) ; return true ; } return false ; } </s>

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Patmos Delay Slot Killer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static int ix86_reloc_rw_mask ( void ) { return ( flag_pic || ! ix86_direct_extern_access ) ? 3 : 0 ; } </s>

If flag_pic or ix86_direct_extern_access is false , then neither local nor global relocs should be placed in readonly memory .


<s> void emitTagType ( const MCSymbolWasm * ) override { } </s>


"vector argument passed to unprototyped function"

The VX ABI differs for vararg functions . Therefore we need the prototype of the callee to be available when passing vector type values .


<s> static rtx sh_struct_value_rtx ( tree fndecl , int incoming ATTRIBUTE_UNUSED ) { if ( TARGET_HITACHI || sh_attr_renesas_p ( fndecl ) ) return 0 ; return gen_rtx_REG ( Pmode , 2 ) ; } </s>

The Renesas calling convention does n't quite fit into this scheme since the address is passed like an invisible argument , but one that is always passed in memory .


<s> static rtx_insn * alphaev4_next_group ( rtx_insn * insn , int * pin_use , int * plen ) { int len , in_use ; len = in_use = 0 ; if ( ! INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == CLOBBER || GET_CODE ( PATTERN ( insn ) ) == USE ) goto next_and_done ; while ( 1 ) { enum alphaev4_pipe pipe ; pipe = alphaev4_insn_pipe ( insn ) ; switch ( pipe ) { case EV4_STOP : if ( in_use ) goto done ; if ( recog_memoized ( insn ) < 0 ) len = - 1 ; else len = get_attr_length ( insn ) ; goto next_and_done ; case EV4_IBX : if ( in_use & EV4_IB0 ) { if ( in_use & EV4_IB1 ) goto done ; in_use |= EV4_IB1 ; } else in_use |= EV4_IB0 | EV4_IBX ; break ; case EV4_IB0 : if ( in_use & EV4_IB0 ) { if ( ! ( in_use & EV4_IBX ) || ( in_use & EV4_IB1 ) ) goto done ; in_use |= EV4_IB1 ; } in_use |= EV4_IB0 ; break ; case EV4_IB1 : if ( in_use & EV4_IB1 ) goto done ; in_use |= EV4_IB1 ; break ; default : gcc_unreachable ( ) ; } len += 4 ; if ( JUMP_P ( insn ) ) goto next_and_done ; next : insn = next_nonnote_insn ( insn ) ; if ( ! insn || ! INSN_P ( insn ) ) goto done ; if ( GET_MODE ( insn ) == TImode ) goto done ; if ( GET_CODE ( insn ) == CLOBBER || GET_CODE ( insn ) == USE ) goto next ; } next_and_done : insn = next_nonnote_insn ( insn ) ; done : * plen = len ; * pin_use = in_use ; return insn ; } </s>

IN_USE is a mask of the slots currently filled within the insn group . The mask bits come from alphaev4_pipe above . If EV4_IBX is set , then the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1 . LEN is , of course , the length of the group in bytes .


<s>
const
char
*
output_return
(
rtx
insn
)
{
if
(
sparc_leaf_function_p
)
{
gcc_assert
(
!
current_function_calls_eh_return
)
;
return
"jmp\t%%o7+%)%#"
;
}
else
{
if
(
current_function_calls_eh_return
)
{
gcc_assert
(
!
final_sequence
)
;
if
(
!
flag_delayed_branch
)
fputs
(
"\tadd\t%fp, %g1, %fp\n"
,
asm_out_file
)
;
if
(
TARGET_V9
)
fputs
(
"\treturn\t%i7+8\n"
,
asm_out_file
)
;
else
fputs
(
"\trestore\n\tjmp\t%o7+8\n"
,
asm_out_file
)
;
if
(
flag_delayed_branch
)
fputs
(
"\t add\t%sp, %g1, %sp\n"
,
asm_out_file
)
;
else
fputs
(
"\t nop\n"
,
asm_out_file
)
;
}
else
if
(
final_sequence
)
{
rtx
delay
,
pat
;
delay
=
NEXT_INSN
(
insn
)
;
gcc_assert
(
delay
)
;
pat
=
PATTERN
(
delay
)
;
if
(
TARGET_V9
&&
!
epilogue_renumber
(
&
pat
,
1
)
)
{
epilogue_renumber
(
&
pat
,
0
)
;
return
"return\t%%i7+%)%#"
;
}
else
{
output_asm_insn
(
"jmp\t%%i7+%)"
,
)
;
output_restore
(
pat
)
;
PATTERN
(
delay
)
=
gen_blockage
(
)
;
INSN_CODE
(
delay
)
=
1
;
}
}
else
{
if
(
TARGET_V9
)
return
"return\t%%i7+%)\n\t nop"
;
else
if
(
flag_delayed_branch
)
return
"jmp\t%%i7+%)\n\t restore"
;
else
return
"restore\n\tjmp\t%%o7+%)\n\t nop"
;
}
}
return
""
;
}
</s>


<s> const MipsGNULDBackend & getTarget ( ) const { return m_Target ; } </s>

getTarget - Return the target machine this machine code is compiled with


<s> Optional < RegImmPair > ARMBaseInstrInfo :: isAddImmediate ( const MachineInstr & MI , Register Reg ) const { int Sign = 1 ; unsigned Opcode = MI . getOpcode ( ) ; int64_t Offset = 0 ; if ( Reg != MI . getOperand ( 0 ) . getReg ( ) ) return None ; if ( Opcode == ARM :: SUBri ) Sign = - 1 ; else if ( Opcode != ARM :: ADDri ) return None ; if ( ! MI . getOperand ( 0 ) . isReg ( ) || ! MI . getOperand ( 1 ) . isReg ( ) || ! MI . getOperand ( 2 ) . isImm ( ) ) return None ; Offset = MI . getOperand ( 2 ) . getImm ( ) * Sign ; return RegImmPair { MI . getOperand ( 1 ) . getReg ( ) , Offset } ; } </s>

If the specific machine instruction is an instruction that adds an immediate value and a register , and stores the result in the given register Reg , return a pair of the source register and the offset which has been added .


<s> bool AArch64InstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF ) const { return MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoRedZone ) && ! MF . getFunction ( ) -> hasAddressTaken ( ) ; } </s>

Return true if the function can safely be outlined from .


<s> void X86FrameLowering :: emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , int64_t NumBytes , bool InEpilogue ) const { bool isSub = NumBytes < 0 ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; uint64_t Chunk = ( 1LL << 31 ) - 1 ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { if ( Offset > Chunk ) { unsigned Reg = 0 ; if ( isSub && ! isEAXLiveIn ( MBB ) ) Reg = ( unsigned ) ( Is64Bit ? X86 :: RAX : X86 :: EAX ) ; else Reg = findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { unsigned Opc = Is64Bit ? X86 :: MOV64ri : X86 :: MOV32ri ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , Reg ) . addImm ( Offset ) ; Opc = isSub ? getSUBrrOpcode ( Is64Bit ) : getADDrrOpcode ( Is64Bit ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addReg ( Reg ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; Offset = 0 ; continue ; } } uint64_t ThisVal = std :: min ( Offset , Chunk ) ; if ( ThisVal == ( Is64Bit ? 8 : 4 ) ) { unsigned Reg = isSub ? ( unsigned ) ( Is64Bit ? X86 :: RAX : X86 :: EAX ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { unsigned Opc = isSub ? ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) : ( Is64Bit ? X86 :: POP64r : X86 :: POP32r ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ; if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; else MI -> setFlag ( MachineInstr :: FrameDestroy ) ; Offset -= ThisVal ; continue ; } } MachineInstrBuilder MI = BuildStackAdjustment ( MBB , MBBI , DL , isSub ? - ThisVal : ThisVal , InEpilogue ) ; if ( isSub ) MI . setMIFlag ( MachineInstr :: FrameSetup ) ; else MI . setMIFlag ( MachineInstr :: FrameDestroy ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> void xtensa_split_DI_reg_imm ( rtx * operands ) { rtx lowpart , highpart ; if ( WORDS_BIG_ENDIAN ) split_double ( operands [ 1 ] , & highpart , & lowpart ) ; else split_double ( operands [ 1 ] , & lowpart , & highpart ) ; operands [ 3 ] = highpart ; operands [ 2 ] = gen_highpart ( SImode , operands [ 0 ] ) ; operands [ 1 ] = lowpart ; operands [ 0 ] = gen_lowpart ( SImode , operands [ 0 ] ) ; } </s>

Split a DImode pair of reg ( operand [ 0 ] ) and const_int ( operand [ 1 ] ) into two SImode pairs , the low-part ( operands [ 0 ] and [ 1 ] ) and the high-part ( operands [ 2 ] and [ 3 ] ) .


"NVPTX DAG->DAG Pattern Instruction Selection"


<s> static tree ix86_stack_protect_fail ( void ) { return TARGET_64BIT ? default_external_stack_protect_fail ( ) : default_hidden_stack_protect_fail ( ) ; } </s>

For 32-bit code we can save PIC register setup by using __stack_chk_fail_local hidden function instead of calling __stack_chk_fail directly . 64-bit code does n't need to setup any PIC register , so it is better to call __stack_chk_fail directly .


<s> static rtx_insn * find_next_cycle_insn ( rtx_insn * insn , int clock ) { rtx_insn * t = insn ; if ( GET_MODE ( t ) == TImode ) t = next_real_insn ( t ) ; while ( t && GET_MODE ( t ) != TImode ) t = next_real_insn ( t ) ; if ( t && insn_get_clock ( t ) == clock ) return t ; return NULL ; } </s>

Scan forwards from INSN until we find the next insn that has mode TImode ( indicating it starts a new cycle ) , and occurs in cycle CLOCK . Return it if we find such an insn , NULL_RTX otherwise .


<s> bool function_instance :: reads_global_state_p ( ) const { unsigned int flags = call_properties ( ) ; if ( flags & CP_READ_FPCR ) return true ; return flags & ( CP_READ_MEMORY | CP_READ_FFR ) ; } </s>

Return true if calls to the function could read some form of global state .


<s> static void mips_expand_vi_general ( machine_mode vmode , machine_mode imode , unsigned nelt , unsigned nvar , rtx target , rtx vals ) { rtx mem = assign_stack_temp ( vmode , GET_MODE_SIZE ( vmode ) ) ; unsigned int i , isize = GET_MODE_SIZE ( imode ) ; if ( nvar < nelt ) mips_expand_vi_constant ( vmode , nelt , mem , vals ) ; for ( i = 0 ; i < nelt ; ++ i ) { rtx x = XVECEXP ( vals , 0 , i ) ; if ( ! mips_constant_elt_p ( x ) ) emit_move_insn ( adjust_address ( mem , imode , i * isize ) , x ) ; } emit_move_insn ( target , mem ) ; } </s>

A subroutine of mips_expand_vec_init , expand anything via memory .


<s> bool RISCVPassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( ) ) ; return false ; } </s>

This method should install a ( global ) instruction selector pass , which converts possibly generic instructions to fully target-specific instructions , thereby constraining all generic virtual registers to register classes .


<s> static void visium_va_start ( tree valist , rtx nextarg ATTRIBUTE_UNUSED ) { const CUMULATIVE_ARGS * ca = & crtl -> args . info ; int gp_saved = MAX_ARGS_IN_GP_REGISTERS - ca -> grcount ; int fp_saved = ( TARGET_FPU ? MAX_ARGS_IN_FP_REGISTERS - ca -> frcount : 0 ) ; int named_stack_size = ca -> stack_words * UNITS_PER_WORD , offset ; tree f_ovfl , f_gbase , f_fbase , f_gbytes , f_fbytes ; tree ovfl , gbase , gbytes , fbase , fbytes , t ; f_ovfl = TYPE_FIELDS ( va_list_type_node ) ; f_gbase = TREE_CHAIN ( f_ovfl ) ; f_fbase = TREE_CHAIN ( f_gbase ) ; f_gbytes = TREE_CHAIN ( f_fbase ) ; f_fbytes = TREE_CHAIN ( f_gbytes ) ; ovfl = build3 ( COMPONENT_REF , TREE_TYPE ( f_ovfl ) , valist , f_ovfl , NULL_TREE ) ; gbase = build3 ( COMPONENT_REF , TREE_TYPE ( f_gbase ) , valist , f_gbase , NULL_TREE ) ; fbase = build3 ( COMPONENT_REF , TREE_TYPE ( f_fbase ) , valist , f_fbase , NULL_TREE ) ; gbytes = build3 ( COMPONENT_REF , TREE_TYPE ( f_gbytes ) , valist , f_gbytes , NULL_TREE ) ; fbytes = build3 ( COMPONENT_REF , TREE_TYPE ( f_fbytes ) , valist , f_fbytes , NULL_TREE ) ; t = make_tree ( TREE_TYPE ( ovfl ) , virtual_incoming_args_rtx ) ; t = fold_build_pointer_plus_hwi ( t , named_stack_size ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( ovfl ) , ovfl , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( gbase ) , virtual_incoming_args_rtx ) ; offset = MAX_ARGS_IN_GP_REGISTERS * UNITS_PER_WORD ; t = fold_build_pointer_plus_hwi ( t , - offset ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( gbase ) , gbase , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; if ( fp_saved ) { t = make_tree ( TREE_TYPE ( fbase ) , virtual_incoming_args_rtx ) ; offset = gp_saved * UNITS_PER_WORD + MAX_ARGS_IN_FP_REGISTERS * UNITS_PER_HWFPVALUE ; t = fold_build_pointer_plus_hwi ( t , - offset ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( fbase ) , fbase , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; } t = build2 ( MODIFY_EXPR , TREE_TYPE ( gbytes ) , gbytes , size_int ( gp_saved * UNITS_PER_WORD ) ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( fbytes ) , fbytes , size_int ( fp_saved * UNITS_PER_HWFPVALUE ) ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; } </s>

Implement ` va_start ' for varargs and stdarg .


<s> static bool no_global_regs_above ( int first_greg ) { int i ; for ( i = 0 ; i < 32 - first_greg ; i ++ ) if ( global_regs [ first_greg + i ] ) return false ; return true ; } </s>

Look for user-defined global regs . We should not save and restore these , and can not use stmw/lmw if there are any in its range .


<s> bool NVPTXPassConfig :: addInstSelector ( ) { const NVPTXSubtarget & ST = * getTM < NVPTXTargetMachine > ( ) . getSubtargetImpl ( ) ; addPass ( createLowerAggrCopies ( ) ) ; addPass ( createAllocaHoisting ( ) ) ; addPass ( createNVPTXISelDag ( getNVPTXTargetMachine ( ) , getOptLevel ( ) ) ) ; if ( ! ST . hasImageHandles ( ) ) addPass ( createNVPTXReplaceImageHandlesPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .

NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX


<s> bool insertEdge ( unsigned Reg ) { return Edges . insert ( Reg ) . second ; } </s>

Update the call graph after inserting a new edge .


<s> static int sign_bit_position ( const rtx op ) { const int sz = GET_MODE_SIZE ( GET_MODE ( op ) ) ; return sz * 8 - 1 ; } </s>

Return the sign bit position for given OP 's mode .


<s> static rtx copy_operand ( rtx op , machine_mode mode ) { if ( GET_MODE ( op ) != VOIDmode ) { if ( REG_P ( op ) ) op = gen_rtx_REG ( mode , REGNO ( op ) ) ; else { op = copy_rtx ( op ) ; PUT_MODE ( op , mode ) ; } } return op ; } </s>


<s> static void xstormy16_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( * cum < NUM_ARGUMENT_REGISTERS && * cum + XSTORMY16_WORD_SIZE ( type , mode ) > NUM_ARGUMENT_REGISTERS ) * cum = NUM_ARGUMENT_REGISTERS ; * cum += XSTORMY16_WORD_SIZE ( type , mode ) ; } </s>

Update CUM to advance past an argument in the argument list . The values MODE , TYPE and NAMED describe that argument . Once this is done , the variable CUM is suitable for analyzing the * following * argument with ` TARGET_FUNCTION_ARG ' , etc . This function need not do anything if the argument in question was passed on the stack . The compiler knows how to track the amount of stack space used for arguments without any special help . However , it makes life easier for xstormy16_build_va_list if it does update the word count .


<s> std :: pair < SDValue , SDValue > SystemZSelectionDAGInfo :: EmitTargetCodeForMemchr ( SelectionDAG & DAG , SDLoc DL , SDValue Chain , SDValue Src , SDValue Char , SDValue Length , MachinePointerInfo SrcPtrInfo ) const { EVT PtrVT = Src . getValueType ( ) ; SDVTList VTs = DAG . getVTList ( PtrVT , MVT :: Other , MVT :: Glue ) ; Length = DAG . getZExtOrTrunc ( Length , DL , PtrVT ) ; Char = DAG . getZExtOrTrunc ( Char , DL , MVT :: i32 ) ; Char = DAG . getNode ( ISD :: AND , DL , MVT :: i32 , Char , DAG . getConstant ( 255 , MVT :: i32 ) ) ; SDValue Limit = DAG . getNode ( ISD :: ADD , DL , PtrVT , Src , Length ) ; SDValue End = DAG . getNode ( SystemZISD :: SEARCH_STRING , DL , VTs , Chain , Limit , Src , Char ) ; Chain = End . getValue ( 1 ) ; SDValue Glue = End . getValue ( 2 ) ; SmallVector < SDValue , 5 > Ops ; Ops . push_back ( End ) ; Ops . push_back ( DAG . getConstant ( 0 , PtrVT ) ) ; Ops . push_back ( DAG . getConstant ( SystemZ :: CCMASK_SRST , MVT :: i32 ) ) ; Ops . push_back ( DAG . getConstant ( SystemZ :: CCMASK_SRST_FOUND , MVT :: i32 ) ) ; Ops . push_back ( Glue ) ; VTs = DAG . getVTList ( PtrVT , MVT :: Glue ) ; End = DAG . getNode ( SystemZISD :: SELECT_CCMASK , DL , VTs , Ops ) ; return std :: make_pair ( End , Chain ) ; } </s>

Emit target-specific code that performs a memchr , in cases where that is faster than a libcall .


<s> bool NVPTXAssignValidGlobalNames :: runOnModule ( Module & M ) { for ( GlobalVariable & GV : M . globals ( ) ) { if ( GV . hasLocalLinkage ( ) ) { GV . setName ( cleanUpName ( GV . getName ( ) ) ) ; } } for ( Function & F : M . functions ( ) ) if ( F . hasLocalLinkage ( ) ) F . setName ( cleanUpName ( F . getName ( ) ) ) ; return true ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> void MipsFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MipsInstrInfo & TII = * static_cast < const MipsInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; unsigned StackSize = MFI -> getStackSize ( ) ; unsigned NewReg = 0 ; int NewImm = 0 ; bool ATUsed = false ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( Mips :: ADDu ) , Mips :: SP ) . addReg ( Mips :: FP ) . addReg ( Mips :: ZERO ) ; } if ( StackSize ) { ATUsed = expandRegLargeImmPair ( Mips :: SP , StackSize , NewReg , NewImm , MBB , MBBI ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDiu ) , Mips :: SP ) . addReg ( NewReg ) . addImm ( NewImm ) ; if ( ATUsed ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ATMACRO ) ) ; } } </s>

Mips Mips Mips Mips 0 0 0 Mips::ADDu Mips::SP Mips::FP Mips::ZERO Mips::SP Mips::ADDiu Mips::SP Mips::ATMACRO


<s> SDValue PPCTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { if ( PPCSubTarget . isSVR4ABI ( ) && ! PPCSubTarget . isPPC64 ( ) ) { return LowerFormalArguments_32SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } else { return LowerFormalArguments_Darwin_Or_64SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> static bool arm_must_pass_in_stack ( machine_mode mode , const_tree type ) { if ( TARGET_AAPCS_BASED ) return must_pass_in_stack_var_size ( mode , type ) ; else return must_pass_in_stack_var_size_or_pad ( mode , type ) ; } </s>

Return true if a type must be passed in memory . For AAPCS , small aggregates ( padded to the size of a word ) should be passed in a register .


<s> bool X86FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const X86RegisterInfo * RegInfo = MF . getSubtarget < X86Subtarget > ( ) . getRegisterInfo ( ) ; unsigned SlotSize = RegInfo -> getSlotSize ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned CalleeSavedFrameSize = 0 ; int SpillSlotOffset = getOffsetOfLocalArea ( ) + X86FI -> getTCReturnAddrDelta ( ) ; if ( hasFP ( MF ) ) { SpillSlotOffset -= SlotSize ; MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; unsigned FPReg = RegInfo -> getFrameRegister ( MF ) ; for ( unsigned i = 0 ; i < CSI . size ( ) ; ++ i ) { if ( TRI -> regsOverlap ( CSI [ i ] . getReg ( ) , FPReg ) ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - 1 ] . setFrameIdx ( SlotIndex ) ; } X86FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = RegInfo -> getMinimalPhysRegClass ( Reg ) ; SpillSlotOffset -= std :: abs ( SpillSlotOffset ) % RC -> getAlignment ( ) ; SpillSlotOffset -= RC -> getSize ( ) ; int SlotIndex = MFI -> CreateFixedSpillStackObject ( RC -> getSize ( ) , SpillSlotOffset ) ; CSI [ i - 1 ] . setFrameIdx ( SlotIndex ) ; MFI -> ensureMaxAlignment ( RC -> getAlignment ( ) ) ; } return true ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> static void nds32_emit_stack_v3push ( unsigned Rb , unsigned Re , unsigned imm8u ) { unsigned regno ; int num_use_regs ; int par_index ; int offset ; rtx reg ; rtx mem ; rtx push_rtx ; rtx adjust_sp_rtx ; rtx parallel_insn ; num_use_regs = Re - Rb + 1 + 3 ; parallel_insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_use_regs + 1 ) ) ; par_index = 0 ; offset = - ( num_use_regs * 4 ) ; for ( regno = Rb ; regno <= Re ; regno ++ ) { reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( mem , reg ) ; XVECEXP ( parallel_insn , 0 , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; } reg = gen_rtx_REG ( SImode , FP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( mem , reg ) ; XVECEXP ( parallel_insn , 0 , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; reg = gen_rtx_REG ( SImode , GP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( mem , reg ) ; XVECEXP ( parallel_insn , 0 , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; reg = gen_rtx_REG ( SImode , LP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( mem , reg ) ; XVECEXP ( parallel_insn , 0 , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; offset = - ( num_use_regs * 4 ) ; adjust_sp_rtx = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , offset - imm8u ) ) ; XVECEXP ( parallel_insn , 0 , par_index ) = adjust_sp_rtx ; RTX_FRAME_RELATED_P ( adjust_sp_rtx ) = 1 ; parallel_insn = emit_insn ( parallel_insn ) ; RTX_FRAME_RELATED_P ( parallel_insn ) = 1 ; } </s>

Function to create a parallel rtx pattern which presents stack v3push behavior . The overall concept are : `` push registers to memory '' , `` adjust stack pointer '' .


"immediate value expected for vector index"

tryParseRegister - parse one register if possible


<s> static bool visium_legitimate_address_p ( enum machine_mode mode , rtx x , bool strict ) { rtx base ; unsigned int regno ; if ( GET_CODE ( x ) == PLUS ) { if ( ! rtx_ok_for_offset_p ( mode , XEXP ( x , 1 ) ) ) return false ; base = XEXP ( x , 0 ) ; } else base = x ; if ( GET_CODE ( base ) == SUBREG ) base = SUBREG_REG ( base ) ; if ( ! REG_P ( base ) ) return false ; regno = REGNO ( base ) ; if ( strict ) return REGNO_OK_FOR_BASE_P ( regno ) ; return BASE_REGISTER_P ( regno ) || regno >= FIRST_PSEUDO_REGISTER ; } </s>

Return whether X is a legitimate memory address for a memory operand of mode MODE . Legitimate addresses are defined in two variants : a strict variant and a non-strict one . The STRICT parameter chooses which variant is desired by the caller . The strict variant is used in the reload pass . It must be defined so that any pseudo-register that has not been allocated a hard register is considered a memory reference . This is because in contexts where some kind of register is required , a pseudo-register with no hard register must be rejected . For non-hard registers , the strict variant should look up the ` reg_renumber ' array ; it should then proceed using the hard register number in the array , or treat the pseudo as a memory reference if the array holds ` -1 ' . The non-strict variant is used in other passes . It must be defined to accept all pseudo-registers in every context where some kind of register is required .


<s> static int optimal_immediate_sequence ( enum rtx_code code , unsigned HOST_WIDE_INT val , struct four_ints * return_sequence ) { int best_consecutive_zeros = 0 ; int i ; int best_start = 0 ; int insns1 , insns2 ; struct four_ints tmp_sequence ; if ( TARGET_ARM ) { for ( i = 0 ; i < 32 ; i += 2 ) { int consecutive_zeros = 0 ; if ( ! ( val & ( 3 << i ) ) ) { while ( ( i < 32 ) && ! ( val & ( 3 << i ) ) ) { consecutive_zeros += 2 ; i += 2 ; } if ( consecutive_zeros > best_consecutive_zeros ) { best_consecutive_zeros = consecutive_zeros ; best_start = i - consecutive_zeros ; } i -= 2 ; } } } insns1 = optimal_immediate_sequence_1 ( code , val , return_sequence , best_start ) ; if ( best_start != 0 && ( ( ( ( unsigned HOST_WIDE_INT ) 1 ) << best_start ) < val ) ) { insns2 = optimal_immediate_sequence_1 ( code , val , & tmp_sequence , 0 ) ; if ( insns2 <= insns1 ) { * return_sequence = tmp_sequence ; insns1 = insns2 ; } } return insns1 ; } </s>

Return a sequence of integers , in RETURN_SEQUENCE that fit into ARM/THUMB2 immediates , and add up to VAL . Thr function return value gives the number of insns required .


"Unexpected fixup kind in fixupNeedsRelaxation()!"

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> int s390_mem_constraint ( const char * str , rtx op ) { char c = str [ 0 ] ; switch ( c ) { case 'A' : if ( ! MEM_P ( op ) || MEM_VOLATILE_P ( op ) ) return 0 ; if ( ( reload_completed || reload_in_progress ) ? ! offsettable_memref_p ( op ) : ! offsettable_nonstrict_memref_p ( op ) ) return 0 ; return s390_check_qrst_address ( str [ 1 ] , XEXP ( op , 0 ) , true ) ; case 'B' : if ( ! MEM_P ( op ) ) return 0 ; return s390_check_qrst_address ( str [ 1 ] , XEXP ( op , 0 ) , false ) ; case 'Q' : case 'R' : case 'S' : case 'T' : if ( GET_CODE ( op ) != MEM ) return 0 ; return s390_check_qrst_address ( c , XEXP ( op , 0 ) , true ) ; case 'Y' : if ( ! s390_decompose_addrstyle_without_index ( op , NULL , NULL ) ) return 0 ; break ; case 'Z' : return s390_check_qrst_address ( str [ 1 ] , op , true ) ; default : return 0 ; } return 1 ; } </s>

Evaluates constraint strings described by the regular expression ( [ A|B|Z ] ( Q|R|S|T ) ) |U|W|Y and returns 1 if OP is a valid operand for the constraint given in STR , or 0 else .


<s>
bool
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
override
{
switch
(
ConstraintID
)
{
default
:
errs
(
)
<<
"ConstraintID: "
<<
ConstraintID
<<
"\n"
;
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_es
:
case
InlineAsm
::
Constraint_i
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_o
:
case
InlineAsm
::
Constraint_Q
:
case
InlineAsm
::
Constraint_Z
:
case
InlineAsm
::
Constraint_Zy
:
const
TargetRegisterInfo
*
TRI
=
PPCSubTarget
->
getRegisterInfo
(
)
;
const
TargetRegisterClass
*
TRC
=
TRI
->
getPointerRegClass
(
*
MF
,
1
)
;
SDLoc
dl
(
Op
)
;
SDValue
RC
=
CurDAG
->
getTargetConstant
(
TRC
->
getID
(
)
,
dl
,
MVT
::
i32
)
;
SDValue
NewOp
=
SDValue
(
CurDAG
->
getMachineNode
(
TargetOpcode
::
COPY_TO_REGCLASS
,
dl
,
Op
.
getValueType
(
)
,
Op
,
RC
)
,
0
)
;
OutOps
.
push_back
(
NewOp
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> static enum dispatch_group get_insn_group ( rtx_insn * insn ) { enum dispatch_group group = get_mem_group ( insn ) ; if ( group ) return group ; if ( is_branch ( insn ) ) return disp_branch ; if ( is_cmp ( insn ) ) return disp_cmp ; if ( has_immediate ( insn ) ) return disp_imm ; if ( is_prefetch ( insn ) ) return disp_prefetch ; return disp_no_group ; } </s>


<s> bool PPCRegisterInfo :: isCallerPreservedPhysReg ( unsigned PhysReg , const MachineFunction & MF ) const { assert ( TargetRegisterInfo :: isPhysicalRegister ( PhysReg ) ) ; if ( TM . isELFv2ABI ( ) && PhysReg == PPC :: X2 ) { return ( getReservedRegs ( MF ) . test ( PPC :: X2 ) ) ; } else { return false ; } } </s>

Physical registers that may be modified within a function but are guaranteed to be restored before any uses .


<s> void R600InstrInfo :: reserveIndirectRegisters ( BitVector & Reserved , const MachineFunction & MF ) const { const AMDGPUFrameLowering * TFL = static_cast < const AMDGPUFrameLowering * > ( MF . getTarget ( ) . getFrameLowering ( ) ) ; unsigned StackWidth = TFL -> getStackWidth ( MF ) ; int End = getIndirectIndexEnd ( MF ) ; if ( End == - 1 ) return ; for ( int Index = getIndirectIndexBegin ( MF ) ; Index <= End ; ++ Index ) { unsigned SuperReg = AMDGPU :: R600_Reg128RegClass . getRegister ( Index ) ; Reserved . set ( SuperReg ) ; for ( unsigned Chan = 0 ; Chan < StackWidth ; ++ Chan ) { unsigned Reg = AMDGPU :: R600_TReg32RegClass . getRegister ( ( 4 * Index ) + Chan ) ; Reserved . set ( Reg ) ; } } } </s>

Reserve the registers that may be accessed using indirect addressing .


<s> const char * MipsTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case MipsISD :: JmpLink : return "MipsISD::JmpLink" ; case MipsISD :: Hi : return "MipsISD::Hi" ; case MipsISD :: Lo : return "MipsISD::Lo" ; case MipsISD :: GPRel : return "MipsISD::GPRel" ; case MipsISD :: ThreadPointer : return "MipsISD::ThreadPointer" ; case MipsISD :: Ret : return "MipsISD::Ret" ; case MipsISD :: FPBrcond : return "MipsISD::FPBrcond" ; case MipsISD :: FPCmp : return "MipsISD::FPCmp" ; case MipsISD :: CMovFP_T : return "MipsISD::CMovFP_T" ; case MipsISD :: CMovFP_F : return "MipsISD::CMovFP_F" ; case MipsISD :: FPRound : return "MipsISD::FPRound" ; case MipsISD :: MAdd : return "MipsISD::MAdd" ; case MipsISD :: MAddu : return "MipsISD::MAddu" ; case MipsISD :: MSub : return "MipsISD::MSub" ; case MipsISD :: MSubu : return "MipsISD::MSubu" ; case MipsISD :: DivRem : return "MipsISD::DivRem" ; case MipsISD :: DivRemU : return "MipsISD::DivRemU" ; case MipsISD :: BuildPairF64 : return "MipsISD::BuildPairF64" ; case MipsISD :: ExtractElementF64 : return "MipsISD::ExtractElementF64" ; case MipsISD :: Wrapper : return "MipsISD::Wrapper" ; case MipsISD :: DynAlloc : return "MipsISD::DynAlloc" ; case MipsISD :: Sync : return "MipsISD::Sync" ; case MipsISD :: Ext : return "MipsISD::Ext" ; case MipsISD :: Ins : return "MipsISD::Ins" ; case MipsISD :: LWL : return "MipsISD::LWL" ; case MipsISD :: LWR : return "MipsISD::LWR" ; case MipsISD :: SWL : return "MipsISD::SWL" ; case MipsISD :: SWR : return "MipsISD::SWR" ; case MipsISD :: LDL : return "MipsISD::LDL" ; case MipsISD :: LDR : return "MipsISD::LDR" ; case MipsISD :: SDL : return "MipsISD::SDL" ; case MipsISD :: SDR : return "MipsISD::SDR" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific

Mips Mips MipsISD::JmpLink "MipsISD::JmpLink" MipsISD::Hi "MipsISD::Hi" MipsISD::Lo "MipsISD::Lo" MipsISD::GPRel "MipsISD::GPRel" MipsISD::ThreadPointer "MipsISD::ThreadPointer" MipsISD::Ret "MipsISD::Ret" MipsISD::FPBrcond "MipsISD::FPBrcond" MipsISD::FPCmp "MipsISD::FPCmp" MipsISD::CMovFP_T "MipsISD::CMovFP_T" MipsISD::CMovFP_F "MipsISD::CMovFP_F" MipsISD::FPRound "MipsISD::FPRound" MipsISD::MAdd "MipsISD::MAdd" MipsISD::MAddu "MipsISD::MAddu" MipsISD::MSub "MipsISD::MSub" MipsISD::MSubu "MipsISD::MSubu" MipsISD::DivRem "MipsISD::DivRem" MipsISD::DivRemU "MipsISD::DivRemU" MipsISD::BuildPairF64 "MipsISD::BuildPairF64" MipsISD::ExtractElementF64 "MipsISD::ExtractElementF64" MipsISD::Wrapper "MipsISD::Wrapper" MipsISD::DynAlloc "MipsISD::DynAlloc" MipsISD::Sync "MipsISD::Sync" MipsISD::Ext "MipsISD::Ext" MipsISD::Ins "MipsISD::Ins" MipsISD::LWL "MipsISD::LWL" MipsISD::LWR "MipsISD::LWR" MipsISD::SWL "MipsISD::SWL" MipsISD::SWR "MipsISD::SWR" MipsISD::LDL "MipsISD::LDL" MipsISD::LDR "MipsISD::LDR" MipsISD::SDL "MipsISD::SDL" MipsISD::SDR "MipsISD::SDR"


<s> static void alpha_setup_incoming_varargs ( CUMULATIVE_ARGS * pcum , enum machine_mode mode , tree type , int * pretend_size , int no_rtl ) { CUMULATIVE_ARGS cum = * pcum ; FUNCTION_ARG_ADVANCE ( cum , mode , type , 1 ) ; if ( cum . num_reg_words < 6 ) { if ( ! no_rtl ) { emit_insn ( gen_umk_mismatch_args ( GEN_INT ( cum . num_reg_words ) ) ) ; emit_insn ( gen_arg_home_umk ( ) ) ; } * pretend_size = 0 ; } if ( cum . num_args < 6 ) { if ( ! no_rtl ) { emit_move_insn ( gen_rtx_REG ( DImode , 1 ) , virtual_incoming_args_rtx ) ; emit_insn ( gen_arg_home ( ) ) ; } * pretend_size = 7 * UNITS_PER_WORD ; } if ( cum >= 6 ) return ; if ( ! no_rtl ) { int count , set = get_varargs_alias_set ( ) ; rtx tmp ; count = cfun -> va_list_gpr_size / UNITS_PER_WORD ; if ( count > 6 - cum ) count = 6 - cum ; gcc_assert ( ( VA_LIST_MAX_FPR_SIZE & 3 ) == 3 ) ; if ( cfun -> va_list_fpr_size & 1 ) { tmp = gen_rtx_MEM ( BLKmode , plus_constant ( virtual_incoming_args_rtx , ( cum + 6 ) * UNITS_PER_WORD ) ) ; MEM_NOTRAP_P ( tmp ) = 1 ; set_mem_alias_set ( tmp , set ) ; move_block_from_reg ( 16 + cum , tmp , count ) ; } if ( cfun -> va_list_fpr_size & 2 ) { tmp = gen_rtx_MEM ( BLKmode , plus_constant ( virtual_incoming_args_rtx , cum * UNITS_PER_WORD ) ) ; MEM_NOTRAP_P ( tmp ) = 1 ; set_mem_alias_set ( tmp , set ) ; move_block_from_reg ( 16 + cum + TARGET_FPREGS * 32 , tmp , count ) ; } } * pretend_size = 12 * UNITS_PER_WORD ; } </s>

Perform any needed actions needed for a function that is receiving a variable number of arguments .


<s> const char * AArch64Relocator :: getName ( Relocator :: Type pType ) const { assert ( ApplyFunctions . find ( pType ) != ApplyFunctions . end ( ) ) ; return ApplyFunctions [ pType ] . name ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> gimple * fold ( gimple_folder & f ) const OVERRIDE { if ( tree amount = uniform_integer_cst_p ( gimple_call_arg ( f . call , 2 ) ) ) { if ( wi :: to_widest ( amount ) >= 0 ) { function_instance instance ( "svlsl" , functions :: svlsl , shapes :: binary_uint_opt_n , MODE_n , f . type_suffix_ids , f . pred ) ; gcall * call = as_a < gcall * > ( f . redirect_call ( instance ) ) ; gimple_call_set_arg ( call , 2 , amount ) ; return call ; } int element_bits = f . type_suffix ( 0 ) . element_bits ; if ( wi :: to_widest ( amount ) >= - element_bits ) { amount = wide_int_to_tree ( TREE_TYPE ( amount ) , - wi :: to_wide ( amount ) ) ; function_instance instance ( "svrshr" , functions :: svrshr , shapes :: shift_right_imm , MODE_n , f . type_suffix_ids , f . pred ) ; gcall * call = as_a < gcall * > ( f . redirect_call ( instance ) ) ; gimple_call_set_arg ( call , 2 , amount ) ; return call ; } } return NULL ; } </s>

Try to fold the call . Return the new statement on success and null on failure .


<s> void TPCIndexMap :: sort ( ) { LoopData loopTemp [ 5 ] ; int size = 0 ; for ( unsigned long i = 0 ; i < m_loopInfoVec . size ( ) ; i ++ ) { if ( m_loopInfoVec [ i ] . is_Valid ( ) ) { loopTemp [ m_loopInfoVec [ i ] . get_DIM ( ) ] = m_loopInfoVec [ i ] ; size ++ ; } } for ( int i = 0 ; i < size ; i ++ ) m_loopInfoVec [ i ] = loopTemp [ i ] ; } </s>


<s> BitVector ARMBaseRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( ARM :: SP ) ; Reserved . set ( ARM :: PC ) ; Reserved . set ( ARM :: FPSCR ) ; Reserved . set ( ARM :: APSR_NZCV ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( FramePtr ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( BasePtr ) ; if ( STI . isR9Reserved ( ) ) Reserved . set ( ARM :: R9 ) ; if ( ! STI . hasVFP3 ( ) || STI . hasD16 ( ) ) { assert ( ARM :: D31 == ARM :: D16 + 15 ) ; for ( unsigned i = 0 ; i != 16 ; ++ i ) Reserved . set ( ARM :: D16 + i ) ; } const TargetRegisterClass * RC = & ARM :: GPRPairRegClass ; for ( TargetRegisterClass :: iterator I = RC -> begin ( ) , E = RC -> end ( ) ; I != E ; ++ I ) for ( MCSubRegIterator SI ( * I , this ) ; SI . isValid ( ) ; ++ SI ) if ( Reserved . test ( * SI ) ) Reserved . set ( * I ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static bool isReverseMask ( ArrayRef < int > M , EVT VT ) { unsigned NumElts = VT . getVectorNumElements ( ) ; if ( NumElts != M . size ( ) ) return false ; for ( unsigned i = 0 ; i != NumElts ; ++ i ) if ( M [ i ] >= 0 && M [ i ] != ( int ) ( NumElts - 1 - i ) ) return false ; return true ; } </s>

Return true if this shuffle mask swaps the order of elements from exactly one source vector .


<s> TargetIRAnalysis AMDGPUTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( const Function & F ) { return TargetTransformInfo ( AMDGPUTTIImpl ( this , F . getParent ( ) -> getDataLayout ( ) ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


"Can only insert epilog into returning blocks"


<s> static char * nvptx_replace_dot ( const char * name ) { if ( strchr ( name , '.' ) == NULL ) return NULL ; char * p = xstrdup ( name ) ; for ( size_t i = 0 ; i < strlen ( p ) ; ++ i ) if ( p [ i ] == '.' ) p [ i ] = '$' ; return p ; } </s>

Return NULL if NAME contains no dot . Otherwise return a copy of NAME with the dots replaced with dollar signs .


<s> EVT MipsTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsZeroVal , bool MemcpyStrSrc , MachineFunction & MF ) const { if ( Subtarget -> hasMips64 ( ) ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> static rtx_insn * loongarch_call_tls_get_addr ( rtx sym , enum loongarch_symbol_type type , rtx v0 ) { rtx loc , a0 ; rtx_insn * insn ; a0 = gen_rtx_REG ( Pmode , GP_ARG_FIRST ) ; if ( ! loongarch_tls_symbol ) loongarch_tls_symbol = init_one_libfunc ( "__tls_get_addr" ) ; loc = loongarch_unspec_address ( sym , type ) ; start_sequence ( ) ; if ( type == SYMBOL_TLSLDM ) emit_insn ( loongarch_got_load_tls_ld ( a0 , loc ) ) ; else if ( type == SYMBOL_TLSGD ) emit_insn ( loongarch_got_load_tls_gd ( a0 , loc ) ) ; else gcc_unreachable ( ) ; insn = emit_call_insn ( gen_call_value_internal ( v0 , loongarch_tls_symbol , const0_rtx ) ) ; RTL_CONST_CALL_P ( insn ) = 1 ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , a0 ) ; insn = get_insns ( ) ; end_sequence ( ) ; return insn ; } </s>

Return an instruction sequence that calls __tls_get_addr . SYM is the TLS symbol we are referencing and TYPE is the symbol type to use ( either global dynamic or local dynamic ) . V0 is an RTX for the return value location .


<s> static bool avr_allocate_stack_slots_for_args ( void ) { return ! cfun -> machine -> is_naked ; } </s>

Implement ` TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS '


<s> static int mingw32_gt_pch_use_address ( void * & addr , size_t size , int fd , size_t offset ) { void * mmap_addr ; HANDLE mmap_handle ; char * object_name = NULL ; OSVERSIONINFO version_info ; int r ; version_info . dwOSVersionInfoSize = sizeof ( version_info ) ; if ( size == 0 ) return 0 ; if ( ( offset & ( va_granularity - 1 ) ) != 0 ) return - 1 ; GetVersionEx ( & version_info ) ; char local_object_name [ sizeof ( OBJECT_NAME_FMT ) + sizeof ( DWORD ) * 2 ] ; if ( version_info . dwMajorVersion > 4 ) { snprintf ( local_object_name , sizeof ( local_object_name ) , OBJECT_NAME_FMT "%lx" , GetCurrentProcessId ( ) ) ; object_name = local_object_name ; } mmap_handle = CreateFileMappingA ( ( HANDLE ) _get_osfhandle ( fd ) , NULL , PAGE_WRITECOPY | SEC_COMMIT , 0 , 0 , object_name ) ; if ( mmap_handle == NULL ) { w32_error ( __FUNCTION__ , __FILE__ , __LINE__ , "CreateFileMapping" ) ; return - 1 ; } for ( r = 0 ; r < 5 ; r ++ ) { mmap_addr = MapViewOfFileEx ( mmap_handle , FILE_MAP_COPY , 0 , offset , size , addr ) ; if ( mmap_addr == addr ) break ; if ( r != 4 ) Sleep ( 500 ) ; } if ( mmap_addr != addr ) { w32_error ( __FUNCTION__ , __FILE__ , __LINE__ , "MapViewOfFileEx" ) ; CloseHandle ( mmap_handle ) ; return - 1 ; } return 1 ; } </s>

ADDR is an address returned by gt_pch_get_address . Attempt to allocate SIZE bytes at the same address and load it with the data from FD at OFFSET . Return -1 if we could n't allocate memory at ADDR , return 0 if the memory is allocated but the data not loaded , return 1 if done .


<s> bool RISCVTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { switch ( Intrinsic ) { default : return false ; case Intrinsic :: riscv_masked_atomicrmw_xchg_i32 : case Intrinsic :: riscv_masked_atomicrmw_add_i32 : case Intrinsic :: riscv_masked_atomicrmw_sub_i32 : case Intrinsic :: riscv_masked_atomicrmw_nand_i32 : case Intrinsic :: riscv_masked_atomicrmw_max_i32 : case Intrinsic :: riscv_masked_atomicrmw_min_i32 : case Intrinsic :: riscv_masked_atomicrmw_umax_i32 : case Intrinsic :: riscv_masked_atomicrmw_umin_i32 : case Intrinsic :: riscv_masked_cmpxchg_i32 : PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 0 ) -> getType ( ) ) ; Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: getVT ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . align = 4 ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; } } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> void Initialize ( const MachineFunction & MF , bool isPIC ) { IsPIC = isPIC ; } </s>

This method must be called before any actual lowering is done .


<s> static bool rs6000_save_toc_in_prologue_p ( void ) { return ( cfun && cfun -> machine && cfun -> machine -> save_toc_in_prologue ) ; } </s>

Return whether we need to always update the saved TOC pointer when we update the stack pointer .


"stack limit expression is not supported"

Emit the correct code for allocating stack space , as insns . If COPY_R12 , make sure a copy of the old frame is left in r12 . The generated code may use hard register 0 as a temporary .


<s>
SDValue
KudeyarTargetLowering
::
LowerCall
(
TargetLowering
::
CallLoweringInfo
&
CLI
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SelectionDAG
&
DAG
=
CLI
.
DAG
;
DebugLoc
&
dl
=
CLI
.
DL
;
SmallVector
<
ISD
::
OutputArg
,
32
>
&
Outs
=
CLI
.
Outs
;
SmallVector
<
SDValue
,
32
>
&
OutVals
=
CLI
.
OutVals
;
SmallVector
<
ISD
::
InputArg
,
32
>
&
Ins
=
CLI
.
Ins
;
SDValue
Chain
=
CLI
.
Chain
;
SDValue
Callee
=
CLI
.
Callee
;
bool
&
isTailCall
=
CLI
.
IsTailCall
;
CallingConv
::
ID
CallConv
=
CLI
.
CallConv
;
bool
isVarArg
=
CLI
.
IsVarArg
;
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
OutVals
,
Ins
,
dl
,
DAG
,
InVals
)
;
case
CallingConv
::
Kudeyar_INTR
:
report_fatal_error
(
"ISRs cannot be called directly"
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .

Kudeyar
Kudeyar
ISD::OutputArg
32
32
ISD::InputArg
32
"Unsupported calling convention"
Kudeyar
"ISRs cannot be called directly"


<s> bool XCoreTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_XCore ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


"CJG DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> void LC2200AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; MCInst TmpInst ; TmpInst . setOpcode ( MI -> getOpcode ( ) ) ; for ( const MachineOperand & MO : MI -> operands ( ) ) { MCOperand MCOp ; if ( LowerLC2200MachineOperandToMCOperand ( MO , MCOp , * this ) ) TmpInst . addOperand ( MCOp ) ; } EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


"Unexpected Kind in getPointerRegClass!"

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> const MCExpr * X86_64MachoTargetObjectFile :: getTTypeGlobalReference ( const GlobalValue * GV , unsigned Encoding , Mangler & Mang , const TargetMachine & TM , MachineModuleInfo * MMI , MCStreamer & Streamer ) const { if ( ( Encoding & DW_EH_PE_indirect ) && ( Encoding & DW_EH_PE_pcrel ) ) { const MCSymbol * Sym = TM . getSymbol ( GV , Mang ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_GOTPCREL , getContext ( ) ) ; const MCExpr * Four = MCConstantExpr :: Create ( 4 , getContext ( ) ) ; return MCBinaryExpr :: CreateAdd ( Res , Four , getContext ( ) ) ; } return TargetLoweringObjectFileMachO :: getTTypeGlobalReference ( GV , Encoding , Mang , TM , MMI , Streamer ) ; } </s>

The mach-o version of this method defaults to returning a stub reference .


<s> bool HexagonInstrInfo :: analyzeLoop ( MachineLoop & L , MachineInstr * & IndVarInst , MachineInstr * & CmpInst ) const { MachineBasicBlock * LoopEnd = L . getBottomBlock ( ) ; MachineBasicBlock :: iterator I = LoopEnd -> getFirstTerminator ( ) ; if ( I != LoopEnd -> end ( ) && isEndLoopN ( I -> getOpcode ( ) ) ) { IndVarInst = nullptr ; CmpInst = & * I ; return false ; } return true ; } </s>

Analyze the loop code , return true if it can not be understood .


<s>
void
SPUInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
)
const
{
unsigned
opc
;
bool
isValidFrameIdx
=
(
FrameIdx
<
SPUFrameInfo
::
maxFrameOffset
(
)
)
;
if
(
RC
==
SPU
::
GPRCRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr128
:
SPU
::
STQXr128
)
;
}
else
if
(
RC
==
SPU
::
R64CRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr64
:
SPU
::
STQXr64
)
;
}
else
if
(
RC
==
SPU
::
R64FPRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr64
:
SPU
::
STQXr64
)
;
}
else
if
(
RC
==
SPU
::
R32CRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr32
:
SPU
::
STQXr32
)
;
}
else
if
(
RC
==
SPU
::
R32FPRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr32
:
SPU
::
STQXr32
)
;
}
else
if
(
RC
==
SPU
::
R16CRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr16
:
SPU
::
STQXr16
)
;
}
else
if
(
RC
==
SPU
::
R8CRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr8
:
SPU
::
STQXr8
)
;
}
else
if
(
RC
==
SPU
::
VECREGRegisterClass
)
{
opc
=
(
isValidFrameIdx
)
SPU
::
STQDv16i8
:
SPU
::
STQXv16i8
;
}
else
{
llvm_unreachable
(
"Unknown regclass!"
)
;
}
DebugLoc
DL
=
DebugLoc
::
getUnknownLoc
(
)
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
opc
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
,
FrameIdx
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> const char * HexagonTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case HexagonISD :: CONST32 : return "HexagonISD::CONST32" ; case HexagonISD :: ADJDYNALLOC : return "HexagonISD::ADJDYNALLOC" ; case HexagonISD :: CMPICC : return "HexagonISD::CMPICC" ; case HexagonISD :: CMPFCC : return "HexagonISD::CMPFCC" ; case HexagonISD :: BRICC : return "HexagonISD::BRICC" ; case HexagonISD :: BRFCC : return "HexagonISD::BRFCC" ; case HexagonISD :: SELECT_ICC : return "HexagonISD::SELECT_ICC" ; case HexagonISD :: SELECT_FCC : return "HexagonISD::SELECT_FCC" ; case HexagonISD :: Hi : return "HexagonISD::Hi" ; case HexagonISD :: Lo : return "HexagonISD::Lo" ; case HexagonISD :: FTOI : return "HexagonISD::FTOI" ; case HexagonISD :: ITOF : return "HexagonISD::ITOF" ; case HexagonISD :: CALL : return "HexagonISD::CALL" ; case HexagonISD :: RET_FLAG : return "HexagonISD::RET_FLAG" ; case HexagonISD :: BR_JT : return "HexagonISD::BR_JT" ; case HexagonISD :: TC_RETURN : return "HexagonISD::TC_RETURN" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> Optional < MCFixupKind > ELFPPCAsmBackend :: getFixupKind ( StringRef Name ) const { if ( TT . isOSBinFormatELF ( ) ) { unsigned Type ; if ( TT . isPPC64 ( ) ) { Type = llvm :: StringSwitch < unsigned > ( Name ) . Default ( - 1u ) ; } else { Type = llvm :: StringSwitch < unsigned > ( Name ) . Default ( - 1u ) ; } if ( Type != - 1u ) return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ; } return None ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s>
void
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
override
{
Value
=
adjustFixupValue
(
Fixup
.
getKind
(
)
,
Value
)
;
if
(
!
Value
)
return
;
llvm_unreachable
(
"applyFixup() unimplemented"
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool x86_maybe_negate_const_int ( rtx * loc , machine_mode mode ) { HOST_WIDE_INT val ; if ( ! CONST_INT_P ( * loc ) ) return false ; switch ( mode ) { case DImode : gcc_assert ( x86_64_immediate_operand ( * loc , mode ) ) ; mode = SImode ; break ; case SImode : case HImode : case QImode : break ; default : gcc_unreachable ( ) ; } if ( mode_signbit_p ( mode , * loc ) ) return false ; val = INTVAL ( * loc ) ; if ( ( val < 0 && val != - 128 ) || val == 128 ) { * loc = GEN_INT ( - val ) ; return true ; } return false ; } </s>

If profitable , negate ( without causing overflow ) integer constant of mode MODE at location LOC . Return true in this case .


<s> const X86InstrInfo * getInstrInfo ( ) const { return getTargetMachine ( ) . getInstrInfo ( ) ; } </s>


<s> bool FalkorHWPFFix :: runOnMachineFunction ( MachineFunction & Fn ) { auto & ST = Fn . getSubtarget < AArch64Subtarget > ( ) ; if ( ST . getProcFamily ( ) != AArch64Subtarget :: Falkor ) return false ; if ( skipFunction ( Fn . getFunction ( ) ) ) return false ; TII = static_cast < const AArch64InstrInfo * > ( ST . getInstrInfo ( ) ) ; TRI = ST . getRegisterInfo ( ) ; MachineLoopInfo & LI = getAnalysis < MachineLoopInfo > ( ) ; Modified = false ; for ( MachineLoop * I : LI ) for ( MachineLoop * L : depth_first ( I ) ) if ( L -> isInnermost ( ) ) runOnLoop ( * L , Fn ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s>
SDValue
XCoreTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
isVarArg
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .

XCore
XCore
ISD::InputArg
"Unsupported calling convention"


<s> InstructionCost ARMTTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind , Instruction * Inst ) { if ( ( Opcode == Instruction :: SDiv || Opcode == Instruction :: UDiv || Opcode == Instruction :: SRem || Opcode == Instruction :: URem ) && Idx == 1 ) return 0 ; if ( Opcode == Instruction :: GetElementPtr && Idx != 0 ) return 0 ; if ( Opcode == Instruction :: And ) { if ( Imm == 255 || Imm == 65535 ) return 0 ; return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( ~ Imm , Ty , CostKind ) ) ; } if ( Opcode == Instruction :: Add ) return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( - Imm , Ty , CostKind ) ) ; if ( Opcode == Instruction :: ICmp && Imm . isNegative ( ) && Ty -> getIntegerBitWidth ( ) == 32 ) { int64_t NegImm = - Imm . getSExtValue ( ) ; if ( ST -> isThumb2 ( ) && NegImm < 1 << 12 ) return 0 ; if ( ST -> isThumb ( ) && NegImm < 1 << 8 ) return 0 ; } if ( Opcode == Instruction :: Xor && Imm . isAllOnes ( ) ) return 0 ; if ( Inst && ( ( ST -> hasV6Ops ( ) && ! ST -> isThumb ( ) ) || ST -> isThumb2 ( ) ) && Ty -> getIntegerBitWidth ( ) <= 32 ) { if ( isSSATMinMaxPattern ( Inst , Imm ) || ( isa < ICmpInst > ( Inst ) && Inst -> hasOneUse ( ) && isSSATMinMaxPattern ( cast < Instruction > ( * Inst -> user_begin ( ) ) , Imm ) ) ) return 0 ; } if ( Inst && Opcode == Instruction :: ICmp && Idx == 1 && Imm . isAllOnesValue ( ) ) { ICmpInst :: Predicate Pred = cast < ICmpInst > ( Inst ) -> getPredicate ( ) ; if ( Pred == ICmpInst :: ICMP_SGT || Pred == ICmpInst :: ICMP_SLE ) return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( Imm + 1 , Ty , CostKind ) ) ; } return getIntImmCost ( Imm , Ty , CostKind ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> void M88kInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & O ) { printInstruction ( MI , Address , STI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static void mips_multi_add_label ( const char * label ) { struct mips_multi_member * member ; member = mips_multi_add ( ) ; member -> is_label_p = true ; member -> format = label ; } </s>

Add the given label definition to the current multi-insn sequence . The definition should include the colon .


<s> static bool pru_function_value_regno_p ( const unsigned int regno ) { return regno == FIRST_RETVAL_REGNUM ; } </s>


<s> static std :: unique_ptr < AMDGPUOperand > CreateReg ( unsigned RegNo , SMLoc S , SMLoc E , const MCRegisterInfo * TRI ) { auto Op = llvm :: make_unique < AMDGPUOperand > ( Register ) ; Op -> Reg . RegNo = RegNo ; Op -> Reg . TRI = TRI ; Op -> Reg . Modifiers = - 1 ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> bool AArch64FrameLowering :: enableStackSlotScavenging ( const MachineFunction & MF ) const { const AArch64FunctionInfo * AFI = MF . getInfo < AArch64FunctionInfo > ( ) ; return AFI -> hasCalleeSaveStackFreeSpace ( ) ; } </s>

Returns true if the stack slot holes in the fixed and callee-save stack area should be used when allocating other stack locations to reduce stack size .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"WebAssembly Lower br_unless"
;
}
</s>

getPassName - Return a nice clean name for a pass .

WebAssembly
"WebAssembly Lower br_unless"


<s> static tree ix86_veclibabi_acml ( combined_fn fn , tree type_out , tree type_in ) { char name [ 20 ] = "__vr.._" ; tree fntype , new_fndecl , args ; unsigned arity ; const char * bname ; machine_mode el_mode , in_mode ; int n , in_n ; if ( ! TARGET_64BIT || ! flag_unsafe_math_optimizations ) return NULL_TREE ; el_mode = TYPE_MODE ( TREE_TYPE ( type_out ) ) ; n = TYPE_VECTOR_SUBPARTS ( type_out ) ; in_mode = TYPE_MODE ( TREE_TYPE ( type_in ) ) ; in_n = TYPE_VECTOR_SUBPARTS ( type_in ) ; if ( el_mode != in_mode || n != in_n ) return NULL_TREE ; switch ( fn ) { CASE_CFN_SIN : CASE_CFN_COS : CASE_CFN_EXP : CASE_CFN_LOG : CASE_CFN_LOG2 : CASE_CFN_LOG10 : if ( el_mode == DFmode && n == 2 ) { name [ 4 ] = 'd' ; name [ 5 ] = '2' ; } else if ( el_mode == SFmode && n == 4 ) { name [ 4 ] = 's' ; name [ 5 ] = '4' ; } else return NULL_TREE ; break ; default : return NULL_TREE ; } tree fndecl = mathfn_built_in ( TREE_TYPE ( type_in ) , fn ) ; bname = IDENTIFIER_POINTER ( DECL_NAME ( fndecl ) ) ; sprintf ( name + 7 , "%s" , bname + 10 ) ; arity = 0 ; for ( args = DECL_ARGUMENTS ( fndecl ) ; args ; args = TREE_CHAIN ( args ) ) arity ++ ; if ( arity == 1 ) fntype = build_function_type_list ( type_out , type_in , NULL ) ; else fntype = build_function_type_list ( type_out , type_in , type_in , NULL ) ; new_fndecl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , fntype ) ; TREE_PUBLIC ( new_fndecl ) = 1 ; DECL_EXTERNAL ( new_fndecl ) = 1 ; DECL_IS_NOVOPS ( new_fndecl ) = 1 ; TREE_READONLY ( new_fndecl ) = 1 ; return new_fndecl ; } </s>

Handler for an ACML-style interface to a library with vectorized intrinsics .


<s> void arc_print_operand_address ( FILE * file , rtx addr ) { register rtx base , index = 0 ; switch ( GET_CODE ( addr ) ) { case REG : fputs ( reg_names [ REGNO ( addr ) ] , file ) ; break ; case SYMBOL_REF : output_addr_const ( file , addr ) ; if ( SYMBOL_REF_SMALL_P ( addr ) ) fprintf ( file , "@sda" ) ; break ; case PLUS : if ( GET_CODE ( XEXP ( addr , 0 ) ) == MULT ) index = XEXP ( XEXP ( addr , 0 ) , 0 ) , base = XEXP ( addr , 1 ) ; else if ( CONST_INT_P ( XEXP ( addr , 0 ) ) ) index = XEXP ( addr , 0 ) , base = XEXP ( addr , 1 ) ; else base = XEXP ( addr , 0 ) , index = XEXP ( addr , 1 ) ; gcc_assert ( OBJECT_P ( base ) ) ; arc_print_operand_address ( file , base ) ; if ( CONSTANT_P ( base ) && CONST_INT_P ( index ) ) fputc ( '+' , file ) ; else fputc ( ',' , file ) ; gcc_assert ( OBJECT_P ( index ) ) ; arc_print_operand_address ( file , index ) ; break ; case CONST : { rtx c = XEXP ( addr , 0 ) ; gcc_assert ( GET_CODE ( XEXP ( c , 0 ) ) == SYMBOL_REF ) ; gcc_assert ( GET_CODE ( XEXP ( c , 1 ) ) == CONST_INT ) ; output_address ( XEXP ( addr , 0 ) ) ; break ; } case PRE_INC : case PRE_DEC : gcc_unreachable ( ) ; break ; default : if ( flag_pic ) arc_output_pic_addr_const ( file , addr , 0 ) ; else output_addr_const ( file , addr ) ; break ; } } </s>

Print a memory address as an operand to reference that memory location .


<s> void bpf_core_reloc_add ( const tree type , const char * section_name , vec < unsigned int > * accessors , rtx_code_label * label ) { char buf [ 40 ] ; unsigned int i , n = 0 ; if ( accessors -> length ( ) < 1 ) return ; for ( i = 0 ; i < accessors -> length ( ) - 1 ; i ++ ) n += snprintf ( buf + n , sizeof ( buf ) - n , "%u:" , ( * accessors ) [ i ] ) ; snprintf ( buf + n , sizeof ( buf ) - n , "%u" , ( * accessors ) [ i ] ) ; bpf_core_reloc_ref bpfcr = ggc_cleared_alloc < bpf_core_reloc_t > ( ) ; ctf_container_ref ctfc = ctf_get_tu_ctfc ( ) ; ctf_add_string ( ctfc , buf , & ( bpfcr -> bpfcr_astr_off ) , CTF_AUX_STRTAB ) ; bpfcr -> bpfcr_type = get_btf_id ( ctf_lookup_tree_type ( ctfc , type ) ) ; bpfcr -> bpfcr_insn_label = label ; bpfcr -> bpfcr_kind = BPF_RELO_FIELD_BYTE_OFFSET ; bpf_core_section_ref sec ; FOR_EACH_VEC_ELT ( * bpf_core_sections , i , sec ) if ( strcmp ( sec -> name , section_name ) == 0 ) { vec_safe_push ( sec -> relocs , bpfcr ) ; return ; } sec = ggc_cleared_alloc < bpf_core_section_t > ( ) ; ctf_add_string ( ctfc , section_name , & sec -> name_offset , CTF_AUX_STRTAB ) ; if ( strcmp ( section_name , "" ) ) ctfc -> ctfc_aux_strlen += strlen ( section_name ) + 1 ; sec -> name = section_name ; vec_alloc ( sec -> relocs , 1 ) ; vec_safe_push ( sec -> relocs , bpfcr ) ; vec_safe_push ( bpf_core_sections , sec ) ; } </s>

Create a new BPF CO-RE relocation record , and add it to the appropriate CO-RE section .


<s> void HexagonSubtarget :: adjustSchedDependency ( SUnit * Src , int SrcOpIdx , SUnit * Dst , int DstOpIdx , SDep & Dep ) const { MachineInstr * SrcInst = Src -> getInstr ( ) ; MachineInstr * DstInst = Dst -> getInstr ( ) ; if ( ! Src -> isInstr ( ) || ! Dst -> isInstr ( ) ) return ; const HexagonInstrInfo * QII = getInstrInfo ( ) ; SmallSet < SUnit * , 4 > ExclSrc ; SmallSet < SUnit * , 4 > ExclDst ; if ( QII -> canExecuteInBundle ( * SrcInst , * DstInst ) && isBestZeroLatency ( Src , Dst , QII , ExclSrc , ExclDst ) ) { Dep . setLatency ( 0 ) ; return ; } if ( ! hasV60Ops ( ) ) return ; if ( DstInst -> isCopy ( ) ) Dep . setLatency ( 0 ) ; if ( ( DstInst -> isRegSequence ( ) || DstInst -> isCopy ( ) ) && Dst -> NumSuccs == 1 ) { Register DReg = DstInst -> getOperand ( 0 ) . getReg ( ) ; MachineInstr * DDst = Dst -> Succs [ 0 ] . getSUnit ( ) -> getInstr ( ) ; unsigned UseIdx = - 1 ; for ( unsigned OpNum = 0 ; OpNum < DDst -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = DDst -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . getReg ( ) && MO . isUse ( ) && MO . getReg ( ) == DReg ) { UseIdx = OpNum ; break ; } } int DLatency = ( InstrInfo . getOperandLatency ( & InstrItins , * SrcInst , 0 , * DDst , UseIdx ) ) ; DLatency = std :: max ( DLatency , 0 ) ; Dep . setLatency ( ( unsigned ) DLatency ) ; } ExclSrc . clear ( ) ; ExclDst . clear ( ) ; if ( EnableDotCurSched && QII -> isToBeScheduledASAP ( * SrcInst , * DstInst ) && isBestZeroLatency ( Src , Dst , QII , ExclSrc , ExclDst ) ) { Dep . setLatency ( 0 ) ; return ; } updateLatency ( * SrcInst , * DstInst , Dep ) ; } </s>

Perform target specific adjustments to the latency of a schedule dependency .


<s> SDValue R600TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; SmallVector < ISD :: InputArg , 8 > LocalIns ; if ( AMDGPU :: isShader ( CallConv ) ) { CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForCall ( CallConv , isVarArg ) ) ; } else { analyzeFormalArgumentsCompute ( CCInfo , Ins ) ; } for ( unsigned i = 0 , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const ISD :: InputArg & In = Ins [ i ] ; EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector ( ) ) { MemVT = MemVT . getVectorElementType ( ) ; } if ( AMDGPU :: isShader ( CallConv ) ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & R600 :: R600_Reg128RegClass ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , AMDGPUASI . PARAM_I_ADDRESS ) ; ISD :: LoadExtType Ext = ISD :: NON_EXTLOAD ; if ( MemVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) { Ext = ISD :: SEXTLOAD ; } unsigned ValBase = ArgLocs [ In . getOrigArgIndex ( ) ] . getLocMemOffset ( ) ; unsigned PartOffset = VA . getLocMemOffset ( ) ; unsigned Alignment = MinAlign ( VT . getStoreSize ( ) , PartOffset ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) , PartOffset - ValBase ) ; SDValue Arg = DAG . getLoad ( ISD :: UNINDEXED , Ext , VT , DL , Chain , DAG . getConstant ( PartOffset , DL , MVT :: i32 ) , DAG . getUNDEF ( MVT :: i32 ) , PtrInfo , MemVT , Alignment , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; InVals . push_back ( Arg ) ; } return Chain ; } </s>


<s> static bool ix86_hard_regno_scratch_ok ( unsigned int regno ) { return ( ! cfun -> machine -> no_caller_saved_registers || ( ! epilogue_completed && df_regs_ever_live_p ( regno ) ) ) ; } </s>

Return nonzero if register REGNO can be used as a scratch register in peephole2 .


<s> MachineBasicBlock :: iterator SICFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static rtx nios2_function_value ( const_tree ret_type , const_tree fn ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( TYPE_MODE ( ret_type ) , FIRST_RETVAL_REGNO ) ; } </s>


"rs6000_can_inline_p:, caller %s, callee %s, %s inline\n"

Hook to determine if one function can safely inline another .


<s> static void indirect_thunk_name ( char name [ 32 ] , unsigned int regno , enum indirect_thunk_prefix need_prefix , bool ret_p ) { if ( regno != INVALID_REGNUM && regno != CX_REG && ret_p ) gcc_unreachable ( ) ; if ( USE_HIDDEN_LINKONCE ) { const char * prefix ; if ( need_prefix == indirect_thunk_prefix_nt && regno != INVALID_REGNUM ) { prefix = "_nt" ; } else prefix = "" ; const char * ret = ret_p ? "return" : "indirect" ; if ( regno != INVALID_REGNUM ) { const char * reg_prefix ; if ( LEGACY_INT_REGNO_P ( regno ) ) reg_prefix = TARGET_64BIT ? "r" : "e" ; else reg_prefix = "" ; sprintf ( name , "__x86_%s_thunk%s_%s%s" , ret , prefix , reg_prefix , reg_names [ regno ] ) ; } else sprintf ( name , "__x86_%s_thunk%s" , ret , prefix ) ; } else { if ( regno != INVALID_REGNUM ) ASM_GENERATE_INTERNAL_LABEL ( name , "LITR" , regno ) ; else { if ( ret_p ) ASM_GENERATE_INTERNAL_LABEL ( name , "LRT" , 0 ) ; else ASM_GENERATE_INTERNAL_LABEL ( name , "LIT" , 0 ) ; } } } </s>

Fills in the label name that should be used for the indirect thunk .


<s> inline bool isKMergeMasked ( uint64_t TSFlags ) { return isKMasked ( TSFlags ) && ( TSFlags & X86II :: EVEX_Z ) == 0 ; } </s>

Returns true iff the group of FMA opcodes holds k-merge-masked opcodes .


<s> unsigned SIRegisterInfo :: getRegPressureSetLimit ( const MachineFunction & MF , unsigned Idx ) const { if ( Idx == getVGPRPressureSet ( ) || Idx == getAGPRPressureSet ( ) ) return getRegPressureLimit ( & AMDGPU :: VGPR_32RegClass , const_cast < MachineFunction & > ( MF ) ) ; if ( Idx == getSGPRPressureSet ( ) ) return getRegPressureLimit ( & AMDGPU :: SGPR_32RegClass , const_cast < MachineFunction & > ( MF ) ) ; return AMDGPURegisterInfo :: getRegPressureSetLimit ( MF , Idx ) ; } </s>

Get the register unit pressure limit for this dimension .


<s> static void sparc_emit_probe_stack_range ( HOST_WIDE_INT first , HOST_WIDE_INT size ) { rtx g1 = gen_rtx_REG ( Pmode , 1 ) ; if ( size <= PROBE_INTERVAL ) { emit_move_insn ( g1 , GEN_INT ( first ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , g1 , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , g1 ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , g1 , - size ) ) ; } else if ( size <= 5 * PROBE_INTERVAL ) { HOST_WIDE_INT i ; emit_move_insn ( g1 , GEN_INT ( first + PROBE_INTERVAL ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , g1 , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , g1 ) ) ) ; emit_stack_probe ( g1 ) ; for ( i = 2 * PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) { emit_insn ( gen_rtx_SET ( VOIDmode , g1 , plus_constant ( Pmode , g1 , - PROBE_INTERVAL ) ) ) ; emit_stack_probe ( g1 ) ; } emit_stack_probe ( plus_constant ( Pmode , g1 , ( i - PROBE_INTERVAL ) - size ) ) ; } else { HOST_WIDE_INT rounded_size ; rtx g4 = gen_rtx_REG ( Pmode , 4 ) ; emit_move_insn ( g1 , GEN_INT ( first ) ) ; rounded_size = size & - PROBE_INTERVAL ; emit_move_insn ( g4 , GEN_INT ( rounded_size ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , g1 , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , g1 ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , g4 , gen_rtx_MINUS ( Pmode , g1 , g4 ) ) ) ; if ( TARGET_ARCH64 ) emit_insn ( gen_probe_stack_rangedi ( g1 , g1 , g4 ) ) ; else emit_insn ( gen_probe_stack_rangesi ( g1 , g1 , g4 ) ) ; if ( size != rounded_size ) emit_stack_probe ( plus_constant ( Pmode , g4 , rounded_size - size ) ) ; } emit_insn ( gen_blockage ( ) ) ; } </s>

Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE , inclusive . These are offsets from the current stack pointer . Note that we do n't use the REG+REG addressing mode for the probes because of the stack bias in 64-bit mode . And it does n't really buy us anything so the advantages of having a single code win here .


<s> const MCPhysReg * AMDGPURegisterInfo :: getCalleeSavedRegs ( const MachineFunction * ) const { return & CalleeSavedReg ; } </s>


<s>
SDValue
LEGTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
)
const
{
if
(
isVarArg
)
{
report_fatal_error
(
"VarArg not supported"
)
;
}
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_LEG
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
<
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
{
RetOps
.
push_back
(
Flag
)
;
}
return
DAG
.
getNode
(
LEGISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .