<s> int shl_sext_kind ( rtx left_rtx , rtx size_rtx , int * costp ) { int left , size , insize , ext ; int cost = 0 , best_cost ; int kind ; left = INTVAL ( left_rtx ) ; size = INTVAL ( size_rtx ) ; insize = size - left ; gcc_assert ( insize > 0 ) ; kind = 0 ; best_cost = ashl_lshr_seq [ 32 - insize ] . insn_count + ashl_lshr_seq [ 32 - size ] . insn_count ; if ( size <= 16 ) { cost = ashl_lshr_seq [ 16 - insize ] . insn_count + 1 + ashl_lshr_seq [ 16 - size ] . insn_count ; if ( cost < best_cost ) { kind = 5 ; best_cost = cost ; } } for ( ext = 16 ; ext >= insize ; ext -= 8 ) { if ( ext <= size ) { cost = ext_ashl_lshr_seq [ ext - insize ] . insn_count + 1 + ashl_lshr_seq [ size - ext ] . insn_count ; if ( cost < best_cost ) { kind = ext / ( unsigned ) 8 ; best_cost = cost ; } } if ( EXT_SHIFT_SIGNED ( size - ext ) ) cost = ext_ashl_lshr_seq [ ext - insize ] . insn_count + ext_ashl_lshr_seq [ size - ext ] . insn_count + 1 ; else if ( size <= 16 ) cost = ext_ashl_lshr_seq [ ext - insize ] . insn_count + 1 + ext_ashl_lshr_seq [ size > ext ? size - ext : ext - size ] . insn_count + 1 ; else continue ; if ( cost < best_cost ) { kind = ext / ( unsigned ) 8 + 2 ; best_cost = cost ; } } if ( insize < 8 ) { cost = 3 + ashl_lshr_seq [ left ] . insn_count ; if ( cost < best_cost ) { kind = 6 ; best_cost = cost ; } if ( left < 31 ) { cost = 3 + ext_ashl_lshr_seq [ left + 1 ] . insn_count + 1 ; if ( cost < best_cost ) { kind = 7 ; best_cost = cost ; } } } if ( TARGET_DYNSHIFT ) { cost = ashl_lshr_seq [ 32 - insize ] . insn_count + 1 + SH_DYNAMIC_SHIFT_COST ; if ( cost < best_cost ) { kind = 0 ; best_cost = cost ; } } if ( costp ) * costp = cost ; return kind ; } </s>

Try to find a good way to implement the combiner pattern [ ( set ( match_operand : SI 0 `` register_operand '' `` =r '' ) ( sign_extract : SI ( ashift : SI ( match_operand : SI 1 `` register_operand '' `` r '' ) ( match_operand : SI 2 `` const_int_operand '' `` n '' ) ( match_operand : SI 3 `` const_int_operand '' `` n '' ) ( const_int 0 ) ) ) ( clobber ( reg : SI T_REG ) ) ] LEFT_RTX is operand 2 in the above pattern , and SIZE_RTX is operand 3. return 0 for simple left / right shift combination . return 1 for left shift / 8 bit sign extend / left shift . return 2 for left shift / 16 bit sign extend / left shift . return 3 for left shift / 8 bit sign extend / shift / sign extend . return 4 for left shift / 16 bit sign extend / shift / sign extend . return 5 for left shift / 16 bit sign extend / right shift return 6 for < 8 bit sign extend / left shift . return 7 for < 8 bit sign extend / left shift / single right shift . If COSTP is nonzero , assign the calculated cost to * COSTP .


<s> int leaf_return_peephole_ok ( ) { return ( actual_fsize == 0 ) ; } </s>

Return nonzero if a return peephole merging return with setting of output register is ok .


<s> void AArch64PassConfig :: addPreEmitPass ( ) { if ( EnableA53Fix835769 ) addPass ( createAArch64A53Fix835769 ( ) ) ; addPass ( createAArch64BranchRelaxation ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getSubtarget < AArch64Subtarget > ( ) . isTargetMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool PPCFunctionInfo :: isLiveInZExt ( unsigned VReg ) const { for ( const std :: pair < unsigned , ISD :: ArgFlagsTy > & LiveIn : LiveInAttrs ) if ( LiveIn . first == VReg ) return LiveIn . second . isZExt ( ) ; return false ; } </s>

This function returns true if the specified vreg is a live-in register and zero-extended .


<s> void AMDGPUPassConfig :: addCodeGenPrepare ( ) { if ( TM -> getTargetTriple ( ) . getArch ( ) == Triple :: amdgcn ) addPass ( createAMDGPUAnnotateKernelFeaturesPass ( ) ) ; if ( TM -> getTargetTriple ( ) . getArch ( ) == Triple :: amdgcn && EnableLowerKernelArguments ) addPass ( createAMDGPULowerKernelArgumentsPass ( ) ) ; TargetPassConfig :: addCodeGenPrepare ( ) ; if ( isPassEnabled ( EnableLoadStoreVectorizer ) ) addPass ( createLoadStoreVectorizerPass ( ) ) ; addPass ( createLowerSwitchPass ( ) ) ; } </s>

Add pass to prepare the LLVM IR for code generation .


"********** Replace Physical Registers **********\n"

"LiveIntervals shouldn't be active yet!"

runOnMachineFunction - Emit the function body .


"MIPS16 PIC for ABIs other than o32 and o64"

"hard-float MIPS16 code for ABIs other than o32 and o64"

Set up the target-dependent global state for ISA mode COMPRESSION_MODE , which is either MASK_MIPS16 or MASK_MICROMIPS .


<s> bool BPFDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintCode ) { default : return true ; case InlineAsm :: Constraint_m : if ( ! SelectAddr ( Op , Op0 , Op1 ) ) return true ; break ; } SDLoc DL ( Op ) ; SDValue AluOp = CurDAG -> getTargetConstant ( ISD :: ADD , DL , MVT :: i32 ) ; ; OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; OutOps . push_back ( AluOp ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> bool AMDGPUPromoteKernelArguments :: runOnFunction ( Function & F ) { MemorySSA & MSSA = getAnalysis < MemorySSAWrapperPass > ( ) . getMSSA ( ) ; AliasAnalysis & AA = getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; return run ( F , MSSA , AA ) ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void Thumb1FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const Thumb1InstrInfo & TII = * static_cast < const Thumb1InstrInfo * > ( STI . getInstrInfo ( ) ) ; const Thumb1RegisterInfo * RegInfo = static_cast < const Thumb1RegisterInfo * > ( STI . getRegisterInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; DebugLoc dl = Old -> getDebugLoc ( ) ; unsigned Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { unsigned Align = getStackAlignment ( ) ; Amount = ( Amount + Align - 1 ) / Align * Align ; unsigned Opc = Old -> getOpcode ( ) ; if ( Opc == ARM :: ADJCALLSTACKDOWN || Opc == ARM :: tADJCALLSTACKDOWN ) { emitSPUpdate ( MBB , I , TII , dl , * RegInfo , - Amount ) ; } else { assert ( Opc == ARM :: ADJCALLSTACKUP || Opc == ARM :: tADJCALLSTACKUP ) ; emitSPUpdate ( MBB , I , TII , dl , * RegInfo , Amount ) ; } } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static int ep_memory_offset ( enum machine_mode mode , int unsignedp ATTRIBUTE_UNUSED ) { int max_offset = 0 ; switch ( mode ) { case QImode : if ( TARGET_SMALL_SLD ) max_offset = ( 1 << 4 ) ; else if ( TARGET_V850E && ( ( unsignedp && ! TARGET_US_BIT_SET ) || ( ! unsignedp && TARGET_US_BIT_SET ) ) ) max_offset = ( 1 << 4 ) ; else max_offset = ( 1 << 7 ) ; break ; case HImode : if ( TARGET_SMALL_SLD ) max_offset = ( 1 << 5 ) ; else if ( TARGET_V850E && ( ( unsignedp && ! TARGET_US_BIT_SET ) || ( ! unsignedp && TARGET_US_BIT_SET ) ) ) max_offset = ( 1 << 5 ) ; else max_offset = ( 1 << 8 ) ; break ; case SImode : case SFmode : max_offset = ( 1 << 8 ) ; break ; default : break ; } return max_offset ; } </s>

Return maximum offset supported for a short EP memory reference of mode MODE and signedness UNSIGNEDP .


<s> BitVector OR1KRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; Reserved . set ( OR1K :: R0 ) ; Reserved . set ( OR1K :: R1 ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( OR1K :: R2 ) ; Reserved . set ( OR1K :: R9 ) ; Reserved . set ( OR1K :: R10 ) ; Reserved . set ( OR1K :: R16 ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( getBaseRegister ( ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void s390_expand_merge ( rtx target , rtx src1 , rtx src2 , bool high_p ) { machine_mode mode = GET_MODE ( target ) ; opt_machine_mode opt_mode_2x = mode_for_vector ( GET_MODE_INNER ( mode ) , 2 * GET_MODE_NUNITS ( mode ) ) ; gcc_assert ( opt_mode_2x . exists ( ) ) ; machine_mode mode_double_nelts = opt_mode_2x . require ( ) ; rtx constv = s390_expand_merge_perm_const ( mode , high_p ) ; src1 = force_reg ( GET_MODE ( src1 ) , src1 ) ; src2 = force_reg ( GET_MODE ( src2 ) , src2 ) ; rtx x = gen_rtx_VEC_CONCAT ( mode_double_nelts , src1 , src2 ) ; x = gen_rtx_VEC_SELECT ( mode , x , constv ) ; emit_insn ( gen_rtx_SET ( target , x ) ) ; } </s>

Emit RTL to implement a vector merge operation of SRC1 and SRC2 which creates the result in TARGET . HIGH_P determines whether a merge hi or lo will be generated .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
Kind
==
Register
&&
"Invalid type access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , is64bit ) , DataLayout ( Subtarget . getDataLayout ( ) ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) { } </s>


<s>
bool
HexagonFrameLowering
::
spillCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
->
getTarget
(
)
.
getInstrInfo
(
)
;
if
(
CSI
.
empty
(
)
)
{
return
false
;
}
bool
ContiguousRegs
=
true
;
for
(
unsigned
i
=
0
;
i
<
CSI
.
size
(
)
;
++
i
)
{
unsigned
Reg
=
CSI
[
i
]
.
getReg
(
)
;
const
uint16_t
*
SuperReg
=
TRI
->
getSuperRegisters
(
Reg
)
;
assert
(
SuperReg
[
0
]
&&
!
SuperReg
[
1
]
&&
"Expected exactly one superreg"
)
;
bool
CanUseDblStore
=
false
;
const
TargetRegisterClass
*
SuperRegClass
=
0
;
if
(
ContiguousRegs
&&
(
i
<
CSI
.
size
(
)
1
)
)
{
const
uint16_t
*
SuperRegNext
=
TRI
->
getSuperRegisters
(
CSI
[
i
+
1
]
.
getReg
(
)
)
;
assert
(
SuperRegNext
[
0
]
&&
!
SuperRegNext
[
1
]
&&
"Expected exactly one superreg"
)
;
SuperRegClass
=
TRI
->
getMinimalPhysRegClass
(
SuperReg
[
0
]
)
;
CanUseDblStore
=
(
SuperRegNext
[
0
]
==
SuperReg
[
0
]
)
;
}
if
(
CanUseDblStore
)
{
TII
.
storeRegToStackSlot
(
MBB
,
MI
,
SuperReg
[
0
]
,
true
,
CSI
[
i
+
1
]
.
getFrameIdx
(
)
,
SuperRegClass
,
TRI
)
;
MBB
.
addLiveIn
(
SuperReg
[
0
]
)
;
++
i
;
}
else
{
ContiguousRegs
=
false
;
const
TargetRegisterClass
*
RC
=
TRI
->
getMinimalPhysRegClass
(
Reg
)
;
TII
.
storeRegToStackSlot
(
MBB
,
MI
,
Reg
,
true
,
CSI
[
i
]
.
getFrameIdx
(
)
,
RC
,
TRI
)
;
MBB
.
addLiveIn
(
Reg
)
;
}
}
return
true
;
}
</s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s>
void
RISCVAsmBackend
::
relaxInstruction
(
const
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
,
MCInst
&
Res
)
const
{
switch
(
Inst
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Opcode not expected!"
)
;
case
RISCV
::
C_BEQZ
:
Res
.
setOpcode
(
RISCV
::
BEQ
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
Res
.
addOperand
(
MCOperand
::
createReg
(
RISCV
::
X0
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
1
)
)
;
break
;
case
RISCV
::
C_BNEZ
:
Res
.
setOpcode
(
RISCV
::
BNE
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
Res
.
addOperand
(
MCOperand
::
createReg
(
RISCV
::
X0
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
1
)
)
;
break
;
case
RISCV
::
C_J
:
Res
.
setOpcode
(
RISCV
::
JAL
)
;
Res
.
addOperand
(
MCOperand
::
createReg
(
RISCV
::
X0
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
break
;
case
RISCV
::
C_JAL
:
Res
.
setOpcode
(
RISCV
::
JAL
)
;
Res
.
addOperand
(
MCOperand
::
createReg
(
RISCV
::
X1
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
break
;
}
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF ; } </s>

Return information about object file lowering .


<s>
void
PPCInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
if
(
PPC
::
F8RCRegClass
.
contains
(
DestReg
)
&&
PPC
::
VSLRCRegClass
.
contains
(
SrcReg
)
)
{
unsigned
SuperReg
=
TRI
->
getMatchingSuperReg
(
DestReg
,
PPC
::
sub_64
,
&
PPC
::
VSRCRegClass
)
;
if
(
SrcReg
==
SuperReg
)
return
;
DestReg
=
SuperReg
;
}
else
if
(
PPC
::
VRRCRegClass
.
contains
(
DestReg
)
&&
PPC
::
VSHRCRegClass
.
contains
(
SrcReg
)
)
{
unsigned
SuperReg
=
TRI
->
getMatchingSuperReg
(
DestReg
,
PPC
::
sub_128
,
&
PPC
::
VSRCRegClass
)
;
if
(
SrcReg
==
SuperReg
)
return
;
DestReg
=
SuperReg
;
}
else
if
(
PPC
::
F8RCRegClass
.
contains
(
SrcReg
)
&&
PPC
::
VSLRCRegClass
.
contains
(
DestReg
)
)
{
unsigned
SuperReg
=
TRI
->
getMatchingSuperReg
(
SrcReg
,
PPC
::
sub_64
,
&
PPC
::
VSRCRegClass
)
;
if
(
DestReg
==
SuperReg
)
return
;
SrcReg
=
SuperReg
;
}
else
if
(
PPC
::
VRRCRegClass
.
contains
(
SrcReg
)
&&
PPC
::
VSHRCRegClass
.
contains
(
DestReg
)
)
{
unsigned
SuperReg
=
TRI
->
getMatchingSuperReg
(
SrcReg
,
PPC
::
sub_128
,
&
PPC
::
VSRCRegClass
)
;
if
(
DestReg
==
SuperReg
)
return
;
SrcReg
=
SuperReg
;
}
unsigned
Opc
;
if
(
PPC
::
GPRCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
OR
;
else
if
(
PPC
::
G8RCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
OR8
;
else
if
(
PPC
::
F4RCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
FMR
;
else
if
(
PPC
::
CRRCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
MCRF
;
else
if
(
PPC
::
VRRCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
VOR
;
else
if
(
PPC
::
VSRCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
XXLOR
;
else
if
(
PPC
::
CRBITRCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
CROR
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
const
MCInstrDesc
&
MCID
=
get
(
Opc
)
;
if
(
MCID
.
getNumOperands
(
)
==
3
)
BuildMI
(
MBB
,
I
,
DL
,
MCID
,
DestReg
)
.
addReg
(
SrcReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
BuildMI
(
MBB
,
I
,
DL
,
MCID
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>

PowerPC
PPC
PPC::F8RCRegClass
PPC::VSLRCRegClass
PPC::sub_64
PPC::VSRCRegClass
PPC::VRRCRegClass
PPC::VSHRCRegClass
PPC::sub_128
PPC::VSRCRegClass
PPC::F8RCRegClass
PPC::VSLRCRegClass
PPC::sub_64
PPC::VSRCRegClass
PPC::VRRCRegClass
PPC::VSHRCRegClass
PPC::sub_128
PPC::VSRCRegClass
PPC::GPRCRegClass
PPC::OR
PPC::G8RCRegClass
PPC::OR8
PPC::F4RCRegClass
PPC::FMR
PPC::CRRCRegClass
PPC::MCRF
PPC::VRRCRegClass
PPC::VOR
PPC::VSRCRegClass
PPC::XXLOR
PPC::CRBITRCRegClass
PPC::CROR
"Impossible reg-to-reg copy"
3


<s> SDNode * PPCDAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * PPCSubTarget -> getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; const Module * M = MF -> getFunction ( ) . getParent ( ) ; DebugLoc dl ; if ( PPCLowering -> getPointerTy ( CurDAG -> getDataLayout ( ) ) == MVT :: i32 ) { if ( PPCSubTarget -> isTargetELF ( ) ) { GlobalBaseReg = PPC :: R30 ; if ( M -> getPICLevel ( ) == PICLevel :: SmallPIC ) { BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MoveGOTtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; MF -> getInfo < PPCFunctionInfo > ( ) -> setUsesPICBase ( true ) ; } else { BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; unsigned TempReg = RegInfo -> createVirtualRegister ( & PPC :: GPRCRegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: UpdateGBR ) , GlobalBaseReg ) . addReg ( TempReg , RegState :: Define ) . addReg ( GlobalBaseReg ) ; MF -> getInfo < PPCFunctionInfo > ( ) -> setUsesPICBase ( true ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: GPRC_and_GPRC_NOR0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; } } else { MF -> getInfo < PPCFunctionInfo > ( ) -> setShrinkWrapDisabled ( true ) ; GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: G8RC_and_G8RC_NOX0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR8 ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR8 ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , PPCLowering -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

PowerPC PPC PPC PPC MVT::i32 PPC PPC::R30 PPC::MoveGOTtoLR PPC::MFLR PPC PPC::MovePCtoLR PPC::MFLR PPC::GPRCRegClass PPC::UpdateGBR PPC PPC::GPRC_and_GPRC_NOR0RegClass PPC::MovePCtoLR PPC::MFLR PPC PPC::G8RC_and_G8RC_NOX0RegClass PPC::MovePCtoLR8 PPC::MFLR8 PPC


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createVideocoreELFObjectWriter ( OS , OSType , true ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static bool prologue_saved_reg_p ( unsigned regno ) { gcc_assert ( GP_REG_P ( regno ) ) ; if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) return true ; if ( regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed ) return true ; if ( regno == PIC_OFFSET_TABLE_REGNUM && crtl -> uses_pic_offset_table ) return true ; if ( regno == RA_REGNO && df_regs_ever_live_p ( RA_REGNO ) ) return true ; return false ; } </s>

Return true if REGNO should be saved in the prologue .


<s> static reg_class_t nios2_preferred_reload_class ( rtx x ATTRIBUTE_UNUSED , reg_class_t regclass ) { return regclass == NO_REGS ? GENERAL_REGS : regclass ; } </s>


<s>
static
void
init_device
(
)
{
init_hsa_runtime_functions
(
)
;
XHSA
(
hsa_fns
.
hsa_init_fn
(
)
,
"Initialize run-time"
)
;
XHSA_CMP
(
hsa_fns
.
hsa_iterate_agents_fn
(
get_gpu_agent
,
)
,
status
==
HSA_STATUS_SUCCESS
||
status
==
HSA_STATUS_INFO_BREAK
,
"Find a device"
)
;
uint32_t
queue_size
=
0
;
XHSA
(
hsa_fns
.
hsa_agent_get_info_fn
(
device
,
HSA_AGENT_INFO_QUEUE_MAX_SIZE
,
&
queue_size
)
,
"Find max queue size"
)
;
XHSA
(
hsa_fns
.
hsa_queue_create_fn
(
device
,
queue_size
,
HSA_QUEUE_TYPE_SINGLE
,
,
,
UINT32_MAX
,
UINT32_MAX
,
&
queue
)
,
"Set up a device queue"
)
;
XHSA_CMP
(
hsa_fns
.
hsa_agent_iterate_regions_fn
(
device
,
get_kernarg_region
,
)
,
status
==
HSA_STATUS_SUCCESS
||
status
==
HSA_STATUS_INFO_BREAK
,
"Locate kernargs memory"
)
;
XHSA_CMP
(
hsa_fns
.
hsa_agent_iterate_regions_fn
(
device
,
get_heap_region
,
)
,
status
==
HSA_STATUS_SUCCESS
||
status
==
HSA_STATUS_INFO_BREAK
,
"Locate device memory"
)
;
}
</s>

Initialize the HSA Runtime library and GPU device .

gcn
"Initialize run-time"
"Find a device"
0
"Find max queue size"
"Set up a device queue"
"Locate kernargs memory"
"Locate device memory"


"Altivec is not implemented on AIX yet."

Return a mask of call-preserved registers for the given calling convention on the current function .


"Checking if value is in small-data, -G"

Return true if this global address should be placed into small data/bss section .


<s> static bool rs6000_legitimate_address_p ( machine_mode mode , rtx x , bool reg_ok_strict ) { bool reg_offset_p = reg_offset_addressing_ok_p ( mode ) ; if ( VECTOR_MEM_ALTIVEC_P ( mode ) && GET_CODE ( x ) == AND && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT && INTVAL ( XEXP ( x , 1 ) ) == - 16 ) x = XEXP ( x , 0 ) ; if ( TARGET_ELF && RS6000_SYMBOL_REF_TLS_P ( x ) ) return 0 ; if ( legitimate_indirect_address_p ( x , reg_ok_strict ) ) return 1 ; if ( TARGET_UPDATE && ( GET_CODE ( x ) == PRE_INC || GET_CODE ( x ) == PRE_DEC ) && mode_supports_pre_incdec_p ( mode ) && legitimate_indirect_address_p ( XEXP ( x , 0 ) , reg_ok_strict ) ) return 1 ; if ( virtual_stack_registers_memory_p ( x ) ) return 1 ; if ( reg_offset_p && legitimate_small_data_p ( mode , x ) ) return 1 ; if ( reg_offset_p && legitimate_constant_pool_address_p ( x , mode , reg_ok_strict || lra_in_progress ) ) return 1 ; if ( mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX_TIMODE ) return 0 ; if ( ! reg_ok_strict && reg_offset_p && GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 0 ) ) == REG && ( XEXP ( x , 0 ) == virtual_stack_vars_rtx || XEXP ( x , 0 ) == arg_pointer_rtx ) && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) return 1 ; if ( rs6000_legitimate_offset_address_p ( mode , x , reg_ok_strict , false ) ) return 1 ; if ( mode != TFmode && mode != TDmode && ( ( TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT ) || TARGET_POWERPC64 || ( mode != DFmode && mode != DDmode ) || ( TARGET_E500_DOUBLE && mode != DDmode ) ) && ( TARGET_POWERPC64 || mode != DImode ) && ( mode != TImode || VECTOR_MEM_VSX_P ( TImode ) ) && mode != PTImode && ! avoiding_indexed_address_p ( mode ) && legitimate_indexed_address_p ( x , reg_ok_strict ) ) return 1 ; if ( TARGET_UPDATE && GET_CODE ( x ) == PRE_MODIFY && mode_supports_pre_modify_p ( mode ) && legitimate_indirect_address_p ( XEXP ( x , 0 ) , reg_ok_strict ) && ( rs6000_legitimate_offset_address_p ( mode , XEXP ( x , 1 ) , reg_ok_strict , false ) || ( ! avoiding_indexed_address_p ( mode ) && legitimate_indexed_address_p ( XEXP ( x , 1 ) , reg_ok_strict ) ) ) && rtx_equal_p ( XEXP ( XEXP ( x , 1 ) , 0 ) , XEXP ( x , 0 ) ) ) return 1 ; if ( reg_offset_p && legitimate_lo_sum_address_p ( mode , x , reg_ok_strict ) ) return 1 ; return 0 ; } </s>

TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression that is a valid memory address for an instruction . The MODE argument is the machine mode for the MEM expression that wants to use this address . On the RS/6000 , there are four valid address : a SYMBOL_REF that refers to a constant pool entry of an address ( or the sum of it plus a constant ) , a short ( 16-bit signed ) constant plus a register , the sum of two registers , or a register indirect , possibly with an auto-increment . For DFmode , DDmode and DImode with a constant plus register , we must ensure that both words are addressable or PowerPC64 with offset word aligned . For modes spanning multiple registers ( DFmode and DDmode in 32-bit GPRs , 32-bit DImode , TImode , TFmode , TDmode ) , indexed addressing can not be used because adjacent memory cells are accessed by adding word-sized offsets during assembly output .


<s> void ConvergingVLIWScheduler :: releaseTopNode ( SUnit * SU ) { for ( const SDep & PI : SU -> Preds ) { unsigned PredReadyCycle = PI . getSUnit ( ) -> TopReadyCycle ; unsigned MinLatency = PI . getLatency ( ) ; Top . MaxMinLatency = std :: max ( MinLatency , Top . MaxMinLatency ) ; if ( SU -> TopReadyCycle < PredReadyCycle + MinLatency ) SU -> TopReadyCycle = PredReadyCycle + MinLatency ; } if ( ! SU -> isScheduled ) Top . releaseNode ( SU , SU -> TopReadyCycle ) ; } </s>

SU has had all predecessor dependencies resolved .


<s> void GCNPassConfig :: addOptimizedRegAlloc ( FunctionPass * RegAllocPass ) { TargetPassConfig :: addOptimizedRegAlloc ( RegAllocPass ) ; } </s>

addOptimizedRegAlloc - Add passes related to register allocation .


<s> bool SITargetLowering :: requiresUniformRegister ( MachineFunction & MF , const Value * V ) const { if ( const CallInst * CI = dyn_cast < CallInst > ( V ) ) { if ( isa < InlineAsm > ( CI -> getCalledValue ( ) ) ) { const SIRegisterInfo * SIRI = Subtarget -> getRegisterInfo ( ) ; ImmutableCallSite CS ( CI ) ; TargetLowering :: AsmOperandInfoVector TargetConstraints = ParseConstraints ( MF . getDataLayout ( ) , Subtarget -> getRegisterInfo ( ) , CS ) ; for ( auto & TC : TargetConstraints ) { if ( TC . Type == InlineAsm :: isOutput ) { ComputeConstraintToUse ( TC , SDValue ( ) ) ; unsigned AssignedReg ; const TargetRegisterClass * RC ; std :: tie ( AssignedReg , RC ) = getRegForInlineAsmConstraint ( SIRI , TC . ConstraintCode , TC . ConstraintVT ) ; if ( RC ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( AssignedReg != 0 && SIRI -> isSGPRReg ( MRI , AssignedReg ) ) return true ; else if ( SIRI -> isSGPRClass ( RC ) ) return true ; } } } } } SmallPtrSet < const Value * , 16 > Visited ; return hasCFUser ( V , Visited , Subtarget -> getWavefrontSize ( ) ) ; } </s>

Allows target to decide about the register class of the specific value that is live outside the defining block .


<s> bool MSP430FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MSP430MachineFunctionInfo * MFI = MF . getInfo < MSP430MachineFunctionInfo > ( ) ; MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ; for ( const CalleeSavedInfo & I : llvm :: reverse ( CSI ) ) { unsigned Reg = I . getReg ( ) ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( MSP430 :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ; } return true ; } </s>


<s> static void emit_store_conditional ( enum machine_mode mode , rtx res , rtx mem , rtx val ) { rtx ( * fn ) ( rtx , rtx , rtx ) = NULL ; if ( mode == SImode ) fn = gen_store_conditional_si ; else if ( mode == DImode ) fn = gen_store_conditional_di ; emit_insn ( fn ( res , mem , val ) ) ; } </s>

A subroutine of the atomic operation splitters . Emit a store-conditional instruction in MODE .


Called through CC_STATUS_INIT , which is invoked by final whenever a label is encountered .


<s> Optional < MCFixupKind > AArch64AsmBackend :: getFixupKind ( StringRef Name ) const { if ( ! TheTriple . isOSBinFormatELF ( ) ) return None ; unsigned Type = llvm :: StringSwitch < unsigned > ( Name ) . Case ( "BFD_RELOC_NONE" , ELF :: R_AARCH64_NONE ) . Case ( "BFD_RELOC_16" , ELF :: R_AARCH64_ABS16 ) . Case ( "BFD_RELOC_32" , ELF :: R_AARCH64_ABS32 ) . Case ( "BFD_RELOC_64" , ELF :: R_AARCH64_ABS64 ) . Default ( - 1u ) ; if ( Type == - 1u ) return None ; return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s>
static
void
avr_asm_out_dtor
(
rtx
symbol
,
int
priority
)
{
fputs
(
"\t.global __do_global_dtors\n"
,
asm_out_file
)
;
default_dtor_section_asm_out_destructor
(
symbol
,
priority
)
;
}
</s>

Worker function for TARGET_ASM_DESTRUCTOR .


INSN is being issued in current solution . Account for its impact on the decoder model .


"CFProtection used on invalid architecture!"

This virtual method can be overridden by targets that want to emit something at the start of their file .


<s> const MCExpr * JVMAsmPrinter :: lowerConstant ( const Constant * CV ) { return AsmPrinter :: lowerConstant ( CV ) ; } </s>

Lower the specified LLVM Constant to an MCExpr .


<s> static unsigned int increase_distance ( rtx_insn * prev , rtx_insn * next , unsigned int distance ) { df_ref def , use ; if ( ! prev || ! next ) return distance + ( distance & 1 ) + 2 ; if ( ! DF_INSN_USES ( next ) || ! DF_INSN_DEFS ( prev ) ) return distance + 1 ; FOR_EACH_INSN_USE ( use , next ) FOR_EACH_INSN_DEF ( def , prev ) if ( ! DF_REF_IS_ARTIFICIAL ( def ) && DF_REF_REGNO ( use ) == DF_REF_REGNO ( def ) ) return distance + ( distance & 1 ) + 2 ; return distance + 1 ; } </s>

Increase given DISTANCE in half-cycles according to dependencies between PREV and NEXT instructions . Add 1 half-cycle if there is no dependency and go to next cycle if there is some dependecy .


<s> void MMIXInstPrinter :: printRegName ( raw_ostream & O , unsigned RegNo ) const { O << getRegisterName ( RegNo ) ; } </s>


<s>
const
uint32_t
*
Z80RegisterInfo
::
getCallPreservedMask
(
const
MachineFunction
&
MF
,
CallingConv
::
ID
CC
)
const
{
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
Is24Bit
CSR_EZ80_C_RegMask
:
CSR_Z80_C_RegMask
;
case
CallingConv
::
PreserveAll
:
case
CallingConv
::
Z80_LibCall
:
case
CallingConv
::
Z80_LibCall_AC
:
case
CallingConv
::
Z80_LibCall_BC
:
case
CallingConv
::
Z80_LibCall_C
:
case
CallingConv
::
Z80_LibCall_L
:
return
Is24Bit
CSR_EZ80_AllRegs_RegMask
:
CSR_Z80_AllRegs_RegMask
;
}
}
</s>


<s> enum h8sx_shift_type h8sx_classify_shift ( machine_mode mode , enum rtx_code code , rtx op ) { if ( ! TARGET_H8300SX ) return H8SX_SHIFT_NONE ; switch ( code ) { case ASHIFT : case LSHIFTRT : if ( GET_CODE ( op ) != CONST_INT ) return H8SX_SHIFT_BINARY ; if ( INTVAL ( op ) <= 0 || INTVAL ( op ) >= GET_MODE_BITSIZE ( mode ) ) return H8SX_SHIFT_NONE ; if ( exact_log2 ( INTVAL ( op ) ) >= 0 ) return H8SX_SHIFT_UNARY ; return H8SX_SHIFT_BINARY ; case ASHIFTRT : if ( op == const1_rtx || op == const2_rtx ) return H8SX_SHIFT_UNARY ; return H8SX_SHIFT_NONE ; case ROTATE : if ( GET_CODE ( op ) == CONST_INT && ( INTVAL ( op ) == 1 || INTVAL ( op ) == 2 || INTVAL ( op ) == GET_MODE_BITSIZE ( mode ) - 2 || INTVAL ( op ) == GET_MODE_BITSIZE ( mode ) - 1 ) ) return H8SX_SHIFT_UNARY ; return H8SX_SHIFT_NONE ; default : return H8SX_SHIFT_NONE ; } } </s>

Classify a shift with the given mode and code . OP is the shift amount .


<s> void PPCPassConfig :: addPreRegAlloc ( ) { initializePPCVSXFMAMutatePass ( * PassRegistry :: getPassRegistry ( ) ) ; insertPass ( VSXFMAMutateEarly ? & RegisterCoalescerID : & MachineSchedulerID , & PPCVSXFMAMutateID ) ; addPass ( createPPCTLSDynamicCallPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> bool SIRegisterInfo :: isFrameOffsetLegal ( const MachineInstr * MI , Register BaseReg , int64_t Offset ) const { if ( ! SIInstrInfo :: isMUBUF ( * MI ) ) return false ; int64_t NewOffset = Offset + getMUBUFInstrOffset ( MI ) ; return isUInt < 12 > ( NewOffset ) ; } </s>

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s> void ia64_vms_output_aligned_decl_common ( FILE * file , tree decl , const char * name , unsigned HOST_WIDE_INT size , unsigned int align ) { tree attr = DECL_ATTRIBUTES ( decl ) ; if ( attr ) attr = lookup_attribute ( "common_object" , attr ) ; if ( attr ) { tree id = TREE_VALUE ( TREE_VALUE ( attr ) ) ; const char * name ; if ( TREE_CODE ( id ) == IDENTIFIER_NODE ) name = IDENTIFIER_POINTER ( id ) ; else if ( TREE_CODE ( id ) == STRING_CST ) name = TREE_STRING_POINTER ( id ) ; else abort ( ) ; fprintf ( file , "\t.vms_common\t\"%s\"," , name ) ; } else fprintf ( file , "%s" , COMMON_ASM_OP ) ; assemble_name ( file , name ) ; fprintf ( file , "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u" , size , align / BITS_PER_UNIT ) ; fputc ( '\n' , file ) ; } </s>

Part of the low level implementation of DEC Ada pragma Common_Object .


<s> MCDisassembler :: DecodeStatus X86GenericDisassembler :: getInstruction ( MCInst & instr , uint64_t & size , const MemoryObject & region , uint64_t address , raw_ostream & vStream , raw_ostream & cStream ) const { CommentStream = & cStream ; InternalInstruction internalInstr ; dlog_t loggerFn = logger ; if ( & vStream == & nulls ( ) ) loggerFn = 0 ; int ret = decodeInstruction ( & internalInstr , regionReader , ( const void * ) & region , loggerFn , ( void * ) & vStream , ( const void * ) MII , address , fMode ) ; if ( ret ) { size = internalInstr . readerCursor - address ; return Fail ; } else { size = internalInstr . length ; return ( ! translateInstruction ( instr , internalInstr , this ) ) ? Success : Fail ; } } </s>

Returns the disassembly of a single instruction .


<s> bool AMDGPUInstrInfo :: isCoalescableExtInstr ( const MachineInstr & MI , unsigned & SrcReg , unsigned & DstReg , unsigned & SubIdx ) const { return false ; } </s>

isCoalescableExtInstr - Return true if the instruction is a `` coalescable '' extension instruction .


<s> static bool peek ( struct InternalInstruction * insn , uint8_t & byte ) { uint64_t offset = insn -> readerCursor - insn -> startLocation ; if ( offset >= insn -> bytes . size ( ) ) return true ; byte = insn -> bytes [ offset ] ; return false ; } </s>


<s> void X86WinAllocaExpander :: lower ( MachineInstr * MI , Lowering L ) { DebugLoc DL = MI -> getDebugLoc ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: iterator I = * MI ; int64_t Amount = getWinAllocaAmount ( MI , MRI ) ; if ( Amount == 0 ) { MI -> eraseFromParent ( ) ; return ; } bool Is64Bit = STI -> is64Bit ( ) ; assert ( SlotSize == 4 || SlotSize == 8 ) ; unsigned RegA = ( SlotSize == 8 ) ? X86 :: RAX : X86 :: EAX ; switch ( L ) { case TouchAndSub : assert ( Amount >= SlotSize ) ; BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) ) . addReg ( RegA , RegState :: Undef ) ; Amount -= SlotSize ; if ( ! Amount ) break ; case Sub : assert ( Amount > 0 ) ; if ( Amount == SlotSize ) { BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) ) . addReg ( RegA , RegState :: Undef ) ; } else { BuildMI ( * MBB , I , DL , TII -> get ( getSubOpcode ( Is64Bit , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } break ; case Probe : BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: COPY ) , RegA ) . addReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ; STI -> getFrameLowering ( ) -> emitStackProbe ( * MBB -> getParent ( ) , * MBB , MI , DL , false ) ; break ; } unsigned AmountReg = MI -> getOperand ( 0 ) . getReg ( ) ; MI -> eraseFromParent ( ) ; for ( ; ; ) { if ( ! MRI -> use_empty ( AmountReg ) ) break ; MachineInstr * AmountDef = MRI -> getUniqueVRegDef ( AmountReg ) ; if ( ! AmountDef ) break ; if ( AmountDef -> isCopy ( ) && AmountDef -> getOperand ( 1 ) . isReg ( ) ) AmountReg = AmountDef -> getOperand ( 1 ) . isReg ( ) ; AmountDef -> eraseFromParent ( ) ; break ; } } </s>


<s> static tree alpha_fold_builtin_cmpbge ( unsigned HOST_WIDE_INT opint [ ] , long op_const ) { if ( op_const == 3 ) { int i , val ; for ( i = 0 , val = 0 ; i < 8 ; ++ i ) { unsigned HOST_WIDE_INT c0 = ( opint [ 0 ] >> ( i * 8 ) ) & 0xff ; unsigned HOST_WIDE_INT c1 = ( opint [ 1 ] >> ( i * 8 ) ) & 0xff ; if ( c0 >= c1 ) val |= 1 << i ; } return build_int_cst ( long_integer_type_node , val ) ; } else if ( op_const == 2 && opint [ 1 ] == 0 ) return build_int_cst ( long_integer_type_node , 0xff ) ; return NULL ; } </s>

Fold the builtin for the CMPBGE instruction . This is a vector comparison with an 8 bit output vector . OPINT contains the integer operands ; bit N of OP_CONST is set if OPINT [ N ] is valid .


<s> int X86TTIImpl :: getIntImmCost ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; unsigned ImmIdx = ~ 0U ; switch ( Opcode ) { default : return TTI :: TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: Store : ImmIdx = 0 ; break ; case Instruction :: ICmp : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 ) { uint64_t ImmVal = Imm . getZExtValue ( ) ; if ( ImmVal == 0x100000000ULL || ImmVal == 0xffffffff ) return TTI :: TCC_Free ; } ImmIdx = 1 ; break ; case Instruction :: And : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 && isUInt < 32 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; ImmIdx = 1 ; break ; case Instruction :: Add : case Instruction :: Sub : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 && Imm . getZExtValue ( ) == 0x80000000 ) return TTI :: TCC_Free ; ImmIdx = 1 ; break ; case Instruction :: Mul : case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : case Instruction :: Or : case Instruction :: Xor : ImmIdx = 1 ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == 1 ) return TTI :: TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: IntToPtr : case Instruction :: PtrToInt : case Instruction :: BitCast : case Instruction :: PHI : case Instruction :: Call : case Instruction :: Select : case Instruction :: Ret : case Instruction :: Load : break ; } if ( Idx == ImmIdx ) { int NumConstants = divideCeil ( BitSize , 64 ) ; int Cost = X86TTIImpl :: getIntImmCost ( Imm , Ty ) ; return ( Cost <= NumConstants * TTI :: TCC_Basic ) ? static_cast < int > ( TTI :: TCC_Free ) : Cost ; } return X86TTIImpl :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


"mproc DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s>
static
void
pru_option_override
(
void
)
{
SUBTARGET_OVERRIDE_OPTIONS
;
if
(
flag_pic
==
1
)
warning
(
OPT_fpic
,
"%<-fpic%> is not supported"
)
;
if
(
flag_pic
==
2
)
warning
(
OPT_fPIC
,
"%<-fPIC%> is not supported"
)
;
if
(
flag_pie
==
1
)
warning
(
OPT_fpie
,
"%<-fpie%> is not supported"
)
;
if
(
flag_pie
==
2
)
warning
(
OPT_fPIE
,
"%<-fPIE%> is not supported"
)
;
if
(
flag_reorder_blocks_and_partition
)
{
inform
(
input_location
,
"%<-freorder-blocks-and-partition%> "
"not supported on this architecture"
)
;
flag_reorder_blocks_and_partition
=
0
;
flag_reorder_blocks
=
1
;
}
init_machine_status
=
&
pru_init_machine_status
;
target_option_default_node
=
target_option_current_node
=
build_target_option_node
(
&
global_options
,
&
global_options_set
)
;
pru_register_abicheck_pass
(
)
;
}
</s>


<s> int Z80oldInstrInfo :: getSPAdjust ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { case Z80old :: POP16r : case Z80old :: POP16AF : return 2 ; case Z80old :: PUSH16r : case Z80old :: PUSH16AF : return - 2 ; } return TargetInstrInfo :: getSPAdjust ( MI ) ; } </s>

getSPAdjust - This returns the stack pointer adjustment made by this instruction .


<s> CCAssignFn * AMDGPUCallLowering :: CCAssignFnForCall ( CallingConv :: ID CC , bool IsVarArg ) const { return CC_AMDGPU ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> unsigned PPCInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case PPC :: STD : case PPC :: STW : case PPC :: STFS : case PPC :: STFD : if ( MI -> getOperand ( 1 ) . isImm ( ) && ! MI -> getOperand ( 1 ) . getImm ( ) && MI -> getOperand ( 2 ) . isFI ( ) ) { FrameIndex = MI -> getOperand ( 2 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> void Initialize ( const MachineFunction & MF , bool isPIC , bool isLittleEndian ) { IsPIC = isPIC ; IsLittleEndian = isLittleEndian ; } </s>

This method must be called before any actual lowering is done .


<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < 512 > Key ; Key . reserve ( CPU . size ( ) + FS . size ( ) ) ; Key += CPU ; Key += FS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) Key += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; FS = Key . substr ( CPU . size ( ) ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < X86Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; X86GISelActualAccessor * GISel = new X86GISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new X86CallLowering ( * I -> getTargetLowering ( ) ) ) ; GISel -> Legalizer . reset ( new X86LegalizerInfo ( * I , * this ) ) ; auto * RBI = new X86RegisterBankInfo ( * I -> getRegisterInfo ( ) ) ; GISel -> RegBankInfo . reset ( RBI ) ; GISel -> InstSelector . reset ( createX86InstructionSelector ( * this , * I , * RBI ) ) ; I -> setGISelAccessor ( * GISel ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
Register
getStackAddress
(
uint64_t
Size
,
int64_t
Offset
,
MachinePointerInfo
&
MPO
)
override
{
assert
(
(
Size
==
1
||
Size
==
2
||
Size
==
4
||
Size
==
8
)
&&
"Unsupported size"
)
;
LLT
p0
=
LLT
::
pointer
(
0
,
32
)
;
LLT
s32
=
LLT
::
scalar
(
32
)
;
Register
SPReg
=
MRI
.
createGenericVirtualRegister
(
p0
)
;
MIRBuilder
.
buildCopy
(
SPReg
,
Register
(
ARM
::
SP
)
)
;
Register
OffsetReg
=
MRI
.
createGenericVirtualRegister
(
s32
)
;
MIRBuilder
.
buildConstant
(
OffsetReg
,
Offset
)
;
Register
AddrReg
=
MRI
.
createGenericVirtualRegister
(
p0
)
;
MIRBuilder
.
buildPtrAdd
(
AddrReg
,
SPReg
,
OffsetReg
)
;
MPO
=
MachinePointerInfo
::
getStack
(
MIRBuilder
.
getMF
(
)
,
Offset
)
;
return
AddrReg
;
}
</s>

Materialize a VReg containing the address of the specified stack-based object .


<s> virtual bool hasRawTextSupport ( ) const { return true ; } </s>

Return true if this asm streamer supports emitting unformatted text to the .s file with EmitRawText .


<s> static bool classof ( const MCExpr * E ) { return E -> getKind ( ) == MCExpr :: Target ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> void msp430_register_pragmas ( void ) { c_register_addr_space ( "__near" , ADDR_SPACE_NEAR ) ; if ( msp430x ) c_register_addr_space ( "__far" , ADDR_SPACE_FAR ) ; } </s>


"execute-only should not generate constant pools"

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> bool HexagonRemoveExtendArgs :: runOnFunction ( Function & F ) { unsigned Idx = 1 ; for ( Function :: arg_iterator AI = F . arg_begin ( ) , AE = F . arg_end ( ) ; AI != AE ; ++ AI , ++ Idx ) { if ( F . paramHasAttr ( Idx , Attribute :: SExt ) ) { Argument * Arg = AI ; if ( ! isa < PointerType > ( Arg -> getType ( ) ) ) { for ( Instruction :: use_iterator UI = Arg -> use_begin ( ) ; UI != Arg -> use_end ( ) ; ) { if ( isa < SExtInst > ( * UI ) ) { Instruction * Use = cast < Instruction > ( * UI ) ; SExtInst * SI = new SExtInst ( Arg , Use -> getType ( ) ) ; assert ( EVT :: getEVT ( SI -> getType ( ) ) == ( EVT :: getEVT ( Use -> getType ( ) ) ) ) ; ++ UI ; Use -> replaceAllUsesWith ( SI ) ; Instruction * First = F . getEntryBlock ( ) . begin ( ) ; SI -> insertBefore ( First ) ; Use -> eraseFromParent ( ) ; } else { ++ UI ; } } } } } return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


"Unexpected data type for Gather/Scatter"

Calculate the cost of Gather / Scatter operation .


"TGSI DAG->DAG Pattern Instruction Selection"


<s> bool WebAssemblyInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool ) const { const auto & MFI = * MBB . getParent ( ) -> getInfo < WebAssemblyFunctionInfo > ( ) ; if ( MFI . isCFGStackified ( ) ) return true ; bool HaveCond = false ; for ( MachineInstr & MI : MBB . terminators ( ) ) { switch ( MI . getOpcode ( ) ) { default : return true ; case WebAssembly :: BR_IF : if ( HaveCond ) return true ; Cond . push_back ( MachineOperand :: CreateImm ( true ) ) ; Cond . push_back ( MI . getOperand ( 1 ) ) ; TBB = MI . getOperand ( 0 ) . getMBB ( ) ; HaveCond = true ; break ; case WebAssembly :: BR_UNLESS : if ( HaveCond ) return true ; Cond . push_back ( MachineOperand :: CreateImm ( false ) ) ; Cond . push_back ( MI . getOperand ( 1 ) ) ; TBB = MI . getOperand ( 0 ) . getMBB ( ) ; HaveCond = true ; break ; case WebAssembly :: BR : if ( ! HaveCond ) TBB = MI . getOperand ( 0 ) . getMBB ( ) ; else FBB = MI . getOperand ( 0 ) . getMBB ( ) ; break ; case WebAssembly :: BR_ON_EXN : if ( HaveCond ) return true ; Cond . push_back ( MachineOperand :: CreateImm ( true ) ) ; Cond . push_back ( MI . getOperand ( 2 ) ) ; TBB = MI . getOperand ( 0 ) . getMBB ( ) ; HaveCond = true ; break ; } if ( MI . isBarrier ( ) ) break ; } return false ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> static void aarch64_record_vector_load_arg ( tree addr ) { tree decl = aarch64_vector_load_decl ( addr ) ; if ( ! decl ) return ; if ( ! cfun -> machine -> vector_load_decls ) cfun -> machine -> vector_load_decls = hash_set < tree > :: create_ggc ( 31 ) ; cfun -> machine -> vector_load_decls -> add ( decl ) ; } </s>

We 've seen a vector load from address ADDR . Record it in vector_load_decls , if appropriate .


<s> bool SILowerControlFlowPass :: runOnMachineFunction ( MachineFunction & MF ) { bool HaveCf = false ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , Next = llvm :: next ( I ) ; I != MBB . end ( ) ; I = Next ) { Next = llvm :: next ( I ) ; MachineInstr & MI = * I ; switch ( MI . getOpcode ( ) ) { default : break ; case AMDGPU :: SI_IF : If ( MI ) ; break ; case AMDGPU :: SI_ELSE : Else ( MI ) ; break ; case AMDGPU :: SI_BREAK : Break ( MI ) ; break ; case AMDGPU :: SI_IF_BREAK : IfBreak ( MI ) ; break ; case AMDGPU :: SI_ELSE_BREAK : ElseBreak ( MI ) ; break ; case AMDGPU :: SI_LOOP : Loop ( MI ) ; break ; case AMDGPU :: SI_END_CF : HaveCf = true ; EndCf ( MI ) ; break ; case AMDGPU :: S_BRANCH : Branch ( MI ) ; break ; } } } unsigned ShaderType = MF . getInfo < SIMachineFunctionInfo > ( ) -> ShaderType ; if ( HaveCf && ShaderType == ShaderType :: PIXEL ) { for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ; if ( MBB . succ_empty ( ) ) { MachineInstr & MI = * MBB . getFirstNonPHI ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; BuildMI ( MBB , & MI , DL , TII -> get ( AMDGPU :: S_CBRANCH_EXECNZ ) ) . addImm ( 3 ) . addReg ( AMDGPU :: EXEC ) ; BuildMI ( MBB , & MI , DL , TII -> get ( AMDGPU :: EXP ) ) . addImm ( 0 ) . addImm ( 0x09 ) . addImm ( 0 ) . addImm ( 1 ) . addImm ( 1 ) . addReg ( AMDGPU :: SREG_LIT_0 ) . addReg ( AMDGPU :: SREG_LIT_0 ) . addReg ( AMDGPU :: SREG_LIT_0 ) . addReg ( AMDGPU :: SREG_LIT_0 ) ; BuildMI ( MBB , & MI , DL , TII -> get ( AMDGPU :: S_ENDPGM ) ) ; } } } return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> void LC3MCInstLower :: Initialize ( Mangler * M , MCContext * C ) { Mang = M ; Ctx = C ; } </s>


<s> static reg_class_t sparc_secondary_reload ( bool in_p , rtx x , reg_class_t rclass_i , machine_mode mode , secondary_reload_info * sri ) { enum reg_class rclass = ( enum reg_class ) rclass_i ; sri -> icode = CODE_FOR_nothing ; sri -> extra_cost = 0 ; if ( FP_REG_CLASS_P ( rclass ) && ( mode == HImode || mode == QImode ) && ( GET_CODE ( x ) == MEM || ( ( GET_CODE ( x ) == REG || GET_CODE ( x ) == SUBREG ) && true_regnum ( x ) == - 1 ) ) ) return GENERAL_REGS ; if ( TARGET_ARCH32 && rclass == EXTRA_FP_REGS && mode == DFmode && GET_CODE ( x ) == MEM && ! mem_min_alignment ( x , 8 ) ) return FP_REGS ; if ( ( ( TARGET_CM_MEDANY && symbolic_operand ( x , mode ) ) || ( TARGET_CM_EMBMEDANY && text_segment_operand ( x , mode ) ) ) && ! flag_pic ) { if ( in_p ) sri -> icode = direct_optab_handler ( reload_in_optab , mode ) ; else sri -> icode = direct_optab_handler ( reload_out_optab , mode ) ; return NO_REGS ; } if ( TARGET_VIS3 && TARGET_ARCH32 ) { int regno = true_regnum ( x ) ; if ( ( rclass == EXTRA_FP_REGS && SPARC_INT_REG_P ( regno ) ) || ( ( general_or_i64_p ( rclass ) || rclass == GENERAL_OR_FP_REGS ) && SPARC_FP_REG_P ( regno ) ) ) { sri -> extra_cost = 2 ; return FP_REGS ; } } return NO_REGS ; } </s>


<s> void print ( DiagnosticPrinter & DP ) const override { DP << Msg ; } </s>

print - Print a debug representation of the operand to the given stream .


<s> bool X86TargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { if ( ! CI -> isTailCall ( ) ) return false ; CallSite CS ( CI ) ; CallingConv :: ID CalleeCC = CS . getCallingConv ( ) ; if ( ! IsTailCallConvention ( CalleeCC ) && CalleeCC != CallingConv :: C ) return false ; return true ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> bool WebAssemblyDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { switch ( ConstraintID ) { case InlineAsm :: Constraint_m : OutOps . push_back ( Op ) ; return false ; default : break ; } return true ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> std :: unique_ptr < ARMInputExMap > ARMInputExMap :: create ( Input & pInput ) { std :: unique_ptr < ARMInputExMap > exMap ( new ARMInputExMap ( ) ) ; LDContext * ctx = pInput . context ( ) ; for ( LDContext :: sect_iterator it = ctx -> sectBegin ( ) , end = ctx -> sectEnd ( ) ; it != end ; ++ it ) { LDSection * sect = * it ; if ( sect -> type ( ) == llvm :: ELF :: SHT_ARM_EXIDX ) { ARMExSectionTuple * exTuple = exMap -> getOrCreateByExSection ( * sect ) ; exTuple -> setExIdxSection ( sect ) ; exTuple -> setTextSection ( sect -> getLink ( ) ) ; if ( sect -> getLink ( ) == NULL ) { fatal ( diag :: eh_missing_text_section ) << sect -> name ( ) << pInput . name ( ) ; } } } ARMInputExMap :: iterator it = exMap -> begin ( ) ; ARMInputExMap :: iterator end = exMap -> end ( ) ; while ( it != end ) { ARMExSectionTuple * exTuple = it -> second . get ( ) ; LDSection * const text = exTuple -> getTextSection ( ) ; LDSection * const exIdx = exTuple -> getExIdxSection ( ) ; if ( ( text -> kind ( ) == LDFileFormat :: Ignore ) || ( text -> kind ( ) == LDFileFormat :: Folded ) ) { exIdx -> setKind ( LDFileFormat :: Ignore ) ; ARMInputExMap :: iterator deadIt = it ++ ; exMap -> erase ( deadIt ) ; continue ; } RegionFragment * textFrag = findRegionFragment ( * text ) ; RegionFragment * exIdxFrag = findRegionFragment ( * exIdx ) ; exTuple -> setTextFragment ( textFrag ) ; exTuple -> setExIdxFragment ( exIdxFrag ) ; if ( exIdxFrag == NULL ) { ARMInputExMap :: iterator deadIt = it ++ ; exMap -> erase ( deadIt ) ; continue ; } ++ it ; } return exMap ; } </s>

ARM ARM ARMInputExMap::create ARM ARM ARM ARM ARMInputExMap::iterator ARMInputExMap::iterator ARM ARMInputExMap::iterator ARMInputExMap::iterator


<s>
unsigned
PPCVSXSwapRemoval
::
lookThruCopyLike
(
unsigned
SrcReg
,
unsigned
VecIdx
)
{
MachineInstr
*
MI
=
MRI
->
getVRegDef
(
SrcReg
)
;
if
(
!
MI
->
isCopyLike
(
)
)
return
SrcReg
;
unsigned
CopySrcReg
,
CopySrcSubreg
;
if
(
MI
->
isCopy
(
)
)
{
CopySrcReg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
CopySrcSubreg
=
MI
->
getOperand
(
1
)
.
getSubReg
(
)
;
}
else
{
assert
(
MI
->
isSubregToReg
(
)
&&
"bad opcode for lookThruCopyLike"
)
;
CopySrcReg
=
MI
->
getOperand
(
2
)
.
getReg
(
)
;
CopySrcSubreg
=
MI
->
getOperand
(
2
)
.
getSubReg
(
)
;
}
if
(
!
TargetRegisterInfo
::
isVirtualRegister
(
CopySrcReg
)
)
{
SwapVector
[
VecIdx
]
.
MentionsPhysVR
=
1
;
return
CopySrcReg
;
}
if
(
CopySrcSubreg
!=
0
)
{
SwapVector
[
VecIdx
]
.
HasImplicitSubreg
=
1
;
return
CopySrcReg
;
}
return
lookThruCopyLike
(
CopySrcReg
,
VecIdx
)
;
}
</s>

Returns the original SrcReg unless it is the target of a copy-like operation , in which case we chain backwards through all such operations to the ultimate source register .


<s> static std :: unique_ptr < MSP430Operand > CreateReg ( unsigned RegNum , SMLoc S , SMLoc E ) { return make_unique < MSP430Operand > ( k_Reg , RegNum , S , E ) ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> int next_insn_test_reg ( rtx insn , rtx reg ) { rtx body ; insn = next_nonnote_insn ( insn ) ; if ( GET_CODE ( insn ) != INSN ) return 0 ; body = PATTERN ( insn ) ; if ( sets_cc0_p ( body ) != 1 ) return 0 ; if ( rtx_equal_p ( XEXP ( body , 1 ) , reg ) == 0 ) return 0 ; return 1 ; } </s>

Returns 1 if the next insn after 'insn ' is a test of the register 'reg ' . This is used to decide whether a move that set flags should be used instead .


<s> static void frv_register_nop ( rtx nop ) { nop = make_insn_raw ( nop ) ; NEXT_INSN ( nop ) = 0 ; PREV_INSN ( nop ) = 0 ; frv_nops [ frv_num_nops ++ ] = nop ; } </s>

Add an instruction with pattern NOP to frv_nops [ ] .


<s>
void
M68kOperand
::
print
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
KindTy
::
Invalid
:
OS
<<
"invalid"
;
break
;
case
KindTy
::
Token
:
OS
<<
"token '"
<<
Token
<<
"'"
;
break
;
case
KindTy
::
Imm
:
OS
<<
"immediate "
<<
Imm
;
break
;
case
KindTy
::
MemOp
:
MemOp
.
print
(
OS
)
;
break
;
}
}
</s>

M68k
M68k
"invalid"
"token '"
"'"
"immediate "


<s> static void mmix_trampoline_init ( rtx m_tramp , tree fndecl , rtx static_chain ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx mem ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( 2 * UNITS_PER_WORD ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp , DImode , 2 * UNITS_PER_WORD ) ; emit_move_insn ( mem , static_chain ) ; mem = adjust_address ( m_tramp , DImode , 3 * UNITS_PER_WORD ) ; emit_move_insn ( mem , fnaddr ) ; mem = adjust_address ( m_tramp , DImode , 0 ) ; emit_insn ( gen_sync_icache ( mem , GEN_INT ( TRAMPOLINE_SIZE - 1 ) ) ) ; } </s>

Set the static chain and function pointer field in the trampoline . We also SYNCID here to be sure ( does n't matter in the simulator , but some day it will ) .


";; %smode fixup for i%d; addr %lu, range (%ld,%ld): "

Record INSN , which will need fixing up to load a value from the minipool . ADDRESS is the offset of the insn since the start of the function ; LOC is a pointer to the part of the insn which requires fixing ; VALUE is the constant that must be loaded , which is of type MODE .


<s> void csky_set_eh_return_address ( rtx source , rtx scratch ) { HOST_WIDE_INT delta = 0 ; rtx basereg , addr ; unsigned int reg_mask ; csky_layout_stack_frame ( ) ; reg_mask = cfun -> machine -> reg_mask ; if ( reg_mask & ( 1 << CSKY_LR_REGNUM ) ) { int i = 0 ; if ( frame_pointer_needed ) { basereg = hard_frame_pointer_rtx ; delta = 0 ; } else { basereg = stack_pointer_rtx ; delta = cfun -> machine -> reg_offset ; } for ( i = 0 ; i < CSKY_LR_REGNUM ; i ++ ) if ( reg_mask & ( 1 << i ) ) delta += 4 ; if ( ( CSKY_TARGET_ARCH ( CK801 ) && delta >= CSKY_LD16_MAX_OFFSET ( Pmode ) ) || delta >= CSKY_LD32_MAX_OFFSET ( Pmode ) ) { emit_insn ( gen_movsi ( scratch , GEN_INT ( delta ) ) ) ; emit_insn ( gen_addsi3 ( scratch , scratch , basereg ) ) ; addr = scratch ; } else addr = plus_constant ( Pmode , basereg , delta ) ; emit_move_insn ( gen_frame_mem ( Pmode , addr ) , source ) ; } else emit_move_insn ( gen_rtx_REG ( Pmode , CSKY_LR_REGNUM ) , source ) ; } </s>

Helper for csky_eh_return splitter : store the call frame exception handler address in lr .


<s> virtual const PPCInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


Return the function that is used to expand the < u > mulsidi3 pattern . EXT_CODE is the code of the extension used . Return NULL if widening multiplication should n't be used .


<s> static void frv_frame_access ( frv_frame_accessor_t * accessor , rtx reg , int stack_offset ) { enum machine_mode mode = GET_MODE ( reg ) ; rtx mem = frv_frame_mem ( mode , accessor -> base , stack_offset - accessor -> base_offset ) ; if ( accessor -> op == FRV_LOAD ) { if ( SPR_P ( REGNO ( reg ) ) ) { rtx temp = gen_rtx_REG ( mode , TEMP_REGNO ) ; emit_insn ( gen_rtx_SET ( VOIDmode , temp , mem ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , reg , temp ) ) ; } else emit_insn ( gen_rtx_SET ( VOIDmode , reg , mem ) ) ; emit_insn ( gen_rtx_USE ( VOIDmode , reg ) ) ; } else { if ( SPR_P ( REGNO ( reg ) ) ) { rtx temp = gen_rtx_REG ( mode , TEMP_REGNO ) ; emit_insn ( gen_rtx_SET ( VOIDmode , temp , reg ) ) ; frv_frame_insn ( gen_rtx_SET ( Pmode , mem , temp ) , frv_dwarf_store ( reg , stack_offset ) ) ; } else if ( GET_MODE ( reg ) == DImode ) { rtx reg1 = gen_rtx_REG ( SImode , REGNO ( reg ) ) ; rtx reg2 = gen_rtx_REG ( SImode , REGNO ( reg ) + 1 ) ; rtx set1 = frv_dwarf_store ( reg1 , stack_offset ) ; rtx set2 = frv_dwarf_store ( reg2 , stack_offset + 4 ) ; frv_frame_insn ( gen_rtx_SET ( Pmode , mem , reg ) , gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set1 , set2 ) ) ) ; } else frv_frame_insn ( gen_rtx_SET ( Pmode , mem , reg ) , frv_dwarf_store ( reg , stack_offset ) ) ; } } </s>

Emit instructions that transfer REG to or from the memory location ( sp + STACK_OFFSET ) . The register is stored in memory if ACCESSOR- > OP is FRV_STORE and loaded if it is FRV_LOAD . Only the prologue uses this function to store registers and only the epilogue uses it to load them . The caller sets up ACCESSOR so that BASE is equal to ( sp + BASE_OFFSET ) . The generated instruction will use BASE as its base register . BASE may simply be the stack pointer , but if several accesses are being made to a region far away from the stack pointer , it may be more efficient to set up a temporary instead . Store instructions will be frame-related and will be annotated with the overall effect of the store . Load instructions will be followed by a ( use ) to prevent later optimizations from zapping them . The function takes care of the moves to and from SPRs , using TEMP_REGNO as a temporary in such cases .


<s> DecodeStatus DLXDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & , raw_ostream & ) const { uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Bytes , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTableDLX32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { PostOperandDecodeAdjust ( Instr , Insn ) ; Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s> bool AArch64TargetLowering :: isFMAFasterThanFMulAndFAdd ( EVT VT ) const { VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f32 : case MVT :: f64 : return true ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> static bool tilegx_tls_referenced_p ( rtx x ) { if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS ) x = XEXP ( XEXP ( x , 0 ) , 0 ) ; if ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) ) return true ; return false ; } </s>

Return true if X contains a thread-local symbol .


<s> bool X86TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , Align Alignment , MachineMemOperand :: Flags Flags , bool * Fast ) const { if ( Fast ) { switch ( VT . getSizeInBits ( ) ) { default : * Fast = true ; break ; case 128 : * Fast = ! Subtarget . isUnalignedMem16Slow ( ) ; break ; case 256 : * Fast = ! Subtarget . isUnalignedMem32Slow ( ) ; break ; } } if ( ! ! ( Flags & MachineMemOperand :: MONonTemporal ) && VT . isVector ( ) ) { if ( ! ! ( Flags & MachineMemOperand :: MOLoad ) ) return ( Alignment < 16 || ! Subtarget . hasSSE41 ( ) ) ; return false ; } return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> rtx function_expander :: get_reg_target ( ) { machine_mode target_mode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( fndecl ) ) ) ; if ( ! possible_target || GET_MODE ( possible_target ) != target_mode ) possible_target = gen_reg_rtx ( target_mode ) ; return possible_target ; } </s>

Return a REG rtx that can be used for the result of the function , using the preferred target if suitable .


<s> int X86FrameLowering :: mergeSPUpdates ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , bool doMergeWithPrevious ) const { if ( ( doMergeWithPrevious && MBBI == MBB . begin ( ) ) || ( ! doMergeWithPrevious && MBBI == MBB . end ( ) ) ) return 0 ; MachineBasicBlock :: iterator PI = doMergeWithPrevious ? std :: prev ( MBBI ) : MBBI ; MachineBasicBlock :: iterator NI = doMergeWithPrevious ? nullptr : std :: next ( MBBI ) ; PI = skipDebugInstructionsBackward ( PI , MBB . begin ( ) ) ; if ( NI != nullptr ) NI = skipDebugInstructionsForward ( NI , MBB . end ( ) ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = 0 ; if ( ! doMergeWithPrevious && NI != MBB . end ( ) && NI -> getOpcode ( ) == TargetOpcode :: CFI_INSTRUCTION ) { return Offset ; } if ( ( Opc == X86 :: ADD64ri32 || Opc == X86 :: ADD64ri8 || Opc == X86 :: ADD32ri || Opc == X86 :: ADD32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { assert ( PI -> getOperand ( 1 ) . getReg ( ) == StackPtr ) ; Offset += PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == X86 :: LEA32r || Opc == X86 :: LEA64_32r ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr && PI -> getOperand ( 1 ) . getReg ( ) == StackPtr && PI -> getOperand ( 2 ) . getImm ( ) == 1 && PI -> getOperand ( 3 ) . getReg ( ) == X86 :: NoRegister && PI -> getOperand ( 5 ) . getReg ( ) == X86 :: NoRegister ) { Offset += PI -> getOperand ( 4 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == X86 :: SUB64ri32 || Opc == X86 :: SUB64ri8 || Opc == X86 :: SUB32ri || Opc == X86 :: SUB32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { assert ( PI -> getOperand ( 1 ) . getReg ( ) == StackPtr ) ; Offset -= PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } return Offset ; } </s>

Check the instruction before/after the passed instruction .


<s> void BPFPassConfig :: addPreEmitPass ( ) { const BPFSubtarget * Subtarget = getBPFTargetMachine ( ) . getSubtargetImpl ( ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) if ( Subtarget -> getHasAlu32 ( ) && ! DisableMIPeephole ) addPass ( createBPFMIPreEmitPeepholePass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool AArch64TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Align , bool * Fast ) const { if ( Subtarget -> requiresStrictAlign ( ) ) return false ; if ( Fast ) * Fast = true ; return true ; } </s>


<s> static rtx mmix_function_arg_1 ( const cumulative_args_t argsp_v , const function_arg_info & arg , bool incoming ) { CUMULATIVE_ARGS * argsp = get_cumulative_args ( argsp_v ) ; machine_mode mode = arg . mode == VOIDmode ? DImode : arg . mode ; if ( arg . end_marker_p ( ) ) return ( argsp -> regs < MMIX_MAX_ARGS_IN_REGS ) ? gen_rtx_REG ( mode , ( incoming ? MMIX_FIRST_INCOMING_ARG_REGNUM : MMIX_FIRST_ARG_REGNUM ) + argsp -> regs ) : NULL_RTX ; return ( argsp -> regs < MMIX_MAX_ARGS_IN_REGS && ! targetm . calls . must_pass_in_stack ( arg ) && ( GET_MODE_BITSIZE ( mode ) <= 64 || argsp -> lib || TARGET_LIBFUNC ) ) ? gen_rtx_REG ( mode , ( incoming ? MMIX_FIRST_INCOMING_ARG_REGNUM : MMIX_FIRST_ARG_REGNUM ) + argsp -> regs ) : NULL_RTX ; } </s>

Helper function for mmix_function_arg and mmix_function_incoming_arg .


"insertBranch must not be told to insert a fallthrough"

"ARM branch conditions have two or three components!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LiveVariables > ( ) ; AU . addPreserved < LiveVariables > ( ) ; AU . addRequired < MachinePostDominatorTree > ( ) ; AU . addPreserved < MachinePostDominatorTree > ( ) ; AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static inline bool inline_secondary_memory_needed ( machine_mode mode , reg_class_t class1 , reg_class_t class2 , int strict ) { if ( lra_in_progress && ( class1 == NO_REGS || class2 == NO_REGS ) ) return false ; if ( MAYBE_FLOAT_CLASS_P ( class1 ) != FLOAT_CLASS_P ( class1 ) || MAYBE_FLOAT_CLASS_P ( class2 ) != FLOAT_CLASS_P ( class2 ) || MAYBE_SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class1 ) || MAYBE_SSE_CLASS_P ( class2 ) != SSE_CLASS_P ( class2 ) || MAYBE_MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class1 ) || MAYBE_MMX_CLASS_P ( class2 ) != MMX_CLASS_P ( class2 ) || MAYBE_MASK_CLASS_P ( class1 ) != MASK_CLASS_P ( class1 ) || MAYBE_MASK_CLASS_P ( class2 ) != MASK_CLASS_P ( class2 ) ) { gcc_assert ( ! strict || lra_in_progress ) ; return true ; } if ( FLOAT_CLASS_P ( class1 ) != FLOAT_CLASS_P ( class2 ) ) return true ; if ( MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class2 ) ) return true ; if ( MASK_CLASS_P ( class1 ) != MASK_CLASS_P ( class2 ) ) { if ( ! ( INTEGER_CLASS_P ( class1 ) || INTEGER_CLASS_P ( class2 ) ) || GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) return true ; } if ( SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class2 ) ) { if ( ! TARGET_SSE2 ) return true ; if ( ! ( INTEGER_CLASS_P ( class1 ) || INTEGER_CLASS_P ( class2 ) ) ) return true ; int msize = GET_MODE_SIZE ( mode ) ; if ( msize > UNITS_PER_WORD ) return true ; int minsize = GET_MODE_SIZE ( TARGET_SSE2 ? HImode : SImode ) ; if ( msize < minsize ) return true ; if ( ( SSE_CLASS_P ( class1 ) && ! TARGET_INTER_UNIT_MOVES_FROM_VEC ) || ( SSE_CLASS_P ( class2 ) && ! TARGET_INTER_UNIT_MOVES_TO_VEC ) ) return true ; } return false ; } </s>

If we are copying between general and FP registers , we need a memory location . The same is true for SSE and MMX registers . To optimize register_move_cost performance , allow inline variant . The macro ca n't work reliably when one of the CLASSES is class containing registers from multiple units ( SSE , MMX , integer ) . We avoid this by never combining those units in single alternative in the machine description . Ensure that this constraint holds to avoid unexpected surprises . When STRICT is false , we are being called from REGISTER_MOVE_COST , so do not enforce these sanity checks .


<s> bool visitInstruction ( Instruction & I ) { return false ; } </s>

Specify what to return for unhandled instructions .


<s> void SITargetLowering :: AdjustInstrPostInstrSelection ( MachineInstr & MI , SDNode * Node ) const { const SIInstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; if ( TII -> isVOP3 ( MI . getOpcode ( ) ) ) { TII -> legalizeOperandsVOP3 ( MRI , MI ) ; if ( MI . getDesc ( ) . OpInfo ) { unsigned Opc = MI . getOpcode ( ) ; const SIRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; for ( auto I : { AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src0 ) , AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src1 ) } ) { if ( I == - 1 ) break ; MachineOperand & Op = MI . getOperand ( I ) ; if ( ! Op . isReg ( ) || ! Op . getReg ( ) . isVirtual ( ) ) continue ; auto * RC = TRI -> getRegClassForReg ( MRI , Op . getReg ( ) ) ; if ( ! TRI -> hasAGPRs ( RC ) ) continue ; auto * Src = MRI . getUniqueVRegDef ( Op . getReg ( ) ) ; if ( ! Src || ! Src -> isCopy ( ) || ! TRI -> isSGPRReg ( MRI , Src -> getOperand ( 1 ) . getReg ( ) ) ) continue ; auto * NewRC = TRI -> getEquivalentVGPRClass ( RC ) ; MRI . setRegClass ( Op . getReg ( ) , NewRC ) ; } if ( auto * Src2 = TII -> getNamedOperand ( MI , AMDGPU :: OpName :: src2 ) ) { if ( Src2 -> isReg ( ) && Src2 -> getReg ( ) . isVirtual ( ) ) { auto * RC = TRI -> getRegClassForReg ( MRI , Src2 -> getReg ( ) ) ; if ( TRI -> isVectorSuperClass ( RC ) ) { auto * NewRC = TRI -> getEquivalentAGPRClass ( RC ) ; MRI . setRegClass ( Src2 -> getReg ( ) , NewRC ) ; if ( Src2 -> isTied ( ) ) MRI . setRegClass ( MI . getOperand ( 0 ) . getReg ( ) , NewRC ) ; } } } } return ; } if ( TII -> isMIMG ( MI ) ) { if ( ! MI . mayStore ( ) ) AddIMGInit ( MI ) ; TII -> enforceOperandRCAlignment ( MI , AMDGPU :: OpName :: vaddr ) ; } } </s>

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .

AMDGPU SI SI SI AMDGPU::getNamedOperandIdx AMDGPU::OpName AMDGPU::getNamedOperandIdx AMDGPU::OpName 1 1 AMDGPU::OpName 0 AMDGPU::OpName


<s> void rs6000_expand_extract_even ( rtx target , rtx op0 , rtx op1 ) { machine_mode vmode = GET_MODE ( target ) ; unsigned i , nelt = GET_MODE_NUNITS ( vmode ) ; rtx perm [ 16 ] ; for ( i = 0 ; i < nelt ; i ++ ) perm [ i ] = GEN_INT ( i * 2 ) ; rs6000_do_expand_vec_perm ( target , op0 , op1 , vmode , nelt , perm ) ; } </s>


<s> MachineSDNode * SITargetLowering :: buildRSRC ( SelectionDAG & DAG , SDLoc DL , SDValue Ptr , uint32_t RsrcDword1 , uint64_t RsrcDword2And3 ) const { SDValue PtrLo = DAG . getTargetExtractSubreg ( AMDGPU :: sub0 , DL , MVT :: i32 , Ptr ) ; SDValue PtrHi = DAG . getTargetExtractSubreg ( AMDGPU :: sub1 , DL , MVT :: i32 , Ptr ) ; if ( RsrcDword1 ) { PtrHi = SDValue ( DAG . getMachineNode ( AMDGPU :: S_OR_B32 , DL , MVT :: i32 , PtrHi , DAG . getConstant ( RsrcDword1 , DL , MVT :: i32 ) ) , 0 ) ; } SDValue DataLo = buildSMovImm32 ( DAG , DL , RsrcDword2And3 & UINT64_C ( 0xFFFFFFFF ) ) ; SDValue DataHi = buildSMovImm32 ( DAG , DL , RsrcDword2And3 >> 32 ) ; const SDValue Ops [ ] = { DAG . getTargetConstant ( AMDGPU :: SReg_128RegClassID , DL , MVT :: i32 ) , PtrLo , DAG . getTargetConstant ( AMDGPU :: sub0 , DL , MVT :: i32 ) , PtrHi , DAG . getTargetConstant ( AMDGPU :: sub1 , DL , MVT :: i32 ) , DataLo , DAG . getTargetConstant ( AMDGPU :: sub2 , DL , MVT :: i32 ) , DataHi , DAG . getTargetConstant ( AMDGPU :: sub3 , DL , MVT :: i32 ) } ; return DAG . getMachineNode ( AMDGPU :: REG_SEQUENCE , DL , MVT :: v4i32 , Ops ) ; } </s>

Return a resource descriptor with the 'Add TID ' bit enabled The TID ( Thread ID ) is multiplied by the stride value ( bits [ 61:48 ] of the resource descriptor ) to create an offset , which is added to the resource pointer .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"VideoCore4 Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> TargetLowering :: AtomicExpansionKind SITargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * RMW ) const { switch ( RMW -> getOperation ( ) ) { case AtomicRMWInst :: FAdd : { Type * Ty = RMW -> getType ( ) ; if ( Ty -> isHalfTy ( ) ) return AtomicExpansionKind :: None ; if ( ! Ty -> isFloatTy ( ) ) return AtomicExpansionKind :: CmpXChg ; unsigned AS = RMW -> getPointerAddressSpace ( ) ; return ( AS == AMDGPUAS :: LOCAL_ADDRESS && Subtarget -> hasLDSFPAtomics ( ) ) ? AtomicExpansionKind :: None : AtomicExpansionKind :: CmpXChg ; } default : break ; } return AMDGPUTargetLowering :: shouldExpandAtomicRMWInIR ( RMW ) ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> void ARMELFStreamer :: Reset ( ) { ExTab = NULL ; FnStart = NULL ; Personality = NULL ; CantUnwind = false ; } </s>


<s> void thumb2_expand_return ( bool simple_return ) { int i , num_regs ; unsigned long saved_regs_mask ; arm_stack_offsets * offsets ; offsets = arm_get_frame_offsets ( ) ; saved_regs_mask = offsets -> saved_regs_mask ; for ( i = 0 , num_regs = 0 ; i <= LAST_ARM_REGNUM ; i ++ ) if ( saved_regs_mask & ( 1 << i ) ) num_regs ++ ; if ( ! simple_return && saved_regs_mask ) { if ( num_regs == 1 ) { rtx par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( 2 ) ) ; rtx reg = gen_rtx_REG ( SImode , PC_REGNUM ) ; rtx addr = gen_rtx_MEM ( SImode , gen_rtx_POST_INC ( SImode , stack_pointer_rtx ) ) ; set_mem_alias_set ( addr , get_frame_alias_set ( ) ) ; XVECEXP ( par , 0 , 0 ) = ret_rtx ; XVECEXP ( par , 0 , 1 ) = gen_rtx_SET ( SImode , reg , addr ) ; RTX_FRAME_RELATED_P ( XVECEXP ( par , 0 , 1 ) ) = 1 ; emit_jump_insn ( par ) ; } else { saved_regs_mask &= ~ ( 1 << LR_REGNUM ) ; saved_regs_mask |= ( 1 << PC_REGNUM ) ; arm_emit_multi_reg_pop ( saved_regs_mask ) ; } } else { emit_jump_insn ( simple_return_rtx ) ; } } </s>


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> void mips_expand_scc ( rtx operands [ ] ) { rtx target = operands [ 0 ] ; enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; rtx op0 = operands [ 2 ] ; rtx op1 = operands [ 3 ] ; gcc_assert ( GET_MODE_CLASS ( GET_MODE ( op0 ) ) == MODE_INT ) ; if ( code == EQ || code == NE ) { if ( ISA_HAS_SEQ_SNE && reg_imm10_operand ( op1 , GET_MODE ( op1 ) ) ) mips_emit_binary ( code , target , op0 , op1 ) ; else { rtx zie = mips_zero_if_equal ( op0 , op1 ) ; mips_emit_binary ( code , target , zie , const0_rtx ) ; } } else mips_emit_int_order_test ( code , 0 , target , op0 , op1 ) ; } </s>

Try performing the comparison in OPERANDS [ 1 ] , whose arms are OPERANDS [ 2 ] and OPERAND [ 3 ] . Store the result in OPERANDS [ 0 ] . On 64-bit targets , the mode of the comparison and target will always be SImode , thus possibly narrower than that of the comparison 's operands .


<s>
Value
*
HexagonTargetLowering
::
emitLoadLinked
(
IRBuilder
<
>
&
Builder
,
Value
*
Addr
,
AtomicOrdering
Ord
)
const
{
BasicBlock
*
BB
=
Builder
.
GetInsertBlock
(
)
;
Module
*
M
=
BB
->
getParent
(
)
->
getParent
(
)
;
auto
PT
=
cast
<
PointerType
>
(
Addr
->
getType
(
)
)
;
Type
*
Ty
=
PT
->
getElementType
(
)
;
unsigned
SZ
=
Ty
->
getPrimitiveSizeInBits
(
)
;
assert
(
(
SZ
==
32
||
SZ
==
64
)
&&
"Only 32/64-bit atomic loads supported"
)
;
Intrinsic
::
ID
IntID
=
(
SZ
==
32
)
Intrinsic
::
hexagon_L2_loadw_locked
:
Intrinsic
::
hexagon_L4_loadd_locked
;
Function
*
Fn
=
Intrinsic
::
getDeclaration
(
M
,
IntID
)
;
PointerType
*
NewPtrTy
=
Builder
.
getIntNTy
(
SZ
)
->
getPointerTo
(
PT
->
getAddressSpace
(
)
)
;
Addr
=
Builder
.
CreateBitCast
(
Addr
,
NewPtrTy
)
;
Value
*
Call
=
Builder
.
CreateCall
(
Fn
,
Addr
,
"larx"
)
;
return
Builder
.
CreateBitCast
(
Call
,
Ty
)
;
}
</s>

Perform a load-linked operation on Addr , returning a `` Value * '' with the corresponding pointee type .


<s> void SparcPassConfig :: addPreEmitPass ( ) { addPass ( createSparcDelaySlotFillerPass ( getSparcTargetMachine ( ) ) ) ; if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> insertNOPLoad ( ) ) { addPass ( new InsertNOPLoad ( getSparcTargetMachine ( ) ) ) ; } } </s>


<s> bool AMDGPUPassConfig :: addPreISel ( ) { const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . device ( ) -> getGeneration ( ) > AMDGPUDeviceInfo :: HD6XXX ) { addPass ( createAMDGPUStructurizeCFGPass ( ) ) ; addPass ( createSIAnnotateControlFlowPass ( ) ) ; } return false ; } </s>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; const PPCSubtarget & STI = MF . getSubtarget < PPCSubtarget > ( ) ; if ( ! STI . hasVSX ( ) ) return false ; bool Changed = false ; initialize ( MF ) ; if ( gatherVectorInstructions ( ) ) { formWebs ( ) ; recordUnoptimizableWebs ( ) ; markSwapsForRemoval ( ) ; Changed = removeSwaps ( ) ; } delete EC ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> static void frv_align_label ( void ) { unsigned int alignment , target , nop ; rtx_insn * x , * last , * barrier , * label ; last = frv_packet . insns [ frv_packet . num_insns - 1 ] ; label = barrier = 0 ; alignment = 4 ; for ( x = NEXT_INSN ( last ) ; x != 0 && ! INSN_P ( x ) ; x = NEXT_INSN ( x ) ) { if ( LABEL_P ( x ) ) { unsigned int subalign = 1 << label_to_alignment ( x ) ; alignment = MAX ( alignment , subalign ) ; label = x ; } if ( BARRIER_P ( x ) ) barrier = x ; } if ( TARGET_ALIGN_LABELS && label != 0 && barrier == 0 && frv_packet . num_insns < frv_packet . issue_rate ) alignment = MAX ( alignment , 8 ) ; frv_packet_address += frv_packet . num_insns * 4 ; target = ( frv_packet_address + alignment - 1 ) & - alignment ; if ( barrier == 0 ) { for ( nop = 0 ; nop < frv_num_nops ; nop ++ ) while ( frv_packet_address < target && frv_pack_insn_p ( frv_nops [ nop ] ) ) { frv_insert_nop_in_packet ( frv_nops [ nop ] ) ; frv_packet_address += 4 ; } last = frv_packet . insns [ frv_packet . num_insns - 1 ] ; nop = 0 ; while ( frv_packet_address < target ) { last = emit_insn_after ( PATTERN ( frv_nops [ nop ] ) , last ) ; frv_packet_address += 4 ; if ( frv_num_nops > 1 ) nop ^= 1 ; } } frv_packet_address = target ; } </s>

If the current packet falls through to a label , try to pad the packet with nops in order to fit the label 's alignment requirements .


<s> static tree rs6000_d_handle_target_object_format ( void ) { const char * objfmt = NULL ; if ( TARGET_ELF ) objfmt = "elf" ; else if ( TARGET_MACHO ) objfmt = "macho" ; else if ( TARGET_XCOFF ) objfmt = "coff" ; if ( objfmt == NULL ) return NULL_TREE ; return build_string_literal ( strlen ( objfmt ) + 1 , objfmt ) ; } </s>

Handle a call to ` __traits ( getTargetInfo , `` objectFormat '' ) ' .


<s> static void ix86_add_queued_cfa_restore_notes ( rtx insn ) { rtx last ; if ( ! queued_cfa_restores ) return ; for ( last = queued_cfa_restores ; XEXP ( last , 1 ) ; last = XEXP ( last , 1 ) ) ; XEXP ( last , 1 ) = REG_NOTES ( insn ) ; REG_NOTES ( insn ) = queued_cfa_restores ; queued_cfa_restores = NULL_RTX ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Add queued REG_CFA_RESTORE notes if any to INSN .


<s> static rtx move_to_de ( int opno , rtx before ) { rtx src = OP ( opno ) ; machine_mode mode = GET_MODE ( src ) ; rtx reg ; if ( mode == VOIDmode ) mode = recog_data . operand_mode [ opno ] ; reg = ( mode == QImode ) ? E : DE ; if ( mode == QImode || ! is_virtual_register ( OP ( opno ) ) ) { OP ( opno ) = move_to_acc ( opno , before ) ; OP ( opno ) = move_acc_to_reg ( OP ( opno ) , E_REG , before ) ; } else { gen_and_emit_move ( reg , src , before , true ) ; } return reg ; } </s>

Copy OP ( opno ) to E or DE , placing any generated insns before BEFORE . Returns E/DE RTX .


<s> const PPCSubtarget * getSubtargetImpl ( ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static rtx move_from_acc ( unsigned int opno , rtx after ) { rtx dest = OP ( opno ) ; machine_mode mode = GET_MODE ( dest ) ; if ( REG_P ( dest ) && REGNO ( dest ) < 2 ) return dest ; return gen_and_emit_move ( dest , mode == QImode ? A : AX , after , false ) ; } </s>

Copy accumulator ( A or AX ) to DEST , placing any generated insns after AFTER . Returns accumulator RTX .


"Scavenger spill for register not yet implemented."

Spill the register so it can be used by the register scavenger .


<s> int tls_symbolic_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { if ( GET_CODE ( op ) != SYMBOL_REF ) return 0 ; return SYMBOL_REF_TLS_MODEL ( op ) ; } </s>

Return the TLS type for TLS symbols , 0 for otherwise .


<s> static void rs6000_expand_vector_set_var_p9 ( rtx target , rtx val , rtx idx ) { machine_mode mode = GET_MODE ( target ) ; gcc_assert ( VECTOR_MEM_VSX_P ( mode ) && ! CONST_INT_P ( idx ) ) ; machine_mode inner_mode = GET_MODE ( val ) ; int width = GET_MODE_SIZE ( inner_mode ) ; gcc_assert ( width >= 1 && width <= 8 ) ; int shift = exact_log2 ( width ) ; machine_mode idx_mode = GET_MODE ( idx ) ; machine_mode shift_mode ; rtx ( * gen_ashl ) ( rtx , rtx , rtx ) ; rtx ( * gen_pcvr1 ) ( rtx , rtx ) ; rtx ( * gen_pcvr2 ) ( rtx , rtx ) ; if ( TARGET_POWERPC64 ) { shift_mode = DImode ; gen_ashl = gen_ashldi3 ; gen_pcvr1 = BYTES_BIG_ENDIAN ? gen_altivec_lvsl_reg_di : gen_altivec_lvsr_reg_di ; gen_pcvr2 = BYTES_BIG_ENDIAN ? gen_altivec_lvsr_reg_di : gen_altivec_lvsl_reg_di ; } else { shift_mode = SImode ; gen_ashl = gen_ashlsi3 ; gen_pcvr1 = BYTES_BIG_ENDIAN ? gen_altivec_lvsl_reg_si : gen_altivec_lvsr_reg_si ; gen_pcvr2 = BYTES_BIG_ENDIAN ? gen_altivec_lvsr_reg_si : gen_altivec_lvsl_reg_si ; } rtx tmp = gen_reg_rtx ( shift_mode ) ; idx = convert_modes ( shift_mode , idx_mode , idx , 1 ) ; emit_insn ( gen_ashl ( tmp , idx , GEN_INT ( shift ) ) ) ; rtx pcvr1 = gen_reg_rtx ( V16QImode ) ; emit_insn ( gen_pcvr1 ( pcvr1 , tmp ) ) ; rtx sub_target = simplify_gen_subreg ( V16QImode , target , mode , 0 ) ; rtx perm1 = gen_altivec_vperm_v8hiv16qi ( sub_target , sub_target , sub_target , pcvr1 ) ; emit_insn ( perm1 ) ; rs6000_expand_vector_set ( target , val , const0_rtx ) ; rtx pcvr2 = gen_reg_rtx ( V16QImode ) ; emit_insn ( gen_pcvr2 ( pcvr2 , tmp ) ) ; rtx perm2 = gen_altivec_vperm_v8hiv16qi ( sub_target , sub_target , sub_target , pcvr2 ) ; emit_insn ( perm2 ) ; } </s>

Insert VAL into IDX of TARGET , VAL size is same of the vector element , IDX is variable and also counts by vector element size for p9 and above .


<s> bool ix86_notrack_prefixed_insn_p ( rtx_insn * insn ) { if ( ! insn || ! ( ( flag_cf_protection & CF_BRANCH ) ) ) return false ; if ( CALL_P ( insn ) ) { rtx call = get_call_rtx_from ( insn ) ; gcc_assert ( call != NULL_RTX ) ; rtx addr = XEXP ( call , 0 ) ; if ( MEM_P ( addr ) && GET_CODE ( XEXP ( addr , 0 ) ) == SYMBOL_REF ) return false ; else return find_reg_note ( insn , REG_CALL_NOCF_CHECK , 0 ) ; } if ( JUMP_P ( insn ) && ! flag_cet_switch ) { rtx target = JUMP_LABEL ( insn ) ; if ( target == NULL_RTX || ANY_RETURN_P ( target ) ) return false ; rtx_insn * label = as_a < rtx_insn * > ( target ) ; rtx_insn * table = next_insn ( label ) ; if ( table == NULL_RTX || ! JUMP_TABLE_DATA_P ( table ) ) return false ; else return true ; } return false ; } </s>

Return 1 if control tansfer instruction INSN should be encoded with notrack prefix .


"Not expecting modifiers with immediates"

Commutes the operands in the given instruction by changing the operands order and/or changing the instruction 's opcode and/or the immediate value operand .


<s> bool M68kFrameLowering :: canSimplifyCallFramePseudos ( const MachineFunction & MF ) const { return hasReservedCallFrame ( MF ) || ( hasFP ( MF ) && ! TRI -> hasStackRealignment ( MF ) ) || TRI -> hasBasePointer ( MF ) ; } </s>

canSimplifyCallFramePseudos - If there is a reserved call frame , the call frame pseudos can be simplified .


<s> static bool tilegx_vector_mode_supported_p ( machine_mode mode ) { return mode == V8QImode || mode == V4HImode || mode == V2SImode ; } </s>


<s> void PPCTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , APInt & KnownZero , APInt & KnownOne , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { KnownZero = KnownOne = APInt ( KnownZero . getBitWidth ( ) , 0 ) ; switch ( Op . getOpcode ( ) ) { default : break ; case PPCISD :: LBRX : { if ( cast < VTSDNode > ( Op . getOperand ( 2 ) ) -> getVT ( ) == MVT :: i16 ) KnownZero = 0xFFFF0000 ; break ; } case ISD :: INTRINSIC_WO_CHAIN : { switch ( cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ) { default : break ; case Intrinsic :: ppc_altivec_vcmpbfp_p : case Intrinsic :: ppc_altivec_vcmpeqfp_p : case Intrinsic :: ppc_altivec_vcmpequb_p : case Intrinsic :: ppc_altivec_vcmpequh_p : case Intrinsic :: ppc_altivec_vcmpequw_p : case Intrinsic :: ppc_altivec_vcmpequd_p : case Intrinsic :: ppc_altivec_vcmpgefp_p : case Intrinsic :: ppc_altivec_vcmpgtfp_p : case Intrinsic :: ppc_altivec_vcmpgtsb_p : case Intrinsic :: ppc_altivec_vcmpgtsh_p : case Intrinsic :: ppc_altivec_vcmpgtsw_p : case Intrinsic :: ppc_altivec_vcmpgtsd_p : case Intrinsic :: ppc_altivec_vcmpgtub_p : case Intrinsic :: ppc_altivec_vcmpgtuh_p : case Intrinsic :: ppc_altivec_vcmpgtuw_p : case Intrinsic :: ppc_altivec_vcmpgtud_p : KnownZero = ~ 1U ; break ; } } } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> bool AArch64AsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { unsigned Kind = Fixup . getKind ( ) ; if ( Kind == FK_NONE ) return true ; if ( Kind == AArch64 :: fixup_aarch64_pcrel_adrp_imm21 ) return true ; AArch64MCExpr :: VariantKind RefKind = static_cast < AArch64MCExpr :: VariantKind > ( Target . getRefKind ( ) ) ; AArch64MCExpr :: VariantKind SymLoc = AArch64MCExpr :: getSymbolLoc ( RefKind ) ; if ( Kind == AArch64 :: fixup_aarch64_ldr_pcrel_imm19 && SymLoc == AArch64MCExpr :: VK_GOT ) return true ; return false ; } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> auto end ( ) const { return Data . end ( ) ; } </s>

Get a const_iterator to the end of the symbol table .


<s> bool SIInstrInfo :: shouldClusterMemOps ( MachineInstr & FirstLdSt , MachineInstr & SecondLdSt , unsigned NumLoads ) const { const MachineOperand * FirstDst = nullptr ; const MachineOperand * SecondDst = nullptr ; if ( ( isMUBUF ( FirstLdSt ) && isMUBUF ( SecondLdSt ) ) || ( isMTBUF ( FirstLdSt ) && isMTBUF ( SecondLdSt ) ) || ( isFLAT ( FirstLdSt ) && isFLAT ( SecondLdSt ) ) ) { FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: vdata ) ; SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: vdata ) ; } else if ( isSMRD ( FirstLdSt ) && isSMRD ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: sdst ) ; SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: sdst ) ; } else if ( isDS ( FirstLdSt ) && isDS ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: vdst ) ; SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: vdst ) ; } if ( ! FirstDst || ! SecondDst ) return false ; unsigned LoadClusterThreshold = 16 ; const MachineRegisterInfo & MRI = FirstLdSt . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * DstRC = MRI . getRegClass ( FirstDst -> getReg ( ) ) ; return ( NumLoads * DstRC -> getSize ( ) ) <= LoadClusterThreshold ; } </s>

Returns true if the two given memory operations should be scheduled adjacent .

AMDGPU SI AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName 16


<s> virtual const Z80InstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> static unsigned int mips_get_compress_on_flags ( tree attributes ) { unsigned int flags = 0 ; if ( lookup_attribute ( "mips16" , attributes ) != NULL ) flags |= MASK_MIPS16 ; if ( lookup_attribute ( "micromips" , attributes ) != NULL ) flags |= MASK_MICROMIPS ; return flags ; } </s>

Return the set of compression modes that are explicitly required by the attributes in ATTRIBUTES .


<s> bool runOnFunction ( Function & F ) override { if ( skipFunction ( F ) ) return false ; auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; auto & TM = TPC -> getTM < PPCTargetMachine > ( ) ; ST = TM . getSubtargetImpl ( F ) ; PHINodeSet PromotablePHINodes = getPromotablePHINodes ( F ) ; B2IMap Bool2IntMap ; bool Changed = false ; for ( auto & BB : F ) { for ( auto & I : BB ) { if ( auto * R = dyn_cast < ReturnInst > ( & I ) ) if ( F . getReturnType ( ) -> isIntegerTy ( 1 ) ) Changed |= runOnUse ( R -> getOperandUse ( 0 ) , PromotablePHINodes , Bool2IntMap ) ; if ( auto * CI = dyn_cast < CallInst > ( & I ) ) for ( auto & U : CI -> operands ( ) ) if ( U -> getType ( ) -> isIntegerTy ( 1 ) ) Changed |= runOnUse ( U , PromotablePHINodes , Bool2IntMap ) ; } } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { const M680x0Subtarget & STI = MF . getSubtarget < M680x0Subtarget > ( ) ; M680x0MachineFunctionInfo * MxFI = MF . getInfo < M680x0MachineFunctionInfo > ( ) ; unsigned GlobalBaseReg = MxFI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg == 0 ) return false ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; const M680x0InstrInfo * TII = STI . getInstrInfo ( ) ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( M680x0 :: LEA32q ) , GlobalBaseReg ) . addExternalSymbol ( "_GLOBAL_OFFSET_TABLE_" , M680x0II :: MO_GOTPCREL ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


"Successfully decoded 64-bit instruction."

"Not a 64-bit instruction, falling back to 32-bit."

Returns the disassembly of a single instruction .


<s> const TargetRegisterClass * ARMBaseRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & ARM :: GPRRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s>
bool
DeadCodeElimination
::
erase
(
const
SetVector
<
NodeId
>
&
Nodes
)
{
if
(
Nodes
.
empty
(
)
)
return
false
;
NodeList
DRNs
,
DINs
;
for
(
auto
I
:
Nodes
)
{
auto
BA
=
DFG
.
addr
<
NodeBase
*
>
(
I
)
;
uint16_t
Type
=
BA
.
Addr
->
getType
(
)
;
if
(
Type
==
NodeAttrs
::
Ref
)
{
DRNs
.
push_back
(
DFG
.
addr
<
RefNode
*
>
(
I
)
)
;
continue
;
}
uint16_t
Kind
=
BA
.
Addr
->
getKind
(
)
;
if
(
Kind
==
NodeAttrs
::
Stmt
||
Kind
==
NodeAttrs
::
Phi
)
{
for
(
auto
N
:
NodeAddr
<
CodeNode
*
>
(
BA
)
.
Addr
->
members
(
DFG
)
)
DRNs
.
push_back
(
N
)
;
DINs
.
push_back
(
DFG
.
addr
<
InstrNode
*
>
(
I
)
)
;
}
else
{
llvm_unreachable
(
"Unexpected code node"
)
;
return
false
;
}
}
auto
UsesFirst
=
[
]
(
NodeAddr
<
RefNode
*
>
A
,
NodeAddr
<
RefNode
*
>
B
)
->
bool
{
uint16_t
KindA
=
A
.
Addr
->
getKind
(
)
,
KindB
=
B
.
Addr
->
getKind
(
)
;
if
(
KindA
==
NodeAttrs
::
Use
&&
KindB
==
NodeAttrs
::
Def
)
return
true
;
if
(
KindA
==
NodeAttrs
::
Def
&&
KindB
==
NodeAttrs
::
Use
)
return
false
;
return
A
.
Id
<
B
.
Id
;
}
;
llvm
::
sort
(
DRNs
.
begin
(
)
,
DRNs
.
end
(
)
,
UsesFirst
)
;
if
(
trace
(
)
)
dbgs
(
)
<<
"Removing dead ref nodes:\n"
;
for
(
NodeAddr
<
RefNode
*
>
RA
:
DRNs
)
{
if
(
trace
(
)
)
dbgs
(
)
<<
"  "
<<
PrintNode
<
RefNode
*
>
(
RA
,
DFG
)
<<
'\n'
;
if
(
DFG
.
IsUse
(
RA
)
)
DFG
.
unlinkUse
(
RA
,
true
)
;
else
if
(
DFG
.
IsDef
(
RA
)
)
DFG
.
unlinkDef
(
RA
,
true
)
;
}
for
(
NodeAddr
<
InstrNode
*
>
IA
:
DINs
)
{
NodeAddr
<
BlockNode
*
>
BA
=
IA
.
Addr
->
getOwner
(
DFG
)
;
BA
.
Addr
->
removeMember
(
IA
,
DFG
)
;
if
(
!
DFG
.
IsCode
<
NodeAttrs
::
Stmt
>
(
IA
)
)
continue
;
MachineInstr
*
MI
=
NodeAddr
<
StmtNode
*
>
(
IA
)
.
Addr
->
getCode
(
)
;
if
(
trace
(
)
)
dbgs
(
)
<<
"erasing: "
<<
*
MI
;
MI
->
eraseFromParent
(
)
;
}
return
true
;
}
</s>

erase - Erases an element identified by Key , if it exists .

Hexagon
"Unexpected code node"
"Removing dead ref nodes:\n"
"  "
"erasing: "


<s>
bool
ARMAsmPrinter
::
doInitialization
(
Module
&
M
)
{
bool
Result
=
AsmPrinter
::
doInitialization
(
M
)
;
DW
=
getAnalysisIfAvailable
<
DwarfWriter
>
(
)
;
if
(
Subtarget
->
isThumb
(
)
)
O
<<
"\t.syntax unified\n"
;
if
(
Subtarget
->
isTargetELF
(
)
)
{
std
::
string
CPUString
=
Subtarget
->
getCPUString
(
)
;
if
(
CPUString
!=
"generic"
)
O
<<
"\t.cpu "
<<
CPUString
<<
'\n'
;
if
(
Subtarget
->
hasVFP2
(
)
)
O
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
VFP_arch
<<
", 2\n"
;
if
(
!
UnsafeFPMath
)
O
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
ABI_FP_denormal
<<
", 1\n"
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
ABI_FP_exceptions
<<
", 1\n"
;
if
(
FiniteOnlyFPMath
(
)
)
O
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
ABI_FP_number_model
<<
", 1\n"
;
else
O
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
ABI_FP_number_model
<<
", 3\n"
;
O
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
ABI_align8_needed
<<
", 1\n"
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
ABI_align8_preserved
<<
", 1\n"
;
if
(
Subtarget
->
isAAPCS_ABI
(
)
&&
FloatABIType
==
FloatABI
::
Hard
)
O
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
ABI_HardFP_use
<<
", 3\n"
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
ABI_VFP_args
<<
", 1\n"
;
}
return
Result
;
}
</s>

Set up the AsmPrinter when we are working on a new module .

ARM
ARM
"\t.syntax unified\n"
"generic"
"\t.cpu "
"\t.eabi_attribute "
ARMBuildAttrs::VFP_arch
", 2\n"
"\t.eabi_attribute "
ARMBuildAttrs::ABI_FP_denormal
", 1\n"
"\t.eabi_attribute "
ARMBuildAttrs::ABI_FP_exceptions
", 1\n"
"\t.eabi_attribute "
ARMBuildAttrs::ABI_FP_number_model
", 1\n"
"\t.eabi_attribute "
ARMBuildAttrs::ABI_FP_number_model
", 3\n"
"\t.eabi_attribute "
ARMBuildAttrs::ABI_align8_needed
", 1\n"
"\t.eabi_attribute "
ARMBuildAttrs::ABI_align8_preserved
", 1\n"
"\t.eabi_attribute "
ARMBuildAttrs::ABI_HardFP_use
", 3\n"
"\t.eabi_attribute "
ARMBuildAttrs::ABI_VFP_args
", 1\n"


<s> static bool isExtended ( uint64_t TSFlags ) { return ( TSFlags >> HexagonII :: ExtendedPos ) & HexagonII :: ExtendedMask ; } </s>

Test if the given EVT is extended ( as opposed to being simple ) .


<s> void X86RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; if ( ! TFI -> hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; uint64_t Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = 0 ; if ( Old -> getOpcode ( ) == getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( getSUBriOpcode ( Is64Bit , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Old -> getOpcode ( ) == getCallFrameDestroyOpcode ( ) ) ; uint64_t CalleeAmt = Old -> getOperand ( 1 ) . getImm ( ) ; Amount -= CalleeAmt ; if ( Amount ) { unsigned Opc = getADDriOpcode ( Is64Bit , Amount ) ; New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { unsigned Opc = getSUBriOpcode ( Is64Bit , CalleeAmt ) ; MachineInstr * Old = I ; MachineInstr * New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> int reg_unused_after ( rtx reg , rtx insn ) { enum rtx_code code ; rtx set ; set = single_set ( insn ) ; if ( set && GET_CODE ( SET_DEST ( set ) ) != MEM && reg_overlap_mentioned_p ( reg , SET_DEST ( set ) ) ) return 1 ; while ( ( insn = NEXT_INSN ( insn ) ) ) { rtx set ; if ( ! INSN_P ( insn ) ) continue ; code = GET_CODE ( insn ) ; if ( code == CODE_LABEL ) return 1 ; if ( code == JUMP_INSN ) return 0 ; else if ( code == INSN && GET_CODE ( PATTERN ( insn ) ) == SEQUENCE ) { int i ; int retval = 0 ; for ( i = 0 ; i < XVECLEN ( PATTERN ( insn ) , 0 ) ; i ++ ) { rtx this_insn = XVECEXP ( PATTERN ( insn ) , 0 , i ) ; rtx set = single_set ( this_insn ) ; if ( GET_CODE ( this_insn ) == CALL_INSN ) code = CALL_INSN ; else if ( GET_CODE ( this_insn ) == JUMP_INSN ) { if ( INSN_ANNULLED_BRANCH_P ( this_insn ) ) return 0 ; code = JUMP_INSN ; } if ( set && reg_overlap_mentioned_p ( reg , SET_SRC ( set ) ) ) return 0 ; if ( set && reg_overlap_mentioned_p ( reg , SET_DEST ( set ) ) ) { if ( GET_CODE ( SET_DEST ( set ) ) != MEM ) retval = 1 ; else return 0 ; } if ( set == 0 && reg_overlap_mentioned_p ( reg , PATTERN ( this_insn ) ) ) return 0 ; } if ( retval == 1 ) return 1 ; else if ( code == JUMP_INSN ) return 0 ; } set = single_set ( insn ) ; if ( set && reg_overlap_mentioned_p ( reg , SET_SRC ( set ) ) ) return 0 ; if ( set && reg_overlap_mentioned_p ( reg , SET_DEST ( set ) ) ) return GET_CODE ( SET_DEST ( set ) ) != MEM ; if ( set == 0 && reg_overlap_mentioned_p ( reg , PATTERN ( insn ) ) ) return 0 ; if ( code == CALL_INSN && call_really_used_regs [ REGNO ( reg ) ] ) return 1 ; } return 1 ; } </s>

Return nonzero if REG is not used after INSN . We assume REG is a reload reg , and therefore does not live past labels or calls or jumps .


<s> const BlackfinRegisterInfo * getRegisterInfo ( ) { return static_cast < const BlackfinTargetMachine & > ( TM ) . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


"%qE attribute ignored without %<-mcmse%> "

"%qE attribute only applies to base type of a "

Called upon detection of the use of the cmse_nonsecure_call attribute , this function will check whether the attribute is allowed here and will add the attribute to the function type tree or otherwise issue a diagnostic . The reason we check this at declaration time is to only allow the use of the attribute with declarations of function pointers and not function declarations . This function checks NODE is of the expected type and issues diagnostics otherwise using NAME . If it is not of the expected type * NO_ADD_ATTRS will be set to true .


<s> SDValue PPCTargetLowering :: LowerCall ( TargetLowering :: CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const { SelectionDAG & DAG = CLI . DAG ; DebugLoc & dl = CLI . DL ; SmallVector < ISD :: OutputArg , 32 > & Outs = CLI . Outs ; SmallVector < SDValue , 32 > & OutVals = CLI . OutVals ; SmallVector < ISD :: InputArg , 32 > & Ins = CLI . Ins ; SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; bool & isTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool isVarArg = CLI . IsVarArg ; if ( isTailCall ) isTailCall = IsEligibleForTailCallOptimization ( Callee , CallConv , isVarArg , Ins , DAG ) ; if ( PPCSubTarget . isSVR4ABI ( ) && ! PPCSubTarget . isPPC64 ( ) ) return LowerCall_SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; return LowerCall_Darwin ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; } </s>

This hook must be implemented to lower calls into the specified DAG .

PowerPC PPC ISD::OutputArg 32 32 ISD::InputArg 32 PPC PPC PPC