<s> bool AArch64TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( VT . getVectorNumElements ( ) == 4 && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ 4 ] ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { if ( M [ i ] < 0 ) PFIndexes [ i ] = 8 ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ 0 ] * 9 * 9 * 9 + PFIndexes [ 1 ] * 9 * 9 + PFIndexes [ 2 ] * 9 + PFIndexes [ 3 ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> 30 ) ; if ( Cost <= 4 ) return true ; } bool DummyBool ; int DummyInt ; unsigned DummyUnsigned ; return ( ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isREVMask ( M , VT , 64 ) || isREVMask ( M , VT , 32 ) || isREVMask ( M , VT , 16 ) || isEXTMask ( M , VT , DummyBool , DummyUnsigned ) || isTRNMask ( M , VT , DummyUnsigned ) || isUZPMask ( M , VT , DummyUnsigned ) || isZIPMask ( M , VT , DummyUnsigned ) || isTRN_v_undef_Mask ( M , VT , DummyUnsigned ) || isUZP_v_undef_Mask ( M , VT , DummyUnsigned ) || isZIP_v_undef_Mask ( M , VT , DummyUnsigned ) || isINSMask ( M , VT . getVectorNumElements ( ) , DummyBool , DummyInt ) || isConcatMask ( M , VT , VT . getSizeInBits ( ) == 128 ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s>
static
void
bpf_output_constructor
(
rtx
symbol
,
int
priority
ATTRIBUTE_UNUSED
)
{
tree
decl
=
SYMBOL_REF_DECL
(
symbol
)
;
if
(
decl
)
sorry_at
(
DECL_SOURCE_LOCATION
(
decl
)
,
"no constructors"
)
;
else
sorry
(
"no constructors"
)
;
}
</s>

Output the assembly code for a constructor . Since eBPF does n't support indirect calls , constructors are not supported .


<s> static int h8300_monitor_function_p ( tree func ) { tree a ; if ( TREE_CODE ( func ) != FUNCTION_DECL ) return 0 ; a = lookup_attribute ( "monitor" , DECL_ATTRIBUTES ( func ) ) ; return a != NULL_TREE ; } </s>

Return nonzero if FUNC is a monitor function as specified by the `` monitor '' attribute .


<s> void releaseTopNode ( SUnit * SU ) override { } </s>

SU has had all predecessor dependencies resolved .


<s> virtual const SystemZRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
PPC
::
NumTargetFixupKinds
]
=
{
{
"fixup_ppc_br24"
,
6
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_brcond14"
,
16
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_lo16"
,
16
,
16
,
0
}
,
{
"fixup_ppc_ha16"
,
16
,
16
,
0
}
,
{
"fixup_ppc_lo14"
,
16
,
14
,
0
}
,
{
"fixup_ppc_toc"
,
0
,
64
,
0
}
,
{
"fixup_ppc_toc16"
,
16
,
16
,
0
}
,
{
"fixup_ppc_toc16_ds"
,
16
,
14
,
0
}
,
{
"fixup_ppc_tlsreg"
,
0
,
0
,
0
}
,
{
"fixup_ppc_nofixup"
,
0
,
0
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s>
static
rtx
mips_expand_builtin_msa_test_branch
(
enum
insn_code
icode
,
tree
exp
)
{
struct
expand_operand
ops
[
3
]
;
rtx_insn
*
cbranch
;
rtx_code_label
*
true_label
,
*
done_label
;
rtx
cmp_result
;
true_label
=
gen_label_rtx
(
)
;
done_label
=
gen_label_rtx
(
)
;
create_input_operand
(
&
ops
[
0
]
,
true_label
,
TYPE_MODE
(
TREE_TYPE
(
exp
)
)
)
;
mips_prepare_builtin_arg
(
&
ops
[
1
]
,
exp
,
0
)
;
create_fixed_operand
(
&
ops
[
2
]
,
const0_rtx
)
;
if
(
GET_CODE
(
ops
[
1
]
.
value
)
!=
REG
)
ops
[
1
]
.
value
=
force_reg
(
ops
[
1
]
.
mode
,
ops
[
1
]
.
value
)
;
if
(
(
cbranch
=
maybe_gen_insn
(
icode
,
3
,
ops
)
)
==
NULL_RTX
)
error
(
"failed to expand built-in function"
)
;
cmp_result
=
gen_reg_rtx
(
SImode
)
;
mips_emit_move
(
cmp_result
,
const0_rtx
)
;
emit_jump_insn
(
cbranch
)
;
emit_jump_insn
(
gen_jump
(
done_label
)
)
;
emit_barrier
(
)
;
emit_label
(
true_label
)
;
mips_emit_move
(
cmp_result
,
const1_rtx
)
;
emit_label
(
done_label
)
;
return
cmp_result
;
}
</s>

Expand an MSA built-in for a compare and branch instruction specified by ICODE , set a general-purpose register to 1 if the branch was taken , 0 otherwise .


<s> void frv_expand_epilogue ( bool emit_return ) { frv_stack_t * info = frv_stack_info ( ) ; rtx fp = frame_pointer_rtx ; rtx sp = stack_pointer_rtx ; rtx return_addr ; int fp_offset ; fp_offset = info -> reg_offset [ FRAME_POINTER_REGNUM ] ; if ( ! current_function_sp_is_unchanging ) emit_insn ( gen_addsi3 ( sp , fp , frv_frame_offset_rtx ( - fp_offset ) ) ) ; frv_frame_access_standard_regs ( FRV_LOAD , info ) ; if ( info -> save_p [ LR_REGNO ] ) { int lr_offset ; rtx mem ; lr_offset = info -> reg_offset [ LR_REGNO ] ; if ( frame_pointer_needed ) mem = frv_frame_mem ( Pmode , fp , lr_offset - fp_offset ) ; else mem = frv_frame_mem ( Pmode , sp , lr_offset ) ; return_addr = gen_rtx_REG ( Pmode , TEMP_REGNO ) ; emit_insn ( gen_rtx_SET ( VOIDmode , return_addr , mem ) ) ; } else return_addr = gen_rtx_REG ( Pmode , LR_REGNO ) ; if ( frame_pointer_needed ) { emit_insn ( gen_rtx_SET ( VOIDmode , fp , gen_rtx_MEM ( Pmode , fp ) ) ) ; emit_insn ( gen_rtx_USE ( VOIDmode , fp ) ) ; } if ( info -> total_size != 0 ) { rtx offset = frv_frame_offset_rtx ( info -> total_size ) ; emit_insn ( gen_stack_adjust ( sp , sp , offset ) ) ; } if ( current_function_calls_eh_return ) emit_insn ( gen_stack_adjust ( sp , sp , EH_RETURN_STACKADJ_RTX ) ) ; if ( emit_return ) emit_jump_insn ( gen_epilogue_return ( return_addr ) ) ; else { rtx lr = return_addr ; if ( REGNO ( return_addr ) != LR_REGNO ) { lr = gen_rtx_REG ( Pmode , LR_REGNO ) ; emit_move_insn ( lr , return_addr ) ; } emit_insn ( gen_rtx_USE ( VOIDmode , lr ) ) ; } } </s>

Called after register allocation to add any instructions needed for the epilogue . Using an epilogue insn is favored compared to putting all of the instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook , since it allows the scheduler to intermix instructions with the saves of the caller saved registers . In some cases , it might be necessary to emit a barrier instruction as the last insn to prevent such scheduling .


<s> static bool mips_in_small_data_p ( const_tree decl ) { unsigned HOST_WIDE_INT size ; if ( TREE_CODE ( decl ) == STRING_CST || TREE_CODE ( decl ) == FUNCTION_DECL ) return false ; if ( TARGET_ABICALLS || TARGET_VXWORKS_RTP ) return false ; if ( TREE_CODE ( decl ) == VAR_DECL && DECL_SECTION_NAME ( decl ) != 0 ) { const char * name ; name = DECL_SECTION_NAME ( decl ) ; if ( strcmp ( name , ".sdata" ) != 0 && strcmp ( name , ".sbss" ) != 0 ) return false ; if ( mips_lo_relocs [ SYMBOL_GP_RELATIVE ] || ! DECL_EXTERNAL ( decl ) ) return true ; } else if ( TARGET_EMBEDDED_DATA ) { if ( TREE_CODE ( decl ) != VAR_DECL ) return false ; if ( TREE_READONLY ( decl ) && ! TREE_SIDE_EFFECTS ( decl ) && ( ! DECL_INITIAL ( decl ) || TREE_CONSTANT ( DECL_INITIAL ( decl ) ) ) ) return false ; } if ( ! TARGET_LOCAL_SDATA && ! TREE_PUBLIC ( decl ) ) return false ; if ( ! TARGET_EXTERN_SDATA && DECL_P ( decl ) ) { if ( DECL_EXTERNAL ( decl ) ) return false ; if ( DECL_COMMON ( decl ) && DECL_INITIAL ( decl ) == NULL ) return false ; } size = int_size_in_bytes ( TREE_TYPE ( decl ) ) ; return size > 0 && size <= mips_small_data_threshold ; } </s>

Implement TARGET_IN_SMALL_DATA_P . Return true if it would be safe to access DECL using % gp_rel ( ... ) ( $ gp ) .


<s> bool Thumb2ITBlockPass :: runOnMachineFunction ( MachineFunction & Fn ) { const TargetMachine & TM = Fn . getTarget ( ) ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; TRI = TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ; restrictIT = TM . getSubtarget < ARMSubtarget > ( ) . restrictIT ( ) ; if ( ! AFI -> isThumbFunction ( ) ) return false ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ) { MachineBasicBlock & MBB = * MFI ; ++ MFI ; Modified |= InsertITInstructions ( MBB ) ; } if ( Modified ) AFI -> setHasITBlocks ( true ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool cr16_function_value_regno_p ( const unsigned int regno ) { return ( regno == cr16_ret_register ( ) ) ; } </s>

Worker function for TARGET_FUNCTION_VALUE_REGNO_P .


<s> static bool sparc_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { if ( aligned_p && size == 8 && ( GET_CODE ( x ) != CONST_INT && GET_CODE ( x ) != CONST_DOUBLE ) ) { if ( TARGET_V9 ) { assemble_integer_with_op ( "\t.xword\t" , x ) ; return true ; } else { assemble_aligned_integer ( 4 , const0_rtx ) ; assemble_aligned_integer ( 4 , x ) ; return true ; } } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . The sparc version has special handling for aligned DI-mode objects .


<s> bool detect_cmse_nonsecure_call ( tree addr ) { if ( ! addr ) return FALSE ; tree fntype = TREE_TYPE ( addr ) ; if ( use_cmse && lookup_attribute ( "cmse_nonsecure_call" , TYPE_ATTRIBUTES ( fntype ) ) ) return TRUE ; return FALSE ; } </s>

Returns true if -mcmse has been passed and the function pointed to by 'addr ' has the cmse_nonsecure_call attribute and returns false otherwise .


<s> unsigned X86TTI :: getIntImmCost ( Intrinsic :: ID IID , const APInt & Imm , Type * Ty ) const { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return ~ 0U ; switch ( IID ) { default : return TargetTransformInfo :: getIntImmCost ( IID , Imm , Ty ) ; case Intrinsic :: sadd_with_overflow : case Intrinsic :: uadd_with_overflow : case Intrinsic :: ssub_with_overflow : case Intrinsic :: usub_with_overflow : case Intrinsic :: smul_with_overflow : case Intrinsic :: umul_with_overflow : if ( Imm . getBitWidth ( ) <= 64 && isInt < 32 > ( Imm . getSExtValue ( ) ) ) return TCC_Free ; else return X86TTI :: getIntImmCost ( Imm , Ty ) ; case Intrinsic :: experimental_stackmap : case Intrinsic :: experimental_patchpoint_void : case Intrinsic :: experimental_patchpoint_i64 : if ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) return TCC_Free ; else return X86TTI :: getIntImmCost ( Imm , Ty ) ; } } </s>

Calculate the cost of materializing a 64-bit value .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool HexagonTargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { return LI -> getType ( ) -> getPrimitiveSizeInBits ( ) > 64 ; } </s>

Returns how the given ( atomic ) load should be expanded by the IR-level AtomicExpand pass .


<s> bool MipsMCCodeEmitter :: isMicroMips ( const MCSubtargetInfo & STI ) const { return STI . getFeatureBits ( ) & Mips :: FeatureMicroMips ; } </s>

Check whether a given symbol has been flagged with MICROMIPS flag .


<s> SDValue HexagonTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { if ( isHvxOperation ( N , DCI . DAG ) ) { if ( SDValue V = PerformHvxDAGCombine ( N , DCI ) ) return V ; return SDValue ( ) ; } if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; SDValue Op ( N , 0 ) ; const SDLoc & dl ( Op ) ; unsigned Opc = Op . getOpcode ( ) ; if ( Opc == HexagonISD :: P2D ) { SDValue P = Op . getOperand ( 0 ) ; switch ( P . getOpcode ( ) ) { case HexagonISD :: PTRUE : return DCI . DAG . getConstant ( - 1 , dl , ty ( Op ) ) ; case HexagonISD :: PFALSE : return getZero ( dl , ty ( Op ) , DCI . DAG ) ; default : break ; } } else if ( Opc == ISD :: VSELECT ) { SDValue Cond = Op . getOperand ( 0 ) ; if ( Cond -> getOpcode ( ) == ISD :: XOR ) { SDValue C0 = Cond . getOperand ( 0 ) , C1 = Cond . getOperand ( 1 ) ; if ( C1 -> getOpcode ( ) == HexagonISD :: PTRUE ) { SDValue VSel = DCI . DAG . getNode ( ISD :: VSELECT , dl , ty ( Op ) , C0 , Op . getOperand ( 2 ) , Op . getOperand ( 1 ) ) ; return VSel ; } } } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> bool PPCRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { if ( MF . getFunction ( ) -> hasFnAttribute ( "no-realign-stack" ) ) return false ; return true ; } </s>

True if the stack can be realigned for the target .


<s> bool ScheduleDAGPostRA :: isSchedulingBoundary ( const MachineInstr * MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) { return SchedImpl -> isSchedulingBoundary ( MI , MBB , MF ) ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> void tilepro_expand_unaligned_load ( rtx dest_reg , rtx mem , HOST_WIDE_INT bitsize , HOST_WIDE_INT bit_offset , bool sign ) { machine_mode mode ; rtx addr_lo , addr_hi ; rtx mem_lo , mem_hi , hi ; rtx mema , wide_result ; int last_byte_offset ; HOST_WIDE_INT byte_offset = bit_offset / BITS_PER_UNIT ; mode = GET_MODE ( dest_reg ) ; hi = gen_reg_rtx ( mode ) ; if ( bitsize == 2 * BITS_PER_UNIT && ( bit_offset % BITS_PER_UNIT ) == 0 ) { rtx lo ; mem_lo = adjust_address ( mem , QImode , byte_offset ) ; mem_hi = adjust_address ( mem , QImode , byte_offset + 1 ) ; lo = gen_reg_rtx ( mode ) ; emit_insn ( gen_zero_extendqisi2 ( lo , mem_lo ) ) ; if ( sign ) { rtx tmp = gen_reg_rtx ( mode ) ; emit_insn ( gen_extendqisi2 ( gen_lowpart ( SImode , hi ) , mem_hi ) ) ; emit_insn ( gen_ashlsi3 ( gen_lowpart ( SImode , tmp ) , gen_lowpart ( SImode , hi ) , GEN_INT ( 8 ) ) ) ; emit_insn ( gen_iorsi3 ( gen_lowpart ( SImode , dest_reg ) , gen_lowpart ( SImode , lo ) , gen_lowpart ( SImode , tmp ) ) ) ; } else { emit_insn ( gen_zero_extendqisi2 ( gen_lowpart ( SImode , hi ) , mem_hi ) ) ; emit_insn ( gen_insn_intlb ( gen_lowpart ( SImode , dest_reg ) , gen_lowpart ( SImode , hi ) , gen_lowpart ( SImode , lo ) ) ) ; } return ; } mema = XEXP ( mem , 0 ) ; addr_lo = force_reg ( Pmode , plus_constant ( Pmode , mema , byte_offset ) ) ; mem_lo = change_address ( mem , mode , gen_rtx_AND ( Pmode , addr_lo , GEN_INT ( - 4 ) ) ) ; set_mem_alias_set ( mem_lo , 0 ) ; last_byte_offset = ( bit_offset + bitsize - 1 ) / BITS_PER_UNIT ; addr_hi = force_reg ( Pmode , plus_constant ( Pmode , mema , last_byte_offset ) ) ; mem_hi = change_address ( mem , mode , gen_rtx_AND ( Pmode , addr_hi , GEN_INT ( - 4 ) ) ) ; set_mem_alias_set ( mem_hi , 0 ) ; if ( bitsize == 32 ) { addr_lo = make_safe_from ( addr_lo , dest_reg ) ; wide_result = dest_reg ; } else { wide_result = gen_reg_rtx ( mode ) ; } emit_move_insn ( hi , mem_hi ) ; emit_move_insn ( wide_result , mem_lo ) ; emit_insn ( gen_insn_dword_align ( gen_lowpart ( SImode , wide_result ) , gen_lowpart ( SImode , wide_result ) , gen_lowpart ( SImode , hi ) , addr_lo ) ) ; if ( bitsize != 32 ) { rtx extracted = extract_bit_field ( gen_lowpart ( SImode , wide_result ) , bitsize , bit_offset % BITS_PER_UNIT , ! sign , gen_lowpart ( SImode , dest_reg ) , SImode , SImode ) ; if ( extracted != dest_reg ) emit_move_insn ( dest_reg , gen_lowpart ( SImode , extracted ) ) ; } } </s>


<s> const SISubtarget * GCNTargetMachine :: getSubtargetImpl ( const Function & F ) const { StringRef GPU = getGPUName ( F ) ; StringRef FS = getFeatureString ( F ) ; SmallString < 128 > SubtargetKey ( GPU ) ; SubtargetKey . append ( FS ) ; auto & I = SubtargetMap [ SubtargetKey ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < SISubtarget > ( TargetTriple , GPU , FS , * this ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; SIGISelActualAccessor * GISel = new SIGISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new AMDGPUCallLowering ( * I -> getTargetLowering ( ) ) ) ; I -> setGISelAccessor ( * GISel ) ; } I -> setScalarizeGlobalBehavior ( ScalarizeGlobal ) ; return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> Value * GCNTTIImpl :: rewriteIntrinsicWithAddressSpace ( IntrinsicInst * II , Value * OldV , Value * NewV ) const { auto IntrID = II -> getIntrinsicID ( ) ; switch ( IntrID ) { case Intrinsic :: amdgcn_atomic_inc : case Intrinsic :: amdgcn_atomic_dec : case Intrinsic :: amdgcn_ds_fadd : case Intrinsic :: amdgcn_ds_fmin : case Intrinsic :: amdgcn_ds_fmax : { const ConstantInt * IsVolatile = cast < ConstantInt > ( II -> getArgOperand ( 4 ) ) ; if ( ! IsVolatile -> isZero ( ) ) return nullptr ; Module * M = II -> getParent ( ) -> getParent ( ) -> getParent ( ) ; Type * DestTy = II -> getType ( ) ; Type * SrcTy = NewV -> getType ( ) ; Function * NewDecl = Intrinsic :: getDeclaration ( M , II -> getIntrinsicID ( ) , { DestTy , SrcTy } ) ; II -> setArgOperand ( 0 , NewV ) ; II -> setCalledFunction ( NewDecl ) ; return II ; } case Intrinsic :: amdgcn_is_shared : case Intrinsic :: amdgcn_is_private : { unsigned TrueAS = IntrID == Intrinsic :: amdgcn_is_shared ? AMDGPUAS :: LOCAL_ADDRESS : AMDGPUAS :: PRIVATE_ADDRESS ; unsigned NewAS = NewV -> getType ( ) -> getPointerAddressSpace ( ) ; LLVMContext & Ctx = NewV -> getType ( ) -> getContext ( ) ; ConstantInt * NewVal = ( TrueAS == NewAS ) ? ConstantInt :: getTrue ( Ctx ) : ConstantInt :: getFalse ( Ctx ) ; return NewVal ; } case Intrinsic :: ptrmask : { unsigned OldAS = OldV -> getType ( ) -> getPointerAddressSpace ( ) ; unsigned NewAS = NewV -> getType ( ) -> getPointerAddressSpace ( ) ; Value * MaskOp = II -> getArgOperand ( 1 ) ; Type * MaskTy = MaskOp -> getType ( ) ; bool DoTruncate = false ; if ( ! getTLI ( ) -> isNoopAddrSpaceCast ( OldAS , NewAS ) ) { if ( DL . getPointerSizeInBits ( OldAS ) != 64 || DL . getPointerSizeInBits ( NewAS ) != 32 ) return nullptr ; KnownBits Known = computeKnownBits ( MaskOp , DL , 0 , nullptr , II ) ; if ( Known . countMinLeadingOnes ( ) < 32 ) return nullptr ; DoTruncate = true ; } IRBuilder < > B ( II ) ; if ( DoTruncate ) { MaskTy = B . getInt32Ty ( ) ; MaskOp = B . CreateTrunc ( MaskOp , MaskTy ) ; } return B . CreateIntrinsic ( Intrinsic :: ptrmask , { NewV -> getType ( ) , MaskTy } , { NewV , MaskOp } ) ; } default : return nullptr ; } } </s>

Rewrite intrinsic call II such that OldV will be replaced with NewV , which has a different address space .


<s> void VERegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const VEFrameLowering * TFI = getFrameLowering ( MF ) ; Register FrameReg ; int Offset ; Offset = TFI -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) . getFixed ( ) ; Offset += MI . getOperand ( FIOperandNum + offsetToDisp ( MI ) ) . getImm ( ) ; if ( MI . getOpcode ( ) == VE :: STQrii ) { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; Register SrcReg = MI . getOperand ( 3 ) . getReg ( ) ; Register SrcHiReg = getSubReg ( SrcReg , VE :: sub_even ) ; Register SrcLoReg = getSubReg ( SrcReg , VE :: sub_odd ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( VE :: STrii ) ) . addReg ( FrameReg ) . addImm ( 0 ) . addImm ( 0 ) . addReg ( SrcLoReg ) ; replaceFI ( MF , II , * StMI , dl , 0 , Offset , FrameReg ) ; MI . setDesc ( TII . get ( VE :: STrii ) ) ; MI . getOperand ( 3 ) . setReg ( SrcHiReg ) ; Offset += 8 ; } else if ( MI . getOpcode ( ) == VE :: LDQrii ) { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; Register DestReg = MI . getOperand ( 0 ) . getReg ( ) ; Register DestHiReg = getSubReg ( DestReg , VE :: sub_even ) ; Register DestLoReg = getSubReg ( DestReg , VE :: sub_odd ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( VE :: LDrii ) , DestLoReg ) . addReg ( FrameReg ) . addImm ( 0 ) . addImm ( 0 ) ; replaceFI ( MF , II , * StMI , dl , 1 , Offset , FrameReg ) ; MI . setDesc ( TII . get ( VE :: LDrii ) ) ; MI . getOperand ( 0 ) . setReg ( DestHiReg ) ; Offset += 8 ; } replaceFI ( MF , II , MI , dl , FIOperandNum , Offset , FrameReg ) ; } </s>


<s> bool isToken ( ) const override { return Kind == k_Token ; } </s>


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Mips Emit GP Restore"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool ARMPreAllocLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { if ( AssumeMisalignedLoadStores || skipFunction ( * Fn . getFunction ( ) ) ) return false ; TD = & Fn . getDataLayout ( ) ; STI = & static_cast < const ARMSubtarget & > ( Fn . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; MF = & Fn ; bool Modified = false ; for ( MachineBasicBlock & MFI : Fn ) Modified |= RescheduleLoadStoreInstrs ( & MFI ) ; return Modified ; } </s>


<s> bool TriCoreFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool rs6000_is_valid_shift_mask ( rtx mask , rtx shift , machine_mode mode ) { int nb , ne ; if ( ! rs6000_is_valid_mask ( mask , & nb , & ne , mode ) ) return false ; int n = GET_MODE_PRECISION ( mode ) ; int sh = - 1 ; if ( CONST_INT_P ( XEXP ( shift , 1 ) ) ) { sh = INTVAL ( XEXP ( shift , 1 ) ) ; if ( sh < 0 || sh >= n ) return false ; } rtx_code code = GET_CODE ( shift ) ; if ( sh == 0 ) code = ROTATE ; if ( code == ROTATE && sh >= 0 && nb >= ne && ne >= sh ) code = ASHIFT ; if ( code == ROTATE && sh >= 0 && nb >= ne && nb < sh ) { code = LSHIFTRT ; sh = n - sh ; } if ( mode == DImode && code == ROTATE ) return ( nb == 63 || ne == 0 || ne == sh ) ; if ( mode == SImode && code == ROTATE ) return ( nb < 32 && ne < 32 && sh < 32 ) ; if ( ne > nb ) return false ; if ( sh < 0 ) return false ; if ( code == ASHIFT && ne < sh ) return false ; if ( nb < 32 && ne < 32 && sh < 32 && ! ( code == LSHIFTRT && nb >= 32 - sh ) ) return true ; if ( code == LSHIFTRT ) sh = 64 - sh ; if ( nb == 63 || ne == 0 || ne == sh ) return ! ( code == LSHIFTRT && nb >= sh ) ; return false ; } </s>

Return whether MASK ( a CONST_INT ) is a valid mask for any rlw [ i ] nm , rld [ i ] cl , rld [ i ] cr , or rld [ i ] c instruction , to implement an AND with shift SHIFT ( a ROTATE , ASHIFT , or LSHIFTRT ) in mode MODE .


<s> bool isReg ( ) const { return Kind == k_Register ; } </s>


<s> bool MipsRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; const MipsSubtarget & Subtarget = MF . getSubtarget < MipsSubtarget > ( ) ; unsigned FP = Subtarget . isGP32bit ( ) ? Mips :: FP : Mips :: FP_64 ; unsigned BP = Subtarget . isGP32bit ( ) ? Mips :: S7 : Mips :: S7_64 ; if ( ! Subtarget . hasStandardEncoding ( ) ) return false ; if ( ! MF . getRegInfo ( ) . canReserveReg ( FP ) ) return false ; if ( Subtarget . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) ) return true ; return MF . getRegInfo ( ) . canReserveReg ( BP ) ; } </s>


"Instr doesn't have FrameIndex operand!"


<s> CCAssignFn * X86FastISel :: CCAssignFnForCall ( CallingConv :: ID CC , bool isTaillCall ) { if ( Subtarget -> is64Bit ( ) ) { if ( CC == CallingConv :: GHC ) return CC_X86_64_GHC ; else if ( Subtarget -> isTargetWin64 ( ) ) return CC_X86_Win64_C ; else return CC_X86_64_C ; } if ( CC == CallingConv :: X86_FastCall ) return CC_X86_32_FastCall ; else if ( CC == CallingConv :: X86_ThisCall ) return CC_X86_32_ThisCall ; else if ( CC == CallingConv :: Fast ) return CC_X86_32_FastCC ; else if ( CC == CallingConv :: GHC ) return CC_X86_32_GHC ; else return CC_X86_32_C ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> static int arm_get_vfp_saved_size ( void ) { unsigned int regno ; int count ; int saved ; saved = 0 ; if ( TARGET_HARD_FLOAT ) { count = 0 ; for ( regno = FIRST_VFP_REGNUM ; regno < LAST_VFP_REGNUM ; regno += 2 ) { if ( ( ! df_regs_ever_live_p ( regno ) || call_used_regs [ regno ] ) && ( ! df_regs_ever_live_p ( regno + 1 ) || call_used_regs [ regno + 1 ] ) ) { if ( count > 0 ) { if ( count == 2 && ! arm_arch6 ) count ++ ; saved += count * 8 ; } count = 0 ; } else count ++ ; } if ( count > 0 ) { if ( count == 2 && ! arm_arch6 ) count ++ ; saved += count * 8 ; } } return saved ; } </s>

Return the number of bytes required to save VFP registers .


<s> bool ARMPassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createGlobalMergePass ( TM ) ) ; return false ; } </s>


<s> void DLXInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator Position , unsigned SourceRegister , bool IsKill , int FrameIndex , const TargetRegisterClass * RegisterClass , const TargetRegisterInfo * RegisterInfo ) const { } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> static bool classof ( const MCExpr * E ) { return E -> getKind ( ) == MCExpr :: Target ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> static rtx cr16_function_arg ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; cum -> last_parm_in_reg = 0 ; if ( arg . end_marker_p ( ) ) return NULL_RTX ; if ( targetm . calls . must_pass_in_stack ( arg ) || ( cum -> ints < 0 ) ) return NULL_RTX ; if ( arg . mode == BLKmode ) { if ( enough_regs_for_param ( cum , arg . type , arg . mode ) != 0 ) { cum -> last_parm_in_reg = 1 ; return gen_rtx_REG ( arg . mode , MIN_REG_FOR_PASSING_ARGS + cum -> ints ) ; } } if ( ( MIN_REG_FOR_PASSING_ARGS + cum -> ints ) > MAX_REG_FOR_PASSING_ARGS ) return NULL_RTX ; else { if ( enough_regs_for_param ( cum , arg . type , arg . mode ) != 0 ) { cum -> last_parm_in_reg = 1 ; return gen_rtx_REG ( arg . mode , MIN_REG_FOR_PASSING_ARGS + cum -> ints ) ; } } return NULL_RTX ; } </s>

Implements the macro FUNCTION_ARG defined in cr16.h .


<s> SDValue AArch64SelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { const AArch64Subtarget & STI = DAG . getMachineFunction ( ) . getSubtarget < AArch64Subtarget > ( ) ; if ( STI . hasMOPS ( ) ) return EmitMOPS ( AArch64ISD :: MOPS_MEMCOPY , DAG , DL , Chain , Dst , Src , Size , Alignment , isVolatile , DstPtrInfo , SrcPtrInfo ) ; return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .


<s> void SparcRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ; if ( Offset >= - 4096 && Offset <= 4095 ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( SP :: I6 , false ) ; MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ; } else { unsigned OffHi = ( unsigned ) Offset >> 10U ; BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( SP :: SETHIi ) , SP :: G1 ) . addImm ( OffHi ) ; BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( SP :: ADDrr ) , SP :: G1 ) . addReg ( SP :: G1 ) . addReg ( SP :: I6 ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( SP :: G1 , false ) ; MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset & ( ( 1 << 10 ) - 1 ) ) ; } } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool AArch64TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Align , bool * Fast ) const { if ( Subtarget -> requiresStrictAlign ( ) ) return false ; if ( Fast ) { * Fast = ! Subtarget -> isMisaligned128StoreSlow ( ) || VT . getStoreSize ( ) != 16 || Align <= 2 || VT == MVT :: v2i64 ; } return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


Set up the AsmPrinter when we are working on a new module .


"rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n"

A C expression returning the cost of moving data from a register of class CLASS1 to one of CLASS2 .


<s> static bool aarch64_evpc_rev ( struct expand_vec_perm_d * d ) { unsigned int i , j , diff , nelt = d -> nelt ; rtx ( * gen ) ( rtx , rtx ) ; if ( ! d -> one_vector_p ) return false ; diff = d -> perm [ 0 ] ; switch ( diff ) { case 7 : switch ( d -> vmode ) { case V16QImode : gen = gen_aarch64_rev64v16qi ; break ; case V8QImode : gen = gen_aarch64_rev64v8qi ; break ; default : return false ; } break ; case 3 : switch ( d -> vmode ) { case V16QImode : gen = gen_aarch64_rev32v16qi ; break ; case V8QImode : gen = gen_aarch64_rev32v8qi ; break ; case V8HImode : gen = gen_aarch64_rev64v8hi ; break ; case V4HImode : gen = gen_aarch64_rev64v4hi ; break ; default : return false ; } break ; case 1 : switch ( d -> vmode ) { case V16QImode : gen = gen_aarch64_rev16v16qi ; break ; case V8QImode : gen = gen_aarch64_rev16v8qi ; break ; case V8HImode : gen = gen_aarch64_rev32v8hi ; break ; case V4HImode : gen = gen_aarch64_rev32v4hi ; break ; case V4SImode : gen = gen_aarch64_rev64v4si ; break ; case V2SImode : gen = gen_aarch64_rev64v2si ; break ; case V4SFmode : gen = gen_aarch64_rev64v4sf ; break ; case V2SFmode : gen = gen_aarch64_rev64v2sf ; break ; default : return false ; } break ; default : return false ; } for ( i = 0 ; i < nelt ; i += diff + 1 ) for ( j = 0 ; j <= diff ; j += 1 ) { gcc_assert ( i + j < nelt ) ; if ( d -> perm [ i + j ] != i + diff - j ) return false ; } if ( d -> testing_p ) return true ; emit_insn ( gen ( d -> target , d -> op0 ) ) ; return true ; } </s>


<s> void Nios2RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { } </s>


<s> void HexagonAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst MCB ; MCB . setOpcode ( Hexagon :: BUNDLE ) ; MCB . addOperand ( MCOperand :: createImm ( 0 ) ) ; const MCInstrInfo & MCII = * Subtarget -> getInstrInfo ( ) ; if ( MI -> isBundle ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI -> getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( ! MII -> isDebugValue ( ) && ! MII -> isImplicitDef ( ) ) HexagonLowerToMC ( MCII , & * MII , MCB , * this ) ; } else HexagonLowerToMC ( MCII , MI , MCB , * this ) ; bool Ok = HexagonMCInstrInfo :: canonicalizePacket ( MCII , * Subtarget , OutStreamer -> getContext ( ) , MCB , nullptr ) ; assert ( Ok ) ; ( void ) Ok ; if ( HexagonMCInstrInfo :: bundleSize ( MCB ) == 0 ) return ; OutStreamer -> EmitInstruction ( MCB , getSubtargetInfo ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .

Hexagon Hexagon Hexagon::BUNDLE 0 Hexagon Hexagon Hexagon Hexagon 0


<s>
const
char
*
getPassName
(
)
const
override
{
return
"X86 LEA Fixup"
;
}
</s>


<s> static bool h8300_print_operand_punct_valid_p ( unsigned char code ) { return ( code == '#' ) ; } </s>


<s> TargetLowering :: ConstraintWeight SystemZTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'a' : case 'd' : case 'h' : case 'r' : if ( CallOperandVal -> getType ( ) -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatingPointTy ( ) ) weight = CW_Register ; break ; case 'I' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isUInt < 8 > ( C -> getZExtValue ( ) ) ) weight = CW_Constant ; break ; case 'J' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isUInt < 12 > ( C -> getZExtValue ( ) ) ) weight = CW_Constant ; break ; case 'K' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isInt < 16 > ( C -> getSExtValue ( ) ) ) weight = CW_Constant ; break ; case 'L' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isInt < 20 > ( C -> getSExtValue ( ) ) ) weight = CW_Constant ; break ; case 'M' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( C -> getZExtValue ( ) == 0x7fffffff ) weight = CW_Constant ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> static void mips_output_args_xfer ( int fp_code , char direction ) { unsigned int gparg , fparg , f ; CUMULATIVE_ARGS cum ; gcc_assert ( TARGET_OLDABI ) ; mips_init_cumulative_args ( & cum , NULL ) ; for ( f = ( unsigned int ) fp_code ; f != 0 ; f >>= 2 ) { machine_mode mode ; struct mips_arg_info info ; if ( ( f & 3 ) == 1 ) mode = SFmode ; else if ( ( f & 3 ) == 2 ) mode = DFmode ; else gcc_unreachable ( ) ; mips_get_arg_info ( & info , & cum , mode , NULL , true ) ; gparg = mips_arg_regno ( & info , false ) ; fparg = mips_arg_regno ( & info , true ) ; if ( mode == SFmode ) mips_output_32bit_xfer ( direction , gparg , fparg ) ; else mips_output_64bit_xfer ( direction , gparg , fparg ) ; mips_function_arg_advance ( pack_cumulative_args ( & cum ) , mode , NULL , true ) ; } } </s>

Write out code to move floating-point arguments into or out of general registers . FP_CODE is the code describing which arguments are present ( see the comment above the definition of CUMULATIVE_ARGS in mips.h ) . DIRECTION is as for mips_output_32bit_xfer .


<s>
bool
Cpu0AsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNum
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
int
Offset
=
0
;
if
(
ExtraCode
)
{
return
true
;
}
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNum
)
;
assert
(
MO
.
isReg
(
)
&&
"unexpected inline asm memory operand"
)
;
O
<<
Offset
<<
"($"
<<
Cpu0InstPrinter
::
getRegisterName
(
MO
.
getReg
(
)
)
<<
")"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> void OR1KMCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { unsigned CurByte = 0 ; ++ MCNumEmitted ; unsigned Value = getBinaryCodeForInstr ( MI , Fixups , STI ) ; EmitBEConstant ( Value , 4 , CurByte , OS ) ; } </s>

Encode the given Inst to bytes and append to CB .


<s> outliner :: OutlinedFunction RISCVInstrInfo :: getOutliningCandidateInfo ( std :: vector < outliner :: Candidate > & RepeatedSequenceLocs ) const { auto CannotInsertCall = [ ] ( outliner :: Candidate & C ) { const TargetRegisterInfo * TRI = C . getMF ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; C . initLRU ( * TRI ) ; LiveRegUnits LRU = C . LRU ; return ! LRU . available ( RISCV :: X5 ) ; } ; llvm :: erase_if ( RepeatedSequenceLocs , CannotInsertCall ) ; if ( RepeatedSequenceLocs . size ( ) < 2 ) return outliner :: OutlinedFunction ( ) ; unsigned SequenceSize = 0 ; auto I = RepeatedSequenceLocs [ 0 ] . front ( ) ; auto E = std :: next ( RepeatedSequenceLocs [ 0 ] . back ( ) ) ; for ( ; I != E ; ++ I ) SequenceSize += getInstSizeInBytes ( * I ) ; unsigned CallOverhead = 8 ; for ( auto & C : RepeatedSequenceLocs ) C . setCallInfo ( MachineOutlinerDefault , CallOverhead ) ; unsigned FrameOverhead = 4 ; if ( RepeatedSequenceLocs [ 0 ] . getMF ( ) -> getSubtarget ( ) . getFeatureBits ( ) [ RISCV :: FeatureStdExtC ] ) FrameOverhead = 2 ; return outliner :: OutlinedFunction ( RepeatedSequenceLocs , SequenceSize , FrameOverhead , MachineOutlinerDefault ) ; } </s>

Returns a outliner : :OutlinedFunction struct containing target-specific information for a set of outlining candidates .


<s> static rtx mips_return_fpr_pair ( enum machine_mode mode , enum machine_mode mode1 , HOST_WIDE_INT offset1 , enum machine_mode mode2 , HOST_WIDE_INT offset2 ) { int inc ; inc = ( TARGET_NEWABI ? 2 : FP_INC ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode1 , FP_RETURN ) , GEN_INT ( offset1 ) ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode2 , FP_RETURN + inc ) , GEN_INT ( offset2 ) ) ) ) ; } </s>

Return a composite value in a pair of floating-point registers . MODE1 and OFFSET1 are the mode and byte offset for the first value , likewise MODE2 and OFFSET2 for the second . MODE is the mode of the complete value . For n32 & n64 , $ f0 always holds the first value and $ f2 the second . Otherwise the values are packed together as closely as possible .


<s> static tree resolve_vec_addec_subec ( resolution * res , rs6000_gen_builtins fcode , tree * args , tree * types , location_t loc ) { if ( TREE_CODE ( types [ 0 ] ) != VECTOR_TYPE || ! lang_hooks . types_compatible_p ( types [ 0 ] , types [ 1 ] ) || ! lang_hooks . types_compatible_p ( types [ 1 ] , types [ 2 ] ) ) { * res = resolved_bad ; return error_mark_node ; } switch ( TYPE_MODE ( TREE_TYPE ( types [ 0 ] ) ) ) { case E_SImode : { args [ 0 ] = save_expr ( args [ 0 ] ) ; args [ 1 ] = save_expr ( args [ 1 ] ) ; vec < tree , va_gc > * params = make_tree_vector ( ) ; vec_safe_push ( params , args [ 0 ] ) ; vec_safe_push ( params , args [ 1 ] ) ; tree as_c_builtin ; if ( fcode == RS6000_OVLD_VEC_ADDEC ) as_c_builtin = rs6000_builtin_decls [ RS6000_OVLD_VEC_ADDC ] ; else as_c_builtin = rs6000_builtin_decls [ RS6000_OVLD_VEC_SUBC ] ; tree call1 = altivec_resolve_overloaded_builtin ( loc , as_c_builtin , params ) ; params = make_tree_vector ( ) ; vec_safe_push ( params , args [ 0 ] ) ; vec_safe_push ( params , args [ 1 ] ) ; tree as_builtin ; if ( fcode == RS6000_OVLD_VEC_ADDEC ) as_builtin = rs6000_builtin_decls [ RS6000_OVLD_VEC_ADD ] ; else as_builtin = rs6000_builtin_decls [ RS6000_OVLD_VEC_SUB ] ; tree call2 = altivec_resolve_overloaded_builtin ( loc , as_builtin , params ) ; tree const1 = build_int_cstu ( TREE_TYPE ( types [ 0 ] ) , 1 ) ; tree ones_vector = build_vector_from_val ( types [ 0 ] , const1 ) ; tree and_expr = fold_build2_loc ( loc , BIT_AND_EXPR , types [ 0 ] , args [ 2 ] , ones_vector ) ; params = make_tree_vector ( ) ; vec_safe_push ( params , call2 ) ; vec_safe_push ( params , and_expr ) ; call2 = altivec_resolve_overloaded_builtin ( loc , as_c_builtin , params ) ; params = make_tree_vector ( ) ; vec_safe_push ( params , call1 ) ; vec_safe_push ( params , call2 ) ; tree or_builtin = rs6000_builtin_decls [ RS6000_OVLD_VEC_OR ] ; * res = resolved ; return altivec_resolve_overloaded_builtin ( loc , or_builtin , params ) ; } case E_TImode : * res = unresolved ; break ; default : * res = resolved_bad ; } return error_mark_node ; } </s>

Resolve an overloaded vec_addec or vec_subec call and return a tree expression for the resolved call if successful . ARGS contains the arguments to the call . TYPES contains their types . RES must be set to indicate the status of the resolution attempt . LOC contains statement location information .


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = 0 ; i != 4 ; ++ i ) Data [ Offset + i ] |= uint8_t ( ( Value >> ( ( 4 - i - 1 ) * 8 ) ) & 0xff ) ; } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static void alpha_override_options_after_change ( void ) { if ( optimize > 0 ) { if ( align_loops <= 0 ) align_loops = 16 ; if ( align_jumps <= 0 ) align_jumps = 16 ; } if ( align_functions <= 0 ) align_functions = 16 ; } </s>


<s> static rtx legitimize_dllimport_symbol ( rtx symbol , bool want_reg ) { tree imp_decl ; rtx x ; gcc_assert ( SYMBOL_REF_DECL ( symbol ) ) ; imp_decl = get_dllimport_decl ( SYMBOL_REF_DECL ( symbol ) , true ) ; x = DECL_RTL ( imp_decl ) ; if ( want_reg ) x = force_reg ( Pmode , x ) ; return x ; } </s>

Expand SYMBOL into its corresponding dllimport symbol . WANT_REG is true if we require the result be a register .


<s> static void aarch64_expand_vec_perm_1 ( rtx target , rtx op0 , rtx op1 , rtx sel ) { machine_mode vmode = GET_MODE ( target ) ; bool one_vector_p = rtx_equal_p ( op0 , op1 ) ; gcc_checking_assert ( vmode == V8QImode || vmode == V16QImode ) ; gcc_checking_assert ( GET_MODE ( op0 ) == vmode ) ; gcc_checking_assert ( GET_MODE ( op1 ) == vmode ) ; gcc_checking_assert ( GET_MODE ( sel ) == vmode ) ; gcc_checking_assert ( TARGET_SIMD ) ; if ( one_vector_p ) { if ( vmode == V8QImode ) { rtx pair = gen_reg_rtx ( V16QImode ) ; emit_insn ( gen_aarch64_combinev8qi ( pair , op0 , op0 ) ) ; emit_insn ( gen_aarch64_tbl1v8qi ( target , pair , sel ) ) ; } else { emit_insn ( gen_aarch64_tbl1v16qi ( target , op0 , sel ) ) ; } } else { rtx pair ; if ( vmode == V8QImode ) { pair = gen_reg_rtx ( V16QImode ) ; emit_insn ( gen_aarch64_combinev8qi ( pair , op0 , op1 ) ) ; emit_insn ( gen_aarch64_tbl1v8qi ( target , pair , sel ) ) ; } else { pair = gen_reg_rtx ( OImode ) ; emit_insn ( gen_aarch64_combinev16qi ( pair , op0 , op1 ) ) ; emit_insn ( gen_aarch64_tbl2v16qi ( target , pair , sel ) ) ; } } } </s>


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCRelaxableFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
override
{
llvm_unreachable
(
"RelaxInstruction() unimplemented"
)
;
return
false
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> bool SIFixupVectorISel :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: Selected ) ) return false ; if ( skipFunction ( MF . getFunction ( ) ) ) return false ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const SIInstrInfo * TII = ST . getInstrInfo ( ) ; const SIRegisterInfo * TRI = ST . getRegisterInfo ( ) ; bool FuncModified = false ; for ( MachineBasicBlock & MBB : MF ) { FuncModified |= fixupGlobalSaddr ( MBB , MF , MRI , ST , TII , TRI ) ; } return FuncModified ; } </s>

runOnMachineFunction - Emit the function body .


<s> static int length_fp_args ( rtx_insn * insn ) { int length = 0 ; rtx link ; for ( link = CALL_INSN_FUNCTION_USAGE ( insn ) ; link ; link = XEXP ( link , 1 ) ) { int arg_mode , regno ; rtx use = XEXP ( link , 0 ) ; if ( ! ( GET_CODE ( use ) == USE && GET_CODE ( XEXP ( use , 0 ) ) == REG && FUNCTION_ARG_REGNO_P ( REGNO ( XEXP ( use , 0 ) ) ) ) ) continue ; arg_mode = GET_MODE ( XEXP ( use , 0 ) ) ; regno = REGNO ( XEXP ( use , 0 ) ) ; if ( regno >= 32 && regno <= 39 ) { if ( arg_mode == SFmode ) length += 8 ; else length += 12 ; } } return length ; } </s>

Compute length of the FP argument copy sequence for INSN .


<s> ARMTargetLowering :: ConstraintType ARMTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'l' : return C_RegisterClass ; case 'w' : return C_RegisterClass ; case 'h' : return C_RegisterClass ; case 'x' : return C_RegisterClass ; case 't' : return C_RegisterClass ; case 'j' : return C_Other ; case 'Q' : return C_Memory ; } } else if ( Constraint . size ( ) == 2 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'T' : return C_RegisterClass ; case 'U' : return C_Memory ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


"CFGuard check mechanism only used on 32-bit X86"

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static inline unsigned int avr_ret_register ( void ) { return 24 ; } </s>

Returns register number for function return value .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
InfosBE
[
PPC
::
NumTargetFixupKinds
]
=
{
{
"fixup_ppc_br24"
,
6
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_br24_notoc"
,
6
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_brcond14"
,
16
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_br24abs"
,
6
,
24
,
0
}
,
{
"fixup_ppc_brcond14abs"
,
16
,
14
,
0
}
,
{
"fixup_ppc_half16"
,
0
,
16
,
0
}
,
{
"fixup_ppc_half16ds"
,
0
,
14
,
0
}
,
{
"fixup_ppc_pcrel34"
,
0
,
34
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_nofixup"
,
0
,
0
,
0
}
}
;
const
static
MCFixupKindInfo
InfosLE
[
PPC
::
NumTargetFixupKinds
]
=
{
{
"fixup_ppc_br24"
,
2
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_br24_notoc"
,
2
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_brcond14"
,
2
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_br24abs"
,
2
,
24
,
0
}
,
{
"fixup_ppc_brcond14abs"
,
2
,
14
,
0
}
,
{
"fixup_ppc_half16"
,
0
,
16
,
0
}
,
{
"fixup_ppc_half16ds"
,
2
,
14
,
0
}
,
{
"fixup_ppc_pcrel34"
,
0
,
34
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_nofixup"
,
0
,
0
,
0
}
}
;
if
(
Kind
>=
FirstLiteralRelocationKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
FK_NONE
)
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
(
Endian
==
support
::
little
InfosLE
:
InfosBE
)
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> static bool arm_fixed_condition_code_regs ( unsigned int * p1 , unsigned int * p2 ) { if ( ! TARGET_32BIT ) return false ; * p1 = CC_REGNUM ; * p2 = TARGET_HARD_FLOAT ? VFPCC_REGNUM : INVALID_REGNUM ; return true ; } </s>

Implement TARGET_FIXED_CONDITION_CODE_REGS . We only have condition code registers when not targetting Thumb1 . The VFP condition register only exists when generating hard-float code .


"Invalid mixing of IEEE 128-bit and IBM 128-bit floating "

Return the diagnostic message string if the binary operation OP is not permitted on TYPE1 and TYPE2 , NULL otherwise .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 Domain Reassignment Pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> EVT ARMTargetLowering :: getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const { if ( ( Op . isMemcpy ( ) || Op . isZeroMemset ( ) ) && Subtarget -> hasNEON ( ) && ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { bool Fast ; if ( Op . size ( ) >= 16 && ( Op . isAligned ( Align ( 16 ) ) || ( allowsMisalignedMemoryAccesses ( MVT :: v2f64 , 0 , Align ( 1 ) , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) { return MVT :: v2f64 ; } else if ( Op . size ( ) >= 8 && ( Op . isAligned ( Align ( 8 ) ) || ( allowsMisalignedMemoryAccesses ( MVT :: f64 , 0 , Align ( 1 ) , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) { return MVT :: f64 ; } } return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"X86 Atom pad short functions"
;
}
</s>


<s>
unsigned
MSP430InstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugInstr
(
)
)
continue
;
if
(
I
->
getOpcode
(
)
!=
MSP430
::
JMP
&&
I
->
getOpcode
(
)
!=
MSP430
::
JCC
&&
I
->
getOpcode
(
)
!=
MSP430
::
Bi
&&
I
->
getOpcode
(
)
!=
MSP430
::
Br
&&
I
->
getOpcode
(
)
!=
MSP430
::
Bm
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s> static void get_scratch_register_on_entry ( struct scratch_reg * sr , unsigned int regno1 , unsigned long live_regs ) { int regno = - 1 ; sr -> saved = false ; if ( regno1 != LR_REGNUM && ( live_regs & ( 1 << LR_REGNUM ) ) != 0 ) regno = LR_REGNUM ; else { unsigned int i ; for ( i = 4 ; i < 11 ; i ++ ) if ( regno1 != i && ( live_regs & ( 1 << i ) ) != 0 ) { regno = i ; break ; } if ( regno < 0 ) { if ( regno1 == IP_REGNUM && IS_NESTED ( arm_current_func_type ( ) ) ) regno1 = 3 ; regno = ( regno1 == 3 ? 2 : 3 ) ; sr -> saved = REGNO_REG_SET_P ( df_get_live_out ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) , regno ) ; } } sr -> reg = gen_rtx_REG ( SImode , regno ) ; if ( sr -> saved ) { rtx addr = gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ; rtx insn = emit_set_insn ( gen_frame_mem ( SImode , addr ) , sr -> reg ) ; rtx x = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - 4 ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , x ) ; } } </s>

Return a short-lived scratch register for use on function entry . In 32-bit mode , it is valid only after the registers are saved in the prologue . This register must be released by means of release_scratch_register_on_entry once it is dead .


<s> void AMDGPUTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , APInt & KnownZero , APInt & KnownOne , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { unsigned BitWidth = KnownZero . getBitWidth ( ) ; KnownZero = KnownOne = APInt ( BitWidth , 0 ) ; APInt KnownZero2 ; APInt KnownOne2 ; unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { default : break ; case AMDGPUISD :: CARRY : case AMDGPUISD :: BORROW : { KnownZero = APInt :: getHighBitsSet ( 32 , 31 ) ; break ; } case AMDGPUISD :: BFE_I32 : case AMDGPUISD :: BFE_U32 : { ConstantSDNode * CWidth = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ; if ( ! CWidth ) return ; uint32_t Width = CWidth -> getZExtValue ( ) & 0x1f ; if ( Opc == AMDGPUISD :: BFE_U32 ) KnownZero = APInt :: getHighBitsSet ( 32 , 32 - Width ) ; break ; } case AMDGPUISD :: FP_TO_FP16 : case AMDGPUISD :: FP16_ZEXT : { unsigned BitWidth = KnownZero . getBitWidth ( ) ; KnownZero = APInt :: getHighBitsSet ( BitWidth , BitWidth - 16 ) ; break ; } } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> static bool arm_can_output_mi_thunk ( const_tree , HOST_WIDE_INT , HOST_WIDE_INT vcall_offset , const_tree ) { if ( vcall_offset && TARGET_THUMB1 ) return false ; return true ; } </s>

Can output mi_thunk for all cases except for non-zero vcall_offset in Thumb1 .


<s> void XCoreTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { Known . resetAll ( ) ; switch ( Op . getOpcode ( ) ) { default : break ; case XCoreISD :: LADD : case XCoreISD :: LSUB : if ( Op . getResNo ( ) == 1 ) { Known . Zero = APInt :: getHighBitsSet ( Known . getBitWidth ( ) , Known . getBitWidth ( ) - 1 ) ; } break ; case ISD :: INTRINSIC_W_CHAIN : { unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) -> getZExtValue ( ) ; switch ( IntNo ) { case Intrinsic :: xcore_getts : Known . Zero = APInt :: getHighBitsSet ( Known . getBitWidth ( ) , Known . getBitWidth ( ) - 16 ) ; break ; case Intrinsic :: xcore_int : case Intrinsic :: xcore_inct : Known . Zero = APInt :: getHighBitsSet ( Known . getBitWidth ( ) , Known . getBitWidth ( ) - 8 ) ; break ; case Intrinsic :: xcore_testct : Known . Zero = APInt :: getHighBitsSet ( Known . getBitWidth ( ) , Known . getBitWidth ( ) - 1 ) ; break ; case Intrinsic :: xcore_testwct : Known . Zero = APInt :: getHighBitsSet ( Known . getBitWidth ( ) , Known . getBitWidth ( ) - 3 ) ; break ; } } break ; } } </s>


Create a TOC reference for symbol_ref SYMBOL . If LARGETOC_REG is non-null , use that as the register to put the HIGH value into if register allocation is already done .


<s> void aarch64_split_simd_move ( rtx dst , rtx src ) { machine_mode src_mode = GET_MODE ( src ) ; machine_mode dst_mode = GET_MODE ( dst ) ; gcc_assert ( VECTOR_MODE_P ( dst_mode ) ) ; if ( REG_P ( dst ) && REG_P ( src ) ) { gcc_assert ( VECTOR_MODE_P ( src_mode ) ) ; emit_insn ( gen_aarch64_split_simd_mov ( src_mode , dst , src ) ) ; } } </s>


<s> TargetPassConfig * P2TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new P2PassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> static rtx sh_trampoline_adjust_address ( rtx tramp ) { if ( TARGET_SHMEDIA ) tramp = expand_simple_binop ( Pmode , PLUS , tramp , const1_rtx , gen_reg_rtx ( Pmode ) , 0 , OPTAB_LIB_WIDEN ) ; return tramp ; } </s>

On SH5 , trampolines are SHmedia code , so add 1 to the address .


"\n%?=%d reload_completed=%d reload_in_progress=%d\n %r\n"

Test for extra memory constraint ' Q ' . It 's a memory address based on Y or Z pointer with valid displacement .


<s> static bool pdp11_secondary_memory_needed ( machine_mode , reg_class_t c1 , reg_class_t c2 ) { int fromfloat = ( c1 == LOAD_FPU_REGS || c1 == NO_LOAD_FPU_REGS || c1 == FPU_REGS ) ; int tofloat = ( c2 == LOAD_FPU_REGS || c2 == NO_LOAD_FPU_REGS || c2 == FPU_REGS ) ; return ( fromfloat != tofloat ) ; } </s>

Implement TARGET_SECONDARY_MEMORY_NEEDED . The answer is yes if we 're going between general register and FPU registers . The mode does n't matter in making this check .


<s> void visitCallInst ( CallInst & I ) { if ( ! I . getCalledFunction ( ) ) return ; StringRef Name = I . getCalledFunction ( ) -> getName ( ) ; if ( Name == "llvm.AMDGPU.tex" ) { ReplaceTexIntrinsic ( I , false , TexSign , "llvm.R600.tex" , "llvm.R600.texc" ) ; return ; } if ( Name == "llvm.AMDGPU.txl" ) { ReplaceTexIntrinsic ( I , true , TexSign , "llvm.R600.txl" , "llvm.R600.txlc" ) ; return ; } if ( Name == "llvm.AMDGPU.txb" ) { ReplaceTexIntrinsic ( I , true , TexSign , "llvm.R600.txb" , "llvm.R600.txbc" ) ; return ; } if ( Name == "llvm.AMDGPU.txf" ) { ReplaceTXF ( I ) ; return ; } if ( Name == "llvm.AMDGPU.txq" ) { ReplaceTexIntrinsic ( I , false , TexQSign , "llvm.R600.txq" , "llvm.R600.txq" ) ; return ; } if ( Name == "llvm.AMDGPU.ddx" ) { ReplaceTexIntrinsic ( I , false , TexSign , "llvm.R600.ddx" , "llvm.R600.ddx" ) ; return ; } if ( Name == "llvm.AMDGPU.ddy" ) { ReplaceTexIntrinsic ( I , false , TexSign , "llvm.R600.ddy" , "llvm.R600.ddy" ) ; return ; } } </s>


<s> bool runOnMachineFunction ( MachineFunction & F ) override { bool Changed = false ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) { Changed |= runOnMachineBasicBlock ( * FI ) ; FISCTextSectOffset += FI -> size ( ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s>
void
push
(
const
pseudo_node_t
&
back
)
{
if
(
dump_file
)
fprintf
(
dump_file
,
"Pushing backedge %d:%+d\n"
,
back
.
first
back
.
first
->
index
:
0
,
back
.
second
)
;
brackets
.
safe_push
(
bracket
(
back
)
)
;
}
</s>

Output RTL to push register RN onto the stack .


<s> unsigned SparcAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & GOp , unsigned Kind ) { SparcOperand & Op = ( SparcOperand & ) GOp ; if ( Op . isFloatOrDoubleReg ( ) ) { switch ( Kind ) { default : break ; case MCK_DFPRegs : if ( ! Op . isFloatReg ( ) || SparcOperand :: MorphToDoubleReg ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; case MCK_QFPRegs : if ( SparcOperand :: MorphToQuadReg ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; } } if ( Op . isIntReg ( ) && Kind == MCK_IntPair ) { if ( SparcOperand :: MorphToIntPairReg ( Op ) ) return MCTargetAsmParser :: Match_Success ; } if ( Op . isCoprocReg ( ) && Kind == MCK_CoprocPair ) { if ( SparcOperand :: MorphToCoprocPairReg ( Op ) ) return MCTargetAsmParser :: Match_Success ; } return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .

Sparc Sparc Sparc Sparc SparcOperand::MorphToDoubleReg SparcOperand::MorphToQuadReg SparcOperand::MorphToIntPairReg SparcOperand::MorphToCoprocPairReg


<s> static bool rs6000_parm_needs_stack ( cumulative_args_t args_so_far , tree type ) { int unsignedp ; rtx entry_parm ; if ( type == NULL || type == error_mark_node ) return true ; if ( TYPE_MODE ( type ) == VOIDmode ) return false ; if ( TREE_CODE ( type ) == COMPLEX_TYPE ) return ( rs6000_parm_needs_stack ( args_so_far , TREE_TYPE ( type ) ) || rs6000_parm_needs_stack ( args_so_far , TREE_TYPE ( type ) ) ) ; if ( ( TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == RECORD_TYPE ) && TYPE_TRANSPARENT_AGGR ( type ) ) type = TREE_TYPE ( first_field ( type ) ) ; function_arg_info arg ( type , true ) ; apply_pass_by_reference_rules ( get_cumulative_args ( args_so_far ) , arg ) ; unsignedp = TYPE_UNSIGNED ( type ) ; arg . mode = promote_mode ( arg . type , arg . mode , & unsignedp ) ; if ( rs6000_must_pass_in_stack ( arg ) ) return true ; entry_parm = rs6000_function_arg ( args_so_far , arg ) ; if ( entry_parm == NULL ) return true ; if ( GET_CODE ( entry_parm ) == PARALLEL && XEXP ( XVECEXP ( entry_parm , 0 , 0 ) , 0 ) == NULL_RTX ) return true ; if ( rs6000_arg_partial_bytes ( args_so_far , arg ) != 0 ) return true ; rs6000_function_arg_advance ( args_so_far , arg ) ; return false ; } </s>

Process parameter of type TYPE after ARGS_SO_FAR parameters were already processes . Return true if the parameter must be passed ( fully or partially ) on the stack .


<s> bool ARMFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; bool isVarArg = AFI -> getArgRegsSaveSize ( ) > 0 ; unsigned NumAlignedDPRCS2Regs = AFI -> getNumAlignedDPRCS2Regs ( ) ; if ( NumAlignedDPRCS2Regs ) emitAlignedDPRCS2Restores ( MBB , MI , NumAlignedDPRCS2Regs , CSI , TRI ) ; unsigned PopOpc = AFI -> isThumbFunction ( ) ? ARM :: t2LDMIA_UPD : ARM :: LDMIA_UPD ; unsigned LdrOpc = AFI -> isThumbFunction ( ) ? ARM :: t2LDR_POST : ARM :: LDR_POST_IMM ; unsigned FltOpc = ARM :: VLDMDIA_UPD ; emitPopInst ( MBB , MI , CSI , FltOpc , 0 , isVarArg , true , & isARMArea3Register , NumAlignedDPRCS2Regs ) ; emitPopInst ( MBB , MI , CSI , PopOpc , LdrOpc , isVarArg , false , & isARMArea2Register , 0 ) ; emitPopInst ( MBB , MI , CSI , PopOpc , LdrOpc , isVarArg , false , & isARMArea1Register , 0 ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


"PPC pre-emit peephole: erasing instruction: "


<s> bool AMDGPUPassConfig :: addInstSelector ( ) { addPass ( createAMDGPUISelDag ( getAMDGPUTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static rtx s390_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return s390_function_and_libcall_value ( mode , NULL_TREE , NULL_TREE , true ) ; } </s>

Define where to return a scalar libcall return value of mode MODE .


<s> BitVector Nios2RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( 1 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


"No ISEL instructions in this function\n"


<s> int reg_or_0_operand ( rtx op , enum machine_mode mode ) { switch ( GET_CODE ( op ) ) { case CONST_INT : return INTVAL ( op ) == 0 ; case REG : case SUBREG : return register_operand ( op , mode ) ; default : break ; } return 0 ; } </s>

Return true if OP is either a register or 0


<s> static enum attr_op_type sched_address_type ( machine_mode mode , rtx addr_rtx ) { struct m68k_address address ; if ( symbolic_operand ( addr_rtx , VOIDmode ) ) return OP_TYPE_MEM7 ; if ( ! m68k_decompose_address ( mode , addr_rtx , reload_completed , & address ) ) { gcc_assert ( ! reload_completed ) ; return OP_TYPE_MEM234 ; } if ( address . scale != 0 ) return OP_TYPE_MEM6 ; if ( address . base != NULL_RTX ) { if ( address . offset == NULL_RTX ) return OP_TYPE_MEM234 ; return OP_TYPE_MEM5 ; } gcc_assert ( address . offset != NULL_RTX ) ; return OP_TYPE_MEM7 ; } </s>

Return type of memory ADDR_RTX refers to .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addRequiredID ( LoopSimplifyID ) ; AU . addRequiredID ( LCSSAID ) ; AU . addRequired < AAResultsWrapperPass > ( ) ; AU . addPreserved < AAResultsWrapperPass > ( ) ; AU . addRequired < ScalarEvolutionWrapperPass > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addRequired < TargetLibraryInfoWrapperPass > ( ) ; AU . addPreserved < TargetLibraryInfoWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static int supersparc_adjust_cost ( rtx insn , rtx link , rtx dep_insn , int cost ) { enum attr_type insn_type ; if ( ! recog_memoized ( insn ) ) return 0 ; insn_type = get_attr_type ( insn ) ; if ( REG_NOTE_KIND ( link ) == 0 ) { if ( insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD ) return cost + 3 ; if ( insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE ) { rtx pat = PATTERN ( insn ) ; rtx dep_pat = PATTERN ( dep_insn ) ; if ( GET_CODE ( pat ) != SET || GET_CODE ( dep_pat ) != SET ) return cost ; if ( rtx_equal_p ( SET_DEST ( dep_pat ) , SET_SRC ( pat ) ) ) return cost ; return cost + 3 ; } if ( insn_type == TYPE_SHIFT ) return cost + 3 ; } else { if ( insn_type == TYPE_IALU || insn_type == TYPE_SHIFT ) return 0 ; } return cost ; } </s>

Adjust the cost of a scheduling dependency . Return the new cost of a dependency LINK or INSN on DEP_INSN . COST is the current cost .


<s> const MCExpr * X86_64MachoTargetObjectFile :: getIndirectSymViaGOTPCRel ( const GlobalValue * GV , const MCSymbol * Sym , const MCValue & MV , int64_t Offset , MachineModuleInfo * MMI , MCStreamer & Streamer ) const { unsigned FinalOff = Offset + MV . getConstant ( ) + 4 ; const MCExpr * Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_GOTPCREL , getContext ( ) ) ; const MCExpr * Off = MCConstantExpr :: create ( FinalOff , getContext ( ) ) ; return MCBinaryExpr :: createAdd ( Res , Off , getContext ( ) ) ; } </s>

Get the target specific PC relative GOT entry relocation .


<s> void HexagonTargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { if ( isHvxOperation ( N , DAG ) ) { ReplaceHvxNodeResults ( N , Results , DAG ) ; if ( ! Results . empty ( ) ) return ; } const SDLoc & dl ( N ) ; switch ( N -> getOpcode ( ) ) { case ISD :: SRL : case ISD :: SRA : case ISD :: SHL : return ; case ISD :: BITCAST : if ( N -> getValueType ( 0 ) == MVT :: i8 ) { if ( N -> getOperand ( 0 ) . getValueType ( ) == MVT :: v8i1 ) { SDValue P = getInstr ( Hexagon :: C2_tfrpr , dl , MVT :: i32 , N -> getOperand ( 0 ) , DAG ) ; SDValue T = DAG . getAnyExtOrTrunc ( P , dl , MVT :: i8 ) ; Results . push_back ( T ) ; } } break ; } } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s>
SDValue
BlackfinTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
SmallVector
<
CCValAssign
,
16
>
ArgLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
ArgLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AllocateStack
(
12
,
4
)
;
CCInfo
.
AnalyzeFormalArguments
(
Ins
,
CC_Blackfin
)
;
for
(
unsigned
i
=
0
,
e
=
ArgLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
ArgLocs
[
i
]
;
if
(
VA
.
isRegLoc
(
)
)
{
EVT
RegVT
=
VA
.
getLocVT
(
)
;
TargetRegisterClass
*
RC
=
VA
.
getLocReg
(
)
==
BF
::
P0
BF
::
PRegisterClass
:
BF
::
DRegisterClass
;
assert
(
RC
->
contains
(
VA
.
getLocReg
(
)
)
&&
"Unexpected regclass in CCState"
)
;
assert
(
RC
->
hasType
(
RegVT
)
&&
"Unexpected regclass in CCState"
)
;
unsigned
Reg
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
RC
)
;
MF
.
getRegInfo
(
)
.
addLiveIn
(
VA
.
getLocReg
(
)
,
Reg
)
;
SDValue
ArgValue
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
Reg
,
RegVT
)
;
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
SExt
)
ArgValue
=
DAG
.
getNode
(
ISD
::
AssertSext
,
dl
,
RegVT
,
ArgValue
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
else
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExt
)
ArgValue
=
DAG
.
getNode
(
ISD
::
AssertZext
,
dl
,
RegVT
,
ArgValue
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
if
(
VA
.
getLocInfo
(
)
!=
CCValAssign
::
Full
)
ArgValue
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
ArgValue
)
;
InVals
.
push_back
(
ArgValue
)
;
}
else
{
assert
(
VA
.
isMemLoc
(
)
&&
"CCValAssign must be RegLoc or MemLoc"
)
;
unsigned
ObjSize
=
VA
.
getLocVT
(
)
.
getStoreSize
(
)
;
int
FI
=
MFI
->
CreateFixedObject
(
ObjSize
,
VA
.
getLocMemOffset
(
)
,
true
)
;
SDValue
FIN
=
DAG
.
getFrameIndex
(
FI
,
MVT
::
i32
)
;
InVals
.
push_back
(
DAG
.
getLoad
(
VA
.
getValVT
(
)
,
dl
,
Chain
,
FIN
,
MachinePointerInfo
(
)
,
false
,
false
,
0
)
)
;
}
}
return
Chain
;
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> static bool bfin_function_ok_for_sibcall ( tree decl ATTRIBUTE_UNUSED , tree exp ATTRIBUTE_UNUSED ) { cgraph_node * this_func , * called_func ; e_funkind fkind = funkind ( TREE_TYPE ( current_function_decl ) ) ; if ( fkind != SUBROUTINE ) return false ; if ( ! TARGET_ID_SHARED_LIBRARY || TARGET_SEP_DATA ) return true ; if ( ! decl ) return false ; this_func = cgraph_node :: local_info_node ( current_function_decl ) ; called_func = cgraph_node :: local_info_node ( decl ) ; if ( ! called_func ) return false ; return ! called_func -> local || this_func -> local ; } </s>

Decide whether we can make a sibling call to a function . DECL is the declaration of the function being targeted by the call and EXP is the CALL_EXPR representing the call .


"MIa must load from or modify a memory location"

"MIb must load from or modify a memory location"

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> static rtx push ( int rn ) { rtx reg = gen_rtx_REG ( word_mode , rn ) ; rtx x ; if ( ! TARGET_NORMAL_MODE ) x = gen_push_h8300hs_advanced ( reg ) ; else x = gen_push_h8300hs_normal ( reg ) ; x = F ( emit_insn ( x ) , 0 ) ; add_reg_note ( x , REG_INC , stack_pointer_rtx ) ; return x ; } </s>


<s> static rtx sparc_function_value_1 ( const_tree type , machine_mode mode , bool outgoing ) { int regbase = ( outgoing ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST ) ; enum mode_class mclass = GET_MODE_CLASS ( mode ) ; int regno ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( ( TARGET_ARCH32 && size <= 8 ) || ( TARGET_ARCH64 && size <= 32 ) ) ; if ( mode == BLKmode ) return function_arg_vector_value ( size , SPARC_FP_ARG_FIRST ) ; mclass = MODE_FLOAT ; } if ( TARGET_ARCH64 && type ) { if ( TREE_CODE ( type ) == RECORD_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 32 ) ; return function_arg_record_value ( type , mode , 0 , 1 , regbase ) ; } else if ( TREE_CODE ( type ) == UNION_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 32 ) ; return function_arg_union_value ( size , mode , 0 , regbase ) ; } else if ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) ; else if ( AGGREGATE_TYPE_P ( type ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 32 ) ; mode = mode_for_size ( size * BITS_PER_UNIT , MODE_INT , 0 ) ; if ( mode == BLKmode ) return function_arg_union_value ( size , mode , 0 , regbase ) ; else mclass = MODE_INT ; } else if ( mclass == MODE_INT && GET_MODE_SIZE ( mode ) < UNITS_PER_WORD ) mode = word_mode ; } else if ( TARGET_ARCH32 && ! ( type && AGGREGATE_TYPE_P ( type ) ) && mclass == MODE_INT && GET_MODE_SIZE ( mode ) < UNITS_PER_WORD ) mode = word_mode ; if ( ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) && TARGET_FPU ) regno = SPARC_FP_ARG_FIRST ; else regno = regbase ; return gen_rtx_REG ( mode , regno ) ; } </s>

Handle TARGET_FUNCTION_VALUE , and TARGET_LIBCALL_VALUE target hook . For v9 , function return values are subject to the same rules as arguments , except that up to 32 bytes may be returned in registers .


"WebAssembly should not have callee-saved registers"

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool SILowerControlFlow :: runOnMachineFunction ( MachineFunction & MF ) { const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; LIS = getAnalysisIfAvailable < LiveIntervals > ( ) ; MachineFunction :: iterator NextBB ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; BI = NextBB ) { NextBB = std :: next ( BI ) ; MachineBasicBlock & MBB = * BI ; MachineBasicBlock :: iterator I , Next ; for ( I = MBB . begin ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; switch ( MI . getOpcode ( ) ) { case AMDGPU :: SI_IF : emitIf ( MI ) ; break ; case AMDGPU :: SI_ELSE : emitElse ( MI ) ; break ; case AMDGPU :: SI_BREAK : emitBreak ( MI ) ; break ; case AMDGPU :: SI_IF_BREAK : emitIfBreak ( MI ) ; break ; case AMDGPU :: SI_ELSE_BREAK : emitElseBreak ( MI ) ; break ; case AMDGPU :: SI_LOOP : emitLoop ( MI ) ; break ; case AMDGPU :: SI_END_CF : emitEndCf ( MI ) ; break ; default : break ; } } } return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> void ARMBaseRegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , unsigned PredReg ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: LDRcp ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addReg ( 0 ) . addImm ( 0 ) . addImm ( Pred ) . addReg ( PredReg ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s> static void do_add3 ( rtx dest , rtx src1 , rtx src2 ) { if ( GET_MODE ( dest ) == DImode ) emit_insn ( gen_adddi3 ( dest , src1 , src2 ) ) ; else emit_insn ( gen_addsi3 ( dest , src1 , src2 ) ) ; } </s>

Emit an add of the proper mode for DEST . DEST is the destination register for the add . SRC1 is the first add input . SRC2 is the second add input . Computes DEST = SRC1+SRC2 .


<s>
void
WebAssemblyTargetAsmStreamer
::
emitFunctionType
(
const
MCSymbolWasm
*
Sym
)
{
assert
(
Sym
->
isFunction
(
)
)
;
OS
<<
"\t.functype\t"
<<
Sym
->
getName
(
)
<<
" "
;
OS
<<
WebAssembly
::
signatureToString
(
Sym
->
getSignature
(
)
)
;
OS
<<
"\n"
;
}
</s>

WebAssembly
WebAssembly
"\t.functype\t"
" "
WebAssembly::signatureToString
"\n"


<s> void AArch64PassConfig :: addPreRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAdvSIMDScalar ) { addPass ( createAArch64AdvSIMDScalar ( ) ) ; addPass ( & PeepholeOptimizerID ) ; } } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> virtual const AMDGPUSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool AArch64TargetLowering :: hasPairedLoad ( EVT LoadedType , unsigned & RequiredAligment ) const { if ( ! LoadedType . isSimple ( ) || ( ! LoadedType . isInteger ( ) && ! LoadedType . isFloatingPoint ( ) ) ) return false ; RequiredAligment = 0 ; unsigned NumBits = LoadedType . getSizeInBits ( ) ; return NumBits == 32 || NumBits == 64 ; } </s>

Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory .


<s> bool MINA32AsmParser :: ParseDirective ( AsmToken DirectiveID ) { MCAsmParser & Parser = getParser ( ) ; if ( DirectiveID . getString ( ) == ".ent" ) { Parser . Lex ( ) ; return false ; } if ( DirectiveID . getString ( ) == ".end" ) { Parser . Lex ( ) ; return false ; } if ( DirectiveID . getString ( ) == ".frame" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( DirectiveID . getString ( ) == ".set" ) { return parseDirectiveSet ( ) ; } if ( DirectiveID . getString ( ) == ".fmask" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( DirectiveID . getString ( ) == ".mask" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( DirectiveID . getString ( ) == ".gpword" ) { Parser . eatToEndOfStatement ( ) ; return false ; } return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , CPU , FS ) , ReserveXRegister ( AArch64 :: GPR64commonRegClass . getNumRegs ( ) ) , CustomCallSavedXRegs ( AArch64 :: GPR64commonRegClass . getNumRegs ( ) ) , IsLittle ( LittleEndian ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS , CPU ) ) , TSInfo ( ) , TLInfo ( TM , * this ) { if ( AArch64 :: isX18ReservedByDefault ( TT ) ) ReserveXRegister . set ( 18 ) ; CallLoweringInfo . reset ( new AArch64CallLowering ( * getTargetLowering ( ) ) ) ; InlineAsmLoweringInfo . reset ( new InlineAsmLowering ( getTargetLowering ( ) ) ) ; Legalizer . reset ( new AArch64LegalizerInfo ( * this ) ) ; auto * RBI = new AArch64RegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( createAArch64InstructionSelector ( * static_cast < const AArch64TargetMachine * > ( & TM ) , * this , * RBI ) ) ; RegBankInfo . reset ( RBI ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


"the destination register can't equal the base register in an "

"instruction that modifies the base register."

ParseInstruction - Parse one assembly instruction .


<s> static bool arm_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { machine_mode mode ; if ( size == UNITS_PER_WORD && aligned_p ) { fputs ( "\t.word\t" , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; if ( NEED_GOT_RELOC && flag_pic && making_const_table && ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF ) ) { if ( ! arm_pic_data_is_text_relative || ( GET_CODE ( x ) == SYMBOL_REF && ( ! SYMBOL_REF_LOCAL_P ( x ) || ( SYMBOL_REF_DECL ( x ) ? DECL_WEAK ( SYMBOL_REF_DECL ( x ) ) : 0 ) ) ) ) fputs ( "(GOT)" , asm_out_file ) ; else fputs ( "(GOTOFF)" , asm_out_file ) ; } fputc ( '\n' , asm_out_file ) ; return true ; } mode = GET_MODE ( x ) ; if ( arm_vector_mode_supported_p ( mode ) ) { int i , units ; gcc_assert ( GET_CODE ( x ) == CONST_VECTOR ) ; units = CONST_VECTOR_NUNITS ( x ) ; size = GET_MODE_UNIT_SIZE ( mode ) ; if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) for ( i = 0 ; i < units ; i ++ ) { rtx elt = CONST_VECTOR_ELT ( x , i ) ; assemble_integer ( elt , size , i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT , 1 ) ; } else for ( i = 0 ; i < units ; i ++ ) { rtx elt = CONST_VECTOR_ELT ( x , i ) ; assemble_real ( * CONST_DOUBLE_REAL_VALUE ( elt ) , GET_MODE_INNER ( mode ) , i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT ) ; } return true ; } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . The ARM version needs to handle word-sized values specially .


<s>
CCAssignFn
*
ARMFastISel
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
Return
,
bool
isVarArg
)
{
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
if
(
Subtarget
->
hasVFP2
(
)
&&
!
isVarArg
)
{
if
(
!
Subtarget
->
isAAPCS_ABI
(
)
)
return
(
Return
RetFastCC_ARM_APCS
:
FastCC_ARM_APCS
)
;
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
}
LLVM_FALLTHROUGH
;
case
CallingConv
::
C
:
case
CallingConv
::
CXX_FAST_TLS
:
if
(
Subtarget
->
isAAPCS_ABI
(
)
)
{
if
(
Subtarget
->
hasVFP2
(
)
&&
TM
.
Options
.
FloatABIType
==
FloatABI
::
Hard
&&
!
isVarArg
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
else
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
}
else
{
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
}
case
CallingConv
::
ARM_AAPCS_VFP
:
case
CallingConv
::
Swift
:
if
(
!
isVarArg
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
LLVM_FALLTHROUGH
;
case
CallingConv
::
ARM_AAPCS
:
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
case
CallingConv
::
ARM_APCS
:
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
case
CallingConv
::
GHC
:
if
(
Return
)
llvm_unreachable
(
"Can't return in GHC call convention"
)
;
else
return
CC_ARM_APCS_GHC
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .

ARM
ARM
"Unsupported calling convention"
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
"Can't return in GHC call convention"
ARM


<s> bool NVPTXAsmPrinter :: doFinalization ( Module & M ) { if ( ! GlobalsEmitted ) { emitGlobals ( M ) ; GlobalsEmitted = true ; } Module :: GlobalListType & global_list = M . getGlobalList ( ) ; int i , n = global_list . size ( ) ; GlobalVariable * * gv_array = new GlobalVariable * [ n ] ; i = 0 ; for ( Module :: global_iterator I = global_list . begin ( ) , E = global_list . end ( ) ; I != E ; ++ I ) gv_array [ i ++ ] = & * I ; while ( ! global_list . empty ( ) ) global_list . remove ( global_list . begin ( ) ) ; bool ret = AsmPrinter :: doFinalization ( M ) ; for ( i = 0 ; i < n ; i ++ ) global_list . insert ( global_list . end ( ) , gv_array [ i ] ) ; clearAnnotationCache ( & M ) ; delete [ ] gv_array ; return ret ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s>
void
HexagonCommonGEP
::
collect
(
)
{
ValueVect
BO
;
getBlockTraversalOrder
(
&
Fn
->
front
(
)
,
BO
)
;
ValueToNodeMap
NM
;
for
(
ValueVect
::
iterator
I
=
BO
.
begin
(
)
,
E
=
BO
.
end
(
)
;
I
!=
E
;
++
I
)
{
BasicBlock
*
B
=
cast
<
BasicBlock
>
(
*
I
)
;
for
(
BasicBlock
::
iterator
J
=
B
->
begin
(
)
,
F
=
B
->
end
(
)
;
J
!=
F
;
++
J
)
{
if
(
!
isa
<
GetElementPtrInst
>
(
J
)
)
continue
;
GetElementPtrInst
*
GepI
=
cast
<
GetElementPtrInst
>
(
J
)
;
if
(
isHandledGepForm
(
GepI
)
)
processGepInst
(
GepI
,
NM
)
;
}
}
DEBUG
(
dbgs
(
)
<<
"Gep nodes after initial collection:\n"
<<
Nodes
)
;
}
</s>

Analyze the given instruction MI and fill in the Uses , Defs and DeadDefs list based on the MachineOperand flags .

Hexagon
Hexagon
"Gep nodes after initial collection:\n"


<s> bool OR1KAsmPrinter :: isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { const MachineBasicBlock * Pred = * MBB -> pred_begin ( ) ; if ( const BasicBlock * bb = Pred -> getBasicBlock ( ) ) if ( isa < SwitchInst > ( bb -> getTerminator ( ) ) ) return false ; if ( ! AsmPrinter :: isBlockOnlyReachableByFallthrough ( MBB ) ) return false ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> isTerminator ( ) ) ; return ! I -> isBarrier ( ) ; } </s>

isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


<s> const TargetRegisterInfo * getRegisterInfo ( ) const override { return getSubtargetImpl ( ) -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> BitVector SparcRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( SP :: G1 ) ; if ( ReserveAppRegisters ) { Reserved . set ( SP :: G2 ) ; Reserved . set ( SP :: G3 ) ; Reserved . set ( SP :: G4 ) ; } if ( ! Subtarget . is64Bit ( ) ) Reserved . set ( SP :: G5 ) ; Reserved . set ( SP :: O6 ) ; Reserved . set ( SP :: I6 ) ; Reserved . set ( SP :: I7 ) ; Reserved . set ( SP :: G0 ) ; Reserved . set ( SP :: G6 ) ; Reserved . set ( SP :: G7 ) ; if ( ! Subtarget . isV9 ( ) ) { for ( unsigned n = 0 ; n != 16 ; ++ n ) { for ( MCRegAliasIterator AI ( SP :: D16 + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; } } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
bool
AVRFrameLowering
::
spillCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
ArrayRef
<
CalleeSavedInfo
>
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
if
(
CSI
.
empty
(
)
)
{
return
false
;
}
unsigned
CalleeFrameSize
=
0
;
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
AVRSubtarget
&
STI
=
MF
.
getSubtarget
<
AVRSubtarget
>
(
)
;
const
TargetInstrInfo
&
TII
=
*
STI
.
getInstrInfo
(
)
;
AVRMachineFunctionInfo
*
AVRFI
=
MF
.
getInfo
<
AVRMachineFunctionInfo
>
(
)
;
for
(
const
CalleeSavedInfo
&
I
:
llvm
::
reverse
(
CSI
)
)
{
Register
Reg
=
I
.
getReg
(
)
;
bool
IsNotLiveIn
=
!
MBB
.
isLiveIn
(
Reg
)
;
assert
(
TRI
->
getRegSizeInBits
(
*
TRI
->
getMinimalPhysRegClass
(
Reg
)
)
==
8
&&
"Invalid register size"
)
;
if
(
IsNotLiveIn
)
{
MBB
.
addLiveIn
(
Reg
)
;
}
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
PUSHRr
)
)
.
addReg
(
Reg
,
getKillRegState
(
IsNotLiveIn
)
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
++
CalleeFrameSize
;
}
AVRFI
->
setCalleeSavedFrameSize
(
CalleeFrameSize
)
;
return
true
;
}
</s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .

AVR
AVR
0
AVR
AVR
AVR
AVR
AVR
8
"Invalid register size"
AVR::PUSHRr
AVR


<s> static void v850_insert_attributes ( tree decl , tree * attr_ptr ATTRIBUTE_UNUSED ) { if ( data_area_stack && data_area_stack -> data_area && current_function_decl == NULL_TREE && ( TREE_CODE ( decl ) == VAR_DECL || TREE_CODE ( decl ) == CONST_DECL ) && v850_get_data_area ( decl ) == DATA_AREA_NORMAL ) v850_set_data_area ( decl , data_area_stack -> data_area ) ; if ( GHS_default_section_names [ ( int ) GHS_SECTION_KIND_SDATA ] == NULL ) { GHS_default_section_names [ ( int ) GHS_SECTION_KIND_SDATA ] = ".sdata" ; GHS_default_section_names [ ( int ) GHS_SECTION_KIND_ROSDATA ] = ".rosdata" ; GHS_default_section_names [ ( int ) GHS_SECTION_KIND_TDATA ] = ".tdata" ; GHS_default_section_names [ ( int ) GHS_SECTION_KIND_ZDATA ] = ".zdata" ; GHS_default_section_names [ ( int ) GHS_SECTION_KIND_ROZDATA ] = ".rozdata" ; } if ( current_function_decl == NULL_TREE && ( TREE_CODE ( decl ) == VAR_DECL || TREE_CODE ( decl ) == CONST_DECL || TREE_CODE ( decl ) == FUNCTION_DECL ) && ( ! DECL_EXTERNAL ( decl ) || DECL_INITIAL ( decl ) ) && ! DECL_SECTION_NAME ( decl ) ) { enum GHS_section_kind kind = GHS_SECTION_KIND_DEFAULT ; const char * chosen_section ; if ( TREE_CODE ( decl ) == FUNCTION_DECL ) kind = GHS_SECTION_KIND_TEXT ; else { switch ( v850_get_data_area ( decl ) ) { default : gcc_unreachable ( ) ; case DATA_AREA_SDA : kind = ( ( TREE_READONLY ( decl ) ) ? GHS_SECTION_KIND_ROSDATA : GHS_SECTION_KIND_SDATA ) ; break ; case DATA_AREA_TDA : kind = GHS_SECTION_KIND_TDATA ; break ; case DATA_AREA_ZDA : kind = ( ( TREE_READONLY ( decl ) ) ? GHS_SECTION_KIND_ROZDATA : GHS_SECTION_KIND_ZDATA ) ; break ; case DATA_AREA_NORMAL : if ( TREE_READONLY ( decl ) ) kind = GHS_SECTION_KIND_RODATA ; else if ( DECL_INITIAL ( decl ) ) kind = GHS_SECTION_KIND_DATA ; else kind = GHS_SECTION_KIND_BSS ; } } chosen_section = GHS_current_section_names [ ( int ) kind ] ; if ( chosen_section == NULL ) chosen_section = GHS_default_section_names [ ( int ) kind ] ; if ( chosen_section ) { set_decl_section_name ( decl , chosen_section ) ; } } } </s>

Add data area to the given declaration if a ghs data area pragma is currently in effect ( # pragma ghs startXXX/endXXX ) .


<s> static bool expand_perm_with_rot ( const struct expand_vec_perm_d & d ) { if ( d . nelt != 4 ) return false ; if ( d . op0 == d . op1 && is_reverse_perm_mask ( d ) ) { if ( d . testing_p ) return true ; rtx tmp = gen_reg_rtx ( d . vmode ) ; rtx op0_reg = force_reg ( GET_MODE ( d . op0 ) , d . op0 ) ; emit_insn ( gen_vpdi4_2 ( d . vmode , tmp , op0_reg , op0_reg ) ) ; if ( d . vmode == V4SImode ) emit_insn ( gen_rotlv4si3_di ( d . target , tmp ) ) ; else if ( d . vmode == V4SFmode ) emit_insn ( gen_rotlv4sf3_di ( d . target , tmp ) ) ; return true ; } return false ; } </s>

The case of reversing a four-element vector [ 0 , 1 , 2 , 3 ] can be handled by first permuting the doublewords [ 2 , 3 , 0 , 1 ] and subsequently rotating them by 32 bits .


<s>
void
AMDGPUAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
)
const
{
Value
=
adjustFixupValue
(
Fixup
,
Value
,
&
Asm
.
getContext
(
)
)
;
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
uint32_t
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
Data
[
Offset
+
i
]
|=
static_cast
<
uint8_t
>
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static std :: unique_ptr < SparcOperand > CreateReg ( unsigned RegNum , unsigned Kind , SMLoc S , SMLoc E ) { auto Op = std :: make_unique < SparcOperand > ( k_Register ) ; Op -> Reg . RegNum = RegNum ; Op -> Reg . Kind = ( SparcOperand :: RegisterKind ) Kind ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .

Sparc Sparc Sparc SparcOperand::RegisterKind


<s> static bool loongarch_valid_offset_p ( rtx x , machine_mode mode ) { if ( ! ( const_arith_operand ( x , Pmode ) || ( ( mode == E_SImode || mode == E_DImode ) && const_imm16_operand ( x , Pmode ) && ( loongarch_signed_immediate_p ( INTVAL ( x ) , 14 , 2 ) ) ) ) ) return false ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && ! IMM12_OPERAND ( INTVAL ( x ) + GET_MODE_SIZE ( mode ) - UNITS_PER_WORD ) ) return false ; return true ; } </s>

Return true if , for every base register BASE_REG , ( plus BASE_REG X ) can address a value of mode MODE .


<s> static void nvptx_reorg_subreg ( void ) { struct reg_replace qiregs , hiregs , siregs , diregs ; rtx_insn * insn , * next ; qiregs . n_allocated = 0 ; hiregs . n_allocated = 0 ; siregs . n_allocated = 0 ; diregs . n_allocated = 0 ; qiregs . mode = QImode ; hiregs . mode = HImode ; siregs . mode = SImode ; diregs . mode = DImode ; for ( insn = get_insns ( ) ; insn ; insn = next ) { next = NEXT_INSN ( insn ) ; if ( ! NONDEBUG_INSN_P ( insn ) || asm_noperands ( PATTERN ( insn ) ) >= 0 || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) continue ; qiregs . n_in_use = 0 ; hiregs . n_in_use = 0 ; siregs . n_in_use = 0 ; diregs . n_in_use = 0 ; extract_insn ( insn ) ; enum attr_subregs_ok s_ok = get_attr_subregs_ok ( insn ) ; for ( int i = 0 ; i < recog_data . n_operands ; i ++ ) { rtx op = recog_data . operand [ i ] ; if ( GET_CODE ( op ) != SUBREG ) continue ; rtx inner = SUBREG_REG ( op ) ; machine_mode outer_mode = GET_MODE ( op ) ; machine_mode inner_mode = GET_MODE ( inner ) ; gcc_assert ( s_ok ) ; if ( s_ok && ( GET_MODE_PRECISION ( inner_mode ) >= GET_MODE_PRECISION ( outer_mode ) ) ) continue ; gcc_assert ( SCALAR_INT_MODE_P ( outer_mode ) ) ; struct reg_replace * r = ( outer_mode == QImode ? & qiregs : outer_mode == HImode ? & hiregs : outer_mode == SImode ? & siregs : & diregs ) ; rtx new_reg = get_replacement ( r ) ; if ( recog_data . operand_type [ i ] != OP_OUT ) { enum rtx_code code ; if ( GET_MODE_PRECISION ( inner_mode ) < GET_MODE_PRECISION ( outer_mode ) ) code = ZERO_EXTEND ; else code = TRUNCATE ; rtx pat = gen_rtx_SET ( new_reg , gen_rtx_fmt_e ( code , outer_mode , inner ) ) ; emit_insn_before ( pat , insn ) ; } if ( recog_data . operand_type [ i ] != OP_IN ) { enum rtx_code code ; if ( GET_MODE_PRECISION ( inner_mode ) < GET_MODE_PRECISION ( outer_mode ) ) code = TRUNCATE ; else code = ZERO_EXTEND ; rtx pat = gen_rtx_SET ( inner , gen_rtx_fmt_e ( code , inner_mode , new_reg ) ) ; emit_insn_after ( pat , insn ) ; } validate_change ( insn , recog_data . operand_loc [ i ] , new_reg , false ) ; } } } </s>

Clean up subreg operands . In ptx assembly , everything is typed , and the presence of subregs would break the rules for most instructions . Replace them with a suitable new register of the right size , plus conversion copyin/copyout instructions .


<s> void ix86_emit_i387_asinh ( rtx op0 , rtx op1 ) { rtx e1 = gen_reg_rtx ( XFmode ) ; rtx e2 = gen_reg_rtx ( XFmode ) ; rtx scratch = gen_reg_rtx ( HImode ) ; rtx flags = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; rtx cst1 , tmp ; rtx_code_label * jump_label = gen_label_rtx ( ) ; rtx_insn * insn ; emit_insn ( gen_mulxf3 ( e1 , op1 , op1 ) ) ; cst1 = force_reg ( XFmode , CONST1_RTX ( XFmode ) ) ; emit_insn ( gen_addxf3 ( e2 , e1 , cst1 ) ) ; emit_insn ( gen_sqrtxf2 ( e2 , e2 ) ) ; emit_insn ( gen_addxf3 ( e2 , e2 , cst1 ) ) ; emit_insn ( gen_divxf3 ( e1 , e1 , e2 ) ) ; emit_insn ( gen_fxamxf2_i387 ( scratch , op1 ) ) ; emit_insn ( gen_absxf2 ( e2 , op1 ) ) ; emit_insn ( gen_addxf3 ( e1 , e1 , e2 ) ) ; ix86_emit_i387_log1p ( e2 , e1 ) ; emit_insn ( gen_testqi_ext_1_ccno ( scratch , GEN_INT ( 0x02 ) ) ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_EQ ( VOIDmode , flags , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , jump_label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; predict_jump ( REG_BR_PROB_BASE * 50 / 100 ) ; JUMP_LABEL ( insn ) = jump_label ; emit_insn ( gen_negxf2 ( e2 , e2 ) ) ; emit_label ( jump_label ) ; LABEL_NUSES ( jump_label ) = 1 ; emit_move_insn ( op0 , e2 ) ; } </s>

Output code to perform an asinh XFmode calculation .


<s> unsigned MOSTargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT , const ISD :: ArgFlagsTy & Flags ) const { if ( Flags . isPointer ( ) ) return 1 ; return TargetLowering :: getNumRegistersForCallingConv ( Context , CC , VT , Flags ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s> void SPIRVPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; addPass ( createSPIRVLowerConstExprLegacyPass ( ) ) ; addPass ( createSPIRVOCLRegularizerPass ( ) ) ; addPass ( createSPIRVPreTranslationLegalizerPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> bool MipsFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool AAPTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_AAP ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> static int rs6000_emit_p9_fp_cmove ( rtx dest , rtx op , rtx true_cond , rtx false_cond ) { enum rtx_code code = GET_CODE ( op ) ; rtx op0 = XEXP ( op , 0 ) ; rtx op1 = XEXP ( op , 1 ) ; machine_mode result_mode = GET_MODE ( dest ) ; rtx compare_rtx ; rtx cmove_rtx ; rtx clobber_rtx ; if ( ! can_create_pseudo_p ( ) ) return 0 ; switch ( code ) { case EQ : case GE : case GT : break ; case NE : case LT : case LE : code = swap_condition ( code ) ; std :: swap ( op0 , op1 ) ; break ; default : return 0 ; } compare_rtx = gen_rtx_fmt_ee ( code , CCFPmode , op0 , op1 ) ; cmove_rtx = gen_rtx_SET ( dest , gen_rtx_IF_THEN_ELSE ( result_mode , compare_rtx , true_cond , false_cond ) ) ; clobber_rtx = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_SCRATCH ( V2DImode ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , cmove_rtx , clobber_rtx ) ) ) ; return 1 ; } </s>

ISA 3.0 ( power9 ) conditional move subcase to emit XSCMP { EQ , GE , GT , NE } DP and XXSEL instructions for SF/DF scalars . Move TRUE_COND to DEST if OP of the operands of the last comparison is nonzero/true , FALSE_COND if it is zero/false . Return 0 if the hardware has no such operation .


<s> void MipsMCInstLower :: Initialize ( Mangler * M , MCContext * C ) { Mang = M ; Ctx = C ; } </s>

This method must be called before any actual lowering is done .


<s> static bool s390_function_arg_integer ( enum machine_mode mode , tree type ) { int size = s390_function_arg_size ( mode , type ) ; if ( size > 8 ) return false ; if ( ! type ) return GET_MODE_CLASS ( mode ) == MODE_INT || ( TARGET_SOFT_FLOAT && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) ; if ( INTEGRAL_TYPE_P ( type ) || POINTER_TYPE_P ( type ) || TREE_CODE ( type ) == OFFSET_TYPE || ( TARGET_SOFT_FLOAT && TREE_CODE ( type ) == REAL_TYPE ) ) return true ; if ( AGGREGATE_TYPE_P ( type ) && exact_log2 ( size ) >= 0 && ! s390_function_arg_float ( mode , type ) ) return true ; return false ; } </s>

Return true if a function argument of type TYPE and mode MODE is to be passed in an integer register , or a pair of integer registers , if available .


<s>
unsigned
assignCustomValue
(
const
ARMCallLowering
::
ArgInfo
&
Arg
,
ArrayRef
<
CCValAssign
>
VAs
)
override
{
assert
(
Arg
.
Regs
.
size
(
)
==
1
&&
"Can't handle multple regs yet"
)
;
CCValAssign
VA
=
VAs
[
0
]
;
assert
(
VA
.
needsCustom
(
)
&&
"Value doesn't need custom handling"
)
;
assert
(
VA
.
getValVT
(
)
==
MVT
::
f64
&&
"Unsupported type"
)
;
CCValAssign
NextVA
=
VAs
[
1
]
;
assert
(
NextVA
.
needsCustom
(
)
&&
"Value doesn't need custom handling"
)
;
assert
(
NextVA
.
getValVT
(
)
==
MVT
::
f64
&&
"Unsupported type"
)
;
assert
(
VA
.
getValNo
(
)
==
NextVA
.
getValNo
(
)
&&
"Values belong to different arguments"
)
;
assert
(
VA
.
isRegLoc
(
)
&&
"Value should be in reg"
)
;
assert
(
NextVA
.
isRegLoc
(
)
&&
"Value should be in reg"
)
;
Register
NewRegs
[
]
=
{
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
32
)
)
,
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
32
)
)
}
;
assignValueToReg
(
NewRegs
[
0
]
,
VA
.
getLocReg
(
)
,
VA
)
;
assignValueToReg
(
NewRegs
[
1
]
,
NextVA
.
getLocReg
(
)
,
NextVA
)
;
bool
IsLittle
=
MIRBuilder
.
getMF
(
)
.
getSubtarget
<
ARMSubtarget
>
(
)
.
isLittle
(
)
;
if
(
!
IsLittle
)
std
::
swap
(
NewRegs
[
0
]
,
NewRegs
[
1
]
)
;
MIRBuilder
.
buildMerge
(
Arg
.
Regs
[
0
]
,
NewRegs
)
;
return
1
;
}
</s>

Handle custom values , which may be passed into one or more of VAs .


<s> bool R600InstrInfo :: isVector ( const MachineInstr & MI ) const { return get ( MI . getOpcode ( ) ) . TSFlags & R600_InstFlag :: VECTOR ; } </s>

Vector instructions are instructions that must fill all instruction slots within an instruction group .


<s> InstructionCost ARMTargetLowering :: getScalingFactorCost ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( isLegalAddressingMode ( DL , AM , Ty , AS ) ) { if ( Subtarget -> hasFPAO ( ) ) return AM . Scale < 0 ? 1 : 0 ; return 0 ; } return - 1 ; } </s>

Return the cost of the scaling factor used in the addressing mode represented by AM for this target , for a load/store of the specified type .


<s> static void rs6000_emit_stack_tie ( void ) { rtx mem = gen_rtx_MEM ( BLKmode , gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ) ; set_mem_alias_set ( mem , rs6000_sr_alias_set ) ; emit_insn ( gen_stack_tie ( mem ) ) ; } </s>

This ties together stack memory ( MEM with an alias set of rs6000_sr_alias_set ) and the change to the stack pointer .


<s> void AnalyzeFormalArguments ( const SmallVectorImpl < ISD :: InputArg > & Ins , CCAssignFn Fn ) { PreAnalyzeFormalArgumentsForF128 ( Ins ) ; CCState :: AnalyzeFormalArguments ( Ins , Fn ) ; OriginalArgWasFloat . clear ( ) ; OriginalArgWasF128 . clear ( ) ; OriginalArgWasFloatVector . clear ( ) ; } </s>

AnalyzeFormalArguments - Analyze an array of argument values , incorporating info about the formals into this state .