<s> static void reset ( ) { Blocks . clear ( ) ; PredicatedInsts . clear ( ) ; CurrentPredicates . clear ( ) ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s> static void riscv_adjust_block_mem ( rtx mem , unsigned HOST_WIDE_INT length , rtx * loop_reg , rtx * loop_mem ) { * loop_reg = copy_addr_to_reg ( XEXP ( mem , 0 ) ) ; * loop_mem = change_address ( mem , BLKmode , * loop_reg ) ; set_mem_align ( * loop_mem , MIN ( MEM_ALIGN ( mem ) , length * BITS_PER_UNIT ) ) ; } </s>

Helper function for doing a loop-based block operation on memory reference MEM . Each iteration of the loop will operate on LENGTH bytes of MEM . Create a new base register for use within the loop and point it to the start of MEM . Create a new memory reference that uses this register . Store them in * LOOP_REG and * LOOP_MEM respectively .


<s> void HexagonRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOp , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; MachineBasicBlock & MB = * MI . getParent ( ) ; MachineFunction & MF = * MB . getParent ( ) ; auto & HST = MF . getSubtarget < HexagonSubtarget > ( ) ; auto & HII = * HST . getInstrInfo ( ) ; auto & HFI = * HST . getFrameLowering ( ) ; unsigned BP = 0 ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; int Offset = HFI . getFrameIndexReference ( MF , FI , BP ) ; int RealOffset = Offset + MI . getOperand ( FIOp + 1 ) . getImm ( ) ; bool IsKill = false ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case Hexagon :: PS_fia : MI . setDesc ( HII . get ( Hexagon :: A2_addi ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + 1 ) ; return ; case Hexagon :: PS_fi : MI . setDesc ( HII . get ( Hexagon :: A2_addi ) ) ; break ; } if ( ! HII . isValidOffset ( Opc , RealOffset ) ) { auto & MRI = MF . getRegInfo ( ) ; unsigned TmpR = MRI . createVirtualRegister ( & Hexagon :: IntRegsRegClass ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( MB , II , DL , HII . get ( Hexagon :: A2_addi ) , TmpR ) . addReg ( BP ) . addImm ( RealOffset ) ; BP = TmpR ; RealOffset = 0 ; IsKill = true ; } MI . getOperand ( FIOp ) . ChangeToRegister ( BP , false , false , IsKill ) ; MI . getOperand ( FIOp + 1 ) . ChangeToImmediate ( RealOffset ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


"AArch64 Collect Linker Optimization Hint (LOH)"

getPassName - Return a nice clean name for a pass .


<s> bool SITargetLowering :: requiresUniformRegister ( MachineFunction & MF , const Value * V ) const { if ( const IntrinsicInst * Intrinsic = dyn_cast < IntrinsicInst > ( V ) ) { switch ( Intrinsic -> getIntrinsicID ( ) ) { default : return false ; case Intrinsic :: amdgcn_if_break : return true ; } } if ( const ExtractValueInst * ExtValue = dyn_cast < ExtractValueInst > ( V ) ) { if ( const IntrinsicInst * Intrinsic = dyn_cast < IntrinsicInst > ( ExtValue -> getOperand ( 0 ) ) ) { switch ( Intrinsic -> getIntrinsicID ( ) ) { default : return false ; case Intrinsic :: amdgcn_if : case Intrinsic :: amdgcn_else : { ArrayRef < unsigned > Indices = ExtValue -> getIndices ( ) ; if ( Indices . size ( ) == 1 && Indices [ 0 ] == 1 ) { return true ; } } } } } if ( const CallInst * CI = dyn_cast < CallInst > ( V ) ) { if ( isa < InlineAsm > ( CI -> getCalledValue ( ) ) ) { const SIRegisterInfo * SIRI = Subtarget -> getRegisterInfo ( ) ; ImmutableCallSite CS ( CI ) ; TargetLowering :: AsmOperandInfoVector TargetConstraints = ParseConstraints ( MF . getDataLayout ( ) , Subtarget -> getRegisterInfo ( ) , CS ) ; for ( auto & TC : TargetConstraints ) { if ( TC . Type == InlineAsm :: isOutput ) { ComputeConstraintToUse ( TC , SDValue ( ) ) ; unsigned AssignedReg ; const TargetRegisterClass * RC ; std :: tie ( AssignedReg , RC ) = getRegForInlineAsmConstraint ( SIRI , TC . ConstraintCode , TC . ConstraintVT ) ; if ( RC ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( AssignedReg != 0 && SIRI -> isSGPRReg ( MRI , AssignedReg ) ) return true ; else if ( SIRI -> isSGPRClass ( RC ) ) return true ; } } } } } SmallPtrSet < const Value * , 16 > Visited ; return hasCFUser ( V , Visited ) ; } </s>

Allows target to decide about the register class of the specific value that is live outside the defining block .


<s> void m32r_expand_prologue ( void ) { int regno ; int frame_size ; unsigned int gmask ; int pic_reg_used = flag_pic && ( crtl -> uses_pic_offset_table | crtl -> profile ) ; if ( ! current_frame_info . initialized ) m32r_compute_frame_size ( get_frame_size ( ) ) ; gmask = current_frame_info . gmask ; gcc_assert ( current_frame_info . total_size || ! gmask ) ; if ( current_frame_info . pretend_size != 0 ) { HOST_WIDE_INT pretend_size = current_frame_info . pretend_size ; emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - pretend_size ) ) ) ; } if ( current_frame_info . save_fp ) emit_insn ( gen_movsi_push ( stack_pointer_rtx , frame_pointer_rtx ) ) ; gmask &= ~ ( FRAME_POINTER_MASK | RETURN_ADDR_MASK ) ; for ( regno = 0 ; regno <= M32R_MAX_INT_REGS ; ++ regno ) { if ( ( gmask & ( 1 << regno ) ) != 0 ) emit_insn ( gen_movsi_push ( stack_pointer_rtx , gen_rtx_REG ( Pmode , regno ) ) ) ; } if ( current_frame_info . save_lr ) emit_insn ( gen_movsi_push ( stack_pointer_rtx , gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ) ) ; frame_size = ( current_frame_info . total_size - ( current_frame_info . pretend_size + current_frame_info . reg_size ) ) ; if ( frame_size == 0 ) ; else if ( frame_size <= 32768 ) emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - frame_size ) ) ) ; else { rtx tmp = gen_rtx_REG ( Pmode , PROLOGUE_TMP_REGNUM ) ; emit_insn ( gen_movsi ( tmp , GEN_INT ( frame_size ) ) ) ; emit_insn ( gen_subsi3 ( stack_pointer_rtx , stack_pointer_rtx , tmp ) ) ; } if ( frame_pointer_needed ) emit_insn ( gen_movsi ( frame_pointer_rtx , stack_pointer_rtx ) ) ; if ( crtl -> profile ) emit_insn ( gen_movsi_push ( stack_pointer_rtx , gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ) ) ; if ( pic_reg_used ) { m32r_load_pic_register ( ) ; m32r_reload_lr ( stack_pointer_rtx , ( crtl -> profile ? 0 : frame_size ) ) ; } if ( crtl -> profile && ! pic_reg_used ) emit_insn ( gen_blockage ( ) ) ; } </s>

Expand the m32r prologue as a series of insns .


<s> bool fusion_p9_p ( rtx addis_reg , rtx addis_value , rtx dest , rtx src ) { rtx addr , mem , offset ; enum machine_mode mode = GET_MODE ( src ) ; if ( ! base_reg_operand ( addis_reg , GET_MODE ( addis_reg ) ) ) return false ; if ( ! fusion_gpr_addis ( addis_value , GET_MODE ( addis_value ) ) ) return false ; if ( GET_CODE ( src ) == FLOAT_EXTEND || GET_CODE ( src ) == ZERO_EXTEND ) src = XEXP ( src , 0 ) ; if ( fpr_reg_operand ( src , mode ) || int_reg_operand ( src , mode ) ) { if ( ! MEM_P ( dest ) ) return false ; mem = dest ; } else if ( MEM_P ( src ) ) { if ( ! fpr_reg_operand ( dest , mode ) && ! int_reg_operand ( dest , mode ) ) return false ; mem = src ; } else return false ; addr = XEXP ( mem , 0 ) ; if ( GET_CODE ( addr ) == PLUS ) { if ( ! rtx_equal_p ( addis_reg , XEXP ( addr , 0 ) ) ) return false ; return satisfies_constraint_I ( XEXP ( addr , 1 ) ) ; } else if ( GET_CODE ( addr ) == LO_SUM ) { if ( ! rtx_equal_p ( addis_reg , XEXP ( addr , 0 ) ) ) return false ; offset = XEXP ( addr , 1 ) ; if ( TARGET_XCOFF || ( TARGET_ELF && TARGET_POWERPC64 ) ) return small_toc_ref ( offset , GET_MODE ( offset ) ) ; else if ( TARGET_ELF && ! TARGET_POWERPC64 ) return CONSTANT_P ( offset ) ; } return false ; } </s>

Return true if the peephole2 can combine a load/store involving a combination of an addis instruction and the memory operation . This was added to the ISA 3.0 ( power9 ) hardware .


<s> void init_68881_table ( void ) { int i ; REAL_VALUE_TYPE r ; machine_mode mode ; mode = SFmode ; for ( i = 0 ; i < 7 ; i ++ ) { if ( i == 6 ) mode = DFmode ; r = REAL_VALUE_ATOF ( strings_68881 [ i ] , mode ) ; values_68881 [ i ] = r ; } inited_68881_table = 1 ; } </s>

Set up values_68881 array by converting the decimal values strings_68881 to binary .


<s>
bool
WebAssemblyTTIImpl
::
haveFastSqrt
(
Type
*
Ty
)
const
{
assert
(
Ty
->
isFPOrFPVectorTy
(
)
&&
"Ty must be floating point"
)
;
return
true
;
}
</s>

Return true if the hardware has a fast square-root instruction .

WebAssembly
WebAssembly
"Ty must be floating point"


<s> static int aarch64_sched_issue_rate ( void ) { return aarch64_tune_params -> issue_rate ; } </s>

Return the number of instructions that can be issued per cycle .


<s>
void
output_ascii
(
FILE
*
file
,
const
char
*
p
,
int
n
)
{
char
c
;
int
i
,
count_string
;
const
char
*
for_string
=
"\t.byte \""
;
const
char
*
for_decimal
=
"\t.byte "
;
const
char
*
to_close
=
;
count_string
=
0
;
for
(
i
=
0
;
i
<
n
;
i
++
)
{
c
=
*
p
++
;
if
(
c
>=
' '
&&
c
<
0177
)
{
if
(
for_string
)
fputs
(
for_string
,
file
)
;
putc
(
c
,
file
)
;
if
(
c
==
'"'
)
{
putc
(
c
,
file
)
;
++
count_string
;
}
for_string
=
;
for_decimal
=
"\"\n\t.byte "
;
to_close
=
"\"\n"
;
++
count_string
;
if
(
count_string
>=
512
)
{
fputs
(
to_close
,
file
)
;
for_string
=
"\t.byte \""
;
for_decimal
=
"\t.byte "
;
to_close
=
;
count_string
=
0
;
}
}
else
{
if
(
for_decimal
)
fputs
(
for_decimal
,
file
)
;
fprintf
(
file
,
"%d"
,
c
)
;
for_string
=
"\n\t.byte \""
;
for_decimal
=
", "
;
to_close
=
"\n"
;
count_string
=
0
;
}
}
if
(
to_close
)
fputs
(
to_close
,
file
)
;
}
</s>

Output an assembler pseudo-op to write an ASCII string of N characters starting at P to FILE . On the RS/6000 , we have to do this using the .byte operation and write out special characters outside the quoted string . Also , the assembler is broken ; very long strings are truncated , so we must artificially break them up early .


<s> SDNode * SITargetLowering :: legalizeTargetIndependentNode ( SDNode * Node , SelectionDAG & DAG ) const { if ( Node -> getOpcode ( ) == ISD :: CopyToReg ) { RegisterSDNode * DestReg = cast < RegisterSDNode > ( Node -> getOperand ( 1 ) ) ; SDValue SrcVal = Node -> getOperand ( 2 ) ; if ( SrcVal . getValueType ( ) == MVT :: i1 && Register :: isPhysicalRegister ( DestReg -> getReg ( ) ) ) { SDLoc SL ( Node ) ; MachineRegisterInfo & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue VReg = DAG . getRegister ( MRI . createVirtualRegister ( & AMDGPU :: VReg_1RegClass ) , MVT :: i1 ) ; SDNode * Glued = Node -> getGluedNode ( ) ; SDValue ToVReg = DAG . getCopyToReg ( Node -> getOperand ( 0 ) , SL , VReg , SrcVal , SDValue ( Glued , Glued ? Glued -> getNumValues ( ) - 1 : 0 ) ) ; SDValue ToResultReg = DAG . getCopyToReg ( ToVReg , SL , SDValue ( DestReg , 0 ) , VReg , ToVReg . getValue ( 1 ) ) ; DAG . ReplaceAllUsesWith ( Node , ToResultReg . getNode ( ) ) ; DAG . RemoveDeadNode ( Node ) ; return ToResultReg . getNode ( ) ; } } SmallVector < SDValue , 8 > Ops ; for ( unsigned i = 0 ; i < Node -> getNumOperands ( ) ; ++ i ) { if ( ! isFrameIndexOp ( Node -> getOperand ( i ) ) ) { Ops . push_back ( Node -> getOperand ( i ) ) ; continue ; } SDLoc DL ( Node ) ; Ops . push_back ( SDValue ( DAG . getMachineNode ( AMDGPU :: S_MOV_B32 , DL , Node -> getOperand ( i ) . getValueType ( ) , Node -> getOperand ( i ) ) , 0 ) ) ; } return DAG . UpdateNodeOperands ( Node , Ops ) ; } </s>

Legalize target independent instructions ( e.g .


<s> static void s390_regs_ever_clobbered ( int * regs_ever_clobbered ) { basic_block cur_bb ; rtx cur_insn ; unsigned int i ; memset ( regs_ever_clobbered , 0 , 16 * sizeof ( int ) ) ; if ( ! current_function_is_leaf ) { for ( i = 0 ; i < 16 ; i ++ ) regs_ever_clobbered [ i ] = call_really_used_regs [ i ] ; } if ( current_function_calls_eh_return || cfun -> machine -> has_landing_pad_p ) for ( i = 0 ; EH_RETURN_DATA_REGNO ( i ) != INVALID_REGNUM ; i ++ ) if ( current_function_calls_eh_return || ( cfun -> machine -> has_landing_pad_p && regs_ever_live [ EH_RETURN_DATA_REGNO ( i ) ] ) ) regs_ever_clobbered [ EH_RETURN_DATA_REGNO ( i ) ] = 1 ; if ( current_function_has_nonlocal_label ) for ( i = 0 ; i < 16 ; i ++ ) if ( ! call_really_used_regs [ i ] ) regs_ever_clobbered [ i ] = 1 ; FOR_EACH_BB ( cur_bb ) { FOR_BB_INSNS ( cur_bb , cur_insn ) { if ( INSN_P ( cur_insn ) ) note_stores ( PATTERN ( cur_insn ) , s390_reg_clobbered_rtx , regs_ever_clobbered ) ; } } } </s>

Walks through all basic blocks of the current function looking for clobbered hard regs using s390_reg_clobbered_rtx . The fields of the passed integer array REGS_EVER_CLOBBERED are set to one for each of those regs .


<s> bool SIRegisterInfo :: isFrameOffsetLegal ( const MachineInstr * MI , Register BaseReg , int64_t Offset ) const { if ( ! SIInstrInfo :: isMUBUF ( * MI ) && ! ! SIInstrInfo :: isFLATScratch ( * MI ) ) return false ; int64_t NewOffset = Offset + getScratchInstrOffset ( MI ) ; if ( SIInstrInfo :: isMUBUF ( * MI ) ) return SIInstrInfo :: isLegalMUBUFImmOffset ( NewOffset ) ; const SIInstrInfo * TII = ST . getInstrInfo ( ) ; return TII -> isLegalFLATOffset ( NewOffset , AMDGPUAS :: PRIVATE_ADDRESS , true ) ; } </s>

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s> static int thumb2_legitimate_index_p ( machine_mode mode , rtx index , int strict_p ) { enum rtx_code code = GET_CODE ( index ) ; if ( TARGET_HARD_FLOAT && ( mode == SFmode || mode == DFmode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 256 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE ( mode ) ) { if ( ! TARGET_LDRD || mode != DImode ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; } if ( TARGET_NEON && VALID_NEON_QREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1016 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( TARGET_NEON && VALID_NEON_DREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( arm_address_register_rtx_p ( index , strict_p ) && ( GET_MODE_SIZE ( mode ) <= 4 ) ) return 1 ; if ( mode == DImode || mode == DFmode ) { if ( code == CONST_INT ) { HOST_WIDE_INT val = INTVAL ( index ) ; return val > - 256 && val < 256 && ( val & 3 ) == 0 ; } else return 0 ; } if ( code == MULT ) { rtx xiop0 = XEXP ( index , 0 ) ; rtx xiop1 = XEXP ( index , 1 ) ; return ( ( arm_address_register_rtx_p ( xiop0 , strict_p ) && thumb2_index_mul_operand ( xiop1 ) ) || ( arm_address_register_rtx_p ( xiop1 , strict_p ) && thumb2_index_mul_operand ( xiop0 ) ) ) ; } else if ( code == ASHIFT ) { rtx op = XEXP ( index , 1 ) ; return ( arm_address_register_rtx_p ( XEXP ( index , 0 ) , strict_p ) && CONST_INT_P ( op ) && INTVAL ( op ) > 0 && INTVAL ( op ) <= 3 ) ; } return ( code == CONST_INT && INTVAL ( index ) < 4096 && INTVAL ( index ) > - 256 ) ; } </s>

Return nonzero if INDEX is a valid Thumb-2 address index operand .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( AFI -> getGlobalBaseReg ( ) == 0 ) return false ; const ARMSubtarget & STI = static_cast < const ARMSubtarget & > ( MF . getSubtarget ( ) ) ; if ( STI . isThumb1Only ( ) ) return false ; const TargetMachine & TM = MF . getTarget ( ) ; if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) return false ; LLVMContext * Context = & MF . getFunction ( ) -> getContext ( ) ; unsigned ARMPCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = STI . isThumb ( ) ? 4 : 8 ; ARMConstantPoolValue * CPV = ARMConstantPoolSymbol :: Create ( * Context , "_GLOBAL_OFFSET_TABLE_" , ARMPCLabelIndex , PCAdj ) ; unsigned Align = TM . getDataLayout ( ) -> getPrefTypeAlignment ( Type :: getInt32PtrTy ( * Context ) ) ; unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned TempReg = MF . getRegInfo ( ) . createVirtualRegister ( & ARM :: rGPRRegClass ) ; unsigned Opc = STI . isThumb2 ( ) ? ARM :: t2LDRpci : ARM :: LDRcp ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , TempReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == ARM :: LDRcp ) MIB . addImm ( 0 ) ; AddDefaultPred ( MIB ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; Opc = STI . isThumb2 ( ) ? ARM :: tPICADD : ARM :: PICADD ; MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addReg ( TempReg ) . addImm ( ARMPCLabelIndex ) ; if ( Opc == ARM :: PICADD ) AddDefaultPred ( MIB ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .

ARM ARM ARM 0 ARM ARM ARM 4 8 ARM ARM "_GLOBAL_OFFSET_TABLE_" ARM ARM::rGPRRegClass ARM::t2LDRpci ARM::LDRcp ARM::LDRcp 0 ARM::tPICADD ARM::PICADD ARM ARM::PICADD


<s> static bool csky_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { const HOST_WIDE_INT size = int_size_in_bytes ( type ) ; return ( size == - 1 || size > 2 * UNITS_PER_WORD ) ; } </s>

Implement TARGET_RETURN_IN_MEMORY to decide whether TYPE should be returned in memory ( true ) or in a register ( false ) . FNTYPE is the type of the function making the call .


<s> TargetLowering :: ConstraintType mprocTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return C_RegisterClass ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> void F2003fMCAsmStreamer :: emitRawComment ( const Twine & T , bool TabPrefix ) { OS << MAI -> getCommentString ( ) << T ; EmitEOL ( ) ; } </s>

Print T and prefix it with the comment string ( normally # ) and optionally a tab .


<s> const TargetRegisterClass * SIInstrInfo :: getOpRegClass ( const MachineInstr & MI , unsigned OpNo ) const { const MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const MCInstrDesc & Desc = get ( MI . getOpcode ( ) ) ; if ( MI . isVariadic ( ) || OpNo >= Desc . getNumOperands ( ) || Desc . OpInfo [ OpNo ] . RegClass == - 1 ) { Register Reg = MI . getOperand ( OpNo ) . getReg ( ) ; if ( Reg . isVirtual ( ) ) return MRI . getRegClass ( Reg ) ; return RI . getPhysRegClass ( Reg ) ; } unsigned RCID = Desc . OpInfo [ OpNo ] . RegClass ; return adjustAllocatableRegClass ( ST , RI , MRI , Desc , RCID , true ) ; } </s>

Return the correct register class for OpNo .


<s> std :: pair < const TargetRegisterClass * , uint8_t > HexagonTargetLowering :: findRepresentativeClass ( const TargetRegisterInfo * TRI , MVT VT ) const { const TargetRegisterClass * RRC = nullptr ; uint8_t Cost = 1 ; switch ( VT . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( TRI , VT ) ; case MVT :: v64i8 : case MVT :: v32i16 : case MVT :: v16i32 : RRC = & Hexagon :: HvxVRRegClass ; break ; case MVT :: v128i8 : case MVT :: v64i16 : case MVT :: v32i32 : if ( Subtarget . hasV60TOps ( ) && Subtarget . useHVXOps ( ) && Subtarget . useHVX128BOps ( ) ) RRC = & Hexagon :: HvxVRRegClass ; else RRC = & Hexagon :: HvxWRRegClass ; break ; case MVT :: v256i8 : case MVT :: v128i16 : case MVT :: v64i32 : RRC = & Hexagon :: HvxWRRegClass ; break ; } return std :: make_pair ( RRC , Cost ) ; } </s>

Return the largest legal super-reg register class of the register class for the specified type and its associated `` cost '' .


<s>
bool
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
override
{
switch
(
ConstraintID
)
{
default
:
errs
(
)
<<
"ConstraintID: "
<<
ConstraintID
<<
"\n"
;
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_es
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_o
:
case
InlineAsm
::
Constraint_Q
:
case
InlineAsm
::
Constraint_Z
:
case
InlineAsm
::
Constraint_Zy
:
const
TargetRegisterInfo
*
TRI
=
Subtarget
->
getRegisterInfo
(
)
;
const
TargetRegisterClass
*
TRC
=
TRI
->
getPointerRegClass
(
*
MF
,
1
)
;
SDLoc
dl
(
Op
)
;
SDValue
RC
=
CurDAG
->
getTargetConstant
(
TRC
->
getID
(
)
,
dl
,
MVT
::
i32
)
;
SDValue
NewOp
=
SDValue
(
CurDAG
->
getMachineNode
(
TargetOpcode
::
COPY_TO_REGCLASS
,
dl
,
Op
.
getValueType
(
)
,
Op
,
RC
)
,
0
)
;
OutOps
.
push_back
(
NewOp
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> static rtx_insn * alphaev5_next_group ( rtx_insn * insn , int * pin_use , int * plen ) { int len , in_use ; len = in_use = 0 ; if ( ! INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == CLOBBER || GET_CODE ( PATTERN ( insn ) ) == USE ) goto next_and_done ; while ( 1 ) { enum alphaev5_pipe pipe ; pipe = alphaev5_insn_pipe ( insn ) ; switch ( pipe ) { case EV5_STOP : if ( in_use ) goto done ; if ( recog_memoized ( insn ) < 0 ) len = - 1 ; else len = get_attr_length ( insn ) ; goto next_and_done ; case EV5_E01 : if ( in_use & EV5_E0 ) { if ( in_use & EV5_E1 ) goto done ; in_use |= EV5_E1 ; } else in_use |= EV5_E0 | EV5_E01 ; break ; case EV5_E0 : if ( in_use & EV5_E0 ) { if ( ! ( in_use & EV5_E01 ) || ( in_use & EV5_E1 ) ) goto done ; in_use |= EV5_E1 ; } in_use |= EV5_E0 ; break ; case EV5_E1 : if ( in_use & EV5_E1 ) goto done ; in_use |= EV5_E1 ; break ; case EV5_FAM : if ( in_use & EV5_FA ) { if ( in_use & EV5_FM ) goto done ; in_use |= EV5_FM ; } else in_use |= EV5_FA | EV5_FAM ; break ; case EV5_FA : if ( in_use & EV5_FA ) goto done ; in_use |= EV5_FA ; break ; case EV5_FM : if ( in_use & EV5_FM ) goto done ; in_use |= EV5_FM ; break ; case EV5_NONE : break ; default : gcc_unreachable ( ) ; } len += 4 ; if ( JUMP_P ( insn ) ) goto next_and_done ; next : insn = next_nonnote_insn ( insn ) ; if ( ! insn || ! INSN_P ( insn ) ) goto done ; if ( GET_MODE ( insn ) == TImode ) goto done ; if ( GET_CODE ( insn ) == CLOBBER || GET_CODE ( insn ) == USE ) goto next ; } next_and_done : insn = next_nonnote_insn ( insn ) ; done : * plen = len ; * pin_use = in_use ; return insn ; } </s>

IN_USE is a mask of the slots currently filled within the insn group . The mask bits come from alphaev5_pipe above . If EV5_E01 is set , then the insn in EV5_E0 can be swapped by the hardware into EV5_E1 . LEN is , of course , the length of the group in bytes .


<s> int cris_cfun_uses_pic_table ( ) { return current_function_uses_pic_offset_table ; } </s>

Return current_function_uses_pic_offset_table . For use in cris.md , since some generated files do not include function.h .


<s> bool TPCIndexMap :: runOnFunction ( Function & F ) { p_func = & F ; p_SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; p_LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; collectDataLoop ( F , p_SE , p_LI ) ; sort ( ) ; print_data ( ) ; return false ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> virtual MVT getScalarShiftAmountTy ( EVT LHSTy ) const { return MVT :: i8 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> void NyuziInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << StringRef ( getRegisterName ( RegNo ) ) . lower ( ) ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"SI Type Rewriter"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> MachineBasicBlock * PIC16TargetLowering :: EmitInstrWithCustomInserter ( MachineInstr * MI , MachineBasicBlock * BB ) const { const TargetInstrInfo & TII = * getTargetMachine ( ) . getInstrInfo ( ) ; unsigned CC = ( PIC16CC :: CondCodes ) MI -> getOperand ( 3 ) . getImm ( ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; BuildMI ( BB , dl , TII . get ( PIC16 :: pic16brcond ) ) . addMBB ( sinkMBB ) . addImm ( CC ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> transferSuccessors ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( BB , dl , TII . get ( PIC16 :: PHI ) , MI -> getOperand ( 0 ) . getReg ( ) ) . addReg ( MI -> getOperand ( 2 ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( 1 ) . getReg ( ) ) . addMBB ( thisMBB ) ; F -> DeleteMachineInstr ( MI ) ; return BB ; } </s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static enum machine_mode rs6000_eh_return_filter_mode ( void ) { return TARGET_32BIT ? SImode : word_mode ; } </s>


"without AVX512F enabled changes the ABI"

Return the `` natural '' mode for TYPE . In most cases , this is just TYPE_MODE . But in the case of vector types , it is some vector mode . When we have only some of our vector isa extensions enabled , then there are some modes for which vector_mode_supported_p is false . For these modes , the generic vector support in gcc will choose some non-vector mode in order to implement the type . By computing the natural mode , we 'll select the proper ABI location for the operand and not depend on whatever the middle-end decides to do with these vector types .


"Equivalent instruction substitution pass"


<s> bool SITargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Align , bool * IsFast ) const { if ( IsFast ) * IsFast = false ; if ( ! VT . isSimple ( ) || VT == MVT :: Other ) return false ; if ( AddrSpace == AMDGPUAS :: LOCAL_ADDRESS ) { return Align % 4 == 0 ; } if ( VT . bitsLT ( MVT :: i32 ) ) return false ; if ( IsFast ) * IsFast = true ; return VT . bitsGT ( MVT :: i32 ) && Align % 4 == 0 ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const R600InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; for ( MachineFunction :: iterator BB = MF . begin ( ) , BB_E = MF . end ( ) ; BB != BB_E ; ++ BB ) { MachineBasicBlock & MBB = * BB ; MachineBasicBlock :: iterator I = MBB . begin ( ) ; if ( I -> getOpcode ( ) == AMDGPU :: CF_ALU ) continue ; for ( MachineBasicBlock :: iterator E = MBB . end ( ) ; I != E ; ) { if ( isALU ( I ) ) I = MakeALUClause ( MBB , I ) ; else ++ I ; } } return false ; } </s>


<s> bool LatticeCell :: add ( uint32_t Property ) { bool Changed = convertToProperty ( ) ; uint32_t Ps = properties ( ) ; if ( Ps == ( Ps & Property ) ) return Changed ; Properties = Property & Ps ; return true ; } </s>


<s>
bool
AVRInstrInfo
::
reverseBranchCondition
(
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
assert
(
Cond
.
size
(
)
==
1
&&
"Invalid AVR branch condition!"
)
;
AVRCC
::
CondCodes
CC
=
static_cast
<
AVRCC
::
CondCodes
>
(
Cond
[
0
]
.
getImm
(
)
)
;
Cond
[
0
]
.
setImm
(
getOppositeCondition
(
CC
)
)
;
return
false
;
}
</s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> static rtx m68k_delegitimize_address ( rtx orig_x ) { rtx x ; struct m68k_address addr ; rtx unspec ; orig_x = delegitimize_mem_from_attrs ( orig_x ) ; x = orig_x ; if ( MEM_P ( x ) ) x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) != PLUS || GET_MODE ( x ) != Pmode ) return orig_x ; if ( ! m68k_decompose_address ( GET_MODE ( x ) , x , false , & addr ) || addr . offset == NULL_RTX || GET_CODE ( addr . offset ) != CONST ) return orig_x ; unspec = XEXP ( addr . offset , 0 ) ; if ( GET_CODE ( unspec ) == PLUS && CONST_INT_P ( XEXP ( unspec , 1 ) ) ) unspec = XEXP ( unspec , 0 ) ; if ( GET_CODE ( unspec ) != UNSPEC || ( XINT ( unspec , 1 ) != UNSPEC_RELOC16 && XINT ( unspec , 1 ) != UNSPEC_RELOC32 ) ) return orig_x ; x = XVECEXP ( unspec , 0 , 0 ) ; gcc_assert ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF ) ; if ( unspec != XEXP ( addr . offset , 0 ) ) x = gen_rtx_PLUS ( Pmode , x , XEXP ( XEXP ( addr . offset , 0 ) , 1 ) ) ; if ( addr . index ) { rtx idx = addr . index ; if ( addr . scale != 1 ) idx = gen_rtx_MULT ( Pmode , idx , GEN_INT ( addr . scale ) ) ; x = gen_rtx_PLUS ( Pmode , idx , x ) ; } if ( addr . base ) x = gen_rtx_PLUS ( Pmode , addr . base , x ) ; if ( MEM_P ( orig_x ) ) x = replace_equiv_address_nv ( orig_x , x ) ; return x ; } </s>

In the name of slightly smaller debug output , and to cater to general assembler lossage , recognize various UNSPEC sequences and turn them back into a direct symbol reference .


<s>
int
m32c_cannot_change_mode_class
(
enum
machine_mode
from
,
enum
machine_mode
to
,
int
rclass
)
{
fprintf
(
stderr
,
"cannot change from %s to %s in %s\n"
,
mode_name
[
from
]
,
mode_name
[
to
]
,
class_names
[
rclass
]
)
;
if
(
to
==
QImode
)
return
(
class_contents
[
rclass
]
[
0
]
&
0x1ffa
)
;
if
(
class_contents
[
rclass
]
[
0
]
&
0x0005
&&
GET_MODE_SIZE
(
from
)
>
1
)
return
0
;
if
(
GET_MODE_SIZE
(
from
)
>
2
)
return
0
;
return
1
;
}
</s>

Implements CANNOT_CHANGE_MODE_CLASS . Only r0 and r1 can change to QI ( r0l , r1l ) because the chip does n't support QI ops on other registers ( well , it does on a0/a1 but if we let gcc do that , reload suffers ) . Otherwise , we allow changes to larger modes .


"Legal fp imm: materialize 0 using the zero register\n"

Returns true if the target can instruction select the specified FP immediate natively .


<s> bool loongarch_split_symbol ( rtx temp , rtx addr , machine_mode mode , rtx * low_out ) { enum loongarch_symbol_type symbol_type ; if ( ! TARGET_EXPLICIT_RELOCS ) return false ; if ( ( GET_CODE ( addr ) == HIGH && mode == MAX_MACHINE_MODE ) || ! loongarch_symbolic_constant_p ( addr , & symbol_type ) || loongarch_symbol_insns ( symbol_type , mode ) == 0 || ! loongarch_split_symbol_type ( symbol_type ) ) return false ; rtx high , temp1 = NULL ; if ( temp == NULL ) temp = gen_reg_rtx ( Pmode ) ; high = gen_rtx_HIGH ( Pmode , copy_rtx ( addr ) ) ; high = loongarch_force_temporary ( temp , high ) ; if ( loongarch_symbol_extreme_p ( symbol_type ) && can_create_pseudo_p ( ) ) { gcc_assert ( TARGET_EXPLICIT_RELOCS ) ; temp1 = gen_reg_rtx ( Pmode ) ; emit_move_insn ( temp1 , gen_rtx_LO_SUM ( Pmode , gen_rtx_REG ( Pmode , 0 ) , addr ) ) ; emit_insn ( gen_lui_h_lo20 ( temp1 , temp1 , addr ) ) ; emit_insn ( gen_lui_h_hi12 ( temp1 , temp1 , addr ) ) ; } if ( low_out ) switch ( symbol_type ) { case SYMBOL_PCREL64 : if ( can_create_pseudo_p ( ) ) { * low_out = gen_rtx_PLUS ( Pmode , high , temp1 ) ; break ; } case SYMBOL_PCREL : * low_out = gen_rtx_LO_SUM ( Pmode , high , addr ) ; break ; case SYMBOL_GOT_DISP : { if ( TARGET_CMODEL_EXTREME && can_create_pseudo_p ( ) ) * low_out = gen_rtx_MEM ( Pmode , gen_rtx_PLUS ( Pmode , high , temp1 ) ) ; else { rtx low = gen_rtx_LO_SUM ( Pmode , high , addr ) ; rtx mem = gen_rtx_MEM ( Pmode , low ) ; * low_out = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , mem ) , UNSPEC_LOAD_FROM_GOT ) ; } break ; } default : gcc_unreachable ( ) ; } return true ; } </s>

If MODE is MAX_MACHINE_MODE , ADDR appears as a move operand , otherwise it appears in a MEM of that mode . Return true if ADDR is a legitimate constant in that context and can be split into high and low parts . If so , and if LOW_OUT is nonnull , emit the high part and store the low part in * LOW_OUT . Leave * LOW_OUT unchanged otherwise . Return false if build with '-mno-explicit-relocs ' . TEMP is as for loongarch_force_temporary and is used to load the high part into a register . When MODE is MAX_MACHINE_MODE , the low part is guaranteed to be a legitimize SET_SRC for an .md pattern , otherwise the low part is guaranteed to be a legitimate address for mode MODE .


<s> StackOffset AArch64FrameLowering :: getNonLocalFrameIndexReference ( const MachineFunction & MF , int FI ) const { return StackOffset :: getFixed ( getSEHFrameIndexOffset ( MF , FI ) ) ; } </s>

getNonLocalFrameIndexReference - This method returns the offset used to reference a frame index location .


<s> void print ( raw_ostream & OS , const TargetMachine * TM = nullptr ) const { const TargetRegisterInfo * TRI = TM ? TM -> getRegisterInfo ( ) : nullptr ; if ( isReg ( ) ) { OS << PrintReg ( Contents . R . Reg , TRI , Contents . R . Sub ) ; } if ( isImm ( ) ) { OS << Contents . ImmVal ; } } </s>

print - Print a debug representation of the operand to the given stream .


<s> bool X86TargetLowering :: isCommutativeBinOp ( unsigned Opcode ) const { switch ( Opcode ) { case X86ISD :: PCMPEQ : case X86ISD :: PMULDQ : case X86ISD :: PMULUDQ : case X86ISD :: FMAXC : case X86ISD :: FMINC : case X86ISD :: FAND : case X86ISD :: FOR : case X86ISD :: FXOR : return true ; } return TargetLoweringBase :: isCommutativeBinOp ( Opcode ) ; } </s>

Returns true if the opcode is a commutative binary operation .


<s> bool BPFCheckAndAdjustIR :: runOnModule ( Module & M ) { checkIR ( M ) ; return adjustIR ( M ) ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> TargetLowering :: AtomicExpansionKind RISCVTargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { if ( AI -> isFloatingPointOperation ( ) ) return AtomicExpansionKind :: CmpXChg ; unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size == 8 || Size == 16 ) return AtomicExpansionKind :: MaskedIntrinsic ; return AtomicExpansionKind :: None ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> bool FPGATTIImpl :: isLegalAddImmediate ( int64_t Imm ) { return true ; } </s>

Return true if the specified immediate is legal add immediate , that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register .


<s> bool HexagonInstrInfo :: hasLoadFromStackSlot ( const MachineInstr & MI , SmallVectorImpl < const MachineMemOperand * > & Accesses ) const { if ( MI . isBundle ( ) ) { const MachineBasicBlock * MBB = MI . getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI . getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( TargetInstrInfo :: hasLoadFromStackSlot ( * MII , Accesses ) ) return true ; return false ; } return TargetInstrInfo :: hasLoadFromStackSlot ( MI , Accesses ) ; } </s>

If the specified machine instruction has a load from a stack slot , return true along with the FrameIndices of the loaded stack slot and the machine mem operands containing the reference .


<s> bool DLXAsmPrinter :: isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { const MachineBasicBlock * Pred = * MBB -> pred_begin ( ) ; if ( const BasicBlock * B = Pred -> getBasicBlock ( ) ) if ( isa < SwitchInst > ( B -> getTerminator ( ) ) ) return false ; if ( ! AsmPrinter :: isBlockOnlyReachableByFallthrough ( MBB ) ) return false ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> isTerminator ( ) ) { } return ! I -> isBarrier ( ) ; } </s>

isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


<s>
std
::
string
AMDGPUIntrinsicInfo
::
getName
(
unsigned
int
IntrID
,
Type
*
*
Tys
,
unsigned
int
numTys
)
const
{
static
const
char
*
const
names
[
]
=
{
}
;
if
(
IntrID
<
Intrinsic
::
num_intrinsics
)
{
return
0
;
}
assert
(
IntrID
<
AMDGPUIntrinsic
::
num_AMDGPU_intrinsics
&&
"Invalid intrinsic ID"
)
;
std
::
string
Result
(
names
[
IntrID
Intrinsic
::
num_intrinsics
]
)
;
return
Result
;
}
</s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> static bool sparc_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { enum mode_class mclass1 , mclass2 ; unsigned short size1 , size2 ; if ( mode1 == mode2 ) return true ; mclass1 = GET_MODE_CLASS ( mode1 ) ; mclass2 = GET_MODE_CLASS ( mode2 ) ; if ( mclass1 != mclass2 ) return false ; if ( ! TARGET_V9 ) return true ; if ( mclass1 != MODE_FLOAT && mclass1 != MODE_VECTOR_INT ) return true ; size1 = GET_MODE_SIZE ( mode1 ) ; size2 = GET_MODE_SIZE ( mode2 ) ; if ( ( size1 > 4 && size2 == 4 ) || ( size2 > 4 && size1 == 4 ) ) return false ; return true ; } </s>

Return TRUE if it is a good idea to tie two pseudo registers when one has mode MODE1 and one has mode MODE2 . If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2 , for any hard reg , then this must be FALSE for correct output . For V9 we have to deal with the fact that only the lower 32 floating point registers are 32-bit addressable .


<s> bool mep_ipipe_ldc_p ( rtx_insn * insn ) { rtx pat , src ; pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , 0 , 0 ) ; if ( GET_CODE ( pat ) == SET ) { src = SET_SRC ( pat ) ; if ( GET_CODE ( src ) == UNSPEC || GET_CODE ( src ) == UNSPEC_VOLATILE ) src = XVECEXP ( src , 0 , 0 ) ; if ( REG_P ( src ) ) switch ( REGNO ( src ) ) { case PSW_REGNO : case LP_REGNO : case SAR_REGNO : case HI_REGNO : case LO_REGNO : return true ; } } return false ; } </s>

Return true if INSN is an ldc instruction that issues to the MeP-h1 integer pipeline . This is true for instructions that read from PSW , LP , SAR , HI and LO .


<s> void AArch64FrameLowering :: resetCFIToInitialState ( MachineBasicBlock & MBB ) const { MachineFunction & MF = * MBB . getParent ( ) ; const auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; const auto & TRI = static_cast < const AArch64RegisterInfo & > ( * Subtarget . getRegisterInfo ( ) ) ; const auto & MFI = * MF . getInfo < AArch64FunctionInfo > ( ) ; const MCInstrDesc & CFIDesc = TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ; DebugLoc DL ; MachineBasicBlock :: iterator InsertPt = MBB . begin ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfa ( nullptr , TRI . getDwarfRegNum ( AArch64 :: SP , true ) , 0 ) ) ; BuildMI ( MBB , InsertPt , DL , CFIDesc ) . addCFIIndex ( CFIIndex ) ; if ( MFI . shouldSignReturnAddress ( ) ) { CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createNegateRAState ( nullptr ) ) ; BuildMI ( MBB , InsertPt , DL , CFIDesc ) . addCFIIndex ( CFIIndex ) ; } if ( needsShadowCallStackPrologueEpilogue ( MF ) ) insertCFISameValue ( CFIDesc , MF , MBB , InsertPt , TRI . getDwarfRegNum ( AArch64 :: X18 , true ) ) ; const std :: vector < CalleeSavedInfo > & CSI = MF . getFrameInfo ( ) . getCalleeSavedInfo ( ) ; for ( const auto & Info : CSI ) { unsigned Reg = Info . getReg ( ) ; if ( ! TRI . regNeedsCFI ( Reg , Reg ) ) continue ; insertCFISameValue ( CFIDesc , MF , MBB , InsertPt , TRI . getDwarfRegNum ( Reg , true ) ) ; } } </s>

Emit CFI instructions that recreate the state of the unwind information upon fucntion entry .


<s> bool ARMAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AFI = MF . getInfo < ARMFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; Subtarget = & MF . getSubtarget < ARMSubtarget > ( ) ; SetupMachineFunction ( MF ) ; const Function & F = MF . getFunction ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; for ( auto * GV : AFI -> getGlobalsPromotedToConstantPool ( ) ) PromotedGlobals . insert ( GV ) ; unsigned OptimizationGoal ; if ( F . hasFnAttribute ( Attribute :: OptimizeNone ) ) OptimizationGoal = 6 ; else if ( F . optForMinSize ( ) ) OptimizationGoal = 4 ; else if ( F . optForSize ( ) ) OptimizationGoal = 3 ; else if ( TM . getOptLevel ( ) == CodeGenOpt :: Aggressive ) OptimizationGoal = 2 ; else if ( TM . getOptLevel ( ) > CodeGenOpt :: None ) OptimizationGoal = 1 ; else OptimizationGoal = 5 ; if ( OptimizationGoals == - 1 ) OptimizationGoals = OptimizationGoal ; else if ( OptimizationGoals != ( int ) OptimizationGoal ) OptimizationGoals = 0 ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = F . hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer -> EmitCOFFSymbolType ( Type ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; emitXRayTable ( ) ; if ( ! ThumbIndirectPads . empty ( ) ) { OutStreamer -> EmitAssemblerFlag ( MCAF_Code16 ) ; EmitAlignment ( 1 ) ; for ( std :: pair < unsigned , MCSymbol * > & TIP : ThumbIndirectPads ) { OutStreamer -> EmitLabel ( TIP . second ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( ARM :: tBX ) . addReg ( TIP . first ) . addImm ( ARMCC :: AL ) . addReg ( 0 ) ) ; } ThumbIndirectPads . clear ( ) ; } return false ; } </s>

runOnMachineFunction - Emit the function body .


"Memory locations not expected for call return"

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


"\t\tcvta.local.u%d %%r%d, %%simtstack_ar + "

Output code for allocating per-lane storage and switching soft-stack pointer . ENTERING indicates whether we are entering or leaving non-uniform execution . PTR is the register pointing to allocated storage , it is assigned to on entering and used to restore state on leaving . SIZE and ALIGN are used only on entering .


<s> void X86PassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & LiveRangeShrinkID ) ; addPass ( createX86FixupSetCC ( ) ) ; addPass ( createX86OptimizeLEAs ( ) ) ; addPass ( createX86CallFrameOptimization ( ) ) ; addPass ( createX86AvoidStoreForwardingBlocks ( ) ) ; } if ( EnableSpeculativeLoadHardening ) addPass ( createX86SpeculativeLoadHardeningPass ( ) ) ; addPass ( createX86FlagsCopyLoweringPass ( ) ) ; addPass ( createX86WinAllocaExpander ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static int ix86_multiplication_cost ( const struct processor_costs * cost , enum machine_mode mode ) { machine_mode inner_mode = mode ; if ( VECTOR_MODE_P ( mode ) ) inner_mode = GET_MODE_INNER ( mode ) ; if ( SSE_FLOAT_MODE_P ( mode ) && TARGET_SSE_MATH ) return inner_mode == DFmode ? cost -> mulsd : cost -> mulss ; else if ( X87_FLOAT_MODE_P ( mode ) ) return cost -> fmul ; else if ( FLOAT_MODE_P ( mode ) ) return ix86_vec_cost ( mode , inner_mode == DFmode ? cost -> mulsd : cost -> mulss , true ) ; else if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) { if ( TARGET_AVX512DQ ) return ix86_vec_cost ( mode , cost -> mulss , true ) ; if ( mode == V16QImode || mode == V32QImode ) { int extra = 11 ; if ( TARGET_XOP && mode == V16QImode ) extra = 5 ; else if ( TARGET_SSSE3 ) extra = 6 ; return ix86_vec_cost ( mode , cost -> mulss * 2 + cost -> sse_op * extra , true ) ; } else if ( mode == V2DImode || mode == V4DImode ) { if ( TARGET_XOP && mode == V2DImode ) return ix86_vec_cost ( mode , cost -> mulss * 2 + cost -> sse_op * 3 , true ) ; else return ix86_vec_cost ( mode , cost -> mulss * 3 + cost -> sse_op * 5 , true ) ; } else if ( mode == V4SImode && ! ( TARGET_SSE4_1 || TARGET_AVX ) ) return ix86_vec_cost ( mode , cost -> mulss * 2 + cost -> sse_op * 5 , true ) ; else return ix86_vec_cost ( mode , cost -> mulss , true ) ; } else return ( cost -> mult_init [ MODE_INDEX ( mode ) ] + cost -> mult_bit * 7 ) ; } </s>


Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> void rs6000_split_signbit ( rtx dest , rtx src ) { machine_mode d_mode = GET_MODE ( dest ) ; machine_mode s_mode = GET_MODE ( src ) ; rtx dest_di = ( d_mode == DImode ) ? dest : gen_lowpart ( DImode , dest ) ; rtx shift_reg = dest_di ; gcc_assert ( FLOAT128_IEEE_P ( s_mode ) && TARGET_POWERPC64 ) ; if ( MEM_P ( src ) ) { rtx mem = ( WORDS_BIG_ENDIAN ? adjust_address ( src , DImode , 0 ) : adjust_address ( src , DImode , 8 ) ) ; emit_insn ( gen_rtx_SET ( dest_di , mem ) ) ; } else { unsigned int r = reg_or_subregno ( src ) ; if ( INT_REGNO_P ( r ) ) shift_reg = gen_rtx_REG ( DImode , r + ( BYTES_BIG_ENDIAN == 0 ) ) ; else { gcc_assert ( VSX_REGNO_P ( r ) ) ; if ( s_mode == KFmode ) emit_insn ( gen_signbitkf2_dm2 ( dest_di , src ) ) ; else emit_insn ( gen_signbittf2_dm2 ( dest_di , src ) ) ; } } emit_insn ( gen_lshrdi3 ( dest_di , shift_reg , GEN_INT ( 63 ) ) ) ; return ; } </s>

Split a signbit operation on 64-bit machines with direct move . Also allow for the value to come from memory or if it is already loaded into a GPR .


<s> bool empty ( ) const { return Edges . empty ( ) ; } </s>

Determine whether this version information is empty ( e.g. , all version components are zero ) .


<s> unsigned SIInstrInfo :: getNumWaitStates ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { default : if ( MI . isMetaInstruction ( ) ) return 0 ; return 1 ; case AMDGPU :: S_NOP : return MI . getOperand ( 0 ) . getImm ( ) + 1 ; case AMDGPU :: SI_MASKED_UNREACHABLE : case AMDGPU :: WAVE_BARRIER : return 0 ; } } </s>

Return the number of wait states that result from executing this instruction .


<s> unsigned XCoreTargetLowering :: getJumpTableEncoding ( ) const { return MachineJumpTableInfo :: EK_Inline ; } </s>

Return the entry encoding for a jump table in the current function .


<s> virtual const SparcRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static ChildIteratorType child_begin ( const NodeRef N ) { return N -> child_begin ( ) ; } </s>

nodes_iterator/begin/end - Allow iteration over all nodes in the graph


<s> void neon_lane_bounds ( rtx operand , HOST_WIDE_INT low , HOST_WIDE_INT high , const_tree exp ) { bounds_check ( operand , low , high , exp , "lane" ) ; } </s>


<s> static HOST_WIDE_INT round_frame_size ( HOST_WIDE_INT size ) { return ( ( size + STACK_BOUNDARY / BITS_PER_UNIT - 1 ) & - STACK_BOUNDARY / BITS_PER_UNIT ) ; } </s>


<s> static int tilepro_pic_address_needs_scratch ( rtx x ) { if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && ( GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == SYMBOL_REF || GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == LABEL_REF ) && CONST_INT_P ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ) return true ; return false ; } </s>

Return true if X requires a scratch register . It is given that flag_pic is on and that X satisfies CONSTANT_P .


<s> static enum tls_model tls_symbolic_operand_type ( rtx addr ) { enum tls_model tls_kind = TLS_MODEL_NONE ; rtx sym , addend ; if ( GET_CODE ( addr ) == CONST ) { split_const ( addr , & sym , & addend ) ; if ( GET_CODE ( sym ) == SYMBOL_REF ) tls_kind = SYMBOL_REF_TLS_MODEL ( sym ) ; } else if ( GET_CODE ( addr ) == SYMBOL_REF ) tls_kind = SYMBOL_REF_TLS_MODEL ( addr ) ; return tls_kind ; } </s>

Return the TLS model to use for SYMBOL .


<s> bool RISCVAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == ".option" ) return parseDirectiveOption ( ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> unsigned getNumFixupKinds ( ) const override { return UPT :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> bool PPCInstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , const SmallVectorImpl < MachineOperand > & Cond , unsigned TrueReg , unsigned FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( ! TM . getSubtargetImpl ( ) -> hasISEL ( ) ) return false ; if ( Cond . size ( ) != 2 ) return false ; if ( Cond [ 1 ] . getReg ( ) == PPC :: CTR || Cond [ 1 ] . getReg ( ) == PPC :: CTR8 ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( ! PPC :: GPRCRegClass . hasSubClassEq ( RC ) && ! PPC :: GPRC_NOR0RegClass . hasSubClassEq ( RC ) && ! PPC :: G8RCRegClass . hasSubClassEq ( RC ) && ! PPC :: G8RC_NOX0RegClass . hasSubClassEq ( RC ) ) return false ; CondCycles = 1 ; TrueCycles = 1 ; FalseCycles = 1 ; return true ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> RegisterAggr & RegisterAggr :: clear ( const RegisterAggr & RG ) { for ( std :: pair < RegisterId , LaneBitmask > P : RG . Masks ) clear ( RegisterRef ( P . first , P . second ) ) ; return * this ; } </s>


<s> const TargetRegisterClass * SITargetLowering :: getRegClassFor ( MVT VT , bool isDivergent ) const { const TargetRegisterClass * RC = TargetLoweringBase :: getRegClassFor ( VT , false ) ; const SIRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; if ( RC == & AMDGPU :: VReg_1RegClass && ! isDivergent ) return & AMDGPU :: SReg_64RegClass ; if ( ! TRI -> isSGPRClass ( RC ) && ! isDivergent ) return TRI -> getEquivalentSGPRClass ( RC ) ; else if ( TRI -> isSGPRClass ( RC ) && isDivergent ) return TRI -> getEquivalentVGPRClass ( RC ) ; return RC ; } </s>

Return the register class that should be used for the specified value type .


<s> static rtx frv_expand_store_builtin ( enum insn_code icode , tree call ) { rtx op0 = frv_read_argument ( call , 0 ) ; rtx op1 = frv_read_argument ( call , 1 ) ; rtx cookie = frv_io_address_cookie ( op0 ) ; op0 = frv_volatile_memref ( insn_data [ icode ] . operand [ 0 ] . mode , op0 ) ; convert_move ( op0 , force_reg ( insn_data [ icode ] . operand [ 0 ] . mode , op1 ) , 1 ) ; emit_insn ( GEN_FCN ( icode ) ( copy_rtx ( op0 ) , cookie , GEN_INT ( FRV_IO_WRITE ) ) ) ; cfun -> machine -> has_membar_p = 1 ; return NULL_RTX ; } </s>


<s> void aarch64_swap_ldrstr_operands ( rtx * operands , bool load ) { rtx mem_1 , mem_2 , base_1 , base_2 , offset_1 , offset_2 ; HOST_WIDE_INT offval_1 , offval_2 ; if ( load ) { mem_1 = operands [ 1 ] ; mem_2 = operands [ 3 ] ; } else { mem_1 = operands [ 0 ] ; mem_2 = operands [ 2 ] ; } extract_base_offset_in_addr ( mem_1 , & base_1 , & offset_1 ) ; extract_base_offset_in_addr ( mem_2 , & base_2 , & offset_2 ) ; offval_1 = INTVAL ( offset_1 ) ; offval_2 = INTVAL ( offset_2 ) ; if ( offval_1 > offval_2 ) { std :: swap ( operands [ 0 ] , operands [ 2 ] ) ; std :: swap ( operands [ 1 ] , operands [ 3 ] ) ; } } </s>

Given OPERANDS of consecutive load/store that can be merged , swap them if they are not in ascending order .


"SIInstrInfo::loadRegFromStackSlot - Do not know how to"

Load the specified register of the given register class from the specified stack frame index .


"-max-stackframe=%d is not usable, not between 0 and %d"

"unknown CRIS version specification in -march= or -mcpu= : %s"

"unknown CRIS cpu version specification in -mtune= : %s"

"-fPIC and -fpic are not supported in this configuration"

The TARGET_OPTION_OVERRIDE worker . As is the norm , this also parses -mfoo=bar type parameters .


<s> static void vax_init_libfuncs ( void ) { set_optab_libfunc ( udiv_optab , SImode , TARGET_ELF ? "*__udiv" : "*udiv" ) ; set_optab_libfunc ( umod_optab , SImode , TARGET_ELF ? "*__urem" : "*urem" ) ; } </s>

We can use the BSD C library routines for the libgcc calls that are still generated , since that 's what they boil down to anyways . When ELF , avoid the user 's namespace .


<s> static void pa_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int arg_size = FUNCTION_ARG_SIZE ( mode , type ) ; cum -> nargs_prototype -- ; cum -> words += ( arg_size + ( ( cum -> words & 01 ) && type != NULL_TREE && arg_size > 1 ) ) ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> void ARMDAGToDAGISel :: PreprocessISelDAG ( ) { if ( ! Subtarget -> hasV6T2Ops ( ) ) return ; bool isThumb2 = Subtarget -> isThumb ( ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( N -> getOpcode ( ) != ISD :: ADD ) continue ; SDValue N0 = N -> getOperand ( 0 ) ; SDValue N1 = N -> getOperand ( 1 ) ; unsigned And_imm = 0 ; if ( ! isOpcWithIntImmediate ( N1 . getNode ( ) , ISD :: AND , And_imm ) ) { if ( isOpcWithIntImmediate ( N0 . getNode ( ) , ISD :: AND , And_imm ) ) std :: swap ( N0 , N1 ) ; } if ( ! And_imm ) continue ; unsigned TZ = countTrailingZeros ( And_imm ) ; if ( TZ != 1 && TZ != 2 ) continue ; And_imm >>= TZ ; if ( And_imm & ( And_imm + 1 ) ) continue ; SDValue Srl = N1 . getOperand ( 0 ) ; unsigned Srl_imm = 0 ; if ( ! isOpcWithIntImmediate ( Srl . getNode ( ) , ISD :: SRL , Srl_imm ) || ( Srl_imm <= 2 ) ) continue ; SDValue CPTmp0 ; SDValue CPTmp1 ; SDValue CPTmp2 ; if ( isThumb2 ) { if ( SelectT2ShifterOperandReg ( N0 , CPTmp0 , CPTmp1 ) ) continue ; } else { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) || SelectRegShifterOperand ( N0 , CPTmp0 , CPTmp1 , CPTmp2 ) ) continue ; } Srl = CurDAG -> getNode ( ISD :: SRL , SDLoc ( Srl ) , MVT :: i32 , Srl . getOperand ( 0 ) , CurDAG -> getConstant ( Srl_imm + TZ , SDLoc ( Srl ) , MVT :: i32 ) ) ; N1 = CurDAG -> getNode ( ISD :: AND , SDLoc ( N1 ) , MVT :: i32 , Srl , CurDAG -> getConstant ( And_imm , SDLoc ( Srl ) , MVT :: i32 ) ) ; N1 = CurDAG -> getNode ( ISD :: SHL , SDLoc ( N1 ) , MVT :: i32 , N1 , CurDAG -> getConstant ( TZ , SDLoc ( Srl ) , MVT :: i32 ) ) ; CurDAG -> UpdateNodeOperands ( N , N0 , N1 ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> void TGSIAsmPrinter :: EmitInstruction ( const MachineInstr * mi ) { MCInst mci ; LowerMachineInstrToMCInst ( mi , mci , * this ) ; EmitMCInstruction ( mci ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"WebAssembly Register Stackify"
;
}
</s>

getPassName - Return a nice clean name for a pass .

WebAssembly
"WebAssembly Register Stackify"


<s> const TargetRegisterClass * MCS51RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & MCS51 :: PTRDISPREGSRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> void rs6000_expand_vector_extract ( rtx target , rtx vec , int elt ) { machine_mode mode = GET_MODE ( vec ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx mem ; if ( VECTOR_MEM_VSX_P ( mode ) ) { switch ( mode ) { default : break ; case V1TImode : gcc_assert ( elt == 0 && inner_mode == TImode ) ; emit_move_insn ( target , gen_lowpart ( TImode , vec ) ) ; break ; case V2DFmode : emit_insn ( gen_vsx_extract_v2df ( target , vec , GEN_INT ( elt ) ) ) ; return ; case V2DImode : emit_insn ( gen_vsx_extract_v2di ( target , vec , GEN_INT ( elt ) ) ) ; return ; case V4SFmode : emit_insn ( gen_vsx_extract_v4sf ( target , vec , GEN_INT ( elt ) ) ) ; return ; } } mem = assign_stack_temp ( mode , GET_MODE_SIZE ( mode ) ) ; emit_move_insn ( mem , vec ) ; mem = adjust_address_nv ( mem , inner_mode , elt * GET_MODE_SIZE ( inner_mode ) ) ; emit_move_insn ( target , adjust_address_nv ( mem , inner_mode , 0 ) ) ; } </s>

Extract field ELT from VEC into TARGET .


<s> Register getExceptionPointerRegister ( const Constant * PersonalityFn ) const override { return SystemZ :: R6D ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s>
void
rs6000_xcoff_declare_function_name
(
FILE
*
file
,
const
char
*
name
,
tree
decl
)
{
char
*
buffer
=
(
char
*
)
alloca
(
strlen
(
name
)
+
1
)
;
char
*
p
;
int
dollar_inside
=
0
;
struct
declare_alias_data
data
=
{
file
,
false
}
;
strcpy
(
buffer
,
name
)
;
p
=
strchr
(
buffer
,
'$'
)
;
while
(
p
)
{
*
p
=
'_'
;
dollar_inside
++
;
p
=
strchr
(
p
+
1
,
'$'
)
;
}
if
(
TREE_PUBLIC
(
decl
)
)
{
if
(
!
RS6000_WEAK
||
!
DECL_WEAK
(
decl
)
)
{
if
(
dollar_inside
)
{
fprintf
(
file
,
"\t.rename .%s,\".%s\"\n"
,
buffer
,
name
)
;
fprintf
(
file
,
"\t.rename %s,\"%s\"\n"
,
buffer
,
name
)
;
}
fputs
(
"\t.globl ."
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
fputs
(
rs6000_xcoff_visibility
(
decl
)
,
file
)
;
putc
(
'\n'
,
file
)
;
}
}
else
{
if
(
dollar_inside
)
{
fprintf
(
file
,
"\t.rename .%s,\".%s\"\n"
,
buffer
,
name
)
;
fprintf
(
file
,
"\t.rename %s,\"%s\"\n"
,
buffer
,
name
)
;
}
fputs
(
"\t.lglobl ."
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
putc
(
'\n'
,
file
)
;
}
fputs
(
"\t.csect "
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
fputs
(
TARGET_32BIT
"[DS]\n"
:
"[DS],3\n"
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
fputs
(
":\n"
,
file
)
;
symtab_node
::
get
(
decl
)
->
call_for_symbol_and_aliases
(
rs6000_declare_alias
,
&
data
,
true
)
;
fputs
(
TARGET_32BIT
"\t.long ."
:
"\t.llong ."
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
fputs
(
", TOC[tc0], 0\n"
,
file
)
;
in_section
=
;
switch_to_section
(
function_section
(
decl
)
)
;
putc
(
'.'
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
fputs
(
":\n"
,
file
)
;
data
.
function_descriptor
=
true
;
symtab_node
::
get
(
decl
)
->
call_for_symbol_and_aliases
(
rs6000_declare_alias
,
&
data
,
true
)
;
if
(
!
DECL_IGNORED_P
(
decl
)
)
{
if
(
write_symbols
==
DBX_DEBUG
||
write_symbols
==
XCOFF_DEBUG
)
xcoffout_declare_function
(
file
,
decl
,
buffer
)
;
else
if
(
write_symbols
==
DWARF2_DEBUG
)
{
name
=
(
*
targetm
.
strip_name_encoding
)
(
name
)
;
fprintf
(
file
,
"\t.function .%s,.%s,2,0\n"
,
name
,
name
)
;
}
}
return
;
}
</s>

This macro produces the initial definition of a function name . On the RS/6000 , we need to place an extra ' . ' in the function name and output the function descriptor . Dollar signs are converted to underscores . The csect for the function will have already been created when text_section was selected . We do have to go back to that csect , however . The third and fourth parameters to the .function pseudo-op ( 16 and 044 ) are placeholders which no longer have any use . Because AIX assembler 's .set command has unexpected semantics , we output all aliases as alternative labels in front of the definition .


<s> void X86IntelInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; unsigned Flags = MI -> getFlags ( ) ; if ( ( TSFlags & X86II :: LOCK ) || ( Flags & X86 :: IP_HAS_LOCK ) ) OS << "\tlock\t" ; if ( Flags & X86 :: IP_HAS_REPEAT_NE ) OS << "\trepne\t" ; else if ( Flags & X86 :: IP_HAS_REPEAT ) OS << "\trep\t" ; if ( ( TSFlags & X86II :: NOTRACK ) || ( Flags & X86 :: IP_HAS_NOTRACK ) ) OS << "\tnotrack\t" ; printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAnyX86InstComments ( MI , * CommentStream , MII , getRegisterName ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static bool callee_saved_regno_p ( int regno ) { if ( ! call_used_regs [ regno ] && df_regs_ever_live_p ( regno ) ) return true ; switch ( regno ) { case HARD_FRAME_POINTER_REGNUM : return frame_pointer_needed ; case LR_REGNUM : return ( frame_pointer_needed || ! crtl -> is_leaf || crtl -> uses_pic_offset_table || df_regs_ever_live_p ( regno ) ) ; case HW_TO_GCC_REGNO ( 25 ) : case HW_TO_GCC_REGNO ( 27 ) : case HW_TO_GCC_REGNO ( 29 ) : case HW_TO_GCC_REGNO ( 31 ) : return crtl -> calls_eh_return ; default : return false ; } } </s>

Returns true if REGNO must be saved for the current function .


<s> const std :: string getAsStr ( ) const override { return "AMDInfo[" + std :: to_string ( Attributes . size ( ) ) + "]" ; } </s>

See AbstractState : :getAsStr ( Attributor ) .


<s> static scalar_int_mode pru_unwind_word_mode ( void ) { return SImode ; } </s>

Implement TARGET_UNWIND_WORD_MODE . Since PRU is really a 32-bit CPU , the default word_mode is not suitable .


<s> bool runOnMachineFunction ( MachineFunction & F ) override { TM = & F . getTarget ( ) ; bool Changed = false ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; if ( Changed ) F . getRegInfo ( ) . invalidateLiveness ( ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> SDNode * BlackfinDAGToDAGISel :: Select ( SDNode * N ) { if ( N -> isMachineOpcode ( ) ) return NULL ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: FrameIndex : { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , MVT :: i32 ) ; return CurDAG -> SelectNodeTo ( N , BF :: ADDpp , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , MVT :: i32 ) ) ; } } return SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> void initializePass ( ) override { pushTTIStack ( this ) ; } </s>

initializePass - This method may be overriden by immutable passes to allow them to perform various initialization actions they require .


<s> void GCNPassConfig :: addFastRegAlloc ( ) { insertPass ( & PHIEliminationID , & SILowerControlFlowID , false ) ; insertPass ( & TwoAddressInstructionPassID , & SIWholeQuadModeID ) ; insertPass ( & TwoAddressInstructionPassID , & SIPreAllocateWWMRegsID ) ; TargetPassConfig :: addFastRegAlloc ( ) ; } </s>

addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast register allocation .


<s>
enum
calling_abi
ix86_function_type_abi
(
const_tree
fntype
)
{
enum
calling_abi
abi
=
ix86_abi
;
if
(
fntype
==
NULL_TREE
||
TYPE_ATTRIBUTES
(
fntype
)
==
NULL_TREE
)
return
abi
;
if
(
abi
==
SYSV_ABI
&&
lookup_attribute
(
"ms_abi"
,
TYPE_ATTRIBUTES
(
fntype
)
)
)
{
if
(
TARGET_X32
)
error
(
"X32 does not support ms_abi attribute"
)
;
abi
=
MS_ABI
;
}
else
if
(
abi
==
MS_ABI
&&
lookup_attribute
(
"sysv_abi"
,
TYPE_ATTRIBUTES
(
fntype
)
)
)
abi
=
SYSV_ABI
;
return
abi
;
}
</s>

Returns value SYSV_ABI , MS_ABI dependent on fntype , specifying the call abi used .


<s> static const predefined_function_abi & aarch64_sve_abi ( void ) { predefined_function_abi & sve_abi = function_abis [ ARM_PCS_SVE ] ; if ( ! sve_abi . initialized_p ( ) ) { HARD_REG_SET full_reg_clobbers = default_function_abi . full_reg_clobbers ( ) ; for ( int regno = V8_REGNUM ; regno <= V23_REGNUM ; ++ regno ) CLEAR_HARD_REG_BIT ( full_reg_clobbers , regno ) ; for ( int regno = P4_REGNUM ; regno <= P15_REGNUM ; ++ regno ) CLEAR_HARD_REG_BIT ( full_reg_clobbers , regno ) ; sve_abi . initialize ( ARM_PCS_SVE , full_reg_clobbers ) ; } return sve_abi ; } </s>


"instruction requires a CPU feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> bool DeadCodeElimination :: isDead ( unsigned R ) const { for ( auto I = MRI . use_begin ( R ) , E = MRI . use_end ( ) ; I != E ; ++ I ) { MachineInstr * UseI = I -> getParent ( ) ; if ( UseI -> isDebugValue ( ) ) continue ; if ( UseI -> isPHI ( ) ) { assert ( ! UseI -> getOperand ( 0 ) . getSubReg ( ) ) ; Register DR = UseI -> getOperand ( 0 ) . getReg ( ) ; if ( DR == R ) continue ; } return false ; } return true ; } </s>

isDead - Returns true if this is a dead def kill slot .


"Encoding of this operand type is not supported yet."

getMachineOpValue - Return binary encoding of operand .


<s>
bool
PPCInstrInfo
::
FoldImmediate
(
MachineInstr
&
UseMI
,
MachineInstr
&
DefMI
,
Register
Reg
,
MachineRegisterInfo
*
MRI
)
const
{
unsigned
DefOpc
=
DefMI
.
getOpcode
(
)
;
if
(
DefOpc
!=
PPC
::
LI
&&
DefOpc
!=
PPC
::
LI8
)
return
false
;
if
(
!
DefMI
.
getOperand
(
1
)
.
isImm
(
)
)
return
false
;
if
(
DefMI
.
getOperand
(
1
)
.
getImm
(
)
!=
0
)
return
false
;
const
MCInstrDesc
&
UseMCID
=
UseMI
.
getDesc
(
)
;
if
(
UseMCID
.
isPseudo
(
)
)
return
false
;
unsigned
UseIdx
;
for
(
UseIdx
=
0
;
UseIdx
<
UseMI
.
getNumOperands
(
)
;
++
UseIdx
)
if
(
UseMI
.
getOperand
(
UseIdx
)
.
isReg
(
)
&&
UseMI
.
getOperand
(
UseIdx
)
.
getReg
(
)
==
Reg
)
break
;
assert
(
UseIdx
<
UseMI
.
getNumOperands
(
)
&&
"Cannot find Reg in UseMI"
)
;
assert
(
UseIdx
<
UseMCID
.
getNumOperands
(
)
&&
"No operand description for Reg"
)
;
const
MCOperandInfo
*
UseInfo
=
&
UseMCID
.
OpInfo
[
UseIdx
]
;
if
(
UseInfo
->
isLookupPtrRegClass
(
)
)
{
if
(
UseInfo
->
RegClass
!=
1
)
return
false
;
}
else
{
if
(
UseInfo
->
RegClass
!=
PPC
::
GPRC_NOR0RegClassID
&&
UseInfo
->
RegClass
!=
PPC
::
G8RC_NOX0RegClassID
)
return
false
;
}
if
(
UseInfo
->
Constraints
!=
0
)
return
false
;
MCRegister
ZeroReg
;
if
(
UseInfo
->
isLookupPtrRegClass
(
)
)
{
bool
isPPC64
=
Subtarget
.
isPPC64
(
)
;
ZeroReg
=
isPPC64
PPC
::
ZERO8
:
PPC
::
ZERO
;
}
else
{
ZeroReg
=
UseInfo
->
RegClass
==
PPC
::
G8RC_NOX0RegClassID
PPC
::
ZERO8
:
PPC
::
ZERO
;
}
bool
DeleteDef
=
MRI
->
hasOneNonDBGUse
(
Reg
)
;
UseMI
.
getOperand
(
UseIdx
)
.
setReg
(
ZeroReg
)
;
if
(
DeleteDef
)
DefMI
.
eraseFromParent
(
)
;
return
true
;
}
</s>

Reg is known to be defined by a move immediate instruction , try to fold the immediate into the use instruction .


"Hexagon relaxInstruction only works on bundles"

"No room to insert extender for relaxation"

Relax the instruction in the given fragment to the next wider instruction .


<s>
SDValue
XCoreTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_XCore
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
if
(
RVLocs
[
i
]
.
isRegLoc
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
Outs
[
i
]
.
Val
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
XCoreISD
::
RETSP
,
dl
,
MVT
::
Other
,
Chain
,
DAG
.
getConstant
(
0
,
MVT
::
i32
)
,
Flag
)
;
else
return
DAG
.
getNode
(
XCoreISD
::
RETSP
,
dl
,
MVT
::
Other
,
Chain
,
DAG
.
getConstant
(
0
,
MVT
::
i32
)
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> virtual const DCPU16InstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> bool XCoreAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , O ) ; } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> std :: pair < uint16_t , uint16_t > X86InstrInfo :: getExecutionDomain ( const MachineInstr & MI ) const { uint16_t domain = ( MI . getDesc ( ) . TSFlags >> X86II :: SSEDomainShift ) & 3 ; unsigned opcode = MI . getOpcode ( ) ; uint16_t validDomains = 0 ; if ( domain ) { if ( lookup ( MI . getOpcode ( ) , domain , ReplaceableInstrs ) ) { validDomains = 0xe ; } else if ( lookup ( opcode , domain , ReplaceableInstrsAVX2 ) ) { validDomains = Subtarget . hasAVX2 ( ) ? 0xe : 0x6 ; } else if ( lookupAVX512 ( opcode , domain , ReplaceableInstrsAVX512 ) ) { validDomains = 0xe ; } else if ( lookupAVX512 ( opcode , domain , ReplaceableInstrsAVX512DQ ) ) { validDomains = Subtarget . hasDQI ( ) ? 0xe : 0x8 ; } else if ( const uint16_t * table = lookupAVX512 ( opcode , domain , ReplaceableInstrsAVX512DQMasked ) ) { if ( domain == 1 || ( domain == 3 && table [ 3 ] == opcode ) ) validDomains = Subtarget . hasDQI ( ) ? 0xa : 0x8 ; else validDomains = Subtarget . hasDQI ( ) ? 0xc : 0x8 ; } } return std :: make_pair ( domain , validDomains ) ; } </s>

Return the current execution domain and bit mask of possible domains for instruction .


<s> unsigned LEGInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { assert ( 0 && "Unimplemented" ) ; return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> static bool symbol_p ( rtx x ) { int c = GET_CODE ( x ) ; return ( c == CONST_INT || c == CONST || c == SYMBOL_REF ) ; } </s>

MEP has very few instructions that can refer to the span of addresses used by symbols , so it 's common to check for them .


<s> static bool rs6000_secondary_reload_simple_move ( enum rs6000_reg_type to_type , enum rs6000_reg_type from_type , machine_mode mode ) { int size = GET_MODE_SIZE ( mode ) ; if ( TARGET_DIRECT_MOVE && ( ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) || ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) { if ( TARGET_POWERPC64 ) { if ( size == 8 ) return true ; if ( size == 16 && TARGET_P9_VECTOR && mode != TDmode ) return true ; } if ( TARGET_VSX_SMALL_INTEGER ) { if ( mode == SImode ) return true ; if ( TARGET_P9_VECTOR && ( mode == HImode || mode == QImode ) ) return true ; } if ( mode == SDmode ) return true ; } else if ( TARGET_MFPGPR && TARGET_POWERPC64 && size == 8 && ( ( to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE ) || ( to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; else if ( ( size == 4 || ( TARGET_POWERPC64 && size == 8 ) ) && ( ( to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE ) || ( to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; return false ; } </s>

Helper function for rs6000_secondary_reload to return true if a move to a different register classe is really a simple move .


<s> static inline int shiftcosts ( rtx x ) { if ( GET_MODE_SIZE ( GET_MODE ( x ) ) > UNITS_PER_WORD ) { if ( GET_MODE ( x ) == DImode && CONST_INT_P ( XEXP ( x , 1 ) ) && INTVAL ( XEXP ( x , 1 ) ) == 1 ) return 2 ; return - 1 ; } if ( ! CONST_INT_P ( XEXP ( x , 1 ) ) ) return SH_DYNAMIC_SHIFT_COST ; int value = INTVAL ( XEXP ( x , 1 ) ) & 31 ; if ( GET_CODE ( x ) == ASHIFTRT ) { int cost = ashiftrt_insns [ value ] ; if ( cost > 1 + SH_DYNAMIC_SHIFT_COST ) cost = 1 + SH_DYNAMIC_SHIFT_COST ; return cost ; } else return ashl_lshr_seq [ value ] . insn_count ; } </s>


<s> bool NVPTXPassConfig :: addInstSelector ( ) { addPass ( createLowerAggrCopies ( ) ) ; addPass ( createSplitBBatBarPass ( ) ) ; addPass ( createAllocaHoisting ( ) ) ; addPass ( createNVPTXISelDag ( getNVPTXTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static bool aarch64_returns_value_in_sve_regs_p ( const_tree fntype ) { tree return_type = TREE_TYPE ( fntype ) ; pure_scalable_type_info pst_info ; switch ( pst_info . analyze ( return_type ) ) { case pure_scalable_type_info :: IS_PST : return ( pst_info . num_zr ( ) <= NUM_FP_ARG_REGS && pst_info . num_pr ( ) <= NUM_PR_ARG_REGS ) ; case pure_scalable_type_info :: DOESNT_MATTER : gcc_assert ( aarch64_return_in_memory_1 ( return_type ) ) ; return false ; case pure_scalable_type_info :: NO_ABI_IDENTITY : case pure_scalable_type_info :: ISNT_PST : return false ; } gcc_unreachable ( ) ; } </s>

Return true if a function with type FNTYPE returns its value in SVE vector or predicate registers .


getTargetNodeName - This method returns the name of a target specific


<s>
bool
SystemZAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
;
MatchResult
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MatchingInlineAsm
)
;
switch
(
MatchResult
)
{
default
:
break
;
case
Match_Success
:
Inst
.
setLoc
(
IDLoc
)
;
Out
.
EmitInstruction
(
Inst
,
STI
)
;
return
false
;
case
Match_MissingFeature
:
{
assert
(
ErrorInfo
&&
"Unknown missing feature!"
)
;
std
::
string
Msg
=
"instruction requires:"
;
uint64_t
Mask
=
1
;
for
(
unsigned
I
=
0
;
I
<
sizeof
(
ErrorInfo
)
*
8
1
;
++
I
)
{
if
(
ErrorInfo
&
Mask
)
{
Msg
+=
" "
;
Msg
+=
getSubtargetFeatureName
(
ErrorInfo
&
Mask
)
;
}
Mask
<<=
1
;
}
return
Error
(
IDLoc
,
Msg
)
;
}
case
Match_InvalidOperand
:
{
SMLoc
ErrorLoc
=
IDLoc
;
if
(
ErrorInfo
!=
~
0ULL
)
{
if
(
ErrorInfo
>=
Operands
.
size
(
)
)
return
Error
(
IDLoc
,
"too few operands for instruction"
)
;
ErrorLoc
=
(
(
SystemZOperand
&
)
*
Operands
[
ErrorInfo
]
)
.
getStartLoc
(
)
;
if
(
ErrorLoc
==
SMLoc
(
)
)
ErrorLoc
=
IDLoc
;
}
return
Error
(
ErrorLoc
,
"invalid operand for instruction"
)
;
}
case
Match_MnemonicFail
:
return
Error
(
IDLoc
,
"invalid instruction"
)
;
}
llvm_unreachable
(
"Unexpected match type"
)
;
}
</s>


<s> static tree rs6000_builtin_vectorized_libmass ( combined_fn fn , tree type_out , tree type_in ) { char name [ 32 ] ; const char * suffix = NULL ; tree fntype , new_fndecl , bdecl = NULL_TREE ; int n_args = 1 ; const char * bname ; machine_mode el_mode , in_mode ; int n , in_n ; if ( ! flag_unsafe_math_optimizations || ! TARGET_VSX ) return NULL_TREE ; el_mode = TYPE_MODE ( TREE_TYPE ( type_out ) ) ; n = TYPE_VECTOR_SUBPARTS ( type_out ) ; in_mode = TYPE_MODE ( TREE_TYPE ( type_in ) ) ; in_n = TYPE_VECTOR_SUBPARTS ( type_in ) ; if ( el_mode != in_mode || n != in_n ) return NULL_TREE ; switch ( fn ) { CASE_CFN_ATAN2 : CASE_CFN_HYPOT : CASE_CFN_POW : n_args = 2 ; gcc_fallthrough ( ) ; CASE_CFN_ACOS : CASE_CFN_ACOSH : CASE_CFN_ASIN : CASE_CFN_ASINH : CASE_CFN_ATAN : CASE_CFN_ATANH : CASE_CFN_CBRT : CASE_CFN_COS : CASE_CFN_COSH : CASE_CFN_ERF : CASE_CFN_ERFC : CASE_CFN_EXP2 : CASE_CFN_EXP : CASE_CFN_EXPM1 : CASE_CFN_LGAMMA : CASE_CFN_LOG10 : CASE_CFN_LOG1P : CASE_CFN_LOG2 : CASE_CFN_LOG : CASE_CFN_SIN : CASE_CFN_SINH : CASE_CFN_SQRT : CASE_CFN_TAN : CASE_CFN_TANH : if ( el_mode == DFmode && n == 2 ) { bdecl = mathfn_built_in ( double_type_node , fn ) ; suffix = "d2" ; } else if ( el_mode == SFmode && n == 4 ) { bdecl = mathfn_built_in ( float_type_node , fn ) ; suffix = "4" ; } else return NULL_TREE ; if ( ! bdecl ) return NULL_TREE ; break ; default : return NULL_TREE ; } gcc_assert ( suffix != NULL ) ; bname = IDENTIFIER_POINTER ( DECL_NAME ( bdecl ) ) ; if ( ! bname ) return NULL_TREE ; strcpy ( name , bname + sizeof ( "__builtin_" ) - 1 ) ; strcat ( name , suffix ) ; if ( n_args == 1 ) fntype = build_function_type_list ( type_out , type_in , NULL ) ; else if ( n_args == 2 ) fntype = build_function_type_list ( type_out , type_in , type_in , NULL ) ; else gcc_unreachable ( ) ; new_fndecl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , fntype ) ; TREE_PUBLIC ( new_fndecl ) = 1 ; DECL_EXTERNAL ( new_fndecl ) = 1 ; DECL_IS_NOVOPS ( new_fndecl ) = 1 ; TREE_READONLY ( new_fndecl ) = 1 ; return new_fndecl ; } </s>

Handler for the Mathematical Acceleration Subsystem ( mass ) interface to a library with vectorized intrinsics .


<s> void sparc_expand_epilogue ( bool for_eh ) { HOST_WIDE_INT size = sparc_frame_size ; if ( cfun -> calls_alloca ) emit_insn ( gen_frame_blockage ( ) ) ; if ( sparc_n_global_fp_regs > 0 ) emit_save_or_restore_global_fp_regs ( sparc_frame_base_reg , sparc_frame_base_offset - sparc_apparent_frame_size , SORR_RESTORE ) ; if ( size == 0 || for_eh ) ; else if ( sparc_leaf_function_p ) { if ( size <= 4096 ) emit_insn ( gen_stack_pointer_inc ( GEN_INT ( size ) ) ) ; else if ( size <= 8192 ) { emit_insn ( gen_stack_pointer_inc ( GEN_INT ( 4096 ) ) ) ; emit_insn ( gen_stack_pointer_inc ( GEN_INT ( size - 4096 ) ) ) ; } else { rtx reg = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( reg , GEN_INT ( size ) ) ; emit_insn ( gen_stack_pointer_inc ( reg ) ) ; } } } </s>

Expand the function epilogue , either normal or part of a sibcall . We emit all the instructions except the return or the call .


<s> void SystemZAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { SystemZMCInstLower Lower ( Mang , MF -> getContext ( ) , * this ) ; MCInst LoweredMI ; switch ( MI -> getOpcode ( ) ) { case SystemZ :: Return : LoweredMI = MCInstBuilder ( SystemZ :: BR ) . addReg ( SystemZ :: R14D ) ; break ; case SystemZ :: CallBRASL : LoweredMI = MCInstBuilder ( SystemZ :: BRASL ) . addReg ( SystemZ :: R14D ) . addExpr ( Lower . getExpr ( MI -> getOperand ( 0 ) , MCSymbolRefExpr :: VK_PLT ) ) ; break ; case SystemZ :: CallBASR : LoweredMI = MCInstBuilder ( SystemZ :: BASR ) . addReg ( SystemZ :: R14D ) . addReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ; break ; case SystemZ :: CallJG : LoweredMI = MCInstBuilder ( SystemZ :: JG ) . addExpr ( Lower . getExpr ( MI -> getOperand ( 0 ) , MCSymbolRefExpr :: VK_PLT ) ) ; break ; case SystemZ :: CallBR : LoweredMI = MCInstBuilder ( SystemZ :: BR ) . addReg ( SystemZ :: R1D ) ; break ; case SystemZ :: IILF64 : LoweredMI = MCInstBuilder ( SystemZ :: IILF ) . addReg ( SystemZMC :: getRegAsGR32 ( MI -> getOperand ( 0 ) . getReg ( ) ) ) . addImm ( MI -> getOperand ( 2 ) . getImm ( ) ) ; break ; case SystemZ :: IIHF64 : LoweredMI = MCInstBuilder ( SystemZ :: IIHF ) . addReg ( SystemZMC :: getRegAsGRH32 ( MI -> getOperand ( 0 ) . getReg ( ) ) ) . addImm ( MI -> getOperand ( 2 ) . getImm ( ) ) ; break ; case SystemZ :: RISBHH : case SystemZ :: RISBHL : LoweredMI = lowerRIEfLow ( MI , SystemZ :: RISBHG ) ; break ; case SystemZ :: RISBLH : case SystemZ :: RISBLL : LoweredMI = lowerRIEfLow ( MI , SystemZ :: RISBLG ) ; break ; case SystemZ :: NAME ## 64 : LoweredMI = lowerRILow ( MI , SystemZ :: NAME ) ; break LOWER_LOW ( IILL ) ; LOWER_LOW ( IILH ) ; LOWER_LOW ( NILL ) ; LOWER_LOW ( NILH ) ; LOWER_LOW ( NILF ) ; LOWER_LOW ( OILL ) ; LOWER_LOW ( OILH ) ; LOWER_LOW ( OILF ) ; LOWER_LOW ( XILF ) ; case SystemZ :: NAME ## 64 : LoweredMI = lowerRIHigh ( MI , SystemZ :: NAME ) ; break LOWER_HIGH ( IIHL ) ; LOWER_HIGH ( IIHH ) ; LOWER_HIGH ( NIHL ) ; LOWER_HIGH ( NIHH ) ; LOWER_HIGH ( NIHF ) ; LOWER_HIGH ( OIHL ) ; LOWER_HIGH ( OIHH ) ; LOWER_HIGH ( OIHF ) ; LOWER_HIGH ( XIHF ) ; default : Lower . lower ( MI , LoweredMI ) ; break ; } OutStreamer . EmitInstruction ( LoweredMI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { TargetTransformInfo :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> MCELFStreamer & getStreamer ( ) { return static_cast < MCELFStreamer & > ( Streamer ) ; } </s>

Return the output streamer for the assembler .


<s> static void ix86_adjust_counter ( rtx countreg , HOST_WIDE_INT value ) { rtx ( * gen_add ) ( rtx , rtx , rtx ) = GET_MODE ( countreg ) == DImode ? gen_adddi3 : gen_addsi3 ; emit_insn ( gen_add ( countreg , countreg , GEN_INT ( - value ) ) ) ; } </s>


<s>
void
MipsDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
if
(
trySelect
(
Node
)
)
return
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
ADD
:
if
(
Node
->
getSimpleValueType
(
0
)
.
isVector
(
)
&&
selectVecAddAsVecSubIfProfitable
(
Node
)
)
return
;
break
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
ReplaceNode
(
Node
,
getGlobalBaseReg
(
)
)
;
return
;
case
ISD
::
LOAD
:
case
ISD
::
STORE
:
assert
(
(
Subtarget
->
systemSupportsUnalignedAccess
(
)
||
cast
<
MemSDNode
>
(
Node
)
->
getMemoryVT
(
)
.
getSizeInBits
(
)
/
8
<=
cast
<
MemSDNode
>
(
Node
)
->
getAlignment
(
)
)
&&
"Unexpected unaligned loads/stores."
)
;
break
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

Mips
Mips
"== "
"\n"
1
ISD::ADD
0
ISD::GLOBAL_OFFSET_TABLE
ISD::LOAD
ISD::STORE
8
"Unexpected unaligned loads/stores."


<s>
void
ATTRIBUTE_UNUSED
ix86_debug_options
(
void
)
{
char
*
opts
=
ix86_target_string
(
ix86_isa_flags
,
ix86_isa_flags2
,
target_flags
,
ix86_target_flags
,
ix86_arch_string
,
ix86_tune_string
,
ix86_fpmath
,
true
)
;
if
(
opts
)
{
fprintf
(
stderr
,
"%s\n\n"
,
opts
)
;
free
(
opts
)
;
}
else
fputs
(
"<no options>\n\n"
,
stderr
)
;
return
;
}
</s>

Function that is callable from the debugger to print the current options .


<s>
const
char
*
emit_fusion_gpr_load
(
rtx
target
,
rtx
mem
)
{
rtx
addis_value
;
rtx
addr
;
rtx
load_offset
;
const
char
*
load_str
=
;
machine_mode
mode
;
if
(
GET_CODE
(
mem
)
==
ZERO_EXTEND
)
mem
=
XEXP
(
mem
,
0
)
;
gcc_assert
(
REG_P
(
target
)
&&
MEM_P
(
mem
)
)
;
addr
=
XEXP
(
mem
,
0
)
;
fusion_split_address
(
addr
,
&
addis_value
,
&
load_offset
)
;
mode
=
GET_MODE
(
mem
)
;
switch
(
mode
)
{
case
E_QImode
:
load_str
=
"lbz"
;
break
;
case
E_HImode
:
load_str
=
"lhz"
;
break
;
case
E_SImode
:
case
E_SFmode
:
load_str
=
"lwz"
;
break
;
case
E_DImode
:
case
E_DFmode
:
gcc_assert
(
TARGET_POWERPC64
)
;
load_str
=
"ld"
;
break
;
default
:
fatal_insn
(
"Bad GPR fusion"
,
gen_rtx_SET
(
target
,
mem
)
)
;
}
emit_fusion_addis
(
target
,
addis_value
)
;
emit_fusion_load_store
(
target
,
target
,
load_offset
,
load_str
)
;
return
""
;
}
</s>

Return a string to fuse an addis instruction with a gpr load to the same register that we loaded up the addis instruction . The address that is used is the logical address that was formed during peephole2 : ( lo_sum ( high ) ( low-part ) ) The code is complicated , so we call output_asm_insn directly , and just return `` '' .

rs6000
0
0
"lbz"
"lhz"
"lwz"
"ld"
"Bad GPR fusion"
""


<s> bool MipsLegalizerInfo :: legalizeCustom ( MachineInstr & MI , MachineRegisterInfo & MRI , MachineIRBuilder & MIRBuilder , GISelChangeObserver & Observer ) const { using namespace TargetOpcode ; MIRBuilder . setInstr ( MI ) ; const MipsSubtarget & STI = static_cast < const MipsSubtarget & > ( MIRBuilder . getMF ( ) . getSubtarget ( ) ) ; const LLT s32 = LLT :: scalar ( 32 ) ; const LLT s64 = LLT :: scalar ( 64 ) ; switch ( MI . getOpcode ( ) ) { case G_UITOFP : { Register Dst = MI . getOperand ( 0 ) . getReg ( ) ; Register Src = MI . getOperand ( 1 ) . getReg ( ) ; LLT DstTy = MRI . getType ( Dst ) ; LLT SrcTy = MRI . getType ( Src ) ; if ( SrcTy != s32 ) return false ; if ( DstTy != s32 && DstTy != s64 ) return false ; MachineInstrBuilder Bitcast = MIRBuilder . buildInstr ( STI . isFP64bit ( ) ? Mips :: BuildPairF64_64 : Mips :: BuildPairF64 , { s64 } , { Src , MIRBuilder . buildConstant ( s32 , UINT32_C ( 0x43300000 ) ) } ) ; Bitcast . constrainAllUses ( MIRBuilder . getTII ( ) , * STI . getRegisterInfo ( ) , * STI . getRegBankInfo ( ) ) ; MachineInstrBuilder TwoP52FP = MIRBuilder . buildFConstant ( s64 , BitsToDouble ( UINT64_C ( 0x4330000000000000 ) ) ) ; if ( DstTy == s64 ) MIRBuilder . buildFSub ( Dst , Bitcast , TwoP52FP ) ; else { MachineInstrBuilder ResF64 = MIRBuilder . buildFSub ( s64 , Bitcast , TwoP52FP ) ; MIRBuilder . buildFPTrunc ( Dst , ResF64 ) ; } MI . eraseFromParent ( ) ; break ; } default : return false ; } return true ; } </s>

Called for instructions with the Custom LegalizationAction .


<s> static rtx bfin_struct_value_rtx ( tree fntype ATTRIBUTE_UNUSED , int incoming ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( Pmode , REG_P0 ) ; } </s>

Register in which address to store a structure value is passed to a function .


<s> bool sh_can_use_simple_return_p ( void ) { if ( ! reload_completed || frame_pointer_needed ) return false ; if ( optimize_function_for_size_p ( cfun ) ) return false ; HARD_REG_SET live_regs_mask ; int d = calc_live_regs ( & live_regs_mask ) ; if ( rounded_frame_size ( d ) > 4 ) return false ; return true ; } </s>

Return true if it is appropriate to emit ` ret ' instructions in the body of a function .


<s> static bool chain_contains_only_swaps ( swap_web_entry * insn_entry , struct df_link * link , enum chain_purpose purpose ) { if ( ! link ) return false ; for ( ; link ; link = link -> next ) { if ( ! ALTIVEC_OR_VSX_VECTOR_MODE ( GET_MODE ( DF_REF_REG ( link -> ref ) ) ) ) continue ; if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) return false ; rtx reached_insn = DF_REF_INSN ( link -> ref ) ; unsigned uid = INSN_UID ( reached_insn ) ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( reached_insn ) ; if ( ! insn_entry [ uid ] . is_swap || insn_entry [ uid ] . is_load || insn_entry [ uid ] . is_store ) return false ; if ( purpose == FOR_LOADS ) { df_ref use ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { struct df_link * swap_link = DF_REF_CHAIN ( use ) ; while ( swap_link ) { if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) return false ; rtx swap_def_insn = DF_REF_INSN ( swap_link -> ref ) ; unsigned uid2 = INSN_UID ( swap_def_insn ) ; if ( ! insn_entry [ uid2 ] . is_swap || ! insn_entry [ uid2 ] . is_load ) return false ; swap_link = swap_link -> next ; } } } else if ( purpose == FOR_STORES ) { df_ref def ; FOR_EACH_INSN_INFO_DEF ( def , insn_info ) { struct df_link * swap_link = DF_REF_CHAIN ( def ) ; while ( swap_link ) { if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) return false ; rtx swap_use_insn = DF_REF_INSN ( swap_link -> ref ) ; unsigned uid2 = INSN_UID ( swap_use_insn ) ; if ( ! insn_entry [ uid2 ] . is_swap || insn_entry [ uid2 ] . is_load ) return false ; swap_link = swap_link -> next ; } } } } return true ; } </s>

Return true if the UD or DU chain headed by LINK is non-empty , and every entry on the chain references an insn that is a register swap . Furthermore , if PURPOSE is FOR_LOADS , each such register swap must have only permuting loads as reaching defs . If PURPOSE is FOR_STORES , each such register swap must have only register swaps or permuting stores as reached uses .


<s> static machine_mode mips_preferred_simd_mode ( machine_mode mode ATTRIBUTE_UNUSED ) { if ( TARGET_PAIRED_SINGLE_FLOAT && mode == SFmode ) return V2SFmode ; return word_mode ; } </s>


<s> static void gen_int_relational ( enum rtx_code code , rtx result , rtx cmp0 , rtx cmp1 , rtx destination ) { machine_mode mode ; int branch_p ; mode = GET_MODE ( cmp0 ) ; if ( mode == VOIDmode ) mode = GET_MODE ( cmp1 ) ; branch_p = ( destination != 0 ) ; switch ( code ) { case LE : case LT : case LEU : case LTU : { rtx temp ; code = swap_condition ( code ) ; temp = cmp0 ; cmp0 = cmp1 ; cmp1 = temp ; break ; } default : break ; } if ( branch_p ) { rtx insn , cond , label ; if ( ! register_operand ( cmp0 , mode ) ) cmp0 = force_reg ( mode , cmp0 ) ; if ( ! register_operand ( cmp1 , mode ) ) cmp1 = force_reg ( mode , cmp1 ) ; cond = gen_rtx_fmt_ee ( code , mode , cmp0 , cmp1 ) ; label = gen_rtx_LABEL_REF ( VOIDmode , destination ) ; insn = gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , cond , label , pc_rtx ) ) ; emit_jump_insn ( insn ) ; } else { if ( ( GET_CODE ( cmp0 ) == CONST_INT ) && ( INTVAL ( cmp0 ) != 0 ) ) cmp0 = force_reg ( mode , cmp0 ) ; if ( GET_CODE ( cmp1 ) == CONST_INT ) { switch ( code ) { case EQ : case NE : case LE : case LT : case GE : case GT : if ( ! satisfies_constraint_K ( cmp1 ) ) cmp1 = force_reg ( mode , cmp1 ) ; break ; case LEU : case LTU : case GEU : case GTU : if ( ! satisfies_constraint_L ( cmp1 ) ) cmp1 = force_reg ( mode , cmp1 ) ; break ; default : gcc_unreachable ( ) ; } } emit_move_insn ( result , gen_rtx_fmt_ee ( code , mode , cmp0 , cmp1 ) ) ; } } </s>

Generate the code to compare two integer values . The return value is the comparison expression .


<s> param_iterator arg_end ( ) const { return ArgumentParams . end ( ) ; } </s>

Return the iterator pointing to the end of the argument list .


<s> bool SICDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & static_cast < const SICSubtarget & > ( MF . getSubtarget ( ) ) ; bool Ret = SelectionDAGISel :: runOnMachineFunction ( MF ) ; return Ret ; } </s>

runOnMachineFunction - Emit the function body .


<s> void rs6000_emit_eh_reg_restore ( rtx source , rtx scratch ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; rtx operands [ 2 ] ; operands [ 0 ] = source ; operands [ 1 ] = scratch ; if ( info -> lr_save_p ) { rtx frame_rtx = stack_pointer_rtx ; HOST_WIDE_INT sp_offset = 0 ; rtx tmp ; if ( frame_pointer_needed || cfun -> calls_alloca || info -> total_size > 32767 ) { tmp = gen_frame_mem ( Pmode , frame_rtx ) ; emit_move_insn ( operands [ 1 ] , tmp ) ; frame_rtx = operands [ 1 ] ; } else if ( info -> push_p ) sp_offset = info -> total_size ; tmp = plus_constant ( Pmode , frame_rtx , info -> lr_save_offset + sp_offset ) ; tmp = gen_frame_mem ( Pmode , tmp ) ; emit_move_insn ( tmp , operands [ 0 ] ) ; } else emit_move_insn ( gen_rtx_REG ( Pmode , LR_REGNO ) , operands [ 0 ] ) ; cfun -> machine -> lr_save_state = info -> lr_save_p + 1 ; } </s>

Emit instructions to restore the link register after determining where its value has been stored .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> const CJGRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool SPIRVEmitIntrinsics :: runOnFunction ( Function & Func ) { if ( Func . isDeclaration ( ) ) return false ; F = & Func ; IRB = new IRBuilder < > ( Func . getContext ( ) ) ; AggrConsts . clear ( ) ; AggrStores . clear ( ) ; IRB -> SetInsertPoint ( & Func . getEntryBlock ( ) . front ( ) ) ; for ( auto & GV : Func . getParent ( ) -> globals ( ) ) processGlobalValue ( GV ) ; preprocessCompositeConstants ( ) ; SmallVector < Instruction * > Worklist ; for ( auto & I : instructions ( Func ) ) Worklist . push_back ( & I ) ; for ( auto & I : Worklist ) insertAssignTypeIntrs ( I ) ; for ( auto * I : Worklist ) { TrackConstants = true ; if ( ! I -> getType ( ) -> isVoidTy ( ) || isa < StoreInst > ( I ) ) IRB -> SetInsertPoint ( I -> getNextNode ( ) ) ; I = visit ( * I ) ; processInstrAfterVisit ( I ) ; } return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> rtx gen_push ( rtx operand0 , enum machine_mode mode ) { return gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( mode , gen_rtx_PRE_DEC ( mode , gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ) ) , operand0 ) ; } </s>

Code to generate prologue and epilogue sequences


<s> size_type empty ( ) const { return V . none ( ) ; } </s>

Determine whether this version information is empty ( e.g. , all version components are zero ) .


<s>
bool
AlphaAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
this
->
MF
=
&
MF
;
SetupMachineFunction
(
MF
)
;
O
<<
"\n\n"
;
EmitConstantPool
(
MF
.
getConstantPool
(
)
)
;
EmitJumpTableInfo
(
MF
.
getJumpTableInfo
(
)
,
MF
)
;
const
Function
*
F
=
MF
.
getFunction
(
)
;
SwitchToSection
(
TAI
->
SectionForGlobal
(
F
)
)
;
EmitAlignment
(
4
,
F
)
;
switch
(
F
->
getLinkage
(
)
)
{
default
:
assert
(
0
&&
"Unknown linkage type!"
)
;
case
Function
::
InternalLinkage
:
case
Function
::
PrivateLinkage
:
break
;
case
Function
::
ExternalLinkage
:
O
<<
"\t.globl "
<<
CurrentFnName
<<
"\n"
;
break
;
case
Function
::
WeakAnyLinkage
:
case
Function
::
WeakODRLinkage
:
case
Function
::
LinkOnceAnyLinkage
:
case
Function
::
LinkOnceODRLinkage
:
O
<<
TAI
->
getWeakRefDirective
(
)
<<
CurrentFnName
<<
"\n"
;
break
;
}
printVisibility
(
CurrentFnName
,
F
->
getVisibility
(
)
)
;
O
<<
"\t.ent "
<<
CurrentFnName
<<
"\n"
;
O
<<
CurrentFnName
<<
":\n"
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
I
!=
MF
.
begin
(
)
)
{
printBasicBlockLabel
(
I
,
true
,
true
)
;
O
<<
'\n'
;
}
for
(
MachineBasicBlock
::
const_iterator
II
=
I
->
begin
(
)
,
E
=
I
->
end
(
)
;
II
!=
E
;
++
II
)
{
++
EmittedInsts
;
if
(
!
printInstruction
(
II
)
)
{
assert
(
0
&&
"Unhandled instruction in asm writer!"
)
;
abort
(
)
;
}
}
}
O
<<
"\t.end "
<<
CurrentFnName
<<
"\n"
;
return
false
;
}
</s>

Alpha
Alpha
"\n\n"
4
0
"Unknown linkage type!"
"\t.globl "
"\n"
"\n"
"\t.ent "
"\n"
":\n"
0
"Unhandled instruction in asm writer!"
"\t.end "
"\n"


<s>
void
PPCTargetLowering
::
LowerAsmOperandForConstraint
(
SDValue
Op
,
std
::
string
&
Constraint
,
std
::
vector
<
SDValue
>
&
Ops
,
SelectionDAG
&
DAG
)
const
{
SDValue
Result
;
if
(
Constraint
.
length
(
)
>
1
)
return
;
char
Letter
=
Constraint
[
0
]
;
switch
(
Letter
)
{
default
:
break
;
case
'I'
:
case
'J'
:
case
'K'
:
case
'L'
:
case
'M'
:
case
'N'
:
case
'O'
:
case
'P'
:
{
ConstantSDNode
*
CST
=
dyn_cast
<
ConstantSDNode
>
(
Op
)
;
if
(
!
CST
)
return
;
unsigned
Value
=
CST
->
getZExtValue
(
)
;
switch
(
Letter
)
{
default
:
llvm_unreachable
(
"Unknown constraint letter!"
)
;
case
'I'
:
if
(
(
short
)
Value
==
(
int
)
Value
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'J'
:
case
'L'
:
if
(
(
short
)
Value
==
0
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'K'
:
if
(
(
Value
>>
16
)
==
0
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'M'
:
if
(
Value
>
31
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'N'
:
if
(
(
int
)
Value
>
0
&&
isPowerOf2_32
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'O'
:
if
(
Value
==
0
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'P'
:
if
(
(
short
)
Value
==
(
int
)
Value
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
}
break
;
}
}
if
(
Result
.
getNode
(
)
)
{
Ops
.
push_back
(
Result
)
;
return
;
}
TargetLowering
::
LowerAsmOperandForConstraint
(
Op
,
Constraint
,
Ops
,
DAG
)
;
}
</s>

Lower the specified operand into the Ops vector .


<s> unsigned MipsTargetLowering :: getJumpTableEncoding ( ) const { if ( IsN64 ) return MachineJumpTableInfo :: EK_GPRel64BlockAddress ; return TargetLowering :: getJumpTableEncoding ( ) ; } </s>

Return the entry encoding for a jump table in the current function .


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { unsigned NumOps = Inst . getNumOperands ( ) ; if ( NumOps == 0 || Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ NumOps - 1 ] . OperandType != MCOI :: OPERAND_PCREL ) return false ; Target = Addr + Inst . getOperand ( NumOps - 1 ) . getImm ( ) * Size ; return true ; } </s>

Given a branch instruction try to get the address the branch targets .


"%s as it already contains this value\n"

Generate and emit a move of ( register ) FROM into TO . if WHERE is not NULL then if BEFORE is true then emit the insn before WHERE , otherwise emit it after WHERE . If TO already contains FROM then do nothing . Returns TO if BEFORE is true , FROM otherwise .


<s> static rtx h8300_get_index ( rtx x , machine_mode mode , int * size ) { int dummy , factor ; if ( size == 0 ) size = & dummy ; factor = ( mode == VOIDmode ? 0 : GET_MODE_SIZE ( mode ) ) ; if ( TARGET_H8300SX && factor <= 4 && ( mode == VOIDmode || GET_MODE_CLASS ( mode ) == MODE_INT || GET_MODE_CLASS ( mode ) == MODE_FLOAT ) ) { if ( factor <= 1 && GET_CODE ( x ) == ZERO_EXTEND ) { * size = GET_MODE_SIZE ( GET_MODE ( XEXP ( x , 0 ) ) ) ; return XEXP ( x , 0 ) ; } else { rtx index ; if ( GET_CODE ( x ) == AND && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT && ( factor == 0 || INTVAL ( XEXP ( x , 1 ) ) == 0xff * factor || INTVAL ( XEXP ( x , 1 ) ) == 0xffff * factor ) ) { index = XEXP ( x , 0 ) ; * size = ( INTVAL ( XEXP ( x , 1 ) ) >= 0xffff ? 2 : 1 ) ; } else { index = x ; * size = 4 ; } if ( GET_CODE ( index ) == MULT && GET_CODE ( XEXP ( index , 1 ) ) == CONST_INT && ( factor == 0 || factor == INTVAL ( XEXP ( index , 1 ) ) ) ) return XEXP ( index , 0 ) ; } } * size = 0 ; return x ; } </s>

Given that X occurs in an address of the form ( plus X constant ) , return the part of X that is expected to be a register . There are four kinds of addressing mode to recognize : @ ( dd , Rn ) @ ( dd , RnL.b ) @ ( dd , Rn.w ) @ ( dd , ERn.l ) If SIZE is nonnull , and the address is one of the last three forms , set * SIZE to the index multiplication factor . Set it to 0 for plain @ ( dd , Rn ) addresses . MODE is the mode of the value being accessed . It can be VOIDmode if the address is known to be valid , but its mode is unknown .


<s> int sh_pr_n_sets ( ) { return REG_N_SETS ( PR_REG ) ; } </s>

For use by ALLOCATE_INITIAL_VALUE . Note that sh.md contains some 'special function ' patterns ( type sfunc ) that clobber pr , but that do not look like function calls to leaf_function_p . Hence we must do this extra check .


<s>
TargetTransformInfo
::
PopcntSupportKind
PPCTTIImpl
::
getPopcntSupport
(
unsigned
TyWidth
)
{
assert
(
isPowerOf2_32
(
TyWidth
)
&&
"Ty width must be power of 2"
)
;
if
(
ST
->
hasPOPCNTD
(
)
&&
TyWidth
<=
64
)
return
TTI
::
PSK_FastHardware
;
return
TTI
::
PSK_Software
;
}
</s>

Return hardware support for population count .

PowerPC
PPC
"Ty width must be power of 2"
64


<s> bool HexagonEvaluator :: evaluate ( const MachineInstr & BI , const CellMapType & Inputs , BranchTargetList & Targets , bool & FallsThru ) const { unsigned Opc = BI . getOpcode ( ) ; bool SimpleBranch = false ; bool Negated = false ; switch ( Opc ) { case Hexagon :: J2_jumpf : case Hexagon :: J2_jumpfpt : case Hexagon :: J2_jumpfnew : case Hexagon :: J2_jumpfnewpt : Negated = true ; LLVM_FALLTHROUGH ; case Hexagon :: J2_jumpt : case Hexagon :: J2_jumptpt : case Hexagon :: J2_jumptnew : case Hexagon :: J2_jumptnewpt : SimpleBranch = true ; break ; case Hexagon :: J2_jump : Targets . insert ( BI . getOperand ( 0 ) . getMBB ( ) ) ; FallsThru = false ; return true ; default : return false ; } if ( ! SimpleBranch ) return false ; RegisterRef PR = BI . getOperand ( 0 ) ; RegisterCell PC = getCell ( PR , Inputs ) ; const BT :: BitValue & Test = PC [ 0 ] ; if ( ! Test . is ( 0 ) && ! Test . is ( 1 ) ) return false ; if ( ! Test . is ( ! Negated ) ) { FallsThru = true ; return true ; } Targets . insert ( BI . getOperand ( 1 ) . getMBB ( ) ) ; FallsThru = false ; return true ; } </s>

evaluate - Evaluate Expr and append the resulting set to Elts .