<s> unsigned X86InstrInfo :: getOpcodeAfterMemoryUnfold ( unsigned Opc , bool UnfoldLoad , bool UnfoldStore , unsigned * LoadRegIndex ) const { auto I = MemOp2RegOpTable . find ( Opc ) ; if ( I == MemOp2RegOpTable . end ( ) ) return 0 ; bool FoldedLoad = I -> second . second & TB_FOLDED_LOAD ; bool FoldedStore = I -> second . second & TB_FOLDED_STORE ; if ( UnfoldLoad && ! FoldedLoad ) return 0 ; if ( UnfoldStore && ! FoldedStore ) return 0 ; if ( LoadRegIndex ) * LoadRegIndex = I -> second . second & TB_INDEX_MASK ; return I -> second . first ; } </s>

getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode .


<s> bool LanaiPassConfig :: addInstSelector ( ) { addPass ( createLanaiISelDag ( getLanaiTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void bfin_hardware_loop ( void ) { cfun -> machine -> has_hardware_loops ++ ; } </s>

Increment the counter for the number of loop instructions in the current function .


"Not all fixup kinds added to Infos array"


"Cannot emit contents before setting section!"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


"Instruction should be in a basic block!"

"Generic instruction has unexpected implicit operands\n"

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s> static void mips_74k_agen_init ( rtx_insn * insn ) { if ( ! insn || CALL_P ( insn ) || JUMP_P ( insn ) ) mips_last_74k_agen_insn = TYPE_UNKNOWN ; else { enum attr_type type = get_attr_type ( insn ) ; if ( type == TYPE_LOAD || type == TYPE_STORE ) mips_last_74k_agen_insn = type ; } } </s>

Initialize mips_last_74k_agen_insn from INSN . A null argument resets to TYPE_UNKNOWN state .


<s> bool isToken ( ) const override { return Kind == OpKind_Token ; } </s>


runOnMachineFunction - Emit the function body .


<s> const char * XCoreTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case XCoreISD :: BL : return "XCoreISD::BL" ; case XCoreISD :: PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper" ; case XCoreISD :: DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper" ; case XCoreISD :: CPRelativeWrapper : return "XCoreISD::CPRelativeWrapper" ; case XCoreISD :: LDWSP : return "XCoreISD::LDWSP" ; case XCoreISD :: STWSP : return "XCoreISD::STWSP" ; case XCoreISD :: RETSP : return "XCoreISD::RETSP" ; case XCoreISD :: LADD : return "XCoreISD::LADD" ; case XCoreISD :: LSUB : return "XCoreISD::LSUB" ; case XCoreISD :: LMUL : return "XCoreISD::LMUL" ; case XCoreISD :: MACCU : return "XCoreISD::MACCU" ; case XCoreISD :: MACCS : return "XCoreISD::MACCS" ; case XCoreISD :: CRC8 : return "XCoreISD::CRC8" ; case XCoreISD :: BR_JT : return "XCoreISD::BR_JT" ; case XCoreISD :: BR_JT32 : return "XCoreISD::BR_JT32" ; case XCoreISD :: FRAME_TO_ARGS_OFFSET : return "XCoreISD::FRAME_TO_ARGS_OFFSET" ; case XCoreISD :: EH_RETURN : return "XCoreISD::EH_RETURN" ; case XCoreISD :: MEMBARRIER : return "XCoreISD::MEMBARRIER" ; default : return nullptr ; } } </s>

getTargetNodeName - This method returns the name of a target specific

XCore XCore XCoreISD::BL "XCoreISD::BL" XCoreISD::PCRelativeWrapper "XCoreISD::PCRelativeWrapper" XCoreISD::DPRelativeWrapper "XCoreISD::DPRelativeWrapper" XCoreISD::CPRelativeWrapper "XCoreISD::CPRelativeWrapper" XCoreISD::LDWSP "XCoreISD::LDWSP" XCoreISD::STWSP "XCoreISD::STWSP" XCoreISD::RETSP "XCoreISD::RETSP" XCoreISD::LADD "XCoreISD::LADD" XCoreISD::LSUB "XCoreISD::LSUB" XCoreISD::LMUL "XCoreISD::LMUL" XCoreISD::MACCU "XCoreISD::MACCU" XCoreISD::MACCS "XCoreISD::MACCS" XCoreISD::CRC8 "XCoreISD::CRC8" XCoreISD::BR_JT "XCoreISD::BR_JT" XCoreISD::BR_JT32 "XCoreISD::BR_JT32" XCoreISD::FRAME_TO_ARGS_OFFSET "XCoreISD::FRAME_TO_ARGS_OFFSET" XCoreISD::EH_RETURN "XCoreISD::EH_RETURN" XCoreISD::MEMBARRIER "XCoreISD::MEMBARRIER"


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == 0 ) Inst . addOperand ( MCOperand :: CreateImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ; } </s>


"XtensaInstrInfo::analyzeBranch not yet implemented"

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < MachineBranchProbabilityInfo > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
SDNode
*
LM32DAGToDAGISel
::
getGlobalBaseReg
(
)
{
assert
(
0
&&
"getGlobalBaseReg() not supported."
)
;
unsigned
GlobalBaseReg
=
getInstrInfo
(
)
->
getGlobalBaseReg
(
MF
)
;
return
CurDAG
->
getRegister
(
GlobalBaseReg
,
TLI
.
getPointerTy
(
)
)
.
getNode
(
)
;
}
</s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


"Can only insert epilog into returning blocks"


<s> bool splitFramePushPop ( const MachineFunction & MF ) const { return ( useR7AsFramePointer ( ) && MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) || isThumb1Only ( ) ; } </s>

Returns true if the frame setup is split into two separate pushes ( first r0-r7 , lr then r8-r11 ) , principally so that the frame pointer is adjacent to lr .


<s> PPCSubtarget :: PPCSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , bool is64Bit , CodeGenOpt :: Level OptLevel ) : PPCGenSubtargetInfo ( TT , CPU , FS ) , IsPPC64 ( is64Bit ) , TargetTriple ( TT ) { initializeEnvironment ( ) ; std :: string FullFS = FS ; if ( OptLevel >= CodeGenOpt :: Default ) { if ( ! FullFS . empty ( ) ) FullFS = "+crbits," + FullFS ; else FullFS = "+crbits" ; } resetSubtargetFeatures ( CPU , FullFS ) ; } </s>

This constructor initializes the data members to match that of the specified triple .

PowerPC PPC PPC PPC PPC "+crbits," "+crbits"


<s> void TOYAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createELFObjectWriter ( createELFObjectTargetWriter ( ) , OS , true ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static reg_class_t pa_secondary_reload ( bool in_p , rtx x , reg_class_t rclass_i , machine_mode mode , secondary_reload_info * sri ) { int regno ; enum reg_class rclass = ( enum reg_class ) rclass_i ; if ( rclass == R1_REGS ) return NO_REGS ; if ( REG_P ( x ) ) { regno = REGNO ( x ) ; if ( rclass == BASE_REG_CLASS && regno < FIRST_PSEUDO_REGISTER ) return NO_REGS ; } else regno = - 1 ; if ( GET_CODE ( x ) == MEM && GET_CODE ( XEXP ( x , 0 ) ) == MEM ) return NO_REGS ; if ( flag_pic && FP_REG_CLASS_P ( rclass ) && ( GET_CODE ( x ) == CONST_INT || GET_CODE ( x ) == CONST_DOUBLE ) ) { switch ( mode ) { case SImode : sri -> icode = CODE_FOR_reload_insi_r1 ; break ; case DImode : sri -> icode = CODE_FOR_reload_indi_r1 ; break ; case SFmode : sri -> icode = CODE_FOR_reload_insf_r1 ; break ; case DFmode : sri -> icode = CODE_FOR_reload_indf_r1 ; break ; default : gcc_unreachable ( ) ; } return NO_REGS ; } if ( pa_symbolic_expression_p ( x ) ) { if ( GET_CODE ( x ) == HIGH ) x = XEXP ( x , 0 ) ; if ( flag_pic || ! read_only_operand ( x , VOIDmode ) ) { switch ( mode ) { case SImode : sri -> icode = CODE_FOR_reload_insi_r1 ; break ; case DImode : sri -> icode = CODE_FOR_reload_indi_r1 ; break ; default : gcc_unreachable ( ) ; } return NO_REGS ; } } if ( regno >= FIRST_PSEUDO_REGISTER || GET_CODE ( x ) == SUBREG ) regno = true_regnum ( x ) ; if ( ( regno >= FIRST_PSEUDO_REGISTER || regno == - 1 ) && FP_REG_CLASS_P ( rclass ) ) { if ( MEM_P ( x ) ) { x = XEXP ( x , 0 ) ; if ( IS_INDEX_ADDR_P ( x ) ) return NO_REGS ; } sri -> icode = ( in_p ? direct_optab_handler ( reload_in_optab , mode ) : direct_optab_handler ( reload_out_optab , mode ) ) ; return NO_REGS ; } if ( rclass == SHIFT_REGS ) { if ( regno >= FIRST_PSEUDO_REGISTER || regno < 0 ) { sri -> icode = ( in_p ? direct_optab_handler ( reload_in_optab , mode ) : direct_optab_handler ( reload_out_optab , mode ) ) ; return NO_REGS ; } if ( FP_REG_CLASS_P ( REGNO_REG_CLASS ( regno ) ) ) return GENERAL_REGS ; } if ( regno >= 0 && regno < FIRST_PSEUDO_REGISTER && REGNO_REG_CLASS ( regno ) == SHIFT_REGS && FP_REG_CLASS_P ( rclass ) ) return GENERAL_REGS ; return NO_REGS ; } </s>

Inform reload about cases where moving X with a mode MODE to or from a register in RCLASS requires an extra scratch or immediate register . Return the class needed for the immediate register .


Emit the appropriate code to do a comparison , returning the register the comparison was done it .


<s> bool XCoreTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty ) const { if ( Ty -> getTypeID ( ) == Type :: VoidTyID ) return AM . Scale == 0 && isImmUs ( AM . BaseOffs ) && isImmUs4 ( AM . BaseOffs ) ; const DataLayout * TD = TM . getSubtargetImpl ( ) -> getDataLayout ( ) ; unsigned Size = TD -> getTypeAllocSize ( Ty ) ; if ( AM . BaseGV ) { return Size >= 4 && ! AM . HasBaseReg && AM . Scale == 0 && AM . BaseOffs % 4 == 0 ; } switch ( Size ) { case 1 : if ( AM . Scale == 0 ) { return isImmUs ( AM . BaseOffs ) ; } return AM . Scale == 1 && AM . BaseOffs == 0 ; case 2 : case 3 : if ( AM . Scale == 0 ) { return isImmUs2 ( AM . BaseOffs ) ; } return AM . Scale == 2 && AM . BaseOffs == 0 ; default : if ( AM . Scale == 0 ) { return isImmUs4 ( AM . BaseOffs ) ; } return AM . Scale == 4 && AM . BaseOffs == 0 ; } } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> static bool aarch64_if_then_else_costs ( rtx op0 , rtx op1 , rtx op2 , int * cost , bool speed ) { rtx inner ; rtx comparator ; enum rtx_code cmpcode ; const struct cpu_cost_table * extra_cost = aarch64_tune_params . insn_extra_cost ; if ( COMPARISON_P ( op0 ) ) { inner = XEXP ( op0 , 0 ) ; comparator = XEXP ( op0 , 1 ) ; cmpcode = GET_CODE ( op0 ) ; } else { inner = op0 ; comparator = const0_rtx ; cmpcode = NE ; } if ( GET_CODE ( op1 ) == PC || GET_CODE ( op2 ) == PC ) { if ( GET_MODE_CLASS ( GET_MODE ( inner ) ) == MODE_CC ) return true ; else { if ( cmpcode == NE || cmpcode == EQ ) { if ( comparator == const0_rtx ) { if ( GET_CODE ( inner ) == ZERO_EXTRACT ) * cost += rtx_cost ( XEXP ( inner , 0 ) , VOIDmode , ZERO_EXTRACT , 0 , speed ) ; else * cost += rtx_cost ( inner , VOIDmode , cmpcode , 0 , speed ) ; return true ; } if ( register_operand ( inner , VOIDmode ) && aarch64_imm24 ( comparator , VOIDmode ) ) { * cost += COSTS_N_INSNS ( 2 ) ; if ( speed ) * cost += extra_cost -> alu . arith * 2 ; return true ; } } else if ( cmpcode == LT || cmpcode == GE ) { if ( comparator == const0_rtx ) return true ; } } } else if ( GET_MODE_CLASS ( GET_MODE ( inner ) ) == MODE_CC ) { if ( GET_CODE ( op1 ) == COMPARE ) { if ( XEXP ( op1 , 1 ) == const0_rtx ) * cost += 1 ; if ( speed ) { machine_mode mode = GET_MODE ( XEXP ( op1 , 0 ) ) ; const struct cpu_cost_table * extra_cost = aarch64_tune_params . insn_extra_cost ; if ( GET_MODE_CLASS ( mode ) == MODE_INT ) * cost += extra_cost -> alu . arith ; else * cost += extra_cost -> fp [ mode == DFmode ] . compare ; } return true ; } if ( GET_CODE ( op1 ) == NEG || GET_CODE ( op1 ) == NOT || ( GET_CODE ( op1 ) == PLUS && XEXP ( op1 , 1 ) == const1_rtx ) ) op1 = XEXP ( op1 , 0 ) ; else if ( GET_CODE ( op1 ) == ZERO_EXTEND && GET_CODE ( op2 ) == ZERO_EXTEND ) { op1 = XEXP ( op1 , 0 ) ; op2 = XEXP ( op2 , 0 ) ; } * cost += rtx_cost ( op1 , VOIDmode , IF_THEN_ELSE , 1 , speed ) ; * cost += rtx_cost ( op2 , VOIDmode , IF_THEN_ELSE , 2 , speed ) ; return true ; } return false ; } </s>

Calculate the cost of calculating ( if_then_else ( OP0 ) ( OP1 ) ( OP2 ) ) , storing it in * COST . Result is true if the total cost of the operation has now been calculated .


<s> bool AArch64AsmParser :: ParseDirective ( AsmToken DirectiveID ) { const MCObjectFileInfo :: Environment Format = getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ; bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; auto IDVal = DirectiveID . getIdentifier ( ) . lower ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == ".arch" ) parseDirectiveArch ( Loc ) ; else if ( IDVal == ".cpu" ) parseDirectiveCPU ( Loc ) ; else if ( IDVal == ".tlsdesccall" ) parseDirectiveTLSDescCall ( Loc ) ; else if ( IDVal == ".ltorg" || IDVal == ".pool" ) parseDirectiveLtorg ( Loc ) ; else if ( IDVal == ".unreq" ) parseDirectiveUnreq ( Loc ) ; else if ( IDVal == ".inst" ) parseDirectiveInst ( Loc ) ; else if ( IDVal == ".cfi_negate_ra_state" ) parseDirectiveCFINegateRAState ( ) ; else if ( IDVal == ".cfi_b_key_frame" ) parseDirectiveCFIBKeyFrame ( ) ; else if ( IDVal == ".arch_extension" ) parseDirectiveArchExtension ( Loc ) ; else if ( IsMachO ) { if ( IDVal == MCLOHDirectiveName ( ) ) parseDirectiveLOH ( IDVal , Loc ) ; else return true ; } else return true ; return false ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool nios2_fpu_insn_enabled ( enum n2fpu_code code ) { return N2FPU_ENABLED_P ( code ) ; } </s>

Export the FPU insn enabled predicate to nios2.md .


<s> virtual const TargetFrameInfo * getFrameInfo ( ) const { return & FrameInfo ; } </s>

getFrameInfo - Return the frame info object for the current function .


<s> void Stack :: dump ( ) const { print ( dbgs ( ) ) ; dbgs ( ) << "\n" ; dbgs ( ) . flush ( ) ; } </s>

Dump the plan to stderr ( for debugging ) .


<s> static void visium_save_regs ( int alloc , int offset , int low_regno , int high_regno ) { const int volatile_p = current_frame_info . interrupt ; int regno ; emit_frame_insn ( gen_addsi3_flags ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - alloc ) ) ) ; for ( regno = low_regno ; regno <= high_regno ; regno ++ ) { enum reg_type reg_type = GET_REG_TYPE ( regno ) ; int mask_bit = 1 << ( regno - first_regno [ reg_type ] ) ; rtx insn ; if ( current_frame_info . mask [ reg_type ] & mask_bit ) { offset -= reg_type_size [ reg_type ] ; switch ( reg_type ) { case general : { rtx mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; MEM_VOLATILE_P ( mem ) = volatile_p ; emit_frame_insn ( gen_movsi ( mem , gen_rtx_REG ( SImode , regno ) ) ) ; } break ; case mdb : { rtx tmp = gen_rtx_REG ( DImode , PROLOGUE_TMP_REGNUM ) ; rtx mem = gen_frame_mem ( DImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; rtx reg = gen_rtx_REG ( DImode , regno ) ; MEM_VOLATILE_P ( mem ) = volatile_p ; emit_insn ( gen_movdi ( tmp , reg ) ) ; if ( volatile_p ) emit_insn ( gen_movdi ( mem , tmp ) ) ; else { insn = emit_frame_insn ( gen_movdi ( mem , tmp ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , mem , reg ) ) ; } } break ; case mdc : { rtx tmp = gen_rtx_REG ( SImode , PROLOGUE_TMP_REGNUM ) ; rtx mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; rtx reg = gen_rtx_REG ( SImode , regno ) ; MEM_VOLATILE_P ( mem ) = volatile_p ; emit_insn ( gen_movsi ( tmp , reg ) ) ; insn = emit_frame_insn ( gen_movsi ( mem , tmp ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , mem , reg ) ) ; } break ; case floating : { rtx tmp = gen_rtx_REG ( SFmode , PROLOGUE_TMP_REGNUM ) ; rtx mem = gen_frame_mem ( SFmode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; rtx reg = gen_rtx_REG ( SFmode , regno ) ; MEM_VOLATILE_P ( mem ) = volatile_p ; emit_insn ( gen_movsf ( tmp , reg ) ) ; insn = emit_frame_insn ( gen_movsf ( mem , tmp ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , mem , reg ) ) ; } break ; default : break ; } } } } </s>

Allocate ALLOC bytes on the stack and save the registers LOW_REGNO to HIGH_REGNO at OFFSET from the stack pointer .


<s> int frame_pointer_required_p ( void ) { return ( current_function_calls_alloca || current_function_args_info . nregs == 0 || get_frame_size ( ) > 0 ) ; } </s>

Return 1 if frame pointer for current function required .


<s> static void aarch64_restore_callee_saves ( machine_mode mode , HOST_WIDE_INT start_offset , unsigned start , unsigned limit , bool skip_wb , rtx * cfi_ops ) { rtx base_rtx = stack_pointer_rtx ; rtx ( * gen_mem_ref ) ( machine_mode , rtx ) = ( frame_pointer_needed ? gen_frame_mem : gen_rtx_MEM ) ; unsigned regno ; unsigned regno2 ; HOST_WIDE_INT offset ; for ( regno = aarch64_next_callee_save ( start , limit ) ; regno <= limit ; regno = aarch64_next_callee_save ( regno + 1 , limit ) ) { if ( cfun -> machine -> reg_is_wrapped_separately [ regno ] ) continue ; rtx reg , mem ; if ( skip_wb && ( regno == cfun -> machine -> frame . wb_candidate1 || regno == cfun -> machine -> frame . wb_candidate2 ) ) continue ; reg = gen_rtx_REG ( mode , regno ) ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno ] ; mem = gen_mem_ref ( mode , plus_constant ( Pmode , base_rtx , offset ) ) ; regno2 = aarch64_next_callee_save ( regno + 1 , limit ) ; if ( regno2 <= limit && ! cfun -> machine -> reg_is_wrapped_separately [ regno2 ] && ( ( cfun -> machine -> frame . reg_offset [ regno ] + UNITS_PER_WORD ) == cfun -> machine -> frame . reg_offset [ regno2 ] ) ) { rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; rtx mem2 ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno2 ] ; mem2 = gen_mem_ref ( mode , plus_constant ( Pmode , base_rtx , offset ) ) ; emit_insn ( aarch64_gen_load_pair ( mode , reg , mem , reg2 , mem2 ) ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg2 , * cfi_ops ) ; regno = regno2 ; } else emit_move_insn ( reg , mem ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg , * cfi_ops ) ; } } </s>

Emit code to restore the callee registers of mode MODE from register number START up to and including LIMIT . Restore from the stack offset START_OFFSET , skipping any write-back candidates if SKIP_WB is true . Write the appropriate REG_CFA_RESTORE notes into CFI_OPS .


<s> bool AMDGPUPassConfig :: addPostRegAlloc ( ) { const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . device ( ) -> getGeneration ( ) > AMDGPUDeviceInfo :: HD6XXX ) { addPass ( createSIInsertWaits ( * TM ) ) ; } return false ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s>
void
AArch64TargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this"
)
;
case
ISD
::
BITCAST
:
ReplaceBITCASTResults
(
N
,
Results
,
DAG
)
;
return
;
case
ISD
::
FP_TO_UINT
:
case
ISD
::
FP_TO_SINT
:
assert
(
N
->
getValueType
(
0
)
==
MVT
::
i128
&&
"unexpected illegal conversion"
)
;
return
;
}
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> bool X86TargetLowering :: isNarrowingProfitable ( EVT VT1 , EVT VT2 ) const { return ! ( VT1 == MVT :: i32 && VT2 == MVT :: i16 ) ; } </s>

Return true if it 's profitable to narrow operations of type SrcVT to DestVT .


<s> void rs6000_cost_data :: adjust_vect_cost_per_loop ( loop_vec_info loop_vinfo ) { if ( LOOP_VINFO_FULLY_WITH_LENGTH_P ( loop_vinfo ) ) { rgroup_controls * rgc ; unsigned int num_vectors_m1 ; unsigned int shift_cnt = 0 ; FOR_EACH_VEC_ELT ( LOOP_VINFO_LENS ( loop_vinfo ) , num_vectors_m1 , rgc ) if ( rgc -> type ) shift_cnt += num_vectors_m1 + 1 ; add_stmt_cost ( shift_cnt , scalar_stmt , NULL , NULL , NULL_TREE , 0 , vect_body ) ; } } </s>

For some target specific vectorization cost which ca n't be handled per stmt , we check the requisite conditions and adjust the vectorization cost accordingly if satisfied . One typical example is to model shift cost for vector with length by counting number of required lengths under condition LOOP_VINFO_FULLY_WITH_LENGTH_P .


<s>
StringRef
getPassName
(
)
const
override
{
return
"WebAssembly Register Numbering"
;
}
</s>

getPassName - Return a nice clean name for a pass .

WebAssembly
"WebAssembly Register Numbering"


<s> bool X86TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * SI ) const { return false ; } </s>

Returns how the given ( atomic ) load should be expanded by the IR-level AtomicExpand pass .


<s> static bool i386_pe_dllimport_p ( tree decl ) { if ( TREE_CODE ( decl ) != VAR_DECL && TREE_CODE ( decl ) != FUNCTION_DECL ) return false ; if ( lookup_attribute ( "dllimport" , DECL_ATTRIBUTES ( decl ) ) ) return true ; if ( associated_type ( decl ) && lookup_attribute ( "dllimport" , TYPE_ATTRIBUTES ( associated_type ( decl ) ) ) ) return i386_pe_type_dllimport_p ( decl ) ; return false ; } </s>

Return non-zero if DECL is a dllimport 'd object .


<s> bool SITargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & CI , unsigned IntrID ) const { switch ( IntrID ) { case Intrinsic :: amdgcn_atomic_inc : case Intrinsic :: amdgcn_atomic_dec : { Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: getVT ( CI . getType ( ) ) ; Info . ptrVal = CI . getOperand ( 0 ) ; Info . align = 0 ; const ConstantInt * Vol = dyn_cast < ConstantInt > ( CI . getOperand ( 4 ) ) ; Info . vol = ! Vol || ! Vol -> isNullValue ( ) ; Info . readMem = true ; Info . writeMem = true ; return true ; } default : return false ; } } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> static bool ix86_legitimate_combined_insn ( rtx_insn * insn ) { int i ; gcc_assert ( INSN_CODE ( insn ) >= 0 ) ; extract_insn ( insn ) ; preprocess_constraints ( insn ) ; int n_operands = recog_data . n_operands ; int n_alternatives = recog_data . n_alternatives ; for ( i = 0 ; i < n_operands ; i ++ ) { rtx op = recog_data . operand [ i ] ; machine_mode mode = GET_MODE ( op ) ; const operand_alternative * op_alt ; int offset = 0 ; bool win ; int j ; if ( UNARY_P ( op ) ) op = XEXP ( op , 0 ) ; if ( SUBREG_P ( op ) ) { if ( REG_P ( SUBREG_REG ( op ) ) && REGNO ( SUBREG_REG ( op ) ) < FIRST_PSEUDO_REGISTER ) offset = subreg_regno_offset ( REGNO ( SUBREG_REG ( op ) ) , GET_MODE ( SUBREG_REG ( op ) ) , SUBREG_BYTE ( op ) , GET_MODE ( op ) ) ; op = SUBREG_REG ( op ) ; } if ( ! ( REG_P ( op ) && HARD_REGISTER_P ( op ) ) ) continue ; op_alt = recog_op_alt ; win = ! n_alternatives ; alternative_mask preferred = get_preferred_alternatives ( insn ) ; for ( j = 0 ; j < n_alternatives ; j ++ , op_alt += n_operands ) { if ( ! TEST_BIT ( preferred , j ) ) continue ; if ( op_alt [ i ] . anything_ok || ( op_alt [ i ] . matches != - 1 && operands_match_p ( recog_data . operand [ i ] , recog_data . operand [ op_alt [ i ] . matches ] ) ) || reg_fits_class_p ( op , op_alt [ i ] . cl , offset , mode ) ) { win = true ; break ; } } if ( ! win ) return false ; } return true ; } </s>

Implement the TARGET_LEGITIMATE_COMBINED_INSN hook .


<s> bool XCoreInstrInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) { return true ; } MachineFunction * MF = MBB . getParent ( ) ; XCoreFunctionInfo * XFI = MF -> getInfo < XCoreFunctionInfo > ( ) ; bool emitFrameMoves = XCoreRegisterInfo :: needsFrameMoves ( * MF ) ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator it = CSI . begin ( ) ; it != CSI . end ( ) ; ++ it ) { MBB . addLiveIn ( it -> getReg ( ) ) ; unsigned Reg = it -> getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; storeRegToStackSlot ( MBB , MI , Reg , true , it -> getFrameIdx ( ) , RC , & RI ) ; if ( emitFrameMoves ) { MCSymbol * SaveLabel = MF -> getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MI , DL , get ( XCore :: PROLOG_LABEL ) ) . addSym ( SaveLabel ) ; XFI -> getSpillLabels ( ) . push_back ( std :: make_pair ( SaveLabel , * it ) ) ; } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .

XCore XCore XCore XCore XCore XCore::PROLOG_LABEL


"Should be handled target independently"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void SITargetLowering :: allocateSpecialInputVGPRs ( CCState & CCInfo , MachineFunction & MF , const SIRegisterInfo & TRI , SIMachineFunctionInfo & Info ) const { const unsigned Mask = 0x3ff ; ArgDescriptor Arg ; if ( Info . hasWorkItemIDX ( ) ) { Arg = allocateVGPR32Input ( CCInfo , Mask ) ; Info . setWorkItemIDX ( Arg ) ; } if ( Info . hasWorkItemIDY ( ) ) { Arg = allocateVGPR32Input ( CCInfo , Mask << 10 , Arg ) ; Info . setWorkItemIDY ( Arg ) ; } if ( Info . hasWorkItemIDZ ( ) ) Info . setWorkItemIDZ ( allocateVGPR32Input ( CCInfo , Mask << 20 , Arg ) ) ; } </s>

Allocate implicit function VGPR arguments at the end of allocated user arguments .


<s> static unsigned int sh_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( XD_REGISTER_P ( regno ) ) return CEIL ( GET_MODE_SIZE ( mode ) , 2 * UNITS_PER_WORD ) ; return CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ; } </s>

Implement TARGET_HARD_REGNO_NREGS . On the SH all but the XD regs are UNITS_PER_WORD bits wide .


<s> static rtx m32r_function_value ( const_tree valtype , const_tree fn_decl_or_type ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( TYPE_MODE ( valtype ) , 0 ) ; } </s>

Worker function for TARGET_FUNCTION_VALUE .


<s> bool Thumb1FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > 0 ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , TII . get ( ARM :: tPOP ) ) ; AddDefaultPred ( MIB ) ; bool NumRegs = false ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( Reg == ARM :: LR ) { if ( isVarArg ) continue ; Reg = ARM :: PC ; ( * MIB ) . setDesc ( TII . get ( ARM :: tPOP_RET ) ) ; MI = MBB . erase ( MI ) ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; NumRegs = true ; } if ( NumRegs ) MBB . insert ( MI , & * MIB ) ; else MF . DeleteMachineInstr ( MIB ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static bool ix86_vector_mode_supported_p ( enum machine_mode mode ) { if ( TARGET_SSE && VALID_SSE_REG_MODE ( mode ) ) return true ; if ( TARGET_SSE2 && VALID_SSE2_REG_MODE ( mode ) ) return true ; if ( TARGET_MMX && VALID_MMX_REG_MODE ( mode ) ) return true ; if ( TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW ( mode ) ) return true ; return false ; } </s>

Implements target hook vector_mode_supported_p .


<s> MachineRegisterInfo & getRegInfo ( Block & MBB ) { return MBB . getParent ( ) -> getRegInfo ( ) ; } </s>

getRegInfo - Return information about the registers currently in use .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> unsigned HexagonMCCodeEmitter :: getMachineOpValue ( MCInst const & MI , MCOperand const & MO , SmallVectorImpl < MCFixup > & Fixups , MCSubtargetInfo const & STI ) const { if ( MO . isReg ( ) ) return MCT . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; assert ( MO . isExpr ( ) ) ; return getExprOpValue ( MI , MO , MO . getExpr ( ) , Fixups , STI ) ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> bool expand_a_shift ( machine_mode mode , enum rtx_code code , rtx operands [ ] ) { switch ( h8sx_classify_shift ( mode , code , operands [ 2 ] ) ) { case H8SX_SHIFT_BINARY : operands [ 1 ] = force_reg ( mode , operands [ 1 ] ) ; return false ; case H8SX_SHIFT_UNARY : return false ; case H8SX_SHIFT_NONE : break ; } emit_move_insn ( copy_rtx ( operands [ 0 ] ) , operands [ 1 ] ) ; if ( operands [ 2 ] == CONST0_RTX ( QImode ) ) ; else if ( GET_CODE ( operands [ 2 ] ) == CONST_INT && ! h8300_shift_needs_scratch_p ( INTVAL ( operands [ 2 ] ) , mode , code ) ) emit_insn ( gen_rtx_SET ( copy_rtx ( operands [ 0 ] ) , gen_rtx_fmt_ee ( code , mode , copy_rtx ( operands [ 1 ] ) , operands [ 2 ] ) ) ) ; else emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , gen_rtx_SET ( copy_rtx ( operands [ 0 ] ) , gen_rtx_fmt_ee ( code , mode , copy_rtx ( operands [ 0 ] ) , operands [ 2 ] ) ) , gen_rtx_CLOBBER ( VOIDmode , gen_rtx_SCRATCH ( QImode ) ) ) ) ) ; return true ; } </s>

Called from the .md file to emit code to do shifts . Returns a boolean indicating success ( currently this is always TRUE ) .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { TM = static_cast < const PPCTargetMachine * > ( & MF . getTarget ( ) ) ; TII = TM -> getInstrInfo ( ) ; bool Changed = false ; if ( MF . size ( ) < 2 ) return Changed ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed = true ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s>
bool
SystemZDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
SystemZAddressingMode
::
AddrForm
Form
;
SystemZAddressingMode
::
DispRange
DispRange
;
SDValue
Base
,
Disp
,
Index
;
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
case
InlineAsm
::
Constraint_Q
:
case
InlineAsm
::
Constraint_ZQ
:
Form
=
SystemZAddressingMode
::
FormBD
;
DispRange
=
SystemZAddressingMode
::
Disp12Only
;
break
;
case
InlineAsm
::
Constraint_R
:
case
InlineAsm
::
Constraint_ZR
:
Form
=
SystemZAddressingMode
::
FormBDXNormal
;
DispRange
=
SystemZAddressingMode
::
Disp12Only
;
break
;
case
InlineAsm
::
Constraint_S
:
case
InlineAsm
::
Constraint_ZS
:
Form
=
SystemZAddressingMode
::
FormBD
;
DispRange
=
SystemZAddressingMode
::
Disp20Only
;
break
;
case
InlineAsm
::
Constraint_T
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_o
:
case
InlineAsm
::
Constraint_p
:
case
InlineAsm
::
Constraint_ZT
:
Form
=
SystemZAddressingMode
::
FormBDXNormal
;
DispRange
=
SystemZAddressingMode
::
Disp20Only
;
break
;
}
if
(
selectBDXAddr
(
Form
,
DispRange
,
Op
,
Base
,
Disp
,
Index
)
)
{
const
TargetRegisterClass
*
TRC
=
Subtarget
->
getRegisterInfo
(
)
->
getPointerRegClass
(
*
MF
)
;
SDLoc
DL
(
Base
)
;
SDValue
RC
=
CurDAG
->
getTargetConstant
(
TRC
->
getID
(
)
,
DL
,
MVT
::
i32
)
;
if
(
Base
.
getOpcode
(
)
!=
ISD
::
TargetFrameIndex
&&
Base
.
getOpcode
(
)
!=
ISD
::
Register
)
{
Base
=
SDValue
(
CurDAG
->
getMachineNode
(
TargetOpcode
::
COPY_TO_REGCLASS
,
DL
,
Base
.
getValueType
(
)
,
Base
,
RC
)
,
0
)
;
}
if
(
Index
.
getOpcode
(
)
!=
ISD
::
Register
)
{
Index
=
SDValue
(
CurDAG
->
getMachineNode
(
TargetOpcode
::
COPY_TO_REGCLASS
,
DL
,
Index
.
getValueType
(
)
,
Index
,
RC
)
,
0
)
;
}
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Disp
)
;
OutOps
.
push_back
(
Index
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> rtx tilegx_return_addr ( int count , rtx frame ATTRIBUTE_UNUSED ) { if ( count != 0 ) return const0_rtx ; return get_hard_reg_initial_val ( Pmode , TILEGX_LINK_REGNUM ) ; } </s>

Return an RTX indicating where the return address to the calling function can be found .


<s> static inline bool offset_6bit_signed_scaled_p ( machine_mode mode , poly_int64 offset ) { HOST_WIDE_INT multiple ; return ( constant_multiple_p ( offset , GET_MODE_SIZE ( mode ) , & multiple ) && IN_RANGE ( multiple , - 32 , 31 ) ) ; } </s>

Return true if OFFSET is a signed 6-bit value multiplied by the size of MODE .


<s>
static
const
char
*
output_inline_const
(
machine_mode
mode
,
rtx
operands
[
]
)
{
HOST_WIDE_INT
x
=
0
,
y
=
0
;
int
trick_no
;
rtx
out_operands
[
3
]
;
char
buf
[
256
]
;
char
load_op
[
256
]
;
const
char
*
dst_fmt
;
HOST_WIDE_INT
value
;
value
=
INTVAL
(
operands
[
1
]
)
;
trick_no
=
try_constant_tricks
(
value
,
&
x
,
&
y
)
;
gcc_assert
(
trick_no
!=
0
)
;
if
(
trick_no
==
1
)
x
=
value
;
out_operands
[
0
]
=
operands
[
0
]
;
out_operands
[
1
]
=
GEN_INT
(
x
)
;
if
(
trick_no
>
2
)
out_operands
[
2
]
=
GEN_INT
(
y
)
;
if
(
mode
==
DImode
&&
(
!
TARGET_LITTLE_END
)
)
dst_fmt
=
"%R0"
;
else
dst_fmt
=
"%0"
;
if
(
x
>=
0
&&
x
<=
127
)
sprintf
(
load_op
,
"movi\t%s,%%1"
,
dst_fmt
)
;
else
if
(
CONST_OK_FOR_M
(
x
)
)
sprintf
(
load_op
,
"bgeni\t%s,%%P1"
,
dst_fmt
)
;
else
if
(
CONST_OK_FOR_N
(
x
)
)
sprintf
(
load_op
,
"bmaski\t%s,%%N1"
,
dst_fmt
)
;
else
{
sprintf
(
load_op
,
"BADMOVI-inline_const %s, %%1"
,
dst_fmt
)
;
gcc_unreachable
(
)
;
}
switch
(
trick_no
)
{
case
1
:
strcpy
(
buf
,
load_op
)
;
break
;
case
2
:
sprintf
(
buf
,
"%s\n\tnot\t%s\t// %ld 0x%lx"
,
load_op
,
dst_fmt
,
value
,
value
)
;
break
;
case
3
:
sprintf
(
buf
,
"%s\n\taddi\t%s,%%2\t// %ld 0x%lx"
,
load_op
,
dst_fmt
,
value
,
value
)
;
break
;
case
4
:
sprintf
(
buf
,
"%s\n\tsubi\t%s,%%2\t// %ld 0x%lx"
,
load_op
,
dst_fmt
,
value
,
value
)
;
break
;
case
5
:
sprintf
(
buf
,
"%s\n\trsubi\t%s,%%2\t// %ld 0x%lx"
,
load_op
,
dst_fmt
,
value
,
value
)
;
break
;
case
6
:
sprintf
(
buf
,
"%s\n\tbseti\t%s,%%P2\t// %ld 0x%lx"
,
load_op
,
dst_fmt
,
value
,
value
)
;
break
;
case
7
:
sprintf
(
buf
,
"%s\n\tbclri\t%s,%%Q2\t// %ld 0x%lx"
,
load_op
,
dst_fmt
,
value
,
value
)
;
break
;
case
8
:
sprintf
(
buf
,
"%s\n\trotli\t%s,%%2\t// %ld 0x%lx"
,
load_op
,
dst_fmt
,
value
,
value
)
;
break
;
case
9
:
sprintf
(
buf
,
"%s\n\tlsli\t%s,%%2\t// %ld 0x%lx"
,
load_op
,
dst_fmt
,
value
,
value
)
;
break
;
case
10
:
sprintf
(
buf
,
"%s\n\tixh\t%s,%s\t// %ld 0x%lx"
,
load_op
,
dst_fmt
,
dst_fmt
,
value
,
value
)
;
break
;
case
11
:
sprintf
(
buf
,
"%s\n\tixw\t%s,%s\t// %ld 0x%lx"
,
load_op
,
dst_fmt
,
dst_fmt
,
value
,
value
)
;
break
;
default
:
return
""
;
}
output_asm_insn
(
buf
,
out_operands
)
;
return
""
;
}
</s>


<s> unsigned getMaxInlineSizeThreshold ( ) const { return 64 ; } </s>

Returns the maximum memset / memcpy size that still makes it profitable to inline the call .


<s> bool PatmosPMLProfileImport :: runOnMachineFunction ( MachineFunction & MF ) { PMLMachineFunctionImport & PI = getAnalysis < PMLMachineFunctionImport > ( ) ; if ( ! PI . isAvailable ( ) ) return false ; PI . loadCriticalityMap ( ) ; PatmosMachineFunctionInfo & PMFI = * MF . getInfo < PatmosMachineFunctionInfo > ( ) ; PatmosAnalysisInfo & PAI = PMFI . getAnalysisInfo ( ) ; MachineBranchProbabilityInfo & MBPI = getAnalysis < MachineBranchProbabilityInfo > ( ) ; for ( MachineFunction :: iterator it = MF . begin ( ) , ie = MF . end ( ) ; it != ie ; it ++ ) { MachineBasicBlock * MBB = & * it ; double Crit = PI . getCriticalty ( MBB ) ; PAI . setCriticality ( MBB , Crit ) ; uint64_t Freq = PI . getWCETFrequency ( MBB ) ; PAI . setFrequency ( MBB , Freq ) ; for ( MachineBasicBlock :: succ_iterator succ = MBB -> succ_begin ( ) , se = MBB -> succ_end ( ) ; succ != se ; succ ++ ) { MachineBasicBlock * ToMBB = * succ ; uint32_t Weight ; if ( UseCritEdgeWeight ) { Weight = round ( PI . getCriticalty ( MBB , ToMBB , 1.0 ) * 10000.0 ) ; } else { Weight = PI . getWCETFrequency ( MBB , ToMBB , 0 ) ; } MBPI . setEdgeWeight ( MBB , succ , Weight ) ; } } return false ; } </s>


<s> static bool mips_lx_address_p ( rtx addr , machine_mode mode ) { if ( GET_CODE ( addr ) != PLUS || ! REG_P ( XEXP ( addr , 0 ) ) || ! REG_P ( XEXP ( addr , 1 ) ) ) return false ; if ( ISA_HAS_LBX && mode == QImode ) return true ; if ( ISA_HAS_LHX && mode == HImode ) return true ; if ( ISA_HAS_LWX && mode == SImode ) return true ; if ( ISA_HAS_LDX && mode == DImode ) return true ; return false ; } </s>

Return true if ADDR matches the pattern for the L { B , H , W , D } { , U } X load indexed address instruction . Note that such addresses are not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense , because their use is so restricted .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
Kind
==
KindReg
&&
"Not a register"
)
;
return
Reg
.
Num
;
}
</s>

Returns the register associated with this edge .


<s> static void sh_file_start ( void ) { default_file_start ( ) ; if ( TARGET_ELF ) fprintf ( asm_out_file , "%s\n" , TEXT_SECTION_ASM_OP ) ; else switch_to_section ( data_section ) ; if ( TARGET_LITTLE_ENDIAN ) fputs ( "\t.little\n" , asm_out_file ) ; if ( ! TARGET_ELF ) { if ( TARGET_SHCOMPACT ) fputs ( "\t.mode\tSHcompact\n" , asm_out_file ) ; else if ( TARGET_SHMEDIA ) fprintf ( asm_out_file , "\t.mode\tSHmedia\n\t.abi\t%i\n" , TARGET_SHMEDIA64 ? 64 : 32 ) ; } } </s>

Output the start of the assembler file .


<s>
static
void
output_indirect_thunk
(
enum
indirect_thunk_prefix
need_prefix
,
unsigned
int
regno
)
{
char
indirectlabel1
[
32
]
;
char
indirectlabel2
[
32
]
;
ASM_GENERATE_INTERNAL_LABEL
(
indirectlabel1
,
INDIRECT_LABEL
,
indirectlabelno
++
)
;
ASM_GENERATE_INTERNAL_LABEL
(
indirectlabel2
,
INDIRECT_LABEL
,
indirectlabelno
++
)
;
if
(
need_prefix
==
indirect_thunk_prefix_bnd
)
fputs
(
"\tbnd call\t"
,
asm_out_file
)
;
else
fputs
(
"\tcall\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
indirectlabel2
)
;
fputc
(
'\n'
,
asm_out_file
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
indirectlabel1
)
;
fprintf
(
asm_out_file
,
"\tpause\n\tlfence\n"
)
;
fputs
(
"\tjmp\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
indirectlabel1
)
;
fputc
(
'\n'
,
asm_out_file
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
indirectlabel2
)
;
if
(
regno
!=
INVALID_REGNUM
)
{
rtx
xops
[
2
]
;
xops
[
0
]
=
gen_rtx_MEM
(
word_mode
,
stack_pointer_rtx
)
;
xops
[
1
]
=
gen_rtx_REG
(
word_mode
,
regno
)
;
output_asm_insn
(
"mov\t{%1, %0|%0, %1}"
,
xops
)
;
}
else
{
rtx
xops
[
2
]
;
xops
[
0
]
=
stack_pointer_rtx
;
xops
[
1
]
=
plus_constant
(
Pmode
,
stack_pointer_rtx
,
UNITS_PER_WORD
)
;
output_asm_insn
(
"lea\t{%E1, %0|%0, %E1}"
,
xops
)
;
}
if
(
need_prefix
==
indirect_thunk_prefix_bnd
)
fputs
(
"\tbnd ret\n"
,
asm_out_file
)
;
else
fputs
(
"\tret\n"
,
asm_out_file
)
;
}
</s>

Output a call and return thunk for indirect branch . If BND_P is true , the BND prefix is needed . If REGNO ! = -1 , the function address is in REGNO and the call and return thunk looks like : call L2 L1 : pause lfence jmp L1 L2 : mov % REG , ( % sp ) ret Otherwise , the function address is on the top of stack and the call and return thunk looks like : call L2 L1 : pause lfence jmp L1 L2 : lea WORD_SIZE ( % sp ) , % sp ret


<s> static type_suffix_index parse_element_type ( const function_instance & instance , const char * & format ) { int ch = * format ++ ; if ( ch == 'f' || ch == 's' || ch == 'u' ) { type_class_index tclass = ( ch == 'f' ? TYPE_float : ch == 's' ? TYPE_signed : TYPE_unsigned ) ; char * end ; unsigned int bits = strtol ( format , & end , 10 ) ; format = end ; if ( bits == 0 || bits == 1 ) bits = instance . type_suffix ( bits ) . element_bits ; return find_type_suffix ( tclass , bits ) ; } if ( ch == 'w' ) { type_suffix_index suffix = parse_element_type ( instance , format ) ; if ( type_suffixes [ suffix ] . integer_p ) return find_type_suffix ( type_suffixes [ suffix ] . tclass , 64 ) ; return suffix ; } if ( ch == 'p' ) return TYPE_SUFFIX_b ; if ( ch == 'B' ) return TYPE_SUFFIX_bf16 ; if ( ch == 'q' ) { type_suffix_index suffix = parse_element_type ( instance , format ) ; return find_type_suffix ( type_suffixes [ suffix ] . tclass , type_suffixes [ suffix ] . element_bits / 4 ) ; } if ( ch == 'h' ) { type_suffix_index suffix = parse_element_type ( instance , format ) ; if ( suffix == TYPE_SUFFIX_b ) return suffix ; return find_type_suffix ( type_suffixes [ suffix ] . tclass , type_suffixes [ suffix ] . element_bits / 2 ) ; } if ( ch == '0' || ch == '1' ) return instance . type_suffix_ids [ ch - '0' ] ; gcc_unreachable ( ) ; } </s>

Parse and move past an element type in FORMAT and return it as a type suffix . The format is : [ 01 ] - the element type in type suffix 0 or 1 of INSTANCE f < bits > - a floating-point type with the given number of bits f [ 01 ] - a floating-point type with the same width as type suffix 0 or 1 B - bfloat16_t h < elt > - a half-sized version of < elt > p - a predicate ( represented as TYPE_SUFFIX_b ) q < elt > - a quarter-sized version of < elt > s < bits > - a signed type with the given number of bits s [ 01 ] - a signed type with the same width as type suffix 0 or 1 u < bits > - an unsigned type with the given number of bits u [ 01 ] - an unsigned type with the same width as type suffix 0 or 1 w < elt > - a 64-bit version of < elt > if < elt > is integral , otherwise < elt > where < elt > is another element type .


<s> int GCNTTIImpl :: getArithmeticReductionCost ( unsigned Opcode , VectorType * Ty , bool IsPairwise ) { EVT OrigTy = TLI -> getValueType ( DL , Ty ) ; if ( IsPairwise || ! ST -> hasVOP3PInsts ( ) || OrigTy . getScalarSizeInBits ( ) != 16 ) return BaseT :: getArithmeticReductionCost ( Opcode , Ty , IsPairwise ) ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; return LT . first * getFullRateInstrCost ( ) ; } </s>

Calculate the cost of vector reduction intrinsics .


<s> bool PPCPassConfig :: addIRTranslator ( ) { addPass ( new IRTranslator ( ) ) ; return false ; } </s>

This method should install an IR translator pass , which converts from LLVM code to machine instructions with possibly generic opcodes .


<s> bool X86AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( AsmVariant ) { printIntelMemReference ( * this , MI , OpNo , O ) ; return false ; } if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : break ; case 'H' : printMemReference ( * this , MI , OpNo , O , "H" ) ; return false ; case 'P' : printMemReference ( * this , MI , OpNo , O , "no-rip" ) ; return false ; } } printMemReference ( * this , MI , OpNo , O ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


The LTO frontend only enables exceptions when it sees a function that uses it . This changes the return value of dwarf2out_do_frame , so we have to check before every function .


<s> bool PIC16AsmPrinter :: doFinalization ( Module & M ) { EmitAllAutos ( M ) ; printLibcallDecls ( ) ; DbgInfo . EndModule ( M ) ; O << "\n\t" << "END\n" ; return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


"Instructions set to be inserted is empty!"

Fix up the placeholder we may add in genAlternativeCodeSequence ( ) .


<s>
bool
AMDGPUAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
SetupMachineFunction
(
MF
)
;
OutStreamer
.
emitRawComment
(
Twine
(
'@'
)
+
MF
.
getName
(
)
+
Twine
(
':'
)
)
;
MCContext
&
Context
=
getObjFileLowering
(
)
.
getContext
(
)
;
const
MCSectionELF
*
ConfigSection
=
Context
.
getELFSection
(
".AMDGPU.config"
,
ELF
::
SHT_PROGBITS
,
0
,
SectionKind
::
getReadOnly
(
)
)
;
OutStreamer
.
SwitchSection
(
ConfigSection
)
;
const
AMDGPUSubtarget
&
STM
=
TM
.
getSubtarget
<
AMDGPUSubtarget
>
(
)
;
SIProgramInfo
KernelInfo
;
if
(
STM
.
getGeneration
(
)
>
AMDGPUSubtarget
::
NORTHERN_ISLANDS
)
{
getSIProgramInfo
(
KernelInfo
,
MF
)
;
EmitProgramInfoSI
(
MF
,
KernelInfo
)
;
}
else
{
EmitProgramInfoR600
(
MF
)
;
}
DisasmLines
.
clear
(
)
;
HexLines
.
clear
(
)
;
DisasmLineMaxLen
=
0
;
OutStreamer
.
SwitchSection
(
getObjFileLowering
(
)
.
getTextSection
(
)
)
;
EmitFunctionBody
(
)
;
if
(
isVerbose
(
)
)
{
const
MCSectionELF
*
CommentSection
=
Context
.
getELFSection
(
".AMDGPU.csdata"
,
ELF
::
SHT_PROGBITS
,
0
,
SectionKind
::
getReadOnly
(
)
)
;
OutStreamer
.
SwitchSection
(
CommentSection
)
;
if
(
STM
.
getGeneration
(
)
>=
AMDGPUSubtarget
::
SOUTHERN_ISLANDS
)
{
OutStreamer
.
emitRawComment
(
" Kernel info:"
,
false
)
;
OutStreamer
.
emitRawComment
(
" codeLenInByte = "
+
Twine
(
KernelInfo
.
CodeLen
)
,
false
)
;
OutStreamer
.
emitRawComment
(
" NumSgprs: "
+
Twine
(
KernelInfo
.
NumSGPR
)
,
false
)
;
OutStreamer
.
emitRawComment
(
" NumVgprs: "
+
Twine
(
KernelInfo
.
NumVGPR
)
,
false
)
;
OutStreamer
.
emitRawComment
(
" FloatMode: "
+
Twine
(
KernelInfo
.
FloatMode
)
,
false
)
;
OutStreamer
.
emitRawComment
(
" IeeeMode: "
+
Twine
(
KernelInfo
.
IEEEMode
)
,
false
)
;
}
else
{
R600MachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
R600MachineFunctionInfo
>
(
)
;
OutStreamer
.
emitRawComment
(
Twine
(
"SQ_PGM_RESOURCES:STACK_SIZE = "
+
Twine
(
MFI
->
StackSize
)
)
)
;
}
}
if
(
STM
.
dumpCode
(
)
)
{
MF
.
dump
(
)
;
if
(
DisasmEnabled
)
{
OutStreamer
.
SwitchSection
(
Context
.
getELFSection
(
".AMDGPU.disasm"
,
ELF
::
SHT_NOTE
,
0
,
SectionKind
::
getReadOnly
(
)
)
)
;
for
(
size_t
i
=
0
;
i
<
DisasmLines
.
size
(
)
;
++
i
)
{
std
::
string
Comment
(
DisasmLineMaxLen
DisasmLines
[
i
]
.
size
(
)
,
' '
)
;
Comment
+=
" ; "
+
HexLines
[
i
]
+
"\n"
;
OutStreamer
.
EmitBytes
(
StringRef
(
DisasmLines
[
i
]
)
)
;
OutStreamer
.
EmitBytes
(
StringRef
(
Comment
)
)
;
}
}
}
return
false
;
}
</s>


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
k_Immediate
:
OS
<<
"Imm<"
;
OS
<<
*
Imm
.
Val
;
OS
<<
">"
;
break
;
case
k_Memory
:
OS
<<
"Mem<"
;
Mem
.
Base
->
print
(
OS
)
;
OS
<<
", "
;
OS
<<
*
Mem
.
Off
;
OS
<<
">"
;
break
;
case
k_PhysRegister
:
OS
<<
"PhysReg<"
<<
PhysReg
.
Num
<<
">"
;
break
;
case
k_RegisterIndex
:
OS
<<
"RegIdx<"
<<
RegIdx
.
Index
<<
":"
<<
RegIdx
.
Kind
<<
">"
;
break
;
case
k_Token
:
OS
<<
Tok
.
Data
;
break
;
case
k_RegList
:
OS
<<
"RegList< "
;
for
(
auto
Reg
:
(
*
RegList
.
List
)
)
OS
<<
Reg
<<
" "
;
OS
<<
">"
;
break
;
case
k_RegPair
:
OS
<<
"RegPair<"
<<
RegIdx
.
Index
<<
","
<<
RegIdx
.
Index
+
1
<<
">"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> void Finish ( ) { const size_t ContentsSize = Contents . size ( ) ; const size_t VendorHeaderSize = 4 + CurrentVendor . size ( ) + 1 ; const size_t TagHeaderSize = 1 + 4 ; Streamer . EmitIntValue ( VendorHeaderSize + TagHeaderSize + ContentsSize , 4 ) ; Streamer . EmitBytes ( CurrentVendor , 0 ) ; Streamer . EmitIntValue ( 0 , 1 ) ; Streamer . EmitIntValue ( ARMBuildAttrs :: File , 1 ) ; Streamer . EmitIntValue ( TagHeaderSize + ContentsSize , 4 ) ; Streamer . EmitBytes ( Contents , 0 ) ; Contents . clear ( ) ; } </s>

Finish - Do final processing and write the object to the output stream .


<s> CCAssignFn * CSKYTargetLowering :: CCAssignFnForReturn ( CallingConv :: ID CC , bool IsVarArg ) const { if ( IsVarArg || ! Subtarget . useHardFloatABI ( ) ) return RetCC_CSKY_ABIV2_SOFT ; else return RetCC_CSKY_ABIV2_FP ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> MachineBasicBlock * SITargetLowering :: EmitInstrWithCustomInserter ( MachineInstr * MI , MachineBasicBlock * BB ) const { MachineBasicBlock :: iterator I = * MI ; const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; switch ( MI -> getOpcode ( ) ) { default : return AMDGPUTargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; case AMDGPU :: BRANCH : return BB ; case AMDGPU :: SI_RegisterStorePseudo : { MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; unsigned Reg = MRI . createVirtualRegister ( & AMDGPU :: SReg_64RegClass ) ; MachineInstrBuilder MIB = BuildMI ( * BB , I , MI -> getDebugLoc ( ) , TII -> get ( AMDGPU :: SI_RegisterStore ) , Reg ) ; for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) MIB . addOperand ( MI -> getOperand ( i ) ) ; MI -> eraseFromParent ( ) ; break ; } } return BB ; } </s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> const Triple & getTargetTriple ( ) const { return TargetTriple ; } </s>

Get the target triple which is a string describing the target host .


<s> void SICTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; this -> TM = & static_cast < const SICTargetMachine & > ( TM ) ; } </s>

This method must be called before any actual lowering is done .


<s> void setReg ( unsigned Val ) { Contents . RegNum = Val ; } </s>

Assigns the associated register for this edge .


"attribute %<target%> argument not a string"

"FDPIC mode is not supported in Thumb-1 mode"

"invalid fpu for target attribute or pragma %qs"

"auto fpu selection not currently permitted here"

"invalid architecture for target attribute or pragma %qs"

"unknown target attribute or pragma %qs"

Inner function to process the attribute ( ( target ( ... ) ) ) , take an argument and set the current options from the argument . If we have a list , recursively go over the list .


<s> bool HSAILTargetLowering :: allowsMisalignedMemoryAccesses ( EVT , unsigned AddrSpace , unsigned Align , bool * Fast ) const { if ( Fast ) * Fast = true ; return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> static void tilegx_trampoline_init ( rtx m_tramp , tree fndecl , rtx static_chain ) { rtx fnaddr , chaddr ; rtx mem ; rtx begin_addr , end_addr ; int ptr_mode_size = GET_MODE_SIZE ( ptr_mode ) ; fnaddr = copy_to_reg ( XEXP ( DECL_RTL ( fndecl ) , 0 ) ) ; chaddr = copy_to_reg ( static_chain ) ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp , ptr_mode , TRAMPOLINE_SIZE - 2 * ptr_mode_size ) ; emit_move_insn ( mem , fnaddr ) ; mem = adjust_address ( m_tramp , ptr_mode , TRAMPOLINE_SIZE - ptr_mode_size ) ; emit_move_insn ( mem , chaddr ) ; begin_addr = force_reg ( Pmode , XEXP ( m_tramp , 0 ) ) ; end_addr = force_reg ( Pmode , plus_constant ( Pmode , XEXP ( m_tramp , 0 ) , TRAMPOLINE_SIZE ) ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , "__clear_cache" ) , LCT_NORMAL , VOIDmode , 2 , begin_addr , Pmode , end_addr , Pmode ) ; } </s>


<s>
SDValue
AVRTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
auto
CCFunction
=
CCAssignFnForReturn
(
CallConv
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
CCFunction
)
;
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
unsigned
e
=
RVLocs
.
size
(
)
;
if
(
e
>
1
)
{
std
::
reverse
(
RVLocs
.
begin
(
)
,
RVLocs
.
end
(
)
)
;
}
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
if
(
MF
.
getFunction
(
)
.
getAttributes
(
)
.
hasAttribute
(
AttributeList
::
FunctionIndex
,
Attribute
::
Naked
)
)
{
return
Chain
;
}
unsigned
RetOpc
=
(
CallConv
==
CallingConv
::
AVR_INTR
||
CallConv
==
CallingConv
::
AVR_SIGNAL
)
AVRISD
::
RETI_FLAG
:
AVRISD
::
RET_FLAG
;
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
{
RetOps
.
push_back
(
Flag
)
;
}
return
DAG
.
getNode
(
RetOpc
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static int riscv_binary_cost ( rtx x , int single_insns , int double_insns ) { if ( GET_MODE_SIZE ( GET_MODE ( x ) ) == UNITS_PER_WORD * 2 ) return COSTS_N_INSNS ( double_insns ) ; return COSTS_N_INSNS ( single_insns ) ; } </s>

Return the cost of binary operation X , given that the instruction sequence for a word-sized or smaller operation takes SIGNLE_INSNS instructions and that the sequence of a double-word operation takes DOUBLE_INSNS instructions .


<s> static void iq2000_va_start ( tree valist , rtx nextarg ) { int int_arg_words ; int gpr_save_area_size ; int_arg_words = crtl -> args . info . arg_words ; if ( int_arg_words < 8 ) gpr_save_area_size = ( 8 - int_arg_words ) * UNITS_PER_WORD ; else gpr_save_area_size = 0 ; nextarg = plus_constant ( Pmode , nextarg , - gpr_save_area_size ) ; std_expand_builtin_va_start ( valist , nextarg ) ; } </s>


<s> static int vfp3_const_double_index ( rtx x ) { REAL_VALUE_TYPE r , m ; int sign , exponent ; unsigned HOST_WIDE_INT mantissa , mant_hi ; unsigned HOST_WIDE_INT mask ; int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1 ; bool fail ; if ( ! TARGET_VFP3 || ! CONST_DOUBLE_P ( x ) ) return - 1 ; r = * CONST_DOUBLE_REAL_VALUE ( x ) ; if ( REAL_VALUE_ISINF ( r ) || REAL_VALUE_ISNAN ( r ) || REAL_VALUE_MINUS_ZERO ( r ) ) return - 1 ; sign = REAL_VALUE_NEGATIVE ( r ) ? 1 : 0 ; r = real_value_abs ( & r ) ; exponent = REAL_EXP ( & r ) ; real_ldexp ( & m , & r , point_pos - exponent ) ; wide_int w = real_to_integer ( & m , & fail , HOST_BITS_PER_WIDE_INT * 2 ) ; mantissa = w . elt ( 0 ) ; mant_hi = w . elt ( 1 ) ; if ( mantissa != 0 ) return - 1 ; point_pos -= HOST_BITS_PER_WIDE_INT ; mantissa = mant_hi ; mask = ( ( unsigned HOST_WIDE_INT ) 1 << ( point_pos - 5 ) ) - 1 ; if ( ( mantissa & mask ) != 0 ) return - 1 ; mantissa >>= point_pos - 5 ; if ( mantissa == 0 ) return - 1 ; gcc_assert ( mantissa >= 16 && mantissa <= 31 ) ; exponent = 5 - exponent ; if ( exponent < 0 || exponent > 7 ) return - 1 ; return ( sign << 7 ) | ( ( exponent ^ 3 ) << 4 ) | ( mantissa - 16 ) ; } </s>

Return an integer index for a VFPv3 immediate operand X suitable for the fconst [ sd ] instruction , or -1 if X is n't suitable .


<s>
Register
HexagonTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
const
MachineFunction
&
)
const
{
Register
Reg
=
StringSwitch
<
Register
>
(
RegName
)
.
Case
(
"r19"
,
Hexagon
::
R19
)
.
Default
(
Register
(
)
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) -> findAssociatedFragment ( ) ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s> static bool mips_need_noat_wrapper_p ( rtx_insn * insn , rtx * opvec , int noperands ) { if ( recog_memoized ( insn ) >= 0 ) { subrtx_iterator :: array_type array ; for ( int i = 0 ; i < noperands ; i ++ ) FOR_EACH_SUBRTX ( iter , array , opvec [ i ] , NONCONST ) if ( REG_P ( * iter ) && REGNO ( * iter ) == AT_REGNUM ) return true ; } return false ; } </s>

Return true if INSN needs to be wrapped in `` .set noat '' . INSN has NOPERANDS operands , stored in OPVEC .


<s>
MachineBasicBlock
*
SparcTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
,
DenseMap
<
MachineBasicBlock
*
,
MachineBasicBlock
*
>
*
EM
)
const
{
const
TargetInstrInfo
&
TII
=
*
getTargetMachine
(
)
.
getInstrInfo
(
)
;
unsigned
BROpcode
;
unsigned
CC
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown SELECT_CC!"
)
;
case
SP
::
SELECT_CC_Int_ICC
:
case
SP
::
SELECT_CC_FP_ICC
:
case
SP
::
SELECT_CC_DFP_ICC
:
BROpcode
=
SP
::
BCOND
;
break
;
case
SP
::
SELECT_CC_Int_FCC
:
case
SP
::
SELECT_CC_FP_FCC
:
case
SP
::
SELECT_CC_DFP_FCC
:
BROpcode
=
SP
::
FBCOND
;
break
;
}
CC
=
(
SPCC
::
CondCodes
)
MI
->
getOperand
(
3
)
.
getImm
(
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
It
=
BB
;
++
It
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
sinkMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
BROpcode
)
)
.
addMBB
(
sinkMBB
)
.
addImm
(
CC
)
;
F
->
insert
(
It
,
copy0MBB
)
;
F
->
insert
(
It
,
sinkMBB
)
;
for
(
MachineBasicBlock
::
succ_iterator
I
=
BB
->
succ_begin
(
)
,
E
=
BB
->
succ_end
(
)
;
I
!=
E
;
++
I
)
{
EM
->
insert
(
std
::
make_pair
(
*
I
,
sinkMBB
)
)
;
sinkMBB
->
addSuccessor
(
*
I
)
;
}
while
(
!
BB
->
succ_empty
(
)
)
BB
->
removeSuccessor
(
BB
->
succ_begin
(
)
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
sinkMBB
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
SP
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
F
->
DeleteMachineInstr
(
MI
)
;
return
BB
;
}
</s>


<s> static bool nios2_cannot_force_const_mem ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { return nios2_legitimate_constant_p ( mode , x ) == false ; } </s>


<s> MVT X86TargetLowering :: getPreferredSwitchConditionType ( LLVMContext & Context , EVT ConditionVT ) const { if ( ConditionVT . getSizeInBits ( ) < 32 ) return MVT :: i32 ; return TargetLoweringBase :: getPreferredSwitchConditionType ( Context , ConditionVT ) ; } </s>

Returns preferred type for switch condition .


<s> bool AMDGPUAlwaysInline :: runOnModule ( Module & M ) { std :: vector < GlobalAlias * > AliasesToRemove ; SmallPtrSet < Function * , 8 > FuncsToAlwaysInline ; SmallPtrSet < Function * , 8 > FuncsToNoInline ; for ( GlobalAlias & A : M . aliases ( ) ) { if ( Function * F = dyn_cast < Function > ( A . getAliasee ( ) ) ) { A . replaceAllUsesWith ( F ) ; AliasesToRemove . push_back ( & A ) ; } } if ( GlobalOpt ) { for ( GlobalAlias * A : AliasesToRemove ) { A -> eraseFromParent ( ) ; } } for ( GlobalVariable & GV : M . globals ( ) ) { unsigned AS = GV . getType ( ) -> getAddressSpace ( ) ; if ( AS != AMDGPUAS :: LOCAL_ADDRESS && AS != AMDGPUAS :: REGION_ADDRESS ) continue ; recursivelyVisitUsers ( GV , FuncsToAlwaysInline ) ; } if ( ! AMDGPUTargetMachine :: EnableFunctionCalls || StressCalls ) { auto IncompatAttr = StressCalls ? Attribute :: AlwaysInline : Attribute :: NoInline ; for ( Function & F : M ) { if ( ! F . isDeclaration ( ) && ! F . use_empty ( ) && ! F . hasFnAttribute ( IncompatAttr ) ) { if ( StressCalls ) { if ( ! FuncsToAlwaysInline . count ( & F ) ) FuncsToNoInline . insert ( & F ) ; } else FuncsToAlwaysInline . insert ( & F ) ; } } } for ( Function * F : FuncsToAlwaysInline ) F -> addFnAttr ( Attribute :: AlwaysInline ) ; for ( Function * F : FuncsToNoInline ) F -> addFnAttr ( Attribute :: NoInline ) ; return ! FuncsToAlwaysInline . empty ( ) || ! FuncsToNoInline . empty ( ) ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> TargetPassConfig * SICTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new SICPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> bool Z80AsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const { llvm_unreachable ( "Unimplemented" ) ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> static void ix86_option_override ( void ) { opt_pass * pass_insert_vzeroupper = make_pass_insert_vzeroupper ( g ) ; struct register_pass_info insert_vzeroupper_info = { pass_insert_vzeroupper , "reload" , 1 , PASS_POS_INSERT_AFTER } ; opt_pass * pass_stv = make_pass_stv ( g ) ; struct register_pass_info stv_info = { pass_stv , "combine" , 1 , PASS_POS_INSERT_AFTER } ; ix86_option_override_internal ( true , & global_options , & global_options_set ) ; register_pass ( & insert_vzeroupper_info ) ; register_pass ( & stv_info ) ; } </s>

Implement the TARGET_OPTION_OVERRIDE hook .


<s> void SparcDAGToDAGISel :: Select ( SDNode * N ) { SDLoc dl ( N ) ; if ( N -> isMachineOpcode ( ) ) { N -> setNodeId ( - 1 ) ; return ; } switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: INLINEASM : { if ( tryInlineAsm ( N ) ) return ; break ; } case SPISD :: GLOBAL_BASE_REG : ReplaceNode ( N , getGlobalBaseReg ( ) ) ; return ; case ISD :: SDIV : case ISD :: UDIV : { if ( N -> getValueType ( 0 ) == MVT :: i64 ) break ; SDValue DivLHS = N -> getOperand ( 0 ) ; SDValue DivRHS = N -> getOperand ( 1 ) ; SDValue TopPart ; if ( N -> getOpcode ( ) == ISD :: SDIV ) { TopPart = SDValue ( CurDAG -> getMachineNode ( SP :: SRAri , dl , MVT :: i32 , DivLHS , CurDAG -> getTargetConstant ( 31 , dl , MVT :: i32 ) ) , 0 ) ; } else { TopPart = CurDAG -> getRegister ( SP :: G0 , MVT :: i32 ) ; } TopPart = CurDAG -> getCopyToReg ( CurDAG -> getEntryNode ( ) , dl , SP :: Y , TopPart , SDValue ( ) ) . getValue ( 1 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: SDIV ? SP :: SDIVrr : SP :: UDIVrr ; CurDAG -> SelectNodeTo ( N , Opcode , MVT :: i32 , DivLHS , DivRHS , TopPart ) ; return ; } } SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s>
void
relaxInstruction
(
const
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
,
MCInst
&
Res
)
const
override
{
llvm_unreachable
(
"relaxInstruction() unimplemented"
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static inline int bpf_helper_code ( const char * name ) { int i ; for ( i = 1 ; i < BPF_BUILTIN_HELPER_MAX ; ++ i ) if ( strcmp ( name , bpf_helper_names [ i ] ) == 0 ) return i ; return 0 ; } </s>

Return the builtin code corresponding to the kernel helper builtin __builtin_NAME , or 0 if the name does n't correspond to a kernel helper builtin .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createAArch64ELFObjectWriter ( OS , OSABI , IsLittle ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> void notice_update_cc ( rtx body , rtx insn ) { rtx set ; switch ( get_attr_cc ( insn ) ) { case CC_NONE : break ; case CC_NONE_0HIT : if ( cc_status . value1 != 0 && reg_overlap_mentioned_p ( recog_data . operand [ 0 ] , cc_status . value1 ) ) cc_status . value1 = 0 ; if ( cc_status . value2 != 0 && reg_overlap_mentioned_p ( recog_data . operand [ 0 ] , cc_status . value2 ) ) cc_status . value2 = 0 ; break ; case CC_SET_ZN : CC_STATUS_INIT ; cc_status . flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY ; set = single_set ( insn ) ; cc_status . value1 = SET_SRC ( set ) ; if ( SET_DEST ( set ) != cc0_rtx ) cc_status . value2 = SET_DEST ( set ) ; break ; case CC_SET_ZNV : CC_STATUS_INIT ; cc_status . flags |= CC_NO_CARRY ; set = single_set ( insn ) ; cc_status . value1 = SET_SRC ( set ) ; if ( SET_DEST ( set ) != cc0_rtx ) { if ( GET_CODE ( SET_DEST ( set ) ) == STRICT_LOW_PART ) cc_status . value2 = XEXP ( SET_DEST ( set ) , 0 ) ; else cc_status . value2 = SET_DEST ( set ) ; } break ; case CC_COMPARE : CC_STATUS_INIT ; cc_status . value1 = SET_SRC ( body ) ; break ; case CC_CLOBBER : CC_STATUS_INIT ; break ; } } </s>

On the 68000 , all the insns to store in an address register fail to set the cc 's . However , in some cases these instructions can make it possibly invalid to use the saved cc 's . In those cases we clear out some or all of the saved cc 's so they wo n't be used .


<s> void X86PassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & LiveRangeShrinkID ) ; addPass ( createX86FixupSetCC ( ) ) ; addPass ( createX86OptimizeLEAs ( ) ) ; addPass ( createX86CallFrameOptimization ( ) ) ; } addPass ( createX86WinAllocaExpander ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static void frv_frame_insn ( rtx pattern , rtx dwarf_pattern ) { rtx insn = emit_insn ( pattern ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = alloc_EXPR_LIST ( REG_FRAME_RELATED_EXPR , dwarf_pattern , REG_NOTES ( insn ) ) ; } </s>

Emit a frame-related instruction whose pattern is PATTERN . The instruction is the last in a sequence that cumulatively performs the operation described by DWARF_PATTERN . The instruction is marked as frame-related and has a REG_FRAME_RELATED_EXPR note containing DWARF_PATTERN .


<s> const RegisterBankInfo * getRegBankInfo ( ) const override { return & RegBankInfo ; } </s>

If the information for the register banks is available , return it .


<s> bool HexagonInstrInfo :: analyzeCompare ( const MachineInstr * MI , unsigned & SrcReg , unsigned & SrcReg2 , int & Mask , int & Value ) const { unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case Hexagon :: CMPEHexagon4rr : case Hexagon :: CMPEQri : case Hexagon :: CMPEQrr : case Hexagon :: CMPGT64rr : case Hexagon :: CMPGTU64rr : case Hexagon :: CMPGTUri : case Hexagon :: CMPGTUrr : case Hexagon :: CMPGTri : case Hexagon :: CMPGTrr : case Hexagon :: CMPLTUrr : case Hexagon :: CMPLTrr : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; Mask = ~ 0 ; break ; case Hexagon :: CMPbEQri_V4 : case Hexagon :: CMPbEQrr_sbsb_V4 : case Hexagon :: CMPbEQrr_ubub_V4 : case Hexagon :: CMPbGTUri_V4 : case Hexagon :: CMPbGTUrr_V4 : case Hexagon :: CMPbGTrr_V4 : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; Mask = 0xFF ; break ; case Hexagon :: CMPhEQri_V4 : case Hexagon :: CMPhEQrr_shl_V4 : case Hexagon :: CMPhEQrr_xor_V4 : case Hexagon :: CMPhGTUri_V4 : case Hexagon :: CMPhGTUrr_V4 : case Hexagon :: CMPhGTrr_shl_V4 : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; Mask = 0xFFFF ; break ; } switch ( Opc ) { case Hexagon :: CMPEHexagon4rr : case Hexagon :: CMPEQrr : case Hexagon :: CMPGT64rr : case Hexagon :: CMPGTU64rr : case Hexagon :: CMPGTUrr : case Hexagon :: CMPGTrr : case Hexagon :: CMPbEQrr_sbsb_V4 : case Hexagon :: CMPbEQrr_ubub_V4 : case Hexagon :: CMPbGTUrr_V4 : case Hexagon :: CMPbGTrr_V4 : case Hexagon :: CMPhEQrr_shl_V4 : case Hexagon :: CMPhEQrr_xor_V4 : case Hexagon :: CMPhGTUrr_V4 : case Hexagon :: CMPhGTrr_shl_V4 : case Hexagon :: CMPLTUrr : case Hexagon :: CMPLTrr : SrcReg2 = MI -> getOperand ( 2 ) . getReg ( ) ; return true ; case Hexagon :: CMPEQri : case Hexagon :: CMPGTUri : case Hexagon :: CMPGTri : case Hexagon :: CMPbEQri_V4 : case Hexagon :: CMPbGTUri_V4 : case Hexagon :: CMPhEQri_V4 : case Hexagon :: CMPhGTUri_V4 : SrcReg2 = 0 ; Value = MI -> getOperand ( 2 ) . getImm ( ) ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> static rtx tilegx_text_label_rtx ( void ) { return cfun -> machine -> text_label_rtx ; } </s>

Return the register storing the value of the text label .


<s> const EpiphanySubtarget * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


"indirect call in function, which are not supported by eBPF"

Return the appropriate instruction to CALL to a function . TARGET is an RTX denoting the address of the called function . The main purposes of this function are : - To reject indirect CALL instructions , which are not supported by eBPF . - To recognize calls to kernel helper functions and emit the corresponding CALL N instruction . This function is called from the expansion of the 'call ' pattern in bpf.md .


<s> static reg_class_t arc_secondary_reload ( bool in_p , rtx x , reg_class_t cl , machine_mode mode , secondary_reload_info * sri ) { enum rtx_code code = GET_CODE ( x ) ; if ( cl == DOUBLE_REGS ) return GENERAL_REGS ; if ( ( cl == LPCOUNT_REG || cl == WRITABLE_CORE_REGS ) && in_p && MEM_P ( x ) ) return GENERAL_REGS ; if ( code == SUBREG ) { rtx addr = NULL_RTX ; x = SUBREG_REG ( x ) ; if ( REG_P ( x ) ) { int regno = REGNO ( x ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) regno = reg_renumber [ regno ] ; if ( regno != - 1 ) return NO_REGS ; if ( reg_equiv_mem ( REGNO ( x ) ) ) { rtx mem = reg_equiv_mem ( REGNO ( x ) ) ; addr = find_replacement ( & XEXP ( mem , 0 ) ) ; } } else { gcc_assert ( MEM_P ( x ) ) ; addr = XEXP ( x , 0 ) ; addr = simplify_rtx ( addr ) ; } if ( addr && GET_CODE ( addr ) == PLUS && CONST_INT_P ( XEXP ( addr , 1 ) ) && ( ! RTX_OK_FOR_OFFSET_P ( mode , XEXP ( addr , 1 ) ) ) ) { switch ( mode ) { case QImode : sri -> icode = in_p ? CODE_FOR_reload_qi_load : CODE_FOR_reload_qi_store ; break ; case HImode : sri -> icode = in_p ? CODE_FOR_reload_hi_load : CODE_FOR_reload_hi_store ; break ; default : break ; } } } return NO_REGS ; } </s>

For ARC base register + offset addressing , the validity of the address is mode-dependent for most of the offset range , as the offset can be scaled by the access size . We do n't expose these as mode-dependent addresses in the mode_dependent_address_p target hook , because that would disable lots of optimizations , and most uses of these addresses are for 32 or 64 bit accesses anyways , which are fine . However , that leaves some addresses for 8 / 16 bit values not properly reloaded by the generic code , which is why we have to schedule secondary reloads for these .


<s> void addLiveInAttr ( unsigned VReg , ISD :: ArgFlagsTy Flags ) { LiveInAttrs . push_back ( std :: make_pair ( VReg , Flags ) ) ; } </s>

This function associates attributes for each live-in virtual register .


<s> bool AVRFrameLowering :: hasFP ( const MachineFunction & MF ) const { const AVRMachineFunctionInfo * FuncInfo = MF . getInfo < AVRMachineFunctionInfo > ( ) ; return ( FuncInfo -> getHasSpills ( ) || FuncInfo -> getHasAllocas ( ) || FuncInfo -> getHasStackArgs ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void rs6000_asm_output_dwarf_datarel ( FILE * file , int size , const char * label ) { fputs ( integer_asm_op ( size , FALSE ) , file ) ; assemble_name ( file , label ) ; fputs ( "-__gcc_unwind_dbase" , file ) ; } </s>

Output a symbol offset relative to the dbase for the current object . We use __gcc_unwind_dbase as an arbitrary base for dbase and assume signed offsets . __gcc_unwind_dbase is embedded in all executables/libraries through libgcc/config/rs6000/crtdbase.S .


<s>
MipsSubtarget
::
MipsSubtarget
(
const
std
::
string
&
TT
,
const
std
::
string
&
CPU
,
const
std
::
string
&
FS
,
bool
little
,
Reloc
::
Model
_RM
,
MipsTargetMachine
*
_TM
)
:
MipsGenSubtargetInfo
(
TT
,
CPU
,
FS
)
,
MipsArchVersion
(
Mips32
)
,
MipsABI
(
UnknownABI
)
,
IsLittle
(
little
)
,
IsSingleFloat
(
false
)
,
IsFP64bit
(
false
)
,
IsGP64bit
(
false
)
,
HasVFPU
(
false
)
,
IsLinux
(
true
)
,
HasSEInReg
(
false
)
,
HasCondMov
(
false
)
,
HasSwap
(
false
)
,
HasBitCount
(
false
)
,
HasFPIdx
(
false
)
,
InMips16Mode
(
false
)
,
InMicroMipsMode
(
false
)
,
HasDSP
(
false
)
,
HasDSPR2
(
false
)
,
AllowMixed16_32
(
Mixed16_32
|
Mips_Os16
)
,
Os16
(
Mips_Os16
)
,
RM
(
_RM
)
,
OverrideMode
(
NoOverride
)
,
TM
(
_TM
)
{
std
::
string
CPUName
=
CPU
;
if
(
CPUName
.
empty
(
)
)
CPUName
=
"mips32"
;
ParseSubtargetFeatures
(
CPUName
,
FS
)
;
PreviousInMips16Mode
=
InMips16Mode
;
InstrItins
=
getInstrItineraryForCPU
(
CPUName
)
;
if
(
MipsABI
==
UnknownABI
)
MipsABI
=
hasMips64
(
)
N64
:
O32
;
assert
(
(
(
!
hasMips64
(
)
&&
(
isABI_O32
(
)
||
isABI_EABI
(
)
)
)
||
(
hasMips64
(
)
&&
(
isABI_N32
(
)
||
isABI_N64
(
)
)
)
)
&&
"Invalid  Arch & ABI pair."
)
;
if
(
TT
.
find
(
"linux"
)
==
std
::
string
::
npos
)
IsLinux
=
false
;
UseSmallSection
=
!
IsLinux
&&
(
RM
==
Reloc
::
Static
)
;
}
</s>

This constructor initializes the data members to match that of the specified triple .

Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
"mips32"
Mips
Mips
Mips
Mips
Mips
Mips
Mips
"Invalid  Arch & ABI pair."
"linux"


<s> bool isToken ( ) const { return Kind == Token ; } </s>


<s> unsigned ARMTargetLowering :: getJumpTableEncoding ( ) const { if ( Subtarget -> useInlineJumpTables ( ) ) { return MachineJumpTableInfo :: EK_Inline ; } else { return TargetLowering :: getJumpTableEncoding ( ) ; } } </s>

Return the entry encoding for a jump table in the current function .


<s> static void initiate_bundle_states ( void ) { bundle_states_num = 0 ; free_bundle_state_chain = NULL ; allocated_bundle_states_chain = NULL ; } </s>

Start work with abstract data ` bundle states ' .


<s> RCPair ARMTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { switch ( Constraint . size ( ) ) { case 1 : switch ( Constraint [ 0 ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: tGPRRegClass ) ; return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'h' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: hGPRRegClass ) ; break ; case 'r' : if ( Subtarget -> isThumb1Only ( ) ) return RCPair ( 0U , & ARM :: tGPRRegClass ) ; return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'w' : if ( VT == MVT :: Other ) break ; if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPRRegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPRRegClass ) ; break ; case 'x' : if ( VT == MVT :: Other ) break ; if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPR_8RegClass ) ; break ; case 't' : if ( VT == MVT :: Other ) break ; if ( VT == MVT :: f32 || VT == MVT :: i32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPR_VFP2RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPR_VFP2RegClass ) ; break ; } break ; case 2 : if ( Constraint [ 0 ] == 'T' ) { switch ( Constraint [ 1 ] ) { default : break ; case 'e' : return RCPair ( 0U , & ARM :: tGPREvenRegClass ) ; case 'o' : return RCPair ( 0U , & ARM :: tGPROddRegClass ) ; } } break ; default : break ; } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( ARM :: CPSR ) , & ARM :: CCRRegClass ) ; return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> static inline int and_xor_ior_costs ( rtx x , int code ) { const int cost_scale = GET_MODE_SIZE ( GET_MODE ( x ) ) > UNITS_PER_WORD ? 2 : 1 ; if ( ! CONST_INT_P ( XEXP ( x , 1 ) ) ) return 1 * cost_scale ; int i = INTVAL ( XEXP ( x , 1 ) ) ; if ( ( i == 0xff || i == 0xffff ) && code == AND ) return 1 * cost_scale ; if ( CONST_OK_FOR_K08 ( i ) ) return 2 * cost_scale ; if ( CONST_OK_FOR_I08 ( i ) ) return 2 * cost_scale ; return 3 * cost_scale ; } </s>

Return the cost of an AND/XOR/IOR operation .


<s> MachineBasicBlock * AMDGPUCFGStructurizer :: clone ( MachineBasicBlock * MBB ) { MachineFunction * Func = MBB -> getParent ( ) ; MachineBasicBlock * NewMBB = Func -> CreateMachineBasicBlock ( ) ; Func -> push_back ( NewMBB ) ; for ( MachineBasicBlock :: iterator It = MBB -> begin ( ) , E = MBB -> end ( ) ; It != E ; ++ It ) { MachineInstr * MI = Func -> CloneMachineInstr ( It ) ; NewMBB -> push_back ( MI ) ; } return NewMBB ; } </s>

Make a functionally equivalent copy of this MachineFunctionInfo in MF .


<s>
void
X86InstrInfo
::
replaceBranchWithTailCall
(
MachineBasicBlock
&
MBB
,
SmallVectorImpl
<
MachineOperand
>
&
BranchCond
,
const
MachineInstr
&
TailCall
)
const
{
assert
(
canMakeTailCallConditional
(
BranchCond
,
TailCall
)
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
!
I
->
isBranch
(
)
)
assert
(
0
&&
"Can't find the branch to replace!"
)
;
X86
::
CondCode
CC
=
getCondFromBranchOpc
(
I
->
getOpcode
(
)
)
;
assert
(
BranchCond
.
size
(
)
==
1
)
;
if
(
CC
!=
BranchCond
[
0
]
.
getImm
(
)
)
continue
;
break
;
}
unsigned
Opc
=
TailCall
.
getOpcode
(
)
==
X86
::
TCRETURNdi
X86
::
TCRETURNdicc
:
X86
::
TCRETURNdi64cc
;
auto
MIB
=
BuildMI
(
MBB
,
I
,
MBB
.
findDebugLoc
(
I
)
,
get
(
Opc
)
)
;
MIB
->
addOperand
(
TailCall
.
getOperand
(
0
)
)
;
MIB
.
addImm
(
0
)
;
MIB
->
addOperand
(
BranchCond
[
0
]
)
;
MIB
.
copyImplicitOps
(
TailCall
)
;
LivePhysRegs
LiveRegs
(
getRegisterInfo
(
)
)
;
LiveRegs
.
addLiveOuts
(
MBB
)
;
SmallVector
<
std
::
pair
<
unsigned
,
const
MachineOperand
*
>
,
8
>
Clobbers
;
LiveRegs
.
stepForward
(
*
MIB
,
Clobbers
)
;
for
(
const
auto
&
C
:
Clobbers
)
{
MIB
.
addReg
(
C
.
first
,
RegState
::
Implicit
)
;
MIB
.
addReg
(
C
.
first
,
RegState
::
Implicit
|
RegState
::
Define
)
;
}
I
->
eraseFromParent
(
)
;
}
</s>

Replace the conditional branch in MBB with a conditional tail call .


<s> Sched :: Preference PPCTargetLowering :: getSchedulingPreference ( SDNode * N ) const { unsigned Directive = PPCSubTarget . getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_440 || Directive == PPC :: DIR_A2 ) return Sched :: ILP ; return TargetLowering :: getSchedulingPreference ( N ) ; } </s>


<s>
void
ARMTTIImpl
::
getUnrollingPreferences
(
Loop
*
L
,
ScalarEvolution
&
SE
,
TTI
::
UnrollingPreferences
&
UP
)
{
if
(
!
ST
->
isMClass
(
)
)
return
BasicTTIImplBase
::
getUnrollingPreferences
(
L
,
SE
,
UP
)
;
UP
.
OptSizeThreshold
=
0
;
UP
.
PartialOptSizeThreshold
=
0
;
if
(
L
->
getHeader
(
)
->
getParent
(
)
->
hasOptSize
(
)
)
return
;
if
(
!
ST
->
isThumb2
(
)
)
return
;
SmallVector
<
BasicBlock
*
,
4
>
ExitingBlocks
;
L
->
getExitingBlocks
(
ExitingBlocks
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Loop has:\n"
<<
"Blocks: "
<<
L
->
getNumBlocks
(
)
<<
"\n"
<<
"Exit blocks: "
<<
ExitingBlocks
.
size
(
)
<<
"\n"
)
;
if
(
ExitingBlocks
.
size
(
)
>
2
)
return
;
if
(
ST
->
hasBranchPredictor
(
)
&&
L
->
getNumBlocks
(
)
>
4
)
return
;
if
(
getBooleanLoopAttribute
(
L
,
"llvm.loop.isvectorized"
)
)
return
;
unsigned
Cost
=
0
;
for
(
auto
*
BB
:
L
->
getBlocks
(
)
)
{
for
(
auto
&
I
:
*
BB
)
{
if
(
I
.
getType
(
)
->
isVectorTy
(
)
)
return
;
if
(
isa
<
CallInst
>
(
I
)
||
isa
<
InvokeInst
>
(
I
)
)
{
if
(
const
Function
*
F
=
cast
<
CallBase
>
(
I
)
.
getCalledFunction
(
)
)
{
if
(
!
isLoweredToCall
(
F
)
)
continue
;
}
return
;
}
SmallVector
<
const
Value
*
,
4
>
Operands
(
I
.
value_op_begin
(
)
,
I
.
value_op_end
(
)
)
;
Cost
+=
getUserCost
(
&
I
,
Operands
,
TargetTransformInfo
::
TCK_SizeAndLatency
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Cost of loop: "
<<
Cost
<<
"\n"
)
;
UP
.
Partial
=
true
;
UP
.
Runtime
=
true
;
UP
.
UpperBound
=
true
;
UP
.
UnrollRemainder
=
true
;
UP
.
DefaultUnrollRuntimeCount
=
4
;
UP
.
UnrollAndJam
=
true
;
UP
.
UnrollAndJamInnerLoopThreshold
=
60
;
if
(
Cost
<
12
)
UP
.
Force
=
true
;
}
</s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> static char * detect_caches_freebsd ( void ) { unsigned l1_sizekb , l1_line , l1_assoc , l2_sizekb ; size_t len = 4 ; sysctlbyname ( "machdep.cacheline_size" , & l1_line , & len , NULL , 0 ) ; l1_sizekb = 32 ; l1_assoc = 0 ; l2_sizekb = 512 ; return describe_cache ( l1_sizekb , l1_line , l1_assoc , l2_sizekb ) ; } </s>

Returns the description of caches on FreeBSD PPC .


<s> void WebAssemblyFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { uint64_t StackSize = MF . getFrameInfo ( ) . getStackSize ( ) ; if ( ! needsSP ( MF ) || ! needsSPWriteback ( MF ) ) return ; const auto * TII = MF . getSubtarget < WebAssemblySubtarget > ( ) . getInstrInfo ( ) ; auto & MRI = MF . getRegInfo ( ) ; auto InsertPt = MBB . getFirstTerminator ( ) ; DebugLoc DL ; if ( InsertPt != MBB . end ( ) ) DL = InsertPt -> getDebugLoc ( ) ; unsigned SPReg = 0 ; if ( hasBP ( MF ) ) { auto FI = MF . getInfo < WebAssemblyFunctionInfo > ( ) ; SPReg = FI -> getBasePointerVreg ( ) ; } else if ( StackSize ) { const TargetRegisterClass * PtrRC = MRI . getTargetRegisterInfo ( ) -> getPointerRegClass ( MF ) ; Register OffsetReg = MRI . createVirtualRegister ( PtrRC ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( WebAssembly :: CONST_I32 ) , OffsetReg ) . addImm ( StackSize ) ; SPReg = MRI . createVirtualRegister ( PtrRC ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( WebAssembly :: ADD_I32 ) , SPReg ) . addReg ( hasFP ( MF ) ? WebAssembly :: FP32 : WebAssembly :: SP32 ) . addReg ( OffsetReg ) ; } else { SPReg = hasFP ( MF ) ? WebAssembly :: FP32 : WebAssembly :: SP32 ; } writeSPToGlobal ( SPReg , MF , MBB , InsertPt , DL ) ; } </s>


<s> bool AArch64TTIImpl :: getTgtMemIntrinsic ( IntrinsicInst * Inst , MemIntrinsicInfo & Info ) { switch ( Inst -> getIntrinsicID ( ) ) { default : break ; case Intrinsic :: aarch64_neon_ld2 : case Intrinsic :: aarch64_neon_ld3 : case Intrinsic :: aarch64_neon_ld4 : Info . ReadMem = true ; Info . WriteMem = false ; Info . Vol = false ; Info . NumMemRefs = 1 ; Info . PtrVal = Inst -> getArgOperand ( 0 ) ; break ; case Intrinsic :: aarch64_neon_st2 : case Intrinsic :: aarch64_neon_st3 : case Intrinsic :: aarch64_neon_st4 : Info . ReadMem = false ; Info . WriteMem = true ; Info . Vol = false ; Info . NumMemRefs = 1 ; Info . PtrVal = Inst -> getArgOperand ( Inst -> getNumArgOperands ( ) - 1 ) ; break ; } switch ( Inst -> getIntrinsicID ( ) ) { default : return false ; case Intrinsic :: aarch64_neon_ld2 : case Intrinsic :: aarch64_neon_st2 : Info . MatchingId = VECTOR_LDST_TWO_ELEMENTS ; break ; case Intrinsic :: aarch64_neon_ld3 : case Intrinsic :: aarch64_neon_st3 : Info . MatchingId = VECTOR_LDST_THREE_ELEMENTS ; break ; case Intrinsic :: aarch64_neon_ld4 : case Intrinsic :: aarch64_neon_st4 : Info . MatchingId = VECTOR_LDST_FOUR_ELEMENTS ; break ; } return true ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> bool SPIRVPassConfig :: addGlobalInstructionSelect ( ) { addPass ( new SPIRVInstructionSelect ( ) ) ; return false ; } </s>

This method should install a ( global ) instruction selector pass , which converts possibly generic instructions to fully target-specific instructions , thereby constraining all generic virtual registers to register classes .


<s> bool Z80TargetLowering :: IsDesirableToPromoteOp ( SDValue Op , EVT & PVT ) const { if ( isDesirableToShrinkOp ( Op . getOpcode ( ) , MVT :: i24 , Op . getValueType ( ) ) ) return false ; PVT = MVT :: i24 ; return true ; } </s>

Return true if the target has native support for the specified value type and it is 'desirable ' to use the type .


<s> bool RV16KExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const RV16KInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : MF ) { for ( auto MBBI = MBB . begin ( ) ; MBBI != MBB . end ( ) ; ++ MBBI ) { Modified |= expandBccPseudo ( MBB , MBBI ) ; } } return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool X86InstrInfo :: isCoalescableExtInstr ( const MachineInstr & MI , unsigned & SrcReg , unsigned & DstReg , unsigned & SubIdx ) const { switch ( MI . getOpcode ( ) ) { default : break ; case X86 :: MOVSX16rr8 : case X86 :: MOVZX16rr8 : case X86 :: MOVSX32rr8 : case X86 :: MOVZX32rr8 : case X86 :: MOVSX64rr8 : if ( ! Subtarget . is64Bit ( ) ) return false ; LLVM_FALLTHROUGH ; case X86 :: MOVSX32rr16 : case X86 :: MOVZX32rr16 : case X86 :: MOVSX64rr16 : case X86 :: MOVSX64rr32 : { if ( MI . getOperand ( 0 ) . getSubReg ( ) || MI . getOperand ( 1 ) . getSubReg ( ) ) return false ; SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; DstReg = MI . getOperand ( 0 ) . getReg ( ) ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( "Unreachable!" ) ; case X86 :: MOVSX16rr8 : case X86 :: MOVZX16rr8 : case X86 :: MOVSX32rr8 : case X86 :: MOVZX32rr8 : case X86 :: MOVSX64rr8 : SubIdx = X86 :: sub_8bit ; break ; case X86 :: MOVSX32rr16 : case X86 :: MOVZX32rr16 : case X86 :: MOVSX64rr16 : SubIdx = X86 :: sub_16bit ; break ; case X86 :: MOVSX64rr32 : SubIdx = X86 :: sub_32bit ; break ; } return true ; } } return false ; } </s>

isCoalescableExtInstr - Return true if the instruction is a `` coalescable '' extension instruction .


<s> bool Z80FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB . getParent ( ) ; bool UseShadow = shouldUseShadow ( MF ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( UseShadow && ! Z80 :: I24RegClass . contains ( Reg ) && ! Z80 :: I16RegClass . contains ( Reg ) ) continue ; MachineInstrBuilder MIB ; if ( Reg == Z80 :: AF ) MIB = BuildMI ( MBB , MI , DL , TII . get ( Is24Bit ? Z80 :: POP24AF : Z80 :: POP16AF ) ) ; else MIB = BuildMI ( MBB , MI , DL , TII . get ( Is24Bit ? Z80 :: POP24r : Z80 :: POP16r ) , Reg ) ; MIB . setMIFlag ( MachineInstr :: FrameDestroy ) ; } if ( UseShadow ) shadowCalleeSavedRegisters ( MBB , MI , DL , MachineInstr :: FrameDestroy , CSI ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> MCallGraph * getCallGraph ( ) { return & MCG ; } </s>

The internal CallGraph around which the rest of this interface is wrapped .


<s> static bool isReturnBlock ( const MachineBasicBlock * MBB ) { for ( auto MI = MBB -> begin ( ) , ME = MBB -> end ( ) ; MI != ME ; MI ++ ) if ( MI -> isReturn ( ) ) return true ; return false ; } </s>

Convenience function that returns true if the block ends in a return instruction .


<s> bool mem_operand_gpr ( rtx op , machine_mode mode ) { unsigned HOST_WIDE_INT offset ; int extra ; rtx addr = XEXP ( op , 0 ) ; if ( TARGET_UPDATE && ( GET_CODE ( addr ) == PRE_INC || GET_CODE ( addr ) == PRE_DEC ) && mode_supports_pre_incdec_p ( mode ) && legitimate_indirect_address_p ( XEXP ( addr , 0 ) , false ) ) return true ; if ( ! rs6000_offsettable_memref_p ( op , mode , false ) ) return false ; op = address_offset ( addr ) ; if ( op == NULL_RTX ) return true ; offset = INTVAL ( op ) ; if ( TARGET_POWERPC64 && ( offset & 3 ) != 0 ) return false ; extra = GET_MODE_SIZE ( mode ) - UNITS_PER_WORD ; if ( extra < 0 ) extra = 0 ; if ( GET_CODE ( addr ) == LO_SUM ) offset = ( ( offset & 0xffff ) ^ 0x8000 ) - 0x8000 ; return offset + 0x8000 < 0x10000u - extra ; } </s>

Return true if the MEM operand is a memory operand suitable for use with a ( full width , possibly multiple ) gpr load/store . On powerpc64 this means the offset must be divisible by 4 . Implements ' Y ' constraint . Accept direct , indexed , offset , lo_sum and tocref . Since this is a constraint function we know the operand has satisfied a suitable memory predicate . Offsetting a lo_sum should not be allowed , except where we know by alignment that a 32k boundary is not crossed . Note that by `` offsetting '' here we mean a further offset to access parts of the MEM . It 's fine to have a lo_sum where the inner address is offset from a sym , since the same sym+offset will appear in the high part of the address calculation .


<s> bool R600InstrInfo :: FindSwizzleForVectorSlot ( const std :: vector < std :: vector < std :: pair < int , unsigned > > > & IGSrcs , std :: vector < R600InstrInfo :: BankSwizzle > & SwzCandidate , const std :: vector < std :: pair < int , unsigned > > & TransSrcs , R600InstrInfo :: BankSwizzle TransSwz ) const { unsigned ValidUpTo = 0 ; do { ValidUpTo = isLegalUpTo ( IGSrcs , SwzCandidate , TransSrcs , TransSwz ) ; if ( ValidUpTo == IGSrcs . size ( ) ) return true ; } while ( NextPossibleSolution ( SwzCandidate , ValidUpTo ) ) ; return false ; } </s>

Enumerate all possible Swizzle sequence to find one that can meet all read port requirements .


<s> unsigned X86InstrInfo :: getPartialRegUpdateClearance ( const MachineInstr * MI , unsigned OpNum , const TargetRegisterInfo * TRI ) const { if ( OpNum != 0 || ! hasPartialRegUpdate ( MI -> getOpcode ( ) ) ) return 0 ; const MachineOperand & MO = MI -> getOperand ( 0 ) ; unsigned Reg = MO . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { if ( MO . readsReg ( ) || MI -> readsVirtualRegister ( Reg ) ) return 0 ; } else { if ( MI -> readsRegister ( Reg , TRI ) ) return 0 ; } return 16 ; } </s>

Inform the BreakFalseDeps pass how many idle instructions we would like before a partial register update .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addPreserved < MachineFunctionAnalysis > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool VERegisterInfo :: isConstantPhysReg ( MCRegister PhysReg ) const { switch ( PhysReg ) { case VE :: VM0 : case VE :: VMP0 : return true ; default : return false ; } } </s>

Returns true if PhysReg is unallocatable and constant throughout the function .


<s> PredicatedBlock * SPScope :: getHeader ( ) const { return Priv -> Blocks . front ( ) ; } </s>

The header is the entry for each iteration .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < TargetPassConfig > ( ) ; } </s>


<s> static unsigned getReg ( const void * D , unsigned RC , unsigned RegNo ) { const AArch64Disassembler * Dis = static_cast < const AArch64Disassembler * > ( D ) ; return Dis -> getRegInfo ( ) -> getRegClass ( RC ) . getRegister ( RegNo ) ; } </s>

Returns the register associated with this edge .


<s> bool TOYTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; if ( ! CCInfo . CheckReturn ( Outs , RetCC_TOY ) ) { return false ; } if ( CCInfo . getNextStackOffset ( ) != 0 && isVarArg ) { return false ; } return true ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
auto
RegName
=
[
]
(
unsigned
Reg
)
{
if
(
Reg
)
return
CSKYInstPrinter
::
getRegisterName
(
Reg
)
;
else
return
"noreg"
;
}
;
switch
(
Kind
)
{
case
CPOP
:
OS
<<
*
getConstpoolOp
(
)
;
break
;
case
Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
KindTy
::
Register
:
OS
<<
"<register "
<<
RegName
(
getReg
(
)
)
<<
">"
;
break
;
case
RegisterSeq
:
OS
<<
"<register-seq "
;
OS
<<
RegName
(
getRegSeq
(
)
.
first
)
<<
"-"
<<
RegName
(
getRegSeq
(
)
.
second
)
<<
">"
;
break
;
case
RegisterList
:
OS
<<
"<register-list "
;
OS
<<
RegName
(
getRegList
(
)
.
List1From
)
<<
"-"
<<
RegName
(
getRegList
(
)
.
List1To
)
<<
","
;
OS
<<
RegName
(
getRegList
(
)
.
List2From
)
<<
"-"
<<
RegName
(
getRegList
(
)
.
List2To
)
<<
","
;
OS
<<
RegName
(
getRegList
(
)
.
List3From
)
<<
"-"
<<
RegName
(
getRegList
(
)
.
List3To
)
<<
","
;
OS
<<
RegName
(
getRegList
(
)
.
List4From
)
<<
"-"
<<
RegName
(
getRegList
(
)
.
List4To
)
;
break
;
case
Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> bool isVector ( ) const { llvm_unreachable ( "unimplemented" ) ; return false ; } </s>

Vector instructions are instructions that must fill all instruction slots within an instruction group .


"flag setting instruction only valid outside IT block"

"instruction only valid inside IT block"

"instruction variant requires ARMv6 or later"

"immediate operand must be in the range [0,15]"

"immediate operand must be in the range [0,239]"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> bool X86RegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ; if ( CantUseSP ( MFI ) ) return MRI -> canReserveReg ( BasePtr ) ; return true ; } </s>

True if the stack can be realigned for the target .


<s>
void
HexagonInstPrinter
::
printSymbol
(
const
MCInst
*
MI
,
unsigned
OpNo
,
raw_ostream
&
O
,
bool
hi
)
const
{
const
MCOperand
&
MO
=
MI
->
getOperand
(
OpNo
)
;
O
<<
'#'
<<
(
hi
"HI"
:
"LO"
)
<<
'('
;
if
(
MO
.
isImm
(
)
)
{
O
<<
'#'
;
printOperand
(
MI
,
OpNo
,
O
)
;
}
else
{
assert
(
"Unknown symbol operand"
)
;
printOperand
(
MI
,
OpNo
,
O
)
;
}
O
<<
')'
;
}
</s>

Hexagon
Hexagon
"HI"
"LO"
"Unknown symbol operand"


<s> virtual void releaseTopNode ( SUnit * SU ) { } </s>

SU has had all predecessor dependencies resolved .


<s> void sparc_initialize_trampoline ( rtx tramp , rtx fnaddr , rtx cxt ) { emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( tramp , 0 ) ) , expand_binop ( SImode , ior_optab , expand_shift ( RSHIFT_EXPR , SImode , fnaddr , size_int ( 10 ) , 0 , 1 ) , GEN_INT ( trunc_int_for_mode ( 0x03000000 , SImode ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( tramp , 4 ) ) , expand_binop ( SImode , ior_optab , expand_shift ( RSHIFT_EXPR , SImode , cxt , size_int ( 10 ) , 0 , 1 ) , GEN_INT ( trunc_int_for_mode ( 0x05000000 , SImode ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( tramp , 8 ) ) , expand_binop ( SImode , ior_optab , expand_and ( SImode , fnaddr , GEN_INT ( 0x3ff ) , NULL_RTX ) , GEN_INT ( trunc_int_for_mode ( 0x81c06000 , SImode ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( tramp , 12 ) ) , expand_binop ( SImode , ior_optab , expand_and ( SImode , cxt , GEN_INT ( 0x3ff ) , NULL_RTX ) , GEN_INT ( trunc_int_for_mode ( 0x8410a000 , SImode ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ) ; emit_insn ( gen_flush ( validize_mem ( gen_rtx_MEM ( SImode , tramp ) ) ) ) ; if ( sparc_cpu != PROCESSOR_ULTRASPARC && sparc_cpu != PROCESSOR_ULTRASPARC3 ) emit_insn ( gen_flush ( validize_mem ( gen_rtx_MEM ( SImode , plus_constant ( tramp , 8 ) ) ) ) ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , "__enable_execute_stack" ) , LCT_NORMAL , VOIDmode , 1 , tramp , Pmode ) ; } </s>

Emit RTL insns to initialize the variable parts of a trampoline . FNADDR is an RTX for the address of the function 's pure code . CXT is an RTX for the static chain value for the function . This takes 16 insns : 2 shifts & 2 ands ( to split up addresses ) , 4 sethi ( to load in opcodes ) , 4 iors ( to merge address and opcodes ) , and 4 writes ( to store insns ) . This is a bit excessive . Perhaps a different mechanism would be better here . Emit enough FLUSH insns to synchronize the data and instruction caches .


<s>
SDValue
MSP430TargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
isVarArg
,
Ins
,
dl
,
DAG
,
InVals
)
;
case
CallingConv
::
MSP430_INTR
:
if
(
Ins
.
empty
(
)
)
return
Chain
;
else
{
report_fatal_error
(
"ISRs cannot have arguments"
)
;
return
SDValue
(
)
;
}
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s>
bool
MipsConstantIslands
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
MF
=
&
mf
;
MCP
=
mf
.
getConstantPool
(
)
;
DEBUG
(
dbgs
(
)
<<
"constant island machine function "
<<
"\n"
)
;
if
(
!
TM
.
getSubtarget
<
MipsSubtarget
>
(
)
.
inMips16Mode
(
)
||
!
MipsSubtarget
::
useConstantIslands
(
)
)
{
return
false
;
}
TII
=
(
const
MipsInstrInfo
*
)
MF
->
getTarget
(
)
.
getInstrInfo
(
)
;
DEBUG
(
dbgs
(
)
<<
"constant island processing "
<<
"\n"
)
;
prescanForConstants
(
)
;
MF
->
getRegInfo
(
)
.
invalidateLiveness
(
)
;
MF
->
RenumberBlocks
(
)
;
std
::
vector
<
MachineInstr
*
>
CPEMIs
;
if
(
!
MCP
->
isEmpty
(
)
)
doInitialPlacement
(
CPEMIs
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .

Mips
Mips
"constant island machine function "
"\n"
Mips
Mips
Mips
Mips
"constant island processing "
"\n"


<s> unsigned HexagonInstrInfo :: getUnits ( const MachineInstr * MI ) const { const TargetSubtargetInfo & ST = MI -> getParent ( ) -> getParent ( ) -> getSubtarget ( ) ; const InstrItineraryData & II = * ST . getInstrItineraryData ( ) ; const InstrStage & IS = * II . beginStage ( MI -> getDesc ( ) . getSchedClass ( ) ) ; return IS . getUnits ( ) ; } </s>