<s> bool PPCTargetLowering :: SelectAddressEVXRegReg ( SDValue N , SDValue & Base , SDValue & Index , SelectionDAG & DAG ) const { for ( SDNode * U : N -> uses ( ) ) { if ( MemSDNode * Memop = dyn_cast < MemSDNode > ( U ) ) { if ( Memop -> getMemoryVT ( ) == MVT :: f64 ) { Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } } } return false ; } </s>

SelectAddressEVXRegReg - Given the specified addressed , check to see if it can be more efficiently represented as [ r+imm ] .


<s> static unsigned size ( const GraphType & G ) { return G . getNodes ( ) . size ( ) ; } </s>

The number of name/type pairs is returned .


<s>
void
MetadataStreamer
::
verify
(
StringRef
HSAMetadataString
)
const
{
errs
(
)
<<
"AMDGPU HSA Metadata Parser Test: "
;
HSAMD
::
Metadata
FromHSAMetadataString
;
if
(
fromString
(
HSAMetadataString
,
FromHSAMetadataString
)
)
{
errs
(
)
<<
"FAIL\n"
;
return
;
}
std
::
string
ToHSAMetadataString
;
if
(
toString
(
FromHSAMetadataString
,
ToHSAMetadataString
)
)
{
errs
(
)
<<
"FAIL\n"
;
return
;
}
errs
(
)
<<
(
HSAMetadataString
==
ToHSAMetadataString
"PASS"
:
"FAIL"
)
<<
'\n'
;
if
(
HSAMetadataString
!=
ToHSAMetadataString
)
{
errs
(
)
<<
"Original input: "
<<
HSAMetadataString
<<
'\n'
<<
"Produced output: "
<<
ToHSAMetadataString
<<
'\n'
;
}
}
</s>

AMDGPU
"AMDGPU HSA Metadata Parser Test: "
"FAIL\n"
"FAIL\n"
"PASS"
"FAIL"
"Original input: "
"Produced output: "


"insertBranch must not be told to insert a fallthrough"

"P2 branch conditions have one component!"

"Unconditional branch with multiple successors!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> PPCGenScalarMASSEntries ( ) : ModulePass ( ID ) { ScalarMASSFuncs = { } ; } </s>


<s> static void insertNoops ( int NopCnt , const TPCMCCodeEmitter * CE , raw_ostream & OS ) { if ( NopCnt == 0 ) return ; APInt DummyInstruction ( TPCII :: InstructionSize , 0 ) ; APInt DSPUSlot ( TPCII :: SPUSize , TPCII :: spuNOP ) ; APInt DVPUSlot ( TPCII :: VPUSize , TPCII :: vpuNOP ) ; APInt DLDSlot ( TPCII :: LDSize , TPCII :: ldNOP << 16 ) ; APInt DSTSlot ( TPCII :: STSize , TPCII :: stNOP << 16 ) ; APInt DImmValue ( TPCII :: ImmSize , 0 ) ; DummyInstruction |= DSPUSlot . zext ( TPCII :: InstructionSize ) . shl ( TPCII :: SPUStart ) ; DummyInstruction |= DVPUSlot . zext ( TPCII :: InstructionSize ) . shl ( TPCII :: VPUStart ) ; DummyInstruction |= DLDSlot . zext ( TPCII :: InstructionSize ) . shl ( TPCII :: LDStart ) ; DummyInstruction |= DSTSlot . zext ( TPCII :: InstructionSize ) . shl ( TPCII :: STStart ) ; DummyInstruction |= DImmValue . zext ( TPCII :: InstructionSize ) . shl ( TPCII :: ImmStart ) ; for ( int i = 0 ; i < NopCnt ; ++ i ) { EmitInstruction ( DummyInstruction , TPCII :: InstructionSize , OS ) ; } } </s>

Insert noops into the instruction stream at the specified point .

TPC TPC 0 TPC 0 TPC TPC TPC TPC TPC TPC 16 TPC TPC 16 TPC 0 TPC TPC TPC TPC TPC TPC TPC TPC TPC TPC 0 TPC


<s>
void
print
(
DiagnosticPrinter
&
DP
)
const
override
{
std
::
string
Str
;
raw_string_ostream
OS
(
Str
)
;
if
(
DLoc
)
{
DILocation
DIL
(
DLoc
.
getAsMDNode
(
)
)
;
StringRef
Filename
=
DIL
.
getFilename
(
)
;
unsigned
Line
=
DIL
.
getLineNumber
(
)
;
unsigned
Column
=
DIL
.
getColumnNumber
(
)
;
OS
<<
Filename
<<
':'
<<
Line
<<
':'
<<
Column
<<
' '
;
}
OS
<<
"in function "
<<
Fn
.
getName
(
)
<<
' '
<<
*
Fn
.
getFunctionType
(
)
<<
'\n'
<<
Description
;
if
(
Value
)
Value
->
print
(
OS
)
;
OS
<<
'\n'
;
OS
.
flush
(
)
;
DP
<<
Str
;
}
</s>

print - Print a debug representation of the operand to the given stream .


"insufficient arguments to overloaded function %s"

"too many arguments to overloaded function %s"

"parameter list does not match a valid signature for %s()"

target hook for resolve_overloaded_builtin ( ) . Returns a function call RTX if we can resolve the overloaded builtin


<s> bool HexagonInstrInfo :: isComplex ( const MachineInstr & MI ) const { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const TargetInstrInfo * TII = MF -> getSubtarget ( ) . getInstrInfo ( ) ; const HexagonInstrInfo * QII = ( const HexagonInstrInfo * ) TII ; if ( ! ( isTC1 ( MI ) ) && ! ( QII -> isTC2Early ( MI ) ) && ! ( MI . getDesc ( ) . mayLoad ( ) ) && ! ( MI . getDesc ( ) . mayStore ( ) ) && ( MI . getDesc ( ) . getOpcode ( ) != Hexagon :: S2_allocframe ) && ( MI . getDesc ( ) . getOpcode ( ) != Hexagon :: L2_deallocframe ) && ! ( QII -> isMemOp ( MI ) ) && ! ( MI . isBranch ( ) ) && ! ( MI . isReturn ( ) ) && ! MI . isCall ( ) ) return true ; return false ; } </s>

Return whether the location is computed on the expression stack , meaning it can not be a simple register location .

Hexagon Hexagon Hexagon Hexagon Hexagon::S2_allocframe Hexagon::L2_deallocframe


<s> const char * SICTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case SICISD :: JmpLink : return "SICISD::JmpLink" ; case SICISD :: TailCall : return "SICISD::TailCall" ; case SICISD :: Hi : return "SICISD::Hi" ; case SICISD :: Lo : return "SICISD::Lo" ; case SICISD :: GPRel : return "SICISD::GPRel" ; case SICISD :: Glob : return "SICISD::Glob" ; case SICISD :: Ret : return "SICISD::Ret" ; case SICISD :: EH_RETURN : return "SICISD::EH_RETURN" ; case SICISD :: DivRem : return "SICISD::DivRem" ; case SICISD :: DivRemU : return "SICISD::DivRemU" ; case SICISD :: Wrapper : return "SICISD::Wrapper" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific

SIC SIC SICISD::JmpLink "SICISD::JmpLink" SICISD::TailCall "SICISD::TailCall" SICISD::Hi "SICISD::Hi" SICISD::Lo "SICISD::Lo" SICISD::GPRel "SICISD::GPRel" SICISD::Glob "SICISD::Glob" SICISD::Ret "SICISD::Ret" SICISD::EH_RETURN "SICISD::EH_RETURN" SICISD::DivRem "SICISD::DivRem" SICISD::DivRemU "SICISD::DivRemU" SICISD::Wrapper "SICISD::Wrapper"


<s> virtual const SPUInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> void print ( raw_ostream & OS , const TargetMachine * TM = nullptr ) const { const TargetRegisterInfo * TRI = TM ? TM -> getSubtargetImpl ( ) -> getRegisterInfo ( ) : nullptr ; if ( isReg ( ) ) { OS << PrintReg ( Contents . R . Reg , TRI , Contents . R . Sub ) ; } if ( isImm ( ) ) { OS << Contents . ImmVal ; } } </s>


"Tiny codesize model not supported on X86"

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s> static bool compare_sign_p ( rtx_insn * insn ) { RTX_CODE cond = compare_condition ( insn ) ; return ( cond == GE || cond == LT ) ; } </s>

Returns nonzero if INSN is a tst insn that only tests the sign .


"WebAssembly doesn't support non-C calling conventions"

"WebAssembly doesn't support varargs yet"

"WebAssembly doesn't support struct return yet"

"WebAssembly hasn't implemented zext arguments"

"WebAssembly hasn't implemented sext arguments"

"WebAssembly hasn't implemented inreg arguments"

"WebAssembly hasn't implemented sret arguments"

"WebAssembly hasn't implemented byval arguments"

"WebAssembly hasn't implemented inalloca arguments"

"WebAssembly hasn't implemented nest arguments"

"WebAssembly hasn't implemented returned arguments"

"WebAssembly hasn't implemented cons regs arguments"

"WebAssembly hasn't implemented cons regs last arguments"

"WebAssembly hasn't implemented split arguments"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> unsigned int Z80Operand :: getReg ( ) const { return this -> Reg . RegNumber ; } </s>

Returns the register associated with this edge .


<s> void s390_expand_vec_compare ( rtx target , enum rtx_code cond , rtx cmp_op1 , rtx cmp_op2 ) { machine_mode mode = GET_MODE ( target ) ; bool neg_p = false , swap_p = false ; rtx tmp ; if ( GET_MODE_CLASS ( GET_MODE ( cmp_op1 ) ) == MODE_VECTOR_FLOAT ) { switch ( cond ) { case NE : cond = EQ ; neg_p = true ; break ; case UNGT : cond = GE ; neg_p = true ; swap_p = true ; break ; case UNGE : cond = GT ; neg_p = true ; swap_p = true ; break ; case LE : cond = GE ; swap_p = true ; break ; case UNLE : cond = GT ; neg_p = true ; break ; case LT : cond = GT ; swap_p = true ; break ; case UNLT : cond = GE ; neg_p = true ; break ; case UNEQ : emit_insn ( gen_vec_cmpuneqv2df ( target , cmp_op1 , cmp_op2 ) ) ; return ; case LTGT : emit_insn ( gen_vec_cmpltgtv2df ( target , cmp_op1 , cmp_op2 ) ) ; return ; case ORDERED : emit_insn ( gen_vec_orderedv2df ( target , cmp_op1 , cmp_op2 ) ) ; return ; case UNORDERED : emit_insn ( gen_vec_unorderedv2df ( target , cmp_op1 , cmp_op2 ) ) ; return ; default : break ; } } else { switch ( cond ) { case NE : cond = EQ ; neg_p = true ; break ; case GE : cond = GT ; neg_p = true ; swap_p = true ; break ; case GEU : cond = GTU ; neg_p = true ; swap_p = true ; break ; case LE : cond = GT ; neg_p = true ; break ; case LEU : cond = GTU ; neg_p = true ; break ; case LT : cond = GT ; swap_p = true ; break ; case LTU : cond = GTU ; swap_p = true ; break ; default : break ; } } if ( swap_p ) { tmp = cmp_op1 ; cmp_op1 = cmp_op2 ; cmp_op2 = tmp ; } emit_insn ( gen_rtx_SET ( target , gen_rtx_fmt_ee ( cond , mode , cmp_op1 , cmp_op2 ) ) ) ; if ( neg_p ) emit_insn ( gen_rtx_SET ( target , gen_rtx_NOT ( mode , target ) ) ) ; } </s>

Generate a vector comparison COND of CMP_OP1 and CMP_OP2 and store the result in TARGET .


<s> static bool visium_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( GP_REGISTER_P ( regno ) ) return GP_REGISTER_P ( end_hard_regno ( mode , regno ) - 1 ) ; if ( FP_REGISTER_P ( regno ) ) return mode == SFmode || ( mode == SImode && TARGET_FPU_IEEE ) ; return ( GET_MODE_CLASS ( mode ) == MODE_INT && visium_hard_regno_nregs ( regno , mode ) == 1 ) ; } </s>

Implement TARGET_HARD_REGNO_MODE_OK . Modes with sizes which cross from the one register class to the other can not be allowed . Only single floats are allowed in the floating point registers , and only fixed point values in the EAM registers .


<s> SDNode * PPCDAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * PPCSubTarget -> getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; const Module * M = MF -> getFunction ( ) -> getParent ( ) ; DebugLoc dl ; if ( PPCLowering -> getPointerTy ( CurDAG -> getDataLayout ( ) ) == MVT :: i32 ) { if ( PPCSubTarget -> isTargetELF ( ) ) { GlobalBaseReg = PPC :: R30 ; if ( M -> getPICLevel ( ) == PICLevel :: SmallPIC ) { BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MoveGOTtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; MF -> getInfo < PPCFunctionInfo > ( ) -> setUsesPICBase ( true ) ; } else { BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; unsigned TempReg = RegInfo -> createVirtualRegister ( & PPC :: GPRCRegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: UpdateGBR ) , GlobalBaseReg ) . addReg ( TempReg , RegState :: Define ) . addReg ( GlobalBaseReg ) ; MF -> getInfo < PPCFunctionInfo > ( ) -> setUsesPICBase ( true ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: GPRC_NOR0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: G8RC_NOX0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR8 ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR8 ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , PPCLowering -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

PowerPC PPC PPC PPC MVT::i32 PPC PPC::R30 PPC::MoveGOTtoLR PPC::MFLR PPC PPC::MovePCtoLR PPC::MFLR PPC::GPRCRegClass PPC::UpdateGBR PPC PPC::GPRC_NOR0RegClass PPC::MovePCtoLR PPC::MFLR PPC::G8RC_NOX0RegClass PPC::MovePCtoLR8 PPC::MFLR8 PPC


<s> static bool alpha_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( IN_RANGE ( regno , 32 , 62 ) ) return ( mode == SFmode || mode == DFmode || mode == DImode || mode == SCmode || mode == DCmode ) ; return true ; } </s>

Implement TARGET_HARD_REGNO_MODE_OK . On Alpha , the integer registers can hold any mode . The floating-point registers can hold 64-bit integers as well , but not smaller values .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF ; } </s>

Return information about object file lowering .


<s> void setFrameAdjustment ( MachineInstr & I , int64_t V ) const { assert ( isFrameInstr ( I ) ) ; I . getOperand ( 1 ) . setImm ( V ) ; } </s>

Sets the stack pointer adjustment made inside the frame made up by this instruction .


<s> int ARM64TargetLowering :: getScalingFactorCost ( const AddrMode & AM , Type * Ty ) const { if ( isLegalAddressingMode ( AM , Ty ) ) return AM . Scale != 0 && AM . Scale != 1 ; return - 1 ; } </s>

Return the cost of the scaling factor used in the addressing mode represented by AM for this target , for a load/store of the specified type .


"********** Fixing br_table Default Targets **********\n"

runOnMachineFunction - Emit the function body .


<s> void AArch64CA53ErratumStub :: applyFixup ( FragmentRef & pSrcFragRef , IRBuilder & pBuilder , BranchIsland & pIsland ) { assert ( isMyDuty ( pSrcFragRef ) ) ; std :: string sym_name ( "__" ) ; sym_name . append ( name ( ) ) . append ( llvm :: utohexstr ( pIsland . numOfStubs ( ) ) ) . append ( "@" ) . append ( pIsland . name ( ) ) ; LDSymbol * stub_sym = pBuilder . AddSymbol < IRBuilder :: Force , IRBuilder :: Unresolve > ( sym_name , ResolveInfo :: NoType , ResolveInfo :: Define , ResolveInfo :: Local , size ( ) , initSymValue ( ) , FragmentRef :: Create ( * this , initSymValue ( ) ) , ResolveInfo :: Default ) ; setSymInfo ( stub_sym -> resolveInfo ( ) ) ; FragmentRef * target = FragmentRef :: Create ( * pSrcFragRef . frag ( ) , pSrcFragRef . offset ( ) + getErratumInsnOffset ( ) + AArch64InsnHelpers :: InsnSize ) ; ResolveInfo * target_info = pBuilder . CreateLocalSymbol ( * target ) ; fixup_iterator it = fixup_begin ( ) ; Relocation * reloc = Relocation :: Create ( ( * it ) -> type ( ) , * ( FragmentRef :: Create ( * this , ( * it ) -> offset ( ) ) ) , ( * it ) -> addend ( ) ) ; reloc -> setSymInfo ( target_info ) ; std :: unique_ptr < unsigned [ ] > code ( new unsigned [ getErratumSequenceSize ( ) / 4 ] ) ; pSrcFragRef . memcpy ( code . get ( ) , getErratumSequenceSize ( ) , 0 ) ; reloc -> target ( ) = code [ getErratumInsnOffset ( ) / AArch64InsnHelpers :: InsnSize ] ; pIsland . addRelocation ( * reloc ) ; ++ it ; reloc = Relocation :: Create ( ( * it ) -> type ( ) , * ( FragmentRef :: Create ( * this , ( * it ) -> offset ( ) ) ) , ( * it ) -> addend ( ) ) ; reloc -> setSymInfo ( target_info ) ; reloc -> target ( ) = AArch64InsnHelpers :: buildBranchInsn ( ) ; pIsland . addRelocation ( * reloc ) ; assert ( ( ++ it ) == fixup_end ( ) ) ; } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
void
Z80oldInstrInfo
::
reMaterialize
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DstReg
,
unsigned
SubIdx
,
const
MachineInstr
&
Orig
,
const
TargetRegisterInfo
&
TRI
)
const
{
if
(
!
Orig
.
modifiesRegister
(
Z80old
::
F
,
&
TRI
)
||
MBB
.
computeRegisterLiveness
(
&
TRI
,
Z80old
::
F
,
I
)
==
MachineBasicBlock
::
LQR_Dead
)
{
return
TargetInstrInfo
::
reMaterialize
(
MBB
,
I
,
DstReg
,
SubIdx
,
Orig
,
TRI
)
;
}
unsigned
Opc
;
int
Val
;
switch
(
Orig
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unexpected instruction!"
)
;
case
Z80old
::
LD8r0
:
Opc
=
Z80old
::
LD8ri
;
Val
=
0
;
break
;
}
BuildMI
(
MBB
,
I
,
Orig
.
getDebugLoc
(
)
,
get
(
Opc
)
)
.
addReg
(
DstReg
,
RegState
::
Define
,
SubIdx
)
.
addImm
(
Val
)
;
}
</s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s> MachineInstrBuilder SIInstrInfo :: buildIndirectWrite ( MachineBasicBlock * MBB , MachineBasicBlock :: iterator I , unsigned ValueReg , unsigned Address , unsigned OffsetReg ) const { const DebugLoc & DL = MBB -> findDebugLoc ( I ) ; unsigned IndirectBaseReg = AMDGPU :: VGPR_32RegClass . getRegister ( getIndirectIndexBegin ( * MBB -> getParent ( ) ) ) ; return BuildMI ( * MBB , I , DL , get ( AMDGPU :: SI_INDIRECT_DST_V1 ) ) . addReg ( IndirectBaseReg , RegState :: Define ) . addOperand ( I -> getOperand ( 0 ) ) . addReg ( IndirectBaseReg ) . addReg ( OffsetReg ) . addImm ( 0 ) . addReg ( ValueReg ) ; } </s>

Build instruction ( s ) for an indirect register write .


"SIInstrInfo::storeRegToStackSlot - Do not know how to"

Store the specified register of the given register class to the specified stack frame index .


<s> bool use_return_insn ( void ) { if ( ! reload_completed || frame_pointer_needed || get_frame_size ( ) != 0 ) return false ; m68k_compute_frame_layout ( ) ; return current_frame . reg_no ? false : true ; } </s>

Return true if this function 's epilogue can be output as RTL .


<s> bool ARMTargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( VT . getVectorNumElements ( ) == 4 && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ 4 ] ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { if ( M [ i ] < 0 ) PFIndexes [ i ] = 8 ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ 0 ] * 9 * 9 * 9 + PFIndexes [ 1 ] * 9 * 9 + PFIndexes [ 2 ] * 9 + PFIndexes [ 3 ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> 30 ) ; if ( Cost <= 4 ) return true ; } bool ReverseVEXT ; unsigned Imm , WhichResult ; return ( ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isVREVMask ( M , VT , 64 ) || isVREVMask ( M , VT , 32 ) || isVREVMask ( M , VT , 16 ) || isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTRNMask ( M , VT , WhichResult ) || isVUZPMask ( M , VT , WhichResult ) || isVZIPMask ( M , VT , WhichResult ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> bool R600TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Align , bool * IsFast ) const { if ( IsFast ) * IsFast = false ; if ( ! VT . isSimple ( ) || VT == MVT :: Other ) return false ; if ( VT . bitsLT ( MVT :: i32 ) ) return false ; if ( IsFast ) * IsFast = true ; return VT . bitsGT ( MVT :: i32 ) && Align % 4 == 0 ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> MachineInstrBuilder MipsInstrInfo :: genInstrWithNewOpc ( unsigned NewOpc , MachineBasicBlock :: iterator I ) const { MachineInstrBuilder MIB ; int ZeroOperandPosition = - 1 ; bool BranchWithZeroOperand = false ; if ( I -> isBranch ( ) && ! I -> isPseudo ( ) ) { auto TRI = I -> getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; ZeroOperandPosition = I -> findRegisterUseOperandIdx ( Mips :: ZERO , false , TRI ) ; BranchWithZeroOperand = ZeroOperandPosition != - 1 ; } if ( BranchWithZeroOperand ) { switch ( NewOpc ) { case Mips :: BEQC : NewOpc = Mips :: BEQZC ; break ; case Mips :: BNEC : NewOpc = Mips :: BNEZC ; break ; case Mips :: BGEC : NewOpc = Mips :: BGEZC ; break ; case Mips :: BLTC : NewOpc = Mips :: BLTZC ; break ; case Mips :: BEQC64 : NewOpc = Mips :: BEQZC64 ; break ; case Mips :: BNEC64 : NewOpc = Mips :: BNEZC64 ; break ; } } MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , get ( NewOpc ) ) ; if ( NewOpc == Mips :: JIC || NewOpc == Mips :: JIALC || NewOpc == Mips :: JIC64 || NewOpc == Mips :: JIALC64 ) { if ( NewOpc == Mips :: JIALC || NewOpc == Mips :: JIALC64 ) MIB -> RemoveOperand ( 0 ) ; for ( unsigned J = 0 , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { MIB . add ( I -> getOperand ( J ) ) ; } MIB . addImm ( 0 ) ; } else { for ( unsigned J = 0 , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { if ( BranchWithZeroOperand && ( unsigned ) ZeroOperandPosition == J ) continue ; MIB . add ( I -> getOperand ( J ) ) ; } } MIB . copyImplicitOps ( * I ) ; MIB . cloneMemRefs ( * I ) ; return MIB ; } </s>

Create an instruction which has the same operands and memory operands as MI but has a new opcode .


<s> SMLoc getLoc ( ) const { return getParser ( ) . getTok ( ) . getLoc ( ) ; } </s>

Get the source location of the point where the field was defined .


<s> static bool sh_function_value_regno_p ( const unsigned int regno ) { return ( ( regno ) == FIRST_RET_REG || ( TARGET_SH2E && ( regno ) == FIRST_FP_RET_REG ) || ( TARGET_SHMEDIA_FPU && ( regno ) == FIRST_FP_RET_REG ) ) ; } </s>

Return true if N is a possible register number of function value .


<s> void NVPTXFrameLowering :: emitPrologue ( MachineFunction & MF ) const { if ( MF . getFrameInfo ( ) -> hasStackObjects ( ) ) { MachineBasicBlock & MBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = DebugLoc ( ) ; if ( tm . getSubtargetImpl ( ) -> hasGenericLdSt ( ) ) { if ( is64bit ) { MachineInstr * MI = BuildMI ( MBB , MBBI , dl , tm . getInstrInfo ( ) -> get ( NVPTX :: cvta_local_yes_64 ) , NVPTX :: VRFrame ) . addReg ( NVPTX :: VRFrameLocal ) ; BuildMI ( MBB , MI , dl , tm . getInstrInfo ( ) -> get ( NVPTX :: IMOV64rr ) , NVPTX :: VRFrameLocal ) . addReg ( NVPTX :: VRDepot ) ; } else { MachineInstr * MI = BuildMI ( MBB , MBBI , dl , tm . getInstrInfo ( ) -> get ( NVPTX :: cvta_local_yes ) , NVPTX :: VRFrame ) . addReg ( NVPTX :: VRFrameLocal ) ; BuildMI ( MBB , MI , dl , tm . getInstrInfo ( ) -> get ( NVPTX :: IMOV32rr ) , NVPTX :: VRFrameLocal ) . addReg ( NVPTX :: VRDepot ) ; } } else { if ( is64bit ) BuildMI ( MBB , MBBI , dl , tm . getInstrInfo ( ) -> get ( NVPTX :: IMOV64rr ) , NVPTX :: VRFrame ) . addReg ( NVPTX :: VRDepot ) ; else BuildMI ( MBB , MBBI , dl , tm . getInstrInfo ( ) -> get ( NVPTX :: IMOV32rr ) , NVPTX :: VRFrame ) . addReg ( NVPTX :: VRDepot ) ; } } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

NVPTX NVPTX NVPTX::cvta_local_yes_64 NVPTX::VRFrame NVPTX::VRFrameLocal NVPTX::IMOV64rr NVPTX::VRFrameLocal NVPTX::VRDepot NVPTX::cvta_local_yes NVPTX::VRFrame NVPTX::VRFrameLocal NVPTX::IMOV32rr NVPTX::VRFrameLocal NVPTX::VRDepot NVPTX::IMOV64rr NVPTX::VRFrame NVPTX::VRDepot NVPTX::IMOV32rr NVPTX::VRFrame NVPTX::VRDepot


<s> static void ix86_conditional_register_usage ( void ) { int i , c_mask ; if ( ! TARGET_64BIT ) { for ( i = FIRST_REX_INT_REG ; i <= LAST_REX_INT_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; for ( i = FIRST_REX_SSE_REG ; i <= LAST_REX_SSE_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; } c_mask = CALL_USED_REGISTERS_MASK ( TARGET_64BIT_MS_ABI ) ; CLEAR_HARD_REG_SET ( reg_class_contents [ ( int ) CLOBBERED_REGS ] ) ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { if ( call_used_regs [ i ] > 1 ) call_used_regs [ i ] = ! ! ( call_used_regs [ i ] & c_mask ) ; if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) GENERAL_REGS ] , i ) && call_used_regs [ i ] ) SET_HARD_REG_BIT ( reg_class_contents [ ( int ) CLOBBERED_REGS ] , i ) ; } if ( ! TARGET_MMX ) for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) MMX_REGS ] , i ) ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; if ( ! TARGET_SSE ) for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) SSE_REGS ] , i ) ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; if ( ! ( TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ) ) for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) FLOAT_REGS ] , i ) ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; if ( ! TARGET_AVX512F ) { for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; for ( i = FIRST_MASK_REG ; i <= LAST_MASK_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; } if ( ! TARGET_MPX ) for ( i = FIRST_BND_REG ; i <= LAST_BND_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; } </s>

Update register usage after having seen the compiler flags .


<s>
void
print
(
raw_ostream
&
O
)
const
override
{
switch
(
Kind
)
{
case
k_Tok
:
O
<<
"Token "
<<
Tok
;
break
;
case
k_Reg
:
O
<<
"Register "
<<
Reg
;
break
;
case
k_Imm
:
O
<<
"Immediate "
<<
*
Imm
;
break
;
case
k_Mem
:
O
<<
"Memory "
;
O
<<
*
Mem
.
Offset
<<
"("
<<
Reg
<<
")"
;
break
;
case
k_IndReg
:
O
<<
"RegInd "
<<
Reg
;
break
;
case
k_PostIndReg
:
O
<<
"PostInc "
<<
Reg
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

MSP430
"Token "
"Register "
"Immediate "
"Memory "
"("
")"
"RegInd "
"PostInc "


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void pru_expand_prologue ( void ) { int regno_start ; int total_frame_size ; int sp_offset ; int save_regs_base ; int save_offset ; total_frame_size = cfun -> machine -> total_size ; if ( flag_stack_usage_info ) current_function_static_stack_size = total_frame_size ; if ( ! UBYTE_INT ( total_frame_size ) ) { pru_add_to_sp ( cfun -> machine -> save_regs_offset - total_frame_size , REG_NOTE_MAX ) ; save_regs_base = 0 ; sp_offset = - cfun -> machine -> save_regs_offset ; } else if ( total_frame_size ) { pru_add_to_sp ( - total_frame_size , REG_NOTE_MAX ) ; save_regs_base = cfun -> machine -> save_regs_offset ; sp_offset = 0 ; } else save_regs_base = sp_offset = 0 ; regno_start = 0 ; save_offset = save_regs_base ; do regno_start = xbbo_next_reg_cluster ( regno_start , & save_offset , true ) ; while ( regno_start >= 0 ) ; if ( frame_pointer_needed ) { int fp_offset = total_frame_size - crtl -> args . pretend_args_size + sp_offset ; pru_add3_frame_adjust ( hard_frame_pointer_rtx , stack_pointer_rtx , fp_offset , REG_NOTE_MAX ) ; } if ( sp_offset ) pru_add_to_sp ( sp_offset , REG_FRAME_RELATED_EXPR ) ; if ( crtl -> profile ) emit_insn ( gen_blockage ( ) ) ; } </s>


<s>
void
Thumb1InstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
assert
(
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
PseudoSourceValue
::
getFixedStack
(
FI
)
,
MachineMemOperand
::
MOLoad
,
0
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tRestore
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .

ARM
ARM::tGPRRegisterClass
ARM
"Unknown regclass!"
ARM::tGPRRegisterClass
ARM
0
ARM::tRestore
0


<s> bool riscv_split_symbol ( rtx temp , rtx addr , machine_mode mode , rtx * low_out ) { enum riscv_symbol_type symbol_type ; if ( ( GET_CODE ( addr ) == HIGH && mode == MAX_MACHINE_MODE ) || ! riscv_symbolic_constant_p ( addr , & symbol_type ) || riscv_symbol_insns ( symbol_type ) == 0 || ! riscv_split_symbol_type ( symbol_type ) ) return false ; if ( low_out ) switch ( symbol_type ) { case SYMBOL_ABSOLUTE : { rtx high = gen_rtx_HIGH ( Pmode , copy_rtx ( addr ) ) ; high = riscv_force_temporary ( temp , high ) ; * low_out = gen_rtx_LO_SUM ( Pmode , high , addr ) ; } break ; case SYMBOL_PCREL : { static unsigned seqno ; char buf [ 32 ] ; rtx label ; ssize_t bytes = snprintf ( buf , sizeof ( buf ) , ".LA%u" , seqno ) ; gcc_assert ( ( size_t ) bytes < sizeof ( buf ) ) ; label = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; SYMBOL_REF_FLAGS ( label ) |= SYMBOL_FLAG_LOCAL ; if ( temp == NULL ) temp = gen_reg_rtx ( Pmode ) ; if ( Pmode == DImode ) emit_insn ( gen_auipcdi ( temp , copy_rtx ( addr ) , GEN_INT ( seqno ) ) ) ; else emit_insn ( gen_auipcsi ( temp , copy_rtx ( addr ) , GEN_INT ( seqno ) ) ) ; * low_out = gen_rtx_LO_SUM ( Pmode , temp , label ) ; seqno ++ ; } break ; default : gcc_unreachable ( ) ; } return true ; } </s>

If MODE is MAX_MACHINE_MODE , ADDR appears as a move operand , otherwise it appears in a MEM of that mode . Return true if ADDR is a legitimate constant in that context and can be split into high and low parts . If so , and if LOW_OUT is nonnull , emit the high part and store the low part in * LOW_OUT . Leave * LOW_OUT unchanged otherwise . TEMP is as for riscv_force_temporary and is used to load the high part into a register . When MODE is MAX_MACHINE_MODE , the low part is guaranteed to be a legitimize SET_SRC for an .md pattern , otherwise the low part is guaranteed to be a legitimate address for mode MODE .


<s> const char * MipsTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case MipsISD :: JmpLink : return "MipsISD::JmpLink" ; case MipsISD :: Hi : return "MipsISD::Hi" ; case MipsISD :: Lo : return "MipsISD::Lo" ; case MipsISD :: GPRel : return "MipsISD::GPRel" ; case MipsISD :: ThreadPointer : return "MipsISD::ThreadPointer" ; case MipsISD :: Ret : return "MipsISD::Ret" ; case MipsISD :: FPBrcond : return "MipsISD::FPBrcond" ; case MipsISD :: FPCmp : return "MipsISD::FPCmp" ; case MipsISD :: CMovFP_T : return "MipsISD::CMovFP_T" ; case MipsISD :: CMovFP_F : return "MipsISD::CMovFP_F" ; case MipsISD :: FPRound : return "MipsISD::FPRound" ; case MipsISD :: MAdd : return "MipsISD::MAdd" ; case MipsISD :: MAddu : return "MipsISD::MAddu" ; case MipsISD :: MSub : return "MipsISD::MSub" ; case MipsISD :: MSubu : return "MipsISD::MSubu" ; case MipsISD :: DivRem : return "MipsISD::DivRem" ; case MipsISD :: DivRemU : return "MipsISD::DivRemU" ; case MipsISD :: BuildPairF64 : return "MipsISD::BuildPairF64" ; case MipsISD :: ExtractElementF64 : return "MipsISD::ExtractElementF64" ; case MipsISD :: Wrapper : return "MipsISD::Wrapper" ; case MipsISD :: DynAlloc : return "MipsISD::DynAlloc" ; case MipsISD :: Sync : return "MipsISD::Sync" ; case MipsISD :: Ext : return "MipsISD::Ext" ; case MipsISD :: Ins : return "MipsISD::Ins" ; case MipsISD :: LWL : return "MipsISD::LWL" ; case MipsISD :: LWR : return "MipsISD::LWR" ; case MipsISD :: SWL : return "MipsISD::SWL" ; case MipsISD :: SWR : return "MipsISD::SWR" ; case MipsISD :: LDL : return "MipsISD::LDL" ; case MipsISD :: LDR : return "MipsISD::LDR" ; case MipsISD :: SDL : return "MipsISD::SDL" ; case MipsISD :: SDR : return "MipsISD::SDR" ; case MipsISD :: EXTP : return "MipsISD::EXTP" ; case MipsISD :: EXTPDP : return "MipsISD::EXTPDP" ; case MipsISD :: EXTR_S_H : return "MipsISD::EXTR_S_H" ; case MipsISD :: EXTR_W : return "MipsISD::EXTR_W" ; case MipsISD :: EXTR_R_W : return "MipsISD::EXTR_R_W" ; case MipsISD :: EXTR_RS_W : return "MipsISD::EXTR_RS_W" ; case MipsISD :: SHILO : return "MipsISD::SHILO" ; case MipsISD :: MTHLIP : return "MipsISD::MTHLIP" ; case MipsISD :: MULT : return "MipsISD::MULT" ; case MipsISD :: MULTU : return "MipsISD::MULTU" ; case MipsISD :: MADD_DSP : return "MipsISD::MADD_DSPDSP" ; case MipsISD :: MADDU_DSP : return "MipsISD::MADDU_DSP" ; case MipsISD :: MSUB_DSP : return "MipsISD::MSUB_DSP" ; case MipsISD :: MSUBU_DSP : return "MipsISD::MSUBU_DSP" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific

Mips Mips MipsISD::JmpLink "MipsISD::JmpLink" MipsISD::Hi "MipsISD::Hi" MipsISD::Lo "MipsISD::Lo" MipsISD::GPRel "MipsISD::GPRel" MipsISD::ThreadPointer "MipsISD::ThreadPointer" MipsISD::Ret "MipsISD::Ret" MipsISD::FPBrcond "MipsISD::FPBrcond" MipsISD::FPCmp "MipsISD::FPCmp" MipsISD::CMovFP_T "MipsISD::CMovFP_T" MipsISD::CMovFP_F "MipsISD::CMovFP_F" MipsISD::FPRound "MipsISD::FPRound" MipsISD::MAdd "MipsISD::MAdd" MipsISD::MAddu "MipsISD::MAddu" MipsISD::MSub "MipsISD::MSub" MipsISD::MSubu "MipsISD::MSubu" MipsISD::DivRem "MipsISD::DivRem" MipsISD::DivRemU "MipsISD::DivRemU" MipsISD::BuildPairF64 "MipsISD::BuildPairF64" MipsISD::ExtractElementF64 "MipsISD::ExtractElementF64" MipsISD::Wrapper "MipsISD::Wrapper" MipsISD::DynAlloc "MipsISD::DynAlloc" MipsISD::Sync "MipsISD::Sync" MipsISD::Ext "MipsISD::Ext" MipsISD::Ins "MipsISD::Ins" MipsISD::LWL "MipsISD::LWL" MipsISD::LWR "MipsISD::LWR" MipsISD::SWL "MipsISD::SWL" MipsISD::SWR "MipsISD::SWR" MipsISD::LDL "MipsISD::LDL" MipsISD::LDR "MipsISD::LDR" MipsISD::SDL "MipsISD::SDL" MipsISD::SDR "MipsISD::SDR" MipsISD::EXTP "MipsISD::EXTP" MipsISD::EXTPDP "MipsISD::EXTPDP" MipsISD::EXTR_S_H "MipsISD::EXTR_S_H" MipsISD::EXTR_W "MipsISD::EXTR_W" MipsISD::EXTR_R_W "MipsISD::EXTR_R_W" MipsISD::EXTR_RS_W "MipsISD::EXTR_RS_W" MipsISD::SHILO "MipsISD::SHILO" MipsISD::MTHLIP "MipsISD::MTHLIP" MipsISD::MULT "MipsISD::MULT" MipsISD::MULTU "MipsISD::MULTU" MipsISD::MADD_DSP "MipsISD::MADD_DSPDSP" MipsISD::MADDU_DSP "MipsISD::MADDU_DSP" MipsISD::MSUB_DSP "MipsISD::MSUB_DSP" MipsISD::MSUBU_DSP "MipsISD::MSUBU_DSP"


<s> Optional < MCFixupKind > ELFPPCAsmBackend :: getFixupKind ( StringRef Name ) const { if ( TT . isPPC64 ( ) ) { if ( Name == "R_PPC64_NONE" ) return FK_NONE ; } else { if ( Name == "R_PPC_NONE" ) return FK_NONE ; } return MCAsmBackend :: getFixupKind ( Name ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> bool runOnModule ( Module & M ) override { FeatureBitset Features = coalesceFeatures ( M ) ; std :: string FeatureStr = getFeatureString ( Features ) ; for ( auto & F : M ) replaceFeatures ( F , FeatureStr ) ; bool Stripped = false ; if ( ! Features [ WebAssembly :: FeatureAtomics ] ) { Stripped |= stripAtomics ( M ) ; Stripped |= stripThreadLocals ( M ) ; } recordFeatures ( M , Features , Stripped ) ; return true ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"R600 Texture Intrinsics Replacer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool supportSwiftError ( ) const override { return true ; } </s>

Return true if the target supports swifterror attribute .


<s> bool FISCFrameLowering :: hasFP ( const MachineFunction & MF ) const { return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> Value * AArch64TargetLowering :: getIRStackGuard ( IRBuilder < > & IRB ) const { if ( Subtarget -> isTargetAndroid ( ) ) return UseTlsOffset ( IRB , 0x28 ) ; if ( Subtarget -> isTargetFuchsia ( ) ) return UseTlsOffset ( IRB , - 0x10 ) ; return TargetLowering :: getIRStackGuard ( IRB ) ; } </s>

If the target has a standard location for the stack protector cookie , returns the address of that location .


<s> static int access_check ( const char * name , int mode ) { if ( mode == X_OK ) { struct stat st ; if ( stat ( name , & st ) < 0 || S_ISDIR ( st . st_mode ) ) return - 1 ; } return access ( name , mode ) ; } </s>

Check whether NAME can be accessed in MODE . This is like access , except that it never considers directories to be executable .


<s>
void
ARCompactFrameLowering
::
emitPrologue
(
MachineFunction
&
MF
)
const
{
MachineBasicBlock
&
MBB
=
MF
.
front
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
ARCompactFunctionInfo
*
AFI
=
MF
.
getInfo
<
ARCompactFunctionInfo
>
(
)
;
const
ARCompactInstrInfo
&
TII
=
*
static_cast
<
const
ARCompactInstrInfo
*
>
(
MF
.
getTarget
(
)
.
getInstrInfo
(
)
)
;
DebugLoc
dl
=
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
EmitComment
(
MBB
,
MBBI
,
dl
,
TII
,
"PROLOGUE START"
)
;
unsigned
int
NumBytes
=
MFI
->
getStackSize
(
)
;
NumBytes
=
(
NumBytes
+
3
)
&
~
3
;
unsigned
VARegSaveSize
=
AFI
->
getVarArgsRegSaveSize
(
)
;
if
(
VARegSaveSize
)
{
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
ARC
::
SUBrsi
)
,
ARC
::
SP
)
.
addReg
(
ARC
::
SP
)
.
addImm
(
VARegSaveSize
)
;
}
if
(
MFI
->
adjustsStack
(
)
)
{
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
ARC
::
STrri_a
)
)
.
addReg
(
ARC
::
SP
)
.
addImm
(
UNITS_PER_WORD
)
.
addReg
(
ARC
::
BLINK
)
;
}
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
ARC
::
STrri_a
)
)
.
addReg
(
ARC
::
SP
)
.
addImm
(
UNITS_PER_WORD
)
.
addReg
(
ARC
::
FP
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
ARC
::
MOVrr
)
,
ARC
::
FP
)
.
addReg
(
ARC
::
SP
)
;
if
(
NumBytes
>
0
)
{
assert
(
(
NumBytes
&
0x3
)
==
0
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
ARC
::
SUBrsi
)
,
ARC
::
SP
)
.
addReg
(
ARC
::
SP
)
.
addImm
(
NumBytes
)
;
}
EmitComment
(
MBB
,
MBBI
,
dl
,
TII
,
"PROLOGUE END"
)
;
}
</s>

ARCompact
ARC
ARC
ARC
ARC
ARC
"PROLOGUE START"
3
3
ARC::SUBrsi
ARC::SP
ARC::SP
ARC::STrri_a
ARC::SP
ARC::BLINK
ARC::STrri_a
ARC::SP
ARC::FP
ARC::MOVrr
ARC::FP
ARC::SP
0
0x3
0
ARC::SUBrsi
ARC::SP
ARC::SP
"PROLOGUE END"


<s> bool ARMPreAllocLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { TD = Fn . getTarget ( ) . getDataLayout ( ) ; TII = Fn . getTarget ( ) . getInstrInfo ( ) ; TRI = Fn . getTarget ( ) . getRegisterInfo ( ) ; STI = & Fn . getTarget ( ) . getSubtarget < ARMSubtarget > ( ) ; MRI = & Fn . getRegInfo ( ) ; MF = & Fn ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) Modified |= RescheduleLoadStoreInstrs ( MFI ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> const TPCTargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


<s> const DataLayout * getDataLayout ( ) const override { return getSubtargetImpl ( ) -> getDataLayout ( ) ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


".extern .shared .u%d __nvptx_stacks[32];\n"

".extern .shared .u32 __nvptx_uni[32];\n"

Write out the function declarations we 've collected .


<s> NVPTXSubtarget :: NVPTXSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const NVPTXTargetMachine & TM ) : NVPTXGenSubtargetInfo ( TT , CPU , FS ) , PTXVersion ( 0 ) , SmVersion ( 20 ) , TM ( TM ) , InstrInfo ( ) , TLInfo ( TM , initializeSubtargetDependencies ( CPU , FS ) ) , FrameLowering ( ) { } </s>

This constructor initializes the data members to match that of the specified module .


<s> bool X86ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { STI = & MF . getSubtarget < X86Subtarget > ( ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; X86FL = STI -> getFrameLowering ( ) ; bool Modified = ExpandPseudosWhichAffectControlFlow ( MF ) ; for ( MachineBasicBlock & MBB : MF ) Modified |= ExpandMBB ( MBB ) ; return Modified ; } </s>


<s> unsigned WebAssemblyFastISel :: signExtend ( unsigned Reg , const Value * V , MVT :: SimpleValueType From , MVT :: SimpleValueType To ) { if ( To == MVT :: i64 ) { if ( From == MVT :: i64 ) return copyValue ( Reg ) ; Reg = signExtendToI32 ( Reg , V , From ) ; unsigned Result = createResultReg ( & WebAssembly :: I64RegClass ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( WebAssembly :: I64_EXTEND_S_I32 ) , Result ) . addReg ( Reg ) ; return Result ; } return signExtendToI32 ( Reg , V , From ) ; } </s>

Return a new range in the specified integer type , which must be strictly larger than the current type .


<s> bool VETargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> static enum aarch64_parse_opt_result aarch64_parse_arch ( const char * to_parse , const struct processor * * res , uint64_t * isa_flags , std :: string * invalid_extension ) { const char * ext ; const struct processor * arch ; size_t len ; ext = strchr ( to_parse , '+' ) ; if ( ext != NULL ) len = ext - to_parse ; else len = strlen ( to_parse ) ; if ( len == 0 ) return AARCH64_PARSE_MISSING_ARG ; for ( arch = all_architectures ; arch -> name != NULL ; arch ++ ) { if ( strlen ( arch -> name ) == len && strncmp ( arch -> name , to_parse , len ) == 0 ) { uint64_t isa_temp = arch -> flags ; if ( ext != NULL ) { enum aarch64_parse_opt_result ext_res = aarch64_parse_extension ( ext , & isa_temp , invalid_extension ) ; if ( ext_res != AARCH64_PARSE_OK ) return ext_res ; } * res = arch ; * isa_flags = isa_temp ; return AARCH64_PARSE_OK ; } } return AARCH64_PARSE_INVALID_ARG ; } </s>

Parse the TO_PARSE string and put the architecture struct that it selects into RES and the architectural features into ISA_FLAGS . Return an aarch64_parse_opt_result describing the parse result . If there is an error parsing , RES and ISA_FLAGS are left unchanged .


<s> void X86InstrInfo :: breakPartialRegDependency ( MachineBasicBlock :: iterator MI , unsigned OpNum , const TargetRegisterInfo * TRI ) const { unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; if ( MI -> killsRegister ( Reg , TRI ) ) return ; if ( X86 :: VR128RegClass . contains ( Reg ) ) { bool HasAVX = TM . getSubtarget < X86Subtarget > ( ) . hasAVX ( ) ; unsigned Opc = HasAVX ? X86 :: VXORPSrr : X86 :: XORPSrr ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , get ( Opc ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; } else if ( X86 :: VR256RegClass . contains ( Reg ) ) { unsigned XReg = TRI -> getSubReg ( Reg , X86 :: sub_xmm ) ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , get ( X86 :: VXORPSrr ) , XReg ) . addReg ( XReg , RegState :: Undef ) . addReg ( XReg , RegState :: Undef ) . addReg ( Reg , RegState :: ImplicitDefine ) ; } else return ; MI -> addRegisterKilled ( Reg , TRI , true ) ; } </s>

Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum .


<s> SmallPtrSetImpl < MachineBasicBlock * > & getBlocksSet ( ) { return BlockSet ; } </s>

Return a direct , immutable handle to the blocks set .


<s> static void compute_zdepwi_operands ( unsigned HOST_WIDE_INT imm , unsigned * op ) { int lsb , len ; for ( lsb = 0 ; lsb < 32 ; lsb ++ ) { if ( ( imm & 1 ) != 0 ) break ; imm >>= 1 ; } if ( ( imm & 0x10 ) == 0 ) len = ( lsb <= 28 ) ? 4 : 32 - lsb ; else { for ( len = 5 ; len < 32 - lsb ; len ++ ) { if ( ( imm & ( ( unsigned HOST_WIDE_INT ) 1 << len ) ) == 0 ) break ; } imm = ( imm & 0xf ) - 0x10 ; } op [ 0 ] = imm ; op [ 1 ] = 31 - lsb ; op [ 2 ] = len ; } </s>

Compute position ( in OP [ 1 ] ) and width ( in OP [ 2 ] ) useful for copying IMM to a register using the zdepi instructions . Store the immediate value to insert in OP [ 0 ] .


<s> bool X86AsmParser :: parsePrimaryExpr ( const MCExpr * & Res , SMLoc & EndLoc ) { MCAsmParser & Parser = getParser ( ) ; if ( getTok ( ) . is ( AsmToken :: Percent ) || ( isParsingIntelSyntax ( ) && getTok ( ) . is ( AsmToken :: Identifier ) && MatchRegisterName ( Parser . getTok ( ) . getString ( ) ) ) ) { SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; unsigned RegNo ; if ( ParseRegister ( RegNo , StartLoc , EndLoc ) ) return true ; Res = X86MCExpr :: create ( RegNo , Parser . getContext ( ) ) ; return false ; } return Parser . parsePrimaryExpr ( Res , EndLoc ) ; } </s>


<s>
int
AArch64AsmParser
::
tryParseRegister
(
)
{
MCAsmParser
&
Parser
=
getParser
(
)
;
const
AsmToken
&
Tok
=
Parser
.
getTok
(
)
;
assert
(
Tok
.
is
(
AsmToken
::
Identifier
)
&&
"Token is not an Identifier"
)
;
std
::
string
lowerCase
=
Tok
.
getString
(
)
.
lower
(
)
;
if
(
isSVEVectorOrPredicateRegister
(
lowerCase
)
)
return
1
;
unsigned
RegNum
=
matchRegisterNameAlias
(
lowerCase
,
false
)
;
if
(
RegNum
==
0
)
RegNum
=
StringSwitch
<
unsigned
>
(
lowerCase
)
.
Case
(
"fp"
,
AArch64
::
FP
)
.
Case
(
"lr"
,
AArch64
::
LR
)
.
Case
(
"x31"
,
AArch64
::
XZR
)
.
Case
(
"w31"
,
AArch64
::
WZR
)
.
Default
(
0
)
;
if
(
RegNum
==
0
)
return
1
;
Parser
.
Lex
(
)
;
return
RegNum
;
}
</s>

tryParseRegister - parse one register if possible


"Should use MaskedValueIsZero if you don't know whether Op"

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> StringRef getPassName ( ) const override { return RISCV_MERGE_BASE_OFFSET_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> virtual const TargetSubtargetInfo * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool ARMBaseInstrInfo :: isPredicable ( MachineInstr & MI ) const { if ( ! MI . isPredicable ( ) ) return false ; if ( MI . isBundle ( ) ) return false ; if ( ! isEligibleForITBlock ( & MI ) ) return false ; ARMFunctionInfo * AFI = MI . getParent ( ) -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; if ( AFI -> isThumb2Function ( ) ) { if ( getSubtarget ( ) . restrictIT ( ) ) return isV8EligibleForIT ( & MI ) ; } else { if ( ( MI . getDesc ( ) . TSFlags & ARMII :: DomainMask ) == ARMII :: DomainNEON ) return false ; } return true ; } </s>

Return true if the specified instruction can be predicated .

ARM ARM ARM ARM ARMII::DomainMask ARMII::DomainNEON


<s> void X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const X86Subtarget & STI = MF . getSubtarget < X86Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; const X86RegisterInfo & RegInfo = * STI . getRegisterInfo ( ) ; unsigned StackPtr = RegInfo . getStackRegister ( ) ; bool reserveCallFrame = hasReservedCallFrame ( MF ) ; int Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; const bool Uses64BitStackPtr = STI . isTarget64BitLP64 ( ) || STI . isTargetNaCl64 ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t InternalAmt = ( isDestroy || Amount ) ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { if ( Amount == 0 ) return ; unsigned StackAlign = getStackAlignment ( ) ; Amount = RoundUpToAlignment ( Amount , StackAlign ) ; MachineInstr * New = nullptr ; Amount -= InternalAmt ; if ( Amount ) { if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( Uses64BitStackPtr , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; unsigned Opc = getADDriOpcode ( Uses64BitStackPtr , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } return ; } if ( Opcode == TII . getCallFrameDestroyOpcode ( ) && InternalAmt ) { unsigned Opc = getSUBriOpcode ( Uses64BitStackPtr , InternalAmt ) ; MachineInstr * New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( InternalAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! std :: prev ( I ) -> isCall ( ) ) -- I ; MBB . insert ( I , New ) ; } } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> void NVPTXAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; if ( nvptxSubtarget . getDrvInterface ( ) == NVPTX :: CUDA ) emitLineNumberAsDotLoc ( * MI ) ; MCInst Inst ; lowerToMCInst ( MI , Inst ) ; OutStreamer . EmitInstruction ( Inst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> SDValue AArch64TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : case ISD :: SUB : return performAddSubLongCombine ( N , DCI , DAG ) ; case ISD :: XOR : return performXorCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: MUL : return performMulCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SINT_TO_FP : case ISD :: UINT_TO_FP : return performIntToFpCombine ( N , DAG ) ; case ISD :: OR : return performORCombine ( N , DCI , Subtarget ) ; case ISD :: INTRINSIC_WO_CHAIN : return performIntrinsicCombine ( N , DCI , Subtarget ) ; case ISD :: ANY_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: SIGN_EXTEND : return performExtendCombine ( N , DCI , DAG ) ; case ISD :: BITCAST : return performBitcastCombine ( N , DCI , DAG ) ; case ISD :: CONCAT_VECTORS : return performConcatVectorsCombine ( N , DCI , DAG ) ; case ISD :: SELECT : return performSelectCombine ( N , DAG ) ; case ISD :: VSELECT : return performVSelectCombine ( N , DCI . DAG ) ; case ISD :: STORE : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case AArch64ISD :: BRCOND : return performBRCONDCombine ( N , DCI , DAG ) ; case AArch64ISD :: DUP : return performPostLD1Combine ( N , DCI , false ) ; case ISD :: INSERT_VECTOR_ELT : return performPostLD1Combine ( N , DCI , true ) ; case ISD :: INTRINSIC_VOID : case ISD :: INTRINSIC_W_CHAIN : switch ( cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) -> getZExtValue ( ) ) { case Intrinsic :: aarch64_neon_ld2 : case Intrinsic :: aarch64_neon_ld3 : case Intrinsic :: aarch64_neon_ld4 : case Intrinsic :: aarch64_neon_ld1x2 : case Intrinsic :: aarch64_neon_ld1x3 : case Intrinsic :: aarch64_neon_ld1x4 : case Intrinsic :: aarch64_neon_ld2lane : case Intrinsic :: aarch64_neon_ld3lane : case Intrinsic :: aarch64_neon_ld4lane : case Intrinsic :: aarch64_neon_ld2r : case Intrinsic :: aarch64_neon_ld3r : case Intrinsic :: aarch64_neon_ld4r : case Intrinsic :: aarch64_neon_st2 : case Intrinsic :: aarch64_neon_st3 : case Intrinsic :: aarch64_neon_st4 : case Intrinsic :: aarch64_neon_st1x2 : case Intrinsic :: aarch64_neon_st1x3 : case Intrinsic :: aarch64_neon_st1x4 : case Intrinsic :: aarch64_neon_st2lane : case Intrinsic :: aarch64_neon_st3lane : case Intrinsic :: aarch64_neon_st4lane : return performNEONPostLDSTCombine ( N , DCI , DAG ) ; default : break ; } } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> unsigned SIInstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { unsigned Count = 0 ; unsigned RemovedSize = 0 ; for ( MachineInstr & MI : llvm :: make_early_inc_range ( MBB . terminators ( ) ) ) { if ( MI . isBranch ( ) || MI . isReturn ( ) ) { RemovedSize += getInstSizeInBytes ( MI ) ; MI . eraseFromParent ( ) ; ++ Count ; } } if ( BytesRemoved ) * BytesRemoved = RemovedSize ; return Count ; } </s>

Remove the branching code at the end of the specific MBB .


<s>
void
TPCSchedStrategy
::
schedNode
(
SUnit
*
SU
,
bool
IsTopNode
)
{
MachineInstr
*
MI
=
SU
->
getInstr
(
)
;
(
void
)
MI
;
lastScheduledSU
=
SU
;
if
(
IsTopNode
)
{
Top
.
bumpNode
(
SU
,
isPostRA
)
;
SU
->
TopReadyCycle
=
Top
.
CurrCycle
;
LLVM_DEBUG
(
dbgs
(
)
<<
"   ** TopReadyCycle = "
<<
SU
->
TopReadyCycle
<<
"\n"
)
;
}
else
{
Bot
.
bumpNode
(
SU
,
isPostRA
)
;
SU
->
BotReadyCycle
=
Bot
.
CurrCycle
;
LLVM_DEBUG
(
dbgs
(
)
<<
"   ** BotReadyCycle = "
<<
SU
->
BotReadyCycle
<<
"\n"
)
;
}
}
</s>

ScheduleDAGMI has scheduled an instruction - tell HazardRec about it .

TPC
TPC
"   ** TopReadyCycle = "
"\n"
"   ** BotReadyCycle = "
"\n"


<s> void rs6000_emit_epilogue_components ( sbitmap components ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; rtx ptr_reg = gen_rtx_REG ( Pmode , frame_pointer_needed_indeed ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ) ; machine_mode reg_mode = Pmode ; int reg_size = TARGET_32BIT ? 4 : 8 ; machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode ; int fp_reg_size = 8 ; int offset = info -> fp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_fp_reg_save ; i < 64 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( fp_reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } offset += fp_reg_size ; } offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_gp_reg_save ; i < 32 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } offset += reg_size ; } if ( bitmap_bit_p ( components , 0 ) ) { int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; rtx reg = gen_rtx_REG ( reg_mode , 0 ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; rtx lr = gen_rtx_REG ( Pmode , LR_REGNO ) ; insn = emit_move_insn ( lr , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_RESTORE , lr ) ; } } </s>


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


Compute the size of the local area and the size to be adjusted by the * prologue and epilogue .


"$gp should only be used for TLS in cap-table mode"

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static void avr_asm_init_sections ( void ) { if ( avr_arch -> flash_pm_offset == 0 ) readonly_data_section -> unnamed . callback = avr_output_data_section_asm_op ; data_section -> unnamed . callback = avr_output_data_section_asm_op ; bss_section -> unnamed . callback = avr_output_bss_section_asm_op ; } </s>

Implement ` TARGET_ASM_INIT_SECTIONS ' .


<s> class LLVM_LIBRARY_VISIBILITY SystemZMCInstLower { MCContext & Ctx ; SystemZAsmPrinter & AsmPrinter ; public : SystemZMCInstLower ( MCContext & ctx , SystemZAsmPrinter & asmPrinter ) ; void lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCOperand lowerOperand ( const MachineOperand & MO ) const ; const MCExpr * getExpr ( const MachineOperand & MO , MCSymbolRefExpr :: VariantKind Kind ) const ; } </s>

Implementation of the SCEVPredicate interface .


<s> rtx legitimize_pic_address ( rtx orig , machine_mode mode ATTRIBUTE_UNUSED , rtx reg ) { if ( tls_symbolic_operand ( orig , Pmode ) != TLS_MODEL_NONE ) return orig ; if ( GET_CODE ( orig ) == LABEL_REF || ( GET_CODE ( orig ) == SYMBOL_REF && SYMBOL_REF_LOCAL_P ( orig ) ) ) { if ( reg == NULL_RTX ) reg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_symGOTOFF2reg ( reg , orig ) ) ; return reg ; } else if ( GET_CODE ( orig ) == SYMBOL_REF ) { if ( reg == NULL_RTX ) reg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_symGOT2reg ( reg , orig ) ) ; return reg ; } return orig ; } </s>

Legitimize PIC addresses . If the address is already position-independent , we return ORIG . Newly generated position-independent addresses go into a reg . This is REG if nonzero , otherwise we allocate register ( s ) as necessary .


<s> static void nios2_alternate_compare_const ( enum rtx_code code , rtx op , enum rtx_code * alt_code , rtx * alt_op , machine_mode mode ) { HOST_WIDE_INT opval = INTVAL ( op ) ; enum rtx_code scode = signed_condition ( code ) ; bool dec_p = ( scode == LT || scode == GE ) ; if ( code == EQ || code == NE ) { * alt_code = code ; * alt_op = op ; return ; } * alt_op = ( dec_p ? gen_int_mode ( opval - 1 , mode ) : gen_int_mode ( opval + 1 , mode ) ) ; * alt_code = reverse_condition ( swap_condition ( code ) ) ; { unsigned HOST_WIDE_INT alt_opval = INTVAL ( * alt_op ) ; if ( code == scode ) alt_opval ^= ( 1 << ( GET_MODE_BITSIZE ( mode ) - 1 ) ) ; alt_opval &= GET_MODE_MASK ( mode ) ; gcc_assert ( dec_p ? alt_opval != GET_MODE_MASK ( mode ) : alt_opval != 0 ) ; } } </s>

Return in * ALT_CODE and * ALT_OP , an alternate equivalent constant comparison , e.g . > = 1 into > 0 .


<s> void PPCTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , APInt & KnownZero , APInt & KnownOne , const SelectionDAG & DAG , unsigned Depth ) const { KnownZero = KnownOne = APInt ( KnownZero . getBitWidth ( ) , 0 ) ; switch ( Op . getOpcode ( ) ) { default : break ; case PPCISD :: LBRX : { if ( cast < VTSDNode > ( Op . getOperand ( 2 ) ) -> getVT ( ) == MVT :: i16 ) KnownZero = 0xFFFF0000 ; break ; } case ISD :: INTRINSIC_WO_CHAIN : { switch ( cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ) { default : break ; case Intrinsic :: ppc_altivec_vcmpbfp_p : case Intrinsic :: ppc_altivec_vcmpeqfp_p : case Intrinsic :: ppc_altivec_vcmpequb_p : case Intrinsic :: ppc_altivec_vcmpequh_p : case Intrinsic :: ppc_altivec_vcmpequw_p : case Intrinsic :: ppc_altivec_vcmpgefp_p : case Intrinsic :: ppc_altivec_vcmpgtfp_p : case Intrinsic :: ppc_altivec_vcmpgtsb_p : case Intrinsic :: ppc_altivec_vcmpgtsh_p : case Intrinsic :: ppc_altivec_vcmpgtsw_p : case Intrinsic :: ppc_altivec_vcmpgtub_p : case Intrinsic :: ppc_altivec_vcmpgtuh_p : case Intrinsic :: ppc_altivec_vcmpgtuw_p : KnownZero = ~ 1U ; break ; } } } } </s>


"64-bit code requested on a subtarget that doesn't support it!"

This constructor initializes the data members to match that of the specified triple .


<s> bool X86TargetLowering :: isNarrowingProfitable ( MVT VT1 , MVT VT2 ) const { return ! ( VT1 == MVT :: i32 && VT2 == MVT :: i16 ) ; } </s>

Return true if it 's profitable to narrow operations of type SrcVT to DestVT .


<s> MCSymbol * ARM64MCInstLower :: GetExternalSymbolSymbol ( const MachineOperand & MO ) const { return Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; } </s>

Return the MCSymbol for the specified ExternalSymbol .


"Unexpected fixup kind in fixupNeedsRelaxation()!"

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> static int const_ok_for_op ( HOST_WIDE_INT i , enum rtx_code code ) { if ( const_ok_for_arm ( i ) ) return 1 ; switch ( code ) { case PLUS : return const_ok_for_arm ( ARM_SIGN_EXTEND ( - i ) ) ; case MINUS : case XOR : case IOR : return 0 ; case AND : return const_ok_for_arm ( ARM_SIGN_EXTEND ( ~ i ) ) ; default : gcc_unreachable ( ) ; } } </s>

Return true if I is a valid constant for the operation CODE .


<s> void SHUXIFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


"MEMOPw offset is not aligned correctly."

"MEMOPh offset is not aligned correctly."

"No offset range is defined for this opcode. "

"Please define it in the above switch statement!"


<s> static void arm_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain_value ) { rtx fnaddr , mem , a_tramp ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp , SImode , TARGET_32BIT ? 8 : 12 ) ; emit_move_insn ( mem , chain_value ) ; mem = adjust_address ( m_tramp , SImode , TARGET_32BIT ? 12 : 16 ) ; fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; emit_move_insn ( mem , fnaddr ) ; a_tramp = XEXP ( m_tramp , 0 ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , "__clear_cache" ) , LCT_NORMAL , VOIDmode , a_tramp , Pmode , plus_constant ( Pmode , a_tramp , TRAMPOLINE_SIZE ) , Pmode ) ; } </s>

Emit RTL insns to initialize the variable parts of a trampoline .


<s> static int v850_arg_partial_bytes ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , bool named ) { int size , align ; if ( TARGET_GHS && ! named ) return 0 ; if ( mode == BLKmode ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; if ( type ) align = TYPE_ALIGN ( type ) / BITS_PER_UNIT ; else align = size ; cum -> nbytes = ( cum -> nbytes + align - 1 ) & ~ ( align - 1 ) ; if ( cum -> nbytes > 4 * UNITS_PER_WORD ) return 0 ; if ( cum -> nbytes + size <= 4 * UNITS_PER_WORD ) return 0 ; if ( type == NULL_TREE && cum -> nbytes + size > 4 * UNITS_PER_WORD ) return 0 ; return 4 * UNITS_PER_WORD - cum -> nbytes ; } </s>

Return the number of bytes which must be put into registers for values which are part in registers and part in memory .


<s> bool X86InstrInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; bool is64Bit = TM . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ; unsigned Opc = is64Bit ? X86 :: POP64r : X86 :: POP32r ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; BuildMI ( MBB , MI , DL , get ( Opc ) , Reg ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> void X86TargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( Subtarget . getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) || Subtarget . getTargetTriple ( ) . isWindowsItaniumEnvironment ( ) ) { M . getOrInsertGlobal ( "__security_cookie" , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; FunctionCallee SecurityCheckCookie = M . getOrInsertFunction ( "__security_check_cookie" , Type :: getVoidTy ( M . getContext ( ) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; if ( Function * F = dyn_cast < Function > ( SecurityCheckCookie . getCallee ( ) ) ) { F -> setCallingConv ( CallingConv :: X86_FastCall ) ; F -> addAttribute ( 1 , Attribute :: AttrKind :: InReg ) ; } return ; } auto GuardMode = getTargetMachine ( ) . Options . StackProtectorGuard ; if ( ( GuardMode == llvm :: StackProtectorGuards :: TLS || GuardMode == llvm :: StackProtectorGuards :: None ) && hasStackGuardSlotTLS ( Subtarget . getTargetTriple ( ) ) ) return ; TargetLowering :: insertSSPDeclarations ( M ) ; } </s>

Inserts necessary declarations for SSP ( stack protection ) purpose .


<s> const char * TOYTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case TOYISD :: CALL : return "TOYISD::CALL" ; case TOYISD :: BR_CC : return "TOYISD::BR_CC" ; case TOYISD :: CMPEQ : return "TOYISD::CMPEQ" ; case TOYISD :: CMPNE : return "TOYISD::CMPNE" ; case TOYISD :: CMPLT : return "TOYISD::CMPLT" ; case TOYISD :: CMPLE : return "TOYISD::CMPLE" ; case TOYISD :: CMPGT : return "TOYISD::CMPGT" ; case TOYISD :: CMPGE : return "TOYISD::CMPGE" ; case TOYISD :: RET_FLAG : return "TOYIDS::RET_FLAG" ; } } </s>

getTargetNodeName - This method returns the name of a target specific

TOY TOY 0 TOYISD::CALL "TOYISD::CALL" TOYISD::BR_CC "TOYISD::BR_CC" TOYISD::CMPEQ "TOYISD::CMPEQ" TOYISD::CMPNE "TOYISD::CMPNE" TOYISD::CMPLT "TOYISD::CMPLT" TOYISD::CMPLE "TOYISD::CMPLE" TOYISD::CMPGT "TOYISD::CMPGT" TOYISD::CMPGE "TOYISD::CMPGE" TOYISD::RET_FLAG "TOYIDS::RET_FLAG"


<s> virtual const X86Subtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool tilepro_expand_addsi ( rtx op0 , rtx op1 , rtx op2 ) { rtx temp ; HOST_WIDE_INT n ; HOST_WIDE_INT high ; if ( add_operand ( op2 , SImode ) ) return false ; if ( ! CONST_INT_P ( op2 ) ) return false ; temp = create_temp_reg_if_possible ( SImode , op0 ) ; n = INTVAL ( op2 ) ; high = ( n + ( n & 0x8000 ) ) & ~ 0xffff ; emit_move_insn ( temp , gen_rtx_PLUS ( SImode , op1 , gen_int_si ( high ) ) ) ; emit_move_insn ( op0 , gen_rtx_PLUS ( SImode , temp , gen_int_si ( n - high ) ) ) ; return true ; } </s>


<s> unsigned HexagonTTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args ) { return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo , Args ) ; } </s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> static void add_constant ( int dest , int src , int value , int mark_frame ) { rtx_insn * insn ; int hi , lo ; if ( src == dest && value == 0 ) return ; if ( value == 0 ) { insn = emit_move_insn ( gen_rtx_REG ( SImode , dest ) , gen_rtx_REG ( SImode , src ) ) ; if ( mark_frame ) RTX_FRAME_RELATED_P ( insn ) = 1 ; return ; } if ( value >= - 32768 && value <= 32767 ) { insn = emit_insn ( gen_addsi3 ( gen_rtx_REG ( SImode , dest ) , gen_rtx_REG ( SImode , src ) , GEN_INT ( value ) ) ) ; if ( mark_frame ) RTX_FRAME_RELATED_P ( insn ) = 1 ; return ; } hi = trunc_int_for_mode ( value & 0xffff0000 , SImode ) ; lo = value & 0xffff ; insn = emit_move_insn ( gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP ) , GEN_INT ( hi ) ) ; if ( lo ) { insn = emit_insn ( gen_iorsi3 ( gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP ) , gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP ) , GEN_INT ( lo ) ) ) ; } insn = emit_insn ( gen_addsi3 ( gen_rtx_REG ( SImode , dest ) , gen_rtx_REG ( SImode , src ) , gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP ) ) ) ; if ( mark_frame ) { RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( SImode , gen_rtx_REG ( SImode , dest ) , gen_rtx_PLUS ( SImode , gen_rtx_REG ( SImode , dest ) , GEN_INT ( value ) ) ) ) ; } } </s>

Add a constant to the pool and return its label .


<s>
bool
BlackfinAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
SetupMachineFunction
(
MF
)
;
EmitConstantPool
(
MF
.
getConstantPool
(
)
)
;
EmitJumpTableInfo
(
MF
.
getJumpTableInfo
(
)
,
MF
)
;
const
Function
*
F
=
MF
.
getFunction
(
)
;
OutStreamer
.
SwitchSection
(
getObjFileLowering
(
)
.
SectionForGlobal
(
F
,
Mang
,
TM
)
)
;
EmitAlignment
(
2
,
F
)
;
emitLinkage
(
CurrentFnName
,
F
->
getLinkage
(
)
)
;
printVisibility
(
CurrentFnName
,
F
->
getVisibility
(
)
)
;
O
<<
"\t.type\t"
<<
CurrentFnName
<<
", STT_FUNC\n"
<<
CurrentFnName
<<
":\n"
;
if
(
DW
)
DW
->
BeginFunction
(
&
MF
)
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
!
VerboseAsm
&&
(
I
->
pred_empty
(
)
||
I
->
isOnlyReachableByFallthrough
(
)
)
)
{
}
else
{
printBasicBlockLabel
(
I
,
true
,
true
,
VerboseAsm
)
;
O
<<
'\n'
;
}
for
(
MachineBasicBlock
::
const_iterator
II
=
I
->
begin
(
)
,
E
=
I
->
end
(
)
;
II
!=
E
;
++
II
)
{
printInstruction
(
II
)
;
++
EmittedInsts
;
}
}
O
<<
"\t.size "
<<
CurrentFnName
<<
", .-"
<<
CurrentFnName
<<
"\n"
;
if
(
DW
)
DW
->
EndFunction
(
&
MF
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .

Blackfin
2
"\t.type\t"
", STT_FUNC\n"
":\n"
"\t.size "
", .-"
"\n"


<s> bool X86IndirectThunks :: doInitialization ( Module & M ) { initTIs ( M , TIs ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> bool AMDGPUAnnotateUniformValues :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; DA = & getAnalysis < DivergenceAnalysis > ( ) ; MDR = & getAnalysis < MemoryDependenceWrapperPass > ( ) . getMemDep ( ) ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; isKernelFunc = F . getCallingConv ( ) == CallingConv :: AMDGPU_KERNEL ; visit ( F ) ; noClobberClones . clear ( ) ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static bool bpf_core_is_maybe_aggregate_access ( tree expr ) { switch ( TREE_CODE ( expr ) ) { case COMPONENT_REF : case BIT_FIELD_REF : case ARRAY_REF : case ARRAY_RANGE_REF : return true ; case ADDR_EXPR : case NOP_EXPR : return bpf_core_is_maybe_aggregate_access ( TREE_OPERAND ( expr , 0 ) ) ; default : return false ; } } </s>

Return whether EXPR could access some aggregate data structure that BPF CO-RE support needs to know about .


<s> OperandMatchResultTy BPFAsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { const AsmToken & Tok = getParser ( ) . getTok ( ) ; StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; RegNo = 0 ; StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( ! MatchRegisterName ( Name ) ) { getParser ( ) . Lex ( ) ; return MatchOperand_Success ; } return MatchOperand_NoMatch ; } </s>

tryParseRegister - parse one register if possible


<s> uint64_t PPCFrameLowering :: determineFrameLayout ( const MachineFunction & MF , bool UseEstimate , unsigned * NewMaxCallFrameSize ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const PPCFunctionInfo * FI = MF . getInfo < PPCFunctionInfo > ( ) ; uint64_t FrameSize = UseEstimate ? MFI . estimateStackSize ( MF ) : MFI . getStackSize ( ) ; Align TargetAlign = getStackAlign ( ) ; Align MaxAlign = MFI . getMaxAlign ( ) ; Align Alignment = std :: max ( TargetAlign , MaxAlign ) ; const PPCRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; bool DisableRedZone = MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoRedZone ) ; bool CanUseRedZone = ! MFI . hasVarSizedObjects ( ) && ! MFI . adjustsStack ( ) && ! MustSaveLR ( MF , LR ) && ! FI -> mustSaveTOC ( ) && ! RegInfo -> hasBasePointer ( MF ) ; bool FitsInRedZone = FrameSize <= Subtarget . getRedZoneSize ( ) ; if ( ! DisableRedZone && CanUseRedZone && FitsInRedZone ) { return 0 ; } unsigned maxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI . hasVarSizedObjects ( ) ) maxCallFrameSize = alignTo ( maxCallFrameSize , Alignment ) ; if ( NewMaxCallFrameSize ) * NewMaxCallFrameSize = maxCallFrameSize ; FrameSize += maxCallFrameSize ; FrameSize = alignTo ( FrameSize , Alignment ) ; return FrameSize ; } </s>

Determine the frame layout but do not update the machine function .


<s> static void ix86_add_new_builtins ( HOST_WIDE_INT isa ) { if ( ( isa & deferred_isa_values ) == 0 ) return ; deferred_isa_values &= ~ isa ; int i ; tree saved_current_target_pragma = current_target_pragma ; current_target_pragma = NULL_TREE ; for ( i = 0 ; i < ( int ) IX86_BUILTIN_MAX ; i ++ ) { if ( ( ix86_builtins_isa [ i ] . isa & isa ) != 0 && ix86_builtins_isa [ i ] . set_and_not_built_p ) { tree decl , type ; ix86_builtins_isa [ i ] . set_and_not_built_p = false ; type = ix86_get_builtin_func_type ( ix86_builtins_isa [ i ] . tcode ) ; decl = add_builtin_function_ext_scope ( ix86_builtins_isa [ i ] . name , type , i , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ i ] = decl ; if ( ix86_builtins_isa [ i ] . const_p ) TREE_READONLY ( decl ) = 1 ; if ( ix86_builtins_isa [ i ] . leaf_p ) DECL_ATTRIBUTES ( decl ) = build_tree_list ( get_identifier ( "leaf" ) , NULL_TREE ) ; if ( ix86_builtins_isa [ i ] . nothrow_p ) TREE_NOTHROW ( decl ) = 1 ; } } current_target_pragma = saved_current_target_pragma ; } </s>

Add any new builtin functions for a given ISA that may not have been declared . This saves a bit of space compared to adding all of the declarations to the tree , even if we did n't use them .


"address operand requires constraint for"

Return a pointer register name as a string


<s> void Z80InstPrinterBase :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static bool sparc_handle_option ( size_t code , const char * arg , int value ATTRIBUTE_UNUSED ) { switch ( code ) { case OPT_mfpu : case OPT_mhard_float : case OPT_msoft_float : fpu_option_set = true ; break ; case OPT_mcpu_ : sparc_select [ 1 ] . string = arg ; break ; case OPT_mtune_ : sparc_select [ 2 ] . string = arg ; break ; } return true ; } </s>


<s>
static
void
unicosmk_output_dex
(
FILE
*
file
)
{
struct
unicosmk_dex
*
dex
;
int
i
;
if
(
unicosmk_dex_list
==
)
return
;
fprintf
(
file
,
"\t.dexstart\n"
)
;
i
=
unicosmk_dex_count
;
for
(
dex
=
unicosmk_dex_list
;
dex
;
dex
=
dex
->
next
)
{
fprintf
(
file
,
"\tDEX (%d) = "
,
i
)
;
assemble_name
(
file
,
dex
->
name
)
;
putc
(
'\n'
,
file
)
;
i
;
}
fprintf
(
file
,
"\t.dexend\n"
)
;
}
</s>

Output the DEX definitions for this file .


<s> static void s390_chunkify_finish ( struct constant_pool * pool_list ) { struct constant_pool * curr_pool = NULL ; rtx_insn * insn ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( INSN_P ( insn ) ) replace_ltrel_base ( & PATTERN ( insn ) ) ; curr_pool = s390_find_pool ( pool_list , insn ) ; if ( ! curr_pool ) continue ; if ( NONJUMP_INSN_P ( insn ) || CALL_P ( insn ) ) { rtx addr , pool_ref = NULL_RTX ; find_constant_pool_ref ( PATTERN ( insn ) , & pool_ref ) ; if ( pool_ref ) { if ( s390_execute_label ( insn ) ) addr = s390_find_execute ( curr_pool , insn ) ; else addr = s390_find_constant ( curr_pool , get_pool_constant ( pool_ref ) , get_pool_mode ( pool_ref ) ) ; replace_constant_pool_ref ( & PATTERN ( insn ) , pool_ref , addr ) ; INSN_CODE ( insn ) = - 1 ; } } } for ( curr_pool = pool_list ; curr_pool ; curr_pool = curr_pool -> next ) s390_dump_pool ( curr_pool , 0 ) ; while ( pool_list ) { struct constant_pool * next = pool_list -> next ; s390_free_pool ( pool_list ) ; pool_list = next ; } } </s>

POOL_LIST is a chunk list as prepared by s390_chunkify_start . After we have decided to use this list , finish implementing all changes to the current function as required .


"Pseudo opcode found in EmitInstruction()"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> SDNode * MSP430TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallSDNode * TheCall , unsigned CallingConv , SelectionDAG & DAG ) { bool isVarArg = TheCall -> isVarArg ( ) ; DebugLoc dl = TheCall -> getDebugLoc ( ) ; SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallingConv , isVarArg , getTargetMachine ( ) , RVLocs ) ; CCInfo . AnalyzeCallResult ( TheCall , RetCC_MSP430 ) ; SmallVector < SDValue , 8 > ResultVals ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; ResultVals . push_back ( Chain . getValue ( 0 ) ) ; } ResultVals . push_back ( Chain ) ; return DAG . getNode ( ISD :: MERGE_VALUES , dl , TheCall -> getVTList ( ) , & ResultVals [ 0 ] , ResultVals . size ( ) ) . getNode ( ) ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> bool Cpu0InstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock & MBB = * MI -> getParent ( ) ; switch ( MI -> getDesc ( ) . getOpcode ( ) ) { default : return false ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> SDValue AMDGPUTargetLowering :: CreateLiveInRegister ( SelectionDAG & DAG , const TargetRegisterClass * RC , unsigned Reg , EVT VT , const SDLoc & SL , bool RawReg ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned VReg ; if ( ! MRI . isLiveIn ( Reg ) ) { VReg = MRI . createVirtualRegister ( RC ) ; MRI . addLiveIn ( Reg , VReg ) ; } else { VReg = MRI . getLiveInVirtReg ( Reg ) ; } if ( RawReg ) return DAG . getRegister ( VReg , VT ) ; return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , SL , VReg , VT ) ; } </s>

Helper function that adds Reg to the LiveIn list of the DAG 's MachineFunction .


<s> bool NyuziAsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s>
void
XCoreRegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected"
)
;
MachineInstr
&
MI
=
*
II
;
MachineOperand
&
FrameOp
=
MI
.
getOperand
(
FIOperandNum
)
;
int
FrameIndex
=
FrameOp
.
getIndex
(
)
;
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
const
XCoreInstrInfo
&
TII
=
*
static_cast
<
const
XCoreInstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
const
XCoreFrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
int
Offset
=
MF
.
getFrameInfo
(
)
->
getObjectOffset
(
FrameIndex
)
;
int
StackSize
=
MF
.
getFrameInfo
(
)
->
getStackSize
(
)
;
DEBUG
(
errs
(
)
<<
"\nFunction         : "
<<
MF
.
getName
(
)
<<
"\n"
)
;
DEBUG
(
errs
(
)
<<
"<--------->\n"
)
;
DEBUG
(
MI
.
print
(
errs
(
)
)
)
;
DEBUG
(
errs
(
)
<<
"FrameIndex         : "
<<
FrameIndex
<<
"\n"
)
;
DEBUG
(
errs
(
)
<<
"FrameOffset        : "
<<
Offset
<<
"\n"
)
;
DEBUG
(
errs
(
)
<<
"StackSize          : "
<<
StackSize
<<
"\n"
)
;
Offset
+=
StackSize
;
unsigned
FrameReg
=
getFrameRegister
(
MF
)
;
if
(
MI
.
isDebugValue
(
)
)
{
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
)
;
return
;
}
Offset
+=
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
0
)
;
assert
(
Offset
%
4
==
0
&&
"Misaligned stack offset"
)
;
DEBUG
(
errs
(
)
<<
"Offset             : "
<<
Offset
<<
"\n"
<<
"<--------->\n"
)
;
Offset
/=
4
;
unsigned
Reg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
assert
(
XCore
::
GRRegsRegClass
.
contains
(
Reg
)
&&
"Unexpected register operand"
)
;
if
(
TFI
->
hasFP
(
MF
)
)
{
if
(
isImmUs
(
Offset
)
)
InsertFPImmInst
(
II
,
TII
,
Reg
,
FrameReg
,
Offset
)
;
else
InsertFPConstInst
(
II
,
TII
,
Reg
,
FrameReg
,
Offset
,
RS
)
;
}
else
{
if
(
isImmU16
(
Offset
)
)
InsertSPImmInst
(
II
,
TII
,
Reg
,
Offset
)
;
else
InsertSPConstInst
(
II
,
TII
,
Reg
,
Offset
,
RS
)
;
}
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
MBB
.
erase
(
II
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .

XCore
XCore
0
"Unexpected"
XCore
XCore
XCore
"\nFunction         : "
"\n"
"<--------->\n"
"FrameIndex         : "
"\n"
"FrameOffset        : "
"\n"
"StackSize          : "
"\n"
1
1
1
0
4
0
"Misaligned stack offset"
"Offset             : "
"\n"
"<--------->\n"
4
0
XCore::GRRegsRegClass
"Unexpected register operand"


<s> const char * CAHPTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( CAHPISD :: NodeType ) Opcode ) { case CAHPISD :: FIRST_NUMBER : break ; case CAHPISD :: BR_CC : return "CAHPISD::BR_CC" ; case CAHPISD :: CALL : return "CAHPISD::CALL" ; case CAHPISD :: SELECT_CC : return "CAHPISD::SELECT_CC" ; case CAHPISD :: RET_FLAG : return "CAHPISD::RET_FLAG" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s>
const
char
*
getPassName
(
)
const
override
{
return
"AMDGPU OpenCL Image Type Pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static bool must_reload_pic_reg_p ( void ) { if ( ! TARGET_DSBT ) return false ; cgraph_node * local_info_node = cgraph_node :: local_info_node ( current_function_decl ) ; if ( ( crtl -> uses_pic_offset_table || ! crtl -> is_leaf ) && ! local_info_node -> local ) return true ; return false ; } </s>

Return true if we need to save and modify the PIC register in the prologue .


<s> unsigned int rs6000_special_round_type_align ( tree type , unsigned int computed , unsigned int specified ) { unsigned int align = MAX ( computed , specified ) ; tree field = TYPE_FIELDS ( type ) ; while ( field != NULL && TREE_CODE ( field ) != FIELD_DECL ) field = DECL_CHAIN ( field ) ; if ( field != NULL && field != type ) { type = TREE_TYPE ( field ) ; while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; if ( type != error_mark_node && TYPE_MODE ( type ) == DFmode ) align = MAX ( align , 64 ) ; } return align ; } </s>

Darwin , AIX increases natural record alignment to doubleword if the first field is an FP double while the FP fields remain word aligned .


<s> Register ( const MachineOperand & MO ) : R ( MO . getReg ( ) ) , S ( MO . getSubReg ( ) ) { } </s>


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"ARM Machine Code Emitter"
;
}
</s>


<s> const char * getPassName ( ) const override { return PASS_NAME ; } </s>


<s> unsigned X86InstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex , unsigned & MemBytes ) const { if ( isFrameLoadOpcode ( MI . getOpcode ( ) , MemBytes ) ) if ( MI . getOperand ( 0 ) . getSubReg ( ) == 0 && isFrameOperand ( MI , 1 , FrameIndex ) ) return MI . getOperand ( 0 ) . getReg ( ) ; return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> EVT CSKYTargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & Context , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> static bool rs6000_can_eliminate ( const int from , const int to ) { return ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : from == RS6000_PIC_OFFSET_TABLE_REGNUM ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC_OR_PCREL || constant_pool_empty_p ( ) : true ) ; } </s>

Given FROM and TO register numbers , say whether this elimination is allowed . Frame pointer elimination is automatically handled . For the RS/6000 , if frame pointer elimination is being done , we would like to convert ap into fp , not sp . We need r30 if -mminimal-toc was specified , and there are constant pool references .


<s> static unsigned int frame_header_opt ( ) { struct cgraph_node * node ; function * fn ; FOR_EACH_DEFINED_FUNCTION ( node ) { fn = node -> get_fun ( ) ; if ( fn != NULL ) fn -> machine -> does_not_use_frame_header = ! needs_frame_header_p ( fn ) ; } FOR_EACH_DEFINED_FUNCTION ( node ) { fn = node -> get_fun ( ) ; if ( fn != NULL ) fn -> machine -> optimize_call_stack = ! callees_functions_use_frame_header ( fn ) && ! is_leaf_function ( fn ) ; } FOR_EACH_DEFINED_FUNCTION ( node ) { fn = node -> get_fun ( ) ; if ( fn != NULL && fn -> machine -> optimize_call_stack ) set_callers_may_not_allocate_frame ( fn ) ; } return 0 ; } </s>

Scan each function to determine those that need its frame headers . Perform a second scan to determine if the allocation can be skipped because none of their callees require the frame header .


<s> SDValue AMDGPUTargetLowering :: SplitVectorLoad ( const SDValue & Op , SelectionDAG & DAG ) const { LoadSDNode * Load = dyn_cast < LoadSDNode > ( Op ) ; EVT MemEltVT = Load -> getMemoryVT ( ) . getVectorElementType ( ) ; EVT EltVT = Op . getValueType ( ) . getVectorElementType ( ) ; EVT PtrVT = Load -> getBasePtr ( ) . getValueType ( ) ; unsigned NumElts = Load -> getMemoryVT ( ) . getVectorNumElements ( ) ; SmallVector < SDValue , 8 > Loads ; SDLoc SL ( Op ) ; for ( unsigned i = 0 , e = NumElts ; i != e ; ++ i ) { SDValue Ptr = DAG . getNode ( ISD :: ADD , SL , PtrVT , Load -> getBasePtr ( ) , DAG . getConstant ( i * ( MemEltVT . getSizeInBits ( ) / 8 ) , PtrVT ) ) ; Loads . push_back ( DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , EltVT , Load -> getChain ( ) , Ptr , MachinePointerInfo ( Load -> getMemOperand ( ) -> getValue ( ) ) , MemEltVT , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> getAlignment ( ) ) ) ; } return DAG . getNode ( ISD :: BUILD_VECTOR , SL , Op . getValueType ( ) , Loads ) ; } </s>

Split a vector load into 2 loads of half the vector .


"rs6000_secondary_reload_inner:%d, type = %s\n"

Better tracing for rs6000_secondary_reload_inner .


<s> bool VETargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , Align A , MachineMemOperand :: Flags , bool * Fast ) const { if ( Fast ) { * Fast = true ; } return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> void X86PassConfig :: addPostRegAlloc ( ) { addPass ( createX86FloatingPointStackifierPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


"Unsupported cpu name returned from kernel for "

"Please use an explicit cpu name.  Valid cpu names are: %s"

Returns the canonical AT_PLATFORM if present , otherwise NULL .


<s> void tilegx_compute_pcrel_address ( rtx result , rtx addr ) { rtx text_label_symbol = tilegx_text_label_symbol ( ) ; rtx text_label_rtx = tilegx_text_label_rtx ( ) ; rtx temp , temp2 , temp3 ; temp = create_temp_reg_if_possible ( Pmode , result ) ; temp2 = create_temp_reg_if_possible ( Pmode , result ) ; if ( TARGET_32BIT ) { emit_insn ( gen_mov_pcrel_step1_32bit ( temp , addr , text_label_symbol ) ) ; emit_insn ( gen_mov_pcrel_step2_32bit ( temp2 , temp , addr , text_label_symbol ) ) ; emit_insn ( gen_mov_pcrel_step3_32bit ( result , temp2 , text_label_rtx , addr , text_label_symbol ) ) ; } else if ( tilegx_cmodel == CM_LARGE_PIC ) { temp3 = create_temp_reg_if_possible ( Pmode , result ) ; emit_insn ( gen_mov_large_pcrel_step1 ( temp , addr , text_label_symbol ) ) ; emit_insn ( gen_mov_large_pcrel_step2 ( temp2 , temp , addr , text_label_symbol ) ) ; emit_insn ( gen_mov_large_pcrel_step3 ( temp3 , temp2 , addr , text_label_symbol ) ) ; emit_insn ( gen_mov_large_pcrel_step4 ( result , temp3 , text_label_rtx , addr , text_label_symbol ) ) ; } else { emit_insn ( gen_mov_pcrel_step1 ( temp , addr , text_label_symbol ) ) ; emit_insn ( gen_mov_pcrel_step2 ( temp2 , temp , addr , text_label_symbol ) ) ; emit_insn ( gen_mov_pcrel_step3 ( result , temp2 , text_label_rtx , addr , text_label_symbol ) ) ; } } </s>

Returns a register that points to ADDR , a symbolic address , by computing its address relative to tilegx_text_label_symbol .


<s> int RISCVFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; int MinCSFI = 0 ; int MaxCSFI = - 1 ; int Offset = MFI . getObjectOffset ( FI ) - getOffsetOfLocalArea ( ) + MFI . getOffsetAdjustment ( ) ; if ( CSI . size ( ) ) { MinCSFI = CSI [ 0 ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - 1 ] . getFrameIdx ( ) ; } FrameReg = RI -> getFrameRegister ( MF ) ; if ( FI >= MinCSFI && FI <= MaxCSFI ) { FrameReg = RISCV :: X2 ; Offset += MF . getFrameInfo ( ) . getStackSize ( ) ; } return Offset ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> HOST_WIDE_INT loongarch_initial_elimination_offset ( int from , int to ) { HOST_WIDE_INT src , dest ; loongarch_compute_frame_info ( ) ; if ( to == HARD_FRAME_POINTER_REGNUM ) dest = cfun -> machine -> frame . hard_frame_pointer_offset ; else if ( to == STACK_POINTER_REGNUM ) dest = 0 ; else gcc_unreachable ( ) ; if ( from == FRAME_POINTER_REGNUM ) src = cfun -> machine -> frame . frame_pointer_offset ; else if ( from == ARG_POINTER_REGNUM ) src = cfun -> machine -> frame . arg_pointer_offset ; else gcc_unreachable ( ) ; return src - dest ; } </s>

Implement INITIAL_ELIMINATION_OFFSET . FROM is either the frame pointer or argument pointer . TO is either the stack pointer or hard frame pointer .


<s> unsigned MipsTargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT . isVector ( ) ) return std :: max ( ( ( unsigned ) VT . getSizeInBits ( ) / ( Subtarget . isABI_O32 ( ) ? 32 : 64 ) ) , 1U ) ; return MipsTargetLowering :: getNumRegisters ( Context , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s> void arm_const_bounds ( rtx operand , HOST_WIDE_INT low , HOST_WIDE_INT high ) { bounds_check ( operand , low , high , NULL_TREE , "constant" ) ; } </s>


<s>
SDNode
*
WebAssemblyDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
DEBUG
(
errs
(
)
<<
"Selecting: "
)
;
DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
DEBUG
(
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
nullptr
;
}
SDNode
*
ResNode
=
nullptr
;
EVT
VT
=
Node
->
getValueType
(
0
)
;
switch
(
Node
->
getOpcode
(
)
)
{
default
:
break
;
(
void
)
VT
;
}
ResNode
=
SelectCode
(
Node
)
;
DEBUG
(
errs
(
)
<<
"=> "
)
;
if
(
ResNode
==
nullptr
||
ResNode
==
Node
)
DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
else
DEBUG
(
ResNode
->
dump
(
CurDAG
)
)
;
DEBUG
(
errs
(
)
<<
"\n"
)
;
return
ResNode
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

WebAssembly
WebAssembly
"Selecting: "
"\n"
"== "
"\n"
1
0
"=> "
"\n"


<s> static bool avr_decl_memx_p ( tree decl ) { if ( TREE_CODE ( decl ) != VAR_DECL || TREE_TYPE ( decl ) == error_mark_node ) { return false ; } return ( ADDR_SPACE_MEMX == TYPE_ADDR_SPACE ( TREE_TYPE ( decl ) ) ) ; } </s>

Return TRUE if DECL is a VAR_DECL located in the 24-bit flash address space and FALSE , otherwise .


<s> rtx fusion_wrap_memory_address ( rtx old_mem ) { rtx old_addr = XEXP ( old_mem , 0 ) ; rtvec v = gen_rtvec ( 1 , old_addr ) ; rtx new_addr = gen_rtx_UNSPEC ( Pmode , v , UNSPEC_FUSION_ADDIS ) ; return replace_equiv_address_nv ( old_mem , new_addr , false ) ; } </s>

Wrap a TOC address that can be fused to indicate that special fusion processing is needed .


<s> static bool mips_expand_vpc_loongson_pshufh ( struct expand_vec_perm_d * d ) { unsigned i , mask ; rtx rmask ; if ( ! ( TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI ) ) return false ; if ( d -> vmode != V4HImode ) return false ; if ( d -> testing_p ) return true ; for ( i = mask = 0 ; i < 4 ; i ++ ) mask |= ( d -> perm [ i ] & 3 ) << ( i * 2 ) ; rmask = force_reg ( SImode , GEN_INT ( mask ) ) ; if ( d -> one_vector_p ) emit_insn ( gen_loongson_pshufh ( d -> target , d -> op0 , rmask ) ) ; else { rtx t0 , t1 , x , merge , rmerge [ 4 ] ; t0 = gen_reg_rtx ( V4HImode ) ; t1 = gen_reg_rtx ( V4HImode ) ; emit_insn ( gen_loongson_pshufh ( t1 , d -> op1 , rmask ) ) ; emit_insn ( gen_loongson_pshufh ( t0 , d -> op0 , rmask ) ) ; for ( i = 0 ; i < 4 ; ++ i ) rmerge [ i ] = ( d -> perm [ i ] & 4 ? constm1_rtx : const0_rtx ) ; merge = gen_rtx_CONST_VECTOR ( V4HImode , gen_rtvec_v ( 4 , rmerge ) ) ; merge = force_reg ( V4HImode , merge ) ; x = gen_rtx_AND ( V4HImode , merge , t1 ) ; emit_insn ( gen_rtx_SET ( t1 , x ) ) ; x = gen_rtx_NOT ( V4HImode , merge ) ; x = gen_rtx_AND ( V4HImode , x , t0 ) ; emit_insn ( gen_rtx_SET ( t0 , x ) ) ; x = gen_rtx_IOR ( V4HImode , t0 , t1 ) ; emit_insn ( gen_rtx_SET ( d -> target , x ) ) ; } return true ; } </s>

Recognize patterns for the Loongson PSHUFH instruction .


<s> int cris_simple_epilogue ( ) { int regno ; int reglimit = STACK_POINTER_REGNUM ; int lastreg = - 1 ; if ( ! reload_completed || frame_pointer_needed || get_frame_size ( ) != 0 || current_function_pretend_args_size || current_function_args_size || current_function_outgoing_args_size || current_function_calls_eh_return || ! TARGET_PROLOGUE_EPILOGUE ) return 0 ; for ( regno = 0 ; regno < reglimit ; regno ++ ) if ( ( regs_ever_live [ regno ] && ! call_used_regs [ regno ] ) || ( regno == ( int ) PIC_OFFSET_TABLE_REGNUM && ( current_function_uses_pic_offset_table || ( flag_pic && regs_ever_live [ regno + 1 ] && ! call_used_regs [ regno + 1 ] ) ) ) ) { if ( lastreg != regno - 1 ) return 0 ; lastreg = regno ; } return 1 ; } </s>

Return ! = 0 if the return sequence for the current function is short , like `` ret '' or `` jump [ sp+ ] '' . Prior to reloading , we ca n't tell how many registers must be saved , so return 0 then .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"SI Fold Operands"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool csky_valid_mem_constraint_operand ( rtx op , const char * constraint ) { struct csky_address addr ; if ( GET_CODE ( op ) != MEM ) return false ; if ( ! decompose_csky_address ( XEXP ( op , 0 ) , & addr ) ) return false ; if ( ! is_csky_address_register_rtx_p ( addr . base , 0 ) ) return false ; if ( addr . index && ( constraint [ 0 ] == 'Q' || constraint [ 0 ] == 'W' ) ) { if ( ! is_csky_address_register_rtx_p ( addr . index , 0 ) ) return false ; if ( addr . scale == 1 || addr . scale == 2 || addr . scale == 4 || addr . scale == 8 ) return true ; return false ; } else if ( addr . disp && constraint [ 0 ] == 'Q' ) { rtx disp = addr . disp ; if ( ! CONST_INT_P ( disp ) ) return false ; if ( ( ( unsigned ) INTVAL ( disp ) % 4 ) == 0 && ( unsigned ) INTVAL ( disp ) <= ( unsigned ) 1020 ) return true ; return false ; } else if ( constraint [ 0 ] == 'Q' ) return true ; return false ; } </s>

Support for the Q or W memory constraint . Returns true if OP is a MEM RTX with an address consisting of base + index or base + displacement .


<s>
void
AlphaInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
if
(
RC
==
Alpha
::
F4RCRegisterClass
)
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Alpha
::
STS
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIdx
)
.
addReg
(
Alpha
::
F31
)
;
else
if
(
RC
==
Alpha
::
F8RCRegisterClass
)
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Alpha
::
STT
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIdx
)
.
addReg
(
Alpha
::
F31
)
;
else
if
(
RC
==
Alpha
::
GPRCRegisterClass
)
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Alpha
::
STQ
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIdx
)
.
addReg
(
Alpha
::
F31
)
;
else
llvm_unreachable
(
"Unhandled register class"
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> static void mips_dfa_post_advance_cycle ( void ) { if ( TUNE_LOONGSON_2EF ) mips_ls2_dfa_post_advance_cycle ( curr_state ) ; } </s>

Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE . This hook is being called at the start of each cycle .


<s>
static
void
determineFrameLayout
(
MachineFunction
&
MF
)
{
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
TeeRISCMachineFunctionInfo
*
TFI
=
MF
.
getInfo
<
TeeRISCMachineFunctionInfo
>
(
)
;
TFI
->
adjustLoadArgsFI
(
MFI
)
;
TFI
->
adjustStoreVarArgsFI
(
MFI
)
;
unsigned
FrameSize
=
MFI
->
getStackSize
(
)
;
DEBUG
(
dbgs
(
)
<<
"Original Frame Size: "
<<
FrameSize
<<
"\n"
)
;
unsigned
TargetAlign
=
MF
.
getTarget
(
)
.
getFrameLowering
(
)
->
getStackAlignment
(
)
;
unsigned
AlignMask
=
TargetAlign
1
;
FrameSize
=
(
FrameSize
+
AlignMask
)
&
~
AlignMask
;
MFI
->
setStackSize
(
FrameSize
)
;
DEBUG
(
dbgs
(
)
<<
"Aligned Frame Size: "
<<
FrameSize
<<
"\n"
)
;
}
</s>

Determine the frame layout but do not update the machine function .

TeeRISC
TeeRISC
TeeRISC
"Original Frame Size: "
"\n"
1
"Aligned Frame Size: "
"\n"


<s> static int mcore_ior_cost ( rtx x ) { int val ; if ( GET_CODE ( XEXP ( x , 1 ) ) != CONST_INT ) return 2 ; val = INTVAL ( XEXP ( x , 1 ) ) ; if ( CONST_OK_FOR_M ( val ) ) return 2 ; else if ( const_ok_for_mcore ( val ) ) return 3 ; else if ( TARGET_HARDLIT && mcore_const_ok_for_inline ( val ) ) return 4 ; return 5 ; } </s>

What does an or cost - see and_cost ( ) .


<s> unsigned ARMBaseInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case ARM :: STRrs : case ARM :: t2STRs : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isReg ( ) && MI -> getOperand ( 3 ) . isImm ( ) && MI -> getOperand ( 2 ) . getReg ( ) == 0 && MI -> getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: STRi12 : case ARM :: t2STRi12 : case ARM :: tSTRspi : case ARM :: VSTRD : case ARM :: VSTRS : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VST1q64Pseudo : if ( MI -> getOperand ( 0 ) . isFI ( ) && MI -> getOperand ( 2 ) . getSubReg ( ) == 0 ) { FrameIndex = MI -> getOperand ( 0 ) . getIndex ( ) ; return MI -> getOperand ( 2 ) . getReg ( ) ; } break ; case ARM :: VSTMQIA : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .