<s>
const
char
*
output_ior
(
rtx
*
operands
)
{
unsigned
HOST_WIDE_INT
mask
=
INTVAL
(
operands
[
2
]
)
;
int
bs0
,
bs1
,
p
,
len
;
if
(
INTVAL
(
operands
[
2
]
)
==
0
)
return
"copy %1,%0"
;
for
(
bs0
=
0
;
bs0
<
32
;
bs0
++
)
if
(
(
mask
&
(
1
<<
bs0
)
)
!=
0
)
break
;
for
(
bs1
=
bs0
;
bs1
<
32
;
bs1
++
)
if
(
(
mask
&
(
1
<<
bs1
)
)
==
0
)
break
;
gcc_assert
(
bs1
==
32
||
(
(
unsigned
HOST_WIDE_INT
)
1
<<
bs1
)
>
mask
)
;
p
=
31
bs0
;
len
=
bs1
bs0
;
operands
[
2
]
=
GEN_INT
(
p
)
;
operands
[
3
]
=
GEN_INT
(
len
)
;
return
"{depi|depwi} -1,%2,%3,%0"
;
}
</s>

Emit the code to do an inclusive OR operation .


<s> void MOSInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , Register DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { loadStoreRegStackSlot ( MBB , MI , DestReg , false , FrameIndex , RC , TRI , true ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> bool Cpu0TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_Cpu0 ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> bool PPCTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( DisablePPCPreinc ) return false ; bool isLoad = true ; SDValue Ptr ; EVT VT ; unsigned Alignment ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; Alignment = LD -> getAlignment ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Alignment = ST -> getAlignment ( ) ; isLoad = false ; } else return false ; if ( VT . isVector ( ) ) { if ( ! Subtarget . hasQPX ( ) || ( VT != MVT :: v4f64 && VT != MVT :: v4f32 ) ) { return false ; } else if ( SelectAddressRegRegOnly ( Ptr , Offset , Base , DAG ) ) { AM = ISD :: PRE_INC ; return true ; } } if ( SelectAddressRegReg ( Ptr , Base , Offset , DAG ) ) { bool Swap = false ; if ( isa < FrameIndexSDNode > ( Base ) || isa < RegisterSDNode > ( Base ) ) Swap = true ; else if ( ! isLoad ) { SDValue Val = cast < StoreSDNode > ( N ) -> getValue ( ) ; if ( Val == Base || Base . getNode ( ) -> isPredecessorOf ( Val . getNode ( ) ) ) Swap = true ; } if ( Swap ) std :: swap ( Base , Offset ) ; AM = ISD :: PRE_INC ; return true ; } if ( VT != MVT :: i64 ) { if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , 0 ) ) return false ; } else { if ( Alignment < 4 ) return false ; if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , 4 ) ) return false ; } if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { if ( LD -> getValueType ( 0 ) == MVT :: i64 && LD -> getMemoryVT ( ) == MVT :: i32 && LD -> getExtensionType ( ) == ISD :: SEXTLOAD && isa < ConstantSDNode > ( Offset ) ) return false ; } AM = ISD :: PRE_INC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .


<s>
SDValue
XCoreTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
isVarArg
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .

XCore
XCore
ISD::InputArg
"Unsupported calling convention"


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createARMMachObjectWriter ( OS , false , object :: mach :: CTM_ARM , Subtype ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s>
void
WebAssemblyDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
DEBUG
(
errs
(
)
<<
"Selecting: "
)
;
DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
DEBUG
(
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
EVT
VT
=
Node
->
getValueType
(
0
)
;
switch
(
Node
->
getOpcode
(
)
)
{
default
:
break
;
(
void
)
VT
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

WebAssembly
WebAssembly
"Selecting: "
"\n"
"== "
"\n"
1
0


"Caller should have checked for a comparison"

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


"Unknown architecture specific memory model"

"HLE_ACQUIRE not used with ACQUIRE or stronger memory model"

"HLE_RELEASE not used with RELEASE or stronger memory model"

Validate target specific memory model bits in VAL .


<s> void WebAssemblyAsmPrinter :: emitEndOfAsmFile ( Module & M ) { emitDecls ( M ) ; for ( const auto & F : M ) { if ( ! F . isIntrinsic ( ) && F . hasAddressTaken ( ) ) { MCSymbolWasm * FunctionTable = WebAssembly :: getOrCreateFunctionTableSymbol ( OutContext , Subtarget ) ; OutStreamer -> emitSymbolAttribute ( FunctionTable , MCSA_NoDeadStrip ) ; break ; } } for ( const auto & G : M . globals ( ) ) { if ( ! G . hasInitializer ( ) && G . hasExternalLinkage ( ) && ! WebAssembly :: isWasmVarAddressSpace ( G . getAddressSpace ( ) ) && G . getValueType ( ) -> isSized ( ) ) { uint16_t Size = M . getDataLayout ( ) . getTypeAllocSize ( G . getValueType ( ) ) ; OutStreamer -> emitELFSize ( getSymbol ( & G ) , MCConstantExpr :: create ( Size , OutContext ) ) ; } } if ( const NamedMDNode * Named = M . getNamedMetadata ( "wasm.custom_sections" ) ) { for ( const Metadata * MD : Named -> operands ( ) ) { const auto * Tuple = dyn_cast < MDTuple > ( MD ) ; if ( ! Tuple || Tuple -> getNumOperands ( ) != 2 ) continue ; const MDString * Name = dyn_cast < MDString > ( Tuple -> getOperand ( 0 ) ) ; const MDString * Contents = dyn_cast < MDString > ( Tuple -> getOperand ( 1 ) ) ; if ( ! Name || ! Contents ) continue ; OutStreamer -> PushSection ( ) ; std :: string SectionName = ( ".custom_section." + Name -> getString ( ) ) . str ( ) ; MCSectionWasm * MySection = OutContext . getWasmSection ( SectionName , SectionKind :: getMetadata ( ) ) ; OutStreamer -> SwitchSection ( MySection ) ; OutStreamer -> emitBytes ( Contents -> getString ( ) ) ; OutStreamer -> PopSection ( ) ; } } EmitProducerInfo ( M ) ; EmitTargetFeatures ( M ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


"\n;; Failed condition for casesi_<mode>_sequence\n\n"

Perform some extra checks on operands of casesi_ < mode > _sequence . Not all operand dependencies can be described by means of predicates . This function performs left over checks and should always return true . Returning false means that someone changed the casesi expander but did not adjust casesi_ < mode > _sequence .


<s>
static
void
rs6000_file_start
(
void
)
{
char
buffer
[
80
]
;
const
char
*
start
=
buffer
;
FILE
*
file
=
asm_out_file
;
rs6000_default_cpu
=
TARGET_CPU_DEFAULT
;
default_file_start
(
)
;
if
(
flag_verbose_asm
)
{
sprintf
(
buffer
,
"\n%s rs6000/powerpc options:"
,
ASM_COMMENT_START
)
;
if
(
rs6000_default_cpu
!=
0
&&
rs6000_default_cpu
[
0
]
!=
'\0'
)
{
fprintf
(
file
,
"%s --with-cpu=%s"
,
start
,
rs6000_default_cpu
)
;
start
=
""
;
}
if
(
global_options_set
.
x_rs6000_cpu_index
)
{
fprintf
(
file
,
"%s -mcpu=%s"
,
start
,
processor_target_table
[
rs6000_cpu_index
]
.
name
)
;
start
=
""
;
}
if
(
global_options_set
.
x_rs6000_tune_index
)
{
fprintf
(
file
,
"%s -mtune=%s"
,
start
,
processor_target_table
[
rs6000_tune_index
]
.
name
)
;
start
=
""
;
}
if
(
PPC405_ERRATUM77
)
{
fprintf
(
file
,
"%s PPC405CR_ERRATUM77"
,
start
)
;
start
=
""
;
}
switch
(
rs6000_sdata
)
{
case
SDATA_NONE
:
fprintf
(
file
,
"%s -msdata=none"
,
start
)
;
start
=
""
;
break
;
case
SDATA_DATA
:
fprintf
(
file
,
"%s -msdata=data"
,
start
)
;
start
=
""
;
break
;
case
SDATA_SYSV
:
fprintf
(
file
,
"%s -msdata=sysv"
,
start
)
;
start
=
""
;
break
;
case
SDATA_EABI
:
fprintf
(
file
,
"%s -msdata=eabi"
,
start
)
;
start
=
""
;
break
;
}
if
(
rs6000_sdata
&&
g_switch_value
)
{
fprintf
(
file
,
"%s -G %d"
,
start
,
g_switch_value
)
;
start
=
""
;
}
if
(
*
start
==
'\0'
)
putc
(
'\n'
,
file
)
;
}
if
(
rs6000_default_cpu
==
0
||
rs6000_default_cpu
[
0
]
==
'\0'
||
!
global_options_set
.
x_rs6000_cpu_index
)
{
fputs
(
"\t.machine "
,
asm_out_file
)
;
if
(
(
rs6000_isa_flags
&
OPTION_MASK_DIRECT_MOVE
)
!=
0
)
fputs
(
"power8\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_POPCNTD
)
!=
0
)
fputs
(
"power7\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_CMPB
)
!=
0
)
fputs
(
"power6\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_POPCNTB
)
!=
0
)
fputs
(
"power5\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_MFCRF
)
!=
0
)
fputs
(
"power4\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_POWERPC64
)
!=
0
)
fputs
(
"ppc64\n"
,
asm_out_file
)
;
else
fputs
(
"ppc\n"
,
asm_out_file
)
;
}
if
(
DEFAULT_ABI
==
ABI_ELFv2
)
fprintf
(
file
,
"\t.abiversion 2\n"
)
;
if
(
DEFAULT_ABI
==
ABI_AIX
||
DEFAULT_ABI
==
ABI_ELFv2
||
(
TARGET_ELF
&&
flag_pic
==
2
)
)
{
switch_to_section
(
toc_section
)
;
switch_to_section
(
text_section
)
;
}
}
</s>

Do anything needed at the start of the asm file .


"%qE attribute only applies to functions"

"section of %q+D conflicts with previous declaration"

Handle a `` l1_text '' attribute ; arguments as in struct attribute_spec.handler .


"module has aliases, which LLVM does not yet support for AIX"

Set up the AsmPrinter when we are working on a new module .


<s> bool AArch64InstrInfo :: hasUnscaledLdStOffset ( unsigned Opc ) { switch ( Opc ) { default : return false ; case AArch64 :: STURSi : case AArch64 :: STRSpre : case AArch64 :: STURDi : case AArch64 :: STRDpre : case AArch64 :: STURQi : case AArch64 :: STRQpre : case AArch64 :: STURBBi : case AArch64 :: STURHHi : case AArch64 :: STURWi : case AArch64 :: STRWpre : case AArch64 :: STURXi : case AArch64 :: STRXpre : case AArch64 :: LDURSi : case AArch64 :: LDRSpre : case AArch64 :: LDURDi : case AArch64 :: LDRDpre : case AArch64 :: LDURQi : case AArch64 :: LDRQpre : case AArch64 :: LDURWi : case AArch64 :: LDRWpre : case AArch64 :: LDURXi : case AArch64 :: LDRXpre : case AArch64 :: LDURSWi : case AArch64 :: LDURHHi : case AArch64 :: LDURBBi : case AArch64 :: LDURSBWi : case AArch64 :: LDURSHWi : return true ; } } </s>

Return true if it has an unscaled load/store offset .


<s> bool SIInstrInfo :: findCommutedOpIndices ( MachineInstr * MI , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( ! MCID . isCommutable ( ) ) return false ; unsigned Opc = MI -> getOpcode ( ) ; int Src0Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src0 ) ; if ( Src0Idx == - 1 ) return false ; if ( ! MI -> getOperand ( Src0Idx ) . isReg ( ) ) return false ; int Src1Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src1 ) ; if ( Src1Idx == - 1 ) return false ; if ( ! MI -> getOperand ( Src1Idx ) . isReg ( ) ) return false ; SrcOpIdx1 = Src0Idx ; SrcOpIdx2 = Src1Idx ; return true ; } </s>

Returns true iff the routine could find two commutable operands in the given machine instruction .


<s>
bool
DeadCodeElimination
::
erase
(
const
SetVector
<
NodeId
>
&
Nodes
)
{
if
(
Nodes
.
empty
(
)
)
return
false
;
NodeList
DRNs
,
DINs
;
for
(
auto
I
:
Nodes
)
{
auto
BA
=
DFG
.
addr
<
NodeBase
*
>
(
I
)
;
uint16_t
Type
=
BA
.
Addr
->
getType
(
)
;
if
(
Type
==
NodeAttrs
::
Ref
)
{
DRNs
.
push_back
(
DFG
.
addr
<
RefNode
*
>
(
I
)
)
;
continue
;
}
uint16_t
Kind
=
BA
.
Addr
->
getKind
(
)
;
if
(
Kind
==
NodeAttrs
::
Stmt
||
Kind
==
NodeAttrs
::
Phi
)
{
append_range
(
DRNs
,
NodeAddr
<
CodeNode
*
>
(
BA
)
.
Addr
->
members
(
DFG
)
)
;
DINs
.
push_back
(
DFG
.
addr
<
InstrNode
*
>
(
I
)
)
;
}
else
{
llvm_unreachable
(
"Unexpected code node"
)
;
return
false
;
}
}
auto
UsesFirst
=
[
]
(
NodeAddr
<
RefNode
*
>
A
,
NodeAddr
<
RefNode
*
>
B
)
->
bool
{
uint16_t
KindA
=
A
.
Addr
->
getKind
(
)
,
KindB
=
B
.
Addr
->
getKind
(
)
;
if
(
KindA
==
NodeAttrs
::
Use
&&
KindB
==
NodeAttrs
::
Def
)
return
true
;
if
(
KindA
==
NodeAttrs
::
Def
&&
KindB
==
NodeAttrs
::
Use
)
return
false
;
return
A
.
Id
<
B
.
Id
;
}
;
llvm
::
sort
(
DRNs
,
UsesFirst
)
;
if
(
trace
(
)
)
dbgs
(
)
<<
"Removing dead ref nodes:\n"
;
for
(
NodeAddr
<
RefNode
*
>
RA
:
DRNs
)
{
if
(
trace
(
)
)
dbgs
(
)
<<
"  "
<<
PrintNode
<
RefNode
*
>
(
RA
,
DFG
)
<<
'\n'
;
if
(
DFG
.
IsUse
(
RA
)
)
DFG
.
unlinkUse
(
RA
,
true
)
;
else
if
(
DFG
.
IsDef
(
RA
)
)
DFG
.
unlinkDef
(
RA
,
true
)
;
}
for
(
NodeAddr
<
InstrNode
*
>
IA
:
DINs
)
{
NodeAddr
<
BlockNode
*
>
BA
=
IA
.
Addr
->
getOwner
(
DFG
)
;
BA
.
Addr
->
removeMember
(
IA
,
DFG
)
;
if
(
!
DFG
.
IsCode
<
NodeAttrs
::
Stmt
>
(
IA
)
)
continue
;
MachineInstr
*
MI
=
NodeAddr
<
StmtNode
*
>
(
IA
)
.
Addr
->
getCode
(
)
;
if
(
trace
(
)
)
dbgs
(
)
<<
"erasing: "
<<
*
MI
;
MI
->
eraseFromParent
(
)
;
}
return
true
;
}
</s>

erase - Erases an element identified by Key , if it exists .

Hexagon
"Unexpected code node"
"Removing dead ref nodes:\n"
"  "
"erasing: "


<s> void visium_split_double_add ( enum rtx_code code , rtx op0 , rtx op1 , rtx op2 ) { rtx op3 = gen_lowpart ( SImode , op0 ) ; rtx op4 = gen_lowpart ( SImode , op1 ) ; rtx op5 ; rtx op6 = gen_highpart ( SImode , op0 ) ; rtx op7 = ( op1 == const0_rtx ? op1 : gen_highpart ( SImode , op1 ) ) ; rtx op8 ; rtx x , pat , flags ; if ( CONST_INT_P ( op2 ) ) { HOST_WIDE_INT val = INTVAL ( op2 ) ; if ( val < 0 ) { code = ( code == MINUS ? PLUS : MINUS ) ; val = - val ; } op5 = gen_int_mode ( val , SImode ) ; op8 = const0_rtx ; } else { op5 = gen_lowpart ( SImode , op2 ) ; op8 = gen_highpart ( SImode , op2 ) ; } if ( op4 == const0_rtx ) pat = gen_negsi2_insn_set_carry ( op3 , op5 ) ; else if ( code == MINUS ) pat = gen_subsi3_insn_set_carry ( op3 , op4 , op5 ) ; else pat = gen_addsi3_insn_set_carry ( op3 , op4 , op5 ) ; emit_insn ( pat ) ; if ( op8 == const0_rtx ) x = op7 ; else x = gen_rtx_fmt_ee ( code , SImode , op7 , op8 ) ; flags = gen_rtx_REG ( CCCmode , FLAGS_REGNUM ) ; x = gen_rtx_fmt_ee ( code , SImode , x , gen_rtx_LTU ( SImode , flags , const0_rtx ) ) ; pat = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( 2 ) ) ; XVECEXP ( pat , 0 , 0 ) = gen_rtx_SET ( op6 , x ) ; flags = gen_rtx_REG ( CCmode , FLAGS_REGNUM ) ; XVECEXP ( pat , 0 , 1 ) = gen_rtx_CLOBBER ( VOIDmode , flags ) ; emit_insn ( pat ) ; visium_flags_exposed = true ; } </s>

Split a double addition or subtraction of operands .


<s> void M68kAsmPrinter :: emitFunctionBodyStart ( ) { } </s>

Targets can override this to emit stuff before the first basic block in the function .


<s> TPCII :: IType TPCMCInstrInfo :: getType ( MCInstrInfo const & MCII , MCInst const & MCI ) { return static_cast < TPCII :: IType > ( TPCII :: getInstrType ( getDesc ( MCII , MCI ) ) ) ; } </s>

Overload to return most specific vector type .


<s> void PHILinearize :: clear ( ) { PHIInfo = PHIInfoT ( ) ; } </s>


<s> bool PPCFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( ! Subtarget . isSVR4ABI ( ) ) return false ; MachineFunction * MF = MBB . getParent ( ) ; const PPCInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc DL ; bool CRSpilled = false ; MachineInstrBuilder CRMIB ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg == PPC :: VRSAVE && ! Subtarget . isDarwinABI ( ) ) continue ; bool IsCRField = PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ; MBB . addLiveIn ( Reg ) ; if ( CRSpilled && IsCRField ) { CRMIB . addReg ( Reg , RegState :: ImplicitKill ) ; continue ; } if ( IsCRField ) { PPCFunctionInfo * FuncInfo = MF -> getInfo < PPCFunctionInfo > ( ) ; if ( Subtarget . isPPC64 ( ) ) { FuncInfo -> addMustSaveCR ( Reg ) ; } else { CRSpilled = true ; FuncInfo -> setSpillsCR ( ) ; CRMIB = BuildMI ( * MF , DL , TII . get ( PPC :: MFCR ) , PPC :: R12 ) . addReg ( Reg , RegState :: ImplicitKill ) ; MBB . insert ( MI , CRMIB ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( PPC :: STW ) ) . addReg ( PPC :: R12 , getKillRegState ( true ) ) , CSI [ i ] . getFrameIdx ( ) ) ) ; } } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> void M68kFrameLowering :: emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , int64_t NumBytes , bool InEpilogue ) const { bool IsSub = NumBytes < 0 ; uint64_t Offset = IsSub ? - NumBytes : NumBytes ; uint64_t Chunk = ( 1LL << 31 ) - 1 ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { if ( Offset > Chunk ) { Register Reg ; if ( IsSub && ! isRegLiveIn ( MBB , M68k :: D0 ) ) Reg = M68k :: D0 ; else Reg = findDeadCallerSavedReg ( MBB , MBBI , TRI ) ; if ( Reg ) { unsigned Opc = M68k :: MOV32ri ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , Reg ) . addImm ( Offset ) ; Opc = IsSub ? M68k :: SUB32rr : M68k :: ADD32rr ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addReg ( Reg ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; Offset = 0 ; continue ; } } uint64_t ThisVal = std :: min ( Offset , Chunk ) ; MachineInstrBuilder MI = BuildStackAdjustment ( MBB , MBBI , DL , IsSub ? - ThisVal : ThisVal , InEpilogue ) ; if ( IsSub ) MI . setMIFlag ( MachineInstr :: FrameSetup ) ; else MI . setMIFlag ( MachineInstr :: FrameDestroy ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> bool ARMFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; unsigned PushOpc = AFI -> isThumbFunction ( ) ? ARM :: t2STMDB_UPD : ARM :: STMDB_UPD ; unsigned PushOneOpc = AFI -> isThumbFunction ( ) ? ARM :: t2STR_PRE : ARM :: STR_PRE_IMM ; unsigned FltOpc = ARM :: VSTMDDB_UPD ; unsigned NumAlignedDPRCS2Regs = AFI -> getNumAlignedDPRCS2Regs ( ) ; if ( llvm :: any_of ( CSI , [ ] ( const CalleeSavedInfo & C ) { return C . getReg ( ) == ARM :: FPCXTNS ; } ) ) { BuildMI ( MBB , MI , DebugLoc ( ) , STI . getInstrInfo ( ) -> get ( ARM :: VSTR_FPCXTNS_pre ) , ARM :: SP ) . addReg ( ARM :: SP ) . addImm ( - 4 ) . add ( predOps ( ARMCC :: AL ) ) ; } emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & isARMArea1Register , 0 , MachineInstr :: FrameSetup ) ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & isARMArea2Register , 0 , MachineInstr :: FrameSetup ) ; emitPushInst ( MBB , MI , CSI , FltOpc , 0 , true , & isARMArea3Register , NumAlignedDPRCS2Regs , MachineInstr :: FrameSetup ) ; if ( NumAlignedDPRCS2Regs ) emitAlignedDPRCS2Spills ( MBB , MI , NumAlignedDPRCS2Regs , CSI , TRI ) ; return true ; } </s>


<s> static int arm_get_strip_length ( int c ) { switch ( c ) { ARM_NAME_ENCODING_LENGTHS default : return 0 ; } } </s>

Return the length of a function name prefix that starts with the character ' c ' .


<s> MVT :: SimpleValueType getCmpLibcallReturnType ( ) const override { return MVT :: i8 ; } </s>

Return the ValueType for comparison libcalls .


<s> int arc_hazard ( rtx_insn * pred , rtx_insn * succ ) { if ( ! pred || ! INSN_P ( pred ) || ! succ || ! INSN_P ( succ ) ) return 0 ; if ( arc_loop_hazard ( pred , succ ) ) return 4 ; if ( TARGET_ARC600 ) return arc600_corereg_hazard ( pred , succ ) ; return 0 ; } </s>

For ARC600 : A write to a core reg greater or equal to 32 must not be immediately followed by a use . Anticipate the length requirement to insert a nop between PRED and SUCC to prevent a hazard .


<s> void LanaiTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; } </s>

This method must be called before any actual lowering is done .


<s> static bool pass_in_memory ( machine_mode mode , const_tree type , bool for_return ) { if ( type ) { if ( AGGREGATE_TYPE_P ( type ) ) return true ; if ( TREE_CODE ( type ) == VECTOR_TYPE ) return true ; } if ( ! for_return && COMPLEX_MODE_P ( mode ) ) mode = GET_MODE_INNER ( mode ) ; if ( GET_MODE_CLASS ( mode ) != MODE_INT && GET_MODE_CLASS ( mode ) != MODE_FLOAT ) return true ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) return true ; return false ; } </s>

Determine whether MODE and TYPE ( possibly NULL ) should be passed or returned in memory . Integer and floating types supported by the machine are passed in registers , everything else is passed in memory . Complex types are split .


<s> static bool isKnownNonNull ( Register Val , MachineRegisterInfo & MRI , const AMDGPUTargetMachine & TM , unsigned AddrSpace ) { MachineInstr * Def = MRI . getVRegDef ( Val ) ; switch ( Def -> getOpcode ( ) ) { case AMDGPU :: G_FRAME_INDEX : case AMDGPU :: G_GLOBAL_VALUE : case AMDGPU :: G_BLOCK_ADDR : return true ; case AMDGPU :: G_CONSTANT : { const ConstantInt * CI = Def -> getOperand ( 1 ) . getCImm ( ) ; return CI -> getSExtValue ( ) != TM . getNullPointerValue ( AddrSpace ) ; } default : return false ; } return false ; } </s>

Return true if we know that underlying value is nonnull .


<s> bool ARMCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto DL = MF . getDataLayout ( ) ; auto & TLI = * getTLI < ARMTargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb ( ) ) return false ; if ( Subtarget -> useSoftFloat ( ) || ! Subtarget -> hasVFP2 ( ) ) return false ; for ( auto & Arg : F . args ( ) ) if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; SmallVector < ArgInfo , 8 > ArgInfos ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + 1 , DL , F ) ; splitToValueTypes ( AInfo , ArgInfos , DL , MF . getRegInfo ( ) ) ; Idx ++ ; } FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; return handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> unsigned PPCTTIImpl :: getCacheLineSize ( ) const { if ( CacheLineSize . getNumOccurrences ( ) > 0 ) return CacheLineSize ; unsigned Directive = ST -> getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_PWR7 || Directive == PPC :: DIR_PWR8 || Directive == PPC :: DIR_PWR9 ) return 128 ; return 64 ; } </s>

Return the target cache line size in bytes .


<s> const DataLayout * getDataLayout ( ) const override { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> static bool aarch64_sve_valid_immediate ( unsigned HOST_WIDE_INT val64 , simd_immediate_info * info ) { scalar_int_mode mode = DImode ; unsigned int val32 = val64 & 0xffffffff ; if ( val32 == ( val64 >> 32 ) ) { mode = SImode ; unsigned int val16 = val32 & 0xffff ; if ( val16 == ( val32 >> 16 ) ) { mode = HImode ; unsigned int val8 = val16 & 0xff ; if ( val8 == ( val16 >> 8 ) ) mode = QImode ; } } HOST_WIDE_INT val = trunc_int_for_mode ( val64 , mode ) ; if ( IN_RANGE ( val , - 0x80 , 0x7f ) ) { if ( info ) * info = simd_immediate_info ( mode , val ) ; return true ; } if ( ( val & 0xff ) == 0 && IN_RANGE ( val , - 0x8000 , 0x7f00 ) ) { if ( info ) * info = simd_immediate_info ( mode , val ) ; return true ; } if ( aarch64_bitmask_imm ( val64 , mode ) ) { if ( info ) * info = simd_immediate_info ( mode , val ) ; return true ; } return false ; } </s>

Return true if replicating VAL64 gives a valid immediate for an SVE MOV instruction . If INFO is nonnull , use it to describe valid immediates .


<s> bool MipsTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_Mips ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> void tilepro_expand_tablejump ( rtx op0 , rtx op1 ) { if ( flag_pic ) { rtx table = gen_rtx_LABEL_REF ( Pmode , op1 ) ; rtx temp = gen_reg_rtx ( Pmode ) ; rtx text_label_symbol = tilepro_text_label_symbol ( ) ; rtx text_label_rtx = tilepro_text_label_rtx ( ) ; emit_insn ( gen_addli_pcrel ( temp , text_label_rtx , table , text_label_symbol ) ) ; emit_insn ( gen_auli_pcrel ( temp , temp , table , text_label_symbol ) ) ; emit_move_insn ( temp , gen_rtx_PLUS ( Pmode , convert_to_mode ( Pmode , op0 , false ) , temp ) ) ; op0 = temp ; } emit_jump_insn ( gen_tablejump_aux ( op0 , op1 ) ) ; } </s>


<s> rtx bfin_gen_compare ( rtx cmp , enum machine_mode mode ATTRIBUTE_UNUSED ) { enum rtx_code code1 , code2 ; rtx op0 = bfin_compare_op0 , op1 = bfin_compare_op1 ; rtx tem = bfin_cc_rtx ; enum rtx_code code = GET_CODE ( cmp ) ; if ( GET_MODE ( op0 ) == BImode ) { gcc_assert ( ( code == NE || code == EQ ) && op1 == const0_rtx ) ; tem = op0 , code2 = code ; } else { switch ( code ) { case EQ : case LT : case LE : case LEU : case LTU : code1 = code ; code2 = NE ; break ; default : code1 = reverse_condition ( code ) ; code2 = EQ ; break ; } emit_insn ( gen_rtx_SET ( BImode , tem , gen_rtx_fmt_ee ( code1 , BImode , op0 , op1 ) ) ) ; } return gen_rtx_fmt_ee ( code2 , BImode , tem , CONST0_RTX ( BImode ) ) ; } </s>

Emit rtl for a comparison operation CMP in mode MODE . Operands have been stored in bfin_compare_op0 and bfin_compare_op1 already .


"Lowering returned the wrong number of results!"

This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types .


<s> Function * AMDGPULibFunc :: getOrInsertFunction ( Module * M , const AMDGPULibFunc & fInfo ) { std :: string const FuncName = fInfo . mangle ( ) ; Function * F = dyn_cast_or_null < Function > ( M -> getValueSymbolTable ( ) . lookup ( FuncName ) ) ; if ( F && ! F -> isDeclaration ( ) && ! F -> isVarArg ( ) && F -> arg_size ( ) == fInfo . getNumArgs ( ) ) { return F ; } FunctionType * FuncTy = fInfo . getFunctionType ( * M ) ; bool hasPtr = false ; for ( FunctionType :: param_iterator PI = FuncTy -> param_begin ( ) , PE = FuncTy -> param_end ( ) ; PI != PE ; ++ PI ) { const Type * argTy = static_cast < const Type * > ( * PI ) ; if ( argTy -> isPointerTy ( ) ) { hasPtr = true ; break ; } } Constant * C = nullptr ; if ( hasPtr ) { C = M -> getOrInsertFunction ( FuncName , FuncTy ) ; } else { AttributeList Attr ; LLVMContext & Ctx = M -> getContext ( ) ; Attr . addAttribute ( Ctx , AttributeList :: FunctionIndex , Attribute :: ReadOnly ) ; Attr . addAttribute ( Ctx , AttributeList :: FunctionIndex , Attribute :: NoUnwind ) ; C = M -> getOrInsertFunction ( FuncName , FuncTy , Attr ) ; } return cast < Function > ( C ) ; } </s>

Look up the specified function in the module symbol table .


<s> static rtx frv_expand_voidtriop_builtin ( enum insn_code icode , tree arglist ) { rtx pat ; rtx op0 = frv_read_argument ( & arglist ) ; rtx op1 = frv_read_argument ( & arglist ) ; rtx op2 = frv_read_argument ( & arglist ) ; rtx op3 ; op0 = frv_int_to_acc ( icode , 0 , op0 ) ; if ( ! op0 ) return NULL_RTX ; op1 = frv_legitimize_argument ( icode , 1 , op1 ) ; op2 = frv_legitimize_argument ( icode , 2 , op2 ) ; op3 = frv_matching_accg_for_acc ( op0 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 , op2 , op3 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return NULL_RTX ; } </s>

Expand builtins that take three operands and return void . The first argument must be a constant that describes a pair or quad accumulators . A fourth argument is created that is the accumulator guard register that corresponds to the accumulator .


<s> int arm_no_early_alu_shift_value_dep ( rtx producer , rtx consumer ) { rtx value , op ; rtx early_op ; if ( ! arm_get_set_operands ( producer , consumer , & value , & op ) ) return 0 ; if ( ( early_op = arm_find_shift_sub_rtx ( op ) ) ) if ( ! reg_overlap_mentioned_p ( value , XEXP ( early_op , 0 ) ) ) return 1 ; return 0 ; } </s>

Return nonzero if the CONSUMER instruction ( an ALU op ) does not have an early register shift value dependency on the result of PRODUCER .


<s> void MipsSEFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; const MipsSEInstrInfo & TII = * static_cast < const MipsSEInstrInfo * > ( STI . getInstrInfo ( ) ) ; const MipsRegisterInfo & RegInfo = * static_cast < const MipsRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; unsigned SP = ABI . GetStackPtr ( ) ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned ZERO = ABI . GetNullPtr ( ) ; unsigned MOVE = ABI . GetGPRMoveOp ( ) ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI . getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , DL , TII . get ( MOVE ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( MipsFI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = ABI . ArePtrs64bit ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI . getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = 0 ; J < 4 ; ++ J ) { TII . loadRegFromStackSlot ( MBB , I , ABI . GetEhDataReg ( J ) , MipsFI -> getEhDataRegFI ( J ) , RC , & RegInfo ) ; } } if ( MF . getFunction ( ) . hasFnAttribute ( "interrupt" ) ) emitInterruptEpilogueStub ( MF , MBB ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize , MBB , MBBI ) ; } </s>

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips 0 Mips Mips::GPR64RegClass Mips::GPR32RegClass 0 0 4 Mips "interrupt"


<s> bool RISCVTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , Subtarget . isRV64 ( ) ? RetCC_RISCV64 : RetCC_RISCV32 ) ; } </s>

RISCV RISCV ISD::OutputArg 16 RISCV RISCV


Generate a sequence of instructions that zero registers specified by NEED_ZEROED_HARDREGS . Return the ZEROED_HARDREGS that are actually zeroed .


<s> static void arm_test_cpu_arch_data ( void ) { const arch_option * arch ; const cpu_option * cpu ; auto_sbitmap target_isa ( isa_num_bits ) ; auto_sbitmap isa1 ( isa_num_bits ) ; auto_sbitmap isa2 ( isa_num_bits ) ; for ( arch = all_architectures ; arch -> common . name != NULL ; ++ arch ) { const cpu_arch_extension * ext1 , * ext2 ; if ( arch -> common . extensions == NULL ) continue ; arm_initialize_isa ( target_isa , arch -> common . isa_bits ) ; for ( ext1 = arch -> common . extensions ; ext1 -> name != NULL ; ++ ext1 ) { if ( ext1 -> alias ) continue ; arm_initialize_isa ( isa1 , ext1 -> isa_bits ) ; for ( ext2 = ext1 + 1 ; ext2 -> name != NULL ; ++ ext2 ) { if ( ext2 -> alias || ext1 -> remove != ext2 -> remove ) continue ; arm_initialize_isa ( isa2 , ext2 -> isa_bits ) ; ASSERT_TRUE ( ! bitmap_subset_p ( isa2 , isa1 ) ) ; ASSERT_TRUE ( ! bitmap_intersect_p ( isa2 , target_isa ) ) ; } } } for ( cpu = all_cores ; cpu -> common . name != NULL ; ++ cpu ) { const cpu_arch_extension * ext1 , * ext2 ; if ( cpu -> common . extensions == NULL ) continue ; arm_initialize_isa ( target_isa , arch -> common . isa_bits ) ; for ( ext1 = cpu -> common . extensions ; ext1 -> name != NULL ; ++ ext1 ) { if ( ext1 -> alias ) continue ; arm_initialize_isa ( isa1 , ext1 -> isa_bits ) ; for ( ext2 = ext1 + 1 ; ext2 -> name != NULL ; ++ ext2 ) { if ( ext2 -> alias || ext1 -> remove != ext2 -> remove ) continue ; arm_initialize_isa ( isa2 , ext2 -> isa_bits ) ; ASSERT_TRUE ( ! bitmap_subset_p ( isa2 , isa1 ) ) ; ASSERT_TRUE ( ! bitmap_intersect_p ( isa2 , target_isa ) ) ; } } } } </s>

Scan the static data tables generated by parsecpu.awk looking for potential issues with the data . We primarily check for inconsistencies in the option extensions at present ( extensions that duplicate others but are n't marked as aliases ) . Furthermore , for correct canonicalization later options must never be a subset of an earlier option . Any extension should also only specify other feature bits and never an architecture bit . The architecture is inferred from the declaration of the extension .


<s> void X86PassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createExecutionDependencyFixPass ( & X86 :: VR128RegClass ) ) ; if ( UseVZeroUpper ) addPass ( createX86IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86PadShortFunctions ( ) ) ; addPass ( createX86FixupLEAs ( ) ) ; } if ( Triple ( TM -> getTargetTriple ( ) ) . isOSNaCl ( ) ) { addPass ( createX86NaClRewritePass ( ) ) ; } } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void MSP430MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; unsigned Size = Desc . getSize ( ) ; Offset = 2 ; uint64_t BinaryOpCode = getBinaryCodeForInstr ( MI , Fixups , STI ) ; size_t WordCount = Size / 2 ; while ( WordCount -- ) { support :: endian :: write ( OS , ( uint16_t ) BinaryOpCode , support :: little ) ; BinaryOpCode >>= 16 ; } } </s>

Encode the given Inst to bytes and append to CB .


<s> bool R600MCCodeEmitter :: isFlagSet ( const MCInst & MI , unsigned Operand , unsigned Flag ) const { const MCInstrDesc & MCDesc = MCII . get ( MI . getOpcode ( ) ) ; unsigned FlagIndex = GET_FLAG_OPERAND_IDX ( MCDesc . TSFlags ) ; if ( FlagIndex == 0 ) { return false ; } assert ( MI . getOperand ( FlagIndex ) . isImm ( ) ) ; return ! ! ( ( MI . getOperand ( FlagIndex ) . getImm ( ) >> ( NUM_MO_FLAGS * Operand ) ) & Flag ) ; } </s>

Determine if the specified Flag is set on this Operand .


<s>
int
ARM64LoadStoreOpt
::
getMemSize
(
MachineInstr
*
MemMI
)
{
switch
(
MemMI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Opcode has has unknown size!"
)
;
case
ARM64
::
STRSui
:
case
ARM64
::
STURSi
:
return
4
;
case
ARM64
::
STRDui
:
case
ARM64
::
STURDi
:
return
8
;
case
ARM64
::
STRQui
:
case
ARM64
::
STURQi
:
return
16
;
case
ARM64
::
STRWui
:
case
ARM64
::
STURWi
:
return
4
;
case
ARM64
::
STRXui
:
case
ARM64
::
STURXi
:
return
8
;
case
ARM64
::
LDRSui
:
case
ARM64
::
LDURSi
:
return
4
;
case
ARM64
::
LDRDui
:
case
ARM64
::
LDURDi
:
return
8
;
case
ARM64
::
LDRQui
:
case
ARM64
::
LDURQi
:
return
16
;
case
ARM64
::
LDRWui
:
case
ARM64
::
LDURWi
:
return
4
;
case
ARM64
::
LDRXui
:
case
ARM64
::
LDURXi
:
return
8
;
}
}
</s>

Returns the size in bytes of the memory access .


<s>
static
const
char
*
singlemove_string
(
rtx
*
operands
)
{
if
(
operands
[
1
]
!=
const0_rtx
)
return
"mov %1,%0"
;
return
"clr %0"
;
}
</s>

Return the best assembler insn template for moving operands [ 1 ] into operands [ 0 ] as a fullword .


<s> static bool aarch64_extending_load_p ( stmt_vec_info stmt_info ) { gassign * assign = dyn_cast < gassign * > ( stmt_info -> stmt ) ; if ( ! assign || ! CONVERT_EXPR_CODE_P ( gimple_assign_rhs_code ( assign ) ) ) return false ; tree rhs = gimple_assign_rhs1 ( stmt_info -> stmt ) ; tree lhs_type = TREE_TYPE ( gimple_assign_lhs ( assign ) ) ; tree rhs_type = TREE_TYPE ( rhs ) ; if ( ! INTEGRAL_TYPE_P ( lhs_type ) || ! INTEGRAL_TYPE_P ( rhs_type ) || TYPE_PRECISION ( lhs_type ) <= TYPE_PRECISION ( rhs_type ) ) return false ; stmt_vec_info def_stmt_info = stmt_info -> vinfo -> lookup_def ( rhs ) ; return ( def_stmt_info && STMT_VINFO_DATA_REF ( def_stmt_info ) && DR_IS_READ ( STMT_VINFO_DATA_REF ( def_stmt_info ) ) ) ; } </s>

Return true if STMT_INFO extends the result of a load .


<s> bool MipsSEDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & TM . getSubtarget < MipsSubtarget > ( ) ; if ( Subtarget -> inMips16Mode ( ) ) return false ; return MipsDAGToDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s>
bool
HSAILMCAsmInfo
::
isValidUnquotedName
(
StringRef
Name
)
const
{
char
First
=
Name
.
front
(
)
;
assert
(
(
First
==
'%'
||
First
==
'&'
||
First
==
'@'
)
&&
"Missing valid prefix character"
)
;
Name
=
Name
.
drop_front
(
1
)
;
if
(
!
Name
.
empty
(
)
)
{
if
(
!
isValidFirstChar
(
Name
.
front
(
)
)
)
return
false
;
Name
=
Name
.
drop_front
(
)
;
}
for
(
char
C
:
Name
)
{
if
(
!
isValidChar
(
C
)
)
return
false
;
}
return
true
;
}
</s>

Return true if the identifier Name does not need quotes to be syntactically correct .

HSAIL
HSAIL
"Missing valid prefix character"
1


<s> unsigned NyuziTTIImpl :: getNumberOfRegisters ( bool Vec ) const { return 32 ; } </s>


<s> static void compute_save_world_info ( rs6000_stack_t * info_ptr ) { info_ptr -> world_save_p = 1 ; info_ptr -> world_save_p = ( WORLD_SAVE_P ( info_ptr ) && DEFAULT_ABI == ABI_DARWIN && ! ( current_function_calls_setjmp && flag_exceptions ) && info_ptr -> first_fp_reg_save == FIRST_SAVED_FP_REGNO && info_ptr -> first_gp_reg_save == FIRST_SAVED_GP_REGNO && info_ptr -> first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO && info_ptr -> cr_save_p ) ; if ( WORLD_SAVE_P ( info_ptr ) ) { rtx insn ; for ( insn = get_last_insn_anywhere ( ) ; insn ; insn = PREV_INSN ( insn ) ) if ( GET_CODE ( insn ) == CALL_INSN && SIBLING_CALL_P ( insn ) ) { info_ptr -> world_save_p = 0 ; break ; } } if ( WORLD_SAVE_P ( info_ptr ) ) { info_ptr -> vrsave_size = 4 ; if ( info_ptr -> vrsave_mask == 0 ) info_ptr -> vrsave_mask = compute_vrsave_mask ( ) ; gcc_assert ( info_ptr -> first_fp_reg_save >= FIRST_SAVED_FP_REGNO && ( info_ptr -> first_altivec_reg_save >= FIRST_SAVED_ALTIVEC_REGNO ) ) ; } return ; } </s>

For a very restricted set of circumstances , we can cut down the size of prologues/epilogues by calling our own save/restore-the-world routines .


<s> const HexagonSubtarget * HexagonTargetMachine :: getSubtargetImpl ( const Function & F ) const { AttributeList FnAttrs = F . getAttributes ( ) ; Attribute CPUAttr = FnAttrs . getFnAttr ( "target-cpu" ) ; Attribute FSAttr = FnAttrs . getFnAttr ( "target-features" ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; if ( F . getFnAttribute ( "unsafe-fp-math" ) . getValueAsBool ( ) ) FS = FS . empty ( ) ? "+unsafe-fp" : "+unsafe-fp," + FS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < HexagonSubtarget > ( TargetTriple , CPU , FS , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

Hexagon Hexagon Hexagon "target-cpu" "target-features" "unsafe-fp-math" "+unsafe-fp" "+unsafe-fp," Hexagon


<s>
void
WebAssemblyTargetAsmStreamer
::
emitGlobalType
(
const
MCSymbolWasm
*
Sym
)
{
assert
(
Sym
->
isGlobal
(
)
)
;
OS
<<
"\t.globaltype\t"
<<
Sym
->
getName
(
)
<<
", "
<<
WebAssembly
::
typeToString
(
static_cast
<
wasm
::
ValType
>
(
Sym
->
getGlobalType
(
)
.
Type
)
)
;
if
(
!
Sym
->
getGlobalType
(
)
.
Mutable
)
OS
<<
", immutable"
;
OS
<<
'\n'
;
}
</s>

WebAssembly
WebAssembly
"\t.globaltype\t"
", "
WebAssembly::typeToString
wasm::ValType
", immutable"


<s> bool emitSymbolAttribute ( MCSymbol * Symbol , MCSymbolAttr Attribute ) override { return true ; } </s>


<s> static int v850_arg_partial_bytes ( cumulative_args_t cum_v , machine_mode mode , tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int size , align ; if ( ! named ) return 0 ; if ( mode == BLKmode ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; if ( size < 1 ) size = 1 ; if ( ! TARGET_GCC_ABI ) align = UNITS_PER_WORD ; else if ( type ) align = TYPE_ALIGN ( type ) / BITS_PER_UNIT ; else align = size ; cum -> nbytes = ( cum -> nbytes + align - 1 ) & ~ ( align - 1 ) ; if ( cum -> nbytes > 4 * UNITS_PER_WORD ) return 0 ; if ( cum -> nbytes + size <= 4 * UNITS_PER_WORD ) return 0 ; if ( type == NULL_TREE && cum -> nbytes + size > 4 * UNITS_PER_WORD ) return 0 ; return 4 * UNITS_PER_WORD - cum -> nbytes ; } </s>

Return the number of bytes which must be put into registers for values which are part in registers and part in memory .


<s> void BTFDebug :: beginInstruction ( const MachineInstr * MI ) { DebugHandlerBase :: beginInstruction ( MI ) ; if ( SkipInstruction || MI -> isMetaInstruction ( ) || MI -> getFlag ( MachineInstr :: FrameSetup ) ) return ; if ( MI -> isInlineAsm ( ) ) { unsigned NumDefs = 0 ; for ( ; MI -> getOperand ( NumDefs ) . isReg ( ) && MI -> getOperand ( NumDefs ) . isDef ( ) ; ++ NumDefs ) ; const char * AsmStr = MI -> getOperand ( NumDefs ) . getSymbolName ( ) ; if ( AsmStr [ 0 ] == 0 ) return ; } const DebugLoc & DL = MI -> getDebugLoc ( ) ; if ( ! DL || PrevInstLoc == DL ) { if ( LineInfoGenerated == false ) { auto * S = MI -> getMF ( ) -> getFunction ( ) . getSubprogram ( ) ; MCSymbol * FuncLabel = Asm -> getFunctionBegin ( ) ; constructLineInfo ( S , FuncLabel , S -> getLine ( ) , 0 ) ; LineInfoGenerated = true ; } return ; } MCSymbol * LineSym = OS . getContext ( ) . createTempSymbol ( ) ; OS . EmitLabel ( LineSym ) ; auto SP = DL . get ( ) -> getScope ( ) -> getSubprogram ( ) ; constructLineInfo ( SP , LineSym , DL . getLine ( ) , DL . getCol ( ) ) ; LineInfoGenerated = true ; PrevInstLoc = DL ; } </s>


<s> bool MipsSEFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * EntryBlock = MF -> begin ( ) ; const TargetInstrInfo & TII = * MF -> getTarget ( ) . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == Mips :: RA || Reg == Mips :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> bool PPCAsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { std :: string NewOpcode ; if ( parseOptionalToken ( AsmToken :: Plus ) ) { NewOpcode = std :: string ( Name ) ; NewOpcode += '+' ; Name = NewOpcode ; } if ( parseOptionalToken ( AsmToken :: Minus ) ) { NewOpcode = std :: string ( Name ) ; NewOpcode += '-' ; Name = NewOpcode ; } size_t Dot = Name . find ( '.' ) ; StringRef Mnemonic = Name . slice ( 0 , Dot ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( PPCOperand :: CreateTokenWithStringCopy ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; else Operands . push_back ( PPCOperand :: CreateToken ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; if ( Dot != StringRef :: npos ) { SMLoc DotLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Dot ) ; StringRef DotStr = Name . slice ( Dot , StringRef :: npos ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( PPCOperand :: CreateTokenWithStringCopy ( DotStr , DotLoc , isPPC64 ( ) ) ) ; else Operands . push_back ( PPCOperand :: CreateToken ( DotStr , DotLoc , isPPC64 ( ) ) ) ; } if ( parseOptionalToken ( AsmToken :: EndOfStatement ) ) return false ; if ( ParseOperand ( Operands ) ) return true ; while ( ! parseOptionalToken ( AsmToken :: EndOfStatement ) ) { if ( parseToken ( AsmToken :: Comma ) || ParseOperand ( Operands ) ) return true ; } if ( getSTI ( ) . getFeatureBits ( ) [ PPC :: FeatureBookE ] && Operands . size ( ) == 4 && ( Name == "dcbt" || Name == "dcbtst" ) ) { std :: swap ( Operands [ 1 ] , Operands [ 3 ] ) ; std :: swap ( Operands [ 2 ] , Operands [ 1 ] ) ; } if ( Name == "lqarx" || Name == "ldarx" || Name == "lwarx" || Name == "lharx" || Name == "lbarx" ) { if ( Operands . size ( ) != 5 ) return false ; PPCOperand & EHOp = ( PPCOperand & ) * Operands [ 4 ] ; if ( EHOp . isU1Imm ( ) && EHOp . getImm ( ) == 0 ) Operands . pop_back ( ) ; } return false ; } </s>

ParseInstruction - Parse one assembly instruction .

PowerPC PPC 0 PPC PPC PPC PPC PPC PPC PPC PPC PPC::FeatureBookE 4 "dcbt" "dcbtst" 1 3 2 1 "lqarx" "ldarx" "lwarx" "lharx" "lbarx" 5 PPC PPC 4 0


<s> static int feature_compare ( const void * v1 , const void * v2 ) { typedef struct _function_version_info { tree version_decl ; tree predicate_chain ; unsigned int dispatch_priority ; } function_version_info ; const function_version_info c1 = * ( const function_version_info * ) v1 ; const function_version_info c2 = * ( const function_version_info * ) v2 ; return ( c2 . dispatch_priority - c1 . dispatch_priority ) ; } </s>

V1 and V2 point to function versions with different priorities based on the target ISA . This function compares their priorities .


<s> static int ix86_avx_u128_mode_needed ( rtx_insn * insn ) { if ( CALL_P ( insn ) ) { rtx link ; for ( link = CALL_INSN_FUNCTION_USAGE ( insn ) ; link ; link = XEXP ( link , 1 ) ) { if ( GET_CODE ( XEXP ( link , 0 ) ) == USE ) { rtx arg = XEXP ( XEXP ( link , 0 ) , 0 ) ; if ( ix86_check_avx256_register ( arg ) ) return AVX_U128_DIRTY ; } } return AVX_U128_CLEAN ; } subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , NONCONST ) if ( ix86_check_avx256_register ( * iter ) ) return AVX_U128_DIRTY ; return AVX_U128_ANY ; } </s>

Return needed mode for entity in optimize_mode_switching pass .


<s> bool isToken ( ) const override { return Kind == Token ; } </s>


Returns assembly code to perform a DImode shift using a 64-bit global or out register on SPARC-V8+ .


"%<-fexcess-precision=16%> is not compatible with %<-mfpmath=387%>"

Set the value of FLT_EVAL_METHOD in float.h . When using only the FPU , assume that the fpcw is set to extended precision ; when using only SSE , rounding is correct ; when using both SSE and the FPU , the rounding precision is indeterminate , since either may be chosen apparently at random .


<s> bool aarch64_is_noplt_call_p ( rtx sym ) { const_tree decl = SYMBOL_REF_DECL ( sym ) ; if ( flag_pic && decl && ( ! flag_plt || lookup_attribute ( "noplt" , DECL_ATTRIBUTES ( decl ) ) ) && ! targetm . binds_local_p ( decl ) ) return true ; return false ; } </s>

Return true if calls to symbol-ref SYM should not go through plt stubs .


<s> virtual const TeeRISCSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>


<s> const MCFixup * RISCVMCExpr :: getPCRelHiFixup ( ) const { MCValue AUIPCLoc ; if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( AUIPCLoc , nullptr , nullptr ) ) return nullptr ; const MCSymbolRefExpr * AUIPCSRE = AUIPCLoc . getSymA ( ) ; if ( ! AUIPCSRE ) return nullptr ; const MCSymbol * AUIPCSymbol = & AUIPCSRE -> getSymbol ( ) ; const auto * DF = dyn_cast_or_null < MCDataFragment > ( AUIPCSymbol -> getFragment ( ) ) ; if ( ! DF ) return nullptr ; uint64_t Offset = AUIPCSymbol -> getOffset ( ) ; if ( DF -> getContents ( ) . size ( ) == Offset ) { DF = dyn_cast_or_null < MCDataFragment > ( DF -> getNextNode ( ) ) ; if ( ! DF ) return nullptr ; Offset = 0 ; } for ( const MCFixup & F : DF -> getFixups ( ) ) { if ( F . getOffset ( ) != Offset ) continue ; switch ( ( unsigned ) F . getKind ( ) ) { default : continue ; case RISCV :: fixup_riscv_got_hi20 : case RISCV :: fixup_riscv_tls_got_hi20 : case RISCV :: fixup_riscv_tls_gd_hi20 : case RISCV :: fixup_riscv_pcrel_hi20 : return & F ; } } return nullptr ; } </s>

Get the corresponding PC-relative HI fixup that a VK_RISCV_PCREL_LO points to , and optionally the fragment containing it .


<s> bool SIRegisterInfo :: requiresFrameIndexScavenging ( const MachineFunction & MF ) const { return false ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> bool function_resolver :: scalar_argument_p ( unsigned int i ) { tree type = get_argument_type ( i ) ; return ( INTEGRAL_TYPE_P ( type ) || POINTER_TYPE_P ( type ) || SCALAR_FLOAT_TYPE_P ( type ) ) ; } </s>

Return true if argument I is some form of scalar value .


<s> static void riscv_emit_epilogue_components ( sbitmap components ) { riscv_process_components ( components , false ) ; } </s>


<s> static bool find_alignment_op ( rtx_insn * insn , rtx base_reg , vec < rtx_insn * > * and_insns , vec < rtx > * and_ops ) { df_ref base_use ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; rtx and_operation = 0 ; FOR_EACH_INSN_INFO_USE ( base_use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( base_use ) , base_reg ) ) continue ; struct df_link * base_def_link = DF_REF_CHAIN ( base_use ) ; if ( ! base_def_link ) return false ; while ( base_def_link ) { if ( DF_REF_IS_ARTIFICIAL ( base_def_link -> ref ) ) return false ; rtx_insn * and_insn = DF_REF_INSN ( base_def_link -> ref ) ; and_operation = alignment_mask ( and_insn ) ; if ( ! and_operation ) return false ; and_insns -> safe_push ( and_insn ) ; and_ops -> safe_push ( and_operation ) ; base_def_link = base_def_link -> next ; } } return and_operation ; } </s>

Given INSN that 's a load or store based at BASE_REG , check if all of its feeding computations align its address on a 16-byte boundary . If so , return true and add all definition insns into AND_INSNS and their corresponding fully-expanded rtxes for the masking operations into AND_OPS .


<s>
SDValue
AArch64TargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
DL
,
SelectionDAG
&
DAG
)
const
{
CCAssignFn
*
RetCC
=
CallConv
==
CallingConv
::
WebKit_JS
RetCC_AArch64_WebKit_JS
:
RetCC_AArch64_AAPCS
;
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
realRVLocIdx
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
,
++
realRVLocIdx
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Arg
=
OutVals
[
realRVLocIdx
]
;
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
if
(
Outs
[
i
]
.
ArgVT
==
MVT
::
i1
)
{
Arg
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
DL
,
MVT
::
i1
,
Arg
)
;
Arg
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
DL
,
VA
.
getLocVT
(
)
,
Arg
)
;
}
break
;
case
CCValAssign
::
BCvt
:
Arg
=
DAG
.
getNode
(
ISD
::
BITCAST
,
DL
,
VA
.
getLocVT
(
)
,
Arg
)
;
break
;
}
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
Arg
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
AArch64ISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s>
void
PPCInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
O
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
)
{
if
(
MI
->
getOpcode
(
)
==
PPC
::
RLWINM
)
{
unsigned
char
SH
=
MI
->
getOperand
(
2
)
.
getImm
(
)
;
unsigned
char
MB
=
MI
->
getOperand
(
3
)
.
getImm
(
)
;
unsigned
char
ME
=
MI
->
getOperand
(
4
)
.
getImm
(
)
;
bool
useSubstituteMnemonic
=
false
;
if
(
SH
<=
31
&&
MB
==
0
&&
ME
==
(
31
SH
)
)
{
O
<<
"\tslwi "
;
useSubstituteMnemonic
=
true
;
}
if
(
SH
<=
31
&&
MB
==
(
32
SH
)
&&
ME
==
31
)
{
O
<<
"\tsrwi "
;
useSubstituteMnemonic
=
true
;
SH
=
32
SH
;
}
if
(
useSubstituteMnemonic
)
{
printOperand
(
MI
,
0
,
O
)
;
O
<<
", "
;
printOperand
(
MI
,
1
,
O
)
;
O
<<
", "
<<
(
unsigned
int
)
SH
;
printAnnotation
(
O
,
Annot
)
;
return
;
}
}
if
(
(
MI
->
getOpcode
(
)
==
PPC
::
OR
||
MI
->
getOpcode
(
)
==
PPC
::
OR8
)
&&
MI
->
getOperand
(
1
)
.
getReg
(
)
==
MI
->
getOperand
(
2
)
.
getReg
(
)
)
{
O
<<
"\tmr "
;
printOperand
(
MI
,
0
,
O
)
;
O
<<
", "
;
printOperand
(
MI
,
1
,
O
)
;
printAnnotation
(
O
,
Annot
)
;
return
;
}
if
(
MI
->
getOpcode
(
)
==
PPC
::
RLDICR
)
{
unsigned
char
SH
=
MI
->
getOperand
(
2
)
.
getImm
(
)
;
unsigned
char
ME
=
MI
->
getOperand
(
3
)
.
getImm
(
)
;
if
(
63
SH
==
ME
)
{
O
<<
"\tsldi "
;
printOperand
(
MI
,
0
,
O
)
;
O
<<
", "
;
printOperand
(
MI
,
1
,
O
)
;
O
<<
", "
<<
(
unsigned
int
)
SH
;
printAnnotation
(
O
,
Annot
)
;
return
;
}
}
if
(
MI
->
getOpcode
(
)
==
TargetOpcode
::
COPY_TO_REGCLASS
)
return
;
printInstruction
(
MI
,
O
)
;
printAnnotation
(
O
,
Annot
)
;
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s> static MCAsmInfo * createMCAsmInfo ( const Target & T , StringRef TT ) { Triple TheTriple ( TT ) ; switch ( TheTriple . getOS ( ) ) { case Triple :: Darwin : return new ARMMCAsmInfoDarwin ( ) ; default : return new ARMELFMCAsmInfo ( ) ; } } </s>

createMCAsmInfo - Create a MCAsmInfo implementation for the specified target triple .


<s> void rs6000_emit_eh_reg_restore ( rtx source , rtx scratch ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; rtx operands [ 2 ] ; operands [ 0 ] = source ; operands [ 1 ] = scratch ; if ( info -> lr_save_p ) { rtx frame_rtx = stack_pointer_rtx ; HOST_WIDE_INT sp_offset = 0 ; rtx tmp ; if ( frame_pointer_needed || cfun -> calls_alloca || info -> total_size > 32767 ) { tmp = gen_frame_mem ( Pmode , frame_rtx ) ; emit_move_insn ( operands [ 1 ] , tmp ) ; frame_rtx = operands [ 1 ] ; } else if ( info -> push_p ) sp_offset = info -> total_size ; tmp = plus_constant ( Pmode , frame_rtx , info -> lr_save_offset + sp_offset ) ; tmp = gen_frame_mem ( Pmode , tmp ) ; emit_move_insn ( tmp , operands [ 0 ] ) ; } else emit_move_insn ( gen_rtx_REG ( Pmode , LR_REGNO ) , operands [ 0 ] ) ; cfun -> machine -> lr_save_state = info -> lr_save_p + 1 ; } </s>

Emit instructions to restore the link register after determining where its value has been stored .


<s> rtx aarch64_reverse_mask ( enum machine_mode mode ) { rtx mask ; rtvec v = rtvec_alloc ( 16 ) ; int i , j ; int nunits = GET_MODE_NUNITS ( mode ) ; int usize = GET_MODE_UNIT_SIZE ( mode ) ; gcc_assert ( BYTES_BIG_ENDIAN ) ; gcc_assert ( AARCH64_VALID_SIMD_QREG_MODE ( mode ) ) ; for ( i = 0 ; i < nunits ; i ++ ) for ( j = 0 ; j < usize ; j ++ ) RTVEC_ELT ( v , i * usize + j ) = GEN_INT ( ( i + 1 ) * usize - 1 - j ) ; mask = gen_rtx_CONST_VECTOR ( V16QImode , v ) ; return force_reg ( V16QImode , mask ) ; } </s>

Generate a byte permute mask for a register of mode MODE , which has NUNITS units .


<s> static rtx choose_baseaddr ( HOST_WIDE_INT cfa_offset , unsigned int * align , unsigned int scratch_regno = INVALID_REGNUM ) { rtx base_reg = NULL ; HOST_WIDE_INT base_offset = 0 ; if ( align && * align ) choose_basereg ( cfa_offset , base_reg , base_offset , * align , align ) ; if ( ! base_reg ) choose_basereg ( cfa_offset , base_reg , base_offset , 0 , align ) ; gcc_assert ( base_reg != NULL ) ; rtx base_offset_rtx = GEN_INT ( base_offset ) ; if ( ! x86_64_immediate_operand ( base_offset_rtx , Pmode ) ) { gcc_assert ( scratch_regno != INVALID_REGNUM ) ; rtx scratch_reg = gen_rtx_REG ( Pmode , scratch_regno ) ; emit_move_insn ( scratch_reg , base_offset_rtx ) ; return gen_rtx_PLUS ( Pmode , base_reg , scratch_reg ) ; } return plus_constant ( Pmode , base_reg , base_offset ) ; } </s>

Return an RTX that points to CFA_OFFSET within the stack frame . The valid base registers are taken from CFUN- > MACHINE- > FS .


<s> bool VideoCore4FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { return false ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


Return an array that contains the direct target flag values and their names .


initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> Relocator :: Result abs ( Relocation & pReloc , X86_64Relocator & pParent ) { ResolveInfo * rsym = pReloc . symInfo ( ) ; Relocator :: DWord A = pReloc . target ( ) + pReloc . addend ( ) ; Relocator :: DWord S = pReloc . symValue ( ) ; Relocation * dyn_rel = pParent . getRelRelMap ( ) . lookUp ( pReloc ) ; bool has_dyn_rel = ( dyn_rel != NULL ) ; LDSection & target_sect = pReloc . targetRef ( ) . frag ( ) -> getParent ( ) -> getSection ( ) ; if ( ( llvm :: ELF :: SHF_ALLOC & target_sect . flag ( ) ) == 0x0 ) { pReloc . target ( ) = S + A ; return Relocator :: OK ; } if ( rsym -> isLocal ( ) && has_dyn_rel ) { dyn_rel -> setAddend ( S + A ) ; return Relocator :: OK ; } if ( ! rsym -> isLocal ( ) ) { if ( rsym -> reserved ( ) & X86Relocator :: ReservePLT ) { S = helper_get_PLT_address ( * rsym , pParent ) ; } if ( has_dyn_rel ) { if ( llvm :: ELF :: R_X86_64_64 == pReloc . type ( ) && helper_use_relative_reloc ( * rsym , pParent ) ) { dyn_rel -> setAddend ( S + A ) ; } else { dyn_rel -> setAddend ( A ) ; return Relocator :: OK ; } } } pReloc . target ( ) = S + A ; return Relocator :: OK ; } </s>

Compute known bits for the absolute value .


<s>
MachineBasicBlock
*
HexagonTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
case
Hexagon
::
ADJDYNALLOC
:
{
MachineFunction
*
MF
=
BB
->
getParent
(
)
;
HexagonMachineFunctionInfo
*
FuncInfo
=
MF
->
getInfo
<
HexagonMachineFunctionInfo
>
(
)
;
FuncInfo
->
addAllocaAdjustInst
(
MI
)
;
return
BB
;
}
default
:
llvm_unreachable
(
"Unexpected instr type to insert"
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .

Hexagon
Hexagon
Hexagon::ADJDYNALLOC
Hexagon
Hexagon
"Unexpected instr type to insert"


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM , bool is64Bit ) : LLVMTargetMachine ( T , TT , CPU , FS , RM , CM ) , Subtarget ( TT , CPU , FS , StackAlignmentOverride , is64Bit ) , FrameLowering ( * this , Subtarget ) , ELFWriterInfo ( is64Bit , true ) { if ( getRelocationModel ( ) == Reloc :: Static ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . is64Bit ( ) ) { Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; } else if ( Subtarget . isTargetCygMing ( ) ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . isTargetDarwin ( ) ) { if ( getRelocationModel ( ) == Reloc :: PIC_ ) Subtarget . setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; Subtarget . setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( Subtarget . isTargetELF ( ) ) { Subtarget . setPICStyle ( PICStyles :: GOT ) ; } if ( FloatABIType == FloatABI :: Default ) FloatABIType = FloatABI :: Hard ; } </s>


<s> static rtx rs6000_spe_function_arg ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type ) { int gregno = cum -> sysv_gregno ; if ( TARGET_E500_DOUBLE && ( mode == DFmode || mode == DCmode ) ) { int n_words = rs6000_arg_size ( mode , type ) ; if ( mode == DFmode ) gregno += ( 1 - gregno ) & 1 ; if ( gregno + n_words - 1 > GP_ARG_MAX_REG ) return NULL_RTX ; return spe_build_register_parallel ( mode , gregno ) ; } if ( cum -> stdarg ) { int n_words = rs6000_arg_size ( mode , type ) ; if ( n_words == 2 && ( gregno & 1 ) == 0 ) gregno += 1 ; if ( gregno + n_words - 1 <= GP_ARG_MAX_REG ) { rtx r1 , r2 ; enum machine_mode m = SImode ; r1 = gen_rtx_REG ( m , gregno ) ; r1 = gen_rtx_EXPR_LIST ( m , r1 , const0_rtx ) ; r2 = gen_rtx_REG ( m , gregno + 1 ) ; r2 = gen_rtx_EXPR_LIST ( m , r2 , GEN_INT ( 4 ) ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , r1 , r2 ) ) ; } else return NULL_RTX ; } else { if ( gregno <= GP_ARG_MAX_REG ) return gen_rtx_REG ( mode , gregno ) ; else return NULL_RTX ; } } </s>

Determine where to put a SIMD argument on the SPE .


<s>
bool
HexagonInstrInfo
::
PredicateInstruction
(
MachineInstr
&
MI
,
ArrayRef
<
MachineOperand
>
Cond
)
const
{
if
(
Cond
.
empty
(
)
||
isNewValueJump
(
Cond
[
0
]
.
getImm
(
)
)
||
isEndLoopN
(
Cond
[
0
]
.
getImm
(
)
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"\nCannot predicate:"
;
MI
.
dump
(
)
;
)
;
return
false
;
}
int
Opc
=
MI
.
getOpcode
(
)
;
assert
(
isPredicable
(
MI
)
&&
"Expected predicable instruction"
)
;
bool
invertJump
=
predOpcodeHasNot
(
Cond
)
;
MachineBasicBlock
&
B
=
*
MI
.
getParent
(
)
;
DebugLoc
DL
=
MI
.
getDebugLoc
(
)
;
unsigned
PredOpc
=
getCondOpcode
(
Opc
,
invertJump
)
;
MachineInstrBuilder
T
=
BuildMI
(
B
,
MI
,
DL
,
get
(
PredOpc
)
)
;
unsigned
NOp
=
0
,
NumOps
=
MI
.
getNumOperands
(
)
;
while
(
NOp
<
NumOps
)
{
MachineOperand
&
Op
=
MI
.
getOperand
(
NOp
)
;
if
(
!
Op
.
isReg
(
)
||
!
Op
.
isDef
(
)
||
Op
.
isImplicit
(
)
)
break
;
T
.
add
(
Op
)
;
NOp
++
;
}
unsigned
PredReg
,
PredRegPos
,
PredRegFlags
;
bool
GotPredReg
=
getPredReg
(
Cond
,
PredReg
,
PredRegPos
,
PredRegFlags
)
;
(
void
)
GotPredReg
;
assert
(
GotPredReg
)
;
T
.
addReg
(
PredReg
,
PredRegFlags
)
;
while
(
NOp
<
NumOps
)
T
.
add
(
MI
.
getOperand
(
NOp
++
)
)
;
MI
.
setDesc
(
get
(
PredOpc
)
)
;
while
(
unsigned
n
=
MI
.
getNumOperands
(
)
)
MI
.
RemoveOperand
(
n
1
)
;
for
(
unsigned
i
=
0
,
n
=
T
->
getNumOperands
(
)
;
i
<
n
;
++
i
)
MI
.
addOperand
(
T
->
getOperand
(
i
)
)
;
MachineBasicBlock
::
instr_iterator
TI
=
T
->
getIterator
(
)
;
B
.
erase
(
TI
)
;
MachineRegisterInfo
&
MRI
=
B
.
getParent
(
)
->
getRegInfo
(
)
;
MRI
.
clearKillFlags
(
PredReg
)
;
return
true
;
}
</s>

Convert the instruction into a predicated instruction .


<s>
void
AMDGPUInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
DestReg
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
!
"Not Implemented"
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s>
bool
ARMAsmBackend
::
shouldForceRelocation
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
)
{
const
MCSymbolRefExpr
*
A
=
Target
.
getSymA
(
)
;
const
MCSymbol
*
Sym
=
A
&
A
->
getSymbol
(
)
:
nullptr
;
const
unsigned
FixupKind
=
Fixup
.
getKind
(
)
;
if
(
(
unsigned
)
Fixup
.
getKind
(
)
==
ARM
::
fixup_arm_thumb_bl
)
{
assert
(
Sym
&&
"How did we resolve this?"
)
;
if
(
Sym
->
isExternal
(
)
)
return
true
;
}
if
(
Sym
&&
Sym
->
isELF
(
)
)
{
unsigned
Type
=
dyn_cast
<
MCSymbolELF
>
(
Sym
)
->
getType
(
)
;
if
(
(
Type
==
ELF
::
STT_FUNC
||
Type
==
ELF
::
STT_GNU_IFUNC
)
)
{
if
(
Asm
.
isThumbFunc
(
Sym
)
&&
(
FixupKind
==
ARM
::
fixup_arm_uncondbranch
)
)
return
true
;
if
(
!
Asm
.
isThumbFunc
(
Sym
)
&&
(
FixupKind
==
ARM
::
fixup_arm_thumb_br
||
FixupKind
==
ARM
::
fixup_arm_thumb_bl
||
FixupKind
==
ARM
::
fixup_t2_condbranch
||
FixupKind
==
ARM
::
fixup_t2_uncondbranch
)
)
return
true
;
}
}
if
(
A
&&
(
FixupKind
==
ARM
::
fixup_arm_thumb_blx
||
FixupKind
==
ARM
::
fixup_arm_blx
||
FixupKind
==
ARM
::
fixup_arm_uncondbl
||
FixupKind
==
ARM
::
fixup_arm_condbl
)
)
return
true
;
return
false
;
}
</s>

Hook to check if a relocation is needed for some target specific reason .


<s> bool ARMBaseInstrInfo :: isSchedulingBoundary ( const MachineInstr * MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( MI -> isDebugValue ( ) ) return false ; if ( MI -> isTerminator ( ) || MI -> isPosition ( ) ) return true ; MachineBasicBlock :: const_iterator I = MI ; while ( ++ I != MBB -> end ( ) && I -> isDebugValue ( ) ) ; if ( I != MBB -> end ( ) && I -> getOpcode ( ) == ARM :: t2IT ) return true ; if ( ! MI -> isCall ( ) && MI -> definesRegister ( ARM :: SP ) ) return true ; return false ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> static rtx construct_plt_address ( rtx symbol ) { rtx tmp , unspec ; gcc_assert ( GET_CODE ( symbol ) == SYMBOL_REF ) ; gcc_assert ( ix86_cmodel == CM_LARGE_PIC && ! TARGET_PECOFF ) ; gcc_assert ( Pmode == DImode ) ; tmp = gen_reg_rtx ( Pmode ) ; unspec = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , symbol ) , UNSPEC_PLTOFF ) ; emit_move_insn ( tmp , gen_rtx_CONST ( Pmode , unspec ) ) ; emit_insn ( ix86_gen_add3 ( tmp , tmp , pic_offset_table_rtx ) ) ; return tmp ; } </s>

For given symbol ( function ) construct code to compute address of it 's PLT entry in large x86-64 PIC model .


<s> void rs6000_emit_le_vsx_load ( rtx dest , rtx source , machine_mode mode ) { rtx tmp , permute_mem , permute_reg ; if ( mode == TImode || mode == V1TImode ) { mode = V2DImode ; dest = gen_lowpart ( V2DImode , dest ) ; source = adjust_address ( source , V2DImode , 0 ) ; } tmp = can_create_pseudo_p ( ) ? gen_reg_rtx_and_attrs ( dest ) : dest ; permute_mem = rs6000_gen_le_vsx_permute ( source , mode ) ; permute_reg = rs6000_gen_le_vsx_permute ( tmp , mode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , permute_mem ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , permute_reg ) ) ; } </s>

Emit a little-endian load from vector memory location SOURCE to VSX register DEST in mode MODE . The load is done with two permuting insn 's that represent an lxvd2x and xxpermdi .


<s> void AArch64TTIImpl :: getUnrollingPreferences ( Loop * L , TTI :: UnrollingPreferences & UP ) { UP . PartialOptSizeThreshold = 0 ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> BitVector SIRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AMDGPU :: INDIRECT_BASE_ADDR ) ; reserveRegisterTuples ( Reserved , AMDGPU :: EXEC ) ; reserveRegisterTuples ( Reserved , AMDGPU :: FLAT_SCR ) ; reserveRegisterTuples ( Reserved , AMDGPU :: VGPR254 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: VGPR255 ) ; if ( MF . getSubtarget < AMDGPUSubtarget > ( ) . hasSGPRInitBug ( ) ) { unsigned NumSGPRs = AMDGPU :: SGPR_32RegClass . getNumRegs ( ) ; unsigned Limit = AMDGPUSubtarget :: FIXED_SGPR_COUNT_FOR_INIT_BUG - 4 ; for ( unsigned i = Limit ; i < NumSGPRs ; ++ i ) { unsigned Reg = AMDGPU :: SGPR_32RegClass . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool RISCVTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { auto & DL = I . getModule ( ) -> getDataLayout ( ) ; switch ( Intrinsic ) { default : return false ; case Intrinsic :: riscv_masked_atomicrmw_xchg_i32 : case Intrinsic :: riscv_masked_atomicrmw_add_i32 : case Intrinsic :: riscv_masked_atomicrmw_sub_i32 : case Intrinsic :: riscv_masked_atomicrmw_nand_i32 : case Intrinsic :: riscv_masked_atomicrmw_max_i32 : case Intrinsic :: riscv_masked_atomicrmw_min_i32 : case Intrinsic :: riscv_masked_atomicrmw_umax_i32 : case Intrinsic :: riscv_masked_atomicrmw_umin_i32 : case Intrinsic :: riscv_masked_cmpxchg_i32 : Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: i32 ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . align = Align ( 4 ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; case Intrinsic :: riscv_masked_strided_load : Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . ptrVal = I . getArgOperand ( 1 ) ; Info . memVT = getValueType ( DL , I . getType ( ) -> getScalarType ( ) ) ; Info . align = Align ( DL . getTypeSizeInBits ( I . getType ( ) -> getScalarType ( ) ) / 8 ) ; Info . size = MemoryLocation :: UnknownSize ; Info . flags |= MachineMemOperand :: MOLoad ; return true ; case Intrinsic :: riscv_masked_strided_store : Info . opc = ISD :: INTRINSIC_VOID ; Info . ptrVal = I . getArgOperand ( 1 ) ; Info . memVT = getValueType ( DL , I . getArgOperand ( 0 ) -> getType ( ) -> getScalarType ( ) ) ; Info . align = Align ( DL . getTypeSizeInBits ( I . getArgOperand ( 0 ) -> getType ( ) -> getScalarType ( ) ) / 8 ) ; Info . size = MemoryLocation :: UnknownSize ; Info . flags |= MachineMemOperand :: MOStore ; return true ; } } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s>
static
void
nvptx_record_offload_symbol
(
tree
decl
)
{
fprintf
(
asm_out_file
,
"//:%s_MAP %s\n"
,
TREE_CODE
(
decl
)
==
VAR_DECL
"VAR"
:
"FUNC"
,
IDENTIFIER_POINTER
(
DECL_ASSEMBLER_NAME
(
decl
)
)
)
;
}
</s>

Record a symbol for mkoffload to enter into the mapping table .


<s> int ep_memory_operand ( rtx op , enum machine_mode mode , int unsigned_load ) { rtx addr , op0 , op1 ; int max_offset ; int mask ; if ( ! TARGET_EP ) return FALSE ; if ( GET_CODE ( op ) != MEM ) return FALSE ; max_offset = ep_memory_offset ( mode , unsigned_load ) ; mask = GET_MODE_SIZE ( mode ) - 1 ; addr = XEXP ( op , 0 ) ; if ( GET_CODE ( addr ) == CONST ) addr = XEXP ( addr , 0 ) ; switch ( GET_CODE ( addr ) ) { default : break ; case SYMBOL_REF : return SYMBOL_REF_TDA_P ( addr ) ; case REG : return REGNO ( addr ) == EP_REGNUM ; case PLUS : op0 = XEXP ( addr , 0 ) ; op1 = XEXP ( addr , 1 ) ; if ( GET_CODE ( op1 ) == CONST_INT && INTVAL ( op1 ) < max_offset && INTVAL ( op1 ) >= 0 && ( INTVAL ( op1 ) & mask ) == 0 ) { if ( GET_CODE ( op0 ) == REG && REGNO ( op0 ) == EP_REGNUM ) return TRUE ; if ( GET_CODE ( op0 ) == SYMBOL_REF && SYMBOL_REF_TDA_P ( op0 ) ) return TRUE ; } break ; } return FALSE ; } </s>

Return true if OP is a valid short EP memory reference


<s> void GCNPassConfig :: addOptimizedRegAlloc ( ) { insertPass ( & MachineSchedulerID , & SIWholeQuadModeID ) ; insertPass ( & MachineSchedulerID , & SIPreAllocateWWMRegsID ) ; if ( OptExecMaskPreRA ) insertPass ( & MachineSchedulerID , & SIOptimizeExecMaskingPreRAID ) ; if ( isPassEnabled ( EnablePreRAOptimizations ) ) insertPass ( & RenameIndependentSubregsID , & GCNPreRAOptimizationsID ) ; if ( TM -> getOptLevel ( ) > CodeGenOpt :: Less ) insertPass ( & MachineSchedulerID , & SIFormMemoryClausesID ) ; if ( OptVGPRLiveRange ) insertPass ( & LiveVariablesID , & SIOptimizeVGPRLiveRangeID ) ; insertPass ( & PHIEliminationID , & SILowerControlFlowID ) ; if ( EnableDCEInRA ) insertPass ( & DetectDeadLanesID , & DeadMachineInstructionElimID ) ; TargetPassConfig :: addOptimizedRegAlloc ( ) ; } </s>

addOptimizedRegAlloc - Add passes related to register allocation .


<s> void reset ( ) { Dist . clear ( ) ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s> rtx s390_return_addr_rtx ( int count , rtx frame ATTRIBUTE_UNUSED ) { int offset ; rtx addr ; if ( ! TARGET_BACKCHAIN && count > 0 ) return NULL_RTX ; if ( count == 0 ) { if ( TARGET_CPU_ZARCH ) return get_hard_reg_initial_val ( Pmode , RETURN_REGNUM ) ; else { cfun_frame_layout . save_return_addr_p = true ; return gen_rtx_MEM ( Pmode , return_address_pointer_rtx ) ; } } if ( TARGET_PACKED_STACK ) offset = - 2 * UNITS_PER_WORD ; else offset = RETURN_REGNUM * UNITS_PER_WORD ; addr = plus_constant ( frame , offset ) ; addr = memory_address ( Pmode , addr ) ; return gen_rtx_MEM ( Pmode , addr ) ; } </s>

Return an RTL expression representing the value of the return address for the frame COUNT steps up from the current frame . FRAME is the frame pointer of that frame .


<s> int mips_address_insns ( rtx x , machine_mode mode , bool might_split_p ) { struct mips_address_info addr ; int factor ; bool msa_p = ( ! might_split_p && MSA_SUPPORTED_MODE_P ( mode ) ) ; if ( mode != BLKmode && might_split_p ) factor = ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; else factor = 1 ; if ( mips_classify_address ( & addr , x , mode , false ) ) switch ( addr . type ) { case ADDRESS_REG : if ( msa_p ) { if ( mips_signed_immediate_p ( INTVAL ( addr . offset ) , 10 , mips_ldst_scaled_shift ( mode ) ) ) return 1 ; else return 0 ; } if ( TARGET_MIPS16 && ! mips16_unextended_reference_p ( mode , addr . reg , UINTVAL ( addr . offset ) ) ) return factor * 2 ; return factor ; case ADDRESS_LO_SUM : return msa_p ? 0 : TARGET_MIPS16 ? factor * 2 : factor ; case ADDRESS_CONST_INT : return msa_p ? 0 : factor ; case ADDRESS_SYMBOLIC : return msa_p ? 0 : factor * mips_symbol_insns ( addr . symbol_type , mode ) ; } return 0 ; } </s>

Return the number of instructions needed to load or store a value of mode MODE at X . Return 0 if X is n't valid for MODE . For mips16 code , count extended instructions as two instructions .


<s> static void bounds_check ( rtx operand , HOST_WIDE_INT low , HOST_WIDE_INT high , const char * err ) { HOST_WIDE_INT lane ; gcc_assert ( CONST_INT_P ( operand ) ) ; lane = INTVAL ( operand ) ; if ( lane < low || lane >= high ) error ( err ) ; } </s>

Ensure OPERAND lies between LOW ( inclusive ) and HIGH ( exclusive ) . Raise ERR if it does n't . FIXME : NEON bounds checks occur late in compilation , so reported source locations are bogus .


<s> void mips_expand_vec_minmax ( rtx target , rtx op0 , rtx op1 , rtx ( * cmp ) ( rtx , rtx , rtx ) , bool min_p ) { machine_mode vmode = GET_MODE ( target ) ; rtx tc , t0 , t1 , x ; tc = gen_reg_rtx ( vmode ) ; t0 = gen_reg_rtx ( vmode ) ; t1 = gen_reg_rtx ( vmode ) ; emit_insn ( cmp ( tc , op0 , op1 ) ) ; x = gen_rtx_AND ( vmode , tc , ( min_p ? op1 : op0 ) ) ; emit_insn ( gen_rtx_SET ( t0 , x ) ) ; x = gen_rtx_NOT ( vmode , tc ) ; x = gen_rtx_AND ( vmode , x , ( min_p ? op0 : op1 ) ) ; emit_insn ( gen_rtx_SET ( t1 , x ) ) ; x = gen_rtx_IOR ( vmode , t0 , t1 ) ; emit_insn ( gen_rtx_SET ( target , x ) ) ; } </s>


<s> static int mips_fpr_return_fields ( tree valtype , tree * fields ) { tree field ; int i ; if ( ! TARGET_NEWABI ) return 0 ; if ( TREE_CODE ( valtype ) != RECORD_TYPE ) return 0 ; i = 0 ; for ( field = TYPE_FIELDS ( valtype ) ; field != 0 ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( TREE_CODE ( TREE_TYPE ( field ) ) != REAL_TYPE ) return 0 ; if ( i == 2 ) return 0 ; fields [ i ++ ] = field ; } return i ; } </s>

See whether VALTYPE is a record whose fields should be returned in floating-point registers . If so , return the number of fields and list them in FIELDS ( which should have two elements ) . Return 0 otherwise . For n32 & n64 , a structure with one or two fields is returned in floating-point registers as long as every field has a floating-point type . The C++ FE used to remove zero-width bit-fields in GCC 11 and earlier . To make a proper diagnostic , this function will set HAS_CXX_ZERO_WIDTH_BF to true once a C++ zero-width bit-field shows up , and then ignore it . We had failed to ignore C++17 empty bases in GCC 7 , 8 , 9 , 10 , and 11 . This caused an ABI incompatibility between C++14 and C++17 . This is fixed now and to make a proper diagnostic , this function will set HAS_CXX17_EMPTY_BASE to true once a C++17 empty base shows up , and then ignore it . The caller should use the value of HAS_CXX17_EMPTY_BASE and/or HAS_CXX_ZERO_WIDTH_BF to emit a proper -Wpsabi inform .


<s> static bool need_to_save_reg ( unsigned int regno ) { if ( ! fixed_regs [ regno ] && ! call_used_regs [ regno ] && df_regs_ever_live_p ( regno ) ) return true ; if ( flag_pic && ( regno == PIC_OFFSET_TABLE_REGNUM || regno == TILEPRO_PIC_TEXT_LABEL_REGNUM ) && ( crtl -> uses_pic_offset_table || crtl -> saves_all_registers ) ) return true ; if ( crtl -> calls_eh_return ) { unsigned i ; for ( i = 0 ; EH_RETURN_DATA_REGNO ( i ) != INVALID_REGNUM ; i ++ ) { if ( regno == EH_RETURN_DATA_REGNO ( i ) ) return true ; } } return false ; } </s>

Return whether REGNO needs to be saved in the stack frame .


<s> TargetPassConfig * GBZ80TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new GBZ80PassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> unsigned getUnits ( ) const { return ( Slots ) ; } </s>


<s> Optional < Instruction * > AArch64TTIImpl :: instCombineIntrinsic ( InstCombiner & IC , IntrinsicInst & II ) const { Intrinsic :: ID IID = II . getIntrinsicID ( ) ; switch ( IID ) { default : break ; case Intrinsic :: aarch64_sve_convert_from_svbool : return instCombineConvertFromSVBool ( IC , II ) ; case Intrinsic :: aarch64_sve_dup : return instCombineSVEDup ( IC , II ) ; case Intrinsic :: aarch64_sve_lasta : case Intrinsic :: aarch64_sve_lastb : return instCombineSVELast ( IC , II ) ; } return None ; } </s>

Targets can implement their own combinations for target-specific intrinsics .


<s> static void tilegx_setup_incoming_varargs ( cumulative_args_t cum , const function_arg_info & arg , int * pretend_args , int no_rtl ) { CUMULATIVE_ARGS local_cum = * get_cumulative_args ( cum ) ; int first_reg ; targetm . calls . function_arg_advance ( pack_cumulative_args ( & local_cum ) , arg ) ; first_reg = local_cum ; if ( local_cum < TILEGX_NUM_ARG_REGS ) { * pretend_args = UNITS_PER_WORD * ( TILEGX_NUM_ARG_REGS - first_reg ) ; if ( ! no_rtl ) { alias_set_type set = get_varargs_alias_set ( ) ; rtx tmp = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , virtual_incoming_args_rtx , - STACK_POINTER_OFFSET - UNITS_PER_WORD * ( TILEGX_NUM_ARG_REGS - first_reg ) ) ) ; MEM_NOTRAP_P ( tmp ) = 1 ; set_mem_alias_set ( tmp , set ) ; move_block_from_reg ( first_reg , tmp , TILEGX_NUM_ARG_REGS - first_reg ) ; } } else * pretend_args = 0 ; } </s>


<s> bool MipsSEInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { MachineBasicBlock & MBB = * MI . getParent ( ) ; bool isMicroMips = Subtarget . inMicroMipsMode ( ) ; unsigned Opc ; switch ( MI . getDesc ( ) . getOpcode ( ) ) { default : return false ; case Mips :: RetRA : expandRetRA ( MBB , MI ) ; break ; case Mips :: ERet : expandERet ( MBB , MI ) ; break ; case Mips :: PseudoMFHI : Opc = isMicroMips ? Mips :: MFHI16_MM : Mips :: MFHI ; expandPseudoMFHiLo ( MBB , MI , Opc ) ; break ; case Mips :: PseudoMFLO : Opc = isMicroMips ? Mips :: MFLO16_MM : Mips :: MFLO ; expandPseudoMFHiLo ( MBB , MI , Opc ) ; break ; case Mips :: PseudoMFHI64 : expandPseudoMFHiLo ( MBB , MI , Mips :: MFHI64 ) ; break ; case Mips :: PseudoMFLO64 : expandPseudoMFHiLo ( MBB , MI , Mips :: MFLO64 ) ; break ; case Mips :: PseudoMTLOHI : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO , Mips :: MTHI , false ) ; break ; case Mips :: PseudoMTLOHI64 : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO64 , Mips :: MTHI64 , false ) ; break ; case Mips :: PseudoMTLOHI_DSP : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO_DSP , Mips :: MTHI_DSP , true ) ; break ; case Mips :: PseudoCVT_S_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_D32_W : Opc = isMicroMips ? Mips :: CVT_D32_W_MM : Mips :: CVT_D32_W ; expandCvtFPInt ( MBB , MI , Opc , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_S_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_L , Mips :: DMTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_W : Opc = isMicroMips ? Mips :: CVT_D64_W_MM : Mips :: CVT_D64_W ; expandCvtFPInt ( MBB , MI , Opc , Mips :: MTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_L , Mips :: DMTC1 , true ) ; break ; case Mips :: BuildPairF64 : expandBuildPairF64 ( MBB , MI , isMicroMips , false ) ; break ; case Mips :: BuildPairF64_64 : expandBuildPairF64 ( MBB , MI , isMicroMips , true ) ; break ; case Mips :: ExtractElementF64 : expandExtractElementF64 ( MBB , MI , isMicroMips , false ) ; break ; case Mips :: ExtractElementF64_64 : expandExtractElementF64 ( MBB , MI , isMicroMips , true ) ; break ; case Mips :: MIPSeh_return32 : case Mips :: MIPSeh_return64 : expandEhReturn ( MBB , MI ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> static rtx tilepro_legitimize_tls_address ( rtx addr ) { rtx ret ; gcc_assert ( can_create_pseudo_p ( ) ) ; if ( GET_CODE ( addr ) == SYMBOL_REF ) switch ( SYMBOL_REF_TLS_MODEL ( addr ) ) { case TLS_MODEL_GLOBAL_DYNAMIC : case TLS_MODEL_LOCAL_DYNAMIC : { rtx r0 , temp1 , temp2 , temp3 , got ; rtx_insn * last ; ret = gen_reg_rtx ( Pmode ) ; r0 = gen_rtx_REG ( Pmode , 0 ) ; temp1 = gen_reg_rtx ( Pmode ) ; temp2 = gen_reg_rtx ( Pmode ) ; temp3 = gen_reg_rtx ( Pmode ) ; got = tilepro_tls_got ( ) ; emit_insn ( gen_tls_gd_addhi ( temp1 , got , addr ) ) ; emit_insn ( gen_tls_gd_addlo ( temp2 , temp1 , addr ) ) ; emit_move_insn ( r0 , temp2 ) ; emit_insn ( gen_tls_gd_call ( addr ) ) ; emit_move_insn ( temp3 , r0 ) ; last = emit_insn ( gen_tls_gd_add ( ret , temp3 , addr ) ) ; set_unique_reg_note ( last , REG_EQUAL , copy_rtx ( addr ) ) ; break ; } case TLS_MODEL_INITIAL_EXEC : { rtx temp1 , temp2 , temp3 , got ; rtx_insn * last ; ret = gen_reg_rtx ( Pmode ) ; temp1 = gen_reg_rtx ( Pmode ) ; temp2 = gen_reg_rtx ( Pmode ) ; temp3 = gen_reg_rtx ( Pmode ) ; got = tilepro_tls_got ( ) ; emit_insn ( gen_tls_ie_addhi ( temp1 , got , addr ) ) ; emit_insn ( gen_tls_ie_addlo ( temp2 , temp1 , addr ) ) ; emit_insn ( gen_tls_ie_load ( temp3 , temp2 , addr ) ) ; last = emit_move_insn ( ret , gen_rtx_PLUS ( Pmode , gen_rtx_REG ( Pmode , THREAD_POINTER_REGNUM ) , temp3 ) ) ; set_unique_reg_note ( last , REG_EQUAL , copy_rtx ( addr ) ) ; break ; } case TLS_MODEL_LOCAL_EXEC : { rtx temp1 ; rtx_insn * last ; ret = gen_reg_rtx ( Pmode ) ; temp1 = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_tls_le_addhi ( temp1 , gen_rtx_REG ( Pmode , THREAD_POINTER_REGNUM ) , addr ) ) ; last = emit_insn ( gen_tls_le_addlo ( ret , temp1 , addr ) ) ; set_unique_reg_note ( last , REG_EQUAL , copy_rtx ( addr ) ) ; break ; } default : gcc_unreachable ( ) ; } else if ( GET_CODE ( addr ) == CONST ) { rtx base , offset ; gcc_assert ( GET_CODE ( XEXP ( addr , 0 ) ) == PLUS ) ; base = tilepro_legitimize_tls_address ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) ; offset = XEXP ( XEXP ( addr , 0 ) , 1 ) ; base = force_operand ( base , NULL_RTX ) ; ret = force_reg ( Pmode , gen_rtx_PLUS ( Pmode , base , offset ) ) ; } else gcc_unreachable ( ) ; return ret ; } </s>

ADDR contains a thread-local SYMBOL_REF . Generate code to compute this ( thread-local ) address .


<s> void NVPTXTargetStreamer :: outputDwarfFileDirectives ( ) { for ( const std :: string & S : DwarfFiles ) getStreamer ( ) . emitRawText ( S ) ; DwarfFiles . clear ( ) ; } </s>

Outputs the list of the DWARF '.file ' directives to the streamer .


"internal error: instruction without _e64 suffix "

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> void emitVERegisterScratch ( unsigned reg ) override { } </s>

Emit `` .register < reg > , # scratch '' .


<s> bool X86TargetLowering :: shouldSinkOperands ( Instruction * I , SmallVectorImpl < Use * > & Ops ) const { using namespace llvm :: PatternMatch ; FixedVectorType * VTy = dyn_cast < FixedVectorType > ( I -> getType ( ) ) ; if ( ! VTy ) return false ; if ( I -> getOpcode ( ) == Instruction :: Mul && VTy -> getElementType ( ) -> isIntegerTy ( 64 ) ) { for ( auto & Op : I -> operands ( ) ) { if ( any_of ( Ops , [ & ] ( Use * U ) { return U -> get ( ) == Op ; } ) ) continue ; if ( Subtarget . hasSSE41 ( ) && match ( Op . get ( ) , m_AShr ( m_Shl ( m_Value ( ) , m_SpecificInt ( 32 ) ) , m_SpecificInt ( 32 ) ) ) ) { Ops . push_back ( & cast < Instruction > ( Op ) -> getOperandUse ( 0 ) ) ; Ops . push_back ( & Op ) ; } else if ( Subtarget . hasSSE2 ( ) && match ( Op . get ( ) , m_And ( m_Value ( ) , m_SpecificInt ( UINT64_C ( 0xffffffff ) ) ) ) ) { Ops . push_back ( & Op ) ; } } return ! Ops . empty ( ) ; } int ShiftAmountOpNum = - 1 ; if ( I -> isShift ( ) ) ShiftAmountOpNum = 1 ; else if ( auto * II = dyn_cast < IntrinsicInst > ( I ) ) { if ( II -> getIntrinsicID ( ) == Intrinsic :: fshl || II -> getIntrinsicID ( ) == Intrinsic :: fshr ) ShiftAmountOpNum = 2 ; } if ( ShiftAmountOpNum == - 1 ) return false ; auto * Shuf = dyn_cast < ShuffleVectorInst > ( I -> getOperand ( ShiftAmountOpNum ) ) ; if ( Shuf && getSplatIndex ( Shuf -> getShuffleMask ( ) ) >= 0 && isVectorShiftByScalarCheap ( I -> getType ( ) ) ) { Ops . push_back ( & I -> getOperandUse ( ShiftAmountOpNum ) ) ; return true ; } return false ; } </s>

Return true if sinking I 's operands to the same basic block as I is profitable , e.g .


<s> bool AArch64MIPeepholeOpt :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; TII = static_cast < const AArch64InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MRI = & MF . getRegInfo ( ) ; if ( ! MRI -> isSSA ( ) ) return false ; bool Changed = false ; SmallSetVector < MachineInstr * , 8 > ToBeRemoved ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) { switch ( MI . getOpcode ( ) ) { default : break ; case AArch64 :: ANDWrr : Changed = visitAND < uint32_t > ( MI , ToBeRemoved ) ; break ; case AArch64 :: ANDXrr : Changed = visitAND < uint64_t > ( MI , ToBeRemoved ) ; break ; case AArch64 :: ORRWrs : Changed = visitORR ( MI , ToBeRemoved ) ; } } } for ( MachineInstr * MI : ToBeRemoved ) MI -> eraseFromParent ( ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool free_insn_info ( const rtx & t ATTRIBUTE_UNUSED , insn_info_list_t * v , void * arg ATTRIBUTE_UNUSED ) { while ( v -> length ( ) > 0 ) delete v -> pop ( ) ; return true ; } </s>

Callback to free all tag_insn_info objects .


"CFGuard check mechanism only used on 32-bit X86"

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
bool
RISCVInstrInfo
::
areMemAccessesTriviallyDisjoint
(
const
MachineInstr
&
MIa
,
const
MachineInstr
&
MIb
)
const
{
assert
(
MIa
.
mayLoadOrStore
(
)
&&
"MIa must be a load or store."
)
;
assert
(
MIb
.
mayLoadOrStore
(
)
&&
"MIb must be a load or store."
)
;
if
(
MIa
.
hasUnmodeledSideEffects
(
)
||
MIb
.
hasUnmodeledSideEffects
(
)
||
MIa
.
hasOrderedMemoryRef
(
)
||
MIb
.
hasOrderedMemoryRef
(
)
)
return
false
;
const
TargetRegisterInfo
*
TRI
=
STI
.
getRegisterInfo
(
)
;
const
MachineOperand
*
BaseOpA
=
nullptr
,
*
BaseOpB
=
nullptr
;
int64_t
OffsetA
=
0
,
OffsetB
=
0
;
unsigned
int
WidthA
=
0
,
WidthB
=
0
;
if
(
getMemOperandWithOffsetWidth
(
MIa
,
BaseOpA
,
OffsetA
,
WidthA
,
TRI
)
&&
getMemOperandWithOffsetWidth
(
MIb
,
BaseOpB
,
OffsetB
,
WidthB
,
TRI
)
)
{
if
(
BaseOpA
->
isIdenticalTo
(
*
BaseOpB
)
)
{
int
LowOffset
=
std
::
min
(
OffsetA
,
OffsetB
)
;
int
HighOffset
=
std
::
max
(
OffsetA
,
OffsetB
)
;
int
LowWidth
=
(
LowOffset
==
OffsetA
)
WidthA
:
WidthB
;
if
(
LowOffset
+
LowWidth
<=
HighOffset
)
return
true
;
}
}
return
false
;
}
</s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> unsigned int ix86_get_callcvt ( const_tree type ) { unsigned int ret = 0 ; bool is_stdarg ; tree attrs ; if ( TARGET_64BIT ) return IX86_CALLCVT_CDECL ; attrs = TYPE_ATTRIBUTES ( type ) ; if ( attrs != NULL_TREE ) { if ( lookup_attribute ( "cdecl" , attrs ) ) ret |= IX86_CALLCVT_CDECL ; else if ( lookup_attribute ( "stdcall" , attrs ) ) ret |= IX86_CALLCVT_STDCALL ; else if ( lookup_attribute ( "fastcall" , attrs ) ) ret |= IX86_CALLCVT_FASTCALL ; else if ( lookup_attribute ( "thiscall" , attrs ) ) ret |= IX86_CALLCVT_THISCALL ; if ( ( ret & ( IX86_CALLCVT_THISCALL | IX86_CALLCVT_FASTCALL ) ) == 0 ) { if ( lookup_attribute ( "regparm" , attrs ) ) ret |= IX86_CALLCVT_REGPARM ; if ( lookup_attribute ( "sseregparm" , attrs ) ) ret |= IX86_CALLCVT_SSEREGPARM ; } if ( IX86_BASE_CALLCVT ( ret ) != 0 ) return ret ; } is_stdarg = stdarg_p ( type ) ; if ( TARGET_RTD && ! is_stdarg ) return IX86_CALLCVT_STDCALL | ret ; if ( ret != 0 || is_stdarg || TREE_CODE ( type ) != METHOD_TYPE || ix86_function_type_abi ( type ) != MS_ABI ) return IX86_CALLCVT_CDECL | ret ; return IX86_CALLCVT_THISCALL ; } </s>

This function determines from TYPE the calling-convention .


"stack re-alignment, but LLVM couldn't handle it "

"(probably because it has a dynamic alloca)."

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> void LEGAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( OutStreamer , TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> rtx cris_return_addr_rtx ( int count , rtx frameaddr ATTRIBUTE_UNUSED ) { cfun -> machine -> needs_return_address_on_stack = 1 ; return count == 0 ? gen_rtx_MEM ( Pmode , plus_constant ( Pmode , virtual_incoming_args_rtx , - 4 ) ) : NULL_RTX ; } </s>

The RETURN_ADDR_RTX worker . We mark that the return address is used , either by EH or __builtin_return_address , for use by the function prologue and epilogue . FIXME : This is n't optimal ; we just use the mark in the prologue and epilogue to say that the return address is to be stored in the stack frame . We could return SRP for leaf-functions and use the initial-value machinery .


<s> void MipsSEFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; const MipsSEInstrInfo & TII = * static_cast < const MipsSEInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; const MipsRegisterInfo & RegInfo = * static_cast < const MipsRegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; unsigned SP = STI . isABI_N64 ( ) ? Mips :: SP_64 : Mips :: SP ; unsigned FP = STI . isABI_N64 ( ) ? Mips :: FP_64 : Mips :: FP ; unsigned ZERO = STI . isABI_N64 ( ) ? Mips :: ZERO_64 : Mips :: ZERO ; unsigned ADDu = STI . isABI_N64 ( ) ? Mips :: DADDu : Mips :: ADDu ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( ADDu ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( MipsFI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = 0 ; J < 4 ; ++ J ) { TII . loadRegFromStackSlot ( MBB , I , ehDataReg ( J ) , MipsFI -> getEhDataRegFI ( J ) , RC , & RegInfo ) ; } } uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize , MBB , MBBI ) ; } </s>


<s> void arc_init_expanders ( void ) { init_machine_status = arc_init_machine_status ; } </s>

Implements INIT_EXPANDERS . We just set up to call the above function .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> static void restore_non_core_regs ( phase1_vrs * vrs ) { if ( ( vrs -> demand_save_flags & DEMAND_SAVE_VFP ) == 0 ) __gnu_Unwind_Restore_VFP ( & vrs -> vfp ) ; } </s>

Restore coprocessor state after phase1 unwinding .


"Not expecting modifiers with immediates"

Commutes the operands in the given instruction by changing the operands order and/or changing the instruction 's opcode and/or the immediate value operand .


<s> bool HexagonInstrInfo :: analyzeCompare ( const MachineInstr * MI , unsigned & SrcReg , unsigned & SrcReg2 , int & Mask , int & Value ) const { unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case Hexagon :: C2_cmpeqp : case Hexagon :: C2_cmpeqi : case Hexagon :: C2_cmpeq : case Hexagon :: C2_cmpgtp : case Hexagon :: C2_cmpgtup : case Hexagon :: C2_cmpgtui : case Hexagon :: C2_cmpgtu : case Hexagon :: C2_cmpgti : case Hexagon :: C2_cmpgt : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; Mask = ~ 0 ; break ; case Hexagon :: CMPbEQri_V4 : case Hexagon :: CMPbEQrr_sbsb_V4 : case Hexagon :: CMPbEQrr_ubub_V4 : case Hexagon :: CMPbGTUri_V4 : case Hexagon :: CMPbGTUrr_V4 : case Hexagon :: CMPbGTrr_V4 : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; Mask = 0xFF ; break ; case Hexagon :: CMPhEQri_V4 : case Hexagon :: CMPhEQrr_shl_V4 : case Hexagon :: CMPhEQrr_xor_V4 : case Hexagon :: CMPhGTUri_V4 : case Hexagon :: CMPhGTUrr_V4 : case Hexagon :: CMPhGTrr_shl_V4 : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; Mask = 0xFFFF ; break ; } switch ( Opc ) { case Hexagon :: C2_cmpeqp : case Hexagon :: C2_cmpeq : case Hexagon :: C2_cmpgtp : case Hexagon :: C2_cmpgtup : case Hexagon :: C2_cmpgtu : case Hexagon :: C2_cmpgt : case Hexagon :: CMPbEQrr_sbsb_V4 : case Hexagon :: CMPbEQrr_ubub_V4 : case Hexagon :: CMPbGTUrr_V4 : case Hexagon :: CMPbGTrr_V4 : case Hexagon :: CMPhEQrr_shl_V4 : case Hexagon :: CMPhEQrr_xor_V4 : case Hexagon :: CMPhGTUrr_V4 : case Hexagon :: CMPhGTrr_shl_V4 : SrcReg2 = MI -> getOperand ( 2 ) . getReg ( ) ; return true ; case Hexagon :: C2_cmpeqi : case Hexagon :: C2_cmpgtui : case Hexagon :: C2_cmpgti : case Hexagon :: CMPbEQri_V4 : case Hexagon :: CMPbGTUri_V4 : case Hexagon :: CMPhEQri_V4 : case Hexagon :: CMPhGTUri_V4 : SrcReg2 = 0 ; Value = MI -> getOperand ( 2 ) . getImm ( ) ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> bool AVRShiftExpand :: runOnFunction ( Function & F ) { SmallVector < BinaryOperator * , 1 > ShiftInsts ; auto & Ctx = F . getContext ( ) ; for ( Instruction & I : instructions ( F ) ) { if ( ! I . isShift ( ) ) continue ; if ( I . getType ( ) != Type :: getInt32Ty ( Ctx ) ) continue ; if ( isa < ConstantInt > ( I . getOperand ( 1 ) ) ) continue ; ShiftInsts . push_back ( cast < BinaryOperator > ( & I ) ) ; } for ( auto * I : ShiftInsts ) { expand ( I ) ; } return ShiftInsts . size ( ) > 0 ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s>
void
WebAssemblyInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
MCRegister
DestReg
,
MCRegister
SrcReg
,
bool
KillSrc
)
const
{
auto
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
const
TargetRegisterClass
*
RC
=
Register
::
isVirtualRegister
(
DestReg
)
MRI
.
getRegClass
(
DestReg
)
:
MRI
.
getTargetRegisterInfo
(
)
->
getMinimalPhysRegClass
(
DestReg
)
;
unsigned
CopyOpcode
;
if
(
RC
==
&
WebAssembly
::
I32RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_I32
;
else
if
(
RC
==
&
WebAssembly
::
I64RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_I64
;
else
if
(
RC
==
&
WebAssembly
::
F32RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_F32
;
else
if
(
RC
==
&
WebAssembly
::
F64RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_F64
;
else
if
(
RC
==
&
WebAssembly
::
V128RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_V128
;
else
if
(
RC
==
&
WebAssembly
::
EXNREFRegClass
)
CopyOpcode
=
WebAssembly
::
COPY_EXNREF
;
else
llvm_unreachable
(
"Unexpected register class"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
CopyOpcode
)
,
DestReg
)
.
addReg
(
SrcReg
,
KillSrc
RegState
::
Kill
:
0
)
;
}
</s>