<s>
void
AlphaRegisterInfo
::
emitPrologue
(
MachineFunction
&
MF
)
const
{
MachineBasicBlock
&
MBB
=
MF
.
front
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
DebugLoc
dl
=
(
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
(
)
)
;
bool
FP
=
hasFP
(
MF
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
LDAHg
)
,
Alpha
::
R29
)
.
addGlobalAddress
(
const_cast
<
Function
*
>
(
MF
.
getFunction
(
)
)
)
.
addReg
(
Alpha
::
R27
)
.
addImm
(
++
curgpdist
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
LDAg
)
,
Alpha
::
R29
)
.
addGlobalAddress
(
const_cast
<
Function
*
>
(
MF
.
getFunction
(
)
)
)
.
addReg
(
Alpha
::
R29
)
.
addImm
(
curgpdist
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
ALTENT
)
)
.
addGlobalAddress
(
const_cast
<
Function
*
>
(
MF
.
getFunction
(
)
)
)
;
long
NumBytes
=
MFI
->
getStackSize
(
)
;
if
(
FP
)
NumBytes
+=
8
;
if
(
NumBytes
==
0
)
return
;
unsigned
Align
=
MF
.
getTarget
(
)
.
getFrameInfo
(
)
->
getStackAlignment
(
)
;
NumBytes
=
(
NumBytes
+
Align
1
)
/
Align
*
Align
;
MFI
->
setStackSize
(
NumBytes
)
;
NumBytes
=
NumBytes
;
if
(
NumBytes
>=
IMM_LOW
)
{
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
LDA
)
,
Alpha
::
R30
)
.
addImm
(
NumBytes
)
.
addReg
(
Alpha
::
R30
)
;
}
else
if
(
getUpper16
(
NumBytes
)
>=
IMM_LOW
)
{
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
LDAH
)
,
Alpha
::
R30
)
.
addImm
(
getUpper16
(
NumBytes
)
)
.
addReg
(
Alpha
::
R30
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
LDA
)
,
Alpha
::
R30
)
.
addImm
(
getLower16
(
NumBytes
)
)
.
addReg
(
Alpha
::
R30
)
;
}
else
{
report_fatal_error
(
"Too big a stack frame at "
+
Twine
(
NumBytes
)
)
;
}
if
(
FP
)
{
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
STQ
)
)
.
addReg
(
Alpha
::
R15
)
.
addImm
(
0
)
.
addReg
(
Alpha
::
R30
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Alpha
::
BISr
)
,
Alpha
::
R15
)
.
addReg
(
Alpha
::
R30
)
.
addReg
(
Alpha
::
R30
)
;
}
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> unsigned AMDGPURegisterBankInfo :: copyCost ( const RegisterBank & A , const RegisterBank & B , unsigned Size ) const { return RegisterBankInfo :: copyCost ( A , B , Size ) ; } </s>

Get the cost of a copy from B to A , or put differently , get the cost of A = COPY B .


<s>
TargetLowering
::
AtomicExpansionKind
X86TargetLowering
::
shouldExpandAtomicRMWInIR
(
AtomicRMWInst
*
AI
)
const
{
unsigned
NativeWidth
=
Subtarget
.
is64Bit
(
)
64
:
32
;
Type
*
MemType
=
AI
->
getType
(
)
;
if
(
MemType
->
getPrimitiveSizeInBits
(
)
>
NativeWidth
)
{
return
needsCmpXchgNb
(
MemType
)
AtomicExpansionKind
::
CmpXChg
:
AtomicExpansionKind
::
;
}
AtomicRMWInst
::
BinOp
Op
=
AI
->
getOperation
(
)
;
switch
(
Op
)
{
default
:
llvm_unreachable
(
"Unknown atomic operation"
)
;
case
AtomicRMWInst
::
Xchg
:
case
AtomicRMWInst
::
Add
:
case
AtomicRMWInst
::
Sub
:
return
AtomicExpansionKind
::
;
case
AtomicRMWInst
::
Or
:
case
AtomicRMWInst
::
And
:
case
AtomicRMWInst
::
Xor
:
return
!
AI
->
use_empty
(
)
AtomicExpansionKind
::
CmpXChg
:
AtomicExpansionKind
::
;
case
AtomicRMWInst
::
Nand
:
case
AtomicRMWInst
::
Max
:
case
AtomicRMWInst
::
Min
:
case
AtomicRMWInst
::
UMax
:
case
AtomicRMWInst
::
UMin
:
return
AtomicExpansionKind
::
CmpXChg
;
}
}
</s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> void print_operand_address ( FILE * file , register rtx addr ) { rtx reg ; rtx offset ; if ( GET_CODE ( addr ) == AND && GET_CODE ( XEXP ( addr , 1 ) ) == CONST_INT && INTVAL ( XEXP ( addr , 1 ) ) == - 16 ) addr = XEXP ( addr , 0 ) ; switch ( GET_CODE ( addr ) ) { case REG : fprintf ( file , "0(%s)" , reg_names [ REGNO ( addr ) ] ) ; break ; case PLUS : reg = XEXP ( addr , 0 ) ; offset = XEXP ( addr , 1 ) ; if ( GET_CODE ( offset ) == REG ) { fprintf ( file , "%s,%s" , reg_names [ REGNO ( reg ) ] , reg_names [ REGNO ( offset ) ] ) ; } else if ( GET_CODE ( offset ) == CONST_INT ) { fprintf ( file , HOST_WIDE_INT_PRINT_DEC "(%s)" , INTVAL ( offset ) , reg_names [ REGNO ( reg ) ] ) ; } else abort ( ) ; break ; case CONST : case LABEL_REF : case SYMBOL_REF : case CONST_INT : output_addr_const ( file , addr ) ; break ; default : debug_rtx ( addr ) ; abort ( ) ; } } </s>

Print the operand address represented by the rtx addr


<s> int same_cmp_following_p ( rtx i1 ) { rtx_insn * i2 , * i3 ; i2 = next_nonnote_insn ( i1 ) ; if ( i2 == NULL ) return 0 ; i3 = next_nonnote_insn ( i2 ) ; if ( i3 == NULL ) return 0 ; return ( INSN_P ( i3 ) && rtx_equal_p ( PATTERN ( i1 ) , PATTERN ( i3 ) ) && any_condjump_p ( i2 ) && onlyjump_p ( i2 ) ) ; } </s>

Return nonzero if we have the same comparison insn as I1 two insns after I1 . I1 is assumed to be a comparison insn .


<s> unsigned X86TargetLowering :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { unsigned FPDiff = RegInfo -> hasFP ( MF ) ? 1 : 0 ; switch ( RC -> getID ( ) ) { default : return 0 ; case X86 :: GR32RegClassID : return 4 - FPDiff ; case X86 :: GR64RegClassID : return 8 - FPDiff ; case X86 :: VR128RegClassID : return Subtarget -> is64Bit ( ) ? 10 : 4 ; case X86 :: VR64RegClassID : return 4 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s>
bool
RISCVInstrInfo
::
verifyInstruction
(
const
MachineInstr
&
MI
,
StringRef
&
ErrInfo
)
const
{
const
MCInstrInfo
*
MCII
=
STI
.
getInstrInfo
(
)
;
MCInstrDesc
const
&
Desc
=
MCII
->
get
(
MI
.
getOpcode
(
)
)
;
for
(
auto
&
OI
:
enumerate
(
Desc
.
operands
(
)
)
)
{
unsigned
OpType
=
OI
.
value
(
)
.
OperandType
;
if
(
OpType
>=
RISCVOp
::
OPERAND_FIRST_RISCV_IMM
&&
OpType
<=
RISCVOp
::
OPERAND_LAST_RISCV_IMM
)
{
const
MachineOperand
&
MO
=
MI
.
getOperand
(
OI
.
index
(
)
)
;
if
(
MO
.
isImm
(
)
)
{
int64_t
Imm
=
MO
.
getImm
(
)
;
bool
Ok
;
switch
(
OpType
)
{
default
:
llvm_unreachable
(
"Unexpected operand type"
)
;
case
RISCVOp
::
OPERAND_UIMM2
:
Ok
=
isUInt
<
2
>
(
Imm
)
;
break
;
case
RISCVOp
::
OPERAND_UIMM3
:
Ok
=
isUInt
<
3
>
(
Imm
)
;
break
;
case
RISCVOp
::
OPERAND_UIMM4
:
Ok
=
isUInt
<
4
>
(
Imm
)
;
break
;
case
RISCVOp
::
OPERAND_UIMM5
:
Ok
=
isUInt
<
5
>
(
Imm
)
;
break
;
case
RISCVOp
::
OPERAND_UIMM7
:
Ok
=
isUInt
<
7
>
(
Imm
)
;
break
;
case
RISCVOp
::
OPERAND_UIMM12
:
Ok
=
isUInt
<
12
>
(
Imm
)
;
break
;
case
RISCVOp
::
OPERAND_SIMM12
:
Ok
=
isInt
<
12
>
(
Imm
)
;
break
;
case
RISCVOp
::
OPERAND_UIMM20
:
Ok
=
isUInt
<
20
>
(
Imm
)
;
break
;
case
RISCVOp
::
OPERAND_UIMMLOG2XLEN
:
if
(
STI
.
getTargetTriple
(
)
.
isArch64Bit
(
)
)
Ok
=
isUInt
<
6
>
(
Imm
)
;
else
Ok
=
isUInt
<
5
>
(
Imm
)
;
break
;
case
RISCVOp
::
OPERAND_RVKRNUM
:
Ok
=
Imm
>=
0
&&
Imm
<=
10
;
break
;
}
if
(
!
Ok
)
{
ErrInfo
=
"Invalid immediate"
;
return
false
;
}
}
}
}
return
true
;
}
</s>

Perform target-specific instruction verification .


<s> void M680x0FrameLowering :: emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , int64_t NumBytes , bool InEpilogue ) const { bool isSub = NumBytes < 0 ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; uint64_t Chunk = ( 1LL << 31 ) - 1 ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { if ( Offset > Chunk ) { unsigned Reg = 0 ; if ( isSub && ! isRegLiveIn ( MBB , M680x0 :: D0 ) ) Reg = ( unsigned ) ( M680x0 :: D0 ) ; else Reg = findDeadCallerSavedReg ( MBB , MBBI , TRI ) ; if ( Reg ) { unsigned Opc = M680x0 :: MOV32ri ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , Reg ) . addImm ( Offset ) ; Opc = isSub ? getSUBrrOpcode ( ) : getADDrrOpcode ( ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addReg ( Reg ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; Offset = 0 ; continue ; } } uint64_t ThisVal = std :: min ( Offset , Chunk ) ; MachineInstrBuilder MI = BuildStackAdjustment ( MBB , MBBI , DL , isSub ? - ThisVal : ThisVal , InEpilogue ) ; if ( isSub ) MI . setMIFlag ( MachineInstr :: FrameSetup ) ; else MI . setMIFlag ( MachineInstr :: FrameDestroy ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s>
static
unsigned
getDepth
(
const
SmallVectorImpl
<
const
MachineBasicBlock
*
>
&
Stack
,
const
MachineBasicBlock
*
MBB
)
{
unsigned
Depth
=
0
;
for
(
auto
X
:
reverse
(
Stack
)
)
{
if
(
X
==
MBB
)
break
;
++
Depth
;
}
assert
(
Depth
<
Stack
.
size
(
)
&&
"Branch destination should be in scope"
)
;
return
Depth
;
}
</s>

The depth , in the dependence graph , for a node .

WebAssembly
0
"Branch destination should be in scope"


<s> static bool mcore_legitimate_address_p ( machine_mode mode , rtx x , bool strict_p , addr_space_t as ) { gcc_assert ( ADDR_SPACE_GENERIC_P ( as ) ) ; if ( mcore_base_register_rtx_p ( x , strict_p ) ) return true ; else if ( GET_CODE ( x ) == PLUS || GET_CODE ( x ) == LO_SUM ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; if ( mcore_base_register_rtx_p ( xop0 , strict_p ) && mcore_legitimate_index_p ( mode , xop1 ) ) return true ; if ( mcore_base_register_rtx_p ( xop1 , strict_p ) && mcore_legitimate_index_p ( mode , xop0 ) ) return true ; } return false ; } </s>

Worker function for TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P . Allow REG REG + disp


<s> unsigned AVRAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned ExpectedKind ) { AVROperand & Op = static_cast < AVROperand & > ( AsmOp ) ; MatchClassKind Expected = static_cast < MatchClassKind > ( ExpectedKind ) ; if ( Op . isImm ( ) ) { if ( MCConstantExpr const * Const = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ) { int64_t RegNum = Const -> getValue ( ) ; std :: ostringstream RegName ; RegName << "r" << RegNum ; RegNum = MatchRegisterName ( RegName . str ( ) ) ; if ( RegNum != AVR :: NoRegister ) { Op . makeReg ( RegNum ) ; if ( validateOperandClass ( Op , Expected ) == Match_Success ) { return Match_Success ; } } } } if ( Op . isReg ( ) ) { if ( isSubclass ( Expected , MCK_DREGS ) ) { unsigned correspondingDREG = toDREG ( Op . getReg ( ) ) ; if ( correspondingDREG != AVR :: NoRegister ) { Op . makeReg ( correspondingDREG ) ; return validateOperandClass ( Op , Expected ) ; } } } return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .

AVR AVR AVR AVR "r" AVR::NoRegister AVR::NoRegister


<s> TargetLowering :: ConstraintWeight DLXTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & Info , const char * Constraint ) const { ConstraintWeight Weight = CW_Invalid ; return Weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> const MCPhysReg * XtensaRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return 0 ; } </s>


<s>
void
MINA32AsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
adjustFixupValue
(
Fixup
,
Target
,
Value
,
&
Asm
.
getContext
(
)
)
;
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
auto
NumBits
=
Info
.
TargetSize
+
Info
.
TargetOffset
;
auto
NumBytes
=
(
NumBits
/
8
)
+
(
(
NumBits
%
8
)
==
0
0
:
1
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
<
NumBytes
;
++
i
)
{
uint8_t
mask
=
(
(
Value
>>
(
i
*
8
)
)
&
0xFF
)
;
Data
[
Offset
+
i
]
|=
mask
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static rtx arc_legitimize_pic_address ( rtx addr ) { if ( ! flag_pic ) return addr ; switch ( GET_CODE ( addr ) ) { case UNSPEC : switch ( XINT ( addr , 1 ) ) { case ARC_UNSPEC_GOT : case ARC_UNSPEC_GOTOFFPC : addr = XVECEXP ( addr , 0 , 0 ) ; break ; default : return addr ; } case SYMBOL_REF : if ( SYMBOL_REF_TLS_MODEL ( addr ) ) return addr ; if ( ! arc_symbol_binds_local_p ( addr ) ) return gen_const_mem ( Pmode , arc_unspec_offset ( addr , ARC_UNSPEC_GOT ) ) ; case LABEL_REF : return arc_unspec_offset ( addr , ARC_UNSPEC_GOTOFFPC ) ; default : break ; } return addr ; } </s>

Legitimize a pic address reference in ORIG . The return value is the legitimated address . If OLDX is non-zero , it is the target to assign the address to first .


<s> static bool pru_legitimate_address_p ( machine_mode mode , rtx operand , bool strict_p ) { switch ( GET_CODE ( operand ) ) { case SYMBOL_REF : case LABEL_REF : case CONST : case CONST_WIDE_INT : return false ; case CONST_INT : return ctable_addr_operand ( operand , VOIDmode ) ; case REG : return pru_regno_ok_for_base_p ( REGNO ( operand ) , strict_p ) ; case PLUS : { rtx op0 = XEXP ( operand , 0 ) ; rtx op1 = XEXP ( operand , 1 ) ; return pru_valid_addr_expr_p ( mode , op0 , op1 , strict_p ) ; } default : break ; } return false ; } </s>


<s> static bool s390_pragma_target_parse ( tree args , tree pop_target ) { tree prev_tree = build_target_option_node ( & global_options , & global_options_set ) ; tree cur_tree ; if ( ! args ) cur_tree = pop_target ; else { cur_tree = s390_valid_target_attribute_tree ( args , & global_options , & global_options_set , true ) ; if ( ! cur_tree || cur_tree == error_mark_node ) { cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( prev_tree ) ) ; return false ; } } target_option_current_node = cur_tree ; s390_activate_target_options ( target_option_current_node ) ; { struct cl_target_option * prev_opt ; struct cl_target_option * cur_opt ; prev_opt = TREE_TARGET_OPTION ( prev_tree ) ; cur_opt = TREE_TARGET_OPTION ( cur_tree ) ; cpp_options * cpp_opts = cpp_get_options ( parse_in ) ; unsigned char saved_warn_unused_macros = cpp_opts -> warn_unused_macros ; cpp_opts -> warn_unused_macros = 0 ; s390_cpu_cpp_builtins_internal ( parse_in , cur_opt , prev_opt ) ; cpp_opts -> warn_unused_macros = saved_warn_unused_macros ; } return true ; } </s>

Hook to validate the current # pragma GCC target and set the state , and update the macros based on what was changed . If ARGS is NULL , then POP_TARGET is used to reset the options .


<s> int following_call ( rtx insn ) { if ( ! TARGET_JUMP_IN_DELAY ) return 0 ; insn = PREV_INSN ( insn ) ; while ( insn && GET_CODE ( insn ) == NOTE ) insn = PREV_INSN ( insn ) ; if ( insn && ( ( GET_CODE ( insn ) == CALL_INSN && get_attr_type ( insn ) != TYPE_DYNCALL ) || ( GET_CODE ( insn ) == INSN && GET_CODE ( PATTERN ( insn ) ) != SEQUENCE && GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER && get_attr_type ( insn ) == TYPE_MILLI ) ) ) return 1 ; return 0 ; } </s>

Return nonzero if INSN ( a jump insn ) immediately follows a call to a named function . This is used to avoid filling the delay slot of the jump since it can usually be eliminated by modifying RP in the delay slot of the call .


<s> bool Z80TargetLowering :: isNarrowingProfitable ( EVT VT1 , EVT VT2 ) const { return ! ( VT1 == MVT :: i24 && VT2 == MVT :: i16 ) ; } </s>

Return true if it 's profitable to narrow operations of type SrcVT to DestVT .


runOnMachineFunction - Emit the function body .

NVPTX NVPTX NVPTX::VRFrame NVPTX::VRFrame


"density %d%%, cost %d exceeds threshold, penalizing "

Test for likely overcommitment of vector hardware resources . If a loop iteration is relatively large , and too large a percentage of instructions in the loop are vectorized , the cost model may not adequately reflect delays from unavailable vector resources . Penalize the loop body cost for this case .


"********** MI Converging Scheduling VLIW "

"** VLIWMachineScheduler::schedule picking next node\n"

Schedule - This is called back from ScheduleDAGInstrs : :Run ( ) when it 's time to do some work .


"256-bit vector operations only available in AVX2"

Change the opcode of MI to execute in Domain .


<s> bool RISCVRegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , Register Reg , int & FrameIdx ) const { const auto * RVFI = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; if ( ! RVFI -> useSaveRestoreLibCalls ( MF ) ) return false ; const auto * FII = llvm :: find_if ( FixedCSRFIMap , [ & ] ( auto P ) { return P . first == Reg ; } ) ; if ( FII == std :: end ( FixedCSRFIMap ) ) return false ; FrameIdx = FII -> second ; return true ; } </s>

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register .


<s> void GCNPassConfig :: addPreLegalizeMachineIR ( ) { bool IsOptNone = getOptLevel ( ) == CodeGenOpt :: None ; addPass ( createAMDGPUPreLegalizeCombiner ( IsOptNone ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before legalization .


<s> bool cris_simple_epilogue ( void ) { unsigned int regno ; unsigned int reglimit = STACK_POINTER_REGNUM ; bool got_really_used = false ; if ( ! reload_completed || frame_pointer_needed || get_frame_size ( ) != 0 || current_function_pretend_args_size || current_function_args_size || current_function_outgoing_args_size || current_function_calls_eh_return || ! TARGET_PROLOGUE_EPILOGUE ) return false ; if ( current_function_uses_pic_offset_table ) { push_topmost_sequence ( ) ; got_really_used = reg_used_between_p ( pic_offset_table_rtx , get_insns ( ) , NULL_RTX ) ; pop_topmost_sequence ( ) ; } for ( regno = 0 ; regno < reglimit ; regno ++ ) if ( cris_reg_saved_in_regsave_area ( regno , got_really_used ) ) return false ; return true ; } </s>

Return ! = 0 if the return sequence for the current function is short , like `` ret '' or `` jump [ sp+ ] '' . Prior to reloading , we ca n't tell how many registers must be saved , so return 0 then .


<s> bool prefersVectorizedAddressing ( ) { return false ; } </s>

Return true if target does n't mind addresses in vectors .


"Only Linux target is expected to contain LOAD_STACK_GUARD"

"Invalid D-Form Pseudo-ops on non-P9 target."

This function is called for all pseudo instructions that remain after register allocation .


This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s>
bool
M68kInstrInfo
::
ExpandMOVEM
(
MachineInstrBuilder
&
MIB
,
const
MCInstrDesc
&
Desc
,
bool
IsRM
)
const
{
int
Reg
=
0
,
Offset
=
0
,
Base
=
0
;
auto
XR32
=
RI
.
getRegClass
(
M68k
::
XR32RegClassID
)
;
auto
DL
=
MIB
->
getDebugLoc
(
)
;
auto
MI
=
MIB
.
getInstr
(
)
;
auto
&
MBB
=
*
MIB
->
getParent
(
)
;
if
(
IsRM
)
{
Reg
=
MIB
->
getOperand
(
0
)
.
getReg
(
)
;
Offset
=
MIB
->
getOperand
(
1
)
.
getImm
(
)
;
Base
=
MIB
->
getOperand
(
2
)
.
getReg
(
)
;
}
else
{
Offset
=
MIB
->
getOperand
(
0
)
.
getImm
(
)
;
Base
=
MIB
->
getOperand
(
1
)
.
getReg
(
)
;
Reg
=
MIB
->
getOperand
(
2
)
.
getReg
(
)
;
}
if
(
!
XR32
->
contains
(
Reg
)
)
{
Reg
=
RI
.
getMatchingMegaReg
(
Reg
,
XR32
)
;
assert
(
Reg
&&
"Has not meaningful MEGA register"
)
;
}
unsigned
Mask
=
1
<<
RI
.
getSpillRegisterOrder
(
Reg
)
;
if
(
IsRM
)
{
BuildMI
(
MBB
,
MI
,
DL
,
Desc
)
.
addImm
(
Mask
)
.
addImm
(
Offset
)
.
addReg
(
Base
)
.
addReg
(
Reg
,
RegState
::
ImplicitDefine
)
.
copyImplicitOps
(
*
MIB
)
;
}
else
{
BuildMI
(
MBB
,
MI
,
DL
,
Desc
)
.
addImm
(
Offset
)
.
addReg
(
Base
)
.
addImm
(
Mask
)
.
addReg
(
Reg
,
RegState
::
Implicit
)
.
copyImplicitOps
(
*
MIB
)
;
}
MIB
->
eraseFromParent
(
)
;
return
true
;
}
</s>

Expand all MOVEM pseudos into real MOVEMs .


<s> bool AMDGPUAlwaysInline :: runOnModule ( Module & M ) { std :: vector < GlobalAlias * > AliasesToRemove ; SmallPtrSet < Function * , 8 > FuncsToAlwaysInline ; SmallPtrSet < Function * , 8 > FuncsToNoInline ; for ( GlobalAlias & A : M . aliases ( ) ) { if ( Function * F = dyn_cast < Function > ( A . getAliasee ( ) ) ) { A . replaceAllUsesWith ( F ) ; AliasesToRemove . push_back ( & A ) ; } } if ( GlobalOpt ) { for ( GlobalAlias * A : AliasesToRemove ) { A -> eraseFromParent ( ) ; } } for ( GlobalVariable & GV : M . globals ( ) ) { unsigned AS = GV . getAddressSpace ( ) ; if ( AS != AMDGPUAS :: LOCAL_ADDRESS && AS != AMDGPUAS :: REGION_ADDRESS ) continue ; recursivelyVisitUsers ( GV , FuncsToAlwaysInline ) ; } if ( ! AMDGPUTargetMachine :: EnableFunctionCalls || StressCalls ) { auto IncompatAttr = StressCalls ? Attribute :: AlwaysInline : Attribute :: NoInline ; for ( Function & F : M ) { if ( ! F . isDeclaration ( ) && ! F . use_empty ( ) && ! F . hasFnAttribute ( IncompatAttr ) ) { if ( StressCalls ) { if ( ! FuncsToAlwaysInline . count ( & F ) ) FuncsToNoInline . insert ( & F ) ; } else FuncsToAlwaysInline . insert ( & F ) ; } } } for ( Function * F : FuncsToAlwaysInline ) F -> addFnAttr ( Attribute :: AlwaysInline ) ; for ( Function * F : FuncsToNoInline ) F -> addFnAttr ( Attribute :: NoInline ) ; return ! FuncsToAlwaysInline . empty ( ) || ! FuncsToNoInline . empty ( ) ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> static tree rs6000_builtin_vectorized_libmass ( combined_fn fn , tree type_out , tree type_in ) { char name [ 32 ] ; const char * suffix = NULL ; tree fntype , new_fndecl , bdecl = NULL_TREE ; int n_args = 1 ; const char * bname ; machine_mode el_mode , in_mode ; int n , in_n ; if ( ! flag_unsafe_math_optimizations || ! TARGET_VSX ) return NULL_TREE ; el_mode = TYPE_MODE ( TREE_TYPE ( type_out ) ) ; n = TYPE_VECTOR_SUBPARTS ( type_out ) ; in_mode = TYPE_MODE ( TREE_TYPE ( type_in ) ) ; in_n = TYPE_VECTOR_SUBPARTS ( type_in ) ; if ( el_mode != in_mode || n != in_n ) return NULL_TREE ; switch ( fn ) { CASE_CFN_ATAN2 : CASE_CFN_HYPOT : CASE_CFN_POW : n_args = 2 ; gcc_fallthrough ( ) ; CASE_CFN_ACOS : CASE_CFN_ACOSH : CASE_CFN_ASIN : CASE_CFN_ASINH : CASE_CFN_ATAN : CASE_CFN_ATANH : CASE_CFN_CBRT : CASE_CFN_COS : CASE_CFN_COSH : CASE_CFN_ERF : CASE_CFN_ERFC : CASE_CFN_EXP2 : CASE_CFN_EXP : CASE_CFN_EXPM1 : CASE_CFN_LGAMMA : CASE_CFN_LOG10 : CASE_CFN_LOG1P : CASE_CFN_LOG2 : CASE_CFN_LOG : CASE_CFN_SIN : CASE_CFN_SINH : CASE_CFN_SQRT : CASE_CFN_TAN : CASE_CFN_TANH : if ( el_mode == DFmode && n == 2 ) { bdecl = mathfn_built_in ( double_type_node , fn ) ; suffix = "d2" ; } else if ( el_mode == SFmode && n == 4 ) { bdecl = mathfn_built_in ( float_type_node , fn ) ; suffix = "4" ; } else return NULL_TREE ; if ( ! bdecl ) return NULL_TREE ; break ; default : return NULL_TREE ; } gcc_assert ( suffix != NULL ) ; bname = IDENTIFIER_POINTER ( DECL_NAME ( bdecl ) ) ; if ( ! bname ) return NULL_TREE ; strcpy ( name , bname + sizeof ( "__builtin_" ) - 1 ) ; strcat ( name , suffix ) ; if ( n_args == 1 ) fntype = build_function_type_list ( type_out , type_in , NULL ) ; else if ( n_args == 2 ) fntype = build_function_type_list ( type_out , type_in , type_in , NULL ) ; else gcc_unreachable ( ) ; new_fndecl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , fntype ) ; TREE_PUBLIC ( new_fndecl ) = 1 ; DECL_EXTERNAL ( new_fndecl ) = 1 ; DECL_IS_NOVOPS ( new_fndecl ) = 1 ; TREE_READONLY ( new_fndecl ) = 1 ; return new_fndecl ; } </s>

Handler for the Mathematical Acceleration Subsystem ( mass ) interface to a library with vectorized intrinsics .


<s> static bool nios2_function_value_regno_p ( const unsigned int regno ) { return regno == FIRST_RETVAL_REGNO ; } </s>


<s> bool ix86_expand_strlen ( rtx out , rtx src , rtx eoschar , rtx align ) { if ( TARGET_UNROLL_STRLEN && TARGET_INLINE_ALL_STRINGOPS && eoschar == const0_rtx && optimize > 1 ) { rtx addr = force_reg ( Pmode , XEXP ( src , 0 ) ) ; emit_move_insn ( out , addr ) ; ix86_expand_strlensi_unroll_1 ( out , src , align ) ; emit_insn ( gen_sub2_insn ( out , addr ) ) ; return true ; } else return false ; } </s>


<s> int use_return_insn ( int iscond , rtx sibling ) { int regno ; unsigned int func_type ; unsigned long saved_int_regs ; unsigned HOST_WIDE_INT stack_adjust ; arm_stack_offsets * offsets ; if ( ! reload_completed ) return 0 ; func_type = arm_current_func_type ( ) ; if ( func_type & ( ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN ) ) return 0 ; if ( IS_INTERRUPT ( func_type ) && ( frame_pointer_needed || TARGET_THUMB ) ) return 0 ; if ( TARGET_LDRD && current_tune -> prefer_ldrd_strd && ! optimize_function_for_size_p ( cfun ) ) return 0 ; offsets = arm_get_frame_offsets ( ) ; stack_adjust = offsets -> outgoing_args - offsets -> saved_regs ; if ( crtl -> args . pretend_args_size || cfun -> machine -> uses_anonymous_args || crtl -> calls_eh_return || cfun -> calls_alloca || ! ( stack_adjust == 0 || ( TARGET_APCS_FRAME && frame_pointer_needed && stack_adjust == 4 ) ) || ( ! ( TARGET_APCS_FRAME && frame_pointer_needed ) && arm_compute_static_chain_stack_bytes ( ) != 0 ) ) return 0 ; saved_int_regs = offsets -> saved_regs_mask ; if ( stack_adjust == 4 && ! arm_arch5t && TARGET_ARM ) { if ( ! call_used_or_fixed_reg_p ( 3 ) ) return 0 ; if ( arm_size_return_regs ( ) >= ( 4 * UNITS_PER_WORD ) ) return 0 ; if ( sibling ) { gcc_assert ( CALL_P ( sibling ) ) ; if ( find_regno_fusage ( sibling , USE , 3 ) ) return 0 ; } if ( saved_int_regs & 0x7 ) return 0 ; } if ( TARGET_INTERWORK && saved_int_regs != 0 && ! IS_INTERRUPT ( func_type ) ) return 0 ; if ( iscond && arm_tune_strongarm ) { if ( saved_int_regs != 0 && saved_int_regs != ( 1 << LR_REGNUM ) ) return 0 ; if ( flag_pic && arm_pic_register != INVALID_REGNUM && df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) ) return 0 ; } if ( IS_CMSE_ENTRY ( func_type ) && ( saved_int_regs || TARGET_HAVE_FPCXT_CMSE ) ) return 0 ; if ( saved_int_regs && ! ( saved_int_regs & ( 1 << LR_REGNUM ) ) ) return 0 ; if ( TARGET_VFP_BASE ) for ( regno = FIRST_VFP_REGNUM ; regno <= LAST_VFP_REGNUM ; regno ++ ) if ( reg_needs_saving_p ( regno ) ) return 0 ; if ( TARGET_REALLY_IWMMXT ) for ( regno = FIRST_IWMMXT_REGNUM ; regno <= LAST_IWMMXT_REGNUM ; regno ++ ) if ( reg_needs_saving_p ( regno ) ) return 0 ; return 1 ; } </s>

Return true if this function 's epilogue can be output as RTL .


<s>
void
SIInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
DestReg
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
SIMachineFunctionInfo
*
MFI
=
MF
->
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MachineFrameInfo
&
FrameInfo
=
MF
->
getFrameInfo
(
)
;
const
DebugLoc
&
DL
=
MBB
.
findDebugLoc
(
MI
)
;
unsigned
Align
=
FrameInfo
.
getObjectAlignment
(
FrameIndex
)
;
unsigned
Size
=
FrameInfo
.
getObjectSize
(
FrameIndex
)
;
unsigned
SpillSize
=
TRI
->
getSpillSize
(
*
RC
)
;
MachinePointerInfo
PtrInfo
=
MachinePointerInfo
::
getFixedStack
(
*
MF
,
FrameIndex
)
;
MachineMemOperand
*
MMO
=
MF
->
getMachineMemOperand
(
PtrInfo
,
MachineMemOperand
::
MOLoad
,
Size
,
Align
)
;
if
(
RI
.
isSGPRClass
(
RC
)
)
{
MFI
->
setHasSpilledSGPRs
(
)
;
const
MCInstrDesc
&
OpDesc
=
get
(
getSGPRSpillRestoreOpcode
(
SpillSize
)
)
;
if
(
TargetRegisterInfo
::
isVirtualRegister
(
DestReg
)
&&
SpillSize
==
4
)
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
MRI
.
constrainRegClass
(
DestReg
,
&
AMDGPU
::
SReg_32_XM0RegClass
)
;
}
FrameInfo
.
setStackID
(
FrameIndex
,
SIStackID
::
SGPR_SPILL
)
;
MachineInstrBuilder
Spill
=
BuildMI
(
MBB
,
MI
,
DL
,
OpDesc
,
DestReg
)
.
addFrameIndex
(
FrameIndex
)
.
addMemOperand
(
MMO
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
,
RegState
::
Implicit
)
.
addReg
(
MFI
->
getFrameOffsetReg
(
)
,
RegState
::
Implicit
)
;
if
(
ST
.
hasScalarStores
(
)
)
{
Spill
.
addReg
(
AMDGPU
::
M0
,
RegState
::
ImplicitDefine
|
RegState
::
Dead
)
;
}
return
;
}
assert
(
RI
.
hasVGPRs
(
RC
)
&&
"Only VGPR spilling expected"
)
;
unsigned
Opcode
=
getVGPRSpillRestoreOpcode
(
SpillSize
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opcode
)
,
DestReg
)
.
addFrameIndex
(
FrameIndex
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
)
.
addReg
(
MFI
->
getFrameOffsetReg
(
)
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


"selector must be an integer constant in the range 0..%wi"

Return the integer constant in ARG . Constrain it to be in the range of the subparts of VEC_TYPE ; issue an error if not .


<s>
MachineBasicBlock
*
MipsTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
const
TargetInstrInfo
*
TII
=
getTargetMachine
(
)
.
getInstrInfo
(
)
;
bool
isFPCmp
=
false
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
assert
(
false
&&
"Unexpected instr type to insert"
)
;
case
Mips
::
Select_FCC
:
case
Mips
::
Select_FCC_S32
:
case
Mips
::
Select_FCC_D32
:
isFPCmp
=
true
;
case
Mips
::
Select_CC
:
case
Mips
::
Select_CC_S32
:
case
Mips
::
Select_CC_D32
:
{
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
It
=
BB
;
++
It
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
sinkMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
if
(
isFPCmp
)
{
Mips
::
CondCode
CC
=
(
Mips
::
CondCode
)
MI
->
getOperand
(
4
)
.
getImm
(
)
;
unsigned
Opc
=
FPBranchCodeToOpc
(
GetFPBranchCodeFromCond
(
CC
)
)
;
BuildMI
(
BB
,
dl
,
TII
->
get
(
Opc
)
)
.
addMBB
(
sinkMBB
)
;
}
else
BuildMI
(
BB
,
dl
,
TII
->
get
(
Mips
::
BNE
)
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addReg
(
Mips
::
ZERO
)
.
addMBB
(
sinkMBB
)
;
F
->
insert
(
It
,
copy0MBB
)
;
F
->
insert
(
It
,
sinkMBB
)
;
for
(
MachineBasicBlock
::
succ_iterator
i
=
BB
->
succ_begin
(
)
,
e
=
BB
->
succ_end
(
)
;
i
!=
e
;
++
i
)
sinkMBB
->
addSuccessor
(
*
i
)
;
while
(
!
BB
->
succ_empty
(
)
)
BB
->
removeSuccessor
(
BB
->
succ_begin
(
)
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
sinkMBB
;
BuildMI
(
BB
,
dl
,
TII
->
get
(
Mips
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
3
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
F
->
DeleteMachineInstr
(
MI
)
;
return
BB
;
}
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s>
const
uint32_t
*
DCPU16RegisterInfo
::
getCallPreservedMask
(
CallingConv
::
ID
CallConv
)
const
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
CSR_DCPU16_RegMask
;
}
}
</s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void XCoreInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) && ! I -> isDebugValue ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ; BuildMI ( MBB , I , DL , get ( XCore :: LDWFI ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) . addMemOperand ( MMO ) ; } </s>


<s> bool SPUTargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { typedef llvm :: FunctionPass * ( * BuilderFunc ) ( const char * ) ; BuilderFunc schedulerCreator = ( BuilderFunc ) ( intptr_t ) sys :: DynamicLibrary :: SearchForAddressOfSymbol ( "createTCESchedulerPass" ) ; if ( schedulerCreator != NULL ) PM . add ( schedulerCreator ( "cellspu" ) ) ; PM . add ( createSPUNopFillerPass ( * this ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

CellSPU SPU "createTCESchedulerPass" "cellspu" SPU


<s> bool SIRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & Fn ) const { const SIMachineFunctionInfo * Info = Fn . getInfo < SIMachineFunctionInfo > ( ) ; if ( Info -> isEntryFunction ( ) ) { const MachineFrameInfo & MFI = Fn . getFrameInfo ( ) ; return MFI . hasStackObjects ( ) || MFI . hasCalls ( ) ; } return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> void GCNHazardRecognizer :: EmitInstruction ( MachineInstr * MI ) { CurrCycleInstr = MI ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & OS ) { if ( CommentStream ) HasCustomInstComment = EmitAnyX86InstComments ( MI , * CommentStream , MII ) ; printInstFlags ( MI , OS , STI ) ; if ( MI -> getOpcode ( ) == X86 :: CALLpcrel32 && ( STI . getFeatureBits ( ) [ X86 :: Is64Bit ] ) ) { OS << "\tcallq\t" ; printPCRelImm ( MI , Address , 0 , OS ) ; } else if ( MI -> getOpcode ( ) == X86 :: DATA16_PREFIX && STI . getFeatureBits ( ) [ X86 :: Is16Bit ] ) { OS << "\tdata32" ; } else if ( ! printAliasInstr ( MI , Address , OS ) && ! printVecCompareInstr ( MI , OS ) ) printInstruction ( MI , Address , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool TVMInstrInfo :: isPredicated ( const MachineInstr & MI ) const { return MI . getOpcode ( ) == TVM :: THROWIF || MI . getOpcode ( ) == TVM :: THROWIFNOT ; } </s>

Returns true if the instruction is already predicated .


<s>
StringRef
AMDGPUAsmPrinter
::
getPassName
(
)
const
{
return
"AMDGPU Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
static
bool
aarch64_validate_mtune
(
const
char
*
str
,
const
struct
processor
*
*
res
)
{
enum
aarch64_parse_opt_result
parse_res
=
aarch64_parse_tune
(
str
,
res
)
;
if
(
parse_res
==
AARCH64_PARSE_OK
)
return
true
;
switch
(
parse_res
)
{
case
AARCH64_PARSE_MISSING_ARG
:
error
(
"missing cpu name in %<-mtune=%s%>"
,
str
)
;
break
;
case
AARCH64_PARSE_INVALID_ARG
:
error
(
"unknown value %qs for %<-mtune%>"
,
str
)
;
aarch64_print_hint_for_core
(
str
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
return
false
;
}
</s>

Validate a command-line -mtune option . Parse the cpu specified in STR and throw errors if appropriate . Put the result , if it is valid , in RES . Return whether the option is valid .

aarch64
"missing cpu name in %<-mtune=%s%>"
"unknown value %qs for %<-mtune%>"


<s>
SDValue
AMDGPUTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
Op
->
print
(
errs
(
)
,
&
DAG
)
;
llvm_unreachable
(
"Custom lowering code for this"
"instruction is not implemented yet!"
)
;
break
;
case
ISD
::
SIGN_EXTEND_INREG
:
return
LowerSIGN_EXTEND_INREG
(
Op
,
DAG
)
;
case
ISD
::
CONCAT_VECTORS
:
return
LowerCONCAT_VECTORS
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_SUBVECTOR
:
return
LowerEXTRACT_SUBVECTOR
(
Op
,
DAG
)
;
case
ISD
::
UDIVREM
:
return
LowerUDIVREM
(
Op
,
DAG
)
;
case
ISD
::
SDIVREM
:
return
LowerSDIVREM
(
Op
,
DAG
)
;
case
ISD
::
FREM
:
return
LowerFREM
(
Op
,
DAG
)
;
case
ISD
::
FCEIL
:
return
LowerFCEIL
(
Op
,
DAG
)
;
case
ISD
::
FTRUNC
:
return
LowerFTRUNC
(
Op
,
DAG
)
;
case
ISD
::
FRINT
:
return
LowerFRINT
(
Op
,
DAG
)
;
case
ISD
::
FNEARBYINT
:
return
LowerFNEARBYINT
(
Op
,
DAG
)
;
case
ISD
::
FROUND
:
return
LowerFROUND
(
Op
,
DAG
)
;
case
ISD
::
FFLOOR
:
return
LowerFFLOOR
(
Op
,
DAG
)
;
case
ISD
::
FLOG
:
return
LowerFLOG
(
Op
,
DAG
,
1
/
AMDGPU_LOG2E_F
)
;
case
ISD
::
FLOG10
:
return
LowerFLOG
(
Op
,
DAG
,
AMDGPU_LN2_F
/
AMDGPU_LN10_F
)
;
case
ISD
::
FEXP
:
return
lowerFEXP
(
Op
,
DAG
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerSINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
UINT_TO_FP
:
return
LowerUINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_FP16
:
return
LowerFP_TO_FP16
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_SINT
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_UINT
(
Op
,
DAG
)
;
case
ISD
::
CTTZ
:
case
ISD
::
CTTZ_ZERO_UNDEF
:
case
ISD
::
CTLZ
:
case
ISD
::
CTLZ_ZERO_UNDEF
:
return
LowerCTLZ_CTTZ
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
}
return
Op
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool rs6000_builtin_is_supported ( enum rs6000_gen_builtins fncode ) { switch ( rs6000_builtin_info [ ( size_t ) fncode ] . enable ) { case ENB_ALWAYS : return true ; case ENB_P5 : return TARGET_POPCNTB ; case ENB_P6 : return TARGET_CMPB ; case ENB_P6_64 : return TARGET_CMPB && TARGET_POWERPC64 ; case ENB_P7 : return TARGET_POPCNTD ; case ENB_P7_64 : return TARGET_POPCNTD && TARGET_POWERPC64 ; case ENB_P8 : return TARGET_DIRECT_MOVE ; case ENB_P8V : return TARGET_P8_VECTOR ; case ENB_P9 : return TARGET_MODULO ; case ENB_P9_64 : return TARGET_MODULO && TARGET_POWERPC64 ; case ENB_P9V : return TARGET_P9_VECTOR ; case ENB_P10 : return TARGET_POWER10 ; case ENB_P10_64 : return TARGET_POWER10 && TARGET_POWERPC64 ; case ENB_ALTIVEC : return TARGET_ALTIVEC ; case ENB_VSX : return TARGET_VSX ; case ENB_CELL : return TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL ; case ENB_IEEE128_HW : return TARGET_FLOAT128_HW ; case ENB_DFP : return TARGET_DFP ; case ENB_CRYPTO : return TARGET_CRYPTO ; case ENB_HTM : return TARGET_HTM ; case ENB_MMA : return TARGET_MMA ; default : gcc_unreachable ( ) ; } gcc_unreachable ( ) ; } </s>

Check whether a builtin function is supported in this target configuration .


"Should be handled target independently"


<s>
void
arm_declare_function_name
(
FILE
*
stream
,
const
char
*
name
,
tree
decl
)
{
fprintf
(
stream
,
"\t.syntax unified\n"
)
;
if
(
TARGET_THUMB
)
{
if
(
is_called_in_ARM_mode
(
decl
)
||
(
TARGET_THUMB1
&&
!
TARGET_THUMB1_ONLY
&&
cfun
->
is_thunk
)
)
fprintf
(
stream
,
"\t.code 32\n"
)
;
else
if
(
TARGET_THUMB1
)
fprintf
(
stream
,
"\t.code\t16\n\t.thumb_func\n"
)
;
else
fprintf
(
stream
,
"\t.thumb\n\t.thumb_func\n"
)
;
}
else
fprintf
(
stream
,
"\t.arm\n"
)
;
asm_fprintf
(
asm_out_file
,
"\t.fpu %s\n"
,
TARGET_SOFT_FLOAT
"softvfp"
:
TARGET_FPU_NAME
)
;
if
(
TARGET_POKE_FUNCTION_NAME
)
arm_poke_function_name
(
stream
,
(
const
char
*
)
name
)
;
}
</s>

Implement ASM_DECLARE_FUNCTION_NAME . Output the ISA features used by the function fndecl .


<s> unsigned getCallInstrCost ( Function * F , Type * RetTy , ArrayRef < Type * > Tys ) { return 1 ; } </s>

Compute a cost of the given call instruction .


<s> bool epiphany_uninterruptible_p ( tree t ) { tree attrs ; if ( t ) { attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( t ) ) ; if ( lookup_attribute ( "disinterrupt" , attrs ) ) return true ; } return false ; } </s>

T is a function declaration or the MEM_EXPR of a MEM passed to a call expander . Return true iff the type of T has the uninterruptible attribute . If T is NULL , return false .


<s> bool ARMCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs ) const { auto & TLI = * getTLI < ARMTargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb1Only ( ) ) return false ; if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; auto DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasByValOrInAllocaAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , 8 > SplitArgInfos ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArgInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArgInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArgInfo , SplitArgInfos , MF ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgInfos , ArgHandler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s>
void
AMDGPUAsmPrinter
::
emitEndOfAsmFile
(
Module
&
M
)
{
if
(
!
IsTargetStreamerInitialized
)
initTargetStreamer
(
M
)
;
if
(
!
getTargetStreamer
(
)
)
return
;
if
(
TM
.
getTargetTriple
(
)
.
getOS
(
)
!=
Triple
::
AMDHSA
||
isHsaAbiVersion2
(
getGlobalSTI
(
)
)
)
getTargetStreamer
(
)
->
EmitISAVersion
(
)
;
if
(
TM
.
getTargetTriple
(
)
.
getOS
(
)
==
Triple
::
AMDHSA
)
{
HSAMetadataStream
->
end
(
)
;
bool
Success
=
HSAMetadataStream
->
emitTo
(
*
getTargetStreamer
(
)
)
;
(
void
)
Success
;
assert
(
Success
&&
"Malformed HSA Metadata"
)
;
}
}
</s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> static bool riscv_pass_by_reference ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { HOST_WIDE_INT size = type ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ; struct riscv_arg_info info ; CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( cum != NULL ) { riscv_get_arg_info ( & info , cum , mode , type , named , false ) ; if ( info . num_fprs ) return false ; } return ! IN_RANGE ( size , 0 , 2 * UNITS_PER_WORD ) ; } </s>


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , DebugLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { if ( ! Subtarget -> isAAPCS_ABI ( ) || Subtarget -> isTargetDarwin ( ) ) return SDValue ( ) ; const ARMTargetLowering & TLI = * static_cast < const ARMTargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Type * IntPtrTy = TLI . getTargetData ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( MVT :: i32 ) ) Src = DAG . getNode ( ISD :: TRUNCATE , dl , MVT :: i32 , Src ) ; else Src = DAG . getNode ( ISD :: ZERO_EXTEND , dl , MVT :: i32 , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , 0 , TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , false , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } </s>

Emit target-specific code that performs a memset .


<s> const RegisterBankInfo :: InstructionMapping & MipsRegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const RegisterBankInfo :: InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; switch ( Opc ) { case G_TRUNC : case G_ADD : case G_SUB : case G_MUL : case G_LOAD : case G_STORE : case G_ZEXTLOAD : case G_SEXTLOAD : case G_GEP : case G_AND : case G_OR : case G_XOR : case G_SHL : case G_ASHR : case G_LSHR : case G_SDIV : case G_UDIV : case G_SREM : case G_UREM : OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; break ; case G_CONSTANT : case G_FRAME_INDEX : case G_GLOBAL_VALUE : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr } ) ; break ; case G_ICMP : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] } ) ; break ; case G_SELECT : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] } ) ; break ; default : return getInvalidInstructionMapping ( ) ; } return getInstructionMapping ( DefaultMappingID , 1 , OperandsMapping , NumOperands ) ; } </s>

Get the mapping of the different operands of MI on the register bank .

Mips Mips Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx 1


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool PPCPassConfig :: addPreEmitPass ( ) { PM . add ( createPPCBranchSelectionPass ( ) ) ; return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> virtual const VideoCore4Subtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> std :: pair < unsigned , unsigned > PPCInstrInfo :: decomposeMachineOperandsTargetFlags ( unsigned TF ) const { const unsigned Mask = PPCII :: MO_ACCESS_MASK ; return std :: make_pair ( TF & Mask , TF & ~ Mask ) ; } </s>

Decompose the machine operand 's target flags into two values - the direct target flag value and any of bit flags that are applied .


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { unsigned Idx = IsLittleEndian ? i : 3 - i ; Data [ Offset + Idx ] |= uint8_t ( ( Value >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
void
SystemZInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
DestReg
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
unsigned
Opc
=
0
;
if
(
RC
==
&
SystemZ
::
GR32RegClass
||
RC
==
&
SystemZ
::
ADDR32RegClass
)
Opc
=
SystemZ
::
MOV32rm
;
else
if
(
RC
==
&
SystemZ
::
GR64RegClass
||
RC
==
&
SystemZ
::
ADDR64RegClass
)
{
Opc
=
SystemZ
::
MOV64rm
;
}
else
if
(
RC
==
&
SystemZ
::
FP32RegClass
)
{
Opc
=
SystemZ
::
FMOV32rm
;
}
else
if
(
RC
==
&
SystemZ
::
FP64RegClass
)
{
Opc
=
SystemZ
::
FMOV64rm
;
}
else
if
(
RC
==
&
SystemZ
::
GR64PRegClass
)
{
Opc
=
SystemZ
::
MOV64Prm
;
}
else
if
(
RC
==
&
SystemZ
::
GR128RegClass
)
{
Opc
=
SystemZ
::
MOV128rm
;
}
else
llvm_unreachable
(
"Unsupported regclass to load"
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
,
DestReg
)
,
FrameIdx
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> int ix86_omp_device_kind_arch_isa ( enum omp_device_kind_arch_isa trait , const char * name ) { switch ( trait ) { case omp_device_kind : return strcmp ( name , "cpu" ) == 0 ; case omp_device_arch : if ( strcmp ( name , "intel_mic" ) == 0 ) return 1 ; if ( strcmp ( name , "x86" ) == 0 ) return 1 ; if ( TARGET_64BIT ) { if ( TARGET_X32 ) return strcmp ( name , "x32" ) == 0 ; else return strcmp ( name , "x86_64" ) == 0 ; } if ( strcmp ( name , "ia32" ) == 0 || strcmp ( name , "i386" ) == 0 ) return 1 ; if ( strcmp ( name , "i486" ) == 0 ) return ix86_arch != PROCESSOR_I386 ? 1 : - 1 ; if ( strcmp ( name , "i586" ) == 0 ) return ( ix86_arch != PROCESSOR_I386 && ix86_arch != PROCESSOR_I486 ) ? 1 : - 1 ; if ( strcmp ( name , "i686" ) == 0 ) return ( ix86_arch != PROCESSOR_I386 && ix86_arch != PROCESSOR_I486 && ix86_arch != PROCESSOR_LAKEMONT && ix86_arch != PROCESSOR_PENTIUM ) ? 1 : - 1 ; return 0 ; case omp_device_isa : for ( int i = 0 ; i < 2 ; i ++ ) { struct ix86_target_opts * opts = i ? isa2_opts : isa_opts ; size_t nopts = i ? ARRAY_SIZE ( isa2_opts ) : ARRAY_SIZE ( isa_opts ) ; HOST_WIDE_INT mask = i ? ix86_isa_flags2 : ix86_isa_flags ; for ( size_t n = 0 ; n < nopts ; n ++ ) { if ( opts [ n ] . mask == OPTION_MASK_ISA_SSE4_2 ) { if ( strcmp ( name , "sse4" ) == 0 ) return ( mask & opts [ n ] . mask ) != 0 ? 1 : - 1 ; } if ( strcmp ( name , opts [ n ] . option + 2 ) == 0 ) return ( mask & opts [ n ] . mask ) != 0 ? 1 : - 1 ; } } return 0 ; default : gcc_unreachable ( ) ; } } </s>

Return 1 if TRAIT NAME is present in the OpenMP context 's device trait set , return 0 if not present in any OpenMP context in the whole translation unit , or -1 if not present in the current OpenMP context but might be present in another OpenMP context in the same TU .


<s> bool AArch64FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; return ( MFI -> hasCalls ( ) && MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MFI -> hasStackMap ( ) || MFI -> hasPatchPoint ( ) || RegInfo -> needsStackRealignment ( MF ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> const MCPhysReg * TVMRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const MCPhysReg CalleeSavedRegs [ ] = { 0 } ; return CalleeSavedRegs ; } </s>


<s> ix86_dependencies_evaluation_hook static int ix86_reassociation_width ( unsigned int op , machine_mode mode ) { int width = 1 ; if ( VECTOR_MODE_P ( mode ) ) { int div = 1 ; if ( INTEGRAL_MODE_P ( mode ) ) width = ix86_cost -> reassoc_vec_int ; else if ( FLOAT_MODE_P ( mode ) ) width = ix86_cost -> reassoc_vec_fp ; if ( width == 1 ) return 1 ; if ( ( ix86_tune == PROCESSOR_ZNVER1 || ix86_tune == PROCESSOR_ZNVER2 || ix86_tune == PROCESSOR_ZNVER3 ) && INTEGRAL_MODE_P ( mode ) && op != PLUS && op != MINUS ) return 1 ; if ( TARGET_AVX256_SPLIT_REGS && GET_MODE_BITSIZE ( mode ) > 128 ) div = GET_MODE_BITSIZE ( mode ) / 128 ; else if ( TARGET_SSE_SPLIT_REGS && GET_MODE_BITSIZE ( mode ) > 64 ) div = GET_MODE_BITSIZE ( mode ) / 64 ; width = ( width + div - 1 ) / div ; } else if ( INTEGRAL_MODE_P ( mode ) ) width = ix86_cost -> reassoc_int ; else if ( FLOAT_MODE_P ( mode ) ) width = ix86_cost -> reassoc_fp ; if ( ! TARGET_64BIT && width > 2 ) width = 2 ; return width ; } </s>

Implementation of reassociation_width target hook used by reassoc phase to identify parallelism level in reassociated tree . Statements tree_code is passed in OPC . Arguments type is passed in MODE . Currently parallel reassociation is enabled for Atom processors only and we set reassociation width to be 2 because Atom may issue up to 2 instructions per cycle . Return value should be fixed if parallel reassociation is enabled for other processors .


<s> static reg_class_t pdp11_preferred_reload_class ( rtx x , reg_class_t rclass ) { if ( rclass == FPU_REGS ) return LOAD_FPU_REGS ; if ( rclass == ALL_REGS ) { if ( FLOAT_MODE_P ( GET_MODE ( x ) ) ) return LOAD_FPU_REGS ; else return GENERAL_REGS ; } return rclass ; } </s>

TARGET_PREFERRED_RELOAD_CLASS Given an rtx X being reloaded into a reg required to be in class CLASS , return the class of reg to actually use . In general this is just CLASS ; but on some machines in some cases it is preferable to use a more restrictive class . loading is easier into LOAD_FPU_REGS than FPU_REGS !


<s> HexagonMCExpr * HexagonMCExpr :: create ( MCExpr const * Expr , MCContext & Ctx ) { return new ( Ctx ) HexagonMCExpr ( Expr ) ; } </s>


<s>
const
char
*
getPassName
(
)
const
override
{
return
"ARM A15 S->D optimizer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void AArch64InstPrinter :: printImm ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand ( OpNo ) ; O << "#" << formatImm ( Op . getImm ( ) ) ; } </s>

Implement target specific printing for machine operand immediate value , so that we can have more meaningful mnemonic than a 64-bit integer .


<s>
void
NVPTXAsmPrinter
::
emitHeader
(
Module
&
M
,
raw_ostream
&
O
,
const
NVPTXSubtarget
&
STI
)
{
O
<<
"//\n"
;
O
<<
"// Generated by LLVM NVPTX Back-End\n"
;
O
<<
"//\n"
;
O
<<
"\n"
;
unsigned
PTXVersion
=
STI
.
getPTXVersion
(
)
;
O
<<
".version "
<<
(
PTXVersion
/
10
)
<<
"."
<<
(
PTXVersion
%
10
)
<<
"\n"
;
O
<<
".target "
;
O
<<
STI
.
getTargetName
(
)
;
const
NVPTXTargetMachine
&
NTM
=
static_cast
<
const
NVPTXTargetMachine
&
>
(
TM
)
;
if
(
NTM
.
getDrvInterface
(
)
==
NVPTX
::
NVCL
)
O
<<
", texmode_independent"
;
bool
HasFullDebugInfo
=
false
;
for
(
DICompileUnit
*
CU
:
M
.
debug_compile_units
(
)
)
{
switch
(
CU
->
getEmissionKind
(
)
)
{
case
DICompileUnit
::
NoDebug
:
case
DICompileUnit
::
DebugDirectivesOnly
:
break
;
case
DICompileUnit
::
LineTablesOnly
:
case
DICompileUnit
::
FullDebug
:
HasFullDebugInfo
=
true
;
break
;
}
if
(
HasFullDebugInfo
)
break
;
}
if
(
MMI
&&
MMI
->
hasDebugInfo
(
)
&&
HasFullDebugInfo
)
O
<<
"//, debug"
;
O
<<
"\n"
;
O
<<
".address_size "
;
if
(
NTM
.
is64Bit
(
)
)
O
<<
"64"
;
else
O
<<
"32"
;
O
<<
"\n"
;
O
<<
"\n"
;
}
</s>

Emit the header for this unit , not including the initial length field .

NVPTX
NVPTX
NVPTX
"//\n"
"// Generated by LLVM NVPTX Back-End\n"
"//\n"
"\n"
".version "
10
"."
10
"\n"
".target "
NVPTX
NVPTX
NVPTX::NVCL
", texmode_independent"
"//, debug"
"\n"
".address_size "
"64"
"32"
"\n"
"\n"


<s> bool SystemZPassConfig :: addILPOpts ( ) { addPass ( & EarlyIfConverterID ) ; return true ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"AArch64 Instruction Selection"
;
}
</s>


"SIInstrInfo::loadRegFromStackSlot - Do not know how to"


<s> bool enableIndirectBrExpand ( ) const override { return true ; } </s>

If we are using indirect thunks , we need to expand indirectbr to avoid it lowering to an actual indirect jump .


<s> virtual int getSize ( const MachineInstr * Instr ) { return TM . getInstrInfo ( ) -> getInstrSize ( Instr ) ; } </s>

Return the number of bytes in the encoding of this instruction , or zero if the encoding size can not be known from the opcode .


<s> unsigned HexagonTTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args , const Instruction * CxtI ) { if ( Ty -> isVectorTy ( ) ) { std :: pair < int , MVT > LT = TLI . getTypeLegalizationCost ( DL , Ty ) ; if ( LT . second . isFloatingPoint ( ) ) return LT . first + FloatFactor * getTypeNumElements ( Ty ) ; } return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo , Args , CxtI ) ; } </s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> int RISCVTTIImpl :: getIntImmCost ( Intrinsic :: ID IID , unsigned Idx , const APInt & Imm , Type * Ty ) { return TTI :: TCC_Free ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> bool WebAssemblyFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> void PPCRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( GuaranteedTailCallOpt && I -> getOpcode ( ) == PPC :: ADJCALLSTACKUP ) { if ( int CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { bool is64Bit = Subtarget . isPPC64 ( ) ; CalleeAmt *= - 1 ; unsigned StackReg = is64Bit ? PPC :: X1 : PPC :: R1 ; unsigned TmpReg = is64Bit ? PPC :: X0 : PPC :: R0 ; unsigned ADDIInstr = is64Bit ? PPC :: ADDI8 : PPC :: ADDI ; unsigned ADDInstr = is64Bit ? PPC :: ADD8 : PPC :: ADD4 ; unsigned LISInstr = is64Bit ? PPC :: LIS8 : PPC :: LIS ; unsigned ORIInstr = is64Bit ? PPC :: ORI8 : PPC :: ORI ; MachineInstr * MI = I ; DebugLoc dl = MI -> getDebugLoc ( ) ; if ( isInt16 ( CalleeAmt ) ) { BuildMI ( MBB , I , dl , TII . get ( ADDIInstr ) , StackReg ) . addReg ( StackReg ) . addImm ( CalleeAmt ) ; } else { MachineBasicBlock :: iterator MBBI = I ; BuildMI ( MBB , MBBI , dl , TII . get ( LISInstr ) , TmpReg ) . addImm ( CalleeAmt >> 16 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ORIInstr ) , TmpReg ) . addReg ( TmpReg , RegState :: Kill ) . addImm ( CalleeAmt & 0xFFFF ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ADDInstr ) ) . addReg ( StackReg ) . addReg ( StackReg ) . addReg ( TmpReg ) ; } } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> MachineBasicBlock :: iterator UPTFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( I -> getOpcode ( ) == UPT :: ADJCALLSTACKUP || I -> getOpcode ( ) == UPT :: ADJCALLSTACKDOWN ) { return MBB . erase ( I ) ; } } </s>

UPT UPT UPT::ADJCALLSTACKUP UPT::ADJCALLSTACKDOWN


<s> static rtx arm_expand_unop_builtin ( enum insn_code icode , tree exp , rtx target , int do_load ) { rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , 0 ) ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = NULL_RTX ; machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; machine_mode mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; bool builtin_sha1h_p = false ; if ( insn_data [ icode ] . n_operands == 3 ) { gcc_assert ( icode == CODE_FOR_crypto_sha1h ) ; builtin_sha1h_p = true ; } if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( do_load ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; else { if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; } if ( builtin_sha1h_p ) op1 = GEN_INT ( TARGET_BIG_END ? 1 : 0 ) ; if ( builtin_sha1h_p ) pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; else pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>

Subroutine of arm_expand_builtin to take care of unop insns .


<s> void aarch64_split_sve_subreg_move ( rtx dest , rtx ptrue , rtx src ) { machine_mode mode_with_wider_elts = aarch64_sve_int_mode ( GET_MODE ( dest ) ) ; machine_mode mode_with_narrower_elts = aarch64_sve_int_mode ( GET_MODE ( src ) ) ; if ( GET_MODE_UNIT_SIZE ( mode_with_wider_elts ) < GET_MODE_UNIT_SIZE ( mode_with_narrower_elts ) ) std :: swap ( mode_with_wider_elts , mode_with_narrower_elts ) ; unsigned int unspec = aarch64_sve_rev_unspec ( mode_with_narrower_elts ) ; machine_mode pred_mode = aarch64_sve_pred_mode ( mode_with_wider_elts ) ; ptrue = gen_lowpart ( pred_mode , ptrue ) ; dest = aarch64_replace_reg_mode ( dest , mode_with_wider_elts ) ; src = aarch64_replace_reg_mode ( src , mode_with_wider_elts ) ; emit_insn ( gen_aarch64_pred ( unspec , mode_with_wider_elts , dest , ptrue , src ) ) ; } </s>

Split a * aarch64_sve_mov < mode > _subreg_be pattern with the given operands .


<s> void AArch64Subtarget :: overrideSchedPolicy ( MachineSchedPolicy & Policy , MachineInstr * begin , MachineInstr * end , unsigned NumRegionInstrs ) const { Policy . OnlyTopDown = false ; Policy . OnlyBottomUp = false ; if ( isCyclone ( ) ) Policy . DisableLatencyHeuristic = true ; } </s>

Override generic scheduling policy within a region .


<s> const LC3bRegisterInfo & LC3bInstrInfo :: getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static bool is_branch ( rtx_insn * insn ) { return ( CALL_P ( insn ) || JUMP_P ( insn ) ) ; } </s>

Return true if insn is a branch instruction .


Convert the CONST_WIDE_INT operand OP to broadcast in MODE .


<s>
bool
PPCInstrInfo
::
getFMAPatterns
(
MachineInstr
&
Root
,
SmallVectorImpl
<
MachineCombinerPattern
>
&
Patterns
)
const
{
MachineBasicBlock
*
MBB
=
Root
.
getParent
(
)
;
const
MachineRegisterInfo
&
MRI
=
MBB
->
getParent
(
)
->
getRegInfo
(
)
;
auto
IsAllOpsVirtualReg
=
[
]
(
const
MachineInstr
&
Instr
)
{
for
(
const
auto
&
MO
:
Instr
.
explicit_operands
(
)
)
if
(
!
(
MO
.
isReg
(
)
&&
Register
::
isVirtualRegister
(
MO
.
getReg
(
)
)
)
)
return
false
;
return
true
;
}
;
auto
IsReassociable
=
[
&
]
(
const
MachineInstr
&
Instr
,
int16_t
&
AddOpIdx
,
bool
IsLeaf
,
bool
IsAdd
)
{
int16_t
Idx
=
1
;
if
(
!
IsAdd
)
{
Idx
=
getFMAOpIdxInfo
(
Instr
.
getOpcode
(
)
)
;
if
(
Idx
<
0
)
return
false
;
}
else
if
(
Instr
.
getOpcode
(
)
!=
FMAOpIdxInfo
[
getFMAOpIdxInfo
(
Root
.
getOpcode
(
)
)
]
[
InfoArrayIdxFAddInst
]
)
return
false
;
if
(
!
(
Instr
.
getFlag
(
MachineInstr
::
MIFlag
::
FmReassoc
)
&&
Instr
.
getFlag
(
MachineInstr
::
MIFlag
::
FmNsz
)
)
)
return
false
;
if
(
!
IsAllOpsVirtualReg
(
Instr
)
)
return
false
;
if
(
IsAdd
&&
IsLeaf
)
return
true
;
AddOpIdx
=
FMAOpIdxInfo
[
Idx
]
[
InfoArrayIdxAddOpIdx
]
;
const
MachineOperand
&
OpAdd
=
Instr
.
getOperand
(
AddOpIdx
)
;
MachineInstr
*
MIAdd
=
MRI
.
getUniqueVRegDef
(
OpAdd
.
getReg
(
)
)
;
if
(
!
MIAdd
||
MIAdd
->
getParent
(
)
!=
MBB
)
return
false
;
return
IsLeaf
true
:
MRI
.
hasOneNonDBGUse
(
OpAdd
.
getReg
(
)
)
;
}
;
int16_t
AddOpIdx
=
1
;
if
(
!
IsReassociable
(
Root
,
AddOpIdx
,
false
,
false
)
)
return
false
;
assert
(
(
AddOpIdx
>=
0
)
&&
"add operand index not right!"
)
;
Register
RegB
=
Root
.
getOperand
(
AddOpIdx
)
.
getReg
(
)
;
MachineInstr
*
Prev
=
MRI
.
getUniqueVRegDef
(
RegB
)
;
AddOpIdx
=
1
;
if
(
!
IsReassociable
(
*
Prev
,
AddOpIdx
,
false
,
false
)
)
return
false
;
assert
(
(
AddOpIdx
>=
0
)
&&
"add operand index not right!"
)
;
Register
RegA
=
Prev
->
getOperand
(
AddOpIdx
)
.
getReg
(
)
;
MachineInstr
*
Leaf
=
MRI
.
getUniqueVRegDef
(
RegA
)
;
AddOpIdx
=
1
;
if
(
IsReassociable
(
*
Leaf
,
AddOpIdx
,
true
,
false
)
)
{
Patterns
.
push_back
(
MachineCombinerPattern
::
REASSOC_XMM_AMM_BMM
)
;
return
true
;
}
if
(
IsReassociable
(
*
Leaf
,
AddOpIdx
,
true
,
true
)
)
{
Patterns
.
push_back
(
MachineCombinerPattern
::
REASSOC_XY_AMM_BMM
)
;
return
true
;
}
return
false
;
}
</s>

Return true when there is potentially a faster code sequence for a fma chain ending in Root .


<s> static tree s390_builtin_decl ( unsigned fcode , bool initialized_p ATTRIBUTE_UNUSED ) { if ( fcode >= S390_BUILTIN_MAX ) return error_mark_node ; return s390_builtin_decls [ fcode ] ; } </s>

Return the decl for the target specific builtin with the function code FCODE .


<s> enum avms_arg_type alpha_arg_type ( enum machine_mode mode ) { switch ( mode ) { case SFmode : return TARGET_FLOAT_VAX ? FF : FS ; case DFmode : return TARGET_FLOAT_VAX ? FD : FT ; default : return I64 ; } } </s>

Return the VMS argument type corresponding to MODE .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < LoopInfo > ( ) ; AU . addPreserved < LoopInfo > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addRequired < ScalarEvolution > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s>
static
void
ix86_print_operand_address
(
FILE
*
file
,
machine_mode
,
rtx
addr
)
{
if
(
this_is_asm_operands
&&
!
address_operand
(
addr
,
VOIDmode
)
)
output_operand_lossage
(
"invalid constraints for operand"
)
;
else
ix86_print_operand_address_as
(
file
,
addr
,
ADDR_SPACE_GENERIC
,
false
)
;
}
</s>

Print a memory operand whose address is ADDR .


<s> static int hppa_register_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t from , reg_class_t to ) { if ( from == SHIFT_REGS ) return 0x100 ; else if ( to == SHIFT_REGS && FP_REG_CLASS_P ( from ) ) return 18 ; else if ( ( FP_REG_CLASS_P ( from ) && ! FP_REG_CLASS_P ( to ) ) || ( FP_REG_CLASS_P ( to ) && ! FP_REG_CLASS_P ( from ) ) ) return 16 ; else return 2 ; } </s>

Implement the TARGET_REGISTER_MOVE_COST hook . Compute extra cost of moving data between one register class and another . Make moves from SAR so expensive they should never happen . We used to have 0xffff here , but that generates overflow in rare cases . Copies involving a FP register and a non-FP register are relatively expensive because they must go through memory . Other copies are reasonably cheap .


<s> static void pa_init_libfuncs ( void ) { if ( HPUX_LONG_DOUBLE_LIBRARY ) { set_optab_libfunc ( add_optab , TFmode , "_U_Qfadd" ) ; set_optab_libfunc ( sub_optab , TFmode , "_U_Qfsub" ) ; set_optab_libfunc ( smul_optab , TFmode , "_U_Qfmpy" ) ; set_optab_libfunc ( sdiv_optab , TFmode , "_U_Qfdiv" ) ; set_optab_libfunc ( smin_optab , TFmode , "_U_Qmin" ) ; set_optab_libfunc ( smax_optab , TFmode , "_U_Qfmax" ) ; set_optab_libfunc ( sqrt_optab , TFmode , "_U_Qfsqrt" ) ; set_optab_libfunc ( abs_optab , TFmode , "_U_Qfabs" ) ; set_optab_libfunc ( neg_optab , TFmode , "_U_Qfneg" ) ; set_optab_libfunc ( eq_optab , TFmode , "_U_Qfeq" ) ; set_optab_libfunc ( ne_optab , TFmode , "_U_Qfne" ) ; set_optab_libfunc ( gt_optab , TFmode , "_U_Qfgt" ) ; set_optab_libfunc ( ge_optab , TFmode , "_U_Qfge" ) ; set_optab_libfunc ( lt_optab , TFmode , "_U_Qflt" ) ; set_optab_libfunc ( le_optab , TFmode , "_U_Qfle" ) ; set_optab_libfunc ( unord_optab , TFmode , "_U_Qfunord" ) ; set_conv_libfunc ( sext_optab , TFmode , SFmode , "_U_Qfcnvff_sgl_to_quad" ) ; set_conv_libfunc ( sext_optab , TFmode , DFmode , "_U_Qfcnvff_dbl_to_quad" ) ; set_conv_libfunc ( trunc_optab , SFmode , TFmode , "_U_Qfcnvff_quad_to_sgl" ) ; set_conv_libfunc ( trunc_optab , DFmode , TFmode , "_U_Qfcnvff_quad_to_dbl" ) ; set_conv_libfunc ( sfix_optab , SImode , TFmode , TARGET_64BIT ? "__U_Qfcnvfxt_quad_to_sgl" : "_U_Qfcnvfxt_quad_to_sgl" ) ; set_conv_libfunc ( sfix_optab , DImode , TFmode , "_U_Qfcnvfxt_quad_to_dbl" ) ; set_conv_libfunc ( ufix_optab , SImode , TFmode , "_U_Qfcnvfxt_quad_to_usgl" ) ; set_conv_libfunc ( ufix_optab , DImode , TFmode , "_U_Qfcnvfxt_quad_to_udbl" ) ; set_conv_libfunc ( sfloat_optab , TFmode , SImode , "_U_Qfcnvxf_sgl_to_quad" ) ; set_conv_libfunc ( sfloat_optab , TFmode , DImode , "_U_Qfcnvxf_dbl_to_quad" ) ; set_conv_libfunc ( ufloat_optab , TFmode , SImode , "_U_Qfcnvxf_usgl_to_quad" ) ; set_conv_libfunc ( ufloat_optab , TFmode , DImode , "_U_Qfcnvxf_udbl_to_quad" ) ; } if ( TARGET_SYNC_LIBCALL ) init_sync_libfuncs ( UNITS_PER_WORD ) ; } </s>

Initialize optabs to point to emulation routines .


<s> unsigned MipsCodeEmitter :: getBranchTargetOpValue ( const MachineInstr & MI , unsigned OpNo ) const { return 0 ; } </s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .


"builtin %s only accepts a string argument"

"cpu %s is an invalid argument to builtin %s"

"hwcap %s is an invalid argument to builtin %s"

Expand the CPU builtin in FCODE and store the result in TARGET .


"ADJSTACKDOWN and ADJSTACKUP should be no-ops"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static std :: unique_ptr < MipsOperand > CreateMem ( std :: unique_ptr < MipsOperand > Base , const MCExpr * Off , SMLoc S , SMLoc E , MipsAsmParser & Parser ) { auto Op = llvm :: make_unique < MipsOperand > ( k_Memory , Parser ) ; Op -> Mem . Base = Base . release ( ) ; Op -> Mem . Off = Off ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>


<s> bool PPCFrameLowering :: enableShrinkWrapping ( const MachineFunction & MF ) const { if ( MF . getInfo < PPCFunctionInfo > ( ) -> shrinkWrapDisabled ( ) ) return false ; return ! MF . getSubtarget < PPCSubtarget > ( ) . is32BitELFABI ( ) ; } </s>

Returns true if the target will correctly handle shrink wrapping .


<s> inline unsigned int function_base :: call_properties ( const function_instance & instance ) const { unsigned int flags = 0 ; if ( instance . type_suffix ( 0 ) . float_p || instance . type_suffix ( 1 ) . float_p ) flags |= CP_READ_FPCR | CP_RAISE_FP_EXCEPTIONS ; return flags ; } </s>

Default implementation of function_base : :call_properties , with conservatively correct behavior for floating-point instructions .


<s> unsigned getAlign ( ) const { return Align ; } </s>

Return the minimum known alignment in bytes of the actual memory reference .


<s> void XCoreInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , get ( XCore :: STWFI ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> Register WebAssemblyRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { static const unsigned Regs [ 2 ] [ 2 ] = { { WebAssembly :: SP32 , WebAssembly :: SP64 } , { WebAssembly :: FP32 , WebAssembly :: FP64 } } ; const WebAssemblyFrameLowering * TFI = getFrameLowering ( MF ) ; return Regs [ TFI -> hasFP ( MF ) ] [ TT . isArch64Bit ( ) ] ; } </s>


<s> int riscv_address_insns ( rtx x , enum machine_mode mode , bool might_split_p ) { struct riscv_address_info addr ; int n = 1 ; if ( ! riscv_classify_address ( & addr , x , mode , false ) ) return 0 ; if ( mode != BLKmode && might_split_p ) n += ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; if ( addr . type == ADDRESS_LO_SUM ) n += riscv_symbol_insns ( addr . symbol_type ) - 1 ; return n ; } </s>

Return the number of instructions needed to load or store a value of mode MODE at address X . Return 0 if X is n't valid for MODE . Assume that multiword moves may need to be split into word moves if MIGHT_SPLIT_P , otherwise assume that a single load or store is enough .


<s> void MipsSEFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; const MipsSEInstrInfo & TII = * static_cast < const MipsSEInstrInfo * > ( STI . getInstrInfo ( ) ) ; const MipsRegisterInfo & RegInfo = * static_cast < const MipsRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; unsigned SP = ABI . GetStackPtr ( ) ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned ZERO = ABI . GetNullPtr ( ) ; unsigned MOVE = ABI . GetGPRMoveOp ( ) ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , DL , TII . get ( MOVE ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( MipsFI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = ABI . ArePtrs64bit ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = 0 ; J < 4 ; ++ J ) { TII . loadRegFromStackSlot ( MBB , I , ABI . GetEhDataReg ( J ) , MipsFI -> getEhDataRegFI ( J ) , RC , & RegInfo ) ; } } if ( MF . getFunction ( ) -> hasFnAttribute ( "interrupt" ) ) emitInterruptEpilogueStub ( MF , MBB ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize , MBB , MBBI ) ; } </s>

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips 0 Mips Mips::GPR64RegClass Mips::GPR32RegClass 0 0 4 Mips "interrupt"


This function will set the fpscr from memory . MODE is the mode we are setting it to .


<s>
void
BTFDebug
::
beginFunctionImpl
(
const
MachineFunction
*
MF
)
{
auto
*
SP
=
MF
->
getFunction
(
)
.
getSubprogram
(
)
;
auto
*
Unit
=
SP
->
getUnit
(
)
;
if
(
Unit
->
getEmissionKind
(
)
==
DICompileUnit
::
NoDebug
)
{
SkipInstruction
=
true
;
return
;
}
SkipInstruction
=
false
;
if
(
MapDefNotCollected
)
{
processGlobals
(
true
)
;
MapDefNotCollected
=
false
;
}
std
::
unordered_map
<
uint32_t
,
StringRef
>
FuncArgNames
;
for
(
const
DINode
*
DN
:
SP
->
getRetainedNodes
(
)
)
{
if
(
const
auto
*
DV
=
dyn_cast
<
DILocalVariable
>
(
DN
)
)
{
uint32_t
Arg
=
DV
->
getArg
(
)
;
if
(
Arg
)
{
visitTypeEntry
(
DV
->
getType
(
)
)
;
FuncArgNames
[
Arg
]
=
DV
->
getName
(
)
;
}
}
}
uint32_t
ProtoTypeId
;
visitSubroutineType
(
SP
->
getType
(
)
,
true
,
FuncArgNames
,
ProtoTypeId
)
;
uint8_t
Scope
=
SP
->
isLocalToUnit
(
)
BTF
::
FUNC_STATIC
:
BTF
::
FUNC_GLOBAL
;
auto
FuncTypeEntry
=
std
::
make_unique
<
BTFTypeFunc
>
(
SP
->
getName
(
)
,
ProtoTypeId
,
Scope
)
;
uint32_t
FuncTypeId
=
addType
(
std
::
move
(
FuncTypeEntry
)
)
;
for
(
const
auto
&
TypeEntry
:
TypeEntries
)
TypeEntry
->
completeType
(
*
this
)
;
MCSymbol
*
FuncLabel
=
Asm
->
getFunctionBegin
(
)
;
BTFFuncInfo
FuncInfo
;
FuncInfo
.
Label
=
FuncLabel
;
FuncInfo
.
TypeId
=
FuncTypeId
;
if
(
FuncLabel
->
isInSection
(
)
)
{
MCSection
&
Section
=
FuncLabel
->
getSection
(
)
;
const
MCSectionELF
*
SectionELF
=
dyn_cast
<
MCSectionELF
>
(
&
Section
)
;
assert
(
SectionELF
&&
"Null section for Function Label"
)
;
SecNameOff
=
addString
(
SectionELF
->
getName
(
)
)
;
}
else
{
SecNameOff
=
addString
(
".text"
)
;
}
FuncInfoTable
[
SecNameOff
]
.
push_back
(
FuncInfo
)
;
}
</s>


<s>
SDValue
VETargetLowering
::
withTargetFlags
(
SDValue
Op
,
unsigned
TF
,
SelectionDAG
&
DAG
)
const
{
if
(
const
GlobalAddressSDNode
*
GA
=
dyn_cast
<
GlobalAddressSDNode
>
(
Op
)
)
return
DAG
.
getTargetGlobalAddress
(
GA
->
getGlobal
(
)
,
SDLoc
(
GA
)
,
GA
->
getValueType
(
0
)
,
GA
->
getOffset
(
)
,
TF
)
;
if
(
const
BlockAddressSDNode
*
BA
=
dyn_cast
<
BlockAddressSDNode
>
(
Op
)
)
return
DAG
.
getTargetBlockAddress
(
BA
->
getBlockAddress
(
)
,
Op
.
getValueType
(
)
,
0
,
TF
)
;
if
(
const
ExternalSymbolSDNode
*
ES
=
dyn_cast
<
ExternalSymbolSDNode
>
(
Op
)
)
return
DAG
.
getTargetExternalSymbol
(
ES
->
getSymbol
(
)
,
ES
->
getValueType
(
0
)
,
TF
)
;
llvm_unreachable
(
"Unhandled address SDNode"
)
;
}
</s>


<s> bool r0rel_constant_p ( rtx op ) { if ( GET_CODE ( op ) == SYMBOL_REF && nios2_symbol_ref_in_r0rel_data_p ( op ) ) return true ; else if ( GET_CODE ( op ) == CONST && GET_CODE ( XEXP ( op , 0 ) ) == PLUS ) return r0rel_constant_p ( XEXP ( XEXP ( op , 0 ) , 0 ) ) ; else if ( GET_CODE ( op ) == CONST_INT && SMALL_INT ( INTVAL ( op ) ) ) return true ; return false ; } </s>

Likewise if this is a zero-relative accessible reference .


<s> TargetLoweringBase :: LegalizeTypeAction X86TargetLowering :: getPreferredVectorAction ( EVT VT ) const { if ( VT == MVT :: v32i1 && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return TypeSplitVector ; if ( ExperimentalVectorWideningLegalization && VT . getVectorNumElements ( ) != 1 && VT . getVectorElementType ( ) . getSimpleVT ( ) != MVT :: i1 ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s> static void expand_block_set_1 ( rtx dst_reg , rtx value_rtx , rtx bytes_rtx ) { value_rtx = convert_to_mode ( Pmode , value_rtx , 1 ) ; emit_library_call ( byt_memset_libfunc , LCT_NORMAL , VOIDmode , 3 , dst_reg , Pmode , value_rtx , Pmode , convert_to_mode ( TYPE_MODE ( sizetype ) , bytes_rtx , TYPE_UNSIGNED ( sizetype ) ) , TYPE_MODE ( sizetype ) ) ; } </s>

Generate a call to a library function to set BYTES_RTX bytes at address DST_REG to VALUE_RTX in 1-byte chunks .


<s> FastISel * PPCTargetLowering :: createFastISel ( FunctionLoweringInfo & FuncInfo , const TargetLibraryInfo * LibInfo ) const { return PPC :: createFastISel ( FuncInfo , LibInfo ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> static void sparc_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int regno , padding ; function_arg_slotno ( cum , mode , type , named , false , & regno , & padding ) ; cum -> words += padding ; if ( TARGET_ARCH32 ) { cum -> words += ( mode != BLKmode ? ROUND_ADVANCE ( GET_MODE_SIZE ( mode ) ) : ROUND_ADVANCE ( int_size_in_bytes ( type ) ) ) ; } else { if ( type && AGGREGATE_TYPE_P ( type ) ) { int size = int_size_in_bytes ( type ) ; if ( size <= 8 ) ++ cum -> words ; else if ( size <= 16 ) cum -> words += 2 ; else ++ cum -> words ; } else { cum -> words += ( mode != BLKmode ? ROUND_ADVANCE ( GET_MODE_SIZE ( mode ) ) : ROUND_ADVANCE ( int_size_in_bytes ( type ) ) ) ; } } } </s>

Handle the TARGET_FUNCTION_ARG_ADVANCE hook . Update the data in CUM to advance over an argument of mode MODE and data type TYPE . TYPE is null for libcalls where that information may not be available .


<s> bool X86TargetLowering :: isFMAFasterThanFMulAndFAdd ( EVT VT ) const { if ( ! ( Subtarget -> hasFMA ( ) || Subtarget -> hasFMA4 ( ) ) ) return false ; VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f32 : case MVT :: f64 : return true ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


"Can't store this register to stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> bool ARMBaseInstrInfo :: isCopyInstrImpl ( const MachineInstr & MI , const MachineOperand * & Src , const MachineOperand * & Dest ) const { if ( ! MI . isMoveReg ( ) || ( MI . getOpcode ( ) == ARM :: VORRq && MI . getOperand ( 1 ) . getReg ( ) != MI . getOperand ( 2 ) . getReg ( ) ) ) return false ; Dest = & MI . getOperand ( 0 ) ; Src = & MI . getOperand ( 1 ) ; return true ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


<s> static inline int arm_arm_address_cost ( rtx x ) { enum rtx_code c = GET_CODE ( x ) ; if ( c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC ) return 0 ; if ( c == MEM || c == LABEL_REF || c == SYMBOL_REF ) return 10 ; if ( c == PLUS || c == MINUS ) { if ( GET_CODE ( XEXP ( x , 0 ) ) == CONST_INT ) return 2 ; if ( ARITHMETIC_P ( XEXP ( x , 0 ) ) || ARITHMETIC_P ( XEXP ( x , 1 ) ) ) return 3 ; return 4 ; } return 6 ; } </s>

All address computations that can be done are free , but rtx cost returns the same for practically all of them . So we weight the different types of address here in the order ( most pref first ) : PRE/POST_INC/DEC , SHIFT or NON-INT sum , INT sum , REG , MEM or LABEL .


<s> static rtx gen_frame_mem_offset ( machine_mode mode , rtx reg , int offset ) { rtx int_rtx , offset_rtx ; int_rtx = GEN_INT ( offset ) ; if ( ( TARGET_SPE_ABI && SPE_VECTOR_MODE ( mode ) && ! SPE_CONST_OFFSET_OK ( offset ) ) || ( TARGET_E500_DOUBLE && mode == DFmode ) ) { offset_rtx = gen_rtx_REG ( Pmode , FIXED_SCRATCH ) ; emit_move_insn ( offset_rtx , int_rtx ) ; } else offset_rtx = int_rtx ; return gen_frame_mem ( mode , gen_rtx_PLUS ( Pmode , reg , offset_rtx ) ) ; } </s>

Emit an offset memory reference suitable for a frame store , while converting to a valid addressing mode .


<s>
bool
MipsDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_R
:
case
InlineAsm
::
Constraint_ZC
:
OutOps
.
push_back
(
Op
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .

Mips
Mips
"Unexpected asm memory constraint"


<s> unsigned getExceptionPointerRegister ( const Constant * PersonalityFn ) const override { return SP :: I0 ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s> bool sh_vector_mode_supported_p ( machine_mode mode ATTRIBUTE_UNUSED ) { return false ; } </s>

Implements target hook vector_mode_supported_p .


<s> void microblaze_expand_epilogue ( void ) { HOST_WIDE_INT fsiz = current_frame_info . total_size ; rtx fsiz_rtx = GEN_INT ( fsiz ) ; rtx reg_rtx ; rtx mem_rtx ; if ( microblaze_can_use_return_insn ( ) ) { emit_jump_insn ( gen_return_internal ( gen_rtx_REG ( Pmode , GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM ) ) ) ; return ; } if ( fsiz > 0 ) { if ( ! crtl -> is_leaf || interrupt_handler ) { mem_rtx = gen_rtx_MEM ( SImode , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , const0_rtx ) ) ; if ( interrupt_handler ) MEM_VOLATILE_P ( mem_rtx ) = 1 ; reg_rtx = gen_rtx_REG ( SImode , MB_ABI_SUB_RETURN_ADDR_REGNUM ) ; emit_move_insn ( reg_rtx , mem_rtx ) ; } if ( frame_pointer_needed ) emit_insn ( gen_movsi ( stack_pointer_rtx , hard_frame_pointer_rtx ) ) ; save_restore_insns ( 0 ) ; emit_insn ( gen_blockage ( ) ) ; emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , fsiz_rtx ) ) ; } if ( crtl -> calls_eh_return ) emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , gen_raw_REG ( SImode , MB_EH_STACKADJ_REGNUM ) ) ) ; emit_jump_insn ( gen_return_internal ( gen_rtx_REG ( Pmode , GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM ) ) ) ; } </s>

Expand the epilogue into a bunch of separate insns .


<s> static void rs6000_darwin64_record_arg_flush ( CUMULATIVE_ARGS * cum , HOST_WIDE_INT bitpos , rtx rvec [ ] , int * k ) { machine_mode mode ; unsigned int regno ; unsigned int startbit , endbit ; int this_regno , intregs , intoffset ; rtx reg ; if ( cum -> intoffset == - 1 ) return ; intoffset = cum -> intoffset ; cum -> intoffset = - 1 ; if ( intoffset % BITS_PER_WORD != 0 ) { mode = mode_for_size ( BITS_PER_WORD - intoffset % BITS_PER_WORD , MODE_INT , 0 ) ; if ( mode == BLKmode ) { intoffset = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; mode = word_mode ; } } else mode = word_mode ; startbit = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; endbit = ROUND_UP ( bitpos , BITS_PER_WORD ) ; intregs = ( endbit - startbit ) / BITS_PER_WORD ; this_regno = cum -> words + intoffset / BITS_PER_WORD ; if ( intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno ) cum -> use_stack = 1 ; intregs = MIN ( intregs , GP_ARG_NUM_REG - this_regno ) ; if ( intregs <= 0 ) return ; intoffset /= BITS_PER_UNIT ; do { regno = GP_ARG_MIN_REG + this_regno ; reg = gen_rtx_REG ( mode , regno ) ; rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( intoffset ) ) ; this_regno += 1 ; intoffset = ( intoffset | ( UNITS_PER_WORD - 1 ) ) + 1 ; mode = word_mode ; intregs -= 1 ; } while ( intregs > 0 ) ; } </s>

A subroutine of rs6000_darwin64_record_arg . Assign the bits of the structure between cum- > intoffset and bitpos to integer registers .


<s> static rtx arc_dwarf_register_span ( rtx rtl ) { machine_mode mode = GET_MODE ( rtl ) ; unsigned regno ; rtx p ; if ( GET_MODE_SIZE ( mode ) != 8 ) return NULL_RTX ; p = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( 2 ) ) ; regno = REGNO ( rtl ) ; XVECEXP ( p , 0 , 0 ) = gen_rtx_REG ( SImode , regno ) ; XVECEXP ( p , 0 , 1 ) = gen_rtx_REG ( SImode , regno + 1 ) ; return p ; } </s>

Return a parallel of registers to represent where to find the register pieces if required , otherwise NULL_RTX .


"Some operands reg class are incompatible!"

optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare ; remove Compare if possible .


<s> const char * SHUXITargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( SHUXIISD :: NodeType ) Opcode ) { case SHUXIISD :: FIRST_NUMBER : break ; case SHUXIISD :: CMP : return "SHUXIISD::CMP" ; case SHUXIISD :: RET_FLAG : return "SHUXIISD::RET_FLAG" ; case SHUXIISD :: BR_CC : return "SHUXIISD::BR_CC" ; case SHUXIISD :: SELECT_CC : return "SHUXIISD::SELECT_CC" ; case SHUXIISD :: Wrapper : return "SHUXIISD::Wrapper" ; case SHUXIISD :: CALL : return "SHUXIISD::CALL" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> void WebAssemblyCFGStackify :: releaseMemory ( ) { ScopeTops . clear ( ) ; BeginToEnd . clear ( ) ; EndToBegin . clear ( ) ; TryToEHPad . clear ( ) ; EHPadToTry . clear ( ) ; BeginToBottom . clear ( ) ; } </s>

releaseMemory ( ) - This member can be implemented by a pass if it wants to be able to release its memory when it is no longer needed .


Return 1 if br.ret can do all the work required to return from a function .


<s> virtual const TargetSubtargetInfo * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static void spu_emit_branch_hint ( rtx_insn * before , rtx_insn * branch , rtx target , int distance , sbitmap blocks ) { rtx_insn * hint ; rtx_insn * insn ; rtx_jump_table_data * table ; if ( before == 0 || branch == 0 || target == 0 ) return ; if ( distance > 600 ) return ; if ( NOTE_INSN_BASIC_BLOCK_P ( before ) ) before = NEXT_INSN ( before ) ; rtx_code_label * branch_label = gen_label_rtx ( ) ; LABEL_NUSES ( branch_label ) ++ ; LABEL_PRESERVE_P ( branch_label ) = 1 ; insn = emit_label_before ( branch_label , branch ) ; rtx branch_label_ref = gen_rtx_LABEL_REF ( VOIDmode , branch_label ) ; bitmap_set_bit ( blocks , BLOCK_FOR_INSN ( branch ) -> index ) ; hint = emit_insn_before ( gen_hbr ( branch_label_ref , target ) , before ) ; recog_memoized ( hint ) ; INSN_LOCATION ( hint ) = INSN_LOCATION ( branch ) ; HINTED_P ( branch ) = 1 ; if ( GET_CODE ( target ) == LABEL_REF ) HINTED_P ( XEXP ( target , 0 ) ) = 1 ; else if ( tablejump_p ( branch , 0 , & table ) ) { rtvec vec ; int j ; if ( GET_CODE ( PATTERN ( table ) ) == ADDR_VEC ) vec = XVEC ( PATTERN ( table ) , 0 ) ; else vec = XVEC ( PATTERN ( table ) , 1 ) ; for ( j = GET_NUM_ELEM ( vec ) - 1 ; j >= 0 ; -- j ) HINTED_P ( XEXP ( RTVEC_ELT ( vec , j ) , 0 ) ) = 1 ; } if ( distance >= 588 ) { insn = emit_insn_before ( gen_blockage ( ) , hint ) ; recog_memoized ( insn ) ; INSN_LOCATION ( insn ) = INSN_LOCATION ( hint ) ; } else if ( distance <= 8 * 4 ) { int d ; for ( d = distance ; d < 8 * 4 ; d += 4 ) { insn = emit_insn_after ( gen_nopn_nv ( gen_rtx_REG ( SImode , 127 ) ) , hint ) ; recog_memoized ( insn ) ; INSN_LOCATION ( insn ) = INSN_LOCATION ( hint ) ; } insn = emit_insn_after ( gen_blockage ( ) , hint ) ; recog_memoized ( insn ) ; INSN_LOCATION ( insn ) = INSN_LOCATION ( hint ) ; if ( CALL_P ( branch ) && distance < 8 * 4 ) { insn = emit_insn_before ( gen_blockage ( ) , branch ) ; recog_memoized ( insn ) ; INSN_LOCATION ( insn ) = INSN_LOCATION ( branch ) ; } } } </s>


<s> const uint16_t * MipsRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_SaveList ; if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_SaveList ; if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_SaveList ; if ( Subtarget . isFP64bit ( ) ) return CSR_O32_FP64_SaveList ; return CSR_O32_SaveList ; } </s>


"Tail call for extern symbol not yet supported."

Targets should implement this to emit instructions .


<s> rtx_insn * s390_emit_jump ( rtx target , rtx cond ) { rtx insn ; target = gen_rtx_LABEL_REF ( VOIDmode , target ) ; if ( cond ) target = gen_rtx_IF_THEN_ELSE ( VOIDmode , cond , target , pc_rtx ) ; insn = gen_rtx_SET ( VOIDmode , pc_rtx , target ) ; return emit_jump_insn ( insn ) ; } </s>

Emit a jump instruction to TARGET . If COND is NULL_RTX , emit an unconditional jump , else a conditional jump under condition COND .


<s> static struct mips_multi_member * mips_multi_add ( void ) { mips_multi_member empty ; memset ( & empty , 0 , sizeof ( empty ) ) ; return mips_multi_members . safe_push ( empty ) ; } </s>

Add a new , uninitialized member to the current multi-insn sequence .


<s> void AnalyzeCallResult ( const SmallVectorImpl < ISD :: InputArg > & Ins , CCAssignFn Fn , const TargetLowering :: CallLoweringInfo & CLI ) { PreAnalyzeCallResultForF128 ( Ins , CLI ) ; CCState :: AnalyzeCallResult ( Ins , Fn ) ; OriginalArgWasFloat . clear ( ) ; OriginalArgWasF128 . clear ( ) ; } </s>

AnalyzeCallResult - Same as above except it 's specialized for calls which produce a single value .


<s> static void add_to_reg ( rtx reg , HOST_WIDE_INT value , int frame , int epilogue_p ) { if ( value == 0 ) return ; if ( value > 120 || value < - 120 ) { rtx tmpreg ; rtx tmpreg2 ; rtx_insn * insn ; tmpreg2 = NULL_RTX ; if ( epilogue_p >= 0 ) tmpreg = gen_rtx_REG ( SImode , REG_P1 ) ; else { int i ; for ( i = REG_P0 ; i <= REG_P5 ; i ++ ) if ( ( df_regs_ever_live_p ( i ) && ! call_used_regs [ i ] ) || ( ! TARGET_FDPIC && i == PIC_OFFSET_TABLE_REGNUM && ( crtl -> uses_pic_offset_table || ( TARGET_ID_SHARED_LIBRARY && ! crtl -> is_leaf ) ) ) ) break ; if ( i <= REG_P5 ) tmpreg = gen_rtx_REG ( SImode , i ) ; else { tmpreg = gen_rtx_REG ( SImode , REG_P1 ) ; tmpreg2 = gen_rtx_REG ( SImode , REG_I0 ) ; emit_move_insn ( tmpreg2 , tmpreg ) ; } } if ( frame ) frame_related_constant_load ( tmpreg , value , TRUE ) ; else insn = emit_move_insn ( tmpreg , GEN_INT ( value ) ) ; insn = emit_insn ( gen_addsi3 ( reg , reg , tmpreg ) ) ; if ( frame ) RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( tmpreg2 != NULL_RTX ) emit_move_insn ( tmpreg , tmpreg2 ) ; } else do { int size = value ; rtx_insn * insn ; if ( size > 60 ) size = 60 ; else if ( size < - 60 ) size = - 60 ; insn = emit_insn ( gen_addsi3 ( reg , reg , GEN_INT ( size ) ) ) ; if ( frame ) RTX_FRAME_RELATED_P ( insn ) = 1 ; value -= size ; } while ( value != 0 ) ; } </s>

Generate efficient code to add a value to a P register . Set RTX_FRAME_RELATED_P on the generated insns if FRAME is nonzero . EPILOGUE_P is zero if this function is called for prologue , otherwise it 's nonzero . And it 's less than zero if this is for sibcall epilogue .


<s> Optional < bool > isSyncScopeInclusion ( SyncScope :: ID A , SyncScope :: ID B ) const { const auto & AIO = getSyncScopeInclusionOrdering ( A ) ; const auto & BIO = getSyncScopeInclusionOrdering ( B ) ; if ( ! AIO || ! BIO ) return None ; return AIO . getValue ( ) > BIO . getValue ( ) ; } </s>

In AMDGPU target synchronization scopes are inclusive , meaning a larger synchronization scope is inclusive of a smaller synchronization scope .


"FPDelta isn't aligned per the Win64 ABI!"

"VLAs and dynamic stack realign, but no FP?!"

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s>
bool
MipsCodeEmitter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
JTI
=
(
(
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getJITInfo
(
)
;
II
=
(
(
const
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getInstrInfo
(
)
;
TD
=
(
(
const
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getDataLayout
(
)
;
Subtarget
=
&
TM
.
getSubtarget
<
MipsSubtarget
>
(
)
;
MCPEs
=
&
MF
.
getConstantPool
(
)
->
getConstants
(
)
;
MJTEs
=
0
;
if
(
MF
.
getJumpTableInfo
(
)
)
MJTEs
=
&
MF
.
getJumpTableInfo
(
)
->
getJumpTables
(
)
;
JTI
->
Initialize
(
MF
,
IsPIC
,
Subtarget
->
isLittle
(
)
)
;
MCE
.
setModuleInfo
(
&
getAnalysis
<
MachineModuleInfo
>
(
)
)
;
do
{
DEBUG
(
errs
(
)
<<
"JITTing function '"
<<
MF
.
getName
(
)
<<
"'\n"
)
;
MCE
.
startFunction
(
MF
)
;
for
(
MachineFunction
::
iterator
MBB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBB
!=
E
;
++
MBB
)
{
MCE
.
StartMachineBasicBlock
(
MBB
)
;
for
(
MachineBasicBlock
::
instr_iterator
I
=
MBB
->
instr_begin
(
)
,
E
=
MBB
->
instr_end
(
)
;
I
!=
E
;
++
I
)
emitInstruction
(
*
I
)
;
}
}
while
(
MCE
.
finishFunction
(
MF
)
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .

Mips
Mips
Mips
Mips
Mips
Mips
0
"JITTing function '"
"'\n"


"Cannot store this register to stack slot!"

Store the specified register of the given register class to the specified stack frame index .


<s> bool PPCInstrInfo :: getMachineCombinerPatterns ( MachineInstr & Root , SmallVectorImpl < MachineCombinerPattern > & Patterns , bool DoRegPressureReduce ) const { if ( Subtarget . getTargetMachine ( ) . getOptLevel ( ) != CodeGenOpt :: Aggressive ) return false ; if ( getFMAPatterns ( Root , Patterns , DoRegPressureReduce ) ) return true ; return TargetInstrInfo :: getMachineCombinerPatterns ( Root , Patterns , DoRegPressureReduce ) ; } </s>

Return true when there is potentially a faster code sequence for an instruction chain ending in Root .


<s> static void sparc_handle_vis_mul8x16 ( tree * n_elts , enum sparc_builtins fncode , tree inner_type , tree cst0 , tree cst1 ) { unsigned i , num = VECTOR_CST_NELTS ( cst0 ) ; int scale ; switch ( fncode ) { case SPARC_BUILTIN_FMUL8X16 : for ( i = 0 ; i < num ; ++ i ) { int val = sparc_vis_mul8x16 ( TREE_INT_CST_LOW ( VECTOR_CST_ELT ( cst0 , i ) ) , TREE_INT_CST_LOW ( VECTOR_CST_ELT ( cst1 , i ) ) ) ; n_elts [ i ] = build_int_cst ( inner_type , val ) ; } break ; case SPARC_BUILTIN_FMUL8X16AU : scale = TREE_INT_CST_LOW ( VECTOR_CST_ELT ( cst1 , 0 ) ) ; for ( i = 0 ; i < num ; ++ i ) { int val = sparc_vis_mul8x16 ( TREE_INT_CST_LOW ( VECTOR_CST_ELT ( cst0 , i ) ) , scale ) ; n_elts [ i ] = build_int_cst ( inner_type , val ) ; } break ; case SPARC_BUILTIN_FMUL8X16AL : scale = TREE_INT_CST_LOW ( VECTOR_CST_ELT ( cst1 , 1 ) ) ; for ( i = 0 ; i < num ; ++ i ) { int val = sparc_vis_mul8x16 ( TREE_INT_CST_LOW ( VECTOR_CST_ELT ( cst0 , i ) ) , scale ) ; n_elts [ i ] = build_int_cst ( inner_type , val ) ; } break ; default : gcc_unreachable ( ) ; } } </s>

Multiply the vector elements in ELTS0 to the elements in ELTS1 as specified by FNCODE . All of the elements in ELTS0 and ELTS1 lists must be integer constants . A tree list with the results of the multiplications is returned , and each element in the list is of INNER_TYPE .


<s>
int
AArch64LoadStoreOpt
::
getMemSize
(
MachineInstr
*
MemMI
)
{
switch
(
MemMI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Opcode has has unknown size!"
)
;
case
AArch64
::
STRSui
:
case
AArch64
::
STURSi
:
return
4
;
case
AArch64
::
STRDui
:
case
AArch64
::
STURDi
:
return
8
;
case
AArch64
::
STRQui
:
case
AArch64
::
STURQi
:
return
16
;
case
AArch64
::
STRWui
:
case
AArch64
::
STURWi
:
return
4
;
case
AArch64
::
STRXui
:
case
AArch64
::
STURXi
:
return
8
;
case
AArch64
::
LDRSui
:
case
AArch64
::
LDURSi
:
return
4
;
case
AArch64
::
LDRDui
:
case
AArch64
::
LDURDi
:
return
8
;
case
AArch64
::
LDRQui
:
case
AArch64
::
LDURQi
:
return
16
;
case
AArch64
::
LDRWui
:
case
AArch64
::
LDURWi
:
return
4
;
case
AArch64
::
LDRXui
:
case
AArch64
::
LDURXi
:
return
8
;
}
}
</s>

Returns the size in bytes of the memory access .


<s> bool X86FastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { const Value * Ptr = LI -> getPointerOperand ( ) ; X86AddressMode AM ; if ( ! X86SelectAddress ( Ptr , AM ) ) return false ; const X86InstrInfo & XII = ( const X86InstrInfo & ) TII ; unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; unsigned Alignment = LI -> getAlignment ( ) ; if ( Alignment == 0 ) Alignment = DL . getABITypeAlignment ( LI -> getType ( ) ) ; SmallVector < MachineOperand , 8 > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , MI , OpNo , AddrOps , FuncInfo . InsertPt , Size , Alignment , true ) ; if ( ! Result ) return false ; unsigned OperandNo = 0 ; for ( MachineInstr :: mop_iterator I = Result -> operands_begin ( ) , E = Result -> operands_end ( ) ; I != E ; ++ I , ++ OperandNo ) { MachineOperand & MO = * I ; if ( ! MO . isReg ( ) || MO . isDef ( ) || MO . getReg ( ) != AM . IndexReg ) continue ; unsigned IndexReg = constrainOperandRegClass ( Result -> getDesc ( ) , MO . getReg ( ) , OperandNo ) ; if ( IndexReg == MO . getReg ( ) ) continue ; MO . setReg ( IndexReg ) ; } Result -> addMemOperand ( * FuncInfo . MF , createMachineMemOperandFor ( LI ) ) ; MI -> eraseFromParent ( ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> static sbitmap aarch64_get_separate_components ( void ) { aarch64_layout_frame ( ) ; sbitmap components = sbitmap_alloc ( LAST_SAVED_REGNUM + 1 ) ; bitmap_clear ( components ) ; for ( unsigned regno = 0 ; regno <= LAST_SAVED_REGNUM ; regno ++ ) if ( aarch64_register_saved_on_entry ( regno ) ) { poly_int64 offset = cfun -> machine -> frame . reg_offset [ regno ] ; if ( ! frame_pointer_needed ) offset += cfun -> machine -> frame . frame_size - cfun -> machine -> frame . hard_fp_offset ; if ( offset_12bit_unsigned_scaled_p ( DImode , offset ) ) bitmap_set_bit ( components , regno ) ; } if ( frame_pointer_needed ) bitmap_clear_bit ( components , HARD_FRAME_POINTER_REGNUM ) ; unsigned reg1 = cfun -> machine -> frame . wb_candidate1 ; unsigned reg2 = cfun -> machine -> frame . wb_candidate2 ; if ( reg2 != INVALID_REGNUM ) bitmap_clear_bit ( components , reg2 ) ; if ( reg1 != INVALID_REGNUM ) bitmap_clear_bit ( components , reg1 ) ; bitmap_clear_bit ( components , LR_REGNUM ) ; bitmap_clear_bit ( components , SP_REGNUM ) ; return components ; } </s>


"Do not know how to return this many arguments!"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .