<s> static int try_constant_tricks ( HOST_WIDE_INT value , HOST_WIDE_INT * x , HOST_WIDE_INT * y ) { HOST_WIDE_INT i ; unsigned HOST_WIDE_INT bit , shf , rot ; if ( const_ok_for_mcore ( value ) ) return 1 ; if ( ! TARGET_HARDLIT ) return 0 ; if ( const_ok_for_mcore ( ~ value ) ) { * x = ~ value ; return 2 ; } for ( i = 1 ; i <= 32 ; i ++ ) { if ( const_ok_for_mcore ( value - i ) ) { * x = value - i ; * y = i ; return 3 ; } if ( const_ok_for_mcore ( value + i ) ) { * x = value + i ; * y = i ; return 4 ; } } bit = 0x80000000ULL ; for ( i = 0 ; i <= 31 ; i ++ ) { if ( const_ok_for_mcore ( i - value ) ) { * x = i - value ; * y = i ; return 5 ; } if ( const_ok_for_mcore ( value & ~ bit ) ) { * y = bit ; * x = value & ~ bit ; return 6 ; } if ( const_ok_for_mcore ( value | bit ) ) { * y = ~ bit ; * x = value | bit ; return 7 ; } bit >>= 1 ; } shf = value ; rot = value ; for ( i = 1 ; i < 31 ; i ++ ) { int c ; c = rot << 31 ; rot >>= 1 ; rot &= 0x7FFFFFFF ; rot |= c ; if ( const_ok_for_mcore ( rot ) ) { * y = i ; * x = rot ; return 8 ; } if ( shf & 1 ) shf = 0 ; shf >>= 1 ; if ( shf != 0 && const_ok_for_mcore ( shf ) ) { * y = i ; * x = shf ; return 9 ; } } if ( ( value % 3 ) == 0 && const_ok_for_mcore ( value / 3 ) ) { * x = value / 3 ; return 10 ; } if ( ( value % 5 ) == 0 && const_ok_for_mcore ( value / 5 ) ) { * x = value / 5 ; return 11 ; } return 0 ; } </s>

Try tricks to load a constant inline and return the trick number if success ( 0 is non-inlinable ) . 0 : not inlinable 1 : single instruction ( do the usual thing ) 2 : single insn followed by a 'not ' 3 : single insn followed by a subi 4 : single insn followed by an addi 5 : single insn followed by rsubi 6 : single insn followed by bseti 7 : single insn followed by bclri 8 : single insn followed by rotli 9 : single insn followed by lsli 10 : single insn followed by ixh 11 : single insn followed by ixw .


<s> const BitTracker :: RegisterCell & lookup ( unsigned VR ) { unsigned RInd = TargetRegisterInfo :: virtReg2Index ( VR ) ; if ( RInd >= CVect . size ( ) ) CVect . resize ( std :: max ( RInd + 16 , 32U ) , 0 ) ; const BitTracker :: RegisterCell * CP = CVect [ RInd ] ; if ( CP == 0 ) CP = CVect [ RInd ] = & BT . lookup ( VR ) ; return * CP ; } </s>

This method finds the value with the given Name in the the symbol table .


<s>
bool
CSKYConstantIslands
::
isBBInRange
(
MachineInstr
*
MI
,
MachineBasicBlock
*
DestBB
,
unsigned
MaxDisp
)
{
unsigned
BrOffset
=
getOffsetOf
(
MI
)
;
unsigned
DestOffset
=
BBInfo
[
DestBB
->
getNumber
(
)
]
.
Offset
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Branch of destination "
<<
printMBBReference
(
*
DestBB
)
<<
" from "
<<
printMBBReference
(
*
MI
->
getParent
(
)
)
<<
" max delta="
<<
MaxDisp
<<
" from "
<<
getOffsetOf
(
MI
)
<<
" to "
<<
DestOffset
<<
" offset "
<<
int
(
DestOffset
BrOffset
)
<<
"\t"
<<
*
MI
)
;
if
(
BrOffset
<=
DestOffset
)
{
if
(
DestOffset
BrOffset
<=
MaxDisp
)
return
true
;
}
else
{
if
(
BrOffset
DestOffset
<=
MaxDisp
)
return
true
;
}
return
false
;
}
</s>

isBBInRange - Returns true if the distance between specific MI and specific BB can fit in MI 's displacement field .

CSKY
CSKY
"Branch of destination "
" from "
" max delta="
" from "
" to "
" offset "
"\t"


<s> static inline int desc_is_active ( unsigned char qp , unw_word t , struct unw_state_record * sr ) { if ( sr -> when_target <= sr -> region_start + MIN ( ( int ) t , sr -> region_len - 1 ) ) return 0 ; if ( qp > 0 ) { if ( ( sr -> pr_val & ( 1UL << qp ) ) == 0 ) return 0 ; sr -> pr_mask |= ( 1UL << qp ) ; } return 1 ; } </s>


<s>
static
void
ATTRIBUTE_UNUSED
i386_output_dwarf_dtprel
(
FILE
*
file
,
int
size
,
rtx
x
)
{
fputs
(
ASM_LONG
,
file
)
;
output_addr_const
(
file
,
x
)
;
fputs
(
"@dtpoff"
,
file
)
;
switch
(
size
)
{
case
4
:
break
;
case
8
:
fputs
(
", 0"
,
file
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
</s>

This is called from dwarf2out.cc via TARGET_ASM_OUTPUT_DWARF_DTPREL . We need to emit DTP-relative relocations .


<s> virtual void registerRoots ( ) { } </s>

Notify this strategy that all roots have been released ( including those that depend on EntrySU or ExitSU ) .


"\n%s -G value = %d, Arch = %s, ISA = %d\n"


<s> int c4x_hard_regno_rename_ok ( unsigned int regno1 , unsigned int regno2 ) { if ( IS_FLOAT_CALL_SAVED_REGNO ( regno1 ) && IS_INT_CALL_SAVED_REGNO ( regno2 ) ) return 0 ; if ( IS_INT_CALL_SAVED_REGNO ( regno1 ) && IS_FLOAT_CALL_SAVED_REGNO ( regno2 ) ) return 0 ; if ( IS_EXT_REGNO ( regno1 ) && ! IS_EXT_REGNO ( regno2 ) ) return 0 ; if ( IS_EXT_REGNO ( regno2 ) && ! IS_EXT_REGNO ( regno1 ) ) return 0 ; return 1 ; } </s>

Return nonzero if REGNO1 can be renamed to REGNO2 .


<s> void SHUXIAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calling convention CallConv .


<s> rtx aarch64_pfalse_reg ( machine_mode mode ) { gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL ) ; rtx reg = force_reg ( VNx16BImode , CONST0_RTX ( VNx16BImode ) ) ; return gen_lowpart ( mode , reg ) ; } </s>

Return an all-false predicate register of mode MODE .


<s> void Cpu0AsmPrinter :: emitFrameDirective ( ) { const TargetRegisterInfo & RI = * TM . getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) -> getStackSize ( ) ; if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( "\t.frame\t$" + StringRef ( Cpu0InstPrinter :: getRegisterName ( stackReg ) ) . lower ( ) + "," + Twine ( stackSize ) + ",$" + StringRef ( Cpu0InstPrinter :: getRegisterName ( returnReg ) ) . lower ( ) ) ; } </s>


<s> static int mips_set_reg_reg_piece_cost ( machine_mode mode , unsigned int units ) { return COSTS_N_INSNS ( ( GET_MODE_SIZE ( mode ) + units - 1 ) / units ) ; } </s>

Return the cost of moving between two registers of mode MODE , assuming that the move will be in pieces of at most UNITS bytes .


<s>
bool
ARMAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
;
bool
PendConditionalInstruction
=
false
;
SmallVector
<
NearMissInfo
,
4
>
NearMisses
;
MatchResult
=
MatchInstruction
(
Operands
,
Inst
,
NearMisses
,
MatchingInlineAsm
,
PendConditionalInstruction
,
Out
)
;
switch
(
MatchResult
)
{
case
Match_Success
:
LLVM_DEBUG
(
dbgs
(
)
<<
"Parsed as: "
;
Inst
.
dump_pretty
(
dbgs
(
)
,
MII
.
getName
(
Inst
.
getOpcode
(
)
)
)
;
dbgs
(
)
<<
"\n"
)
;
if
(
validateInstruction
(
Inst
,
Operands
)
)
{
forwardITPosition
(
)
;
return
true
;
}
{
bool
wasInITBlock
=
inITBlock
(
)
;
while
(
processInstruction
(
Inst
,
Operands
,
Out
)
)
LLVM_DEBUG
(
dbgs
(
)
<<
"Changed to: "
;
Inst
.
dump_pretty
(
dbgs
(
)
,
MII
.
getName
(
Inst
.
getOpcode
(
)
)
)
;
dbgs
(
)
<<
"\n"
)
;
if
(
wasInITBlock
&&
hasV8Ops
(
)
&&
isThumb
(
)
&&
!
isV8EligibleForIT
(
&
Inst
)
)
{
Warning
(
IDLoc
,
"deprecated instruction in IT block"
)
;
}
}
forwardITPosition
(
)
;
if
(
Inst
.
getOpcode
(
)
==
ARM
::
ITasm
)
return
false
;
Inst
.
setLoc
(
IDLoc
)
;
if
(
PendConditionalInstruction
)
{
PendingConditionalInsts
.
push_back
(
Inst
)
;
if
(
isITBlockFull
(
)
||
isITBlockTerminator
(
Inst
)
)
flushPendingInstructions
(
Out
)
;
}
else
{
Out
.
EmitInstruction
(
Inst
,
getSTI
(
)
)
;
}
return
false
;
case
Match_NearMisses
:
ReportNearMisses
(
NearMisses
,
IDLoc
,
Operands
)
;
return
true
;
case
Match_MnemonicFail
:
{
uint64_t
FBS
=
ComputeAvailableFeatures
(
getSTI
(
)
.
getFeatureBits
(
)
)
;
std
::
string
Suggestion
=
ARMMnemonicSpellCheck
(
(
(
ARMOperand
&
)
*
Operands
[
0
]
)
.
getToken
(
)
,
FBS
)
;
return
Error
(
IDLoc
,
"invalid instruction"
+
Suggestion
,
(
(
ARMOperand
&
)
*
Operands
[
0
]
)
.
getLocRange
(
)
)
;
}
}
llvm_unreachable
(
"Implement any new match types added!"
)
;
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .

ARM
ARM
4
"Parsed as: "
"\n"
"Changed to: "
"\n"
"deprecated instruction in IT block"
ARM::ITasm
ARM
ARM
0
"invalid instruction"
ARM
0
"Implement any new match types added!"


<s> bool X86CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto DL = MF . getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned Idx = 0 ; for ( const auto & Arg : F . args ( ) ) { if ( Arg . hasAttribute ( Attribute :: ByVal ) || Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: Nest ) || VRegs [ Idx ] . size ( ) > 1 ) return false ; ArgInfo OrigArg ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArg , Idx + AttributeList :: FirstArgIndex , DL , F ) ; if ( ! splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < Register > Regs ) { MIRBuilder . buildMerge ( VRegs [ Idx ] [ 0 ] , Regs ) ; } ) ) return false ; Idx ++ ; } MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; FormalArgHandler Handler ( MIRBuilder , MRI , CC_X86 ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> unsigned WebAssemblyFastISel :: signExtend ( unsigned Reg , const Value * V , MVT :: SimpleValueType From , MVT :: SimpleValueType To ) { if ( To == MVT :: i64 ) { if ( From == MVT :: i64 ) return copyValue ( Reg ) ; Reg = signExtendToI32 ( Reg , V , From ) ; Register Result = createResultReg ( & WebAssembly :: I64RegClass ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( WebAssembly :: I64_EXTEND_S_I32 ) , Result ) . addReg ( Reg ) ; return Result ; } if ( To == MVT :: i32 ) return signExtendToI32 ( Reg , V , From ) ; return 0 ; } </s>

Return a new range in the specified integer type , which must be strictly larger than the current type .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
auto
RegName
=
[
]
(
unsigned
Reg
)
{
if
(
Reg
)
return
RISCVInstPrinter
::
getRegisterName
(
Reg
)
;
else
return
"noreg"
;
}
;
switch
(
Kind
)
{
case
KindTy
::
Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
KindTy
::
Register
:
OS
<<
"<register "
<<
RegName
(
getReg
(
)
)
<<
">"
;
break
;
case
KindTy
::
Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
case
KindTy
::
SystemRegister
:
OS
<<
"<sysreg: "
<<
getSysReg
(
)
<<
'>'
;
break
;
case
KindTy
::
VType
:
OS
<<
"<vtype: "
;
RISCVVType
::
printVType
(
getVType
(
)
,
OS
)
;
OS
<<
'>'
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

RI5CY
RISCV
"noreg"
"<register "
">"
"'"
"'"
"<sysreg: "
"<vtype: "
RISCV


<s> int mips_load_store_insns ( rtx mem , rtx_insn * insn ) { machine_mode mode ; bool might_split_p ; rtx set ; gcc_assert ( MEM_P ( mem ) ) ; mode = GET_MODE ( mem ) ; might_split_p = GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ; if ( might_split_p ) { set = single_set ( insn ) ; if ( set && ! mips_split_move_insn_p ( SET_DEST ( set ) , SET_SRC ( set ) , insn ) ) might_split_p = false ; } return mips_address_insns ( XEXP ( mem , 0 ) , mode , might_split_p ) ; } </s>

Return the number of instructions needed to implement INSN , given that it loads from or stores to MEM . Assume that BASE_INSN_LENGTH is the length of one instruction .


<s> virtual unsigned int execute ( function * fun ) { return rs6000_analyze_swaps ( fun ) ; } </s>


<s> static rtx frv_frame_offset_rtx ( int offset ) { rtx offset_rtx = GEN_INT ( offset ) ; if ( IN_RANGE ( offset , - 2048 , 2047 ) ) return offset_rtx ; else { rtx reg_rtx = gen_rtx_REG ( SImode , OFFSET_REGNO ) ; if ( IN_RANGE ( offset , - 32768 , 32767 ) ) emit_insn ( gen_movsi ( reg_rtx , offset_rtx ) ) ; else { emit_insn ( gen_movsi_high ( reg_rtx , offset_rtx ) ) ; emit_insn ( gen_movsi_lo_sum ( reg_rtx , offset_rtx ) ) ; } return reg_rtx ; } } </s>

Return an rtx with the value OFFSET , which will either be a register or a signed 12-bit integer . It can be used as the second operand in an `` add '' instruction , or as the index in a load or store . The function returns a constant rtx if OFFSET is small enough , otherwise it loads the constant into register OFFSET_REGNO and returns that .


<s> void ix86_expand_push ( enum machine_mode mode , rtx x ) { rtx tmp ; tmp = expand_simple_binop ( Pmode , PLUS , stack_pointer_rtx , GEN_INT ( - GET_MODE_SIZE ( mode ) ) , stack_pointer_rtx , 1 , OPTAB_DIRECT ) ; if ( tmp != stack_pointer_rtx ) emit_move_insn ( stack_pointer_rtx , tmp ) ; tmp = gen_rtx_MEM ( mode , stack_pointer_rtx ) ; emit_move_insn ( tmp , x ) ; } </s>

Expand a push in MODE . This is some mode for which we do not support proper push instructions , at least from the registers that we expect the value to live in .


<s> BitVector MMIXRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , MMIX :: r254 ) ; markSuperRegs ( Reserved , MMIX :: r253 ) ; markSuperRegs ( Reserved , MMIX :: r252 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void LanaiFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const LanaiRegisterInfo * LRI = STI . getRegisterInfo ( ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned StackAlign = LRI -> needsStackRealignment ( MF ) ? MFI -> getMaxAlignment ( ) : getStackAlignment ( ) ; unsigned MaxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; if ( MFI -> hasVarSizedObjects ( ) ) MaxCallFrameSize = alignTo ( MaxCallFrameSize , StackAlign ) ; MFI -> setMaxCallFrameSize ( MaxCallFrameSize ) ; if ( ! ( hasReservedCallFrame ( MF ) && MFI -> adjustsStack ( ) ) ) FrameSize += MaxCallFrameSize ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI -> setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s> bool isDesirableToTransformToIntegerOp ( unsigned Opc , EVT VT ) const override { if ( Opc != ISD :: LOAD && Opc != ISD :: STORE ) return false ; if ( VT != MVT :: f32 && VT != MVT :: f64 ) return false ; return true ; } </s>

Return true if it is profitable for dag combiner to transform a floating point op of specified opcode to a equivalent op of an integer type .


<s>
void
Hexagon_CCState
::
AnalyzeCallResult
(
EVT
VT
,
Hexagon_CCAssignFn
Fn
)
{
if
(
Fn
(
0
,
VT
,
VT
,
CCValAssign
::
Full
,
ISD
::
ArgFlagsTy
(
)
,
*
this
,
1
,
1
,
false
)
)
{
dbgs
(
)
<<
"Call result has unhandled type "
<<
VT
.
getEVTString
(
)
<<
"\n"
;
abort
(
)
;
}
}
</s>

AnalyzeCallResult - Same as above except it 's specialized for calls which produce a single value .

Hexagon
Hexagon
Hexagon
0
ISD::ArgFlagsTy
1
1
"Call result has unhandled type "
"\n"


<s> bool small_data_operand ( rtx op , machine_mode mode ATTRIBUTE_UNUSED ) { if ( ! TARGET_SDATA_USE ) return 0 ; if ( GET_CODE ( op ) == SYMBOL_REF ) return SYMBOL_REF_SMALL_P ( op ) ; if ( GET_CODE ( op ) == CONST && GET_CODE ( XEXP ( op , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( op , 0 ) , 0 ) ) == SYMBOL_REF && satisfies_constraint_J ( XEXP ( XEXP ( op , 0 ) , 1 ) ) ) return SYMBOL_REF_SMALL_P ( XEXP ( XEXP ( op , 0 ) , 0 ) ) ; return 0 ; } </s>

Return 1 for an operand in small memory on V.4/eabi .


<s> bool GCNPassConfig :: addIRTranslator ( ) { addPass ( new IRTranslator ( ) ) ; return false ; } </s>

This method should install an IR translator pass , which converts from LLVM code to machine instructions with possibly generic opcodes .


<s> static rtx nvptx_function_arg ( cumulative_args_t , machine_mode mode , const_tree , bool named ) { if ( mode == VOIDmode ) return NULL_RTX ; if ( named ) return gen_reg_rtx ( mode ) ; return NULL_RTX ; } </s>


<s> bool CSKYFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool loongarch_global_symbol_p ( const_rtx x ) { if ( LABEL_REF_P ( x ) ) return false ; const_tree decl = SYMBOL_REF_DECL ( x ) ; if ( ! decl ) return ! SYMBOL_REF_LOCAL_P ( x ) || SYMBOL_REF_EXTERNAL_P ( x ) ; return DECL_P ( decl ) && ( TREE_PUBLIC ( decl ) || DECL_WEAK ( decl ) ) ; } </s>

Return true if SYMBOL_REF X is associated with a global symbol ( in the STB_GLOBAL sense ) .


<s> bool ix86_standard_x87sse_constant_load_p ( const rtx_insn * insn , rtx dst ) { rtx src = find_constant_src ( insn ) ; gcc_assert ( REG_P ( dst ) ) ; if ( src == NULL || ( SSE_REGNO_P ( REGNO ( dst ) ) && standard_sse_constant_p ( src , GET_MODE ( dst ) ) != 1 ) || ( STACK_REGNO_P ( REGNO ( dst ) ) && standard_80387_constant_p ( src ) < 1 ) ) return false ; return true ; } </s>

Returns true if INSN can be transformed from a memory load to a supported FP constant load .


<s> TargetLowering :: ConstraintType TPCTargetLowering :: getConstraintType ( StringRef Constraint ) const { unsigned S = Constraint . size ( ) ; if ( S == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 's' : case 'v' : case 'S' : case 'V' : return C_RegisterClass ; case 'g' : case 'l' : case 'L' : return C_Memory ; } } if ( S > 1 && Constraint [ 0 ] == '{' && Constraint [ S - 1 ] == '}' ) { if ( S == 8 && Constraint . substr ( 1 , 6 ) == "memory" ) return C_Memory ; return C_Register ; } return C_Unknown ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> bool HexagonInstrInfo :: isExtended ( const MachineInstr & MI ) const { const uint64_t F = MI . getDesc ( ) . TSFlags ; if ( ( F >> HexagonII :: ExtendedPos ) & HexagonII :: ExtendedMask ) return true ; for ( MachineInstr :: const_mop_iterator I = MI . operands_begin ( ) , E = MI . operands_end ( ) ; I != E ; ++ I ) { if ( I -> getTargetFlags ( ) && HexagonII :: HMOTF_ConstExtended ) return true ; } return false ; } </s>

Test if the given EVT is extended ( as opposed to being simple ) .

Hexagon Hexagon HexagonII::ExtendedPos HexagonII::ExtendedMask HexagonII::HMOTF_ConstExtended


<s>
ArrayRef
<
MCPhysReg
>
MipsABIInfo
::
GetByValArgRegs
(
)
const
{
if
(
IsO32
(
)
)
return
makeArrayRef
(
O32IntRegs
)
;
if
(
IsN32
(
)
||
IsN64
(
)
)
return
makeArrayRef
(
Mips64IntRegs
)
;
llvm_unreachable
(
"Unhandled ABI"
)
;
}
</s>

The registers to use for byval arguments .


<s> bool compact_sda_memory_operand ( rtx op , machine_mode mode , bool short_p ) { rtx addr ; int size ; int align = 0 ; int mask = 0 ; if ( GET_CODE ( op ) != MEM ) return false ; if ( mode == VOIDmode ) mode = GET_MODE ( op ) ; size = GET_MODE_SIZE ( mode ) ; if ( size > UNITS_PER_WORD ) return false ; addr = XEXP ( op , 0 ) ; if ( ! legitimate_small_data_address_p ( addr ) ) return false ; if ( ! short_p || size == 1 ) return true ; align = get_symbol_alignment ( addr ) ; switch ( mode ) { case E_HImode : mask = 1 ; break ; default : mask = 3 ; break ; } if ( align && ( ( align & mask ) == 0 ) ) return true ; return false ; } </s>

volatile cache option still to be handled .


<s> BitVector CJGRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( CJG :: SR ) ; Reserved . set ( CJG :: PC ) ; Reserved . set ( CJG :: SP ) ; return Reserved ; } </s>


<s> bool ARMTargetLowering :: isVectorLoadExtDesirable ( SDValue ExtVal ) const { EVT VT = ExtVal . getValueType ( ) ; if ( ! isTypeLegal ( VT ) ) return false ; if ( auto * Ld = dyn_cast < MaskedLoadSDNode > ( ExtVal . getOperand ( 0 ) ) ) { if ( Ld -> isExpandingLoad ( ) ) return false ; } if ( ExtVal -> use_empty ( ) || ! ExtVal -> use_begin ( ) -> isOnlyUserOf ( ExtVal . getNode ( ) ) ) return true ; SDNode * U = * ExtVal -> use_begin ( ) ; if ( ( U -> getOpcode ( ) == ISD :: ADD || U -> getOpcode ( ) == ISD :: SUB || U -> getOpcode ( ) == ISD :: SHL || U -> getOpcode ( ) == ARMISD :: VSHLIMM ) ) return false ; return true ; } </s>

Return true if folding a vector load into ExtVal ( a sign , zero , or any extend node ) is profitable .

ARM ARM 0 ISD::ADD ISD::SUB ISD::SHL ARMISD::VSHLIMM


<s> bool SIMemoryLegalizer :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; SIMemOpAccess MOA ( MF ) ; CC = SICacheControl :: create ( MF . getSubtarget < GCNSubtarget > ( ) ) ; for ( auto & MBB : MF ) { for ( auto MI = MBB . begin ( ) ; MI != MBB . end ( ) ; ++ MI ) { if ( MI -> isBundle ( ) && MI -> mayLoadOrStore ( ) ) { MachineBasicBlock :: instr_iterator II ( MI -> getIterator ( ) ) ; for ( MachineBasicBlock :: instr_iterator I = ++ II , E = MBB . instr_end ( ) ; I != E && I -> isBundledWithPred ( ) ; ++ I ) { I -> unbundleFromPred ( ) ; for ( MachineOperand & MO : I -> operands ( ) ) if ( MO . isReg ( ) ) MO . setIsInternalRead ( false ) ; } MI -> eraseFromParent ( ) ; MI = II -> getIterator ( ) ; } if ( ! ( MI -> getDesc ( ) . TSFlags & SIInstrFlags :: maybeAtomic ) ) continue ; if ( const auto & MOI = MOA . getLoadInfo ( MI ) ) Changed |= expandLoad ( MOI . getValue ( ) , MI ) ; else if ( const auto & MOI = MOA . getStoreInfo ( MI ) ) Changed |= expandStore ( MOI . getValue ( ) , MI ) ; else if ( const auto & MOI = MOA . getAtomicFenceInfo ( MI ) ) Changed |= expandAtomicFence ( MOI . getValue ( ) , MI ) ; else if ( const auto & MOI = MOA . getAtomicCmpxchgOrRmwInfo ( MI ) ) Changed |= expandAtomicCmpxchgOrRmw ( MOI . getValue ( ) , MI ) ; } } Changed |= removeAtomicPseudoMIs ( ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .

AMDGPU SI SI SI SIInstrFlags::maybeAtomic


<s> TargetPassConfig * F2003fTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new F2003fPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> bool X86TargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , unsigned Intrinsic ) const { const IntrinsicData * IntrData = getIntrinsicWithChain ( Intrinsic ) ; if ( ! IntrData ) return false ; Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . readMem = false ; Info . writeMem = false ; Info . vol = false ; Info . offset = 0 ; switch ( IntrData -> Type ) { case EXPAND_FROM_MEM : { Info . ptrVal = I . getArgOperand ( 0 ) ; Info . memVT = MVT :: getVT ( I . getType ( ) ) ; Info . align = 1 ; Info . readMem = true ; break ; } case COMPRESS_TO_MEM : { Info . ptrVal = I . getArgOperand ( 0 ) ; Info . memVT = MVT :: getVT ( I . getArgOperand ( 1 ) -> getType ( ) ) ; Info . align = 1 ; Info . writeMem = true ; break ; } case TRUNCATE_TO_MEM_VI8 : case TRUNCATE_TO_MEM_VI16 : case TRUNCATE_TO_MEM_VI32 : { Info . ptrVal = I . getArgOperand ( 0 ) ; MVT VT = MVT :: getVT ( I . getArgOperand ( 1 ) -> getType ( ) ) ; MVT ScalarVT = MVT :: INVALID_SIMPLE_VALUE_TYPE ; if ( IntrData -> Type == TRUNCATE_TO_MEM_VI8 ) ScalarVT = MVT :: i8 ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI16 ) ScalarVT = MVT :: i16 ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI32 ) ScalarVT = MVT :: i32 ; Info . memVT = MVT :: getVectorVT ( ScalarVT , VT . getVectorNumElements ( ) ) ; Info . align = 1 ; Info . writeMem = true ; break ; } case STOREANT : { Info . ptrVal = I . getArgOperand ( 0 ) ; Info . memVT = MVT :: getVT ( I . getArgOperand ( 1 ) -> getType ( ) ) ; Info . align = Info . memVT . getSizeInBits ( ) / 8 ; Info . writeMem = true ; break ; } default : return false ; } return true ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> static enum sched_fusion_type fusion_load_store ( rtx_insn * insn , rtx * base , rtx * offset ) { rtx x , dest , src ; enum sched_fusion_type fusion = SCHED_FUSION_LD ; gcc_assert ( INSN_P ( insn ) ) ; x = PATTERN ( insn ) ; if ( GET_CODE ( x ) != SET ) return SCHED_FUSION_NONE ; src = SET_SRC ( x ) ; dest = SET_DEST ( x ) ; machine_mode dest_mode = GET_MODE ( dest ) ; if ( ! aarch64_mode_valid_for_sched_fusion_p ( dest_mode ) ) return SCHED_FUSION_NONE ; if ( GET_CODE ( src ) == SIGN_EXTEND ) { fusion = SCHED_FUSION_LD_SIGN_EXTEND ; src = XEXP ( src , 0 ) ; if ( ! MEM_P ( src ) || GET_MODE ( src ) != SImode ) return SCHED_FUSION_NONE ; } else if ( GET_CODE ( src ) == ZERO_EXTEND ) { fusion = SCHED_FUSION_LD_ZERO_EXTEND ; src = XEXP ( src , 0 ) ; if ( ! MEM_P ( src ) || GET_MODE ( src ) != SImode ) return SCHED_FUSION_NONE ; } if ( MEM_P ( src ) && REG_P ( dest ) ) extract_base_offset_in_addr ( src , base , offset ) ; else if ( MEM_P ( dest ) && ( REG_P ( src ) || src == const0_rtx ) ) { fusion = SCHED_FUSION_ST ; extract_base_offset_in_addr ( dest , base , offset ) ; } else return SCHED_FUSION_NONE ; if ( * base == NULL_RTX || * offset == NULL_RTX ) fusion = SCHED_FUSION_NONE ; return fusion ; } </s>

If INSN is a load or store of address in the form of [ base+offset ] , extract the two parts and set to BASE and OFFSET . IS_LOAD is set to TRUE if it 's a load . Return TRUE if INSN is such an instruction , otherwise return FALSE .


<s> int h8300_shift_needs_scratch_p ( int count , enum machine_mode mode ) { enum h8_cpu cpu ; int a , lr , ar ; if ( GET_MODE_BITSIZE ( mode ) <= count ) return 1 ; if ( TARGET_H8300 ) cpu = H8_300 ; else if ( TARGET_H8300H ) cpu = H8_300H ; else cpu = H8_S ; switch ( mode ) { case QImode : a = shift_alg_qi [ cpu ] [ SHIFT_ASHIFT ] [ count ] ; lr = shift_alg_qi [ cpu ] [ SHIFT_LSHIFTRT ] [ count ] ; ar = shift_alg_qi [ cpu ] [ SHIFT_ASHIFTRT ] [ count ] ; break ; case HImode : a = shift_alg_hi [ cpu ] [ SHIFT_ASHIFT ] [ count ] ; lr = shift_alg_hi [ cpu ] [ SHIFT_LSHIFTRT ] [ count ] ; ar = shift_alg_hi [ cpu ] [ SHIFT_ASHIFTRT ] [ count ] ; break ; case SImode : a = shift_alg_si [ cpu ] [ SHIFT_ASHIFT ] [ count ] ; lr = shift_alg_si [ cpu ] [ SHIFT_LSHIFTRT ] [ count ] ; ar = shift_alg_si [ cpu ] [ SHIFT_ASHIFTRT ] [ count ] ; break ; default : gcc_unreachable ( ) ; } return ( a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP || ( TARGET_H8300H && mode == SImode && count == 8 ) ) ; } </s>

Given COUNT and MODE of a shift , return 1 if a scratch reg may be needed for some shift with COUNT and MODE . Return 0 otherwise .


<s>
unsigned
SystemZInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
!
I
->
isBranch
(
)
)
break
;
if
(
!
getBranchInfo
(
*
I
)
.
Target
->
isMBB
(
)
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .

SystemZ
SystemZ
"code size not handled"
0


<s> bool ARMGlobalMerge :: runOnFunction ( Function & F ) { return false ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s>
const
MCPhysReg
*
X86RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
const
X86Subtarget
&
Subtarget
=
MF
->
getSubtarget
<
X86Subtarget
>
(
)
;
bool
HasSSE
=
Subtarget
.
hasSSE1
(
)
;
bool
HasAVX
=
Subtarget
.
hasAVX
(
)
;
bool
HasAVX512
=
Subtarget
.
hasAVX512
(
)
;
bool
CallsEHReturn
=
MF
->
getMMI
(
)
.
callsEHReturn
(
)
;
assert
(
MF
&&
"MachineFunction required"
)
;
switch
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
)
{
case
CallingConv
::
GHC
:
case
CallingConv
::
HiPE
:
return
CSR_NoRegs_SaveList
;
case
CallingConv
::
AnyReg
:
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
return
CSR_64_AllRegs_SaveList
;
case
CallingConv
::
PreserveMost
:
return
CSR_64_RT_MostRegs_SaveList
;
case
CallingConv
::
PreserveAll
:
if
(
HasAVX
)
return
CSR_64_RT_AllRegs_AVX_SaveList
;
return
CSR_64_RT_AllRegs_SaveList
;
case
CallingConv
::
CXX_FAST_TLS
:
if
(
Is64Bit
)
return
MF
->
getInfo
<
X86MachineFunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_64_CXX_TLS_Darwin_PE_SaveList
:
CSR_64_TLS_Darwin_SaveList
;
break
;
case
CallingConv
::
Intel_OCL_BI
:
{
if
(
HasAVX512
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX512
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX_SaveList
;
if
(
HasAVX
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX_SaveList
;
if
(
!
HasAVX
&&
!
IsWin64
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_SaveList
;
break
;
}
case
CallingConv
::
HHVM
:
return
CSR_64_HHVM_SaveList
;
case
CallingConv
::
Cold
:
if
(
Is64Bit
)
return
CSR_64_MostRegs_SaveList
;
break
;
case
CallingConv
::
X86_64_Win64
:
return
CSR_Win64_SaveList
;
case
CallingConv
::
X86_64_SysV
:
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
case
CallingConv
::
X86_INTR
:
if
(
Is64Bit
)
{
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
else
return
CSR_64_AllRegs_SaveList
;
}
else
{
if
(
HasSSE
)
return
CSR_32_AllRegs_SSE_SaveList
;
else
return
CSR_32_AllRegs_SaveList
;
}
default
:
break
;
}
if
(
Is64Bit
)
{
if
(
IsWin64
)
return
CSR_Win64_SaveList
;
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
}
if
(
CallsEHReturn
)
return
CSR_32EHRet_SaveList
;
return
CSR_32_SaveList
;
}
</s>


<s> void Z80DAGToDAGISel :: Select ( SDNode * Node ) { SelectCode ( Node ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> static void tilegx_conditional_register_usage ( void ) { global_regs [ TILEGX_NETORDER_REGNUM ] = 1 ; if ( TILEGX_PIC_TEXT_LABEL_REGNUM != INVALID_REGNUM ) fixed_regs [ TILEGX_PIC_TEXT_LABEL_REGNUM ] = 1 ; if ( PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM ) fixed_regs [ PIC_OFFSET_TABLE_REGNUM ] = 1 ; } </s>


<s> void BTFDebug :: beginInstruction ( const MachineInstr * MI ) { DebugHandlerBase :: beginInstruction ( MI ) ; if ( SkipInstruction || MI -> isMetaInstruction ( ) || MI -> getFlag ( MachineInstr :: FrameSetup ) ) return ; if ( MI -> isInlineAsm ( ) ) { unsigned NumDefs = 0 ; for ( ; MI -> getOperand ( NumDefs ) . isReg ( ) && MI -> getOperand ( NumDefs ) . isDef ( ) ; ++ NumDefs ) ; const char * AsmStr = MI -> getOperand ( NumDefs ) . getSymbolName ( ) ; if ( AsmStr [ 0 ] == 0 ) return ; } if ( MI -> getOpcode ( ) == BPF :: LD_imm64 ) processLDimm64 ( MI ) ; const DebugLoc & DL = MI -> getDebugLoc ( ) ; if ( ! DL || PrevInstLoc == DL ) { if ( LineInfoGenerated == false ) { auto * S = MI -> getMF ( ) -> getFunction ( ) . getSubprogram ( ) ; MCSymbol * FuncLabel = Asm -> getFunctionBegin ( ) ; constructLineInfo ( S , FuncLabel , S -> getLine ( ) , 0 ) ; LineInfoGenerated = true ; } return ; } MCSymbol * LineSym = OS . getContext ( ) . createTempSymbol ( ) ; OS . EmitLabel ( LineSym ) ; auto SP = DL . get ( ) -> getScope ( ) -> getSubprogram ( ) ; constructLineInfo ( SP , LineSym , DL . getLine ( ) , DL . getCol ( ) ) ; LineInfoGenerated = true ; PrevInstLoc = DL ; } </s>


<s> bool RISCVInstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF , bool OutlineFromLinkOnceODRs ) const { const Function & F = MF . getFunction ( ) ; if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) ) return false ; if ( F . hasSection ( ) ) return false ; return true ; } </s>

Return true if the function can safely be outlined from .


<s>
SUnit
*
ConvergingVLIWScheduler
::
pickNodeBidrectional
(
bool
&
IsTopNode
)
{
if
(
SUnit
*
SU
=
Bot
.
pickOnlyChoice
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Picked only Bottom\n"
)
;
IsTopNode
=
false
;
return
SU
;
}
if
(
SUnit
*
SU
=
Top
.
pickOnlyChoice
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Picked only Top\n"
)
;
IsTopNode
=
true
;
return
SU
;
}
SchedCandidate
BotCand
;
CandResult
BotResult
=
pickNodeFromQueue
(
Bot
,
DAG
->
getBotRPTracker
(
)
,
BotCand
)
;
assert
(
BotResult
!=
NoCand
&&
"failed to find the first candidate"
)
;
if
(
BotResult
==
SingleExcess
||
BotResult
==
SingleCritical
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Prefered Bottom Node\n"
)
;
IsTopNode
=
false
;
return
BotCand
.
SU
;
}
SchedCandidate
TopCand
;
CandResult
TopResult
=
pickNodeFromQueue
(
Top
,
DAG
->
getTopRPTracker
(
)
,
TopCand
)
;
assert
(
TopResult
!=
NoCand
&&
"failed to find the first candidate"
)
;
if
(
TopResult
==
SingleExcess
||
TopResult
==
SingleCritical
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Prefered Top Node\n"
)
;
IsTopNode
=
true
;
return
TopCand
.
SU
;
}
if
(
BotResult
==
SingleMax
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Prefered Bottom Node SingleMax\n"
)
;
IsTopNode
=
false
;
return
BotCand
.
SU
;
}
if
(
TopResult
==
SingleMax
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Prefered Top Node SingleMax\n"
)
;
IsTopNode
=
true
;
return
TopCand
.
SU
;
}
if
(
TopCand
.
SCost
>
BotCand
.
SCost
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Prefered Top Node Cost\n"
)
;
IsTopNode
=
true
;
return
TopCand
.
SU
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Prefered Bottom in Node order\n"
)
;
IsTopNode
=
false
;
return
BotCand
.
SU
;
}
</s>

Pick the best candidate node from either the top or bottom queue .

Hexagon
"Picked only Bottom\n"
"Picked only Top\n"
"failed to find the first candidate"
"Prefered Bottom Node\n"
"failed to find the first candidate"
"Prefered Top Node\n"
"Prefered Bottom Node SingleMax\n"
"Prefered Top Node SingleMax\n"
"Prefered Top Node Cost\n"
"Prefered Bottom in Node order\n"


<s> bool SIRemoveShortExecBranches :: runOnMachineFunction ( MachineFunction & MF ) { const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; MF . RenumberBlocks ( ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; if ( MBBI == MBB . end ( ) ) continue ; MachineInstr & MI = * MBBI ; switch ( MI . getOpcode ( ) ) { case AMDGPU :: S_CBRANCH_EXECZ : Changed = removeExeczBranch ( MI , MBB ) ; break ; default : break ; } } return Changed ; } </s>


<s>
virtual
llvm
::
StringRef
getPassName
(
)
const
{
return
"Add implicit SYCL global offset"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool can_be_rotated_to_positive_16bits ( HOST_WIDE_INT c ) { int rot = 0 ; bool res = can_be_rotated_to_lowbits ( c , 16 , & rot ) ; return res && rot > 0 ; } </s>

Check if C ( as 64bit integer ) can be rotated to a positive 16bits constant which contains 48bits leading zeros and 16bits of any value .


Return the bytes needed to compute the frame pointer from the current stack pointer . SIZE is the size needed for local variables .


"Function has local memory argument.  Promoting to "


<s> bool AMDGPUAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( AMDGPU :: IsaInfo :: hasCodeObjectV3 ( & getSTI ( ) ) ) { if ( IDVal == ".amdgcn_target" ) return ParseDirectiveAMDGCNTarget ( ) ; if ( IDVal == ".amdhsa_kernel" ) return ParseDirectiveAMDHSAKernel ( ) ; } else { if ( IDVal == ".hsa_code_object_version" ) return ParseDirectiveHSACodeObjectVersion ( ) ; if ( IDVal == ".hsa_code_object_isa" ) return ParseDirectiveHSACodeObjectISA ( ) ; if ( IDVal == ".amd_kernel_code_t" ) return ParseDirectiveAMDKernelCodeT ( ) ; if ( IDVal == ".amdgpu_hsa_kernel" ) return ParseDirectiveAMDGPUHsaKernel ( ) ; if ( IDVal == ".amd_amdgpu_isa" ) return ParseDirectiveISAVersion ( ) ; } if ( IDVal == AMDGPU :: HSAMD :: AssemblerDirectiveBegin ) return ParseDirectiveHSAMetadata ( ) ; if ( IDVal == PALMD :: AssemblerDirective ) return ParseDirectivePALMetadata ( ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s>
MachineBasicBlock
::
iterator
MCS51FrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
)
const
{
const
MCS51Subtarget
&
STI
=
MF
.
getSubtarget
<
MCS51Subtarget
>
(
)
;
const
MCS51InstrInfo
&
TII
=
*
STI
.
getInstrInfo
(
)
;
if
(
hasReservedCallFrame
(
MF
)
)
{
fixStackStores
(
MBB
,
MI
,
TII
,
MCS51
::
R29R28
)
;
return
MBB
.
erase
(
MI
)
;
}
DebugLoc
DL
=
MI
->
getDebugLoc
(
)
;
unsigned
int
Opcode
=
MI
->
getOpcode
(
)
;
int
Amount
=
TII
.
getFrameSize
(
*
MI
)
;
if
(
Amount
!=
0
)
{
assert
(
getStackAlign
(
)
==
Align
(
1
)
&&
"Unsupported stack alignment"
)
;
if
(
Opcode
==
TII
.
getCallFrameSetupOpcode
(
)
)
{
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
MCS51
::
SPREAD
)
,
MCS51
::
R31R30
)
.
addReg
(
MCS51
::
SP
)
;
MachineInstr
*
New
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
MCS51
::
SUBIWRdK
)
,
MCS51
::
R31R30
)
.
addReg
(
MCS51
::
R31R30
,
RegState
::
Kill
)
.
addImm
(
Amount
)
;
New
->
getOperand
(
3
)
.
setIsDead
(
)
;
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
MCS51
::
SPWRITE
)
,
MCS51
::
SP
)
.
addReg
(
MCS51
::
R31R30
)
;
fixStackStores
(
MBB
,
MI
,
TII
,
MCS51
::
R31R30
)
;
}
else
{
assert
(
Opcode
==
TII
.
getCallFrameDestroyOpcode
(
)
)
;
unsigned
addOpcode
;
if
(
isUInt
<
6
>
(
Amount
)
)
{
addOpcode
=
MCS51
::
ADIWRdK
;
}
else
{
addOpcode
=
MCS51
::
SUBIWRdK
;
Amount
=
Amount
;
}
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
MCS51
::
SPREAD
)
,
MCS51
::
R31R30
)
.
addReg
(
MCS51
::
SP
)
;
MachineInstr
*
New
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
addOpcode
)
,
MCS51
::
R31R30
)
.
addReg
(
MCS51
::
R31R30
,
RegState
::
Kill
)
.
addImm
(
Amount
)
;
New
->
getOperand
(
3
)
.
setIsDead
(
)
;
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
MCS51
::
SPWRITE
)
,
MCS51
::
SP
)
.
addReg
(
MCS51
::
R31R30
,
RegState
::
Kill
)
;
}
}
return
MBB
.
erase
(
MI
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool MipsPassConfig :: addIRTranslator ( ) { addPass ( new IRTranslator ( getOptLevel ( ) ) ) ; return false ; } </s>

This method should install an IR translator pass , which converts from LLVM code to machine instructions with possibly generic opcodes .


<s>
MachineBasicBlock
::
iterator
SIFrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
int64_t
Amount
=
I
->
getOperand
(
0
)
.
getImm
(
)
;
if
(
Amount
==
0
)
return
MBB
.
erase
(
I
)
;
const
GCNSubtarget
&
ST
=
MF
.
getSubtarget
<
GCNSubtarget
>
(
)
;
const
SIInstrInfo
*
TII
=
ST
.
getInstrInfo
(
)
;
const
DebugLoc
&
DL
=
I
->
getDebugLoc
(
)
;
unsigned
Opc
=
I
->
getOpcode
(
)
;
bool
IsDestroy
=
Opc
==
TII
->
getCallFrameDestroyOpcode
(
)
;
uint64_t
CalleePopAmount
=
IsDestroy
I
->
getOperand
(
1
)
.
getImm
(
)
:
0
;
if
(
!
hasReservedCallFrame
(
MF
)
)
{
Amount
=
alignTo
(
Amount
,
getStackAlign
(
)
)
;
assert
(
isUInt
<
32
>
(
Amount
)
&&
"exceeded stack address space size"
)
;
const
SIMachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
SIMachineFunctionInfo
>
(
)
;
unsigned
SPReg
=
MFI
->
getStackPtrOffsetReg
(
)
;
unsigned
Op
=
IsDestroy
AMDGPU
::
S_SUB_U32
:
AMDGPU
::
S_ADD_U32
;
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
Op
)
,
SPReg
)
.
addReg
(
SPReg
)
.
addImm
(
Amount
*
ST
.
getWavefrontSize
(
)
)
;
}
else
if
(
CalleePopAmount
!=
0
)
{
llvm_unreachable
(
"is this used?"
)
;
}
return
MBB
.
erase
(
I
)
;
}
</s>


<s> static void ready_reorder ( rtx * ready , int nready ) { SCHED_REORDER ( ready , nready ) ; } </s>

Sort the ready list READY by ascending priority , using the SCHED_REORDER macro .


"Missing call preserved mask for calling convention"

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


<s> SMLoc getEndLoc ( ) const override { return End ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> static bool or1k_pass_by_reference ( cumulative_args_t , machine_mode mode , const_tree type , bool ) { HOST_WIDE_INT size ; if ( type ) { if ( AGGREGATE_TYPE_P ( type ) ) return true ; size = int_size_in_bytes ( type ) ; } else size = GET_MODE_SIZE ( mode ) ; return size < 0 || size > 8 ; } </s>

Worker for TARGET_PASS_BY_REFERENCE . Returns true if an argument of TYPE in MODE should be passed by reference as required by the OpenRISC ABI . On OpenRISC structures , unions and arguments larger than 64-bits are passed by reference .


<s> rtx m68k_legitimize_call_address ( rtx x ) { gcc_assert ( MEM_P ( x ) ) ; if ( call_operand ( XEXP ( x , 0 ) , VOIDmode ) ) return x ; return replace_equiv_address ( x , force_reg ( Pmode , XEXP ( x , 0 ) ) ) ; } </s>

Convert X to a legitimate function call memory reference and return the result .


<s> int arc_verify_short ( rtx_insn * insn , int , int check_attr ) { enum attr_iscompact iscompact ; struct machine_function * machine ; if ( check_attr > 0 ) { iscompact = get_attr_iscompact ( insn ) ; if ( iscompact == ISCOMPACT_FALSE ) return 0 ; } machine = cfun -> machine ; if ( machine -> force_short_suffix >= 0 ) return machine -> force_short_suffix ; return ( get_attr_length ( insn ) & 2 ) != 0 ; } </s>

Return non-zero if INSN should be output as a short insn . UNALIGN is zero if the current insn is aligned to a 4-byte-boundary , two otherwise . If CHECK_ATTR is greater than 0 , check the iscompact attribute first .


<s> void aarch64_d_target_versions ( void ) { d_add_builtin_version ( "AArch64" ) ; d_add_builtin_version ( "D_HardFloat" ) ; } </s>

Implement TARGET_D_CPU_VERSIONS for AArch64 targets .


"%<bank_switch%> has no effect on non-interrupt functions"

Emits the prologue . See the frame layout comment earlier in this file . We can reserve up to 256 bytes with the ENTER opcode , beyond that we manually update sp .


<s> void X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { bool reserveCallFrame = hasReservedCallFrame ( MF ) ; unsigned Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t InternalAmt = ( isDestroy || Amount ) ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { unsigned StackAlign = getStackAlignment ( ) ; Amount = RoundUpToAlignment ( Amount , StackAlign ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const Function * Fn = MF . getFunction ( ) ; bool WindowsCFI = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool DwarfCFI = ! WindowsCFI && ( MMI . hasDebugInfo ( ) || Fn -> needsUnwindTableEntry ( ) ) ; bool HasDwarfEHHandlers = ! WindowsCFI && ! MF . getMMI ( ) . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < X86MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , I , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == 0 ) return ; Amount -= InternalAmt ; if ( isDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) && MMI . usePreciseUnwindInfo ( ) ) BuildCFI ( MBB , I , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ; if ( Amount ) { int Offset = isDestroy ? Amount : - Amount ; if ( ! ( Fn -> optForMinSize ( ) && adjustStackWithPops ( MBB , I , DL , Offset ) ) ) BuildStackAdjustment ( MBB , I , DL , Offset , false ) ; } if ( DwarfCFI && ! hasFP ( MF ) ) { int CFAOffset = Amount ; if ( ! MMI . usePreciseUnwindInfo ( ) ) CFAOffset += InternalAmt ; CFAOffset = isDestroy ? - CFAOffset : CFAOffset ; BuildCFI ( MBB , I , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , CFAOffset ) ) ; } return ; } if ( isDestroy && InternalAmt ) { MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! std :: prev ( I ) -> isCall ( ) ) -- I ; BuildStackAdjustment ( MBB , I , DL , - InternalAmt , false ) ; } } </s>


<s> bool M68kAsmParser :: emit ( MCInst & Inst , SMLoc const & Loc , MCStreamer & Out ) const { Inst . setLoc ( Loc ) ; Out . emitInstruction ( Inst , STI ) ; return false ; } </s>

Output the remark via the diagnostic handler and to the optimization record file .


<s> bool AlphaTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { if ( VT != MVT :: f32 && VT != MVT :: f64 ) return false ; return Imm . isZero ( ) || Imm . isNegZero ( ) ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( Size , Offset , true ) ; MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; return MIRBuilder . buildFrameIndex ( LLT :: pointer ( 0 , DL . getPointerSizeInBits ( 0 ) ) , FI ) . getReg ( 0 ) ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> static bool ea_symbol_ref_p ( const_rtx x ) { tree decl ; if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS ) { rtx plus = XEXP ( x , 0 ) ; rtx op0 = XEXP ( plus , 0 ) ; rtx op1 = XEXP ( plus , 1 ) ; if ( GET_CODE ( op1 ) == CONST_INT ) x = op0 ; } return ( GET_CODE ( x ) == SYMBOL_REF && ( decl = SYMBOL_REF_DECL ( x ) ) != 0 && TREE_CODE ( decl ) == VAR_DECL && TYPE_ADDR_SPACE ( TREE_TYPE ( decl ) ) ) ; } </s>

Return true if X is a SYMBOL_REF to an __ea qualified variable .


<s> static rtx r10k_simplify_address ( rtx x , rtx_insn * insn ) { rtx newx , op0 , op1 , set , note ; rtx_insn * def_insn ; df_ref use , def ; struct df_link * defs ; newx = NULL_RTX ; if ( UNARY_P ( x ) ) { op0 = r10k_simplify_address ( XEXP ( x , 0 ) , insn ) ; if ( op0 != XEXP ( x , 0 ) ) newx = simplify_gen_unary ( GET_CODE ( x ) , GET_MODE ( x ) , op0 , GET_MODE ( XEXP ( x , 0 ) ) ) ; } else if ( BINARY_P ( x ) ) { op0 = r10k_simplify_address ( XEXP ( x , 0 ) , insn ) ; op1 = r10k_simplify_address ( XEXP ( x , 1 ) , insn ) ; if ( op0 != XEXP ( x , 0 ) || op1 != XEXP ( x , 1 ) ) newx = simplify_gen_binary ( GET_CODE ( x ) , GET_MODE ( x ) , op0 , op1 ) ; } else if ( GET_CODE ( x ) == LO_SUM ) { op0 = r10k_simplify_address ( XEXP ( x , 0 ) , insn ) ; if ( GET_CODE ( op0 ) == HIGH ) newx = XEXP ( x , 1 ) ; } else if ( REG_P ( x ) ) { use = df_find_use ( insn , regno_reg_rtx [ REGNO ( x ) ] ) ; gcc_assert ( use ) ; defs = DF_REF_CHAIN ( use ) ; if ( defs && defs -> next == NULL ) { def = defs -> ref ; if ( DF_REF_IS_ARTIFICIAL ( def ) ) { if ( x == stack_pointer_rtx && DF_REF_BB ( def ) == ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) newx = virtual_incoming_args_rtx ; } else if ( dominated_by_p ( CDI_DOMINATORS , DF_REF_BB ( use ) , DF_REF_BB ( def ) ) ) { def_insn = DF_REF_INSN ( def ) ; if ( NONJUMP_INSN_P ( def_insn ) ) { set = single_set ( def_insn ) ; if ( set && rtx_equal_p ( SET_DEST ( set ) , x ) ) { note = find_reg_equal_equiv_note ( def_insn ) ; if ( note ) newx = XEXP ( note , 0 ) ; else newx = SET_SRC ( set ) ; newx = r10k_simplify_address ( newx , def_insn ) ; } } } } } if ( newx && r10k_simplified_address_p ( newx ) ) return newx ; return x ; } </s>

X is an expression that appears in INSN . Try to use the UD chains to simplify it , returning the simplified form on success and the original form otherwise . Replace the incoming value of $ sp with virtual_incoming_args_rtx ( which should never occur in X otherwise ) .


<s> void NVPTXAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; if ( nvptxSubtarget . getDrvInterface ( ) == NVPTX :: CUDA ) emitLineNumberAsDotLoc ( * MI ) ; printInstruction ( MI , OS ) ; OutStreamer . EmitRawText ( OS . str ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> virtual const LanaiRegisterInfo & getRegisterInfo ( ) const { return RegisterInfo ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> Register M88kIncomingValueHandler :: getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO , ISD :: ArgFlagsTy Flags ) { auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; const bool IsImmutable = ! Flags . isByVal ( ) ; int FI = MFI . CreateFixedObject ( Size , Offset , IsImmutable ) ; MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; llvm :: LLT FramePtr = LLT :: pointer ( 0 , 32 ) ; MachineInstrBuilder AddrReg = MIRBuilder . buildFrameIndex ( FramePtr , FI ) ; return AddrReg . getReg ( 0 ) ; } </s>


<s> bool enableInterleavedAccessVectorization ( ) { return ! ST -> hasSVE ( ) ; } </s>

Enable matching of interleaved access groups .


<s> bool SystemZElimCompare :: runOnMachineFunction ( MachineFunction & F ) { TII = static_cast < const SystemZInstrInfo * > ( F . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = & TII -> getRegisterInfo ( ) ; bool Changed = false ; for ( auto & MBB : F ) Changed |= processBlock ( MBB ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s>
static
void
*
device_malloc
(
size_t
size
)
{
void
*
result
;
XHSA
(
hsa_fns
.
hsa_memory_allocate_fn
(
kernargs_region
,
size
,
&
result
)
,
"Allocate device memory"
)
;
return
result
;
}
</s>

Allocate some device memory from the kernargs region . The returned address will be 32-bit ( with excess zeroed on 64-bit host ) , and accessible via the same address on both host and target ( via __flat_scalar GCN address space ) .


<s> explicit Entry ( const MachineLoop * L ) : Loop ( L ) , NumBlocksLeft ( L -> getNumBlocks ( ) ) { } </s>


"converting far pointer to near pointer"

Convert from one address space to another .


"Return instruction can only reference SP relative frame objects"

"Requesting 64-bit offset in 32-bit immediate!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool GBZ80PostISel :: runOnMachineFunction ( MachineFunction & MF ) { bool Modified = false ; this -> MF = & MF ; const GBZ80Subtarget & STI = MF . getSubtarget < GBZ80Subtarget > ( ) ; TRI = STI . getRegisterInfo ( ) ; TII = STI . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; Modified |= expandShiftLoop16 ( ) ; Modified |= expandPseudos ( ) ; Modified |= expandBranch16 ( ) ; Modified |= optimizeCP ( ) ; return Modified ; } </s>


<s>
const
char
*
cr16_emit_add_sub_di
(
rtx
*
operands
,
enum
rtx_code
code
)
{
rtx
lo_op
[
2
]
;
rtx
hi0_op
[
2
]
;
rtx
hi1_op
[
2
]
;
lo_op
[
0
]
=
gen_lowpart
(
SImode
,
operands
[
0
]
)
;
hi0_op
[
0
]
=
simplify_gen_subreg
(
HImode
,
operands
[
0
]
,
DImode
,
4
)
;
hi1_op
[
0
]
=
simplify_gen_subreg
(
HImode
,
operands
[
0
]
,
DImode
,
6
)
;
lo_op
[
1
]
=
gen_lowpart
(
SImode
,
operands
[
2
]
)
;
hi0_op
[
1
]
=
simplify_gen_subreg
(
HImode
,
operands
[
2
]
,
DImode
,
4
)
;
hi1_op
[
1
]
=
simplify_gen_subreg
(
HImode
,
operands
[
2
]
,
DImode
,
6
)
;
switch
(
code
)
{
case
PLUS
:
{
output_asm_insn
(
"addd\t%1, %0"
,
lo_op
)
;
output_asm_insn
(
"addcw\t%1, %0"
,
hi0_op
)
;
output_asm_insn
(
"addcw\t%1, %0"
,
hi1_op
)
;
break
;
}
case
MINUS
:
{
output_asm_insn
(
"subd\t%1, %0"
,
lo_op
)
;
output_asm_insn
(
"subcw\t%1, %0"
,
hi0_op
)
;
output_asm_insn
(
"subcw\t%1, %0"
,
hi1_op
)
;
break
;
}
default
:
break
;
}
return
""
;
}
</s>

Helper function for md file . This function is used to emit arithmetic DI instructions . The argument `` num '' decides which instruction to be printed .


<s> const uint16_t * LEGRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { LEG :: R4 , LEG :: R5 , LEG :: R6 , LEG :: R7 , LEG :: R8 , LEG :: R9 , 0 } ; return CalleeSavedRegs ; } </s>


<s>
bool
ARMTargetLowering
::
ExpandInlineAsm
(
CallInst
*
CI
)
const
{
if
(
!
Subtarget
->
hasV6Ops
(
)
)
return
false
;
InlineAsm
*
IA
=
cast
<
InlineAsm
>
(
CI
->
getCalledValue
(
)
)
;
std
::
string
AsmStr
=
IA
->
getAsmString
(
)
;
SmallVector
<
StringRef
,
4
>
AsmPieces
;
SplitString
(
AsmStr
,
AsmPieces
,
";\n"
)
;
switch
(
AsmPieces
.
size
(
)
)
{
default
:
return
false
;
case
1
:
AsmStr
=
std
::
string
(
AsmPieces
[
0
]
)
;
AsmPieces
.
clear
(
)
;
SplitString
(
AsmStr
,
AsmPieces
,
" \t,"
)
;
if
(
AsmPieces
.
size
(
)
==
3
&&
AsmPieces
[
0
]
==
"rev"
&&
AsmPieces
[
1
]
==
"$0"
&&
AsmPieces
[
2
]
==
"$1"
&&
IA
->
getConstraintString
(
)
.
compare
(
0
,
4
,
"=l,l"
)
==
0
)
{
IntegerType
*
Ty
=
dyn_cast
<
IntegerType
>
(
CI
->
getType
(
)
)
;
if
(
Ty
&&
Ty
->
getBitWidth
(
)
==
32
)
return
IntrinsicLowering
::
LowerToByteSwap
(
CI
)
;
}
break
;
}
return
false
;
}
</s>

This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to .


<s> static void s390_check_type_for_vector_abi ( const_tree type , bool arg_p , bool in_struct_p ) { static hash_set < const_tree > visited_types_hash ; if ( s390_vector_abi ) return ; if ( type == NULL_TREE || TREE_CODE ( type ) == ERROR_MARK ) return ; if ( visited_types_hash . contains ( type ) ) return ; visited_types_hash . add ( type ) ; if ( VECTOR_TYPE_P ( type ) ) { int type_size = int_size_in_bytes ( type ) ; if ( ! arg_p && type_size < 16 ) return ; if ( arg_p && type_size > 16 && ! in_struct_p ) return ; s390_vector_abi = TARGET_VX_ABI ? 2 : 1 ; } else if ( POINTER_TYPE_P ( type ) || TREE_CODE ( type ) == ARRAY_TYPE ) { s390_check_type_for_vector_abi ( TREE_TYPE ( type ) , arg_p , in_struct_p ) ; } else if ( TREE_CODE ( type ) == FUNCTION_TYPE || TREE_CODE ( type ) == METHOD_TYPE ) { tree arg_chain ; s390_check_type_for_vector_abi ( TREE_TYPE ( type ) , true , false ) ; for ( arg_chain = TYPE_ARG_TYPES ( type ) ; arg_chain ; arg_chain = TREE_CHAIN ( arg_chain ) ) s390_check_type_for_vector_abi ( TREE_VALUE ( arg_chain ) , true , false ) ; } else if ( RECORD_OR_UNION_TYPE_P ( type ) ) { tree field ; for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; s390_check_type_for_vector_abi ( TREE_TYPE ( field ) , arg_p , true ) ; } } } </s>

Set the vector ABI marker if TYPE is subject to the vector ABI switch . The vector ABI affects only vector data types . There are two aspects of the vector ABI relevant here : 1. vectors > = 16 bytes have an alignment of 8 bytes with the new ABI and natural alignment with the old . 2. vector < = 16 bytes are passed in VRs or by value on the stack with the new ABI but by reference on the stack with the old . If ARG_P is true TYPE is used for a function argument or return value . The ABI marker then is set for all vector data types . If ARG_P is false only type 1 vectors are being checked .


"Function has local memory argument. Promoting to "

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


"RegScavenger required for long branching"

"new block should be inserted for expanding unconditional branch"

"Branch offsets outside of the signed 32-bit range not supported"

Insert an unconditional indirect branch at the end of MBB to NewDestBB .


<s> unsigned X86RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const X86FrameLowering * TFI = getFrameLowering ( MF ) ; unsigned FPDiff = TFI -> hasFP ( MF ) ? 1 : 0 ; switch ( RC -> getID ( ) ) { default : return 0 ; case X86 :: GR32RegClassID : return 4 - FPDiff ; case X86 :: GR64RegClassID : return 12 - FPDiff ; case X86 :: VR128RegClassID : return Is64Bit ? 10 : 4 ; case X86 :: VR64RegClassID : return 4 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> static void csky_setup_incoming_varargs ( cumulative_args_t pcum_v , machine_mode mode , tree type , int * pretend_size , int second_time ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * pcum = get_cumulative_args ( pcum_v ) ; CUMULATIVE_ARGS local_cum ; cumulative_args_t local_cum_v = pack_cumulative_args ( & local_cum ) ; int regs_to_push ; cfun -> machine -> uses_anonymous_args = 1 ; local_cum = * pcum ; csky_function_arg_advance ( local_cum_v , mode , type , true ) ; regs_to_push = CSKY_NPARM_REGS - local_cum ; if ( regs_to_push ) * pretend_size = regs_to_push * UNITS_PER_WORD ; } </s>

Implement TARGET_SETUP_INCOMING_VARARGS . On C-Sky the copy from the argument registers to the stack is emitted by the prologue hooks , so here we just have to note how much stack space to save .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> static void alpha_emit_xfloating_libcall ( rtx func , rtx target , rtx operands [ ] , int noperands , rtx equiv ) { rtx usage = NULL_RTX , reg ; int regno = 16 , i ; start_sequence ( ) ; for ( i = 0 ; i < noperands ; ++ i ) { switch ( GET_MODE ( operands [ i ] ) ) { case E_TFmode : reg = gen_rtx_REG ( TFmode , regno ) ; regno += 2 ; break ; case E_DFmode : reg = gen_rtx_REG ( DFmode , regno + 32 ) ; regno += 1 ; break ; case E_VOIDmode : gcc_assert ( CONST_INT_P ( operands [ i ] ) ) ; case E_DImode : reg = gen_rtx_REG ( DImode , regno ) ; regno += 1 ; break ; default : gcc_unreachable ( ) ; } emit_move_insn ( reg , operands [ i ] ) ; use_reg ( & usage , reg ) ; } switch ( GET_MODE ( target ) ) { case E_TFmode : reg = gen_rtx_REG ( TFmode , 16 ) ; break ; case E_DFmode : reg = gen_rtx_REG ( DFmode , 32 ) ; break ; case E_DImode : reg = gen_rtx_REG ( DImode , 0 ) ; break ; default : gcc_unreachable ( ) ; } rtx mem = gen_rtx_MEM ( QImode , func ) ; rtx_insn * tmp = emit_call_insn ( gen_call_value ( reg , mem , const0_rtx , const0_rtx , const0_rtx ) ) ; CALL_INSN_FUNCTION_USAGE ( tmp ) = usage ; RTL_CONST_CALL_P ( tmp ) = 1 ; tmp = get_insns ( ) ; end_sequence ( ) ; emit_libcall_block ( tmp , target , reg , equiv ) ; } </s>

Emit an X_floating library function call . Note that these functions do not follow normal calling conventions : TFmode arguments are passed in two integer registers ( as opposed to indirect ) ; TFmode return values appear in R16+R17 . FUNC is the function name to call . TARGET is where the output belongs . OPERANDS are the inputs . NOPERANDS is the count of inputs . EQUIV is the expression equivalent for the function .


<s> void ARMTargetELFStreamer :: emitInst ( uint32_t Inst , char Suffix ) { getStreamer ( ) . emitInst ( Inst , Suffix ) ; } </s>

Callback used to implement the .inst directive .


<s> static void AnalyzeArguments ( CCState & State , SmallVectorImpl < CCValAssign > & ArgLocs , const SmallVectorImpl < ArgT > & Args ) { static const MCPhysReg RegList [ ] = { MSP430 :: R15 , MSP430 :: R14 , MSP430 :: R13 , MSP430 :: R12 } ; static const unsigned NbRegs = array_lengthof ( RegList ) ; if ( State . isVarArg ( ) ) { AnalyzeVarArgs ( State , Args ) ; return ; } SmallVector < unsigned , 4 > ArgsParts ; ParseFunctionArgs ( Args , ArgsParts ) ; unsigned RegsLeft = NbRegs ; bool UseStack = false ; unsigned ValNo = 0 ; for ( unsigned i = 0 , e = ArgsParts . size ( ) ; i != e ; i ++ ) { MVT ArgVT = Args [ ValNo ] . VT ; ISD :: ArgFlagsTy ArgFlags = Args [ ValNo ] . Flags ; MVT LocVT = ArgVT ; CCValAssign :: LocInfo LocInfo = CCValAssign :: Full ; if ( LocVT == MVT :: i8 ) { LocVT = MVT :: i16 ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } if ( ArgFlags . isByVal ( ) ) { State . HandleByVal ( ValNo ++ , ArgVT , LocVT , LocInfo , 2 , 2 , ArgFlags ) ; continue ; } unsigned Parts = ArgsParts [ i ] ; if ( ! UseStack && Parts <= RegsLeft ) { unsigned FirstVal = ValNo ; for ( unsigned j = 0 ; j < Parts ; j ++ ) { unsigned Reg = State . AllocateReg ( RegList ) ; State . addLoc ( CCValAssign :: getReg ( ValNo ++ , ArgVT , Reg , LocVT , LocInfo ) ) ; RegsLeft -- ; } SmallVectorImpl < CCValAssign > :: iterator B = ArgLocs . begin ( ) + FirstVal ; std :: reverse ( B , B + Parts ) ; } else { UseStack = true ; for ( unsigned j = 0 ; j < Parts ; j ++ ) CC_MSP430_AssignStack ( ValNo ++ , ArgVT , LocVT , LocInfo , ArgFlags , State ) ; } } } </s>

The function will invoke AnalyzeCallOperands .


<s>
void
PPCTargetLowering
::
LowerAsmOperandForConstraint
(
SDValue
Op
,
char
Letter
,
std
::
vector
<
SDValue
>
&
Ops
,
SelectionDAG
&
DAG
)
const
{
SDValue
Result
(
0
,
0
)
;
switch
(
Letter
)
{
default
:
break
;
case
'I'
:
case
'J'
:
case
'K'
:
case
'L'
:
case
'M'
:
case
'N'
:
case
'O'
:
case
'P'
:
{
ConstantSDNode
*
CST
=
dyn_cast
<
ConstantSDNode
>
(
Op
)
;
if
(
!
CST
)
return
;
unsigned
Value
=
CST
->
getZExtValue
(
)
;
switch
(
Letter
)
{
default
:
llvm_unreachable
(
"Unknown constraint letter!"
)
;
case
'I'
:
if
(
(
short
)
Value
==
(
int
)
Value
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'J'
:
case
'L'
:
if
(
(
short
)
Value
==
0
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'K'
:
if
(
(
Value
>>
16
)
==
0
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'M'
:
if
(
Value
>
31
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'N'
:
if
(
(
int
)
Value
>
0
&&
isPowerOf2_32
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'O'
:
if
(
Value
==
0
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'P'
:
if
(
(
short
)
Value
==
(
int
)
Value
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
}
break
;
}
}
if
(
Result
.
getNode
(
)
)
{
Ops
.
push_back
(
Result
)
;
return
;
}
TargetLowering
::
LowerAsmOperandForConstraint
(
Op
,
Letter
,
Ops
,
DAG
)
;
}
</s>

Lower the specified operand into the Ops vector .


Return a string to output before text in the current function . This function is only used with SOM . Because we do n't support named subspaces , we can only create a new subspace or switch back to the default text subspace .


<s> unsigned ARMBaseInstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr * MI , int & FrameIndex ) const { const MachineMemOperand * Dummy ; return MI -> mayLoad ( ) && hasLoadFromStackSlot ( MI , Dummy , FrameIndex ) ; } </s>

isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s>
void
mmix_asm_output_source_filename
(
FILE
*
stream
,
const
char
*
name
)
{
fprintf
(
stream
,
"# 1 "
)
;
OUTPUT_QUOTED_STRING
(
stream
,
name
)
;
fprintf
(
stream
,
"\n"
)
;
}
</s>


<s> bool X86TargetLowering :: areJTsAllowed ( const Function * Fn ) const { if ( Subtarget . useIndirectThunkBranches ( ) ) return false ; return TargetLowering :: areJTsAllowed ( Fn ) ; } </s>

Returns true if lowering to a jump table is allowed .


<s> bool llvm :: getAlign ( const CallInst & I , unsigned index , unsigned & align ) { if ( MDNode * alignNode = I . getMetadata ( "callalign" ) ) { for ( int i = 0 , n = alignNode -> getNumOperands ( ) ; i < n ; i ++ ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( alignNode -> getOperand ( i ) ) ) { unsigned v = CI -> getZExtValue ( ) ; if ( ( v >> 16 ) == index ) { align = v & 0xFFFF ; return true ; } if ( ( v >> 16 ) > index ) { return false ; } } } } return false ; } </s>

Return the minimum known alignment in bytes of the actual memory reference .


<s> void R600TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { switch ( N -> getOpcode ( ) ) { default : return ; case ISD :: FP_TO_UINT : Results . push_back ( LowerFPTOUINT ( N -> getOperand ( 0 ) , DAG ) ) ; return ; case ISD :: LOAD : { SDNode * Node = LowerLOAD ( SDValue ( N , 0 ) , DAG ) . getNode ( ) ; Results . push_back ( SDValue ( Node , 0 ) ) ; Results . push_back ( SDValue ( Node , 1 ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( N , 1 ) , SDValue ( Node , 1 ) ) ; return ; } case ISD :: STORE : SDNode * Node = LowerSTORE ( SDValue ( N , 0 ) , DAG ) . getNode ( ) ; Results . push_back ( SDValue ( Node , 0 ) ) ; return ; } } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s>
bool
SITargetLowering
::
isLegalAddressingMode
(
const
DataLayout
&
DL
,
const
AddrMode
&
AM
,
Type
*
Ty
,
unsigned
AS
)
const
{
if
(
AM
.
BaseGV
)
return
false
;
switch
(
AS
)
{
case
AMDGPUAS
::
GLOBAL_ADDRESS
:
{
if
(
Subtarget
->
getGeneration
(
)
>=
AMDGPUSubtarget
::
VOLCANIC_ISLANDS
)
{
return
isLegalFlatAddressingMode
(
AM
)
;
}
return
isLegalMUBUFAddressingMode
(
AM
)
;
}
case
AMDGPUAS
::
CONSTANT_ADDRESS
:
{
if
(
AM
.
BaseOffs
%
4
!=
0
)
return
isLegalMUBUFAddressingMode
(
AM
)
;
if
(
DL
.
getTypeStoreSize
(
Ty
)
<
4
)
return
isLegalMUBUFAddressingMode
(
AM
)
;
if
(
Subtarget
->
getGeneration
(
)
==
AMDGPUSubtarget
::
SOUTHERN_ISLANDS
)
{
if
(
!
isUInt
<
8
>
(
AM
.
BaseOffs
/
4
)
)
return
false
;
}
else
if
(
Subtarget
->
getGeneration
(
)
==
AMDGPUSubtarget
::
SEA_ISLANDS
)
{
if
(
!
isUInt
<
32
>
(
AM
.
BaseOffs
/
4
)
)
return
false
;
}
else
if
(
Subtarget
->
getGeneration
(
)
==
AMDGPUSubtarget
::
VOLCANIC_ISLANDS
)
{
if
(
!
isUInt
<
20
>
(
AM
.
BaseOffs
)
)
return
false
;
}
else
llvm_unreachable
(
"unhandled generation"
)
;
if
(
AM
.
Scale
==
0
)
return
true
;
if
(
AM
.
Scale
==
1
&&
AM
.
HasBaseReg
)
return
true
;
return
false
;
}
case
AMDGPUAS
::
PRIVATE_ADDRESS
:
case
AMDGPUAS
::
UNKNOWN_ADDRESS_SPACE
:
return
isLegalMUBUFAddressingMode
(
AM
)
;
case
AMDGPUAS
::
LOCAL_ADDRESS
:
case
AMDGPUAS
::
REGION_ADDRESS
:
{
if
(
!
isUInt
<
16
>
(
AM
.
BaseOffs
)
)
return
false
;
if
(
AM
.
Scale
==
0
)
return
true
;
if
(
AM
.
Scale
==
1
&&
AM
.
HasBaseReg
)
return
true
;
return
false
;
}
case
AMDGPUAS
::
FLAT_ADDRESS
:
return
isLegalFlatAddressingMode
(
AM
)
;
default
:
llvm_unreachable
(
"unhandled address space"
)
;
}
}
</s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> inline units_index function_instance :: displacement_units ( ) const { return mode_suffix ( ) . displacement_units ; } </s>

If the function takes a vector or scalar displacement , return the units in which the displacement is measured , otherwise return UNITS_none .


<s> static int need_to_save_reg ( int regno , int saving ) { if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) return 1 ; if ( flag_pic && regno == PIC_OFFSET_TABLE_REGNUM && ( ! saving || cfun -> machine -> pic_reg == pic_offset_table_rtx ) ) return 1 ; return 0 ; } </s>

Return whether REGNO needs to be saved in the stack frame .


<s> inline const MatchEntry * end ( const MatchEntry array [ ] ) { return array ; } </s>

Get a const_iterator to the end of the symbol table .


<s> bool X86InstrInfo :: isSafeToMoveRegClassDefs ( const TargetRegisterClass * RC ) const { return ! ( RC == & X86 :: CCRRegClass || RC == & X86 :: RFP32RegClass || RC == & X86 :: RFP64RegClass || RC == & X86 :: RFP80RegClass ) ; } </s>

isSafeToMoveRegClassDefs - Return true if it 's safe to move a machine instruction that defines the specified register class .


<s>
bool
PPCRegisterInfo
::
needsFrameBaseReg
(
MachineInstr
*
MI
,
int64_t
Offset
)
const
{
assert
(
Offset
<
0
&&
"Local offset must be negative"
)
;
unsigned
OpC
=
MI
->
getOpcode
(
)
;
if
(
!
ImmToIdxMap
.
count
(
OpC
)
)
return
false
;
if
(
(
OpC
==
PPC
::
ADDI
||
OpC
==
PPC
::
ADDI8
)
&&
MI
->
getOperand
(
2
)
.
getImm
(
)
==
0
)
return
false
;
MachineBasicBlock
&
MBB
=
*
MI
->
getParent
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
PPCSubtarget
&
Subtarget
=
MF
.
getSubtarget
<
PPCSubtarget
>
(
)
;
const
PPCFrameLowering
*
PPCFI
=
static_cast
<
const
PPCFrameLowering
*
>
(
Subtarget
.
getFrameLowering
(
)
)
;
unsigned
StackEst
=
PPCFI
->
determineFrameLayout
(
MF
,
false
,
true
)
;
if
(
!
StackEst
)
return
false
;
Offset
+=
StackEst
;
return
!
isFrameOffsetLegal
(
MI
,
getBaseRegister
(
MF
)
,
Offset
)
;
}
</s>

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .

PowerPC
PPC
0
"Local offset must be negative"
PPC::ADDI
PPC::ADDI8
2
0
PPC
PPC
PPC
PPC
PPC
PPC


<s> static void emit_frame_store_1 ( rtx value , rtx base_reg , HOST_WIDE_INT frame_bias , HOST_WIDE_INT base_ofs , rtx frame_reg ) { rtx addr , mem , insn ; addr = plus_constant ( base_reg , base_ofs ) ; mem = gen_rtx_MEM ( DImode , addr ) ; set_mem_alias_set ( mem , alpha_sr_alias_set ) ; insn = emit_move_insn ( mem , value ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( frame_bias || value != frame_reg ) { if ( frame_bias ) { addr = plus_constant ( stack_pointer_rtx , frame_bias + base_ofs ) ; mem = gen_rtx_MEM ( DImode , addr ) ; } REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , mem , frame_reg ) , REG_NOTES ( insn ) ) ; } } </s>

Generates a store with the proper unwind info attached . VALUE is stored at BASE_REG+BASE_OFS . If FRAME_BIAS is nonzero , then BASE_REG contains SP+FRAME_BIAS , and that is the unwind info that should be generated . If FRAME_REG ! = VALUE , then VALUE is being stored on behalf of FRAME_REG , and FRAME_REG should be present in the unwind .


<s> void SystemZAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { SystemZMCInstLower Lower ( Mang , MF -> getContext ( ) , * this ) ; MCInst LoweredMI ; Lower . lower ( MI , LoweredMI ) ; OutStreamer . EmitInstruction ( LoweredMI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static void frv_io_handle_set ( rtx x , const_rtx pat ATTRIBUTE_UNUSED , void * data ) { HARD_REG_SET * set = ( HARD_REG_SET * ) data ; unsigned int regno ; if ( REG_P ( x ) ) FOR_EACH_REGNO ( regno , x ) CLEAR_HARD_REG_BIT ( * set , regno ) ; } </s>

A note_stores callback for which DATA points to a HARD_REG_SET . Remove every modified register from the set .


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override { uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> Write32 ( 0x60000000 ) ; OW -> WriteZeros ( Count % 4 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> static poly_int64 ix86_return_pops_args ( tree fundecl , tree funtype , poly_int64 size ) { unsigned int ccvt ; if ( TARGET_64BIT ) return 0 ; ccvt = ix86_get_callcvt ( funtype ) ; if ( ( ccvt & ( IX86_CALLCVT_STDCALL | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL ) ) != 0 && ! stdarg_p ( funtype ) ) return size ; if ( aggregate_value_p ( TREE_TYPE ( funtype ) , fundecl ) && ! ix86_keep_aggregate_return_pointer ( funtype ) ) { int nregs = ix86_function_regparm ( funtype , fundecl ) ; if ( nregs == 0 ) return GET_MODE_SIZE ( Pmode ) ; } return 0 ; } </s>

Value is the number of bytes of arguments automatically popped when returning from a subroutine call . FUNDECL is the declaration node of the function ( as a tree ) , FUNTYPE is the data type of the function ( as a tree ) , or for a library call it is an identifier node for the subroutine name . SIZE is the number of bytes of arguments passed on the stack . On the 80386 , the RTD insn may be used to pop them if the number of args is fixed , but if the number is variable then the caller must pop them all . RTD ca n't be used for library calls now because the library is compiled with the Unix compiler . Use of RTD is a selectable option , since it is incompatible with standard Unix calling sequences . If the option is not selected , the caller must always pop the args . The attribute stdcall is equivalent to RTD on a per module basis .


<s> unsigned ARMBaseRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; const ARMFrameLowering * TFI = getFrameLowering ( MF ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case ARM :: tGPRRegClassID : { bool HasFP = MF . getFrameInfo ( ) . isMaxCallFrameSizeComputed ( ) ? TFI -> hasFP ( MF ) : true ; return 5 - HasFP ; } case ARM :: GPRRegClassID : { bool HasFP = MF . getFrameInfo ( ) . isMaxCallFrameSizeComputed ( ) ? TFI -> hasFP ( MF ) : true ; return 10 - HasFP - ( STI . isR9Reserved ( ) ? 1 : 0 ) ; } case ARM :: SPRRegClassID : case ARM :: DPRRegClassID : return 32 - 10 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


"operands are not valid for this GPU or mode"

"internal error: instruction without _e64 suffix "

"Invalid instructions should have been handled already"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> void HexagonFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { auto & HST = MF . getSubtarget < HexagonSubtarget > ( ) ; auto & HRI = * HST . getRegisterInfo ( ) ; SavedRegs . resize ( HRI . getNumRegs ( ) ) ; if ( MF . getInfo < HexagonMachineFunctionInfo > ( ) -> hasEHReturn ( ) ) for ( const MCPhysReg * R = HRI . getCalleeSavedRegs ( & MF ) ; * R ; ++ R ) SavedRegs . set ( * R ) ; SmallVector < unsigned , 8 > NewRegs ; expandSpillMacros ( MF , NewRegs ) ; if ( OptimizeSpillSlots ) optimizeSpillSlots ( MF , NewRegs ) ; if ( ! NewRegs . empty ( ) && needToReserveScavengingSpillSlots ( MF , HRI ) ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; SetVector < const TargetRegisterClass * > SpillRCs ; for ( unsigned VR : NewRegs ) SpillRCs . insert ( MRI . getRegClass ( VR ) ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; const TargetRegisterClass & IntRC = Hexagon :: IntRegsRegClass ; if ( SpillRCs . count ( & IntRC ) ) { for ( int i = 0 ; i < NumberScavengerSlots ; i ++ ) { int NewFI = MFI . CreateSpillStackObject ( IntRC . getSize ( ) , IntRC . getAlignment ( ) ) ; RS -> addScavengingFrameIndex ( NewFI ) ; } } for ( auto * RC : SpillRCs ) { if ( RC == & IntRC ) continue ; int NewFI = MFI . CreateSpillStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) ) ; RS -> addScavengingFrameIndex ( NewFI ) ; } } TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .

Hexagon Hexagon Hexagon Hexagon 8 Hexagon::IntRegsRegClass 0


<s> static bool aarch64_print_ldpstp_address ( FILE * f , machine_mode mode , rtx x ) { return aarch64_print_address_internal ( f , mode , x , ADDR_QUERY_LDP_STP ) ; } </s>

Print address ' x ' of a LDP/STP with mode 'mode ' .


<s> MachineBasicBlock * SITargetLowering :: EmitInstrWithCustomInserter ( MachineInstr * MI , MachineBasicBlock * BB ) const { MachineBasicBlock :: iterator I = * MI ; const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; switch ( MI -> getOpcode ( ) ) { default : return AMDGPUTargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; case AMDGPU :: BRANCH : return BB ; case AMDGPU :: SI_RegisterStorePseudo : { MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; unsigned Reg = MRI . createVirtualRegister ( & AMDGPU :: SReg_64RegClass ) ; MachineInstrBuilder MIB = BuildMI ( * BB , I , MI -> getDebugLoc ( ) , TII -> get ( AMDGPU :: SI_RegisterStore ) , Reg ) ; for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) MIB . addOperand ( MI -> getOperand ( i ) ) ; MI -> eraseFromParent ( ) ; break ; } } return BB ; } </s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static bool r10k_needs_protection_p ( rtx_insn * insn ) { if ( CALL_P ( insn ) ) return r10k_needs_protection_p_call ( PATTERN ( insn ) ) ; if ( mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE ) { note_stores ( insn , r10k_needs_protection_p_store , & insn ) ; return insn == NULL_RTX ; } return r10k_needs_protection_p_1 ( PATTERN ( insn ) , insn ) ; } </s>

Return true if instruction INSN needs to be protected by an R10K cache barrier .


<s> static int h8300_stack_offset_p ( rtx x , int offset ) { if ( offset == 0 ) return x == stack_pointer_rtx ; return ( GET_CODE ( x ) == PLUS && XEXP ( x , 0 ) == stack_pointer_rtx && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT && INTVAL ( XEXP ( x , 1 ) ) == offset ) ; } </s>

Return true if X has the value sp + OFFSET .


<s> bool ARM64ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const ARM64InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; bool Modified = false ; for ( auto & MBB : MF ) Modified |= expandMBB ( MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> ARCSubtarget :: ARCSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : ARCGenSubtargetInfo ( TT , CPU , CPU , FS ) , InstrInfo ( * this ) , FrameLowering ( * this ) , TLInfo ( TM , * this ) { } </s>

This constructor initializes the data members to match that of the specified triple .


<s> static rtx frv_expand_binop_builtin ( enum insn_code icode , tree arglist , rtx target ) { rtx pat ; rtx op0 = frv_read_argument ( & arglist ) ; rtx op1 = frv_read_argument ( & arglist ) ; target = frv_legitimize_target ( icode , target ) ; op0 = frv_legitimize_argument ( icode , 1 , op0 ) ; op1 = frv_legitimize_argument ( icode , 2 , op1 ) ; pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return target ; } </s>

Expand builtins that take two operands .


<s>
SDValue
PTXTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
if
(
isVarArg
)
llvm_unreachable
(
"PTX does not support varargs"
)
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention."
)
;
case
CallingConv
::
PTX_Kernel
:
assert
(
Outs
.
size
(
)
==
0
&&
"Kernel must return void."
)
;
return
DAG
.
getNode
(
PTXISD
::
EXIT
,
dl
,
MVT
::
Other
,
Chain
)
;
case
CallingConv
::
PTX_Device
:
assert
(
Outs
.
size
(
)
<=
1
&&
"Can at most return one value."
)
;
break
;
}
if
(
Outs
.
size
(
)
==
0
)
return
DAG
.
getNode
(
PTXISD
::
RET
,
dl
,
MVT
::
Other
,
Chain
)
;
SDValue
Flag
;
unsigned
reg
;
if
(
Outs
[
0
]
.
VT
==
MVT
::
i16
)
{
reg
=
PTX
::
RH0
;
}
else
if
(
Outs
[
0
]
.
VT
==
MVT
::
i32
)
{
reg
=
PTX
::
R0
;
}
else
if
(
Outs
[
0
]
.
VT
==
MVT
::
i64
)
{
reg
=
PTX
::
RD0
;
}
else
if
(
Outs
[
0
]
.
VT
==
MVT
::
f32
)
{
reg
=
PTX
::
F0
;
}
else
{
assert
(
Outs
[
0
]
.
VT
==
MVT
::
f64
&&
"Can return only basic types"
)
;
reg
=
PTX
::
FD0
;
}
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
PTXMachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
PTXMachineFunctionInfo
>
(
)
;
MFI
->
setRetReg
(
reg
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
reg
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
reg
,
OutVals
[
0
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
return
DAG
.
getNode
(
PTXISD
::
RET
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool TeakPassConfig :: addInstSelector ( ) { addPass ( createTeakISelDag ( getTeakTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool pure_scalable_type_info :: analyze_registers ( const_tree type ) { analysis_result result = analyze ( type ) ; gcc_assert ( result != DOESNT_MATTER ) ; return result == IS_PST ; } </s>

Analyze a type that is known not to be passed or returned in memory . Return true if it has an ABI identity and is a Pure Scalable Type .


<s>
unsigned
char
X86Subtarget
::
ClassifyGlobalReference
(
const
GlobalValue
*
GV
,
const
TargetMachine
&
TM
)
const
{
if
(
GV
->
hasDLLImportLinkage
(
)
)
return
X86II
::
MO_DLLIMPORT
;
bool
isDecl
=
GV
->
isDeclaration
(
)
&&
!
GV
->
hasNotBeenReadFromBitcode
(
)
;
if
(
isPICStyleRIPRel
(
)
)
{
if
(
TM
.
getCodeModel
(
)
==
CodeModel
::
Large
)
return
X86II
::
MO_NO_FLAG
;
if
(
isTargetDarwin
(
)
)
{
if
(
GV
->
hasDefaultVisibility
(
)
&&
(
isDecl
||
GV
->
isWeakForLinker
(
)
)
)
return
X86II
::
MO_GOTPCREL
;
}
else
{
assert
(
isTargetELF
(
)
&&
"Unknown rip-relative target"
)
;
if
(
!
GV
->
hasLocalLinkage
(
)
&&
GV
->
hasDefaultVisibility
(
)
)
return
X86II
::
MO_GOTPCREL
;
}
return
X86II
::
MO_NO_FLAG
;
}
if
(
isPICStyleGOT
(
)
)
{
if
(
GV
->
hasLocalLinkage
(
)
||
GV
->
hasHiddenVisibility
(
)
)
return
X86II
::
MO_GOTOFF
;
return
X86II
::
MO_GOT
;
}
if
(
isPICStyleStubPIC
(
)
)
{
if
(
!
isDecl
&&
!
GV
->
isWeakForLinker
(
)
)
return
X86II
::
MO_PIC_BASE_OFFSET
;
if
(
!
GV
->
hasHiddenVisibility
(
)
)
return
X86II
::
MO_DARWIN_NONLAZY_PIC_BASE
;
if
(
isDecl
||
GV
->
hasCommonLinkage
(
)
)
{
return
X86II
::
MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE
;
}
return
X86II
::
MO_PIC_BASE_OFFSET
;
}
if
(
isPICStyleStubNoDynamic
(
)
)
{
if
(
!
isDecl
&&
!
GV
->
isWeakForLinker
(
)
)
return
X86II
::
MO_NO_FLAG
;
if
(
!
GV
->
hasHiddenVisibility
(
)
)
return
X86II
::
MO_DARWIN_NONLAZY
;
if
(
isDecl
||
GV
->
hasCommonLinkage
(
)
)
{
return
X86II
::
MO_DARWIN_HIDDEN_NONLAZY
;
}
return
X86II
::
MO_NO_FLAG
;
}
return
X86II
::
MO_NO_FLAG
;
}
</s>

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be referenced for the current subtarget .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { GlobalBaseReg = 0 ; Subtarget = & MF . getSubtarget < PPCSubtarget > ( ) ; PPCLowering = Subtarget -> getTargetLowering ( ) ; if ( Subtarget -> hasROPProtect ( ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; PPCFunctionInfo * FI = MF . getInfo < PPCFunctionInfo > ( ) ; const int Result = MFI . CreateStackObject ( 8 , Align ( 8 ) , false ) ; FI -> setROPProtectionHashSaveIndex ( Result ) ; } SelectionDAGISel :: runOnMachineFunction ( MF ) ; return true ; } </s>


<s> void LC2200FrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const LC2200RegisterInfo * RI = STI . getRegisterInfo ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; unsigned StackAlign = getStackAlignment ( ) ; if ( RI -> needsStackRealignment ( MF ) ) { unsigned MaxStackAlign = std :: max ( StackAlign , MFI . getMaxAlignment ( ) ) ; FrameSize += ( MaxStackAlign - StackAlign ) ; StackAlign = MaxStackAlign ; } uint64_t MaxCallSize = alignTo ( MFI . getMaxCallFrameSize ( ) , StackAlign ) ; MFI . setMaxCallFrameSize ( MaxCallSize ) ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI . setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s>
static
void
arm_unwind_emit_set
(
FILE
*
asm_out_file
,
rtx
p
)
{
rtx
e0
;
rtx
e1
;
e0
=
XEXP
(
p
,
0
)
;
e1
=
XEXP
(
p
,
1
)
;
switch
(
GET_CODE
(
e0
)
)
{
case
MEM
:
if
(
GET_CODE
(
XEXP
(
e0
,
0
)
)
!=
PRE_DEC
||
GET_CODE
(
XEXP
(
XEXP
(
e0
,
0
)
,
0
)
)
!=
REG
||
REGNO
(
XEXP
(
XEXP
(
e0
,
0
)
,
0
)
)
!=
SP_REGNUM
)
abort
(
)
;
asm_fprintf
(
asm_out_file
,
"\t.save "
)
;
if
(
IS_VFP_REGNUM
(
REGNO
(
e1
)
)
)
asm_fprintf
(
asm_out_file
,
"{d%d}\n"
,
(
REGNO
(
e1
)
FIRST_VFP_REGNUM
)
/
2
)
;
else
asm_fprintf
(
asm_out_file
,
"{%r}\n"
,
REGNO
(
e1
)
)
;
break
;
case
REG
:
if
(
REGNO
(
e0
)
==
SP_REGNUM
)
{
if
(
GET_CODE
(
e1
)
!=
PLUS
||
GET_CODE
(
XEXP
(
e1
,
0
)
)
!=
REG
||
REGNO
(
XEXP
(
e1
,
0
)
)
!=
SP_REGNUM
||
GET_CODE
(
XEXP
(
e1
,
1
)
)
!=
CONST_INT
)
abort
(
)
;
asm_fprintf
(
asm_out_file
,
"\t.pad #%wd\n"
,
INTVAL
(
XEXP
(
e1
,
1
)
)
)
;
}
else
if
(
REGNO
(
e0
)
==
HARD_FRAME_POINTER_REGNUM
)
{
HOST_WIDE_INT
offset
;
unsigned
reg
;
if
(
GET_CODE
(
e1
)
==
PLUS
)
{
if
(
GET_CODE
(
XEXP
(
e1
,
0
)
)
!=
REG
||
GET_CODE
(
XEXP
(
e1
,
1
)
)
!=
CONST_INT
)
abort
(
)
;
reg
=
REGNO
(
XEXP
(
e1
,
0
)
)
;
offset
=
INTVAL
(
XEXP
(
e1
,
1
)
)
;
asm_fprintf
(
asm_out_file
,
"\t.setfp %r, %r, #%wd\n"
,
HARD_FRAME_POINTER_REGNUM
,
reg
,
INTVAL
(
XEXP
(
e1
,
1
)
)
)
;
}
else
if
(
GET_CODE
(
e1
)
==
REG
)
{
reg
=
REGNO
(
e1
)
;
asm_fprintf
(
asm_out_file
,
"\t.setfp %r, %r\n"
,
HARD_FRAME_POINTER_REGNUM
,
reg
)
;
}
else
abort
(
)
;
}
else
if
(
GET_CODE
(
e1
)
==
REG
&&
REGNO
(
e1
)
==
SP_REGNUM
)
{
asm_fprintf
(
asm_out_file
,
"\t.movsp %r\n"
,
REGNO
(
e0
)
)
;
}
else
abort
(
)
;
break
;
default
:
abort
(
)
;
}
}
</s>


<s> int sh_dwarf_calling_convention ( tree func ) { if ( sh_attr_renesas_p ( func ) ) return DW_CC_GNU_renesas_sh ; return DW_CC_normal ; } </s>

Implements target hook dwarf_calling_convention . Return an enum of dwarf_calling_convention .


<s> static rtx ix86_get_arg_address_for_bt ( rtx slot , rtx slot_no , rtx special_base ) { rtx addr = NULL ; if ( ! slot || REG_P ( slot ) ) { gcc_assert ( CONST_INT_P ( slot_no ) ) ; addr = plus_constant ( Pmode , special_base , - ( INTVAL ( slot_no ) + 1 ) * GET_MODE_SIZE ( Pmode ) ) ; } else if ( MEM_P ( slot ) ) { addr = XEXP ( slot , 0 ) ; if ( ! register_operand ( addr , Pmode ) ) addr = copy_addr_to_reg ( addr ) ; } else gcc_unreachable ( ) ; return addr ; } </s>

Helper function for ix86_load_bounds and ix86_store_bounds . Return an address to be used to load/store bounds for pointer passed in SLOT . SLOT_NO is an integer constant holding number of a target dependent special slot to be used in case SLOT is not a memory . SPECIAL_BASE is a pointer to be used as a base of fake address to access special slots in Bounds Table . SPECIAL_BASE [ -1 ] , SPECIAL_BASE [ -2 ] etc . will be used as fake pointer locations .


<s> const RISCVSubtarget * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override { if ( Count == 0 ) { return true ; } return false ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s>
virtual
const
char
*
getPassName
(
)
const
override
{
return
"AArch64 Store Pair Suppression"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void PPCRegisterInfo :: lowerACCSpilling ( MachineBasicBlock :: iterator II , unsigned FrameIndex ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; Register SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; bool IsKilled = MI . getOperand ( 0 ) . isKill ( ) ; bool IsPrimed = PPC :: ACCRCRegClass . contains ( SrcReg ) ; Register Reg = PPC :: VSRp0 + ( SrcReg - ( IsPrimed ? PPC :: ACC0 : PPC :: UACC0 ) ) * 2 ; bool IsLittleEndian = Subtarget . isLittleEndian ( ) ; emitAccSpillRestoreInfo ( MBB , IsPrimed , false ) ; if ( IsPrimed ) BuildMI ( MBB , II , DL , TII . get ( PPC :: XXMFACC ) , SrcReg ) . addReg ( SrcReg ) ; addFrameReference ( BuildMI ( MBB , II , DL , TII . get ( PPC :: STXVP ) ) . addReg ( Reg , getKillRegState ( IsKilled ) ) , FrameIndex , IsLittleEndian ? 32 : 0 ) ; addFrameReference ( BuildMI ( MBB , II , DL , TII . get ( PPC :: STXVP ) ) . addReg ( Reg + 1 , getKillRegState ( IsKilled ) ) , FrameIndex , IsLittleEndian ? 0 : 32 ) ; if ( IsPrimed && ! IsKilled ) BuildMI ( MBB , II , DL , TII . get ( PPC :: XXMTACC ) , SrcReg ) . addReg ( SrcReg ) ; MBB . erase ( II ) ; } </s>

lowerACCSpilling - Generate the code for spilling the accumulator register .


<s> static void s390_conditional_register_usage ( void ) { int i ; if ( flag_pic ) { fixed_regs [ PIC_OFFSET_TABLE_REGNUM ] = 1 ; call_used_regs [ PIC_OFFSET_TABLE_REGNUM ] = 1 ; } fixed_regs [ BASE_REGNUM ] = 0 ; call_used_regs [ BASE_REGNUM ] = 0 ; fixed_regs [ RETURN_REGNUM ] = 0 ; call_used_regs [ RETURN_REGNUM ] = 0 ; if ( TARGET_64BIT ) { for ( i = FPR8_REGNUM ; i <= FPR15_REGNUM ; i ++ ) call_used_regs [ i ] = call_really_used_regs [ i ] = 0 ; } else { call_used_regs [ FPR4_REGNUM ] = call_really_used_regs [ FPR4_REGNUM ] = 0 ; call_used_regs [ FPR6_REGNUM ] = call_really_used_regs [ FPR6_REGNUM ] = 0 ; } if ( TARGET_SOFT_FLOAT ) { for ( i = FPR0_REGNUM ; i <= FPR15_REGNUM ; i ++ ) call_used_regs [ i ] = fixed_regs [ i ] = 1 ; } if ( ! TARGET_VX ) { for ( i = VR16_REGNUM ; i <= VR31_REGNUM ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = call_really_used_regs [ i ] = 1 ; } } </s>


<s> static machine_mode spu_addr_space_address_mode ( addr_space_t addrspace ) { switch ( addrspace ) { case ADDR_SPACE_GENERIC : return Pmode ; case ADDR_SPACE_EA : return EAmode ; default : gcc_unreachable ( ) ; } } </s>

Return the appropriate mode for a named address address .


<s> int const_ok_for_dimode_op ( HOST_WIDE_INT i , enum rtx_code code ) { HOST_WIDE_INT hi_val = ( i >> 32 ) & 0xFFFFFFFF ; HOST_WIDE_INT lo_val = i & 0xFFFFFFFF ; rtx hi = GEN_INT ( hi_val ) ; rtx lo = GEN_INT ( lo_val ) ; if ( TARGET_THUMB1 ) return 0 ; switch ( code ) { case AND : case IOR : case XOR : return ( const_ok_for_op ( hi_val , code ) || hi_val == 0xFFFFFFFF ) && ( const_ok_for_op ( lo_val , code ) || lo_val == 0xFFFFFFFF ) ; case PLUS : return arm_not_operand ( hi , SImode ) && arm_add_operand ( lo , SImode ) ; default : return 0 ; } } </s>

Return true if I is a valid di mode constant for the operation CODE .


<s> void PPCPassConfig :: addPreEmitPass ( ) { addPass ( createPPCPreEmitPeepholePass ( ) ) ; addPass ( createPPCExpandISELPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCEarlyReturnPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> const char * SystemZTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case SystemZISD :: RET_FLAG : return "SystemZISD::RET_FLAG" ; case SystemZISD :: CALL : return "SystemZISD::CALL" ; case SystemZISD :: BRCOND : return "SystemZISD::BRCOND" ; case SystemZISD :: CMP : return "SystemZISD::CMP" ; case SystemZISD :: UCMP : return "SystemZISD::UCMP" ; case SystemZISD :: SELECT : return "SystemZISD::SELECT" ; case SystemZISD :: PCRelativeWrapper : return "SystemZISD::PCRelativeWrapper" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific

SystemZ SystemZ SystemZISD::RET_FLAG "SystemZISD::RET_FLAG" SystemZISD::CALL "SystemZISD::CALL" SystemZISD::BRCOND "SystemZISD::BRCOND" SystemZISD::CMP "SystemZISD::CMP" SystemZISD::UCMP "SystemZISD::UCMP" SystemZISD::SELECT "SystemZISD::SELECT" SystemZISD::PCRelativeWrapper "SystemZISD::PCRelativeWrapper"


<s> void XCoreTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; DataSection = Ctx . getELFSection ( ".dp.data" , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_ALLOC | MCSectionELF :: SHF_WRITE | MCSectionELF :: XCORE_SHF_DP_SECTION , SectionKind :: getDataRel ( ) , false ) ; BSSSection = Ctx . getELFSection ( ".dp.bss" , MCSectionELF :: SHT_NOBITS , MCSectionELF :: SHF_ALLOC | MCSectionELF :: SHF_WRITE | MCSectionELF :: XCORE_SHF_DP_SECTION , SectionKind :: getBSS ( ) , false ) ; MergeableConst4Section = Ctx . getELFSection ( ".cp.rodata.cst4" , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_ALLOC | MCSectionELF :: SHF_MERGE | MCSectionELF :: XCORE_SHF_CP_SECTION , SectionKind :: getMergeableConst4 ( ) , false ) ; MergeableConst8Section = Ctx . getELFSection ( ".cp.rodata.cst8" , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_ALLOC | MCSectionELF :: SHF_MERGE | MCSectionELF :: XCORE_SHF_CP_SECTION , SectionKind :: getMergeableConst8 ( ) , false ) ; MergeableConst16Section = Ctx . getELFSection ( ".cp.rodata.cst16" , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_ALLOC | MCSectionELF :: SHF_MERGE | MCSectionELF :: XCORE_SHF_CP_SECTION , SectionKind :: getMergeableConst16 ( ) , false ) ; TLSDataSection = DataSection ; TLSBSSSection = BSSSection ; ReadOnlySection = Ctx . getELFSection ( ".cp.rodata" , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_ALLOC | MCSectionELF :: XCORE_SHF_CP_SECTION , SectionKind :: getReadOnlyWithRel ( ) , false ) ; DataRelSection = DataRelLocalSection = DataSection ; DataRelROSection = DataRelROLocalSection = ReadOnlySection ; } </s>

This method must be called before any actual lowering is done .


<s> static bool rs6000_parm_needs_stack ( cumulative_args_t args_so_far , tree type ) { machine_mode mode ; int unsignedp ; rtx entry_parm ; if ( type == NULL || type == error_mark_node ) return true ; if ( TYPE_MODE ( type ) == VOIDmode ) return false ; if ( TREE_CODE ( type ) == COMPLEX_TYPE ) return ( rs6000_parm_needs_stack ( args_so_far , TREE_TYPE ( type ) ) || rs6000_parm_needs_stack ( args_so_far , TREE_TYPE ( type ) ) ) ; if ( ( TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == RECORD_TYPE ) && TYPE_TRANSPARENT_AGGR ( type ) ) type = TREE_TYPE ( first_field ( type ) ) ; if ( pass_by_reference ( get_cumulative_args ( args_so_far ) , TYPE_MODE ( type ) , type , true ) ) type = build_pointer_type ( type ) ; unsignedp = TYPE_UNSIGNED ( type ) ; mode = promote_mode ( type , TYPE_MODE ( type ) , & unsignedp ) ; if ( rs6000_must_pass_in_stack ( mode , type ) ) return true ; entry_parm = rs6000_function_arg ( args_so_far , mode , type , true ) ; if ( entry_parm == NULL ) return true ; if ( GET_CODE ( entry_parm ) == PARALLEL && XEXP ( XVECEXP ( entry_parm , 0 , 0 ) , 0 ) == NULL_RTX ) return true ; if ( rs6000_arg_partial_bytes ( args_so_far , mode , type , true ) != 0 ) return true ; rs6000_function_arg_advance ( args_so_far , mode , type , true ) ; return false ; } </s>

Process parameter of type TYPE after ARGS_SO_FAR parameters were already processes . Return true if the parameter must be passed ( fully or partially ) on the stack .


<s>
void
Cpu0SEInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
=
0
,
ZeroReg
=
0
;
if
(
Cpu0
::
CPURegsRegClass
.
contains
(
DestReg
)
)
{
if
(
Cpu0
::
CPURegsRegClass
.
contains
(
SrcReg
)
)
Opc
=
Cpu0
::
ADDu
,
ZeroReg
=
Cpu0
::
ZERO
;
else
if
(
SrcReg
==
Cpu0
::
HI
)
Opc
=
Cpu0
::
MFHI
,
SrcReg
=
0
;
else
if
(
SrcReg
==
Cpu0
::
LO
)
Opc
=
Cpu0
::
MFLO
,
SrcReg
=
0
;
}
else
if
(
Cpu0
::
CPURegsRegClass
.
contains
(
SrcReg
)
)
{
if
(
DestReg
==
Cpu0
::
HI
)
Opc
=
Cpu0
::
MTHI
,
DestReg
=
0
;
else
if
(
DestReg
==
Cpu0
::
LO
)
Opc
=
Cpu0
::
MTLO
,
DestReg
=
0
;
}
assert
(
Opc
&&
"Cannot copy registers"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
)
;
if
(
DestReg
)
MIB
.
addReg
(
DestReg
,
RegState
::
Define
)
;
if
(
ZeroReg
)
MIB
.
addReg
(
ZeroReg
)
;
if
(
SrcReg
)
MIB
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> static rtx mips_frame_set ( rtx mem , rtx reg ) { rtx set ; set = gen_rtx_SET ( VOIDmode , mem , reg ) ; RTX_FRAME_RELATED_P ( set ) = 1 ; return set ; } </s>

Return a frame-related rtx that stores register REGNO at ( SP + OFFSET ) . The expression should only be used to store single registers .


<s> SMLoc getStartLoc ( ) const override { return Start ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> bool ia64_const_double_ok_for_letter_p ( rtx value , char c ) { switch ( c ) { case 'G' : return CONST_DOUBLE_OK_FOR_G ( value ) ; default : return false ; } } </s>


<s> static void xtensa_conditional_register_usage ( void ) { unsigned i , c_mask ; c_mask = TARGET_WINDOWED_ABI ? ( 1 << 1 ) : ( 1 << 2 ) ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { if ( call_used_regs [ i ] > 1 ) call_used_regs [ i ] = ! ! ( call_used_regs [ i ] & c_mask ) ; } CLEAR_HARD_REG_BIT ( reg_class_contents [ ( int ) RL_REGS ] , HARD_FRAME_POINTER_REGNUM ) ; } </s>

Update register usage after having seen the compiler flags .


<s> void AArch64PassConfig :: addPreRegBankSelect ( ) { bool IsOptNone = getOptLevel ( ) == CodeGenOpt :: None ; if ( ! IsOptNone ) { addPass ( createAArch64PostLegalizerCombiner ( IsOptNone ) ) ; if ( EnableGISelLoadStoreOptPostLegal ) addPass ( new LoadStoreOpt ( ) ) ; } addPass ( createAArch64PostLegalizerLowering ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before the register bank selection .


<s> bool PIC16TargetMachine :: addPostRegAlloc ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createPIC16MemSelOptimizerPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> static tree alpha_fold_builtin_insxx ( tree op [ ] , unsigned HOST_WIDE_INT opint [ ] , long op_const , unsigned HOST_WIDE_INT bytemask , bool is_high ) { if ( ( op_const & 1 ) && opint [ 0 ] == 0 ) return build_int_cst ( alpha_dimode_u , 0 ) ; if ( op_const & 2 ) { unsigned HOST_WIDE_INT temp , loc , byteloc ; tree * zap_op = NULL ; loc = opint [ 1 ] & 7 ; bytemask <<= loc ; temp = opint [ 0 ] ; if ( is_high ) { byteloc = ( 64 - ( loc * 8 ) ) & 0x3f ; if ( byteloc == 0 ) zap_op = op ; else temp >>= byteloc ; bytemask >>= 8 ; } else { byteloc = loc * 8 ; if ( byteloc == 0 ) zap_op = op ; else temp <<= byteloc ; } opint [ 0 ] = temp ; opint [ 1 ] = bytemask ; return alpha_fold_builtin_zapnot ( zap_op , opint , op_const ) ; } return NULL ; } </s>

Fold the builtins for the INS family of instructions .


<s> ScheduleHazardRecognizer * PPCInstrInfo :: CreateTargetHazardRecognizer ( const TargetSubtargetInfo * STI , const ScheduleDAG * DAG ) const { unsigned Directive = static_cast < const PPCSubtarget * > ( STI ) -> getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_440 || Directive == PPC :: DIR_A2 || Directive == PPC :: DIR_E500mc || Directive == PPC :: DIR_E5500 ) { const InstrItineraryData * II = static_cast < const PPCSubtarget * > ( STI ) -> getInstrItineraryData ( ) ; return new ScoreboardHazardRecognizer ( II , DAG ) ; } return TargetInstrInfo :: CreateTargetHazardRecognizer ( STI , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .


<s> const TeakRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .