<s> unsigned int compute_plussi_length ( rtx * operands , bool need_flags ) { machine_mode mode = GET_MODE ( operands [ 0 ] ) ; gcc_assert ( mode == SImode ) ; if ( GET_CODE ( operands [ 2 ] ) == CONST_INT && register_operand ( operands [ 1 ] , VOIDmode ) ) { HOST_WIDE_INT intval = INTVAL ( operands [ 2 ] ) ; if ( TARGET_H8300SX && ( intval >= 1 && intval <= 7 ) ) return 2 ; if ( TARGET_H8300SX && ( intval >= - 7 && intval <= - 1 ) ) return 2 ; switch ( ( unsigned int ) intval & 0xffffffff ) { case 0x00000001 : case 0x00000002 : return 2 ; case 0x00000004 : if ( need_flags ) return 6 ; else return 2 ; case 0xffffffff : case 0xfffffffe : return 2 ; case 0xfffffffc : if ( need_flags ) return 6 ; else return 2 ; case 0x00010000 : case 0x00020000 : if ( ! need_flags ) return 2 ; case 0xffff0000 : case 0xfffe0000 : if ( ! need_flags ) return 2 ; } if ( ( intval & 0xffff ) == 0 ) return 4 ; } if ( GET_CODE ( operands [ 2 ] ) == CONST_INT && INTVAL ( operands [ 2 ] ) < 0 ) return h8300_length_from_table ( operands [ 0 ] , GEN_INT ( - INTVAL ( operands [ 2 ] ) ) , & addl_length_table ) ; else return h8300_length_from_table ( operands [ 0 ] , operands [ 2 ] , & addl_length_table ) ; } </s>

Compute the length of an addition insn .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
ARM
::
NumTargetFixupKinds
]
=
{
{
"fixup_arm_ldst_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_ldst_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_pcrel_10_unscaled"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_pcrel_10"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_pcrel_10"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_thumb_adr_pcrel_10"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_adr_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_adr_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_condbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_uncondbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_condbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_uncondbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_br"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_bl"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_blx"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cb"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cp"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_bcc"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> bool XtensaInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { default : return false ; } } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> static rtx frv_function_value ( const_tree valtype , const_tree fn_decl_or_type ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( TYPE_MODE ( valtype ) , RETURN_VALUE_REGNUM ) ; } </s>


<s> static void tilegx_print_operand_address ( FILE * file , machine_mode mode , rtx addr ) { if ( GET_CODE ( addr ) == POST_DEC || GET_CODE ( addr ) == POST_INC ) { int offset = GET_MODE_SIZE ( mode ) ; gcc_assert ( mode != VOIDmode ) ; if ( output_memory_autoinc_first ) fprintf ( file , "%s" , reg_names [ REGNO ( XEXP ( addr , 0 ) ) ] ) ; else fprintf ( file , "%d" , GET_CODE ( addr ) == POST_DEC ? - offset : offset ) ; } else if ( GET_CODE ( addr ) == POST_MODIFY ) { gcc_assert ( mode != VOIDmode ) ; gcc_assert ( GET_CODE ( XEXP ( addr , 1 ) ) == PLUS ) ; if ( output_memory_autoinc_first ) fprintf ( file , "%s" , reg_names [ REGNO ( XEXP ( addr , 0 ) ) ] ) ; else fprintf ( file , HOST_WIDE_INT_PRINT_DEC , INTVAL ( XEXP ( XEXP ( addr , 1 ) , 1 ) ) ) ; } else tilegx_print_operand ( file , addr , 'r' ) ; } </s>


<s> void vax_expand_prologue ( void ) { int regno , offset ; int mask = 0 ; HOST_WIDE_INT size ; rtx insn ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) mask |= 1 << regno ; insn = emit_insn ( gen_procedure_entry_mask ( GEN_INT ( mask ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; vax_add_reg_cfa_offset ( insn , 4 , arg_pointer_rtx ) ; vax_add_reg_cfa_offset ( insn , 8 , frame_pointer_rtx ) ; vax_add_reg_cfa_offset ( insn , 12 , pc_rtx ) ; offset = 16 ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( mask & ( 1 << regno ) ) { vax_add_reg_cfa_offset ( insn , offset , gen_rtx_REG ( SImode , regno ) ) ; offset += 4 ; } add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , frame_pointer_rtx , offset ) ) ; size = get_frame_size ( ) ; size -= vax_starting_frame_offset ( ) ; emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - size ) ) ) ; emit_insn ( gen_blockage ( ) ) ; } </s>

Generate the assembly code for function entry . FILE is a stdio stream to output the code to . SIZE is an int : how many units of temporary storage to allocate . Refer to the array ` regs_ever_live ' to determine which registers to save ; ` regs_ever_live [ I ] ' is nonzero if register number I is ever used in the function . This function is responsible for knowing which registers should not be saved even if used .


<s>
unsigned
LC3MCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
{
return
CTX
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
}
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
assert
(
MO
.
isExpr
(
)
&&
"unknown operand kind in printOperand"
)
;
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
MCExpr
::
ExprKind
Kind
=
Expr
->
getKind
(
)
;
if
(
Kind
==
MCExpr
::
Binary
)
{
Expr
=
static_cast
<
const
MCBinaryExpr
*
>
(
Expr
)
->
getLHS
(
)
;
Kind
=
Expr
->
getKind
(
)
;
}
assert
(
Kind
==
MCExpr
::
SymbolRef
)
;
unsigned
FixupKind
;
switch
(
cast
<
MCSymbolRefExpr
>
(
Expr
)
->
getKind
(
)
)
{
default
:
llvm_unreachable
(
"Unknown fixup kind!"
)
;
case
MCSymbolRefExpr
::
VK_LC3_LO
:
{
FixupKind
=
LC3
::
fixup_lc3_mov_lo16_pcrel
;
break
;
}
case
MCSymbolRefExpr
::
VK_LC3_HI
:
{
FixupKind
=
LC3
::
fixup_lc3_mov_hi16_pcrel
;
break
;
}
}
Fixups
.
push_back
(
MCFixup
::
create
(
0
,
MO
.
getExpr
(
)
,
MCFixupKind
(
FixupKind
)
)
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> void initialize ( ScheduleDAGMI * dag ) override { } </s>

Initialize the strategy after building the DAG for a new region .


<s>
const
char
*
getPassName
(
)
const
{
return
"TOY PreRegAlloc"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"NEON reg-reg move conversion"
;
}
</s>


<s> bool AArch64AsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { unsigned Kind = Fixup . getKind ( ) ; if ( Kind >= FirstLiteralRelocationKind ) return true ; if ( Kind == AArch64 :: fixup_aarch64_pcrel_adrp_imm21 ) return true ; return false ; } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> bool m68k_use_return_insn ( void ) { if ( ! reload_completed || frame_pointer_needed || get_frame_size ( ) != 0 ) return false ; m68k_compute_frame_layout ( ) ; return current_frame . offset == 0 ; } </s>

Return true if a simple ( return ) instruction is sufficient for this instruction ( i.e . if no epilogue is needed ) .


<s> bool WebAssemblyFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const auto * RegInfo = MF . getSubtarget < WebAssemblySubtarget > ( ) . getRegisterInfo ( ) ; return MFI -> hasCalls ( ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MFI -> hasStackMap ( ) || MFI -> hasPatchPoint ( ) || RegInfo -> needsStackRealignment ( MF ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void FISCInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool LanaiInstrInfo :: getMemOperandWithOffset ( MachineInstr & LdSt , MachineOperand * & BaseOp , int64_t & Offset , const TargetRegisterInfo * TRI ) const { switch ( LdSt . getOpcode ( ) ) { default : return false ; case Lanai :: LDW_RI : case Lanai :: LDW_RR : case Lanai :: SW_RR : case Lanai :: SW_RI : case Lanai :: LDHs_RI : case Lanai :: LDHz_RI : case Lanai :: STH_RI : case Lanai :: LDBs_RI : case Lanai :: LDBz_RI : unsigned Width ; return getMemOperandWithOffsetWidth ( LdSt , BaseOp , Offset , Width , TRI ) ; } } </s>

Get the base operand and byte offset of an instruction that reads/writes memory .


<s> int simple_memory_operand ( rtx op , machine_mode mode ATTRIBUTE_UNUSED ) { rtx addr ; if ( GET_CODE ( op ) != MEM ) return FALSE ; if ( GET_MODE_SIZE ( GET_MODE ( op ) ) > ( HAVE_64BIT_P ( ) ? 8 : 4 ) ) return FALSE ; indirection : addr = XEXP ( op , 0 ) ; switch ( GET_CODE ( addr ) ) { case REG : return 1 ; case PRE_DEC : case POST_INC : return 0 ; case MEM : if ( GET_CODE ( XEXP ( addr , 0 ) ) == REG ) return 0 ; op = addr ; goto indirection ; case CONST_INT : case LABEL_REF : case CONST : case SYMBOL_REF : return 0 ; case PLUS : return 0 ; default : break ; } return FALSE ; } </s>

Return truth value if a memory operand fits in a single instruction ( ie , register + small offset ) .


<s> MachineInstrBuilder SIInstrInfo :: buildIndirectWrite ( MachineBasicBlock * MBB , MachineBasicBlock :: iterator I , unsigned ValueReg , unsigned Address , unsigned OffsetReg ) const { llvm_unreachable ( "Unimplemented" ) ; } </s>

Build instruction ( s ) for an indirect register write .


<s> void PPCRegisterInfo :: lowerCRSpilling ( MachineBasicBlock :: iterator II , unsigned FrameIndex ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = TM . isPPC64 ( ) ; const TargetRegisterClass * G8RC = & PPC :: G8RCRegClass ; const TargetRegisterClass * GPRC = & PPC :: GPRCRegClass ; Register Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; Register SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: MFOCRF8 : PPC :: MFOCRF ) , Reg ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( 0 ) . isKill ( ) ) ) ; if ( SrcReg != PPC :: CR0 ) { Register Reg1 = Reg ; Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: RLWINM8 : PPC :: RLWINM ) , Reg ) . addReg ( Reg1 , RegState :: Kill ) . addImm ( getEncodingValue ( SrcReg ) * 4 ) . addImm ( 0 ) . addImm ( 31 ) ; } addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: STW8 : PPC :: STW ) ) . addReg ( Reg , RegState :: Kill ) , FrameIndex ) ; MBB . erase ( II ) ; } </s>

lowerCRSpilling - Generate the code for spilling a CR register .


<s> static std :: unique_ptr < MipsOperand > CreateReg ( unsigned Index , RegKind RegKind , const MCRegisterInfo * RegInfo , SMLoc S , SMLoc E , MipsAsmParser & Parser ) { auto Op = make_unique < MipsOperand > ( k_RegisterIndex , Parser ) ; Op -> RegIdx . Index = Index ; Op -> RegIdx . RegInfo = RegInfo ; Op -> RegIdx . Kind = RegKind ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> RCPair ARMTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: tGPRRegClass ) ; return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'h' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: hGPRRegClass ) ; break ; case 'r' : if ( Subtarget -> isThumb1Only ( ) ) return RCPair ( 0U , & ARM :: tGPRRegClass ) ; return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'w' : if ( VT == MVT :: Other ) break ; if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPRRegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPRRegClass ) ; break ; case 'x' : if ( VT == MVT :: Other ) break ; if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPR_8RegClass ) ; break ; case 't' : if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( ARM :: CPSR ) , & ARM :: CCRRegClass ) ; return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> unsigned GCNHazardRecognizer :: PreEmitNoops ( MachineInstr * MI ) { int WaitStates = std :: max ( 0 , checkAnyInstHazards ( MI ) ) ; if ( SIInstrInfo :: isSMRD ( * MI ) ) return std :: max ( WaitStates , checkSMRDHazards ( MI ) ) ; if ( SIInstrInfo :: isVALU ( * MI ) ) WaitStates = std :: max ( WaitStates , checkVALUHazards ( MI ) ) ; if ( SIInstrInfo :: isVMEM ( * MI ) || SIInstrInfo :: isFLAT ( * MI ) ) WaitStates = std :: max ( WaitStates , checkVMEMHazards ( MI ) ) ; if ( SIInstrInfo :: isDPP ( * MI ) ) WaitStates = std :: max ( WaitStates , checkDPPHazards ( MI ) ) ; if ( isDivFMas ( MI -> getOpcode ( ) ) ) WaitStates = std :: max ( WaitStates , checkDivFMasHazards ( MI ) ) ; if ( isRWLane ( MI -> getOpcode ( ) ) ) WaitStates = std :: max ( WaitStates , checkRWLaneHazards ( MI ) ) ; if ( MI -> isInlineAsm ( ) ) return std :: max ( WaitStates , checkInlineAsmHazards ( MI ) ) ; if ( isSGetReg ( MI -> getOpcode ( ) ) ) return std :: max ( WaitStates , checkGetRegHazards ( MI ) ) ; if ( isSSetReg ( MI -> getOpcode ( ) ) ) return std :: max ( WaitStates , checkSetRegHazards ( MI ) ) ; if ( isRFE ( MI -> getOpcode ( ) ) ) return std :: max ( WaitStates , checkRFEHazards ( MI ) ) ; if ( ST . hasReadM0MovRelInterpHazard ( ) && ( TII . isVINTRP ( * MI ) || isSMovRel ( MI -> getOpcode ( ) ) ) ) return std :: max ( WaitStates , checkReadM0Hazards ( MI ) ) ; if ( ST . hasReadM0SendMsgHazard ( ) && isSendMsgTraceDataOrGDS ( * MI ) ) return std :: max ( WaitStates , checkReadM0Hazards ( MI ) ) ; return WaitStates ; } </s>

PreEmitNoops - This callback is invoked prior to emitting an instruction .


<s> static void epiphany_setup_incoming_varargs ( cumulative_args_t cum , const function_arg_info & arg , int * pretend_size , int no_rtl ) { int first_anon_arg ; CUMULATIVE_ARGS next_cum ; machine_function_t * mf = MACHINE_FUNCTION ( cfun ) ; gcc_assert ( arg . mode != BLKmode ) ; next_cum = * get_cumulative_args ( cum ) ; next_cum = ( ROUND_ADVANCE_CUM ( next_cum , arg . mode , arg . type ) + ROUND_ADVANCE_ARG ( arg . mode , arg . type ) ) ; first_anon_arg = next_cum ; if ( first_anon_arg < MAX_EPIPHANY_PARM_REGS && ! no_rtl ) { int first_reg_offset = first_anon_arg ; * pretend_size = ( ( MAX_EPIPHANY_PARM_REGS - first_reg_offset ) * UNITS_PER_WORD ) ; } mf -> args_parsed = 1 ; mf -> pretend_args_odd = ( ( * pretend_size & UNITS_PER_WORD ) ? 1 : 0 ) ; } </s>

Do any needed setup for a variadic function . For the EPIPHANY , we actually emit the code in epiphany_expand_prologue . CUM has not been updated for the last named argument which has type TYPE and mode MODE , and we rely on this fact .


<s> bool RISCVTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; Optional < unsigned > FirstMaskArgument ; if ( Subtarget . hasStdExtV ( ) ) FirstMaskArgument = preAssignMask ( Outs ) ; for ( unsigned i = 0 , e = Outs . size ( ) ; i != e ; ++ i ) { MVT VT = Outs [ i ] . VT ; ISD :: ArgFlagsTy ArgFlags = Outs [ i ] . Flags ; RISCVABI :: ABI ABI = MF . getSubtarget < RISCVSubtarget > ( ) . getTargetABI ( ) ; if ( CC_RISCV ( MF . getDataLayout ( ) , ABI , i , VT , VT , CCValAssign :: Full , ArgFlags , CCInfo , true , true , nullptr , * this , FirstMaskArgument ) ) return false ; } return true ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .

RISCV RISCV ISD::OutputArg 16 0 ISD::ArgFlagsTy RISCVABI::ABI RISCV RISCV


<s>
const
char
*
arm_output_iwmmxt_tinsr
(
rtx
*
operands
)
{
int
mask
=
INTVAL
(
operands
[
3
]
)
;
int
i
;
char
templ
[
50
]
;
int
units
=
mode_nunits
[
GET_MODE
(
operands
[
0
]
)
]
;
gcc_assert
(
(
mask
&
(
mask
1
)
)
==
0
)
;
for
(
i
=
0
;
i
<
units
;
++
i
)
{
if
(
(
mask
&
0x01
)
==
1
)
{
break
;
}
mask
>>=
1
;
}
gcc_assert
(
i
<
units
)
;
{
switch
(
GET_MODE
(
operands
[
0
]
)
)
{
case
V8QImode
:
sprintf
(
templ
,
"tinsrb%%?\t%%0, %%2, #%d"
,
i
)
;
break
;
case
V4HImode
:
sprintf
(
templ
,
"tinsrh%%?\t%%0, %%2, #%d"
,
i
)
;
break
;
case
V2SImode
:
sprintf
(
templ
,
"tinsrw%%?\t%%0, %%2, #%d"
,
i
)
;
break
;
default
:
gcc_unreachable
(
)
;
break
;
}
output_asm_insn
(
templ
,
operands
)
;
}
return
""
;
}
</s>

Output assembly for a WMMX tinsr instruction .


<s> bool HexagonRegisterInfo :: shouldCoalesce ( MachineInstr * MI , const TargetRegisterClass * SrcRC , unsigned SubReg , const TargetRegisterClass * DstRC , unsigned DstSubReg , const TargetRegisterClass * NewRC , LiveIntervals & LIS ) const { MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const HexagonSubtarget & HST = MF . getSubtarget < HexagonSubtarget > ( ) ; if ( ! HST . useHVXOps ( ) || NewRC -> getID ( ) != Hexagon :: HvxWRRegClass . getID ( ) ) return true ; bool SmallSrc = SrcRC -> getID ( ) == Hexagon :: HvxVRRegClass . getID ( ) ; bool SmallDst = DstRC -> getID ( ) == Hexagon :: HvxVRRegClass . getID ( ) ; if ( ! SmallSrc && ! SmallDst ) return true ; unsigned DstReg = MI -> getOperand ( 0 ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; const SlotIndexes & Indexes = * LIS . getSlotIndexes ( ) ; auto HasCall = [ & Indexes ] ( const LiveInterval :: Segment & S ) { for ( SlotIndex I = S . start . getBaseIndex ( ) , E = S . end . getBaseIndex ( ) ; I != E ; I = I . getNextIndex ( ) ) { if ( const MachineInstr * MI = Indexes . getInstructionFromIndex ( I ) ) if ( MI -> isCall ( ) ) return true ; } return false ; } ; if ( SmallSrc == SmallDst ) { return ! any_of ( LIS . getInterval ( DstReg ) , HasCall ) && ! any_of ( LIS . getInterval ( SrcReg ) , HasCall ) ; } unsigned SmallReg = SmallSrc ? SrcReg : DstReg ; unsigned LargeReg = SmallSrc ? DstReg : SrcReg ; return any_of ( LIS . getInterval ( LargeReg ) , HasCall ) || ! any_of ( LIS . getInterval ( SmallReg ) , HasCall ) ; } </s>

Hexagon Hexagon Hexagon Hexagon Hexagon::HvxWRRegClass Hexagon::HvxVRRegClass Hexagon::HvxVRRegClass 0 1


<s> bool isThumb ( ) const { return ( STI . getFeatureBits ( ) & ARM :: ModeThumb ) != 0 ; } </s>

Tests whether the target is Thumb ( little and big endian ) .


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetOptions & Options ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , stackAlignment ( 4 ) , CPUString ( CPU ) , TargetTriple ( TT ) , Options ( Options ) , TargetABI ( ARM_ABI_APCS ) { initializeEnvironment ( ) ; resetSubtargetFeatures ( CPU , FS ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s>
unsigned
IA64RegisterInfo
::
getRARegister
(
)
const
{
assert
(
0
&&
"What is the return address register"
)
;
return
0
;
}
</s>

This method should return the register where the return address can be found .


<s> static void mips_block_move_loop ( rtx dest , rtx src , HOST_WIDE_INT length , HOST_WIDE_INT bytes_per_iter ) { rtx_code_label * label ; rtx src_reg , dest_reg , final_src , test ; HOST_WIDE_INT leftover ; leftover = length % bytes_per_iter ; length -= leftover ; mips_adjust_block_mem ( src , bytes_per_iter , & src_reg , & src ) ; mips_adjust_block_mem ( dest , bytes_per_iter , & dest_reg , & dest ) ; final_src = expand_simple_binop ( Pmode , PLUS , src_reg , GEN_INT ( length ) , 0 , 0 , OPTAB_WIDEN ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; mips_block_move_straight ( dest , src , bytes_per_iter ) ; mips_emit_move ( src_reg , plus_constant ( Pmode , src_reg , bytes_per_iter ) ) ; mips_emit_move ( dest_reg , plus_constant ( Pmode , dest_reg , bytes_per_iter ) ) ; test = gen_rtx_NE ( VOIDmode , src_reg , final_src ) ; if ( Pmode == DImode ) emit_jump_insn ( gen_cbranchdi4 ( test , src_reg , final_src , label ) ) ; else emit_jump_insn ( gen_cbranchsi4 ( test , src_reg , final_src , label ) ) ; if ( leftover ) mips_block_move_straight ( dest , src , leftover ) ; else emit_insn ( gen_nop ( ) ) ; } </s>

Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES per iteration . LENGTH must be at least MAX_MOVE_BYTES . Assume that the memory regions do not overlap .


<s>
SDValue
TGSITargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
)
const
{
SDValue
Flag
;
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
ccinfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
ccinfo
.
AnalyzeReturn
(
Outs
,
RetCC_TGSI
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"CCValAssign must be RegLoc"
)
;
unsigned
Reg
=
VA
.
getLocReg
(
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
Reg
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
TGSIISD
::
RET
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
else
return
DAG
.
getNode
(
TGSIISD
::
RET
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .

TGSI
TGSI
ISD::OutputArg
16
TGSI
0
"CCValAssign must be RegLoc"
1
TGSIISD::RET
MVT::Other
TGSIISD::RET
MVT::Other


<s> static bool nios2_rtx_costs ( rtx x , machine_mode mode ATTRIBUTE_UNUSED , int outer_code ATTRIBUTE_UNUSED , int opno ATTRIBUTE_UNUSED , int * total , bool speed ATTRIBUTE_UNUSED ) { int code = GET_CODE ( x ) ; switch ( code ) { case CONST_INT : if ( INTVAL ( x ) == 0 ) { * total = COSTS_N_INSNS ( 0 ) ; return true ; } else if ( nios2_simple_const_p ( x ) ) { * total = COSTS_N_INSNS ( 2 ) ; return true ; } else { * total = COSTS_N_INSNS ( 4 ) ; return true ; } case LABEL_REF : case SYMBOL_REF : case CONST : case CONST_DOUBLE : { * total = COSTS_N_INSNS ( 4 ) ; return true ; } case AND : { if ( GET_CODE ( XEXP ( x , 0 ) ) == NOT && GET_CODE ( XEXP ( x , 1 ) ) == NOT ) { * total = COSTS_N_INSNS ( 1 ) ; return true ; } return false ; } case MULT : { * total = COSTS_N_INSNS ( 1 ) ; return false ; } case SIGN_EXTEND : { * total = COSTS_N_INSNS ( 3 ) ; return false ; } case ZERO_EXTEND : { * total = COSTS_N_INSNS ( 1 ) ; return false ; } case ZERO_EXTRACT : if ( TARGET_HAS_BMX ) { * total = COSTS_N_INSNS ( 1 ) ; return true ; } default : return false ; } } </s>

Compute a ( partial ) cost for rtx X . Return true if the complete cost has been computed , and false if subexpressions should be scanned . In either case , * TOTAL contains the cost result .


<s> void Cpu0SEFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; Cpu0MachineFunctionInfo * Cpu0FI = MF . getInfo < Cpu0MachineFunctionInfo > ( ) ; const Cpu0SEInstrInfo & TII = * static_cast < const Cpu0SEInstrInfo * > ( STI . getInstrInfo ( ) ) ; const Cpu0RegisterInfo & RegInfo = * static_cast < const Cpu0RegisterInfo * > ( STI . getRegisterInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; Cpu0ABIInfo ABI = STI . getABI ( ) ; unsigned SP = Cpu0 :: SP ; unsigned FP = Cpu0 :: FP ; unsigned ZERO = Cpu0 :: ZERO ; unsigned ADDu = Cpu0 :: ADDu ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI . getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( ADDu ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( Cpu0FI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = & Cpu0 :: GPROutRegClass ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI . getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = 0 ; J < ABI . EhDataRegSize ( ) ; ++ J ) { TII . loadRegFromStackSlot ( MBB , I , ABI . GetEhDataReg ( J ) , Cpu0FI -> getEhDataRegFI ( J ) , RC , & RegInfo ) ; } } uint64_t StackSize = MFI . getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize , MBB , MBBI ) ; } </s>


<s> static void or1k_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int nreg = CEIL ( GET_MODE_SIZE ( arg . mode ) , UNITS_PER_WORD ) ; gcc_assert ( nreg <= 2 ) ; if ( arg . named ) * cum += nreg ; } </s>

Worker for TARGET_FUNCTION_ARG_ADVANCE . Update the cumulative args descriptor CUM_V to advance past the next function argument . Note , this is not called for arguments passed on the stack .


<s> unsigned MipsSEInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( ( Opc == Mips :: LW ) || ( Opc == Mips :: LD ) || ( Opc == Mips :: LWC1 ) || ( Opc == Mips :: LDC1 ) || ( Opc == Mips :: LDC164 ) ) { if ( ( MI -> getOperand ( 1 ) . isFI ( ) ) && ( MI -> getOperand ( 2 ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( 2 ) ) ) ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s>
void
dump
(
)
{
errs
(
)
<<
"SystemZRRIAddressMode "
<<
this
<<
'\n'
;
if
(
BaseType
==
RegBase
)
{
errs
(
)
<<
"Base.Reg "
;
if
(
Base
.
Reg
.
getNode
(
)
!=
0
)
Base
.
Reg
.
getNode
(
)
->
dump
(
)
;
else
errs
(
)
<<
"nul"
;
errs
(
)
<<
'\n'
;
}
else
{
errs
(
)
<<
" Base.FrameIndex "
<<
Base
.
FrameIndex
<<
'\n'
;
}
if
(
!
isRI
)
{
errs
(
)
<<
"IndexReg "
;
if
(
IndexReg
.
getNode
(
)
!=
0
)
IndexReg
.
getNode
(
)
->
dump
(
)
;
else
errs
(
)
<<
"nul"
;
}
errs
(
)
<<
" Disp "
<<
Disp
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

SystemZ
"SystemZRRIAddressMode "
"Base.Reg "
0
"nul"
" Base.FrameIndex "
"IndexReg "
0
"nul"
" Disp "


<s> bool FPGATTIImpl :: isLegalICmpImmediate ( int64_t Imm ) { return true ; } </s>

Return true if the specified immediate is legal icmp immediate , that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register .


<s> SDValue SITargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( N ) ; EVT VT = N -> getValueType ( 0 ) ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: SELECT_CC : { ConstantSDNode * True , * False ; if ( ( True = dyn_cast < ConstantSDNode > ( N -> getOperand ( 2 ) ) ) && ( False = dyn_cast < ConstantSDNode > ( N -> getOperand ( 3 ) ) ) && True -> isAllOnesValue ( ) && False -> isNullValue ( ) && VT == MVT :: i1 ) { return DAG . getNode ( ISD :: SETCC , DL , VT , N -> getOperand ( 0 ) , N -> getOperand ( 1 ) , N -> getOperand ( 4 ) ) ; } break ; } case ISD :: SETCC : { SDValue Arg0 = N -> getOperand ( 0 ) ; SDValue Arg1 = N -> getOperand ( 1 ) ; SDValue CC = N -> getOperand ( 2 ) ; ConstantSDNode * C = NULL ; ISD :: CondCode CCOp = dyn_cast < CondCodeSDNode > ( CC ) -> get ( ) ; if ( VT == MVT :: i1 && Arg0 . getOpcode ( ) == ISD :: SIGN_EXTEND && Arg0 . getOperand ( 0 ) . getValueType ( ) == MVT :: i1 && ( C = dyn_cast < ConstantSDNode > ( Arg1 ) ) && C -> isNullValue ( ) && CCOp == ISD :: SETNE ) { return SimplifySetCC ( VT , Arg0 . getOperand ( 0 ) , DAG . getConstant ( 0 , MVT :: i1 ) , CCOp , true , DCI , DL ) ; } break ; } } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> const char * RISCVTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { case RISCVISD :: NODE : \ return "RISCVISD::" # NODE ; switch ( ( RISCVISD :: NodeType ) Opcode ) { case RISCVISD :: FIRST_NUMBER : break ; NODE_NAME_CASE ( RET_FLAG ) NODE_NAME_CASE ( URET_FLAG ) NODE_NAME_CASE ( SRET_FLAG ) NODE_NAME_CASE ( MRET_FLAG ) NODE_NAME_CASE ( CALL ) NODE_NAME_CASE ( SELECT_CC ) NODE_NAME_CASE ( BuildPairF64 ) NODE_NAME_CASE ( SplitF64 ) NODE_NAME_CASE ( TAIL ) NODE_NAME_CASE ( SLLW ) NODE_NAME_CASE ( SRAW ) NODE_NAME_CASE ( SRLW ) NODE_NAME_CASE ( DIVW ) NODE_NAME_CASE ( DIVUW ) NODE_NAME_CASE ( REMUW ) NODE_NAME_CASE ( ROLW ) NODE_NAME_CASE ( RORW ) NODE_NAME_CASE ( FSLW ) NODE_NAME_CASE ( FSRW ) NODE_NAME_CASE ( FMV_H_X ) NODE_NAME_CASE ( FMV_X_ANYEXTH ) NODE_NAME_CASE ( FMV_W_X_RV64 ) NODE_NAME_CASE ( FMV_X_ANYEXTW_RV64 ) NODE_NAME_CASE ( READ_CYCLE_WIDE ) NODE_NAME_CASE ( GREVI ) NODE_NAME_CASE ( GREVIW ) NODE_NAME_CASE ( GORCI ) NODE_NAME_CASE ( GORCIW ) NODE_NAME_CASE ( VMV_X_S ) NODE_NAME_CASE ( SPLAT_VECTOR_I64 ) NODE_NAME_CASE ( READ_VLENB ) NODE_NAME_CASE ( TRUNCATE_VECTOR ) NODE_NAME_CASE ( VLEFF ) NODE_NAME_CASE ( VLEFF_MASK ) NODE_NAME_CASE ( VLSEGFF ) NODE_NAME_CASE ( VLSEGFF_MASK ) NODE_NAME_CASE ( READ_VL ) NODE_NAME_CASE ( VSLIDEUP ) NODE_NAME_CASE ( VSLIDEDOWN ) NODE_NAME_CASE ( VID ) } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

RI5CY RISCV RISCVISD::NODE "RISCVISD::" RISCVISD::NodeType RISCVISD::FIRST_NUMBER


<s>
uint32_t
AMDGPUTargetLowering
::
getImplicitParameterOffset
(
const
AMDGPUMachineFunction
*
MFI
,
const
ImplicitParameter
Param
)
const
{
unsigned
Alignment
=
Subtarget
->
getAlignmentForImplicitArgPtr
(
)
;
uint64_t
ArgOffset
=
alignTo
(
MFI
->
getABIArgOffset
(
)
,
Alignment
)
;
switch
(
Param
)
{
case
GRID_DIM
:
return
ArgOffset
;
case
GRID_OFFSET
:
return
ArgOffset
+
4
;
}
llvm_unreachable
(
"unexpected implicit parameter type"
)
;
}
</s>

Helper function that returns the byte offset of the given type of implicit parameter .

AMDGPU
AMDGPU
AMDGPU
4
"unexpected implicit parameter type"


<s> unsigned GCNHazardRecognizer :: PreEmitNoops ( MachineInstr * MI ) { if ( SIInstrInfo :: isSMRD ( * MI ) ) return std :: max ( 0 , checkSMRDHazards ( MI ) ) ; if ( SIInstrInfo :: isVALU ( * MI ) ) { int WaitStates = std :: max ( 0 , checkVALUHazards ( MI ) ) ; if ( SIInstrInfo :: isVMEM ( * MI ) ) WaitStates = std :: max ( WaitStates , checkVMEMHazards ( MI ) ) ; if ( SIInstrInfo :: isDPP ( * MI ) ) WaitStates = std :: max ( WaitStates , checkDPPHazards ( MI ) ) ; if ( isDivFMas ( MI -> getOpcode ( ) ) ) WaitStates = std :: max ( WaitStates , checkDivFMasHazards ( MI ) ) ; if ( isRWLane ( MI -> getOpcode ( ) ) ) WaitStates = std :: max ( WaitStates , checkRWLaneHazards ( MI ) ) ; return WaitStates ; } if ( isSGetReg ( MI -> getOpcode ( ) ) ) return std :: max ( 0 , checkGetRegHazards ( MI ) ) ; if ( isSSetReg ( MI -> getOpcode ( ) ) ) return std :: max ( 0 , checkSetRegHazards ( MI ) ) ; if ( isRFE ( MI -> getOpcode ( ) ) ) return std :: max ( 0 , checkRFEHazards ( MI ) ) ; return 0 ; } </s>

PreEmitNoops - This callback is invoked prior to emitting an instruction .


<s> static enum unwind_info_type bpf_debug_unwind_info ( ) { return UI_NONE ; } </s>

Define the mechanism that will be used for describing frame unwind information to the debugger . In eBPF it is not possible to unwind frames .


<s> static unsigned aarch64_add_stmt_cost ( void * data , int count , enum vect_cost_for_stmt kind , struct _stmt_vec_info * stmt_info , int misalign , enum vect_cost_model_location where ) { unsigned * cost = ( unsigned * ) data ; unsigned retval = 0 ; if ( flag_vect_cost_model ) { tree vectype = stmt_info ? stmt_vectype ( stmt_info ) : NULL_TREE ; int stmt_cost = aarch64_builtin_vectorization_cost ( kind , vectype , misalign ) ; if ( stmt_info && vectype && aarch64_sve_mode_p ( TYPE_MODE ( vectype ) ) ) stmt_cost = aarch64_sve_adjust_stmt_cost ( kind , stmt_info , vectype , stmt_cost ) ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( stmt_info ) ) count *= 50 ; retval = ( unsigned ) ( count * stmt_cost ) ; cost [ where ] += retval ; } return retval ; } </s>


<s> bool M680x0InstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { MachineInstrBuilder MIB ( * MI . getParent ( ) -> getParent ( ) , MI ) ; switch ( MI . getOpcode ( ) ) { case M680x0 :: PUSH8d : return ExpandPUSH_POP ( MIB , get ( M680x0 :: MOV8ed ) , true ) ; case M680x0 :: PUSH16d : return ExpandPUSH_POP ( MIB , get ( M680x0 :: MOV16er ) , true ) ; case M680x0 :: PUSH32r : return ExpandPUSH_POP ( MIB , get ( M680x0 :: MOV32er ) , true ) ; case M680x0 :: POP8d : return ExpandPUSH_POP ( MIB , get ( M680x0 :: MOV8do ) , false ) ; case M680x0 :: POP16d : return ExpandPUSH_POP ( MIB , get ( M680x0 :: MOV16ro ) , false ) ; case M680x0 :: POP32r : return ExpandPUSH_POP ( MIB , get ( M680x0 :: MOV32ro ) , false ) ; case M680x0 :: SETCS_C8d : return Expand2AddrUndef ( MIB , get ( M680x0 :: SUBX8dd ) ) ; case M680x0 :: SETCS_C16d : return Expand2AddrUndef ( MIB , get ( M680x0 :: SUBX16dd ) ) ; case M680x0 :: SETCS_C32d : return Expand2AddrUndef ( MIB , get ( M680x0 :: SUBX32dd ) ) ; } return false ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> bool R600InstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumTCycles , unsigned ExtraTCycles , MachineBasicBlock & FMBB , unsigned NumFCycles , unsigned ExtraFCycles , BranchProbability Probability ) const { return true ; } </s>


"TPC does not support costs based purely on Types. Use the "


<s> void mips_output_aligned_bss ( FILE * stream , tree decl , const char * name , unsigned HOST_WIDE_INT size , int align ) { extern tree last_assemble_variable_decl ; if ( mips_in_small_data_p ( decl ) ) named_section ( 0 , ".sbss" , 0 ) ; else bss_section ( ) ; ASM_OUTPUT_ALIGN ( stream , floor_log2 ( align / BITS_PER_UNIT ) ) ; last_assemble_variable_decl = decl ; ASM_DECLARE_OBJECT_NAME ( stream , name , decl ) ; ASM_OUTPUT_SKIP ( stream , size != 0 ? size : 1 ) ; } </s>

Implement ASM_OUTPUT_ALIGNED_BSS . This differs from the default only in the use of sbss .


<s> static rtx rs6000_expand_zeroop_builtin ( enum insn_code icode , rtx target ) { rtx pat ; machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; if ( icode == CODE_FOR_nothing ) return 0 ; if ( target == 0 || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; pat = GEN_FCN ( icode ) ( target ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>

Expand an expression EXP that calls a builtin without arguments .


<s> void MipsSEInstrInfo :: adjustStackPtr ( unsigned SP , int64_t Amount , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const MipsSubtarget & STI = TM . getSubtarget < MipsSubtarget > ( ) ; DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned ADDu = STI . isABI_N64 ( ) ? Mips :: DADDu : Mips :: ADDu ; unsigned ADDiu = STI . isABI_N64 ( ) ? Mips :: DADDiu : Mips :: ADDiu ; if ( isInt < 16 > ( Amount ) ) BuildMI ( MBB , I , DL , get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; else { unsigned Reg = loadImmediate ( Amount , MBB , I , DL , 0 ) ; BuildMI ( MBB , I , DL , get ( ADDu ) , SP ) . addReg ( SP ) . addReg ( Reg , RegState :: Kill ) ; } } </s>

Mips Mips Mips Mips Mips::DADDu Mips::ADDu Mips::DADDiu Mips::ADDiu 16 0


<s> SITargetLowering :: ConstraintType SITargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 's' : case 'v' : case 'a' : return C_RegisterClass ; case 'A' : return C_Other ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s>
char
*
emit_cond_move
(
rtx
*
operands
,
rtx
insn
ATTRIBUTE_UNUSED
)
{
static
char
buffer
[
100
]
;
const
char
*
dest
=
reg_names
[
REGNO
(
operands
[
0
]
)
]
;
buffer
[
0
]
=
0
;
gcc_assert
(
GET_CODE
(
operands
[
0
]
)
==
REG
)
;
gcc_assert
(
conditional_move_operand
(
operands
[
2
]
,
SImode
)
)
;
gcc_assert
(
conditional_move_operand
(
operands
[
3
]
,
SImode
)
)
;
if
(
GET_CODE
(
operands
[
1
]
)
==
NE
)
{
rtx
tmp
=
operands
[
2
]
;
operands
[
2
]
=
operands
[
3
]
;
operands
[
3
]
=
tmp
;
}
sprintf
(
buffer
,
"mvfc %s, cbr"
,
dest
)
;
if
(
INTVAL
(
operands
[
2
]
)
==
0
)
sprintf
(
buffer
+
strlen
(
buffer
)
,
"\n\txor3 %s, %s, #1"
,
dest
,
dest
)
;
return
buffer
;
}
</s>

Generate the correct assembler code to handle the conditional loading of a value into a register . It is known that the operands satisfy the conditional_move_operand ( ) function above . The destination is operand [ 0 ] . The condition is operand [ 1 ] . The 'true ' value is operand [ 2 ] and the 'false ' value is operand [ 3 ] .


Return an array that contains the direct target flag values and their names .


<s> static void arm_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain_value ) { rtx fnaddr , mem , a_tramp ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp , SImode , TARGET_32BIT ? 8 : 12 ) ; emit_move_insn ( mem , chain_value ) ; mem = adjust_address ( m_tramp , SImode , TARGET_32BIT ? 12 : 16 ) ; fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; emit_move_insn ( mem , fnaddr ) ; a_tramp = XEXP ( m_tramp , 0 ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , "__clear_cache" ) , LCT_NORMAL , VOIDmode , 2 , a_tramp , Pmode , plus_constant ( Pmode , a_tramp , TRAMPOLINE_SIZE ) , Pmode ) ; } </s>

Emit RTL insns to initialize the variable parts of a trampoline .


<s> bool SIPeepholeSDWA :: runOnMachineFunction ( MachineFunction & MF ) { const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; if ( ! ST . hasSDWA ( ) || skipFunction ( MF . getFunction ( ) ) ) return false ; MRI = & MF . getRegInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; TII = ST . getInstrInfo ( ) ; bool Ret = false ; for ( MachineBasicBlock & MBB : MF ) { bool Changed = false ; do { matchSDWAOperands ( MBB ) ; for ( const auto & OperandPair : SDWAOperands ) { const auto & Operand = OperandPair . second ; MachineInstr * PotentialMI = Operand -> potentialToConvert ( TII ) ; if ( PotentialMI && isConvertibleToSDWA ( * PotentialMI , ST ) ) { PotentialMatches [ PotentialMI ] . push_back ( Operand . get ( ) ) ; } } for ( auto & PotentialPair : PotentialMatches ) { MachineInstr & PotentialMI = * PotentialPair . first ; convertToSDWA ( PotentialMI , PotentialPair . second ) ; } PotentialMatches . clear ( ) ; SDWAOperands . clear ( ) ; Changed = ! ConvertedInstructions . empty ( ) ; if ( Changed ) Ret = true ; while ( ! ConvertedInstructions . empty ( ) ) legalizeScalarOperands ( * ConvertedInstructions . pop_back_val ( ) , ST ) ; } while ( Changed ) ; } return Ret ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool HexagonInstrInfo :: isPredicated ( const MachineInstr * MI ) const { const uint64_t F = MI -> getDesc ( ) . TSFlags ; return ( F >> HexagonII :: PredicatedPos ) & HexagonII :: PredicatedMask ; } </s>

Returns true if the instruction is already predicated .

Hexagon Hexagon HexagonII::PredicatedPos HexagonII::PredicatedMask


<s> SMLoc getLoc ( ) { return getParser ( ) . getTok ( ) . getLoc ( ) ; } </s>

Get the source location of the point where the field was defined .


<s>
void
TPCMachineScheduler
::
schedule
(
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"********** TPC MI Scheduling BB#"
<<
BB
->
getNumber
(
)
<<
" "
<<
BB
->
getName
(
)
<<
" in_func "
<<
BB
->
getParent
(
)
->
getFunction
(
)
.
getName
(
)
<<
" at loop depth "
<<
MLI
->
getLoopDepth
(
BB
)
<<
" \n"
)
;
LLVM_DEBUG
(
SchedImpl
->
dumpPolicy
(
)
)
;
buildDAGWithRegPressure
(
)
;
postprocessDAG
(
)
;
SmallVector
<
SUnit
*
,
8
>
TopRoots
,
BotRoots
;
findRootsAndBiasEdges
(
TopRoots
,
BotRoots
)
;
SchedImpl
->
initialize
(
this
)
;
LLVM_DEBUG
(
unsigned
maxH
=
0
;
for
(
unsigned
su
=
0
,
e
=
SUnits
.
size
(
)
;
su
!=
e
;
++
su
)
if
(
SUnits
[
su
]
.
getHeight
(
)
>
maxH
)
maxH
=
SUnits
[
su
]
.
getHeight
(
)
;
dbgs
(
)
<<
"Max Height "
<<
maxH
<<
"\n"
;
)
;
LLVM_DEBUG
(
unsigned
maxD
=
0
;
for
(
unsigned
su
=
0
,
e
=
SUnits
.
size
(
)
;
su
!=
e
;
++
su
)
if
(
SUnits
[
su
]
.
getDepth
(
)
>
maxD
)
maxD
=
SUnits
[
su
]
.
getDepth
(
)
;
dbgs
(
)
<<
"Max Depth "
<<
maxD
<<
"\n"
;
)
;
LLVM_DEBUG
(
for
(
unsigned
su
=
0
,
e
=
SUnits
.
size
(
)
;
su
!=
e
;
++
su
)
dumpNode
(
SUnits
[
su
]
)
;
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"--- Scheduled DAG ---\n"
;
dump
(
)
;
dbgs
(
)
<<
"--- End of scheduled DAG ---\n"
;
)
;
if
(
TPCViewMISchedDAGs
)
viewGraph
(
)
;
initQueues
(
TopRoots
,
BotRoots
)
;
bool
IsTopNode
=
false
;
while
(
true
)
{
SUnit
*
SU
=
SchedImpl
->
pickNode
(
IsTopNode
)
;
if
(
!
SU
)
break
;
if
(
!
checkSchedLimit
(
)
)
break
;
scheduleMI
(
SU
,
IsTopNode
)
;
SchedImpl
->
schedNode
(
SU
,
IsTopNode
)
;
updateQueues
(
SU
,
IsTopNode
)
;
}
placeDebugValues
(
)
;
LLVM_DEBUG
(
{
unsigned
BBNum
=
begin
(
)
->
getParent
(
)
->
getNumber
(
)
;
dbgs
(
)
<<
"*** Final schedule for BB#"
<<
BBNum
<<
" ***\n"
;
dumpSchedule
(
)
;
dbgs
(
)
<<
'\n'
<<
"**********\n"
;
}
)
;
}
</s>

Schedule - This is called back from ScheduleDAGInstrs : :Run ( ) when it 's time to do some work .

TPC
TPC
"********** TPC MI Scheduling BB#"
" "
" in_func "
" at loop depth "
" \n"
8
0
0
"Max Height "
"\n"
0
0
"Max Depth "
"\n"
0
"--- Scheduled DAG ---\n"
"--- End of scheduled DAG ---\n"
TPC
"*** Final schedule for BB#"
" ***\n"
"**********\n"


<s> int io ( int from , int to ) { int regs_saved ; calc_live_regs ( & regs_saved ) ; int total_saved_regs_space = ( regs_saved ) * 2 ; int total_auto_space = get_frame_size ( ) ; int pcsize = TARGET_BIG ? 4 : 2 ; if ( from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM ) { return total_saved_regs_space + pcsize ; } if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) { return total_saved_regs_space + total_auto_space + pcsize ; } if ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) { return total_auto_space ; } if ( from == RETURN_ADDRESS_POINTER_REGNUM && to == FRAME_POINTER_REGNUM ) { return total_saved_regs_space ; } if ( from == RETURN_ADDRESS_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) { return total_saved_regs_space + total_auto_space ; } gcc_unreachable ( ) ; } </s>

INITIAL_ELIMINATION_OFFSET specifies the initial difference between the specified pair of registers , and must be defined if ELIMINABLE_REGS is defined .


<s>
const
Constant
*
X86TargetLowering
::
getTargetConstantFromLoad
(
LoadSDNode
*
LD
)
const
{
assert
(
LD
&&
"Unexpected null LoadSDNode"
)
;
return
getTargetConstantFromNode
(
LD
)
;
}
</s>

This method returns the constant pool value that will be loaded by LD .


"insertBranch must not be told to insert a fallthrough"

"# of Mips branch conditions must be <= 3!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> unsigned getNumberOfRegisters ( unsigned ClassID ) const { bool VectorRegs = ( ClassID == 1 ) ; if ( VectorRegs ) { return 0 ; } return 64 ; } </s>


"ARM constant island placement and branch shortening pass"

getPassName - Return a nice clean name for a pass .


<s> static void pop ( int regno ) { rtx x ; x = emit_insn ( gen_movsi_pop ( gen_rtx_REG ( Pmode , regno ) , stack_pointer_rtx ) ) ; add_reg_note ( x , REG_INC , stack_pointer_rtx ) ; } </s>

Output RTL to pop register RN from the stack .


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) -> findAssociatedFragment ( ) ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s> unsigned PPCDispatchGroupSBHazardRecognizer :: PreEmitNoops ( SUnit * SU ) { if ( isLoadAfterStore ( SU ) && CurSlots < 6 ) { unsigned Directive = DAG -> MF . getSubtarget < PPCSubtarget > ( ) . getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_PWR6 || Directive == PPC :: DIR_PWR7 || Directive == PPC :: DIR_PWR8 || Directive == PPC :: DIR_PWR9 ) return 1 ; return 5 - CurSlots ; } return ScoreboardHazardRecognizer :: PreEmitNoops ( SU ) ; } </s>

PreEmitNoops - This callback is invoked prior to emitting an instruction .


<s> static void frv_reorder_packet ( void ) { unsigned int cursor [ NUM_GROUPS ] ; rtx_insn * insns [ ARRAY_SIZE ( frv_unit_groups ) ] ; unsigned int unit , to , from ; enum frv_insn_group group ; struct frv_packet_group * packet_group ; for ( group = GROUP_I ; group < NUM_GROUPS ; group = ( enum frv_insn_group ) ( group + 1 ) ) { cursor [ group ] = 0 ; frv_sort_insn_group ( group ) ; } to = 0 ; for ( unit = 0 ; unit < ARRAY_SIZE ( frv_unit_groups ) ; unit ++ ) { group = frv_unit_groups [ unit ] ; packet_group = & frv_packet . groups [ group ] ; if ( cursor [ group ] < packet_group -> num_insns ) { gcc_assert ( packet_group -> sorted [ cursor [ group ] ] != packet_group -> nop ) ; insns [ to ++ ] = packet_group -> sorted [ cursor [ group ] ++ ] ; } } gcc_assert ( to == frv_packet . num_insns ) ; CLEAR_PACKING_FLAG ( insns [ to - 1 ] ) ; for ( from = 0 ; from < to - 1 ; from ++ ) { remove_insn ( insns [ from ] ) ; add_insn_before ( insns [ from ] , insns [ to - 1 ] , NULL ) ; SET_PACKING_FLAG ( insns [ from ] ) ; } } </s>

Sort the current packet into assembly-language order . Set packing flags as appropriate .


<s> bool LC3RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> bool PPCAsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { std :: string NewOpcode ; if ( parseOptionalToken ( AsmToken :: Plus ) ) { NewOpcode = Name ; NewOpcode += '+' ; Name = NewOpcode ; } if ( parseOptionalToken ( AsmToken :: Minus ) ) { NewOpcode = Name ; NewOpcode += '-' ; Name = NewOpcode ; } size_t Dot = Name . find ( '.' ) ; StringRef Mnemonic = Name . slice ( 0 , Dot ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( PPCOperand :: CreateTokenWithStringCopy ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; else Operands . push_back ( PPCOperand :: CreateToken ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; if ( Dot != StringRef :: npos ) { SMLoc DotLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Dot ) ; StringRef DotStr = Name . slice ( Dot , StringRef :: npos ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( PPCOperand :: CreateTokenWithStringCopy ( DotStr , DotLoc , isPPC64 ( ) ) ) ; else Operands . push_back ( PPCOperand :: CreateToken ( DotStr , DotLoc , isPPC64 ( ) ) ) ; } if ( parseOptionalToken ( AsmToken :: EndOfStatement ) ) return false ; if ( ParseOperand ( Operands ) ) return true ; while ( ! parseOptionalToken ( AsmToken :: EndOfStatement ) ) { if ( parseToken ( AsmToken :: Comma ) || ParseOperand ( Operands ) ) return true ; } if ( getSTI ( ) . getFeatureBits ( ) [ PPC :: FeatureBookE ] && Operands . size ( ) == 4 && ( Name == "dcbt" || Name == "dcbtst" ) ) { std :: swap ( Operands [ 1 ] , Operands [ 3 ] ) ; std :: swap ( Operands [ 2 ] , Operands [ 1 ] ) ; } return false ; } </s>

ParseInstruction - Parse one assembly instruction .

PowerPC PPC 0 PPC PPC PPC PPC PPC PPC PPC PPC PPC::FeatureBookE 4 "dcbt" "dcbtst" 1 3 2 1


<s> bool nds32_expand_cpymemsi ( rtx dstmem , rtx srcmem , rtx total_bytes , rtx alignment ) { if ( nds32_expand_cpymemsi_unroll ( dstmem , srcmem , total_bytes , alignment ) ) return true ; if ( ! optimize_size && optimize > 2 ) return nds32_expand_cpymemsi_loop ( dstmem , srcmem , total_bytes , alignment ) ; return false ; } </s>

Function to move block memory content by using load_multiple and store_multiple . This is auxiliary extern function to help create rtx template . Check nds32-multiple.md file for the patterns .


<s> void AMDGPUPassConfig :: addIRPasses ( ) { disablePass ( & StackMapLivenessID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & PatchableFunctionID ) ; addPass ( createAMDGPUAlwaysInlinePass ( ) ) ; addPass ( createAlwaysInlinerPass ( ) ) ; addPass ( createBarrierNoopPass ( ) ) ; addPass ( createAMDGPUOpenCLImageTypeLoweringPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static bool arm_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { if ( TARGET_BIG_END && ! ( GET_MODE_SIZE ( from ) == 16 && GET_MODE_SIZE ( to ) == 8 ) && ( GET_MODE_SIZE ( from ) > UNITS_PER_WORD || GET_MODE_SIZE ( to ) > UNITS_PER_WORD ) && reg_classes_intersect_p ( VFP_REGS , rclass ) ) return false ; return true ; } </s>

Implement TARGET_CAN_CHANGE_MODE_CLASS . In VFPv1 , VFP registers could only be accessed in the mode they were set , so subregs would be invalid there . However , we do n't support VFPv1 at the moment , and the restriction was lifted in VFPv2 . In big-endian mode , modes greater than word size ( i.e . DFmode ) are stored in VFP registers in little-endian order . We ca n't describe that accurately to GCC , so avoid taking subregs of such values . The only exception is going from a 128-bit to a 64-bit type . In that case the data layout happens to be consistent for big-endian , so we explicitly allow that case .


<s> bool shouldReduceLoadWidth ( SDNode * Load , ISD :: LoadExtType ExtTy , EVT NewVT ) const override { return false ; } </s>

Return true if we believe it is correct and profitable to reduce the load node to a smaller type .


<s> void P2AsmPrinter :: emitFunctionBodyStart ( ) { MCInstLowering . Initialize ( & MF -> getContext ( ) ) ; } </s>

Targets can override this to emit stuff before the first basic block in the function .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { TM = static_cast < const PPCTargetMachine * > ( & MF . getTarget ( ) ) ; TII = TM -> getSubtargetImpl ( ) -> getInstrInfo ( ) ; bool Changed = false ; if ( MF . size ( ) < 2 ) return Changed ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed = true ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( AFI -> getGlobalBaseReg ( ) == 0 ) return false ; const ARMTargetMachine * TM = static_cast < const ARMTargetMachine * > ( & MF . getTarget ( ) ) ; if ( TM -> getRelocationModel ( ) != Reloc :: PIC_ ) return false ; LLVMContext * Context = & MF . getFunction ( ) -> getContext ( ) ; unsigned ARMPCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = TM -> getSubtarget < ARMSubtarget > ( ) . isThumb ( ) ? 4 : 8 ; ARMConstantPoolValue * CPV = ARMConstantPoolSymbol :: Create ( * Context , "_GLOBAL_OFFSET_TABLE_" , ARMPCLabelIndex , PCAdj ) ; unsigned Align = TM -> getDataLayout ( ) -> getPrefTypeAlignment ( Type :: getInt32PtrTy ( * Context ) ) ; unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; unsigned Opc = TM -> getSubtarget < ARMSubtarget > ( ) . isThumb2 ( ) ? ARM :: t2LDRpci : ARM :: LDRcp ; const TargetInstrInfo & TII = * TM -> getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == ARM :: LDRcp ) MIB . addImm ( 0 ) ; AddDefaultPred ( MIB ) ; return true ; } </s>

ARM ARM ARM 0 ARM ARM ARM ARM 4 8 ARM ARM "_GLOBAL_OFFSET_TABLE_" ARM ARM ARM::t2LDRpci ARM::LDRcp ARM::LDRcp 0


<s> bool X86PassConfig :: addPreRegAlloc ( ) { if ( EnableStackPointerTest ) { addPass ( createStackPointerTester ( getX86TargetMachine ( ) ) ) ; } return false ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static bool nios2_valid_addr_expr_p ( rtx base , rtx offset , bool strict_p ) { if ( ! strict_p && GET_CODE ( base ) == SUBREG ) base = SUBREG_REG ( base ) ; return ( REG_P ( base ) && nios2_regno_ok_for_base_p ( REGNO ( base ) , strict_p ) && ( offset == NULL_RTX || const_arith_operand ( offset , Pmode ) || nios2_unspec_reloc_p ( offset ) ) ) ; } </s>

Return true if the address expression formed by BASE + OFFSET is valid .


<s> const SICTargetLowering * SICTargetLowering :: create ( const SICTargetMachine & TM , const SICSubtarget & STI ) { return new SICTargetLowering ( TM , STI ) ; } </s>


"naked attribute only applies to functions"


"conversion from address space %qs to address space %qs"


<s> const MCExpr * AArch64_MachoTargetObjectFile :: getTTypeGlobalReference ( const GlobalValue * GV , unsigned Encoding , Mangler & Mang , const TargetMachine & TM , MachineModuleInfo * MMI , MCStreamer & Streamer ) const { if ( Encoding & ( DW_EH_PE_indirect | DW_EH_PE_pcrel ) ) { const MCSymbol * Sym = TM . getSymbol ( GV , Mang ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_GOT , getContext ( ) ) ; MCSymbol * PCSym = getContext ( ) . CreateTempSymbol ( ) ; Streamer . EmitLabel ( PCSym ) ; const MCExpr * PC = MCSymbolRefExpr :: Create ( PCSym , getContext ( ) ) ; return MCBinaryExpr :: CreateSub ( Res , PC , getContext ( ) ) ; } return TargetLoweringObjectFileMachO :: getTTypeGlobalReference ( GV , Encoding , Mang , TM , MMI , Streamer ) ; } </s>

The mach-o version of this method defaults to returning a stub reference .


<s> void split_subsi ( rtx * operands ) { int val = INTVAL ( operands [ 1 ] ) ; if ( arc_check_short_reg_p ( operands [ 0 ] ) && arc_check_short_reg_p ( operands [ 2 ] ) ) { if ( val >= - 31 && val <= 127 ) { operands [ 3 ] = gen_rtx_NEG ( SImode , operands [ 2 ] ) ; operands [ 4 ] = gen_rtx_PLUS ( SImode , operands [ 0 ] , operands [ 1 ] ) ; return ; } else if ( val >= 0 && val < 255 ) { operands [ 3 ] = operands [ 1 ] ; operands [ 4 ] = gen_rtx_MINUS ( SImode , operands [ 0 ] , operands [ 2 ] ) ; return ; } } operands [ 3 ] = operands [ 2 ] ; operands [ 4 ] = gen_rtx_MINUS ( SImode , operands [ 1 ] , operands [ 0 ] ) ; } </s>

Operands 0 .. 2 are the operands of a subsi which uses a 12 bit constant in operand 1 , but which would require a LIMM because of operand mismatch . operands 3 and 4 are new SET_SRCs for operands 0 .


<s> static bool expand_vec_perm_identity ( struct expand_vec_perm_d * d ) { unsigned i , nelt = d -> nelt ; for ( i = 0 ; i < nelt ; ++ i ) if ( d -> perm [ i ] != i ) return false ; if ( ! d -> testing_p ) emit_move_insn ( d -> target , d -> op0 ) ; return true ; } </s>


<s> const SystemZSubtarget * SystemZTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool softFloat = F . hasFnAttribute ( "use-soft-float" ) && F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( softFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < SystemZSubtarget > ( TargetTriple , CPU , FS , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

SystemZ SystemZ SystemZ "target-cpu" "target-features" "use-soft-float" "use-soft-float" "true" "+soft-float" ",+soft-float" SystemZ


<s> bool isLittleEndian ( ) const { return isLittle ; } </s>

Tests whether the target triple is little endian .


<s> static void nvptx_goacc_reduction_fini ( gcall * call ) { gimple_stmt_iterator gsi = gsi_for_stmt ( call ) ; tree lhs = gimple_call_lhs ( call ) ; tree ref_to_res = gimple_call_arg ( call , 1 ) ; tree var = gimple_call_arg ( call , 2 ) ; int level = TREE_INT_CST_LOW ( gimple_call_arg ( call , 3 ) ) ; enum tree_code op = ( enum tree_code ) TREE_INT_CST_LOW ( gimple_call_arg ( call , 4 ) ) ; gimple_seq seq = NULL ; tree r = NULL_TREE ; ; push_gimplify_context ( true ) ; if ( level == GOMP_DIM_VECTOR ) { for ( int shfl = PTX_VECTOR_LENGTH / 2 ; shfl > 0 ; shfl = shfl >> 1 ) { tree other_var = make_ssa_name ( TREE_TYPE ( var ) ) ; nvptx_generate_vector_shuffle ( gimple_location ( call ) , other_var , var , shfl , & seq ) ; r = make_ssa_name ( TREE_TYPE ( var ) ) ; gimplify_assign ( r , fold_build2 ( op , TREE_TYPE ( var ) , var , other_var ) , & seq ) ; var = r ; } } else { tree accum = NULL_TREE ; if ( level == GOMP_DIM_WORKER ) { tree offset = gimple_call_arg ( call , 5 ) ; tree call = nvptx_get_worker_red_addr ( TREE_TYPE ( var ) , offset ) ; tree ptr = make_ssa_name ( TREE_TYPE ( call ) ) ; gimplify_assign ( ptr , call , & seq ) ; accum = ptr ; } else if ( integer_zerop ( ref_to_res ) ) r = var ; else accum = ref_to_res ; if ( accum ) { gsi_insert_seq_before ( & gsi , seq , GSI_SAME_STMT ) ; seq = NULL ; r = nvptx_reduction_update ( gimple_location ( call ) , & gsi , accum , var , op ) ; } } if ( lhs ) gimplify_assign ( lhs , r , & seq ) ; pop_gimplify_context ( NULL ) ; gsi_replace_with_seq ( & gsi , seq , true ) ; } </s>

NVPTX implementation of GOACC_REDUCTION_FINI .


<s> const char * AArch64TargetLowering :: LowerXConstraint ( EVT ConstraintVT ) const { if ( ! Subtarget -> hasFPARMv8 ( ) ) return "r" ; if ( ConstraintVT . isFloatingPoint ( ) ) return "w" ; if ( ConstraintVT . isVector ( ) && ( ConstraintVT . getSizeInBits ( ) == 64 || ConstraintVT . getSizeInBits ( ) == 128 ) ) return "w" ; return "r" ; } </s>

Try to replace an X constraint , which matches anything , with another that has more specific requirements based on the type of the corresponding operand .


"Register operands are expected in COPY"


<s> static bool ia64_expand_vecint_compare ( enum rtx_code code , enum machine_mode mode , rtx dest , rtx op0 , rtx op1 ) { bool negate = false ; rtx x ; switch ( code ) { case EQ : case GT : case GTU : break ; case NE : case LE : case LEU : code = reverse_condition ( code ) ; negate = true ; break ; case GE : case GEU : code = reverse_condition ( code ) ; negate = true ; case LT : case LTU : code = swap_condition ( code ) ; x = op0 , op0 = op1 , op1 = x ; break ; default : gcc_unreachable ( ) ; } if ( code == GTU ) { switch ( mode ) { case V2SImode : { rtx t1 , t2 , mask ; t1 = gen_reg_rtx ( V2SImode ) ; emit_insn ( gen_subv2si3 ( t1 , op0 , op1 ) ) ; mask = GEN_INT ( - 0x80000000 ) ; mask = gen_rtx_CONST_VECTOR ( V2SImode , gen_rtvec ( 2 , mask , mask ) ) ; mask = force_reg ( V2SImode , mask ) ; t2 = gen_reg_rtx ( V2SImode ) ; emit_insn ( gen_andv2si3 ( t2 , op0 , mask ) ) ; x = gen_reg_rtx ( V2SImode ) ; emit_insn ( gen_xorv2si3 ( x , t1 , t2 ) ) ; code = GT ; op0 = x ; op1 = CONST0_RTX ( mode ) ; } break ; case V8QImode : case V4HImode : x = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x , gen_rtx_US_MINUS ( mode , op0 , op1 ) ) ) ; code = EQ ; op0 = x ; op1 = CONST0_RTX ( mode ) ; negate = ! negate ; break ; default : gcc_unreachable ( ) ; } } x = gen_rtx_fmt_ee ( code , mode , op0 , op1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , x ) ) ; return negate ; } </s>

Generate an integral vector comparison . Return true if the condition has been reversed , and so the sense of the comparison should be inverted .


<s> EVT SITargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { if ( Size >= 16 && DstAlign >= 4 ) return MVT :: v4i32 ; if ( Size >= 8 && DstAlign >= 4 ) return MVT :: v2i32 ; return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s>
SDValue
TLCS900TargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
if
(
CallConv
==
CallingConv
::
TLCS900_INTR
&&
!
Outs
.
empty
(
)
)
report_fatal_error
(
"ISRs cannot return any value"
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_TLCS900
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
if
(
RVLocs
[
i
]
.
isRegLoc
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
unsigned
Opc
=
(
CallConv
==
CallingConv
::
TLCS900_INTR
TLCS900ISD
::
RETI_FLAG
:
TLCS900ISD
::
RET_FLAG
)
;
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
Opc
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
return
DAG
.
getNode
(
Opc
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s>
unsigned
assignCustomValue
(
const
CallLowering
::
ArgInfo
&
Arg
,
ArrayRef
<
CCValAssign
>
VAs
)
override
{
CCValAssign
VA
=
VAs
[
0
]
;
assert
(
VA
.
needsCustom
(
)
&&
"Value doesn't need custom handling"
)
;
assert
(
VA
.
getValVT
(
)
==
MVT
::
f64
&&
"Unsupported type"
)
;
CCValAssign
NextVA
=
VAs
[
1
]
;
assert
(
NextVA
.
needsCustom
(
)
&&
"Value doesn't need custom handling"
)
;
assert
(
NextVA
.
getValVT
(
)
==
MVT
::
f64
&&
"Unsupported type"
)
;
assert
(
VA
.
getValNo
(
)
==
NextVA
.
getValNo
(
)
&&
"Values belong to different arguments"
)
;
assert
(
VA
.
isRegLoc
(
)
&&
"Value should be in reg"
)
;
assert
(
NextVA
.
isRegLoc
(
)
&&
"Value should be in reg"
)
;
unsigned
NewRegs
[
]
=
{
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
32
)
)
,
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
32
)
)
}
;
MIRBuilder
.
buildExtract
(
NewRegs
[
0
]
,
Arg
.
Reg
,
0
)
;
MIRBuilder
.
buildExtract
(
NewRegs
[
1
]
,
Arg
.
Reg
,
32
)
;
bool
IsLittle
=
MIRBuilder
.
getMF
(
)
.
getSubtarget
<
ARMSubtarget
>
(
)
.
isLittle
(
)
;
if
(
!
IsLittle
)
std
::
swap
(
NewRegs
[
0
]
,
NewRegs
[
1
]
)
;
assignValueToReg
(
NewRegs
[
0
]
,
VA
.
getLocReg
(
)
,
VA
)
;
assignValueToReg
(
NewRegs
[
1
]
,
NextVA
.
getLocReg
(
)
,
NextVA
)
;
return
1
;
}
</s>

Handle custom values , which may be passed into one or more of VAs .


<s>
MachineBasicBlock
*
MSP430TargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
,
DenseMap
<
MachineBasicBlock
*
,
MachineBasicBlock
*
>
*
EM
)
const
{
unsigned
Opc
=
MI
->
getOpcode
(
)
;
if
(
Opc
==
MSP430
::
Shl8
||
Opc
==
MSP430
::
Shl16
||
Opc
==
MSP430
::
Sra8
||
Opc
==
MSP430
::
Sra16
||
Opc
==
MSP430
::
Srl8
||
Opc
==
MSP430
::
Srl16
)
return
EmitShiftInstr
(
MI
,
BB
,
EM
)
;
const
TargetInstrInfo
&
TII
=
*
getTargetMachine
(
)
.
getInstrInfo
(
)
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
assert
(
(
Opc
==
MSP430
::
Select16
||
Opc
==
MSP430
::
Select8
)
&&
"Unexpected instr type to insert"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
I
=
BB
;
++
I
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
copy1MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
MSP430
::
JCC
)
)
.
addMBB
(
copy1MBB
)
.
addImm
(
MI
->
getOperand
(
3
)
.
getImm
(
)
)
;
F
->
insert
(
I
,
copy0MBB
)
;
F
->
insert
(
I
,
copy1MBB
)
;
for
(
MachineBasicBlock
::
succ_iterator
SI
=
BB
->
succ_begin
(
)
,
SE
=
BB
->
succ_end
(
)
;
SI
!=
SE
;
++
SI
)
EM
->
insert
(
std
::
make_pair
(
*
SI
,
copy1MBB
)
)
;
copy1MBB
->
transferSuccessors
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
copy1MBB
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
copy1MBB
)
;
BB
=
copy1MBB
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
MSP430
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
F
->
DeleteMachineInstr
(
MI
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


"function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n"

A C statement ( sans semicolon ) to update the summarizer variable CUM to advance past an argument in the argument list . The values MODE , TYPE and NAMED describe that argument . Once this is done , the variable CUM is suitable for analyzing the * following * argument with ` FUNCTION_ARG ' , etc . This macro need not do anything if the argument in question was passed on the stack . The compiler knows how to track the amount of stack space used for arguments without any special help .


<s> void HexagonInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ) ; if ( Hexagon :: IntRegsRegisterClass -> hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: STriw ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( Hexagon :: DoubleRegsRegisterClass -> hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: STrid ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( Hexagon :: PredRegsRegisterClass -> hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: STriw_pred ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else { assert ( 0 && "Unimplemented" ) ; } } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> SMRange getLocRange ( ) const { return SMRange ( StartLoc , EndLoc ) ; } </s>

getLocRange - Get the range between the first and last token of this operand .


Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calling convention CallConv .


Return an array that contains the bitmask target flag values and their names .

ARM ARM ARM "arm-got" "arm-sbrel" "arm-dllimport" "arm-secrel" "arm-nonlazy"


<s> virtual bool addPostRegAlloc ( ) { if ( PatmosSinglePathInfo :: isEnabled ( ) ) { addPass ( createPatmosSPMarkPass ( getPatmosTargetMachine ( ) ) ) ; addPass ( createPatmosSinglePathInfoPass ( getPatmosTargetMachine ( ) ) ) ; addPass ( createPatmosSPPreparePass ( getPatmosTargetMachine ( ) ) ) ; } return false ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .

Patmos Patmos Patmos Patmos Patmos Patmos Patmos Patmos


<s> void WasmPEI :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < StackProtector > ( ) ; AU . addRequired < TargetPassConfig > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool MipsHazardSchedule :: runOnMachineFunction ( MachineFunction & MF ) { const MipsSubtarget * STI = & static_cast < const MipsSubtarget & > ( MF . getSubtarget ( ) ) ; if ( ! STI -> hasMips32r6 ( ) || STI -> inMicroMipsMode ( ) ) return false ; bool Changed = false ; const MipsInstrInfo * TII = STI -> getInstrInfo ( ) ; for ( MachineFunction :: iterator FI = MF . begin ( ) ; FI != MF . end ( ) ; ++ FI ) { for ( Iter I = FI -> begin ( ) ; I != FI -> end ( ) ; ++ I ) { if ( ! TII -> HasForbiddenSlot ( * I ) ) continue ; Iter Inst ; bool LastInstInFunction = std :: next ( I ) == FI -> end ( ) && std :: next ( FI ) == MF . end ( ) ; if ( ! LastInstInFunction ) { std :: pair < Iter , bool > Res = getNextMachineInstr ( std :: next ( I ) , & * FI ) ; LastInstInFunction |= Res . second ; Inst = Res . first ; } if ( LastInstInFunction || ! TII -> SafeInForbiddenSlot ( * Inst ) ) { Changed = true ; MIBundleBuilder ( & * I ) . append ( BuildMI ( MF , I -> getDebugLoc ( ) , TII -> get ( Mips :: NOP ) ) ) ; NumInsertedNops ++ ; } } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .

Mips Mips Mips Mips Mips Mips Mips Mips::NOP


<s> static bool arm_cxx_key_method_may_be_inline ( void ) { return ! TARGET_AAPCS_BASED ; } </s>

The EABI says that an inline function may never be the key method .


"Pseudo flag setting opcodes only exist in Selection DAG"

Perform target-specific instruction verification .


<s> void TOYInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( TOY :: STR ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ; } </s>


<s> bool AArch64LoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { TII = static_cast < const AArch64InstrInfo * > ( Fn . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; bool Modified = false ; for ( auto & MBB : Fn ) Modified |= optimizeBlock ( MBB ) ; return Modified ; } </s>


<s> static void expand_csky_stack_adjust ( int offset ) { rtx set ; rtx_insn * insn ; int size = ( offset > 0 ? offset : - offset ) ; if ( offset == 0 ) return ; if ( size > CSKY_MAX_SP_ADJUST * 2 ) { rtx tmp , dwarf ; gcc_assert ( cfun -> machine -> reg_size != 0 && ( cfun -> machine -> reg_mask & ( 1 << CSKY_STACKADJUST_REGNUM ) ) ) ; if ( ! flag_sched_prolog ) emit_insn ( gen_blockage ( ) ) ; tmp = gen_rtx_REG ( SImode , CSKY_STACKADJUST_REGNUM ) ; emit_move_insn ( tmp , GEN_INT ( size ) ) ; if ( offset > 0 ) set = gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , tmp ) ; else set = gen_subsi3 ( stack_pointer_rtx , stack_pointer_rtx , tmp ) ; insn = emit_insn ( set ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; dwarf = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , dwarf ) ; if ( ! flag_sched_prolog ) emit_insn ( gen_blockage ( ) ) ; } else while ( size ) { int delta = ( size > CSKY_MAX_SP_ADJUST ? CSKY_MAX_SP_ADJUST : size ) ; if ( offset > 0 ) set = gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( delta ) ) ; else set = gen_subsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( delta ) ) ; insn = emit_insn ( set ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; size -= delta ; } } </s>

Adjust the stack pointer by OFFSET bytes . OFFSET is negative if this is in the prologue , positive if in the epilogue . This may require multiple instructions and/or use of CSKY_STACKADJUST_REGNUM as a scratch register . Emit CFA notes as appropriate .


<s> unsigned AArch64TTIImpl :: getIntImmCost ( Intrinsic :: ID IID , unsigned Idx , const APInt & Imm , Type * Ty ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; switch ( IID ) { default : return TTI :: TCC_Free ; case Intrinsic :: sadd_with_overflow : case Intrinsic :: uadd_with_overflow : case Intrinsic :: ssub_with_overflow : case Intrinsic :: usub_with_overflow : case Intrinsic :: smul_with_overflow : case Intrinsic :: umul_with_overflow : if ( Idx == 1 ) { unsigned NumConstants = ( BitSize + 63 ) / 64 ; unsigned Cost = AArch64TTIImpl :: getIntImmCost ( Imm , Ty ) ; return ( Cost <= NumConstants * TTI :: TCC_Basic ) ? static_cast < unsigned > ( TTI :: TCC_Free ) : Cost ; } break ; case Intrinsic :: experimental_stackmap : if ( ( Idx < 2 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; case Intrinsic :: experimental_patchpoint_void : case Intrinsic :: experimental_patchpoint_i64 : if ( ( Idx < 4 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; } return AArch64TTIImpl :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> BitVector SIRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; reserveRegisterTuples ( Reserved , AMDGPU :: EXEC ) ; reserveRegisterTuples ( Reserved , AMDGPU :: FLAT_SCR ) ; reserveRegisterTuples ( Reserved , AMDGPU :: M0 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_SHARED_BASE ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_SHARED_LIMIT ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_PRIVATE_BASE ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_PRIVATE_LIMIT ) ; reserveRegisterTuples ( Reserved , AMDGPU :: XNACK_MASK ) ; reserveRegisterTuples ( Reserved , AMDGPU :: LDS_DIRECT ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TBA ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TMA ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP0_TTMP1 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP2_TTMP3 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP4_TTMP5 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP6_TTMP7 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP8_TTMP9 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP10_TTMP11 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP12_TTMP13 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP14_TTMP15 ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; unsigned MaxNumSGPRs = ST . getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = AMDGPU :: SGPR_32RegClass . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = AMDGPU :: SGPR_32RegClass . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } unsigned MaxNumVGPRs = ST . getMaxNumVGPRs ( MF ) ; unsigned TotalNumVGPRs = AMDGPU :: VGPR_32RegClass . getNumRegs ( ) ; for ( unsigned i = MaxNumVGPRs ; i < TotalNumVGPRs ; ++ i ) { unsigned Reg = AMDGPU :: VGPR_32RegClass . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } const SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , ScratchWaveOffsetReg ) ; } unsigned ScratchRSrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRSrcReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , ScratchRSrcReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , ScratchWaveOffsetReg ) ) ; } unsigned StackPtrReg = MFI -> getStackPtrOffsetReg ( ) ; if ( StackPtrReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , StackPtrReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , StackPtrReg ) ) ; } unsigned FrameReg = MFI -> getFrameOffsetReg ( ) ; if ( FrameReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , FrameReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , FrameReg ) ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
Value
*
PPCTargetLowering
::
emitMaskedAtomicCmpXchgIntrinsic
(
IRBuilderBase
&
Builder
,
AtomicCmpXchgInst
*
CI
,
Value
*
AlignedAddr
,
Value
*
CmpVal
,
Value
*
NewVal
,
Value
*
Mask
,
AtomicOrdering
Ord
)
const
{
assert
(
EnableQuadwordAtomics
&&
Subtarget
.
hasQuadwordAtomics
(
)
&&
"Only support quadword now"
)
;
Module
*
M
=
Builder
.
GetInsertBlock
(
)
->
getParent
(
)
->
getParent
(
)
;
Type
*
ValTy
=
CmpVal
->
getType
(
)
;
assert
(
ValTy
->
getPrimitiveSizeInBits
(
)
==
128
)
;
Function
*
IntCmpXchg
=
Intrinsic
::
getDeclaration
(
M
,
Intrinsic
::
ppc_cmpxchg_i128
)
;
Type
*
Int64Ty
=
Type
::
getInt64Ty
(
M
->
getContext
(
)
)
;
Value
*
CmpLo
=
Builder
.
CreateTrunc
(
CmpVal
,
Int64Ty
,
"cmp_lo"
)
;
Value
*
CmpHi
=
Builder
.
CreateTrunc
(
Builder
.
CreateLShr
(
CmpVal
,
64
)
,
Int64Ty
,
"cmp_hi"
)
;
Value
*
NewLo
=
Builder
.
CreateTrunc
(
NewVal
,
Int64Ty
,
"new_lo"
)
;
Value
*
NewHi
=
Builder
.
CreateTrunc
(
Builder
.
CreateLShr
(
NewVal
,
64
)
,
Int64Ty
,
"new_hi"
)
;
Value
*
Addr
=
Builder
.
CreateBitCast
(
AlignedAddr
,
Type
::
getInt8PtrTy
(
M
->
getContext
(
)
)
)
;
emitLeadingFence
(
Builder
,
CI
,
Ord
)
;
Value
*
LoHi
=
Builder
.
CreateCall
(
IntCmpXchg
,
{
Addr
,
CmpLo
,
CmpHi
,
NewLo
,
NewHi
}
)
;
emitTrailingFence
(
Builder
,
CI
,
Ord
)
;
Value
*
Lo
=
Builder
.
CreateExtractValue
(
LoHi
,
0
,
"lo"
)
;
Value
*
Hi
=
Builder
.
CreateExtractValue
(
LoHi
,
1
,
"hi"
)
;
Lo
=
Builder
.
CreateZExt
(
Lo
,
ValTy
,
"lo64"
)
;
Hi
=
Builder
.
CreateZExt
(
Hi
,
ValTy
,
"hi64"
)
;
return
Builder
.
CreateOr
(
Lo
,
Builder
.
CreateShl
(
Hi
,
ConstantInt
::
get
(
ValTy
,
64
)
)
,
"val64"
)
;
}
</s>

Perform a masked cmpxchg using a target-specific intrinsic .


<s>
bool
ARMPassConfig
::
addPreSched2
(
)
{
if
(
getOptLevel
(
)
!=
CodeGenOpt
::
)
{
if
(
!
getARMSubtarget
(
)
.
isThumb1Only
(
)
)
{
addPass
(
createARMLoadStoreOptimizationPass
(
)
)
;
printAndVerify
(
"After ARM load / store optimizer"
)
;
}
if
(
(
DisableA15SDOptimization
||
!
getARMSubtarget
(
)
.
isCortexA15
(
)
)
&&
getARMSubtarget
(
)
.
hasNEON
(
)
)
addPass
(
createExecutionDependencyFixPass
(
&
ARM
::
DPRRegClass
)
)
;
}
addPass
(
createARMExpandPseudoPass
(
)
)
;
if
(
getOptLevel
(
)
!=
CodeGenOpt
::
)
{
if
(
!
getARMSubtarget
(
)
.
isThumb1Only
(
)
)
addPass
(
&
IfConverterID
)
;
}
if
(
getARMSubtarget
(
)
.
isThumb2
(
)
)
addPass
(
createThumb2ITBlockPass
(
)
)
;
return
true
;
}
</s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .

ARM
ARM
ARM
ARM
"After ARM load / store optimizer"
ARM
ARM
ARM::DPRRegClass
ARM
ARM
ARM


<s> bool ARMPassConfig :: addInstSelector ( ) { PM -> add ( createARMISelDag ( getARMTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void MSP430FrameInfo :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MSP430MachineFunctionInfo * MSP430FI = MF . getInfo < MSP430MachineFunctionInfo > ( ) ; const MSP430InstrInfo & TII = * static_cast < const MSP430InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; uint64_t NumBytes = 0 ; if ( hasFP ( MF ) ) { uint64_t FrameSize = StackSize - 2 ; NumBytes = FrameSize - MSP430FI -> getCalleeSavedFrameSize ( ) ; MFI -> setOffsetAdjustment ( - NumBytes ) ; BuildMI ( MBB , MBBI , DL , TII . get ( MSP430 :: PUSH16r ) ) . addReg ( MSP430 :: FPW , RegState :: Kill ) ; BuildMI ( MBB , MBBI , DL , TII . get ( MSP430 :: MOV16rr ) , MSP430 :: FPW ) . addReg ( MSP430 :: SPW ) ; for ( MachineFunction :: iterator I = llvm :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( MSP430 :: FPW ) ; } else NumBytes = StackSize - MSP430FI -> getCalleeSavedFrameSize ( ) ; while ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == MSP430 :: PUSH16r ) ) ++ MBBI ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes ) { if ( NumBytes ) { MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( MSP430 :: SUB16ri ) , MSP430 :: SPW ) . addReg ( MSP430 :: SPW ) . addImm ( NumBytes ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; } } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static rtx arm_gen_store_multiple_1 ( int count , int * regs , rtx * mems , rtx basereg , HOST_WIDE_INT wback_offset ) { int i = 0 , j ; rtx result ; if ( GET_CODE ( basereg ) == PLUS ) basereg = XEXP ( basereg , 0 ) ; if ( ! multiple_operation_profitable_p ( false , count , 0 ) ) { rtx seq ; start_sequence ( ) ; for ( i = 0 ; i < count ; i ++ ) emit_move_insn ( mems [ i ] , gen_rtx_REG ( SImode , regs [ i ] ) ) ; if ( wback_offset != 0 ) emit_move_insn ( basereg , plus_constant ( Pmode , basereg , wback_offset ) ) ; seq = get_insns ( ) ; end_sequence ( ) ; return seq ; } result = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count + ( wback_offset != 0 ? 1 : 0 ) ) ) ; if ( wback_offset != 0 ) { XVECEXP ( result , 0 , 0 ) = gen_rtx_SET ( VOIDmode , basereg , plus_constant ( Pmode , basereg , wback_offset ) ) ; i = 1 ; count ++ ; } for ( j = 0 ; i < count ; i ++ , j ++ ) XVECEXP ( result , 0 , i ) = gen_rtx_SET ( VOIDmode , mems [ j ] , gen_rtx_REG ( SImode , regs [ j ] ) ) ; return result ; } </s>

Generate a store-multiple instruction . COUNT is the number of stores in the instruction ; REGS and MEMS are arrays containing the operands . BASEREG is the base register to be used in addressing the memory operands . WBACK_OFFSET is nonzero if the instruction should update the base register .


<s> unsigned PPCTTIImpl :: getCacheLineSize ( ) { if ( CacheLineSize . getNumOccurrences ( ) > 0 ) return CacheLineSize ; unsigned Mcpu = ST -> getMcpu ( ) ; if ( Mcpu == PPC :: MCPU_PWR7 || Mcpu == PPC :: MCPU_PWR8 || Mcpu == PPC :: MCPU_PWR9 ) return 128 ; return 64 ; } </s>

Return the target cache line size in bytes .


<s>
void
RISCVAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
MCFixupKind
Kind
=
Fixup
.
getKind
(
)
;
if
(
Kind
>=
FirstLiteralRelocationKind
)
return
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Kind
)
;
if
(
!
Value
)
return
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
Ctx
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
unsigned
NumBytes
=
alignTo
(
Info
.
TargetSize
+
Info
.
TargetOffset
,
8
)
/
8
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> unsigned SIRegisterInfo :: reservedPrivateSegmentBufferReg ( const MachineFunction & MF ) const { const AMDGPUSubtarget & ST = MF . getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . hasSGPRInitBug ( ) ) { unsigned BaseIdx = AMDGPUSubtarget :: FIXED_SGPR_COUNT_FOR_INIT_BUG - 4 - 4 ; unsigned BaseReg ( AMDGPU :: SGPR_32RegClass . getRegister ( BaseIdx ) ) ; return getMatchingSuperReg ( BaseReg , AMDGPU :: sub0 , & AMDGPU :: SReg_128RegClass ) ; } if ( ST . getGeneration ( ) >= AMDGPUSubtarget :: VOLCANIC_ISLANDS ) { return AMDGPU :: SGPR92_SGPR93_SGPR94_SGPR95 ; } return AMDGPU :: SGPR96_SGPR97_SGPR98_SGPR99 ; } </s>

Return the end register initially reserved for the scratch buffer in case spilling is needed .


<s> void rs6000_expand_atomic_exchange ( rtx operands [ ] ) { rtx retval , mem , val , cond ; machine_mode mode ; enum memmodel model ; rtx label , x , mask , shift ; retval = operands [ 0 ] ; mem = operands [ 1 ] ; val = operands [ 2 ] ; model = memmodel_base ( INTVAL ( operands [ 3 ] ) ) ; mode = GET_MODE ( mem ) ; mask = shift = NULL_RTX ; if ( ! TARGET_SYNC_HI_QI && ( mode == QImode || mode == HImode ) ) { mem = rs6000_adjust_atomic_subword ( mem , & shift , & mask ) ; val = convert_modes ( SImode , mode , val , 1 ) ; val = expand_simple_binop ( SImode , ASHIFT , val , shift , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; retval = gen_reg_rtx ( SImode ) ; mode = SImode ; } mem = rs6000_pre_atomic_barrier ( mem , model ) ; label = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label , 0 ) ) ; emit_load_locked ( mode , retval , mem ) ; x = val ; if ( mask ) x = rs6000_mask_atomic_subword ( retval , val , mask ) ; cond = gen_reg_rtx ( CCmode ) ; emit_store_conditional ( mode , cond , mem , x ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label ) ; rs6000_post_atomic_barrier ( model ) ; if ( shift ) rs6000_finish_atomic_subword ( operands [ 0 ] , retval , shift ) ; } </s>


<s> void BTFDebug :: endModule ( ) { const Module * M = MMI -> getModule ( ) ; for ( const DICompileUnit * CUNode : M -> debug_compile_units ( ) ) { for ( const auto * GVE : CUNode -> getGlobalVariables ( ) ) { DIGlobalVariable * GV = GVE -> getVariable ( ) ; visitTypeEntry ( GV -> getType ( ) . resolve ( ) ) ; } } for ( const auto & TypeEntry : TypeEntries ) TypeEntry -> completeType ( * this ) ; emitBTFSection ( ) ; emitBTFExtSection ( ) ; } </s>

Emit all exception information that should come after the content .


<s>
void
AMDGPUInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
!
"Not Implemented"
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s>
static
void
rs6000_debug_target_options
(
tree
args
,
const
char
*
prefix
)
{
if
(
args
==
NULL_TREE
)
fprintf
(
stderr
,
"%s<NULL>"
,
prefix
)
;
else
if
(
TREE_CODE
(
args
)
==
STRING_CST
)
{
char
*
p
=
ASTRDUP
(
TREE_STRING_POINTER
(
args
)
)
;
char
*
q
;
while
(
(
q
=
strtok
(
p
,
","
)
)
!=
)
{
p
=
;
fprintf
(
stderr
,
"%s\"%s\""
,
prefix
,
q
)
;
prefix
=
", "
;
}
}
else
if
(
TREE_CODE
(
args
)
==
TREE_LIST
)
{
do
{
tree
value
=
TREE_VALUE
(
args
)
;
if
(
value
)
{
rs6000_debug_target_options
(
value
,
prefix
)
;
prefix
=
", "
;
}
args
=
TREE_CHAIN
(
args
)
;
}
while
(
args
!=
NULL_TREE
)
;
}
else
gcc_unreachable
(
)
;
return
;
}
</s>

Print out the target options as a list for -mdebug=target .


<s> static void insert_wic_for_ilb_runout ( rtx_insn * first ) { rtx_insn * insn ; rtx_insn * before_4 = 0 ; rtx_insn * before_16 = 0 ; int addr_offset = 0 ; int length ; int wic_addr0 = 128 * 4 ; int wic_addr1 = 128 * 4 ; int first_addr = INSN_ADDRESSES ( INSN_UID ( first ) ) ; for ( insn = first ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) ) { addr_offset = INSN_ADDRESSES ( INSN_UID ( insn ) ) - first_addr ; length = get_attr_length ( insn ) ; if ( before_4 == 0 && addr_offset + length >= 4 * 4 ) before_4 = insn ; if ( JUMP_P ( insn ) ) return ; if ( before_16 == 0 && addr_offset + length >= 14 * 4 ) before_16 = insn ; if ( CALL_P ( insn ) || tablejump_p ( insn , 0 , 0 ) ) return ; if ( addr_offset + length >= 32 * 4 ) { gcc_assert ( before_4 && before_16 ) ; if ( wic_addr0 > 4 * 4 ) { insn = emit_insn_before ( gen_iprefetch ( gen_int_mode ( addr_offset , SImode ) ) , before_4 ) ; recog_memoized ( insn ) ; INSN_LOCATION ( insn ) = INSN_LOCATION ( before_4 ) ; INSN_ADDRESSES_NEW ( insn , INSN_ADDRESSES ( INSN_UID ( before_4 ) ) ) ; return ; } } } } </s>

Heuristics to identify where to insert at the fall through path of the caller function . If there is a call after the caller branch delay slot then we dont generate the instruction prefetch instruction . Scan up to 32 instructions after the call and checks for the JUMP and call instruction . If there is a call or JUMP instruction in the range of 32 instruction `` wic '' instruction wont be generated . Otherwise insert the `` wic '' instruction in the fall through of the call instruction four instruction after the call . before_4 is used for the position to insert `` wic '' instructions . before_16 is used to check for call and JUMP instruction for first 15 insns .


<s> StringRef MipsInstPrinter :: getOpcodeName ( unsigned Opcode ) const { return getInstructionName ( Opcode ) ; } </s>

Return a string representation for an opcode .


<s>
StringRef
getPassName
(
)
const
override
{
return
"TVM Argument Move"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static rtx mips_expand_builtin_movtf ( enum mips_builtin_type type , enum insn_code icode , enum mips_fp_condition cond , rtx target , tree arglist ) { rtx cmp_result , op0 , op1 ; cmp_result = mips_prepare_builtin_target ( icode , 0 , 0 ) ; op0 = mips_prepare_builtin_arg ( icode , 1 , & arglist ) ; op1 = mips_prepare_builtin_arg ( icode , 2 , & arglist ) ; emit_insn ( GEN_FCN ( icode ) ( cmp_result , op0 , op1 , GEN_INT ( cond ) ) ) ; icode = CODE_FOR_mips_cond_move_tf_ps ; target = mips_prepare_builtin_target ( icode , 0 , target ) ; if ( type == MIPS_BUILTIN_MOVT ) { op1 = mips_prepare_builtin_arg ( icode , 2 , & arglist ) ; op0 = mips_prepare_builtin_arg ( icode , 1 , & arglist ) ; } else { op0 = mips_prepare_builtin_arg ( icode , 1 , & arglist ) ; op1 = mips_prepare_builtin_arg ( icode , 2 , & arglist ) ; } emit_insn ( gen_mips_cond_move_tf_ps ( target , op0 , op1 , cmp_result ) ) ; return target ; } </s>

Expand a __builtin_mips_movt_ * _ps ( ) or __builtin_mips_movf_ * _ps ( ) function ( TYPE says which ) . ARGLIST is the list of arguments to the function , ICODE is the instruction that should be used to compare the first two arguments , and COND is the condition it should test . TARGET , if nonnull , suggests a good place to put the result .


<s> bool X86FastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Load : return X86SelectLoad ( I ) ; case Instruction :: Store : return X86SelectStore ( I ) ; case Instruction :: Ret : return X86SelectRet ( I ) ; case Instruction :: ICmp : case Instruction :: FCmp : return X86SelectCmp ( I ) ; case Instruction :: ZExt : return X86SelectZExt ( I ) ; case Instruction :: SExt : return X86SelectSExt ( I ) ; case Instruction :: Br : return X86SelectBranch ( I ) ; case Instruction :: LShr : case Instruction :: AShr : case Instruction :: Shl : return X86SelectShift ( I ) ; case Instruction :: SDiv : case Instruction :: UDiv : case Instruction :: SRem : case Instruction :: URem : return X86SelectDivRem ( I ) ; case Instruction :: Select : return X86SelectSelect ( I ) ; case Instruction :: Trunc : return X86SelectTrunc ( I ) ; case Instruction :: FPExt : return X86SelectFPExt ( I ) ; case Instruction :: FPTrunc : return X86SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return X86SelectSIToFP ( I ) ; case Instruction :: UIToFP : return X86SelectUIToFP ( I ) ; case Instruction :: IntToPtr : case Instruction :: PtrToInt : { EVT SrcVT = TLI . getValueType ( DL , I -> getOperand ( 0 ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) ; if ( DstVT . bitsGT ( SrcVT ) ) return X86SelectZExt ( I ) ; if ( DstVT . bitsLT ( SrcVT ) ) return X86SelectTrunc ( I ) ; Register Reg = getRegForValue ( I -> getOperand ( 0 ) ) ; if ( Reg == 0 ) return false ; updateValueMap ( I , Reg ) ; return true ; } case Instruction :: BitCast : { if ( ! Subtarget -> hasSSE2 ( ) ) return false ; MVT SrcVT , DstVT ; if ( ! isTypeLegal ( I -> getOperand ( 0 ) -> getType ( ) , SrcVT ) || ! isTypeLegal ( I -> getType ( ) , DstVT ) ) return false ; if ( ! SrcVT . isVector ( ) || ! DstVT . isVector ( ) || SrcVT . getVectorElementType ( ) == MVT :: i1 || DstVT . getVectorElementType ( ) == MVT :: i1 ) return false ; Register Reg = getRegForValue ( I -> getOperand ( 0 ) ) ; if ( Reg == 0 ) return false ; updateValueMap ( I , Reg ) ; return true ; } } return false ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> const char * i386_pe_strip_name_encoding ( const char * str ) { if ( strncmp ( str , DLL_IMPORT_PREFIX , strlen ( DLL_IMPORT_PREFIX ) ) == 0 ) str += strlen ( DLL_IMPORT_PREFIX ) ; else if ( strncmp ( str , DLL_EXPORT_PREFIX , strlen ( DLL_EXPORT_PREFIX ) ) == 0 ) str += strlen ( DLL_EXPORT_PREFIX ) ; if ( * str == '*' ) str += 1 ; return str ; } </s>

Strip only the leading encoding , leaving the stdcall suffix and fastcall prefix if it exists .


<s> static bool aarch64_pac_insn_p ( rtx x ) { if ( ! INSN_P ( x ) ) return x ; subrtx_var_iterator :: array_type array ; FOR_EACH_SUBRTX_VAR ( iter , array , PATTERN ( x ) , ALL ) { rtx sub = * iter ; if ( sub && GET_CODE ( sub ) == UNSPEC ) { int unspec_val = XINT ( sub , 1 ) ; switch ( unspec_val ) { case UNSPEC_PACISP : return true ; default : return false ; } iter . skip_subrtxes ( ) ; } } return false ; } </s>

Check if X ( or any sub-rtx of X ) is a PACIASP/PACIBSP instruction .


<s>
int
scalar_chain
::
convert
(
)
{
bitmap_iterator
bi
;
unsigned
id
;
int
converted_insns
=
0
;
if
(
!
dbg_cnt
(
stv_conversion
)
)
return
0
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Converting chain #%d...\n"
,
chain_id
)
;
convert_registers
(
)
;
EXECUTE_IF_SET_IN_BITMAP
(
insns
,
0
,
id
,
bi
)
{
convert_insn
(
DF_INSN_UID_GET
(
id
)
->
insn
)
;
converted_insns
++
;
}
return
converted_insns
;
}
</s>

Convert whole chain creating required register conversions and copies .


<s> static bool msp430_no_hwmult ( void ) { static const char * cached_match = NULL ; static bool cached_result ; int i ; if ( msp430_hwmult_type == MSP430_HWMULT_NONE ) return true ; if ( msp430_hwmult_type != MSP430_HWMULT_AUTO ) return false ; if ( target_mcu == NULL ) return true ; if ( target_mcu == cached_match ) return cached_result ; cached_match = target_mcu ; for ( i = ARRAY_SIZE ( msp430_mcu_data ) ; i -- ; ) if ( strcasecmp ( target_mcu , msp430_mcu_data [ i ] . name ) == 0 ) return cached_result = msp430_mcu_data [ i ] . hwmpy == 0 ; return cached_result = true ; } </s>

Returns true if the current MCU does not have a hardware multiplier of any kind .


<s> static bool isImm ( const MachineOperand & MO , MachineRegisterInfo * MRI ) { assert ( MO . isReg ( ) ) ; const SPIRVType * TypeInst = MRI -> getVRegDef ( MO . getReg ( ) ) ; if ( TypeInst -> getOpcode ( ) != SPIRV :: ASSIGN_TYPE ) return false ; assert ( TypeInst -> getOperand ( 1 ) . isReg ( ) ) ; MachineInstr * ImmInst = MRI -> getVRegDef ( TypeInst -> getOperand ( 1 ) . getReg ( ) ) ; return ImmInst -> getOpcode ( ) == TargetOpcode :: G_CONSTANT ; } </s>


<s> void visium_expand_int_cstore ( rtx * operands , machine_mode mode ) { enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; rtx op0 = operands [ 0 ] , op1 = operands [ 2 ] , op2 = operands [ 3 ] , sltu ; bool reverse = false ; switch ( code ) { case EQ : case NE : if ( op2 != const0_rtx ) op1 = force_reg ( mode , gen_rtx_XOR ( mode , op1 , op2 ) ) ; op1 = gen_rtx_NOT ( mode , op1 ) ; op2 = constm1_rtx ; if ( code == EQ ) reverse = true ; break ; case LEU : case GEU : code = reverse_condition ( code ) ; reverse = true ; case LTU : case GTU : if ( code == GTU ) { rtx tmp = op1 ; op1 = op2 ; op2 = tmp ; } break ; default : gcc_unreachable ( ) ; } sltu = gen_rtx_LTU ( SImode , op1 , op2 ) ; if ( reverse ) { rtx tmp = copy_to_mode_reg ( SImode , gen_rtx_NEG ( SImode , sltu ) ) ; emit_insn ( gen_add3_insn ( op0 , tmp , const1_rtx ) ) ; } else emit_insn ( gen_rtx_SET ( op0 , sltu ) ) ; } </s>

Expand a cstore of OPERANDS in MODE for EQ/NE/LTU/GTU/GEU/LEU . We generate the result in the C flag and use the ADC/SUBC instructions to write it into the destination register . It would also be possible to implement support for LT/GT/LE/GE by means of the RFLAG instruction followed by some shifts , but this can pessimize the generated code .