<s> static void do_isel ( rtx dest , rtx cmp , rtx src_t , rtx src_f , rtx cr ) { if ( GET_MODE ( dest ) == DImode ) emit_insn ( gen_isel_signed_di ( dest , cmp , src_t , src_f , cr ) ) ; else emit_insn ( gen_isel_signed_si ( dest , cmp , src_t , src_f , cr ) ) ; } </s>

Emit an isel of the proper mode for DEST . DEST is the isel destination register . SRC1 is the isel source if CR is true . SRC2 is the isel source if CR is false . CR is the condition for the isel .


<s> bool X86CallFrameOptimization :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; MRI = & MF . getRegInfo ( ) ; if ( ! isLegal ( MF ) ) return false ; unsigned FrameSetupOpcode = TII -> getCallFrameSetupOpcode ( ) ; bool Changed = false ; ContextVector CallSeqVector ; for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ++ I ) if ( I -> getOpcode ( ) == FrameSetupOpcode ) { CallContext Context ; collectCallInfo ( MF , * BB , I , Context ) ; CallSeqVector . push_back ( Context ) ; } if ( ! isProfitable ( MF , CallSeqVector ) ) return false ; for ( auto CC : CallSeqVector ) if ( CC . UsePush ) Changed |= adjustCallSequence ( MF , CC ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> std :: unique_ptr < PBQPRAConstraint > AArch64Subtarget :: getCustomPBQPConstraints ( ) const { return llvm :: make_unique < A57PBQPConstraints > ( ) ; } </s>

Return PBQPConstraint ( s ) for the target .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < LiveIntervals > ( ) ; AU . addPreserved < LiveIntervals > ( ) ; AU . addRequired < SlotIndexes > ( ) ; AU . addPreserved < SlotIndexes > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static unsigned int insn_is_swap_p ( rtx insn ) { rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) != SET ) return 0 ; rtx rhs = SET_SRC ( body ) ; if ( GET_CODE ( rhs ) != VEC_SELECT ) return 0 ; rtx parallel = XEXP ( rhs , 1 ) ; if ( GET_CODE ( parallel ) != PARALLEL ) return 0 ; unsigned int len = XVECLEN ( parallel , 0 ) ; if ( len != 2 && len != 4 && len != 8 && len != 16 ) return 0 ; for ( unsigned int i = 0 ; i < len / 2 ; ++ i ) { rtx op = XVECEXP ( parallel , 0 , i ) ; if ( GET_CODE ( op ) != CONST_INT || INTVAL ( op ) != len / 2 + i ) return 0 ; } for ( unsigned int i = len / 2 ; i < len ; ++ i ) { rtx op = XVECEXP ( parallel , 0 , i ) ; if ( GET_CODE ( op ) != CONST_INT || INTVAL ( op ) != i - len / 2 ) return 0 ; } return 1 ; } </s>

Return 1 iff INSN swaps doublewords . This may be a reg-reg swap , a permuting load , or a permuting store .


<s> bool isIncomingArgumentHandler ( ) const override { return true ; } </s>

Returns true if the handler is dealing with incoming arguments , i.e .


<s> void aarch64_expand_compare_and_swap ( rtx operands [ ] ) { rtx bval , rval , mem , oldval , newval , is_weak , mod_s , mod_f , x , cc_reg ; machine_mode mode , r_mode ; bval = operands [ 0 ] ; rval = operands [ 1 ] ; mem = operands [ 2 ] ; oldval = operands [ 3 ] ; newval = operands [ 4 ] ; is_weak = operands [ 5 ] ; mod_s = operands [ 6 ] ; mod_f = operands [ 7 ] ; mode = GET_MODE ( mem ) ; if ( is_mm_acquire ( memmodel_from_int ( INTVAL ( mod_f ) ) ) && is_mm_release ( memmodel_from_int ( INTVAL ( mod_s ) ) ) ) mod_s = GEN_INT ( MEMMODEL_ACQ_REL ) ; r_mode = mode ; if ( mode == QImode || mode == HImode ) { r_mode = SImode ; rval = gen_reg_rtx ( r_mode ) ; } if ( TARGET_LSE ) { if ( reg_overlap_mentioned_p ( rval , oldval ) ) rval = copy_to_mode_reg ( r_mode , oldval ) ; else emit_move_insn ( rval , gen_lowpart ( r_mode , oldval ) ) ; emit_insn ( gen_aarch64_compare_and_swap_lse ( mode , rval , mem , newval , mod_s ) ) ; cc_reg = aarch64_gen_compare_reg_maybe_ze ( NE , rval , oldval , mode ) ; } else { insn_code code = code_for_aarch64_compare_and_swap ( mode ) ; if ( ! insn_data [ code ] . operand [ 2 ] . predicate ( oldval , mode ) ) oldval = force_reg ( mode , oldval ) ; emit_insn ( GEN_FCN ( code ) ( rval , mem , oldval , newval , is_weak , mod_s , mod_f ) ) ; cc_reg = gen_rtx_REG ( CCmode , CC_REGNUM ) ; } if ( r_mode != mode ) rval = gen_lowpart ( mode , rval ) ; emit_move_insn ( operands [ 1 ] , rval ) ; x = gen_rtx_EQ ( SImode , cc_reg , const0_rtx ) ; emit_insn ( gen_rtx_SET ( bval , x ) ) ; } </s>


<s> static void aarch64_expand_builtin_va_start ( tree valist , rtx nextarg ATTRIBUTE_UNUSED ) { const CUMULATIVE_ARGS * cum ; tree f_stack , f_grtop , f_vrtop , f_groff , f_vroff ; tree stack , grtop , vrtop , groff , vroff ; tree t ; int gr_save_area_size = cfun -> va_list_gpr_size ; int vr_save_area_size = cfun -> va_list_fpr_size ; int vr_offset ; cum = & crtl -> args . info ; if ( cfun -> va_list_gpr_size ) gr_save_area_size = MIN ( ( NUM_ARG_REGS - cum -> aapcs_ncrn ) * UNITS_PER_WORD , cfun -> va_list_gpr_size ) ; if ( cfun -> va_list_fpr_size ) vr_save_area_size = MIN ( ( NUM_FP_ARG_REGS - cum -> aapcs_nvrn ) * UNITS_PER_VREG , cfun -> va_list_fpr_size ) ; if ( ! TARGET_FLOAT ) { gcc_assert ( cum -> aapcs_nvrn == 0 ) ; vr_save_area_size = 0 ; } f_stack = TYPE_FIELDS ( va_list_type_node ) ; f_grtop = DECL_CHAIN ( f_stack ) ; f_vrtop = DECL_CHAIN ( f_grtop ) ; f_groff = DECL_CHAIN ( f_vrtop ) ; f_vroff = DECL_CHAIN ( f_groff ) ; stack = build3 ( COMPONENT_REF , TREE_TYPE ( f_stack ) , valist , f_stack , NULL_TREE ) ; grtop = build3 ( COMPONENT_REF , TREE_TYPE ( f_grtop ) , valist , f_grtop , NULL_TREE ) ; vrtop = build3 ( COMPONENT_REF , TREE_TYPE ( f_vrtop ) , valist , f_vrtop , NULL_TREE ) ; groff = build3 ( COMPONENT_REF , TREE_TYPE ( f_groff ) , valist , f_groff , NULL_TREE ) ; vroff = build3 ( COMPONENT_REF , TREE_TYPE ( f_vroff ) , valist , f_vroff , NULL_TREE ) ; t = make_tree ( TREE_TYPE ( stack ) , virtual_incoming_args_rtx ) ; if ( cum -> aapcs_stack_size > 0 ) t = fold_build_pointer_plus_hwi ( t , cum -> aapcs_stack_size * UNITS_PER_WORD ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( stack ) , stack , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( grtop ) , virtual_incoming_args_rtx ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( grtop ) , grtop , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( vrtop ) , virtual_incoming_args_rtx ) ; vr_offset = ROUND_UP ( gr_save_area_size , STACK_BOUNDARY / BITS_PER_UNIT ) ; if ( vr_offset ) t = fold_build_pointer_plus_hwi ( t , - vr_offset ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( vrtop ) , vrtop , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( groff ) , groff , build_int_cst ( TREE_TYPE ( groff ) , - gr_save_area_size ) ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( vroff ) , vroff , build_int_cst ( TREE_TYPE ( vroff ) , - vr_save_area_size ) ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; } </s>


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
SHUXI
::
NumTargetFixupKinds
]
=
{
{
"fixup_SHUXI_NONE"
,
0
,
32
,
0
}
,
{
"fixup_SHUXI_32"
,
0
,
32
,
0
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
{
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
}
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> int mcore_expand_insv ( rtx operands [ ] ) { int width = INTVAL ( operands [ 1 ] ) ; int posn = INTVAL ( operands [ 2 ] ) ; int mask ; rtx mreg , sreg , ereg ; if ( width == 1 && GET_CODE ( operands [ 3 ] ) == CONST_INT ) { if ( ( INTVAL ( operands [ 3 ] ) & 1 ) == 0 ) { mask = ~ ( 1 << posn ) ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , gen_rtx_AND ( SImode , operands [ 0 ] , GEN_INT ( mask ) ) ) ) ; } else { mask = 1 << posn ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , gen_rtx_IOR ( SImode , operands [ 0 ] , GEN_INT ( mask ) ) ) ) ; } return 1 ; } if ( ! TARGET_W_FIELD ) return 0 ; if ( width == 8 && posn % 8 == 0 ) return 0 ; if ( width == 16 && posn % 16 == 0 ) return 0 ; if ( GET_CODE ( operands [ 3 ] ) == CONST_INT && INTVAL ( operands [ 3 ] ) == ( ( 1 << width ) - 1 ) ) { mreg = force_reg ( SImode , GEN_INT ( INTVAL ( operands [ 3 ] ) << posn ) ) ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , gen_rtx_IOR ( SImode , operands [ 0 ] , mreg ) ) ) ; return 1 ; } mreg = force_reg ( SImode , GEN_INT ( ~ ( ( ( 1 << width ) - 1 ) << posn ) ) ) ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , gen_rtx_AND ( SImode , operands [ 0 ] , mreg ) ) ) ; if ( GET_CODE ( operands [ 3 ] ) == CONST_INT && INTVAL ( operands [ 3 ] ) == 0 ) return 1 ; sreg = copy_to_mode_reg ( SImode , operands [ 3 ] ) ; if ( width + posn != ( int ) GET_MODE_SIZE ( SImode ) ) { ereg = force_reg ( SImode , GEN_INT ( ( 1 << width ) - 1 ) ) ; emit_insn ( gen_rtx_SET ( sreg , gen_rtx_AND ( SImode , sreg , ereg ) ) ) ; } if ( posn != 0 ) emit_insn ( gen_rtx_SET ( sreg , gen_rtx_ASHIFT ( SImode , sreg , GEN_INT ( posn ) ) ) ) ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , gen_rtx_IOR ( SImode , operands [ 0 ] , sreg ) ) ) ; return 1 ; } </s>


<s> bool isLittleEndian ( ) const { return isLittle ; } </s>

Tests whether the target triple is little endian .


<s> void ix86_split_convert_uns_si_sse ( rtx operands [ ] ) { machine_mode vecmode ; rtx value , large , zero_or_two31 , input , two31 , x ; large = operands [ 1 ] ; zero_or_two31 = operands [ 2 ] ; input = operands [ 3 ] ; two31 = operands [ 4 ] ; vecmode = GET_MODE ( large ) ; value = gen_rtx_REG ( vecmode , REGNO ( operands [ 0 ] ) ) ; if ( MEM_P ( input ) ) { if ( vecmode == V4SFmode ) emit_insn ( gen_vec_setv4sf_0 ( value , CONST0_RTX ( V4SFmode ) , input ) ) ; else emit_insn ( gen_sse2_loadlpd ( value , CONST0_RTX ( V2DFmode ) , input ) ) ; } else { input = gen_rtx_REG ( vecmode , REGNO ( input ) ) ; emit_move_insn ( value , CONST0_RTX ( vecmode ) ) ; if ( vecmode == V4SFmode ) emit_insn ( gen_sse_movss_v4sf ( value , value , input ) ) ; else emit_insn ( gen_sse2_movsd_v2df ( value , value , input ) ) ; } emit_move_insn ( large , two31 ) ; emit_move_insn ( zero_or_two31 , MEM_P ( two31 ) ? large : two31 ) ; x = gen_rtx_fmt_ee ( LE , vecmode , large , value ) ; emit_insn ( gen_rtx_SET ( large , x ) ) ; x = gen_rtx_AND ( vecmode , zero_or_two31 , large ) ; emit_insn ( gen_rtx_SET ( zero_or_two31 , x ) ) ; x = gen_rtx_MINUS ( vecmode , value , zero_or_two31 ) ; emit_insn ( gen_rtx_SET ( value , x ) ) ; large = gen_rtx_REG ( V4SImode , REGNO ( large ) ) ; emit_insn ( gen_ashlv4si3 ( large , large , GEN_INT ( 31 ) ) ) ; x = gen_rtx_REG ( V4SImode , REGNO ( value ) ) ; if ( vecmode == V4SFmode ) emit_insn ( gen_fix_truncv4sfv4si2 ( x , value ) ) ; else emit_insn ( gen_sse2_cvttpd2dq ( x , value ) ) ; value = x ; emit_insn ( gen_xorv4si3 ( value , value , large ) ) ; } </s>

Post-reload splitter for converting an SF or DFmode value in an SSE register into an unsigned SImode .


<s> const TargetRegisterClass * XNCMRegisterInfo :: getPointerRegClass ( unsigned Kind ) const { return & XNCM :: GR16RegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> bool fp_zero_operand ( rtx op ) { const REAL_VALUE_TYPE * r ; if ( GET_MODE ( op ) != SFmode ) return false ; r = CONST_DOUBLE_REAL_VALUE ( op ) ; return real_equal ( r , & dconst0 ) && ! REAL_VALUE_MINUS_ZERO ( * r ) ; } </s>

Returns true if OP is a floating point value with value 0.0 .


<s> static std :: string getEdgeAttributes ( const SUnit * Node , SUnitIterator EI , const ScheduleDAG * Graph ) { if ( EI . isArtificialDep ( ) ) return "color=cyan,style=dashed" ; if ( EI . isCtrlDep ( ) ) return "color=blue,style=dashed" ; return "" ; } </s>

If you want to override the dot attributes printed for a particular edge , override this method .

Patmos "color=cyan,style=dashed" "color=blue,style=dashed" ""


"instruction requires a CPU feature not currently enabled"

"flag setting instruction only valid outside IT block"

"instruction only valid inside IT block"

"instruction variant requires ARMv6 or later"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> unsigned WebAssemblyFastISel :: fastMaterializeConstant ( const Constant * C ) { if ( const auto * GV = dyn_cast < GlobalValue > ( C ) ) { unsigned ResultReg = createResultReg ( Subtarget -> hasAddr64 ( ) ? & WebAssembly :: I64RegClass : & WebAssembly :: I32RegClass ) ; unsigned Opc = Subtarget -> hasAddr64 ( ) ? WebAssembly :: CONST_I64 : WebAssembly :: CONST_I32 ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addGlobalAddress ( GV ) ; return ResultReg ; } return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s> unsigned getNumFixupKinds ( ) const override { return VE :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> Value * ARMTargetLowering :: emitLoadLinked ( IRBuilder < > & Builder , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Type * ValTy = cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ; bool IsAcquire = isAcquireOrStronger ( Ord ) ; if ( ValTy -> getPrimitiveSizeInBits ( ) == 64 ) { Intrinsic :: ID Int = IsAcquire ? Intrinsic :: arm_ldaexd : Intrinsic :: arm_ldrexd ; Function * Ldrex = Intrinsic :: getDeclaration ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldrex , Addr , "lohi" ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Lo = Builder . CreateZExt ( Lo , ValTy , "lo64" ) ; Hi = Builder . CreateZExt ( Hi , ValTy , "hi64" ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , 32 ) ) , "val64" ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; Intrinsic :: ID Int = IsAcquire ? Intrinsic :: arm_ldaex : Intrinsic :: arm_ldrex ; Function * Ldrex = Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateTruncOrBitCast ( Builder . CreateCall ( Ldrex , Addr ) , cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ) ; } </s>

Perform a load-linked operation on Addr , returning a `` Value * '' with the corresponding pointee type .


<s>
void
ARMAsmPrinter
::
emitMachineConstantPoolValue
(
MachineConstantPoolValue
*
MCPV
)
{
const
DataLayout
&
DL
=
getDataLayout
(
)
;
int
Size
=
DL
.
getTypeAllocSize
(
MCPV
->
getType
(
)
)
;
ARMConstantPoolValue
*
ACPV
=
static_cast
<
ARMConstantPoolValue
*
>
(
MCPV
)
;
if
(
ACPV
->
isPromotedGlobal
(
)
)
{
auto
*
ACPC
=
cast
<
ARMConstantPoolConstant
>
(
ACPV
)
;
for
(
const
auto
*
GV
:
ACPC
->
promotedGlobals
(
)
)
{
if
(
!
EmittedPromotedGlobalLabels
.
count
(
GV
)
)
{
MCSymbol
*
GVSym
=
getSymbol
(
GV
)
;
OutStreamer
->
emitLabel
(
GVSym
)
;
EmittedPromotedGlobalLabels
.
insert
(
GV
)
;
}
}
return
emitGlobalConstant
(
DL
,
ACPC
->
getPromotedGlobalInit
(
)
,
0
)
;
}
MCSymbol
*
MCSym
;
if
(
ACPV
->
isLSDA
(
)
)
{
MCSym
=
getMBBExceptionSym
(
MF
->
front
(
)
)
;
}
else
if
(
ACPV
->
isBlockAddress
(
)
)
{
const
BlockAddress
*
BA
=
cast
<
ARMConstantPoolConstant
>
(
ACPV
)
->
getBlockAddress
(
)
;
MCSym
=
GetBlockAddressSymbol
(
BA
)
;
}
else
if
(
ACPV
->
isGlobalValue
(
)
)
{
const
GlobalValue
*
GV
=
cast
<
ARMConstantPoolConstant
>
(
ACPV
)
->
getGV
(
)
;
unsigned
char
TF
=
Subtarget
->
isTargetMachO
(
)
ARMII
::
MO_NONLAZY
:
0
;
MCSym
=
GetARMGVSymbol
(
GV
,
TF
)
;
}
else
if
(
ACPV
->
isMachineBasicBlock
(
)
)
{
const
MachineBasicBlock
*
MBB
=
cast
<
ARMConstantPoolMBB
>
(
ACPV
)
->
getMBB
(
)
;
MCSym
=
MBB
->
getSymbol
(
)
;
}
else
{
assert
(
ACPV
->
isExtSymbol
(
)
&&
"unrecognized constant pool value"
)
;
auto
Sym
=
cast
<
ARMConstantPoolSymbol
>
(
ACPV
)
->
getSymbol
(
)
;
MCSym
=
GetExternalSymbolSymbol
(
Sym
)
;
}
const
MCExpr
*
Expr
=
MCSymbolRefExpr
::
create
(
MCSym
,
getModifierVariantKind
(
ACPV
->
getModifier
(
)
)
,
OutContext
)
;
if
(
ACPV
->
getPCAdjustment
(
)
)
{
MCSymbol
*
PCLabel
=
getPICLabel
(
DL
.
getPrivateGlobalPrefix
(
)
,
getFunctionNumber
(
)
,
ACPV
->
getLabelId
(
)
,
OutContext
)
;
const
MCExpr
*
PCRelExpr
=
MCSymbolRefExpr
::
create
(
PCLabel
,
OutContext
)
;
PCRelExpr
=
MCBinaryExpr
::
createAdd
(
PCRelExpr
,
MCConstantExpr
::
create
(
ACPV
->
getPCAdjustment
(
)
,
OutContext
)
,
OutContext
)
;
if
(
ACPV
->
mustAddCurrentAddress
(
)
)
{
MCSymbol
*
DotSym
=
OutContext
.
createTempSymbol
(
)
;
OutStreamer
->
emitLabel
(
DotSym
)
;
const
MCExpr
*
DotExpr
=
MCSymbolRefExpr
::
create
(
DotSym
,
OutContext
)
;
PCRelExpr
=
MCBinaryExpr
::
createSub
(
PCRelExpr
,
DotExpr
,
OutContext
)
;
}
Expr
=
MCBinaryExpr
::
createSub
(
Expr
,
PCRelExpr
,
OutContext
)
;
}
OutStreamer
->
emitValue
(
Expr
,
Size
)
;
}
</s>

EmitMachineConstantPoolValue - Print a machine constantpool value to the .s file .

ARM
ARM
ARM
ARM
ARM
0
ARM
ARM
ARMII::MO_NONLAZY
0
ARM
ARM
"unrecognized constant pool value"
ARM


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> virtual const MCObjectFormat & getObjectFormat ( ) const { return Format ; } </s>


<s> static unsigned int frv_function_arg_boundary ( machine_mode mode ATTRIBUTE_UNUSED , const_tree type ATTRIBUTE_UNUSED ) { return BITS_PER_WORD ; } </s>

If defined , a C expression that gives the alignment boundary , in bits , of an argument with the specified mode and type . If it is not defined , ` PARM_BOUNDARY ' is used for all arguments .


<s> void Z80PassConfig :: addCodeGenPrepare ( ) { addPass ( createLowerSwitchPass ( ) ) ; TargetPassConfig :: addCodeGenPrepare ( ) ; } </s>

Add pass to prepare the LLVM IR for code generation .


<s> bool PPCInstrInfo :: isCoalescableExtInstr ( const MachineInstr & MI , unsigned & SrcReg , unsigned & DstReg , unsigned & SubIdx ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case PPC :: EXTSW : case PPC :: EXTSW_32 : case PPC :: EXTSW_32_64 : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; DstReg = MI . getOperand ( 0 ) . getReg ( ) ; SubIdx = PPC :: sub_32 ; return true ; } } </s>

isCoalescableExtInstr - Return true if the instruction is a `` coalescable '' extension instruction .


<s> static bool convertible_comparison_p ( rtx_insn * insn ) { if ( ! TARGET_SSE4_1 ) return false ; rtx def_set = single_set ( insn ) ; gcc_assert ( def_set ) ; rtx src = SET_SRC ( def_set ) ; rtx dst = SET_DEST ( def_set ) ; gcc_assert ( GET_CODE ( src ) == COMPARE ) ; if ( GET_CODE ( dst ) != REG || REGNO ( dst ) != FLAGS_REG || GET_MODE ( dst ) != CCZmode ) return false ; rtx op1 = XEXP ( src , 0 ) ; rtx op2 = XEXP ( src , 1 ) ; if ( op2 != CONST0_RTX ( GET_MODE ( op2 ) ) ) return false ; if ( GET_CODE ( op1 ) != IOR ) return false ; op2 = XEXP ( op1 , 1 ) ; op1 = XEXP ( op1 , 0 ) ; if ( ! SUBREG_P ( op1 ) || ! SUBREG_P ( op2 ) || GET_MODE ( op1 ) != SImode || GET_MODE ( op2 ) != SImode || ( ( SUBREG_BYTE ( op1 ) != 0 || SUBREG_BYTE ( op2 ) != GET_MODE_SIZE ( SImode ) ) && ( SUBREG_BYTE ( op2 ) != 0 || SUBREG_BYTE ( op1 ) != GET_MODE_SIZE ( SImode ) ) ) ) return false ; op1 = SUBREG_REG ( op1 ) ; op2 = SUBREG_REG ( op2 ) ; if ( op1 != op2 || ! REG_P ( op1 ) || GET_MODE ( op1 ) != DImode ) return false ; return true ; } </s>

Check if comparison INSN may be transformed into vector comparison . Currently we transform equality/inequality checks which look like : ( set ( reg : CCZ 17 flags ) ( compare : CCZ ( reg : TI x ) ( reg : TI y ) ) )


<s> unsigned SIRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return AMDGPU :: NoRegister ; } </s>


<s> static void emit_soft_tfmode_libcall ( const char * func_name , int nargs , rtx * operands ) { rtx ret_slot = NULL , arg [ 3 ] , func_sym ; int i ; gcc_assert ( nargs == 2 || nargs == 3 ) ; for ( i = 0 ; i < nargs ; ++ i ) { rtx this_arg = operands [ i ] ; rtx this_slot ; if ( GET_MODE ( this_arg ) == TFmode ) { int force_stack_temp ; force_stack_temp = 0 ; if ( TARGET_BUGGY_QP_LIB && i == 0 ) force_stack_temp = 1 ; if ( GET_CODE ( this_arg ) == MEM && ! force_stack_temp ) { tree expr = MEM_EXPR ( this_arg ) ; if ( expr ) mark_addressable ( expr ) ; this_arg = XEXP ( this_arg , 0 ) ; } else if ( CONSTANT_P ( this_arg ) && ! force_stack_temp ) { this_slot = force_const_mem ( TFmode , this_arg ) ; this_arg = XEXP ( this_slot , 0 ) ; } else { this_slot = assign_stack_temp ( TFmode , GET_MODE_SIZE ( TFmode ) ) ; if ( i > 0 ) emit_move_insn ( this_slot , this_arg ) ; else ret_slot = this_slot ; this_arg = XEXP ( this_slot , 0 ) ; } } arg [ i ] = this_arg ; } func_sym = gen_rtx_SYMBOL_REF ( Pmode , func_name ) ; if ( GET_MODE ( operands [ 0 ] ) == TFmode ) { if ( nargs == 2 ) emit_library_call ( func_sym , LCT_NORMAL , VOIDmode , arg [ 0 ] , GET_MODE ( arg [ 0 ] ) , arg [ 1 ] , GET_MODE ( arg [ 1 ] ) ) ; else emit_library_call ( func_sym , LCT_NORMAL , VOIDmode , arg [ 0 ] , GET_MODE ( arg [ 0 ] ) , arg [ 1 ] , GET_MODE ( arg [ 1 ] ) , arg [ 2 ] , GET_MODE ( arg [ 2 ] ) ) ; if ( ret_slot ) emit_move_insn ( operands [ 0 ] , ret_slot ) ; } else { rtx ret ; gcc_assert ( nargs == 2 ) ; ret = emit_library_call_value ( func_sym , operands [ 0 ] , LCT_NORMAL , GET_MODE ( operands [ 0 ] ) , arg [ 1 ] , GET_MODE ( arg [ 1 ] ) ) ; if ( ret != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , ret ) ; } } </s>

Generate a call to FUNC with OPERANDS . Operand 0 is the return value . Unlike normal calls , TFmode operands are passed by reference . It is assumed that no more than 3 operands are required .


<s> void OR1KTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; SDValue Result ( 0 , 0 ) ; if ( Constraint . length ( ) > 1 ) return ; char ConstraintLetter = Constraint [ 0 ] ; switch ( ConstraintLetter ) { default : break ; case 'I' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isInt < 16 > ( C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , dl , Op . getValueType ( ) ) ; break ; } } return ; case 'J' : case 'O' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) == 0 ) { Result = DAG . getTargetConstant ( 0 , dl , Op . getValueType ( ) ) ; break ; } } return ; case 'K' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isUInt < 16 > ( C -> getZExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , dl , Op . getValueType ( ) ) ; break ; } } return ; case 'L' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= 31 ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , dl , Op . getValueType ( ) ) ; break ; } } return ; case 'M' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { int64_t Val = C -> getSExtValue ( ) ; if ( ( isInt < 32 > ( Val ) ) && ( ( Val & 0xffff ) == 0 ) ) { Result = DAG . getTargetConstant ( Val , dl , Op . getValueType ( ) ) ; break ; } } return ; case 'N' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { int64_t Val = C -> getSExtValue ( ) ; if ( ( Val >= - 33554432 ) && ( Val <= 33554431 ) ) { Result = DAG . getTargetConstant ( Val , dl , Op . getValueType ( ) ) ; break ; } } return ; } if ( Result . getNode ( ) ) { Ops . push_back ( Result ) ; return ; } TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; } </s>

Lower the specified operand into the Ops vector .


<s>
void
PTXPassConfig
::
addMachineLateOptimization
(
)
{
if
(
addPass
(
BranchFolderPassID
)
!=
&
NoPassID
)
printNoVerify
(
"After BranchFolding"
)
;
if
(
addPass
(
TailDuplicateID
)
!=
&
NoPassID
)
printNoVerify
(
"After TailDuplicate"
)
;
}
</s>

Add passes that optimize machine instructions after register allocation .

PTX
PTX
"After BranchFolding"
"After TailDuplicate"


<s> void NVPTXPassConfig :: addPostRegAlloc ( ) { addPass ( createNVPTXPrologEpilogPass ( ) , false ) ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> bool SystemZElimCompare :: runOnMachineFunction ( MachineFunction & F ) { TII = static_cast < const SystemZInstrInfo * > ( F . getTarget ( ) . getInstrInfo ( ) ) ; TRI = & TII -> getRegisterInfo ( ) ; bool Changed = false ; for ( auto & MBB : F ) Changed |= processBlock ( MBB ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> void SITypeRewriter :: visitCallInst ( CallInst & I ) { IRBuilder < > Builder ( & I ) ; SmallVector < Value * , 8 > Args ; SmallVector < Type * , 8 > Types ; bool NeedToReplace = false ; Function * F = I . getCalledFunction ( ) ; if ( ! F ) return ; std :: string Name = F -> getName ( ) ; for ( unsigned i = 0 , e = I . getNumArgOperands ( ) ; i != e ; ++ i ) { Value * Arg = I . getArgOperand ( i ) ; if ( Arg -> getType ( ) == v16i8 ) { Args . push_back ( Builder . CreateBitCast ( Arg , v4i32 ) ) ; Types . push_back ( v4i32 ) ; NeedToReplace = true ; Name = Name + ".v4i32" ; } else if ( Arg -> getType ( ) -> isVectorTy ( ) && Arg -> getType ( ) -> getVectorNumElements ( ) == 1 && Arg -> getType ( ) -> getVectorElementType ( ) == Type :: getInt32Ty ( I . getContext ( ) ) ) { Type * ElementTy = Arg -> getType ( ) -> getVectorElementType ( ) ; std :: string TypeName = "i32" ; InsertElementInst * Def = cast < InsertElementInst > ( Arg ) ; Args . push_back ( Def -> getOperand ( 1 ) ) ; Types . push_back ( ElementTy ) ; std :: string VecTypeName = "v1" + TypeName ; Name = Name . replace ( Name . find ( VecTypeName ) , VecTypeName . length ( ) , TypeName ) ; NeedToReplace = true ; } else { Args . push_back ( Arg ) ; Types . push_back ( Arg -> getType ( ) ) ; } } if ( ! NeedToReplace ) { return ; } Function * NewF = Mod -> getFunction ( Name ) ; if ( ! NewF ) { NewF = Function :: Create ( FunctionType :: get ( F -> getReturnType ( ) , Types , false ) , GlobalValue :: ExternalLinkage , Name , Mod ) ; NewF -> setAttributes ( F -> getAttributes ( ) ) ; } I . replaceAllUsesWith ( Builder . CreateCall ( NewF , Args ) ) ; I . eraseFromParent ( ) ; } </s>


<s> bool MipsSETargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AS , Align , MachineMemOperand :: Flags , bool * Fast ) const { if ( VT . isFatPointer ( ) ) return false ; MVT :: SimpleValueType SVT = VT . getSimpleVT ( ) . SimpleTy ; if ( Subtarget . systemSupportsUnalignedAccess ( AS ) ) { if ( Fast ) { if ( Subtarget . isCheri ( ) ) * Fast = false ; else * Fast = true ; } return true ; } switch ( SVT ) { case MVT :: i64 : case MVT :: i32 : if ( Fast ) * Fast = true ; return AS == 0 ; default : return false ; } } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> const SPIRVInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s>
const
RegisterBank
&
AArch64RegisterBankInfo
::
getRegBankFromRegClass
(
const
TargetRegisterClass
&
RC
,
LLT
)
const
{
switch
(
RC
.
getID
(
)
)
{
case
AArch64
::
FPR8RegClassID
:
case
AArch64
::
FPR16RegClassID
:
case
AArch64
::
FPR16_loRegClassID
:
case
AArch64
::
FPR32_with_hsub_in_FPR16_loRegClassID
:
case
AArch64
::
FPR32RegClassID
:
case
AArch64
::
FPR64RegClassID
:
case
AArch64
::
FPR64_loRegClassID
:
case
AArch64
::
FPR128RegClassID
:
case
AArch64
::
FPR128_loRegClassID
:
case
AArch64
::
DDRegClassID
:
case
AArch64
::
DDDRegClassID
:
case
AArch64
::
DDDDRegClassID
:
case
AArch64
::
QQRegClassID
:
case
AArch64
::
QQQRegClassID
:
case
AArch64
::
QQQQRegClassID
:
return
getRegBank
(
AArch64
::
FPRRegBankID
)
;
case
AArch64
::
GPR32commonRegClassID
:
case
AArch64
::
GPR32RegClassID
:
case
AArch64
::
GPR32spRegClassID
:
case
AArch64
::
GPR32sponlyRegClassID
:
case
AArch64
::
GPR32argRegClassID
:
case
AArch64
::
GPR32allRegClassID
:
case
AArch64
::
GPR64commonRegClassID
:
case
AArch64
::
GPR64RegClassID
:
case
AArch64
::
GPR64spRegClassID
:
case
AArch64
::
GPR64sponlyRegClassID
:
case
AArch64
::
GPR64argRegClassID
:
case
AArch64
::
GPR64allRegClassID
:
case
AArch64
::
GPR64noipRegClassID
:
case
AArch64
::
GPR64common_and_GPR64noipRegClassID
:
case
AArch64
::
GPR64noip_and_tcGPR64RegClassID
:
case
AArch64
::
tcGPR64RegClassID
:
case
AArch64
::
WSeqPairsClassRegClassID
:
case
AArch64
::
XSeqPairsClassRegClassID
:
return
getRegBank
(
AArch64
::
GPRRegBankID
)
;
case
AArch64
::
CCRRegClassID
:
return
getRegBank
(
AArch64
::
CCRegBankID
)
;
default
:
llvm_unreachable
(
"Register class not supported"
)
;
}
}
</s>


<s> static int s390_adjust_priority ( rtx_insn * insn , int priority ) { if ( ! INSN_P ( insn ) ) return priority ; if ( s390_tune <= PROCESSOR_2064_Z900 ) return priority ; switch ( s390_safe_attr_type ( insn ) ) { case TYPE_FSTOREDF : case TYPE_FSTORESF : priority = priority << 3 ; break ; case TYPE_STORE : case TYPE_STM : priority = priority << 1 ; break ; default : break ; } return priority ; } </s>

A C statement ( sans semicolon ) to update the integer scheduling priority INSN_PRIORITY ( INSN ) . Reduce the priority to execute the INSN earlier , increase the priority to execute INSN later . Do not define this macro if you do not need to adjust the scheduling priorities of insns . A LA instruction maybe scheduled later , since the pipeline bypasses the calculated value .


<s> virtual const ARCompactInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s>
static
void
rs6000_elf_asm_out_constructor
(
rtx
symbol
,
int
priority
)
{
const
char
*
section
=
".ctors"
;
char
buf
[
18
]
;
if
(
priority
!=
DEFAULT_INIT_PRIORITY
)
{
sprintf
(
buf
,
".ctors.%.5u"
,
MAX_INIT_PRIORITY
priority
)
;
section
=
buf
;
}
switch_to_section
(
get_section
(
section
,
SECTION_WRITE
,
)
)
;
assemble_align
(
POINTER_SIZE
)
;
if
(
DEFAULT_ABI
==
ABI_V4
&&
(
TARGET_RELOCATABLE
||
flag_pic
>
1
)
)
{
fputs
(
"\t.long ("
,
asm_out_file
)
;
output_addr_const
(
asm_out_file
,
symbol
)
;
fputs
(
")@fixup\n"
,
asm_out_file
)
;
}
else
assemble_integer
(
symbol
,
POINTER_SIZE
/
BITS_PER_UNIT
,
POINTER_SIZE
,
1
)
;
}
</s>


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Darwin PPC Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


Store the specified register of the given register class to the specified stack frame index .


<s> bool RISCVTargetLowering :: isEligibleForTailCallOptimization ( CCState & CCInfo , CallLoweringInfo & CLI , MachineFunction & MF , const SmallVector < CCValAssign , 16 > & ArgLocs ) const { auto & Callee = CLI . Callee ; auto CalleeCC = CLI . CallConv ; auto & Outs = CLI . Outs ; auto & Caller = MF . getFunction ( ) ; auto CallerCC = Caller . getCallingConv ( ) ; if ( Caller . hasFnAttribute ( "interrupt" ) ) return false ; if ( CCInfo . getNextStackOffset ( ) != 0 ) return false ; for ( auto & VA : ArgLocs ) if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; auto IsCallerStructRet = Caller . hasStructRetAttr ( ) ; auto IsCalleeStructRet = Outs . empty ( ) ? false : Outs [ 0 ] . Flags . isSRet ( ) ; if ( IsCallerStructRet || IsCalleeStructRet ) return false ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; if ( GV -> hasExternalWeakLinkage ( ) ) return false ; } const RISCVRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( CalleeCC != CallerCC ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } for ( auto & Arg : Outs ) if ( Arg . Flags . isByVal ( ) ) return false ; return true ; } </s>

Returns true if the call can be lowered as a tail call .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"WebAssembly Register Coloring"
;
}
</s>

WebAssembly
"WebAssembly Register Coloring"


<s> MCInstrDesc const & HexagonMCInst :: getDesc ( ) const { return ( MCII -> get ( getOpcode ( ) ) ) ; } </s>

Returns the target instruction descriptor of this MachineInstr .


<s> void ConvergingVLIWScheduler :: releaseTopNode ( SUnit * SU ) { if ( SU -> isScheduled ) return ; for ( SUnit :: succ_iterator I = SU -> Preds . begin ( ) , E = SU -> Preds . end ( ) ; I != E ; ++ I ) { unsigned PredReadyCycle = I -> getSUnit ( ) -> TopReadyCycle ; unsigned MinLatency = I -> getLatency ( ) ; Top . MaxMinLatency = std :: max ( MinLatency , Top . MaxMinLatency ) ; if ( SU -> TopReadyCycle < PredReadyCycle + MinLatency ) SU -> TopReadyCycle = PredReadyCycle + MinLatency ; } Top . releaseNode ( SU , SU -> TopReadyCycle ) ; } </s>

SU has had all predecessor dependencies resolved .


"Do not know how to custom type legalize this operation!"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> void tilepro_expand_unaligned_load ( rtx dest_reg , rtx mem , HOST_WIDE_INT bitsize , HOST_WIDE_INT bit_offset , bool sign ) { machine_mode mode ; rtx addr_lo , addr_hi ; rtx mem_lo , mem_hi , hi ; rtx mema , wide_result ; int last_byte_offset ; HOST_WIDE_INT byte_offset = bit_offset / BITS_PER_UNIT ; mode = GET_MODE ( dest_reg ) ; hi = gen_reg_rtx ( mode ) ; if ( bitsize == 2 * BITS_PER_UNIT && ( bit_offset % BITS_PER_UNIT ) == 0 ) { rtx lo ; mem_lo = adjust_address ( mem , QImode , byte_offset ) ; mem_hi = adjust_address ( mem , QImode , byte_offset + 1 ) ; lo = gen_reg_rtx ( mode ) ; emit_insn ( gen_zero_extendqisi2 ( lo , mem_lo ) ) ; if ( sign ) { rtx tmp = gen_reg_rtx ( mode ) ; emit_insn ( gen_extendqisi2 ( gen_lowpart ( SImode , hi ) , mem_hi ) ) ; emit_insn ( gen_ashlsi3 ( gen_lowpart ( SImode , tmp ) , gen_lowpart ( SImode , hi ) , GEN_INT ( 8 ) ) ) ; emit_insn ( gen_iorsi3 ( gen_lowpart ( SImode , dest_reg ) , gen_lowpart ( SImode , lo ) , gen_lowpart ( SImode , tmp ) ) ) ; } else { emit_insn ( gen_zero_extendqisi2 ( gen_lowpart ( SImode , hi ) , mem_hi ) ) ; emit_insn ( gen_insn_intlb ( gen_lowpart ( SImode , dest_reg ) , gen_lowpart ( SImode , hi ) , gen_lowpart ( SImode , lo ) ) ) ; } return ; } mema = XEXP ( mem , 0 ) ; addr_lo = force_reg ( Pmode , plus_constant ( Pmode , mema , byte_offset ) ) ; mem_lo = change_address ( mem , mode , gen_rtx_AND ( Pmode , addr_lo , GEN_INT ( - 4 ) ) ) ; set_mem_alias_set ( mem_lo , 0 ) ; last_byte_offset = ( bit_offset + bitsize - 1 ) / BITS_PER_UNIT ; addr_hi = force_reg ( Pmode , plus_constant ( Pmode , mema , last_byte_offset ) ) ; mem_hi = change_address ( mem , mode , gen_rtx_AND ( Pmode , addr_hi , GEN_INT ( - 4 ) ) ) ; set_mem_alias_set ( mem_hi , 0 ) ; if ( bitsize == 32 ) { addr_lo = make_safe_from ( addr_lo , dest_reg ) ; wide_result = dest_reg ; } else { wide_result = gen_reg_rtx ( mode ) ; } emit_move_insn ( hi , mem_hi ) ; emit_move_insn ( wide_result , mem_lo ) ; emit_insn ( gen_insn_dword_align ( gen_lowpart ( SImode , wide_result ) , gen_lowpart ( SImode , wide_result ) , gen_lowpart ( SImode , hi ) , addr_lo ) ) ; if ( bitsize != 32 ) { rtx extracted = extract_bit_field ( gen_lowpart ( SImode , wide_result ) , bitsize , bit_offset % BITS_PER_UNIT , ! sign , gen_lowpart ( SImode , dest_reg ) , SImode , SImode , false ) ; if ( extracted != dest_reg ) emit_move_insn ( dest_reg , gen_lowpart ( SImode , extracted ) ) ; } } </s>


"AIX's linkage directives take a visibility setting."

"InternalLinkage should not have other visibility setting."

"CommonLinkage of XCOFF should not come to this path"

"Cannot not be both dllexport and non-default visibility"

This emits linkage information about GVSym based on GV , if this is supported by the target .


<s> static bool nds32_ict_const_p ( rtx x ) { if ( GET_CODE ( x ) == CONST ) { x = XEXP ( x , 0 ) ; return nds32_indirect_call_referenced_p ( x ) ; } return FALSE ; } </s>

Return true if x is const and the referance is ict symbol .


<s> void RISCVTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { if ( Constraint . length ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'I' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isUInt < 8 > ( C -> getZExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ) ; return ; case 'J' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isUInt < 12 > ( C -> getZExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ) ; return ; case 'K' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isInt < 16 > ( C -> getSExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ) ; return ; case 'L' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isInt < 20 > ( C -> getSExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ) ; return ; case 'M' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( C -> getZExtValue ( ) == 0x7fffffff ) Ops . push_back ( DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ) ; return ; } } TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; } </s>


<s> static tree bpf_core_newdecl ( tree type , enum bpf_builtins which ) { tree rettype ; char name [ 80 ] ; static unsigned long pai_count = 0 ; static unsigned long pfi_count = 0 ; switch ( which ) { case BPF_BUILTIN_PRESERVE_ACCESS_INDEX : { rettype = build_function_type_list ( type , type , NULL ) ; int len = snprintf ( name , sizeof ( name ) , "%s" , "__builtin_pai_" ) ; len = snprintf ( name + len , sizeof ( name ) - len , "%lu" , pai_count ++ ) ; } break ; case BPF_BUILTIN_PRESERVE_FIELD_INFO : { rettype = build_function_type_list ( unsigned_type_node , type , unsigned_type_node , NULL ) ; int len = snprintf ( name , sizeof ( name ) , "%s" , "__builtin_pfi_" ) ; len = snprintf ( name + len , sizeof ( name ) - len , "%lu" , pfi_count ++ ) ; } break ; default : gcc_unreachable ( ) ; } return add_builtin_function_ext_scope ( name , rettype , - which , BUILT_IN_MD , NULL , NULL_TREE ) ; } </s>

Synthesize a new builtin function declaration with signature TYPE . Used by bpf_resolve_overloaded_builtin to resolve calls to __builtin_preserve_access_index .


"passing %qT to argument %d of %qE, which"

" expects a vector of 32-bit or 64-bit integers"

Require argument ARGNO to be a vector displacement in a gather-style address . Return its type on success , otherwise return NUM_VECTOR_TYPES .


<s> rtx arm_return_addr ( int count , rtx frame ATTRIBUTE_UNUSED ) { if ( count != 0 ) return NULL_RTX ; return get_hard_reg_initial_val ( Pmode , LR_REGNUM ) ; } </s>

Return an RTX indicating where the return address to the calling function can be found .


<s>
AArch64TTI
::
PopcntSupportKind
AArch64TTI
::
getPopcntSupport
(
unsigned
TyWidth
)
const
{
assert
(
isPowerOf2_32
(
TyWidth
)
&&
"Ty width must be power of 2"
)
;
if
(
TyWidth
==
32
||
TyWidth
==
64
)
return
PSK_FastHardware
;
return
PSK_Software
;
}
</s>

Return hardware support for population count .


<s> bool TriCorePassConfig :: addInstSelector ( ) { addPass ( createTriCoreISelDag ( getTriCoreTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void LoongArchInstPrinter :: printRegName ( raw_ostream & O , unsigned RegNo ) const { O << '$' << getRegisterName ( RegNo ) ; } </s>


"Unable to get the legal offset for nil instruction."

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesAll ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void PTXAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst TmpInst ; LowerPTXMachineInstrToMCInst ( MI , TmpInst , * this ) ; OutStreamer . EmitInstruction ( TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool ARMTTIImpl :: isLoweredToCall ( const Function * F ) { if ( ! F -> isIntrinsic ( ) ) return BaseT :: isLoweredToCall ( F ) ; if ( F -> getName ( ) . startswith ( "llvm.arm" ) ) return false ; switch ( F -> getIntrinsicID ( ) ) { default : break ; case Intrinsic :: powi : case Intrinsic :: sin : case Intrinsic :: cos : case Intrinsic :: pow : case Intrinsic :: log : case Intrinsic :: log10 : case Intrinsic :: log2 : case Intrinsic :: exp : case Intrinsic :: exp2 : return true ; case Intrinsic :: sqrt : case Intrinsic :: fabs : case Intrinsic :: copysign : case Intrinsic :: floor : case Intrinsic :: ceil : case Intrinsic :: trunc : case Intrinsic :: rint : case Intrinsic :: nearbyint : case Intrinsic :: round : case Intrinsic :: canonicalize : case Intrinsic :: lround : case Intrinsic :: llround : case Intrinsic :: lrint : case Intrinsic :: llrint : if ( F -> getReturnType ( ) -> isDoubleTy ( ) && ! ST -> hasFP64 ( ) ) return true ; if ( F -> getReturnType ( ) -> isHalfTy ( ) && ! ST -> hasFullFP16 ( ) ) return true ; return ! ST -> hasFPARMv8Base ( ) && ! ST -> hasVFP2Base ( ) ; case Intrinsic :: masked_store : case Intrinsic :: masked_load : case Intrinsic :: masked_gather : case Intrinsic :: masked_scatter : return ! ST -> hasMVEIntegerOps ( ) ; case Intrinsic :: sadd_with_overflow : case Intrinsic :: uadd_with_overflow : case Intrinsic :: ssub_with_overflow : case Intrinsic :: usub_with_overflow : case Intrinsic :: sadd_sat : case Intrinsic :: uadd_sat : case Intrinsic :: ssub_sat : case Intrinsic :: usub_sat : return false ; } return BaseT :: isLoweredToCall ( F ) ; } </s>

Test whether calls to a function lower to actual program function calls .


<s>
SDValue
SparcTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getTarget
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_Sparc32
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
if
(
RVLocs
[
i
]
.
isRegLoc
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
Outs
[
i
]
.
Val
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
SPISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
return
DAG
.
getNode
(
SPISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


"=== RegBanks reassign analysis on function "

"RegBank reassign stall cycles verification failed."

runOnMachineFunction - Emit the function body .


<s> static bool riscv_print_operand_punct_valid_p ( unsigned char code ) { return ( code == '~' ) ; } </s>


"Should only have an r11 thunk on 64-bit targets"


<s>
static
const
char
*
avr_out_movhi_r_mr_reg_disp_tiny
(
rtx_insn
*
insn
,
rtx
op
[
]
,
int
*
plen
)
{
rtx
dest
=
op
[
0
]
;
rtx
src
=
op
[
1
]
;
rtx
base
=
XEXP
(
src
,
0
)
;
int
reg_dest
=
true_regnum
(
dest
)
;
int
reg_base
=
true_regnum
(
XEXP
(
base
,
0
)
)
;
if
(
reg_base
==
reg_dest
)
{
return
avr_asm_len
(
TINY_ADIW
(
%
I1
,
%
J1
,
%
o1
)
CR_TAB
"ld __tmp_reg__,%b1+"
CR_TAB
"ld %B0,%b1"
CR_TAB
"mov %A0,__tmp_reg__"
,
op
,
plen
,
5
)
;
}
else
{
avr_asm_len
(
TINY_ADIW
(
%
I1
,
%
J1
,
%
o1
)
CR_TAB
"ld %A0,%b1+"
CR_TAB
"ld %B0,%b1"
,
op
,
plen
,
4
)
;
if
(
!
reg_unused_after
(
insn
,
XEXP
(
base
,
0
)
)
)
avr_asm_len
(
TINY_SBIW
(
%
I1
,
%
J1
,
%
o1
+
1
)
,
op
,
plen
,
2
)
;
return
""
;
}
}
</s>

Same as movhi_r_mr , but TINY does not have ADIW , SBIW and LDD


<s> SDValue XCoreSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { unsigned SizeBitWidth = Size . getValueType ( ) . getSizeInBits ( ) ; if ( ! AlwaysInline && ( Align & 3 ) == 0 && DAG . MaskedValueIsZero ( Size , APInt ( SizeBitWidth , 3 ) ) ) { const TargetLowering & TLI = * DAG . getTarget ( ) . getTargetLowering ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = TLI . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; Entry . Node = Src ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMCPY ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( "__memcpy_4" , TLI . getPointerTy ( ) ) , & Args , 0 ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .


<s> void WebAssemblyPassConfig :: addIRPasses ( ) { if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( ) ) ; addPass ( createWebAssemblyFixFunctionBitcasts ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createWebAssemblyOptimizeReturned ( ) ) ; if ( ! EnableEmException ) { addPass ( createLowerInvokePass ( ) ) ; addPass ( createUnreachableBlockEliminationPass ( ) ) ; } if ( EnableEmException || EnableEmSjLj ) addPass ( createWebAssemblyLowerEmscriptenEHSjLj ( EnableEmException , EnableEmSjLj ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly


<s> ScheduleHazardRecognizer :: HazardType GCNHazardRecognizer :: getHazardType ( SUnit * SU , int Stalls ) { MachineInstr * MI = SU -> getInstr ( ) ; auto HazardType = IsHazardRecognizerMode ? NoopHazard : Hazard ; if ( MI -> isBundle ( ) ) return NoHazard ; if ( SIInstrInfo :: isSMRD ( * MI ) && checkSMRDHazards ( MI ) > 0 ) return HazardType ; if ( ST . hasNSAtoVMEMBug ( ) && checkNSAtoVMEMHazard ( MI ) > 0 ) return HazardType ; if ( checkFPAtomicToDenormModeHazard ( MI ) > 0 ) return HazardType ; if ( ST . hasNoDataDepHazard ( ) ) return NoHazard ; if ( ( SIInstrInfo :: isVMEM ( * MI ) || SIInstrInfo :: isFLAT ( * MI ) ) && checkVMEMHazards ( MI ) > 0 ) return HazardType ; if ( SIInstrInfo :: isVALU ( * MI ) && checkVALUHazards ( MI ) > 0 ) return HazardType ; if ( SIInstrInfo :: isDPP ( * MI ) && checkDPPHazards ( MI ) > 0 ) return HazardType ; if ( isDivFMas ( MI -> getOpcode ( ) ) && checkDivFMasHazards ( MI ) > 0 ) return HazardType ; if ( isRWLane ( MI -> getOpcode ( ) ) && checkRWLaneHazards ( MI ) > 0 ) return HazardType ; if ( ( SIInstrInfo :: isVALU ( * MI ) || SIInstrInfo :: isVMEM ( * MI ) || SIInstrInfo :: isFLAT ( * MI ) || SIInstrInfo :: isDS ( * MI ) || SIInstrInfo :: isEXP ( * MI ) ) && checkMAIVALUHazards ( MI ) > 0 ) return HazardType ; if ( isSGetReg ( MI -> getOpcode ( ) ) && checkGetRegHazards ( MI ) > 0 ) return HazardType ; if ( isSSetReg ( MI -> getOpcode ( ) ) && checkSetRegHazards ( MI ) > 0 ) return HazardType ; if ( isRFE ( MI -> getOpcode ( ) ) && checkRFEHazards ( MI ) > 0 ) return HazardType ; if ( ( ( ST . hasReadM0MovRelInterpHazard ( ) && ( TII . isVINTRP ( * MI ) || isSMovRel ( MI -> getOpcode ( ) ) ) ) || ( ST . hasReadM0SendMsgHazard ( ) && isSendMsgTraceDataOrGDS ( TII , * MI ) ) || ( ST . hasReadM0LdsDmaHazard ( ) && isLdsDma ( * MI ) ) || ( ST . hasReadM0LdsDirectHazard ( ) && MI -> readsRegister ( AMDGPU :: LDS_DIRECT ) ) ) && checkReadM0Hazards ( MI ) > 0 ) return HazardType ; if ( SIInstrInfo :: isMAI ( * MI ) && checkMAIHazards ( MI ) > 0 ) return HazardType ; if ( ( SIInstrInfo :: isVMEM ( * MI ) || SIInstrInfo :: isFLAT ( * MI ) || SIInstrInfo :: isDS ( * MI ) ) && checkMAILdStHazards ( MI ) > 0 ) return HazardType ; if ( MI -> isInlineAsm ( ) && checkInlineAsmHazards ( MI ) > 0 ) return HazardType ; return NoHazard ; } </s>

getHazardType - Return the hazard type of emitting this node .


<s>
void
ARMAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
IsPCRel
,
nullptr
)
;
if
(
!
Value
)
return
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
unsigned
FullSizeBytes
;
if
(
!
IsLittleEndian
)
FullSizeBytes
=
getFixupKindContainerSizeBytes
(
Fixup
.
getKind
(
)
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
IsLittleEndian
i
:
(
FullSizeBytes
1
i
)
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
switch
(
(
unsigned
)
Kind
)
{
case
RV16K
::
fixup_rv16k_pcrel_8bit
:
{
const
static
MCFixupKindInfo
info
{
"fixup_rv16k_pcrel_8bit"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
;
return
info
;
}
case
RV16K
::
fixup_rv16k_pcrel_16bit
:
{
const
static
MCFixupKindInfo
info
{
"fixup_rv16k_pcrel_16bit"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
;
return
info
;
}
default
:
llvm_unreachable
(
"Invalid kind!"
)
;
}
}
</s>


<s> bool ix86_check_builtin_isa_match ( unsigned int fcode , HOST_WIDE_INT * pbisa , HOST_WIDE_INT * pbisa2 ) { HOST_WIDE_INT isa = ix86_isa_flags ; HOST_WIDE_INT isa2 = ix86_isa_flags2 ; HOST_WIDE_INT bisa = ix86_builtins_isa [ fcode ] . isa ; HOST_WIDE_INT bisa2 = ix86_builtins_isa [ fcode ] . isa2 ; if ( ( ( bisa & ( OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A ) ) == ( OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A ) ) && ( isa & ( OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A ) ) != 0 ) isa |= ( OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A ) ; if ( ( ( bisa & ( OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 ) ) == ( OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 ) ) && ( isa & ( OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 ) ) != 0 ) isa |= ( OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 ) ; if ( ( ( bisa & ( OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4 ) ) == ( OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4 ) ) && ( isa & ( OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4 ) ) != 0 ) isa |= ( OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4 ) ; if ( ( ( ( bisa & ( OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL ) ) == ( OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL ) ) || ( bisa2 & OPTION_MASK_ISA2_AVXVNNI ) != 0 ) && ( ( ( isa & ( OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL ) ) == ( OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL ) ) || ( isa2 & OPTION_MASK_ISA2_AVXVNNI ) != 0 ) ) { isa |= OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL ; isa2 |= OPTION_MASK_ISA2_AVXVNNI ; } if ( ( ( ( bisa & ( OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL ) ) == ( OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL ) ) || ( bisa2 & OPTION_MASK_ISA2_AVXIFMA ) != 0 ) && ( ( ( isa & ( OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL ) ) == ( OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL ) ) || ( isa2 & OPTION_MASK_ISA2_AVXIFMA ) != 0 ) ) { isa |= OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL ; isa2 |= OPTION_MASK_ISA2_AVXIFMA ; } if ( ( ( ( bisa & OPTION_MASK_ISA_AVX512VL ) != 0 && ( bisa2 & OPTION_MASK_ISA2_AVX512BF16 ) != 0 ) && ( bisa2 & OPTION_MASK_ISA2_AVXNECONVERT ) != 0 ) && ( ( ( isa & OPTION_MASK_ISA_AVX512VL ) != 0 && ( isa2 & OPTION_MASK_ISA2_AVX512BF16 ) != 0 ) || ( isa2 & OPTION_MASK_ISA2_AVXNECONVERT ) != 0 ) ) { isa |= OPTION_MASK_ISA_AVX512VL ; isa2 |= OPTION_MASK_ISA2_AVXNECONVERT | OPTION_MASK_ISA2_AVX512BF16 ; } if ( ( bisa & OPTION_MASK_ISA_MMX ) && ! TARGET_MMX && TARGET_MMX_WITH_SSE && fcode != IX86_BUILTIN_MASKMOVQ ) { bisa &= ~ OPTION_MASK_ISA_MMX ; bisa |= OPTION_MASK_ISA_SSE2 ; } if ( pbisa ) * pbisa = bisa ; if ( pbisa2 ) * pbisa2 = bisa2 ; return ( bisa & isa ) == bisa && ( bisa2 & isa2 ) == bisa2 ; } </s>

Return true if the necessary isa options for this builtin exist , else false . fcode = DECL_MD_FUNCTION_CODE ( fndecl ) ;


"Builtin function %s requires Nios II R%d"

Implement TARGET_EXPAND_BUILTIN . Expand an expression EXP that calls a built-in function , with result going to TARGET if that 's convenient ( and in mode MODE if that 's convenient ) . SUBTARGET may be used as the target for computing one of EXP 's operands . IGNORE is nonzero if the value is to be ignored .


<s> bool RISCVAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { bool HasStdExtC = STI -> getFeatureBits ( ) [ RISCV :: FeatureStdExtC ] ; unsigned MinNopLen = HasStdExtC ? 2 : 4 ; if ( ( Count % MinNopLen ) != 0 ) return false ; for ( ; Count >= 4 ; Count -= 4 ) OS . write ( "\x13\0\0\0" , 4 ) ; if ( Count && HasStdExtC ) OS . write ( "\x01\0" , 2 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> VariantKind getKind ( ) const { return Kind ; } </s>


<s> static tree spu_build_builtin_va_list ( void ) { tree f_args , f_skip , record , type_decl ; bool owp ; record = ( * lang_hooks . types . make_type ) ( RECORD_TYPE ) ; type_decl = build_decl ( BUILTINS_LOCATION , TYPE_DECL , get_identifier ( "__va_list_tag" ) , record ) ; f_args = build_decl ( BUILTINS_LOCATION , FIELD_DECL , get_identifier ( "__args" ) , ptr_type_node ) ; f_skip = build_decl ( BUILTINS_LOCATION , FIELD_DECL , get_identifier ( "__skip" ) , ptr_type_node ) ; DECL_FIELD_CONTEXT ( f_args ) = record ; DECL_ALIGN ( f_args ) = 128 ; DECL_USER_ALIGN ( f_args ) = 1 ; DECL_FIELD_CONTEXT ( f_skip ) = record ; DECL_ALIGN ( f_skip ) = 128 ; DECL_USER_ALIGN ( f_skip ) = 1 ; TYPE_STUB_DECL ( record ) = type_decl ; TYPE_NAME ( record ) = type_decl ; TYPE_FIELDS ( record ) = f_args ; DECL_CHAIN ( f_args ) = f_skip ; owp = warn_padded ; warn_padded = false ; layout_type ( record ) ; warn_padded = owp ; return build_array_type ( record , build_index_type ( size_zero_node ) ) ; } </s>

Create and return the va_list datatype . On SPU , va_list is an array type equivalent to typedef struct __va_list_tag { void * __args __attribute__ ( ( __aligned ( 16 ) ) ) ; void * __skip __attribute__ ( ( __aligned ( 16 ) ) ) ; } va_list [ 1 ] ; where __args points to the arg that will be returned by the next va_arg ( ) , and __skip points to the previous stack frame such that when __args == __skip we should advance __args by 32 bytes .


<s>
bool
AArch64FrameLowering
::
hasFP
(
const
MachineFunction
&
MF
)
const
{
const
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
const
TargetRegisterInfo
*
RegInfo
=
MF
.
getTarget
(
)
.
getRegisterInfo
(
)
;
assert
(
!
RegInfo
->
needsStackRealignment
(
MF
)
&&
"No stack realignment on AArch64!"
)
;
return
(
MFI
->
hasCalls
(
)
||
MFI
->
hasVarSizedObjects
(
)
||
MFI
->
isFrameAddressTaken
(
)
)
;
}
</s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> unsigned X86AsmBackend :: getMaximumNopSize ( ) const { if ( STI . hasFeature ( X86 :: Mode16Bit ) ) return 4 ; if ( ! STI . hasFeature ( X86 :: FeatureNOPL ) && ! STI . hasFeature ( X86 :: Mode64Bit ) ) return 1 ; if ( STI . getFeatureBits ( ) [ X86 :: FeatureFast7ByteNOP ] ) return 7 ; if ( STI . getFeatureBits ( ) [ X86 :: FeatureFast15ByteNOP ] ) return 15 ; if ( STI . getFeatureBits ( ) [ X86 :: FeatureFast11ByteNOP ] ) return 11 ; return 10 ; } </s>

Returns the maximum size of a nop in bytes on this target .


<s> bool AMDGPUPreLegalizerCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: FailedISel ) ) return false ; auto * TPC = & getAnalysis < TargetPassConfig > ( ) ; const Function & F = MF . getFunction ( ) ; bool EnableOpt = MF . getTarget ( ) . getOptLevel ( ) != CodeGenOpt :: None && ! skipFunction ( F ) ; GISelKnownBits * KB = & getAnalysis < GISelKnownBitsAnalysis > ( ) . get ( MF ) ; MachineDominatorTree * MDT = IsOptNone ? nullptr : & getAnalysis < MachineDominatorTree > ( ) ; AMDGPUPreLegalizerCombinerInfo PCInfo ( EnableOpt , F . hasOptSize ( ) , F . hasMinSize ( ) , KB , MDT ) ; Combiner C ( PCInfo , TPC ) ; return C . combineMachineInstrs ( MF , nullptr ) ; } </s>


" Instructions Emitted in this clause\n"

ScheduleDAGMI has scheduled an instruction - tell HazardRec about it .


"SNES dynalloca stack pointer save/restore"

getPassName - Return a nice clean name for a pass .


EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static rtx fr30_function_value ( const_tree valtype , const_tree fntype_or_decli ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( TYPE_MODE ( valtype ) , RETURN_VALUE_REGNUM ) ; } </s>


<s> static void s390_function_num_hotpatch_hw ( tree decl , int * hw_before , int * hw_after ) { tree attr ; attr = lookup_attribute ( "hotpatch" , DECL_ATTRIBUTES ( decl ) ) ; if ( attr ) { tree args = TREE_VALUE ( attr ) ; * hw_before = TREE_INT_CST_LOW ( TREE_VALUE ( args ) ) ; * hw_after = TREE_INT_CST_LOW ( TREE_VALUE ( TREE_CHAIN ( args ) ) ) ; } else { * hw_before = s390_hotpatch_hw_before_label ; * hw_after = s390_hotpatch_hw_after_label ; } } </s>

Assigns the number of NOP halfwords to be emitted before and after the function label to * HW_BEFORE and * HW_AFTER . Both pointers must not be NULL . If hotpatching is disabled for the function , the values are set to zero .


<s> void aarch64_expand_vector_init ( rtx target , rtx vals ) { machine_mode mode = GET_MODE ( target ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; int n_elts = GET_MODE_NUNITS ( mode ) ; int n_var = 0 ; rtx any_const = NULL_RTX ; rtx v0 = XVECEXP ( vals , 0 , 0 ) ; bool all_same = true ; for ( int i = 0 ; i < n_elts ; ++ i ) { rtx x = XVECEXP ( vals , 0 , i ) ; if ( ! ( CONST_INT_P ( x ) || CONST_DOUBLE_P ( x ) ) ) ++ n_var ; else any_const = x ; all_same &= rtx_equal_p ( x , v0 ) ; } if ( n_var == 0 ) { rtx constant = aarch64_simd_make_constant ( vals ) ; if ( constant != NULL_RTX ) { emit_move_insn ( target , constant ) ; return ; } } if ( all_same ) { rtx x = copy_to_mode_reg ( inner_mode , v0 ) ; aarch64_emit_move ( target , gen_rtx_VEC_DUPLICATE ( mode , x ) ) ; return ; } if ( n_var != n_elts ) { rtx copy = copy_rtx ( vals ) ; for ( int i = 0 ; i < n_elts ; i ++ ) { rtx x = XVECEXP ( vals , 0 , i ) ; if ( CONST_INT_P ( x ) || CONST_DOUBLE_P ( x ) ) continue ; rtx subst = any_const ; for ( int bit = n_elts / 2 ; bit > 0 ; bit /= 2 ) { rtx test = XVECEXP ( copy , 0 , i ^ bit ) ; if ( CONST_INT_P ( test ) || CONST_DOUBLE_P ( test ) ) { subst = test ; break ; } } XVECEXP ( copy , 0 , i ) = subst ; } aarch64_expand_vector_init ( target , copy ) ; } enum insn_code icode = optab_handler ( vec_set_optab , mode ) ; gcc_assert ( icode != CODE_FOR_nothing ) ; for ( int i = 0 ; i < n_elts ; i ++ ) { rtx x = XVECEXP ( vals , 0 , i ) ; if ( CONST_INT_P ( x ) || CONST_DOUBLE_P ( x ) ) continue ; x = copy_to_mode_reg ( inner_mode , x ) ; emit_insn ( GEN_FCN ( icode ) ( target , x , GEN_INT ( i ) ) ) ; } } </s>

Expand a vector initialisation sequence , such that TARGET is initialised to contain VALS .


"InsertBranch must not be told to insert a fallthrough"

"Z80old branch conditions have one component!"

"Unconditional branch with multiple successors!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) -> findAssociatedFragment ( ) ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s> TargetPassConfig * MCS51TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new MCS51PassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


"' can not be undefined in a subtraction expression"


<s> static void ix86_recompute_optlev_based_flags ( struct gcc_options * opts , struct gcc_options * opts_set ) { if ( TARGET_64BIT_P ( opts -> x_ix86_isa_flags ) ) { if ( opts -> x_optimize >= 1 ) SET_OPTION_IF_UNSET ( opts , opts_set , flag_omit_frame_pointer , ! USE_IX86_FRAME_POINTER ) ; if ( opts -> x_flag_asynchronous_unwind_tables && TARGET_64BIT_MS_ABI ) SET_OPTION_IF_UNSET ( opts , opts_set , flag_unwind_tables , 1 ) ; if ( opts -> x_flag_asynchronous_unwind_tables == 2 ) opts -> x_flag_unwind_tables = opts -> x_flag_asynchronous_unwind_tables = 1 ; if ( opts -> x_flag_pcc_struct_return == 2 ) opts -> x_flag_pcc_struct_return = 0 ; } else { if ( opts -> x_optimize >= 1 ) SET_OPTION_IF_UNSET ( opts , opts_set , flag_omit_frame_pointer , ! ( USE_IX86_FRAME_POINTER || opts -> x_optimize_size ) ) ; if ( opts -> x_flag_asynchronous_unwind_tables == 2 ) opts -> x_flag_asynchronous_unwind_tables = ! USE_IX86_FRAME_POINTER ; if ( opts -> x_flag_pcc_struct_return == 2 ) { if ( TARGET_IAMCU_P ( opts -> x_target_flags ) ) opts -> x_flag_pcc_struct_return = 0 ; else opts -> x_flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN ; } } } </s>

( Re ) compute option overrides affected by optimization levels in target-specific ways .


<s>
void
MipsRegisterBankInfo
::
setRegBank
(
MachineInstr
&
MI
,
MachineRegisterInfo
&
MRI
)
const
{
Register
Dest
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
switch
(
MI
.
getOpcode
(
)
)
{
case
TargetOpcode
::
G_STORE
:
break
;
case
TargetOpcode
::
G_CONSTANT
:
case
TargetOpcode
::
G_LOAD
:
case
TargetOpcode
::
G_SELECT
:
case
TargetOpcode
::
G_PHI
:
case
TargetOpcode
::
G_IMPLICIT_DEF
:
{
assert
(
MRI
.
getType
(
Dest
)
==
LLT
::
scalar
(
32
)
&&
"Unexpected operand type."
)
;
MRI
.
setRegBank
(
Dest
,
getRegBank
(
Mips
::
GPRBRegBankID
)
)
;
break
;
}
case
TargetOpcode
::
G_PTR_ADD
:
{
assert
(
MRI
.
getType
(
Dest
)
.
isPointer
(
)
&&
"Unexpected operand type."
)
;
MRI
.
setRegBank
(
Dest
,
getRegBank
(
Mips
::
GPRBRegBankID
)
)
;
break
;
}
default
:
llvm_unreachable
(
"Unexpected opcode."
)
;
}
}
</s>

RegBankSelect determined that s64 operand is better to be split into two s32 operands in gprb .

Mips
Mips
0
32
"Unexpected operand type."
Mips::GPRBRegBankID
"Unexpected operand type."
Mips::GPRBRegBankID
"Unexpected opcode."


<s> bool areInlineCompatible ( const Function * Caller , const Function * Callee ) const { return true ; } </s>

Determine whether a callee with the given TLI can be inlined into caller with this TLI , based on 'nobuiltin ' attributes .


<s> static bool mn10300_return_in_memory ( tree type , tree fntype ATTRIBUTE_UNUSED ) { return ( int_size_in_bytes ( type ) > 8 || int_size_in_bytes ( type ) == 0 || TYPE_MODE ( type ) == BLKmode ) ; } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


<s> void aarch64_split_combinev16qi ( rtx operands [ 3 ] ) { unsigned int dest = REGNO ( operands [ 0 ] ) ; unsigned int src1 = REGNO ( operands [ 1 ] ) ; unsigned int src2 = REGNO ( operands [ 2 ] ) ; machine_mode halfmode = GET_MODE ( operands [ 1 ] ) ; unsigned int halfregs = HARD_REGNO_NREGS ( src1 , halfmode ) ; rtx destlo , desthi ; gcc_assert ( halfmode == V16QImode ) ; if ( src1 == dest && src2 == dest + halfregs ) { emit_note ( NOTE_INSN_DELETED ) ; return ; } destlo = gen_rtx_REG_offset ( operands [ 0 ] , halfmode , dest , 0 ) ; desthi = gen_rtx_REG_offset ( operands [ 0 ] , halfmode , dest + halfregs , GET_MODE_SIZE ( halfmode ) ) ; if ( reg_overlap_mentioned_p ( operands [ 2 ] , destlo ) && reg_overlap_mentioned_p ( operands [ 1 ] , desthi ) ) { emit_insn ( gen_xorv16qi3 ( operands [ 1 ] , operands [ 1 ] , operands [ 2 ] ) ) ; emit_insn ( gen_xorv16qi3 ( operands [ 2 ] , operands [ 1 ] , operands [ 2 ] ) ) ; emit_insn ( gen_xorv16qi3 ( operands [ 1 ] , operands [ 1 ] , operands [ 2 ] ) ) ; } else if ( ! reg_overlap_mentioned_p ( operands [ 2 ] , destlo ) ) { if ( src1 != dest ) emit_move_insn ( destlo , operands [ 1 ] ) ; if ( src2 != dest + halfregs ) emit_move_insn ( desthi , operands [ 2 ] ) ; } else { if ( src2 != dest + halfregs ) emit_move_insn ( desthi , operands [ 2 ] ) ; if ( src1 != dest ) emit_move_insn ( destlo , operands [ 1 ] ) ; } } </s>

Split operands into moves from op [ 1 ] + op [ 2 ] into op [ 0 ] .


"fixup kind VK_Mips_GOT_DISP not supported for direct object!"

getMachineOpValue - Return binary encoding of operand .


<s> void RISCVFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; RISCVFunctionInfo * RISCVFI = MF . getInfo < RISCVFunctionInfo > ( ) ; const RISCVSubtarget & STI = MF . getSubtarget < RISCVSubtarget > ( ) ; unsigned FP = STI . isRV64 ( ) ? RISCV :: fp_64 : RISCV :: fp ; if ( hasFP ( MF ) ) SavedRegs . set ( FP ) ; if ( RISCVFI -> getCallsEhReturn ( ) ) RISCVFI -> createEhDataRegsFI ( ) ; uint64_t MaxSPOffset = MF . getInfo < RISCVFunctionInfo > ( ) -> getIncomingArgSize ( ) + MFI -> estimateStackSize ( MF ) ; if ( isInt < 12 > ( MaxSPOffset ) ) return ; const TargetRegisterClass * RC = & RISCV :: GR32BitRegClass ; int FI = MF . getFrameInfo ( ) -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .

RISCV RISCV RISCV RISCV RISCV RISCV RISCV RISCV::fp_64 RISCV::fp RISCV RISCV RISCV 12 RISCV::GR32BitRegClass


<s>
bool
rvexVLIWPacketizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
DEBUG
(
errs
(
)
<<
"Voor VLIW packetizer!\n"
)
;
const
TargetInstrInfo
*
TII
=
Fn
.
getTarget
(
)
.
getInstrInfo
(
)
;
MachineLoopInfo
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
MachineDominatorTree
&
MDT
=
getAnalysis
<
MachineDominatorTree
>
(
)
;
rvexVLIWPacketizerList
Packetizer
(
Fn
,
MLI
,
MDT
)
;
assert
(
Packetizer
.
getResourceTracker
(
)
&&
"Empty DFA table!"
)
;
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
for
(
MachineBasicBlock
::
iterator
RegionEnd
=
MBB
->
end
(
)
,
MBBb
=
MBB
->
begin
(
)
;
RegionEnd
!=
MBBb
;
)
{
MachineBasicBlock
::
iterator
I
=
RegionEnd
;
for
(
;
I
!=
MBBb
;
I
)
{
if
(
TII
->
isSchedulingBoundary
(
llvm
::
prior
(
I
)
,
MBB
,
Fn
)
)
break
;
}
MachineBasicBlock
::
iterator
priorEnd
=
llvm
::
prior
(
RegionEnd
)
;
if
(
I
==
RegionEnd
||
I
==
priorEnd
)
{
RegionEnd
=
priorEnd
;
continue
;
}
Packetizer
.
PacketizeMIs
(
MBB
,
I
,
RegionEnd
)
;
RegionEnd
=
I
;
}
}
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .

rvex
rvex
"Voor VLIW packetizer!\n"
rvex
"Empty DFA table!"


<s>
bool
AArch64TargetLowering
::
lowerInterleavedStore
(
StoreInst
*
SI
,
ShuffleVectorInst
*
SVI
,
unsigned
Factor
)
const
{
assert
(
Factor
>=
2
&&
Factor
<=
getMaxSupportedInterleaveFactor
(
)
&&
"Invalid interleave factor"
)
;
VectorType
*
VecTy
=
SVI
->
getType
(
)
;
assert
(
VecTy
->
getVectorNumElements
(
)
%
Factor
==
0
&&
"Invalid interleaved store"
)
;
unsigned
NumSubElts
=
VecTy
->
getVectorNumElements
(
)
/
Factor
;
Type
*
EltTy
=
VecTy
->
getVectorElementType
(
)
;
VectorType
*
SubVecTy
=
VectorType
::
get
(
EltTy
,
NumSubElts
)
;
const
DataLayout
&
DL
=
SI
->
getModule
(
)
->
getDataLayout
(
)
;
unsigned
SubVecSize
=
DL
.
getTypeSizeInBits
(
SubVecTy
)
;
if
(
!
Subtarget
->
hasNEON
(
)
||
(
SubVecSize
!=
64
&&
SubVecSize
!=
128
)
)
return
false
;
Value
*
Op0
=
SVI
->
getOperand
(
0
)
;
Value
*
Op1
=
SVI
->
getOperand
(
1
)
;
IRBuilder
<
>
Builder
(
SI
)
;
if
(
EltTy
->
isPointerTy
(
)
)
{
Type
*
IntTy
=
DL
.
getIntPtrType
(
EltTy
)
;
unsigned
NumOpElts
=
dyn_cast
<
VectorType
>
(
Op0
->
getType
(
)
)
->
getVectorNumElements
(
)
;
Type
*
IntVecTy
=
VectorType
::
get
(
IntTy
,
NumOpElts
)
;
Op0
=
Builder
.
CreatePtrToInt
(
Op0
,
IntVecTy
)
;
Op1
=
Builder
.
CreatePtrToInt
(
Op1
,
IntVecTy
)
;
SubVecTy
=
VectorType
::
get
(
IntTy
,
NumSubElts
)
;
}
Type
*
PtrTy
=
SubVecTy
->
getPointerTo
(
SI
->
getPointerAddressSpace
(
)
)
;
Type
*
Tys
[
2
]
=
{
SubVecTy
,
PtrTy
}
;
static
const
Intrinsic
::
ID
StoreInts
[
3
]
=
{
Intrinsic
::
aarch64_neon_st2
,
Intrinsic
::
aarch64_neon_st3
,
Intrinsic
::
aarch64_neon_st4
}
;
Function
*
StNFunc
=
Intrinsic
::
getDeclaration
(
SI
->
getModule
(
)
,
StoreInts
[
Factor
2
]
,
Tys
)
;
SmallVector
<
Value
*
,
5
>
Ops
;
for
(
unsigned
i
=
0
;
i
<
Factor
;
i
++
)
Ops
.
push_back
(
Builder
.
CreateShuffleVector
(
Op0
,
Op1
,
getSequentialMask
(
Builder
,
NumSubElts
*
i
,
NumSubElts
)
)
)
;
Ops
.
push_back
(
Builder
.
CreateBitCast
(
SI
->
getPointerOperand
(
)
,
PtrTy
)
)
;
Builder
.
CreateCall
(
StNFunc
,
Ops
)
;
return
true
;
}
</s>

Lower interleaved store ( s ) into target specific instructions/intrinsics .


<s> TargetLowering :: ConstraintWeight LanaiTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & Info , const char * Constraint ) const { ConstraintWeight Weight = CW_Invalid ; Value * CallOperandVal = Info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; switch ( * Constraint ) { case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'O' : if ( isa < ConstantInt > ( CallOperandVal ) ) Weight = CW_Constant ; break ; default : Weight = TargetLowering :: getSingleConstraintMatchWeight ( Info , Constraint ) ; break ; } return Weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> bool addInstSelector ( ) override { addPass ( createUPTISelDag ( getUPTTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static const char * mips_mdebug_abi_name ( void ) { switch ( mips_abi ) { case ABI_32 : return "abi32" ; case ABI_O64 : return "abiO64" ; case ABI_N32 : return "abiN32" ; case ABI_64 : return "abi64" ; case ABI_EABI : return TARGET_64BIT ? "eabi64" : "eabi32" ; default : gcc_unreachable ( ) ; } } </s>

Return the FOO in the name of the `` .mdebug.FOO '' section associated with the current ABI .


<s> bool GCNTTIImpl :: areInlineCompatible ( const Function * Caller , const Function * Callee ) const { const TargetMachine & TM = getTLI ( ) -> getTargetMachine ( ) ; const FeatureBitset & CallerBits = TM . getSubtargetImpl ( * Caller ) -> getFeatureBits ( ) ; const FeatureBitset & CalleeBits = TM . getSubtargetImpl ( * Callee ) -> getFeatureBits ( ) ; FeatureBitset RealCallerBits = CallerBits & ~ InlineFeatureIgnoreList ; FeatureBitset RealCalleeBits = CalleeBits & ~ InlineFeatureIgnoreList ; if ( ( RealCallerBits & RealCalleeBits ) != RealCalleeBits ) return false ; AMDGPU :: SIModeRegisterDefaults CallerMode ( * Caller ) ; AMDGPU :: SIModeRegisterDefaults CalleeMode ( * Callee ) ; return CallerMode . isInlineCompatible ( CalleeMode ) ; } </s>


"Slot for FP register must be last in order to be found!"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> static int avr_num_arg_regs ( machine_mode mode , const_tree type ) { int size ; if ( mode == BLKmode ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; return ( size + 1 ) & ~ 1 ; } </s>

Returns the number of registers to allocate for a function argument .


<s> bool RISCVAsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const { int64_t Offset = int64_t ( Value ) ; switch ( ( unsigned ) Fixup . getKind ( ) ) { default : return false ; case RISCV :: fixup_riscv_rvc_branch : return Offset > 254 || Offset < - 256 ; case RISCV :: fixup_riscv_rvc_jump : return Offset > 2046 || Offset < - 2048 ; } } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> EVT getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const override { return Size >= 8 ? MVT :: i64 : MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> bool CSKYInstPrinter :: applyTargetSpecificCLOption ( StringRef Opt ) { if ( Opt == "no-aliases" ) { NoAliases = true ; return true ; } if ( Opt == "numeric" ) { ArchRegNames = true ; return true ; } return false ; } </s>

Customize the printer according to a command line option .


<s> const char * HexagonTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( HexagonISD :: NodeType ) Opcode ) { case HexagonISD :: ALLOCA : return "HexagonISD::ALLOCA" ; case HexagonISD :: AT_GOT : return "HexagonISD::AT_GOT" ; case HexagonISD :: AT_PCREL : return "HexagonISD::AT_PCREL" ; case HexagonISD :: BARRIER : return "HexagonISD::BARRIER" ; case HexagonISD :: CALL : return "HexagonISD::CALL" ; case HexagonISD :: CALLnr : return "HexagonISD::CALLnr" ; case HexagonISD :: CALLR : return "HexagonISD::CALLR" ; case HexagonISD :: COMBINE : return "HexagonISD::COMBINE" ; case HexagonISD :: CONST32_GP : return "HexagonISD::CONST32_GP" ; case HexagonISD :: CONST32 : return "HexagonISD::CONST32" ; case HexagonISD :: CP : return "HexagonISD::CP" ; case HexagonISD :: DCFETCH : return "HexagonISD::DCFETCH" ; case HexagonISD :: EH_RETURN : return "HexagonISD::EH_RETURN" ; case HexagonISD :: EXTRACTU : return "HexagonISD::EXTRACTU" ; case HexagonISD :: EXTRACTURP : return "HexagonISD::EXTRACTURP" ; case HexagonISD :: INSERT : return "HexagonISD::INSERT" ; case HexagonISD :: INSERTRP : return "HexagonISD::INSERTRP" ; case HexagonISD :: JT : return "HexagonISD::JT" ; case HexagonISD :: PACKHL : return "HexagonISD::PACKHL" ; case HexagonISD :: POPCOUNT : return "HexagonISD::POPCOUNT" ; case HexagonISD :: RET_FLAG : return "HexagonISD::RET_FLAG" ; case HexagonISD :: SHUFFEB : return "HexagonISD::SHUFFEB" ; case HexagonISD :: SHUFFEH : return "HexagonISD::SHUFFEH" ; case HexagonISD :: SHUFFOB : return "HexagonISD::SHUFFOB" ; case HexagonISD :: SHUFFOH : return "HexagonISD::SHUFFOH" ; case HexagonISD :: TC_RETURN : return "HexagonISD::TC_RETURN" ; case HexagonISD :: VCMPBEQ : return "HexagonISD::VCMPBEQ" ; case HexagonISD :: VCMPBGT : return "HexagonISD::VCMPBGT" ; case HexagonISD :: VCMPBGTU : return "HexagonISD::VCMPBGTU" ; case HexagonISD :: VCMPHEQ : return "HexagonISD::VCMPHEQ" ; case HexagonISD :: VCMPHGT : return "HexagonISD::VCMPHGT" ; case HexagonISD :: VCMPHGTU : return "HexagonISD::VCMPHGTU" ; case HexagonISD :: VCMPWEQ : return "HexagonISD::VCMPWEQ" ; case HexagonISD :: VCMPWGT : return "HexagonISD::VCMPWGT" ; case HexagonISD :: VCMPWGTU : return "HexagonISD::VCMPWGTU" ; case HexagonISD :: VCOMBINE : return "HexagonISD::VCOMBINE" ; case HexagonISD :: VPACK : return "HexagonISD::VPACK" ; case HexagonISD :: VSHLH : return "HexagonISD::VSHLH" ; case HexagonISD :: VSHLW : return "HexagonISD::VSHLW" ; case HexagonISD :: VSPLATB : return "HexagonISD::VSPLTB" ; case HexagonISD :: VSPLATH : return "HexagonISD::VSPLATH" ; case HexagonISD :: VSRAH : return "HexagonISD::VSRAH" ; case HexagonISD :: VSRAW : return "HexagonISD::VSRAW" ; case HexagonISD :: VSRLH : return "HexagonISD::VSRLH" ; case HexagonISD :: VSRLW : return "HexagonISD::VSRLW" ; case HexagonISD :: VSXTBH : return "HexagonISD::VSXTBH" ; case HexagonISD :: VSXTBW : return "HexagonISD::VSXTBW" ; case HexagonISD :: OP_END : break ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

Hexagon Hexagon HexagonISD::NodeType HexagonISD::ALLOCA "HexagonISD::ALLOCA" HexagonISD::AT_GOT "HexagonISD::AT_GOT" HexagonISD::AT_PCREL "HexagonISD::AT_PCREL" HexagonISD::BARRIER "HexagonISD::BARRIER" HexagonISD::CALL "HexagonISD::CALL" HexagonISD::CALLnr "HexagonISD::CALLnr" HexagonISD::CALLR "HexagonISD::CALLR" HexagonISD::COMBINE "HexagonISD::COMBINE" HexagonISD::CONST32_GP "HexagonISD::CONST32_GP" HexagonISD::CONST32 "HexagonISD::CONST32" HexagonISD::CP "HexagonISD::CP" HexagonISD::DCFETCH "HexagonISD::DCFETCH" HexagonISD::EH_RETURN "HexagonISD::EH_RETURN" HexagonISD::EXTRACTU "HexagonISD::EXTRACTU" HexagonISD::EXTRACTURP "HexagonISD::EXTRACTURP" HexagonISD::INSERT "HexagonISD::INSERT" HexagonISD::INSERTRP "HexagonISD::INSERTRP" HexagonISD::JT "HexagonISD::JT" HexagonISD::PACKHL "HexagonISD::PACKHL" HexagonISD::POPCOUNT "HexagonISD::POPCOUNT" HexagonISD::RET_FLAG "HexagonISD::RET_FLAG" HexagonISD::SHUFFEB "HexagonISD::SHUFFEB" HexagonISD::SHUFFEH "HexagonISD::SHUFFEH" HexagonISD::SHUFFOB "HexagonISD::SHUFFOB" HexagonISD::SHUFFOH "HexagonISD::SHUFFOH" HexagonISD::TC_RETURN "HexagonISD::TC_RETURN" HexagonISD::VCMPBEQ "HexagonISD::VCMPBEQ" HexagonISD::VCMPBGT "HexagonISD::VCMPBGT" HexagonISD::VCMPBGTU "HexagonISD::VCMPBGTU" HexagonISD::VCMPHEQ "HexagonISD::VCMPHEQ" HexagonISD::VCMPHGT "HexagonISD::VCMPHGT" HexagonISD::VCMPHGTU "HexagonISD::VCMPHGTU" HexagonISD::VCMPWEQ "HexagonISD::VCMPWEQ" HexagonISD::VCMPWGT "HexagonISD::VCMPWGT" HexagonISD::VCMPWGTU "HexagonISD::VCMPWGTU" HexagonISD::VCOMBINE "HexagonISD::VCOMBINE" HexagonISD::VPACK "HexagonISD::VPACK" HexagonISD::VSHLH "HexagonISD::VSHLH" HexagonISD::VSHLW "HexagonISD::VSHLW" HexagonISD::VSPLATB "HexagonISD::VSPLTB" HexagonISD::VSPLATH "HexagonISD::VSPLATH" HexagonISD::VSRAH "HexagonISD::VSRAH" HexagonISD::VSRAW "HexagonISD::VSRAW" HexagonISD::VSRLH "HexagonISD::VSRLH" HexagonISD::VSRLW "HexagonISD::VSRLW" HexagonISD::VSXTBH "HexagonISD::VSXTBH" HexagonISD::VSXTBW "HexagonISD::VSXTBW" HexagonISD::OP_END


<s>
void
SPScope
::
merge
(
PredicatedBlock
*
b1
,
PredicatedBlock
*
b2
)
{
b1
->
merge
(
b2
)
;
Priv
->
replaceUseOfBlockWith
(
b2
,
b1
)
;
std
::
function
<
bool
(
SPScope
*
)
>
recursiveErase
=
[
&
]
(
auto
scope
)
{
auto
iter
=
std
::
find
(
scope
->
Priv
->
Blocks
.
begin
(
)
,
scope
->
Priv
->
Blocks
.
end
(
)
,
b2
)
;
if
(
iter
!=
scope
->
Priv
->
Blocks
.
end
(
)
)
{
scope
->
Priv
->
Blocks
.
erase
(
iter
)
;
return
true
;
}
else
{
for
(
auto
subscope
:
scope
->
Priv
->
Subscopes
)
{
if
(
recursiveErase
(
subscope
)
)
{
return
true
;
}
}
return
false
;
}
}
;
auto
erased
=
recursiveErase
(
this
)
;
assert
(
erased
&&
"Block not in scope tree\n"
)
;
}
</s>


<s> unsigned int pass_s390_early_mach :: execute ( function * fun ) { rtx_insn * insn ; s390_optimize_nonescaping_tx ( ) ; s390_register_info ( ) ; if ( fun -> machine -> base_reg ) emit_insn_at_entry ( gen_main_pool ( fun -> machine -> base_reg ) ) ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) ) { annotate_constant_pool_refs ( insn ) ; df_insn_rescan ( insn ) ; } return 0 ; } </s>


<s> static rtx altivec_expand_ld_builtin ( tree exp , rtx target , bool * expandedp ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , 0 ) ; unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; tree arg0 ; machine_mode tmode , mode0 ; rtx pat , op0 ; enum insn_code icode ; switch ( fcode ) { case ALTIVEC_BUILTIN_LD_INTERNAL_16qi : icode = CODE_FOR_vector_altivec_load_v16qi ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_8hi : icode = CODE_FOR_vector_altivec_load_v8hi ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_4si : icode = CODE_FOR_vector_altivec_load_v4si ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_4sf : icode = CODE_FOR_vector_altivec_load_v4sf ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_2df : icode = CODE_FOR_vector_altivec_load_v2df ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_2di : icode = CODE_FOR_vector_altivec_load_v2di ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_1ti : icode = CODE_FOR_vector_altivec_load_v1ti ; break ; default : * expandedp = false ; return NULL_RTX ; } * expandedp = true ; arg0 = CALL_EXPR_ARG ( exp , 0 ) ; op0 = expand_normal ( arg0 ) ; tmode = insn_data [ icode ] . operand [ 0 ] . mode ; mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; if ( target == 0 || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>


<s> void push ( unsigned Weight , const Candidate && C ) { operator [ ] ( Weight ) . push_front ( C ) ; } </s>


<s>
const
MCPhysReg
*
AArch64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_AArch64_NoRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_AArch64_AllRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
CXX_FAST_TLS
)
return
MF
->
getInfo
<
AArch64FunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_AArch64_CXX_TLS_Darwin_PE_SaveList
:
CSR_AArch64_CXX_TLS_Darwin_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
.
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_AArch64_AAPCS_SwiftError_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
PreserveMost
)
return
CSR_AArch64_RT_MostRegs_SaveList
;
else
return
CSR_AArch64_AAPCS_SaveList
;
}
</s>


<s> void SPIRVAsmPrinter :: emitEndOfAsmFile ( Module & M ) { if ( ModuleSectionsEmitted == false ) { outputModuleSections ( ) ; ModuleSectionsEmitted = true ; } } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesAll ( ) ; AU . addRequired < MachineModuleInfo > ( ) ; ModulePass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void assignValueToAddress ( unsigned ValVReg , unsigned Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { if ( VA . getLocInfo ( ) == CCValAssign :: LocInfo :: AExt ) { Size = VA . getLocVT ( ) . getSizeInBits ( ) / 8 ; ValVReg = MIRBuilder . buildAnyExt ( LLT :: scalar ( Size * 8 ) , ValVReg ) -> getOperand ( 0 ) . getReg ( ) ; } auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , 1 ) ; MIRBuilder . buildStore ( ValVReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s>
void
ARMOperand
::
dump
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
CondCode
:
OS
<<
ARMCondCodeToString
(
getCondCode
(
)
)
;
break
;
case
CCOut
:
OS
<<
"<ccout "
<<
getReg
(
)
<<
">"
;
break
;
case
Immediate
:
getImm
(
)
->
print
(
OS
)
;
break
;
case
Memory
:
OS
<<
"<memory>"
;
break
;
case
Register
:
OS
<<
"<register "
<<
getReg
(
)
<<
">"
;
break
;
case
RegisterList
:
case
DPRRegisterList
:
case
SPRRegisterList
:
{
OS
<<
"<register_list "
;
const
SmallVectorImpl
<
unsigned
>
&
RegList
=
getRegList
(
)
;
for
(
SmallVectorImpl
<
unsigned
>
::
const_iterator
I
=
RegList
.
begin
(
)
,
E
=
RegList
.
end
(
)
;
I
!=
E
;
)
{
OS
<<
*
I
;
if
(
++
I
<
E
)
OS
<<
", "
;
}
OS
<<
">"
;
break
;
}
case
Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
}
}
</s>

Dump the plan to stderr ( for debugging ) .

ARM
ARM
ARM
"<ccout "
">"
"<memory>"
"<register "
">"
"<register_list "
", "
">"
"'"
"'"


<s> unsigned mmix_dbx_register_number ( unsigned regno ) { regno = MMIX_OUTPUT_REGNO ( regno ) ; return regno >= 224 ? ( regno - 224 ) : ( regno + 48 ) ; } </s>


<s> void AMDGPUTTI :: getUnrollingPreferences ( const Function * , Loop * L , UnrollingPreferences & UP ) const { UP . Threshold = 300 ; UP . MaxCount = UINT_MAX ; UP . Partial = true ; for ( const BasicBlock * BB : L -> getBlocks ( ) ) { for ( const Instruction & I : * BB ) { const GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( & I ) ; if ( ! GEP || GEP -> getAddressSpace ( ) != AMDGPUAS :: PRIVATE_ADDRESS ) continue ; const Value * Ptr = GEP -> getPointerOperand ( ) ; const AllocaInst * Alloca = dyn_cast < AllocaInst > ( GetUnderlyingObject ( Ptr ) ) ; if ( Alloca ) { UP . Threshold = 800 ; } } } } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> bool HexagonBitSimplify :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; auto & HST = MF . getSubtarget < HexagonSubtarget > ( ) ; auto & HRI = * HST . getRegisterInfo ( ) ; auto & HII = * HST . getInstrInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool Changed ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) ; const HexagonEvaluator HE ( HRI , MRI , HII , MF ) ; BitTracker BT ( HE , MF ) ; DEBUG ( BT . trace ( true ) ) ; BT . run ( ) ; MachineBasicBlock & Entry = MF . front ( ) ; RegisterSet AIG ; ConstGeneration ImmG ( BT , HII , MRI ) ; Changed |= visitBlock ( Entry , ImmG , AIG ) ; RegisterSet ARE ; RedundantInstrElimination RIE ( BT , HII , HRI , MRI ) ; bool Ried = visitBlock ( Entry , RIE , ARE ) ; if ( Ried ) { Changed = true ; BT . run ( ) ; } RegisterSet ACG ; CopyGeneration CopyG ( BT , HII , HRI , MRI ) ; Changed |= visitBlock ( Entry , CopyG , ACG ) ; RegisterSet ACP ; CopyPropagation CopyP ( HRI , MRI ) ; Changed |= visitBlock ( Entry , CopyP , ACP ) ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) || Changed ; BT . run ( ) ; RegisterSet ABS ; BitSimplification BitS ( BT , * MDT , HII , HRI , MRI , MF ) ; Changed |= visitBlock ( Entry , BitS , ABS ) ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) || Changed ; if ( Changed ) { for ( auto & B : MF ) for ( auto & I : B ) I . clearKillInfo ( ) ; DeadCodeElimination ( MF , * MDT ) . run ( ) ; } return Changed ; } </s>


<s> TargetLoweringBase :: AtomicRMWExpansionKind AArch64TargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return Size <= 128 ? AtomicRMWExpansionKind :: LLSC : AtomicRMWExpansionKind :: None ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> void d30v_expand_prologue ( ) { rtx sp = stack_pointer_rtx ; d30v_stack_t * info = d30v_stack_info ( ) ; int i ; rtx mem_di = NULL_RTX ; rtx mem_si = NULL_RTX ; int num_memrefs = ( info -> memrefs_2words + info -> memrefs_1word + info -> memrefs_varargs ) ; if ( TARGET_DEBUG_STACK ) debug_stack_info ( info ) ; if ( info -> total_size ) emit_insn ( gen_addsi3 ( sp , sp , GEN_INT ( - info -> total_size ) ) ) ; if ( num_memrefs > 1 ) { rtx save_tmp = gen_rtx ( REG , Pmode , GPR_STACK_TMP ) ; rtx post_inc = gen_rtx ( POST_INC , Pmode , save_tmp ) ; mem_di = gen_rtx ( MEM , DImode , post_inc ) ; mem_si = gen_rtx ( MEM , SImode , post_inc ) ; emit_insn ( gen_addsi3 ( save_tmp , sp , GEN_INT ( info -> save_offset ) ) ) ; } else if ( num_memrefs == 1 ) { rtx addr = plus_constant ( sp , info -> save_offset ) ; mem_di = gen_rtx ( MEM , DImode , addr ) ; mem_si = gen_rtx ( MEM , SImode , addr ) ; } for ( i = ACCUM_FIRST ; i <= ACCUM_LAST ; i ++ ) if ( info -> save_p [ i ] ) { rtx acc_tmp = gen_rtx ( REG , DImode , GPR_ATMP_FIRST ) ; emit_insn ( gen_movdi ( acc_tmp , gen_rtx ( REG , DImode , i ) ) ) ; emit_insn ( gen_movdi ( mem_di , acc_tmp ) ) ; } for ( i = GPR_FIRST ; i <= GPR_LAST ; i += 2 ) if ( info -> save_p [ i ] == 2 ) emit_insn ( gen_movdi ( mem_di , gen_rtx ( REG , DImode , i ) ) ) ; for ( i = GPR_FIRST ; i <= GPR_LAST ; i ++ ) if ( info -> save_p [ i ] == 1 ) emit_insn ( gen_movsi ( mem_si , gen_rtx ( REG , SImode , i ) ) ) ; if ( info -> varargs_p ) { if ( ( info -> memrefs_1word & 1 ) != 0 ) { rtx save_tmp = XEXP ( XEXP ( mem_si , 0 ) , 0 ) ; emit_insn ( gen_addsi3 ( save_tmp , save_tmp , GEN_INT ( UNITS_PER_WORD ) ) ) ; } for ( i = GPR_ARG_FIRST ; i <= GPR_ARG_LAST ; i += 2 ) emit_insn ( gen_movdi ( mem_di , gen_rtx ( REG , DImode , i ) ) ) ; } if ( frame_pointer_needed ) emit_move_insn ( frame_pointer_rtx , sp ) ; emit_insn ( gen_blockage ( ) ) ; } </s>

Called after register allocation to add any instructions needed for the prologue . Using a prologue insn is favored compared to putting all of the instructions in output_function_prologue ( ) , since it allows the scheduler to intermix instructions with the saves of the caller saved registers . In some cases , it might be necessary to emit a barrier instruction as the last insn to prevent such scheduling .


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT ) const override { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> bool isLittleEndian ( ) const { return IsLittleEndian ; } </s>

Tests whether the target triple is little endian .


<s>
void
SNESDAGToDAGISel
::
Select
(
SDNode
*
N
)
{
DEBUG
(
errs
(
)
<<
"Selecting: "
;
N
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
N
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
N
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
N
->
setNodeId
(
1
)
;
return
;
}
if
(
trySelect
(
N
)
)
return
;
SelectCode
(
N
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

SNES
SNES
"Selecting: "
"\n"
"== "
"\n"
1


<s> bool AMDGPUCodeGenPrepare :: isSigned ( const SelectInst & I ) const { return isa < ICmpInst > ( I . getOperand ( 0 ) ) ? cast < ICmpInst > ( I . getOperand ( 0 ) ) -> isSigned ( ) : false ; } </s>

Returns true if all source operands of the recurrence are SExtInsts .


<s> bool ARMBaseInstrInfo :: isPredicable ( MachineInstr * MI ) const { if ( ! MI -> isPredicable ( ) ) return false ; ARMFunctionInfo * AFI = MI -> getParent ( ) -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; if ( AFI -> isThumb2Function ( ) ) { if ( getSubtarget ( ) . restrictIT ( ) ) return isV8EligibleForIT ( MI ) ; } else { if ( ( MI -> getDesc ( ) . TSFlags & ARMII :: DomainMask ) == ARMII :: DomainNEON ) return false ; } return true ; } </s>

Return true if the specified instruction can be predicated .

ARM ARM ARM ARM ARMII::DomainMask ARMII::DomainNEON


<s> bool empty ( ) const { return Stack . empty ( ) || top ( ) == bottom ( ) ; } </s>

Determine whether this version information is empty ( e.g. , all version components are zero ) .


<s> static int uses_TOC ( void ) { rtx insn ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) ) { rtx pat = PATTERN ( insn ) ; int i ; if ( GET_CODE ( pat ) == PARALLEL ) for ( i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) { rtx sub = XVECEXP ( pat , 0 , i ) ; if ( GET_CODE ( sub ) == USE ) { sub = XEXP ( sub , 0 ) ; if ( GET_CODE ( sub ) == UNSPEC && XINT ( sub , 1 ) == UNSPEC_TOC ) return 1 ; } } } return 0 ; } </s>

This retuns nonzero if the current function uses the TOC . This is determined by the presence of ( unspec ... 7 ) , which is generated by the various load_toc_ * patterns .


"No offset range is defined for this opcode. "

"Please define it in the above switch statement!"


<s> SDNode * SparcDAGToDAGISel :: Select ( SDNode * N ) { SDLoc dl ( N ) ; if ( N -> isMachineOpcode ( ) ) return NULL ; switch ( N -> getOpcode ( ) ) { default : break ; case SPISD :: GLOBAL_BASE_REG : return getGlobalBaseReg ( ) ; case ISD :: SDIV : case ISD :: UDIV : { if ( N -> getValueType ( 0 ) == MVT :: i64 ) break ; SDValue DivLHS = N -> getOperand ( 0 ) ; SDValue DivRHS = N -> getOperand ( 1 ) ; SDValue TopPart ; if ( N -> getOpcode ( ) == ISD :: SDIV ) { TopPart = SDValue ( CurDAG -> getMachineNode ( SP :: SRAri , dl , MVT :: i32 , DivLHS , CurDAG -> getTargetConstant ( 31 , MVT :: i32 ) ) , 0 ) ; } else { TopPart = CurDAG -> getRegister ( SP :: G0 , MVT :: i32 ) ; } TopPart = SDValue ( CurDAG -> getMachineNode ( SP :: WRYrr , dl , MVT :: Glue , TopPart , CurDAG -> getRegister ( SP :: G0 , MVT :: i32 ) ) , 0 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: SDIV ? SP :: SDIVrr : SP :: UDIVrr ; return CurDAG -> SelectNodeTo ( N , Opcode , MVT :: i32 , DivLHS , DivRHS , TopPart ) ; } case ISD :: MULHU : case ISD :: MULHS : { SDValue MulLHS = N -> getOperand ( 0 ) ; SDValue MulRHS = N -> getOperand ( 1 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: MULHU ? SP :: UMULrr : SP :: SMULrr ; SDNode * Mul = CurDAG -> getMachineNode ( Opcode , dl , MVT :: i32 , MVT :: Glue , MulLHS , MulRHS ) ; return CurDAG -> SelectNodeTo ( N , SP :: RDY , MVT :: i32 , SDValue ( Mul , 1 ) ) ; } } return SelectCode ( N ) ; } </s>


<s> bool isToken ( ) const override { return Kind == Token ; } </s>


<s> static struct constant_pool * s390_find_pool ( struct constant_pool * pool_list , rtx insn ) { struct constant_pool * pool ; for ( pool = pool_list ; pool ; pool = pool -> next ) if ( bitmap_bit_p ( pool -> insns , INSN_UID ( insn ) ) ) break ; return pool ; } </s>

Return pool out of POOL_LIST that covers INSN .


<s>
void
AVRDAGToDAGISel
::
Select
(
SDNode
*
N
)
{
if
(
N
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
errs
(
)
<<
"== "
;
N
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
N
->
setNodeId
(
1
)
;
return
;
}
if
(
trySelect
(
N
)
)
return
;
SelectCode
(
N
)
;
}
</s>


<s> const LegalizerInfo * getLegalizerInfo ( ) const override { return Legalizer . get ( ) ; } </s>

Expose LegalizerInfo so the clients can re-use .


<s> bool X86InstructionSelector :: selectBinaryOp ( MachineInstr & I , MachineRegisterInfo & MRI , MachineFunction & MF ) const { const unsigned DefReg = I . getOperand ( 0 ) . getReg ( ) ; LLT Ty = MRI . getType ( DefReg ) ; const RegisterBank & RB = * RBI . getRegBank ( DefReg , MRI , TRI ) ; unsigned NewOpc = I . getOpcode ( ) ; switch ( NewOpc ) { case TargetOpcode :: G_FADD : NewOpc = getFAddOp ( Ty , RB ) ; break ; case TargetOpcode :: G_FSUB : NewOpc = getFSubOp ( Ty , RB ) ; break ; case TargetOpcode :: G_ADD : NewOpc = getAddOp ( Ty , RB ) ; break ; case TargetOpcode :: G_SUB : NewOpc = getSubOp ( Ty , RB ) ; break ; default : break ; } if ( NewOpc == I . getOpcode ( ) ) return false ; I . setDesc ( TII . get ( NewOpc ) ) ; return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ; } </s>

Select and emit code for a binary operator instruction , which has an opcode which directly corresponds to the given ISD opcode .


<s> const Nios2Subtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


"Stack realignment in presence of dynamic allocas is "

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> int AArch64TTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; int Cost = 0 ; if ( isWideningInstruction ( Ty , Opcode , Args ) ) Cost += ST -> getWideningBaseCost ( ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( ISD == ISD :: SDIV && Opd2Info == TargetTransformInfo :: OK_UniformConstantValue && Opd2PropInfo == TargetTransformInfo :: OP_PowerOf2 ) { Cost += getArithmeticInstrCost ( Instruction :: Add , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Sub , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Select , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: AShr , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return Cost ; } switch ( ISD ) { default : return Cost + BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: ADD : case ISD :: MUL : case ISD :: XOR : case ISD :: OR : case ISD :: AND : return ( Cost + 1 ) * LT . first ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> SDValue XCoreTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , unsigned CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_XCore ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .