<s> int store_multiple_operation ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { int count ; int mask ; int i ; unsigned int last ; rtx elt ; count = XVECLEN ( op , 0 ) ; if ( count < 2 ) return 0 ; elt = XVECEXP ( op , 0 , 0 ) ; if ( GET_CODE ( elt ) != SET || GET_CODE ( SET_DEST ( elt ) ) != REG || REGNO ( SET_DEST ( elt ) ) != STACK_POINTER_REGNUM || GET_CODE ( SET_SRC ( elt ) ) != PLUS ) return 0 ; elt = SET_SRC ( elt ) ; if ( GET_CODE ( XEXP ( elt , 0 ) ) != REG || REGNO ( XEXP ( elt , 0 ) ) != STACK_POINTER_REGNUM || GET_CODE ( XEXP ( elt , 1 ) ) != CONST_INT || INTVAL ( XEXP ( elt , 1 ) ) != - ( count - 1 ) * 4 ) return 0 ; last = LAST_EXTENDED_REGNUM + 1 ; mask = 0 ; for ( i = 1 ; i < count ; i ++ ) { elt = XVECEXP ( op , 0 , i ) ; if ( GET_CODE ( elt ) != SET || GET_CODE ( SET_DEST ( elt ) ) != MEM || GET_CODE ( SET_SRC ( elt ) ) != REG || REGNO ( SET_SRC ( elt ) ) >= last ) return 0 ; last = REGNO ( SET_SRC ( elt ) ) ; mask |= ( 1 << last ) ; elt = XEXP ( SET_DEST ( elt ) , 0 ) ; if ( GET_CODE ( elt ) != PLUS || GET_CODE ( XEXP ( elt , 0 ) ) != REG || REGNO ( XEXP ( elt , 0 ) ) != STACK_POINTER_REGNUM || GET_CODE ( XEXP ( elt , 1 ) ) != CONST_INT || INTVAL ( XEXP ( elt , 1 ) ) != - i * 4 ) return 0 ; } if ( ( mask & 0x3c000 ) != 0 && ( mask & 0x3c000 ) != 0x3c000 ) return 0 ; return mask ; } </s>

Return true if OP is a store multiple operation . It is known to be a PARALLEL and the first section will be tested . OP is the current operation . MODE is the current operation mode .


<s> static int ix86_mode_exit ( int entity ) { switch ( entity ) { case X86_DIRFLAG : return X86_DIRFLAG_ANY ; case AVX_U128 : return ix86_avx_u128_mode_exit ( ) ; case I387_ROUNDEVEN : case I387_TRUNC : case I387_FLOOR : case I387_CEIL : return I387_CW_ANY ; default : gcc_unreachable ( ) ; } } </s>

Return a mode that ENTITY is assumed to be switched to at function exit .


<s> ArrayRef < std :: pair < int , const char * >> AMDGPUInstrInfo :: getSerializableTargetIndices ( ) const { static std :: pair < int , const char * > TargetIndices [ ] = { { AMDGPU :: TI_CONSTDATA_START , "amdgpu-constdata-start" } , { AMDGPU :: TI_SCRATCH_RSRC_DWORD0 , "amdgpu-scratch-rsrc-dword0" } , { AMDGPU :: TI_SCRATCH_RSRC_DWORD1 , "amdgpu-scratch-rsrc-dword1" } , { AMDGPU :: TI_SCRATCH_RSRC_DWORD2 , "amdgpu-scratch-rsrc-dword2" } , { AMDGPU :: TI_SCRATCH_RSRC_DWORD3 , "amdgpu-scratch-rsrc-dword3" } } ; return makeArrayRef ( TargetIndices ) ; } </s>

Return an array that contains the ids of the target indices ( used for the TargetIndex machine operand ) and their names .


<s> bool SIFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MFI . hasCalls ( ) && ! MF . getInfo < SIMachineFunctionInfo > ( ) -> isEntryFunction ( ) ) { return MFI . getStackSize ( ) != 0 ; } return frameTriviallyRequiresSP ( MFI ) || MFI . isFrameAddressTaken ( ) || MF . getSubtarget < GCNSubtarget > ( ) . getRegisterInfo ( ) -> needsStackRealignment ( MF ) || MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> SDValue M68kTargetLowering :: getPICJumpTableRelocBase ( SDValue Table , SelectionDAG & DAG ) const { if ( getJumpTableEncoding ( ) == MachineJumpTableInfo :: EK_Custom32 ) return DAG . getNode ( M68kISD :: GLOBAL_BASE_REG , SDLoc ( ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; return Table ; } </s>

Returns relocation base for the given PIC jumptable .


<s> SDValue rvexTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { return Chain ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> const uint16_t * PatmosRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const TargetFrameLowering * TFI = TM . getFrameLowering ( ) ; static const uint16_t CalleeSavedRegs [ ] = { Patmos :: S0 , Patmos :: SRB , Patmos :: SRO , Patmos :: R21 , Patmos :: R22 , Patmos :: R23 , Patmos :: R24 , Patmos :: R25 , Patmos :: R26 , Patmos :: R27 , Patmos :: R28 , Patmos :: P1 , Patmos :: P2 , Patmos :: P3 , Patmos :: P4 , Patmos :: P5 , Patmos :: P6 , Patmos :: P7 , 0 } ; static const uint16_t CalleeSavedRegsFP [ ] = { Patmos :: S0 , Patmos :: SRB , Patmos :: SRO , Patmos :: R21 , Patmos :: R22 , Patmos :: R23 , Patmos :: R24 , Patmos :: R25 , Patmos :: R26 , Patmos :: R27 , Patmos :: R28 , Patmos :: RFP , Patmos :: P1 , Patmos :: P2 , Patmos :: P3 , Patmos :: P4 , Patmos :: P5 , Patmos :: P6 , Patmos :: P7 , 0 } ; return ( TFI -> hasFP ( * MF ) ) ? CalleeSavedRegsFP : CalleeSavedRegs ; } </s>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { TII = MF . getSubtarget < R600Subtarget > ( ) . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; DEBUG ( MF . dump ( ) ; ) ; OrderedBlks . clear ( ) ; Visited . clear ( ) ; FuncRep = & MF ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; DEBUG ( dbgs ( ) << "LoopInfo:\n" ; PrintLoopinfo ( * MLI ) ; ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; DEBUG ( MDT -> print ( dbgs ( ) , ( const Module * ) nullptr ) ; ) ; PDT = & getAnalysis < MachinePostDominatorTree > ( ) ; DEBUG ( PDT -> print ( dbgs ( ) ) ; ) ; prepare ( ) ; run ( ) ; DEBUG ( MF . dump ( ) ; ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> static void thumb_set_frame_pointer ( arm_stack_offsets * offsets ) { HOST_WIDE_INT amount ; rtx insn , dwarf ; amount = offsets -> outgoing_args - offsets -> locals_base ; if ( amount < 1024 ) insn = emit_insn ( gen_addsi3 ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( amount ) ) ) ; else { emit_insn ( gen_movsi ( hard_frame_pointer_rtx , GEN_INT ( amount ) ) ) ; if ( TARGET_THUMB2 ) { insn = emit_insn ( gen_addsi3 ( hard_frame_pointer_rtx , stack_pointer_rtx , hard_frame_pointer_rtx ) ) ; } else { insn = emit_insn ( gen_addsi3 ( hard_frame_pointer_rtx , hard_frame_pointer_rtx , stack_pointer_rtx ) ) ; } dwarf = gen_rtx_SET ( VOIDmode , hard_frame_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , amount ) ) ; RTX_FRAME_RELATED_P ( dwarf ) = 1 ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , dwarf ) ; } RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Set the Thumb frame pointer from the stack pointer .


<s> void i386_pe_seh_end_prologue ( FILE * f ) { if ( ! TARGET_SEH ) return ; if ( cfun -> is_thunk ) return ; cfun -> machine -> seh -> after_prologue = true ; fputs ( "\t.seh_endprologue\n" , f ) ; } </s>

Emit an assembler directive for the end of the prologue .


<s>
ChangeStatus
updateImpl
(
Attributor
&
A
)
override
{
ChangeStatus
Change
=
ChangeStatus
::
UNCHANGED
;
auto
CheckCallSite
=
[
&
]
(
AbstractCallSite
CS
)
{
Function
*
Caller
=
CS
.
getInstruction
(
)
->
getFunction
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"[AAAMDFlatWorkGroupSize] Call "
<<
Caller
->
getName
(
)
<<
"->"
<<
getAssociatedFunction
(
)
->
getName
(
)
<<
'\n'
)
;
const
auto
&
CallerInfo
=
A
.
getAAFor
<
AAAMDFlatWorkGroupSize
>
(
*
this
,
IRPosition
::
function
(
*
Caller
)
,
DepClassTy
::
REQUIRED
)
;
Change
|=
clampStateAndIndicateChange
(
this
->
getState
(
)
,
CallerInfo
.
getState
(
)
)
;
return
true
;
}
;
bool
AllCallSitesKnown
=
true
;
if
(
!
A
.
checkForAllCallSites
(
CheckCallSite
,
*
this
,
true
,
AllCallSitesKnown
)
)
return
indicatePessimisticFixpoint
(
)
;
return
Change
;
}
</s>

The actual update/transfer function which has to be implemented by the derived classes .

AMDGPU
"[AAAMDFlatWorkGroupSize] Call "
"->"


<s> static reg_class_t ix86_preferred_reload_class ( rtx x , reg_class_t regclass ) { machine_mode mode = GET_MODE ( x ) ; if ( regclass == NO_REGS ) return NO_REGS ; if ( x == CONST0_RTX ( mode ) ) return regclass ; if ( CONSTANT_P ( x ) && ( MAYBE_MMX_CLASS_P ( regclass ) || MAYBE_SSE_CLASS_P ( regclass ) || MAYBE_MASK_CLASS_P ( regclass ) ) ) return NO_REGS ; if ( CONST_DOUBLE_P ( x ) ) { if ( INTEGER_CLASS_P ( regclass ) ) return regclass ; if ( IS_STACK_MODE ( mode ) && standard_80387_constant_p ( x ) > 0 ) { if ( FLOAT_CLASS_P ( regclass ) ) return FLOAT_REGS ; else if ( regclass == FP_TOP_SSE_REGS ) return FP_TOP_REG ; else if ( regclass == FP_SECOND_SSE_REGS ) return FP_SECOND_REG ; } return NO_REGS ; } if ( SSE_FLOAT_MODE_P ( mode ) && TARGET_SSE_MATH ) return SSE_CLASS_P ( regclass ) ? regclass : NO_REGS ; if ( GET_CODE ( x ) == PLUS ) return INTEGER_CLASS_P ( regclass ) ? regclass : NO_REGS ; if ( GET_MODE ( x ) == QImode && ! CONSTANT_P ( x ) ) { if ( Q_CLASS_P ( regclass ) ) return regclass ; else if ( reg_class_subset_p ( Q_REGS , regclass ) ) return Q_REGS ; else return NO_REGS ; } return regclass ; } </s>

Put float CONST_DOUBLE in the constant pool instead of fp regs . QImode must go into class Q_REGS . Narrow ALL_REGS to GENERAL_REGS . This supports allowing movsf and movdf to do mem-to-mem moves through integer regs .


<s> bool SITargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { if ( AMDGPU :: isEntryFunctionCC ( CallConv ) ) return true ; SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , CCAssignFnForReturn ( CallConv , IsVarArg ) ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .

AMDGPU SI ISD::OutputArg AMDGPU::isEntryFunctionCC 16


<s> bool MBlazeAsmParser :: ParseInstruction ( StringRef Name , SMLoc NameLoc , SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { size_t dotLoc = Name . find ( '.' ) ; Operands . push_back ( MBlazeOperand :: CreateToken ( Name . substr ( 0 , dotLoc ) , NameLoc ) ) ; if ( dotLoc < Name . size ( ) ) Operands . push_back ( MBlazeOperand :: CreateToken ( Name . substr ( dotLoc ) , NameLoc ) ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( ! ParseOperand ( Operands ) ) return true ; while ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) && getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( ! ParseOperand ( Operands ) ) return true ; } if ( Name . startswith ( "lw" ) || Name . startswith ( "sw" ) || Name . startswith ( "lh" ) || Name . startswith ( "sh" ) || Name . startswith ( "lb" ) || Name . startswith ( "sb" ) ) return ( ParseMemory ( Operands ) == NULL ) ; return false ; } </s>

ParseInstruction - Parse one assembly instruction .

MBlaze MBlaze MBlaze 0 MBlaze "lw" "sw" "lh" "sh" "lb" "sb"


<s>
void
SIFrameLowering
::
processFunctionBeforeFrameFinalized
(
MachineFunction
&
MF
,
RegScavenger
*
RS
)
const
{
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
if
(
!
MFI
.
hasStackObjects
(
)
)
return
;
bool
MayNeedScavengingEmergencySlot
=
MFI
.
hasStackObjects
(
)
;
assert
(
(
RS
||
!
MayNeedScavengingEmergencySlot
)
&&
"RegScavenger required if spilling"
)
;
if
(
MayNeedScavengingEmergencySlot
)
{
int
ScavengeFI
=
MFI
.
CreateSpillStackObject
(
AMDGPU
::
SGPR_32RegClass
.
getSize
(
)
,
AMDGPU
::
SGPR_32RegClass
.
getAlignment
(
)
)
;
RS
->
addScavengingFrameIndex
(
ScavengeFI
)
;
}
}
</s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> static void sparc_asm_function_epilogue ( FILE * file , HOST_WIDE_INT size ATTRIBUTE_UNUSED ) { rtx insn , last_real_insn ; insn = get_last_insn ( ) ; last_real_insn = prev_real_insn ( insn ) ; if ( last_real_insn && NONJUMP_INSN_P ( last_real_insn ) && GET_CODE ( PATTERN ( last_real_insn ) ) == SEQUENCE ) last_real_insn = XVECEXP ( PATTERN ( last_real_insn ) , 0 , 0 ) ; if ( last_real_insn && CALL_P ( last_real_insn ) && ! SIBLING_CALL_P ( last_real_insn ) ) fputs ( "\tnop\n" , file ) ; sparc_output_deferred_case_vectors ( ) ; } </s>

This function generates the assembly code for function exit .


<s> static int arm_needs_doubleword_align ( machine_mode mode , const_tree type ) { if ( ! type ) return GET_MODE_ALIGNMENT ( mode ) > PARM_BOUNDARY ; if ( ! AGGREGATE_TYPE_P ( type ) ) return TYPE_ALIGN ( TYPE_MAIN_VARIANT ( type ) ) > PARM_BOUNDARY ; if ( TREE_CODE ( type ) == ARRAY_TYPE ) return TYPE_ALIGN ( TREE_TYPE ( type ) ) > PARM_BOUNDARY ; int ret = 0 ; int ret2 = 0 ; for ( tree field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) if ( DECL_ALIGN ( field ) > PARM_BOUNDARY ) { if ( TREE_CODE ( field ) == FIELD_DECL ) return 1 ; else ret = - 1 ; } else if ( TREE_CODE ( field ) == FIELD_DECL && DECL_BIT_FIELD_TYPE ( field ) && TYPE_ALIGN ( DECL_BIT_FIELD_TYPE ( field ) ) > PARM_BOUNDARY ) ret2 = 1 ; if ( ret2 ) return 2 ; return ret ; } </s>

Return 1 if double word alignment is required for argument passing . Return -1 if double word alignment used to be required for argument passing before PR77728 ABI fix , but is not required anymore . Return 0 if double word alignment is not required and was n't requried before either .


"hazard recognizer does not support bottom-up scheduling."

RecedeCycle - This callback is invoked whenever the next bottom-up instruction to be scheduled can not issue in the current cycle , either because of latency or resource conflicts .


<s> bool mips_cannot_change_mode_class ( enum machine_mode from , enum machine_mode to , enum reg_class class ) { if ( MIN ( GET_MODE_SIZE ( from ) , GET_MODE_SIZE ( to ) ) <= UNITS_PER_WORD && MAX ( GET_MODE_SIZE ( from ) , GET_MODE_SIZE ( to ) ) > UNITS_PER_WORD ) { if ( TARGET_BIG_ENDIAN ) { if ( FP_INC > 1 && reg_classes_intersect_p ( FP_REGS , class ) ) return true ; } else { if ( reg_classes_intersect_p ( ACC_REGS , class ) ) return true ; } } if ( TARGET_FLOAT64 && from == SImode && GET_MODE_SIZE ( to ) >= UNITS_PER_WORD && reg_classes_intersect_p ( FP_REGS , class ) ) return true ; return false ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
void
BPFDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
DEBUG
(
dbgs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;
return
;
}
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
SDIV
:
{
DebugLoc
Empty
;
const
DebugLoc
&
DL
=
Node
->
getDebugLoc
(
)
;
if
(
DL
!=
Empty
)
errs
(
)
<<
"Error at line "
<<
DL
.
getLine
(
)
<<
": "
;
else
errs
(
)
<<
"Error: "
;
errs
(
)
<<
"Unsupport signed division for DAG: "
;
Node
->
print
(
errs
(
)
,
CurDAG
)
;
errs
(
)
<<
"Please convert to unsigned div/mod.\n"
;
break
;
}
case
ISD
::
INTRINSIC_W_CHAIN
:
{
unsigned
IntNo
=
cast
<
ConstantSDNode
>
(
Node
->
getOperand
(
1
)
)
->
getZExtValue
(
)
;
switch
(
IntNo
)
{
case
Intrinsic
::
bpf_load_byte
:
case
Intrinsic
::
bpf_load_half
:
case
Intrinsic
::
bpf_load_word
:
{
SDLoc
DL
(
Node
)
;
SDValue
Chain
=
Node
->
getOperand
(
0
)
;
SDValue
N1
=
Node
->
getOperand
(
1
)
;
SDValue
Skb
=
Node
->
getOperand
(
2
)
;
SDValue
N3
=
Node
->
getOperand
(
3
)
;
SDValue
R6Reg
=
CurDAG
->
getRegister
(
BPF
::
R6
,
MVT
::
i64
)
;
Chain
=
CurDAG
->
getCopyToReg
(
Chain
,
DL
,
R6Reg
,
Skb
,
SDValue
(
)
)
;
Node
=
CurDAG
->
UpdateNodeOperands
(
Node
,
Chain
,
N1
,
R6Reg
,
N3
)
;
break
;
}
}
break
;
}
case
ISD
::
FrameIndex
:
{
int
FI
=
cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
EVT
VT
=
Node
->
getValueType
(
0
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
VT
)
;
unsigned
Opc
=
BPF
::
MOV_rr
;
if
(
Node
->
hasOneUse
(
)
)
{
CurDAG
->
SelectNodeTo
(
Node
,
Opc
,
VT
,
TFI
)
;
return
;
}
ReplaceNode
(
Node
,
CurDAG
->
getMachineNode
(
Opc
,
SDLoc
(
Node
)
,
VT
,
TFI
)
)
;
return
;
}
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> void emit_shift ( enum rtx_code code , rtx op0 , rtx op1 , rtx op2 ) { rtx shift = gen_rtx_fmt_ee ( code , SImode , op1 , op2 ) ; rtx pat = ( ( shift4_operator ( shift , SImode ) ? gen_shift_si3 : gen_shift_si3_loop ) ( op0 , op1 , op2 , shift ) ) ; emit_insn ( pat ) ; } </s>

Emit a shift insn to set OP0 to OP1 shifted by OP2 ; CODE specifies what kind of shift .


<s> void alpha_emit_xfloating_arith ( enum rtx_code code , rtx operands [ ] ) { rtx func ; int mode ; rtx out_operands [ 3 ] ; func = alpha_lookup_xfloating_lib_func ( code ) ; mode = alpha_compute_xfloating_mode_arg ( code , alpha_fprm ) ; out_operands [ 0 ] = operands [ 1 ] ; out_operands [ 1 ] = operands [ 2 ] ; out_operands [ 2 ] = GEN_INT ( mode ) ; alpha_emit_xfloating_libcall ( func , operands [ 0 ] , out_operands , 3 , gen_rtx_fmt_ee ( code , TFmode , operands [ 1 ] , operands [ 2 ] ) ) ; } </s>

Emit an X_floating library function call for arithmetic ( + , - , * , / ) .


<s> SDValue AArch64TargetLowering :: BuildSDIVPow2 ( SDNode * N , const APInt & Divisor , SelectionDAG & DAG , std :: vector < SDNode * > * Created ) const { AttributeList Attr = DAG . getMachineFunction ( ) . getFunction ( ) -> getAttributes ( ) ; if ( isIntDivCheap ( N -> getValueType ( 0 ) , Attr ) ) return SDValue ( N , 0 ) ; EVT VT = N -> getValueType ( 0 ) ; if ( ( VT != MVT :: i32 && VT != MVT :: i64 ) || ! ( Divisor . isPowerOf2 ( ) || ( - Divisor ) . isPowerOf2 ( ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( 0 ) ; unsigned Lg2 = Divisor . countTrailingZeros ( ) ; SDValue Zero = DAG . getConstant ( 0 , DL , VT ) ; SDValue Pow2MinusOne = DAG . getConstant ( ( 1ULL << Lg2 ) - 1 , DL , VT ) ; SDValue CCVal ; SDValue Cmp = getAArch64Cmp ( N0 , Zero , ISD :: SETLT , CCVal , DAG , DL ) ; SDValue Add = DAG . getNode ( ISD :: ADD , DL , VT , N0 , Pow2MinusOne ) ; SDValue CSel = DAG . getNode ( AArch64ISD :: CSEL , DL , VT , Add , N0 , CCVal , Cmp ) ; if ( Created ) { Created -> push_back ( Cmp . getNode ( ) ) ; Created -> push_back ( Add . getNode ( ) ) ; Created -> push_back ( CSel . getNode ( ) ) ; } SDValue SRA = DAG . getNode ( ISD :: SRA , DL , VT , CSel , DAG . getConstant ( Lg2 , DL , MVT :: i64 ) ) ; if ( Divisor . isNonNegative ( ) ) return SRA ; if ( Created ) Created -> push_back ( SRA . getNode ( ) ) ; return DAG . getNode ( ISD :: SUB , DL , VT , DAG . getConstant ( 0 , DL , VT ) , SRA ) ; } </s>

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators .


<s> void MipsTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF :: SHF_MIPS_GPREL ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF :: SHF_MIPS_GPREL ) ; this -> TM = & static_cast < const MipsTargetMachine & > ( TM ) ; } </s>

This method must be called before any actual lowering is done .


<s> static bool aarch64_sve_cmp_operand_p ( rtx_code op_code , rtx x ) { if ( register_operand ( x , VOIDmode ) ) return true ; switch ( op_code ) { case LTU : case LEU : case GEU : case GTU : return aarch64_sve_cmp_immediate_p ( x , false ) ; case LT : case LE : case GE : case GT : case NE : case EQ : return aarch64_sve_cmp_immediate_p ( x , true ) ; default : gcc_unreachable ( ) ; } } </s>

Return true if X is a valid second operand for the SVE instruction that implements integer comparison OP_CODE .


<s> static int get_arc_condition_code ( rtx comparison ) { switch ( GET_MODE ( XEXP ( comparison , 0 ) ) ) { case CCmode : case SImode : switch ( GET_CODE ( comparison ) ) { case EQ : return ARC_CC_EQ ; case NE : return ARC_CC_NE ; case GT : return ARC_CC_GT ; case LE : return ARC_CC_LE ; case GE : return ARC_CC_GE ; case LT : return ARC_CC_LT ; case GTU : return ARC_CC_HI ; case LEU : return ARC_CC_LS ; case LTU : return ARC_CC_LO ; case GEU : return ARC_CC_HS ; default : gcc_unreachable ( ) ; } case CC_ZNmode : switch ( GET_CODE ( comparison ) ) { case EQ : return ARC_CC_EQ ; case NE : return ARC_CC_NE ; case GE : return ARC_CC_P ; case LT : return ARC_CC_N ; case GT : return ARC_CC_PNZ ; default : gcc_unreachable ( ) ; } case CC_Zmode : switch ( GET_CODE ( comparison ) ) { case EQ : return ARC_CC_EQ ; case NE : return ARC_CC_NE ; default : gcc_unreachable ( ) ; } case CC_Cmode : switch ( GET_CODE ( comparison ) ) { case LTU : return ARC_CC_C ; case GEU : return ARC_CC_NC ; default : gcc_unreachable ( ) ; } case CC_FP_GTmode : if ( TARGET_ARGONAUT_SET && TARGET_SPFP ) switch ( GET_CODE ( comparison ) ) { case GT : return ARC_CC_N ; case UNLE : return ARC_CC_P ; default : gcc_unreachable ( ) ; } else switch ( GET_CODE ( comparison ) ) { case GT : return ARC_CC_HI ; case UNLE : return ARC_CC_LS ; default : gcc_unreachable ( ) ; } case CC_FP_GEmode : switch ( GET_CODE ( comparison ) ) { case GE : return ARC_CC_HS ; case UNLT : return ARC_CC_LO ; default : gcc_unreachable ( ) ; } case CC_FP_UNEQmode : switch ( GET_CODE ( comparison ) ) { case UNEQ : return ARC_CC_EQ ; case LTGT : return ARC_CC_NE ; default : gcc_unreachable ( ) ; } case CC_FP_ORDmode : switch ( GET_CODE ( comparison ) ) { case UNORDERED : return ARC_CC_C ; case ORDERED : return ARC_CC_NC ; default : gcc_unreachable ( ) ; } case CC_FPXmode : switch ( GET_CODE ( comparison ) ) { case EQ : return ARC_CC_EQ ; case NE : return ARC_CC_NE ; case UNORDERED : return ARC_CC_C ; case ORDERED : return ARC_CC_NC ; case LTGT : return ARC_CC_HI ; case UNEQ : return ARC_CC_LS ; default : gcc_unreachable ( ) ; } default : gcc_unreachable ( ) ; } return ( 42 ) ; } </s>

Returns the index of the ARC condition code string in ` arc_condition_codes ' . COMPARISON should be an rtx like ` ( eq ( ... ) ( ... ) ) ' .


<s> static bool sparc_vectorize_vec_perm_const ( machine_mode vmode , rtx target , rtx op0 , rtx op1 , const vec_perm_indices & sel ) { if ( ! TARGET_VIS2 ) return false ; if ( ! target ) return true ; if ( vmode != V8QImode ) return false ; rtx nop0 = force_reg ( vmode , op0 ) ; if ( op0 == op1 ) op1 = nop0 ; op0 = nop0 ; op1 = force_reg ( vmode , op1 ) ; unsigned int i , mask ; for ( i = mask = 0 ; i < 8 ; ++ i ) mask |= ( sel [ i ] & 0xf ) << ( 28 - i * 4 ) ; rtx mask_rtx = force_reg ( SImode , gen_int_mode ( mask , SImode ) ) ; emit_insn ( gen_bmasksi_vis ( gen_reg_rtx ( SImode ) , mask_rtx , const0_rtx ) ) ; emit_insn ( gen_bshufflev8qi_vis ( target , op0 , op1 ) ) ; return true ; } </s>


<s>
int
M680x0RegisterInfo
::
getSpillRegisterOrder
(
unsigned
Reg
)
const
{
int
Result
=
getRegisterOrder
(
Reg
,
*
getRegClass
(
M680x0
::
SPILLRegClassID
)
)
;
if
(
Result
<
0
)
{
llvm_unreachable
(
"Cannot determine spill order"
)
;
}
return
Result
;
}
</s>

Return spill order index of a register , if there is none then trap .


<s> int frv_expand_block_clear ( rtx operands [ ] ) { rtx orig_dest = operands [ 0 ] ; rtx bytes_rtx = operands [ 1 ] ; rtx align_rtx = operands [ 3 ] ; int constp = ( GET_CODE ( bytes_rtx ) == CONST_INT ) ; int align ; int bytes ; int offset ; int num_reg ; rtx dest_reg ; rtx dest_addr ; rtx dest_mem ; int clear_bytes ; enum machine_mode mode ; if ( ! constp ) return FALSE ; gcc_assert ( GET_CODE ( align_rtx ) == CONST_INT ) ; align = INTVAL ( align_rtx ) ; bytes = INTVAL ( bytes_rtx ) ; if ( bytes <= 0 ) return TRUE ; if ( bytes > TOTAL_MOVE_REG * align ) return FALSE ; dest_reg = copy_addr_to_reg ( XEXP ( orig_dest , 0 ) ) ; num_reg = offset = 0 ; for ( ; bytes > 0 ; ( bytes -= clear_bytes ) , ( offset += clear_bytes ) ) { dest_addr = ( ( offset == 0 ) ? dest_reg : plus_constant ( dest_reg , offset ) ) ; if ( bytes >= 4 && align >= 4 ) mode = SImode ; else if ( bytes >= 2 && align >= 2 ) mode = HImode ; else mode = QImode ; clear_bytes = GET_MODE_SIZE ( mode ) ; dest_mem = change_address ( orig_dest , mode , dest_addr ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest_mem , const0_rtx ) ) ; } return TRUE ; } </s>

Expand a block clear operation , and return 1 if successful . Return 0 if we should let the compiler generate normal code . operands [ 0 ] is the destination operands [ 1 ] is the length operands [ 3 ] is the alignment


<s> void GCNPassConfig :: addPreEmitPass ( ) { addPass ( createSIMemoryLegalizerPass ( ) ) ; addPass ( createSIInsertWaitcntsPass ( ) ) ; addPass ( createSIShrinkInstructionsPass ( ) ) ; addPass ( createSIModeRegisterPass ( ) ) ; addPass ( & PostRAHazardRecognizerID ) ; addPass ( & SIInsertSkipsPassID ) ; addPass ( & BranchRelaxationPassID ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


"rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n"

A C expressions returning the cost of moving data of MODE from a register to or from memory .


<s> SDValue X86SelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { if ( DstPtrInfo . getAddrSpace ( ) >= 256 || SrcPtrInfo . getAddrSpace ( ) >= 256 ) return SDValue ( ) ; const MCPhysReg ClobberSet [ ] = { X86 :: RCX , X86 :: RSI , X86 :: RDI , X86 :: ECX , X86 :: ESI , X86 :: EDI } ; if ( isBaseRegConflictPossible ( DAG , ClobberSet ) ) return SDValue ( ) ; const X86Subtarget & Subtarget = DAG . getMachineFunction ( ) . getSubtarget < X86Subtarget > ( ) ; if ( UseFSRMForMemcpy && Subtarget . hasFSRM ( ) ) return emitRepmovs ( Subtarget , DAG , dl , Chain , Dst , Src , Size , MVT :: i8 ) ; if ( ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ) return emitConstantSizeRepmov ( DAG , Subtarget , dl , Chain , Dst , Src , ConstantSize -> getZExtValue ( ) , Size . getValueType ( ) , Alignment . value ( ) , isVolatile , AlwaysInline , DstPtrInfo , SrcPtrInfo ) ; return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .


<s> bool SystemZTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , Align , MachineMemOperand :: Flags , bool * Fast ) const { if ( Fast ) * Fast = true ; return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s>
bool
HexagonPassConfig
::
addInstSelector
(
)
{
HexagonTargetMachine
&
TM
=
getHexagonTargetMachine
(
)
;
bool
NoOpt
=
(
getOptLevel
(
)
==
CodeGenOpt
::
)
;
if
(
!
NoOpt
)
addPass
(
createHexagonOptimizeSZextends
(
)
)
;
addPass
(
createHexagonISelDag
(
TM
,
getOptLevel
(
)
)
)
;
if
(
!
NoOpt
)
{
if
(
EnableGenPred
)
addPass
(
createHexagonGenPredicate
(
)
,
false
)
;
if
(
EnableLoopResched
)
addPass
(
createHexagonLoopRescheduling
(
)
,
false
)
;
if
(
!
DisableHSDR
)
addPass
(
createHexagonSplitDoubleRegs
(
)
)
;
if
(
EnableBitSimplify
)
addPass
(
createHexagonBitSimplify
(
)
,
false
)
;
addPass
(
createHexagonPeephole
(
)
)
;
printAndVerify
(
"After hexagon peephole pass"
)
;
if
(
EnableGenInsert
)
addPass
(
createHexagonGenInsert
(
)
,
false
)
;
if
(
EnableEarlyIf
)
addPass
(
createHexagonEarlyIfConversion
(
)
,
false
)
;
}
return
false
;
}
</s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .

Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
"After hexagon peephole pass"
Hexagon
Hexagon


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { const PPCSubtarget & STI = MF . getSubtarget < PPCSubtarget > ( ) ; if ( ! STI . hasVSX ( ) ) return false ; LIS = & getAnalysis < LiveIntervals > ( ) ; TII = STI . getInstrInfo ( ) ; bool Changed = false ; if ( DisableVSXFMAMutate ) return Changed ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed = true ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


"Can't return value from vararg function in memory"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> pop ( unsigned i ) : i ( i ) { } </s>


<s> std :: string LineReader :: readLine ( unsigned lineNum ) { if ( lineNum < theCurLine ) { theCurLine = 0 ; fstr . seekg ( 0 , std :: ios :: beg ) ; } while ( theCurLine < lineNum ) { fstr . getline ( buff , 500 ) ; theCurLine ++ ; } return buff ; } </s>


"This eliminateCallFramePseudoInstr does not support Thumb1!"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static bool microblaze_legitimate_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { if ( microblaze_cannot_force_const_mem ( mode , x ) ) return false ; if ( GET_CODE ( x ) == CONST_DOUBLE ) { return microblaze_const_double_ok ( x , GET_MODE ( x ) ) ; } if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS ) { rtx p0 , p1 ; p0 = XEXP ( XEXP ( x , 0 ) , 0 ) ; p1 = XEXP ( XEXP ( x , 0 ) , 1 ) ; if ( GET_CODE ( p1 ) == CONST_INT ) { if ( ( GET_CODE ( p0 ) == UNSPEC ) ) return false ; if ( ( GET_CODE ( p0 ) == SYMBOL_REF || GET_CODE ( p0 ) == LABEL_REF ) && ( microblaze_tls_symbol_p ( p0 ) || ! SMALL_INT ( p1 ) ) ) return false ; } } return true ; } </s>

Implement TARGET_LEGITIMATE_CONSTANT_P . At present , GAS does n't understand li . [ sd ] , so do n't allow it to be generated at present .


<s> const PPCMCExpr * PPCMCExpr :: Create ( VariantKind Kind , const MCExpr * Expr , bool isDarwin , MCContext & Ctx ) { return new ( Ctx ) PPCMCExpr ( Kind , Expr , isDarwin ) ; } </s>

Construct a unary instruction , given the opcode and an operand .


<s> MCSymbol * OR1KMCInstLower :: GetBlockAddressSymbol ( const MachineOperand & MO ) const { return Printer . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; } </s>

Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block .


<s> bool isLegalMaskedStore ( Type * DataTy , Align Alignment ) { return isLegalMaskedLoad ( DataTy , Alignment ) ; } </s>

Return true if the target supports masked store .


<s> void MipsTargetELFStreamer :: emitAssignment ( MCSymbol * Symbol , const MCExpr * Value ) { if ( Value -> getKind ( ) != MCExpr :: SymbolRef ) return ; const MCSymbol & RhsSym = static_cast < const MCSymbolRefExpr * > ( Value ) -> getSymbol ( ) ; MCSymbolData & Data = getStreamer ( ) . getOrCreateSymbolData ( & RhsSym ) ; uint8_t Type = MCELF :: GetType ( Data ) ; if ( ( Type != ELF :: STT_FUNC ) || ! ( MCELF :: getOther ( Data ) & ( ELF :: STO_MIPS_MICROMIPS >> 2 ) ) ) return ; MCSymbolData & SymbolData = getStreamer ( ) . getOrCreateSymbolData ( Symbol ) ; MCELF :: setOther ( SymbolData , ELF :: STO_MIPS_MICROMIPS >> 2 ) ; } </s>


<s> bool MOSCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const auto & TFI = static_cast < const MOSFrameLowering & > ( * MF . getSubtarget ( ) . getFrameLowering ( ) ) ; if ( TFI . isISR ( MF ) ) MIRBuilder . buildInstr ( MOS :: CLD_Implied ) ; SmallVector < ArgInfo > SplitArgs ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) . isZero ( ) ) continue ; ArgInfo OrigArg { VRegs [ Idx ] , Arg . getType ( ) , Idx } ; setArgFlags ( OrigArg , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL ) ; ++ Idx ; } MOSIncomingArgsHandler Handler ( MIRBuilder , MRI ) ; MOSValueAssigner Assigner ( true , MRI , MF ) ; if ( ! determineAndHandleAssignments ( Handler , Assigner , SplitArgs , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ) return false ; if ( F . isVarArg ( ) ) { auto * FuncInfo = MF . getInfo < MOSFunctionInfo > ( ) ; FuncInfo -> setVarArgsStackIndex ( MF . getFrameInfo ( ) . CreateFixedObject ( 1 , Assigner . StackOffset , true ) ) ; } return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .

MOS MOS MOS MOS::CLD_Implied 0 MOS MOS MOS 1


<s> bool isMem ( ) const override { return Kind == k_Memory ; } </s>


<s> unsigned TeakInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { return get ( MI . getOpcode ( ) ) . getSize ( ) >> 1 ; } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> static unsigned estimateStackSize ( MachineFunction & MF ) { const MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; int Offset = 0 ; for ( int i = FFI -> getObjectIndexBegin ( ) ; i != 0 ; ++ i ) { int FixedOff = - FFI -> getObjectOffset ( i ) ; if ( FixedOff > Offset ) Offset = FixedOff ; } for ( unsigned i = 0 , e = FFI -> getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( FFI -> isDeadObjectIndex ( i ) ) continue ; Offset += FFI -> getObjectSize ( i ) ; unsigned Align = FFI -> getObjectAlignment ( i ) ; Offset = ( Offset + Align - 1 ) / Align * Align ; } return ( unsigned ) Offset ; } </s>

Estimate and return the size of the stack frame .


<s> DecodeStatus AVRDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CStream ) const { uint32_t Insn ; DecodeStatus Result ; { Result = readInstruction16 ( Bytes , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( getDecoderTable ( Size ) , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) return Result ; } { Result = readInstruction32 ( Bytes , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( getDecoderTable ( Size ) , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { return Result ; } return MCDisassembler :: Fail ; } } </s>

Returns the disassembly of a single instruction .


<s> bool sh_loads_bankedreg_p ( rtx insn ) { if ( GET_CODE ( PATTERN ( insn ) ) == SET ) { rtx op = SET_DEST ( PATTERN ( insn ) ) ; if ( REG_P ( op ) && BANKED_REGISTER_P ( REGNO ( op ) ) ) return true ; } return false ; } </s>

Return true iff INSN loads a banked register .


<s> static SDValue getTargetNode ( ConstantPoolSDNode * N , SDLoc DL , EVT Ty , SelectionDAG & DAG , unsigned Flags ) { return DAG . getTargetConstantPool ( N -> getConstVal ( ) , Ty , N -> getAlignment ( ) , N -> getOffset ( ) , Flags ) ; } </s>

Retrieve the target node this edge connects to .


<s>
MachineBasicBlock
::
iterator
AVRFrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
)
const
{
const
AVRSubtarget
&
STI
=
MF
.
getSubtarget
<
AVRSubtarget
>
(
)
;
const
TargetFrameLowering
&
TFI
=
*
STI
.
getFrameLowering
(
)
;
const
AVRInstrInfo
&
TII
=
*
STI
.
getInstrInfo
(
)
;
if
(
TFI
.
hasReservedCallFrame
(
MF
)
)
{
fixStackStores
(
MBB
,
MI
,
TII
,
false
)
;
return
MBB
.
erase
(
MI
)
;
}
DebugLoc
DL
=
MI
->
getDebugLoc
(
)
;
unsigned
int
Opcode
=
MI
->
getOpcode
(
)
;
int
Amount
=
MI
->
getOperand
(
0
)
.
getImm
(
)
;
if
(
Amount
!=
0
)
{
assert
(
TFI
.
getStackAlignment
(
)
==
1
&&
"Unsupported stack alignment"
)
;
if
(
Opcode
==
TII
.
getCallFrameSetupOpcode
(
)
)
{
fixStackStores
(
MBB
,
MI
,
TII
,
true
)
;
}
else
{
assert
(
Opcode
==
TII
.
getCallFrameDestroyOpcode
(
)
)
;
unsigned
addOpcode
;
if
(
isUInt
<
6
>
(
Amount
)
)
{
addOpcode
=
AVR
::
ADIWRdK
;
}
else
{
addOpcode
=
AVR
::
SUBIWRdK
;
Amount
=
Amount
;
}
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
SPREAD
)
,
AVR
::
R31R30
)
.
addReg
(
AVR
::
SP
)
;
MachineInstr
*
New
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
addOpcode
)
,
AVR
::
R31R30
)
.
addReg
(
AVR
::
R31R30
,
RegState
::
Kill
)
.
addImm
(
Amount
)
;
New
->
getOperand
(
3
)
.
setIsDead
(
)
;
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
SPWRITE
)
,
AVR
::
SP
)
.
addReg
(
AVR
::
R31R30
,
RegState
::
Kill
)
;
}
}
return
MBB
.
erase
(
MI
)
;
}
</s>


<s> virtual const DataLayout * getDataLayout ( ) const { return & Layout ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> MCSection * LanaiTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , unsigned & Align ) const { if ( isConstantInSmallSection ( DL , C ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: getSectionForConstant ( DL , Kind , C , Align ) ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> static bool v850_legitimate_address_p ( machine_mode mode , rtx x , bool strict_p , addr_space_t as ATTRIBUTE_UNUSED ) { gcc_assert ( ADDR_SPACE_GENERIC_P ( as ) ) ; if ( v850_rtx_ok_for_base_p ( x , strict_p ) ) return true ; if ( CONSTANT_ADDRESS_P ( x ) && ( mode == QImode || INTVAL ( x ) % 2 == 0 ) && ( GET_MODE_SIZE ( mode ) <= 4 || INTVAL ( x ) % 4 == 0 ) ) return true ; if ( GET_CODE ( x ) == LO_SUM && REG_P ( XEXP ( x , 0 ) ) && v850_reg_ok_for_base_p ( XEXP ( x , 0 ) , strict_p ) && CONSTANT_P ( XEXP ( x , 1 ) ) && ( ! CONST_INT_P ( XEXP ( x , 1 ) ) || ( ( mode == QImode || INTVAL ( XEXP ( x , 1 ) ) % 2 == 0 ) && constraint_satisfied_p ( XEXP ( x , 1 ) , CONSTRAINT_K ) ) ) && GET_MODE_SIZE ( mode ) <= GET_MODE_SIZE ( word_mode ) ) return true ; if ( special_symbolref_operand ( x , mode ) && ( GET_MODE_SIZE ( mode ) <= GET_MODE_SIZE ( word_mode ) ) ) return true ; if ( GET_CODE ( x ) == PLUS && v850_rtx_ok_for_base_p ( XEXP ( x , 0 ) , strict_p ) && constraint_satisfied_p ( XEXP ( x , 1 ) , CONSTRAINT_K ) && ( ( mode == QImode || INTVAL ( XEXP ( x , 1 ) ) % 2 == 0 ) && CONST_OK_FOR_K ( INTVAL ( XEXP ( x , 1 ) ) + ( GET_MODE_NUNITS ( mode ) * UNITS_PER_WORD ) ) ) ) return true ; return false ; } </s>


<s> bool ARMAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AFI = MF . getInfo < ARMFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; Subtarget = & MF . getSubtarget < ARMSubtarget > ( ) ; SetupMachineFunction ( MF ) ; const Function * F = MF . getFunction ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; unsigned OptimizationGoal ; if ( F -> hasFnAttribute ( Attribute :: OptimizeNone ) ) OptimizationGoal = 6 ; else if ( F -> optForMinSize ( ) ) OptimizationGoal = 4 ; else if ( F -> optForSize ( ) ) OptimizationGoal = 3 ; else if ( TM . getOptLevel ( ) == CodeGenOpt :: Aggressive ) OptimizationGoal = 2 ; else if ( TM . getOptLevel ( ) > CodeGenOpt :: None ) OptimizationGoal = 1 ; else OptimizationGoal = 5 ; if ( OptimizationGoals == - 1 ) OptimizationGoals = OptimizationGoal ; else if ( OptimizationGoals != ( int ) OptimizationGoal ) OptimizationGoals = 0 ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = F -> hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer -> EmitCOFFSymbolType ( Type ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; if ( ! ThumbIndirectPads . empty ( ) ) { OutStreamer -> EmitAssemblerFlag ( MCAF_Code16 ) ; EmitAlignment ( 1 ) ; for ( unsigned i = 0 , e = ThumbIndirectPads . size ( ) ; i < e ; i ++ ) { OutStreamer -> EmitLabel ( ThumbIndirectPads [ i ] . second ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( ARM :: tBX ) . addReg ( ThumbIndirectPads [ i ] . first ) . addImm ( ARMCC :: AL ) . addReg ( 0 ) ) ; } ThumbIndirectPads . clear ( ) ; } return false ; } </s>


<s> void aarch64_gen_atomic_ldop ( enum rtx_code code , rtx out_data , rtx out_result , rtx mem , rtx value , rtx model_rtx ) { machine_mode mode = GET_MODE ( mem ) ; machine_mode wmode = ( mode == DImode ? DImode : SImode ) ; const bool short_mode = ( mode < SImode ) ; aarch64_atomic_load_op_code ldop_code ; rtx src ; rtx x ; if ( out_data ) out_data = gen_lowpart ( mode , out_data ) ; if ( out_result ) out_result = gen_lowpart ( mode , out_result ) ; if ( ! register_operand ( value , mode ) || code == AND || code == MINUS ) { src = out_result ? out_result : out_data ; emit_move_insn ( src , gen_lowpart ( mode , value ) ) ; } else src = value ; gcc_assert ( register_operand ( src , mode ) ) ; switch ( code ) { case SET : aarch64_emit_atomic_swap ( mode , out_data , src , mem , model_rtx ) ; return ; case MINUS : { rtx neg_src ; if ( short_mode ) src = gen_lowpart ( wmode , src ) ; neg_src = gen_rtx_NEG ( wmode , src ) ; emit_insn ( gen_rtx_SET ( src , neg_src ) ) ; if ( short_mode ) src = gen_lowpart ( mode , src ) ; } case PLUS : ldop_code = AARCH64_LDOP_PLUS ; break ; case IOR : ldop_code = AARCH64_LDOP_OR ; break ; case XOR : ldop_code = AARCH64_LDOP_XOR ; break ; case AND : { rtx not_src ; if ( short_mode ) src = gen_lowpart ( wmode , src ) ; not_src = gen_rtx_NOT ( wmode , src ) ; emit_insn ( gen_rtx_SET ( src , not_src ) ) ; if ( short_mode ) src = gen_lowpart ( mode , src ) ; } ldop_code = AARCH64_LDOP_BIC ; break ; default : gcc_unreachable ( ) ; } aarch64_emit_atomic_load_op ( ldop_code , mode , out_data , src , mem , model_rtx ) ; if ( ! out_result ) return ; if ( short_mode ) { src = gen_lowpart ( wmode , src ) ; out_data = gen_lowpart ( wmode , out_data ) ; out_result = gen_lowpart ( wmode , out_result ) ; } x = NULL_RTX ; switch ( code ) { case MINUS : case PLUS : x = gen_rtx_PLUS ( wmode , out_data , src ) ; break ; case IOR : x = gen_rtx_IOR ( wmode , out_data , src ) ; break ; case XOR : x = gen_rtx_XOR ( wmode , out_data , src ) ; break ; case AND : aarch64_emit_bic ( wmode , out_result , out_data , src , 0 ) ; return ; default : gcc_unreachable ( ) ; } emit_set_insn ( out_result , x ) ; return ; } </s>

Emit an atomic load+operate . CODE is the operation . OUT_DATA is the location to store the data read from memory . OUT_RESULT is the location to store the result of the operation . MEM is the memory location to read and modify . MODEL_RTX is the memory ordering to use . VALUE is the second operand for the operation . Either OUT_DATA or OUT_RESULT , but not both , can be NULL .


<s> bool MipsSEInstrInfo :: isReallyTriviallyReMaterializable ( const MachineInstr & MI , AAResults * AA ) const { switch ( MI . getOpcode ( ) ) { case Mips :: CheriBoundedStackPseudoImm : assert ( MI . getOperand ( 3 ) . isImm ( ) ) ; return true ; case Mips :: CIncOffsetImm : case Mips :: CMove : case Mips :: COPY : return MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 1 ) . getReg ( ) == Mips :: CNULL ; case Mips :: LUi64 : { auto Flags = MI . getOperand ( 1 ) . getTargetFlags ( ) ; if ( Flags == MipsII :: MO_CAPTABLE_OFF_HI ) { return true ; } return false ; } default : return false ; } } </s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> StringRef SIRegisterInfo :: getRegAsmName ( unsigned Reg ) const { switch ( Reg ) { case AMDGPU :: FLAT_SCR : return "flat_scratch" ; case AMDGPU :: FLAT_SCR_LO : return "flat_scratch_lo" ; case AMDGPU :: FLAT_SCR_HI : return "flat_scratch_hi" ; default : break ; } const TargetRegisterClass * RC = getMinimalPhysRegClass ( Reg ) ; unsigned Size = getRegSizeInBits ( * RC ) ; unsigned AltName = AMDGPU :: NoRegAltName ; switch ( Size ) { case 32 : AltName = AMDGPU :: Reg32 ; break ; case 64 : AltName = AMDGPU :: Reg64 ; break ; case 96 : AltName = AMDGPU :: Reg96 ; break ; case 128 : AltName = AMDGPU :: Reg128 ; break ; case 160 : AltName = AMDGPU :: Reg160 ; break ; case 256 : AltName = AMDGPU :: Reg256 ; break ; case 512 : AltName = AMDGPU :: Reg512 ; break ; case 1024 : AltName = AMDGPU :: Reg1024 ; break ; } return AMDGPUInstPrinter :: getRegisterName ( Reg , AltName ) ; } </s>


<s> bool X86CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto DL = MF . getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { if ( Arg . hasAttribute ( Attribute :: ByVal ) || Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: Nest ) ) return false ; ArgInfo OrigArg ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArg , Idx + AttributeList :: FirstArgIndex , DL , F ) ; if ( ! splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs ) { MIRBuilder . buildMerge ( VRegs [ Idx ] , Regs ) ; } ) ) return false ; Idx ++ ; } MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; FormalArgHandler Handler ( MIRBuilder , MRI , CC_X86 ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>


<s> const MipsMCExpr * MipsMCExpr :: Create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { return new ( Ctx ) MipsMCExpr ( Kind , Expr ) ; } </s>


<s> const MCS51InstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> bool GCNPassConfig :: addPreISel ( ) { AMDGPUPassConfig :: addPreISel ( ) ; if ( TM -> getOptLevel ( ) > CodeGenOpt :: None ) addPass ( createAMDGPULateCodeGenPreparePass ( ) ) ; if ( isPassEnabled ( EnableAtomicOptimizations , CodeGenOpt :: Less ) ) { addPass ( createAMDGPUAtomicOptimizerPass ( ) ) ; } if ( TM -> getOptLevel ( ) > CodeGenOpt :: None ) addPass ( createSinkingPass ( ) ) ; addPass ( & AMDGPUUnifyDivergentExitNodesID ) ; if ( ! LateCFGStructurize ) { if ( EnableStructurizerWorkarounds ) { addPass ( createFixIrreduciblePass ( ) ) ; addPass ( createUnifyLoopExitsPass ( ) ) ; } addPass ( createStructurizeCFGPass ( false ) ) ; } addPass ( createAMDGPUAnnotateUniformValues ( ) ) ; if ( ! LateCFGStructurize ) { addPass ( createSIAnnotateControlFlowPass ( ) ) ; } addPass ( createLCSSAPass ( ) ) ; if ( TM -> getOptLevel ( ) > CodeGenOpt :: Less ) addPass ( & AMDGPUPerfHintAnalysisID ) ; return false ; } </s>

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU SI AMDGPU


<s> const AAPTargetMachine & getTargetMachine ( ) { return static_cast < const AAPTargetMachine & > ( TM ) ; } </s>

Return the target machine ( if available ) .


"unimplemented opcode in encodeInstruction()"

Encode the given Inst to bytes and append to CB .


<s> bool HexagonTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { LSBaseSDNode * LSN = dyn_cast < LSBaseSDNode > ( N ) ; if ( ! LSN ) return false ; EVT VT = LSN -> getMemoryVT ( ) ; if ( ! VT . isSimple ( ) ) return false ; bool IsLegalType = VT == MVT :: i8 || VT == MVT :: i16 || VT == MVT :: i32 || VT == MVT :: i64 || VT == MVT :: f32 || VT == MVT :: f64 || VT == MVT :: v2i16 || VT == MVT :: v2i32 || VT == MVT :: v4i8 || VT == MVT :: v4i16 || VT == MVT :: v8i8 || Subtarget . isHVXVectorType ( VT . getSimpleVT ( ) ) ; if ( ! IsLegalType ) return false ; if ( Op -> getOpcode ( ) != ISD :: ADD ) return false ; Base = Op -> getOperand ( 0 ) ; Offset = Op -> getOperand ( 1 ) ; if ( ! isa < ConstantSDNode > ( Offset . getNode ( ) ) ) return false ; AM = ISD :: POST_INC ; int32_t V = cast < ConstantSDNode > ( Offset . getNode ( ) ) -> getSExtValue ( ) ; return Subtarget . getInstrInfo ( ) -> isValidAutoIncImm ( VT , V ) ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .


<s> std :: pair < unsigned , const TargetRegisterClass * > RV16KTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , & RV16K :: GPRRegClass ) ; default : break ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> Liveness ( MachineRegisterInfo & mri , const DataFlowGraph & g ) : DFG ( g ) , TRI ( g . getTRI ( ) ) , PRI ( g . getPRI ( ) ) , MDT ( g . getDT ( ) ) , MDF ( g . getDF ( ) ) , MRI ( mri ) , LiveMap ( g . getPRI ( ) ) , Empty ( ) , NoRegs ( g . getPRI ( ) ) , Trace ( false ) { } </s>

During our initial pass over the program , we determine that things are either alive or maybe alive . More ...


<s> inline bool isAdd ( const MCInstrDesc & MCInstD ) { if ( isSPUInst ( MCInstD ) ) return getSlotOpCode ( MCInstD ) == spuADD ; if ( isVPUInst ( MCInstD ) ) return getSlotOpCode ( MCInstD ) == vpuADD ; return false ; } </s>

Return true if the instruction is an add instruction .


<s> const char * HexagonTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( HexagonISD :: NodeType ) Opcode ) { case HexagonISD :: ALLOCA : return "HexagonISD::ALLOCA" ; case HexagonISD :: AT_GOT : return "HexagonISD::AT_GOT" ; case HexagonISD :: AT_PCREL : return "HexagonISD::AT_PCREL" ; case HexagonISD :: BARRIER : return "HexagonISD::BARRIER" ; case HexagonISD :: CALL : return "HexagonISD::CALL" ; case HexagonISD :: CALLnr : return "HexagonISD::CALLnr" ; case HexagonISD :: CALLR : return "HexagonISD::CALLR" ; case HexagonISD :: COMBINE : return "HexagonISD::COMBINE" ; case HexagonISD :: CONST32_GP : return "HexagonISD::CONST32_GP" ; case HexagonISD :: CONST32 : return "HexagonISD::CONST32" ; case HexagonISD :: CP : return "HexagonISD::CP" ; case HexagonISD :: DCFETCH : return "HexagonISD::DCFETCH" ; case HexagonISD :: EH_RETURN : return "HexagonISD::EH_RETURN" ; case HexagonISD :: EXTRACTU : return "HexagonISD::EXTRACTU" ; case HexagonISD :: EXTRACTURP : return "HexagonISD::EXTRACTURP" ; case HexagonISD :: INSERT : return "HexagonISD::INSERT" ; case HexagonISD :: INSERTRP : return "HexagonISD::INSERTRP" ; case HexagonISD :: JT : return "HexagonISD::JT" ; case HexagonISD :: PACKHL : return "HexagonISD::PACKHL" ; case HexagonISD :: RET_FLAG : return "HexagonISD::RET_FLAG" ; case HexagonISD :: SHUFFEB : return "HexagonISD::SHUFFEB" ; case HexagonISD :: SHUFFEH : return "HexagonISD::SHUFFEH" ; case HexagonISD :: SHUFFOB : return "HexagonISD::SHUFFOB" ; case HexagonISD :: SHUFFOH : return "HexagonISD::SHUFFOH" ; case HexagonISD :: TC_RETURN : return "HexagonISD::TC_RETURN" ; case HexagonISD :: VCMPBEQ : return "HexagonISD::VCMPBEQ" ; case HexagonISD :: VCMPBGT : return "HexagonISD::VCMPBGT" ; case HexagonISD :: VCMPBGTU : return "HexagonISD::VCMPBGTU" ; case HexagonISD :: VCMPHEQ : return "HexagonISD::VCMPHEQ" ; case HexagonISD :: VCMPHGT : return "HexagonISD::VCMPHGT" ; case HexagonISD :: VCMPHGTU : return "HexagonISD::VCMPHGTU" ; case HexagonISD :: VCMPWEQ : return "HexagonISD::VCMPWEQ" ; case HexagonISD :: VCMPWGT : return "HexagonISD::VCMPWGT" ; case HexagonISD :: VCMPWGTU : return "HexagonISD::VCMPWGTU" ; case HexagonISD :: VCOMBINE : return "HexagonISD::VCOMBINE" ; case HexagonISD :: VPACK : return "HexagonISD::VPACK" ; case HexagonISD :: VSHLH : return "HexagonISD::VSHLH" ; case HexagonISD :: VSHLW : return "HexagonISD::VSHLW" ; case HexagonISD :: VSPLATB : return "HexagonISD::VSPLTB" ; case HexagonISD :: VSPLATH : return "HexagonISD::VSPLATH" ; case HexagonISD :: VSRAH : return "HexagonISD::VSRAH" ; case HexagonISD :: VSRAW : return "HexagonISD::VSRAW" ; case HexagonISD :: VSRLH : return "HexagonISD::VSRLH" ; case HexagonISD :: VSRLW : return "HexagonISD::VSRLW" ; case HexagonISD :: VSXTBH : return "HexagonISD::VSXTBH" ; case HexagonISD :: VSXTBW : return "HexagonISD::VSXTBW" ; case HexagonISD :: READCYCLE : return "HexagonISD::READCYCLE" ; case HexagonISD :: OP_END : break ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

Hexagon Hexagon HexagonISD::NodeType HexagonISD::ALLOCA "HexagonISD::ALLOCA" HexagonISD::AT_GOT "HexagonISD::AT_GOT" HexagonISD::AT_PCREL "HexagonISD::AT_PCREL" HexagonISD::BARRIER "HexagonISD::BARRIER" HexagonISD::CALL "HexagonISD::CALL" HexagonISD::CALLnr "HexagonISD::CALLnr" HexagonISD::CALLR "HexagonISD::CALLR" HexagonISD::COMBINE "HexagonISD::COMBINE" HexagonISD::CONST32_GP "HexagonISD::CONST32_GP" HexagonISD::CONST32 "HexagonISD::CONST32" HexagonISD::CP "HexagonISD::CP" HexagonISD::DCFETCH "HexagonISD::DCFETCH" HexagonISD::EH_RETURN "HexagonISD::EH_RETURN" HexagonISD::EXTRACTU "HexagonISD::EXTRACTU" HexagonISD::EXTRACTURP "HexagonISD::EXTRACTURP" HexagonISD::INSERT "HexagonISD::INSERT" HexagonISD::INSERTRP "HexagonISD::INSERTRP" HexagonISD::JT "HexagonISD::JT" HexagonISD::PACKHL "HexagonISD::PACKHL" HexagonISD::RET_FLAG "HexagonISD::RET_FLAG" HexagonISD::SHUFFEB "HexagonISD::SHUFFEB" HexagonISD::SHUFFEH "HexagonISD::SHUFFEH" HexagonISD::SHUFFOB "HexagonISD::SHUFFOB" HexagonISD::SHUFFOH "HexagonISD::SHUFFOH" HexagonISD::TC_RETURN "HexagonISD::TC_RETURN" HexagonISD::VCMPBEQ "HexagonISD::VCMPBEQ" HexagonISD::VCMPBGT "HexagonISD::VCMPBGT" HexagonISD::VCMPBGTU "HexagonISD::VCMPBGTU" HexagonISD::VCMPHEQ "HexagonISD::VCMPHEQ" HexagonISD::VCMPHGT "HexagonISD::VCMPHGT" HexagonISD::VCMPHGTU "HexagonISD::VCMPHGTU" HexagonISD::VCMPWEQ "HexagonISD::VCMPWEQ" HexagonISD::VCMPWGT "HexagonISD::VCMPWGT" HexagonISD::VCMPWGTU "HexagonISD::VCMPWGTU" HexagonISD::VCOMBINE "HexagonISD::VCOMBINE" HexagonISD::VPACK "HexagonISD::VPACK" HexagonISD::VSHLH "HexagonISD::VSHLH" HexagonISD::VSHLW "HexagonISD::VSHLW" HexagonISD::VSPLATB "HexagonISD::VSPLTB" HexagonISD::VSPLATH "HexagonISD::VSPLATH" HexagonISD::VSRAH "HexagonISD::VSRAH" HexagonISD::VSRAW "HexagonISD::VSRAW" HexagonISD::VSRLH "HexagonISD::VSRLH" HexagonISD::VSRLW "HexagonISD::VSRLW" HexagonISD::VSXTBH "HexagonISD::VSXTBH" HexagonISD::VSXTBW "HexagonISD::VSXTBW" HexagonISD::READCYCLE "HexagonISD::READCYCLE" HexagonISD::OP_END


<s> bool doFinalization ( Module & M ) override { Result . reset ( ) ; return false ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == & ARM :: GPRRegClass || RC == & ARM :: tGPRRegClass || RC == & ARM :: tcGPRRegClass || RC == & ARM :: rGPRRegClass || RC == & ARM :: GPRnopcRegClass ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2LDRi12 ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } if ( ARM :: GPRPairRegClass . hasSubClassEq ( RC ) ) { if ( TargetRegisterInfo :: isVirtualRegister ( DestReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( DestReg , & ARM :: GPRPair_with_gsub_1_in_rGPRRegClass ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( ARM :: t2LDRDi8 ) ) ; AddDReg ( MIB , DestReg , ARM :: gsub_0 , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , ARM :: gsub_1 , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ; AddDefaultPred ( MIB ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; } ARMBaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC , TRI ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


"too many opcodes for __aeabi_unwind_cpp_pr0"

Finalize the unwind opcode sequence for emitBytes ( )


"should only be called once per function"

runOnSCC - This method should be implemented by the subclass to perform whatever action is necessary for the specified SCC .


<s>
SDValue
MSP430TargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
if
(
CallConv
==
CallingConv
::
MSP430_INTR
&&
!
Outs
.
empty
(
)
)
report_fatal_error
(
"ISRs cannot return any value"
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_MSP430
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
if
(
RVLocs
[
i
]
.
isRegLoc
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
unsigned
Opc
=
(
CallConv
==
CallingConv
::
MSP430_INTR
MSP430ISD
::
RETI_FLAG
:
MSP430ISD
::
RET_FLAG
)
;
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
Opc
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
return
DAG
.
getNode
(
Opc
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void mn10300_split_cbranch ( machine_mode cmp_mode , rtx cmp_op , rtx label_ref ) { rtx flags , x ; flags = gen_rtx_REG ( cmp_mode , CC_REG ) ; x = gen_rtx_COMPARE ( cmp_mode , XEXP ( cmp_op , 0 ) , XEXP ( cmp_op , 1 ) ) ; x = gen_rtx_SET ( VOIDmode , flags , x ) ; emit_insn ( x ) ; x = gen_rtx_fmt_ee ( GET_CODE ( cmp_op ) , VOIDmode , flags , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , label_ref , pc_rtx ) ; x = gen_rtx_SET ( VOIDmode , pc_rtx , x ) ; emit_jump_insn ( x ) ; } </s>

A helper function for splitting cbranch patterns after reload .


<s> static MCAsmInfo * createMCAsmInfo ( const Target & T , StringRef TT ) { Triple TheTriple ( TT ) ; switch ( TheTriple . getOS ( ) ) { case Triple :: Darwin : return new X86MCAsmInfoDarwin ( TheTriple ) ; case Triple :: MinGW32 : case Triple :: MinGW64 : case Triple :: Cygwin : case Triple :: Win32 : return new X86MCAsmInfoCOFF ( TheTriple ) ; default : return new X86ELFMCAsmInfo ( TheTriple ) ; } } </s>

createMCAsmInfo - Create a MCAsmInfo implementation for the specified target triple .


<s> static const char * cond_string ( enum rtx_code code ) { switch ( code ) { case NE : return "ne" ; case EQ : return "eq" ; case GE : if ( cc_prev_status . flags & CC_OVERFLOW_UNUSABLE ) return "pl" ; else return "ge" ; case LT : if ( cc_prev_status . flags & CC_OVERFLOW_UNUSABLE ) return "mi" ; else return "lt" ; case GEU : return "sh" ; case LTU : return "lo" ; default : gcc_unreachable ( ) ; } } </s>

Return assembly language string which identifies a comparison type .

avr "ne" "eq" "pl" "ge" "mi" "lt" "sh" "lo"


<s> bool ARCOptAddrMode :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) || KILL_PASS ( ) ) return false ; if ( DUMP_BEFORE ( ) ) MF . dump ( ) ; if ( VIEW_BEFORE ( ) ) MF . viewCFG ( ) ; AST = & MF . getSubtarget < ARCSubtarget > ( ) ; AII = AST -> getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; bool Changed = false ; for ( auto & MBB : MF ) Changed |= processBasicBlock ( MBB ) ; if ( DUMP_AFTER ( ) ) MF . dump ( ) ; if ( VIEW_AFTER ( ) ) MF . viewCFG ( ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> static char * to_host_file_spec ( char * filespec ) { if ( strchr ( filespec , ']' ) || strchr ( filespec , ':' ) ) return filespec ; else { strcpy ( filename_buff , filespec ) ; decc$to_vms ( filespec , translate_unix , 1 , 1 ) ; strcpy ( new_host_filespec , filename_buff ) ; return new_host_filespec ; } return filespec ; } </s>

Translate a Unix syntax file specification FILESPEC into VMS syntax . If indicators of VMS syntax found , return input string . Return a pointer to a static buffer .


<s> static bool arm_const_not_ok_for_debug_p ( rtx p ) { tree decl_op0 = NULL ; tree decl_op1 = NULL ; if ( GET_CODE ( p ) == UNSPEC ) return true ; if ( GET_CODE ( p ) == MINUS ) { if ( GET_CODE ( XEXP ( p , 1 ) ) == SYMBOL_REF ) { decl_op1 = SYMBOL_REF_DECL ( XEXP ( p , 1 ) ) ; if ( decl_op1 && GET_CODE ( XEXP ( p , 0 ) ) == SYMBOL_REF && ( decl_op0 = SYMBOL_REF_DECL ( XEXP ( p , 0 ) ) ) ) { if ( ( VAR_P ( decl_op1 ) || TREE_CODE ( decl_op1 ) == CONST_DECL ) && ( VAR_P ( decl_op0 ) || TREE_CODE ( decl_op0 ) == CONST_DECL ) ) return ( get_variable_section ( decl_op1 , false ) != get_variable_section ( decl_op0 , false ) ) ; if ( TREE_CODE ( decl_op1 ) == LABEL_DECL && TREE_CODE ( decl_op0 ) == LABEL_DECL ) return ( DECL_CONTEXT ( decl_op1 ) != DECL_CONTEXT ( decl_op0 ) ) ; } return true ; } } return false ; } </s>

This is a temporary fix for PR60655 . Ideally we need to handle most of these cases in the generic part but currently we reject minus ( .. ) ( sym_ref ) . We try to ameliorate the case with minus ( sym_ref1 ) ( sym_ref2 ) where they are in the same section .


<s> bool AMDGPULowerIntrinsics :: makeLIDRangeMetadata ( Function & F ) const { auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; const TargetMachine & TM = TPC -> getTM < TargetMachine > ( ) ; bool Changed = false ; for ( auto * U : F . users ( ) ) { auto * CI = dyn_cast < CallInst > ( U ) ; if ( ! CI ) continue ; Changed |= AMDGPUCommonSubtarget :: get ( TM , F ) . makeLIDRangeMetadata ( CI ) ; } return Changed ; } </s>

Creates value range metadata on an workitemid . * intrinsic call or load .


<s> void clear ( ) { memset ( ScoreLBs , 0 , sizeof ( ScoreLBs ) ) ; memset ( ScoreUBs , 0 , sizeof ( ScoreUBs ) ) ; PendingEvents = 0 ; memset ( MixedPendingEvents , 0 , sizeof ( MixedPendingEvents ) ) ; for ( auto T : inst_counter_types ( ) ) memset ( VgprScores [ T ] , 0 , sizeof ( VgprScores [ T ] ) ) ; memset ( SgprScores , 0 , sizeof ( SgprScores ) ) ; } </s>


<s> static bool msp430_var_in_low_mem ( tree decl ) { gcc_assert ( VAR_P ( decl ) ) ; if ( has_attr ( ATTR_UPPER , decl ) || has_attr ( ATTR_EITHER , decl ) || has_attr ( ATTR_PERSIST , decl ) || ( ! has_attr ( ATTR_LOWER , decl ) && ! has_attr ( ATTR_NOINIT , decl ) && ( has_attr ( "section" , decl ) || msp430_data_region == MSP430_REGION_UPPER || msp430_data_region == MSP430_REGION_EITHER || msp430_data_region == MSP430_REGION_ANY ) ) ) return false ; return true ; } </s>

Given a non-automatic VAR_DECL which can possibly have a section , return true if the variable will definitely be placed in the lower memory region ( below address 0x10000 ) .


<s> const uint32_t * SIRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { switch ( CC ) { case CallingConv :: C : case CallingConv :: Fast : case CallingConv :: Cold : return ST . hasGFX90AInsts ( ) ? CSR_AMDGPU_GFX90AInsts_RegMask : CSR_AMDGPU_RegMask ; case CallingConv :: AMDGPU_Gfx : return ST . hasGFX90AInsts ( ) ? CSR_AMDGPU_SI_Gfx_GFX90AInsts_RegMask : CSR_AMDGPU_SI_Gfx_RegMask ; default : return nullptr ; } } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool expand_move ( rtx * operands , machine_mode mode ) { rtx op = operands [ 1 ] ; if ( ( TARGET_ID_SHARED_LIBRARY || TARGET_FDPIC ) && SYMBOLIC_CONST ( op ) ) emit_pic_move ( operands , mode ) ; else if ( mode == SImode && GET_CODE ( op ) == CONST && GET_CODE ( XEXP ( op , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( op , 0 ) , 0 ) ) == SYMBOL_REF && ! targetm . legitimate_constant_p ( mode , op ) ) { rtx dest = operands [ 0 ] ; rtx op0 , op1 ; gcc_assert ( ! reload_in_progress && ! reload_completed ) ; op = XEXP ( op , 0 ) ; op0 = force_reg ( mode , XEXP ( op , 0 ) ) ; op1 = XEXP ( op , 1 ) ; if ( ! insn_data [ CODE_FOR_addsi3 ] . operand [ 2 ] . predicate ( op1 , mode ) ) op1 = force_reg ( mode , op1 ) ; if ( GET_CODE ( dest ) == MEM ) dest = gen_reg_rtx ( mode ) ; emit_insn ( gen_addsi3 ( dest , op0 , op1 ) ) ; if ( dest == operands [ 0 ] ) return true ; operands [ 1 ] = dest ; } else if ( ( reload_in_progress | reload_completed ) == 0 && GET_CODE ( operands [ 0 ] ) == MEM && GET_CODE ( operands [ 1 ] ) != REG ) operands [ 1 ] = force_reg ( mode , operands [ 1 ] ) ; return false ; } </s>

Expand a move operation in mode MODE . The operands are in OPERANDS .


<s> string str ( void ) const { stringbuf buf ; char kind [ ] = { '-' , 'u' , 'd' , 'x' } ; for ( unsigned long i = 0 ; i < uses . size ( ) ; i ++ ) { int x = 0 ; if ( uses . test ( i ) ) x += 1 ; if ( defs . test ( i ) ) x += 2 ; buf . sputc ( kind [ x ] ) ; } return buf . str ( ) ; } </s>

Return the twine contents as a std : :string .


<s> static bool timode_scalar_to_vector_candidate_p ( rtx_insn * insn ) { rtx def_set = pseudo_reg_set ( insn ) ; if ( ! def_set ) return false ; rtx src = SET_SRC ( def_set ) ; rtx dst = SET_DEST ( def_set ) ; if ( GET_MODE ( dst ) != TImode ) return false ; if ( MEM_P ( dst ) ) { if ( misaligned_operand ( dst , TImode ) && ! TARGET_SSE_UNALIGNED_STORE_OPTIMAL ) return false ; switch ( GET_CODE ( src ) ) { default : return false ; case REG : case CONST_WIDE_INT : return true ; case CONST_INT : return standard_sse_constant_p ( src , TImode ) ; } } else if ( MEM_P ( src ) ) { return ( REG_P ( dst ) && ( ! misaligned_operand ( src , TImode ) || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL ) ) ; } return false ; } </s>

The TImode version of scalar_to_vector_candidate_p .


<s> static int loongarch_zero_extend_cost ( rtx op ) { if ( MEM_P ( op ) ) return 0 ; return COSTS_N_INSNS ( 1 ) ; } </s>

Return the cost of zero-extending OP to mode MODE , not including the cost of OP itself .


<s> static rtx get_branch_target ( rtx_insn * branch ) { if ( JUMP_P ( branch ) ) { rtx set , src ; if ( GET_CODE ( PATTERN ( branch ) ) == RETURN ) return gen_rtx_REG ( SImode , LINK_REGISTER_REGNUM ) ; if ( extract_asm_operands ( PATTERN ( branch ) ) != NULL ) return NULL ; set = single_set ( branch ) ; src = SET_SRC ( set ) ; if ( GET_CODE ( SET_DEST ( set ) ) != PC ) abort ( ) ; if ( GET_CODE ( src ) == IF_THEN_ELSE ) { rtx lab = 0 ; rtx note = find_reg_note ( branch , REG_BR_PROB , 0 ) ; if ( note ) { int prob = profile_probability :: from_reg_br_prob_note ( XINT ( note , 0 ) ) . to_reg_br_prob_base ( ) ; if ( prob > ( REG_BR_PROB_BASE * 6 / 10 ) && GET_CODE ( XEXP ( src , 1 ) ) != PC ) lab = XEXP ( src , 1 ) ; else if ( prob < ( REG_BR_PROB_BASE * 4 / 10 ) && GET_CODE ( XEXP ( src , 2 ) ) != PC ) lab = XEXP ( src , 2 ) ; } if ( lab ) { if ( GET_CODE ( lab ) == RETURN ) return gen_rtx_REG ( SImode , LINK_REGISTER_REGNUM ) ; return lab ; } return 0 ; } return src ; } else if ( CALL_P ( branch ) ) { rtx call ; if ( GET_CODE ( PATTERN ( branch ) ) != PARALLEL ) abort ( ) ; call = XVECEXP ( PATTERN ( branch ) , 0 , 0 ) ; if ( GET_CODE ( call ) == SET ) call = SET_SRC ( call ) ; if ( GET_CODE ( call ) != CALL ) abort ( ) ; return XEXP ( XEXP ( call , 0 ) , 0 ) ; } return 0 ; } </s>

Returns 0 if we do n't want a hint for this branch . Otherwise return the rtx for the branch target .


"cannot return value in vector register because"

" altivec instructions are disabled, use -maltivec"

Handle the INIT_CUMULATIVE_ARGS macro . Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is 0 .


<s> char * mcore_output_call ( rtx operands [ ] , int index ) { static char buffer [ 20 ] ; rtx addr = operands [ index ] ; if ( REG_P ( addr ) ) { if ( TARGET_CG_DATA ) { gcc_assert ( mcore_current_function_name ) ; ASM_OUTPUT_CG_EDGE ( asm_out_file , mcore_current_function_name , "unknown" , 1 ) ; } sprintf ( buffer , "jsr\t%%%d" , index ) ; } else { if ( TARGET_CG_DATA ) { gcc_assert ( mcore_current_function_name ) ; gcc_assert ( GET_CODE ( addr ) == SYMBOL_REF ) ; ASM_OUTPUT_CG_EDGE ( asm_out_file , mcore_current_function_name , XSTR ( addr , 0 ) , 0 ) ; } sprintf ( buffer , "jbsr\t%%%d" , index ) ; } return buffer ; } </s>

Functions to output assembly code for a function call .


<s> static void nvptx_goacc_reduction_teardown ( gcall * call , offload_attrs * oa ) { gimple_stmt_iterator gsi = gsi_for_stmt ( call ) ; tree lhs = gimple_call_lhs ( call ) ; tree var = gimple_call_arg ( call , 2 ) ; int level = TREE_INT_CST_LOW ( gimple_call_arg ( call , 3 ) ) ; gimple_seq seq = NULL ; push_gimplify_context ( true ) ; if ( level == GOMP_DIM_WORKER || ( level == GOMP_DIM_VECTOR && oa -> vector_length > PTX_WARP_SIZE ) ) { tree offset = gimple_call_arg ( call , 5 ) ; tree call = nvptx_get_shared_red_addr ( TREE_TYPE ( var ) , offset , level == GOMP_DIM_VECTOR ) ; tree ptr = make_ssa_name ( TREE_TYPE ( call ) ) ; gimplify_assign ( ptr , call , & seq ) ; var = build_simple_mem_ref ( ptr ) ; TREE_THIS_VOLATILE ( var ) = 1 ; } if ( level != GOMP_DIM_GANG ) { tree ref_to_res = gimple_call_arg ( call , 1 ) ; if ( ! integer_zerop ( ref_to_res ) ) gimplify_assign ( build_simple_mem_ref ( ref_to_res ) , var , & seq ) ; } if ( lhs ) gimplify_assign ( lhs , var , & seq ) ; pop_gimplify_context ( NULL ) ; gsi_replace_with_seq ( & gsi , seq , true ) ; } </s>

NVPTX implementation of GOACC_REDUCTION_TEARDOWN .


<s> bool isImm ( ) const override { return Kind == IMMEDIATE ; } </s>


<s> void XtensaMCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { uint64_t Hex = getBinaryCodeForInstr ( MI , Fixups , STI ) ; support :: endian :: write < uint8_t > ( OS , ( Hex >> 0 ) & 0xff , llvm :: support :: little ) ; support :: endian :: write < uint8_t > ( OS , ( Hex >> 8 ) & 0xff , llvm :: support :: little ) ; if ( ! ( Hex & 8 ) ) support :: endian :: write < uint8_t > ( OS , ( Hex >> 16 ) & 0xff , llvm :: support :: little ) ; } </s>

Encode the given Inst to bytes and append to CB .


<s> const Cpu0RegisterInfo & Cpu0SEInstrInfo :: getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


Expand movmem , as if from a __builtin_memcpy . Return true if we succeed , otherwise return false .


<s> void NVPTXTargetMachine :: registerPassBuilderCallbacks ( PassBuilder & PB ) { PB . registerPipelineParsingCallback ( [ ] ( StringRef PassName , FunctionPassManager & PM , ArrayRef < PassBuilder :: PipelineElement > ) { if ( PassName == "nvvm-reflect" ) { PM . addPass ( NVVMReflectPass ( ) ) ; return true ; } if ( PassName == "nvvm-intr-range" ) { PM . addPass ( NVVMIntrRangePass ( ) ) ; return true ; } return false ; } ) ; PB . registerPipelineStartEPCallback ( [ this ] ( ModulePassManager & PM , OptimizationLevel Level ) { FunctionPassManager FPM ; FPM . addPass ( NVVMReflectPass ( Subtarget . getSmVersion ( ) ) ) ; PM . addPass ( createModuleToFunctionPassAdaptor ( std :: move ( FPM ) ) ) ; } ) ; } </s>

Invoke the PassBuilder callback registration .

NVPTX NVPTX "nvvm-reflect" "nvvm-intr-range"


<s> StackOffset ( const StackOffset & Other ) : Bytes ( Other . Bytes ) { } </s>


<s> bool ARMBaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; const ARMFrameLowering * TFI = getFrameLowering ( MF ) ; if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; if ( AFI -> isThumb1OnlyFunction ( ) ) return false ; if ( ! MRI -> canReserveReg ( getFramePointerReg ( MF . getSubtarget < ARMSubtarget > ( ) ) ) ) return false ; if ( TFI -> hasReservedCallFrame ( MF ) ) return true ; return MRI -> canReserveReg ( BasePtr ) ; } </s>

True if the stack can be realigned for the target .


<s> void sparc_emit_floatunsdi ( rtx * operands , machine_mode mode ) { rtx i0 , i1 , f0 , in , out ; out = operands [ 0 ] ; in = force_reg ( DImode , operands [ 1 ] ) ; rtx_code_label * neglab = gen_label_rtx ( ) ; rtx_code_label * donelab = gen_label_rtx ( ) ; i0 = gen_reg_rtx ( DImode ) ; i1 = gen_reg_rtx ( DImode ) ; f0 = gen_reg_rtx ( mode ) ; emit_cmp_and_jump_insns ( in , const0_rtx , LT , const0_rtx , DImode , 0 , neglab ) ; emit_insn ( gen_rtx_SET ( VOIDmode , out , gen_rtx_FLOAT ( mode , in ) ) ) ; emit_jump_insn ( gen_jump ( donelab ) ) ; emit_barrier ( ) ; emit_label ( neglab ) ; emit_insn ( gen_lshrdi3 ( i0 , in , const1_rtx ) ) ; emit_insn ( gen_anddi3 ( i1 , in , const1_rtx ) ) ; emit_insn ( gen_iordi3 ( i0 , i0 , i1 ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , f0 , gen_rtx_FLOAT ( mode , i0 ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , out , gen_rtx_PLUS ( mode , f0 , f0 ) ) ) ; emit_label ( donelab ) ; } </s>

Generate an unsigned DImode to FP conversion . This is the same code optabs would emit if we did n't have TFmode patterns .


<s> static int arc_memory_move_cost ( machine_mode mode , reg_class_t rclass ATTRIBUTE_UNUSED , bool in ATTRIBUTE_UNUSED ) { if ( ( GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD ) || ( ( GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD * 2 ) && TARGET_LL64 ) ) return 6 ; return ( 2 * GET_MODE_SIZE ( mode ) ) ; } </s>


<s> DecodeStatus SparcDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & VStream , raw_ostream & CStream ) const { uint32_t Insn ; bool isLittleEndian = getContext ( ) . getAsmInfo ( ) -> isLittleEndian ( ) ; DecodeStatus Result = readInstruction32 ( Bytes , Address , Size , Insn , isLittleEndian ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( STI . getFeatureBits ( ) [ Sparc :: FeatureV9 ] ) { Result = decodeInstruction ( DecoderTableSparcV932 , Instr , Insn , Address , this , STI ) ; } else { Result = decodeInstruction ( DecoderTableSparcV832 , Instr , Insn , Address , this , STI ) ; } if ( Result != MCDisassembler :: Fail ) return Result ; Result = decodeInstruction ( DecoderTableSparc32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .

Sparc Sparc Sparc::FeatureV9 Sparc Sparc Sparc 4


<s> static inline tree def_builtin ( HOST_WIDE_INT mask , HOST_WIDE_INT mask2 , const char * name , enum ix86_builtin_func_type tcode , enum ix86_builtins code ) { tree decl = NULL_TREE ; if ( ! ( mask & OPTION_MASK_ISA_64BIT ) || TARGET_64BIT ) { ix86_builtins_isa [ ( int ) code ] . isa = mask ; ix86_builtins_isa [ ( int ) code ] . isa2 = mask2 ; mask &= ~ OPTION_MASK_ISA_64BIT ; if ( ( mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512VL ) && mask != OPTION_MASK_ISA_AVX512VL ) mask &= ~ OPTION_MASK_ISA_AVX512VL ; if ( ( mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512BW ) && mask != OPTION_MASK_ISA_AVX512BW ) mask &= ~ OPTION_MASK_ISA_AVX512BW ; if ( ( ( mask2 == 0 || ( mask2 & ix86_isa_flags2 ) != 0 ) && ( mask == 0 || ( mask & ix86_isa_flags ) != 0 ) ) || ( ( mask & OPTION_MASK_ISA_MMX ) != 0 && TARGET_MMX_WITH_SSE ) || ( mask2 == OPTION_MASK_ISA2_AVXVNNI ) || ( lang_hooks . builtin_function == lang_hooks . builtin_function_ext_scope ) ) { tree type = ix86_get_builtin_func_type ( tcode ) ; decl = add_builtin_function ( name , type , code , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ ( int ) code ] = decl ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = false ; } else { deferred_isa_values |= mask ; deferred_isa_values2 |= mask2 ; ix86_builtins [ ( int ) code ] = NULL_TREE ; ix86_builtins_isa [ ( int ) code ] . tcode = tcode ; ix86_builtins_isa [ ( int ) code ] . name = name ; ix86_builtins_isa [ ( int ) code ] . const_p = false ; ix86_builtins_isa [ ( int ) code ] . pure_p = false ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = true ; } } return decl ; } </s>

Add a SPARC builtin function with NAME , ICODE , CODE and TYPE . Return the function decl or NULL_TREE if the builtin was not added .


<s> static int signal_function_p ( tree func ) { tree a ; if ( TREE_CODE ( func ) != FUNCTION_DECL ) return 0 ; a = lookup_attribute ( "signal" , DECL_ATTRIBUTES ( func ) ) ; return a != NULL_TREE ; } </s>

Return nonzero if FUNC is a signal function as specified by the `` signal '' attribute .


<s>
const
char
*
output_fp_compare
(
rtx
insn
,
rtx
*
operands
,
bool
eflags_p
,
bool
unordered_p
)
{
int
stack_top_dies
;
rtx
cmp_op0
,
cmp_op1
;
int
is_sse
=
SSE_REG_P
(
operands
[
0
]
)
||
SSE_REG_P
(
operands
[
1
]
)
;
if
(
eflags_p
)
{
cmp_op0
=
operands
[
0
]
;
cmp_op1
=
operands
[
1
]
;
}
else
{
cmp_op0
=
operands
[
1
]
;
cmp_op1
=
operands
[
2
]
;
}
if
(
is_sse
)
{
if
(
GET_MODE
(
operands
[
0
]
)
==
SFmode
)
if
(
unordered_p
)
return
"%vucomiss\t{%1, %0|%0, %1}"
;
else
return
"%vcomiss\t{%1, %0|%0, %1}"
;
else
if
(
unordered_p
)
return
"%vucomisd\t{%1, %0|%0, %1}"
;
else
return
"%vcomisd\t{%1, %0|%0, %1}"
;
}
gcc_assert
(
STACK_TOP_P
(
cmp_op0
)
)
;
stack_top_dies
=
find_regno_note
(
insn
,
REG_DEAD
,
FIRST_STACK_REG
)
!=
0
;
if
(
cmp_op1
==
CONST0_RTX
(
GET_MODE
(
cmp_op1
)
)
)
{
if
(
stack_top_dies
)
{
output_asm_insn
(
"ftst\n\tfnstsw\t%0"
,
operands
)
;
return
output_387_ffreep
(
operands
,
1
)
;
}
else
return
"ftst\n\tfnstsw\t%0"
;
}
if
(
STACK_REG_P
(
cmp_op1
)
&&
stack_top_dies
&&
find_regno_note
(
insn
,
REG_DEAD
,
REGNO
(
cmp_op1
)
)
&&
REGNO
(
cmp_op1
)
!=
FIRST_STACK_REG
)
{
if
(
eflags_p
)
{
if
(
unordered_p
)
output_asm_insn
(
"fucomip\t{%y1, %0|%0, %y1}"
,
operands
)
;
else
output_asm_insn
(
"fcomip\t{%y1, %0|%0, %y1}"
,
operands
)
;
return
output_387_ffreep
(
operands
,
0
)
;
}
else
{
if
(
unordered_p
)
return
"fucompp\n\tfnstsw\t%0"
;
else
return
"fcompp\n\tfnstsw\t%0"
;
}
}
else
{
static
const
char
*
const
alt
[
16
]
=
{
"fcom%Z2\t%y2\n\tfnstsw\t%0"
,
"fcomp%Z2\t%y2\n\tfnstsw\t%0"
,
"fucom%Z2\t%y2\n\tfnstsw\t%0"
,
"fucomp%Z2\t%y2\n\tfnstsw\t%0"
,
"ficom%Z2\t%y2\n\tfnstsw\t%0"
,
"ficomp%Z2\t%y2\n\tfnstsw\t%0"
,
,
,
"fcomi\t{%y1, %0|%0, %y1}"
,
"fcomip\t{%y1, %0|%0, %y1}"
,
"fucomi\t{%y1, %0|%0, %y1}"
,
"fucomip\t{%y1, %0|%0, %y1}"
,
,
,
,
}
;
int
mask
;
const
char
*
ret
;
mask
=
eflags_p
<<
3
;
mask
|=
(
GET_MODE_CLASS
(
GET_MODE
(
cmp_op1
)
)
==
MODE_INT
)
<<
2
;
mask
|=
unordered_p
<<
1
;
mask
|=
stack_top_dies
;
gcc_assert
(
mask
<
16
)
;
ret
=
alt
[
mask
]
;
gcc_assert
(
ret
)
;
return
ret
;
}
}
</s>

Output code for INSN to compare OPERANDS . EFLAGS_P is 1 when fcomi should be used and 2 when fnstsw should be used . UNORDERED_P is true when fucom should be used .


<s> bool MVEGatherScatterLowering :: runOnFunction ( Function & F ) { if ( ! EnableMaskedGatherScatters ) return false ; auto & TPC = getAnalysis < TargetPassConfig > ( ) ; auto & TM = TPC . getTM < TargetMachine > ( ) ; auto * ST = & TM . getSubtarget < ARMSubtarget > ( F ) ; if ( ! ST -> hasMVEIntegerOps ( ) ) return false ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; SmallVector < IntrinsicInst * , 4 > Gathers ; SmallVector < IntrinsicInst * , 4 > Scatters ; bool Changed = false ; for ( BasicBlock & BB : F ) { Changed |= SimplifyInstructionsInBlock ( & BB ) ; for ( Instruction & I : BB ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & I ) ; if ( II && II -> getIntrinsicID ( ) == Intrinsic :: masked_gather && isa < FixedVectorType > ( II -> getType ( ) ) ) { Gathers . push_back ( II ) ; Changed |= optimiseAddress ( II -> getArgOperand ( 0 ) , II -> getParent ( ) , LI ) ; } else if ( II && II -> getIntrinsicID ( ) == Intrinsic :: masked_scatter && isa < FixedVectorType > ( II -> getArgOperand ( 0 ) -> getType ( ) ) ) { Scatters . push_back ( II ) ; Changed |= optimiseAddress ( II -> getArgOperand ( 1 ) , II -> getParent ( ) , LI ) ; } } } for ( unsigned i = 0 ; i < Gathers . size ( ) ; i ++ ) { IntrinsicInst * I = Gathers [ i ] ; Instruction * L = lowerGather ( I ) ; if ( L == nullptr ) continue ; SimplifyInstructionsInBlock ( L -> getParent ( ) ) ; Changed = true ; } for ( unsigned i = 0 ; i < Scatters . size ( ) ; i ++ ) { IntrinsicInst * I = Scatters [ i ] ; Instruction * S = lowerScatter ( I ) ; if ( S == nullptr ) continue ; SimplifyInstructionsInBlock ( S -> getParent ( ) ) ; Changed = true ; } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static bool arm_vectorize_vec_perm_const_ok ( machine_mode vmode , const unsigned char * sel ) { struct expand_vec_perm_d d ; unsigned int i , nelt , which ; bool ret ; d . vmode = vmode ; d . nelt = nelt = GET_MODE_NUNITS ( d . vmode ) ; d . testing_p = true ; memcpy ( d . perm , sel , nelt ) ; for ( i = which = 0 ; i < nelt ; ++ i ) { unsigned char e = d . perm [ i ] ; gcc_assert ( e < 2 * nelt ) ; which |= ( e < nelt ? 1 : 2 ) ; } if ( which == 2 ) for ( i = 0 ; i < nelt ; ++ i ) d . perm [ i ] -= nelt ; d . one_vector_p = ( which != 3 ) ; d . target = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 1 ) ; d . op1 = d . op0 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 2 ) ; if ( ! d . one_vector_p ) d . op1 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 3 ) ; start_sequence ( ) ; ret = arm_expand_vec_perm_const_1 ( & d ) ; end_sequence ( ) ; return ret ; } </s>


<s> VariantKind getKind ( ) const { return Kind ; } </s>


<s> bool AArch64CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { auto & Args = F . getArgumentList ( ) ; MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned i = 0 ; for ( auto & Arg : Args ) { ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + 1 , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs , ArrayRef < uint64_t > Offsets ) { MIRBuilder . buildSequence ( VRegs [ i ] , Regs , Offsets ) ; } ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; if ( F . isVarArg ( ) ) { if ( ! MF . getSubtarget < AArch64Subtarget > ( ) . isTargetDarwin ( ) ) { return false ; } uint64_t StackOffset = alignTo ( Handler . StackUsed , 8 ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; AArch64FunctionInfo * FuncInfo = MF . getInfo < AArch64FunctionInfo > ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( 4 , StackOffset , true ) ) ; } MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> void AArch64PassConfig :: addPostRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableDeadRegisterElimination ) addPass ( createAArch64DeadRegisterDefinitions ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && usingDefaultRegAlloc ( ) ) addPass ( createAArch64A57FPLoadBalancing ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


"Can only insert epilog into returning blocks"

"SPURegisterInfo::emitEpilogue: FrameSize not aligned"


<s> rtx extract_nth_lmsw_access_reg ( rtx_insn * insn , int n ) { rtx nth_rtx = extract_nth_access_rtx ( insn , n ) ; if ( nth_rtx == NULL_RTX ) return NULL_RTX ; switch ( get_attr_type ( insn ) ) { case TYPE_LOAD_MULTIPLE : return SET_DEST ( nth_rtx ) ; case TYPE_STORE_MULTIPLE : return SET_SRC ( nth_rtx ) ; default : gcc_unreachable ( ) ; } } </s>

Returns the register operated by the nth load/store operation in the real micro-operation accessing order . This function assumes INSN must be a multiple-word load/store insn .


<s> unsigned PPCFastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return PPCMaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return PPCMaterializeGV ( GV , VT ) ; else if ( isa < ConstantInt > ( C ) ) return PPCMaterializeInt ( C , VT , VT != MVT :: i1 ) ; return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s> unsigned getElementSize ( ) { return CurType . ElementSize ; } </s>

Return the size of an element read or written by Inst .


<s> bool isCall ( unsigned Opcode , bool * IsIndirectCall ) { * IsIndirectCall = false ; switch ( Opcode ) { default : return false ; case Mips :: JAL : case Mips :: BAL_BR : case Mips :: BLTZAL : case Mips :: BGEZAL : return true ; case Mips :: JALR : * IsIndirectCall = true ; return true ; } } </s>

Mips Mips::JAL Mips::BAL_BR Mips::BLTZAL Mips::BGEZAL Mips::JALR


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool RISCVTargetLowering :: isDesirableToCommuteWithShift ( const SDNode * N , CombineLevel Level ) const { SDValue N0 = N -> getOperand ( 0 ) ; EVT Ty = N0 . getValueType ( ) ; if ( Ty . isScalarInteger ( ) && ( N0 . getOpcode ( ) == ISD :: ADD || N0 . getOpcode ( ) == ISD :: OR ) ) { auto * C1 = dyn_cast < ConstantSDNode > ( N0 -> getOperand ( 1 ) ) ; auto * C2 = dyn_cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) ; if ( C1 && C2 ) { APInt C1Int = C1 -> getAPIntValue ( ) ; APInt ShiftedC1Int = C1Int << C2 -> getAPIntValue ( ) ; if ( isLegalAddImmediate ( ShiftedC1Int . getSExtValue ( ) ) ) return true ; if ( isLegalAddImmediate ( C1Int . getSExtValue ( ) ) ) return false ; int C1Cost = RISCVMatInt :: getIntMatCost ( C1Int , Ty . getSizeInBits ( ) , Subtarget . is64Bit ( ) ) ; int ShiftedC1Cost = RISCVMatInt :: getIntMatCost ( ShiftedC1Int , Ty . getSizeInBits ( ) , Subtarget . is64Bit ( ) ) ; if ( C1Cost < ShiftedC1Cost ) return false ; } } return true ; } </s>

Return true if it is profitable to move this shift by a constant amount through its operand , adjusting any immediate operands as necessary to preserve semantics .

RISCV RISCV 0 ISD::ADD ISD::OR 1 1 RISCVMatInt::getIntMatCost RISCVMatInt::getIntMatCost


<s> unsigned int mn10300_get_live_callee_saved_regs ( unsigned int * bytes_saved ) { int mask ; int i ; unsigned int count ; count = mask = 0 ; for ( i = 0 ; i <= LAST_EXTENDED_REGNUM ; i ++ ) if ( df_regs_ever_live_p ( i ) && ! call_used_regs [ i ] ) { mask |= ( 1 << i ) ; ++ count ; } if ( ( mask & 0x3c000 ) != 0 ) { for ( i = 0x04000 ; i < 0x40000 ; i <<= 1 ) if ( ( mask & i ) == 0 ) ++ count ; mask |= 0x3c000 ; } if ( bytes_saved ) * bytes_saved = count * UNITS_PER_WORD ; return mask ; } </s>

Returns the set of live , callee-saved registers as a bitmask . The callee-saved extended registers can not be stored individually , so all of them will be included in the mask if any one of them is used .


<s> bool isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const override { const bool SrcIsCheri = isCheriPointer ( SrcAS , nullptr ) ; const bool DestIsCheri = isCheriPointer ( DestAS , nullptr ) ; if ( ( SrcIsCheri || DestIsCheri ) && ( SrcIsCheri != DestIsCheri ) ) return false ; return SrcAS < 256 && DestAS < 256 ; } </s>

Returns true if a cast between SrcAS and DestAS is a noop .


<s> void function_expander :: add_address_operand ( rtx x ) { m_ops . safe_grow ( m_ops . length ( ) + 1 , true ) ; create_address_operand ( & m_ops . last ( ) , x ) ; } </s>

Add an address operand with value X . The static operand data says what mode and form the address must have .


<s> bool R600InstrInfo :: isLegalToSplitMBBAt ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) const { for ( MachineInstr :: const_mop_iterator I = MBBI -> operands_begin ( ) , E = MBBI -> operands_end ( ) ; I != E ; ++ I ) { if ( I -> isReg ( ) && ! TargetRegisterInfo :: isVirtualRegister ( I -> getReg ( ) ) && I -> isUse ( ) && RI . isPhysRegLiveAcrossClauses ( I -> getReg ( ) ) ) return false ; } return true ; } </s>

Return true if it 's legal to split the given basic block at the specified instruction ( i.e .


<s>
bool
X86CallFrameOptimization
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
STI
=
&
MF
.
getSubtarget
<
X86Subtarget
>
(
)
;
TII
=
STI
->
getInstrInfo
(
)
;
TFL
=
STI
->
getFrameLowering
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
const
X86RegisterInfo
&
RegInfo
=
*
static_cast
<
const
X86RegisterInfo
*
>
(
STI
->
getRegisterInfo
(
)
)
;
SlotSize
=
RegInfo
.
getSlotSize
(
)
;
assert
(
isPowerOf2_32
(
SlotSize
)
&&
"Expect power of 2 stack slot size"
)
;
Log2SlotSize
=
Log2_32
(
SlotSize
)
;
if
(
!
isLegal
(
MF
)
)
return
false
;
unsigned
FrameSetupOpcode
=
TII
->
getCallFrameSetupOpcode
(
)
;
bool
Changed
=
false
;
ContextVector
CallSeqVector
;
for
(
auto
&
MBB
:
MF
)
for
(
auto
&
MI
:
MBB
)
if
(
MI
.
getOpcode
(
)
==
FrameSetupOpcode
)
{
CallContext
Context
;
collectCallInfo
(
MF
,
MBB
,
MI
,
Context
)
;
CallSeqVector
.
push_back
(
Context
)
;
}
if
(
!
isProfitable
(
MF
,
CallSeqVector
)
)
return
false
;
for
(
auto
CC
:
CallSeqVector
)
{
if
(
CC
.
UsePush
)
{
adjustCallSequence
(
MF
,
CC
)
;
Changed
=
true
;
}
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s>
bool
Cpu0DAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_m
:
OutOps
.
push_back
(
Op
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> rtx rs6000_find_base_term ( rtx op ) { rtx base ; base = op ; if ( GET_CODE ( base ) == CONST ) base = XEXP ( base , 0 ) ; if ( GET_CODE ( base ) == PLUS ) base = XEXP ( base , 0 ) ; if ( GET_CODE ( base ) == UNSPEC ) switch ( XINT ( base , 1 ) ) { case UNSPEC_TOCREL : case UNSPEC_MACHOPIC_OFFSET : return XVECEXP ( base , 0 , 0 ) ; } return op ; } </s>


<s> void emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const override { } </s>


<s> void MipsPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; if ( getMipsSubtarget ( ) . os16 ( ) ) addPass ( createMipsOs16 ( getMipsTargetMachine ( ) ) ) ; if ( getMipsSubtarget ( ) . inMips16HardFloat ( ) ) addPass ( createMips16HardFloat ( getMipsTargetMachine ( ) ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

Mips Mips Mips Mips Mips Mips Mips Mips Mips


<s> bool ExpandPseudo :: expand ( ) { bool Expanded = false ; for ( MachineFunction :: iterator BB = MF . begin ( ) , BBEnd = MF . end ( ) ; BB != BBEnd ; ++ BB ) for ( Iter I = BB -> begin ( ) , End = BB -> end ( ) ; I != End ; ) Expanded |= expandInstr ( * BB , I ++ ) ; return Expanded ; } </s>

expand - Expand a record into a set of elements if possible .


"Expected a reg or frame index operand."

Return true if this is a load/store that can be potentially paired/merged .


<s> const uint16_t * LC3RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { LC3 :: R4 , LC3 :: R5 , LC3 :: R6 , LC3 :: R7 , LC3 :: R8 , LC3 :: R9 , 0 } ; return CalleeSavedRegs ; } </s>


"M68k DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> void eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { MBB . erase ( MI ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool X86InstrInfo :: getMachineCombinerPatterns ( MachineInstr & Root , SmallVectorImpl < MachineCombinerPattern :: MC_PATTERN > & Patterns ) const { bool Commute ; if ( isReassociationCandidate ( Root , Commute ) ) { if ( Commute ) { Patterns . push_back ( MachineCombinerPattern :: MC_REASSOC_AX_YB ) ; Patterns . push_back ( MachineCombinerPattern :: MC_REASSOC_XA_YB ) ; } else { Patterns . push_back ( MachineCombinerPattern :: MC_REASSOC_AX_BY ) ; Patterns . push_back ( MachineCombinerPattern :: MC_REASSOC_XA_BY ) ; } return true ; } return false ; } </s>

Return true when there is potentially a faster code sequence for an instruction chain ending in Root .


<s> const uint32_t * RISCVRegisterInfo :: getCallPreservedMask ( const MachineFunction & , CallingConv :: ID ) const { return CSR_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void markGlobalAsPromotedToConstantPool ( const GlobalVariable * GV ) { PromotedGlobals . insert ( GV ) ; } </s>

Indicate to the backend that GV has had its storage changed to inside a constant pool .


<s> void arm_emit_fp16_const ( rtx c ) { REAL_VALUE_TYPE r ; long bits ; REAL_VALUE_FROM_CONST_DOUBLE ( r , c ) ; bits = real_to_target ( NULL , & r , HFmode ) ; if ( WORDS_BIG_ENDIAN ) assemble_zeros ( 2 ) ; assemble_integer ( GEN_INT ( bits ) , 2 , BITS_PER_WORD , 1 ) ; if ( ! WORDS_BIG_ENDIAN ) assemble_zeros ( 2 ) ; } </s>

Emit a fp16 constant appropriately padded to occupy a 4-byte word . HFmode constant pool entries are actually loaded with ldr .


<s>
void
crx_print_operand_address
(
FILE
*
file
,
rtx
addr
)
{
enum
crx_addrtype
addrtype
;
struct
crx_address
address
;
int
offset
;
addrtype
=
crx_decompose_address
(
addr
,
&
address
)
;
if
(
address
.
disp
)
offset
=
INTVAL
(
address
.
disp
)
;
else
offset
=
0
;
switch
(
addrtype
)
{
case
CRX_REG_REL
:
fprintf
(
file
,
"%d(%s)"
,
offset
,
reg_names
[
REGNO
(
address
.
base
)
]
)
;
return
;
case
CRX_POST_INC
:
switch
(
GET_CODE
(
address
.
side_effect
)
)
{
case
PLUS
:
break
;
case
MINUS
:
offset
=
offset
;
break
;
case
POST_INC
:
offset
=
GET_MODE_SIZE
(
output_memory_reference_mode
)
;
break
;
case
POST_DEC
:
offset
=
GET_MODE_SIZE
(
output_memory_reference_mode
)
;
break
;
default
:
abort
(
)
;
}
fprintf
(
file
,
"%d(%s)+"
,
offset
,
reg_names
[
REGNO
(
address
.
base
)
]
)
;
return
;
case
CRX_SCALED_INDX
:
fprintf
(
file
,
"%d(%s, %s, %d)"
,
offset
,
reg_names
[
REGNO
(
address
.
base
)
]
,
reg_names
[
REGNO
(
address
.
index
)
]
,
address
.
scale
)
;
return
;
case
CRX_ABSOLUTE
:
output_addr_const
(
file
,
address
.
disp
)
;
return
;
default
:
abort
(
)
;
}
}
</s>

Implements the macro PRINT_OPERAND_ADDRESS defined in crx.h .


"There must be a free register after frame setup"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> static rtx frv_expand_voidtriop_builtin ( enum insn_code icode , tree call ) { rtx pat ; rtx op0 = frv_read_argument ( call , 0 ) ; rtx op1 = frv_read_argument ( call , 1 ) ; rtx op2 = frv_read_argument ( call , 2 ) ; rtx op3 ; op0 = frv_int_to_acc ( icode , 0 , op0 ) ; if ( ! op0 ) return NULL_RTX ; op1 = frv_legitimize_argument ( icode , 1 , op1 ) ; op2 = frv_legitimize_argument ( icode , 2 , op2 ) ; op3 = frv_matching_accg_for_acc ( op0 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 , op2 , op3 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return NULL_RTX ; } </s>

Expand builtins that take three operands and return void . The first argument must be a constant that describes a pair or quad accumulators . A fourth argument is created that is the accumulator guard register that corresponds to the accumulator .


<s> int PPCTTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { if ( DisablePPCConstHoist ) return BaseT :: getIntImmCost ( Imm , Ty , CostKind ) ; assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return ~ 0U ; if ( Imm == 0 ) return TTI :: TCC_Free ; if ( Imm . getBitWidth ( ) <= 64 ) { if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Basic ; if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) { if ( ( Imm . getZExtValue ( ) & 0xFFFF ) == 0 ) return TTI :: TCC_Basic ; return 2 * TTI :: TCC_Basic ; } } return 4 * TTI :: TCC_Basic ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> bool SystemZInstrInfo :: isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , BranchProbability Probability ) const { return NumCycles == 1 ; } </s>

Return true if it 's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion .


"Dangerous instruction in branch delay slot!"

Targets should implement this to emit instructions .


<s> bool MipsPassConfig :: addPreRegAlloc ( ) { if ( ! getMipsSubtarget ( ) . hasMips64 ( ) ) PM . add ( createMipsEmitGPRestorePass ( getMipsTargetMachine ( ) ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> bool AArch64RedundantCopyElimination :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; DomBBClobberedRegs . init ( * TRI ) ; DomBBUsedRegs . init ( * TRI ) ; OptBBClobberedRegs . init ( * TRI ) ; OptBBUsedRegs . init ( * TRI ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) Changed |= optimizeBlock ( & MBB ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .