<s> rtx ix86_fixup_binary_operands ( enum rtx_code code , machine_mode mode , rtx operands [ ] ) { rtx dst = operands [ 0 ] ; rtx src1 = operands [ 1 ] ; rtx src2 = operands [ 2 ] ; if ( ix86_swap_binary_operands_p ( code , mode , operands ) ) { gcc_assert ( GET_MODE ( src1 ) == GET_MODE ( src2 ) ) ; std :: swap ( src1 , src2 ) ; } if ( MEM_P ( src1 ) && MEM_P ( src2 ) ) { if ( rtx_equal_p ( src1 , src2 ) ) { src2 = force_reg ( mode , src2 ) ; src1 = src2 ; } else if ( rtx_equal_p ( dst , src1 ) ) src2 = force_reg ( mode , src2 ) ; else src1 = force_reg ( mode , src1 ) ; } if ( MEM_P ( dst ) && ! rtx_equal_p ( dst , src1 ) ) dst = gen_reg_rtx ( mode ) ; if ( CONSTANT_P ( src1 ) ) src1 = force_reg ( mode , src1 ) ; if ( MEM_P ( src1 ) && ! rtx_equal_p ( dst , src1 ) ) src1 = force_reg ( mode , src1 ) ; if ( code == PLUS && GET_MODE_CLASS ( mode ) == MODE_INT && MEM_P ( src2 ) ) src2 = force_reg ( mode , src2 ) ; operands [ 1 ] = src1 ; operands [ 2 ] = src2 ; return dst ; } </s>

Fix up OPERANDS to satisfy ix86_binary_operator_ok . Return the destination to use for the operation . If different from the true destination in operands [ 0 ] , a copy operation will be required .


<s> bool PPCTargetLowering :: SelectAddressRegRegOnly ( SDValue N , SDValue & Base , SDValue & Index , SelectionDAG & DAG ) const { if ( SelectAddressRegReg ( N , Base , Index , DAG ) ) return true ; if ( N . getOpcode ( ) == ISD :: ADD ) { Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } Base = DAG . getRegister ( PPC :: R0 , N . getValueType ( ) ) ; Index = N ; return true ; } </s>

SelectAddressRegRegOnly - Given the specified addressed , force it to be represented as an indexed [ r+r ] operation .


<s> EVT PPCTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { if ( this -> PPCSubTarget . isPPC64 ( ) ) { return MVT :: i64 ; } else { return MVT :: i32 ; } } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> virtual bool isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumTCycles , unsigned ExtraTCycles , MachineBasicBlock & FMBB , unsigned NumFCycles , unsigned ExtraFCycles , const BranchProbability & Probability ) const { const MCInstrDesc & TMCID = prior ( TMBB . end ( ) ) -> getDesc ( ) ; if ( TMCID . isReturn ( ) || TMCID . isCall ( ) ) return false ; const MCInstrDesc & FMCID = prior ( FMBB . end ( ) ) -> getDesc ( ) ; if ( FMCID . isReturn ( ) || FMCID . isCall ( ) ) return false ; if ( ( NumTCycles + NumFCycles ) > 16 ) return false ; return ! mayStall ( TMBB ) && ! mayStall ( FMBB ) ; } </s>


<s> unsigned int darwin_rs6000_special_round_type_align ( tree type , unsigned int computed , unsigned int specified ) { unsigned int align = MAX ( computed , specified ) ; if ( TYPE_PACKED ( type ) ) return align ; do { tree field = TYPE_FIELDS ( type ) ; while ( field != NULL && TREE_CODE ( field ) != FIELD_DECL ) field = DECL_CHAIN ( field ) ; if ( ! field ) break ; if ( DECL_PACKED ( field ) ) return align ; type = TREE_TYPE ( field ) ; while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; } while ( AGGREGATE_TYPE_P ( type ) ) ; if ( ! AGGREGATE_TYPE_P ( type ) && type != error_mark_node ) align = MAX ( align , TYPE_ALIGN ( type ) ) ; return align ; } </s>

Darwin increases record alignment to the natural alignment of the first field .


initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> unsigned X86TargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { if ( classifyEHPersonality ( PersonalityFn ) == EHPersonality :: CoreCLR ) return Subtarget -> isTarget64BitLP64 ( ) ? X86 :: RDX : X86 :: EDX ; return Subtarget -> isTarget64BitLP64 ( ) ? X86 :: RAX : X86 :: EAX ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s> const X86TargetMachine * getTargetMachine ( ) const { return static_cast < const X86TargetMachine * > ( & TM ) ; } </s>

Return the target machine ( if available ) .


<s> TargetLowering :: AtomicExpansionKind ARMTargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { if ( AI -> isFloatingPointOperation ( ) ) return AtomicExpansionKind :: CmpXChg ; unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; bool hasAtomicRMW = ! Subtarget -> isThumb ( ) || Subtarget -> hasV8MBaselineOps ( ) ; return ( Size <= ( Subtarget -> isMClass ( ) ? 32U : 64U ) && hasAtomicRMW ) ? AtomicExpansionKind :: LLSC : AtomicExpansionKind :: None ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> const TargetRegisterClass * getMatchingSuperRegClass ( const TargetRegisterClass * A , const TargetRegisterClass * B , unsigned Idx ) const { return A ; } </s>

getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register in it has a sub-register of the specified sub-register index which is in the specified register class B .


<s> bool SIFoldOperands :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; MRI = & MF . getRegInfo ( ) ; ST = & MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST -> getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; bool IsIEEEMode = MFI -> getMode ( ) . IEEE ; bool HasNSZ = MFI -> hasNoSignedZerosFPMath ( ) ; for ( MachineBasicBlock * MBB : depth_first ( & MF ) ) { MachineBasicBlock :: iterator I , Next ; for ( I = MBB -> begin ( ) ; I != MBB -> end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; tryFoldInst ( TII , & MI ) ; if ( ! TII -> isFoldableCopy ( MI ) ) { if ( IsIEEEMode || ( ! HasNSZ && ! MI . getFlag ( MachineInstr :: FmNsz ) ) || ! tryFoldOMod ( MI ) ) tryFoldClamp ( MI ) ; continue ; } MachineOperand & OpToFold = MI . getOperand ( 1 ) ; bool FoldingImm = OpToFold . isImm ( ) || OpToFold . isFI ( ) || OpToFold . isGlobal ( ) ; if ( ! FoldingImm && ! OpToFold . isReg ( ) ) continue ; if ( OpToFold . isReg ( ) && ! TargetRegisterInfo :: isVirtualRegister ( OpToFold . getReg ( ) ) ) continue ; MachineOperand & Dst = MI . getOperand ( 0 ) ; if ( Dst . isReg ( ) && ! TargetRegisterInfo :: isVirtualRegister ( Dst . getReg ( ) ) ) continue ; foldInstOperand ( MI , OpToFold ) ; } } return false ; } </s>

runOnMachineFunction - Emit the function body .


"code model %s does not support PIC mode"

Adjust target options after streaming them in . This is mainly about reconciling them with global options .


<s> bool ARMTargetLowering :: isDesirableToCommuteWithShift ( const SDNode * N , CombineLevel Level ) const { if ( Level == BeforeLegalizeTypes ) return true ; if ( N -> getOpcode ( ) != ISD :: SHL ) return true ; if ( Subtarget -> isThumb1Only ( ) ) { if ( N -> getOpcode ( ) != ISD :: SHL ) return true ; SDValue N1 = N -> getOperand ( 0 ) ; if ( N1 -> getOpcode ( ) != ISD :: ADD && N1 -> getOpcode ( ) != ISD :: AND && N1 -> getOpcode ( ) != ISD :: OR && N1 -> getOpcode ( ) != ISD :: XOR ) return true ; if ( auto * Const = dyn_cast < ConstantSDNode > ( N1 -> getOperand ( 1 ) ) ) { if ( Const -> getAPIntValue ( ) . ult ( 256 ) ) return false ; if ( N1 -> getOpcode ( ) == ISD :: ADD && Const -> getAPIntValue ( ) . slt ( 0 ) && Const -> getAPIntValue ( ) . sgt ( - 256 ) ) return false ; } return true ; } return false ; } </s>

Return true if it is profitable to move this shift by a constant amount through its operand , adjusting any immediate operands as necessary to preserve semantics .


<s> void GCNILPScheduler :: releasePredecessors ( const SUnit * SU ) { for ( const auto & PredEdge : SU -> Preds ) { auto PredSU = PredEdge . getSUnit ( ) ; if ( PredEdge . isWeak ( ) ) continue ; assert ( PredSU -> isBoundaryNode ( ) || PredSU -> NumSuccsLeft > 0 ) ; PredSU -> setHeightToAtLeast ( SU -> getHeight ( ) + PredEdge . getLatency ( ) ) ; if ( ! PredSU -> isBoundaryNode ( ) && -- PredSU -> NumSuccsLeft == 0 ) PendingQueue . push_front ( * new ( Alloc . Allocate ( ) ) Candidate ( PredSU ) ) ; } } </s>

releasePredecessors - Call releasePred on each of SU 's predecessors .


<s> bool X86IndirectBranchTrackingPass :: runOnMachineFunction ( MachineFunction & MF ) { const X86Subtarget & SubTarget = MF . getSubtarget < X86Subtarget > ( ) ; Metadata * isCFProtectionSupported = MF . getMMI ( ) . getModule ( ) -> getModuleFlag ( "cf-protection-branch" ) ; const X86TargetMachine * TM = static_cast < const X86TargetMachine * > ( & MF . getTarget ( ) ) ; bool isJITwithCET = TM -> isJIT ( ) ; bool isJITwithCET = false ; if ( ! isCFProtectionSupported && ! IndirectBranchTracking && ! isJITwithCET ) return false ; bool Changed = false ; TII = SubTarget . getInstrInfo ( ) ; EndbrOpcode = SubTarget . is64Bit ( ) ? X86 :: ENDBR64 : X86 :: ENDBR32 ; if ( ( TM -> getCodeModel ( ) == CodeModel :: Large || MF . getFunction ( ) . hasAddressTaken ( ) || ! MF . getFunction ( ) . hasLocalLinkage ( ) ) && ! MF . getFunction ( ) . doesNoCfCheck ( ) ) { auto MBB = MF . begin ( ) ; Changed |= addENDBR ( * MBB , MBB -> begin ( ) ) ; } for ( auto & MBB : MF ) { if ( MBB . hasAddressTaken ( ) ) Changed |= addENDBR ( MBB , MBB . begin ( ) ) ; bool EHPadIBTNeeded = MBB . isEHPad ( ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( I -> isCall ( ) && IsCallReturnTwice ( I -> getOperand ( 0 ) ) ) Changed |= addENDBR ( MBB , std :: next ( I ) ) ; if ( EHPadIBTNeeded && I -> isEHLabel ( ) ) { Changed |= addENDBR ( MBB , std :: next ( I ) ) ; EHPadIBTNeeded = false ; } } } return Changed ; } </s>


Return true if the vector misalignment factor is supported by the target .


<s> bool ARMTargetLowering :: shouldSinkOperands ( Instruction * I , SmallVectorImpl < Use * > & Ops ) const { if ( ! Subtarget -> hasNEON ( ) || ! I -> getType ( ) -> isVectorTy ( ) ) return false ; switch ( I -> getOpcode ( ) ) { case Instruction :: Sub : case Instruction :: Add : { if ( ! areExtractExts ( I -> getOperand ( 0 ) , I -> getOperand ( 1 ) ) ) return false ; Ops . push_back ( & I -> getOperandUse ( 0 ) ) ; Ops . push_back ( & I -> getOperandUse ( 1 ) ) ; return true ; } default : return false ; } return false ; } </s>

Return true if sinking I 's operands to the same basic block as I is profitable , e.g .


<s> const DataLayout * getDataLayout ( ) const override { return getSubtargetImpl ( ) -> getDataLayout ( ) ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> Optional < MCFixupKind > RISCVAsmBackend :: getFixupKind ( StringRef Name ) const { if ( STI . getTargetTriple ( ) . isOSBinFormatELF ( ) ) { unsigned Type ; Type = llvm :: StringSwitch < unsigned > ( Name ) . Default ( - 1u ) ; if ( Type != - 1u ) return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ; } return None ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> BitVector WebAssemblyRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; for ( auto Reg : { WebAssembly :: SP32 , WebAssembly :: SP64 , WebAssembly :: FP32 , WebAssembly :: FP64 } ) Reserved . set ( Reg ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> EVT X86TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsZeroVal , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( IsZeroVal && ! F -> getFnAttributes ( ) . hasAttribute ( Attributes :: NoImplicitFloat ) ) { if ( Size >= 16 && ( Subtarget -> isUnalignedMemAccessFast ( ) || ( ( DstAlign == 0 || DstAlign >= 16 ) && ( SrcAlign == 0 || SrcAlign >= 16 ) ) ) ) { if ( Size >= 32 ) { if ( Subtarget -> hasInt256 ( ) ) return MVT :: v8i32 ; if ( Subtarget -> hasFp256 ( ) ) return MVT :: v8f32 ; } if ( Subtarget -> hasSSE2 ( ) ) return MVT :: v4i32 ; if ( Subtarget -> hasSSE1 ( ) ) return MVT :: v4f32 ; } else if ( ! MemcpyStrSrc && Size >= 8 && ! Subtarget -> is64Bit ( ) && Subtarget -> hasSSE2 ( ) ) { return MVT :: f64 ; } } if ( Subtarget -> is64Bit ( ) && Size >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>


<s> static bool xtensa_function_value_regno_p ( const unsigned int regno ) { return ( regno == GP_RETURN ) ; } </s>

Worker function TARGET_FUNCTION_VALUE_REGNO_P .


<s> static void pru_function_arg_regi_mark_slot ( int regi , cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; HOST_WIDE_INT param_size = pru_function_arg_size ( mode , type ) ; gcc_assert ( named ) ; while ( param_size -- ) { gcc_assert ( regi >= FIRST_ARG_REGNUM && regi <= LAST_ARG_REGNUM ) ; gcc_assert ( ! cum -> regs_used [ regi - FIRST_ARG_REGNUM ] ) ; cum -> regs_used [ regi - FIRST_ARG_REGNUM ] = true ; regi ++ ; } } </s>

Mark CUM_V that a function argument will occupy HW register slot starting at REGI . The number of consecutive 8-bit HW registers marked as occupied depends on the MODE and TYPE of the argument .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"X86 FP_REG_KILL inserter"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void SITypeRewriter :: visitCallInst ( CallInst & I ) { IRBuilder < > Builder ( & I ) ; SmallVector < Value * , 8 > Args ; SmallVector < Type * , 8 > Types ; bool NeedToReplace = false ; Function * F = I . getCalledFunction ( ) ; std :: string Name = F -> getName ( ) . str ( ) ; for ( unsigned i = 0 , e = I . getNumArgOperands ( ) ; i != e ; ++ i ) { Value * Arg = I . getArgOperand ( i ) ; if ( Arg -> getType ( ) == v16i8 ) { Args . push_back ( Builder . CreateBitCast ( Arg , v4i32 ) ) ; Types . push_back ( v4i32 ) ; NeedToReplace = true ; Name = Name + ".v4i32" ; } else if ( Arg -> getType ( ) -> isVectorTy ( ) && Arg -> getType ( ) -> getVectorNumElements ( ) == 1 && Arg -> getType ( ) -> getVectorElementType ( ) == Type :: getInt32Ty ( I . getContext ( ) ) ) { Type * ElementTy = Arg -> getType ( ) -> getVectorElementType ( ) ; std :: string TypeName = "i32" ; InsertElementInst * Def = dyn_cast < InsertElementInst > ( Arg ) ; assert ( Def ) ; Args . push_back ( Def -> getOperand ( 1 ) ) ; Types . push_back ( ElementTy ) ; std :: string VecTypeName = "v1" + TypeName ; Name = Name . replace ( Name . find ( VecTypeName ) , VecTypeName . length ( ) , TypeName ) ; NeedToReplace = true ; } else { Args . push_back ( Arg ) ; Types . push_back ( Arg -> getType ( ) ) ; } } if ( ! NeedToReplace ) { return ; } Function * NewF = Mod -> getFunction ( Name ) ; if ( ! NewF ) { NewF = Function :: Create ( FunctionType :: get ( F -> getReturnType ( ) , Types , false ) , GlobalValue :: ExternalLinkage , Name , Mod ) ; NewF -> setAttributes ( F -> getAttributes ( ) ) ; } I . replaceAllUsesWith ( Builder . CreateCall ( NewF , Args ) ) ; I . eraseFromParent ( ) ; } </s>


<s>
static
void
aarch64_sls_emit_function_stub
(
FILE
*
out_file
,
int
regnum
)
{
asm_fprintf
(
out_file
,
"\tmov\tx16, x%d\n"
,
regnum
)
;
asm_fprintf
(
out_file
,
"\tbr\tx16\n"
)
;
}
</s>

Helper function for aarch64_sls_emit_blr_function_thunks and aarch64_sls_emit_shared_blr_thunks below .


<s> const char * ix86_output_indirect_jmp ( rtx call_op ) { if ( cfun -> machine -> indirect_branch_type != indirect_branch_keep ) { if ( ix86_red_zone_used ) gcc_unreachable ( ) ; ix86_output_indirect_branch ( call_op , "%0" , true ) ; } else output_asm_insn ( "%!jmp\t%A0" , & call_op ) ; return ( ix86_harden_sls & harden_sls_indirect_jmp ) ? "int3" : "" ; } </s>

Output indirect jump . CALL_OP is the jump target .


<s> bool MipsAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>


<s>
SDValue
PatmosTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
isVarArg
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .

Patmos
Patmos
ISD::InputArg
"Unsupported calling convention"


<s> unsigned ARM64InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case ARM64 :: LDRWui : case ARM64 :: LDRXui : case ARM64 :: LDRBui : case ARM64 :: LDRHui : case ARM64 :: LDRSui : case ARM64 :: LDRDui : case ARM64 :: LDRQui : if ( MI -> getOperand ( 0 ) . getSubReg ( ) == 0 && MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> static rtx nvptx_expand_shared_addr ( tree exp , rtx target , machine_mode ARG_UNUSED ( mode ) , int ignore , int vector ) { if ( ignore ) return target ; unsigned align = TREE_INT_CST_LOW ( CALL_EXPR_ARG ( exp , 2 ) ) ; unsigned offset = TREE_INT_CST_LOW ( CALL_EXPR_ARG ( exp , 0 ) ) ; unsigned size = TREE_INT_CST_LOW ( CALL_EXPR_ARG ( exp , 1 ) ) ; rtx addr = worker_red_sym ; if ( vector ) { offload_attrs oa ; populate_offload_attrs ( & oa ) ; unsigned int psize = ROUND_UP ( size + offset , align ) ; unsigned int pnum = nvptx_mach_max_workers ( ) ; vector_red_partition = MAX ( vector_red_partition , psize ) ; vector_red_size = MAX ( vector_red_size , psize * pnum ) ; vector_red_align = MAX ( vector_red_align , align ) ; if ( cfun -> machine -> red_partition == NULL ) cfun -> machine -> red_partition = gen_reg_rtx ( Pmode ) ; addr = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_nvptx_red_partition ( addr , GEN_INT ( offset ) ) ) ; } else { worker_red_align = MAX ( worker_red_align , align ) ; worker_red_size = MAX ( worker_red_size , size + offset ) ; if ( offset ) { addr = gen_rtx_PLUS ( Pmode , addr , GEN_INT ( offset ) ) ; addr = gen_rtx_CONST ( Pmode , addr ) ; } } emit_move_insn ( target , addr ) ; return target ; } </s>

Shared-memory reduction address expander .


<s> static rtx address_offset ( rtx op ) { if ( GET_CODE ( op ) == PRE_INC || GET_CODE ( op ) == PRE_DEC ) op = XEXP ( op , 0 ) ; else if ( GET_CODE ( op ) == PRE_MODIFY || GET_CODE ( op ) == LO_SUM ) op = XEXP ( op , 1 ) ; if ( GET_CODE ( op ) == CONST ) op = XEXP ( op , 0 ) ; if ( GET_CODE ( op ) == PLUS ) op = XEXP ( op , 1 ) ; if ( CONST_INT_P ( op ) ) return op ; return NULL_RTX ; } </s>

Given an address , return a constant offset term if one exists .


<s> void h8300_expand_branch ( rtx operands [ ] ) { enum rtx_code code = GET_CODE ( operands [ 0 ] ) ; rtx op0 = operands [ 1 ] ; rtx op1 = operands [ 2 ] ; rtx label = operands [ 3 ] ; rtx tmp ; tmp = gen_rtx_COMPARE ( VOIDmode , op0 , op1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cc0_rtx , tmp ) ) ; tmp = gen_rtx_fmt_ee ( code , VOIDmode , cc0_rtx , const0_rtx ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , tmp ) ) ; } </s>


<s>
bool
X86AsmParser
::
ParseDirective
(
AsmToken
DirectiveID
)
{
MCAsmParser
&
Parser
=
getParser
(
)
;
StringRef
IDVal
=
DirectiveID
.
getIdentifier
(
)
;
if
(
IDVal
==
".word"
)
return
ParseDirectiveWord
(
2
,
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
.
startswith
(
".code"
)
)
return
ParseDirectiveCode
(
IDVal
,
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
.
startswith
(
".att_syntax"
)
)
{
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.att_syntax noprefix' is not "
"supported: registers must have a "
"'%' prefix in .att_syntax"
)
;
}
getParser
(
)
.
setAssemblerDialect
(
0
)
;
return
false
;
}
else
if
(
IDVal
.
startswith
(
".intel_syntax"
)
)
{
getParser
(
)
.
setAssemblerDialect
(
1
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.intel_syntax prefix' is not "
"supported: registers must not have "
"a '%' prefix in .intel_syntax"
)
;
}
return
false
;
}
else
if
(
IDVal
.
startswith
(
".dwarf_addr_size"
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
!=
"4"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
".dwarf_addr_size must be 4"
)
;
Parser
.
Lex
(
)
;
return
false
;
}
return
true
;
}
</s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s>
void
SPUInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
unsigned
opc
;
bool
isValidFrameIdx
=
(
FrameIdx
<
SPUFrameInfo
::
maxFrameOffset
(
)
)
;
if
(
RC
==
SPU
::
GPRCRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr128
:
SPU
::
STQXr128
)
;
}
else
if
(
RC
==
SPU
::
R64CRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr64
:
SPU
::
STQXr64
)
;
}
else
if
(
RC
==
SPU
::
R64FPRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr64
:
SPU
::
STQXr64
)
;
}
else
if
(
RC
==
SPU
::
R32CRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr32
:
SPU
::
STQXr32
)
;
}
else
if
(
RC
==
SPU
::
R32FPRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr32
:
SPU
::
STQXr32
)
;
}
else
if
(
RC
==
SPU
::
R16CRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr16
:
SPU
::
STQXr16
)
;
}
else
if
(
RC
==
SPU
::
R8CRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr8
:
SPU
::
STQXr8
)
;
}
else
if
(
RC
==
SPU
::
VECREGRegisterClass
)
{
opc
=
(
isValidFrameIdx
)
SPU
::
STQDv16i8
:
SPU
::
STQXv16i8
;
}
else
{
llvm_unreachable
(
"Unknown regclass!"
)
;
}
DebugLoc
DL
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
opc
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
,
FrameIdx
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool AArch64FastISel :: isTypeLegal ( Type * Ty , MVT & VT ) { EVT evt = TLI . getValueType ( DL , Ty , true ) ; if ( Subtarget -> isTargetILP32 ( ) && Ty -> isPointerTy ( ) ) return false ; if ( evt == MVT :: Other || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; if ( VT == MVT :: f128 ) return false ; return TLI . isTypeLegal ( VT ) ; } </s>


<s> Value * ARMTargetLowering :: emitStoreConditional ( IRBuilderBase & Builder , Value * Val , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = isReleaseOrStronger ( Ord ) ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == 64 ) { Intrinsic :: ID Int = IsRelease ? Intrinsic :: arm_stlexd : Intrinsic :: arm_strexd ; Function * Strex = Intrinsic :: getDeclaration ( M , Int ) ; Type * Int32Ty = Type :: getInt32Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int32Ty , "lo" ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , 32 ) , Int32Ty , "hi" ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall ( Strex , { Lo , Hi , Addr } ) ; } Intrinsic :: ID Int = IsRelease ? Intrinsic :: arm_stlex : Intrinsic :: arm_strex ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Strex = Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateCall ( Strex , { Builder . CreateZExtOrBitCast ( Val , Strex -> getFunctionType ( ) -> getParamType ( 0 ) ) , Addr } ) ; } </s>

Perform a store-conditional operation to Addr .


<s> unsigned getPrefLoopAlignment ( ) const { return PrefLoopAlignment ; } </s>


<s> void arm_register_target_pragmas ( void ) { targetm . target_option . pragma_parse = arm_pragma_target_parse ; REGISTER_SUBTARGET_PRAGMAS ( ) ; } </s>

Register target pragmas . We need to add the hook for parsing # pragma GCC option here rather than in arm.cc since it will pull in various preprocessor functions , and those are not present in languages like fortran without a preprocessor .


Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook .


<s>
bool
RegDefsUses
::
update
(
const
MachineInstr
&
MI
,
unsigned
Begin
,
unsigned
End
)
{
BitVector
NewDefs
(
TRI
.
getNumRegs
(
)
)
,
NewUses
(
TRI
.
getNumRegs
(
)
)
;
bool
HasHazard
=
false
;
for
(
unsigned
I
=
Begin
;
I
!=
End
;
++
I
)
{
const
MachineOperand
&
MO
=
MI
.
getOperand
(
I
)
;
if
(
MO
.
isReg
(
)
&&
MO
.
getReg
(
)
)
{
if
(
checkRegDefsUses
(
NewDefs
,
NewUses
,
MO
.
getReg
(
)
,
MO
.
isDef
(
)
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
DEBUG_TYPE
": found register hazard for operand "
<<
I
<<
": "
;
MO
.
dump
(
)
)
;
HasHazard
=
true
;
}
}
}
Defs
|=
NewDefs
;
Uses
|=
NewUses
;
return
HasHazard
;
}
</s>

Mips
": found register hazard for operand "
": "


"@c Copyright (C) 2012-2023 Free Software Foundation, Inc.\n"

"@c For copying conditions, see the file "

"@c This file is generated automatically using\n"

Main program to convert flat files into built-in initialization code .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Branch Coalescing"
;
}
</s>


<s> static void v850_set_data_area ( tree decl , v850_data_area data_area ) { tree name ; switch ( data_area ) { case DATA_AREA_SDA : name = get_identifier ( "sda" ) ; break ; case DATA_AREA_TDA : name = get_identifier ( "tda" ) ; break ; case DATA_AREA_ZDA : name = get_identifier ( "zda" ) ; break ; default : return ; } DECL_ATTRIBUTES ( decl ) = tree_cons ( name , NULL , DECL_ATTRIBUTES ( decl ) ) ; } </s>

Store the indicated data area in the decl 's attributes .


<s> bool isIndirect ( ) { return Target != nullptr && Target -> isReg ( ) ; } </s>

Returns whether this is an indirect value .


<s> static void release_scratch_register_on_entry ( struct scratch_reg * sr ) { if ( sr -> saved ) { struct machine_function * m = cfun -> machine ; rtx x , insn = emit_insn ( gen_pop ( sr -> reg ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; x = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( UNITS_PER_WORD ) ) ; x = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , x ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , x ) ; m -> fs . sp_offset -= UNITS_PER_WORD ; } } </s>

Release a scratch register obtained from the preceding function . If RELEASE_VIA_POP is true , we just pop the register off the stack to release it . This is what non-Linux systems use with -fstack-check . Otherwise we use OFFSET to locate the saved register and the allocated stack space becomes part of the local frame and is deallocated by the epilogue .


<s> HOST_WIDE_INT sparc_compute_frame_size ( HOST_WIDE_INT size , int leaf_function ) { HOST_WIDE_INT frame_size , apparent_frame_size ; int args_size , n_global_fp_regs = 0 ; bool save_local_in_regs_p = false ; unsigned int i ; if ( leaf_function && ! cfun -> calls_alloca ) args_size = 0 ; else args_size = crtl -> outgoing_args_size + REG_PARM_STACK_SPACE ( cfun -> decl ) ; if ( TARGET_ARCH64 ) { for ( i = 0 ; i < 8 ; i ++ ) if ( save_global_or_fp_reg_p ( i , 0 ) ) n_global_fp_regs += 2 ; } else { for ( i = 0 ; i < 8 ; i += 2 ) if ( save_global_or_fp_reg_p ( i , 0 ) || save_global_or_fp_reg_p ( i + 1 , 0 ) ) n_global_fp_regs += 2 ; } if ( TARGET_FLAT ) for ( i = 16 ; i < 32 ; i ++ ) if ( save_local_or_in_reg_p ( i , leaf_function ) ) { save_local_in_regs_p = true ; break ; } for ( i = 32 ; i < ( TARGET_V9 ? 96 : 64 ) ; i += 2 ) if ( save_global_or_fp_reg_p ( i , 0 ) || save_global_or_fp_reg_p ( i + 1 , 0 ) ) n_global_fp_regs += 2 ; if ( size == 0 && n_global_fp_regs == 0 && args_size == 0 && ! save_local_in_regs_p ) frame_size = apparent_frame_size = 0 ; else { apparent_frame_size = ROUND_UP ( size , 8 ) + n_global_fp_regs * 4 ; frame_size = apparent_frame_size + ROUND_UP ( args_size , 8 ) ; frame_size += FIRST_PARM_OFFSET ( cfun -> decl ) ; frame_size = SPARC_STACK_ALIGN ( frame_size ) ; } sparc_frame_size = frame_size ; sparc_apparent_frame_size = apparent_frame_size ; sparc_n_global_fp_regs = n_global_fp_regs ; sparc_save_local_in_regs_p = save_local_in_regs_p ; return frame_size ; } </s>

Compute the frame size required by the function . This function is called during the reload pass and also by sparc_expand_prologue .


<s> void bpf_print_operand ( FILE * file , rtx op , int code ATTRIBUTE_UNUSED ) { switch ( GET_CODE ( op ) ) { case REG : fprintf ( file , "%s" , reg_names [ REGNO ( op ) ] ) ; break ; case MEM : output_address ( GET_MODE ( op ) , XEXP ( op , 0 ) ) ; break ; case CONST_DOUBLE : if ( CONST_DOUBLE_HIGH ( op ) ) fprintf ( file , HOST_WIDE_INT_PRINT_DOUBLE_HEX , CONST_DOUBLE_HIGH ( op ) , CONST_DOUBLE_LOW ( op ) ) ; else if ( CONST_DOUBLE_LOW ( op ) < 0 ) fprintf ( file , HOST_WIDE_INT_PRINT_HEX , CONST_DOUBLE_LOW ( op ) ) ; else fprintf ( file , HOST_WIDE_INT_PRINT_DEC , CONST_DOUBLE_LOW ( op ) ) ; break ; default : output_addr_const ( file , op ) ; } } </s>

Print an instruction operand . This function is called in the macro PRINT_OPERAND defined in bpf.h


<s>
const
uint32_t
*
AArch64RegisterInfo
::
getThisReturnPreservedMask
(
const
MachineFunction
&
MF
,
CallingConv
::
ID
CC
)
const
{
assert
(
CC
!=
CallingConv
::
GHC
&&
"should not be GHC calling convention."
)
;
return
CSR_AArch64_AAPCS_ThisReturn_RegMask
;
}
</s>

getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned ' is on an i32 first argument if the calling convention is one that can ( partially ) model this attribute with a preserved mask ( i.e .


<s> static int c6x_save_reg ( unsigned int regno ) { return ( ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] && ! fixed_regs [ regno ] ) || ( regno == RETURN_ADDR_REGNO && ( df_regs_ever_live_p ( regno ) || ! crtl -> is_leaf ) ) || ( regno == PIC_OFFSET_TABLE_REGNUM && must_reload_pic_reg_p ( ) ) ) ; } </s>


<s> bool and_operands_ok ( machine_mode mode , rtx op1 , rtx op2 ) { if ( memory_operand ( op1 , mode ) ) { if ( TARGET_MIPS16 ) { struct mips_address_info addr ; if ( ! mips_classify_address ( & addr , op1 , mode , false ) ) return false ; } return and_load_operand ( op2 , mode ) ; } else return and_reg_operand ( op2 , mode ) ; } </s>

Return true iff OP1 and OP2 are valid operands together for the * and < MODE > 3 and * and < MODE > 3_mips16 patterns . For the cases to consider , see the table in the comment before the pattern .


<s>
const
char
*
getPassName
(
)
const
{
return
"R600 Control Flow Finalizer Pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static bool is_store_insn1 ( rtx pat ) { if ( ! pat || pat == NULL_RTX ) return false ; if ( GET_CODE ( pat ) == SET ) return is_mem_ref ( SET_DEST ( pat ) ) ; if ( GET_CODE ( pat ) == PARALLEL ) { int i ; for ( i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) if ( is_store_insn1 ( XVECEXP ( pat , 0 , i ) ) ) return true ; } return false ; } </s>

Determine if PAT is a PATTERN of a store insn .


<s> static bool nds32_rtx_costs ( rtx x , int code , int outer_code , int opno , int * total , bool speed ) { return nds32_rtx_costs_impl ( x , code , outer_code , opno , total , speed ) ; } </s>

This target hook describes the relative costs of RTL expressions . Return 'true ' when all subexpressions of x have been processed . Return 'false ' to sum the costs of sub-rtx , plus cost of this operation . Refer to gcc/rtlanal.cc for more information .


<s> static bool legitimate_offset_address_p ( machine_mode mode , rtx x , bool index , bool strict ) { if ( GET_CODE ( x ) != PLUS ) return false ; if ( ! RTX_OK_FOR_BASE_P ( XEXP ( x , 0 ) , ( strict ) ) ) return false ; if ( ( ( index && RTX_OK_FOR_INDEX_P ( XEXP ( x , 1 ) , ( strict ) ) && GET_MODE_SIZE ( ( mode ) ) <= 4 ) || RTX_OK_FOR_OFFSET_P ( mode , XEXP ( x , 1 ) ) ) ) return true ; if ( ! flag_pic && ( GET_CODE ( XEXP ( x , 1 ) ) == SYMBOL_REF ) && ( GET_MODE_SIZE ( mode ) <= 4 ) && ( ! SYMBOL_REF_SMALL_P ( XEXP ( x , 1 ) ) ) ) return true ; return false ; } </s>

Check for constructions like REG + OFFS , where OFFS can be a register , an immediate or an long immediate .


<s> static tree rs6000_builtin_mask_for_load ( void ) { if ( TARGET_ALTIVEC ) return altivec_builtin_mask_for_load ; else return 0 ; } </s>


<s> static int ix86_memory_move_cost ( machine_mode mode , reg_class_t regclass , bool in ) { return inline_memory_move_cost ( mode , ( enum reg_class ) regclass , in ? 1 : 0 ) ; } </s>

Return the cost of moving data of mode M between a register and memory . A value of 2 is the default ; this cost is relative to those in ` REGISTER_MOVE_COST ' . If moving between registers and memory is more expensive than between two registers , you should define this macro to express the relative cost . Model also increased moving costs of QImode registers in non Q_REGS classes .


<s>
static
reg_class_t
m32c_preferred_reload_class
(
rtx
x
,
reg_class_t
rclass
)
{
reg_class_t
newclass
=
rclass
;
fprintf
(
stderr
,
"\npreferred_reload_class for %s is "
,
class_names
[
rclass
]
)
;
if
(
rclass
==
NO_REGS
)
rclass
=
GET_MODE
(
x
)
==
QImode
HL_REGS
:
R03_REGS
;
if
(
reg_classes_intersect_p
(
rclass
,
CR_REGS
)
)
{
switch
(
GET_MODE
(
x
)
)
{
case
E_QImode
:
newclass
=
HL_REGS
;
break
;
default
:
break
;
}
}
else
if
(
newclass
==
QI_REGS
&&
GET_MODE_SIZE
(
GET_MODE
(
x
)
)
>
2
)
newclass
=
SI_REGS
;
else
if
(
GET_MODE_SIZE
(
GET_MODE
(
x
)
)
>
4
&&
!
reg_class_subset_p
(
R03_REGS
,
rclass
)
)
newclass
=
DI_REGS
;
rclass
=
reduce_class
(
rclass
,
newclass
,
rclass
)
;
if
(
GET_MODE
(
x
)
==
QImode
)
rclass
=
reduce_class
(
rclass
,
HL_REGS
,
rclass
)
;
fprintf
(
stderr
,
"%s\n"
,
class_names
[
rclass
]
)
;
debug_rtx
(
x
)
;
if
(
GET_CODE
(
x
)
==
MEM
&&
GET_CODE
(
XEXP
(
x
,
0
)
)
==
PLUS
&&
GET_CODE
(
XEXP
(
XEXP
(
x
,
0
)
,
0
)
)
==
PLUS
)
fprintf
(
stderr
,
"Glorm!\n"
)
;
return
rclass
;
}
</s>

Implements PREFERRED_RELOAD_CLASS . In general , prefer general registers of the appropriate size .


<s> MipsTargetLowering :: ConstraintType MipsTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'd' : case 'y' : case 'f' : case 'c' : case 'l' : case 'x' : return C_RegisterClass ; case 'R' : return C_Memory ; } } if ( Constraint == "ZC" ) return C_Memory ; return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s>
void
WebAssemblyInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
auto
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
const
TargetRegisterClass
*
RC
=
Register
::
isVirtualRegister
(
DestReg
)
MRI
.
getRegClass
(
DestReg
)
:
MRI
.
getTargetRegisterInfo
(
)
->
getMinimalPhysRegClass
(
DestReg
)
;
unsigned
CopyOpcode
;
if
(
RC
==
&
WebAssembly
::
I32RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_I32
;
else
if
(
RC
==
&
WebAssembly
::
I64RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_I64
;
else
if
(
RC
==
&
WebAssembly
::
F32RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_F32
;
else
if
(
RC
==
&
WebAssembly
::
F64RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_F64
;
else
if
(
RC
==
&
WebAssembly
::
V128RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_V128
;
else
if
(
RC
==
&
WebAssembly
::
EXNREFRegClass
)
CopyOpcode
=
WebAssembly
::
COPY_EXNREF
;
else
llvm_unreachable
(
"Unexpected register class"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
CopyOpcode
)
,
DestReg
)
.
addReg
(
SrcReg
,
KillSrc
RegState
::
Kill
:
0
)
;
}
</s>


<s> unsigned DLXInstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { return 1 ; } </s>

isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s> static void emit_save_or_restore_global_fp_regs ( rtx base , int offset , sorr_act_t action ) { if ( offset < - 4096 || offset + sparc_n_global_fp_regs * 4 > 4095 ) { base = emit_adjust_base_to_offset ( base , offset ) ; offset = 0 ; } offset = emit_save_or_restore_regs ( 0 , 8 , base , offset , 0 , save_global_or_fp_reg_p , action , SORR_NONE ) ; emit_save_or_restore_regs ( 32 , TARGET_V9 ? 96 : 64 , base , offset , 0 , save_global_or_fp_reg_p , action , SORR_NONE ) ; } </s>

Emit code to save/restore call-saved global and FP registers .


<s> static bool iq2000_pass_by_reference ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int size ; if ( cum && targetm . calls . must_pass_in_stack ( mode , type ) ) { CUMULATIVE_ARGS temp ; temp = * cum ; if ( iq2000_function_arg ( pack_cumulative_args ( & temp ) , mode , type , named ) != 0 ) return 1 ; } if ( type == NULL_TREE || mode == DImode || mode == DFmode ) return 0 ; size = int_size_in_bytes ( type ) ; return size == - 1 || size > UNITS_PER_WORD ; } </s>

Return true when an argument must be passed by reference .


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> unsigned int R600InstrInfo :: getInstrLatency ( const InstrItineraryData * ItinData , const MachineInstr * MI , unsigned * PredCost ) const { if ( PredCost ) * PredCost = 2 ; return 2 ; } </s>

Compute the instruction latency of a given instruction .


<s>
static
void
nvptx_file_start
(
void
)
{
fputs
(
"// BEGIN PREAMBLE\n"
,
asm_out_file
)
;
fputs
(
"\t.version\t3.1\n"
,
asm_out_file
)
;
fputs
(
"\t.target\tsm_30\n"
,
asm_out_file
)
;
fprintf
(
asm_out_file
,
"\t.address_size %d\n"
,
GET_MODE_BITSIZE
(
Pmode
)
)
;
fputs
(
"// END PREAMBLE\n"
,
asm_out_file
)
;
}
</s>

Implement TARGET_ASM_FILE_START . Write the kinds of things ptxas expects at the start of a file .

nvptx
"// BEGIN PREAMBLE\n"
"\t.version\t3.1\n"
"\t.target\tsm_30\n"
"\t.address_size %d\n"
"// END PREAMBLE\n"


<s> static void expand_set_or_cpymem_via_rep ( rtx destmem , rtx srcmem , rtx destptr , rtx srcptr , rtx value , rtx orig_value , rtx count , machine_mode mode , bool issetmem ) { rtx destexp ; rtx srcexp ; rtx countreg ; HOST_WIDE_INT rounded_count ; if ( mode == QImode && CONST_INT_P ( count ) && ! ( INTVAL ( count ) & 3 ) && ! TARGET_PREFER_KNOWN_REP_MOVSB_STOSB && ( ! issetmem || orig_value == const0_rtx ) ) mode = SImode ; if ( destptr != XEXP ( destmem , 0 ) || GET_MODE ( destmem ) != BLKmode ) destmem = adjust_automodify_address_nv ( destmem , BLKmode , destptr , 0 ) ; countreg = ix86_zero_extend_to_Pmode ( scale_counter ( count , GET_MODE_SIZE ( mode ) ) ) ; if ( mode != QImode ) { destexp = gen_rtx_ASHIFT ( Pmode , countreg , GEN_INT ( exact_log2 ( GET_MODE_SIZE ( mode ) ) ) ) ; destexp = gen_rtx_PLUS ( Pmode , destexp , destptr ) ; } else destexp = gen_rtx_PLUS ( Pmode , destptr , countreg ) ; if ( ( ! issetmem || orig_value == const0_rtx ) && CONST_INT_P ( count ) ) { rounded_count = ROUND_DOWN ( INTVAL ( count ) , ( HOST_WIDE_INT ) GET_MODE_SIZE ( mode ) ) ; destmem = shallow_copy_rtx ( destmem ) ; set_mem_size ( destmem , rounded_count ) ; } else if ( MEM_SIZE_KNOWN_P ( destmem ) ) clear_mem_size ( destmem ) ; if ( issetmem ) { value = force_reg ( mode , gen_lowpart ( mode , value ) ) ; emit_insn ( gen_rep_stos ( destptr , countreg , destmem , value , destexp ) ) ; } else { if ( srcptr != XEXP ( srcmem , 0 ) || GET_MODE ( srcmem ) != BLKmode ) srcmem = adjust_automodify_address_nv ( srcmem , BLKmode , srcptr , 0 ) ; if ( mode != QImode ) { srcexp = gen_rtx_ASHIFT ( Pmode , countreg , GEN_INT ( exact_log2 ( GET_MODE_SIZE ( mode ) ) ) ) ; srcexp = gen_rtx_PLUS ( Pmode , srcexp , srcptr ) ; } else srcexp = gen_rtx_PLUS ( Pmode , srcptr , countreg ) ; if ( CONST_INT_P ( count ) ) { rounded_count = ROUND_DOWN ( INTVAL ( count ) , ( HOST_WIDE_INT ) GET_MODE_SIZE ( mode ) ) ; srcmem = shallow_copy_rtx ( srcmem ) ; set_mem_size ( srcmem , rounded_count ) ; } else { if ( MEM_SIZE_KNOWN_P ( srcmem ) ) clear_mem_size ( srcmem ) ; } emit_insn ( gen_rep_mov ( destptr , destmem , srcptr , srcmem , countreg , destexp , srcexp ) ) ; } } </s>

Output `` rep ; mov '' or `` rep ; stos '' instruction depending on ISSETMEM argument . When ISSETMEM is true , arguments SRCMEM and SRCPTR are ignored . When ISSETMEM is false , arguments VALUE and ORIG_VALUE are ignored . For setmem case , VALUE is a promoted to a wider size ORIG_VALUE . ORIG_VALUE is the original value passed to memset to fill the memory with . Other arguments have same meaning as for previous function .


<s> bool RISCVAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { bool HasStdExtC = STI . getFeatureBits ( ) [ RISCV :: FeatureStdExtC ] ; unsigned MinNopLen = HasStdExtC ? 2 : 4 ; if ( ( Count % MinNopLen ) != 0 ) return false ; for ( ; Count >= 4 ; Count -= 4 ) OS . write ( "\x13\0\0\0" , 4 ) ; if ( Count && HasStdExtC ) OS . write ( "\x01\0" , 2 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> static int tilepro_compare_multipliers ( const void * key , const void * t ) { return * ( const int * ) key - ( ( const struct tilepro_multiply_insn_seq * ) t ) -> multiplier ; } </s>


<s> unsigned R600InstrInfo :: isLegalUpTo ( const std :: vector < std :: vector < std :: pair < int , unsigned >> > & IGSrcs , const std :: vector < R600InstrInfo :: BankSwizzle > & Swz , const std :: vector < std :: pair < int , unsigned >> & TransSrcs , R600InstrInfo :: BankSwizzle TransSwz ) const { int Vector [ 4 ] [ 3 ] ; memset ( Vector , - 1 , sizeof ( Vector ) ) ; for ( unsigned i = 0 , e = IGSrcs . size ( ) ; i < e ; i ++ ) { const std :: vector < std :: pair < int , unsigned >> & Srcs = Swizzle ( IGSrcs [ i ] , Swz [ i ] ) ; for ( unsigned j = 0 ; j < 3 ; j ++ ) { const std :: pair < int , unsigned > & Src = Srcs [ j ] ; if ( Src . first < 0 || Src . first == 255 ) continue ; if ( Src . first == GET_REG_INDEX ( RI . getEncodingValue ( R600 :: OQAP ) ) ) { if ( Swz [ i ] != R600InstrInfo :: ALU_VEC_012_SCL_210 && Swz [ i ] != R600InstrInfo :: ALU_VEC_021_SCL_122 ) { return false ; } continue ; } if ( Vector [ Src . second ] [ j ] < 0 ) Vector [ Src . second ] [ j ] = Src . first ; if ( Vector [ Src . second ] [ j ] != Src . first ) return i ; } } for ( unsigned i = 0 , e = TransSrcs . size ( ) ; i < e ; ++ i ) { const std :: pair < int , unsigned > & Src = TransSrcs [ i ] ; unsigned Cycle = getTransSwizzle ( TransSwz , i ) ; if ( Src . first < 0 ) continue ; if ( Src . first == 255 ) continue ; if ( Vector [ Src . second ] [ Cycle ] < 0 ) Vector [ Src . second ] [ Cycle ] = Src . first ; if ( Vector [ Src . second ] [ Cycle ] != Src . first ) return IGSrcs . size ( ) - 1 ; } return IGSrcs . size ( ) ; } </s>

returns how many MIs ( whose inputs are represented by IGSrcs ) can be packed in the same Instruction Group while meeting read port limitations given a Swz swizzle sequence .


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { if ( RC == ARM :: GPRRegisterClass || RC == ARM :: tGPRRegisterClass || RC == ARM :: tcGPRRegisterClass || RC == ARM :: rGPRRegisterClass ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2LDRi12 ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } ARMBaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC , TRI ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .

ARM ARM::GPRRegisterClass ARM::tGPRRegisterClass ARM::tcGPRRegisterClass ARM::rGPRRegisterClass ARM::t2LDRi12 0 ARM


<s>
void
alpha_output_filename
(
FILE
*
stream
,
const
char
*
name
)
{
static
int
first_time
=
TRUE
;
if
(
first_time
)
{
first_time
=
FALSE
;
++
num_source_filenames
;
current_function_file
=
name
;
fprintf
(
stream
,
"\t.file\t%d "
,
num_source_filenames
)
;
output_quoted_string
(
stream
,
name
)
;
fprintf
(
stream
,
"\n"
)
;
}
else
if
(
name
!=
current_function_file
&&
strcmp
(
name
,
current_function_file
)
!=
0
)
{
++
num_source_filenames
;
current_function_file
=
name
;
fprintf
(
stream
,
"\t.file\t%d "
,
num_source_filenames
)
;
output_quoted_string
(
stream
,
name
)
;
fprintf
(
stream
,
"\n"
)
;
}
}
</s>

alpha
"\t.file\t%d "
"\n"
0
"\t.file\t%d "
"\n"


<s> bool AMDGPUCFGPerform :: runOnMachineFunction ( MachineFunction & func ) { return CFGStructurizer < AMDGPUCFGStructurizer > ( ) . run ( func , * this , getTargetRegisterInfo ( ) ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> void flushPendingInstructions ( MCStreamer & Out ) override { if ( ! inImplicitITBlock ( ) ) { assert ( PendingConditionalInsts . size ( ) == 0 ) ; return ; } MCInst ITInst ; ITInst . setOpcode ( ARM :: t2IT ) ; ITInst . addOperand ( MCOperand :: createImm ( ITState . Cond ) ) ; ITInst . addOperand ( MCOperand :: createImm ( ITState . Mask ) ) ; Out . EmitInstruction ( ITInst , getSTI ( ) ) ; assert ( PendingConditionalInsts . size ( ) <= 4 ) ; for ( const MCInst & Inst : PendingConditionalInsts ) { Out . EmitInstruction ( Inst , getSTI ( ) ) ; } PendingConditionalInsts . clear ( ) ; ITState . Mask = 0 ; ITState . CurPosition = ~ 0U ; } </s>

Ensure that all previously parsed instructions have been emitted to the output streamer , if the target does not emit them immediately .


<s> const char * TeeRISCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case TeeRISC_ISD :: RET : return "TeeRISC_ISD::RET" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s>
StringRef
getPassName
(
)
const
override
{
return
"Z80 DAG->DAG Instruction Selection"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static rtx_code_label * mips16_add_constant ( struct mips16_constant_pool * pool , rtx value , machine_mode mode ) { struct mips16_constant * * p , * c ; bool first_of_size_p ; first_of_size_p = true ; for ( p = & pool -> first ; * p != 0 ; p = & ( * p ) -> next ) { if ( mode == ( * p ) -> mode && rtx_equal_p ( value , ( * p ) -> value ) ) return ( * p ) -> label ; if ( GET_MODE_SIZE ( mode ) < GET_MODE_SIZE ( ( * p ) -> mode ) ) break ; if ( GET_MODE_SIZE ( mode ) == GET_MODE_SIZE ( ( * p ) -> mode ) ) first_of_size_p = false ; } if ( pool -> first == 0 ) pool -> highest_address = pool -> insn_address - ( UNITS_PER_WORD - 2 ) + 0x8000 ; pool -> highest_address -= GET_MODE_SIZE ( mode ) ; if ( first_of_size_p ) pool -> highest_address -= GET_MODE_SIZE ( mode ) - 1 ; c = XNEW ( struct mips16_constant ) ; c -> value = value ; c -> mode = mode ; c -> label = gen_label_rtx ( ) ; c -> next = * p ; * p = c ; return c -> label ; } </s>

Add constant VALUE to POOL and return its label . MODE is the value 's mode ( used for CONST_INTs , etc . ) .


<s> static rtx sparc_function_arg ( cumulative_args_t cum , const function_arg_info & arg ) { return sparc_function_arg_1 ( cum , arg , false ) ; } </s>

Handle the TARGET_FUNCTION_ARG target hook .


<s> SDValue MipsTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; unsigned Opc = N -> getOpcode ( ) ; switch ( Opc ) { default : break ; case ISD :: SDIVREM : case ISD :: UDIVREM : return performDivRemCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SELECT : return performSELECTCombine ( N , DAG , DCI , Subtarget ) ; case MipsISD :: CMovFP_F : case MipsISD :: CMovFP_T : return performCMovFPCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: AND : return performANDCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: OR : return performORCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: ADD : return performADDCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SHL : return performSHLCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SUB : return performSUBCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips Mips ISD::SDIVREM ISD::UDIVREM ISD::SELECT MipsISD::CMovFP_F MipsISD::CMovFP_T ISD::AND ISD::OR ISD::ADD ISD::SHL ISD::SUB


<s> unsigned ARMBaseRegisterInfo :: getFrameRegister ( MachineFunction & MF ) const { if ( STI . isTargetDarwin ( ) || hasFP ( MF ) ) return FramePtr ; return ARM :: SP ; } </s>


<s> const char * Cpu0TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case Cpu0ISD :: JmpLink : return "Cpu0ISD::JmpLink" ; case Cpu0ISD :: TailCall : return "Cpu0ISD::TailCall" ; case Cpu0ISD :: Hi : return "Cpu0ISD::Hi" ; case Cpu0ISD :: Lo : return "Cpu0ISD::Lo" ; case Cpu0ISD :: GPRel : return "Cpu0ISD::GPRel" ; case Cpu0ISD :: Ret : return "Cpu0ISD::Ret" ; case Cpu0ISD :: EH_RETURN : return "Cpu0ISD::EH_RETURN" ; case Cpu0ISD :: DivRem : return "Cpu0ISD::DivRem" ; case Cpu0ISD :: DivRemU : return "Cpu0ISD::DivRemU" ; case Cpu0ISD :: Wrapper : return "Cpu0ISD::Wrapper" ; case Cpu0ISD :: Sync : return "Cpu0ISD::Sync" ; default : return NULL ; } } </s>


"\nrs6000_secondary_reload_gpr, type = %s\n"

Convert reloads involving 64-bit gprs and misaligned offset addressing , or multiple 32-bit gprs and offsets that are too large , to use indirect addressing .


<s>
void
arc_init
(
void
)
{
char
*
tmp
;
if
(
arc_cpu_string
==
0
||
!
strcmp
(
arc_cpu_string
,
"base"
)
)
{
arc_cpu_string
=
"base"
;
arc_cpu_type
=
0
;
arc_mangle_cpu
=
;
}
else
if
(
ARC_EXTENSION_CPU
(
arc_cpu_string
)
)
;
else
{
error
(
"bad value (%s) for -mcpu switch"
,
arc_cpu_string
)
;
arc_cpu_string
=
"base"
;
arc_cpu_type
=
0
;
arc_mangle_cpu
=
;
}
arc_text_section
=
tmp
=
xmalloc
(
strlen
(
arc_text_string
)
+
sizeof
(
ARC_SECTION_FORMAT
)
+
1
)
;
sprintf
(
tmp
,
ARC_SECTION_FORMAT
,
arc_text_string
)
;
arc_data_section
=
tmp
=
xmalloc
(
strlen
(
arc_data_string
)
+
sizeof
(
ARC_SECTION_FORMAT
)
+
1
)
;
sprintf
(
tmp
,
ARC_SECTION_FORMAT
,
arc_data_string
)
;
arc_rodata_section
=
tmp
=
xmalloc
(
strlen
(
arc_rodata_string
)
+
sizeof
(
ARC_SECTION_FORMAT
)
+
1
)
;
sprintf
(
tmp
,
ARC_SECTION_FORMAT
,
arc_rodata_string
)
;
arc_init_reg_tables
(
)
;
memset
(
arc_punct_chars
,
0
,
sizeof
(
arc_punct_chars
)
)
;
arc_punct_chars
[
'#'
]
=
1
;
arc_punct_chars
[
'*'
]
=
1
;
arc_punct_chars
[
'?'
]
=
1
;
arc_punct_chars
[
'!'
]
=
1
;
arc_punct_chars
[
'~'
]
=
1
;
}
</s>

Called by OVERRIDE_OPTIONS to initialize various things .


<s> bool PPCFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( ! Subtarget . isSVR4ABI ( ) ) return false ; MachineFunction * MF = MBB . getParent ( ) ; const PPCInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; PPCFunctionInfo * FI = MF -> getInfo < PPCFunctionInfo > ( ) ; bool MustSaveTOC = FI -> mustSaveTOC ( ) ; DebugLoc DL ; bool CRSpilled = false ; MachineInstrBuilder CRMIB ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg == PPC :: VRSAVE && ! Subtarget . isDarwinABI ( ) ) continue ; bool IsCRField = PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ; const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; bool IsLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! IsLiveIn ) MBB . addLiveIn ( Reg ) ; if ( CRSpilled && IsCRField ) { CRMIB . addReg ( Reg , RegState :: ImplicitKill ) ; continue ; } if ( ( Reg == PPC :: X2 || Reg == PPC :: R2 ) && MustSaveTOC ) continue ; if ( IsCRField ) { PPCFunctionInfo * FuncInfo = MF -> getInfo < PPCFunctionInfo > ( ) ; if ( Subtarget . isPPC64 ( ) ) { FuncInfo -> addMustSaveCR ( Reg ) ; } else { CRSpilled = true ; FuncInfo -> setSpillsCR ( ) ; CRMIB = BuildMI ( * MF , DL , TII . get ( PPC :: MFCR ) , PPC :: R12 ) . addReg ( Reg , RegState :: ImplicitKill ) ; MBB . insert ( MI , CRMIB ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( PPC :: STW ) ) . addReg ( PPC :: R12 , getKillRegState ( true ) ) , CSI [ i ] . getFrameIdx ( ) ) ) ; } } else { if ( CSI [ i ] . isSpilledToReg ( ) ) { NumPESpillVSR ++ ; BuildMI ( MBB , MI , DL , TII . get ( PPC :: MTVSRD ) , CSI [ i ] . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , ! IsLiveIn , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> void ix86_expand_truncdf_32 ( rtx operand0 , rtx operand1 ) { machine_mode mode = GET_MODE ( operand0 ) ; rtx xa , mask , TWO52 , one , res , smask , tmp ; rtx_code_label * label ; TWO52 = ix86_gen_TWO52 ( mode ) ; res = gen_reg_rtx ( mode ) ; emit_move_insn ( res , operand1 ) ; xa = ix86_expand_sse_fabs ( res , & smask ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; tmp = expand_simple_binop ( mode , PLUS , xa , TWO52 , NULL_RTX , 0 , OPTAB_DIRECT ) ; tmp = expand_simple_binop ( mode , MINUS , tmp , TWO52 , tmp , 0 , OPTAB_DIRECT ) ; emit_move_insn ( res , tmp ) ; one = force_reg ( mode , const_double_from_real_value ( dconst1 , mode ) ) ; mask = ix86_expand_sse_compare_mask ( UNGT , res , xa , false ) ; emit_insn ( gen_rtx_SET ( VOIDmode , mask , gen_rtx_AND ( mode , mask , one ) ) ) ; tmp = expand_simple_binop ( mode , MINUS , res , mask , NULL_RTX , 0 , OPTAB_DIRECT ) ; emit_move_insn ( res , tmp ) ; ix86_sse_copysign_to_positive ( res , res , force_reg ( mode , operand1 ) , smask ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; emit_move_insn ( operand0 , res ) ; } </s>

Expand SSE sequence for computing trunc from OPERAND1 storing into OPERAND0 .


<s> void s390_expand_atomic ( machine_mode mode , enum rtx_code code , rtx target , rtx mem , rtx val , bool after ) { struct alignment_context ac ; rtx cmp ; rtx new_rtx = gen_reg_rtx ( SImode ) ; rtx orig = gen_reg_rtx ( SImode ) ; rtx_code_label * csloop = gen_label_rtx ( ) ; gcc_assert ( ! target || register_operand ( target , VOIDmode ) ) ; gcc_assert ( MEM_P ( mem ) ) ; init_alignment_context ( & ac , mem , mode ) ; if ( ! ( ac . aligned && code == SET && MEM_P ( val ) ) ) val = s390_expand_mask_and_shift ( val , mode , ac . shift ) ; if ( code == PLUS || code == MINUS ) emit_move_insn ( orig , val ) ; else if ( code == MULT || code == AND ) val = expand_simple_binop ( SImode , XOR , val , ac . modemaski , NULL_RTX , 1 , OPTAB_DIRECT ) ; cmp = force_reg ( SImode , ac . memsi ) ; emit_label ( csloop ) ; emit_move_insn ( new_rtx , cmp ) ; switch ( code ) { case PLUS : case MINUS : val = expand_simple_binop ( SImode , code , new_rtx , orig , NULL_RTX , 1 , OPTAB_DIRECT ) ; val = expand_simple_binop ( SImode , AND , val , ac . modemask , NULL_RTX , 1 , OPTAB_DIRECT ) ; case SET : if ( ac . aligned && MEM_P ( val ) ) store_bit_field ( new_rtx , GET_MODE_BITSIZE ( mode ) , 0 , 0 , 0 , SImode , val , false ) ; else { new_rtx = expand_simple_binop ( SImode , AND , new_rtx , ac . modemaski , NULL_RTX , 1 , OPTAB_DIRECT ) ; new_rtx = expand_simple_binop ( SImode , IOR , new_rtx , val , NULL_RTX , 1 , OPTAB_DIRECT ) ; } break ; case AND : case IOR : case XOR : new_rtx = expand_simple_binop ( SImode , code , new_rtx , val , NULL_RTX , 1 , OPTAB_DIRECT ) ; break ; case MULT : new_rtx = expand_simple_binop ( SImode , AND , new_rtx , val , NULL_RTX , 1 , OPTAB_DIRECT ) ; new_rtx = expand_simple_binop ( SImode , XOR , new_rtx , ac . modemask , NULL_RTX , 1 , OPTAB_DIRECT ) ; break ; default : gcc_unreachable ( ) ; } s390_emit_jump ( csloop , s390_emit_compare_and_swap ( NE , cmp , ac . memsi , cmp , new_rtx , CCZ1mode ) ) ; if ( target ) convert_move ( target , expand_simple_binop ( SImode , LSHIFTRT , after ? new_rtx : cmp , ac . shift , NULL_RTX , 1 , OPTAB_DIRECT ) , 1 ) ; } </s>

Expand an atomic operation CODE of mode MODE . MEM is the memory location and VAL the value to play with . If AFTER is true then store the the value MEM holds after the operation , if AFTER is false then store the value MEM holds before the operation . If TARGET is zero then discard that value , else store it to TARGET .


<s> static bool s390_output_addr_const_extra ( FILE * file , rtx x ) { if ( GET_CODE ( x ) == UNSPEC && XVECLEN ( x , 0 ) == 1 ) switch ( XINT ( x , 1 ) ) { case UNSPEC_GOTENT : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fprintf ( file , "@GOTENT" ) ; return true ; case UNSPEC_GOT : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fprintf ( file , "@GOT" ) ; return true ; case UNSPEC_GOTOFF : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fprintf ( file , "@GOTOFF" ) ; return true ; case UNSPEC_PLT31 : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fprintf ( file , "@PLT" ) ; return true ; case UNSPEC_PLTOFF : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fprintf ( file , "@PLTOFF" ) ; return true ; case UNSPEC_TLSGD : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fprintf ( file , "@TLSGD" ) ; return true ; case UNSPEC_TLSLDM : assemble_name ( file , get_some_local_dynamic_name ( ) ) ; fprintf ( file , "@TLSLDM" ) ; return true ; case UNSPEC_DTPOFF : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fprintf ( file , "@DTPOFF" ) ; return true ; case UNSPEC_NTPOFF : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fprintf ( file , "@NTPOFF" ) ; return true ; case UNSPEC_GOTNTPOFF : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fprintf ( file , "@GOTNTPOFF" ) ; return true ; case UNSPEC_INDNTPOFF : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fprintf ( file , "@INDNTPOFF" ) ; return true ; } if ( GET_CODE ( x ) == UNSPEC && XVECLEN ( x , 0 ) == 2 ) switch ( XINT ( x , 1 ) ) { case UNSPEC_POOL_OFFSET : x = gen_rtx_MINUS ( GET_MODE ( x ) , XVECEXP ( x , 0 , 0 ) , XVECEXP ( x , 0 , 1 ) ) ; output_addr_const ( file , x ) ; return true ; } return false ; } </s>

Output machine-dependent UNSPECs occurring in address constant X in assembler syntax to stdio stream FILE . Returns true if the constant X could be recognized , false otherwise .


<s> static bool is_store_insn ( rtx insn , rtx * str_mem ) { if ( ! insn || ! INSN_P ( insn ) ) return false ; return is_store_insn1 ( PATTERN ( insn ) , str_mem ) ; } </s>


<s> bool MLxExpansion :: runOnMachineFunction ( MachineFunction & Fn ) { TII = static_cast < const ARMBaseInstrInfo * > ( Fn . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; const ARMSubtarget * STI = & Fn . getTarget ( ) . getSubtarget < ARMSubtarget > ( ) ; isLikeA9 = STI -> isLikeA9 ( ) || STI -> isSwift ( ) ; isSwift = STI -> isSwift ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : Fn ) Modified |= ExpandFPMLxInstructions ( MBB ) ; return Modified ; } </s>


<s> unsigned AVRInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { case AVR :: LDDRdPtrQ : case AVR :: LDDWRdYQ : { if ( ( MI -> getOperand ( 1 ) . isFI ( ) ) && ( MI -> getOperand ( 2 ) . isImm ( ) ) && ( MI -> getOperand ( 2 ) . getImm ( ) == 0 ) ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } default : break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> bool HexagonTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AS , unsigned Align , bool * Fast ) const { if ( Fast ) * Fast = false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case MVT :: v64i8 : case MVT :: v128i8 : case MVT :: v256i8 : case MVT :: v32i16 : case MVT :: v64i16 : case MVT :: v128i16 : case MVT :: v16i32 : case MVT :: v32i32 : case MVT :: v64i32 : case MVT :: v8i64 : case MVT :: v16i64 : case MVT :: v32i64 : return true ; } return false ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> void PPCRegisterInfo :: lowerCRSpilling ( MachineBasicBlock :: iterator II , unsigned FrameIndex ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = Subtarget . isPPC64 ( ) ; const TargetRegisterClass * G8RC = & PPC :: G8RCRegClass ; const TargetRegisterClass * GPRC = & PPC :: GPRCRegClass ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: MFCR8pseud : PPC :: MFCRpseud ) , Reg ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( 0 ) . isKill ( ) ) ) ; if ( SrcReg != PPC :: CR0 ) { unsigned Reg1 = Reg ; Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: RLWINM8 : PPC :: RLWINM ) , Reg ) . addReg ( Reg1 , RegState :: Kill ) . addImm ( getEncodingValue ( SrcReg ) * 4 ) . addImm ( 0 ) . addImm ( 31 ) ; } addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: STW8 : PPC :: STW ) ) . addReg ( Reg , RegState :: Kill ) , FrameIndex ) ; MBB . erase ( II ) ; } </s>

lowerCRSpilling - Generate the code for spilling a CR register .


<s> MachineInstr * X86InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr & MI , ArrayRef < unsigned > Ops , MachineBasicBlock :: iterator InsertPt , int FrameIndex , LiveIntervals * LIS ) const { if ( NoFusing ) return nullptr ; if ( ! MF . getFunction ( ) -> optForSize ( ) && hasPartialRegUpdate ( MI . getOpcode ( ) ) ) return nullptr ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned Size = MFI . getObjectSize ( FrameIndex ) ; unsigned Alignment = MFI . getObjectAlignment ( FrameIndex ) ; if ( ! RI . needsStackRealignment ( MF ) ) Alignment = std :: min ( Alignment , Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) ) ; if ( Ops . size ( ) == 2 && Ops [ 0 ] == 0 && Ops [ 1 ] == 1 ) { unsigned NewOpc = 0 ; unsigned RCSize = 0 ; switch ( MI . getOpcode ( ) ) { default : return nullptr ; case X86 :: TEST8rr : NewOpc = X86 :: CMP8ri ; RCSize = 1 ; break ; case X86 :: TEST16rr : NewOpc = X86 :: CMP16ri8 ; RCSize = 2 ; break ; case X86 :: TEST32rr : NewOpc = X86 :: CMP32ri8 ; RCSize = 4 ; break ; case X86 :: TEST64rr : NewOpc = X86 :: CMP64ri8 ; RCSize = 8 ; break ; } if ( Size < RCSize ) return nullptr ; MI . setDesc ( get ( NewOpc ) ) ; MI . getOperand ( 1 ) . ChangeToImmediate ( 0 ) ; } else if ( Ops . size ( ) != 1 ) return nullptr ; return foldMemoryOperandImpl ( MF , MI , Ops [ 0 ] , MachineOperand :: CreateFI ( FrameIndex ) , InsertPt , Size , Alignment , true ) ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> static void rs6000_function_specific_save ( struct cl_target_option * ptr , struct gcc_options * opts ) { ptr -> x_rs6000_isa_flags = opts -> x_rs6000_isa_flags ; ptr -> x_rs6000_isa_flags_explicit = opts -> x_rs6000_isa_flags_explicit ; } </s>


<s> static int sparc_register_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t from , reg_class_t to ) { bool need_memory = false ; if ( from == NO_REGS || to == NO_REGS ) return 100 ; if ( from == FPCC_REGS || to == FPCC_REGS ) need_memory = true ; else if ( ( FP_REG_CLASS_P ( from ) && general_or_i64_p ( to ) ) || ( general_or_i64_p ( from ) && FP_REG_CLASS_P ( to ) ) ) { if ( TARGET_VIS3 ) { int size = GET_MODE_SIZE ( mode ) ; if ( size == 8 || size == 4 ) { if ( ! TARGET_ARCH32 || size == 4 ) return 4 ; else return 6 ; } } need_memory = true ; } if ( need_memory ) { if ( sparc_cpu == PROCESSOR_ULTRASPARC || sparc_cpu == PROCESSOR_ULTRASPARC3 || sparc_cpu == PROCESSOR_NIAGARA || sparc_cpu == PROCESSOR_NIAGARA2 || sparc_cpu == PROCESSOR_NIAGARA3 || sparc_cpu == PROCESSOR_NIAGARA4 || sparc_cpu == PROCESSOR_NIAGARA7 || sparc_cpu == PROCESSOR_M8 ) return 12 ; return 6 ; } return 2 ; } </s>


<s> void HSAILImageHandles :: finalize ( ) { char buf [ 16 ] ; for ( unsigned i = 0 ; i < HSAILSamplers . size ( ) ; i ++ ) { if ( getSamplerSymbol ( i ) . empty ( ) ) { sprintf ( buf , "%s%u" , "__Samp" , index ) ; HSAILSamplers [ i ] -> setSym ( buf ) ; index ++ ; } } } </s>

Analyze the strings and build the final table .


<s> bool isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const override { return SrcAS < 256 && DestAS < 256 ; } </s>

Returns true if a cast between SrcAS and DestAS is a noop .


<s> inline void function_expander :: add_all_one_mask_operand ( machine_mode mode ) { add_input_operand ( mode , CONSTM1_RTX ( mode ) ) ; } </s>

Since we may normalize vop/vop_tu/vop_m/vop_tumu .. into a single patter . We add a fake all true mask for the intrinsics that do n't need a real mask .


<s> void xstormy16_expand_move ( enum machine_mode mode , rtx dest , rtx src ) { if ( ( GET_CODE ( dest ) == MEM ) && ( GET_CODE ( XEXP ( dest , 0 ) ) == PRE_MODIFY ) ) { rtx pmv = XEXP ( dest , 0 ) ; rtx dest_reg = XEXP ( pmv , 0 ) ; rtx dest_mod = XEXP ( pmv , 1 ) ; rtx set = gen_rtx_SET ( Pmode , dest_reg , dest_mod ) ; rtx clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( BImode , 16 ) ) ; dest = gen_rtx_MEM ( mode , dest_reg ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set , clobber ) ) ) ; } else if ( ( GET_CODE ( src ) == MEM ) && ( GET_CODE ( XEXP ( src , 0 ) ) == PRE_MODIFY ) ) { rtx pmv = XEXP ( src , 0 ) ; rtx src_reg = XEXP ( pmv , 0 ) ; rtx src_mod = XEXP ( pmv , 1 ) ; rtx set = gen_rtx_SET ( Pmode , src_reg , src_mod ) ; rtx clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( BImode , 16 ) ) ; src = gen_rtx_MEM ( mode , src_reg ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set , clobber ) ) ) ; } if ( ! reload_in_progress && ! reload_completed && GET_CODE ( dest ) == MEM && ( GET_CODE ( XEXP ( dest , 0 ) ) != CONST_INT || ! xstormy16_legitimate_address_p ( mode , XEXP ( dest , 0 ) , 0 ) ) && ! xstormy16_below100_operand ( dest , mode ) && GET_CODE ( src ) != REG && GET_CODE ( src ) != SUBREG ) src = copy_to_mode_reg ( mode , src ) ; if ( reload_completed && mode != HImode && mode != QImode ) { xstormy16_split_move ( mode , dest , src ) ; return ; } emit_insn ( gen_rtx_SET ( VOIDmode , dest , src ) ) ; } </s>

Expander for the 'move ' patterns . Emit insns to copy a value of mode MODE from SRC to DEST .


<s> long compute_frame_size ( poly_int64 size ) { int regno ; if ( reload_completed && cfun -> machine -> frame_laid_out ) return cfun -> machine -> current_frame_size ; if ( cfun -> static_chain_decl != NULL ) size += ( 1 * UNITS_PER_WORD ) ; cfun -> machine -> callee_save_size = 0 ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; ++ regno ) { if ( xtensa_call_save_reg ( regno ) ) cfun -> machine -> callee_save_size += UNITS_PER_WORD ; } cfun -> machine -> current_frame_size = XTENSA_STACK_ALIGN ( size + cfun -> machine -> callee_save_size + crtl -> outgoing_args_size + ( WINDOW_SIZE * UNITS_PER_WORD ) ) ; cfun -> machine -> callee_save_size = XTENSA_STACK_ALIGN ( cfun -> machine -> callee_save_size ) ; cfun -> machine -> frame_laid_out = true ; return cfun -> machine -> current_frame_size ; } </s>

Typical stack layout should looks like this after the function 's prologue : | | -- ^ | | \ | | | arguments saved | Increasing | | on the stack | addresses PARENT arg pointer - > | | / -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - | | - space for argument split between regs & stack -- CHILD | | \ < -- ( return address here ) | | other call | | saved registers | | / -- frame pointer - > | | \ ___ | | local | | | variables |f | | / |r -- |a | | \ |m | | outgoing |e | | arguments | | Decreasing ( hard ) frame pointer | | / | | addresses and stack pointer - > | | / _|_ | -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- V


<s> static rtx pru_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( mode , FIRST_RETVAL_REGNUM ) ; } </s>


<s> void MipsAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( Fixup , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned TargetOffset = getFixupKindInfo ( Kind ) . TargetOffset ; unsigned NumBytes = ( TargetOffset + getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { case FK_Data_2 : case Mips :: fixup_Mips_16 : FullSize = 2 ; break ; case FK_Data_8 : case Mips :: fixup_Mips_64 : FullSize = 8 ; break ; case FK_Data_4 : default : FullSize = 4 ; break ; } uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - 1 - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= ( Value & Mask ) << TargetOffset ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> SDValue M680x0TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { case M680x0ISD :: SUBX : return combineSUBX ( N , DAG ) ; case M680x0ISD :: ADDX : return combineADDX ( N , DAG , DCI ) ; case M680x0ISD :: SETCC : return combineM680x0SetCC ( N , DAG , Subtarget ) ; case M680x0ISD :: BRCOND : return combineM680x0BrCond ( N , DAG , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


"Code generation for MIPS-I is not implemented"

"Code generation for MIPS-V is not implemented"

"MSA requires a 64-bit FPU register file (FR=1 mode). "

"-mattr=+nooddspreg requires the O32 ABI."

"FPXX is not permitted for the N32/N64 ABI's."

"position-independent code requires '-mabicalls'"

"warning: cannot use small-data accesses for '-mabicalls'"

This constructor initializes the data members to match that of the specified triple .


<s> void i386_pe_unique_section ( tree decl , int reloc ) { int len ; const char * name , * prefix ; char * string ; name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; name = i386_pe_strip_name_encoding_full ( name ) ; if ( TREE_CODE ( decl ) == FUNCTION_DECL ) prefix = ".text$" ; else if ( decl_readonly_section ( decl , reloc ) ) prefix = ".rdata$" ; else prefix = ".data$" ; len = strlen ( name ) + strlen ( prefix ) ; string = alloca ( len + 1 ) ; sprintf ( string , "%s%s" , prefix , name ) ; DECL_SECTION_NAME ( decl ) = build_string ( len , string ) ; } </s>


";;\t\tBACKEND: move insn %d to the top of list\n"

";;\t\tBACKEND: best insn %d already on top\n"

"ready list ooo attributes - sched state: %d\n"

This function is called via hook TARGET_SCHED_REORDER before issuing one insn from list READY which contains * NREADYP entries . For target z10 it reorders load instructions to avoid early load conflicts in the floating point pipeline


<s> void SIRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const SISubtarget & Subtarget = MF -> getSubtarget < SISubtarget > ( ) ; const SIInstrInfo * TII = Subtarget . getInstrInfo ( ) ; if ( Offset == 0 ) { BuildMI ( * MBB , Ins , DL , TII -> get ( AMDGPU :: V_MOV_B32_e32 ) , BaseReg ) . addFrameIndex ( FrameIdx ) ; return ; } MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; unsigned OffsetReg = MRI . createVirtualRegister ( & AMDGPU :: SReg_32_XM0RegClass ) ; unsigned FIReg = MRI . createVirtualRegister ( & AMDGPU :: VGPR_32RegClass ) ; BuildMI ( * MBB , Ins , DL , TII -> get ( AMDGPU :: S_MOV_B32 ) , OffsetReg ) . addImm ( Offset ) ; BuildMI ( * MBB , Ins , DL , TII -> get ( AMDGPU :: V_MOV_B32_e32 ) , FIReg ) . addFrameIndex ( FrameIdx ) ; TII -> getAddNoCarry ( * MBB , Ins , DL , BaseReg ) . addReg ( OffsetReg , RegState :: Kill ) . addReg ( FIReg ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { bool HasAVX = TM . getSubtarget < X86Subtarget > ( ) . hasAVX ( ) ; if ( CC == CallingConv :: Intel_OCL_BI ) { if ( IsWin64 && HasAVX ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( Is64Bit && HasAVX ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; } if ( CC == CallingConv :: GHC || CC == CallingConv :: HiPE ) return CSR_NoRegs_RegMask ; if ( ! Is64Bit ) return CSR_32_RegMask ; if ( IsWin64 ) return CSR_Win64_RegMask ; return CSR_64_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
SDValue
AVRTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
auto
CCFunction
=
CCAssignFnForReturn
(
CallConv
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
CCFunction
)
;
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
unsigned
e
=
RVLocs
.
size
(
)
;
if
(
e
>
1
)
{
std
::
reverse
(
RVLocs
.
begin
(
)
,
RVLocs
.
end
(
)
)
;
}
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
if
(
MF
.
getFunction
(
)
.
getAttributes
(
)
.
hasAttribute
(
AttributeList
::
FunctionIndex
,
Attribute
::
Naked
)
)
{
return
Chain
;
}
const
AVRMachineFunctionInfo
*
AFI
=
MF
.
getInfo
<
AVRMachineFunctionInfo
>
(
)
;
unsigned
RetOpc
=
AFI
->
isInterruptOrSignalHandler
(
)
AVRISD
::
RETI_FLAG
:
AVRISD
::
RET_FLAG
;
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
{
RetOps
.
push_back
(
Flag
)
;
}
return
DAG
.
getNode
(
RetOpc
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool enablePostRAScheduler ( ) const override { return true ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s> const TargetRegisterClass * Thumb1RegisterInfo :: getPointerRegClass ( unsigned Kind ) const { return ARM :: tGPRRegisterClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s>
void
AlphaTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
DebugLoc
dl
=
N
->
getDebugLoc
(
)
;
assert
(
N
->
getValueType
(
0
)
==
MVT
::
i32
&&
N
->
getOpcode
(
)
==
ISD
::
VAARG
&&
"Unknown node to custom promote!"
)
;
SDValue
Chain
,
DataPtr
;
LowerVAARG
(
N
,
Chain
,
DataPtr
,
DAG
)
;
SDValue
Res
=
DAG
.
getLoad
(
N
->
getValueType
(
0
)
,
dl
,
Chain
,
DataPtr
,
,
0
,
false
,
false
,
0
)
;
Results
.
push_back
(
Res
)
;
Results
.
push_back
(
SDValue
(
Res
.
getNode
(
)
,
1
)
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> static void init_vselect_insn ( void ) { unsigned i ; rtx x ; x = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( MAX_VECT_LEN ) ) ; for ( i = 0 ; i < MAX_VECT_LEN ; ++ i ) XVECEXP ( x , 0 , i ) = const0_rtx ; x = gen_rtx_VEC_SELECT ( V2DFmode , gen_rtx_VEC_CONCAT ( V4DFmode , const0_rtx , const0_rtx ) , x ) ; x = gen_rtx_SET ( VOIDmode , const0_rtx , x ) ; start_sequence ( ) ; vselect_insn = emit_insn ( x ) ; end_sequence ( ) ; } </s>


<s> static struct machine_function * arm_init_machine_status ( void ) { struct machine_function * machine ; machine = ggc_cleared_alloc < machine_function > ( ) ; machine -> func_type = ARM_FT_UNKNOWN ; machine -> static_chain_stack_bytes = - 1 ; return machine ; } </s>

Functions to save and restore machine-specific function data .


<s> void TPCInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { DebugLoc DL ; BuildMI ( MBB , MI , DL , get ( TPC :: NOPv ) ) ; } </s>

Insert a noop into the instruction stream at the specified point .


<s> static void ft32_operand_lossage ( const char * msgid , rtx op ) { debug_rtx ( op ) ; output_operand_lossage ( "%s" , msgid ) ; } </s>

Emit an error message when we 're in an asm , and a fatal error for `` normal '' insns . Formatted output is n't easily implemented , since we use output_operand_lossage to output the actual message and handle the categorization of the error .


<s>
static
void
avr_file_end
(
void
)
{
if
(
avr_need_copy_data_p
)
fputs
(
".global __do_copy_data\n"
,
asm_out_file
)
;
if
(
avr_need_clear_bss_p
)
fputs
(
".global __do_clear_bss\n"
,
asm_out_file
)
;
}
</s>

Outputs to the stdio stream FILE some appropriate text to go at the end of an assembler file .

avr
".global __do_copy_data\n"
".global __do_clear_bss\n"


"no low registers available for popping high registers"

The bits which are n't usefully expanded as rtl .


Generate copies from defs used by the chain but not defined therein . Also populates defs_map which is used later by convert_insn .


<s> const uint16_t * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return ( STI . isTargetIOS ( ) ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ; } </s>


<s> static unsigned int cris_atomic_align_for_mode ( machine_mode mode ) { return GET_MODE_BITSIZE ( mode ) ; } </s>

Atomic types require alignment to be at least their `` natural '' size .


<s> bool AMDGPUAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( isHsaAbiVersion3Or4 ( & getSTI ( ) ) ) { if ( IDVal == ".amdhsa_kernel" ) return ParseDirectiveAMDHSAKernel ( ) ; if ( IDVal == AMDGPU :: HSAMD :: V3 :: AssemblerDirectiveBegin ) return ParseDirectiveHSAMetadata ( ) ; } else { if ( IDVal == ".hsa_code_object_version" ) return ParseDirectiveHSACodeObjectVersion ( ) ; if ( IDVal == ".hsa_code_object_isa" ) return ParseDirectiveHSACodeObjectISA ( ) ; if ( IDVal == ".amd_kernel_code_t" ) return ParseDirectiveAMDKernelCodeT ( ) ; if ( IDVal == ".amdgpu_hsa_kernel" ) return ParseDirectiveAMDGPUHsaKernel ( ) ; if ( IDVal == ".amd_amdgpu_isa" ) return ParseDirectiveISAVersion ( ) ; if ( IDVal == AMDGPU :: HSAMD :: AssemblerDirectiveBegin ) return ParseDirectiveHSAMetadata ( ) ; } if ( IDVal == ".amdgcn_target" ) return ParseDirectiveAMDGCNTarget ( ) ; if ( IDVal == ".amdgpu_lds" ) return ParseDirectiveAMDGPULDS ( ) ; if ( IDVal == PALMD :: AssemblerDirectiveBegin ) return ParseDirectivePALMetadataBegin ( ) ; if ( IDVal == PALMD :: AssemblerDirective ) return ParseDirectivePALMetadata ( ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


"Unexpected register class in CSRsViaCopy!"

"Function should be nounwind in insertCopiesSplitCSR!"

Insert explicit copies in entry and exit blocks .


<s> bool enableMachineSchedDefaultSched ( ) const override { return false ; } </s>

True if the machine scheduler should disable the TLI preference for preRA scheduling with the source level scheduler .


<s> bool HexagonTargetLowering :: IsEligibleForTailCallOptimization ( SDValue Callee , CallingConv :: ID CalleeCC , bool isVarArg , bool isCalleeStructRet , bool isCallerStructRet , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SmallVectorImpl < ISD :: InputArg > & Ins , SelectionDAG & DAG ) const { const Function * CallerF = DAG . getMachineFunction ( ) . getFunction ( ) ; CallingConv :: ID CallerCC = CallerF -> getCallingConv ( ) ; bool CCMatch = CallerCC == CalleeCC ; if ( ! isa < GlobalAddressSDNode > ( Callee ) && ! isa < ExternalSymbolSDNode > ( Callee ) ) { return false ; } if ( ! CCMatch ) return false ; if ( isVarArg ) return false ; if ( isCalleeStructRet || isCallerStructRet ) return false ; return true ; } </s>

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization .

Hexagon Hexagon ISD::OutputArg ISD::InputArg


<s> static void sparc_conditional_register_usage ( void ) { if ( PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM ) fixed_regs [ PIC_OFFSET_TABLE_REGNUM ] = 1 ; if ( TARGET_ARCH32 && fixed_regs [ 5 ] ) fixed_regs [ 5 ] = 1 ; else if ( TARGET_ARCH64 && fixed_regs [ 5 ] == 2 ) fixed_regs [ 5 ] = 0 ; if ( ! TARGET_V9 ) { int regno ; for ( regno = SPARC_FIRST_V9_FP_REG ; regno <= SPARC_LAST_V9_FP_REG ; regno ++ ) fixed_regs [ regno ] = 1 ; for ( regno = SPARC_FIRST_V9_FCC_REG + 1 ; regno <= SPARC_LAST_V9_FCC_REG ; regno ++ ) fixed_regs [ regno ] = 1 ; } if ( ! TARGET_FPU ) { int regno ; for ( regno = 32 ; regno < SPARC_LAST_V9_FCC_REG ; regno ++ ) fixed_regs [ regno ] = 1 ; } if ( fixed_regs [ 2 ] == 2 ) fixed_regs [ 2 ] = ! TARGET_APP_REGS ; if ( fixed_regs [ 3 ] == 2 ) fixed_regs [ 3 ] = ! TARGET_APP_REGS ; if ( TARGET_ARCH32 && fixed_regs [ 4 ] == 2 ) fixed_regs [ 4 ] = ! TARGET_APP_REGS ; else if ( TARGET_CM_EMBMEDANY ) fixed_regs [ 4 ] = 1 ; else if ( fixed_regs [ 4 ] == 2 ) fixed_regs [ 4 ] = 0 ; if ( TARGET_FLAT ) memset ( sparc_leaf_regs , 0 , FIRST_PSEUDO_REGISTER ) ; if ( TARGET_VIS ) global_regs [ SPARC_GSR_REG ] = 1 ; } </s>

If ! TARGET_FPU , then make the fp registers and fp cc regs fixed so that they wo n't be allocated .


<s> static HOST_WIDE_INT rs6000_starting_frame_offset ( void ) { if ( FRAME_GROWS_DOWNWARD ) return 0 ; return RS6000_STARTING_FRAME_OFFSET ; } </s>


<s> Register LanaiMachineFunctionInfo :: getGlobalBaseReg ( ) { if ( GlobalBaseReg ) return GlobalBaseReg ; return GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( & Lanai :: GPRRegClass ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s>
bool
WebAssemblyArgumentMove
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
DEBUG
(
{
dbgs
(
)
<<
"********** Argument Move **********\n"
<<
"********** Function: "
<<
MF
.
getName
(
)
<<
'\n'
;
}
)
;
bool
Changed
=
false
;
MachineBasicBlock
&
EntryMBB
=
MF
.
front
(
)
;
MachineBasicBlock
::
iterator
InsertPt
=
EntryMBB
.
end
(
)
;
for
(
auto
MII
=
EntryMBB
.
begin
(
)
,
MIE
=
EntryMBB
.
end
(
)
;
MII
!=
MIE
;
++
MII
)
{
MachineInstr
*
MI
=
MII
;
if
(
!
IsArgument
(
MI
)
)
{
InsertPt
=
MII
;
break
;
}
}
for
(
auto
I
=
InsertPt
,
E
=
EntryMBB
.
end
(
)
;
I
!=
E
;
++
I
)
{
MachineInstr
*
MI
=
I
;
if
(
IsArgument
(
MI
)
)
{
EntryMBB
.
insert
(
InsertPt
,
MI
->
removeFromParent
(
)
)
;
Changed
=
true
;
}
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

WebAssembly
WebAssembly
"********** Argument Move **********\n"
"********** Function: "


<s> void AMDGPUPeepholeOpt :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineFunctionAnalysis > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; AU . setPreservesAll ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Darwin PPC Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"getBranchTargetOpValue expects only expressions"

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s> bool MBlazeAsmPrinter :: isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { if ( MBB -> isLandingPad ( ) || MBB -> pred_empty ( ) ) return false ; MachineBasicBlock :: const_pred_iterator PI = MBB -> pred_begin ( ) , PI2 = PI ; ++ PI2 ; if ( PI2 != MBB -> pred_end ( ) ) return false ; const MachineBasicBlock * Pred = * PI ; if ( ! Pred -> isLayoutSuccessor ( MBB ) ) return false ; if ( Pred -> empty ( ) ) return true ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> isTerminator ( ) ) ; return I == Pred -> end ( ) || ! I -> isBarrier ( ) ; } </s>

isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


<s> static int ix86_mode_entry ( int entity ) { switch ( entity ) { case X86_DIRFLAG : return ix86_dirflag_mode_entry ( ) ; case AVX_U128 : return ix86_avx_u128_mode_entry ( ) ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : case I387_MASK_PM : return I387_CW_ANY ; default : gcc_unreachable ( ) ; } } </s>

Return a mode that ENTITY is assumed to be switched to at function entry .


<s> static inline bool m32r_load_postinc_p ( machine_mode mode , const_rtx x , bool strict ) { if ( ( mode == SImode || mode == SFmode ) && GET_CODE ( x ) == POST_INC && REG_P ( XEXP ( x , 0 ) ) && m32r_rtx_ok_for_base_p ( XEXP ( x , 0 ) , strict ) ) return true ; return false ; } </s>

Is this a load and increment operation .


<s> bool MOSAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { while ( ( Count -- ) > 0 ) { OS << 0xEA ; } return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> void clear ( ) { hasVPU = false ; hasSPU = false ; hasLD = false ; hasST = false ; VPUInst = 0L ; SPUInst = 0L ; LDInst = 0L ; STInst = 0L ; LdSrcExtra = 0 ; StSrcExtra = 0 ; LdSwitch = 0 ; StSwitch = 0 ; Imm = 0L ; immSlotBusy = false ; compress = 0 ; inited = false ; doNotCompress = false ; } </s>


<s> static bool v850_function_value_regno_p ( const unsigned int regno ) { return ( regno == RV_REGNUM ) ; } </s>

Worker function for TARGET_FUNCTION_VALUE_REGNO_P .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineBranchProbabilityInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> static inline bool inline_secondary_memory_needed ( enum reg_class class1 , enum reg_class class2 , machine_mode mode , int strict ) { if ( lra_in_progress && ( class1 == NO_REGS || class2 == NO_REGS ) ) return false ; if ( MAYBE_FLOAT_CLASS_P ( class1 ) != FLOAT_CLASS_P ( class1 ) || MAYBE_FLOAT_CLASS_P ( class2 ) != FLOAT_CLASS_P ( class2 ) || MAYBE_SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class1 ) || MAYBE_SSE_CLASS_P ( class2 ) != SSE_CLASS_P ( class2 ) || MAYBE_MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class1 ) || MAYBE_MMX_CLASS_P ( class2 ) != MMX_CLASS_P ( class2 ) ) { gcc_assert ( ! strict || lra_in_progress ) ; return true ; } if ( FLOAT_CLASS_P ( class1 ) != FLOAT_CLASS_P ( class2 ) ) return true ; if ( ( MAYBE_MASK_CLASS_P ( class1 ) != MAYBE_MASK_CLASS_P ( class2 ) ) && ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) ) return true ; if ( MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class2 ) ) return true ; if ( SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class2 ) ) { if ( ! TARGET_SSE2 ) return true ; if ( ( SSE_CLASS_P ( class1 ) && ! TARGET_INTER_UNIT_MOVES_FROM_VEC ) || ( SSE_CLASS_P ( class2 ) && ! TARGET_INTER_UNIT_MOVES_TO_VEC ) ) return true ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) return true ; } return false ; } </s>

If we are copying between general and FP registers , we need a memory location . The same is true for SSE and MMX registers . To optimize register_move_cost performance , allow inline variant . The macro ca n't work reliably when one of the CLASSES is class containing registers from multiple units ( SSE , MMX , integer ) . We avoid this by never combining those units in single alternative in the machine description . Ensure that this constraint holds to avoid unexpected surprises . When STRICT is false , we are being called from REGISTER_MOVE_COST , so do not enforce these sanity checks .


<s> int pic_address_needs_scratch ( rtx x ) { if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == SYMBOL_REF && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 1 ) ) == CONST_INT && ! SMALL_INT ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ) return 1 ; return 0 ; } </s>

Return true if X is an address which needs a temporary register when reloaded while generating PIC code .


<s> bool SystemZMCAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { for ( uint64_t I = 0 ; I != Count ; ++ I ) OW -> write8 ( 7 ) ; return true ; } </s>


<s>
static
int
avr_address_cost
(
rtx
x
,
machine_mode
mode
ATTRIBUTE_UNUSED
,
addr_space_t
as
ATTRIBUTE_UNUSED
,
bool
speed
ATTRIBUTE_UNUSED
)
{
int
cost
=
4
;
if
(
GET_CODE
(
x
)
==
PLUS
&&
CONST_INT_P
(
XEXP
(
x
,
1
)
)
&&
(
REG_P
(
XEXP
(
x
,
0
)
)
||
SUBREG_P
(
XEXP
(
x
,
0
)
)
)
)
{
if
(
INTVAL
(
XEXP
(
x
,
1
)
)
>
MAX_LD_OFFSET
(
mode
)
)
cost
=
18
;
}
else
if
(
CONSTANT_ADDRESS_P
(
x
)
)
{
if
(
io_address_operand
(
x
,
QImode
)
)
cost
=
2
;
if
(
AVR_TINY
&&
avr_address_tiny_absdata_p
(
x
,
QImode
)
)
cost
=
2
;
}
if
(
avr_log
.
address_cost
)
avr_edump
(
"\n%?: %d = %r\n"
,
cost
,
x
)
;
return
cost
;
}
</s>

Calculate the cost of a memory address .


<s>
virtual
const
char
*
getPassName
(
)
const
override
{
return
"SI Shrink Instructions"
;
}
</s>


<s>
unsigned
PPCTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
SelectionDAG
&
DAG
)
const
{
bool
isPPC64
=
Subtarget
.
isPPC64
(
)
;
bool
isDarwinABI
=
Subtarget
.
isDarwinABI
(
)
;
if
(
(
isPPC64
&&
VT
!=
MVT
::
i64
&&
VT
!=
MVT
::
i32
)
||
(
!
isPPC64
&&
VT
!=
MVT
::
i32
)
)
report_fatal_error
(
"Invalid register global variable type"
)
;
bool
is64Bit
=
isPPC64
&&
VT
==
MVT
::
i64
;
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"r1"
,
is64Bit
PPC
::
X1
:
PPC
::
R1
)
.
Case
(
"r2"
,
(
isDarwinABI
||
isPPC64
)
0
:
PPC
::
R2
)
.
Case
(
"r13"
,
(
!
isPPC64
&&
isDarwinABI
)
0
:
(
is64Bit
PPC
::
X13
:
PPC
::
R13
)
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> bool AMDGPUTargetELFStreamer :: EmitHSAMetadata ( const AMDGPU :: HSAMD :: Metadata & HSAMetadata ) { std :: string HSAMetadataString ; if ( HSAMD :: toString ( HSAMetadata , HSAMetadataString ) ) return false ; auto & Context = getContext ( ) ; auto * DescBegin = Context . createTempSymbol ( ) ; auto * DescEnd = Context . createTempSymbol ( ) ; auto * DescSZ = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( DescEnd , Context ) , MCSymbolRefExpr :: create ( DescBegin , Context ) , Context ) ; EmitNote ( ElfNote :: NoteNameV2 , DescSZ , ELF :: NT_AMD_AMDGPU_HSA_METADATA , [ & ] ( MCELFStreamer & OS ) { OS . emitLabel ( DescBegin ) ; OS . emitBytes ( HSAMetadataString ) ; OS . emitLabel ( DescEnd ) ; } ) ; return true ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 Assembly Printer"
;
}
</s>


<s> Register M68kRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? FramePtr : StackPtr ; } </s>


<s> static rtx riscv_force_binary ( enum machine_mode mode , enum rtx_code code , rtx x , rtx y ) { return riscv_emit_binary ( code , gen_reg_rtx ( mode ) , x , y ) ; } </s>

Compute ( CODE X Y ) and store the result in a new register of mode MODE . Return that new register .


<s> static unsigned int sparc_min_arithmetic_precision ( void ) { return 32 ; } </s>


<s> bool PatmosSinglePathInfo :: doInitialization ( Module & M ) { return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s>
bool
MOSInstrInfo
::
isBranchOffsetInRange
(
unsigned
BranchOpc
,
int64_t
BrOffset
)
const
{
switch
(
BranchOpc
)
{
default
:
llvm_unreachable
(
"Bad branch opcode"
)
;
case
MOS
::
GBR
:
case
MOS
::
BR
:
case
MOS
::
BRA
:
return
126
<=
BrOffset
&&
BrOffset
<=
129
;
case
MOS
::
JMP
:
return
true
;
}
}
</s>

Determine if the branch target is in range .

MOS
MOS
"Bad branch opcode"
MOS::GBR
MOS::BR
MOS::BRA
126
129
MOS::JMP


<s>
SDValue
XCoreTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
switch
(
CallConv
)
{
default
:
report_fatal_error
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
isVarArg
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .

XCore
XCore
ISD::InputArg
"Unsupported calling convention"


<s> rtx riscv_expand_builtin ( tree exp , rtx target , rtx subtarget ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , int ignore ATTRIBUTE_UNUSED ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , 0 ) ; unsigned int fcode = DECL_MD_FUNCTION_CODE ( fndecl ) ; unsigned int subcode = fcode >> RISCV_BUILTIN_SHIFT ; switch ( fcode & RISCV_BUILTIN_CLASS ) { case RISCV_BUILTIN_VECTOR : return riscv_vector :: expand_builtin ( subcode , exp , target ) ; case RISCV_BUILTIN_GENERAL : { const struct riscv_builtin_description * d = & riscv_builtins [ subcode ] ; switch ( d -> builtin_type ) { case RISCV_BUILTIN_DIRECT : return riscv_expand_builtin_direct ( d -> icode , target , exp , true ) ; case RISCV_BUILTIN_DIRECT_NO_TARGET : return riscv_expand_builtin_direct ( d -> icode , target , exp , false ) ; } } } gcc_unreachable ( ) ; } </s>


"Can only insert epilog into returning blocks"


<s> ARMSubtarget :: ARMSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const ARMBaseTargetMachine & TM , bool IsLittle , bool MinSize ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , UseMulOps ( UseFusedMulOps ) , ReservedGPRegisters ( ARM :: GPRRegClass . getNumRegs ( ) ) , CPUString ( CPU ) , OptMinSize ( MinSize ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( ARMBaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( ARMBaseInstrInfo * ) new ARMInstrInfo ( * this ) : ( ARMBaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) { CallLoweringInfo . reset ( new ARMCallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new ARMLegalizerInfo ( * this ) ) ; auto * RBI = new ARMRegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( createARMInstructionSelector ( * static_cast < const ARMBaseTargetMachine * > ( & TM ) , * this , * RBI ) ) ; RegBankInfo . reset ( RBI ) ; } </s>

This constructor initializes the data members to match that of the specified triple .

ARM ARM ARM ARM ARM ARM::GPRRegClass ARM ARM ARM ARM ARM ARM ARM ARM ARM


<s> static const uint16_t * lookup ( unsigned opcode , unsigned domain ) { for ( unsigned i = 0 , e = array_lengthof ( ReplaceableInstrs ) ; i != e ; ++ i ) if ( ReplaceableInstrs [ i ] [ domain - 1 ] == opcode ) return ReplaceableInstrs [ i ] ; return 0 ; } </s>

This method finds the value with the given Name in the the symbol table .


<s>
CCAssignFn
*
ARMFastISel
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
Return
,
bool
isVarArg
)
{
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
if
(
Subtarget
->
hasVFP2
(
)
&&
!
isVarArg
)
{
if
(
!
Subtarget
->
isAAPCS_ABI
(
)
)
return
(
Return
RetFastCC_ARM_APCS
:
FastCC_ARM_APCS
)
;
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
}
case
CallingConv
::
C
:
case
CallingConv
::
CXX_FAST_TLS
:
if
(
Subtarget
->
isAAPCS_ABI
(
)
)
{
if
(
Subtarget
->
hasVFP2
(
)
&&
TM
.
Options
.
FloatABIType
==
FloatABI
::
Hard
&&
!
isVarArg
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
else
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
}
else
{
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
}
case
CallingConv
::
ARM_AAPCS_VFP
:
case
CallingConv
::
Swift
:
if
(
!
isVarArg
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
case
CallingConv
::
ARM_AAPCS
:
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
case
CallingConv
::
ARM_APCS
:
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
case
CallingConv
::
GHC
:
if
(
Return
)
llvm_unreachable
(
"Can't return in GHC call convention"
)
;
else
return
CC_ARM_APCS_GHC
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .

ARM
ARM
"Unsupported calling convention"
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
"Can't return in GHC call convention"
ARM