<s> unsigned PPCTargetLowering :: getByValTypeAlignment ( Type * Ty , const DataLayout & DL ) const { Align Alignment = Subtarget . isPPC64 ( ) ? Align ( 8 ) : Align ( 4 ) ; if ( Subtarget . hasAltivec ( ) || Subtarget . hasQPX ( ) ) getMaxByValAlign ( Ty , Alignment , Subtarget . hasQPX ( ) ? Align ( 32 ) : Align ( 16 ) ) ; return Alignment . value ( ) ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


<s> SDNode * X86DAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI . getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> unsigned int rs6000_dbx_register_number ( unsigned int regno , unsigned int format ) { if ( ( format == 0 && write_symbols != DWARF2_DEBUG ) || format == 2 ) return regno ; if ( regno <= 63 ) return regno ; if ( regno == LR_REGNO ) return 108 ; if ( regno == CTR_REGNO ) return 109 ; if ( format == 1 && regno == CR2_REGNO ) return 64 ; if ( CR_REGNO_P ( regno ) ) return regno - CR0_REGNO + 86 ; if ( regno == CA_REGNO ) return 101 ; if ( ALTIVEC_REGNO_P ( regno ) ) return regno - FIRST_ALTIVEC_REGNO + 1124 ; if ( regno == VRSAVE_REGNO ) return 356 ; if ( regno == VSCR_REGNO ) return 67 ; return regno ; } </s>

Map internal gcc register numbers to DWARF2 register numbers .


<s> bool compact_sda_memory_operand ( rtx op , machine_mode mode , bool short_p ) { rtx addr ; int size ; tree decl = NULL_TREE ; int align = 0 ; int mask = 0 ; if ( GET_CODE ( op ) != MEM ) return false ; if ( mode == VOIDmode ) mode = GET_MODE ( op ) ; size = GET_MODE_SIZE ( mode ) ; if ( size > UNITS_PER_WORD ) return false ; addr = XEXP ( op , 0 ) ; if ( ! LEGITIMATE_SMALL_DATA_ADDRESS_P ( addr ) ) return false ; if ( ! short_p || size == 1 ) return true ; if ( GET_CODE ( XEXP ( addr , 1 ) ) == SYMBOL_REF ) decl = SYMBOL_REF_DECL ( XEXP ( addr , 1 ) ) ; else if ( GET_CODE ( XEXP ( XEXP ( XEXP ( addr , 1 ) , 0 ) , 0 ) ) == SYMBOL_REF ) decl = SYMBOL_REF_DECL ( XEXP ( XEXP ( XEXP ( addr , 1 ) , 0 ) , 0 ) ) ; if ( decl ) align = DECL_ALIGN ( decl ) ; align = align / BITS_PER_UNIT ; switch ( mode ) { case E_HImode : mask = 1 ; break ; default : mask = 3 ; break ; } if ( align && ( ( align & mask ) == 0 ) ) return true ; return false ; } </s>

volatile cache option still to be handled .


<s> unsigned HexagonTTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * DataTy , Value * Ptr , bool VariableMask , unsigned Alignment , const Instruction * I ) { return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , I ) ; } </s>

Calculate the cost of Gather / Scatter operation .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineModuleInfoWrapperPass > ( ) ; AU . setPreservesAll ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static unsigned int aarch64_autovectorize_vector_modes ( vector_modes * modes , bool ) { static const machine_mode sve_modes [ ] = { VNx16QImode , VNx8QImode , VNx4QImode , VNx2QImode } ; static const machine_mode advsimd_modes [ ] = { V16QImode , V8QImode , V4HImode , V2SImode } ; bool only_asimd_p = aarch64_autovec_preference == 1 ; bool only_sve_p = aarch64_autovec_preference == 2 ; unsigned int sve_i = ( TARGET_SVE && ! only_asimd_p ) ? 0 : ARRAY_SIZE ( sve_modes ) ; unsigned int advsimd_i = 0 ; while ( ! only_sve_p && advsimd_i < ARRAY_SIZE ( advsimd_modes ) ) { if ( sve_i < ARRAY_SIZE ( sve_modes ) && aarch64_cmp_autovec_modes ( sve_modes [ sve_i ] , advsimd_modes [ advsimd_i ] ) ) modes -> safe_push ( sve_modes [ sve_i ++ ] ) ; else modes -> safe_push ( advsimd_modes [ advsimd_i ++ ] ) ; } while ( sve_i < ARRAY_SIZE ( sve_modes ) ) modes -> safe_push ( sve_modes [ sve_i ++ ] ) ; unsigned int flags = 0 ; if ( TARGET_SVE && aarch64_sve_compare_costs ) flags |= VECT_COMPARE_COSTS ; return flags ; } </s>

Return a list of possible vector sizes for the vectorizer to iterate over .


<s> static bool m32r_legitimate_address_p ( machine_mode mode , rtx x , bool strict ) { if ( m32r_rtx_ok_for_base_p ( x , strict ) || m32r_legitimate_offset_addres_p ( mode , x , strict ) || m32r_legitimate_lo_sum_addres_p ( mode , x , strict ) || m32r_load_postinc_p ( mode , x , strict ) || m32r_store_preinc_predec_p ( mode , x , strict ) ) return true ; return false ; } </s>


<s> static rtx arc_emit_call_tls_get_addr ( rtx sym , int reloc , rtx eqv ) { rtx r0 = gen_rtx_REG ( Pmode , R0_REG ) ; rtx call_fusage = NULL_RTX ; start_sequence ( ) ; rtx x = arc_unspec_offset ( sym , reloc ) ; emit_move_insn ( r0 , x ) ; use_reg ( & call_fusage , r0 ) ; gcc_assert ( reloc == UNSPEC_TLS_GD ) ; rtx call_insn = emit_call_insn ( gen_tls_gd_get_addr ( sym ) ) ; RTL_PURE_CALL_P ( call_insn ) = 1 ; add_function_usage_to ( call_insn , call_fusage ) ; rtx_insn * insns = get_insns ( ) ; end_sequence ( ) ; rtx dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , r0 , eqv ) ; return dest ; } </s>

Helper to be used by TLS Global dynamic model .


"LC3 DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> static bool nios2_rtx_costs ( rtx x , machine_mode mode , int outer_code , int opno , int * total , bool speed ) { int code = GET_CODE ( x ) ; switch ( code ) { case CONST_INT : if ( INTVAL ( x ) == 0 || nios2_simple_const_p ( x ) ) { * total = COSTS_N_INSNS ( 0 ) ; return true ; } else { * total = COSTS_N_INSNS ( 1 ) ; return true ; } case LABEL_REF : case SYMBOL_REF : case CONST : case CONST_DOUBLE : if ( gprel_constant_p ( x ) || r0rel_constant_p ( x ) ) { * total = COSTS_N_INSNS ( 1 ) ; return true ; } else { * total = COSTS_N_INSNS ( 1 ) ; return true ; } case HIGH : { * total = COSTS_N_INSNS ( 0 ) ; return true ; } case LO_SUM : { * total = COSTS_N_INSNS ( 0 ) ; return true ; } case AND : { if ( GET_CODE ( XEXP ( x , 0 ) ) == NOT && GET_CODE ( XEXP ( x , 1 ) ) == NOT ) { * total = COSTS_N_INSNS ( 1 ) ; return true ; } return false ; } case MULT : { if ( ! TARGET_HAS_MUL ) * total = COSTS_N_INSNS ( 5 ) ; else if ( speed ) * total = COSTS_N_INSNS ( 2 ) ; else * total = COSTS_N_INSNS ( 1 ) ; return false ; } case DIV : { if ( ! TARGET_HAS_DIV ) * total = COSTS_N_INSNS ( 5 ) ; else if ( speed ) * total = COSTS_N_INSNS ( 2 ) ; else * total = COSTS_N_INSNS ( 1 ) ; return false ; } case ASHIFT : case ASHIFTRT : case LSHIFTRT : case ROTATE : { if ( ! speed ) * total = COSTS_N_INSNS ( 1 ) ; else * total = COSTS_N_INSNS ( 2 ) ; return false ; } case ZERO_EXTRACT : if ( TARGET_HAS_BMX ) { * total = COSTS_N_INSNS ( 1 ) ; return true ; } return false ; case SIGN_EXTEND : { if ( MEM_P ( XEXP ( x , 0 ) ) ) * total = COSTS_N_INSNS ( 1 ) ; else * total = COSTS_N_INSNS ( 3 ) ; return false ; } case MEM : { rtx addr = XEXP ( x , 0 ) ; * total = nios2_address_cost ( addr , mode , ADDR_SPACE_GENERIC , speed ) ; if ( outer_code == SET && opno == 0 ) ; else if ( outer_code == SET || outer_code == SIGN_EXTEND || outer_code == ZERO_EXTEND ) { if ( speed ) * total += COSTS_N_INSNS ( 1 ) ; } else * total += COSTS_N_INSNS ( speed ? 2 : 1 ) ; return true ; } default : return false ; } } </s>

Compute a ( partial ) cost for rtx X . Return true if the complete cost has been computed , and false if subexpressions should be scanned . In either case , * TOTAL contains the cost result .


<s> virtual void EmitInstruction ( const MCInst & Inst ) { if ( IsThumb ) EmitThumbMappingSymbol ( ) ; else EmitARMMappingSymbol ( ) ; MCELFStreamer :: EmitInstruction ( Inst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static bool support_relaxed_compatible_p ( const vector_insn_info & info1 , const vector_insn_info & info2 ) { if ( fault_first_load_p ( info1 . get_insn ( ) -> rtl ( ) ) && info2 . demand_p ( DEMAND_AVL ) && info2 . has_avl_reg ( ) && info2 . get_avl_source ( ) && info2 . get_avl_source ( ) -> insn ( ) -> is_phi ( ) ) { hash_set < set_info * > sets = get_all_sets ( info2 . get_avl_source ( ) , true , false , false ) ; for ( set_info * set : sets ) { if ( read_vl_insn_p ( set -> insn ( ) -> rtl ( ) ) ) { const insn_info * insn = get_backward_fault_first_load_insn ( set -> insn ( ) ) ; if ( insn == info1 . get_insn ( ) ) return info2 . compatible_vtype_p ( info1 ) ; } } } return false ; } </s>

Return true if the instruction support relaxed compatible check .


<s> Cpu0Subtarget & Cpu0Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { initSubtargetFeatures ( CPU , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


"Unrecognized Hexagon processor version"


<s> void F2003fInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
Register
:
OS
<<
"<register x"
;
OS
<<
getReg
(
)
<<
">"
;
break
;
case
Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> void assignValueToReg ( Register ValVReg , Register PhysReg , CCValAssign VA ) override { MIB . addUse ( PhysReg , RegState :: Implicit ) ; Register ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildCopy ( PhysReg , ExtReg ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


"\nrs6000_legitimize_address: mode %s, old code %s, "

"\nrs6000_legitimize_address: mode %s, code %s, no change:\n"

Debug version of rs6000_legitimize_address .


<s> bool SIInstrInfo :: isReallyTriviallyReMaterializable ( const MachineInstr & MI , AliasAnalysis * AA ) const { switch ( MI . getOpcode ( ) ) { case AMDGPU :: V_MOV_B32_e32 : case AMDGPU :: V_MOV_B32_e64 : case AMDGPU :: V_MOV_B64_PSEUDO : return MI . getNumOperands ( ) == MI . getDesc ( ) . getNumOperands ( ) ; default : return false ; } } </s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> static void print_slot ( rtx insn ) { final_scan_insn ( XVECEXP ( insn , 0 , 1 ) , asm_out_file , optimize , 1 , NULL ) ; INSN_DELETED_P ( XVECEXP ( insn , 0 , 1 ) ) = 1 ; } </s>

Print an instruction which would have gone into a delay slot after another instruction , but could n't because the other instruction expanded into a sequence where putting the slot insn at the end would n't work .


<s>
const
char
*
output_parallel_movb
(
rtx
*
operands
,
int
length
)
{
if
(
length
==
4
)
return
"mov%I1b,tr %1,%0,%2"
;
if
(
dbr_sequence_length
(
)
==
0
)
{
if
(
GET_CODE
(
operands
[
1
]
)
==
CONST_INT
)
return
"b %2\n\tldi %1,%0"
;
else
return
"b %2\n\tcopy %1,%0"
;
}
else
{
if
(
GET_CODE
(
operands
[
1
]
)
==
CONST_INT
)
return
"ldi %1,%0\n\tb %2"
;
else
return
"copy %1,%0\n\tb %2"
;
}
}
</s>

Output an unconditional move and branch insn .


"Should never see frame index on non-address operand"

Get the offset from the referenced frame index in the instruction , if there is one .


<s> bool enableSubRegLiveness ( ) const override { return true ; } </s>

Enable tracking of subregister liveness in register allocator .


<s> static MCInstrInfo * createMCInstrInfo ( ) { auto * X = new MCInstrInfo ( ) ; InitWebAssemblyMCInstrInfo ( X ) ; return X ; } </s>

createMCInstrInfo - Create a MCInstrInfo implementation .


<s>
int
X86FrameLowering
::
getFrameIndexReferencePreferSP
(
const
MachineFunction
&
MF
,
int
FI
,
unsigned
&
FrameReg
,
bool
IgnoreSPUpdates
)
const
{
const
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
const
uint64_t
StackSize
=
MFI
->
getStackSize
(
)
;
if
(
MFI
->
isFixedObjectIndex
(
FI
)
&&
TRI
->
needsStackRealignment
(
MF
)
&&
!
STI
.
isTargetWin64
(
)
)
return
getFrameIndexReference
(
MF
,
FI
,
FrameReg
)
;
const
TargetFrameLowering
*
TFI
=
MF
.
getSubtarget
(
)
.
getFrameLowering
(
)
;
if
(
!
IgnoreSPUpdates
&&
!
TFI
->
hasReservedCallFrame
(
MF
)
)
return
getFrameIndexReference
(
MF
,
FI
,
FrameReg
)
;
assert
(
MF
.
getInfo
<
X86MachineFunctionInfo
>
(
)
->
getTCReturnAddrDelta
(
)
>=
0
&&
"we don't handle this case!"
)
;
FrameReg
=
TRI
->
getStackRegister
(
)
;
int
Offset
=
MFI
->
getObjectOffset
(
FI
)
getOffsetOfLocalArea
(
)
;
return
Offset
+
StackSize
;
}
</s>

Same as getFrameIndexReference , except that the stack pointer ( as opposed to the frame pointer ) will be the preferred value for FrameReg .


<s>
void
relaxInstruction
(
const
MCInst
&
Inst
,
MCInst
&
Res
)
const
{
llvm_unreachable
(
"relaxInstruction() unimplemented"
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s>
static
int
rename_chain
(
tag_insn_info
*
insn_info
,
tag_map_t
&
tag_map
,
du_head_p
head
)
{
unsigned
dest_regno
=
head
->
regno
;
if
(
head
->
cannot_rename
||
head
->
renamed
)
return
1
;
HARD_REG_SET
unavailable
;
enum
reg_class
super_class
=
init_unavailable
(
insn_info
,
tag_map
,
head
,
&
unavailable
)
;
unsigned
new_regno
=
find_rename_reg
(
head
,
super_class
,
&
unavailable
,
dest_regno
,
false
)
;
if
(
new_regno
!=
dest_regno
&&
regrename_do_replace
(
head
,
new_regno
)
)
{
if
(
dump_file
&&
(
dump_flags
&
TDF_DETAILS
)
)
fprintf
(
dump_file
,
"\tInsn %d: Renamed %d to %d\n"
,
INSN_UID
(
insn_info
->
insn
)
,
dest_regno
,
new_regno
)
;
return
new_regno
;
}
return
1
;
}
</s>

Find a suitable and available register and rename the chain of occurrences of the register defined in the def/use chain headed by HEAD in which INSN exists . CUR_TAG , TAGS and TAG_MAP are used to determine which registers are unavailable due to a potential collision due to the rename . The routine returns the register number in case of a successful rename or -1 to indicate failure .


<s> SDNode * mprocDAGToDAGISel :: Select ( SDNode * Node ) { } </s>

Main hook for targets to transform nodes into machine nodes .


<s> bool AMDGPUTargetLowering :: storeOfVectorConstantIsCheap ( EVT MemVT , unsigned NumElem , unsigned AS ) const { return true ; } </s>

Return true if it is expected to be cheaper to do a store of vector constant with the given size and type for the address space than to store the individual scalar element constants .


<s> void SITargetLowering :: AdjustInstrPostInstrSelection ( MachineInstr * MI , SDNode * Node ) const { const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( getTargetMachine ( ) . getInstrInfo ( ) ) ; if ( ! TII -> isMIMG ( MI -> getOpcode ( ) ) ) return ; unsigned VReg = MI -> getOperand ( 0 ) . getReg ( ) ; unsigned Writemask = MI -> getOperand ( 1 ) . getImm ( ) ; unsigned BitsSet = 0 ; for ( unsigned i = 0 ; i < 4 ; ++ i ) BitsSet += Writemask & ( 1 << i ) ? 1 : 0 ; const TargetRegisterClass * RC ; switch ( BitsSet ) { default : return ; case 1 : RC = & AMDGPU :: VReg_32RegClass ; break ; case 2 : RC = & AMDGPU :: VReg_64RegClass ; break ; case 3 : RC = & AMDGPU :: VReg_96RegClass ; break ; } MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; MRI . setRegClass ( VReg , RC ) ; } </s>

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


"instruction requires a CPU feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> bool MandarinTargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> MCSymbol * MipsELFStreamer :: emitCFILabel ( ) { MCSymbol * Label = getContext ( ) . createTempSymbol ( "cfi" , true ) ; MCELFStreamer :: emitLabel ( Label ) ; return Label ; } </s>

When emitting an object file , create and emit a real label .


<s> static bool riscv_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { unsigned int nregs = riscv_hard_regno_nregs ( regno , mode ) ; if ( GP_REG_P ( regno ) ) { if ( ! GP_REG_P ( regno + nregs - 1 ) ) return false ; } else if ( FP_REG_P ( regno ) ) { if ( ! FP_REG_P ( regno + nregs - 1 ) ) return false ; if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && GET_MODE_CLASS ( mode ) != MODE_COMPLEX_FLOAT ) return false ; if ( GET_MODE_UNIT_SIZE ( mode ) > UNITS_PER_FP_REG || ( ! call_used_regs [ regno ] && GET_MODE_UNIT_SIZE ( mode ) > UNITS_PER_FP_ARG ) ) return false ; } else return false ; for ( unsigned i = 1 ; i < nregs ; i ++ ) if ( call_used_regs [ regno ] != call_used_regs [ regno + i ] ) return false ; return true ; } </s>


<s> const uint16_t * Cpu0RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_O32_SaveList ; } </s>


<s> bool canMergeStoresTo ( EVT MemVT ) const override { return ( MemVT . getSizeInBits ( ) <= 32 ) ; } </s>

Returns if it 's reasonable to merge stores to MemVT size .


<s> void push_back ( Value * V ) { if ( ! S . count ( V ) ) { Q . push_back ( V ) ; S . insert ( V ) ; } } </s>

Insert a node at the back ; never copies .


This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static bool can_use_cdx_ldstw ( int regno , int basereg , int offset ) { if ( CDX_REG_P ( regno ) && CDX_REG_P ( basereg ) && ( offset & 0x3 ) == 0 && offset >= 0 && offset < 0x40 ) return true ; else if ( basereg == SP_REGNO && offset >= 0 && offset < 0x80 && ( offset & 0x3 ) == 0 ) return true ; return false ; } </s>

Helper function : return true if a load/store using REGNO with address BASEREG and offset OFFSET meets the constraints for a 2-byte CDX ldw.n , stw.n , ldwsp.n , or stwsp.n instruction .


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( Size , Offset , true ) ; MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( LLT :: pointer ( 0 , DL . getPointerSizeInBits ( 0 ) ) ) ; MIRBuilder . buildFrameIndex ( AddrReg , FI ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


Returns the index for the immediate for a given instruction .


<s> MVT SITargetLowering :: getScalarShiftAmountTy ( const DataLayout & , EVT ) const { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> Instruction * visitInstruction ( Instruction & I ) { return & I ; } </s>

Specify what to return for unhandled instructions .


<s> bool GCNPassConfig :: addPreISel ( ) { AMDGPUPassConfig :: addPreISel ( ) ; if ( EnableAtomicOptimizations ) { addPass ( createAMDGPUAtomicOptimizerPass ( ) ) ; } addPass ( & AMDGPUUnifyDivergentExitNodesID ) ; if ( ! LateCFGStructurize ) { if ( EnableStructurizerWorkarounds ) { addPass ( createUnifyLoopExitsPass ( ) ) ; } addPass ( createStructurizeCFGPass ( false ) ) ; } addPass ( createSinkingPass ( ) ) ; addPass ( createAMDGPUAnnotateUniformValues ( ) ) ; if ( ! LateCFGStructurize ) { addPass ( createSIAnnotateControlFlowPass ( ) ) ; } addPass ( createLCSSAPass ( ) ) ; return false ; } </s>


<s> unsigned getMaxCallFrameSize ( ) const { return MaxCallFrameSize ; } </s>

Return the maximum size of a call frame that must be allocated for an outgoing function call .


<s>
StringRef
getPassName
(
)
const
override
{
return
"R600 Packetizer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool ARMBaseInstrInfo :: isPredicated ( const MachineInstr * MI ) const { if ( MI -> isBundle ( ) ) { MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; while ( ++ I != E && I -> isInsideBundle ( ) ) { int PIdx = I -> findFirstPredOperandIdx ( ) ; if ( PIdx != - 1 && I -> getOperand ( PIdx ) . getImm ( ) != ARMCC :: AL ) return true ; } return false ; } int PIdx = MI -> findFirstPredOperandIdx ( ) ; return PIdx != - 1 && MI -> getOperand ( PIdx ) . getImm ( ) != ARMCC :: AL ; } </s>

Returns true if the instruction is already predicated .


<s>
static
void
pa_output_function_prologue
(
FILE
*
file
,
HOST_WIDE_INT
size
ATTRIBUTE_UNUSED
)
{
ASM_OUTPUT_LABEL
(
file
,
XSTR
(
XEXP
(
DECL_RTL
(
current_function_decl
)
,
0
)
,
0
)
)
;
fputs
(
"\t.PROC\n"
,
file
)
;
fprintf
(
file
,
"\t.CALLINFO FRAME="
HOST_WIDE_INT_PRINT_DEC
,
actual_fsize
)
;
if
(
crtl
->
is_leaf
)
fputs
(
",NO_CALLS"
,
file
)
;
else
fputs
(
",CALLS"
,
file
)
;
if
(
rp_saved
)
fputs
(
",SAVE_RP"
,
file
)
;
if
(
frame_pointer_needed
)
fputs
(
",SAVE_SP"
,
file
)
;
if
(
gr_saved
)
fprintf
(
file
,
",ENTRY_GR=%d"
,
gr_saved
+
2
)
;
if
(
fr_saved
)
fprintf
(
file
,
",ENTRY_FR=%d"
,
fr_saved
+
11
)
;
fputs
(
"\n\t.ENTRY\n"
,
file
)
;
remove_useless_addtr_insns
(
0
)
;
}
</s>

On HP-PA , move-double insns between fpu and cpu need an 8-byte block of memory . If any fpu reg is used in the function , we allocate such a block here , at the bottom of the frame , just in case it 's needed . If this function is a leaf procedure , then we may choose not to do a `` save '' insn . The decision about whether or not to do this is made in regclass.c .


<s> std :: pair < unsigned , bool > lookup ( const Value * V ) const { return IDs . lookup ( V ) ; } </s>

This method finds the value with the given Name in the the symbol table .


"Blocked load and store instructions: \n"

runOnMachineFunction - Emit the function body .


<s> void s390_sched_dependencies_evaluation ( rtx_insn * head , rtx_insn * tail ) { if ( ! frame_pointer_needed || ! epilogue_completed ) return ; while ( head != tail && DEBUG_INSN_P ( head ) ) head = NEXT_INSN ( head ) ; rtx_insn * r15_restore = NULL , * r11_restore = NULL ; for ( rtx_insn * insn = tail ; insn != head ; insn = PREV_INSN ( insn ) ) { rtx set = single_set ( insn ) ; if ( ! INSN_P ( insn ) || ! RTX_FRAME_RELATED_P ( insn ) || set == NULL_RTX || ! REG_P ( SET_DEST ( set ) ) || ! FP_REG_P ( SET_SRC ( set ) ) ) continue ; if ( REGNO ( SET_DEST ( set ) ) == HARD_FRAME_POINTER_REGNUM ) r11_restore = insn ; if ( REGNO ( SET_DEST ( set ) ) == STACK_POINTER_REGNUM ) r15_restore = insn ; } if ( r11_restore == NULL || r15_restore == NULL ) return ; add_dependence ( r11_restore , r15_restore , REG_DEP_ANTI ) ; } </s>

Evaluate the insns between HEAD and TAIL and do back-end to install back-end specific dependencies . Establish an ANTI dependency between r11 and r15 restores from FPRs to prevent the instructions scheduler from reordering them since this would break CFI . No further handling in the sched_reorder hook is required since the r11 and r15 restore will never appear in the same ready list with that change .


<s> static bool thumb2_index_mul_operand ( rtx op ) { HOST_WIDE_INT val ; if ( ! CONST_INT_P ( op ) ) return false ; val = INTVAL ( op ) ; return ( val == 1 || val == 2 || val == 4 || val == 8 ) ; } </s>

Return true if OP is a valid index scaling factor for Thumb-2 address index operand . i.e . 1 , 2 , 4 or 8 .


<s> const TargetRegisterClass * PPCRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; if ( Subtarget . hasVSX ( ) ) { if ( TM . isELFv2ABI ( ) || Subtarget . isAIXABI ( ) ) { if ( Subtarget . hasP9Vector ( ) && EnableGPRToVecSpills && RC == & PPC :: G8RCRegClass ) { InflateGP8RC ++ ; return & PPC :: SPILLTOVSRRCRegClass ; } if ( RC == & PPC :: GPRCRegClass && EnableGPRToVecSpills ) InflateGPRC ++ ; } if ( RC == & PPC :: F8RCRegClass ) return & PPC :: VSFRCRegClass ; else if ( RC == & PPC :: VRRCRegClass ) return & PPC :: VSRCRegClass ; else if ( RC == & PPC :: F4RCRegClass && Subtarget . hasP8Vector ( ) ) return & PPC :: VSSRCRegClass ; } return TargetRegisterInfo :: getLargestLegalSuperClass ( RC , MF ) ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .

PowerPC PPC PPC PPC PPC::G8RCRegClass PPC::SPILLTOVSRRCRegClass PPC::GPRCRegClass PPC::F8RCRegClass PPC::VSFRCRegClass PPC::VRRCRegClass PPC::VSRCRegClass PPC::F4RCRegClass PPC::VSSRCRegClass


<s> bool SIModeRegister :: runOnMachineFunction ( MachineFunction & MF ) { BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const SIInstrInfo * TII = ST . getInstrInfo ( ) ; for ( MachineBasicBlock & BB : MF ) processBlockPhase1 ( BB , TII ) ; for ( MachineBasicBlock & BB : MF ) Phase2List . push ( & BB ) ; while ( ! Phase2List . empty ( ) ) { processBlockPhase2 ( * Phase2List . front ( ) , TII ) ; Phase2List . pop ( ) ; } for ( MachineBasicBlock & BB : MF ) processBlockPhase3 ( BB , TII ) ; BlockInfo . clear ( ) ; return Changed ; } </s>


<s>
static
void
rs6000_define_or_undefine_macro
(
bool
define_p
,
const
char
*
name
)
{
if
(
TARGET_DEBUG_BUILTIN
||
TARGET_DEBUG_TARGET
)
fprintf
(
stderr
,
"#%s %s\n"
,
(
define_p
)
"define"
:
"undef"
,
name
)
;
if
(
define_p
)
cpp_define
(
parse_in
,
name
)
;
else
cpp_undef
(
parse_in
,
name
)
;
}
</s>


<s> bool hasAndNotCompare ( SDValue ) const override { return true ; } </s>

Return true if the target should transform : ( X & Y ) == Y � ? ( ~X & Y ) == 0 ( X & Y ) ! = Y � ? ( ~X & Y ) ! = 0 .


"enabling backtrace support is only meaningful when compiling for the Thumb"

"enabling callee interworking support is only meaningful when compiling for the Thumb"

"%<-g%> with %<-mno-apcs-frame%> may not give sensible "

"cannot use %<-mtp=cp15%> with 16-bit Thumb"

"%s only supports non-pic code on M-profile targets with the "

"%s only supports non-pic code on M-profile targets"

"%s incompatible with %<-mword-relocations%>"

Check any incompatible options that the user has specified .


<s> bool X86InstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF , bool OutlineFromLinkOnceODRs ) const { const Function & F = MF . getFunction ( ) ; if ( Subtarget . getFrameLowering ( ) -> has128ByteRedZone ( MF ) ) { const X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; if ( ! X86FI || X86FI -> getUsesRedZone ( ) ) return false ; } if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) ) return false ; return true ; } </s>

Return true if the function can safely be outlined from .


<s> void MipsTargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { SDValue Res = LowerOperation ( SDValue ( N , 0 ) , DAG ) ; for ( unsigned I = 0 , E = Res -> getNumValues ( ) ; I != E ; ++ I ) Results . push_back ( Res . getValue ( I ) ) ; } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> bool isTruncateFree ( Type * SrcTy , Type * DstTy ) const override { if ( ! SrcTy -> isIntegerTy ( ) || ! DstTy -> isIntegerTy ( ) ) return false ; return SrcTy -> getPrimitiveSizeInBits ( ) == 64 && DstTy -> getPrimitiveSizeInBits ( ) == 32 ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s> void PPCMachOTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileMachO :: Initialize ( Ctx , TM ) ; LSDASection = getMachOSection ( "__TEXT" , "__gcc_except_tab" , 0 , SectionKind :: getReadOnlyWithRel ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s> void notice_update_cc ( rtx body , rtx insn ) { switch ( get_attr_cc ( insn ) ) { case CC_NONE : break ; case CC_NONE_0HIT : if ( cc_status . value1 != 0 && reg_overlap_mentioned_p ( recog_data . operand [ 0 ] , cc_status . value1 ) ) cc_status . value1 = 0 ; break ; case CC_SET_ZN : CC_STATUS_INIT ; cc_status . flags |= CC_NO_CARRY | CC_OVERFLOW_UNUSABLE ; cc_status . value1 = recog_data . operand [ 0 ] ; break ; case CC_SET_ZNV : CC_STATUS_INIT ; cc_status . flags |= CC_NO_CARRY ; cc_status . value1 = recog_data . operand [ 0 ] ; break ; case CC_COMPARE : CC_STATUS_INIT ; cc_status . value1 = SET_SRC ( body ) ; if ( GET_CODE ( cc_status . value1 ) == COMPARE && GET_MODE ( XEXP ( cc_status . value1 , 0 ) ) == SFmode ) cc_status . mdep . fpCC = 1 ; break ; case CC_CLOBBER : CC_STATUS_INIT ; break ; default : gcc_unreachable ( ) ; } } </s>

On the 68000 , all the insns to store in an address register fail to set the cc 's . However , in some cases these instructions can make it possibly invalid to use the saved cc 's . In those cases we clear out some or all of the saved cc 's so they wo n't be used .


"Instr doesn't have FrameIndex operand!"

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s> static bool extract_base_offset_in_addr ( rtx mem , rtx * base , rtx * offset ) { rtx addr ; gcc_assert ( MEM_P ( mem ) ) ; addr = XEXP ( mem , 0 ) ; if ( REG_P ( addr ) ) { * base = addr ; * offset = const0_rtx ; return true ; } if ( GET_CODE ( addr ) == PLUS && REG_P ( XEXP ( addr , 0 ) ) && CONST_INT_P ( XEXP ( addr , 1 ) ) ) { * base = XEXP ( addr , 0 ) ; * offset = XEXP ( addr , 1 ) ; return true ; } * base = NULL_RTX ; * offset = NULL_RTX ; return false ; } </s>

If MEM is in the form of `` base+offset '' , extract the two parts of address and set to BASE and OFFSET , otherwise return false after clearing BASE and OFFSET .


<s>
bool
DeadCodeElimination
::
collect
(
)
{
LiveNodes
.
clear
(
)
;
SetQueue
<
NodeId
>
WorkQ
;
for
(
NodeAddr
<
BlockNode
*
>
BA
:
DFG
.
getFunc
(
)
.
Addr
->
members
(
DFG
)
)
for
(
NodeAddr
<
InstrNode
*
>
IA
:
BA
.
Addr
->
members
(
DFG
)
)
scanInstr
(
IA
,
WorkQ
)
;
while
(
!
WorkQ
.
empty
(
)
)
{
NodeId
N
=
WorkQ
.
pop_front
(
)
;
LiveNodes
.
insert
(
N
)
;
auto
RA
=
DFG
.
addr
<
RefNode
*
>
(
N
)
;
if
(
DFG
.
IsDef
(
RA
)
)
processDef
(
RA
,
WorkQ
)
;
else
processUse
(
RA
,
WorkQ
)
;
}
if
(
trace
(
)
)
{
dbgs
(
)
<<
"Live nodes:\n"
;
for
(
NodeId
N
:
LiveNodes
)
{
auto
RA
=
DFG
.
addr
<
RefNode
*
>
(
N
)
;
dbgs
(
)
<<
PrintNode
<
RefNode
*
>
(
RA
,
DFG
)
<<
"\n"
;
}
}
auto
IsDead
=
[
this
]
(
NodeAddr
<
InstrNode
*
>
IA
)
->
bool
{
for
(
NodeAddr
<
DefNode
*
>
DA
:
IA
.
Addr
->
members_if
(
DFG
.
IsDef
,
DFG
)
)
if
(
LiveNodes
.
count
(
DA
.
Id
)
)
return
false
;
return
true
;
}
;
for
(
NodeAddr
<
BlockNode
*
>
BA
:
DFG
.
getFunc
(
)
.
Addr
->
members
(
DFG
)
)
{
for
(
NodeAddr
<
InstrNode
*
>
IA
:
BA
.
Addr
->
members
(
DFG
)
)
{
for
(
NodeAddr
<
RefNode
*
>
RA
:
IA
.
Addr
->
members
(
DFG
)
)
if
(
!
LiveNodes
.
count
(
RA
.
Id
)
)
DeadNodes
.
insert
(
RA
.
Id
)
;
if
(
DFG
.
IsCode
<
NodeAttrs
::
Stmt
>
(
IA
)
)
if
(
isLiveInstr
(
NodeAddr
<
StmtNode
*
>
(
IA
)
.
Addr
->
getCode
(
)
)
)
continue
;
if
(
IsDead
(
IA
)
)
{
DeadInstrs
.
insert
(
IA
.
Id
)
;
if
(
trace
(
)
)
dbgs
(
)
<<
"Dead instr: "
<<
PrintNode
<
InstrNode
*
>
(
IA
,
DFG
)
<<
"\n"
;
}
}
}
return
!
DeadNodes
.
empty
(
)
;
}
</s>

Analyze the given instruction MI and fill in the Uses , Defs and DeadDefs list based on the MachineOperand flags .

Hexagon
"Live nodes:\n"
"\n"
"Dead instr: "
"\n"


<s> inline machine_mode function_checker :: ret_mode ( ) const { return TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( fndecl ) ) ) ; } </s>

Return the machine_mode of the corresponding return type .


<s> static scalar_int_mode rs6000_abi_word_mode ( void ) { return TARGET_32BIT ? SImode : DImode ; } </s>

The mode the ABI uses for a word . This is not the same as word_mode for -m32 -mpowerpc64 . This is used to implement various target hooks .


<s> bool WinEHStatePass :: doFinalization ( Module & M ) { assert ( TheModule == & M ) ; TheModule = nullptr ; EHLinkRegistrationTy = nullptr ; CXXEHRegistrationTy = nullptr ; SEHRegistrationTy = nullptr ; SetJmp3 = nullptr ; CxxLongjmpUnwind = nullptr ; SehLongjmpUnwind = nullptr ; Cookie = nullptr ; return false ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> enum reg_class aarch64_regno_regclass ( unsigned regno ) { if ( GP_REGNUM_P ( regno ) ) return GENERAL_REGS ; if ( regno == SP_REGNUM ) return STACK_REG ; if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return POINTER_REGS ; if ( FP_REGNUM_P ( regno ) ) return ( FP_LO8_REGNUM_P ( regno ) ? FP_LO8_REGS : FP_LO_REGNUM_P ( regno ) ? FP_LO_REGS : FP_REGS ) ; if ( PR_REGNUM_P ( regno ) ) return PR_LO_REGNUM_P ( regno ) ? PR_LO_REGS : PR_HI_REGS ; if ( regno == FFR_REGNUM || regno == FFRT_REGNUM ) return FFR_REGS ; return NO_REGS ; } </s>


<s> static rtx aarch64_gen_store_pair ( machine_mode mode , rtx mem1 , rtx reg1 , rtx mem2 , rtx reg2 ) { switch ( mode ) { case E_DImode : return gen_store_pairdi ( mem1 , reg1 , mem2 , reg2 ) ; case E_DFmode : return gen_store_pairdf ( mem1 , reg1 , mem2 , reg2 ) ; default : gcc_unreachable ( ) ; } } </s>

Generate and return a store pair instruction of mode MODE to store register REG1 to MEM1 and register REG2 to MEM2 .


<s>
void
Thumb1InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
ARMSubtarget
&
st
=
MF
.
getSubtarget
<
ARMSubtarget
>
(
)
;
assert
(
ARM
::
GPRRegClass
.
contains
(
DestReg
,
SrcReg
)
&&
"Thumb1 can only copy GPR registers"
)
;
if
(
st
.
hasV6Ops
(
)
||
ARM
::
hGPRRegClass
.
contains
(
SrcReg
)
||
!
ARM
::
tGPRRegClass
.
contains
(
DestReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tMOVr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
else
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tPUSH
)
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tPOP
)
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
.
addReg
(
DestReg
,
getDefRegState
(
true
)
)
;
}
}
</s>

ARM
ARM
ARM
ARM::GPRRegClass
"Thumb1 can only copy GPR registers"
ARM::hGPRRegClass
ARM::tGPRRegClass
ARM::tMOVr
ARMCC::AL
ARM::tPUSH
ARMCC::AL
ARM::tPOP
ARMCC::AL


<s>
static
void
*
cygwin_gt_pch_get_address
(
size_t
sz
,
int
fd
)
{
void
*
base
;
off_t
p
=
lseek
(
fd
,
0
,
SEEK_CUR
)
;
if
(
p
==
(
off_t
)
1
)
fatal_error
(
input_location
,
"cannot get position in PCH file: %m"
)
;
if
(
(
size_t
)
p
<
sz
)
{
if
(
ftruncate
(
fd
,
sz
)
==
1
)
fatal_error
(
input_location
,
"cannot extend PCH file: %m"
)
;
}
base
=
mmap
(
,
sz
,
PROT_READ
|
PROT_WRITE
,
MAP_PRIVATE
,
fd
,
0
)
;
if
(
base
==
MAP_FAILED
)
base
=
;
else
munmap
(
base
,
sz
)
;
if
(
lseek
(
fd
,
p
,
SEEK_SET
)
==
(
off_t
)
1
)
fatal_error
(
input_location
,
"cannot set position in PCH file: %m"
)
;
return
base
;
}
</s>

Identify an address that 's likely to be free in a subsequent invocation of the compiler . The area should be able to hold SIZE bytes . FD is an open file descriptor if the host would like to probe with mmap .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


"***** Machine Function before Domain Reassignment *****\n"

"***** Machine Function after Domain Reassignment *****\n"

runOnMachineFunction - Emit the function body .


<s> void MetadataStreamerV4 :: begin ( const Module & Mod , const IsaInfo :: AMDGPUTargetID & TargetID ) { emitVersion ( ) ; emitTargetID ( TargetID ) ; emitPrintf ( Mod ) ; getRootMetadata ( "amdhsa.kernels" ) = HSAMetadataDoc -> getArrayNode ( ) ; } </s>


<s> static int arm_sched_reorder ( FILE * file , int verbose , rtx_insn * * ready , int * n_readyp , int clock ) { switch ( arm_tune ) { case cortexa7 : cortexa7_sched_reorder ( file , verbose , ready , n_readyp , clock ) ; break ; default : break ; } return arm_issue_rate ( ) ; } </s>


<s>
char
*
output_cbranch
(
rtx
op
,
const
char
*
label
,
int
reversed
,
rtx_insn
*
insn
)
{
static
char
string
[
64
]
;
enum
rtx_code
code
=
GET_CODE
(
op
)
;
rtx
cc_reg
=
XEXP
(
op
,
0
)
;
machine_mode
mode
=
GET_MODE
(
cc_reg
)
;
int
cc_regno
=
REGNO
(
cc_reg
)
CR0_REGNO
;
int
need_longbranch
=
label
!=
&&
get_attr_length
(
insn
)
==
8
;
int
really_reversed
=
reversed
^
need_longbranch
;
char
*
s
=
string
;
const
char
*
ccode
;
const
char
*
pred
;
rtx
note
;
validate_condition_mode
(
code
,
mode
)
;
if
(
really_reversed
)
{
if
(
mode
==
CCFPmode
)
code
=
reverse_condition_maybe_unordered
(
code
)
;
else
code
=
reverse_condition
(
code
)
;
}
if
(
(
!
TARGET_FPRS
&&
TARGET_HARD_FLOAT
)
&&
mode
==
CCFPmode
)
{
switch
(
code
)
{
case
EQ
:
code
=
GT
;
break
;
case
NE
:
code
=
UNLE
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
switch
(
code
)
{
case
NE
:
case
LTGT
:
ccode
=
"ne"
;
break
;
case
EQ
:
case
UNEQ
:
ccode
=
"eq"
;
break
;
case
GE
:
case
GEU
:
ccode
=
"ge"
;
break
;
case
GT
:
case
GTU
:
case
UNGT
:
ccode
=
"gt"
;
break
;
case
LE
:
case
LEU
:
ccode
=
"le"
;
break
;
case
LT
:
case
LTU
:
case
UNLT
:
ccode
=
"lt"
;
break
;
case
UNORDERED
:
ccode
=
"un"
;
break
;
case
ORDERED
:
ccode
=
"nu"
;
break
;
case
UNGE
:
ccode
=
"nl"
;
break
;
case
UNLE
:
ccode
=
"ng"
;
break
;
default
:
gcc_unreachable
(
)
;
}
pred
=
""
;
note
=
find_reg_note
(
insn
,
REG_BR_PROB
,
NULL_RTX
)
;
if
(
note
!=
NULL_RTX
)
{
int
prob
=
XINT
(
note
,
0
)
REG_BR_PROB_BASE
/
2
;
if
(
rs6000_always_hint
||
(
abs
(
prob
)
>
REG_BR_PROB_BASE
/
100
*
48
&&
br_prob_note_reliable_p
(
note
)
)
)
{
if
(
abs
(
prob
)
>
REG_BR_PROB_BASE
/
20
&&
(
(
prob
>
0
)
^
need_longbranch
)
)
pred
=
"+"
;
else
pred
=
"-"
;
}
}
if
(
label
==
)
s
+=
sprintf
(
s
,
"b%slr%s "
,
ccode
,
pred
)
;
else
s
+=
sprintf
(
s
,
"b%s%s "
,
ccode
,
pred
)
;
if
(
reg_names
[
cc_regno
+
CR0_REGNO
]
[
0
]
==
'%'
)
*
s
++
=
'%'
;
s
+=
sprintf
(
s
,
"%s"
,
reg_names
[
cc_regno
+
CR0_REGNO
]
)
;
if
(
label
!=
)
{
if
(
need_longbranch
)
s
+=
sprintf
(
s
,
",$+8\n\tb %s"
,
label
)
;
else
s
+=
sprintf
(
s
,
",%s"
,
label
)
;
}
return
string
;
}
</s>

Output a conditional branch to LABEL . CODE is the comparison code . CC_MODE is the mode of the CC register . REVERSED is non-zero if we should reverse the sense of the comparison . INSN is the instruction .


<s> static int getRegClass ( RegisterKind Is , unsigned RegWidth ) { if ( Is == IS_VGPR ) { switch ( RegWidth ) { default : return - 1 ; case 1 : return AMDGPU :: VGPR_32RegClassID ; case 2 : return AMDGPU :: VReg_64RegClassID ; case 3 : return AMDGPU :: VReg_96RegClassID ; case 4 : return AMDGPU :: VReg_128RegClassID ; case 8 : return AMDGPU :: VReg_256RegClassID ; case 16 : return AMDGPU :: VReg_512RegClassID ; } } else if ( Is == IS_TTMP ) { switch ( RegWidth ) { default : return - 1 ; case 1 : return AMDGPU :: TTMP_32RegClassID ; case 2 : return AMDGPU :: TTMP_64RegClassID ; case 4 : return AMDGPU :: TTMP_128RegClassID ; } } else if ( Is == IS_SGPR ) { switch ( RegWidth ) { default : return - 1 ; case 1 : return AMDGPU :: SGPR_32RegClassID ; case 2 : return AMDGPU :: SGPR_64RegClassID ; case 4 : return AMDGPU :: SGPR_128RegClassID ; case 8 : return AMDGPU :: SReg_256RegClassID ; case 16 : return AMDGPU :: SReg_512RegClassID ; } } return - 1 ; } </s>

Given a machine instruction descriptor , returns the register class constraint for OpNum , or NULL .


<s> std :: string BTFTypeStruct :: getName ( ) { return std :: string ( STy -> getName ( ) ) ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> SDValue AArch64TargetLowering :: getSqrtEstimate ( SDValue Operand , SelectionDAG & DAG , int Enabled , int & ExtraSteps , bool & UseOneConst , bool Reciprocal ) const { if ( Enabled == ReciprocalEstimate :: Enabled || ( Enabled == ReciprocalEstimate :: Unspecified && Subtarget -> useRSqrt ( ) ) ) if ( SDValue Estimate = getEstimate ( Subtarget , AArch64ISD :: FRSQRTE , Operand , DAG , ExtraSteps ) ) { SDLoc DL ( Operand ) ; EVT VT = Operand . getValueType ( ) ; SDNodeFlags Flags ; Flags . setAllowReassociation ( true ) ; for ( int i = ExtraSteps ; i > 0 ; -- i ) { SDValue Step = DAG . getNode ( ISD :: FMUL , DL , VT , Estimate , Estimate , Flags ) ; Step = DAG . getNode ( AArch64ISD :: FRSQRTS , DL , VT , Operand , Step , Flags ) ; Estimate = DAG . getNode ( ISD :: FMUL , DL , VT , Estimate , Step , Flags ) ; } if ( ! Reciprocal ) { EVT CCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue FPZero = DAG . getConstantFP ( 0.0 , DL , VT ) ; SDValue Eq = DAG . getSetCC ( DL , CCVT , Operand , FPZero , ISD :: SETEQ ) ; Estimate = DAG . getNode ( ISD :: FMUL , DL , VT , Operand , Estimate , Flags ) ; Estimate = DAG . getNode ( VT . isVector ( ) ? ISD :: VSELECT : ISD :: SELECT , DL , VT , Eq , Operand , Estimate ) ; } ExtraSteps = 0 ; return Estimate ; } return SDValue ( ) ; } </s>

Hooks for building estimates in place of slower divisions and square roots .


<s> bool DLXInstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Condition ) const { return false ; } </s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> static rtx gen_compare_reg_1 ( enum rtx_code code , rtx x , rtx y ) { machine_mode mode ; rtx cc_reg ; if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_CC ) return x ; mode = SELECT_CC_MODE ( code , x , y ) ; if ( TARGET_V9 && GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) { int reg ; static int next_fcc_reg = 0 ; static rtx prev_args [ 4 ] [ 2 ] ; for ( reg = 0 ; reg < 4 ; reg ++ ) if ( prev_args [ reg ] [ 0 ] == x && prev_args [ reg ] [ 1 ] == y ) break ; if ( reg == 4 ) { reg = next_fcc_reg ; prev_args [ reg ] [ 0 ] = x ; prev_args [ reg ] [ 1 ] = y ; next_fcc_reg = ( next_fcc_reg + 1 ) & 3 ; } cc_reg = gen_rtx_REG ( mode , reg + SPARC_FIRST_V9_FCC_REG ) ; } cc_reg = gen_reg_rtx ( mode ) ; else if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) cc_reg = gen_rtx_REG ( mode , SPARC_FCC_REG ) ; else cc_reg = gen_rtx_REG ( mode , SPARC_ICC_REG ) ; emit_insn ( gen_rtx_SET ( cc_reg , gen_rtx_COMPARE ( mode , x , y ) ) ) ; return cc_reg ; } </s>

Emit the compare insn and return the CC reg for a CODE comparison with operands X and Y .


<s> bool isImm ( ) const override { return Kind == k_Immediate ; } </s>


<s>
bool
SIRegisterInfo
::
eliminateSGPRToVGPRSpillFrameIndex
(
MachineBasicBlock
::
iterator
MI
,
int
FI
,
RegScavenger
*
RS
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
case
AMDGPU
::
SI_SPILL_S512_SAVE
:
case
AMDGPU
::
SI_SPILL_S256_SAVE
:
case
AMDGPU
::
SI_SPILL_S160_SAVE
:
case
AMDGPU
::
SI_SPILL_S128_SAVE
:
case
AMDGPU
::
SI_SPILL_S96_SAVE
:
case
AMDGPU
::
SI_SPILL_S64_SAVE
:
case
AMDGPU
::
SI_SPILL_S32_SAVE
:
return
spillSGPR
(
MI
,
FI
,
RS
,
true
)
;
case
AMDGPU
::
SI_SPILL_S512_RESTORE
:
case
AMDGPU
::
SI_SPILL_S256_RESTORE
:
case
AMDGPU
::
SI_SPILL_S160_RESTORE
:
case
AMDGPU
::
SI_SPILL_S128_RESTORE
:
case
AMDGPU
::
SI_SPILL_S96_RESTORE
:
case
AMDGPU
::
SI_SPILL_S64_RESTORE
:
case
AMDGPU
::
SI_SPILL_S32_RESTORE
:
return
restoreSGPR
(
MI
,
FI
,
RS
,
true
)
;
default
:
llvm_unreachable
(
"not an SGPR spill instruction"
)
;
}
}
</s>


"Alignment not a multiple of the instruction size:"

Write an ( optimal ) nop sequence of Count bytes to the given output .


"Unknown opcode to check as cheap as a move!"

Return true if the instruction is as cheap as a move instruction .


<s> rtx arc_regno_use_in ( unsigned int regno , rtx x ) { const char * fmt ; int i , j ; rtx tem ; if ( REG_P ( x ) && refers_to_regno_p ( regno , x ) ) return x ; fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'e' ) { if ( ( tem = regno_use_in ( regno , XEXP ( x , i ) ) ) ) return tem ; } else if ( fmt [ i ] == 'E' ) for ( j = XVECLEN ( x , i ) - 1 ; j >= 0 ; j -- ) if ( ( tem = regno_use_in ( regno , XVECEXP ( x , i , j ) ) ) ) return tem ; } return NULL_RTX ; } </s>

Searches X for any reference to REGNO , returning the rtx of the reference found if any . Otherwise , returns NULL_RTX .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Mips Hazard Schedule"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static rtx nios2_expand_builtin ( tree exp , rtx target , rtx subtarget ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , int ignore ATTRIBUTE_UNUSED ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , 0 ) ; unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; if ( fcode < nios2_fpu_builtin_base ) { const struct nios2_builtin_desc * d = & nios2_builtins [ fcode ] ; switch ( fcode ) { case NIOS2_BUILTIN_sync : emit_insn ( gen_sync ( ) ) ; return const0_rtx ; case NIOS2_BUILTIN_ldbio : case NIOS2_BUILTIN_ldbuio : case NIOS2_BUILTIN_ldhio : case NIOS2_BUILTIN_ldhuio : case NIOS2_BUILTIN_ldwio : case NIOS2_BUILTIN_stbio : case NIOS2_BUILTIN_sthio : case NIOS2_BUILTIN_stwio : return nios2_expand_ldstio_builtin ( exp , target , d ) ; case NIOS2_BUILTIN_rdctl : case NIOS2_BUILTIN_wrctl : return nios2_expand_rdwrctl_builtin ( exp , target , d ) ; default : gcc_unreachable ( ) ; } } else if ( fcode < nios2_custom_builtin_base ) return nios2_expand_fpu_builtin ( exp , fcode - nios2_fpu_builtin_base , target ) ; else if ( fcode < nios2_custom_builtin_end ) return nios2_expand_custom_builtin ( exp , fcode - nios2_custom_builtin_base , target ) ; else gcc_unreachable ( ) ; } </s>

Implement TARGET_EXPAND_BUILTIN . Expand an expression EXP that calls a built-in function , with result going to TARGET if that 's convenient ( and in mode MODE if that 's convenient ) . SUBTARGET may be used as the target for computing one of EXP 's operands . IGNORE is nonzero if the value is to be ignored .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"ARM Assembly Printer"
;
}
</s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 Partial Reduction"
;
}
</s>


<s> void SystemZAsmPrinter :: emitFunctionBodyEnd ( ) { if ( TM . getTargetTriple ( ) . isOSzOS ( ) ) { MCSymbol * FnEndSym = createTempSymbol ( "func_end" ) ; OutStreamer -> emitLabel ( FnEndSym ) ; OutStreamer -> PushSection ( ) ; OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getPPA1Section ( ) ) ; emitPPA1 ( FnEndSym ) ; OutStreamer -> PopSection ( ) ; CurrentFnPPA1Sym = nullptr ; CurrentFnEPMarkerSym = nullptr ; } } </s>

Targets can override this to emit stuff after the last basic block in the function .


<s> bool AMDGPURewriteOutArguments :: doInitialization ( Module & M ) { DL = & M . getDataLayout ( ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> bool isMem ( ) const override { return false ; } </s>


<s> bool PatmosFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * TM . getInstrInfo ( ) ; PatmosMachineFunctionInfo & PMFI = * MF . getInfo < PatmosMachineFunctionInfo > ( ) ; if ( hasFP ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( Patmos :: MOV ) , Patmos :: RSP ) ) . addReg ( Patmos :: RFP ) ; } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; unsigned tmpReg = Reg ; if ( Patmos :: PRegsRegClass . contains ( Reg ) ) continue ; if ( Reg == Patmos :: S0 && PMFI . getS0SpillReg ( ) ) { TII . copyPhysReg ( MBB , MI , DL , Reg , PMFI . getS0SpillReg ( ) , true ) ; prior ( MI ) -> setFlag ( MachineInstr :: FrameSetup ) ; continue ; } if ( Patmos :: SRegsRegClass . contains ( Reg ) ) tmpReg = Patmos :: R9 ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( tmpReg ) ; TII . loadRegFromStackSlot ( MBB , MI , tmpReg , CSI [ i - 1 ] . getFrameIdx ( ) , RC , TRI ) ; prior ( MI ) -> setFlag ( MachineInstr :: FrameSetup ) ; if ( tmpReg != Reg ) { TII . copyPhysReg ( MBB , MI , DL , Reg , tmpReg , true ) ; prior ( MI ) -> setFlag ( MachineInstr :: FrameSetup ) ; } } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> int lm32_expand_block_move ( rtx * operands ) { if ( ( GET_CODE ( operands [ 2 ] ) == CONST_INT ) && ( INTVAL ( operands [ 2 ] ) <= 32 ) ) { lm32_block_move_inline ( operands [ 0 ] , operands [ 1 ] , INTVAL ( operands [ 2 ] ) , INTVAL ( operands [ 3 ] ) ) ; return 1 ; } return 0 ; } </s>

Expand string/block move operations . operands [ 0 ] is the pointer to the destination . operands [ 1 ] is the pointer to the source . operands [ 2 ] is the number of bytes to move . operands [ 3 ] is the alignment .


<s> Optional < Value * > X86TTIImpl :: simplifyDemandedUseBitsIntrinsic ( InstCombiner & IC , IntrinsicInst & II , APInt DemandedMask , KnownBits & Known , bool & KnownBitsComputed ) const { switch ( II . getIntrinsicID ( ) ) { default : break ; case Intrinsic :: x86_mmx_pmovmskb : case Intrinsic :: x86_sse_movmsk_ps : case Intrinsic :: x86_sse2_movmsk_pd : case Intrinsic :: x86_sse2_pmovmskb_128 : case Intrinsic :: x86_avx_movmsk_ps_256 : case Intrinsic :: x86_avx_movmsk_pd_256 : case Intrinsic :: x86_avx2_pmovmskb : { unsigned ArgWidth ; if ( II . getIntrinsicID ( ) == Intrinsic :: x86_mmx_pmovmskb ) { ArgWidth = 8 ; } else { auto Arg = II . getArgOperand ( 0 ) ; auto ArgType = cast < FixedVectorType > ( Arg -> getType ( ) ) ; ArgWidth = ArgType -> getNumElements ( ) ; } APInt DemandedElts = DemandedMask . zextOrTrunc ( ArgWidth ) ; Type * VTy = II . getType ( ) ; if ( DemandedElts . isNullValue ( ) ) { return ConstantInt :: getNullValue ( VTy ) ; } Known . Zero . setBitsFrom ( ArgWidth ) ; KnownBitsComputed = true ; break ; } } return None ; } </s>

Can be used to implement target-specific instruction combining .


<s>
bool
AVRFrameLowering
::
spillCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
if
(
CSI
.
empty
(
)
)
{
return
false
;
}
unsigned
CalleeFrameSize
=
0
;
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
AVRSubtarget
&
STI
=
MF
.
getSubtarget
<
AVRSubtarget
>
(
)
;
const
TargetInstrInfo
&
TII
=
*
STI
.
getInstrInfo
(
)
;
AVRMachineFunctionInfo
*
AVRFI
=
MF
.
getInfo
<
AVRMachineFunctionInfo
>
(
)
;
for
(
unsigned
i
=
CSI
.
size
(
)
;
i
!=
0
;
i
)
{
unsigned
Reg
=
CSI
[
i
1
]
.
getReg
(
)
;
bool
IsNotLiveIn
=
!
MBB
.
isLiveIn
(
Reg
)
;
assert
(
TRI
->
getRegSizeInBits
(
*
TRI
->
getMinimalPhysRegClass
(
Reg
)
)
==
8
&&
"Invalid register size"
)
;
if
(
IsNotLiveIn
)
{
MBB
.
addLiveIn
(
Reg
)
;
}
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
PUSHRr
)
)
.
addReg
(
Reg
,
getKillRegState
(
IsNotLiveIn
)
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
++
CalleeFrameSize
;
}
AVRFI
->
setCalleeSavedFrameSize
(
CalleeFrameSize
)
;
return
true
;
}
</s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .

AVR
AVR
0
AVR
AVR
AVR
AVR
AVR
0
1
8
"Invalid register size"
AVR::PUSHRr
AVR


<s>
char
*
aarch64_output_sve_ptrues
(
rtx
const_unspec
)
{
static
char
templ
[
40
]
;
struct
simd_immediate_info
info
;
bool
is_valid
=
aarch64_simd_valid_immediate
(
const_unspec
,
&
info
)
;
gcc_assert
(
is_valid
&&
info
.
insn
==
simd_immediate_info
::
PTRUE
)
;
char
element_char
=
sizetochar
(
GET_MODE_BITSIZE
(
info
.
elt_mode
)
)
;
snprintf
(
templ
,
sizeof
(
templ
)
,
"ptrues\t%%0.%c, %s"
,
element_char
,
svpattern_token
(
info
.
u
.
pattern
)
)
;
return
templ
;
}
</s>

Return the asm template for a PTRUES . CONST_UNSPEC is the aarch64_sve_ptrue_svpattern_immediate that describes the predicate pattern .


<s> static void ATTRIBUTE_UNUSED mips_output_dwarf_dtprel ( FILE * file , int size , rtx x ) { switch ( size ) { case 4 : fputs ( "\t.dtprelword\t" , file ) ; break ; case 8 : fputs ( "\t.dtpreldword\t" , file ) ; break ; default : gcc_unreachable ( ) ; } output_addr_const ( file , x ) ; fputs ( "+0x8000" , file ) ; } </s>


<s> TargetIRAnalysis ARCTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( const Function & F ) { return TargetTransformInfo ( ARCTTIImpl ( this , F ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


<s> bool X86TargetLowering :: decomposeMulByConstant ( EVT VT , SDValue C ) const { APInt MulC ; if ( ! ISD :: isConstantSplatVector ( C . getNode ( ) , MulC ) ) return false ; if ( isOperationLegal ( ISD :: MUL , VT ) ) return false ; return ( MulC + 1 ) . isPowerOf2 ( ) || ( MulC - 1 ) . isPowerOf2 ( ) ; } </s>

Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds .


<s>
Register
getStackAddress
(
uint64_t
Size
,
int64_t
Offset
,
MachinePointerInfo
&
MPO
)
override
{
assert
(
(
Size
==
1
||
Size
==
2
||
Size
==
4
||
Size
==
8
)
&&
"Unsupported size"
)
;
auto
&
MFI
=
MIRBuilder
.
getMF
(
)
.
getFrameInfo
(
)
;
int
FI
=
MFI
.
CreateFixedObject
(
Size
,
Offset
,
true
)
;
MPO
=
MachinePointerInfo
::
getFixedStack
(
MIRBuilder
.
getMF
(
)
,
FI
)
;
unsigned
AddrReg
=
MRI
.
createGenericVirtualRegister
(
LLT
::
pointer
(
MPO
.
getAddrSpace
(
)
,
32
)
)
;
MIRBuilder
.
buildFrameIndex
(
AddrReg
,
FI
)
;
return
AddrReg
;
}
</s>

Materialize a VReg containing the address of the specified stack-based object .


<s> ScheduleDAGInstrs * GCNPassConfig :: createMachineScheduler ( MachineSchedContext * C ) const { const GCNSubtarget & ST = C -> MF -> getSubtarget < GCNSubtarget > ( ) ; if ( ST . enableSIScheduler ( ) ) return createSIMachineScheduler ( C ) ; return createGCNMaxOccupancyMachineScheduler ( C ) ; } </s>

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level .


<s> Optional < Value * > ARMTTIImpl :: simplifyDemandedVectorEltsIntrinsic ( InstCombiner & IC , IntrinsicInst & II , APInt OrigDemandedElts , APInt & UndefElts , APInt & UndefElts2 , APInt & UndefElts3 , std :: function < void ( Instruction * , unsigned , APInt , APInt & ) > SimplifyAndSetOp ) const { auto SimplifyNarrowInstrTopBottom = [ & ] ( unsigned TopOpc ) { unsigned NumElts = cast < FixedVectorType > ( II . getType ( ) ) -> getNumElements ( ) ; unsigned IsTop = cast < ConstantInt > ( II . getOperand ( TopOpc ) ) -> getZExtValue ( ) ; APInt DemandedElts = APInt :: getSplat ( NumElts , IsTop ? APInt :: getLowBitsSet ( 2 , 1 ) : APInt :: getHighBitsSet ( 2 , 1 ) ) ; SimplifyAndSetOp ( & II , 0 , OrigDemandedElts & DemandedElts , UndefElts ) ; UndefElts &= APInt :: getSplat ( NumElts , ! IsTop ? APInt :: getLowBitsSet ( 2 , 1 ) : APInt :: getHighBitsSet ( 2 , 1 ) ) ; return None ; } ; switch ( II . getIntrinsicID ( ) ) { default : break ; case Intrinsic :: arm_mve_vcvt_narrow : SimplifyNarrowInstrTopBottom ( 2 ) ; break ; case Intrinsic :: arm_mve_vqmovn : SimplifyNarrowInstrTopBottom ( 4 ) ; break ; case Intrinsic :: arm_mve_vshrn : SimplifyNarrowInstrTopBottom ( 7 ) ; break ; } return None ; } </s>


<s> unsigned MipsAsmParser :: checkTargetMatchPredicate ( MCInst & Inst ) { return Match_Success ; } </s>

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


<s> void SystemZFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo * MFFrame = MF . getFrameInfo ( ) ; uint64_t MaxReach = ( MFFrame -> estimateStackSize ( MF ) + SystemZMC :: CallFrameSize * 2 ) ; if ( ! isUInt < 12 > ( MaxReach ) ) { RS -> addScavengingFrameIndex ( MFFrame -> CreateStackObject ( 8 , 8 , false ) ) ; RS -> addScavengingFrameIndex ( MFFrame -> CreateStackObject ( 8 , 8 , false ) ) ; } } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


More limited version of SimplifyDemandedBits that can be used to `` look through '' ops that do n't contribute to the DemandedBits/DemandedElts - bitwise ops etc .


<s> rtl_opt_pass * make_pass_fma_steering ( gcc :: context * ctxt ) { return new pass_fma_steering ( ctxt ) ; } </s>

Create a new fma steering pass instance .


<s> rtx mips_gen_const_int_vector ( machine_mode mode , HOST_WIDE_INT val ) { rtx c = gen_int_mode ( val , GET_MODE_INNER ( mode ) ) ; return gen_const_vec_duplicate ( mode , c ) ; } </s>

Return a const_int vector of VAL with mode MODE .


<s> bool SIInstrInfo :: findCommutedOpIndices ( MachineInstr * MI , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( ! MCID . isCommutable ( ) ) return false ; unsigned Opc = MI -> getOpcode ( ) ; int Src0Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src0 ) ; if ( Src0Idx == - 1 ) return false ; if ( ! MI -> getOperand ( Src0Idx ) . isReg ( ) ) return false ; int Src1Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src1 ) ; if ( Src1Idx == - 1 ) return false ; if ( ! MI -> getOperand ( Src1Idx ) . isReg ( ) ) return false ; if ( hasModifiersSet ( * MI , AMDGPU :: OpName :: src0_modifiers ) || hasModifiersSet ( * MI , AMDGPU :: OpName :: src1_modifiers ) ) return false ; SrcOpIdx1 = Src0Idx ; SrcOpIdx2 = Src1Idx ; return true ; } </s>

Returns true iff the routine could find two commutable operands in the given machine instruction .

AMDGPU SI AMDGPU::getNamedOperandIdx AMDGPU::OpName 1 AMDGPU::getNamedOperandIdx AMDGPU::OpName 1 AMDGPU::OpName AMDGPU::OpName


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : LLVMTargetMachine ( T , TT ) , DataLayout ( "E-p:32:32-f128:128:128" ) , Subtarget ( TT , FS ) , TLInfo ( * this ) , InstrInfo ( Subtarget ) , FrameInfo ( TargetFrameInfo :: StackGrowsDown , 8 , 0 ) { } </s>


<s>
LLVM_DUMP_METHOD
void
GCNRegPressure
::
print
(
raw_ostream
&
OS
,
const
GCNSubtarget
*
ST
)
const
{
OS
<<
"VGPRs: "
<<
getVGPRNum
(
)
;
if
(
ST
)
OS
<<
"(O"
<<
ST
->
getOccupancyWithNumVGPRs
(
getVGPRNum
(
)
)
<<
')'
;
OS
<<
", SGPRs: "
<<
getSGPRNum
(
)
;
if
(
ST
)
OS
<<
"(O"
<<
ST
->
getOccupancyWithNumSGPRs
(
getSGPRNum
(
)
)
<<
')'
;
OS
<<
", LVGPR WT: "
<<
getVGPRTuplesWeight
(
)
<<
", LSGPR WT: "
<<
getSGPRTuplesWeight
(
)
;
if
(
ST
)
OS
<<
" -> Occ: "
<<
getOccupancy
(
*
ST
)
;
OS
<<
'\n'
;
}
</s>

print - Print a debug representation of the operand to the given stream .

AMDGPU
"VGPRs: "
"(O"
", SGPRs: "
"(O"
", LVGPR WT: "
", LSGPR WT: "
" -> Occ: "


<s> SDValue TLCS900TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_TLCS900 ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static bool s390_handle_arch_option ( const char * arg , enum processor_type * type , enum processor_flags * flags ) { static struct pta { const char * const name ; const enum processor_type processor ; const enum processor_flags flags ; } const processor_alias_table [ ] = { { "g5" , PROCESSOR_9672_G5 , PF_IEEE_FLOAT } , { "g6" , PROCESSOR_9672_G6 , PF_IEEE_FLOAT } , { "z900" , PROCESSOR_2064_Z900 , PF_IEEE_FLOAT | PF_ZARCH } , { "z990" , PROCESSOR_2084_Z990 , PF_IEEE_FLOAT | PF_ZARCH | PF_LONG_DISPLACEMENT } , { "z9-109" , PROCESSOR_2094_Z9_109 , PF_IEEE_FLOAT | PF_ZARCH | PF_LONG_DISPLACEMENT | PF_EXTIMM } , } ; size_t i ; for ( i = 0 ; i < ARRAY_SIZE ( processor_alias_table ) ; i ++ ) if ( strcmp ( arg , processor_alias_table [ i ] . name ) == 0 ) { * type = processor_alias_table [ i ] . processor ; * flags = processor_alias_table [ i ] . flags ; return true ; } return false ; } </s>

Return true if ARG is the name of a processor . Set * TYPE and * FLAGS to the associated processor_type and processor_flags if so .


Hook to validate the current # pragma GCC target and set the state , and update the macros based on what was changed . If ARGS is NULL , then POP_TARGET is used to reset the options .


<s> DecodeStatus HexagonDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & os , raw_ostream & cs ) const { DecodeStatus Result = DecodeStatus :: Success ; bool Complete = false ; Size = 0 ; * CurrentBundle = & MI ; MI . clear ( ) ; MI . setOpcode ( Hexagon :: BUNDLE ) ; MI . addOperand ( MCOperand :: createImm ( 0 ) ) ; while ( Result == Success && Complete == false ) { if ( Bytes . size ( ) < HEXAGON_INSTR_SIZE ) return MCDisassembler :: Fail ; MCInst * Inst = new ( getContext ( ) ) MCInst ; Result = getSingleInstruction ( * Inst , MI , Bytes , Address , os , cs , Complete ) ; MI . addOperand ( MCOperand :: createInst ( Inst ) ) ; Size += HEXAGON_INSTR_SIZE ; Bytes = Bytes . slice ( HEXAGON_INSTR_SIZE ) ; } return Result ; } </s>

Returns the disassembly of a single instruction .


<s> const_iterator end ( ) const { return m_SectToExData . end ( ) ; } </s>

Get a const_iterator to the end of the symbol table .


<s> TargetLowering :: AtomicExpansionKind AArch64TargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return Size <= 128 ? AtomicExpansionKind :: LLSC : AtomicExpansionKind :: None ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> rtx visium_eh_return_handler_rtx ( void ) { rtx mem = gen_frame_mem ( SImode , plus_constant ( Pmode , hard_frame_pointer_rtx , 4 ) ) ; MEM_VOLATILE_P ( mem ) = 1 ; return mem ; } </s>

Helper function for EH_RETURN_HANDLER_RTX . Return the RTX representing a location in which to store the address of an exception handler to which we should return .


<s> static void ignore_all_aliases ( HARD_REG_SET * unavailable , machine_mode mode , unsigned reg ) { add_to_hard_reg_set ( unavailable , mode , reg ) ; add_to_hard_reg_set ( unavailable , mode , reg + 16 ) ; add_to_hard_reg_set ( unavailable , mode , reg + 32 ) ; add_to_hard_reg_set ( unavailable , mode , reg + 48 ) ; } </s>

Add all aliases of the register to the unavailable register set . REG is the smallest register number that can then be used to reference its aliases . UNAVAILABLE is the hard register set to add the ignored register numbers to and MODE is the mode in which the registers would have been used .


<s> bool VETargetLowering :: hasAndNot ( SDValue Y ) const { EVT VT = Y . getValueType ( ) ; if ( VT . isVector ( ) ) return false ; if ( auto * C = dyn_cast < ConstantSDNode > ( Y ) ) return false ; return true ; } </s>

Return true if the target has a bitwise and-not operation : X = ~A & B This can be used to simplify select or other instructions .


<s> void X86InstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , unsigned SubIdx , const MachineInstr * Orig , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( I ) ; if ( SubIdx && TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) { DestReg = TRI -> getSubReg ( DestReg , SubIdx ) ; SubIdx = 0 ; } bool Clone = true ; unsigned Opc = Orig -> getOpcode ( ) ; switch ( Opc ) { default : break ; case X86 :: MOV8r0 : case X86 :: MOV16r0 : case X86 :: MOV32r0 : case X86 :: MOV64r0 : { if ( ! isSafeToClobberEFLAGS ( MBB , I ) ) { switch ( Opc ) { default : break ; case X86 :: MOV8r0 : Opc = X86 :: MOV8ri ; break ; case X86 :: MOV16r0 : Opc = X86 :: MOV16ri ; break ; case X86 :: MOV32r0 : Opc = X86 :: MOV32ri ; break ; case X86 :: MOV64r0 : Opc = X86 :: MOV64ri64i32 ; break ; } Clone = false ; } break ; } } if ( Clone ) { MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( Orig ) ; MI -> getOperand ( 0 ) . setReg ( DestReg ) ; MBB . insert ( I , MI ) ; } else { BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addImm ( 0 ) ; } MachineInstr * NewMI = prior ( I ) ; NewMI -> getOperand ( 0 ) . setSubReg ( SubIdx ) ; } </s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s> void Tile64RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> void UnwindOpcodeAssembler :: EmitSPOffset ( int64_t Offset ) { if ( Offset > 0x200 ) { uint8_t Buff [ 16 ] ; Buff [ 0 ] = ARM :: EHABI :: UNWIND_OPCODE_INC_VSP_ULEB128 ; size_t ULEBSize = encodeULEB128 ( ( Offset - 0x204 ) >> 2 , Buff + 1 ) ; EmitBytes ( Buff , ULEBSize + 1 ) ; } else if ( Offset > 0 ) { if ( Offset > 0x100 ) { EmitInt8 ( ARM :: EHABI :: UNWIND_OPCODE_INC_VSP | 0x3fu ) ; Offset -= 0x100 ; } EmitInt8 ( ARM :: EHABI :: UNWIND_OPCODE_INC_VSP | static_cast < uint8_t > ( ( Offset - 4 ) >> 2 ) ) ; } else if ( Offset < 0 ) { while ( Offset < - 0x100 ) { EmitInt8 ( ARM :: EHABI :: UNWIND_OPCODE_DEC_VSP | 0x3fu ) ; Offset += 0x100 ; } EmitInt8 ( ARM :: EHABI :: UNWIND_OPCODE_DEC_VSP | static_cast < uint8_t > ( ( ( - Offset ) - 4 ) >> 2 ) ) ; } } </s>

Emit unwind opcodes to add $ sp with an offset .


<s> static bool s390_is_longrunning ( rtx_insn * insn ) { if ( insn == NULL_RTX ) return false ; return s390_is_fxd ( insn ) || s390_is_fpd ( insn ) ; } </s>

Returns TRUE if INSN is a long-running instruction .


<s> static enum riscv_privilege_levels riscv_get_interrupt_type ( tree decl ) { gcc_assert ( decl != NULL_TREE ) ; if ( ( TREE_CODE ( decl ) != FUNCTION_DECL ) || ( ! riscv_interrupt_type_p ( TREE_TYPE ( decl ) ) ) ) return UNKNOWN_MODE ; tree attr_args = TREE_VALUE ( lookup_attribute ( "interrupt" , TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ) ) ; if ( attr_args && TREE_CODE ( TREE_VALUE ( attr_args ) ) != VOID_TYPE ) { const char * string = TREE_STRING_POINTER ( TREE_VALUE ( attr_args ) ) ; if ( ! strcmp ( string , "user" ) ) return USER_MODE ; else if ( ! strcmp ( string , "supervisor" ) ) return SUPERVISOR_MODE ; else return MACHINE_MODE ; } else return MACHINE_MODE ; } </s>

Get the interrupt type , return UNKNOWN_MODE if it 's not interrupt function .


<s> bool SIInstrInfo :: shouldClusterMemOps ( const MachineOperand & BaseOp1 , const MachineOperand & BaseOp2 , unsigned NumLoads ) const { const MachineInstr & FirstLdSt = * BaseOp1 . getParent ( ) ; const MachineInstr & SecondLdSt = * BaseOp2 . getParent ( ) ; if ( ! memOpsHaveSameBasePtr ( FirstLdSt , BaseOp1 , SecondLdSt , BaseOp2 ) ) return false ; const MachineOperand * FirstDst = nullptr ; const MachineOperand * SecondDst = nullptr ; if ( ( isMUBUF ( FirstLdSt ) && isMUBUF ( SecondLdSt ) ) || ( isMTBUF ( FirstLdSt ) && isMTBUF ( SecondLdSt ) ) || ( isFLAT ( FirstLdSt ) && isFLAT ( SecondLdSt ) ) ) { const unsigned MaxGlobalLoadCluster = 6 ; if ( NumLoads > MaxGlobalLoadCluster ) return false ; FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: vdata ) ; if ( ! FirstDst ) FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: vdst ) ; SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: vdata ) ; if ( ! SecondDst ) SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: vdst ) ; } else if ( isSMRD ( FirstLdSt ) && isSMRD ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: sdst ) ; SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: sdst ) ; } else if ( isDS ( FirstLdSt ) && isDS ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , AMDGPU :: OpName :: vdst ) ; SecondDst = getNamedOperand ( SecondLdSt , AMDGPU :: OpName :: vdst ) ; } if ( ! FirstDst || ! SecondDst ) return false ; unsigned LoadClusterThreshold = 16 ; const MachineRegisterInfo & MRI = FirstLdSt . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const unsigned Reg = FirstDst -> getReg ( ) ; const TargetRegisterClass * DstRC = TargetRegisterInfo :: isVirtualRegister ( Reg ) ? MRI . getRegClass ( Reg ) : RI . getPhysRegClass ( Reg ) ; return ( NumLoads * ( RI . getRegSizeInBits ( * DstRC ) / 8 ) ) <= LoadClusterThreshold ; } </s>

Returns true if the two given memory operations should be scheduled adjacent .

AMDGPU SI 6 AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName AMDGPU::OpName 16 8


<s> bool AlphaAsmPrinter :: doFinalization ( Module & M ) { for ( Module :: const_global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ; I != E ; ++ I ) printModuleLevelGV ( I ) ; return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> bool XtensaRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s>
void
HexagonHazardRecognizer
::
EmitInstruction
(
SUnit
*
SU
)
{
MachineInstr
*
MI
=
SU
->
getInstr
(
)
;
if
(
!
MI
)
return
;
for
(
const
MachineOperand
&
MO
:
MI
->
operands
(
)
)
if
(
MO
.
isReg
(
)
&&
MO
.
isDef
(
)
&&
!
MO
.
isImplicit
(
)
)
RegDefs
.
insert
(
MO
.
getReg
(
)
)
;
if
(
TII
->
isZeroCost
(
MI
->
getOpcode
(
)
)
)
return
;
if
(
!
Resources
->
canReserveResources
(
*
MI
)
)
{
assert
(
TII
->
mayBeNewStore
(
*
MI
)
&&
"Expecting .new store"
)
;
MachineFunction
*
MF
=
MI
->
getParent
(
)
->
getParent
(
)
;
MachineInstr
*
NewMI
=
MF
->
CreateMachineInstr
(
TII
->
get
(
TII
->
getDotNewOp
(
*
MI
)
)
,
MI
->
getDebugLoc
(
)
)
;
assert
(
Resources
->
canReserveResources
(
*
NewMI
)
)
;
Resources
->
reserveResources
(
*
NewMI
)
;
MF
->
DeleteMachineInstr
(
NewMI
)
;
}
else
Resources
->
reserveResources
(
*
MI
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
" Add instruction "
<<
*
MI
)
;
if
(
TII
->
mayBeCurLoad
(
*
MI
)
)
for
(
auto
&
S
:
SU
->
Succs
)
if
(
S
.
isAssignedRegDep
(
)
&&
S
.
getLatency
(
)
==
0
&&
S
.
getSUnit
(
)
->
NumPredsLeft
==
1
)
{
UsesDotCur
=
S
.
getSUnit
(
)
;
DotCurPNum
=
PacketNum
;
break
;
}
if
(
SU
==
UsesDotCur
)
{
UsesDotCur
=
nullptr
;
DotCurPNum
=
1
;
}
UsesLoad
=
MI
->
mayLoad
(
)
;
if
(
TII
->
isHVXVec
(
*
MI
)
&&
!
MI
->
mayLoad
(
)
&&
!
MI
->
mayStore
(
)
)
for
(
auto
&
S
:
SU
->
Succs
)
if
(
S
.
isAssignedRegDep
(
)
&&
S
.
getLatency
(
)
==
0
&&
TII
->
mayBeNewStore
(
*
S
.
getSUnit
(
)
->
getInstr
(
)
)
&&
Resources
->
canReserveResources
(
*
S
.
getSUnit
(
)
->
getInstr
(
)
)
)
{
PrefVectorStoreNew
=
S
.
getSUnit
(
)
;
break
;
}
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void NVPTXAsmPrinter :: emitFunctionBodyEnd ( ) { VRegMapping . clear ( ) ; } </s>

Targets can override this to emit stuff after the last basic block in the function .


<s>
MachineBasicBlock
*
Tile64TargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
MBB
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
assert
(
0
&&
"Unexpected instr type to insert!"
)
;
case
T64
::
SELECT
:
return
EmitSELECTWithCustomInserter
(
MI
,
MBB
)
;
case
T64
::
STORE_FP
:
return
EmitSTORE_FPWithCustomInserter
(
MI
,
MBB
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> bool fp_zero_operand ( rtx op ) { REAL_VALUE_TYPE r ; if ( GET_MODE ( op ) != SFmode ) return false ; REAL_VALUE_FROM_CONST_DOUBLE ( r , op ) ; return REAL_VALUES_EQUAL ( r , dconst0 ) && ! REAL_VALUE_MINUS_ZERO ( r ) ; } </s>

Returns true if OP is a floating point value with value 0.0 .


<s> bool SPIRVCallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < Register > VRegs , FunctionLoweringInfo & FLI , Register SwiftErrorVReg ) const { if ( VRegs . size ( ) > 1 ) return false ; if ( Val ) return MIRBuilder . buildInstr ( SPIRV :: OpReturnValue ) . addUse ( VRegs [ 0 ] ) . constrainAllUses ( MIRBuilder . getTII ( ) , * ST . getRegisterInfo ( ) , * ST . getRegBankInfo ( ) ) ; MIRBuilder . buildInstr ( SPIRV :: OpReturn ) ; return true ; } </s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .

SPIRV SPIRV 1 SPIRV::OpReturnValue 0 SPIRV::OpReturn


<s> bool writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const override { return false ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s>
bool
AMDGPUAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
setForcedEncodingSize
(
0
)
;
if
(
Name
.
endswith
(
"_e64"
)
)
setForcedEncodingSize
(
64
)
;
else
if
(
Name
.
endswith
(
"_e32"
)
)
setForcedEncodingSize
(
32
)
;
Operands
.
push_back
(
AMDGPUOperand
::
CreateToken
(
Name
,
NameLoc
)
)
;
while
(
!
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
{
AMDGPUAsmParser
::
OperandMatchResultTy
Res
=
parseOperand
(
Operands
,
Name
)
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
Parser
.
Lex
(
)
;
switch
(
Res
)
{
case
MatchOperand_Success
:
break
;
case
MatchOperand_ParseFail
:
return
Error
(
getLexer
(
)
.
getLoc
(
)
,
"failed parsing operand."
)
;
case
MatchOperand_NoMatch
:
return
Error
(
getLexer
(
)
.
getLoc
(
)
,
"not a valid operand."
)
;
}
}
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .


<s> int legitimate_pic_operand_p ( rtx x ) { if ( SYMBOL_REF_P ( x ) || ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == SYMBOL_REF ) ) return 0 ; return 1 ; } </s>

Return true if OP is a legitimate general operand when generating PIC code . It is given that flag_pic is on and that OP satisfies CONSTANT_P or is a CONST_DOUBLE .


<s> bool X86AsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const { return ! isInt < 8 > ( Value ) ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> void HexagonRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOp , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; MachineBasicBlock & MB = * MI . getParent ( ) ; MachineFunction & MF = * MB . getParent ( ) ; auto & HST = MF . getSubtarget < HexagonSubtarget > ( ) ; auto & HII = * HST . getInstrInfo ( ) ; auto & HFI = * HST . getFrameLowering ( ) ; Register BP ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; int Offset = HFI . getFrameIndexReference ( MF , FI , BP ) ; int RealOffset = Offset + MI . getOperand ( FIOp + 1 ) . getImm ( ) ; bool IsKill = false ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case Hexagon :: PS_fia : MI . setDesc ( HII . get ( Hexagon :: A2_addi ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + 1 ) ; return ; case Hexagon :: PS_fi : MI . setDesc ( HII . get ( Hexagon :: A2_addi ) ) ; break ; } if ( ! HII . isValidOffset ( Opc , RealOffset , this ) ) { auto & MRI = MF . getRegInfo ( ) ; Register TmpR = MRI . createVirtualRegister ( & Hexagon :: IntRegsRegClass ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( MB , II , DL , HII . get ( Hexagon :: A2_addi ) , TmpR ) . addReg ( BP ) . addImm ( RealOffset ) ; BP = TmpR ; RealOffset = 0 ; IsKill = true ; } MI . getOperand ( FIOp ) . ChangeToRegister ( BP , false , false , IsKill ) ; MI . getOperand ( FIOp + 1 ) . ChangeToImmediate ( RealOffset ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s>
MachineInstr
*
SIInstrInfo
::
commuteInstruction
(
MachineInstr
*
MI
,
bool
NewMI
)
const
{
if
(
MI
->
getNumOperands
(
)
<
3
)
return
nullptr
;
int
Src0Idx
=
AMDGPU
::
getNamedOperandIdx
(
MI
->
getOpcode
(
)
,
AMDGPU
::
OpName
::
src0
)
;
assert
(
Src0Idx
!=
1
&&
"Should always have src0 operand"
)
;
if
(
!
MI
->
getOperand
(
Src0Idx
)
.
isReg
(
)
)
return
nullptr
;
int
Src1Idx
=
AMDGPU
::
getNamedOperandIdx
(
MI
->
getOpcode
(
)
,
AMDGPU
::
OpName
::
src1
)
;
if
(
(
Src1Idx
!=
1
)
&&
isVOP2
(
MI
->
getOpcode
(
)
)
&&
(
!
isOperandLegal
(
MI
,
Src0Idx
,
&
MI
->
getOperand
(
Src1Idx
)
)
||
!
isOperandLegal
(
MI
,
Src1Idx
,
&
MI
->
getOperand
(
Src0Idx
)
)
)
)
return
nullptr
;
if
(
Src1Idx
!=
1
&&
!
MI
->
getOperand
(
Src1Idx
)
.
isReg
(
)
)
{
if
(
NewMI
||
!
MI
->
getOperand
(
Src1Idx
)
.
isImm
(
)
||
(
!
isVOP2
(
MI
->
getOpcode
(
)
)
&&
!
isVOP3
(
MI
->
getOpcode
(
)
)
)
)
{
return
nullptr
;
}
const
MachineOperand
*
Src0Mods
=
getNamedOperand
(
*
MI
,
AMDGPU
::
OpName
::
src0_modifiers
)
;
const
MachineOperand
*
Src1Mods
=
getNamedOperand
(
*
MI
,
AMDGPU
::
OpName
::
src1_modifiers
)
;
const
MachineOperand
*
Src2Mods
=
getNamedOperand
(
*
MI
,
AMDGPU
::
OpName
::
src2_modifiers
)
;
if
(
(
Src0Mods
&&
Src0Mods
->
getImm
(
)
)
||
(
Src1Mods
&&
Src1Mods
->
getImm
(
)
)
||
(
Src2Mods
&&
Src2Mods
->
getImm
(
)
)
)
return
nullptr
;
unsigned
Reg
=
MI
->
getOperand
(
Src0Idx
)
.
getReg
(
)
;
unsigned
SubReg
=
MI
->
getOperand
(
Src0Idx
)
.
getSubReg
(
)
;
MI
->
getOperand
(
Src0Idx
)
.
ChangeToImmediate
(
MI
->
getOperand
(
Src1Idx
)
.
getImm
(
)
)
;
MI
->
getOperand
(
Src1Idx
)
.
ChangeToRegister
(
Reg
,
false
)
;
MI
->
getOperand
(
Src1Idx
)
.
setSubReg
(
SubReg
)
;
}
else
{
MI
=
TargetInstrInfo
::
commuteInstruction
(
MI
,
NewMI
)
;
}
if
(
MI
)
MI
->
setDesc
(
get
(
commuteOpcode
(
MI
->
getOpcode
(
)
)
)
)
;
return
MI
;
}
</s>

This method commutes the operands of the given machine instruction MI .


"********** MI Converging Scheduling VLIW "

"** VLIWMachineScheduler::schedule picking next node\n"

Schedule - This is called back from ScheduleDAGInstrs : :Run ( ) when it 's time to do some work .


<s> static unsigned int pdp11_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( regno <= PC_REGNUM ) return CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ; return 1 ; } </s>


<s> void SystemZPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) == CodeGenOpt :: None ) addPass ( createSystemZPostRewritePass ( getSystemZTargetMachine ( ) ) ) ; addPass ( createSystemZExpandPseudoPass ( getSystemZTargetMachine ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & IfConverterID ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .

SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ


<s> bool RISCVELFTargetObjectFile :: isGlobalInSmallSection ( const GlobalObject * GO , const TargetMachine & TM ) const { const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GO ) ; if ( ! GVA ) return false ; if ( GVA -> hasSection ( ) ) { StringRef Section = GVA -> getSection ( ) ; if ( Section == ".sdata" || Section == ".sbss" ) return true ; return false ; } if ( ( ( GVA -> hasExternalLinkage ( ) && GVA -> isDeclaration ( ) ) || GVA -> hasCommonLinkage ( ) ) ) return false ; Type * Ty = GVA -> getValueType ( ) ; if ( ! Ty -> isSized ( ) ) return false ; return isInSmallSection ( GVA -> getParent ( ) -> getDataLayout ( ) . getTypeAllocSize ( Ty ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s>
unsigned
getStackAddress
(
uint64_t
Size
,
int64_t
Offset
,
MachinePointerInfo
&
MPO
)
override
{
assert
(
(
Size
==
1
||
Size
==
2
||
Size
==
4
||
Size
==
8
)
&&
"Unsupported size"
)
;
auto
&
MFI
=
MIRBuilder
.
getMF
(
)
.
getFrameInfo
(
)
;
int
FI
=
MFI
.
CreateFixedObject
(
Size
,
Offset
,
true
)
;
MPO
=
MachinePointerInfo
::
getFixedStack
(
MIRBuilder
.
getMF
(
)
,
FI
)
;
unsigned
AddrReg
=
MRI
.
createGenericVirtualRegister
(
LLT
::
pointer
(
MPO
.
getAddrSpace
(
)
,
32
)
)
;
MIRBuilder
.
buildFrameIndex
(
AddrReg
,
FI
)
;
return
AddrReg
;
}
</s>

Materialize a VReg containing the address of the specified stack-based object .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addPreserved < StackProtector > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
void
X86InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
Register
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
assert
(
MF
.
getFrameInfo
(
)
.
getObjectSize
(
FrameIdx
)
>=
TRI
->
getSpillSize
(
*
RC
)
&&
"Stack slot too small for store"
)
;
unsigned
Alignment
=
std
::
max
<
uint32_t
>
(
TRI
->
getSpillSize
(
*
RC
)
,
16
)
;
bool
isAligned
=
(
Subtarget
.
getFrameLowering
(
)
->
getStackAlignment
(
)
>=
Alignment
)
||
RI
.
canRealignStack
(
MF
)
;
unsigned
Opc
=
getStoreRegOpcode
(
SrcReg
,
RC
,
isAligned
,
Subtarget
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DebugLoc
(
)
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool ARMTargetLowering :: isUsedByReturnOnly ( SDNode * N , SDValue & Chain ) const { if ( N -> getNumValues ( ) != 1 ) return false ; if ( ! N -> hasNUsesOfValue ( 1 , 0 ) ) return false ; SDValue TCChain = Chain ; SDNode * Copy = * N -> use_begin ( ) ; if ( Copy -> getOpcode ( ) == ISD :: CopyToReg ) { if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - 1 ) . getValueType ( ) == MVT :: Glue ) return false ; TCChain = Copy -> getOperand ( 0 ) ; } else if ( Copy -> getOpcode ( ) == ARMISD :: VMOVRRD ) { SDNode * VMov = Copy ; SmallPtrSet < SDNode * , 2 > Copies ; for ( SDNode * U : VMov -> uses ( ) ) { if ( U -> getOpcode ( ) != ISD :: CopyToReg ) return false ; Copies . insert ( U ) ; } if ( Copies . size ( ) > 2 ) return false ; for ( SDNode * U : VMov -> uses ( ) ) { SDValue UseChain = U -> getOperand ( 0 ) ; if ( Copies . count ( UseChain . getNode ( ) ) ) Copy = U ; else { if ( U -> getOperand ( U -> getNumOperands ( ) - 1 ) . getValueType ( ) == MVT :: Glue ) return false ; TCChain = UseChain ; } } } else if ( Copy -> getOpcode ( ) == ISD :: BITCAST ) { if ( ! Copy -> hasOneUse ( ) ) return false ; Copy = * Copy -> use_begin ( ) ; if ( Copy -> getOpcode ( ) != ISD :: CopyToReg || ! Copy -> hasNUsesOfValue ( 1 , 0 ) ) return false ; if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - 1 ) . getValueType ( ) == MVT :: Glue ) return false ; TCChain = Copy -> getOperand ( 0 ) ; } else { return false ; } bool HasRet = false ; for ( const SDNode * U : Copy -> uses ( ) ) { if ( U -> getOpcode ( ) != ARMISD :: RET_FLAG && U -> getOpcode ( ) != ARMISD :: INTRET_FLAG ) return false ; HasRet = true ; } if ( ! HasRet ) return false ; Chain = TCChain ; return true ; } </s>

Return true if result of the specified node is used by a return node only .


<s> SDValue R600TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; R600MachineFunctionInfo * MFI = MF . getInfo < R600MachineFunctionInfo > ( ) ; SmallVector < ISD :: InputArg , 8 > LocalIns ; getOriginalFunctionArgs ( DAG , MF . getFunction ( ) , Ins , LocalIns ) ; AnalyzeFormalArguments ( CCInfo , LocalIns ) ; for ( unsigned i = 0 , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const ISD :: InputArg & In = Ins [ i ] ; EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector ( ) ) { MemVT = MemVT . getVectorElementType ( ) ; } if ( MFI -> getShaderType ( ) != ShaderType :: COMPUTE ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & AMDGPU :: R600_Reg128RegClass ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , AMDGPUAS :: CONSTANT_BUFFER_0 ) ; ISD :: LoadExtType Ext = ISD :: NON_EXTLOAD ; if ( MemVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) { Ext = ISD :: SEXTLOAD ; } unsigned ValBase = ArgLocs [ In . OrigArgIndex ] . getLocMemOffset ( ) ; unsigned PartOffset = VA . getLocMemOffset ( ) ; unsigned Offset = 36 + VA . getLocMemOffset ( ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) , PartOffset - ValBase ) ; SDValue Arg = DAG . getLoad ( ISD :: UNINDEXED , Ext , VT , DL , Chain , DAG . getConstant ( Offset , MVT :: i32 ) , DAG . getUNDEF ( MVT :: i32 ) , PtrInfo , MemVT , false , true , true , 4 ) ; InVals . push_back ( Arg ) ; MFI -> ABIArgOffset = Offset + MemVT . getStoreSize ( ) ; } return Chain ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> BitVector HexagonRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( Hexagon :: R29 ) ; Reserved . set ( Hexagon :: R30 ) ; Reserved . set ( Hexagon :: R31 ) ; Reserved . set ( Hexagon :: VTMP ) ; Reserved . set ( Hexagon :: GELR ) ; Reserved . set ( Hexagon :: GSR ) ; Reserved . set ( Hexagon :: GOSP ) ; Reserved . set ( Hexagon :: G3 ) ; Reserved . set ( Hexagon :: SA0 ) ; Reserved . set ( Hexagon :: LC0 ) ; Reserved . set ( Hexagon :: SA1 ) ; Reserved . set ( Hexagon :: LC1 ) ; Reserved . set ( Hexagon :: P3_0 ) ; Reserved . set ( Hexagon :: USR ) ; Reserved . set ( Hexagon :: PC ) ; Reserved . set ( Hexagon :: UGP ) ; Reserved . set ( Hexagon :: GP ) ; Reserved . set ( Hexagon :: CS0 ) ; Reserved . set ( Hexagon :: CS1 ) ; Reserved . set ( Hexagon :: UPCYCLELO ) ; Reserved . set ( Hexagon :: UPCYCLEHI ) ; Reserved . set ( Hexagon :: FRAMELIMIT ) ; Reserved . set ( Hexagon :: FRAMEKEY ) ; Reserved . set ( Hexagon :: PKTCOUNTLO ) ; Reserved . set ( Hexagon :: PKTCOUNTHI ) ; Reserved . set ( Hexagon :: UTIMERLO ) ; Reserved . set ( Hexagon :: UTIMERHI ) ; Reserved . set ( Hexagon :: C8 ) ; Reserved . set ( Hexagon :: USR_OVF ) ; if ( MF . getSubtarget < HexagonSubtarget > ( ) . hasReservedR19 ( ) ) Reserved . set ( Hexagon :: R19 ) ; for ( int x = Reserved . find_first ( ) ; x >= 0 ; x = Reserved . find_next ( x ) ) markSuperRegs ( Reserved , x ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static rtx visium_function_value_1 ( machine_mode mode ) { if ( TARGET_FPU && ( ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && GET_MODE_SIZE ( mode ) <= UNITS_PER_HWFPVALUE ) || ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT && GET_MODE_SIZE ( mode ) <= UNITS_PER_HWFPVALUE * 2 ) ) ) return gen_rtx_REG ( mode , FP_RETURN_REGNUM ) ; return gen_rtx_REG ( mode , RETURN_REGNUM ) ; } </s>


FIXME : This probably can be done using a define_split in arc.md . Alternately , generate rtx rather than output instructions .


<s> int frv_emit_scc ( rtx operands [ ] ) { rtx set ; rtx test_rtx ; rtx clobber ; rtx cr_reg ; enum rtx_code test = GET_CODE ( operands [ 1 ] ) ; rtx cc_reg = frv_emit_comparison ( test , operands [ 2 ] , operands [ 3 ] ) ; test_rtx = gen_rtx_fmt_ee ( test , SImode , cc_reg , const0_rtx ) ; set = gen_rtx_SET ( VOIDmode , operands [ 0 ] , test_rtx ) ; cr_reg = ( ( TARGET_ALLOC_CC ) ? gen_reg_rtx ( CC_CCRmode ) : gen_rtx_REG ( CC_CCRmode , ( ( GET_MODE ( cc_reg ) == CC_FPmode ) ? FCR_FIRST : ICR_FIRST ) ) ) ; clobber = gen_rtx_CLOBBER ( VOIDmode , cr_reg ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set , clobber ) ) ) ; return TRUE ; } </s>

Emit code to set a gpr to 1/0 based on a comparison . The comparison operands were previously stored in frv_compare_op0 and frv_compare_op1 .


<s> void emitDwarfLocDirective ( unsigned FileNo , unsigned Line , unsigned Column , unsigned Flags , unsigned Isa , unsigned Discriminator , StringRef FileName ) override { } </s>

This implements the DWARF2 '.loc fileno lineno ... ' assembler directive .


<s> bool MipsSEFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * EntryBlock = & MF -> front ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == Mips :: RA || Reg == Mips :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> int m68k_hard_regno_rename_ok ( unsigned int old_reg ATTRIBUTE_UNUSED , unsigned int new_reg ) { if ( m68k_interrupt_function_p ( current_function_decl ) && ! regs_ever_live [ new_reg ] ) return 0 ; return 1 ; } </s>

Return nonzero if register old_reg can be renamed to register new_reg .


Expand movmem , as if from a __builtin_memcpy . Return true if we succeed , otherwise return false .


<s> void split_di ( rtx operands [ ] , int num , rtx lo_half [ ] , rtx hi_half [ ] ) { while ( num -- ) { rtx op = operands [ num ] ; if ( MEM_P ( op ) ) { lo_half [ num ] = adjust_address ( op , SImode , 0 ) ; hi_half [ num ] = adjust_address ( op , SImode , 4 ) ; } else { lo_half [ num ] = simplify_gen_subreg ( SImode , op , GET_MODE ( op ) == VOIDmode ? DImode : GET_MODE ( op ) , 0 ) ; hi_half [ num ] = simplify_gen_subreg ( SImode , op , GET_MODE ( op ) == VOIDmode ? DImode : GET_MODE ( op ) , 4 ) ; } } } </s>

Split one or more DImode RTL references into pairs of SImode references . The RTL can be REG , offsettable MEM , integer constant , or CONST_DOUBLE . `` operands '' is a pointer to an array of DImode RTL to split and `` num '' is its length . lo_half and hi_half are output arrays that parallel `` operands '' .


<s> const HexagonRegisterInfo * getRegisterInfo ( ) const override { return & RegInfo ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> SDValue AMDGPUTargetLowering :: SplitVectorLoad ( const SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; if ( VT . getVectorNumElements ( ) == 2 ) return ScalarizeVectorLoad ( Op , DAG ) ; LoadSDNode * Load = cast < LoadSDNode > ( Op ) ; SDValue BasePtr = Load -> getBasePtr ( ) ; EVT PtrVT = BasePtr . getValueType ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; SDLoc SL ( Op ) ; MachinePointerInfo SrcValue ( Load -> getMemOperand ( ) -> getValue ( ) ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Op , SL , LoVT , HiVT ) ; SDValue LoLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , LoVT , Load -> getChain ( ) , BasePtr , SrcValue , LoMemVT , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> isInvariant ( ) , Load -> getAlignment ( ) ) ; SDValue HiPtr = DAG . getNode ( ISD :: ADD , SL , PtrVT , BasePtr , DAG . getConstant ( LoMemVT . getStoreSize ( ) , SL , PtrVT ) ) ; SDValue HiLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , HiVT , Load -> getChain ( ) , HiPtr , SrcValue . getWithOffset ( LoMemVT . getStoreSize ( ) ) , HiMemVT , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> isInvariant ( ) , Load -> getAlignment ( ) ) ; SDValue Ops [ ] = { DAG . getNode ( ISD :: CONCAT_VECTORS , SL , VT , LoLoad , HiLoad ) , DAG . getNode ( ISD :: TokenFactor , SL , MVT :: Other , LoLoad . getValue ( 1 ) , HiLoad . getValue ( 1 ) ) } ; return DAG . getMergeValues ( Ops , SL ) ; } </s>

Split a vector load into 2 loads of half the vector .


<s> const char * getPassName ( ) const override { return ARM_PREALLOC_LOAD_STORE_OPT_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> void c6x_function_end ( FILE * file , const char * fname ) { c6x_output_fn_unwind ( file ) ; insn_info . release ( ) ; if ( ! flag_inhibit_size_directive ) ASM_OUTPUT_MEASURED_SIZE ( file , fname ) ; } </s>

Called when a function has been assembled . It should perform all the tasks of ASM_DECLARE_FUNCTION_SIZE in elfos.h , plus target-specific tasks . We free the reservation ( and other scheduling ) information here now that all insns have been output .


<s> std :: pair < unsigned , const TargetRegisterClass * > AVRTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'a' : return std :: make_pair ( 0U , & AVR :: LD8loRegClass ) ; case 'b' : return std :: make_pair ( 0U , & AVR :: PTRDISPREGSRegClass ) ; case 'd' : return std :: make_pair ( 0U , & AVR :: LD8RegClass ) ; case 'l' : return std :: make_pair ( 0U , & AVR :: GPR8loRegClass ) ; case 'e' : return std :: make_pair ( 0U , & AVR :: PTRREGSRegClass ) ; case 'q' : return std :: make_pair ( 0U , & AVR :: GPRSPRegClass ) ; case 'r' : if ( VT == MVT :: i8 ) return std :: make_pair ( 0U , & AVR :: GPR8RegClass ) ; return std :: make_pair ( 0U , & AVR :: DREGSRegClass ) ; case 't' : return std :: make_pair ( unsigned ( AVR :: R0 ) , & AVR :: GPR8RegClass ) ; case 'w' : return std :: make_pair ( 0U , & AVR :: IWREGSRegClass ) ; case 'x' : case 'X' : return std :: make_pair ( unsigned ( AVR :: R27R26 ) , & AVR :: PTRREGSRegClass ) ; case 'y' : case 'Y' : return std :: make_pair ( unsigned ( AVR :: R29R28 ) , & AVR :: PTRREGSRegClass ) ; case 'z' : case 'Z' : return std :: make_pair ( unsigned ( AVR :: R31R30 ) , & AVR :: PTRREGSRegClass ) ; default : break ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Subtarget . getRegisterInfo ( ) , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> bool riscv_hard_regno_rename_ok ( unsigned from_regno ATTRIBUTE_UNUSED , unsigned to_regno ) { return ! cfun -> machine -> interrupt_handler_p || df_regs_ever_live_p ( to_regno ) ; } </s>

Return nonzero if register FROM_REGNO can be renamed to register TO_REGNO .


<s> void X86IntelInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot ) { printInstruction ( MI , OS ) ; if ( CommentStream ) { printAnnotation ( OS , Annot ) ; EmitAnyX86InstComments ( MI , * CommentStream , getRegisterName ) ; } } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static void expand_interrupt_handler_prologue ( rtx spreg , e_funkind fkind , bool all ) { HOST_WIDE_INT frame_size = get_frame_size ( ) ; rtx predec1 = gen_rtx_PRE_DEC ( SImode , spreg ) ; rtx predec = gen_rtx_MEM ( SImode , predec1 ) ; rtx_insn * insn ; tree attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ; tree kspisusp = lookup_attribute ( "kspisusp" , attrs ) ; if ( kspisusp ) { insn = emit_move_insn ( spreg , gen_rtx_REG ( Pmode , REG_USP ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } if ( fkind == EXCPT_HANDLER ) { insn = emit_insn ( gen_addsi3 ( spreg , spreg , GEN_INT ( - 12 ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } if ( ! crtl -> is_leaf ) all = true ; expand_prologue_reg_save ( spreg , all , true ) ; if ( ENABLE_WA_05000283 || ENABLE_WA_05000315 ) { rtx chipid = GEN_INT ( trunc_int_for_mode ( 0xFFC00014 , SImode ) ) ; rtx p5reg = gen_rtx_REG ( Pmode , REG_P5 ) ; emit_insn ( gen_movbi ( bfin_cc_rtx , const1_rtx ) ) ; emit_insn ( gen_movsi_high ( p5reg , chipid ) ) ; emit_insn ( gen_movsi_low ( p5reg , p5reg , chipid ) ) ; emit_insn ( gen_dummy_load ( p5reg , bfin_cc_rtx ) ) ; } if ( lookup_attribute ( "nesting" , attrs ) ) { rtx srcreg = gen_rtx_REG ( Pmode , ret_regs [ fkind ] ) ; insn = emit_move_insn ( predec , srcreg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } do_link ( spreg , frame_size , all ) ; if ( fkind == EXCPT_HANDLER ) { rtx r0reg = gen_rtx_REG ( SImode , REG_R0 ) ; rtx r1reg = gen_rtx_REG ( SImode , REG_R1 ) ; rtx r2reg = gen_rtx_REG ( SImode , REG_R2 ) ; emit_move_insn ( r0reg , gen_rtx_REG ( SImode , REG_SEQSTAT ) ) ; emit_insn ( gen_ashrsi3 ( r0reg , r0reg , GEN_INT ( 26 ) ) ) ; emit_insn ( gen_ashlsi3 ( r0reg , r0reg , GEN_INT ( 26 ) ) ) ; emit_move_insn ( r1reg , spreg ) ; emit_move_insn ( r2reg , gen_rtx_REG ( Pmode , REG_FP ) ) ; emit_insn ( gen_addsi3 ( r2reg , r2reg , GEN_INT ( 8 ) ) ) ; } } </s>

Generate a prologue suitable for a function of kind FKIND . This is called for interrupt and exception handler prologues . SPREG contains ( reg : SI REG_SP ) .