<s> void SIAnnotateControlFlow :: initialize ( Module & M , const GCNSubtarget & ST ) { LLVMContext & Context = M . getContext ( ) ; Void = Type :: getVoidTy ( Context ) ; Boolean = Type :: getInt1Ty ( Context ) ; IntMask = ST . isWave32 ( ) ? Type :: getInt32Ty ( Context ) : Type :: getInt64Ty ( Context ) ; ReturnStruct = StructType :: get ( Boolean , IntMask ) ; BoolTrue = ConstantInt :: getTrue ( Context ) ; BoolFalse = ConstantInt :: getFalse ( Context ) ; BoolUndef = UndefValue :: get ( Boolean ) ; IntMaskZero = ConstantInt :: get ( IntMask , 0 ) ; If = Intrinsic :: getDeclaration ( & M , Intrinsic :: amdgcn_if , { IntMask } ) ; Else = Intrinsic :: getDeclaration ( & M , Intrinsic :: amdgcn_else , { IntMask , IntMask } ) ; IfBreak = Intrinsic :: getDeclaration ( & M , Intrinsic :: amdgcn_if_break , { IntMask , IntMask } ) ; Loop = Intrinsic :: getDeclaration ( & M , Intrinsic :: amdgcn_loop , { IntMask } ) ; EndCf = Intrinsic :: getDeclaration ( & M , Intrinsic :: amdgcn_end_cf , { IntMask } ) ; } </s>

Initialize the strategy after building the DAG for a new region .


<s> static rtx aarch64_expand_builtin_data_intrinsic ( unsigned int fcode , tree exp , rtx target ) { expand_operand ops [ 2 ] ; machine_mode mode = TYPE_MODE ( TREE_TYPE ( exp ) ) ; create_output_operand ( & ops [ 0 ] , target , mode ) ; create_input_operand ( & ops [ 1 ] , expand_normal ( CALL_EXPR_ARG ( exp , 0 ) ) , mode ) ; enum insn_code icode ; switch ( fcode ) { case AARCH64_REV16 : case AARCH64_REV16L : case AARCH64_REV16LL : icode = code_for_aarch64_rev16 ( mode ) ; break ; case AARCH64_RBIT : case AARCH64_RBITL : case AARCH64_RBITLL : icode = code_for_aarch64_rbit ( mode ) ; break ; default : gcc_unreachable ( ) ; } expand_insn ( icode , 2 , ops ) ; return ops [ 0 ] . value ; } </s>

Function to expand an expression EXP which calls one of the ACLE Data Intrinsic builtins FCODE with the result going to TARGET .


<s> const char * tilepro_output_cbranch ( rtx_insn * insn , rtx * operands , bool reversed ) { enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; const char * opcode ; const char * rev_opcode ; if ( reversed ) code = reverse_condition ( code ) ; switch ( code ) { case NE : opcode = "bnz" ; rev_opcode = "bz" ; break ; case EQ : opcode = "bz" ; rev_opcode = "bnz" ; break ; case GE : opcode = "bgez" ; rev_opcode = "blz" ; break ; case GT : opcode = "bgz" ; rev_opcode = "blez" ; break ; case LE : opcode = "blez" ; rev_opcode = "bgz" ; break ; case LT : opcode = "blz" ; rev_opcode = "bgez" ; break ; default : gcc_unreachable ( ) ; } return tilepro_output_cbranch_with_opcode ( insn , operands , opcode , rev_opcode , 2 , false ) ; } </s>

Output assembly code for a conditional branch instruction .

tilepro 1 "bnz" "bz" "bz" "bnz" "bgez" "blz" "bgz" "blez" "blez" "bgz" "blz" "bgez" 2


<s> unsigned int rs6000_data_alignment ( tree type , unsigned int align , enum data_align how ) { if ( how != align_opt ) { if ( TREE_CODE ( type ) == VECTOR_TYPE ) { if ( ( TARGET_SPE && SPE_VECTOR_MODE ( TYPE_MODE ( type ) ) ) || ( TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE ( TYPE_MODE ( type ) ) ) ) { if ( align < 64 ) align = 64 ; } else if ( align < 128 ) align = 128 ; } else if ( TARGET_E500_DOUBLE && TREE_CODE ( type ) == REAL_TYPE && TYPE_MODE ( type ) == DFmode ) { if ( align < 64 ) align = 64 ; } } if ( how != align_abi ) { if ( TREE_CODE ( type ) == ARRAY_TYPE && TYPE_MODE ( TREE_TYPE ( type ) ) == QImode ) { if ( align < BITS_PER_WORD ) align = BITS_PER_WORD ; } } return align ; } </s>

Return alignment of TYPE . Existing alignment is ALIGN . HOW selects whether the alignment is abi mandated , optional , or both abi and optional alignment .


<s> tree aarch64_general_builtin_decl ( unsigned code , bool ) { if ( code >= AARCH64_BUILTIN_MAX ) return error_mark_node ; return aarch64_builtin_decls [ code ] ; } </s>

Implement TARGET_BUILTIN_DECL for the AARCH64_BUILTIN_GENERAL group .


<s> InstructionCost RISCVTTIImpl :: getMinMaxReductionCost ( VectorType * Ty , VectorType * CondTy , bool IsUnsigned , TTI :: TargetCostKind CostKind ) { if ( ! isa < FixedVectorType > ( Ty ) ) return BaseT :: getMinMaxReductionCost ( Ty , CondTy , IsUnsigned , CostKind ) ; if ( ! ST -> useRVVForFixedLengthVectors ( ) ) return BaseT :: getMinMaxReductionCost ( Ty , CondTy , IsUnsigned , CostKind ) ; if ( Ty -> getScalarSizeInBits ( ) > ST -> getELEN ( ) ) return BaseT :: getMinMaxReductionCost ( Ty , CondTy , IsUnsigned , CostKind ) ; InstructionCost BaseCost = 2 ; unsigned VL = cast < FixedVectorType > ( Ty ) -> getNumElements ( ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; return ( LT . first - 1 ) + BaseCost + Log2_32_Ceil ( VL ) ; } </s>

Try to calculate op costs for min/max reduction operations .


<s> unsigned X86TargetLowering :: getJumpTableEncoding ( ) const { if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ && Subtarget -> isPICStyleGOT ( ) ) return MachineJumpTableInfo :: EK_Custom32 ; return TargetLowering :: getJumpTableEncoding ( ) ; } </s>

Return the entry encoding for a jump table in the current function .


<s> void emitInst ( uint32_t Inst ) { char Buffer [ 4 ] ; for ( unsigned I = 0 ; I < 4 ; ++ I ) { Buffer [ I ] = uint8_t ( Inst ) ; Inst >>= 8 ; } emitA64MappingSymbol ( ) ; MCELFStreamer :: emitBytes ( StringRef ( Buffer , 4 ) ) ; } </s>

Callback used to implement the .inst directive .


<s> void SystemZTTIImpl :: getPeelingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: PeelingPreferences & PP ) { BaseT :: getPeelingPreferences ( L , SE , PP ) ; } </s>

Get target-customized preferences for the generic loop peeling transformation .


<s> bool PPCTargetLowering :: SelectAddressEVXRegReg ( SDValue N , SDValue & Base , SDValue & Index , SelectionDAG & DAG ) const { for ( SDNode :: use_iterator UI = N -> use_begin ( ) , E = N -> use_end ( ) ; UI != E ; ++ UI ) { if ( MemSDNode * Memop = dyn_cast < MemSDNode > ( * UI ) ) { if ( Memop -> getMemoryVT ( ) == MVT :: f64 ) { Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } } } return false ; } </s>

SelectAddressEVXRegReg - Given the specified addressed , check to see if it can be more efficiently represented as [ r+imm ] .


<s> uint64_t R600MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixup , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) { if ( HAS_NATIVE_OPERANDS ( MCII . get ( MI . getOpcode ( ) ) . TSFlags ) ) { return MRI . getEncodingValue ( MO . getReg ( ) ) ; } else { return getHWReg ( MO . getReg ( ) ) ; } } else if ( MO . isImm ( ) ) { return MO . getImm ( ) ; } else { assert ( 0 ) ; return 0 ; } } </s>

getMachineOpValue - Return binary encoding of operand .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineTraceMetrics > ( ) ; AU . addPreserved < MachineTraceMetrics > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void MipsTargetMachine :: resetSubtarget ( MachineFunction * MF ) { LLVM_DEBUG ( dbgs ( ) << "resetSubtarget\n" ) ; Subtarget = & MF -> getSubtarget < MipsSubtarget > ( ) ; } </s>

Reset the subtarget for the Mips target .


<s> static rtx_insn * avr_md_asm_adjust ( vec < rtx > & , vec < rtx > & , vec < machine_mode > & , vec < const char * > & , vec < rtx > & clobbers , HARD_REG_SET & clobbered_regs , location_t ) { clobbers . safe_push ( cc_reg_rtx ) ; SET_HARD_REG_BIT ( clobbered_regs , REG_CC ) ; return NULL ; } </s>

Prepend to CLOBBERS hard registers that are automatically clobbered for an asm . We do this for CC_REGNUM to maintain source compatibility with the original cc0-based compiler .


<s> inline machine_mode function_checker :: arg_mode ( unsigned int argno ) const { return TYPE_MODE ( TREE_TYPE ( m_args [ argno ] ) ) ; } </s>

Return the machine_mode of the corresponding arg type .


<s> static SDValue getTargetNode ( ConstantPoolSDNode * N , SDLoc DL , EVT Ty , SelectionDAG & DAG , unsigned Flags ) { return DAG . getTargetConstantPool ( N -> getConstVal ( ) , Ty , N -> getAlignment ( ) , N -> getOffset ( ) , Flags ) ; } </s>

Retrieve the target node this edge connects to .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: CreateImm ( 0 ) ) ; else if ( auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ; } </s>


<s> void RISCVFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const RISCVInstrInfo & TII = * static_cast < const RISCVInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; const RISCVSubtarget & STI = MF . getSubtarget < RISCVSubtarget > ( ) ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( 0 ) . getImm ( ) ; if ( I -> getOpcode ( ) == RISCV :: ADJCALLSTACKDOWN ) Amount = - Amount ; unsigned SP = STI . isRV64 ( ) ? RISCV :: sp_64 : RISCV :: sp ; TII . adjustStackPtr ( SP , Amount , MBB , I ) ; } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

RISCV RISCV RISCV RISCV RISCV RISCV 0 RISCV::ADJCALLSTACKDOWN RISCV::sp_64 RISCV::sp


<s> unsigned RISCVRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? RISCV :: X8 : RISCV :: X2 ; } </s>


<s> void m32c_initialize_trampoline ( rtx tramp , rtx function , rtx chainval ) { if ( TARGET_A16 ) { emit_move_insn ( A0 ( HImode , 0 ) , GEN_INT ( 0xc475 - 0x10000 ) ) ; emit_move_insn ( A0 ( HImode , 2 ) , chainval ) ; emit_move_insn ( A0 ( QImode , 4 ) , GEN_INT ( 0xfc - 0x100 ) ) ; emit_move_insn ( A0 ( HImode , 5 ) , function ) ; emit_move_insn ( A0 ( QImode , 7 ) , GEN_INT ( 0x00 ) ) ; } else { emit_move_insn ( A0 ( QImode , 0 ) , GEN_INT ( 0xbc - 0x100 ) ) ; emit_move_insn ( A0 ( PSImode , 1 ) , chainval ) ; emit_move_insn ( A0 ( QImode , 4 ) , GEN_INT ( 0xcc - 0x100 ) ) ; emit_move_insn ( A0 ( PSImode , 5 ) , function ) ; } } </s>


<s> bool MBlazePassConfig :: addInstSelector ( ) { addPass ( createMBlazeISelDag ( getMBlazeTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool Thumb1FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( ARM :: tPUSH ) ) ; AddDefaultPred ( MIB ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; bool isKill = true ; if ( Reg == ARM :: LR ) { MachineFunction & MF = * MBB . getParent ( ) ; if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) && MF . getRegInfo ( ) . isLiveIn ( Reg ) ) isKill = false ; } if ( isKill ) MBB . addLiveIn ( Reg ) ; MIB . addReg ( Reg , getKillRegState ( isKill ) ) ; } MIB . setMIFlags ( MachineInstr :: FrameSetup ) ; return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> bool arc_legitimate_pc_offset_p ( rtx addr ) { if ( GET_CODE ( addr ) != CONST ) return false ; addr = XEXP ( addr , 0 ) ; if ( GET_CODE ( addr ) == PLUS ) { if ( GET_CODE ( XEXP ( addr , 1 ) ) != CONST_INT ) return false ; addr = XEXP ( addr , 0 ) ; } return ( GET_CODE ( addr ) == UNSPEC && XVECLEN ( addr , 0 ) == 1 && XINT ( addr , 1 ) == ARC_UNSPEC_GOT && GET_CODE ( XVECEXP ( addr , 0 , 0 ) ) == SYMBOL_REF ) ; } </s>

Return true if ADDR is an address that needs to be expressed as an explicit sum of pcl + offset .


<s>
unsigned
AArch64TargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
SelectionDAG
&
DAG
)
const
{
unsigned
Reg
=
MatchRegisterName
(
RegName
)
;
if
(
AArch64
::
X1
<=
Reg
&&
Reg
<=
AArch64
::
X28
)
{
const
MCRegisterInfo
*
MRI
=
Subtarget
->
getRegisterInfo
(
)
;
unsigned
DwarfRegNum
=
MRI
->
getDwarfRegNum
(
Reg
,
false
)
;
if
(
!
Subtarget
->
isXRegisterReserved
(
DwarfRegNum
)
)
Reg
=
0
;
}
if
(
Reg
)
return
Reg
;
report_fatal_error
(
Twine
(
"Invalid register name \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;
}
</s>

Return the register ID of the name passed in .


<s>
static
bool
arm_rtx_costs
(
rtx
x
,
machine_mode
mode
ATTRIBUTE_UNUSED
,
int
outer_code
,
int
opno
ATTRIBUTE_UNUSED
,
int
*
total
,
bool
speed
)
{
bool
result
;
int
code
=
GET_CODE
(
x
)
;
gcc_assert
(
current_tune
->
insn_extra_cost
)
;
result
=
arm_rtx_costs_internal
(
x
,
(
enum
rtx_code
)
code
,
(
enum
rtx_code
)
outer_code
,
current_tune
->
insn_extra_cost
,
total
,
speed
)
;
if
(
dump_file
&&
arm_verbose_cost
)
{
print_rtl_single
(
dump_file
,
x
)
;
fprintf
(
dump_file
,
"\n%s cost: %d (%s)\n"
,
speed
"Hot"
:
"Cold"
,
*
total
,
result
"final"
:
"partial"
)
;
}
return
result
;
}
</s>

arm
"\n%s cost: %d (%s)\n"
"Hot"
"Cold"
"final"
"partial"


<s> void init_cumulative_args ( CUMULATIVE_ARGS * cum , tree fntype , rtx libname ATTRIBUTE_UNUSED ) { static CUMULATIVE_ARGS zero_cum ; tree param , next_param ; * cum = zero_cum ; for ( param = fntype ? TYPE_ARG_TYPES ( fntype ) : 0 ; param != 0 ; param = next_param ) { next_param = TREE_CHAIN ( param ) ; if ( next_param == 0 && TREE_VALUE ( param ) != void_type_node ) cum -> gp_reg_found = 1 ; } } </s>

Handle the INIT_CUMULATIVE_ARGS macro . Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is 0 .


<s> bool isImm ( ) const override { return Kind == Immediate ; } </s>


<s> virtual unsigned getISAEncoding ( ) { if ( ! Subtarget -> isTargetDarwin ( ) ) return 0 ; return Subtarget -> isThumb ( ) ? ARM :: DW_ISA_ARM_thumb : ARM :: DW_ISA_ARM_arm ; } </s>

Get the value for DW_AT_APPLE_isa . Zero if no isa encoding specified .


<s> static rtx rs6000_internal_arg_pointer ( void ) { if ( flag_split_stack && ( lookup_attribute ( "no_split_stack" , DECL_ATTRIBUTES ( cfun -> decl ) ) == NULL ) ) { if ( cfun -> machine -> split_stack_arg_pointer == NULL_RTX ) { rtx pat ; cfun -> machine -> split_stack_arg_pointer = gen_reg_rtx ( Pmode ) ; REG_POINTER ( cfun -> machine -> split_stack_arg_pointer ) = 1 ; pat = gen_rtx_SET ( cfun -> machine -> split_stack_arg_pointer , gen_rtx_REG ( Pmode , 12 ) ) ; push_topmost_sequence ( ) ; emit_insn_after ( pat , get_insns ( ) ) ; pop_topmost_sequence ( ) ; } rtx ret = plus_constant ( Pmode , cfun -> machine -> split_stack_arg_pointer , FIRST_PARM_OFFSET ( current_function_decl ) ) ; return copy_to_reg ( ret ) ; } return virtual_incoming_args_rtx ; } </s>

Return the internal arg pointer used for function incoming arguments . When -fsplit-stack , the arg pointer is r12 so we need to copy it to a pseudo in order for it to be preserved over calls and suchlike . We 'd really like to use a pseudo here for the internal arg pointer but data-flow analysis is not prepared to accept pseudos as live at the beginning of a function .


<s> bool SILowerControlFlow :: runOnMachineFunction ( MachineFunction & MF ) { const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; LIS = getAnalysisIfAvailable < LiveIntervals > ( ) ; MRI = & MF . getRegInfo ( ) ; BoolRC = TRI -> getBoolRC ( ) ; InsertKillCleanups = MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: AMDGPU_PS ; if ( ST . isWave32 ( ) ) { AndOpc = AMDGPU :: S_AND_B32 ; OrOpc = AMDGPU :: S_OR_B32 ; XorOpc = AMDGPU :: S_XOR_B32 ; MovTermOpc = AMDGPU :: S_MOV_B32_term ; Andn2TermOpc = AMDGPU :: S_ANDN2_B32_term ; XorTermrOpc = AMDGPU :: S_XOR_B32_term ; OrTermrOpc = AMDGPU :: S_OR_B32_term ; OrSaveExecOpc = AMDGPU :: S_OR_SAVEEXEC_B32 ; Exec = AMDGPU :: EXEC_LO ; } else { AndOpc = AMDGPU :: S_AND_B64 ; OrOpc = AMDGPU :: S_OR_B64 ; XorOpc = AMDGPU :: S_XOR_B64 ; MovTermOpc = AMDGPU :: S_MOV_B64_term ; Andn2TermOpc = AMDGPU :: S_ANDN2_B64_term ; XorTermrOpc = AMDGPU :: S_XOR_B64_term ; OrTermrOpc = AMDGPU :: S_OR_B64_term ; OrSaveExecOpc = AMDGPU :: S_OR_SAVEEXEC_B64 ; Exec = AMDGPU :: EXEC ; } SmallVector < MachineInstr * , 32 > Worklist ; MachineFunction :: iterator NextBB ; for ( MachineFunction :: iterator BI = MF . begin ( ) ; BI != MF . end ( ) ; BI = NextBB ) { NextBB = std :: next ( BI ) ; MachineBasicBlock * MBB = & * BI ; MachineBasicBlock :: iterator I , E , Next ; E = MBB -> end ( ) ; for ( I = MBB -> begin ( ) ; I != E ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; MachineBasicBlock * SplitMBB = MBB ; switch ( MI . getOpcode ( ) ) { case AMDGPU :: SI_IF : SplitMBB = process ( MI ) ; break ; case AMDGPU :: SI_ELSE : case AMDGPU :: SI_IF_BREAK : case AMDGPU :: SI_LOOP : case AMDGPU :: SI_END_CF : if ( InsertKillCleanups ) Worklist . push_back ( & MI ) ; else SplitMBB = process ( MI ) ; break ; case AMDGPU :: SI_INIT_EXEC : case AMDGPU :: SI_INIT_EXEC_FROM_INPUT : lowerInitExec ( MBB , MI ) ; if ( LIS ) LIS -> removeAllRegUnitsForPhysReg ( AMDGPU :: EXEC ) ; break ; default : break ; } if ( SplitMBB != MBB ) { MBB = Next -> getParent ( ) ; E = MBB -> end ( ) ; } } } for ( MachineInstr * MI : Worklist ) process ( * MI ) ; optimizeEndCf ( ) ; LoweredEndCf . clear ( ) ; LoweredIf . clear ( ) ; NeedsKillCleanup . clear ( ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s>
void
SIInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
Register
SrcReg
,
bool
isKill
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
SIMachineFunctionInfo
*
MFI
=
MF
->
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MachineFrameInfo
&
FrameInfo
=
MF
->
getFrameInfo
(
)
;
const
DebugLoc
&
DL
=
MBB
.
findDebugLoc
(
MI
)
;
MachinePointerInfo
PtrInfo
=
MachinePointerInfo
::
getFixedStack
(
*
MF
,
FrameIndex
)
;
MachineMemOperand
*
MMO
=
MF
->
getMachineMemOperand
(
PtrInfo
,
MachineMemOperand
::
MOStore
,
FrameInfo
.
getObjectSize
(
FrameIndex
)
,
FrameInfo
.
getObjectAlign
(
FrameIndex
)
)
;
unsigned
SpillSize
=
TRI
->
getSpillSize
(
*
RC
)
;
if
(
RI
.
isSGPRClass
(
RC
)
)
{
MFI
->
setHasSpilledSGPRs
(
)
;
assert
(
SrcReg
!=
AMDGPU
::
M0
&&
"m0 should not be spilled"
)
;
assert
(
SrcReg
!=
AMDGPU
::
EXEC_LO
&&
SrcReg
!=
AMDGPU
::
EXEC_HI
&&
SrcReg
!=
AMDGPU
::
EXEC
&&
"exec should not be spilled"
)
;
const
MCInstrDesc
&
OpDesc
=
get
(
getSGPRSpillSaveOpcode
(
SpillSize
)
)
;
if
(
Register
::
isVirtualRegister
(
SrcReg
)
&&
SpillSize
==
4
)
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
MRI
.
constrainRegClass
(
SrcReg
,
&
AMDGPU
::
SReg_32_XM0_XEXECRegClass
)
;
}
BuildMI
(
MBB
,
MI
,
DL
,
OpDesc
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIndex
)
.
addMemOperand
(
MMO
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
,
RegState
::
Implicit
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
,
RegState
::
Implicit
)
;
if
(
RI
.
spillSGPRToVGPR
(
)
)
FrameInfo
.
setStackID
(
FrameIndex
,
TargetStackID
::
SGPRSpill
)
;
return
;
}
unsigned
Opcode
=
RI
.
hasAGPRs
(
RC
)
getAGPRSpillSaveOpcode
(
SpillSize
)
:
getVGPRSpillSaveOpcode
(
SpillSize
)
;
MFI
->
setHasSpilledVGPRs
(
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opcode
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIndex
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool M88kPassConfig :: addIRTranslator ( ) { addPass ( new IRTranslator ( ) ) ; return false ; } </s>

This method should install an IR translator pass , which converts from LLVM code to machine instructions with possibly generic opcodes .


<s> static int s390_sched_score ( rtx_insn * insn ) { unsigned int mask = s390_get_sched_attrmask ( insn ) ; int score = 0 ; switch ( s390_sched_state ) { case 0 : if ( ( mask & S390_SCHED_ATTR_MASK_CRACKED ) != 0 || ( mask & S390_SCHED_ATTR_MASK_EXPANDED ) != 0 ) score += 5 ; if ( ( mask & S390_SCHED_ATTR_MASK_GROUPALONE ) != 0 ) score += 10 ; case 1 : if ( ( mask & S390_SCHED_ATTR_MASK_CRACKED ) == 0 && ( mask & S390_SCHED_ATTR_MASK_EXPANDED ) == 0 && ( mask & S390_SCHED_ATTR_MASK_GROUPALONE ) == 0 ) score += 10 ; if ( ( mask & S390_SCHED_ATTR_MASK_ENDGROUP ) == 0 ) score += 5 ; break ; case 2 : if ( ( mask & S390_SCHED_ATTR_MASK_CRACKED ) == 0 && ( mask & S390_SCHED_ATTR_MASK_EXPANDED ) == 0 && ( mask & S390_SCHED_ATTR_MASK_GROUPALONE ) == 0 ) score += 10 ; if ( ( mask & S390_SCHED_ATTR_MASK_ENDGROUP ) != 0 ) score += 10 ; break ; case S390_SCHED_STATE_NORMAL : if ( ( mask & S390_SCHED_ATTR_MASK_CRACKED ) == 0 && ( mask & S390_SCHED_ATTR_MASK_EXPANDED ) == 0 ) score += 5 ; if ( ( mask & S390_SCHED_ATTR_MASK_GROUPALONE ) != 0 ) score += 10 ; break ; case S390_SCHED_STATE_CRACKED : if ( ( mask & S390_SCHED_ATTR_MASK_CRACKED ) != 0 || ( mask & S390_SCHED_ATTR_MASK_EXPANDED ) != 0 ) score += 5 ; break ; } if ( s390_tune >= PROCESSOR_2964_Z13 ) { int units , i ; unsigned unit_mask , m = 1 ; unit_mask = s390_get_unit_mask ( insn , & units ) ; gcc_assert ( units <= MAX_SCHED_UNITS ) ; for ( i = 0 ; i < units ; i ++ , m <<= 1 ) if ( m & unit_mask ) score += ( last_scheduled_unit_distance [ i ] * MAX_SCHED_MIX_SCORE / MAX_SCHED_MIX_DISTANCE ) ; unsigned latency = insn_default_latency ( insn ) ; int other_side = 1 - current_side ; if ( latency > LONGRUNNING_THRESHOLD ) { if ( get_attr_z13_unit_fxu ( insn ) && fxu_longrunning [ current_side ] && fxu_longrunning [ other_side ] <= fxu_longrunning [ current_side ] ) score = MAX ( 0 , score - 10 ) ; if ( get_attr_z13_unit_vfu ( insn ) && vfu_longrunning [ current_side ] && vfu_longrunning [ other_side ] <= vfu_longrunning [ current_side ] ) score = MAX ( 0 , score - 10 ) ; } } return score ; } </s>

Return the scheduling score for INSN . The higher the score the better . The score is calculated from the OOO scheduling attributes of INSN and the scheduling state s390_sched_state .


"enabling backtrace support is only meaningful when compiling for the Thumb"

"enabling callee interworking support is only meaningful when compiling for the Thumb"

"-g with -mno-apcs-frame may not give sensible debugging"

"can not use -mtp=cp15 with 16-bit Thumb"

"-mslow-flash-data only supports non-pic code on armv7-m targets"

Check any incompatible options that the user has specified .


<s> bool AGCPassConfig :: addInstSelector ( ) { addPass ( createAGCISelDag ( getAGCTargetMachine ( ) ) ) ; return false ; } </s>


<s>
bool
ARMBaseInstrInfo
::
getInsertSubregLikeInputs
(
const
MachineInstr
&
MI
,
unsigned
DefIdx
,
RegSubRegPair
&
BaseReg
,
RegSubRegPairAndIdx
&
InsertedReg
)
const
{
assert
(
DefIdx
<
MI
.
getDesc
(
)
.
getNumDefs
(
)
&&
"Invalid definition index"
)
;
assert
(
MI
.
isInsertSubregLike
(
)
&&
"Invalid kind of instruction"
)
;
switch
(
MI
.
getOpcode
(
)
)
{
case
ARM
::
VSETLNi32
:
case
ARM
::
MVE_VMOV_to_lane_32
:
const
MachineOperand
&
MOBaseReg
=
MI
.
getOperand
(
1
)
;
const
MachineOperand
&
MOInsertedReg
=
MI
.
getOperand
(
2
)
;
if
(
MOInsertedReg
.
isUndef
(
)
)
return
false
;
const
MachineOperand
&
MOIndex
=
MI
.
getOperand
(
3
)
;
BaseReg
.
Reg
=
MOBaseReg
.
getReg
(
)
;
BaseReg
.
SubReg
=
MOBaseReg
.
getSubReg
(
)
;
InsertedReg
.
Reg
=
MOInsertedReg
.
getReg
(
)
;
InsertedReg
.
SubReg
=
MOInsertedReg
.
getSubReg
(
)
;
InsertedReg
.
SubIdx
=
ARM
::
ssub_0
+
MOIndex
.
getImm
(
)
;
return
true
;
}
llvm_unreachable
(
"Target dependent opcode missing"
)
;
}
</s>

Target-dependent implementation of getInsertSubregInputs .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Split basic blocks at barrier"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"\nrs6000_legitimize_address: mode %s, old code %s, "

"\nrs6000_legitimize_address: mode %s, code %s, no change:\n"

Debug version of rs6000_legitimize_address .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> SDValue AArch64TargetLowering :: BuildSDIVPow2 ( SDNode * N , const APInt & Divisor , SelectionDAG & DAG , SmallVectorImpl < SDNode * > & Created ) const { AttributeList Attr = DAG . getMachineFunction ( ) . getFunction ( ) . getAttributes ( ) ; if ( isIntDivCheap ( N -> getValueType ( 0 ) , Attr ) ) return SDValue ( N , 0 ) ; EVT VT = N -> getValueType ( 0 ) ; if ( ( VT != MVT :: i32 && VT != MVT :: i64 ) || ! ( Divisor . isPowerOf2 ( ) || Divisor . isNegatedPowerOf2 ( ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( 0 ) ; unsigned Lg2 = Divisor . countTrailingZeros ( ) ; SDValue Zero = DAG . getConstant ( 0 , DL , VT ) ; SDValue Pow2MinusOne = DAG . getConstant ( ( 1ULL << Lg2 ) - 1 , DL , VT ) ; SDValue CCVal ; SDValue Cmp = getAArch64Cmp ( N0 , Zero , ISD :: SETLT , CCVal , DAG , DL ) ; SDValue Add = DAG . getNode ( ISD :: ADD , DL , VT , N0 , Pow2MinusOne ) ; SDValue CSel = DAG . getNode ( AArch64ISD :: CSEL , DL , VT , Add , N0 , CCVal , Cmp ) ; Created . push_back ( Cmp . getNode ( ) ) ; Created . push_back ( Add . getNode ( ) ) ; Created . push_back ( CSel . getNode ( ) ) ; SDValue SRA = DAG . getNode ( ISD :: SRA , DL , VT , CSel , DAG . getConstant ( Lg2 , DL , MVT :: i64 ) ) ; if ( Divisor . isNonNegative ( ) ) return SRA ; Created . push_back ( SRA . getNode ( ) ) ; return DAG . getNode ( ISD :: SUB , DL , VT , DAG . getConstant ( 0 , DL , VT ) , SRA ) ; } </s>

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators .


<s> static void mark_swaps_for_removal ( swap_web_entry * insn_entry , unsigned int i ) { rtx insn = insn_entry [ i ] . insn ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; if ( insn_entry [ i ] . is_load ) { df_ref def ; FOR_EACH_INSN_INFO_DEF ( def , insn_info ) { struct df_link * link = DF_REF_CHAIN ( def ) ; while ( link ) { rtx use_insn = DF_REF_INSN ( link -> ref ) ; insn_entry [ INSN_UID ( use_insn ) ] . will_delete = 1 ; link = link -> next ; } } } else if ( insn_entry [ i ] . is_store ) { df_ref use ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { machine_mode mode = GET_MODE ( DF_REF_REG ( use ) ) ; if ( ! VECTOR_MODE_P ( mode ) ) continue ; struct df_link * link = DF_REF_CHAIN ( use ) ; while ( link ) { rtx def_insn = DF_REF_INSN ( link -> ref ) ; insn_entry [ INSN_UID ( def_insn ) ] . will_delete = 1 ; link = link -> next ; } } } } </s>

Mark the xxswapdi instructions associated with permuting loads and stores for removal . Note that we only flag them for deletion here , as there is a possibility of a swap being reached from multiple loads , etc .


<s> void crx_init_cumulative_args ( CUMULATIVE_ARGS * cum , tree fntype , rtx libfunc ATTRIBUTE_UNUSED ) { tree param , next_param ; cum -> ints = 0 ; for ( param = ( fntype ) ? TYPE_ARG_TYPES ( fntype ) : 0 ; param != ( tree ) 0 ; param = next_param ) { next_param = TREE_CHAIN ( param ) ; if ( next_param == ( tree ) 0 && TREE_VALUE ( param ) != void_type_node ) { cum -> ints = - 1 ; return ; } } } </s>

Implements the macro INIT_CUMULATIVE_ARGS defined in crx.h .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { TII = MF . getSubtarget < PPCSubtarget > ( ) . getInstrInfo ( ) ; LIS = & getAnalysis < LiveIntervals > ( ) ; bool Changed = false ; for ( MachineBasicBlock & B : llvm :: make_early_inc_range ( MF ) ) if ( processBlock ( B ) ) Changed = true ; return Changed ; } </s>


<s> static int s390_memory_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t rclass ATTRIBUTE_UNUSED , bool in ATTRIBUTE_UNUSED ) { return 2 ; } </s>


"getBranchTargetOpValue expects only expressions or immediates"

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s>
static
bool
ix86_function_ok_for_sibcall
(
tree
decl
,
tree
exp
)
{
tree
type
,
decl_or_type
;
rtx
a
,
b
;
bool
bind_global
=
decl
&&
!
targetm
.
binds_local_p
(
decl
)
;
if
(
ix86_function_naked
(
current_function_decl
)
)
return
false
;
if
(
cfun
->
machine
->
no_caller_saved_registers
)
return
false
;
if
(
!
TARGET_MACHO
&&
!
TARGET_64BIT
&&
flag_pic
&&
flag_plt
&&
bind_global
)
return
false
;
if
(
ix86_minimum_incoming_stack_boundary
(
true
)
<
PREFERRED_STACK_BOUNDARY
)
return
false
;
if
(
decl
)
{
decl_or_type
=
decl
;
type
=
TREE_TYPE
(
decl
)
;
}
else
{
type
=
CALL_EXPR_FN
(
exp
)
;
type
=
TREE_TYPE
(
type
)
;
type
=
TREE_TYPE
(
type
)
;
decl_or_type
=
type
;
}
if
(
(
OUTGOING_REG_PARM_STACK_SPACE
(
type
)
!=
OUTGOING_REG_PARM_STACK_SPACE
(
TREE_TYPE
(
current_function_decl
)
)
)
||
(
REG_PARM_STACK_SPACE
(
decl_or_type
)
!=
REG_PARM_STACK_SPACE
(
current_function_decl
)
)
)
{
maybe_complain_about_tail_call
(
exp
,
"inconsistent size of stack space"
" allocated for arguments which are"
" passed in registers"
)
;
return
false
;
}
a
=
ix86_function_value
(
TREE_TYPE
(
exp
)
,
decl_or_type
,
false
)
;
b
=
ix86_function_value
(
TREE_TYPE
(
DECL_RESULT
(
cfun
->
decl
)
)
,
cfun
->
decl
,
false
)
;
if
(
STACK_REG_P
(
a
)
||
STACK_REG_P
(
b
)
)
{
if
(
!
rtx_equal_p
(
a
,
b
)
)
return
false
;
}
else
if
(
VOID_TYPE_P
(
TREE_TYPE
(
DECL_RESULT
(
cfun
->
decl
)
)
)
)
;
else
if
(
!
rtx_equal_p
(
a
,
b
)
)
return
false
;
if
(
TARGET_64BIT
)
{
if
(
cfun
->
machine
->
call_abi
==
MS_ABI
&&
ix86_function_type_abi
(
type
)
==
SYSV_ABI
)
return
false
;
}
else
{
if
(
!
decl
||
(
bind_global
&&
flag_pic
&&
!
flag_plt
)
||
(
TARGET_DLLIMPORT_DECL_ATTRIBUTES
&&
DECL_DLLIMPORT_P
(
decl
)
)
||
flag_force_indirect_call
)
{
if
(
ix86_function_regparm
(
type
,
decl
)
>=
3
&&
!
cfun
->
machine
->
arg_reg_available
)
return
false
;
}
}
if
(
decl
&&
ix86_use_pseudo_pic_reg
(
)
)
{
cgraph_node
*
node
=
cgraph_node
::
get
(
decl
)
;
if
(
node
&&
node
->
ifunc_resolver
)
return
false
;
}
if
(
(
(
flag_cf_protection
&
(
CF_RETURN
|
CF_BRANCH
)
)
==
(
CF_RETURN
|
CF_BRANCH
)
)
&&
lookup_attribute
(
"indirect_return"
,
TYPE_ATTRIBUTES
(
type
)
)
&&
!
lookup_attribute
(
"indirect_return"
,
TYPE_ATTRIBUTES
(
TREE_TYPE
(
cfun
->
decl
)
)
)
)
return
false
;
return
true
;
}
</s>

Decide whether we can make a sibling call to a function . DECL is the declaration of the function being targeted by the call and EXP is the CALL_EXPR representing the call .


<s> rtx rs6000_address_for_altivec ( rtx x ) { gcc_assert ( MEM_P ( x ) ) ; if ( ! altivec_indexed_or_indirect_operand ( x , GET_MODE ( x ) ) ) { rtx addr = XEXP ( x , 0 ) ; int strict_p = ( reload_in_progress || reload_completed ) ; if ( ! legitimate_indexed_address_p ( addr , strict_p ) && ! legitimate_indirect_address_p ( addr , strict_p ) ) addr = copy_to_mode_reg ( Pmode , addr ) ; addr = gen_rtx_AND ( Pmode , addr , GEN_INT ( - 16 ) ) ; x = change_address ( x , GET_MODE ( x ) , addr ) ; } return x ; } </s>

Given a memory reference , if it is not in the form for altivec memory reference instructions ( i.e . reg or reg+reg addressing with AND of -16 ) , convert to the altivec format .


<s> void F2003fMCAsmStreamer :: emitExplicitComments ( ) { StringRef Comments = ExplicitCommentToEmit ; if ( ! Comments . empty ( ) ) OS << Comments ; ExplicitCommentToEmit . clear ( ) ; } </s>


<s>
void
final_prescan_insn
(
rtx_insn
*
insn
,
rtx
*
opvec
ATTRIBUTE_UNUSED
,
int
noperands
ATTRIBUTE_UNUSED
)
{
if
(
TARGET_DUMPISIZE
)
fprintf
(
asm_out_file
,
"\n! at %04x\n"
,
INSN_ADDRESSES
(
INSN_UID
(
insn
)
)
)
;
if
(
TARGET_RELAX
)
{
rtx
note
;
note
=
find_reg_note
(
insn
,
REG_LABEL_OPERAND
,
NULL_RTX
)
;
if
(
note
)
{
rtx
pattern
;
pattern
=
PATTERN
(
insn
)
;
if
(
GET_CODE
(
pattern
)
==
PARALLEL
)
pattern
=
XVECEXP
(
pattern
,
0
,
0
)
;
switch
(
GET_CODE
(
pattern
)
)
{
case
SET
:
if
(
GET_CODE
(
SET_SRC
(
pattern
)
)
!=
CALL
&&
get_attr_type
(
insn
)
!=
TYPE_SFUNC
)
{
targetm
.
asm_out
.
internal_label
(
asm_out_file
,
"L"
,
CODE_LABEL_NUMBER
(
XEXP
(
note
,
0
)
)
)
;
break
;
}
case
CALL
:
asm_fprintf
(
asm_out_file
,
"\t.uses %LL%d\n"
,
CODE_LABEL_NUMBER
(
XEXP
(
note
,
0
)
)
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
}
}
</s>

If defined , a C statement to be executed just prior to the output of assembler code for INSN , to modify the extracted operands so they will be output differently . Here the argument OPVEC is the vector containing the operands extracted from INSN , and NOPERANDS is the number of elements of the vector which contain meaningful data for this insn . The contents of this vector are what will be used to convert the insn template into assembler code , so you can change the assembler output by changing the contents of the vector . We use it to check if the current insn needs a nop in front of it because of load delays , and also to update the delay slot statistics .


<s> bool AMDGPUTargetLowering :: isKnownNeverNaNForTargetNode ( SDValue Op , const SelectionDAG & DAG , bool SNaN , unsigned Depth ) const { unsigned Opcode = Op . getOpcode ( ) ; switch ( Opcode ) { case AMDGPUISD :: FMIN_LEGACY : case AMDGPUISD :: FMAX_LEGACY : { if ( SNaN ) return true ; return false ; } case AMDGPUISD :: FMUL_LEGACY : case AMDGPUISD :: CVT_PKRTZ_F16_F32 : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( 0 ) , SNaN , Depth + 1 ) && DAG . isKnownNeverNaN ( Op . getOperand ( 1 ) , SNaN , Depth + 1 ) ; } case AMDGPUISD :: FMED3 : case AMDGPUISD :: FMIN3 : case AMDGPUISD :: FMAX3 : case AMDGPUISD :: FMAD_FTZ : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( 0 ) , SNaN , Depth + 1 ) && DAG . isKnownNeverNaN ( Op . getOperand ( 1 ) , SNaN , Depth + 1 ) && DAG . isKnownNeverNaN ( Op . getOperand ( 2 ) , SNaN , Depth + 1 ) ; } case AMDGPUISD :: CVT_F32_UBYTE0 : case AMDGPUISD :: CVT_F32_UBYTE1 : case AMDGPUISD :: CVT_F32_UBYTE2 : case AMDGPUISD :: CVT_F32_UBYTE3 : return true ; case AMDGPUISD :: RCP : case AMDGPUISD :: RSQ : case AMDGPUISD :: RCP_LEGACY : case AMDGPUISD :: RSQ_LEGACY : case AMDGPUISD :: RSQ_CLAMP : { if ( SNaN ) return true ; return false ; } case AMDGPUISD :: LDEXP : case AMDGPUISD :: FRACT : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( 0 ) , SNaN , Depth + 1 ) ; } case AMDGPUISD :: DIV_SCALE : case AMDGPUISD :: DIV_FMAS : case AMDGPUISD :: DIV_FIXUP : case AMDGPUISD :: TRIG_PREOP : return SNaN ; case AMDGPUISD :: SIN_HW : case AMDGPUISD :: COS_HW : { return SNaN ; } case ISD :: INTRINSIC_WO_CHAIN : { unsigned IntrinsicID = cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ; switch ( IntrinsicID ) { case Intrinsic :: amdgcn_cubeid : return true ; case Intrinsic :: amdgcn_frexp_mant : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( 1 ) , SNaN , Depth + 1 ) ; } case Intrinsic :: amdgcn_cvt_pkrtz : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( 1 ) , SNaN , Depth + 1 ) && DAG . isKnownNeverNaN ( Op . getOperand ( 2 ) , SNaN , Depth + 1 ) ; } case Intrinsic :: amdgcn_fdot2 : return SNaN ; default : return false ; } } default : return false ; } } </s>


<s>
unsigned
assignCustomValue
(
const
ARMCallLowering
::
ArgInfo
&
Arg
,
ArrayRef
<
CCValAssign
>
VAs
)
override
{
CCValAssign
VA
=
VAs
[
0
]
;
assert
(
VA
.
needsCustom
(
)
&&
"Value doesn't need custom handling"
)
;
assert
(
VA
.
getValVT
(
)
==
MVT
::
f64
&&
"Unsupported type"
)
;
CCValAssign
NextVA
=
VAs
[
1
]
;
assert
(
NextVA
.
needsCustom
(
)
&&
"Value doesn't need custom handling"
)
;
assert
(
NextVA
.
getValVT
(
)
==
MVT
::
f64
&&
"Unsupported type"
)
;
assert
(
VA
.
getValNo
(
)
==
NextVA
.
getValNo
(
)
&&
"Values belong to different arguments"
)
;
assert
(
VA
.
isRegLoc
(
)
&&
"Value should be in reg"
)
;
assert
(
NextVA
.
isRegLoc
(
)
&&
"Value should be in reg"
)
;
unsigned
NewRegs
[
]
=
{
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
32
)
)
,
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
32
)
)
}
;
assignValueToReg
(
NewRegs
[
0
]
,
VA
.
getLocReg
(
)
,
VA
)
;
assignValueToReg
(
NewRegs
[
1
]
,
NextVA
.
getLocReg
(
)
,
NextVA
)
;
bool
IsLittle
=
MIRBuilder
.
getMF
(
)
.
getSubtarget
<
ARMSubtarget
>
(
)
.
isLittle
(
)
;
if
(
!
IsLittle
)
std
::
swap
(
NewRegs
[
0
]
,
NewRegs
[
1
]
)
;
MIRBuilder
.
buildSequence
(
Arg
.
Reg
,
NewRegs
,
{
0
,
32
}
)
;
return
1
;
}
</s>

Handle custom values , which may be passed into one or more of VAs .


<s> TargetPassConfig * mprocTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new mprocPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> bool TeakRegisterInfo :: needsFrameBaseReg ( MachineInstr * MI , int64_t Offset ) const { return false ; } </s>

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s> const MipsSubtarget * MipsTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool hasMips16Attr = ! F . getFnAttribute ( "mips16" ) . hasAttribute ( Attribute :: None ) ; bool hasNoMips16Attr = ! F . getFnAttribute ( "nomips16" ) . hasAttribute ( Attribute :: None ) ; bool HasMicroMipsAttr = ! F . getFnAttribute ( "micromips" ) . hasAttribute ( Attribute :: None ) ; bool HasNoMicroMipsAttr = ! F . getFnAttribute ( "nomicromips" ) . hasAttribute ( Attribute :: None ) ; bool softFloat = F . hasFnAttribute ( "use-soft-float" ) && F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( hasMips16Attr ) FS += FS . empty ( ) ? "+mips16" : ",+mips16" ; else if ( hasNoMips16Attr ) FS += FS . empty ( ) ? "-mips16" : ",-mips16" ; if ( HasMicroMipsAttr ) FS += FS . empty ( ) ? "+micromips" : ",+micromips" ; else if ( HasNoMicroMipsAttr ) FS += FS . empty ( ) ? "-micromips" : ",-micromips" ; if ( softFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < MipsSubtarget > ( TargetTriple , CPU , FS , isLittle , * this , Options . StackAlignmentOverride ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

Mips Mips Mips "target-cpu" "target-features" Mips "mips16" Mips "nomips16" Mips "micromips" Mips "nomicromips" "use-soft-float" "use-soft-float" "true" Mips "+mips16" ",+mips16" Mips "-mips16" ",-mips16" Mips "+micromips" ",+micromips" Mips "-micromips" ",-micromips" "+soft-float" ",+soft-float" Mips


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


"instructions, but the target does not support ARM mode execution."


<s> static int nds32_register_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t from , reg_class_t to ) { if ( from == HIGH_REGS || to == HIGH_REGS ) return 6 ; return 2 ; } </s>

Describing Relative Costs of Operations .


<s> EVT AArch64TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { bool Fast ; const Function * F = MF . getFunction ( ) ; if ( Subtarget -> hasFPARMv8 ( ) && ! IsMemset && Size >= 16 && ! F -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoImplicitFloat ) && ( memOpAlign ( SrcAlign , DstAlign , 16 ) || ( allowsUnalignedMemoryAccesses ( MVT :: f128 , 0 , & Fast ) && Fast ) ) ) return MVT :: f128 ; return Size >= 8 ? MVT :: i64 : MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> static rtx arc_builtin_setjmp_frame_value ( void ) { return gen_raw_REG ( Pmode , FRAME_POINTER_REGNUM ) ; } </s>

Return the frame pointer value to be backed up in the setjmp buffer .


<s> static enum mips_split_type mips_insn_split_type ( rtx insn ) { basic_block bb = BLOCK_FOR_INSN ( insn ) ; if ( bb ) { if ( optimize_bb_for_speed_p ( bb ) ) return SPLIT_FOR_SPEED ; else return SPLIT_FOR_SIZE ; } return SPLIT_IF_NECESSARY ; } </s>

Return the split type for instruction INSN .


<s> static bool supported_simd_type ( tree t ) { if ( SCALAR_FLOAT_TYPE_P ( t ) || INTEGRAL_TYPE_P ( t ) || POINTER_TYPE_P ( t ) ) { HOST_WIDE_INT s = tree_to_shwi ( TYPE_SIZE_UNIT ( t ) ) ; return s == 1 || s == 2 || s == 4 || s == 8 ; } return false ; } </s>

Return true for types that could be supported as SIMD return or argument types .


<s> static void replace_swapped_aligned_load ( swap_web_entry * insn_entry , rtx swap_insn ) { unsigned uid = INSN_UID ( swap_insn ) ; gcc_assert ( insn_entry [ uid ] . is_swap && ! insn_entry [ uid ] . is_load ) ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( swap_insn ) ; df_ref use = DF_INSN_INFO_USES ( insn_info ) ; struct df_link * def_link = DF_REF_CHAIN ( use ) ; gcc_assert ( def_link && ! def_link -> next ) ; gcc_assert ( def_link && def_link -> ref && ! DF_REF_IS_ARTIFICIAL ( def_link -> ref ) && ! def_link -> next ) ; rtx_insn * def_insn = DF_REF_INSN ( def_link -> ref ) ; unsigned uid2 = INSN_UID ( def_insn ) ; gcc_assert ( insn_entry [ uid2 ] . is_load && insn_entry [ uid2 ] . is_swap ) ; rtx body = PATTERN ( def_insn ) ; gcc_assert ( ( GET_CODE ( body ) == SET ) && ( GET_CODE ( SET_SRC ( body ) ) == VEC_SELECT ) && ( GET_CODE ( XEXP ( SET_SRC ( body ) , 0 ) ) == MEM ) ) ; rtx src_exp = XEXP ( SET_SRC ( body ) , 0 ) ; enum machine_mode mode = GET_MODE ( src_exp ) ; rtx lvx = rs6000_gen_lvx ( mode , SET_DEST ( body ) , src_exp ) ; rtx_insn * new_insn = emit_insn_before ( lvx , def_insn ) ; rtx new_body = PATTERN ( new_insn ) ; gcc_assert ( ( GET_CODE ( new_body ) == SET ) && ( GET_CODE ( SET_SRC ( new_body ) ) == MEM ) ) ; set_block_for_insn ( new_insn , BLOCK_FOR_INSN ( def_insn ) ) ; df_insn_rescan ( new_insn ) ; df_insn_delete ( def_insn ) ; remove_insn ( def_insn ) ; def_insn -> set_deleted ( ) ; mark_swaps_for_removal ( insn_entry , uid ) ; replace_swap_with_copy ( insn_entry , uid ) ; } </s>

Given that SWAP_INSN represents a swap of an aligned load-with-swap , replace the load with an aligned load ( without swap ) and replace the swap with a copy insn .


<s> bool X86TTIImpl :: isLegalMaskedScatter ( Type * DataType ) { if ( ! ST -> hasAVX512 ( ) ) return false ; return isLegalMaskedGather ( DataType ) ; } </s>

Return true if the target supports masked scatter .


<s> void MipsFrameInfo :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; const MipsRegisterInfo * RegInfo = static_cast < const MipsRegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; const MipsInstrInfo & TII = * static_cast < const MipsInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; bool isPIC = ( MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ; adjustMipsStackFrame ( MF ) ; unsigned StackSize = MFI -> getStackSize ( ) ; if ( StackSize == 0 && ! MFI -> adjustsStack ( ) ) return ; int FPOffset = MipsFI -> getFPStackOffset ( ) ; int RAOffset = MipsFI -> getRAStackOffset ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: NOREORDER ) ) ; if ( isPIC && STI . isABI_O32 ( ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: CPLOAD ) ) . addReg ( RegInfo -> getPICCallReg ( ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: NOMACRO ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDiu ) , Mips :: SP ) . addReg ( Mips :: SP ) . addImm ( - StackSize ) ; if ( MFI -> adjustsStack ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: SW ) ) . addReg ( Mips :: RA ) . addImm ( RAOffset ) . addReg ( Mips :: SP ) ; } if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: SW ) ) . addReg ( Mips :: FP ) . addImm ( FPOffset ) . addReg ( Mips :: SP ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDu ) , Mips :: FP ) . addReg ( Mips :: SP ) . addReg ( Mips :: ZERO ) ; } if ( MipsFI -> needGPSaveRestore ( ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: CPRESTORE ) ) . addImm ( MipsFI -> getGPStackOffset ( ) ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips 0 Mips Mips Mips::NOREORDER Mips::CPLOAD Mips::NOMACRO Mips::ADDiu Mips::SP Mips::SP Mips::SW Mips::RA Mips::SP Mips::SW Mips::FP Mips::SP Mips::ADDu Mips::FP Mips::SP Mips::ZERO Mips Mips::CPRESTORE Mips


<s> static bool rs6000_secondary_reload_simple_move ( enum rs6000_reg_type to_type , enum rs6000_reg_type from_type , machine_mode mode ) { int size = GET_MODE_SIZE ( mode ) ; if ( TARGET_DIRECT_MOVE && ( ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) || ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) { if ( TARGET_POWERPC64 ) { if ( size == 8 ) return true ; if ( size == 16 && TARGET_P9_VECTOR && mode != TDmode ) return true ; } if ( TARGET_P8_VECTOR ) { if ( mode == SImode ) return true ; if ( TARGET_P9_VECTOR && ( mode == HImode || mode == QImode ) ) return true ; } if ( mode == SDmode ) return true ; } else if ( ( size == 4 || ( TARGET_POWERPC64 && size == 8 ) ) && ( ( to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE ) || ( to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; return false ; } </s>

Helper function for rs6000_secondary_reload to return true if a move to a different register classe is really a simple move .


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) { switch ( Op . getOpcode ( ) ) { case ISD :: AND : return LowerANDOR ( Op , DAG ) ; case ISD :: BRCOND : return LowerBRCOND ( Op , DAG ) ; case ISD :: CALL : return LowerCALL ( Op , DAG ) ; case ISD :: ConstantPool : return LowerConstantPool ( Op , DAG ) ; case ISD :: DYNAMIC_STACKALLOC : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case ISD :: FORMAL_ARGUMENTS : return LowerFORMAL_ARGUMENTS ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return LowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( Op , DAG ) ; case ISD :: OR : return LowerANDOR ( Op , DAG ) ; case ISD :: RET : return LowerRET ( Op , DAG ) ; case ISD :: SELECT : return LowerSELECT ( Op , DAG ) ; case ISD :: SETCC : return LowerSETCC ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::AND ISD::BRCOND ISD::CALL ISD::ConstantPool ISD::DYNAMIC_STACKALLOC ISD::FORMAL_ARGUMENTS ISD::GlobalAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::OR ISD::RET ISD::SELECT ISD::SETCC


<s> BitVector MipsRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t ReservedCPURegs [ ] = { Mips :: ZERO , Mips :: AT , Mips :: K0 , Mips :: K1 , Mips :: SP } ; static const uint16_t ReservedCPU64Regs [ ] = { Mips :: ZERO_64 , Mips :: AT_64 , Mips :: K0_64 , Mips :: K1_64 , Mips :: SP_64 } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: const_iterator RegIter ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; if ( Subtarget . hasMips64 ( ) ) { for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPU64Regs ) ; ++ I ) Reserved . set ( ReservedCPU64Regs [ I ] ) ; for ( RegIter Reg = Mips :: AFGR64RegClass . begin ( ) , EReg = Mips :: AFGR64RegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } else { for ( RegIter Reg = Mips :: CPU64RegsRegClass . begin ( ) , EReg = Mips :: CPU64RegsRegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; for ( RegIter Reg = Mips :: FGR64RegClass . begin ( ) , EReg = Mips :: FGR64RegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) ) { Reserved . set ( Mips :: FP ) ; Reserved . set ( Mips :: FP_64 ) ; } Reserved . set ( Mips :: HWR29 ) ; Reserved . set ( Mips :: HWR29_64 ) ; if ( Subtarget . inMips16Mode ( ) ) { Reserved . set ( Mips :: RA ) ; Reserved . set ( Mips :: RA_64 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
static
void
xtensa_asm_trampoline_template
(
FILE
*
stream
)
{
bool
use_call0
=
(
TARGET_CONST16
||
TARGET_ABSOLUTE_LITERALS
)
;
fprintf
(
stream
,
"\t.begin no-transform\n"
)
;
if
(
TARGET_WINDOWED_ABI
)
{
fprintf
(
stream
,
"\tentry\tsp, %d\n"
,
MIN_FRAME_SIZE
)
;
if
(
use_call0
)
{
fprintf
(
stream
,
"\tmov\ta10, a0\n"
)
;
fprintf
(
stream
,
"\tcall0\t.Lskipconsts\n"
)
;
}
else
fprintf
(
stream
,
"\tj\t.Lskipconsts\n"
)
;
fprintf
(
stream
,
"\t.align\t4\n"
)
;
fprintf
(
stream
,
".Lchainval:%s0\n"
,
integer_asm_op
(
4
,
TRUE
)
)
;
fprintf
(
stream
,
".Lfnaddr:%s0\n"
,
integer_asm_op
(
4
,
TRUE
)
)
;
fprintf
(
stream
,
".Lskipconsts:\n"
)
;
if
(
use_call0
)
{
fprintf
(
stream
,
"\taddi\ta0, a0, 3\n"
)
;
fprintf
(
stream
,
"\tl32i\ta9, a0, 0\n"
)
;
fprintf
(
stream
,
"\tl32i\ta8, a0, 4\n"
)
;
}
else
{
fprintf
(
stream
,
"\tl32r\ta9, .Lchainval\n"
)
;
fprintf
(
stream
,
"\tl32r\ta8, .Lfnaddr\n"
)
;
}
fprintf
(
stream
,
"\ts32i\ta9, sp, %d\n"
,
MIN_FRAME_SIZE
20
)
;
fprintf
(
stream
,
"\tl32i\ta9, a8, 0\n"
)
;
fprintf
(
stream
,
"\textui\ta9, a9, %d, 12\n"
,
TARGET_BIG_ENDIAN
8
:
12
)
;
fprintf
(
stream
,
"\tslli\ta9, a9, 3\n"
)
;
fprintf
(
stream
,
"\taddi\ta9, a9, %d\n"
,
MIN_FRAME_SIZE
)
;
fprintf
(
stream
,
"\tsub\ta9, sp, a9\n"
)
;
fprintf
(
stream
,
"\tmovsp\tsp, a9\n"
)
;
if
(
use_call0
)
fprintf
(
stream
,
"\tmov\ta0, a10\n"
)
;
fprintf
(
stream
,
"\taddi\ta8, a8, 3\n"
)
;
fprintf
(
stream
,
"\tjx\ta8\n"
)
;
if
(
use_call0
)
fprintf
(
stream
,
"\t.byte\t0\n"
)
;
else
fprintf
(
stream
,
"\tnop\n"
)
;
}
else
{
if
(
use_call0
)
{
fprintf
(
stream
,
"\tmov\ta10, a0\n"
)
;
fprintf
(
stream
,
"\tcall0\t.Lskipconsts\n"
)
;
}
else
fprintf
(
stream
,
"\tj\t.Lskipconsts\n"
)
;
fprintf
(
stream
,
"\t.align\t4\n"
)
;
fprintf
(
stream
,
".Lchainval:%s0\n"
,
integer_asm_op
(
4
,
TRUE
)
)
;
fprintf
(
stream
,
".Lfnaddr:%s0\n"
,
integer_asm_op
(
4
,
TRUE
)
)
;
fprintf
(
stream
,
".Lskipconsts:\n"
)
;
if
(
use_call0
)
{
fprintf
(
stream
,
"\taddi\ta0, a0, 3\n"
)
;
fprintf
(
stream
,
"\tl32i\ta8, a0, 0\n"
)
;
fprintf
(
stream
,
"\tl32i\ta9, a0, 4\n"
)
;
fprintf
(
stream
,
"\tmov\ta0, a10\n"
)
;
}
else
{
fprintf
(
stream
,
"\tl32r\ta8, .Lchainval\n"
)
;
fprintf
(
stream
,
"\tl32r\ta9, .Lfnaddr\n"
)
;
}
fprintf
(
stream
,
"\tjx\ta9\n"
)
;
if
(
use_call0
)
fprintf
(
stream
,
"\t.byte\t0\n"
)
;
else
fprintf
(
stream
,
"\tnop\n"
)
;
}
fprintf
(
stream
,
"\t.end no-transform\n"
)
;
}
</s>

TRAMPOLINE_TEMPLATE : For Xtensa , the trampoline must perform an ENTRY instruction with a minimal stack frame in order to get some free registers . Once the actual call target is known , the proper stack frame size is extracted from the ENTRY instruction at the target and the current frame is adjusted to match . The trampoline then transfers control to the instruction following the ENTRY at the target . Note : this assumes that the target begins with an ENTRY instruction .


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
READ_REGISTER
:
ExpandREAD_REGISTER
(
N
,
Results
,
DAG
)
;
break
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SREM
:
case
ISD
::
UREM
:
Res
=
LowerREM
(
N
,
DAG
)
;
break
;
case
ISD
::
SDIVREM
:
case
ISD
::
UDIVREM
:
Res
=
LowerDivRem
(
SDValue
(
N
,
0
)
,
DAG
)
;
assert
(
Res
.
getNumOperands
(
)
==
2
&&
"DivRem needs two values"
)
;
Results
.
push_back
(
Res
.
getValue
(
0
)
)
;
Results
.
push_back
(
Res
.
getValue
(
1
)
)
;
return
;
case
ISD
::
READCYCLECOUNTER
:
ReplaceREADCYCLECOUNTER
(
N
,
Results
,
DAG
,
Subtarget
)
;
return
;
case
ISD
::
UDIV
:
case
ISD
::
SDIV
:
assert
(
Subtarget
->
isTargetWindows
(
)
&&
"can only expand DIV on Windows"
)
;
return
ExpandDIV_Windows
(
SDValue
(
N
,
0
)
,
DAG
,
N
->
getOpcode
(
)
==
ISD
::
SDIV
,
Results
)
;
case
ISD
::
ATOMIC_CMP_SWAP
:
ReplaceCMP_SWAP_64Results
(
N
,
Results
,
DAG
)
;
return
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
ReplaceLongIntrinsic
(
N
,
Results
,
DAG
)
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

ARM
ARM
"Don't know how to custom expand this!"
ISD::READ_REGISTER
ISD::BITCAST
ISD::SRL
ISD::SRA
ISD::SREM
ISD::UREM
ISD::SDIVREM
ISD::UDIVREM
0
2
"DivRem needs two values"
0
1
ISD::READCYCLECOUNTER
ISD::UDIV
ISD::SDIV
"can only expand DIV on Windows"
0
ISD::SDIV
ISD::ATOMIC_CMP_SWAP
ISD::INTRINSIC_WO_CHAIN


<s>
void
Z80TargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
DEBUG
(
dbgs
(
)
<<
"ReplaceNodeResults: "
;
N
->
dump
(
&
DAG
)
)
;
}
</s>


<s> void GCNPassConfig :: addPreRegBankSelect ( ) { bool IsOptNone = getOptLevel ( ) == CodeGenOpt :: None ; addPass ( createAMDGPUPostLegalizeCombiner ( IsOptNone ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before the register bank selection .


<s> static bool s390_hard_regno_call_part_clobbered ( unsigned int regno , machine_mode mode ) { if ( ! TARGET_64BIT && TARGET_ZARCH && GET_MODE_SIZE ( mode ) > 4 && ( ( regno >= 6 && regno <= 15 ) || regno == 32 ) ) return true ; if ( TARGET_VX && GET_MODE_SIZE ( mode ) > 8 && ( ( ( TARGET_64BIT && regno >= 24 && regno <= 31 ) ) || ( ! TARGET_64BIT && ( regno == 18 || regno == 19 ) ) ) ) return true ; return false ; } </s>

Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED . When generating code that runs in z/Architecture mode , but conforms to the 31-bit ABI , GPRs can hold 8 bytes ; the ABI guarantees only that the lower 4 bytes are saved across calls , however .


<s> static bool classof ( const MCExpr * E ) { return E -> getKind ( ) == MCExpr :: Target ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> static void s390_chunkify_cancel ( struct constant_pool * pool_list ) { struct constant_pool * curr_pool = NULL ; rtx_insn * insn ; for ( curr_pool = pool_list ; curr_pool ; curr_pool = curr_pool -> next ) { rtx_insn * barrier = PREV_INSN ( curr_pool -> pool_insn ) ; rtx_insn * jump = barrier ? PREV_INSN ( barrier ) : NULL ; rtx_insn * label = NEXT_INSN ( curr_pool -> pool_insn ) ; if ( jump && JUMP_P ( jump ) && barrier && BARRIER_P ( barrier ) && label && LABEL_P ( label ) && GET_CODE ( PATTERN ( jump ) ) == SET && SET_DEST ( PATTERN ( jump ) ) == pc_rtx && GET_CODE ( SET_SRC ( PATTERN ( jump ) ) ) == LABEL_REF && XEXP ( SET_SRC ( PATTERN ( jump ) ) , 0 ) == label ) { remove_insn ( jump ) ; remove_insn ( barrier ) ; remove_insn ( label ) ; } remove_insn ( curr_pool -> pool_insn ) ; } for ( insn = get_insns ( ) ; insn ; ) { rtx_insn * next_insn = NEXT_INSN ( insn ) ; if ( NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == SET && GET_CODE ( SET_SRC ( PATTERN ( insn ) ) ) == UNSPEC && XINT ( SET_SRC ( PATTERN ( insn ) ) , 1 ) == UNSPEC_RELOAD_BASE ) remove_insn ( insn ) ; insn = next_insn ; } while ( pool_list ) { struct constant_pool * next = pool_list -> next ; s390_free_pool ( pool_list ) ; pool_list = next ; } } </s>

POOL_LIST is a chunk list as prepared by s390_chunkify_start . We have decided we can not use this list , so revert all changes to the current function that were done by s390_chunkify_start .


<s> bool isThumb ( ) const { return getSTI ( ) . getFeatureBits ( ) [ ARM :: ModeThumb ] ; } </s>

Tests whether the target is Thumb ( little and big endian ) .


<s> static tree rs6000_builtin_decl ( unsigned code , bool initialize_p ATTRIBUTE_UNUSED ) { HOST_WIDE_INT fnmask ; if ( code >= RS6000_BUILTIN_COUNT ) return error_mark_node ; fnmask = rs6000_builtin_info [ code ] . mask ; if ( ( fnmask & rs6000_builtin_mask ) != fnmask ) { rs6000_invalid_builtin ( ( enum rs6000_builtins ) code ) ; return error_mark_node ; } return rs6000_builtin_decls [ code ] ; } </s>

Returns the rs6000 builtin decl for CODE .


"value of %<-mfixed-range%> must have form REG1-REG2"

Parse the -mfixed-range= option string .


<s> static const char * get_round_mode_suffix ( void ) { enum attr_round_suffix s = get_attr_round_suffix ( current_output_insn ) ; switch ( s ) { case ROUND_SUFFIX_NONE : return NULL ; case ROUND_SUFFIX_NORMAL : switch ( alpha_fprm ) { case ALPHA_FPRM_NORM : return NULL ; case ALPHA_FPRM_MINF : return "m" ; case ALPHA_FPRM_CHOP : return "c" ; case ALPHA_FPRM_DYN : return "d" ; default : gcc_unreachable ( ) ; } break ; case ROUND_SUFFIX_C : return "c" ; default : gcc_unreachable ( ) ; } gcc_unreachable ( ) ; } </s>

Return the rounding mode suffix applicable to the current instruction , or NULL .


<s> const F2003fRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


runOnMachineFunction - Emit the function body .


<s> static bool s390_return_in_memory ( tree type , tree fundecl ATTRIBUTE_UNUSED ) { if ( INTEGRAL_TYPE_P ( type ) || POINTER_TYPE_P ( type ) || TREE_CODE ( type ) == OFFSET_TYPE || TREE_CODE ( type ) == REAL_TYPE ) return int_size_in_bytes ( type ) > 8 ; if ( AGGREGATE_TYPE_P ( type ) || TREE_CODE ( type ) == COMPLEX_TYPE || TREE_CODE ( type ) == VECTOR_TYPE ) return true ; return true ; } </s>

Return true if return values of type TYPE should be returned in a memory buffer whose address is passed by the caller as hidden first argument .


<s> void Nios2FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


<s> Value * AArch64TargetLowering :: emitStoreConditional ( IRBuilderBase & Builder , Value * Val , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = isReleaseOrStronger ( Ord ) ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == 128 ) { Intrinsic :: ID Int = IsRelease ? Intrinsic :: aarch64_stlxp : Intrinsic :: aarch64_stxp ; Function * Stxr = Intrinsic :: getDeclaration ( M , Int ) ; Type * Int64Ty = Type :: getInt64Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int64Ty , "lo" ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , 64 ) , Int64Ty , "hi" ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall ( Stxr , { Lo , Hi , Addr } ) ; } Intrinsic :: ID Int = IsRelease ? Intrinsic :: aarch64_stlxr : Intrinsic :: aarch64_stxr ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Stxr = Intrinsic :: getDeclaration ( M , Int , Tys ) ; const DataLayout & DL = M -> getDataLayout ( ) ; IntegerType * IntValTy = Builder . getIntNTy ( DL . getTypeSizeInBits ( Val -> getType ( ) ) ) ; Val = Builder . CreateBitCast ( Val , IntValTy ) ; CallInst * CI = Builder . CreateCall ( Stxr , { Builder . CreateZExtOrBitCast ( Val , Stxr -> getFunctionType ( ) -> getParamType ( 0 ) ) , Addr } ) ; CI -> addParamAttr ( 1 , Attribute :: get ( Builder . getContext ( ) , Attribute :: ElementType , Val -> getType ( ) ) ) ; return CI ; } </s>

Perform a store-conditional operation to Addr .


<s>
SDValue
SHUXITargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
if
(
IsVarArg
)
{
report_fatal_error
(
"VarArg not supported"
)
;
}
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_SHUXI
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
<
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
{
RetOps
.
push_back
(
Flag
)
;
}
return
DAG
.
getNode
(
SHUXIISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


"argument %d must be a constant immediate"

Expand a FCMLA lane expression EXP with code FCODE and result going to TARGET if that is convenient .


<s> static void mips_emit_loadgp ( void ) { rtx addr , offset , incoming_address , base , index , pic_reg ; pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx ; switch ( mips_current_loadgp_style ( ) ) { case LOADGP_ABSOLUTE : if ( mips_gnu_local_gp == NULL ) { mips_gnu_local_gp = gen_rtx_SYMBOL_REF ( Pmode , "__gnu_local_gp" ) ; SYMBOL_REF_FLAGS ( mips_gnu_local_gp ) |= SYMBOL_FLAG_LOCAL ; } emit_insn ( PMODE_INSN ( gen_loadgp_absolute , ( pic_reg , mips_gnu_local_gp ) ) ) ; break ; case LOADGP_OLDABI : break ; case LOADGP_NEWABI : addr = XEXP ( DECL_RTL ( current_function_decl ) , 0 ) ; offset = mips_unspec_address ( addr , SYMBOL_GOTOFF_LOADGP ) ; incoming_address = gen_rtx_REG ( Pmode , PIC_FUNCTION_ADDR_REGNUM ) ; emit_insn ( PMODE_INSN ( gen_loadgp_newabi , ( pic_reg , offset , incoming_address ) ) ) ; break ; case LOADGP_RTP : base = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( VXWORKS_GOTT_BASE ) ) ; index = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( VXWORKS_GOTT_INDEX ) ) ; emit_insn ( PMODE_INSN ( gen_loadgp_rtp , ( pic_reg , base , index ) ) ) ; break ; default : return ; } if ( TARGET_MIPS16 ) emit_insn ( PMODE_INSN ( gen_copygp_mips16 , ( pic_offset_table_rtx , pic_reg ) ) ) ; if ( ! TARGET_EXPLICIT_RELOCS || crtl -> profile ) emit_insn ( gen_loadgp_blockage ( ) ) ; } </s>

If we 're generating n32 or n64 abicalls , emit instructions to set up the global pointer .


<s> const Triple & getTargetTriple ( ) const { return TargetTriple ; } </s>

Get the target triple which is a string describing the target host .


<s> bool RISCVTargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const { return isInt < 12 > ( Imm ) ; } </s>

Return true if the specified immediate is legal icmp immediate , that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register .


<s>
bool
ARMAsmPrinter
::
doFinalization
(
Module
&
M
)
{
if
(
Subtarget
->
isTargetDarwin
(
)
)
{
TargetLoweringObjectFileMachO
&
TLOFMacho
=
static_cast
<
TargetLoweringObjectFileMachO
&
>
(
getObjFileLowering
(
)
)
;
O
<<
'\n'
;
if
(
!
GVNonLazyPtrs
.
empty
(
)
)
{
OutStreamer
.
SwitchSection
(
TLOFMacho
.
getNonLazySymbolPointerSection
(
)
)
;
EmitAlignment
(
2
)
;
for
(
StringMap
<
std
::
string
>
::
iterator
I
=
GVNonLazyPtrs
.
begin
(
)
,
E
=
GVNonLazyPtrs
.
end
(
)
;
I
!=
E
;
++
I
)
{
O
<<
I
->
second
<<
":\n"
;
O
<<
"\t.indirect_symbol "
<<
I
->
getKeyData
(
)
<<
"\n"
;
O
<<
"\t.long\t0\n"
;
}
}
if
(
!
HiddenGVNonLazyPtrs
.
empty
(
)
)
{
OutStreamer
.
SwitchSection
(
getObjFileLowering
(
)
.
getDataSection
(
)
)
;
EmitAlignment
(
2
)
;
for
(
StringMap
<
std
::
string
>
::
iterator
I
=
HiddenGVNonLazyPtrs
.
begin
(
)
,
E
=
HiddenGVNonLazyPtrs
.
end
(
)
;
I
!=
E
;
++
I
)
{
O
<<
I
->
second
<<
":\n"
;
O
<<
"\t.long "
<<
I
->
getKeyData
(
)
<<
"\n"
;
}
}
O
<<
"\t.subsections_via_symbols\n"
;
}
return
AsmPrinter
::
doFinalization
(
M
)
;
}
</s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .

ARM
ARM
2
":\n"
"\t.indirect_symbol "
"\n"
"\t.long\t0\n"
2
":\n"
"\t.long "
"\n"
"\t.subsections_via_symbols\n"


<s> machine_mode memory_vector_mode ( const function_instance & ) const OVERRIDE { return m_mode ; } </s>

If the function addresses memory , return a vector mode whose GET_MODE_NUNITS is the number of elements addressed and whose GET_MODE_INNER is the mode of a single scalar memory element .


<s> const TargetRegisterClass * Nios2RegisterInfo :: intRegClass ( unsigned Size ) const { return & Nios2 :: CPURegsRegClass ; } </s>


<s> bool X86TargetLowering :: isSafeMemOpType ( MVT VT ) const { if ( VT == MVT :: f32 ) return X86ScalarSSEf32 ; else if ( VT == MVT :: f64 ) return X86ScalarSSEf64 ; return TargetLowering :: isSafeMemOpType ( VT ) ; } </s>

Returns true if it 's safe to use load / store of the specified type to expand memcpy / memset inline .


<s> int mems_ok_for_quad_peep ( rtx mem1 , rtx mem2 ) { rtx addr1 , addr2 ; unsigned int reg1 , reg2 ; int offset1 , offset2 ; if ( MEM_VOLATILE_P ( mem1 ) || MEM_VOLATILE_P ( mem2 ) ) return 0 ; addr1 = XEXP ( mem1 , 0 ) ; addr2 = XEXP ( mem2 , 0 ) ; if ( GET_CODE ( addr1 ) == PLUS ) { if ( ! REG_P ( XEXP ( addr1 , 0 ) ) ) return 0 ; else { reg1 = REGNO ( XEXP ( addr1 , 0 ) ) ; if ( ! CONST_INT_P ( XEXP ( addr1 , 1 ) ) ) return 0 ; offset1 = INTVAL ( XEXP ( addr1 , 1 ) ) ; } } else if ( ! REG_P ( addr1 ) ) return 0 ; else { reg1 = REGNO ( addr1 ) ; offset1 = 0 ; } if ( GET_CODE ( addr2 ) == PLUS ) { if ( ! REG_P ( XEXP ( addr2 , 0 ) ) ) return 0 ; else { reg2 = REGNO ( XEXP ( addr2 , 0 ) ) ; if ( ! CONST_INT_P ( XEXP ( addr2 , 1 ) ) ) return 0 ; offset2 = INTVAL ( XEXP ( addr2 , 1 ) ) ; } } else if ( ! REG_P ( addr2 ) ) return 0 ; else { reg2 = REGNO ( addr2 ) ; offset2 = 0 ; } if ( reg1 != reg2 ) return 0 ; if ( offset2 != offset1 + 8 ) return 0 ; return 1 ; } </s>

Return 1 if addr1 and addr2 are suitable for lfq or stfq insn . addr1 and addr2 must be in consecutive memory locations ( addr2 == addr1 + 8 ) .


"Unexpected instruction for custom inserter!"

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> bool isImm ( ) const override { return Kind == Immediate ; } </s>


<s> unsigned GCNSubtarget :: getOccupancyWithNumVGPRs ( unsigned VGPRs ) const { unsigned MaxWaves = getMaxWavesPerEU ( ) ; unsigned Granule = getVGPRAllocGranule ( ) ; if ( VGPRs < Granule ) return MaxWaves ; unsigned RoundedRegs = ( ( VGPRs + Granule - 1 ) / Granule ) * Granule ; return std :: min ( getTotalNumVGPRs ( ) / RoundedRegs , MaxWaves ) ; } </s>

Return the maximum number of waves per SIMD for kernels using VGPRs VGPRs .


"***** Machine Function before Domain Reassignment *****\n"

"***** Machine Function after Domain Reassignment *****\n"


"Couldn't get MachineMemOperand for store to stack."

"Only support 4-byte stores to stack now."

"Only support GPR32 stores to stack now."

Store the specified register of the given register class to the specified stack frame index .


<s> const TargetRegisterClass * X86RegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC ) const { if ( RC == X86 :: GR8_NOREXRegisterClass ) return RC ; const TargetRegisterClass * Super = RC ; TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case X86 :: GR8RegClassID : case X86 :: GR16RegClassID : case X86 :: GR32RegClassID : case X86 :: GR64RegClassID : case X86 :: FR32RegClassID : case X86 :: FR64RegClassID : case X86 :: RFP32RegClassID : case X86 :: RFP64RegClassID : case X86 :: RFP80RegClassID : case X86 :: VR128RegClassID : case X86 :: VR256RegClassID : if ( Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; } Super = * I ++ ; } while ( Super ) ; return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .


<s> bool riscv_legitimize_move ( enum machine_mode mode , rtx dest , rtx src ) { if ( ! register_operand ( dest , mode ) && ! reg_or_0_operand ( src , mode ) ) { riscv_emit_move ( dest , force_reg ( mode , src ) ) ; return true ; } if ( CONSTANT_P ( src ) && ! move_operand ( src , mode ) ) { riscv_legitimize_const_move ( mode , dest , src ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , copy_rtx ( src ) ) ; return true ; } return false ; } </s>

If ( set DEST SRC ) is not a valid move instruction , emit an equivalent sequence that is valid .


<s> MCSymbol * WebAssemblyMCInstLower :: GetExternalSymbolSymbol ( const MachineOperand & MO ) const { const char * Name = MO . getSymbolName ( ) ; MCSymbol * Sym = Printer . GetExternalSymbolSymbol ( Name ) ; if ( isa < MCSymbolELF > ( Sym ) ) return Sym ; MCSymbolWasm * WasmSym = cast < MCSymbolWasm > ( Sym ) ; const WebAssemblySubtarget & Subtarget = Printer . getSubtarget ( ) ; if ( strcmp ( Name , "__stack_pointer" ) == 0 ) return WasmSym ; SmallVector < wasm :: ValType , 4 > Returns ; SmallVector < wasm :: ValType , 4 > Params ; GetSignature ( Subtarget , Name , Returns , Params ) ; WasmSym -> setReturns ( std :: move ( Returns ) ) ; WasmSym -> setParams ( std :: move ( Params ) ) ; WasmSym -> setIsFunction ( true ) ; return WasmSym ; } </s>

Return the MCSymbol for the specified ExternalSymbol .


<s> static rtx s390_function_value ( const_tree ret_type , const_tree fn_decl_or_type , bool outgoing ) { return s390_function_and_libcall_value ( TYPE_MODE ( ret_type ) , ret_type , fn_decl_or_type , outgoing ) ; } </s>

Define where to return a ( scalar ) value of type TYPE . If TYPE is null , define where to return a ( scalar ) value of mode MODE from a libcall .


<s> bool ia64_legitimate_constant_p ( rtx x ) { switch ( GET_CODE ( x ) ) { case CONST_INT : case LABEL_REF : return true ; case CONST_DOUBLE : if ( GET_MODE ( x ) == VOIDmode ) return true ; return CONST_DOUBLE_OK_FOR_G ( x ) ; case CONST : case SYMBOL_REF : return tls_symbolic_operand_type ( x ) == 0 ; case CONST_VECTOR : { enum machine_mode mode = GET_MODE ( x ) ; if ( mode == V2SFmode ) return ia64_extra_constraint ( x , 'Y' ) ; return ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT && GET_MODE_SIZE ( mode ) <= 8 ) ; } default : return false ; } } </s>

Return true if X is a constant that is valid for some immediate field in an instruction .


<s> static void spu_canonicalize_comparison ( int * code , rtx * op0 , rtx * op1 , bool op0_preserve_value ) { if ( ! op0_preserve_value && ( * code == LE || * code == LT || * code == LEU || * code == LTU ) ) { rtx tem = * op0 ; * op0 = * op1 ; * op1 = tem ; * code = ( int ) swap_condition ( ( enum rtx_code ) * code ) ; } } </s>

Canonicalize a comparison from one we do n't have to one we do have .


<s> void cris_asm_output_ident ( const char * string ) { if ( symtab -> state != PARSING ) return ; default_asm_output_ident_directive ( string ) ; } </s>

Queue an .ident string in the queue of top-level asm statements . If the front-end is done , we must be being called from toplev.cc . In that case , do nothing .


<s> void riscv_move_integer ( rtx temp , rtx dest , HOST_WIDE_INT value ) { struct riscv_integer_op codes [ RISCV_MAX_INTEGER_OPS ] ; machine_mode mode ; int i , num_ops ; rtx x ; mode = GET_MODE ( dest ) ; num_ops = riscv_build_integer ( codes , value , mode ) ; if ( can_create_pseudo_p ( ) && num_ops > 2 && num_ops >= riscv_split_integer_cost ( value ) ) x = riscv_split_integer ( value , mode ) ; else { x = GEN_INT ( codes [ 0 ] . value ) ; for ( i = 1 ; i < num_ops ; i ++ ) { if ( ! can_create_pseudo_p ( ) ) x = riscv_emit_set ( temp , x ) ; else x = force_reg ( mode , x ) ; x = gen_rtx_fmt_ee ( codes [ i ] . code , mode , x , GEN_INT ( codes [ i ] . value ) ) ; } } riscv_emit_set ( dest , x ) ; } </s>

Load VALUE into DEST . TEMP is as for riscv_force_temporary .


<s> void RISCVDAGToDAGISel :: PostprocessISelDAG ( ) { HandleSDNode Dummy ( CurDAG -> getRoot ( ) ) ; SelectionDAG :: allnodes_iterator Position = CurDAG -> allnodes_end ( ) ; bool MadeChange = false ; while ( Position != CurDAG -> allnodes_begin ( ) ) { SDNode * N = & * -- Position ; if ( N -> use_empty ( ) || ! N -> isMachineOpcode ( ) ) continue ; MadeChange |= doPeepholeSExtW ( N ) ; MadeChange |= doPeepholeLoadStoreADDI ( N ) ; MadeChange |= doPeepholeMaskedRVV ( N ) ; } CurDAG -> setRoot ( Dummy . getValue ( ) ) ; if ( MadeChange ) CurDAG -> RemoveDeadNodes ( ) ; } </s>

PostprocessISelDAG ( ) - This hook allows the target to hack on the graph right after selection .


<s> static bool ix86_expand_sse_fp_minmax ( rtx dest , enum rtx_code code , rtx cmp_op0 , rtx cmp_op1 , rtx if_true , rtx if_false ) { enum machine_mode mode ; bool is_min ; rtx tmp ; if ( code == LT ) ; else if ( code == UNGE ) { tmp = if_true ; if_true = if_false ; if_false = tmp ; } else return false ; if ( rtx_equal_p ( cmp_op0 , if_true ) && rtx_equal_p ( cmp_op1 , if_false ) ) is_min = true ; else if ( rtx_equal_p ( cmp_op1 , if_true ) && rtx_equal_p ( cmp_op0 , if_false ) ) is_min = false ; else return false ; mode = GET_MODE ( dest ) ; if ( ! flag_finite_math_only || ! flag_unsafe_math_optimizations ) { int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX ; rtvec v ; if_true = force_reg ( mode , if_true ) ; v = gen_rtvec ( 2 , if_true , if_false ) ; tmp = gen_rtx_UNSPEC ( mode , v , u ) ; } else { code = is_min ? SMIN : SMAX ; tmp = gen_rtx_fmt_ee ( code , mode , if_true , if_false ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , dest , tmp ) ) ; return true ; } </s>

Detect conditional moves that exactly match min/max operational semantics . Note that this is IEEE safe , as long as we do n't interchange the operands . Returns FALSE if this conditional move does n't match a MIN/MAX , and TRUE if the operation is successful and instructions are emitted .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"X86 Optimize Call Frame"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void loongarch_expand_epilogue ( bool sibcall_p ) { struct loongarch_frame_info * frame = & cfun -> machine -> frame ; HOST_WIDE_INT step1 = frame -> total_size ; HOST_WIDE_INT step2 = 0 ; rtx ra = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; rtx insn ; bool need_barrier_p = ( get_frame_size ( ) + cfun -> machine -> frame . arg_pointer_offset ) != 0 ; if ( ! sibcall_p && loongarch_can_use_return_insn ( ) ) { emit_jump_insn ( gen_return ( ) ) ; return ; } if ( cfun -> calls_alloca ) { loongarch_emit_stack_tie ( ) ; need_barrier_p = false ; rtx adjust = GEN_INT ( - frame -> hard_frame_pointer_offset ) ; if ( ! IMM12_OPERAND ( INTVAL ( adjust ) ) ) { loongarch_emit_move ( LARCH_PROLOGUE_TEMP ( Pmode ) , adjust ) ; adjust = LARCH_PROLOGUE_TEMP ( Pmode ) ; } insn = emit_insn ( gen_add3_insn ( stack_pointer_rtx , hard_frame_pointer_rtx , adjust ) ) ; rtx dwarf = NULL_RTX ; rtx minus_offset = GEN_INT ( - frame -> hard_frame_pointer_offset ) ; rtx cfa_adjust_value = gen_rtx_PLUS ( Pmode , hard_frame_pointer_rtx , minus_offset ) ; rtx cfa_adjust_rtx = gen_rtx_SET ( stack_pointer_rtx , cfa_adjust_value ) ; dwarf = alloc_reg_note ( REG_CFA_ADJUST_CFA , cfa_adjust_rtx , dwarf ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = dwarf ; } if ( ( frame -> mask | frame -> fmask ) != 0 ) { step2 = loongarch_first_stack_step ( frame ) ; step1 -= step2 ; } if ( step1 > 0 ) { loongarch_emit_stack_tie ( ) ; need_barrier_p = false ; rtx adjust = GEN_INT ( step1 ) ; if ( ! IMM12_OPERAND ( step1 ) ) { loongarch_emit_move ( LARCH_PROLOGUE_TEMP ( Pmode ) , adjust ) ; adjust = LARCH_PROLOGUE_TEMP ( Pmode ) ; } insn = emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , adjust ) ) ; rtx dwarf = NULL_RTX ; rtx cfa_adjust_rtx = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( step2 ) ) ; dwarf = alloc_reg_note ( REG_CFA_DEF_CFA , cfa_adjust_rtx , dwarf ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = dwarf ; } loongarch_for_each_saved_reg ( frame -> total_size - step2 , loongarch_restore_reg ) ; if ( need_barrier_p ) loongarch_emit_stack_tie ( ) ; if ( step2 > 0 ) { insn = emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( step2 ) ) ) ; rtx dwarf = NULL_RTX ; rtx cfa_adjust_rtx = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , const0_rtx ) ; dwarf = alloc_reg_note ( REG_CFA_DEF_CFA , cfa_adjust_rtx , dwarf ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = dwarf ; } if ( crtl -> calls_eh_return ) emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , EH_RETURN_STACKADJ_RTX ) ) ; if ( ! sibcall_p ) emit_jump_insn ( gen_simple_return_internal ( ra ) ) ; } </s>

Expand an `` epilogue '' or `` sibcall_epilogue '' pattern ; SIBCALL_P says which .


<s> bool mips_eh_uses ( unsigned int regno ) { if ( reload_completed && ! TARGET_ABSOLUTE_JUMPS ) { if ( mips_cfun_has_cprestore_slot_p ( ) ) { if ( regno == CPRESTORE_SLOT_REGNUM ) return true ; } else { if ( cfun -> machine -> global_pointer == regno ) return true ; } } return false ; } </s>


<s> SDValue XtensaTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & dl , SelectionDAG & DAG ) const { SDValue ret ; return ret ; } </s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> unsigned PPCTTIImpl :: getIntrinsicInstrCost ( Intrinsic :: ID ID , Type * RetTy , ArrayRef < Type * > Tys , FastMathFlags FMF , unsigned ScalarizationCostPassed ) { if ( ID == Intrinsic :: bswap && ST -> hasP9Vector ( ) ) return TLI -> getTypeLegalizationCost ( DL , RetTy ) . first ; return BaseT :: getIntrinsicInstrCost ( ID , RetTy , Tys , FMF , ScalarizationCostPassed ) ; } </s>

PowerPC PPC Intrinsic::ID Intrinsic::bswap


<s> MachineBasicBlock :: iterator LanaiFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static rtx nds32_expand_builtin_store ( enum insn_code icode , tree exp , rtx target ) { rtx pat ; rtx op0 = nds32_read_argument ( exp , 0 ) ; rtx op1 = nds32_read_argument ( exp , 1 ) ; rtx addr_helper = gen_reg_rtx ( insn_data [ icode ] . operand [ 1 ] . mode ) ; op0 = nds32_legitimize_argument ( icode , 0 , op0 ) ; op1 = nds32_legitimize_argument ( icode , 2 , op1 ) ; pat = GEN_FCN ( icode ) ( op0 , addr_helper , op1 ) ; if ( ! pat ) return NULL_RTX ; emit_move_insn ( addr_helper , GEN_INT ( 0 ) ) ; emit_insn ( pat ) ; return target ; } </s>


<s> unsigned LC3InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s>
bool
X86IntelAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
this
->
MF
=
&
MF
;
SetupMachineFunction
(
MF
)
;
O
<<
"\n\n"
;
EmitConstantPool
(
MF
.
getConstantPool
(
)
)
;
const
Function
*
F
=
MF
.
getFunction
(
)
;
unsigned
CC
=
F
->
getCallingConv
(
)
;
if
(
CC
==
CallingConv
::
X86_StdCall
||
CC
==
CallingConv
::
X86_FastCall
)
FunctionInfoMap
[
F
]
=
*
MF
.
getInfo
<
X86MachineFunctionInfo
>
(
)
;
decorateName
(
CurrentFnName
,
F
)
;
SwitchToTextSection
(
"_text"
,
F
)
;
unsigned
FnAlign
=
4
;
if
(
F
->
hasFnAttr
(
Attribute
::
OptimizeForSize
)
)
FnAlign
=
1
;
switch
(
F
->
getLinkage
(
)
)
{
default
:
assert
(
0
&&
"Unsupported linkage type!"
)
;
case
Function
::
PrivateLinkage
:
case
Function
::
InternalLinkage
:
EmitAlignment
(
FnAlign
)
;
break
;
case
Function
::
DLLExportLinkage
:
DLLExportedFns
.
insert
(
CurrentFnName
)
;
case
Function
::
ExternalLinkage
:
O
<<
"\tpublic "
<<
CurrentFnName
<<
"\n"
;
EmitAlignment
(
FnAlign
)
;
break
;
}
O
<<
CurrentFnName
<<
"\tproc near\n"
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
!
I
->
pred_empty
(
)
)
{
printBasicBlockLabel
(
I
,
true
,
true
)
;
O
<<
'\n'
;
}
for
(
MachineBasicBlock
::
const_iterator
II
=
I
->
begin
(
)
,
E
=
I
->
end
(
)
;
II
!=
E
;
++
II
)
{
printMachineInstruction
(
II
)
;
}
}
EmitJumpTableInfo
(
MF
.
getJumpTableInfo
(
)
,
MF
)
;
O
<<
CurrentFnName
<<
"\tendp\n"
;
O
.
flush
(
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool Cpu0AsmPrinter :: lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) { MCOp = MCInstLowering . LowerOperand ( MO ) ; return MCOp . isValid ( ) ; } </s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> static bool aarch64_sve_data_mode_p ( machine_mode mode ) { return aarch64_classify_vector_mode ( mode ) & VEC_SVE_DATA ; } </s>

Return true if MODE is an SVE data vector mode ; either a single vector or a structure of vectors .


"Unexpected target call instruction operand list!"

Print the specified MCInst to the specified raw_ostream .


<s> static const char * getName ( ) { return DEBUG_TYPE ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> size_t THMToTHMStub :: size ( ) const { return m_Size ; } </s>

The number of name/type pairs is returned .


<s> bool AArch64FrameLowering :: canUseRedZone ( const MachineFunction & MF ) const { if ( ! EnableRedZone ) return false ; if ( MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoRedZone ) ) return false ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const AArch64FunctionInfo * AFI = MF . getInfo < AArch64FunctionInfo > ( ) ; unsigned NumBytes = AFI -> getLocalStackSize ( ) ; return ! ( MFI -> hasCalls ( ) || hasFP ( MF ) || NumBytes > 128 ) ; } </s>

Can this function use the red zone for local allocations .


<s> bool pass_vsetvl :: cleanup_illegal_dirty_blocks ( void ) { bool changed_p = false ; for ( const bb_info * bb : crtl -> ssa -> bbs ( ) ) { basic_block cfg_bb = bb -> cfg_bb ( ) ; const auto & prop = m_vector_manager -> vector_block_infos [ cfg_bb -> index ] . reaching_out ; if ( ! prop . valid_or_dirty_p ( ) ) continue ; if ( hard_empty_block_p ( bb , prop ) ) { m_vector_manager -> vector_block_infos [ cfg_bb -> index ] . local_dem = vector_insn_info :: get_hard_empty ( ) ; m_vector_manager -> vector_block_infos [ cfg_bb -> index ] . reaching_out = vector_insn_info :: get_hard_empty ( ) ; changed_p = true ; continue ; } } return changed_p ; } </s>


<s> unsigned X86FastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( DL , C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const auto * CI = dyn_cast < ConstantInt > ( C ) ) return X86MaterializeInt ( CI , VT ) ; if ( const auto * CFP = dyn_cast < ConstantFP > ( C ) ) return X86MaterializeFP ( CFP , VT ) ; if ( const auto * GV = dyn_cast < GlobalValue > ( C ) ) return X86MaterializeGV ( GV , VT ) ; if ( isa < UndefValue > ( C ) ) { unsigned Opc = 0 ; switch ( VT . SimpleTy ) { default : break ; case MVT :: f32 : if ( ! Subtarget -> hasSSE1 ( ) ) Opc = X86 :: LD_Fp032 ; break ; case MVT :: f64 : if ( ! Subtarget -> hasSSE2 ( ) ) Opc = X86 :: LD_Fp064 ; break ; case MVT :: f80 : Opc = X86 :: LD_Fp080 ; break ; } if ( Opc ) { Register ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; return ResultReg ; } } return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s> static void loongarch_setup_incoming_varargs ( cumulative_args_t cum , const function_arg_info & arg , int * pretend_size ATTRIBUTE_UNUSED , int no_rtl ) { CUMULATIVE_ARGS local_cum ; int gp_saved ; local_cum = * get_cumulative_args ( cum ) ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) ) loongarch_function_arg_advance ( pack_cumulative_args ( & local_cum ) , arg ) ; gp_saved = MAX_ARGS_IN_REGISTERS - local_cum . num_gprs ; if ( ! no_rtl && gp_saved > 0 ) { rtx ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , REG_PARM_STACK_SPACE ( cfun -> decl ) - gp_saved * UNITS_PER_WORD ) ; rtx mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . num_gprs + GP_ARG_FIRST , mem , gp_saved ) ; } if ( REG_PARM_STACK_SPACE ( cfun -> decl ) == 0 ) cfun -> machine -> varargs_size = gp_saved * UNITS_PER_WORD ; } </s>


<s> static void riscv_set_frame_expr ( rtx frame_pattern ) { rtx insn ; insn = get_last_insn ( ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = alloc_EXPR_LIST ( REG_FRAME_RELATED_EXPR , frame_pattern , REG_NOTES ( insn ) ) ; } </s>

Make the last instruction frame-related and note that it performs the operation described by FRAME_PATTERN .


<s>
SDValue
SystemZTargetLowering
::
LowerReturn
(
SDValue
Chain
,
unsigned
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_SystemZ
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
if
(
RVLocs
[
i
]
.
isRegLoc
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
SDValue
ResValue
=
Outs
[
i
]
.
Val
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
SExt
)
ResValue
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
ResValue
)
;
else
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExt
)
ResValue
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
ResValue
)
;
else
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
AExt
)
ResValue
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
ResValue
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
ResValue
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>


<s>
SDValue
XCoreTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
BR_JT
:
return
LowerBR_JT
(
Op
,
DAG
)
;
case
ISD
::
LOAD
:
return
LowerLOAD
(
Op
,
DAG
)
;
case
ISD
::
STORE
:
return
LowerSTORE
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
VAARG
:
return
LowerVAARG
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
SMUL_LOHI
:
return
LowerSMUL_LOHI
(
Op
,
DAG
)
;
case
ISD
::
UMUL_LOHI
:
return
LowerUMUL_LOHI
(
Op
,
DAG
)
;
case
ISD
::
ADD
:
case
ISD
::
SUB
:
return
ExpandADDSUB
(
Op
.
getNode
(
)
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
INIT_TRAMPOLINE
:
return
LowerINIT_TRAMPOLINE
(
Op
,
DAG
)
;
case
ISD
::
ADJUST_TRAMPOLINE
:
return
LowerADJUST_TRAMPOLINE
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

XCore
XCore
ISD::GlobalAddress
ISD::GlobalTLSAddress
ISD::BlockAddress
ISD::ConstantPool
ISD::BR_JT
ISD::LOAD
ISD::STORE
ISD::SELECT_CC
ISD::VAARG
ISD::VASTART
ISD::SMUL_LOHI
ISD::UMUL_LOHI
ISD::ADD
ISD::SUB
ISD::FRAMEADDR
ISD::INIT_TRAMPOLINE
ISD::ADJUST_TRAMPOLINE
"unimplemented operand"


<s>
void
addInst
(
MachineInstr
*
MI
,
SetVector
<
MachineInstr
*
>
&
Preds
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM Loops: Adding predicated MI: "
<<
*
MI
)
;
if
(
!
Divergent
&&
!
set_difference
(
Preds
,
PredicateThen
->
Predicates
)
.
empty
(
)
)
{
Divergent
=
&
Insts
.
back
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
" - has divergent predicate: "
<<
*
Divergent
->
MI
)
;
}
Insts
.
emplace_back
(
MI
,
Preds
)
;
assert
(
Insts
.
size
(
)
<=
4
&&
"Too many instructions in VPT block!"
)
;
}
</s>

ARM
"ARM Loops: Adding predicated MI: "
" - has divergent predicate: "
4
"Too many instructions in VPT block!"


<s> bool X86TargetLowering :: areJTsAllowed ( const Function * Fn ) const { if ( Subtarget . useRetpolineIndirectBranches ( ) ) return false ; return TargetLowering :: areJTsAllowed ( Fn ) ; } </s>

Returns true if lowering to a jump table is allowed .


<s>
unsigned
char
X86Subtarget
::
classifyLocalReference
(
const
GlobalValue
*
GV
)
const
{
if
(
!
isPositionIndependent
(
)
)
return
X86II
::
MO_NO_FLAG
;
if
(
is64Bit
(
)
)
{
if
(
isTargetELF
(
)
)
{
switch
(
TM
.
getCodeModel
(
)
)
{
case
CodeModel
::
Small
:
case
CodeModel
::
Kernel
:
return
X86II
::
MO_NO_FLAG
;
case
CodeModel
::
Large
:
return
X86II
::
MO_GOTOFF
;
case
CodeModel
::
Medium
:
if
(
isa
<
Function
>
(
GV
)
)
return
X86II
::
MO_NO_FLAG
;
return
X86II
::
MO_GOTOFF
;
}
llvm_unreachable
(
"invalid code model"
)
;
}
return
X86II
::
MO_NO_FLAG
;
}
if
(
isTargetCOFF
(
)
)
return
X86II
::
MO_NO_FLAG
;
if
(
isTargetDarwin
(
)
)
{
if
(
GV
&&
(
GV
->
isDeclarationForLinker
(
)
||
GV
->
hasCommonLinkage
(
)
)
)
return
X86II
::
MO_DARWIN_NONLAZY_PIC_BASE
;
return
X86II
::
MO_PIC_BASE_OFFSET
;
}
return
X86II
::
MO_GOTOFF
;
}
</s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s> std :: unique_ptr < PBQPRAConstraint > AArch64Subtarget :: getCustomPBQPConstraints ( ) const { return balanceFPOps ( ) ? llvm :: make_unique < A57ChainingConstraint > ( ) : nullptr ; } </s>

Return PBQPConstraint ( s ) for the target .


<s> int shl_and_length ( rtx insn ) { rtx set_src , left_rtx , mask_rtx ; int attributes [ 3 ] ; set_src = SET_SRC ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) ) ; left_rtx = XEXP ( XEXP ( set_src , 0 ) , 1 ) ; mask_rtx = XEXP ( set_src , 1 ) ; shl_and_kind ( left_rtx , mask_rtx , attributes ) ; return attributes [ 1 ] ; } </s>

This is used in length attributes of the unnamed instructions corresponding to shl_and_kind return values of 1 and 2 .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 vzeroupper inserter"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool MBlazeAsmPrinter :: isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { if ( MBB -> isLandingPad ( ) || MBB -> pred_empty ( ) ) return false ; MachineBasicBlock :: const_pred_iterator PI = MBB -> pred_begin ( ) , PI2 = PI ; ++ PI2 ; if ( PI2 != MBB -> pred_end ( ) ) return false ; const MachineBasicBlock * Pred = * PI ; if ( ! Pred -> isLayoutSuccessor ( MBB ) ) return false ; if ( Pred -> empty ( ) ) return true ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> getDesc ( ) . isTerminator ( ) ) ; return I == Pred -> end ( ) || ! I -> getDesc ( ) . isBarrier ( ) ; } </s>

isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


<s> SDValue SICTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; unsigned Opc = N -> getOpcode ( ) ; switch ( Opc ) { default : break ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> unsigned HexagonTTIImpl :: getIntrinsicInstrCost ( Intrinsic :: ID ID , Type * RetTy , ArrayRef < Type * > Tys , FastMathFlags FMF , unsigned ScalarizationCostPassed , const Instruction * I ) { if ( ID == Intrinsic :: bswap ) { std :: pair < int , MVT > LT = TLI . getTypeLegalizationCost ( DL , RetTy ) ; return LT . first + 2 ; } return BaseT :: getIntrinsicInstrCost ( ID , RetTy , Tys , FMF , ScalarizationCostPassed , I ) ; } </s>

Hexagon Hexagon Intrinsic::ID Intrinsic::bswap 2


<s> static bool nios2_symbolic_constant_p ( rtx x ) { rtx base , offset ; if ( flag_pic ) return false ; if ( GET_CODE ( x ) == LABEL_REF ) return true ; else if ( CONSTANT_P ( x ) ) { split_const ( x , & base , & offset ) ; return ( SYMBOL_REF_P ( base ) && ! SYMBOL_REF_TLS_MODEL ( base ) && ! gprel_constant_p ( base ) && ! r0rel_constant_p ( base ) && SMALL_INT ( INTVAL ( offset ) ) ) ; } return false ; } </s>

Return true if X is constant expression with a reference to an `` ordinary '' symbol ; not GOT-relative , not GP-relative , not TLS .


<s> const TargetRegisterClass * KudeyarRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & Kudeyar :: GPRRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> static void get_scratch_register_on_entry ( struct scratch_reg * sr ) { int regno ; sr -> saved = false ; if ( TARGET_64BIT ) { regno = R11_REG ; } else { tree decl = current_function_decl , fntype = TREE_TYPE ( decl ) ; bool fastcall_p = lookup_attribute ( "fastcall" , TYPE_ATTRIBUTES ( fntype ) ) != NULL_TREE ; bool thiscall_p = lookup_attribute ( "thiscall" , TYPE_ATTRIBUTES ( fntype ) ) != NULL_TREE ; bool static_chain_p = DECL_STATIC_CHAIN ( decl ) ; int regparm = ix86_function_regparm ( fntype , decl ) ; int drap_regno = crtl -> drap_reg ? REGNO ( crtl -> drap_reg ) : INVALID_REGNUM ; if ( ( regparm < 1 || ( fastcall_p && ! static_chain_p ) ) && drap_regno != AX_REG ) regno = AX_REG ; else if ( thiscall_p && ! static_chain_p && drap_regno != AX_REG ) regno = AX_REG ; else if ( regparm < 2 && ! thiscall_p && drap_regno != DX_REG ) regno = DX_REG ; else if ( regparm < 3 && ! fastcall_p && ! thiscall_p && ! static_chain_p && drap_regno != CX_REG ) regno = CX_REG ; else if ( ix86_save_reg ( BX_REG , true , false ) ) regno = BX_REG ; else if ( ! ( regparm == 3 && static_chain_p ) && ix86_save_reg ( SI_REG , true , false ) ) regno = SI_REG ; else if ( ix86_save_reg ( DI_REG , true , false ) ) regno = DI_REG ; else { regno = ( drap_regno == AX_REG ? DX_REG : AX_REG ) ; sr -> saved = true ; } } sr -> reg = gen_rtx_REG ( Pmode , regno ) ; if ( sr -> saved ) { rtx_insn * insn = emit_insn ( gen_push ( sr -> reg ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } </s>

Return a short-lived scratch register for use on function entry . In 32-bit mode , it is valid only after the registers are saved in the prologue . This register must be released by means of release_scratch_register_on_entry once it is dead .


<s> static unsigned int m32c_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { unsigned int rv = m32c_hard_regno_nregs_1 ( regno , mode ) ; return rv ? rv : 1 ; } </s>

Implements HARD_REGNO_NREGS . This is complicated by the fact that different registers are different sizes from each other , * and * may be different sizes in different chip families .


<s> WebAssemblyTargetMachine :: WebAssemblyTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , TT . isArch64Bit ( ) ? "e-m:e-p:64:64-i64:64-n32:64-S128" : "e-m:e-p:32:32-i64:64-n32:64-S128" , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , CM ? * CM : CodeModel :: Large , OL ) , TLOF ( TT . isOSBinFormatELF ( ) ? static_cast < TargetLoweringObjectFile * > ( new WebAssemblyTargetObjectFileELF ( ) ) : static_cast < TargetLoweringObjectFile * > ( new WebAssemblyTargetObjectFile ( ) ) ) { this -> Options . TrapUnreachable = true ; if ( ! TT . isOSBinFormatELF ( ) ) { this -> Options . FunctionSections = true ; this -> Options . DataSections = true ; this -> Options . UniqueSectionNames = true ; } initAsmInfo ( ) ; } </s>

Create an WebAssembly architecture model .

WebAssembly WebAssembly WebAssembly "e-m:e-p:64:64-i64:64-n32:64-S128" "e-m:e-p:32:32-i64:64-n32:64-S128" WebAssembly WebAssembly


<s> bool isLegalMaskedGather ( Type * DataType , Align Alignment ) { return isLegalMaskedGatherScatter ( DataType , Alignment ) ; } </s>

Return true if the target supports masked gather .


<s> std :: pair < unsigned , const TargetRegisterClass * > XCoreTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'r' : return std :: make_pair ( 0U , & XCore :: GRRegsRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


"instruction use requires an option to be enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s>
void
HexagonHazardRecognizer
::
Reset
(
)
{
DEBUG
(
dbgs
(
)
<<
"Reset hazard recognizer\n"
)
;
Resources
->
clearResources
(
)
;
PacketNum
=
0
;
UsesDotCur
=
nullptr
;
DotCurPNum
=
1
;
UsesLoad
=
false
;
PrefVectorStoreNew
=
nullptr
;
RegDefs
.
clear
(
)
;
}
</s>


<s> bool isMachineVerifierClean ( ) const override { return false ; } </s>

Returns true if the target is expected to pass all machine verifier checks .


<s> bool mips_const_vector_same_int_p ( rtx op , machine_mode mode , HOST_WIDE_INT low , HOST_WIDE_INT high ) { HOST_WIDE_INT value ; rtx elem0 ; if ( ! mips_const_vector_same_val_p ( op , mode ) ) return false ; elem0 = CONST_VECTOR_ELT ( op , 0 ) ; if ( ! CONST_INT_P ( elem0 ) ) return false ; value = INTVAL ( elem0 ) ; return ( value >= low && value <= high ) ; } </s>

Return true if OP is a constant vector with the number of units in MODE , and each unit has the same integer value in the range [ LOW , HIGH ] .