<s> bool HexagonOptimizeSZextends :: runOnFunction ( Function & F ) { unsigned Idx = 1 ; for ( auto & Arg : F . args ( ) ) { if ( F . getAttributes ( ) . hasAttribute ( Idx , Attribute :: SExt ) ) { if ( ! isa < PointerType > ( Arg . getType ( ) ) ) { for ( auto UI = Arg . use_begin ( ) ; UI != Arg . use_end ( ) ; ) { if ( isa < SExtInst > ( * UI ) ) { Instruction * Use = cast < Instruction > ( * UI ) ; SExtInst * SI = new SExtInst ( & Arg , Use -> getType ( ) ) ; assert ( EVT :: getEVT ( SI -> getType ( ) ) == ( EVT :: getEVT ( Use -> getType ( ) ) ) ) ; ++ UI ; Use -> replaceAllUsesWith ( SI ) ; Instruction * First = & F . getEntryBlock ( ) . front ( ) ; SI -> insertBefore ( First ) ; Use -> eraseFromParent ( ) ; } else { ++ UI ; } } } } ++ Idx ; } for ( auto & B : F ) { for ( auto & I : B ) { BinaryOperator * Ashr = dyn_cast < BinaryOperator > ( & I ) ; if ( ! ( Ashr && Ashr -> getOpcode ( ) == Instruction :: AShr ) ) continue ; Value * AshrOp1 = Ashr -> getOperand ( 1 ) ; ConstantInt * C = dyn_cast < ConstantInt > ( AshrOp1 ) ; if ( ! ( C && C -> getSExtValue ( ) == 16 ) ) continue ; Instruction * Shl = dyn_cast < Instruction > ( Ashr -> getOperand ( 0 ) ) ; if ( ! ( Shl && Shl -> getOpcode ( ) == Instruction :: Shl ) ) continue ; Value * Intr = Shl -> getOperand ( 0 ) ; Value * ShlOp1 = Shl -> getOperand ( 1 ) ; C = dyn_cast < ConstantInt > ( ShlOp1 ) ; if ( ! ( C && C -> getSExtValue ( ) == 16 ) ) continue ; if ( IntrinsicInst * I = dyn_cast < IntrinsicInst > ( Intr ) ) { if ( ! intrinsicAlreadySextended ( I -> getIntrinsicID ( ) ) ) continue ; for ( auto UI = Ashr -> user_begin ( ) , UE = Ashr -> user_end ( ) ; UI != UE ; ++ UI ) { const Use & TheUse = UI . getUse ( ) ; if ( Instruction * J = dyn_cast < Instruction > ( TheUse . getUser ( ) ) ) { J -> replaceUsesOfWith ( Ashr , I ) ; } } } } } return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> rtx legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , enum machine_mode mode ATTRIBUTE_UNUSED ) { rtx constant_term = const0_rtx ; if ( TLS_SYMBOLIC_CONST ( x ) ) { x = legitimize_tls_address ( x , 0 ) ; if ( legitimate_address_p ( mode , x , FALSE ) ) return x ; } else if ( flag_pic ) { if ( SYMBOLIC_CONST ( x ) || ( GET_CODE ( x ) == PLUS && ( SYMBOLIC_CONST ( XEXP ( x , 0 ) ) || SYMBOLIC_CONST ( XEXP ( x , 1 ) ) ) ) ) x = legitimize_pic_address ( x , 0 ) ; if ( legitimate_address_p ( mode , x , FALSE ) ) return x ; } x = eliminate_constant_term ( x , & constant_term ) ; if ( GET_CODE ( constant_term ) == CONST_INT && ! TARGET_LONG_DISPLACEMENT && ! DISP_IN_RANGE ( INTVAL ( constant_term ) ) && ! ( REG_P ( x ) && REGNO_PTR_FRAME_P ( REGNO ( x ) ) ) ) { HOST_WIDE_INT lower = INTVAL ( constant_term ) & 0xfff ; HOST_WIDE_INT upper = INTVAL ( constant_term ) ^ lower ; rtx temp = gen_reg_rtx ( Pmode ) ; rtx val = force_operand ( GEN_INT ( upper ) , temp ) ; if ( val != temp ) emit_move_insn ( temp , val ) ; x = gen_rtx_PLUS ( Pmode , x , temp ) ; constant_term = GEN_INT ( lower ) ; } if ( GET_CODE ( x ) == PLUS ) { if ( GET_CODE ( XEXP ( x , 0 ) ) == REG ) { rtx temp = gen_reg_rtx ( Pmode ) ; rtx val = force_operand ( XEXP ( x , 1 ) , temp ) ; if ( val != temp ) emit_move_insn ( temp , val ) ; x = gen_rtx_PLUS ( Pmode , XEXP ( x , 0 ) , temp ) ; } else if ( GET_CODE ( XEXP ( x , 1 ) ) == REG ) { rtx temp = gen_reg_rtx ( Pmode ) ; rtx val = force_operand ( XEXP ( x , 0 ) , temp ) ; if ( val != temp ) emit_move_insn ( temp , val ) ; x = gen_rtx_PLUS ( Pmode , temp , XEXP ( x , 1 ) ) ; } } if ( constant_term != const0_rtx ) x = gen_rtx_PLUS ( Pmode , x , constant_term ) ; return x ; } </s>

Try machine-dependent ways of modifying an illegitimate address X to be legitimate . If we find one , return the new , valid address . OLDX is the address as it was before break_out_memory_refs was called . In some cases it is useful to look at this to decide what needs to be done . MODE is the mode of the operand pointed to by X .


<s> static void ix86_output_indirect_branch_via_push ( rtx call_op , const char * xasm , bool sibcall_p ) { char thunk_name_buf [ 32 ] ; char * thunk_name ; char push_buf [ 64 ] ; enum indirect_thunk_prefix need_prefix = indirect_thunk_need_prefix ( current_output_insn ) ; int regno = - 1 ; if ( cfun -> machine -> indirect_branch_type != indirect_branch_thunk_inline ) { if ( cfun -> machine -> indirect_branch_type == indirect_branch_thunk ) indirect_thunk_needed = true ; indirect_thunk_name ( thunk_name_buf , regno , need_prefix , false ) ; thunk_name = thunk_name_buf ; } else thunk_name = NULL ; snprintf ( push_buf , sizeof ( push_buf ) , "push{%c}\t%s" , TARGET_64BIT ? 'q' : 'l' , xasm ) ; if ( sibcall_p ) { output_asm_insn ( push_buf , & call_op ) ; if ( thunk_name != NULL ) fprintf ( asm_out_file , "\tjmp\t%s\n" , thunk_name ) ; else output_indirect_thunk ( regno ) ; } else { char indirectlabel1 [ 32 ] ; char indirectlabel2 [ 32 ] ; ASM_GENERATE_INTERNAL_LABEL ( indirectlabel1 , INDIRECT_LABEL , indirectlabelno ++ ) ; ASM_GENERATE_INTERNAL_LABEL ( indirectlabel2 , INDIRECT_LABEL , indirectlabelno ++ ) ; fputs ( "\tjmp\t" , asm_out_file ) ; assemble_name_raw ( asm_out_file , indirectlabel2 ) ; fputc ( '\n' , asm_out_file ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , indirectlabel1 ) ; if ( MEM_P ( call_op ) ) { struct ix86_address parts ; rtx addr = XEXP ( call_op , 0 ) ; if ( ix86_decompose_address ( addr , & parts ) && parts . base == stack_pointer_rtx ) { if ( parts . index ) { addr = gen_rtx_MULT ( Pmode , parts . index , GEN_INT ( parts . scale ) ) ; addr = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , addr ) ; } else addr = stack_pointer_rtx ; rtx disp ; if ( parts . disp != NULL_RTX ) disp = plus_constant ( Pmode , parts . disp , UNITS_PER_WORD ) ; else disp = GEN_INT ( UNITS_PER_WORD ) ; addr = gen_rtx_PLUS ( Pmode , addr , disp ) ; call_op = gen_rtx_MEM ( GET_MODE ( call_op ) , addr ) ; } } output_asm_insn ( push_buf , & call_op ) ; if ( thunk_name != NULL ) fprintf ( asm_out_file , "\tjmp\t%s\n" , thunk_name ) ; else output_indirect_thunk ( regno ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , indirectlabel2 ) ; fputs ( "\tcall\t" , asm_out_file ) ; assemble_name_raw ( asm_out_file , indirectlabel1 ) ; fputc ( '\n' , asm_out_file ) ; } } </s>

Output indirect branch via a call and return thunk . CALL_OP is the branch target . XASM is the assembly template for CALL_OP . Branch is a tail call if SIBCALL_P is true . A normal call is converted to : jmp L2 L1 : push CALL_OP jmp __x86_indirect_thunk L2 : call L1 and a tail call is converted to : push CALL_OP jmp __x86_indirect_thunk


"Can only put epilog before 'retl' instruction!"


<s> static ds_t ia64_get_insn_spec_ds ( rtx_insn * insn ) { int code = get_insn_spec_code ( insn ) ; switch ( code ) { case UNSPEC_LDA : return BEGIN_DATA ; case UNSPEC_LDS : case UNSPEC_LDS_A : return BEGIN_CONTROL ; case UNSPEC_LDSA : return BEGIN_DATA | BEGIN_CONTROL ; default : return 0 ; } } </s>

If INSN is a speculative load , return a ds with the speculation types . Otherwise [ if INSN is a normal instruction ] return 0 .


<s> void WebAssemblyCFGStackify :: releaseMemory ( ) { ScopeTops . clear ( ) ; BeginToEnd . clear ( ) ; EndToBegin . clear ( ) ; TryToEHPad . clear ( ) ; EHPadToTry . clear ( ) ; } </s>

releaseMemory ( ) - This member can be implemented by a pass if it wants to be able to release its memory when it is no longer needed .


<s> bool mips_unsigned_immediate_p ( unsigned HOST_WIDE_INT x , int bits , int shift = 0 ) { return ( x & ( ( 1 << shift ) - 1 ) ) == 0 && x < ( ( unsigned ) 1 << ( shift + bits ) ) ; } </s>

Return true if X fits within an unsigned field of BITS bits that is shifted left SHIFT bits before being used .


<s> static void csky_function_arg_advance ( cumulative_args_t pcum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * pcum = get_cumulative_args ( pcum_v ) ; int * reg = & pcum -> reg ; machine_mode mode = arg . mode ; int param_size = csky_num_arg_regs ( mode , arg . type , pcum -> is_stdarg ) ; int param_regs_nums = CSKY_NPARM_REGS ; if ( FUNCTION_VARG_MODE_P ( mode ) && ! pcum -> is_stdarg ) { reg = & pcum -> freg ; param_regs_nums = CSKY_NPARM_FREGS ; } if ( * reg + param_size > param_regs_nums ) * reg = param_regs_nums ; else * reg += param_size ; } </s>


<s> bool ARMAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { const uint16_t Thumb1_16bitNopEncoding = 0x46c0 ; const uint16_t Thumb2_16bitNopEncoding = 0xbf00 ; const uint32_t ARMv4_NopEncoding = 0xe1a00000 ; const uint32_t ARMv6T2_NopEncoding = 0xe320f000 ; if ( isThumb ( ) ) { const uint16_t nopEncoding = hasNOP ( ) ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding ; uint64_t NumNops = Count / 2 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> Write16 ( nopEncoding ) ; if ( Count & 1 ) OW -> Write8 ( 0 ) ; return true ; } const uint32_t nopEncoding = hasNOP ( ) ? ARMv6T2_NopEncoding : ARMv4_NopEncoding ; uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> Write32 ( nopEncoding ) ; switch ( Count % 4 ) { default : break ; case 1 : OW -> Write8 ( 0 ) ; break ; case 2 : OW -> Write16 ( 0 ) ; break ; case 3 : OW -> Write16 ( 0 ) ; OW -> Write8 ( 0xa0 ) ; break ; } return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> static rtx extract_sfunc_addr ( rtx insn ) { rtx pattern = PATTERN ( insn ) ; const int len = XVECLEN ( pattern , 0 ) ; for ( int i = 0 ; i < len ; i ++ ) { rtx part = XVECEXP ( pattern , 0 , i ) ; if ( GET_CODE ( part ) == USE && GET_MODE ( XEXP ( part , 0 ) ) == Pmode && GENERAL_REGISTER_P ( true_regnum ( XEXP ( part , 0 ) ) ) ) return XEXP ( part , 0 ) ; } gcc_assert ( GET_CODE ( XVECEXP ( pattern , 0 , 0 ) ) == UNSPEC_VOLATILE ) ; return XVECEXP ( XVECEXP ( pattern , 0 , 0 ) , 0 , 1 ) ; } </s>

INSN is an sfunc ; return the rtx that describes the address used .


<s> void rs6000_expand_vector_extract ( rtx target , rtx vec , rtx elt ) { machine_mode mode = GET_MODE ( vec ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx mem ; if ( VECTOR_MEM_VSX_P ( mode ) && CONST_INT_P ( elt ) ) { switch ( mode ) { default : break ; case E_V1TImode : gcc_assert ( INTVAL ( elt ) == 0 && inner_mode == TImode ) ; emit_move_insn ( target , gen_lowpart ( TImode , vec ) ) ; break ; case E_V2DFmode : emit_insn ( gen_vsx_extract_v2df ( target , vec , elt ) ) ; return ; case E_V2DImode : emit_insn ( gen_vsx_extract_v2di ( target , vec , elt ) ) ; return ; case E_V4SFmode : emit_insn ( gen_vsx_extract_v4sf ( target , vec , elt ) ) ; return ; case E_V16QImode : if ( TARGET_DIRECT_MOVE_64BIT ) { emit_insn ( gen_vsx_extract_v16qi ( target , vec , elt ) ) ; return ; } else break ; case E_V8HImode : if ( TARGET_DIRECT_MOVE_64BIT ) { emit_insn ( gen_vsx_extract_v8hi ( target , vec , elt ) ) ; return ; } else break ; case E_V4SImode : if ( TARGET_DIRECT_MOVE_64BIT ) { emit_insn ( gen_vsx_extract_v4si ( target , vec , elt ) ) ; return ; } break ; } } else if ( VECTOR_MEM_VSX_P ( mode ) && ! CONST_INT_P ( elt ) && TARGET_DIRECT_MOVE_64BIT ) { if ( GET_MODE ( elt ) != DImode ) { rtx tmp = gen_reg_rtx ( DImode ) ; convert_move ( tmp , elt , 0 ) ; elt = tmp ; } else if ( ! REG_P ( elt ) ) elt = force_reg ( DImode , elt ) ; switch ( mode ) { case E_V2DFmode : emit_insn ( gen_vsx_extract_v2df_var ( target , vec , elt ) ) ; return ; case E_V2DImode : emit_insn ( gen_vsx_extract_v2di_var ( target , vec , elt ) ) ; return ; case E_V4SFmode : emit_insn ( gen_vsx_extract_v4sf_var ( target , vec , elt ) ) ; return ; case E_V4SImode : emit_insn ( gen_vsx_extract_v4si_var ( target , vec , elt ) ) ; return ; case E_V8HImode : emit_insn ( gen_vsx_extract_v8hi_var ( target , vec , elt ) ) ; return ; case E_V16QImode : emit_insn ( gen_vsx_extract_v16qi_var ( target , vec , elt ) ) ; return ; default : gcc_unreachable ( ) ; } } gcc_assert ( CONST_INT_P ( elt ) ) ; mem = assign_stack_temp ( mode , GET_MODE_SIZE ( mode ) ) ; emit_move_insn ( mem , vec ) ; mem = adjust_address_nv ( mem , inner_mode , INTVAL ( elt ) * GET_MODE_SIZE ( inner_mode ) ) ; emit_move_insn ( target , adjust_address_nv ( mem , inner_mode , 0 ) ) ; } </s>

Extract field ELT from VEC into TARGET .


"AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "


<s> const PPCSubtarget * PPCTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . hasFnAttribute ( "use-soft-float" ) && F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < PPCSubtarget > ( TargetTriple , CPU , computeFSAdditions ( FS , getOptLevel ( ) , getTargetTriple ( ) ) , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

PowerPC PPC PPC "target-cpu" "target-features" "use-soft-float" "use-soft-float" "true" "+soft-float" ",+soft-float" PPC


<s> static void init_sched_state ( c6x_sched_context_t sc ) { sc -> last_scheduled_insn = NULL ; sc -> last_scheduled_iter0 = NULL ; sc -> issued_this_cycle = 0 ; memset ( sc -> jump_cycles , 0 , sizeof sc -> jump_cycles ) ; memset ( sc -> jump_cond , 0 , sizeof sc -> jump_cond ) ; sc -> jump_cycle_index = 0 ; sc -> delays_finished_at = 0 ; sc -> curr_sched_clock = 0 ; sc -> prev_cycle_state_ctx = xmalloc ( dfa_state_size ) ; memset ( sc -> reg_n_accesses , 0 , sizeof sc -> reg_n_accesses ) ; memset ( sc -> reg_n_xaccesses , 0 , sizeof sc -> reg_n_xaccesses ) ; memset ( sc -> reg_set_in_cycle , 0 , sizeof sc -> reg_set_in_cycle ) ; state_reset ( sc -> prev_cycle_state_ctx ) ; } </s>

Initialize SC . Used by c6x_init_sched_context and c6x_sched_init .


<s> static bool ix86_expand_sse_fp_minmax ( rtx dest , enum rtx_code code , rtx cmp_op0 , rtx cmp_op1 , rtx if_true , rtx if_false ) { machine_mode mode ; bool is_min ; rtx tmp ; if ( code == LT ) ; else if ( code == UNGE ) std :: swap ( if_true , if_false ) ; else return false ; if ( rtx_equal_p ( cmp_op0 , if_true ) && rtx_equal_p ( cmp_op1 , if_false ) ) is_min = true ; else if ( rtx_equal_p ( cmp_op1 , if_true ) && rtx_equal_p ( cmp_op0 , if_false ) ) is_min = false ; else return false ; mode = GET_MODE ( dest ) ; if ( ! flag_finite_math_only || ! flag_unsafe_math_optimizations ) { int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX ; rtvec v ; if_true = force_reg ( mode , if_true ) ; v = gen_rtvec ( 2 , if_true , if_false ) ; tmp = gen_rtx_UNSPEC ( mode , v , u ) ; } else { code = is_min ? SMIN : SMAX ; tmp = gen_rtx_fmt_ee ( code , mode , if_true , if_false ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , dest , tmp ) ) ; return true ; } </s>

Detect conditional moves that exactly match min/max operational semantics . Note that this is IEEE safe , as long as we do n't interchange the operands . Returns FALSE if this conditional move does n't match a MIN/MAX , and TRUE if the operation is successful and instructions are emitted .


<s>
void
TPCSchedStrategy
::
releaseBottomNode
(
SUnit
*
SU
)
{
MachineInstr
*
MI
=
SU
->
getInstr
(
)
;
(
void
)
MI
;
if
(
SU
->
isScheduled
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"*** release Bot - already scheduled: "
<<
*
MI
)
;
return
;
}
assert
(
SU
->
getInstr
(
)
&&
"Scheduled SUnit must have instr"
)
;
for
(
SUnit
::
succ_iterator
I
=
SU
->
Succs
.
begin
(
)
,
E
=
SU
->
Succs
.
end
(
)
;
I
!=
E
;
++
I
)
{
unsigned
SuccReadyCycle
=
I
->
getSUnit
(
)
->
BotReadyCycle
;
unsigned
MinLatency
=
I
->
getLatency
(
)
;
Bot
.
MaxMinLatency
=
std
::
max
(
MinLatency
,
Bot
.
MaxMinLatency
)
;
if
(
SU
->
BotReadyCycle
<
SuccReadyCycle
+
MinLatency
)
SU
->
BotReadyCycle
=
SuccReadyCycle
+
MinLatency
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"*** released Bot (ready = "
<<
SU
->
BotReadyCycle
<<
"): "
<<
*
MI
)
;
Bot
.
releaseNode
(
SU
,
SU
->
BotReadyCycle
,
isPostRA
)
;
}
</s>

Currently only scheduling top-down , so this method is empty .

TPC
TPC
"*** release Bot - already scheduled: "
"Scheduled SUnit must have instr"
"*** released Bot (ready = "
"): "


<s> bool TMS320C64XFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { const MachineFunction * MF ; unsigned int i , reg ; bool is_kill ; MF = MBB . getParent ( ) ; const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; for ( i = 0 ; i < CSI . size ( ) ; ++ i ) { is_kill = true ; reg = CSI [ i ] . getReg ( ) ; MachineRegisterInfo :: livein_iterator li = MRI . livein_begin ( ) ; for ( ; li != MRI . livein_end ( ) ; li ++ ) { if ( li -> first == reg ) { is_kill = false ; break ; } } MBB . addLiveIn ( reg ) ; const TargetInstrInfo & TII = * ( MF -> getTarget ( ) . getInstrInfo ( ) ) ; TII . storeRegToStackSlot ( MBB , MBBI , reg , is_kill , CSI [ i ] . getFrameIdx ( ) , 0 , 0 ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> void R600TargetLowering :: getStackAddress ( unsigned StackWidth , unsigned ElemIdx , unsigned & Channel , unsigned & PtrIncr ) const { switch ( StackWidth ) { default : case 1 : Channel = 0 ; if ( ElemIdx > 0 ) { PtrIncr = 1 ; } else { PtrIncr = 0 ; } break ; case 2 : Channel = ElemIdx % 2 ; if ( ElemIdx == 2 ) { PtrIncr = 1 ; } else { PtrIncr = 0 ; } break ; case 4 : Channel = ElemIdx ; PtrIncr = 0 ; break ; } } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> static int cris_address_cost ( rtx x ) { if ( BASE_OR_AUTOINCR_P ( x ) ) return 0 ; if ( GET_CODE ( x ) == MEM ) return ( 2 + 4 ) / 2 ; if ( CONSTANT_P ( x ) ) return ( 2 + 4 ) / 2 ; if ( GET_CODE ( x ) == PLUS ) { rtx tem1 = XEXP ( x , 0 ) ; rtx tem2 = XEXP ( x , 1 ) ; if ( ( GET_CODE ( tem1 ) == MULT && BIAP_INDEX_P ( tem1 ) ) || REG_P ( tem1 ) ) return 2 / 2 ; if ( GET_CODE ( tem2 ) == CONST_INT && INTVAL ( tem2 ) < 128 && INTVAL ( tem2 ) >= - 128 ) return 2 / 2 ; if ( GET_CODE ( tem2 ) == CONST_INT && CONST_OK_FOR_LETTER_P ( INTVAL ( tem2 ) , 'L' ) ) return ( 2 + 2 ) / 2 ; if ( CONSTANT_P ( tem2 ) ) return ( 2 + 2 + 2 ) / 2 ; return ( 2 + 2 + 2 ) / 2 ; } return 10 ; } </s>


<s> MachineInstrBuilder buildLoad ( const DstOp & Res , Register Addr , uint64_t Size , MachinePointerInfo & MPO ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; unsigned Alignment = inferAlignmentFromPtrInfo ( MF , MPO ) ; auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , Size , Alignment ) ; return MIRBuilder . buildLoad ( Res , Addr , * MMO ) ; } </s>

Build and insert a G_LOAD instruction , while constructing the MachineMemOperand .


<s> unsigned getPointerSize ( ) const { return 4 ; } </s>

Layout pointer size in bytes , rounded up to a whole number of bytes .


<s> static inline int avr_lookup_function_attribute1 ( const_tree func , const char * name ) { if ( FUNCTION_DECL == TREE_CODE ( func ) ) { if ( NULL_TREE != lookup_attribute ( name , DECL_ATTRIBUTES ( func ) ) ) { return true ; } func = TREE_TYPE ( func ) ; } gcc_assert ( TREE_CODE ( func ) == FUNCTION_TYPE || TREE_CODE ( func ) == METHOD_TYPE ) ; return NULL_TREE != lookup_attribute ( name , TYPE_ATTRIBUTES ( func ) ) ; } </s>

A helper for the subsequent function attribute used to dig for attribute 'name ' in a FUNCTION_DECL or FUNCTION_TYPE


"Warning: Illegal instruction detected: "

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> std :: pair < const TargetRegisterClass * , uint8_t > HexagonTargetLowering :: findRepresentativeClass ( const TargetRegisterInfo * TRI , MVT VT ) const { if ( Subtarget . isHVXVectorType ( VT , true ) ) { unsigned BitWidth = VT . getSizeInBits ( ) ; unsigned VecWidth = Subtarget . getVectorLength ( ) * 8 ; if ( VT . getVectorElementType ( ) == MVT :: i1 ) return std :: make_pair ( & Hexagon :: HvxQRRegClass , 1 ) ; if ( BitWidth == VecWidth ) return std :: make_pair ( & Hexagon :: HvxVRRegClass , 1 ) ; assert ( BitWidth == 2 * VecWidth ) ; return std :: make_pair ( & Hexagon :: HvxWRRegClass , 1 ) ; } return TargetLowering :: findRepresentativeClass ( TRI , VT ) ; } </s>

Return the largest legal super-reg register class of the register class for the specified type and its associated `` cost '' .


"_reflect function should not have a body"

"_reflect's return type should be integer"

"Only a call instruction can use _reflect"

"Only one operand expect for _reflect function"

"Format of _reflect function not recognized"

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s>
unsigned
getExplicitKernelArgOffset
(
const
Function
&
F
)
const
{
switch
(
TargetTriple
.
getOS
(
)
)
{
case
Triple
::
AMDHSA
:
case
Triple
::
AMDPAL
:
case
Triple
::
Mesa3D
:
return
0
;
case
Triple
::
UnknownOS
:
default
:
return
36
;
}
llvm_unreachable
(
"invalid triple OS"
)
;
}
</s>

Returns the offset in bytes from the start of the input buffer of the first explicit kernel argument .


"frame pointer should not have been eliminated"

"SecondSPAdjustAmount should be greater than zero"


<s> std :: pair < const TargetRegisterClass * , uint8_t > X86TargetLowering :: findRepresentativeClass ( MVT VT ) const { const TargetRegisterClass * RRC = nullptr ; uint8_t Cost = 1 ; switch ( VT . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( VT ) ; case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : case MVT :: i64 : RRC = Subtarget -> is64Bit ( ) ? & X86 :: GR64RegClass : & X86 :: GR32RegClass ; break ; case MVT :: x86mmx : RRC = & X86 :: VR64RegClass ; break ; case MVT :: f32 : case MVT :: f64 : case MVT :: v16i8 : case MVT :: v8i16 : case MVT :: v4i32 : case MVT :: v2i64 : case MVT :: v4f32 : case MVT :: v2f64 : case MVT :: v32i8 : case MVT :: v8i32 : case MVT :: v4i64 : case MVT :: v8f32 : case MVT :: v4f64 : RRC = & X86 :: VR128RegClass ; break ; } return std :: make_pair ( RRC , Cost ) ; } </s>


<s>
unsigned
R600InstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
if
(
I
==
MBB
.
begin
(
)
)
{
return
0
;
}
I
;
switch
(
I
->
getOpcode
(
)
)
{
default
:
return
0
;
case
AMDGPU
::
JUMP_COND
:
{
MachineInstr
*
predSet
=
findFirstPredicateSetterFrom
(
MBB
,
I
)
;
clearFlag
(
*
predSet
,
0
,
MO_FLAG_PUSH
)
;
I
->
eraseFromParent
(
)
;
MachineBasicBlock
::
iterator
CfAlu
=
FindLastAluClause
(
MBB
)
;
if
(
CfAlu
==
MBB
.
end
(
)
)
break
;
assert
(
CfAlu
->
getOpcode
(
)
==
AMDGPU
::
CF_ALU_PUSH_BEFORE
)
;
CfAlu
->
setDesc
(
get
(
AMDGPU
::
CF_ALU
)
)
;
break
;
}
case
AMDGPU
::
JUMP
:
I
->
eraseFromParent
(
)
;
break
;
}
I
=
MBB
.
end
(
)
;
if
(
I
==
MBB
.
begin
(
)
)
{
return
1
;
}
I
;
switch
(
I
->
getOpcode
(
)
)
{
default
:
return
1
;
case
AMDGPU
::
JUMP_COND
:
{
MachineInstr
*
predSet
=
findFirstPredicateSetterFrom
(
MBB
,
I
)
;
clearFlag
(
*
predSet
,
0
,
MO_FLAG_PUSH
)
;
I
->
eraseFromParent
(
)
;
MachineBasicBlock
::
iterator
CfAlu
=
FindLastAluClause
(
MBB
)
;
if
(
CfAlu
==
MBB
.
end
(
)
)
break
;
assert
(
CfAlu
->
getOpcode
(
)
==
AMDGPU
::
CF_ALU_PUSH_BEFORE
)
;
CfAlu
->
setDesc
(
get
(
AMDGPU
::
CF_ALU
)
)
;
break
;
}
case
AMDGPU
::
JUMP
:
I
->
eraseFromParent
(
)
;
break
;
}
return
2
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s>
const
char
*
AMDGPUAsmPrinter
::
getPassName
(
)
const
{
return
"AMDGPU Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static bool ix86_dep_by_shift_count_body ( const_rtx set_body , const_rtx use_body ) { rtx set_dest ; rtx shift_rtx ; int i ; switch ( GET_CODE ( set_body ) ) { case SET : set_dest = SET_DEST ( set_body ) ; if ( ! set_dest || ! REG_P ( set_dest ) ) return false ; break ; case PARALLEL : for ( i = XVECLEN ( set_body , 0 ) - 1 ; i >= 0 ; i -- ) if ( ix86_dep_by_shift_count_body ( XVECEXP ( set_body , 0 , i ) , use_body ) ) return true ; default : return false ; } switch ( GET_CODE ( use_body ) ) { case SET : shift_rtx = XEXP ( use_body , 1 ) ; break ; case PARALLEL : for ( i = XVECLEN ( use_body , 0 ) - 1 ; i >= 0 ; i -- ) if ( ix86_dep_by_shift_count_body ( set_body , XVECEXP ( use_body , 0 , i ) ) ) return true ; default : return false ; } if ( shift_rtx && ( GET_CODE ( shift_rtx ) == ASHIFT || GET_CODE ( shift_rtx ) == LSHIFTRT || GET_CODE ( shift_rtx ) == ASHIFTRT || GET_CODE ( shift_rtx ) == ROTATE || GET_CODE ( shift_rtx ) == ROTATERT ) ) { rtx shift_count = XEXP ( shift_rtx , 1 ) ; if ( REG_P ( shift_count ) ) { if ( reload_completed && true_regnum ( set_dest ) == true_regnum ( shift_count ) ) return true ; else if ( REGNO ( set_dest ) == REGNO ( shift_count ) ) return true ; } } return false ; } </s>

Return true if destination reg of SET_BODY is shift count of USE_BODY .


<s>
StringRef
getPassName
(
)
const
override
{
return
"GCN DPP Combine"
;
}
</s>


<s> unsigned reset ( unsigned NewTop ) { List . resize ( NewTop + 1 ) ; return NewTop ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s>
DecodeStatus
AArch64Disassembler
::
getInstruction
(
MCInst
&
MI
,
uint64_t
&
Size
,
ArrayRef
<
uint8_t
>
Bytes
,
uint64_t
Address
,
raw_ostream
&
CS
)
const
{
CommentStream
=
&
CS
;
Size
=
0
;
if
(
Bytes
.
size
(
)
<
4
)
return
Fail
;
Size
=
4
;
uint32_t
Insn
=
(
Bytes
[
3
]
<<
24
)
|
(
Bytes
[
2
]
<<
16
)
|
(
Bytes
[
1
]
<<
8
)
|
(
Bytes
[
0
]
<<
0
)
;
const
uint8_t
*
Tables
[
]
=
{
DecoderTable32
,
DecoderTableFallback32
}
;
for
(
auto
Table
:
Tables
)
{
DecodeStatus
Result
=
decodeInstruction
(
Table
,
MI
,
Insn
,
Address
,
this
,
STI
)
;
const
MCInstrDesc
&
Desc
=
MCII
->
get
(
MI
.
getOpcode
(
)
)
;
for
(
unsigned
i
=
0
;
i
<
Desc
.
getNumOperands
(
)
;
i
++
)
{
if
(
Desc
.
OpInfo
[
i
]
.
OperandType
==
MCOI
::
OPERAND_REGISTER
)
{
switch
(
Desc
.
OpInfo
[
i
]
.
RegClass
)
{
default
:
break
;
case
AArch64
::
MPRRegClassID
:
MI
.
insert
(
MI
.
begin
(
)
+
i
,
MCOperand
::
createReg
(
AArch64
::
ZA
)
)
;
break
;
case
AArch64
::
MPR8RegClassID
:
MI
.
insert
(
MI
.
begin
(
)
+
i
,
MCOperand
::
createReg
(
AArch64
::
ZAB0
)
)
;
break
;
}
}
else
if
(
Desc
.
OpInfo
[
i
]
.
OperandType
==
AArch64
::
OPERAND_IMPLICIT_IMM_0
)
{
MI
.
insert
(
MI
.
begin
(
)
+
i
,
MCOperand
::
createImm
(
0
)
)
;
}
}
if
(
MI
.
getOpcode
(
)
==
AArch64
::
LDR_ZA
||
MI
.
getOpcode
(
)
==
AArch64
::
STR_ZA
)
{
const
MCOperand
&
Imm4Op
=
MI
.
getOperand
(
2
)
;
assert
(
Imm4Op
.
isImm
(
)
&&
"Unexpected operand type!"
)
;
MI
.
addOperand
(
Imm4Op
)
;
}
if
(
Result
!=
MCDisassembler
::
Fail
)
return
Result
;
}
return
MCDisassembler
::
Fail
;
}
</s>

Returns the disassembly of a single instruction .


"non-standard ABI extension with no compatibility guarantee"

Return a nonzero value to say to return the function value in memory , just as large structures are always returned . TYPE will be the data type of the value , and FNTYPE will be the type of the function doing the returning , or @ code { NULL } for libcalls . The AIX ABI for the RS/6000 specifies that all structures are returned in memory . The Darwin ABI does the same . The SVR4 ABI specifies that structures < = 8 bytes are returned in r3/r4 , but a draft put them in memory , and GCC used to implement the draft instead of the final standard . Therefore , aix_struct_return controls this instead of DEFAULT_ABI ; V.4 targets needing backward compatibility can change DRAFT_V4_STRUCT_RET to override the default , and -m switches get the final word . See rs6000_override_options for more details . The PPC32 SVR4 ABI uses IEEE double extended for long double , if 128-bit long double support is enabled . These values are returned in memory . int_size_in_bytes returns -1 for variable size objects , which go in memory always . The cast to unsigned makes -1 > 8 .


<s>
void
M68kInstrInfo
::
AddSExt
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
Reg
,
MVT
From
,
MVT
To
)
const
{
if
(
From
==
MVT
::
i8
)
{
unsigned
R
=
Reg
;
if
(
To
==
MVT
::
i32
)
{
R
=
RI
.
getSubReg
(
Reg
,
M68k
::
MxSubRegIndex16Lo
)
;
assert
(
R
&&
"No viable SUB register available"
)
;
}
BuildMI
(
MBB
,
I
,
DL
,
get
(
M68k
::
EXT16
)
,
R
)
.
addReg
(
R
)
;
}
if
(
To
==
MVT
::
i32
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
M68k
::
EXT32
)
,
Reg
)
.
addReg
(
Reg
)
;
}
</s>


<s>
bool
AArch64DAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
char
ConstraintCode
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
assert
(
ConstraintCode
==
'm'
&&
"unexpected asm memory constraint"
)
;
OutOps
.
push_back
(
Op
)
;
return
false
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> unsigned HexagonInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case Hexagon :: L2_loadrb_io : case Hexagon :: L2_loadrub_io : case Hexagon :: L2_loadrh_io : case Hexagon :: L2_loadruh_io : case Hexagon :: L2_loadri_io : case Hexagon :: L2_loadrd_io : case Hexagon :: V6_vL32b_ai : case Hexagon :: V6_vL32b_ai_128B : case Hexagon :: V6_vL32Ub_ai : case Hexagon :: V6_vL32Ub_ai_128B : case Hexagon :: LDriw_pred : case Hexagon :: LDriw_mod : case Hexagon :: PS_vloadrq_ai : case Hexagon :: PS_vloadrw_ai : case Hexagon :: PS_vloadrq_ai_128B : case Hexagon :: PS_vloadrw_ai_128B : { const MachineOperand OpFI = MI . getOperand ( 1 ) ; if ( ! OpFI . isFI ( ) ) return 0 ; const MachineOperand OpOff = MI . getOperand ( 2 ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != 0 ) return 0 ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } case Hexagon :: L2_ploadrbt_io : case Hexagon :: L2_ploadrbf_io : case Hexagon :: L2_ploadrubt_io : case Hexagon :: L2_ploadrubf_io : case Hexagon :: L2_ploadrht_io : case Hexagon :: L2_ploadrhf_io : case Hexagon :: L2_ploadruht_io : case Hexagon :: L2_ploadruhf_io : case Hexagon :: L2_ploadrit_io : case Hexagon :: L2_ploadrif_io : case Hexagon :: L2_ploadrdt_io : case Hexagon :: L2_ploadrdf_io : { const MachineOperand OpFI = MI . getOperand ( 2 ) ; if ( ! OpFI . isFI ( ) ) return 0 ; const MachineOperand OpOff = MI . getOperand ( 3 ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != 0 ) return 0 ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> static void expand_block_set_1 ( rtx dst_reg , rtx value_rtx , rtx bytes_rtx ) { const rtx sym = gen_rtx_SYMBOL_REF ( Pmode , "__byt_memset" ) ; value_rtx = convert_to_mode ( Pmode , value_rtx , 1 ) ; emit_library_call ( sym , LCT_NORMAL , VOIDmode , 3 , dst_reg , Pmode , value_rtx , Pmode , convert_to_mode ( TYPE_MODE ( sizetype ) , bytes_rtx , TYPE_UNSIGNED ( sizetype ) ) , TYPE_MODE ( sizetype ) ) ; } </s>

Generate a call to a library function to set BYTES_RTX bytes at address DST_REG to VALUE_RTX in 1-byte chunks .


"LOAD_STACK_GUARD currently supported only for MachO."

This function is called for all pseudo instructions that remain after register allocation .


<s> int neon_immediate_valid_for_logic ( rtx op , machine_mode mode , int inverse , rtx * modconst , int * elementwidth ) { rtx tmpconst ; int tmpwidth ; int retval = neon_valid_immediate ( op , mode , inverse , & tmpconst , & tmpwidth ) ; if ( retval < 0 || retval > 5 ) return 0 ; if ( modconst ) * modconst = tmpconst ; if ( elementwidth ) * elementwidth = tmpwidth ; return 1 ; } </s>

Return TRUE if rtx X is legal for use in a VORR or VBIC instruction . If the immediate is valid , write a constant suitable for using as an operand to VORR/VBIC/VAND/VORN to * MODCONST and the corresponding element width to * ELEMENTWIDTH . See neon_valid_immediate for description of INVERSE .


<s> static rtx epiphany_function_arg ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS cum = * get_cumulative_args ( cum_v ) ; if ( PASS_IN_REG_P ( cum , arg . mode , arg . type ) ) return gen_rtx_REG ( arg . mode , ROUND_ADVANCE_CUM ( cum , arg . mode , arg . type ) ) ; return 0 ; } </s>

On the EPIPHANY the first MAX_EPIPHANY_PARM_REGS args are normally in registers and the rest are pushed .


<s>
bool
AMDGPUAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Name
=
parseMnemonicSuffix
(
Name
)
;
Operands
.
push_back
(
AMDGPUOperand
::
CreateToken
(
this
,
Name
,
NameLoc
)
)
;
bool
IsMIMG
=
Name
.
startswith
(
"image_"
)
;
while
(
!
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
{
OperandMode
Mode
=
OperandMode_Default
;
if
(
IsMIMG
&&
isGFX10
(
)
&&
Operands
.
size
(
)
==
2
)
Mode
=
OperandMode_NSA
;
OperandMatchResultTy
Res
=
parseOperand
(
Operands
,
Name
,
Mode
)
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
Parser
.
Lex
(
)
;
switch
(
Res
)
{
case
MatchOperand_Success
:
break
;
case
MatchOperand_ParseFail
:
Error
(
getLexer
(
)
.
getLoc
(
)
,
"failed parsing operand."
)
;
while
(
!
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
{
Parser
.
Lex
(
)
;
}
return
true
;
case
MatchOperand_NoMatch
:
Error
(
getLexer
(
)
.
getLoc
(
)
,
"not a valid operand."
)
;
while
(
!
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
{
Parser
.
Lex
(
)
;
}
return
true
;
}
}
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

AMDGPU
AMDGPU
AMDGPU
"image_"
2
"failed parsing operand."
"not a valid operand."


<s> TargetFrameLowering :: DwarfFrameBase WebAssemblyFrameLowering :: getDwarfFrameBase ( const MachineFunction & MF ) const { DwarfFrameBase Loc ; Loc . Kind = DwarfFrameBase :: WasmFrameBase ; const WebAssemblyFunctionInfo & MFI = * MF . getInfo < WebAssemblyFunctionInfo > ( ) ; if ( needsSP ( MF ) && MFI . isFrameBaseVirtual ( ) ) { unsigned LocalNum = MFI . getFrameBaseLocal ( ) ; Loc . Location . WasmLoc = { WebAssembly :: TI_LOCAL , LocalNum } ; } else { Loc . Location . WasmLoc = { WebAssembly :: TI_GLOBAL_RELOC , 0 } ; } return Loc ; } </s>

Return the frame base information to be encoded in the DWARF subprogram debug info .


<s> bool isReg ( ) const override { return Kind == KindTy :: Register ; } </s>


<s>
unsigned
HexagonAsmParser
::
validateTargetOperandClass
(
MCParsedAsmOperand
&
AsmOp
,
unsigned
Kind
)
{
HexagonOperand
*
Op
=
static_cast
<
HexagonOperand
*
>
(
&
AsmOp
)
;
switch
(
Kind
)
{
case
MCK_0
:
{
int64_t
Value
;
return
Op
->
isImm
(
)
&&
Op
->
Imm
.
Val
->
evaluateAsAbsolute
(
Value
)
&&
Value
==
0
Match_Success
:
Match_InvalidOperand
;
}
case
MCK_1
:
{
int64_t
Value
;
return
Op
->
isImm
(
)
&&
Op
->
Imm
.
Val
->
evaluateAsAbsolute
(
Value
)
&&
Value
==
1
Match_Success
:
Match_InvalidOperand
;
}
}
if
(
Op
->
Kind
==
HexagonOperand
::
Token
&&
Kind
!=
InvalidMatchClass
)
{
StringRef
myStringRef
=
StringRef
(
Op
->
Tok
.
Data
,
Op
->
Tok
.
Length
)
;
if
(
matchTokenString
(
myStringRef
.
lower
(
)
)
==
(
MatchClassKind
)
Kind
)
return
Match_Success
;
if
(
matchTokenString
(
myStringRef
.
upper
(
)
)
==
(
MatchClassKind
)
Kind
)
return
Match_Success
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Unmatched Operand:"
)
;
LLVM_DEBUG
(
Op
->
dump
(
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"\n"
)
;
return
Match_InvalidOperand
;
}
</s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .

Hexagon
Hexagon
Hexagon
Hexagon
0
1
Hexagon
"Unmatched Operand:"
"\n"


<s> const TargetRegisterClass * M88kRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & M88k :: GPRRCRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> void TOYInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI , O ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> BitVector RISCVRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , RISCV :: X0 ) ; markSuperRegs ( Reserved , RISCV :: X1 ) ; markSuperRegs ( Reserved , RISCV :: X2 ) ; markSuperRegs ( Reserved , RISCV :: X3 ) ; markSuperRegs ( Reserved , RISCV :: X4 ) ; markSuperRegs ( Reserved , RISCV :: X8 ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool SystemZInstrInfo :: isPredicable ( MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( STI . hasLoadStoreOnCond ( ) && getConditionalMove ( Opcode ) ) return true ; if ( Opcode == SystemZ :: Return || Opcode == SystemZ :: CallJG || Opcode == SystemZ :: CallBR ) return true ; return false ; } </s>

Return true if the specified instruction can be predicated .

SystemZ SystemZ SystemZ::Return SystemZ::CallJG SystemZ::CallBR


<s> bool AArch64PromoteConstant :: runOnFunction ( Function & F ) { bool LocalChange = false ; SmallPtrSet < Constant * , 8 > AlreadyChecked ; for ( Instruction & I : inst_range ( & F ) ) { for ( Value * Op : I . operand_values ( ) ) { Constant * Cst = dyn_cast < Constant > ( Op ) ; if ( Cst && ! isa < GlobalValue > ( Cst ) && ! isa < ConstantExpr > ( Cst ) && AlreadyChecked . insert ( Cst ) . second ) LocalChange |= promoteConstant ( Cst ) ; } } return LocalChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


Schedule - This is called back from ScheduleDAGInstrs : :Run ( ) when it 's time to do some work .


"Instr doesn't have FrameIndex operand!"

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s>
const
char
*
pa_output_millicode_call
(
rtx_insn
*
insn
,
rtx
call_dest
)
{
int
attr_length
=
get_attr_length
(
insn
)
;
int
seq_length
=
dbr_sequence_length
(
)
;
rtx
xoperands
[
4
]
;
xoperands
[
0
]
=
call_dest
;
if
(
!
TARGET_LONG_CALLS
&&
(
attr_length
==
8
||
(
attr_length
==
28
&&
get_attr_type
(
insn
)
==
TYPE_SH_FUNC_ADRS
)
)
)
{
xoperands
[
1
]
=
gen_rtx_REG
(
Pmode
,
TARGET_64BIT
2
:
31
)
;
output_asm_insn
(
"{bl|b,l} %0,%1"
,
xoperands
)
;
}
else
{
if
(
TARGET_64BIT
)
{
xoperands
[
1
]
=
gen_rtx_REG
(
Pmode
,
1
)
;
xoperands
[
2
]
=
xoperands
[
1
]
;
pa_output_pic_pcrel_sequence
(
xoperands
)
;
output_asm_insn
(
"bve,l (%%r1),%%r2"
,
xoperands
)
;
}
else
if
(
TARGET_PORTABLE_RUNTIME
)
{
output_asm_insn
(
"ldil L'%0,%%r1"
,
xoperands
)
;
output_asm_insn
(
"ldo R'%0(%%r1),%%r1"
,
xoperands
)
;
output_asm_insn
(
"{bl|b,l} .+8,%%r31"
,
xoperands
)
;
output_asm_insn
(
"addi 8,%%r31,%%r31"
,
xoperands
)
;
output_asm_insn
(
"bv %%r0(%%r1)"
,
xoperands
)
;
}
else
if
(
!
flag_pic
)
{
output_asm_insn
(
"ldil L'%0,%%r1"
,
xoperands
)
;
if
(
TARGET_PA_20
)
output_asm_insn
(
"be,l R'%0(%%sr4,%%r1),%%sr0,%%r31"
,
xoperands
)
;
else
output_asm_insn
(
"ble R'%0(%%sr4,%%r1)"
,
xoperands
)
;
}
else
{
xoperands
[
1
]
=
gen_rtx_REG
(
Pmode
,
31
)
;
xoperands
[
2
]
=
gen_rtx_REG
(
Pmode
,
1
)
;
pa_output_pic_pcrel_sequence
(
xoperands
)
;
output_asm_insn
(
"ldo {16|24}(%%r31),%%r31"
,
xoperands
)
;
output_asm_insn
(
"bv %%r0(%%r1)"
,
xoperands
)
;
}
}
if
(
seq_length
==
0
)
output_asm_insn
(
"nop"
,
xoperands
)
;
return
""
;
}
</s>

INSN is a function call . CALL_DEST is the routine we are calling .


<s> bool M68kCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const auto & DL = F . getParent ( ) -> getDataLayout ( ) ; auto & TLI = * getTLI < M68kTargetLowering > ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned I = 0 ; for ( const auto & Arg : F . args ( ) ) { ArgInfo OrigArg { VRegs [ I ] , Arg . getType ( ) , I } ; setArgFlags ( OrigArg , I + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , F . getCallingConv ( ) ) ; ++ I ; } CCAssignFn * AssignFn = TLI . getCCAssignFn ( F . getCallingConv ( ) , false , F . isVarArg ( ) ) ; IncomingValueAssigner ArgAssigner ( AssignFn ) ; FormalArgHandler ArgHandler ( MIRBuilder , MRI ) ; return determineAndHandleAssignments ( ArgHandler , ArgAssigner , SplitArgs , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> const unsigned * MSP430RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const Function * F = MF -> getFunction ( ) ; static const unsigned CalleeSavedRegs [ ] = { MSP430 :: FPW , MSP430 :: R5W , MSP430 :: R6W , MSP430 :: R7W , MSP430 :: R8W , MSP430 :: R9W , MSP430 :: R10W , MSP430 :: R11W , 0 } ; static const unsigned CalleeSavedRegsFP [ ] = { MSP430 :: R5W , MSP430 :: R6W , MSP430 :: R7W , MSP430 :: R8W , MSP430 :: R9W , MSP430 :: R10W , MSP430 :: R11W , 0 } ; static const unsigned CalleeSavedRegsIntr [ ] = { MSP430 :: FPW , MSP430 :: R5W , MSP430 :: R6W , MSP430 :: R7W , MSP430 :: R8W , MSP430 :: R9W , MSP430 :: R10W , MSP430 :: R11W , MSP430 :: R12W , MSP430 :: R13W , MSP430 :: R14W , MSP430 :: R15W , 0 } ; static const unsigned CalleeSavedRegsIntrFP [ ] = { MSP430 :: R5W , MSP430 :: R6W , MSP430 :: R7W , MSP430 :: R8W , MSP430 :: R9W , MSP430 :: R10W , MSP430 :: R11W , MSP430 :: R12W , MSP430 :: R13W , MSP430 :: R14W , MSP430 :: R15W , 0 } ; if ( hasFP ( * MF ) ) return ( F -> getCallingConv ( ) == CallingConv :: MSP430_INTR ? CalleeSavedRegsIntrFP : CalleeSavedRegsFP ) ; else return ( F -> getCallingConv ( ) == CallingConv :: MSP430_INTR ? CalleeSavedRegsIntr : CalleeSavedRegs ) ; } </s>


<s> static tree aarch64_builtin_decl ( unsigned int code , bool initialize_p ) { unsigned int subcode = code >> AARCH64_BUILTIN_SHIFT ; switch ( code & AARCH64_BUILTIN_CLASS ) { case AARCH64_BUILTIN_GENERAL : return aarch64_general_builtin_decl ( subcode , initialize_p ) ; case AARCH64_BUILTIN_SVE : return aarch64_sve :: builtin_decl ( subcode , initialize_p ) ; } gcc_unreachable ( ) ; } </s>


<s> static rtx sparc_struct_value_rtx ( tree fndecl , int incoming ) { if ( TARGET_ARCH64 ) return NULL_RTX ; else { rtx mem ; if ( incoming ) mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , frame_pointer_rtx , STRUCT_VALUE_OFFSET ) ) ; else mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , STRUCT_VALUE_OFFSET ) ) ; if ( incoming == 2 && sparc_std_struct_return && TYPE_SIZE_UNIT ( TREE_TYPE ( fndecl ) ) && TREE_CODE ( TYPE_SIZE_UNIT ( TREE_TYPE ( fndecl ) ) ) == INTEGER_CST ) { rtx ret_reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; rtx scratch = gen_reg_rtx ( SImode ) ; rtx_code_label * endlab = gen_label_rtx ( ) ; tree size = TYPE_SIZE_UNIT ( TREE_TYPE ( fndecl ) ) ; rtx size_rtx = GEN_INT ( TREE_INT_CST_LOW ( size ) & 0xfff ) ; rtx temp_val = assign_stack_local ( Pmode , TREE_INT_CST_LOW ( size ) , 0 ) ; emit_move_insn ( scratch , gen_rtx_MEM ( SImode , plus_constant ( Pmode , ret_reg , 8 ) ) ) ; emit_insn ( gen_add3_insn ( ret_reg , ret_reg , GEN_INT ( 4 ) ) ) ; emit_cmp_and_jump_insns ( scratch , size_rtx , EQ , const0_rtx , SImode , 0 , endlab ) ; emit_insn ( gen_sub3_insn ( ret_reg , ret_reg , GEN_INT ( 4 ) ) ) ; emit_move_insn ( mem , XEXP ( temp_val , 0 ) ) ; emit_label ( endlab ) ; } return mem ; } } </s>

Handle the TARGET_STRUCT_VALUE target hook . Return where to find the structure return value address .


<s> bool AArch64ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const AArch64InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; bool Modified = false ; for ( auto & MBB : MF ) Modified |= expandMBB ( MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> const std :: string & HexagonAbsoluteStub :: name ( ) const { return m_Name ; } </s>

Gets the name of the pass we are mixed into .


<s>
static
int
set_exe
(
const
char
*
arg
)
{
char
allargs
[
1024
]
;
int
res
;
snprintf
(
allargs
,
sizeof
(
allargs
)
,
"$@gnu:[bin]set_exe %s %s"
,
exefullfilename
,
arg
)
;
if
(
verbose
)
printf
(
"%s\n"
,
allargs
)
;
res
=
system
(
allargs
)
;
if
(
verbose
>
1
)
printf
(
"$!status = %d\n"
,
res
)
;
if
(
(
res
&
1
)
!=
1
)
{
fprintf
(
stderr
,
"ld error: popen set_exe\n"
)
;
return
1
;
}
return
0
;
}
</s>

Set environment defined executable attributes .


<s> static rtx ia64_function_incoming_arg ( cumulative_args_t cum , machine_mode mode , const_tree type , bool named ) { return ia64_function_arg_1 ( cum , mode , type , named , true ) ; } </s>

Implement TARGET_FUNCION_INCOMING_ARG target hook .


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { TM = static_cast < const PPCTargetMachine * > ( & MF . getTarget ( ) ) ; TII = TM -> getInstrInfo ( ) ; bool Changed = false ; if ( MF . size ( ) < 2 ) return Changed ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed = true ; } return Changed ; } </s>


<s> static reg_class_t csky_spill_class ( reg_class_t rclass , machine_mode mode ATTRIBUTE_UNUSED ) { if ( ( rclass == MINI_REGS && ! TARGET_MINI_REGISTERS ) || ( rclass == LOW_REGS && TARGET_HIGH_REGISTERS ) ) return GENERAL_REGS ; return NO_REGS ; } </s>

Implement TARGET_SPILL_CLASS . Try spilling to a larger register class before spilling to memory .


<s> static const char * svpattern_token ( enum aarch64_svpattern pattern ) { switch ( pattern ) { AARCH64_FOR_SVPATTERN ( CASE ) case AARCH64_NUM_SVPATTERNS : break ; } gcc_unreachable ( ) ; } </s>

Return the assembly token for svpattern value VALUE .


<s> static int num_insns_constant_gpr ( HOST_WIDE_INT value ) { if ( SIGNED_INTEGER_16BIT_P ( value ) ) return 1 ; else if ( ( value & 0xffff ) == 0 && ( value >> 31 == - 1 || value >> 31 == 0 ) ) return 1 ; else if ( TARGET_PREFIXED && SIGNED_INTEGER_34BIT_P ( value ) ) return 1 ; else if ( TARGET_POWERPC64 ) { HOST_WIDE_INT low = sext_hwi ( value , 32 ) ; HOST_WIDE_INT high = value >> 31 ; if ( high == 0 || high == - 1 ) return 2 ; high >>= 1 ; if ( low == 0 || low == high ) return num_insns_constant_gpr ( high ) + 1 ; else if ( high == 0 ) return num_insns_constant_gpr ( low ) + 1 ; else return ( num_insns_constant_gpr ( high ) + num_insns_constant_gpr ( low ) + 1 ) ; } else return 2 ; } </s>

Helper for num_insns_constant . Calculate number of instructions to load VALUE to a single gpr using combinations of addi , addis , ori , oris , sldi and rldimi instructions .


Expand setmem , as if from a __builtin_memset . Return true if we succeed , otherwise return false .


"unexpected argument to msp430_select_hwmult_lib: %s"

"unrecognized hwpy field in msp430_mcu_data[%d]: %d"

"unexpected first argument to msp430_select_hwmult_lib: %s"

"msp430_select_hwmult_lib needs one or more arguments"

Implement spec function ` msp430_hwmult_lib麓 .


<s>
const
char
*
output_probe_stack_range
(
rtx
reg1
,
rtx
reg2
)
{
static
int
labelno
=
0
;
char
loop_lab
[
32
]
;
rtx
xops
[
2
]
;
ASM_GENERATE_INTERNAL_LABEL
(
loop_lab
,
"LPSRL"
,
labelno
++
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
loop_lab
)
;
xops
[
0
]
=
reg1
;
xops
[
1
]
=
GEN_INT
(
PROBE_INTERVAL
)
;
output_asm_insn
(
"sub\t%0, %0, %1"
,
xops
)
;
output_asm_insn
(
"str\tr0, [%0, #0]"
,
xops
)
;
xops
[
1
]
=
reg2
;
output_asm_insn
(
"cmp\t%0, %1"
,
xops
)
;
fputs
(
"\tbne\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
loop_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
return
""
;
}
</s>

Wrapper around the output_probe_stack_range routines .


<s> bool AMDGPUTTI :: hasBranchDivergence ( ) const { return true ; } </s>

Return true if branch divergence exists .


<s>
BitVector
ARMBaseRegisterInfo
::
getReservedRegs
(
const
MachineFunction
&
MF
)
const
{
const
ARMSubtarget
&
STI
=
MF
.
getSubtarget
<
ARMSubtarget
>
(
)
;
const
ARMFrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
BitVector
Reserved
(
getNumRegs
(
)
)
;
markSuperRegs
(
Reserved
,
ARM
::
SP
)
;
markSuperRegs
(
Reserved
,
ARM
::
PC
)
;
markSuperRegs
(
Reserved
,
ARM
::
FPSCR
)
;
markSuperRegs
(
Reserved
,
ARM
::
APSR_NZCV
)
;
if
(
TFI
->
hasFP
(
MF
)
)
markSuperRegs
(
Reserved
,
getFramePointerReg
(
STI
)
)
;
if
(
hasBasePointer
(
MF
)
)
markSuperRegs
(
Reserved
,
BasePtr
)
;
if
(
STI
.
isR9Reserved
(
)
)
markSuperRegs
(
Reserved
,
ARM
::
R9
)
;
if
(
MF
.
getFunction
(
)
.
isPagerando
(
)
)
markSuperRegs
(
Reserved
,
ARM
::
R9
)
;
if
(
!
STI
.
hasVFP3
(
)
||
STI
.
hasD16
(
)
)
{
static_assert
(
ARM
::
D31
==
ARM
::
D16
+
15
,
"Register list not consecutive!"
)
;
for
(
unsigned
R
=
0
;
R
<
16
;
++
R
)
markSuperRegs
(
Reserved
,
ARM
::
D16
+
R
)
;
}
const
TargetRegisterClass
&
RC
=
ARM
::
GPRPairRegClass
;
for
(
unsigned
Reg
:
RC
)
for
(
MCSubRegIterator
SI
(
Reg
,
this
)
;
SI
.
isValid
(
)
;
++
SI
)
if
(
Reserved
.
test
(
*
SI
)
)
markSuperRegs
(
Reserved
,
Reg
)
;
assert
(
checkAllSuperRegsMarked
(
Reserved
)
)
;
return
Reserved
;
}
</s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void GCNPassConfig :: addPreEmitPass ( ) { addPass ( & PostRAHazardRecognizerID ) ; addPass ( createSIInsertWaitsPass ( ) ) ; addPass ( createSIShrinkInstructionsPass ( ) ) ; addPass ( & SIInsertSkipsPassID ) ; addPass ( createSIDebuggerInsertNopsPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


"inserting int3 after trailing call instruction:\n"

"inserting int3 in trailing empty MBB:\n"


"Fill value of memset must be a compile time constant"

"Size in memset call must be a compile time constant"

"memset may be called only for local memory"

"Size in memset must be a multiple of space unit"

Emit target-specific code that performs a memset .


<s>
void
MetadataStreamerV2
::
verify
(
StringRef
HSAMetadataString
)
const
{
errs
(
)
<<
"AMDGPU HSA Metadata Parser Test: "
;
HSAMD
::
Metadata
FromHSAMetadataString
;
if
(
fromString
(
std
::
string
(
HSAMetadataString
)
,
FromHSAMetadataString
)
)
{
errs
(
)
<<
"FAIL\n"
;
return
;
}
std
::
string
ToHSAMetadataString
;
if
(
toString
(
FromHSAMetadataString
,
ToHSAMetadataString
)
)
{
errs
(
)
<<
"FAIL\n"
;
return
;
}
errs
(
)
<<
(
HSAMetadataString
==
ToHSAMetadataString
"PASS"
:
"FAIL"
)
<<
'\n'
;
if
(
HSAMetadataString
!=
ToHSAMetadataString
)
{
errs
(
)
<<
"Original input: "
<<
HSAMetadataString
<<
'\n'
<<
"Produced output: "
<<
ToHSAMetadataString
<<
'\n'
;
}
}
</s>

AMDGPU
"AMDGPU HSA Metadata Parser Test: "
"FAIL\n"
"FAIL\n"
"PASS"
"FAIL"
"Original input: "
"Produced output: "


<s> bool ARCFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; bool HasFP = MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) . hasVarSizedObjects ( ) || MF . getFrameInfo ( ) . isFrameAddressTaken ( ) || RegInfo -> hasStackRealignment ( MF ) ; return HasFP ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
const
MCPhysReg
*
RISCVRegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
auto
&
Subtarget
=
MF
->
getSubtarget
<
RISCVSubtarget
>
(
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_NoRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
hasFnAttribute
(
"interrupt"
)
)
{
if
(
Subtarget
.
hasStdExtD
(
)
)
return
CSR_XLEN_F64_Interrupt_SaveList
;
if
(
Subtarget
.
hasStdExtF
(
)
)
return
CSR_XLEN_F32_Interrupt_SaveList
;
return
CSR_Interrupt_SaveList
;
}
switch
(
Subtarget
.
getTargetABI
(
)
)
{
default
:
llvm_unreachable
(
"Unrecognized ABI"
)
;
case
RISCVABI
::
ABI_ILP32
:
case
RISCVABI
::
ABI_LP64
:
return
CSR_ILP32_LP64_SaveList
;
case
RISCVABI
::
ABI_ILP32F
:
case
RISCVABI
::
ABI_LP64F
:
return
CSR_ILP32F_LP64F_SaveList
;
case
RISCVABI
::
ABI_ILP32D
:
case
RISCVABI
::
ABI_LP64D
:
return
CSR_ILP32D_LP64D_SaveList
;
}
}
</s>


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Sparc Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void HexagonFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; auto & HST = static_cast < const HexagonSubtarget & > ( MF . getSubtarget ( ) ) ; auto & HRI = * HST . getRegisterInfo ( ) ; bool HasEHReturn = MF . getInfo < HexagonMachineFunctionInfo > ( ) -> hasEHReturn ( ) ; if ( HasEHReturn ) { for ( const MCPhysReg * CSRegs = HRI . getCalleeSavedRegs ( & MF ) ; * CSRegs ; ++ CSRegs ) SavedRegs . set ( * CSRegs ) ; } const TargetRegisterClass & RC = Hexagon :: IntRegsRegClass ; bool HasReplacedPseudoInst = replacePredRegPseudoSpillCode ( MF ) ; if ( HasReplacedPseudoInst && needToReserveScavengingSpillSlots ( MF , HRI ) ) { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; for ( int i = 0 ; i < NumberScavengerSlots ; i ++ ) RS -> addScavengingFrameIndex ( MFI -> CreateSpillStackObject ( RC . getSize ( ) , RC . getAlignment ( ) ) ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .

Hexagon Hexagon Hexagon Hexagon Hexagon::IntRegsRegClass 0


"Frame indices can only appear as a debug operand in a DBG_VALUE*"

runOnMachineFunction - Emit the function body .


<s> static bool classof ( const Shape * S ) { return S -> getKind ( ) == SK_Loop ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s>
const
char
*
Cpu0AsmPrinter
::
getCurrentABIString
(
)
const
{
switch
(
static_cast
<
Cpu0TargetMachine
&
>
(
TM
)
.
getABI
(
)
.
GetEnumValue
(
)
)
{
case
Cpu0ABIInfo
::
ABI
::
O32
:
return
"abiO32"
;
case
Cpu0ABIInfo
::
ABI
::
S32
:
return
"abiS32"
;
default
:
llvm_unreachable
(
"Unknown Cpu0 ABI"
)
;
}
}
</s>


<s> static void set_rop_modrm_reg_bits ( int base , HARD_REG_SET & in , HARD_REG_SET & out ) { SET_HARD_REG_BIT ( out , base ) ; SET_HARD_REG_BIT ( out , base + 1 ) ; SET_HARD_REG_BIT ( in , base + 2 ) ; SET_HARD_REG_BIT ( in , base + 3 ) ; } </s>

Given a register number BASE , the lowest of a group of registers , update regsets IN and OUT with the registers that should be avoided in input and output operands respectively when trying to avoid generating a modr/m byte for -mmitigate-rop .


<s> virtual unsigned getNumFixupKinds ( ) const { return 0 ; } </s>

Get the number of target specific fixup kinds .


<s>
unsigned
TGSIRegisterInfo
::
getFrameRegister
(
const
MachineFunction
&
MF
)
const
{
llvm_unreachable
(
"What is the frame register"
)
;
return
0
;
}
</s>

TGSI
TGSI
"What is the frame register"
0


<s> void arc_expand_prologue ( void ) { int size = get_frame_size ( ) ; unsigned int gmask = cfun -> machine -> frame_info . gmask ; unsigned int frame_size_to_allocate ; int first_offset = 0 ; size = ARC_STACK_ALIGN ( size ) ; size = ( ! cfun -> machine -> frame_info . initialized ? arc_compute_frame_size ( size ) : cfun -> machine -> frame_info . total_size ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = size ; frame_size_to_allocate = size ; gcc_assert ( ! ( size == 0 && gmask ) ) ; if ( cfun -> machine -> frame_info . pretend_size != 0 ) { gcc_assert ( cfun -> machine -> frame_info . pretend_size <= 32 ) ; frame_stack_add ( - ( HOST_WIDE_INT ) cfun -> machine -> frame_info . pretend_size ) ; frame_size_to_allocate -= cfun -> machine -> frame_info . pretend_size ; } if ( MUST_SAVE_RETURN_ADDR ) { rtx ra = gen_rtx_REG ( SImode , RETURN_ADDR_REGNUM ) ; rtx mem = gen_frame_mem ( Pmode , gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ) ; frame_move_inc ( mem , ra , stack_pointer_rtx , 0 ) ; frame_size_to_allocate -= UNITS_PER_WORD ; } if ( cfun -> machine -> frame_info . reg_size ) { first_offset = - cfun -> machine -> frame_info . reg_size ; arc_save_restore ( stack_pointer_rtx , gmask , 0 , & first_offset ) ; frame_size_to_allocate -= cfun -> machine -> frame_info . reg_size ; } if ( frame_pointer_needed ) { rtx addr = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( - UNITS_PER_WORD + first_offset ) ) ; rtx mem = gen_frame_mem ( Pmode , gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , addr ) ) ; frame_move_inc ( mem , frame_pointer_rtx , stack_pointer_rtx , 0 ) ; frame_size_to_allocate -= UNITS_PER_WORD ; first_offset = 0 ; frame_move ( frame_pointer_rtx , stack_pointer_rtx ) ; } frame_size_to_allocate -= first_offset ; if ( frame_size_to_allocate > 0 ) frame_stack_add ( ( HOST_WIDE_INT ) 0 - frame_size_to_allocate ) ; if ( crtl -> uses_pic_offset_table ) arc_finalize_pic ( ) ; } </s>

Set up the stack and frame pointer ( if desired ) for the function .


<s> static rtx rx_function_value ( const_tree ret_type , const_tree fn_decl_or_type ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode mode = TYPE_MODE ( ret_type ) ; if ( GET_MODE_SIZE ( mode ) > 0 && GET_MODE_SIZE ( mode ) < 4 && ! COMPLEX_MODE_P ( mode ) && ! VECTOR_TYPE_P ( ret_type ) && ! VECTOR_MODE_P ( mode ) ) return gen_rtx_REG ( SImode , FUNC_RETURN_REGNUM ) ; return gen_rtx_REG ( mode , FUNC_RETURN_REGNUM ) ; } </s>

Return an RTL describing where a function return value of type RET_TYPE is held .


<s> const char * AArch64TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case AArch64ISD :: BR_CC : return "AArch64ISD::BR_CC" ; case AArch64ISD :: Call : return "AArch64ISD::Call" ; case AArch64ISD :: FPMOV : return "AArch64ISD::FPMOV" ; case AArch64ISD :: GOTLoad : return "AArch64ISD::GOTLoad" ; case AArch64ISD :: BFI : return "AArch64ISD::BFI" ; case AArch64ISD :: EXTR : return "AArch64ISD::EXTR" ; case AArch64ISD :: Ret : return "AArch64ISD::Ret" ; case AArch64ISD :: SBFX : return "AArch64ISD::SBFX" ; case AArch64ISD :: SELECT_CC : return "AArch64ISD::SELECT_CC" ; case AArch64ISD :: SETCC : return "AArch64ISD::SETCC" ; case AArch64ISD :: TC_RETURN : return "AArch64ISD::TC_RETURN" ; case AArch64ISD :: THREAD_POINTER : return "AArch64ISD::THREAD_POINTER" ; case AArch64ISD :: TLSDESCCALL : return "AArch64ISD::TLSDESCCALL" ; case AArch64ISD :: WrapperLarge : return "AArch64ISD::WrapperLarge" ; case AArch64ISD :: WrapperSmall : return "AArch64ISD::WrapperSmall" ; case AArch64ISD :: NEON_BSL : return "AArch64ISD::NEON_BSL" ; case AArch64ISD :: NEON_MOVIMM : return "AArch64ISD::NEON_MOVIMM" ; case AArch64ISD :: NEON_MVNIMM : return "AArch64ISD::NEON_MVNIMM" ; case AArch64ISD :: NEON_FMOVIMM : return "AArch64ISD::NEON_FMOVIMM" ; case AArch64ISD :: NEON_CMP : return "AArch64ISD::NEON_CMP" ; case AArch64ISD :: NEON_CMPZ : return "AArch64ISD::NEON_CMPZ" ; case AArch64ISD :: NEON_TST : return "AArch64ISD::NEON_TST" ; case AArch64ISD :: NEON_DUPIMM : return "AArch64ISD::NEON_DUPIMM" ; case AArch64ISD :: NEON_QSHLs : return "AArch64ISD::NEON_QSHLs" ; case AArch64ISD :: NEON_QSHLu : return "AArch64ISD::NEON_QSHLu" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> bool riscv_can_use_return_insn ( void ) { return ( reload_completed && cfun -> machine -> frame . total_size == 0 && ! cfun -> machine -> interrupt_handler_p ) ; } </s>

Return nonzero if this function is known to have a null epilogue . This allows the optimizer to omit jumps to jumps if no stack was created .


"the destination register can't equal the base register in an "

"instruction that modifies the base register."

ParseInstruction - Parse one assembly instruction .


<s> virtual MVT getShiftAmountTy ( EVT LHSTy ) const { return MVT :: i32 ; } </s>

Returns the type for the shift amount of a shift opcode .


<s> MachineInstr * AArch64InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , int FrameIndex ) const { if ( MI -> isCopy ( ) ) { unsigned DstReg = MI -> getOperand ( 0 ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; if ( SrcReg == AArch64 :: SP && TargetRegisterInfo :: isVirtualRegister ( DstReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( DstReg , & AArch64 :: GPR64RegClass ) ; return nullptr ; } if ( DstReg == AArch64 :: SP && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & AArch64 :: GPR64RegClass ) ; return nullptr ; } } return nullptr ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> bool ix86_using_red_zone ( void ) { return TARGET_RED_ZONE && ! TARGET_64BIT_MS_ABI ; } </s>


<s> InstructionCost HexagonTTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: TargetCostKind CostKind , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args , const Instruction * CxtI ) { if ( CostKind != TTI :: TCK_RecipThroughput ) return BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo , Args , CxtI ) ; if ( Ty -> isVectorTy ( ) ) { std :: pair < InstructionCost , MVT > LT = TLI . getTypeLegalizationCost ( DL , Ty ) ; if ( LT . second . isFloatingPoint ( ) ) return LT . first + FloatFactor * getTypeNumElements ( Ty ) ; } return BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo , Args , CxtI ) ; } </s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> const SISubtarget * SITargetLowering :: getSubtarget ( ) const { return static_cast < const SISubtarget * > ( Subtarget ) ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


<s> SDValue X86TargetLowering :: getPICJumpTableRelocBase ( SDValue Table , SelectionDAG & DAG ) const { if ( ! Subtarget -> is64Bit ( ) ) return DAG . getNode ( X86ISD :: GlobalBaseReg , DebugLoc ( ) , getPointerTy ( ) ) ; return Table ; } </s>

Returns relocation base for the given PIC jumptable .


"movhi hi(%s), r0, r6\n\tmovea lo(%s), r6, r6\n\tjmp r6"

Construct a JR instruction to a routine that will perform the equivalent of the RTL passed in as an argument . This RTL is a function epilogue that pops registers off the stack and possibly releases some extra stack space as well . The code has already verified that the RTL matches these requirements .


<s> int m68hc11_register_move_cost ( enum machine_mode mode , enum reg_class from , enum reg_class to ) { if ( from < to ) { enum reg_class tmp = to ; to = from , from = tmp ; } if ( to >= S_REGS ) return m68hc11_memory_move_cost ( mode , S_REGS , 0 ) ; else if ( from <= S_REGS ) return COSTS_N_INSNS ( 1 ) + ( reload_completed | reload_in_progress ) ; else return COSTS_N_INSNS ( 2 ) ; } </s>

Cost of moving data from a register of class 'from ' to on in class 'to ' . Reload does not check the constraint of set insns when the two registers have a move cost of 2 . Setting a higher cost will force reload to check the constraints .


<s> void AMDGPUPassConfig :: addCodeGenPrepare ( ) { const AMDGPUSubtarget & ST = * getAMDGPUTargetMachine ( ) . getSubtargetImpl ( ) ; if ( ST . isPromoteAllocaEnabled ( ) ) { addPass ( createAMDGPUPromoteAlloca ( ST ) ) ; addPass ( createSROAPass ( ) ) ; } TargetPassConfig :: addCodeGenPrepare ( ) ; } </s>

Add pass to prepare the LLVM IR for code generation .


"empty class %qT parameter passing ABI "

"changes in %<-fabi-version=12%> (GCC 8)"


<s> static bool h8300_legitimate_address_p ( machine_mode mode , rtx x , bool strict ) { if ( h8300_rtx_ok_for_base_p ( x , strict ) ) return 1 ; if ( CONSTANT_ADDRESS_P ( x ) ) return 1 ; if ( TARGET_H8300SX && ( GET_CODE ( x ) == PRE_INC || GET_CODE ( x ) == PRE_DEC || GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == POST_DEC ) && h8300_rtx_ok_for_base_p ( XEXP ( x , 0 ) , strict ) ) return 1 ; if ( GET_CODE ( x ) == PLUS && CONSTANT_ADDRESS_P ( XEXP ( x , 1 ) ) && h8300_rtx_ok_for_base_p ( h8300_get_index ( XEXP ( x , 0 ) , mode , 0 ) , strict ) ) return 1 ; return 0 ; } </s>

Return nozero if X is a legitimate address . On the H8/300 , a legitimate address has the form REG , REG+CONSTANT_ADDRESS or CONSTANT_ADDRESS .


<s>
bool
AArch64InstrInfo
::
areMemAccessesTriviallyDisjoint
(
const
MachineInstr
&
MIa
,
const
MachineInstr
&
MIb
,
AliasAnalysis
*
AA
)
const
{
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
const
MachineOperand
*
BaseOpA
=
nullptr
,
*
BaseOpB
=
nullptr
;
int64_t
OffsetA
=
0
,
OffsetB
=
0
;
unsigned
WidthA
=
0
,
WidthB
=
0
;
assert
(
MIa
.
mayLoadOrStore
(
)
&&
"MIa must be a load or store."
)
;
assert
(
MIb
.
mayLoadOrStore
(
)
&&
"MIb must be a load or store."
)
;
if
(
MIa
.
hasUnmodeledSideEffects
(
)
||
MIb
.
hasUnmodeledSideEffects
(
)
||
MIa
.
hasOrderedMemoryRef
(
)
||
MIb
.
hasOrderedMemoryRef
(
)
)
return
false
;
if
(
getMemOperandWithOffsetWidth
(
MIa
,
BaseOpA
,
OffsetA
,
WidthA
,
TRI
)
&&
getMemOperandWithOffsetWidth
(
MIb
,
BaseOpB
,
OffsetB
,
WidthB
,
TRI
)
)
{
if
(
BaseOpA
->
isIdenticalTo
(
*
BaseOpB
)
)
{
int
LowOffset
=
OffsetA
<
OffsetB
OffsetA
:
OffsetB
;
int
HighOffset
=
OffsetA
<
OffsetB
OffsetB
:
OffsetA
;
int
LowWidth
=
(
LowOffset
==
OffsetA
)
WidthA
:
WidthB
;
if
(
LowOffset
+
LowWidth
<=
HighOffset
)
return
true
;
}
}
return
false
;
}
</s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s>
TargetLowering
::
AtomicExpansionKind
X86TargetLowering
::
shouldExpandAtomicRMWInIR
(
AtomicRMWInst
*
AI
)
const
{
unsigned
NativeWidth
=
Subtarget
.
is64Bit
(
)
64
:
32
;
Type
*
MemType
=
AI
->
getType
(
)
;
if
(
MemType
->
getPrimitiveSizeInBits
(
)
>
NativeWidth
)
{
return
needsCmpXchgNb
(
MemType
)
AtomicExpansionKind
::
CmpXChg
:
AtomicExpansionKind
::
;
}
AtomicRMWInst
::
BinOp
Op
=
AI
->
getOperation
(
)
;
switch
(
Op
)
{
default
:
llvm_unreachable
(
"Unknown atomic operation"
)
;
case
AtomicRMWInst
::
Xchg
:
case
AtomicRMWInst
::
Add
:
case
AtomicRMWInst
::
Sub
:
return
AtomicExpansionKind
::
;
case
AtomicRMWInst
::
Or
:
case
AtomicRMWInst
::
And
:
case
AtomicRMWInst
::
Xor
:
return
shouldExpandLogicAtomicRMWInIR
(
AI
)
;
case
AtomicRMWInst
::
Nand
:
case
AtomicRMWInst
::
Max
:
case
AtomicRMWInst
::
Min
:
case
AtomicRMWInst
::
UMax
:
case
AtomicRMWInst
::
UMin
:
case
AtomicRMWInst
::
FAdd
:
case
AtomicRMWInst
::
FSub
:
return
AtomicExpansionKind
::
CmpXChg
;
}
}
</s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


"%qE attribute only applies to functions"

Handle a `` naked '' attribute ; arguments as in struct attribute_spec.handler .


<s> static bool arm_evpc_neon_vzip ( struct expand_vec_perm_d * d ) { unsigned int i , high , mask , nelt = d -> nelt ; rtx out0 , out1 , in0 , in1 , x ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; high = nelt / 2 ; if ( d -> perm [ 0 ] == high ) ; else if ( d -> perm [ 0 ] == 0 ) high = 0 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt / 2 ; i ++ ) { unsigned elt = ( i + high ) & mask ; if ( d -> perm [ i * 2 ] != elt ) return false ; elt = ( elt + nelt ) & mask ; if ( d -> perm [ i * 2 + 1 ] != elt ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vzipv16qi_internal ; break ; case V8QImode : gen = gen_neon_vzipv8qi_internal ; break ; case V8HImode : gen = gen_neon_vzipv8hi_internal ; break ; case V4HImode : gen = gen_neon_vzipv4hi_internal ; break ; case V4SImode : gen = gen_neon_vzipv4si_internal ; break ; case V2SImode : gen = gen_neon_vzipv2si_internal ; break ; case V2SFmode : gen = gen_neon_vzipv2sf_internal ; break ; case V4SFmode : gen = gen_neon_vzipv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN ) { x = in0 , in0 = in1 , in1 = x ; high = ! high ; } out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( high ) x = out0 , out0 = out1 , out1 = x ; emit_insn ( gen ( out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s> bool RISCVAsmBackend :: fixupNeedsRelaxationAdvanced ( const MCFixup & Fixup , bool Resolved , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout , const bool WasForced ) const { if ( ! Resolved && ! WasForced ) return true ; int64_t Offset = int64_t ( Value ) ; switch ( Fixup . getTargetKind ( ) ) { default : return false ; case RISCV :: fixup_riscv_rvc_branch : return Offset > 254 || Offset < - 256 ; case RISCV :: fixup_riscv_rvc_jump : return Offset > 2046 || Offset < - 2048 ; } } </s>

Target specific predicate for whether a given fixup requires the associated instruction to be relaxed .


<s>
void
Thumb1InstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
->
hasSuperClassEq
(
&
ARM
::
tGPRRegClass
)
||
(
Register
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
->
hasSuperClassEq
(
&
ARM
::
tGPRRegClass
)
||
(
Register
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
,
MachineMemOperand
::
MOLoad
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tLDRspi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .

ARM
ARM::tGPRRegClass
ARM
"Unknown regclass!"
ARM::tGPRRegClass
ARM
ARM::tLDRspi
0
ARMCC::AL


<s> static const char * detect_processor_aix ( void ) { switch ( _system_configuration . implementation ) { case 0x0008 : return "601" ; case 0x0020 : return "603" ; case 0x0010 : return "604" ; case 0x0040 : return "620" ; case 0x0080 : return "630" ; case 0x0100 : case 0x0200 : case 0x0400 : return "rs64" ; case 0x0800 : return "power4" ; case 0x2000 : if ( _system_configuration . version == 0x0F0000 ) return "power5" ; else return "power5+" ; case 0x4000 : return "power6" ; case 0x8000 : return "power7" ; case 0x10000 : return "power8" ; case 0x20000 : return "power9" ; default : return "powerpc" ; } } </s>

Returns the processor implementation on AIX .


<s> bool X86ATTAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : break ; case 'P' : printMemReference ( MI , OpNo , "no-rip" ) ; return false ; } } printMemReference ( MI , OpNo ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> static void pru_elf_asm_destructor ( rtx symbol , int priority ) { char buf [ 23 ] ; section * s ; if ( priority == DEFAULT_INIT_PRIORITY ) snprintf ( buf , sizeof ( buf ) , ".fini_array" ) ; else { snprintf ( buf , sizeof ( buf ) , ".fini_array.%.5u" , priority ) ; } s = get_section ( buf , SECTION_WRITE | SECTION_NOTYPE , NULL ) ; switch_to_section ( s ) ; assemble_aligned_integer ( INIT_ARRAY_ENTRY_BYTES , symbol ) ; } </s>


"Stack alignment other than 4 byte is not supported"

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> unsigned GCNTTIImpl :: getNumberOfRegisters ( unsigned RCID ) const { const SIRegisterInfo * TRI = ST -> getRegisterInfo ( ) ; const TargetRegisterClass * RC = TRI -> getRegClass ( RCID ) ; unsigned NumVGPRs = ( TRI -> getRegSizeInBits ( * RC ) + 31 ) / 32 ; return getHardwareNumberOfRegisters ( false ) / NumVGPRs ; } </s>


<s> bool MipsTargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createMipsISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static bool nds32_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { return ( ! TARGET_V3PUSH && ! nds32_isr_function_p ( current_function_decl ) && ( cfun -> machine -> va_args_size == 0 ) && decl && ! flag_pic ) ; } </s>

Return true if it is ok to do sibling call optimization .


<s> static bool s390_decompose_constant_pool_ref ( rtx * ref , rtx * disp , bool * is_ptr , bool * is_base_ptr , bool * is_pool_ptr ) { if ( ! * ref ) return true ; if ( GET_CODE ( * ref ) == UNSPEC ) switch ( XINT ( * ref , 1 ) ) { case UNSPEC_LTREF : if ( ! * disp ) * disp = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , XVECEXP ( * ref , 0 , 0 ) ) , UNSPEC_LTREL_OFFSET ) ; else return false ; * ref = XVECEXP ( * ref , 0 , 1 ) ; break ; default : return false ; } if ( ! REG_P ( * ref ) || GET_MODE ( * ref ) != Pmode ) return false ; if ( REGNO ( * ref ) == STACK_POINTER_REGNUM || REGNO ( * ref ) == FRAME_POINTER_REGNUM || ( ( reload_completed || reload_in_progress ) && frame_pointer_needed && REGNO ( * ref ) == HARD_FRAME_POINTER_REGNUM ) || REGNO ( * ref ) == ARG_POINTER_REGNUM || ( flag_pic && REGNO ( * ref ) == PIC_OFFSET_TABLE_REGNUM ) ) * is_ptr = * is_base_ptr = true ; if ( ( reload_completed || reload_in_progress ) && * ref == cfun -> machine -> base_reg ) * is_ptr = * is_base_ptr = * is_pool_ptr = true ; return true ; } </s>

Attempts to split ` ref ' , which should be UNSPEC_LTREF , into ( base + ` disp ' ) . If successful , also determines the following characteristics of ` ref ' : ` is_ptr ' - whether it can be an LA argument , ` is_base_ptr ' - whether the resulting base is a well-known base register ( stack/frame pointer , etc ) , ` is_pool_ptr ` - whether it is considered a literal pool pointer for purposes of avoiding two different literal pool pointers per insn during or after reload ( ` B ' constraint ) .


<s> bool CSKYInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { TBB = FBB = nullptr ; Cond . clear ( ) ; MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) || ! isUnpredicatedTerminator ( * I ) ) return false ; MachineBasicBlock :: iterator FirstUncondOrIndirectBr = MBB . end ( ) ; int NumTerminators = 0 ; for ( auto J = I . getReverse ( ) ; J != MBB . rend ( ) && isUnpredicatedTerminator ( * J ) ; J ++ ) { NumTerminators ++ ; if ( J -> getDesc ( ) . isUnconditionalBranch ( ) || J -> getDesc ( ) . isIndirectBranch ( ) ) { FirstUncondOrIndirectBr = J . getReverse ( ) ; } } if ( AllowModify && FirstUncondOrIndirectBr != MBB . end ( ) ) { while ( std :: next ( FirstUncondOrIndirectBr ) != MBB . end ( ) ) { std :: next ( FirstUncondOrIndirectBr ) -> eraseFromParent ( ) ; NumTerminators -- ; } I = FirstUncondOrIndirectBr ; } if ( I -> getDesc ( ) . isIndirectBranch ( ) ) return true ; if ( NumTerminators > 2 ) return true ; if ( NumTerminators == 1 && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { TBB = getBranchDestBlock ( * I ) ; return false ; } if ( NumTerminators == 1 && I -> getDesc ( ) . isConditionalBranch ( ) ) { parseCondBranch ( * I , TBB , Cond ) ; return false ; } if ( NumTerminators == 2 && std :: prev ( I ) -> getDesc ( ) . isConditionalBranch ( ) && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { parseCondBranch ( * std :: prev ( I ) , TBB , Cond ) ; FBB = getBranchDestBlock ( * I ) ; return false ; } return true ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


"Can't load this register from stack slot"


<s> void PPCRegisterInfo :: adjustStackMapLiveOutMask ( uint32_t * Mask ) const { for ( unsigned PseudoReg : { PPC :: ZERO , PPC :: ZERO8 , PPC :: RM } ) Mask [ PseudoReg / 32 ] &= ~ ( 1u << ( PseudoReg % 32 ) ) ; } </s>

Prior to adding the live-out mask to a stackmap or patchpoint instruction , provide the target the opportunity to adjust it ( mainly to remove pseudo-registers that should be ignored ) .


"Cannot handle this call frame pseudo instruction"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> BitVector MipsRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t ReservedCPURegs [ ] = { Mips :: ZERO , Mips :: K0 , Mips :: K1 , Mips :: SP } ; static const uint16_t ReservedCPU64Regs [ ] = { Mips :: ZERO_64 , Mips :: K0_64 , Mips :: K1_64 , Mips :: SP_64 } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: const_iterator RegIter ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPU64Regs ) ; ++ I ) Reserved . set ( ReservedCPU64Regs [ I ] ) ; if ( Subtarget . hasMips64 ( ) ) { for ( RegIter Reg = Mips :: AFGR64RegClass . begin ( ) , EReg = Mips :: AFGR64RegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } else { for ( RegIter Reg = Mips :: FGR64RegClass . begin ( ) , EReg = Mips :: FGR64RegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) ) { if ( Subtarget . inMips16Mode ( ) ) Reserved . set ( Mips :: S0 ) ; else { Reserved . set ( Mips :: FP ) ; Reserved . set ( Mips :: FP_64 ) ; } } Reserved . set ( Mips :: HWR29 ) ; Reserved . set ( Mips :: HWR29_64 ) ; Reserved . set ( Mips :: DSPCtrl ) ; if ( Subtarget . inMips16Mode ( ) ) { Reserved . set ( Mips :: RA ) ; Reserved . set ( Mips :: RA_64 ) ; } if ( Subtarget . useSmallSection ( ) ) { Reserved . set ( Mips :: GP ) ; Reserved . set ( Mips :: GP_64 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static bool c6x_function_ok_for_sibcall ( tree decl , tree exp ) { if ( c6x_call_saved_register_used ( exp ) ) return false ; if ( ! flag_pic ) return true ; if ( TARGET_DSBT ) { struct cgraph_local_info * this_func ; if ( ! decl ) return false ; this_func = cgraph_node :: local_info ( current_function_decl ) ; return this_func -> local ; } return true ; } </s>

Decide whether we can make a sibling call to a function . DECL is the declaration of the function being targeted by the call and EXP is the CALL_EXPR representing the call .


<s> bool MipsTargetMachine :: addPreEmitPass ( PassManagerBase & PM , bool Fast ) { PM . add ( createMipsDelaySlotFillerPass ( * this ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> rtx rs6000_emit_set_const ( rtx dest , enum machine_mode mode , rtx source , int n ATTRIBUTE_UNUSED ) { rtx result , insn , set ; HOST_WIDE_INT c0 , c1 ; switch ( mode ) { case QImode : case HImode : if ( dest == NULL ) dest = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , source ) ) ; return dest ; case SImode : result = no_new_pseudos ? dest : gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , result , GEN_INT ( INTVAL ( source ) & ( ~ ( HOST_WIDE_INT ) 0xffff ) ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , gen_rtx_IOR ( SImode , result , GEN_INT ( INTVAL ( source ) & 0xffff ) ) ) ) ; result = dest ; break ; case DImode : switch ( GET_CODE ( source ) ) { case CONST_INT : c0 = INTVAL ( source ) ; c1 = - ( c0 < 0 ) ; break ; case CONST_DOUBLE : c0 = CONST_DOUBLE_LOW ( source ) ; c1 = - ( c0 < 0 ) ; c0 = CONST_DOUBLE_LOW ( source ) ; c1 = CONST_DOUBLE_HIGH ( source ) ; break ; default : gcc_unreachable ( ) ; } result = rs6000_emit_set_long_const ( dest , c0 , c1 ) ; break ; default : gcc_unreachable ( ) ; } insn = get_last_insn ( ) ; set = single_set ( insn ) ; if ( ! CONSTANT_P ( SET_SRC ( set ) ) ) set_unique_reg_note ( insn , REG_EQUAL , source ) ; return result ; } </s>

Try to output insns to set TARGET equal to the constant C if it can be done in less than N insns . Do all computations in MODE . Returns the place where the output has been placed if it can be done and the insns have been emitted . If it would take more than N insns , zero is returned and no insns and emitted .


<s> unsigned getMinPrefetchStride ( ) const override { return MinPrefetchStride ; } </s>

Some HW prefetchers can handle accesses up to a certain constant stride .


<s> unsigned getFramePtr ( ) const { return FramePtr ; } </s>

Returns physical register used as frame pointer .


<s>
void
HexagonEarlyIfConversion
::
removeBlock
(
MachineBasicBlock
*
B
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Removing block "
<<
PrintMB
(
B
)
<<
"\n"
)
;
MachineDomTreeNode
*
N
=
MDT
->
getNode
(
B
)
;
MachineDomTreeNode
*
IDN
=
N
->
getIDom
(
)
;
if
(
IDN
)
{
MachineBasicBlock
*
IDB
=
IDN
->
getBlock
(
)
;
using
GTN
=
GraphTraits
<
MachineDomTreeNode
*
>
;
using
DTNodeVectType
=
SmallVector
<
MachineDomTreeNode
*
,
4
>
;
DTNodeVectType
Cn
(
GTN
::
child_begin
(
N
)
,
GTN
::
child_end
(
N
)
)
;
for
(
DTNodeVectType
::
iterator
I
=
Cn
.
begin
(
)
,
E
=
Cn
.
end
(
)
;
I
!=
E
;
++
I
)
{
MachineBasicBlock
*
SB
=
(
*
I
)
->
getBlock
(
)
;
MDT
->
changeImmediateDominator
(
SB
,
IDB
)
;
}
}
while
(
!
B
->
succ_empty
(
)
)
B
->
removeSuccessor
(
B
->
succ_begin
(
)
)
;
for
(
auto
I
=
B
->
pred_begin
(
)
,
E
=
B
->
pred_end
(
)
;
I
!=
E
;
++
I
)
(
*
I
)
->
removeSuccessor
(
B
,
true
)
;
Deleted
.
insert
(
B
)
;
MDT
->
eraseNode
(
B
)
;
MFN
->
erase
(
B
->
getIterator
(
)
)
;
}
</s>

This method completely removes BB from all data structures , including all of the Loop objects it is nested in and our mapping from MachineBasicBlocks to loops .

Hexagon
Hexagon
"Removing block "
"\n"
4


<s> static void loongarch_emit_probe_stack_range ( HOST_WIDE_INT first , HOST_WIDE_INT size ) { if ( ( TARGET_64BIT && ( first + size <= 32768 ) ) || ( ! TARGET_64BIT && ( first + size <= 2048 ) ) ) { HOST_WIDE_INT i ; for ( i = PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + i ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + size ) ) ) ; } else { HOST_WIDE_INT rounded_size ; rtx r13 = LARCH_PROLOGUE_TEMP ( Pmode ) ; rtx r12 = LARCH_PROLOGUE_TEMP2 ( Pmode ) ; rtx r14 = LARCH_PROLOGUE_TEMP3 ( Pmode ) ; gcc_assert ( first <= 16384 ) ; rounded_size = ROUND_DOWN ( size , PROBE_INTERVAL ) ; if ( first != 0 ) { emit_move_insn ( r14 , GEN_INT ( first ) ) ; emit_insn ( gen_rtx_SET ( r13 , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , r14 ) ) ) ; } else emit_move_insn ( r13 , stack_pointer_rtx ) ; emit_move_insn ( r14 , GEN_INT ( PROBE_INTERVAL ) ) ; if ( rounded_size == 0 ) emit_move_insn ( r12 , r13 ) ; else { emit_move_insn ( r12 , GEN_INT ( rounded_size ) ) ; emit_insn ( gen_rtx_SET ( r12 , gen_rtx_MINUS ( Pmode , r13 , r12 ) ) ) ; emit_insn ( gen_probe_stack_range ( Pmode , r13 , r13 , r12 , r14 ) ) ; } if ( size != rounded_size ) { if ( TARGET_64BIT ) emit_stack_probe ( plus_constant ( Pmode , r12 , rounded_size - size ) ) ; else { HOST_WIDE_INT i ; for ( i = 2048 ; i < ( size - rounded_size ) ; i += 2048 ) { emit_stack_probe ( plus_constant ( Pmode , r12 , - i ) ) ; emit_insn ( gen_rtx_SET ( r12 , plus_constant ( Pmode , r12 , - 2048 ) ) ) ; } rtx r1 = plus_constant ( Pmode , r12 , - ( size - rounded_size - i + 2048 ) ) ; emit_stack_probe ( r1 ) ; } } } emit_insn ( gen_blockage ( ) ) ; } </s>

Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE , inclusive . These are offsets from the current stack pointer .


<s> const RegisterBankInfo :: InstructionMapping & MipsRegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const RegisterBankInfo :: InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; switch ( Opc ) { case G_ADD : case G_LOAD : case G_STORE : case G_GEP : OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; break ; case G_CONSTANT : case G_FRAME_INDEX : case G_GLOBAL_VALUE : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr } ) ; break ; default : return getInvalidInstructionMapping ( ) ; } return getInstructionMapping ( DefaultMappingID , 1 , OperandsMapping , NumOperands ) ; } </s>

Get the mapping of the different operands of MI on the register bank .

Mips Mips Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx 1


<s>
void
MandarinInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
MD
::
GenericRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
MD
::
MOVrr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
else
if
(
MD
::
DoubleRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
MD
::
MOV2rr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
else
if
(
MD
::
DoubleRegsRegClass
.
contains
(
DestReg
)
&&
(
SrcReg
==
MD
::
R0
||
SrcReg
==
MD
::
R2
)
)
{
printf
(
"Registers are already there\n"
)
;
}
else
if
(
MD
::
QuadRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
MD
::
MOV4rr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
else
if
(
MD
::
QuadRegsRegClass
.
contains
(
DestReg
)
&&
SrcReg
==
MD
::
R0
)
{
printf
(
"Registers are already there\n"
)
;
}
else
{
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
}
</s>

Mandarin
MD::GenericRegsRegClass
MD::MOVrr
MD::DoubleRegsRegClass
MD::MOV2rr
MD::DoubleRegsRegClass
MD::R0
MD::R2
"Registers are already there\n"
MD::QuadRegsRegClass
MD::MOV4rr
MD::QuadRegsRegClass
MD::R0
"Registers are already there\n"
"Impossible reg-to-reg copy"


<s>
unsigned
TMS320C64XInstrInfo
::
isLoadFromStackSlot
(
const
MachineInstr
*
MI
,
int
&
FrameIndex
)
const
{
const
TargetInstrDesc
desc
=
MI
->
getDesc
(
)
;
if
(
desc
.
TSFlags
&
TMS320C64XII
::
is_memaccess
&&
!
(
desc
.
TSFlags
&
TMS320C64XII
::
is_store
)
)
{
if
(
MI
->
getOperand
(
0
)
.
getReg
(
)
==
TMS320C64X
::
B15
)
{
MachineOperand
op
=
MI
->
getOperand
(
1
)
;
if
(
op
.
isFI
(
)
)
{
FrameIndex
=
op
.
getIndex
(
)
;
return
true
;
}
else
{
llvm_unreachable
(
"Found load-from-stack sans "
"frame index operand"
)
;
}
}
}
return
false
;
}
</s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


Return nonzero if X ( an RTX ) is a legitimate memory address on the target machine for a memory operand of mode MODE .


<s> bool AArch64TargetLowering :: isShuffleMaskLegal ( ArrayRef < int > M , EVT VT ) const { if ( useSVEForFixedLengthVectorVT ( VT ) ) return false ; if ( VT . getVectorNumElements ( ) == 4 && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned Cost = getPerfectShuffleCost ( M ) ; if ( Cost <= 1 ) return true ; } bool DummyBool ; int DummyInt ; unsigned DummyUnsigned ; return ( ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isREVMask ( M , VT , 64 ) || isREVMask ( M , VT , 32 ) || isREVMask ( M , VT , 16 ) || isEXTMask ( M , VT , DummyBool , DummyUnsigned ) || isTRNMask ( M , VT , DummyUnsigned ) || isUZPMask ( M , VT , DummyUnsigned ) || isZIPMask ( M , VT , DummyUnsigned ) || isTRN_v_undef_Mask ( M , VT , DummyUnsigned ) || isUZP_v_undef_Mask ( M , VT , DummyUnsigned ) || isZIP_v_undef_Mask ( M , VT , DummyUnsigned ) || isINSMask ( M , VT . getVectorNumElements ( ) , DummyBool , DummyInt ) || isConcatMask ( M , VT , VT . getSizeInBits ( ) == 128 ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> bool X86TargetLowering :: isVectorClearMaskLegal ( const SmallVectorImpl < int > & Mask , EVT VT ) const { if ( ! VT . isSimple ( ) ) return false ; MVT SVT = VT . getSimpleVT ( ) ; if ( ExperimentalVectorShuffleLegality ) return isShuffleMaskLegal ( Mask , VT ) ; unsigned NumElts = SVT . getVectorNumElements ( ) ; if ( NumElts == 2 ) return true ; if ( NumElts == 4 && SVT . is128BitVector ( ) ) { return ( isMOVLMask ( Mask , SVT ) || isCommutedMOVLMask ( Mask , SVT , true ) || isSHUFPMask ( Mask , SVT ) || isSHUFPMask ( Mask , SVT , true ) || isBlendMask ( Mask , SVT , Subtarget -> hasSSE41 ( ) , Subtarget -> hasInt256 ( ) ) ) ; } return false ; } </s>


<s> enum indirect_thunk_prefix indirect_thunk_need_prefix ( rtx_insn * insn ) { enum indirect_thunk_prefix need_prefix ; if ( ix86_bnd_prefixed_insn_p ( insn ) ) need_prefix = indirect_thunk_prefix_bnd ; else if ( ( cfun -> machine -> indirect_branch_type == indirect_branch_thunk_extern ) && ix86_notrack_prefixed_insn_p ( insn ) ) { need_prefix = indirect_thunk_prefix_nt ; } else need_prefix = indirect_thunk_prefix_none ; return need_prefix ; } </s>

Return the prefix needed for an indirect branch INSN .


<s> bool XNCMPassConfig :: addPreEmitPass ( ) { return false ; } </s>


<s> bool X86TargetLowering :: isZExtFree ( SDValue Val , EVT VT2 ) const { EVT VT1 = Val . getValueType ( ) ; if ( isZExtFree ( VT1 , VT2 ) ) return true ; if ( Val . getOpcode ( ) != ISD :: LOAD ) return false ; if ( ! VT1 . isSimple ( ) || ! VT1 . isInteger ( ) || ! VT2 . isSimple ( ) || ! VT2 . isInteger ( ) ) return false ; switch ( VT1 . getSimpleVT ( ) . SimpleTy ) { default : break ; case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : return true ; } return false ; } </s>

Return true if zero-extending the specific node Val to type VT2 is free ( either because it 's implicitly zero-extended such as ARM ldrb / ldrh or because it 's folded such as X86 zero-extending loads ) .


"SIInstrInfo::storeRegToStackSlot - Can't spill VGPR!"

Store the specified register of the given register class to the specified stack frame index .


<s> static bool aarch64_vectorize_vec_perm_const ( machine_mode vmode , rtx target , rtx op0 , rtx op1 , const vec_perm_indices & sel ) { struct expand_vec_perm_d d ; if ( op0 && rtx_equal_p ( op0 , op1 ) ) d . one_vector_p = true ; else if ( sel . all_from_input_p ( 0 ) ) { d . one_vector_p = true ; op1 = op0 ; } else if ( sel . all_from_input_p ( 1 ) ) { d . one_vector_p = true ; op0 = op1 ; } else d . one_vector_p = false ; d . perm . new_vector ( sel . encoding ( ) , d . one_vector_p ? 1 : 2 , sel . nelts_per_input ( ) ) ; d . vmode = vmode ; d . vec_flags = aarch64_classify_vector_mode ( d . vmode ) ; d . target = target ; d . op0 = op0 ; d . op1 = op1 ; d . testing_p = ! target ; if ( ! d . testing_p ) return aarch64_expand_vec_perm_const_1 ( & d ) ; rtx_insn * last = get_last_insn ( ) ; bool ret = aarch64_expand_vec_perm_const_1 ( & d ) ; gcc_assert ( last == get_last_insn ( ) ) ; return ret ; } </s>


<s> AtomicRMWExpansionKind shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const override { return AtomicRMWExpansionKind :: LLSC ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> const TargetRegisterClass * getPointerRegClass ( const MachineFunction & MF , unsigned Kind = 0 ) const override { return & RISCV :: GPRRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


"Replacing store %d with permuted store\n"

Convert the non-permuting store INSN to a permuting one .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TargetABI ( computeTargetABI ( TT , CPU , Options ) ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) { if ( isTargetHardFloat ( ) ) this -> Options . FloatABIType = FloatABI :: Hard ; else this -> Options . FloatABIType = FloatABI :: Soft ; } if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( ( TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABI || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF ) && ! ( TargetTriple . isOSWindows ( ) || TargetTriple . isOSDarwin ( ) ) ) this -> Options . EABIVersion = EABI :: GNU ; else this -> Options . EABIVersion = EABI :: EABI5 ; } if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } setSupportsDebugEntryValues ( true ) ; initAsmInfo ( ) ; setMachineOutliner ( true ) ; setSupportsDefaultOutlining ( false ) ; } </s>


<s> static const char * i386_find_on_wrapper_list ( const char * target ) { static char first_time = 1 ; static hash_table < nofree_string_hash > * wrappers ; if ( first_time ) { static char wrapper_list_buffer [ ] = CXX_WRAP_SPEC_LIST ; char * bufptr ; wrappers = new hash_table < nofree_string_hash > ( 8 ) ; for ( bufptr = wrapper_list_buffer ; * bufptr ; ++ bufptr ) { char * found = NULL ; if ( ISSPACE ( * bufptr ) ) continue ; if ( * bufptr == '_' ) found = bufptr ; while ( * bufptr && ! ISSPACE ( * bufptr ) ) ++ bufptr ; if ( * bufptr ) * bufptr = 0 ; if ( found ) * wrappers -> find_slot ( found , INSERT ) = found ; } first_time = 0 ; } return wrappers -> find ( target ) ; } </s>

Search for a function named TARGET in the list of library wrappers we are using , returning a pointer to it if found or NULL if not . This function might be called on quite a few symbols , and we only have the list of names of wrapped functions available to us as a spec string , so first time round we lazily initialise a hash table to make things quicker .


<s> void Hexagon_CCState :: HandleByVal ( unsigned ValNo , EVT ValVT , EVT LocVT , CCValAssign :: LocInfo LocInfo , int MinSize , int MinAlign , ISD :: ArgFlagsTy ArgFlags ) { unsigned Align = ArgFlags . getByValAlign ( ) ; unsigned Size = ArgFlags . getByValSize ( ) ; if ( MinSize > ( int ) Size ) Size = MinSize ; if ( MinAlign > ( int ) Align ) Align = MinAlign ; unsigned Offset = AllocateStack ( Size , Align ) ; addLoc ( CCValAssign :: getMem ( ValNo , ValVT . getSimpleVT ( ) , Offset , LocVT . getSimpleVT ( ) , LocInfo ) ) ; } </s>

Target-specific cleanup for formal ByVal parameters .


<s> void MipsPassConfig :: addPreEmitPass ( ) { MipsTargetMachine & TM = getMipsTargetMachine ( ) ; addPass ( createMipsDelaySlotFillerPass ( TM ) ) ; addPass ( createMipsHazardSchedule ( ) ) ; addPass ( createMipsLongBranchPass ( TM ) ) ; addPass ( createMipsConstantIslandPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> reg_class_t csky_secondary_reload ( bool in_p ATTRIBUTE_UNUSED , rtx x , reg_class_t rclass , machine_mode mode , secondary_reload_info * sri ATTRIBUTE_UNUSED ) { int regno = - 1 ; if ( GET_CODE ( x ) == SIGN_EXTEND ) { int off = 0 ; x = XEXP ( x , 0 ) ; if ( reg_renumber ) regno = true_regnum ( x ) ; else { while ( GET_CODE ( x ) == SUBREG ) { off += subreg_regno_offset ( REGNO ( SUBREG_REG ( x ) ) , GET_MODE ( SUBREG_REG ( x ) ) , SUBREG_BYTE ( x ) , GET_MODE ( x ) ) ; x = SUBREG_REG ( x ) ; } if ( GET_CODE ( x ) == REG ) regno = REGNO ( x ) + off ; } } else if ( GET_CODE ( x ) == REG || GET_CODE ( x ) == SUBREG ) regno = true_regnum ( x ) ; if ( rclass == HILO_REGS && ! CSKY_GENERAL_REGNO_P ( regno ) ) return GENERAL_REGS ; if ( rclass == V_REGS && ! CSKY_GENERAL_REGNO_P ( regno ) ) { if ( MEM_P ( x ) && ( mode == SFmode || mode == DFmode ) ) return NO_REGS ; else return GENERAL_REGS ; } return NO_REGS ; } </s>

Implement TARGET_SECONDARY_RELOAD . If copying a register of RCLASS from/to X requires an intermediate register , the hook should return the REGISTER_CLASS required for this intermediate register . If no intermediate register is required , it should return NO_REGS . If more than one intermediate register is required , describe the one that is closest in the copy chain to the reload register .


<s> static rtx get_branch_target ( rtx_insn * branch ) { if ( JUMP_P ( branch ) ) { rtx set , src ; if ( GET_CODE ( PATTERN ( branch ) ) == RETURN ) return gen_rtx_REG ( SImode , LINK_REGISTER_REGNUM ) ; if ( extract_asm_operands ( PATTERN ( branch ) ) != NULL ) return NULL ; set = single_set ( branch ) ; src = SET_SRC ( set ) ; if ( GET_CODE ( SET_DEST ( set ) ) != PC ) abort ( ) ; if ( GET_CODE ( src ) == IF_THEN_ELSE ) { rtx lab = 0 ; rtx note = find_reg_note ( branch , REG_BR_PROB , 0 ) ; if ( note ) { int prob = XINT ( note , 0 ) ; if ( prob > ( REG_BR_PROB_BASE * 6 / 10 ) && GET_CODE ( XEXP ( src , 1 ) ) != PC ) lab = XEXP ( src , 1 ) ; else if ( prob < ( REG_BR_PROB_BASE * 4 / 10 ) && GET_CODE ( XEXP ( src , 2 ) ) != PC ) lab = XEXP ( src , 2 ) ; } if ( lab ) { if ( GET_CODE ( lab ) == RETURN ) return gen_rtx_REG ( SImode , LINK_REGISTER_REGNUM ) ; return lab ; } return 0 ; } return src ; } else if ( CALL_P ( branch ) ) { rtx call ; if ( GET_CODE ( PATTERN ( branch ) ) != PARALLEL ) abort ( ) ; call = XVECEXP ( PATTERN ( branch ) , 0 , 0 ) ; if ( GET_CODE ( call ) == SET ) call = SET_SRC ( call ) ; if ( GET_CODE ( call ) != CALL ) abort ( ) ; return XEXP ( XEXP ( call , 0 ) , 0 ) ; } return 0 ; } </s>

Returns 0 if we do n't want a hint for this branch . Otherwise return the rtx for the branch target .