<s>
static
void
pru_dump_frame_layout
(
FILE
*
file
)
{
fprintf
(
file
,
"\t%s Current Frame Info\n"
,
ASM_COMMENT_START
)
;
fprintf
(
file
,
"\t%s total_size = %d\n"
,
ASM_COMMENT_START
,
cfun
->
machine
->
total_size
)
;
fprintf
(
file
,
"\t%s var_size = %d\n"
,
ASM_COMMENT_START
,
cfun
->
machine
->
var_size
)
;
fprintf
(
file
,
"\t%s out_args_size = %d\n"
,
ASM_COMMENT_START
,
cfun
->
machine
->
out_args_size
)
;
fprintf
(
file
,
"\t%s save_reg_size = %d\n"
,
ASM_COMMENT_START
,
cfun
->
machine
->
save_reg_size
)
;
fprintf
(
file
,
"\t%s initialized = %d\n"
,
ASM_COMMENT_START
,
cfun
->
machine
->
initialized
)
;
fprintf
(
file
,
"\t%s save_regs_offset = %d\n"
,
ASM_COMMENT_START
,
cfun
->
machine
->
save_regs_offset
)
;
fprintf
(
file
,
"\t%s is_leaf = %d\n"
,
ASM_COMMENT_START
,
crtl
->
is_leaf
)
;
fprintf
(
file
,
"\t%s frame_pointer_needed = %d\n"
,
ASM_COMMENT_START
,
frame_pointer_needed
)
;
fprintf
(
file
,
"\t%s pretend_args_size = %d\n"
,
ASM_COMMENT_START
,
crtl
->
args
.
pretend_args_size
)
;
}
</s>

pru
"\t%s Current Frame Info\n"
"\t%s total_size = %d\n"
"\t%s var_size = %d\n"
"\t%s out_args_size = %d\n"
"\t%s save_reg_size = %d\n"
"\t%s initialized = %d\n"
"\t%s save_regs_offset = %d\n"
"\t%s is_leaf = %d\n"
"\t%s frame_pointer_needed = %d\n"
"\t%s pretend_args_size = %d\n"


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const PPCFrameLowering * PPCFI = static_cast < const PPCFrameLowering * > ( MF . getTarget ( ) . getFrameLowering ( ) ) ; Reserved . set ( PPC :: R0 ) ; Reserved . set ( PPC :: R1 ) ; Reserved . set ( PPC :: LR ) ; Reserved . set ( PPC :: LR8 ) ; Reserved . set ( PPC :: RM ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: R2 ) ; Reserved . set ( PPC :: R13 ) ; } if ( Subtarget . isDarwinABI ( ) ) { Reserved . set ( PPC :: R2 ) ; } if ( Subtarget . isPPC64 ( ) ) { Reserved . set ( PPC :: R13 ) ; Reserved . set ( PPC :: R31 ) ; if ( ! requiresRegisterScavenging ( MF ) ) Reserved . set ( PPC :: R0 ) ; Reserved . set ( PPC :: X0 ) ; Reserved . set ( PPC :: X1 ) ; Reserved . set ( PPC :: X13 ) ; Reserved . set ( PPC :: X31 ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: X2 ) ; } if ( Subtarget . isDarwinABI ( ) ) { Reserved . set ( PPC :: X2 ) ; } } if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: R31 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> unsigned HOST_WIDE_INT s390_extract_part ( rtx op , machine_mode mode , int def ) { unsigned HOST_WIDE_INT value = 0 ; int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE ( mode ) ; int part_bits = GET_MODE_BITSIZE ( mode ) ; unsigned HOST_WIDE_INT part_mask = ( ( unsigned HOST_WIDE_INT ) 1 << part_bits ) - 1 ; int i ; for ( i = 0 ; i < max_parts ; i ++ ) { if ( i == 0 ) value = ( unsigned HOST_WIDE_INT ) INTVAL ( op ) ; else value >>= part_bits ; if ( ( value & part_mask ) != ( def & part_mask ) ) return value & part_mask ; } gcc_unreachable ( ) ; } </s>

Return the part of op which has a value different from def . The size of the part is determined by mode . Use this function only if you already know that op really contains such a part .


<s> bool shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const override { return true ; } </s>

Returns true if it is beneficial to convert a load of a constant to just the constant itself .


<s> std :: pair < unsigned , const TargetRegisterClass * > MandarinTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , & MD :: GenericRegsRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s>
bool
RV16KInstrInfo
::
reverseBranchCondition
(
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
using
std
::
swap
;
assert
(
(
Cond
.
size
(
)
==
3
)
&&
"Invalid branch condition!"
)
;
bool
Swap
=
false
;
RV16K
::
CondCode
CC
;
switch
(
Cond
[
2
]
.
getImm
(
)
)
{
default
:
llvm_unreachable
(
"Invalid cond code"
)
;
case
RV16K
::
COND_E
:
CC
=
RV16K
::
COND_NE
;
break
;
case
RV16K
::
COND_NE
:
CC
=
RV16K
::
COND_E
;
break
;
case
RV16K
::
COND_L
:
Swap
=
true
;
CC
=
RV16K
::
COND_LE
;
break
;
case
RV16K
::
COND_LE
:
Swap
=
true
;
CC
=
RV16K
::
COND_L
;
break
;
case
RV16K
::
COND_B
:
Swap
=
true
;
CC
=
RV16K
::
COND_BE
;
break
;
case
RV16K
::
COND_BE
:
Swap
=
true
;
CC
=
RV16K
::
COND_B
;
break
;
}
Cond
[
2
]
.
setImm
(
CC
)
;
if
(
Swap
)
swap
(
Cond
[
0
]
,
Cond
[
1
]
)
;
return
false
;
}
</s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> bool X86InstrInfo :: isUnpredicatedTerminator ( const MachineInstr * MI ) const { const TargetInstrDesc & TID = MI -> getDesc ( ) ; if ( ! TID . isTerminator ( ) ) return false ; if ( TID . isBranch ( ) && ! TID . isBarrier ( ) ) return true ; if ( ! TID . isPredicable ( ) ) return true ; return ! isPredicated ( MI ) ; } </s>

Returns true if the instruction is a terminator instruction that has not been predicated .


<s> bool HexagonTargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( Kind . isBSS ( ) || Kind . isDataNoRel ( ) || Kind . isCommon ( ) ) { Type * Ty = GV -> getType ( ) -> getElementType ( ) ; return IsInSmallSection ( GV -> getParent ( ) -> getDataLayout ( ) . getTypeAllocSize ( Ty ) ) ; } return false ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> static void push_regs ( HARD_REG_SET * mask , int interrupt_handler ) { int i = interrupt_handler ? LAST_BANKED_REG + 1 : 0 ; int skip_fpscr = 0 ; for ( ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { if ( i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD && hard_reg_set_intersect_p ( * mask , reg_class_contents [ DF_REGS ] ) ) { HARD_REG_SET unsaved ; push ( FPSCR_REG ) ; COMPL_HARD_REG_SET ( unsaved , * mask ) ; fpscr_set_from_mem ( NORMAL_MODE ( FP_MODE ) , unsaved ) ; skip_fpscr = 1 ; } if ( i != PR_REG && ( i != FPSCR_REG || ! skip_fpscr ) && TEST_HARD_REG_BIT ( * mask , i ) ) { if ( ! ( sh_cfun_resbank_handler_p ( ) && ( ( i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG ) || i == MACH_REG || i == MACL_REG || i == GBR_REG ) ) ) push ( i ) ; } } if ( interrupt_handler ) { bool use_movml = false ; if ( TARGET_SH2A ) { unsigned int count = 0 ; for ( i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) if ( TEST_HARD_REG_BIT ( * mask , i ) ) count ++ ; else break ; if ( count == LAST_BANKED_REG - FIRST_BANKED_REG + 1 ) use_movml = true ; } if ( sh_cfun_resbank_handler_p ( ) ) ; else if ( use_movml ) { rtx x , mem , reg , set ; rtx sp_reg = gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) ; emit_insn ( gen_blockage ( ) ) ; x = gen_movml_push_banked ( sp_reg ) ; x = frame_insn ( x ) ; for ( i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) { mem = gen_rtx_MEM ( SImode , plus_constant ( Pmode , sp_reg , i * 4 ) ) ; reg = gen_rtx_REG ( SImode , i ) ; add_reg_note ( x , REG_CFA_OFFSET , gen_rtx_SET ( SImode , mem , reg ) ) ; } set = gen_rtx_SET ( SImode , sp_reg , plus_constant ( Pmode , sp_reg , - 32 ) ) ; add_reg_note ( x , REG_CFA_ADJUST_CFA , set ) ; emit_insn ( gen_blockage ( ) ) ; } else for ( i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) if ( TEST_HARD_REG_BIT ( * mask , i ) ) push ( i ) ; } if ( TEST_HARD_REG_BIT ( * mask , PR_REG ) && ! sh_cfun_resbank_handler_p ( ) ) push ( PR_REG ) ; } </s>

Generate code to push the regs specified in the mask . remember that the mask is of the internal shape of the regs , not the external shape - so go through the renumber vector


<s> const MMIXSubtarget * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool X86TargetMachine :: addPreEmitPass ( PassManagerBase & PM ) { bool ShouldPrint = false ; if ( getOptLevel ( ) != CodeGenOpt :: None && Subtarget . hasXMMInt ( ) ) { PM . add ( createExecutionDependencyFixPass ( & X86 :: VR128RegClass ) ) ; ShouldPrint = true ; } if ( Subtarget . hasAVX ( ) && UseVZeroUpper ) { PM . add ( createX86IssueVZeroUpperPass ( ) ) ; ShouldPrint = true ; } return ShouldPrint ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static rtx bfin_function_arg ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int bytes = arg . promoted_size_in_bytes ( ) ; if ( arg . end_marker_p ( ) ) return GEN_INT ( cum -> call_cookie ) ; if ( bytes == - 1 ) return NULL_RTX ; if ( cum -> nregs ) return gen_rtx_REG ( arg . mode , * ( cum -> arg_regs ) ) ; return NULL_RTX ; } </s>

Define where to put the arguments to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) .


<s> bool rs6000_is_valid_and_mask ( rtx mask , machine_mode mode ) { int nb , ne ; if ( ! rs6000_is_valid_mask ( mask , & nb , & ne , mode ) ) return false ; if ( mode == DImode ) return ( ne == 0 || nb == 63 || ( nb < 32 && ne <= nb ) ) ; if ( mode == SImode ) return ( nb < 32 && ne < 32 ) ; return false ; } </s>

Return whether MASK ( a CONST_INT ) is a valid mask for any rlwinm , rldicl , or rldicr instruction , to implement an AND with it in mode MODE .


<s> static void emit_constant_insn ( rtx cond , rtx pattern ) { if ( cond ) pattern = gen_rtx_COND_EXEC ( VOIDmode , copy_rtx ( cond ) , pattern ) ; emit_insn ( pattern ) ; } </s>

Emit an instruction with the indicated PATTERN . If COND is non-NULL , conditionalize the execution of the instruction on COND being true .


<s> virtual const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> static void frv_fill_unused_units ( enum frv_insn_group group ) { unsigned int non_nops , nops , i ; struct frv_packet_group * packet_group ; packet_group = & frv_packet . groups [ group ] ; frv_sort_insn_group ( group ) ; i = nops = 0 ; for ( non_nops = 0 ; non_nops < packet_group -> num_insns ; non_nops ++ ) while ( packet_group -> sorted [ i ++ ] == packet_group -> nop ) nops ++ ; while ( nops -- > 0 ) frv_insert_nop_in_packet ( packet_group -> nop ) ; } </s>

See whether we need to add nops to group GROUP in order to make a valid packet .


<s> static bool riscv_cannot_force_const_mem ( enum machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { enum riscv_symbol_type type ; rtx base , offset ; if ( GET_CODE ( x ) == HIGH ) return true ; split_const ( x , & base , & offset ) ; if ( riscv_symbolic_constant_p ( base , & type ) ) { if ( SMALL_OPERAND ( INTVAL ( offset ) ) && riscv_symbol_insns ( type ) > 0 ) return true ; if ( flag_pic ) return true ; } if ( tls_referenced_p ( x ) ) return true ; return false ; } </s>


<s>
void
ARCFrameLowering
::
determineCalleeSaves
(
MachineFunction
&
MF
,
BitVector
&
SavedRegs
,
RegScavenger
*
RS
)
const
{
DEBUG
(
dbgs
(
)
<<
"Determine Callee Saves: "
<<
MF
.
getName
(
)
<<
"\n"
)
;
TargetFrameLowering
::
determineCalleeSaves
(
MF
,
SavedRegs
,
RS
)
;
SavedRegs
.
set
(
ARC
::
BLINK
)
;
}
</s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .

ARC
ARC
"Determine Callee Saves: "
"\n"
ARC::BLINK


<s> int symbol_mentioned_p ( rtx x ) { const char * fmt ; int i ; if ( SYMBOL_REF_P ( x ) ) return 1 ; if ( GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNSPEC_TLS ) return 0 ; fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( x , i ) - 1 ; j >= 0 ; j -- ) if ( symbol_mentioned_p ( XVECEXP ( x , i , j ) ) ) return 1 ; } else if ( fmt [ i ] == 'e' && symbol_mentioned_p ( XEXP ( x , i ) ) ) return 1 ; } return 0 ; } </s>

Return TRUE if X references a SYMBOL_REF .


<s> void arm_asm_declare_function_name ( FILE * file , const char * name , tree decl ) { size_t cmse_name_len ; char * cmse_name = 0 ; char cmse_prefix [ ] = "__acle_se_" ; if ( use_cmse && lookup_attribute ( "cmse_nonsecure_entry" , DECL_ATTRIBUTES ( decl ) ) ) { cmse_name_len = sizeof ( cmse_prefix ) + strlen ( name ) ; cmse_name = XALLOCAVEC ( char , cmse_name_len ) ; snprintf ( cmse_name , cmse_name_len , "%s%s" , cmse_prefix , name ) ; targetm . asm_out . globalize_label ( file , cmse_name ) ; ARM_DECLARE_FUNCTION_NAME ( file , cmse_name , decl ) ; ASM_OUTPUT_TYPE_DIRECTIVE ( file , cmse_name , "function" ) ; } ARM_DECLARE_FUNCTION_NAME ( file , name , decl ) ; ASM_OUTPUT_TYPE_DIRECTIVE ( file , name , "function" ) ; ASM_DECLARE_RESULT ( file , DECL_RESULT ( decl ) ) ; ASM_OUTPUT_LABEL ( file , name ) ; if ( cmse_name ) ASM_OUTPUT_LABEL ( file , cmse_name ) ; ARM_OUTPUT_FN_UNWIND ( file , TRUE ) ; } </s>

Output in FILE asm statements needed to declare the NAME of the function defined by its DECL node .


<s>
bool
SILoadStoreOptimizer
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
STM
=
&
MF
.
getSubtarget
<
SISubtarget
>
(
)
;
if
(
!
STM
->
loadStoreOptEnabled
(
)
)
return
false
;
TII
=
STM
->
getInstrInfo
(
)
;
TRI
=
&
TII
->
getRegisterInfo
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
AA
=
&
getAnalysis
<
AAResultsWrapperPass
>
(
)
.
getAAResults
(
)
;
assert
(
MRI
->
isSSA
(
)
&&
"Must be run on SSA"
)
;
DEBUG
(
dbgs
(
)
<<
"Running SILoadStoreOptimizer\n"
)
;
bool
Modified
=
false
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
CreatedX2
=
0
;
Modified
|=
optimizeBlock
(
MBB
)
;
if
(
CreatedX2
>=
1
)
Modified
|=
optimizeBlock
(
MBB
)
;
}
return
Modified
;
}
</s>

runOnMachineFunction - Emit the function body .

AMDGPU
SI
SI
"Must be run on SSA"
"Running SILoadStoreOptimizer\n"
0
1


<s> static void nds32_setup_incoming_varargs ( cumulative_args_t ca , machine_mode mode , tree type , int * pretend_args_size , int second_time ATTRIBUTE_UNUSED ) { unsigned int total_args_regs ; unsigned int num_of_used_regs ; unsigned int remaining_reg_count ; CUMULATIVE_ARGS * cum ; if ( TARGET_HARD_FLOAT ) return ; cum = get_cumulative_args ( ca ) ; total_args_regs = NDS32_MAX_GPR_REGS_FOR_ARGS + NDS32_GPR_ARG_FIRST_REGNUM ; num_of_used_regs = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG ( cum -> gpr_offset , mode , type ) + NDS32_NEED_N_REGS_FOR_ARG ( mode , type ) ; remaining_reg_count = total_args_regs - num_of_used_regs ; * pretend_args_size = remaining_reg_count * UNITS_PER_WORD ; return ; } </s>


<s> static void gen_safe_add ( rtx dest , rtx src , rtx val , bool is_frame_related ) { rtx insn ; if ( val == NULL_RTX || INTVAL ( val ) == 0 ) { gcc_assert ( dest != src ) ; insn = emit_move_insn ( dest , src ) ; } else if ( ok_for_max_constant ( INTVAL ( val ) ) ) insn = emit_insn ( gen_addsi3 ( dest , src , val ) ) ; else { val = gen_rtx_CONST ( SImode , gen_rtx_UNSPEC ( SImode , gen_rtvec ( 1 , val ) , UNSPEC_CONST ) ) ; insn = emit_insn ( gen_addsi3 ( dest , src , val ) ) ; if ( is_frame_related ) add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( dest , gen_rtx_PLUS ( SImode , src , val ) ) ) ; return ; } if ( is_frame_related ) RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Generate an ADD of SRC plus VAL into DEST . Handles the case where VAL is too big for max_constant_value . Sets FRAME_RELATED_P on the insn if IS_FRAME_RELATED is true .


<s> SMLoc getOffsetOfLoc ( ) const override { return OffsetOfLoc ; } </s>

getOffsetOfLoc - Get the location of the offset operator .


<s> static bool bfin_legitimate_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { rtx sym ; HOST_WIDE_INT offset ; if ( GET_CODE ( x ) != CONST ) return true ; x = XEXP ( x , 0 ) ; gcc_assert ( GET_CODE ( x ) == PLUS ) ; sym = XEXP ( x , 0 ) ; x = XEXP ( x , 1 ) ; if ( GET_CODE ( sym ) != SYMBOL_REF || GET_CODE ( x ) != CONST_INT ) return true ; offset = INTVAL ( x ) ; if ( SYMBOL_REF_DECL ( sym ) == 0 ) return true ; if ( offset < 0 || offset >= int_size_in_bytes ( TREE_TYPE ( SYMBOL_REF_DECL ( sym ) ) ) ) return false ; return true ; } </s>

Ensure that for any constant of the form symbol + offset , the offset remains within the object . Any other constants are ok . This ensures that flat binaries never have to deal with relocations crossing section boundaries .


<s> int arm_is_longcall_p ( rtx sym_ref , int call_cookie , int call_symbol ) { if ( ! call_symbol ) { if ( GET_CODE ( sym_ref ) != MEM ) return 0 ; sym_ref = XEXP ( sym_ref , 0 ) ; } if ( GET_CODE ( sym_ref ) != SYMBOL_REF ) return 0 ; if ( call_cookie & CALL_SHORT ) return 0 ; if ( TARGET_LONG_CALLS ) { if ( flag_function_sections || DECL_SECTION_NAME ( current_function_decl ) ) return 1 ; } if ( current_file_function_operand ( sym_ref ) ) return 0 ; return ( call_cookie & CALL_LONG ) || ENCODED_LONG_CALL_ATTR_P ( XSTR ( sym_ref , 0 ) ) || TARGET_LONG_CALLS ; } </s>

Return nonzero if a 32 bit `` long_call '' should be generated for this call . We generate a long_call if the function : a. has an __attribute__ ( ( long call ) ) or b. is within the scope of a # pragma long_calls or c. the -mlong-calls command line switch has been specified . and either : 1 . -ffunction-sections is in effect or 2. the current function has __attribute__ ( ( section ) ) or 3. the target function has __attribute__ ( ( section ) ) However we do not generate a long call if the function : d. has an __attribute__ ( ( short_call ) ) or e. is inside the scope of a # pragma no_long_calls or f. is defined within the current compilation unit . This function will be called by C fragments contained in the machine description file . SYM_REF and CALL_COOKIE correspond to the matched rtl operands . CALL_SYMBOL is used to distinguish between two different callers of the function . It is set to 1 in the `` call_symbol '' and `` call_symbol_value '' patterns and to 0 in the `` call '' and `` call_value '' patterns . This is because of the difference in the SYM_REFs passed by these patterns .


<s> static rtx nds32_legitimize_target ( enum insn_code icode , rtx target ) { enum machine_mode mode = insn_data [ icode ] . operand [ 0 ] . mode ; if ( ! target || GET_MODE ( target ) != mode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , mode ) ) return gen_reg_rtx ( mode ) ; else return target ; } </s>

Return a legitimate rtx for instruction ICODE 's return value . Use TARGET if it 's not null , has the right mode , and satisfies operand 0 's predicate .


<s> bool isReg ( ) const override { return Kind == k_Register ; } </s>


<s> MSP430Subtarget :: MSP430Subtarget ( const TargetMachine & TM , const Module & M , const std :: string & FS ) { std :: string CPU = "generic" ; ParseSubtargetFeatures ( FS , CPU ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s>
SDValue
RISCVTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
report_fatal_error
(
"unimplemented operand"
)
;
case
ISD
::
GlobalAddress
:
return
lowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
lowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
lowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
lowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
lowerSELECT
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
lowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
lowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
lowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
SHL_PARTS
:
return
lowerShiftLeftParts
(
Op
,
DAG
)
;
case
ISD
::
SRA_PARTS
:
return
lowerShiftRightParts
(
Op
,
DAG
,
true
)
;
case
ISD
::
SRL_PARTS
:
return
lowerShiftRightParts
(
Op
,
DAG
,
false
)
;
case
ISD
::
BITCAST
:
{
assert
(
Subtarget
.
is64Bit
(
)
&&
Subtarget
.
hasStdExtF
(
)
&&
"Unexpected custom legalisation"
)
;
SDLoc
DL
(
Op
)
;
SDValue
Op0
=
Op
.
getOperand
(
0
)
;
if
(
Op
.
getValueType
(
)
!=
MVT
::
f32
||
Op0
.
getValueType
(
)
!=
MVT
::
i32
)
return
SDValue
(
)
;
SDValue
NewOp0
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
DL
,
MVT
::
i64
,
Op0
)
;
SDValue
FPConv
=
DAG
.
getNode
(
RISCVISD
::
FMV_W_X_RV64
,
DL
,
MVT
::
f32
,
NewOp0
)
;
return
FPConv
;
}
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> static rtx m32c_function_value ( const_tree valtype , const_tree fn_decl_or_type ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { const machine_mode mode = TYPE_MODE ( valtype ) ; return m32c_libcall_value ( mode , NULL_RTX ) ; } </s>

Implements FUNCTION_VALUE . Functions and libcalls have the same conventions .


<s> void RISCVAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { return ; } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool mips_expand_ins_as_unaligned_store ( rtx dest , rtx src , HOST_WIDE_INT width , HOST_WIDE_INT bitpos ) { rtx left , right ; machine_mode mode ; if ( ! mips_get_unaligned_mem ( dest , width , bitpos , & left , & right ) ) return false ; mode = int_mode_for_size ( width , 0 ) . require ( ) ; src = gen_lowpart ( mode , src ) ; if ( mode == DImode ) { emit_insn ( gen_mov_sdl ( dest , src , left ) ) ; emit_insn ( gen_mov_sdr ( copy_rtx ( dest ) , copy_rtx ( src ) , right ) ) ; } else { emit_insn ( gen_mov_swl ( dest , src , left ) ) ; emit_insn ( gen_mov_swr ( copy_rtx ( dest ) , copy_rtx ( src ) , right ) ) ; } return true ; } </s>

Try to use left/right stores to expand an `` ins '' pattern . DEST , WIDTH , BITPOS and SRC are the operands passed to the expander ; the operation is the equivalent of : ( set ( zero_extract DEST WIDTH BITPOS ) SRC ) Return true on success .


";; loop %d start_label not before loop_end\n"

A callback for the hw-doloop pass . Called to optimize LOOP in a machine-specific fashion ; returns true if successful and false if the hwloop_fail function should be called .


<s> void HexagonPassConfig :: addPostRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableRDFOpt ) addPass ( createHexagonRDFOpt ( ) ) ; if ( ! DisableHexagonCFGOpt ) addPass ( createHexagonCFGOptimizer ( ) , false ) ; if ( ! DisableAModeOpt ) addPass ( createHexagonOptAddrMode ( ) , false ) ; } } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .

Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon


<s> virtual bool isConditionalBranch ( const MCInst & Inst ) const { if ( Inst . getOpcode ( ) == ARM :: Bcc && Inst . getOperand ( 1 ) . getImm ( ) == ARMCC :: AL ) return false ; return MCInstrAnalysis :: isConditionalBranch ( Inst ) ; } </s>

Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block .


<s> bool WebAssemblySubtarget :: enableAtomicExpand ( ) const { return hasAtomics ( ) ; } </s>

True if the subtarget should run the atomic expansion pass .


Emit target-specific code that performs a memcpy .


<s> bool PPCExpandAtomicPseudo :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; TII = static_cast < const PPCInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = & TII -> getRegisterInfo ( ) ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , MBBE = MBB . end ( ) ; MBBI != MBBE ; ) { MachineInstr & MI = * MBBI ; MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; Changed |= expandMI ( MBB , MI , NMBBI ) ; MBBI = NMBBI ; } } if ( Changed ) MF . RenumberBlocks ( ) ; return Changed ; } </s>


<s> void AVRInstrInfo :: insertIndirectBranch ( MachineBasicBlock & MBB , MachineBasicBlock & NewDestBB , MachineBasicBlock & RestoreBB , const DebugLoc & DL , int64_t BrOffset , RegScavenger * RS ) const { BuildMI ( & MBB , DL , get ( AVR :: JMPk ) ) . addMBB ( & NewDestBB ) ; return ; } </s>

Insert an unconditional indirect branch at the end of MBB to NewDestBB .


<s> const char * getName ( ) const { return ( Available . getID ( ) == TPCSchedStrategy :: TopQID ) ? "Top" : "Bot" ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> void ARMBaseRegisterInfo :: updateRegAllocHint ( unsigned Reg , unsigned NewReg , MachineFunction & MF ) const { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; std :: pair < unsigned , unsigned > Hint = MRI -> getRegAllocationHint ( Reg ) ; if ( ( Hint . first == ( unsigned ) ARMRI :: RegPairOdd || Hint . first == ( unsigned ) ARMRI :: RegPairEven ) && TargetRegisterInfo :: isVirtualRegister ( Hint . second ) ) { unsigned OtherReg = Hint . second ; Hint = MRI -> getRegAllocationHint ( OtherReg ) ; if ( Hint . second == Reg ) { MRI -> setRegAllocationHint ( OtherReg , Hint . first , NewReg ) ; if ( TargetRegisterInfo :: isVirtualRegister ( NewReg ) ) MRI -> setRegAllocationHint ( NewReg , Hint . first == ( unsigned ) ARMRI :: RegPairOdd ? ARMRI :: RegPairEven : ARMRI :: RegPairOdd , OtherReg ) ; } } } </s>

A callback to allow target a chance to update register allocation hints when a register is `` changed '' ( e.g .

ARM ARM ARMRI::RegPairOdd ARMRI::RegPairEven ARMRI::RegPairOdd ARMRI::RegPairEven ARMRI::RegPairOdd


<s> bool isMem ( ) const override { assert ( false ) ; return false ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < AssumptionCacheTracker > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; AU . addRequired < ScalarEvolution > ( ) ; AU . addRequired < TargetTransformInfoWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
SDValue
BPFTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
report_fatal_error
(
"Unsupported dynamic stack allocation"
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>


<s>
SDValue
AMDGPUTargetLowering
::
LowerCall
(
CallLoweringInfo
&
CLI
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SDValue
Callee
=
CLI
.
Callee
;
SelectionDAG
&
DAG
=
CLI
.
DAG
;
const
Function
&
Fn
=
*
DAG
.
getMachineFunction
(
)
.
getFunction
(
)
;
StringRef
FuncName
(
"<unknown>"
)
;
if
(
const
ExternalSymbolSDNode
*
G
=
dyn_cast
<
ExternalSymbolSDNode
>
(
Callee
)
)
FuncName
=
G
->
getSymbol
(
)
;
else
if
(
const
GlobalAddressSDNode
*
G
=
dyn_cast
<
GlobalAddressSDNode
>
(
Callee
)
)
FuncName
=
G
->
getGlobal
(
)
->
getName
(
)
;
DiagnosticInfoUnsupported
NoCalls
(
Fn
,
"call to function "
+
FuncName
)
;
DAG
.
getContext
(
)
->
diagnose
(
NoCalls
)
;
return
SDValue
(
)
;
}
</s>

This hook must be implemented to lower calls into the specified DAG .

AMDGPU
AMDGPU
"<unknown>"
"call to function "


<s>
unsigned
getReg
(
)
const
override
{
assert
(
Kind
==
Register
&&
"Invalid type access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s>
bool
MipsConstantIslands
::
isBBInRange
(
MachineInstr
*
MI
,
MachineBasicBlock
*
DestBB
,
unsigned
MaxDisp
)
{
unsigned
PCAdj
=
4
;
unsigned
BrOffset
=
getOffsetOf
(
MI
)
+
PCAdj
;
unsigned
DestOffset
=
BBInfo
[
DestBB
->
getNumber
(
)
]
.
Offset
;
DEBUG
(
dbgs
(
)
<<
"Branch of destination "
<<
printMBBReference
(
*
DestBB
)
<<
" from "
<<
printMBBReference
(
*
MI
->
getParent
(
)
)
<<
" max delta="
<<
MaxDisp
<<
" from "
<<
getOffsetOf
(
MI
)
<<
" to "
<<
DestOffset
<<
" offset "
<<
int
(
DestOffset
BrOffset
)
<<
"\t"
<<
*
MI
)
;
if
(
BrOffset
<=
DestOffset
)
{
if
(
DestOffset
BrOffset
<=
MaxDisp
)
return
true
;
}
else
{
if
(
BrOffset
DestOffset
<=
MaxDisp
)
return
true
;
}
return
false
;
}
</s>

isBBInRange - Returns true if the distance between specific MI and specific BB can fit in MI 's displacement field .

Mips
Mips
4
"Branch of destination "
" from "
" max delta="
" from "
" to "
" offset "
"\t"


<s> void HexagonPassConfig :: addPreEmitPass ( ) { bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) addPass ( createHexagonNewValueJump ( ) , false ) ; addPass ( createHexagonExpandPredSpillCode ( ) , false ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( createHexagonFixupHwLoops ( ) , false ) ; addPass ( createHexagonPacketizer ( ) , false ) ; } } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


"Frame offsets outside of the signed 16-bit range not supported"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> const TVMInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> bool BitSimplification :: processBlock ( MachineBasicBlock & B , const RegisterSet & AVs ) { if ( ! BT . reached ( & B ) ) return false ; bool Changed = false ; RegisterSet AVB = AVs ; RegisterSet Defs ; for ( auto I = B . begin ( ) , E = B . end ( ) ; I != E ; ++ I , AVB . insert ( Defs ) ) { MachineInstr * MI = & * I ; Defs . clear ( ) ; HBS :: getInstrDefs ( * MI , Defs ) ; unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == TargetOpcode :: COPY || Opc == TargetOpcode :: REG_SEQUENCE ) continue ; if ( MI -> mayStore ( ) ) { bool T = genStoreUpperHalf ( MI ) ; T = T || genStoreImmediate ( MI ) ; Changed |= T ; continue ; } if ( Defs . count ( ) != 1 ) continue ; const MachineOperand & Op0 = MI -> getOperand ( 0 ) ; if ( ! Op0 . isReg ( ) || ! Op0 . isDef ( ) ) continue ; BitTracker :: RegisterRef RD = Op0 ; if ( ! BT . has ( RD . Reg ) ) continue ; const TargetRegisterClass * FRC = HBS :: getFinalVRegClass ( RD , MRI ) ; const BitTracker :: RegisterCell & RC = BT . lookup ( RD . Reg ) ; if ( FRC -> getID ( ) == Hexagon :: DoubleRegsRegClassID ) { bool T = genPackhl ( MI , RD , RC ) ; T = T || simplifyExtractLow ( MI , RD , RC , AVB ) ; Changed |= T ; continue ; } if ( FRC -> getID ( ) == Hexagon :: IntRegsRegClassID ) { bool T = genBitSplit ( MI , RD , RC , AVB ) ; T = T || simplifyExtractLow ( MI , RD , RC , AVB ) ; T = T || genExtractHalf ( MI , RD , RC ) ; T = T || genCombineHalf ( MI , RD , RC ) ; T = T || genExtractLow ( MI , RD , RC ) ; Changed |= T ; continue ; } if ( FRC -> getID ( ) == Hexagon :: PredRegsRegClassID ) { bool T = simplifyTstbit ( MI , RD , RC ) ; Changed |= T ; continue ; } } return Changed ; } </s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .

Hexagon 1 0 Hexagon::DoubleRegsRegClassID Hexagon::IntRegsRegClassID Hexagon::PredRegsRegClassID


<s> void BTFTypeStruct :: completeType ( BTFDebug & BDebug ) { if ( IsCompleted ) return ; IsCompleted = true ; BTFType . NameOff = BDebug . addString ( STy -> getName ( ) ) ; const DINodeArray Elements = STy -> getElements ( ) ; for ( const auto * Element : Elements ) { struct BTF :: BTFMember BTFMember ; const auto * DDTy = cast < DIDerivedType > ( Element ) ; BTFMember . NameOff = BDebug . addString ( DDTy -> getName ( ) ) ; if ( HasBitField ) { uint8_t BitFieldSize = DDTy -> isBitField ( ) ? DDTy -> getSizeInBits ( ) : 0 ; BTFMember . Offset = BitFieldSize << 24 | DDTy -> getOffsetInBits ( ) ; } else { BTFMember . Offset = DDTy -> getOffsetInBits ( ) ; } BTFMember . Type = BDebug . getTypeId ( DDTy -> getBaseType ( ) ) ; Members . push_back ( BTFMember ) ; } } </s>

Complete BTF type generation after all related DebugInfo types have been visited so their BTF type id 's are available for cross referece .


<s> bool ARMBaseRegisterInfo :: canSimplifyCallFramePseudos ( const MachineFunction & MF ) const { return hasReservedCallFrame ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

canSimplifyCallFramePseudos - If there is a reserved call frame , the call frame pseudos can be simplified .


<s> BitVector AArch64RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; Reserved . set ( AArch64 :: XSP ) ; Reserved . set ( AArch64 :: WSP ) ; Reserved . set ( AArch64 :: XZR ) ; Reserved . set ( AArch64 :: WZR ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( AArch64 :: X29 ) ; Reserved . set ( AArch64 :: W29 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void setPersonality ( const MCSymbol * Per ) { HasPersonality = true ; } </s>


<s> XCoreSubtarget :: XCoreSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : XCoreGenSubtargetInfo ( TT , CPU , FS ) , InstrInfo ( ) , FrameLowering ( * this ) , TLInfo ( TM , * this ) , TSInfo ( ) { } </s>

This constructor initializes the data members to match that of the specified triple .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"ARM64 Promote Constant"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void OR1KFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; const OR1KRegisterInfo * TRI = static_cast < const OR1KRegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; bool IsPIC = MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; bool HasRA = MFI -> adjustsStack ( ) || IsPIC ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; int FPOffset = HasRA ? - 8 : - 4 ; int RAOffset = - 4 ; int BPOffset = FPOffset - 4 ; int StackSize = ( int ) MFI -> getStackSize ( ) ; if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII -> get ( OR1K :: ADDI ) , OR1K :: R1 ) . addReg ( OR1K :: R2 ) . addImm ( 0 ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( OR1K :: LWZ ) , OR1K :: R2 ) . addReg ( OR1K :: R1 ) . addImm ( FPOffset ) ; } else if ( isInt < 16 > ( StackSize ) ) { if ( StackSize ) { BuildMI ( MBB , MBBI , dl , TII -> get ( OR1K :: ADDI ) , OR1K :: R1 ) . addReg ( OR1K :: R1 ) . addImm ( StackSize ) ; } } else { unsigned ScratchReg = OR1K :: R13 ; BuildMI ( MBB , MBBI , dl , TII -> get ( OR1K :: MOVHI ) , ScratchReg ) . addImm ( ( uint32_t ) StackSize >> 16 ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( OR1K :: ORI ) , ScratchReg ) . addReg ( ScratchReg ) . addImm ( StackSize & 0xffffU ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( OR1K :: ADD ) , OR1K :: R1 ) . addReg ( OR1K :: R1 ) . addReg ( ScratchReg ) ; } if ( TRI -> hasBasePointer ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII -> get ( OR1K :: LWZ ) , TRI -> getBaseRegister ( ) ) . addReg ( OR1K :: R1 ) . addImm ( BPOffset ) ; } if ( HasRA ) { BuildMI ( MBB , MBBI , dl , TII -> get ( OR1K :: LWZ ) , OR1K :: R9 ) . addReg ( OR1K :: R1 ) . addImm ( RAOffset ) ; } } </s>


<s> static const struct mips_cpu_info * mips_default_arch ( void ) { unsigned int i ; for ( i = 0 ; i < ARRAY_SIZE ( mips_cpu_info_table ) ; i ++ ) if ( strcmp ( mips_cpu_info_table [ i ] . name , MIPS_CPU_STRING_DEFAULT ) == 0 ) return mips_cpu_info_table + i ; gcc_unreachable ( ) ; return mips_cpu_info_from_isa ( MIPS_ISA_DEFAULT ) ; return mips_cpu_info_from_opt ( MIPS_ARCH_OPTION_FROM_ABI ) ; } </s>

Return a default mips_cpu_info entry , given that no -march= option was explicitly specified .


<s> int xstormy16_initial_elimination_offset ( int from , int to ) { struct xstormy16_stack_layout layout ; int result ; layout = xstormy16_compute_stack_layout ( ) ; if ( from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) result = layout . sp_minus_fp - layout . locals_size ; else if ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) result = - layout . locals_size ; else if ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) result = - layout . fp_minus_ap ; else if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) result = - ( layout . sp_minus_fp + layout . fp_minus_ap ) ; else gcc_unreachable ( ) ; return result ; } </s>

Determine how all the special registers get eliminated .


<s> static bool sh_legitimate_address_p ( machine_mode mode , rtx x , bool strict ) { if ( ! ALLOW_INDEXED_ADDRESS && GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , 0 ) ) && REG_P ( XEXP ( x , 1 ) ) ) return false ; if ( REG_P ( x ) && REGNO ( x ) == GBR_REG ) return true ; if ( MAYBE_BASE_REGISTER_RTX_P ( x , strict ) ) return true ; else if ( ( GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == PRE_DEC ) && ! TARGET_SHMEDIA && MAYBE_BASE_REGISTER_RTX_P ( XEXP ( x , 0 ) , strict ) ) return true ; else if ( GET_CODE ( x ) == PLUS ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; if ( REG_P ( xop0 ) && REGNO ( xop0 ) == GBR_REG ) return gbr_displacement ( xop1 , mode ) ; if ( GET_MODE_SIZE ( mode ) <= 8 && MAYBE_BASE_REGISTER_RTX_P ( xop0 , strict ) && sh_legitimate_index_p ( mode , xop1 , TARGET_SH2A , false ) ) return true ; if ( ( ALLOW_INDEXED_ADDRESS || GET_MODE ( x ) == DImode || ( ( xop0 == stack_pointer_rtx || xop0 == hard_frame_pointer_rtx ) && REG_P ( xop1 ) && REGNO ( xop1 ) == R0_REG ) || ( ( xop1 == stack_pointer_rtx || xop1 == hard_frame_pointer_rtx ) && REG_P ( xop0 ) && REGNO ( xop0 ) == R0_REG ) ) && ( ( ! TARGET_SHMEDIA && GET_MODE_SIZE ( mode ) <= 4 ) || ( TARGET_SHMEDIA && GET_MODE_SIZE ( mode ) <= 8 ) || ( ( TARGET_SH4 || TARGET_SH2A_DOUBLE ) && TARGET_FMOVD && mode == DFmode ) ) ) { if ( MAYBE_BASE_REGISTER_RTX_P ( xop1 , strict ) && MAYBE_INDEX_REGISTER_RTX_P ( xop0 , strict ) ) return true ; if ( MAYBE_INDEX_REGISTER_RTX_P ( xop1 , strict ) && MAYBE_BASE_REGISTER_RTX_P ( xop0 , strict ) ) return true ; } } return false ; } </s>

Recognize an RTL expression that is a valid memory address for an instruction . The MODE argument is the machine mode for the MEM expression that wants to use this address . Allow REG REG+disp REG+r0 REG++ -- REG GBR GBR+disp


"8-byte alignment required for for all register save slots"

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> static void riscv_block_move_straight ( rtx dest , rtx src , HOST_WIDE_INT length ) { HOST_WIDE_INT offset , delta ; unsigned HOST_WIDE_INT bits ; int i ; enum machine_mode mode ; rtx * regs ; bits = MAX ( BITS_PER_UNIT , MIN ( BITS_PER_WORD , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) ) ) ; mode = mode_for_size ( bits , MODE_INT , 0 ) . require ( ) ; delta = bits / BITS_PER_UNIT ; regs = XALLOCAVEC ( rtx , length / delta ) ; for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) { regs [ i ] = gen_reg_rtx ( mode ) ; riscv_emit_move ( regs [ i ] , adjust_address ( src , mode , offset ) ) ; } for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) riscv_emit_move ( adjust_address ( dest , mode , offset ) , regs [ i ] ) ; if ( offset < length ) { src = adjust_address ( src , BLKmode , offset ) ; dest = adjust_address ( dest , BLKmode , offset ) ; move_by_pieces ( dest , src , length - offset , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) , 0 ) ; } } </s>

Emit straight-line code to move LENGTH bytes from SRC to DEST . Assume that the areas do not overlap .


<s> static tree aarch64_comparison_type ( stmt_vec_info stmt_info ) { if ( auto * assign = dyn_cast < gassign * > ( stmt_info -> stmt ) ) if ( TREE_CODE_CLASS ( gimple_assign_rhs_code ( assign ) ) == tcc_comparison ) return TREE_TYPE ( gimple_assign_rhs1 ( assign ) ) ; return aarch64_embedded_comparison_type ( stmt_info ) ; } </s>

If STMT_INFO is a comparison or contains an embedded comparison , return the scalar type of the values being compared . Return null otherwise .


<s> bool X86FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || TRI -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MFI -> hasOpaqueSPAdjustment ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) || MMI . hasEHFunclets ( ) || MMI . callsEHReturn ( ) || MFI -> hasStackMap ( ) || MFI -> hasPatchPoint ( ) || MFI -> hasCopyImplyingStackAdjustment ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool SITargetLowering :: shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const { const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; return TII -> isInlineConstant ( Imm ) ; } </s>

Returns true if it is beneficial to convert a load of a constant to just the constant itself .


<s> static rtx ix86_delegitimize_address ( rtx orig_x ) { rtx x = orig_x , y ; if ( GET_CODE ( x ) == MEM ) x = XEXP ( x , 0 ) ; if ( TARGET_64BIT ) { if ( GET_CODE ( x ) != CONST || GET_CODE ( XEXP ( x , 0 ) ) != UNSPEC || XINT ( XEXP ( x , 0 ) , 1 ) != UNSPEC_GOTPCREL || GET_CODE ( orig_x ) != MEM ) return orig_x ; return XVECEXP ( XEXP ( x , 0 ) , 0 , 0 ) ; } if ( GET_CODE ( x ) != PLUS || GET_CODE ( XEXP ( x , 1 ) ) != CONST ) return orig_x ; if ( GET_CODE ( XEXP ( x , 0 ) ) == REG && REGNO ( XEXP ( x , 0 ) ) == PIC_OFFSET_TABLE_REGNUM ) y = NULL ; else if ( GET_CODE ( XEXP ( x , 0 ) ) == PLUS ) { y = XEXP ( x , 0 ) ; if ( GET_CODE ( XEXP ( y , 0 ) ) == REG && REGNO ( XEXP ( y , 0 ) ) == PIC_OFFSET_TABLE_REGNUM ) y = XEXP ( y , 1 ) ; else if ( GET_CODE ( XEXP ( y , 1 ) ) == REG && REGNO ( XEXP ( y , 1 ) ) == PIC_OFFSET_TABLE_REGNUM ) y = XEXP ( y , 0 ) ; else return orig_x ; if ( GET_CODE ( y ) != REG && GET_CODE ( y ) != MULT && GET_CODE ( y ) != ASHIFT ) return orig_x ; } else return orig_x ; x = XEXP ( XEXP ( x , 1 ) , 0 ) ; if ( GET_CODE ( x ) == UNSPEC && ( ( XINT ( x , 1 ) == UNSPEC_GOT && GET_CODE ( orig_x ) == MEM ) || ( XINT ( x , 1 ) == UNSPEC_GOTOFF && GET_CODE ( orig_x ) != MEM ) ) ) { if ( y ) return gen_rtx_PLUS ( Pmode , y , XVECEXP ( x , 0 , 0 ) ) ; return XVECEXP ( x , 0 , 0 ) ; } if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 0 ) ) == UNSPEC && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT && ( ( XINT ( XEXP ( x , 0 ) , 1 ) == UNSPEC_GOT && GET_CODE ( orig_x ) == MEM ) || ( XINT ( XEXP ( x , 0 ) , 1 ) == UNSPEC_GOTOFF && GET_CODE ( orig_x ) != MEM ) ) ) { x = gen_rtx_PLUS ( VOIDmode , XVECEXP ( XEXP ( x , 0 ) , 0 , 0 ) , XEXP ( x , 1 ) ) ; if ( y ) return gen_rtx_PLUS ( Pmode , y , x ) ; return x ; } return orig_x ; } </s>

In the name of slightly smaller debug output , and to cater to general assembler lossage , recognize PIC+GOTOFF and turn it back into a direct symbol reference . On Darwin , this is necessary to avoid a crash , because Darwin has a different PIC label for each routine but the DWARF debugging information is not associated with any particular routine , so it 's necessary to remove references to the PIC label from RTL stored by the DWARF output code .


<s> bool X86RegisterInfo :: isArgumentRegister ( const MachineFunction & MF , MCRegister Reg ) const { const X86Subtarget & ST = MF . getSubtarget < X86Subtarget > ( ) ; const TargetRegisterInfo & TRI = * ST . getRegisterInfo ( ) ; auto IsSubReg = [ & ] ( MCRegister RegA , MCRegister RegB ) { return TRI . isSuperOrSubRegisterEq ( RegA , RegB ) ; } ; if ( ! ST . is64Bit ( ) ) return llvm :: any_of ( SmallVector < MCRegister > { X86 :: EAX , X86 :: ECX , X86 :: EDX } , [ & ] ( MCRegister & RegA ) { return IsSubReg ( RegA , Reg ) ; } ) || ( ST . hasMMX ( ) && X86 :: VR64RegClass . contains ( Reg ) ) ; CallingConv :: ID CC = MF . getFunction ( ) . getCallingConv ( ) ; if ( CC == CallingConv :: X86_64_SysV && IsSubReg ( X86 :: RAX , Reg ) ) return true ; if ( llvm :: any_of ( SmallVector < MCRegister > { X86 :: RDX , X86 :: RCX , X86 :: R8 , X86 :: R9 } , [ & ] ( MCRegister & RegA ) { return IsSubReg ( RegA , Reg ) ; } ) ) return true ; if ( CC != CallingConv :: Win64 && llvm :: any_of ( SmallVector < MCRegister > { X86 :: RDI , X86 :: RSI } , [ & ] ( MCRegister & RegA ) { return IsSubReg ( RegA , Reg ) ; } ) ) return true ; if ( ST . hasSSE1 ( ) && llvm :: any_of ( SmallVector < MCRegister > { X86 :: XMM0 , X86 :: XMM1 , X86 :: XMM2 , X86 :: XMM3 , X86 :: XMM4 , X86 :: XMM5 , X86 :: XMM6 , X86 :: XMM7 } , [ & ] ( MCRegister & RegA ) { return IsSubReg ( RegA , Reg ) ; } ) ) return true ; return X86GenRegisterInfo :: isArgumentRegister ( MF , Reg ) ; } </s>

isArgumentReg - Returns true if Reg can be used as an argument to a function .


<s> bool TPCInstrInfo :: isProfitableToHoist ( MachineInstr & MI ) const { if ( MI . getOpcode ( ) == TPC :: MOVvip || MI . getOpcode ( ) == TPC :: MOV_ld_vip ) return false ; return true ; } </s>

Return true if it is profitable to hoist instruction in the then/else to before if .


<s> void MipsSEFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; const MipsSEInstrInfo & TII = * static_cast < const MipsSEInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; const MipsRegisterInfo & RegInfo = * static_cast < const MipsRegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; unsigned SP = STI . isABI_N64 ( ) ? Mips :: SP_64 : Mips :: SP ; unsigned FP = STI . isABI_N64 ( ) ? Mips :: FP_64 : Mips :: FP ; unsigned ZERO = STI . isABI_N64 ( ) ? Mips :: ZERO_64 : Mips :: ZERO ; unsigned ADDu = STI . isABI_N64 ( ) ? Mips :: DADDu : Mips :: ADDu ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( ADDu ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( MipsFI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & Mips :: CPU64RegsRegClass : & Mips :: CPURegsRegClass ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = 0 ; J < 4 ; ++ J ) { TII . loadRegFromStackSlot ( MBB , I , ehDataReg ( J ) , MipsFI -> getEhDataRegFI ( J ) , RC , & RegInfo ) ; } } uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize , MBB , MBBI ) ; } </s>

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips::SP_64 Mips::SP Mips::FP_64 Mips::FP Mips::ZERO_64 Mips::ZERO Mips::DADDu Mips::ADDu 0 Mips Mips::CPU64RegsRegClass Mips::CPURegsRegClass 0 0 4 Mips


<s>
bool
AArch64AdvSIMDScalar
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
bool
Changed
=
false
;
DEBUG
(
dbgs
(
)
<<
"***** AArch64AdvSIMDScalar *****\n"
)
;
MRI
=
&
mf
.
getRegInfo
(
)
;
TII
=
mf
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
for
(
MachineFunction
::
iterator
I
=
mf
.
begin
(
)
,
E
=
mf
.
end
(
)
;
I
!=
E
;
++
I
)
if
(
processMachineBasicBlock
(
I
)
)
Changed
=
true
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static void frv_reorder_packet ( void ) { unsigned int cursor [ NUM_GROUPS ] ; rtx insns [ ARRAY_SIZE ( frv_unit_groups ) ] ; unsigned int unit , to , from ; enum frv_insn_group group ; struct frv_packet_group * packet_group ; for ( group = 0 ; group < NUM_GROUPS ; group ++ ) { cursor [ group ] = 0 ; frv_sort_insn_group ( group ) ; } to = 0 ; for ( unit = 0 ; unit < ARRAY_SIZE ( frv_unit_groups ) ; unit ++ ) { group = frv_unit_groups [ unit ] ; packet_group = & frv_packet . groups [ group ] ; if ( cursor [ group ] < packet_group -> num_insns ) { gcc_assert ( packet_group -> sorted [ cursor [ group ] ] != packet_group -> nop ) ; insns [ to ++ ] = packet_group -> sorted [ cursor [ group ] ++ ] ; } } gcc_assert ( to == frv_packet . num_insns ) ; CLEAR_PACKING_FLAG ( insns [ to - 1 ] ) ; for ( from = 0 ; from < to - 1 ; from ++ ) { remove_insn ( insns [ from ] ) ; add_insn_before ( insns [ from ] , insns [ to - 1 ] ) ; SET_PACKING_FLAG ( insns [ from ] ) ; } } </s>

Sort the current packet into assembly-language order . Set packing flags as appropriate .


"Only integer vectors are supported here"

Return a SCEV for the constant 0 of a specific type .


<s> int mips_can_use_return_insn ( void ) { tree return_type ; if ( ! reload_completed ) return 0 ; if ( regs_ever_live [ 31 ] || current_function_profile ) return 0 ; return_type = DECL_RESULT ( current_function_decl ) ; if ( TARGET_MIPS16 && mips16_hard_float && ! aggregate_value_p ( return_type , current_function_decl ) && GET_MODE_CLASS ( DECL_MODE ( return_type ) ) == MODE_FLOAT && GET_MODE_SIZE ( DECL_MODE ( return_type ) ) <= UNITS_PER_FPVALUE ) return 0 ; if ( cfun -> machine -> frame . initialized ) return cfun -> machine -> frame . total_size == 0 ; return compute_frame_size ( get_frame_size ( ) ) == 0 ; } </s>

Return nonzero if this function is known to have a null epilogue . This allows the optimizer to omit jumps to jumps if no stack was created .


<s> static rtx nds32_gen_dup_4_byte_to_word_value ( rtx value ) { rtx value4word = gen_reg_rtx ( SImode ) ; nds32_gen_dup_4_byte_to_word_value_aux ( value , value4word ) ; return value4word ; } </s>

Auxiliary function for expand setmem pattern .


<s> enum reg_class arm_regno_class ( int regno ) { if ( regno == PC_REGNUM ) return NO_REGS ; if ( IS_VPR_REGNUM ( regno ) ) return VPR_REG ; if ( IS_PAC_REGNUM ( regno ) ) return PAC_REG ; if ( TARGET_THUMB1 ) { if ( regno == STACK_POINTER_REGNUM ) return STACK_REG ; if ( regno == CC_REGNUM ) return CC_REG ; if ( regno < 8 ) return LO_REGS ; return HI_REGS ; } if ( TARGET_THUMB2 && regno < 8 ) return LO_REGS ; if ( regno <= LAST_ARM_REGNUM || regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return TARGET_THUMB2 ? HI_REGS : GENERAL_REGS ; if ( regno == CC_REGNUM || regno == VFPCC_REGNUM ) return TARGET_THUMB2 ? CC_REG : NO_REGS ; if ( IS_VFP_REGNUM ( regno ) ) { if ( regno <= D7_VFP_REGNUM ) return VFP_D0_D7_REGS ; else if ( regno <= LAST_LO_VFP_REGNUM ) return VFP_LO_REGS ; else return VFP_HI_REGS ; } if ( IS_IWMMXT_REGNUM ( regno ) ) return IWMMXT_REGS ; if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return IWMMXT_GR_REGS ; return NO_REGS ; } </s>

For efficiency and historical reasons LO_REGS , HI_REGS and CC_REGS are not used in arm mode .


<s> static rtx_insn * rs6000_md_asm_adjust ( vec < rtx > & , vec < rtx > & , vec < const char * > & , vec < rtx > & clobbers , HARD_REG_SET & clobbered_regs ) { clobbers . safe_push ( gen_rtx_REG ( SImode , CA_REGNO ) ) ; SET_HARD_REG_BIT ( clobbered_regs , CA_REGNO ) ; return NULL ; } </s>

Implement TARGET_MD_ASM_ADJUST . All asm statements are considered to clobber the XER [ CA ] bit because clobbering that bit without telling the compiler worked just fine with versions of GCC before GCC 5 , and breaking a lot of older code in ways that are hard to track down is not such a great idea .


<s> bool AArch64PassConfig :: addInstSelector ( ) { addPass ( createAArch64ISelDag ( getAArch64TargetMachine ( ) , getOptLevel ( ) ) ) ; if ( TM -> getSubtarget < AArch64Subtarget > ( ) . isTargetELF ( ) && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createAArch64CleanupLocalDynamicTLSPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> virtual void * getAdjustedAnalysisPointer ( const void * ID ) override { if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo * ) this ; return this ; } </s>

getAdjustedAnalysisPointer - This method is used when a pass implements an analysis interface through multiple inheritance .


<s> static rtx nds32_expand_binop_builtin ( enum insn_code icode , tree exp , rtx target , bool return_p ) { rtx pat ; rtx op0 = nds32_read_argument ( exp , 0 ) ; rtx op1 = nds32_read_argument ( exp , 1 ) ; int op0_num = return_p ? 1 : 0 ; int op1_num = return_p ? 2 : 1 ; if ( return_p ) target = nds32_legitimize_target ( icode , target ) ; op0 = nds32_legitimize_argument ( icode , op0_num , op0 ) ; op1 = nds32_legitimize_argument ( icode , op1_num , op1 ) ; if ( return_p ) pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; else pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return target ; } </s>

Expand builtins that take two operands .


"emitPrologue doesn't support framepointer-less functions"

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s>
bool
AMDGPUAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
setForcedEncodingSize
(
0
)
;
if
(
Name
.
endswith
(
"_e64"
)
)
setForcedEncodingSize
(
64
)
;
else
if
(
Name
.
endswith
(
"_e32"
)
)
setForcedEncodingSize
(
32
)
;
Operands
.
push_back
(
AMDGPUOperand
::
CreateToken
(
Name
,
NameLoc
)
)
;
while
(
!
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
{
AMDGPUAsmParser
::
OperandMatchResultTy
Res
=
parseOperand
(
Operands
,
Name
)
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
Parser
.
Lex
(
)
;
switch
(
Res
)
{
case
MatchOperand_Success
:
break
;
case
MatchOperand_ParseFail
:
return
Error
(
getLexer
(
)
.
getLoc
(
)
,
"failed parsing operand."
)
;
case
MatchOperand_NoMatch
:
return
Error
(
getLexer
(
)
.
getLoc
(
)
,
"not a valid operand."
)
;
}
}
AMDGPUAsmParser
::
OperandMatchResultTy
Res
;
while
(
(
Res
=
parseOperand
(
Operands
,
Name
)
)
!=
MatchOperand_NoMatch
)
{
if
(
Res
!=
MatchOperand_Success
)
return
Error
(
getLexer
(
)
.
getLoc
(
)
,
"failed parsing operand."
)
;
}
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .


<s> int first_fp_reg_to_save ( ) { int first_reg ; for ( first_reg = 14 + 32 ; first_reg <= 63 ; first_reg ++ ) if ( regs_ever_live [ first_reg ] ) break ; return first_reg ; } </s>


<s> static void do_load_for_compare_from_addr ( machine_mode mode , rtx dest , rtx addr , rtx orig_addr ) { rtx mem = gen_rtx_MEM ( mode , addr ) ; MEM_COPY_ATTRIBUTES ( mem , orig_addr ) ; set_mem_size ( mem , GET_MODE_SIZE ( mode ) ) ; do_load_for_compare ( dest , mem , mode ) ; return ; } </s>

Prepare address and then do a load . MODE is the mode to use for the load . DEST is the destination register for the data . ADDR is the address to be loaded . ORIG_ADDR is the original address expression .


<s> static tree make_attribute ( const char * name , const char * arg_name , tree chain ) { tree attr_name ; tree attr_arg_name ; tree attr_args ; tree attr ; attr_name = get_identifier ( name ) ; attr_arg_name = build_string ( strlen ( arg_name ) , arg_name ) ; attr_args = tree_cons ( NULL_TREE , attr_arg_name , NULL_TREE ) ; attr = tree_cons ( attr_name , attr_args , chain ) ; return attr ; } </s>

Makes a function attribute of the form NAME ( ARG_NAME ) and chains it to CHAIN .


<s> bool PPCTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( DisablePPCPreinc ) return false ; bool isLoad = true ; SDValue Ptr ; EVT VT ; unsigned Alignment ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; Alignment = LD -> getAlignment ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Alignment = ST -> getAlignment ( ) ; isLoad = false ; } else return false ; if ( VT . isVector ( ) ) return false ; if ( SelectAddressRegReg ( Ptr , Base , Offset , DAG ) ) { bool Swap = false ; if ( isa < FrameIndexSDNode > ( Base ) || isa < RegisterSDNode > ( Base ) ) Swap = true ; else if ( ! isLoad ) { SDValue Val = cast < StoreSDNode > ( N ) -> getValue ( ) ; if ( Val == Base || Base . getNode ( ) -> isPredecessorOf ( Val . getNode ( ) ) ) Swap = true ; } if ( Swap ) std :: swap ( Base , Offset ) ; AM = ISD :: PRE_INC ; return true ; } if ( VT != MVT :: i64 ) { if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , false ) ) return false ; } else { if ( Alignment < 4 ) return false ; if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , true ) ) return false ; } if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { if ( LD -> getValueType ( 0 ) == MVT :: i64 && LD -> getMemoryVT ( ) == MVT :: i32 && LD -> getExtensionType ( ) == ISD :: SEXTLOAD && isa < ConstantSDNode > ( Offset ) ) return false ; } AM = ISD :: PRE_INC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .


<s>
int
AArch64TTIImpl
::
getMinMaxReductionCost
(
VectorType
*
Ty
,
VectorType
*
CondTy
,
bool
IsPairwise
,
bool
IsUnsigned
,
TTI
::
TargetCostKind
CostKind
)
{
if
(
!
isa
<
ScalableVectorType
>
(
Ty
)
)
return
BaseT
::
getMinMaxReductionCost
(
Ty
,
CondTy
,
IsPairwise
,
IsUnsigned
,
CostKind
)
;
assert
(
(
isa
<
ScalableVectorType
>
(
Ty
)
&&
isa
<
ScalableVectorType
>
(
CondTy
)
)
&&
"Both vector needs to be scalable"
)
;
std
::
pair
<
int
,
MVT
>
LT
=
TLI
->
getTypeLegalizationCost
(
DL
,
Ty
)
;
int
LegalizationCost
=
0
;
if
(
LT
.
first
>
1
)
{
Type
*
LegalVTy
=
EVT
(
LT
.
second
)
.
getTypeForEVT
(
Ty
->
getContext
(
)
)
;
unsigned
CmpOpcode
=
Ty
->
isFPOrFPVectorTy
(
)
Instruction
::
FCmp
:
Instruction
::
ICmp
;
LegalizationCost
=
getCmpSelInstrCost
(
CmpOpcode
,
LegalVTy
,
LegalVTy
,
CmpInst
::
BAD_ICMP_PREDICATE
,
CostKind
)
+
getCmpSelInstrCost
(
Instruction
::
Select
,
LegalVTy
,
LegalVTy
,
CmpInst
::
BAD_ICMP_PREDICATE
,
CostKind
)
;
LegalizationCost
*=
LT
.
first
1
;
}
return
LegalizationCost
+
2
;
}
</s>

Try to calculate op costs for min/max reduction operations .


<s> const MCPhysReg * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const ARMSubtarget & STI = MF -> getSubtarget < ARMSubtarget > ( ) ; const MCPhysReg * RegList = STI . isTargetDarwin ( ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ; const Function * F = MF -> getFunction ( ) ; if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F -> hasFnAttribute ( "interrupt" ) ) { if ( STI . isMClass ( ) ) { return CSR_AAPCS_SaveList ; } else if ( F -> getFnAttribute ( "interrupt" ) . getValueAsString ( ) == "FIQ" ) { return CSR_FIQ_SaveList ; } else { return CSR_GenericInt_SaveList ; } } return RegList ; } </s>

ARM ARM ARM ARM "interrupt" "interrupt" "FIQ"


<s> static inline tree def_builtin ( HOST_WIDE_INT mask , HOST_WIDE_INT mask2 , const char * name , enum ix86_builtin_func_type tcode , enum ix86_builtins code ) { tree decl = NULL_TREE ; if ( ! ( mask & OPTION_MASK_ISA_64BIT ) || TARGET_64BIT ) { ix86_builtins_isa [ ( int ) code ] . isa = mask ; ix86_builtins_isa [ ( int ) code ] . isa2 = mask2 ; mask &= ~ OPTION_MASK_ISA_64BIT ; if ( ( mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512VL ) && mask != OPTION_MASK_ISA_AVX512VL ) mask &= ~ OPTION_MASK_ISA_AVX512VL ; if ( ( mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512BW ) && mask != OPTION_MASK_ISA_AVX512BW ) mask &= ~ OPTION_MASK_ISA_AVX512BW ; if ( ( ( mask2 == 0 || ( mask2 & ix86_isa_flags2 ) != 0 ) && ( mask == 0 || ( mask & ix86_isa_flags ) != 0 ) ) || ( lang_hooks . builtin_function == lang_hooks . builtin_function_ext_scope ) ) { tree type = ix86_get_builtin_func_type ( tcode ) ; decl = add_builtin_function ( name , type , code , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ ( int ) code ] = decl ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = false ; } else { deferred_isa_values |= mask ; deferred_isa_values2 |= mask2 ; ix86_builtins [ ( int ) code ] = NULL_TREE ; ix86_builtins_isa [ ( int ) code ] . tcode = tcode ; ix86_builtins_isa [ ( int ) code ] . name = name ; ix86_builtins_isa [ ( int ) code ] . const_p = false ; ix86_builtins_isa [ ( int ) code ] . pure_p = false ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = true ; } } return decl ; } </s>

Add a SPARC builtin function with NAME , ICODE , CODE and TYPE . Return the function decl or NULL_TREE if the builtin was not added .


"getJumpTargetOpValue expects only expressions or an immediate"

getJumpTargetOpValue - Return binary encoding of the jump target operand .


<s> const uint32_t * LoongArchRegisterInfo :: getNoPreservedMask ( ) const { return CSR_NoRegs_RegMask ; } </s>

Return a register mask that clobbers everything .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> unsigned SNESInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : { const MCInstrDesc & Desc = get ( Opcode ) ; return Desc . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return 0 ; case TargetOpcode :: INLINEASM : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const SNESTargetMachine & TM = static_cast < const SNESTargetMachine & > ( MF . getTarget ( ) ) ; const SNESSubtarget & STI = MF . getSubtarget < SNESSubtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; return TII . getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s>
SDValue
PTXTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unimplemented operand"
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

PTX
PTX
"Unimplemented operand"
ISD::SETCC
ISD::GlobalAddress


<s> const M68kRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void HexagonPassConfig :: addPreSched2 ( ) { addPass ( createHexagonCopyToCombine ( ) , false ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & IfConverterID , false ) ; addPass ( createHexagonSplitConst32AndConst64 ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> BaseType :: const_iterator end ( ) const { return List . end ( ) ; } </s>

Get a const_iterator to the end of the symbol table .


<s> int symbolic_reference_mentioned_p ( rtx op ) { const char * fmt ; int i ; if ( GET_CODE ( op ) == SYMBOL_REF || GET_CODE ( op ) == LABEL_REF ) return 1 ; fmt = GET_RTX_FORMAT ( GET_CODE ( op ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( op ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( op , i ) - 1 ; j >= 0 ; j -- ) if ( symbolic_reference_mentioned_p ( XVECEXP ( op , i , j ) ) ) return 1 ; } else if ( fmt [ i ] == 'e' && symbolic_reference_mentioned_p ( XEXP ( op , i ) ) ) return 1 ; } return 0 ; } </s>

Return true if OP contains a symbol reference


<s> const LC2200Subtarget * getSubtargetImpl ( const Function & ) const override { return & DefaultSubtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
bool
HexagonExpandCondsets
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
*
MF
.
getFunction
(
)
)
)
return
false
;
HII
=
static_cast
<
const
HexagonInstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
LIS
=
&
getAnalysis
<
LiveIntervals
>
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
DEBUG
(
LIS
->
print
(
dbgs
(
)
<<
"Before expand-condsets\n"
,
MF
.
getFunction
(
)
->
getParent
(
)
)
)
;
bool
Changed
=
false
;
std
::
set
<
unsigned
>
CoalUpd
,
PredUpd
;
SmallVector
<
MachineInstr
*
,
16
>
Condsets
;
for
(
auto
&
B
:
MF
)
for
(
auto
&
I
:
B
)
if
(
isCondset
(
I
)
)
Condsets
.
push_back
(
&
I
)
;
Changed
|=
coalesceSegments
(
Condsets
,
CoalUpd
)
;
std
::
set
<
unsigned
>
KillUpd
;
for
(
MachineInstr
*
MI
:
Condsets
)
for
(
MachineOperand
&
Op
:
MI
->
operands
(
)
)
if
(
Op
.
isReg
(
)
&&
Op
.
isUse
(
)
)
if
(
!
CoalUpd
.
count
(
Op
.
getReg
(
)
)
)
KillUpd
.
insert
(
Op
.
getReg
(
)
)
;
updateLiveness
(
KillUpd
,
false
,
true
,
false
)
;
DEBUG
(
LIS
->
print
(
dbgs
(
)
<<
"After coalescing\n"
,
MF
.
getFunction
(
)
->
getParent
(
)
)
)
;
for
(
MachineInstr
*
MI
:
Condsets
)
Changed
|=
split
(
*
MI
,
PredUpd
)
;
Condsets
.
clear
(
)
;
DEBUG
(
LIS
->
print
(
dbgs
(
)
<<
"After splitting\n"
,
MF
.
getFunction
(
)
->
getParent
(
)
)
)
;
for
(
auto
&
B
:
MF
)
Changed
|=
predicateInBlock
(
B
,
PredUpd
)
;
DEBUG
(
LIS
->
print
(
dbgs
(
)
<<
"After predicating\n"
,
MF
.
getFunction
(
)
->
getParent
(
)
)
)
;
PredUpd
.
insert
(
CoalUpd
.
begin
(
)
,
CoalUpd
.
end
(
)
)
;
updateLiveness
(
PredUpd
,
true
,
true
,
true
)
;
DEBUG
(
{
if
(
Changed
)
LIS
->
print
(
dbgs
(
)
<<
"After expand-condsets\n"
,
MF
.
getFunction
(
)
->
getParent
(
)
)
;
}
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

Hexagon
Hexagon
Hexagon
"Before expand-condsets\n"
16
"After coalescing\n"
"After splitting\n"
"After predicating\n"
"After expand-condsets\n"


<s> int big_const_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { if ( GET_CODE ( op ) == CONST_INT && CONST_OK_FOR_LETTER_P ( INTVAL ( op ) , 'M' ) ) return 1 ; return 0 ; } </s>

Return truth value of whether OP is a constant that requires two loads to put in a register .


<s> int MMIXFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; int MinCSFI = 0 ; int MaxCSFI = - 1 ; int Offset = MFI . getObjectOffset ( FI ) - getOffsetOfLocalArea ( ) + MFI . getOffsetAdjustment ( ) ; if ( CSI . size ( ) ) { MinCSFI = CSI [ 0 ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - 1 ] . getFrameIdx ( ) ; } FrameReg = RI -> getFrameRegister ( MF ) ; if ( FI >= MinCSFI && FI <= MaxCSFI ) { FrameReg = MMIX :: r254 ; Offset += MF . getFrameInfo ( ) . getStackSize ( ) ; } return Offset ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


"********** Memory Intrinsic Results **********\n"

"MemIntrinsicResults expects liveness tracking"


<s> const TargetRegisterClass * X86RegisterInfo :: getPointerRegClass ( ) const { const X86Subtarget * Subtarget = & TM . getSubtarget < X86Subtarget > ( ) ; if ( Subtarget -> is64Bit ( ) ) return & X86 :: GR64RegClass ; else return & X86 :: GR32RegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> bool AArch64TargetLowering :: isMulAddWithConstProfitable ( const SDValue & AddNode , const SDValue & ConstNode ) const { const EVT VT = AddNode . getValueType ( ) ; if ( VT . isVector ( ) || VT . getScalarSizeInBits ( ) > 64 ) return true ; const ConstantSDNode * C1Node = cast < ConstantSDNode > ( AddNode . getOperand ( 1 ) ) ; const ConstantSDNode * C2Node = cast < ConstantSDNode > ( ConstNode ) ; const int64_t C1 = C1Node -> getSExtValue ( ) ; const APInt C1C2 = C1Node -> getAPIntValue ( ) * C2Node -> getAPIntValue ( ) ; if ( ! isLegalAddImmediate ( C1 ) || isLegalAddImmediate ( C1C2 . getSExtValue ( ) ) ) return true ; SmallVector < AArch64_IMM :: ImmInsnModel , 4 > Insn ; AArch64_IMM :: expandMOVImm ( C1C2 . getZExtValue ( ) , VT . getSizeInBits ( ) , Insn ) ; if ( Insn . size ( ) > 1 ) return false ; return true ; } </s>

Return true if it may be profitable to transform ( mul ( add x , c1 ) , c2 ) - > ( add ( mul x , c2 ) , c1 * c2 ) .


<s> bool X86TargetLowering :: isSafeMemOpType ( MVT VT ) const { if ( VT == MVT :: f32 ) return X86ScalarSSEf32 ; else if ( VT == MVT :: f64 ) return X86ScalarSSEf64 ; return true ; } </s>

Returns true if it 's safe to use load / store of the specified type to expand memcpy / memset inline .


<s> Bucket ( const SCEV * B , Instruction * I ) : BaseSCEV ( B ) , Elements ( 1 , BucketElement ( I ) ) { } </s>

The bucket assigned by balanced partitioning .


<s> bool AArch64TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { CCAssignFn * RetCC = CCAssignFnForReturn ( CallConv ) ; SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> const uint32_t * LEGRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { return CC_Save_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> ATTRIBUTE_UNUSED static section * x86_64_elf_select_section ( tree decl , int reloc , unsigned HOST_WIDE_INT align ) { if ( ix86_in_large_data_p ( decl ) ) { const char * sname = NULL ; unsigned int flags = SECTION_WRITE ; switch ( categorize_decl_for_section ( decl , reloc ) ) { case SECCAT_DATA : sname = ".ldata" ; break ; case SECCAT_DATA_REL : sname = ".ldata.rel" ; break ; case SECCAT_DATA_REL_LOCAL : sname = ".ldata.rel.local" ; break ; case SECCAT_DATA_REL_RO : sname = ".ldata.rel.ro" ; break ; case SECCAT_DATA_REL_RO_LOCAL : sname = ".ldata.rel.ro.local" ; break ; case SECCAT_BSS : sname = ".lbss" ; flags |= SECTION_BSS ; break ; case SECCAT_RODATA : case SECCAT_RODATA_MERGE_STR : case SECCAT_RODATA_MERGE_STR_INIT : case SECCAT_RODATA_MERGE_CONST : sname = ".lrodata" ; flags = 0 ; break ; case SECCAT_SRODATA : case SECCAT_SDATA : case SECCAT_SBSS : gcc_unreachable ( ) ; case SECCAT_TEXT : case SECCAT_TDATA : case SECCAT_TBSS : break ; } if ( sname ) { if ( ! DECL_P ( decl ) ) return get_section ( sname , flags , NULL ) ; return get_named_section ( decl , sname , reloc ) ; } } return default_elf_select_section ( decl , reloc , align ) ; } </s>

switch to the appropriate section for output of DECL . DECL is either a ` VAR_DECL ' node or a constant of some sort . RELOC indicates whether forming the initial value of DECL requires link-time relocations .


<s> bool RISCVRegisterInfo :: isAsmClobberable ( const MachineFunction & MF , MCRegister PhysReg ) const { return ! MF . getSubtarget < RISCVSubtarget > ( ) . isRegisterReservedByUser ( PhysReg ) ; } </s>

Returns false if we ca n't guarantee that Physreg , specified as an IR asm clobber constraint , will be preserved across the statement .


<s> int ARMTTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned Bits = Ty -> getPrimitiveSizeInBits ( ) ; if ( Bits == 0 || Bits > 64 ) return 4 ; int64_t SImmVal = Imm . getSExtValue ( ) ; uint64_t ZImmVal = Imm . getZExtValue ( ) ; if ( ! ST -> isThumb ( ) ) { if ( ( SImmVal >= 0 && SImmVal < 65536 ) || ( ARM_AM :: getSOImmVal ( ZImmVal ) != - 1 ) || ( ARM_AM :: getSOImmVal ( ~ ZImmVal ) != - 1 ) ) return 1 ; return ST -> hasV6T2Ops ( ) ? 2 : 3 ; } if ( ST -> isThumb2 ( ) ) { if ( ( SImmVal >= 0 && SImmVal < 65536 ) || ( ARM_AM :: getT2SOImmVal ( ZImmVal ) != - 1 ) || ( ARM_AM :: getT2SOImmVal ( ~ ZImmVal ) != - 1 ) ) return 1 ; return ST -> hasV6T2Ops ( ) ? 2 : 3 ; } if ( SImmVal >= 0 && SImmVal < 256 ) return 1 ; if ( ( ~ ZImmVal < 256 ) || ARM_AM :: isThumbImmShiftedVal ( ZImmVal ) ) return 2 ; return 3 ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> int bpf_core_get_sou_member_index ( ctf_container_ref ctfc , const tree node ) { if ( TREE_CODE ( node ) == FIELD_DECL ) { const tree container = DECL_CONTEXT ( node ) ; const char * name = IDENTIFIER_POINTER ( DECL_NAME ( node ) ) ; dw_die_ref die = lookup_type_die ( container ) ; if ( die == NULL ) return - 1 ; ctf_dtdef_ref dtd = ctf_dtd_lookup ( ctfc , die ) ; if ( dtd == NULL ) return - 1 ; unsigned int kind = CTF_V2_INFO_KIND ( dtd -> dtd_data . ctti_info ) ; if ( kind != CTF_K_STRUCT && kind != CTF_K_UNION ) return - 1 ; int i = 0 ; ctf_dmdef_t * dmd ; for ( dmd = dtd -> dtd_u . dtu_members ; dmd != NULL ; dmd = ( ctf_dmdef_t * ) ctf_dmd_list_next ( dmd ) ) { if ( get_btf_id ( dmd -> dmd_type ) > BTF_MAX_TYPE ) continue ; if ( strcmp ( dmd -> dmd_name , name ) == 0 ) return i ; i ++ ; } } return - 1 ; } </s>

Return the 0-based index of the field NODE in its containing struct or union type .


<s> MachineBasicBlock :: iterator AArch64InstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , const outliner :: Candidate & C ) const { if ( C . CallConstructionID == MachineOutlinerTailCall ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: TCRETURNdi ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) . addImm ( 0 ) ) ; return It ; } if ( C . CallConstructionID == MachineOutlinerNoLRSave || C . CallConstructionID == MachineOutlinerThunk ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: BL ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; return It ; } MachineBasicBlock :: iterator CallPt ; MachineInstr * STRXpre = BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: STRXpre ) ) . addReg ( AArch64 :: SP , RegState :: Define ) . addReg ( AArch64 :: LR ) . addReg ( AArch64 :: SP ) . addImm ( - 16 ) ; It = MBB . insert ( It , STRXpre ) ; It ++ ; It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: BL ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; CallPt = It ; It ++ ; MachineInstr * LDRXpost = BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: LDRXpost ) ) . addReg ( AArch64 :: SP , RegState :: Define ) . addReg ( AArch64 :: LR , RegState :: Define ) . addReg ( AArch64 :: SP ) . addImm ( 16 ) ; It = MBB . insert ( It , LDRXpost ) ; return CallPt ; } </s>

Insert a call to an outlined function into the program .


"Instr doesn't have FrameIndex operand!"

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s>
const
MCPhysReg
*
X86RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
const
X86Subtarget
&
Subtarget
=
MF
->
getSubtarget
<
X86Subtarget
>
(
)
;
bool
HasAVX
=
Subtarget
.
hasAVX
(
)
;
bool
HasAVX512
=
Subtarget
.
hasAVX512
(
)
;
bool
CallsEHReturn
=
MF
->
getMMI
(
)
.
callsEHReturn
(
)
;
assert
(
MF
&&
"MachineFunction required"
)
;
switch
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
)
{
case
CallingConv
::
GHC
:
case
CallingConv
::
HiPE
:
return
CSR_NoRegs_SaveList
;
case
CallingConv
::
AnyReg
:
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
return
CSR_64_AllRegs_SaveList
;
case
CallingConv
::
PreserveMost
:
return
CSR_64_RT_MostRegs_SaveList
;
case
CallingConv
::
PreserveAll
:
if
(
HasAVX
)
return
CSR_64_RT_AllRegs_AVX_SaveList
;
return
CSR_64_RT_AllRegs_SaveList
;
case
CallingConv
::
Intel_OCL_BI
:
{
if
(
HasAVX512
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX512
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX_SaveList
;
if
(
HasAVX
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX_SaveList
;
if
(
!
HasAVX
&&
!
IsWin64
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_SaveList
;
break
;
}
case
CallingConv
::
Cold
:
if
(
Is64Bit
)
return
CSR_64_MostRegs_SaveList
;
break
;
case
CallingConv
::
X86_64_Win64
:
return
CSR_Win64_SaveList
;
case
CallingConv
::
X86_64_SysV
:
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
default
:
break
;
}
if
(
Is64Bit
)
{
if
(
IsWin64
)
return
CSR_Win64_SaveList
;
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
}
if
(
CallsEHReturn
)
return
CSR_32EHRet_SaveList
;
return
CSR_32_SaveList
;
}
</s>


<s> static rtx_insn * aarch64_prev_real_insn ( rtx_insn * insn ) { if ( ! insn ) return NULL ; do { insn = prev_real_insn ( insn ) ; } while ( insn && recog_memoized ( insn ) < 0 ) ; return insn ; } </s>

Find the first rtx_insn before insn that will generate an assembly instruction .


"Check for a non-legal type in this operation\n"

LowerOperation - Provide custom lowering hooks for some operations .


<s> static bool m32r_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { return ( m32r_hard_regno_modes [ regno ] & m32r_mode_class [ mode ] ) != 0 ; } </s>


<s> static void ix86_vec_perm_index_canon ( struct expand_vec_perm_d * d ) { unsigned nelt = d -> nelt ; if ( d -> perm [ 0 ] < nelt ) return ; for ( unsigned i = 0 ; i != nelt ; i ++ ) d -> perm [ i ] = ( d -> perm [ i ] + nelt ) % ( 2 * nelt ) ; std :: swap ( d -> op0 , d -> op1 ) ; return ; } </s>

Canonicalize vec_perm index to make the first index always comes from the first vector .


<s> TargetPassConfig * LEGTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new LEGPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> void AGCInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { unsigned Opcode = MI -> getOpcode ( ) ; if ( MII . get ( Opcode ) . TSFlags & AGCII :: IsExtracode ) O << "\t" << "extend" << "\n" ; printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .

AGC AGC AGCII::IsExtracode "\t" "extend" "\n"


<s> static unsigned int mn10300_case_values_threshold ( void ) { return 6 ; } </s>

Dispatch tables on the mn10300 are extremely expensive in terms of code and readonly data size . So we crank up the case threshold value to encourage a series of if/else comparisons to implement many small switch statements . In theory , this value could be increased much more if we were solely optimizing for space , but we keep it `` reasonable '' to avoid serious code efficiency lossage .


"64-bit code requested on a subtarget that doesn't support it!"

"Segmented stacks are only implemented on ELF."

This constructor initializes the data members to match that of the specified triple .


<s> bool SIInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock & MBB = * MI -> getParent ( ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; switch ( MI -> getOpcode ( ) ) { default : return AMDGPUInstrInfo :: expandPostRAPseudo ( MI ) ; case AMDGPU :: SI_CONSTDATA_PTR : { unsigned Reg = MI -> getOperand ( 0 ) . getReg ( ) ; unsigned RegLo = RI . getSubReg ( Reg , AMDGPU :: sub0 ) ; unsigned RegHi = RI . getSubReg ( Reg , AMDGPU :: sub1 ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: S_GETPC_B64 ) , Reg ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: S_ADD_I32 ) , RegLo ) . addReg ( RegLo ) . addTargetIndex ( AMDGPU :: TI_CONSTDATA_START ) . addReg ( AMDGPU :: SCC , RegState :: Define | RegState :: Implicit ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: S_ADDC_U32 ) , RegHi ) . addReg ( RegHi ) . addImm ( 0 ) . addReg ( AMDGPU :: SCC , RegState :: Define | RegState :: Implicit ) . addReg ( AMDGPU :: SCC , RegState :: Implicit ) ; MI -> eraseFromParent ( ) ; break ; } } return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s>
bool
ARCBranchFinalize
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
DEBUG
(
dbgs
(
)
<<
"Running ARC Branch Finalize on "
<<
MF
.
getFunction
(
)
->
getName
(
)
<<
"\n"
)
;
std
::
vector
<
MachineInstr
*
>
Branches
;
bool
Changed
=
false
;
unsigned
MaxSize
=
0
;
TII
=
MF
.
getSubtarget
<
ARCSubtarget
>
(
)
.
getInstrInfo
(
)
;
std
::
map
<
MachineBasicBlock
*
,
unsigned
>
BlockToPCMap
;
std
::
vector
<
std
::
pair
<
MachineInstr
*
,
unsigned
>>
BranchToPCList
;
unsigned
PC
=
0
;
for
(
auto
&
MBB
:
MF
)
{
BlockToPCMap
.
insert
(
std
::
make_pair
(
&
MBB
,
PC
)
)
;
for
(
auto
&
MI
:
MBB
)
{
unsigned
Size
=
TII
->
getInstSizeInBytes
(
MI
)
;
if
(
Size
>
8
||
Size
==
0
)
{
DEBUG
(
dbgs
(
)
<<
"Unknown (or size 0) size for: "
<<
MI
<<
"\n"
)
;
}
else
{
MaxSize
+=
Size
;
}
if
(
MI
.
isBranch
(
)
)
{
Branches
.
push_back
(
&
MI
)
;
BranchToPCList
.
emplace_back
(
&
MI
,
PC
)
;
}
PC
+=
Size
;
}
}
for
(
auto
P
:
BranchToPCList
)
{
if
(
isBRccPseudo
(
P
.
first
)
)
isInt
<
9
>
(
MaxSize
)
replaceWithBRcc
(
P
.
first
)
:
replaceWithCmpBcc
(
P
.
first
)
;
}
DEBUG
(
dbgs
(
)
<<
"Estimated function size for "
<<
MF
.
getFunction
(
)
->
getName
(
)
<<
": "
<<
MaxSize
<<
"\n"
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

ARC
ARC
"Running ARC Branch Finalize on "
"\n"
0
ARC
0
8
0
"Unknown (or size 0) size for: "
"\n"
9
"Estimated function size for "
": "
"\n"


<s> unsigned GCNHazardRecognizer :: PreEmitNoops ( MachineInstr * MI ) { int WaitStates = std :: max ( 0 , checkAnyInstHazards ( MI ) ) ; if ( SIInstrInfo :: isSMRD ( * MI ) ) return std :: max ( WaitStates , checkSMRDHazards ( MI ) ) ; if ( SIInstrInfo :: isVALU ( * MI ) ) { WaitStates = std :: max ( WaitStates , checkVALUHazards ( MI ) ) ; if ( SIInstrInfo :: isVMEM ( * MI ) ) WaitStates = std :: max ( WaitStates , checkVMEMHazards ( MI ) ) ; if ( SIInstrInfo :: isDPP ( * MI ) ) WaitStates = std :: max ( WaitStates , checkDPPHazards ( MI ) ) ; if ( isDivFMas ( MI -> getOpcode ( ) ) ) WaitStates = std :: max ( WaitStates , checkDivFMasHazards ( MI ) ) ; if ( isRWLane ( MI -> getOpcode ( ) ) ) WaitStates = std :: max ( WaitStates , checkRWLaneHazards ( MI ) ) ; if ( TII . isVINTRP ( * MI ) ) WaitStates = std :: max ( WaitStates , checkReadM0Hazards ( MI ) ) ; return WaitStates ; } if ( isSGetReg ( MI -> getOpcode ( ) ) ) return std :: max ( WaitStates , checkGetRegHazards ( MI ) ) ; if ( isSSetReg ( MI -> getOpcode ( ) ) ) return std :: max ( WaitStates , checkSetRegHazards ( MI ) ) ; if ( isRFE ( MI -> getOpcode ( ) ) ) return std :: max ( WaitStates , checkRFEHazards ( MI ) ) ; if ( TII . isVINTRP ( * MI ) || isSMovRel ( MI -> getOpcode ( ) ) ) return std :: max ( WaitStates , checkReadM0Hazards ( MI ) ) ; return WaitStates ; } </s>

PreEmitNoops - This callback is invoked prior to emitting an instruction .


Internal function to either define or undef the appropriate system macros .


<s> MVT SITargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( CC != CallingConv :: AMDGPU_KERNEL && VT . isVector ( ) ) { EVT ScalarVT = VT . getScalarType ( ) ; unsigned Size = ScalarVT . getSizeInBits ( ) ; if ( Size == 32 ) return ScalarVT . getSimpleVT ( ) ; if ( Size == 64 ) return MVT :: i32 ; if ( Size == 16 && Subtarget -> has16BitInsts ( ) && isPowerOf2_32 ( VT . getVectorNumElements ( ) ) ) return VT . isInteger ( ) ? MVT :: v2i16 : MVT :: v2f16 ; } return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


<s>
StringRef
getPassName
(
)
const
override
{
return
"MMIX Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static int pru_arg_partial_bytes ( cumulative_args_t , const function_arg_info & ) { return 0 ; } </s>

Implement TARGET_ARG_PARTIAL_BYTES . PRU never splits any arguments between registers and memory , so we can return 0 .


<s> unsigned MipsRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; bool IsN64 = Subtarget . isABI_N64 ( ) ; if ( Subtarget . inMips16Mode ( ) ) return TFI -> hasFP ( MF ) ? Mips :: S0 : Mips :: SP ; else return TFI -> hasFP ( MF ) ? ( IsN64 ? Mips :: FP_64 : Mips :: FP ) : ( IsN64 ? Mips :: SP_64 : Mips :: SP ) ; } </s>

Mips Mips Mips Mips::S0 Mips::SP Mips::FP_64 Mips::FP Mips::SP_64 Mips::SP


"%<-max-stackframe=%d%> is not usable, "

"unknown CRIS version specification in %<-march=%> or "

"unknown CRIS cpu version specification in %<-mtune=%>: %s"

"%<-fPIC%> and %<-fpic%> are not supported on this target"

The TARGET_OPTION_OVERRIDE worker . As is the norm , this also parses -mfoo=bar type parameters .


<s> static void expand_block_move_4 ( rtx dst , rtx dst_reg , rtx src , rtx src_reg , rtx bytes_rtx ) { const rtx sym = gen_rtx_SYMBOL_REF ( Pmode , "__long_int_memcpy" ) ; unsigned HOST_WIDE_INT bytes = UINTVAL ( bytes_rtx ) ; unsigned int rem = bytes % 4 ; if ( TARGET_BMI ) { unsigned int i ; rtx insn ; emit_move_insn ( regno_reg_rtx [ 1 ] , dst_reg ) ; emit_move_insn ( regno_reg_rtx [ 2 ] , src_reg ) ; emit_move_insn ( regno_reg_rtx [ 3 ] , bytes_rtx ) ; insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( 8 ) ) ; XVECEXP ( insn , 0 , 0 ) = gen_rtx_SET ( VOIDmode , replace_equiv_address_nv ( dst , regno_reg_rtx [ 1 ] ) , replace_equiv_address_nv ( src , regno_reg_rtx [ 2 ] ) ) ; XVECEXP ( insn , 0 , 1 ) = gen_rtx_USE ( VOIDmode , regno_reg_rtx [ 3 ] ) ; for ( i = 1 ; i <= 6 ; i ++ ) XVECEXP ( insn , 0 , 1 + i ) = gen_rtx_CLOBBER ( VOIDmode , regno_reg_rtx [ i ] ) ; emit_insn ( insn ) ; } else emit_library_call ( sym , LCT_NORMAL , VOIDmode , 3 , dst_reg , Pmode , src_reg , Pmode , convert_to_mode ( TYPE_MODE ( sizetype ) , GEN_INT ( bytes >> 2 ) , TYPE_UNSIGNED ( sizetype ) ) , TYPE_MODE ( sizetype ) ) ; if ( rem == 0 ) return ; dst = replace_equiv_address_nv ( dst , dst_reg ) ; src = replace_equiv_address_nv ( src , src_reg ) ; bytes -= rem ; if ( rem > 1 ) { emit_move_insn ( adjust_address_nv ( dst , HImode , bytes ) , adjust_address_nv ( src , HImode , bytes ) ) ; bytes += 2 ; rem -= 2 ; } if ( rem > 0 ) emit_move_insn ( adjust_address_nv ( dst , QImode , bytes ) , adjust_address_nv ( src , QImode , bytes ) ) ; } </s>

Generate a call to a library function to move BYTES_RTX bytes from SRC with address SRC_REG to DST with address DST_REG in 4-byte chunks .


<s> unsigned SIRegisterInfo :: findUnusedRegister ( const MachineRegisterInfo & MRI , const TargetRegisterClass * RC , const MachineFunction & MF ) const { for ( unsigned Reg : * RC ) if ( MRI . isAllocatable ( Reg ) && ! MRI . isPhysRegUsed ( Reg ) ) return Reg ; return AMDGPU :: NoRegister ; } </s>

Returns a lowest register that is not used at any point in the function .


<s> unsigned MipsRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; bool IsN64 = Subtarget . isABI_N64 ( ) ; return TFI -> hasFP ( MF ) ? ( IsN64 ? Mips :: FP_64 : Mips :: FP ) : ( IsN64 ? Mips :: SP_64 : Mips :: SP ) ; } </s>

Mips Mips Mips::FP_64 Mips::FP Mips::SP_64 Mips::SP


<s> int frv_adjust_field_align ( tree field , int computed ) { if ( field && DECL_BIT_FIELD ( field ) && ! DECL_ARTIFICIAL ( field ) ) { tree parent = DECL_CONTEXT ( field ) ; tree prev = NULL_TREE ; tree cur ; for ( cur = TYPE_FIELDS ( parent ) ; cur && cur != field ; cur = DECL_CHAIN ( cur ) ) { if ( TREE_CODE ( cur ) != FIELD_DECL ) continue ; prev = cur ; } gcc_assert ( cur ) ; if ( prev && ! DECL_PACKED ( field ) && ! integer_zerop ( DECL_SIZE ( field ) ) && DECL_BIT_FIELD_TYPE ( field ) != DECL_BIT_FIELD_TYPE ( prev ) ) { int prev_align = TYPE_ALIGN ( TREE_TYPE ( prev ) ) ; int cur_align = TYPE_ALIGN ( TREE_TYPE ( field ) ) ; computed = ( prev_align > cur_align ) ? prev_align : cur_align ; } } return computed ; } </s>

The definition type of the bit field data is either char , short , long or long long . The maximum bit size is the number of bits of its own type . The bit field data is assigned to a storage unit that has an adequate size for bit field data retention and is located at the smallest address . Consecutive bit field data are packed at consecutive bits having the same storage unit , with regard to the type , beginning with the MSB and continuing toward the LSB . If a field to be assigned lies over a bit field type boundary , its assignment is completed by aligning it with a boundary suitable for the type . When a bit field having a bit length of 0 is declared , it is forcibly assigned to the next storage unit . e.g ) struct { int a:2 ; int b:6 ; char c:4 ; int d:10 ; int :0 ; int f:2 ; } x ; +0 +1 +2 +3 & x 00000000 00000000 00000000 00000000 MLM -- -- L a b & x+4 00000000 00000000 00000000 00000000 M -- L c & x+8 00000000 00000000 00000000 00000000 M -- -- -- -- -- L d & x+12 00000000 00000000 00000000 00000000 ML f


"PTX does not support weak declarations"

Implement TARGET_ASM_ASSEMBLE_UNDEFINED_DECL . Write an extern declaration only for variable DECL with NAME to FILE .


<s> void CAHPPassConfig :: addPreEmitPass ( ) { addPass ( & BranchRelaxationPassID ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> unsigned getNumberOfRegisters ( unsigned ClassID ) const { bool Vector = ( ClassID == 1 ) ; if ( Vector ) { if ( ST -> hasVInstructions ( ) ) return 32 ; return 0 ; } return 31 ; } </s>


<s> bool SIInsertWaits :: runOnMachineFunction ( MachineFunction & MF ) { bool Changes = false ; TII = static_cast < const SIInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = static_cast < const SIRegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; MRI = & MF . getRegInfo ( ) ; WaitedOn = ZeroCounts ; LastIssued = ZeroCounts ; memset ( & UsedRegs , 0 , sizeof ( UsedRegs ) ) ; memset ( & DefinedRegs , 0 , sizeof ( DefinedRegs ) ) ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { Changes |= insertWait ( MBB , I , handleOperands ( * I ) ) ; pushInstruction ( * I ) ; } Changes |= insertWait ( MBB , MBB . getFirstTerminator ( ) , LastIssued ) ; } return Changes ; } </s>


<s> bool ARMCallLowering :: lowerCall ( MachineIRBuilder & MIRBuilder , CallingConv :: ID CallConv , const MachineOperand & Callee , const ArgInfo & OrigRet , ArrayRef < ArgInfo > OrigArgs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; const auto & TLI = * getTLI < ARMTargetLowering > ( ) ; const auto & DL = MF . getDataLayout ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( MF . getSubtarget < ARMSubtarget > ( ) . genLongCalls ( ) ) return false ; auto CallSeqStart = MIRBuilder . buildInstr ( ARM :: ADJCALLSTACKDOWN ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( ARM :: BLX ) . add ( Callee ) . addRegMask ( TRI -> getCallPreservedMask ( MF , CallConv ) ) ; SmallVector < ArgInfo , 8 > ArgInfos ; for ( auto Arg : OrigArgs ) { if ( ! isSupportedType ( DL , TLI , Arg . Ty ) ) return false ; if ( ! Arg . IsFixed ) return false ; splitToValueTypes ( Arg , ArgInfos , DL , MRI ) ; } auto ArgAssignFn = TLI . CCAssignFnForCall ( CallConv , false ) ; OutgoingValueHandler ArgHandler ( MIRBuilder , MRI , MIB , ArgAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( ! OrigRet . Ty -> isVoidTy ( ) ) { if ( ! isSupportedType ( DL , TLI , OrigRet . Ty ) ) return false ; ArgInfos . clear ( ) ; splitToValueTypes ( OrigRet , ArgInfos , DL , MRI ) ; auto RetAssignFn = TLI . CCAssignFnForReturn ( CallConv , false ) ; CallReturnHandler RetHandler ( MIRBuilder , MRI , MIB , RetAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , RetHandler ) ) return false ; } CallSeqStart . addImm ( ArgHandler . StackSize ) . add ( predOps ( ARMCC :: AL ) ) ; MIRBuilder . buildInstr ( ARM :: ADJCALLSTACKUP ) . addImm ( ArgHandler . StackSize ) . addImm ( 0 ) . add ( predOps ( ARMCC :: AL ) ) ; return true ; } </s>

This hook must be implemented to lower the given call instruction , including argument and return value marshalling .

ARM ARM ARM ARM ARM::ADJCALLSTACKDOWN ARM::BLX 8 ARMCC::AL ARM::ADJCALLSTACKUP 0 ARMCC::AL


<s> BitVector HSAILRegisterInfo :: getRegsAvailable ( const TargetRegisterClass * RC ) const { BitVector Mask ( getNumRegs ( ) ) ; for ( TargetRegisterClass :: iterator I = RC -> begin ( ) , E = RC -> end ( ) ; I != E ; ++ I ) Mask . set ( * I ) ; return Mask ; } </s>

Return all available registers in the register class in Mask .


<s> int byte_immediate_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { return ( GET_CODE ( op ) == CONST_INT && INTVAL ( op ) <= 0xff && INTVAL ( op ) >= 0 ) ; } </s>

Predicate function for immediate operand which fits to byte ( 8bit )


<s> static bool save_reg_p ( int reg ) { if ( reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ! TARGET_SINGLE_PIC_BASE ) { if ( crtl -> calls_eh_return && ( ( DEFAULT_ABI == ABI_V4 && flag_pic ) || ( DEFAULT_ABI == ABI_DARWIN && flag_pic ) || ( TARGET_TOC && TARGET_MINIMAL_TOC ) ) ) return true ; if ( TARGET_TOC && TARGET_MINIMAL_TOC && ! constant_pool_empty_p ( ) ) return true ; if ( DEFAULT_ABI == ABI_V4 && ( flag_pic == 1 || ( flag_pic && TARGET_SECURE_PLT ) ) && df_regs_ever_live_p ( RS6000_PIC_OFFSET_TABLE_REGNUM ) ) return true ; if ( DEFAULT_ABI == ABI_DARWIN && flag_pic && crtl -> uses_pic_offset_table ) return true ; } return ! call_used_regs [ reg ] && df_regs_ever_live_p ( reg ) ; } </s>

Determine whether the REG is really used .


<s> static rtx rs6000_internal_arg_pointer ( void ) { if ( flag_split_stack && ( lookup_attribute ( "no_split_stack" , DECL_ATTRIBUTES ( cfun -> decl ) ) == NULL ) ) { if ( cfun -> machine -> split_stack_arg_pointer == NULL_RTX ) { rtx pat ; cfun -> machine -> split_stack_arg_pointer = gen_reg_rtx ( Pmode ) ; REG_POINTER ( cfun -> machine -> split_stack_arg_pointer ) = 1 ; pat = gen_rtx_SET ( cfun -> machine -> split_stack_arg_pointer , gen_rtx_REG ( Pmode , 12 ) ) ; push_topmost_sequence ( ) ; emit_insn_after ( pat , get_insns ( ) ) ; pop_topmost_sequence ( ) ; } return plus_constant ( Pmode , cfun -> machine -> split_stack_arg_pointer , FIRST_PARM_OFFSET ( current_function_decl ) ) ; } return virtual_incoming_args_rtx ; } </s>

Return the internal arg pointer used for function incoming arguments . When -fsplit-stack , the arg pointer is r12 so we need to copy it to a pseudo in order for it to be preserved over calls and suchlike . We 'd really like to use a pseudo here for the internal arg pointer but data-flow analysis is not prepared to accept pseudos as live at the beginning of a function .


"operation should have been legalized before now"

Select and emit code for a binary operator instruction , which has an opcode which directly corresponds to the given ISD opcode .


<s> bool isReg ( ) const override { return Kind == k_Register && ! Reg . isVector ; } </s>


<s> static machine_mode frv_matching_accg_mode ( machine_mode mode ) { switch ( mode ) { case E_V4SImode : return V4QImode ; case E_DImode : return HImode ; case E_SImode : return QImode ; default : gcc_unreachable ( ) ; } } </s>

If an ACC rtx has mode MODE , return the mode that the matching ACCG should have .


<s>
bool
AMDGPUMachineCFGStructurizer
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
const
SISubtarget
&
ST
=
MF
.
getSubtarget
<
SISubtarget
>
(
)
;
const
SIInstrInfo
*
TII
=
ST
.
getInstrInfo
(
)
;
TRI
=
ST
.
getRegisterInfo
(
)
;
MRI
=
&
(
MF
.
getRegInfo
(
)
)
;
initFallthroughMap
(
MF
)
;
checkRegOnlyPHIInputs
(
MF
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"----STRUCTURIZER START----\n"
)
;
LLVM_DEBUG
(
MF
.
dump
(
)
)
;
Regions
=
&
(
getAnalysis
<
MachineRegionInfoPass
>
(
)
.
getRegionInfo
(
)
)
;
LLVM_DEBUG
(
Regions
->
dump
(
)
)
;
RegionMRT
*
RTree
=
MRT
::
buildMRT
(
MF
,
Regions
,
TII
,
MRI
)
;
setRegionMRT
(
RTree
)
;
initializeSelectRegisters
(
RTree
,
0
,
MRI
,
TII
)
;
LLVM_DEBUG
(
RTree
->
dump
(
TRI
)
)
;
bool
result
=
structurizeRegions
(
RTree
,
true
)
;
delete
RTree
;
LLVM_DEBUG
(
dbgs
(
)
<<
"----STRUCTURIZER END----\n"
)
;
initFallthroughMap
(
MF
)
;
return
result
;
}
</s>

runOnMachineFunction - Emit the function body .

AMDGPU
AMDGPU
SI
SI
SI
"----STRUCTURIZER START----\n"
0
"----STRUCTURIZER END----\n"


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> void h8300_expand_branch ( rtx operands [ ] ) { enum rtx_code code = GET_CODE ( operands [ 0 ] ) ; rtx op0 = operands [ 1 ] ; rtx op1 = operands [ 2 ] ; rtx label = operands [ 3 ] ; rtx tmp ; tmp = gen_rtx_COMPARE ( VOIDmode , op0 , op1 ) ; emit_insn ( gen_rtx_SET ( cc0_rtx , tmp ) ) ; tmp = gen_rtx_fmt_ee ( code , VOIDmode , cc0_rtx , const0_rtx ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; } </s>


<s> bool TypedPointerType :: isValidElementType ( Type * ElemTy ) { return ! ElemTy -> isVoidTy ( ) && ! ElemTy -> isLabelTy ( ) && ! ElemTy -> isMetadataTy ( ) && ! ElemTy -> isTokenTy ( ) && ! ElemTy -> isX86_AMXTy ( ) ; } </s>

Return true if the specified type is valid as a element type .


<s> void SparcPassConfig :: addPreEmitPass ( ) { addPass ( createSparcDelaySlotFillerPass ( getSparcTargetMachine ( ) ) ) ; } </s>


<s> static void emit_load_locked ( machine_mode mode , rtx reg , rtx mem ) { rtx ( * fn ) ( rtx , rtx ) = NULL ; if ( mode == SImode ) fn = gen_load_locked_si ; else if ( mode == DImode ) fn = gen_load_locked_di ; emit_insn ( fn ( reg , mem ) ) ; } </s>

A subroutine of the atomic operation splitters . Emit a load-locked instruction in MODE . For QI/HImode , possibly use a pattern than includes the zero_extend operation .