<s>
bool
FPS
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
bool
FPIsUsed
=
false
;
assert
(
X86
::
FP6
==
X86
::
FP0
+
6
&&
"Register enums aren't sorted right!"
)
;
for
(
unsigned
i
=
0
;
i
<=
6
;
++
i
)
if
(
MF
.
getRegInfo
(
)
.
isPhysRegUsed
(
X86
::
FP0
+
i
)
)
{
FPIsUsed
=
true
;
break
;
}
if
(
!
FPIsUsed
)
return
false
;
Bundles
=
&
getAnalysis
<
EdgeBundles
>
(
)
;
TII
=
MF
.
getTarget
(
)
.
getInstrInfo
(
)
;
bundleCFG
(
MF
)
;
StackTop
=
0
;
SmallPtrSet
<
MachineBasicBlock
*
,
8
>
Processed
;
MachineBasicBlock
*
Entry
=
MF
.
begin
(
)
;
bool
Changed
=
false
;
for
(
df_ext_iterator
<
MachineBasicBlock
*
,
SmallPtrSet
<
MachineBasicBlock
*
,
8
>
>
I
=
df_ext_begin
(
Entry
,
Processed
)
,
E
=
df_ext_end
(
Entry
,
Processed
)
;
I
!=
E
;
++
I
)
Changed
|=
processBasicBlock
(
MF
,
*
*
I
)
;
if
(
MF
.
size
(
)
!=
Processed
.
size
(
)
)
for
(
MachineFunction
::
iterator
BB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
BB
!=
E
;
++
BB
)
if
(
Processed
.
insert
(
BB
)
)
Changed
|=
processBasicBlock
(
MF
,
*
BB
)
;
LiveBundles
.
clear
(
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> FastISel * ARM :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) { const TargetMachine & TM = funcInfo . MF -> getTarget ( ) ; const ARMSubtarget * Subtarget = & TM . getSubtarget < ARMSubtarget > ( ) ; if ( Subtarget -> isTargetIOS ( ) && ! Subtarget -> isThumb1Only ( ) ) return new ARMFastISel ( funcInfo , libInfo ) ; return 0 ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> bool aarch64_emit_approx_div ( rtx quo , rtx num , rtx den ) { machine_mode mode = GET_MODE ( quo ) ; if ( GET_MODE_INNER ( mode ) == HFmode ) return false ; bool use_approx_division_p = ( flag_mlow_precision_div || ( aarch64_tune_params . approx_modes -> division & AARCH64_APPROX_MODE ( mode ) ) ) ; if ( ! flag_finite_math_only || flag_trapping_math || ! flag_unsafe_math_optimizations || optimize_function_for_size_p ( cfun ) || ! use_approx_division_p ) return false ; if ( ! TARGET_SIMD && VECTOR_MODE_P ( mode ) ) return false ; rtx xrcp = gen_reg_rtx ( mode ) ; emit_insn ( ( * get_recpe_type ( mode ) ) ( xrcp , den ) ) ; int iterations = ( GET_MODE_INNER ( mode ) == DFmode ) ? 3 : 2 ; if ( flag_mlow_precision_div ) iterations -- ; rtx xtmp = gen_reg_rtx ( mode ) ; while ( iterations -- ) { emit_insn ( ( * get_recps_type ( mode ) ) ( xtmp , xrcp , den ) ) ; if ( iterations > 0 ) emit_set_insn ( xrcp , gen_rtx_MULT ( mode , xrcp , xtmp ) ) ; } if ( num != CONST1_RTX ( mode ) ) { rtx xnum = force_reg ( mode , num ) ; emit_set_insn ( xrcp , gen_rtx_MULT ( mode , xrcp , xnum ) ) ; } emit_set_insn ( quo , gen_rtx_MULT ( mode , xrcp , xtmp ) ) ; return true ; } </s>

Emit the instruction sequence to compute the approximation for the division of NUM by DEN in QUO and return whether the sequence was emitted or not .


<s>
SDValue
TGSITargetLowering
::
LowerOperation
(
SDValue
op
,
SelectionDAG
&
dag
)
const
{
switch
(
op
.
getOpcode
(
)
)
{
case
ISD
::
INTRINSIC_WO_CHAIN
:
{
unsigned
IntrinsicID
=
cast
<
ConstantSDNode
>
(
op
.
getOperand
(
0
)
)
->
getZExtValue
(
)
;
EVT
VT
=
op
.
getValueType
(
)
;
switch
(
IntrinsicID
)
{
case
Intrinsic
::
tgsi_read_blockid_x
:
return
CreateLiveInRegister
(
dag
,
&
TGSI
::
IRegsRegClass
,
TGSI_BLOCK_ID
(
x
)
,
VT
)
;
case
Intrinsic
::
tgsi_read_blockid_y
:
return
CreateLiveInRegister
(
dag
,
&
TGSI
::
IRegsRegClass
,
TGSI_BLOCK_ID
(
y
)
,
VT
)
;
case
Intrinsic
::
tgsi_read_blockid_z
:
return
CreateLiveInRegister
(
dag
,
&
TGSI
::
IRegsRegClass
,
TGSI_BLOCK_ID
(
z
)
,
VT
)
;
case
Intrinsic
::
tgsi_read_blocksize_x
:
return
CreateLiveInRegister
(
dag
,
&
TGSI
::
IRegsRegClass
,
TGSI_BLOCK_SIZE
(
x
)
,
VT
)
;
case
Intrinsic
::
tgsi_read_blocksize_y
:
return
CreateLiveInRegister
(
dag
,
&
TGSI
::
IRegsRegClass
,
TGSI_BLOCK_SIZE
(
y
)
,
VT
)
;
case
Intrinsic
::
tgsi_read_blocksize_z
:
return
CreateLiveInRegister
(
dag
,
&
TGSI
::
IRegsRegClass
,
TGSI_BLOCK_SIZE
(
z
)
,
VT
)
;
case
Intrinsic
::
tgsi_read_gridsize_x
:
return
CreateLiveInRegister
(
dag
,
&
TGSI
::
IRegsRegClass
,
TGSI_GRID_SIZE
(
x
)
,
VT
)
;
case
Intrinsic
::
tgsi_read_gridsize_y
:
return
CreateLiveInRegister
(
dag
,
&
TGSI
::
IRegsRegClass
,
TGSI_GRID_SIZE
(
y
)
,
VT
)
;
case
Intrinsic
::
tgsi_read_gridsize_z
:
return
CreateLiveInRegister
(
dag
,
&
TGSI
::
IRegsRegClass
,
TGSI_GRID_SIZE
(
z
)
,
VT
)
;
case
Intrinsic
::
tgsi_read_threadid_x
:
return
CreateLiveInRegister
(
dag
,
&
TGSI
::
IRegsRegClass
,
TGSI_THREAD_ID
(
x
)
,
VT
)
;
case
Intrinsic
::
tgsi_read_threadid_y
:
return
CreateLiveInRegister
(
dag
,
&
TGSI
::
IRegsRegClass
,
TGSI_THREAD_ID
(
y
)
,
VT
)
;
case
Intrinsic
::
tgsi_read_threadid_z
:
return
CreateLiveInRegister
(
dag
,
&
TGSI
::
IRegsRegClass
,
TGSI_THREAD_ID
(
z
)
,
VT
)
;
case
Intrinsic
::
tgsi_read_workdim
:
return
CreateLiveInRegister
(
dag
,
&
TGSI
::
IRegsRegClass
,
TGSI_WORK_DIM
,
VT
)
;
default
:
llvm_unreachable
(
"Unknown TGSI Intrinsic"
)
;
}
break
;
}
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

TGSI
TGSI
ISD::INTRINSIC_WO_CHAIN
0
Intrinsic::tgsi_read_blockid_x
TGSI::IRegsRegClass
TGSI
Intrinsic::tgsi_read_blockid_y
TGSI::IRegsRegClass
TGSI
Intrinsic::tgsi_read_blockid_z
TGSI::IRegsRegClass
TGSI
Intrinsic::tgsi_read_blocksize_x
TGSI::IRegsRegClass
TGSI
Intrinsic::tgsi_read_blocksize_y
TGSI::IRegsRegClass
TGSI
Intrinsic::tgsi_read_blocksize_z
TGSI::IRegsRegClass
TGSI
Intrinsic::tgsi_read_gridsize_x
TGSI::IRegsRegClass
TGSI
Intrinsic::tgsi_read_gridsize_y
TGSI::IRegsRegClass
TGSI
Intrinsic::tgsi_read_gridsize_z
TGSI::IRegsRegClass
TGSI
Intrinsic::tgsi_read_threadid_x
TGSI::IRegsRegClass
TGSI
Intrinsic::tgsi_read_threadid_y
TGSI::IRegsRegClass
TGSI
Intrinsic::tgsi_read_threadid_z
TGSI::IRegsRegClass
TGSI
Intrinsic::tgsi_read_workdim
TGSI::IRegsRegClass
TGSI
"Unknown TGSI Intrinsic"
"Should not custom lower this!"


<s> void s390_expand_vec_compare_cc ( rtx target , enum rtx_code code , rtx cmp1 , rtx cmp2 , bool all_p ) { machine_mode cc_producer_mode , cc_consumer_mode , scratch_mode ; rtx tmp_reg = gen_reg_rtx ( SImode ) ; bool swap_p = false ; if ( GET_MODE_CLASS ( GET_MODE ( cmp1 ) ) == MODE_VECTOR_INT ) { switch ( code ) { case EQ : case NE : cc_producer_mode = CCVEQmode ; break ; case GE : case LT : code = swap_condition ( code ) ; swap_p = true ; case GT : case LE : cc_producer_mode = CCVIHmode ; break ; case GEU : case LTU : code = swap_condition ( code ) ; swap_p = true ; case GTU : case LEU : cc_producer_mode = CCVIHUmode ; break ; default : gcc_unreachable ( ) ; } scratch_mode = GET_MODE ( cmp1 ) ; if ( code == NE || code == LE || code == LEU ) all_p = ! all_p ; cc_consumer_mode = all_p ? CCVIALLmode : CCVIANYmode ; } else if ( GET_MODE_CLASS ( GET_MODE ( cmp1 ) ) == MODE_VECTOR_FLOAT ) { bool inv_p = false ; switch ( code ) { case EQ : cc_producer_mode = CCVEQmode ; break ; case NE : cc_producer_mode = CCVEQmode ; inv_p = true ; break ; case GT : cc_producer_mode = CCVFHmode ; break ; case GE : cc_producer_mode = CCVFHEmode ; break ; case UNLE : cc_producer_mode = CCVFHmode ; inv_p = true ; break ; case UNLT : cc_producer_mode = CCVFHEmode ; inv_p = true ; break ; case LT : cc_producer_mode = CCVFHmode ; code = GT ; swap_p = true ; break ; case LE : cc_producer_mode = CCVFHEmode ; code = GE ; swap_p = true ; break ; default : gcc_unreachable ( ) ; } scratch_mode = mode_for_vector ( int_mode_for_mode ( GET_MODE_INNER ( GET_MODE ( cmp1 ) ) ) , GET_MODE_NUNITS ( GET_MODE ( cmp1 ) ) ) ; gcc_assert ( scratch_mode != BLKmode ) ; if ( inv_p ) all_p = ! all_p ; cc_consumer_mode = all_p ? CCVFALLmode : CCVFANYmode ; } else gcc_unreachable ( ) ; if ( swap_p ) { rtx tmp = cmp2 ; cmp2 = cmp1 ; cmp1 = tmp ; } emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , gen_rtx_SET ( gen_rtx_REG ( cc_producer_mode , CC_REGNUM ) , gen_rtx_COMPARE ( cc_producer_mode , cmp1 , cmp2 ) ) , gen_rtx_CLOBBER ( VOIDmode , gen_rtx_SCRATCH ( scratch_mode ) ) ) ) ) ; emit_move_insn ( target , const0_rtx ) ; emit_move_insn ( tmp_reg , const1_rtx ) ; emit_move_insn ( target , gen_rtx_IF_THEN_ELSE ( SImode , gen_rtx_fmt_ee ( code , VOIDmode , gen_rtx_REG ( cc_consumer_mode , CC_REGNUM ) , const0_rtx ) , tmp_reg , target ) ) ; } </s>

Expand the comparison CODE of CMP1 and CMP2 and copy 1 or 0 into TARGET if either all ( ALL_P is true ) or any ( ALL_P is false ) of the elements in CMP1 and CMP2 fulfill the comparison .


<s> bool arm_pad_reg_upward ( enum machine_mode mode ATTRIBUTE_UNUSED , tree type , int first ATTRIBUTE_UNUSED ) { if ( TARGET_AAPCS_BASED && BYTES_BIG_ENDIAN && ( AGGREGATE_TYPE_P ( type ) || TREE_CODE ( type ) == COMPLEX_TYPE ) && int_size_in_bytes ( type ) <= 4 ) return true ; return ! BYTES_BIG_ENDIAN ; } </s>

Similarly , for use by BLOCK_REG_PADDING ( MODE , TYPE , FIRST ) . For non-AAPCS , return ! BYTES_BIG_ENDIAN if the least significant byte of the register has useful data , and return the opposite if the most significant byte does . For AAPCS , small aggregates and small complex types are always padded upwards .


<s> static int ia64_mode_to_int ( machine_mode mode ) { switch ( mode ) { case BImode : return 0 ; case QImode : return 1 ; case HImode : return 2 ; case SImode : return 3 ; case DImode : return 4 ; case SFmode : return 5 ; case DFmode : return 6 ; case XFmode : return 7 ; case TImode : return SPEC_MODE_INVALID ; default : return SPEC_MODE_INVALID ; } } </s>


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override { const AArch64Subtarget & ST = C -> MF -> getSubtarget < AArch64Subtarget > ( ) ; if ( ST . hasFuseAES ( ) || ST . hasFuseLiterals ( ) ) { ScheduleDAGMI * DAG = createGenericSchedPostRA ( C ) ; DAG -> addMutation ( createAArch64MacroFusionDAGMutation ( ) ) ; return DAG ; } return nullptr ; } </s>

Similar to createMachineScheduler but used when postRA machine scheduling is enabled .


<s> int nds32_can_use_return_insn ( void ) { int sp_adjust ; if ( ! reload_completed ) return 0 ; if ( cfun -> machine -> attr_naked_p && ! flag_ret_in_naked_func ) return 0 ; sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; if ( ! cfun -> machine -> fp_as_gp_p && satisfies_constraint_Iu08 ( GEN_INT ( sp_adjust ) ) && NDS32_DOUBLE_WORD_ALIGN_P ( sp_adjust ) && ! cfun -> calls_alloca && NDS32_V3PUSH_AVAILABLE_P && ! ( TARGET_HARD_FLOAT && ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) ) ) return 1 ; return ( cfun -> machine -> naked_p && ( cfun -> machine -> va_args_size == 0 ) ) ; } </s>

Return nonzero if this function is known to have a null epilogue . This allows the optimizer to omit jumps to jumps if no stack was created .


<s> Optional < Instruction * > AArch64TTIImpl :: instCombineIntrinsic ( InstCombiner & IC , IntrinsicInst & II ) const { Intrinsic :: ID IID = II . getIntrinsicID ( ) ; switch ( IID ) { default : break ; case Intrinsic :: aarch64_sve_convert_from_svbool : return instCombineConvertFromSVBool ( IC , II ) ; case Intrinsic :: aarch64_sve_dup : return instCombineSVEDup ( IC , II ) ; case Intrinsic :: aarch64_sve_dup_x : return instCombineSVEDupX ( IC , II ) ; case Intrinsic :: aarch64_sve_cmpne : case Intrinsic :: aarch64_sve_cmpne_wide : return instCombineSVECmpNE ( IC , II ) ; case Intrinsic :: aarch64_sve_rdffr : return instCombineRDFFR ( IC , II ) ; case Intrinsic :: aarch64_sve_lasta : case Intrinsic :: aarch64_sve_lastb : return instCombineSVELast ( IC , II ) ; case Intrinsic :: aarch64_sve_cntd : return instCombineSVECntElts ( IC , II , 2 ) ; case Intrinsic :: aarch64_sve_cntw : return instCombineSVECntElts ( IC , II , 4 ) ; case Intrinsic :: aarch64_sve_cnth : return instCombineSVECntElts ( IC , II , 8 ) ; case Intrinsic :: aarch64_sve_cntb : return instCombineSVECntElts ( IC , II , 16 ) ; case Intrinsic :: aarch64_sve_ptest_any : case Intrinsic :: aarch64_sve_ptest_first : case Intrinsic :: aarch64_sve_ptest_last : return instCombineSVEPTest ( IC , II ) ; case Intrinsic :: aarch64_sve_mul : case Intrinsic :: aarch64_sve_fmul : return instCombineSVEVectorMul ( IC , II ) ; case Intrinsic :: aarch64_sve_fadd : return instCombineSVEVectorFAdd ( IC , II ) ; case Intrinsic :: aarch64_sve_fsub : return instCombineSVEVectorBinOp ( IC , II ) ; case Intrinsic :: aarch64_sve_tbl : return instCombineSVETBL ( IC , II ) ; case Intrinsic :: aarch64_sve_uunpkhi : case Intrinsic :: aarch64_sve_uunpklo : case Intrinsic :: aarch64_sve_sunpkhi : case Intrinsic :: aarch64_sve_sunpklo : return instCombineSVEUnpack ( IC , II ) ; case Intrinsic :: aarch64_sve_tuple_get : return instCombineSVETupleGet ( IC , II ) ; case Intrinsic :: aarch64_sve_zip1 : case Intrinsic :: aarch64_sve_zip2 : return instCombineSVEZip ( IC , II ) ; case Intrinsic :: aarch64_sve_ld1_gather_index : return instCombineLD1GatherIndex ( IC , II ) ; case Intrinsic :: aarch64_sve_st1_scatter_index : return instCombineST1ScatterIndex ( IC , II ) ; case Intrinsic :: aarch64_sve_ld1 : return instCombineSVELD1 ( IC , II , DL ) ; case Intrinsic :: aarch64_sve_st1 : return instCombineSVEST1 ( IC , II , DL ) ; } return None ; } </s>

Targets can implement their own combinations for target-specific intrinsics .


"LOAD_STACK_GUARD currently supported only for MachO."

This function is called for all pseudo instructions that remain after register allocation .


<s> TargetIRAnalysis XCoreTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( Function & ) { return TargetTransformInfo ( XCoreTTIImpl ( this ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s>
void
WebAssemblyAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
DEBUG
(
dbgs
(
)
<<
"EmitInstruction: "
<<
*
MI
<<
'\n'
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
WebAssembly
::
ARGUMENT_I32
:
case
WebAssembly
::
ARGUMENT_I64
:
case
WebAssembly
::
ARGUMENT_F32
:
case
WebAssembly
::
ARGUMENT_F64
:
break
;
case
WebAssembly
::
LOOP_END
:
break
;
default
:
{
WebAssemblyMCInstLower
MCInstLowering
(
OutContext
,
*
this
)
;
MCInst
TmpInst
;
MCInstLowering
.
Lower
(
MI
,
TmpInst
)
;
EmitToStreamer
(
*
OutStreamer
,
TmpInst
)
;
break
;
}
}
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> virtual const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> static bool arm_can_inline_p ( tree caller , tree callee ) { tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET ( caller ) ; tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET ( callee ) ; bool can_inline = true ; struct cl_target_option * caller_opts = TREE_TARGET_OPTION ( caller_tree ? caller_tree : target_option_default_node ) ; struct cl_target_option * callee_opts = TREE_TARGET_OPTION ( callee_tree ? callee_tree : target_option_default_node ) ; if ( callee_opts == caller_opts ) return true ; struct arm_build_target caller_target ; struct arm_build_target callee_target ; caller_target . isa = sbitmap_alloc ( isa_num_bits ) ; callee_target . isa = sbitmap_alloc ( isa_num_bits ) ; arm_configure_build_target ( & caller_target , caller_opts , false ) ; arm_configure_build_target ( & callee_target , callee_opts , false ) ; if ( ! bitmap_subset_p ( callee_target . isa , caller_target . isa ) ) can_inline = false ; sbitmap_free ( caller_target . isa ) ; sbitmap_free ( callee_target . isa ) ; return can_inline ; } </s>

Hook to determine if one function can safely inline another .


<s> static int const_costs ( rtx r , enum rtx_code c ) { HOST_WIDE_INT high , low ; switch ( c ) { case CONST_INT : return const_costs_int ( INTVAL ( r ) , 0 ) ; case CONST_DOUBLE : const_double_split ( r , & high , & low ) ; if ( GET_MODE ( r ) == SFmode ) return const_costs_int ( high , 1 ) ; else return const_costs_int ( high , 1 ) + const_costs_int ( low , 1 ) ; case SYMBOL_REF : case LABEL_REF : case CONST : return 2 ; case HIGH : return 1 ; default : return 4 ; } } </s>

Return the cost of the rtx R with code CODE .


Change register usage conditional on target flags .


<s> bool RISCVAsmBackend :: shouldInsertExtraNopBytesForCodeAlign ( const MCAlignFragment & AF , unsigned & Size ) { if ( ! STI . getFeatureBits ( ) [ RISCV :: FeatureRelax ] ) return false ; bool HasStdExtC = STI . getFeatureBits ( ) [ RISCV :: FeatureStdExtC ] ; unsigned MinNopLen = HasStdExtC ? 2 : 4 ; Size = AF . getAlignment ( ) - MinNopLen ; return true ; } </s>

Hook to check if extra nop bytes must be inserted for alignment directive .

RISCV RISCV RISCV::FeatureRelax RISCV::FeatureStdExtC 2 4


<s> static rtx rs6000_mask_atomic_subword ( rtx oldval , rtx newval , rtx mask ) { rtx x ; x = gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x , gen_rtx_AND ( SImode , gen_rtx_NOT ( SImode , mask ) , oldval ) ) ) ; x = expand_simple_binop ( SImode , IOR , newval , x , x , 1 , OPTAB_LIB_WIDEN ) ; return x ; } </s>

A subroutine of the various atomic expanders . For sub-word operands , combine OLDVAL and NEWVAL via MASK . Returns a new pseduo .


<s> void NVPTXPassConfig :: addIRPasses ( ) { disablePass ( & PrologEpilogCodeInserterID ) ; disablePass ( & MachineCopyPropagationID ) ; disablePass ( & BranchFolderPassID ) ; TargetPassConfig :: addIRPasses ( ) ; addPass ( createGenericToNVVMPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


runOnMachineFunction - Emit the function body .


<s> char * aarch64_output_sve_vector_inc_dec ( const char * operands , rtx x ) { int factor ; unsigned int nelts_per_vq ; if ( ! aarch64_sve_vector_inc_dec_immediate_p ( x , & factor , & nelts_per_vq ) ) gcc_unreachable ( ) ; if ( factor < 0 ) return aarch64_output_sve_cnt_immediate ( "dec" , operands , AARCH64_SV_ALL , - factor , nelts_per_vq ) ; else return aarch64_output_sve_cnt_immediate ( "inc" , operands , AARCH64_SV_ALL , factor , nelts_per_vq ) ; } </s>

Return the asm template for an SVE vector INC or DEC instruction . OPERANDS gives the operands before the vector count and X is the value of the vector count operand itself .


<s> EVT R600TargetLowering :: getSetCCResultType ( EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> void MipsPassConfig :: addPreEmitPass ( ) { addPass ( createMipsExpandPseudoPass ( ) ) ; addPass ( createMicroMipsSizeReducePass ( ) ) ; if ( EnableMulMulFix ) addPass ( createMipsMulMulBugPass ( ) ) ; addPass ( createMipsDelaySlotFillerPass ( ) ) ; addPass ( createMipsBranchExpansion ( ) ) ; addPass ( createMipsConstantIslandPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void TPCAsmInstCompress :: EmitInstruction ( MCInst & Inst , MCStreamer & Out , const MCSubtargetInfo & STI ) { Out . EmitInstruction ( Inst , STI ) ; } </s>


<s> void OR1KRegisterInfo :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const { } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> static bool isEqual ( SPIRV :: SpecialTypeDescriptor LHS , SPIRV :: SpecialTypeDescriptor RHS ) { return getHashValue ( LHS ) == getHashValue ( RHS ) ; } </s>

isEqual - Compares two trees for structural equality and returns true if they are equal .


<s> bool ARMCodeGenPrepare :: doFinalization ( Module & M ) { delete Promoter ; return false ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> static tree xstormy16_build_builtin_va_list ( void ) { tree f_1 , f_2 , record , type_decl ; record = ( * lang_hooks . types . make_type ) ( RECORD_TYPE ) ; type_decl = build_decl ( TYPE_DECL , get_identifier ( "__va_list_tag" ) , record ) ; f_1 = build_decl ( FIELD_DECL , get_identifier ( "base" ) , ptr_type_node ) ; f_2 = build_decl ( FIELD_DECL , get_identifier ( "count" ) , unsigned_type_node ) ; DECL_FIELD_CONTEXT ( f_1 ) = record ; DECL_FIELD_CONTEXT ( f_2 ) = record ; TREE_CHAIN ( record ) = type_decl ; TYPE_NAME ( record ) = type_decl ; TYPE_FIELDS ( record ) = f_1 ; TREE_CHAIN ( f_1 ) = f_2 ; layout_type ( record ) ; return record ; } </s>

Build the va_list type . For this chip , va_list is a record containing a counter and a pointer . The counter is of type 'int ' and indicates how many bytes have been used to date . The pointer indicates the stack position for arguments that have not been passed in registers . To keep the layout nice , the pointer is first in the structure .


<s> const uint32_t * Z80oldRegisterInfo :: getNoPreservedMask ( ) const { return CSR_NoRegs_RegMask ; } </s>

Return a register mask that clobbers everything .


<s> virtual const GBZ80RegisterInfo * getRegisterInfo ( ) const { return & getInstrInfo ( ) -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool forceScalarizeMaskedScatter ( VectorType * VTy , Align Alignment ) { return forceScalarizeMaskedGather ( VTy , Alignment ) ; } </s>

Return true if the target forces scalarizing of llvm.masked.scatter intrinsics .


<s>
BitVector
ARMBaseRegisterInfo
::
getReservedRegs
(
const
MachineFunction
&
MF
)
const
{
const
ARMSubtarget
&
STI
=
MF
.
getSubtarget
<
ARMSubtarget
>
(
)
;
const
ARMFrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
BitVector
Reserved
(
getNumRegs
(
)
)
;
markSuperRegs
(
Reserved
,
ARM
::
SP
)
;
markSuperRegs
(
Reserved
,
ARM
::
PC
)
;
markSuperRegs
(
Reserved
,
ARM
::
FPSCR
)
;
markSuperRegs
(
Reserved
,
ARM
::
APSR_NZCV
)
;
if
(
TFI
->
hasFP
(
MF
)
)
markSuperRegs
(
Reserved
,
getFramePointerReg
(
STI
)
)
;
if
(
hasBasePointer
(
MF
)
)
markSuperRegs
(
Reserved
,
BasePtr
)
;
if
(
STI
.
isR9Reserved
(
)
)
markSuperRegs
(
Reserved
,
ARM
::
R9
)
;
const
Function
&
F
=
MF
.
getFunction
(
)
;
if
(
F
.
getCallingConv
(
)
==
CallingConv
::
Mono
)
markSuperRegs
(
Reserved
,
ARM
::
R8
)
;
if
(
!
STI
.
hasVFP3
(
)
||
STI
.
hasD16
(
)
)
{
static_assert
(
ARM
::
D31
==
ARM
::
D16
+
15
,
"Register list not consecutive!"
)
;
for
(
unsigned
R
=
0
;
R
<
16
;
++
R
)
markSuperRegs
(
Reserved
,
ARM
::
D16
+
R
)
;
}
const
TargetRegisterClass
&
RC
=
ARM
::
GPRPairRegClass
;
for
(
unsigned
Reg
:
RC
)
for
(
MCSubRegIterator
SI
(
Reg
,
this
)
;
SI
.
isValid
(
)
;
++
SI
)
if
(
Reserved
.
test
(
*
SI
)
)
markSuperRegs
(
Reserved
,
Reg
)
;
assert
(
checkAllSuperRegsMarked
(
Reserved
)
)
;
return
Reserved
;
}
</s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


"Only floating point immediates are supported at the moment."


<s> bool isImm ( ) const { return Kind == k_Immediate ; } </s>


<s> BitVector SIRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AMDGPU :: INDIRECT_BASE_ADDR ) ; reserveRegisterTuples ( Reserved , AMDGPU :: EXEC ) ; reserveRegisterTuples ( Reserved , AMDGPU :: FLAT_SCR ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_SHARED_BASE ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_SHARED_LIMIT ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_PRIVATE_BASE ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_PRIVATE_LIMIT ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TBA ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TMA ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP0_TTMP1 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP2_TTMP3 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP4_TTMP5 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP6_TTMP7 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP8_TTMP9 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP10_TTMP11 ) ; const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; unsigned MaxNumSGPRs = ST . getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = AMDGPU :: SGPR_32RegClass . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = AMDGPU :: SGPR_32RegClass . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } unsigned MaxNumVGPRs = ST . getMaxNumVGPRs ( MF ) ; unsigned TotalNumVGPRs = AMDGPU :: VGPR_32RegClass . getNumRegs ( ) ; for ( unsigned i = MaxNumVGPRs ; i < TotalNumVGPRs ; ++ i ) { unsigned Reg = AMDGPU :: VGPR_32RegClass . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } const SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , ScratchWaveOffsetReg ) ; } unsigned ScratchRSrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRSrcReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , ScratchRSrcReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , ScratchWaveOffsetReg ) ) ; } return Reserved ; } </s>


<s> MachineInstr * SIInstrInfo :: createPHISourceCopy ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator InsPt , const DebugLoc & DL , Register Src , unsigned SrcSubReg , Register Dst ) const { if ( InsPt != MBB . end ( ) && ( InsPt -> getOpcode ( ) == AMDGPU :: SI_IF || InsPt -> getOpcode ( ) == AMDGPU :: SI_ELSE || InsPt -> getOpcode ( ) == AMDGPU :: SI_IF_BREAK ) && InsPt -> definesRegister ( Src ) ) { InsPt ++ ; return BuildMI ( MBB , InsPt , DL , get ( ST . isWave32 ( ) ? AMDGPU :: S_MOV_B32_term : AMDGPU :: S_MOV_B64_term ) , Dst ) . addReg ( Src , 0 , SrcSubReg ) . addReg ( AMDGPU :: EXEC , RegState :: Implicit ) ; } return TargetInstrInfo :: createPHISourceCopy ( MBB , InsPt , DL , Src , SrcSubReg , Dst ) ; } </s>

During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destination register in a target specific manner .


<s> uint8_t get_sew ( ) const { return m_sew ; } </s>

Helper function to get SEW operand . We always have SEW value for all RVV instructions that have VTYPE OP .


<s>
void
WebAssemblyAsmPrinter
::
emitInstruction
(
const
MachineInstr
*
MI
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"EmitInstruction: "
<<
*
MI
<<
'\n'
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
WebAssembly
::
ARGUMENT_i32
:
case
WebAssembly
::
ARGUMENT_i32_S
:
case
WebAssembly
::
ARGUMENT_i64
:
case
WebAssembly
::
ARGUMENT_i64_S
:
case
WebAssembly
::
ARGUMENT_f32
:
case
WebAssembly
::
ARGUMENT_f32_S
:
case
WebAssembly
::
ARGUMENT_f64
:
case
WebAssembly
::
ARGUMENT_f64_S
:
case
WebAssembly
::
ARGUMENT_v16i8
:
case
WebAssembly
::
ARGUMENT_v16i8_S
:
case
WebAssembly
::
ARGUMENT_v8i16
:
case
WebAssembly
::
ARGUMENT_v8i16_S
:
case
WebAssembly
::
ARGUMENT_v4i32
:
case
WebAssembly
::
ARGUMENT_v4i32_S
:
case
WebAssembly
::
ARGUMENT_v2i64
:
case
WebAssembly
::
ARGUMENT_v2i64_S
:
case
WebAssembly
::
ARGUMENT_v4f32
:
case
WebAssembly
::
ARGUMENT_v4f32_S
:
case
WebAssembly
::
ARGUMENT_v2f64
:
case
WebAssembly
::
ARGUMENT_v2f64_S
:
break
;
case
WebAssembly
::
FALLTHROUGH_RETURN
:
{
if
(
isVerbose
(
)
)
{
OutStreamer
->
AddComment
(
"fallthrough-return"
)
;
OutStreamer
->
AddBlankLine
(
)
;
}
break
;
}
case
WebAssembly
::
COMPILER_FENCE
:
break
;
default
:
{
WebAssemblyMCInstLower
MCInstLowering
(
OutContext
,
*
this
)
;
MCInst
TmpInst
;
MCInstLowering
.
lower
(
MI
,
TmpInst
)
;
EmitToStreamer
(
*
OutStreamer
,
TmpInst
)
;
break
;
}
}
}
</s>

Targets should implement this to emit instructions .


<s> static machine_mode select_block_compare_mode ( unsigned HOST_WIDE_INT offset , unsigned HOST_WIDE_INT bytes , unsigned HOST_WIDE_INT align ) { unsigned HOST_WIDE_INT maxread = ROUND_UP ( bytes , align ) ; int word_mode_ok = ! ( ! BYTES_BIG_ENDIAN && ! TARGET_LDBRX && word_mode == DImode ) ; if ( word_mode_ok && bytes >= UNITS_PER_WORD ) return word_mode ; else if ( bytes == GET_MODE_SIZE ( SImode ) ) return SImode ; else if ( bytes == GET_MODE_SIZE ( HImode ) ) return HImode ; else if ( bytes == GET_MODE_SIZE ( QImode ) ) return QImode ; else if ( bytes < GET_MODE_SIZE ( SImode ) && TARGET_EFFICIENT_OVERLAPPING_UNALIGNED && offset >= GET_MODE_SIZE ( SImode ) - bytes ) return SImode ; else if ( word_mode_ok && bytes < UNITS_PER_WORD && TARGET_EFFICIENT_OVERLAPPING_UNALIGNED && offset >= UNITS_PER_WORD - bytes ) return word_mode ; else if ( word_mode_ok && maxread >= UNITS_PER_WORD ) return word_mode ; else if ( maxread >= GET_MODE_SIZE ( SImode ) ) return SImode ; else if ( bytes > GET_MODE_SIZE ( SImode ) ) return SImode ; else if ( bytes > GET_MODE_SIZE ( HImode ) ) return HImode ; return QImode ; } </s>

Select the mode to be used for reading the next chunk of bytes in the compare . OFFSET is the current read offset from the beginning of the block . BYTES is the number of bytes remaining to be read . ALIGN is the minimum alignment of the memory blocks being compared in bytes .


<s> void ARMBaseRegisterInfo :: getRegAllocationHints ( unsigned VirtReg , ArrayRef < MCPhysReg > Order , SmallVectorImpl < MCPhysReg > & Hints , const MachineFunction & MF , const VirtRegMap * VRM ) const { const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; std :: pair < unsigned , unsigned > Hint = MRI . getRegAllocationHint ( VirtReg ) ; unsigned Odd ; switch ( Hint . first ) { case ARMRI :: RegPairEven : Odd = 0 ; break ; case ARMRI :: RegPairOdd : Odd = 1 ; break ; default : TargetRegisterInfo :: getRegAllocationHints ( VirtReg , Order , Hints , MF , VRM ) ; return ; } unsigned PairedPhys = 0 ; if ( VRM && VRM -> hasPhys ( Hint . second ) ) { PairedPhys = getPairedGPR ( VRM -> getPhys ( Hint . second ) , Odd , this ) ; if ( PairedPhys && MRI . isReserved ( PairedPhys ) ) PairedPhys = 0 ; } if ( PairedPhys && std :: find ( Order . begin ( ) , Order . end ( ) , PairedPhys ) != Order . end ( ) ) Hints . push_back ( PairedPhys ) ; for ( unsigned I = 0 , E = Order . size ( ) ; I != E ; ++ I ) { unsigned Reg = Order [ I ] ; if ( Reg == PairedPhys || ( getEncodingValue ( Reg ) & 1 ) != Odd ) continue ; unsigned Paired = getPairedGPR ( Reg , ! Odd , this ) ; if ( ! Paired || MRI . isReserved ( Paired ) ) continue ; Hints . push_back ( Reg ) ; } } </s>

Get a list of 'hint ' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg .


<s> static bool arc_handle_option ( size_t code , const char * arg , int value ATTRIBUTE_UNUSED ) { switch ( code ) { case OPT_mcpu_ : return strcmp ( arg , "base" ) == 0 || ARC_EXTENSION_CPU ( arg ) ; default : return true ; } } </s>


<s> static bool ix86_pic_register_p ( rtx x ) { if ( GET_CODE ( x ) == VALUE && CSELIB_VAL_PTR ( x ) ) return ( pic_offset_table_rtx && rtx_equal_for_cselib_p ( x , pic_offset_table_rtx ) ) ; else if ( GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNSPEC_SET_GOT ) return true ; else if ( ! REG_P ( x ) ) return false ; else if ( pic_offset_table_rtx ) { if ( REGNO ( x ) == REGNO ( pic_offset_table_rtx ) ) return true ; if ( HARD_REGISTER_P ( x ) && ! HARD_REGISTER_P ( pic_offset_table_rtx ) && ORIGINAL_REGNO ( x ) == REGNO ( pic_offset_table_rtx ) ) return true ; return false ; } else return REGNO ( x ) == PIC_OFFSET_TABLE_REGNUM ; } </s>

Return true if X is a representation of the PIC register . This copes with calls from ix86_find_base_term , where the register might have been replaced by a cselib value .


<s> const AMDGPUInstrInfo * getInstrInfo ( ) const override { return getSubtargetImpl ( ) -> getInstrInfo ( ) ; } </s>


Implement TARGET_SETUP_INCOMING_VARARGS . On C-Sky the copy from the argument registers to the stack is emitted by the prologue hooks , so here we just have to note how much stack space to save .


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & getSubtargetImpl ( ) -> getInstrItineraryData ( ) ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> const uint32_t * AArch64RegisterInfo :: getThisReturnPreservedMask ( CallingConv :: ID ) const { return CSR_AArch64_AAPCS_ThisReturn_RegMask ; } </s>

getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned ' is on an i32 first argument if the calling convention is one that can ( partially ) model this attribute with a preserved mask ( i.e .


<s> bool LC3RegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { return false ; } </s>

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot .


<s>
bool
X86DAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
SDValue
Op0
,
Op1
,
Op2
,
Op3
,
Op4
;
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_o
:
case
InlineAsm
::
Constraint_v
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_X
:
case
InlineAsm
::
Constraint_p
:
if
(
!
selectAddr
(
nullptr
,
Op
,
Op0
,
Op1
,
Op2
,
Op3
,
Op4
)
)
return
true
;
break
;
}
OutOps
.
push_back
(
Op0
)
;
OutOps
.
push_back
(
Op1
)
;
OutOps
.
push_back
(
Op2
)
;
OutOps
.
push_back
(
Op3
)
;
OutOps
.
push_back
(
Op4
)
;
return
false
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s>
StringRef
getPassName
(
)
const
override
{
return
"ARM MLA / MLS expansion pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void ARMPassConfig :: addIRPasses ( ) { if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( 1 , false , false , true , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < ARMSubtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST . isThumb1Only ( ) ; } ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> bool X86FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } unsigned FPReg = TRI -> getFrameRegister ( MF ) ; unsigned Opc = STI . is64Bit ( ) ? X86 :: POP64r : X86 :: POP32r ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; if ( Reg == FPReg ) continue ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static void aarch64_emit_unspec_cond ( rtx target , rtx_code code , machine_mode pred_mode , rtx pred , rtx op0 , rtx op1 ) { rtx unspec = aarch64_gen_unspec_cond ( code , pred_mode , pred , op0 , op1 ) ; emit_set_insn ( target , unspec ) ; } </s>

Emit an instruction : ( set TARGET ( unspec : PRED_MODE [ PRED OP0 OP1 ] UNSPEC_COND_ < X > ) ) where < X > is the operation associated with comparison CODE .


"Warning: Illegal instruction detected: "

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> const MCPhysReg * PPCRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const PPCSubtarget & Subtarget = MF -> getSubtarget < PPCSubtarget > ( ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: AnyReg ) { if ( Subtarget . hasVSX ( ) ) return CSR_64_AllRegs_VSX_SaveList ; if ( Subtarget . hasAltivec ( ) ) return CSR_64_AllRegs_Altivec_SaveList ; return CSR_64_AllRegs_SaveList ; } if ( Subtarget . isDarwinABI ( ) ) return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_SaveList : CSR_Darwin64_SaveList ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_SaveList : CSR_Darwin32_SaveList ) ; if ( TM . isPPC64 ( ) && MF -> getInfo < PPCFunctionInfo > ( ) -> isSplitCSR ( ) ) return CSR_SRV464_TLS_PE_SaveList ; bool SaveR2 = MF -> getRegInfo ( ) . isAllocatable ( PPC :: X2 ) ; return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? ( SaveR2 ? CSR_SVR464_R2_Altivec_SaveList : CSR_SVR464_Altivec_SaveList ) : ( SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList ) ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR432_Altivec_SaveList : CSR_SVR432_SaveList ) ; } </s>

PowerPC PPC PPC PPC PPC PPC PPC PPC::X2 PPC


<s>
static
void
microblaze_asm_trampoline_template
(
FILE
*
f
)
{
fprintf
(
f
,
"\tmfs r18, rpc\n"
)
;
fprintf
(
f
,
"\tlwi r3, r18, 16\n"
)
;
fprintf
(
f
,
"\tlwi r18, r18, 20\n"
)
;
fprintf
(
f
,
"\tbra r18\n"
)
;
}
</s>

Generate assembler code for constant parts of a trampoline .

microblaze
"\tmfs r18, rpc\n"
"\tlwi r3, r18, 16\n"
"\tlwi r18, r18, 20\n"
"\tbra r18\n"


<s> SDValue SystemZSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , SDLoc DL , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool IsVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { if ( IsVolatile ) return SDValue ( ) ; if ( auto * CSize = dyn_cast < ConstantSDNode > ( Size ) ) return emitMemMem ( DAG , DL , SystemZISD :: MVC , SystemZISD :: MVC_LOOP , Chain , Dst , Src , CSize -> getZExtValue ( ) ) ; return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .

SystemZ SystemZ SystemZISD::MVC SystemZISD::MVC_LOOP


<s> bool PPCInstrInfo :: findCommutedOpIndices ( MachineInstr & MI , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { int AltOpc = PPC :: getAltVSXFMAOpcode ( MI . getOpcode ( ) ) ; if ( AltOpc == - 1 ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , 2 , 3 ) ; } </s>

Returns true iff the routine could find two commutable operands in the given machine instruction .


<s> static inline int avr_popcount ( unsigned int val ) { int pop = 0 ; while ( val ) { val &= val - 1 ; pop ++ ; } return pop ; } </s>

Custom function to count number of set bits .


<s> bool NVPTXPassConfig :: addInstSelector ( ) { addPass ( createLowerAggrCopies ( ) ) ; addPass ( createSplitBBatBarPass ( ) ) ; addPass ( createAllocaHoisting ( ) ) ; addPass ( createNVPTXISelDag ( getNVPTXTargetMachine ( ) , getOptLevel ( ) ) ) ; addPass ( createVectorElementizePass ( getNVPTXTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static bool visium_legitimate_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ATTRIBUTE_UNUSED ) { return true ; } </s>

Return true if X is a legitimate constant for a MODE immediate operand . X is guaranteed to satisfy the CONSTANT_P predicate .


<s> MBlazeTargetLowering :: ConstraintType MBlazeTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'd' : case 'y' : case 'f' : return C_RegisterClass ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineBlockFrequencyInfo > ( ) ; AU . addPreserved < MachineBlockFrequencyInfo > ( ) ; AU . addRequired < LiveIntervals > ( ) ; AU . addPreserved < LiveIntervals > ( ) ; AU . addRequired < SlotIndexes > ( ) ; AU . addPreserved < SlotIndexes > ( ) ; AU . addRequired < LiveStacks > ( ) ; AU . addPreserved < LiveStacks > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; AU . addRequired < VirtRegMap > ( ) ; AU . addPreserved < VirtRegMap > ( ) ; AU . addRequired < LiveRegMatrix > ( ) ; AU . addPreserved < LiveRegMatrix > ( ) ; AU . addRequired < EdgeBundles > ( ) ; AU . addRequired < SpillPlacement > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return createLEGELFObjectWriter ( OS , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s>
const
char
*
getPassName
(
)
const
{
return
"Hexagon CFG Optimizer"
;
}
</s>


Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 CondBr Folding"
;
}
</s>


"Patmos DAG->DAG Pattern Instruction Selection"


<s> static HOST_WIDE_INT arg_area_size ( void ) { if ( crtl -> outgoing_args_size ) { if ( crtl -> outgoing_args_size >= FIXED_STACK_AREA ) return crtl -> outgoing_args_size ; else return FIXED_STACK_AREA ; } return 0 ; } </s>

Return the number of bytes we must reserve for outgoing arguments in the current function 's stack frame .


<s>
static
unsigned
getOpcode_EXTEND_VECTOR_INREG
(
unsigned
Opcode
)
{
switch
(
Opcode
)
{
case
ISD
::
ANY_EXTEND
:
case
ISD
::
ANY_EXTEND_VECTOR_INREG
:
return
ISD
::
ANY_EXTEND_VECTOR_INREG
;
case
ISD
::
ZERO_EXTEND
:
case
ISD
::
ZERO_EXTEND_VECTOR_INREG
:
return
ISD
::
ZERO_EXTEND_VECTOR_INREG
;
case
ISD
::
SIGN_EXTEND
:
case
ISD
::
SIGN_EXTEND_VECTOR_INREG
:
return
ISD
::
SIGN_EXTEND_VECTOR_INREG
;
}
llvm_unreachable
(
"Unknown opcode"
)
;
}
</s>

Convert * _EXTEND to * _EXTEND_VECTOR_INREG opcode .


<s> int ia64_function_arg_boundary ( enum machine_mode mode , tree type ) { if ( mode == TFmode && TARGET_HPUX && TARGET_ILP32 ) return PARM_BOUNDARY * 2 ; if ( type ) { if ( TYPE_ALIGN ( type ) > PARM_BOUNDARY ) return PARM_BOUNDARY * 2 ; else return PARM_BOUNDARY ; } if ( GET_MODE_BITSIZE ( mode ) > PARM_BOUNDARY ) return PARM_BOUNDARY * 2 ; else return PARM_BOUNDARY ; } </s>

Arguments with alignment larger than 8 bytes start at the next even boundary . On ILP32 HPUX , TFmode arguments start on next even boundary even though their normal alignment is 8 bytes . See ia64_function_arg .


"Branch with unknown extendable field type"

immediateExtend - Changes the instruction in place to one using an immediate extender .


<s>
const
MCFixupKindInfo
&
WebAssemblyAsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
WebAssembly
::
NumTargetFixupKinds
]
=
{
{
"fixup_sleb128_i32"
,
0
,
5
*
8
,
0
}
,
{
"fixup_sleb128_i64"
,
0
,
10
*
8
,
0
}
,
{
"fixup_uleb128_i32"
,
0
,
5
*
8
,
0
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> bool M88kCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned I = 0 ; for ( const auto & Arg : F . args ( ) ) { ArgInfo OrigArg { VRegs [ I ] , Arg . getType ( ) , I } ; setArgFlags ( OrigArg , I + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , F . getCallingConv ( ) ) ; ++ I ; } IncomingValueAssigner ArgAssigner ( CC_M88k ) ; FormalArgHandler ArgHandler ( MIRBuilder , MRI ) ; return determineAndHandleAssignments ( ArgHandler , ArgAssigner , SplitArgs , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> bool AMDGPUTargetLowering :: isKnownNeverNaNForTargetNode ( SDValue Op , const SelectionDAG & DAG , bool SNaN , unsigned Depth ) const { unsigned Opcode = Op . getOpcode ( ) ; switch ( Opcode ) { case AMDGPUISD :: FMIN_LEGACY : case AMDGPUISD :: FMAX_LEGACY : { if ( SNaN ) return true ; return false ; } case AMDGPUISD :: FMUL_LEGACY : case AMDGPUISD :: CVT_PKRTZ_F16_F32 : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( 0 ) , SNaN , Depth + 1 ) && DAG . isKnownNeverNaN ( Op . getOperand ( 1 ) , SNaN , Depth + 1 ) ; } case AMDGPUISD :: FMED3 : case AMDGPUISD :: FMIN3 : case AMDGPUISD :: FMAX3 : case AMDGPUISD :: FMAD_FTZ : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( 0 ) , SNaN , Depth + 1 ) && DAG . isKnownNeverNaN ( Op . getOperand ( 1 ) , SNaN , Depth + 1 ) && DAG . isKnownNeverNaN ( Op . getOperand ( 2 ) , SNaN , Depth + 1 ) ; } case AMDGPUISD :: CVT_F32_UBYTE0 : case AMDGPUISD :: CVT_F32_UBYTE1 : case AMDGPUISD :: CVT_F32_UBYTE2 : case AMDGPUISD :: CVT_F32_UBYTE3 : return true ; case AMDGPUISD :: RCP : case AMDGPUISD :: RSQ : case AMDGPUISD :: RCP_LEGACY : case AMDGPUISD :: RSQ_LEGACY : case AMDGPUISD :: RSQ_CLAMP : { if ( SNaN ) return true ; return false ; } case AMDGPUISD :: LDEXP : case AMDGPUISD :: FRACT : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( 0 ) , SNaN , Depth + 1 ) ; } case AMDGPUISD :: DIV_SCALE : case AMDGPUISD :: DIV_FMAS : case AMDGPUISD :: DIV_FIXUP : case AMDGPUISD :: TRIG_PREOP : return SNaN ; case AMDGPUISD :: SIN_HW : case AMDGPUISD :: COS_HW : { return SNaN ; } case ISD :: INTRINSIC_WO_CHAIN : { unsigned IntrinsicID = cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ; switch ( IntrinsicID ) { case Intrinsic :: amdgcn_cubeid : return true ; case Intrinsic :: amdgcn_frexp_mant : if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( 1 ) , SNaN , Depth + 1 ) ; default : return false ; } } default : return false ; } } </s>


<s> rtx loongarch_return_addr ( int count , rtx frame ATTRIBUTE_UNUSED ) { if ( count != 0 ) return const0_rtx ; return get_hard_reg_initial_val ( Pmode , RETURN_ADDR_REGNUM ) ; } </s>

Implement RETURN_ADDR_RTX . We do not support moving back to a previous frame .


<s> bool ARMBaseInstrInfo :: isSchedulingBoundary ( const MachineInstr * MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( MI -> isDebugValue ( ) ) return false ; if ( MI -> isTerminator ( ) || MI -> isLabel ( ) ) return true ; MachineBasicBlock :: const_iterator I = MI ; while ( ++ I != MBB -> end ( ) && I -> isDebugValue ( ) ) ; if ( I != MBB -> end ( ) && I -> getOpcode ( ) == ARM :: t2IT ) return true ; if ( ! MI -> isCall ( ) && MI -> definesRegister ( ARM :: SP ) ) return true ; return false ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> const char * X86TargetLowering :: LowerXConstraint ( EVT ConstraintVT ) const { if ( ConstraintVT . isFloatingPoint ( ) ) { if ( Subtarget . hasSSE1 ( ) ) return "x" ; } return TargetLowering :: LowerXConstraint ( ConstraintVT ) ; } </s>

Try to replace an X constraint , which matches anything , with another that has more specific requirements based on the type of the corresponding operand .


<s> virtual const HexagonRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> const LanaiMCExpr * LanaiMCExpr :: create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { return new ( Ctx ) LanaiMCExpr ( Kind , Expr ) ; } </s>


<s> static bool classof ( const ARMConstantPoolMBB * ) { return true ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> static rtx ia64_dfa_pre_cycle_insn ( void ) { return dfa_pre_cycle_insn ; } </s>

The following function returns the pseudo insn DFA_PRE_CYCLE_INSN used by the DFA insn scheduler .


<s> void RISCVFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const RISCVRegisterInfo * RI = STI . getRegisterInfo ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; Align StackAlign = getStackAlign ( ) ; if ( RI -> needsStackRealignment ( MF ) ) { Align MaxStackAlign = std :: max ( StackAlign , MFI . getMaxAlign ( ) ) ; FrameSize += ( MaxStackAlign . value ( ) - StackAlign . value ( ) ) ; StackAlign = MaxStackAlign ; } uint64_t MaxCallSize = alignTo ( MFI . getMaxCallFrameSize ( ) , StackAlign ) ; MFI . setMaxCallFrameSize ( MaxCallSize ) ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI . setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s> void WebAssemblyInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> void NVPTXPassConfig :: addIRPasses ( ) { disablePass ( & PrologEpilogCodeInserterID ) ; disablePass ( & MachineCopyPropagationID ) ; disablePass ( & TailDuplicateID ) ; addPass ( createNVVMReflectPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createNVPTXImageOptimizerPass ( ) ) ; addPass ( createNVPTXAssignValidGlobalNamesPass ( ) ) ; addPass ( createGenericToNVVMPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addMemorySpaceInferencePasses ( ) ; addStraightLineScalarOptimizationPasses ( ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addEarlyCSEOrGVNPass ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> virtual const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s>
bool
Mips16HardFloat
::
runOnModule
(
Module
&
M
)
{
DEBUG
(
errs
(
)
<<
"Run on Module Mips16HardFloat\n"
)
;
bool
Modified
=
false
;
for
(
Module
::
iterator
F
=
M
.
begin
(
)
,
E
=
M
.
end
(
)
;
F
!=
E
;
++
F
)
{
if
(
F
->
isDeclaration
(
)
||
F
->
hasFnAttribute
(
"mips16_fp_stub"
)
||
F
->
hasFnAttribute
(
"nomips16"
)
)
continue
;
Modified
|=
fixupFPReturnAndCall
(
*
F
,
&
M
,
Subtarget
)
;
FPParamVariant
V
=
whichFPParamVariantNeeded
(
*
F
)
;
if
(
V
!=
NoSig
)
{
Modified
=
true
;
createFPFnStub
(
F
,
&
M
,
V
,
Subtarget
)
;
}
}
return
Modified
;
}
</s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> int shmedia_cleanup_truncate ( rtx x ) { int n_changes = 0 ; subrtx_var_iterator :: array_type array ; FOR_EACH_SUBRTX_VAR ( iter , array , x , NONCONST ) { rtx x = * iter ; if ( GET_CODE ( x ) == TRUNCATE ) { rtx reg = XEXP ( x , 0 ) ; machine_mode reg_mode = GET_MODE ( reg ) ; if ( REG_P ( reg ) && GET_MODE_SIZE ( reg_mode ) > 8 ) { int offset = subreg_lowpart_offset ( DImode , reg_mode ) ; XEXP ( x , 0 ) = simplify_subreg ( DImode , reg , reg_mode , offset ) ; n_changes += 1 ; iter . skip_subrtxes ( ) ; } } } return n_changes ; } </s>

Look through X cleaning up truncates of registers that span multiple actual hard registers . Return the number of changes made .


<s> bool XNCMInstrInfo :: isUnpredicatedTerminator ( const MachineInstr * MI ) const { if ( ! MI -> isTerminator ( ) ) return false ; if ( MI -> isBranch ( ) && ! MI -> isBarrier ( ) ) return true ; if ( ! MI -> isPredicable ( ) ) return true ; return ! isPredicated ( MI ) ; } </s>

Returns true if the instruction is a terminator instruction that has not been predicated .


<s>
void
TLCS900InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
;
if
(
TLCS900
::
GR16RegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
TLCS900
::
MOV16rr
;
else
if
(
TLCS900
::
GR8RegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
TLCS900
::
MOV8rr
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> inline machine_mode function_instance :: vector_mode ( unsigned int i ) const { return type_suffix ( i ) . vector_mode ; } </s>

Return the machine_mode of the corresponding vector type .


<s> static rtx function_arg_record_value ( const_tree type , machine_mode mode , int slotno , int named , int regbase ) { HOST_WIDE_INT typesize = int_size_in_bytes ( type ) ; struct function_arg_record_value_parms parms ; unsigned int nregs ; parms . ret = NULL_RTX ; parms . slotno = slotno ; parms . named = named ; parms . regbase = regbase ; parms . stack = 0 ; parms . nregs = 0 ; parms . intoffset = 0 ; function_arg_record_value_1 ( type , 0 , & parms , false ) ; if ( parms . intoffset != - 1 ) { unsigned int startbit , endbit ; int intslots , this_slotno ; startbit = parms . intoffset & - BITS_PER_WORD ; endbit = ( typesize * BITS_PER_UNIT + BITS_PER_WORD - 1 ) & - BITS_PER_WORD ; intslots = ( endbit - startbit ) / BITS_PER_WORD ; this_slotno = slotno + parms . intoffset / BITS_PER_WORD ; if ( intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno ) { intslots = MAX ( 0 , SPARC_INT_ARG_MAX - this_slotno ) ; parms . stack = 1 ; } parms . nregs += intslots ; } nregs = parms . nregs ; if ( nregs == 0 ) { if ( typesize <= 0 ) { return gen_rtx_REG ( mode , regbase ) ; } else { nregs = ( typesize + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } if ( nregs + slotno > SPARC_INT_ARG_MAX ) nregs = SPARC_INT_ARG_MAX - slotno ; } gcc_assert ( nregs != 0 ) ; parms . ret = gen_rtx_PARALLEL ( mode , rtvec_alloc ( parms . stack + nregs ) ) ; if ( parms . stack ) XVECEXP ( parms . ret , 0 , 0 ) = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; parms . nregs = 0 ; parms . intoffset = 0 ; function_arg_record_value_2 ( type , 0 , & parms , false ) ; function_arg_record_value_3 ( typesize * BITS_PER_UNIT , & parms ) ; gcc_assert ( parms . nregs == nregs ) ; return parms . ret ; } </s>

Used by function_arg and sparc_function_value_1 to implement the complex conventions of the 64-bit ABI for passing and returning structures . Return an expression valid as a return value for the FUNCTION_ARG and TARGET_FUNCTION_VALUE . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . MODE is the argument 's machine mode . SLOTNO is the index number of the argument 's slot in the parameter array . NAMED is true if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . REGBASE is the regno of the base register for the parameter array .


<s> SDValue NVPTXTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { CodeGenOpt :: Level OptLevel = getTargetMachine ( ) . getOptLevel ( ) ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : case ISD :: FADD : return PerformADDCombine ( N , DCI , nvptxSubtarget , OptLevel ) ; case ISD :: MUL : return PerformMULCombine ( N , DCI , OptLevel ) ; case ISD :: SHL : return PerformSHLCombine ( N , DCI , OptLevel ) ; case ISD :: AND : return PerformANDCombine ( N , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

NVPTX NVPTX ISD::ADD ISD::FADD ISD::MUL ISD::SHL ISD::AND


<s> int tilepro_adjust_insn_length ( rtx_insn * insn , int length ) { machine_mode mode = GET_MODE ( insn ) ; if ( mode == SImode ) return 0 ; return length ; } </s>

Return the length of INSN . LENGTH is the initial length computed by attributes in the machine-description file . This is where we account for bundles .


<s> void X86InstrInfo :: buildOutlinedFrame ( MachineBasicBlock & MBB , MachineFunction & MF , const outliner :: TargetCostInfo & TCI ) const { if ( TCI . FrameConstructionID == MachineOutlinerTailCall ) return ; MachineInstr * retq = BuildMI ( MF , DebugLoc ( ) , get ( X86 :: RETQ ) ) ; MBB . insert ( MBB . end ( ) , retq ) ; } </s>

Insert a custom frame for outlined functions .


<s> void GCNSubtarget :: adjustSchedDependency ( SUnit * Src , SUnit * Dst , SDep & Dep ) const { if ( Dep . getKind ( ) != SDep :: Kind :: Data || ! Dep . getReg ( ) || ! Src -> isInstr ( ) || ! Dst -> isInstr ( ) ) return ; MachineInstr * SrcI = Src -> getInstr ( ) ; MachineInstr * DstI = Dst -> getInstr ( ) ; if ( SrcI -> isBundle ( ) ) { const SIRegisterInfo * TRI = getRegisterInfo ( ) ; auto Reg = Dep . getReg ( ) ; MachineBasicBlock :: const_instr_iterator I ( SrcI -> getIterator ( ) ) ; MachineBasicBlock :: const_instr_iterator E ( SrcI -> getParent ( ) -> instr_end ( ) ) ; unsigned Lat = 0 ; for ( ++ I ; I != E && I -> isBundledWithPred ( ) ; ++ I ) { if ( I -> modifiesRegister ( Reg , TRI ) ) Lat = InstrInfo . getInstrLatency ( getInstrItineraryData ( ) , * I ) ; else if ( Lat ) -- Lat ; } Dep . setLatency ( Lat ) ; } else if ( DstI -> isBundle ( ) ) { const SIRegisterInfo * TRI = getRegisterInfo ( ) ; auto Reg = Dep . getReg ( ) ; MachineBasicBlock :: const_instr_iterator I ( DstI -> getIterator ( ) ) ; MachineBasicBlock :: const_instr_iterator E ( DstI -> getParent ( ) -> instr_end ( ) ) ; unsigned Lat = InstrInfo . getInstrLatency ( getInstrItineraryData ( ) , * SrcI ) ; for ( ++ I ; I != E && I -> isBundledWithPred ( ) && Lat ; ++ I ) { if ( I -> readsRegister ( Reg , TRI ) ) break ; -- Lat ; } Dep . setLatency ( Lat ) ; } } </s>

Perform target specific adjustments to the latency of a schedule dependency .


<s>
bool
NVPTXAsmPrinter
::
doInitialization
(
Module
&
M
)
{
StringRef
TT
=
TM
.
getTargetTriple
(
)
;
StringRef
CPU
=
TM
.
getTargetCPU
(
)
;
StringRef
FS
=
TM
.
getTargetFeatureString
(
)
;
const
NVPTXTargetMachine
&
NTM
=
static_cast
<
const
NVPTXTargetMachine
&
>
(
TM
)
;
const
NVPTXSubtarget
STI
(
TT
,
CPU
,
FS
,
NTM
)
;
SmallString
<
128
>
Str1
;
raw_svector_ostream
OS1
(
Str1
)
;
MMI
=
getAnalysisIfAvailable
<
MachineModuleInfo
>
(
)
;
MMI
->
AnalyzeModule
(
M
)
;
const_cast
<
TargetLoweringObjectFile
&
>
(
getObjFileLowering
(
)
)
.
Initialize
(
OutContext
,
TM
)
;
Mang
=
new
Mangler
(
TM
.
getDataLayout
(
)
)
;
emitHeader
(
M
,
OS1
,
STI
)
;
OutStreamer
.
EmitRawText
(
OS1
.
str
(
)
)
;
if
(
!
M
.
getModuleInlineAsm
(
)
.
empty
(
)
)
{
OutStreamer
.
AddComment
(
"Start of file scope inline assembly"
)
;
OutStreamer
.
AddBlankLine
(
)
;
OutStreamer
.
EmitRawText
(
StringRef
(
M
.
getModuleInlineAsm
(
)
)
)
;
OutStreamer
.
AddBlankLine
(
)
;
OutStreamer
.
AddComment
(
"End of file scope inline assembly"
)
;
OutStreamer
.
AddBlankLine
(
)
;
}
if
(
Triple
(
TM
.
getTargetTriple
(
)
)
.
getOS
(
)
!=
Triple
::
NVCL
)
recordAndEmitFilenames
(
M
)
;
GlobalsEmitted
=
false
;
return
false
;
}
</s>

Set up the AsmPrinter when we are working on a new module .

NVPTX
NVPTX
NVPTX
NVPTX
NVPTX
128
"Start of file scope inline assembly"
"End of file scope inline assembly"


Get a const_iterator to the end of the symbol table .


<s> MachineBasicBlock :: iterator AArch64InstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , const MachineOutlinerInfo & MInfo ) const { if ( MInfo . CallConstructionID == MachineOutlinerTailCall ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: TCRETURNdi ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) . addImm ( 0 ) ) ; return It ; } if ( MInfo . CallConstructionID == MachineOutlinerNoLRSave || MInfo . CallConstructionID == MachineOutlinerThunk ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: BL ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; return It ; } MachineBasicBlock :: iterator CallPt ; MachineInstr * STRXpre = BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: STRXpre ) ) . addReg ( AArch64 :: SP , RegState :: Define ) . addReg ( AArch64 :: LR ) . addReg ( AArch64 :: SP ) . addImm ( - 16 ) ; It = MBB . insert ( It , STRXpre ) ; It ++ ; It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: BL ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; CallPt = It ; It ++ ; MachineInstr * LDRXpost = BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: LDRXpost ) ) . addReg ( AArch64 :: SP , RegState :: Define ) . addReg ( AArch64 :: LR , RegState :: Define ) . addReg ( AArch64 :: SP ) . addImm ( 16 ) ; It = MBB . insert ( It , LDRXpost ) ; return CallPt ; } </s>

Insert a call to an outlined function into the program .


<s> unsigned internalKnownBits ( ) const { unsigned Bits = Unalign ? Unalign : KnownBits ; if ( Size & ( ( 1u << Bits ) - 1 ) ) Bits = CountTrailingZeros_32 ( Size ) ; return Bits ; } </s>

Compute the number of known offset bits internally to this block .


<s>
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
MipsTargetLowering
::
getRegForInlineAsmConstraint
(
const
std
::
string
&
Constraint
,
EVT
VT
)
const
{
if
(
Constraint
.
size
(
)
==
1
)
{
switch
(
Constraint
[
0
]
)
{
case
'd'
:
case
'y'
:
case
'r'
:
if
(
VT
==
MVT
::
i32
||
VT
==
MVT
::
i16
||
VT
==
MVT
::
i8
)
return
std
::
make_pair
(
0U
,
&
Mips
::
CPURegsRegClass
)
;
if
(
VT
==
MVT
::
i64
&&
!
HasMips64
)
return
std
::
make_pair
(
0U
,
&
Mips
::
CPURegsRegClass
)
;
if
(
VT
==
MVT
::
i64
&&
HasMips64
)
return
std
::
make_pair
(
0U
,
&
Mips
::
CPU64RegsRegClass
)
;
return
std
::
make_pair
(
0u
,
static_cast
<
const
TargetRegisterClass
*
>
(
0
)
)
;
case
'f'
:
if
(
VT
==
MVT
::
f32
)
return
std
::
make_pair
(
0U
,
&
Mips
::
FGR32RegClass
)
;
if
(
(
VT
==
MVT
::
f64
)
&&
(
!
Subtarget
->
isSingleFloat
(
)
)
)
{
if
(
Subtarget
->
isFP64bit
(
)
)
return
std
::
make_pair
(
0U
,
&
Mips
::
FGR64RegClass
)
;
return
std
::
make_pair
(
0U
,
&
Mips
::
AFGR64RegClass
)
;
}
break
;
case
'c'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
(
unsigned
)
Mips
::
T9
,
&
Mips
::
CPURegsRegClass
)
;
assert
(
VT
==
MVT
::
i64
&&
"Unexpected type."
)
;
return
std
::
make_pair
(
(
unsigned
)
Mips
::
T9_64
,
&
Mips
::
CPU64RegsRegClass
)
;
case
'l'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
(
unsigned
)
Mips
::
LO
,
&
Mips
::
HILORegClass
)
;
return
std
::
make_pair
(
(
unsigned
)
Mips
::
LO64
,
&
Mips
::
HILO64RegClass
)
;
case
'x'
:
return
std
::
make_pair
(
0u
,
static_cast
<
const
TargetRegisterClass
*
>
(
0
)
)
;
}
}
return
TargetLowering
::
getRegForInlineAsmConstraint
(
Constraint
,
VT
)
;
}
</s>

Given a physical register constraint ( e.g .


<s>
const
char
*
mcore_output_andn
(
rtx
insn
ATTRIBUTE_UNUSED
,
rtx
operands
[
]
)
{
HOST_WIDE_INT
x
,
y
;
rtx
out_operands
[
3
]
;
const
char
*
load_op
;
char
buf
[
256
]
;
int
trick_no
;
trick_no
=
try_constant_tricks
(
INTVAL
(
operands
[
1
]
)
,
&
x
,
&
y
)
;
gcc_assert
(
trick_no
==
2
)
;
out_operands
[
0
]
=
operands
[
0
]
;
out_operands
[
1
]
=
GEN_INT
(
x
)
;
out_operands
[
2
]
=
operands
[
2
]
;
if
(
x
>=
0
&&
x
<=
127
)
load_op
=
"movi\t%0,%1"
;
else
if
(
CONST_OK_FOR_M
(
x
)
)
load_op
=
"bgeni\t%0,%P1"
;
else
if
(
CONST_OK_FOR_N
(
x
)
)
load_op
=
"bmaski\t%0,%N1"
;
else
{
load_op
=
"BADMOVI-andn\t%0, %1"
;
gcc_unreachable
(
)
;
}
sprintf
(
buf
,
"%s\n\tandn\t%%2,%%0"
,
load_op
)
;
output_asm_insn
(
buf
,
out_operands
)
;
return
""
;
}
</s>

Outputs the peephole for moving a constant that gets not'ed followed by an and ( i.e . combine the not and the and into andn ) . BRC


<s> bool runOnMachineFunction ( MachineFunction & MF ) { const PatmosMachineFunctionInfo * PMFI = MF . getInfo < PatmosMachineFunctionInfo > ( ) ; bool Changed = false ; if ( MinSubfunctionAlignment > MF . getAlignment ( ) . value ( ) ) { MF . ensureAlignment ( Align ( MinSubfunctionAlignment ) ) ; Changed = true ; } for ( MachineFunction :: iterator i = MF . begin ( ) , ie = MF . end ( ) ; i != ie ; ++ i ) { unsigned align ; if ( PMFI -> isMethodCacheRegionEntry ( & * i ) ) { align = MinSubfunctionAlignment ; } else { align = i -> getAlignment ( ) . value ( ) ; } if ( align > i -> getAlignment ( ) . value ( ) ) { i -> setAlignment ( Align ( align ) ) ; Changed = true ; } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> void VideocoreInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << StringRef ( getRegisterName ( RegNo ) ) . lower ( ) ; } </s>


<s> static inline bool has_func_attr ( const_tree decl , const char * func_attr ) { if ( decl == NULL_TREE ) decl = current_function_decl ; return lookup_attribute ( func_attr , DECL_ATTRIBUTES ( decl ) ) != NULL_TREE ; } </s>

Returns true if the provided function has the specified attribute .


<s> bool X86CallLowering :: splitToValueTypes ( const ArgInfo & OrigArg , SmallVectorImpl < ArgInfo > & SplitArgs , const DataLayout & DL , MachineRegisterInfo & MRI , SplitArgTy PerformArgSplit ) const { const X86TargetLowering & TLI = * getTLI < X86TargetLowering > ( ) ; LLVMContext & Context = OrigArg . Ty -> getContext ( ) ; SmallVector < EVT , 4 > SplitVTs ; SmallVector < uint64_t , 4 > Offsets ; ComputeValueVTs ( TLI , DL , OrigArg . Ty , SplitVTs , & Offsets , 0 ) ; if ( OrigArg . Ty -> isVoidTy ( ) ) return true ; EVT VT = SplitVTs [ 0 ] ; unsigned NumParts = TLI . getNumRegisters ( Context , VT ) ; if ( NumParts == 1 ) { SplitArgs . emplace_back ( OrigArg . Reg , VT . getTypeForEVT ( Context ) , OrigArg . Flags , OrigArg . IsFixed ) ; return true ; } SmallVector < unsigned , 8 > SplitRegs ; EVT PartVT = TLI . getRegisterType ( Context , VT ) ; Type * PartTy = PartVT . getTypeForEVT ( Context ) ; for ( unsigned i = 0 ; i < NumParts ; ++ i ) { ArgInfo Info = ArgInfo { MRI . createGenericVirtualRegister ( getLLTForType ( * PartTy , DL ) ) , PartTy , OrigArg . Flags } ; SplitArgs . push_back ( Info ) ; SplitRegs . push_back ( Info . Reg ) ; } PerformArgSplit ( SplitRegs ) ; return true ; } </s>

Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> int mcore_byte_offset ( unsigned int mask ) { if ( mask == 0x00ffffffL ) return 0 ; else if ( mask == 0xff00ffffL ) return 1 ; else if ( mask == 0xffff00ffL ) return 2 ; else if ( mask == 0xffffff00L ) return 3 ; return - 1 ; } </s>


<s> static void addInst ( MachineInstr * MI ) { Blocks . back ( ) . insert ( MI ) ; PredicatedInsts . emplace ( MI , std :: make_unique < PredicatedMI > ( MI , CurrentPredicates ) ) ; } </s>


<s> static rtx aarch64_gen_storewb_pair ( machine_mode mode , rtx base , rtx reg , rtx reg2 , HOST_WIDE_INT adjustment ) { switch ( mode ) { case E_DImode : return gen_storewb_pairdi_di ( base , base , reg , reg2 , GEN_INT ( - adjustment ) , GEN_INT ( UNITS_PER_WORD - adjustment ) ) ; case E_DFmode : return gen_storewb_pairdf_di ( base , base , reg , reg2 , GEN_INT ( - adjustment ) , GEN_INT ( UNITS_PER_WORD - adjustment ) ) ; case E_TFmode : return gen_storewb_pairtf_di ( base , base , reg , reg2 , GEN_INT ( - adjustment ) , GEN_INT ( UNITS_PER_VREG - adjustment ) ) ; default : gcc_unreachable ( ) ; } } </s>

Generate and return an instruction to store the pair of registers REG and REG2 of mode MODE to location BASE with write-back adjusting the stack location BASE by ADJUSTMENT .


<s>
MachineBasicBlock
*
XCoreTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
const
TargetInstrInfo
&
TII
=
*
getTargetMachine
(
)
.
getInstrInfo
(
)
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
assert
(
(
MI
->
getOpcode
(
)
==
XCore
::
SELECT_CC
)
&&
"Unexpected instr type to insert"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
It
=
BB
;
++
It
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
sinkMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
F
->
insert
(
It
,
copy0MBB
)
;
F
->
insert
(
It
,
sinkMBB
)
;
sinkMBB
->
splice
(
sinkMBB
->
begin
(
)
,
BB
,
std
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
BB
->
end
(
)
)
;
sinkMBB
->
transferSuccessorsAndUpdatePHIs
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
sinkMBB
)
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
XCore
::
BRFT_lru6
)
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
sinkMBB
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
sinkMBB
;
BuildMI
(
*
BB
,
BB
->
begin
(
)
,
dl
,
TII
.
get
(
XCore
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
3
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
MI
->
eraseFromParent
(
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s>
void
pru_function_profiler
(
FILE
*
file
,
int
labelno
ATTRIBUTE_UNUSED
)
{
fprintf
(
file
,
"\tmov\tr1, ra\n"
)
;
fprintf
(
file
,
"\tcall\t_mcount\n"
)
;
fprintf
(
file
,
"\tmov\tra, r1\n"
)
;
}
</s>

pru
"\tmov\tr1, ra\n"
"\tcall\t_mcount\n"
"\tmov\tra, r1\n"


<s> const DataLayout * getDataLayout ( ) const override { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> bool AVRFrameLowering :: hasFP ( const MachineFunction & MF ) const { const AVRMachineFunctionInfo * FuncInfo = MF . getInfo < AVRMachineFunctionInfo > ( ) ; return ( FuncInfo -> getHasSpills ( ) || FuncInfo -> getHasAllocas ( ) || FuncInfo -> getHasStackArgs ( ) || MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void CAHPFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( hasFP ( MF ) ) { SavedRegs . set ( CAHP :: X0 ) ; SavedRegs . set ( CAHP :: X2 ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> SDValue PPCTargetLowering :: BuildSDIVPow2 ( SDNode * N , const APInt & Divisor , SelectionDAG & DAG , std :: vector < SDNode * > * Created ) const { EVT VT = N -> getValueType ( 0 ) ; if ( VT == MVT :: i64 && ! Subtarget . isPPC64 ( ) ) return SDValue ( ) ; if ( ( VT != MVT :: i32 && VT != MVT :: i64 ) || ! ( Divisor . isPowerOf2 ( ) || ( - Divisor ) . isPowerOf2 ( ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( 0 ) ; bool IsNegPow2 = ( - Divisor ) . isPowerOf2 ( ) ; unsigned Lg2 = ( IsNegPow2 ? - Divisor : Divisor ) . countTrailingZeros ( ) ; SDValue ShiftAmt = DAG . getConstant ( Lg2 , DL , VT ) ; SDValue Op = DAG . getNode ( PPCISD :: SRA_ADDZE , DL , VT , N0 , ShiftAmt ) ; if ( Created ) Created -> push_back ( Op . getNode ( ) ) ; if ( IsNegPow2 ) { Op = DAG . getNode ( ISD :: SUB , DL , VT , DAG . getConstant ( 0 , DL , VT ) , Op ) ; if ( Created ) Created -> push_back ( Op . getNode ( ) ) ; } return Op ; } </s>

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators .


<s>
void
AMDGPUInstPrinter
::
printOffset
(
const
MCInst
*
MI
,
unsigned
OpNo
,
const
MCSubtargetInfo
&
STI
,
raw_ostream
&
O
)
{
uint16_t
Imm
=
MI
->
getOperand
(
OpNo
)
.
getImm
(
)
;
if
(
Imm
!=
0
)
{
O
<<
(
(
OpNo
==
0
)
"offset:"
:
" offset:"
)
;
printU16ImmDecOperand
(
MI
,
OpNo
,
O
)
;
}
}
</s>

This is just convenient handler for printing offsets .


<s> static int epiphany_memory_move_cost ( machine_mode mode , reg_class_t rclass ATTRIBUTE_UNUSED , bool in ATTRIBUTE_UNUSED ) { return GET_MODE_CLASS ( mode ) == MODE_INT ? 3 : 4 ; } </s>

Compute the cost of moving data between registers and memory . For integer , load latency is twice as long as register-register moves , but issue pich is the same . For floating point , load latency is three times as much as a reg-reg move .


"built-in function %qE not supported for MIPS16"

Expand builtin functions . This is called from TARGET_EXPAND_BUILTIN .


<s> bool AArch64RegisterInfo :: shouldCoalesce ( MachineInstr * MI , const TargetRegisterClass * SrcRC , unsigned SubReg , const TargetRegisterClass * DstRC , unsigned DstSubReg , const TargetRegisterClass * NewRC , LiveIntervals & LIS ) const { if ( MI -> isCopy ( ) && ( ( DstRC -> getID ( ) == AArch64 :: GPR64RegClassID ) || ( DstRC -> getID ( ) == AArch64 :: GPR64commonRegClassID ) ) && MI -> getOperand ( 0 ) . getSubReg ( ) && MI -> getOperand ( 1 ) . getSubReg ( ) ) return false ; return true ; } </s>


<s> const Nios2RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


Returns a extern , comdat VAR_DECL of type TYPE and name NAME .


"Can only insert epilogue into returning blocks"

"Expected to see callee-save register restore code"


<s> static scalar_int_mode aarch64_sve_container_int_mode ( machine_mode mode ) { return int_mode_for_size ( aarch64_sve_container_bits ( mode ) , 0 ) . require ( ) ; } </s>

Return an integer element mode that contains exactly aarch64_sve_container_bits ( MODE ) bits . This is wider than aarch64_sve_element_int_mode if MODE is a partial vector , otherwise it 's the same .


<s> void PPCRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( PerformTailCallOpt && I -> getOpcode ( ) == PPC :: ADJCALLSTACKUP ) { if ( int CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { bool is64Bit = Subtarget . isPPC64 ( ) ; CalleeAmt *= - 1 ; unsigned StackReg = is64Bit ? PPC :: X1 : PPC :: R1 ; unsigned TmpReg = is64Bit ? PPC :: X0 : PPC :: R0 ; unsigned ADDIInstr = is64Bit ? PPC :: ADDI8 : PPC :: ADDI ; unsigned ADDInstr = is64Bit ? PPC :: ADD8 : PPC :: ADD4 ; unsigned LISInstr = is64Bit ? PPC :: LIS8 : PPC :: LIS ; unsigned ORIInstr = is64Bit ? PPC :: ORI8 : PPC :: ORI ; MachineInstr * MI = I ; DebugLoc dl = MI -> getDebugLoc ( ) ; if ( isInt16 ( CalleeAmt ) ) { BuildMI ( MBB , I , dl , TII . get ( ADDIInstr ) , StackReg ) . addReg ( StackReg ) . addImm ( CalleeAmt ) ; } else { MachineBasicBlock :: iterator MBBI = I ; BuildMI ( MBB , MBBI , dl , TII . get ( LISInstr ) , TmpReg ) . addImm ( CalleeAmt >> 16 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ORIInstr ) , TmpReg ) . addReg ( TmpReg , false , false , true ) . addImm ( CalleeAmt & 0xFFFF ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ADDInstr ) ) . addReg ( StackReg ) . addReg ( StackReg ) . addReg ( TmpReg ) ; } } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> StringRef getPassName ( ) const override { return SNES_EXPAND_PSEUDO_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


getTargetNodeName - This method returns the name of a target specific


<s>
MachineBasicBlock
*
SparcTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
const
TargetInstrInfo
&
TII
=
*
getTargetMachine
(
)
.
getInstrInfo
(
)
;
unsigned
BROpcode
;
unsigned
CC
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
assert
(
0
&&
"Unknown SELECT_CC!"
)
;
case
SP
::
SELECT_CC_Int_ICC
:
case
SP
::
SELECT_CC_FP_ICC
:
case
SP
::
SELECT_CC_DFP_ICC
:
BROpcode
=
SP
::
BCOND
;
break
;
case
SP
::
SELECT_CC_Int_FCC
:
case
SP
::
SELECT_CC_FP_FCC
:
case
SP
::
SELECT_CC_DFP_FCC
:
BROpcode
=
SP
::
FBCOND
;
break
;
}
CC
=
(
SPCC
::
CondCodes
)
MI
->
getOperand
(
3
)
.
getImm
(
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
It
=
BB
;
++
It
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
sinkMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
BROpcode
)
)
.
addMBB
(
sinkMBB
)
.
addImm
(
CC
)
;
F
->
insert
(
It
,
copy0MBB
)
;
F
->
insert
(
It
,
sinkMBB
)
;
sinkMBB
->
transferSuccessors
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
sinkMBB
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
SP
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
F
->
DeleteMachineInstr
(
MI
)
;
return
BB
;
}
</s>


<s> TargetPassConfig * VETargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new VEPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> static machine_mode ix86_get_mask_mode ( unsigned nunits , unsigned vector_size ) { unsigned elem_size = vector_size / nunits ; if ( ( TARGET_AVX512F && vector_size == 64 ) || ( TARGET_AVX512VL && ( vector_size == 32 || vector_size == 16 ) ) ) { if ( elem_size == 4 || elem_size == 8 || TARGET_AVX512BW ) return smallest_mode_for_size ( nunits , MODE_INT ) ; } machine_mode elem_mode = smallest_mode_for_size ( elem_size * BITS_PER_UNIT , MODE_INT ) ; gcc_assert ( elem_size * nunits == vector_size ) ; return mode_for_vector ( elem_mode , nunits ) ; } </s>

Implemenation of targetm.vectorize.get_mask_mode .


<s> void XCoreTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; DataSection = Ctx . getELFSection ( ".dp.data" , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_ALLOC | MCSectionELF :: SHF_WRITE | MCSectionELF :: XCORE_SHF_DP_SECTION , SectionKind :: getDataRel ( ) ) ; BSSSection = Ctx . getELFSection ( ".dp.bss" , MCSectionELF :: SHT_NOBITS , MCSectionELF :: SHF_ALLOC | MCSectionELF :: SHF_WRITE | MCSectionELF :: XCORE_SHF_DP_SECTION , SectionKind :: getBSS ( ) ) ; MergeableConst4Section = Ctx . getELFSection ( ".cp.rodata.cst4" , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_ALLOC | MCSectionELF :: SHF_MERGE | MCSectionELF :: XCORE_SHF_CP_SECTION , SectionKind :: getMergeableConst4 ( ) ) ; MergeableConst8Section = Ctx . getELFSection ( ".cp.rodata.cst8" , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_ALLOC | MCSectionELF :: SHF_MERGE | MCSectionELF :: XCORE_SHF_CP_SECTION , SectionKind :: getMergeableConst8 ( ) ) ; MergeableConst16Section = Ctx . getELFSection ( ".cp.rodata.cst16" , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_ALLOC | MCSectionELF :: SHF_MERGE | MCSectionELF :: XCORE_SHF_CP_SECTION , SectionKind :: getMergeableConst16 ( ) ) ; TLSDataSection = DataSection ; TLSBSSSection = BSSSection ; ReadOnlySection = Ctx . getELFSection ( ".cp.rodata" , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_ALLOC | MCSectionELF :: XCORE_SHF_CP_SECTION , SectionKind :: getReadOnlyWithRel ( ) ) ; DataRelSection = DataRelLocalSection = DataSection ; DataRelROSection = DataRelROLocalSection = ReadOnlySection ; } </s>

This method must be called before any actual lowering is done .


<s> const char * RISCVTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( RISCVISD :: NodeType ) Opcode ) { case RISCVISD :: FIRST_NUMBER : break ; case RISCVISD :: RET_FLAG : return "RISCVISD::RET_FLAG" ; case RISCVISD :: URET_FLAG : return "RISCVISD::URET_FLAG" ; case RISCVISD :: SRET_FLAG : return "RISCVISD::SRET_FLAG" ; case RISCVISD :: MRET_FLAG : return "RISCVISD::MRET_FLAG" ; case RISCVISD :: CALL : return "RISCVISD::CALL" ; case RISCVISD :: SELECT_CC : return "RISCVISD::SELECT_CC" ; case RISCVISD :: BuildPairF64 : return "RISCVISD::BuildPairF64" ; case RISCVISD :: SplitF64 : return "RISCVISD::SplitF64" ; case RISCVISD :: TAIL : return "RISCVISD::TAIL" ; case RISCVISD :: SLLW : return "RISCVISD::SLLW" ; case RISCVISD :: SRAW : return "RISCVISD::SRAW" ; case RISCVISD :: SRLW : return "RISCVISD::SRLW" ; case RISCVISD :: DIVW : return "RISCVISD::DIVW" ; case RISCVISD :: DIVUW : return "RISCVISD::DIVUW" ; case RISCVISD :: REMUW : return "RISCVISD::REMUW" ; } return nullptr ; } </s>


<s>
SDValue
AMDGPUTargetLowering
::
LowerCall
(
CallLoweringInfo
&
CLI
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SDValue
Callee
=
CLI
.
Callee
;
SelectionDAG
&
DAG
=
CLI
.
DAG
;
const
Function
&
Fn
=
*
DAG
.
getMachineFunction
(
)
.
getFunction
(
)
;
StringRef
FuncName
(
"<unknown>"
)
;
if
(
const
ExternalSymbolSDNode
*
G
=
dyn_cast
<
ExternalSymbolSDNode
>
(
Callee
)
)
FuncName
=
G
->
getSymbol
(
)
;
else
if
(
const
GlobalAddressSDNode
*
G
=
dyn_cast
<
GlobalAddressSDNode
>
(
Callee
)
)
FuncName
=
G
->
getGlobal
(
)
->
getName
(
)
;
DiagnosticInfoUnsupported
NoCalls
(
Fn
,
"unsupported call to function "
+
FuncName
,
CLI
.
DL
.
getDebugLoc
(
)
)
;
DAG
.
getContext
(
)
->
diagnose
(
NoCalls
)
;
if
(
!
CLI
.
IsTailCall
)
{
for
(
unsigned
I
=
0
,
E
=
CLI
.
Ins
.
size
(
)
;
I
!=
E
;
++
I
)
InVals
.
push_back
(
DAG
.
getUNDEF
(
CLI
.
Ins
[
I
]
.
VT
)
)
;
}
return
DAG
.
getEntryNode
(
)
;
}
</s>

This hook must be implemented to lower calls into the specified DAG .

AMDGPU
AMDGPU
"<unknown>"
"unsupported call to function "
0


"TVM doesn't support non-C calling conventions"

"TVM hasn't implemented inalloca results"

"TVM hasn't implemented cons regs results"

"TVM hasn't implemented cons regs last results"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static int ia64_reloc_rw_mask ( void ) { return flag_pic ? 3 : 2 ; } </s>

For others , relax this so that relocations to local data goes in read-only segments , but we still can not allow global relocations in read-only segments .


<s> static rtx rs6000_emit_vector_compare_inner ( enum rtx_code code , rtx op0 , rtx op1 ) { rtx mask ; machine_mode mode = GET_MODE ( op0 ) ; switch ( code ) { default : break ; case GE : if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) return NULL_RTX ; case EQ : case GT : case GTU : case ORDERED : case UNORDERED : case UNEQ : case LTGT : mask = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( mask , gen_rtx_fmt_ee ( code , mode , op0 , op1 ) ) ) ; return mask ; } return NULL_RTX ; } </s>

Return insn for VSX or Altivec comparisons .


<s>
bool
AMDGPULegalizerInfo
::
legalizeKernargMemParameter
(
MachineInstr
&
MI
,
MachineIRBuilder
&
B
,
uint64_t
Offset
,
Align
Alignment
)
const
{
Register
DstReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
assert
(
B
.
getMRI
(
)
->
getType
(
DstReg
)
==
LLT
::
scalar
(
32
)
&&
"unexpected kernarg parameter type"
)
;
Register
Ptr
=
getKernargParameterPtr
(
B
,
Offset
)
;
MachinePointerInfo
PtrInfo
(
AMDGPUAS
::
CONSTANT_ADDRESS
)
;
B
.
buildLoad
(
DstReg
,
Ptr
,
PtrInfo
,
Align
(
4
)
,
MachineMemOperand
::
MODereferenceable
|
MachineMemOperand
::
MOInvariant
)
;
MI
.
eraseFromParent
(
)
;
return
true
;
}
</s>

Legalize a value that 's loaded from kernel arguments .


"Couldn't locate library: lib%s.exe, lib%s.a or lib%s.olb\n"

Given a library name NAME , i.e . foo , Look for libfoo.lib and then libfoo.a in the set of directories we are allowed to search in . May return NULL if the library can be discarded .


"instructions, but the target does not support ARM mode execution."

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> Optional < MCFixupKind > AArch64AsmBackend :: getFixupKind ( StringRef Name ) const { if ( TheTriple . isOSBinFormatELF ( ) && Name == "R_AARCH64_NONE" ) return FK_NONE ; return MCAsmBackend :: getFixupKind ( Name ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> static bool sh_legitimize_address_displacement ( rtx * offset1 , rtx * offset2 , poly_int64 orig_offset , machine_mode mode ) { if ( ( TARGET_FPU_DOUBLE && mode == DFmode ) || ( TARGET_SH2E && mode == SFmode ) ) return false ; struct disp_adjust adj = sh_find_mov_disp_adjust ( mode , orig_offset ) ; if ( adj . offset_adjust != NULL_RTX && adj . mov_disp != NULL_RTX ) { * offset1 = adj . offset_adjust ; * offset2 = adj . mov_disp ; return true ; } return false ; } </s>

Return true if DISP can be legitimized .


<s>
int
SparcRegisterInfo
::
getDwarfRegNum
(
unsigned
RegNum
,
bool
isEH
)
const
{
llvm_unreachable
(
"What is the dwarf register number"
)
;
return
1
;
}
</s>

Map a target register to an equivalent dwarf register number .

Sparc
Sparc
"What is the dwarf register number"
1


<s>
char
*
neon_output_logic_immediate
(
const
char
*
mnem
,
rtx
*
op2
,
machine_mode
mode
,
int
inverse
,
int
quad
)
{
int
width
,
is_valid
;
static
char
templ
[
40
]
;
is_valid
=
neon_immediate_valid_for_logic
(
*
op2
,
mode
,
inverse
,
op2
,
&
width
)
;
gcc_assert
(
is_valid
!=
0
)
;
if
(
quad
)
sprintf
(
templ
,
"%s.i%d\t%%q0, %%2"
,
mnem
,
width
)
;
else
sprintf
(
templ
,
"%s.i%d\t%%P0, %%2"
,
mnem
,
width
)
;
return
templ
;
}
</s>

Return a string suitable for output of Neon immediate logic operation MNEM .


"Malformed basic block: unconditional branch not last"

Remove the branching code at the end of the specific MBB .


<s> Register getRegister ( ) const { assert ( ! IsStack ) ; return Reg ; } </s>

Return the specified register in the class .


<s> InstructionCost PPCTTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { if ( DisablePPCConstHoist ) return BaseT :: getIntImmCost ( Imm , Ty , CostKind ) ; assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return ~ 0U ; if ( Imm == 0 ) return TTI :: TCC_Free ; if ( Imm . getBitWidth ( ) <= 64 ) { if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Basic ; if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) { if ( ( Imm . getZExtValue ( ) & 0xFFFF ) == 0 ) return TTI :: TCC_Basic ; return 2 * TTI :: TCC_Basic ; } } return 4 * TTI :: TCC_Basic ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> static bool s390_scalar_mode_supported_p ( machine_mode mode ) { if ( ! TARGET_64BIT && TARGET_ZARCH && mode == TImode ) return false ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) return default_decimal_float_supported_p ( ) ; return default_scalar_mode_supported_p ( mode ) ; } </s>

Return true if the back end supports mode MODE .


<s> const char * VETargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( VEISD :: NodeType ) Opcode ) { case VEISD :: FIRST_NUMBER : break ; case VEISD :: RET_FLAG : return "VEISD::RET_FLAG" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static bool mmix_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { if ( aligned_p ) switch ( size ) { case 1 : if ( GET_CODE ( x ) != CONST_INT ) { aligned_p = 0 ; break ; } fputs ( "\tBYTE\t" , asm_out_file ) ; mmix_print_operand ( asm_out_file , x , 'B' ) ; fputc ( '\n' , asm_out_file ) ; return true ; case 2 : if ( GET_CODE ( x ) != CONST_INT ) { aligned_p = 0 ; break ; } fputs ( "\tWYDE\t" , asm_out_file ) ; mmix_print_operand ( asm_out_file , x , 'W' ) ; fputc ( '\n' , asm_out_file ) ; return true ; case 4 : if ( GET_CODE ( x ) != CONST_INT ) { aligned_p = 0 ; break ; } fputs ( "\tTETRA\t" , asm_out_file ) ; mmix_print_operand ( asm_out_file , x , 'L' ) ; fputc ( '\n' , asm_out_file ) ; return true ; case 8 : gcc_assert ( GET_CODE ( x ) != CONST_DOUBLE ) ; assemble_integer_with_op ( "\tOCTA\t" , x ) ; return true ; } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . Use mmix_print_operand for WYDE and TETRA . Use mmix_output_octa to output 8-byte CONST_DOUBLEs .


<s> bool Cpu0AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Cpu0FI = MF . getInfo < Cpu0FunctionInfo > ( ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> AliasResult AMDGPUAAResult :: alias ( const MemoryLocation & LocA , const MemoryLocation & LocB ) { unsigned asA = LocA . Ptr -> getType ( ) -> getPointerAddressSpace ( ) ; unsigned asB = LocB . Ptr -> getType ( ) -> getPointerAddressSpace ( ) ; AliasResult Result = getAliasResult ( asA , asB ) ; if ( Result == NoAlias ) return Result ; return AAResultBase :: alias ( LocA , LocB ) ; } </s>

alias - If one of the pointers is to a global that we are tracking , and the other is some random pointer , we know there can not be an alias , because the address of the global is n't taken .


"After expanding ARM pseudo instructions."


<s> void MOSInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , Register SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { loadStoreRegStackSlot ( MBB , MI , SrcReg , isKill , FrameIndex , RC , TRI , false ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> static void loongarch_init_print_operand_punct ( void ) { const char * p ; for ( p = ".$" ; * p ; p ++ ) loongarch_print_operand_punct [ ( unsigned char ) * p ] = true ; } </s>


<s> static void ia64_output_dwarf_dtprel ( FILE * file , int size , rtx x ) { gcc_assert ( size == 4 || size == 8 ) ; if ( size == 4 ) fputs ( "\tdata4.ua\t@dtprel(" , file ) ; else fputs ( "\tdata8.ua\t@dtprel(" , file ) ; output_addr_const ( file , x ) ; fputs ( ")" , file ) ; } </s>

This is called from dwarf2out.cc via TARGET_ASM_OUTPUT_DWARF_DTPREL . We need to emit DTP-relative relocations .


<s> void F2003fDAGToDAGISel :: Select ( SDNode * Node ) { SDLoc dl ( Node ) ; if ( Node -> isMachineOpcode ( ) ) { Node -> setNodeId ( - 1 ) ; return ; } switch ( Node -> getOpcode ( ) ) { default : break ; case ISD :: FrameIndex : { int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; CurDAG -> SelectNodeTo ( Node , F2003f :: ATAframe , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i16 ) ) ; return ; } } SelectCode ( Node ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> static enum reg_class mep_secondary_copro_reload_class ( enum reg_class rclass , rtx x ) { if ( mep_general_reg ( x ) ) return NO_REGS ; if ( mep_general_copro_reg ( x ) ) { if ( mep_have_copro_copro_moves_p ) return NO_REGS ; if ( mep_have_core_copro_moves_p ) return GENERAL_REGS ; return NO_REGS ; } if ( reg_class_subset_p ( rclass , LOADABLE_CR_REGS ) && constraint_satisfied_p ( x , CONSTRAINT_U ) ) return NO_REGS ; return GENERAL_REGS ; } </s>

Return the secondary reload class needed for moving value X to or from a register in coprocessor register class CLASS .


<s> void m32c_init_cumulative_args ( CUMULATIVE_ARGS * ca , tree fntype ATTRIBUTE_UNUSED , rtx libname ATTRIBUTE_UNUSED , tree fndecl ATTRIBUTE_UNUSED , int n_named_args ATTRIBUTE_UNUSED ) { ca -> force_mem = 0 ; ca -> parm_num = 1 ; } </s>


<s> std :: vector < SIScheduleBlock * > getBlocks ( ) { return BlocksScheduled ; } </s>

Get a list of the basic blocks which make up this loop .


<s> static bool mep_mentioned_p ( rtx in , rtx reg , int modes_too ) { const char * fmt ; int i ; enum rtx_code code ; if ( in == 0 ) return false ; if ( reg && GET_CODE ( reg ) != REG ) return false ; if ( GET_CODE ( in ) == LABEL_REF ) return ( reg == 0 ) ; code = GET_CODE ( in ) ; switch ( code ) { case MEM : if ( reg ) return mep_mentioned_p ( XEXP ( in , 0 ) , reg , modes_too ) ; return true ; case REG : if ( ! reg ) return false ; if ( modes_too && ( GET_MODE ( in ) != GET_MODE ( reg ) ) ) return false ; return ( REGNO ( in ) == REGNO ( reg ) ) ; case SCRATCH : case CC0 : case PC : case CONST_INT : case CONST_DOUBLE : return false ; default : break ; } if ( code == SET && ! reg ) return mep_mentioned_p ( SET_DEST ( in ) , reg , modes_too ) ; fmt = GET_RTX_FORMAT ( code ) ; for ( i = GET_RTX_LENGTH ( code ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { register int j ; for ( j = XVECLEN ( in , i ) - 1 ; j >= 0 ; j -- ) if ( mep_mentioned_p ( XVECEXP ( in , i , j ) , reg , modes_too ) ) return true ; } else if ( fmt [ i ] == 'e' && mep_mentioned_p ( XEXP ( in , i ) , reg , modes_too ) ) return true ; } return false ; } </s>


<s> void OrderedRegisterList :: insert ( unsigned VR ) { iterator L = std :: lower_bound ( Seq . begin ( ) , Seq . end ( ) , VR , Ord ) ; if ( L == Seq . end ( ) ) Seq . push_back ( VR ) ; else Seq . insert ( L , VR ) ; } </s>

insert - Append entry to the vector if it does n't already exist .


<s> void NVPTXRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( NVPTX :: VRFrame , false ) ; MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool ARMBaseInstrInfo :: ClobbersPredicate ( MachineInstr & MI , std :: vector < MachineOperand > & Pred , bool SkipDead ) const { bool Found = false ; for ( const MachineOperand & MO : MI . operands ( ) ) { bool ClobbersCPSR = MO . isRegMask ( ) && MO . clobbersPhysReg ( ARM :: CPSR ) ; bool IsCPSR = MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == ARM :: CPSR ; if ( ClobbersCPSR || IsCPSR ) { const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( MCID . TSFlags & ARMII :: ThumbArithFlagSetting && MO . isDead ( ) && SkipDead ) continue ; Pred . push_back ( MO ) ; Found = true ; } } return Found ; } </s>

If the specified instruction defines any predicate or condition code register ( s ) used for predication , returns true as well as the definition predicate ( s ) by reference .

ARM ARM ARM::CPSR ARM::CPSR ARMII::ThumbArithFlagSetting


<s> Optional < ExtAddrMode > X86InstrInfo :: getAddrModeFromMemoryOp ( const MachineInstr & MemI , const TargetRegisterInfo * TRI ) const { const MCInstrDesc & Desc = MemI . getDesc ( ) ; int MemRefBegin = X86II :: getMemoryOperandNo ( Desc . TSFlags ) ; if ( MemRefBegin < 0 ) return None ; MemRefBegin += X86II :: getOperandBias ( Desc ) ; auto & BaseOp = MemI . getOperand ( MemRefBegin + X86 :: AddrBaseReg ) ; if ( ! BaseOp . isReg ( ) ) return None ; const MachineOperand & DispMO = MemI . getOperand ( MemRefBegin + X86 :: AddrDisp ) ; if ( ! DispMO . isImm ( ) ) return None ; ExtAddrMode AM ; AM . BaseReg = BaseOp . getReg ( ) ; AM . ScaledReg = MemI . getOperand ( MemRefBegin + X86 :: AddrIndexReg ) . getReg ( ) ; AM . Scale = MemI . getOperand ( MemRefBegin + X86 :: AddrScaleAmt ) . getImm ( ) ; AM . Displacement = DispMO . getImm ( ) ; return AM ; } </s>

Target dependent implementation to get the values constituting the address MachineInstr that is accessing memory .


<s> bool vax_maybe_split_dimode_move ( rtx * operands ) { return ( TARGET_QMATH && ( ! MEM_P ( operands [ 0 ] ) || GET_CODE ( XEXP ( operands [ 0 ] , 0 ) ) == PRE_DEC || GET_CODE ( XEXP ( operands [ 0 ] , 0 ) ) == POST_INC || ! illegal_addsub_di_memory_operand ( operands [ 0 ] , DImode ) ) && ( ( CONST_INT_P ( operands [ 1 ] ) && ( unsigned HOST_WIDE_INT ) INTVAL ( operands [ 1 ] ) >= 64 ) || GET_CODE ( operands [ 1 ] ) == CONST_DOUBLE ) ) ; } </s>


"Instr doesn't have FrameIndex operand!"


<s> long compute_frame_size ( poly_int64 size ) { int regno ; if ( reload_completed && cfun -> machine -> frame_laid_out ) return cfun -> machine -> current_frame_size ; if ( cfun -> static_chain_decl != NULL ) size += ( 1 * UNITS_PER_WORD ) ; cfun -> machine -> callee_save_size = 0 ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; ++ regno ) { if ( xtensa_call_save_reg ( regno ) ) cfun -> machine -> callee_save_size += UNITS_PER_WORD ; } cfun -> machine -> current_frame_size = XTENSA_STACK_ALIGN ( size + cfun -> machine -> callee_save_size + crtl -> outgoing_args_size + ( WINDOW_SIZE * UNITS_PER_WORD ) ) ; cfun -> machine -> callee_save_size = XTENSA_STACK_ALIGN ( cfun -> machine -> callee_save_size ) ; cfun -> machine -> frame_laid_out = true ; return cfun -> machine -> current_frame_size ; } </s>

Typical stack layout should looks like this after the function 's prologue : | | -- ^ | | \ | | | arguments saved | Increasing | | on the stack | addresses PARENT arg pointer - > | | / -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - | | - space for argument split between regs & stack -- CHILD | | \ < -- ( return address here ) | | other call | | saved registers | | / -- frame pointer - > | | \ ___ | | local | | | variables |f | | / |r -- |a | | \ |m | | outgoing |e | | arguments | | Decreasing ( hard ) frame pointer | | / | | addresses and stack pointer - > | | / _|_ | -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- V