<s> int frv_legitimate_memory_operand ( rtx op , enum machine_mode mode , int condexec_p ) { return ( ( GET_MODE ( op ) == mode || mode == VOIDmode ) && GET_CODE ( op ) == MEM && frv_legitimate_address_p ( mode , XEXP ( op , 0 ) , reload_completed , condexec_p , FALSE ) ) ; } </s>

Return 1 if operand is a valid FRV address . CONDEXEC_P is true if the operand is used by a predicated instruction .


<s> bool AArch64FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; static const LoadStoreMethod PossibleClasses [ ] = { { & AArch64 :: GPR64RegClass , AArch64 :: LSPair64_STR , AArch64 :: LS64_STR } , { & AArch64 :: FPR64RegClass , AArch64 :: LSFPPair64_STR , AArch64 :: LSFP64_STR } , } ; const unsigned NumClasses = llvm :: array_lengthof ( PossibleClasses ) ; emitFrameMemOps ( true , MBB , MBBI , CSI , TRI , PossibleClasses , NumClasses ) ; return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s>
bool
runOnMachineFunction
(
MachineFunction
&
F
)
{
bool
Changed
=
false
;
if
(
TM
.
getSubtargetImpl
(
)
->
getCFLType
(
)
!=
PatmosSubtarget
::
CFL_DELAYED
)
{
DEBUG
(
dbgs
(
)
<<
"\n[DelaySlotKiller] "
<<
F
.
getFunction
(
)
->
getName
(
)
<<
"\n"
)
;
for
(
MachineFunction
::
iterator
FI
=
F
.
begin
(
)
,
FE
=
F
.
end
(
)
;
FI
!=
FE
;
++
FI
)
Changed
|=
killDelaySlots
(
*
FI
)
;
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

Patmos
Patmos
"\n[DelaySlotKiller] "
"\n"


<s> void WebAssemblyFrameLowering :: writeSPToGlobal ( unsigned SrcReg , MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & InsertStore , const DebugLoc & DL ) const { const auto * TII = MF . getSubtarget < WebAssemblySubtarget > ( ) . getInstrInfo ( ) ; const char * ES = "__stack_pointer" ; auto * SPSymbol = MF . createExternalSymbolName ( ES ) ; BuildMI ( MBB , InsertStore , DL , TII -> get ( getOpcGlobSet ( MF ) ) ) . addExternalSymbol ( SPSymbol ) . addReg ( SrcReg ) ; } </s>

Write SP back to __stack_pointer global .

WebAssembly WebAssembly WebAssembly "__stack_pointer"


<s> static bool hasReassociableSibling ( const MachineInstr & Inst , bool & Commuted ) { const MachineBasicBlock * MBB = Inst . getParent ( ) ; const MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; MachineInstr * MI1 = MRI . getUniqueVRegDef ( Inst . getOperand ( 1 ) . getReg ( ) ) ; MachineInstr * MI2 = MRI . getUniqueVRegDef ( Inst . getOperand ( 2 ) . getReg ( ) ) ; unsigned AssocOpcode = Inst . getOpcode ( ) ; Commuted = MI1 -> getOpcode ( ) != AssocOpcode && MI2 -> getOpcode ( ) == AssocOpcode ; if ( Commuted ) std :: swap ( MI1 , MI2 ) ; if ( MI1 -> getOpcode ( ) == AssocOpcode && hasReassociableOperands ( * MI1 , MBB ) && MRI . hasOneNonDBGUse ( MI1 -> getOperand ( 0 ) . getReg ( ) ) ) return true ; return false ; } </s>

Return true when \P Inst has reassociable sibling .


<s> static unsigned int h8300_move_length ( rtx * operands , const h8300_length_table * table ) { unsigned int size ; size = h8300_length_from_table ( operands [ 0 ] , operands [ 1 ] , table ) ; if ( REG_P ( operands [ 0 ] ) && h8300_short_move_mem_p ( operands [ 1 ] , POST_INC ) ) size -= 2 ; if ( REG_P ( operands [ 1 ] ) && h8300_short_move_mem_p ( operands [ 0 ] , PRE_DEC ) ) size -= 2 ; return size ; } </s>

Calculate the length of move instruction INSN using the given length table . Although the tables are correct for most cases , there is some irregularity in the length of mov.b and mov.w . The following forms : mov @ ERs+ , Rd mov @ ( d:16 , ERs ) , Rd mov Rs , @ -ERd mov Rs , @ ( d:16 , ERd ) are two bytes shorter than most other `` mov Rs , @ complex '' or `` mov @ complex , Rd '' combinations .


<s> void ARMPassConfig :: addPreEmitPass ( ) { addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( createUnpackMachineBundles ( [ ] ( const MachineFunction & MF ) { return MF . getSubtarget < ARMSubtarget > ( ) . isThumb2 ( ) ; } ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createARMOptimizeBarriersPass ( ) ) ; addPass ( createARMConstantIslandPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> SDValue SparcTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: BITCAST : return PerformBITCASTCombine ( N , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


"attribute %<target%> argument not a string"

"invalid fpu for attribute(target(\"%s\"))"

Inner function to process the attribute ( ( target ( ... ) ) ) , take an argument and set the current options from the argument . If we have a list , recursively go over the list .


<s> enum reg_class arm_regno_class ( int regno ) { if ( regno == PC_REGNUM ) return NO_REGS ; if ( TARGET_THUMB1 ) { if ( regno == STACK_POINTER_REGNUM ) return STACK_REG ; if ( regno == CC_REGNUM ) return CC_REG ; if ( regno < 8 ) return LO_REGS ; return HI_REGS ; } if ( TARGET_THUMB2 && regno < 8 ) return LO_REGS ; if ( regno <= LAST_ARM_REGNUM || regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return TARGET_THUMB2 ? HI_REGS : GENERAL_REGS ; if ( regno == CC_REGNUM || regno == VFPCC_REGNUM ) return TARGET_THUMB2 ? CC_REG : NO_REGS ; if ( IS_VFP_REGNUM ( regno ) ) { if ( regno <= D7_VFP_REGNUM ) return VFP_D0_D7_REGS ; else if ( regno <= LAST_LO_VFP_REGNUM ) return VFP_LO_REGS ; else return VFP_HI_REGS ; } if ( IS_IWMMXT_REGNUM ( regno ) ) return IWMMXT_REGS ; if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return IWMMXT_GR_REGS ; return NO_REGS ; } </s>

For efficiency and historical reasons LO_REGS , HI_REGS and CC_REGS are not used in arm mode .


<s> int X86TTIImpl :: getIntrinsicInstrCost ( Intrinsic :: ID IID , Type * RetTy , ArrayRef < Value * > Args , FastMathFlags FMF , unsigned VF ) { return BaseT :: getIntrinsicInstrCost ( IID , RetTy , Args , FMF , VF ) ; } </s>


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"PIC16 Memsel Optimizer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
SDValue
VETargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_VE
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
OutVal
=
OutVals
[
i
]
;
switch
(
VA
.
getLocInfo
(
)
)
{
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
SExt
:
OutVal
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
DL
,
VA
.
getLocVT
(
)
,
OutVal
)
;
break
;
case
CCValAssign
::
ZExt
:
OutVal
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
DL
,
VA
.
getLocVT
(
)
,
OutVal
)
;
break
;
case
CCValAssign
::
AExt
:
OutVal
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
DL
,
VA
.
getLocVT
(
)
,
OutVal
)
;
break
;
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
}
assert
(
!
VA
.
needsCustom
(
)
&&
"Unexpected custom lowering"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
OutVal
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
VEISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> const RegisterBankInfo :: InstructionMapping & MipsRegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const RegisterBankInfo :: InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; switch ( Opc ) { case G_TRUNC : case G_ADD : case G_SUB : case G_MUL : case G_UMULH : case G_LOAD : case G_STORE : case G_ZEXTLOAD : case G_SEXTLOAD : case G_GEP : case G_AND : case G_OR : case G_XOR : case G_SHL : case G_ASHR : case G_LSHR : case G_SDIV : case G_UDIV : case G_SREM : case G_UREM : OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; break ; case G_FCONSTANT : { LLT Ty = MRI . getType ( MI . getOperand ( 0 ) . getReg ( ) ) ; unsigned Size = Ty . getSizeInBits ( ) ; const RegisterBankInfo :: ValueMapping * FPRValueMapping = Size == 32 ? & Mips :: ValueMappings [ Mips :: SPRIdx ] : & Mips :: ValueMappings [ Mips :: DPRIdx ] ; OperandsMapping = getOperandsMapping ( { FPRValueMapping , nullptr } ) ; break ; } case G_CONSTANT : case G_FRAME_INDEX : case G_GLOBAL_VALUE : case G_BRCOND : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr } ) ; break ; case G_ICMP : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] } ) ; break ; case G_SELECT : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] } ) ; break ; default : return getInvalidInstructionMapping ( ) ; } return getInstructionMapping ( DefaultMappingID , 1 , OperandsMapping , NumOperands ) ; } </s>

Get the mapping of the different operands of MI on the register bank .

Mips Mips Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx 0 32 Mips::ValueMappings Mips::SPRIdx Mips::ValueMappings Mips::DPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx 1


<s> uint64_t getNullPointerValue ( unsigned AddrSpace ) const { return ( AddrSpace == AMDGPUAS :: LOCAL_ADDRESS || AddrSpace == AMDGPUAS :: REGION_ADDRESS ) ? - 1 : 0 ; } </s>

Get the integer value of a null pointer in the given address space .


<s> bool X86FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || TRI -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasOpaqueSPAdjustment ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> hasPreallocatedCall ( ) || MF . callsUnwindInit ( ) || MF . hasEHFunclets ( ) || MF . callsEHReturn ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || MFI . hasCopyImplyingStackAdjustment ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> XCoreSubtarget :: XCoreSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : XCoreGenSubtargetInfo ( TT , CPU , CPU , FS ) , FrameLowering ( * this ) , TLInfo ( TM , * this ) { } </s>

This constructor initializes the data members to match that of the specified triple .


<s> bool rs6000_tls_referenced_p ( rtx x ) { if ( ! TARGET_HAVE_TLS ) return false ; return for_each_rtx ( & x , & rs6000_tls_symbol_ref_1 , 0 ) ; } </s>

Return 1 if X contains a thread-local symbol .


<s> const char * FISCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return NULL ; case FISCISD :: RET_FLAG : return "RetFlag" ; case FISCISD :: LOAD_SYM : return "LOAD_SYM" ; case FISCISD :: MOVEi64 : return "MOVEi64" ; case FISCISD :: CALL : return "CALL" ; case FISCISD :: SELECT_CC : return "SELECT_CC" ; case FISCISD :: CMP : return "CMP" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> bool PPCTargetLowering :: SelectAddressPCRel ( SDValue N , SDValue & Base ) const { Base = N ; if ( N . getOpcode ( ) == PPCISD :: MAT_PCREL_ADDR ) return true ; if ( isValidPCRelNode < ConstantPoolSDNode > ( N ) || isValidPCRelNode < GlobalAddressSDNode > ( N ) || isValidPCRelNode < JumpTableSDNode > ( N ) || isValidPCRelNode < BlockAddressSDNode > ( N ) ) return true ; return false ; } </s>

SelectAddressPCRel - Represent the specified address as pc relative to be represented as [ pc+imm ] .


"Instr doesn't have FrameIndex operand!"

"Unconditionally using R28 for evil purposes Offset: "

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static void ia64_copy_rbs ( struct _Unwind_Context * info , unsigned long dst , unsigned long src , long len , unsigned long dst_rnat ) { long count ; unsigned long src_rnat ; unsigned long shift1 , shift2 ; len <<= 3 ; dst_rnat &= ( 1UL << ( ( dst >> 3 ) & 0x3f ) ) - 1 ; src_rnat = src >= info -> regstk_top ? info -> rnat : * ( unsigned long * ) ( src | 0x1f8 ) ; src_rnat &= ~ ( ( 1UL << ( ( src >> 3 ) & 0x3f ) ) - 1 ) ; src_rnat &= ~ ( 1UL << 63 ) ; shift1 = ( ( dst - src ) >> 3 ) & 0x3f ; if ( ( dst & 0x1f8 ) < ( src & 0x1f8 ) ) shift1 -- ; shift2 = 0x3f - shift1 ; if ( ( dst & 0x1f8 ) >= ( src & 0x1f8 ) ) { count = ~ dst & 0x1f8 ; goto first ; } count = ~ src & 0x1f8 ; goto second ; while ( len > 0 ) { src_rnat = src >= info -> regstk_top ? info -> rnat : * ( unsigned long * ) ( src | 0x1f8 ) ; src_rnat &= ~ ( 1UL << 63 ) ; count = shift2 << 3 ; first : if ( count > len ) count = len ; memcpy ( ( char * ) dst , ( char * ) src , count ) ; dst += count ; src += count ; len -= count ; dst_rnat |= ( src_rnat << shift1 ) & ~ ( 1UL << 63 ) ; if ( len <= 0 ) break ; * ( long * ) dst = dst_rnat ; dst += 8 ; dst_rnat = 0 ; count = shift1 << 3 ; second : if ( count > len ) count = len ; memcpy ( ( char * ) dst , ( char * ) src , count ) ; dst += count ; src += count + 8 ; len -= count + 8 ; dst_rnat |= ( src_rnat >> shift2 ) ; } if ( ( dst & 0x1f8 ) == 0x1f8 ) { * ( long * ) dst = dst_rnat ; dst += 8 ; dst_rnat = 0 ; } info -> regstk_top = dst & ~ 0x1ffUL ; info -> rnat = dst_rnat ; } </s>

Copy register backing store from SRC to DST , LEN words ( which include both saved registers and nat collections ) . DST_RNAT is a partial nat collection for DST . SRC and DST do n't have to be equal modulo 64 slots , so it can not be done with a simple memcpy as the nat collections will be at different relative offsets and need to be combined together .


<s> unsigned SIInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( ! MI . mayStore ( ) ) return AMDGPU :: NoRegister ; if ( isMUBUF ( MI ) || isVGPRSpill ( MI ) ) return isStackAccess ( MI , FrameIndex ) ; if ( isSGPRSpill ( MI ) ) return isSGPRStackAccess ( MI , FrameIndex ) ; return AMDGPU :: NoRegister ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .

AMDGPU SI AMDGPU::NoRegister AMDGPU::NoRegister


<s> void rs6000_asm_output_dwarf_pcrel ( FILE * file , int size , const char * label ) { fputs ( integer_asm_op ( size , FALSE ) , file ) ; assemble_name ( file , label ) ; fputs ( "-$" , file ) ; } </s>

Overide the default 'SYMBOL- . ' syntax with AIX compatible 'SYMBOL- $ ' .


<s> static struct machine_function * tilepro_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function > ( ) ; } </s>

Functions to save and restore machine-specific function data .


<s> bool vax_legitimate_address_p ( machine_mode mode , rtx x , bool strict ) { rtx xfoo0 , xfoo1 ; if ( nonindexed_address_p ( x , strict ) ) return true ; if ( GET_CODE ( x ) != PLUS ) return false ; xfoo0 = XEXP ( x , 0 ) ; xfoo1 = XEXP ( x , 1 ) ; if ( index_term_p ( xfoo0 , mode , strict ) && nonindexed_address_p ( xfoo1 , strict ) ) return true ; if ( index_term_p ( xfoo1 , mode , strict ) && nonindexed_address_p ( xfoo0 , strict ) ) return true ; if ( indexable_address_p ( xfoo0 , xfoo1 , mode , strict ) || indexable_address_p ( xfoo1 , xfoo0 , mode , strict ) ) return true ; return false ; } </s>

legitimate_address_p returns true if it recognizes an RTL expression `` x '' that is a valid memory address for an instruction . The MODE argument is the machine mode for the MEM expression that wants to use this address .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 avoid trailing call pass"
;
}
</s>


<s> static inline ChildIteratorType child_begin ( NodeRef N ) { return N -> getChildren ( ) . begin ( ) ; } </s>

nodes_iterator/begin/end - Allow iteration over all nodes in the graph


<s> bool easy_altivec_constant ( rtx op , enum machine_mode mode ) { unsigned step , copies ; if ( mode == VOIDmode ) mode = GET_MODE ( op ) ; else if ( mode != GET_MODE ( op ) ) return false ; step = GET_MODE_NUNITS ( mode ) / 4 ; copies = 1 ; if ( vspltis_constant ( op , step , copies ) ) return true ; if ( step == 1 ) copies <<= 1 ; else step >>= 1 ; if ( vspltis_constant ( op , step , copies ) ) return true ; if ( step == 1 ) copies <<= 1 ; else step >>= 1 ; if ( vspltis_constant ( op , step , copies ) ) return true ; return false ; } </s>

Return true if OP is of the given MODE and can be synthesized with a vspltisb , vspltish or vspltisw .


<s> bool AArch64PassConfig :: addIRTranslator ( ) { addPass ( new IRTranslator ( getOptLevel ( ) ) ) ; return false ; } </s>

This method should install an IR translator pass , which converts from LLVM code to machine instructions with possibly generic opcodes .


<s> void GCNPassConfig :: addPreEmitPass ( ) { addPass ( createSIInsertWaits ( * TM ) , false ) ; addPass ( createSILowerControlFlowPass ( * TM ) , false ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> unsigned AArch64InstrInfo :: getLoadStoreImmIdx ( unsigned Opc ) { switch ( Opc ) { default : return 2 ; case AArch64 :: LDPXi : case AArch64 :: LDPDi : case AArch64 :: STPXi : case AArch64 :: STPDi : case AArch64 :: LDNPXi : case AArch64 :: LDNPDi : case AArch64 :: STNPXi : case AArch64 :: STNPDi : case AArch64 :: LDPQi : case AArch64 :: STPQi : case AArch64 :: LDNPQi : case AArch64 :: STNPQi : case AArch64 :: LDPWi : case AArch64 :: LDPSi : case AArch64 :: STPWi : case AArch64 :: STPSi : case AArch64 :: LDNPWi : case AArch64 :: LDNPSi : case AArch64 :: STNPWi : case AArch64 :: STNPSi : case AArch64 :: LDG : case AArch64 :: STGPi : case AArch64 :: LD1B_IMM : case AArch64 :: LD1H_IMM : case AArch64 :: LD1W_IMM : case AArch64 :: LD1D_IMM : case AArch64 :: ST1B_IMM : case AArch64 :: ST1H_IMM : case AArch64 :: ST1W_IMM : case AArch64 :: ST1D_IMM : case AArch64 :: LD1B_H_IMM : case AArch64 :: LD1SB_H_IMM : case AArch64 :: LD1H_S_IMM : case AArch64 :: LD1SH_S_IMM : case AArch64 :: LD1W_D_IMM : case AArch64 :: LD1SW_D_IMM : case AArch64 :: ST1B_H_IMM : case AArch64 :: ST1H_S_IMM : case AArch64 :: ST1W_D_IMM : case AArch64 :: LD1B_S_IMM : case AArch64 :: LD1SB_S_IMM : case AArch64 :: LD1H_D_IMM : case AArch64 :: LD1SH_D_IMM : case AArch64 :: ST1B_S_IMM : case AArch64 :: ST1H_D_IMM : case AArch64 :: LD1B_D_IMM : case AArch64 :: LD1SB_D_IMM : case AArch64 :: ST1B_D_IMM : return 3 ; case AArch64 :: ADDG : case AArch64 :: STGOffset : case AArch64 :: LDR_PXI : case AArch64 :: STR_PXI : return 2 ; } } </s>

Returns the index for the immediate for a given instruction .


<s> bool XCoreRegisterInfo :: needsFrameMoves ( const MachineFunction & MF ) { return MF . needsFrameMoves ( ) ; } </s>


<s>
MCSymbol
*
X86MCInstLower
::
GetSymbolFromOperand
(
const
MachineOperand
&
MO
)
const
{
const
DataLayout
&
DL
=
MF
.
getDataLayout
(
)
;
assert
(
(
MO
.
isGlobal
(
)
||
MO
.
isSymbol
(
)
||
MO
.
isMBB
(
)
)
&&
"Isn't a symbol reference"
)
;
MCSymbol
*
Sym
=
nullptr
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
switch
(
MO
.
getTargetFlags
(
)
)
{
case
X86II
::
MO_DLLIMPORT
:
Name
+=
"__imp_"
;
break
;
case
X86II
::
MO_DARWIN_STUB
:
Suffix
=
"$stub"
;
break
;
case
X86II
::
MO_DARWIN_NONLAZY
:
case
X86II
::
MO_DARWIN_NONLAZY_PIC_BASE
:
Suffix
=
"$non_lazy_ptr"
;
break
;
}
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
.
getPrivateGlobalPrefix
(
)
;
unsigned
PrefixLen
=
Name
.
size
(
)
;
if
(
MO
.
isGlobal
(
)
)
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
AsmPrinter
.
getNameWithPrefix
(
Name
,
GV
)
;
}
else
if
(
MO
.
isSymbol
(
)
)
{
Mangler
::
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
,
DL
)
;
}
else
if
(
MO
.
isMBB
(
)
)
{
assert
(
Suffix
.
empty
(
)
)
;
Sym
=
MO
.
getMBB
(
)
->
getSymbol
(
)
;
}
unsigned
OrigLen
=
Name
.
size
(
)
PrefixLen
;
Name
+=
Suffix
;
if
(
!
Sym
)
Sym
=
Ctx
.
getOrCreateSymbol
(
Name
)
;
StringRef
OrigName
=
StringRef
(
Name
)
.
substr
(
PrefixLen
,
OrigLen
)
;
switch
(
MO
.
getTargetFlags
(
)
)
{
default
:
break
;
case
X86II
::
MO_DARWIN_NONLAZY
:
case
X86II
::
MO_DARWIN_NONLAZY_PIC_BASE
:
{
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
getMachOMMI
(
)
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AsmPrinter
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
break
;
}
case
X86II
::
MO_DARWIN_STUB
:
{
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
getMachOMMI
(
)
.
getFnStubEntry
(
Sym
)
;
if
(
StubSym
.
getPointer
(
)
)
return
Sym
;
if
(
MO
.
isGlobal
(
)
)
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AsmPrinter
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
else
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
Ctx
.
getOrCreateSymbol
(
OrigName
)
,
false
)
;
}
break
;
}
}
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


<s> TargetPassConfig * MMIXTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new MMIXPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> void X86FrameLowering :: emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , int64_t NumBytes , bool InEpilogue ) const { bool isSub = NumBytes < 0 ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; uint64_t Chunk = ( 1LL << 31 ) - 1 ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; if ( Offset == 0 ) { MachineInstrBuilder MI = BuildMI ( MBB , MBBI , DL , TII . get ( X86 :: SUB64ri8 ) , StackPtr ) . addReg ( StackPtr ) . addImm ( 0 ) ; if ( ! InEpilogue ) MI . setMIFlag ( MachineInstr :: FrameSetup ) ; else MI . setMIFlag ( MachineInstr :: FrameDestroy ) ; } while ( Offset ) { if ( Offset > Chunk ) { unsigned Reg = 0 ; if ( isSub && ! isEAXLiveIn ( MBB ) ) Reg = ( unsigned ) ( Is64Bit ? X86 :: RAX : X86 :: EAX ) ; else Reg = findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { unsigned Opc = Is64Bit ? X86 :: MOV64ri : X86 :: MOV32ri ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , Reg ) . addImm ( Offset ) ; Opc = isSub ? getSUBrrOpcode ( Is64Bit ) : getADDrrOpcode ( Is64Bit ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addReg ( Reg ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; Offset = 0 ; continue ; } } uint64_t ThisVal = std :: min ( Offset , Chunk ) ; if ( ThisVal == ( Is64Bit ? 8 : 4 ) && false ) { unsigned Reg = isSub ? ( unsigned ) ( Is64Bit ? X86 :: RAX : X86 :: EAX ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { unsigned Opc = isSub ? ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) : ( Is64Bit ? X86 :: POP64r : X86 :: POP32r ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ; if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; else MI -> setFlag ( MachineInstr :: FrameDestroy ) ; Offset -= ThisVal ; continue ; } } MachineInstrBuilder MI = BuildStackAdjustment ( MBB , MBBI , DL , isSub ? - ThisVal : ThisVal , InEpilogue ) ; if ( isSub ) MI . setMIFlag ( MachineInstr :: FrameSetup ) ; else MI . setMIFlag ( MachineInstr :: FrameDestroy ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s>
void
HexagonInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
OS
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
)
{
assert
(
HexagonMCInstrInfo
::
isBundle
(
*
MI
)
)
;
assert
(
HexagonMCInstrInfo
::
bundleSize
(
*
MI
)
<=
HEXAGON_PACKET_SIZE
)
;
assert
(
HexagonMCInstrInfo
::
bundleSize
(
*
MI
)
>
0
)
;
HasExtender
=
false
;
for
(
auto
const
&
I
:
HexagonMCInstrInfo
::
bundleInstructions
(
*
MI
)
)
{
MCInst
const
&
MCI
=
*
I
.
getInst
(
)
;
if
(
HexagonMCInstrInfo
::
isDuplex
(
MII
,
MCI
)
)
{
printInstruction
(
MCI
.
getOperand
(
1
)
.
getInst
(
)
,
OS
)
;
OS
<<
'\v'
;
HasExtender
=
false
;
printInstruction
(
MCI
.
getOperand
(
0
)
.
getInst
(
)
,
OS
)
;
}
else
printInstruction
(
&
MCI
,
OS
)
;
setExtender
(
MCI
)
;
OS
<<
"\n"
;
}
bool
IsLoop0
=
HexagonMCInstrInfo
::
isInnerLoop
(
*
MI
)
;
bool
IsLoop1
=
HexagonMCInstrInfo
::
isOuterLoop
(
*
MI
)
;
if
(
IsLoop0
)
{
OS
<<
(
IsLoop1
" :endloop01"
:
" :endloop0"
)
;
}
else
if
(
IsLoop1
)
{
OS
<<
" :endloop1"
;
}
}
</s>

Print the specified MCInst to the specified raw_ostream .

Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
0
Hexagon
Hexagon
1
0
"\n"
Hexagon
Hexagon
" :endloop01"
" :endloop0"
" :endloop1"


<s> static bool ix86_secondary_memory_needed ( machine_mode mode , reg_class_t class1 , reg_class_t class2 ) { return inline_secondary_memory_needed ( mode , class1 , class2 , true ) ; } </s>

If we are copying between general and FP registers , we need a memory location . The same is true for SSE and MMX registers . The macro ca n't work reliably when one of the CLASSES is class containing registers from multiple units ( SSE , MMX , integer ) . We avoid this by never combining those units in single alternative in the machine description . Ensure that this constraint holds to avoid unexpected surprises . When STRICT is false , we are being called from REGISTER_MOVE_COST , so do not enforce these sanity checks .


" Instructions Emitted in this clause\n"

ScheduleDAGMI has scheduled an instruction - tell HazardRec about it .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( const auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s> MachineInstrBuilder R600InstrInfo :: buildIndirectRead ( MachineBasicBlock * MBB , MachineBasicBlock :: iterator I , unsigned ValueReg , unsigned Address , unsigned OffsetReg ) const { unsigned AddrReg = AMDGPU :: R600_AddrRegClass . getRegister ( Address ) ; MachineInstr * MOVA = buildDefaultInstruction ( * MBB , I , AMDGPU :: MOVA_INT_eg , AMDGPU :: AR_X , OffsetReg ) ; setImmOperand ( MOVA , R600Operands :: WRITE , 0 ) ; MachineInstrBuilder Mov = buildDefaultInstruction ( * MBB , I , AMDGPU :: MOV , ValueReg , AddrReg ) . addReg ( AMDGPU :: AR_X , RegState :: Implicit | RegState :: Kill ) ; setImmOperand ( Mov , R600Operands :: SRC0_REL , 1 ) ; return Mov ; } </s>

Build instruction ( s ) for an indirect register read .


<s> void TeakFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; uint64_t StackSize = computeStackSize ( MF ) ; if ( ! StackSize ) return ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; StackSize -= CSI . size ( ) * 2 ; if ( ! StackSize ) return ; BuildMI ( MBB , MBBI , dl , TII . get ( Teak :: MOV_regnobp016_regnob16 ) , Teak :: SP ) . addReg ( Teak :: R7 ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Teak :: NOP ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Teak :: POP_regnob16 ) , Teak :: R7 ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } </s>


<s> TargetPassConfig * PatmosTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new PatmosPassConfig ( this , PM ) ; } </s>


<s> static MBlazeOperand * CreateReg ( unsigned RegNum , SMLoc S , SMLoc E ) { MBlazeOperand * Op = new MBlazeOperand ( Register ) ; Op -> Reg . RegNum = RegNum ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> bool umips_12bit_offset_address_p ( rtx x , machine_mode mode ) { struct mips_address_info addr ; return ( mips_classify_address ( & addr , x , mode , false ) && addr . type == ADDRESS_REG && CONST_INT_P ( addr . offset ) && UMIPS_12BIT_OFFSET_P ( INTVAL ( addr . offset ) ) ) ; } </s>

Return true if X is a legitimate address with a 12-bit offset . MODE is the mode of the value being accessed .


<s>
const
char
*
mcore_output_jump_label_table
(
void
)
{
int
i
;
if
(
pool_size
)
{
fprintf
(
asm_out_file
,
"\t.align 2\n"
)
;
for
(
i
=
0
;
i
<
pool_size
;
i
++
)
{
pool_node
*
p
=
pool_vector
+
i
;
(
*
targetm
.
asm_out
.
internal_label
)
(
asm_out_file
,
"L"
,
CODE_LABEL_NUMBER
(
p
->
label
)
)
;
output_asm_insn
(
".long	%0"
,
&
p
->
value
)
;
}
pool_size
=
0
;
}
return
""
;
}
</s>

Dump out any constants accumulated in the final pass . These will only be labels .

mcore
"\t.align 2\n"
0
"L"
".long	%0"
0
""


<s> void GBZ80FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> void JVMPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; addPass ( createJVMLowerMemoryIntrinsics ( ) ) ; addPass ( createAggressiveDCEPass ( ) ) ; if ( JvmAggOpt ) addPass ( createInstructionCombiningPass ( ) ) ; addPass ( createJVMIRDecorator ( ) ) ; addPass ( createAggressiveDCEPass ( ) ) ; if ( JvmAggOpt ) addPass ( createInstructionCombiningPass ( ) ) ; if ( JvmClient ) addPass ( createX2JavaPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s>
static
void
aarch64_parse_cpu
(
void
)
{
char
*
ext
;
const
struct
processor
*
cpu
;
char
*
str
=
(
char
*
)
alloca
(
strlen
(
aarch64_cpu_string
)
+
1
)
;
size_t
len
;
strcpy
(
str
,
aarch64_cpu_string
)
;
ext
=
strchr
(
str
,
'+'
)
;
if
(
ext
!=
)
len
=
ext
str
;
else
len
=
strlen
(
str
)
;
if
(
len
==
0
)
{
error
(
"missing cpu name in -mcpu=%qs"
,
str
)
;
return
;
}
for
(
cpu
=
all_cores
;
cpu
->
name
!=
;
cpu
++
)
{
if
(
strlen
(
cpu
->
name
)
==
len
&&
strncmp
(
cpu
->
name
,
str
,
len
)
==
0
)
{
selected_cpu
=
cpu
;
aarch64_isa_flags
=
selected_cpu
->
flags
;
if
(
ext
!=
)
{
aarch64_parse_extension
(
ext
)
;
}
return
;
}
}
error
(
"unknown value %qs for -mcpu"
,
str
)
;
return
;
}
</s>

Parse the TO_PARSE string and put the result tuning in RES and the architecture flags in ISA_FLAGS . Return an aarch64_parse_opt_result describing the parse result . If there is an error parsing , RES and ISA_FLAGS are left unchanged .


<s> static std :: unique_ptr < SNESOperand > CreateReg ( unsigned RegNum , SMLoc S , SMLoc E ) { return make_unique < SNESOperand > ( RegNum , S , E ) ; } </s>


"LR & FP are always handled in emitPrologue"

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> int rs6000_trampoline_size ( ) { int ret = 0 ; switch ( DEFAULT_ABI ) { default : abort ( ) ; case ABI_AIX : ret = ( TARGET_32BIT ) ? 12 : 24 ; break ; case ABI_DARWIN : case ABI_V4 : case ABI_AIX_NODESC : ret = ( TARGET_32BIT ) ? 40 : 48 ; break ; } return ret ; } </s>

Length in units of the trampoline for entering a nested function .


<s> static bool msp430_check_plus_not_high_mem ( rtx op ) { if ( GET_CODE ( op ) != PLUS ) return false ; rtx op0 = XEXP ( op , 0 ) ; rtx op1 = XEXP ( op , 1 ) ; if ( SYMBOL_REF_P ( op0 ) && ( SYMBOL_REF_FLAGS ( op0 ) & SYMBOL_FLAG_LOW_MEM ) && msp430_check_index_not_high_mem ( op1 ) ) return true ; return false ; } </s>

If this returns true , we do n't need a 430X insn .


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> void SparcFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr & MI = * I ; DebugLoc DL = MI . getDebugLoc ( ) ; int Size = MI . getOperand ( 0 ) . getImm ( ) ; if ( MI . getOpcode ( ) == SP :: ADJCALLSTACKDOWN ) Size = - Size ; const SparcInstrInfo & TII = * static_cast < const SparcInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; if ( Size ) BuildMI ( MBB , I , DL , TII . get ( SP :: ADDri ) , SP :: O6 ) . addReg ( SP :: O6 ) . addImm ( Size ) ; } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

Sparc Sparc 0 SP::ADJCALLSTACKDOWN Sparc Sparc SP::ADDri SP::O6 SP::O6


<s> bool SystemZShortenInst :: runOnMachineFunction ( MachineFunction & F ) { if ( skipFunction ( * F . getFunction ( ) ) ) return false ; const SystemZSubtarget & ST = F . getSubtarget < SystemZSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; LiveRegs . init ( TRI ) ; bool Changed = false ; for ( auto & MBB : F ) Changed |= processBlock ( MBB ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool loongarch_split_move_p ( rtx dest , rtx src ) { unsigned int size = GET_MODE_SIZE ( GET_MODE ( dest ) ) ; if ( size == 8 && FP_REG_RTX_P ( src ) && FP_REG_RTX_P ( dest ) ) return false ; if ( size == 8 ) { if ( FP_REG_RTX_P ( dest ) && MEM_P ( src ) ) return false ; if ( FP_REG_RTX_P ( src ) && MEM_P ( dest ) ) return false ; } return size > UNITS_PER_WORD ; } </s>

Return true if a move from SRC to DEST should be split into two . SPLIT_TYPE describes the split condition .


<s> unsigned HexagonInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case Hexagon :: L2_loadri_io : case Hexagon :: L2_loadrd_io : case Hexagon :: L2_loadrh_io : case Hexagon :: L2_loadrb_io : case Hexagon :: L2_loadrub_io : if ( MI -> getOperand ( 2 ) . isFI ( ) && MI -> getOperand ( 1 ) . isImm ( ) && ( MI -> getOperand ( 1 ) . getImm ( ) == 0 ) ) { FrameIndex = MI -> getOperand ( 2 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> bool NVPTXInferAddressSpaces :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; std :: vector < Value * > Postorder = collectGenericAddressExpressions ( F ) ; ValueToAddrSpaceMapTy InferredAddrSpace ; inferAddressSpaces ( Postorder , & InferredAddrSpace ) ; return rewriteWithNewAddressSpaces ( Postorder , InferredAddrSpace , & F ) ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> const MCExpr * SparcELFTargetObjectFile :: getTTypeGlobalReference ( const GlobalValue * GV , unsigned Encoding , Mangler & Mang , const TargetMachine & TM , MachineModuleInfo * MMI , MCStreamer & Streamer ) const { if ( Encoding & dwarf :: DW_EH_PE_pcrel ) { MachineModuleInfoELF & ELFMMI = MMI -> getObjFileInfo < MachineModuleInfoELF > ( ) ; MCSymbol * SSym = getSymbolWithGlobalValueBase ( GV , ".DW.stub" , Mang , TM ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = ELFMMI . getGVStubEntry ( SSym ) ; if ( ! StubSym . getPointer ( ) ) { MCSymbol * Sym = TM . getSymbol ( GV , Mang ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Sym , ! GV -> hasLocalLinkage ( ) ) ; } MCContext & Ctx = getContext ( ) ; return SparcMCExpr :: Create ( SparcMCExpr :: VK_Sparc_R_DISP32 , MCSymbolRefExpr :: Create ( SSym , Ctx ) , Ctx ) ; } return TargetLoweringObjectFileELF :: getTTypeGlobalReference ( GV , Encoding , Mang , TM , MMI , Streamer ) ; } </s>

The mach-o version of this method defaults to returning a stub reference .


<s> int ARMAsmParser :: tryParseRegister ( ) { MCAsmParser & Parser = getParser ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return - 1 ; std :: string lowerCase = Tok . getString ( ) . lower ( ) ; unsigned RegNum = MatchRegisterName ( lowerCase ) ; if ( ! RegNum ) { RegNum = StringSwitch < unsigned > ( lowerCase ) . Case ( "r13" , ARM :: SP ) . Case ( "r14" , ARM :: LR ) . Case ( "r15" , ARM :: PC ) . Case ( "ip" , ARM :: R12 ) . Case ( "a1" , ARM :: R0 ) . Case ( "a2" , ARM :: R1 ) . Case ( "a3" , ARM :: R2 ) . Case ( "a4" , ARM :: R3 ) . Case ( "v1" , ARM :: R4 ) . Case ( "v2" , ARM :: R5 ) . Case ( "v3" , ARM :: R6 ) . Case ( "v4" , ARM :: R7 ) . Case ( "v5" , ARM :: R8 ) . Case ( "v6" , ARM :: R9 ) . Case ( "v7" , ARM :: R10 ) . Case ( "v8" , ARM :: R11 ) . Case ( "sb" , ARM :: R9 ) . Case ( "sl" , ARM :: R10 ) . Case ( "fp" , ARM :: R11 ) . Default ( 0 ) ; } if ( ! RegNum ) { StringMap < unsigned > :: const_iterator Entry = RegisterReqs . find ( lowerCase ) ; if ( Entry == RegisterReqs . end ( ) ) return - 1 ; Parser . Lex ( ) ; return Entry -> getValue ( ) ; } if ( hasD16 ( ) && RegNum >= ARM :: D16 && RegNum <= ARM :: D31 ) return - 1 ; Parser . Lex ( ) ; return RegNum ; } </s>

tryParseRegister - parse one register if possible


"Copy one register into another with a different width"


<s> static bool c6x_return_in_msb ( const_tree valtype ) { HOST_WIDE_INT size = int_size_in_bytes ( valtype ) ; return TARGET_BIG_ENDIAN && AGGREGATE_TYPE_P ( valtype ) && size == 3 ; } </s>

Values which must be returned in the most-significant end of the return register .


<s>
bool
FPS
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
bool
FPIsUsed
=
false
;
assert
(
X86
::
FP6
==
X86
::
FP0
+
6
&&
"Register enums aren't sorted right!"
)
;
for
(
unsigned
i
=
0
;
i
<=
6
;
++
i
)
if
(
MF
.
getRegInfo
(
)
.
isPhysRegUsed
(
X86
::
FP0
+
i
)
)
{
FPIsUsed
=
true
;
break
;
}
if
(
!
FPIsUsed
)
return
false
;
TII
=
MF
.
getTarget
(
)
.
getInstrInfo
(
)
;
StackTop
=
0
;
SmallPtrSet
<
MachineBasicBlock
*
,
8
>
Processed
;
MachineBasicBlock
*
Entry
=
MF
.
begin
(
)
;
bool
Changed
=
false
;
for
(
df_ext_iterator
<
MachineBasicBlock
*
,
SmallPtrSet
<
MachineBasicBlock
*
,
8
>
>
I
=
df_ext_begin
(
Entry
,
Processed
)
,
E
=
df_ext_end
(
Entry
,
Processed
)
;
I
!=
E
;
++
I
)
Changed
|=
processBasicBlock
(
MF
,
*
*
I
)
;
return
Changed
;
}
</s>


<s> const X86RegisterInfo * getRegisterInfo ( ) const override { return & getInstrInfo ( ) -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static bool c6x_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { if ( to == STACK_POINTER_REGNUM ) return ! frame_pointer_needed ; return true ; } </s>

Given FROM and TO register numbers , say whether this elimination is allowed . Frame pointer elimination is automatically handled .


<s> void crx_expand_prologue ( void ) { crx_compute_frame ( ) ; crx_compute_save_regs ( ) ; if ( size_for_adjusting_sp + sum_regs == 0 ) return ; if ( last_reg_to_save != - 1 ) emit_insn ( gen_push_for_prologue ( GEN_INT ( sum_regs ) ) ) ; if ( size_for_adjusting_sp > 0 ) emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - size_for_adjusting_sp ) ) ) ; if ( frame_pointer_needed ) emit_move_insn ( frame_pointer_rtx , stack_pointer_rtx ) ; } </s>

CompactRISC CRX Architecture stack layout : 0 + -- -- -- -- -- -- -- -- -- -- - | . . | +==================== Sp ( x ) =Ap ( x+1 ) A | Args for functions | | called by X and Dynamically | | Dynamic allocations allocated and | | ( alloca , variable deallocated Stack | length arrays ) . grows + -- -- -- -- -- -- -- -- -- -- Fp ( x ) down| | Local variables of X ward| + -- -- -- -- -- -- -- -- -- -- | | Regs saved for X-1 | +==================== Sp ( x-1 ) =Ap ( x ) | Args for func X | pushed by X-1 + -- -- -- -- -- -- -- -- -- -- Fp ( x-1 ) | | V


"Retrying function scheduling with lowest recorded occupancy "

After the schedule has been formed , call this function to combine the instructions from the different stages/cycles .


<s> static rtx_insn * maybe_dead_move ( rtx dest , rtx src , bool ATTRIBUTE_UNUSED maybe_dead_p ) { rtx_insn * insn = emit_move_insn ( dest , src ) ; if ( maybe_dead_p ) REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_MAYBE_DEAD , const0_rtx , NULL ) ; return insn ; } </s>

Move SRC to DEST . Mark the move as being potentially dead if MAYBE_DEAD_P .


<s> bool AArch64PreLegalizerCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: FailedISel ) ) return false ; auto * TPC = & getAnalysis < TargetPassConfig > ( ) ; const Function & F = MF . getFunction ( ) ; bool EnableOpt = MF . getTarget ( ) . getOptLevel ( ) != CodeGenOpt :: None && ! skipFunction ( F ) ; GISelKnownBits * KB = & getAnalysis < GISelKnownBitsAnalysis > ( ) . get ( MF ) ; MachineDominatorTree * MDT = IsOptNone ? nullptr : & getAnalysis < MachineDominatorTree > ( ) ; AArch64PreLegalizerCombinerInfo PCInfo ( EnableOpt , F . hasOptSize ( ) , F . hasMinSize ( ) , KB , MDT ) ; Combiner C ( PCInfo , TPC ) ; return C . combineMachineInstrs ( MF , nullptr ) ; } </s>


<s> bool z8k_mode_dependent_address ( const_rtx addr , addr_space_t addr_space ATTRIBUTE_UNUSED ) { return ( GET_CODE ( addr ) == POST_INC || GET_CODE ( addr ) == PRE_DEC ) ; } </s>

emit_move_insn ( gen_rtx_MEM ( Pmode , plus_constant ( Pmode , tramp , 2 ) ) , cxt ) ; emit_move_insn ( gen_rtx_MEM ( Pmode , plus_constant ( Pmode , tramp , 8 ) ) , fnaddr ) ; } else { emit_move_insn ( gen_rtx_MEM ( HImode , plus_constant ( Pmode , tramp , 2 ) ) , cxt ) ; emit_move_insn ( gen_rtx_MEM ( HImode , plus_constant ( Pmode , tramp , 6 ) ) , fnaddr ) ; } } boolz8k_legitimate_constant_p ( enum machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { return GET_CODE ( x ) ! = CONST_DOUBLE ; } boolz8k_can_eliminate ( const int from , const int to ) { return ( ! frame_pointer_needed || ( ( from ) == ARG_POINTER_REGNUM & & ( to ) == FRAME_POINTER_REGNUM ) || ( ( from ) == RETURN_ADDRESS_POINTER_REGNUM & & ( to ) == FRAME_POINTER_REGNUM ) ) ; } Return whether ADDR ( a legitimate address expression ) has an effect that depends on the machine mode it is used for . For the z8k , pushing and popping needs to know the mode


<s> void pdp10_expand_prologue ( ) { int clobbered [ FIRST_PSEUDO_REGISTER ] ; int clobbered_size ; int stack_adjust ; int single_push ; clobbered_size = clobbered_regs ( clobbered ) ; single_push = clobbered_size == UNITS_PER_WORD && ( optimize_size || ! TARGET_EXTENDED ) && current_function_outgoing_args_size == 0 && current_function_pretend_args_size == 0 && get_frame_size ( ) == 0 ; stack_adjust = current_function_outgoing_args_size + get_frame_size ( ) + clobbered_size + current_function_pretend_args_size ; if ( ! single_push && stack_adjust > 0 ) emit_frame_insn ( pdp10_gen_stack_adjust ( GEN_INT ( stack_adjust / 4 ) ) ) ; expand_save_or_restore_return_address ( SAVE , clobbered_size ) ; expand_save_or_restore_regs ( SAVE , clobbered , clobbered_size , single_push ) ; expand_set_up_frame_pointer ( ) ; } </s>


Return an array that contains the bitmask target flag values and their names .

PowerPC PPC PPC "ppc-plt" "ppc-pic" "ppc-pcrel" "ppc-got"


<s> void s390_expand_vcond ( rtx target , rtx then , rtx els , enum rtx_code cond , rtx cmp_op1 , rtx cmp_op2 ) { rtx tmp ; machine_mode result_mode ; rtx result_target ; machine_mode target_mode = GET_MODE ( target ) ; machine_mode cmp_mode = GET_MODE ( cmp_op1 ) ; rtx op = ( cond == LT ) ? els : then ; if ( ( cond == LT || cond == GE ) && target_mode == cmp_mode && cmp_op2 == CONST0_RTX ( cmp_mode ) && op == CONST0_RTX ( target_mode ) && s390_vector_mode_supported_p ( target_mode ) && GET_MODE_CLASS ( target_mode ) == MODE_VECTOR_INT ) { rtx negop = ( cond == LT ) ? then : els ; int shift = GET_MODE_BITSIZE ( GET_MODE_INNER ( target_mode ) ) - 1 ; if ( negop == CONST1_RTX ( target_mode ) ) { rtx res = expand_simple_binop ( cmp_mode , LSHIFTRT , cmp_op1 , GEN_INT ( shift ) , target , 1 , OPTAB_DIRECT ) ; if ( res != target ) emit_move_insn ( target , res ) ; return ; } else if ( all_ones_operand ( negop , target_mode ) ) { rtx res = expand_simple_binop ( cmp_mode , ASHIFTRT , cmp_op1 , GEN_INT ( shift ) , target , 0 , OPTAB_DIRECT ) ; if ( res != target ) emit_move_insn ( target , res ) ; return ; } } result_mode = mode_for_int_vector ( cmp_mode ) . require ( ) ; result_target = gen_reg_rtx ( result_mode ) ; if ( ! REG_P ( cmp_op1 ) ) cmp_op1 = force_reg ( GET_MODE ( cmp_op1 ) , cmp_op1 ) ; if ( ! REG_P ( cmp_op2 ) ) cmp_op2 = force_reg ( GET_MODE ( cmp_op2 ) , cmp_op2 ) ; s390_expand_vec_compare ( result_target , cond , cmp_op1 , cmp_op2 ) ; if ( all_ones_operand ( then , GET_MODE ( then ) ) && const0_operand ( els , GET_MODE ( els ) ) ) { emit_move_insn ( target , gen_rtx_SUBREG ( target_mode , result_target , 0 ) ) ; return ; } if ( ! REG_P ( then ) ) then = force_reg ( target_mode , then ) ; if ( ! REG_P ( els ) ) els = force_reg ( target_mode , els ) ; tmp = gen_rtx_fmt_ee ( EQ , VOIDmode , result_target , CONST0_RTX ( result_mode ) ) ; tmp = gen_rtx_IF_THEN_ELSE ( target_mode , tmp , els , then ) ; gcc_assert ( target_mode == GET_MODE ( then ) ) ; emit_insn ( gen_rtx_SET ( target , tmp ) ) ; } </s>

Generate a vector comparison expression loading either elements of THEN or ELS into TARGET depending on the comparison COND of CMP_OP1 and CMP_OP2 .


<s> virtual const SPUSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> const AArch64RegisterInfo * getRegisterInfo ( ) const override { return & getInstrInfo ( ) -> getRegisterInfo ( ) ; } </s>


<s> int rs6000_memory_move_cost ( enum machine_mode mode , enum reg_class class , int in ATTRIBUTE_UNUSED ) { if ( reg_classes_intersect_p ( class , GENERAL_REGS ) ) return 4 * hard_regno_nregs [ 0 ] [ mode ] ; else if ( reg_classes_intersect_p ( class , FLOAT_REGS ) ) return 4 * hard_regno_nregs [ 32 ] [ mode ] ; else if ( reg_classes_intersect_p ( class , ALTIVEC_REGS ) ) return 4 * hard_regno_nregs [ FIRST_ALTIVEC_REGNO ] [ mode ] ; else return 4 + rs6000_register_move_cost ( mode , class , GENERAL_REGS ) ; } </s>

A C expressions returning the cost of moving data of MODE from a register to or from memory .


<s> bool JVMTargetLowering :: CanLowerReturn ( CallingConv :: ID , MachineFunction & , bool , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & ) const { return Outs . size ( ) <= 1 ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> static bool dispatch_violation ( void ) { if ( dispatch_window_list -> next ) return dispatch_window_list -> next -> violation ; return dispatch_window_list -> violation ; } </s>

Return true if a dispatch violation encountered .


<s> static int eco32_num_arg_regs ( enum machine_mode mode , const_tree type ) { int size ; if ( targetm . calls . must_pass_in_stack ( mode , type ) ) return 0 ; if ( type && mode == BLKmode ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; return ( size + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } </s>

Compute the number of word sized registers needed to hold a function argument of mode INT_MODE and tree type TYPE .


<s> static bool aarch64_rtx_arith_op_extract_p ( rtx x , machine_mode mode ) { if ( GET_CODE ( x ) == SIGN_EXTRACT || GET_CODE ( x ) == ZERO_EXTRACT ) { rtx op0 = XEXP ( x , 0 ) ; rtx op1 = XEXP ( x , 1 ) ; rtx op2 = XEXP ( x , 2 ) ; if ( GET_CODE ( op0 ) == MULT && CONST_INT_P ( op1 ) && op2 == const0_rtx && CONST_INT_P ( XEXP ( op0 , 1 ) ) && aarch64_is_extend_from_extract ( mode , XEXP ( op0 , 1 ) , op1 ) ) { return true ; } } else if ( GET_CODE ( x ) == SIGN_EXTEND || GET_CODE ( x ) == ZERO_EXTEND ) return REG_P ( XEXP ( x , 0 ) ) ; return false ; } </s>

Return true if X is a zero or sign extract usable in an ADD or SUB ( extended register ) instruction .


<s> void ScheduleDAGPostRA :: startBlock ( MachineBasicBlock * BB ) { ScheduleDAGInstrs :: startBlock ( BB ) ; if ( AntiDepBreak != NULL ) AntiDepBreak -> StartBlock ( BB ) ; } </s>

Prepares to perform scheduling in the given block .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s>
InstructionCost
PPCTTIImpl
::
getArithmeticInstrCost
(
unsigned
Opcode
,
Type
*
Ty
,
TTI
::
TargetCostKind
CostKind
,
TTI
::
OperandValueKind
Op1Info
,
TTI
::
OperandValueKind
Op2Info
,
TTI
::
OperandValueProperties
Opd1PropInfo
,
TTI
::
OperandValueProperties
Opd2PropInfo
,
ArrayRef
<
const
Value
*
>
Args
,
const
Instruction
*
CxtI
)
{
assert
(
TLI
->
InstructionOpcodeToISD
(
Opcode
)
&&
"Invalid opcode"
)
;
InstructionCost
CostFactor
=
vectorCostAdjustmentFactor
(
Opcode
,
Ty
,
nullptr
)
;
if
(
!
CostFactor
.
isValid
(
)
)
return
InstructionCost
::
getMax
(
)
;
if
(
CostKind
!=
TTI
::
TCK_RecipThroughput
)
return
BaseT
::
getArithmeticInstrCost
(
Opcode
,
Ty
,
CostKind
,
Op1Info
,
Op2Info
,
Opd1PropInfo
,
Opd2PropInfo
,
Args
,
CxtI
)
;
InstructionCost
Cost
=
BaseT
::
getArithmeticInstrCost
(
Opcode
,
Ty
,
CostKind
,
Op1Info
,
Op2Info
,
Opd1PropInfo
,
Opd2PropInfo
)
;
return
Cost
*
CostFactor
;
}
</s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> std :: pair < unsigned , const TargetRegisterClass * > AlphaTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , Alpha :: GPRCRegisterClass ) ; case 'f' : return VT == MVT :: f64 ? std :: make_pair ( 0U , Alpha :: F8RCRegisterClass ) : std :: make_pair ( 0U , Alpha :: F4RCRegisterClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s>
void
print
(
)
{
if
(
numSymbols
==
0
)
{
for
(
unsigned
i
=
0
;
i
<
size
;
i
++
)
{
if
(
i
)
O
<<
", "
;
O
<<
(
unsigned
int
)
buffer
[
i
]
;
}
}
else
{
unsigned
int
pos
=
0
;
unsigned
int
nSym
=
0
;
unsigned
int
nextSymbolPos
=
symbolPosInBuffer
[
nSym
]
;
unsigned
int
nBytes
=
4
;
if
(
static_cast
<
const
NVPTXTargetMachine
&
>
(
AP
.
TM
)
.
is64Bit
(
)
)
nBytes
=
8
;
for
(
pos
=
0
;
pos
<
size
;
pos
+=
nBytes
)
{
if
(
pos
)
O
<<
", "
;
if
(
pos
==
nextSymbolPos
)
{
const
Value
*
v
=
Symbols
[
nSym
]
;
const
Value
*
v0
=
SymbolsBeforeStripping
[
nSym
]
;
if
(
const
GlobalValue
*
GVar
=
dyn_cast
<
GlobalValue
>
(
v
)
)
{
MCSymbol
*
Name
=
AP
.
getSymbol
(
GVar
)
;
PointerType
*
PTy
=
dyn_cast
<
PointerType
>
(
v0
->
getType
(
)
)
;
bool
IsNonGenericPointer
=
false
;
if
(
PTy
&&
PTy
->
getAddressSpace
(
)
!=
0
)
{
IsNonGenericPointer
=
true
;
}
if
(
EmitGeneric
&&
!
isa
<
Function
>
(
v
)
&&
!
IsNonGenericPointer
)
{
O
<<
"generic("
;
Name
->
print
(
O
,
AP
.
MAI
)
;
O
<<
")"
;
}
else
{
Name
->
print
(
O
,
AP
.
MAI
)
;
}
}
else
if
(
const
ConstantExpr
*
CExpr
=
dyn_cast
<
ConstantExpr
>
(
v0
)
)
{
const
MCExpr
*
Expr
=
AP
.
lowerConstantForGV
(
cast
<
Constant
>
(
CExpr
)
,
false
)
;
AP
.
printMCExpr
(
*
Expr
,
O
)
;
}
else
llvm_unreachable
(
"symbol type unknown"
)
;
nSym
++
;
if
(
nSym
>=
numSymbols
)
nextSymbolPos
=
size
+
1
;
else
nextSymbolPos
=
symbolPosInBuffer
[
nSym
]
;
}
else
if
(
nBytes
==
4
)
O
<<
*
(
unsigned
int
*
)
(
&
buffer
[
pos
]
)
;
else
O
<<
*
(
unsigned
long
long
*
)
(
&
buffer
[
pos
]
)
;
}
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> void bfin_expand_call ( rtx retval , rtx fnaddr , rtx callarg1 , rtx cookie , int sibcall ) { rtx use = NULL , call ; rtx callee = XEXP ( fnaddr , 0 ) ; rtx pat = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( sibcall ? 3 : 2 ) ) ; if ( cookie == NULL_RTX ) cookie = const0_rtx ; if ( flag_pic && GET_CODE ( callee ) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P ( callee ) ) use_reg ( & use , pic_offset_table_rtx ) ; if ( ( ! register_no_elim_operand ( callee , Pmode ) && GET_CODE ( callee ) != SYMBOL_REF ) || ( GET_CODE ( callee ) == SYMBOL_REF && ( flag_pic || bfin_longcall_p ( callee , INTVAL ( cookie ) ) ) ) ) { callee = copy_to_mode_reg ( Pmode , callee ) ; fnaddr = gen_rtx_MEM ( Pmode , callee ) ; } call = gen_rtx_CALL ( VOIDmode , fnaddr , callarg1 ) ; if ( retval ) call = gen_rtx_SET ( VOIDmode , retval , call ) ; XVECEXP ( pat , 0 , 0 ) = call ; XVECEXP ( pat , 0 , 1 ) = gen_rtx_USE ( VOIDmode , cookie ) ; if ( sibcall ) XVECEXP ( pat , 0 , 2 ) = gen_rtx_RETURN ( VOIDmode ) ; call = emit_call_insn ( pat ) ; if ( use ) CALL_INSN_FUNCTION_USAGE ( call ) = use ; } </s>

Expand a call instruction . FNADDR is the call target , RETVAL the return value . COOKIE is a CONST_INT holding the call_cookie prepared init_cumulative_args . SIBCALL is nonzero if this is a sibling call .


"M-extension must be enabled to calculate the poly_int "

Expand mult operation with constant integer , multiplicand also used as a * temporary register .


<s>
StringRef
getPassName
(
)
const
override
{
return
"SI Fix VGPR copies"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> SDValue P2TargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: GlobalAddress : return lowerGlobalAddress ( Op , DAG ) ; case ISD :: VASTART : return lowerVASTART ( Op , DAG ) ; case ISD :: VAARG : return lowerVAARG ( Op , DAG ) ; case ISD :: JumpTable : return lowerJumpTable ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

P2 P2 ISD::GlobalAddress ISD::VASTART ISD::VAARG ISD::JumpTable


"After Machine LICM, CSE and Sinking passes"

"After codegen peephole optimization pass"

Methods with trivial inline returns are convenient points in the common codegen pass pipeline where targets may insert passes .


<s> bool ARMFrameLowering :: enableShrinkWrapping ( const MachineFunction & MF ) const { if ( STI . hasV8_1MMainlineOps ( ) && MF . getInfo < ARMFunctionInfo > ( ) -> isCmseNSEntryFunction ( ) ) return false ; return true ; } </s>

Returns true if the target will correctly handle shrink wrapping .


<s> bool PPCTTIImpl :: canSaveCmp ( Loop * L , BranchInst * * BI , ScalarEvolution * SE , LoopInfo * LI , DominatorTree * DT , AssumptionCache * AC , TargetLibraryInfo * LibInfo ) { for ( Loop :: iterator I = L -> begin ( ) , E = L -> end ( ) ; I != E ; ++ I ) if ( canSaveCmp ( * I , BI , SE , LI , DT , AC , LibInfo ) ) return false ; HardwareLoopInfo HWLoopInfo ( L ) ; if ( ! HWLoopInfo . canAnalyze ( * LI ) ) return false ; if ( ! isHardwareLoopProfitable ( L , * SE , * AC , LibInfo , HWLoopInfo ) ) return false ; if ( ! HWLoopInfo . isHardwareLoopCandidate ( * SE , * LI , * DT ) ) return false ; * BI = HWLoopInfo . ExitBranch ; return true ; } </s>

Return true if the target can save a compare for loop count , for example hardware loop saves a compare .


<s> static void ix86_emit_mode_set ( int entity , int mode , int prev_mode ATTRIBUTE_UNUSED , HARD_REG_SET regs_live ) { switch ( entity ) { case X86_DIRFLAG : if ( mode == X86_DIRFLAG_RESET ) emit_insn ( gen_cld ( ) ) ; break ; case AVX_U128 : if ( mode == AVX_U128_CLEAN ) ix86_avx_emit_vzeroupper ( regs_live ) ; break ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : case I387_MASK_PM : if ( mode != I387_CW_ANY && mode != I387_CW_UNINITIALIZED ) emit_i387_cw_initialization ( mode ) ; break ; default : gcc_unreachable ( ) ; } } </s>

Generate one or more insns to set ENTITY to MODE . HARD_REG_LIVE is the set of hard registers live at the point where the insn ( s ) are to be inserted .


<s> bool VEPassConfig :: addInstSelector ( ) { addPass ( createVEISelDag ( getVETargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static bool is_costly_group ( rtx * group_insns , rtx next_insn ) { int i ; int issue_rate = rs6000_issue_rate ( ) ; for ( i = 0 ; i < issue_rate ; i ++ ) { sd_iterator_def sd_it ; dep_t dep ; rtx insn = group_insns [ i ] ; if ( ! insn ) continue ; FOR_EACH_DEP ( insn , SD_LIST_RES_FORW , sd_it , dep ) { rtx next = DEP_CON ( dep ) ; if ( next == next_insn && rs6000_is_costly_dependence ( dep , dep_cost ( dep ) , 0 ) ) return true ; } } return false ; } </s>

Return true if it is recommended to keep NEXT_INSN `` far '' ( in a separate dispatch group ) from the insns in GROUP_INSNS . Return false otherwise .


<s>
const
char
*
avr_double_lib
(
int
argc
,
const
char
*
*
argv
)
{
int
dbl
=
64
;
int
dbl
=
32
;
int
ldb
=
64
;
int
ldb
=
32
;
for
(
int
i
=
0
;
i
<
argc
;
i
++
)
{
if
(
strcmp
(
argv
[
i
]
,
"mdouble=32"
)
==
0
)
{
dbl
=
32
;
ldb
=
dbl
;
}
else
if
(
strcmp
(
argv
[
i
]
,
"mdouble=64"
)
==
0
)
{
ldb
=
dbl
=
64
;
}
else
if
(
strcmp
(
argv
[
i
]
,
"mlong-double=32"
)
==
0
)
{
ldb
=
dbl
=
32
;
}
else
if
(
strcmp
(
argv
[
i
]
,
"mlong-double=64"
)
==
0
)
{
ldb
=
64
;
dbl
=
ldb
;
}
}
return
concat
(
" %<mdouble=* -mdouble="
,
dbl
==
32
"32"
:
"64"
,
" %<mlong-double=* -mlong-double="
,
ldb
==
32
"32"
:
"64"
,
)
;
}
</s>

Re-build the -mdouble= and -mlong-double= options . This is needed because these options are not independent of each other .


<s> BitVector MipsRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const unsigned ReservedCPURegs [ ] = { Mips :: ZERO , Mips :: AT , Mips :: K0 , Mips :: K1 , Mips :: GP , Mips :: SP , Mips :: FP , Mips :: RA , 0 } ; static const unsigned ReservedCPU64Regs [ ] = { Mips :: ZERO_64 , Mips :: AT_64 , Mips :: K0_64 , Mips :: K1_64 , Mips :: GP_64 , Mips :: SP_64 , Mips :: FP_64 , Mips :: RA_64 , 0 } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: iterator RegIter ; for ( const unsigned * Reg = ReservedCPURegs ; * Reg ; ++ Reg ) Reserved . set ( * Reg ) ; if ( Subtarget . hasMips64 ( ) ) { for ( const unsigned * Reg = ReservedCPU64Regs ; * Reg ; ++ Reg ) Reserved . set ( * Reg ) ; for ( RegIter Reg = Mips :: AFGR64RegisterClass -> begin ( ) ; Reg != Mips :: AFGR64RegisterClass -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ; } else { for ( RegIter Reg = Mips :: CPU64RegsRegisterClass -> begin ( ) ; Reg != Mips :: CPU64RegsRegisterClass -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ; for ( RegIter Reg = Mips :: FGR64RegisterClass -> begin ( ) ; Reg != Mips :: FGR64RegisterClass -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


"Function 'main' can't be interrupt function"

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> void ARCPassConfig :: addPreEmitPass ( ) { addPass ( createARCBranchFinalizePass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool TL45PassConfig :: addPreISel ( ) { return false ; } </s>


<s> void s390_expand_logical_operator ( enum rtx_code code , enum machine_mode mode , rtx * operands ) { enum machine_mode wmode = mode ; rtx dst = operands [ 0 ] ; rtx src1 = operands [ 1 ] ; rtx src2 = operands [ 2 ] ; rtx op , clob , tem ; if ( ! s390_logical_operator_ok_p ( operands ) ) dst = gen_reg_rtx ( mode ) ; if ( ( mode == QImode || mode == HImode ) && GET_CODE ( dst ) != MEM ) wmode = SImode ; if ( mode != wmode ) { if ( GET_CODE ( dst ) == SUBREG && ( tem = simplify_subreg ( wmode , dst , mode , 0 ) ) != 0 ) dst = tem ; else if ( REG_P ( dst ) ) dst = gen_rtx_SUBREG ( wmode , dst , 0 ) ; else dst = gen_reg_rtx ( wmode ) ; if ( GET_CODE ( src1 ) == SUBREG && ( tem = simplify_subreg ( wmode , src1 , mode , 0 ) ) != 0 ) src1 = tem ; else if ( GET_MODE ( src1 ) != VOIDmode ) src1 = gen_rtx_SUBREG ( wmode , force_reg ( mode , src1 ) , 0 ) ; if ( GET_CODE ( src2 ) == SUBREG && ( tem = simplify_subreg ( wmode , src2 , mode , 0 ) ) != 0 ) src2 = tem ; else if ( GET_MODE ( src2 ) != VOIDmode ) src2 = gen_rtx_SUBREG ( wmode , force_reg ( mode , src2 ) , 0 ) ; } op = gen_rtx_SET ( VOIDmode , dst , gen_rtx_fmt_ee ( code , wmode , src1 , src2 ) ) ; clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , CC_REGNUM ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , op , clob ) ) ) ; if ( dst != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , gen_lowpart ( mode , dst ) ) ; } </s>

Expand logical operator CODE in mode MODE with operands OPERANDS .


<s> void assignValueToAddress ( const CallLowering :: ArgInfo & Arg , unsigned ValRegIndex , Register Addr , uint64_t MemSize , MachinePointerInfo & MPO , CCValAssign & VA ) override { Register ValVReg = VA . getLocInfo ( ) != CCValAssign :: LocInfo :: FPExt ? extendRegister ( Arg . Regs [ ValRegIndex ] , VA ) : Arg . Regs [ ValRegIndex ] ; const LLT RegTy = MRI . getType ( ValVReg ) ; MemSize = std :: min ( MemSize , ( uint64_t ) RegTy . getSizeInBytes ( ) ) ; assignValueToAddress ( ValVReg , Addr , MemSize , MPO , VA ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> int store_update_operand ( rtx op , enum machine_mode mode ) { if ( GET_CODE ( op ) != MEM || GET_MODE ( op ) != mode ) return 0 ; op = XEXP ( op , 0 ) ; if ( GET_CODE ( op ) != PLUS || GET_MODE ( op ) != Pmode || ! register_operand ( XEXP ( op , 0 ) , Pmode ) || ! ( GET_CODE ( XEXP ( op , 1 ) ) == CONST_INT && SMALL_INT ( INTVAL ( XEXP ( op , 1 ) ) ) ) ) return 0 ; return 1 ; } </s>

Return true if OP is valid store with update operand .


<s> bool isMem ( ) const override { return Kind == k_Memory ; } </s>


<s>
SDValue
PTXTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
if
(
isVarArg
)
llvm_unreachable
(
"PTX does not support varargs"
)
;
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
PTXMachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
PTXMachineFunctionInfo
>
(
)
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
break
;
case
CallingConv
::
PTX_Kernel
:
MFI
->
setKernel
(
true
)
;
break
;
case
CallingConv
::
PTX_Device
:
MFI
->
setKernel
(
false
)
;
break
;
}
if
(
MFI
->
isDoneAddArg
(
)
)
llvm_unreachable
(
"cannot add argument registers twice"
)
;
for
(
struct
argmap_entry
*
i
=
argmap
,
*
e
=
argmap
+
array_lengthof
(
argmap
)
;
i
!=
e
;
++
i
)
i
->
reset
(
)
;
for
(
int
i
=
0
,
e
=
Ins
.
size
(
)
;
i
!=
e
;
++
i
)
{
MVT
::
SimpleValueType
VT
=
Ins
[
i
]
.
VT
.
SimpleTy
;
struct
argmap_entry
*
entry
=
std
::
find
(
argmap
,
argmap
+
array_lengthof
(
argmap
)
,
VT
)
;
if
(
entry
==
argmap
+
array_lengthof
(
argmap
)
)
llvm_unreachable
(
"Type of argument is not supported"
)
;
if
(
MFI
->
isKernel
(
)
&&
entry
->
RC
==
PTX
::
PredsRegisterClass
)
llvm_unreachable
(
"cannot pass preds to kernel"
)
;
MachineRegisterInfo
&
RegInfo
=
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
;
unsigned
preg
=
*
++
(
entry
->
loc
)
;
unsigned
vreg
=
RegInfo
.
createVirtualRegister
(
entry
->
RC
)
;
RegInfo
.
addLiveIn
(
preg
,
vreg
)
;
MFI
->
addArgReg
(
preg
)
;
SDValue
inval
;
if
(
MFI
->
isKernel
(
)
)
inval
=
DAG
.
getNode
(
PTXISD
::
READ_PARAM
,
dl
,
VT
,
Chain
,
DAG
.
getTargetConstant
(
i
,
MVT
::
i32
)
)
;
else
inval
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
vreg
,
VT
)
;
InVals
.
push_back
(
inval
)
;
}
MFI
->
doneAddArg
(
)
;
return
Chain
;
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .

PTX
PTX
ISD::InputArg
"PTX does not support varargs"
PTX
PTX
"Unsupported calling convention"
PTX
PTX
"cannot add argument registers twice"
0
MVT::SimpleValueType
"Type of argument is not supported"
PTX::PredsRegisterClass
"cannot pass preds to kernel"
PTXISD::READ_PARAM
MVT::i32


<s> bool HexagonInstrInfo :: analyzeCompare ( const MachineInstr * MI , unsigned & SrcReg , unsigned & SrcReg2 , int & Mask , int & Value ) const { unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case Hexagon :: C2_cmpeqp : case Hexagon :: C2_cmpeqi : case Hexagon :: C2_cmpeq : case Hexagon :: C2_cmpgtp : case Hexagon :: C2_cmpgtup : case Hexagon :: C2_cmpgtui : case Hexagon :: C2_cmpgtu : case Hexagon :: C2_cmpgti : case Hexagon :: C2_cmpgt : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; Mask = ~ 0 ; break ; case Hexagon :: A4_cmpbeqi : case Hexagon :: A4_cmpbeq : case Hexagon :: A4_cmpbgtui : case Hexagon :: A4_cmpbgtu : case Hexagon :: A4_cmpbgt : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; Mask = 0xFF ; break ; case Hexagon :: A4_cmpheqi : case Hexagon :: A4_cmpheq : case Hexagon :: A4_cmphgtui : case Hexagon :: A4_cmphgtu : case Hexagon :: A4_cmphgt : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; Mask = 0xFFFF ; break ; } switch ( Opc ) { case Hexagon :: C2_cmpeqp : case Hexagon :: C2_cmpeq : case Hexagon :: C2_cmpgtp : case Hexagon :: C2_cmpgtup : case Hexagon :: C2_cmpgtu : case Hexagon :: C2_cmpgt : case Hexagon :: A4_cmpbeq : case Hexagon :: A4_cmpbgtu : case Hexagon :: A4_cmpbgt : case Hexagon :: A4_cmpheq : case Hexagon :: A4_cmphgtu : case Hexagon :: A4_cmphgt : SrcReg2 = MI -> getOperand ( 2 ) . getReg ( ) ; return true ; case Hexagon :: C2_cmpeqi : case Hexagon :: C2_cmpgtui : case Hexagon :: C2_cmpgti : case Hexagon :: A4_cmpbeqi : case Hexagon :: A4_cmpbgtui : case Hexagon :: A4_cmpheqi : case Hexagon :: A4_cmphgtui : SrcReg2 = 0 ; Value = MI -> getOperand ( 2 ) . getImm ( ) ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> static void ix86_emit_probe_stack_range ( HOST_WIDE_INT first , HOST_WIDE_INT size ) { if ( size <= 7 * PROBE_INTERVAL ) { HOST_WIDE_INT i ; for ( i = PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + i ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + size ) ) ) ; } else { HOST_WIDE_INT rounded_size , last ; struct scratch_reg sr ; get_scratch_register_on_entry ( & sr ) ; rounded_size = size & - PROBE_INTERVAL ; emit_move_insn ( sr . reg , GEN_INT ( - first ) ) ; last = first + rounded_size ; emit_insn ( ix86_gen_probe_stack_range ( sr . reg , sr . reg , GEN_INT ( - last ) ) ) ; if ( size != rounded_size ) emit_stack_probe ( plus_constant ( Pmode , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , sr . reg ) , rounded_size - size ) ) ; release_scratch_register_on_entry ( & sr ) ; } emit_insn ( gen_blockage ( ) ) ; } </s>

Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE , inclusive . These are offsets from the current stack pointer .


<s> void SIInstrInfo :: swapOperands ( MachineInstr & Inst ) const { assert ( Inst . getNumExplicitOperands ( ) == 3 ) ; MachineOperand Op1 = Inst . getOperand ( 1 ) ; Inst . removeOperand ( 1 ) ; Inst . addOperand ( Op1 ) ; } </s>

Exchange the two operands to this instruction in such a way that it does not modify the semantics of the instruction .


<s> MachineBasicBlock :: iterator SHUXIFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const SHUXIInstrInfo & TII = * static_cast < const SHUXIInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; unsigned StackAlign = getStackAlignment ( ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr & Old = * I ; uint64_t Amount = Old . getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = nullptr ; if ( Old . getOpcode ( ) == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( SHUXI :: SUBri ) , SHUXI :: SP ) . addReg ( SHUXI :: SP ) . addImm ( Amount ) ; } else { assert ( Old . getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) ; uint64_t CalleeAmt = Old . getOperand ( 1 ) . getImm ( ) ; Amount -= CalleeAmt ; if ( Amount ) New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( SHUXI :: ADDri ) , SHUXI :: SP ) . addReg ( SHUXI :: SP ) . addImm ( Amount ) ; } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { MachineInstr & Old = * I ; MachineInstr * New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( SHUXI :: SUBri ) , SHUXI :: SP ) . addReg ( SHUXI :: SP ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static rtx rs6000_adjust_atomic_subword ( rtx orig_mem , rtx * pshift , rtx * pmask ) { rtx addr , align , shift , mask , mem ; HOST_WIDE_INT shift_mask ; machine_mode mode = GET_MODE ( orig_mem ) ; shift_mask = ( mode == QImode ? 0x18 : 0x10 ) ; addr = XEXP ( orig_mem , 0 ) ; addr = force_reg ( GET_MODE ( addr ) , addr ) ; align = expand_simple_binop ( Pmode , AND , addr , GEN_INT ( - 4 ) , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; mem = gen_rtx_MEM ( SImode , align ) ; MEM_VOLATILE_P ( mem ) = MEM_VOLATILE_P ( orig_mem ) ; if ( MEM_ALIAS_SET ( orig_mem ) == ALIAS_SET_MEMORY_BARRIER ) set_mem_alias_set ( mem , ALIAS_SET_MEMORY_BARRIER ) ; shift = gen_reg_rtx ( SImode ) ; addr = gen_lowpart ( SImode , addr ) ; rtx tmp = gen_reg_rtx ( SImode ) ; emit_insn ( gen_ashlsi3 ( tmp , addr , GEN_INT ( 3 ) ) ) ; emit_insn ( gen_andsi3 ( shift , tmp , GEN_INT ( shift_mask ) ) ) ; if ( BYTES_BIG_ENDIAN ) shift = expand_simple_binop ( SImode , XOR , shift , GEN_INT ( shift_mask ) , shift , 1 , OPTAB_LIB_WIDEN ) ; * pshift = shift ; mask = expand_simple_binop ( SImode , ASHIFT , GEN_INT ( GET_MODE_MASK ( mode ) ) , shift , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; * pmask = mask ; return mem ; } </s>

A subroutine of the various atomic expanders . For sub-word operations , we must adjust things to operate on SImode . Given the original MEM , return a new aligned memory . Also build and return the quantities by which to shift and mask .


<s> bool MSP430FrameInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) BuildMI ( MBB , MI , DL , TII . get ( MSP430 :: POP16r ) , CSI [ i ] . getReg ( ) ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool SIMemoryLegalizer :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; const IsaInfo :: IsaVersion IV = IsaInfo :: getIsaVersion ( ST . getFeatureBits ( ) ) ; MMI = & MF . getMMI ( ) . getObjFileInfo < AMDGPUMachineModuleInfo > ( ) ; TII = ST . getInstrInfo ( ) ; Vmcnt0Immediate = AMDGPU :: encodeWaitcnt ( IV , 0 , getExpcntBitMask ( IV ) , getLgkmcntBitMask ( IV ) ) ; Wbinvl1Opcode = ST . getGeneration ( ) <= AMDGPUSubtarget :: SOUTHERN_ISLANDS ? AMDGPU :: BUFFER_WBINVL1 : AMDGPU :: BUFFER_WBINVL1_VOL ; for ( auto & MBB : MF ) { for ( auto MI = MBB . begin ( ) ; MI != MBB . end ( ) ; ++ MI ) { if ( ! ( MI -> getDesc ( ) . TSFlags & SIInstrFlags :: maybeAtomic ) ) continue ; if ( const auto & MOI = SIMemOpInfo :: getLoadInfo ( MI ) ) Changed |= expandLoad ( MOI . getValue ( ) , MI ) ; else if ( const auto & MOI = SIMemOpInfo :: getStoreInfo ( MI ) ) Changed |= expandStore ( MOI . getValue ( ) , MI ) ; else if ( const auto & MOI = SIMemOpInfo :: getAtomicFenceInfo ( MI ) ) Changed |= expandAtomicFence ( MOI . getValue ( ) , MI ) ; else if ( const auto & MOI = SIMemOpInfo :: getAtomicCmpxchgInfo ( MI ) ) Changed |= expandAtomicCmpxchg ( MOI . getValue ( ) , MI ) ; else if ( const auto & MOI = SIMemOpInfo :: getAtomicRmwInfo ( MI ) ) Changed |= expandAtomicRmw ( MOI . getValue ( ) , MI ) ; } } Changed |= removeAtomicPseudoMIs ( ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .

AMDGPU SI SI SI AMDGPU AMDGPU::encodeWaitcnt 0 AMDGPU AMDGPU::BUFFER_WBINVL1 AMDGPU::BUFFER_WBINVL1_VOL SIInstrFlags::maybeAtomic SI SI SI SI SI


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesAll ( ) ; AU . addRequired < MachineModuleInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> int easy_df_const ( rtx op ) { long l [ 2 ] ; REAL_VALUE_TO_TARGET_DOUBLE ( * CONST_DOUBLE_REAL_VALUE ( op ) , l ) ; if ( l [ 0 ] == 0 && l [ 1 ] == 0 ) return 1 ; if ( ( l [ 0 ] & 0xffff ) == 0 && l [ 1 ] == 0 ) return 1 ; return 0 ; } </s>

Return 1 if OP is a DFmode const we want to handle inline . This must match the code in the movdf pattern . It is used by the ' H ' CONST_DOUBLE_OK_FOR_LETTER .


<s>
void
output_pop_multiple
(
rtx
insn
,
rtx
*
operands
)
{
char
buf
[
80
]
;
int
ok
;
ok
=
pop_multiple_operation
(
PATTERN
(
insn
)
,
VOIDmode
)
;
gcc_assert
(
ok
)
;
if
(
first_dreg_to_save
==
8
)
sprintf
(
buf
,
"( p5:%d ) = [sp++];\n"
,
first_preg_to_save
)
;
else
if
(
first_preg_to_save
==
6
)
sprintf
(
buf
,
"( r7:%d ) = [sp++];\n"
,
first_dreg_to_save
)
;
else
sprintf
(
buf
,
"( r7:%d, p5:%d ) = [sp++];\n"
,
first_dreg_to_save
,
first_preg_to_save
)
;
output_asm_insn
(
buf
,
operands
)
;
}
</s>

Emit assembly code for one multi-register pop described by INSN , with operands in OPERANDS .


<s> bool BlackfinRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> void avr_expand_prologue ( void ) { HARD_REG_SET set ; HOST_WIDE_INT size ; size = get_frame_size ( ) + avr_outgoing_args_size ( ) ; cfun -> machine -> stack_usage = 0 ; if ( cfun -> machine -> is_naked ) { return ; } avr_regs_to_save ( & set ) ; if ( cfun -> machine -> is_interrupt || cfun -> machine -> is_signal ) { if ( cfun -> machine -> is_interrupt ) emit_insn ( gen_enable_interrupt ( ) ) ; emit_push_byte ( AVR_ZERO_REGNO , true ) ; emit_push_byte ( AVR_TMP_REGNO , true ) ; emit_push_sfr ( sreg_rtx , false , false ) ; emit_move_insn ( zero_reg_rtx , const0_rtx ) ; emit_use ( zero_reg_rtx ) ; if ( AVR_HAVE_RAMPD ) emit_push_sfr ( rampd_rtx , false , true ) ; if ( AVR_HAVE_RAMPX && TEST_HARD_REG_BIT ( set , REG_X ) && TEST_HARD_REG_BIT ( set , REG_X + 1 ) ) { emit_push_sfr ( rampx_rtx , false , true ) ; } if ( AVR_HAVE_RAMPY && ( frame_pointer_needed || ( TEST_HARD_REG_BIT ( set , REG_Y ) && TEST_HARD_REG_BIT ( set , REG_Y + 1 ) ) ) ) { emit_push_sfr ( rampy_rtx , false , true ) ; } if ( AVR_HAVE_RAMPZ && TEST_HARD_REG_BIT ( set , REG_Z ) && TEST_HARD_REG_BIT ( set , REG_Z + 1 ) ) { emit_push_sfr ( rampz_rtx , false , AVR_HAVE_RAMPD ) ; } } avr_prologue_setup_frame ( size , set ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = cfun -> machine -> stack_usage ; } </s>


<s> void AVRPassConfig :: addIRPasses ( ) { addPass ( createAVRShiftExpandPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> bool HexagonBitSimplify :: isEqual ( const BitTracker :: RegisterCell & RC1 , uint16_t B1 , const BitTracker :: RegisterCell & RC2 , uint16_t B2 , uint16_t W ) { for ( uint16_t i = 0 ; i < W ; ++ i ) { if ( RC1 [ B1 + i ] . Type == BitTracker :: BitValue :: Ref && RC1 [ B1 + i ] . RefI . Reg == 0 ) return false ; if ( RC2 [ B2 + i ] . Type == BitTracker :: BitValue :: Ref && RC2 [ B2 + i ] . RefI . Reg == 0 ) return false ; if ( RC1 [ B1 + i ] != RC2 [ B2 + i ] ) return false ; } return true ; } </s>

isEqual - Compares two trees for structural equality and returns true if they are equal .


"frame pointer should not have been eliminated"

"SecondSPAdjustAmount should be greater than zero"


<s> SDValue R600TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; R600MachineFunctionInfo * MFI = MF . getInfo < R600MachineFunctionInfo > ( ) ; SmallVector < ISD :: InputArg , 8 > LocalIns ; getOriginalFunctionArgs ( DAG , MF . getFunction ( ) , Ins , LocalIns ) ; AnalyzeFormalArguments ( CCInfo , LocalIns ) ; for ( unsigned i = 0 , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const ISD :: InputArg & In = Ins [ i ] ; EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector ( ) ) { MemVT = MemVT . getVectorElementType ( ) ; } if ( AMDGPU :: isShader ( CallConv ) ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & AMDGPU :: R600_Reg128RegClass ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , AMDGPUAS :: CONSTANT_BUFFER_0 ) ; ISD :: LoadExtType Ext = ISD :: NON_EXTLOAD ; if ( MemVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) { Ext = ISD :: SEXTLOAD ; } unsigned ValBase = ArgLocs [ In . getOrigArgIndex ( ) ] . getLocMemOffset ( ) ; unsigned PartOffset = VA . getLocMemOffset ( ) ; unsigned Offset = 36 + VA . getLocMemOffset ( ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) , PartOffset - ValBase ) ; SDValue Arg = DAG . getLoad ( ISD :: UNINDEXED , Ext , VT , DL , Chain , DAG . getConstant ( Offset , DL , MVT :: i32 ) , DAG . getUNDEF ( MVT :: i32 ) , PtrInfo , MemVT , 4 , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MOInvariant ) ; InVals . push_back ( Arg ) ; MFI -> ABIArgOffset = Offset + MemVT . getStoreSize ( ) ; } return Chain ; } </s>


"Lower pointer arguments of CUDA kernels"

getPassName - Return a nice clean name for a pass .


<s> static void aarch64_emit_load_exclusive ( machine_mode mode , rtx rval , rtx mem , rtx model_rtx ) { rtx ( * gen ) ( rtx , rtx , rtx ) ; switch ( mode ) { case E_QImode : gen = gen_aarch64_load_exclusiveqi ; break ; case E_HImode : gen = gen_aarch64_load_exclusivehi ; break ; case E_SImode : gen = gen_aarch64_load_exclusivesi ; break ; case E_DImode : gen = gen_aarch64_load_exclusivedi ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( rval , mem , model_rtx ) ) ; } </s>


<s> bool PatmosAsmPrinter :: isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { if ( MBB -> isEHPad ( ) || MBB -> pred_empty ( ) || MBB -> hasAddressTaken ( ) ) return false ; MachineBasicBlock :: const_pred_iterator PI = MBB -> pred_begin ( ) , PI2 = PI ; if ( ++ PI2 != MBB -> pred_end ( ) ) return false ; const MachineBasicBlock * Pred = * PI ; if ( ! Pred -> isLayoutSuccessor ( MBB ) ) return false ; if ( isFStart ( MBB ) ) return false ; if ( Pred -> empty ( ) ) return true ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> isTerminator ( ) ) ; return I == Pred -> end ( ) || ! I -> isBarrier ( ) ; } </s>

isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


<s> bool DCPU16FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> void R600InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { if ( AMDGPU :: R600_Reg128RegClass . contains ( DestReg ) && AMDGPU :: R600_Reg128RegClass . contains ( SrcReg ) ) { for ( unsigned I = 0 ; I < 4 ; I ++ ) { unsigned SubRegIndex = RI . getSubRegFromChannel ( I ) ; buildDefaultInstruction ( MBB , MI , AMDGPU :: MOV , RI . getSubReg ( DestReg , SubRegIndex ) , RI . getSubReg ( SrcReg , SubRegIndex ) ) . addReg ( DestReg , RegState :: Define | RegState :: Implicit ) ; } } else { assert ( ! AMDGPU :: R600_Reg128RegClass . contains ( DestReg ) && ! AMDGPU :: R600_Reg128RegClass . contains ( SrcReg ) ) ; MachineInstr * NewMI = buildDefaultInstruction ( MBB , MI , AMDGPU :: MOV , DestReg , SrcReg ) ; NewMI -> getOperand ( getOperandIdx ( * NewMI , AMDGPU :: OpName :: src0 ) ) . setIsKill ( KillSrc ) ; } } </s>


<s> static bool bpf_pass_by_reference ( cumulative_args_t cum ATTRIBUTE_UNUSED , const function_arg_info & arg ) { unsigned num_bytes = arg . type_size_in_bytes ( ) ; return ( arg . aggregate_type_p ( ) || ( num_bytes > 8 * 5 ) ) ; } </s>

Return true if an argument at the position indicated by CUM should be passed by reference . If the hook returns true , a copy of that argument is made in memory and a pointer to the argument is passed instead of the argument itself .


<s>
bool
SIInstrInfo
::
isInlineConstant
(
const
MachineOperand
&
MO
,
uint8_t
OperandType
)
const
{
if
(
!
MO
.
isImm
(
)
||
OperandType
<
AMDGPU
::
OPERAND_SRC_FIRST
||
OperandType
>
AMDGPU
::
OPERAND_SRC_LAST
)
return
false
;
int64_t
Imm
=
MO
.
getImm
(
)
;
switch
(
OperandType
)
{
case
AMDGPU
::
OPERAND_REG_IMM_INT32
:
case
AMDGPU
::
OPERAND_REG_IMM_FP32
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_INT32
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_FP32
:
case
AMDGPU
::
OPERAND_REG_IMM_V2FP32
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_V2FP32
:
case
AMDGPU
::
OPERAND_REG_IMM_V2INT32
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_V2INT32
:
case
AMDGPU
::
OPERAND_REG_INLINE_AC_INT32
:
case
AMDGPU
::
OPERAND_REG_INLINE_AC_FP32
:
{
int32_t
Trunc
=
static_cast
<
int32_t
>
(
Imm
)
;
return
AMDGPU
::
isInlinableLiteral32
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
case
AMDGPU
::
OPERAND_REG_IMM_INT64
:
case
AMDGPU
::
OPERAND_REG_IMM_FP64
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_INT64
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_FP64
:
case
AMDGPU
::
OPERAND_REG_INLINE_AC_FP64
:
return
AMDGPU
::
isInlinableLiteral64
(
MO
.
getImm
(
)
,
ST
.
hasInv2PiInlineImm
(
)
)
;
case
AMDGPU
::
OPERAND_REG_IMM_INT16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_INT16
:
case
AMDGPU
::
OPERAND_REG_INLINE_AC_INT16
:
return
AMDGPU
::
isInlinableIntLiteral
(
Imm
)
;
case
AMDGPU
::
OPERAND_REG_IMM_V2INT16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_V2INT16
:
case
AMDGPU
::
OPERAND_REG_INLINE_AC_V2INT16
:
return
AMDGPU
::
isInlinableIntLiteralV216
(
Imm
)
;
case
AMDGPU
::
OPERAND_REG_IMM_FP16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_FP16
:
case
AMDGPU
::
OPERAND_REG_INLINE_AC_FP16
:
{
if
(
isInt
<
16
>
(
Imm
)
||
isUInt
<
16
>
(
Imm
)
)
{
int16_t
Trunc
=
static_cast
<
int16_t
>
(
Imm
)
;
return
ST
.
has16BitInsts
(
)
&&
AMDGPU
::
isInlinableLiteral16
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
return
false
;
}
case
AMDGPU
::
OPERAND_REG_IMM_V2FP16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_V2FP16
:
case
AMDGPU
::
OPERAND_REG_INLINE_AC_V2FP16
:
{
uint32_t
Trunc
=
static_cast
<
uint32_t
>
(
Imm
)
;
return
AMDGPU
::
isInlinableLiteralV216
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
default
:
llvm_unreachable
(
"invalid bitwidth"
)
;
}
}
</s>

returns true if the operand OpIdx in MI is a valid inline immediate .


<s> static bool arm_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( GET_MODE_CLASS ( mode ) == MODE_CC ) return ( regno == CC_REGNUM || ( TARGET_HARD_FLOAT && regno == VFPCC_REGNUM ) ) ; if ( regno == CC_REGNUM && GET_MODE_CLASS ( mode ) != MODE_CC ) return false ; if ( TARGET_THUMB1 ) return ( ARM_NUM_REGS ( mode ) < 2 ) || ( regno < LAST_LO_REGNUM ) ; if ( TARGET_HARD_FLOAT && IS_VFP_REGNUM ( regno ) ) { if ( mode == SFmode || mode == SImode ) return VFP_REGNO_OK_FOR_SINGLE ( regno ) ; if ( mode == DFmode ) return VFP_REGNO_OK_FOR_DOUBLE ( regno ) ; if ( mode == HFmode ) return VFP_REGNO_OK_FOR_SINGLE ( regno ) ; if ( mode == HImode ) return VFP_REGNO_OK_FOR_SINGLE ( regno ) ; if ( TARGET_NEON ) return ( VALID_NEON_DREG_MODE ( mode ) && VFP_REGNO_OK_FOR_DOUBLE ( regno ) ) || ( VALID_NEON_QREG_MODE ( mode ) && NEON_REGNO_OK_FOR_QUAD ( regno ) ) || ( mode == TImode && NEON_REGNO_OK_FOR_NREGS ( regno , 2 ) ) || ( mode == EImode && NEON_REGNO_OK_FOR_NREGS ( regno , 3 ) ) || ( mode == OImode && NEON_REGNO_OK_FOR_NREGS ( regno , 4 ) ) || ( mode == CImode && NEON_REGNO_OK_FOR_NREGS ( regno , 6 ) ) || ( mode == XImode && NEON_REGNO_OK_FOR_NREGS ( regno , 8 ) ) ; return false ; } if ( TARGET_REALLY_IWMMXT ) { if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return mode == SImode ; if ( IS_IWMMXT_REGNUM ( regno ) ) return VALID_IWMMXT_REG_MODE ( mode ) ; } if ( regno <= LAST_ARM_REGNUM ) { if ( ARM_NUM_REGS ( mode ) > 4 ) return false ; if ( TARGET_THUMB2 ) return true ; return ! ( TARGET_LDRD && GET_MODE_SIZE ( mode ) > 4 && ( regno & 1 ) != 0 ) ; } if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return GET_MODE_CLASS ( mode ) == MODE_INT ; return false ; } </s>

Returns true if REGNO is a valid register for holding a quantity of type MODE .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addPreserved < DominatorTreeWrapperPass > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> const uint16_t * RISCVRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( Subtarget . isRV64 ( ) ) if ( Subtarget . hasD ( ) ) return CSR_RV64D_SaveList ; else if ( Subtarget . hasF ( ) ) return CSR_RV64F_SaveList ; else return CSR_RV64_SaveList ; else if ( Subtarget . hasD ( ) ) return CSR_RV32D_SaveList ; else if ( Subtarget . hasF ( ) ) return CSR_RV32F_SaveList ; else return CSR_RV32_SaveList ; } </s>


<s>
void
M88kMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
uint64_t
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
assert
(
MCII
.
get
(
MI
.
getOpcode
(
)
)
.
getSize
(
)
==
4
&&
"Unexpected instr length"
)
;
for
(
int
I
=
(
4
1
)
*
8
;
I
>=
0
;
I
-=
8
)
OS
<<
static_cast
<
uint8_t
>
(
(
Bits
>>
I
)
&
0xff
)
;
}
</s>

Encode the given Inst to bytes and append to CB .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addPreservedID ( MachineLoopInfoID ) ; AU . addPreservedID ( MachineDominatorsID ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequiredID ( LoopSimplifyID ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; } </s>


<s> bool HexagonAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( ( IDVal . lower ( ) == ".word" ) || ( IDVal . lower ( ) == ".4byte" ) ) return ParseDirectiveValue ( 4 , DirectiveID . getLoc ( ) ) ; if ( IDVal . lower ( ) == ".short" || IDVal . lower ( ) == ".hword" || IDVal . lower ( ) == ".half" ) return ParseDirectiveValue ( 2 , DirectiveID . getLoc ( ) ) ; if ( IDVal . lower ( ) == ".falign" ) return ParseDirectiveFalign ( 256 , DirectiveID . getLoc ( ) ) ; if ( ( IDVal . lower ( ) == ".lcomm" ) || ( IDVal . lower ( ) == ".lcommon" ) ) return ParseDirectiveComm ( true , DirectiveID . getLoc ( ) ) ; if ( ( IDVal . lower ( ) == ".comm" ) || ( IDVal . lower ( ) == ".common" ) ) return ParseDirectiveComm ( false , DirectiveID . getLoc ( ) ) ; if ( IDVal . lower ( ) == ".subsection" ) return ParseDirectiveSubsection ( DirectiveID . getLoc ( ) ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> InstructionCost SystemZTTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; if ( BitSize > 64 ) return TTI :: TCC_Free ; if ( Imm == 0 ) return TTI :: TCC_Free ; if ( Imm . getBitWidth ( ) <= 64 ) { if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Basic ; if ( isUInt < 32 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Basic ; if ( ( Imm . getZExtValue ( ) & 0xffffffff ) == 0 ) return TTI :: TCC_Basic ; return 2 * TTI :: TCC_Basic ; } return 4 * TTI :: TCC_Basic ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> std :: pair < uint16_t , uint16_t > X86InstrInfo :: getExecutionDomain ( const MachineInstr & MI ) const { uint16_t domain = ( MI . getDesc ( ) . TSFlags >> X86II :: SSEDomainShift ) & 3 ; bool hasAVX2 = Subtarget . hasAVX2 ( ) ; uint16_t validDomains = 0 ; if ( domain && lookup ( MI . getOpcode ( ) , domain ) ) validDomains = 0xe ; else if ( domain && lookupAVX2 ( MI . getOpcode ( ) , domain ) ) validDomains = hasAVX2 ? 0xe : 0x6 ; return std :: make_pair ( domain , validDomains ) ; } </s>

Return the current execution domain and bit mask of possible domains for instruction .


<s> bool mips_split_move_p ( rtx dest , rtx src , enum mips_split_type split_type ) { if ( mips_mult_move_p ( dest , src , split_type ) ) return false ; unsigned int size = GET_MODE_SIZE ( GET_MODE ( dest ) ) ; if ( size == 8 && FP_REG_RTX_P ( src ) && FP_REG_RTX_P ( dest ) ) return false ; if ( size == 8 && ISA_HAS_LDC1_SDC1 ) { if ( FP_REG_RTX_P ( dest ) && MEM_P ( src ) ) return false ; if ( FP_REG_RTX_P ( src ) && MEM_P ( dest ) ) return false ; } return size > UNITS_PER_WORD ; } </s>

Return true if a move from SRC to DEST should be split into two . SPLIT_TYPE describes the split condition .


<s> void AArch64PreLegalizerCombiner :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < TargetPassConfig > ( ) ; AU . setPreservesCFG ( ) ; getSelectionDAGFallbackAnalysisUsage ( AU ) ; AU . addRequired < GISelKnownBitsAnalysis > ( ) ; AU . addPreserved < GISelKnownBitsAnalysis > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void X86InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Alignment = RC -> getSize ( ) == 32 ? 32 : 16 ; bool isAligned = ( TM . getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , TM ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) , DestReg ) , FrameIdx ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> bool SITargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Alignment , MachineMemOperand :: Flags Flags , bool * IsFast ) const { if ( IsFast ) * IsFast = false ; if ( VT == MVT :: Other || ( VT != MVT :: Other && VT . getSizeInBits ( ) > 1024 && VT . getStoreSize ( ) > 16 ) ) { return false ; } return allowsMisalignedMemoryAccessesImpl ( VT . getSizeInBits ( ) , AddrSpace , Align ( Alignment ) , Flags , IsFast ) ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> unsigned ARCInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { int Opcode = MI . getOpcode ( ) ; if ( isLoad ( Opcode ) ) { if ( ( MI . getOperand ( 1 ) . isFI ( ) ) && ( MI . getOperand ( 2 ) . isImm ( ) ) && ( isZeroImm ( MI . getOperand ( 2 ) ) ) ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


"Unexpected register class in CSRsViaCopy!"

"Function should be nounwind in insertCopiesSplitCSR!"

Insert explicit copies in entry and exit blocks .


<s>
bool
MipsAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
SmallVectorImpl
<
MCParsedAsmOperand
*
>
&
Operands
)
{
StringRef
Mnemonic
;
if
(
requestsDoubleOperand
(
Name
)
)
{
setFpFormat
(
FP_FORMAT_D
)
;
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Name
,
NameLoc
)
)
;
Mnemonic
=
Name
;
}
else
{
setDefaultFpFormat
(
)
;
size_t
Start
=
0
,
Next
=
Name
.
find
(
'.'
)
;
Mnemonic
=
Name
.
slice
(
Start
,
Next
)
;
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Mnemonic
,
NameLoc
)
)
;
if
(
Next
!=
StringRef
::
npos
)
{
size_t
Dot
=
Name
.
find
(
'.'
,
Next
+
1
)
;
StringRef
Format
=
Name
.
slice
(
Next
,
Dot
)
;
if
(
Dot
==
StringRef
::
npos
)
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Format
,
NameLoc
)
)
;
else
{
if
(
Name
.
startswith
(
"c."
)
)
{
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
"."
,
NameLoc
)
)
;
int
Cc
=
ConvertCcString
(
Format
)
;
if
(
Cc
==
1
)
{
return
Error
(
NameLoc
,
"Invalid conditional code"
)
;
}
SMLoc
E
=
SMLoc
::
getFromPointer
(
Parser
.
getTok
(
)
.
getLoc
(
)
.
getPointer
(
)
1
)
;
Operands
.
push_back
(
MipsOperand
::
CreateImm
(
MCConstantExpr
::
Create
(
Cc
,
getContext
(
)
)
,
NameLoc
,
E
)
)
;
}
else
{
return
parseMathOperation
(
Name
,
NameLoc
,
Operands
)
;
}
Format
=
Name
.
slice
(
Dot
,
StringRef
::
npos
)
;
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Format
,
NameLoc
)
)
;
}
setFpFormat
(
Format
)
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
ParseOperand
(
Operands
,
Mnemonic
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Mips
Mips
MipsOperand::CreateToken
0
MipsOperand::CreateToken
1
MipsOperand::CreateToken
"c."
MipsOperand::CreateToken
"."
1
"Invalid conditional code"
1
MipsOperand::CreateImm
MipsOperand::CreateToken
"unexpected token in argument list"
"unexpected token in argument list"
"unexpected token in argument list"


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TargetABI ( computeTargetABI ( TT , CPU , Options ) ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) { if ( isTargetHardFloat ( ) ) this -> Options . FloatABIType = FloatABI :: Hard ; else this -> Options . FloatABIType = FloatABI :: Soft ; } if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( ( TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABI || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF ) && ! ( TargetTriple . isOSWindows ( ) || TargetTriple . isOSDarwin ( ) ) ) this -> Options . EABIVersion = EABI :: GNU ; else this -> Options . EABIVersion = EABI :: EABI5 ; } if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } setSupportsDebugEntryValues ( true ) ; initAsmInfo ( ) ; } </s>