<s> bool GCNPassConfig :: addPreISel ( ) { AMDGPUPassConfig :: addPreISel ( ) ; if ( EnableAtomicOptimizations ) { addPass ( createAMDGPUAtomicOptimizerPass ( ) ) ; } addPass ( & AMDGPUUnifyDivergentExitNodesID ) ; if ( ! LateCFGStructurize ) { addPass ( createStructurizeCFGPass ( true ) ) ; } addPass ( createSinkingPass ( ) ) ; addPass ( createAMDGPUAnnotateUniformValues ( ) ) ; if ( ! LateCFGStructurize ) { addPass ( createSIAnnotateControlFlowPass ( ) ) ; } return false ; } </s>


<s> SDValue SITargetLowering :: getMemIntrinsicNode ( unsigned Opcode , const SDLoc & DL , SDVTList VTList , ArrayRef < SDValue > Ops , EVT MemVT , MachineMemOperand * MMO , SelectionDAG & DAG ) const { EVT VT = VTList . VTs [ 0 ] ; EVT WidenedVT = VT ; EVT WidenedMemVT = MemVT ; if ( ! Subtarget -> hasDwordx3LoadStores ( ) && ( WidenedVT == MVT :: v3i32 || WidenedVT == MVT :: v3f32 ) ) { WidenedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , WidenedVT . getVectorElementType ( ) , 4 ) ; WidenedMemVT = EVT :: getVectorVT ( * DAG . getContext ( ) , WidenedMemVT . getVectorElementType ( ) , 4 ) ; MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MMO , 0 , 16 ) ; } assert ( VTList . NumVTs == 2 ) ; SDVTList WidenedVTList = DAG . getVTList ( WidenedVT , VTList . VTs [ 1 ] ) ; auto NewOp = DAG . getMemIntrinsicNode ( Opcode , DL , WidenedVTList , Ops , WidenedMemVT , MMO ) ; if ( WidenedVT != VT ) { auto Extract = DAG . getNode ( ISD :: EXTRACT_SUBVECTOR , DL , VT , NewOp , DAG . getVectorIdxConstant ( 0 , DL ) ) ; NewOp = DAG . getMergeValues ( { Extract , SDValue ( NewOp . getNode ( ) , 1 ) } , DL ) ; } return NewOp ; } </s>

Creates a MemIntrinsicNode that may produce a result and takes a list of operands .


"constant argument %d for builtin %qF is invalid (%s)"

"constant argument %d for builtin %qF is out of range (0..%wu)"

"constant argument %d for builtin %qF is out of range "

Return true if ARG is appropriate as argument number ARGNUM of builtin DECL . The operand flags from s390-builtins.def have to passed as OP_FLAGS .


<s>
bool
M68kInstrInfo
::
ExpandMOVSZX_RM
(
MachineInstrBuilder
&
MIB
,
bool
IsSigned
,
const
MCInstrDesc
&
Desc
,
MVT
MVTDst
,
MVT
MVTSrc
)
const
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Expand "
<<
*
MIB
.
getInstr
(
)
<<
" to LOAD and "
)
;
unsigned
Dst
=
MIB
->
getOperand
(
0
)
.
getReg
(
)
;
unsigned
SubDst
=
RI
.
getSubReg
(
Dst
,
MVTSrc
==
MVT
::
i8
M68k
::
MxSubRegIndex8Lo
:
M68k
::
MxSubRegIndex16Lo
)
;
assert
(
SubDst
&&
"No viable SUB register available"
)
;
MIB
->
setDesc
(
Desc
)
;
MIB
->
getOperand
(
0
)
.
setReg
(
SubDst
)
;
MachineBasicBlock
::
iterator
I
=
MIB
.
getInstr
(
)
;
I
++
;
MachineBasicBlock
&
MBB
=
*
MIB
->
getParent
(
)
;
DebugLoc
DL
=
MIB
->
getDebugLoc
(
)
;
if
(
IsSigned
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Sign Extend"
<<
'\n'
)
;
AddSExt
(
MBB
,
I
,
DL
,
Dst
,
MVTSrc
,
MVTDst
)
;
}
else
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Zero Extend"
<<
'\n'
)
;
AddZExt
(
MBB
,
I
,
DL
,
Dst
,
MVTSrc
,
MVTDst
)
;
}
return
true
;
}
</s>


<s> void RISCVAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; MCInst TmpInst ; LowerRISCVMachineInstrToMCInst ( MI , TmpInst , * this ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool RISCVAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { bool HasStdExtC = STI . getFeatureBits ( ) [ RISCV :: FeatureStdExtC ] ; unsigned MinNopLen = HasStdExtC ? 2 : 4 ; if ( ( Count % MinNopLen ) != 0 ) return false ; uint64_t Nop32Count = Count / 4 ; for ( uint64_t i = Nop32Count ; i != 0 ; -- i ) OW -> write32 ( 0x13 ) ; if ( HasStdExtC ) { uint64_t Nop16Count = ( Count - Nop32Count * 4 ) / 2 ; for ( uint64_t i = Nop16Count ; i != 0 ; -- i ) OW -> write16 ( 0x01 ) ; } return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> void aarch64_subvti_scratch_regs ( rtx op1 , rtx op2 , rtx * low_dest , rtx * low_in1 , rtx * low_in2 , rtx * high_dest , rtx * high_in1 , rtx * high_in2 ) { * low_dest = gen_reg_rtx ( DImode ) ; * low_in1 = simplify_gen_subreg ( DImode , op1 , TImode , subreg_lowpart_offset ( DImode , TImode ) ) ; * low_in2 = simplify_gen_subreg ( DImode , op2 , TImode , subreg_lowpart_offset ( DImode , TImode ) ) ; * high_dest = gen_reg_rtx ( DImode ) ; * high_in1 = simplify_gen_subreg ( DImode , op1 , TImode , subreg_highpart_offset ( DImode , TImode ) ) ; * high_in2 = simplify_gen_subreg ( DImode , op2 , TImode , subreg_highpart_offset ( DImode , TImode ) ) ; } </s>

Generate DImode scratch registers for 128-bit ( TImode ) subtraction . This function differs from 'arch64_addti_scratch_regs ' in that OP1 can be an immediate constant ( zero ) . We must call subreg_highpart_offset with DImode and TImode arguments , otherwise VOIDmode will be used for the const_int which generates an internal error from subreg_size_highpart_offset which does not expect a size of zero . OP1 represents the TImode destination operand 1 OP2 represents the TImode destination operand 2 LOW_DEST represents the low half ( DImode ) of TImode operand 0 LOW_IN1 represents the low half ( DImode ) of TImode operand 1 LOW_IN2 represents the low half ( DImode ) of TImode operand 2 HIGH_DEST represents the high half ( DImode ) of TImode operand 0 HIGH_IN1 represents the high half ( DImode ) of TImode operand 1 HIGH_IN2 represents the high half ( DImode ) of TImode operand 2 .


<s> unsigned AArch64TTI :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , OperandValueKind Opd1Info , OperandValueKind Opd2Info , OperandValueProperties Opd1PropInfo , OperandValueProperties Opd2PropInfo ) const { std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Ty ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return TargetTransformInfo :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: ADD : case ISD :: MUL : case ISD :: XOR : case ISD :: OR : case ISD :: AND : return 1 * LT . first ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .


"Relocation required in an instruction that we cannot encode!"

getMachineOpValue - Return binary encoding of operand .


<s> bool RISCVTargetLowering :: isZExtFree ( SDValue Val , EVT VT2 ) const { if ( auto * LD = dyn_cast < LoadSDNode > ( Val ) ) { EVT MemVT = LD -> getMemoryVT ( ) ; if ( ( MemVT == MVT :: i8 || MemVT == MVT :: i16 ) && ( LD -> getExtensionType ( ) == ISD :: NON_EXTLOAD || LD -> getExtensionType ( ) == ISD :: ZEXTLOAD ) ) return true ; } return TargetLowering :: isZExtFree ( Val , VT2 ) ; } </s>

Return true if zero-extending the specific node Val to type VT2 is free ( either because it 's implicitly zero-extended such as ARM ldrb / ldrh or because it 's folded such as X86 zero-extending loads ) .


"Can only insert epilogue into returning blocks"

"Expected to see callee-save register restore code"


<s> bool XCoreLowerThreadLocal :: runOnModule ( Module & M ) { bool MadeChange = false ; SmallVector < GlobalVariable * , 16 > ThreadLocalGlobals ; for ( GlobalVariable & GV : M . globals ( ) ) if ( GV . isThreadLocal ( ) ) ThreadLocalGlobals . push_back ( & GV ) ; for ( unsigned I = 0 , E = ThreadLocalGlobals . size ( ) ; I != E ; ++ I ) { MadeChange |= lowerGlobal ( ThreadLocalGlobals [ I ] ) ; } return MadeChange ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> static void add_sched_insns_for_speculation ( void ) { rtx_insn * insn ; if ( ! ENABLE_WA_SPECULATIVE_LOADS && ! ENABLE_WA_SPECULATIVE_SYNCS && ! ENABLE_WA_INDIRECT_CALLS ) return ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { rtx pat ; if ( NOTE_P ( insn ) || BARRIER_P ( insn ) || LABEL_P ( insn ) ) continue ; if ( JUMP_TABLE_DATA_P ( insn ) ) continue ; pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == USE || GET_CODE ( pat ) == CLOBBER || GET_CODE ( pat ) == ASM_INPUT || asm_noperands ( pat ) >= 0 ) continue ; if ( JUMP_P ( insn ) ) { if ( any_condjump_p ( insn ) && ! cbranch_predicted_taken_p ( insn ) ) { rtx_insn * n = next_real_insn ( insn ) ; emit_insn_before ( gen_stall ( GEN_INT ( 3 ) ) , n ) ; } } } for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( JUMP_P ( insn ) && any_condjump_p ( insn ) && ( cbranch_predicted_taken_p ( insn ) ) ) { rtx_insn * target = JUMP_LABEL_AS_INSN ( insn ) ; rtx_insn * next = next_real_insn ( target ) ; if ( GET_CODE ( PATTERN ( next ) ) == UNSPEC_VOLATILE && get_attr_type ( next ) == TYPE_STALL ) continue ; emit_insn_before ( gen_stall ( GEN_INT ( 1 ) ) , next ) ; } } } </s>

Called just before the final scheduling pass . If we need to insert NOPs later on to work around speculative loads , insert special placeholder insns that cause loads to be delayed for as many cycles as necessary ( and possible ) . This reduces the number of NOPs we need to add . The dummy insns we generate are later removed by bfin_gen_bundles .


<s> unsigned RISCVAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { RISCVOperand & Op = static_cast < RISCVOperand & > ( AsmOp ) ; if ( ! Op . isReg ( ) ) return Match_InvalidOperand ; MCRegister Reg = Op . getReg ( ) ; bool IsRegFPR64 = RISCVMCRegisterClasses [ RISCV :: FPR64RegClassID ] . contains ( Reg ) ; bool IsRegFPR64C = RISCVMCRegisterClasses [ RISCV :: FPR64CRegClassID ] . contains ( Reg ) ; if ( ( IsRegFPR64 && Kind == MCK_FPR32 ) || ( IsRegFPR64C && Kind == MCK_FPR32C ) ) { Op . Reg . RegNum = convertFPR64ToFPR32 ( Reg ) ; return Match_Success ; } if ( IsRegFPR64 && Kind == MCK_FPR16 ) { Op . Reg . RegNum = convertFPR64ToFPR16 ( Reg ) ; return Match_Success ; } return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .

RISCV RISCV RISCV RISCV RISCV RISCV::FPR64RegClassID RISCV RISCV::FPR64CRegClassID


<s> MVT SPUTargetLowering :: getSetCCResultType ( MVT VT ) const { return ( ( VT == MVT :: i8 || VT == MVT :: i16 || VT == MVT :: i32 ) ? VT : MVT :: i32 ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> bool sh_in_recog_treg_set_expr ( void ) { return sh_recog_treg_set_expr_reent_count > 0 ; } </s>

Returns true when recog of a 'treg_set_expr ' is currently in progress . This can be used as a condition for insn/split patterns to allow certain T bit setting patters only to be matched as sub expressions of other patterns .


"Hexagon generate \"extract\" instructions"

getPassName - Return a nice clean name for a pass .


"ARM hazards don't support scoreboard lookahead"

getHazardType - Return the hazard type of emitting this node .


<s> unsigned OR1KRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? OR1K :: R2 : OR1K :: R1 ; } </s>


<s> unsigned getNumberOfRegisters ( bool Vector ) const override { if ( Vector ) { if ( ST -> hasNEON ( ) ) return 16 ; return 0 ; } if ( ST -> isThumb1Only ( ) ) return 8 ; return 13 ; } </s>


<s> unsigned SIRegisterInfo :: getRegPressureSetLimit ( unsigned Idx ) const { unsigned SGPRLimit = getNumSGPRsAllowed ( ST . getGeneration ( ) , ST . getMaxWavesPerCU ( ) ) ; unsigned VGPRLimit = getNumVGPRsAllowed ( ST . getMaxWavesPerCU ( ) ) ; for ( regclass_iterator I = regclass_begin ( ) , E = regclass_end ( ) ; I != E ; ++ I ) { unsigned NumSubRegs = std :: max ( ( int ) ( * I ) -> getSize ( ) / 4 , 1 ) ; unsigned Limit ; if ( isSGPRClass ( * I ) ) { Limit = SGPRLimit / NumSubRegs ; } else { Limit = VGPRLimit / NumSubRegs ; } const int * Sets = getRegClassPressureSets ( * I ) ; assert ( Sets ) ; for ( unsigned i = 0 ; Sets [ i ] != - 1 ; ++ i ) { if ( Sets [ i ] == ( int ) Idx ) return Limit ; } } return 256 ; } </s>

Get the register unit pressure limit for this dimension .


<s> bool ARCFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; bool HasFP = MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) . hasVarSizedObjects ( ) || MF . getFrameInfo ( ) . isFrameAddressTaken ( ) || RegInfo -> needsStackRealignment ( MF ) ; return HasFP ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> rtx frv_split_abs ( rtx operands [ ] ) { rtx dest = operands [ 0 ] ; rtx src = operands [ 1 ] ; rtx cc_reg = operands [ 2 ] ; rtx cr_reg = operands [ 3 ] ; rtx ret ; start_sequence ( ) ; emit_insn ( gen_rtx_SET ( cc_reg , gen_rtx_COMPARE ( CCmode , src , const0_rtx ) ) ) ; emit_insn ( gen_rtx_SET ( cr_reg , gen_rtx_fmt_ee ( LT , CC_CCRmode , cc_reg , const0_rtx ) ) ) ; emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_NE ( CC_CCRmode , cr_reg , const0_rtx ) , gen_negsi2 ( dest , src ) ) ) ; if ( ! rtx_equal_p ( dest , src ) ) emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_EQ ( CC_CCRmode , cr_reg , const0_rtx ) , gen_rtx_SET ( dest , src ) ) ) ; ret = get_insns ( ) ; end_sequence ( ) ; return ret ; } </s>

Split an integer abs operation returning a SEQUENCE containing all of the insns .


<s> static rtx xtensa_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) < UNITS_PER_WORD ) ? SImode : mode , GP_RETURN_FIRST ) ; } </s>

Worker function for TARGET_LIBCALL_VALUE .


<s> static int sh_contains_memref_p_1 ( rtx * loc , void * data ATTRIBUTE_UNUSED ) { return ( GET_CODE ( * loc ) == MEM ) ; } </s>

Called by sh_contains_memref_p via for_each_rtx .


<s>
bool
HexagonPassConfig
::
addInstSelector
(
)
{
HexagonTargetMachine
&
TM
=
getHexagonTargetMachine
(
)
;
bool
NoOpt
=
(
getOptLevel
(
)
==
CodeGenOpt
::
)
;
if
(
!
NoOpt
)
addPass
(
createHexagonRemoveExtendArgs
(
TM
)
)
;
addPass
(
createHexagonISelDag
(
TM
,
getOptLevel
(
)
)
)
;
if
(
!
NoOpt
)
{
if
(
EnableGenPred
)
addPass
(
createHexagonGenPredicate
(
)
,
false
)
;
addPass
(
createHexagonPeephole
(
)
)
;
printAndVerify
(
"After hexagon peephole pass"
)
;
if
(
EnableGenInsert
)
addPass
(
createHexagonGenInsert
(
)
,
false
)
;
if
(
EnableEarlyIf
)
addPass
(
createHexagonEarlyIfConversion
(
)
,
false
)
;
}
return
false
;
}
</s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .

Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
"After hexagon peephole pass"
Hexagon
Hexagon


<s> unsigned GBZ80RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return GB :: SP ; } </s>


<s>
const
MCFixupKindInfo
&
WebAssemblyAsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
WebAssembly
::
NumTargetFixupKinds
]
=
{
{
"fixup_code_sleb128_i32"
,
0
,
5
*
8
,
0
}
,
{
"fixup_code_sleb128_i64"
,
0
,
10
*
8
,
0
}
,
{
"fixup_code_uleb128_i32"
,
0
,
5
*
8
,
0
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> static inline bool offset_12bit_unsigned_scaled_p ( machine_mode mode , poly_int64 offset ) { HOST_WIDE_INT multiple ; return ( constant_multiple_p ( offset , GET_MODE_SIZE ( mode ) , & multiple ) && IN_RANGE ( multiple , 0 , 4095 ) ) ; } </s>

Return true if OFFSET is an unsigned 12-bit value multiplied by the size of MODE .


Relax the instruction in the given fragment to the next wider instruction .


<s>
void
X86ATTInstPrinter
::
printPCRelImm
(
const
MCInst
*
MI
,
unsigned
OpNo
,
raw_ostream
&
O
)
{
const
MCOperand
&
Op
=
MI
->
getOperand
(
OpNo
)
;
if
(
Op
.
isImm
(
)
)
O
<<
formatImm
(
Op
.
getImm
(
)
)
;
else
{
assert
(
Op
.
isExpr
(
)
&&
"unknown pcrel immediate operand"
)
;
const
MCConstantExpr
*
BranchTarget
=
dyn_cast
<
MCConstantExpr
>
(
Op
.
getExpr
(
)
)
;
int64_t
Address
;
if
(
BranchTarget
&&
BranchTarget
->
evaluateAsAbsolute
(
Address
)
)
{
O
<<
formatHex
(
(
uint64_t
)
Address
)
;
}
else
{
O
<<
*
Op
.
getExpr
(
)
;
}
}
}
</s>


<s>
LLVM_DUMP_METHOD
void
ARMConstantPoolValue
::
dump
(
)
const
{
errs
(
)
<<
"  "
<<
*
this
;
}
</s>

Dump the plan to stderr ( for debugging ) .


<s> unsigned getPointerSize ( ) const { return PointerSize ; } </s>

Layout pointer size in bytes , rounded up to a whole number of bytes .


<s> int small_data_operand ( rtx op ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED ) { rtx sym_ref ; if ( rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA ) return 0 ; if ( DEFAULT_ABI != ABI_V4 ) return 0 ; if ( GET_CODE ( op ) == SYMBOL_REF ) sym_ref = op ; else if ( GET_CODE ( op ) != CONST || GET_CODE ( XEXP ( op , 0 ) ) != PLUS || GET_CODE ( XEXP ( XEXP ( op , 0 ) , 0 ) ) != SYMBOL_REF || GET_CODE ( XEXP ( XEXP ( op , 0 ) , 1 ) ) != CONST_INT ) return 0 ; else { rtx sum = XEXP ( op , 0 ) ; HOST_WIDE_INT summand ; summand = INTVAL ( XEXP ( sum , 1 ) ) ; if ( summand < 0 || summand > g_switch_value ) return 0 ; sym_ref = XEXP ( sum , 0 ) ; } return SYMBOL_REF_SMALL_P ( sym_ref ) ; return 0 ; } </s>

Return 1 for an operand in small memory on V.4/eabi .


<s> const uint32_t * M68kRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { return CSR_STD_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool HexagonInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumTCycles , unsigned ExtraTCycles , MachineBasicBlock & FMBB , unsigned NumFCycles , unsigned ExtraFCycles , const BranchProbability & Probability ) const { return true ; } </s>


<s> static int s390_issue_rate ( void ) { switch ( s390_tune ) { case PROCESSOR_2084_Z990 : case PROCESSOR_2094_Z9_109 : case PROCESSOR_2094_Z9_EC : case PROCESSOR_2817_Z196 : return 3 ; case PROCESSOR_2097_Z10 : return 2 ; case PROCESSOR_9672_G5 : case PROCESSOR_9672_G6 : case PROCESSOR_2064_Z900 : case PROCESSOR_2827_ZEC12 : case PROCESSOR_2964_Z13 : default : return 1 ; } } </s>

The number of instructions that can be issued per cycle .


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64Bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , Options . StackAlignmentOverride , is64Bit ) , FrameLowering ( * this , Subtarget ) , ELFWriterInfo ( is64Bit , true ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) { if ( getRelocationModel ( ) == Reloc :: Static ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . is64Bit ( ) ) { Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; } else if ( Subtarget . isTargetCygMing ( ) ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . isTargetDarwin ( ) ) { if ( getRelocationModel ( ) == Reloc :: PIC_ ) Subtarget . setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; Subtarget . setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( Subtarget . isTargetELF ( ) ) { Subtarget . setPICStyle ( PICStyles :: GOT ) ; } if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = FloatABI :: Hard ; } </s>


<s> static void unw_access_gr ( struct _Unwind_Context * info , int regnum , unsigned long * val , char * nat , int write ) { unsigned long * addr , * nat_addr = 0 , nat_mask = 0 , dummy_nat ; struct unw_ireg * ireg ; if ( ( unsigned ) regnum - 1 >= 127 ) abort ( ) ; if ( regnum < 1 ) { nat_addr = addr = & dummy_nat ; dummy_nat = 0 ; } else if ( regnum < 32 ) { ireg = & info -> ireg [ regnum - 2 ] ; addr = ireg -> loc ; if ( addr ) { nat_addr = addr + ireg -> nat . off ; switch ( ireg -> nat . type ) { case UNW_NAT_VAL : if ( write ) { if ( * nat ) { addr [ 0 ] = 0 ; addr [ 1 ] = 0x1fffe ; return ; } addr [ 1 ] = 0x1003e ; } else if ( addr [ 0 ] == 0 && addr [ 1 ] == 0x1ffe ) { * val = 0 ; * nat = 1 ; return ; } case UNW_NAT_NONE : dummy_nat = 0 ; nat_addr = & dummy_nat ; break ; case UNW_NAT_MEMSTK : nat_mask = 1UL << ( ( long ) addr & 0x1f8 ) / 8 ; break ; case UNW_NAT_REGSTK : if ( ( unsigned long ) addr >= info -> regstk_top ) nat_addr = & info -> rnat ; else nat_addr = ia64_rse_rnat_addr ( addr ) ; nat_mask = 1UL << ia64_rse_slot_num ( addr ) ; break ; } } } else { addr = ia64_rse_skip_regs ( ( unsigned long * ) info -> bsp , regnum - 32 ) ; if ( ( unsigned long ) addr >= info -> regstk_top ) nat_addr = & info -> rnat ; else nat_addr = ia64_rse_rnat_addr ( addr ) ; nat_mask = 1UL << ia64_rse_slot_num ( addr ) ; } if ( write ) { * addr = * val ; if ( * nat ) * nat_addr |= nat_mask ; else * nat_addr &= ~ nat_mask ; } else { * val = * addr ; * nat = ( * nat_addr & nat_mask ) != 0 ; } } </s>


This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly


<s> bool AMDGPUPrintfRuntimeBinding :: runOnModule ( Module & M ) { Triple TT ( M . getTargetTriple ( ) ) ; if ( TT . getArch ( ) == Triple :: r600 ) return false ; auto PrintfFunction = M . getFunction ( "printf" ) ; if ( ! PrintfFunction ) return false ; for ( auto & U : PrintfFunction -> uses ( ) ) { if ( auto * CI = dyn_cast < CallInst > ( U . getUser ( ) ) ) { if ( CI -> isCallee ( & U ) ) Printfs . push_back ( CI ) ; } } if ( Printfs . empty ( ) ) return false ; TD = & M . getDataLayout ( ) ; auto DTWP = getAnalysisIfAvailable < DominatorTreeWrapperPass > ( ) ; DT = DTWP ? & DTWP -> getDomTree ( ) : nullptr ; auto GetTLI = [ this ] ( Function & F ) -> TargetLibraryInfo & { return this -> getAnalysis < TargetLibraryInfoWrapperPass > ( ) . getTLI ( F ) ; } ; return lowerPrintfForGpu ( M , GetTLI ) ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


"Instr doesn't have FrameIndex operand!"

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s> static void s390_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( s390_function_arg_vector ( mode , type ) ) { if ( ! named ) return ; cum -> vrs += 1 ; } else if ( s390_function_arg_float ( mode , type ) ) { cum -> fprs += 1 ; } else if ( s390_function_arg_integer ( mode , type ) ) { int size = s390_function_arg_size ( mode , type ) ; cum -> gprs += ( ( size + UNITS_PER_LONG - 1 ) / UNITS_PER_LONG ) ; } else gcc_unreachable ( ) ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available. ) . The boolean NAMED specifies whether the argument is a named argument ( as opposed to an unnamed argument matching an ellipsis ) .


"Cannot spill SGPR to memory without RegScavenger"

"Exec is already saved, refuse to save again"

prepare - Reset state and prepare for a new spill placement computation .


"LowerFormalArguments Unhandled argument type: "

"functions with VarArgs or StructRet are not supported"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> void ARMHazardRecognizer :: Reset ( ) { LastMI = 0 ; Stalls = 0 ; ITBlockSize = 0 ; ScoreboardHazardRecognizer :: Reset ( ) ; } </s>


<s> static enum tls_model tls_symbolic_operand_type ( rtx addr ) { enum tls_model tls_kind = TLS_MODEL_NONE ; if ( GET_CODE ( addr ) == CONST ) { poly_int64 addend ; rtx sym = strip_offset ( addr , & addend ) ; if ( GET_CODE ( sym ) == SYMBOL_REF ) tls_kind = SYMBOL_REF_TLS_MODEL ( sym ) ; } else if ( GET_CODE ( addr ) == SYMBOL_REF ) tls_kind = SYMBOL_REF_TLS_MODEL ( addr ) ; return tls_kind ; } </s>

Return the TLS model to use for SYMBOL .


getTargetNodeName - This method returns the name of a target specific


<s> bool X86TargetLowering :: isVectorClearMaskLegal ( const std :: vector < SDValue > & BVOps , MVT EVT , SelectionDAG & DAG ) const { unsigned NumElts = BVOps . size ( ) ; if ( EVT . getSizeInBits ( ) * NumElts == 64 ) return false ; if ( NumElts == 2 ) return true ; if ( NumElts == 4 ) { return ( isMOVLMask ( & BVOps [ 0 ] , 4 ) || isCommutedMOVL ( & BVOps [ 0 ] , 4 , true ) || isSHUFPMask ( & BVOps [ 0 ] , 4 ) || isCommutedSHUFP ( & BVOps [ 0 ] , 4 ) ) ; } return false ; } </s>


<s> int s390_arg_frame_offset ( ) { struct s390_frame frame ; s390_frame_info ( & frame ) ; return frame . frame_size + STACK_POINTER_OFFSET ; } </s>

Return offset between argument pointer and frame pointer initially after prologue .


<s> void X86TargetLowering :: initializeSplitCSR ( MachineBasicBlock * Entry ) const { if ( ! Subtarget -> is64Bit ( ) ) return ; X86MachineFunctionInfo * AFI = Entry -> getParent ( ) -> getInfo < X86MachineFunctionInfo > ( ) ; AFI -> setIsSplitCSR ( true ) ; } </s>

Perform necessary initialization to handle a subset of CSRs explicitly via copies .


<s> void nds32_spilt_doubleword ( rtx * operands , bool load_p ) { int reg = load_p ? 0 : 1 ; int mem = load_p ? 1 : 0 ; rtx reg_rtx = load_p ? operands [ 0 ] : operands [ 1 ] ; rtx mem_rtx = load_p ? operands [ 1 ] : operands [ 0 ] ; rtx low_part [ 2 ] , high_part [ 2 ] ; rtx sub_mem = XEXP ( mem_rtx , 0 ) ; low_part [ reg ] = simplify_gen_subreg ( SImode , reg_rtx , GET_MODE ( reg_rtx ) , 0 ) ; high_part [ reg ] = simplify_gen_subreg ( SImode , reg_rtx , GET_MODE ( reg_rtx ) , 4 ) ; if ( GET_CODE ( sub_mem ) == POST_DEC ) { sub_mem = XEXP ( sub_mem , 0 ) ; low_part [ mem ] = gen_rtx_MEM ( SImode , gen_rtx_POST_MODIFY ( Pmode , sub_mem , gen_rtx_PLUS ( Pmode , sub_mem , GEN_INT ( 4 ) ) ) ) ; high_part [ mem ] = gen_rtx_MEM ( SImode , gen_rtx_POST_MODIFY ( Pmode , sub_mem , gen_rtx_PLUS ( Pmode , sub_mem , GEN_INT ( - 12 ) ) ) ) ; } else if ( GET_CODE ( sub_mem ) == POST_INC ) { sub_mem = XEXP ( sub_mem , 0 ) ; low_part [ mem ] = gen_rtx_MEM ( SImode , gen_rtx_POST_INC ( Pmode , sub_mem ) ) ; high_part [ mem ] = gen_rtx_MEM ( SImode , gen_rtx_POST_INC ( Pmode , sub_mem ) ) ; } else if ( GET_CODE ( sub_mem ) == POST_MODIFY ) { rtx post_mem = XEXP ( sub_mem , 0 ) ; rtx plus_op = XEXP ( sub_mem , 1 ) ; rtx post_val = XEXP ( plus_op , 1 ) ; low_part [ mem ] = gen_rtx_MEM ( SImode , gen_rtx_POST_MODIFY ( Pmode , post_mem , gen_rtx_PLUS ( Pmode , post_mem , post_val ) ) ) ; high_part [ mem ] = gen_rtx_MEM ( SImode , plus_constant ( Pmode , post_mem , 4 ) ) ; } else { low_part [ mem ] = adjust_address ( mem_rtx , SImode , 0 ) ; high_part [ mem ] = adjust_address ( mem_rtx , SImode , 4 ) ; } if ( ( load_p && reg_overlap_mentioned_p ( low_part [ 0 ] , high_part [ 1 ] ) ) || GET_CODE ( sub_mem ) == POST_MODIFY ) { operands [ 2 ] = high_part [ 0 ] ; operands [ 3 ] = high_part [ 1 ] ; operands [ 4 ] = low_part [ 0 ] ; operands [ 5 ] = low_part [ 1 ] ; } else { operands [ 2 ] = low_part [ 0 ] ; operands [ 3 ] = low_part [ 1 ] ; operands [ 4 ] = high_part [ 0 ] ; operands [ 5 ] = high_part [ 1 ] ; } } </s>

Spilt a doubleword instrucion to two single word instructions .


<s>
bool
X86CmovConverterPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
if
(
!
EnableCmovConverter
)
return
false
;
DEBUG
(
dbgs
(
)
<<
"********** "
<<
getPassName
(
)
<<
" : "
<<
MF
.
getName
(
)
<<
"**********\n"
)
;
bool
Changed
=
false
;
MachineLoopInfo
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
const
TargetSubtargetInfo
&
STI
=
MF
.
getSubtarget
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
TII
=
STI
.
getInstrInfo
(
)
;
TRI
=
STI
.
getRegisterInfo
(
)
;
TSchedModel
.
init
(
&
STI
)
;
if
(
ForceMemOperand
)
{
CmovGroups
AllCmovGroups
;
SmallVector
<
MachineBasicBlock
*
,
4
>
Blocks
;
for
(
auto
&
MBB
:
MF
)
Blocks
.
push_back
(
&
MBB
)
;
if
(
collectCmovCandidates
(
Blocks
,
AllCmovGroups
,
true
)
)
{
for
(
auto
&
Group
:
AllCmovGroups
)
{
if
(
!
llvm
::
any_of
(
Group
,
[
&
]
(
MachineInstr
*
I
)
{
return
I
->
mayLoad
(
)
;
}
)
)
continue
;
Changed
=
true
;
convertCmovInstsToBranches
(
Group
)
;
}
}
}
SmallVector
<
MachineLoop
*
,
4
>
Loops
(
MLI
.
begin
(
)
,
MLI
.
end
(
)
)
;
for
(
int
i
=
0
;
i
<
(
int
)
Loops
.
size
(
)
;
++
i
)
for
(
MachineLoop
*
Child
:
Loops
[
i
]
->
getSubLoops
(
)
)
Loops
.
push_back
(
Child
)
;
for
(
MachineLoop
*
CurrLoop
:
Loops
)
{
if
(
!
CurrLoop
->
getSubLoops
(
)
.
empty
(
)
)
continue
;
CmovGroups
CmovInstGroups
;
if
(
!
collectCmovCandidates
(
CurrLoop
->
getBlocks
(
)
,
CmovInstGroups
)
)
continue
;
if
(
!
checkForProfitableCmovCandidates
(
CurrLoop
->
getBlocks
(
)
,
CmovInstGroups
)
)
continue
;
Changed
=
true
;
for
(
auto
&
Group
:
CmovInstGroups
)
convertCmovInstsToBranches
(
Group
)
;
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> rtx expand ( function_expander & e ) const OVERRIDE { return e . use_exact_insn ( CODE_FOR_aarch64_wrffr ) ; } </s>


<s> void emitInst ( uint32_t Inst ) { char Buffer [ 4 ] ; const bool LittleEndian = getContext ( ) . getAsmInfo ( ) -> isLittleEndian ( ) ; EmitA64MappingSymbol ( ) ; for ( unsigned II = 0 ; II != 4 ; ++ II ) { const unsigned I = LittleEndian ? ( 4 - II - 1 ) : II ; Buffer [ 4 - II - 1 ] = uint8_t ( Inst >> I * CHAR_BIT ) ; } MCELFStreamer :: EmitBytes ( StringRef ( Buffer , 4 ) ) ; } </s>

Callback used to implement the .inst directive .


<s> static rtx nvptx_wsync ( bool after ) { return gen_nvptx_barsync ( GEN_INT ( after ) ) ; } </s>

Emit a worker-level synchronization barrier . We use different markers for before and after synchronizations .


<s> const BPFInstrInfo * getInstrInfo ( ) { return getTargetMachine ( ) . getInstrInfo ( ) ; } </s>


<s> bool GCNPassConfig :: addLegalizeMachineIR ( ) { return false ; } </s>

This method should install a legalize pass , which converts the instruction sequence into one that can be selected by the target .


<s> virtual const BPFSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool MSP430TargetLowering :: isTruncateFree ( EVT VT1 , EVT VT2 ) const { if ( ! VT1 . isInteger ( ) || ! VT2 . isInteger ( ) ) return false ; return ( VT1 . getSizeInBits ( ) > VT2 . getSizeInBits ( ) ) ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s> virtual EVT getSetCCResultType ( LLVMContext & , EVT ) const { return MVT :: i32 ; } </s>

Return the value type to use for ISD : :SETCC .


<s> bool X86TargetLowering :: canMergeStoresTo ( unsigned AddressSpace , EVT MemVT , const SelectionDAG & DAG ) const { bool NoFloat = DAG . getMachineFunction ( ) . getFunction ( ) . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; if ( NoFloat ) { unsigned MaxIntSize = Subtarget . is64Bit ( ) ? 64 : 32 ; return ( MemVT . getSizeInBits ( ) <= MaxIntSize ) ; } return true ; } </s>

Returns if it 's reasonable to merge stores to MemVT size .


<s> bool PPCTargetLowering :: SelectAddressPCRel ( SDValue N , SDValue & Base ) const { ConstantPoolSDNode * ConstPoolNode = dyn_cast < ConstantPoolSDNode > ( N . getNode ( ) ) ; bool HasFlag = ConstPoolNode && ConstPoolNode -> getTargetFlags ( ) == PPCII :: MO_PCREL_FLAG ; bool HasNode = N . getOpcode ( ) == PPCISD :: MAT_PCREL_ADDR ; if ( HasFlag || HasNode ) { Base = N ; return true ; } return false ; } </s>

SelectAddressPCRel - Represent the specified address as pc relative to be represented as [ pc+imm ] .


<s> MachineInstr * WebAssemblyInstrInfo :: commuteInstructionImpl ( MachineInstr & MI , bool NewMI , unsigned OpIdx1 , unsigned OpIdx2 ) const { WebAssemblyFunctionInfo & MFI = * MI . getParent ( ) -> getParent ( ) -> getInfo < WebAssemblyFunctionInfo > ( ) ; if ( MFI . isVRegStackified ( MI . getOperand ( OpIdx1 ) . getReg ( ) ) || MFI . isVRegStackified ( MI . getOperand ( OpIdx2 ) . getReg ( ) ) ) return nullptr ; return TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1 , OpIdx2 ) ; } </s>

Commutes the operands in the given instruction by changing the operands order and/or changing the instruction 's opcode and/or the immediate value operand .

WebAssembly WebAssembly WebAssembly WebAssembly


<s> bool SILowerControlFlow :: runOnMachineFunction ( MachineFunction & MF ) { const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; LIS = getAnalysisIfAvailable < LiveIntervals > ( ) ; MRI = & MF . getRegInfo ( ) ; BoolRC = TRI -> getBoolRC ( ) ; if ( ST . isWave32 ( ) ) { AndOpc = AMDGPU :: S_AND_B32 ; OrOpc = AMDGPU :: S_OR_B32 ; XorOpc = AMDGPU :: S_XOR_B32 ; MovTermOpc = AMDGPU :: S_MOV_B32_term ; Andn2TermOpc = AMDGPU :: S_ANDN2_B32_term ; XorTermrOpc = AMDGPU :: S_XOR_B32_term ; OrSaveExecOpc = AMDGPU :: S_OR_SAVEEXEC_B32 ; Exec = AMDGPU :: EXEC_LO ; } else { AndOpc = AMDGPU :: S_AND_B64 ; OrOpc = AMDGPU :: S_OR_B64 ; XorOpc = AMDGPU :: S_XOR_B64 ; MovTermOpc = AMDGPU :: S_MOV_B64_term ; Andn2TermOpc = AMDGPU :: S_ANDN2_B64_term ; XorTermrOpc = AMDGPU :: S_XOR_B64_term ; OrSaveExecOpc = AMDGPU :: S_OR_SAVEEXEC_B64 ; Exec = AMDGPU :: EXEC ; } MachineFunction :: iterator NextBB ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; BI = NextBB ) { NextBB = std :: next ( BI ) ; MachineBasicBlock & MBB = * BI ; MachineBasicBlock :: iterator I , Next , Last ; for ( I = MBB . begin ( ) , Last = MBB . end ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; switch ( MI . getOpcode ( ) ) { case AMDGPU :: SI_IF : emitIf ( MI ) ; break ; case AMDGPU :: SI_ELSE : emitElse ( MI ) ; break ; case AMDGPU :: SI_IF_BREAK : emitIfBreak ( MI ) ; break ; case AMDGPU :: SI_LOOP : emitLoop ( MI ) ; break ; case AMDGPU :: SI_END_CF : emitEndCf ( MI ) ; break ; case AMDGPU :: S_AND_B64 : case AMDGPU :: S_OR_B64 : case AMDGPU :: S_AND_B32 : case AMDGPU :: S_OR_B32 : combineMasks ( MI ) ; Last = I ; continue ; default : Last = I ; continue ; } Next = ( Last == MBB . end ( ) ) ? MBB . begin ( ) : Last ; } } return true ; } </s>


<s> static rtx arm_trampoline_adjust_address ( rtx addr ) { if ( TARGET_THUMB && ! TARGET_FDPIC ) addr = expand_simple_binop ( Pmode , IOR , addr , const1_rtx , NULL , 0 , OPTAB_LIB_WIDEN ) ; return addr ; } </s>

Thumb trampolines should be entered in thumb mode , so set the bottom bit of the address .


<s> int mmix_function_value_regno_p ( int regno ) { return regno == MMIX_RETURN_VALUE_REGNUM ; } </s>


<s>
static
std
::
unique_ptr
<
X86Operand
>
CreateMem
(
unsigned
ModeSize
,
unsigned
SegReg
,
const
MCExpr
*
Disp
,
unsigned
BaseReg
,
unsigned
IndexReg
,
unsigned
Scale
,
SMLoc
StartLoc
,
SMLoc
EndLoc
,
unsigned
Size
=
0
,
StringRef
SymName
=
StringRef
(
)
,
void
*
OpDecl
=
nullptr
,
unsigned
FrontendSize
=
0
)
{
assert
(
(
SegReg
||
BaseReg
||
IndexReg
)
&&
"Invalid memory operand!"
)
;
assert
(
(
(
Scale
==
1
||
Scale
==
2
||
Scale
==
4
||
Scale
==
8
)
)
&&
"Invalid scale!"
)
;
auto
Res
=
std
::
make_unique
<
X86Operand
>
(
Memory
,
StartLoc
,
EndLoc
)
;
Res
->
Mem
.
SegReg
=
SegReg
;
Res
->
Mem
.
Disp
=
Disp
;
Res
->
Mem
.
BaseReg
=
BaseReg
;
Res
->
Mem
.
IndexReg
=
IndexReg
;
Res
->
Mem
.
Scale
=
Scale
;
Res
->
Mem
.
Size
=
Size
;
Res
->
Mem
.
ModeSize
=
ModeSize
;
Res
->
Mem
.
FrontendSize
=
FrontendSize
;
Res
->
SymName
=
SymName
;
Res
->
OpDecl
=
OpDecl
;
Res
->
AddressOf
=
false
;
return
Res
;
}
</s>


<s> bool MipsTargetLowering :: shouldSignExtendTypeInLibCall ( EVT Type , bool IsSigned ) const { if ( Subtarget . hasMips3 ( ) && Subtarget . useSoftFloat ( ) ) { if ( Type == MVT :: i32 ) return true ; } return IsSigned ; } </s>

Returns true if arguments should be sign-extended in lib calls .


<s> void rvexAsmPrinter :: emitFrameDirective ( ) { const TargetRegisterInfo & RI = * TM . getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) -> getStackSize ( ) ; if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( "\t.frame\t$" + StringRef ( rvexInstPrinter :: getRegisterName ( stackReg ) ) . lower ( ) + "," + Twine ( stackSize ) + ",$" + StringRef ( rvexInstPrinter :: getRegisterName ( returnReg ) ) . lower ( ) ) ; } </s>

rvex rvex "\t.frame\t$" rvex "," ",$" rvex


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> unsigned FISCInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s>
static
int
frv_arg_partial_bytes
(
CUMULATIVE_ARGS
*
cum
,
enum
machine_mode
mode
,
tree
type
ATTRIBUTE_UNUSED
,
bool
named
ATTRIBUTE_UNUSED
)
{
enum
machine_mode
xmode
=
(
mode
==
BLKmode
)
SImode
:
mode
;
int
bytes
=
GET_MODE_SIZE
(
xmode
)
;
int
words
=
(
bytes
+
UNITS_PER_WORD
1
)
/
UNITS_PER_WORD
;
int
arg_num
=
*
cum
;
int
ret
;
ret
=
(
(
arg_num
<=
LAST_ARG_REGNUM
&&
arg_num
+
words
>
LAST_ARG_REGNUM
+
1
)
LAST_ARG_REGNUM
arg_num
+
1
:
0
)
;
ret
*=
UNITS_PER_WORD
;
if
(
TARGET_DEBUG_ARG
&&
ret
)
fprintf
(
stderr
,
"frv_arg_partial_bytes: %d\n"
,
ret
)
;
return
ret
;
}
</s>

A C expression for the number of words , at the beginning of an argument , must be put in registers . The value must be zero for arguments that are passed entirely in registers or that are entirely pushed on the stack . On some machines , certain arguments must be passed partially in registers and partially in memory . On these machines , typically the first N words of arguments are passed in registers , and the rest on the stack . If a multi-word argument ( a ` double ' or a structure ) crosses that boundary , its first few words must be passed in registers and the rest must be pushed . This macro tells the compiler when this occurs , and how many of the words should go in registers . ` FUNCTION_ARG ' for these arguments should return the first register to be used by the caller for this argument ; likewise ` FUNCTION_INCOMING_ARG ' , for the called function .


"Code generation for MIPS-I is not implemented"

"Code generation for MIPS-V is not implemented"

"MSA requires a 64-bit FPU register file (FR=1 mode). "

"-mattr=+nooddspreg requires the O32 ABI."

"FPXX is not permitted for the N32/N64 ABI's."

"position-independent code requires '-mabicalls'"

"warning: cannot use small-data accesses for '-mabicalls'"

This constructor initializes the data members to match that of the specified triple .


<s> bool AArch64CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; bool Split = false ; LLT Ty = MRI . getType ( VRegs [ i ] ) ; unsigned Dst = VRegs [ i ] ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , F . getCallingConv ( ) , [ & ] ( unsigned Reg , uint64_t Offset ) { if ( ! Split ) { Split = true ; Dst = MRI . createGenericVirtualRegister ( Ty ) ; MIRBuilder . buildUndef ( Dst ) ; } unsigned Tmp = MRI . createGenericVirtualRegister ( Ty ) ; MIRBuilder . buildInsert ( Tmp , Dst , Reg , Offset ) ; Dst = Tmp ; } ) ; if ( Dst != VRegs [ i ] ) MIRBuilder . buildCopy ( VRegs [ i ] , Dst ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; if ( F . isVarArg ( ) ) { if ( ! MF . getSubtarget < AArch64Subtarget > ( ) . isTargetDarwin ( ) ) { return false ; } uint64_t StackOffset = alignTo ( Handler . StackUsed , 8 ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; AArch64FunctionInfo * FuncInfo = MF . getInfo < AArch64FunctionInfo > ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( 4 , StackOffset , true ) ) ; } MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> void TPCFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


<s> bool SIInstrInfo :: isSafeToMoveRegClassDefs ( const TargetRegisterClass * RC ) const { return RC != & AMDGPU :: EXECRegRegClass ; } </s>

isSafeToMoveRegClassDefs - Return true if it 's safe to move a machine instruction that defines the specified register class .


<s> static void sh_setup_incoming_varargs ( cumulative_args_t ca , const function_arg_info & arg , int * pretend_arg_size , int second_time ATTRIBUTE_UNUSED ) { gcc_assert ( cfun -> stdarg ) ; if ( TARGET_VARARGS_PRETEND_ARGS ( current_function_decl ) ) { int named_parm_regs = 0 , anon_parm_regs ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) ) named_parm_regs = ( sh_round_reg ( * get_cumulative_args ( ca ) , arg . mode ) + CEIL ( arg . promoted_size_in_bytes ( ) , UNITS_PER_WORD ) ) ; anon_parm_regs = NPARM_REGS ( SImode ) - named_parm_regs ; if ( anon_parm_regs > 0 ) * pretend_arg_size = anon_parm_regs * 4 ; } } </s>

We actually emit the code in sh_expand_prologue . We used to use a static variable to flag that we need to emit this code , but that does n't when inlining , when functions are deferred and then emitted later . Fortunately , we already have two flags that are part of struct function that tell if a function uses varargs or stdarg .


"instruction requires a CPU feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> static reg_class_t cris_preferred_reload_class ( rtx x , reg_class_t rclass ) { if ( rclass != MOF_REGS && rclass != MOF_SRP_REGS && rclass != SRP_REGS && rclass != CC0_REGS && rclass != SPECIAL_REGS ) return GENERAL_REGS ; if ( GET_CODE ( x ) == PLUS && ! reg_class_subset_p ( rclass , GENERAL_REGS ) ) return NO_REGS ; if ( satisfies_constraint_P ( x ) && ! reg_class_subset_p ( rclass , GENERAL_REGS ) ) return NO_REGS ; return rclass ; } </s>

Worker function for TARGET_PREFERRED_RELOAD_CLASS . It seems like gcc ( 2.7.2 and 2.9x of 2000-03-22 ) may send `` NO_REGS '' as the class for a constant ( testcase : __Mul in arit.c ) . To avoid forcing out a constant into the constant pool , we will trap this case and return something a bit more sane . FIXME : Check if this is a bug . Beware that we must not `` override '' classes that can be specified as constraint letters , or else asm operands using them will fail when they need to be reloaded . FIXME : Investigate whether that constitutes a bug .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createX86ELFObjectWriter ( OS , true , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static struct machine_function * cris_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function > ( ) ; } </s>

Zero initialization is OK for all current fields .


<s> TargetPassConfig * TGSITargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new TGSIPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s>
bool
ARCInstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
TBB
=
FBB
=
nullptr
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
if
(
I
==
MBB
.
begin
(
)
)
return
false
;
I
;
while
(
isPredicated
(
*
I
)
||
I
->
isTerminator
(
)
||
I
->
isDebugValue
(
)
)
{
bool
CantAnalyze
=
false
;
while
(
I
->
isDebugValue
(
)
||
!
I
->
isTerminator
(
)
)
{
if
(
I
==
MBB
.
begin
(
)
)
return
false
;
I
;
}
if
(
isJumpOpcode
(
I
->
getOpcode
(
)
)
)
{
CantAnalyze
=
true
;
}
else
if
(
isUncondBranchOpcode
(
I
->
getOpcode
(
)
)
)
{
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
}
else
if
(
isCondBranchOpcode
(
I
->
getOpcode
(
)
)
)
{
if
(
!
Cond
.
empty
(
)
)
return
true
;
assert
(
!
FBB
&&
"FBB should have been null."
)
;
FBB
=
TBB
;
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
Cond
.
push_back
(
I
->
getOperand
(
1
)
)
;
Cond
.
push_back
(
I
->
getOperand
(
2
)
)
;
Cond
.
push_back
(
I
->
getOperand
(
3
)
)
;
}
else
if
(
I
->
isReturn
(
)
)
{
CantAnalyze
=
!
isPredicated
(
*
I
)
;
}
else
{
return
true
;
}
if
(
!
isPredicated
(
*
I
)
&&
(
isUncondBranchOpcode
(
I
->
getOpcode
(
)
)
||
isJumpOpcode
(
I
->
getOpcode
(
)
)
||
I
->
isReturn
(
)
)
)
{
Cond
.
clear
(
)
;
FBB
=
nullptr
;
if
(
AllowModify
)
{
MachineBasicBlock
::
iterator
DI
=
std
::
next
(
I
)
;
while
(
DI
!=
MBB
.
end
(
)
)
{
MachineInstr
&
InstToDelete
=
*
DI
;
++
DI
;
InstToDelete
.
eraseFromParent
(
)
;
}
}
}
if
(
CantAnalyze
)
return
true
;
if
(
I
==
MBB
.
begin
(
)
)
return
false
;
I
;
}
return
false
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> bool arm_needs_doubleword_align ( enum machine_mode mode , tree type ) { return ( GET_MODE_ALIGNMENT ( mode ) > PARM_BOUNDARY || ( type && TYPE_ALIGN ( type ) > PARM_BOUNDARY ) ) ; } </s>

Return 1 if double word alignment is required for argument passing . Return -1 if double word alignment used to be required for argument passing before PR77728 ABI fix , but is not required anymore . Return 0 if double word alignment is not required and was n't requried before either .


<s> void spu_allocate_stack ( rtx op0 , rtx op1 ) { HOST_WIDE_INT v ; rtx chain = gen_reg_rtx ( V4SImode ) ; rtx stack_bot = gen_frame_mem ( V4SImode , stack_pointer_rtx ) ; rtx sp = gen_reg_rtx ( V4SImode ) ; rtx splatted = gen_reg_rtx ( V4SImode ) ; rtx pat = gen_reg_rtx ( TImode ) ; emit_move_insn ( chain , stack_bot ) ; op1 = force_reg ( SImode , op1 ) ; v = 0x1020300010203ll ; emit_move_insn ( pat , immed_double_const ( v , v , TImode ) ) ; emit_insn ( gen_shufb ( splatted , op1 , op1 , pat ) ) ; emit_insn ( gen_spu_convert ( sp , stack_pointer_rtx ) ) ; emit_insn ( gen_subv4si3 ( sp , sp , splatted ) ) ; if ( flag_stack_check ) { rtx avail = gen_reg_rtx ( SImode ) ; rtx result = gen_reg_rtx ( SImode ) ; emit_insn ( gen_vec_extractv4si ( avail , sp , GEN_INT ( 1 ) ) ) ; emit_insn ( gen_cgt_si ( result , avail , GEN_INT ( - 1 ) ) ) ; emit_insn ( gen_spu_heq ( result , GEN_INT ( 0 ) ) ) ; } emit_insn ( gen_spu_convert ( stack_pointer_rtx , sp ) ) ; emit_move_insn ( stack_bot , chain ) ; emit_move_insn ( op0 , virtual_stack_dynamic_rtx ) ; } </s>

We need to correctly update the back chain pointer and the Available Stack Size ( which is in the second slot of the sp register . )


<s> bool LanaiRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; return true ; } </s>

True if the stack can be realigned for the target .


<s> static bool sh_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { if ( to == SFmode && VECTOR_MODE_P ( from ) && GET_MODE_INNER ( from ) == SFmode ) return optimize ? ! reg_classes_intersect_p ( GENERAL_REGS , rclass ) : true ; if ( GET_MODE_SIZE ( from ) != GET_MODE_SIZE ( to ) ) { if ( TARGET_LITTLE_ENDIAN ) { if ( GET_MODE_SIZE ( to ) < 8 || GET_MODE_SIZE ( from ) < 8 ) return ! reg_classes_intersect_p ( DF_REGS , rclass ) ; } else { if ( GET_MODE_SIZE ( from ) < 8 ) return ! reg_classes_intersect_p ( DF_REGS , rclass ) ; } } return true ; } </s>


"SRetReturnReg should have been set in LowerFormalArguments()."

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool HexagonInstrInfo :: hasStoreToStackSlot ( const MachineInstr & MI , SmallVectorImpl < const MachineMemOperand * > & Accesses ) const { if ( MI . isBundle ( ) ) { const MachineBasicBlock * MBB = MI . getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI . getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( TargetInstrInfo :: hasStoreToStackSlot ( * MII , Accesses ) ) return true ; return false ; } return TargetInstrInfo :: hasStoreToStackSlot ( MI , Accesses ) ; } </s>

If the specified machine instruction has a store to a stack slot , return true along with the FrameIndices of the loaded stack slot and the machine mem operands containing the reference .


<s> bool Thumb1InstrInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( CSI . empty ( ) ) return false ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > 0 ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( ARM :: tPOP ) ) ; AddDefaultPred ( MIB ) ; MIB . addReg ( 0 ) ; bool NumRegs = false ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( Reg == ARM :: LR ) { if ( isVarArg ) continue ; Reg = ARM :: PC ; ( * MIB ) . setDesc ( get ( ARM :: tPOP_RET ) ) ; MI = MBB . erase ( MI ) ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; NumRegs = true ; } if ( NumRegs ) MBB . insert ( MI , & * MIB ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> void Z80FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool NVPTXFavorNonGenericAddrSpaces :: runOnFunction ( Function & F ) { if ( DisableFavorNonGeneric ) return false ; bool Changed = false ; for ( BasicBlock & B : F ) { for ( Instruction & I : B ) { if ( isa < LoadInst > ( I ) ) { Changed |= optimizeMemoryInstruction ( & I , 0 ) ; } else if ( isa < StoreInst > ( I ) ) { Changed |= optimizeMemoryInstruction ( & I , 1 ) ; } } } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> CCAssignFn * ARM64FastISel :: CCAssignFnForCall ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: WebKit_JS ) return CC_ARM64_WebKit_JS ; return Subtarget -> isTargetDarwin ( ) ? CC_ARM64_DarwinPCS : CC_ARM64_AAPCS ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> static void aarch64_emit_unlikely_jump ( rtx insn ) { rtx_insn * jump = emit_jump_insn ( insn ) ; add_reg_br_prob_note ( jump , profile_probability :: very_unlikely ( ) ) ; } </s>

Mark the previous jump instruction as unlikely .


"Custom lowering not defined for operation"

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool WebAssemblyTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { switch ( Intrinsic ) { case Intrinsic :: wasm_atomic_notify : Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: i32 ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . align = 4 ; Info . flags = MachineMemOperand :: MOVolatile | MachineMemOperand :: MOLoad ; return true ; case Intrinsic :: wasm_atomic_wait_i32 : Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: i32 ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . align = 4 ; Info . flags = MachineMemOperand :: MOVolatile | MachineMemOperand :: MOLoad ; return true ; case Intrinsic :: wasm_atomic_wait_i64 : Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: i64 ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . align = 8 ; Info . flags = MachineMemOperand :: MOVolatile | MachineMemOperand :: MOLoad ; return true ; default : return false ; } } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> void AMDGPUDAGToDAGISel :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < AMDGPUArgumentUsageInfo > ( ) ; AU . addRequired < LegacyDivergenceAnalysis > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; SelectionDAGISel :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool AArch64InstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF , bool OutlineFromLinkOnceODRs ) const { const Function & F = MF . getFunction ( ) ; if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) ) return false ; if ( F . hasSection ( ) ) return false ; AArch64FunctionInfo * AFI = MF . getInfo < AArch64FunctionInfo > ( ) ; if ( ! AFI || AFI -> hasRedZone ( ) . getValueOr ( true ) ) return false ; if ( MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) return false ; return true ; } </s>

Return true if the function can safely be outlined from .


<s> inline static int arm_constant_limit ( bool size_p ) { return size_p ? 1 : current_tune -> constant_limit ; } </s>

The maximum number of insns to be used when loading a constant .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


"********** AArch64 Conditional Compares **********\n"

runOnMachineFunction - Emit the function body .


<s> unsigned AArch64TTIImpl :: getIntrinsicInstrCost ( const IntrinsicCostAttributes & ICA , TTI :: TargetCostKind CostKind ) { auto * RetTy = ICA . getReturnType ( ) ; switch ( ICA . getID ( ) ) { case Intrinsic :: umin : case Intrinsic :: umax : { auto LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; if ( LT . second == MVT :: v2i64 ) return LT . first * 2 ; LLVM_FALLTHROUGH ; } case Intrinsic :: smin : case Intrinsic :: smax : { static const auto ValidMinMaxTys = { MVT :: v8i8 , MVT :: v16i8 , MVT :: v4i16 , MVT :: v8i16 , MVT :: v2i32 , MVT :: v4i32 } ; auto LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; if ( any_of ( ValidMinMaxTys , [ & LT ] ( MVT M ) { return M == LT . second ; } ) ) return LT . first ; break ; } default : break ; } return BaseT :: getIntrinsicInstrCost ( ICA , CostKind ) ; } </s>


<s> inline bool vgpr_2reg_mode_p ( machine_mode mode ) { return ( mode == DImode || mode == DFmode || mode == V64DImode || mode == V64DFmode ) ; } </s>

Return true if MODE is valid for pair of VGPR registers .


<s> const char * RISCVTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { case RISCVISD :: NODE : \ return "RISCVISD::" # NODE ; switch ( ( RISCVISD :: NodeType ) Opcode ) { case RISCVISD :: FIRST_NUMBER : break ; NODE_NAME_CASE ( RET_FLAG ) NODE_NAME_CASE ( URET_FLAG ) NODE_NAME_CASE ( SRET_FLAG ) NODE_NAME_CASE ( MRET_FLAG ) NODE_NAME_CASE ( CALL ) NODE_NAME_CASE ( SELECT_CC ) NODE_NAME_CASE ( BuildPairF64 ) NODE_NAME_CASE ( SplitF64 ) NODE_NAME_CASE ( TAIL ) NODE_NAME_CASE ( SLLW ) NODE_NAME_CASE ( SRAW ) NODE_NAME_CASE ( SRLW ) NODE_NAME_CASE ( DIVW ) NODE_NAME_CASE ( DIVUW ) NODE_NAME_CASE ( REMUW ) NODE_NAME_CASE ( ROLW ) NODE_NAME_CASE ( RORW ) NODE_NAME_CASE ( FSLW ) NODE_NAME_CASE ( FSRW ) NODE_NAME_CASE ( FMV_H_X ) NODE_NAME_CASE ( FMV_X_ANYEXTH ) NODE_NAME_CASE ( FMV_W_X_RV64 ) NODE_NAME_CASE ( FMV_X_ANYEXTW_RV64 ) NODE_NAME_CASE ( READ_CYCLE_WIDE ) NODE_NAME_CASE ( GREVI ) NODE_NAME_CASE ( GREVIW ) NODE_NAME_CASE ( GORCI ) NODE_NAME_CASE ( GORCIW ) NODE_NAME_CASE ( VMV_X_S ) NODE_NAME_CASE ( SPLAT_VECTOR_I64 ) NODE_NAME_CASE ( READ_VLENB ) NODE_NAME_CASE ( TRUNCATE_VECTOR ) NODE_NAME_CASE ( VLEFF ) NODE_NAME_CASE ( VLEFF_MASK ) NODE_NAME_CASE ( VLSEGFF ) NODE_NAME_CASE ( VLSEGFF_MASK ) NODE_NAME_CASE ( READ_VL ) NODE_NAME_CASE ( VSLIDEUP ) NODE_NAME_CASE ( VSLIDEDOWN ) NODE_NAME_CASE ( VID ) } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

RISCV RISCV RISCVISD::NODE "RISCVISD::" RISCVISD::NodeType RISCVISD::FIRST_NUMBER


"ARM PIC Global Base Reg Initialization"

getPassName - Return a nice clean name for a pass .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"SI Load / Store Optimizer"
;
}
</s>


<s>
void
MipsDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
if
(
trySelect
(
Node
)
)
return
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
ReplaceNode
(
Node
,
getGlobalBaseReg
(
)
)
;
return
;
case
ISD
::
LOAD
:
case
ISD
::
STORE
:
assert
(
(
Subtarget
->
systemSupportsUnalignedAccess
(
)
||
cast
<
MemSDNode
>
(
Node
)
->
getMemoryVT
(
)
.
getSizeInBits
(
)
/
8
<=
cast
<
MemSDNode
>
(
Node
)
->
getAlignment
(
)
)
&&
"Unexpected unaligned loads/stores."
)
;
break
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

Mips
Mips
"Selecting: "
"\n"
"== "
"\n"
1
ISD::GLOBAL_OFFSET_TABLE
ISD::LOAD
ISD::STORE
8
"Unexpected unaligned loads/stores."


<s> bool AArch64InstrInfo :: isStridedAccess ( const MachineInstr & MI ) const { return llvm :: any_of ( MI . memoperands ( ) , [ ] ( MachineMemOperand * MMO ) { return MMO -> getFlags ( ) & MOStridedAccess ; } ) ; } </s>

Return true if the given load or store is a strided memory access .


<s> unsigned Cpu0MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups ) const { if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; unsigned RegNo = getCpu0RegisterNumbering ( Reg ) ; return RegNo ; } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isFPImm ( ) ) { return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( 32 ) . getLimitedValue ( ) ) ; } assert ( MO . isExpr ( ) ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; if ( Kind == MCExpr :: Binary ) { Expr = static_cast < const MCBinaryExpr * > ( Expr ) -> getLHS ( ) ; Kind = Expr -> getKind ( ) ; } assert ( Kind == MCExpr :: SymbolRef ) ; Cpu0 :: Fixups FixupKind = Cpu0 :: Fixups ( 0 ) ; switch ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) ) { case MCSymbolRefExpr :: VK_Cpu0_GPREL : FixupKind = Cpu0 :: fixup_Cpu0_GPREL16 ; break ; case MCSymbolRefExpr :: VK_Cpu0_GOT_CALL : FixupKind = Cpu0 :: fixup_Cpu0_CALL24 ; break ; case MCSymbolRefExpr :: VK_Cpu0_GOT16 : FixupKind = Cpu0 :: fixup_Cpu0_GOT_Global ; break ; case MCSymbolRefExpr :: VK_Cpu0_GOT : FixupKind = Cpu0 :: fixup_Cpu0_GOT_Local ; break ; case MCSymbolRefExpr :: VK_Cpu0_ABS_HI : FixupKind = Cpu0 :: fixup_Cpu0_HI16 ; break ; case MCSymbolRefExpr :: VK_Cpu0_ABS_LO : FixupKind = Cpu0 :: fixup_Cpu0_LO16 ; break ; default : break ; } Fixups . push_back ( MCFixup :: Create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) ) ) ; return 0 ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> void AMDGPUTargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { switch ( N -> getOpcode ( ) ) { case ISD :: SIGN_EXTEND_INREG : return ; default : return ; } } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> static void ft32_setup_incoming_varargs ( cumulative_args_t cum_v , enum machine_mode mode , tree type ATTRIBUTE_UNUSED , int * pretend_size , int no_rtl ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int named_size = GET_MODE_SIZE ( SImode ) * ( * cum - FT32_R0 ) + GET_MODE_SIZE ( mode ) ; if ( named_size < 24 ) * pretend_size = 24 - named_size ; else * pretend_size = 0 ; } </s>

Worker function for TARGET_SETUP_INCOMING_VARARGS .


<s> static bool aarch64_base_register_rtx_p ( rtx x , bool strict_p ) { if ( ! strict_p && GET_CODE ( x ) == SUBREG ) x = SUBREG_REG ( x ) ; return ( REG_P ( x ) && aarch64_regno_ok_for_base_p ( REGNO ( x ) , strict_p ) ) ; } </s>

Return true if X is a valid base register for mode MODE . STRICT_P is true if REG_OK_STRICT is in effect .


<s> Register getExceptionPointerRegister ( const Constant * PersonalityFn ) const override { return SP :: I0 ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s> void LanaiTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { SDValue Result ( nullptr , 0 ) ; if ( Constraint . length ( ) > 1 ) return ; char ConstraintLetter = Constraint [ 0 ] ; switch ( ConstraintLetter ) { case 'I' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isInt < 16 > ( C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'J' : case 'O' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) == 0 ) { Result = DAG . getTargetConstant ( 0 , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'K' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isUInt < 16 > ( C -> getZExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'L' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= 31 ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'M' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { int64_t Val = C -> getSExtValue ( ) ; if ( ( isInt < 32 > ( Val ) ) && ( ( Val & 0xffff ) == 0 ) ) { Result = DAG . getTargetConstant ( Val , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'N' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { int64_t Val = C -> getSExtValue ( ) ; if ( ( Val >= - 33554432 ) && ( Val <= 33554431 ) ) { Result = DAG . getTargetConstant ( Val , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; default : break ; } if ( Result . getNode ( ) ) { Ops . push_back ( Result ) ; return ; } TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; } </s>

Lower the specified operand into the Ops vector .


<s> static rtx mmix_function_arg_1 ( const cumulative_args_t argsp_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED , bool incoming ) { CUMULATIVE_ARGS * argsp = get_cumulative_args ( argsp_v ) ; if ( type == void_type_node ) return ( argsp -> regs < MMIX_MAX_ARGS_IN_REGS ) ? gen_rtx_REG ( mode , ( incoming ? MMIX_FIRST_INCOMING_ARG_REGNUM : MMIX_FIRST_ARG_REGNUM ) + argsp -> regs ) : NULL_RTX ; return ( argsp -> regs < MMIX_MAX_ARGS_IN_REGS && ! targetm . calls . must_pass_in_stack ( mode , type ) && ( GET_MODE_BITSIZE ( mode ) <= 64 || argsp -> lib || TARGET_LIBFUNC ) ) ? gen_rtx_REG ( mode , ( incoming ? MMIX_FIRST_INCOMING_ARG_REGNUM : MMIX_FIRST_ARG_REGNUM ) + argsp -> regs ) : NULL_RTX ; } </s>

Helper function for mmix_function_arg and mmix_function_incoming_arg .


<s> void s390_expand_plus_operand ( rtx target , rtx src , rtx scratch ) { rtx sum1 , sum2 ; struct s390_address ad ; gcc_assert ( GET_CODE ( src ) == PLUS ) ; gcc_assert ( GET_MODE ( src ) == Pmode ) ; sum1 = find_replacement ( & XEXP ( src , 0 ) ) ; sum2 = find_replacement ( & XEXP ( src , 1 ) ) ; src = gen_rtx_PLUS ( Pmode , sum1 , sum2 ) ; if ( ! s390_decompose_address ( src , & ad ) || ( ad . base && ! REGNO_OK_FOR_BASE_P ( REGNO ( ad . base ) ) ) || ( ad . indx && ! REGNO_OK_FOR_INDEX_P ( REGNO ( ad . indx ) ) ) ) { if ( true_regnum ( sum1 ) < 1 || true_regnum ( sum1 ) > 15 ) { emit_move_insn ( scratch , sum1 ) ; sum1 = scratch ; } if ( true_regnum ( sum2 ) < 1 || true_regnum ( sum2 ) > 15 ) { emit_move_insn ( scratch , sum2 ) ; sum2 = scratch ; } if ( sum1 == scratch && sum2 == scratch ) { debug_rtx ( src ) ; gcc_unreachable ( ) ; } src = gen_rtx_PLUS ( Pmode , sum1 , sum2 ) ; } s390_load_address ( target , src ) ; } </s>

Generate code to load SRC , which is PLUS that is not a legitimate operand for the LA instruction , into TARGET . SCRATCH may be used as scratch register .


<s> void mips_split_move ( rtx dest , rtx src , enum mips_split_type split_type ) { rtx low_dest ; gcc_checking_assert ( mips_split_move_p ( dest , src , split_type ) ) ; if ( FP_REG_RTX_P ( dest ) || FP_REG_RTX_P ( src ) ) { if ( ! TARGET_64BIT && GET_MODE ( dest ) == DImode ) emit_insn ( gen_move_doubleword_fprdi ( dest , src ) ) ; else if ( ! TARGET_64BIT && GET_MODE ( dest ) == DFmode ) emit_insn ( gen_move_doubleword_fprdf ( dest , src ) ) ; else if ( ! TARGET_64BIT && GET_MODE ( dest ) == V2SFmode ) emit_insn ( gen_move_doubleword_fprv2sf ( dest , src ) ) ; else if ( ! TARGET_64BIT && GET_MODE ( dest ) == V2SImode ) emit_insn ( gen_move_doubleword_fprv2si ( dest , src ) ) ; else if ( ! TARGET_64BIT && GET_MODE ( dest ) == V4HImode ) emit_insn ( gen_move_doubleword_fprv4hi ( dest , src ) ) ; else if ( ! TARGET_64BIT && GET_MODE ( dest ) == V8QImode ) emit_insn ( gen_move_doubleword_fprv8qi ( dest , src ) ) ; else if ( TARGET_64BIT && GET_MODE ( dest ) == TFmode ) emit_insn ( gen_move_doubleword_fprtf ( dest , src ) ) ; else gcc_unreachable ( ) ; } else if ( REG_P ( dest ) && REGNO ( dest ) == MD_REG_FIRST ) { low_dest = mips_subword ( dest , false ) ; mips_emit_move ( low_dest , mips_subword ( src , false ) ) ; if ( TARGET_64BIT ) emit_insn ( gen_mthidi_ti ( dest , mips_subword ( src , true ) , low_dest ) ) ; else emit_insn ( gen_mthisi_di ( dest , mips_subword ( src , true ) , low_dest ) ) ; } else if ( REG_P ( src ) && REGNO ( src ) == MD_REG_FIRST ) { mips_emit_move ( mips_subword ( dest , false ) , mips_subword ( src , false ) ) ; if ( TARGET_64BIT ) emit_insn ( gen_mfhidi_ti ( mips_subword ( dest , true ) , src ) ) ; else emit_insn ( gen_mfhisi_di ( mips_subword ( dest , true ) , src ) ) ; } else { low_dest = mips_subword ( dest , false ) ; if ( REG_P ( low_dest ) && reg_overlap_mentioned_p ( low_dest , src ) ) { mips_emit_move ( mips_subword ( dest , true ) , mips_subword ( src , true ) ) ; mips_emit_move ( low_dest , mips_subword ( src , false ) ) ; } else { mips_emit_move ( low_dest , mips_subword ( src , false ) ) ; mips_emit_move ( mips_subword ( dest , true ) , mips_subword ( src , true ) ) ; } } } </s>

Split a move from SRC to DEST , given that mips_split_move_p holds . SPLIT_TYPE describes the split condition .


<s>
unsigned
getReg
(
)
const
{
assert
(
Kind
==
Register
&&
"Invalid access!"
)
;
return
Reg
.
RegNo
;
}
</s>

Returns the register associated with this edge .


<s> bool X86Subtarget :: enableEarlyIfConversion ( ) const { return hasCMov ( ) && X86EarlyIfConv ; } </s>

Enable the use of the early if conversion pass .


"%qE attribute only applies to functions"

Handle an attribute requiring a FUNCTION_DECL ; arguments as in struct attribute_spec.handler .


<s> void ia64_split_return_addr_rtx ( rtx dest ) { rtx src ; if ( TEST_HARD_REG_BIT ( current_frame_info . mask , BR_REG ( 0 ) ) ) { if ( current_frame_info . reg_save_b0 != 0 ) src = gen_rtx_REG ( DImode , current_frame_info . reg_save_b0 ) ; else { HOST_WIDE_INT off ; unsigned int regno ; off = ( current_frame_info . spill_cfa_off + current_frame_info . spill_size ) ; for ( regno = GR_REG ( 1 ) ; regno <= GR_REG ( 31 ) ; ++ regno ) if ( TEST_HARD_REG_BIT ( current_frame_info . mask , regno ) ) off -= 8 ; if ( frame_pointer_needed ) src = hard_frame_pointer_rtx ; else { src = stack_pointer_rtx ; off += current_frame_info . total_size ; } if ( CONST_OK_FOR_I ( off ) ) emit_insn ( gen_adddi3 ( dest , src , GEN_INT ( off ) ) ) ; else { emit_move_insn ( dest , GEN_INT ( off ) ) ; emit_insn ( gen_adddi3 ( dest , src , dest ) ) ; } src = gen_rtx_MEM ( Pmode , dest ) ; } } else src = gen_rtx_REG ( DImode , BR_REG ( 0 ) ) ; emit_move_insn ( dest , src ) ; } </s>

Split this value after reload , now that we know where the return address is saved .


<s> void rs6000_final_prescan_insn ( rtx_insn * insn , rtx [ ] , int ) { prepend_p_to_next_insn = ( get_attr_maybe_prefixed ( insn ) == MAYBE_PREFIXED_YES && get_attr_prefixed ( insn ) == PREFIXED_YES ) ; return ; } </s>

Define FINAL_PRESCAN_INSN if some processing needs to be done before outputting the assembler code . On the PowerPC , we remember if the current insn is a prefixed insn where we need to emit a ' p ' before the insn . In addition , if the insn is part of a PC-relative reference to an external label optimization , this is recorded also .


<s> static hash_set < basic_block > get_all_predecessors ( basic_block cfg_bb ) { hash_set < basic_block > blocks ; auto_vec < basic_block > work_list ; hash_set < basic_block > visited_list ; work_list . safe_push ( cfg_bb ) ; while ( ! work_list . is_empty ( ) ) { basic_block new_cfg_bb = work_list . pop ( ) ; visited_list . add ( new_cfg_bb ) ; edge e ; edge_iterator ei ; FOR_EACH_EDGE ( e , ei , new_cfg_bb -> preds ) { if ( ! visited_list . contains ( e -> src ) ) work_list . safe_push ( e -> src ) ; blocks . add ( e -> src ) ; } } return blocks ; } </s>

Recursively find all predecessor blocks for cfg_bb .


<s> static unsigned parse_field ( const char * field ) { const char * rest = strchr ( field , ':' ) ; char * after ; unsigned fint = strtol ( rest + 1 , & after , 16 ) ; if ( after == rest + 1 ) return - 1 ; return fint ; } </s>

Returns the hex integer that is after ' : ' for the FIELD . Returns -1 is returned if there was problem parsing the integer .


<s> int aarch64_vec_fpconst_pow_of_2 ( rtx x ) { int nelts ; if ( GET_CODE ( x ) != CONST_VECTOR || ! CONST_VECTOR_NUNITS ( x ) . is_constant ( & nelts ) ) return - 1 ; if ( GET_MODE_CLASS ( GET_MODE ( x ) ) != MODE_VECTOR_FLOAT ) return - 1 ; int firstval = aarch64_fpconst_pow_of_2 ( CONST_VECTOR_ELT ( x , 0 ) ) ; if ( firstval <= 0 ) return - 1 ; for ( int i = 1 ; i < nelts ; i ++ ) if ( aarch64_fpconst_pow_of_2 ( CONST_VECTOR_ELT ( x , i ) ) != firstval ) return - 1 ; return firstval ; } </s>

If X is a vector of equal CONST_DOUBLE values and that value is Y , return the aarch64_fpconst_pow_of_2 of Y . Otherwise return -1 .


<s> OperandMatchResultTy X86AsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { bool Result = ParseRegister ( RegNo , StartLoc , EndLoc , true ) ; bool PendingErrors = getParser ( ) . hasPendingError ( ) ; getParser ( ) . clearPendingErrors ( ) ; if ( PendingErrors ) return MatchOperand_ParseFail ; if ( Result ) return MatchOperand_NoMatch ; return MatchOperand_Success ; } </s>

tryParseRegister - parse one register if possible


<s> const MINA32MCExpr * MINA32MCExpr :: create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { return new ( Ctx ) MINA32MCExpr ( Kind , Expr ) ; } </s>


<s> static bool iq2000_pass_by_reference ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int size ; if ( cum && targetm . calls . must_pass_in_stack ( arg ) ) { CUMULATIVE_ARGS temp ; temp = * cum ; if ( iq2000_function_arg ( pack_cumulative_args ( & temp ) , arg ) != 0 ) return 1 ; } if ( arg . type == NULL_TREE || arg . mode == DImode || arg . mode == DFmode ) return 0 ; size = int_size_in_bytes ( arg . type ) ; return size == - 1 || size > UNITS_PER_WORD ; } </s>

Return true when an argument must be passed by reference .


<s> TargetLowering :: AtomicExpansionKind AArch64TargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size > 128 ) return AtomicExpansionKind :: None ; if ( AI -> getOperation ( ) == AtomicRMWInst :: Nand ) return AtomicExpansionKind :: LLSC ; return ( Subtarget -> hasLSE ( ) && Size < 128 ) ? AtomicExpansionKind :: None : AtomicExpansionKind :: LLSC ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> bool X86InstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , const SmallVectorImpl < MachineOperand > & Cond , unsigned TrueReg , unsigned FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( ! Subtarget . hasCMov ( ) ) return false ; if ( Cond . size ( ) != 1 ) return false ; if ( ( X86 :: CondCode ) Cond [ 0 ] . getImm ( ) > X86 :: COND_S ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( X86 :: GR16RegClass . hasSubClassEq ( RC ) || X86 :: GR32RegClass . hasSubClassEq ( RC ) || X86 :: GR64RegClass . hasSubClassEq ( RC ) ) { CondCycles = 2 ; TrueCycles = 2 ; FalseCycles = 2 ; return true ; } return false ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> bool ARMFrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { if ( STI . hasV8_1MMainlineOps ( ) && MF . getInfo < ARMFunctionInfo > ( ) -> isCmseNSEntryFunction ( ) ) { CSI . emplace_back ( ARM :: FPCXTNS ) ; CSI . back ( ) . setRestored ( false ) ; } const auto & AFI = * MF . getInfo < ARMFunctionInfo > ( ) ; if ( AFI . shouldSignReturnAddress ( ) ) { CSI . insert ( find_if ( CSI , [ = ] ( const auto & CS ) { unsigned Reg = CS . getReg ( ) ; return Reg == ARM :: R10 || Reg == ARM :: R11 || Reg == ARM :: R8 || Reg == ARM :: R9 || ARM :: DPRRegClass . contains ( Reg ) ; } ) , CalleeSavedInfo ( ARM :: R12 ) ) ; } return false ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


If the following function returns TRUE , we will use the DFA insn scheduler .


"saturation bit range must be in the range [%wd, %wd]"

"saturation bit range must be a constant immediate"

Expand an ACLE builtin , i.e . those registered only if their respective target constraints are met . This check happens within arm_expand_builtin_args .


<s> bool isMem ( ) const override { return false ; } </s>


<s> const X86Subtarget * getSubtarget ( ) const { return Subtarget ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasV4TOps ( false ) , HasV5TOps ( false ) , HasV5TEOps ( false ) , HasV6Ops ( false ) , HasV6T2Ops ( false ) , HasV7Ops ( false ) , HasVFPv2 ( false ) , HasVFPv3 ( false ) , HasVFPv4 ( false ) , HasNEON ( false ) , HasNEON2 ( false ) , UseNEONForSinglePrecisionFP ( false ) , SlowFPVMLx ( false ) , HasVMLxForwarding ( false ) , SlowFPBrcc ( false ) , InThumbMode ( false ) , HasThumb2 ( false ) , IsMClass ( false ) , NoARM ( false ) , PostRAScheduler ( false ) , IsR9Reserved ( ReserveR9 ) , UseMovt ( false ) , SupportsTailCall ( false ) , HasFP16 ( false ) , HasD16 ( false ) , HasHardwareDivide ( false ) , HasT2ExtractPack ( false ) , HasDataBarrier ( false ) , Pref32BitThumb ( false ) , AvoidCPSRPartialUpdate ( false ) , HasMPExtension ( false ) , FPOnlySP ( false ) , AllowsUnalignedMem ( false ) , Thumb2DSP ( false ) , stackAlignment ( 4 ) , CPUString ( CPU ) , TargetTriple ( TT ) , TargetABI ( ARM_ABI_APCS ) { if ( CPUString . empty ( ) ) CPUString = "generic" ; std :: string ArchFS = ARM_MC :: ParseARMTriple ( TT ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ArchFS + "," + FS ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; if ( ! HasV6T2Ops && hasThumb2 ( ) ) HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; computeIssueWidth ( ) ; if ( TT . find ( "eabi" ) != std :: string :: npos ) TargetABI = ARM_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = 8 ; if ( ! isTargetIOS ( ) ) UseMovt = hasV6T2Ops ( ) ; else { IsR9Reserved = ReserveR9 | ! HasV6Ops ; UseMovt = DarwinUseMOVT && hasV6T2Ops ( ) ; SupportsTailCall = ! getTargetTriple ( ) . isOSVersionLT ( 5 , 0 ) ; } if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; if ( ! StrictAlign && hasV6Ops ( ) && isTargetDarwin ( ) ) AllowsUnalignedMem = true ; } </s>

This constructor initializes the data members to match that of the specified triple .

ARM ARM ARM ARM ARM ARM 4 ARM "generic" ARM ARM "," "eabi" ARM 8 5 0


<s> X86Subtarget :: X86Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const X86TargetMachine & TM , unsigned StackAlignOverride ) : X86GenSubtargetInfo ( TT , CPU , FS ) , X86ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TM ( TM ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , TSInfo ( ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( * this , getStackAlignment ( ) ) { if ( TM . getRelocationModel ( ) == Reloc :: Static ) { setPICStyle ( PICStyles :: None ) ; } else if ( is64Bit ( ) ) { setPICStyle ( PICStyles :: RIPRel ) ; } else if ( isTargetCOFF ( ) ) { setPICStyle ( PICStyles :: None ) ; } else if ( isTargetDarwin ( ) ) { if ( isPositionIndependent ( ) ) setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( TM . getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( isTargetELF ( ) ) { setPICStyle ( PICStyles :: GOT ) ; } } </s>


"Malformed basic block: unconditional branch not last"

Remove the branching code at the end of the specific MBB .


<s> bool X86InstrInfo :: analyzeCompare ( const MachineInstr & MI , unsigned & SrcReg , unsigned & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI . getOpcode ( ) ) { default : break ; case X86 :: CMP64ri32 : case X86 :: CMP64ri8 : case X86 :: CMP32ri : case X86 :: CMP32ri8 : case X86 :: CMP16ri : case X86 :: CMP16ri8 : case X86 :: CMP8ri : if ( ! MI . getOperand ( 1 ) . isImm ( ) ) return false ; SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 1 ) . getImm ( ) ; return true ; case X86 :: SUB64rm : case X86 :: SUB32rm : case X86 :: SUB16rm : case X86 :: SUB8rm : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case X86 :: SUB64rr : case X86 :: SUB32rr : case X86 :: SUB16rr : case X86 :: SUB8rr : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 2 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case X86 :: SUB64ri32 : case X86 :: SUB64ri8 : case X86 :: SUB32ri : case X86 :: SUB32ri8 : case X86 :: SUB16ri : case X86 :: SUB16ri8 : case X86 :: SUB8ri : if ( ! MI . getOperand ( 2 ) . isImm ( ) ) return false ; SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 2 ) . getImm ( ) ; return true ; case X86 :: CMP64rr : case X86 :: CMP32rr : case X86 :: CMP16rr : case X86 :: CMP8rr : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 1 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case X86 :: TEST8rr : case X86 :: TEST16rr : case X86 :: TEST32rr : case X86 :: TEST64rr : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; if ( MI . getOperand ( 1 ) . getReg ( ) != SrcReg ) return false ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> void PPCInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC ) const { MachineFunction & MF = * MBB . getParent ( ) ; SmallVector < MachineInstr * , 4 > NewMIs ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; LoadRegFromStackSlot ( MF , DL , DestReg , FrameIdx , RC , NewMIs ) ; for ( unsigned i = 0 , e = NewMIs . size ( ) ; i != e ; ++ i ) MBB . insert ( MI , NewMIs [ i ] ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> static int ix86_avx_u128_mode_needed ( rtx_insn * insn ) { if ( DEBUG_INSN_P ( insn ) ) return AVX_U128_ANY ; if ( CALL_P ( insn ) ) { rtx link ; for ( link = CALL_INSN_FUNCTION_USAGE ( insn ) ; link ; link = XEXP ( link , 1 ) ) { if ( GET_CODE ( XEXP ( link , 0 ) ) == USE ) { rtx arg = XEXP ( XEXP ( link , 0 ) , 0 ) ; if ( ix86_check_avx_upper_register ( arg ) ) return AVX_U128_DIRTY ; } } bool avx_upper_reg_found = false ; note_stores ( insn , ix86_check_avx_upper_stores , & avx_upper_reg_found ) ; if ( avx_upper_reg_found ) return AVX_U128_DIRTY ; const function_abi & abi = insn_callee_abi ( insn ) ; if ( ! hard_reg_set_subset_p ( reg_class_contents [ SSE_REGS ] , abi . mode_clobbers ( V4DImode ) ) ) return AVX_U128_ANY ; return AVX_U128_CLEAN ; } subrtx_iterator :: array_type array ; rtx set = single_set ( insn ) ; if ( set ) { rtx dest = SET_DEST ( set ) ; rtx src = SET_SRC ( set ) ; if ( ix86_check_avx_upper_register ( dest ) ) { if ( standard_sse_constant_p ( src , GET_MODE ( dest ) ) != 1 ) return AVX_U128_DIRTY ; else return AVX_U128_ANY ; } else { FOR_EACH_SUBRTX ( iter , array , src , NONCONST ) if ( ix86_check_avx_upper_register ( * iter ) ) return AVX_U128_DIRTY ; } return AVX_U128_ANY ; } FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , NONCONST ) if ( ix86_check_avx_upper_register ( * iter ) ) return AVX_U128_DIRTY ; return AVX_U128_ANY ; } </s>

Return needed mode for entity in optimize_mode_switching pass .


"SGPR spill should have been removed in SILowerSGPRSpills"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


"Unknown fence ordering in emitLeadingFence"


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> void GCNPassConfig :: addOptimizedRegAlloc ( ) { if ( OptExecMaskPreRA ) { insertPass ( & MachineSchedulerID , & SIOptimizeExecMaskingPreRAID ) ; insertPass ( & SIOptimizeExecMaskingPreRAID , & SIFormMemoryClausesID ) ; } else { insertPass ( & MachineSchedulerID , & SIFormMemoryClausesID ) ; } insertPass ( & PHIEliminationID , & SILowerControlFlowID , false ) ; insertPass ( & RegisterCoalescerID , & SIPreAllocateWWMRegsID , false ) ; if ( EnableDCEInRA ) insertPass ( & RenameIndependentSubregsID , & DeadMachineInstructionElimID ) ; TargetPassConfig :: addOptimizedRegAlloc ( ) ; } </s>

addOptimizedRegAlloc - Add passes related to register allocation .


<s> static bool dimode_scalar_to_vector_candidate_p ( rtx_insn * insn ) { rtx def_set = single_set ( insn ) ; if ( ! def_set ) return false ; if ( has_non_address_hard_reg ( insn ) ) return false ; rtx src = SET_SRC ( def_set ) ; rtx dst = SET_DEST ( def_set ) ; if ( GET_CODE ( src ) == COMPARE ) return convertible_comparison_p ( insn ) ; if ( ( GET_MODE ( src ) != DImode && ! CONST_INT_P ( src ) ) || GET_MODE ( dst ) != DImode ) return false ; if ( ! REG_P ( dst ) && ! MEM_P ( dst ) ) return false ; switch ( GET_CODE ( src ) ) { case ASHIFTRT : if ( ! TARGET_AVX512VL ) return false ; case ASHIFT : case LSHIFTRT : if ( ! REG_P ( XEXP ( src , 1 ) ) && ( ! SUBREG_P ( XEXP ( src , 1 ) ) || SUBREG_BYTE ( XEXP ( src , 1 ) ) != 0 || ! REG_P ( SUBREG_REG ( XEXP ( src , 1 ) ) ) ) && ( ! CONST_INT_P ( XEXP ( src , 1 ) ) || ! IN_RANGE ( INTVAL ( XEXP ( src , 1 ) ) , 0 , 63 ) ) ) return false ; if ( GET_MODE ( XEXP ( src , 1 ) ) != QImode && ! CONST_INT_P ( XEXP ( src , 1 ) ) ) return false ; break ; case PLUS : case MINUS : case IOR : case XOR : case AND : if ( ! REG_P ( XEXP ( src , 1 ) ) && ! MEM_P ( XEXP ( src , 1 ) ) && ! CONST_INT_P ( XEXP ( src , 1 ) ) ) return false ; if ( GET_MODE ( XEXP ( src , 1 ) ) != DImode && ! CONST_INT_P ( XEXP ( src , 1 ) ) ) return false ; break ; case NEG : case NOT : break ; case REG : return true ; case MEM : case CONST_INT : return REG_P ( dst ) ; default : return false ; } if ( ! REG_P ( XEXP ( src , 0 ) ) && ! MEM_P ( XEXP ( src , 0 ) ) && ! CONST_INT_P ( XEXP ( src , 0 ) ) && ( GET_CODE ( src ) != AND || GET_CODE ( XEXP ( src , 0 ) ) != NOT || ! REG_P ( XEXP ( XEXP ( src , 0 ) , 0 ) ) ) ) return false ; if ( GET_MODE ( XEXP ( src , 0 ) ) != DImode && ! CONST_INT_P ( XEXP ( src , 0 ) ) ) return false ; return true ; } </s>

The DImode version of scalar_to_vector_candidate_p .


<s> static int mcore_arg_partial_bytes ( cumulative_args_t cum , const function_arg_info & arg ) { int reg = ROUND_REG ( * get_cumulative_args ( cum ) , arg . mode ) ; if ( ! arg . named ) return 0 ; if ( targetm . calls . must_pass_in_stack ( arg ) ) return 0 ; if ( reg >= NPARM_REGS ) return 0 ; if ( reg + mcore_num_arg_regs ( arg . mode , arg . type ) <= NPARM_REGS ) return 0 ; reg = NPARM_REGS - reg ; return reg * UNITS_PER_WORD ; } </s>

Returns the number of bytes of argument registers required to hold * part * of a parameter of machine mode MODE and type TYPE ( which may be NULL if the type is not known ) . If the argument fits entirely in the argument registers , or entirely on the stack , then 0 is returned . CUM is the number of argument registers already used by earlier parameters to the function .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesAll ( ) ; AU . addRequired < MachineModuleInfo > ( ) ; AU . addRequired < DwarfWriter > ( ) ; AsmPrinter :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool NPEnginePassConfig :: addPreEmitPass ( ) { return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
MachineBasicBlock
*
SparcTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
const
TargetInstrInfo
&
TII
=
*
getTargetMachine
(
)
.
getInstrInfo
(
)
;
unsigned
BROpcode
;
unsigned
CC
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown SELECT_CC!"
)
;
case
SP
::
SELECT_CC_Int_ICC
:
case
SP
::
SELECT_CC_FP_ICC
:
case
SP
::
SELECT_CC_DFP_ICC
:
case
SP
::
SELECT_CC_QFP_ICC
:
BROpcode
=
SP
::
BCOND
;
break
;
case
SP
::
SELECT_CC_Int_FCC
:
case
SP
::
SELECT_CC_FP_FCC
:
case
SP
::
SELECT_CC_DFP_FCC
:
case
SP
::
SELECT_CC_QFP_FCC
:
BROpcode
=
SP
::
FBCOND
;
break
;
}
CC
=
(
SPCC
::
CondCodes
)
MI
->
getOperand
(
3
)
.
getImm
(
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
It
=
BB
;
++
It
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
sinkMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
F
->
insert
(
It
,
copy0MBB
)
;
F
->
insert
(
It
,
sinkMBB
)
;
sinkMBB
->
splice
(
sinkMBB
->
begin
(
)
,
BB
,
llvm
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
BB
->
end
(
)
)
;
sinkMBB
->
transferSuccessorsAndUpdatePHIs
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
sinkMBB
)
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
BROpcode
)
)
.
addMBB
(
sinkMBB
)
.
addImm
(
CC
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
sinkMBB
;
BuildMI
(
*
BB
,
BB
->
begin
(
)
,
dl
,
TII
.
get
(
SP
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
MI
->
eraseFromParent
(
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> void MipsAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsPCRel ) const { MCFixupKind Kind = Fixup . getKind ( ) ; MCContext & Ctx = Asm . getContext ( ) ; Value = adjustFixupValue ( Fixup , Value , Ctx ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { case FK_Data_2 : case Mips :: fixup_Mips_16 : case Mips :: fixup_MICROMIPS_PC10_S1 : FullSize = 2 ; break ; case FK_Data_8 : case Mips :: fixup_Mips_64 : FullSize = 8 ; break ; case FK_Data_4 : default : FullSize = 4 ; break ; } uint64_t CurVal = 0 ; bool microMipsLEByteOrder = needsMMLEByteOrder ( ( unsigned ) Kind ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? ( microMipsLEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - 1 - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? ( microMipsLEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> yaml :: MachineFunctionInfo * GCNTargetMachine :: createDefaultFuncInfoYAML ( ) const { return new yaml :: SIMachineFunctionInfo ( ) ; } </s>

Allocate and return a default initialized instance of the YAML representation for the MachineFunctionInfo .


"Instr doesn't have FrameIndex operand!"

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s> bool MINA32DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < MINA32Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool SIInsertSkips :: runOnMachineFunction ( MachineFunction & MF ) { const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; SkipThreshold = SkipThresholdFlag ; bool HaveKill = false ; bool MadeChange = false ; SmallVector < MachineBasicBlock * , 16 > ExecBranchStack ; MachineFunction :: iterator NextBB ; MachineBasicBlock * EmptyMBBAtEnd = nullptr ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; BI = NextBB ) { NextBB = std :: next ( BI ) ; MachineBasicBlock & MBB = * BI ; bool HaveSkipBlock = false ; if ( ! ExecBranchStack . empty ( ) && ExecBranchStack . back ( ) == & MBB ) { ExecBranchStack . pop_back ( ) ; } if ( HaveKill && ExecBranchStack . empty ( ) ) { HaveKill = false ; } MachineBasicBlock :: iterator I , Next ; for ( I = MBB . begin ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; switch ( MI . getOpcode ( ) ) { case AMDGPU :: SI_MASK_BRANCH : ExecBranchStack . push_back ( MI . getOperand ( 0 ) . getMBB ( ) ) ; MadeChange |= skipMaskBranch ( MI , MBB ) ; break ; case AMDGPU :: S_BRANCH : if ( MBB . isLayoutSuccessor ( MI . getOperand ( 0 ) . getMBB ( ) ) ) { MI . eraseFromParent ( ) ; } else if ( HaveSkipBlock ) { MI . eraseFromParent ( ) ; } break ; case AMDGPU :: SI_KILL_F32_COND_IMM_TERMINATOR : case AMDGPU :: SI_KILL_I1_TERMINATOR : MadeChange = true ; kill ( MI ) ; if ( ExecBranchStack . empty ( ) ) { if ( skipIfDead ( MI , * NextBB ) ) { HaveSkipBlock = true ; NextBB = std :: next ( BI ) ; BE = MF . end ( ) ; } } else { HaveKill = true ; } MI . eraseFromParent ( ) ; break ; case AMDGPU :: SI_RETURN_TO_EPILOG : assert ( ! MF . getInfo < SIMachineFunctionInfo > ( ) -> returnsVoid ( ) ) ; if ( BI != -- MF . end ( ) || I != MBB . getFirstTerminator ( ) ) { if ( ! EmptyMBBAtEnd ) { EmptyMBBAtEnd = MF . CreateMachineBasicBlock ( ) ; MF . insert ( MF . end ( ) , EmptyMBBAtEnd ) ; } MBB . addSuccessor ( EmptyMBBAtEnd ) ; BuildMI ( * BI , I , MI . getDebugLoc ( ) , TII -> get ( AMDGPU :: S_BRANCH ) ) . addMBB ( EmptyMBBAtEnd ) ; I -> eraseFromParent ( ) ; } break ; default : break ; } } } return MadeChange ; } </s>


<s>
const
char
*
getPassName
(
)
const
override
{
return
"AArch64 branch relaxation pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static int uses_TOC ( void ) { rtx_insn * insn ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) ) { rtx pat = PATTERN ( insn ) ; int i ; if ( GET_CODE ( pat ) == PARALLEL ) for ( i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) { rtx sub = XVECEXP ( pat , 0 , i ) ; if ( GET_CODE ( sub ) == USE ) { sub = XEXP ( sub , 0 ) ; if ( GET_CODE ( sub ) == UNSPEC && XINT ( sub , 1 ) == UNSPEC_TOC ) return 1 ; } } } return 0 ; } </s>

This retuns nonzero if the current function uses the TOC . This is determined by the presence of ( unspec ... 7 ) , which is generated by the various load_toc_ * patterns .


<s>
void
Hexagon_CCState
::
AnalyzeCallOperands
(
SmallVectorImpl
<
EVT
>
&
ArgVTs
,
SmallVectorImpl
<
ISD
::
ArgFlagsTy
>
&
Flags
,
Hexagon_CCAssignFn
Fn
)
{
unsigned
NumOps
=
ArgVTs
.
size
(
)
;
for
(
unsigned
i
=
0
;
i
!=
NumOps
;
++
i
)
{
EVT
ArgVT
=
ArgVTs
[
i
]
;
ISD
::
ArgFlagsTy
ArgFlags
=
Flags
[
i
]
;
if
(
Fn
(
i
,
ArgVT
,
ArgVT
,
CCValAssign
::
Full
,
ArgFlags
,
*
this
,
1
,
1
,
false
)
)
{
dbgs
(
)
<<
"Call operand #"
<<
i
<<
" has unhandled type "
<<
ArgVT
.
getEVTString
(
)
<<
"\n"
;
abort
(
)
;
}
}
}
</s>

AnalyzeCallOperands - Same as above except it takes vectors of types and argument flags .

Hexagon
Hexagon
ISD::ArgFlagsTy
Hexagon
0
ISD::ArgFlagsTy
1
1
"Call operand #"
" has unhandled type "
"\n"


<s> MVT X86TargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , EVT VT ) const { if ( VT == MVT :: v32i1 && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return MVT :: v32i8 ; return TargetLowering :: getRegisterTypeForCallingConv ( Context , VT ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


<s> bool AArch64PassConfig :: addILPOpts ( ) { if ( EnableCondOpt ) addPass ( createAArch64ConditionOptimizerPass ( ) ) ; if ( EnableCCMP ) addPass ( createAArch64ConditionalCompares ( ) ) ; if ( EnableMCR ) addPass ( & MachineCombinerID ) ; if ( EnableCondBrTuning ) addPass ( createAArch64CondBrTuning ( ) ) ; if ( EnableEarlyIfConversion ) addPass ( & EarlyIfConverterID ) ; if ( EnableStPairSuppress ) addPass ( createAArch64StorePairSuppressPass ( ) ) ; addPass ( createAArch64VectorByElementOptPass ( ) ) ; return true ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .


<s>
bool
MOSCallLowering
::
lowerReturn
(
MachineIRBuilder
&
MIRBuilder
,
const
Value
*
Val
,
ArrayRef
<
Register
>
VRegs
,
FunctionLoweringInfo
&
FLI
)
const
{
MachineFunction
&
MF
=
MIRBuilder
.
getMF
(
)
;
const
auto
&
TFI
=
static_cast
<
const
MOSFrameLowering
&
>
(
*
MF
.
getSubtarget
(
)
.
getFrameLowering
(
)
)
;
const
Function
&
F
=
MF
.
getFunction
(
)
;
auto
Return
=
MIRBuilder
.
buildInstrNoInsert
(
TFI
.
isISR
(
MF
)
MOS
::
RTI
:
MOS
::
RTS
)
;
if
(
Val
)
{
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
const
TargetLowering
&
TLI
=
*
getTLI
(
)
;
const
DataLayout
&
DL
=
MF
.
getDataLayout
(
)
;
LLVMContext
&
Ctx
=
Val
->
getContext
(
)
;
SmallVector
<
EVT
>
ValueVTs
;
ComputeValueVTs
(
TLI
,
DL
,
Val
->
getType
(
)
,
ValueVTs
)
;
SmallVector
<
LLT
>
ValueLLTs
;
computeValueLLTs
(
DL
,
*
Val
->
getType
(
)
,
ValueLLTs
)
;
assert
(
ValueVTs
.
size
(
)
==
VRegs
.
size
(
)
&&
"Need one MVT for each VReg."
)
;
assert
(
ValueLLTs
.
size
(
)
==
VRegs
.
size
(
)
&&
"Need one LLT for each VReg."
)
;
SmallVector
<
ArgInfo
>
Args
;
for
(
const
auto
&
I
:
zip
(
VRegs
,
ValueVTs
,
ValueLLTs
)
)
{
Args
.
emplace_back
(
std
::
get
<
0
>
(
I
)
,
std
::
get
<
1
>
(
I
)
.
getTypeForEVT
(
Ctx
)
,
0
)
;
setArgFlags
(
Args
.
back
(
)
,
AttributeList
::
ReturnIndex
,
DL
,
F
)
;
adjustArgFlags
(
Args
.
back
(
)
,
std
::
get
<
2
>
(
I
)
)
;
}
MOSOutgoingReturnHandler
Handler
(
MIRBuilder
,
Return
,
MRI
)
;
MOSValueAssigner
Assigner
(
false
,
MRI
,
MF
)
;
if
(
!
determineAndHandleAssignments
(
Handler
,
Assigner
,
Args
,
MIRBuilder
,
F
.
getCallingConv
(
)
,
F
.
isVarArg
(
)
)
)
return
false
;
}
MIRBuilder
.
insertInstr
(
Return
)
;
return
true
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .

MOS
MOS
MOS
MOS::RTI
MOS::RTS
"Need one MVT for each VReg."
"Need one LLT for each VReg."
0
1
0
2
MOS
MOS


"Can only insert epilog into returning blocks"


<s> void PPCInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << getRegisterName ( RegNo ) ; } </s>


<s> void HexagonCommonGEP :: removeDeadCode ( ) { ValueVect BO ; BO . push_back ( & Fn -> front ( ) ) ; for ( unsigned i = 0 ; i < BO . size ( ) ; ++ i ) { BasicBlock * B = cast < BasicBlock > ( BO [ i ] ) ; for ( auto DTN : children < DomTreeNode * > ( DT -> getNode ( B ) ) ) BO . push_back ( DTN -> getBlock ( ) ) ; } for ( Value * V : llvm :: reverse ( BO ) ) { BasicBlock * B = cast < BasicBlock > ( V ) ; ValueVect Ins ; for ( Instruction & I : llvm :: reverse ( * B ) ) Ins . push_back ( & I ) ; for ( Value * I : Ins ) { Instruction * In = cast < Instruction > ( I ) ; if ( isInstructionTriviallyDead ( In ) ) In -> eraseFromParent ( ) ; } } } </s>

Remove all dead instructions between the I and E .