<s> MipsTargetLowering :: ConstraintType MipsTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'd' : case 'y' : case 'f' : case 'c' : case 'l' : case 'x' : return C_RegisterClass ; case 'R' : return C_Memory ; } } if ( Constraint == "ZC" ) return C_Memory ; return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> void split_ti ( rtx operands [ ] , int num , rtx lo_half [ ] , rtx hi_half [ ] ) { while ( num -- ) { rtx op = operands [ num ] ; if ( GET_CODE ( op ) == MEM ) { lo_half [ num ] = adjust_address ( op , DImode , 0 ) ; hi_half [ num ] = adjust_address ( op , DImode , 8 ) ; } else { lo_half [ num ] = simplify_gen_subreg ( DImode , op , TImode , 0 ) ; hi_half [ num ] = simplify_gen_subreg ( DImode , op , TImode , 8 ) ; } } } </s>

Split one or more TImode RTL references into pairs of DImode references . The RTL can be REG , offsettable MEM , integer constant , or CONST_DOUBLE . `` operands '' is a pointer to an array of DImode RTL to split and `` num '' is its length . lo_half and hi_half are output arrays that parallel `` operands '' .


<s>
const
uint32_t
*
Z80oldRegisterInfo
::
getCallPreservedMask
(
const
MachineFunction
&
MF
,
CallingConv
::
ID
CC
)
const
{
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
CSR_Z80old_C_RegMask
;
case
CallingConv
::
PreserveAll
:
case
CallingConv
::
Z80_LibCall
:
case
CallingConv
::
Z80_LibCall_AC
:
case
CallingConv
::
Z80_LibCall_BC
:
case
CallingConv
::
Z80_LibCall_C
:
case
CallingConv
::
Z80_LibCall_L
:
return
CSR_Z80old_AllRegs_RegMask
;
}
}
</s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void GCNPassConfig :: addPreEmitPass ( ) { addPass ( createSIMemoryLegalizerPass ( ) ) ; addPass ( createSIInsertWaitcntsPass ( ) ) ; addPass ( createSIShrinkInstructionsPass ( ) ) ; addPass ( createSIModeRegisterPass ( ) ) ; if ( getOptLevel ( ) > CodeGenOpt :: None ) addPass ( & SIInsertHardClausesID ) ; addPass ( & SILateBranchLoweringPassID ) ; if ( getOptLevel ( ) > CodeGenOpt :: None ) addPass ( & SIPreEmitPeepholeID ) ; addPass ( & PostRAHazardRecognizerID ) ; addPass ( & BranchRelaxationPassID ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void SIFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const SIMachineFunctionInfo * FuncInfo = MF . getInfo < SIMachineFunctionInfo > ( ) ; if ( FuncInfo -> isEntryFunction ( ) ) return ; const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; const SIInstrInfo * TII = ST . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; for ( const SIMachineFunctionInfo :: SGPRSpillVGPRCSR & Reg : FuncInfo -> getSGPRSpillVGPRs ( ) ) { if ( ! Reg . FI . hasValue ( ) ) continue ; TII -> loadRegFromStackSlot ( MBB , MBBI , Reg . VGPR , Reg . FI . getValue ( ) , & AMDGPU :: VGPR_32RegClass , & TII -> getRegisterInfo ( ) ) ; } unsigned StackPtrReg = FuncInfo -> getStackPtrOffsetReg ( ) ; if ( StackPtrReg == AMDGPU :: NoRegister ) return ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; uint32_t NumBytes = MFI . getStackSize ( ) ; DebugLoc DL ; if ( NumBytes != 0 && hasSP ( MF ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( AMDGPU :: S_SUB_U32 ) , StackPtrReg ) . addReg ( StackPtrReg ) . addImm ( NumBytes * ST . getWavefrontSize ( ) ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } } </s>

AMDGPU SI SI SI SI SI SI SI AMDGPU::VGPR_32RegClass AMDGPU::NoRegister 0 AMDGPU::S_SUB_U32


<s> bool R600InstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { MachineOperand & MO = Cond [ 1 ] ; switch ( MO . getImm ( ) ) { case AMDGPU :: PRED_SETE_INT : MO . setImm ( AMDGPU :: PRED_SETNE_INT ) ; break ; case AMDGPU :: PRED_SETNE_INT : MO . setImm ( AMDGPU :: PRED_SETE_INT ) ; break ; case AMDGPU :: PRED_SETE : MO . setImm ( AMDGPU :: PRED_SETNE ) ; break ; case AMDGPU :: PRED_SETNE : MO . setImm ( AMDGPU :: PRED_SETE ) ; break ; default : return true ; } MachineOperand & MO2 = Cond [ 2 ] ; switch ( MO2 . getReg ( ) ) { case AMDGPU :: PRED_SEL_ZERO : MO2 . setReg ( AMDGPU :: PRED_SEL_ONE ) ; break ; case AMDGPU :: PRED_SEL_ONE : MO2 . setReg ( AMDGPU :: PRED_SEL_ZERO ) ; break ; default : return true ; } return false ; } </s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> static void aarch64_add_offset_1 ( scalar_int_mode mode , rtx dest , rtx src , HOST_WIDE_INT offset , rtx temp1 , bool frame_related_p , bool emit_move_imm ) { gcc_assert ( emit_move_imm || temp1 != NULL_RTX ) ; gcc_assert ( temp1 == NULL_RTX || ! reg_overlap_mentioned_p ( temp1 , src ) ) ; unsigned HOST_WIDE_INT moffset = absu_hwi ( offset ) ; rtx_insn * insn ; if ( ! moffset ) { if ( ! rtx_equal_p ( dest , src ) ) { insn = emit_insn ( gen_rtx_SET ( dest , src ) ) ; RTX_FRAME_RELATED_P ( insn ) = frame_related_p ; } return ; } if ( aarch64_uimm12_shift ( moffset ) ) { insn = emit_insn ( gen_add3_insn ( dest , src , GEN_INT ( offset ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = frame_related_p ; return ; } if ( moffset < 0x1000000 && ( ( ! temp1 && ! can_create_pseudo_p ( ) ) || ! aarch64_move_imm ( moffset , mode ) ) ) { HOST_WIDE_INT low_off = moffset & 0xfff ; low_off = offset < 0 ? - low_off : low_off ; insn = emit_insn ( gen_add3_insn ( dest , src , GEN_INT ( low_off ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = frame_related_p ; insn = emit_insn ( gen_add2_insn ( dest , GEN_INT ( offset - low_off ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = frame_related_p ; return ; } if ( emit_move_imm ) { gcc_assert ( temp1 != NULL_RTX || can_create_pseudo_p ( ) ) ; temp1 = aarch64_force_temporary ( mode , temp1 , gen_int_mode ( moffset , mode ) ) ; } insn = emit_insn ( offset < 0 ? gen_sub3_insn ( dest , src , temp1 ) : gen_add3_insn ( dest , src , temp1 ) ) ; if ( frame_related_p ) { RTX_FRAME_RELATED_P ( insn ) = frame_related_p ; rtx adj = plus_constant ( mode , src , offset ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( dest , adj ) ) ; } } </s>

A subroutine of aarch64_add_offset . Set DEST to SRC + OFFSET for a non-polynomial OFFSET . MODE is the mode of the addition . FRAME_RELATED_P is true if the RTX_FRAME_RELATED flag should be set and CFA adjustments added to the generated instructions . TEMP1 , if nonnull , is a register of mode MODE that can be used as a temporary if register allocation is already complete . This temporary register may overlap DEST but must not overlap SRC . If TEMP1 is known to hold abs ( OFFSET ) , EMIT_MOVE_IMM can be set to false to avoid emitting the immediate again . Since this function may be used to adjust the stack pointer , we must ensure that it can not cause transient stack deallocation ( for example by first incrementing SP and then decrementing when adjusting by a large immediate ) .


"Parsing feature error when emitTargetAttributes?"

Emit the build attributes that only depend on the hardware that we expect .


<s>
bool
m32c_mov_ok
(
rtx
*
operands
,
enum
machine_mode
mode
ATTRIBUTE_UNUSED
)
{
rtx
op0
=
operands
[
0
]
;
rtx
op1
=
operands
[
1
]
;
if
(
TARGET_A24
)
return
true
;
fprintf
(
stderr
,
"m32c_mov_ok %s\n"
,
mode_name
[
mode
]
)
;
debug_rtx
(
op0
)
;
debug_rtx
(
op1
)
;
if
(
GET_CODE
(
op0
)
==
SUBREG
)
op0
=
XEXP
(
op0
,
0
)
;
if
(
GET_CODE
(
op1
)
==
SUBREG
)
op1
=
XEXP
(
op1
,
0
)
;
if
(
GET_CODE
(
op0
)
==
MEM
&&
GET_CODE
(
op1
)
==
MEM
&&
!
reload_completed
)
{
fprintf
(
stderr
,
" - no, mem to mem\n"
)
;
return
false
;
}
fprintf
(
stderr
,
" - ok\n"
)
;
return
true
;
}
</s>

Returns TRUE if we support a move between the first two operands . At the moment , we just want to discourage mem to mem moves until after reload , because reload has a hard time with our limited number of address registers , and we can get into a situation where we need three of them when we only have two .


<s> bool AArch64TargetLowering :: shouldExpandGetActiveLaneMask ( EVT ResVT , EVT OpVT ) const { if ( ! Subtarget -> hasSVE ( ) ) return true ; if ( ResVT != MVT :: nxv2i1 && ResVT != MVT :: nxv4i1 && ResVT != MVT :: nxv8i1 && ResVT != MVT :: nxv16i1 && ResVT != MVT :: v2i1 && ResVT != MVT :: v4i1 && ResVT != MVT :: v8i1 && ResVT != MVT :: v16i1 ) return true ; if ( OpVT != MVT :: i32 && OpVT != MVT :: i64 ) return true ; return false ; } </s>

Return true if the @ llvm.get.active.lane.mask intrinsic should be expanded using generic code in SelectionDAGBuilder .


<s> void GCNPassConfig :: addPreSched2 ( ) { } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> gimple * gimple_folder :: fold_to_pfalse ( ) { return gimple_build_assign ( lhs , build_zero_cst ( TREE_TYPE ( lhs ) ) ) ; } </s>


<s>
Optional
<
RegImmPair
>
AArch64InstrInfo
::
isAddImmediate
(
const
MachineInstr
&
MI
,
Register
Reg
)
const
{
int
Sign
=
1
;
int64_t
Offset
=
0
;
const
MachineOperand
&
Op0
=
MI
.
getOperand
(
0
)
;
if
(
!
Op0
.
isReg
(
)
||
Reg
!=
Op0
.
getReg
(
)
)
return
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
return
;
case
AArch64
::
SUBWri
:
case
AArch64
::
SUBXri
:
case
AArch64
::
SUBSWri
:
case
AArch64
::
SUBSXri
:
Sign
*=
1
;
LLVM_FALLTHROUGH
;
case
AArch64
::
ADDSWri
:
case
AArch64
::
ADDSXri
:
case
AArch64
::
ADDWri
:
case
AArch64
::
ADDXri
:
{
if
(
!
MI
.
getOperand
(
0
)
.
isReg
(
)
||
!
MI
.
getOperand
(
1
)
.
isReg
(
)
||
!
MI
.
getOperand
(
2
)
.
isImm
(
)
)
return
;
int
Shift
=
MI
.
getOperand
(
3
)
.
getImm
(
)
;
assert
(
(
Shift
==
0
||
Shift
==
12
)
&&
"Shift can be either 0 or 12"
)
;
Offset
=
Sign
*
(
MI
.
getOperand
(
2
)
.
getImm
(
)
<<
Shift
)
;
}
}
return
RegImmPair
{
MI
.
getOperand
(
1
)
.
getReg
(
)
,
Offset
}
;
}
</s>

If the specific machine instruction is an instruction that adds an immediate value and a register , and stores the result in the given register Reg , return a pair of the source register and the offset which has been added .


<s> const MCExpr * M68kTargetLowering :: getPICJumpTableRelocBaseExpr ( const MachineFunction * MF , unsigned JTI , MCContext & Ctx ) const { return MCSymbolRefExpr :: create ( MF -> getJTISymbol ( JTI , Ctx ) , Ctx ) ; } </s>

This returns the relocation base for the given PIC jumptable , the same as getPICJumpTableRelocBase , but as an MCExpr .


"register_move_cost %s from %s to %s = %d\n"

Implements REGISTER_MOVE_COST . We make impossible moves prohibitively expensive , like trying to put QIs in r2/r3 ( there are no opcodes to do that ) . We also discourage use of mem * registers since they 're really memory .


<s> static rtx emit_new_cond_insn ( rtx insn , int cond ) { rtx c_insn = 0 ; rtx pat , dst , src ; cond_type num ; if ( ( num = is_cond_candidate ( insn ) ) == COND_NO ) return NULL ; pat = PATTERN ( insn ) ; if ( GET_CODE ( insn ) == INSN ) { dst = SET_DEST ( pat ) ; src = SET_SRC ( pat ) ; } else { dst = JUMP_LABEL ( insn ) ; src = NULL_RTX ; } switch ( num ) { case COND_MOV_INSN : case COND_CLR_INSN : if ( cond ) c_insn = gen_movt0 ( dst , src , dst ) ; else c_insn = gen_movt0 ( dst , dst , src ) ; break ; case COND_INC_INSN : if ( cond ) c_insn = gen_incscc ( dst , dst ) ; else c_insn = gen_incscc_false ( dst , dst ) ; break ; case COND_DEC_INSN : if ( cond ) c_insn = gen_decscc ( dst , dst ) ; else c_insn = gen_decscc_false ( dst , dst ) ; break ; case COND_BRANCH_INSN : if ( cond ) c_insn = gen_branch_true ( dst ) ; else c_insn = gen_branch_false ( dst ) ; break ; default : return NULL ; } if ( rtx_length [ GET_CODE ( c_insn ) ] >= 7 && rtx_length [ GET_CODE ( insn ) ] >= 7 ) { REG_NOTES ( c_insn ) = REG_NOTES ( insn ) ; } if ( num == COND_BRANCH_INSN ) { c_insn = emit_jump_insn_before ( c_insn , insn ) ; ++ LABEL_NUSES ( dst ) ; JUMP_LABEL ( c_insn ) = dst ; } else c_insn = emit_insn_after ( c_insn , insn ) ; delete_insn ( insn ) ; return c_insn ; } </s>

Emit a conditional version of insn and replace the old insn with the new one . Return the new insn if emitted .


<s> bool XtensaRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return false ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> int ARMTTIImpl :: getIntImmCost ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) { if ( ( Opcode == Instruction :: SDiv || Opcode == Instruction :: UDiv || Opcode == Instruction :: SRem || Opcode == Instruction :: URem ) && Idx == 1 ) return 0 ; if ( Opcode == Instruction :: And ) return std :: min ( getIntImmCost ( Imm , Ty ) , getIntImmCost ( ~ Imm , Ty ) ) ; if ( Opcode == Instruction :: Add ) return std :: min ( getIntImmCost ( Imm , Ty ) , getIntImmCost ( - Imm , Ty ) ) ; if ( Opcode == Instruction :: ICmp && Imm . isNegative ( ) && Ty -> getIntegerBitWidth ( ) == 32 ) { int64_t NegImm = - Imm . getSExtValue ( ) ; if ( ST -> isThumb2 ( ) && NegImm < 1 << 12 ) return 0 ; if ( ST -> isThumb ( ) && NegImm < 1 << 8 ) return 0 ; } return getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> static bool is_imported_p ( rtx x ) { if ( ! TARGET_DLLIMPORT_DECL_ATTRIBUTES || GET_CODE ( x ) != SYMBOL_REF ) return false ; return SYMBOL_REF_DLLIMPORT_P ( x ) || SYMBOL_REF_STUBVAR_P ( x ) ; } </s>

Nonzero if the symbol is marked as dllimport , or as stub-variable , otherwise zero .


<s> const RegisterBankInfo * getRegBankInfo ( ) const override { return RegBankInfo . get ( ) ; } </s>

If the information for the register banks is available , return it .


"MIa must load from or modify a memory location"

"MIb must load from or modify a memory location"

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s>
bool
SIInstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
MachineBasicBlock
::
iterator
I
=
MBB
.
getFirstTerminator
(
)
;
auto
E
=
MBB
.
end
(
)
;
if
(
I
==
E
)
return
false
;
while
(
I
!=
E
&&
!
I
->
isBranch
(
)
&&
!
I
->
isReturn
(
)
)
{
switch
(
I
->
getOpcode
(
)
)
{
case
AMDGPU
::
S_MOV_B64_term
:
case
AMDGPU
::
S_XOR_B64_term
:
case
AMDGPU
::
S_OR_B64_term
:
case
AMDGPU
::
S_ANDN2_B64_term
:
case
AMDGPU
::
S_AND_B64_term
:
case
AMDGPU
::
S_MOV_B32_term
:
case
AMDGPU
::
S_XOR_B32_term
:
case
AMDGPU
::
S_OR_B32_term
:
case
AMDGPU
::
S_ANDN2_B32_term
:
case
AMDGPU
::
S_AND_B32_term
:
break
;
case
AMDGPU
::
SI_IF
:
case
AMDGPU
::
SI_ELSE
:
case
AMDGPU
::
SI_KILL_I1_TERMINATOR
:
case
AMDGPU
::
SI_KILL_F32_COND_IMM_TERMINATOR
:
return
true
;
default
:
llvm_unreachable
(
"unexpected non-branch terminator inst"
)
;
}
++
I
;
}
if
(
I
==
E
)
return
false
;
return
analyzeBranchImpl
(
MBB
,
I
,
TBB
,
FBB
,
Cond
,
AllowModify
)
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> static bool aarch64_can_inline_p ( tree caller , tree callee ) { tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET ( caller ) ; tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET ( callee ) ; struct cl_target_option * caller_opts = TREE_TARGET_OPTION ( caller_tree ? caller_tree : target_option_default_node ) ; struct cl_target_option * callee_opts = TREE_TARGET_OPTION ( callee_tree ? callee_tree : target_option_default_node ) ; if ( ( caller_opts -> x_aarch64_isa_flags & callee_opts -> x_aarch64_isa_flags ) != callee_opts -> x_aarch64_isa_flags ) return false ; if ( ( TARGET_STRICT_ALIGN_P ( caller_opts -> x_target_flags ) != TARGET_STRICT_ALIGN_P ( callee_opts -> x_target_flags ) ) && ! ( ! TARGET_STRICT_ALIGN_P ( callee_opts -> x_target_flags ) && TARGET_STRICT_ALIGN_P ( caller_opts -> x_target_flags ) ) ) return false ; bool always_inline = lookup_attribute ( "always_inline" , DECL_ATTRIBUTES ( callee ) ) ; if ( always_inline ) return true ; if ( caller_opts -> x_aarch64_cmodel_var != callee_opts -> x_aarch64_cmodel_var ) return false ; if ( caller_opts -> x_aarch64_tls_dialect != callee_opts -> x_aarch64_tls_dialect ) return false ; if ( ! aarch64_tribools_ok_for_inlining_p ( caller_opts -> x_aarch64_fix_a53_err835769 , callee_opts -> x_aarch64_fix_a53_err835769 , 2 , TARGET_FIX_ERR_A53_835769_DEFAULT ) ) return false ; if ( ! aarch64_tribools_ok_for_inlining_p ( caller_opts -> x_aarch64_fix_a53_err843419 , callee_opts -> x_aarch64_fix_a53_err843419 , 2 , TARGET_FIX_ERR_A53_843419 ) ) return false ; if ( ! aarch64_tribools_ok_for_inlining_p ( caller_opts -> x_flag_omit_leaf_frame_pointer , callee_opts -> x_flag_omit_leaf_frame_pointer , 2 , 1 ) ) return false ; if ( callee_opts -> x_aarch64_override_tune_string != NULL && caller_opts -> x_aarch64_override_tune_string == NULL ) return false ; if ( callee_opts -> x_aarch64_override_tune_string && caller_opts -> x_aarch64_override_tune_string && ( strcmp ( callee_opts -> x_aarch64_override_tune_string , caller_opts -> x_aarch64_override_tune_string ) != 0 ) ) return false ; return true ; } </s>

Implement TARGET_CAN_INLINE_P . Decide whether it is valid to inline CALLEE into CALLER based on target-specific info . Make sure that the caller and callee have compatible architectural features . Then go through the other possible target attributes and see if they can block inlining . Try not to reject always_inline callees unless they are incompatible architecturally .


<s> bool getAlign ( const Function & F , unsigned index , unsigned & align ) { std :: vector < unsigned > Vs ; bool retval = findAllNVVMAnnotation ( & F , "align" , Vs ) ; if ( ! retval ) return false ; for ( int i = 0 , e = Vs . size ( ) ; i < e ; i ++ ) { unsigned v = Vs [ i ] ; if ( ( v >> 16 ) == index ) { align = v & 0xFFFF ; return true ; } } return false ; } </s>

Return the minimum known alignment in bytes of the actual memory reference .


<s> static bool classof ( const MipsMCSymbolRefExpr * ) { return true ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> unsigned getMaxCallFrameSize ( ) const { return MaxCallFrameSize ; } </s>

Return the maximum size of a call frame that must be allocated for an outgoing function call .


<s> static void msp430_compute_frame_info ( void ) { int i ; cfun -> machine -> computed = 1 ; cfun -> machine -> framesize_regs = 0 ; cfun -> machine -> framesize_locals = get_frame_size ( ) ; cfun -> machine -> framesize_outgoing = crtl -> outgoing_args_size ; for ( i = 0 ; i < ARG_POINTER_REGNUM ; i ++ ) if ( msp430_preserve_reg_p ( i ) ) { cfun -> machine -> need_to_save [ i ] = 1 ; cfun -> machine -> framesize_regs += ( TARGET_LARGE ? 4 : 2 ) ; } else cfun -> machine -> need_to_save [ i ] = 0 ; if ( ( cfun -> machine -> framesize_locals + cfun -> machine -> framesize_outgoing ) & 1 ) cfun -> machine -> framesize_locals ++ ; cfun -> machine -> framesize = ( cfun -> machine -> framesize_regs + cfun -> machine -> framesize_locals + cfun -> machine -> framesize_outgoing ) ; } </s>

Compute all the frame-related fields in our machine_function structure .


<s> WebAssemblySubtarget :: WebAssemblySubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : WebAssemblyGenSubtargetInfo ( TT , CPU , FS ) , HasSIMD128 ( false ) , HasAtomics ( false ) , HasNontrappingFPToInt ( false ) , CPUString ( CPU ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS ) ) , TSInfo ( ) , TLInfo ( TM , * this ) { } </s>

This constructor initializes the data members to match that of the specified triple .

WebAssembly WebAssembly WebAssembly WebAssembly


"calling %qD with attribute sseregparm without "

"calling %qT with attribute sseregparm without "

Return 1 or 2 , if we can pass up to SSE_REGPARM_MAX SFmode ( 1 ) and DFmode ( 2 ) arguments in SSE registers for a function with the indicated TYPE and DECL . DECL may be NULL when calling function indirectly or considering a libcall . Otherwise return 0 .


<s> static void rs6000_emit_nmsub ( rtx dst , rtx m1 , rtx m2 , rtx a ) { machine_mode mode = GET_MODE ( dst ) ; rtx r ; gcc_assert ( optab_handler ( fma_optab , mode ) != CODE_FOR_nothing ) ; r = gen_rtx_NEG ( mode , a ) ; r = gen_rtx_FMA ( mode , m1 , m2 , r ) ; r = gen_rtx_NEG ( mode , r ) ; emit_insn ( gen_rtx_SET ( dst , r ) ) ; } </s>

Generate a FNMSUB instruction : dst = -fma ( m1 , m2 , -a ) .


<s> static rtx sparc_legitimize_pic_address ( rtx orig , rtx reg ) { bool gotdata_op = false ; if ( GET_CODE ( orig ) == SYMBOL_REF || ( GET_CODE ( orig ) == LABEL_REF && ! can_use_mov_pic_label_ref ( orig ) ) ) { rtx pic_ref , address ; rtx_insn * insn ; if ( reg == 0 ) { gcc_assert ( can_create_pseudo_p ( ) ) ; reg = gen_reg_rtx ( Pmode ) ; } if ( flag_pic == 2 ) { rtx temp_reg = ( ! can_create_pseudo_p ( ) ? reg : gen_reg_rtx ( Pmode ) ) ; if ( TARGET_ARCH64 ) { emit_insn ( gen_movdi_high_pic ( temp_reg , orig ) ) ; emit_insn ( gen_movdi_lo_sum_pic ( temp_reg , temp_reg , orig ) ) ; } else { emit_insn ( gen_movsi_high_pic ( temp_reg , orig ) ) ; emit_insn ( gen_movsi_lo_sum_pic ( temp_reg , temp_reg , orig ) ) ; } address = temp_reg ; gotdata_op = true ; } else address = orig ; crtl -> uses_pic_offset_table = 1 ; if ( gotdata_op ) { if ( TARGET_ARCH64 ) insn = emit_insn ( gen_movdi_pic_gotdata_op ( reg , pic_offset_table_rtx , address , orig ) ) ; else insn = emit_insn ( gen_movsi_pic_gotdata_op ( reg , pic_offset_table_rtx , address , orig ) ) ; } else { pic_ref = gen_const_mem ( Pmode , gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , address ) ) ; insn = emit_move_insn ( reg , pic_ref ) ; } set_unique_reg_note ( insn , REG_EQUAL , orig ) ; return reg ; } else if ( GET_CODE ( orig ) == CONST ) { rtx base , offset ; if ( GET_CODE ( XEXP ( orig , 0 ) ) == PLUS && XEXP ( XEXP ( orig , 0 ) , 0 ) == pic_offset_table_rtx ) return orig ; if ( reg == 0 ) { gcc_assert ( can_create_pseudo_p ( ) ) ; reg = gen_reg_rtx ( Pmode ) ; } gcc_assert ( GET_CODE ( XEXP ( orig , 0 ) ) == PLUS ) ; base = sparc_legitimize_pic_address ( XEXP ( XEXP ( orig , 0 ) , 0 ) , reg ) ; offset = sparc_legitimize_pic_address ( XEXP ( XEXP ( orig , 0 ) , 1 ) , base == reg ? NULL_RTX : reg ) ; if ( GET_CODE ( offset ) == CONST_INT ) { if ( SMALL_INT ( offset ) ) return plus_constant ( Pmode , base , INTVAL ( offset ) ) ; else if ( can_create_pseudo_p ( ) ) offset = force_reg ( Pmode , offset ) ; else gcc_unreachable ( ) ; } return gen_rtx_PLUS ( Pmode , base , offset ) ; } else if ( GET_CODE ( orig ) == LABEL_REF ) crtl -> uses_pic_offset_table = 1 ; return orig ; } </s>

Legitimize PIC addresses . If the address is already position-independent , we return ORIG . Newly generated position-independent addresses go into a reg . This is REG if nonzero , otherwise we allocate register ( s ) as necessary .


<s> bool isToken ( ) const { return Kind == k_Token ; } </s>


<s> int getIntImmCost ( Intrinsic :: ID IID , unsigned Idx , const APInt & Imm , Type * Ty ) { return getIntImmCost ( Imm , Ty ) ; } </s>


<s> static bool rs6000_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { if ( RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p ) { static int recurse = 0 ; if ( DEFAULT_ABI == ABI_V4 && ( TARGET_RELOCATABLE || flag_pic > 1 ) && in_section != toc_section && ! recurse && ! CONST_SCALAR_INT_P ( x ) && CONSTANT_P ( x ) ) { char buf [ 256 ] ; recurse = 1 ; ASM_GENERATE_INTERNAL_LABEL ( buf , "LCP" , fixuplabelno ) ; fixuplabelno ++ ; ASM_OUTPUT_LABEL ( asm_out_file , buf ) ; fprintf ( asm_out_file , "\t.long\t(" ) ; output_addr_const ( asm_out_file , x ) ; fprintf ( asm_out_file , ")@fixup\n" ) ; fprintf ( asm_out_file , "\t.section\t\".fixup\",\"aw\"\n" ) ; ASM_OUTPUT_ALIGN ( asm_out_file , 2 ) ; fprintf ( asm_out_file , "\t.long\t" ) ; assemble_name ( asm_out_file , buf ) ; fprintf ( asm_out_file , "\n\t.previous\n" ) ; recurse = 0 ; return true ; } else if ( SYMBOL_REF_P ( x ) && XSTR ( x , 0 ) [ 0 ] == '.' && DEFAULT_ABI == ABI_AIX ) { const char * name = XSTR ( x , 0 ) ; while ( * name == '.' ) name ++ ; fprintf ( asm_out_file , "\t.long\t%s\n" , name ) ; return true ; } } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . The powerpc version has to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP is defined . It also needs to handle DI-mode objects on 64-bit targets .


<s> static void lm32_block_move_inline ( rtx dest , rtx src , HOST_WIDE_INT length , HOST_WIDE_INT alignment ) { HOST_WIDE_INT offset , delta ; unsigned HOST_WIDE_INT bits ; int i ; machine_mode mode ; rtx * regs ; switch ( alignment ) { case 1 : bits = 8 ; break ; case 2 : bits = 16 ; break ; default : bits = 32 ; break ; } mode = mode_for_size ( bits , MODE_INT , 0 ) ; delta = bits / BITS_PER_UNIT ; regs = XALLOCAVEC ( rtx , length / delta ) ; for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) { regs [ i ] = gen_reg_rtx ( mode ) ; emit_move_insn ( regs [ i ] , adjust_address ( src , mode , offset ) ) ; } for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) emit_move_insn ( adjust_address ( dest , mode , offset ) , regs [ i ] ) ; if ( offset < length ) { src = adjust_address ( src , BLKmode , offset ) ; dest = adjust_address ( dest , BLKmode , offset ) ; move_by_pieces ( dest , src , length - offset , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) , 0 ) ; } } </s>

Emit straight-line code to move LENGTH bytes from SRC to DEST . Assume that the areas do not overlap .


<s> bool invalid_e500_subreg ( rtx op , machine_mode mode ) { if ( TARGET_E500_DOUBLE ) { if ( GET_CODE ( op ) == SUBREG && ( mode == SImode || mode == DImode || mode == TImode || mode == DDmode || mode == TDmode || mode == PTImode ) && REG_P ( SUBREG_REG ( op ) ) && ( GET_MODE ( SUBREG_REG ( op ) ) == DFmode || GET_MODE ( SUBREG_REG ( op ) ) == TFmode || GET_MODE ( SUBREG_REG ( op ) ) == IFmode || GET_MODE ( SUBREG_REG ( op ) ) == KFmode ) ) return true ; if ( GET_CODE ( op ) == SUBREG && ( mode == DFmode || mode == TFmode || mode == IFmode || mode == KFmode ) && REG_P ( SUBREG_REG ( op ) ) && ( GET_MODE ( SUBREG_REG ( op ) ) == DImode || GET_MODE ( SUBREG_REG ( op ) ) == TImode || GET_MODE ( SUBREG_REG ( op ) ) == PTImode || GET_MODE ( SUBREG_REG ( op ) ) == DDmode || GET_MODE ( SUBREG_REG ( op ) ) == TDmode ) ) return true ; } if ( TARGET_SPE && GET_CODE ( op ) == SUBREG && mode == SImode && REG_P ( SUBREG_REG ( op ) ) && SPE_VECTOR_MODE ( GET_MODE ( SUBREG_REG ( op ) ) ) ) return true ; return false ; } </s>

Return TRUE if OP is an invalid SUBREG operation on the e500 .


<s> static rtx force_offsettable ( rtx addr , HOST_WIDE_INT size , bool reuse ) { rtx base = addr ; rtx offs = const0_rtx ; if ( GET_CODE ( base ) == PLUS ) { offs = XEXP ( base , 1 ) ; base = XEXP ( base , 0 ) ; } if ( ! REG_P ( base ) || ( REGNO ( base ) != STACK_POINTER_REGNUM && REGNO_PTR_FRAME_P ( REGNO ( base ) ) ) || ! CONST_INT_P ( offs ) || ! SMALL_INT ( INTVAL ( offs ) ) || ! SMALL_INT ( INTVAL ( offs ) + size ) ) { if ( reuse ) emit_insn ( gen_add2_insn ( addr , offs ) ) ; else addr = copy_to_mode_reg ( Pmode , addr ) ; } return addr ; } </s>

Helper function of arc_expand_movmem . ADDR points to a chunk of memory . Emit code and return an potentially modified address such that offsets up to SIZE are can be added to yield a legitimate address . if REUSE is set , ADDR is a register that may be modified .


<s> bool HexagonAsmParser :: isLabel ( AsmToken & Token ) { MCAsmLexer & Lexer = getLexer ( ) ; AsmToken const & Second = Lexer . getTok ( ) ; AsmToken Third = Lexer . peekTok ( ) ; StringRef String = Token . getString ( ) ; if ( Token . is ( AsmToken :: TokenKind :: LCurly ) || Token . is ( AsmToken :: TokenKind :: RCurly ) ) return false ; if ( ! Token . is ( AsmToken :: TokenKind :: Identifier ) ) return true ; if ( ! matchRegister ( String . lower ( ) ) ) return true ; ( void ) Second ; assert ( Second . is ( AsmToken :: Colon ) ) ; StringRef Raw ( String . data ( ) , Third . getString ( ) . data ( ) - String . data ( ) + Third . getString ( ) . size ( ) ) ; std :: string Collapsed = Raw ; Collapsed . erase ( remove_if ( Collapsed , isspace ) , Collapsed . end ( ) ) ; StringRef Whole = Collapsed ; std :: pair < StringRef , StringRef > DotSplit = Whole . split ( '.' ) ; if ( ! matchRegister ( DotSplit . first . lower ( ) ) ) return true ; return false ; } </s>

Returns true if the MachineInstr represents a label .


Return an array that contains the direct target flag values and their names .


<s>
SDValue
BlackfinTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
SmallVector
<
CCValAssign
,
16
>
ArgLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
ArgLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AllocateStack
(
12
,
4
)
;
CCInfo
.
AnalyzeFormalArguments
(
Ins
,
CC_Blackfin
)
;
for
(
unsigned
i
=
0
,
e
=
ArgLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
ArgLocs
[
i
]
;
if
(
VA
.
isRegLoc
(
)
)
{
EVT
RegVT
=
VA
.
getLocVT
(
)
;
TargetRegisterClass
*
RC
=
VA
.
getLocReg
(
)
==
BF
::
P0
BF
::
PRegisterClass
:
BF
::
DRegisterClass
;
assert
(
RC
->
contains
(
VA
.
getLocReg
(
)
)
&&
"Unexpected regclass in CCState"
)
;
assert
(
RC
->
hasType
(
RegVT
)
&&
"Unexpected regclass in CCState"
)
;
unsigned
Reg
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
RC
)
;
MF
.
getRegInfo
(
)
.
addLiveIn
(
VA
.
getLocReg
(
)
,
Reg
)
;
SDValue
ArgValue
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
Reg
,
RegVT
)
;
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
SExt
)
ArgValue
=
DAG
.
getNode
(
ISD
::
AssertSext
,
dl
,
RegVT
,
ArgValue
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
else
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExt
)
ArgValue
=
DAG
.
getNode
(
ISD
::
AssertZext
,
dl
,
RegVT
,
ArgValue
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
if
(
VA
.
getLocInfo
(
)
!=
CCValAssign
::
Full
)
ArgValue
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
ArgValue
)
;
InVals
.
push_back
(
ArgValue
)
;
}
else
{
assert
(
VA
.
isMemLoc
(
)
&&
"CCValAssign must be RegLoc or MemLoc"
)
;
unsigned
ObjSize
=
VA
.
getLocVT
(
)
.
getStoreSize
(
)
;
int
FI
=
MFI
->
CreateFixedObject
(
ObjSize
,
VA
.
getLocMemOffset
(
)
,
true
)
;
SDValue
FIN
=
DAG
.
getFrameIndex
(
FI
,
MVT
::
i32
)
;
InVals
.
push_back
(
DAG
.
getLoad
(
VA
.
getValVT
(
)
,
dl
,
Chain
,
FIN
,
MachinePointerInfo
(
)
,
false
,
false
,
0
)
)
;
}
}
return
Chain
;
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> void GCNILPScheduler :: releasePending ( ) { for ( auto I = PendingQueue . begin ( ) , E = PendingQueue . end ( ) ; I != E ; ) { auto & C = * I ++ ; if ( C . SU -> getHeight ( ) <= CurCycle ) { PendingQueue . remove ( C ) ; AvailQueue . push_back ( C ) ; C . SU -> NodeQueueId = CurQueueId ++ ; } } } </s>

Release pending ready nodes in to the available queue .


<s> static machine_mode arc_preferred_simd_mode ( machine_mode mode ) { switch ( mode ) { case HImode : return TARGET_PLUS_QMACW ? V4HImode : V2HImode ; case SImode : return V2SImode ; default : return word_mode ; } } </s>

Implements target hook TARGET_VECTORIZE_PREFERRED_SIMD_MODE .


<s> static bool pru_arg_in_reg_bysize ( size_t sz ) { return sz == 1 || sz == 2 || sz == 3 || sz == 4 || sz == 8 ; } </s>


<s> bool mips_cannot_change_mode_class ( machine_mode from , machine_mode to , enum reg_class rclass ) { if ( GET_MODE_SIZE ( from ) == 8 && GET_MODE_SIZE ( to ) == 8 && INTEGRAL_MODE_P ( from ) && INTEGRAL_MODE_P ( to ) ) return false ; return reg_classes_intersect_p ( FP_REGS , rclass ) ; } </s>


<s> static bool pa_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { if ( size == UNITS_PER_WORD && aligned_p && function_label_operand ( x , VOIDmode ) ) { fputs ( size == 8 ? "\t.dword\tP%" : "\t.word\tP%" , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; fputc ( '\n' , asm_out_file ) ; return true ; } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . This code handles aligned SI and DI integers specially , since function references must be preceded by P % .


<s> unsigned BlackfinRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; return TFI -> hasFP ( MF ) ? BF :: FP : BF :: SP ; } </s>


<s> bool enableMachineSchedDefaultSched ( ) const override { return true ; } </s>

True if the machine scheduler should disable the TLI preference for preRA scheduling with the source level scheduler .


<s> void loongarch_init_builtins ( void ) { const struct loongarch_builtin_description * d ; unsigned int i ; tree type ; for ( i = 0 ; i < ARRAY_SIZE ( loongarch_builtins ) ; i ++ ) { d = & loongarch_builtins [ i ] ; if ( d -> avail ( ) ) { type = loongarch_build_function_type ( d -> function_type ) ; loongarch_builtin_decls [ i ] = add_builtin_function ( d -> name , type , i , BUILT_IN_MD , NULL , NULL ) ; loongarch_get_builtin_decl_index [ d -> icode ] = i ; } } } </s>


<s> static rtx ix86_function_value ( const_tree valtype , const_tree fntype_or_decl , bool ) { machine_mode mode , orig_mode ; orig_mode = TYPE_MODE ( valtype ) ; mode = type_natural_mode ( valtype , NULL , true ) ; return ix86_function_value_1 ( valtype , fntype_or_decl , orig_mode , mode ) ; } </s>

Define how to find the value returned by a function . VALTYPE is the data type of the value ( as a tree ) . If the precise function being called is known , FUNC is its FUNCTION_DECL ; otherwise , FUNC is 0 .


<s> static void free_state_stack ( struct unw_reg_state * rs ) { struct unw_reg_state * p , * next ; for ( p = rs -> next ; p != NULL ; p = next ) { next = p -> next ; free_reg_state ( p ) ; } rs -> next = NULL ; } </s>

Free all stacked register states ( but not RS itself ) .


<s> void pop_back ( ) { rbegin ( ) -> second . pop_back ( ) ; if ( rbegin ( ) -> second . empty ( ) ) erase ( rbegin ( ) -> first ) ; } </s>

Pop one bit from the end of the vector .


<s> int X86FrameLowering :: mergeSPUpdates ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , bool doMergeWithPrevious ) const { if ( ( doMergeWithPrevious && MBBI == MBB . begin ( ) ) || ( ! doMergeWithPrevious && MBBI == MBB . end ( ) ) ) return 0 ; MachineBasicBlock :: iterator PI = doMergeWithPrevious ? std :: prev ( MBBI ) : MBBI ; PI = skipDebugInstructionsBackward ( PI , MBB . begin ( ) ) ; if ( doMergeWithPrevious && PI != MBB . begin ( ) && PI -> isCFIInstruction ( ) ) PI = std :: prev ( PI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = 0 ; if ( ( Opc == X86 :: ADD64ri32 || Opc == X86 :: ADD64ri8 || Opc == X86 :: ADD32ri || Opc == X86 :: ADD32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { assert ( PI -> getOperand ( 1 ) . getReg ( ) == StackPtr ) ; Offset = PI -> getOperand ( 2 ) . getImm ( ) ; } else if ( ( Opc == X86 :: LEA32r || Opc == X86 :: LEA64_32r ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr && PI -> getOperand ( 1 ) . getReg ( ) == StackPtr && PI -> getOperand ( 2 ) . getImm ( ) == 1 && PI -> getOperand ( 3 ) . getReg ( ) == X86 :: NoRegister && PI -> getOperand ( 5 ) . getReg ( ) == X86 :: NoRegister ) { Offset = PI -> getOperand ( 4 ) . getImm ( ) ; } else if ( ( Opc == X86 :: SUB64ri32 || Opc == X86 :: SUB64ri8 || Opc == X86 :: SUB32ri || Opc == X86 :: SUB32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { assert ( PI -> getOperand ( 1 ) . getReg ( ) == StackPtr ) ; Offset = - PI -> getOperand ( 2 ) . getImm ( ) ; } else return 0 ; PI = MBB . erase ( PI ) ; if ( PI != MBB . end ( ) && PI -> isCFIInstruction ( ) ) { auto CIs = MBB . getParent ( ) -> getFrameInstructions ( ) ; MCCFIInstruction CI = CIs [ PI -> getOperand ( 0 ) . getCFIIndex ( ) ] ; if ( CI . getOperation ( ) == MCCFIInstruction :: OpDefCfaOffset ) PI = MBB . erase ( PI ) ; } if ( ! doMergeWithPrevious ) MBBI = skipDebugInstructionsForward ( PI , MBB . end ( ) ) ; return Offset ; } </s>

Check the instruction before/after the passed instruction .


<s> bool HexagonTargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( Kind . isBSS ( ) || Kind . isDataNoRel ( ) || Kind . isCommon ( ) ) { Type * Ty = GV -> getType ( ) -> getElementType ( ) ; return IsInSmallSection ( TM . getTargetData ( ) -> getTypeAllocSize ( Ty ) ) ; } return false ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> static void xstormy16_asm_out_destructor ( rtx symbol , int priority ) { const char * section = ".dtors" ; char buf [ 16 ] ; if ( priority != DEFAULT_INIT_PRIORITY ) { sprintf ( buf , ".dtors.%.5u" , MAX_INIT_PRIORITY - priority ) ; section = buf ; } switch_to_section ( get_section ( section , 0 , NULL ) ) ; assemble_align ( POINTER_SIZE ) ; assemble_integer ( symbol , POINTER_SIZE / BITS_PER_UNIT , POINTER_SIZE , 1 ) ; } </s>

Output constructors and destructors . Just like default_named_section_asm_out_ * but do n't set the sections writable .


<s> static section * avr_asm_select_section ( tree decl , int reloc , unsigned HOST_WIDE_INT align ) { section * sect = default_elf_select_section ( decl , reloc , align ) ; if ( decl && DECL_P ( decl ) && avr_progmem_p ( decl , DECL_ATTRIBUTES ( decl ) ) ) { addr_space_t as = TYPE_ADDR_SPACE ( TREE_TYPE ( decl ) ) ; if ( ADDR_SPACE_GENERIC_P ( as ) ) as = ADDR_SPACE_FLASH ; if ( sect -> common . flags & SECTION_NAMED ) { const char * name = sect -> named . name ; const char * old_prefix = ".rodata" ; const char * new_prefix = avr_addrspace [ as ] . section_name ; if ( startswith ( name , old_prefix ) ) { const char * sname = ACONCAT ( ( new_prefix , name + strlen ( old_prefix ) , NULL ) ) ; return get_section ( sname , sect -> common . flags & ~ SECTION_DECLARED , sect -> named . decl ) ; } } if ( ! progmem_section [ as ] ) { progmem_section [ as ] = get_unnamed_section ( 0 , avr_output_progmem_section_asm_op , avr_addrspace [ as ] . section_name ) ; } return progmem_section [ as ] ; } return sect ; } </s>


"Function has local memory argument.  Promoting to "

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void HexagonTTIImpl :: getPeelingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: PeelingPreferences & PP ) { BaseT :: getPeelingPreferences ( L , SE , PP ) ; if ( L && L -> isInnermost ( ) && canPeel ( L ) && SE . getSmallConstantTripCount ( L ) == 0 && SE . getSmallConstantMaxTripCount ( L ) > 0 && SE . getSmallConstantMaxTripCount ( L ) <= 5 ) { PP . PeelCount = 2 ; } } </s>

Get target-customized preferences for the generic loop peeling transformation .


<s> const MCPhysReg * SIRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { CallingConv :: ID CC = MF -> getFunction ( ) . getCallingConv ( ) ; switch ( CC ) { case CallingConv :: C : case CallingConv :: Fast : case CallingConv :: Cold : return MF -> getSubtarget < GCNSubtarget > ( ) . hasGFX90AInsts ( ) ? CSR_AMDGPU_HighRegs_With_AGPRs_SaveList : CSR_AMDGPU_HighRegs_SaveList ; case CallingConv :: AMDGPU_Gfx : return MF -> getSubtarget < GCNSubtarget > ( ) . hasGFX90AInsts ( ) ? CSR_AMDGPU_SI_Gfx_With_AGPRs_SaveList : CSR_AMDGPU_SI_Gfx_SaveList ; default : { static const MCPhysReg NoCalleeSavedReg = AMDGPU :: NoRegister ; return & NoCalleeSavedReg ; } } } </s>

AMDGPU SI AMDGPU AMDGPU AMDGPU SI SI AMDGPU::NoRegister


<s> void microblaze_expand_conditional_branch ( machine_mode mode , rtx operands [ ] ) { enum rtx_code code = GET_CODE ( operands [ 0 ] ) ; rtx cmp_op0 = operands [ 1 ] ; rtx cmp_op1 = operands [ 2 ] ; rtx label1 = operands [ 3 ] ; rtx comp_reg = gen_reg_rtx ( SImode ) ; rtx condition ; gcc_assert ( ( GET_CODE ( cmp_op0 ) == REG ) || ( GET_CODE ( cmp_op0 ) == SUBREG ) ) ; if ( cmp_op1 == const0_rtx ) { comp_reg = cmp_op0 ; condition = gen_rtx_fmt_ee ( signed_condition ( code ) , SImode , comp_reg , const0_rtx ) ; emit_jump_insn ( gen_condjump ( condition , label1 ) ) ; } else if ( code == EQ || code == NE ) { emit_insn ( gen_xorsi3 ( comp_reg , cmp_op0 , cmp_op1 ) ) ; condition = gen_rtx_fmt_ee ( signed_condition ( code ) , SImode , comp_reg , const0_rtx ) ; emit_jump_insn ( gen_condjump ( condition , label1 ) ) ; } else { cmp_op1 = force_reg ( mode , cmp_op1 ) ; condition = gen_rtx_fmt_ee ( code , mode , cmp_op0 , cmp_op1 ) ; emit_jump_insn ( gen_branch_compare ( condition , cmp_op0 , cmp_op1 , label1 ) ) ; } } </s>

Generate conditional branch -- first , generate test condition , second , generate correct branch instruction .


"Instructions with multiple result values not implemented"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void Cpu0MCCodeEmitter :: EmitInstruction ( uint64_t Val , unsigned Size , raw_ostream & OS ) const { for ( unsigned i = 0 ; i < Size ; ++ i ) { unsigned Shift = IsLittleEndian ? i * 8 : ( Size - 1 - i ) * 8 ; EmitByte ( ( Val >> Shift ) & 0xff , OS ) ; } } </s>


<s> bool loongarch_legitimize_move ( machine_mode mode , rtx dest , rtx src ) { if ( ! register_operand ( dest , mode ) && ! reg_or_0_operand ( src , mode ) ) { loongarch_emit_move ( dest , force_reg ( mode , src ) ) ; return true ; } if ( ! register_operand ( dest , mode ) && ! register_operand ( src , mode ) && ! const_0_operand ( src , mode ) ) { loongarch_emit_move ( dest , force_reg ( mode , src ) ) ; return true ; } if ( CONSTANT_P ( src ) && ! move_operand ( src , mode ) ) { loongarch_legitimize_const_move ( mode , dest , src ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , copy_rtx ( src ) ) ; return true ; } return false ; } </s>

If ( set DEST SRC ) is not a valid move instruction , emit an equivalent sequence that is valid .


<s> static bool addr_generation_dependency_p ( rtx dep_rtx , rtx_insn * insn ) { rtx target , pat ; if ( NONJUMP_INSN_P ( dep_rtx ) ) dep_rtx = PATTERN ( dep_rtx ) ; if ( GET_CODE ( dep_rtx ) == SET ) { target = SET_DEST ( dep_rtx ) ; if ( GET_CODE ( target ) == STRICT_LOW_PART ) target = XEXP ( target , 0 ) ; while ( GET_CODE ( target ) == SUBREG ) target = SUBREG_REG ( target ) ; if ( GET_CODE ( target ) == REG ) { int regno = REGNO ( target ) ; if ( s390_safe_attr_type ( insn ) == TYPE_LA ) { pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == PARALLEL ) { gcc_assert ( XVECLEN ( pat , 0 ) == 2 ) ; pat = XVECEXP ( pat , 0 , 0 ) ; } gcc_assert ( GET_CODE ( pat ) == SET ) ; return refers_to_regno_p ( regno , SET_SRC ( pat ) ) ; } else if ( get_attr_atype ( insn ) == ATYPE_AGEN ) return reg_used_in_mem_p ( regno , PATTERN ( insn ) ) ; } } return false ; } </s>

Returns true if expression DEP_RTX sets an address register used by instruction INSN to address memory .


<s>
MipsSubtarget
::
MipsSubtarget
(
const
std
::
string
&
TT
,
const
std
::
string
&
CPU
,
const
std
::
string
&
FS
,
bool
little
)
:
MipsGenSubtargetInfo
(
TT
,
CPU
,
FS
)
,
MipsArchVersion
(
Mips32
)
,
MipsABI
(
UnknownABI
)
,
IsLittle
(
little
)
,
IsSingleFloat
(
false
)
,
IsFP64bit
(
false
)
,
IsGP64bit
(
false
)
,
HasVFPU
(
false
)
,
IsLinux
(
true
)
,
HasSEInReg
(
false
)
,
HasCondMov
(
false
)
,
HasMulDivAdd
(
false
)
,
HasMinMax
(
false
)
,
HasSwap
(
false
)
,
HasBitCount
(
false
)
,
InMips16Mode
(
false
)
{
std
::
string
CPUName
=
CPU
;
if
(
CPUName
.
empty
(
)
)
CPUName
=
"mips32"
;
ParseSubtargetFeatures
(
CPUName
,
FS
)
;
InstrItins
=
getInstrItineraryForCPU
(
CPUName
)
;
if
(
MipsABI
==
UnknownABI
)
MipsABI
=
hasMips64
(
)
N64
:
O32
;
assert
(
(
(
!
hasMips64
(
)
&&
(
isABI_O32
(
)
||
isABI_EABI
(
)
)
)
||
(
hasMips64
(
)
&&
(
isABI_N32
(
)
||
isABI_N64
(
)
)
)
)
&&
"Invalid  Arch & ABI pair."
)
;
if
(
TT
.
find
(
"linux"
)
==
std
::
string
::
npos
)
IsLinux
=
false
;
}
</s>

This constructor initializes the data members to match that of the specified triple .

Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
"mips32"
Mips
Mips
Mips
Mips
Mips
"Invalid  Arch & ABI pair."
"linux"


<s> static void alpha_sa_mask ( unsigned long * imaskP , unsigned long * fmaskP ) { unsigned long imask = 0 ; unsigned long fmask = 0 ; unsigned int i ; if ( cfun -> is_thunk ) { * imaskP = 0 ; * fmaskP = 0 ; return ; } if ( TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK ) imask |= ( 1UL << HARD_FRAME_POINTER_REGNUM ) ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( ! fixed_regs [ i ] && ! call_used_regs [ i ] && df_regs_ever_live_p ( i ) && i != REG_RA ) { if ( i < 32 ) imask |= ( 1UL << i ) ; else fmask |= ( 1UL << ( i - 32 ) ) ; } if ( crtl -> calls_eh_return ) { for ( i = 0 ; ; ++ i ) { unsigned regno = EH_RETURN_DATA_REGNO ( i ) ; if ( regno == INVALID_REGNUM ) break ; imask |= 1UL << regno ; } } if ( imask || fmask || alpha_ra_ever_killed ( ) ) imask |= ( 1UL << REG_RA ) ; * imaskP = imask ; * fmaskP = fmask ; } </s>

Compute register masks for saved registers .


"non-standard ABI extension with no compatibility guarantee"

Return a nonzero value to say to return the function value in memory , just as large structures are always returned . TYPE will be the data type of the value , and FNTYPE will be the type of the function doing the returning , or @ code { NULL } for libcalls . The AIX ABI for the RS/6000 specifies that all structures are returned in memory . The Darwin ABI does the same . The SVR4 ABI specifies that structures < = 8 bytes are returned in r3/r4 , but a draft put them in memory , and GCC used to implement the draft instead of the final standard . Therefore , aix_struct_return controls this instead of DEFAULT_ABI ; V.4 targets needing backward compatibility can change DRAFT_V4_STRUCT_RET to override the default , and -m switches get the final word . See rs6000_override_options for more details . The PPC32 SVR4 ABI uses IEEE double extended for long double , if 128-bit long double support is enabled . These values are returned in memory . int_size_in_bytes returns -1 for variable size objects , which go in memory always . The cast to unsigned makes -1 > 8 .


<s> bool X86CallFrameOptimization :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; MRI = & MF . getRegInfo ( ) ; if ( ! isLegal ( MF ) ) return false ; int FrameSetupOpcode = TII -> getCallFrameSetupOpcode ( ) ; bool Changed = false ; ContextMap CallSeqMap ; for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ++ I ) if ( I -> getOpcode ( ) == FrameSetupOpcode ) { CallContext & Context = CallSeqMap [ I ] ; collectCallInfo ( MF , * BB , I , Context ) ; } if ( ! isProfitable ( MF , CallSeqMap ) ) return false ; for ( auto CC : CallSeqMap ) if ( CC . second . UsePush ) Changed |= adjustCallSequence ( MF , CC . first , CC . second ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool arm_cannot_copy_insn_p ( rtx_insn * insn ) { if ( recog_memoized ( insn ) == CODE_FOR_tlscall ) return true ; subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , ALL ) { const_rtx x = * iter ; if ( GET_CODE ( x ) == UNSPEC && ( XINT ( x , 1 ) == UNSPEC_PIC_BASE || XINT ( x , 1 ) == UNSPEC_PIC_UNIFIED ) ) return true ; } return false ; } </s>

Must not copy any rtx that uses a pc-relative address .


<s> void MSP430InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool shouldBuildLookupTablesForConstant ( Constant * C ) const { if ( ST -> isROPI ( ) || ST -> isRWPI ( ) || ST -> isPIP ( ) ) return ! C -> needsRelocation ( ) ; return true ; } </s>

Return true if switches should be turned into lookup tables containing this constant value for the target .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < AAResultsWrapperPass > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> int ARMTTIImpl :: getIntrinsicInstrCost ( const IntrinsicCostAttributes & ICA , TTI :: TargetCostKind CostKind ) { if ( ST -> hasMVEIntegerOps ( ) && ICA . getID ( ) == Intrinsic :: get_active_lane_mask ) return 0 ; return BaseT :: getIntrinsicInstrCost ( ICA , CostKind ) ; } </s>


<s>
bool
PPCCTRLoopsVerify
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
if
(
!
MDT
->
isReachableFromEntry
(
&
MBB
)
)
continue
;
for
(
MachineBasicBlock
::
iterator
MII
=
MBB
.
getFirstTerminator
(
)
,
MIIE
=
MBB
.
end
(
)
;
MII
!=
MIIE
;
++
MII
)
{
unsigned
Opc
=
MII
->
getOpcode
(
)
;
if
(
Opc
==
PPC
::
BDNZ8
||
Opc
==
PPC
::
BDNZ
||
Opc
==
PPC
::
BDZ8
||
Opc
==
PPC
::
BDZ
)
if
(
!
verifyCTRBranch
(
&
MBB
,
MII
)
)
llvm_unreachable
(
"Invalid PPC CTR loop!"
)
;
}
}
return
false
;
}
</s>

PowerPC
PPC
PPC::BDNZ8
PPC::BDNZ
PPC::BDZ8
PPC::BDZ
"Invalid PPC CTR loop!"


<s> bool enableInterleavedAccessVectorization ( ) { return true ; } </s>

Enable matching of interleaved access groups .


<s> static bool alpha_cannot_copy_insn_p ( rtx_insn * insn ) { if ( ! reload_completed || ! TARGET_EXPLICIT_RELOCS ) return false ; if ( recog_memoized ( insn ) >= 0 ) return get_attr_cannot_copy ( insn ) ; else return false ; } </s>

Indicate that INSN can not be duplicated . This is true for any insn that we 've marked with gpdisp relocs , since those have to stay in 1-1 correspondence with one another . Technically we could copy them if we could set up a mapping from one sequence number to another , across the set of insns to be duplicated . This seems overly complicated and error-prone since interblock motion from sched-ebb could move one of the pair of insns to a different block . Also can not allow jsr insns to be duplicated . If they throw exceptions , then they 'll be in a different block from their ldgp . Which could lead the bb reorder code to think that it would be ok to copy just the block containing the call and branch to the block containing the ldgp .


<s> bool pass_vsetvl :: can_refine_vsetvl_p ( const basic_block cfg_bb , const vector_insn_info & info ) const { if ( ! m_vector_manager -> all_same_ratio_p ( m_vector_manager -> vector_avin [ cfg_bb -> index ] ) ) return false ; if ( ! m_vector_manager -> all_same_avl_p ( cfg_bb , m_vector_manager -> vector_avin [ cfg_bb -> index ] ) ) return false ; size_t expr_id = bitmap_first_set_bit ( m_vector_manager -> vector_avin [ cfg_bb -> index ] ) ; if ( ! m_vector_manager -> vector_exprs [ expr_id ] -> same_vlmax_p ( info ) ) return false ; if ( ! m_vector_manager -> vector_exprs [ expr_id ] -> compatible_avl_p ( info ) ) return false ; edge e ; edge_iterator ei ; bool all_valid_p = true ; FOR_EACH_EDGE ( e , ei , cfg_bb -> preds ) { if ( bitmap_empty_p ( m_vector_manager -> vector_avout [ e -> src -> index ] ) ) { all_valid_p = false ; break ; } } if ( ! all_valid_p ) return false ; return true ; } </s>

Return true if VSETVL in the block can be refined as vsetvl zero , zero .


<s> bool s390_contiguous_bitmask_p ( unsigned HOST_WIDE_INT in , int size , int * pos , int * length ) { int tmp_pos = 0 ; int tmp_length = 0 ; int i ; unsigned HOST_WIDE_INT mask = 1ULL ; bool contiguous = false ; for ( i = 0 ; i < size ; mask <<= 1 , i ++ ) { if ( contiguous ) { if ( mask & in ) tmp_length ++ ; else break ; } else { if ( mask & in ) { contiguous = true ; tmp_length ++ ; } else tmp_pos ++ ; } } if ( ! tmp_length ) return false ; mask = ( - 1LL & ~ ( ( ( 1ULL << ( tmp_length + tmp_pos - 1 ) ) << 1 ) - 1 ) ) ; if ( mask & in ) return false ; if ( tmp_length + tmp_pos - 1 > size ) return false ; if ( length ) * length = tmp_length ; if ( pos ) * pos = tmp_pos ; return true ; } </s>

Return true if IN contains a contiguous bitfield in the lower SIZE bits and no other bits are set in IN . POS and LENGTH can be used to obtain the start position and the length of the bitfield . POS gives the position of the first bit of the bitfield counting from the lowest order bit starting with zero . In order to use this value for S/390 instructions this has to be converted to `` bits big endian '' style .


"Destination is smaller than source can't copy"


"rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n"

A C expressions returning the cost of moving data of MODE from a register to or from memory .


<s>
bool
ARCFrameLowering
::
restoreCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
MutableArrayRef
<
CalleeSavedInfo
>
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Restore callee saved registers: "
<<
MBB
.
getParent
(
)
->
getName
(
)
<<
"\n"
)
;
unsigned
Last
=
determineLastCalleeSave
(
CSI
)
;
if
(
UseSaveRestoreFunclet
&&
Last
>
ARC
::
R14
)
{
return
true
;
}
return
false
;
}
</s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .

ARC
ARC
"Restore callee saved registers: "
"\n"
ARC::R14


<s> static bool ix86_nopic_noplt_attribute_p ( rtx call_op ) { if ( flag_pic || ix86_cmodel == CM_LARGE || ! ( TARGET_64BIT || HAVE_AS_IX86_GOT32X ) || TARGET_MACHO || TARGET_SEH || TARGET_PECOFF || SYMBOL_REF_LOCAL_P ( call_op ) ) return false ; tree symbol_decl = SYMBOL_REF_DECL ( call_op ) ; if ( ! flag_plt || ( symbol_decl != NULL_TREE && lookup_attribute ( "noplt" , DECL_ATTRIBUTES ( symbol_decl ) ) ) ) return true ; return false ; } </s>

Return true if the function being called was marked with attribute `` noplt '' or using -fno-plt and we are compiling for non-PIC and x86_64 . We need to handle the non-PIC case in the backend because there is no easy interface for the front-end to force non-PLT calls to use the GOT . This is currently used only with 64-bit ELF targets to call the function marked `` noplt '' indirectly .


<s>
static
void
rs6000_sched_finish
(
FILE
*
dump
,
int
sched_verbose
)
{
int
n_groups
;
if
(
sched_verbose
)
fprintf
(
dump
,
"=== Finishing schedule.\n"
)
;
if
(
reload_completed
&&
rs6000_sched_groups
)
{
if
(
sel_sched_p
(
)
)
return
;
if
(
rs6000_sched_insert_nops
==
sched_finish_none
)
return
;
if
(
rs6000_sched_insert_nops
==
sched_finish_pad_groups
)
n_groups
=
pad_groups
(
dump
,
sched_verbose
,
current_sched_info
->
prev_head
,
current_sched_info
->
next_tail
)
;
else
n_groups
=
redefine_groups
(
dump
,
sched_verbose
,
current_sched_info
->
prev_head
,
current_sched_info
->
next_tail
)
;
if
(
sched_verbose
>=
6
)
{
fprintf
(
dump
,
"ngroups = %d\n"
,
n_groups
)
;
print_rtl
(
dump
,
current_sched_info
->
prev_head
)
;
fprintf
(
dump
,
"Done finish_sched\n"
)
;
}
}
}
</s>

The following function is called at the end of scheduling BB . After reload , it inserts nops at insn group bundling .

powerpcspe
"=== Finishing schedule.\n"
6
"ngroups = %d\n"
"Done finish_sched\n"


<s> bool PatmosFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s>
void
AArch64Operand
::
print
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
k_FPImm
:
OS
<<
"<fpimm "
<<
getFPImm
(
)
.
bitcastToAPInt
(
)
.
getZExtValue
(
)
;
if
(
!
getFPImmIsExact
(
)
)
OS
<<
" (inexact)"
;
OS
<<
">"
;
break
;
case
k_Barrier
:
{
StringRef
Name
=
getBarrierName
(
)
;
if
(
!
Name
.
empty
(
)
)
OS
<<
"<barrier "
<<
Name
<<
">"
;
else
OS
<<
"<barrier invalid #"
<<
getBarrier
(
)
<<
">"
;
break
;
}
case
k_Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
k_ShiftedImm
:
{
unsigned
Shift
=
getShiftedImmShift
(
)
;
OS
<<
"<shiftedimm "
;
OS
<<
*
getShiftedImmVal
(
)
;
OS
<<
", lsl #"
<<
AArch64_AM
::
getShiftValue
(
Shift
)
<<
">"
;
break
;
}
case
k_CondCode
:
OS
<<
"<condcode "
<<
getCondCode
(
)
<<
">"
;
break
;
case
k_VectorList
:
{
OS
<<
"<vectorlist "
;
unsigned
Reg
=
getVectorListStart
(
)
;
for
(
unsigned
i
=
0
,
e
=
getVectorListCount
(
)
;
i
!=
e
;
++
i
)
OS
<<
Reg
+
i
<<
" "
;
OS
<<
">"
;
break
;
}
case
k_VectorIndex
:
OS
<<
"<vectorindex "
<<
getVectorIndex
(
)
<<
">"
;
break
;
case
k_SysReg
:
OS
<<
"<sysreg: "
<<
getSysReg
(
)
<<
'>'
;
break
;
case
k_Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
case
k_SysCR
:
OS
<<
"c"
<<
getSysCR
(
)
;
break
;
case
k_Prefetch
:
{
StringRef
Name
=
getPrefetchName
(
)
;
if
(
!
Name
.
empty
(
)
)
OS
<<
"<prfop "
<<
Name
<<
">"
;
else
OS
<<
"<prfop invalid #"
<<
getPrefetch
(
)
<<
">"
;
break
;
}
case
k_PSBHint
:
OS
<<
getPSBHintName
(
)
;
break
;
case
k_BTIHint
:
OS
<<
getBTIHintName
(
)
;
break
;
case
k_MatrixRegister
:
OS
<<
"<matrix "
<<
getMatrixReg
(
)
<<
">"
;
break
;
case
k_MatrixTileList
:
{
OS
<<
"<matrixlist "
;
unsigned
RegMask
=
getMatrixTileListRegMask
(
)
;
unsigned
MaxBits
=
8
;
for
(
unsigned
I
=
MaxBits
;
I
>
0
;
I
)
OS
<<
(
(
RegMask
&
(
1
<<
(
I
1
)
)
)
>>
(
I
1
)
)
;
OS
<<
'>'
;
break
;
}
case
k_SVCR
:
{
OS
<<
getSVCR
(
)
;
break
;
}
case
k_Register
:
OS
<<
"<register "
<<
getReg
(
)
<<
">"
;
if
(
!
getShiftExtendAmount
(
)
&&
!
hasShiftExtendAmount
(
)
)
break
;
LLVM_FALLTHROUGH
;
case
k_ShiftExtend
:
OS
<<
"<"
<<
AArch64_AM
::
getShiftExtendName
(
getShiftExtendType
(
)
)
<<
" #"
<<
getShiftExtendAmount
(
)
;
if
(
!
hasShiftExtendAmount
(
)
)
OS
<<
"<imp>"
;
OS
<<
'>'
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

AArch64
AArch64
"<fpimm "
" (inexact)"
">"
"<barrier "
">"
"<barrier invalid #"
">"
"<shiftedimm "
", lsl #"
AArch64_AM::getShiftValue
">"
"<condcode "
">"
"<vectorlist "
0
" "
">"
"<vectorindex "
">"
"<sysreg: "
"'"
"'"
"c"
"<prfop "
">"
"<prfop invalid #"
">"
"<matrix "
">"
"<matrixlist "
8
0
1
1
1
"<register "
">"
"<"
AArch64_AM::getShiftExtendName
" #"
"<imp>"


<s> unsigned AVRMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; if ( MO . isFPImm ( ) ) return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( 32 ) . getLimitedValue ( ) ) ; assert ( MO . isExpr ( ) ) ; return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> bool HexagonOptimizeSZextends :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { if ( F . getAttributes ( ) . hasParamAttr ( Idx , Attribute :: SExt ) ) { if ( ! isa < PointerType > ( Arg . getType ( ) ) ) { for ( auto UI = Arg . use_begin ( ) ; UI != Arg . use_end ( ) ; ) { if ( isa < SExtInst > ( * UI ) ) { Instruction * Use = cast < Instruction > ( * UI ) ; SExtInst * SI = new SExtInst ( & Arg , Use -> getType ( ) ) ; assert ( EVT :: getEVT ( SI -> getType ( ) ) == ( EVT :: getEVT ( Use -> getType ( ) ) ) ) ; ++ UI ; Use -> replaceAllUsesWith ( SI ) ; Instruction * First = & F . getEntryBlock ( ) . front ( ) ; SI -> insertBefore ( First ) ; Use -> eraseFromParent ( ) ; } else { ++ UI ; } } } } ++ Idx ; } for ( auto & B : F ) { for ( auto & I : B ) { BinaryOperator * Ashr = dyn_cast < BinaryOperator > ( & I ) ; if ( ! ( Ashr && Ashr -> getOpcode ( ) == Instruction :: AShr ) ) continue ; Value * AshrOp1 = Ashr -> getOperand ( 1 ) ; ConstantInt * C = dyn_cast < ConstantInt > ( AshrOp1 ) ; if ( ! ( C && C -> getSExtValue ( ) == 16 ) ) continue ; Instruction * Shl = dyn_cast < Instruction > ( Ashr -> getOperand ( 0 ) ) ; if ( ! ( Shl && Shl -> getOpcode ( ) == Instruction :: Shl ) ) continue ; Value * Intr = Shl -> getOperand ( 0 ) ; Value * ShlOp1 = Shl -> getOperand ( 1 ) ; C = dyn_cast < ConstantInt > ( ShlOp1 ) ; if ( ! ( C && C -> getSExtValue ( ) == 16 ) ) continue ; if ( IntrinsicInst * I = dyn_cast < IntrinsicInst > ( Intr ) ) { if ( ! intrinsicAlreadySextended ( I -> getIntrinsicID ( ) ) ) continue ; for ( auto UI = Ashr -> user_begin ( ) , UE = Ashr -> user_end ( ) ; UI != UE ; ++ UI ) { const Use & TheUse = UI . getUse ( ) ; if ( Instruction * J = dyn_cast < Instruction > ( TheUse . getUser ( ) ) ) { J -> replaceUsesOfWith ( Ashr , I ) ; } } } } } return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void MipsELFStreamer :: EmitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , bool ) { MCELFStreamer :: EmitInstruction ( Inst , STI ) ; MCContext & Context = getContext ( ) ; const MCRegisterInfo * MCRegInfo = Context . getRegisterInfo ( ) ; for ( unsigned OpIndex = 0 ; OpIndex < Inst . getNumOperands ( ) ; ++ OpIndex ) { const MCOperand & Op = Inst . getOperand ( OpIndex ) ; if ( ! Op . isReg ( ) ) continue ; unsigned Reg = Op . getReg ( ) ; RegInfoRecord -> SetPhysRegUsed ( Reg , MCRegInfo ) ; } createPendingLabelRelocs ( ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


"%<gp_offset%> (%ld) or %<end_offset%> (%ld) is less than zero"

Save or restore instructions based on whether this is the prologue or epilogue . prologue is 1 for the prologue .


<s> MachineInstr * SystemZInstrInfo :: commuteInstructionImpl ( MachineInstr & MI , bool NewMI , unsigned OpIdx1 , unsigned OpIdx2 ) const { auto cloneIfNew = [ NewMI ] ( MachineInstr & MI ) -> MachineInstr & { if ( NewMI ) return * MI . getParent ( ) -> getParent ( ) -> CloneMachineInstr ( & MI ) ; return MI ; } ; switch ( MI . getOpcode ( ) ) { case SystemZ :: LOCRMux : case SystemZ :: LOCFHR : case SystemZ :: LOCR : case SystemZ :: LOCGR : { auto & WorkingMI = cloneIfNew ( MI ) ; unsigned CCValid = WorkingMI . getOperand ( 3 ) . getImm ( ) ; unsigned CCMask = WorkingMI . getOperand ( 4 ) . getImm ( ) ; WorkingMI . getOperand ( 4 ) . setImm ( CCMask ^ CCValid ) ; return TargetInstrInfo :: commuteInstructionImpl ( WorkingMI , false , OpIdx1 , OpIdx2 ) ; } default : return TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1 , OpIdx2 ) ; } } </s>

Commutes the operands in the given instruction by changing the operands order and/or changing the instruction 's opcode and/or the immediate value operand .

SystemZ SystemZ SystemZ::LOCRMux SystemZ::LOCFHR SystemZ::LOCR SystemZ::LOCGR 3 4 4


<s> unsigned getCacheLineSize ( ) const override { return 256 ; } </s>

Return the target cache line size in bytes .


<s> tree ix86_builtin_decl ( unsigned code , bool ) { if ( code >= IX86_BUILTIN_MAX ) return error_mark_node ; return ix86_builtins [ code ] ; } </s>


<s>
void
AVRDAGToDAGISel
::
Select
(
SDNode
*
N
)
{
DEBUG
(
errs
(
)
<<
"Selecting: "
;
N
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
N
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
N
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
N
->
setNodeId
(
1
)
;
return
;
}
if
(
trySelect
(
N
)
)
return
;
SelectCode
(
N
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> void MINA32FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX


<s> static void aarch64_pop_regs ( unsigned regno1 , unsigned regno2 , HOST_WIDE_INT adjustment , rtx * cfi_ops ) { machine_mode mode = aarch64_reg_save_mode ( regno1 ) ; rtx reg1 = gen_rtx_REG ( mode , regno1 ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg1 , * cfi_ops ) ; if ( regno2 == INVALID_REGNUM ) { rtx mem = plus_constant ( Pmode , stack_pointer_rtx , adjustment ) ; mem = gen_rtx_POST_MODIFY ( Pmode , stack_pointer_rtx , mem ) ; emit_move_insn ( reg1 , gen_frame_mem ( mode , mem ) ) ; } else { rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg2 , * cfi_ops ) ; emit_insn ( aarch64_gen_loadwb_pair ( mode , stack_pointer_rtx , reg1 , reg2 , adjustment ) ) ; } } </s>

Pop the two registers numbered REGNO1 , REGNO2 from the stack , adjusting it afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes into CFI_OPS .


<s> static bool rs6000_secondary_reload_direct_move ( enum rs6000_reg_type to_type , enum rs6000_reg_type from_type , machine_mode mode , secondary_reload_info * sri , bool altivec_p ) { bool ret = false ; enum insn_code icode = CODE_FOR_nothing ; int cost = 0 ; int size = GET_MODE_SIZE ( mode ) ; if ( TARGET_POWERPC64 && size == 16 ) { if ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) { cost = 3 ; icode = reg_addr [ mode ] . reload_vsx_gpr ; } else if ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) { cost = 3 ; icode = reg_addr [ mode ] . reload_gpr_vsx ; } } else if ( TARGET_POWERPC64 && mode == SFmode ) { if ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) { cost = 3 ; icode = reg_addr [ mode ] . reload_gpr_vsx ; } else if ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) { cost = 2 ; icode = reg_addr [ mode ] . reload_vsx_gpr ; } } else if ( ! TARGET_POWERPC64 && size == 8 ) { if ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE && ! altivec_p ) { cost = 3 ; icode = reg_addr [ mode ] . reload_fpr_gpr ; } } if ( icode != CODE_FOR_nothing ) { ret = true ; if ( sri ) { sri -> icode = icode ; sri -> extra_cost = cost ; } } return ret ; } </s>

Power8 helper function for rs6000_secondary_reload , handle all of the special direct moves that involve allocating an extra register , return the insn code of the helper function if there is such a function or CODE_FOR_nothing if not .


<s> const NVPTXInstrInfo * getInstrInfo ( ) const override { return getSubtargetImpl ( ) -> getInstrInfo ( ) ; } </s>


"Builtin function %s is only valid for the cell processor"

"Builtin function %s requires the -mvsx option"

"Builtin function %s requires the -mhtm option"

"Builtin function %s requires the -maltivec option"

"Builtin function %s requires the -mpaired option"

"Builtin function %s requires the -mspe option"

"Builtin function %s requires the -mhard-dfp and"

"Builtin function %s requires the -mhard-dfp option"

"Builtin function %s requires the -mpower8-vector option"

"Builtin function %s requires the -mcpu=power9 and"

"Builtin function %s requires the -mcpu=power9 option"

"Builtin function %s requires the -mhard-float and"

"Builtin function %s requires the -mhard-float option"

"Builtin function %s requires the -mfloat128 option"

"Builtin function %s is not supported with the current options"

Raise an error message for a builtin function that is called without the appropriate target options being set .


<s> static void mips16e_mask_registers ( unsigned int * mask_ptr , const unsigned char * regs , unsigned int size , unsigned int * num_regs_ptr ) { unsigned int i ; i = mips16e_find_first_register ( * mask_ptr , regs , size ) ; for ( i ++ ; i < size ; i ++ ) if ( ! BITSET_P ( * mask_ptr , regs [ i ] ) ) { * num_regs_ptr += 1 ; * mask_ptr |= 1 << regs [ i ] ; } } </s>

* MASK_PTR is a mask of general-purpose registers and * NUM_REGS_PTR is the number of set bits . If * MASK_PTR contains REGS [ X ] for some X in [ 0 , SIZE ) , adjust * MASK_PTR and * NUM_REGS_PTR so that the same is true for all indexes ( X , SIZE ) .


"function parameters cannot have __fp16 type"


<s> int MipsAsmParser :: tryParseRegister ( bool is64BitReg ) { const AsmToken & Tok = Parser . getTok ( ) ; int RegNum = - 1 ; if ( Tok . is ( AsmToken :: Identifier ) ) { std :: string lowerCase = Tok . getString ( ) . lower ( ) ; RegNum = matchRegisterName ( lowerCase , is64BitReg ) ; } else if ( Tok . is ( AsmToken :: Integer ) ) RegNum = matchRegisterByNumber ( static_cast < unsigned > ( Tok . getIntVal ( ) ) , is64BitReg ? Mips :: CPU64RegsRegClassID : Mips :: CPURegsRegClassID ) ; return RegNum ; } </s>

tryParseRegister - parse one register if possible


<s> const X86InstrInfo * getInstrInfo ( ) const { return getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) ; } </s>


<s> StringRef X86TargetLowering :: getStackProbeSymbolName ( MachineFunction & MF ) const { if ( MF . getFunction ( ) . hasFnAttribute ( "probe-stack" ) ) return MF . getFunction ( ) . getFnAttribute ( "probe-stack" ) . getValueAsString ( ) ; if ( ! Subtarget . isOSWindows ( ) || Subtarget . isTargetMachO ( ) || MF . getFunction ( ) . hasFnAttribute ( "no-stack-arg-probe" ) ) return "" ; if ( Subtarget . is64Bit ( ) ) return Subtarget . isTargetCygMing ( ) ? "___chkstk_ms" : "__chkstk" ; return Subtarget . isTargetCygMing ( ) ? "_alloca" : "_chkstk" ; } </s>

Returns the name of the symbol used to emit stack probes or the empty string if not applicable .


<s>
bool
R600ClauseMergePass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
*
MF
.
getFunction
(
)
)
)
return
false
;
TII
=
static_cast
<
const
R600InstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
for
(
MachineFunction
::
iterator
BB
=
MF
.
begin
(
)
,
BB_E
=
MF
.
end
(
)
;
BB
!=
BB_E
;
++
BB
)
{
MachineBasicBlock
&
MBB
=
*
BB
;
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
,
E
=
MBB
.
end
(
)
;
MachineBasicBlock
::
iterator
LatestCFAlu
=
E
;
while
(
I
!=
E
)
{
MachineInstr
*
MI
=
I
++
;
if
(
(
!
TII
->
canBeConsideredALU
(
MI
)
&&
!
isCFAlu
(
MI
)
)
||
TII
->
mustBeLastInClause
(
MI
->
getOpcode
(
)
)
)
LatestCFAlu
=
E
;
if
(
!
isCFAlu
(
MI
)
)
continue
;
cleanPotentialDisabledCFAlu
(
MI
)
;
if
(
LatestCFAlu
!=
E
&&
mergeIfPossible
(
LatestCFAlu
,
MI
)
)
{
MI
->
eraseFromParent
(
)
;
}
else
{
assert
(
MI
->
getOperand
(
8
)
.
getImm
(
)
&&
"CF ALU instruction disabled"
)
;
LatestCFAlu
=
MI
;
}
}
}
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> const LegalizerInfo * X86Subtarget :: getLegalizerInfo ( ) const { return Legalizer . get ( ) ; } </s>

Expose LegalizerInfo so the clients can re-use .


<s> static void ix86_emit_restore_reg_using_pop ( rtx reg ) { struct machine_function * m = cfun -> machine ; rtx_insn * insn = emit_insn ( gen_pop ( reg ) ) ; ix86_add_cfa_restore_note ( insn , reg , m -> fs . sp_offset ) ; m -> fs . sp_offset -= UNITS_PER_WORD ; if ( m -> fs . cfa_reg == crtl -> drap_reg && REGNO ( reg ) == REGNO ( crtl -> drap_reg ) ) { add_reg_note ( insn , REG_CFA_DEF_CFA , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; m -> fs . drap_valid = true ; return ; } if ( m -> fs . cfa_reg == stack_pointer_rtx ) { rtx x = plus_constant ( Pmode , stack_pointer_rtx , UNITS_PER_WORD ) ; x = gen_rtx_SET ( stack_pointer_rtx , x ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , x ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; m -> fs . cfa_offset -= UNITS_PER_WORD ; } if ( reg == hard_frame_pointer_rtx ) { m -> fs . fp_valid = false ; if ( m -> fs . cfa_reg == hard_frame_pointer_rtx ) { m -> fs . cfa_reg = stack_pointer_rtx ; m -> fs . cfa_offset -= UNITS_PER_WORD ; add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , stack_pointer_rtx , m -> fs . cfa_offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } } </s>

Emit code to restore REG using a POP insn .


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const PPCFrameLowering * PPCFI = static_cast < const PPCFrameLowering * > ( MF . getTarget ( ) . getFrameLowering ( ) ) ; Reserved . set ( PPC :: R0 ) ; Reserved . set ( PPC :: R1 ) ; Reserved . set ( PPC :: LR ) ; Reserved . set ( PPC :: LR8 ) ; Reserved . set ( PPC :: RM ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: R2 ) ; Reserved . set ( PPC :: R13 ) ; } if ( Subtarget . isPPC64 ( ) ) { Reserved . set ( PPC :: R13 ) ; Reserved . set ( PPC :: R31 ) ; Reserved . set ( PPC :: X0 ) ; Reserved . set ( PPC :: X1 ) ; Reserved . set ( PPC :: X13 ) ; Reserved . set ( PPC :: X31 ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: X2 ) ; } } if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: R31 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


"movhi hi(%s), r0, r6\n\tmovea lo(%s), r6, r6\n\tjmp r6"

Construct a JR instruction to a routine that will perform the equivalent of the RTL passed in as an argument . This RTL is a function epilogue that pops registers off the stack and possibly releases some extra stack space as well . The code has already verified that the RTL matches these requirements .


<s> static bool is_fusable_store ( rtx_insn * insn , rtx * str_mem ) { if ( is_store_insn ( insn , str_mem ) && get_attr_prefixed ( insn ) == PREFIXED_NO && get_attr_update ( insn ) == UPDATE_NO && get_attr_indexed ( insn ) == INDEXED_NO ) { if ( ! MEM_SIZE_KNOWN_P ( * str_mem ) ) return false ; machine_mode mode = GET_MODE ( * str_mem ) ; HOST_WIDE_INT size = MEM_SIZE ( * str_mem ) ; if ( INTEGRAL_MODE_P ( mode ) ) return ( size == 4 || size == 8 ) ; else if ( FLOAT_MODE_P ( mode ) ) return ( size == 8 ) ; } return false ; } </s>

Determine if INSN is a store to memory that can be fused with a similar adjacent store .


<s>
SDValue
NyuziTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BUILD_VECTOR
:
return
LowerBUILD_VECTOR
(
Op
,
DAG
)
;
case
ISD
::
VECTOR_SHUFFLE
:
return
LowerVECTOR_SHUFFLE
(
Op
,
DAG
)
;
case
ISD
::
INSERT_VECTOR_ELT
:
return
LowerINSERT_VECTOR_ELT
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_VECTOR_ELT
:
return
LowerEXTRACT_VECTOR_ELT
(
Op
,
DAG
)
;
case
ISD
::
SCALAR_TO_VECTOR
:
return
LowerSCALAR_TO_VECTOR
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
LowerSELECT
(
Op
,
DAG
)
;
case
ISD
::
VSELECT
:
return
LowerVSELECT
(
Op
,
DAG
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
FDIV
:
return
LowerFDIV
(
Op
,
DAG
)
;
case
ISD
::
FNEG
:
return
LowerFNEG
(
Op
,
DAG
)
;
case
ISD
::
FABS
:
return
LowerFABS
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
CTLZ_ZERO_UNDEF
:
return
LowerCTLZ_ZERO_UNDEF
(
Op
,
DAG
)
;
case
ISD
::
CTTZ_ZERO_UNDEF
:
return
LowerCTTZ_ZERO_UNDEF
(
Op
,
DAG
)
;
case
ISD
::
UINT_TO_FP
:
return
LowerUINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerSINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
SIGN_EXTEND
:
return
LowerSIGN_EXTEND
(
Op
,
DAG
)
;
case
ISD
::
ZERO_EXTEND
:
return
LowerZERO_EXTEND
(
Op
,
DAG
)
;
case
ISD
::
TRUNCATE
:
return
LowerTRUNCATE
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_XINT
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> static void c6x_mark_reg_written ( rtx reg , int cycles ) { unsigned regno = REGNO ( reg ) ; unsigned nregs = REG_NREGS ( reg ) ; while ( nregs -- > 0 ) ss . reg_set_in_cycle [ regno + nregs ] = cycles ; } </s>

Note that register REG is written in cycle CYCLES .


<s> void SystemZConstantPoolValue :: print ( raw_ostream & O ) const { O << GV << "@" << int ( Modifier ) ; } </s>

print - Print a debug representation of the operand to the given stream .


<s> bool HexagonHardwareLoops :: isDead ( const MachineInstr * MI , SmallVectorImpl < MachineInstr * > & DeadPhis ) const { for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( MRI -> use_nodbg_empty ( Reg ) ) continue ; typedef MachineRegisterInfo :: use_nodbg_iterator use_nodbg_iterator ; use_nodbg_iterator I = MRI -> use_nodbg_begin ( Reg ) ; use_nodbg_iterator End = MRI -> use_nodbg_end ( ) ; if ( std :: next ( I ) != End || ! I . getOperand ( ) . getParent ( ) -> isPHI ( ) ) return false ; MachineInstr * OnePhi = I . getOperand ( ) . getParent ( ) ; for ( unsigned j = 0 , f = OnePhi -> getNumOperands ( ) ; j != f ; ++ j ) { const MachineOperand & OPO = OnePhi -> getOperand ( j ) ; if ( ! OPO . isReg ( ) || ! OPO . isDef ( ) ) continue ; unsigned OPReg = OPO . getReg ( ) ; use_nodbg_iterator nextJ ; for ( use_nodbg_iterator J = MRI -> use_nodbg_begin ( OPReg ) ; J != End ; J = nextJ ) { nextJ = std :: next ( J ) ; MachineOperand & Use = J . getOperand ( ) ; MachineInstr * UseMI = Use . getParent ( ) ; if ( MI != UseMI ) return false ; } } DeadPhis . push_back ( OnePhi ) ; } return true ; } </s>

isDead - Returns true if this is a dead def kill slot .


<s> void HexagonPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; addPass ( createAtomicExpandPass ( ) ) ; if ( ! NoOpt ) { if ( EnableLoopPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableCommGEP ) addPass ( createHexagonCommonGEP ( ) ) ; if ( EnableGenExtract ) addPass ( createHexagonGenExtract ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> bool X86InstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF , bool OutlineFromLinkOnceODRs ) const { const Function * F = MF . getFunction ( ) ; if ( ! F -> hasFnAttribute ( Attribute :: NoRedZone ) ) return false ; if ( ! OutlineFromLinkOnceODRs && F -> hasLinkOnceODRLinkage ( ) ) return false ; return true ; } </s>

Return true if the function can safely be outlined from .


<s> bool LanaiRegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & ) const { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> static bool s390_fix_long_loop_prediction ( rtx_insn * insn ) { rtx set = single_set ( insn ) ; rtx code_label , label_ref ; rtx_insn * uncond_jump ; rtx_insn * cur_insn ; rtx tmp ; int distance ; if ( GET_CODE ( PATTERN ( insn ) ) == PARALLEL || ! set || SET_DEST ( set ) != pc_rtx || GET_CODE ( SET_SRC ( set ) ) != IF_THEN_ELSE ) return false ; if ( ANY_RETURN_P ( XEXP ( SET_SRC ( set ) , 1 ) ) && XEXP ( SET_SRC ( set ) , 2 ) == pc_rtx ) return false ; label_ref = ( GET_CODE ( XEXP ( SET_SRC ( set ) , 1 ) ) == LABEL_REF ? XEXP ( SET_SRC ( set ) , 1 ) : XEXP ( SET_SRC ( set ) , 2 ) ) ; gcc_assert ( GET_CODE ( label_ref ) == LABEL_REF ) ; code_label = XEXP ( label_ref , 0 ) ; if ( INSN_ADDRESSES ( INSN_UID ( code_label ) ) == - 1 || INSN_ADDRESSES ( INSN_UID ( insn ) ) == - 1 || ( INSN_ADDRESSES ( INSN_UID ( insn ) ) - INSN_ADDRESSES ( INSN_UID ( code_label ) ) < PREDICT_DISTANCE ) ) return false ; for ( distance = 0 , cur_insn = PREV_INSN ( insn ) ; distance < PREDICT_DISTANCE - 6 ; distance += get_attr_length ( cur_insn ) , cur_insn = PREV_INSN ( cur_insn ) ) if ( ! cur_insn || JUMP_P ( cur_insn ) || LABEL_P ( cur_insn ) ) return false ; rtx_code_label * new_label = gen_label_rtx ( ) ; uncond_jump = emit_jump_insn_after ( gen_rtx_SET ( pc_rtx , gen_rtx_LABEL_REF ( VOIDmode , code_label ) ) , insn ) ; emit_label_after ( new_label , uncond_jump ) ; tmp = XEXP ( SET_SRC ( set ) , 1 ) ; XEXP ( SET_SRC ( set ) , 1 ) = XEXP ( SET_SRC ( set ) , 2 ) ; XEXP ( SET_SRC ( set ) , 2 ) = tmp ; INSN_CODE ( insn ) = - 1 ; XEXP ( label_ref , 0 ) = new_label ; JUMP_LABEL ( insn ) = new_label ; JUMP_LABEL ( uncond_jump ) = code_label ; return true ; } </s>

On z10 and later the dynamic branch prediction must see the backward jump within a certain windows . If not it falls back to the static prediction . This function rearranges the loop backward branch in a way which makes the static prediction always correct . The function returns true if it added an instruction .


<s> bool legitimate_la_operand_p ( rtx op ) { struct s390_address addr ; if ( ! s390_decompose_address ( op , & addr ) ) return false ; return ( TARGET_64BIT || addr . pointer ) ; } </s>

Return 1 if OP is a valid operand for the LA instruction . In 31-bit , we need to prove that the result is used as an address , as LA performs only a 31-bit addition .


<s> bool X86TargetLowering :: isCheapToSpeculateCtlz ( ) const { return Subtarget -> hasLZCNT ( ) ; } </s>

Return true if it is cheap to speculate a call to intrinsic ctlz .


<s>
static
wasm
::
ValType
getType
(
const
TargetRegisterClass
*
RC
)
{
if
(
RC
==
&
WebAssembly
::
I32RegClass
)
return
wasm
::
ValType
::
I32
;
if
(
RC
==
&
WebAssembly
::
I64RegClass
)
return
wasm
::
ValType
::
I64
;
if
(
RC
==
&
WebAssembly
::
F32RegClass
)
return
wasm
::
ValType
::
F32
;
if
(
RC
==
&
WebAssembly
::
F64RegClass
)
return
wasm
::
ValType
::
F64
;
llvm_unreachable
(
"Unexpected register class"
)
;
}
</s>

Overload to return most specific vector type .


<s> inline static const char * getTagName ( TAGS tag ) { switch ( tag ) { default : return "" ; case PREFIX_SYMBOL : return "@" ; case AUTOS_LABEL : return ".auto." ; case FRAME_LABEL : return ".frame." ; case TEMPS_LABEL : return ".temp." ; case ARGS_LABEL : return ".args." ; case RET_LABEL : return ".ret." ; case LIBCALL : return ".lib." ; case FRAME_SECTION : return ".frame_section." ; case AUTOS_SECTION : return ".autos_section." ; case CODE_SECTION : return ".code_section." ; case USER_SECTION : return ".user_section." ; } } </s>

Return the tag of this operand bundle as a string .


<s> static bool avr_hard_regno_call_part_clobbered ( unsigned , unsigned regno , machine_mode mode ) { if ( ! avr_hard_regno_mode_ok ( regno , mode ) ) return 0 ; return ( ( regno <= LAST_CALLEE_SAVED_REG && regno + GET_MODE_SIZE ( mode ) > 1 + LAST_CALLEE_SAVED_REG ) || ( regno < REG_Y && regno + GET_MODE_SIZE ( mode ) > REG_Y ) || ( regno < REG_Z && regno + GET_MODE_SIZE ( mode ) > REG_Z ) ) ; } </s>

Implement ` HARD_REGNO_CALL_PART_CLOBBERED ' .


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> bool R600InstrInfo :: FindSwizzleForVectorSlot ( const std :: vector < std :: vector < std :: pair < int , unsigned > > > & IGSrcs , std :: vector < R600InstrInfo :: BankSwizzle > & SwzCandidate , const std :: vector < std :: pair < int , unsigned > > & TransSrcs , R600InstrInfo :: BankSwizzle TransSwz ) const { unsigned ValidUpTo = 0 ; do { ValidUpTo = isLegalUpTo ( IGSrcs , SwzCandidate , TransSrcs , TransSwz ) ; if ( ValidUpTo == IGSrcs . size ( ) ) return true ; } while ( NextPossibleSolution ( SwzCandidate , ValidUpTo ) ) ; return false ; } </s>

Enumerate all possible Swizzle sequence to find one that can meet all read port requirements .


<s>
bool
FixupBWInstPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
!
FixupBWInsts
||
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
this
->
MF
=
&
MF
;
TII
=
MF
.
getSubtarget
<
X86Subtarget
>
(
)
.
getInstrInfo
(
)
;
OptForSize
=
MF
.
getFunction
(
)
.
hasOptSize
(
)
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
LiveRegs
.
init
(
TII
->
getRegisterInfo
(
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Start X86FixupBWInsts\n"
;
)
;
for
(
auto
&
MBB
:
MF
)
processBasicBlock
(
MF
,
MBB
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"End X86FixupBWInsts\n"
;
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


"%<target_clones%> attribute needs GLIBC (2.23 and newer) that "

"multiversioning needs %<ifunc%> which is not supported "

Make a dispatcher declaration for the multi-versioned function DECL . Calls to DECL function will be replaced with calls to the dispatcher by the front-end . Returns the decl of the dispatcher function .


<s> static bool r10k_needs_protection_p_1 ( rtx x , rtx_insn * insn ) { subrtx_var_iterator :: array_type array ; FOR_EACH_SUBRTX_VAR ( iter , array , x , NONCONST ) { rtx mem = * iter ; if ( MEM_P ( mem ) ) { if ( ( MEM_EXPR ( mem ) && MEM_OFFSET_KNOWN_P ( mem ) && r10k_safe_mem_expr_p ( MEM_EXPR ( mem ) , MEM_OFFSET ( mem ) ) ) || r10k_safe_address_p ( XEXP ( mem , 0 ) , insn ) ) iter . skip_subrtxes ( ) ; else return true ; } } return false ; } </s>

Return true if X contains a MEM that is not safe from R10K speculation . INSN is the instruction that contains X .


<s> const PPCMCExpr * PPCMCExpr :: Create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { int AssemblerDialect = Ctx . getAsmInfo ( ) -> getAssemblerDialect ( ) ; return new ( Ctx ) PPCMCExpr ( Kind , Expr , AssemblerDialect ) ; } </s>

Construct a unary instruction , given the opcode and an operand .


<s>
const
MCExpr
*
ARMElfTargetObjectFile
::
getTTypeGlobalReference
(
const
GlobalValue
*
GV
,
unsigned
Encoding
,
Mangler
&
Mang
,
const
TargetMachine
&
TM
,
MachineModuleInfo
*
MMI
,
MCStreamer
&
Streamer
)
const
{
if
(
TM
.
getMCAsmInfo
(
)
->
getExceptionHandlingType
(
)
!=
ExceptionHandling
::
ARM
)
return
TargetLoweringObjectFileELF
::
getTTypeGlobalReference
(
GV
,
Encoding
,
Mang
,
TM
,
MMI
,
Streamer
)
;
assert
(
Encoding
==
DW_EH_PE_absptr
&&
"Can handle absptr encoding only"
)
;
return
MCSymbolRefExpr
::
Create
(
TM
.
getSymbol
(
GV
,
Mang
)
,
MCSymbolRefExpr
::
VK_ARM_TARGET2
,
getContext
(
)
)
;
}
</s>

The mach-o version of this method defaults to returning a stub reference .

ARM
ARM
ARM
"Can handle absptr encoding only"
ARM


<s>
SDValue
SystemZTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
return
SDValue
(
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

SystemZ
SystemZ
ISD::BR_CC
ISD::SELECT_CC
ISD::GlobalAddress
ISD::JumpTable
ISD::ConstantPool
"Should not custom lower this!"


<s> void MBlazeInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; BuildMI ( MBB , I , DL , get ( MBlaze :: LWI ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> bool ARMFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; unsigned CFSize = FFI -> getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( 1 << 12 ) - 1 ) / 2 ) return false ; return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> static int arm_barrier_cost ( rtx_insn * insn ) { int base_cost = 50 ; rtx_insn * next = next_nonnote_insn ( insn ) ; if ( next != NULL && LABEL_P ( next ) ) base_cost -= 20 ; switch ( GET_CODE ( insn ) ) { case CODE_LABEL : return 50 ; case INSN : case CALL_INSN : return base_cost ; case JUMP_INSN : return base_cost - 10 ; default : return base_cost + 10 ; } } </s>

Return the cost of forcibly inserting a barrier after INSN .


<s> void ix86_emit_fp_unordered_jump ( rtx label ) { rtx reg = gen_reg_rtx ( HImode ) ; rtx temp ; emit_insn ( gen_x86_fnstsw_1 ( reg ) ) ; if ( TARGET_SAHF && ( TARGET_USE_SAHF || optimize_insn_for_size_p ( ) ) ) { emit_insn ( gen_x86_sahf_1 ( reg ) ) ; temp = gen_rtx_REG ( CCmode , FLAGS_REG ) ; temp = gen_rtx_UNORDERED ( VOIDmode , temp , const0_rtx ) ; } else { emit_insn ( gen_testqi_ext_ccno_0 ( reg , GEN_INT ( 0x04 ) ) ) ; temp = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; temp = gen_rtx_NE ( VOIDmode , temp , const0_rtx ) ; } temp = gen_rtx_IF_THEN_ELSE ( VOIDmode , temp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; temp = gen_rtx_SET ( pc_rtx , temp ) ; emit_jump_insn ( temp ) ; predict_jump ( REG_BR_PROB_BASE * 10 / 100 ) ; } </s>

Output code to perform a conditional jump to LABEL , if C2 flag in FP status register is set .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"SI insert wait instructions"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> StringRef getPassName ( ) const override { return AARCH64_BRANCH_TARGETS_NAME ; } </s>


<s> bool aarch64_use_return_insn_p ( void ) { if ( ! reload_completed ) return false ; if ( crtl -> profile ) return false ; aarch64_layout_frame ( ) ; return known_eq ( cfun -> machine -> frame . frame_size , 0 ) ; } </s>

Return TRUE if we can use a simple_return insn . This function checks whether the callee saved stack is empty , which means no restore actions are need . The pro_and_epilogue will use this to check whether shrink-wrapping opt is feasible .


<s> int rx_adjust_insn_length ( rtx_insn * insn , int current_length ) { rtx extend , mem , offset ; bool zero ; int factor ; if ( ! INSN_P ( insn ) ) return current_length ; switch ( INSN_CODE ( insn ) ) { default : return current_length ; case CODE_FOR_plussi3_zero_extendhi : case CODE_FOR_andsi3_zero_extendhi : case CODE_FOR_iorsi3_zero_extendhi : case CODE_FOR_xorsi3_zero_extendhi : case CODE_FOR_divsi3_zero_extendhi : case CODE_FOR_udivsi3_zero_extendhi : case CODE_FOR_minussi3_zero_extendhi : case CODE_FOR_smaxsi3_zero_extendhi : case CODE_FOR_sminsi3_zero_extendhi : case CODE_FOR_multsi3_zero_extendhi : case CODE_FOR_comparesi3_zero_extendhi : zero = true ; factor = 2 ; break ; case CODE_FOR_plussi3_sign_extendhi : case CODE_FOR_andsi3_sign_extendhi : case CODE_FOR_iorsi3_sign_extendhi : case CODE_FOR_xorsi3_sign_extendhi : case CODE_FOR_divsi3_sign_extendhi : case CODE_FOR_udivsi3_sign_extendhi : case CODE_FOR_minussi3_sign_extendhi : case CODE_FOR_smaxsi3_sign_extendhi : case CODE_FOR_sminsi3_sign_extendhi : case CODE_FOR_multsi3_sign_extendhi : case CODE_FOR_comparesi3_sign_extendhi : zero = false ; factor = 2 ; break ; case CODE_FOR_plussi3_zero_extendqi : case CODE_FOR_andsi3_zero_extendqi : case CODE_FOR_iorsi3_zero_extendqi : case CODE_FOR_xorsi3_zero_extendqi : case CODE_FOR_divsi3_zero_extendqi : case CODE_FOR_udivsi3_zero_extendqi : case CODE_FOR_minussi3_zero_extendqi : case CODE_FOR_smaxsi3_zero_extendqi : case CODE_FOR_sminsi3_zero_extendqi : case CODE_FOR_multsi3_zero_extendqi : case CODE_FOR_comparesi3_zero_extendqi : zero = true ; factor = 1 ; break ; case CODE_FOR_plussi3_sign_extendqi : case CODE_FOR_andsi3_sign_extendqi : case CODE_FOR_iorsi3_sign_extendqi : case CODE_FOR_xorsi3_sign_extendqi : case CODE_FOR_divsi3_sign_extendqi : case CODE_FOR_udivsi3_sign_extendqi : case CODE_FOR_minussi3_sign_extendqi : case CODE_FOR_smaxsi3_sign_extendqi : case CODE_FOR_sminsi3_sign_extendqi : case CODE_FOR_multsi3_sign_extendqi : case CODE_FOR_comparesi3_sign_extendqi : zero = false ; factor = 1 ; break ; } extend = single_set ( insn ) ; gcc_assert ( extend != NULL_RTX ) ; extend = SET_SRC ( extend ) ; if ( GET_CODE ( XEXP ( extend , 0 ) ) == ZERO_EXTEND || GET_CODE ( XEXP ( extend , 0 ) ) == SIGN_EXTEND ) extend = XEXP ( extend , 0 ) ; else extend = XEXP ( extend , 1 ) ; gcc_assert ( ( zero && ( GET_CODE ( extend ) == ZERO_EXTEND ) ) || ( ! zero && ( GET_CODE ( extend ) == SIGN_EXTEND ) ) ) ; mem = XEXP ( extend , 0 ) ; gcc_checking_assert ( MEM_P ( mem ) ) ; if ( REG_P ( XEXP ( mem , 0 ) ) ) return ( zero && factor == 1 ) ? 2 : 3 ; gcc_checking_assert ( GET_CODE ( XEXP ( mem , 0 ) ) == PLUS ) ; gcc_checking_assert ( REG_P ( XEXP ( XEXP ( mem , 0 ) , 0 ) ) ) ; offset = XEXP ( XEXP ( mem , 0 ) , 1 ) ; gcc_checking_assert ( GET_CODE ( offset ) == CONST_INT ) ; if ( IN_RANGE ( INTVAL ( offset ) , 0 , 255 * factor ) ) return ( zero && factor == 1 ) ? 3 : 4 ; return ( zero && factor == 1 ) ? 4 : 5 ; } </s>

Compute the real length of the extending load-and-op instructions .


<s> bool nios2_large_constant_memory_operand_p ( rtx x ) { rtx addr ; if ( GET_CODE ( x ) != MEM ) return false ; addr = XEXP ( x , 0 ) ; return ( nios2_large_constant_p ( addr ) || nios2_plus_large_constant_p ( addr ) ) ; } </s>

Return true if X is a MEM whose address expression involves a large ( 32-bit ) constant .


<s> bool M68kInstrInfo :: getStackSlotRange ( const TargetRegisterClass * RC , unsigned SubIdx , unsigned & Size , unsigned & Offset , const MachineFunction & MF ) const { Size = 4 ; Offset = 0 ; return true ; } </s>

Compute the size in bytes and offset within a stack slot of a spilled register or subregister .


<s> const PIC16TargetObjectFile & getObjFileLowering ( ) const { return ( const PIC16TargetObjectFile & ) AsmPrinter :: getObjFileLowering ( ) ; } </s>

Return information about object file lowering .


<s> SDValue AArch64TargetLowering :: getRecipEstimate ( SDValue Operand , SelectionDAG & DAG , int Enabled , int & ExtraSteps ) const { if ( Enabled == ReciprocalEstimate :: Enabled ) if ( SDValue Estimate = getEstimate ( Subtarget , AArch64ISD :: FRECPE , Operand , DAG , ExtraSteps ) ) { SDLoc DL ( Operand ) ; EVT VT = Operand . getValueType ( ) ; SDNodeFlags Flags ; Flags . setUnsafeAlgebra ( true ) ; for ( int i = ExtraSteps ; i > 0 ; -- i ) { SDValue Step = DAG . getNode ( AArch64ISD :: FRECPS , DL , VT , Operand , Estimate , & Flags ) ; Estimate = DAG . getNode ( ISD :: FMUL , DL , VT , Estimate , Step , & Flags ) ; } ExtraSteps = 0 ; return Estimate ; } return SDValue ( ) ; } </s>

Return a reciprocal estimate value for the input operand .


<s>
SDValue
VETargetLowering
::
withTargetFlags
(
SDValue
Op
,
unsigned
TF
,
SelectionDAG
&
DAG
)
const
{
if
(
const
GlobalAddressSDNode
*
GA
=
dyn_cast
<
GlobalAddressSDNode
>
(
Op
)
)
return
DAG
.
getTargetGlobalAddress
(
GA
->
getGlobal
(
)
,
SDLoc
(
GA
)
,
GA
->
getValueType
(
0
)
,
GA
->
getOffset
(
)
,
TF
)
;
if
(
const
BlockAddressSDNode
*
BA
=
dyn_cast
<
BlockAddressSDNode
>
(
Op
)
)
return
DAG
.
getTargetBlockAddress
(
BA
->
getBlockAddress
(
)
,
Op
.
getValueType
(
)
,
0
,
TF
)
;
if
(
const
ConstantPoolSDNode
*
CP
=
dyn_cast
<
ConstantPoolSDNode
>
(
Op
)
)
return
DAG
.
getTargetConstantPool
(
CP
->
getConstVal
(
)
,
CP
->
getValueType
(
0
)
,
CP
->
getAlign
(
)
,
CP
->
getOffset
(
)
,
TF
)
;
if
(
const
ExternalSymbolSDNode
*
ES
=
dyn_cast
<
ExternalSymbolSDNode
>
(
Op
)
)
return
DAG
.
getTargetExternalSymbol
(
ES
->
getSymbol
(
)
,
ES
->
getValueType
(
0
)
,
TF
)
;
if
(
const
JumpTableSDNode
*
JT
=
dyn_cast
<
JumpTableSDNode
>
(
Op
)
)
return
DAG
.
getTargetJumpTable
(
JT
->
getIndex
(
)
,
JT
->
getValueType
(
0
)
,
TF
)
;
llvm_unreachable
(
"Unhandled address SDNode"
)
;
}
</s>


<s> bool SparcSubtarget :: enableMachineScheduler ( ) const { return true ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


<s> bool SIFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MFI . hasCalls ( ) && ! MF . getInfo < SIMachineFunctionInfo > ( ) -> isEntryFunction ( ) ) { return MFI . getStackSize ( ) != 0 ; } return MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || MF . getSubtarget < GCNSubtarget > ( ) . getRegisterInfo ( ) -> needsStackRealignment ( MF ) || MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static void computeKnownBits ( SelectionDAG & DAG , SDValue Op , APInt & KnownZero , APInt & KnownOne ) { if ( Op . getOpcode ( ) == ARMISD :: BFI ) { computeKnownBits ( DAG , Op . getOperand ( 0 ) , KnownZero , KnownOne ) ; ConstantSDNode * CI = cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ; const APInt & Mask = CI -> getAPIntValue ( ) ; KnownZero &= Mask ; KnownOne &= Mask ; return ; } if ( Op . getOpcode ( ) == ARMISD :: CMOV ) { APInt KZ2 ( KnownZero . getBitWidth ( ) , 0 ) ; APInt KO2 ( KnownOne . getBitWidth ( ) , 0 ) ; computeKnownBits ( DAG , Op . getOperand ( 1 ) , KnownZero , KnownOne ) ; computeKnownBits ( DAG , Op . getOperand ( 2 ) , KZ2 , KO2 ) ; KnownZero &= KZ2 ; KnownOne &= KO2 ; return ; } return DAG . computeKnownBits ( Op , KnownZero , KnownOne ) ; } </s>

Determine which bits of Op are known to be either zero or one and return them in Known .