<s> SDValue HexagonTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SDValue Op ( N , 0 ) ; if ( isHvxOperation ( Op ) ) { if ( SDValue V = PerformHvxDAGCombine ( N , DCI ) ) return V ; return SDValue ( ) ; } const SDLoc & dl ( Op ) ; unsigned Opc = Op . getOpcode ( ) ; if ( Opc == HexagonISD :: P2D ) { SDValue P = Op . getOperand ( 0 ) ; switch ( P . getOpcode ( ) ) { case HexagonISD :: PTRUE : return DCI . DAG . getConstant ( - 1 , dl , ty ( Op ) ) ; case HexagonISD :: PFALSE : return getZero ( dl , ty ( Op ) , DCI . DAG ) ; default : break ; } } else if ( Opc == ISD :: VSELECT ) { SDValue Cond = Op . getOperand ( 0 ) ; if ( Cond -> getOpcode ( ) == ISD :: XOR ) { SDValue C0 = Cond . getOperand ( 0 ) , C1 = Cond . getOperand ( 1 ) ; if ( C1 -> getOpcode ( ) == HexagonISD :: PTRUE ) { SDValue VSel = DCI . DAG . getNode ( ISD :: VSELECT , dl , ty ( Op ) , C0 , Op . getOperand ( 2 ) , Op . getOperand ( 1 ) ) ; return VSel ; } } } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> int c4x_Q_constraint ( rtx op ) { enum machine_mode mode = GET_MODE ( op ) ; if ( GET_CODE ( op ) != MEM ) return 0 ; op = XEXP ( op , 0 ) ; switch ( GET_CODE ( op ) ) { case REG : return 1 ; case PLUS : { rtx op0 = XEXP ( op , 0 ) ; rtx op1 = XEXP ( op , 1 ) ; if ( ! REG_P ( op0 ) ) return 0 ; if ( REG_P ( op1 ) ) return 1 ; if ( GET_CODE ( op1 ) != CONST_INT ) return 0 ; if ( mode == HImode || mode == HFmode ) return IS_DISP8_OFF_CONST ( INTVAL ( op1 ) ) ; return IS_DISP8_CONST ( INTVAL ( op1 ) ) ; } break ; default : break ; } return 0 ; } </s>

ARx + 9-bit signed const or IRn * ARx , * +ARx ( n ) , * -ARx ( n ) , * +ARx ( IRn ) , * -Arx ( IRn ) for -256 < n < 256 We do n't include the pre/post inc/dec forms here since they are handled by the < > constraints .


<s> unsigned HexagonRegisterInfo :: getNumRegPressureSets ( ) const { return 4 ; } </s>

Get the number of dimensions of register pressure .


<s> MachineInstr * SystemZInstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const { return nullptr ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s>
SDValue
HexagonTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
llvm_unreachable
(
"TLS not implemented for Hexagon."
)
;
case
ISD
::
MEMBARRIER
:
return
LowerMEMBARRIER
(
Op
,
DAG
)
;
case
ISD
::
ATOMIC_FENCE
:
return
LowerATOMIC_FENCE
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGLOBALADDRESS
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
BR_JT
:
return
LowerBR_JT
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
INLINEASM
:
return
LowerINLINEASM
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

Hexagon
Hexagon
"Should not custom lower this!"
ISD::RETURNADDR
ISD::FRAMEADDR
ISD::GlobalTLSAddress
"TLS not implemented for Hexagon."
ISD::MEMBARRIER
ISD::ATOMIC_FENCE
ISD::GlobalAddress
ISD::VASTART
ISD::BR_JT
ISD::DYNAMIC_STACKALLOC
ISD::SELECT_CC
ISD::INTRINSIC_WO_CHAIN
ISD::INLINEASM


<s>
const
char
*
output_parallel_addb
(
rtx
*
operands
,
int
length
)
{
if
(
operands
[
0
]
==
operands
[
1
]
)
operands
[
1
]
=
operands
[
2
]
;
if
(
length
==
4
)
return
"add%I1b,tr %1,%0,%3"
;
if
(
dbr_sequence_length
(
)
==
0
)
{
return
"b %3\n\tadd%I1 %1,%0,%0"
;
}
else
{
return
"add%I1 %1,%0,%0\n\tb %3"
;
}
}
</s>

Output an unconditional add and branch insn .


<s>
unsigned
SIInstrInfo
::
getInstSizeInBytes
(
const
MachineInstr
&
MI
)
const
{
unsigned
Opc
=
MI
.
getOpcode
(
)
;
const
MCInstrDesc
&
Desc
=
getMCOpcodeFromPseudo
(
Opc
)
;
unsigned
DescSize
=
Desc
.
getSize
(
)
;
if
(
DescSize
!=
0
&&
DescSize
!=
4
)
return
DescSize
;
if
(
isFixedSize
(
MI
)
)
return
DescSize
;
if
(
isVALU
(
MI
)
||
isSALU
(
MI
)
)
{
int
Src0Idx
=
AMDGPU
::
getNamedOperandIdx
(
Opc
,
AMDGPU
::
OpName
::
src0
)
;
if
(
Src0Idx
==
1
)
return
4
;
if
(
isLiteralConstantLike
(
MI
.
getOperand
(
Src0Idx
)
,
Desc
.
OpInfo
[
Src0Idx
]
)
)
return
8
;
int
Src1Idx
=
AMDGPU
::
getNamedOperandIdx
(
Opc
,
AMDGPU
::
OpName
::
src1
)
;
if
(
Src1Idx
==
1
)
return
4
;
if
(
isLiteralConstantLike
(
MI
.
getOperand
(
Src1Idx
)
,
Desc
.
OpInfo
[
Src1Idx
]
)
)
return
8
;
return
4
;
}
if
(
DescSize
==
4
)
return
4
;
switch
(
Opc
)
{
case
TargetOpcode
::
IMPLICIT_DEF
:
case
TargetOpcode
::
KILL
:
case
TargetOpcode
::
DBG_VALUE
:
case
TargetOpcode
::
EH_LABEL
:
return
0
;
case
TargetOpcode
::
BUNDLE
:
return
getInstBundleSize
(
MI
)
;
case
TargetOpcode
::
INLINEASM
:
{
const
MachineFunction
*
MF
=
MI
.
getParent
(
)
->
getParent
(
)
;
const
char
*
AsmStr
=
MI
.
getOperand
(
0
)
.
getSymbolName
(
)
;
return
getInlineAsmLength
(
AsmStr
,
*
MF
->
getTarget
(
)
.
getMCAsmInfo
(
)
)
;
}
default
:
llvm_unreachable
(
"unable to find instruction size"
)
;
}
}
</s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> const MCExpr * X86LinuxTargetObjectFile :: getDebugThreadLocalSymbol ( const MCSymbol * Sym ) const { return MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_DTPOFF , getContext ( ) ) ; } </s>

Describe a TLS variable address within debug info .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < AssumptionCacheTracker > ( ) ; AU . addRequired < DivergenceAnalysis > ( ) ; AU . setPreservesAll ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO , ISD :: ArgFlagsTy Flags ) override { LLT p0 = LLT :: pointer ( 0 , DL . getPointerSizeInBits ( 0 ) ) ; LLT SType = LLT :: scalar ( DL . getPointerSizeInBits ( 0 ) ) ; Register StackReg = STI . getRegisterInfo ( ) -> getStackRegister ( ) ; auto SPReg = MIRBuilder . buildCopy ( p0 , StackReg ) . getReg ( 0 ) ; auto OffsetReg = MIRBuilder . buildConstant ( SType , Offset ) ; auto AddrReg = MIRBuilder . buildPtrAdd ( p0 , SPReg , OffsetReg ) ; MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ; return AddrReg . getReg ( 0 ) ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s>
void
SystemZInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
DestReg
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
unsigned
Opc
=
0
;
if
(
RC
==
&
SystemZ
::
GR32RegClass
||
RC
==
&
SystemZ
::
ADDR32RegClass
)
Opc
=
SystemZ
::
MOV32rm
;
else
if
(
RC
==
&
SystemZ
::
GR64RegClass
||
RC
==
&
SystemZ
::
ADDR64RegClass
)
{
Opc
=
SystemZ
::
MOV64rm
;
}
else
if
(
RC
==
&
SystemZ
::
FP32RegClass
)
{
Opc
=
SystemZ
::
FMOV32rm
;
}
else
if
(
RC
==
&
SystemZ
::
FP64RegClass
)
{
Opc
=
SystemZ
::
FMOV64rm
;
}
else
if
(
RC
==
&
SystemZ
::
GR64PRegClass
)
{
Opc
=
SystemZ
::
MOV64Prm
;
}
else
if
(
RC
==
&
SystemZ
::
GR128RegClass
)
{
Opc
=
SystemZ
::
MOV128rm
;
}
else
llvm_unreachable
(
"Unsupported regclass to load"
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
,
DestReg
)
,
FrameIdx
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> MVT X86TargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i1 && Subtarget . hasAVX512 ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; MVT RegisterVT ; unsigned NumRegisters ; std :: tie ( RegisterVT , NumRegisters ) = handleMaskRegisterForCallingConv ( NumElts , CC , Subtarget ) ; if ( RegisterVT != MVT :: INVALID_SIMPLE_VALUE_TYPE ) return RegisterVT ; } if ( VT == MVT :: v3f16 && Subtarget . hasFP16 ( ) ) return MVT :: v8f16 ; return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


"function_adv({gp reg found = %d, arg # = %2d, words = %2d}, %4s, "

Handle the FUNCTION_ARG_ADVANCE macro . Update the data in CUM to advance over an argument of mode MODE and data type TYPE . TYPE is null for libcalls where that information may not be available .


<s> static void register_builtin_types ( ) { scalar_types [ VECTOR_TYPE_ ## ACLE_NAME ] = SCALAR_TYPE ; for ( unsigned int i = 0 ; i < NUM_VECTOR_TYPES ; ++ i ) { tree eltype = scalar_types [ i ] ; tree vectype ; unsigned int num_zr = 0 , num_pr = 0 ; if ( eltype == boolean_type_node ) { vectype = build_truth_vector_type_for_mode ( BYTES_PER_SVE_VECTOR , VNx16BImode ) ; gcc_assert ( TYPE_MODE ( vectype ) == VNx16BImode && TYPE_MODE ( vectype ) == TYPE_MODE_RAW ( vectype ) && TYPE_ALIGN ( vectype ) == 16 && known_eq ( wi :: to_poly_offset ( TYPE_SIZE ( vectype ) ) , BYTES_PER_SVE_VECTOR ) ) ; num_pr = 1 ; } else { scalar_mode elmode = SCALAR_TYPE_MODE ( eltype ) ; unsigned int elbytes = GET_MODE_SIZE ( elmode ) ; poly_uint64 nunits = exact_div ( BYTES_PER_SVE_VECTOR , elbytes ) ; machine_mode mode = aarch64_sve_data_mode ( elmode , nunits ) . require ( ) ; vectype = build_vector_type_for_mode ( eltype , mode ) ; gcc_assert ( VECTOR_MODE_P ( TYPE_MODE ( vectype ) ) && TYPE_MODE ( vectype ) == mode && TYPE_MODE_RAW ( vectype ) == mode && TYPE_ALIGN ( vectype ) == 128 && known_eq ( wi :: to_poly_offset ( TYPE_SIZE ( vectype ) ) , BITS_PER_SVE_VECTOR ) ) ; num_zr = 1 ; } vectype = build_distinct_type_copy ( vectype ) ; gcc_assert ( vectype == TYPE_MAIN_VARIANT ( vectype ) ) ; SET_TYPE_STRUCTURAL_EQUALITY ( vectype ) ; TYPE_ARTIFICIAL ( vectype ) = 1 ; TYPE_INDIVISIBLE_P ( vectype ) = 1 ; add_sve_type_attribute ( vectype , num_zr , num_pr , vector_types [ i ] . mangled_name ) ; make_type_sizeless ( vectype ) ; abi_vector_types [ i ] = vectype ; lang_hooks . types . register_builtin_type ( vectype , vector_types [ i ] . abi_name ) ; } } </s>

Register the built-in RVV ABI types , such as __rvv_int32m1_t .


"Can only insert epilog into returning blocks"

"SPURegisterInfo::emitEpilogue: FrameSize not aligned"


<s> void SPIRVAsmPrinter :: emitEndOfAsmFile ( Module & M ) { if ( ModuleSectionsEmitted == false ) { MAI = & SPIRVModuleAnalysis :: MAI ; outputModuleSections ( ) ; ModuleSectionsEmitted = true ; } } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> rtx xlogue_layout :: get_stub_rtx ( enum xlogue_stub stub ) { const unsigned n_extra_regs = cfun -> machine -> call_ms2sysv_extra_regs ; gcc_checking_assert ( n_extra_regs <= MAX_EXTRA_REGS ) ; gcc_assert ( stub < XLOGUE_STUB_COUNT ) ; gcc_assert ( crtl -> stack_realign_finalized ) ; return gen_rtx_SYMBOL_REF ( Pmode , get_stub_name ( stub , n_extra_regs ) ) ; } </s>

Return rtx of a symbol ref for the entry point ( based upon cfun- > machine- > call_ms2sysv_extra_regs ) of the specified stub .


<s>
Value
*
PPCTargetLowering
::
emitMaskedAtomicRMWIntrinsic
(
IRBuilderBase
&
Builder
,
AtomicRMWInst
*
AI
,
Value
*
AlignedAddr
,
Value
*
Incr
,
Value
*
Mask
,
Value
*
ShiftAmt
,
AtomicOrdering
Ord
)
const
{
assert
(
EnableQuadwordAtomics
&&
Subtarget
.
hasQuadwordAtomics
(
)
&&
"Only support quadword now"
)
;
Module
*
M
=
Builder
.
GetInsertBlock
(
)
->
getParent
(
)
->
getParent
(
)
;
Type
*
ValTy
=
cast
<
PointerType
>
(
AlignedAddr
->
getType
(
)
)
->
getElementType
(
)
;
assert
(
ValTy
->
getPrimitiveSizeInBits
(
)
==
128
)
;
Function
*
RMW
=
Intrinsic
::
getDeclaration
(
M
,
getIntrinsicForAtomicRMWBinOp128
(
AI
->
getOperation
(
)
)
)
;
Type
*
Int64Ty
=
Type
::
getInt64Ty
(
M
->
getContext
(
)
)
;
Value
*
IncrLo
=
Builder
.
CreateTrunc
(
Incr
,
Int64Ty
,
"incr_lo"
)
;
Value
*
IncrHi
=
Builder
.
CreateTrunc
(
Builder
.
CreateLShr
(
Incr
,
64
)
,
Int64Ty
,
"incr_hi"
)
;
Value
*
Addr
=
Builder
.
CreateBitCast
(
AlignedAddr
,
Type
::
getInt8PtrTy
(
M
->
getContext
(
)
)
)
;
Value
*
LoHi
=
Builder
.
CreateCall
(
RMW
,
{
Addr
,
IncrLo
,
IncrHi
}
)
;
Value
*
Lo
=
Builder
.
CreateExtractValue
(
LoHi
,
0
,
"lo"
)
;
Value
*
Hi
=
Builder
.
CreateExtractValue
(
LoHi
,
1
,
"hi"
)
;
Lo
=
Builder
.
CreateZExt
(
Lo
,
ValTy
,
"lo64"
)
;
Hi
=
Builder
.
CreateZExt
(
Hi
,
ValTy
,
"hi64"
)
;
return
Builder
.
CreateOr
(
Lo
,
Builder
.
CreateShl
(
Hi
,
ConstantInt
::
get
(
ValTy
,
64
)
)
,
"val64"
)
;
}
</s>

Perform a masked atomicrmw using a target-specific intrinsic .


<s> unsigned LanaiInstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == Lanai :: LDW_RI ) { unsigned Reg ; if ( ( Reg = isLoadFromStackSlot ( MI , FrameIndex ) ) ) return Reg ; const MachineMemOperand * Dummy ; return hasLoadFromStackSlot ( MI , Dummy , FrameIndex ) ; } return 0 ; } </s>

isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s> unsigned epiphany_adjust_field_align ( tree field , unsigned computed ) { if ( computed == 32 && TREE_CODE ( TREE_TYPE ( field ) ) == ARRAY_TYPE ) { tree elmsz = TYPE_SIZE ( TREE_TYPE ( TREE_TYPE ( field ) ) ) ; if ( ! tree_fits_uhwi_p ( elmsz ) || tree_to_uhwi ( elmsz ) >= 32 ) return 64 ; } return computed ; } </s>

Upping the alignment of arrays in structs is not only a performance enhancement , it also helps preserve assumptions about how arrays-at-the-end-of-structs work , like for struct gcov_fn_info in libgcov.c .


<s> static void spu_finish_cost ( void * data , unsigned * prologue_cost , unsigned * body_cost , unsigned * epilogue_cost ) { unsigned * cost = ( unsigned * ) data ; * prologue_cost = cost [ vect_prologue ] ; * body_cost = cost [ vect_body ] ; * epilogue_cost = cost [ vect_epilogue ] ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addPreserved < MachineBlockFrequencyInfo > ( ) ; AU . addPreservedID ( MachineDominatorsID ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> bool PPCTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , Align , MachineMemOperand :: Flags , bool * Fast ) const { if ( DisablePPCUnaligned ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( VT . isFloatingPoint ( ) && ! VT . isVector ( ) && ! Subtarget . allowsUnalignedFPAccess ( ) ) return false ; if ( VT . getSimpleVT ( ) . isVector ( ) ) { if ( Subtarget . hasVSX ( ) ) { if ( VT != MVT :: v2f64 && VT != MVT :: v2i64 && VT != MVT :: v4f32 && VT != MVT :: v4i32 ) return false ; } else { return false ; } } if ( VT == MVT :: ppcf128 ) return false ; if ( Fast ) * Fast = true ; return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> void R600PassConfig :: addPreSched2 ( ) { addPass ( createR600EmitClauseMarkers ( ) , false ) ; if ( EnableR600IfConvert ) addPass ( & IfConverterID , false ) ; addPass ( createR600ClauseMergePass ( ) , false ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> void AVRTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { Base :: Initialize ( Ctx , TM ) ; ProgmemDataSection = Ctx . getELFSection ( ".progmem.data" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ; } </s>

This method must be called before any actual lowering is done .


<s> bool AMDGPUTargetELFStreamer :: EmitHSAMetadata ( const AMDGPU :: HSAMD :: Metadata & HSAMetadata ) { std :: string HSAMetadataString ; if ( HSAMD :: toString ( HSAMetadata , HSAMetadataString ) ) return false ; auto & Context = getContext ( ) ; auto * DescBegin = Context . createTempSymbol ( ) ; auto * DescEnd = Context . createTempSymbol ( ) ; auto * DescSZ = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( DescEnd , Context ) , MCSymbolRefExpr :: create ( DescBegin , Context ) , Context ) ; EmitAMDGPUNote ( DescSZ , ELF :: NT_AMD_AMDGPU_HSA_METADATA , [ & ] ( MCELFStreamer & OS ) { OS . EmitLabel ( DescBegin ) ; OS . EmitBytes ( HSAMetadataString ) ; OS . EmitLabel ( DescEnd ) ; } ) ; return true ; } </s>

AMDGPU AMDGPU AMDGPU::HSAMD AMDGPU AMDGPU


<s> const RegClassWeight & R600RegisterInfo :: getRegClassWeight ( const TargetRegisterClass * RC ) const { return RCW ; } </s>

Get the weight in units of pressure for this register class .


<s>
SDValue
AArch64TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom lower this!"
)
;
case
ISD
::
FADD
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
ADD_F128
)
;
case
ISD
::
FSUB
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
SUB_F128
)
;
case
ISD
::
FMUL
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
MUL_F128
)
;
case
ISD
::
FDIV
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
DIV_F128
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
,
true
)
;
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
,
false
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
,
true
)
;
case
ISD
::
UINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
,
false
)
;
case
ISD
::
FP_ROUND
:
return
LowerFP_ROUND
(
Op
,
DAG
)
;
case
ISD
::
FP_EXTEND
:
return
LowerFP_EXTEND
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
BRCOND
:
return
LowerBRCOND
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddressELF
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
LowerSELECT
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
case
ISD
::
VACOPY
:
return
LowerVACOPY
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
}
return
SDValue
(
)
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool NVVMIntrRange :: runOnFunction ( Function & F ) { bool Changed = false ; for ( Instruction & I : instructions ( F ) ) { CallInst * Call = dyn_cast < CallInst > ( & I ) ; if ( ! Call ) continue ; if ( Function * Callee = Call -> getCalledFunction ( ) ) { switch ( Callee -> getIntrinsicID ( ) ) { case Intrinsic :: ptx_read_tid_x : case Intrinsic :: nvvm_read_ptx_sreg_tid_x : Changed |= addRangeMetadata ( 0 , MaxBlockSize . x , Call ) ; break ; case Intrinsic :: ptx_read_tid_y : case Intrinsic :: nvvm_read_ptx_sreg_tid_y : Changed |= addRangeMetadata ( 0 , MaxBlockSize . y , Call ) ; break ; case Intrinsic :: ptx_read_tid_z : case Intrinsic :: nvvm_read_ptx_sreg_tid_z : Changed |= addRangeMetadata ( 0 , MaxBlockSize . z , Call ) ; break ; case Intrinsic :: ptx_read_ntid_x : case Intrinsic :: nvvm_read_ptx_sreg_ntid_x : Changed |= addRangeMetadata ( 1 , MaxBlockSize . x + 1 , Call ) ; break ; case Intrinsic :: ptx_read_ntid_y : case Intrinsic :: nvvm_read_ptx_sreg_ntid_y : Changed |= addRangeMetadata ( 1 , MaxBlockSize . y + 1 , Call ) ; break ; case Intrinsic :: ptx_read_ntid_z : case Intrinsic :: nvvm_read_ptx_sreg_ntid_z : Changed |= addRangeMetadata ( 1 , MaxBlockSize . z + 1 , Call ) ; break ; case Intrinsic :: ptx_read_ctaid_x : case Intrinsic :: nvvm_read_ptx_sreg_ctaid_x : Changed |= addRangeMetadata ( 0 , MaxGridSize . x , Call ) ; break ; case Intrinsic :: ptx_read_ctaid_y : case Intrinsic :: nvvm_read_ptx_sreg_ctaid_y : Changed |= addRangeMetadata ( 0 , MaxGridSize . y , Call ) ; break ; case Intrinsic :: ptx_read_ctaid_z : case Intrinsic :: nvvm_read_ptx_sreg_ctaid_z : Changed |= addRangeMetadata ( 0 , MaxGridSize . z , Call ) ; break ; case Intrinsic :: ptx_read_nctaid_x : case Intrinsic :: nvvm_read_ptx_sreg_nctaid_x : Changed |= addRangeMetadata ( 1 , MaxGridSize . x + 1 , Call ) ; break ; case Intrinsic :: ptx_read_nctaid_y : case Intrinsic :: nvvm_read_ptx_sreg_nctaid_y : Changed |= addRangeMetadata ( 1 , MaxGridSize . y + 1 , Call ) ; break ; case Intrinsic :: ptx_read_nctaid_z : case Intrinsic :: nvvm_read_ptx_sreg_nctaid_z : Changed |= addRangeMetadata ( 1 , MaxGridSize . z + 1 , Call ) ; break ; case Intrinsic :: nvvm_read_ptx_sreg_warpsize : Changed |= addRangeMetadata ( 32 , 32 + 1 , Call ) ; break ; case Intrinsic :: ptx_read_laneid : Changed |= addRangeMetadata ( 0 , 32 , Call ) ; break ; default : break ; } } } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool RISCVExpandAtomicPseudo :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const RISCVInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; bool Modified = false ; for ( auto & MBB : MF ) Modified |= expandMBB ( MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s>
void
emit_safe_across_calls
(
void
)
{
unsigned
int
rs
,
re
;
int
out_state
;
rs
=
1
;
out_state
=
0
;
while
(
1
)
{
while
(
rs
<
64
&&
call_used_regs
[
PR_REG
(
rs
)
]
)
rs
++
;
if
(
rs
>=
64
)
break
;
for
(
re
=
rs
+
1
;
re
<
64
&&
!
call_used_regs
[
PR_REG
(
re
)
]
;
re
++
)
continue
;
if
(
out_state
==
0
)
{
fputs
(
"\t.pred.safe_across_calls "
,
asm_out_file
)
;
out_state
=
1
;
}
else
fputc
(
','
,
asm_out_file
)
;
if
(
re
==
rs
+
1
)
fprintf
(
asm_out_file
,
"p%u"
,
rs
)
;
else
fprintf
(
asm_out_file
,
"p%u-p%u"
,
rs
,
re
1
)
;
rs
=
re
+
1
;
}
if
(
out_state
)
fputc
(
'\n'
,
asm_out_file
)
;
}
</s>


<s> bool DCPU16PassConfig :: addInstSelector ( ) { addPass ( createDCPU16ISelDag ( getDCPU16TargetMachine ( ) , getOptLevel ( ) ) ) ; addPass ( createDCPU16Peephole ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static bool mmix_print_operand_punct_valid_p ( unsigned char code ) { return code == '+' || code == '.' || code == '!' ; } </s>


<s> static void ix86_conditional_register_usage ( void ) { int i , c_mask ; if ( cfun && cfun -> machine -> no_caller_saved_registers ) for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( ! fixed_regs [ i ] && ! ix86_function_value_regno_p ( i ) ) call_used_regs [ i ] = 0 ; if ( ! TARGET_64BIT ) { for ( i = FIRST_REX_INT_REG ; i <= LAST_REX_INT_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; for ( i = FIRST_REX_SSE_REG ; i <= LAST_REX_SSE_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; } c_mask = CALL_USED_REGISTERS_MASK ( TARGET_64BIT_MS_ABI ) ; CLEAR_HARD_REG_SET ( reg_class_contents [ ( int ) CLOBBERED_REGS ] ) ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { if ( call_used_regs [ i ] > 1 ) call_used_regs [ i ] = ! ! ( call_used_regs [ i ] & c_mask ) ; if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) GENERAL_REGS ] , i ) && call_used_regs [ i ] ) SET_HARD_REG_BIT ( reg_class_contents [ ( int ) CLOBBERED_REGS ] , i ) ; } if ( ! TARGET_MMX ) for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) MMX_REGS ] , i ) ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; if ( ! TARGET_SSE ) for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) SSE_REGS ] , i ) ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; if ( ! ( TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ) ) for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) FLOAT_REGS ] , i ) ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; if ( ! TARGET_AVX512F ) { for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; for ( i = FIRST_MASK_REG ; i <= LAST_MASK_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; } } </s>

Update register usage after having seen the compiler flags .


<s> static HOST_WIDE_INT iq2000_constant_alignment ( const_tree exp , HOST_WIDE_INT align ) { if ( TREE_CODE ( exp ) == STRING_CST || TREE_CODE ( exp ) == CONSTRUCTOR ) return MAX ( align , BITS_PER_WORD ) ; return align ; } </s>


<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < 512 > Key ; unsigned PreferVectorWidthOverride = 0 ; if ( F . hasFnAttribute ( "prefer-vector-width" ) ) { StringRef Val = F . getFnAttribute ( "prefer-vector-width" ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( 0 , Width ) ) { Key += "prefer-vector-width=" ; Key += Val ; PreferVectorWidthOverride = Width ; } } unsigned RequiredVectorWidth = UINT32_MAX ; if ( F . hasFnAttribute ( "min-legal-vector-width" ) ) { StringRef Val = F . getFnAttribute ( "min-legal-vector-width" ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( 0 , Width ) ) { Key += "min-legal-vector-width=" ; Key += Val ; RequiredVectorWidth = Width ; } } Key += CPU ; unsigned FSStart = Key . size ( ) ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) Key += FS . empty ( ) ? "+soft-float" : "+soft-float," ; Key += FS ; FS = Key . substr ( FSStart ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < X86Subtarget > ( TargetTriple , CPU , FS , * this , MaybeAlign ( Options . StackAlignmentOverride ) , PreferVectorWidthOverride , RequiredVectorWidth ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { unsigned Idx = IsLittleEndian ? i : 3 - i ; Data [ Offset + Idx ] |= uint8_t ( ( Value >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> static tree make_resolver_func ( const tree default_decl , const tree ifunc_alias_decl , basic_block * empty_bb ) { tree decl , type , t ; tree decl_name = clone_function_name ( default_decl , "resolver" ) ; const char * resolver_name = IDENTIFIER_POINTER ( decl_name ) ; type = build_function_type_list ( ptr_type_node , NULL_TREE ) ; decl = build_fn_decl ( resolver_name , type ) ; SET_DECL_ASSEMBLER_NAME ( decl , decl_name ) ; DECL_NAME ( decl ) = decl_name ; TREE_USED ( decl ) = 1 ; DECL_ARTIFICIAL ( decl ) = 1 ; DECL_IGNORED_P ( decl ) = 1 ; TREE_PUBLIC ( decl ) = 0 ; DECL_UNINLINABLE ( decl ) = 1 ; DECL_EXTERNAL ( decl ) = 0 ; DECL_EXTERNAL ( ifunc_alias_decl ) = 0 ; DECL_CONTEXT ( decl ) = NULL_TREE ; DECL_INITIAL ( decl ) = make_node ( BLOCK ) ; DECL_STATIC_CONSTRUCTOR ( decl ) = 0 ; if ( DECL_COMDAT_GROUP ( default_decl ) || TREE_PUBLIC ( default_decl ) ) { DECL_COMDAT ( decl ) = 1 ; make_decl_one_only ( decl , DECL_ASSEMBLER_NAME ( decl ) ) ; } else TREE_PUBLIC ( ifunc_alias_decl ) = 0 ; t = build_decl ( UNKNOWN_LOCATION , RESULT_DECL , NULL_TREE , ptr_type_node ) ; DECL_CONTEXT ( t ) = decl ; DECL_ARTIFICIAL ( t ) = 1 ; DECL_IGNORED_P ( t ) = 1 ; DECL_RESULT ( decl ) = t ; gimplify_function_tree ( decl ) ; push_cfun ( DECL_STRUCT_FUNCTION ( decl ) ) ; * empty_bb = init_lowered_empty_function ( decl , false , profile_count :: uninitialized ( ) ) ; cgraph_node :: add_new_function ( decl , true ) ; symtab -> call_cgraph_insertion_hooks ( cgraph_node :: get_create ( decl ) ) ; pop_cfun ( ) ; gcc_assert ( ifunc_alias_decl != NULL ) ; DECL_ATTRIBUTES ( ifunc_alias_decl ) = make_attribute ( "ifunc" , resolver_name , DECL_ATTRIBUTES ( ifunc_alias_decl ) ) ; cgraph_node :: create_same_body_alias ( ifunc_alias_decl , decl ) ; return decl ; } </s>

Make the resolver function decl to dispatch the versions of a multi- versioned function , DEFAULT_DECL . Create an empty basic block in the resolver and store the pointer in EMPTY_BB . Return the decl of the resolver function .


<s>
const
TargetRegisterClass
*
AVRRegisterInfo
::
getLargestLegalSuperClass
(
const
TargetRegisterClass
*
RC
,
const
MachineFunction
&
MF
)
const
{
if
(
RC
->
hasType
(
MVT
::
i16
)
)
{
return
&
AVR
::
DREGSRegClass
;
}
if
(
RC
->
hasType
(
MVT
::
i8
)
)
{
return
&
AVR
::
GPR8RegClass
;
}
llvm_unreachable
(
"Invalid register size"
)
;
}
</s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .


"Blackfin intrinsics are not overloaded"

Create or insert an LLVM Function declaration for an intrinsic , and return it .


<s> bool P2PassConfig :: addInstSelector ( ) { addPass ( createP2ISelDag ( getP2TargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>


<s> bool M680x0InstrInfo :: ExpandPUSH_POP ( MachineInstrBuilder & MIB , const MCInstrDesc & Desc , bool isPush ) const { MachineBasicBlock :: iterator I = MIB . getInstr ( ) ; I ++ ; MachineBasicBlock & MBB = * MIB -> getParent ( ) ; MachineOperand MO = MIB -> getOperand ( 0 ) ; DebugLoc DL = MIB -> getDebugLoc ( ) ; if ( isPush ) { BuildMI ( MBB , I , DL , Desc ) . addReg ( RI . getStackRegister ( ) ) . add ( MO ) ; } else { BuildMI ( MBB , I , DL , Desc , MO . getReg ( ) ) . addReg ( RI . getStackRegister ( ) ) ; } MIB -> eraseFromParent ( ) ; return true ; } </s>


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
READ_REGISTER
:
ExpandREAD_REGISTER
(
N
,
Results
,
DAG
)
;
break
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
case
ISD
::
SHL
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SREM
:
case
ISD
::
UREM
:
Res
=
LowerREM
(
N
,
DAG
)
;
break
;
case
ISD
::
SDIVREM
:
case
ISD
::
UDIVREM
:
Res
=
LowerDivRem
(
SDValue
(
N
,
0
)
,
DAG
)
;
assert
(
Res
.
getNumOperands
(
)
==
2
&&
"DivRem needs two values"
)
;
Results
.
push_back
(
Res
.
getValue
(
0
)
)
;
Results
.
push_back
(
Res
.
getValue
(
1
)
)
;
return
;
case
ISD
::
SADDSAT
:
case
ISD
::
SSUBSAT
:
case
ISD
::
UADDSAT
:
case
ISD
::
USUBSAT
:
Res
=
LowerADDSUBSAT
(
SDValue
(
N
,
0
)
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
READCYCLECOUNTER
:
ReplaceREADCYCLECOUNTER
(
N
,
Results
,
DAG
,
Subtarget
)
;
return
;
case
ISD
::
UDIV
:
case
ISD
::
SDIV
:
assert
(
Subtarget
->
isTargetWindows
(
)
&&
"can only expand DIV on Windows"
)
;
return
ExpandDIV_Windows
(
SDValue
(
N
,
0
)
,
DAG
,
N
->
getOpcode
(
)
==
ISD
::
SDIV
,
Results
)
;
case
ISD
::
ATOMIC_CMP_SWAP
:
ReplaceCMP_SWAP_64Results
(
N
,
Results
,
DAG
)
;
return
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
ReplaceLongIntrinsic
(
N
,
Results
,
DAG
)
;
case
ISD
::
LOAD
:
LowerLOAD
(
N
,
Results
,
DAG
)
;
break
;
case
ISD
::
TRUNCATE
:
Res
=
LowerTruncate
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SIGN_EXTEND
:
case
ISD
::
ZERO_EXTEND
:
Res
=
LowerVectorExtend
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
FP_TO_SINT_SAT
:
case
ISD
::
FP_TO_UINT_SAT
:
Res
=
LowerFP_TO_INT_SAT
(
SDValue
(
N
,
0
)
,
DAG
,
Subtarget
)
;
break
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> bool mprocTargetLowering :: isZExtFree ( EVT VT1 , EVT VT2 ) const { return 0 ; } </s>

Return true if zero-extending the specific node Val to type VT2 is free ( either because it 's implicitly zero-extended such as ARM ldrb / ldrh or because it 's folded such as X86 zero-extending loads ) .


<s> enum reg_class c6x_regno_reg_class ( int reg ) { if ( reg >= REG_A1 && reg <= REG_A2 ) return PREDICATE_A_REGS ; if ( reg == REG_A0 && TARGET_INSNS_64 ) return PREDICATE_A_REGS ; if ( reg >= REG_B0 && reg <= REG_B2 ) return PREDICATE_B_REGS ; if ( A_REGNO_P ( reg ) ) return NONPREDICATE_A_REGS ; if ( call_used_or_fixed_reg_p ( reg ) ) return CALL_USED_B_REGS ; return B_REGS ; } </s>


<s> void R600InstrInfo :: reserveIndirectRegisters ( BitVector & Reserved , const MachineFunction & MF ) const { const R600Subtarget & ST = MF . getSubtarget < R600Subtarget > ( ) ; const R600FrameLowering * TFL = ST . getFrameLowering ( ) ; unsigned StackWidth = TFL -> getStackWidth ( MF ) ; int End = getIndirectIndexEnd ( MF ) ; if ( End == - 1 ) return ; for ( int Index = getIndirectIndexBegin ( MF ) ; Index <= End ; ++ Index ) { unsigned SuperReg = AMDGPU :: R600_Reg128RegClass . getRegister ( Index ) ; Reserved . set ( SuperReg ) ; for ( unsigned Chan = 0 ; Chan < StackWidth ; ++ Chan ) { unsigned Reg = AMDGPU :: R600_TReg32RegClass . getRegister ( ( 4 * Index ) + Chan ) ; Reserved . set ( Reg ) ; } } } </s>

Reserve the registers that may be accessed using indirect addressing .


<s> void releaseMemory ( ) override { ShapeBBs . clear ( ) ; DefVisited . clear ( ) ; BBVisitedInfo . clear ( ) ; } </s>

releaseMemory ( ) - This member can be implemented by a pass if it wants to be able to release its memory when it is no longer needed .


<s> virtual bool isMem ( ) const LLVM_OVERRIDE { return Kind == KindMem ; } </s>


<s> int neon_immediate_valid_for_logic ( rtx op , machine_mode mode , int inverse , rtx * modconst , int * elementwidth ) { rtx tmpconst ; int tmpwidth ; int retval = simd_valid_immediate ( op , mode , inverse , & tmpconst , & tmpwidth ) ; if ( retval < 0 || retval > 5 ) return 0 ; if ( modconst ) * modconst = tmpconst ; if ( elementwidth ) * elementwidth = tmpwidth ; return 1 ; } </s>

Return TRUE if rtx X is legal for use in a VORR or VBIC instruction . If the immediate is valid , write a constant suitable for using as an operand to VORR/VBIC/VAND/VORN to * MODCONST and the corresponding element width to * ELEMENTWIDTH . See neon_valid_immediate for description of INVERSE .


<s> MSP430Subtarget :: MSP430Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : MSP430GenSubtargetInfo ( TT , CPU , FS ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM ) , TSInfo ( * TM . getDataLayout ( ) ) { } </s>

This constructor initializes the data members to match that of the specified triple .


<s> void mips_split_msa_copy_d ( rtx dest , rtx src , rtx index , rtx ( * gen_fn ) ( rtx , rtx , rtx ) ) { gcc_assert ( ( GET_MODE ( src ) == V2DImode && GET_MODE ( dest ) == DImode ) || ( GET_MODE ( src ) == V2DFmode && GET_MODE ( dest ) == DFmode ) ) ; rtx low = mips_subword ( dest , false ) ; rtx high = mips_subword ( dest , true ) ; rtx new_src = simplify_gen_subreg ( V4SImode , src , GET_MODE ( src ) , 0 ) ; emit_insn ( gen_fn ( low , new_src , GEN_INT ( INTVAL ( index ) * 2 ) ) ) ; emit_insn ( gen_fn ( high , new_src , GEN_INT ( INTVAL ( index ) * 2 + 1 ) ) ) ; } </s>

Split a COPY_S.D with operands DEST , SRC and INDEX . GEN is a function used to generate subregs .


<s>
static
void
riscv_print_operand
(
FILE
*
file
,
rtx
op
,
int
letter
)
{
enum
machine_mode
mode
=
GET_MODE
(
op
)
;
enum
rtx_code
code
=
GET_CODE
(
op
)
;
switch
(
letter
)
{
case
'h'
:
if
(
code
==
HIGH
)
op
=
XEXP
(
op
,
0
)
;
riscv_print_operand_reloc
(
file
,
op
,
true
)
;
break
;
case
'R'
:
riscv_print_operand_reloc
(
file
,
op
,
false
)
;
break
;
case
'C'
:
fputs
(
GET_RTX_NAME
(
code
)
,
file
)
;
break
;
case
'A'
:
if
(
riscv_memmodel_needs_amo_acquire
(
(
enum
memmodel
)
INTVAL
(
op
)
)
)
fputs
(
".aq"
,
file
)
;
break
;
case
'F'
:
if
(
riscv_memmodel_needs_release_fence
(
(
enum
memmodel
)
INTVAL
(
op
)
)
)
fputs
(
"fence iorw,ow; "
,
file
)
;
break
;
default
:
switch
(
code
)
{
case
REG
:
if
(
letter
&&
letter
!=
'z'
)
output_operand_lossage
(
"invalid use of '%%%c'"
,
letter
)
;
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
op
)
]
)
;
break
;
case
MEM
:
if
(
letter
&&
letter
!=
'z'
)
output_operand_lossage
(
"invalid use of '%%%c'"
,
letter
)
;
else
output_address
(
mode
,
XEXP
(
op
,
0
)
)
;
break
;
default
:
if
(
letter
==
'z'
&&
op
==
CONST0_RTX
(
GET_MODE
(
op
)
)
)
fputs
(
reg_names
[
GP_REG_FIRST
]
,
file
)
;
else
if
(
letter
&&
letter
!=
'z'
)
output_operand_lossage
(
"invalid use of '%%%c'"
,
letter
)
;
else
output_addr_const
(
file
,
riscv_strip_unspec_address
(
op
)
)
;
break
;
}
}
}
</s>

Implement TARGET_PRINT_OPERAND . The RISCV-specific operand codes are : ' h' Print the high-part relocation associated with OP , after stripping any outermost HIGH . ' R' Print the low-part relocation associated with OP . ' C' Print the integer branch condition for comparison OP . ' A' Print the atomic operation suffix for memory model OP . ' F' Print a FENCE if the memory model requires a release . ' z' Print x0 if OP is zero , otherwise print OP normally .

riscv
0
".aq"
"fence iorw,ow; "
"invalid use of '%%%c'"
"%s"
"invalid use of '%%%c'"
0
"invalid use of '%%%c'"


<s> void RISCVPassConfig :: addPreSched2 ( ) { } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> void ARMTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { unsigned BitWidth = Known . getBitWidth ( ) ; Known . resetAll ( ) ; switch ( Op . getOpcode ( ) ) { default : break ; case ARMISD :: ADDC : case ARMISD :: ADDE : case ARMISD :: SUBC : case ARMISD :: SUBE : if ( Op . getResNo ( ) == 0 ) break ; Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - 1 ) ; break ; case ARMISD :: CMOV : { DAG . computeKnownBits ( Op . getOperand ( 0 ) , Known , Depth + 1 ) ; if ( Known . isUnknown ( ) ) return ; KnownBits KnownRHS ; DAG . computeKnownBits ( Op . getOperand ( 1 ) , KnownRHS , Depth + 1 ) ; Known . Zero &= KnownRHS . Zero ; Known . One &= KnownRHS . One ; return ; } case ISD :: INTRINSIC_W_CHAIN : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ; Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case Intrinsic :: arm_ldaex : case Intrinsic :: arm_ldrex : { EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } } case ARMISD :: BFI : { DAG . computeKnownBits ( Op . getOperand ( 0 ) , Known , Depth + 1 ) ; ConstantSDNode * CI = cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ; const APInt & Mask = CI -> getAPIntValue ( ) ; Known . Zero &= Mask ; Known . One &= Mask ; return ; } } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> static int arc_address_cost ( rtx addr , machine_mode , addr_space_t , bool speed ) { switch ( GET_CODE ( addr ) ) { case REG : return speed || arc_check_short_reg_p ( addr ) ? 0 : 1 ; case PRE_INC : case PRE_DEC : case POST_INC : case POST_DEC : case PRE_MODIFY : case POST_MODIFY : return ! speed ; case LABEL_REF : case SYMBOL_REF : case CONST : if ( TARGET_NPS_CMEM && cmem_address ( addr , SImode ) ) return 0 ; return COSTS_N_INSNS ( 1 ) ; case PLUS : { rtx plus0 = XEXP ( addr , 0 ) ; rtx plus1 = XEXP ( addr , 1 ) ; if ( GET_CODE ( plus0 ) != REG && ( GET_CODE ( plus0 ) != MULT || ! CONST_INT_P ( XEXP ( plus0 , 1 ) ) || ( INTVAL ( XEXP ( plus0 , 1 ) ) != 2 && INTVAL ( XEXP ( plus0 , 1 ) ) != 4 ) ) ) break ; switch ( GET_CODE ( plus1 ) ) { case CONST_INT : return ( ! RTX_OK_FOR_OFFSET_P ( SImode , plus1 ) ? COSTS_N_INSNS ( 1 ) : speed ? 0 : ( arc_check_short_reg_p ( plus0 ) && satisfies_constraint_O ( plus1 ) ) ? 0 : 1 ) ; case REG : return ( speed < 1 ? 0 : ( arc_check_short_reg_p ( plus0 ) && arc_check_short_reg_p ( plus1 ) ) ? 0 : 1 ) ; case CONST : case SYMBOL_REF : case LABEL_REF : return COSTS_N_INSNS ( 1 ) ; default : break ; } break ; } default : break ; } return 4 ; } </s>

Provide the costs of an addressing mode that contains ADDR . If ADDR is not a valid address , its cost is irrelevant .


<s> static int ix86_avx_u128_mode_after ( int mode , rtx_insn * insn ) { rtx pat = PATTERN ( insn ) ; if ( vzeroupper_pattern ( pat , VOIDmode ) || vzeroall_pattern ( pat , VOIDmode ) ) return AVX_U128_CLEAN ; if ( CALL_P ( insn ) ) { bool avx_upper_reg_found = false ; note_stores ( pat , ix86_check_avx_upper_stores , & avx_upper_reg_found ) ; return avx_upper_reg_found ? AVX_U128_DIRTY : AVX_U128_CLEAN ; } return mode ; } </s>

Calculate mode of upper 128bit AVX registers after the insn .


<s> void FixupLEAPass :: processInstruction ( MachineBasicBlock :: iterator & I , MachineBasicBlock & MBB ) { MachineInstr & MI = * I ; const MCInstrDesc & Desc = MI . getDesc ( ) ; int AddrOffset = X86II :: getMemoryOperandNo ( Desc . TSFlags ) ; if ( AddrOffset >= 0 ) { AddrOffset += X86II :: getOperandBias ( Desc ) ; MachineOperand & p = MI . getOperand ( AddrOffset + X86 :: AddrBaseReg ) ; if ( p . isReg ( ) && p . getReg ( ) != X86 :: ESP ) { seekLEAFixup ( p , I , MBB ) ; } MachineOperand & q = MI . getOperand ( AddrOffset + X86 :: AddrIndexReg ) ; if ( q . isReg ( ) && q . getReg ( ) != X86 :: ESP ) { seekLEAFixup ( q , I , MBB ) ; } } } </s>

Process a single instruction and collect debug info anchors .


<s> MVT SITargetLowering :: getScalarShiftAmountTy ( EVT VT ) const { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> void apply ( ScheduleDAGInstrs * DAGInstrs ) override { ScheduleDAGMI * DAG = static_cast < ScheduleDAGMI * > ( DAGInstrs ) ; SUnit * SUa = nullptr ; for ( SUnit & SU : DAG -> SUnits ) { MachineInstr & MI2 = * SU . getInstr ( ) ; if ( ! MI2 . mayLoad ( ) && ! MI2 . mayStore ( ) ) { SUa = nullptr ; continue ; } if ( ! SUa ) { SUa = & SU ; continue ; } MachineInstr & MI1 = * SUa -> getInstr ( ) ; if ( ( TII -> isVMEM ( MI1 ) && TII -> isVMEM ( MI2 ) ) || ( TII -> isFLAT ( MI1 ) && TII -> isFLAT ( MI2 ) ) || ( TII -> isSMRD ( MI1 ) && TII -> isSMRD ( MI2 ) ) || ( TII -> isDS ( MI1 ) && TII -> isDS ( MI2 ) ) ) { SU . addPredBarrier ( SUa ) ; for ( const SDep & SI : SU . Preds ) { if ( SI . getSUnit ( ) != SUa ) SUa -> addPred ( SDep ( SI . getSUnit ( ) , SDep :: Artificial ) ) ; } if ( & SU != & DAG -> ExitSU ) { for ( const SDep & SI : SUa -> Succs ) { if ( SI . getSUnit ( ) != & SU ) SI . getSUnit ( ) -> addPred ( SDep ( & SU , SDep :: Artificial ) ) ; } } } SUa = & SU ; } } </s>

Apply the profile inference algorithm for a given function .


"The ABI for passing parameters with %d-byte"

Gives the alignment boundary , in bits , of an argument with the specified mode and type .


<s> bool AMDGPULowerIntrinsics :: makeLIDRangeMetadata ( Function & F ) const { if ( ! TM ) return false ; bool Changed = false ; const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( F ) ; for ( auto * U : F . users ( ) ) { auto * CI = dyn_cast < CallInst > ( U ) ; if ( ! CI ) continue ; Changed |= ST . makeLIDRangeMetadata ( CI ) ; } return Changed ; } </s>

Creates value range metadata on an workitemid . * intrinsic call or load .


<s> tree nds32_builtin_decl_impl ( unsigned code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= NDS32_BUILTIN_COUNT ) return error_mark_node ; return nds32_builtin_decls [ code ] ; } </s>


<s> int direct_return ( ) { if ( reload_completed ) { d30v_stack_t * info = d30v_stack_info ( ) ; if ( info -> total_size == 0 ) return 1 ; if ( info -> total_size == info -> vars_size && IN_RANGE_P ( info -> total_size , 1 , 31 ) ) return 1 ; } return 0 ; } </s>

Return non-zero if this function is known to have a null epilogue .


<s> int arc_get_unalign ( void ) { return cfun -> machine -> unalign ; } </s>

Accessor functions for cfun- > machine- > unalign .


<s> static int shcompact_byref ( const CUMULATIVE_ARGS * cum , machine_mode mode , const_tree type , bool named ) { unsigned HOST_WIDE_INT size ; if ( type ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; if ( cum -> arg_count [ SH_ARG_INT ] < NPARM_REGS ( SImode ) && ( ! named || GET_SH_ARG_CLASS ( mode ) == SH_ARG_INT || ( GET_SH_ARG_CLASS ( mode ) == SH_ARG_FLOAT && cum -> arg_count [ SH_ARG_FLOAT ] >= NPARM_REGS ( SFmode ) ) ) && size > 4 && ! SHCOMPACT_FORCE_ON_STACK ( mode , type ) && ! SH5_WOULD_BE_PARTIAL_NREGS ( * cum , mode , type , named ) ) return size ; else return 0 ; } </s>

Whether an argument must be passed by reference . On SHcompact , we pretend arguments wider than 32-bits that would have been passed in registers are passed by reference , so that an SHmedia trampoline loads them into the full 64-bits registers .


<s> static void arm_pre_atomic_barrier ( enum memmodel model ) { if ( need_atomic_barrier_p ( model , true ) ) emit_insn ( gen_memory_barrier ( ) ) ; } </s>

Emit a memory barrier around an atomic sequence according to MODEL .


<s> bool Mips16FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == Mips :: RA ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) MBB . addLiveIn ( Reg ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> const char * HexagonTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( HexagonISD :: NodeType ) Opcode ) { case HexagonISD :: ADDC : return "HexagonISD::ADDC" ; case HexagonISD :: SUBC : return "HexagonISD::SUBC" ; case HexagonISD :: ALLOCA : return "HexagonISD::ALLOCA" ; case HexagonISD :: AT_GOT : return "HexagonISD::AT_GOT" ; case HexagonISD :: AT_PCREL : return "HexagonISD::AT_PCREL" ; case HexagonISD :: BARRIER : return "HexagonISD::BARRIER" ; case HexagonISD :: CALL : return "HexagonISD::CALL" ; case HexagonISD :: CALLnr : return "HexagonISD::CALLnr" ; case HexagonISD :: CALLR : return "HexagonISD::CALLR" ; case HexagonISD :: COMBINE : return "HexagonISD::COMBINE" ; case HexagonISD :: CONST32_GP : return "HexagonISD::CONST32_GP" ; case HexagonISD :: CONST32 : return "HexagonISD::CONST32" ; case HexagonISD :: CP : return "HexagonISD::CP" ; case HexagonISD :: DCFETCH : return "HexagonISD::DCFETCH" ; case HexagonISD :: EH_RETURN : return "HexagonISD::EH_RETURN" ; case HexagonISD :: TSTBIT : return "HexagonISD::TSTBIT" ; case HexagonISD :: EXTRACTU : return "HexagonISD::EXTRACTU" ; case HexagonISD :: INSERT : return "HexagonISD::INSERT" ; case HexagonISD :: JT : return "HexagonISD::JT" ; case HexagonISD :: RET_FLAG : return "HexagonISD::RET_FLAG" ; case HexagonISD :: TC_RETURN : return "HexagonISD::TC_RETURN" ; case HexagonISD :: VASL : return "HexagonISD::VASL" ; case HexagonISD :: VASR : return "HexagonISD::VASR" ; case HexagonISD :: VLSR : return "HexagonISD::VLSR" ; case HexagonISD :: VSPLAT : return "HexagonISD::VSPLAT" ; case HexagonISD :: VEXTRACTW : return "HexagonISD::VEXTRACTW" ; case HexagonISD :: VINSERTW0 : return "HexagonISD::VINSERTW0" ; case HexagonISD :: VROR : return "HexagonISD::VROR" ; case HexagonISD :: READCYCLE : return "HexagonISD::READCYCLE" ; case HexagonISD :: VZERO : return "HexagonISD::VZERO" ; case HexagonISD :: VSPLATW : return "HexagonISD::VSPLATW" ; case HexagonISD :: D2P : return "HexagonISD::D2P" ; case HexagonISD :: P2D : return "HexagonISD::P2D" ; case HexagonISD :: V2Q : return "HexagonISD::V2Q" ; case HexagonISD :: Q2V : return "HexagonISD::Q2V" ; case HexagonISD :: QCAT : return "HexagonISD::QCAT" ; case HexagonISD :: QTRUE : return "HexagonISD::QTRUE" ; case HexagonISD :: QFALSE : return "HexagonISD::QFALSE" ; case HexagonISD :: TYPECAST : return "HexagonISD::TYPECAST" ; case HexagonISD :: VALIGN : return "HexagonISD::VALIGN" ; case HexagonISD :: VALIGNADDR : return "HexagonISD::VALIGNADDR" ; case HexagonISD :: OP_END : break ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

Hexagon Hexagon HexagonISD::NodeType HexagonISD::ADDC "HexagonISD::ADDC" HexagonISD::SUBC "HexagonISD::SUBC" HexagonISD::ALLOCA "HexagonISD::ALLOCA" HexagonISD::AT_GOT "HexagonISD::AT_GOT" HexagonISD::AT_PCREL "HexagonISD::AT_PCREL" HexagonISD::BARRIER "HexagonISD::BARRIER" HexagonISD::CALL "HexagonISD::CALL" HexagonISD::CALLnr "HexagonISD::CALLnr" HexagonISD::CALLR "HexagonISD::CALLR" HexagonISD::COMBINE "HexagonISD::COMBINE" HexagonISD::CONST32_GP "HexagonISD::CONST32_GP" HexagonISD::CONST32 "HexagonISD::CONST32" HexagonISD::CP "HexagonISD::CP" HexagonISD::DCFETCH "HexagonISD::DCFETCH" HexagonISD::EH_RETURN "HexagonISD::EH_RETURN" HexagonISD::TSTBIT "HexagonISD::TSTBIT" HexagonISD::EXTRACTU "HexagonISD::EXTRACTU" HexagonISD::INSERT "HexagonISD::INSERT" HexagonISD::JT "HexagonISD::JT" HexagonISD::RET_FLAG "HexagonISD::RET_FLAG" HexagonISD::TC_RETURN "HexagonISD::TC_RETURN" HexagonISD::VASL "HexagonISD::VASL" HexagonISD::VASR "HexagonISD::VASR" HexagonISD::VLSR "HexagonISD::VLSR" HexagonISD::VSPLAT "HexagonISD::VSPLAT" HexagonISD::VEXTRACTW "HexagonISD::VEXTRACTW" HexagonISD::VINSERTW0 "HexagonISD::VINSERTW0" HexagonISD::VROR "HexagonISD::VROR" HexagonISD::READCYCLE "HexagonISD::READCYCLE" HexagonISD::VZERO "HexagonISD::VZERO" HexagonISD::VSPLATW "HexagonISD::VSPLATW" HexagonISD::D2P "HexagonISD::D2P" HexagonISD::P2D "HexagonISD::P2D" HexagonISD::V2Q "HexagonISD::V2Q" HexagonISD::Q2V "HexagonISD::Q2V" HexagonISD::QCAT "HexagonISD::QCAT" HexagonISD::QTRUE "HexagonISD::QTRUE" HexagonISD::QFALSE "HexagonISD::QFALSE" HexagonISD::TYPECAST "HexagonISD::TYPECAST" HexagonISD::VALIGN "HexagonISD::VALIGN" HexagonISD::VALIGNADDR "HexagonISD::VALIGNADDR" HexagonISD::OP_END


<s>
void
CSKYInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
Register
SrcReg
,
bool
IsKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
CSKYMachineFunctionInfo
*
CFI
=
MF
.
getInfo
<
CSKYMachineFunctionInfo
>
(
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
unsigned
Opcode
=
0
;
if
(
CSKY
::
GPRRegClass
.
hasSubClassEq
(
RC
)
)
{
Opcode
=
CSKY
::
ST32W
;
}
else
if
(
CSKY
::
CARRYRegClass
.
hasSubClassEq
(
RC
)
)
{
Opcode
=
CSKY
::
SPILL_CARRY
;
CFI
->
setSpillsCR
(
)
;
}
else
{
llvm_unreachable
(
"Unknown RegisterClass"
)
;
}
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
,
MachineMemOperand
::
MOStore
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlign
(
FI
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opcode
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
IsKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool mips_pad_reg_upward ( machine_mode mode , tree type ) { if ( type != 0 ? FLOAT_TYPE_P ( type ) : GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return ! BYTES_BIG_ENDIAN ; return mips_pad_arg_upward ( mode , type ) ; } </s>

Likewise BLOCK_REG_PADDING ( MODE , TYPE , ... ) . Return ! BYTES_BIG_ENDIAN if the least significant byte of the register has useful data . Return the opposite if the most significant byte does .


<s> rtx frv_split_minmax ( rtx operands [ ] ) { rtx dest = operands [ 0 ] ; rtx minmax = operands [ 1 ] ; rtx src1 = operands [ 2 ] ; rtx src2 = operands [ 3 ] ; rtx cc_reg = operands [ 4 ] ; rtx cr_reg = operands [ 5 ] ; rtx ret ; enum rtx_code test_code ; machine_mode cr_mode = GET_MODE ( cr_reg ) ; start_sequence ( ) ; switch ( GET_CODE ( minmax ) ) { default : gcc_unreachable ( ) ; case SMIN : test_code = LT ; break ; case SMAX : test_code = GT ; break ; case UMIN : test_code = LTU ; break ; case UMAX : test_code = GTU ; break ; } emit_insn ( gen_rtx_SET ( cc_reg , gen_rtx_COMPARE ( GET_MODE ( cc_reg ) , src1 , src2 ) ) ) ; emit_insn ( gen_rtx_SET ( cr_reg , gen_rtx_fmt_ee ( test_code , GET_MODE ( cr_reg ) , cc_reg , const0_rtx ) ) ) ; if ( GET_CODE ( src2 ) == CONST_INT && INTVAL ( src2 ) != 0 ) { gcc_assert ( ! rtx_equal_p ( dest , src1 ) ) ; emit_move_insn ( dest , src2 ) ; emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_NE ( cr_mode , cr_reg , const0_rtx ) , gen_rtx_SET ( dest , src1 ) ) ) ; } else { if ( ! rtx_equal_p ( dest , src1 ) ) emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_NE ( cr_mode , cr_reg , const0_rtx ) , gen_rtx_SET ( dest , src1 ) ) ) ; if ( ! rtx_equal_p ( dest , src2 ) ) emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_EQ ( cr_mode , cr_reg , const0_rtx ) , gen_rtx_SET ( dest , src2 ) ) ) ; } ret = get_insns ( ) ; end_sequence ( ) ; return ret ; } </s>

Split a min/max operation returning a SEQUENCE containing all of the insns .


<s> bool alpha_expand_mov ( machine_mode mode , rtx * operands ) { rtx tmp ; if ( MEM_P ( operands [ 0 ] ) && ! reg_or_0_operand ( operands [ 1 ] , mode ) ) operands [ 1 ] = force_reg ( mode , operands [ 1 ] ) ; if ( mode == Pmode && symbolic_operand ( operands [ 1 ] , mode ) ) { tmp = alpha_legitimize_address_1 ( operands [ 1 ] , operands [ 0 ] , mode ) ; if ( tmp ) { if ( tmp == operands [ 0 ] ) return true ; operands [ 1 ] = tmp ; return false ; } } if ( ! CONSTANT_P ( operands [ 1 ] ) || input_operand ( operands [ 1 ] , mode ) ) return false ; if ( CONST_INT_P ( operands [ 1 ] ) || GET_CODE ( operands [ 1 ] ) == CONST_DOUBLE || GET_CODE ( operands [ 1 ] ) == CONST_VECTOR ) { if ( alpha_split_const_mov ( mode , operands ) ) return true ; } tmp = force_const_mem ( mode , operands [ 1 ] ) ; if ( tmp == NULL_RTX ) return false ; if ( reload_in_progress ) { emit_move_insn ( operands [ 0 ] , XEXP ( tmp , 0 ) ) ; operands [ 1 ] = replace_equiv_address ( tmp , operands [ 0 ] ) ; } else operands [ 1 ] = validize_mem ( tmp ) ; return false ; } </s>

Expand a move instruction ; return true if all work is done . We do n't handle non-bwx subword loads here .


<s> bool isReg ( ) const override { return Kind == k_Register ; } </s>


<s> static bool classof ( const MCExpr * E ) { return E -> getKind ( ) == MCExpr :: Target ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s>
void
VideoCore4AsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
VideoCore4MCInstLower
MCInstLowering
(
OutContext
,
*
Mang
,
*
this
)
;
SmallString
<
256
>
Str
;
raw_svector_ostream
O
(
Str
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
VideoCore4
::
BR_JT
:
{
auto
regName
=
VideoCore4InstPrinter
::
getRegisterName
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
;
unsigned
JTI
=
MI
->
getOperand
(
0
)
.
getIndex
(
)
;
const
MachineFunction
*
MF
=
MI
->
getParent
(
)
->
getParent
(
)
;
const
MachineJumpTableInfo
*
MJTI
=
MF
->
getJumpTableInfo
(
)
;
const
std
::
vector
<
MachineJumpTableEntry
>
&
JT
=
MJTI
->
getJumpTables
(
)
;
const
std
::
vector
<
MachineBasicBlock
*
>
&
JTBBs
=
JT
[
JTI
]
.
MBBs
;
O
<<
"\t# Inline jumptable on "
<<
regName
<<
"\n"
;
for
(
unsigned
i
=
0
,
e
=
JTBBs
.
size
(
)
;
i
!=
e
;
++
i
)
{
MachineBasicBlock
*
MBB
=
JTBBs
[
i
]
;
O
<<
"\t# Jumptable entry "
<<
i
<<
"\n"
;
O
<<
"\tcmp "
<<
regName
<<
", "
<<
i
<<
"\n"
;
O
<<
"\tbeq "
<<
*
MBB
->
getSymbol
(
)
<<
"\n"
;
}
OutStreamer
.
EmitRawText
(
O
.
str
(
)
)
;
return
;
}
}
MCInst
TmpInst
;
MCInstLowering
.
Lower
(
MI
,
TmpInst
)
;
EmitToStreamer
(
OutStreamer
,
TmpInst
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void LEGRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { MachineInstr & MI = * II ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ; unsigned FI = FIOp . getIndex ( ) ; unsigned ImmOpIdx = 0 ; switch ( MI . getOpcode ( ) ) { default : return ; case LEG :: LDR : case LEG :: STR : ImmOpIdx = FIOperandNum + 1 ; break ; } MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ; int Offset = MFI -> getObjectOffset ( FI ) + MFI -> getStackSize ( ) + ImmOp . getImm ( ) ; FIOp . ChangeToRegister ( LEG :: SP , false ) ; ImmOp . setImm ( Offset ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool AVRTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { int64_t Offs = AM . BaseOffs ; if ( AM . BaseGV && ! AM . HasBaseReg && AM . Scale == 0 && Offs == 0 ) { return true ; } if ( isa < PointerType > ( Ty ) && AS == AVR :: ProgramMemory ) { return false ; } if ( Offs < 0 ) Offs = - Offs ; if ( AM . BaseGV == 0 && AM . HasBaseReg && AM . Scale == 0 && isUInt < 6 > ( Offs ) ) { return true ; } return false ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s>
void
arm_declare_function_name
(
FILE
*
stream
,
const
char
*
name
,
tree
decl
)
{
fprintf
(
stream
,
"\t.syntax unified\n"
)
;
if
(
TARGET_THUMB
)
{
if
(
is_called_in_ARM_mode
(
decl
)
||
(
TARGET_THUMB1
&&
!
TARGET_THUMB1_ONLY
&&
cfun
->
is_thunk
)
)
fprintf
(
stream
,
"\t.code 32\n"
)
;
else
if
(
TARGET_THUMB1
)
fprintf
(
stream
,
"\t.code\t16\n\t.thumb_func\n"
)
;
else
fprintf
(
stream
,
"\t.thumb\n\t.thumb_func\n"
)
;
}
else
fprintf
(
stream
,
"\t.arm\n"
)
;
asm_fprintf
(
asm_out_file
,
"\t.fpu %s\n"
,
(
TARGET_SOFT_FLOAT
"softvfp"
:
arm_identify_fpu_from_isa
(
arm_active_target
.
isa
)
)
)
;
if
(
TARGET_POKE_FUNCTION_NAME
)
arm_poke_function_name
(
stream
,
(
const
char
*
)
name
)
;
}
</s>

Implement ASM_DECLARE_FUNCTION_NAME . Output the ISA features used by the function fndecl .


<s>
static
void
arm_unwind_emit_stm
(
FILE
*
asm_out_file
,
rtx
p
)
{
int
i
;
HOST_WIDE_INT
offset
;
HOST_WIDE_INT
nregs
;
int
reg_size
;
unsigned
reg
;
unsigned
lastreg
;
rtx
e
;
e
=
XVECEXP
(
p
,
0
,
0
)
;
if
(
GET_CODE
(
e
)
!=
SET
||
GET_CODE
(
XEXP
(
e
,
0
)
)
!=
REG
||
REGNO
(
XEXP
(
e
,
0
)
)
!=
SP_REGNUM
||
GET_CODE
(
XEXP
(
e
,
1
)
)
!=
PLUS
)
abort
(
)
;
offset
=
INTVAL
(
XEXP
(
XEXP
(
e
,
1
)
,
1
)
)
;
nregs
=
XVECLEN
(
p
,
0
)
1
;
reg
=
REGNO
(
XEXP
(
XVECEXP
(
p
,
0
,
1
)
,
1
)
)
;
if
(
reg
<
16
)
{
if
(
nregs
*
4
==
offset
4
)
{
fprintf
(
asm_out_file
,
"\t.pad #4\n"
)
;
offset
-=
4
;
}
reg_size
=
4
;
}
else
if
(
IS_VFP_REGNUM
(
reg
)
)
{
offset
-=
4
;
reg_size
=
8
;
}
else
if
(
reg
>=
FIRST_FPA_REGNUM
&&
reg
<=
LAST_FPA_REGNUM
)
{
asm_fprintf
(
asm_out_file
,
"\t.save %r, %wd\n"
,
reg
,
nregs
)
;
return
;
}
else
abort
(
)
;
if
(
offset
!=
nregs
*
reg_size
)
abort
(
)
;
fprintf
(
asm_out_file
,
"\t.save {"
)
;
offset
=
0
;
lastreg
=
0
;
for
(
i
=
1
;
i
<=
nregs
;
i
++
)
{
e
=
XVECEXP
(
p
,
0
,
i
)
;
if
(
GET_CODE
(
e
)
!=
SET
||
GET_CODE
(
XEXP
(
e
,
0
)
)
!=
MEM
||
GET_CODE
(
XEXP
(
e
,
1
)
)
!=
REG
)
abort
(
)
;
reg
=
REGNO
(
XEXP
(
e
,
1
)
)
;
if
(
reg
<
lastreg
)
abort
(
)
;
if
(
i
!=
1
)
fprintf
(
asm_out_file
,
", "
)
;
if
(
IS_VFP_REGNUM
(
reg
)
)
asm_fprintf
(
asm_out_file
,
"d%d"
,
(
reg
FIRST_VFP_REGNUM
)
/
2
)
;
else
asm_fprintf
(
asm_out_file
,
"%r"
,
reg
)
;
e
=
XEXP
(
XEXP
(
e
,
0
)
,
0
)
;
if
(
GET_CODE
(
e
)
==
PLUS
)
{
offset
+=
reg_size
;
if
(
GET_CODE
(
XEXP
(
e
,
0
)
)
!=
REG
||
REGNO
(
XEXP
(
e
,
0
)
)
!=
SP_REGNUM
||
GET_CODE
(
XEXP
(
e
,
1
)
)
!=
CONST_INT
||
offset
!=
INTVAL
(
XEXP
(
e
,
1
)
)
)
abort
(
)
;
}
else
if
(
i
!=
1
||
GET_CODE
(
e
)
!=
REG
||
REGNO
(
e
)
!=
SP_REGNUM
)
abort
(
)
;
}
fprintf
(
asm_out_file
,
"}\n"
)
;
}
</s>

Emit unwind directives for a store-multiple instruction . This should only ever be generated by the function prologue code , so we expect it to have a particular form .


<s> static void mips_sim_issue_insn ( struct mips_sim * state , rtx_insn * insn ) { curr_state = state -> dfa_state ; state_transition ( curr_state , insn ) ; state -> insns_left = targetm . sched . variable_issue ( 0 , false , insn , state -> insns_left ) ; mips_sim_insn = insn ; note_stores ( PATTERN ( insn ) , mips_sim_record_set , state ) ; } </s>

Issue instruction INSN in scheduler state STATE . Assume that INSN can issue immediately ( i.e. , that mips_sim_wait_insn has already been called ) .


<s> ScheduleHazardRecognizer :: HazardType GCNHazardRecognizer :: getHazardType ( SUnit * SU , int Stalls ) { MachineInstr * MI = SU -> getInstr ( ) ; if ( SIInstrInfo :: isSMRD ( * MI ) && checkSMRDHazards ( MI ) > 0 ) return NoopHazard ; if ( ( SIInstrInfo :: isVMEM ( * MI ) || SIInstrInfo :: isFLAT ( * MI ) ) && checkVMEMHazards ( MI ) > 0 ) return NoopHazard ; if ( SIInstrInfo :: isVALU ( * MI ) && checkVALUHazards ( MI ) > 0 ) return NoopHazard ; if ( SIInstrInfo :: isDPP ( * MI ) && checkDPPHazards ( MI ) > 0 ) return NoopHazard ; if ( isDivFMas ( MI -> getOpcode ( ) ) && checkDivFMasHazards ( MI ) > 0 ) return NoopHazard ; if ( isRWLane ( MI -> getOpcode ( ) ) && checkRWLaneHazards ( MI ) > 0 ) return NoopHazard ; if ( isSGetReg ( MI -> getOpcode ( ) ) && checkGetRegHazards ( MI ) > 0 ) return NoopHazard ; if ( isSSetReg ( MI -> getOpcode ( ) ) && checkSetRegHazards ( MI ) > 0 ) return NoopHazard ; if ( isRFE ( MI -> getOpcode ( ) ) && checkRFEHazards ( MI ) > 0 ) return NoopHazard ; if ( ST . hasReadM0MovRelInterpHazard ( ) && ( TII . isVINTRP ( * MI ) || isSMovRel ( MI -> getOpcode ( ) ) ) && checkReadM0Hazards ( MI ) > 0 ) return NoopHazard ; if ( ST . hasReadM0SendMsgHazard ( ) && isSendMsgTraceDataOrGDS ( * MI ) && checkReadM0Hazards ( MI ) > 0 ) return NoopHazard ; if ( checkAnyInstHazards ( MI ) > 0 ) return NoopHazard ; return NoHazard ; } </s>

getHazardType - Return the hazard type of emitting this node .


<s> outliner :: InstrType RISCVInstrInfo :: getOutliningType ( MachineBasicBlock :: iterator & MBBI , unsigned Flags ) const { MachineInstr & MI = * MBBI ; MachineBasicBlock * MBB = MI . getParent ( ) ; const TargetRegisterInfo * TRI = MBB -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; if ( MI . isPosition ( ) ) { if ( MI . isCFIInstruction ( ) ) return outliner :: InstrType :: Invisible ; return outliner :: InstrType :: Illegal ; } if ( MI . isInlineAsm ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . isTerminator ( ) && ! MBB -> succ_empty ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . isReturn ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . modifiesRegister ( RISCV :: X5 , TRI ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( RISCV :: X5 ) ) return outliner :: InstrType :: Illegal ; for ( const auto & MO : MI . operands ( ) ) if ( MO . isMBB ( ) || MO . isBlockAddress ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . isMetaInstruction ( ) ) return outliner :: InstrType :: Invisible ; return outliner :: InstrType :: Legal ; } </s>

Returns how or if MIT should be outlined .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
(
Kind
==
k_Register
)
&&
"Invalid access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s>
char
*
output_cbranch
(
rtx
op
,
const
char
*
label
,
int
reversed
,
rtx
insn
)
{
static
char
string
[
64
]
;
enum
rtx_code
code
=
GET_CODE
(
op
)
;
rtx
cc_reg
=
XEXP
(
op
,
0
)
;
enum
machine_mode
mode
=
GET_MODE
(
cc_reg
)
;
int
cc_regno
=
REGNO
(
cc_reg
)
CR0_REGNO
;
int
need_longbranch
=
label
!=
&&
get_attr_length
(
insn
)
==
8
;
int
really_reversed
=
reversed
^
need_longbranch
;
char
*
s
=
string
;
const
char
*
ccode
;
const
char
*
pred
;
rtx
note
;
validate_condition_mode
(
code
,
mode
)
;
if
(
really_reversed
)
{
if
(
mode
==
CCFPmode
)
code
=
reverse_condition_maybe_unordered
(
code
)
;
else
code
=
reverse_condition
(
code
)
;
}
if
(
(
TARGET_E500
&&
!
TARGET_FPRS
&&
TARGET_HARD_FLOAT
)
&&
mode
==
CCFPmode
)
{
switch
(
code
)
{
case
EQ
:
code
=
GT
;
break
;
case
NE
:
code
=
UNLE
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
switch
(
code
)
{
case
NE
:
case
LTGT
:
ccode
=
"ne"
;
break
;
case
EQ
:
case
UNEQ
:
ccode
=
"eq"
;
break
;
case
GE
:
case
GEU
:
ccode
=
"ge"
;
break
;
case
GT
:
case
GTU
:
case
UNGT
:
ccode
=
"gt"
;
break
;
case
LE
:
case
LEU
:
ccode
=
"le"
;
break
;
case
LT
:
case
LTU
:
case
UNLT
:
ccode
=
"lt"
;
break
;
case
UNORDERED
:
ccode
=
"un"
;
break
;
case
ORDERED
:
ccode
=
"nu"
;
break
;
case
UNGE
:
ccode
=
"nl"
;
break
;
case
UNLE
:
ccode
=
"ng"
;
break
;
default
:
gcc_unreachable
(
)
;
}
pred
=
""
;
note
=
find_reg_note
(
insn
,
REG_BR_PROB
,
NULL_RTX
)
;
if
(
note
!=
NULL_RTX
)
{
int
prob
=
INTVAL
(
XEXP
(
note
,
0
)
)
REG_BR_PROB_BASE
/
2
;
if
(
rs6000_always_hint
||
abs
(
prob
)
>
REG_BR_PROB_BASE
/
100
*
48
)
{
if
(
abs
(
prob
)
>
REG_BR_PROB_BASE
/
20
&&
(
(
prob
>
0
)
^
need_longbranch
)
)
pred
=
"+"
;
else
pred
=
"-"
;
}
}
if
(
label
==
)
s
+=
sprintf
(
s
,
"{b%sr|b%slr%s} "
,
ccode
,
ccode
,
pred
)
;
else
s
+=
sprintf
(
s
,
"{b%s|b%s%s} "
,
ccode
,
ccode
,
pred
)
;
if
(
reg_names
[
cc_regno
+
CR0_REGNO
]
[
0
]
==
'%'
)
*
s
++
=
'%'
;
s
+=
sprintf
(
s
,
"%s"
,
reg_names
[
cc_regno
+
CR0_REGNO
]
)
;
if
(
label
!=
)
{
if
(
need_longbranch
)
s
+=
sprintf
(
s
,
",$+8\n\tb %s"
,
label
)
;
else
s
+=
sprintf
(
s
,
",%s"
,
label
)
;
}
return
string
;
}
</s>

Output a conditional branch to LABEL . CODE is the comparison code . CC_MODE is the mode of the CC register . REVERSED is non-zero if we should reverse the sense of the comparison . INSN is the instruction .


"Not all fixup kinds added to Infos array"


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> static bool riscv_pass_by_reference ( cumulative_args_t cum_v , const function_arg_info & arg ) { HOST_WIDE_INT size = arg . type_size_in_bytes ( ) . to_constant ( ) ; ; struct riscv_arg_info info ; CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( cum != NULL ) { riscv_get_arg_info ( & info , cum , arg . mode , arg . type , arg . named , false ) ; if ( info . num_fprs ) return false ; } return ! IN_RANGE ( size , 0 , 2 * UNITS_PER_WORD ) ; } </s>


<s> rtx pa_get_deferred_plabel ( rtx symbol ) { const char * fname = XSTR ( symbol , 0 ) ; size_t i ; for ( i = 0 ; i < n_deferred_plabels ; i ++ ) if ( strcmp ( fname , XSTR ( deferred_plabels [ i ] . symbol , 0 ) ) == 0 ) break ; if ( deferred_plabels == NULL || i == n_deferred_plabels ) { tree id ; if ( deferred_plabels == 0 ) deferred_plabels = ggc_alloc < deferred_plabel > ( ) ; else deferred_plabels = GGC_RESIZEVEC ( struct deferred_plabel , deferred_plabels , n_deferred_plabels + 1 ) ; i = n_deferred_plabels ++ ; deferred_plabels [ i ] . internal_label = gen_label_rtx ( ) ; deferred_plabels [ i ] . symbol = symbol ; id = maybe_get_identifier ( targetm . strip_name_encoding ( fname ) ) ; if ( id ) mark_referenced ( id ) ; } return deferred_plabels [ i ] . internal_label ; } </s>

Search the deferred plabel list for SYMBOL and return its internal label . If an entry for SYMBOL is not found , a new entry is created .


<s> DFAPacketizer * HexagonInstrInfo :: CreateTargetScheduleState ( const TargetSubtargetInfo & STI ) const { const InstrItineraryData * II = STI . getInstrItineraryData ( ) ; return static_cast < const HexagonSubtarget & > ( STI ) . createDFAPacketizer ( II ) ; } </s>

Create machine specific model for scheduling .


<s> static int tilegx_saved_regs_size ( void ) { int reg_save_size = 0 ; int regno ; int offset_to_frame ; int align_mask ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( need_to_save_reg ( regno ) ) reg_save_size += UNITS_PER_WORD ; offset_to_frame = crtl -> args . pretend_args_size + reg_save_size ; align_mask = ( STACK_BOUNDARY / BITS_PER_UNIT ) - 1 ; reg_save_size += ( - offset_to_frame ) & align_mask ; return reg_save_size ; } </s>

Return the size of the register savev area . This function is only correct starting with local register allocation


<s> bool HexagonMCChecker :: check ( bool FullCheck ) { bool chkB = checkBranches ( ) ; bool chkP = checkPredicates ( ) ; bool chkNV = checkNewValues ( ) ; bool chkR = checkRegisters ( ) ; bool chkRRO = checkRegistersReadOnly ( ) ; bool chkELB = checkEndloopBranches ( ) ; checkRegisterCurDefs ( ) ; bool chkS = checkSolo ( ) ; bool chkSh = true ; if ( FullCheck ) chkSh = checkShuffle ( ) ; bool chkSl = true ; if ( FullCheck ) chkSl = checkSlots ( ) ; bool chkAXOK = checkAXOK ( ) ; bool chk = chkB && chkP && chkNV && chkR && chkRRO && chkELB && chkS && chkSh && chkSl && chkAXOK ; return chk ; } </s>

Check if the constraints are satisfiable .


<s> bool AArch64AsmParser :: ParseDirective ( AsmToken DirectiveID ) { const MCObjectFileInfo :: Environment Format = getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ; bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; bool IsCOFF = Format == MCObjectFileInfo :: IsCOFF ; StringRef IDVal = DirectiveID . getIdentifier ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == ".arch" ) return parseDirectiveArch ( Loc ) ; if ( IDVal == ".cpu" ) return parseDirectiveCPU ( Loc ) ; if ( IDVal == ".hword" ) return parseDirectiveWord ( 2 , Loc ) ; if ( IDVal == ".word" ) return parseDirectiveWord ( 4 , Loc ) ; if ( IDVal == ".xword" ) return parseDirectiveWord ( 8 , Loc ) ; if ( IDVal == ".tlsdesccall" ) return parseDirectiveTLSDescCall ( Loc ) ; if ( IDVal == ".ltorg" || IDVal == ".pool" ) return parseDirectiveLtorg ( Loc ) ; if ( IDVal == ".unreq" ) return parseDirectiveUnreq ( Loc ) ; if ( ! IsMachO && ! IsCOFF ) { if ( IDVal == ".inst" ) return parseDirectiveInst ( Loc ) ; } return parseDirectiveLOH ( IDVal , Loc ) ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s>
const
char
*
avr_out_sbxx_branch
(
rtx
insn
,
rtx
operands
[
]
)
{
enum
rtx_code
comp
=
GET_CODE
(
operands
[
0
]
)
;
int
long_jump
=
(
get_attr_length
(
insn
)
>=
4
)
;
int
reverse
=
long_jump
||
jump_over_one_insn_p
(
insn
,
operands
[
3
]
)
;
if
(
comp
==
GE
)
comp
=
EQ
;
else
if
(
comp
==
LT
)
comp
=
NE
;
if
(
reverse
)
comp
=
reverse_condition
(
comp
)
;
if
(
GET_CODE
(
operands
[
1
]
)
==
CONST_INT
)
{
if
(
INTVAL
(
operands
[
1
]
)
<
0x40
)
{
if
(
comp
==
EQ
)
output_asm_insn
(
AS2
(
sbis
,
%
1
0x20
,
%
2
)
,
operands
)
;
else
output_asm_insn
(
AS2
(
sbic
,
%
1
0x20
,
%
2
)
,
operands
)
;
}
else
{
output_asm_insn
(
AS2
(
in
,
__tmp_reg__
,
%
1
0x20
)
,
operands
)
;
if
(
comp
==
EQ
)
output_asm_insn
(
AS2
(
sbrs
,
__tmp_reg__
,
%
2
)
,
operands
)
;
else
output_asm_insn
(
AS2
(
sbrc
,
__tmp_reg__
,
%
2
)
,
operands
)
;
}
}
else
{
if
(
GET_MODE
(
operands
[
1
]
)
==
QImode
)
{
if
(
comp
==
EQ
)
output_asm_insn
(
AS2
(
sbrs
,
%
1
,
%
2
)
,
operands
)
;
else
output_asm_insn
(
AS2
(
sbrc
,
%
1
,
%
2
)
,
operands
)
;
}
else
{
static
char
buf
[
]
=
"sbrc %A1,0"
;
int
bit_nr
=
exact_log2
(
INTVAL
(
operands
[
2
]
)
&
GET_MODE_MASK
(
GET_MODE
(
operands
[
1
]
)
)
)
;
buf
[
3
]
=
(
comp
==
EQ
)
's'
:
'c'
;
buf
[
6
]
=
'A'
+
(
bit_nr
>>
3
)
;
buf
[
9
]
=
'0'
+
(
bit_nr
&
7
)
;
output_asm_insn
(
buf
,
operands
)
;
}
}
if
(
long_jump
)
return
(
AS1
(
rjmp
,
.
+
4
)
CR_TAB
AS1
(
jmp
,
%
3
)
)
;
if
(
!
reverse
)
return
AS1
(
rjmp
,
%
3
)
;
return
""
;
}
</s>

Output a branch that tests a single bit of a register ( QI , HI or SImode ) or memory location in the I/O space ( QImode only ) . Operand 0 : comparison operator ( must be EQ or NE , compare bit to zero ) . Operand 1 : register operand to test , or CONST_INT memory address . Operand 2 : bit number ( for QImode operand ) or mask ( HImode , SImode ) . Operand 3 : label to jump to if the test is true .


<s>
void
print
(
raw_ostream
&
O
)
const
override
{
switch
(
Kind
)
{
case
k_Token
:
O
<<
"Token: \""
<<
getToken
(
)
<<
"\""
;
break
;
case
k_Register
:
O
<<
"Register: "
<<
getReg
(
)
;
break
;
case
k_Immediate
:
O
<<
"Immediate: \""
<<
*
getImm
(
)
<<
"\""
;
break
;
case
k_Memri
:
{
O
<<
"Memri: \""
<<
getReg
(
)
<<
'+'
<<
*
getImm
(
)
<<
"\""
;
break
;
}
}
O
<<
"\n"
;
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> const uint16_t * TOYRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { TOY :: LR , TOY :: R2 , TOY :: R3 } ; return CalleeSavedRegs ; } </s>


<s> static void pdp11_asm_print_operand ( FILE * file , rtx x , int code ) { long sval [ 2 ] ; if ( code == '#' ) fprintf ( file , "#" ) ; else if ( code == '@' ) { if ( TARGET_UNIX_ASM ) fprintf ( file , "*" ) ; else fprintf ( file , "@" ) ; } else if ( GET_CODE ( x ) == REG ) fprintf ( file , "%s" , reg_names [ REGNO ( x ) ] ) ; else if ( GET_CODE ( x ) == MEM ) output_address ( GET_MODE ( x ) , XEXP ( x , 0 ) ) ; else if ( GET_CODE ( x ) == CONST_DOUBLE && GET_MODE ( x ) != SImode ) { REAL_VALUE_TO_TARGET_DOUBLE ( * CONST_DOUBLE_REAL_VALUE ( x ) , sval ) ; fprintf ( file , "$%#lo" , sval [ 0 ] >> 16 ) ; } else { putc ( '$' , file ) ; output_addr_const_pdp11 ( file , x ) ; } } </s>

Special format operators handled here : # -- output the correct immediate operand marker for the assembler dialect . @ -- output the correct indirect marker for the assembler dialect . o -- emit a constant value as a number ( not an immediate operand ) in octal .


<s> inline bool BitTracker :: has ( unsigned Reg ) const { return Map . find ( Reg ) != Map . end ( ) ; } </s>

Tests whether a library function is available .


<s> BitVector Cpu0RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t ReservedCPURegs [ ] = { Cpu0 :: ZERO , Cpu0 :: AT , Cpu0 :: SP , Cpu0 :: LR , Cpu0 :: PC } ; BitVector Reserved ( getNumRegs ( ) ) ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; const Cpu0MachineFunctionInfo * Cpu0FI = MF . getInfo < Cpu0MachineFunctionInfo > ( ) ; if ( Cpu0FI -> globalBaseRegFixed ( ) ) Reserved . set ( Cpu0 :: GP ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


"Replacing load %d with permuted load\n"

Convert the non-permuting load INSN to a permuting one .


<s> static int mn10300_arg_partial_bytes ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , bool named ATTRIBUTE_UNUSED ) { int size , align ; int nregs = 2 ; if ( mode == BLKmode ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; align = size ; cum -> nbytes = ( cum -> nbytes + 3 ) & ~ 3 ; if ( cum -> nbytes > nregs * UNITS_PER_WORD ) return 0 ; if ( cum -> nbytes + size <= nregs * UNITS_PER_WORD ) return 0 ; if ( type == NULL_TREE && cum -> nbytes + size > nregs * UNITS_PER_WORD ) return 0 ; return nregs * UNITS_PER_WORD - cum -> nbytes ; } </s>

Return the number of bytes of registers to use for an argument passed partially in registers and partially in memory .


<s> bool ARMTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , Align Alignment , MachineMemOperand :: Flags , bool * Fast ) const { if ( ! VT . isSimple ( ) ) return false ; bool AllowsUnaligned = Subtarget -> allowsUnalignedMem ( ) ; auto Ty = VT . getSimpleVT ( ) . SimpleTy ; if ( Ty == MVT :: i8 || Ty == MVT :: i16 || Ty == MVT :: i32 ) { if ( AllowsUnaligned ) { if ( Fast ) * Fast = Subtarget -> hasV7Ops ( ) ; return true ; } } if ( Ty == MVT :: f64 || Ty == MVT :: v2f64 ) { if ( Subtarget -> hasNEON ( ) && ( AllowsUnaligned || Subtarget -> isLittle ( ) ) ) { if ( Fast ) * Fast = true ; return true ; } } if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; if ( ( Ty == MVT :: v16i1 || Ty == MVT :: v8i1 || Ty == MVT :: v4i1 || Ty == MVT :: v2i1 ) ) { if ( Fast ) * Fast = true ; return true ; } if ( ( Ty == MVT :: v4i8 || Ty == MVT :: v8i8 || Ty == MVT :: v4i16 ) && Alignment >= VT . getScalarSizeInBits ( ) / 8 ) { if ( Fast ) * Fast = true ; return true ; } if ( Ty == MVT :: v16i8 || Ty == MVT :: v8i16 || Ty == MVT :: v8f16 || Ty == MVT :: v4i32 || Ty == MVT :: v4f32 || Ty == MVT :: v2i64 || Ty == MVT :: v2f64 ) { if ( Fast ) * Fast = true ; return true ; } return false ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> std :: string getName ( ) { return Name ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> static bool classof ( const MCStreamer * S ) { return S -> getKind ( ) == SK_ARMELFStreamer ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


"Should be loading %r15 and something else"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s>
SDValue
PatmosTargetLowering
::
LowerCall
(
CallLoweringInfo
&
CLI
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
CLI
.
IsTailCall
=
false
;
switch
(
CLI
.
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
CLI
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .

Patmos
Patmos
"Unsupported calling convention"


<s>
MCSymbol
*
MSP430MCInstLower
::
GetExternalSymbolSymbol
(
const
MachineOperand
&
MO
)
const
{
switch
(
MO
.
getTargetFlags
(
)
)
{
default
:
llvm_unreachable
(
"Unknown target flag on GV operand"
)
;
case
0
:
break
;
}
return
Printer
.
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
;
}
</s>

Return the MCSymbol for the specified ExternalSymbol .


<s> int includes_rshift_p ( rtx shiftop , rtx andop ) { unsigned HOST_WIDE_INT shift_mask = ~ ( unsigned HOST_WIDE_INT ) 0 ; shift_mask >>= INTVAL ( shiftop ) ; return ( INTVAL ( andop ) & 0xffffffff & ~ shift_mask ) == 0 ; } </s>


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"MBlaze Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"P2 DAG->DAG Pattern Instruction Selection"


<s> void SNESFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> unsigned getNumFixupKinds ( ) const { return ARM64 :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> bool JVMAsmBackend :: mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> static int arc_compute_millicode_save_restore_regs ( unsigned int gmask , struct arc_frame_info * frame ) { int regno ; int start_reg = 13 , end_reg = 25 ; for ( regno = start_reg ; regno <= end_reg && ( gmask & ( 1L << regno ) ) ; ) regno ++ ; end_reg = regno - 1 ; if ( regno - start_reg >= 3 - ( crtl -> is_leaf == 0 ) ) { frame -> millicode_start_reg = 13 ; frame -> millicode_end_reg = regno - 1 ; return 1 ; } return 0 ; } </s>

Return non-zero if there are registers to be saved or loaded using millicode thunks . We can only use consecutive sequences starting with r13 , and not going beyond r25 . GMASK is a bitmask of registers to save . This function sets FRAME- > millicod_start_reg .. FRAME- > millicode_end_reg to the range of registers to be saved / restored with a millicode call .


<s> void SparcDAGToDAGISel :: Select ( SDNode * N ) { SDLoc dl ( N ) ; if ( N -> isMachineOpcode ( ) ) { N -> setNodeId ( - 1 ) ; return ; } switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: INLINEASM : { if ( tryInlineAsm ( N ) ) return ; break ; } case SPISD :: GLOBAL_BASE_REG : ReplaceNode ( N , getGlobalBaseReg ( ) ) ; return ; case ISD :: SDIV : case ISD :: UDIV : { if ( N -> getValueType ( 0 ) == MVT :: i64 ) break ; SDValue DivLHS = N -> getOperand ( 0 ) ; SDValue DivRHS = N -> getOperand ( 1 ) ; SDValue TopPart ; if ( N -> getOpcode ( ) == ISD :: SDIV ) { TopPart = SDValue ( CurDAG -> getMachineNode ( SP :: SRAri , dl , MVT :: i32 , DivLHS , CurDAG -> getTargetConstant ( 31 , dl , MVT :: i32 ) ) , 0 ) ; } else { TopPart = CurDAG -> getRegister ( SP :: G0 , MVT :: i32 ) ; } TopPart = CurDAG -> getCopyToReg ( CurDAG -> getEntryNode ( ) , dl , SP :: Y , TopPart , SDValue ( ) ) . getValue ( 1 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: SDIV ? SP :: SDIVrr : SP :: UDIVrr ; if ( ( ( SparcTargetMachine & ) TM ) . getSubtargetImpl ( ) -> performSDIVReplace ( ) && Opcode == SP :: SDIVrr ) { Opcode = SP :: SDIVCCrr ; } CurDAG -> SelectNodeTo ( N , Opcode , MVT :: i32 , DivLHS , DivRHS , TopPart ) ; return ; } } SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> static bool ix86_must_pass_in_stack ( const function_arg_info & arg ) { if ( must_pass_in_stack_var_size_or_pad ( arg ) ) return true ; return ( ! TARGET_64BIT && arg . mode == TImode && arg . type && TREE_CODE ( arg . type ) != VECTOR_TYPE ) ; } </s>

Return if we do not know how to pass TYPE solely in registers .


<s> void split_di ( rtx operands [ ] , int num , rtx lo_half [ ] , rtx hi_half [ ] ) { while ( num -- ) { rtx op = operands [ num ] ; if ( GET_CODE ( op ) == MEM ) { lo_half [ num ] = adjust_address ( op , SImode , 0 ) ; hi_half [ num ] = adjust_address ( op , SImode , 4 ) ; } else { lo_half [ num ] = simplify_gen_subreg ( SImode , op , GET_MODE ( op ) == VOIDmode ? DImode : GET_MODE ( op ) , 0 ) ; hi_half [ num ] = simplify_gen_subreg ( SImode , op , GET_MODE ( op ) == VOIDmode ? DImode : GET_MODE ( op ) , 4 ) ; } } } </s>

Split one or more DImode RTL references into pairs of SImode references . The RTL can be REG , offsettable MEM , integer constant , or CONST_DOUBLE . `` operands '' is a pointer to an array of DImode RTL to split and `` num '' is its length . lo_half and hi_half are output arrays that parallel `` operands '' .


<s> void emitAssignment ( MCSymbol * Symbol , const MCExpr * Value ) override { } </s>


<s>
SDNode
*
BPFDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
DEBUG
(
dbgs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;
return
;
}
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
INTRINSIC_W_CHAIN
:
{
unsigned
IntNo
=
cast
<
ConstantSDNode
>
(
Node
->
getOperand
(
1
)
)
->
getZExtValue
(
)
;
switch
(
IntNo
)
{
case
Intrinsic
::
bpf_load_byte
:
case
Intrinsic
::
bpf_load_half
:
case
Intrinsic
::
bpf_load_word
:
{
SDLoc
DL
(
Node
)
;
SDValue
Chain
=
Node
->
getOperand
(
0
)
;
SDValue
N1
=
Node
->
getOperand
(
1
)
;
SDValue
Skb
=
Node
->
getOperand
(
2
)
;
SDValue
N3
=
Node
->
getOperand
(
3
)
;
SDValue
R6Reg
=
CurDAG
->
getRegister
(
BPF
::
R6
,
MVT
::
i64
)
;
Chain
=
CurDAG
->
getCopyToReg
(
Chain
,
DL
,
R6Reg
,
Skb
,
SDValue
(
)
)
;
Node
=
CurDAG
->
UpdateNodeOperands
(
Node
,
Chain
,
N1
,
R6Reg
,
N3
)
;
break
;
}
}
break
;
}
case
ISD
::
FrameIndex
:
{
int
FI
=
cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
EVT
VT
=
Node
->
getValueType
(
0
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
VT
)
;
unsigned
Opc
=
BPF
::
MOV_rr
;
if
(
Node
->
hasOneUse
(
)
)
return
CurDAG
->
SelectNodeTo
(
Node
,
Opc
,
VT
,
TFI
)
;
return
CurDAG
->
getMachineNode
(
Opc
,
SDLoc
(
Node
)
,
VT
,
TFI
)
;
}
}
SDNode
*
ResNode
=
SelectCode
(
Node
)
;
DEBUG
(
dbgs
(
)
<<
"=> "
;
if
(
ResNode
==
nullptr
||
ResNode
==
Node
)
Node
->
dump
(
CurDAG
)
;
else
ResNode
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;
return
ResNode
;
}
</s>


"********** MI Converging Scheduling VLIW "

"** VLIWMachineScheduler::schedule picking next node\n"

Schedule - This is called back from ScheduleDAGInstrs : :Run ( ) when it 's time to do some work .


<s> void Mips16FrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( StackSize == 0 && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; MachineLocation DstML , SrcML ; TII . makeFrame ( Mips :: SP , StackSize , MBB , MBBI ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - StackSize ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . size ( ) ) { const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; unsigned DReg = MRI -> getDwarfRegNum ( Reg , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DReg , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: MoveR3216 ) , Mips :: S0 ) . addReg ( Mips :: SP ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Mips Mips Mips Mips 0 Mips::SP Mips::MoveR3216 Mips::S0 Mips::SP


<s> FunctionPass * WebAssemblyPassConfig :: createTargetRegisterAllocator ( bool ) { return nullptr ; } </s>

createTargetRegisterAllocator - Create the register allocator pass for this target at the current optimization level .


"********** Prepare For LiveIntervals **********\n"

"LiveIntervals shouldn't be active yet!"

runOnMachineFunction - Emit the function body .


<s> int h8300_tiny_constant_address_p ( rtx x ) { const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode ( 0x00000000 , SImode ) ; const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode ( 0x00007fff , SImode ) ; const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode ( 0x00ff8000 , SImode ) ; const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode ( 0x00ffffff , SImode ) ; const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode ( 0x00000000 , SImode ) ; const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode ( 0x00007fff , SImode ) ; const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode ( 0xffff8000 , SImode ) ; const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode ( 0xffffffff , SImode ) ; unsigned HOST_WIDE_INT addr ; switch ( GET_CODE ( x ) ) { case SYMBOL_REF : return ( TARGET_NORMAL_MODE || ( SYMBOL_REF_FLAGS ( x ) & SYMBOL_FLAG_TINY_DATA ) != 0 ) ; case CONST_INT : addr = INTVAL ( x ) ; return ( TARGET_NORMAL_MODE || ( TARGET_H8300H && ( IN_RANGE ( addr , h1 , h2 ) || IN_RANGE ( addr , h3 , h4 ) ) ) || ( TARGET_H8300S && ( IN_RANGE ( addr , s1 , s2 ) || IN_RANGE ( addr , s3 , s4 ) ) ) ) ; case CONST : return TARGET_NORMAL_MODE ; default : return 0 ; } } </s>

Nonzero if X is a constant address suitable as an 16-bit absolute on H8/300H and H8S .


<s> bool AVRAsmParser :: ParseDirective ( llvm :: AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal . lower ( ) == ".long" ) { parseLiteralValues ( SIZE_LONG , DirectiveID . getLoc ( ) ) ; } else if ( IDVal . lower ( ) == ".word" || IDVal . lower ( ) == ".short" ) { parseLiteralValues ( SIZE_WORD , DirectiveID . getLoc ( ) ) ; } else if ( IDVal . lower ( ) == ".byte" ) { parseLiteralValues ( 1 , DirectiveID . getLoc ( ) ) ; } return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s>
void
SystemZMCAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
MCFixupKind
Kind
=
Fixup
.
getKind
(
)
;
if
(
Kind
>=
FirstLiteralRelocationKind
)
return
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
unsigned
BitSize
=
getFixupKindInfo
(
Kind
)
.
TargetSize
;
unsigned
Size
=
(
BitSize
+
7
)
/
8
;
assert
(
Offset
+
Size
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
Value
=
extractBitsForFixup
(
Kind
,
Value
,
Fixup
,
Asm
.
getContext
(
)
)
;
if
(
BitSize
<
64
)
Value
&=
(
(
uint64_t
)
1
<<
BitSize
)
1
;
unsigned
ShiftValue
=
(
Size
*
8
)
8
;
for
(
unsigned
I
=
0
;
I
!=
Size
;
++
I
)
{
Data
[
Offset
+
I
]
|=
uint8_t
(
Value
>>
ShiftValue
)
;
ShiftValue
-=
8
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static void tilegx_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int byte_size = ( ( mode == BLKmode ) ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ) ; int word_size = ( byte_size + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; bool doubleword_aligned_p ; doubleword_aligned_p = tilegx_function_arg_boundary ( mode , type ) > BITS_PER_WORD ; if ( doubleword_aligned_p ) * cum += * cum & 1 ; if ( * cum < TILEGX_NUM_ARG_REGS && * cum + word_size > TILEGX_NUM_ARG_REGS ) * cum = TILEGX_NUM_ARG_REGS ; * cum += word_size ; } </s>


"SPUTargetLowering::LowerOperation(): need to lower this!\n"

LowerOperation - Provide custom lowering hooks for some operations .


<s> static void nvptx_goacc_reduction_init ( gcall * call , offload_attrs * oa ) { gimple_stmt_iterator gsi = gsi_for_stmt ( call ) ; tree lhs = gimple_call_lhs ( call ) ; tree var = gimple_call_arg ( call , 2 ) ; int level = TREE_INT_CST_LOW ( gimple_call_arg ( call , 3 ) ) ; enum tree_code rcode = ( enum tree_code ) TREE_INT_CST_LOW ( gimple_call_arg ( call , 4 ) ) ; tree init = omp_reduction_init_op ( gimple_location ( call ) , rcode , TREE_TYPE ( var ) ) ; gimple_seq seq = NULL ; push_gimplify_context ( true ) ; if ( level == GOMP_DIM_VECTOR && oa -> vector_length == PTX_WARP_SIZE ) { tree tid = make_ssa_name ( integer_type_node ) ; tree dim_vector = gimple_call_arg ( call , 3 ) ; gimple * tid_call = gimple_build_call_internal ( IFN_GOACC_DIM_POS , 1 , dim_vector ) ; gimple * cond_stmt = gimple_build_cond ( NE_EXPR , tid , integer_zero_node , NULL_TREE , NULL_TREE ) ; gimple_call_set_lhs ( tid_call , tid ) ; gimple_seq_add_stmt ( & seq , tid_call ) ; gimple_seq_add_stmt ( & seq , cond_stmt ) ; edge init_edge = split_block ( gsi_bb ( gsi ) , call ) ; basic_block init_bb = init_edge -> dest ; basic_block call_bb = init_edge -> src ; init_edge -> flags ^= EDGE_FALLTHRU | EDGE_TRUE_VALUE ; init_edge -> probability = profile_probability :: even ( ) ; gimple_seq init_seq = NULL ; tree init_var = make_ssa_name ( TREE_TYPE ( var ) ) ; gimplify_assign ( init_var , init , & init_seq ) ; gsi = gsi_start_bb ( init_bb ) ; gsi_insert_seq_before ( & gsi , init_seq , GSI_SAME_STMT ) ; gsi_prev ( & gsi ) ; edge inited_edge = split_block ( gsi_bb ( gsi ) , gsi_stmt ( gsi ) ) ; basic_block dst_bb = inited_edge -> dest ; edge nop_edge = make_edge ( call_bb , dst_bb , EDGE_FALSE_VALUE ) ; nop_edge -> probability = profile_probability :: even ( ) ; gphi * phi = create_phi_node ( lhs , dst_bb ) ; add_phi_arg ( phi , init_var , inited_edge , gimple_location ( call ) ) ; add_phi_arg ( phi , var , nop_edge , gimple_location ( call ) ) ; set_immediate_dominator ( CDI_DOMINATORS , dst_bb , call_bb ) ; gsi = gsi_for_stmt ( call ) ; } else { if ( level == GOMP_DIM_GANG ) { tree ref_to_res = gimple_call_arg ( call , 1 ) ; if ( integer_zerop ( ref_to_res ) ) init = var ; } if ( lhs != NULL_TREE ) gimplify_assign ( lhs , init , & seq ) ; } pop_gimplify_context ( NULL ) ; gsi_replace_with_seq ( & gsi , seq , true ) ; } </s>

NVPTX implementation of GOACC_REDUCTION_INIT .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> SDValue X86TargetLowering :: getRecipEstimate ( SDValue Op , DAGCombinerInfo & DCI , unsigned & RefinementSteps ) const { EVT VT = Op . getValueType ( ) ; const char * RecipOp ; if ( VT == MVT :: f32 && Subtarget -> hasSSE1 ( ) ) RecipOp = "divf" ; else if ( ( VT == MVT :: v4f32 && Subtarget -> hasSSE1 ( ) ) || ( VT == MVT :: v8f32 && Subtarget -> hasAVX ( ) ) ) RecipOp = "vec-divf" ; else return SDValue ( ) ; TargetRecip Recips = DCI . DAG . getTarget ( ) . Options . Reciprocals ; if ( ! Recips . isEnabled ( RecipOp ) ) return SDValue ( ) ; RefinementSteps = Recips . getRefinementSteps ( RecipOp ) ; return DCI . DAG . getNode ( X86ISD :: FRCP , SDLoc ( Op ) , VT , Op ) ; } </s>

Return a reciprocal estimate value for the input operand .


<s> const RegClassWeight & R600RegisterInfo :: getRegClassWeight ( const TargetRegisterClass * RC ) const { return RCW ; } </s>

Get the weight in units of pressure for this register class .


<s>
int
m32c_limit_reload_class
(
enum
machine_mode
mode
,
int
rclass
)
{
fprintf
(
stderr
,
"limit_reload_class for %s: %s ->"
,
mode_name
[
mode
]
,
class_names
[
rclass
]
)
;
if
(
mode
==
QImode
)
rclass
=
reduce_class
(
rclass
,
HL_REGS
,
rclass
)
;
else
if
(
mode
==
HImode
)
rclass
=
reduce_class
(
rclass
,
HI_REGS
,
rclass
)
;
else
if
(
mode
==
SImode
)
rclass
=
reduce_class
(
rclass
,
SI_REGS
,
rclass
)
;
if
(
rclass
!=
A_REGS
)
rclass
=
reduce_class
(
rclass
,
DI_REGS
,
rclass
)
;
fprintf
(
stderr
,
" %s\n"
,
class_names
[
rclass
]
)
;
return
rclass
;
}
</s>

Implements LIMIT_RELOAD_CLASS . We basically want to avoid using address registers for reloads since they 're needed for address reloads .

m32c
"limit_reload_class for %s: %s ->"
" %s\n"


<s> bool RISCVTargetLowering :: shouldSinkOperands ( Instruction * I , SmallVectorImpl < Use * > & Ops ) const { using namespace llvm :: PatternMatch ; if ( ! I -> getType ( ) -> isVectorTy ( ) || ! Subtarget . hasStdExtV ( ) ) return false ; auto IsSinker = [ & ] ( Instruction * I , int Operand ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Add : case Instruction :: Sub : case Instruction :: Mul : case Instruction :: FAdd : case Instruction :: FSub : case Instruction :: FMul : case Instruction :: FDiv : return true ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return Operand == 1 ; case Instruction :: Call : if ( auto * II = dyn_cast < IntrinsicInst > ( I ) ) { switch ( II -> getIntrinsicID ( ) ) { case Intrinsic :: fma : return Operand == 0 || Operand == 1 ; default : return false ; } } return false ; default : return false ; } } ; for ( auto OpIdx : enumerate ( I -> operands ( ) ) ) { if ( ! IsSinker ( I , OpIdx . index ( ) ) ) continue ; Instruction * Op = dyn_cast < Instruction > ( OpIdx . value ( ) . get ( ) ) ; if ( ! Op || any_of ( Ops , [ & ] ( Use * U ) { return U -> get ( ) == Op ; } ) ) continue ; if ( ! match ( Op , m_Shuffle ( m_InsertElt ( m_Undef ( ) , m_Value ( ) , m_ZeroInt ( ) ) , m_Undef ( ) , m_ZeroMask ( ) ) ) ) continue ; for ( Use & U : Op -> uses ( ) ) { Instruction * Insn = cast < Instruction > ( U . getUser ( ) ) ; if ( ! IsSinker ( Insn , U . getOperandNo ( ) ) ) return false ; } Ops . push_back ( & Op -> getOperandUse ( 0 ) ) ; Ops . push_back ( & OpIdx . value ( ) ) ; } return true ; } </s>

Return true if sinking I 's operands to the same basic block as I is profitable , e.g .


<s>
void
SystemZInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
unsigned
Opc
=
0
;
if
(
RC
==
&
SystemZ
::
GR32RegClass
||
RC
==
&
SystemZ
::
ADDR32RegClass
)
Opc
=
SystemZ
::
MOV32mr
;
else
if
(
RC
==
&
SystemZ
::
GR64RegClass
||
RC
==
&
SystemZ
::
ADDR64RegClass
)
{
Opc
=
SystemZ
::
MOV64mr
;
}
else
if
(
RC
==
&
SystemZ
::
FP32RegClass
)
{
Opc
=
SystemZ
::
FMOV32mr
;
}
else
if
(
RC
==
&
SystemZ
::
FP64RegClass
)
{
Opc
=
SystemZ
::
FMOV64mr
;
}
else
if
(
RC
==
&
SystemZ
::
GR64PRegClass
)
{
Opc
=
SystemZ
::
MOV64Pmr
;
}
else
if
(
RC
==
&
SystemZ
::
GR128RegClass
)
{
Opc
=
SystemZ
::
MOV128mr
;
}
else
llvm_unreachable
(
"Unsupported regclass to store"
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


"custom instruction opcode must be compile time "

"constant in the range 0-255 for __builtin_custom_%s"

Helper function for expanding custom builtins .


<s> bool LM32RegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( MF . getFunction ( ) -> hasFnAttribute ( "no-realign-stack" ) && ! MFI -> hasVarSizedObjects ( ) ) ; } </s>

True if the stack can be realigned for the target .