<s>
bool
FixupLEAPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
const
X86Subtarget
&
ST
=
MF
.
getSubtarget
<
X86Subtarget
>
(
)
;
bool
IsSlowLEA
=
ST
.
slowLEA
(
)
;
bool
IsSlow3OpsLEA
=
ST
.
slow3OpsLEA
(
)
;
bool
LEAUsesAG
=
ST
.
leaUsesAG
(
)
;
bool
OptIncDec
=
!
ST
.
slowIncDec
(
)
||
MF
.
getFunction
(
)
.
hasOptSize
(
)
;
bool
UseLEAForSP
=
ST
.
useLeaForSP
(
)
;
TSM
.
init
(
&
ST
)
;
TII
=
ST
.
getInstrInfo
(
)
;
TRI
=
ST
.
getRegisterInfo
(
)
;
auto
*
PSI
=
&
getAnalysis
<
ProfileSummaryInfoWrapperPass
>
(
)
.
getPSI
(
)
;
auto
*
MBFI
=
(
PSI
&&
PSI
->
hasProfileSummary
(
)
)
&
getAnalysis
<
LazyMachineBlockFrequencyInfoPass
>
(
)
.
getBFI
(
)
:
nullptr
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Start X86FixupLEAs\n"
;
)
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
bool
OptIncDecPerBB
=
OptIncDec
||
llvm
::
shouldOptimizeForSize
(
&
MBB
,
PSI
,
MBFI
)
;
for
(
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
;
I
!=
MBB
.
end
(
)
;
++
I
)
{
if
(
!
isLEA
(
I
->
getOpcode
(
)
)
)
continue
;
if
(
optTwoAddrLEA
(
I
,
MBB
,
OptIncDecPerBB
,
UseLEAForSP
)
)
continue
;
if
(
IsSlowLEA
)
processInstructionForSlowLEA
(
I
,
MBB
)
;
else
if
(
IsSlow3OpsLEA
)
processInstrForSlow3OpLEA
(
I
,
MBB
,
OptIncDecPerBB
)
;
}
if
(
LEAUsesAG
)
{
for
(
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
;
I
!=
MBB
.
end
(
)
;
++
I
)
processInstruction
(
I
,
MBB
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
"End X86FixupLEAs\n"
;
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


"Unrecognized Hexagon processor version"

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> int microblaze_expand_shift ( rtx operands [ ] ) { gcc_assert ( ( GET_CODE ( operands [ 2 ] ) == CONST_INT ) || ( GET_CODE ( operands [ 2 ] ) == REG ) || ( GET_CODE ( operands [ 2 ] ) == SUBREG ) ) ; if ( ( GET_CODE ( operands [ 2 ] ) == CONST_INT ) && ( INTVAL ( operands [ 2 ] ) == 1 ) ) return 0 ; if ( TARGET_BARREL_SHIFT ) return 0 ; gcc_assert ( ( GET_CODE ( operands [ 0 ] ) == REG ) || ( GET_CODE ( operands [ 0 ] ) == SUBREG ) || ( GET_CODE ( operands [ 1 ] ) == REG ) || ( GET_CODE ( operands [ 1 ] ) == SUBREG ) ) ; if ( operands [ 2 ] == const0_rtx && ! rtx_equal_p ( operands [ 0 ] , operands [ 1 ] ) ) { emit_insn ( gen_movsi ( operands [ 0 ] , operands [ 1 ] ) ) ; return 1 ; } return 0 ; } </s>


<s> bool LanaiInstrInfo :: analyzeCompare ( const MachineInstr & MI , Register & SrcReg , Register & SrcReg2 , int64_t & CmpMask , int64_t & CmpValue ) const { switch ( MI . getOpcode ( ) ) { default : break ; case Lanai :: SFSUB_F_RI_LO : case Lanai :: SFSUB_F_RI_HI : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = Register ( ) ; CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 1 ) . getImm ( ) ; return true ; case Lanai :: SFSUB_F_RR : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 1 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> bool aarch64_sve_mode_p ( machine_mode mode ) { return aarch64_classify_vector_mode ( mode ) & VEC_ANY_SVE ; } </s>

Return true if MODE is any form of SVE mode , including predicates , vectors and structures .


"M680x0 PIC Global Base Reg Initialization"

getPassName - Return a nice clean name for a pass .


"PIC16 DAG->DAG Pattern Instruction Selection"


<s> bool SparcDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintCode ) { default : return true ; case 'm' : if ( ! SelectADDRrr ( Op , Op , Op0 , Op1 ) ) SelectADDRri ( Op , Op , Op0 , Op1 ) ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> static int loongarch_move_to_gpr_cost ( reg_class_t from ) { switch ( from ) { case GENERAL_REGS : return 2 ; case FP_REGS : return 4 ; default : return 0 ; } } </s>

Return the cost of moving a value from a register of class FROM to a GPR . Return 0 for classes that are unions of other classes handled by this function .


<s> bool isDefined ( ) { return Inst2Replace != nullptr ; } </s>

isDefined - Check if this symbol is defined ( i.e. , it has an address ) .


<s> EVT ARMTargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return getPointerTy ( DL ) ; if ( Subtarget -> hasMVEIntegerOps ( ) && ( VT == MVT :: v4i32 || VT == MVT :: v8i16 || VT == MVT :: v16i8 ) ) return MVT :: getVectorVT ( MVT :: i1 , VT . getVectorElementCount ( ) ) ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> bool aarch64_float_const_representable_p ( rtx x ) { int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1 ; int exponent ; unsigned HOST_WIDE_INT mantissa , mask ; REAL_VALUE_TYPE r , m ; bool fail ; if ( ! CONST_DOUBLE_P ( x ) ) return false ; if ( GET_MODE ( x ) == VOIDmode ) return false ; REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; if ( REAL_VALUE_ISINF ( r ) || REAL_VALUE_ISNAN ( r ) || REAL_VALUE_MINUS_ZERO ( r ) ) return false ; r = real_value_abs ( & r ) ; exponent = REAL_EXP ( & r ) ; real_ldexp ( & m , & r , point_pos - exponent ) ; wide_int w = real_to_integer ( & m , & fail , HOST_BITS_PER_WIDE_INT * 2 ) ; if ( w . elt ( 0 ) != 0 ) return false ; mantissa = w . elt ( 1 ) ; point_pos -= HOST_BITS_PER_WIDE_INT ; mask = ( ( unsigned HOST_WIDE_INT ) 1 << ( point_pos - 5 ) ) - 1 ; if ( ( mantissa & mask ) != 0 ) return false ; mantissa >>= point_pos - 5 ; if ( mantissa == 0 ) return false ; mantissa &= ~ ( 1 << 4 ) ; gcc_assert ( mantissa <= 15 ) ; exponent = 5 - exponent ; return ( exponent >= 0 && exponent <= 7 ) ; } </s>

Return true iff X can be represented by a quarter-precision floating point immediate operand X . Note , we can not represent 0.0 .


"passing %qT to argument %d of %qE, which"

Require argument ARGNO to be a ( possibly variable ) scalar , expecting it to have the following properties : - the type class must be the same as for type suffix 0 if EXPECTED_TCLASS is SAME_TYPE_CLASS , otherwise it must be EXPECTED_TCLASS itself . - the element size must be the same as for type suffix 0 if EXPECTED_BITS is SAME_TYPE_SIZE , otherwise it must be EXPECTED_BITS itself . Return true if the argument is valid , otherwise report an appropriate error . Note that we do n't check whether the scalar type actually has the required properties , since that 's subject to implicit promotions and conversions . Instead we just use the expected properties to tune the error message .


<s> void Finish ( MachineBasicBlock & MBB , MOVEMState & State ) { auto MI = State . begin ( ) ; auto End = State . end ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; if ( std :: next ( MI ) == End ) { State = MOVEMState ( ) ; return ; } while ( MI != End ) { auto Next = std :: next ( MI ) ; MBB . erase ( MI ) ; MI = Next ; } if ( State . isLoad ( ) ) { BuildMI ( MBB , End , DL , TII -> get ( M68k :: MOVM32mp ) ) . addImm ( State . getMask ( ) ) . addImm ( State . getFinalOffset ( ) ) . addReg ( State . getBase ( ) ) ; } else { BuildMI ( MBB , End , DL , TII -> get ( M68k :: MOVM32pm ) ) . addImm ( State . getFinalOffset ( ) ) . addReg ( State . getBase ( ) ) . addImm ( State . getMask ( ) ) ; } State = MOVEMState ( ) ; } </s>

Finish - Do final processing and write the object to the output stream .


<s> void ix86_expand_reduc ( rtx ( * fn ) ( rtx , rtx , rtx ) , rtx dest , rtx in ) { rtx half , dst , vec = in ; machine_mode mode = GET_MODE ( in ) ; int i ; if ( TARGET_SSE4_1 && mode == V8HImode && fn == gen_uminv8hi3 ) { emit_insn ( gen_sse4_1_phminposuw ( dest , in ) ) ; return ; } for ( i = GET_MODE_BITSIZE ( mode ) ; i > GET_MODE_UNIT_BITSIZE ( mode ) ; i >>= 1 ) { half = gen_reg_rtx ( mode ) ; emit_reduc_half ( half , vec , i ) ; if ( i == GET_MODE_UNIT_BITSIZE ( mode ) * 2 ) dst = dest ; else dst = gen_reg_rtx ( mode ) ; emit_insn ( fn ( dst , half , vec ) ) ; vec = dst ; } } </s>

Expand a vector reduction . FN is the binary pattern to reduce ; DEST is the destination ; IN is the input vector .


"SSE vector return without SSE enabled "

"MMX vector return without MMX enabled "

When returning SSE vector types , we have a choice of either ( 1 ) being abi incompatible with a -march switch , or ( 2 ) generating an error . Given no good solution , I think the safest thing is one warning . The user wo n't be able to use -Werror , but .... Choose the STRUCT_VALUE_RTX hook because that 's ( at present ) only called in response to actually generating a caller or callee that uses such a type . As opposed to RETURN_IN_MEMORY , which is called via aggregate_value_p for general type probing from tree-ssa .


<s>
MachineBasicBlock
::
iterator
AVRFrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
)
const
{
const
AVRSubtarget
&
STI
=
MF
.
getSubtarget
<
AVRSubtarget
>
(
)
;
const
AVRInstrInfo
&
TII
=
*
STI
.
getInstrInfo
(
)
;
if
(
hasReservedCallFrame
(
MF
)
)
{
fixStackStores
(
MBB
,
MI
,
TII
,
AVR
::
R29R28
)
;
return
MBB
.
erase
(
MI
)
;
}
DebugLoc
DL
=
MI
->
getDebugLoc
(
)
;
unsigned
int
Opcode
=
MI
->
getOpcode
(
)
;
int
Amount
=
TII
.
getFrameSize
(
*
MI
)
;
if
(
Amount
!=
0
)
{
assert
(
getStackAlign
(
)
==
Align
(
1
)
&&
"Unsupported stack alignment"
)
;
if
(
Opcode
==
TII
.
getCallFrameSetupOpcode
(
)
)
{
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
SPREAD
)
,
AVR
::
R31R30
)
.
addReg
(
AVR
::
SP
)
;
MachineInstr
*
New
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
SUBIWRdK
)
,
AVR
::
R31R30
)
.
addReg
(
AVR
::
R31R30
,
RegState
::
Kill
)
.
addImm
(
Amount
)
;
New
->
getOperand
(
3
)
.
setIsDead
(
)
;
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
SPWRITE
)
,
AVR
::
SP
)
.
addReg
(
AVR
::
R31R30
)
;
fixStackStores
(
MBB
,
MI
,
TII
,
AVR
::
R31R30
)
;
}
else
{
assert
(
Opcode
==
TII
.
getCallFrameDestroyOpcode
(
)
)
;
unsigned
addOpcode
;
if
(
isUInt
<
6
>
(
Amount
)
)
{
addOpcode
=
AVR
::
ADIWRdK
;
}
else
{
addOpcode
=
AVR
::
SUBIWRdK
;
Amount
=
Amount
;
}
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
SPREAD
)
,
AVR
::
R31R30
)
.
addReg
(
AVR
::
SP
)
;
MachineInstr
*
New
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
addOpcode
)
,
AVR
::
R31R30
)
.
addReg
(
AVR
::
R31R30
,
RegState
::
Kill
)
.
addImm
(
Amount
)
;
New
->
getOperand
(
3
)
.
setIsDead
(
)
;
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AVR
::
SPWRITE
)
,
AVR
::
SP
)
.
addReg
(
AVR
::
R31R30
,
RegState
::
Kill
)
;
}
}
return
MBB
.
erase
(
MI
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> const TargetRegisterClass * X86RegisterInfo :: getGPRsForTailCall ( const MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( IsWin64 || ( F && F -> getCallingConv ( ) == CallingConv :: Win64 ) ) return & X86 :: GR64_TCW64RegClass ; else if ( Is64Bit ) return & X86 :: GR64_TCRegClass ; bool hasHipeCC = ( F ? F -> getCallingConv ( ) == CallingConv :: HiPE : false ) ; if ( hasHipeCC ) return & X86 :: GR32RegClass ; return & X86 :: GR32_TCRegClass ; } </s>

getGPRsForTailCall - Returns a register class with registers that can be used in forming tail calls .


<s>
bool
X86AsmParser
::
ParseDirective
(
AsmToken
DirectiveID
)
{
MCAsmParser
&
Parser
=
getParser
(
)
;
StringRef
IDVal
=
DirectiveID
.
getIdentifier
(
)
;
if
(
IDVal
==
".word"
)
return
ParseDirectiveWord
(
2
,
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
.
startswith
(
".code"
)
)
return
ParseDirectiveCode
(
IDVal
,
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
.
startswith
(
".att_syntax"
)
)
{
getParser
(
)
.
setParsingInlineAsm
(
false
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.att_syntax noprefix' is not "
"supported: registers must have a "
"'%' prefix in .att_syntax"
)
;
}
getParser
(
)
.
setAssemblerDialect
(
0
)
;
return
false
;
}
else
if
(
IDVal
.
startswith
(
".intel_syntax"
)
)
{
getParser
(
)
.
setAssemblerDialect
(
1
)
;
getParser
(
)
.
setParsingInlineAsm
(
true
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.intel_syntax prefix' is not "
"supported: registers must not have "
"a '%' prefix in .intel_syntax"
)
;
}
return
false
;
}
else
if
(
IDVal
==
".even"
)
return
parseDirectiveEven
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_proc"
)
return
parseDirectiveFPOProc
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_setframe"
)
return
parseDirectiveFPOSetFrame
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_pushreg"
)
return
parseDirectiveFPOPushReg
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_stackalloc"
)
return
parseDirectiveFPOStackAlloc
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_endprologue"
)
return
parseDirectiveFPOEndPrologue
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_endproc"
)
return
parseDirectiveFPOEndProc
(
DirectiveID
.
getLoc
(
)
)
;
return
true
;
}
</s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> static void rs6000_elf_encode_section_info ( tree decl , rtx rtl , int first ) { default_encode_section_info ( decl , rtl , first ) ; if ( first && TREE_CODE ( decl ) == FUNCTION_DECL && ! TARGET_AIX && DEFAULT_ABI == ABI_AIX ) { rtx sym_ref = XEXP ( rtl , 0 ) ; size_t len = strlen ( XSTR ( sym_ref , 0 ) ) ; char * str = alloca ( len + 2 ) ; str [ 0 ] = '.' ; memcpy ( str + 1 , XSTR ( sym_ref , 0 ) , len + 1 ) ; XSTR ( sym_ref , 0 ) = ggc_alloc_string ( str , len + 1 ) ; } } </s>

For a SYMBOL_REF , set generic flags and then perform some target-specific processing . When the AIX ABI is requested on a non-AIX system , replace the function name with the real name ( with a leading . ) rather than the function descriptor name . This saves a lot of overriding code to read the prefixes .


<s> int regs_used ( rtx x , int is_dest ) { enum rtx_code code ; const char * fmt ; int used = 0 ; if ( ! x ) return used ; code = GET_CODE ( x ) ; switch ( code ) { case REG : if ( REGNO ( x ) < 16 ) return ( ( ( 1 << HARD_REGNO_NREGS ( 0 , GET_MODE ( x ) ) ) - 1 ) << ( REGNO ( x ) + is_dest ) ) ; return 0 ; case SUBREG : { rtx y = SUBREG_REG ( x ) ; if ( ! REG_P ( y ) ) break ; if ( REGNO ( y ) < 16 ) return ( ( ( 1 << HARD_REGNO_NREGS ( 0 , GET_MODE ( x ) ) ) - 1 ) << ( REGNO ( y ) + subreg_regno_offset ( REGNO ( y ) , GET_MODE ( y ) , SUBREG_BYTE ( x ) , GET_MODE ( x ) ) + is_dest ) ) ; return 0 ; } case SET : return regs_used ( SET_SRC ( x ) , 0 ) | regs_used ( SET_DEST ( x ) , 16 ) ; case RETURN : return 0x00ffff00 ; case CLOBBER : is_dest = 1 ; break ; case MEM : is_dest = 0 ; break ; case CALL : used |= 0x00ff00f0 ; break ; default : break ; } fmt = GET_RTX_FORMAT ( code ) ; for ( int i = GET_RTX_LENGTH ( code ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { for ( int j = XVECLEN ( x , i ) - 1 ; j >= 0 ; j -- ) used |= regs_used ( XVECEXP ( x , i , j ) , is_dest ) ; } else if ( fmt [ i ] == 'e' ) used |= regs_used ( XEXP ( x , i ) , is_dest ) ; } return used ; } </s>

Given a X , a pattern of an insn or a part of it , return a mask of used general registers . Bits 0 .. 15 mean that the respective registers are used as inputs in the instruction . Bits 16 .. 31 mean that the registers 0 .. 15 , respectively , are used as outputs , or are clobbered . IS_DEST should be set to 16 if X is the destination of a SET , else to 0 .


<s> unsigned MipsSEInstrInfo :: loadImmediate ( int64_t Imm , MachineBasicBlock & MBB , MachineBasicBlock :: iterator II , const DebugLoc & DL , unsigned * NewImm ) const { MipsAnalyzeImmediate AnalyzeImm ; const MipsSubtarget & STI = Subtarget ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; unsigned Size = STI . isABI_N64 ( ) ? 64 : 32 ; unsigned LUi = STI . isABI_N64 ( ) ? Mips :: LUi64 : Mips :: LUi ; unsigned ZEROReg = STI . isABI_N64 ( ) ? Mips :: ZERO_64 : Mips :: ZERO ; const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; bool LastInstrIsADDiu = NewImm ; const MipsAnalyzeImmediate :: InstSeq & Seq = AnalyzeImm . Analyze ( Imm , Size , LastInstrIsADDiu ) ; MipsAnalyzeImmediate :: InstSeq :: const_iterator Inst = Seq . begin ( ) ; assert ( Seq . size ( ) && ( ! LastInstrIsADDiu || ( Seq . size ( ) > 1 ) ) ) ; unsigned Reg = RegInfo . createVirtualRegister ( RC ) ; if ( Inst -> Opc == LUi ) BuildMI ( MBB , II , DL , get ( LUi ) , Reg ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; else BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , Reg ) . addReg ( ZEROReg ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; for ( ++ Inst ; Inst != Seq . end ( ) - LastInstrIsADDiu ; ++ Inst ) BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; if ( LastInstrIsADDiu ) * NewImm = Inst -> ImmOpnd ; return Reg ; } </s>

Emit a series of instructions to load an immediate .


<s>
SDValue
SystemZTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
if
(
Subtarget
.
hasVector
(
)
)
VerifyVectorTypes
(
Outs
)
;
SmallVector
<
CCValAssign
,
16
>
RetLocs
;
CCState
RetCCInfo
(
CallConv
,
IsVarArg
,
MF
,
RetLocs
,
*
DAG
.
getContext
(
)
)
;
RetCCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_SystemZ
)
;
if
(
RetLocs
.
empty
(
)
)
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
Chain
)
;
if
(
CallConv
==
CallingConv
::
GHC
)
report_fatal_error
(
"GHC functions return void only"
)
;
SDValue
Glue
;
SmallVector
<
SDValue
,
4
>
RetOps
;
RetOps
.
push_back
(
Chain
)
;
for
(
unsigned
I
=
0
,
E
=
RetLocs
.
size
(
)
;
I
!=
E
;
++
I
)
{
CCValAssign
&
VA
=
RetLocs
[
I
]
;
SDValue
RetValue
=
OutVals
[
I
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
RetValue
=
convertValVTToLocVT
(
DAG
,
DL
,
VA
,
RetValue
)
;
Register
Reg
=
VA
.
getLocReg
(
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
Reg
,
RetValue
,
Glue
)
;
Glue
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
Reg
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Glue
.
getNode
(
)
)
RetOps
.
push_back
(
Glue
)
;
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static bool ia64_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { if ( reg_classes_intersect_p ( rclass , BR_REGS ) ) return from == to ; if ( SCALAR_FLOAT_MODE_P ( from ) != SCALAR_FLOAT_MODE_P ( to ) ) return ! reg_classes_intersect_p ( rclass , FR_REGS ) ; return true ; } </s>

Implement TARGET_CAN_CHANGE_MODE_CLASS . In BR regs , we ca n't change the DImode at all . In FP regs , we ca n't change FP values to integer values and vice versa , but we can change e.g . DImode to SImode , and V2SFmode into DImode .


<s> MCDisassembler :: DecodeStatus TriCoreDisassembler :: getInstruction ( MCInst & instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & vStream , raw_ostream & cStream ) const { uint16_t insn16 ; if ( ! readInstruction16 ( Bytes , Address , Size , insn16 ) ) { return Fail ; } DecodeStatus Result = decodeInstruction ( DecoderTable16 , instr , insn16 , Address , this , STI ) ; if ( Result != Fail ) { Size = 2 ; return Result ; } uint32_t insn32 ; if ( ! readInstruction32 ( Bytes , Address , Size , insn32 ) ) { return Fail ; } Result = decodeInstruction ( DecoderTable32 , instr , insn32 , Address , this , STI ) ; if ( Result != Fail ) { Size = 4 ; return Result ; } return Fail ; } </s>

Returns the disassembly of a single instruction .


<s> MVT AlphaTargetLowering :: getSetCCResultType ( MVT VT ) const { return MVT :: i64 ; } </s>


<s> static void aarch64_emit_atomic_load_op ( enum aarch64_atomic_load_op_code code , machine_mode mode , rtx dst , rtx src , rtx mem , rtx model ) { typedef rtx ( * aarch64_atomic_load_op_fn ) ( rtx , rtx , rtx , rtx ) ; const aarch64_atomic_load_op_fn plus [ ] = { gen_aarch64_atomic_loadaddqi , gen_aarch64_atomic_loadaddhi , gen_aarch64_atomic_loadaddsi , gen_aarch64_atomic_loadadddi } ; const aarch64_atomic_load_op_fn eor [ ] = { gen_aarch64_atomic_loadeorqi , gen_aarch64_atomic_loadeorhi , gen_aarch64_atomic_loadeorsi , gen_aarch64_atomic_loadeordi } ; const aarch64_atomic_load_op_fn ior [ ] = { gen_aarch64_atomic_loadsetqi , gen_aarch64_atomic_loadsethi , gen_aarch64_atomic_loadsetsi , gen_aarch64_atomic_loadsetdi } ; const aarch64_atomic_load_op_fn bic [ ] = { gen_aarch64_atomic_loadclrqi , gen_aarch64_atomic_loadclrhi , gen_aarch64_atomic_loadclrsi , gen_aarch64_atomic_loadclrdi } ; aarch64_atomic_load_op_fn gen ; int idx = 0 ; switch ( mode ) { case E_QImode : idx = 0 ; break ; case E_HImode : idx = 1 ; break ; case E_SImode : idx = 2 ; break ; case E_DImode : idx = 3 ; break ; default : gcc_unreachable ( ) ; } switch ( code ) { case AARCH64_LDOP_PLUS : gen = plus [ idx ] ; break ; case AARCH64_LDOP_XOR : gen = eor [ idx ] ; break ; case AARCH64_LDOP_OR : gen = ior [ idx ] ; break ; case AARCH64_LDOP_BIC : gen = bic [ idx ] ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( dst , mem , src , model ) ) ; } </s>


<s> static void emit_cbcond_insn ( enum rtx_code code , rtx op0 , rtx op1 , rtx label ) { rtx if_then_else ; if_then_else = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 , op1 ) , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; emit_jump_insn ( gen_rtx_SET ( pc_rtx , if_then_else ) ) ; } </s>

Emit a conditional jump insn for the UA2011 architecture using comparison code CODE and jump target LABEL . This function exists to take advantage of the UA2011 Compare and Branch insns .


"value of %<-mfixed-range%> must have form REG1-REG2"

Parse the -mfixed-range= option string .


<s> bool HexagonInstrInfo :: analyzeCompare ( const MachineInstr * MI , unsigned & SrcReg , unsigned & SrcReg2 , int & Mask , int & Value ) const { unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case Hexagon :: CMPEHexagon4rr : case Hexagon :: CMPEQri : case Hexagon :: CMPEQrr : case Hexagon :: CMPGT64rr : case Hexagon :: CMPGTU64rr : case Hexagon :: CMPGTUri : case Hexagon :: CMPGTUrr : case Hexagon :: CMPGTri : case Hexagon :: CMPGTrr : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; Mask = ~ 0 ; break ; case Hexagon :: CMPbEQri_V4 : case Hexagon :: CMPbEQrr_sbsb_V4 : case Hexagon :: CMPbEQrr_ubub_V4 : case Hexagon :: CMPbGTUri_V4 : case Hexagon :: CMPbGTUrr_V4 : case Hexagon :: CMPbGTrr_V4 : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; Mask = 0xFF ; break ; case Hexagon :: CMPhEQri_V4 : case Hexagon :: CMPhEQrr_shl_V4 : case Hexagon :: CMPhEQrr_xor_V4 : case Hexagon :: CMPhGTUri_V4 : case Hexagon :: CMPhGTUrr_V4 : case Hexagon :: CMPhGTrr_shl_V4 : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; Mask = 0xFFFF ; break ; } switch ( Opc ) { case Hexagon :: CMPEHexagon4rr : case Hexagon :: CMPEQrr : case Hexagon :: CMPGT64rr : case Hexagon :: CMPGTU64rr : case Hexagon :: CMPGTUrr : case Hexagon :: CMPGTrr : case Hexagon :: CMPbEQrr_sbsb_V4 : case Hexagon :: CMPbEQrr_ubub_V4 : case Hexagon :: CMPbGTUrr_V4 : case Hexagon :: CMPbGTrr_V4 : case Hexagon :: CMPhEQrr_shl_V4 : case Hexagon :: CMPhEQrr_xor_V4 : case Hexagon :: CMPhGTUrr_V4 : case Hexagon :: CMPhGTrr_shl_V4 : SrcReg2 = MI -> getOperand ( 2 ) . getReg ( ) ; return true ; case Hexagon :: CMPEQri : case Hexagon :: CMPGTUri : case Hexagon :: CMPGTri : case Hexagon :: CMPbEQri_V4 : case Hexagon :: CMPbGTUri_V4 : case Hexagon :: CMPhEQri_V4 : case Hexagon :: CMPhGTUri_V4 : SrcReg2 = 0 ; Value = MI -> getOperand ( 2 ) . getImm ( ) ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> static void free_array_of_ptrs ( void * * ptr , unsigned n ) { unsigned i ; if ( ! ptr ) return ; for ( i = 0 ; i < n ; i ++ ) { if ( ! ptr [ i ] ) break ; free ( ptr [ i ] ) ; } free ( ptr ) ; return ; } </s>

Auxiliary function that frees elements of PTR and PTR itself . N is number of elements to be freed . If PTR is NULL , nothing is freed . If an element is NULL , subsequent elements are not freed .


<s> void print ( raw_ostream & OS ) const override { } </s>

print - Print a debug representation of the operand to the given stream .


<s> virtual const MBlazeRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void print_operand_address ( FILE * file , register rtx addr ) { register rtx breg ; rtx offset ; int again = 0 ; retry : switch ( GET_CODE ( addr ) ) { case MEM : if ( TARGET_UNIX_ASM ) fprintf ( file , "*" ) ; else fprintf ( file , "@" ) ; addr = XEXP ( addr , 0 ) ; again = 1 ; goto retry ; case REG : fprintf ( file , "(%s)" , reg_names [ REGNO ( addr ) ] ) ; break ; case PRE_MODIFY : case PRE_DEC : fprintf ( file , "-(%s)" , reg_names [ REGNO ( XEXP ( addr , 0 ) ) ] ) ; break ; case POST_MODIFY : case POST_INC : fprintf ( file , "(%s)+" , reg_names [ REGNO ( XEXP ( addr , 0 ) ) ] ) ; break ; case PLUS : breg = 0 ; offset = 0 ; if ( CONSTANT_ADDRESS_P ( XEXP ( addr , 0 ) ) || GET_CODE ( XEXP ( addr , 0 ) ) == MEM ) { offset = XEXP ( addr , 0 ) ; addr = XEXP ( addr , 1 ) ; } else if ( CONSTANT_ADDRESS_P ( XEXP ( addr , 1 ) ) || GET_CODE ( XEXP ( addr , 1 ) ) == MEM ) { offset = XEXP ( addr , 1 ) ; addr = XEXP ( addr , 0 ) ; } if ( GET_CODE ( addr ) != PLUS ) ; else if ( GET_CODE ( XEXP ( addr , 0 ) ) == REG ) { breg = XEXP ( addr , 0 ) ; addr = XEXP ( addr , 1 ) ; } else if ( GET_CODE ( XEXP ( addr , 1 ) ) == REG ) { breg = XEXP ( addr , 1 ) ; addr = XEXP ( addr , 0 ) ; } if ( GET_CODE ( addr ) == REG ) { gcc_assert ( breg == 0 ) ; breg = addr ; addr = 0 ; } if ( offset != 0 ) { gcc_assert ( addr == 0 ) ; addr = offset ; } if ( addr != 0 ) output_addr_const_pdp11 ( file , addr ) ; if ( breg != 0 ) { gcc_assert ( GET_CODE ( breg ) == REG ) ; fprintf ( file , "(%s)" , reg_names [ REGNO ( breg ) ] ) ; } break ; default : if ( ! again && GET_CODE ( addr ) == CONST_INT ) { if ( ! TARGET_UNIX_ASM ) fprintf ( file , "@$" ) ; } output_addr_const_pdp11 ( file , addr ) ; } } </s>

Print the operand address represented by the rtx addr


<s> char const * HexagonMCInstrInfo :: getName ( MCInstrInfo const & MCII , MCInst const & MCI ) { return MCII . getName ( MCI . getOpcode ( ) ) ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s>
MCSymbol
*
X86MCInstLower
::
GetSymbolFromOperand
(
const
MachineOperand
&
MO
)
const
{
const
DataLayout
&
DL
=
MF
.
getDataLayout
(
)
;
assert
(
(
MO
.
isGlobal
(
)
||
MO
.
isSymbol
(
)
||
MO
.
isMBB
(
)
)
&&
"Isn't a symbol reference"
)
;
MCSymbol
*
Sym
=
nullptr
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
switch
(
MO
.
getTargetFlags
(
)
)
{
case
X86II
::
MO_DLLIMPORT
:
Name
+=
"__imp_"
;
break
;
case
X86II
::
MO_DARWIN_NONLAZY
:
case
X86II
::
MO_DARWIN_NONLAZY_PIC_BASE
:
Suffix
=
"$non_lazy_ptr"
;
break
;
}
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
.
getPrivateGlobalPrefix
(
)
;
if
(
MO
.
isGlobal
(
)
)
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
AsmPrinter
.
getNameWithPrefix
(
Name
,
GV
)
;
}
else
if
(
MO
.
isSymbol
(
)
)
{
Mangler
::
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
,
DL
)
;
}
else
if
(
MO
.
isMBB
(
)
)
{
assert
(
Suffix
.
empty
(
)
)
;
Sym
=
MO
.
getMBB
(
)
->
getSymbol
(
)
;
}
Name
+=
Suffix
;
if
(
!
Sym
)
Sym
=
Ctx
.
getOrCreateSymbol
(
Name
)
;
switch
(
MO
.
getTargetFlags
(
)
)
{
default
:
break
;
case
X86II
::
MO_DARWIN_NONLAZY
:
case
X86II
::
MO_DARWIN_NONLAZY_PIC_BASE
:
{
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
getMachOMMI
(
)
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AsmPrinter
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
break
;
}
}
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


<s> virtual const BlackfinRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>


<s>
const
char
*
avr_out_sbxx_branch
(
rtx_insn
*
insn
,
rtx
operands
[
]
)
{
enum
rtx_code
comp
=
GET_CODE
(
operands
[
0
]
)
;
bool
long_jump
=
get_attr_length
(
insn
)
>=
4
;
bool
reverse
=
long_jump
||
jump_over_one_insn_p
(
insn
,
operands
[
3
]
)
;
if
(
comp
==
GE
)
comp
=
EQ
;
else
if
(
comp
==
LT
)
comp
=
NE
;
if
(
reverse
)
comp
=
reverse_condition
(
comp
)
;
switch
(
GET_CODE
(
operands
[
1
]
)
)
{
default
:
gcc_unreachable
(
)
;
case
CONST_INT
:
case
CONST
:
case
SYMBOL_REF
:
if
(
low_io_address_operand
(
operands
[
1
]
,
QImode
)
)
{
if
(
comp
==
EQ
)
output_asm_insn
(
"sbis %i1,%2"
,
operands
)
;
else
output_asm_insn
(
"sbic %i1,%2"
,
operands
)
;
}
else
{
gcc_assert
(
io_address_operand
(
operands
[
1
]
,
QImode
)
)
;
output_asm_insn
(
"in __tmp_reg__,%i1"
,
operands
)
;
if
(
comp
==
EQ
)
output_asm_insn
(
"sbrs __tmp_reg__,%2"
,
operands
)
;
else
output_asm_insn
(
"sbrc __tmp_reg__,%2"
,
operands
)
;
}
break
;
case
REG
:
if
(
comp
==
EQ
)
output_asm_insn
(
"sbrs %T1%T2"
,
operands
)
;
else
output_asm_insn
(
"sbrc %T1%T2"
,
operands
)
;
break
;
}
if
(
long_jump
)
return
(
"rjmp .+4"
CR_TAB
"jmp %x3"
)
;
if
(
!
reverse
)
return
"rjmp %x3"
;
return
""
;
}
</s>

Output a branch that tests a single bit of a register ( QI , HI or SImode ) or memory location in the I/O space ( QImode only ) . Operand 0 : comparison operator ( must be EQ or NE , compare bit to zero ) . Operand 1 : register operand to test , or CONST_INT memory address . Operand 2 : bit number ( for QImode operand ) or mask ( HImode , SImode ) . Operand 3 : label to jump to if the test is true .


"Process function before frame finalized: "

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s>
void
A57ChainingConstraint
::
apply
(
PBQPRAGraph
&
G
)
{
const
MachineFunction
&
MF
=
G
.
getMetadata
(
)
.
MF
;
LiveIntervals
&
LIs
=
G
.
getMetadata
(
)
.
LIS
;
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
DEBUG
(
MF
.
dump
(
)
)
;
for
(
const
auto
&
MBB
:
MF
)
{
Chains
.
clear
(
)
;
for
(
const
auto
&
MI
:
MBB
)
{
for
(
auto
r
:
Chains
)
{
SmallVector
<
unsigned
,
8
>
toDel
;
if
(
regJustKilledBefore
(
LIs
,
r
,
MI
)
)
{
DEBUG
(
dbgs
(
)
<<
"Killing chain "
<<
printReg
(
r
,
TRI
)
<<
" at "
;
MI
.
print
(
dbgs
(
)
)
;
)
;
toDel
.
push_back
(
r
)
;
}
while
(
!
toDel
.
empty
(
)
)
{
Chains
.
remove
(
toDel
.
back
(
)
)
;
toDel
.
pop_back
(
)
;
}
}
switch
(
MI
.
getOpcode
(
)
)
{
case
AArch64
::
FMSUBSrrr
:
case
AArch64
::
FMADDSrrr
:
case
AArch64
::
FNMSUBSrrr
:
case
AArch64
::
FNMADDSrrr
:
case
AArch64
::
FMSUBDrrr
:
case
AArch64
::
FMADDDrrr
:
case
AArch64
::
FNMSUBDrrr
:
case
AArch64
::
FNMADDDrrr
:
{
unsigned
Rd
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
unsigned
Ra
=
MI
.
getOperand
(
3
)
.
getReg
(
)
;
if
(
addIntraChainConstraint
(
G
,
Rd
,
Ra
)
)
addInterChainConstraint
(
G
,
Rd
,
Ra
)
;
break
;
}
case
AArch64
::
FMLAv2f32
:
case
AArch64
::
FMLSv2f32
:
{
unsigned
Rd
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
addInterChainConstraint
(
G
,
Rd
,
Rd
)
;
break
;
}
default
:
break
;
}
}
}
}
</s>

Apply the profile inference algorithm for a given function .


<s> bool arc_is_secure_call_p ( rtx pat ) { tree attrs ; tree decl = SYMBOL_REF_DECL ( pat ) ; if ( ! decl ) return false ; attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; if ( lookup_attribute ( "secure_call" , attrs ) ) return true ; return false ; } </s>

Return nonzero if the symbol is a secure function .


<s> rtx i860_saveregs ( ) { rtx fn = gen_rtx_SYMBOL_REF ( Pmode , "__builtin_saveregs" ) ; rtx save = gen_reg_rtx ( Pmode ) ; rtx valreg = LIBCALL_VALUE ( Pmode ) ; rtx ret ; emit_move_insn ( save , valreg ) ; ret = emit_library_call_value ( fn , NULL_RTX , 1 , Pmode , 0 ) ; if ( GET_CODE ( ret ) != REG || REGNO ( ret ) < FIRST_PSEUDO_REGISTER ) ret = copy_to_reg ( ret ) ; emit_move_insn ( valreg , save ) ; return ret ; } </s>

Expand a library call to __builtin_saveregs .


<s> void MipsMCCodeEmitter :: emitInstruction ( uint64_t Val , unsigned Size , const MCSubtargetInfo & STI , raw_ostream & OS ) const { if ( IsLittleEndian && Size == 4 && isMicroMips ( STI ) ) { emitInstruction ( Val >> 16 , 2 , STI , OS ) ; emitInstruction ( Val , 2 , STI , OS ) ; } else { for ( unsigned i = 0 ; i < Size ; ++ i ) { unsigned Shift = IsLittleEndian ? i * 8 : ( Size - 1 - i ) * 8 ; EmitByte ( ( Val >> Shift ) & 0xff , OS ) ; } } } </s>

Targets should implement this to emit instructions .


<s> bool BTFDebug :: InstLower ( const MachineInstr * MI , MCInst & OutMI ) { if ( MI -> getOpcode ( ) == BPF :: LD_imm64 ) { const MachineOperand & MO = MI -> getOperand ( 1 ) ; if ( MO . isGlobal ( ) ) { const GlobalValue * GVal = MO . getGlobal ( ) ; auto * GVar = dyn_cast < GlobalVariable > ( GVal ) ; if ( GVar && GVar -> hasAttribute ( BPFCoreSharedInfo :: AmaAttr ) ) { MDNode * MDN = GVar -> getMetadata ( LLVMContext :: MD_preserve_access_index ) ; DIType * Ty = dyn_cast < DIType > ( MDN ) ; std :: string TypeName = Ty -> getName ( ) ; int64_t Imm = AccessOffsets [ TypeName + ":" + GVar -> getName ( ) . str ( ) ] ; OutMI . setOpcode ( BPF :: MOV_ri ) ; OutMI . addOperand ( MCOperand :: createReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ) ; OutMI . addOperand ( MCOperand :: createImm ( Imm ) ) ; return true ; } else if ( GVar && ! GVar -> hasInitializer ( ) && GVar -> hasExternalLinkage ( ) && GVar -> getSection ( ) == BPFCoreSharedInfo :: PatchableExtSecName ) { const IntegerType * IntTy = dyn_cast < IntegerType > ( GVar -> getValueType ( ) ) ; assert ( IntTy ) ; if ( IntTy -> getBitWidth ( ) == 64 ) OutMI . setOpcode ( BPF :: LD_imm64 ) ; else OutMI . setOpcode ( BPF :: MOV_ri ) ; OutMI . addOperand ( MCOperand :: createReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ) ; OutMI . addOperand ( MCOperand :: createImm ( 0 ) ) ; return true ; } } } return false ; } </s>


<s> static bool ix86_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( mode1 == mode2 ) return true ; if ( ix86_tieable_integer_mode_p ( mode1 ) && ix86_tieable_integer_mode_p ( mode2 ) ) return true ; if ( mode2 == XFmode ) return mode1 == SFmode || mode1 == DFmode ; if ( mode2 == DFmode ) return mode1 == SFmode ; if ( GET_MODE_SIZE ( mode2 ) == 64 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == 64 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode1 ) ) ; if ( GET_MODE_SIZE ( mode2 ) == 32 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == 32 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode1 ) ) ; if ( GET_MODE_SIZE ( mode2 ) == 16 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == 16 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode1 ) ) ; if ( GET_MODE_SIZE ( mode2 ) == 8 && ix86_hard_regno_mode_ok ( FIRST_MMX_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == 8 && ix86_hard_regno_mode_ok ( FIRST_MMX_REG , mode1 ) ) ; return false ; } </s>

Return true if MODE1 is accessible in a register that can hold MODE2 without copying . That is , all register classes that can hold MODE2 can also hold MODE1 .


More limited version of SimplifyDemandedBits that can be used to `` look through '' ops that do n't contribute to the DemandedBits/DemandedElts - bitwise ops etc .


<s> void tilegx_final_prescan_insn ( rtx_insn * insn ) { insn_mode = GET_MODE ( insn ) ; } </s>

Implement FINAL_PRESCAN_INSN . This is used to emit bundles .


<s> bool ARMInstrInfo :: SubsumesPredicate ( const SmallVectorImpl < MachineOperand > & Pred1 , const SmallVectorImpl < MachineOperand > & Pred2 ) const { if ( Pred1 . size ( ) > 2 || Pred2 . size ( ) > 2 ) return false ; ARMCC :: CondCodes CC1 = ( ARMCC :: CondCodes ) Pred1 [ 0 ] . getImm ( ) ; ARMCC :: CondCodes CC2 = ( ARMCC :: CondCodes ) Pred2 [ 0 ] . getImm ( ) ; if ( CC1 == CC2 ) return true ; switch ( CC1 ) { default : return false ; case ARMCC :: AL : return true ; case ARMCC :: HS : return CC2 == ARMCC :: HI ; case ARMCC :: LS : return CC2 == ARMCC :: LO || CC2 == ARMCC :: EQ ; case ARMCC :: GE : return CC2 == ARMCC :: GT ; case ARMCC :: LE : return CC2 == ARMCC :: LT ; } } </s>

Returns true if the first specified predicate subsumes the second , e.g .

ARM ARM 2 2 ARMCC::CondCodes ARMCC::CondCodes 0 ARMCC::CondCodes ARMCC::CondCodes 0 ARMCC::AL ARMCC::HS ARMCC::HI ARMCC::LS ARMCC::LO ARMCC::EQ ARMCC::GE ARMCC::GT ARMCC::LE ARMCC::LT


<s> void rs6000_emit_parity ( rtx dst , rtx src ) { machine_mode mode = GET_MODE ( dst ) ; rtx tmp ; tmp = gen_reg_rtx ( mode ) ; if ( TARGET_CMPB ) { if ( mode == SImode ) { emit_insn ( gen_popcntbsi2 ( tmp , src ) ) ; emit_insn ( gen_paritysi2_cmpb ( dst , tmp ) ) ; } else { emit_insn ( gen_popcntbdi2 ( tmp , src ) ) ; emit_insn ( gen_paritydi2_cmpb ( dst , tmp ) ) ; } return ; } if ( mode == SImode ) { if ( rs6000_cost -> mulsi_const >= COSTS_N_INSNS ( 3 ) ) { rtx tmp1 , tmp2 , tmp3 , tmp4 ; tmp1 = gen_reg_rtx ( SImode ) ; emit_insn ( gen_popcntbsi2 ( tmp1 , src ) ) ; tmp2 = gen_reg_rtx ( SImode ) ; emit_insn ( gen_lshrsi3 ( tmp2 , tmp1 , GEN_INT ( 16 ) ) ) ; tmp3 = gen_reg_rtx ( SImode ) ; emit_insn ( gen_xorsi3 ( tmp3 , tmp1 , tmp2 ) ) ; tmp4 = gen_reg_rtx ( SImode ) ; emit_insn ( gen_lshrsi3 ( tmp4 , tmp3 , GEN_INT ( 8 ) ) ) ; emit_insn ( gen_xorsi3 ( tmp , tmp3 , tmp4 ) ) ; } else rs6000_emit_popcount ( tmp , src ) ; emit_insn ( gen_andsi3 ( dst , tmp , const1_rtx ) ) ; } else { if ( rs6000_cost -> muldi >= COSTS_N_INSNS ( 5 ) ) { rtx tmp1 , tmp2 , tmp3 , tmp4 , tmp5 , tmp6 ; tmp1 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_popcntbdi2 ( tmp1 , src ) ) ; tmp2 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_lshrdi3 ( tmp2 , tmp1 , GEN_INT ( 32 ) ) ) ; tmp3 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_xordi3 ( tmp3 , tmp1 , tmp2 ) ) ; tmp4 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_lshrdi3 ( tmp4 , tmp3 , GEN_INT ( 16 ) ) ) ; tmp5 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_xordi3 ( tmp5 , tmp3 , tmp4 ) ) ; tmp6 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_lshrdi3 ( tmp6 , tmp5 , GEN_INT ( 8 ) ) ) ; emit_insn ( gen_xordi3 ( tmp , tmp5 , tmp6 ) ) ; } else rs6000_emit_popcount ( tmp , src ) ; emit_insn ( gen_anddi3 ( dst , tmp , const1_rtx ) ) ; } } </s>

Emit parity intrinsic on TARGET_POPCNTB targets . DST is the target , and SRC is the argument operand .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS , bool isThumb ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS , isThumb ) , JITInfo ( ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) { DefRelocModel = getRelocationModel ( ) ; } </s>


<s> bool AMDGPUUnifyMetadata :: runOnModule ( Module & M ) { const char * Vers [ ] = { kOCLMD :: SpirVer , kOCLMD :: OCLVer } ; const char * Exts [ ] = { kOCLMD :: UsedExt , kOCLMD :: UsedOptCoreFeat , kOCLMD :: CompilerOptions , kOCLMD :: LLVMIdent } ; bool Changed = false ; for ( auto & I : Vers ) Changed |= unifyVersionMD ( M , I , true ) ; for ( auto & I : Exts ) Changed |= unifyExtensionMD ( M , I ) ; return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Patmos PML Profile Import Pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> void MipsCallLowering :: splitToValueTypes ( const ArgInfo & OrigArg , unsigned OriginalIndex , SmallVectorImpl < ArgInfo > & SplitArgs , SmallVectorImpl < unsigned > & SplitArgsOrigIndices ) const { SplitArgs . push_back ( OrigArg ) ; SplitArgsOrigIndices . push_back ( OriginalIndex ) ; } </s>

Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> bool XtensaInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return false ; if ( ! isUnpredicatedTerminator ( * I ) ) return false ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! isUnpredicatedTerminator ( * I ) ) break ; if ( ! I -> isBranch ( ) ) return true ; return true ; } return true ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> const char * output_branchy_insn ( enum rtx_code code , const char * templ , rtx_insn * insn , rtx * operands ) { rtx_insn * next_insn = NEXT_INSN ( insn ) ; if ( next_insn && JUMP_P ( next_insn ) && condjump_p ( next_insn ) ) { rtx src = SET_SRC ( PATTERN ( next_insn ) ) ; if ( GET_CODE ( src ) == IF_THEN_ELSE && GET_CODE ( XEXP ( src , 0 ) ) != code ) { rtx_code_label * lab = gen_label_rtx ( ) ; emit_label_after ( lab , next_insn ) ; INSN_ADDRESSES_NEW ( lab , INSN_ADDRESSES ( INSN_UID ( next_insn ) ) + get_attr_length ( next_insn ) ) ; operands [ 9 ] = lab ; return templ ; } else { int offset = ( branch_dest ( next_insn ) - INSN_ADDRESSES ( INSN_UID ( next_insn ) ) + 4 ) ; if ( offset >= - 252 && offset <= 258 ) { if ( GET_CODE ( src ) == IF_THEN_ELSE ) src = XEXP ( src , 1 ) ; operands [ 9 ] = src ; return templ ; } } } rtx_code_label * lab = gen_label_rtx ( ) ; emit_label_after ( lab , insn ) ; INSN_ADDRESSES_NEW ( lab , INSN_ADDRESSES ( INSN_UID ( insn ) ) + get_attr_length ( insn ) ) ; operands [ 9 ] = lab ; return templ ; } </s>

Output a code sequence for INSN using TEMPL with OPERANDS ; but before , fill in operands 9 as a label to the successor insn . We try to use jump threading where possible . IF CODE matches the comparison in the IF_THEN_ELSE of a following jump , we assume the jump is taken . I.e . EQ means follow jmp and bf , NE means follow jmp and bt , if the address is in range .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> SDValue TGSITargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { MachineFunction & mf = DAG . getMachineFunction ( ) ; MachineRegisterInfo & reginfo = mf . getRegInfo ( ) ; SmallVector < CCValAssign , 16 > ArgLocs ; CCState ccinfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCAssignFn * ccfn = KernCC_TGSI ; ccinfo . AnalyzeFormalArguments ( Ins , ccfn ) ; for ( unsigned i = 0 , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & va = ArgLocs [ i ] ; MVT vt = va . getValVT ( ) ; SDValue arg ; if ( va . isRegLoc ( ) ) { unsigned vreg = reginfo . createVirtualRegister ( getRegClassFor ( vt ) ) ; reginfo . addLiveIn ( va . getLocReg ( ) , vreg ) ; arg = DAG . getCopyFromReg ( Chain , dl , vreg , vt ) ; } else { SDValue ptr = DAG . getConstant ( va . getLocMemOffset ( ) , dl , MVT :: i32 ) ; arg = DAG . getNode ( TGSIISD :: LOAD_INPUT , dl , vt , Chain , ptr ) ; } InVals . push_back ( arg ) ; } return Chain ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> unsigned int AArch64InstrInfo :: getTailDuplicateSize ( CodeGenOpt :: Level OptLevel ) const { return OptLevel >= CodeGenOpt :: Aggressive ? 6 : 2 ; } </s>

Returns the target-specific default value for tail duplication .


<s> bool PatmosInstrInfo :: SubsumesPredicate ( ArrayRef < MachineOperand > Pred1 , ArrayRef < MachineOperand > Pred2 ) const { assert ( Pred1 . size ( ) == 2 && Pred2 . size ( ) == 2 ) ; unsigned preg1 = Pred1 [ 0 ] . getReg ( ) ; int flag1 = Pred1 [ 1 ] . getImm ( ) ; if ( ( preg1 == Patmos :: NoRegister || preg1 == Patmos :: P0 ) && ! flag1 ) return true ; if ( preg1 == Pred2 [ 0 ] . getReg ( ) && flag1 == Pred2 [ 1 ] . getImm ( ) ) return true ; return false ; } </s>


<s> static unsigned getReg ( const void * D , unsigned RC , unsigned RegNo ) { const MipsDisassemblerBase * Dis = static_cast < const MipsDisassemblerBase * > ( D ) ; const MCRegisterInfo * RegInfo = Dis -> getContext ( ) . getRegisterInfo ( ) ; return * ( RegInfo -> getRegClass ( RC ) . begin ( ) + RegNo ) ; } </s>

Returns the register associated with this edge .


<s>
const
MCPhysReg
*
Z80oldRegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
switch
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
CSR_Z80old_C_SaveList
;
case
CallingConv
::
PreserveAll
:
case
CallingConv
::
Z80_LibCall
:
case
CallingConv
::
Z80_LibCall_AC
:
case
CallingConv
::
Z80_LibCall_BC
:
case
CallingConv
::
Z80_LibCall_C
:
case
CallingConv
::
Z80_LibCall_L
:
return
CSR_Z80old_AllRegs_SaveList
;
}
}
</s>


<s>
const
uint32_t
*
LoongArchRegisterInfo
::
getCallPreservedMask
(
const
MachineFunction
&
MF
,
CallingConv
::
ID
CC
)
const
{
auto
&
Subtarget
=
MF
.
getSubtarget
<
LoongArchSubtarget
>
(
)
;
switch
(
Subtarget
.
getTargetABI
(
)
)
{
default
:
llvm_unreachable
(
"Unrecognized ABI"
)
;
case
LoongArchABI
::
ABI_ILP32S
:
case
LoongArchABI
::
ABI_LP64S
:
return
CSR_ILP32S_LP64S_RegMask
;
case
LoongArchABI
::
ABI_ILP32F
:
case
LoongArchABI
::
ABI_LP64F
:
return
CSR_ILP32F_LP64F_RegMask
;
case
LoongArchABI
::
ABI_ILP32D
:
case
LoongArchABI
::
ABI_LP64D
:
return
CSR_ILP32D_LP64D_RegMask
;
}
}
</s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool X86FrameLowering :: canSimplifyCallFramePseudos ( const MachineFunction & MF ) const { return hasReservedCallFrame ( MF ) || ( hasFP ( MF ) && ! TRI -> needsStackRealignment ( MF ) ) || TRI -> hasBasePointer ( MF ) ; } </s>

canSimplifyCallFramePseudos - If there is a reserved call frame , the call frame pseudos can be simplified .


"[Single-Path] Clone functions reachable from single-path roots\n"


<s>
const
char
*
getPassName
(
)
const
override
{
return
"MSP430 Branch Selector"
;
}
</s>


<s>
bool
AMDGPUSimplifyLibCalls
::
runOnFunction
(
Function
&
F
)
{
if
(
skipFunction
(
F
)
)
return
false
;
bool
Changed
=
false
;
auto
AA
=
&
getAnalysis
<
AAResultsWrapperPass
>
(
)
.
getAAResults
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"AMDIC: process function "
;
F
.
printAsOperand
(
dbgs
(
)
,
false
,
F
.
getParent
(
)
)
;
dbgs
(
)
<<
'\n'
;
)
;
for
(
auto
&
BB
:
F
)
{
for
(
BasicBlock
::
iterator
I
=
BB
.
begin
(
)
,
E
=
BB
.
end
(
)
;
I
!=
E
;
)
{
CallInst
*
CI
=
dyn_cast
<
CallInst
>
(
I
)
;
++
I
;
if
(
!
CI
)
continue
;
Function
*
Callee
=
CI
->
getCalledFunction
(
)
;
if
(
Callee
==
0
)
continue
;
LLVM_DEBUG
(
dbgs
(
)
<<
"AMDIC: try folding "
<<
*
CI
<<
"\n"
;
dbgs
(
)
.
flush
(
)
)
;
if
(
Simplifier
.
fold
(
CI
,
AA
)
)
Changed
=
true
;
}
}
return
Changed
;
}
</s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .

AMDGPU
AMDGPU
"AMDIC: process function "
0
"AMDIC: try folding "
"\n"


<s> bool SparcFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static rtx expand_mla_mls_lane ( function_expander & e , int unspec ) { e . rotate_inputs_left ( 0 , 4 ) ; insn_code icode = code_for_aarch64_lane ( unspec , e . vector_mode ( 0 ) ) ; return e . use_exact_insn ( icode ) ; } </s>

Expand a call to svmla_lane or svmls_lane using floating-point unspec UNSPEC .


<s> SDValue AMDGPUTargetLowering :: loadStackInputValue ( SelectionDAG & DAG , EVT VT , const SDLoc & SL , int64_t Offset ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; int FI = getOrCreateFixedStackObject ( MFI , VT . getStoreSize ( ) , Offset ) ; auto SrcPtrInfo = MachinePointerInfo :: getStack ( MF , Offset ) ; SDValue Ptr = DAG . getFrameIndex ( FI , MVT :: i32 ) ; return DAG . getLoad ( VT , SL , DAG . getEntryNode ( ) , Ptr , SrcPtrInfo , Align ( 4 ) , MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; } </s>

Similar to CreateLiveInRegister , except value maybe loaded from a stack slot rather than passed in a register .


<s> bool MipsPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) == CodeGenOpt :: None ) { addPass ( createMipsOptimizePICCallPass ( getMipsTargetMachine ( ) ) ) ; return true ; } else return false ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static bool rs6000_secondary_memory_needed ( machine_mode mode , reg_class_t from_class , reg_class_t to_class ) { enum rs6000_reg_type from_type , to_type ; bool altivec_p = ( ( from_class == ALTIVEC_REGS ) || ( to_class == ALTIVEC_REGS ) ) ; from_type = reg_class_to_reg_type [ ( int ) from_class ] ; to_type = reg_class_to_reg_type [ ( int ) to_class ] ; if ( rs6000_secondary_reload_move ( to_type , from_type , mode , ( secondary_reload_info * ) 0 , altivec_p ) ) return false ; if ( IS_FP_VECT_REG_TYPE ( from_type ) || IS_FP_VECT_REG_TYPE ( to_type ) ) return true ; return false ; } </s>

If we are copying between FP or AltiVec registers and anything else , we need a memory location . The exception is when we are targeting ppc64 and the move to/from fpr to gpr instructions are available . Also , under VSX , you can copy vector registers from the FP register set to the Altivec register set and vice versa .


<s> unsigned ARMTTIImpl :: getFPOpCost ( Type * Ty ) { if ( ST -> hasVFP2 ( ) && ! ST -> isThumb1Only ( ) ) { if ( Ty -> isFloatTy ( ) ) { return TargetTransformInfo :: TCC_Basic ; } if ( Ty -> isDoubleTy ( ) ) { return ST -> isFPOnlySP ( ) ? TargetTransformInfo :: TCC_Expensive : TargetTransformInfo :: TCC_Basic ; } } return TargetTransformInfo :: TCC_Expensive ; } </s>

Return the expected cost of supporting the floating point operation of the specified type .


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCRelaxableFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
override
{
llvm_unreachable
(
"fixupNeedsRelaxation() unimplemented"
)
;
return
false
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> bool M68kAsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s>
bool
RISCVInstrInfo
::
isBranch
(
const
MachineInstr
*
MI
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
const
MachineOperand
*
&
Target
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
case
RISCV
::
J
:
case
RISCV
::
J64
:
case
RISCV
::
JAL
:
case
RISCV
::
JAL64
:
case
RISCV
::
JALR
:
case
RISCV
::
JALR64
:
Cond
[
0
]
.
setImm
(
RISCV
::
CCMASK_ANY
)
;
Target
=
&
MI
->
getOperand
(
0
)
;
return
true
;
case
RISCV
::
BEQ
:
case
RISCV
::
BEQ64
:
Cond
[
0
]
.
setImm
(
RISCV
::
CCMASK_CMP_EQ
)
;
Target
=
&
MI
->
getOperand
(
0
)
;
return
true
;
case
RISCV
::
BNE
:
case
RISCV
::
BNE64
:
Cond
[
0
]
.
setImm
(
RISCV
::
CCMASK_CMP_NE
)
;
Target
=
&
MI
->
getOperand
(
0
)
;
return
true
;
case
RISCV
::
BLT
:
case
RISCV
::
BLT64
:
Cond
[
0
]
.
setImm
(
RISCV
::
CCMASK_CMP_LT
)
;
Target
=
&
MI
->
getOperand
(
0
)
;
return
true
;
case
RISCV
::
BLTU
:
case
RISCV
::
BLTU64
:
Cond
[
0
]
.
setImm
(
RISCV
::
CCMASK_CMP_LT
|
RISCV
::
CCMASK_CMP_UO
)
;
Target
=
&
MI
->
getOperand
(
0
)
;
return
true
;
case
RISCV
::
BGE
:
case
RISCV
::
BGE64
:
Cond
[
0
]
.
setImm
(
RISCV
::
CCMASK_CMP_GE
)
;
Target
=
&
MI
->
getOperand
(
0
)
;
return
true
;
case
RISCV
::
BGEU
:
case
RISCV
::
BGEU64
:
Cond
[
0
]
.
setImm
(
RISCV
::
CCMASK_CMP_GE
|
RISCV
::
CCMASK_CMP_UO
)
;
Target
=
&
MI
->
getOperand
(
0
)
;
return
true
;
case
RISCV
::
BGT
:
case
RISCV
::
BGT64
:
Cond
[
0
]
.
setImm
(
RISCV
::
CCMASK_CMP_GT
)
;
Target
=
&
MI
->
getOperand
(
0
)
;
return
true
;
case
RISCV
::
BGTU
:
case
RISCV
::
BGTU64
:
Cond
[
0
]
.
setImm
(
RISCV
::
CCMASK_CMP_GT
|
RISCV
::
CCMASK_CMP_UO
)
;
Target
=
&
MI
->
getOperand
(
0
)
;
return
true
;
case
RISCV
::
BLE
:
case
RISCV
::
BLE64
:
Cond
[
0
]
.
setImm
(
RISCV
::
CCMASK_CMP_LE
)
;
Target
=
&
MI
->
getOperand
(
0
)
;
return
true
;
case
RISCV
::
BLEU
:
case
RISCV
::
BLEU64
:
Cond
[
0
]
.
setImm
(
RISCV
::
CCMASK_CMP_LE
|
RISCV
::
CCMASK_CMP_UO
)
;
Target
=
&
MI
->
getOperand
(
0
)
;
return
true
;
default
:
assert
(
!
MI
->
getDesc
(
)
.
isBranch
(
)
&&
"Unknown branch opcode"
)
;
return
false
;
}
}
</s>

Returns true if this is a conditional , unconditional , or indirect branch .


<s> unsigned X86AsmParser :: checkTargetMatchPredicate ( MCInst & Inst ) { unsigned Opc = Inst . getOpcode ( ) ; const MCInstrDesc & MCID = MII . get ( Opc ) ; if ( ForcedVEXEncoding == VEXEncoding_EVEX && ( MCID . TSFlags & X86II :: EncodingMask ) != X86II :: EVEX ) return Match_Unsupported ; if ( ( ForcedVEXEncoding == VEXEncoding_VEX || ForcedVEXEncoding == VEXEncoding_VEX2 || ForcedVEXEncoding == VEXEncoding_VEX3 ) && ( MCID . TSFlags & X86II :: EncodingMask ) != X86II :: VEX ) return Match_Unsupported ; if ( MCID . TSFlags & X86II :: ExplicitVEXPrefix && ( ForcedVEXEncoding != VEXEncoding_VEX && ForcedVEXEncoding != VEXEncoding_VEX2 && ForcedVEXEncoding != VEXEncoding_VEX3 ) ) return Match_Unsupported ; return Match_Success ; } </s>

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


<s> bool mips_expand_unaligned_store ( rtx dest , rtx src , unsigned int width , int bitpos ) { rtx left , right ; if ( ! mips_get_unaligned_mem ( & dest , width , bitpos , & left , & right ) ) return false ; src = gen_lowpart ( mode_for_size ( width , MODE_INT , 0 ) , src ) ; if ( GET_MODE ( src ) == DImode ) { emit_insn ( gen_mov_sdl ( dest , src , left ) ) ; emit_insn ( gen_mov_sdr ( copy_rtx ( dest ) , copy_rtx ( src ) , right ) ) ; } else { emit_insn ( gen_mov_swl ( dest , src , left ) ) ; emit_insn ( gen_mov_swr ( copy_rtx ( dest ) , copy_rtx ( src ) , right ) ) ; } return true ; } </s>

Try to expand ( set ( zero_extract DEST WIDTH BITPOS ) SRC ) . Return true on success .


<s> static bool arm_pass_by_reference ( cumulative_args_t cum ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , const_tree type , bool named ATTRIBUTE_UNUSED ) { return type && TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ; } </s>

Variable sized types are passed by reference . This is a GCC extension to the ARM ABI .


<s>
const
Metadata
*
get
(
ArrayRef
<
const
Metadata
*
>
MDs
)
const
{
assert
(
ID
&&
"Expected non-zero ID"
)
;
assert
(
ID
<=
MDs
.
size
(
)
&&
"Expected valid ID"
)
;
return
MDs
[
ID
1
]
;
}
</s>

Get the generated Value for a given VPValue and given Part and Lane .

DirectX
"Expected non-zero ID"
"Expected valid ID"
1


<s> unsigned X86RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? FramePtr : StackPtr ; } </s>


<s> const char * riscv_output_move ( rtx dest , rtx src ) { enum rtx_code dest_code , src_code ; machine_mode mode ; bool dbl_p ; dest_code = GET_CODE ( dest ) ; src_code = GET_CODE ( src ) ; mode = GET_MODE ( dest ) ; dbl_p = ( GET_MODE_SIZE ( mode ) == 8 ) ; if ( dbl_p && riscv_split_64bit_move_p ( dest , src ) ) return "#" ; if ( dest_code == REG && GP_REG_P ( REGNO ( dest ) ) ) { if ( src_code == REG && FP_REG_P ( REGNO ( src ) ) ) return dbl_p ? "fmv.x.d\t%0,%1" : "fmv.x.s\t%0,%1" ; if ( src_code == MEM ) switch ( GET_MODE_SIZE ( mode ) ) { case 1 : return "lbu\t%0,%1" ; case 2 : return "lhu\t%0,%1" ; case 4 : return "lw\t%0,%1" ; case 8 : return "ld\t%0,%1" ; } if ( src_code == CONST_INT ) return "li\t%0,%1" ; if ( src_code == HIGH ) return "lui\t%0,%h1" ; if ( symbolic_operand ( src , VOIDmode ) ) switch ( riscv_classify_symbolic_expression ( src ) ) { case SYMBOL_GOT_DISP : return "la\t%0,%1" ; case SYMBOL_ABSOLUTE : return "lla\t%0,%1" ; case SYMBOL_PCREL : return "lla\t%0,%1" ; default : gcc_unreachable ( ) ; } } if ( ( src_code == REG && GP_REG_P ( REGNO ( src ) ) ) || ( src == CONST0_RTX ( mode ) ) ) { if ( dest_code == REG ) { if ( GP_REG_P ( REGNO ( dest ) ) ) return "mv\t%0,%z1" ; if ( FP_REG_P ( REGNO ( dest ) ) ) { if ( ! dbl_p ) return "fmv.s.x\t%0,%z1" ; if ( TARGET_64BIT ) return "fmv.d.x\t%0,%z1" ; gcc_assert ( src == CONST0_RTX ( mode ) ) ; return "fcvt.d.w\t%0,x0" ; } } if ( dest_code == MEM ) switch ( GET_MODE_SIZE ( mode ) ) { case 1 : return "sb\t%z1,%0" ; case 2 : return "sh\t%z1,%0" ; case 4 : return "sw\t%z1,%0" ; case 8 : return "sd\t%z1,%0" ; } } if ( src_code == REG && FP_REG_P ( REGNO ( src ) ) ) { if ( dest_code == REG && FP_REG_P ( REGNO ( dest ) ) ) return dbl_p ? "fmv.d\t%0,%1" : "fmv.s\t%0,%1" ; if ( dest_code == MEM ) return dbl_p ? "fsd\t%1,%0" : "fsw\t%1,%0" ; } if ( dest_code == REG && FP_REG_P ( REGNO ( dest ) ) ) { if ( src_code == MEM ) return dbl_p ? "fld\t%0,%1" : "flw\t%0,%1" ; } gcc_unreachable ( ) ; } </s>

Return the appropriate instructions to move SRC into DEST . Assume that SRC is operand 1 and DEST is operand 0 .


<s> void order_regs_for_local_alloc ( void ) { if ( ! leaf_function_p ( ) ) { static const int reg_nonleaf_alloc_order [ FIRST_PSEUDO_REGISTER ] = REG_ALLOC_ORDER ; static const int reg_nonleaf_alloc_order_call0 [ FIRST_PSEUDO_REGISTER ] = { 11 , 10 , 9 , 8 , 7 , 6 , 5 , 4 , 3 , 2 , 12 , 13 , 14 , 15 , 18 , 19 , 20 , 21 , 22 , 23 , 24 , 25 , 26 , 27 , 28 , 29 , 30 , 31 , 32 , 33 , 34 , 0 , 1 , 16 , 17 , 35 , } ; memcpy ( reg_alloc_order , TARGET_WINDOWED_ABI ? reg_nonleaf_alloc_order : reg_nonleaf_alloc_order_call0 , FIRST_PSEUDO_REGISTER * sizeof ( int ) ) ; } else { int i , num_arg_regs ; int nxt = 0 ; num_arg_regs = crtl -> args . info . arg_words ; if ( num_arg_regs > MAX_ARGS_IN_REGISTERS ) num_arg_regs = MAX_ARGS_IN_REGISTERS ; for ( i = GP_ARG_FIRST ; i < 16 - num_arg_regs ; i ++ ) reg_alloc_order [ nxt ++ ] = i + num_arg_regs ; for ( i = 0 ; i < num_arg_regs ; i ++ ) reg_alloc_order [ nxt ++ ] = GP_ARG_FIRST + i ; for ( i = 0 ; i < BR_REG_NUM ; i ++ ) reg_alloc_order [ nxt ++ ] = BR_REG_FIRST + i ; for ( i = 0 ; i < 16 ; i ++ ) reg_alloc_order [ nxt ++ ] = FP_REG_FIRST + i ; reg_alloc_order [ nxt ++ ] = 0 ; reg_alloc_order [ nxt ++ ] = 1 ; reg_alloc_order [ nxt ++ ] = 16 ; reg_alloc_order [ nxt ++ ] = 17 ; reg_alloc_order [ nxt ++ ] = ACC_REG_FIRST ; } } </s>

Choose the order in which to allocate hard registers for pseudo-registers local to a basic block . Store the desired register order in the array ` reg_alloc_order ' . Element 0 should be the register to allocate first ; element 1 , the next register ; and so on .


<s> static int getRegClass ( RegisterKind Is , unsigned RegWidth ) { if ( Is == IS_VGPR ) { switch ( RegWidth ) { default : return - 1 ; case 1 : return AMDGPU :: VGPR_32RegClassID ; case 2 : return AMDGPU :: VReg_64RegClassID ; case 3 : return AMDGPU :: VReg_96RegClassID ; case 4 : return AMDGPU :: VReg_128RegClassID ; case 5 : return AMDGPU :: VReg_160RegClassID ; case 6 : return AMDGPU :: VReg_192RegClassID ; case 7 : return AMDGPU :: VReg_224RegClassID ; case 8 : return AMDGPU :: VReg_256RegClassID ; case 16 : return AMDGPU :: VReg_512RegClassID ; case 32 : return AMDGPU :: VReg_1024RegClassID ; } } else if ( Is == IS_TTMP ) { switch ( RegWidth ) { default : return - 1 ; case 1 : return AMDGPU :: TTMP_32RegClassID ; case 2 : return AMDGPU :: TTMP_64RegClassID ; case 4 : return AMDGPU :: TTMP_128RegClassID ; case 8 : return AMDGPU :: TTMP_256RegClassID ; case 16 : return AMDGPU :: TTMP_512RegClassID ; } } else if ( Is == IS_SGPR ) { switch ( RegWidth ) { default : return - 1 ; case 1 : return AMDGPU :: SGPR_32RegClassID ; case 2 : return AMDGPU :: SGPR_64RegClassID ; case 3 : return AMDGPU :: SGPR_96RegClassID ; case 4 : return AMDGPU :: SGPR_128RegClassID ; case 5 : return AMDGPU :: SGPR_160RegClassID ; case 6 : return AMDGPU :: SGPR_192RegClassID ; case 7 : return AMDGPU :: SGPR_224RegClassID ; case 8 : return AMDGPU :: SGPR_256RegClassID ; case 16 : return AMDGPU :: SGPR_512RegClassID ; } } else if ( Is == IS_AGPR ) { switch ( RegWidth ) { default : return - 1 ; case 1 : return AMDGPU :: AGPR_32RegClassID ; case 2 : return AMDGPU :: AReg_64RegClassID ; case 3 : return AMDGPU :: AReg_96RegClassID ; case 4 : return AMDGPU :: AReg_128RegClassID ; case 5 : return AMDGPU :: AReg_160RegClassID ; case 6 : return AMDGPU :: AReg_192RegClassID ; case 7 : return AMDGPU :: AReg_224RegClassID ; case 8 : return AMDGPU :: AReg_256RegClassID ; case 16 : return AMDGPU :: AReg_512RegClassID ; case 32 : return AMDGPU :: AReg_1024RegClassID ; } } return - 1 ; } </s>

Given a machine instruction descriptor , returns the register class constraint for OpNum , or NULL .


<s> void sparc_expand_vector_init ( rtx target , rtx vals ) { const machine_mode mode = GET_MODE ( target ) ; const machine_mode inner_mode = GET_MODE_INNER ( mode ) ; const int n_elts = GET_MODE_NUNITS ( mode ) ; int i , n_var = 0 ; bool all_same = true ; rtx mem ; for ( i = 0 ; i < n_elts ; i ++ ) { rtx x = XVECEXP ( vals , 0 , i ) ; if ( ! ( CONST_SCALAR_INT_P ( x ) || CONST_DOUBLE_P ( x ) || CONST_FIXED_P ( x ) ) ) n_var ++ ; if ( i > 0 && ! rtx_equal_p ( x , XVECEXP ( vals , 0 , 0 ) ) ) all_same = false ; } if ( n_var == 0 ) { emit_move_insn ( target , gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , 0 ) ) ) ; return ; } if ( GET_MODE_SIZE ( inner_mode ) == GET_MODE_SIZE ( mode ) ) { if ( GET_MODE_SIZE ( inner_mode ) == 4 ) { emit_move_insn ( gen_lowpart ( SImode , target ) , gen_lowpart ( SImode , XVECEXP ( vals , 0 , 0 ) ) ) ; return ; } else if ( GET_MODE_SIZE ( inner_mode ) == 8 ) { emit_move_insn ( gen_lowpart ( DImode , target ) , gen_lowpart ( DImode , XVECEXP ( vals , 0 , 0 ) ) ) ; return ; } } else if ( GET_MODE_SIZE ( inner_mode ) == GET_MODE_SIZE ( word_mode ) && GET_MODE_SIZE ( mode ) == 2 * GET_MODE_SIZE ( word_mode ) ) { emit_move_insn ( gen_highpart ( word_mode , target ) , gen_lowpart ( word_mode , XVECEXP ( vals , 0 , 0 ) ) ) ; emit_move_insn ( gen_lowpart ( word_mode , target ) , gen_lowpart ( word_mode , XVECEXP ( vals , 0 , 1 ) ) ) ; return ; } if ( all_same && GET_MODE_SIZE ( mode ) == 8 ) { if ( TARGET_VIS2 ) { vector_init_bshuffle ( target , XVECEXP ( vals , 0 , 0 ) , mode , inner_mode ) ; return ; } if ( mode == V8QImode ) { vector_init_fpmerge ( target , XVECEXP ( vals , 0 , 0 ) ) ; return ; } if ( mode == V4HImode ) { vector_init_faligndata ( target , XVECEXP ( vals , 0 , 0 ) ) ; return ; } } mem = assign_stack_temp ( mode , GET_MODE_SIZE ( mode ) ) ; for ( i = 0 ; i < n_elts ; i ++ ) emit_move_insn ( adjust_address_nv ( mem , inner_mode , i * GET_MODE_SIZE ( inner_mode ) ) , XVECEXP ( vals , 0 , i ) ) ; emit_move_insn ( target , mem ) ; } </s>

Emit code to initialize TARGET to values for individual fields VALS .


<s> unsigned int pure_scalable_type_info :: num_zr ( ) const { unsigned int res = 0 ; for ( unsigned int i = 0 ; i < pieces . length ( ) ; ++ i ) res += pieces [ i ] . num_zr ; return res ; } </s>

Return the total number of vector registers required by the PST .


<s> MCSymbol * LanaiMCInstLower :: GetBlockAddressSymbol ( const MachineOperand & MO ) const { return Printer . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; } </s>

Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block .


<s> bool WebAssemblyTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( AM . BaseOffs < 0 ) return false ; if ( AM . Scale != 0 ) return false ; return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> StringRef getName ( ) const { return SectionName ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


Targets may add passes immediately before machine code is emitted in this callback .


<s> FastISel * WebAssemblyTargetLowering :: createFastISel ( FunctionLoweringInfo & FuncInfo , const TargetLibraryInfo * LibInfo ) const { return WebAssembly :: createFastISel ( FuncInfo , LibInfo ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> rtx function_expander :: use_contiguous_prefetch_insn ( insn_code icode ) { add_input_operand ( icode , args [ 0 ] ) ; add_address_operand ( get_contiguous_base ( VNx16QImode ) ) ; for ( unsigned int i = args . length ( ) - 3 ; i < args . length ( ) ; ++ i ) add_input_operand ( icode , args [ i ] ) ; return generate_insn ( icode ) ; } </s>

Implement the call using instruction ICODE , which prefetches from address operand 1 under the control of predicate operand 0 . Operands 2 , 3 and 4 respectively specify the svprfop value , the PREFETCH rw flag and the PREFETCH locality .


<s> static int frv_string_begins_with ( const char * name , const char * prefix ) { const int prefix_len = strlen ( prefix ) ; return ( strncmp ( name , prefix , prefix_len ) == 0 ) ; } </s>

Return true if NAME ( a STRING_CST node ) begins with PREFIX .


<s> static bool rs6000_can_eliminate ( const int from , const int to ) { return ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : from == RS6000_PIC_OFFSET_TABLE_REGNUM ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || constant_pool_empty_p ( ) : true ) ; } </s>

Given FROM and TO register numbers , say whether this elimination is allowed . Frame pointer elimination is automatically handled . For the RS/6000 , if frame pointer elimination is being done , we would like to convert ap into fp , not sp . We need r30 if -mminimal-toc was specified , and there are constant pool references .


<s> unsigned int arm_dbx_register_number ( unsigned int regno ) { if ( regno < 16 ) return regno ; if ( IS_VFP_REGNUM ( regno ) ) { if ( VFP_REGNO_OK_FOR_SINGLE ( regno ) ) return 64 + regno - FIRST_VFP_REGNUM ; else return 256 + ( regno - FIRST_VFP_REGNUM ) / 2 ; } if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return 104 + regno - FIRST_IWMMXT_GR_REGNUM ; if ( IS_IWMMXT_REGNUM ( regno ) ) return 112 + regno - FIRST_IWMMXT_REGNUM ; gcc_unreachable ( ) ; } </s>

Map internal gcc register numbers to DWARF2 register numbers .


"Unexpected data type for Gather/Scatter"

Calculate the cost of Gather / Scatter operation .


<s> static rtx frv_legitimize_tls_address ( rtx addr , enum tls_model model ) { rtx dest , tp = gen_rtx_REG ( Pmode , 29 ) ; rtx picreg = get_hard_reg_initial_val ( Pmode , 15 ) ; switch ( model ) { case TLS_MODEL_INITIAL_EXEC : if ( flag_pic == 1 ) { dest = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_tls_load_gottlsoff12 ( dest , addr , picreg ) ) ; dest = gen_rtx_PLUS ( Pmode , tp , dest ) ; } else { rtx tmp = gen_reg_rtx ( Pmode ) ; dest = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_tlsoff_hilo ( tmp , addr , GEN_INT ( R_FRV_GOTTLSOFF_HI ) ) ) ; emit_insn ( gen_tls_tlsoff_ld ( dest , picreg , tmp , addr ) ) ; dest = gen_rtx_PLUS ( Pmode , tp , dest ) ; } break ; case TLS_MODEL_LOCAL_DYNAMIC : { rtx reg , retval ; if ( TARGET_INLINE_PLT ) retval = gen_inlined_tls_plt ( GEN_INT ( 0 ) ) ; else { retval = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_call_gettlsoff ( retval , GEN_INT ( 0 ) , picreg ) ) ; } reg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( reg , gen_rtx_PLUS ( Pmode , retval , tp ) ) ) ; dest = gen_tlsmoff ( addr , reg ) ; break ; } case TLS_MODEL_LOCAL_EXEC : dest = gen_tlsmoff ( addr , gen_rtx_REG ( Pmode , 29 ) ) ; break ; case TLS_MODEL_GLOBAL_DYNAMIC : { rtx retval ; if ( TARGET_INLINE_PLT ) retval = gen_inlined_tls_plt ( addr ) ; else { retval = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_call_gettlsoff ( retval , addr , picreg ) ) ; } dest = gen_rtx_PLUS ( Pmode , retval , tp ) ; break ; } default : gcc_unreachable ( ) ; } return dest ; } </s>


<s> NodeId DataFlowGraph :: id ( const NodeBase * P ) const { if ( P == nullptr ) return 0 ; return Memory . id ( P ) ; } </s>


<s> void R600InstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & O ) { O . flush ( ) ; printInstruction ( MI , Address , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


"invalid argument to built-in function %s"

Return true if OPVAL can be used for operand OPNUM of instruction ICODE . The instruction should require a constant operand of some sort . The function prints an error if OPVAL is not valid .


<s> MachineInstrBuilder buildLoad ( const DstOp & Res , Register Addr , uint64_t Size , MachinePointerInfo & MPO ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , Size , inferAlignFromPtrInfo ( MF , MPO ) ) ; return MIRBuilder . buildLoad ( Res , Addr , * MMO ) ; } </s>

Build and insert a G_LOAD instruction , while constructing the MachineMemOperand .


<s>
const
char
*
output_probe_stack_range
(
rtx
reg1
,
rtx
reg2
)
{
static
int
labelno
=
0
;
char
loop_lab
[
32
]
,
end_lab
[
32
]
;
rtx
xops
[
2
]
;
ASM_GENERATE_INTERNAL_LABEL
(
loop_lab
,
"LPSRL"
,
labelno
)
;
ASM_GENERATE_INTERNAL_LABEL
(
end_lab
,
"LPSRE"
,
labelno
++
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
loop_lab
)
;
xops
[
0
]
=
reg1
;
xops
[
1
]
=
reg2
;
output_asm_insn
(
"cmp\t%0, %1"
,
xops
)
;
if
(
TARGET_ARCH64
)
fputs
(
"\tbe,pn\t%xcc,"
,
asm_out_file
)
;
else
fputs
(
"\tbe\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
end_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
xops
[
1
]
=
GEN_INT
(
PROBE_INTERVAL
)
;
output_asm_insn
(
" add\t%0, %1, %0"
,
xops
)
;
if
(
TARGET_ARCH64
)
fputs
(
"\tba,pt\t%xcc,"
,
asm_out_file
)
;
else
fputs
(
"\tba\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
loop_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
xops
[
1
]
=
GEN_INT
(
SPARC_STACK_BIAS
)
;
output_asm_insn
(
" st\t%%g0, [%0+%1]"
,
xops
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
end_lab
)
;
return
""
;
}
</s>

Wrapper around the output_probe_stack_range routines .


<s>
static
void
dump_target_flag_bits
(
const
int
flags
)
{
if
(
flags
&
MASK_64BIT
)
fprintf
(
stderr
,
"64BIT "
)
;
if
(
flags
&
MASK_APP_REGS
)
fprintf
(
stderr
,
"APP_REGS "
)
;
if
(
flags
&
MASK_FASTER_STRUCTS
)
fprintf
(
stderr
,
"FASTER_STRUCTS "
)
;
if
(
flags
&
MASK_FLAT
)
fprintf
(
stderr
,
"FLAT "
)
;
if
(
flags
&
MASK_FMAF
)
fprintf
(
stderr
,
"FMAF "
)
;
if
(
flags
&
MASK_FPU
)
fprintf
(
stderr
,
"FPU "
)
;
if
(
flags
&
MASK_HARD_QUAD
)
fprintf
(
stderr
,
"HARD_QUAD "
)
;
if
(
flags
&
MASK_POPC
)
fprintf
(
stderr
,
"POPC "
)
;
if
(
flags
&
MASK_PTR64
)
fprintf
(
stderr
,
"PTR64 "
)
;
if
(
flags
&
MASK_STACK_BIAS
)
fprintf
(
stderr
,
"STACK_BIAS "
)
;
if
(
flags
&
MASK_UNALIGNED_DOUBLES
)
fprintf
(
stderr
,
"UNALIGNED_DOUBLES "
)
;
if
(
flags
&
MASK_V8PLUS
)
fprintf
(
stderr
,
"V8PLUS "
)
;
if
(
flags
&
MASK_VIS
)
fprintf
(
stderr
,
"VIS "
)
;
if
(
flags
&
MASK_VIS2
)
fprintf
(
stderr
,
"VIS2 "
)
;
if
(
flags
&
MASK_VIS3
)
fprintf
(
stderr
,
"VIS3 "
)
;
if
(
flags
&
MASK_CBCOND
)
fprintf
(
stderr
,
"CBCOND "
)
;
if
(
flags
&
MASK_DEPRECATED_V8_INSNS
)
fprintf
(
stderr
,
"DEPRECATED_V8_INSNS "
)
;
if
(
flags
&
MASK_SPARCLET
)
fprintf
(
stderr
,
"SPARCLET "
)
;
if
(
flags
&
MASK_SPARCLITE
)
fprintf
(
stderr
,
"SPARCLITE "
)
;
if
(
flags
&
MASK_V8
)
fprintf
(
stderr
,
"V8 "
)
;
if
(
flags
&
MASK_V9
)
fprintf
(
stderr
,
"V9 "
)
;
}
</s>

sparc
"64BIT "
"APP_REGS "
"FASTER_STRUCTS "
"FLAT "
"FMAF "
"FPU "
"HARD_QUAD "
"POPC "
"PTR64 "
"STACK_BIAS "
"UNALIGNED_DOUBLES "
"V8PLUS "
"VIS "
"VIS2 "
"VIS3 "
"CBCOND "
"DEPRECATED_V8_INSNS "
"SPARCLET "
"SPARCLITE "
"V8 "
"V9 "


<s> int mmix_extra_constraint ( rtx x , int c , int strict ) { HOST_WIDEST_INT value ; if ( c == 'U' ) return strict ? strict_memory_address_p ( Pmode , x ) : memory_address_p ( Pmode , x ) ; if ( c == 'R' ) return GET_CODE ( x ) != CONST_INT && GET_CODE ( x ) != CONST_DOUBLE && mmix_constant_address_p ( x ) && ( ! TARGET_BASE_ADDRESSES || ( GET_CODE ( x ) == LABEL_REF || ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_FLAG ( x ) ) ) ) ; if ( GET_CODE ( x ) != CONST_DOUBLE || GET_MODE ( x ) != VOIDmode ) return 0 ; value = mmix_intval ( x ) ; if ( c == 'S' ) return mmix_shiftable_wyde_value ( value ) ; else if ( c == 'T' ) return mmix_shiftable_wyde_value ( ~ value ) ; return 0 ; } </s>

EXTRA_CONSTRAINT . We need this since our constants are not always expressible as CONST_INT : s , but rather often as CONST_DOUBLE : s .


<s> SDNode * SITargetLowering :: legalizeTargetIndependentNode ( SDNode * Node , SelectionDAG & DAG ) const { if ( Node -> getOpcode ( ) == ISD :: CopyToReg ) { RegisterSDNode * DestReg = cast < RegisterSDNode > ( Node -> getOperand ( 1 ) ) ; SDValue SrcVal = Node -> getOperand ( 2 ) ; if ( SrcVal . getValueType ( ) == MVT :: i1 && DestReg -> getReg ( ) . isPhysical ( ) ) { SDLoc SL ( Node ) ; MachineRegisterInfo & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue VReg = DAG . getRegister ( MRI . createVirtualRegister ( & AMDGPU :: VReg_1RegClass ) , MVT :: i1 ) ; SDNode * Glued = Node -> getGluedNode ( ) ; SDValue ToVReg = DAG . getCopyToReg ( Node -> getOperand ( 0 ) , SL , VReg , SrcVal , SDValue ( Glued , Glued ? Glued -> getNumValues ( ) - 1 : 0 ) ) ; SDValue ToResultReg = DAG . getCopyToReg ( ToVReg , SL , SDValue ( DestReg , 0 ) , VReg , ToVReg . getValue ( 1 ) ) ; DAG . ReplaceAllUsesWith ( Node , ToResultReg . getNode ( ) ) ; DAG . RemoveDeadNode ( Node ) ; return ToResultReg . getNode ( ) ; } } SmallVector < SDValue , 8 > Ops ; for ( unsigned i = 0 ; i < Node -> getNumOperands ( ) ; ++ i ) { if ( ! isFrameIndexOp ( Node -> getOperand ( i ) ) ) { Ops . push_back ( Node -> getOperand ( i ) ) ; continue ; } SDLoc DL ( Node ) ; Ops . push_back ( SDValue ( DAG . getMachineNode ( AMDGPU :: S_MOV_B32 , DL , Node -> getOperand ( i ) . getValueType ( ) , Node -> getOperand ( i ) ) , 0 ) ) ; } return DAG . UpdateNodeOperands ( Node , Ops ) ; } </s>

Legalize target independent instructions ( e.g .


<s>
static
void
arm_output_mi_thunk
(
FILE
*
file
,
tree
thunk
ATTRIBUTE_UNUSED
,
HOST_WIDE_INT
delta
,
HOST_WIDE_INT
vcall_offset
ATTRIBUTE_UNUSED
,
tree
function
)
{
static
int
thunk_label
=
0
;
char
label
[
256
]
;
int
mi_delta
=
delta
;
const
char
*
const
mi_op
=
mi_delta
<
0
"sub"
:
"add"
;
int
shift
=
0
;
int
this_regno
=
(
aggregate_value_p
(
TREE_TYPE
(
TREE_TYPE
(
function
)
)
,
function
)
1
:
0
)
;
if
(
mi_delta
<
0
)
mi_delta
=
mi_delta
;
if
(
TARGET_THUMB
)
{
int
labelno
=
thunk_label
++
;
ASM_GENERATE_INTERNAL_LABEL
(
label
,
"LTHUMBFUNC"
,
labelno
)
;
fputs
(
"\tldr\tr12, "
,
file
)
;
assemble_name
(
file
,
label
)
;
fputc
(
'\n'
,
file
)
;
}
while
(
mi_delta
!=
0
)
{
if
(
(
mi_delta
&
(
3
<<
shift
)
)
==
0
)
shift
+=
2
;
else
{
asm_fprintf
(
file
,
"\t%s\t%r, %r, #%d\n"
,
mi_op
,
this_regno
,
this_regno
,
mi_delta
&
(
0xff
<<
shift
)
)
;
mi_delta
&=
~
(
0xff
<<
shift
)
;
shift
+=
8
;
}
}
if
(
TARGET_THUMB
)
{
fprintf
(
file
,
"\tbx\tr12\n"
)
;
ASM_OUTPUT_ALIGN
(
file
,
2
)
;
assemble_name
(
file
,
label
)
;
fputs
(
":\n"
,
file
)
;
assemble_integer
(
XEXP
(
DECL_RTL
(
function
)
,
0
)
,
4
,
BITS_PER_WORD
,
1
)
;
}
else
{
fputs
(
"\tb\t"
,
file
)
;
assemble_name
(
file
,
XSTR
(
XEXP
(
DECL_RTL
(
function
)
,
0
)
,
0
)
)
;
if
(
NEED_PLT_RELOC
)
fputs
(
"(PLT)"
,
file
)
;
fputc
(
'\n'
,
file
)
;
}
}
</s>

Output code to add DELTA to the first argument , and then jump to FUNCTION . Used for C++ multiple inheritance .


<s> NyuziTargetLowering :: ConstraintType NyuziTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 's' : case 'r' : case 'v' : return C_RegisterClass ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> static int ia64_adjust_cost ( rtx_insn * insn , int dep_type1 , rtx_insn * dep_insn , int cost , dw_t dw ) { enum reg_note dep_type = ( enum reg_note ) dep_type1 ; enum attr_itanium_class dep_class ; enum attr_itanium_class insn_class ; insn_class = ia64_safe_itanium_class ( insn ) ; dep_class = ia64_safe_itanium_class ( dep_insn ) ; if ( dep_type == REG_DEP_TRUE && ( dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF ) && ( insn_class == ITANIUM_CLASS_BR || insn_class == ITANIUM_CLASS_SCALL ) ) return 0 ; if ( dw == MIN_DEP_WEAK ) return PARAM_VALUE ( PARAM_SCHED_MEM_TRUE_DEP_COST ) ; else if ( dw > MIN_DEP_WEAK ) { if ( mflag_sched_fp_mem_deps_zero_cost && dep_class == ITANIUM_CLASS_STF ) return 0 ; else return cost ; } if ( dep_type != REG_DEP_OUTPUT ) return cost ; if ( dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF || insn_class == ITANIUM_CLASS_ST || insn_class == ITANIUM_CLASS_STF ) return 0 ; return cost ; } </s>

Adjust the cost of a scheduling dependency . Return the new cost of a dependency LINK or INSN on DEP_INSN . COST is the current cost .


<s> NVPTXSubtarget :: NVPTXSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool is64Bit ) : NVPTXGenSubtargetInfo ( TT , CPU , FS ) , Is64Bit ( is64Bit ) , PTXVersion ( 0 ) , SmVersion ( 20 ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( ( const NVPTXTargetMachine & ) TM , * this ) , TSInfo ( TM . getDataLayout ( ) ) , FrameLowering ( * this ) { Triple T ( TT ) ; if ( T . getOS ( ) == Triple :: NVCL ) drvInterface = NVPTX :: NVCL ; else drvInterface = NVPTX :: CUDA ; } </s>

This constructor initializes the data members to match that of the specified module .

NVPTX NVPTX NVPTX NVPTX 0 20 NVPTX NVPTX::NVCL NVPTX::CUDA


<s> static bool has_non_address_hard_reg ( rtx_insn * insn ) { df_ref ref ; FOR_EACH_INSN_DEF ( ref , insn ) if ( HARD_REGISTER_P ( DF_REF_REAL_REG ( ref ) ) && ! DF_REF_FLAGS_IS_SET ( ref , DF_REF_MUST_CLOBBER ) && DF_REF_REGNO ( ref ) != FLAGS_REG ) return true ; FOR_EACH_INSN_USE ( ref , insn ) if ( ! DF_REF_REG_MEM_P ( ref ) && HARD_REGISTER_P ( DF_REF_REAL_REG ( ref ) ) ) return true ; return false ; } </s>

Return 1 if INSN uses or defines a hard register . Hard register uses in a memory address are ignored . Clobbers and flags definitions are ignored .


<s> SDNode * LC3DAGToDAGISel :: Select ( SDNode * N ) { switch ( N -> getOpcode ( ) ) { case ISD :: Constant : return SelectMoveImmediate ( N ) ; case ISD :: BR_CC : return SelectConditionalBranch ( N ) ; } return SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> bool HexagonInstrInfo :: isPredicable ( const MachineInstr & MI ) const { if ( ! MI . getDesc ( ) . isPredicable ( ) ) return false ; if ( MI . isCall ( ) || isTailCall ( MI ) ) { if ( ! Subtarget . usePredicatedCalls ( ) ) return false ; } if ( ! Subtarget . hasV62TOps ( ) ) { switch ( MI . getOpcode ( ) ) { case Hexagon :: V6_vL32b_ai : case Hexagon :: V6_vL32b_pi : case Hexagon :: V6_vL32b_ppu : case Hexagon :: V6_vL32b_cur_ai : case Hexagon :: V6_vL32b_cur_pi : case Hexagon :: V6_vL32b_cur_ppu : case Hexagon :: V6_vL32b_nt_ai : case Hexagon :: V6_vL32b_nt_pi : case Hexagon :: V6_vL32b_nt_ppu : case Hexagon :: V6_vL32b_tmp_ai : case Hexagon :: V6_vL32b_tmp_pi : case Hexagon :: V6_vL32b_tmp_ppu : case Hexagon :: V6_vL32b_nt_cur_ai : case Hexagon :: V6_vL32b_nt_cur_pi : case Hexagon :: V6_vL32b_nt_cur_ppu : case Hexagon :: V6_vL32b_nt_tmp_ai : case Hexagon :: V6_vL32b_nt_tmp_pi : case Hexagon :: V6_vL32b_nt_tmp_ppu : return false ; } } return true ; } </s>

Return true if the specified instruction can be predicated .


<s> static rtx_insn * rs6000_emit_savres_rtx ( rs6000_stack_t * info , rtx frame_reg_rtx , int save_area_offset , int lr_offset , machine_mode reg_mode , int sel ) { int i ; int offset , start_reg , end_reg , n_regs , use_reg ; int reg_size = GET_MODE_SIZE ( reg_mode ) ; rtx sym ; rtvec p ; rtx par ; rtx_insn * insn ; offset = 0 ; start_reg = ( ( sel & SAVRES_REG ) == SAVRES_GPR ? info -> first_gp_reg_save : ( sel & SAVRES_REG ) == SAVRES_FPR ? info -> first_fp_reg_save : ( sel & SAVRES_REG ) == SAVRES_VR ? info -> first_altivec_reg_save : - 1 ) ; end_reg = ( ( sel & SAVRES_REG ) == SAVRES_GPR ? 32 : ( sel & SAVRES_REG ) == SAVRES_FPR ? 64 : ( sel & SAVRES_REG ) == SAVRES_VR ? LAST_ALTIVEC_REGNO + 1 : - 1 ) ; n_regs = end_reg - start_reg ; p = rtvec_alloc ( 3 + ( ( sel & SAVRES_LR ) ? 1 : 0 ) + ( ( sel & SAVRES_REG ) == SAVRES_VR ? 1 : 0 ) + n_regs ) ; if ( ! ( sel & SAVRES_SAVE ) && ( sel & SAVRES_LR ) ) RTVEC_ELT ( p , offset ++ ) = ret_rtx ; RTVEC_ELT ( p , offset ++ ) = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; sym = rs6000_savres_routine_sym ( info , sel ) ; RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , sym ) ; use_reg = ptr_regno_for_savres ( sel ) ; if ( ( sel & SAVRES_REG ) == SAVRES_VR ) { RTVEC_ELT ( p , offset ++ ) = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , use_reg ) ) ; RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , gen_rtx_REG ( Pmode , 0 ) ) ; } else RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , gen_rtx_REG ( Pmode , use_reg ) ) ; for ( i = 0 ; i < end_reg - start_reg ; i ++ ) RTVEC_ELT ( p , i + offset ) = gen_frame_set ( gen_rtx_REG ( reg_mode , start_reg + i ) , frame_reg_rtx , save_area_offset + reg_size * i , ( sel & SAVRES_SAVE ) != 0 ) ; if ( ( sel & SAVRES_SAVE ) && ( sel & SAVRES_LR ) ) RTVEC_ELT ( p , i + offset ) = gen_frame_store ( gen_rtx_REG ( Pmode , 0 ) , frame_reg_rtx , lr_offset ) ; par = gen_rtx_PARALLEL ( VOIDmode , p ) ; if ( ! ( sel & SAVRES_SAVE ) && ( sel & SAVRES_LR ) ) { insn = emit_jump_insn ( par ) ; JUMP_LABEL ( insn ) = ret_rtx ; } else insn = emit_insn ( par ) ; return insn ; } </s>

Construct a parallel rtx describing the effect of a call to an out-of-line register save/restore routine , and emit the insn or jump_insn as appropriate .


<s> void rl78_register_pragmas ( void ) { c_register_addr_space ( "__near" , ADDR_SPACE_NEAR ) ; c_register_addr_space ( "__far" , ADDR_SPACE_FAR ) ; } </s>


<s>
bool
MipsAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
SmallVectorImpl
<
MCParsedAsmOperand
*
>
&
Operands
)
{
if
(
requestsDoubleOperand
(
Name
)
)
{
setFpFormat
(
FP_FORMAT_D
)
;
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Name
,
NameLoc
)
)
;
}
else
{
setDefaultFpFormat
(
)
;
size_t
Start
=
0
,
Next
=
Name
.
find
(
'.'
)
;
StringRef
Mnemonic
=
Name
.
slice
(
Start
,
Next
)
;
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Mnemonic
,
NameLoc
)
)
;
if
(
Next
!=
StringRef
::
npos
)
{
size_t
Dot
=
Name
.
find
(
'.'
,
Next
+
1
)
;
StringRef
Format
=
Name
.
slice
(
Next
,
Dot
)
;
if
(
Dot
==
StringRef
::
npos
)
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Format
,
NameLoc
)
)
;
else
{
if
(
Name
.
startswith
(
"c."
)
)
{
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
"."
,
NameLoc
)
)
;
int
Cc
=
ConvertCcString
(
Format
)
;
if
(
Cc
==
1
)
{
return
Error
(
NameLoc
,
"Invalid conditional code"
)
;
}
SMLoc
E
=
SMLoc
::
getFromPointer
(
Parser
.
getTok
(
)
.
getLoc
(
)
.
getPointer
(
)
1
)
;
Operands
.
push_back
(
MipsOperand
::
CreateImm
(
MCConstantExpr
::
Create
(
Cc
,
getContext
(
)
)
,
NameLoc
,
E
)
)
;
}
else
{
return
parseMathOperation
(
Name
,
NameLoc
,
Operands
)
;
}
Format
=
Name
.
slice
(
Dot
,
StringRef
::
npos
)
;
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Format
,
NameLoc
)
)
;
}
setFpFormat
(
Format
)
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
EatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
EatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
EatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Mips
Mips
MipsOperand::CreateToken
0
MipsOperand::CreateToken
1
MipsOperand::CreateToken
"c."
MipsOperand::CreateToken
"."
1
"Invalid conditional code"
1
MipsOperand::CreateImm
MipsOperand::CreateToken
"unexpected token in argument list"
"unexpected token in argument list"
"unexpected token in argument list"


<s>
void
emitLabel
(
MCSymbol
*
Symbol
,
SMLoc
Loc
=
SMLoc
(
)
)
override
{
if
(
Symbol
->
isUndefined
(
)
)
return
;
assert
(
getCurrentSection
(
)
.
first
&&
"Cannot emit before setting section!"
)
;
AssignFragment
(
Symbol
,
&
getCurrentSection
(
)
.
first
->
getDummyFragment
(
)
)
;
}
</s>

Emit a label for Symbol into the current section .

Patmos
"Cannot emit before setting section!"


<s> static int rs6000_get_some_local_dynamic_name_1 ( rtx * px , void * data ATTRIBUTE_UNUSED ) { rtx x = * px ; if ( GET_CODE ( x ) == SYMBOL_REF ) { const char * str = XSTR ( x , 0 ) ; if ( SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_DYNAMIC ) { cfun -> machine -> some_ld_name = str ; return 1 ; } } return 0 ; } </s>

Helper function for rs6000_get_some_local_dynamic_name .


<s> void x86_elf_aligned_common ( FILE * file , const char * name , unsigned HOST_WIDE_INT size , int align ) { if ( ( ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC ) && size > ( unsigned int ) ix86_section_threshold ) fprintf ( file , ".largecomm\t" ) ; else fprintf ( file , "%s" , COMMON_ASM_OP ) ; assemble_name ( file , name ) ; fprintf ( file , "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n" , size , align / BITS_PER_UNIT ) ; } </s>

This says how to output assembler code to declare an uninitialized external linkage data object . For medium model x86-64 we need to use .largecomm opcode for large objects .


<s> bool SIInsertSkips :: runOnMachineFunction ( MachineFunction & MF ) { const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; SkipThreshold = SkipThresholdFlag ; SmallVector < MachineInstr * , 4 > KillInstrs ; bool MadeChange = false ; for ( MachineBasicBlock & MBB : MF ) { MachineBasicBlock :: iterator I , Next ; for ( I = MBB . begin ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; switch ( MI . getOpcode ( ) ) { case AMDGPU :: SI_MASK_BRANCH : MadeChange |= skipMaskBranch ( MI , MBB ) ; break ; case AMDGPU :: S_BRANCH : if ( MBB . isLayoutSuccessor ( MI . getOperand ( 0 ) . getMBB ( ) ) ) { assert ( & MI == & MBB . back ( ) ) ; MI . eraseFromParent ( ) ; MadeChange = true ; } break ; case AMDGPU :: SI_KILL_F32_COND_IMM_TERMINATOR : case AMDGPU :: SI_KILL_I1_TERMINATOR : { MadeChange = true ; bool CanKill = kill ( MI ) ; if ( CanKill && MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: AMDGPU_PS && dominatesAllReachable ( MBB ) ) { KillInstrs . push_back ( & MI ) ; } else { MI . eraseFromParent ( ) ; } break ; } case AMDGPU :: SI_KILL_CLEANUP : if ( MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: AMDGPU_PS && dominatesAllReachable ( MBB ) ) { KillInstrs . push_back ( & MI ) ; } else { MI . eraseFromParent ( ) ; } break ; default : break ; } } } for ( MachineInstr * Kill : KillInstrs ) { skipIfDead ( * Kill -> getParent ( ) , std :: next ( Kill -> getIterator ( ) ) , Kill -> getDebugLoc ( ) ) ; Kill -> eraseFromParent ( ) ; } KillInstrs . clear ( ) ; EarlyExitBlock = nullptr ; return MadeChange ; } </s>

runOnMachineFunction - Emit the function body .


<s>
MachineBasicBlock
*
FISCTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
const
TargetInstrInfo
&
TII
=
*
BB
->
getParent
(
)
->
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
=
MI
->
getDebugLoc
(
)
;
assert
(
MI
->
getOpcode
(
)
==
FISC
::
Select
&&
"Unexpected instr type to insert"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
I
=
++
BB
->
getIterator
(
)
;
MachineBasicBlock
*
ThisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
Copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
Copy1MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
F
->
insert
(
I
,
Copy0MBB
)
;
F
->
insert
(
I
,
Copy1MBB
)
;
Copy1MBB
->
splice
(
Copy1MBB
->
begin
(
)
,
BB
,
std
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
BB
->
end
(
)
)
;
Copy1MBB
->
transferSuccessorsAndUpdatePHIs
(
BB
)
;
BB
->
addSuccessor
(
Copy0MBB
)
;
BB
->
addSuccessor
(
Copy1MBB
)
;
BuildMI
(
BB
,
DL
,
TII
.
get
(
FISC
::
Bcc
)
)
.
addOperand
(
MI
->
getOperand
(
3
)
)
.
addMBB
(
Copy1MBB
,
FISCII
::
MO_CALL19
)
;
BB
=
Copy0MBB
;
BB
->
addSuccessor
(
Copy1MBB
)
;
BB
=
Copy1MBB
;
BuildMI
(
*
BB
,
BB
->
begin
(
)
,
DL
,
TII
.
get
(
FISC
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
Copy0MBB
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
ThisMBB
)
;
MI
->
eraseFromParent
(
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static bool tryAddingSymbolicOperand ( int64_t Value , bool isBranch , uint64_t Address , uint64_t Offset , uint64_t Width , MCInst & MI , const MCDisassembler * Decoder ) { return Decoder -> tryAddingSymbolicOperand ( MI , Value , Address , isBranch , Offset , Width ) ; } </s>

Try to add a symbolic operand instead of Value to the MCInst .


<s> bool PPCRegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , unsigned Reg , int & FrameIdx ) const { if ( Subtarget . isSVR4ABI ( ) && PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ) { if ( Subtarget . isPPC64 ( ) ) { FrameIdx = 0 ; } else if ( CRSpillFrameIdx ) { FrameIdx = CRSpillFrameIdx ; } else { MachineFrameInfo * MFI = ( ( MachineFunction & ) MF ) . getFrameInfo ( ) ; FrameIdx = MFI -> CreateFixedObject ( ( uint64_t ) 4 , ( int64_t ) - 4 , true ) ; CRSpillFrameIdx = FrameIdx ; } return true ; } return false ; } </s>

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register .


<s> void X86FrameLowering :: BuildCFI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , const MCCFIInstruction & CFIInst ) const { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CFIIndex = MF . getMMI ( ) . addFrameInst ( CFIInst ) ; BuildMI ( MBB , MBBI , DL , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } </s>

Wraps up getting a CFI index and building a MachineInstr for it .


<s> bool LanaiAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] ) return true ; switch ( ExtraCode [ 0 ] ) { case 'H' : { if ( OpNo == 0 ) return true ; const MachineOperand & FlagsOP = MI -> getOperand ( OpNo - 1 ) ; if ( ! FlagsOP . isImm ( ) ) return true ; unsigned Flags = FlagsOP . getImm ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; if ( NumVals != 2 ) return true ; unsigned RegOp = OpNo + 1 ; if ( RegOp >= MI -> getNumOperands ( ) ) return true ; const MachineOperand & MO = MI -> getOperand ( RegOp ) ; if ( ! MO . isReg ( ) ) return true ; unsigned Reg = MO . getReg ( ) ; O << LanaiInstPrinter :: getRegisterName ( Reg ) ; return false ; } default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , O ) ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> void BPFAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const { if ( Fixup . getKind ( ) == FK_SecRel_4 || Fixup . getKind ( ) == FK_SecRel_8 ) { assert ( Value == 0 ) ; } else if ( Fixup . getKind ( ) == FK_Data_4 ) { support :: endian :: write < uint32_t > ( & Data [ Fixup . getOffset ( ) ] , Value , Endian ) ; } else if ( Fixup . getKind ( ) == FK_Data_8 ) { support :: endian :: write < uint64_t > ( & Data [ Fixup . getOffset ( ) ] , Value , Endian ) ; } else if ( Fixup . getKind ( ) == FK_PCRel_4 ) { Value = ( uint32_t ) ( ( Value - 8 ) / 8 ) ; if ( Endian == support :: little ) { Data [ Fixup . getOffset ( ) + 1 ] = 0x10 ; support :: endian :: write32le ( & Data [ Fixup . getOffset ( ) + 4 ] , Value ) ; } else { Data [ Fixup . getOffset ( ) + 1 ] = 0x1 ; support :: endian :: write32be ( & Data [ Fixup . getOffset ( ) + 4 ] , Value ) ; } } else { assert ( Fixup . getKind ( ) == FK_PCRel_2 ) ; Value = ( uint16_t ) ( ( Value - 8 ) / 8 ) ; support :: endian :: write < uint16_t > ( & Data [ Fixup . getOffset ( ) + 2 ] , Value , Endian ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool MipsInstrInfo :: SafeInFPUDelaySlot ( const MachineInstr & MIInSlot , const MachineInstr & FPUMI ) const { if ( MIInSlot . isInlineAsm ( ) ) return false ; if ( HasFPUDelaySlot ( MIInSlot ) ) return false ; switch ( MIInSlot . getOpcode ( ) ) { case Mips :: BC1F : case Mips :: BC1FL : case Mips :: BC1T : case Mips :: BC1TL : return false ; } for ( const MachineOperand & Op : FPUMI . defs ( ) ) { if ( ! Op . isReg ( ) ) continue ; bool Reads , Writes ; std :: tie ( Reads , Writes ) = MIInSlot . readsWritesVirtualRegister ( Op . getReg ( ) ) ; if ( Reads || Writes ) return false ; } return true ; } </s>

Predicate to determine if an instruction can go in an FPU delay slot .


<s> const MCPhysReg * ARCRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_ARC_SaveList ; } </s>


<s>
void
MetadataStreamer
::
dump
(
StringRef
HSAMetadataString
)
const
{
errs
(
)
<<
"AMDGPU HSA Metadata:\n"
<<
HSAMetadataString
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .


<s>
bool
Z80RegisterInfo
::
shouldCoalesce
(
MachineInstr
*
MI
,
const
TargetRegisterClass
*
SrcRC
,
unsigned
SrcSubReg
,
const
TargetRegisterClass
*
DstRC
,
unsigned
DstSubReg
,
const
TargetRegisterClass
*
NewRC
,
LiveIntervals
&
LIS
)
const
{
const
TargetRegisterInfo
&
TRI
=
*
MI
->
getParent
(
)
->
getParent
(
)
->
getRegInfo
(
)
.
getTargetRegisterInfo
(
)
;
(
void
)
TRI
;
DEBUG
(
dbgs
(
)
<<
TRI
.
getRegClassName
(
SrcRC
)
<<
'['
<<
SrcRC
->
getNumRegs
(
)
<<
"]:"
<<
(
SrcSubReg
TRI
.
getSubRegIndexName
(
SrcSubReg
)
:
""
)
<<
" -> "
<<
TRI
.
getRegClassName
(
DstRC
)
<<
'['
<<
DstRC
->
getNumRegs
(
)
<<
"]:"
<<
(
DstSubReg
TRI
.
getSubRegIndexName
(
DstSubReg
)
:
""
)
<<
' '
<<
TRI
.
getRegClassName
(
NewRC
)
<<
'['
<<
NewRC
->
getNumRegs
(
)
<<
"]\n"
)
;
return
std
::
min
(
SrcRC
->
getNumRegs
(
)
,
DstRC
->
getNumRegs
(
)
)
<=
NewRC
->
getNumRegs
(
)
;
}
</s>


<s> static void pa_select_section ( tree exp , int reloc , unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED ) { if ( TREE_CODE ( exp ) == VAR_DECL && TREE_READONLY ( exp ) && ! TREE_THIS_VOLATILE ( exp ) && DECL_INITIAL ( exp ) && ( DECL_INITIAL ( exp ) == error_mark_node || TREE_CONSTANT ( DECL_INITIAL ( exp ) ) ) && ! reloc ) { if ( TARGET_SOM && DECL_ONE_ONLY ( exp ) && ! DECL_WEAK ( exp ) ) som_one_only_readonly_data_section ( ) ; else readonly_data_section ( ) ; } else if ( CONSTANT_CLASS_P ( exp ) && ! reloc ) readonly_data_section ( ) ; else if ( TARGET_SOM && TREE_CODE ( exp ) == VAR_DECL && DECL_ONE_ONLY ( exp ) && ! DECL_WEAK ( exp ) ) som_one_only_data_section ( ) ; else data_section ( ) ; } </s>

On hpux10 , the linker will give an error if we have a reference in the read-only data section to a symbol defined in a shared library . Therefore , expressions that might require a reloc can not be placed in the read-only data section .


<s> static int ix86_mode_entry ( int entity ) { switch ( entity ) { case AVX_U128 : return ix86_avx_u128_mode_entry ( ) ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : case I387_MASK_PM : return I387_CW_ANY ; default : gcc_unreachable ( ) ; } } </s>

Return a mode that ENTITY is assumed to be switched to at function entry .


<s> static bool c6x_output_ttype ( rtx x ) { if ( GET_CODE ( x ) != CONST_INT ) fputs ( "\t.ehtype\t" , asm_out_file ) ; else fputs ( "\t.word\t" , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; fputc ( '\n' , asm_out_file ) ; return TRUE ; } </s>

Output a reference from a function exception table to the type_info object X . Output these via a special assembly directive .


<s> unsigned NVPTXRegisterInfo :: getRARegister ( ) const { return 0 ; } </s>

This method should return the register where the return address can be found .