<s> static bool sh_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( SPECIAL_REGISTER_P ( regno ) ) return mode == SImode ; if ( regno == FPUL_REG ) return ( mode == SImode || mode == SFmode ) ; if ( FP_REGISTER_P ( regno ) && mode == SFmode ) return true ; if ( mode == V2SFmode ) { if ( ( ( FP_REGISTER_P ( regno ) && ( regno - FIRST_FP_REG ) % 2 == 0 ) || GENERAL_REGISTER_P ( regno ) ) ) return true ; else return false ; } if ( mode == V4SFmode ) { if ( ( FP_REGISTER_P ( regno ) && ( regno - FIRST_FP_REG ) % 4 == 0 ) || GENERAL_REGISTER_P ( regno ) ) return true ; else return false ; } if ( mode == V16SFmode ) return regno == FIRST_XD_REG ; if ( FP_REGISTER_P ( regno ) ) { if ( mode == SFmode || mode == SImode || ( ( TARGET_SH2E ) && mode == SCmode ) || ( ( ( TARGET_FPU_DOUBLE && mode == DFmode ) || mode == DCmode ) && ( ( regno - FIRST_FP_REG ) & 1 ) == 0 ) || ( TARGET_SH4 && mode == TImode && ( ( regno - FIRST_FP_REG ) & 3 ) == 0 ) ) return true ; else return false ; } if ( XD_REGISTER_P ( regno ) ) return mode == DFmode ; if ( regno == PR_REG ) return mode == SImode ; if ( regno == FPSCR_REG ) return mode == SImode ; return true ; } </s>

Return true if hard register REGNO can hold a value of machine-mode MODE . We can allow any mode in any general register . The special registers only allow SImode . Do n't allow any mode in the PR . We can not hold DCmode values in the XD registers because alter_reg handles subregs of them incorrectly . We could work around this by spacing the XD registers like the DR registers , but this would require additional memory in every compilation to hold larger register vectors . We could hold SFmode / SCmode values in XD registers , but that would require a tertiary reload when reloading from / to memory , and a secondary reload to reload from / to general regs ; that seems to be a losing proposition . We want to allow TImode FP regs so that when V4SFmode is loaded as TImode , it wo n't be ferried through GP registers first .


<s> bool empty ( ) { return ( ! HaveConst && Q . empty ( ) ) ; } </s>

Determine whether this version information is empty ( e.g. , all version components are zero ) .


<s> bool SystemZCopyPhysRegs :: runOnMachineFunction ( MachineFunction & F ) { TII = static_cast < const SystemZInstrInfo * > ( F . getSubtarget ( ) . getInstrInfo ( ) ) ; MRI = & F . getRegInfo ( ) ; bool Modified = false ; for ( auto & MBB : F ) Modified |= visitMBB ( MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool hasLiveCondCodeDef ( MachineInstr * MI ) { for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == X86 :: EFLAGS && ! MO . isDead ( ) ) { return true ; } } return false ; } </s>

True if MI has a condition code def , e.g .


"eliminateCallFramePseudoInstr size too big: "

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


"%qs and floating point or vector arguments"


<s> bool ARMOptimizeBarriersPass :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; std :: vector < MachineInstr * > ToRemove ; int64_t DMBType = - 1 ; for ( auto & MBB : MF ) { bool IsRemovableNextDMB = false ; for ( auto & MI : MBB ) { if ( MI . getOpcode ( ) == ARM :: DMB ) { if ( IsRemovableNextDMB ) { if ( MI . getOperand ( 0 ) . getImm ( ) == DMBType ) { ToRemove . push_back ( & MI ) ; } else { DMBType = MI . getOperand ( 0 ) . getImm ( ) ; } } else { IsRemovableNextDMB = true ; DMBType = MI . getOperand ( 0 ) . getImm ( ) ; } } else if ( ! CanMovePastDMB ( & MI ) ) { IsRemovableNextDMB = false ; } } } bool Changed = false ; for ( auto MI : ToRemove ) { MI -> eraseFromParent ( ) ; ++ NumDMBsRemoved ; Changed = true ; } return Changed ; } </s>


<s> bool ix86_expand_pextr ( rtx * operands ) { rtx dst = operands [ 0 ] ; rtx src = operands [ 1 ] ; unsigned int size = INTVAL ( operands [ 2 ] ) ; unsigned int pos = INTVAL ( operands [ 3 ] ) ; if ( SUBREG_P ( dst ) ) { if ( SUBREG_BYTE ( dst ) > 0 ) return false ; dst = SUBREG_REG ( dst ) ; } if ( SUBREG_P ( src ) ) { pos += SUBREG_BYTE ( src ) * BITS_PER_UNIT ; src = SUBREG_REG ( src ) ; } switch ( GET_MODE ( src ) ) { case V16QImode : case V8HImode : case V4SImode : case V2DImode : case V1TImode : case TImode : { machine_mode srcmode , dstmode ; rtx d , pat ; dstmode = mode_for_size ( size , MODE_INT , 0 ) ; switch ( dstmode ) { case QImode : if ( ! TARGET_SSE4_1 ) return false ; srcmode = V16QImode ; break ; case HImode : if ( ! TARGET_SSE2 ) return false ; srcmode = V8HImode ; break ; case SImode : if ( ! TARGET_SSE4_1 ) return false ; srcmode = V4SImode ; break ; case DImode : gcc_assert ( TARGET_64BIT ) ; if ( ! TARGET_SSE4_1 ) return false ; srcmode = V2DImode ; break ; default : return false ; } if ( pos & ( size - 1 ) ) return false ; if ( GET_MODE ( dst ) == dstmode ) d = dst ; else d = gen_reg_rtx ( dstmode ) ; pat = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 1 , GEN_INT ( pos / size ) ) ) ; pat = gen_rtx_VEC_SELECT ( dstmode , gen_lowpart ( srcmode , src ) , pat ) ; if ( dstmode == QImode || dstmode == HImode ) { pat = gen_rtx_ZERO_EXTEND ( SImode , pat ) ; d = gen_lowpart ( SImode , d ) ; } emit_insn ( gen_rtx_SET ( d , pat ) ) ; if ( d != dst ) emit_move_insn ( dst , gen_lowpart ( GET_MODE ( dst ) , d ) ) ; return true ; } default : return false ; } } </s>

Expand an extract from a vector register through pextr insn . Return true if successful .


<s>
void
print
(
DiagnosticPrinter
&
DP
)
const
override
{
DP
<<
"unsupported "
<<
getDescription
(
)
<<
" in "
<<
Fn
.
getName
(
)
;
}
</s>

print - Print a debug representation of the operand to the given stream .


"Flag output operand is of invalid type"


<s> bool HexagonPassConfig :: addInstSelector ( ) { addPass ( createHexagonRemoveExtendOps ( getHexagonTargetMachine ( ) ) ) ; addPass ( createHexagonISelDag ( getHexagonTargetMachine ( ) , getOptLevel ( ) ) ) ; addPass ( createHexagonPeephole ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .

Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon


<s>
void
RISCVMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
unsigned
Size
=
Desc
.
getSize
(
)
;
if
(
MI
.
getOpcode
(
)
==
RISCV
::
PseudoCALLReg
||
MI
.
getOpcode
(
)
==
RISCV
::
PseudoCALL
||
MI
.
getOpcode
(
)
==
RISCV
::
PseudoTAIL
)
{
expandFunctionCall
(
MI
,
OS
,
Fixups
,
STI
)
;
MCNumEmitted
+=
2
;
return
;
}
if
(
MI
.
getOpcode
(
)
==
RISCV
::
PseudoAddTPRel
)
{
expandAddTPRel
(
MI
,
OS
,
Fixups
,
STI
)
;
MCNumEmitted
+=
1
;
return
;
}
switch
(
Size
)
{
default
:
llvm_unreachable
(
"Unhandled encodeInstruction length!"
)
;
case
2
:
{
uint16_t
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
support
::
endian
::
write
<
uint16_t
>
(
OS
,
Bits
,
support
::
little
)
;
break
;
}
case
4
:
{
uint32_t
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
support
::
endian
::
write
(
OS
,
Bits
,
support
::
little
)
;
break
;
}
}
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .

RISCV
RISCV
RISCV::PseudoCALLReg
RISCV::PseudoCALL
RISCV::PseudoTAIL
2
RISCV::PseudoAddTPRel
1
"Unhandled encodeInstruction length!"
2
support::endian
support::little
4
support::endian
support::little


<s>
StringRef
getPassName
(
)
const
override
{
return
"Windows 32-bit x86 EH state insertion"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"Empty ranges shouldn't remain in the worklist"


<s> static bool arm_asm_elf_flags_numeric ( unsigned int flags , unsigned int * num ) { if ( flags & SECTION_ARM_PURECODE ) { * num = 0x20000000 ; if ( ! ( flags & SECTION_DEBUG ) ) * num |= 0x2 ; if ( flags & SECTION_EXCLUDE ) * num |= 0x80000000 ; if ( flags & SECTION_WRITE ) * num |= 0x1 ; if ( flags & SECTION_CODE ) * num |= 0x4 ; if ( flags & SECTION_MERGE ) * num |= 0x10 ; if ( flags & SECTION_STRINGS ) * num |= 0x20 ; if ( flags & SECTION_TLS ) * num |= 0x400 ; if ( HAVE_COMDAT_GROUP && ( flags & SECTION_LINKONCE ) ) * num |= 0x200 ; return true ; } return false ; } </s>

Implement the TARGET_ASM_ELF_FLAGS_NUMERIC hook . For pure-code sections there is no letter code for this attribute , so output all the section flags numerically when this is needed .


<s> void AArch64PassConfig :: addPreEmitPass ( ) { if ( EnableA53Fix835769 ) addPass ( createAArch64A53Fix835769 ( ) ) ; if ( BranchRelaxation ) addPass ( createAArch64BranchRelaxation ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void F2003fInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { BuildMI ( MBB , I , DL , get ( F2003f :: KRZrr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } </s>


<s> bool writeNopData ( raw_ostream & OS , uint64_t Count ) const override { if ( Count == 0 ) { return true ; } return false ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


Emit target-specific code that performs a memcpy .


<s> void ARMTTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP ) { if ( ! ST -> isMClass ( ) ) return BasicTTIImplBase :: getUnrollingPreferences ( L , SE , UP ) ; if ( ! ST -> isThumb2 ( ) || L -> getNumBlocks ( ) != 1 ) return ; UP . OptSizeThreshold = 0 ; UP . PartialOptSizeThreshold = 0 ; BasicBlock * BB = L -> getLoopLatch ( ) ; if ( BB -> getParent ( ) -> optForSize ( ) ) return ; unsigned Cost = 0 ; for ( auto & I : * BB ) { if ( isa < CallInst > ( I ) || isa < InvokeInst > ( I ) ) { ImmutableCallSite CS ( & I ) ; if ( const Function * F = CS . getCalledFunction ( ) ) { if ( ! isLoweredToCall ( F ) ) continue ; } return ; } SmallVector < const Value * , 4 > Operands ( I . value_op_begin ( ) , I . value_op_end ( ) ) ; Cost += getUserCost ( & I , Operands ) ; } UP . Partial = true ; UP . Runtime = true ; UP . UnrollRemainder = true ; UP . DefaultUnrollRuntimeCount = 4 ; if ( Cost < 12 ) UP . Force = true ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> Register RISCVRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const RISCVFrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? TFI -> getFPReg ( ) : TFI -> getSPReg ( ) ; } </s>


<s> static bool arm_evpc_neon_vtbl ( struct expand_vec_perm_d * d ) { rtx rperm [ MAX_VECT_LEN ] , sel ; machine_mode vmode = d -> vmode ; unsigned int i , nelt = d -> perm . length ( ) ; if ( BYTES_BIG_ENDIAN ) return false ; if ( d -> testing_p ) return true ; if ( vmode != V8QImode && vmode != V16QImode ) return false ; for ( i = 0 ; i < nelt ; ++ i ) rperm [ i ] = GEN_INT ( d -> perm [ i ] ) ; sel = gen_rtx_CONST_VECTOR ( vmode , gen_rtvec_v ( nelt , rperm ) ) ; sel = force_reg ( vmode , sel ) ; arm_expand_vec_perm_1 ( d -> target , d -> op0 , d -> op1 , sel ) ; return true ; } </s>

The NEON VTBL instruction is a fully variable permuation that 's even stronger than what we expose via VEC_PERM_EXPR . What it does n't do is mask the index operand as VEC_PERM_EXPR requires . Therefore we can do slightly better by expanding this as a constant where we do n't have to apply a mask .


<s>
ScheduleHazardRecognizer
*
PPCInstrInfo
::
CreateTargetPostRAHazardRecognizer
(
const
InstrItineraryData
*
II
,
const
ScheduleDAG
*
DAG
)
const
{
unsigned
Directive
=
DAG
->
MF
.
getSubtarget
<
PPCSubtarget
>
(
)
.
getDarwinDirective
(
)
;
if
(
Directive
==
PPC
::
DIR_PWR7
||
Directive
==
PPC
::
DIR_PWR8
)
return
new
PPCDispatchGroupSBHazardRecognizer
(
II
,
DAG
)
;
if
(
Directive
!=
PPC
::
DIR_440
&&
Directive
!=
PPC
::
DIR_A2
&&
Directive
!=
PPC
::
DIR_E500mc
&&
Directive
!=
PPC
::
DIR_E5500
)
{
assert
(
DAG
->
TII
&&
"No InstrInfo?"
)
;
return
new
PPCHazardRecognizer970
(
*
DAG
)
;
}
return
new
ScoreboardHazardRecognizer
(
II
,
DAG
)
;
}
</s>

Allocate and return a hazard recognizer to use for by non-scheduling passes .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Local Dynamic TLS Access Clean-up"
;
}
</s>


<s> void SPIRVPassConfig :: addISelPrepare ( ) { addPass ( createSPIRVEmitIntrinsicsPass ( & getTM < SPIRVTargetMachine > ( ) ) ) ; TargetPassConfig :: addISelPrepare ( ) ; } </s>

Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection .


<s> bool X86TargetLowering :: canMergeStoresTo ( unsigned AddressSpace , EVT MemVT , const SelectionDAG & DAG ) const { bool NoFloat = DAG . getMachineFunction ( ) . getFunction ( ) -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ; if ( NoFloat ) { unsigned MaxIntSize = Subtarget . is64Bit ( ) ? 64 : 32 ; return ( MemVT . getSizeInBits ( ) <= MaxIntSize ) ; } return true ; } </s>

Returns if it 's reasonable to merge stores to MemVT size .


<s> static bool aarch64_hard_regno_mode_ok ( unsigned regno , machine_mode mode ) { if ( GET_MODE_CLASS ( mode ) == MODE_CC ) return regno == CC_REGNUM ; if ( regno == VG_REGNUM ) return mode == DImode ; unsigned int vec_flags = aarch64_classify_vector_mode ( mode ) ; if ( vec_flags & VEC_SVE_PRED ) return pr_or_ffr_regnum_p ( regno ) ; if ( pr_or_ffr_regnum_p ( regno ) ) return false ; if ( regno == SP_REGNUM ) return mode == Pmode || mode == ptr_mode ; if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return mode == Pmode ; if ( GP_REGNUM_P ( regno ) ) { if ( vec_flags & VEC_ANY_SVE ) return false ; if ( known_le ( GET_MODE_SIZE ( mode ) , 8 ) ) return true ; if ( known_le ( GET_MODE_SIZE ( mode ) , 16 ) ) return ( regno & 1 ) == 0 ; } else if ( FP_REGNUM_P ( regno ) ) { if ( vec_flags & VEC_STRUCT ) return end_hard_regno ( mode , regno ) - 1 <= V31_REGNUM ; else return ! VECTOR_MODE_P ( mode ) || vec_flags != 0 ; } return false ; } </s>


<s> static int cris_initial_frame_pointer_offset ( void ) { int regno ; int offs = 0 ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( cris_reg_saved_in_regsave_area ( regno ) ) offs += 4 ; offs += get_frame_size ( ) ; offs += crtl -> outgoing_args_size ; if ( TARGET_STACK_ALIGN ) offs = TARGET_ALIGN_BY_32 ? ( offs + 3 ) & ~ 3 : ( offs + 1 ) & ~ 1 ; return offs ; } </s>

This used to be the INITIAL_FRAME_POINTER_OFFSET worker ; now only handles FP - > SP elimination offset .


<s> virtual const InstrItineraryData * getInstrItineraryData ( ) const { return InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> void PPCFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const PPCRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; PPCFunctionInfo * FI = MF . getInfo < PPCFunctionInfo > ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; SavedRegs . reset ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; const bool isPPC64 = Subtarget . isPPC64 ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( ) ; FPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int BPSI = FI -> getBasePointerSaveIndex ( ) ; if ( ! BPSI && RegInfo -> hasBasePointer ( MF ) ) { int BPOffset = getBasePointerSaveOffset ( ) ; BPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , BPOffset , true ) ; FI -> setBasePointerSaveIndex ( BPSI ) ; } if ( FI -> usesPICBase ( ) ) { int PBPSI = MFI . CreateFixedObject ( 4 , - 8 , true ) ; FI -> setPICBasePointerSaveIndex ( PBPSI ) ; } if ( needsFP ( MF ) ) SavedRegs . reset ( isPPC64 ? PPC :: X31 : PPC :: R31 ) ; if ( RegInfo -> hasBasePointer ( MF ) ) SavedRegs . reset ( RegInfo -> getBaseRegister ( MF ) ) ; if ( FI -> usesPICBase ( ) ) SavedRegs . reset ( PPC :: R30 ) ; int TCSPDelta = 0 ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < 0 ) { MFI . CreateFixedObject ( - 1 * TCSPDelta , TCSPDelta , true ) ; } if ( ( SavedRegs . test ( PPC :: CR2 ) || SavedRegs . test ( PPC :: CR3 ) || SavedRegs . test ( PPC :: CR4 ) ) ) { const uint64_t SpillSize = 4 ; const int64_t SpillOffset = Subtarget . isPPC64 ( ) ? 8 : Subtarget . isAIXABI ( ) ? 4 : - 4 ; int FrameIdx = MFI . CreateFixedObject ( SpillSize , SpillOffset , true , false ) ; FI -> setCRSpillFrameIndex ( FrameIdx ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


"Can only insert epilog into returning blocks"


<s> bool WebAssemblyFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; bool HasFixedSizedObjects = MFI . getStackSize ( ) > 0 ; bool NeedsFixedReference = ! hasBP ( MF ) || HasFixedSizedObjects ; return MFI . isFrameAddressTaken ( ) || ( MFI . hasVarSizedObjects ( ) && NeedsFixedReference ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void mips_split_64bit_move ( rtx dest , rtx src ) { if ( FP_REG_RTX_P ( dest ) ) { emit_insn ( gen_load_df_low ( copy_rtx ( dest ) , mips_subword ( src , 0 ) ) ) ; emit_insn ( gen_load_df_high ( dest , mips_subword ( src , 1 ) , copy_rtx ( dest ) ) ) ; } else if ( FP_REG_RTX_P ( src ) ) { emit_move_insn ( mips_subword ( dest , 0 ) , mips_subword ( src , 0 ) ) ; emit_insn ( gen_store_df_high ( mips_subword ( dest , 1 ) , src ) ) ; } else { rtx low_dest ; low_dest = mips_subword ( dest , 0 ) ; if ( REG_P ( low_dest ) && reg_overlap_mentioned_p ( low_dest , src ) ) { emit_move_insn ( mips_subword ( dest , 1 ) , mips_subword ( src , 1 ) ) ; emit_move_insn ( low_dest , mips_subword ( src , 0 ) ) ; } else { emit_move_insn ( low_dest , mips_subword ( src , 0 ) ) ; emit_move_insn ( mips_subword ( dest , 1 ) , mips_subword ( src , 1 ) ) ; } } } </s>

Split a 64-bit move from SRC to DEST assuming that mips_split_64bit_move_p holds . Moves into and out of FPRs cause some difficulty here . Such moves will always be DFmode , since paired FPRs are not allowed to store DImode values . The most natural representation would be two separate 32-bit moves , such as : ( set ( reg : SI $ f0 ) ( mem : SI ... ) ) ( set ( reg : SI $ f1 ) ( mem : SI ... ) ) However , the second insn is invalid because odd-numbered FPRs are not allowed to store independent values . Use the patterns load_df_low , load_df_high and store_df_high instead .


<s>
void
X86InstrInfo
::
reMaterialize
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
unsigned
SubIdx
,
const
MachineInstr
&
Orig
,
const
TargetRegisterInfo
&
TRI
)
const
{
bool
ClobbersEFLAGS
=
false
;
for
(
const
MachineOperand
&
MO
:
Orig
.
operands
(
)
)
{
if
(
MO
.
isReg
(
)
&&
MO
.
isDef
(
)
&&
MO
.
getReg
(
)
==
X86
::
EFLAGS
)
{
ClobbersEFLAGS
=
true
;
break
;
}
}
if
(
ClobbersEFLAGS
&&
!
isSafeToClobberEFLAGS
(
MBB
,
I
)
)
{
int
Value
;
switch
(
Orig
.
getOpcode
(
)
)
{
case
X86
::
MOV32r0
:
Value
=
0
;
break
;
case
X86
::
MOV32r1
:
Value
=
1
;
break
;
case
X86
::
MOV32r_1
:
Value
=
1
;
break
;
default
:
llvm_unreachable
(
"Unexpected instruction!"
)
;
}
const
DebugLoc
&
DL
=
Orig
.
getDebugLoc
(
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
X86
::
MOV32ri
)
)
.
addOperand
(
Orig
.
getOperand
(
0
)
)
.
addImm
(
Value
)
;
}
else
{
MachineInstr
*
MI
=
MBB
.
getParent
(
)
->
CloneMachineInstr
(
&
Orig
)
;
MBB
.
insert
(
I
,
MI
)
;
}
MachineInstr
&
NewMI
=
*
std
::
prev
(
I
)
;
NewMI
.
substituteRegister
(
Orig
.
getOperand
(
0
)
.
getReg
(
)
,
DestReg
,
SubIdx
,
TRI
)
;
}
</s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s> static int hi_const ( rtx src ) { return ( GET_CODE ( src ) == CONST_INT && INTVAL ( src ) >= - 32768 && INTVAL ( src ) <= 32767 ) ; } </s>

Return nonzero if constant would be an ok source for a mov.w instead of a mov.l .


<s> const LoongArchInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> static bool aarch64_optab_supported_p ( int op , machine_mode mode1 , machine_mode , optimization_type opt_type ) { switch ( op ) { case rsqrt_optab : return opt_type == OPTIMIZE_FOR_SPEED && use_rsqrt_p ( mode1 ) ; default : return true ; } } </s>

Implement the TARGET_OPTAB_SUPPORTED_P hook .


<s>
void
SPUInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
)
const
{
unsigned
opc
;
bool
isValidFrameIdx
=
(
FrameIdx
<
SPUFrameInfo
::
maxFrameOffset
(
)
)
;
if
(
RC
==
SPU
::
GPRCRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr128
:
SPU
::
STQXr128
)
;
}
else
if
(
RC
==
SPU
::
R64CRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr64
:
SPU
::
STQXr64
)
;
}
else
if
(
RC
==
SPU
::
R64FPRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr64
:
SPU
::
STQXr64
)
;
}
else
if
(
RC
==
SPU
::
R32CRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr32
:
SPU
::
STQXr32
)
;
}
else
if
(
RC
==
SPU
::
R32FPRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr32
:
SPU
::
STQXr32
)
;
}
else
if
(
RC
==
SPU
::
R16CRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr16
:
SPU
::
STQXr16
)
;
}
else
if
(
RC
==
SPU
::
R8CRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr8
:
SPU
::
STQXr8
)
;
}
else
if
(
RC
==
SPU
::
VECREGRegisterClass
)
{
opc
=
(
isValidFrameIdx
)
SPU
::
STQDv16i8
:
SPU
::
STQXv16i8
;
}
else
{
assert
(
0
&&
"Unknown regclass!"
)
;
abort
(
)
;
}
DebugLoc
DL
=
DebugLoc
::
getUnknownLoc
(
)
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
opc
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
,
FrameIdx
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> unsigned getFlatAddressSpace ( ) const { if ( IsGraphicsShader ) return - 1 ; return AMDGPUAS :: FLAT_ADDRESS ; } </s>

Returns the address space ID for a target 's 'flat ' address space .


<s> int xstormy16_interrupt_function_p ( ) { tree attributes ; if ( ! cfun ) return 0 ; attributes = TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ; return lookup_attribute ( "interrupt" , attributes ) != NULL_TREE ; } </s>

Return nonzero if the function is an interrupt function .


<s> BitVector SIRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AMDGPU :: EXEC ) ; Reserved . set ( AMDGPU :: INDIRECT_BASE_ADDR ) ; const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( TM . getInstrInfo ( ) ) ; TII -> reserveIndirectRegisters ( Reserved , MF ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static inline ChildIteratorType child_begin ( NodeType * N ) { return N -> Sites . begin ( ) ; } </s>

nodes_iterator/begin/end - Allow iteration over all nodes in the graph


"64-bit WebAssembly (wasm64) is not currently supported"

runOnMachineFunction - Emit the function body .


<s>
static
std
::
unique_ptr
<
X86Operand
>
CreateMem
(
unsigned
SegReg
,
const
MCExpr
*
Disp
,
unsigned
BaseReg
,
unsigned
IndexReg
,
unsigned
Scale
,
SMLoc
StartLoc
,
SMLoc
EndLoc
,
unsigned
Size
=
0
,
StringRef
SymName
=
StringRef
(
)
,
void
*
OpDecl
=
nullptr
)
{
assert
(
(
SegReg
||
BaseReg
||
IndexReg
)
&&
"Invalid memory operand!"
)
;
assert
(
(
(
Scale
==
1
||
Scale
==
2
||
Scale
==
4
||
Scale
==
8
)
)
&&
"Invalid scale!"
)
;
auto
Res
=
llvm
::
make_unique
<
X86Operand
>
(
Memory
,
StartLoc
,
EndLoc
)
;
Res
->
Mem
.
SegReg
=
SegReg
;
Res
->
Mem
.
Disp
=
Disp
;
Res
->
Mem
.
BaseReg
=
BaseReg
;
Res
->
Mem
.
IndexReg
=
IndexReg
;
Res
->
Mem
.
Scale
=
Scale
;
Res
->
Mem
.
Size
=
Size
;
Res
->
SymName
=
SymName
;
Res
->
OpDecl
=
OpDecl
;
Res
->
AddressOf
=
false
;
return
Res
;
}
</s>


<s> unsigned AArch64RegisterBankInfo :: copyCost ( const RegisterBank & A , const RegisterBank & B , unsigned Size ) const { if ( & A == & AArch64 :: GPRRegBank && & B == & AArch64 :: FPRRegBank ) return 5 ; if ( & A == & AArch64 :: FPRRegBank && & B == & AArch64 :: GPRRegBank ) return 4 ; return RegisterBankInfo :: copyCost ( A , B , Size ) ; } </s>

Get the cost of a copy from B to A , or put differently , get the cost of A = COPY B .


"position-independent code requires the Linux ABI"

"-mgprel-sec= argument is not a valid regular expression."

"-mr0rel-sec= argument is not a valid regular expression."

"BMX instructions are only supported with R2 architecture"

"CDX instructions are only supported with R2 architecture"


<s>
const
char
*
getPassName
(
)
const
override
{
return
"X86 Fixup SetCC"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> const char * RISCVTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( RISCVISD :: NodeType ) Opcode ) { case RISCVISD :: FIRST_NUMBER : break ; case RISCVISD :: RET_FLAG : return "RISCVISD::RET_FLAG" ; case RISCVISD :: CALL : return "RISCVISD::CALL" ; case RISCVISD :: SELECT_CC : return "RISCVISD::SELECT_CC" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static bool interesting_frame_related_regno ( unsigned int regno ) { if ( regno == 0 ) return true ; if ( regno == CR2_REGNO ) return true ; return save_reg_p ( regno ) ; } </s>

This function is called when rs6000_frame_related is processing SETs within a PARALLEL , and returns whether the REGNO save ought to be marked RTX_FRAME_RELATED_P . The PARALLELs involved are those for out-of-line register save functions , store multiple , and the Darwin world_save . They may contain registers that do n't really need saving .


"unknown core architecture %qs specified with %qs"

Set ` avr_arch ' as specified by ` -mmcu= ' . Return true on success .


<s> bool nds32_gw_ex_to_ex_p ( rtx_insn * producer , rtx_insn * consumer ) { return nds32_n10_ex_to_ex_p ( producer , consumer ) ; } </s>

Check dependencies from EX to EX ( ADDR_OUT - > ADDR_IN ) .


<s> bool SIInstrInfo :: isReallyTriviallyReMaterializable ( const MachineInstr * MI , AliasAnalysis * AA ) const { switch ( MI -> getOpcode ( ) ) { case AMDGPU :: V_MOV_B32_e32 : case AMDGPU :: V_MOV_B32_e64 : return true ; default : return false ; } } </s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> bool ARMExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getTarget ( ) . getInstrInfo ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= ExpandMBB ( * MFI ) ; return Modified ; } </s>


<s> void aarch64_emit_call_insn ( rtx pat ) { rtx insn = emit_call_insn ( pat ) ; rtx * fusage = & CALL_INSN_FUNCTION_USAGE ( insn ) ; clobber_reg ( fusage , gen_rtx_REG ( word_mode , IP0_REGNUM ) ) ; clobber_reg ( fusage , gen_rtx_REG ( word_mode , IP1_REGNUM ) ) ; } </s>

Emit call insn with PAT and do aarch64-specific handling .


<s> std :: pair < unsigned , unsigned > AMDGPUSubtarget :: getWavesPerEU ( const Function & F ) const { std :: pair < unsigned , unsigned > Default ( 1 , 0 ) ; std :: pair < unsigned , unsigned > FlatWorkGroupSizes = getFlatWorkGroupSizes ( F ) ; unsigned MinImpliedByFlatWorkGroupSize = getMaxWavesPerEU ( FlatWorkGroupSizes . second ) ; bool RequestedFlatWorkGroupSize = false ; if ( F . hasFnAttribute ( "amdgpu-max-work-group-size" ) || F . hasFnAttribute ( "amdgpu-flat-work-group-size" ) ) { Default . first = MinImpliedByFlatWorkGroupSize ; RequestedFlatWorkGroupSize = true ; } std :: pair < unsigned , unsigned > Requested = AMDGPU :: getIntegerPairAttribute ( F , "amdgpu-waves-per-eu" , Default , true ) ; if ( Requested . second && Requested . first > Requested . second ) return Default ; if ( Requested . first < getMinWavesPerEU ( ) || Requested . first > getMaxWavesPerEU ( ) ) return Default ; if ( Requested . second > getMaxWavesPerEU ( ) ) return Default ; if ( RequestedFlatWorkGroupSize && Requested . first > MinImpliedByFlatWorkGroupSize ) return Default ; return Requested ; } </s>

Overload which uses the specified values for the flat work group sizes , rather than querying the function itself .

AMDGPU AMDGPU 1 0 "amdgpu-max-work-group-size" "amdgpu-flat-work-group-size" AMDGPU::getIntegerPairAttribute "amdgpu-waves-per-eu"


<s> bool doFinalization ( Module & M ) override { return false ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> static void ix86_emit_vec_binop ( enum rtx_code code , machine_mode mode , rtx dst , rtx src1 , rtx src2 ) { rtx tmp ; tmp = gen_rtx_SET ( dst , gen_rtx_fmt_ee ( code , mode , src1 , src2 ) ) ; if ( GET_MODE_SIZE ( mode ) <= GET_MODE_SIZE ( SImode ) && GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) { rtx clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , tmp , clob ) ) ; } emit_insn ( tmp ) ; } </s>

Emit x86 binary operand CODE in mode MODE for SSE vector instructions that can be performed using GP registers .


<s> static SDValue matchBinOpReduction ( SDNode * Extract , unsigned & BinOp , ArrayRef < ISD :: NodeType > CandidateBinOps ) { if ( ( Extract -> getOpcode ( ) != ISD :: EXTRACT_VECTOR_ELT ) || ! isNullConstant ( Extract -> getOperand ( 1 ) ) ) return SDValue ( ) ; SDValue Op = Extract -> getOperand ( 0 ) ; unsigned Stages = Log2_32 ( Op . getValueType ( ) . getVectorNumElements ( ) ) ; if ( llvm :: none_of ( CandidateBinOps , [ Op ] ( ISD :: NodeType BinOp ) { return Op . getOpcode ( ) == unsigned ( BinOp ) ; } ) ) return SDValue ( ) ; unsigned CandidateBinOp = Op . getOpcode ( ) ; for ( unsigned i = 0 ; i < Stages ; ++ i ) { if ( Op . getOpcode ( ) != CandidateBinOp ) return SDValue ( ) ; ShuffleVectorSDNode * Shuffle = dyn_cast < ShuffleVectorSDNode > ( Op . getOperand ( 0 ) . getNode ( ) ) ; if ( Shuffle ) { Op = Op . getOperand ( 1 ) ; } else { Shuffle = dyn_cast < ShuffleVectorSDNode > ( Op . getOperand ( 1 ) . getNode ( ) ) ; Op = Op . getOperand ( 0 ) ; } if ( ! Shuffle || Shuffle -> getOperand ( 0 ) != Op ) return SDValue ( ) ; for ( int Index = 0 , MaskEnd = 1 << i ; Index < MaskEnd ; ++ Index ) if ( Shuffle -> getMaskElt ( Index ) != MaskEnd + Index ) return SDValue ( ) ; } BinOp = CandidateBinOp ; return Op ; } </s>

Match a binop + shuffle pyramid that represents a horizontal reduction over the elements of a vector starting from the EXTRACT_VECTOR_ELT node /p Extract .


Relax the instruction in the given fragment to the next wider instruction .


<s> void X86IntelInstPrinter :: printInst ( const MCInst * MI ) { printInstruction ( MI ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool RISCVFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return true ; MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) DL = MI -> getDebugLoc ( ) ; const char * SpillLibCall = getSpillLibCallName ( * MF , CSI ) ; if ( SpillLibCall ) { BuildMI ( MBB , MI , DL , TII . get ( RISCV :: PseudoCALLReg ) , RISCV :: X5 ) . addExternalSymbol ( SpillLibCall , RISCVII :: MO_CALL ) . setMIFlag ( MachineInstr :: FrameSetup ) ; for ( auto & CS : CSI ) MBB . addLiveIn ( CS . getReg ( ) ) ; } const auto & NonLibcallCSI = getNonLibcallCSI ( * MF , CSI ) ; for ( auto & CS : NonLibcallCSI ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , ! MBB . isLiveIn ( Reg ) , CS . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> void DLXPassConfig :: addPreSched2 ( ) { addPass ( createDLXMemAluCombinerPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> bool TPCPassConfig :: addPreISel ( ) { bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) { addPass ( createTPCFMAoptPass ( ) ) ; addPass ( createTPCUnbranchPass ( ) ) ; } addPass ( createTPCSelectorPreshaper ( ) ) ; addPass ( createTPCSingleUseScalarOptimizer ( ) ) ; addPass ( createAggressiveDCEPass ( ) ) ; return false ; } </s>


<s> int fix_bit_operand ( rtx * operands , enum rtx_code code ) { if ( code == AND ? single_zero_operand ( operands [ 2 ] , QImode ) : single_one_operand ( operands [ 2 ] , QImode ) ) { if ( GET_CODE ( operands [ 0 ] ) == MEM && ! OK_FOR_U ( operands [ 0 ] ) ) { rtx mem = gen_rtx_MEM ( GET_MODE ( operands [ 0 ] ) , copy_to_mode_reg ( Pmode , XEXP ( operands [ 0 ] , 0 ) ) ) ; MEM_COPY_ATTRIBUTES ( mem , operands [ 0 ] ) ; operands [ 0 ] = mem ; } if ( GET_CODE ( operands [ 1 ] ) == MEM && ! OK_FOR_U ( operands [ 1 ] ) ) { rtx mem = gen_rtx_MEM ( GET_MODE ( operands [ 1 ] ) , copy_to_mode_reg ( Pmode , XEXP ( operands [ 1 ] , 0 ) ) ) ; MEM_COPY_ATTRIBUTES ( mem , operands [ 0 ] ) ; operands [ 1 ] = mem ; } return 0 ; } operands [ 1 ] = force_reg ( QImode , operands [ 1 ] ) ; { rtx res = gen_reg_rtx ( QImode ) ; switch ( code ) { case AND : emit_insn ( gen_andqi3_1 ( res , operands [ 1 ] , operands [ 2 ] ) ) ; break ; case IOR : emit_insn ( gen_iorqi3_1 ( res , operands [ 1 ] , operands [ 2 ] ) ) ; break ; case XOR : emit_insn ( gen_xorqi3_1 ( res , operands [ 1 ] , operands [ 2 ] ) ) ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen_movqi ( operands [ 0 ] , res ) ) ; } return 1 ; } </s>

Fix the operands of a gen_xxx so that it could become a bit operating insn .


<s> bool X86TTIImpl :: isLegalNTLoad ( Type * DataType , unsigned Alignment ) { unsigned DataSize = DL . getTypeStoreSize ( DataType ) ; if ( Alignment >= DataSize && ( DataSize == 16 || DataSize == 32 ) ) return DataSize == 16 ? ST -> hasSSE1 ( ) : ST -> hasAVX2 ( ) ; return false ; } </s>

Return true if the target supports nontemporal load .


"relaxInstruction is not implemented yet"


<s> bool runOnModule ( Module & M ) override { CallGraph CG = CallGraph ( M ) ; UsedList = getUsedList ( M ) ; bool Changed = superAlignLDSGlobals ( M ) ; Changed |= processUsedLDS ( CG , M ) ; for ( Function & F : M . functions ( ) ) { if ( F . isDeclaration ( ) ) continue ; if ( ! AMDGPU :: isKernel ( F . getCallingConv ( ) ) ) continue ; Changed |= processUsedLDS ( CG , M , & F ) ; } UsedList . clear ( ) ; return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> const LegalizerInfo * ARMSubtarget :: getLegalizerInfo ( ) const { return Legalizer . get ( ) ; } </s>

Expose LegalizerInfo so the clients can re-use .


<s> static bool must_save_fp_p ( void ) { return df_regs_ever_live_p ( REG_FP ) ; } </s>

Determine if we are going to save the frame pointer in the prologue .


<s> int needs_regstack_p ( ) { int i ; rtx insn ; if ( frame_pointer_needed ) return 1 ; for ( i = R_LR ( 127 ) ; i >= R_LR ( 0 ) ; i -- ) if ( regs_ever_live [ i ] ) return 1 ; for ( insn = get_insns ( ) ; insn ; insn = next_insn ( insn ) ) if ( GET_CODE ( insn ) == CALL_INSN || ( GET_CODE ( insn ) == INSN && GET_CODE ( PATTERN ( insn ) ) == SEQUENCE && GET_CODE ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) ) == CALL_INSN ) ) return 1 ; return 0 ; } </s>

Return 1 if the current function will adjust the register stack .


<s> const MCExpr * ARMTargetStreamer :: addConstantPoolEntry ( const MCExpr * Expr , SMLoc Loc ) { return ConstantPools -> addEntry ( Streamer , Expr , 4 , Loc ) ; } </s>

Add a new entry to the constant pool for the current section and return an MCExpr that can be used to refer to the constant pool location .


<s> static void unicosmk_gen_dsib ( unsigned long * imaskP ATTRIBUTE_UNUSED ) { } </s>

Set up the dynamic subprogram information block ( DSIB ) and update the frame pointer register ( $ 15 ) for subroutines which have a frame . If the subroutine does n't have a frame , simply increment $ 15 .


<s> static bool rs6000_expand_vec_perm_const_1 ( rtx target , rtx op0 , rtx op1 , unsigned char perm0 , unsigned char perm1 ) { rtx x ; if ( ( perm0 & 2 ) == ( perm1 & 2 ) ) { if ( perm0 & 2 ) op0 = op1 ; else op1 = op0 ; } if ( rtx_equal_p ( op0 , op1 ) ) { perm0 = perm0 & 1 ; perm1 = ( perm1 & 1 ) + 2 ; } else if ( perm0 & 2 ) { if ( perm1 & 2 ) return false ; perm0 -= 2 ; perm1 += 2 ; std :: swap ( op0 , op1 ) ; } else if ( ( perm1 & 2 ) == 0 ) return false ; if ( target != NULL ) { machine_mode vmode , dmode ; rtvec v ; vmode = GET_MODE ( target ) ; gcc_assert ( GET_MODE_NUNITS ( vmode ) == 2 ) ; dmode = mode_for_vector ( GET_MODE_INNER ( vmode ) , 4 ) . require ( ) ; x = gen_rtx_VEC_CONCAT ( dmode , op0 , op1 ) ; v = gen_rtvec ( 2 , GEN_INT ( perm0 ) , GEN_INT ( perm1 ) ) ; x = gen_rtx_VEC_SELECT ( vmode , x , gen_rtx_PARALLEL ( VOIDmode , v ) ) ; emit_insn ( gen_rtx_SET ( target , x ) ) ; } return true ; } </s>

Expand a Paired Single or VSX Permute Doubleword constant permutation . Return true if we match an efficient implementation .


<s> BitVector HexagonRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( HEXAGON_RESERVED_REG_1 ) ; Reserved . set ( HEXAGON_RESERVED_REG_2 ) ; Reserved . set ( Hexagon :: R29 ) ; Reserved . set ( Hexagon :: R30 ) ; Reserved . set ( Hexagon :: R31 ) ; Reserved . set ( Hexagon :: PC ) ; Reserved . set ( Hexagon :: D14 ) ; Reserved . set ( Hexagon :: D15 ) ; Reserved . set ( Hexagon :: LC0 ) ; Reserved . set ( Hexagon :: LC1 ) ; Reserved . set ( Hexagon :: SA0 ) ; Reserved . set ( Hexagon :: SA1 ) ; Reserved . set ( Hexagon :: UGP ) ; Reserved . set ( Hexagon :: GP ) ; Reserved . set ( Hexagon :: CS0 ) ; Reserved . set ( Hexagon :: CS1 ) ; Reserved . set ( Hexagon :: CS ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
bool
ARMBasicBlockUtils
::
isBBInRange
(
MachineInstr
*
MI
,
MachineBasicBlock
*
DestBB
,
unsigned
MaxDisp
)
const
{
unsigned
PCAdj
=
isThumb
4
:
8
;
unsigned
BrOffset
=
getOffsetOf
(
MI
)
+
PCAdj
;
unsigned
DestOffset
=
BBInfo
[
DestBB
->
getNumber
(
)
]
.
Offset
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Branch of destination "
<<
printMBBReference
(
*
DestBB
)
<<
" from "
<<
printMBBReference
(
*
MI
->
getParent
(
)
)
<<
" max delta="
<<
MaxDisp
<<
" from "
<<
getOffsetOf
(
MI
)
<<
" to "
<<
DestOffset
<<
" offset "
<<
int
(
DestOffset
BrOffset
)
<<
"\t"
<<
*
MI
)
;
if
(
BrOffset
<=
DestOffset
)
{
if
(
DestOffset
BrOffset
<=
MaxDisp
)
return
true
;
}
else
{
if
(
BrOffset
DestOffset
<=
MaxDisp
)
return
true
;
}
return
false
;
}
</s>

isBBInRange - Returns true if the distance between specific MI and specific BB can fit in MI 's displacement field .

ARM
ARM
4
8
"Branch of destination "
" from "
" max delta="
" from "
" to "
" offset "
"\t"


<s> bool aarch64_expand_vec_perm_const ( rtx target , rtx op0 , rtx op1 , rtx sel ) { struct expand_vec_perm_d d ; int i , nelt , which ; d . target = target ; d . op0 = op0 ; d . op1 = op1 ; d . vmode = GET_MODE ( target ) ; gcc_assert ( VECTOR_MODE_P ( d . vmode ) ) ; d . nelt = nelt = GET_MODE_NUNITS ( d . vmode ) ; d . testing_p = false ; for ( i = which = 0 ; i < nelt ; ++ i ) { rtx e = XVECEXP ( sel , 0 , i ) ; int ei = INTVAL ( e ) & ( 2 * nelt - 1 ) ; which |= ( ei < nelt ? 1 : 2 ) ; d . perm [ i ] = ei ; } switch ( which ) { default : gcc_unreachable ( ) ; case 3 : d . one_vector_p = false ; if ( ! rtx_equal_p ( op0 , op1 ) ) break ; case 2 : for ( i = 0 ; i < nelt ; ++ i ) d . perm [ i ] &= nelt - 1 ; d . op0 = op1 ; d . one_vector_p = true ; break ; case 1 : d . op1 = op0 ; d . one_vector_p = true ; break ; } return aarch64_expand_vec_perm_const_1 ( & d ) ; } </s>


<s> bool PPCAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , O ) ; case 'L' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + 1 == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + 1 ) . isReg ( ) ) return true ; ++ OpNo ; break ; case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << "i" ; return false ; case 'x' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) ) return true ; unsigned Reg = MI -> getOperand ( OpNo ) . getReg ( ) ; if ( PPCInstrInfo :: isVRRegister ( Reg ) ) Reg = PPC :: VSX32 + ( Reg - PPC :: V0 ) ; else if ( PPCInstrInfo :: isVFRegister ( Reg ) ) Reg = PPC :: VSX32 + ( Reg - PPC :: VF0 ) ; const char * RegName ; RegName = PPCInstPrinter :: getRegisterName ( Reg ) ; RegName = PPCRegisterInfo :: stripRegisterPrefix ( RegName ) ; O << RegName ; return false ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> void SystemZPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static bool loongarch_int_order_operand_ok_p ( enum rtx_code code , rtx cmp1 ) { switch ( code ) { case GT : case GTU : return reg_or_0_operand ( cmp1 , VOIDmode ) ; case GE : case GEU : return cmp1 == const1_rtx ; case LT : case LTU : return arith_operand ( cmp1 , VOIDmode ) ; case LE : return sle_operand ( cmp1 , VOIDmode ) ; case LEU : return sleu_operand ( cmp1 , VOIDmode ) ; default : gcc_unreachable ( ) ; } } </s>

Return true if CMP1 is a suitable second operand for integer ordering test CODE .


"Teak DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s>
void
avr_final_prescan_insn
(
rtx_insn
*
insn
,
rtx
*
operand
ATTRIBUTE_UNUSED
,
int
num_operands
ATTRIBUTE_UNUSED
)
{
if
(
avr_log
.
rtx_costs
)
{
rtx
set
=
single_set
(
insn
)
;
if
(
set
)
fprintf
(
asm_out_file
,
"/* DEBUG: cost = %d.  */\n"
,
set_src_cost
(
SET_SRC
(
set
)
,
optimize_insn_for_speed_p
(
)
)
)
;
else
fprintf
(
asm_out_file
,
"/* DEBUG: pattern-cost = %d.  */\n"
,
rtx_cost
(
PATTERN
(
insn
)
,
INSN
,
0
,
optimize_insn_for_speed_p
(
)
)
)
;
}
}
</s>

avr
"/* DEBUG: cost = %d.  */\n"
"/* DEBUG: pattern-cost = %d.  */\n"
0


<s> bool Inserter :: runOnMachineFunction ( MachineFunction & F ) { Cpu0FunctionInfo * Cpu0FI = F . getInfo < Cpu0FunctionInfo > ( ) ; if ( ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) || ( ! Cpu0FI -> globalBaseRegFixed ( ) ) ) return false ; bool Changed = false ; int FI = Cpu0FI -> getGPFI ( ) ; for ( MachineFunction :: iterator MFI = F . begin ( ) , MFE = F . end ( ) ; MFI != MFE ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; MachineBasicBlock :: iterator I = MFI -> begin ( ) ; if ( MBB . isLandingPad ( ) ) { for ( ; I -> getOpcode ( ) != TargetOpcode :: EH_LABEL ; ++ I ) ; ++ I ; DebugLoc dl = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; BuildMI ( MBB , I , dl , TII -> get ( Cpu0 :: LD ) , Cpu0 :: GP ) . addFrameIndex ( FI ) . addImm ( 0 ) ; Changed = true ; } while ( I != MFI -> end ( ) ) { if ( I -> getOpcode ( ) != Cpu0 :: JALR ) { ++ I ; continue ; } DebugLoc dl = I -> getDebugLoc ( ) ; BuildMI ( MBB , ++ I , dl , TII -> get ( Cpu0 :: LD ) , Cpu0 :: GP ) . addFrameIndex ( FI ) . addImm ( 0 ) ; Changed = true ; } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s>
bool
HexagonShuffler
::
check
(
const
bool
RequireShuffle
)
{
const
HexagonPacketSummary
Summary
=
GetPacketSummary
(
)
;
if
(
!
applySlotRestrictions
(
Summary
,
RequireShuffle
)
)
return
false
;
if
(
!
ValidPacketMemoryOps
(
Summary
)
)
{
reportError
(
"invalid instruction packet"
)
;
return
false
;
}
if
(
RequireShuffle
)
ValidResourceUsage
(
Summary
)
;
return
!
CheckFailure
;
}
</s>

Check if the constraints are satisfiable .

Hexagon
Hexagon
Hexagon
"invalid instruction packet"


<s> static void emit_unlikely_jump ( rtx cond , rtx label ) { int very_unlikely = REG_BR_PROB_BASE / 100 - 1 ; rtx x = gen_rtx_IF_THEN_ELSE ( VOIDmode , cond , label , pc_rtx ) ; rtx_insn * insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , x ) ) ; add_int_reg_note ( insn , REG_BR_PROB , very_unlikely ) ; } </s>

Mark the previous jump instruction as unlikely .


<s> bool arm_const_double_by_immediates ( rtx val ) { machine_mode mode = GET_MODE ( val ) ; rtx part ; if ( mode == VOIDmode ) mode = DImode ; part = gen_highpart_mode ( SImode , mode , val ) ; gcc_assert ( CONST_INT_P ( part ) ) ; if ( ! const_ok_for_arm ( INTVAL ( part ) ) ) return false ; part = gen_lowpart ( SImode , val ) ; gcc_assert ( CONST_INT_P ( part ) ) ; if ( ! const_ok_for_arm ( INTVAL ( part ) ) ) return false ; return true ; } </s>

Return true if it is possible to inline both the high and low parts of a 64-bit constant into 32-bit data processing instructions .


<s> MCS51Subtarget & MCS51Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS , const TargetMachine & TM ) { ParseSubtargetFeatures ( CPU , CPU , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool HexagonPassConfig :: addInstSelector ( ) { PM -> add ( createHexagonRemoveExtendOps ( getHexagonTargetMachine ( ) ) ) ; PM -> add ( createHexagonISelDag ( getHexagonTargetMachine ( ) ) ) ; PM -> add ( createHexagonPeephole ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .

Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon


"Slot for FPW register must be last in order to be found!"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> unsigned X86InstrInfo :: getUndefRegClearance ( const MachineInstr & MI , unsigned & OpNum , const TargetRegisterInfo * TRI ) const { if ( ! hasUndefRegUpdate ( MI . getOpcode ( ) ) ) return 0 ; OpNum = 1 ; const MachineOperand & MO = MI . getOperand ( OpNum ) ; if ( MO . isUndef ( ) && Register :: isPhysicalRegister ( MO . getReg ( ) ) ) { return UndefRegClearance ; } return 0 ; } </s>

Inform the BreakFalseDeps pass how many idle instructions we would like before certain undef register reads .


<s> bool AArch64InstrInfo :: isThroughputPattern ( MachineCombinerPattern Pattern ) const { switch ( Pattern ) { default : break ; case MachineCombinerPattern :: FMULADDH_OP1 : case MachineCombinerPattern :: FMULADDH_OP2 : case MachineCombinerPattern :: FMULSUBH_OP1 : case MachineCombinerPattern :: FMULSUBH_OP2 : case MachineCombinerPattern :: FMULADDS_OP1 : case MachineCombinerPattern :: FMULADDS_OP2 : case MachineCombinerPattern :: FMULSUBS_OP1 : case MachineCombinerPattern :: FMULSUBS_OP2 : case MachineCombinerPattern :: FMULADDD_OP1 : case MachineCombinerPattern :: FMULADDD_OP2 : case MachineCombinerPattern :: FMULSUBD_OP1 : case MachineCombinerPattern :: FMULSUBD_OP2 : case MachineCombinerPattern :: FNMULSUBH_OP1 : case MachineCombinerPattern :: FNMULSUBS_OP1 : case MachineCombinerPattern :: FNMULSUBD_OP1 : case MachineCombinerPattern :: FMLAv4i16_indexed_OP1 : case MachineCombinerPattern :: FMLAv4i16_indexed_OP2 : case MachineCombinerPattern :: FMLAv8i16_indexed_OP1 : case MachineCombinerPattern :: FMLAv8i16_indexed_OP2 : case MachineCombinerPattern :: FMLAv1i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv1i32_indexed_OP2 : case MachineCombinerPattern :: FMLAv1i64_indexed_OP1 : case MachineCombinerPattern :: FMLAv1i64_indexed_OP2 : case MachineCombinerPattern :: FMLAv4f16_OP2 : case MachineCombinerPattern :: FMLAv4f16_OP1 : case MachineCombinerPattern :: FMLAv8f16_OP1 : case MachineCombinerPattern :: FMLAv8f16_OP2 : case MachineCombinerPattern :: FMLAv2f32_OP2 : case MachineCombinerPattern :: FMLAv2f32_OP1 : case MachineCombinerPattern :: FMLAv2f64_OP1 : case MachineCombinerPattern :: FMLAv2f64_OP2 : case MachineCombinerPattern :: FMLAv2i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv2i32_indexed_OP2 : case MachineCombinerPattern :: FMLAv2i64_indexed_OP1 : case MachineCombinerPattern :: FMLAv2i64_indexed_OP2 : case MachineCombinerPattern :: FMLAv4f32_OP1 : case MachineCombinerPattern :: FMLAv4f32_OP2 : case MachineCombinerPattern :: FMLAv4i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv4i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv4i16_indexed_OP1 : case MachineCombinerPattern :: FMLSv4i16_indexed_OP2 : case MachineCombinerPattern :: FMLSv8i16_indexed_OP1 : case MachineCombinerPattern :: FMLSv8i16_indexed_OP2 : case MachineCombinerPattern :: FMLSv1i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv1i64_indexed_OP2 : case MachineCombinerPattern :: FMLSv2i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv2i64_indexed_OP2 : case MachineCombinerPattern :: FMLSv4f16_OP1 : case MachineCombinerPattern :: FMLSv4f16_OP2 : case MachineCombinerPattern :: FMLSv8f16_OP1 : case MachineCombinerPattern :: FMLSv8f16_OP2 : case MachineCombinerPattern :: FMLSv2f32_OP2 : case MachineCombinerPattern :: FMLSv2f64_OP2 : case MachineCombinerPattern :: FMLSv4i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv4f32_OP2 : case MachineCombinerPattern :: MULADDv8i8_OP1 : case MachineCombinerPattern :: MULADDv8i8_OP2 : case MachineCombinerPattern :: MULADDv16i8_OP1 : case MachineCombinerPattern :: MULADDv16i8_OP2 : case MachineCombinerPattern :: MULADDv4i16_OP1 : case MachineCombinerPattern :: MULADDv4i16_OP2 : case MachineCombinerPattern :: MULADDv8i16_OP1 : case MachineCombinerPattern :: MULADDv8i16_OP2 : case MachineCombinerPattern :: MULADDv2i32_OP1 : case MachineCombinerPattern :: MULADDv2i32_OP2 : case MachineCombinerPattern :: MULADDv4i32_OP1 : case MachineCombinerPattern :: MULADDv4i32_OP2 : case MachineCombinerPattern :: MULSUBv8i8_OP1 : case MachineCombinerPattern :: MULSUBv8i8_OP2 : case MachineCombinerPattern :: MULSUBv16i8_OP1 : case MachineCombinerPattern :: MULSUBv16i8_OP2 : case MachineCombinerPattern :: MULSUBv4i16_OP1 : case MachineCombinerPattern :: MULSUBv4i16_OP2 : case MachineCombinerPattern :: MULSUBv8i16_OP1 : case MachineCombinerPattern :: MULSUBv8i16_OP2 : case MachineCombinerPattern :: MULSUBv2i32_OP1 : case MachineCombinerPattern :: MULSUBv2i32_OP2 : case MachineCombinerPattern :: MULSUBv4i32_OP1 : case MachineCombinerPattern :: MULSUBv4i32_OP2 : case MachineCombinerPattern :: MULADDv4i16_indexed_OP1 : case MachineCombinerPattern :: MULADDv4i16_indexed_OP2 : case MachineCombinerPattern :: MULADDv8i16_indexed_OP1 : case MachineCombinerPattern :: MULADDv8i16_indexed_OP2 : case MachineCombinerPattern :: MULADDv2i32_indexed_OP1 : case MachineCombinerPattern :: MULADDv2i32_indexed_OP2 : case MachineCombinerPattern :: MULADDv4i32_indexed_OP1 : case MachineCombinerPattern :: MULADDv4i32_indexed_OP2 : case MachineCombinerPattern :: MULSUBv4i16_indexed_OP1 : case MachineCombinerPattern :: MULSUBv4i16_indexed_OP2 : case MachineCombinerPattern :: MULSUBv8i16_indexed_OP1 : case MachineCombinerPattern :: MULSUBv8i16_indexed_OP2 : case MachineCombinerPattern :: MULSUBv2i32_indexed_OP1 : case MachineCombinerPattern :: MULSUBv2i32_indexed_OP2 : case MachineCombinerPattern :: MULSUBv4i32_indexed_OP1 : case MachineCombinerPattern :: MULSUBv4i32_indexed_OP2 : return true ; } return false ; } </s>

Return true when a code sequence can improve throughput .


<s> bool XCoreLowerThreadLocal :: runOnModule ( Module & M ) { bool MadeChange = false ; SmallVector < GlobalVariable * , 16 > ThreadLocalGlobals ; for ( Module :: global_iterator GVI = M . global_begin ( ) , E = M . global_end ( ) ; GVI != E ; ++ GVI ) { GlobalVariable * GV = GVI ; if ( GV -> isThreadLocal ( ) ) ThreadLocalGlobals . push_back ( GV ) ; } for ( unsigned I = 0 , E = ThreadLocalGlobals . size ( ) ; I != E ; ++ I ) { MadeChange |= lowerGlobal ( ThreadLocalGlobals [ I ] ) ; } return MadeChange ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> void aarch64_expand_vec_perm ( rtx target , rtx op0 , rtx op1 , rtx sel ) { machine_mode vmode = GET_MODE ( target ) ; unsigned int nelt = GET_MODE_NUNITS ( vmode ) ; bool one_vector_p = rtx_equal_p ( op0 , op1 ) ; rtx mask ; mask = aarch64_simd_gen_const_vector_dup ( vmode , one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; sel = expand_simple_binop ( vmode , AND , sel , mask , NULL , 0 , OPTAB_LIB_WIDEN ) ; if ( BYTES_BIG_ENDIAN ) { if ( ! one_vector_p ) mask = aarch64_simd_gen_const_vector_dup ( vmode , nelt - 1 ) ; sel = expand_simple_binop ( vmode , XOR , sel , mask , NULL , 0 , OPTAB_LIB_WIDEN ) ; } aarch64_expand_vec_perm_1 ( target , op0 , op1 , sel ) ; } </s>

Expand a vec_perm with the operands given by TARGET , OP0 , OP1 and SEL . NELT is the number of elements in the vector .


<s> static void rs6000_emit_probe_stack_range ( HOST_WIDE_INT first , HOST_WIDE_INT size ) { if ( first + size <= 32768 ) { HOST_WIDE_INT i ; for ( i = PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + i ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + size ) ) ) ; } else { HOST_WIDE_INT rounded_size ; rtx r12 = gen_rtx_REG ( Pmode , 12 ) ; rtx r0 = gen_rtx_REG ( Pmode , 0 ) ; gcc_assert ( first <= 32768 ) ; rounded_size = ROUND_DOWN ( size , PROBE_INTERVAL ) ; emit_insn ( gen_rtx_SET ( r12 , plus_constant ( Pmode , stack_pointer_rtx , - first ) ) ) ; if ( rounded_size > 32768 ) { emit_move_insn ( r0 , GEN_INT ( - rounded_size ) ) ; emit_insn ( gen_rtx_SET ( r0 , gen_rtx_PLUS ( Pmode , r12 , r0 ) ) ) ; } else emit_insn ( gen_rtx_SET ( r0 , plus_constant ( Pmode , r12 , - rounded_size ) ) ) ; if ( TARGET_64BIT ) emit_insn ( gen_probe_stack_rangedi ( r12 , r12 , r0 ) ) ; else emit_insn ( gen_probe_stack_rangesi ( r12 , r12 , r0 ) ) ; if ( size != rounded_size ) emit_stack_probe ( plus_constant ( Pmode , r12 , rounded_size - size ) ) ; } } </s>

Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE , inclusive . These are offsets from the current stack pointer .


<s> static bool ix86_save_reg ( unsigned int regno , bool maybe_eh_return ) { if ( cfun -> machine -> no_caller_saved_registers ) { rtx reg = crtl -> return_rtx ; if ( reg ) { unsigned int i = REGNO ( reg ) ; unsigned int nregs = hard_regno_nregs [ i ] [ GET_MODE ( reg ) ] ; while ( nregs -- > 0 ) if ( ( i + nregs ) == regno ) return false ; reg = crtl -> return_bnd ; if ( reg ) { i = REGNO ( reg ) ; nregs = hard_regno_nregs [ i ] [ GET_MODE ( reg ) ] ; while ( nregs -- > 0 ) if ( ( i + nregs ) == regno ) return false ; } } return ( df_regs_ever_live_p ( regno ) && ! fixed_regs [ regno ] && ! STACK_REGNO_P ( regno ) && ! MMX_REGNO_P ( regno ) && ( regno != HARD_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) ) ; } if ( regno == REAL_PIC_OFFSET_TABLE_REGNUM && pic_offset_table_rtx ) { if ( ix86_use_pseudo_pic_reg ( ) ) { if ( ! TARGET_64BIT && flag_pic && crtl -> profile ) return true ; } else if ( df_regs_ever_live_p ( REAL_PIC_OFFSET_TABLE_REGNUM ) || crtl -> profile || crtl -> calls_eh_return || crtl -> uses_const_pool || cfun -> has_nonlocal_label ) return ix86_select_alt_pic_regnum ( ) == INVALID_REGNUM ; } if ( crtl -> calls_eh_return && maybe_eh_return ) { unsigned i ; for ( i = 0 ; ; i ++ ) { unsigned test = EH_RETURN_DATA_REGNO ( i ) ; if ( test == INVALID_REGNUM ) break ; if ( test == regno ) return true ; } } if ( crtl -> drap_reg && regno == REGNO ( crtl -> drap_reg ) && ! cfun -> machine -> no_drap_save_restore ) return true ; return ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] && ! fixed_regs [ regno ] && ( regno != HARD_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) ) ; } </s>


<s> int same_cmp_preceding_p ( rtx i3 ) { rtx i1 , i2 ; i2 = prev_nonnote_insn ( i3 ) ; if ( i2 == NULL_RTX ) return 0 ; i1 = prev_nonnote_insn ( i2 ) ; if ( i1 == NULL_RTX ) return 0 ; return ( INSN_P ( i1 ) && rtx_equal_p ( PATTERN ( i1 ) , PATTERN ( i3 ) ) && any_condjump_p ( i2 ) && onlyjump_p ( i2 ) ) ; } </s>

Return nonzero if we have the same comparison insn as I3 two insns before I3 . I3 is assumed to be a comparison insn .


<s> static int avr_address_cost ( rtx x ) { if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT && ( REG_P ( XEXP ( x , 0 ) ) || GET_CODE ( XEXP ( x , 0 ) ) == SUBREG ) && INTVAL ( XEXP ( x , 1 ) ) >= 61 ) return 18 ; if ( CONSTANT_ADDRESS_P ( x ) ) { if ( avr_io_address_p ( x , 1 ) ) return 2 ; return 4 ; } return 4 ; } </s>

Calculate the cost of a memory address .


<s> void SystemZPostRASchedStrategy :: releaseTopNode ( SUnit * SU ) { const MCSchedClassDesc * SC = DAG -> getSchedClass ( SU ) ; bool AffectsGrouping = ( SC -> isValid ( ) && ( SC -> BeginGroup || SC -> EndGroup ) ) ; SU -> isScheduleHigh = ( AffectsGrouping || SU -> isUnbuffered ) ; Available . insert ( SU ) ; } </s>

SU has had all predecessor dependencies resolved .


<s> const uint16_t * TOYRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { TOY :: R4 , TOY :: R5 , TOY :: R6 , TOY :: R7 , TOY :: R8 , TOY :: R9 , 0 } ; return CalleeSavedRegs ; } </s>


<s> virtual const DLXRegisterInfo & getRegisterInfo ( ) const { return RegisterInfo ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static struct machine_function * bpf_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function > ( ) ; } </s>

Initialize the per-function machine status .


<s> uint16_t getKind ( ) const { return NodeAttrs :: kind ( Attrs ) ; } </s>


<s> static void loongarch_option_override ( void ) { loongarch_option_override_internal ( & global_options ) ; } </s>


<s> const TargetFrameLowering :: SpillSlot * AMDGPUFrameLowering :: getCalleeSavedSpillSlots ( unsigned & NumEntries ) const { NumEntries = 0 ; return 0 ; } </s>

getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs , that contains an entry for each callee saved register that must be spilled to a particular stack location if it is spilled .


<s> static void pdp11_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; * cum += arg . promoted_size_in_bytes ( ) ; } </s>

Worker function for TARGET_FUNCTION_ARG_ADVANCE . Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> static void find_constant ( rtx in_rtx , imm_info * imm_values ) { if ( INSN_P ( in_rtx ) ) in_rtx = PATTERN ( in_rtx ) ; subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , in_rtx , ALL ) if ( const_rtx x = * iter ) switch ( GET_CODE ( x ) ) { case CONST : case SYMBOL_REF : case CONST_INT : ( imm_values -> imm ) ++ ; if ( x86_64_immediate_operand ( CONST_CAST_RTX ( x ) , SImode ) ) ( imm_values -> imm32 ) ++ ; else ( imm_values -> imm64 ) ++ ; break ; case CONST_DOUBLE : case CONST_WIDE_INT : ( imm_values -> imm ) ++ ; ( imm_values -> imm64 ) ++ ; break ; case CODE_LABEL : if ( LABEL_KIND ( x ) == LABEL_NORMAL ) { ( imm_values -> imm ) ++ ; ( imm_values -> imm32 ) ++ ; } break ; default : break ; } } </s>

Compute number of immediate operands of an instruction .


<s> bool MipsPostLegalizerCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: FailedISel ) ) return false ; auto * TPC = & getAnalysis < TargetPassConfig > ( ) ; const Function & F = MF . getFunction ( ) ; bool EnableOpt = MF . getTarget ( ) . getOptLevel ( ) != CodeGenOpt :: None && ! skipFunction ( F ) ; const MipsSubtarget & ST = MF . getSubtarget < MipsSubtarget > ( ) ; const MipsLegalizerInfo * LI = static_cast < const MipsLegalizerInfo * > ( ST . getLegalizerInfo ( ) ) ; GISelKnownBits * KB = & getAnalysis < GISelKnownBitsAnalysis > ( ) . get ( MF ) ; MipsPostLegalizerCombinerInfo PCInfo ( EnableOpt , F . hasOptSize ( ) , F . hasMinSize ( ) , KB , LI ) ; Combiner C ( PCInfo , TPC ) ; return C . combineMachineInstrs ( MF , nullptr ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool preferred_la_operand_p ( rtx op1 , rtx op2 ) { struct s390_address addr ; if ( op2 != const0_rtx ) op1 = gen_rtx_PLUS ( Pmode , op1 , op2 ) ; if ( ! s390_decompose_address ( op1 , & addr ) ) return false ; if ( addr . base && ! REGNO_OK_FOR_BASE_P ( REGNO ( addr . base ) ) ) return false ; if ( addr . indx && ! REGNO_OK_FOR_INDEX_P ( REGNO ( addr . indx ) ) ) return false ; if ( addr . indx && s390_tune >= PROCESSOR_2817_Z196 ) return false ; if ( ! TARGET_64BIT && ! addr . pointer ) return false ; if ( addr . pointer ) return true ; if ( ( addr . base && REG_P ( addr . base ) && REG_POINTER ( addr . base ) ) || ( addr . indx && REG_P ( addr . indx ) && REG_POINTER ( addr . indx ) ) ) return true ; return false ; } </s>

Return true if it is valid * and * preferable to use LA to compute the sum of OP1 and OP2 .


<s> static rtx frv_frame_mem ( machine_mode mode , rtx base , int offset ) { return gen_rtx_MEM ( mode , gen_rtx_PLUS ( Pmode , base , frv_frame_offset_rtx ( offset ) ) ) ; } </s>

Generate ( mem : MODE ( plus : Pmode BASE ( frv_frame_offset OFFSET ) ) ) ) . The prologue and epilogue uses such expressions to access the stack .


<s> const char * MipsTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case MipsISD :: JmpLink : return "MipsISD::JmpLink" ; case MipsISD :: Hi : return "MipsISD::Hi" ; case MipsISD :: Lo : return "MipsISD::Lo" ; case MipsISD :: GPRel : return "MipsISD::GPRel" ; case MipsISD :: Ret : return "MipsISD::Ret" ; case MipsISD :: CMov : return "MipsISD::CMov" ; case MipsISD :: SelectCC : return "MipsISD::SelectCC" ; case MipsISD :: FPSelectCC : return "MipsISD::FPSelectCC" ; case MipsISD :: FPBrcond : return "MipsISD::FPBrcond" ; case MipsISD :: FPCmp : return "MipsISD::FPCmp" ; case MipsISD :: FPRound : return "MipsISD::FPRound" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific

Mips Mips MipsISD::JmpLink "MipsISD::JmpLink" MipsISD::Hi "MipsISD::Hi" MipsISD::Lo "MipsISD::Lo" MipsISD::GPRel "MipsISD::GPRel" MipsISD::Ret "MipsISD::Ret" MipsISD::CMov "MipsISD::CMov" MipsISD::SelectCC "MipsISD::SelectCC" MipsISD::FPSelectCC "MipsISD::FPSelectCC" MipsISD::FPBrcond "MipsISD::FPBrcond" MipsISD::FPCmp "MipsISD::FPCmp" MipsISD::FPRound "MipsISD::FPRound"


<s> bool R600InstrInfo :: fitsConstReadLimitations ( const std :: vector < MachineInstr * > & MIs ) const { std :: vector < unsigned > Consts ; SmallSet < int64_t , 4 > Literals ; for ( unsigned i = 0 , n = MIs . size ( ) ; i < n ; i ++ ) { MachineInstr & MI = * MIs [ i ] ; if ( ! isALUInstr ( MI . getOpcode ( ) ) ) continue ; for ( const auto & Src : getSrcs ( MI ) ) { if ( Src . first -> getReg ( ) == AMDGPU :: ALU_LITERAL_X ) Literals . insert ( Src . second ) ; if ( Literals . size ( ) > 4 ) return false ; if ( Src . first -> getReg ( ) == AMDGPU :: ALU_CONST ) Consts . push_back ( Src . second ) ; if ( AMDGPU :: R600_KC0RegClass . contains ( Src . first -> getReg ( ) ) || AMDGPU :: R600_KC1RegClass . contains ( Src . first -> getReg ( ) ) ) { unsigned Index = RI . getEncodingValue ( Src . first -> getReg ( ) ) & 0xff ; unsigned Chan = RI . getHWRegChan ( Src . first -> getReg ( ) ) ; Consts . push_back ( ( Index << 2 ) | Chan ) ; } } } return fitsConstReadLimitations ( Consts ) ; } </s>

Same but using const index set instead of MI set .


<s> void MOSInstPrinter :: printRegName ( raw_ostream & O , unsigned RegNo ) const { O << getRegisterName ( RegNo ) ; } </s>


<s> static int ia64_register_move_cost ( machine_mode mode , reg_class_t from , reg_class_t to ) { if ( to == ADDL_REGS ) to = GR_REGS ; if ( from == ADDL_REGS ) from = GR_REGS ; if ( from < to ) { reg_class_t tmp = to ; to = from , from = tmp ; } if ( mode == XFmode || mode == RFmode ) { if ( to != GR_REGS || from != GR_REGS ) return memory_move_cost ( mode , to , false ) ; else return 3 ; } switch ( to ) { case PR_REGS : if ( from == PR_REGS ) return 3 ; if ( from != GR_REGS ) return memory_move_cost ( mode , to , false ) ; break ; case BR_REGS : if ( from != GR_REGS && from != GR_AND_BR_REGS ) return memory_move_cost ( mode , to , false ) ; break ; case AR_I_REGS : case AR_M_REGS : if ( from != GR_REGS ) return memory_move_cost ( mode , to , false ) ; break ; case GR_REGS : case FR_REGS : case FP_REGS : case GR_AND_FR_REGS : case GR_AND_BR_REGS : case ALL_REGS : break ; default : gcc_unreachable ( ) ; } return 2 ; } </s>

Calulate the cost of moving data from a register in class FROM to one in class TO , using MODE .


<s> bool BitSimplification :: processBlock ( MachineBasicBlock & B , const RegisterSet & AVs ) { if ( ! BT . reached ( & B ) ) return false ; bool Changed = false ; RegisterSet AVB = AVs ; RegisterSet Defs ; for ( auto I = B . begin ( ) , E = B . end ( ) ; I != E ; ++ I , AVB . insert ( Defs ) ) { MachineInstr * MI = & * I ; Defs . clear ( ) ; HBS :: getInstrDefs ( * MI , Defs ) ; unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == TargetOpcode :: COPY || Opc == TargetOpcode :: REG_SEQUENCE ) continue ; if ( MI -> mayStore ( ) ) { bool T = genStoreUpperHalf ( MI ) ; T = T || genStoreImmediate ( MI ) ; Changed |= T ; continue ; } if ( Defs . count ( ) != 1 ) continue ; const MachineOperand & Op0 = MI -> getOperand ( 0 ) ; if ( ! Op0 . isReg ( ) || ! Op0 . isDef ( ) ) continue ; BitTracker :: RegisterRef RD = Op0 ; if ( ! BT . has ( RD . Reg ) ) continue ; const TargetRegisterClass * FRC = HBS :: getFinalVRegClass ( RD , MRI ) ; const BitTracker :: RegisterCell & RC = BT . lookup ( RD . Reg ) ; if ( FRC -> getID ( ) == Hexagon :: DoubleRegsRegClassID ) { bool T = genPackhl ( MI , RD , RC ) ; Changed |= T ; continue ; } if ( FRC -> getID ( ) == Hexagon :: IntRegsRegClassID ) { bool T = genExtractHalf ( MI , RD , RC ) ; T = T || genCombineHalf ( MI , RD , RC ) ; T = T || genExtractLow ( MI , RD , RC ) ; Changed |= T ; continue ; } if ( FRC -> getID ( ) == Hexagon :: PredRegsRegClassID ) { bool T = simplifyTstbit ( MI , RD , RC ) ; Changed |= T ; continue ; } } return Changed ; } </s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .

Hexagon 1 0 Hexagon::DoubleRegsRegClassID Hexagon::IntRegsRegClassID Hexagon::PredRegsRegClassID


<s> static void ix86_emit_restore_reg_using_pop ( rtx reg ) { struct machine_function * m = cfun -> machine ; rtx insn = emit_insn ( gen_pop ( reg ) ) ; ix86_add_cfa_restore_note ( insn , reg , m -> fs . sp_offset ) ; m -> fs . sp_offset -= UNITS_PER_WORD ; if ( m -> fs . cfa_reg == crtl -> drap_reg && REGNO ( reg ) == REGNO ( crtl -> drap_reg ) ) { add_reg_note ( insn , REG_CFA_DEF_CFA , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; m -> fs . drap_valid = true ; return ; } if ( m -> fs . cfa_reg == stack_pointer_rtx ) { rtx x = plus_constant ( Pmode , stack_pointer_rtx , UNITS_PER_WORD ) ; x = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , x ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , x ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; m -> fs . cfa_offset -= UNITS_PER_WORD ; } if ( reg == hard_frame_pointer_rtx ) { m -> fs . fp_valid = false ; if ( m -> fs . cfa_reg == hard_frame_pointer_rtx ) { m -> fs . cfa_reg = stack_pointer_rtx ; m -> fs . cfa_offset -= UNITS_PER_WORD ; add_reg_note ( insn , REG_CFA_DEF_CFA , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( m -> fs . cfa_offset ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } } </s>

Emit code to restore REG using a POP insn .


<s> bool RISCVTargetMachine :: isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DstAS ) const { return true ; } </s>

Returns true if a cast between SrcAS and DestAS is a noop .


<s> void ix86_expand_vector_init ( bool mmx_ok , rtx target , rtx vals ) { machine_mode mode = GET_MODE ( target ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; int n_elts = GET_MODE_NUNITS ( mode ) ; int n_var = 0 , one_var = - 1 ; bool all_same = true , all_const_zero = true ; int i ; rtx x ; if ( n_elts != XVECLEN ( vals , 0 ) ) { rtx subtarget = target ; x = XVECEXP ( vals , 0 , 0 ) ; gcc_assert ( GET_MODE_INNER ( GET_MODE ( x ) ) == inner_mode ) ; if ( GET_MODE_NUNITS ( GET_MODE ( x ) ) * 2 == n_elts ) { rtx ops [ 2 ] = { XVECEXP ( vals , 0 , 0 ) , XVECEXP ( vals , 0 , 1 ) } ; if ( inner_mode == QImode || inner_mode == HImode || inner_mode == TImode || inner_mode == HFmode || inner_mode == BFmode ) { unsigned int n_bits = n_elts * GET_MODE_SIZE ( inner_mode ) ; scalar_mode elt_mode = inner_mode == TImode ? DImode : SImode ; n_bits /= GET_MODE_SIZE ( elt_mode ) ; mode = mode_for_vector ( elt_mode , n_bits ) . require ( ) ; inner_mode = mode_for_vector ( elt_mode , n_bits / 2 ) . require ( ) ; ops [ 0 ] = gen_lowpart ( inner_mode , ops [ 0 ] ) ; ops [ 1 ] = gen_lowpart ( inner_mode , ops [ 1 ] ) ; subtarget = gen_reg_rtx ( mode ) ; } ix86_expand_vector_init_concat ( mode , subtarget , ops , 2 ) ; if ( subtarget != target ) emit_move_insn ( target , gen_lowpart ( GET_MODE ( target ) , subtarget ) ) ; return ; } gcc_unreachable ( ) ; } for ( i = 0 ; i < n_elts ; ++ i ) { x = XVECEXP ( vals , 0 , i ) ; if ( ! ( CONST_SCALAR_INT_P ( x ) || CONST_DOUBLE_P ( x ) || CONST_FIXED_P ( x ) ) ) n_var ++ , one_var = i ; else if ( x != CONST0_RTX ( inner_mode ) ) all_const_zero = false ; if ( i > 0 && ! rtx_equal_p ( x , XVECEXP ( vals , 0 , 0 ) ) ) all_same = false ; } if ( n_var == 0 ) { emit_move_insn ( target , gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , 0 ) ) ) ; return ; } if ( all_same && ix86_expand_vector_init_duplicate ( mmx_ok , mode , target , XVECEXP ( vals , 0 , 0 ) ) ) return ; if ( n_var == 1 ) { if ( all_const_zero && ix86_expand_vector_init_one_nonzero ( mmx_ok , mode , target , XVECEXP ( vals , 0 , one_var ) , one_var ) ) return ; if ( ix86_expand_vector_init_one_var ( mmx_ok , mode , target , vals , one_var ) ) return ; } ix86_expand_vector_init_general ( mmx_ok , mode , target , vals ) ; } </s>

Initialize vector TARGET via VALS . Suppress the use of MMX instructions unless MMX_OK is true .


<s>
void
RISCVAsmBackend
::
relaxInstruction
(
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
)
const
{
MCInst
Res
;
switch
(
Inst
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Opcode not expected!"
)
;
case
RISCV
::
C_BEQZ
:
Res
.
setOpcode
(
RISCV
::
BEQ
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
Res
.
addOperand
(
MCOperand
::
createReg
(
RISCV
::
X0
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
1
)
)
;
break
;
case
RISCV
::
C_BNEZ
:
Res
.
setOpcode
(
RISCV
::
BNE
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
Res
.
addOperand
(
MCOperand
::
createReg
(
RISCV
::
X0
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
1
)
)
;
break
;
case
RISCV
::
C_J
:
Res
.
setOpcode
(
RISCV
::
JAL
)
;
Res
.
addOperand
(
MCOperand
::
createReg
(
RISCV
::
X0
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
break
;
case
RISCV
::
C_JAL
:
Res
.
setOpcode
(
RISCV
::
JAL
)
;
Res
.
addOperand
(
MCOperand
::
createReg
(
RISCV
::
X1
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
break
;
}
Inst
=
std
::
move
(
Res
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> TargetIRAnalysis NVPTXTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( const Function & F ) { return TargetTransformInfo ( NVPTXTTIImpl ( this , F ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


<s> bool PPCTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( ! EnablePPCPreinc ) return false ; SDValue Ptr ; MVT VT ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { ST = ST ; Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; } else return false ; if ( VT . isVector ( ) ) return false ; if ( VT != MVT :: i64 ) { if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG ) ) return false ; } else { if ( ! SelectAddressRegImmShift ( Ptr , Offset , Base , DAG ) ) return false ; } if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { if ( LD -> getValueType ( 0 ) == MVT :: i64 && LD -> getMemoryVT ( ) == MVT :: i32 && LD -> getExtensionType ( ) == ISD :: SEXTLOAD && isa < ConstantSDNode > ( Offset ) ) return false ; } AM = ISD :: PRE_INC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .


<s> TargetLowering :: ConstraintWeight PPCTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; const Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'b' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; case 'd' : if ( type -> isDoubleTy ( ) ) weight = CW_Register ; break ; case 'v' : if ( type -> isVectorTy ( ) ) weight = CW_Register ; break ; case 'y' : weight = CW_Register ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s>
bool
AArch64InstrInfo
::
areMemAccessesTriviallyDisjoint
(
MachineInstr
*
MIa
,
MachineInstr
*
MIb
,
AliasAnalysis
*
AA
)
const
{
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
unsigned
BaseRegA
=
0
,
BaseRegB
=
0
;
int
OffsetA
=
0
,
OffsetB
=
0
;
int
WidthA
=
0
,
WidthB
=
0
;
assert
(
MIa
&&
MIa
->
mayLoadOrStore
(
)
&&
"MIa must be a load or store."
)
;
assert
(
MIb
&&
MIb
->
mayLoadOrStore
(
)
&&
"MIb must be a load or store."
)
;
if
(
MIa
->
hasUnmodeledSideEffects
(
)
||
MIb
->
hasUnmodeledSideEffects
(
)
||
MIa
->
hasOrderedMemoryRef
(
)
||
MIb
->
hasOrderedMemoryRef
(
)
)
return
false
;
if
(
getLdStBaseRegImmOfsWidth
(
MIa
,
BaseRegA
,
OffsetA
,
WidthA
,
TRI
)
&&
getLdStBaseRegImmOfsWidth
(
MIb
,
BaseRegB
,
OffsetB
,
WidthB
,
TRI
)
)
{
if
(
BaseRegA
==
BaseRegB
)
{
int
LowOffset
=
OffsetA
<
OffsetB
OffsetA
:
OffsetB
;
int
HighOffset
=
OffsetA
<
OffsetB
OffsetB
:
OffsetA
;
int
LowWidth
=
(
LowOffset
==
OffsetA
)
WidthA
:
WidthB
;
if
(
LowOffset
+
LowWidth
<=
HighOffset
)
return
true
;
}
}
return
false
;
}
</s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < AMDGPUArgumentUsageInfo > ( ) ; AU . addRequired < AMDGPUPerfHintAnalysis > ( ) ; AU . addRequired < DivergenceAnalysis > ( ) ; SelectionDAGISel :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> unsigned postOffset ( unsigned LogAlign = 0 ) const { unsigned PO = Offset + Size ; unsigned Align = 1 << LogAlign ; return ( PO + Align - 1 ) / Align * Align ; } </s>

Compute the offset immediately following this block .


<s> bool AMDGPUInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock * MBB = MI -> getParent ( ) ; switch ( MI -> getOpcode ( ) ) { default : if ( isRegisterLoad ( * MI ) ) { unsigned RegIndex = MI -> getOperand ( 2 ) . getImm ( ) ; unsigned Channel = MI -> getOperand ( 3 ) . getImm ( ) ; unsigned Address = calculateIndirectAddress ( RegIndex , Channel ) ; unsigned OffsetReg = MI -> getOperand ( 1 ) . getReg ( ) ; if ( OffsetReg == AMDGPU :: INDIRECT_BASE_ADDR ) { buildMovInstr ( MBB , MI , MI -> getOperand ( 0 ) . getReg ( ) , getIndirectAddrRegClass ( ) -> getRegister ( Address ) ) ; } else { buildIndirectRead ( MBB , MI , MI -> getOperand ( 0 ) . getReg ( ) , Address , OffsetReg ) ; } } else if ( isRegisterStore ( * MI ) ) { unsigned RegIndex = MI -> getOperand ( 2 ) . getImm ( ) ; unsigned Channel = MI -> getOperand ( 3 ) . getImm ( ) ; unsigned Address = calculateIndirectAddress ( RegIndex , Channel ) ; unsigned OffsetReg = MI -> getOperand ( 1 ) . getReg ( ) ; if ( OffsetReg == AMDGPU :: INDIRECT_BASE_ADDR ) { buildMovInstr ( MBB , MI , getIndirectAddrRegClass ( ) -> getRegister ( Address ) , MI -> getOperand ( 0 ) . getReg ( ) ) ; } else { buildIndirectWrite ( MBB , MI , MI -> getOperand ( 0 ) . getReg ( ) , calculateIndirectAddress ( RegIndex , Channel ) , OffsetReg ) ; } } else { return false ; } } MBB -> erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s>
SDValue
SystemZTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
isVarArg
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .

SystemZ
SystemZ
ISD::InputArg
"Unsupported calling convention"


<s> int arm_early_load_addr_dep ( rtx producer , rtx consumer ) { rtx value , addr ; if ( ! arm_get_set_operands ( producer , consumer , & value , & addr ) ) return 0 ; return reg_overlap_mentioned_p ( value , addr ) ; } </s>

Return nonzero if the CONSUMER instruction ( a load ) does need PRODUCER 's value to calculate the address .


<s> enum attr_op_mem m68k_sched_attr_op_mem ( rtx_insn * insn ) { enum attr_op_type opx ; enum attr_op_type opy ; opx = sched_get_opxy_mem_type ( insn , true ) ; opy = sched_get_opxy_mem_type ( insn , false ) ; if ( opy == OP_TYPE_RN && opx == OP_TYPE_RN ) return OP_MEM_00 ; if ( opy == OP_TYPE_RN && opx == OP_TYPE_MEM1 ) { switch ( get_attr_opx_access ( insn ) ) { case OPX_ACCESS_R : return OP_MEM_10 ; case OPX_ACCESS_W : return OP_MEM_01 ; case OPX_ACCESS_RW : return OP_MEM_11 ; default : gcc_unreachable ( ) ; } } if ( opy == OP_TYPE_RN && opx == OP_TYPE_MEM6 ) { switch ( get_attr_opx_access ( insn ) ) { case OPX_ACCESS_R : return OP_MEM_I0 ; case OPX_ACCESS_W : return OP_MEM_0I ; case OPX_ACCESS_RW : return OP_MEM_I1 ; default : gcc_unreachable ( ) ; } } if ( opy == OP_TYPE_MEM1 && opx == OP_TYPE_RN ) return OP_MEM_10 ; if ( opy == OP_TYPE_MEM1 && opx == OP_TYPE_MEM1 ) { switch ( get_attr_opx_access ( insn ) ) { case OPX_ACCESS_W : return OP_MEM_11 ; default : gcc_assert ( ! reload_completed ) ; return OP_MEM_11 ; } } if ( opy == OP_TYPE_MEM1 && opx == OP_TYPE_MEM6 ) { switch ( get_attr_opx_access ( insn ) ) { case OPX_ACCESS_W : return OP_MEM_1I ; default : gcc_assert ( ! reload_completed ) ; return OP_MEM_1I ; } } if ( opy == OP_TYPE_MEM6 && opx == OP_TYPE_RN ) return OP_MEM_I0 ; if ( opy == OP_TYPE_MEM6 && opx == OP_TYPE_MEM1 ) { switch ( get_attr_opx_access ( insn ) ) { case OPX_ACCESS_W : return OP_MEM_I1 ; default : gcc_assert ( ! reload_completed ) ; return OP_MEM_I1 ; } } gcc_assert ( opy == OP_TYPE_MEM6 && opx == OP_TYPE_MEM6 ) ; gcc_assert ( ! reload_completed ) ; return OP_MEM_I1 ; } </s>


<s> bool AlphaAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; O << "0(" ; printOperand ( MI , OpNo ) ; O << ")" ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s>
void
SystemZPostRASchedStrategy
::
enterMBB
(
MachineBasicBlock
*
NextMBB
)
{
assert
(
(
SchedStates
.
find
(
NextMBB
)
==
SchedStates
.
end
(
)
)
&&
"Entering MBB twice?"
)
;
DEBUG
(
dbgs
(
)
<<
"** Entering "
<<
printMBBReference
(
*
NextMBB
)
)
;
MBB
=
NextMBB
;
HazardRec
=
SchedStates
[
MBB
]
=
new
SystemZHazardRecognizer
(
TII
,
&
SchedModel
)
;
DEBUG
(
const
MachineLoop
*
Loop
=
MLI
->
getLoopFor
(
MBB
)
;
if
(
Loop
&&
Loop
->
getHeader
(
)
==
MBB
)
dbgs
(
)
<<
" (Loop header)"
;
dbgs
(
)
<<
":\n"
;
)
;
MachineBasicBlock
*
SinglePredMBB
=
getSingleSchedPred
(
MBB
,
MLI
->
getLoopFor
(
MBB
)
)
;
if
(
SinglePredMBB
==
nullptr
||
SchedStates
.
find
(
SinglePredMBB
)
==
SchedStates
.
end
(
)
)
return
;
DEBUG
(
dbgs
(
)
<<
"** Continued scheduling from "
<<
printMBBReference
(
*
SinglePredMBB
)
<<
"\n"
;
)
;
HazardRec
->
copyState
(
SchedStates
[
SinglePredMBB
]
)
;
DEBUG
(
HazardRec
->
dumpState
(
)
;
)
;
for
(
MachineBasicBlock
::
iterator
I
=
SinglePredMBB
->
getFirstTerminator
(
)
;
I
!=
SinglePredMBB
->
end
(
)
;
I
++
)
{
DEBUG
(
dbgs
(
)
<<
"** Emitting incoming branch: "
;
I
->
dump
(
)
;
)
;
bool
TakenBranch
=
(
I
->
isBranch
(
)
&&
(
TII
->
getBranchInfo
(
*
I
)
.
Target
->
isReg
(
)
||
TII
->
getBranchInfo
(
*
I
)
.
Target
->
getMBB
(
)
==
MBB
)
)
;
HazardRec
->
emitInstruction
(
&
*
I
,
TakenBranch
)
;
if
(
TakenBranch
)
break
;
}
}
</s>

Tell the strategy that MBB is about to be processed .

SystemZ
SystemZ
"Entering MBB twice?"
"** Entering "
SystemZ
" (Loop header)"
":\n"
"** Continued scheduling from "
"\n"
"** Emitting incoming branch: "


<s> static bool callees_functions_use_frame_header ( function * fn ) { basic_block bb ; gimple_stmt_iterator gsi ; gimple * stmt ; tree called_fn_tree ; function * called_fn ; if ( fn -> cfg == NULL ) return true ; FOR_EACH_BB_FN ( bb , fn ) { for ( gsi = gsi_start_bb ( bb ) ; ! gsi_end_p ( gsi ) ; gsi_next ( & gsi ) ) { stmt = gsi_stmt ( gsi ) ; if ( is_gimple_call ( stmt ) ) { called_fn_tree = gimple_call_fndecl ( stmt ) ; if ( called_fn_tree != NULL ) { called_fn = DECL_STRUCT_FUNCTION ( called_fn_tree ) ; if ( called_fn == NULL || DECL_WEAK ( called_fn_tree ) || has_inlined_assembly ( called_fn ) || ! is_leaf_function ( called_fn ) || ! called_fn -> machine -> does_not_use_frame_header ) return true ; } else return true ; } } } return false ; } </s>

Return true if the argument stack space allocated by function FN is used . Return false if the space is needed or if the need for the space can not be determined .


<s> bool ARMAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AFI = MF . getInfo < ARMFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; Subtarget = & MF . getSubtarget < ARMSubtarget > ( ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = MF . getFunction ( ) -> hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer -> EmitCOFFSymbolType ( Type ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; if ( ! ThumbIndirectPads . empty ( ) ) { OutStreamer -> EmitAssemblerFlag ( MCAF_Code16 ) ; EmitAlignment ( 1 ) ; for ( unsigned i = 0 , e = ThumbIndirectPads . size ( ) ; i < e ; i ++ ) { OutStreamer -> EmitLabel ( ThumbIndirectPads [ i ] . second ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( ARM :: tBX ) . addReg ( ThumbIndirectPads [ i ] . first ) . addImm ( ARMCC :: AL ) . addReg ( 0 ) ) ; } ThumbIndirectPads . clear ( ) ; } return false ; } </s>

runOnMachineFunction - Emit the function body .

ARM ARM ARM ARM 1 0 ARM::tBX ARMCC::AL 0


<s> const MCPhysReg * AMDGPURegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return & CalleeSavedReg ; } </s>


<s> rtx sh_dwarf_register_span ( rtx reg ) { unsigned regno = REGNO ( reg ) ; if ( WORDS_BIG_ENDIAN || GET_MODE ( reg ) != DFmode ) return NULL_RTX ; return gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , gen_rtx_REG ( SFmode , regno + 1 ) , gen_rtx_REG ( SFmode , regno ) ) ) ; } </s>

64 bit floating points memory transfers are paired single precision loads or store . So DWARF information needs fixing in little endian ( unless PR=SZ=1 in FPSCR ) .


<s> int memreg_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { return GET_CODE ( op ) == MEM && GET_CODE ( XEXP ( op , 0 ) ) == REG ; } </s>

Return 1 if OP is ( mem ( reg ... ) ) . This is used in insn length calcs .


<s> static bool s390_cannot_force_const_mem ( machine_mode mode , rtx x ) { switch ( GET_CODE ( x ) ) { case CONST_INT : case CONST_DOUBLE : return false ; case LABEL_REF : return flag_pic != 0 ; case SYMBOL_REF : if ( tls_symbolic_operand ( x ) ) return true ; else return flag_pic != 0 ; case CONST : return s390_cannot_force_const_mem ( mode , XEXP ( x , 0 ) ) ; case PLUS : case MINUS : return s390_cannot_force_const_mem ( mode , XEXP ( x , 0 ) ) || s390_cannot_force_const_mem ( mode , XEXP ( x , 1 ) ) ; case UNSPEC : switch ( XINT ( x , 1 ) ) { case UNSPEC_LTREL_OFFSET : case UNSPEC_GOT : case UNSPEC_GOTOFF : case UNSPEC_PLTOFF : case UNSPEC_TLSGD : case UNSPEC_TLSLDM : case UNSPEC_NTPOFF : case UNSPEC_DTPOFF : case UNSPEC_GOTNTPOFF : case UNSPEC_INDNTPOFF : return false ; case UNSPEC_INSN : return TARGET_CPU_ZARCH ; default : return true ; } break ; default : gcc_unreachable ( ) ; } } </s>

Determine if it 's legal to put X into the constant pool . This is not possible if X contains the address of a symbol that is not constant ( TLS ) or not known at final link time ( PIC ) .


<s> bool SIPostRABundler :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; TRI = MF . getSubtarget < GCNSubtarget > ( ) . getRegisterInfo ( ) ; BitVector BundleUsedRegUnits ( TRI -> getNumRegUnits ( ) ) ; BitVector KillUsedRegUnits ( TRI -> getNumRegUnits ( ) ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { MachineBasicBlock :: instr_iterator Next ; MachineBasicBlock :: instr_iterator B = MBB . instr_begin ( ) ; MachineBasicBlock :: instr_iterator E = MBB . instr_end ( ) ; for ( auto I = B ; I != E ; I = Next ) { Next = std :: next ( I ) ; if ( ! isBundleCandidate ( * I ) ) continue ; assert ( Defs . empty ( ) ) ; if ( I -> getNumExplicitDefs ( ) != 0 ) Defs . insert ( I -> defs ( ) . begin ( ) -> getReg ( ) ) ; MachineBasicBlock :: instr_iterator BundleStart = I ; MachineBasicBlock :: instr_iterator BundleEnd = I ; unsigned ClauseLength = 1 ; for ( I = Next ; I != E ; I = Next ) { Next = std :: next ( I ) ; assert ( BundleEnd != I ) ; if ( canBundle ( * BundleEnd , * I ) ) { BundleEnd = I ; if ( I -> getNumExplicitDefs ( ) != 0 ) Defs . insert ( I -> defs ( ) . begin ( ) -> getReg ( ) ) ; ++ ClauseLength ; } else if ( ! I -> isMetaInstruction ( ) ) { break ; } } Next = std :: next ( BundleEnd ) ; if ( ClauseLength > 1 ) { Changed = true ; if ( Next != E && Next -> isKill ( ) ) { for ( const MachineInstr & BundleMI : make_range ( BundleStart , Next ) ) collectUsedRegUnits ( BundleMI , BundleUsedRegUnits ) ; BundleUsedRegUnits . flip ( ) ; while ( Next != E && Next -> isKill ( ) ) { MachineInstr & Kill = * Next ; collectUsedRegUnits ( Kill , KillUsedRegUnits ) ; KillUsedRegUnits &= BundleUsedRegUnits ; if ( KillUsedRegUnits . none ( ) ) { ++ Next ; Kill . eraseFromParent ( ) ; } else break ; KillUsedRegUnits . reset ( ) ; } BundleUsedRegUnits . reset ( ) ; } finalizeBundle ( MBB , BundleStart , Next ) ; } Defs . clear ( ) ; } } return Changed ; } </s>


<s> bool BitSimplification :: processBlock ( MachineBasicBlock & B , const RegisterSet & AVs ) { bool Changed = false ; RegisterSet AVB = AVs ; RegisterSet Defs ; for ( auto I = B . begin ( ) , E = B . end ( ) ; I != E ; ++ I , AVB . insert ( Defs ) ) { MachineInstr * MI = & * I ; Defs . clear ( ) ; HBS :: getInstrDefs ( * MI , Defs ) ; unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == TargetOpcode :: COPY || Opc == TargetOpcode :: REG_SEQUENCE ) continue ; if ( MI -> mayStore ( ) ) { bool T = genStoreUpperHalf ( MI ) ; T = T || genStoreImmediate ( MI ) ; Changed |= T ; continue ; } if ( Defs . count ( ) != 1 ) continue ; const MachineOperand & Op0 = MI -> getOperand ( 0 ) ; if ( ! Op0 . isReg ( ) || ! Op0 . isDef ( ) ) continue ; BitTracker :: RegisterRef RD = Op0 ; if ( ! BT . has ( RD . Reg ) ) continue ; const TargetRegisterClass * FRC = HBS :: getFinalVRegClass ( RD , MRI ) ; const BitTracker :: RegisterCell & RC = BT . lookup ( RD . Reg ) ; if ( FRC -> getID ( ) == Hexagon :: DoubleRegsRegClassID ) { bool T = genPackhl ( MI , RD , RC ) ; Changed |= T ; continue ; } if ( FRC -> getID ( ) == Hexagon :: IntRegsRegClassID ) { bool T = genExtractHalf ( MI , RD , RC ) ; T = T || genCombineHalf ( MI , RD , RC ) ; T = T || genExtractLow ( MI , RD , RC ) ; Changed |= T ; continue ; } if ( FRC -> getID ( ) == Hexagon :: PredRegsRegClassID ) { bool T = simplifyTstbit ( MI , RD , RC ) ; Changed |= T ; continue ; } } return Changed ; } </s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s> static machine_mode select_block_compare_mode ( unsigned HOST_WIDE_INT offset , unsigned HOST_WIDE_INT bytes , unsigned HOST_WIDE_INT align , bool word_mode_ok ) { unsigned HOST_WIDE_INT maxread = ROUND_UP ( bytes , align ) ; if ( word_mode_ok && bytes >= UNITS_PER_WORD ) return word_mode ; else if ( bytes == GET_MODE_SIZE ( SImode ) ) return SImode ; else if ( bytes == GET_MODE_SIZE ( HImode ) ) return HImode ; else if ( bytes == GET_MODE_SIZE ( QImode ) ) return QImode ; else if ( bytes < GET_MODE_SIZE ( SImode ) && offset >= GET_MODE_SIZE ( SImode ) - bytes ) return SImode ; else if ( word_mode_ok && bytes < UNITS_PER_WORD && offset >= UNITS_PER_WORD - bytes ) return word_mode ; else if ( word_mode_ok && maxread >= UNITS_PER_WORD ) return word_mode ; else if ( maxread >= GET_MODE_SIZE ( SImode ) ) return SImode ; else if ( bytes > GET_MODE_SIZE ( SImode ) ) return SImode ; else if ( bytes > GET_MODE_SIZE ( HImode ) ) return HImode ; return QImode ; } </s>

Select the mode to be used for reading the next chunk of bytes in the compare . OFFSET is the current read offset from the beginning of the block . BYTES is the number of bytes remaining to be read . ALIGN is the minimum alignment of the memory blocks being compared in bytes .


<s> FunctionPass * PTXPassConfig :: createTargetRegisterAllocator ( bool ) { return createPTXRegisterAllocator ( ) ; } </s>

createTargetRegisterAllocator - Create the register allocator pass for this target at the current optimization level .


<s> std :: pair < unsigned , unsigned > M680x0InstrInfo :: decomposeMachineOperandsTargetFlags ( unsigned TF ) const { return std :: make_pair ( TF , 0u ) ; } </s>

Decompose the machine operand 's target flags into two values - the direct target flag value and any of bit flags that are applied .


<s> int avr_function_arg_regno_p ( int r ) { return AVR_TINY ? IN_RANGE ( r , 20 , 25 ) : IN_RANGE ( r , 8 , 25 ) ; } </s>

Returns nonzero if REGNO is the number of a hard register in which function arguments are sometimes passed .


<s> BitVector Cpu0RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t ReservedCPURegs [ ] = { Cpu0 :: ZERO , Cpu0 :: AT , Cpu0 :: FP , Cpu0 :: SP , Cpu0 :: LR , Cpu0 :: PC } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: iterator RegIter ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; if ( MF . getInfo < Cpu0FunctionInfo > ( ) -> globalBaseRegFixed ( ) ) { Reserved . set ( Cpu0 :: GP ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> std :: pair < unsigned , const TargetRegisterClass * > SPUTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'b' : case 'r' : if ( VT == MVT :: i64 ) return std :: make_pair ( 0U , SPU :: R64CRegisterClass ) ; return std :: make_pair ( 0U , SPU :: R32CRegisterClass ) ; case 'f' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , SPU :: R32FPRegisterClass ) ; else if ( VT == MVT :: f64 ) return std :: make_pair ( 0U , SPU :: R64FPRegisterClass ) ; break ; case 'v' : return std :: make_pair ( 0U , SPU :: GPRCRegisterClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


Targets should implement this method to assign a section to globals with an explicit section specfied .


<s> void printPCRelImm ( const MCInst * MI , uint64_t , unsigned OpNo , raw_ostream & O ) { printPCRelImm ( MI , OpNo , O ) ; } </s>


<s> static dispatch_windows * allocate_next_window ( int window_num ) { if ( window_num == 0 ) { if ( dispatch_window_list -> next ) init_window ( 1 ) ; init_window ( 0 ) ; return dispatch_window_list ; } dispatch_window_list -> next = dispatch_window_list1 ; dispatch_window_list1 -> prev = dispatch_window_list ; return dispatch_window_list1 ; } </s>

Allocates a new dispatch window and adds it to WINDOW_LIST . WINDOW_NUM is either 0 or 1 . A maximum of two windows are generated for 48 bytes of instructions . Note that these windows are not dispatch windows that their sizes are DISPATCH_WINDOW_SIZE .


<s> static bool frv_issues_to_branch_unit_p ( rtx insn ) { return frv_unit_groups [ frv_insn_unit ( insn ) ] == GROUP_B ; } </s>

Return true if INSN issues to a branch unit .


<s>
Register
PPCTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
LLT
VT
,
const
MachineFunction
&
MF
)
const
{
bool
isPPC64
=
Subtarget
.
isPPC64
(
)
;
bool
is64Bit
=
isPPC64
&&
VT
==
LLT
::
scalar
(
64
)
;
if
(
!
is64Bit
&&
VT
!=
LLT
::
scalar
(
32
)
)
report_fatal_error
(
"Invalid register global variable type"
)
;
Register
Reg
=
StringSwitch
<
Register
>
(
RegName
)
.
Case
(
"r1"
,
is64Bit
PPC
::
X1
:
PPC
::
R1
)
.
Case
(
"r2"
,
isPPC64
Register
(
)
:
PPC
::
R2
)
.
Case
(
"r13"
,
(
is64Bit
PPC
::
X13
:
PPC
::
R13
)
)
.
Default
(
Register
(
)
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s>
int
AArch64TTIImpl
::
getArithmeticReductionCost
(
unsigned
Opcode
,
VectorType
*
ValTy
,
bool
IsPairwiseForm
,
TTI
::
TargetCostKind
CostKind
)
{
if
(
IsPairwiseForm
)
return
BaseT
::
getArithmeticReductionCost
(
Opcode
,
ValTy
,
IsPairwiseForm
,
CostKind
)
;
std
::
pair
<
int
,
MVT
>
LT
=
TLI
->
getTypeLegalizationCost
(
DL
,
ValTy
)
;
MVT
MTy
=
LT
.
second
;
int
ISD
=
TLI
->
InstructionOpcodeToISD
(
Opcode
)
;
assert
(
ISD
&&
"Invalid opcode"
)
;
static
const
CostTblEntry
CostTblNoPairwise
[
]
{
{
ISD
::
ADD
,
MVT
::
v8i8
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v16i8
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v4i16
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v8i16
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v4i32
,
1
}
,
}
;
if
(
const
auto
*
Entry
=
CostTableLookup
(
CostTblNoPairwise
,
ISD
,
MTy
)
)
return
LT
.
first
*
Entry
->
Cost
;
return
BaseT
::
getArithmeticReductionCost
(
Opcode
,
ValTy
,
IsPairwiseForm
,
CostKind
)
;
}
</s>

Calculate the cost of vector reduction intrinsics .


<s> static void mips_sim_wait_reg ( struct mips_sim * state , rtx insn , rtx reg ) { unsigned int i ; for ( i = 0 ; i < HARD_REGNO_NREGS ( REGNO ( reg ) , GET_MODE ( reg ) ) ; i ++ ) if ( state -> last_set [ REGNO ( reg ) + i ] . insn != 0 ) { unsigned int t ; t = state -> last_set [ REGNO ( reg ) + i ] . time ; t += insn_latency ( state -> last_set [ REGNO ( reg ) + i ] . insn , insn ) ; while ( state -> time < t ) mips_sim_next_cycle ( state ) ; } } </s>

Advance simulation state STATE until instruction INSN can read register REG .


"Frame offsets outside of the signed 16-bit range not supported"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static bool spu_legitimate_address_p ( machine_mode mode , rtx x , bool reg_ok_strict ) { int aligned = GET_MODE_SIZE ( mode ) >= 16 ; if ( aligned && GET_CODE ( x ) == AND && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT && INTVAL ( XEXP ( x , 1 ) ) == ( HOST_WIDE_INT ) - 16 ) x = XEXP ( x , 0 ) ; switch ( GET_CODE ( x ) ) { case LABEL_REF : return ! TARGET_LARGE_MEM ; case SYMBOL_REF : case CONST : if ( ea_symbol_ref_p ( x ) ) return ! reload_in_progress && ! reload_completed ; return ! TARGET_LARGE_MEM ; case CONST_INT : return INTVAL ( x ) >= 0 && INTVAL ( x ) <= 0x3ffff ; case SUBREG : x = XEXP ( x , 0 ) ; if ( REG_P ( x ) ) return 0 ; case REG : return INT_REG_OK_FOR_BASE_P ( x , reg_ok_strict ) ; case PLUS : case LO_SUM : { rtx op0 = XEXP ( x , 0 ) ; rtx op1 = XEXP ( x , 1 ) ; if ( GET_CODE ( op0 ) == SUBREG ) op0 = XEXP ( op0 , 0 ) ; if ( GET_CODE ( op1 ) == SUBREG ) op1 = XEXP ( op1 , 0 ) ; if ( GET_CODE ( op0 ) == REG && INT_REG_OK_FOR_BASE_P ( op0 , reg_ok_strict ) && GET_CODE ( op1 ) == CONST_INT && ( ( INTVAL ( op1 ) >= - 0x2000 && INTVAL ( op1 ) <= 0x1fff ) || op0 == arg_pointer_rtx || op0 == frame_pointer_rtx || op0 == virtual_stack_vars_rtx ) && ( ! aligned || ( INTVAL ( op1 ) & 15 ) == 0 ) ) return TRUE ; if ( GET_CODE ( op0 ) == REG && INT_REG_OK_FOR_BASE_P ( op0 , reg_ok_strict ) && GET_CODE ( op1 ) == REG && INT_REG_OK_FOR_INDEX_P ( op1 , reg_ok_strict ) ) return TRUE ; } break ; default : break ; } return FALSE ; } </s>

Valid address are : - symbol_ref , label_ref , const - reg - reg + const_int , where const_int is 16 byte aligned - reg + reg , alignment does n't matter The alignment matters in the reg+const case because lqd and stqd ignore the 4 least significant bits of the const . We only care about 16 byte modes because the expand phase will change all smaller MEM references to TImode .