<s> bool runOnModule ( Module & M ) override { if ( skipModule ( M ) ) return false ; auto Changed = false ; auto NvvmMetadata = M . getNamedMetadata ( "nvvm.annotations" ) ; if ( ! NvvmMetadata ) return false ; for ( auto MetadataNode : NvvmMetadata -> operands ( ) ) { if ( MetadataNode -> getNumOperands ( ) != 3 ) continue ; const MDOperand & TypeOperand = MetadataNode -> getOperand ( 1 ) ; auto Type = dyn_cast < MDString > ( TypeOperand ) ; if ( ! Type ) continue ; if ( Type -> getString ( ) != "kernel" ) continue ; const MDOperand & FuncOperand = MetadataNode -> getOperand ( 0 ) ; if ( ! FuncOperand ) continue ; auto FuncConstant = dyn_cast < ConstantAsMetadata > ( FuncOperand ) ; if ( ! FuncConstant ) continue ; auto Func = dyn_cast < Function > ( FuncConstant -> getValue ( ) ) ; if ( ! Func ) continue ; auto NewFunc = this -> ProcessFunction ( M , Func ) ; if ( NewFunc ) { Changed = true ; MetadataNode -> replaceOperandWith ( 0 , llvm :: ConstantAsMetadata :: get ( NewFunc ) ) ; } } return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


"Not expecting modifiers with immediates"

This method commutes the operands of the given machine instruction MI .


"loadRegFromStackSlot didn't insert any code!"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s>
unsigned
SparcRegisterInfo
::
getRARegister
(
)
const
{
llvm_unreachable
(
"What is the return address register"
)
;
return
0
;
}
</s>

This method should return the register where the return address can be found .

Sparc
Sparc
"What is the return address register"
0


Function that may creates more instructions for large value on adjusting stack pointer . In nds32 target , 'addi ' can be used for stack pointer adjustment in prologue/epilogue stage . However , sometimes there are too many local variables so that the adjustment value is not able to be fit in the 'addi ' instruction . One solution is to move value into a register and then use 'add ' instruction . In practice , we use TA_REGNUM ( $ r15 ) to accomplish this purpose . Also , we need to return zero for sp adjustment so that proglogue/epilogue knows there is no need to create 'addi ' instruction .


<s> bool X86PassConfig :: addILPOpts ( ) { addPass ( & EarlyIfConverterID ) ; return true ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .


<s>
bool
PPCTargetLowering
::
isFPExtFree
(
EVT
DestVT
,
EVT
SrcVT
)
const
{
assert
(
DestVT
.
isFloatingPoint
(
)
&&
SrcVT
.
isFloatingPoint
(
)
&&
"invalid fpext types"
)
;
return
true
;
}
</s>

Return true if an fpext operation is free ( for instance , because single-precision floating-point numbers are implicitly extended to double-precision ) .


<s> void MCS51TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { SDLoc DL ( N ) ; switch ( N -> getOpcode ( ) ) { case ISD :: ADD : { if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) ) { SDValue Sub = DAG . getNode ( ISD :: SUB , DL , N -> getValueType ( 0 ) , N -> getOperand ( 0 ) , DAG . getConstant ( - C -> getAPIntValue ( ) , DL , C -> getValueType ( 0 ) ) ) ; Results . push_back ( Sub ) ; } break ; } default : { SDValue Res = LowerOperation ( SDValue ( N , 0 ) , DAG ) ; for ( unsigned I = 0 , E = Res -> getNumValues ( ) ; I != E ; ++ I ) Results . push_back ( Res . getValue ( I ) ) ; break ; } } } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s>
void
RISCVTTIImpl
::
getUnrollingPreferences
(
Loop
*
L
,
ScalarEvolution
&
SE
,
TTI
::
UnrollingPreferences
&
UP
,
OptimizationRemarkEmitter
*
ORE
)
{
bool
UseDefaultPreferences
=
true
;
if
(
ST
->
getTuneCPU
(
)
.
contains
(
"sifive-e76"
)
||
ST
->
getTuneCPU
(
)
.
contains
(
"sifive-s76"
)
||
ST
->
getTuneCPU
(
)
.
contains
(
"sifive-u74"
)
||
ST
->
getTuneCPU
(
)
.
contains
(
"sifive-7"
)
)
UseDefaultPreferences
=
false
;
if
(
UseDefaultPreferences
)
return
BasicTTIImplBase
::
getUnrollingPreferences
(
L
,
SE
,
UP
,
ORE
)
;
UP
.
UpperBound
=
true
;
UP
.
OptSizeThreshold
=
0
;
UP
.
PartialOptSizeThreshold
=
0
;
if
(
L
->
getHeader
(
)
->
getParent
(
)
->
hasOptSize
(
)
)
return
;
SmallVector
<
BasicBlock
*
,
4
>
ExitingBlocks
;
L
->
getExitingBlocks
(
ExitingBlocks
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Loop has:\n"
<<
"Blocks: "
<<
L
->
getNumBlocks
(
)
<<
"\n"
<<
"Exit blocks: "
<<
ExitingBlocks
.
size
(
)
<<
"\n"
)
;
if
(
ExitingBlocks
.
size
(
)
>
2
)
return
;
if
(
L
->
getNumBlocks
(
)
>
4
)
return
;
if
(
getBooleanLoopAttribute
(
L
,
"llvm.loop.isvectorized"
)
)
return
;
InstructionCost
Cost
=
0
;
for
(
auto
*
BB
:
L
->
getBlocks
(
)
)
{
for
(
auto
&
I
:
*
BB
)
{
if
(
I
.
getType
(
)
->
isVectorTy
(
)
)
return
;
if
(
isa
<
CallInst
>
(
I
)
||
isa
<
InvokeInst
>
(
I
)
)
{
if
(
const
Function
*
F
=
cast
<
CallBase
>
(
I
)
.
getCalledFunction
(
)
)
{
if
(
!
isLoweredToCall
(
F
)
)
continue
;
}
return
;
}
SmallVector
<
const
Value
*
>
Operands
(
I
.
operand_values
(
)
)
;
Cost
+=
getUserCost
(
&
I
,
Operands
,
TargetTransformInfo
::
TCK_SizeAndLatency
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Cost of loop: "
<<
Cost
<<
"\n"
)
;
UP
.
Partial
=
true
;
UP
.
Runtime
=
true
;
UP
.
UnrollRemainder
=
true
;
UP
.
UnrollAndJam
=
true
;
UP
.
UnrollAndJamInnerLoopThreshold
=
60
;
if
(
Cost
<
12
)
UP
.
Force
=
true
;
}
</s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> void ARMBaseInstrInfo :: buildOutlinedFrame ( MachineBasicBlock & MBB , MachineFunction & MF , const outliner :: OutlinedFunction & OF ) const { if ( OF . FrameConstructionID == MachineOutlinerThunk ) { MachineInstr * Call = & * -- MBB . instr_end ( ) ; bool isThumb = Subtarget . isThumb ( ) ; unsigned FuncOp = isThumb ? 2 : 0 ; unsigned Opc = Call -> getOperand ( FuncOp ) . isReg ( ) ? isThumb ? ARM :: tTAILJMPr : ARM :: TAILJMPr : isThumb ? Subtarget . isTargetMachO ( ) ? ARM :: tTAILJMPd : ARM :: tTAILJMPdND : ARM :: TAILJMPd ; MachineInstrBuilder MIB = BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Opc ) ) . add ( Call -> getOperand ( FuncOp ) ) ; if ( isThumb && ! Call -> getOperand ( FuncOp ) . isReg ( ) ) MIB . add ( predOps ( ARMCC :: AL ) ) ; Call -> eraseFromParent ( ) ; } auto IsNonTailCall = [ ] ( MachineInstr & MI ) { return MI . isCall ( ) && ! MI . isReturn ( ) ; } ; if ( std :: any_of ( MBB . instr_begin ( ) , MBB . instr_end ( ) , IsNonTailCall ) ) { MachineBasicBlock :: iterator It = MBB . begin ( ) ; MachineBasicBlock :: iterator Et = MBB . end ( ) ; if ( OF . FrameConstructionID == MachineOutlinerTailCall || OF . FrameConstructionID == MachineOutlinerThunk ) Et = std :: prev ( MBB . end ( ) ) ; if ( ! MBB . isLiveIn ( ARM :: LR ) ) MBB . addLiveIn ( ARM :: LR ) ; saveLROnStack ( MBB , It ) ; unsigned StackAlignment = Subtarget . getStackAlignment ( ) . value ( ) ; const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const MCRegisterInfo * MRI = STI . getRegisterInfo ( ) ; unsigned DwarfReg = MRI -> getDwarfRegNum ( ARM :: LR , true ) ; int64_t StackPosEntry = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , StackAlignment ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( ARM :: CFI_INSTRUCTION ) ) . addCFIIndex ( StackPosEntry ) . setMIFlags ( MachineInstr :: FrameSetup ) ; int64_t LRPosEntry = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DwarfReg , StackAlignment ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( ARM :: CFI_INSTRUCTION ) ) . addCFIIndex ( LRPosEntry ) . setMIFlags ( MachineInstr :: FrameSetup ) ; restoreLRFromStack ( MBB , Et ) ; } if ( OF . FrameConstructionID == MachineOutlinerTailCall || OF . FrameConstructionID == MachineOutlinerThunk ) return ; BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Subtarget . getReturnOpcode ( ) ) ) . add ( predOps ( ARMCC :: AL ) ) ; } </s>

Insert a custom frame for outlined functions .

ARM ARM 2 0 ARM::tTAILJMPr ARM::TAILJMPr ARM::tTAILJMPd ARM::tTAILJMPdND ARM::TAILJMPd ARMCC::AL ARM::LR ARM::LR ARM::LR ARM::CFI_INSTRUCTION ARM::CFI_INSTRUCTION ARMCC::AL


<s>
void
MipsCodeEmitter
::
emitInstruction
(
const
MachineInstr
&
MI
)
{
DEBUG
(
errs
(
)
<<
"JIT: "
<<
(
void
*
)
MCE
.
getCurrentPCValue
(
)
<<
":\t"
<<
MI
)
;
MCE
.
processDebugLoc
(
MI
.
getDebugLoc
(
)
,
true
)
;
if
(
(
MI
.
getDesc
(
)
.
TSFlags
&
MipsII
::
FormMask
)
==
MipsII
::
Pseudo
)
return
;
emitWordLE
(
getBinaryCodeForInstr
(
MI
)
)
;
++
NumEmitted
;
MCE
.
processDebugLoc
(
MI
.
getDebugLoc
(
)
,
false
)
;
}
</s>

Targets should implement this to emit instructions .

Mips
Mips
"JIT: "
":\t"
MipsII::FormMask
MipsII::Pseudo


<s> machine_mode epiphany_select_cc_mode ( enum rtx_code op , rtx x ATTRIBUTE_UNUSED , rtx y ATTRIBUTE_UNUSED ) { if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) { if ( TARGET_SOFT_CMPSF || op == ORDERED || op == UNORDERED ) { if ( op == EQ || op == NE ) return CC_FP_EQmode ; if ( op == ORDERED || op == UNORDERED ) return CC_FP_ORDmode ; if ( op == UNEQ || op == LTGT ) return CC_FP_UNEQmode ; return CC_FP_GTEmode ; } return CC_FPmode ; } else if ( ( op == EQ || op == NE ) && GET_CODE ( x ) == ZERO_EXTRACT && XEXP ( x , 1 ) == const1_rtx && CONST_INT_P ( XEXP ( x , 2 ) ) ) return CC_N_NEmode ; else if ( ( op == GEU || op == LTU ) && GET_CODE ( x ) == PLUS ) return CC_C_LTUmode ; else if ( ( op == LEU || op == GTU ) && GET_CODE ( x ) == MINUS ) return CC_C_GTUmode ; else return CCmode ; } </s>

Given a comparison code ( EQ , NE , etc . ) and the first operand of a COMPARE , return the mode to be used for the comparison .


<s> int SIInstrInfo :: pseudoToMCOpcode ( int Opcode ) const { SIEncodingFamily Gen = subtargetEncodingFamily ( ST ) ; if ( ( get ( Opcode ) . TSFlags & SIInstrFlags :: renamedInGFX9 ) != 0 && ST . getGeneration ( ) == AMDGPUSubtarget :: GFX9 ) Gen = SIEncodingFamily :: GFX9 ; if ( ST . hasUnpackedD16VMem ( ) && ( get ( Opcode ) . TSFlags & SIInstrFlags :: D16Buf ) ) Gen = SIEncodingFamily :: GFX80 ; if ( get ( Opcode ) . TSFlags & SIInstrFlags :: SDWA ) { switch ( ST . getGeneration ( ) ) { default : Gen = SIEncodingFamily :: SDWA ; break ; case AMDGPUSubtarget :: GFX9 : Gen = SIEncodingFamily :: SDWA9 ; break ; case AMDGPUSubtarget :: GFX10 : Gen = SIEncodingFamily :: SDWA10 ; break ; } } int MCOp = AMDGPU :: getMCOpcode ( Opcode , Gen ) ; if ( MCOp == - 1 ) return Opcode ; if ( MCOp == ( uint16_t ) - 1 ) return - 1 ; if ( isAsmOnlyOpcode ( MCOp ) ) return - 1 ; return MCOp ; } </s>

Return a target-specific opcode if Opcode is a pseudo instruction .


"unrecognized interrupt vector argument of %qE attribute"

"numeric argument of %qE attribute must be in range 0..63"

"argument of %qE attribute is not a string constant or number"

"%qE attribute only applies to functions"

"critical functions cannot be reentrant"

"reentrant functions cannot be critical"


<s> static void arm_init_bf16_types ( void ) { arm_bf16_type_node = make_node ( REAL_TYPE ) ; TYPE_PRECISION ( arm_bf16_type_node ) = 16 ; SET_TYPE_MODE ( arm_bf16_type_node , BFmode ) ; layout_type ( arm_bf16_type_node ) ; lang_hooks . types . register_builtin_type ( arm_bf16_type_node , "__bf16" ) ; arm_bf16_ptr_type_node = build_pointer_type ( arm_bf16_type_node ) ; } </s>

Initialize the backend REAL_TYPE type supporting bfloat types .


<s> void NodeAllocator :: clear ( ) { MemPool . Reset ( ) ; Blocks . clear ( ) ; ActiveEnd = nullptr ; } </s>


<s> static rtx ix86_expand_sse_cmp ( rtx dest , enum rtx_code code , rtx cmp_op0 , rtx cmp_op1 , rtx op_true , rtx op_false ) { machine_mode mode = GET_MODE ( dest ) ; machine_mode cmp_ops_mode = GET_MODE ( cmp_op0 ) ; machine_mode cmp_mode ; bool maskcmp = false ; rtx x ; if ( ix86_use_mask_cmp_p ( mode , cmp_ops_mode , op_true , op_false ) ) { unsigned int nbits = GET_MODE_NUNITS ( cmp_ops_mode ) ; maskcmp = true ; cmp_mode = nbits > 8 ? int_mode_for_size ( nbits , 0 ) . require ( ) : E_QImode ; } else cmp_mode = cmp_ops_mode ; cmp_op0 = force_reg ( cmp_ops_mode , cmp_op0 ) ; int ( * op1_predicate ) ( rtx , machine_mode ) = VECTOR_MODE_P ( cmp_ops_mode ) ? vector_operand : nonimmediate_operand ; if ( ! op1_predicate ( cmp_op1 , cmp_ops_mode ) ) cmp_op1 = force_reg ( cmp_ops_mode , cmp_op1 ) ; if ( optimize || ( maskcmp && cmp_mode != mode ) || ( op_true && reg_overlap_mentioned_p ( dest , op_true ) ) || ( op_false && reg_overlap_mentioned_p ( dest , op_false ) ) ) dest = gen_reg_rtx ( maskcmp ? cmp_mode : mode ) ; if ( maskcmp ) { bool ok = ix86_expand_mask_vec_cmp ( dest , code , cmp_op0 , cmp_op1 ) ; gcc_assert ( ok ) ; return dest ; } x = gen_rtx_fmt_ee ( code , cmp_mode , cmp_op0 , cmp_op1 ) ; if ( cmp_mode != mode ) { x = force_reg ( cmp_ops_mode , x ) ; convert_move ( dest , x , false ) ; } else emit_insn ( gen_rtx_SET ( dest , x ) ) ; return dest ; } </s>

Expand an sse vector comparison . Return the register with the result .


Returns a function decl for a vectorized version of the builtin function with builtin function code FN and the result vector type TYPE , or NULL_TREE if it is not available .


<s>
bool
AVRInstrInfo
::
isBranchOffsetInRange
(
unsigned
BranchOp
,
int64_t
BrOffset
)
const
{
switch
(
BranchOp
)
{
default
:
llvm_unreachable
(
"unexpected opcode!"
)
;
case
AVR
::
JMPk
:
case
AVR
::
CALLk
:
return
true
;
case
AVR
::
RCALLk
:
case
AVR
::
RJMPk
:
return
isIntN
(
13
,
BrOffset
)
;
case
AVR
::
BRBSsk
:
case
AVR
::
BRBCsk
:
case
AVR
::
BREQk
:
case
AVR
::
BRNEk
:
case
AVR
::
BRSHk
:
case
AVR
::
BRLOk
:
case
AVR
::
BRMIk
:
case
AVR
::
BRPLk
:
case
AVR
::
BRGEk
:
case
AVR
::
BRLTk
:
return
isIntN
(
7
,
BrOffset
)
;
}
}
</s>

Determine if the branch target is in range .

AVR
AVR
"unexpected opcode!"
AVR::JMPk
AVR::CALLk
AVR::RCALLk
AVR::RJMPk
13
AVR::BRBSsk
AVR::BRBCsk
AVR::BREQk
AVR::BRNEk
AVR::BRSHk
AVR::BRLOk
AVR::BRMIk
AVR::BRPLk
AVR::BRGEk
AVR::BRLTk
7


<s> const char * J2TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( J2ISD :: NodeType ) Opcode ) { case J2ISD :: FIRST_NUMBER : break ; case J2ISD :: X : \ return # X CASE ( Ret ) ; CASE ( Call ) ; CASE ( Wrapper ) ; CASE ( SHL ) ; CASE ( SRL ) ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> bool SIPeepholeSDWA :: runOnMachineFunction ( MachineFunction & MF ) { const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; if ( ! ST . hasSDWA ( ) || skipFunction ( * MF . getFunction ( ) ) ) return false ; MRI = & MF . getRegInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; TII = ST . getInstrInfo ( ) ; matchSDWAOperands ( MF ) ; for ( const auto & OperandPair : SDWAOperands ) { const auto & Operand = OperandPair . second ; MachineInstr * PotentialMI = Operand -> potentialToConvert ( TII ) ; if ( PotentialMI && isConvertibleToSDWA ( * PotentialMI , ST ) ) { PotentialMatches [ PotentialMI ] . push_back ( Operand . get ( ) ) ; } } for ( auto & PotentialPair : PotentialMatches ) { MachineInstr & PotentialMI = * PotentialPair . first ; convertToSDWA ( PotentialMI , PotentialPair . second ) ; } PotentialMatches . clear ( ) ; SDWAOperands . clear ( ) ; bool Ret = ! ConvertedInstructions . empty ( ) ; while ( ! ConvertedInstructions . empty ( ) ) legalizeScalarOperands ( * ConvertedInstructions . pop_back_val ( ) , ST ) ; return Ret ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool AVRRegisterInfo :: shouldCoalesce ( MachineInstr * MI , const TargetRegisterClass * SrcRC , unsigned SubReg , const TargetRegisterClass * DstRC , unsigned DstSubReg , const TargetRegisterClass * NewRC , LiveIntervals & LIS ) const { if ( this -> getRegClass ( AVR :: PTRDISPREGSRegClassID ) -> hasSubClassEq ( NewRC ) ) { return false ; } return TargetRegisterInfo :: shouldCoalesce ( MI , SrcRC , SubReg , DstRC , DstSubReg , NewRC , LIS ) ; } </s>


<s>
const
char
*
mcore_output_jump_label_table
(
)
{
int
i
;
if
(
pool_size
)
{
fprintf
(
asm_out_file
,
"\t.align 2\n"
)
;
for
(
i
=
0
;
i
<
pool_size
;
i
++
)
{
pool_node
*
p
=
pool_vector
+
i
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
"L"
,
CODE_LABEL_NUMBER
(
p
->
label
)
)
;
output_asm_insn
(
".long	%0"
,
&
p
->
value
)
;
}
pool_size
=
0
;
}
return
""
;
}
</s>

Dump out any constants accumulated in the final pass . These will only be labels .

mcore
"\t.align 2\n"
0
"L"
".long	%0"
0
""


<s> bool X86InstrInfo :: classifyLEAReg ( MachineInstr & MI , const MachineOperand & Src , unsigned Opc , bool AllowSP , unsigned & NewSrc , bool & isKill , bool & isUndef , MachineOperand & ImplicitOp ) const { MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const TargetRegisterClass * RC ; if ( AllowSP ) { RC = Opc != X86 :: LEA32r ? & X86 :: GR64RegClass : & X86 :: GR32RegClass ; } else { RC = Opc != X86 :: LEA32r ? & X86 :: GR64_NOSPRegClass : & X86 :: GR32_NOSPRegClass ; } unsigned SrcReg = Src . getReg ( ) ; if ( Opc != X86 :: LEA64_32r ) { NewSrc = SrcReg ; isKill = Src . isKill ( ) ; isUndef = Src . isUndef ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( NewSrc ) && ! MF . getRegInfo ( ) . constrainRegClass ( NewSrc , RC ) ) return false ; return true ; } if ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) ) { ImplicitOp = Src ; ImplicitOp . setImplicit ( ) ; NewSrc = getX86SubSuperRegister ( Src . getReg ( ) , 64 ) ; MachineBasicBlock :: LivenessQueryResult LQR = MI . getParent ( ) -> computeRegisterLiveness ( & getRegisterInfo ( ) , NewSrc , MI ) ; switch ( LQR ) { case MachineBasicBlock :: LQR_Unknown : return false ; case MachineBasicBlock :: LQR_Live : isKill = MI . killsRegister ( SrcReg ) ; isUndef = false ; break ; default : isKill = false ; isUndef = true ; break ; } } else { NewSrc = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( NewSrc , RegState :: Define | RegState :: Undef , X86 :: sub_32bit ) . addOperand ( Src ) ; isKill = true ; isUndef = false ; } return true ; } </s>

Given an operand within a MachineInstr , insert preceding code to put it into the right format for a particular kind of LEA instruction .


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == ARM :: GPRRegisterClass || RC == ARM :: tGPRRegisterClass ) { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , 0 , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2LDRi12 ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } ARMBaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> char * iq2000_output_conditional_branch ( rtx insn , rtx * operands , int two_operands_p , int float_p , int inverted_p , int length ) { static char buffer [ 200 ] ; enum rtx_code code = GET_CODE ( operands [ 0 ] ) ; int need_z_p ; const char * op1 = "%z2" ; const char * op2 = ( two_operands_p ? ",%z3" : ",%." ) ; const char * comp = ( float_p ? "%F0" : "%C0" ) ; const char * inverted_comp = ( float_p ? "%W0" : "%N0" ) ; iq2000_branch_likely = ( final_sequence && INSN_ANNULLED_BRANCH_P ( insn ) ) ; if ( ! two_operands_p ) { switch ( code ) { case GTU : code = NE ; break ; case LEU : code = EQ ; break ; case GEU : code = EQ ; op1 = "%." ; break ; case LTU : code = NE ; op1 = "%." ; break ; default : break ; } } need_z_p = ( ! float_p && code != EQ && code != NE ) ; if ( need_z_p ) op2 = "" ; buffer [ 0 ] = '\0' ; switch ( length ) { case 4 : case 8 : if ( float_p ) sprintf ( buffer , "b%s%%?\t%%Z2%%1" , inverted_p ? inverted_comp : comp ) ; else sprintf ( buffer , "b%s%s%%?\t%s%s,%%1" , inverted_p ? inverted_comp : comp , need_z_p ? "z" : "" , op1 , op2 ) ; return buffer ; case 12 : case 16 : { const char * target = ( ( iq2000_branch_likely || length == 16 ) ? ".+16" : ".+12" ) ; char * c ; c = strchr ( buffer , '\0' ) ; if ( float_p ) sprintf ( c , "b%s\t%%Z2%s" , inverted_p ? comp : inverted_comp , target ) ; else sprintf ( c , "b%s%s\t%s%s,%s" , inverted_p ? comp : inverted_comp , need_z_p ? "z" : "" , op1 , op2 , target ) ; strcat ( c , "\n\tnop\n\tj\t%1" ) ; if ( length == 16 ) strcat ( buffer , "\n\tnop" ) ; return buffer ; } default : gcc_unreachable ( ) ; } return 0 ; } </s>

Output assembly instructions to perform a conditional branch . INSN is the branch instruction . OPERANDS [ 0 ] is the condition . OPERANDS [ 1 ] is the target of the branch . OPERANDS [ 2 ] is the target of the first operand to the condition . If TWO_OPERANDS_P is nonzero the comparison takes two operands ; OPERANDS [ 3 ] will be the second operand . If INVERTED_P is nonzero we are to branch if the condition does not hold . If FLOAT_P is nonzero this is a floating-point comparison . LENGTH is the length ( in bytes ) of the sequence we are to generate . That tells us whether to generate a simple conditional branch , or a reversed conditional branch around a ` jr ' instruction .


<s> BitVector RISCVRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const RISCVFrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; for ( size_t Reg = 0 ; Reg < getNumRegs ( ) ; Reg ++ ) { if ( MF . getSubtarget < RISCVSubtarget > ( ) . isRegisterReservedByUser ( Reg ) ) markSuperRegs ( Reserved , Reg ) ; } markSuperRegs ( Reserved , RISCV :: X0 ) ; markSuperRegs ( Reserved , RISCV :: X2 ) ; markSuperRegs ( Reserved , RISCV :: X3 ) ; markSuperRegs ( Reserved , RISCV :: X4 ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , RISCV :: X8 ) ; if ( TFI -> hasBP ( MF ) ) markSuperRegs ( Reserved , RISCVABI :: getBPReg ( ) ) ; markSuperRegs ( Reserved , RISCV :: VL ) ; markSuperRegs ( Reserved , RISCV :: VTYPE ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> SDValue Z80oldTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; if ( N -> isMachineOpcode ( ) ) switch ( N -> getMachineOpcode ( ) ) { default : return SDValue ( ) ; case TargetOpcode :: EXTRACT_SUBREG : return combineExtractSubreg ( N , DCI . DAG , Subtarget ) ; } switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: MUL : return combineMul ( N , DCI . DAG , Subtarget ) ; case ISD :: AND : return combineAnd ( N , DCI . DAG ) ; case ISD :: ZERO_EXTEND : return combineZeroExtend ( N , DCI ) ; case ISD :: TRUNCATE : return combineTruncate ( N , DCI . DAG ) ; case Z80oldISD :: SUB : return combineSub ( N , DCI ) ; case Z80oldISD :: SEXT : return combineSExt ( N , DCI . DAG , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


"Operand must be a register when you're"

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> X86DCBasicBlock & getParent ( ) { return static_cast < X86DCBasicBlock & > ( DCInstruction :: getParent ( ) ) ; } </s>

getParent - Return the last analyzed interval .


<s>
ScheduleHazardRecognizer
*
PPCInstrInfo
::
CreateTargetPostRAHazardRecognizer
(
const
InstrItineraryData
*
II
,
const
ScheduleDAG
*
DAG
)
const
{
unsigned
Directive
=
DAG
->
MF
.
getSubtarget
<
PPCSubtarget
>
(
)
.
getCPUDirective
(
)
;
if
(
Directive
==
PPC
::
DIR_PWR7
||
Directive
==
PPC
::
DIR_PWR8
)
return
new
PPCDispatchGroupSBHazardRecognizer
(
II
,
DAG
)
;
if
(
Directive
!=
PPC
::
DIR_440
&&
Directive
!=
PPC
::
DIR_A2
&&
Directive
!=
PPC
::
DIR_E500mc
&&
Directive
!=
PPC
::
DIR_E5500
)
{
assert
(
DAG
->
TII
&&
"No InstrInfo?"
)
;
return
new
PPCHazardRecognizer970
(
*
DAG
)
;
}
return
new
ScoreboardHazardRecognizer
(
II
,
DAG
)
;
}
</s>

Allocate and return a hazard recognizer to use for by non-scheduling passes .


<s>
const
char
*
output_call
(
rtx
x
)
{
if
(
symbolic_operand
(
x
,
VOIDmode
)
)
return
m68k_symbolic_call
;
else
return
"jsr %a0"
;
}
</s>

INSN is either a function call or a millicode call . It may have an unconditional jump in its delay slot . CALL_DEST is the routine we are calling .


<s> unsigned PPCFrameLowering :: determineFrameLayout ( MachineFunction & MF , bool UpdateMF , bool UseEstimate ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = UseEstimate ? MFI -> estimateStackSize ( MF ) : MFI -> getStackSize ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - 1 ; const PPCRegisterInfo * RegInfo = static_cast < const PPCRegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; bool DisableRedZone = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoRedZone ) ; if ( ! DisableRedZone && ( Subtarget . isPPC64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == 0 ) && FrameSize <= 224 && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! RegInfo -> hasBasePointer ( MF ) ) { if ( UpdateMF ) MFI -> setStackSize ( 0 ) ; return 0 ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getMinCallFrameSize ( Subtarget . isPPC64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setStackSize ( FrameSize ) ; return FrameSize ; } </s>

Determine the frame layout but do not update the machine function .


<s> void msp430_expand_eh_return ( rtx eh_handler ) { rtx ap , sa , ra , tmp ; ap = arg_pointer_rtx ; sa = msp430_eh_return_stackadj_rtx ( ) ; ra = eh_handler ; tmp = ap ; tmp = gen_rtx_PLUS ( Pmode , ap , sa ) ; tmp = plus_constant ( Pmode , tmp , TARGET_LARGE ? - 4 : - 2 ) ; tmp = gen_rtx_MEM ( Pmode , tmp ) ; emit_move_insn ( tmp , ra ) ; } </s>

This function is called before reload , to `` fix '' the stack in preparation for an EH return .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


Emit unwind opcodes for .vsave directives .


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ReserveX18 ( AArch64 :: isX18ReservedByDefault ( TT ) ) , IsLittle ( LittleEndian ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS , CPU ) ) , TSInfo ( ) , TLInfo ( TM , * this ) { CallLoweringInfo . reset ( new AArch64CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new AArch64LegalizerInfo ( * this ) ) ; auto * RBI = new AArch64RegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( createAArch64InstructionSelector ( * static_cast < const AArch64TargetMachine * > ( & TM ) , * this , * RBI ) ) ; RegBankInfo . reset ( RBI ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> void X86PassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createExecutionDependencyFixPass ( & X86 :: VR128XRegClass ) ) ; if ( UseVZeroUpper ) addPass ( createX86IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86FixupBWInsts ( ) ) ; addPass ( createX86PadShortFunctions ( ) ) ; addPass ( createX86FixupLEAs ( ) ) ; } } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static rtx tilegx_function_value ( const_tree valtype , const_tree fn_decl_or_type , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode mode ; int unsigned_p ; mode = TYPE_MODE ( valtype ) ; unsigned_p = TYPE_UNSIGNED ( valtype ) ; mode = promote_function_mode ( valtype , mode , & unsigned_p , fn_decl_or_type , 1 ) ; return gen_rtx_REG ( mode , 0 ) ; } </s>


<s> static int arc600_corereg_hazard ( rtx_insn * pred , rtx_insn * succ ) { if ( ! TARGET_ARC600 ) return 0 ; if ( GET_CODE ( PATTERN ( pred ) ) == SEQUENCE ) pred = as_a < rtx_sequence * > ( PATTERN ( pred ) ) -> insn ( 1 ) ; if ( GET_CODE ( PATTERN ( succ ) ) == SEQUENCE ) succ = as_a < rtx_sequence * > ( PATTERN ( succ ) ) -> insn ( 0 ) ; if ( recog_memoized ( pred ) == CODE_FOR_mulsi_600 || recog_memoized ( pred ) == CODE_FOR_umul_600 || recog_memoized ( pred ) == CODE_FOR_mac_600 || recog_memoized ( pred ) == CODE_FOR_mul64_600 || recog_memoized ( pred ) == CODE_FOR_mac64_600 || recog_memoized ( pred ) == CODE_FOR_umul64_600 || recog_memoized ( pred ) == CODE_FOR_umac64_600 ) return 0 ; subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , PATTERN ( pred ) , NONCONST ) { const_rtx x = * iter ; switch ( GET_CODE ( x ) ) { case SET : case POST_INC : case POST_DEC : case PRE_INC : case PRE_DEC : break ; default : continue ; } rtx dest = XEXP ( x , 0 ) ; if ( REG_P ( dest ) && REGNO ( dest ) >= 32 && REGNO ( dest ) < 61 && ( refers_to_regno_p ( REGNO ( dest ) , REGNO ( dest ) + ( GET_MODE_SIZE ( GET_MODE ( dest ) ) + 3 ) / 4U , PATTERN ( succ ) , 0 ) ) ) return 4 ; } return 0 ; } </s>

Return length adjustment for INSN . For ARC600 : A write to a core reg greater or equal to 32 must not be immediately followed by a use . Anticipate the length requirement to insert a nop between PRED and SUCC to prevent a hazard .


<s> static bool aarch64_movw_imm ( HOST_WIDE_INT val , scalar_int_mode mode ) { if ( GET_MODE_SIZE ( mode ) > 4 ) { if ( ( val & ( ( ( HOST_WIDE_INT ) 0xffff ) << 32 ) ) == val || ( val & ( ( ( HOST_WIDE_INT ) 0xffff ) << 48 ) ) == val ) return 1 ; } else { val &= ( HOST_WIDE_INT ) 0xffffffff ; } return ( ( val & ( ( ( HOST_WIDE_INT ) 0xffff ) << 0 ) ) == val || ( val & ( ( ( HOST_WIDE_INT ) 0xffff ) << 16 ) ) == val ) ; } </s>

Return true if val is an immediate that can be loaded into a register by a MOVZ instruction .


"-mmul32x16 supported only for ARC600 or ARC601"

"-mno-dpfp-lrsr supported only with -mdpfp"

"FPX fast and compact options cannot be specified together"

"-mspfp_fast not available on ARC600 or ARC601"

"FPX extensions not available on pre-ARC600 cores"

"PIC is not supported for %s. Generating non-PIC code only.."

Called by OVERRIDE_OPTIONS to initialize various things .


<s> const char * MOSMCExpr :: getName ( ) const { const auto & Modifier = std :: find_if ( std :: begin ( ModifierNames ) , std :: end ( ModifierNames ) , [ this ] ( ModifierEntry const & Mod ) { return Mod . VariantKind == Kind ; } ) ; if ( Modifier != std :: end ( ModifierNames ) ) { return Modifier -> Spelling ; } return nullptr ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
void
AArch64TargetLowering
::
LowerAsmOperandForConstraint
(
SDValue
Op
,
std
::
string
&
Constraint
,
std
::
vector
<
SDValue
>
&
Ops
,
SelectionDAG
&
DAG
)
const
{
SDValue
Result
;
if
(
Constraint
.
size
(
)
!=
1
)
return
;
switch
(
Constraint
[
0
]
)
{
default
:
break
;
case
'I'
:
case
'J'
:
case
'K'
:
case
'L'
:
case
'M'
:
case
'N'
:
case
'Z'
:
{
ConstantSDNode
*
C
=
dyn_cast
<
ConstantSDNode
>
(
Op
)
;
if
(
!
C
)
return
;
uint64_t
CVal
=
C
->
getZExtValue
(
)
;
uint32_t
Bits
;
switch
(
Constraint
[
0
]
)
{
default
:
llvm_unreachable
(
"Unimplemented C_Other constraint"
)
;
case
'I'
:
if
(
CVal
<=
0xfff
)
break
;
return
;
case
'K'
:
if
(
A64Imms
::
isLogicalImm
(
32
,
CVal
,
Bits
)
)
break
;
return
;
case
'L'
:
if
(
A64Imms
::
isLogicalImm
(
64
,
CVal
,
Bits
)
)
break
;
return
;
case
'Z'
:
if
(
CVal
==
0
)
break
;
return
;
}
Result
=
DAG
.
getTargetConstant
(
CVal
,
Op
.
getValueType
(
)
)
;
break
;
}
case
'S'
:
{
if
(
const
GlobalAddressSDNode
*
GA
=
dyn_cast
<
GlobalAddressSDNode
>
(
Op
)
)
{
Result
=
DAG
.
getTargetGlobalAddress
(
GA
->
getGlobal
(
)
,
SDLoc
(
Op
)
,
GA
->
getValueType
(
0
)
)
;
}
else
if
(
const
BlockAddressSDNode
*
BA
=
dyn_cast
<
BlockAddressSDNode
>
(
Op
)
)
{
Result
=
DAG
.
getTargetBlockAddress
(
BA
->
getBlockAddress
(
)
,
BA
->
getValueType
(
0
)
)
;
}
else
if
(
const
ExternalSymbolSDNode
*
ES
=
dyn_cast
<
ExternalSymbolSDNode
>
(
Op
)
)
{
Result
=
DAG
.
getTargetExternalSymbol
(
ES
->
getSymbol
(
)
,
ES
->
getValueType
(
0
)
)
;
}
else
return
;
break
;
}
case
'Y'
:
if
(
const
ConstantFPSDNode
*
CFP
=
dyn_cast
<
ConstantFPSDNode
>
(
Op
)
)
{
if
(
CFP
->
isExactlyValue
(
0.0
)
)
{
Result
=
DAG
.
getTargetConstantFP
(
0.0
,
CFP
->
getValueType
(
0
)
)
;
break
;
}
}
return
;
}
if
(
Result
.
getNode
(
)
)
{
Ops
.
push_back
(
Result
)
;
return
;
}
TargetLowering
::
LowerAsmOperandForConstraint
(
Op
,
Constraint
,
Ops
,
DAG
)
;
}
</s>

Lower the specified operand into the Ops vector .


<s> rtx arc_rewrite_small_data ( rtx op ) { op = copy_insn ( op ) ; subrtx_ptr_iterator :: array_type array ; FOR_EACH_SUBRTX_PTR ( iter , array , & op , ALL ) { rtx * loc = * iter ; if ( arc_rewrite_small_data_p ( * loc ) ) { gcc_assert ( SDATA_BASE_REGNUM == PIC_OFFSET_TABLE_REGNUM ) ; * loc = gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , * loc ) ; if ( loc != & op ) { if ( GET_CODE ( op ) == MEM && & XEXP ( op , 0 ) == loc ) ; else if ( GET_CODE ( op ) == MEM && GET_CODE ( XEXP ( op , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( op , 0 ) , 0 ) ) == MULT ) * loc = force_reg ( Pmode , * loc ) ; else gcc_unreachable ( ) ; } iter . skip_subrtxes ( ) ; } else if ( GET_CODE ( * loc ) == PLUS && rtx_equal_p ( XEXP ( * loc , 0 ) , pic_offset_table_rtx ) ) iter . skip_subrtxes ( ) ; } return op ; } </s>

If possible , rewrite OP so that it refers to small data using explicit relocations .


"Functions with 'no-prototype' attribute must take varargs: "

"Functions with 'no-prototype' attribute should not have params: "

"could not derive a function prototype from usage: "

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s>
CCAssignFn
*
AArch64TargetLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
const
{
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention."
)
;
case
CallingConv
::
WebKit_JS
:
return
CC_AArch64_WebKit_JS
;
case
CallingConv
::
GHC
:
return
CC_AArch64_GHC
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
case
CallingConv
::
PreserveMost
:
case
CallingConv
::
CXX_FAST_TLS
:
case
CallingConv
::
Swift
:
if
(
Subtarget
->
isTargetWindows
(
)
&&
IsVarArg
)
return
CC_AArch64_Win64_VarArg
;
if
(
!
Subtarget
->
isTargetDarwin
(
)
)
return
CC_AArch64_AAPCS
;
return
IsVarArg
CC_AArch64_DarwinPCS_VarArg
:
CC_AArch64_DarwinPCS
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> static bool aarch64_pass_by_reference ( cumulative_args_t pcum ATTRIBUTE_UNUSED , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { HOST_WIDE_INT size ; machine_mode dummymode ; int nregs ; if ( mode == BLKmode && type ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) . to_constant ( ) ; if ( type && AGGREGATE_TYPE_P ( type ) ) { size = int_size_in_bytes ( type ) ; } if ( size < 0 ) return true ; if ( aarch64_vfp_is_call_or_return_candidate ( mode , type , & dummymode , & nregs , NULL ) ) return false ; return size > 2 * UNITS_PER_WORD ; } </s>


<s> static void setup_incoming_varargs_64 ( CUMULATIVE_ARGS * cum ) { rtx save_area , mem ; alias_set_type set ; int i , max ; if ( cfun -> va_list_gpr_size ) ix86_varargs_gpr_size = X86_64_REGPARM_MAX * UNITS_PER_WORD ; else ix86_varargs_gpr_size = 0 ; if ( TARGET_SSE && cfun -> va_list_fpr_size ) ix86_varargs_fpr_size = X86_64_SSE_REGPARM_MAX * 16 ; else ix86_varargs_fpr_size = 0 ; if ( ! ix86_varargs_gpr_size && ! ix86_varargs_fpr_size ) return ; save_area = frame_pointer_rtx ; set = get_varargs_alias_set ( ) ; max = cum -> regno + cfun -> va_list_gpr_size / UNITS_PER_WORD ; if ( max > X86_64_REGPARM_MAX ) max = X86_64_REGPARM_MAX ; for ( i = cum -> regno ; i < max ; i ++ ) { mem = gen_rtx_MEM ( word_mode , plus_constant ( Pmode , save_area , i * UNITS_PER_WORD ) ) ; MEM_NOTRAP_P ( mem ) = 1 ; set_mem_alias_set ( mem , set ) ; emit_move_insn ( mem , gen_rtx_REG ( word_mode , x86_64_int_parameter_registers [ i ] ) ) ; } if ( ix86_varargs_fpr_size ) { machine_mode smode ; rtx_code_label * label ; rtx test ; label = gen_label_rtx ( ) ; test = gen_rtx_EQ ( VOIDmode , gen_rtx_REG ( QImode , AX_REG ) , const0_rtx ) ; emit_jump_insn ( gen_cbranchqi4 ( test , XEXP ( test , 0 ) , XEXP ( test , 1 ) , label ) ) ; smode = V4SFmode ; if ( crtl -> stack_alignment_needed < GET_MODE_ALIGNMENT ( smode ) ) crtl -> stack_alignment_needed = GET_MODE_ALIGNMENT ( smode ) ; max = cum -> sse_regno + cfun -> va_list_fpr_size / 16 ; if ( max > X86_64_SSE_REGPARM_MAX ) max = X86_64_SSE_REGPARM_MAX ; for ( i = cum -> sse_regno ; i < max ; ++ i ) { mem = plus_constant ( Pmode , save_area , i * 16 + ix86_varargs_gpr_size ) ; mem = gen_rtx_MEM ( smode , mem ) ; MEM_NOTRAP_P ( mem ) = 1 ; set_mem_alias_set ( mem , set ) ; set_mem_align ( mem , GET_MODE_ALIGNMENT ( smode ) ) ; emit_move_insn ( mem , gen_rtx_REG ( smode , GET_SSE_REGNO ( i ) ) ) ; } emit_label ( label ) ; } } </s>

Worker function for TARGET_SETUP_INCOMING_VARARGS .


<s> static void h8300_file_start ( void ) { default_file_start ( ) ; if ( TARGET_H8300H ) fputs ( TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n" , asm_out_file ) ; else if ( TARGET_H8300SX ) fputs ( TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n" , asm_out_file ) ; else if ( TARGET_H8300S ) fputs ( TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n" , asm_out_file ) ; } </s>

Output assembly code for the start of the file .


<s> bool AMDGPUPassConfig :: addPreRegAlloc ( ) { addPass ( createAMDGPUConvertToISAPass ( * TM ) ) ; return false ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


"Warning: Illegal instruction detected: "

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
unsigned
MipsCodeEmitter
::
getMachineOpValue
(
const
MachineInstr
&
MI
,
const
MachineOperand
&
MO
)
const
{
if
(
MO
.
isReg
(
)
)
return
MipsRegisterInfo
::
getRegisterNumbering
(
MO
.
getReg
(
)
)
;
else
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
else
if
(
MO
.
isGlobal
(
)
)
emitGlobalAddress
(
MO
.
getGlobal
(
)
,
getRelocation
(
MI
,
MO
)
,
true
)
;
else
if
(
MO
.
isSymbol
(
)
)
emitExternalSymbolAddress
(
MO
.
getSymbolName
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isCPI
(
)
)
emitConstPoolAddress
(
MO
.
getIndex
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isJTI
(
)
)
emitJumpTableAddress
(
MO
.
getIndex
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isMBB
(
)
)
emitMachineBasicBlock
(
MO
.
getMBB
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
llvm_unreachable
(
"Unable to encode MachineOperand!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .

Mips
Mips
Mips
"Unable to encode MachineOperand!"
0


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> StringRef AArch64NamedImmMapper :: toString ( uint32_t Value , uint64_t FeatureBits , bool & Valid ) const { for ( unsigned i = 0 ; i < NumMappings ; ++ i ) { if ( Mappings [ i ] . isValueEqual ( Value , FeatureBits ) ) { Valid = true ; return Mappings [ i ] . Name ; } } Valid = false ; return StringRef ( ) ; } </s>

Convert to a decimal representation in a string .


<s> const unsigned * X86RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { bool callsEHReturn = false ; bool ghcCall = false ; if ( MF ) { callsEHReturn = MF -> getMMI ( ) . callsEHReturn ( ) ; const Function * F = MF -> getFunction ( ) ; ghcCall = ( F ? F -> getCallingConv ( ) == CallingConv :: GHC : false ) ; } if ( ghcCall ) return CSR_Ghc_SaveList ; if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_SaveList ; if ( callsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; } if ( callsEHReturn ) return CSR_32EHRet_SaveList ; return CSR_32_SaveList ; } </s>


<s>
const
char
*
avr_out_insert_notbit
(
rtx_insn
*
insn
,
rtx
operands
[
]
,
rtx
xbitno
,
int
*
plen
)
{
rtx
op
[
4
]
=
{
operands
[
0
]
,
operands
[
1
]
,
operands
[
2
]
,
xbitno
==
NULL_RTX
operands
[
3
]
:
xbitno
}
;
if
(
INTVAL
(
op
[
1
]
)
==
7
&&
test_hard_reg_class
(
LD_REGS
,
op
[
0
]
)
)
{
if
(
INTVAL
(
op
[
3
]
)
==
7
&&
REGNO
(
op
[
0
]
)
==
REGNO
(
op
[
2
]
)
)
{
avr_asm_len
(
"subi %0,0x80"
,
op
,
plen
,
1
)
;
}
else
{
avr_asm_len
(
"bst %2,%3"
CR_TAB
"bld %0,%1"
CR_TAB
"subi %0,0x80"
,
op
,
plen
,
3
)
;
}
}
else
if
(
test_hard_reg_class
(
LD_REGS
,
op
[
0
]
)
&&
(
INTVAL
(
op
[
1
]
)
!=
INTVAL
(
op
[
3
]
)
||
!
reg_overlap_mentioned_p
(
op
[
0
]
,
op
[
2
]
)
)
)
{
avr_asm_len
(
"andi %0,~(1<<%1)"
CR_TAB
"sbrs %2,%3"
CR_TAB
"ori %0,1<<%1"
,
op
,
plen
,
3
)
;
}
else
{
avr_asm_len
(
"com %2"
CR_TAB
"bst %2,%3"
,
op
,
plen
,
2
)
;
if
(
!
reg_unused_after
(
insn
,
op
[
2
]
)
||
reg_overlap_mentioned_p
(
op
[
0
]
,
op
[
2
]
)
)
{
avr_asm_len
(
"com %2"
,
op
,
plen
,
1
)
;
}
avr_asm_len
(
"bld %0,%1"
,
op
,
plen
,
1
)
;
}
return
""
;
}
</s>

Output instructions to insert an inverted bit into OPERANDS [ 0 ] : $ 0. $ 1 = ~ $ 2. $ 3 if XBITNO = NULL $ 0. $ 1 = ~ $ 2.XBITNO if XBITNO ! = NULL . If PLEN = NULL then output the respective instruction sequence which is a combination of BST / BLD and some instruction ( s ) to invert the bit . If PLEN ! = NULL then store the length of the sequence ( in words ) in * PLEN . Return `` '' .


<s>
SDValue
LC3bTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
dl
,
SelectionDAG
&
DAG
)
const
{
std
::
cout
<<
"Here it broke!!!!!\n"
;
return
Chain
;
}
</s>


Change register usage conditional on target flags .


<s>
static
void
bpf_output_destructor
(
rtx
symbol
,
int
priority
ATTRIBUTE_UNUSED
)
{
tree
decl
=
SYMBOL_REF_DECL
(
symbol
)
;
if
(
decl
)
sorry_at
(
DECL_SOURCE_LOCATION
(
decl
)
,
"no destructors"
)
;
else
sorry
(
"no destructors"
)
;
}
</s>

Output the assembly code for a destructor . Since eBPF does n't support indirect calls , destructors are not supported .


<s> static void aarch64_setup_incoming_varargs ( cumulative_args_t cum_v , machine_mode mode , tree type , int * pretend_size ATTRIBUTE_UNUSED , int no_rtl ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; CUMULATIVE_ARGS local_cum ; int gr_saved , vr_saved ; local_cum = * cum ; aarch64_function_arg_advance ( pack_cumulative_args ( & local_cum ) , mode , type , true ) ; gr_saved = NUM_ARG_REGS - local_cum . aapcs_ncrn ; vr_saved = NUM_FP_ARG_REGS - local_cum . aapcs_nvrn ; if ( ! TARGET_FLOAT ) { gcc_assert ( local_cum . aapcs_nvrn == 0 ) ; vr_saved = 0 ; } if ( ! no_rtl ) { if ( gr_saved > 0 ) { rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , - gr_saved * UNITS_PER_WORD ) ; mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . aapcs_ncrn + R0_REGNUM , mem , gr_saved ) ; } if ( vr_saved > 0 ) { machine_mode mode = TImode ; int off , i ; off = - ROUND_UP ( gr_saved * UNITS_PER_WORD , STACK_BOUNDARY / BITS_PER_UNIT ) ; off -= vr_saved * UNITS_PER_VREG ; for ( i = local_cum . aapcs_nvrn ; i < NUM_FP_ARG_REGS ; ++ i ) { rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , off ) ; mem = gen_frame_mem ( mode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; aarch64_emit_move ( mem , gen_rtx_REG ( mode , V0_REGNUM + i ) ) ; off += UNITS_PER_VREG ; } } } cfun -> machine -> frame . saved_varargs_size = ( ROUND_UP ( gr_saved * UNITS_PER_WORD , STACK_BOUNDARY / BITS_PER_UNIT ) + vr_saved * UNITS_PER_VREG ) ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"WebAssembly CallIndirect Fixup"
;
}
</s>

getPassName - Return a nice clean name for a pass .

WebAssembly
"WebAssembly CallIndirect Fixup"


<s> bool MipsAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == ".ent" ) { Parser . Lex ( ) ; return false ; } if ( IDVal == ".end" ) { Parser . Lex ( ) ; return false ; } if ( IDVal == ".frame" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".set" ) { return parseDirectiveSet ( ) ; } if ( IDVal == ".fmask" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".mask" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".gpword" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".word" ) { parseDirectiveWord ( 4 , DirectiveID . getLoc ( ) ) ; return false ; } return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool AArch64FrameLowering :: canUseAsPrologue ( const MachineBasicBlock & MBB ) const { const MachineFunction * MF = MBB . getParent ( ) ; const AArch64Subtarget & Subtarget = MF -> getSubtarget < AArch64Subtarget > ( ) ; const AArch64RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; return ! RegInfo -> needsStackRealignment ( * MF ) ; } </s>

Check whether or not the given MBB can be used as a prologue for the target .


<s> void VERegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const VEFrameLowering * TFI = getFrameLowering ( MF ) ; Register FrameReg ; int Offset ; Offset = TFI -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) ; Offset += MI . getOperand ( FIOperandNum + 2 ) . getImm ( ) ; replaceFI ( MF , II , MI , dl , FIOperandNum , Offset , FrameReg ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static unsigned int rs6000_xcoff_section_type_flags ( tree decl , const char * name , int reloc ) { unsigned int align ; unsigned int flags = default_section_type_flags_1 ( decl , name , reloc , 1 ) ; if ( flags & SECTION_CODE ) align = MIN_UNITS_PER_WORD ; else align = MAX ( ( DECL_ALIGN ( decl ) / BITS_PER_UNIT ) , int_size_in_bytes ( TREE_TYPE ( decl ) ) > MIN_UNITS_PER_WORD ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD ) ; return flags | ( exact_log2 ( align ) & SECTION_ENTSIZE ) ; } </s>

Section attributes . AIX is always PIC .


"attribute %<target%> argument not a string"

"malformed %<target()%> pragma or attribute"

"pragma or attribute %<target(\"%s\")%> is not valid"

"malformed %<target(\"%s\")%> pragma or attribute"

Parse the tree in ARGS that contains the target attribute information and update the global target options space . PRAGMA_OR_ATTR is a string to be used in error messages , specifying whether this is processing a target attribute or a target pragma .


<s> const char * RISCVTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { case RISCVISD :: NODE : \ return "RISCVISD::" # NODE ; switch ( ( RISCVISD :: NodeType ) Opcode ) { case RISCVISD :: FIRST_NUMBER : break ; NODE_NAME_CASE ( RET_FLAG ) NODE_NAME_CASE ( URET_FLAG ) NODE_NAME_CASE ( SRET_FLAG ) NODE_NAME_CASE ( MRET_FLAG ) NODE_NAME_CASE ( CALL ) NODE_NAME_CASE ( SELECT_CC ) NODE_NAME_CASE ( BuildPairF64 ) NODE_NAME_CASE ( SplitF64 ) NODE_NAME_CASE ( TAIL ) NODE_NAME_CASE ( SLLW ) NODE_NAME_CASE ( SRAW ) NODE_NAME_CASE ( SRLW ) NODE_NAME_CASE ( DIVW ) NODE_NAME_CASE ( DIVUW ) NODE_NAME_CASE ( REMUW ) NODE_NAME_CASE ( ROLW ) NODE_NAME_CASE ( RORW ) NODE_NAME_CASE ( FSLW ) NODE_NAME_CASE ( FSRW ) NODE_NAME_CASE ( FMV_H_X ) NODE_NAME_CASE ( FMV_X_ANYEXTH ) NODE_NAME_CASE ( FMV_W_X_RV64 ) NODE_NAME_CASE ( FMV_X_ANYEXTW_RV64 ) NODE_NAME_CASE ( READ_CYCLE_WIDE ) NODE_NAME_CASE ( GREVI ) NODE_NAME_CASE ( GREVIW ) NODE_NAME_CASE ( GORCI ) NODE_NAME_CASE ( GORCIW ) NODE_NAME_CASE ( VMV_X_S ) NODE_NAME_CASE ( SPLAT_VECTOR_I64 ) } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

RISCV RISCV RISCVISD::NODE "RISCVISD::" RISCVISD::NodeType RISCVISD::FIRST_NUMBER


<s> const ARCTargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


<s> bool Thumb2SizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { if ( PredicateFtor && ! PredicateFtor ( MF . getFunction ( ) ) ) return false ; STI = & static_cast < const ARMSubtarget & > ( MF . getSubtarget ( ) ) ; if ( STI -> isThumb1Only ( ) || STI -> prefers32BitThumb ( ) ) return false ; TII = static_cast < const Thumb2InstrInfo * > ( STI -> getInstrInfo ( ) ) ; OptimizeSize = MF . getFunction ( ) . hasOptSize ( ) ; MinimizeSize = STI -> hasMinSize ( ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; ReversePostOrderTraversal < MachineFunction * > RPOT ( & MF ) ; bool Modified = false ; for ( MachineBasicBlock * MBB : RPOT ) Modified |= ReduceMBB ( * MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> size_t HexagonAbsoluteStub :: size ( ) const { return m_Size ; } </s>

The number of name/type pairs is returned .


<s> void rs6000_cost_data :: update_target_cost_per_stmt ( vect_cost_for_stmt kind , stmt_vec_info stmt_info , vect_cost_model_location where , unsigned int orig_count ) { if ( kind == vec_to_scalar || kind == vec_perm || kind == vec_promote_demote || kind == vec_construct || kind == scalar_to_vec || ( where == vect_body && kind == vector_stmt ) ) m_vect_nonmem = true ; if ( ! m_costing_for_scalar && is_a < loop_vec_info > ( m_vinfo ) && where == vect_body ) { m_nstmts += orig_count ; if ( kind == scalar_load || kind == vector_load || kind == unaligned_load || kind == vector_gather_load ) m_nloads += orig_count ; if ( kind == vec_construct && stmt_info && STMT_VINFO_TYPE ( stmt_info ) == load_vec_info_type && ( STMT_VINFO_MEMORY_ACCESS_TYPE ( stmt_info ) == VMAT_ELEMENTWISE || STMT_VINFO_MEMORY_ACCESS_TYPE ( stmt_info ) == VMAT_STRIDED_SLP ) ) { tree vectype = STMT_VINFO_VECTYPE ( stmt_info ) ; unsigned int nunits = vect_nunits_for_cost ( vectype ) ; if ( nunits == 1 ) return ; unsigned int adjusted_cost = ( nunits == 2 ) ? 2 : 1 ; unsigned int extra_cost = nunits * adjusted_cost ; m_extra_ctor_cost += extra_cost ; } } } </s>

Helper function for add_stmt_cost . Check each statement cost entry , gather information and update the target_cost fields accordingly .


<s> BTFTypeFuncProto :: BTFTypeFuncProto ( const DISubroutineType * STy , uint32_t VLen , const std :: unordered_map < uint32_t , StringRef > & FuncArgNames ) : STy ( STy ) , FuncArgNames ( FuncArgNames ) { Kind = BTF :: BTF_KIND_FUNC_PROTO ; BTFType . Info = ( Kind << 24 ) | VLen ; } </s>

The Func kind represents both subprogram and pointee of function pointers .


<s> static void expand_block_set_1 ( rtx dst_reg , rtx value_rtx , rtx bytes_rtx ) { value_rtx = convert_to_mode ( Pmode , value_rtx , 1 ) ; emit_library_call ( byt_memset_libfunc , LCT_NORMAL , VOIDmode , dst_reg , Pmode , value_rtx , Pmode , convert_to_mode ( TYPE_MODE ( sizetype ) , bytes_rtx , TYPE_UNSIGNED ( sizetype ) ) , TYPE_MODE ( sizetype ) ) ; } </s>

Generate a call to a library function to set BYTES_RTX bytes at address DST_REG to VALUE_RTX in 1-byte chunks .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> void arc_eh_return_address_location ( rtx source ) { rtx mem ; int offset ; struct arc_frame_info * afi ; arc_compute_frame_size ( ) ; afi = & cfun -> machine -> frame_info ; gcc_assert ( crtl -> calls_eh_return ) ; gcc_assert ( afi -> save_return_addr ) ; gcc_assert ( afi -> extra_size >= 4 ) ; offset = afi -> reg_size + afi -> extra_size - 4 ; mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , hard_frame_pointer_rtx , offset ) ) ; MEM_VOLATILE_P ( mem ) = true ; emit_move_insn ( mem , source ) ; } </s>

Return rtx for the location of the return address on the stack , suitable for use in __builtin_eh_return . The new return address will be written to this location in order to redirect the return to the exception handler .


<s> int m32r_not_same_reg ( rtx a , rtx b ) { int reg_a = - 1 ; int reg_b = - 2 ; while ( GET_CODE ( a ) == SUBREG ) a = SUBREG_REG ( a ) ; if ( GET_CODE ( a ) == REG ) reg_a = REGNO ( a ) ; while ( GET_CODE ( b ) == SUBREG ) b = SUBREG_REG ( b ) ; if ( GET_CODE ( b ) == REG ) reg_b = REGNO ( b ) ; return reg_a != reg_b ; } </s>

Returns true if the registers contained in the two rtl expressions are different .


<s> TargetTransformInfo DirectXTargetMachine :: getTargetTransformInfo ( const Function & F ) const { return TargetTransformInfo ( DirectXTTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> bool AMDGPUTargetLowering :: isZExtFree ( SDValue Val , EVT VT2 ) const { return isZExtFree ( Val . getValueType ( ) , VT2 ) ; } </s>

Return true if zero-extending the specific node Val to type VT2 is free ( either because it 's implicitly zero-extended such as ARM ldrb / ldrh or because it 's folded such as X86 zero-extending loads ) .


<s>
SDValue
AArch64TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom lower this!"
)
;
case
ISD
::
FADD
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
ADD_F128
)
;
case
ISD
::
FSUB
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
SUB_F128
)
;
case
ISD
::
FMUL
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
MUL_F128
)
;
case
ISD
::
FDIV
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
DIV_F128
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
,
true
)
;
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
,
false
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
,
true
)
;
case
ISD
::
UINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
,
false
)
;
case
ISD
::
FP_ROUND
:
return
LowerFP_ROUND
(
Op
,
DAG
)
;
case
ISD
::
FP_EXTEND
:
return
LowerFP_EXTEND
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
SHL_PARTS
:
return
LowerShiftLeftParts
(
Op
,
DAG
)
;
case
ISD
::
SRL_PARTS
:
case
ISD
::
SRA_PARTS
:
return
LowerShiftRightParts
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
BRCOND
:
return
LowerBRCOND
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddressELF
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
LowerSELECT
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
case
ISD
::
VACOPY
:
return
LowerVACOPY
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
BUILD_VECTOR
:
return
LowerBUILD_VECTOR
(
Op
,
DAG
,
getSubtarget
(
)
)
;
case
ISD
::
CONCAT_VECTORS
:
return
LowerCONCAT_VECTORS
(
Op
,
DAG
)
;
case
ISD
::
VECTOR_SHUFFLE
:
return
LowerVECTOR_SHUFFLE
(
Op
,
DAG
)
;
}
return
SDValue
(
)
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> void XCoreInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) && ! I -> isDebugValue ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = * MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ; BuildMI ( MBB , I , DL , get ( XCore :: STWFI ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) . addMemOperand ( MMO ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s>
const
char
*
ashrsi3_out
(
rtx_insn
*
insn
,
rtx
operands
[
]
,
int
*
len
)
{
if
(
CONST_INT_P
(
operands
[
2
]
)
)
{
int
k
;
int
*
t
=
len
;
if
(
!
len
)
len
=
&
k
;
switch
(
INTVAL
(
operands
[
2
]
)
)
{
case
8
:
{
int
reg0
=
true_regnum
(
operands
[
0
]
)
;
int
reg1
=
true_regnum
(
operands
[
1
]
)
;
*
len
=
6
;
if
(
reg0
<=
reg1
)
return
(
"mov %A0,%B1"
CR_TAB
"mov %B0,%C1"
CR_TAB
"mov %C0,%D1"
CR_TAB
"clr %D0"
CR_TAB
"sbrc %C0,7"
CR_TAB
"dec %D0"
)
;
else
return
(
"clr %D0"
CR_TAB
"sbrc %D1,7"
CR_TAB
"dec %D0"
CR_TAB
"mov %C0,%D1"
CR_TAB
"mov %B0,%C1"
CR_TAB
"mov %A0,%B1"
)
;
}
case
16
:
{
int
reg0
=
true_regnum
(
operands
[
0
]
)
;
int
reg1
=
true_regnum
(
operands
[
1
]
)
;
if
(
reg0
==
reg1
+
2
)
return
*
len
=
4
,
(
"clr %D0"
CR_TAB
"sbrc %B0,7"
CR_TAB
"com %D0"
CR_TAB
"mov %C0,%D0"
)
;
if
(
AVR_HAVE_MOVW
)
return
*
len
=
5
,
(
"movw %A0,%C1"
CR_TAB
"clr %D0"
CR_TAB
"sbrc %B0,7"
CR_TAB
"com %D0"
CR_TAB
"mov %C0,%D0"
)
;
else
return
*
len
=
6
,
(
"mov %B0,%D1"
CR_TAB
"mov %A0,%C1"
CR_TAB
"clr %D0"
CR_TAB
"sbrc %B0,7"
CR_TAB
"com %D0"
CR_TAB
"mov %C0,%D0"
)
;
}
case
24
:
return
*
len
=
6
,
(
"mov %A0,%D1"
CR_TAB
"clr %D0"
CR_TAB
"sbrc %A0,7"
CR_TAB
"com %D0"
CR_TAB
"mov %B0,%D0"
CR_TAB
"mov %C0,%D0"
)
;
default
:
if
(
INTVAL
(
operands
[
2
]
)
<
32
)
break
;
case
31
:
if
(
AVR_HAVE_MOVW
)
return
*
len
=
4
,
(
"lsl %D0"
CR_TAB
"sbc %A0,%A0"
CR_TAB
"mov %B0,%A0"
CR_TAB
"movw %C0,%A0"
)
;
else
return
*
len
=
5
,
(
"lsl %D0"
CR_TAB
"sbc %A0,%A0"
CR_TAB
"mov %B0,%A0"
CR_TAB
"mov %C0,%A0"
CR_TAB
"mov %D0,%A0"
)
;
}
len
=
t
;
}
out_shift_with_cnt
(
"asr %D0"
CR_TAB
"ror %C0"
CR_TAB
"ror %B0"
CR_TAB
"ror %A0"
,
insn
,
operands
,
len
,
4
)
;
return
""
;
}
</s>

32bit arithmetic shift right ( ( signed long ) x > > i )


<s>
SDValue
XNCMTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
isVarArg
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .

XNCM
XNCM
ISD::InputArg
"Unsupported calling convention"


<s> bool ARMBaseRegisterInfo :: requiresVirtualBaseRegisters ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers used for more efficient stack access .


<s> bool isToken ( ) const override { return Kind == TOKEN ; } </s>


<s> bool Cpu0DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { bool Ret = SelectionDAGISel :: runOnMachineFunction ( MF ) ; return Ret ; } </s>


<s> BitVector R600RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const R600Subtarget & ST = MF . getSubtarget < R600Subtarget > ( ) ; const R600InstrInfo * TII = ST . getInstrInfo ( ) ; reserveRegisterTuples ( Reserved , AMDGPU :: ZERO ) ; reserveRegisterTuples ( Reserved , AMDGPU :: HALF ) ; reserveRegisterTuples ( Reserved , AMDGPU :: ONE ) ; reserveRegisterTuples ( Reserved , AMDGPU :: ONE_INT ) ; reserveRegisterTuples ( Reserved , AMDGPU :: NEG_HALF ) ; reserveRegisterTuples ( Reserved , AMDGPU :: NEG_ONE ) ; reserveRegisterTuples ( Reserved , AMDGPU :: PV_X ) ; reserveRegisterTuples ( Reserved , AMDGPU :: ALU_LITERAL_X ) ; reserveRegisterTuples ( Reserved , AMDGPU :: ALU_CONST ) ; reserveRegisterTuples ( Reserved , AMDGPU :: PREDICATE_BIT ) ; reserveRegisterTuples ( Reserved , AMDGPU :: PRED_SEL_OFF ) ; reserveRegisterTuples ( Reserved , AMDGPU :: PRED_SEL_ZERO ) ; reserveRegisterTuples ( Reserved , AMDGPU :: PRED_SEL_ONE ) ; reserveRegisterTuples ( Reserved , AMDGPU :: INDIRECT_BASE_ADDR ) ; for ( TargetRegisterClass :: iterator I = AMDGPU :: R600_AddrRegClass . begin ( ) , E = AMDGPU :: R600_AddrRegClass . end ( ) ; I != E ; ++ I ) { reserveRegisterTuples ( Reserved , * I ) ; } TII -> reserveIndirectRegisters ( Reserved , MF , * this ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> std :: vector < std :: pair < uint64_t , uint64_t >> findPltEntries ( uint64_t PltSectionVA , ArrayRef < uint8_t > PltContents , uint64_t GotPltSectionVA , const Triple & TargetTriple ) const override { std :: vector < std :: pair < uint64_t , uint64_t >> Result ; for ( uint64_t Byte = 0 , End = PltContents . size ( ) ; Byte + 7 < End ; Byte += 4 ) { uint32_t Insn = support :: endian :: read32le ( PltContents . data ( ) + Byte ) ; if ( ( Insn & 0x9f000000 ) != 0x90000000 ) continue ; uint64_t Imm = ( ( ( PltSectionVA + Byte ) >> 12 ) << 12 ) + ( ( ( Insn >> 29 ) & 3 ) << 12 ) + ( ( ( Insn >> 5 ) & 0x3ffff ) << 14 ) ; uint32_t Insn2 = support :: endian :: read32le ( PltContents . data ( ) + Byte + 4 ) ; if ( Insn2 >> 22 == 0x3e5 ) { Imm += ( ( Insn2 >> 10 ) & 0xfff ) << 3 ; Result . push_back ( std :: make_pair ( PltSectionVA + Byte , Imm ) ) ; Byte += 4 ; } } return Result ; } </s>

Returns ( PLT virtual address , GOT virtual address ) pairs for PLT entries .


<s> void X86InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC ) const { const MachineFunction & MF = * MBB . getParent ( ) ; bool isAligned = ( RI . getStackAlignment ( ) >= 16 ) || RI . needsStackRealignment ( MF ) ; unsigned Opc = getLoadRegOpcode ( RC , isAligned ) ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) , DestReg ) , FrameIdx ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> void JVMPassConfig :: addMachinePasses ( ) { addPass ( & PHIEliminationID , false ) ; addPass ( createJVMPreAllocationFixups ( ) ) ; addPass ( createJVMCopyElision ( ) ) ; addPreEmitPass ( ) ; } </s>

Add the complete , standard set of LLVM CodeGen passes .


<s> static rtx loongarch_got_load_tls_le ( rtx dest , rtx sym ) { return gen_got_load_tls_le ( Pmode , dest , sym ) ; } </s>

Add in the thread pointer for a TLS LE access .


<s> bool fp_one_operand ( rtx op ) { if ( GET_MODE ( op ) != SFmode ) return false ; return real_equal ( CONST_DOUBLE_REAL_VALUE ( op ) , & dconst1 ) ; } </s>

Nonzero if OP is a floating point value with value 1.0 .


<s> static int arc_save_callee_milli ( unsigned int gmask , bool save_blink , bool save_fp , HOST_WIDE_INT offset , HOST_WIDE_INT reg_size ) { int start_reg = 13 ; int end_reg = 25 ; int regno , indx , off , nregs ; rtx insn , reg , mem ; int frame_allocated = 0 ; for ( regno = start_reg ; regno <= end_reg && ( gmask & ( 1L << regno ) ) ; ) regno ++ ; end_reg = regno - 1 ; nregs = end_reg - start_reg + 1 ; gcc_assert ( end_reg > 14 ) ; if ( save_blink ) { reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; frame_allocated += frame_save_reg ( reg , offset ) ; offset = 0 ; } if ( reg_size || offset ) { frame_stack_add ( offset - reg_size ) ; frame_allocated += nregs * UNITS_PER_WORD - offset ; offset = 0 ; } insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nregs + 1 ) ) ; indx = 0 ; XVECEXP ( insn , 0 , nregs ) = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ) ; for ( regno = start_reg , indx = 0 , off = 0 ; regno <= end_reg ; regno ++ , indx ++ , off += UNITS_PER_WORD ) { reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , off ) ) ; XVECEXP ( insn , 0 , indx ) = gen_rtx_SET ( mem , reg ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , 0 , indx ) ) = 1 ; gmask = gmask & ~ ( 1L << regno ) ; } insn = frame_insn ( insn ) ; for ( regno = start_reg , off = 0 ; regno <= end_reg ; regno ++ , off += UNITS_PER_WORD ) { reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_rtx_MEM ( SImode , plus_constant ( Pmode , stack_pointer_rtx , off ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , gen_rtx_SET ( mem , reg ) ) ; } if ( arc_must_save_return_addr ( cfun ) ) { emit_insn ( gen_rtx_SET ( gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) , gen_rtx_MEM ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , reg_size ) ) ) ) ; } for ( regno = 0 ; regno <= 31 ; regno ++ ) { if ( ( gmask & ( 1L << regno ) ) == 0 ) continue ; reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , off ) ) ; frame_move_inc ( mem , reg , stack_pointer_rtx , 0 ) ; frame_allocated += UNITS_PER_WORD ; off += UNITS_PER_WORD ; } if ( save_fp ) frame_allocated += frame_save_reg ( hard_frame_pointer_rtx , offset ) ; if ( arc_frame_pointer_needed ( ) ) frame_move ( hard_frame_pointer_rtx , stack_pointer_rtx ) ; return frame_allocated ; } </s>

Millicode thunks implementation : Generates calls to millicodes for registers starting from r13 to r25 Present Limitations : - Only one range supported . The remaining regs will have the ordinary st and ld instructions for store and loads . Hence a gmask asking to store r13-14 , r16-r25 will only generate calls to store and load r13 to r14 while store and load insns will be generated for r16 to r25 in the prologue and epilogue respectively . - Presently library only supports register ranges starting from r13 .


"AMDGPU DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s>
const
char
*
avr_out_tstpsi
(
rtx_insn
*
insn
,
rtx
*
op
,
int
*
plen
)
{
if
(
compare_sign_p
(
insn
)
)
{
avr_asm_len
(
"tst %C0"
,
op
,
plen
,
1
)
;
}
else
if
(
reg_unused_after
(
insn
,
op
[
0
]
)
&&
compare_eq_p
(
insn
)
)
{
avr_asm_len
(
"or %A0,%B0"
CR_TAB
"or %A0,%C0"
,
op
,
plen
,
2
)
;
}
else
{
avr_out_compare
(
insn
,
op
,
plen
)
;
}
return
""
;
}
</s>


<s> void relaxInstruction ( MCInst & Inst , const MCSubtargetInfo & STI ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> bool AArch64InstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Cond , Register DstReg , Register TrueReg , Register FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( ! RI . getCommonSubClass ( RC , MRI . getRegClass ( DstReg ) ) ) return false ; unsigned ExtraCondLat = Cond . size ( ) != 1 ; if ( AArch64 :: GPR64allRegClass . hasSubClassEq ( RC ) || AArch64 :: GPR32allRegClass . hasSubClassEq ( RC ) ) { CondCycles = 1 + ExtraCondLat ; TrueCycles = FalseCycles = 1 ; if ( canFoldIntoCSel ( MRI , TrueReg ) ) TrueCycles = 0 ; else if ( canFoldIntoCSel ( MRI , FalseReg ) ) FalseCycles = 0 ; return true ; } if ( AArch64 :: FPR64RegClass . hasSubClassEq ( RC ) || AArch64 :: FPR32RegClass . hasSubClassEq ( RC ) ) { CondCycles = 5 + ExtraCondLat ; TrueCycles = FalseCycles = 2 ; return true ; } return false ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s>
const
MCPhysReg
*
X86RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"MachineFunction required"
)
;
const
X86Subtarget
&
Subtarget
=
MF
->
getSubtarget
<
X86Subtarget
>
(
)
;
const
Function
*
F
=
MF
->
getFunction
(
)
;
bool
HasSSE
=
Subtarget
.
hasSSE1
(
)
;
bool
HasAVX
=
Subtarget
.
hasAVX
(
)
;
bool
HasAVX512
=
Subtarget
.
hasAVX512
(
)
;
bool
CallsEHReturn
=
MF
->
callsEHReturn
(
)
;
CallingConv
::
ID
CC
=
F
->
getCallingConv
(
)
;
if
(
MF
->
getFunction
(
)
->
hasFnAttribute
(
"no_caller_saved_registers"
)
)
CC
=
CallingConv
::
X86_INTR
;
switch
(
CC
)
{
case
CallingConv
::
GHC
:
case
CallingConv
::
HiPE
:
return
CSR_NoRegs_SaveList
;
case
CallingConv
::
AnyReg
:
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
return
CSR_64_AllRegs_SaveList
;
case
CallingConv
::
PreserveMost
:
return
CSR_64_RT_MostRegs_SaveList
;
case
CallingConv
::
PreserveAll
:
if
(
HasAVX
)
return
CSR_64_RT_AllRegs_AVX_SaveList
;
return
CSR_64_RT_AllRegs_SaveList
;
case
CallingConv
::
CXX_FAST_TLS
:
if
(
Is64Bit
)
return
MF
->
getInfo
<
X86MachineFunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_64_CXX_TLS_Darwin_PE_SaveList
:
CSR_64_TLS_Darwin_SaveList
;
break
;
case
CallingConv
::
Intel_OCL_BI
:
{
if
(
HasAVX512
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX512
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX_SaveList
;
if
(
HasAVX
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX_SaveList
;
if
(
!
HasAVX
&&
!
IsWin64
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_SaveList
;
break
;
}
case
CallingConv
::
HHVM
:
return
CSR_64_HHVM_SaveList
;
case
CallingConv
::
X86_RegCall
:
if
(
Is64Bit
)
{
if
(
IsWin64
)
{
return
(
HasSSE
CSR_Win64_RegCall_SaveList
:
CSR_Win64_RegCall_NoSSE_SaveList
)
;
}
else
{
return
(
HasSSE
CSR_SysV64_RegCall_SaveList
:
CSR_SysV64_RegCall_NoSSE_SaveList
)
;
}
}
else
{
return
(
HasSSE
CSR_32_RegCall_SaveList
:
CSR_32_RegCall_NoSSE_SaveList
)
;
}
case
CallingConv
::
Cold
:
if
(
Is64Bit
)
return
CSR_64_MostRegs_SaveList
;
break
;
case
CallingConv
::
Win64
:
if
(
!
HasSSE
)
return
CSR_Win64_NoSSE_SaveList
;
return
CSR_Win64_SaveList
;
case
CallingConv
::
X86_64_SysV
:
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
case
CallingConv
::
X86_INTR
:
if
(
Is64Bit
)
{
if
(
HasAVX512
)
return
CSR_64_AllRegs_AVX512_SaveList
;
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
if
(
HasSSE
)
return
CSR_64_AllRegs_SaveList
;
return
CSR_64_AllRegs_NoSSE_SaveList
;
}
else
{
if
(
HasAVX512
)
return
CSR_32_AllRegs_AVX512_SaveList
;
if
(
HasAVX
)
return
CSR_32_AllRegs_AVX_SaveList
;
if
(
HasSSE
)
return
CSR_32_AllRegs_SSE_SaveList
;
return
CSR_32_AllRegs_SaveList
;
}
default
:
break
;
}
if
(
Is64Bit
)
{
bool
IsSwiftCC
=
Subtarget
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
F
->
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
;
if
(
IsSwiftCC
)
return
IsWin64
CSR_Win64_SwiftError_SaveList
:
CSR_64_SwiftError_SaveList
;
if
(
IsWin64
)
return
HasSSE
CSR_Win64_SaveList
:
CSR_Win64_NoSSE_SaveList
;
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
}
return
CallsEHReturn
CSR_32EHRet_SaveList
:
CSR_32_SaveList
;
}
</s>


<s> static void riscv_block_move_loop ( rtx dest , rtx src , unsigned HOST_WIDE_INT length , unsigned HOST_WIDE_INT bytes_per_iter ) { rtx label , src_reg , dest_reg , final_src , test ; unsigned HOST_WIDE_INT leftover ; leftover = length % bytes_per_iter ; length -= leftover ; riscv_adjust_block_mem ( src , bytes_per_iter , & src_reg , & src ) ; riscv_adjust_block_mem ( dest , bytes_per_iter , & dest_reg , & dest ) ; final_src = expand_simple_binop ( Pmode , PLUS , src_reg , GEN_INT ( length ) , 0 , 0 , OPTAB_WIDEN ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; riscv_block_move_straight ( dest , src , bytes_per_iter ) ; riscv_emit_move ( src_reg , plus_constant ( Pmode , src_reg , bytes_per_iter ) ) ; riscv_emit_move ( dest_reg , plus_constant ( Pmode , dest_reg , bytes_per_iter ) ) ; test = gen_rtx_NE ( VOIDmode , src_reg , final_src ) ; emit_jump_insn ( gen_cbranch4 ( Pmode , test , src_reg , final_src , label ) ) ; if ( leftover ) riscv_block_move_straight ( dest , src , leftover ) ; else emit_insn ( gen_nop ( ) ) ; } </s>

Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER bytes at a time . LENGTH must be at least BYTES_PER_ITER . Assume that the memory regions do not overlap .


<s> SDValue PPCTargetLowering :: LowerCall ( SDValue Chain , SDValue Callee , CallingConv :: ID CallConv , bool isVarArg , bool & isTailCall , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { if ( isTailCall ) isTailCall = IsEligibleForTailCallOptimization ( Callee , CallConv , isVarArg , Ins , DAG ) ; if ( PPCSubTarget . isSVR4ABI ( ) && ! PPCSubTarget . isPPC64 ( ) ) return LowerCall_SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; return LowerCall_Darwin ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; } </s>

This hook must be implemented to lower calls into the specified DAG .

PowerPC PPC ISD::OutputArg ISD::InputArg PPC PPC PPC


<s> const NyuziSubtarget * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) -> findAssociatedFragment ( ) ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s> unsigned internalKnownBits ( ) const { unsigned Bits = Unalign ? Unalign : KnownBits ; if ( Size & ( ( 1u << Bits ) - 1 ) ) Bits = countTrailingZeros ( Size ) ; return Bits ; } </s>

Compute the number of known offset bits internally to this block .


<s> bool X86InstrInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; bool is64Bit = TM . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ; unsigned SlotSize = is64Bit ? 8 : 4 ; MachineFunction & MF = * MBB . getParent ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; X86FI -> setCalleeSavedFrameSize ( CSI . size ( ) * SlotSize ) ; unsigned Opc = is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s>
bool
SystemZInstrInfo
::
PredicateInstruction
(
MachineInstr
&
MI
,
ArrayRef
<
MachineOperand
>
Pred
)
const
{
assert
(
Pred
.
size
(
)
==
2
&&
"Invalid condition"
)
;
unsigned
CCValid
=
Pred
[
0
]
.
getImm
(
)
;
unsigned
CCMask
=
Pred
[
1
]
.
getImm
(
)
;
assert
(
CCMask
>
0
&&
CCMask
<
15
&&
"Invalid predicate"
)
;
unsigned
Opcode
=
MI
.
getOpcode
(
)
;
if
(
Opcode
==
SystemZ
::
Trap
)
{
MI
.
setDesc
(
get
(
SystemZ
::
CondTrap
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
Return
||
Opcode
==
SystemZ
::
Return_XPLINK
)
{
MI
.
setDesc
(
get
(
Opcode
==
SystemZ
::
Return
SystemZ
::
CondReturn
:
SystemZ
::
CondReturn_XPLINK
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
CallJG
)
{
MachineOperand
FirstOp
=
MI
.
getOperand
(
0
)
;
const
uint32_t
*
RegMask
=
MI
.
getOperand
(
1
)
.
getRegMask
(
)
;
MI
.
removeOperand
(
1
)
;
MI
.
removeOperand
(
0
)
;
MI
.
setDesc
(
get
(
SystemZ
::
CallBRCL
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
add
(
FirstOp
)
.
addRegMask
(
RegMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
CallBR
)
{
MachineOperand
Target
=
MI
.
getOperand
(
0
)
;
const
uint32_t
*
RegMask
=
MI
.
getOperand
(
1
)
.
getRegMask
(
)
;
MI
.
removeOperand
(
1
)
;
MI
.
removeOperand
(
0
)
;
MI
.
setDesc
(
get
(
SystemZ
::
CallBCR
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
add
(
Target
)
.
addRegMask
(
RegMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
return
false
;
}
</s>

Convert the instruction into a predicated instruction .


<s> MachineBasicBlock :: iterator XCoreInstrInfo :: loadImmediate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned Reg , uint64_t Value ) const { DebugLoc dl ; if ( MI != MBB . end ( ) && ! MI -> isDebugValue ( ) ) dl = MI -> getDebugLoc ( ) ; if ( isImmMskBitp ( Value ) ) { int N = Log2_32 ( Value ) + 1 ; return BuildMI ( MBB , MI , dl , get ( XCore :: MKMSK_rus ) , Reg ) . addImm ( N ) . getInstr ( ) ; } if ( isImmU16 ( Value ) ) { int Opcode = isImmU6 ( Value ) ? XCore :: LDC_ru6 : XCore :: LDC_lru6 ; return BuildMI ( MBB , MI , dl , get ( Opcode ) , Reg ) . addImm ( Value ) . getInstr ( ) ; } MachineConstantPool * ConstantPool = MBB . getParent ( ) -> getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Value ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; return BuildMI ( MBB , MI , dl , get ( XCore :: LDWCP_lru6 ) , Reg ) . addConstantPoolIndex ( Idx ) . getInstr ( ) ; } </s>

Emit a series of instructions to load an immediate .


<s> void SITargetLowering :: AdjustInstrPostInstrSelection ( MachineInstr & MI , SDNode * Node ) const { const SIInstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; if ( TII -> isVOP3 ( MI . getOpcode ( ) ) ) { TII -> legalizeOperandsVOP3 ( MRI , MI ) ; if ( const MCOperandInfo * OpInfo = MI . getDesc ( ) . OpInfo ) { unsigned Opc = MI . getOpcode ( ) ; const SIRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; for ( auto I : { AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src0 ) , AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src1 ) } ) { if ( I == - 1 ) break ; MachineOperand & Op = MI . getOperand ( I ) ; if ( ( OpInfo [ I ] . RegClass != llvm :: AMDGPU :: AV_64RegClassID && OpInfo [ I ] . RegClass != llvm :: AMDGPU :: AV_32RegClassID ) || ! Register :: isVirtualRegister ( Op . getReg ( ) ) || ! TRI -> isAGPR ( MRI , Op . getReg ( ) ) ) continue ; auto * Src = MRI . getUniqueVRegDef ( Op . getReg ( ) ) ; if ( ! Src || ! Src -> isCopy ( ) || ! TRI -> isSGPRReg ( MRI , Src -> getOperand ( 1 ) . getReg ( ) ) ) continue ; auto * RC = TRI -> getRegClassForReg ( MRI , Op . getReg ( ) ) ; auto * NewRC = TRI -> getEquivalentVGPRClass ( RC ) ; MRI . setRegClass ( Op . getReg ( ) , NewRC ) ; } } return ; } int NoRetAtomicOp = AMDGPU :: getAtomicNoRetOp ( MI . getOpcode ( ) ) ; if ( NoRetAtomicOp != - 1 ) { if ( ! Node -> hasAnyUseOfValue ( 0 ) ) { MI . setDesc ( TII -> get ( NoRetAtomicOp ) ) ; MI . RemoveOperand ( 0 ) ; return ; } if ( ( Node -> hasNUsesOfValue ( 1 , 0 ) && Node -> use_begin ( ) -> isMachineOpcode ( ) && Node -> use_begin ( ) -> getMachineOpcode ( ) == AMDGPU :: EXTRACT_SUBREG && ! Node -> use_begin ( ) -> hasAnyUseOfValue ( 0 ) ) ) { Register Def = MI . getOperand ( 0 ) . getReg ( ) ; MI . setDesc ( TII -> get ( NoRetAtomicOp ) ) ; MI . RemoveOperand ( 0 ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , TII -> get ( AMDGPU :: IMPLICIT_DEF ) , Def ) ; } return ; } } </s>

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


<s>
DecodeStatus
AMDGPUDisassembler
::
getInstruction
(
MCInst
&
MI
,
uint64_t
&
Size
,
ArrayRef
<
uint8_t
>
Bytes_
,
uint64_t
Address
,
raw_ostream
&
WS
,
raw_ostream
&
CS
)
const
{
CommentStream
=
&
CS
;
assert
(
AMDGPU
::
isVI
(
STI
)
&&
"Can disassemble only VI ISA."
)
;
const
unsigned
MaxInstBytesNum
=
(
std
::
min
)
(
(
size_t
)
8
,
Bytes_
.
size
(
)
)
;
Bytes
=
Bytes_
.
slice
(
0
,
MaxInstBytesNum
)
;
DecodeStatus
Res
=
MCDisassembler
::
Fail
;
do
{
if
(
Bytes
.
size
(
)
>=
8
)
{
const
uint64_t
QW
=
eatBytes
<
uint64_t
>
(
Bytes
)
;
Res
=
tryDecodeInst
(
DecoderTableDPP64
,
MI
,
QW
,
Address
)
;
if
(
Res
)
break
;
Res
=
tryDecodeInst
(
DecoderTableSDWA64
,
MI
,
QW
,
Address
)
;
if
(
Res
)
break
;
}
Bytes
=
Bytes_
.
slice
(
0
,
MaxInstBytesNum
)
;
if
(
Bytes
.
size
(
)
<
4
)
break
;
const
uint32_t
DW
=
eatBytes
<
uint32_t
>
(
Bytes
)
;
Res
=
tryDecodeInst
(
DecoderTableVI32
,
MI
,
DW
,
Address
)
;
if
(
Res
)
break
;
Res
=
tryDecodeInst
(
DecoderTableAMDGPU32
,
MI
,
DW
,
Address
)
;
if
(
Res
)
break
;
if
(
Bytes
.
size
(
)
<
4
)
break
;
const
uint64_t
QW
=
(
(
uint64_t
)
eatBytes
<
uint32_t
>
(
Bytes
)
<<
32
)
|
DW
;
Res
=
tryDecodeInst
(
DecoderTableVI64
,
MI
,
QW
,
Address
)
;
if
(
Res
)
break
;
Res
=
tryDecodeInst
(
DecoderTableAMDGPU64
,
MI
,
QW
,
Address
)
;
}
while
(
false
)
;
Size
=
Res
(
MaxInstBytesNum
Bytes
.
size
(
)
)
:
0
;
return
Res
;
}
</s>

Returns the disassembly of a single instruction .


<s> void Cpu0InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { if ( ! printAliasInstr ( MI , O ) ) printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return createFISCELFObjectWriter ( OS , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static int getRegClass ( RegisterKind Is , unsigned RegWidth ) { if ( Is == IS_VGPR ) { switch ( RegWidth ) { default : return - 1 ; case 1 : return AMDGPU :: VGPR_32RegClassID ; case 2 : return AMDGPU :: VReg_64RegClassID ; case 3 : return AMDGPU :: VReg_96RegClassID ; case 4 : return AMDGPU :: VReg_128RegClassID ; case 5 : return AMDGPU :: VReg_160RegClassID ; case 8 : return AMDGPU :: VReg_256RegClassID ; case 16 : return AMDGPU :: VReg_512RegClassID ; case 32 : return AMDGPU :: VReg_1024RegClassID ; } } else if ( Is == IS_TTMP ) { switch ( RegWidth ) { default : return - 1 ; case 1 : return AMDGPU :: TTMP_32RegClassID ; case 2 : return AMDGPU :: TTMP_64RegClassID ; case 4 : return AMDGPU :: TTMP_128RegClassID ; case 8 : return AMDGPU :: TTMP_256RegClassID ; case 16 : return AMDGPU :: TTMP_512RegClassID ; } } else if ( Is == IS_SGPR ) { switch ( RegWidth ) { default : return - 1 ; case 1 : return AMDGPU :: SGPR_32RegClassID ; case 2 : return AMDGPU :: SGPR_64RegClassID ; case 4 : return AMDGPU :: SGPR_128RegClassID ; case 8 : return AMDGPU :: SGPR_256RegClassID ; case 16 : return AMDGPU :: SGPR_512RegClassID ; } } else if ( Is == IS_AGPR ) { switch ( RegWidth ) { default : return - 1 ; case 1 : return AMDGPU :: AGPR_32RegClassID ; case 2 : return AMDGPU :: AReg_64RegClassID ; case 4 : return AMDGPU :: AReg_128RegClassID ; case 16 : return AMDGPU :: AReg_512RegClassID ; case 32 : return AMDGPU :: AReg_1024RegClassID ; } } return - 1 ; } </s>

Given a machine instruction descriptor , returns the register class constraint for OpNum , or NULL .


<s>
bool
addRegAssignAndRewriteFast
(
)
override
{
llvm_unreachable
(
"should not be used"
)
;
}
</s>

Add core register allocator passes which do the actual register assignment and rewriting .


<s> bool constant_address_p ( rtx x ) { switch ( GET_CODE ( x ) ) { case LABEL_REF : case CONST_INT : case HIGH : return true ; case CONST : if ( flag_pic && pic_address_needs_scratch ( x ) ) return false ; return sparc_legitimate_constant_p ( Pmode , x ) ; case SYMBOL_REF : return ! flag_pic && sparc_legitimate_constant_p ( Pmode , x ) ; default : return false ; } } </s>

Determine if a given RTX is a valid constant address .


<s> static rtx_insn * m68k_emit_movem ( rtx base , HOST_WIDE_INT offset , unsigned int count , unsigned int regno , unsigned int mask , bool store_p , bool adjust_stack_p ) { int i ; rtx body , addr , src , operands [ 2 ] ; machine_mode mode ; body = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( adjust_stack_p + count ) ) ; mode = reg_raw_mode [ regno ] ; i = 0 ; if ( adjust_stack_p ) { src = plus_constant ( Pmode , base , ( count * GET_MODE_SIZE ( mode ) * ( HOST_WIDE_INT ) ( store_p ? - 1 : 1 ) ) ) ; XVECEXP ( body , 0 , i ++ ) = gen_rtx_SET ( VOIDmode , base , src ) ; } for ( ; mask != 0 ; mask >>= 1 , regno ++ ) if ( mask & 1 ) { addr = plus_constant ( Pmode , base , offset ) ; operands [ ! store_p ] = gen_frame_mem ( mode , addr ) ; operands [ store_p ] = gen_rtx_REG ( mode , regno ) ; XVECEXP ( body , 0 , i ++ ) = gen_rtx_SET ( VOIDmode , operands [ 0 ] , operands [ 1 ] ) ; offset += GET_MODE_SIZE ( mode ) ; } gcc_assert ( i == XVECLEN ( body , 0 ) ) ; return emit_insn ( body ) ; } </s>

Emit RTL for a MOVEM or FMOVEM instruction . BASE + OFFSET represents the lowest memory address . COUNT is the number of registers to be moved , with register REGNO + I being moved if bit I of MASK is set . STORE_P specifies the direction of the move and ADJUST_STACK_P says whether or not this is pre-decrement ( if STORE_P ) or post-increment ( if ! STORE_P ) operation .


<s> static bool cris_output_addr_const_extra ( FILE * file , rtx xconst ) { switch ( GET_CODE ( xconst ) ) { rtx x ; case UNSPEC : x = XVECEXP ( xconst , 0 , 0 ) ; CRIS_ASSERT ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF || GET_CODE ( x ) == CONST ) ; output_addr_const ( file , x ) ; switch ( XINT ( xconst , 1 ) ) { case CRIS_UNSPEC_PCREL : gcc_assert ( TARGET_V32 && flag_pic ) ; break ; case CRIS_UNSPEC_PLT_PCREL : gcc_assert ( TARGET_V32 ) ; fprintf ( file , ":PLT" ) ; break ; case CRIS_UNSPEC_PLT_GOTREL : gcc_assert ( ! TARGET_V32 ) ; fprintf ( file , ":PLTG" ) ; break ; case CRIS_UNSPEC_GOTREL : gcc_assert ( ! TARGET_V32 ) ; fprintf ( file , ":GOTOFF" ) ; break ; case CRIS_UNSPEC_GOTREAD : if ( flag_pic == 1 ) fprintf ( file , ":GOT16" ) ; else fprintf ( file , ":GOT" ) ; break ; case CRIS_UNSPEC_PLTGOTREAD : if ( flag_pic == 1 ) fprintf ( file , CRIS_GOTPLT_SUFFIX "16" ) ; else fprintf ( file , CRIS_GOTPLT_SUFFIX ) ; break ; default : gcc_unreachable ( ) ; } return true ; default : return false ; } } </s>

Worker function for OUTPUT_ADDR_CONST_EXTRA .


<s>
void
print
(
)
{
if
(
numSymbols
==
0
)
{
for
(
unsigned
i
=
0
;
i
<
size
;
i
++
)
{
if
(
i
)
O
<<
", "
;
O
<<
(
unsigned
int
)
buffer
[
i
]
;
}
}
else
{
unsigned
int
pos
=
0
;
unsigned
int
nSym
=
0
;
unsigned
int
nextSymbolPos
=
symbolPosInBuffer
[
nSym
]
;
unsigned
int
nBytes
=
4
;
if
(
AP
.
nvptxSubtarget
.
is64Bit
(
)
)
nBytes
=
8
;
for
(
pos
=
0
;
pos
<
size
;
pos
+=
nBytes
)
{
if
(
pos
)
O
<<
", "
;
if
(
pos
==
nextSymbolPos
)
{
const
Value
*
v
=
Symbols
[
nSym
]
;
if
(
const
GlobalValue
*
GVar
=
dyn_cast
<
GlobalValue
>
(
v
)
)
{
MCSymbol
*
Name
=
AP
.
getSymbol
(
GVar
)
;
PointerType
*
PTy
=
dyn_cast
<
PointerType
>
(
GVar
->
getType
(
)
)
;
bool
IsNonGenericPointer
=
false
;
if
(
PTy
&&
PTy
->
getAddressSpace
(
)
!=
0
)
{
IsNonGenericPointer
=
true
;
}
if
(
EmitGeneric
&&
!
isa
<
Function
>
(
v
)
&&
!
IsNonGenericPointer
)
{
O
<<
"generic("
;
O
<<
*
Name
;
O
<<
")"
;
}
else
{
O
<<
*
Name
;
}
}
else
if
(
const
ConstantExpr
*
Cexpr
=
dyn_cast
<
ConstantExpr
>
(
v
)
)
{
O
<<
*
nvptx
::
LowerConstant
(
Cexpr
,
AP
)
;
}
else
llvm_unreachable
(
"symbol type unknown"
)
;
nSym
++
;
if
(
nSym
>=
numSymbols
)
nextSymbolPos
=
size
+
1
;
else
nextSymbolPos
=
symbolPosInBuffer
[
nSym
]
;
}
else
if
(
nBytes
==
4
)
O
<<
*
(
unsigned
int
*
)
(
&
buffer
[
pos
]
)
;
else
O
<<
*
(
unsigned
long
long
*
)
(
&
buffer
[
pos
]
)
;
}
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> bool PPCExpandAtomicPseudo :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; TII = static_cast < const PPCInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = & TII -> getRegisterInfo ( ) ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { MachineBasicBlock & MBB = * I ; for ( MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , MBBE = MBB . end ( ) ; MBBI != MBBE ; ) { MachineInstr & MI = * MBBI ; MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; Changed |= expandMI ( MBB , MI , NMBBI ) ; MBBI = NMBBI ; } } if ( Changed ) MF . RenumberBlocks ( ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool NVPTXAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , O ) ; case 'r' : break ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> bool ARM64InstrInfo :: isCoalescableExtInstr ( const MachineInstr & MI , unsigned & SrcReg , unsigned & DstReg , unsigned & SubIdx ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case ARM64 :: SBFMXri : case ARM64 :: UBFMXri : if ( MI . getOperand ( 2 ) . getImm ( ) != 0 || MI . getOperand ( 3 ) . getImm ( ) != 31 ) return false ; SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; DstReg = MI . getOperand ( 0 ) . getReg ( ) ; SubIdx = ARM64 :: sub_32 ; return true ; } } </s>

isCoalescableExtInstr - Return true if the instruction is a `` coalescable '' extension instruction .


<s>
void
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
override
{
unsigned
Size
=
1
<<
getFixupKindLog2Size
(
Fixup
.
getKind
(
)
)
;
assert
(
Fixup
.
getOffset
(
)
+
Size
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
assert
(
isIntN
(
Size
*
8
+
1
,
Value
)
&&
"Value does not fit in the Fixup field"
)
;
for
(
unsigned
i
=
0
;
i
!=
Size
;
++
i
)
Data
[
Fixup
.
getOffset
(
)
+
i
]
=
uint8_t
(
Value
>>
(
(
Size
i
1
)
*
8
)
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> rtx function_expander :: use_widen_ternop_insn ( insn_code icode ) { int arg_offset = 0 ; if ( use_real_mask_p ( pred ) ) add_input_operand ( arg_offset ++ ) ; else add_all_one_mask_operand ( mask_mode ( ) ) ; for ( int argno = arg_offset ; argno < call_expr_nargs ( exp ) ; argno ++ ) add_input_operand ( argno ) ; add_input_operand ( Pmode , get_tail_policy_for_pred ( pred ) ) ; add_input_operand ( Pmode , get_mask_policy_for_pred ( pred ) ) ; add_input_operand ( Pmode , get_avl_type_rtx ( avl_type :: NONVLMAX ) ) ; return generate_insn ( icode ) ; } </s>

Implement the call using instruction ICODE , with a 1:1 mapping between arguments and input operands .


<s>
MachineBasicBlock
*
RISCVTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unexpected instr type to insert"
)
;
case
RISCV
::
Select_GPR_Using_CC_GPR
:
case
RISCV
::
Select_FPR32_Using_CC_GPR
:
case
RISCV
::
Select_FPR64_Using_CC_GPR
:
return
emitSelectPseudo
(
MI
,
BB
)
;
case
RISCV
::
BuildPairF64Pseudo
:
return
emitBuildPairF64Pseudo
(
MI
,
BB
)
;
case
RISCV
::
SplitF64Pseudo
:
return
emitSplitF64Pseudo
(
MI
,
BB
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static int rs6000_emit_p9_fp_minmax ( rtx dest , rtx op , rtx true_cond , rtx false_cond ) { enum rtx_code code = GET_CODE ( op ) ; rtx op0 = XEXP ( op , 0 ) ; rtx op1 = XEXP ( op , 1 ) ; machine_mode compare_mode = GET_MODE ( op0 ) ; machine_mode result_mode = GET_MODE ( dest ) ; bool max_p = false ; if ( result_mode != compare_mode ) return 0 ; if ( code == GE || code == GT ) max_p = true ; else if ( code == LE || code == LT ) max_p = false ; else return 0 ; if ( rtx_equal_p ( op0 , true_cond ) && rtx_equal_p ( op1 , false_cond ) ) ; else if ( rtx_equal_p ( op1 , true_cond ) && rtx_equal_p ( op0 , false_cond ) && ! HONOR_NANS ( compare_mode ) && ! HONOR_SIGNED_ZEROS ( compare_mode ) ) max_p = ! max_p ; else return 0 ; rs6000_emit_minmax ( dest , max_p ? SMAX : SMIN , op0 , op1 ) ; return 1 ; } </s>

ISA 3.0 ( power9 ) minmax subcase to emit a XSMAXCDP or XSMINCDP instruction for SF/DF scalars . Move TRUE_COND to DEST if OP of the operands of the last comparison is nonzero/true , FALSE_COND if it is zero/false . Return 0 if the hardware has no such operation .


<s>
StringRef
getPassName
(
)
const
override
{
return
"SI annotate control flow"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> FastISel * ARM :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) { const TargetMachine & TM = funcInfo . MF -> getTarget ( ) ; const ARMSubtarget & STI = static_cast < const ARMSubtarget & > ( funcInfo . MF -> getSubtarget ( ) ) ; bool UseFastISel = false ; UseFastISel |= STI . isTargetMachO ( ) && ! STI . isThumb1Only ( ) ; UseFastISel |= STI . isTargetLinux ( ) && ! STI . isThumb ( ) ; UseFastISel |= STI . isTargetNaCl ( ) && ! STI . isThumb ( ) ; if ( UseFastISel ) { TM . Options . NoFramePointerElim = true ; return new ARMFastISel ( funcInfo , libInfo ) ; } return nullptr ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> rtx spu_gen_exp2 ( machine_mode mode , rtx scale ) { gcc_assert ( mode == V4SFmode ) ; gcc_assert ( GET_MODE ( scale ) == SImode || GET_CODE ( scale ) == CONST_INT ) ; if ( GET_CODE ( scale ) != CONST_INT ) { rtx reg = force_reg ( SImode , scale ) ; rtx exp = gen_reg_rtx ( SImode ) ; rtx mul = gen_reg_rtx ( mode ) ; emit_insn ( gen_addsi3 ( exp , reg , GEN_INT ( 127 ) ) ) ; emit_insn ( gen_ashlsi3 ( exp , exp , GEN_INT ( 23 ) ) ) ; emit_insn ( gen_spu_splats ( mul , gen_rtx_SUBREG ( GET_MODE_INNER ( mode ) , exp , 0 ) ) ) ; return mul ; } else { HOST_WIDE_INT exp = 127 + INTVAL ( scale ) ; unsigned char arr [ 16 ] ; arr [ 0 ] = arr [ 4 ] = arr [ 8 ] = arr [ 12 ] = exp >> 1 ; arr [ 1 ] = arr [ 5 ] = arr [ 9 ] = arr [ 13 ] = exp << 7 ; arr [ 2 ] = arr [ 6 ] = arr [ 10 ] = arr [ 14 ] = 0 ; arr [ 3 ] = arr [ 7 ] = arr [ 11 ] = arr [ 15 ] = 0 ; return array_to_constant ( mode , arr ) ; } } </s>

Generate a constant or register which contains 2^SCALE . We assume the result is valid for MODE . Currently , MODE must be V4SFmode and SCALE must be SImode .


<s>
SDValue
AVRTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
auto
CCFunction
=
CCAssignFnForReturn
(
CallConv
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
CCFunction
)
;
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
unsigned
e
=
RVLocs
.
size
(
)
;
if
(
e
>
1
)
{
std
::
reverse
(
RVLocs
.
begin
(
)
,
RVLocs
.
end
(
)
)
;
}
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
if
(
MF
.
getFunction
(
)
->
getAttributes
(
)
.
hasAttribute
(
AttributeList
::
FunctionIndex
,
Attribute
::
Naked
)
)
{
return
Chain
;
}
unsigned
RetOpc
=
(
CallConv
==
CallingConv
::
AVR_INTR
||
CallConv
==
CallingConv
::
AVR_SIGNAL
)
AVRISD
::
RETI_FLAG
:
AVRISD
::
RET_FLAG
;
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
{
RetOps
.
push_back
(
Flag
)
;
}
return
DAG
.
getNode
(
RetOpc
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .