<s>
void
A57ChainingConstraint
::
apply
(
PBQPRAGraph
&
G
)
{
const
MachineFunction
&
MF
=
G
.
getMetadata
(
)
.
MF
;
LiveIntervals
&
LIs
=
G
.
getMetadata
(
)
.
LIS
;
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
LLVM_DEBUG
(
MF
.
dump
(
)
)
;
for
(
const
auto
&
MBB
:
MF
)
{
Chains
.
clear
(
)
;
for
(
const
auto
&
MI
:
MBB
)
{
for
(
auto
r
:
Chains
)
{
SmallVector
<
unsigned
,
8
>
toDel
;
if
(
regJustKilledBefore
(
LIs
,
r
,
MI
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Killing chain "
<<
printReg
(
r
,
TRI
)
<<
" at "
;
MI
.
print
(
dbgs
(
)
)
;
)
;
toDel
.
push_back
(
r
)
;
}
while
(
!
toDel
.
empty
(
)
)
{
Chains
.
remove
(
toDel
.
back
(
)
)
;
toDel
.
pop_back
(
)
;
}
}
switch
(
MI
.
getOpcode
(
)
)
{
case
AArch64
::
FMSUBSrrr
:
case
AArch64
::
FMADDSrrr
:
case
AArch64
::
FNMSUBSrrr
:
case
AArch64
::
FNMADDSrrr
:
case
AArch64
::
FMSUBDrrr
:
case
AArch64
::
FMADDDrrr
:
case
AArch64
::
FNMSUBDrrr
:
case
AArch64
::
FNMADDDrrr
:
{
unsigned
Rd
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
unsigned
Ra
=
MI
.
getOperand
(
3
)
.
getReg
(
)
;
if
(
addIntraChainConstraint
(
G
,
Rd
,
Ra
)
)
addInterChainConstraint
(
G
,
Rd
,
Ra
)
;
break
;
}
case
AArch64
::
FMLAv2f32
:
case
AArch64
::
FMLSv2f32
:
{
unsigned
Rd
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
addInterChainConstraint
(
G
,
Rd
,
Rd
)
;
break
;
}
default
:
break
;
}
}
}
}
</s>

Apply the profile inference algorithm for a given function .


<s> static rtx restore_fpr ( rtx base , int offset , int regnum ) { rtx addr ; addr = gen_rtx_MEM ( DFmode , plus_constant ( base , offset ) ) ; set_mem_alias_set ( addr , get_frame_alias_set ( ) ) ; return emit_move_insn ( gen_rtx_REG ( DFmode , regnum ) , addr ) ; } </s>

Emit insn to restore fpr REGNUM from offset OFFSET relative to register BASE . Return generated insn .


<s> SDValue SITargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( N ) ; EVT VT = N -> getValueType ( 0 ) ; switch ( N -> getOpcode ( ) ) { default : return AMDGPUTargetLowering :: PerformDAGCombine ( N , DCI ) ; case ISD :: SELECT_CC : { ConstantSDNode * True , * False ; if ( ( True = dyn_cast < ConstantSDNode > ( N -> getOperand ( 2 ) ) ) && ( False = dyn_cast < ConstantSDNode > ( N -> getOperand ( 3 ) ) ) && True -> isAllOnesValue ( ) && False -> isNullValue ( ) && VT == MVT :: i1 ) { return DAG . getNode ( ISD :: SETCC , DL , VT , N -> getOperand ( 0 ) , N -> getOperand ( 1 ) , N -> getOperand ( 4 ) ) ; } break ; } case ISD :: SETCC : { SDValue Arg0 = N -> getOperand ( 0 ) ; SDValue Arg1 = N -> getOperand ( 1 ) ; SDValue CC = N -> getOperand ( 2 ) ; ConstantSDNode * C = nullptr ; ISD :: CondCode CCOp = dyn_cast < CondCodeSDNode > ( CC ) -> get ( ) ; if ( VT == MVT :: i1 && Arg0 . getOpcode ( ) == ISD :: SIGN_EXTEND && Arg0 . getOperand ( 0 ) . getValueType ( ) == MVT :: i1 && ( C = dyn_cast < ConstantSDNode > ( Arg1 ) ) && C -> isNullValue ( ) && CCOp == ISD :: SETNE ) { return SimplifySetCC ( VT , Arg0 . getOperand ( 0 ) , DAG . getConstant ( 0 , MVT :: i1 ) , CCOp , true , DCI , DL ) ; } break ; } } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> MCRegister ARMElfTargetObjectFile :: getStaticBase ( ) const { return ARM :: R9 ; } </s>

Returns the register used as static base in RWPI variants .


<s> bool AArch64InstrInfo :: isCoalescableExtInstr ( const MachineInstr & MI , unsigned & SrcReg , unsigned & DstReg , unsigned & SubIdx ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case AArch64 :: SBFMXri : case AArch64 :: UBFMXri : if ( MI . getOperand ( 2 ) . getImm ( ) != 0 || MI . getOperand ( 3 ) . getImm ( ) != 31 ) return false ; SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; DstReg = MI . getOperand ( 0 ) . getReg ( ) ; SubIdx = AArch64 :: sub_32 ; return true ; } } </s>

isCoalescableExtInstr - Return true if the instruction is a `` coalescable '' extension instruction .


<s>
void
HexagonFrameLowering
::
processFunctionBeforeFrameFinalized
(
MachineFunction
&
MF
,
RegScavenger
*
RS
)
const
{
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
bool
HasAlloca
=
MFI
.
hasVarSizedObjects
(
)
;
bool
NeedsAlign
=
(
MFI
.
getMaxAlign
(
)
>
getStackAlign
(
)
)
;
if
(
!
HasAlloca
||
!
NeedsAlign
)
return
;
SmallSet
<
int
,
4
>
DealignSlots
;
unsigned
LFS
=
MFI
.
getLocalFrameSize
(
)
;
for
(
int
i
=
0
,
e
=
MFI
.
getObjectIndexEnd
(
)
;
i
!=
e
;
++
i
)
{
if
(
!
MFI
.
isSpillSlotObjectIndex
(
i
)
||
MFI
.
isDeadObjectIndex
(
i
)
)
continue
;
unsigned
S
=
MFI
.
getObjectSize
(
i
)
;
unsigned
A
=
std
::
max
(
MFI
.
getObjectAlignment
(
i
)
,
8U
)
;
MFI
.
setObjectAlignment
(
i
,
8
)
;
LFS
=
alignTo
(
LFS
+
S
,
A
)
;
MFI
.
mapLocalFrameObject
(
i
,
static_cast
<
int64_t
>
(
LFS
)
)
;
DealignSlots
.
insert
(
i
)
;
}
MFI
.
setLocalFrameSize
(
LFS
)
;
Align
A
=
MFI
.
getLocalFrameMaxAlign
(
)
;
assert
(
A
<=
8
&&
"Unexpected local frame alignment"
)
;
if
(
A
==
1
)
MFI
.
setLocalFrameMaxAlign
(
Align
(
8
)
)
;
MFI
.
setUseLocalStackAllocationBlock
(
true
)
;
if
(
!
DealignSlots
.
empty
(
)
)
{
for
(
MachineBasicBlock
&
BB
:
MF
)
{
for
(
MachineInstr
&
MI
:
BB
)
{
bool
KeepOld
=
true
;
ArrayRef
<
MachineMemOperand
*
>
memops
=
MI
.
memoperands
(
)
;
SmallVector
<
MachineMemOperand
*
,
1
>
new_memops
;
for
(
MachineMemOperand
*
MMO
:
memops
)
{
auto
*
PV
=
MMO
->
getPseudoValue
(
)
;
if
(
auto
*
FS
=
dyn_cast_or_null
<
FixedStackPseudoSourceValue
>
(
PV
)
)
{
int
FI
=
FS
->
getFrameIndex
(
)
;
if
(
DealignSlots
.
count
(
FI
)
)
{
unsigned
A
=
MFI
.
getObjectAlignment
(
FI
)
;
auto
*
NewMMO
=
MF
.
getMachineMemOperand
(
MMO
->
getPointerInfo
(
)
,
MMO
->
getFlags
(
)
,
MMO
->
getSize
(
)
,
A
,
MMO
->
getAAInfo
(
)
,
MMO
->
getRanges
(
)
,
MMO
->
getSyncScopeID
(
)
,
MMO
->
getOrdering
(
)
,
MMO
->
getFailureOrdering
(
)
)
;
new_memops
.
push_back
(
NewMMO
)
;
KeepOld
=
false
;
continue
;
}
}
new_memops
.
push_back
(
MMO
)
;
}
if
(
!
KeepOld
)
MI
.
setMemRefs
(
MF
,
new_memops
)
;
}
}
}
unsigned
AP
=
0
;
if
(
const
MachineInstr
*
AI
=
getAlignaInstr
(
MF
)
)
AP
=
AI
->
getOperand
(
0
)
.
getReg
(
)
;
auto
&
HMFI
=
*
MF
.
getInfo
<
HexagonMachineFunctionInfo
>
(
)
;
HMFI
.
setStackAlignBasePhysReg
(
AP
)
;
}
</s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> bool EvexToVexInstPass :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getSubtarget < X86Subtarget > ( ) . getInstrInfo ( ) ; const X86Subtarget & ST = MF . getSubtarget < X86Subtarget > ( ) ; if ( ! ST . hasAVX512 ( ) ) return false ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) Changed |= CompressEvexToVexImpl ( MI ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> DecodeStatus MOSDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CStream ) const { Size = 0 ; if ( Has65816 ) { if ( ( MLow || XLow ) && Bytes . size ( ) >= 3 ) { uint32_t Insn = 0 ; DecodeStatus Result = MCDisassembler :: Fail ; for ( size_t Byte : seq ( 0 , 3 ) ) { Insn |= Bytes [ Byte ] << ( 8 * Byte ) ; } if ( MLow ) { Result = decodeInstruction ( DecoderTableMOSMLow24 , Instr , Insn , Address , this , STI ) ; } if ( Result == MCDisassembler :: Fail && XLow ) { Result = decodeInstruction ( DecoderTableMOSXLow24 , Instr , Insn , Address , this , STI ) ; } if ( Result != MCDisassembler :: Fail ) { MCOperand & Op = Instr . getOperand ( 0 ) ; if ( ( uint64_t ) Op . getImm ( ) <= UCHAR_MAX ) { Op = MCOperand :: createExpr ( MOSMCExpr :: create ( MOSMCExpr :: VK_MOS_IMM16 , MCConstantExpr :: create ( Op . getImm ( ) , getContext ( ) ) , false , getContext ( ) ) ) ; } Size = 3 ; return Result ; } } } for ( size_t InsnSize : seq_inclusive ( 1 , 4 ) ) { uint32_t Insn = 0 ; DecodeStatus Result ; if ( Bytes . size ( ) < InsnSize ) { return MCDisassembler :: Fail ; } for ( size_t Byte : seq ( ( size_t ) 0 , InsnSize ) ) { Insn |= Bytes [ Byte ] << ( 8 * Byte ) ; } Result = decodeInstruction ( getDecoderTable ( InsnSize ) , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = InsnSize ; return Result ; } } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s> static unsigned int cris_hard_regno_nregs ( unsigned int , machine_mode mode ) { if ( mode == VOIDmode ) return 1 ; return CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ; } </s>

Implement TARGET_HARD_REGNO_NREGS . The VOIDmode test is so we can omit mode on anonymous insns . FIXME : Still needed in 2.9x , at least for Axis-20000319 .


<s> TargetLowering :: AtomicExpansionKind VETargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { if ( AI -> getOperation ( ) == AtomicRMWInst :: Xchg ) { return AtomicExpansionKind :: None ; } return AtomicExpansionKind :: CmpXChg ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> void ix86_emit_i387_cosh ( rtx op0 , rtx op1 ) { rtx e1 = gen_reg_rtx ( XFmode ) ; rtx e2 = gen_reg_rtx ( XFmode ) ; rtx half = const_double_from_real_value ( dconsthalf , XFmode ) ; rtx cst1 ; emit_insn ( gen_expxf2 ( e1 , op1 ) ) ; cst1 = force_reg ( XFmode , CONST1_RTX ( XFmode ) ) ; emit_insn ( gen_divxf3 ( e2 , cst1 , e1 ) ) ; emit_insn ( gen_addxf3 ( e2 , e1 , e2 ) ) ; half = force_reg ( XFmode , half ) ; emit_insn ( gen_mulxf3 ( op0 , e2 , half ) ) ; } </s>

Output code to perform an cosh XFmode calculation .


<s> static bool aarch64_movw_imm ( HOST_WIDE_INT val , machine_mode mode ) { if ( GET_MODE_SIZE ( mode ) > 4 ) { if ( ( val & ( ( ( HOST_WIDE_INT ) 0xffff ) << 32 ) ) == val || ( val & ( ( ( HOST_WIDE_INT ) 0xffff ) << 48 ) ) == val ) return 1 ; } else { val &= ( HOST_WIDE_INT ) 0xffffffff ; } return ( ( val & ( ( ( HOST_WIDE_INT ) 0xffff ) << 0 ) ) == val || ( val & ( ( ( HOST_WIDE_INT ) 0xffff ) << 16 ) ) == val ) ; } </s>

Return true if val is an immediate that can be loaded into a register by a MOVZ instruction .


"CG only instruction mustn't reach ASM printer"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static int scavenge_reg ( HARD_REG_SET * s ) { for ( int r = FIRST_GENERAL_REG ; r <= LAST_GENERAL_REG ; r ++ ) if ( TEST_HARD_REG_BIT ( * s , r ) ) return r ; return - 1 ; } </s>

Find the number of a general purpose register in S .


<s> BitVector SystemZRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; if ( hasFP ( MF ) ) Reserved . set ( SystemZ :: R11D ) ; Reserved . set ( SystemZ :: R14D ) ; Reserved . set ( SystemZ :: R15D ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> const TargetRegisterClass * getPointerRegClass ( const MachineFunction & MF , unsigned Kind = 0 ) const override { return & LoongArch :: GPRRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> static int ia64_speculate_insn ( rtx_insn * insn , ds_t ts , rtx * new_pat ) { int mode_no ; int res ; gcc_assert ( ! ( ts & ~ SPECULATIVE ) ) ; if ( ia64_spec_check_p ( insn ) ) return - 1 ; if ( ( ts & BE_IN_SPEC ) && ! insn_can_be_in_speculative_p ( insn , ts ) ) return - 1 ; mode_no = get_mode_no_for_insn ( insn ) ; if ( mode_no != SPEC_MODE_INVALID ) { if ( ia64_get_insn_spec_ds ( insn ) == ds_get_speculation_types ( ts ) ) res = 0 ; else { res = 1 ; * new_pat = ia64_gen_spec_load ( insn , ts , mode_no ) ; } } else res = - 1 ; return res ; } </s>

Implement targetm.sched.speculate_insn hook . Check if the INSN can be TS speculative . If 'no ' - return -1 . If 'yes ' - generate speculative pattern in the NEW_PAT and return 1 . If current pattern of the INSN already provides TS speculation , return 0 .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"MSP430 Branch Selector"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
static
void
const_double_split
(
rtx
x
,
HOST_WIDE_INT
*
p_high
,
HOST_WIDE_INT
*
p_low
)
{
if
(
GET_CODE
(
x
)
==
CONST_DOUBLE
)
{
long
t
[
2
]
;
REAL_VALUE_TYPE
rv
;
switch
(
GET_MODE
(
x
)
)
{
case
DFmode
:
REAL_VALUE_FROM_CONST_DOUBLE
(
rv
,
x
)
;
REAL_VALUE_TO_TARGET_DOUBLE
(
rv
,
t
)
;
*
p_high
=
t
[
1
]
;
*
p_low
=
t
[
0
]
;
return
;
case
SFmode
:
REAL_VALUE_FROM_CONST_DOUBLE
(
rv
,
x
)
;
REAL_VALUE_TO_TARGET_SINGLE
(
rv
,
*
p_high
)
;
*
p_low
=
0
;
return
;
case
VOIDmode
:
case
DImode
:
*
p_high
=
CONST_DOUBLE_HIGH
(
x
)
;
*
p_low
=
CONST_DOUBLE_LOW
(
x
)
;
return
;
default
:
break
;
}
}
fatal_insn
(
"const_double_split got a bad insn:"
,
x
)
;
}
</s>

Return the high and low words of a CONST_DOUBLE


<s> bool PIC16TargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createPIC16MemSelOptimizerPass ( ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool MSP430RegisterInfo :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> static void expand_set_cint32 ( rtx dest_reg , rtx src_val ) { HOST_WIDE_INT val ; int leading_zeroes , trailing_zeroes ; int lower , upper ; int three_wide_only ; rtx temp ; gcc_assert ( CONST_INT_P ( src_val ) ) ; val = trunc_int_for_mode ( INTVAL ( src_val ) , SImode ) ; if ( expand_set_cint32_one_inst ( dest_reg , val , false ) ) return ; temp = create_temp_reg_if_possible ( SImode , dest_reg ) ; leading_zeroes = 31 - floor_log2 ( val & 0xFFFFFFFF ) ; trailing_zeroes = exact_log2 ( val & - val ) ; lower = trunc_int_for_mode ( val , HImode ) ; upper = trunc_int_for_mode ( ( val - lower ) >> 16 , HImode ) ; for ( three_wide_only = 1 ; three_wide_only >= 0 ; three_wide_only -- ) { int count ; if ( expand_set_cint32_one_inst ( temp , val >> trailing_zeroes , three_wide_only ) ) { emit_move_insn ( dest_reg , gen_rtx_ASHIFT ( SImode , temp , GEN_INT ( trailing_zeroes ) ) ) ; return ; } if ( expand_set_cint32_one_inst ( temp , val << leading_zeroes , three_wide_only ) ) { emit_move_insn ( dest_reg , gen_rtx_LSHIFTRT ( SImode , temp , GEN_INT ( leading_zeroes ) ) ) ; return ; } for ( count = 1 ; count < 32 ; count ++ ) { HOST_WIDE_INT r = rotate_right ( val , count ) ; if ( expand_set_cint32_one_inst ( temp , r , three_wide_only ) ) { emit_move_insn ( dest_reg , gen_rtx_ROTATE ( SImode , temp , GEN_INT ( count ) ) ) ; return ; } } if ( lower == trunc_int_for_mode ( lower , QImode ) ) { break ; } } emit_move_insn ( temp , GEN_INT ( upper << 16 ) ) ; emit_move_insn ( dest_reg , ( gen_rtx_PLUS ( SImode , temp , GEN_INT ( lower ) ) ) ) ; } </s>

Create code to move the CONST_INT value in src_val to dest_reg .


<s> static bool ix86_vector_duplicate_value ( machine_mode mode , rtx target , rtx val ) { bool ok ; rtx_insn * insn ; rtx dup ; dup = gen_rtx_VEC_DUPLICATE ( mode , val ) ; insn = emit_insn ( gen_rtx_SET ( target , dup ) ) ; if ( recog_memoized ( insn ) < 0 ) { rtx_insn * seq ; machine_mode innermode = GET_MODE_INNER ( mode ) ; rtx reg ; start_sequence ( ) ; reg = force_reg ( innermode , val ) ; if ( GET_MODE ( reg ) != innermode ) reg = gen_lowpart ( innermode , reg ) ; XEXP ( dup , 0 ) = reg ; seq = get_insns ( ) ; end_sequence ( ) ; if ( seq ) emit_insn_before ( seq , insn ) ; ok = recog_memoized ( insn ) >= 0 ; gcc_assert ( ok ) ; } return true ; } </s>

A subroutine of ix86_expand_vector_init_duplicate . Tries to fill target with val via vec_duplicate .


<s> static bool loongarch_cannot_force_const_mem ( machine_mode mode , rtx x ) { enum loongarch_symbol_type type ; rtx base , offset ; if ( CONST_INT_P ( x ) && loongarch_legitimate_constant_p ( mode , x ) ) return true ; split_const ( x , & base , & offset ) ; if ( loongarch_symbolic_constant_p ( base , & type ) ) { if ( IMM12_INT ( offset ) && loongarch_symbol_insns ( type , MAX_MACHINE_MODE ) > 0 ) return true ; } if ( tls_referenced_p ( x ) ) return true ; return false ; } </s>


<s> bool SIRegisterInfo :: isConstantPhysReg ( MCRegister PhysReg ) const { switch ( PhysReg ) { case AMDGPU :: SGPR_NULL : case AMDGPU :: SRC_SHARED_BASE : case AMDGPU :: SRC_PRIVATE_BASE : case AMDGPU :: SRC_SHARED_LIMIT : case AMDGPU :: SRC_PRIVATE_LIMIT : return true ; default : return false ; } } </s>

Returns true if PhysReg is unallocatable and constant throughout the function .


<s> void X86InstrInfo :: buildOutlinedFrame ( MachineBasicBlock & MBB , MachineFunction & MF , const outliner :: OutlinedFunction & OF ) const { if ( OF . FrameConstructionID == MachineOutlinerTailCall ) return ; MachineInstr * retq = BuildMI ( MF , DebugLoc ( ) , get ( X86 :: RETQ ) ) ; MBB . insert ( MBB . end ( ) , retq ) ; } </s>

Insert a custom frame for outlined functions .


<s> const MCPhysReg * PPCRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: AnyReg ) { if ( Subtarget . hasVSX ( ) ) return CSR_64_AllRegs_VSX_SaveList ; if ( Subtarget . hasAltivec ( ) ) return CSR_64_AllRegs_Altivec_SaveList ; return CSR_64_AllRegs_SaveList ; } if ( Subtarget . isDarwinABI ( ) ) return Subtarget . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_SaveList : CSR_Darwin64_SaveList ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_SaveList : CSR_Darwin32_SaveList ) ; bool SaveR2 = MF -> getRegInfo ( ) . isAllocatable ( PPC :: X2 ) ; return Subtarget . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? ( SaveR2 ? CSR_SVR464_R2_Altivec_SaveList : CSR_SVR464_Altivec_SaveList ) : ( SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList ) ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR432_Altivec_SaveList : CSR_SVR432_SaveList ) ; } </s>


<s> bool rs6000_gimple_fold_builtin ( gimple_stmt_iterator * gsi ) { gimple * stmt = gsi_stmt ( * gsi ) ; tree fndecl = gimple_call_fndecl ( stmt ) ; gcc_checking_assert ( fndecl && DECL_BUILT_IN_CLASS ( fndecl ) == BUILT_IN_MD ) ; enum rs6000_builtins fn_code = ( enum rs6000_builtins ) DECL_FUNCTION_CODE ( fndecl ) ; tree arg0 , arg1 , lhs ; switch ( fn_code ) { case ALTIVEC_BUILTIN_VADDUBM : case ALTIVEC_BUILTIN_VADDUHM : case ALTIVEC_BUILTIN_VADDUWM : case P8V_BUILTIN_VADDUDM : case ALTIVEC_BUILTIN_VADDFP : case VSX_BUILTIN_XVADDDP : { arg0 = gimple_call_arg ( stmt , 0 ) ; arg1 = gimple_call_arg ( stmt , 1 ) ; lhs = gimple_call_lhs ( stmt ) ; gimple * g = gimple_build_assign ( lhs , PLUS_EXPR , arg0 , arg1 ) ; gimple_set_location ( g , gimple_location ( stmt ) ) ; gsi_replace ( gsi , g , true ) ; return true ; } case ALTIVEC_BUILTIN_VSUBUBM : case ALTIVEC_BUILTIN_VSUBUHM : case ALTIVEC_BUILTIN_VSUBUWM : case P8V_BUILTIN_VSUBUDM : case ALTIVEC_BUILTIN_VSUBFP : case VSX_BUILTIN_XVSUBDP : { arg0 = gimple_call_arg ( stmt , 0 ) ; arg1 = gimple_call_arg ( stmt , 1 ) ; lhs = gimple_call_lhs ( stmt ) ; gimple * g = gimple_build_assign ( lhs , MINUS_EXPR , arg0 , arg1 ) ; gimple_set_location ( g , gimple_location ( stmt ) ) ; gsi_replace ( gsi , g , true ) ; return true ; } case ALTIVEC_BUILTIN_VMULESB : case ALTIVEC_BUILTIN_VMULESH : case ALTIVEC_BUILTIN_VMULEUB : case ALTIVEC_BUILTIN_VMULEUH : { arg0 = gimple_call_arg ( stmt , 0 ) ; arg1 = gimple_call_arg ( stmt , 1 ) ; lhs = gimple_call_lhs ( stmt ) ; gimple * g = gimple_build_assign ( lhs , VEC_WIDEN_MULT_EVEN_EXPR , arg0 , arg1 ) ; gimple_set_location ( g , gimple_location ( stmt ) ) ; gsi_replace ( gsi , g , true ) ; return true ; } case ALTIVEC_BUILTIN_VMULOSB : case ALTIVEC_BUILTIN_VMULOSH : case ALTIVEC_BUILTIN_VMULOUB : case ALTIVEC_BUILTIN_VMULOUH : { arg0 = gimple_call_arg ( stmt , 0 ) ; arg1 = gimple_call_arg ( stmt , 1 ) ; lhs = gimple_call_lhs ( stmt ) ; gimple * g = gimple_build_assign ( lhs , VEC_WIDEN_MULT_ODD_EXPR , arg0 , arg1 ) ; gimple_set_location ( g , gimple_location ( stmt ) ) ; gsi_replace ( gsi , g , true ) ; return true ; } default : break ; } return false ; } </s>

Fold a machine-dependent built-in in GIMPLE . ( For folding into a constant , use rs6000_fold_builtin . )


<s> static bool isNot ( const MachineRegisterInfo & MRI , const MachineInstr & MI ) { if ( MI . getOpcode ( ) != TargetOpcode :: G_XOR ) return false ; auto ConstVal = getIConstantVRegSExtVal ( MI . getOperand ( 2 ) . getReg ( ) , MRI ) ; return ConstVal && * ConstVal == - 1 ; } </s>


<s> static rtx alpha_emit_set_long_const ( rtx target , HOST_WIDE_INT c1 ) { HOST_WIDE_INT d1 , d2 , d3 , d4 ; d1 = ( ( c1 & 0xffff ) ^ 0x8000 ) - 0x8000 ; c1 -= d1 ; d2 = ( ( c1 & 0xffffffff ) ^ 0x80000000 ) - 0x80000000 ; c1 = ( c1 - d2 ) >> 32 ; d3 = ( ( c1 & 0xffff ) ^ 0x8000 ) - 0x8000 ; c1 -= d3 ; d4 = ( ( c1 & 0xffffffff ) ^ 0x80000000 ) - 0x80000000 ; gcc_assert ( c1 == d4 ) ; if ( d4 ) { emit_move_insn ( target , GEN_INT ( d4 ) ) ; if ( d3 ) emit_move_insn ( target , gen_rtx_PLUS ( DImode , target , GEN_INT ( d3 ) ) ) ; } else emit_move_insn ( target , GEN_INT ( d3 ) ) ; emit_move_insn ( target , gen_rtx_ASHIFT ( DImode , target , GEN_INT ( 32 ) ) ) ; if ( d2 ) emit_move_insn ( target , gen_rtx_PLUS ( DImode , target , GEN_INT ( d2 ) ) ) ; if ( d1 ) emit_move_insn ( target , gen_rtx_PLUS ( DImode , target , GEN_INT ( d1 ) ) ) ; return target ; } </s>

Having failed to find a 3 insn sequence in alpha_emit_set_const , fall back to a straight forward decomposition . We do this to avoid exponential run times encountered when looking for longer sequences with alpha_emit_set_const .


<s> bool ARMPreAllocLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { if ( AssumeMisalignedLoadStores || skipFunction ( Fn . getFunction ( ) ) ) return false ; TD = & Fn . getDataLayout ( ) ; STI = & static_cast < const ARMSubtarget & > ( Fn . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; MF = & Fn ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; bool Modified = false ; for ( MachineBasicBlock & MFI : Fn ) Modified |= RescheduleLoadStoreInstrs ( & MFI ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> static void sparc_asm_function_epilogue ( FILE * file ) { rtx_insn * insn = get_last_insn ( ) ; rtx last_real_insn = prev_real_insn ( insn ) ; if ( last_real_insn && NONJUMP_INSN_P ( last_real_insn ) && GET_CODE ( PATTERN ( last_real_insn ) ) == SEQUENCE ) last_real_insn = XVECEXP ( PATTERN ( last_real_insn ) , 0 , 0 ) ; if ( last_real_insn && CALL_P ( last_real_insn ) && ! SIBLING_CALL_P ( last_real_insn ) ) fputs ( "\tnop\n" , file ) ; sparc_output_deferred_case_vectors ( ) ; } </s>

This function generates the assembly code for function exit .


<s> bool rs6000_is_valid_mask ( rtx mask , int * b , int * e , machine_mode mode ) { unsigned HOST_WIDE_INT val = INTVAL ( mask ) ; unsigned HOST_WIDE_INT bit ; int nb , ne ; int n = GET_MODE_PRECISION ( mode ) ; if ( mode != DImode && mode != SImode ) return false ; if ( INTVAL ( mask ) >= 0 ) { bit = val & - val ; ne = exact_log2 ( bit ) ; nb = exact_log2 ( val + bit ) ; } else if ( val + 1 == 0 ) { nb = n ; ne = 0 ; } else if ( val & 1 ) { val = ~ val ; bit = val & - val ; nb = exact_log2 ( bit ) ; ne = exact_log2 ( val + bit ) ; } else { bit = val & - val ; ne = exact_log2 ( bit ) ; if ( val + bit == 0 ) nb = n ; else nb = 0 ; } nb -- ; if ( nb < 0 || ne < 0 || nb >= n || ne >= n ) return false ; if ( b ) * b = nb ; if ( e ) * e = ne ; return true ; } </s>

Return whether MASK ( a CONST_INT ) is a valid mask for any rlwinm , rldicl , rldicr , or rldic instruction in mode MODE . If so , if E is not zero , store there the bit offset ( counted from the right ) where the single stretch of 1 bits begins ; and similarly for B , the bit offset where it ends .


<s> void initializePass ( ) override { pushTTIStack ( this ) ; } </s>

initializePass - This method may be overriden by immutable passes to allow them to perform various initialization actions they require .


<s> static rtx aarch64_strip_extend ( rtx x , bool strip_shift ) { scalar_int_mode mode ; rtx op = x ; if ( ! is_a < scalar_int_mode > ( GET_MODE ( op ) , & mode ) ) return op ; if ( GET_CODE ( op ) == AND && GET_CODE ( XEXP ( op , 0 ) ) == MULT && CONST_INT_P ( XEXP ( XEXP ( op , 0 ) , 1 ) ) && CONST_INT_P ( XEXP ( op , 1 ) ) && aarch64_uxt_size ( exact_log2 ( INTVAL ( XEXP ( XEXP ( op , 0 ) , 1 ) ) ) , INTVAL ( XEXP ( op , 1 ) ) ) != 0 ) return XEXP ( XEXP ( op , 0 ) , 0 ) ; if ( strip_shift && GET_CODE ( op ) == ASHIFT && CONST_INT_P ( XEXP ( op , 1 ) ) && ( ( unsigned HOST_WIDE_INT ) INTVAL ( XEXP ( op , 1 ) ) ) <= 4 ) op = XEXP ( op , 0 ) ; if ( GET_CODE ( op ) == ZERO_EXTEND || GET_CODE ( op ) == SIGN_EXTEND ) op = XEXP ( op , 0 ) ; if ( op != x ) return op ; return x ; } </s>

Helper function for rtx cost calculation . Strip an extend expression from X . Returns the inner operand if successful , or the original expression on failure . We deal with a number of possible canonicalization variations here .


<s> bool ARMFrameInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > 0 ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned PopOpc = AFI -> isThumbFunction ( ) ? ARM :: t2LDMIA_UPD : ARM :: LDMIA_UPD ; unsigned LdrOpc = AFI -> isThumbFunction ( ) ? ARM :: t2LDR_POST : ARM :: LDR_POST ; unsigned FltOpc = ARM :: VLDMDIA_UPD ; emitPopInst ( MBB , MI , CSI , FltOpc , 0 , isVarArg , true , & isARMArea3Register ) ; emitPopInst ( MBB , MI , CSI , PopOpc , LdrOpc , isVarArg , false , & isARMArea2Register ) ; emitPopInst ( MBB , MI , CSI , PopOpc , LdrOpc , isVarArg , false , & isARMArea1Register ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static inline ChildIteratorType child_begin ( NodeType * N ) { return N -> G -> Edges . lower_bound ( N ) ; } </s>

nodes_iterator/begin/end - Allow iteration over all nodes in the graph


<s> static void loongarch_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain_value ) { rtx addr , end_addr , mem ; rtx trampoline [ 8 ] ; unsigned int i , j ; HOST_WIDE_INT end_addr_offset , static_chain_offset , target_function_offset ; end_addr_offset = TRAMPOLINE_CODE_SIZE ; static_chain_offset = end_addr_offset ; target_function_offset = static_chain_offset + GET_MODE_SIZE ( ptr_mode ) ; addr = force_reg ( Pmode , XEXP ( m_tramp , 0 ) ) ; end_addr = loongarch_force_binary ( Pmode , PLUS , addr , GEN_INT ( end_addr_offset ) ) ; i = 0 ; trampoline [ i ++ ] = OP ( 0x18000000 | ( STATIC_CHAIN_REGNUM - GP_REG_FIRST ) ) ; trampoline [ i ++ ] = OP ( ( ptr_mode == DImode ? 0x28c00000 : 0x28800000 ) | 19 | ( ( STATIC_CHAIN_REGNUM - GP_REG_FIRST ) << 5 ) | ( ( target_function_offset & 0xfff ) << 10 ) ) ; trampoline [ i ++ ] = OP ( ( ptr_mode == DImode ? 0x28c00000 : 0x28800000 ) | ( STATIC_CHAIN_REGNUM - GP_REG_FIRST ) | ( ( STATIC_CHAIN_REGNUM - GP_REG_FIRST ) << 5 ) | ( ( static_chain_offset & 0xfff ) << 10 ) ) ; trampoline [ i ++ ] = OP ( 0x4c000000 | ( 19 << 5 ) ) ; for ( j = 0 ; j < i ; j ++ ) { mem = adjust_address ( m_tramp , SImode , j * GET_MODE_SIZE ( SImode ) ) ; loongarch_emit_move ( mem , trampoline [ j ] ) ; } mem = adjust_address ( m_tramp , ptr_mode , static_chain_offset ) ; loongarch_emit_move ( mem , chain_value ) ; mem = adjust_address ( m_tramp , ptr_mode , target_function_offset ) ; loongarch_emit_move ( mem , XEXP ( DECL_RTL ( fndecl ) , 0 ) ) ; emit_insn ( gen_add3_insn ( end_addr , addr , GEN_INT ( TRAMPOLINE_SIZE ) ) ) ; emit_insn ( gen_clear_cache ( addr , end_addr ) ) ; } </s>


<s> MVT MipsTargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( ! VT . isVector ( ) ) return getRegisterType ( Context , VT ) ; return Subtarget . isABI_O32 ( ) || VT . getSizeInBits ( ) == 32 ? MVT :: i32 : MVT :: i64 ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


<s>
const
char
*
getPassName
(
)
const
{
return
"SI Fix SGPR copies"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static void block_move_call ( rtx dest_reg , rtx src_reg , rtx bytes_rtx ) { if ( GET_MODE ( bytes_rtx ) != VOIDmode && GET_MODE ( bytes_rtx ) != Pmode ) bytes_rtx = convert_to_mode ( Pmode , bytes_rtx , 1 ) ; emit_library_call ( m32r_function_symbol ( "memcpy" ) , LCT_NORMAL , VOIDmode , 3 , dest_reg , Pmode , src_reg , Pmode , convert_to_mode ( TYPE_MODE ( sizetype ) , bytes_rtx , TYPE_UNSIGNED ( sizetype ) ) , TYPE_MODE ( sizetype ) ) ; } </s>

Use a library function to move some bytes .


<s> static void arm_option_params_internal ( void ) { if ( TARGET_THUMB1 ) { targetm . min_anchor_offset = 0 ; targetm . max_anchor_offset = 127 ; } else if ( TARGET_THUMB2 ) { targetm . min_anchor_offset = - 248 ; targetm . max_anchor_offset = 4095 ; } else { targetm . min_anchor_offset = TARGET_MIN_ANCHOR_OFFSET ; targetm . max_anchor_offset = TARGET_MAX_ANCHOR_OFFSET ; } max_insns_skipped = optimize_size ? 4 : current_tune -> max_insns_skipped ; if ( TARGET_THUMB2 ) max_insns_skipped = MIN ( max_insns_skipped , MAX_INSN_PER_IT_BLOCK ) ; if ( TARGET_THUMB1 ) targetm . md_asm_adjust = thumb1_md_asm_adjust ; else targetm . md_asm_adjust = arm_md_asm_adjust ; } </s>

Recompute the global settings depending on target attribute options .


<s> bool isToken ( ) const { return Kind == Token ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"Mips Assembly Printer"
;
}
</s>


<s>
void
HexagonHazardRecognizer
::
EmitInstruction
(
SUnit
*
SU
)
{
MachineInstr
*
MI
=
SU
->
getInstr
(
)
;
if
(
!
MI
)
return
;
for
(
const
MachineOperand
&
MO
:
MI
->
operands
(
)
)
if
(
MO
.
isReg
(
)
&&
MO
.
isDef
(
)
&&
!
MO
.
isImplicit
(
)
)
RegDefs
.
insert
(
MO
.
getReg
(
)
)
;
if
(
TII
->
isZeroCost
(
MI
->
getOpcode
(
)
)
)
return
;
if
(
!
Resources
->
canReserveResources
(
*
MI
)
)
{
assert
(
TII
->
mayBeNewStore
(
*
MI
)
&&
"Expecting .new store"
)
;
MachineFunction
*
MF
=
MI
->
getParent
(
)
->
getParent
(
)
;
MachineInstr
*
NewMI
=
MF
->
CreateMachineInstr
(
TII
->
get
(
TII
->
getDotNewOp
(
*
MI
)
)
,
MI
->
getDebugLoc
(
)
)
;
assert
(
Resources
->
canReserveResources
(
*
NewMI
)
)
;
Resources
->
reserveResources
(
*
NewMI
)
;
MF
->
deleteMachineInstr
(
NewMI
)
;
}
else
Resources
->
reserveResources
(
*
MI
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
" Add instruction "
<<
*
MI
)
;
if
(
TII
->
mayBeCurLoad
(
*
MI
)
)
for
(
auto
&
S
:
SU
->
Succs
)
if
(
S
.
isAssignedRegDep
(
)
&&
S
.
getLatency
(
)
==
0
&&
S
.
getSUnit
(
)
->
NumPredsLeft
==
1
)
{
UsesDotCur
=
S
.
getSUnit
(
)
;
DotCurPNum
=
PacketNum
;
break
;
}
if
(
SU
==
UsesDotCur
)
{
UsesDotCur
=
nullptr
;
DotCurPNum
=
1
;
}
UsesLoad
=
MI
->
mayLoad
(
)
;
if
(
TII
->
isHVXVec
(
*
MI
)
&&
!
MI
->
mayLoad
(
)
&&
!
MI
->
mayStore
(
)
)
for
(
auto
&
S
:
SU
->
Succs
)
if
(
S
.
isAssignedRegDep
(
)
&&
S
.
getLatency
(
)
==
0
&&
TII
->
mayBeNewStore
(
*
S
.
getSUnit
(
)
->
getInstr
(
)
)
&&
Resources
->
canReserveResources
(
*
S
.
getSUnit
(
)
->
getInstr
(
)
)
)
{
PrefVectorStoreNew
=
S
.
getSUnit
(
)
;
break
;
}
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> std :: pair < uint16_t , uint16_t > ARMBaseInstrInfo :: getExecutionDomain ( const MachineInstr * MI ) const { if ( MI -> getOpcode ( ) == ARM :: VMOVD && ! isPredicated ( MI ) ) return std :: make_pair ( ExeVFP , ( 1 << ExeVFP ) | ( 1 << ExeNEON ) ) ; if ( Subtarget . isCortexA9 ( ) && ! isPredicated ( MI ) && ( MI -> getOpcode ( ) == ARM :: VMOVRS || MI -> getOpcode ( ) == ARM :: VMOVSR || MI -> getOpcode ( ) == ARM :: VMOVS ) ) return std :: make_pair ( ExeVFP , ( 1 << ExeVFP ) | ( 1 << ExeNEON ) ) ; unsigned Domain = MI -> getDesc ( ) . TSFlags & ARMII :: DomainMask ; if ( Domain & ARMII :: DomainNEON ) return std :: make_pair ( ExeNEON , 0 ) ; if ( ( Domain & ARMII :: DomainNEONA8 ) && Subtarget . isCortexA8 ( ) ) return std :: make_pair ( ExeNEON , 0 ) ; if ( Domain & ARMII :: DomainVFP ) return std :: make_pair ( ExeVFP , 0 ) ; return std :: make_pair ( ExeGeneric , 0 ) ; } </s>

Return the current execution domain and bit mask of possible domains for instruction .


<s> static X86Operand * CreateReg ( unsigned RegNo , SMLoc StartLoc , SMLoc EndLoc , bool AddressOf = false , SMLoc OffsetOfLoc = SMLoc ( ) , StringRef SymName = StringRef ( ) , void * OpDecl = 0 ) { X86Operand * Res = new X86Operand ( Register , StartLoc , EndLoc ) ; Res -> Reg . RegNo = RegNo ; Res -> AddressOf = AddressOf ; Res -> OffsetOfLoc = OffsetOfLoc ; Res -> SymName = SymName ; Res -> OpDecl = OpDecl ; return Res ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> bool RISCVTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , Align Alignment , MachineMemOperand :: Flags Flags , bool * Fast ) const { if ( ! VT . isVector ( ) ) { if ( Fast ) * Fast = false ; return Subtarget . enableUnalignedScalarMem ( ) ; } EVT ElemVT = VT . getVectorElementType ( ) ; if ( Alignment >= ElemVT . getStoreSize ( ) ) { if ( Fast ) * Fast = true ; return true ; } return false ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> bool SSACCmpConv :: isDeadDef ( unsigned DstReg ) { if ( DstReg == AArch64 :: WZR || DstReg == AArch64 :: XZR ) return true ; if ( ! TargetRegisterInfo :: isVirtualRegister ( DstReg ) ) return false ; return MRI -> use_nodbg_empty ( DstReg ) ; } </s>

Return true if this instruction has a dead def .


<s> bool ARMTargetLowering :: isExtractSubvectorCheap ( EVT ResVT , EVT SrcVT , unsigned Index ) const { if ( ! isOperationLegalOrCustom ( ISD :: EXTRACT_SUBVECTOR , ResVT ) ) return false ; return ( Index == 0 || Index == ResVT . getVectorNumElements ( ) ) ; } </s>

Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index .


<s> int M68kFrameLowering :: mergeSPUpdates ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , bool MergeWithPrevious ) const { if ( ( MergeWithPrevious && MBBI == MBB . begin ( ) ) || ( ! MergeWithPrevious && MBBI == MBB . end ( ) ) ) return 0 ; MachineBasicBlock :: iterator PI = MergeWithPrevious ? std :: prev ( MBBI ) : MBBI ; MachineBasicBlock :: iterator NI = MergeWithPrevious ? nullptr : std :: next ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = 0 ; if ( ! MergeWithPrevious && NI != MBB . end ( ) && NI -> getOpcode ( ) == TargetOpcode :: CFI_INSTRUCTION ) { return Offset ; } if ( Opc == M68k :: ADD32ri && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { assert ( PI -> getOperand ( 1 ) . getReg ( ) == StackPtr ) ; Offset += PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! MergeWithPrevious ) MBBI = NI ; } else if ( Opc == M68k :: SUB32ri && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { assert ( PI -> getOperand ( 1 ) . getReg ( ) == StackPtr ) ; Offset -= PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! MergeWithPrevious ) MBBI = NI ; } return Offset ; } </s>

Check the instruction before/after the passed instruction .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 LEA Optimize"
;
}
</s>


<s> static tree fold_build_vec_cmp ( tree_code code , tree type , tree arg0 , tree arg1 ) { tree cmp_type = build_same_sized_truth_vector_type ( type ) ; tree zero_vec = build_zero_cst ( type ) ; tree minus_one_vec = build_minus_one_cst ( type ) ; tree cmp = fold_build2 ( code , cmp_type , arg0 , arg1 ) ; return fold_build3 ( VEC_COND_EXPR , type , cmp , minus_one_vec , zero_vec ) ; } </s>

Helper function to handle the gimple folding of a vector compare operation . This sets up true/false vectors , and uses the VEC_COND_EXPR operation . CODE indicates which comparison is to be made . ( EQ , GT , ... ) . TYPE indicates the type of the result .


<s>
void
relaxInstruction
(
const
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
,
MCInst
&
Res
)
const
override
{
assert
(
!
"Not implemented"
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


"64-bit code requested on a subtarget that doesn't support it!"

This constructor initializes the data members to match that of the specified triple .


"\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n"

Set up the stack and frame pointer ( if desired ) for the function . Note , if this is changed , you need to mirror the changes in m32r_compute_frame_size which calculates the prolog size .


<s> void BPFAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst TmpInst ; if ( ! BTF || ! BTF -> InstLower ( MI , TmpInst ) ) { BPFMCInstLower MCInstLowering ( OutContext , * this ) ; MCInstLowering . Lower ( MI , TmpInst ) ; } EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>


<s> bool mips_symbolic_constant_p ( rtx x , enum mips_symbol_context context , enum mips_symbol_type * symbol_type ) { rtx offset ; split_const ( x , & x , & offset ) ; if ( UNSPEC_ADDRESS_P ( x ) ) { * symbol_type = UNSPEC_ADDRESS_TYPE ( x ) ; x = UNSPEC_ADDRESS ( x ) ; } else if ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF ) { * symbol_type = mips_classify_symbol ( x , context ) ; if ( * symbol_type == SYMBOL_TLS ) return false ; } else return false ; if ( offset == const0_rtx ) return true ; switch ( * symbol_type ) { case SYMBOL_ABSOLUTE : case SYMBOL_64_HIGH : case SYMBOL_64_MID : case SYMBOL_64_LOW : if ( Pmode == DImode && ! ABI_HAS_64BIT_SYMBOLS ) return offset_within_block_p ( x , INTVAL ( offset ) ) ; return true ; case SYMBOL_PC_RELATIVE : if ( GET_CODE ( x ) == LABEL_REF ) return true ; case SYMBOL_GP_RELATIVE : return offset_within_block_p ( x , INTVAL ( offset ) ) ; case SYMBOL_GOT_PAGE_OFST : case SYMBOL_GOTOFF_PAGE : return SMALL_INT ( offset ) ; case SYMBOL_TPREL : case SYMBOL_DTPREL : return mips_offset_within_alignment_p ( x , INTVAL ( offset ) ) ; case SYMBOL_GOT_DISP : case SYMBOL_GOTOFF_DISP : case SYMBOL_GOTOFF_CALL : case SYMBOL_GOTOFF_LOADGP : case SYMBOL_TLSGD : case SYMBOL_TLSLDM : case SYMBOL_GOTTPREL : case SYMBOL_TLS : case SYMBOL_HALF : return false ; } gcc_unreachable ( ) ; } </s>

Return true if X is a symbolic constant that can be calculated in the same way as a bare symbol . If it is , store the type of the symbol in * SYMBOL_TYPE .


<s> bool SIInstrInfo :: isReallyTriviallyReMaterializable ( const MachineInstr & MI , AAResults * AA ) const { switch ( MI . getOpcode ( ) ) { case AMDGPU :: V_MOV_B32_e32 : case AMDGPU :: V_MOV_B32_e64 : case AMDGPU :: V_MOV_B64_PSEUDO : case AMDGPU :: V_ACCVGPR_READ_B32 : case AMDGPU :: V_ACCVGPR_WRITE_B32 : return MI . getNumOperands ( ) == MI . getDesc ( ) . getNumOperands ( ) ; default : return false ; } } </s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> bool MSP430FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


"Should be loading %r15 and something else"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


"Unhandled type for 'r' inline asm constraint"

Given a physical register constraint ( e.g .


<s> static void ia64_init_sched_context ( void * _sc , bool clean_p ) { ia64_sched_context_t sc = ( ia64_sched_context_t ) _sc ; sc -> prev_cycle_state = xmalloc ( dfa_state_size ) ; if ( clean_p ) { state_reset ( sc -> prev_cycle_state ) ; sc -> last_scheduled_insn = NULL ; memset ( sc -> rws_sum , 0 , sizeof ( rws_sum ) ) ; memset ( sc -> rws_insn , 0 , sizeof ( rws_insn ) ) ; sc -> first_instruction = 1 ; sc -> pending_data_specs = 0 ; sc -> current_cycle = 0 ; memset ( sc -> mem_ops_in_group , 0 , sizeof ( mem_ops_in_group ) ) ; } else { memcpy ( sc -> prev_cycle_state , prev_cycle_state , dfa_state_size ) ; sc -> last_scheduled_insn = last_scheduled_insn ; memcpy ( sc -> rws_sum , rws_sum , sizeof ( rws_sum ) ) ; memcpy ( sc -> rws_insn , rws_insn , sizeof ( rws_insn ) ) ; sc -> first_instruction = first_instruction ; sc -> pending_data_specs = pending_data_specs ; sc -> current_cycle = current_cycle ; memcpy ( sc -> mem_ops_in_group , mem_ops_in_group , sizeof ( mem_ops_in_group ) ) ; } } </s>

Initializes the _SC context with clean data , if CLEAN_P , and from the global context otherwise .


<s>
static
const
char
*
comparison_string
(
enum
rtx_code
code
,
rtx
op0
)
{
bool
is_nz_p
=
GET_MODE
(
op0
)
==
CC_NZmode
;
switch
(
code
)
{
default
:
output_operand_lossage
(
"bad condition code"
)
;
case
EQ
:
return
"eq"
;
case
NE
:
return
"ne"
;
case
LT
:
return
is_nz_p
"n"
:
"lt"
;
case
LE
:
return
"le"
;
case
GT
:
return
"gt"
;
case
GE
:
return
is_nz_p
"p"
:
"ge"
;
case
LTU
:
return
is_nz_p
"no"
:
"c"
;
case
LEU
:
return
is_nz_p
"eq"
:
"ls"
;
case
GTU
:
return
is_nz_p
"ne"
:
"hi"
;
case
GEU
:
return
is_nz_p
"ra"
:
"nc"
;
}
}
</s>

Return the comparison operator to use for CODE given that the ICC register is OP0 .

frv
"bad condition code"
"eq"
"ne"
"n"
"lt"
"le"
"gt"
"p"
"ge"
"no"
"c"
"eq"
"ls"
"ne"
"hi"
"ra"
"nc"


<s> static void init_float128_ibm ( machine_mode mode ) { if ( ! TARGET_XL_COMPAT ) { set_optab_libfunc ( add_optab , mode , "__gcc_qadd" ) ; set_optab_libfunc ( sub_optab , mode , "__gcc_qsub" ) ; set_optab_libfunc ( smul_optab , mode , "__gcc_qmul" ) ; set_optab_libfunc ( sdiv_optab , mode , "__gcc_qdiv" ) ; if ( ! ( TARGET_HARD_FLOAT && ( TARGET_FPRS || TARGET_E500_DOUBLE ) ) ) { set_optab_libfunc ( neg_optab , mode , "__gcc_qneg" ) ; set_optab_libfunc ( eq_optab , mode , "__gcc_qeq" ) ; set_optab_libfunc ( ne_optab , mode , "__gcc_qne" ) ; set_optab_libfunc ( gt_optab , mode , "__gcc_qgt" ) ; set_optab_libfunc ( ge_optab , mode , "__gcc_qge" ) ; set_optab_libfunc ( lt_optab , mode , "__gcc_qlt" ) ; set_optab_libfunc ( le_optab , mode , "__gcc_qle" ) ; set_conv_libfunc ( sext_optab , mode , SFmode , "__gcc_stoq" ) ; set_conv_libfunc ( sext_optab , mode , DFmode , "__gcc_dtoq" ) ; set_conv_libfunc ( trunc_optab , SFmode , mode , "__gcc_qtos" ) ; set_conv_libfunc ( trunc_optab , DFmode , mode , "__gcc_qtod" ) ; set_conv_libfunc ( sfix_optab , SImode , mode , "__gcc_qtoi" ) ; set_conv_libfunc ( ufix_optab , SImode , mode , "__gcc_qtou" ) ; set_conv_libfunc ( sfloat_optab , mode , SImode , "__gcc_itoq" ) ; set_conv_libfunc ( ufloat_optab , mode , SImode , "__gcc_utoq" ) ; } if ( ! ( TARGET_HARD_FLOAT && TARGET_FPRS ) ) set_optab_libfunc ( unord_optab , mode , "__gcc_qunord" ) ; } else { set_optab_libfunc ( add_optab , mode , "_xlqadd" ) ; set_optab_libfunc ( sub_optab , mode , "_xlqsub" ) ; set_optab_libfunc ( smul_optab , mode , "_xlqmul" ) ; set_optab_libfunc ( sdiv_optab , mode , "_xlqdiv" ) ; } if ( mode == IFmode ) { set_conv_libfunc ( sext_optab , mode , SDmode , "__dpd_extendsdtf2" ) ; set_conv_libfunc ( sext_optab , mode , DDmode , "__dpd_extendddtf2" ) ; set_conv_libfunc ( trunc_optab , mode , TDmode , "__dpd_trunctftd2" ) ; set_conv_libfunc ( trunc_optab , SDmode , mode , "__dpd_trunctfsd2" ) ; set_conv_libfunc ( trunc_optab , DDmode , mode , "__dpd_trunctfdd2" ) ; set_conv_libfunc ( sext_optab , TDmode , mode , "__dpd_extendtdtf2" ) ; if ( TARGET_POWERPC64 ) { set_conv_libfunc ( sfix_optab , TImode , mode , "__fixtfti" ) ; set_conv_libfunc ( ufix_optab , TImode , mode , "__fixunstfti" ) ; set_conv_libfunc ( sfloat_optab , mode , TImode , "__floattitf" ) ; set_conv_libfunc ( ufloat_optab , mode , TImode , "__floatuntitf" ) ; } } } </s>

Set up AIX/Darwin/64-bit Linux quad floating point routines .


<s> static int pa_adjust_priority ( rtx_insn * insn , int priority ) { rtx set = single_set ( insn ) ; rtx src , dest ; if ( set ) { src = SET_SRC ( set ) ; dest = SET_DEST ( set ) ; if ( GET_CODE ( src ) == LO_SUM && symbolic_operand ( XEXP ( src , 1 ) , VOIDmode ) && ! read_only_operand ( XEXP ( src , 1 ) , VOIDmode ) ) priority >>= 3 ; else if ( GET_CODE ( src ) == MEM && GET_CODE ( XEXP ( src , 0 ) ) == LO_SUM && symbolic_operand ( XEXP ( XEXP ( src , 0 ) , 1 ) , VOIDmode ) && ! read_only_operand ( XEXP ( XEXP ( src , 0 ) , 1 ) , VOIDmode ) ) priority >>= 1 ; else if ( GET_CODE ( dest ) == MEM && GET_CODE ( XEXP ( dest , 0 ) ) == LO_SUM && symbolic_operand ( XEXP ( XEXP ( dest , 0 ) , 1 ) , VOIDmode ) && ! read_only_operand ( XEXP ( XEXP ( dest , 0 ) , 1 ) , VOIDmode ) ) priority >>= 3 ; } return priority ; } </s>

Adjust scheduling priorities . We use this to try and keep addil and the next use of % r1 close together .


<s> static addr_space_t avr_nonconst_pointer_addrspace ( tree typ ) { while ( ARRAY_TYPE == TREE_CODE ( typ ) ) typ = TREE_TYPE ( typ ) ; if ( POINTER_TYPE_P ( typ ) ) { addr_space_t as ; tree target = TREE_TYPE ( typ ) ; if ( FUNCTION_TYPE == TREE_CODE ( target ) ) return avr_nonconst_pointer_addrspace ( TREE_TYPE ( target ) ) ; while ( TREE_CODE ( target ) == ARRAY_TYPE ) target = TREE_TYPE ( target ) ; as = TYPE_ADDR_SPACE ( target ) ; if ( ! ADDR_SPACE_GENERIC_P ( as ) && ! TYPE_READONLY ( target ) && avr_addr_space_supported_p ( as ) ) { return as ; } return avr_nonconst_pointer_addrspace ( target ) ; } return ADDR_SPACE_GENERIC ; } </s>

Scan type TYP for pointer references to address space ASn . Return ADDR_SPACE_GENERIC ( i.e . 0 ) if all pointers targeting the AS are also declared to be CONST . Otherwise , return the respective address space , i.e . a value ! = 0 .


<s> void clear ( ) { BBInfo . clear ( ) ; } </s>


<s> WebAssemblyTargetMachine :: WebAssemblyTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT . isArch64Bit ( ) ? "e-m:e-p:64:64-i64:64-n32:64-S128" : "e-m:e-p:32:32-i64:64-n32:64-S128" , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , CM , OL ) , TLOF ( TT . isOSBinFormatELF ( ) ? static_cast < TargetLoweringObjectFile * > ( new WebAssemblyTargetObjectFileELF ( ) ) : static_cast < TargetLoweringObjectFile * > ( new WebAssemblyTargetObjectFile ( ) ) ) { this -> Options . TrapUnreachable = true ; if ( ! TT . isOSBinFormatELF ( ) ) { this -> Options . FunctionSections = true ; this -> Options . DataSections = true ; this -> Options . UniqueSectionNames = true ; } initAsmInfo ( ) ; } </s>

Create an WebAssembly architecture model .

WebAssembly WebAssembly WebAssembly "e-m:e-p:64:64-i64:64-n32:64-S128" "e-m:e-p:32:32-i64:64-n32:64-S128" WebAssembly WebAssembly


<s> static void cr16_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int l = GET_MODE_BITSIZE ( mode ) / BITS_PER_WORD ; if ( ! cum -> last_parm_in_reg ) return ; if ( targetm . calls . must_pass_in_stack ( mode , type ) || ( cum -> ints < 0 ) ) return ; if ( ( mode == SImode ) || ( mode == HImode ) || ( mode == QImode ) || ( mode == DImode ) ) { if ( l <= 1 ) cum -> ints += 1 ; else cum -> ints += l ; } else if ( ( mode == SFmode ) || ( mode == DFmode ) ) cum -> ints += l ; else if ( ( mode ) == BLKmode ) { if ( ( l = enough_regs_for_param ( cum , type , mode ) ) != 0 ) cum -> ints += l ; } return ; } </s>

Implements the macro FUNCTION_ARG_ADVANCE defined in cr16.h .


<s> void nios2_set_return_address ( rtx address , rtx scratch ) { nios2_compute_frame_layout ( ) ; if ( cfun -> machine -> save_mask & ( 1 << RA_REGNO ) ) { unsigned offset = cfun -> machine -> save_reg_size - 4 ; rtx base ; if ( frame_pointer_needed ) base = hard_frame_pointer_rtx ; else { base = stack_pointer_rtx ; offset += cfun -> machine -> save_regs_offset ; if ( ! SMALL_INT ( offset ) ) { emit_move_insn ( scratch , gen_int_mode ( offset , Pmode ) ) ; emit_insn ( gen_add2_insn ( scratch , base ) ) ; base = scratch ; offset = 0 ; } } if ( offset ) base = plus_constant ( Pmode , base , offset ) ; emit_move_insn ( gen_rtx_MEM ( Pmode , base ) , address ) ; } else emit_move_insn ( gen_rtx_REG ( Pmode , RA_REGNO ) , address ) ; } </s>

Emit code to change the current function 's return address to ADDRESS . SCRATCH is available as a scratch register , if needed . ADDRESS and SCRATCH are both word-mode GPRs .


<s> void tilepro_expand_smulsi3_highpart ( rtx op0 , rtx op1 , rtx op2 ) { tilepro_expand_high_multiply ( op0 , op1 , op2 , true ) ; } </s>


<s> bool X86DAGToDAGISel :: IsProfitableToFold ( SDValue N , SDNode * U , SDNode * Root ) const { if ( OptLevel == CodeGenOpt :: None ) return false ; if ( ! N . hasOneUse ( ) ) return false ; if ( N . getOpcode ( ) != ISD :: LOAD ) return true ; if ( U == Root ) { switch ( U -> getOpcode ( ) ) { default : break ; case X86ISD :: ADD : case X86ISD :: SUB : case X86ISD :: AND : case X86ISD :: XOR : case X86ISD :: OR : case ISD :: ADD : case ISD :: ADDC : case ISD :: ADDE : case ISD :: AND : case ISD :: OR : case ISD :: XOR : { SDValue Op1 = U -> getOperand ( 1 ) ; if ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( Op1 ) ) if ( Imm -> getAPIntValue ( ) . isSignedIntN ( 8 ) ) return false ; if ( Op1 . getOpcode ( ) == X86ISD :: Wrapper ) { SDValue Val = Op1 . getOperand ( 0 ) ; if ( Val . getOpcode ( ) == ISD :: TargetGlobalTLSAddress ) return false ; } } } } return true ; } </s>

IsProfitableToFold - Returns true if it 's profitable to fold the specific operand node N of U during instruction selection that starts at Root .


<s> Register AMDGPULegalizerInfo :: handleD16VData ( MachineIRBuilder & B , MachineRegisterInfo & MRI , Register Reg ) const { if ( ! ST . hasUnpackedD16VMem ( ) ) return Reg ; const LLT S16 = LLT :: scalar ( 16 ) ; const LLT S32 = LLT :: scalar ( 32 ) ; LLT StoreVT = MRI . getType ( Reg ) ; assert ( StoreVT . isVector ( ) && StoreVT . getElementType ( ) == S16 ) ; auto Unmerge = B . buildUnmerge ( S16 , Reg ) ; SmallVector < Register , 4 > WideRegs ; for ( int I = 0 , E = Unmerge -> getNumOperands ( ) - 1 ; I != E ; ++ I ) WideRegs . push_back ( B . buildAnyExt ( S32 , Unmerge . getReg ( I ) ) . getReg ( 0 ) ) ; int NumElts = StoreVT . getNumElements ( ) ; return B . buildBuildVector ( LLT :: vector ( NumElts , S32 ) , WideRegs ) . getReg ( 0 ) ; } </s>

Handle register layout difference for f16 images for some subtargets .


<s> bool X86InstrInfo :: isAssociativeAndCommutative ( const MachineInstr & Inst ) const { switch ( Inst . getOpcode ( ) ) { case X86 :: AND8rr : case X86 :: AND16rr : case X86 :: AND32rr : case X86 :: AND64rr : case X86 :: OR8rr : case X86 :: OR16rr : case X86 :: OR32rr : case X86 :: OR64rr : case X86 :: XOR8rr : case X86 :: XOR16rr : case X86 :: XOR32rr : case X86 :: XOR64rr : case X86 :: IMUL16rr : case X86 :: IMUL32rr : case X86 :: IMUL64rr : case X86 :: PANDrr : case X86 :: PORrr : case X86 :: PXORrr : case X86 :: VPANDrr : case X86 :: VPANDYrr : case X86 :: VPORrr : case X86 :: VPORYrr : case X86 :: VPXORrr : case X86 :: VPXORYrr : case X86 :: MAXCPDrr : case X86 :: MAXCPSrr : case X86 :: MAXCSDrr : case X86 :: MAXCSSrr : case X86 :: MINCPDrr : case X86 :: MINCPSrr : case X86 :: MINCSDrr : case X86 :: MINCSSrr : case X86 :: VMAXCPDrr : case X86 :: VMAXCPSrr : case X86 :: VMAXCPDYrr : case X86 :: VMAXCPSYrr : case X86 :: VMAXCSDrr : case X86 :: VMAXCSSrr : case X86 :: VMINCPDrr : case X86 :: VMINCPSrr : case X86 :: VMINCPDYrr : case X86 :: VMINCPSYrr : case X86 :: VMINCSDrr : case X86 :: VMINCSSrr : return true ; case X86 :: ADDPDrr : case X86 :: ADDPSrr : case X86 :: ADDSDrr : case X86 :: ADDSSrr : case X86 :: MULPDrr : case X86 :: MULPSrr : case X86 :: MULSDrr : case X86 :: MULSSrr : case X86 :: VADDPDrr : case X86 :: VADDPSrr : case X86 :: VADDPDYrr : case X86 :: VADDPSYrr : case X86 :: VADDSDrr : case X86 :: VADDSSrr : case X86 :: VMULPDrr : case X86 :: VMULPSrr : case X86 :: VMULPDYrr : case X86 :: VMULPSYrr : case X86 :: VMULSDrr : case X86 :: VMULSSrr : return Inst . getParent ( ) -> getParent ( ) -> getTarget ( ) . Options . UnsafeFPMath ; default : return false ; } } </s>

Return true when \P Inst is both associative and commutative .


<s> bool SIInstrInfo :: isOperandLegal ( const MachineInstr & MI , unsigned OpIdx , const MachineOperand * MO ) const { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const MCInstrDesc & InstDesc = MI . getDesc ( ) ; const MCOperandInfo & OpInfo = InstDesc . OpInfo [ OpIdx ] ; const TargetRegisterClass * DefinedRC = OpInfo . RegClass != - 1 ? RI . getRegClass ( OpInfo . RegClass ) : nullptr ; if ( ! MO ) MO = & MI . getOperand ( OpIdx ) ; int ConstantBusLimit = ST . getConstantBusLimit ( MI . getOpcode ( ) ) ; int VOP3LiteralLimit = ST . hasVOP3Literal ( ) ? 1 : 0 ; if ( isVALU ( MI ) && usesConstantBus ( MRI , * MO , OpInfo ) ) { if ( isVOP3 ( MI ) && isLiteralConstantLike ( * MO , OpInfo ) && ! VOP3LiteralLimit -- ) return false ; SmallDenseSet < RegSubRegPair > SGPRsUsed ; if ( MO -> isReg ( ) ) SGPRsUsed . insert ( RegSubRegPair ( MO -> getReg ( ) , MO -> getSubReg ( ) ) ) ; for ( unsigned i = 0 , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { if ( i == OpIdx ) continue ; const MachineOperand & Op = MI . getOperand ( i ) ; if ( Op . isReg ( ) ) { RegSubRegPair SGPR ( Op . getReg ( ) , Op . getSubReg ( ) ) ; if ( ! SGPRsUsed . count ( SGPR ) && usesConstantBus ( MRI , Op , InstDesc . OpInfo [ i ] ) ) { if ( -- ConstantBusLimit <= 0 ) return false ; SGPRsUsed . insert ( SGPR ) ; } } else if ( InstDesc . OpInfo [ i ] . OperandType == AMDGPU :: OPERAND_KIMM32 ) { if ( -- ConstantBusLimit <= 0 ) return false ; } else if ( isVOP3 ( MI ) && AMDGPU :: isSISrcOperand ( InstDesc , i ) && isLiteralConstantLike ( Op , InstDesc . OpInfo [ i ] ) ) { if ( ! VOP3LiteralLimit -- ) return false ; if ( -- ConstantBusLimit <= 0 ) return false ; } } } if ( MO -> isReg ( ) ) { assert ( DefinedRC ) ; return isLegalRegOperand ( MRI , OpInfo , * MO ) ; } assert ( MO -> isImm ( ) || MO -> isTargetIndex ( ) || MO -> isFI ( ) || MO -> isGlobal ( ) ) ; if ( ! DefinedRC ) { return true ; } return isImmOperandLegal ( MI , OpIdx , * MO ) ; } </s>

Check if MO is a legal operand if it was the OpIdx Operand for MI .


<s> int barrier_align ( rtx barrier_or_label ) { rtx next = next_real_insn ( barrier_or_label ) , pat , prev ; int slot , credit , jump_to_next = 0 ; if ( ! next ) return 0 ; pat = PATTERN ( next ) ; if ( GET_CODE ( pat ) == ADDR_DIFF_VEC ) return 2 ; if ( GET_CODE ( pat ) == UNSPEC_VOLATILE && XINT ( pat , 1 ) == UNSPECV_ALIGN ) return 0 ; prev = prev_real_insn ( barrier_or_label ) ; if ( GET_CODE ( PATTERN ( prev ) ) == ADDR_DIFF_VEC ) { pat = PATTERN ( prev ) ; return ( ( TARGET_SMALLCODE || ( ( unsigned ) XVECLEN ( pat , 1 ) * GET_MODE_SIZE ( GET_MODE ( pat ) ) <= ( unsigned ) 1 << ( CACHE_LOG - 2 ) ) ) ? 1 << TARGET_SHMEDIA : align_jumps_log ) ; } if ( TARGET_SMALLCODE ) return 0 ; if ( ! TARGET_SH2 || ! optimize ) return align_jumps_log ; if ( mdep_reorg_phase > SH_FIXUP_PCLOAD ) { prev = prev_real_insn ( prev ) ; for ( slot = 2 , credit = ( 1 << ( CACHE_LOG - 2 ) ) + 2 ; credit >= 0 && prev && GET_CODE ( prev ) == INSN ; prev = prev_real_insn ( prev ) ) { jump_to_next = 0 ; if ( GET_CODE ( PATTERN ( prev ) ) == USE || GET_CODE ( PATTERN ( prev ) ) == CLOBBER ) continue ; if ( GET_CODE ( PATTERN ( prev ) ) == SEQUENCE ) { prev = XVECEXP ( PATTERN ( prev ) , 0 , 1 ) ; if ( INSN_UID ( prev ) == INSN_UID ( next ) ) { jump_to_next = 1 ; continue ; } } if ( slot && get_attr_in_delay_slot ( prev ) == IN_DELAY_SLOT_YES ) slot = 0 ; credit -= get_attr_length ( prev ) ; } if ( prev && GET_CODE ( prev ) == JUMP_INSN && JUMP_LABEL ( prev ) ) { rtx x ; if ( jump_to_next || next_real_insn ( JUMP_LABEL ( prev ) ) == next || JUMP_LABEL ( prev ) == next_nonnote_insn ( next ) || ( x = ( NEXT_INSN ( NEXT_INSN ( PREV_INSN ( prev ) ) ) ) , ( INSN_P ( x ) && ( INSN_CODE ( x ) == CODE_FOR_block_branch_redirect || INSN_CODE ( x ) == CODE_FOR_indirect_jump_scratch || INSN_CODE ( x ) == CODE_FOR_stuff_delay_slot ) ) ) ) { rtx pat = PATTERN ( prev ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , 0 , 0 ) ; if ( credit - slot >= ( GET_CODE ( SET_SRC ( pat ) ) == PC ? 2 : 0 ) ) return 0 ; } } } return align_jumps_log ; } </s>

BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following a barrier . Return the base 2 logarithm of the desired alignment .


"Unexpected operand for inline assembly"

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static ArrayRef < MCPhysReg > getAllSGPR128 ( const SISubtarget & ST , const MachineFunction & MF ) { return makeArrayRef ( AMDGPU :: SGPR_128RegClass . begin ( ) , ST . getMaxNumSGPRs ( MF ) / 4 ) ; } </s>

Return all SGPR128 which satisfy the waves per execution unit requirement of the subtarget .


<s> rtx aarch64_expand_builtin ( tree exp , rtx target , rtx subtarget ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , int ignore ATTRIBUTE_UNUSED ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , 0 ) ; int fcode = DECL_FUNCTION_CODE ( fndecl ) ; int icode ; rtx pat , op0 ; tree arg0 ; switch ( fcode ) { case AARCH64_BUILTIN_GET_FPCR : case AARCH64_BUILTIN_SET_FPCR : case AARCH64_BUILTIN_GET_FPSR : case AARCH64_BUILTIN_SET_FPSR : if ( ( fcode == AARCH64_BUILTIN_GET_FPCR ) || ( fcode == AARCH64_BUILTIN_GET_FPSR ) ) { icode = ( fcode == AARCH64_BUILTIN_GET_FPSR ) ? CODE_FOR_get_fpsr : CODE_FOR_get_fpcr ; target = gen_reg_rtx ( SImode ) ; pat = GEN_FCN ( icode ) ( target ) ; } else { target = NULL_RTX ; icode = ( fcode == AARCH64_BUILTIN_SET_FPSR ) ? CODE_FOR_set_fpsr : CODE_FOR_set_fpcr ; arg0 = CALL_EXPR_ARG ( exp , 0 ) ; op0 = expand_normal ( arg0 ) ; pat = GEN_FCN ( icode ) ( op0 ) ; } emit_insn ( pat ) ; return target ; } if ( fcode >= AARCH64_SIMD_BUILTIN_BASE && fcode <= AARCH64_SIMD_BUILTIN_MAX ) return aarch64_simd_expand_builtin ( fcode , exp , target ) ; else if ( fcode >= AARCH64_CRC32_BUILTIN_BASE && fcode <= AARCH64_CRC32_BUILTIN_MAX ) return aarch64_crc32_expand_builtin ( fcode , exp , target ) ; gcc_unreachable ( ) ; } </s>


Try to find a mode with the given mode_suffix_info fields . Return the mode on success or MODE_none on failure .


<s> void s390_output_pool_entry ( rtx exp , machine_mode mode , unsigned int align ) { REAL_VALUE_TYPE r ; switch ( GET_MODE_CLASS ( mode ) ) { case MODE_FLOAT : case MODE_DECIMAL_FLOAT : gcc_assert ( GET_CODE ( exp ) == CONST_DOUBLE ) ; REAL_VALUE_FROM_CONST_DOUBLE ( r , exp ) ; assemble_real ( r , mode , align ) ; break ; case MODE_INT : assemble_integer ( exp , GET_MODE_SIZE ( mode ) , align , 1 ) ; mark_symbol_refs_as_used ( exp ) ; break ; default : gcc_unreachable ( ) ; } } </s>

Output the constant pool entry EXP in mode MODE with alignment ALIGN .


<s> bool RISCVELFTargetObjectFile :: isGlobalInSmallSection ( const GlobalObject * GO , const TargetMachine & TM ) const { const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GO ) ; if ( ! GVA ) return false ; if ( GVA -> hasSection ( ) ) { StringRef Section = GVA -> getSection ( ) ; if ( Section == ".sdata" || Section == ".sbss" ) return true ; return false ; } if ( ( ( GVA -> hasExternalLinkage ( ) && GVA -> isDeclaration ( ) ) || GVA -> hasCommonLinkage ( ) ) ) return false ; Type * Ty = GVA -> getValueType ( ) ; if ( ! Ty -> isSized ( ) ) return false ; return isInSmallSection ( GVA -> getParent ( ) -> getDataLayout ( ) . getTypeAllocSize ( Ty ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , JIT , RM ) , getEffectiveX86CodeModel ( CM , JIT , TT . getArch ( ) == Triple :: x86_64 ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) { if ( TT . isPS4 ( ) || TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = TT . isOSBinFormatMachO ( ) ; } if ( TT . getArch ( ) == Triple :: x86_64 ) setMachineOutliner ( true ) ; initAsmInfo ( ) ; } </s>


"Missing call preserved mask for calling convention"

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


<s> StringRef getPassName ( ) const override { return AARCH64_TYPE_PROMO_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


"OpFunction is expected in the front MBB of MF"

Targets can override this to emit stuff at the start of a basic block .


<s> const ARCRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
const
char
*
output_sibcall
(
rtx
x
)
{
if
(
symbolic_operand
(
x
,
VOIDmode
)
)
return
m68k_symbolic_jump
;
else
return
"jmp %a0"
;
}
</s>


<s> std :: pair < unsigned , unsigned > getWavesPerEU ( ) const { return WavesPerEU ; } </s>

Overload which uses the specified values for the flat work group sizes , rather than querying the function itself .


"64-bit WebAssembly (wasm64) is not currently supported"

runOnMachineFunction - Emit the function body .


<s> void print ( raw_ostream & OS ) const { } </s>

print - Print a debug representation of the operand to the given stream .


<s> void final_prescan_insn ( rtx_insn * insn , rtx opvec [ ] ATTRIBUTE_UNUSED , int noperands ATTRIBUTE_UNUSED ) { if ( dslots_number_nops > 0 ) { rtx pattern = PATTERN ( insn ) ; int length = get_attr_length ( insn ) ; if ( length == 0 || ( iq2000_load_reg != 0 && reg_mentioned_p ( iq2000_load_reg , pattern ) ) || ( iq2000_load_reg2 != 0 && reg_mentioned_p ( iq2000_load_reg2 , pattern ) ) || ( iq2000_load_reg3 != 0 && reg_mentioned_p ( iq2000_load_reg3 , pattern ) ) || ( iq2000_load_reg4 != 0 && reg_mentioned_p ( iq2000_load_reg4 , pattern ) ) ) fputs ( "\tnop\n" , asm_out_file ) ; else dslots_load_filled ++ ; while ( -- dslots_number_nops > 0 ) fputs ( "\tnop\n" , asm_out_file ) ; iq2000_load_reg = 0 ; iq2000_load_reg2 = 0 ; iq2000_load_reg3 = 0 ; iq2000_load_reg4 = 0 ; } if ( ( JUMP_P ( insn ) || CALL_P ( insn ) || ( GET_CODE ( PATTERN ( insn ) ) == RETURN ) ) && NEXT_INSN ( PREV_INSN ( insn ) ) == insn ) { rtx_insn * tmp = insn ; while ( NEXT_INSN ( tmp ) && NOTE_P ( NEXT_INSN ( tmp ) ) && NOTE_KIND ( NEXT_INSN ( tmp ) ) == NOTE_INSN_CALL_ARG_LOCATION ) tmp = NEXT_INSN ( tmp ) ; rtx_insn * nop_insn = emit_insn_after ( gen_nop ( ) , tmp ) ; INSN_ADDRESSES_NEW ( nop_insn , - 1 ) ; } if ( TARGET_STATS && ( JUMP_P ( insn ) || CALL_P ( insn ) ) ) dslots_jump_total ++ ; } </s>

If defined , a C statement to be executed just prior to the output of assembler code for INSN , to modify the extracted operands so they will be output differently . Here the argument OPVEC is the vector containing the operands extracted from INSN , and NOPERANDS is the number of elements of the vector which contain meaningful data for this insn . The contents of this vector are what will be used to convert the insn template into assembler code , so you can change the assembler output by changing the contents of the vector . We use it to check if the current insn needs a nop in front of it because of load delays , and also to update the delay slot statistics .


<s>
void
AArch64InstrInfo
::
suppressLdStPair
(
MachineInstr
*
MI
)
const
{
if
(
MI
->
memoperands_empty
(
)
)
return
;
assert
(
MOSuppressPair
<
(
1
<<
MachineMemOperand
::
MOTargetNumBits
)
&&
"Too many target MO flags"
)
;
(
*
MI
->
memoperands_begin
(
)
)
->
setFlags
(
MOSuppressPair
<<
MachineMemOperand
::
MOTargetStartBit
)
;
}
</s>

Hint that pairing the given load or store is unprofitable .


<s>
void
AlphaTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
{
DebugLoc
dl
=
N
->
getDebugLoc
(
)
;
assert
(
N
->
getValueType
(
0
)
==
MVT
::
i32
&&
N
->
getOpcode
(
)
==
ISD
::
VAARG
&&
"Unknown node to custom promote!"
)
;
SDValue
Chain
,
DataPtr
;
LowerVAARG
(
N
,
Chain
,
DataPtr
,
DAG
)
;
SDValue
Res
=
DAG
.
getLoad
(
N
->
getValueType
(
0
)
,
dl
,
Chain
,
DataPtr
,
,
0
)
;
Results
.
push_back
(
Res
)
;
Results
.
push_back
(
SDValue
(
Res
.
getNode
(
)
,
1
)
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s>
bool
m32c_legitimate_address_p
(
machine_mode
mode
,
rtx
x
,
bool
strict
)
{
int
mode_adjust
;
if
(
CONSTANT_P
(
x
)
)
return
1
;
if
(
TARGET_A16
&&
GET_MODE
(
x
)
!=
HImode
&&
GET_MODE
(
x
)
!=
SImode
)
return
0
;
if
(
TARGET_A24
&&
GET_MODE
(
x
)
!=
PSImode
)
return
0
;
mode_adjust
=
GET_MODE_SIZE
(
mode
)
1
;
if
(
GET_CODE
(
x
)
==
PRE_DEC
||
GET_CODE
(
x
)
==
POST_INC
||
GET_CODE
(
x
)
==
PRE_MODIFY
)
{
return
(
GET_CODE
(
XEXP
(
x
,
0
)
)
==
REG
&&
REGNO
(
XEXP
(
x
,
0
)
)
==
SP_REGNO
)
;
}
if
(
TARGET_A24
&&
GET_CODE
(
x
)
==
MEM
&&
GET_CODE
(
XEXP
(
x
,
0
)
)
!=
PLUS
)
{
fprintf
(
stderr
,
"double indirect\n"
)
;
x
=
XEXP
(
x
,
0
)
;
}
encode_pattern
(
x
)
;
if
(
RTX_IS
(
"r"
)
)
{
switch
(
REGNO
(
patternr
[
0
]
)
)
{
case
A1_REGNO
:
case
SB_REGNO
:
case
FB_REGNO
:
case
SP_REGNO
:
if
(
TARGET_A16
&&
GET_MODE
(
x
)
==
SImode
)
return
0
;
case
A0_REGNO
:
return
1
;
default
:
if
(
IS_PSEUDO
(
patternr
[
0
]
,
strict
)
)
return
1
;
return
0
;
}
}
if
(
TARGET_A16
&&
GET_MODE
(
x
)
==
SImode
)
return
0
;
if
(
RTX_IS
(
"+ri"
)
)
{
int
rn
=
REGNO
(
patternr
[
1
]
)
;
HOST_WIDE_INT
offs
=
INTVAL
(
patternr
[
2
]
)
;
switch
(
rn
)
{
case
A0_REGNO
:
case
A1_REGNO
:
case
SB_REGNO
:
if
(
TARGET_A16
)
return
(
offs
>=
65536
&&
offs
<=
65535
mode_adjust
)
;
if
(
rn
==
SB_REGNO
)
return
(
offs
>=
0
&&
offs
<=
65535
mode_adjust
)
;
return
(
offs
>=
16777216
&&
offs
<=
16777215
)
;
case
FB_REGNO
:
if
(
TARGET_A16
)
return
(
offs
>=
128
&&
offs
<=
127
mode_adjust
)
;
return
(
offs
>=
65536
&&
offs
<=
65535
mode_adjust
)
;
case
SP_REGNO
:
return
(
offs
>=
128
&&
offs
<=
127
mode_adjust
)
;
default
:
if
(
IS_PSEUDO
(
patternr
[
1
]
,
strict
)
)
return
1
;
return
0
;
}
}
if
(
RTX_IS
(
"+rs"
)
||
RTX_IS
(
"+r+si"
)
)
{
rtx
reg
=
patternr
[
1
]
;
switch
(
REGNO
(
reg
)
)
{
case
A0_REGNO
:
case
A1_REGNO
:
return
1
;
default
:
if
(
GET_CODE
(
reg
)
==
SUBREG
)
return
0
;
if
(
IS_PSEUDO
(
reg
,
strict
)
)
return
1
;
return
0
;
}
}
return
0
;
}
</s>

Used by GO_IF_LEGITIMATE_ADDRESS . The r8c/m32c family supports a wide range of non-orthogonal addressing modes , including the ability to double-indirect on * some * of them . Not all insns support all modes , either , but we rely on predicates and constraints to deal with that .


<s> const char * getPassName ( ) const override { return "relooper" ; } </s>


<s> unsigned RISCVTargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { switch ( Op . getOpcode ( ) ) { default : break ; case RISCVISD :: SLLW : case RISCVISD :: SRAW : case RISCVISD :: SRLW : case RISCVISD :: DIVW : case RISCVISD :: DIVUW : case RISCVISD :: REMUW : case RISCVISD :: ROLW : case RISCVISD :: RORW : case RISCVISD :: GREVIW : case RISCVISD :: GORCIW : case RISCVISD :: FSLW : case RISCVISD :: FSRW : return 33 ; } return 1 ; } </s>

Determine the number of bits in the operation that are sign bits .

RISCV RISCV RISCVISD::SLLW RISCVISD::SRAW RISCVISD::SRLW RISCVISD::DIVW RISCVISD::DIVUW RISCVISD::REMUW RISCVISD::ROLW RISCVISD::RORW RISCVISD::GREVIW RISCVISD::GORCIW RISCVISD::FSLW RISCVISD::FSRW 33 1


<s> SDValue R600TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; SmallVector < ISD :: InputArg , 8 > LocalIns ; if ( AMDGPU :: isShader ( CallConv ) ) { CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForCall ( CallConv , isVarArg ) ) ; } else { analyzeFormalArgumentsCompute ( CCInfo , Ins ) ; } for ( unsigned i = 0 , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const ISD :: InputArg & In = Ins [ i ] ; EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector ( ) ) { MemVT = MemVT . getVectorElementType ( ) ; } if ( AMDGPU :: isShader ( CallConv ) ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & R600 :: R600_Reg128RegClass ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , AMDGPUASI . CONSTANT_BUFFER_0 ) ; ISD :: LoadExtType Ext = ISD :: NON_EXTLOAD ; if ( MemVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) { Ext = ISD :: SEXTLOAD ; } unsigned ValBase = ArgLocs [ In . getOrigArgIndex ( ) ] . getLocMemOffset ( ) ; unsigned PartOffset = VA . getLocMemOffset ( ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) , PartOffset - ValBase ) ; SDValue Arg = DAG . getLoad ( ISD :: UNINDEXED , Ext , VT , DL , Chain , DAG . getConstant ( PartOffset , DL , MVT :: i32 ) , DAG . getUNDEF ( MVT :: i32 ) , PtrInfo , MemVT , 4 , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; InVals . push_back ( Arg ) ; } return Chain ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> const char * msp430_mcu_name ( void ) { if ( target_mcu ) { unsigned int i ; unsigned int start_upper ; unsigned int end_upper ; static char mcu_name [ 64 ] ; if ( strncmp ( target_mcu , "msp430i" , 7 ) == 0 ) { snprintf ( mcu_name , sizeof ( mcu_name ) - 1 , "__MSP430i%s__" , target_mcu + 7 ) ; start_upper = 9 ; } else { snprintf ( mcu_name , sizeof ( mcu_name ) - 1 , "__%s__" , target_mcu ) ; start_upper = 2 ; } end_upper = strlen ( mcu_name ) - 2 ; for ( i = start_upper ; i < end_upper ; i ++ ) mcu_name [ i ] = TOUPPER ( mcu_name [ i ] ) ; return mcu_name ; } return msp430x ? "__MSP430XGENERIC__" : "__MSP430GENERIC__" ; } </s>

Generate a C preprocessor symbol based upon the MCU selected by the user . If a specific MCU has not been selected then return a generic symbol instead .


<s>
bool
Z80oldRegisterInfo
::
shouldCoalesce
(
MachineInstr
*
MI
,
const
TargetRegisterClass
*
SrcRC
,
unsigned
SrcSubReg
,
const
TargetRegisterClass
*
DstRC
,
unsigned
DstSubReg
,
const
TargetRegisterClass
*
NewRC
,
LiveIntervals
&
LIS
)
const
{
const
TargetRegisterInfo
&
TRI
=
*
MI
->
getParent
(
)
->
getParent
(
)
->
getRegInfo
(
)
.
getTargetRegisterInfo
(
)
;
(
void
)
TRI
;
LLVM_DEBUG
(
dbgs
(
)
<<
TRI
.
getRegClassName
(
SrcRC
)
<<
'['
<<
SrcRC
->
getNumRegs
(
)
<<
"]:"
<<
(
SrcSubReg
TRI
.
getSubRegIndexName
(
SrcSubReg
)
:
""
)
<<
" -> "
<<
TRI
.
getRegClassName
(
DstRC
)
<<
'['
<<
DstRC
->
getNumRegs
(
)
<<
"]:"
<<
(
DstSubReg
TRI
.
getSubRegIndexName
(
DstSubReg
)
:
""
)
<<
' '
<<
TRI
.
getRegClassName
(
NewRC
)
<<
'['
<<
NewRC
->
getNumRegs
(
)
<<
"]\n"
)
;
return
std
::
min
(
SrcRC
->
getNumRegs
(
)
,
DstRC
->
getNumRegs
(
)
)
<=
NewRC
->
getNumRegs
(
)
;
}
</s>


"%qE attribute only applies to functions"

"%qE attribute requires a void return type"

Handle a `` kernel '' attribute ; arguments as in struct attribute_spec.handler .


<s> void m32c_emit_epilogue ( void ) { if ( m32c_pushm_popm ( PP_justcount ) > 0 || cfun -> machine -> is_interrupt ) emit_insn ( gen_epilogue_start ( ) ) ; m32c_pushm_popm ( PP_popm ) ; if ( cfun -> machine -> is_interrupt ) { enum machine_mode spmode = TARGET_A16 ? HImode : PSImode ; emit_move_insn ( gen_rtx_REG ( spmode , A0_REGNO ) , gen_rtx_REG ( spmode , FP_REGNO ) ) ; emit_move_insn ( gen_rtx_REG ( spmode , SP_REGNO ) , gen_rtx_REG ( spmode , A0_REGNO ) ) ; if ( TARGET_A16 ) emit_insn ( gen_pophi_16 ( gen_rtx_REG ( HImode , FP_REGNO ) ) ) ; else emit_insn ( gen_poppsi ( gen_rtx_REG ( PSImode , FP_REGNO ) ) ) ; emit_insn ( gen_popm ( GEN_INT ( cfun -> machine -> intr_pushm ) ) ) ; emit_jump_insn ( gen_epilogue_reit ( GEN_INT ( TARGET_A16 ? 4 : 6 ) ) ) ; } else if ( cfun -> machine -> use_rts ) emit_jump_insn ( gen_epilogue_rts ( ) ) ; else emit_jump_insn ( gen_epilogue_exitd ( GEN_INT ( TARGET_A16 ? 2 : 4 ) ) ) ; emit_barrier ( ) ; } </s>

Likewise , for the epilogue . The only exception is that , for interrupts , we must manually unwind the frame as the REIT opcode does n't do that .


<s> bool nios2_emit_move_sequence ( rtx * operands , machine_mode mode ) { rtx to = operands [ 0 ] ; rtx from = operands [ 1 ] ; if ( ! register_operand ( to , mode ) && ! reg_or_0_operand ( from , mode ) ) { gcc_assert ( can_create_pseudo_p ( ) ) ; from = copy_to_mode_reg ( mode , from ) ; } if ( CONSTANT_P ( from ) ) { if ( CONST_INT_P ( from ) ) { if ( ! SMALL_INT ( INTVAL ( from ) ) && ! SMALL_INT_UNSIGNED ( INTVAL ( from ) ) && ! UPPER16_INT ( INTVAL ( from ) ) ) { HOST_WIDE_INT high = ( INTVAL ( from ) + 0x8000 ) & ~ 0xffff ; HOST_WIDE_INT low = INTVAL ( from ) & 0xffff ; emit_move_insn ( to , gen_int_mode ( high , SImode ) ) ; emit_insn ( gen_add2_insn ( to , gen_int_mode ( low , HImode ) ) ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , copy_rtx ( from ) ) ; return true ; } } else if ( ! gprel_constant_p ( from ) ) { if ( ! nios2_large_unspec_reloc_p ( from ) ) from = nios2_legitimize_constant_address ( from ) ; if ( CONSTANT_P ( from ) ) { emit_insn ( gen_rtx_SET ( to , gen_rtx_HIGH ( Pmode , copy_rtx ( from ) ) ) ) ; emit_insn ( gen_rtx_SET ( to , gen_rtx_LO_SUM ( Pmode , to , from ) ) ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , copy_rtx ( operands [ 1 ] ) ) ; return true ; } } } operands [ 0 ] = to ; operands [ 1 ] = from ; return false ; } </s>


<s> bool isImm ( ) const { return Kind == Immediate ; } </s>


<s>
SDValue
OpenRISCTargetLowering
::
LowerCall
(
SDValue
Chain
,
SDValue
Callee
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
bool
doesNotRet
,
bool
&
isTailCall
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
OutVals
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .

OpenRISC
OpenRISC
ISD::OutputArg
ISD::InputArg
"Unsupported calling convention"


<s> unsigned int rs6000_data_alignment ( tree type , unsigned int align , enum data_align how ) { if ( how != align_opt ) { if ( TREE_CODE ( type ) == VECTOR_TYPE ) { if ( ( TARGET_SPE && SPE_VECTOR_MODE ( TYPE_MODE ( type ) ) ) || ( TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE ( TYPE_MODE ( type ) ) ) ) { if ( align < 64 ) align = 64 ; } else if ( align < 128 ) align = 128 ; } else if ( TARGET_E500_DOUBLE && TREE_CODE ( type ) == REAL_TYPE && TYPE_MODE ( type ) == DFmode ) { if ( align < 64 ) align = 64 ; } } if ( how != align_abi ) { if ( TREE_CODE ( type ) == ARRAY_TYPE && TYPE_MODE ( TREE_TYPE ( type ) ) == QImode ) { if ( align < BITS_PER_WORD ) align = BITS_PER_WORD ; } } return align ; } </s>

Return alignment of TYPE . Existing alignment is ALIGN . HOW selects whether the alignment is abi mandated , optional , or both abi and optional alignment .


<s>
void
X86ATTInstPrinter
::
printPCRelImm
(
const
MCInst
*
MI
,
unsigned
OpNo
,
raw_ostream
&
O
)
{
const
MCOperand
&
Op
=
MI
->
getOperand
(
OpNo
)
;
if
(
Op
.
isImm
(
)
)
O
<<
formatImm
(
Op
.
getImm
(
)
)
;
else
{
assert
(
Op
.
isExpr
(
)
&&
"unknown pcrel immediate operand"
)
;
const
MCConstantExpr
*
BranchTarget
=
dyn_cast
<
MCConstantExpr
>
(
Op
.
getExpr
(
)
)
;
int64_t
Address
;
if
(
BranchTarget
&&
BranchTarget
->
evaluateAsAbsolute
(
Address
)
)
{
O
<<
formatHex
(
(
uint64_t
)
Address
)
;
}
else
{
Op
.
getExpr
(
)
->
print
(
O
,
&
MAI
)
;
}
}
}
</s>


"JIT relocation model must be set to static or default!"


<s> TargetPassConfig * GCNTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new GCNPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> MCAssembler * getAssembler ( ) const { return Assembler ; } </s>

Get the assembler object this is a layout for .


<s> bool ix86_avoid_lea_for_add ( rtx_insn * insn , rtx operands [ ] ) { unsigned int regno0 , regno1 , regno2 ; if ( ! TARGET_OPT_AGU || optimize_function_for_size_p ( cfun ) ) return false ; regno0 = true_regnum ( operands [ 0 ] ) ; regno1 = true_regnum ( operands [ 1 ] ) ; regno2 = true_regnum ( operands [ 2 ] ) ; if ( regno0 == regno1 || regno0 == regno2 ) return false ; else return ! ix86_lea_outperforms ( insn , regno0 , regno1 , regno2 , 1 , false ) ; } </s>

Return true if we need to split op0 = op1 + op2 into a sequence of move and add to avoid AGU stalls .


<s> virtual const MCSection * getSectionForConstant ( SectionKind Kind ) const { return ReadOnlySection ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> void R600InstrInfo :: reserveIndirectRegisters ( BitVector & Reserved , const MachineFunction & MF ) const { const AMDGPUFrameLowering * TFL = static_cast < const AMDGPUFrameLowering * > ( MF . getSubtarget ( ) . getFrameLowering ( ) ) ; unsigned StackWidth = TFL -> getStackWidth ( MF ) ; int End = getIndirectIndexEnd ( MF ) ; if ( End == - 1 ) return ; for ( int Index = getIndirectIndexBegin ( MF ) ; Index <= End ; ++ Index ) { unsigned SuperReg = AMDGPU :: R600_Reg128RegClass . getRegister ( Index ) ; Reserved . set ( SuperReg ) ; for ( unsigned Chan = 0 ; Chan < StackWidth ; ++ Chan ) { unsigned Reg = AMDGPU :: R600_TReg32RegClass . getRegister ( ( 4 * Index ) + Chan ) ; Reserved . set ( Reg ) ; } } } </s>

Reserve the registers that may be accessed using indirect addressing .


"InsertBranch must not be told to insert a fallthrough"

"CAHP branch conditions have two components!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> unsigned getReg ( ) const override { assert ( isReg ( ) ) ; return MVTToWasmReg ( Reg . Type ) ; } </s>

Returns the register associated with this edge .


<s>
void
addInstruction
(
TagStoreInstr
I
)
{
assert
(
(
TagStores
.
empty
(
)
||
TagStores
.
back
(
)
.
Offset
+
TagStores
.
back
(
)
.
Size
==
I
.
Offset
)
&&
"Non-adjacent tag store instructions."
)
;
TagStores
.
push_back
(
I
)
;
}
</s>

Record pressure difference induced by the given operand list to node with index Idx .


<s> static void ix86_setup_incoming_varargs ( cumulative_args_t cum_v , const function_arg_info & arg , int * , int no_rtl ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; CUMULATIVE_ARGS next_cum ; tree fntype ; gcc_assert ( ! no_rtl ) ; if ( ! TARGET_64BIT ) return ; fntype = TREE_TYPE ( current_function_decl ) ; next_cum = * cum ; if ( stdarg_p ( fntype ) ) ix86_function_arg_advance ( pack_cumulative_args ( & next_cum ) , arg ) ; if ( cum -> call_abi == MS_ABI ) setup_incoming_varargs_ms_64 ( & next_cum ) ; else setup_incoming_varargs_64 ( & next_cum ) ; } </s>

Worker function for TARGET_SETUP_INCOMING_VARARGS .


<s> SDValue SystemZTargetLowering :: prepareVolatileOrAtomicLoad ( SDValue Chain , const SDLoc & DL , SelectionDAG & DAG ) const { return DAG . getNode ( SystemZISD :: SERIALIZE , DL , MVT :: Other , Chain ) ; } </s>

This callback is used to prepare for a volatile or atomic load .

SystemZ SystemZ SystemZISD::SERIALIZE MVT::Other


<s> void emitBytes ( StringRef Data ) override { emitDataMappingSymbol ( ) ; MCELFStreamer :: emitBytes ( Data ) ; } </s>

Emit the bytes in Data into the output .


<s> static char * arc_tolower ( char * lo , const char * up ) { char * lo0 = lo ; for ( ; * up ; up ++ , lo ++ ) * lo = TOLOWER ( * up ) ; * lo = '\0' ; return lo0 ; } </s>

Transform UP into lowercase and write the result to LO . You must provide enough space for LO . Return LO .


<s>
bool
RISCVInstrInfo
::
isBranchOffsetInRange
(
unsigned
BranchOp
,
int64_t
BrOffset
)
const
{
switch
(
BranchOp
)
{
default
:
llvm_unreachable
(
"Unexpected opcode!"
)
;
case
RISCV
::
BEQ
:
case
RISCV
::
BNE
:
case
RISCV
::
BLT
:
case
RISCV
::
BGE
:
case
RISCV
::
BLTU
:
case
RISCV
::
BGEU
:
case
RISCV
::
P_BEQIMM
:
case
RISCV
::
P_BNEIMM
:
return
isIntN
(
13
,
BrOffset
)
;
case
RISCV
::
JAL
:
case
RISCV
::
PseudoBR
:
return
isIntN
(
21
,
BrOffset
)
;
case
RISCV
::
LoopBranch
:
return
true
;
}
}
</s>

Determine if the branch target is in range .

RISCV
RISCV
"Unexpected opcode!"
RISCV::BEQ
RISCV::BNE
RISCV::BLT
RISCV::BGE
RISCV::BLTU
RISCV::BGEU
RISCV::P_BEQIMM
RISCV::P_BNEIMM
13
RISCV::JAL
RISCV::PseudoBR
21
RISCV::LoopBranch


<s> void RISCVFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterClass * RC = & RISCV :: GPRRegClass ; if ( ! isInt < 11 > ( MFI . estimateStackSize ( MF ) ) ) { const DataLayout & DL = MF . getDataLayout ( ) ; int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC , DL ) , RegInfo -> getSpillAlignment ( * RC , DL ) , false ) ; RS -> addScavengingFrameIndex ( RegScavFI ) ; } } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> void ix86_expand_vector_logical_operator ( enum rtx_code code , machine_mode mode , rtx operands [ ] ) { rtx op1 = NULL_RTX , op2 = NULL_RTX ; if ( SUBREG_P ( operands [ 1 ] ) ) { op1 = operands [ 1 ] ; op2 = operands [ 2 ] ; } else if ( SUBREG_P ( operands [ 2 ] ) ) { op1 = operands [ 2 ] ; op2 = operands [ 1 ] ; } if ( op1 && ! TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL && ( SUBREG_P ( op2 ) || GET_CODE ( op2 ) == CONST_VECTOR ) && GET_MODE_CLASS ( GET_MODE ( SUBREG_REG ( op1 ) ) ) == MODE_VECTOR_FLOAT && GET_MODE_SIZE ( GET_MODE ( SUBREG_REG ( op1 ) ) ) == GET_MODE_SIZE ( mode ) && SUBREG_BYTE ( op1 ) == 0 && ( GET_CODE ( op2 ) == CONST_VECTOR || ( GET_MODE ( SUBREG_REG ( op1 ) ) == GET_MODE ( SUBREG_REG ( op2 ) ) && SUBREG_BYTE ( op2 ) == 0 ) ) && can_create_pseudo_p ( ) ) { rtx dst ; switch ( GET_MODE ( SUBREG_REG ( op1 ) ) ) { case E_V4SFmode : case E_V8SFmode : case E_V16SFmode : case E_V2DFmode : case E_V4DFmode : case E_V8DFmode : dst = gen_reg_rtx ( GET_MODE ( SUBREG_REG ( op1 ) ) ) ; if ( GET_CODE ( op2 ) == CONST_VECTOR ) { op2 = gen_lowpart ( GET_MODE ( dst ) , op2 ) ; op2 = force_reg ( GET_MODE ( dst ) , op2 ) ; } else { op1 = operands [ 1 ] ; op2 = SUBREG_REG ( operands [ 2 ] ) ; if ( ! vector_operand ( op2 , GET_MODE ( dst ) ) ) op2 = force_reg ( GET_MODE ( dst ) , op2 ) ; } op1 = SUBREG_REG ( op1 ) ; if ( ! vector_operand ( op1 , GET_MODE ( dst ) ) ) op1 = force_reg ( GET_MODE ( dst ) , op1 ) ; emit_insn ( gen_rtx_SET ( dst , gen_rtx_fmt_ee ( code , GET_MODE ( dst ) , op1 , op2 ) ) ) ; emit_move_insn ( operands [ 0 ] , gen_lowpart ( mode , dst ) ) ; return ; default : break ; } } if ( ! vector_operand ( operands [ 1 ] , mode ) ) operands [ 1 ] = force_reg ( mode , operands [ 1 ] ) ; if ( ! vector_operand ( operands [ 2 ] , mode ) ) operands [ 2 ] = force_reg ( mode , operands [ 2 ] ) ; ix86_fixup_binary_operands_no_copy ( code , mode , operands ) ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , gen_rtx_fmt_ee ( code , mode , operands [ 1 ] , operands [ 2 ] ) ) ) ; } </s>

Expand vector logical operation CODE ( AND , IOR , XOR ) in MODE with the given OPERANDS .


<s>
void
SystemZMCAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
)
const
{
MCFixupKind
Kind
=
Fixup
.
getKind
(
)
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
unsigned
Size
=
(
getFixupKindInfo
(
Kind
)
.
TargetSize
+
7
)
/
8
;
assert
(
Offset
+
Size
<=
DataSize
&&
"Invalid fixup offset!"
)
;
Value
=
extractBitsForFixup
(
Kind
,
Value
)
;
unsigned
ShiftValue
=
(
Size
*
8
)
8
;
for
(
unsigned
I
=
0
;
I
!=
Size
;
++
I
)
{
Data
[
Offset
+
I
]
|=
uint8_t
(
Value
>>
ShiftValue
)
;
ShiftValue
-=
8
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s>
bool
GCNTargetMachine
::
parseMachineFunctionInfo
(
const
yaml
::
MachineFunctionInfo
&
MFI_
,
PerFunctionMIParsingState
&
PFS
,
SMDiagnostic
&
Error
,
SMRange
&
SourceRange
)
const
{
const
yaml
::
SIMachineFunctionInfo
&
YamlMFI
=
reinterpret_cast
<
const
yaml
::
SIMachineFunctionInfo
&
>
(
MFI_
)
;
MachineFunction
&
MF
=
PFS
.
MF
;
SIMachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MFI
->
initializeBaseYamlFields
(
YamlMFI
)
;
auto
parseRegister
=
[
&
]
(
const
yaml
::
StringValue
&
RegName
,
unsigned
&
RegVal
)
{
if
(
parseNamedRegisterReference
(
PFS
,
RegVal
,
RegName
.
Value
,
Error
)
)
{
SourceRange
=
RegName
.
SourceRange
;
return
true
;
}
return
false
;
}
;
auto
diagnoseRegisterClass
=
[
&
]
(
const
yaml
::
StringValue
&
RegName
)
{
const
MemoryBuffer
&
Buffer
=
*
PFS
.
SM
->
getMemoryBuffer
(
PFS
.
SM
->
getMainFileID
(
)
)
;
Error
=
SMDiagnostic
(
*
PFS
.
SM
,
SMLoc
(
)
,
Buffer
.
getBufferIdentifier
(
)
,
1
,
RegName
.
Value
.
size
(
)
,
SourceMgr
::
DK_Error
,
"incorrect register class for field"
,
RegName
.
Value
,
,
)
;
SourceRange
=
RegName
.
SourceRange
;
return
true
;
}
;
if
(
parseRegister
(
YamlMFI
.
ScratchRSrcReg
,
MFI
->
ScratchRSrcReg
)
||
parseRegister
(
YamlMFI
.
ScratchWaveOffsetReg
,
MFI
->
ScratchWaveOffsetReg
)
||
parseRegister
(
YamlMFI
.
FrameOffsetReg
,
MFI
->
FrameOffsetReg
)
||
parseRegister
(
YamlMFI
.
StackPtrOffsetReg
,
MFI
->
StackPtrOffsetReg
)
)
return
true
;
if
(
MFI
->
ScratchRSrcReg
!=
AMDGPU
::
PRIVATE_RSRC_REG
&&
!
AMDGPU
::
SReg_128RegClass
.
contains
(
MFI
->
ScratchRSrcReg
)
)
{
return
diagnoseRegisterClass
(
YamlMFI
.
ScratchRSrcReg
)
;
}
if
(
MFI
->
ScratchWaveOffsetReg
!=
AMDGPU
::
SCRATCH_WAVE_OFFSET_REG
&&
!
AMDGPU
::
SGPR_32RegClass
.
contains
(
MFI
->
ScratchWaveOffsetReg
)
)
{
return
diagnoseRegisterClass
(
YamlMFI
.
ScratchWaveOffsetReg
)
;
}
if
(
MFI
->
FrameOffsetReg
!=
AMDGPU
::
FP_REG
&&
!
AMDGPU
::
SGPR_32RegClass
.
contains
(
MFI
->
FrameOffsetReg
)
)
{
return
diagnoseRegisterClass
(
YamlMFI
.
FrameOffsetReg
)
;
}
if
(
MFI
->
StackPtrOffsetReg
!=
AMDGPU
::
SP_REG
&&
!
AMDGPU
::
SGPR_32RegClass
.
contains
(
MFI
->
StackPtrOffsetReg
)
)
{
return
diagnoseRegisterClass
(
YamlMFI
.
StackPtrOffsetReg
)
;
}
return
false
;
}
</s>

Parse out the target 's MachineFunctionInfo from the YAML reprsentation .


<s> void aarch64_asm_output_external ( FILE * stream , tree decl , const char * name ) { default_elf_asm_output_external ( stream , decl , name ) ; aarch64_asm_output_variant_pcs ( stream , decl , name ) ; } </s>

Implement ASM_OUTPUT_EXTERNAL . Output .variant_pcs for undefined function symbol references .


<s> bool ia64_expand_vecint_minmax ( enum rtx_code code , machine_mode mode , rtx operands [ ] ) { rtx xops [ 6 ] ; if ( mode == V8QImode && ( code == UMIN || code == UMAX ) ) return false ; if ( mode == V4HImode && ( code == SMIN || code == SMAX ) ) return false ; if ( mode == V4HImode && code == UMAX ) { rtx x , tmp = gen_reg_rtx ( mode ) ; x = gen_rtx_US_MINUS ( mode , operands [ 1 ] , operands [ 2 ] ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , x ) ) ; emit_insn ( gen_addv4hi3 ( operands [ 0 ] , tmp , operands [ 2 ] ) ) ; return true ; } xops [ 0 ] = operands [ 0 ] ; xops [ 4 ] = xops [ 1 ] = operands [ 1 ] ; xops [ 5 ] = xops [ 2 ] = operands [ 2 ] ; switch ( code ) { case UMIN : code = LTU ; break ; case UMAX : code = GTU ; break ; case SMIN : code = LT ; break ; case SMAX : code = GT ; break ; default : gcc_unreachable ( ) ; } xops [ 3 ] = gen_rtx_fmt_ee ( code , VOIDmode , operands [ 1 ] , operands [ 2 ] ) ; ia64_expand_vecint_cmov ( xops ) ; return true ; } </s>

Emit an integral vector min or max operation . Return true if all done .


<s> static void aarch64_select_early_remat_modes ( sbitmap modes ) { for ( int i = 0 ; i < NUM_MACHINE_MODES ; ++ i ) if ( aarch64_sve_mode_p ( ( machine_mode ) i ) ) bitmap_set_bit ( modes , i ) ; } </s>


<s> RISCVSubtarget & RISCVSubtarget :: initializeSubtargetDependencies ( const Triple & TT , StringRef CPU , StringRef FS , StringRef ABIName ) { bool Is64Bit = TT . isArch64Bit ( ) ; std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) ) CPUName = Is64Bit ? "generic-rv64" : "generic-rv32" ; ParseSubtargetFeatures ( CPUName , CPUName , FS ) ; if ( Is64Bit ) { XLenVT = MVT :: i64 ; XLen = 64 ; } TargetABI = RISCVABI :: computeTargetABI ( TT , getFeatureBits ( ) , ABIName ) ; RISCVFeatures :: validate ( TT , getFeatureBits ( ) ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


"virtual function multiversioning not supported"

Generate the dispatching code body to dispatch multi-versioned function DECL . The target hook is called to process the `` target '' attributes and provide the code to dispatch the right function at run-time . NODE points to the dispatcher decl whose body will be created .


<s> const M680x0InstrInfo * getInstrInfo ( ) const { return Subtarget -> getInstrInfo ( ) ; } </s>


<s>
void
RISCVMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
verifyInstructionPredicates
(
MI
,
computeAvailableFeatures
(
STI
.
getFeatureBits
(
)
)
)
;
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
unsigned
Size
=
Desc
.
getSize
(
)
;
if
(
MI
.
getOpcode
(
)
==
RISCV
::
PseudoCALLReg
||
MI
.
getOpcode
(
)
==
RISCV
::
PseudoCALL
||
MI
.
getOpcode
(
)
==
RISCV
::
PseudoTAIL
||
MI
.
getOpcode
(
)
==
RISCV
::
PseudoJump
||
MI
.
getOpcode
(
)
==
RISCV
::
PseudoCCALLReg
||
MI
.
getOpcode
(
)
==
RISCV
::
PseudoCCALL
||
MI
.
getOpcode
(
)
==
RISCV
::
PseudoCTAIL
||
MI
.
getOpcode
(
)
==
RISCV
::
PseudoCJump
)
{
expandFunctionCall
(
MI
,
OS
,
Fixups
,
STI
)
;
MCNumEmitted
+=
2
;
return
;
}
if
(
MI
.
getOpcode
(
)
==
RISCV
::
PseudoAddTPRel
)
{
expandAddTPRel
(
MI
,
OS
,
Fixups
,
STI
)
;
MCNumEmitted
+=
1
;
return
;
}
if
(
MI
.
getOpcode
(
)
==
RISCV
::
PseudoCIncOffsetTPRel
)
{
expandCIncOffsetTPRel
(
MI
,
OS
,
Fixups
,
STI
)
;
MCNumEmitted
+=
1
;
return
;
}
switch
(
Size
)
{
default
:
llvm_unreachable
(
"Unhandled encodeInstruction length!"
)
;
case
2
:
{
uint16_t
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
support
::
endian
::
write
<
uint16_t
>
(
OS
,
Bits
,
support
::
little
)
;
break
;
}
case
4
:
{
uint32_t
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
support
::
endian
::
write
(
OS
,
Bits
,
support
::
little
)
;
break
;
}
}
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .

RISCV
RISCV
RISCV::PseudoCALLReg
RISCV::PseudoCALL
RISCV::PseudoTAIL
RISCV::PseudoJump
RISCV::PseudoCCALLReg
RISCV::PseudoCCALL
RISCV::PseudoCTAIL
RISCV::PseudoCJump
2
RISCV::PseudoAddTPRel
1
RISCV::PseudoCIncOffsetTPRel
1
"Unhandled encodeInstruction length!"
2
support::endian
support::little
4
support::endian
support::little


This method may be implemented by targets that want to run passes immediately before register allocation .


<s> Optional < MCFixupKind > X86AsmBackend :: getFixupKind ( StringRef Name ) const { if ( STI . getTargetTriple ( ) . isOSBinFormatELF ( ) ) { if ( STI . getTargetTriple ( ) . getArch ( ) == Triple :: x86_64 ) { if ( Name == "R_X86_64_NONE" ) return FK_NONE ; } else { if ( Name == "R_386_NONE" ) return FK_NONE ; } } return MCAsmBackend :: getFixupKind ( Name ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , int64_t NumBytes , bool Is64Bit , const TargetInstrInfo & TII ) { bool isSub = NumBytes < 0 ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; unsigned Opc = isSub ? getSUBriOpcode ( Is64Bit , Offset ) : getADDriOpcode ( Is64Bit , Offset ) ; uint64_t Chunk = ( 1LL << 31 ) - 1 ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( ThisVal ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> bool AMDGPUAsmParser :: isRegister ( const AsmToken & Token , const AsmToken & NextToken ) const { if ( Token . is ( AsmToken :: LBrac ) ) return true ; if ( ! Token . is ( AsmToken :: Identifier ) ) return false ; StringRef RegName = Token . getString ( ) ; for ( StringRef Reg : Registers ) { if ( RegName . startswith ( Reg ) ) { if ( Reg . size ( ) < RegName . size ( ) ) { unsigned RegNum ; if ( ! RegName . substr ( Reg . size ( ) ) . getAsInteger ( 10 , RegNum ) ) return true ; } else { if ( NextToken . is ( AsmToken :: LBrac ) ) return true ; } } } return getSpecialRegForName ( RegName ) ; } </s>

isRegister - Returns true if this is a normal register use/def slot .


<s>
void
StoreInitializer
::
print
(
raw_ostream
&
O
)
{
StringRef
Str
=
str
(
)
;
assert
(
Str
.
size
(
)
%
InitEltSize
==
0
)
;
if
(
InitEltSize
==
1
)
{
for
(
size_t
I
=
0
,
E
=
Str
.
size
(
)
;
I
!=
E
;
++
I
)
{
if
(
I
!=
0
)
O
<<
", "
;
O
<<
(
static_cast
<
int
>
(
Str
[
I
]
)
&
0xff
)
;
}
return
;
}
for
(
unsigned
I
=
0
,
E
=
Str
.
size
(
)
;
I
!=
E
;
I
+=
InitEltSize
)
{
if
(
I
!=
0
)
O
<<
", "
;
const
char
*
Ptr
=
&
Str
.
data
(
)
[
I
]
;
switch
(
InitEltSize
)
{
case
4
:
{
uint32_t
Tmp
;
std
::
memcpy
(
&
Tmp
,
Ptr
,
4
)
;
if
(
IsFPElt
)
printFloat
(
Tmp
,
O
)
;
else
O
<<
Tmp
;
break
;
}
case
8
:
{
uint64_t
Tmp
;
std
::
memcpy
(
&
Tmp
,
Ptr
,
8
)
;
if
(
IsFPElt
)
printDouble
(
Tmp
,
O
)
;
else
O
<<
Tmp
;
break
;
}
case
2
:
{
uint16_t
Tmp
;
std
::
memcpy
(
&
Tmp
,
Ptr
,
2
)
;
assert
(
!
IsFPElt
&&
"half not implemented"
)
;
O
<<
Tmp
;
break
;
}
default
:
llvm_unreachable
(
"Unhandled element size"
)
;
}
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
switch
(
(
unsigned
)
Kind
)
{
case
CAHP
::
fixup_cahp_hi6
:
{
const
static
MCFixupKindInfo
info
{
"fixup_cahp_hi6"
,
0
,
16
,
0
}
;
return
info
;
}
case
CAHP
::
fixup_cahp_lo10
:
{
const
static
MCFixupKindInfo
info
{
"fixup_cahp_lo10"
,
0
,
24
,
0
}
;
return
info
;
}
case
CAHP
::
fixup_cahp_pcrel_10
:
{
const
static
MCFixupKindInfo
info
{
"fixup_cahp_pcrel_10"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
;
return
info
;
}
case
CAHP
::
fixup_cahp_pcrel_11
:
{
const
static
MCFixupKindInfo
info
{
"fixup_cahp_pcrel_11"
,
5
,
11
,
MCFixupKindInfo
::
FKF_IsPCRel
}
;
return
info
;
}
default
:
llvm_unreachable
(
"Invalid kind!"
)
;
}
}
</s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"Patmos Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
static
MCSymbol
*
GetSymbolFromOperand
(
const
MachineOperand
&
MO
,
AsmPrinter
&
AP
)
{
MCContext
&
Ctx
=
AP
.
OutContext
;
SmallString
<
128
>
Name
;
if
(
!
MO
.
isGlobal
(
)
)
{
assert
(
MO
.
isSymbol
(
)
&&
"Isn't a symbol reference"
)
;
Name
+=
AP
.
MAI
->
getGlobalPrefix
(
)
;
Name
+=
MO
.
getSymbolName
(
)
;
}
else
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
bool
isImplicitlyPrivate
=
false
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_DARWIN_STUB
||
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
)
isImplicitlyPrivate
=
true
;
AP
.
Mang
->
getNameWithPrefix
(
Name
,
GV
,
isImplicitlyPrivate
)
;
}
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_DARWIN_STUB
)
{
Name
+=
"$stub"
;
MCSymbol
*
Sym
=
Ctx
.
GetOrCreateSymbol
(
Name
.
str
(
)
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
getMachOMMI
(
AP
)
.
getFnStubEntry
(
Sym
)
;
if
(
StubSym
.
getPointer
(
)
)
return
Sym
;
if
(
MO
.
isGlobal
(
)
)
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
Mang
->
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
else
{
Name
.
erase
(
Name
.
end
(
)
5
,
Name
.
end
(
)
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
Ctx
.
GetOrCreateSymbol
(
Name
.
str
(
)
)
,
false
)
;
}
return
Sym
;
}
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
{
Name
+=
"$non_lazy_ptr"
;
MCSymbol
*
Sym
=
Ctx
.
GetOrCreateSymbol
(
Name
.
str
(
)
)
;
MachineModuleInfoMachO
&
MachO
=
getMachOMMI
(
AP
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_HIDDEN_FLAG
)
MachO
.
getHiddenGVStubEntry
(
Sym
)
:
MachO
.
getGVStubEntry
(
Sym
)
;
if
(
StubSym
.
getPointer
(
)
==
0
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
Mang
->
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
return
Sym
;
}
return
Ctx
.
GetOrCreateSymbol
(
Name
.
str
(
)
)
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .