<s> bool PPCTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , ( Subtarget . isSVR4ABI ( ) && CallConv == CallingConv :: Cold ) ? RetCC_PPC_Cold : RetCC_PPC ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s>
unsigned
NyuziMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
assert
(
MO
.
isExpr
(
)
)
;
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
if
(
const
NyuziMCExpr
*
McExpr
=
dyn_cast
<
NyuziMCExpr
>
(
Expr
)
)
{
switch
(
McExpr
->
getKind
(
)
)
{
case
NyuziMCExpr
::
VK_Nyuzi_ABS_HI
:
Fixups
.
push_back
(
MCFixup
::
create
(
0
,
MO
.
getExpr
(
)
,
MCFixupKind
(
Nyuzi
::
fixup_Nyuzi_HI19
)
)
)
;
break
;
case
NyuziMCExpr
::
VK_Nyuzi_ABS_LO
:
Fixups
.
push_back
(
MCFixup
::
create
(
0
,
MO
.
getExpr
(
)
,
MCFixupKind
(
Nyuzi
::
fixup_Nyuzi_IMM_LO13
)
)
)
;
break
;
default
:
llvm_unreachable
(
"Unknown fixup type"
)
;
}
}
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> bool Thumb2SizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { if ( PredicateFtor && ! PredicateFtor ( MF . getFunction ( ) ) ) return false ; STI = & MF . getSubtarget < ARMSubtarget > ( ) ; if ( STI -> isThumb1Only ( ) || STI -> prefers32BitThumb ( ) ) return false ; TII = static_cast < const Thumb2InstrInfo * > ( STI -> getInstrInfo ( ) ) ; OptimizeSize = MF . getFunction ( ) . hasOptSize ( ) ; MinimizeSize = STI -> hasMinSize ( ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; ReversePostOrderTraversal < MachineFunction * > RPOT ( & MF ) ; bool Modified = false ; for ( MachineBasicBlock * MBB : RPOT ) Modified |= ReduceMBB ( * MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s>
const
char
*
emit_fusion_gpr_load
(
rtx
target
,
rtx
mem
)
{
rtx
addis_value
;
rtx
addr
;
rtx
load_offset
;
const
char
*
load_str
=
;
const
char
*
mode_name
=
;
machine_mode
mode
;
if
(
GET_CODE
(
mem
)
==
ZERO_EXTEND
)
mem
=
XEXP
(
mem
,
0
)
;
gcc_assert
(
REG_P
(
target
)
&&
MEM_P
(
mem
)
)
;
addr
=
XEXP
(
mem
,
0
)
;
fusion_split_address
(
addr
,
&
addis_value
,
&
load_offset
)
;
mode
=
GET_MODE
(
mem
)
;
switch
(
mode
)
{
case
QImode
:
mode_name
=
"char"
;
load_str
=
"lbz"
;
break
;
case
HImode
:
mode_name
=
"short"
;
load_str
=
"lhz"
;
break
;
case
SImode
:
case
SFmode
:
mode_name
=
(
mode
==
SFmode
)
"float"
:
"int"
;
load_str
=
"lwz"
;
break
;
case
DImode
:
case
DFmode
:
gcc_assert
(
TARGET_POWERPC64
)
;
mode_name
=
(
mode
==
DFmode
)
"double"
:
"long"
;
load_str
=
"ld"
;
break
;
default
:
fatal_insn
(
"Bad GPR fusion"
,
gen_rtx_SET
(
target
,
mem
)
)
;
}
emit_fusion_addis
(
target
,
addis_value
,
"gpr load fusion"
,
mode_name
)
;
emit_fusion_load_store
(
target
,
target
,
load_offset
,
load_str
)
;
return
""
;
}
</s>

Return a string to fuse an addis instruction with a gpr load to the same register that we loaded up the addis instruction . The address that is used is the logical address that was formed during peephole2 : ( lo_sum ( high ) ( low-part ) ) The code is complicated , so we call output_asm_insn directly , and just return `` '' .

rs6000
0
0
"char"
"lbz"
"short"
"lhz"
"float"
"int"
"lwz"
"double"
"long"
"ld"
"Bad GPR fusion"
"gpr load fusion"
""


<s> const MCPhysReg * PPCRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const PPCSubtarget & Subtarget = MF -> getSubtarget < PPCSubtarget > ( ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: AnyReg ) { if ( Subtarget . hasVSX ( ) ) return CSR_64_AllRegs_VSX_SaveList ; if ( Subtarget . hasAltivec ( ) ) return CSR_64_AllRegs_Altivec_SaveList ; return CSR_64_AllRegs_SaveList ; } if ( Subtarget . isDarwinABI ( ) ) return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_SaveList : CSR_Darwin64_SaveList ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_SaveList : CSR_Darwin32_SaveList ) ; if ( TM . isPPC64 ( ) && MF -> getInfo < PPCFunctionInfo > ( ) -> isSplitCSR ( ) ) return CSR_SRV464_TLS_PE_SaveList ; bool SaveR2 = MF -> getRegInfo ( ) . isAllocatable ( PPC :: X2 ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: Cold ) { if ( TM . isPPC64 ( ) ) { if ( Subtarget . hasAltivec ( ) ) return SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList : CSR_SVR64_ColdCC_Altivec_SaveList ; return SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList : CSR_SVR64_ColdCC_SaveList ; } if ( Subtarget . hasAltivec ( ) ) return CSR_SVR32_ColdCC_Altivec_SaveList ; else if ( Subtarget . hasSPE ( ) ) return CSR_SVR32_ColdCC_SPE_SaveList ; return CSR_SVR32_ColdCC_SaveList ; } if ( TM . isPPC64 ( ) ) { if ( Subtarget . hasAltivec ( ) ) return SaveR2 ? CSR_SVR464_R2_Altivec_SaveList : CSR_SVR464_Altivec_SaveList ; return SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList ; } if ( Subtarget . hasAltivec ( ) ) return CSR_SVR432_Altivec_SaveList ; else if ( Subtarget . hasSPE ( ) ) return CSR_SVR432_SPE_SaveList ; return CSR_SVR432_SaveList ; } </s>

PowerPC PPC PPC PPC PPC PPC PPC PPC::X2 PPC PPC


<s> static void nds32_expand_to_rtl_hook ( void ) { cfun -> machine -> strict_aligned_p = 1 ; } </s>

This function will be called just before expansion into rtl .


<s> bool SystemZInstrInfo :: isUnpredicatedTerminator ( const MachineInstr * MI ) const { const TargetInstrDesc & TID = MI -> getDesc ( ) ; if ( ! TID . isTerminator ( ) ) return false ; if ( TID . isBranch ( ) && ! TID . isBarrier ( ) ) return true ; if ( ! TID . isPredicable ( ) ) return true ; return ! isPredicated ( MI ) ; } </s>

Returns true if the instruction is a terminator instruction that has not been predicated .


<s> void dump ( ) const { print ( dbgs ( ) ) ; } </s>

Dump the plan to stderr ( for debugging ) .


<s> static char * locate_lib ( char * lib_name , char * path_val ) { int lib_len = strlen ( lib_name ) ; char * eptr , * sptr ; for ( sptr = path_val ; * sptr ; sptr = eptr ) { char * buf , * ptr ; while ( * sptr == PATH_SEPARATOR ) sptr ++ ; eptr = strchr ( sptr , PATH_SEPARATOR ) ; if ( eptr == 0 ) eptr = strchr ( sptr , 0 ) ; buf = alloca ( ( eptr - sptr ) + lib_len + 4 + 2 ) ; strncpy ( buf , sptr , eptr - sptr ) ; buf [ eptr - sptr ] = 0 ; strcat ( buf , "/" ) ; strcat ( buf , lib_name ) ; ptr = strchr ( buf , 0 ) ; if ( debug || staticp ) { strcpy ( ptr , ".a" ) ; if ( is_regular_file ( buf ) ) return xstrdup ( to_host_file_spec ( buf ) ) ; strcpy ( ptr , ".olb" ) ; if ( is_regular_file ( buf ) ) return xstrdup ( to_host_file_spec ( buf ) ) ; strcpy ( ptr , ".exe" ) ; if ( is_regular_file ( buf ) ) return xstrdup ( to_host_file_spec ( buf ) ) ; } else { strcpy ( ptr , ".exe" ) ; if ( is_regular_file ( buf ) ) return xstrdup ( to_host_file_spec ( buf ) ) ; strcpy ( ptr , ".a" ) ; if ( is_regular_file ( buf ) ) return xstrdup ( to_host_file_spec ( buf ) ) ; strcpy ( ptr , ".olb" ) ; if ( is_regular_file ( buf ) ) return xstrdup ( to_host_file_spec ( buf ) ) ; } } return 0 ; } </s>

Locate library LIB_NAME on the library path .


"%qs attribute only applies to functions"

Handle an `` interrupt '' or `` isr '' attribute ; arguments as in struct attribute_spec.handler .


<s> Align ARMTargetLowering :: getABIAlignmentForCallingConv ( Type * ArgTy , DataLayout DL ) const { const Align ABITypeAlign = DL . getABITypeAlign ( ArgTy ) ; if ( ! ArgTy -> isVectorTy ( ) ) return ABITypeAlign ; return std :: min ( ABITypeAlign , DL . getStackAlignment ( ) ) ; } </s>

Return the correct alignment for the current calling convention .


<s>
void
XtensaInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
llvm_unreachable
(
"Unimplemented operand"
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s>
std
::
string
AMDGPUIntrinsicInfo
::
getName
(
unsigned
int
IntrID
,
Type
*
*
Tys
,
unsigned
int
numTys
)
const
{
static
const
char
*
const
names
[
]
=
{
}
;
if
(
IntrID
<
Intrinsic
::
num_intrinsics
)
{
return
nullptr
;
}
assert
(
IntrID
<
AMDGPUIntrinsic
::
num_AMDGPU_intrinsics
&&
"Invalid intrinsic ID"
)
;
std
::
string
Result
(
names
[
IntrID
Intrinsic
::
num_intrinsics
]
)
;
return
Result
;
}
</s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> static void arc_setup_incoming_varargs ( cumulative_args_t args_so_far , const function_arg_info & arg , int * pretend_size , int no_rtl ) { int first_anon_arg ; CUMULATIVE_ARGS next_cum ; next_cum = * get_cumulative_args ( args_so_far ) ; arc_function_arg_advance ( pack_cumulative_args ( & next_cum ) , arg ) ; first_anon_arg = next_cum ; if ( FUNCTION_ARG_REGNO_P ( first_anon_arg ) ) { int first_reg_offset = first_anon_arg ; if ( ! no_rtl ) { rtx regblock = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , arg_pointer_rtx , FIRST_PARM_OFFSET ( 0 ) ) ) ; move_block_from_reg ( first_reg_offset , regblock , MAX_ARC_PARM_REGS - first_reg_offset ) ; } * pretend_size = ( ( MAX_ARC_PARM_REGS - first_reg_offset ) * UNITS_PER_WORD ) ; } } </s>

Do any needed setup for a variadic function . For the ARC , we must create a register parameter block , and then copy any anonymous arguments in registers to memory . CUM has not been updated for the last named argument which has type TYPE and mode MODE , and we rely on this fact .


<s> EVT MBlazeTargetLowering :: getSetCCResultType ( LLVMContext & , EVT ) const { return MVT :: i32 ; } </s>

Return the value type to use for ISD : :SETCC .


<s>
bool
X86IntelAsmPrinter
::
doInitialization
(
Module
&
M
)
{
bool
Result
=
AsmPrinter
::
doInitialization
(
M
)
;
Mang
->
markCharUnacceptable
(
'.'
)
;
O
<<
"\t.686\n\t.model flat\n\n"
;
for
(
Module
::
iterator
I
=
M
.
begin
(
)
,
E
=
M
.
end
(
)
;
I
!=
E
;
++
I
)
if
(
I
->
isDeclaration
(
)
)
{
std
::
string
Name
=
Mang
->
getValueName
(
I
)
;
decorateName
(
Name
,
I
)
;
O
<<
"\textern "
;
if
(
I
->
hasDLLImportLinkage
(
)
)
{
O
<<
"__imp_"
;
}
O
<<
Name
<<
":near\n"
;
}
for
(
Module
::
const_global_iterator
I
=
M
.
global_begin
(
)
,
E
=
M
.
global_end
(
)
;
I
!=
E
;
++
I
)
{
if
(
I
->
isDeclaration
(
)
)
{
std
::
string
Name
=
Mang
->
getValueName
(
I
)
;
O
<<
"\textern "
;
if
(
I
->
hasDLLImportLinkage
(
)
)
{
O
<<
"__imp_"
;
}
O
<<
Name
<<
":byte\n"
;
}
}
return
Result
;
}
</s>

Set up the AsmPrinter when we are working on a new module .


<s> static tree avr_builtin_decl ( unsigned id , bool initialize_p ATTRIBUTE_UNUSED ) { if ( id < AVR_BUILTIN_COUNT ) return avr_bdesc [ id ] . fndecl ; return error_mark_node ; } </s>


<s> bool X86WinAllocaExpander :: runOnMachineFunction ( MachineFunction & MF ) { if ( ! MF . getInfo < X86MachineFunctionInfo > ( ) -> hasWinAlloca ( ) ) return false ; MRI = & MF . getRegInfo ( ) ; STI = & MF . getSubtarget < X86Subtarget > ( ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; StackPtr = TRI -> getStackRegister ( ) ; SlotSize = TRI -> getSlotSize ( ) ; StackProbeSize = 4096 ; if ( MF . getFunction ( ) . hasFnAttribute ( "stack-probe-size" ) ) { MF . getFunction ( ) . getFnAttribute ( "stack-probe-size" ) . getValueAsString ( ) . getAsInteger ( 0 , StackProbeSize ) ; } NoStackArgProbe = MF . getFunction ( ) . hasFnAttribute ( "no-stack-arg-probe" ) ; if ( NoStackArgProbe ) StackProbeSize = INT64_MAX ; LoweringMap Lowerings ; computeLowerings ( MF , Lowerings ) ; for ( auto & P : Lowerings ) lower ( P . first , P . second ) ; return true ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> unsigned MBlazeInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == MBlaze :: SWI ) { if ( ( MI -> getOperand ( 2 ) . isFI ( ) ) && ( MI -> getOperand ( 1 ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( 1 ) ) ) ) { FrameIndex = MI -> getOperand ( 2 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


Return > = 0 if there is an unused call-clobbered register available for the entire function .


<s> static void nds32_group_insns ( rtx sethi ) { df_ref def_record , use_record ; df_link * link ; rtx_insn * use_insn = NULL ; rtx group_id ; def_record = DF_INSN_DEFS ( sethi ) ; for ( link = DF_REF_CHAIN ( def_record ) ; link ; link = link -> next ) { if ( ! DF_REF_INSN_INFO ( link -> ref ) ) continue ; use_insn = DF_REF_INSN ( link -> ref ) ; if ( ! dominated_by_p ( CDI_DOMINATORS , BLOCK_FOR_INSN ( use_insn ) , BLOCK_FOR_INSN ( sethi ) ) ) return ; use_record = DF_INSN_USES ( use_insn ) ; if ( DF_REF_CHAIN ( use_record ) && DF_REF_CHAIN ( use_record ) -> next ) return ; if ( ! active_insn_p ( use_insn ) ) return ; if ( ! ( recog_memoized ( use_insn ) == CODE_FOR_lo_sum || nds32_symbol_load_store_p ( use_insn ) || ( nds32_reg_base_load_store_p ( use_insn ) && ! nds32_sp_base_or_plus_load_store_p ( use_insn ) ) ) ) return ; } group_id = GEN_INT ( relax_group_id ) ; emit_insn_before ( gen_relax_group ( group_id ) , sethi ) ; for ( link = DF_REF_CHAIN ( def_record ) ; link ; link = link -> next ) { if ( ! DF_REF_INSN_INFO ( link -> ref ) ) continue ; use_insn = DF_REF_INSN ( link -> ref ) ; if ( active_insn_p ( use_insn ) ) emit_insn_before ( gen_relax_group ( group_id ) , use_insn ) ; } relax_group_id ++ ; } </s>

Group the relax candidates with group id .


<s> unsigned OptimizePICCall :: getReg ( const Value * Entry ) { unsigned Reg = ScopedHT . lookup ( Entry ) . second ; assert ( Reg ) ; return Reg ; } </s>

Returns the register associated with this edge .


<s> const char * MipsTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case MipsISD :: JmpLink : return "MipsISD::JmpLink" ; case MipsISD :: Hi : return "MipsISD::Hi" ; case MipsISD :: Lo : return "MipsISD::Lo" ; case MipsISD :: GPRel : return "MipsISD::GPRel" ; case MipsISD :: ThreadPointer : return "MipsISD::ThreadPointer" ; case MipsISD :: Ret : return "MipsISD::Ret" ; case MipsISD :: FPBrcond : return "MipsISD::FPBrcond" ; case MipsISD :: FPCmp : return "MipsISD::FPCmp" ; case MipsISD :: CMovFP_T : return "MipsISD::CMovFP_T" ; case MipsISD :: CMovFP_F : return "MipsISD::CMovFP_F" ; case MipsISD :: FPRound : return "MipsISD::FPRound" ; case MipsISD :: MAdd : return "MipsISD::MAdd" ; case MipsISD :: MAddu : return "MipsISD::MAddu" ; case MipsISD :: MSub : return "MipsISD::MSub" ; case MipsISD :: MSubu : return "MipsISD::MSubu" ; case MipsISD :: DivRem : return "MipsISD::DivRem" ; case MipsISD :: DivRemU : return "MipsISD::DivRemU" ; case MipsISD :: BuildPairF64 : return "MipsISD::BuildPairF64" ; case MipsISD :: ExtractElementF64 : return "MipsISD::ExtractElementF64" ; case MipsISD :: Wrapper : return "MipsISD::Wrapper" ; case MipsISD :: DynAlloc : return "MipsISD::DynAlloc" ; case MipsISD :: Sync : return "MipsISD::Sync" ; case MipsISD :: Ext : return "MipsISD::Ext" ; case MipsISD :: Ins : return "MipsISD::Ins" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific

Mips Mips MipsISD::JmpLink "MipsISD::JmpLink" MipsISD::Hi "MipsISD::Hi" MipsISD::Lo "MipsISD::Lo" MipsISD::GPRel "MipsISD::GPRel" MipsISD::ThreadPointer "MipsISD::ThreadPointer" MipsISD::Ret "MipsISD::Ret" MipsISD::FPBrcond "MipsISD::FPBrcond" MipsISD::FPCmp "MipsISD::FPCmp" MipsISD::CMovFP_T "MipsISD::CMovFP_T" MipsISD::CMovFP_F "MipsISD::CMovFP_F" MipsISD::FPRound "MipsISD::FPRound" MipsISD::MAdd "MipsISD::MAdd" MipsISD::MAddu "MipsISD::MAddu" MipsISD::MSub "MipsISD::MSub" MipsISD::MSubu "MipsISD::MSubu" MipsISD::DivRem "MipsISD::DivRem" MipsISD::DivRemU "MipsISD::DivRemU" MipsISD::BuildPairF64 "MipsISD::BuildPairF64" MipsISD::ExtractElementF64 "MipsISD::ExtractElementF64" MipsISD::Wrapper "MipsISD::Wrapper" MipsISD::DynAlloc "MipsISD::DynAlloc" MipsISD::Sync "MipsISD::Sync" MipsISD::Ext "MipsISD::Ext" MipsISD::Ins "MipsISD::Ins"


<s> virtual bool isConditionalBranch ( const MCInst & Inst ) const { if ( Inst . getOpcode ( ) == AArch64 :: Bcc && Inst . getOperand ( 0 ) . getImm ( ) == A64CC :: AL ) return false ; return MCInstrAnalysis :: isConditionalBranch ( Inst ) ; } </s>

Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block .


<s> bool SystemZTDCPass :: runOnFunction ( Function & F ) { ConvertedInsts . clear ( ) ; LogicOpsWorklist . clear ( ) ; PossibleJunk . clear ( ) ; for ( auto & I : instructions ( F ) ) { if ( I . getOpcode ( ) == Instruction :: FCmp ) convertFCmp ( cast < CmpInst > ( I ) ) ; else if ( I . getOpcode ( ) == Instruction :: ICmp ) convertICmp ( cast < CmpInst > ( I ) ) ; } if ( ConvertedInsts . empty ( ) ) return false ; while ( ! LogicOpsWorklist . empty ( ) ) { BinaryOperator * Op = LogicOpsWorklist . back ( ) ; LogicOpsWorklist . pop_back ( ) ; if ( ConvertedInsts . count ( dyn_cast < Instruction > ( Op -> getOperand ( 0 ) ) ) && ConvertedInsts . count ( dyn_cast < Instruction > ( Op -> getOperand ( 1 ) ) ) && ! ConvertedInsts . count ( Op ) ) convertLogicOp ( * Op ) ; } Module & M = * F . getParent ( ) ; auto & Ctx = M . getContext ( ) ; Value * Zero32 = ConstantInt :: get ( Type :: getInt32Ty ( Ctx ) , 0 ) ; bool MadeChange = false ; for ( auto & It : reverse ( ConvertedInsts ) ) { Instruction * I = It . first ; Value * V ; int Mask ; bool Worthy ; std :: tie ( V , Mask , Worthy ) = It . second ; if ( ! I -> user_empty ( ) ) { if ( ! Worthy ) continue ; Function * TDCFunc = Intrinsic :: getDeclaration ( & M , Intrinsic :: s390_tdc , V -> getType ( ) ) ; IRBuilder < > IRB ( I ) ; Value * MaskVal = ConstantInt :: get ( Type :: getInt64Ty ( Ctx ) , Mask ) ; Instruction * TDC = IRB . CreateCall ( TDCFunc , { V , MaskVal } ) ; Value * ICmp = IRB . CreateICmp ( CmpInst :: ICMP_NE , TDC , Zero32 ) ; I -> replaceAllUsesWith ( ICmp ) ; } I -> eraseFromParent ( ) ; MadeChange = true ; } if ( ! MadeChange ) return false ; for ( auto * I : PossibleJunk ) if ( I -> user_empty ( ) ) I -> eraseFromParent ( ) ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> unsigned MandarinInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { MI -> dump ( ) ; return 0 ; } </s>


<s> bool SIInsertSkips :: runOnMachineFunction ( MachineFunction & MF ) { const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; SkipThreshold = SkipThresholdFlag ; MachineBasicBlock * EmptyMBBAtEnd = nullptr ; SmallVector < MachineInstr * , 4 > KillInstrs ; bool MadeChange = false ; for ( MachineBasicBlock & MBB : MF ) { MachineBasicBlock :: iterator I , Next ; for ( I = MBB . begin ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; switch ( MI . getOpcode ( ) ) { case AMDGPU :: SI_MASK_BRANCH : MadeChange |= skipMaskBranch ( MI , MBB ) ; break ; case AMDGPU :: S_BRANCH : if ( MBB . isLayoutSuccessor ( MI . getOperand ( 0 ) . getMBB ( ) ) ) { assert ( & MI == & MBB . back ( ) ) ; MI . eraseFromParent ( ) ; MadeChange = true ; } break ; case AMDGPU :: SI_KILL_F32_COND_IMM_TERMINATOR : case AMDGPU :: SI_KILL_I1_TERMINATOR : { MadeChange = true ; bool CanKill = kill ( MI ) ; if ( CanKill && MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: AMDGPU_PS && dominatesAllReachable ( MBB ) ) { KillInstrs . push_back ( & MI ) ; } else { MI . eraseFromParent ( ) ; } break ; } case AMDGPU :: SI_RETURN_TO_EPILOG : assert ( ! MF . getInfo < SIMachineFunctionInfo > ( ) -> returnsVoid ( ) ) ; if ( & MBB != & MF . back ( ) || & MI != & MBB . back ( ) ) { if ( ! EmptyMBBAtEnd ) { EmptyMBBAtEnd = MF . CreateMachineBasicBlock ( ) ; MF . insert ( MF . end ( ) , EmptyMBBAtEnd ) ; } MBB . addSuccessor ( EmptyMBBAtEnd ) ; BuildMI ( MBB , & MI , MI . getDebugLoc ( ) , TII -> get ( AMDGPU :: S_BRANCH ) ) . addMBB ( EmptyMBBAtEnd ) ; MI . eraseFromParent ( ) ; MDT -> getBase ( ) . insertEdge ( & MBB , EmptyMBBAtEnd ) ; } break ; case AMDGPU :: S_CBRANCH_VCCZ : case AMDGPU :: S_CBRANCH_VCCNZ : MadeChange |= optimizeVccBranch ( MI ) ; break ; default : break ; } } } for ( MachineInstr * Kill : KillInstrs ) { skipIfDead ( * Kill -> getParent ( ) , std :: next ( Kill -> getIterator ( ) ) , Kill -> getDebugLoc ( ) ) ; Kill -> eraseFromParent ( ) ; } KillInstrs . clear ( ) ; return MadeChange ; } </s>

runOnMachineFunction - Emit the function body .


<s> PPCTargetLowering :: ConstraintType PPCTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'b' : case 'r' : case 'f' : case 'd' : case 'v' : case 'y' : return C_RegisterClass ; case 'Z' : return C_Memory ; } } else if ( Constraint == "wc" ) { return C_RegisterClass ; } else if ( Constraint == "wa" || Constraint == "wd" || Constraint == "wf" || Constraint == "ws" ) { return C_RegisterClass ; } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .

PowerPC PPC PPC 1 0 "wc" "wa" "wd" "wf" "ws"


<s>
static
void
visium_option_override
(
void
)
{
if
(
flag_pic
==
1
)
warning
(
OPT_fpic
,
"%<-fpic%> is not supported"
)
;
if
(
flag_pic
==
2
)
warning
(
OPT_fPIC
,
"%<-fPIC%> is not supported"
)
;
target_flags
|=
MASK_MCM
;
if
(
(
target_flags_explicit
&
MASK_FPU
)
==
0
)
target_flags
|=
MASK_FPU
;
if
(
(
target_flags_explicit
&
MASK_SV_MODE
)
==
0
)
target_flags
|=
MASK_SV_MODE
;
if
(
visium_cpu_and_features
==
PROCESSOR_GR6
)
{
target_flags
|=
MASK_BMI
;
if
(
target_flags
&
MASK_FPU
)
target_flags
|=
MASK_FPU_IEEE
;
}
if
(
!
OPTION_SET_P
(
visium_cpu
)
)
visium_cpu
=
visium_cpu_and_features
;
if
(
flag_align_functions
&&
!
str_align_functions
)
{
if
(
visium_cpu
==
PROCESSOR_GR6
)
str_align_functions
=
"64"
;
else
str_align_functions
=
"256"
;
SET_OPTION_IF_UNSET
(
&
global_options
,
&
global_options_set
,
param_inline_unit_growth
,
100
)
;
}
if
(
flag_align_loops
&&
!
str_align_loops
)
{
if
(
visium_cpu
==
PROCESSOR_GR6
)
str_align_loops
=
"64"
;
else
{
str_align_loops
=
"256:32:8"
;
}
}
if
(
flag_align_jumps
&&
!
str_align_jumps
)
{
if
(
visium_cpu
==
PROCESSOR_GR6
)
str_align_jumps
=
"64"
;
else
str_align_jumps
=
"8"
;
}
}
</s>


<s> void sparc_emit_fixunsdi ( rtx * operands , enum machine_mode mode ) { rtx neglab , donelab , i0 , i1 , f0 , in , out , limit ; out = operands [ 0 ] ; in = force_reg ( mode , operands [ 1 ] ) ; neglab = gen_label_rtx ( ) ; donelab = gen_label_rtx ( ) ; i0 = gen_reg_rtx ( DImode ) ; i1 = gen_reg_rtx ( DImode ) ; limit = gen_reg_rtx ( mode ) ; f0 = gen_reg_rtx ( mode ) ; emit_move_insn ( limit , CONST_DOUBLE_FROM_REAL_VALUE ( REAL_VALUE_ATOF ( "9223372036854775808.0" , mode ) , mode ) ) ; emit_cmp_and_jump_insns ( in , limit , GE , NULL_RTX , mode , 0 , neglab ) ; emit_insn ( gen_rtx_SET ( VOIDmode , out , gen_rtx_FIX ( DImode , gen_rtx_FIX ( mode , in ) ) ) ) ; emit_jump_insn ( gen_jump ( donelab ) ) ; emit_barrier ( ) ; emit_label ( neglab ) ; emit_insn ( gen_rtx_SET ( VOIDmode , f0 , gen_rtx_MINUS ( mode , in , limit ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , i0 , gen_rtx_FIX ( DImode , gen_rtx_FIX ( mode , f0 ) ) ) ) ; emit_insn ( gen_movdi ( i1 , const1_rtx ) ) ; emit_insn ( gen_ashldi3 ( i1 , i1 , GEN_INT ( 63 ) ) ) ; emit_insn ( gen_xordi3 ( out , i0 , i1 ) ) ; emit_label ( donelab ) ; } </s>

Generate an FP to unsigned DImode conversion . This is the same code optabs would emit if we did n't have TFmode patterns .


<s> bool TMS320C64XTargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( TMS320C64XCreateInstSelector ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> const uint32_t * SIRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { switch ( CC ) { case CallingConv :: C : case CallingConv :: Fast : case CallingConv :: Cold : return ST . hasGFX90AInsts ( ) ? CSR_AMDGPU_HighRegs_With_AGPRs_RegMask : CSR_AMDGPU_HighRegs_RegMask ; case CallingConv :: AMDGPU_Gfx : return ST . hasGFX90AInsts ( ) ? CSR_AMDGPU_SI_Gfx_With_AGPRs_RegMask : CSR_AMDGPU_SI_Gfx_RegMask ; default : return nullptr ; } } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"WebAssembly CFG Stackify"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool mayAlias ( const MachineFrameInfo * ) const override { return false ; } </s>

Returns true if this instruction 's memory access aliases the memory access of Other .


"Hexagon generate \"extract\" instructions"


<s> unsigned size ( ) const { return Seq . size ( ) ; } </s>

The number of name/type pairs is returned .


<s> bool msp430_op_not_in_high_mem ( rtx op ) { rtx op0 ; if ( ! TARGET_LARGE || ! MEM_P ( op ) ) return true ; op0 = XEXP ( op , 0 ) ; if ( SYMBOL_REF_P ( op0 ) && ( SYMBOL_REF_FLAGS ( op0 ) & SYMBOL_FLAG_LOW_MEM ) ) return true ; if ( msp430_check_plus_not_high_mem ( op0 ) || ( ( GET_CODE ( op0 ) == CONST ) && msp430_check_plus_not_high_mem ( XEXP ( op0 , 0 ) ) ) ) return true ; if ( ( CONST_INT_P ( op0 ) && ( IN_RANGE ( INTVAL ( op0 ) , 0 , ( 1 << 16 ) - 1 ) ) ) ) return true ; return false ; } </s>

Determine whether an RTX is definitely not a MEM referencing an address in the upper memory region . Returns true if we 've decided the address will be in the lower memory region , or the RTX is not a MEM . Returns false otherwise . The Ys constraint will catch ( mem ( plus ( const/reg ) ) but we catch cases involving a symbol_ref here .


<s> bool SystemZMCAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { for ( uint64_t I = 0 ; I != Count ; ++ I ) OS << '\x7' ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s>
Value
*
PPCTargetLowering
::
emitMaskedAtomicCmpXchgIntrinsic
(
IRBuilderBase
&
Builder
,
AtomicCmpXchgInst
*
CI
,
Value
*
AlignedAddr
,
Value
*
CmpVal
,
Value
*
NewVal
,
Value
*
Mask
,
AtomicOrdering
Ord
)
const
{
assert
(
EnableQuadwordAtomics
&&
Subtarget
.
hasQuadwordAtomics
(
)
&&
"Only support quadword now"
)
;
Module
*
M
=
Builder
.
GetInsertBlock
(
)
->
getParent
(
)
->
getParent
(
)
;
Type
*
ValTy
=
AlignedAddr
->
getType
(
)
->
getPointerElementType
(
)
;
assert
(
ValTy
->
getPrimitiveSizeInBits
(
)
==
128
)
;
Function
*
IntCmpXchg
=
Intrinsic
::
getDeclaration
(
M
,
Intrinsic
::
ppc_cmpxchg_i128
)
;
Type
*
Int64Ty
=
Type
::
getInt64Ty
(
M
->
getContext
(
)
)
;
Value
*
CmpLo
=
Builder
.
CreateTrunc
(
CmpVal
,
Int64Ty
,
"cmp_lo"
)
;
Value
*
CmpHi
=
Builder
.
CreateTrunc
(
Builder
.
CreateLShr
(
CmpVal
,
64
)
,
Int64Ty
,
"cmp_hi"
)
;
Value
*
NewLo
=
Builder
.
CreateTrunc
(
NewVal
,
Int64Ty
,
"new_lo"
)
;
Value
*
NewHi
=
Builder
.
CreateTrunc
(
Builder
.
CreateLShr
(
NewVal
,
64
)
,
Int64Ty
,
"new_hi"
)
;
Value
*
Addr
=
Builder
.
CreateBitCast
(
AlignedAddr
,
Type
::
getInt8PtrTy
(
M
->
getContext
(
)
)
)
;
emitLeadingFence
(
Builder
,
CI
,
Ord
)
;
Value
*
LoHi
=
Builder
.
CreateCall
(
IntCmpXchg
,
{
Addr
,
CmpLo
,
CmpHi
,
NewLo
,
NewHi
}
)
;
emitTrailingFence
(
Builder
,
CI
,
Ord
)
;
Value
*
Lo
=
Builder
.
CreateExtractValue
(
LoHi
,
0
,
"lo"
)
;
Value
*
Hi
=
Builder
.
CreateExtractValue
(
LoHi
,
1
,
"hi"
)
;
Lo
=
Builder
.
CreateZExt
(
Lo
,
ValTy
,
"lo64"
)
;
Hi
=
Builder
.
CreateZExt
(
Hi
,
ValTy
,
"hi64"
)
;
return
Builder
.
CreateOr
(
Lo
,
Builder
.
CreateShl
(
Hi
,
ConstantInt
::
get
(
ValTy
,
64
)
)
,
"val64"
)
;
}
</s>

Perform a masked cmpxchg using a target-specific intrinsic .


<s> bool shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) override { if ( Fixup . getKind ( ) >= FirstLiteralRelocationKind ) return true ; switch ( ( Sparc :: Fixups ) Fixup . getKind ( ) ) { default : return false ; case Sparc :: fixup_sparc_wplt30 : if ( Target . getSymA ( ) -> getSymbol ( ) . isTemporary ( ) ) return false ; LLVM_FALLTHROUGH ; case Sparc :: fixup_sparc_tls_gd_hi22 : case Sparc :: fixup_sparc_tls_gd_lo10 : case Sparc :: fixup_sparc_tls_gd_add : case Sparc :: fixup_sparc_tls_gd_call : case Sparc :: fixup_sparc_tls_ldm_hi22 : case Sparc :: fixup_sparc_tls_ldm_lo10 : case Sparc :: fixup_sparc_tls_ldm_add : case Sparc :: fixup_sparc_tls_ldm_call : case Sparc :: fixup_sparc_tls_ldo_hix22 : case Sparc :: fixup_sparc_tls_ldo_lox10 : case Sparc :: fixup_sparc_tls_ldo_add : case Sparc :: fixup_sparc_tls_ie_hi22 : case Sparc :: fixup_sparc_tls_ie_lo10 : case Sparc :: fixup_sparc_tls_ie_ld : case Sparc :: fixup_sparc_tls_ie_ldx : case Sparc :: fixup_sparc_tls_ie_add : case Sparc :: fixup_sparc_tls_le_hix22 : case Sparc :: fixup_sparc_tls_le_lox10 : return true ; } } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> static void ix86_set_current_function ( tree fndecl ) { if ( fndecl == ix86_previous_fndecl ) return ; tree old_tree ; if ( ix86_previous_fndecl == NULL_TREE ) old_tree = target_option_current_node ; else if ( DECL_FUNCTION_SPECIFIC_TARGET ( ix86_previous_fndecl ) ) old_tree = DECL_FUNCTION_SPECIFIC_TARGET ( ix86_previous_fndecl ) ; else old_tree = target_option_default_node ; if ( fndecl == NULL_TREE ) { if ( old_tree != target_option_current_node ) ix86_reset_previous_fndecl ( ) ; return ; } tree new_tree = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( new_tree == NULL_TREE ) new_tree = target_option_default_node ; if ( old_tree != new_tree ) { cl_target_option_restore ( & global_options , TREE_TARGET_OPTION ( new_tree ) ) ; if ( TREE_TARGET_GLOBALS ( new_tree ) ) restore_target_globals ( TREE_TARGET_GLOBALS ( new_tree ) ) ; else if ( new_tree == target_option_default_node ) restore_target_globals ( & default_target_globals ) ; else TREE_TARGET_GLOBALS ( new_tree ) = save_target_globals_default_opts ( ) ; } ix86_previous_fndecl = fndecl ; if ( TARGET_64BIT && ( call_used_regs [ SI_REG ] == ( cfun -> machine -> call_abi == MS_ABI ) ) ) reinit_regs ( ) ; } </s>

Establish appropriate back-end context for processing the function FNDECL . The argument might be NULL to indicate processing at top level , outside of any function scope .


<s> bool mips_hard_regno_scratch_ok ( unsigned int regno ) { if ( cfun -> machine -> interrupt_handler_p && ! df_regs_ever_live_p ( regno ) ) return false ; return true ; } </s>

Return nonzero if register REGNO can be used as a scratch register in peephole2 .


<s> bool SIInstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Cond , Register DstReg , Register TrueReg , Register FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { switch ( Cond [ 0 ] . getImm ( ) ) { case VCCNZ : case VCCZ : { const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = MRI . getRegClass ( TrueReg ) ; assert ( MRI . getRegClass ( FalseReg ) == RC ) ; int NumInsts = AMDGPU :: getRegBitWidth ( RC -> getID ( ) ) / 32 ; CondCycles = TrueCycles = FalseCycles = NumInsts ; return RI . hasVGPRs ( RC ) && NumInsts <= 6 ; } case SCC_TRUE : case SCC_FALSE : { const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = MRI . getRegClass ( TrueReg ) ; assert ( MRI . getRegClass ( FalseReg ) == RC ) ; int NumInsts = AMDGPU :: getRegBitWidth ( RC -> getID ( ) ) / 32 ; if ( NumInsts % 2 == 0 ) NumInsts /= 2 ; CondCycles = TrueCycles = FalseCycles = NumInsts ; return RI . isSGPRClass ( RC ) ; } default : return false ; } } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> TargetLowering :: AtomicExpansionKind HexagonTargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { const DataLayout & DL = AI -> getModule ( ) -> getDataLayout ( ) ; unsigned Size = DL . getTypeStoreSize ( AI -> getCompareOperand ( ) -> getType ( ) ) ; if ( Size >= 4 && Size <= 8 ) return AtomicExpansionKind :: LLSC ; return AtomicExpansionKind :: None ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s>
MachineBasicBlock
::
iterator
ARCInstrInfo
::
loadImmediate
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
Reg
,
uint64_t
Value
)
const
{
DebugLoc
dl
=
MBB
.
findDebugLoc
(
MI
)
;
if
(
isInt
<
12
>
(
Value
)
)
{
return
BuildMI
(
MBB
,
MI
,
dl
,
get
(
ARC
::
MOV_rs12
)
,
Reg
)
.
addImm
(
Value
)
.
getInstr
(
)
;
}
llvm_unreachable
(
"Need Arc long immediate instructions."
)
;
}
</s>

Emit a series of instructions to load an immediate .


<s> static bool ix86_expand_vector_init_low_nonzero ( bool mmx_ok , enum machine_mode mode , rtx target , rtx var ) { enum machine_mode vsimode ; rtx x ; switch ( mode ) { case V2SFmode : case V2SImode : if ( ! mmx_ok && ! TARGET_SSE ) return false ; case V2DFmode : case V2DImode : var = force_reg ( GET_MODE_INNER ( mode ) , var ) ; x = gen_rtx_VEC_CONCAT ( mode , var , CONST0_RTX ( GET_MODE_INNER ( mode ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , x ) ) ; return true ; case V4SFmode : case V4SImode : var = force_reg ( GET_MODE_INNER ( mode ) , var ) ; x = gen_rtx_VEC_DUPLICATE ( mode , var ) ; x = gen_rtx_VEC_MERGE ( mode , x , CONST0_RTX ( mode ) , const1_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , x ) ) ; return true ; case V8HImode : case V16QImode : vsimode = V4SImode ; goto widen ; case V4HImode : case V8QImode : if ( ! mmx_ok ) return false ; vsimode = V2SImode ; goto widen ; widen : var = convert_modes ( SImode , GET_MODE_INNER ( mode ) , var , true ) ; x = gen_reg_rtx ( vsimode ) ; if ( ! ix86_expand_vector_init_low_nonzero ( mmx_ok , vsimode , x , var ) ) gcc_unreachable ( ) ; emit_move_insn ( target , gen_lowpart ( mode , x ) ) ; return true ; default : return false ; } } </s>

A subroutine of ix86_expand_vector_init . Store into TARGET a vector whose low element is VAR , and other elements are zero . Return true if successful .


<s> void aarch64_override_options_internal ( struct gcc_options * opts ) { aarch64_tune_flags = selected_tune -> flags ; aarch64_tune = selected_tune -> sched_core ; aarch64_tune_params = * ( selected_tune -> tune ) ; aarch64_architecture_version = selected_arch -> architecture_version ; if ( opts -> x_aarch64_override_tune_string ) aarch64_parse_override_string ( opts -> x_aarch64_override_tune_string , & aarch64_tune_params ) ; if ( opts -> x_flag_strict_volatile_bitfields < 0 && abi_version_at_least ( 2 ) ) opts -> x_flag_strict_volatile_bitfields = 1 ; initialize_aarch64_code_model ( opts ) ; initialize_aarch64_tls_size ( opts ) ; int queue_depth = 0 ; switch ( aarch64_tune_params . autoprefetcher_model ) { case tune_params :: AUTOPREFETCHER_OFF : queue_depth = - 1 ; break ; case tune_params :: AUTOPREFETCHER_WEAK : queue_depth = 0 ; break ; case tune_params :: AUTOPREFETCHER_STRONG : queue_depth = max_insn_queue_index + 1 ; break ; default : gcc_unreachable ( ) ; } maybe_set_param_value ( PARAM_SCHED_AUTOPREF_QUEUE_DEPTH , queue_depth , opts -> x_param_values , global_options_set . x_param_values ) ; if ( aarch64_tune_params . prefetch -> num_slots > 0 ) maybe_set_param_value ( PARAM_SIMULTANEOUS_PREFETCHES , aarch64_tune_params . prefetch -> num_slots , opts -> x_param_values , global_options_set . x_param_values ) ; if ( aarch64_tune_params . prefetch -> l1_cache_size >= 0 ) maybe_set_param_value ( PARAM_L1_CACHE_SIZE , aarch64_tune_params . prefetch -> l1_cache_size , opts -> x_param_values , global_options_set . x_param_values ) ; if ( aarch64_tune_params . prefetch -> l1_cache_line_size >= 0 ) maybe_set_param_value ( PARAM_L1_CACHE_LINE_SIZE , aarch64_tune_params . prefetch -> l1_cache_line_size , opts -> x_param_values , global_options_set . x_param_values ) ; if ( aarch64_tune_params . prefetch -> l2_cache_size >= 0 ) maybe_set_param_value ( PARAM_L2_CACHE_SIZE , aarch64_tune_params . prefetch -> l2_cache_size , opts -> x_param_values , global_options_set . x_param_values ) ; maybe_set_param_value ( PARAM_SCHED_PRESSURE_ALGORITHM , SCHED_PRESSURE_MODEL , opts -> x_param_values , global_options_set . x_param_values ) ; if ( opts -> x_flag_prefetch_loop_arrays < 0 && ! opts -> x_optimize_size && aarch64_tune_params . prefetch -> default_opt_level >= 0 && opts -> x_optimize >= aarch64_tune_params . prefetch -> default_opt_level ) opts -> x_flag_prefetch_loop_arrays = 1 ; aarch64_override_options_after_change_1 ( opts ) ; } </s>

'Unpack ' up the internal tuning structs and update the options in OPTS . The caller must have set up selected_tune and selected_arch as all the other target-specific codegen decisions are derived from them .


<s> static unsigned int aarch64_hard_regno_nregs ( unsigned regno , machine_mode mode ) { HOST_WIDE_INT lowest_size = constant_lower_bound ( GET_MODE_SIZE ( mode ) ) ; switch ( aarch64_regno_regclass ( regno ) ) { case FP_REGS : case FP_LO_REGS : if ( aarch64_sve_data_mode_p ( mode ) ) return exact_div ( GET_MODE_SIZE ( mode ) , BYTES_PER_SVE_VECTOR ) . to_constant ( ) ; return CEIL ( lowest_size , UNITS_PER_VREG ) ; case PR_REGS : case PR_LO_REGS : case PR_HI_REGS : return 1 ; default : return CEIL ( lowest_size , UNITS_PER_WORD ) ; } gcc_unreachable ( ) ; } </s>


<s> void X86AsmPrinter :: emitFunctionBodyEnd ( ) { if ( EmitFPOData ) { if ( auto * XTS = static_cast < X86TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ) XTS -> emitFPOEndProc ( ) ; } } </s>

Targets can override this to emit stuff after the last basic block in the function .


<s>
std
::
vector
<
const
SUnit
*
>
GCNMinRegScheduler
::
schedule
(
ArrayRef
<
const
SUnit
*
>
TopRoots
,
const
ScheduleDAG
&
DAG
)
{
const
auto
&
SUnits
=
DAG
.
SUnits
;
std
::
vector
<
const
SUnit
*
>
Schedule
;
Schedule
.
reserve
(
SUnits
.
size
(
)
)
;
initNumPreds
(
SUnits
)
;
int
StepNo
=
0
;
for
(
auto
SU
:
TopRoots
)
{
RQ
.
push_back
(
*
new
(
Alloc
.
Allocate
(
)
)
Candidate
(
SU
,
StepNo
)
)
;
}
releaseSuccessors
(
&
DAG
.
EntrySU
,
StepNo
)
;
while
(
!
RQ
.
empty
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"\n=== Picking candidate, Step = "
<<
StepNo
<<
"\n"
"Ready queue:"
;
for
(
auto
&
C
:
RQ
)
dbgs
(
)
<<
' '
<<
C
.
SU
->
NodeNum
<<
"(P"
<<
C
.
Priority
<<
')'
;
dbgs
(
)
<<
'\n'
;
)
;
auto
C
=
pickCandidate
(
)
;
assert
(
C
)
;
RQ
.
remove
(
*
C
)
;
auto
SU
=
C
->
SU
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Selected "
;
SU
->
dump
(
&
DAG
)
)
;
releaseSuccessors
(
SU
,
StepNo
)
;
Schedule
.
push_back
(
SU
)
;
setIsScheduled
(
SU
)
;
if
(
getReadySuccessors
(
SU
)
==
0
)
bumpPredsPriority
(
SU
,
StepNo
)
;
++
StepNo
;
}
assert
(
SUnits
.
size
(
)
==
Schedule
.
size
(
)
)
;
return
Schedule
;
}
</s>

Schedule - This is called back from ScheduleDAGInstrs : :Run ( ) when it 's time to do some work .

AMDGPU
0
"\n=== Picking candidate, Step = "
"\n"
"Ready queue:"
"(P"
"Selected "
0


<s> unsigned PPCTargetLowering :: getPrefLoopAlignment ( MachineLoop * ML ) const { switch ( Subtarget . getDarwinDirective ( ) ) { default : break ; case PPC :: DIR_970 : case PPC :: DIR_PWR4 : case PPC :: DIR_PWR5 : case PPC :: DIR_PWR5X : case PPC :: DIR_PWR6 : case PPC :: DIR_PWR6X : case PPC :: DIR_PWR7 : case PPC :: DIR_PWR8 : case PPC :: DIR_PWR9 : { if ( ! ML ) break ; const PPCInstrInfo * TII = Subtarget . getInstrInfo ( ) ; uint64_t LoopSize = 0 ; for ( auto I = ML -> block_begin ( ) , IE = ML -> block_end ( ) ; I != IE ; ++ I ) for ( auto J = ( * I ) -> begin ( ) , JE = ( * I ) -> end ( ) ; J != JE ; ++ J ) { LoopSize += TII -> getInstSizeInBytes ( * J ) ; if ( LoopSize > 32 ) break ; } if ( LoopSize > 16 && LoopSize <= 32 ) return 5 ; break ; } } return TargetLowering :: getPrefLoopAlignment ( ML ) ; } </s>


<s>
SDValue
HexagonTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
EH_RETURN
:
return
LowerEH_RETURN
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
llvm_unreachable
(
"TLS not implemented for Hexagon."
)
;
case
ISD
::
ATOMIC_FENCE
:
return
LowerATOMIC_FENCE
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGLOBALADDRESS
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
BR_JT
:
return
LowerBR_JT
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
Op
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
INLINEASM
:
return
LowerINLINEASM
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

Hexagon
Hexagon
"Should not custom lower this!"
ISD::ConstantPool
ISD::EH_RETURN
ISD::RETURNADDR
ISD::FRAMEADDR
ISD::GlobalTLSAddress
"TLS not implemented for Hexagon."
ISD::ATOMIC_FENCE
ISD::GlobalAddress
ISD::BlockAddress
ISD::VASTART
ISD::BR_JT
ISD::DYNAMIC_STACKALLOC
ISD::SELECT_CC
ISD::SELECT
ISD::INTRINSIC_WO_CHAIN
ISD::INLINEASM


<s> static rtx get_thread_pointer ( int to_reg ) { rtx tp , reg , insn ; tp = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , const0_rtx ) , UNSPEC_TP ) ; if ( ! to_reg ) return tp ; reg = gen_reg_rtx ( Pmode ) ; insn = gen_rtx_SET ( VOIDmode , reg , tp ) ; insn = emit_insn ( insn ) ; return reg ; } </s>

Load the thread pointer . If TO_REG is true , force it into a register .


<s>
SDValue
XCoreTargetLowering
::
LowerCall
(
TargetLowering
::
CallLoweringInfo
&
CLI
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SelectionDAG
&
DAG
=
CLI
.
DAG
;
SDLoc
&
dl
=
CLI
.
DL
;
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
=
CLI
.
Outs
;
SmallVectorImpl
<
SDValue
>
&
OutVals
=
CLI
.
OutVals
;
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
=
CLI
.
Ins
;
SDValue
Chain
=
CLI
.
Chain
;
SDValue
Callee
=
CLI
.
Callee
;
bool
&
isTailCall
=
CLI
.
IsTailCall
;
CallingConv
::
ID
CallConv
=
CLI
.
CallConv
;
bool
isVarArg
=
CLI
.
IsVarArg
;
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
report_fatal_error
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
OutVals
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .

XCore
XCore
ISD::OutputArg
ISD::InputArg
"Unsupported calling convention"


<s> void MipsELFStreamer :: emitValueImpl ( const MCExpr * Value , unsigned Size , SMLoc Loc ) { MCELFStreamer :: emitValueImpl ( Value , Size , Loc ) ; Labels . clear ( ) ; } </s>

Overriding these functions allows us to dismiss all labels that are candidates for marking as microMIPS when .word/.long/.4byte etc directives are emitted .


<s> unsigned SIRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const SIFrameLowering * TFI = MF . getSubtarget < GCNSubtarget > ( ) . getFrameLowering ( ) ; const SIMachineFunctionInfo * FuncInfo = MF . getInfo < SIMachineFunctionInfo > ( ) ; return TFI -> hasFP ( MF ) ? FuncInfo -> getFrameOffsetReg ( ) : FuncInfo -> getStackPtrOffsetReg ( ) ; } </s>


<s> bool X86TargetLowering :: isVectorLoadExtDesirable ( SDValue ExtVal ) const { if ( isa < MaskedLoadSDNode > ( ExtVal . getOperand ( 0 ) ) ) return false ; EVT SrcVT = ExtVal . getOperand ( 0 ) . getValueType ( ) ; if ( SrcVT . getScalarType ( ) == MVT :: i1 ) return false ; return true ; } </s>

Return true if folding a vector load into ExtVal ( a sign , zero , or any extend node ) is profitable .


<s> bool runOnMachineFunction ( MachineFunction & MF ) { for ( MachineFunction :: iterator MBBi = MF . begin ( ) ; MBBi != MF . end ( ) ; MBBi ++ ) { MachineBasicBlock & MBB = * MBBi ; for ( MachineBasicBlock :: iterator MIi = MBB . begin ( ) ; MIi != MBB . end ( ) ; MIi ++ ) { MachineInstr & MI = * MIi ; for ( int i = 0 ; i < MI . getNumOperands ( ) ; i ++ ) { MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . isMetadata ( ) ) { const MDNode * mdn = MO . getMetadata ( ) ; mdn -> dump ( ) ; errs ( ) << MI << "\n" ; } } } } return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool DLXPassConfig :: addInstSelector ( ) { addPass ( createDLXISelDag ( getDLXTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64Bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , Options . StackAlignmentOverride , is64Bit ) , FrameLowering ( * this , Subtarget ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) { if ( getRelocationModel ( ) == Reloc :: Static ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . is64Bit ( ) ) { Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; } else if ( Subtarget . isTargetCOFF ( ) ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . isTargetDarwin ( ) ) { if ( getRelocationModel ( ) == Reloc :: PIC_ ) Subtarget . setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; Subtarget . setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( Subtarget . isTargetELF ( ) ) { Subtarget . setPICStyle ( PICStyles :: GOT ) ; } if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = FloatABI :: Hard ; } </s>


<s>
static
void
ia64_output_function_prologue
(
FILE
*
file
,
HOST_WIDE_INT
size
ATTRIBUTE_UNUSED
)
{
int
mask
,
grsave
,
grsave_prev
;
if
(
current_frame_info
.
need_regstk
)
fprintf
(
file
,
"\t.regstk %d, %d, %d, %d\n"
,
current_frame_info
.
n_input_regs
,
current_frame_info
.
n_local_regs
,
current_frame_info
.
n_output_regs
,
current_frame_info
.
n_rotate_regs
)
;
if
(
ia64_except_unwind_info
(
&
global_options
)
!=
UI_TARGET
)
return
;
mask
=
0
;
grsave
=
grsave_prev
=
0
;
if
(
current_frame_info
.
r
[
reg_save_b0
]
!=
0
)
{
mask
|=
8
;
grsave
=
grsave_prev
=
current_frame_info
.
r
[
reg_save_b0
]
;
}
if
(
current_frame_info
.
r
[
reg_save_ar_pfs
]
!=
0
&&
(
grsave_prev
==
0
||
current_frame_info
.
r
[
reg_save_ar_pfs
]
==
grsave_prev
+
1
)
)
{
mask
|=
4
;
if
(
grsave_prev
==
0
)
grsave
=
current_frame_info
.
r
[
reg_save_ar_pfs
]
;
grsave_prev
=
current_frame_info
.
r
[
reg_save_ar_pfs
]
;
}
if
(
current_frame_info
.
r
[
reg_fp
]
!=
0
&&
(
grsave_prev
==
0
||
current_frame_info
.
r
[
reg_fp
]
==
grsave_prev
+
1
)
)
{
mask
|=
2
;
if
(
grsave_prev
==
0
)
grsave
=
HARD_FRAME_POINTER_REGNUM
;
grsave_prev
=
current_frame_info
.
r
[
reg_fp
]
;
}
if
(
current_frame_info
.
r
[
reg_save_pr
]
!=
0
&&
(
grsave_prev
==
0
||
current_frame_info
.
r
[
reg_save_pr
]
==
grsave_prev
+
1
)
)
{
mask
|=
1
;
if
(
grsave_prev
==
0
)
grsave
=
current_frame_info
.
r
[
reg_save_pr
]
;
}
if
(
mask
&&
TARGET_GNU_AS
)
fprintf
(
file
,
"\t.prologue %d, %d\n"
,
mask
,
ia64_dbx_register_number
(
grsave
)
)
;
else
fputs
(
"\t.prologue\n"
,
file
)
;
if
(
current_frame_info
.
spill_cfa_off
!=
16
)
fprintf
(
file
,
"\t.spill %ld\n"
,
(
long
)
(
current_frame_info
.
spill_cfa_off
+
current_frame_info
.
spill_size
)
)
;
}
</s>


<s> const char * SPUTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { if ( node_names . empty ( ) ) { node_names [ ( unsigned ) SPUISD :: RET_FLAG ] = "SPUISD::RET_FLAG" ; node_names [ ( unsigned ) SPUISD :: Hi ] = "SPUISD::Hi" ; node_names [ ( unsigned ) SPUISD :: Lo ] = "SPUISD::Lo" ; node_names [ ( unsigned ) SPUISD :: PCRelAddr ] = "SPUISD::PCRelAddr" ; node_names [ ( unsigned ) SPUISD :: AFormAddr ] = "SPUISD::AFormAddr" ; node_names [ ( unsigned ) SPUISD :: IndirectAddr ] = "SPUISD::IndirectAddr" ; node_names [ ( unsigned ) SPUISD :: LDRESULT ] = "SPUISD::LDRESULT" ; node_names [ ( unsigned ) SPUISD :: CALL ] = "SPUISD::CALL" ; node_names [ ( unsigned ) SPUISD :: SHUFB ] = "SPUISD::SHUFB" ; node_names [ ( unsigned ) SPUISD :: SHUFFLE_MASK ] = "SPUISD::SHUFFLE_MASK" ; node_names [ ( unsigned ) SPUISD :: CNTB ] = "SPUISD::CNTB" ; node_names [ ( unsigned ) SPUISD :: PREFSLOT2VEC ] = "SPUISD::PREFSLOT2VEC" ; node_names [ ( unsigned ) SPUISD :: VEC2PREFSLOT ] = "SPUISD::VEC2PREFSLOT" ; node_names [ ( unsigned ) SPUISD :: SHLQUAD_L_BITS ] = "SPUISD::SHLQUAD_L_BITS" ; node_names [ ( unsigned ) SPUISD :: SHLQUAD_L_BYTES ] = "SPUISD::SHLQUAD_L_BYTES" ; node_names [ ( unsigned ) SPUISD :: VEC_SHL ] = "SPUISD::VEC_SHL" ; node_names [ ( unsigned ) SPUISD :: VEC_SRL ] = "SPUISD::VEC_SRL" ; node_names [ ( unsigned ) SPUISD :: VEC_SRA ] = "SPUISD::VEC_SRA" ; node_names [ ( unsigned ) SPUISD :: VEC_ROTL ] = "SPUISD::VEC_ROTL" ; node_names [ ( unsigned ) SPUISD :: VEC_ROTR ] = "SPUISD::VEC_ROTR" ; node_names [ ( unsigned ) SPUISD :: ROTBYTES_LEFT ] = "SPUISD::ROTBYTES_LEFT" ; node_names [ ( unsigned ) SPUISD :: ROTBYTES_LEFT_BITS ] = "SPUISD::ROTBYTES_LEFT_BITS" ; node_names [ ( unsigned ) SPUISD :: SELECT_MASK ] = "SPUISD::SELECT_MASK" ; node_names [ ( unsigned ) SPUISD :: SELB ] = "SPUISD::SELB" ; node_names [ ( unsigned ) SPUISD :: ADD64_MARKER ] = "SPUISD::ADD64_MARKER" ; node_names [ ( unsigned ) SPUISD :: SUB64_MARKER ] = "SPUISD::SUB64_MARKER" ; node_names [ ( unsigned ) SPUISD :: MUL64_MARKER ] = "SPUISD::MUL64_MARKER" ; } std :: map < unsigned , const char * > :: iterator i = node_names . find ( Opcode ) ; return ( ( i != node_names . end ( ) ) ? i -> second : 0 ) ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s>
void
relaxInstruction
(
const
MCInst
&
Inst
,
MCInst
&
Res
)
const
override
{
llvm_unreachable
(
"relaxInstruction() unimplemented"
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> bool MipsFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


"llvm does not support 'Q', 'R', and 'H' modifiers!"

PrintAsmOperand - Print out an operand for an inline asm expression .


<s>
const
MCFixupKindInfo
&
OR1KAsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
OR1K
::
NumTargetFixupKinds
]
=
{
{
"fixup_OR1K_NONE"
,
0
,
32
,
0
}
,
{
"fixup_OR1K_32"
,
0
,
32
,
0
}
,
{
"fixup_OR1K_16"
,
0
,
16
,
0
}
,
{
"fixup_OR1K_8"
,
0
,
8
,
0
}
,
{
"fixup_OR1K_LO16_INSN"
,
0
,
16
,
0
}
,
{
"fixup_OR1K_HI16_INSN"
,
0
,
16
,
0
}
,
{
"fixup_OR1K_REL26"
,
0
,
26
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_OR1K_PCREL32"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_OR1K_PCREL16"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_OR1K_PCREL8"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_OR1K_GOTPC_HI16"
,
0
,
16
,
0
}
,
{
"fixup_OR1K_GOTPC_LO16"
,
0
,
16
,
0
}
,
{
"fixup_OR1K_GOT16"
,
0
,
16
,
0
}
,
{
"fixup_OR1K_PLT26"
,
0
,
26
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_OR1K_GOTOFF_HI16"
,
0
,
16
,
0
}
,
{
"fixup_OR1K_GOTOFF_LO16"
,
0
,
16
,
0
}
,
{
"fixup_OR1K_COPY"
,
0
,
32
,
0
}
,
{
"fixup_OR1K_GLOB_DAT"
,
0
,
32
,
0
}
,
{
"fixup_OR1K_JMP_SLOT"
,
0
,
32
,
0
}
,
{
"fixup_OR1K_RELATIVE"
,
0
,
32
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> static const char * detect_processor_freebsd ( void ) { return "powerpc" ; } </s>


<s> bool AArch64FastISel :: optimizeSelect ( const SelectInst * SI ) { if ( ! SI -> getType ( ) -> isIntegerTy ( 1 ) ) return false ; const Value * Src1Val , * Src2Val ; unsigned Opc = 0 ; bool NeedExtraOp = false ; if ( auto * CI = dyn_cast < ConstantInt > ( SI -> getTrueValue ( ) ) ) { if ( CI -> isOne ( ) ) { Src1Val = SI -> getCondition ( ) ; Src2Val = SI -> getFalseValue ( ) ; Opc = AArch64 :: ORRWrr ; } else { assert ( CI -> isZero ( ) ) ; Src1Val = SI -> getFalseValue ( ) ; Src2Val = SI -> getCondition ( ) ; Opc = AArch64 :: BICWrr ; } } else if ( auto * CI = dyn_cast < ConstantInt > ( SI -> getFalseValue ( ) ) ) { if ( CI -> isOne ( ) ) { Src1Val = SI -> getCondition ( ) ; Src2Val = SI -> getTrueValue ( ) ; Opc = AArch64 :: ORRWrr ; NeedExtraOp = true ; } else { assert ( CI -> isZero ( ) ) ; Src1Val = SI -> getCondition ( ) ; Src2Val = SI -> getTrueValue ( ) ; Opc = AArch64 :: ANDWrr ; } } if ( ! Opc ) return false ; unsigned Src1Reg = getRegForValue ( Src1Val ) ; if ( ! Src1Reg ) return false ; bool Src1IsKill = hasTrivialKill ( Src1Val ) ; unsigned Src2Reg = getRegForValue ( Src2Val ) ; if ( ! Src2Reg ) return false ; bool Src2IsKill = hasTrivialKill ( Src2Val ) ; if ( NeedExtraOp ) { Src1Reg = emitLogicalOp_ri ( ISD :: XOR , MVT :: i32 , Src1Reg , Src1IsKill , 1 ) ; Src1IsKill = true ; } unsigned ResultReg = fastEmitInst_rr ( Opc , & AArch64 :: GPR32RegClass , Src1Reg , Src1IsKill , Src2Reg , Src2IsKill ) ; updateValueMap ( SI , ResultReg ) ; return true ; } </s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


<s> void ix86_split_fp_branch ( enum rtx_code code , rtx op1 , rtx op2 , rtx target1 , rtx target2 , rtx tmp , rtx pushed ) { rtx second , bypass ; rtx label = NULL_RTX ; rtx condition ; int bypass_probability = - 1 , second_probability = - 1 , probability = - 1 ; rtx i ; if ( target2 != pc_rtx ) { rtx tmp = target2 ; code = reverse_condition_maybe_unordered ( code ) ; target2 = target1 ; target1 = tmp ; } condition = ix86_expand_fp_compare ( code , op1 , op2 , tmp , & second , & bypass ) ; if ( pushed ) ix86_free_from_memory ( GET_MODE ( pushed ) ) ; if ( split_branch_probability >= 0 ) { probability = split_branch_probability ; if ( bypass ) bypass_probability = 1 ; if ( second ) second_probability = 1 ; } if ( bypass != NULL_RTX ) { label = gen_label_rtx ( ) ; i = emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , bypass , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ) ) ; if ( bypass_probability >= 0 ) REG_NOTES ( i ) = gen_rtx_EXPR_LIST ( REG_BR_PROB , GEN_INT ( bypass_probability ) , REG_NOTES ( i ) ) ; } i = emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , condition , target1 , target2 ) ) ) ; if ( probability >= 0 ) REG_NOTES ( i ) = gen_rtx_EXPR_LIST ( REG_BR_PROB , GEN_INT ( probability ) , REG_NOTES ( i ) ) ; if ( second != NULL_RTX ) { i = emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , second , target1 , target2 ) ) ) ; if ( second_probability >= 0 ) REG_NOTES ( i ) = gen_rtx_EXPR_LIST ( REG_BR_PROB , GEN_INT ( second_probability ) , REG_NOTES ( i ) ) ; } if ( label != NULL_RTX ) emit_label ( label ) ; } </s>

Split branch based on floating point condition .


<s> bool hasFP ( const MachineFunction & MF ) const { return true ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"AArch64 MI Peephole Optimization pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
static
void
rs6000_output_function_prologue
(
FILE
*
file
,
HOST_WIDE_INT
size
ATTRIBUTE_UNUSED
)
{
if
(
!
cfun
->
is_thunk
)
rs6000_output_savres_externs
(
file
)
;
if
(
DEFAULT_ABI
==
ABI_ELFv2
&&
cfun
->
machine
->
r2_setup_needed
)
{
const
char
*
name
=
XSTR
(
XEXP
(
DECL_RTL
(
current_function_decl
)
,
0
)
,
0
)
;
fprintf
(
file
,
"0:\taddis 2,12,.TOC.-0b@ha\n"
)
;
fprintf
(
file
,
"\taddi 2,2,.TOC.-0b@l\n"
)
;
fputs
(
"\t.localentry\t"
,
file
)
;
assemble_name
(
file
,
name
)
;
fputs
(
",.-"
,
file
)
;
assemble_name
(
file
,
name
)
;
fputs
(
"\n"
,
file
)
;
}
if
(
TARGET_PROFILE_KERNEL
&&
crtl
->
profile
)
{
gcc_assert
(
DEFAULT_ABI
==
ABI_AIX
||
DEFAULT_ABI
==
ABI_ELFv2
)
;
gcc_assert
(
!
TARGET_32BIT
)
;
asm_fprintf
(
file
,
"\tmflr %s\n"
,
reg_names
[
0
]
)
;
asm_fprintf
(
file
,
"\tstd %s,16(%s)\n"
,
reg_names
[
0
]
,
reg_names
[
1
]
)
;
if
(
DEFAULT_ABI
!=
ABI_ELFv2
&&
cfun
->
static_chain_decl
!=
)
{
asm_fprintf
(
file
,
"\tstd %s,24(%s)\n"
,
reg_names
[
STATIC_CHAIN_REGNUM
]
,
reg_names
[
1
]
)
;
fprintf
(
file
,
"\tbl %s\n"
,
RS6000_MCOUNT
)
;
asm_fprintf
(
file
,
"\tld %s,24(%s)\n"
,
reg_names
[
STATIC_CHAIN_REGNUM
]
,
reg_names
[
1
]
)
;
}
else
fprintf
(
file
,
"\tbl %s\n"
,
RS6000_MCOUNT
)
;
}
rs6000_pic_labelno
++
;
}
</s>


<s> Value * ARM64TargetLowering :: emitStoreConditional ( IRBuilder < > & Builder , Value * Val , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == 128 ) { Intrinsic :: ID Int = IsRelease ? Intrinsic :: arm64_stlxp : Intrinsic :: arm64_stxp ; Function * Stxr = Intrinsic :: getDeclaration ( M , Int ) ; Type * Int64Ty = Type :: getInt64Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int64Ty , "lo" ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , 64 ) , Int64Ty , "hi" ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall3 ( Stxr , Lo , Hi , Addr ) ; } Intrinsic :: ID Int = IsRelease ? Intrinsic :: arm64_stlxr : Intrinsic :: arm64_stxr ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Stxr = Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateCall2 ( Stxr , Builder . CreateZExtOrBitCast ( Val , Stxr -> getFunctionType ( ) -> getParamType ( 0 ) ) , Addr ) ; } </s>

Perform a store-conditional operation to Addr .


<s> Value * Simplifier :: simplify ( Context & C ) { WorkListType Q ; Q . push_back ( C . Root ) ; unsigned Count = 0 ; const unsigned Limit = SimplifyLimit ; while ( ! Q . empty ( ) ) { if ( Count ++ >= Limit ) break ; Instruction * U = dyn_cast < Instruction > ( Q . pop_front_val ( ) ) ; if ( ! U || U -> getParent ( ) || ! C . Used . count ( U ) ) continue ; bool Changed = false ; for ( Rule & R : Rules ) { Value * W = R . Fn ( U , C . Ctx ) ; if ( ! W ) continue ; Changed = true ; C . record ( W ) ; C . replace ( U , W ) ; Q . push_back ( C . Root ) ; break ; } if ( ! Changed ) { for ( Value * Op : U -> operands ( ) ) Q . push_back ( Op ) ; } } return Count < Limit ? C . Root : nullptr ; } </s>

Go through all the nodes in the graph and collapse any two nodes ' a ' and ' b ' if all of the following are true :


<s> bool ARMBaseInstrInfo :: isTailCall ( const MachineInstr & Inst ) const { switch ( Inst . getOpcode ( ) ) { case ARM :: TAILJMPd : case ARM :: TAILJMPr : case ARM :: TCRETURNdi : case ARM :: TCRETURNri : return true ; default : return false ; } } </s>

Determines whether Inst is a tail call instruction .

ARM ARM ARM::TAILJMPd ARM::TAILJMPr ARM::TCRETURNdi ARM::TCRETURNri


<s> static int arc_save_callee_saves ( unsigned int gmask , bool save_blink , bool save_fp , HOST_WIDE_INT offset ) { rtx reg ; int frame_allocated = 0 ; if ( save_blink ) { reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; frame_allocated += frame_save_reg ( reg , offset ) ; offset = 0 ; } if ( gmask ) for ( int i = 31 ; i >= 0 ; i -- ) { machine_mode save_mode = SImode ; if ( TARGET_LL64 && ( ( i - 1 ) % 2 == 0 ) && ( ( gmask & ( 1L << i ) ) != 0 ) && ( ( gmask & ( 1L << ( i - 1 ) ) ) != 0 ) ) { save_mode = DImode ; -- i ; } else if ( ( gmask & ( 1L << i ) ) == 0 ) continue ; reg = gen_rtx_REG ( save_mode , i ) ; frame_allocated += frame_save_reg ( reg , offset ) ; offset = 0 ; } if ( save_fp ) { frame_allocated += frame_save_reg ( hard_frame_pointer_rtx , offset ) ; offset = 0 ; } if ( arc_frame_pointer_needed ( ) ) frame_move ( hard_frame_pointer_rtx , stack_pointer_rtx ) ; return frame_allocated ; } </s>

ARC 's prologue , save any needed call-saved regs ( and call-used if this is an interrupt handler ) for ARCompact ISA , using ST/STD instructions .


<s> const TargetRegisterClass * PPCRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC ) const { if ( Subtarget . hasVSX ( ) ) { if ( RC == & PPC :: F8RCRegClass ) return & PPC :: VSFRCRegClass ; else if ( RC == & PPC :: VRRCRegClass ) return & PPC :: VSRCRegClass ; } return TargetRegisterInfo :: getLargestLegalSuperClass ( RC ) ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .

PowerPC PPC PPC::F8RCRegClass PPC::VSFRCRegClass PPC::VRRCRegClass PPC::VSRCRegClass


Map a target register to an equivalent dwarf register number .


<s> void arm_init_cumulative_args ( CUMULATIVE_ARGS * pcum , tree fntype , rtx libname ATTRIBUTE_UNUSED , tree fndecl ATTRIBUTE_UNUSED ) { pcum -> nregs = ( ( fntype && aggregate_value_p ( TREE_TYPE ( fntype ) , fntype ) ) ? 1 : 0 ) ; pcum -> iwmmxt_nregs = 0 ; pcum -> can_split = true ; pcum -> call_cookie = CALL_NORMAL ; if ( TARGET_LONG_CALLS ) pcum -> call_cookie = CALL_LONG ; if ( fntype ) { if ( lookup_attribute ( "short_call" , TYPE_ATTRIBUTES ( fntype ) ) ) pcum -> call_cookie = CALL_SHORT ; else if ( lookup_attribute ( "long_call" , TYPE_ATTRIBUTES ( fntype ) ) ) pcum -> call_cookie = CALL_LONG ; } pcum -> named_count = 0 ; pcum -> nargs = 0 ; if ( TARGET_REALLY_IWMMXT && fntype ) { tree fn_arg ; for ( fn_arg = TYPE_ARG_TYPES ( fntype ) ; fn_arg ; fn_arg = TREE_CHAIN ( fn_arg ) ) pcum -> named_count += 1 ; if ( ! pcum -> named_count ) pcum -> named_count = INT_MAX ; } } </s>

Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is NULL .


<s> unsigned MipsRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const MipsSubtarget & Subtarget = MF . getSubtarget < MipsSubtarget > ( ) ; const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; bool IsN64 = static_cast < const MipsTargetMachine & > ( MF . getTarget ( ) ) . getABI ( ) . IsN64 ( ) ; if ( Subtarget . inMips16Mode ( ) ) return TFI -> hasFP ( MF ) ? Mips :: S0 : Mips :: SP ; else return TFI -> hasFP ( MF ) ? ( IsN64 ? Mips :: FP_64 : Mips :: FP ) : ( IsN64 ? Mips :: SP_64 : Mips :: SP ) ; } </s>

Mips Mips Mips Mips Mips Mips Mips::S0 Mips::SP Mips::FP_64 Mips::FP Mips::SP_64 Mips::SP


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { TII = static_cast < const R600InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = & TII -> getRegisterInfo ( ) ; DEBUG ( MF . dump ( ) ; ) ; OrderedBlks . clear ( ) ; Visited . clear ( ) ; FuncRep = & MF ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; DEBUG ( dbgs ( ) << "LoopInfo:\n" ; PrintLoopinfo ( * MLI ) ; ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; DEBUG ( MDT -> print ( dbgs ( ) , ( const llvm :: Module * ) nullptr ) ; ) ; PDT = & getAnalysis < MachinePostDominatorTree > ( ) ; DEBUG ( PDT -> print ( dbgs ( ) ) ; ) ; prepare ( ) ; run ( ) ; DEBUG ( MF . dump ( ) ; ) ; return true ; } </s>


<s> bool RISCVAsmBackend :: mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const { return getRelaxedOpcode ( Inst . getOpcode ( ) ) != Inst . getOpcode ( ) ; } </s>

Check whether the given instruction may need relaxation .


<s> static bool bfin_frame_pointer_required ( void ) { e_funkind fkind = funkind ( TREE_TYPE ( current_function_decl ) ) ; if ( fkind != SUBROUTINE ) return true ; if ( TARGET_OMIT_LEAF_FRAME_POINTER && ! crtl -> is_leaf ) return true ; return false ; } </s>

Value should be nonzero if functions must have frame pointers . Zero means the frame pointer need not be set up ( and parms may be accessed via the stack pointer ) in functions that seem suitable .


<s>
void
ARMConstantIslands
::
verify
(
)
{
BBInfoVector
&
BBInfo
=
BBUtils
->
getBBInfo
(
)
;
assert
(
is_sorted
(
*
MF
,
[
&
BBInfo
]
(
const
MachineBasicBlock
&
LHS
,
const
MachineBasicBlock
&
RHS
)
{
return
BBInfo
[
LHS
.
getNumber
(
)
]
.
postOffset
(
)
<
BBInfo
[
RHS
.
getNumber
(
)
]
.
postOffset
(
)
;
}
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Verifying "
<<
CPUsers
.
size
(
)
<<
" CP users.\n"
)
;
for
(
CPUser
&
U
:
CPUsers
)
{
unsigned
UserOffset
=
getUserOffset
(
U
)
;
if
(
isCPEntryInRange
(
U
.
MI
,
UserOffset
,
U
.
CPEMI
,
U
.
getMaxDisp
(
)
+
2
,
U
.
NegOk
,
true
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"OK\n"
)
;
continue
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Out of range.\n"
)
;
dumpBBs
(
)
;
LLVM_DEBUG
(
MF
->
dump
(
)
)
;
llvm_unreachable
(
"Constant pool entry out of range!"
)
;
}
}
</s>

ARM
ARM
"Verifying "
" CP users.\n"
2
"OK\n"
"Out of range.\n"
"Constant pool entry out of range!"


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> machine_mode aarch64_sve_int_mode ( machine_mode mode ) { scalar_int_mode int_mode = aarch64_sve_element_int_mode ( mode ) ; return aarch64_sve_data_mode ( int_mode , GET_MODE_NUNITS ( mode ) ) . require ( ) ; } </s>

Return the integer vector mode associated with SVE mode MODE . Unlike related_int_vector_mode , this can handle the case in which MODE is a predicate ( and thus has a different total size ) .


<s>
MachineInstrBuilder
R600InstrInfo
::
buildIndirectRead
(
MachineBasicBlock
*
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
ValueReg
,
unsigned
Address
,
unsigned
OffsetReg
,
unsigned
AddrChan
)
const
{
unsigned
AddrReg
;
switch
(
AddrChan
)
{
default
:
llvm_unreachable
(
"Invalid Channel"
)
;
case
0
:
AddrReg
=
AMDGPU
::
R600_AddrRegClass
.
getRegister
(
Address
)
;
break
;
case
1
:
AddrReg
=
AMDGPU
::
R600_Addr_YRegClass
.
getRegister
(
Address
)
;
break
;
case
2
:
AddrReg
=
AMDGPU
::
R600_Addr_ZRegClass
.
getRegister
(
Address
)
;
break
;
case
3
:
AddrReg
=
AMDGPU
::
R600_Addr_WRegClass
.
getRegister
(
Address
)
;
break
;
}
MachineInstr
*
MOVA
=
buildDefaultInstruction
(
*
MBB
,
I
,
AMDGPU
::
MOVA_INT_eg
,
AMDGPU
::
AR_X
,
OffsetReg
)
;
setImmOperand
(
MOVA
,
AMDGPU
::
OpName
::
write
,
0
)
;
MachineInstrBuilder
Mov
=
buildDefaultInstruction
(
*
MBB
,
I
,
AMDGPU
::
MOV
,
ValueReg
,
AddrReg
)
.
addReg
(
AMDGPU
::
AR_X
,
RegState
::
Implicit
|
RegState
::
Kill
)
;
setImmOperand
(
Mov
,
AMDGPU
::
OpName
::
src0_rel
,
1
)
;
return
Mov
;
}
</s>

Build instruction ( s ) for an indirect register read .


<s> void visium_split_double_move ( rtx * operands , enum machine_mode mode ) { bool swap = false ; if ( GET_CODE ( operands [ 0 ] ) == REG && GET_CODE ( operands [ 1 ] ) == REG && REGNO ( operands [ 0 ] ) == REGNO ( operands [ 1 ] ) + 1 ) swap = true ; if ( GET_CODE ( operands [ 0 ] ) == REG && GET_CODE ( operands [ 1 ] ) == MEM ) { rtx op = XEXP ( operands [ 1 ] , 0 ) ; if ( GET_CODE ( op ) == SUBREG ) op = SUBREG_REG ( op ) ; if ( GET_CODE ( op ) == REG && REGNO ( op ) == REGNO ( operands [ 0 ] ) ) swap = true ; if ( GET_CODE ( op ) == PLUS ) { rtx x = XEXP ( op , 0 ) ; rtx y = XEXP ( op , 1 ) ; if ( GET_CODE ( x ) == REG && REGNO ( x ) == REGNO ( operands [ 0 ] ) ) swap = true ; if ( GET_CODE ( y ) == REG && REGNO ( y ) == REGNO ( operands [ 0 ] ) ) swap = true ; } } if ( swap ) { operands [ 2 ] = operand_subword ( operands [ 0 ] , 1 , 1 , mode ) ; operands [ 3 ] = operand_subword ( operands [ 1 ] , 1 , 1 , mode ) ; operands [ 4 ] = operand_subword ( operands [ 0 ] , 0 , 1 , mode ) ; operands [ 5 ] = operand_subword ( operands [ 1 ] , 0 , 1 , mode ) ; } else { operands [ 2 ] = operand_subword ( operands [ 0 ] , 0 , 1 , mode ) ; operands [ 3 ] = operand_subword ( operands [ 1 ] , 0 , 1 , mode ) ; operands [ 4 ] = operand_subword ( operands [ 0 ] , 1 , 1 , mode ) ; operands [ 5 ] = operand_subword ( operands [ 1 ] , 1 , 1 , mode ) ; } } </s>

Split a double move of OPERANDS in MODE .


"  Found lowered global address with one use: "

runOnMachineFunction - Emit the function body .


<s> bool AMDGPUAnnotateUniformValues :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; DA = & getAnalysis < DivergenceAnalysis > ( ) ; visit ( F ) ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


getTargetNodeName - This method returns the name of a target specific


<s> void MipsSEFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned BP = ABI . IsN64 ( ) ? Mips :: S7_64 : Mips :: S7 ; if ( hasFP ( MF ) ) setAliasRegs ( MF , SavedRegs , FP ) ; if ( hasBP ( MF ) ) setAliasRegs ( MF , SavedRegs , BP ) ; if ( MipsFI -> callsEhReturn ( ) ) MipsFI -> createEhDataRegsFI ( ) ; if ( ExpandPseudo ( MF ) . expand ( ) ) { const TargetRegisterClass * RC = STI . hasMips64 ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } uint64_t MaxSPOffset = MF . getInfo < MipsFunctionInfo > ( ) -> getIncomingArgSize ( ) + estimateStackSize ( MF ) ; if ( isInt < 16 > ( MaxSPOffset ) ) return ; const TargetRegisterClass * RC = ABI . ArePtrs64bit ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> bool RISCVTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { switch ( Intrinsic ) { default : return false ; case Intrinsic :: riscv_masked_atomicrmw_xchg_i32 : case Intrinsic :: riscv_masked_atomicrmw_add_i32 : case Intrinsic :: riscv_masked_atomicrmw_sub_i32 : case Intrinsic :: riscv_masked_atomicrmw_nand_i32 : case Intrinsic :: riscv_masked_atomicrmw_max_i32 : case Intrinsic :: riscv_masked_atomicrmw_min_i32 : case Intrinsic :: riscv_masked_atomicrmw_umax_i32 : case Intrinsic :: riscv_masked_atomicrmw_umin_i32 : case Intrinsic :: riscv_masked_cmpxchg_i32 : { PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 0 ) -> getType ( ) ) ; Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: getVT ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . align = Align ( 4 ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; } } } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> void bfin_expand_prologue ( void ) { HOST_WIDE_INT frame_size = get_frame_size ( ) ; rtx spreg = gen_rtx_REG ( Pmode , REG_SP ) ; e_funkind fkind = funkind ( TREE_TYPE ( current_function_decl ) ) ; rtx pic_reg_loaded = NULL_RTX ; tree attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ; bool all = lookup_attribute ( "saveall" , attrs ) != NULL_TREE ; if ( fkind != SUBROUTINE ) { expand_interrupt_handler_prologue ( spreg , fkind , all ) ; return ; } if ( crtl -> limit_stack || ( TARGET_STACK_CHECK_L1 && ! DECL_NO_LIMIT_STACK ( current_function_decl ) ) ) { HOST_WIDE_INT offset = bfin_initial_elimination_offset ( ARG_POINTER_REGNUM , STACK_POINTER_REGNUM ) ; rtx lim = crtl -> limit_stack ? stack_limit_rtx : NULL_RTX ; rtx tmp = gen_rtx_REG ( Pmode , REG_R3 ) ; rtx p2reg = gen_rtx_REG ( Pmode , REG_P2 ) ; emit_move_insn ( tmp , p2reg ) ; if ( ! lim ) { emit_move_insn ( p2reg , gen_int_mode ( 0xFFB00000 , SImode ) ) ; emit_move_insn ( p2reg , gen_rtx_MEM ( Pmode , p2reg ) ) ; lim = p2reg ; } if ( GET_CODE ( lim ) == SYMBOL_REF ) { if ( TARGET_ID_SHARED_LIBRARY ) { rtx p1reg = gen_rtx_REG ( Pmode , REG_P1 ) ; rtx val ; pic_reg_loaded = bfin_load_pic_reg ( p2reg ) ; val = legitimize_pic_address ( stack_limit_rtx , p1reg , pic_reg_loaded ) ; emit_move_insn ( p1reg , val ) ; frame_related_constant_load ( p2reg , offset , FALSE ) ; emit_insn ( gen_addsi3 ( p2reg , p2reg , p1reg ) ) ; lim = p2reg ; } else { rtx limit = plus_constant ( Pmode , lim , offset ) ; emit_move_insn ( p2reg , limit ) ; lim = p2reg ; } } else { if ( lim != p2reg ) emit_move_insn ( p2reg , lim ) ; add_to_reg ( p2reg , offset , 0 , 0 ) ; lim = p2reg ; } emit_insn ( gen_compare_lt ( bfin_cc_rtx , spreg , lim ) ) ; emit_insn ( gen_trapifcc ( ) ) ; emit_move_insn ( p2reg , tmp ) ; } expand_prologue_reg_save ( spreg , all , false ) ; do_link ( spreg , frame_size , all ) ; if ( TARGET_ID_SHARED_LIBRARY && ! TARGET_SEP_DATA && ( crtl -> uses_pic_offset_table || ! crtl -> is_leaf ) ) bfin_load_pic_reg ( pic_offset_table_rtx ) ; } </s>

Generate RTL for the prologue of the current function .


<s> unsigned getNumberOfRegisters ( unsigned ClassID ) const { return 64 ; } </s>


<s> rtx array_to_constant ( machine_mode mode , const unsigned char arr [ 16 ] ) { machine_mode inner_mode ; rtvec v ; int units , size , i , j , k ; HOST_WIDE_INT val ; if ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_BITSIZE ( mode ) <= HOST_BITS_PER_WIDE_INT ) { j = GET_MODE_SIZE ( mode ) ; i = j < 4 ? 4 - j : 0 ; for ( val = 0 ; i < j ; i ++ ) val = ( val << 8 ) | arr [ i ] ; val = trunc_int_for_mode ( val , mode ) ; return GEN_INT ( val ) ; } if ( mode == TImode ) { HOST_WIDE_INT high ; for ( i = high = 0 ; i < 8 ; i ++ ) high = ( high << 8 ) | arr [ i ] ; for ( i = 8 , val = 0 ; i < 16 ; i ++ ) val = ( val << 8 ) | arr [ i ] ; return immed_double_const ( val , high , TImode ) ; } if ( mode == SFmode ) { val = ( arr [ 0 ] << 24 ) | ( arr [ 1 ] << 16 ) | ( arr [ 2 ] << 8 ) | arr [ 3 ] ; val = trunc_int_for_mode ( val , SImode ) ; return hwint_to_const_double ( SFmode , val ) ; } if ( mode == DFmode ) { for ( i = 0 , val = 0 ; i < 8 ; i ++ ) val = ( val << 8 ) | arr [ i ] ; return hwint_to_const_double ( DFmode , val ) ; } if ( ! VECTOR_MODE_P ( mode ) ) abort ( ) ; units = GET_MODE_NUNITS ( mode ) ; size = GET_MODE_UNIT_SIZE ( mode ) ; inner_mode = GET_MODE_INNER ( mode ) ; v = rtvec_alloc ( units ) ; for ( k = i = 0 ; i < units ; ++ i ) { val = 0 ; for ( j = 0 ; j < size ; j ++ , k ++ ) val = ( val << 8 ) | arr [ k ] ; if ( GET_MODE_CLASS ( inner_mode ) == MODE_FLOAT ) RTVEC_ELT ( v , i ) = hwint_to_const_double ( inner_mode , val ) ; else RTVEC_ELT ( v , i ) = GEN_INT ( trunc_int_for_mode ( val , inner_mode ) ) ; } if ( k > 16 ) abort ( ) ; return gen_rtx_CONST_VECTOR ( mode , v ) ; } </s>

Convert a 16 byte array to a constant of mode MODE . When MODE is smaller than 16 bytes , use the bytes that would represent that value in a register , e.g. , for QImode return the value of arr [ 3 ] .


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s>
bool
M88kPostLegalizerLowering
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
MF
.
getProperties
(
)
.
hasProperty
(
MachineFunctionProperties
::
Property
::
FailedISel
)
)
return
false
;
assert
(
MF
.
getProperties
(
)
.
hasProperty
(
MachineFunctionProperties
::
Property
::
Legalized
)
&&
"Expected a legalized function?"
)
;
auto
*
TPC
=
&
getAnalysis
<
TargetPassConfig
>
(
)
;
const
Function
&
F
=
MF
.
getFunction
(
)
;
M88kPostLegalizerLoweringInfo
PCInfo
(
F
.
hasOptSize
(
)
,
F
.
hasMinSize
(
)
)
;
Combiner
C
(
PCInfo
,
TPC
)
;
return
C
.
combineMachineInstrs
(
MF
,
nullptr
)
;
}
</s>


<s> static void s390_save_gprs_to_fprs ( void ) { int i ; if ( ! TARGET_Z10 || ! TARGET_HARD_FLOAT || ! crtl -> is_leaf ) return ; for ( i = 6 ; i < 16 ; i ++ ) { if ( FP_REGNO_P ( cfun_gpr_save_slot ( i ) ) ) { rtx_insn * insn = emit_move_insn ( gen_rtx_REG ( DImode , cfun_gpr_save_slot ( i ) ) , gen_rtx_REG ( DImode , i ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"CSKY Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static int pa_arg_partial_bytes ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; unsigned int max_arg_words = 8 ; unsigned int offset = 0 ; if ( ! TARGET_64BIT ) return 0 ; if ( pa_function_arg_size ( arg . mode , arg . type ) > 1 && ( cum -> words & 1 ) ) offset = 1 ; if ( cum -> words + offset + pa_function_arg_size ( arg . mode , arg . type ) <= max_arg_words ) return 0 ; else if ( cum -> words + offset >= max_arg_words ) return 0 ; else return ( max_arg_words - cum -> words - offset ) * UNITS_PER_WORD ; } </s>

If this arg would be passed totally in registers or totally on the stack , then this routine should return zero .


<s> unsigned RISCVTargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { switch ( Op . getOpcode ( ) ) { default : break ; case RISCVISD :: SLLW : case RISCVISD :: SRAW : case RISCVISD :: SRLW : case RISCVISD :: DIVW : case RISCVISD :: DIVUW : case RISCVISD :: REMUW : case RISCVISD :: ROLW : case RISCVISD :: RORW : case RISCVISD :: GREVIW : case RISCVISD :: GORCIW : case RISCVISD :: FSLW : case RISCVISD :: FSRW : return 33 ; case RISCVISD :: VMV_X_S : if ( Op . getOperand ( 0 ) . getScalarValueSizeInBits ( ) > Subtarget . getXLen ( ) ) return 1 ; return Subtarget . getXLen ( ) - Op . getOperand ( 0 ) . getScalarValueSizeInBits ( ) + 1 ; } return 1 ; } </s>

Determine the number of bits in the operation that are sign bits .

RISCV RISCV RISCVISD::SLLW RISCVISD::SRAW RISCVISD::SRLW RISCVISD::DIVW RISCVISD::DIVUW RISCVISD::REMUW RISCVISD::ROLW RISCVISD::RORW RISCVISD::GREVIW RISCVISD::GORCIW RISCVISD::FSLW RISCVISD::FSRW 33 RISCVISD::VMV_X_S 0 1 0 1 1


"Trying to spill a register in naked function "

Store the specified register of the given register class to the specified stack frame index .


<s> bool MipsSEInstrInfo :: isCopyInstr ( const MachineInstr & MI , const MachineOperand * & Src , const MachineOperand * & Dest ) const { bool isDSPControlWrite = false ; if ( isReadOrWriteToDSPReg ( MI , isDSPControlWrite ) ) { if ( ! MI . getOperand ( 1 ) . isImm ( ) || MI . getOperand ( 1 ) . getImm ( ) != ( 1 << 4 ) ) return false ; else if ( isDSPControlWrite ) { Src = & MI . getOperand ( 0 ) ; Dest = & MI . getOperand ( 2 ) ; } else { Dest = & MI . getOperand ( 0 ) ; Src = & MI . getOperand ( 2 ) ; } return true ; } else if ( MI . isMoveReg ( ) || isORCopyInst ( MI ) ) { Dest = & MI . getOperand ( 0 ) ; Src = & MI . getOperand ( 1 ) ; return true ; } return false ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


<s> bool NVPTXLowerKernelArgs :: runOnFunction ( Function & F ) { if ( ! isKernelFunction ( F ) ) return false ; for ( Argument & Arg : F . args ( ) ) { if ( Arg . getType ( ) -> isPointerTy ( ) ) { if ( Arg . hasByValAttr ( ) ) handleByValParam ( & Arg ) ; else if ( TM && TM -> getDrvInterface ( ) == NVPTX :: CUDA ) handlePointerParam ( & Arg ) ; } } return true ; } </s>


<s> unsigned getNumFixupKinds ( ) const { return 2 ; } </s>

Get the number of target specific fixup kinds .


<s> static bool arm_can_inline_p ( tree caller , tree callee ) { tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET ( caller ) ; tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET ( callee ) ; struct cl_target_option * caller_opts = TREE_TARGET_OPTION ( caller_tree ? caller_tree : target_option_default_node ) ; struct cl_target_option * callee_opts = TREE_TARGET_OPTION ( callee_tree ? callee_tree : target_option_default_node ) ; const struct arm_fpu_desc * caller_fpu = & all_fpus [ caller_opts -> x_arm_fpu_index ] ; const struct arm_fpu_desc * callee_fpu = & all_fpus [ callee_opts -> x_arm_fpu_index ] ; if ( ( caller_fpu -> features & callee_fpu -> features ) != callee_fpu -> features ) return false ; if ( callee_fpu -> model != caller_fpu -> model || callee_fpu -> regs != callee_fpu -> regs ) return false ; return true ; } </s>

Hook to determine if one function can safely inline another .


<s> rtx rs6000_allocate_stack_temp ( machine_mode mode , bool offsettable_p , bool reg_reg_p ) { rtx stack = assign_stack_temp ( mode , GET_MODE_SIZE ( mode ) ) ; rtx addr = XEXP ( stack , 0 ) ; int strict_p = ( reload_in_progress || reload_completed ) ; if ( ! legitimate_indirect_address_p ( addr , strict_p ) ) { if ( offsettable_p && ! rs6000_legitimate_offset_address_p ( mode , addr , strict_p , true ) ) stack = replace_equiv_address ( stack , copy_addr_to_reg ( addr ) ) ; else if ( reg_reg_p && ! legitimate_indexed_address_p ( addr , strict_p ) ) stack = replace_equiv_address ( stack , copy_addr_to_reg ( addr ) ) ; } return stack ; } </s>

Allocate a stack temp and fixup the address so it meets the particular memory requirements ( either offetable or REG+REG addressing ) .


<s> int AArch64TargetLowering :: getScalingFactorCost ( const AddrMode & AM , Type * Ty ) const { if ( isLegalAddressingMode ( AM , Ty ) ) return AM . Scale != 0 && AM . Scale != 1 ; return - 1 ; } </s>

Return the cost of the scaling factor used in the addressing mode represented by AM for this target , for a load/store of the specified type .


<s> void visium_profile_hook ( void ) { visium_frame_needed = true ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , "mcount" ) , LCT_NORMAL , VOIDmode ) ; } </s>

Profiling support . Just a call to MCOUNT is needed . No labelled counter location is involved . Proper support for __builtin_return_address is also required , which is fairly straightforward provided a frame gets created .


"WebAssembly hasn't implemented computed gotos"

LowerOperation - Provide custom lowering hooks for some operations .


<s> void X86IntelInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & OS ) { printInstFlags ( MI , OS , STI ) ; if ( MI -> getOpcode ( ) == X86 :: DATA16_PREFIX && STI . getFeatureBits ( ) [ X86 :: Is16Bit ] ) { OS << "\tdata32" ; } else if ( ! printAliasInstr ( MI , Address , OS ) && ! printVecCompareInstr ( MI , OS ) ) printInstruction ( MI , Address , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAnyX86InstComments ( MI , * CommentStream , MII ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> static bool bfin_class_likely_spilled_p ( reg_class_t rclass ) { switch ( rclass ) { case PREGS_CLOBBERED : case PROLOGUE_REGS : case P0REGS : case D0REGS : case D1REGS : case D2REGS : case CCREGS : return true ; default : break ; } return false ; } </s>


"\t.frame\t%s,%ld,%s\t\t# vars= %ld, regs= %d, args= %d\n"

Set up the stack and frame ( if desired ) for the function .


<s> bool ARMGlobalMerge :: doInitialization ( Module & M ) { SmallVector < GlobalVariable * , 16 > Globals , ConstGlobals ; const TargetData * TD = TLI -> getTargetData ( ) ; unsigned MaxOffset = TLI -> getMaximalGlobalOffset ( ) ; bool Changed = false ; for ( Module :: global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ; I != E ; ++ I ) { if ( ! I -> hasLocalLinkage ( ) || I -> isThreadLocal ( ) || I -> hasSection ( ) ) continue ; if ( I -> getAlignment ( ) != 0 ) continue ; if ( I -> getName ( ) . startswith ( "llvm." ) || I -> getName ( ) . startswith ( ".llvm." ) ) continue ; if ( TD -> getTypeAllocSize ( I -> getType ( ) ) < MaxOffset ) { if ( I -> isConstant ( ) ) ConstGlobals . push_back ( I ) ; else Globals . push_back ( I ) ; } } if ( Globals . size ( ) > 1 ) Changed |= doMerge ( Globals , M , false ) ; return Changed ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> static bool mips_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) { if ( mips_abi == ABI_EABI ) { int size ; if ( arg . mode == DImode || arg . mode == DFmode || arg . mode == DQmode || arg . mode == UDQmode || arg . mode == DAmode || arg . mode == UDAmode ) return 0 ; size = arg . type_size_in_bytes ( ) ; return size == - 1 || size > UNITS_PER_WORD ; } else { return targetm . calls . must_pass_in_stack ( arg ) ; } } </s>

Return nonzero when an argument must be passed by reference .


<s> unsigned RISCVInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : return 0 ; case RISCV :: SB : case RISCV :: SH : case RISCV :: SW : case RISCV :: FSW : case RISCV :: SD : case RISCV :: FSD : break ; } if ( MI . getOperand ( 0 ) . isFI ( ) && MI . getOperand ( 1 ) . isImm ( ) && MI . getOperand ( 1 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 0 ) . getIndex ( ) ; return MI . getOperand ( 2 ) . getReg ( ) ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> const TargetRegisterClass * MSP430RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & MSP430 :: GR16RegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> static int decide_alignment ( int align , enum stringop_alg alg , int expected_size , machine_mode move_mode ) { int desired_align = 0 ; gcc_assert ( alg != no_stringop ) ; if ( alg == libcall ) return 0 ; if ( move_mode == VOIDmode ) return 0 ; desired_align = GET_MODE_SIZE ( move_mode ) ; if ( TARGET_CPU_P ( PENTIUMPRO ) && ( alg == rep_prefix_4_byte || alg == rep_prefix_1_byte ) ) desired_align = 8 ; if ( optimize_size ) desired_align = 1 ; if ( desired_align < align ) desired_align = align ; if ( expected_size != - 1 && expected_size < 4 ) desired_align = align ; return desired_align ; } </s>

Decide on alignment . We know that the operand is already aligned to ALIGN ( ALIGN can be based on profile feedback and thus it is not 100 % guaranteed ) .


<s> bool enableIndirectBrExpand ( ) const override { return useIndirectThunkBranches ( ) ; } </s>

If we are using indirect thunks , we need to expand indirectbr to avoid it lowering to an actual indirect jump .


<s> bool AArch64InstrInfo :: shouldOutlineFromFunctionByDefault ( MachineFunction & MF ) const { return MF . getFunction ( ) . hasMinSize ( ) ; } </s>

Return true if the function should be outlined from by default .


<s> bool AMDGPUPassConfig :: addPreEmitPass ( ) { const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . device ( ) -> getGeneration ( ) <= AMDGPUDeviceInfo :: HD6XXX ) { addPass ( createAMDGPUCFGPreparationPass ( * TM ) ) ; addPass ( createAMDGPUCFGStructurizerPass ( * TM ) ) ; addPass ( createR600ExpandSpecialInstrsPass ( * TM ) ) ; addPass ( & FinalizeMachineBundlesID ) ; } else { addPass ( createSILowerControlFlowPass ( * TM ) ) ; } return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static int pa_arg_partial_bytes ( cumulative_args_t cum_v , machine_mode mode , tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; unsigned int max_arg_words = 8 ; unsigned int offset = 0 ; if ( ! TARGET_64BIT ) return 0 ; if ( FUNCTION_ARG_SIZE ( mode , type ) > 1 && ( cum -> words & 1 ) ) offset = 1 ; if ( cum -> words + offset + FUNCTION_ARG_SIZE ( mode , type ) <= max_arg_words ) return 0 ; else if ( cum -> words + offset >= max_arg_words ) return 0 ; else return ( max_arg_words - cum -> words - offset ) * UNITS_PER_WORD ; } </s>

If this arg would be passed totally in registers or totally on the stack , then this routine should return zero .


<s> bool ARMAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AFI = MF . getInfo < ARMFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) { NaClAlignAllJumpTargetsAndConstantPools ( MF ) ; } SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = MF . getFunction ( ) -> hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer . BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer . EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer . EmitCOFFSymbolType ( Type ) ; OutStreamer . EndCOFFSymbolDef ( ) ; } EmitFunctionHeader ( ) ; EmitFunctionBody ( ) ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> unsigned RISCVInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : return 0 ; case RISCV :: LB : case RISCV :: LBU : case RISCV :: LH : case RISCV :: LHU : case RISCV :: FLH : case RISCV :: LW : case RISCV :: FLW : case RISCV :: LWU : case RISCV :: LD : case RISCV :: FLD : case RISCV :: LC_64 : case RISCV :: LC_128 : case RISCV :: CLB : case RISCV :: CLBU : case RISCV :: CLH : case RISCV :: CLHU : case RISCV :: CLW : case RISCV :: CFLW : case RISCV :: CLWU : case RISCV :: CLD : case RISCV :: CFLD : case RISCV :: CLC_64 : case RISCV :: CLC_128 : break ; } if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


"MMIX Internal: Last named vararg would not fit in a register"


<s> bool mips_linked_madd_p ( rtx prev , rtx insn ) { rtx x ; x = single_set ( insn ) ; if ( x == 0 ) return false ; x = SET_SRC ( x ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 0 ) ) == MULT && reg_set_p ( XEXP ( x , 1 ) , prev ) ) return true ; if ( GET_CODE ( x ) == MINUS && GET_CODE ( XEXP ( x , 1 ) ) == MULT && reg_set_p ( XEXP ( x , 0 ) , prev ) ) return true ; return false ; } </s>

Return true if INSN is a multiply-add or multiply-subtract instruction and PREV assigns to the accumulator operand .


<s> bool LC2200PassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( ) ) ; return false ; } </s>

This method should install a ( global ) instruction selector pass , which converts possibly generic instructions to fully target-specific instructions , thereby constraining all generic virtual registers to register classes .


<s> ScheduleHazardRecognizer * ARMBaseInstrInfo :: CreateTargetMIHazardRecognizer ( const InstrItineraryData * II , const ScheduleDAGMI * DAG ) const { MultiHazardRecognizer * MHR = new MultiHazardRecognizer ( ) ; if ( Subtarget . isCortexM7 ( ) && ! DAG -> hasVRegLiveness ( ) ) MHR -> AddHazardRecognizer ( std :: make_unique < ARMBankConflictHazardRecognizer > ( DAG , 0x4 , true ) ) ; auto BHR = TargetInstrInfo :: CreateTargetMIHazardRecognizer ( II , DAG ) ; MHR -> AddHazardRecognizer ( std :: unique_ptr < ScheduleHazardRecognizer > ( BHR ) ) ; return MHR ; } </s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .


<s> void GCNSubtarget :: adjustSchedDependency ( SUnit * Def , int DefOpIdx , SUnit * Use , int UseOpIdx , SDep & Dep ) const { if ( Dep . getKind ( ) != SDep :: Kind :: Data || ! Dep . getReg ( ) || ! Def -> isInstr ( ) || ! Use -> isInstr ( ) ) return ; MachineInstr * DefI = Def -> getInstr ( ) ; MachineInstr * UseI = Use -> getInstr ( ) ; if ( DefI -> isBundle ( ) ) { const SIRegisterInfo * TRI = getRegisterInfo ( ) ; auto Reg = Dep . getReg ( ) ; MachineBasicBlock :: const_instr_iterator I ( DefI -> getIterator ( ) ) ; MachineBasicBlock :: const_instr_iterator E ( DefI -> getParent ( ) -> instr_end ( ) ) ; unsigned Lat = 0 ; for ( ++ I ; I != E && I -> isBundledWithPred ( ) ; ++ I ) { if ( I -> modifiesRegister ( Reg , TRI ) ) Lat = InstrInfo . getInstrLatency ( getInstrItineraryData ( ) , * I ) ; else if ( Lat ) -- Lat ; } Dep . setLatency ( Lat ) ; } else if ( UseI -> isBundle ( ) ) { const SIRegisterInfo * TRI = getRegisterInfo ( ) ; auto Reg = Dep . getReg ( ) ; MachineBasicBlock :: const_instr_iterator I ( UseI -> getIterator ( ) ) ; MachineBasicBlock :: const_instr_iterator E ( UseI -> getParent ( ) -> instr_end ( ) ) ; unsigned Lat = InstrInfo . getInstrLatency ( getInstrItineraryData ( ) , * DefI ) ; for ( ++ I ; I != E && I -> isBundledWithPred ( ) && Lat ; ++ I ) { if ( I -> readsRegister ( Reg , TRI ) ) break ; -- Lat ; } Dep . setLatency ( Lat ) ; } else if ( Dep . getLatency ( ) == 0 && Dep . getReg ( ) == AMDGPU :: VCC_LO ) { Dep . setLatency ( InstrInfo . getSchedModel ( ) . computeOperandLatency ( DefI , DefOpIdx , UseI , UseOpIdx ) ) ; } } </s>

Perform target specific adjustments to the latency of a schedule dependency .


<s>
Function
*
MBlazeIntrinsicInfo
::
getDeclaration
(
Module
*
M
,
unsigned
IntrID
,
Type
*
*
Tys
,
unsigned
numTy
)
const
{
assert
(
!
isOverloaded
(
IntrID
)
&&
"MBlaze intrinsics are not overloaded"
)
;
AttributeSet
AList
=
getAttributes
(
M
->
getContext
(
)
,
(
mblazeIntrinsic
::
ID
)
IntrID
)
;
return
cast
<
Function
>
(
M
->
getOrInsertFunction
(
getName
(
IntrID
)
,
getType
(
M
->
getContext
(
)
,
IntrID
)
,
AList
)
)
;
}
</s>

Create or insert an LLVM Function declaration for an intrinsic , and return it .

MBlaze
MBlaze
"MBlaze intrinsics are not overloaded"
mblazeIntrinsic::ID


<s> static rtx_insn * emit_sp_adjust ( int offset , int * next_scratch_regno , bool frame_related , rtx reg_notes ) { rtx to_add ; rtx imm_rtx = GEN_INT ( offset ) ; rtx pat ; rtx_insn * insn ; if ( satisfies_constraint_J ( imm_rtx ) ) { to_add = imm_rtx ; } else { rtx tmp = gen_rtx_REG ( Pmode , ( * next_scratch_regno ) -- ) ; tilegx_expand_set_const64 ( tmp , imm_rtx ) ; to_add = tmp ; } if ( TARGET_32BIT ) pat = gen_sp_adjust_32bit ( stack_pointer_rtx , stack_pointer_rtx , to_add ) ; else pat = gen_sp_adjust ( stack_pointer_rtx , stack_pointer_rtx , to_add ) ; insn = emit_insn ( pat ) ; REG_NOTES ( insn ) = reg_notes ; if ( frame_related ) { rtx real = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , imm_rtx ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , real ) ; } return insn ; } </s>

This emits code for 'sp += offset ' . The ABI only allows us to modify 'sp ' in a single 'addi ' or 'addli ' , so the backtracer understands it . Larger amounts can not use those instructions , so are added by placing the offset into a large register and using 'add ' . This happens after reload , so we need to expand it ourselves .


<s> static rtx frame_add ( rtx reg , HOST_WIDE_INT offset ) { gcc_assert ( ( offset & 0x3 ) == 0 ) ; if ( ! offset ) return NULL_RTX ; return frame_move ( reg , plus_constant ( Pmode , reg , offset ) ) ; } </s>

Emit a frame insn which adjusts a frame address register REG by OFFSET .


<s> bool M88kPassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( getOptLevel ( ) ) ) ; return false ; } </s>


<s> bool MipsPassConfig :: addPreEmitPass ( ) { PM . add ( createMipsDelaySlotFillerPass ( getMipsTargetMachine ( ) ) ) ; return true ; } </s>


<s> int neg_const_double_rtx_ok_for_fpa ( rtx x ) { REAL_VALUE_TYPE r ; int i ; if ( ! fp_consts_inited ) init_fp_table ( ) ; REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; r = REAL_VALUE_NEGATE ( r ) ; if ( REAL_VALUE_MINUS_ZERO ( r ) ) return 0 ; for ( i = 0 ; i < 8 ; i ++ ) if ( REAL_VALUES_EQUAL ( r , values_fp [ i ] ) ) return 1 ; return 0 ; } </s>

Return TRUE if rtx X is a valid immediate FPA constant .


<s>
bool
AArch64BranchFixup
::
isBBInRange
(
MachineInstr
*
MI
,
MachineBasicBlock
*
DestBB
,
unsigned
OffsetBits
)
{
int64_t
BrOffset
=
getOffsetOf
(
MI
)
;
int64_t
DestOffset
=
BBInfo
[
DestBB
->
getNumber
(
)
]
.
Offset
;
DEBUG
(
dbgs
(
)
<<
"Branch of destination BB#"
<<
DestBB
->
getNumber
(
)
<<
" from BB#"
<<
MI
->
getParent
(
)
->
getNumber
(
)
<<
" bits available="
<<
OffsetBits
<<
" from "
<<
getOffsetOf
(
MI
)
<<
" to "
<<
DestOffset
<<
" offset "
<<
int
(
DestOffset
BrOffset
)
<<
"\t"
<<
*
MI
)
;
return
isIntN
(
OffsetBits
,
DestOffset
BrOffset
)
;
}
</s>

isBBInRange - Returns true if the distance between specific MI and specific BB can fit in MI 's displacement field .

AArch64
AArch64
"Branch of destination BB#"
" from BB#"
" bits available="
" from "
" to "
" offset "
"\t"


"deleting because the set register is never used.\n"

Remove any SETs where the destination is unneeded .


Map a target register to an equivalent SEH register number .


<s> static tree aarch64_general_add_builtin ( const char * name , tree type , unsigned int code , tree attrs = NULL_TREE ) { code = ( code << AARCH64_BUILTIN_SHIFT ) | AARCH64_BUILTIN_GENERAL ; return add_builtin_function ( name , type , code , BUILT_IN_MD , NULL , attrs ) ; } </s>

Wrapper around add_builtin_function . NAME is the name of the built-in function , TYPE is the function type , CODE is the function subcode ( relative to AARCH64_BUILTIN_GENERAL ) , and ATTRS is the function attributes .


<s> static int loongarch_symbol_insns ( enum loongarch_symbol_type type , machine_mode mode ) { switch ( type ) { case SYMBOL_GOT_DISP : if ( ! TARGET_EXPLICIT_RELOCS && mode != MAX_MACHINE_MODE ) return 0 ; return 3 ; case SYMBOL_PCREL : case SYMBOL_TLS_IE : case SYMBOL_TLS_LE : return 2 ; case SYMBOL_TLSGD : case SYMBOL_TLSLDM : return 3 ; case SYMBOL_PCREL64 : return 5 ; case SYMBOL_TLS : return 0 ; } gcc_unreachable ( ) ; } </s>

Returns the number of instructions necessary to reference a symbol .