"should only be seeing stack pointer offset relative FrameIndex"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> void optimization_options ( int level , int size ATTRIBUTE_UNUSED ) { if ( level > 1 ) flag_schedule_insns = 0 ; if ( TARGET_MACHO ) flag_errno_math = 0 ; if ( optimize >= 1 ) flag_omit_frame_pointer = 2 ; flag_pcc_struct_return = 2 ; flag_asynchronous_unwind_tables = 2 ; SUBTARGET_OPTIMIZATION_OPTIONS ; } </s>

Change optimizations to be performed , depending on the optimization level . LEVEL is the optimization level specified ; 2 if ` -O2 ' is specified , 1 if ` -O ' is specified , and 0 if neither is specified . SIZE is nonzero if ` -Os ' is specified and zero otherwise .


<s>
SDValue
PPCTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_PPC
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
PPCISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
else
return
DAG
.
getNode
(
PPCISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool th_mempair_operands_p ( rtx operands [ 4 ] , bool load_p , machine_mode mode ) { rtx mem_1 , mem_2 , reg_1 , reg_2 ; if ( load_p ) { reg_1 = operands [ 0 ] ; mem_1 = operands [ 1 ] ; reg_2 = operands [ 2 ] ; mem_2 = operands [ 3 ] ; if ( ! REG_P ( reg_1 ) || ! REG_P ( reg_2 ) ) return false ; if ( th_mempair_load_overlap_p ( reg_1 , reg_2 , mem_1 ) ) return false ; if ( th_mempair_load_overlap_p ( reg_1 , reg_2 , mem_2 ) ) return false ; } else { mem_1 = operands [ 0 ] ; reg_1 = operands [ 1 ] ; mem_2 = operands [ 2 ] ; reg_2 = operands [ 3 ] ; } if ( ! REG_P ( reg_1 ) || ! GP_REG_P ( REGNO ( reg_1 ) ) || ! REG_P ( reg_2 ) || ! GP_REG_P ( REGNO ( reg_2 ) ) ) return false ; if ( ! MEM_P ( mem_1 ) || ! MEM_P ( mem_2 ) ) return false ; if ( MEM_VOLATILE_P ( mem_1 ) || MEM_VOLATILE_P ( mem_2 ) ) return false ; if ( riscv_slow_unaligned_access_p && known_lt ( MEM_ALIGN ( mem_1 ) , GET_MODE_SIZE ( mode ) * BITS_PER_UNIT ) ) return false ; bool reversed = false ; if ( ! th_mempair_check_consecutive_mems ( mode , & mem_1 , & mem_2 , & reversed ) ) return false ; if ( ( ! reversed && ! th_mempair_operand_p ( mem_1 , mode ) ) || ( reversed && ! th_mempair_operand_p ( mem_2 , mode ) ) ) return false ; gcc_assert ( known_eq ( GET_MODE_SIZE ( GET_MODE ( mem_1 ) ) , GET_MODE_SIZE ( GET_MODE ( mem_2 ) ) ) ) ; return true ; } </s>

Given OPERANDS of consecutive load/store , check if we can merge them into load-pair or store-pair instructions . LOAD is true if they are load instructions . MODE is the mode of memory operation .


<s> bool TPCAsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> static tree gen_stdcall_or_fastcall_suffix ( tree decl , tree id , bool fastcall ) { HOST_WIDE_INT total = 0 ; const char * old_str = IDENTIFIER_POINTER ( id != NULL_TREE ? id : DECL_NAME ( decl ) ) ; char * new_str , * p ; tree type = TREE_TYPE ( DECL_ORIGIN ( decl ) ) ; tree arg ; function_args_iterator args_iter ; gcc_assert ( TREE_CODE ( decl ) == FUNCTION_DECL ) ; if ( prototype_p ( type ) ) { if ( stdarg_p ( type ) ) return NULL_TREE ; FOREACH_FUNCTION_ARGS ( type , arg , args_iter ) { HOST_WIDE_INT parm_size ; HOST_WIDE_INT parm_boundary_bytes = PARM_BOUNDARY / BITS_PER_UNIT ; if ( ! COMPLETE_TYPE_P ( arg ) ) break ; parm_size = int_size_in_bytes ( arg ) ; if ( parm_size < 0 ) break ; parm_size = ( ( parm_size + parm_boundary_bytes - 1 ) / parm_boundary_bytes * parm_boundary_bytes ) ; total += parm_size ; } } p = new_str = XALLOCAVEC ( char , 1 + strlen ( old_str ) + 1 + 8 + 1 ) ; if ( fastcall ) * p ++ = FASTCALL_PREFIX ; sprintf ( p , "%s@" HOST_WIDE_INT_PRINT_DEC , old_str , total ) ; return get_identifier ( new_str ) ; } </s>

Return string which is the former assembler name modified with a suffix consisting of an atsign ( @ ) followed by the number of bytes of arguments . If FASTCALL is true , also add the FASTCALL_PREFIX .


<s> static inline HOST_WIDE_INT htm_spr_num ( enum rs6000_builtins code ) { if ( code == HTM_BUILTIN_GET_TFHAR || code == HTM_BUILTIN_SET_TFHAR ) return TFHAR_SPR ; else if ( code == HTM_BUILTIN_GET_TFIAR || code == HTM_BUILTIN_SET_TFIAR ) return TFIAR_SPR ; else if ( code == HTM_BUILTIN_GET_TEXASR || code == HTM_BUILTIN_SET_TEXASR ) return TEXASR_SPR ; gcc_assert ( code == HTM_BUILTIN_GET_TEXASRU || code == HTM_BUILTIN_SET_TEXASRU ) ; return TEXASRU_SPR ; } </s>

Return the appropriate SPR number associated with the given builtin .


<s>
void
SparcInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
SP
::
IntRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
SP
::
ORrr
)
,
DestReg
)
.
addReg
(
SP
::
G0
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
if
(
SP
::
FPRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
SP
::
FMOVS
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
if
(
SP
::
DFPRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
Subtarget
.
isV9
(
)
SP
::
FMOVD
:
SP
::
FpMOVD
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
</s>

Sparc
Sparc
SP::IntRegsRegClass
SP::ORrr
SP::G0
SP::FPRegsRegClass
SP::FMOVS
SP::DFPRegsRegClass
SP::FMOVD
SP::FpMOVD
"Impossible reg-to-reg copy"


<s> int call_insn_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { if ( GET_CODE ( op ) == MEM ) { rtx inside = XEXP ( op , 0 ) ; if ( register_operand ( inside , Pmode ) ) return 1 ; if ( CONSTANT_ADDRESS_P ( inside ) ) return 1 ; } return 0 ; } </s>

Test for a valid operand for a call instruction . Do n't allow the arg pointer register or virtual regs since they may change into reg + const , which the patterns ca n't handle yet .


<s> static void nvptx_call_args ( rtx arg , tree fntype ) { if ( ! cfun -> machine -> doing_call ) { cfun -> machine -> doing_call = true ; cfun -> machine -> is_varadic = false ; cfun -> machine -> num_args = 0 ; if ( fntype && stdarg_p ( fntype ) ) { cfun -> machine -> is_varadic = true ; cfun -> machine -> has_varadic = true ; cfun -> machine -> num_args ++ ; } } if ( REG_P ( arg ) && arg != pc_rtx ) { cfun -> machine -> num_args ++ ; cfun -> machine -> call_args = alloc_EXPR_LIST ( VOIDmode , arg , cfun -> machine -> call_args ) ; } } </s>

Implement the TARGET_CALL_ARGS hook . Record information about one argument to the next call .


<s> SDValue getInstr ( unsigned MachineOpc , const SDLoc & dl , MVT Ty , ArrayRef < SDValue > Ops , SelectionDAG & DAG ) const { SDNode * N = DAG . getMachineNode ( MachineOpc , dl , Ty , Ops ) ; return SDValue ( N , 0 ) ; } </s>

Returns the representative MachineInstr for this SUnit .


<s>
MachineBasicBlock
*
NyuziTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
case
Nyuzi
::
SELECTI
:
case
Nyuzi
::
SELECTF
:
case
Nyuzi
::
SELECTVI
:
case
Nyuzi
::
SELECTVF
:
case
Nyuzi
::
SELECTMASK
:
return
EmitSelectCC
(
MI
,
BB
)
;
case
Nyuzi
::
ATOMIC_LOAD_ADDR
:
return
EmitAtomicBinary
(
MI
,
BB
,
Nyuzi
::
ADDISSS
)
;
case
Nyuzi
::
ATOMIC_LOAD_ADDI
:
return
EmitAtomicBinary
(
MI
,
BB
,
Nyuzi
::
ADDISSI
)
;
case
Nyuzi
::
ATOMIC_LOAD_SUBR
:
return
EmitAtomicBinary
(
MI
,
BB
,
Nyuzi
::
SUBISSS
)
;
case
Nyuzi
::
ATOMIC_LOAD_NANDR
:
return
EmitAtomicBinary
(
MI
,
BB
,
Nyuzi
::
ANDSSS
,
true
)
;
case
Nyuzi
::
ATOMIC_LOAD_SUBI
:
return
EmitAtomicBinary
(
MI
,
BB
,
Nyuzi
::
SUBISSI
)
;
case
Nyuzi
::
ATOMIC_LOAD_ANDR
:
return
EmitAtomicBinary
(
MI
,
BB
,
Nyuzi
::
ANDSSS
)
;
case
Nyuzi
::
ATOMIC_LOAD_ANDI
:
return
EmitAtomicBinary
(
MI
,
BB
,
Nyuzi
::
ANDSSI
)
;
case
Nyuzi
::
ATOMIC_LOAD_ORR
:
return
EmitAtomicBinary
(
MI
,
BB
,
Nyuzi
::
ORSSS
)
;
case
Nyuzi
::
ATOMIC_LOAD_ORI
:
return
EmitAtomicBinary
(
MI
,
BB
,
Nyuzi
::
ORSSI
)
;
case
Nyuzi
::
ATOMIC_LOAD_XORR
:
return
EmitAtomicBinary
(
MI
,
BB
,
Nyuzi
::
XORSSS
)
;
case
Nyuzi
::
ATOMIC_LOAD_XORI
:
return
EmitAtomicBinary
(
MI
,
BB
,
Nyuzi
::
XORSSI
)
;
case
Nyuzi
::
ATOMIC_LOAD_NANDI
:
return
EmitAtomicBinary
(
MI
,
BB
,
Nyuzi
::
ANDSSI
,
true
)
;
case
Nyuzi
::
ATOMIC_SWAP
:
return
EmitAtomicBinary
(
MI
,
BB
,
0
)
;
case
Nyuzi
::
ATOMIC_CMP_SWAP
:
return
EmitAtomicCmpSwap
(
MI
,
BB
)
;
default
:
llvm_unreachable
(
"unknown atomic operation"
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> void s390_expand_vec_compare_cc ( rtx target , enum rtx_code code , rtx cmp1 , rtx cmp2 , bool all_p ) { enum rtx_code new_code = code ; machine_mode cmp_mode , full_cmp_mode , scratch_mode ; rtx tmp_reg = gen_reg_rtx ( SImode ) ; bool swap_p = false ; if ( GET_MODE_CLASS ( GET_MODE ( cmp1 ) ) == MODE_VECTOR_INT ) { switch ( code ) { case EQ : cmp_mode = CCVEQmode ; break ; case NE : cmp_mode = CCVEQmode ; break ; case GT : cmp_mode = CCVHmode ; break ; case GE : cmp_mode = CCVHmode ; new_code = LE ; swap_p = true ; break ; case LT : cmp_mode = CCVHmode ; new_code = GT ; swap_p = true ; break ; case LE : cmp_mode = CCVHmode ; new_code = LE ; break ; case GTU : cmp_mode = CCVHUmode ; break ; case GEU : cmp_mode = CCVHUmode ; new_code = LEU ; swap_p = true ; break ; case LTU : cmp_mode = CCVHUmode ; new_code = GTU ; swap_p = true ; break ; case LEU : cmp_mode = CCVHUmode ; new_code = LEU ; break ; default : gcc_unreachable ( ) ; } scratch_mode = GET_MODE ( cmp1 ) ; } else if ( GET_MODE ( cmp1 ) == V2DFmode ) { switch ( code ) { case EQ : cmp_mode = CCVEQmode ; break ; case NE : cmp_mode = CCVEQmode ; break ; case GT : cmp_mode = CCVFHmode ; break ; case GE : cmp_mode = CCVFHEmode ; break ; case UNLE : cmp_mode = CCVFHmode ; break ; case UNLT : cmp_mode = CCVFHEmode ; break ; case LT : cmp_mode = CCVFHmode ; new_code = GT ; swap_p = true ; break ; case LE : cmp_mode = CCVFHEmode ; new_code = GE ; swap_p = true ; break ; default : gcc_unreachable ( ) ; } scratch_mode = V2DImode ; } else gcc_unreachable ( ) ; if ( ! all_p ) switch ( cmp_mode ) { case CCVEQmode : full_cmp_mode = CCVEQANYmode ; break ; case CCVHmode : full_cmp_mode = CCVHANYmode ; break ; case CCVHUmode : full_cmp_mode = CCVHUANYmode ; break ; case CCVFHmode : full_cmp_mode = CCVFHANYmode ; break ; case CCVFHEmode : full_cmp_mode = CCVFHEANYmode ; break ; default : gcc_unreachable ( ) ; } else full_cmp_mode = cmp_mode ; if ( swap_p ) { rtx tmp = cmp2 ; cmp2 = cmp1 ; cmp1 = tmp ; } emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , gen_rtx_SET ( gen_rtx_REG ( cmp_mode , CC_REGNUM ) , gen_rtx_COMPARE ( cmp_mode , cmp1 , cmp2 ) ) , gen_rtx_CLOBBER ( VOIDmode , gen_rtx_SCRATCH ( scratch_mode ) ) ) ) ) ; emit_move_insn ( target , const0_rtx ) ; emit_move_insn ( tmp_reg , const1_rtx ) ; emit_move_insn ( target , gen_rtx_IF_THEN_ELSE ( SImode , gen_rtx_fmt_ee ( new_code , VOIDmode , gen_rtx_REG ( full_cmp_mode , CC_REGNUM ) , const0_rtx ) , target , tmp_reg ) ) ; } </s>

Expand the comparison CODE of CMP1 and CMP2 and copy 1 or 0 into TARGET if either all ( ALL_P is true ) or any ( ALL_P is false ) of the elements in CMP1 and CMP2 fulfill the comparison .


<s> bool SHUXIFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> void function_arg_advance ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int named ATTRIBUTE_UNUSED ) { int bytes = avr_num_arg_regs ( mode , type ) ; cum -> nregs -= bytes ; cum -> regno -= bytes ; if ( cum -> nregs <= 0 ) { cum -> nregs = 0 ; cum -> regno = FIRST_CUM_REG ; } } </s>

Handle the FUNCTION_ARG_ADVANCE macro . Update the data in CUM to advance over an argument of mode MODE and data type TYPE . TYPE is null for libcalls where that information may not be available .


<s> StringRef getPassName ( ) const override { return ARM_LOW_OVERHEAD_LOOPS_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> const uint16_t * VideocoreRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_VC4_SaveList ; } </s>


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( ( N -> getOpcode ( ) == X86ISD :: CALL && ! Subtarget -> callRegIndirect ( ) ) || ( N -> getOpcode ( ) == X86ISD :: TC_RETURN && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; EVT SrcVT = N -> getOperand ( 0 ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( 0 ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; bool SrcIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> static bool sh_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { return ( 1 && ( ! TARGET_SHCOMPACT || crtl -> args . info . stack_regs == 0 ) && ! sh_cfun_interrupt_handler_p ( ) && ( ! flag_pic || ( decl && ! TREE_PUBLIC ( decl ) ) || ( decl && DECL_VISIBILITY ( decl ) != VISIBILITY_DEFAULT ) ) ) ; } </s>

If PIC , we can not make sibling calls to global functions because the PLT requires r12 to be live .


<s> long compute_frame_size ( int size ) { int regno ; if ( cfun -> static_chain_decl != NULL ) size += ( 1 * UNITS_PER_WORD ) ; xtensa_callee_save_size = 0 ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; ++ regno ) { if ( xtensa_call_save_reg ( regno ) ) xtensa_callee_save_size += UNITS_PER_WORD ; } xtensa_current_frame_size = XTENSA_STACK_ALIGN ( size + xtensa_callee_save_size + crtl -> outgoing_args_size + ( WINDOW_SIZE * UNITS_PER_WORD ) ) ; xtensa_callee_save_size = XTENSA_STACK_ALIGN ( xtensa_callee_save_size ) ; return xtensa_current_frame_size ; } </s>

Typical stack layout should looks like this after the function 's prologue : | | -- ^ | | \ | | | arguments saved | Increasing | | on the stack | addresses PARENT arg pointer - > | | / -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - | | - space for argument split between regs & stack -- CHILD | | \ < -- ( return address here ) | | other call | | saved registers | | / -- frame pointer - > | | \ ___ | | local | | | variables |f | | / |r -- |a | | \ |m | | outgoing |e | | arguments | | Decreasing ( hard ) frame pointer | | / | | addresses and stack pointer - > | | / _|_ | -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- V


<s> static rtx pop ( int rn ) { rtx reg = gen_rtx_REG ( word_mode , rn ) ; rtx x ; if ( ! TARGET_NORMAL_MODE ) x = gen_pop_h8300hs_advanced ( reg ) ; else x = gen_pop_h8300hs_normal ( reg ) ; x = emit_insn ( x ) ; add_reg_note ( x , REG_INC , stack_pointer_rtx ) ; return x ; } </s>

Output RTL to pop register RN from the stack .


<s> static bool ix86_noce_conversion_profitable_p ( rtx_insn * seq , struct noce_if_info * if_info ) { if ( TARGET_ONE_IF_CONV_INSN && if_info -> speed_p ) { int cmov_cnt = 0 ; for ( rtx_insn * insn = seq ; insn ; insn = NEXT_INSN ( insn ) ) { rtx set = single_set ( insn ) ; if ( ! set ) continue ; if ( GET_CODE ( SET_SRC ( set ) ) != IF_THEN_ELSE ) continue ; rtx src = SET_SRC ( set ) ; machine_mode mode = GET_MODE ( src ) ; if ( GET_MODE_CLASS ( mode ) != MODE_INT && GET_MODE_CLASS ( mode ) != MODE_FLOAT ) continue ; if ( ( ! REG_P ( XEXP ( src , 1 ) ) && ! MEM_P ( XEXP ( src , 1 ) ) ) || ( ! REG_P ( XEXP ( src , 2 ) ) && ! MEM_P ( XEXP ( src , 2 ) ) ) ) continue ; if ( ++ cmov_cnt > 1 ) return false ; } } return default_noce_conversion_profitable_p ( seq , if_info ) ; } </s>

Return true if SEQ is a good candidate as a replacement for the if-convertible sequence described in IF_INFO .


<s> LoadInst * X86TargetLowering :: lowerIdempotentRMWIntoFencedLoad ( AtomicRMWInst * AI ) const { const X86Subtarget & Subtarget = getTargetMachine ( ) . getSubtarget < X86Subtarget > ( ) ; unsigned NativeWidth = Subtarget . is64Bit ( ) ? 64 : 32 ; const Type * MemType = AI -> getType ( ) ; if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) return nullptr ; auto Builder = IRBuilder < > ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SynchScope = AI -> getSynchScope ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; auto Ptr = AI -> getPointerOperand ( ) ; if ( SynchScope == SingleThread ) { return nullptr ; } else if ( hasMFENCE ( Subtarget ) ) { Function * MFence = llvm :: Intrinsic :: getDeclaration ( M , Intrinsic :: x86_sse2_mfence ) ; Builder . CreateCall ( MFence ) ; } else { return nullptr ; } LoadInst * Loaded = Builder . CreateAlignedLoad ( Ptr , AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ) ; Loaded -> setAtomic ( Order , SynchScope ) ; AI -> replaceAllUsesWith ( Loaded ) ; AI -> eraseFromParent ( ) ; return Loaded ; } </s>

On some platforms , an AtomicRMW that never actually modifies the value ( such as fetch_add of 0 ) can be turned into a fence followed by an atomic load .


"%qs is only valid for the cell processor"

"%qs requires ISA 3.0 IEEE 128-bit floating point"

"%qs requires the %qs (or newer), and %qs or %qs options"

"%qs is not supported with the current options"

Raise an error message for a builtin function that is called without the appropriate target options being set .


<s> bool Mips16RegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { DebugLoc DL ; const TargetInstrInfo & TII = * MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; TII . copyPhysReg ( MBB , I , DL , Mips :: T0 , Reg , true ) ; TII . copyPhysReg ( MBB , UseMI , DL , Reg , Mips :: T0 , true ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .


<s> static void ix86_function_specific_restore ( struct gcc_options * opts , struct cl_target_option * ptr ) { enum processor_type old_tune = ix86_tune ; enum processor_type old_arch = ix86_arch ; unsigned HOST_WIDE_INT ix86_arch_mask ; int i ; opts -> x_flag_pic = flag_pic ; ix86_arch = ( enum processor_type ) ptr -> arch ; ix86_schedule = ( enum attr_cpu ) ptr -> schedule ; ix86_tune = ( enum processor_type ) ptr -> tune ; x86_prefetch_sse = ptr -> prefetch_sse ; opts -> x_ix86_branch_cost = ptr -> branch_cost ; ix86_tune_defaulted = ptr -> tune_defaulted ; ix86_arch_specified = ptr -> arch_specified ; opts -> x_ix86_isa_flags_explicit = ptr -> x_ix86_isa_flags_explicit ; opts -> x_ix86_isa_flags2_explicit = ptr -> x_ix86_isa_flags2_explicit ; opts -> x_recip_mask_explicit = ptr -> x_recip_mask_explicit ; opts -> x_ix86_arch_string = ptr -> x_ix86_arch_string ; opts -> x_ix86_tune_string = ptr -> x_ix86_tune_string ; opts -> x_ix86_cmodel = ptr -> x_ix86_cmodel ; opts -> x_ix86_abi = ptr -> x_ix86_abi ; opts -> x_ix86_asm_dialect = ptr -> x_ix86_asm_dialect ; opts -> x_ix86_branch_cost = ptr -> x_ix86_branch_cost ; opts -> x_ix86_dump_tunes = ptr -> x_ix86_dump_tunes ; opts -> x_ix86_force_align_arg_pointer = ptr -> x_ix86_force_align_arg_pointer ; opts -> x_ix86_force_drap = ptr -> x_ix86_force_drap ; opts -> x_ix86_incoming_stack_boundary_arg = ptr -> x_ix86_incoming_stack_boundary_arg ; opts -> x_ix86_pmode = ptr -> x_ix86_pmode ; opts -> x_ix86_preferred_stack_boundary_arg = ptr -> x_ix86_preferred_stack_boundary_arg ; opts -> x_ix86_recip_name = ptr -> x_ix86_recip_name ; opts -> x_ix86_regparm = ptr -> x_ix86_regparm ; opts -> x_ix86_section_threshold = ptr -> x_ix86_section_threshold ; opts -> x_ix86_sse2avx = ptr -> x_ix86_sse2avx ; opts -> x_ix86_stack_protector_guard = ptr -> x_ix86_stack_protector_guard ; opts -> x_ix86_stringop_alg = ptr -> x_ix86_stringop_alg ; opts -> x_ix86_tls_dialect = ptr -> x_ix86_tls_dialect ; opts -> x_ix86_tune_ctrl_string = ptr -> x_ix86_tune_ctrl_string ; opts -> x_ix86_tune_memcpy_strategy = ptr -> x_ix86_tune_memcpy_strategy ; opts -> x_ix86_tune_memset_strategy = ptr -> x_ix86_tune_memset_strategy ; opts -> x_ix86_tune_no_default = ptr -> x_ix86_tune_no_default ; opts -> x_ix86_veclibabi_type = ptr -> x_ix86_veclibabi_type ; ix86_tune_cost = processor_target_table [ ix86_tune ] . cost ; if ( opts -> x_optimize_size ) ix86_cost = & ix86_size_cost ; else ix86_cost = ix86_tune_cost ; if ( old_arch != ix86_arch ) { ix86_arch_mask = HOST_WIDE_INT_1U << ix86_arch ; for ( i = 0 ; i < X86_ARCH_LAST ; ++ i ) ix86_arch_features [ i ] = ! ! ( initial_ix86_arch_features [ i ] & ix86_arch_mask ) ; } if ( old_tune != ix86_tune ) set_ix86_tune_features ( ix86_tune , false ) ; } </s>


<s> MachineOperand * SIInstrInfo :: getNamedOperand ( MachineInstr & MI , unsigned OperandName ) const { int Idx = AMDGPU :: getNamedOperandIdx ( MI . getOpcode ( ) , OperandName ) ; if ( Idx == - 1 ) return nullptr ; return & MI . getOperand ( Idx ) ; } </s>


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian , unsigned MinSVEVectorSizeInBitsOverride , unsigned MaxSVEVectorSizeInBitsOverride ) : AArch64GenSubtargetInfo ( TT , CPU , CPU , FS ) , ReserveXRegister ( AArch64 :: GPR64commonRegClass . getNumRegs ( ) ) , CustomCallSavedXRegs ( AArch64 :: GPR64commonRegClass . getNumRegs ( ) ) , IsLittle ( LittleEndian ) , MinSVEVectorSizeInBits ( MinSVEVectorSizeInBitsOverride ) , MaxSVEVectorSizeInBits ( MaxSVEVectorSizeInBitsOverride ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS , CPU ) ) , TSInfo ( ) , TLInfo ( TM , * this ) { if ( AArch64 :: isX18ReservedByDefault ( TT ) ) ReserveXRegister . set ( 18 ) ; CallLoweringInfo . reset ( new AArch64CallLowering ( * getTargetLowering ( ) ) ) ; InlineAsmLoweringInfo . reset ( new InlineAsmLowering ( getTargetLowering ( ) ) ) ; Legalizer . reset ( new AArch64LegalizerInfo ( * this ) ) ; auto * RBI = new AArch64RegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( createAArch64InstructionSelector ( * static_cast < const AArch64TargetMachine * > ( & TM ) , * this , * RBI ) ) ; RegBankInfo . reset ( RBI ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> void HexagonFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { auto & HRI = * MF . getSubtarget < HexagonSubtarget > ( ) . getRegisterInfo ( ) ; SavedRegs . resize ( HRI . getNumRegs ( ) ) ; if ( MF . getInfo < HexagonMachineFunctionInfo > ( ) -> hasEHReturn ( ) ) for ( const MCPhysReg * R = HRI . getCalleeSavedRegs ( & MF ) ; * R ; ++ R ) SavedRegs . set ( * R ) ; SmallVector < unsigned , 8 > NewRegs ; expandSpillMacros ( MF , NewRegs ) ; if ( OptimizeSpillSlots && ! isOptNone ( MF ) ) optimizeSpillSlots ( MF , NewRegs ) ; if ( ! NewRegs . empty ( ) || mayOverflowFrameOffset ( MF ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; SetVector < const TargetRegisterClass * > SpillRCs ; SpillRCs . insert ( & Hexagon :: IntRegsRegClass ) ; for ( unsigned VR : NewRegs ) SpillRCs . insert ( MRI . getRegClass ( VR ) ) ; for ( auto * RC : SpillRCs ) { if ( ! needToReserveScavengingSpillSlots ( MF , HRI , RC ) ) continue ; unsigned Num = 1 ; switch ( RC -> getID ( ) ) { case Hexagon :: IntRegsRegClassID : Num = NumberScavengerSlots ; break ; case Hexagon :: HvxQRRegClassID : Num = 2 ; break ; } unsigned S = HRI . getSpillSize ( * RC ) ; Align A = HRI . getSpillAlign ( * RC ) ; for ( unsigned i = 0 ; i < Num ; i ++ ) { int NewFI = MFI . CreateSpillStackObject ( S , A ) ; RS -> addScavengingFrameIndex ( NewFI ) ; } } } TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> static bool riscv_check_builtin_call ( location_t loc , vec < location_t > arg_loc , tree fndecl , tree orig_fndecl , unsigned int nargs , tree * args ) { unsigned int code = DECL_MD_FUNCTION_CODE ( fndecl ) ; unsigned int subcode = code >> RISCV_BUILTIN_SHIFT ; switch ( code & RISCV_BUILTIN_CLASS ) { case RISCV_BUILTIN_GENERAL : return true ; case RISCV_BUILTIN_VECTOR : return riscv_vector :: check_builtin_call ( loc , arg_loc , subcode , orig_fndecl , nargs , args ) ; } gcc_unreachable ( ) ; } </s>


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Patmos Bypass From PML"
;
}
</s>


<s> void EmitInstruction ( const MachineInstr * MI ) { printInstruction ( MI ) ; OutStreamer . AddBlankLine ( ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void SPIRVPassConfig :: addPreGlobalInstructionSelect ( ) { addPass ( createSPIRVGenerateDecorationsPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before the ( global ) instruction selection .


"%Klane index must be a constant immediate"

"%Ktotal size and element size must be a non-zero constant immediate"

Expand an AArch64 AdvSIMD builtin ( intrinsic ) .


<s>
MCFixupKindInfo
const
&
SNESAsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
SNES
::
NumTargetFixupKinds
]
=
{
{
"fixup_32"
,
0
,
32
,
0
}
,
{
"fixup_7_pcrel"
,
3
,
7
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_13_pcrel"
,
0
,
12
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_16"
,
0
,
16
,
0
}
,
{
"fixup_16_pm"
,
0
,
16
,
0
}
,
{
"fixup_ldi"
,
0
,
8
,
0
}
,
{
"fixup_lo8_ldi"
,
0
,
8
,
0
}
,
{
"fixup_hi8_ldi"
,
0
,
8
,
0
}
,
{
"fixup_hh8_ldi"
,
0
,
8
,
0
}
,
{
"fixup_ms8_ldi"
,
0
,
8
,
0
}
,
{
"fixup_lo8_ldi_neg"
,
0
,
8
,
0
}
,
{
"fixup_hi8_ldi_neg"
,
0
,
8
,
0
}
,
{
"fixup_hh8_ldi_neg"
,
0
,
8
,
0
}
,
{
"fixup_ms8_ldi_neg"
,
0
,
8
,
0
}
,
{
"fixup_lo8_ldi_pm"
,
0
,
8
,
0
}
,
{
"fixup_hi8_ldi_pm"
,
0
,
8
,
0
}
,
{
"fixup_hh8_ldi_pm"
,
0
,
8
,
0
}
,
{
"fixup_lo8_ldi_pm_neg"
,
0
,
8
,
0
}
,
{
"fixup_hi8_ldi_pm_neg"
,
0
,
8
,
0
}
,
{
"fixup_hh8_ldi_pm_neg"
,
0
,
8
,
0
}
,
{
"fixup_call"
,
0
,
22
,
0
}
,
{
"fixup_6"
,
0
,
16
,
0
}
,
{
"fixup_6_adiw"
,
0
,
6
,
0
}
,
{
"fixup_lo8_ldi_gs"
,
0
,
8
,
0
}
,
{
"fixup_hi8_ldi_gs"
,
0
,
8
,
0
}
,
{
"fixup_8"
,
0
,
8
,
0
}
,
{
"fixup_8_lo8"
,
0
,
8
,
0
}
,
{
"fixup_8_hi8"
,
0
,
8
,
0
}
,
{
"fixup_8_hlo8"
,
0
,
8
,
0
}
,
{
"fixup_sym_diff"
,
0
,
32
,
0
}
,
{
"fixup_16_ldst"
,
0
,
16
,
0
}
,
{
"fixup_lds_sts_16"
,
0
,
16
,
0
}
,
{
"fixup_port6"
,
0
,
16
,
0
}
,
{
"fixup_port5"
,
3
,
5
,
0
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> static bool loongarch_hard_regno_mode_ok_uncached ( unsigned int regno , machine_mode mode ) { unsigned int size ; enum mode_class mclass ; if ( mode == FCCmode ) return FCC_REG_P ( regno ) ; size = GET_MODE_SIZE ( mode ) ; mclass = GET_MODE_CLASS ( mode ) ; if ( GP_REG_P ( regno ) ) return ( ( regno - GP_REG_FIRST ) & 1 ) == 0 || size <= UNITS_PER_WORD ; if ( FP_REG_P ( regno ) ) { if ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT || mclass == MODE_VECTOR_FLOAT ) return size <= UNITS_PER_FPVALUE ; if ( mclass == MODE_INT ) return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG ; } return false ; } </s>

Return true if register REGNO can store a value of mode MODE . The result of this function is cached in loongarch_hard_regno_mode_ok .


<s> bool SITargetLowering :: isFMAFasterThanFMulAndFAdd ( EVT VT ) const { VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f32 : return Subtarget -> hasFP32Denormals ( ) && Subtarget -> hasFastFMAF32 ( ) ; case MVT :: f64 : return true ; case MVT :: f16 : return Subtarget -> has16BitInsts ( ) && Subtarget -> hasFP16Denormals ( ) ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s>
bool
PPCInstrInfo
::
isReallyTriviallyReMaterializable
(
const
MachineInstr
&
MI
,
AliasAnalysis
*
AA
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown rematerializable operation!"
)
;
break
;
case
PPC
::
LI
:
case
PPC
::
LI8
:
case
PPC
::
PLI
:
case
PPC
::
PLI8
:
case
PPC
::
LIS
:
case
PPC
::
LIS8
:
case
PPC
::
ADDIStocHA
:
case
PPC
::
ADDIStocHA8
:
case
PPC
::
ADDItocL
:
case
PPC
::
LOAD_STACK_GUARD
:
case
PPC
::
XXLXORz
:
case
PPC
::
XXLXORspz
:
case
PPC
::
XXLXORdpz
:
case
PPC
::
XXLEQVOnes
:
case
PPC
::
XXSPLTI32DX
:
case
PPC
::
V_SET0B
:
case
PPC
::
V_SET0H
:
case
PPC
::
V_SET0
:
case
PPC
::
V_SETALLONESB
:
case
PPC
::
V_SETALLONESH
:
case
PPC
::
V_SETALLONES
:
case
PPC
::
CRSET
:
case
PPC
::
CRUNSET
:
case
PPC
::
XXSETACCZ
:
return
true
;
}
return
false
;
}
</s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s>
bool
ARM64InstrInfo
::
isLdStPairSuppressed
(
const
MachineInstr
*
MI
)
const
{
assert
(
MOSuppressPair
<
(
1
<<
MachineMemOperand
::
MOTargetNumBits
)
&&
"Too many target MO flags"
)
;
for
(
auto
*
MM
:
MI
->
memoperands
(
)
)
{
if
(
MM
->
getFlags
(
)
&
(
MOSuppressPair
<<
MachineMemOperand
::
MOTargetStartBit
)
)
{
return
true
;
}
}
return
false
;
}
</s>

Return true if pairing the given load or store is hinted to be unprofitable .


<s> bool moxie_offset_address_p ( rtx x ) { x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == PLUS ) { x = XEXP ( x , 1 ) ; if ( GET_CODE ( x ) == CONST_INT ) { unsigned int v = INTVAL ( x ) & 0xFFFF8000 ; return ( v == 0xFFFF8000 || v == 0x00000000 ) ; } } return 0 ; } </s>

Return true for memory offset addresses between -32768 and 32767 .


<s> bool isReg ( ) const { return Kind == K_Register ; } </s>


<s>
const
CallLowering
*
ARMSubtarget
::
getCallLowering
(
)
const
{
assert
(
GISel
&&
"Access to GlobalISel APIs not set"
)
;
return
GISel
->
getCallLowering
(
)
;
}
</s>

ARM
ARM
"Access to GlobalISel APIs not set"


<s> bool shouldTrackLaneMasks ( ) const override { return false ; } </s>

Returns true if lanemasks should be tracked .


<s> void frv_expand_prologue ( void ) { frv_stack_t * info = frv_stack_info ( ) ; rtx sp = stack_pointer_rtx ; rtx fp = frame_pointer_rtx ; frv_frame_accessor_t accessor ; if ( TARGET_DEBUG_STACK ) frv_debug_stack ( info ) ; if ( info -> total_size == 0 ) return ; accessor . op = FRV_STORE ; if ( frame_pointer_needed && info -> total_size > 2048 ) { rtx insn ; accessor . base = gen_rtx_REG ( Pmode , OLD_SP_REGNO ) ; accessor . base_offset = info -> total_size ; insn = emit_insn ( gen_movsi ( accessor . base , sp ) ) ; } else { accessor . base = stack_pointer_rtx ; accessor . base_offset = 0 ; } { rtx asm_offset = frv_frame_offset_rtx ( - info -> total_size ) ; rtx dwarf_offset = GEN_INT ( - info -> total_size ) ; frv_frame_insn ( gen_stack_adjust ( sp , sp , asm_offset ) , gen_rtx_SET ( Pmode , sp , gen_rtx_PLUS ( Pmode , sp , dwarf_offset ) ) ) ; } if ( frame_pointer_needed ) { int fp_offset = info -> reg_offset [ FRAME_POINTER_REGNUM ] ; rtx asm_src = plus_constant ( accessor . base , fp_offset - accessor . base_offset ) ; rtx dwarf_src = plus_constant ( sp , fp_offset ) ; frv_frame_access ( & accessor , fp , fp_offset ) ; frv_frame_insn ( gen_rtx_SET ( VOIDmode , fp , asm_src ) , gen_rtx_SET ( VOIDmode , fp , dwarf_src ) ) ; accessor . base = fp ; accessor . base_offset = fp_offset ; } frv_frame_access_multi ( & accessor , info , STACK_REGS_STRUCT ) ; frv_frame_access_multi ( & accessor , info , STACK_REGS_LR ) ; frv_frame_access_multi ( & accessor , info , STACK_REGS_STDARG ) ; frv_frame_access_standard_regs ( FRV_STORE , info ) ; if ( info -> stdarg_size > 0 ) emit_insn ( gen_blockage ( ) ) ; if ( ! TARGET_FDPIC && flag_pic && cfun -> uses_pic_offset_table ) emit_insn ( gen_pic_prologue ( gen_rtx_REG ( Pmode , PIC_REGNO ) , gen_rtx_REG ( Pmode , LR_REGNO ) , gen_rtx_REG ( SImode , OFFSET_REGNO ) ) ) ; } </s>

Called after register allocation to add any instructions needed for the prologue . Using a prologue insn is favored compared to putting all of the instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook , since it allows the scheduler to intermix instructions with the saves of the caller saved registers . In some cases , it might be necessary to emit a barrier instruction as the last insn to prevent such scheduling . Also any insns generated here should have RTX_FRAME_RELATED_P ( insn ) = 1 so that the debug info generation code can handle them properly .


<s> BufferType :: const_iterator begin ( ) const { return Buffer . begin ( ) ; } </s>


<s> static bool isPairableLdStInst ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { default : return false ; case AArch64 :: STRSui : case AArch64 :: STRDui : case AArch64 :: STRQui : case AArch64 :: STRXui : case AArch64 :: STRWui : case AArch64 :: LDRSui : case AArch64 :: LDRDui : case AArch64 :: LDRQui : case AArch64 :: LDRXui : case AArch64 :: LDRWui : case AArch64 :: LDRSWui : case AArch64 :: STURSi : case AArch64 :: STURDi : case AArch64 :: STURQi : case AArch64 :: STURWi : case AArch64 :: STURXi : case AArch64 :: LDURSi : case AArch64 :: LDURDi : case AArch64 :: LDURQi : case AArch64 :: LDURWi : case AArch64 :: LDURXi : case AArch64 :: LDURSWi : return true ; } } </s>

Return true if pairing the given load or store may be paired with another .


<s> static bool aarch64_evpc_trn ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> nelt ; rtx out , in0 , in1 , x ; rtx ( * gen ) ( rtx , rtx , rtx ) ; machine_mode vmode = d -> vmode ; if ( GET_MODE_UNIT_SIZE ( vmode ) > 8 ) return false ; if ( d -> perm [ 0 ] == 0 ) odd = 0 ; else if ( d -> perm [ 0 ] == 1 ) odd = 1 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt ; i += 2 ) { if ( d -> perm [ i ] != i + odd ) return false ; if ( d -> perm [ i + 1 ] != ( ( i + nelt + odd ) & mask ) ) return false ; } if ( d -> testing_p ) return true ; in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN ) { x = in0 , in0 = in1 , in1 = x ; odd = ! odd ; } out = d -> target ; if ( odd ) { switch ( vmode ) { case V16QImode : gen = gen_aarch64_trn2v16qi ; break ; case V8QImode : gen = gen_aarch64_trn2v8qi ; break ; case V8HImode : gen = gen_aarch64_trn2v8hi ; break ; case V4HImode : gen = gen_aarch64_trn2v4hi ; break ; case V4SImode : gen = gen_aarch64_trn2v4si ; break ; case V2SImode : gen = gen_aarch64_trn2v2si ; break ; case V2DImode : gen = gen_aarch64_trn2v2di ; break ; case V4SFmode : gen = gen_aarch64_trn2v4sf ; break ; case V2SFmode : gen = gen_aarch64_trn2v2sf ; break ; case V2DFmode : gen = gen_aarch64_trn2v2df ; break ; default : return false ; } } else { switch ( vmode ) { case V16QImode : gen = gen_aarch64_trn1v16qi ; break ; case V8QImode : gen = gen_aarch64_trn1v8qi ; break ; case V8HImode : gen = gen_aarch64_trn1v8hi ; break ; case V4HImode : gen = gen_aarch64_trn1v4hi ; break ; case V4SImode : gen = gen_aarch64_trn1v4si ; break ; case V2SImode : gen = gen_aarch64_trn1v2si ; break ; case V2DImode : gen = gen_aarch64_trn1v2di ; break ; case V4SFmode : gen = gen_aarch64_trn1v4sf ; break ; case V2SFmode : gen = gen_aarch64_trn1v2sf ; break ; case V2DFmode : gen = gen_aarch64_trn1v2df ; break ; default : return false ; } } emit_insn ( gen ( out , in0 , in1 ) ) ; return true ; } </s>

Recognize patterns suitable for the TRN instructions .


<s> char * aarch64_output_sve_inc_dec_immediate ( const char * operands , rtx x ) { int factor ; unsigned int nelts_per_vq ; if ( ! aarch64_sve_inc_dec_immediate_p ( x , & factor , & nelts_per_vq ) ) gcc_unreachable ( ) ; if ( factor < 0 ) return aarch64_output_sve_cnt_immediate ( "dec" , operands , - factor , nelts_per_vq ) ; else return aarch64_output_sve_cnt_immediate ( "inc" , operands , factor , nelts_per_vq ) ; } </s>

Return the asm template for an SVE vector INC or DEC instruction . OPERANDS gives the operands before the vector count and X is the value of the vector count operand itself .


<s>
SDValue
PTXTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
if
(
isVarArg
)
llvm_unreachable
(
"PTX does not support varargs"
)
;
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
const
PTXSubtarget
&
ST
=
getTargetMachine
(
)
.
getSubtarget
<
PTXSubtarget
>
(
)
;
PTXMachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
PTXMachineFunctionInfo
>
(
)
;
PTXParamManager
&
PM
=
MFI
->
getParamManager
(
)
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
break
;
case
CallingConv
::
PTX_Kernel
:
MFI
->
setKernel
(
true
)
;
break
;
case
CallingConv
::
PTX_Device
:
MFI
->
setKernel
(
false
)
;
break
;
}
if
(
MFI
->
isKernel
(
)
||
ST
.
useParamSpaceForDeviceArgs
(
)
)
{
for
(
unsigned
i
=
0
,
e
=
Ins
.
size
(
)
;
i
!=
e
;
++
i
)
{
assert
(
(
!
MFI
->
isKernel
(
)
||
Ins
[
i
]
.
VT
!=
MVT
::
i1
)
&&
"Kernels cannot take pred operands"
)
;
unsigned
ParamSize
=
Ins
[
i
]
.
VT
.
getStoreSizeInBits
(
)
;
unsigned
Param
=
PM
.
addArgumentParam
(
ParamSize
)
;
const
std
::
string
&
ParamName
=
PM
.
getParamName
(
Param
)
;
SDValue
ParamValue
=
DAG
.
getTargetExternalSymbol
(
ParamName
.
c_str
(
)
,
MVT
::
Other
)
;
SDValue
ArgValue
=
DAG
.
getNode
(
PTXISD
::
LOAD_PARAM
,
dl
,
Ins
[
i
]
.
VT
,
Chain
,
ParamValue
)
;
InVals
.
push_back
(
ArgValue
)
;
}
}
else
{
for
(
unsigned
i
=
0
,
e
=
Ins
.
size
(
)
;
i
!=
e
;
++
i
)
{
EVT
RegVT
=
Ins
[
i
]
.
VT
;
TargetRegisterClass
*
TRC
=
getRegClassFor
(
RegVT
)
;
SDValue
Index
=
DAG
.
getTargetConstant
(
i
,
MVT
::
i32
)
;
unsigned
Reg
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
TRC
)
;
SDValue
ArgValue
=
DAG
.
getNode
(
PTXISD
::
READ_PARAM
,
dl
,
RegVT
,
Chain
,
Index
)
;
InVals
.
push_back
(
ArgValue
)
;
MFI
->
addArgReg
(
Reg
)
;
}
}
return
Chain
;
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .

PTX
PTX
ISD::InputArg
"PTX does not support varargs"
PTX
PTX
PTX
PTX
PTX
"Unsupported calling convention"
PTX
PTX
0
MVT::i1
"Kernels cannot take pred operands"
MVT::Other
PTXISD::LOAD_PARAM
0
MVT::i32
PTXISD::READ_PARAM


<s> bool ix86_agi_dependent ( rtx_insn * set_insn , rtx_insn * use_insn ) { int i ; extract_insn_cached ( use_insn ) ; for ( i = recog_data . n_operands - 1 ; i >= 0 ; -- i ) if ( MEM_P ( recog_data . operand [ i ] ) ) { rtx addr = XEXP ( recog_data . operand [ i ] , 0 ) ; return modified_in_p ( addr , set_insn ) != 0 ; } return false ; } </s>

Return true iff USE_INSN has a memory address with operands set by SET_INSN .


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s>
void
WebAssemblyInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
auto
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
const
TargetRegisterClass
*
RC
=
TargetRegisterInfo
::
isVirtualRegister
(
DestReg
)
MRI
.
getRegClass
(
DestReg
)
:
MRI
.
getTargetRegisterInfo
(
)
->
getMinimalPhysRegClass
(
SrcReg
)
;
unsigned
CopyLocalOpcode
;
if
(
RC
==
&
WebAssembly
::
I32RegClass
)
CopyLocalOpcode
=
WebAssembly
::
COPY_LOCAL_I32
;
else
if
(
RC
==
&
WebAssembly
::
I64RegClass
)
CopyLocalOpcode
=
WebAssembly
::
COPY_LOCAL_I64
;
else
if
(
RC
==
&
WebAssembly
::
F32RegClass
)
CopyLocalOpcode
=
WebAssembly
::
COPY_LOCAL_F32
;
else
if
(
RC
==
&
WebAssembly
::
F64RegClass
)
CopyLocalOpcode
=
WebAssembly
::
COPY_LOCAL_F64
;
else
llvm_unreachable
(
"Unexpected register class"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
CopyLocalOpcode
)
,
DestReg
)
.
addReg
(
SrcReg
,
KillSrc
RegState
::
Kill
:
0
)
;
}
</s>


<s> unsigned MipsMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; unsigned RegNo = Ctx . getRegisterInfo ( ) -> getEncodingValue ( Reg ) ; return RegNo ; } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isFPImm ( ) ) { return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( 32 ) . getLimitedValue ( ) ) ; } assert ( MO . isExpr ( ) ) ; return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> ScheduleHazardRecognizer :: HazardType SystemZHazardRecognizer :: getHazardType ( SUnit * m , int Stalls ) { return ( fitsIntoCurrentGroup ( m ) ? NoHazard : Hazard ) ; } </s>

getHazardType - Return the hazard type of emitting this node .


<s> bool R600InstrInfo :: PredicateInstruction ( MachineInstr * MI , const SmallVectorImpl < MachineOperand > & Pred ) const { int PIdx = MI -> findFirstPredOperandIdx ( ) ; if ( MI -> getOpcode ( ) == AMDGPU :: CF_ALU ) { MI -> getOperand ( 8 ) . setImm ( 0 ) ; return true ; } if ( PIdx != - 1 ) { MachineOperand & PMO = MI -> getOperand ( PIdx ) ; PMO . setReg ( Pred [ 2 ] . getReg ( ) ) ; MachineInstrBuilder MIB ( * MI -> getParent ( ) -> getParent ( ) , MI ) ; MIB . addReg ( AMDGPU :: PREDICATE_BIT , RegState :: Implicit ) ; return true ; } return false ; } </s>

Convert the instruction into a predicated instruction .


<s> unsigned MipsInstrInfo :: getGlobalBaseReg ( MachineFunction * MF ) const { MipsFunctionInfo * MipsFI = MF -> getInfo < MipsFunctionInfo > ( ) ; unsigned GlobalBaseReg = MipsFI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg != 0 ) return GlobalBaseReg ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; const TargetInstrInfo * TII = MF -> getTarget ( ) . getInstrInfo ( ) ; GlobalBaseReg = RegInfo . createVirtualRegister ( Mips :: CPURegsRegisterClass ) ; BuildMI ( FirstMBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , GlobalBaseReg ) . addReg ( Mips :: GP ) ; RegInfo . addLiveIn ( Mips :: GP ) ; MipsFI -> setGlobalBaseReg ( GlobalBaseReg ) ; return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

Mips Mips Mips Mips Mips Mips 0 Mips::CPURegsRegisterClass Mips::GP Mips::GP Mips


<s> virtual bool requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>


<s> int call26_operand ( rtx op , machine_mode mode ATTRIBUTE_UNUSED ) { if ( flag_pic ) return 1 ; if ( GET_CODE ( op ) == SYMBOL_REF ) return SYMBOL_REF_MODEL ( op ) != M32R_MODEL_LARGE ; return TARGET_CALL26 ; } </s>

Return 1 if OP is a function that can be called with the ` bl ' insn .


"Call frame pseudos should only be used for dynamic stack adjustment"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


runOnMachineFunction - Emit the function body .


<s> void TOYFrameLowering :: emitPrologue ( MachineFunction & MF ) const { const TOYInstrInfo & TII = * static_cast < const TOYInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int StackSize = ( int ) MFI -> getStackSize ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TOY :: ADDri ) , TOY :: SP ) . addReg ( TOY :: SP ) . addImm ( StackSize ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

TOY TOY TOY TOY TOY::ADDri TOY::SP TOY::SP


<s> bool Error ( SMLoc L , const Twine & Msg ) { return Parser . Error ( L , Msg ) ; } </s>

Return an error at the location L , with the message Msg .


Relax the instruction in the given fragment to the next wider instruction .


<s> unsigned getNumFixupKinds ( ) const override { return Sparc :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> SDValue NVPTXTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { CodeGenOpt :: Level OptLevel = getTargetMachine ( ) . getOptLevel ( ) ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : case ISD :: FADD : return PerformADDCombine ( N , DCI , STI , OptLevel ) ; case ISD :: MUL : return PerformMULCombine ( N , DCI , OptLevel ) ; case ISD :: SHL : return PerformSHLCombine ( N , DCI , OptLevel ) ; case ISD :: AND : return PerformANDCombine ( N , DCI ) ; case ISD :: UREM : case ISD :: SREM : return PerformREMCombine ( N , DCI , OptLevel ) ; case ISD :: SETCC : return PerformSETCCCombine ( N , DCI ) ; case NVPTXISD :: StoreRetval : case NVPTXISD :: StoreRetvalV2 : case NVPTXISD :: StoreRetvalV4 : return PerformStoreRetvalCombine ( N ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

NVPTX NVPTX ISD::ADD ISD::FADD ISD::MUL ISD::SHL ISD::AND ISD::UREM ISD::SREM ISD::SETCC NVPTXISD::StoreRetval NVPTXISD::StoreRetvalV2 NVPTXISD::StoreRetvalV4


<s>
static
void
alpha_print_operand_address
(
FILE
*
file
,
machine_mode
,
rtx
addr
)
{
int
basereg
=
31
;
HOST_WIDE_INT
offset
=
0
;
if
(
GET_CODE
(
addr
)
==
AND
)
addr
=
XEXP
(
addr
,
0
)
;
if
(
GET_CODE
(
addr
)
==
PLUS
&&
CONST_INT_P
(
XEXP
(
addr
,
1
)
)
)
{
offset
=
INTVAL
(
XEXP
(
addr
,
1
)
)
;
addr
=
XEXP
(
addr
,
0
)
;
}
if
(
GET_CODE
(
addr
)
==
LO_SUM
)
{
const
char
*
reloc16
,
*
reloclo
;
rtx
op1
=
XEXP
(
addr
,
1
)
;
if
(
GET_CODE
(
op1
)
==
CONST
&&
GET_CODE
(
XEXP
(
op1
,
0
)
)
==
UNSPEC
)
{
op1
=
XEXP
(
op1
,
0
)
;
switch
(
XINT
(
op1
,
1
)
)
{
case
UNSPEC_DTPREL
:
reloc16
=
;
reloclo
=
(
alpha_tls_size
==
16
"dtprel"
:
"dtprello"
)
;
break
;
case
UNSPEC_TPREL
:
reloc16
=
;
reloclo
=
(
alpha_tls_size
==
16
"tprel"
:
"tprello"
)
;
break
;
default
:
output_operand_lossage
(
"unknown relocation unspec"
)
;
return
;
}
output_addr_const
(
file
,
XVECEXP
(
op1
,
0
,
0
)
)
;
}
else
{
reloc16
=
"gprel"
;
reloclo
=
"gprellow"
;
output_addr_const
(
file
,
op1
)
;
}
if
(
offset
)
fprintf
(
file
,
"+"
HOST_WIDE_INT_PRINT_DEC
,
offset
)
;
addr
=
XEXP
(
addr
,
0
)
;
switch
(
GET_CODE
(
addr
)
)
{
case
REG
:
basereg
=
REGNO
(
addr
)
;
break
;
case
SUBREG
:
basereg
=
subreg_regno
(
addr
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
fprintf
(
file
,
"($%d)\t\t!%s"
,
basereg
,
(
basereg
==
29
reloc16
:
reloclo
)
)
;
return
;
}
switch
(
GET_CODE
(
addr
)
)
{
case
REG
:
basereg
=
REGNO
(
addr
)
;
break
;
case
SUBREG
:
basereg
=
subreg_regno
(
addr
)
;
break
;
case
CONST_INT
:
offset
=
INTVAL
(
addr
)
;
break
;
case
SYMBOL_REF
:
gcc_assert
(
TARGET_ABI_OPEN_VMS
||
this_is_asm_operands
)
;
fprintf
(
file
,
"%s"
,
XSTR
(
addr
,
0
)
)
;
return
;
case
CONST
:
gcc_assert
(
TARGET_ABI_OPEN_VMS
||
this_is_asm_operands
)
;
gcc_assert
(
GET_CODE
(
XEXP
(
addr
,
0
)
)
==
PLUS
&&
GET_CODE
(
XEXP
(
XEXP
(
addr
,
0
)
,
0
)
)
==
SYMBOL_REF
)
;
fprintf
(
file
,
"%s+"
HOST_WIDE_INT_PRINT_DEC
,
XSTR
(
XEXP
(
XEXP
(
addr
,
0
)
,
0
)
,
0
)
,
INTVAL
(
XEXP
(
XEXP
(
addr
,
0
)
,
1
)
)
)
;
return
;
default
:
output_operand_lossage
(
"invalid operand address"
)
;
return
;
}
fprintf
(
file
,
HOST_WIDE_INT_PRINT_DEC
"($%d)"
,
offset
,
basereg
)
;
}
</s>


<s> const TargetRegisterClass * M68kRegisterInfo :: getRegsForTailCall ( const MachineFunction & MF ) const { return & M68k :: XR32_TCRegClass ; } </s>

Returns a register class with registers that can be used in forming tail calls .


<s> bool runOnMachineFunction ( MachineFunction & F ) { bool Changed = false ; if ( EnableDelJmp ) { MachineFunction :: iterator FJ = F . begin ( ) ; if ( FJ != F . end ( ) ) FJ ++ ; if ( FJ == F . end ( ) ) return Changed ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FJ != FE ; ++ FI , ++ FJ ) Changed |= runOnMachineBasicBlock ( * FI , * FJ ) ; } return Changed ; } </s>


<s> void AMDGPUAsmPrinter :: emitStartOfAsmFile ( Module & M ) { IsTargetStreamerInitialized = false ; } </s>

This virtual method can be overridden by targets that want to emit something at the start of their file .


<s> bool MipsAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNum ) ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNum , AsmVariant , ExtraCode , O ) ; case 'X' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << "0x" << StringRef ( utohexstr ( MO . getImm ( ) ) ) . lower ( ) ; return false ; case 'x' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << "0x" << StringRef ( utohexstr ( MO . getImm ( ) & 0xffff ) ) . lower ( ) ; return false ; case 'd' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) ; return false ; case 'm' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) - 1 ; return false ; case 'z' : { if ( MO . getType ( ) != MachineOperand :: MO_Immediate ) return true ; int64_t Val = MO . getImm ( ) ; if ( Val ) O << Val ; else O << "$0" ; return false ; } } } printOperand ( MI , OpNum , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s>
MachineBasicBlock
::
iterator
PatmosFrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
const
TargetInstrInfo
&
TII
=
*
STC
.
getInstrInfo
(
)
;
if
(
hasFP
(
MF
)
)
{
MachineInstr
&
MI
=
*
I
;
DebugLoc
dl
=
MI
.
getDebugLoc
(
)
;
int
Size
=
MI
.
getOperand
(
0
)
.
getImm
(
)
;
unsigned
Opcode
;
if
(
MI
.
getOpcode
(
)
==
Patmos
::
ADJCALLSTACKDOWN
)
{
Opcode
=
(
Size
<=
0xFFF
)
Patmos
::
SUBi
:
Patmos
::
SUBl
;
}
else
if
(
MI
.
getOpcode
(
)
==
Patmos
::
ADJCALLSTACKUP
)
{
Opcode
=
(
Size
<=
0xFFF
)
Patmos
::
ADDi
:
Patmos
::
ADDl
;
}
else
{
llvm_unreachable
(
"Unsupported pseudo instruction."
)
;
}
if
(
Size
)
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
dl
,
TII
.
get
(
Opcode
)
,
Patmos
::
RSP
)
)
.
addReg
(
Patmos
::
RSP
)
.
addImm
(
Size
)
;
}
return
MBB
.
erase
(
I
)
;
}
</s>

Patmos
Patmos
0
Patmos::ADJCALLSTACKDOWN
0xFFF
Patmos::SUBi
Patmos::SUBl
Patmos::ADJCALLSTACKUP
0xFFF
Patmos::ADDi
Patmos::ADDl
"Unsupported pseudo instruction."
Patmos::RSP
Patmos::RSP


<s> static void v850_insert_attributes ( tree decl , tree * attr_ptr ATTRIBUTE_UNUSED ) { if ( data_area_stack && data_area_stack -> data_area && current_function_decl == NULL_TREE && ( TREE_CODE ( decl ) == VAR_DECL || TREE_CODE ( decl ) == CONST_DECL ) && v850_get_data_area ( decl ) == DATA_AREA_NORMAL ) v850_set_data_area ( decl , data_area_stack -> data_area ) ; if ( GHS_default_section_names [ ( int ) GHS_SECTION_KIND_SDATA ] == NULL ) { GHS_default_section_names [ ( int ) GHS_SECTION_KIND_SDATA ] = build_string ( sizeof ( ".sdata" ) - 1 , ".sdata" ) ; GHS_default_section_names [ ( int ) GHS_SECTION_KIND_ROSDATA ] = build_string ( sizeof ( ".rosdata" ) - 1 , ".rosdata" ) ; GHS_default_section_names [ ( int ) GHS_SECTION_KIND_TDATA ] = build_string ( sizeof ( ".tdata" ) - 1 , ".tdata" ) ; GHS_default_section_names [ ( int ) GHS_SECTION_KIND_ZDATA ] = build_string ( sizeof ( ".zdata" ) - 1 , ".zdata" ) ; GHS_default_section_names [ ( int ) GHS_SECTION_KIND_ROZDATA ] = build_string ( sizeof ( ".rozdata" ) - 1 , ".rozdata" ) ; } if ( current_function_decl == NULL_TREE && ( TREE_CODE ( decl ) == VAR_DECL || TREE_CODE ( decl ) == CONST_DECL || TREE_CODE ( decl ) == FUNCTION_DECL ) && ( ! DECL_EXTERNAL ( decl ) || DECL_INITIAL ( decl ) ) && ! DECL_SECTION_NAME ( decl ) ) { enum GHS_section_kind kind = GHS_SECTION_KIND_DEFAULT ; tree chosen_section ; if ( TREE_CODE ( decl ) == FUNCTION_DECL ) kind = GHS_SECTION_KIND_TEXT ; else { switch ( v850_get_data_area ( decl ) ) { default : gcc_unreachable ( ) ; case DATA_AREA_SDA : kind = ( ( TREE_READONLY ( decl ) ) ? GHS_SECTION_KIND_ROSDATA : GHS_SECTION_KIND_SDATA ) ; break ; case DATA_AREA_TDA : kind = GHS_SECTION_KIND_TDATA ; break ; case DATA_AREA_ZDA : kind = ( ( TREE_READONLY ( decl ) ) ? GHS_SECTION_KIND_ROZDATA : GHS_SECTION_KIND_ZDATA ) ; break ; case DATA_AREA_NORMAL : if ( TREE_READONLY ( decl ) ) kind = GHS_SECTION_KIND_RODATA ; else if ( DECL_INITIAL ( decl ) ) kind = GHS_SECTION_KIND_DATA ; else kind = GHS_SECTION_KIND_BSS ; } } chosen_section = GHS_current_section_names [ ( int ) kind ] ; if ( chosen_section == NULL ) chosen_section = GHS_default_section_names [ ( int ) kind ] ; if ( chosen_section ) { DECL_SECTION_NAME ( decl ) = chosen_section ; } } } </s>

Add data area to the given declaration if a ghs data area pragma is currently in effect ( # pragma ghs startXXX/endXXX ) .


<s> SDValue MipsSETargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: SMUL_LOHI : return lowerMulDiv ( Op , MipsISD :: Mult , true , true , DAG ) ; case ISD :: UMUL_LOHI : return lowerMulDiv ( Op , MipsISD :: Multu , true , true , DAG ) ; case ISD :: MULHS : return lowerMulDiv ( Op , MipsISD :: Mult , false , true , DAG ) ; case ISD :: MULHU : return lowerMulDiv ( Op , MipsISD :: Multu , false , true , DAG ) ; case ISD :: MUL : return lowerMulDiv ( Op , MipsISD :: Mult , true , false , DAG ) ; case ISD :: SDIVREM : return lowerMulDiv ( Op , MipsISD :: DivRem , true , true , DAG ) ; case ISD :: UDIVREM : return lowerMulDiv ( Op , MipsISD :: DivRemU , true , true , DAG ) ; case ISD :: INTRINSIC_WO_CHAIN : return lowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case ISD :: INTRINSIC_W_CHAIN : return lowerINTRINSIC_W_CHAIN ( Op , DAG ) ; } return MipsTargetLowering :: LowerOperation ( Op , DAG ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::SMUL_LOHI MipsISD::Mult ISD::UMUL_LOHI MipsISD::Multu ISD::MULHS MipsISD::Mult ISD::MULHU MipsISD::Multu ISD::MUL MipsISD::Mult ISD::SDIVREM MipsISD::DivRem ISD::UDIVREM MipsISD::DivRemU ISD::INTRINSIC_WO_CHAIN ISD::INTRINSIC_W_CHAIN Mips


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> unsigned XCoreRegisterInfo :: getFrameRegister ( MachineFunction & MF ) const { bool FP = hasFP ( MF ) ; return FP ? XCore :: R10 : XCore :: SP ; } </s>


<s> int pru_get_ctable_exact_base_index ( unsigned HOST_WIDE_INT caddr ) { unsigned int i ; for ( i = 0 ; i < ARRAY_SIZE ( pru_ctable ) ; i ++ ) { if ( pru_ctable [ i ] . valid && pru_ctable [ i ] . base == caddr ) return i ; } return - 1 ; } </s>

Recognize a CTABLE base address . Return CTABLE entry index , or -1 if base was not found in the pragma-filled pru_ctable .


"node still has unscheduled dependencies"

Move an instruction and update register pressure .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"R600 Packetizer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool OpenRISCFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool MipsRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s>
unsigned
getOpSize
(
const
MachineInstr
&
MI
,
unsigned
OpNo
)
const
{
const
MachineOperand
&
MO
=
MI
.
getOperand
(
OpNo
)
;
if
(
MO
.
isReg
(
)
)
{
if
(
unsigned
SubReg
=
MO
.
getSubReg
(
)
)
{
assert
(
RI
.
getRegSizeInBits
(
*
RI
.
getSubClassWithSubReg
(
MI
.
getParent
(
)
->
getParent
(
)
->
getRegInfo
(
)
.
getRegClass
(
MO
.
getReg
(
)
)
,
SubReg
)
)
>=
32
&&
"Sub-dword subregs are not supported"
)
;
return
RI
.
getSubRegIndexLaneMask
(
SubReg
)
.
getNumLanes
(
)
*
4
;
}
}
return
RI
.
getRegSizeInBits
(
*
getOpRegClass
(
MI
,
OpNo
)
)
/
8
;
}
</s>

This form should usually be preferred since it handles operands with unknown register classes .


<s> virtual const PPCFrameInfo * getFrameInfo ( ) const { return & FrameInfo ; } </s>

getFrameInfo - Return the frame info object for the current function .


<s> bool ARMBaseInstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { if ( Cond . size ( ) == 2 ) { ARMCC :: CondCodes CC = ( ARMCC :: CondCodes ) ( int ) Cond [ 0 ] . getImm ( ) ; Cond [ 0 ] . setImm ( ARMCC :: getOppositeCondition ( CC ) ) ; return false ; } return true ; } </s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> SDNode * HexagonDAGToDAGISel :: Select ( SDNode * N ) { if ( N -> isMachineOpcode ( ) ) return NULL ; switch ( N -> getOpcode ( ) ) { case ISD :: Constant : return SelectConstant ( N ) ; case ISD :: ConstantFP : return SelectConstantFP ( N ) ; case ISD :: ADD : return SelectAdd ( N ) ; case ISD :: SHL : return SelectSHL ( N ) ; case ISD :: LOAD : return SelectLoad ( N ) ; case ISD :: STORE : return SelectStore ( N ) ; case ISD :: SELECT : return SelectSelect ( N ) ; case ISD :: TRUNCATE : return SelectTruncate ( N ) ; case ISD :: MUL : return SelectMul ( N ) ; case ISD :: ZERO_EXTEND : return SelectZeroExtend ( N ) ; case ISD :: INTRINSIC_WO_CHAIN : return SelectIntrinsicWOChain ( N ) ; } return SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .

Hexagon Hexagon ISD::Constant ISD::ConstantFP ISD::ADD ISD::SHL ISD::LOAD ISD::STORE ISD::SELECT ISD::TRUNCATE ISD::MUL ISD::ZERO_EXTEND ISD::INTRINSIC_WO_CHAIN


<s> bool isFI ( ) const { return isImmTy ( ImmTyDppFi ) ; } </s>

isFI - Tests if this is a MO_FrameIndex operand .


<s> static void frv_insert_nop_in_packet ( rtx_insn * insn ) { struct frv_packet_group * packet_group ; rtx_insn * last ; packet_group = & frv_packet . groups [ frv_unit_groups [ frv_insn_unit ( insn ) ] ] ; last = frv_packet . insns [ frv_packet . num_insns - 1 ] ; if ( ! NONJUMP_INSN_P ( last ) ) { insn = emit_insn_before ( PATTERN ( insn ) , last ) ; frv_packet . insns [ frv_packet . num_insns - 1 ] = insn ; frv_packet . insns [ frv_packet . num_insns ++ ] = last ; } else { insn = emit_insn_after ( PATTERN ( insn ) , last ) ; frv_packet . insns [ frv_packet . num_insns ++ ] = insn ; } packet_group -> insns [ packet_group -> num_insns ++ ] = insn ; } </s>

Insert INSN ( a member of frv_nops [ ] ) into the current packet . If the packet ends in a branch or call , insert the nop before it , otherwise add to the end .


<s> bool x86_extended_QIreg_mentioned_p ( rtx insn ) { int i ; extract_insn_cached ( insn ) ; for ( i = 0 ; i < recog_data . n_operands ; i ++ ) if ( REG_P ( recog_data . operand [ i ] ) && REGNO ( recog_data . operand [ i ] ) >= 4 ) return true ; return false ; } </s>

Return nonzero when QImode register that must be represented via REX prefix is used .


<s> static bool mips_return_in_memory ( const_tree type , const_tree fndecl ATTRIBUTE_UNUSED ) { return ( TARGET_OLDABI ? TYPE_MODE ( type ) == BLKmode : ! IN_RANGE ( int_size_in_bytes ( type ) , 0 , 2 * UNITS_PER_WORD ) ) ; } </s>

Implement TARGET_RETURN_IN_MEMORY . Under the old ( i.e. , 32 and O64 ABIs ) all BLKmode objects are returned in memory . Under the new ( N32 and 64-bit MIPS ABIs ) small structures are returned in a register . Objects with varying size must still be returned in memory , of course .


<s> void MipsRegisterInfo :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; if ( MipsFI -> needGPSaveRestore ( ) ) MFI -> setObjectOffset ( MipsFI -> getGPFI ( ) , MipsFI -> getGPStackOffset ( ) ) ; } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> bool quad_address_p ( rtx addr , machine_mode mode , bool strict ) { rtx op0 , op1 ; if ( GET_MODE_SIZE ( mode ) < 16 ) return false ; if ( legitimate_indirect_address_p ( addr , strict ) ) return true ; if ( VECTOR_MODE_P ( mode ) && ! mode_supports_dq_form ( mode ) ) return false ; if ( address_is_prefixed ( addr , mode , NON_PREFIXED_DQ ) ) return true ; if ( GET_CODE ( addr ) != PLUS ) return false ; op0 = XEXP ( addr , 0 ) ; if ( ! REG_P ( op0 ) || ! INT_REG_OK_FOR_BASE_P ( op0 , strict ) ) return false ; op1 = XEXP ( addr , 1 ) ; if ( ! CONST_INT_P ( op1 ) ) return false ; return quad_address_offset_p ( INTVAL ( op1 ) ) ; } </s>

Return true if the ADDR is an acceptable address for a quad memory operation of mode MODE ( either LQ/STQ for general purpose registers , or LXV/STXV for vector registers under ISA 3.0 . GPR_P is true if this address is intended for LQ/STQ . If it is false , the address is intended for the ISA 3.0 LXV/STXV instruction .


<s> Type * ARMTargetLowering :: shouldConvertSplatType ( ShuffleVectorInst * SVI ) const { if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return nullptr ; Type * SVIType = SVI -> getType ( ) ; Type * ScalarType = SVIType -> getScalarType ( ) ; if ( ScalarType -> isFloatTy ( ) ) return Type :: getInt32Ty ( SVIType -> getContext ( ) ) ; if ( ScalarType -> isHalfTy ( ) ) return Type :: getInt16Ty ( SVIType -> getContext ( ) ) ; return nullptr ; } </s>

Given a shuffle vector SVI representing a vector splat , return a new scalar type of size equal to SVI 's scalar type if the new type is more profitable .


<s> static tree find_sole_member ( tree type ) { tree field , member = NULL_TREE ; for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( ! DECL_SIZE ( field ) ) return NULL_TREE ; if ( integer_zerop ( DECL_SIZE ( field ) ) ) continue ; if ( member ) return NULL_TREE ; member = field ; } return member ; } </s>

TYPE is a RECORD_TYPE . If there is only a single non-zero-sized member , return it .


<s> unsigned Cpu0RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? ( Cpu0 :: FP ) : ( Cpu0 :: SP ) ; } </s>


<s> static int aarch64_rtx_mult_cost ( rtx x , int code , int outer , bool speed ) { rtx op0 , op1 ; const struct cpu_cost_table * extra_cost = aarch64_tune_params -> insn_extra_cost ; int cost = 0 ; bool maybe_fma = ( outer == PLUS || outer == MINUS ) ; machine_mode mode = GET_MODE ( x ) ; gcc_checking_assert ( code == MULT ) ; op0 = XEXP ( x , 0 ) ; op1 = XEXP ( x , 1 ) ; if ( VECTOR_MODE_P ( mode ) ) mode = GET_MODE_INNER ( mode ) ; if ( GET_MODE_CLASS ( mode ) == MODE_INT ) { if ( CONST_INT_P ( op1 ) && exact_log2 ( INTVAL ( op1 ) ) > 0 ) { if ( speed ) { if ( maybe_fma ) cost += extra_cost -> alu . arith_shift ; else cost += extra_cost -> alu . shift ; } cost += rtx_cost ( op0 , GET_CODE ( op0 ) , 0 , speed ) ; return cost ; } if ( ( GET_CODE ( op0 ) == ZERO_EXTEND && GET_CODE ( op1 ) == ZERO_EXTEND ) || ( GET_CODE ( op0 ) == SIGN_EXTEND && GET_CODE ( op1 ) == SIGN_EXTEND ) ) { cost += rtx_cost ( XEXP ( op0 , 0 ) , MULT , 0 , speed ) + rtx_cost ( XEXP ( op1 , 0 ) , MULT , 1 , speed ) ; if ( speed ) { if ( maybe_fma ) cost += extra_cost -> mult [ 0 ] . extend_add ; else cost += extra_cost -> mult [ 0 ] . extend ; } return cost ; } cost += rtx_cost ( op0 , MULT , 0 , speed ) + rtx_cost ( op1 , MULT , 1 , speed ) ; if ( speed ) { if ( maybe_fma ) cost += extra_cost -> mult [ mode == DImode ] . add ; else cost += extra_cost -> mult [ mode == DImode ] . simple ; } return cost ; } else { if ( speed ) { if ( GET_CODE ( op0 ) == NEG ) op0 = XEXP ( op0 , 0 ) ; if ( GET_CODE ( op1 ) == NEG ) op1 = XEXP ( op1 , 0 ) ; if ( maybe_fma ) cost += extra_cost -> fp [ mode == DFmode ] . fma ; else cost += extra_cost -> fp [ mode == DFmode ] . mult ; } cost += rtx_cost ( op0 , MULT , 0 , speed ) + rtx_cost ( op1 , MULT , 1 , speed ) ; return cost ; } } </s>

Helper function for rtx cost calculation . Calculate the cost of a MULT , which may be part of a multiply-accumulate rtx . Return the calculated cost of the expression , recursing manually in to operands where needed .


<s> static rtx gen_vsetvl_pat ( rtx_insn * rinsn , const vector_insn_info & info ) { rtx new_pat ; vl_vtype_info new_info = info ; if ( info . get_insn ( ) && info . get_insn ( ) -> rtl ( ) && fault_first_load_p ( info . get_insn ( ) -> rtl ( ) ) ) new_info . set_avl_info ( avl_info ( get_avl ( info . get_insn ( ) -> rtl ( ) ) , nullptr ) ) ; if ( vsetvl_insn_p ( rinsn ) || vlmax_avl_p ( info . get_avl ( ) ) ) { rtx dest = get_vl ( rinsn ) ; new_pat = gen_vsetvl_pat ( VSETVL_NORMAL , new_info , dest ) ; } else if ( INSN_CODE ( rinsn ) == CODE_FOR_vsetvl_vtype_change_only ) new_pat = gen_vsetvl_pat ( VSETVL_VTYPE_CHANGE_ONLY , new_info , NULL_RTX ) ; else new_pat = gen_vsetvl_pat ( VSETVL_DISCARD_RESULT , new_info , NULL_RTX ) ; return new_pat ; } </s>


<s> const uint32_t * SystemZRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { if ( MF . getSubtarget ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) -> getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_SystemZ_SwiftError_RegMask ; return CSR_SystemZ_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void SITargetLowering :: AdjustInstrPostInstrSelection ( MachineInstr * MI , SDNode * Node ) const { if ( AMDGPU :: isMIMG ( MI -> getOpcode ( ) ) == - 1 ) return ; unsigned VReg = MI -> getOperand ( 0 ) . getReg ( ) ; unsigned Writemask = MI -> getOperand ( 1 ) . getImm ( ) ; unsigned BitsSet = 0 ; for ( unsigned i = 0 ; i < 4 ; ++ i ) BitsSet += Writemask & ( 1 << i ) ? 1 : 0 ; const TargetRegisterClass * RC ; switch ( BitsSet ) { default : return ; case 1 : RC = & AMDGPU :: VReg_32RegClass ; break ; case 2 : RC = & AMDGPU :: VReg_64RegClass ; break ; case 3 : RC = & AMDGPU :: VReg_96RegClass ; break ; } MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; MRI . setRegClass ( VReg , RC ) ; } </s>

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


<s> static tree make_resolver_func ( const tree default_decl , const tree dispatch_decl , basic_block * empty_bb ) { tree decl_name = clone_function_name ( default_decl , "resolver" ) ; const char * resolver_name = IDENTIFIER_POINTER ( decl_name ) ; tree type = build_function_type_list ( ptr_type_node , NULL_TREE ) ; tree decl = build_fn_decl ( resolver_name , type ) ; SET_DECL_ASSEMBLER_NAME ( decl , decl_name ) ; DECL_NAME ( decl ) = decl_name ; TREE_USED ( decl ) = 1 ; DECL_ARTIFICIAL ( decl ) = 1 ; DECL_IGNORED_P ( decl ) = 0 ; TREE_PUBLIC ( decl ) = 0 ; DECL_UNINLINABLE ( decl ) = 1 ; DECL_EXTERNAL ( decl ) = 0 ; DECL_EXTERNAL ( dispatch_decl ) = 0 ; DECL_CONTEXT ( decl ) = NULL_TREE ; DECL_INITIAL ( decl ) = make_node ( BLOCK ) ; DECL_STATIC_CONSTRUCTOR ( decl ) = 0 ; tree t = build_decl ( UNKNOWN_LOCATION , RESULT_DECL , NULL_TREE , ptr_type_node ) ; DECL_ARTIFICIAL ( t ) = 1 ; DECL_IGNORED_P ( t ) = 1 ; DECL_RESULT ( decl ) = t ; gimplify_function_tree ( decl ) ; push_cfun ( DECL_STRUCT_FUNCTION ( decl ) ) ; * empty_bb = init_lowered_empty_function ( decl , false , profile_count :: uninitialized ( ) ) ; cgraph_node :: add_new_function ( decl , true ) ; symtab -> call_cgraph_insertion_hooks ( cgraph_node :: get_create ( decl ) ) ; pop_cfun ( ) ; DECL_ATTRIBUTES ( dispatch_decl ) = make_attribute ( "ifunc" , resolver_name , DECL_ATTRIBUTES ( dispatch_decl ) ) ; cgraph_node :: create_same_body_alias ( dispatch_decl , decl ) ; return decl ; } </s>

Make the resolver function decl to dispatch the versions of a multi- versioned function , DEFAULT_DECL . Create an empty basic block in the resolver and store the pointer in EMPTY_BB . Return the decl of the resolver function .


<s> static reg_class_t s390_preferred_reload_class ( rtx op , reg_class_t rclass ) { switch ( GET_CODE ( op ) ) { case CONST_VECTOR : case CONST_DOUBLE : case CONST_INT : case CONST_WIDE_INT : if ( reg_class_subset_p ( GENERAL_REGS , rclass ) && legitimate_reload_constant_p ( op ) ) return GENERAL_REGS ; else if ( reg_class_subset_p ( ADDR_REGS , rclass ) && legitimate_reload_constant_p ( op ) ) return ADDR_REGS ; else if ( reg_class_subset_p ( FP_REGS , rclass ) && legitimate_reload_fp_constant_p ( op ) ) return FP_REGS ; else if ( reg_class_subset_p ( VEC_REGS , rclass ) && legitimate_reload_vector_constant_p ( op ) ) return VEC_REGS ; return NO_REGS ; case CONST : if ( GET_CODE ( XEXP ( op , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( op , 0 ) , 0 ) ) == SYMBOL_REF && GET_CODE ( XEXP ( XEXP ( op , 0 ) , 1 ) ) == CONST_INT ) { if ( flag_pic && reg_class_subset_p ( ADDR_REGS , rclass ) ) return ADDR_REGS ; else return NO_REGS ; } case LABEL_REF : case SYMBOL_REF : if ( ! legitimate_reload_constant_p ( op ) ) return NO_REGS ; case PLUS : if ( reg_class_subset_p ( ADDR_REGS , rclass ) ) return ADDR_REGS ; else return NO_REGS ; default : break ; } return rclass ; } </s>

Given an rtx OP being reloaded into a reg required to be in class CLASS , return the class of reg to actually use .


<s> bool XCoreTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty ) const { if ( Ty -> getTypeID ( ) == Type :: VoidTyID ) return AM . Scale == 0 && isImmUs ( AM . BaseOffs ) && isImmUs4 ( AM . BaseOffs ) ; const TargetData * TD = TM . getTargetData ( ) ; unsigned Size = TD -> getTypeAllocSize ( Ty ) ; if ( AM . BaseGV ) { return Size >= 4 && ! AM . HasBaseReg && AM . Scale == 0 && AM . BaseOffs % 4 == 0 ; } switch ( Size ) { case 1 : if ( AM . Scale == 0 ) { return isImmUs ( AM . BaseOffs ) ; } return AM . Scale == 1 && AM . BaseOffs == 0 ; case 2 : case 3 : if ( AM . Scale == 0 ) { return isImmUs2 ( AM . BaseOffs ) ; } return AM . Scale == 2 && AM . BaseOffs == 0 ; default : if ( AM . Scale == 0 ) { return isImmUs4 ( AM . BaseOffs ) ; } return AM . Scale == 4 && AM . BaseOffs == 0 ; } return false ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { if ( ! Subtarget -> isAAPCS_ABI ( ) || Subtarget -> isTargetDarwin ( ) ) return SDValue ( ) ; const ARMTargetLowering & TLI = * static_cast < const ARMTargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Type * IntPtrTy = TLI . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( MVT :: i32 ) ) Src = DAG . getNode ( ISD :: TRUNCATE , dl , MVT :: i32 , Src ) ; else Src = DAG . getNode ( ISD :: ZERO_EXTEND , dl , MVT :: i32 , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , 0 , TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , false , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } </s>

Emit target-specific code that performs a memset .


<s> static int rs6000_adjust_cost ( rtx insn , rtx link , rtx dep_insn , int cost ) { if ( ! recog_memoized ( insn ) ) return 0 ; if ( REG_NOTE_KIND ( link ) != 0 ) return 0 ; if ( REG_NOTE_KIND ( link ) == 0 ) { if ( rs6000_sched_groups && GET_CODE ( PATTERN ( insn ) ) == SET && GET_CODE ( PATTERN ( dep_insn ) ) == SET && GET_CODE ( XEXP ( PATTERN ( insn ) , 1 ) ) == MEM && GET_CODE ( XEXP ( PATTERN ( dep_insn ) , 0 ) ) == MEM && ( GET_MODE_SIZE ( GET_MODE ( XEXP ( PATTERN ( insn ) , 1 ) ) ) > GET_MODE_SIZE ( GET_MODE ( XEXP ( PATTERN ( dep_insn ) , 0 ) ) ) ) ) return cost + 14 ; switch ( get_attr_type ( insn ) ) { case TYPE_JMPREG : return TARGET_POWER ? 5 : 4 ; case TYPE_BRANCH : if ( ( rs6000_cpu_attr == CPU_PPC603 || rs6000_cpu_attr == CPU_PPC604 || rs6000_cpu_attr == CPU_PPC604E || rs6000_cpu_attr == CPU_PPC620 || rs6000_cpu_attr == CPU_PPC630 || rs6000_cpu_attr == CPU_PPC750 || rs6000_cpu_attr == CPU_PPC7400 || rs6000_cpu_attr == CPU_PPC7450 || rs6000_cpu_attr == CPU_POWER4 || rs6000_cpu_attr == CPU_POWER5 ) && recog_memoized ( dep_insn ) && ( INSN_CODE ( dep_insn ) >= 0 ) && ( get_attr_type ( dep_insn ) == TYPE_CMP || get_attr_type ( dep_insn ) == TYPE_COMPARE || get_attr_type ( dep_insn ) == TYPE_DELAYED_COMPARE || get_attr_type ( dep_insn ) == TYPE_IMUL_COMPARE || get_attr_type ( dep_insn ) == TYPE_LMUL_COMPARE || get_attr_type ( dep_insn ) == TYPE_FPCOMPARE || get_attr_type ( dep_insn ) == TYPE_CR_LOGICAL || get_attr_type ( dep_insn ) == TYPE_DELAYED_CR ) ) return cost + 2 ; default : break ; } } return cost ; } </s>

Adjust the cost of a scheduling dependency . Return the new cost of a dependency LINK or INSN on DEP_INSN . COST is the current cost .


<s> static struct unw_reg_state * alloc_reg_state ( void ) { struct unw_reg_state * rs ; reg_state_alloced ++ ; rs = malloc ( sizeof ( struct unw_reg_state ) ) ; if ( ! rs ) { int n = atomic_alloc ( & emergency_reg_state_free ) ; if ( n >= 0 ) rs = & emergency_reg_state [ n ] ; } return rs ; } </s>

Allocation and deallocation of structures .


<s> static tree ix86_vectorize_builtin_scatter ( const_tree vectype , const_tree index_type , int scale ) { bool si ; enum ix86_builtins code ; if ( ! TARGET_AVX512F ) return NULL_TREE ; if ( ( TREE_CODE ( index_type ) != INTEGER_TYPE && ! POINTER_TYPE_P ( index_type ) ) || ( TYPE_MODE ( index_type ) != SImode && TYPE_MODE ( index_type ) != DImode ) ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) > POINTER_SIZE ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) < POINTER_SIZE && TYPE_UNSIGNED ( index_type ) ) return NULL_TREE ; if ( scale <= 0 || scale > 8 || ( scale & ( scale - 1 ) ) != 0 ) return NULL_TREE ; si = TYPE_MODE ( index_type ) == SImode ; switch ( TYPE_MODE ( vectype ) ) { case E_V8DFmode : code = si ? IX86_BUILTIN_SCATTERALTSIV8DF : IX86_BUILTIN_SCATTERDIV8DF ; break ; case E_V8DImode : code = si ? IX86_BUILTIN_SCATTERALTSIV8DI : IX86_BUILTIN_SCATTERDIV8DI ; break ; case E_V16SFmode : code = si ? IX86_BUILTIN_SCATTERSIV16SF : IX86_BUILTIN_SCATTERALTDIV16SF ; break ; case E_V16SImode : code = si ? IX86_BUILTIN_SCATTERSIV16SI : IX86_BUILTIN_SCATTERALTDIV16SI ; break ; default : return NULL_TREE ; } return ix86_builtins [ code ] ; } </s>

Returns a decl of a function that implements scatter store with register type VECTYPE and index type INDEX_TYPE and SCALE . Return NULL_TREE if it is not available .


<s> static bool rs6000_update_ipa_fn_target_info ( unsigned int & info , const gimple * stmt ) { if ( gimple_code ( stmt ) == GIMPLE_ASM ) { info |= RS6000_FN_TARGET_INFO_HTM ; return false ; } else if ( gimple_code ( stmt ) == GIMPLE_CALL ) { tree fndecl = gimple_call_fndecl ( stmt ) ; if ( fndecl && fndecl_built_in_p ( fndecl , BUILT_IN_MD ) ) { enum rs6000_gen_builtins fcode = ( enum rs6000_gen_builtins ) DECL_MD_FUNCTION_CODE ( fndecl ) ; if ( bif_is_htm ( rs6000_builtin_info [ fcode ] ) ) { info |= RS6000_FN_TARGET_INFO_HTM ; return false ; } } } return true ; } </s>

Hook to update target specific information INFO for inlining by checking the given STMT . Return false if we do n't need to scan any more , otherwise return true .


<s> InstructionCost WebAssemblyTTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: TargetCostKind CostKind , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args , const Instruction * CxtI ) { InstructionCost Cost = BasicTTIImplBase < WebAssemblyTTIImpl > :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( auto * VTy = dyn_cast < VectorType > ( Ty ) ) { switch ( Opcode ) { case Instruction :: LShr : case Instruction :: AShr : case Instruction :: Shl : if ( Opd2Info != TTI :: OK_UniformValue && Opd2Info != TTI :: OK_UniformConstantValue ) Cost = cast < FixedVectorType > ( VTy ) -> getNumElements ( ) * ( TargetTransformInfo :: TCC_Basic + getArithmeticInstrCost ( Opcode , VTy -> getElementType ( ) , CostKind ) + TargetTransformInfo :: TCC_Basic ) ; break ; } } return Cost ; } </s>

This is an approximation of reciprocal throughput of a math/logic op .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s>
void
arc_save_restore
(
FILE
*
file
,
const
char
*
base_reg
,
unsigned
int
offset
,
unsigned
int
gmask
,
const
char
*
op
)
{
int
regno
;
if
(
gmask
==
0
)
return
;
for
(
regno
=
0
;
regno
<=
31
;
regno
++
)
{
if
(
(
gmask
&
(
1L
<<
regno
)
)
!=
0
)
{
fprintf
(
file
,
"\t%s %s,[%s,%d]\n"
,
op
,
reg_names
[
regno
]
,
base_reg
,
offset
)
;
offset
+=
UNITS_PER_WORD
;
}
}
}
</s>

BASE_REG is the base register to use for addressing and to adjust . GMASK is a bitmask of general purpose registers to save/restore . epilogue_p 0 : prologue 1 : epilogue 2 : epilogue , sibling thunk If * FIRST_OFFSET is non-zero , add it first to BASE_REG - preferably using a pre-modify for the first memory access . * FIRST_OFFSET is then zeroed .


<s> unsigned HexagonInstrInfo :: getInlineAsmLength ( const char * Str , const MCAsmInfo & MAI , const TargetSubtargetInfo * STI ) const { StringRef AStr ( Str ) ; bool atInsnStart = true ; unsigned Length = 0 ; const unsigned MaxInstLength = MAI . getMaxInstLength ( STI ) ; for ( ; * Str ; ++ Str ) { if ( * Str == '\n' || strncmp ( Str , MAI . getSeparatorString ( ) , strlen ( MAI . getSeparatorString ( ) ) ) == 0 ) atInsnStart = true ; if ( atInsnStart && ! isSpace ( static_cast < unsigned char > ( * Str ) ) ) { Length += MaxInstLength ; atInsnStart = false ; } if ( atInsnStart && strncmp ( Str , MAI . getCommentString ( ) . data ( ) , MAI . getCommentString ( ) . size ( ) ) == 0 ) atInsnStart = false ; } StringRef Occ ( "##" ) ; Length += AStr . count ( Occ ) * 4 ; return Length ; } </s>

Measure the specified inline asm to determine an approximation of its length .


<s> Instruction * PPCTargetLowering :: emitLeadingFence ( IRBuilder < > & Builder , AtomicOrdering Ord , bool IsStore , bool IsLoad ) const { if ( Ord == SequentiallyConsistent ) return callIntrinsic ( Builder , Intrinsic :: ppc_sync ) ; else if ( isAtLeastRelease ( Ord ) ) return callIntrinsic ( Builder , Intrinsic :: ppc_lwsync ) ; else return nullptr ; } </s>


<s>
bool
AMDGPUCallLowering
::
lowerReturn
(
MachineIRBuilder
&
B
,
const
Value
*
Val
,
ArrayRef
<
Register
>
VRegs
,
FunctionLoweringInfo
&
FLI
)
const
{
MachineFunction
&
MF
=
B
.
getMF
(
)
;
SIMachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MFI
->
setIfReturnsVoid
(
!
Val
)
;
assert
(
!
Val
==
VRegs
.
empty
(
)
&&
"Return value without a vreg"
)
;
CallingConv
::
ID
CC
=
B
.
getMF
(
)
.
getFunction
(
)
.
getCallingConv
(
)
;
const
bool
IsShader
=
AMDGPU
::
isShader
(
CC
)
;
const
bool
IsWaveEnd
=
(
IsShader
&&
MFI
->
returnsVoid
(
)
)
||
AMDGPU
::
isKernel
(
CC
)
;
if
(
IsWaveEnd
)
{
B
.
buildInstr
(
AMDGPU
::
S_ENDPGM
)
.
addImm
(
0
)
;
return
true
;
}
unsigned
ReturnOpc
=
IsShader
AMDGPU
::
SI_RETURN_TO_EPILOG
:
AMDGPU
::
SI_RETURN
;
auto
Ret
=
B
.
buildInstrNoInsert
(
ReturnOpc
)
;
if
(
!
FLI
.
CanLowerReturn
)
insertSRetStores
(
B
,
Val
->
getType
(
)
,
VRegs
,
FLI
.
DemoteRegister
)
;
else
if
(
!
lowerReturnVal
(
B
,
Val
,
VRegs
,
Ret
)
)
return
false
;
B
.
insertInstr
(
Ret
)
;
return
true
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> bool RegisterAliasInfo :: alias ( RegisterRef RA , RegisterRef RB ) const { bool VirtA = TargetRegisterInfo :: isVirtualRegister ( RA . Reg ) ; bool VirtB = TargetRegisterInfo :: isVirtualRegister ( RB . Reg ) ; bool PhysA = TargetRegisterInfo :: isPhysicalRegister ( RA . Reg ) ; bool PhysB = TargetRegisterInfo :: isPhysicalRegister ( RB . Reg ) ; if ( VirtA != VirtB ) return false ; if ( VirtA ) { if ( RA . Reg != RB . Reg ) return false ; if ( RA . Sub == 0 || RB . Sub == 0 ) return true ; unsigned SA = TRI . getSubRegIdxSize ( RA . Sub ) ; unsigned OA = TRI . getSubRegIdxOffset ( RA . Sub ) ; unsigned SB = TRI . getSubRegIdxSize ( RB . Sub ) ; unsigned OB = TRI . getSubRegIdxOffset ( RB . Sub ) ; if ( OA <= OB && OA + SA > OB ) return true ; if ( OB <= OA && OB + SB > OA ) return true ; return false ; } assert ( PhysA && PhysB ) ; ( void ) PhysA , ( void ) PhysB ; unsigned A = RA . Sub ? TRI . getSubReg ( RA . Reg , RA . Sub ) : RA . Reg ; unsigned B = RB . Sub ? TRI . getSubReg ( RB . Reg , RB . Sub ) : RB . Reg ; for ( MCRegAliasIterator I ( A , & TRI , true ) ; I . isValid ( ) ; ++ I ) if ( B == * I ) return true ; return false ; } </s>

alias - If one of the pointers is to a global that we are tracking , and the other is some random pointer , we know there can not be an alias , because the address of the global is n't taken .


<s> void addBlockPlacement ( ) override { } </s>

Add standard basic block placement passes .


<s> static void s390_add_pool_insn ( struct constant_pool * pool , rtx insn ) { bitmap_set_bit ( pool -> insns , INSN_UID ( insn ) ) ; } </s>

Add INSN to the list of insns covered by POOL .


<s> bool isLegalMaskedGather ( Type * DataType , Align Alignment ) const { return isLegalMaskedGatherScatter ( DataType ) ; } </s>

Return true if the target supports masked gather .


<s>
static
const
struct
riscv_cpu_info
*
riscv_parse_cpu
(
const
char
*
cpu_string
)
{
for
(
unsigned
i
=
0
;
i
<
ARRAY_SIZE
(
riscv_cpu_info_table
)
;
i
++
)
if
(
strcmp
(
riscv_cpu_info_table
[
i
]
.
name
,
cpu_string
)
==
0
)
return
riscv_cpu_info_table
+
i
;
error
(
"unknown cpu %qs for %<-mtune%>"
,
cpu_string
)
;
return
riscv_cpu_info_table
;
}
</s>

Return the riscv_cpu_info entry for the given name string .


<s> bool ARMTargetLowering :: isFMAFasterThanFMulAndFAdd ( const MachineFunction & MF , EVT VT ) const { if ( ! Subtarget -> hasMVEFloatOps ( ) ) return false ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: v4f32 : case MVT :: v8f16 : return true ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> static void mips_adjust_block_mem ( rtx mem , HOST_WIDE_INT length , rtx * loop_reg , rtx * loop_mem ) { * loop_reg = copy_addr_to_reg ( XEXP ( mem , 0 ) ) ; * loop_mem = change_address ( mem , BLKmode , * loop_reg ) ; set_mem_align ( * loop_mem , MIN ( MEM_ALIGN ( mem ) , length * BITS_PER_UNIT ) ) ; } </s>

Helper function for doing a loop-based block operation on memory reference MEM . Each iteration of the loop will operate on LENGTH bytes of MEM . Create a new base register for use within the loop and point it to the start of MEM . Create a new memory reference that uses this register . Store them in * LOOP_REG and * LOOP_MEM respectively .


<s> unsigned X86RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; unsigned FPDiff = TFI -> hasFP ( MF ) ? 1 : 0 ; switch ( RC -> getID ( ) ) { default : return 0 ; case X86 :: GR32RegClassID : return 4 - FPDiff ; case X86 :: GR64RegClassID : return 12 - FPDiff ; case X86 :: VR128RegClassID : return TM . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ? 10 : 4 ; case X86 :: VR64RegClassID : return 4 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s>
static
tree
h8300_handle_eightbit_data_attribute
(
tree
*
node
,
tree
name
,
tree
args
ATTRIBUTE_UNUSED
,
int
flags
ATTRIBUTE_UNUSED
,
bool
*
no_add_attrs
)
{
tree
decl
=
*
node
;
if
(
TREE_STATIC
(
decl
)
||
DECL_EXTERNAL
(
decl
)
)
{
DECL_SECTION_NAME
(
decl
)
=
build_string
(
7
,
".eight"
)
;
}
else
{
warning
(
OPT_Wattributes
,
"%qs attribute ignored"
,
IDENTIFIER_POINTER
(
name
)
)
;
*
no_add_attrs
=
true
;
}
return
NULL_TREE
;
}
</s>

Handle an `` eightbit_data '' attribute ; arguments as in struct attribute_spec.handler .


<s> static rtx ldv_expand_builtin ( rtx target , insn_code icode , rtx * op , machine_mode tmode ) { if ( target == 0 || GET_MODE ( target ) != tmode || ! insn_data [ icode ] . operand [ 0 ] . predicate ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; op [ 1 ] = copy_to_mode_reg ( Pmode , op [ 1 ] ) ; bool blk = ( icode == CODE_FOR_altivec_lvlx || icode == CODE_FOR_altivec_lvlxl || icode == CODE_FOR_altivec_lvrx || icode == CODE_FOR_altivec_lvrxl ) ; if ( icode == CODE_FOR_altivec_lvx_v1ti || icode == CODE_FOR_altivec_lvx_v2df || icode == CODE_FOR_altivec_lvx_v2di || icode == CODE_FOR_altivec_lvx_v4sf || icode == CODE_FOR_altivec_lvx_v4si || icode == CODE_FOR_altivec_lvx_v8hi || icode == CODE_FOR_altivec_lvx_v16qi ) { rtx rawaddr ; if ( op [ 0 ] == const0_rtx ) rawaddr = op [ 1 ] ; else { op [ 0 ] = copy_to_mode_reg ( Pmode , op [ 0 ] ) ; rawaddr = gen_rtx_PLUS ( Pmode , op [ 1 ] , op [ 0 ] ) ; } rtx addr = gen_rtx_AND ( Pmode , rawaddr , gen_rtx_CONST_INT ( Pmode , - 16 ) ) ; addr = gen_rtx_MEM ( blk ? BLKmode : tmode , addr ) ; emit_insn ( gen_rtx_SET ( target , addr ) ) ; } else { rtx addr ; if ( op [ 0 ] == const0_rtx ) addr = gen_rtx_MEM ( blk ? BLKmode : tmode , op [ 1 ] ) ; else { op [ 0 ] = copy_to_mode_reg ( Pmode , op [ 0 ] ) ; addr = gen_rtx_MEM ( blk ? BLKmode : tmode , gen_rtx_PLUS ( Pmode , op [ 1 ] , op [ 0 ] ) ) ; } rtx pat = GEN_FCN ( icode ) ( target , addr ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; } return target ; } </s>

Expand an AltiVec vector load builtin , and return the expanded rtx .


<s>
void
GBZ80MCInstLower
::
lowerInstruction
(
const
MachineInstr
&
MI
,
MCInst
&
OutMI
)
const
{
OutMI
.
setOpcode
(
MI
.
getOpcode
(
)
)
;
for
(
MachineOperand
const
&
MO
:
MI
.
operands
(
)
)
{
MCOperand
MCOp
;
switch
(
MO
.
getType
(
)
)
{
default
:
MI
.
print
(
errs
(
)
)
;
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
)
continue
;
MCOp
=
MCOperand
::
createReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
createImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
getSymbol
(
MO
.
getGlobal
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
createExpr
(
MCSymbolRefExpr
::
create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
Ctx
)
)
;
break
;
case
MachineOperand
::
MO_RegisterMask
:
continue
;
case
MachineOperand
::
MO_BlockAddress
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetJTISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetCPISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
}
OutMI
.
addOperand
(
MCOp
)
;
}
}
</s>


<s> void MipsELFStreamer :: emitIntValue ( uint64_t Value , unsigned Size ) { MCELFStreamer :: emitIntValue ( Value , Size ) ; Labels . clear ( ) ; } </s>

Special case of EmitValue that avoids the client having to pass in a MCExpr for constant integers .


<s> bool SIInsertSkips :: runOnMachineFunction ( MachineFunction & MF ) { const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; SkipThreshold = SkipThresholdFlag ; bool HaveKill = false ; bool MadeChange = false ; SmallVector < MachineBasicBlock * , 16 > ExecBranchStack ; MachineFunction :: iterator NextBB ; MachineBasicBlock * EmptyMBBAtEnd = nullptr ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; BI = NextBB ) { NextBB = std :: next ( BI ) ; MachineBasicBlock & MBB = * BI ; bool HaveSkipBlock = false ; if ( ! ExecBranchStack . empty ( ) && ExecBranchStack . back ( ) == & MBB ) { ExecBranchStack . pop_back ( ) ; } if ( HaveKill && ExecBranchStack . empty ( ) ) { HaveKill = false ; } MachineBasicBlock :: iterator I , Next ; for ( I = MBB . begin ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; switch ( MI . getOpcode ( ) ) { case AMDGPU :: SI_MASK_BRANCH : ExecBranchStack . push_back ( MI . getOperand ( 0 ) . getMBB ( ) ) ; MadeChange |= skipMaskBranch ( MI , MBB ) ; break ; case AMDGPU :: S_BRANCH : if ( MBB . isLayoutSuccessor ( MI . getOperand ( 0 ) . getMBB ( ) ) ) { MI . eraseFromParent ( ) ; } else if ( HaveSkipBlock ) { MI . eraseFromParent ( ) ; } break ; case AMDGPU :: SI_KILL_TERMINATOR : MadeChange = true ; kill ( MI ) ; if ( ExecBranchStack . empty ( ) ) { if ( skipIfDead ( MI , * NextBB ) ) { HaveSkipBlock = true ; NextBB = std :: next ( BI ) ; BE = MF . end ( ) ; } } else { HaveKill = true ; } MI . eraseFromParent ( ) ; break ; case AMDGPU :: SI_RETURN_TO_EPILOG : assert ( ! MF . getInfo < SIMachineFunctionInfo > ( ) -> returnsVoid ( ) ) ; if ( BI != -- MF . end ( ) || I != MBB . getFirstTerminator ( ) ) { if ( ! EmptyMBBAtEnd ) { EmptyMBBAtEnd = MF . CreateMachineBasicBlock ( ) ; MF . insert ( MF . end ( ) , EmptyMBBAtEnd ) ; } MBB . addSuccessor ( EmptyMBBAtEnd ) ; BuildMI ( * BI , I , MI . getDebugLoc ( ) , TII -> get ( AMDGPU :: S_BRANCH ) ) . addMBB ( EmptyMBBAtEnd ) ; I -> eraseFromParent ( ) ; } break ; default : break ; } } } return MadeChange ; } </s>

runOnMachineFunction - Emit the function body .


<s> void ix86_split_copysign_var ( rtx operands [ ] ) { enum machine_mode mode , vmode ; rtx dest , scratch , op0 , op1 , mask , nmask , x ; dest = operands [ 0 ] ; scratch = operands [ 1 ] ; op0 = operands [ 2 ] ; op1 = operands [ 3 ] ; nmask = operands [ 4 ] ; mask = operands [ 5 ] ; mode = GET_MODE ( dest ) ; vmode = GET_MODE ( mask ) ; if ( rtx_equal_p ( op0 , op1 ) ) { emit_move_insn ( dest , op0 ) ; return ; } if ( REG_P ( mask ) && REGNO ( dest ) == REGNO ( mask ) ) { gcc_assert ( REGNO ( op1 ) == REGNO ( scratch ) ) ; x = gen_rtx_AND ( vmode , scratch , mask ) ; emit_insn ( gen_rtx_SET ( VOIDmode , scratch , x ) ) ; dest = mask ; op0 = simplify_gen_subreg ( vmode , op0 , mode , 0 ) ; x = gen_rtx_NOT ( vmode , dest ) ; x = gen_rtx_AND ( vmode , x , op0 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , x ) ) ; } else { if ( REGNO ( op1 ) == REGNO ( scratch ) ) { x = gen_rtx_AND ( vmode , scratch , mask ) ; } else { gcc_assert ( REGNO ( mask ) == REGNO ( scratch ) ) ; op1 = simplify_gen_subreg ( vmode , op1 , mode , 0 ) ; x = gen_rtx_AND ( vmode , scratch , op1 ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , scratch , x ) ) ; if ( REGNO ( op0 ) == REGNO ( dest ) ) { dest = simplify_gen_subreg ( vmode , op0 , mode , 0 ) ; x = gen_rtx_AND ( vmode , dest , nmask ) ; } else { gcc_assert ( REGNO ( nmask ) == REGNO ( dest ) ) ; dest = nmask ; op0 = simplify_gen_subreg ( vmode , op0 , mode , 0 ) ; x = gen_rtx_AND ( vmode , dest , op0 ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , dest , x ) ) ; } x = gen_rtx_IOR ( vmode , dest , scratch ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , x ) ) ; } </s>

Deconstruct a copysign operation into bit masks . Operand 0 is variable , so we have to do two masks .


<s> static unsigned int aarch64_add_offset_1_temporaries ( HOST_WIDE_INT offset ) { return abs_hwi ( offset ) < 0x1000000 ? 0 : 1 ; } </s>

Return the number of temporary registers that aarch64_add_offset_1 would need to add OFFSET to a register .


<s> DecodeStatus AVRDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CStream ) const { uint32_t Insn ; DecodeStatus Result ; { Result = readInstruction16 ( Bytes , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( getDecoderTable ( Size ) , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) return Result ; Result = decodeLoadStore ( Instr , Insn , Address , this ) ; if ( Result != MCDisassembler :: Fail ) return Result ; } { Result = readInstruction32 ( Bytes , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( getDecoderTable ( Size ) , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { return Result ; } return MCDisassembler :: Fail ; } } </s>

Returns the disassembly of a single instruction .


<s> bool arm_coproc_builtin_available ( enum unspecv builtin ) { if ( TARGET_THUMB1 ) return false ; switch ( builtin ) { case VUNSPEC_CDP : case VUNSPEC_LDC : case VUNSPEC_LDCL : case VUNSPEC_STC : case VUNSPEC_STCL : case VUNSPEC_MCR : case VUNSPEC_MRC : if ( arm_arch4 ) return true ; break ; case VUNSPEC_CDP2 : case VUNSPEC_LDC2 : case VUNSPEC_LDC2L : case VUNSPEC_STC2 : case VUNSPEC_STC2L : case VUNSPEC_MCR2 : case VUNSPEC_MRC2 : if ( arm_arch5 ) return true ; break ; case VUNSPEC_MCRR : case VUNSPEC_MRRC : if ( arm_arch6 || arm_arch5te ) return true ; break ; case VUNSPEC_MCRR2 : case VUNSPEC_MRRC2 : if ( arm_arch6 ) return true ; break ; default : gcc_unreachable ( ) ; } return false ; } </s>

This function checks for the availability of the coprocessor builtin passed in BUILTIN for the current target . Returns true if it is available and false otherwise . If a BUILTIN is passed for which this function has not been implemented it will cause an exception .


<s> static int sh_issue_rate ( void ) { if ( TARGET_SUPERSCALAR ) return 2 ; else return 1 ; } </s>

This function returns `` 2 '' to indicate dual issue for the SH4 processor . To be used by the DFA pipeline description .


"FPDelta isn't aligned per the Win64 ABI!"

"VLAs and dynamic stack realign, but no FP?!"

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> static bool ix86_eax_live_at_start_p ( void ) { return REGNO_REG_SET_P ( df_get_live_out ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) , 0 ) ; } </s>

Return true if EAX is live at the start of the function . Used by ix86_expand_prologue to determine if we need special help before calling allocate_stack_worker .


<s> bool R600InstrInfo :: isPredicated ( const MachineInstr & MI ) const { int idx = MI . findFirstPredOperandIdx ( ) ; if ( idx < 0 ) return false ; Register Reg = MI . getOperand ( idx ) . getReg ( ) ; switch ( Reg ) { default : return false ; case R600 :: PRED_SEL_ONE : case R600 :: PRED_SEL_ZERO : case R600 :: PREDICATE_BIT : return true ; } } </s>

Returns true if the instruction is already predicated .


<s> static reg_class_t mn10300_preferred_output_reload_class ( rtx x , reg_class_t rclass ) { if ( x == stack_pointer_rtx && rclass != SP_REGS ) return ( TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS ) ; return rclass ; } </s>


<s> static rtx xtensa_function_incoming_arg ( cumulative_args_t cum , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { return xtensa_function_arg_1 ( cum , mode , type , true ) ; } </s>