<s>
bool
MCS51InstrInfo
::
reverseBranchCondition
(
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
assert
(
Cond
.
size
(
)
==
1
&&
"Invalid MCS51 branch condition!"
)
;
MCS51CC
::
CondCodes
CC
=
static_cast
<
MCS51CC
::
CondCodes
>
(
Cond
[
0
]
.
getImm
(
)
)
;
Cond
[
0
]
.
setImm
(
getOppositeCondition
(
CC
)
)
;
return
false
;
}
</s>


<s> bool ARMTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , const Type * Ty ) const { if ( ! isLegalAddressImmediate ( AM . BaseOffs , getValueType ( Ty , true ) , Subtarget ) ) return false ; if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( Subtarget -> isThumb ( ) ) return false ; default : if ( AM . BaseOffs ) return false ; int Scale = AM . Scale ; switch ( getValueType ( Ty ) . getSimpleVT ( ) ) { default : return false ; case MVT :: i1 : case MVT :: i8 : case MVT :: i32 : case MVT :: i64 : if ( Scale < 0 ) Scale = - Scale ; if ( Scale == 1 ) return true ; return isPowerOf2_32 ( Scale & ~ 1 ) ; case MVT :: i16 : if ( ( ( unsigned ) AM . HasBaseReg + Scale ) <= 2 ) return true ; return false ; case MVT :: isVoid : if ( AM . Scale & 1 ) return false ; return isPowerOf2_32 ( AM . Scale ) ; } break ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s>
static
const
struct
riscv_tune_info
*
riscv_parse_tune
(
const
char
*
tune_string
)
{
const
riscv_cpu_info
*
cpu
=
riscv_find_cpu
(
tune_string
)
;
if
(
cpu
)
tune_string
=
cpu
->
tune
;
for
(
unsigned
i
=
0
;
i
<
ARRAY_SIZE
(
riscv_tune_info_table
)
;
i
++
)
if
(
strcmp
(
riscv_tune_info_table
[
i
]
.
name
,
tune_string
)
==
0
)
return
riscv_tune_info_table
+
i
;
error
(
"unknown cpu %qs for %<-mtune%>"
,
tune_string
)
;
return
riscv_tune_info_table
;
}
</s>

Return the riscv_tune_info entry for the given name string .


<s>
bool
X86InstrInfo
::
classifyLEAReg
(
MachineInstr
&
MI
,
const
MachineOperand
&
Src
,
unsigned
Opc
,
bool
AllowSP
,
Register
&
NewSrc
,
bool
&
isKill
,
MachineOperand
&
ImplicitOp
,
LiveVariables
*
LV
)
const
{
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
const
TargetRegisterClass
*
RC
;
if
(
AllowSP
)
{
RC
=
Opc
!=
X86
::
LEA32r
&
X86
::
GR64RegClass
:
&
X86
::
GR32RegClass
;
}
else
{
RC
=
Opc
!=
X86
::
LEA32r
&
X86
::
GR64_NOSPRegClass
:
&
X86
::
GR32_NOSPRegClass
;
}
Register
SrcReg
=
Src
.
getReg
(
)
;
if
(
Opc
!=
X86
::
LEA64_32r
)
{
NewSrc
=
SrcReg
;
isKill
=
Src
.
isKill
(
)
;
assert
(
!
Src
.
isUndef
(
)
&&
"Undef op doesn't need optimization"
)
;
if
(
Register
::
isVirtualRegister
(
NewSrc
)
&&
!
MF
.
getRegInfo
(
)
.
constrainRegClass
(
NewSrc
,
RC
)
)
return
false
;
return
true
;
}
if
(
Register
::
isPhysicalRegister
(
SrcReg
)
)
{
ImplicitOp
=
Src
;
ImplicitOp
.
setImplicit
(
)
;
NewSrc
=
getX86SubSuperRegister
(
Src
.
getReg
(
)
,
64
)
;
isKill
=
Src
.
isKill
(
)
;
assert
(
!
Src
.
isUndef
(
)
&&
"Undef op doesn't need optimization"
)
;
}
else
{
NewSrc
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
RC
)
;
MachineInstr
*
Copy
=
BuildMI
(
*
MI
.
getParent
(
)
,
MI
,
MI
.
getDebugLoc
(
)
,
get
(
TargetOpcode
::
COPY
)
)
.
addReg
(
NewSrc
,
RegState
::
Define
|
RegState
::
Undef
,
X86
::
sub_32bit
)
.
add
(
Src
)
;
isKill
=
true
;
if
(
LV
)
LV
->
replaceKillInstruction
(
SrcReg
,
MI
,
*
Copy
)
;
}
return
true
;
}
</s>

Given an operand within a MachineInstr , insert preceding code to put it into the right format for a particular kind of LEA instruction .


"getIntImmCost can only estimate cost of materialising integers"

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


"Unexpected data type for Gather/Scatter"

Calculate the cost of Gather / Scatter operation .


"loadRegFromStackSlot didn't insert any code!"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> LoadInst * X86TargetLowering :: lowerIdempotentRMWIntoFencedLoad ( AtomicRMWInst * AI ) const { unsigned NativeWidth = Subtarget . is64Bit ( ) ? 64 : 32 ; Type * MemType = AI -> getType ( ) ; if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) return nullptr ; auto Builder = IRBuilder < > ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SynchScope = AI -> getSynchScope ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; auto Ptr = AI -> getPointerOperand ( ) ; if ( SynchScope == SingleThread ) return nullptr ; if ( ! hasMFENCE ( Subtarget ) ) return nullptr ; Function * MFence = llvm :: Intrinsic :: getDeclaration ( M , Intrinsic :: x86_sse2_mfence ) ; Builder . CreateCall ( MFence , { } ) ; LoadInst * Loaded = Builder . CreateAlignedLoad ( Ptr , AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ) ; Loaded -> setAtomic ( Order , SynchScope ) ; AI -> replaceAllUsesWith ( Loaded ) ; AI -> eraseFromParent ( ) ; return Loaded ; } </s>

On some platforms , an AtomicRMW that never actually modifies the value ( such as fetch_add of 0 ) can be turned into a fence followed by an atomic load .


<s> static void init_vselect_insn ( void ) { unsigned i ; rtx x ; x = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( MAX_VECT_LEN ) ) ; for ( i = 0 ; i < MAX_VECT_LEN ; ++ i ) XVECEXP ( x , 0 , i ) = const0_rtx ; x = gen_rtx_VEC_SELECT ( V2DFmode , gen_rtx_VEC_CONCAT ( V4DFmode , const0_rtx , const0_rtx ) , x ) ; x = gen_rtx_SET ( const0_rtx , x ) ; start_sequence ( ) ; vselect_insn = emit_insn ( x ) ; end_sequence ( ) ; } </s>


<s> StringRef getPassName ( ) const override { return RISCV_EXPAND_PSEUDO_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> static bool mips_hard_regno_call_part_clobbered ( unsigned int regno , machine_mode mode ) { if ( TARGET_FLOATXX && hard_regno_nregs ( regno , mode ) == 1 && FP_REG_P ( regno ) && ( regno & 1 ) != 0 ) return true ; if ( ISA_HAS_MSA && FP_REG_P ( regno ) && GET_MODE_SIZE ( mode ) > 8 ) return true ; return false ; } </s>

Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED . Odd-numbered single-precision registers are not considered callee-saved for o32 FPXX as they will be clobbered when run on an FR=1 FPU . MSA vector registers with MODE > 64 bits are part clobbered too .


<s> bool PPCTargetLowering :: IsEligibleForTailCallOptimization ( SDValue Callee , CallingConv :: ID CalleeCC , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SelectionDAG & DAG ) const { if ( ! getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) return false ; if ( isVarArg ) return false ; MachineFunction & MF = DAG . getMachineFunction ( ) ; CallingConv :: ID CallerCC = MF . getFunction ( ) . getCallingConv ( ) ; if ( CalleeCC == CallingConv :: Fast && CallerCC == CalleeCC ) { for ( unsigned i = 0 ; i != Ins . size ( ) ; i ++ ) { ISD :: ArgFlagsTy Flags = Ins [ i ] . Flags ; if ( Flags . isByVal ( ) ) return false ; } if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) return true ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) return G -> getGlobal ( ) -> hasHiddenVisibility ( ) || G -> getGlobal ( ) -> hasProtectedVisibility ( ) ; } return false ; } </s>

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization .

PowerPC PPC ISD::InputArg 0 ISD::ArgFlagsTy


<s> void visium_expand_fp_cstore ( rtx * operands , enum machine_mode mode ATTRIBUTE_UNUSED ) { enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; rtx op0 = operands [ 0 ] , op1 = operands [ 2 ] , op2 = operands [ 3 ] , slt ; bool reverse = false ; switch ( code ) { case UNLE : case UNGE : code = reverse_condition_maybe_unordered ( code ) ; reverse = true ; case LT : case GT : if ( code == GT ) { rtx tmp = op1 ; op1 = op2 ; op2 = tmp ; } break ; default : gcc_unreachable ( ) ; } slt = gen_rtx_LT ( SImode , op1 , op2 ) ; if ( reverse ) { rtx tmp = copy_to_mode_reg ( SImode , gen_rtx_NEG ( SImode , slt ) ) ; emit_insn ( gen_add3_insn ( op0 , tmp , const1_rtx ) ) ; } else emit_insn ( gen_rtx_SET ( VOIDmode , op0 , slt ) ) ; } </s>

Expand a cstore of OPERANDS in MODE for LT/GT/UNGE/UNLE . We generate the result in the C flag and use the ADC/SUBC instructions to write it into the destination register .


<s> static int bb_earliest_end_cycle ( basic_block bb , rtx ignore ) { int earliest = 0 ; rtx_insn * insn ; FOR_BB_INSNS ( bb , insn ) { int cycles , this_clock ; if ( LABEL_P ( insn ) || NOTE_P ( insn ) || DEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER || insn == ignore ) continue ; this_clock = insn_get_clock ( insn ) ; cycles = get_attr_cycles ( insn ) ; if ( earliest < this_clock + cycles ) earliest = this_clock + cycles ; } return earliest ; } </s>

Return the number of cycles taken by BB , as computed by scheduling , including the latencies of all insns with delay slots . IGNORE is an insn we should ignore in the calculation , usually the final branch .


<s> TargetLowering :: ConstraintType SystemZTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'a' : case 'd' : case 'f' : case 'h' : case 'r' : case 'v' : return C_RegisterClass ; case 'Q' : case 'R' : case 'S' : case 'T' : case 'm' : return C_Memory ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : return C_Immediate ; default : break ; } } else if ( Constraint . size ( ) == 2 && Constraint [ 0 ] == 'Z' ) { switch ( Constraint [ 1 ] ) { case 'Q' : case 'R' : case 'S' : case 'T' : return C_Address ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


"********** Fixing Irreducible Control Flow **********\n"

runOnMachineFunction - Emit the function body .


<s> int PPCInstrInfo :: getOperandLatency ( const InstrItineraryData * ItinData , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * UseMI , unsigned UseIdx ) const { int Latency = PPCGenInstrInfo :: getOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ; if ( ! DefMI -> getParent ( ) ) return Latency ; const MachineOperand & DefMO = DefMI -> getOperand ( DefIdx ) ; unsigned Reg = DefMO . getReg ( ) ; bool IsRegCR ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { const MachineRegisterInfo * MRI = & DefMI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; IsRegCR = MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & PPC :: CRRCRegClass ) || MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & PPC :: CRBITRCRegClass ) ; } else { IsRegCR = PPC :: CRRCRegClass . contains ( Reg ) || PPC :: CRBITRCRegClass . contains ( Reg ) ; } if ( UseMI -> isBranch ( ) && IsRegCR ) { if ( Latency < 0 ) Latency = getInstrLatency ( ItinData , DefMI ) ; unsigned Directive = Subtarget . getDarwinDirective ( ) ; switch ( Directive ) { default : break ; case PPC :: DIR_7400 : case PPC :: DIR_750 : case PPC :: DIR_970 : case PPC :: DIR_E5500 : case PPC :: DIR_PWR4 : case PPC :: DIR_PWR5 : case PPC :: DIR_PWR5X : case PPC :: DIR_PWR6 : case PPC :: DIR_PWR6X : case PPC :: DIR_PWR7 : case PPC :: DIR_PWR8 : Latency += 2 ; break ; } } return Latency ; } </s>

Compute and return the use operand latency of a given pair of def and use .


<s>
static
void
rs6000_elf_asm_out_constructor
(
rtx
symbol
,
int
priority
)
{
const
char
*
section
=
".ctors"
;
char
buf
[
16
]
;
if
(
priority
!=
DEFAULT_INIT_PRIORITY
)
{
sprintf
(
buf
,
".ctors.%.5u"
,
MAX_INIT_PRIORITY
priority
)
;
section
=
buf
;
}
named_section_flags
(
section
,
SECTION_WRITE
)
;
assemble_align
(
POINTER_SIZE
)
;
if
(
TARGET_RELOCATABLE
)
{
fputs
(
"\t.long ("
,
asm_out_file
)
;
output_addr_const
(
asm_out_file
,
symbol
)
;
fputs
(
")@fixup\n"
,
asm_out_file
)
;
}
else
assemble_integer
(
symbol
,
POINTER_SIZE
/
BITS_PER_UNIT
,
POINTER_SIZE
,
1
)
;
}
</s>


<s> unsigned TPCTTIImpl :: getNumberOfRegisters ( bool Vector ) const { if ( Vector ) return 40 ; return 32 ; } </s>


<s> static bool legitimate_scaled_address_p ( machine_mode mode , rtx op , bool strict ) { if ( GET_CODE ( op ) != PLUS ) return false ; if ( GET_CODE ( XEXP ( op , 0 ) ) != MULT ) return false ; if ( ! RTX_OK_FOR_INDEX_P ( XEXP ( XEXP ( op , 0 ) , 0 ) , strict ) ) return false ; if ( ! CONST_INT_P ( XEXP ( XEXP ( op , 0 ) , 1 ) ) ) return false ; switch ( GET_MODE_SIZE ( mode ) ) { case 2 : if ( INTVAL ( XEXP ( XEXP ( op , 0 ) , 1 ) ) != 2 ) return false ; break ; case 8 : if ( ! TARGET_LL64 ) return false ; case 4 : if ( INTVAL ( XEXP ( XEXP ( op , 0 ) , 1 ) ) != 4 ) return false ; default : return false ; } if ( RTX_OK_FOR_BASE_P ( XEXP ( op , 1 ) , ( strict ) ) ) return true ; if ( flag_pic ) { if ( CONST_INT_P ( XEXP ( op , 1 ) ) ) return true ; return false ; } if ( legitimate_small_data_address_p ( op , mode ) ) return false ; if ( CONSTANT_P ( XEXP ( op , 1 ) ) ) return true ; return false ; } </s>


"insertBranch must not be told to insert a fallthrough"

Insert branch code into the end of the specified MachineBasicBlock .


<s> enum rtx_code ix86_reverse_condition ( enum rtx_code code , enum machine_mode mode ) { return ( mode != CCFPmode && mode != CCFPUmode ? reverse_condition ( code ) : reverse_condition_maybe_unordered ( code ) ) ; } </s>


"invalid conversion from type %<bfloat16_t%>"

"invalid conversion to type %<bfloat16_t%>"

Return the diagnostic message string if conversion from FROMTYPE to TOTYPE is not allowed , NULL otherwise .


<s> static void rx_get_stack_layout ( unsigned int * lowest , unsigned int * highest , unsigned int * register_mask , unsigned int * frame_size , unsigned int * stack_size ) { unsigned int reg ; unsigned int low ; unsigned int high ; unsigned int fixed_reg = 0 ; unsigned int save_mask ; unsigned int pushed_mask ; unsigned int unneeded_pushes ; if ( is_naked_func ( NULL_TREE ) ) { * lowest = 0 ; * highest = 0 ; * register_mask = 0 ; * frame_size = 0 ; * stack_size = 0 ; return ; } for ( save_mask = high = low = 0 , reg = 1 ; reg < CC_REGNUM ; reg ++ ) { if ( ( df_regs_ever_live_p ( reg ) || ( call_used_regs [ reg ] && is_interrupt_func ( NULL_TREE ) && ! crtl -> is_leaf ) ) && ( ! call_used_regs [ reg ] || is_interrupt_func ( NULL_TREE ) || ( is_fast_interrupt_func ( NULL_TREE ) && ! IN_RANGE ( reg , 10 , 13 ) ) ) ) { if ( low == 0 ) low = reg ; high = reg ; save_mask |= 1 << reg ; } if ( low != 0 && fixed_reg == 0 && fixed_regs [ reg ] ) fixed_reg = reg ; } if ( MUST_SAVE_ACC_REGISTER && bit_count ( save_mask ) < 2 ) { save_mask |= ( 1 << 13 ) | ( 1 << 14 ) ; if ( low == 0 ) low = 13 ; if ( high == 0 || low == high ) high = low + 1 ; } pushed_mask = ( HOST_WIDE_INT_M1U << low ) & ~ ( HOST_WIDE_INT_M1U << ( high + 1 ) ) ; unneeded_pushes = ( pushed_mask & ( ~ save_mask ) ) & pushed_mask ; if ( ( fixed_reg && fixed_reg <= high ) || ( optimize_function_for_speed_p ( cfun ) && bit_count ( save_mask ) < bit_count ( unneeded_pushes ) ) ) { * lowest = 0 ; * highest = 0 ; * register_mask = save_mask ; } else { * lowest = low ; * highest = high ; * register_mask = 0 ; } * frame_size = rx_round_up ( get_frame_size ( ) , STACK_BOUNDARY / BITS_PER_UNIT ) ; if ( crtl -> args . size > 0 ) * frame_size += rx_round_up ( crtl -> args . size , STACK_BOUNDARY / BITS_PER_UNIT ) ; * stack_size = rx_round_up ( crtl -> outgoing_args_size , STACK_BOUNDARY / BITS_PER_UNIT ) ; } </s>

Returns either the lowest numbered and highest numbered registers that occupy the call-saved area of the stack frame , if the registers are stored as a contiguous block , or else a bitmask of the individual registers if they are stored piecemeal . Also computes the size of the frame and the size of the outgoing arguments block ( in bytes ) .


<s>
bool
SIFoldOperands
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
const
SIInstrInfo
*
TII
=
static_cast
<
const
SIInstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
const
SIRegisterInfo
&
TRI
=
TII
->
getRegisterInfo
(
)
;
for
(
MachineFunction
::
iterator
BI
=
MF
.
begin
(
)
,
BE
=
MF
.
end
(
)
;
BI
!=
BE
;
++
BI
)
{
MachineBasicBlock
&
MBB
=
*
BI
;
MachineBasicBlock
::
iterator
I
,
Next
;
for
(
I
=
MBB
.
begin
(
)
;
I
!=
MBB
.
end
(
)
;
I
=
Next
)
{
Next
=
std
::
next
(
I
)
;
MachineInstr
&
MI
=
*
I
;
if
(
!
isSafeToFold
(
MI
.
getOpcode
(
)
)
)
continue
;
unsigned
OpSize
=
TII
->
getOpSize
(
MI
,
1
)
;
MachineOperand
&
OpToFold
=
MI
.
getOperand
(
1
)
;
bool
FoldingImm
=
OpToFold
.
isImm
(
)
;
if
(
!
FoldingImm
&&
!
OpToFold
.
isReg
(
)
)
continue
;
if
(
FoldingImm
&&
!
TII
->
isInlineConstant
(
OpToFold
,
OpSize
)
&&
!
MRI
.
hasOneUse
(
MI
.
getOperand
(
0
)
.
getReg
(
)
)
)
continue
;
if
(
OpToFold
.
isReg
(
)
&&
(
!
TargetRegisterInfo
::
isVirtualRegister
(
OpToFold
.
getReg
(
)
)
||
OpToFold
.
getSubReg
(
)
)
)
continue
;
std
::
vector
<
FoldCandidate
>
FoldList
;
for
(
MachineRegisterInfo
::
use_iterator
Use
=
MRI
.
use_begin
(
MI
.
getOperand
(
0
)
.
getReg
(
)
)
,
E
=
MRI
.
use_end
(
)
;
Use
!=
E
;
++
Use
)
{
MachineInstr
*
UseMI
=
Use
->
getParent
(
)
;
foldOperand
(
OpToFold
,
UseMI
,
Use
.
getOperandNo
(
)
,
FoldList
,
TII
,
TRI
,
MRI
)
;
}
for
(
FoldCandidate
&
Fold
:
FoldList
)
{
if
(
updateOperand
(
Fold
,
TRI
)
)
{
if
(
!
Fold
.
isImm
(
)
)
{
assert
(
Fold
.
OpToFold
&&
Fold
.
OpToFold
->
isReg
(
)
)
;
Fold
.
OpToFold
->
setIsKill
(
false
)
;
}
DEBUG
(
dbgs
(
)
<<
"Folded source from "
<<
MI
<<
" into OpNo "
<<
Fold
.
UseOpNo
<<
" of "
<<
*
Fold
.
UseMI
<<
'\n'
)
;
}
}
}
}
return
false
;
}
</s>

AMDGPU
SI
SI
SI
SI
1
1
0
0
"Folded source from "
" into OpNo "
" of "


<s> bool X86TTIImpl :: isLegalMaskedLoad ( Type * DataTy , int Consecutive ) { int DataWidth = DataTy -> getPrimitiveSizeInBits ( ) ; if ( ( DataWidth < 32 ) || ( Consecutive == 0 ) ) return false ; if ( ST -> hasAVX512 ( ) || ST -> hasAVX2 ( ) ) return true ; return false ; } </s>

Return true if the target supports masked load .


"Should be loading %r15 and something else"


<s> static rtx_insn * frame_emit_add_imm ( rtx dst , rtx src , HOST_WIDE_INT imm , rtx scratch ) { rtx_insn * insn ; if ( satisfies_constraint_K ( GEN_INT ( imm ) ) ) { insn = emit_insn ( gen_addsi3 ( dst , src , GEN_INT ( imm ) ) ) ; } else { emit_insn ( gen_movsi ( scratch , gen_int_mode ( imm , SImode ) ) ) ; insn = emit_insn ( gen_addsi3 ( dst , src , scratch ) ) ; if ( REGNO ( src ) == REGNO ( scratch ) ) abort ( ) ; } return insn ; } </s>

This happens after reload , so we need to expand it .


<s> const AArch64Subtarget * AArch64TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < AArch64Subtarget > ( TargetTriple , CPU , FS , * this , isLittle ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesAll ( ) ; CallGraphSCCPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> int pa_shadd_constant_p ( int val ) { if ( val == 1 || val == 2 || val == 3 ) return 1 ; else return 0 ; } </s>

Return 1 if the given constant is 2 , 4 , or 8 . These are the valid constants for shadd instructions .


<s> machine_mode s390_dwarf_frame_reg_mode ( int regno ) { machine_mode save_mode = default_dwarf_frame_reg_mode ( regno ) ; if ( GENERAL_REGNO_P ( regno ) ) save_mode = Pmode ; if ( GET_MODE_SIZE ( save_mode ) > 8 ) save_mode = DImode ; return save_mode ; } </s>

Return the proper mode for REGNO being represented in the dwarf unwind table .


"C++ constructor pointer had zero size!"

"C++ constructor pointer was not a GlobalValue!"

Targets can override this to change how global constants that are part of a C++ static/global constructor list are emitted .


Output assembly language to define a symbol as COMMON from a DECL , possibly with visibility .


<s> static void rs6000_emit_stack_tie ( rtx fp , bool hard_frame_needed ) { rtvec p ; int i ; rtx regs [ 3 ] ; i = 0 ; regs [ i ++ ] = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; if ( hard_frame_needed ) regs [ i ++ ] = gen_rtx_REG ( Pmode , HARD_FRAME_POINTER_REGNUM ) ; if ( ! ( REGNO ( fp ) == STACK_POINTER_REGNUM || ( hard_frame_needed && REGNO ( fp ) == HARD_FRAME_POINTER_REGNUM ) ) ) regs [ i ++ ] = fp ; p = rtvec_alloc ( i ) ; while ( -- i >= 0 ) { rtx mem = gen_frame_mem ( BLKmode , regs [ i ] ) ; RTVEC_ELT ( p , i ) = gen_rtx_SET ( VOIDmode , mem , const0_rtx ) ; } emit_insn ( gen_stack_tie ( gen_rtx_PARALLEL ( VOIDmode , p ) ) ) ; } </s>

This ties together stack memory ( MEM with an alias set of rs6000_sr_alias_set ) and the change to the stack pointer .


<s> static void alpha_reorg ( void ) { if ( current_function_has_exception_handlers ( ) ) alpha_pad_function_end ( ) ; rtx_insn * insn = prev_active_insn ( get_last_insn ( ) ) ; if ( insn && NONJUMP_INSN_P ( insn ) ) { rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == PARALLEL ) { rtx vec = XVECEXP ( pat , 0 , 0 ) ; if ( GET_CODE ( vec ) == TRAP_IF && XEXP ( vec , 0 ) == const1_rtx ) emit_insn_after ( gen_unop ( ) , insn ) ; } } } </s>


<s> bool fixupNeedsRelaxation ( const MCFixup & , uint64_t , const MCRelaxableFragment * , const MCAsmLayout & ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


"No MachineFunctionInfo for this function!"


<s> static void apply_predication ( const function_instance & instance , tree return_type , vec < tree > & argument_types ) { if ( instance . pred != PRED_none ) { argument_types . quick_insert ( 0 , get_svbool_t ( ) ) ; if ( ( argument_types . length ( ) == 2 && instance . pred == PRED_m ) || instance . shape == shapes :: unary_convert_narrowt ) argument_types . quick_insert ( 0 , return_type ) ; } } </s>


"Unexpected combination of stack realignment and varsized objects"

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> bool X86TTIImpl :: isLegalNTStore ( Type * DataType , Align Alignment ) { unsigned DataSize = DL . getTypeStoreSize ( DataType ) ; if ( ST -> hasSSE4A ( ) && ( DataType -> isFloatTy ( ) || DataType -> isDoubleTy ( ) ) ) return true ; if ( Alignment < DataSize || DataSize < 4 || DataSize > 32 || ! isPowerOf2_32 ( DataSize ) ) return false ; if ( DataSize == 32 ) return ST -> hasAVX ( ) ; if ( DataSize == 16 ) return ST -> hasSSE1 ( ) ; return true ; } </s>

Return true if the target supports nontemporal store .


<s> bool AArch64TargetLowering :: useLoadStackGuardNode ( ) const { return true ; } </s>

If this function returns true , SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic : :stackprotector .


<s> static bool trapping_loads_p ( rtx_insn * insn , int np_reg , bool after_np_branch ) { rtx mem = SET_SRC ( single_set ( insn ) ) ; if ( ! after_np_branch ) np_reg = - 1 ; return ( ( np_reg == - 1 || ! harmless_null_pointer_p ( mem , np_reg ) ) && may_trap_p ( mem ) ) ; } </s>

Return nonzero if INSN contains any loads that may trap .


<s> size_t HSAILPrintfInfo :: getNumOperands ( ) { return mOperands . size ( ) ; } </s>

Return the number of declared MachineOperands for this MachineInstruction .


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , computeDataLayout ( Triple ( TT ) , is64bit ) , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < SparcELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this , is64bit ) { initAsmInfo ( ) ; } </s>


<s> bool ARMBaseInstrInfo :: PredicateInstruction ( MachineInstr * MI , ArrayRef < MachineOperand > Pred ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( isUncondBranchOpcode ( Opc ) ) { MI -> setDesc ( get ( getMatchingCondBranchOpcode ( Opc ) ) ) ; MachineInstrBuilder ( * MI -> getParent ( ) -> getParent ( ) , MI ) . addImm ( Pred [ 0 ] . getImm ( ) ) . addReg ( Pred [ 1 ] . getReg ( ) ) ; return true ; } int PIdx = MI -> findFirstPredOperandIdx ( ) ; if ( PIdx != - 1 ) { MachineOperand & PMO = MI -> getOperand ( PIdx ) ; PMO . setImm ( Pred [ 0 ] . getImm ( ) ) ; MI -> getOperand ( PIdx + 1 ) . setReg ( Pred [ 1 ] . getReg ( ) ) ; return true ; } return false ; } </s>

Convert the instruction into a predicated instruction .


<s> void GCNHazardRecognizer :: AdvanceCycle ( ) { if ( ! CurrCycleInstr ) return ; const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; unsigned NumWaitStates = TII -> getNumWaitStates ( * CurrCycleInstr ) ; EmittedInstrs . push_front ( CurrCycleInstr ) ; for ( unsigned i = 1 , e = std :: min ( NumWaitStates , getMaxLookAhead ( ) ) ; i < e ; ++ i ) { EmittedInstrs . push_front ( nullptr ) ; } EmittedInstrs . resize ( getMaxLookAhead ( ) ) ; CurrCycleInstr = nullptr ; } </s>

AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled can not issue in the current cycle , either because of latency or resource conflicts .


<s> bool MipsExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { STI = & static_cast < const MipsSubtarget & > ( MF . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= expandMBB ( * MFI ) ; if ( Modified ) MF . RenumberBlocks ( ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s>
bool
SystemZInstrInfo
::
PredicateInstruction
(
MachineInstr
&
MI
,
ArrayRef
<
MachineOperand
>
Pred
)
const
{
assert
(
Pred
.
size
(
)
==
2
&&
"Invalid condition"
)
;
unsigned
CCValid
=
Pred
[
0
]
.
getImm
(
)
;
unsigned
CCMask
=
Pred
[
1
]
.
getImm
(
)
;
assert
(
CCMask
>
0
&&
CCMask
<
15
&&
"Invalid predicate"
)
;
unsigned
Opcode
=
MI
.
getOpcode
(
)
;
if
(
STI
.
hasLoadStoreOnCond
(
)
)
{
if
(
unsigned
CondOpcode
=
getConditionalMove
(
Opcode
)
)
{
MI
.
setDesc
(
get
(
CondOpcode
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
}
if
(
Opcode
==
SystemZ
::
Trap
)
{
MI
.
setDesc
(
get
(
SystemZ
::
CondTrap
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
Return
)
{
MI
.
setDesc
(
get
(
SystemZ
::
CondReturn
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
CallJG
)
{
MachineOperand
FirstOp
=
MI
.
getOperand
(
0
)
;
const
uint32_t
*
RegMask
=
MI
.
getOperand
(
1
)
.
getRegMask
(
)
;
MI
.
RemoveOperand
(
1
)
;
MI
.
RemoveOperand
(
0
)
;
MI
.
setDesc
(
get
(
SystemZ
::
CallBRCL
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addOperand
(
FirstOp
)
.
addRegMask
(
RegMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
CallBR
)
{
const
uint32_t
*
RegMask
=
MI
.
getOperand
(
0
)
.
getRegMask
(
)
;
MI
.
RemoveOperand
(
0
)
;
MI
.
setDesc
(
get
(
SystemZ
::
CallBCR
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addRegMask
(
RegMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
return
false
;
}
</s>


<s> int X86FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const X86RegisterInfo * RegInfo = static_cast < const X86RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; FrameReg = ( RegInfo -> needsStackRealignment ( MF ) ) ? RegInfo -> getStackRegister ( ) : RegInfo -> getFrameRegister ( MF ) ; return getFrameIndexOffset ( MF , FI ) ; } </s>


<s> void addOptimizedRegAlloc ( ) override { } </s>

addOptimizedRegAlloc - Add passes related to register allocation .


<s> SMLoc getEndLoc ( ) const { return End ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> TargetLowering :: ConstraintWeight SystemZTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'a' : case 'd' : case 'r' : if ( CallOperandVal -> getType ( ) -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatingPointTy ( ) ) weight = CW_Register ; break ; case 'I' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isUInt < 8 > ( C -> getZExtValue ( ) ) ) weight = CW_Constant ; break ; case 'J' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isUInt < 12 > ( C -> getZExtValue ( ) ) ) weight = CW_Constant ; break ; case 'K' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isInt < 16 > ( C -> getSExtValue ( ) ) ) weight = CW_Constant ; break ; case 'L' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isInt < 20 > ( C -> getSExtValue ( ) ) ) weight = CW_Constant ; break ; case 'M' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( C -> getZExtValue ( ) == 0x7fffffff ) weight = CW_Constant ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


"Can only put epilog before 'jrp' instruction!"


"Constant Island pass failed to converge!"

"Branch Fix Up pass failed to converge!"


"Replacing store %d with permuted store\n"

Convert the non-permuting store INSN to a permuting one .


<s>
SUnit
*
ConvergingVLIWScheduler
::
pickNode
(
bool
&
IsTopNode
)
{
if
(
DAG
->
top
(
)
==
DAG
->
bottom
(
)
)
{
assert
(
Top
.
Available
.
empty
(
)
&&
Top
.
Pending
.
empty
(
)
&&
Bot
.
Available
.
empty
(
)
&&
Bot
.
Pending
.
empty
(
)
&&
"ReadyQ garbage"
)
;
return
nullptr
;
}
SUnit
*
SU
;
if
(
ForceTopDown
)
{
SU
=
Top
.
pickOnlyChoice
(
)
;
if
(
!
SU
)
{
SchedCandidate
TopCand
;
CandResult
TopResult
=
pickNodeFromQueue
(
Top
,
DAG
->
getTopRPTracker
(
)
,
TopCand
)
;
assert
(
TopResult
!=
NoCand
&&
"failed to find the first candidate"
)
;
(
void
)
TopResult
;
SU
=
TopCand
.
SU
;
}
IsTopNode
=
true
;
}
else
if
(
ForceBottomUp
)
{
SU
=
Bot
.
pickOnlyChoice
(
)
;
if
(
!
SU
)
{
SchedCandidate
BotCand
;
CandResult
BotResult
=
pickNodeFromQueue
(
Bot
,
DAG
->
getBotRPTracker
(
)
,
BotCand
)
;
assert
(
BotResult
!=
NoCand
&&
"failed to find the first candidate"
)
;
(
void
)
BotResult
;
SU
=
BotCand
.
SU
;
}
IsTopNode
=
false
;
}
else
{
SU
=
pickNodeBidrectional
(
IsTopNode
)
;
}
if
(
SU
->
isTopReady
(
)
)
Top
.
removeReady
(
SU
)
;
if
(
SU
->
isBottomReady
(
)
)
Bot
.
removeReady
(
SU
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"*** "
<<
(
IsTopNode
"Top"
:
"Bottom"
)
<<
" Scheduling instruction in cycle "
<<
(
IsTopNode
Top
.
CurrCycle
:
Bot
.
CurrCycle
)
<<
" ("
<<
reportPackets
(
)
<<
")\n"
;
SU
->
dump
(
DAG
)
)
;
return
SU
;
}
</s>

Pick the next node to schedule , or return NULL .

Hexagon
"ReadyQ garbage"
"failed to find the first candidate"
"failed to find the first candidate"
"*** "
"Top"
"Bottom"
" Scheduling instruction in cycle "
" ("
")\n"


<s>
static
void
nvptx_record_offload_symbol
(
tree
decl
)
{
switch
(
TREE_CODE
(
decl
)
)
{
case
VAR_DECL
:
fprintf
(
asm_out_file
,
"//:VAR_MAP \"%s\"\n"
,
IDENTIFIER_POINTER
(
DECL_ASSEMBLER_NAME
(
decl
)
)
)
;
break
;
case
FUNCTION_DECL
:
{
tree
attr
=
get_oacc_fn_attrib
(
decl
)
;
tree
dims
=
TREE_VALUE
(
attr
)
;
unsigned
ix
;
fprintf
(
asm_out_file
,
"//:FUNC_MAP \"%s\""
,
IDENTIFIER_POINTER
(
DECL_ASSEMBLER_NAME
(
decl
)
)
)
;
for
(
ix
=
0
;
ix
!=
GOMP_DIM_MAX
;
ix
++
,
dims
=
TREE_CHAIN
(
dims
)
)
{
int
size
=
TREE_INT_CST_LOW
(
TREE_VALUE
(
dims
)
)
;
gcc_assert
(
!
TREE_PURPOSE
(
dims
)
)
;
fprintf
(
asm_out_file
,
", %#x"
,
size
)
;
}
fprintf
(
asm_out_file
,
"\n"
)
;
}
break
;
default
:
gcc_unreachable
(
)
;
}
}
</s>

Record a symbol for mkoffload to enter into the mapping table .


"%<__builtin_mffsl%> not supported with %<-msoft-float%>"

Expand an expression EXP that calls a builtin without arguments .


<s>
unsigned
SparcMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
if
(
MO
.
isImm
(
)
)
return
MO
.
getImm
(
)
;
assert
(
MO
.
isExpr
(
)
)
;
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
if
(
const
SparcMCExpr
*
SExpr
=
dyn_cast
<
SparcMCExpr
>
(
Expr
)
)
{
MCFixupKind
Kind
=
(
MCFixupKind
)
SExpr
->
getFixupKind
(
)
;
Fixups
.
push_back
(
MCFixup
::
Create
(
0
,
Expr
,
Kind
)
)
;
return
0
;
}
int64_t
Res
;
if
(
Expr
->
EvaluateAsAbsolute
(
Res
)
)
return
Res
;
assert
(
0
&&
"Unhandled expression!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> void X86WinAllocaExpander :: lower ( MachineInstr * MI , Lowering L ) { DebugLoc DL = MI -> getDebugLoc ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: iterator I = * MI ; int64_t Amount = getWinAllocaAmount ( MI , MRI ) ; if ( Amount == 0 ) { MI -> eraseFromParent ( ) ; return ; } bool Is64Bit = STI -> is64Bit ( ) ; assert ( SlotSize == 4 || SlotSize == 8 ) ; unsigned RegA = ( SlotSize == 8 ) ? X86 :: RAX : X86 :: EAX ; switch ( L ) { case TouchAndSub : assert ( Amount >= SlotSize ) ; BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) ) . addReg ( RegA , RegState :: Undef ) ; Amount -= SlotSize ; if ( ! Amount ) break ; LLVM_FALLTHROUGH ; case Sub : assert ( Amount > 0 ) ; if ( Amount == SlotSize ) { BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) ) . addReg ( RegA , RegState :: Undef ) ; } else { BuildMI ( * MBB , I , DL , TII -> get ( getSubOpcode ( Is64Bit , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } break ; case Probe : if ( ! NoStackArgProbe ) { BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: COPY ) , RegA ) . addReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ; STI -> getFrameLowering ( ) -> emitStackProbe ( * MBB -> getParent ( ) , * MBB , MI , DL , false ) ; } else { BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? X86 :: SUB64rr : X86 :: SUB32rr ) , StackPtr ) . addReg ( StackPtr ) . addReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ; } break ; } unsigned AmountReg = MI -> getOperand ( 0 ) . getReg ( ) ; MI -> eraseFromParent ( ) ; for ( ; ; ) { if ( ! MRI -> use_empty ( AmountReg ) ) break ; MachineInstr * AmountDef = MRI -> getUniqueVRegDef ( AmountReg ) ; if ( ! AmountDef ) break ; if ( AmountDef -> isCopy ( ) && AmountDef -> getOperand ( 1 ) . isReg ( ) ) AmountReg = AmountDef -> getOperand ( 1 ) . isReg ( ) ; AmountDef -> eraseFromParent ( ) ; break ; } } </s>


<s> const uint16_t * KudeyarRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const TargetFrameLowering * TFI = MF -> getTarget ( ) . getFrameLowering ( ) ; const Function * F = MF -> getFunction ( ) ; if ( TFI -> hasFP ( * MF ) ) return ( F -> getCallingConv ( ) == CallingConv :: Kudeyar_INTR ? CSR_FP_INTR_SaveList : CSR_FP_SaveList ) ; else return ( F -> getCallingConv ( ) == CallingConv :: Kudeyar_INTR ? CSR_NoFP_INTR_SaveList : CSR_NoFP_SaveList ) ; } </s>


<s>
void
mmix_asm_output_internal_label
(
FILE
*
stream
,
const
char
*
name
)
{
assemble_name_raw
(
stream
,
name
)
;
fprintf
(
stream
,
"\tIS @\n"
)
;
}
</s>


<s> MachineInstrBuilder SIInstrInfo :: buildIndirectRead ( MachineBasicBlock * MBB , MachineBasicBlock :: iterator I , unsigned ValueReg , unsigned Address , unsigned OffsetReg ) const { const DebugLoc & DL = MBB -> findDebugLoc ( I ) ; unsigned IndirectBaseReg = AMDGPU :: VReg_32RegClass . getRegister ( getIndirectIndexBegin ( * MBB -> getParent ( ) ) ) ; return BuildMI ( * MBB , I , DL , get ( AMDGPU :: SI_INDIRECT_SRC ) ) . addOperand ( I -> getOperand ( 0 ) ) . addOperand ( I -> getOperand ( 1 ) ) . addReg ( IndirectBaseReg ) . addReg ( OffsetReg ) . addImm ( 0 ) ; } </s>

Build instruction ( s ) for an indirect register read .


<s> BitVector SIRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AMDGPU :: EXEC ) ; Reserved . set ( AMDGPU :: EXEC_LO ) ; Reserved . set ( AMDGPU :: EXEC_HI ) ; Reserved . set ( AMDGPU :: INDIRECT_BASE_ADDR ) ; Reserved . set ( AMDGPU :: FLAT_SCR ) ; Reserved . set ( AMDGPU :: FLAT_SCR_LO ) ; Reserved . set ( AMDGPU :: FLAT_SCR_HI ) ; Reserved . set ( AMDGPU :: VGPR255 ) ; Reserved . set ( AMDGPU :: VGPR254 ) ; if ( MF . getSubtarget < AMDGPUSubtarget > ( ) . hasSGPRInitBug ( ) ) { unsigned NumSGPRs = AMDGPU :: SGPR_32RegClass . getNumRegs ( ) ; unsigned Limit = AMDGPUSubtarget :: FIXED_SGPR_COUNT_FOR_INIT_BUG - 4 ; for ( unsigned i = Limit ; i < NumSGPRs ; ++ i ) { unsigned Reg = AMDGPU :: SGPR_32RegClass . getRegister ( i ) ; MCRegAliasIterator R = MCRegAliasIterator ( Reg , this , true ) ; for ( ; R . isValid ( ) ; ++ R ) Reserved . set ( * R ) ; } } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> unsigned SPScope :: getDepth ( ) const { return ( Priv -> Parent == NULL ) ? 0 : Priv -> Parent -> getDepth ( ) + 1 ; } </s>

The depth , in the dependence graph , for a node .


"Instruction should be in a basic block!"

"Generic instruction has unexpected implicit operands\n"

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s> virtual unsigned getReg ( ) const LLVM_OVERRIDE { return Reg . Num ; } </s>

Returns the register associated with this edge .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> const MCPhysReg * X86TargetLowering :: getScratchRegisters ( CallingConv :: ID ) const { static const MCPhysReg ScratchRegs [ ] = { X86 :: R11 , 0 } ; return ScratchRegs ; } </s>

Returns a 0 terminated array of registers that can be safely used as scratch registers .


<s> bool SHUXIFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) BuildMI ( MBB , MI , DL , TII . get ( SHUXI :: POP ) , CSI [ i ] . getReg ( ) ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> MCContext & getContext ( ) { return Ctx ; } </s>

Return the LLVMContext used by the analysis .


<s> static bool rs6000_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { if ( RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p ) { static int recurse = 0 ; if ( TARGET_RELOCATABLE && in_section != toc_section && ! recurse && ! CONST_SCALAR_INT_P ( x ) && CONSTANT_P ( x ) ) { char buf [ 256 ] ; recurse = 1 ; ASM_GENERATE_INTERNAL_LABEL ( buf , "LCP" , fixuplabelno ) ; fixuplabelno ++ ; ASM_OUTPUT_LABEL ( asm_out_file , buf ) ; fprintf ( asm_out_file , "\t.long\t(" ) ; output_addr_const ( asm_out_file , x ) ; fprintf ( asm_out_file , ")@fixup\n" ) ; fprintf ( asm_out_file , "\t.section\t\".fixup\",\"aw\"\n" ) ; ASM_OUTPUT_ALIGN ( asm_out_file , 2 ) ; fprintf ( asm_out_file , "\t.long\t" ) ; assemble_name ( asm_out_file , buf ) ; fprintf ( asm_out_file , "\n\t.previous\n" ) ; recurse = 0 ; return true ; } else if ( GET_CODE ( x ) == SYMBOL_REF && XSTR ( x , 0 ) [ 0 ] == '.' && DEFAULT_ABI == ABI_AIX ) { const char * name = XSTR ( x , 0 ) ; while ( * name == '.' ) name ++ ; fprintf ( asm_out_file , "\t.long\t%s\n" , name ) ; return true ; } } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . The powerpc version has to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP is defined . It also needs to handle DI-mode objects on 64-bit targets .


<s> static void tilepro_file_end ( void ) { if ( NEED_INDICATE_EXEC_STACK ) file_end_indicate_exec_stack ( ) ; } </s>


<s> bool HexagonGenInsert :: removeDeadCode ( MachineDomTreeNode * N ) { bool Changed = false ; typedef GraphTraits < MachineDomTreeNode * > GTN ; for ( auto I = GTN :: child_begin ( N ) , E = GTN :: child_end ( N ) ; I != E ; ++ I ) Changed |= removeDeadCode ( * I ) ; MachineBasicBlock * B = N -> getBlock ( ) ; std :: vector < MachineInstr * > Instrs ; for ( auto I = B -> rbegin ( ) , E = B -> rend ( ) ; I != E ; ++ I ) Instrs . push_back ( & * I ) ; for ( auto I = Instrs . begin ( ) , E = Instrs . end ( ) ; I != E ; ++ I ) { MachineInstr * MI = * I ; unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == TargetOpcode :: LIFETIME_START || Opc == TargetOpcode :: LIFETIME_END ) continue ; bool Store = false ; if ( MI -> isInlineAsm ( ) || ! MI -> isSafeToMove ( nullptr , Store ) ) continue ; bool AllDead = true ; SmallVector < unsigned , 2 > Regs ; for ( ConstMIOperands Op ( * MI ) ; Op . isValid ( ) ; ++ Op ) { if ( ! Op -> isReg ( ) || ! Op -> isDef ( ) ) continue ; unsigned R = Op -> getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) || ! MRI -> use_nodbg_empty ( R ) ) { AllDead = false ; break ; } Regs . push_back ( R ) ; } if ( ! AllDead ) continue ; B -> erase ( MI ) ; for ( unsigned I = 0 , N = Regs . size ( ) ; I != N ; ++ I ) MRI -> markUsesInDebugValueAsUndef ( Regs [ I ] ) ; Changed = true ; } return Changed ; } </s>

Remove all dead instructions between the I and E .


<s> FastISel * ARM :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) { if ( funcInfo . MF -> getSubtarget < ARMSubtarget > ( ) . useFastISel ( ) ) return new ARMFastISel ( funcInfo , libInfo ) ; return nullptr ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { TII = static_cast < const R600InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = & TII -> getRegisterInfo ( ) ; DEBUG ( MF . dump ( ) ; ) ; OrderedBlks . clear ( ) ; FuncRep = & MF ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; DEBUG ( dbgs ( ) << "LoopInfo:\n" ; PrintLoopinfo ( * MLI ) ; ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; DEBUG ( MDT -> print ( dbgs ( ) , ( const llvm :: Module * ) nullptr ) ; ) ; PDT = & getAnalysis < MachinePostDominatorTree > ( ) ; DEBUG ( PDT -> print ( dbgs ( ) ) ; ) ; prepare ( ) ; run ( ) ; DEBUG ( MF . dump ( ) ; ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> void AArch64AsmPrinter :: emitEndOfAsmFile ( Module & M ) { EmitHwasanMemaccessSymbols ( M ) ; const Triple & TT = TM . getTargetTriple ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { OutStreamer -> emitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } emitStackMaps ( SM ) ; FM . serializeToFaultMapSection ( ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> bool X86FastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { const Value * Ptr = LI -> getPointerOperand ( ) ; X86AddressMode AM ; if ( ! X86SelectAddress ( Ptr , AM ) ) return false ; const X86InstrInfo & XII = ( const X86InstrInfo & ) TII ; unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; unsigned Alignment = LI -> getAlignment ( ) ; if ( Alignment == 0 ) Alignment = DL . getABITypeAlignment ( LI -> getType ( ) ) ; SmallVector < MachineOperand , 8 > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , MI , OpNo , AddrOps , Size , Alignment , true ) ; if ( ! Result ) return false ; Result -> addMemOperand ( * FuncInfo . MF , createMachineMemOperandFor ( LI ) ) ; FuncInfo . MBB -> insert ( FuncInfo . InsertPt , Result ) ; MI -> eraseFromParent ( ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> bool X86DAGToDAGISel :: IsProfitableToFold ( SDValue N , SDNode * U , SDNode * Root ) const { if ( OptLevel == CodeGenOpt :: None ) return false ; if ( ! N . hasOneUse ( ) ) return false ; if ( N . getOpcode ( ) != ISD :: LOAD ) return true ; if ( U == Root ) { switch ( U -> getOpcode ( ) ) { default : break ; case X86ISD :: ADD : case X86ISD :: SUB : case X86ISD :: AND : case X86ISD :: XOR : case X86ISD :: OR : case ISD :: ADD : case ISD :: ADDCARRY : case ISD :: AND : case ISD :: OR : case ISD :: XOR : { SDValue Op1 = U -> getOperand ( 1 ) ; if ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( Op1 ) ) { if ( Imm -> getAPIntValue ( ) . isSignedIntN ( 8 ) ) return false ; if ( U -> getOpcode ( ) == ISD :: AND && Imm -> getAPIntValue ( ) . getBitWidth ( ) == 64 && Imm -> getAPIntValue ( ) . isIntN ( 32 ) ) return false ; } if ( Op1 . getOpcode ( ) == X86ISD :: Wrapper ) { SDValue Val = Op1 . getOperand ( 0 ) ; if ( Val . getOpcode ( ) == ISD :: TargetGlobalTLSAddress ) return false ; } } } } return true ; } </s>

IsProfitableToFold - Returns true if it 's profitable to fold the specific operand node N of U during instruction selection that starts at Root .


<s> SDValue PIC16TargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) { switch ( Op . getOpcode ( ) ) { case ISD :: ADD : case ISD :: ADDC : case ISD :: ADDE : return LowerADD ( Op , DAG ) ; case ISD :: SUB : case ISD :: SUBC : case ISD :: SUBE : return LowerSUB ( Op , DAG ) ; case ISD :: LOAD : return ExpandLoad ( Op . getNode ( ) , DAG ) ; case ISD :: STORE : return ExpandStore ( Op . getNode ( ) , DAG ) ; case ISD :: MUL : return LowerMUL ( Op , DAG ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return LowerShift ( Op , DAG ) ; case ISD :: OR : case ISD :: AND : case ISD :: XOR : return LowerBinOp ( Op , DAG ) ; case ISD :: BR_CC : return LowerBR_CC ( Op , DAG ) ; case ISD :: SELECT_CC : return LowerSELECT_CC ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

PIC16 PIC16 ISD::ADD ISD::ADDC ISD::ADDE ISD::SUB ISD::SUBC ISD::SUBE ISD::LOAD ISD::STORE ISD::MUL ISD::SHL ISD::SRA ISD::SRL ISD::OR ISD::AND ISD::XOR ISD::BR_CC ISD::SELECT_CC


<s> Optional < Instruction * > AArch64TTIImpl :: instCombineIntrinsic ( InstCombiner & IC , IntrinsicInst & II ) const { Intrinsic :: ID IID = II . getIntrinsicID ( ) ; switch ( IID ) { default : break ; case Intrinsic :: aarch64_sve_convert_from_svbool : return instCombineConvertFromSVBool ( IC , II ) ; case Intrinsic :: aarch64_sve_dup : return instCombineSVEDup ( IC , II ) ; case Intrinsic :: aarch64_sve_dup_x : return instCombineSVEDupX ( IC , II ) ; case Intrinsic :: aarch64_sve_cmpne : case Intrinsic :: aarch64_sve_cmpne_wide : return instCombineSVECmpNE ( IC , II ) ; case Intrinsic :: aarch64_sve_rdffr : return instCombineRDFFR ( IC , II ) ; case Intrinsic :: aarch64_sve_lasta : case Intrinsic :: aarch64_sve_lastb : return instCombineSVELast ( IC , II ) ; case Intrinsic :: aarch64_sve_cntd : return instCombineSVECntElts ( IC , II , 2 ) ; case Intrinsic :: aarch64_sve_cntw : return instCombineSVECntElts ( IC , II , 4 ) ; case Intrinsic :: aarch64_sve_cnth : return instCombineSVECntElts ( IC , II , 8 ) ; case Intrinsic :: aarch64_sve_cntb : return instCombineSVECntElts ( IC , II , 16 ) ; case Intrinsic :: aarch64_sve_ptest_any : case Intrinsic :: aarch64_sve_ptest_first : case Intrinsic :: aarch64_sve_ptest_last : return instCombineSVEPTest ( IC , II ) ; case Intrinsic :: aarch64_sve_mul : case Intrinsic :: aarch64_sve_fmul : return instCombineSVEVectorMul ( IC , II ) ; case Intrinsic :: aarch64_sve_fadd : return instCombineSVEVectorFAdd ( IC , II ) ; case Intrinsic :: aarch64_sve_fsub : return instCombineSVEVectorBinOp ( IC , II ) ; case Intrinsic :: aarch64_sve_tbl : return instCombineSVETBL ( IC , II ) ; case Intrinsic :: aarch64_sve_uunpkhi : case Intrinsic :: aarch64_sve_uunpklo : case Intrinsic :: aarch64_sve_sunpkhi : case Intrinsic :: aarch64_sve_sunpklo : return instCombineSVEUnpack ( IC , II ) ; case Intrinsic :: aarch64_sve_tuple_get : return instCombineSVETupleGet ( IC , II ) ; case Intrinsic :: aarch64_sve_zip1 : case Intrinsic :: aarch64_sve_zip2 : return instCombineSVEZip ( IC , II ) ; case Intrinsic :: aarch64_sve_ld1_gather_index : return instCombineLD1GatherIndex ( IC , II ) ; case Intrinsic :: aarch64_sve_st1_scatter_index : return instCombineST1ScatterIndex ( IC , II ) ; case Intrinsic :: aarch64_sve_ld1 : return instCombineSVELD1 ( IC , II , DL ) ; case Intrinsic :: aarch64_sve_st1 : return instCombineSVEST1 ( IC , II , DL ) ; case Intrinsic :: aarch64_sve_sdiv : return instCombineSVESDIV ( IC , II ) ; case Intrinsic :: aarch64_sve_sel : return instCombineSVESel ( IC , II ) ; } return None ; } </s>

Targets can implement their own combinations for target-specific intrinsics .


<s> static void mips_get_cprestore_base_and_offset ( rtx * base , HOST_WIDE_INT * offset , bool load_p ) { const struct mips_frame_info * frame ; frame = & cfun -> machine -> frame ; if ( frame_pointer_needed && ! ( TARGET_CPRESTORE_DIRECTIVE && ! load_p ) ) { * base = hard_frame_pointer_rtx ; * offset = frame -> args_size - frame -> hard_frame_pointer_offset ; } else { * base = stack_pointer_rtx ; * offset = frame -> args_size ; } } </s>

Fill * BASE and * OFFSET such that * BASE + * OFFSET refers to the cprestore slot . LOAD_P is true if the caller wants to load from the cprestore slot ; it is false if the caller wants to store to the slot .


<s> bool Mips16RegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , Register Reg ) const { DebugLoc DL ; const TargetInstrInfo & TII = * MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; TII . copyPhysReg ( MBB , I , DL , Mips :: T0 , Reg , true ) ; TII . copyPhysReg ( MBB , UseMI , DL , Reg , Mips :: T0 , true ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .


<s> bool PPCFrameLowering :: enableShrinkWrapping ( const MachineFunction & MF ) const { return ( MF . getSubtarget < PPCSubtarget > ( ) . isSVR4ABI ( ) && MF . getSubtarget < PPCSubtarget > ( ) . isPPC64 ( ) ) ; } </s>

Returns true if the target will correctly handle shrink wrapping .


<s> unsigned int arc_compute_function_type ( struct function * fun ) { tree attr , decl = fun -> decl ; unsigned int fn_type = fun -> machine -> fn_type ; if ( fn_type != ARC_FUNCTION_UNKNOWN ) return fn_type ; if ( lookup_attribute ( "naked" , DECL_ATTRIBUTES ( decl ) ) != NULL_TREE ) fn_type |= ARC_FUNCTION_NAKED ; else fn_type |= ARC_FUNCTION_NORMAL ; attr = lookup_attribute ( "interrupt" , DECL_ATTRIBUTES ( decl ) ) ; if ( attr != NULL_TREE ) { tree value , args = TREE_VALUE ( attr ) ; gcc_assert ( list_length ( args ) == 1 ) ; value = TREE_VALUE ( args ) ; gcc_assert ( TREE_CODE ( value ) == STRING_CST ) ; if ( ! strcmp ( TREE_STRING_POINTER ( value ) , "ilink1" ) || ! strcmp ( TREE_STRING_POINTER ( value ) , "ilink" ) ) fn_type |= ARC_FUNCTION_ILINK1 ; else if ( ! strcmp ( TREE_STRING_POINTER ( value ) , "ilink2" ) ) fn_type |= ARC_FUNCTION_ILINK2 ; else if ( ! strcmp ( TREE_STRING_POINTER ( value ) , "firq" ) ) fn_type |= ARC_FUNCTION_FIRQ ; else gcc_unreachable ( ) ; } return fun -> machine -> fn_type = fn_type ; } </s>

Type of function DECL . The result is cached . To reset the cache at the end of a function , call with DECL = NULL_TREE .


<s>
void
Mips16InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
MCRegister
DestReg
,
MCRegister
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
=
0
;
if
(
Mips
::
CPU16RegsRegClass
.
contains
(
DestReg
)
&&
Mips
::
GPR32RegClass
.
contains
(
SrcReg
)
)
Opc
=
Mips
::
MoveR3216
;
else
if
(
Mips
::
GPR32RegClass
.
contains
(
DestReg
)
&&
Mips
::
CPU16RegsRegClass
.
contains
(
SrcReg
)
)
Opc
=
Mips
::
Move32R16
;
else
if
(
(
SrcReg
==
Mips
::
HI0
)
&&
(
Mips
::
CPU16RegsRegClass
.
contains
(
DestReg
)
)
)
Opc
=
Mips
::
Mfhi16
,
SrcReg
=
0
;
else
if
(
(
SrcReg
==
Mips
::
LO0
)
&&
(
Mips
::
CPU16RegsRegClass
.
contains
(
DestReg
)
)
)
Opc
=
Mips
::
Mflo16
,
SrcReg
=
0
;
assert
(
Opc
&&
"Cannot copy registers"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
)
;
if
(
DestReg
)
MIB
.
addReg
(
DestReg
,
RegState
::
Define
)
;
if
(
SrcReg
)
MIB
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> static void gcn_goacc_reduction_fini ( gcall * call ) { gimple_stmt_iterator gsi = gsi_for_stmt ( call ) ; tree lhs = gimple_call_lhs ( call ) ; tree ref_to_res = gimple_call_arg ( call , 1 ) ; tree var = gimple_call_arg ( call , 2 ) ; int level = TREE_INT_CST_LOW ( gimple_call_arg ( call , 3 ) ) ; enum tree_code op = ( enum tree_code ) TREE_INT_CST_LOW ( gimple_call_arg ( call , 4 ) ) ; gimple_seq seq = NULL ; tree r = NULL_TREE ; ; push_gimplify_context ( true ) ; tree accum = NULL_TREE ; if ( level == GOMP_DIM_WORKER ) { tree var_type = TREE_TYPE ( var ) ; tree offset = gimple_call_arg ( call , 5 ) ; tree decl = gcn_goacc_get_worker_red_decl ( var_type , TREE_INT_CST_LOW ( offset ) ) ; accum = build_fold_addr_expr ( decl ) ; } else if ( integer_zerop ( ref_to_res ) ) r = var ; else accum = ref_to_res ; if ( accum ) { gsi_insert_seq_before ( & gsi , seq , GSI_SAME_STMT ) ; seq = NULL ; r = gcn_reduction_update ( gimple_location ( call ) , & gsi , accum , var , op ) ; } if ( lhs ) gimplify_assign ( lhs , r , & seq ) ; pop_gimplify_context ( NULL ) ; gsi_replace_with_seq ( & gsi , seq , true ) ; } </s>


<s> static bool classof ( const MCExpr * E ) { return E -> getKind ( ) == MCExpr :: Target ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> RegisterBankInfo :: InstructionMapping X86RegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { auto Opc = MI . getOpcode ( ) ; if ( ! isPreISelGenericOpcode ( Opc ) ) { InstructionMapping Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; } switch ( Opc ) { case TargetOpcode :: G_ADD : case TargetOpcode :: G_SUB : return getOperandsMapping ( MI , false ) ; break ; default : return InstructionMapping { } ; } return InstructionMapping { } ; } </s>

Get the mapping of the different operands of MI on the register bank .


<s> static rtx mips16_stub_function ( const char * name ) { rtx x ; x = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( name ) ) ; SYMBOL_REF_FLAGS ( x ) |= ( SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION ) ; return x ; } </s>

Return a SYMBOL_REF for a MIPS16 function called NAME .


<s> void bpf_expand_epilogue ( void ) { if ( TARGET_XBPF ) { rtx insn ; int regno ; int fp_offset = - cfun -> machine -> local_vars_size ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) { if ( ( df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) ) || ( cfun -> calls_alloca && regno == STACK_POINTER_REGNUM ) ) { rtx mem ; if ( ! IN_RANGE ( fp_offset , - 1 - 0x7fff , 0x7fff ) ) break ; else { mem = gen_frame_mem ( DImode , plus_constant ( DImode , hard_frame_pointer_rtx , fp_offset - 8 ) ) ; insn = emit_move_insn ( gen_rtx_REG ( DImode , regno ) , mem ) ; fp_offset -= 8 ; } } } } emit_jump_insn ( gen_exit ( ) ) ; } </s>

Expand to the instructions in a function epilogue . This function is called when expanding the 'epilogue ' pattern in bpf.md .


"Expect kernels to have non-local linkage"

getFunctionParamOptimizedAlign - since function arguments are passed via .param space , we may want to increase their alignment in a way that ensures that we can effectively vectorize their loads & stores .


<s> bool XCoreRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


"extended registers have no high halves"

"unsupported operand size for extended register"


<s> void X86AsmInstrumentation :: EmitInstruction ( MCStreamer & Out , const MCInst & Inst ) { Out . EmitInstruction ( Inst , * STI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void PTXFPRoundingModePass :: processInstruction ( MachineInstr & MI ) { if ( Instrs . count ( MI . getOpcode ( ) ) ) { const RndModeDesc & Desc = Instrs [ MI . getOpcode ( ) ] ; MachineOperand & Op = MI . getOperand ( Desc . first ) ; if ( Op . getImm ( ) == PTXRoundingMode :: RndDefault ) { Op . setImm ( Desc . second ) ; } } } </s>

Process a single instruction and collect debug info anchors .


<s> static rtx mips_legitimize_tls_address ( rtx loc ) { rtx dest , insn , v0 , v1 , tmp1 , tmp2 , eqv ; enum tls_model model ; v0 = gen_rtx_REG ( Pmode , GP_RETURN ) ; v1 = gen_rtx_REG ( Pmode , GP_RETURN + 1 ) ; model = SYMBOL_REF_TLS_MODEL ( loc ) ; switch ( model ) { case TLS_MODEL_GLOBAL_DYNAMIC : insn = mips_call_tls_get_addr ( loc , SYMBOL_TLSGD , v0 ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insn , dest , v0 , loc ) ; break ; case TLS_MODEL_LOCAL_DYNAMIC : insn = mips_call_tls_get_addr ( loc , SYMBOL_TLSLDM , v0 ) ; tmp1 = gen_reg_rtx ( Pmode ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , const0_rtx ) , UNSPEC_TLS_LDM ) ; emit_libcall_block ( insn , tmp1 , v0 , eqv ) ; tmp2 = mips_unspec_offset_high ( NULL , tmp1 , loc , SYMBOL_DTPREL ) ; dest = gen_rtx_LO_SUM ( Pmode , tmp2 , mips_unspec_address ( loc , SYMBOL_DTPREL ) ) ; break ; case TLS_MODEL_INITIAL_EXEC : tmp1 = gen_reg_rtx ( Pmode ) ; tmp2 = mips_unspec_address ( loc , SYMBOL_GOTTPREL ) ; if ( Pmode == DImode ) { emit_insn ( gen_tls_get_tp_di ( v1 ) ) ; emit_insn ( gen_load_gotdi ( tmp1 , pic_offset_table_rtx , tmp2 ) ) ; } else { emit_insn ( gen_tls_get_tp_si ( v1 ) ) ; emit_insn ( gen_load_gotsi ( tmp1 , pic_offset_table_rtx , tmp2 ) ) ; } dest = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_add3_insn ( dest , tmp1 , v1 ) ) ; break ; case TLS_MODEL_LOCAL_EXEC : if ( Pmode == DImode ) emit_insn ( gen_tls_get_tp_di ( v1 ) ) ; else emit_insn ( gen_tls_get_tp_si ( v1 ) ) ; tmp1 = mips_unspec_offset_high ( NULL , v1 , loc , SYMBOL_TPREL ) ; dest = gen_rtx_LO_SUM ( Pmode , tmp1 , mips_unspec_address ( loc , SYMBOL_TPREL ) ) ; break ; default : gcc_unreachable ( ) ; } return dest ; } </s>

Generate the code to access LOC , a thread local SYMBOL_REF . The return value will be a valid address and move_operand ( either a REG or a LO_SUM ) .


<s> bool AMDGPUAlwaysInline :: runOnModule ( Module & M ) { std :: vector < Function * > FuncsToClone ; for ( Module :: iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) { Function & F = * I ; if ( ! F . hasLocalLinkage ( ) && ! F . isDeclaration ( ) && ! F . use_empty ( ) ) FuncsToClone . push_back ( & F ) ; } for ( Function * F : FuncsToClone ) { ValueToValueMapTy VMap ; Function * NewFunc = CloneFunction ( F , VMap , false ) ; NewFunc -> setLinkage ( GlobalValue :: InternalLinkage ) ; F -> getParent ( ) -> getFunctionList ( ) . push_back ( NewFunc ) ; F -> replaceAllUsesWith ( NewFunc ) ; } for ( Module :: iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) { Function & F = * I ; if ( F . hasLocalLinkage ( ) ) { F . addFnAttr ( Attribute :: AlwaysInline ) ; } } return false ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> static void nios2_setup_incoming_varargs ( cumulative_args_t cum_v , machine_mode mode , tree type , int * pretend_size , int second_time ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; CUMULATIVE_ARGS local_cum ; cumulative_args_t local_cum_v = pack_cumulative_args ( & local_cum ) ; int regs_to_push ; int pret_size ; local_cum = * cum ; nios2_function_arg_advance ( local_cum_v , mode , type , 1 ) ; regs_to_push = NUM_ARG_REGS - local_cum . regs_used ; if ( ! second_time && regs_to_push > 0 ) { rtx ptr = virtual_incoming_args_rtx ; rtx mem = gen_rtx_MEM ( BLKmode , ptr ) ; emit_insn ( gen_blockage ( ) ) ; move_block_from_reg ( local_cum . regs_used + FIRST_ARG_REGNO , mem , regs_to_push ) ; emit_insn ( gen_blockage ( ) ) ; } pret_size = regs_to_push * UNITS_PER_WORD ; if ( pret_size ) * pretend_size = pret_size ; } </s>

TODO : It may be possible to eliminate the copyback and implement own va_arg type .


<s> bool MipsTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , getTargetMachine ( ) , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_MipsO32 ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


"getBranchTarget26OpValue expects only expressions or immediates"

getBranchTarget26OpValue - Return binary encoding of the branch target operand .


<s> static int is_dispatch_slot_restricted ( rtx insn ) { enum attr_type type ; if ( ! rs6000_sched_groups ) return 0 ; if ( ! insn || insn == NULL_RTX || GET_CODE ( insn ) == NOTE || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return 0 ; type = get_attr_type ( insn ) ; switch ( type ) { case TYPE_MFCR : case TYPE_MFCRF : case TYPE_MTCR : case TYPE_DELAYED_CR : case TYPE_CR_LOGICAL : case TYPE_MTJMPR : case TYPE_MFJMPR : return 1 ; case TYPE_IDIV : case TYPE_LDIV : return 2 ; case TYPE_LOAD_L : case TYPE_STORE_C : case TYPE_ISYNC : case TYPE_SYNC : return 4 ; default : if ( rs6000_cpu == PROCESSOR_POWER5 && is_cracked_insn ( insn ) ) return 2 ; return 0 ; } } </s>

The function returns a nonzero value if INSN can be scheduled only as the first insn in a dispatch group ( `` dispatch-slot restricted '' ) . In this case , the returned value indicates how many dispatch slots the insn occupies ( at the beginning of the group ) . Return 0 otherwise .


<s> void sparc_split_reg_reg ( rtx dest , rtx src , machine_mode mode ) { rtx dest1 = gen_highpart ( mode , dest ) ; rtx dest2 = gen_lowpart ( mode , dest ) ; rtx src1 = gen_highpart ( mode , src ) ; rtx src2 = gen_lowpart ( mode , src ) ; if ( reg_overlap_mentioned_p ( dest1 , src2 ) ) { emit_move_insn_1 ( dest2 , src2 ) ; emit_move_insn_1 ( dest1 , src1 ) ; } else { emit_move_insn_1 ( dest1 , src1 ) ; emit_move_insn_1 ( dest2 , src2 ) ; } } </s>

Split a REG < -- > REG move into a pair of moves in MODE .


<s>
bool
MSP430AsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
if
(
Name
.
endswith_insensitive
(
".w"
)
)
Name
=
Name
.
drop_back
(
2
)
;
if
(
!
parseJccInstruction
(
Info
,
Name
,
NameLoc
,
Operands
)
)
return
false
;
if
(
Name
.
startswith_insensitive
(
"rpt"
)
)
return
parseRptDirective
(
Info
,
Name
,
NameLoc
,
Operands
)
;
Operands
.
push_back
(
MSP430Operand
::
CreateToken
(
Name
,
NameLoc
)
)
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
return
false
;
if
(
ParseOperand
(
Operands
)
)
return
true
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
getLexer
(
)
.
Lex
(
)
;
if
(
ParseOperand
(
Operands
)
)
return
true
;
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
getParser
(
)
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
getParser
(
)
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .


<s> static bool hasIndex ( const MachineInstr & MI , const MCRegisterInfo & RI ) { for ( const MachineOperand & Op : MI . explicit_operands ( ) ) if ( isIndex ( Op , RI ) ) { return true ; } return false ; } </s>

Returns true if the given machine instr is mapped to an index , otherwise returns false .


<s> bool X86TargetLowering :: isZExtFree ( const Type * Ty1 , const Type * Ty2 ) const { return Ty1 == Type :: getInt32Ty ( Ty1 -> getContext ( ) ) && Ty2 == Type :: getInt64Ty ( Ty1 -> getContext ( ) ) && Subtarget -> is64Bit ( ) ; } </s>

Return true if zero-extending the specific node Val to type VT2 is free ( either because it 's implicitly zero-extended such as ARM ldrb / ldrh or because it 's folded such as X86 zero-extending loads ) .


<s>
MCSymbol
*
ARMMCInstLower
::
GetExternalSymbolSymbol
(
const
MachineOperand
&
MO
)
const
{
switch
(
MO
.
getTargetFlags
(
)
)
{
default
:
assert
(
0
&&
"Unknown target flag on GV operand"
)
;
case
0
:
break
;
}
return
Printer
.
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
;
}
</s>

Return the MCSymbol for the specified ExternalSymbol .


<s> const AMDGPUTargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


<s> bool HexagonCallFrameInformation :: runOnMachineFunction ( MachineFunction & MF ) { auto & HFI = * MF . getSubtarget < HexagonSubtarget > ( ) . getFrameLowering ( ) ; bool NeedCFI = MF . needsFrameMoves ( ) ; if ( ! NeedCFI ) return false ; HFI . insertCFIInstructions ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static bool avr_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { if ( size == POINTER_SIZE / BITS_PER_UNIT && aligned_p && ( ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( x ) ) || GET_CODE ( x ) == LABEL_REF ) ) { fputs ( "\t.word\tpm(" , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; fputs ( ")\n" , asm_out_file ) ; return true ; } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . The AVR version needs special handling for references to certain labels .


<s> void BPFFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool convertSetCCLogicToBitwiseLogic ( EVT VT ) const override { return VT . isScalarInteger ( ) ; } </s>

Use bitwise logic to make pairs of compares more efficient .


<s> bool PPCSubtarget :: enableMachinePipeliner ( ) const { return getSchedModel ( ) . hasInstrSchedModel ( ) && EnableMachinePipeliner ; } </s>

True if the subtarget should run MachinePipeliner .


<s> const uint32_t * RISCVRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { auto & Subtarget = MF . getSubtarget < RISCVSubtarget > ( ) ; if ( MF . getFunction ( ) . hasFnAttribute ( "interrupt" ) ) { if ( Subtarget . hasStdExtD ( ) ) return CSR_XLEN_F64_Interrupt_RegMask ; if ( Subtarget . hasStdExtF ( ) ) return CSR_XLEN_F32_Interrupt_RegMask ; return CSR_Interrupt_RegMask ; } return CSR_ILP32_LP64_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static tree ix86_build_builtin_va_list ( void ) { if ( TARGET_64BIT ) { tree sysv_va_list , ms_va_list ; sysv_va_list = ix86_build_builtin_va_list_64 ( ) ; sysv_va_list_type_node = build_variant_type_copy ( sysv_va_list ) ; ms_va_list = build_pointer_type ( char_type_node ) ; ms_va_list_type_node = build_variant_type_copy ( ms_va_list ) ; return ( ix86_abi == MS_ABI ) ? ms_va_list : sysv_va_list ; } else { return build_pointer_type ( char_type_node ) ; } } </s>


<s> static machine_mode ix86_secondary_memory_needed_mode ( machine_mode mode ) { if ( GET_MODE_BITSIZE ( mode ) < 32 && INTEGRAL_MODE_P ( mode ) ) return mode_for_size ( 32 , GET_MODE_CLASS ( mode ) , 0 ) . require ( ) ; return mode ; } </s>

Implement TARGET_SECONDARY_MEMORY_NEEDED_MODE . get_secondary_mem widens integral modes to BITS_PER_WORD . There is no need to emit full 64 bit move on 64 bit targets for integral modes that can be moved using 32 bit move .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s>
static
avr_map_op_t
avr_map_decompose
(
unsigned
int
f
,
const
avr_map_op_t
*
g
,
bool
val_const_p
)
{
bool
val_used_p
=
0
!=
avr_map_metric
(
f
,
MAP_MASK_PREIMAGE_F
)
;
avr_map_op_t
f_ginv
=
*
g
;
unsigned
int
ginv
=
g
->
ginv
;
f_ginv
.
cost
=
1
;
for
(
int
i
=
7
;
i
>=
0
;
i
)
{
int
x
=
avr_map
(
f
,
i
)
;
if
(
x
<=
7
)
{
x
=
avr_map
(
ginv
,
x
)
;
if
(
x
>
7
)
return
f_ginv
;
}
f_ginv
.
map
=
(
f_ginv
.
map
<<
4
)
+
x
;
}
if
(
0
==
avr_map_metric
(
f_ginv
.
map
,
MAP_NONFIXED_0_7
)
)
{
f_ginv
.
cost
=
2
+
(
val_used_p
&&
!
val_const_p
)
;
}
else
{
rtx
xop
[
4
]
;
xop
[
0
]
=
all_regs_rtx
[
24
]
;
xop
[
1
]
=
gen_int_mode
(
f_ginv
.
map
,
SImode
)
;
xop
[
2
]
=
all_regs_rtx
[
25
]
;
xop
[
3
]
=
val_used_p
xop
[
0
]
:
const0_rtx
;
avr_out_insert_bits
(
xop
,
&
f_ginv
.
cost
)
;
f_ginv
.
cost
+=
val_const_p
&&
val_used_p
1
:
0
;
}
f_ginv
.
cost
+=
g
->
cost
;
if
(
avr_log
.
builtin
)
avr_edump
(
" %s%d=%d"
,
g
->
str
,
g
->
arg
,
f_ginv
.
cost
)
;
return
f_ginv
;
}
</s>

Try to decompose F as F = ( F o G^-1 ) o G as described above . The result is a struct representing F o G^-1 and G. If result.cost < 0 then such a decomposition does not exist .


<s>
void
PPCTargetLowering
::
LowerAsmOperandForConstraint
(
SDValue
Op
,
std
::
string
&
Constraint
,
std
::
vector
<
SDValue
>
&
Ops
,
SelectionDAG
&
DAG
)
const
{
SDValue
Result
(
0
,
0
)
;
if
(
Constraint
.
length
(
)
>
1
)
return
;
char
Letter
=
Constraint
[
0
]
;
switch
(
Letter
)
{
default
:
break
;
case
'I'
:
case
'J'
:
case
'K'
:
case
'L'
:
case
'M'
:
case
'N'
:
case
'O'
:
case
'P'
:
{
ConstantSDNode
*
CST
=
dyn_cast
<
ConstantSDNode
>
(
Op
)
;
if
(
!
CST
)
return
;
unsigned
Value
=
CST
->
getZExtValue
(
)
;
switch
(
Letter
)
{
default
:
llvm_unreachable
(
"Unknown constraint letter!"
)
;
case
'I'
:
if
(
(
short
)
Value
==
(
int
)
Value
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'J'
:
case
'L'
:
if
(
(
short
)
Value
==
0
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'K'
:
if
(
(
Value
>>
16
)
==
0
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'M'
:
if
(
Value
>
31
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'N'
:
if
(
(
int
)
Value
>
0
&&
isPowerOf2_32
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'O'
:
if
(
Value
==
0
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'P'
:
if
(
(
short
)
Value
==
(
int
)
Value
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
}
break
;
}
}
if
(
Result
.
getNode
(
)
)
{
Ops
.
push_back
(
Result
)
;
return
;
}
TargetLowering
::
LowerAsmOperandForConstraint
(
Op
,
Constraint
,
Ops
,
DAG
)
;
}
</s>

Lower the specified operand into the Ops vector .


<s> void ARMHazardRecognizer :: Reset ( ) { LastMI = 0 ; FpMLxStalls = 0 ; ITBlockSize = 0 ; ScoreboardHazardRecognizer :: Reset ( ) ; } </s>


<s> bool isVirtualSection ( const MCSection & Section ) const { const MCSectionMachO & SMO = static_cast < const MCSectionMachO & > ( Section ) ; return ( SMO . getType ( ) == MCSectionMachO :: S_ZEROFILL || SMO . getType ( ) == MCSectionMachO :: S_GB_ZEROFILL ) ; } </s>

Check whether this section is `` virtual '' , that is has no actual object file contents .


<s> TargetLowering :: ConstraintWeight PPCTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'b' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; case 'd' : if ( type -> isDoubleTy ( ) ) weight = CW_Register ; break ; case 'v' : if ( type -> isVectorTy ( ) ) weight = CW_Register ; break ; case 'y' : weight = CW_Register ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s>
void
Thumb1InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
(
PseudoSourceValue
::
getFixedStack
(
FI
)
)
,
MachineMemOperand
::
MOStore
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tSTRspi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .

ARM
ARM::tGPRRegisterClass
ARM
"Unknown regclass!"
ARM::tGPRRegisterClass
ARM
ARM::tSTRspi
0


<s> bool ARMCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { auto & TLI = * getTLI < ARMTargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb ( ) ) return false ; if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; auto DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasByValOrInAllocaAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , 8 > ArgInfos ; SmallVector < unsigned , 4 > SplitRegs ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; SplitRegs . clear ( ) ; splitToValueTypes ( AInfo , ArgInfos , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { SplitRegs . push_back ( Reg ) ; } ) ; if ( ! SplitRegs . empty ( ) ) MIRBuilder . buildMerge ( VRegs [ Idx ] , SplitRegs ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


"MSP430 DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s>
static
unsigned
getInstSizeInBytes
(
const
MachineInstr
&
MI
,
const
SystemZInstrInfo
*
TII
)
{
unsigned
Size
=
TII
->
getInstSizeInBytes
(
MI
)
;
assert
(
(
Size
||
MI
.
isDebugOrPseudoInstr
(
)
||
MI
.
isPosition
(
)
||
MI
.
isKill
(
)
||
MI
.
isImplicitDef
(
)
||
MI
.
getOpcode
(
)
==
SystemZ
::
MemBarrier
||
MI
.
isInlineAsm
(
)
||
MI
.
getOpcode
(
)
==
SystemZ
::
STACKMAP
||
MI
.
getOpcode
(
)
==
SystemZ
::
PATCHPOINT
)
&&
"Missing size value for instruction."
)
;
return
Size
;
}
</s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .

SystemZ
SystemZ
SystemZ::MemBarrier
SystemZ::STACKMAP
SystemZ::PATCHPOINT
"Missing size value for instruction."


"Can only put epilog before 'retl' instruction!"


<s>
const
char
*
rs6000_insn_for_and_mask
(
machine_mode
mode
,
rtx
*
operands
,
bool
dot
)
{
int
nb
,
ne
;
if
(
!
rs6000_is_valid_mask
(
operands
[
2
]
,
&
nb
,
&
ne
,
mode
)
)
gcc_unreachable
(
)
;
if
(
mode
==
DImode
&&
ne
==
0
)
{
operands
[
3
]
=
GEN_INT
(
63
nb
)
;
if
(
dot
)
return
"rldicl. %0,%1,0,%3"
;
return
"rldicl %0,%1,0,%3"
;
}
if
(
mode
==
DImode
&&
nb
==
63
)
{
operands
[
3
]
=
GEN_INT
(
63
ne
)
;
if
(
dot
)
return
"rldicr. %0,%1,0,%3"
;
return
"rldicr %0,%1,0,%3"
;
}
if
(
nb
<
32
&&
ne
<
32
)
{
operands
[
3
]
=
GEN_INT
(
31
nb
)
;
operands
[
4
]
=
GEN_INT
(
31
ne
)
;
if
(
dot
)
return
"rlwinm. %0,%1,0,%3,%4"
;
return
"rlwinm %0,%1,0,%3,%4"
;
}
gcc_unreachable
(
)
;
}
</s>

Return the instruction template for an AND with mask in mode MODE , with operands OPERANDS . If DOT is true , make it a record-form instruction .


<s>
void
m32r_init
(
)
{
init_reg_tables
(
)
;
memset
(
m32r_punct_chars
,
0
,
sizeof
(
m32r_punct_chars
)
)
;
m32r_punct_chars
[
'#'
]
=
1
;
m32r_punct_chars
[
'@'
]
=
1
;
if
(
!
g_switch_set
)
g_switch_value
=
SDATA_DEFAULT_SIZE
;
if
(
strcmp
(
m32r_model_string
,
"small"
)
==
0
)
m32r_model
=
M32R_MODEL_SMALL
;
else
if
(
strcmp
(
m32r_model_string
,
"medium"
)
==
0
)
m32r_model
=
M32R_MODEL_MEDIUM
;
else
if
(
strcmp
(
m32r_model_string
,
"large"
)
==
0
)
m32r_model
=
M32R_MODEL_LARGE
;
else
error
(
"bad value (%s) for -mmodel switch"
,
m32r_model_string
)
;
if
(
strcmp
(
m32r_sdata_string
,
"none"
)
==
0
)
m32r_sdata
=
M32R_SDATA_NONE
;
else
if
(
strcmp
(
m32r_sdata_string
,
"sdata"
)
==
0
)
m32r_sdata
=
M32R_SDATA_SDATA
;
else
if
(
strcmp
(
m32r_sdata_string
,
"use"
)
==
0
)
m32r_sdata
=
M32R_SDATA_USE
;
else
error
(
"bad value (%s) for -msdata switch"
,
m32r_sdata_string
)
;
}
</s>

Called by OVERRIDE_OPTIONS to initialize various things .


<s>
unsigned
getReg
(
)
const
{
assert
(
Kind
==
Register
&&
"Invalid access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s>
const
char
*
aarch64_output_probe_stack_range
(
rtx
reg1
,
rtx
reg2
)
{
static
int
labelno
=
0
;
char
loop_lab
[
32
]
;
rtx
xops
[
2
]
;
ASM_GENERATE_INTERNAL_LABEL
(
loop_lab
,
"LPSRL"
,
labelno
++
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
loop_lab
)
;
HOST_WIDE_INT
stack_clash_probe_interval
=
1
<<
PARAM_VALUE
(
PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE
)
;
xops
[
0
]
=
reg1
;
HOST_WIDE_INT
interval
;
if
(
flag_stack_clash_protection
)
interval
=
stack_clash_probe_interval
;
else
interval
=
PROBE_INTERVAL
;
gcc_assert
(
aarch64_uimm12_shift
(
interval
)
)
;
xops
[
1
]
=
GEN_INT
(
interval
)
;
output_asm_insn
(
"sub\t%0, %0, %1"
,
xops
)
;
if
(
flag_stack_clash_protection
)
xops
[
1
]
=
GEN_INT
(
STACK_CLASH_CALLER_GUARD
)
;
else
xops
[
1
]
=
CONST0_RTX
(
GET_MODE
(
xops
[
1
]
)
)
;
output_asm_insn
(
"str\txzr, [%0, %1]"
,
xops
)
;
xops
[
1
]
=
reg2
;
output_asm_insn
(
"cmp\t%0, %1"
,
xops
)
;
fputs
(
"\tb.ne\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
loop_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
return
""
;
}
</s>

Probe a range of stack addresses from REG1 to REG2 inclusive . These are absolute addresses .


<s> void FixupLEAPass :: processInstruction ( MachineBasicBlock :: iterator & I , MachineFunction :: iterator MFI ) { MachineInstr * MI = I ; int opcode = MI -> getOpcode ( ) ; const MCInstrDesc & Desc = MI -> getDesc ( ) ; int AddrOffset = X86II :: getMemoryOperandNo ( Desc . TSFlags , opcode ) ; if ( AddrOffset >= 0 ) { AddrOffset += X86II :: getOperandBias ( Desc ) ; MachineOperand & p = MI -> getOperand ( AddrOffset + X86 :: AddrBaseReg ) ; if ( p . isReg ( ) && p . getReg ( ) != X86 :: ESP ) { seekLEAFixup ( p , I , MFI ) ; } MachineOperand & q = MI -> getOperand ( AddrOffset + X86 :: AddrIndexReg ) ; if ( q . isReg ( ) && q . getReg ( ) != X86 :: ESP ) { seekLEAFixup ( q , I , MFI ) ; } } } </s>

Process a single instruction and collect debug info anchors .


<s> int64_t getFrameAdjustment ( const MachineInstr & I ) const { assert ( isFrameInstr ( I ) ) ; if ( isFrameSetup ( I ) ) return I . getOperand ( 2 ) . getImm ( ) ; return I . getOperand ( 1 ) . getImm ( ) ; } </s>

Returns the stack pointer adjustment that happens inside the frame setup .. destroy sequence ( e.g .


<s> int get_dest_uid ( rtx label , int max_uid ) { rtx dest = next_real_insn ( label ) ; int dest_uid ; if ( ! dest ) return 0 ; dest_uid = INSN_UID ( dest ) ; while ( dest_uid >= max_uid ) { dest = NEXT_INSN ( dest ) ; dest_uid = INSN_UID ( dest ) ; } if ( GET_CODE ( dest ) == JUMP_INSN && GET_CODE ( PATTERN ( dest ) ) == RETURN ) return 0 ; return dest_uid ; } </s>

Return the UID of the insn that follows the specified label .


<s> const CallLowering * getCallLowering ( ) const override { return CallLoweringInfo . get ( ) ; } </s>


<s> bool LanaiAsmPrinter :: isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { const MachineBasicBlock * Pred = * MBB -> pred_begin ( ) ; if ( const BasicBlock * B = Pred -> getBasicBlock ( ) ) if ( isa < SwitchInst > ( B -> getTerminator ( ) ) ) return false ; if ( ! AsmPrinter :: isBlockOnlyReachableByFallthrough ( MBB ) ) return false ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> isTerminator ( ) ) { } return ! I -> isBarrier ( ) ; } </s>

isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


<s> TargetLoweringBase :: AtomicRMWExpansionKind ARMTargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return ( Size <= ( Subtarget -> isMClass ( ) ? 32U : 64U ) ) ? AtomicRMWExpansionKind :: LLSC : AtomicRMWExpansionKind :: None ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> std :: unique_ptr < MCObjectWriter > WebAssemblyAsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { return createWebAssemblyWasmObjectWriter ( OS , Is64Bit ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s>
bool
runOnMachineFunction
(
MachineFunction
&
MF
)
override
{
const
X86TargetMachine
*
TM
=
static_cast
<
const
X86TargetMachine
*
>
(
&
MF
.
getTarget
(
)
)
;
const
X86Subtarget
&
STI
=
MF
.
getSubtarget
<
X86Subtarget
>
(
)
;
if
(
STI
.
is64Bit
(
)
&&
(
TM
->
getCodeModel
(
)
==
CodeModel
::
Small
||
TM
->
getCodeModel
(
)
==
CodeModel
::
Kernel
)
)
return
false
;
if
(
!
TM
->
isPositionIndependent
(
)
)
return
false
;
X86MachineFunctionInfo
*
X86FI
=
MF
.
getInfo
<
X86MachineFunctionInfo
>
(
)
;
unsigned
GlobalBaseReg
=
X86FI
->
getGlobalBaseReg
(
)
;
if
(
GlobalBaseReg
==
0
)
return
false
;
MachineBasicBlock
&
FirstMBB
=
MF
.
front
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
FirstMBB
.
begin
(
)
;
DebugLoc
DL
=
FirstMBB
.
findDebugLoc
(
MBBI
)
;
MachineRegisterInfo
&
RegInfo
=
MF
.
getRegInfo
(
)
;
const
X86InstrInfo
*
TII
=
STI
.
getInstrInfo
(
)
;
unsigned
PC
;
if
(
STI
.
isPICStyleGOT
(
)
)
PC
=
RegInfo
.
createVirtualRegister
(
&
X86
::
GR32RegClass
)
;
else
PC
=
GlobalBaseReg
;
if
(
STI
.
is64Bit
(
)
)
{
if
(
TM
->
getCodeModel
(
)
==
CodeModel
::
Medium
)
{
BuildMI
(
FirstMBB
,
MBBI
,
DL
,
TII
->
get
(
X86
::
LEA64r
)
,
PC
)
.
addReg
(
X86
::
RIP
)
.
addImm
(
0
)
.
addReg
(
0
)
.
addExternalSymbol
(
"_GLOBAL_OFFSET_TABLE_"
)
.
addReg
(
0
)
;
}
else
if
(
TM
->
getCodeModel
(
)
==
CodeModel
::
Large
)
{
unsigned
Scratch
=
RegInfo
.
createVirtualRegister
(
&
X86
::
GR64RegClass
)
;
BuildMI
(
FirstMBB
,
MBBI
,
DL
,
TII
->
get
(
X86
::
MOVGOT64r
)
,
PC
)
.
addReg
(
Scratch
,
RegState
::
Undef
|
RegState
::
Define
)
.
addExternalSymbol
(
"_GLOBAL_OFFSET_TABLE_"
)
;
}
else
{
llvm_unreachable
(
"unexpected code model"
)
;
}
}
else
{
BuildMI
(
FirstMBB
,
MBBI
,
DL
,
TII
->
get
(
X86
::
MOVPC32r
)
,
PC
)
.
addImm
(
0
)
;
if
(
STI
.
isPICStyleGOT
(
)
)
{
BuildMI
(
FirstMBB
,
MBBI
,
DL
,
TII
->
get
(
X86
::
ADD32ri
)
,
GlobalBaseReg
)
.
addReg
(
PC
)
.
addExternalSymbol
(
"_GLOBAL_OFFSET_TABLE_"
,
X86II
::
MO_GOT_ABSOLUTE_ADDRESS
)
;
}
}
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> TargetLowering :: AtomicExpansionKind SITargetLowering :: shouldExpandAtomicStoreInIR ( StoreInst * SI ) const { return SI -> getPointerAddressSpace ( ) == AMDGPUAS :: PRIVATE_ADDRESS ? AtomicExpansionKind :: NotAtomic : AtomicExpansionKind :: None ; } </s>

Returns how the given ( atomic ) store should be expanded by the IR-level AtomicExpand pass into .


<s> bool AMDGPUAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( ! AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , O ) ) return false ; if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { case 'r' : break ; default : return true ; } } const MachineOperand & MO = MI -> getOperand ( OpNo ) ; if ( MO . isReg ( ) ) { AMDGPUInstPrinter :: printRegOperand ( MO . getReg ( ) , O , * MF -> getSubtarget ( ) . getRegisterInfo ( ) ) ; return false ; } else if ( MO . isImm ( ) ) { int64_t Val = MO . getImm ( ) ; if ( AMDGPU :: isInlinableIntLiteral ( Val ) ) { O << Val ; } else if ( isUInt < 16 > ( Val ) ) { O << format ( "0x%" PRIx64 , static_cast < uint16_t > ( Val ) ) ; } else if ( isUInt < 32 > ( Val ) ) { O << format ( "0x%" PRIx64 , static_cast < uint32_t > ( Val ) ) ; } else { O << format ( "0x%" PRIx64 , static_cast < uint64_t > ( Val ) ) ; } return false ; } return true ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> bool rx_match_ccmode ( rtx insn , machine_mode cc_mode ) { rtx op1 , flags ; machine_mode flags_mode ; gcc_checking_assert ( XVECLEN ( PATTERN ( insn ) , 0 ) == 2 ) ; op1 = XVECEXP ( PATTERN ( insn ) , 0 , 1 ) ; gcc_checking_assert ( GET_CODE ( SET_SRC ( op1 ) ) == COMPARE ) ; flags = SET_DEST ( op1 ) ; flags_mode = GET_MODE ( flags ) ; if ( GET_MODE ( SET_SRC ( op1 ) ) != flags_mode ) return false ; if ( GET_MODE_CLASS ( flags_mode ) != MODE_CC ) return false ; if ( flags_from_mode ( flags_mode ) & ~ flags_from_mode ( cc_mode ) ) return false ; return true ; } </s>

A helper function for matching parallels that set the flags .


<s> void WebAssemblyFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { auto * MFI = MF . getFrameInfo ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! needsSP ( MF , * MFI ) || ! needsSPWriteback ( MF , * MFI ) ) return ; auto * WFI = MF . getInfo < WebAssemblyFunctionInfo > ( ) ; const auto * TII = MF . getSubtarget < WebAssemblySubtarget > ( ) . getInstrInfo ( ) ; auto & MRI = MF . getRegInfo ( ) ; auto InsertPt = MBB . getFirstTerminator ( ) ; DebugLoc DL ; if ( InsertPt != MBB . end ( ) ) { DL = InsertPt -> getDebugLoc ( ) ; } if ( StackSize ) { unsigned OffsetReg = MRI . createVirtualRegister ( & WebAssembly :: I32RegClass ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( WebAssembly :: CONST_I32 ) , OffsetReg ) . addImm ( StackSize ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( WebAssembly :: ADD_I32 ) , WebAssembly :: SP32 ) . addReg ( hasFP ( MF ) ? WebAssembly :: FP32 : WebAssembly :: SP32 ) . addReg ( OffsetReg ) ; WFI -> stackifyVReg ( OffsetReg ) ; } writeSPToMemory ( ( ! StackSize && hasFP ( MF ) ) ? WebAssembly :: FP32 : WebAssembly :: SP32 , MF , MBB , InsertPt , DL ) ; } </s>


<s> void RISCVTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; } </s>

This method must be called before any actual lowering is done .


<s> void EmitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , bool ) override { EmitA64MappingSymbol ( ) ; MCELFStreamer :: EmitInstruction ( Inst , STI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
void
RegisterAggr
::
print
(
raw_ostream
&
OS
)
const
{
OS
<<
'{'
;
for
(
int
U
=
Units
.
find_first
(
)
;
U
>=
0
;
U
=
Units
.
find_next
(
U
)
)
OS
<<
' '
<<
PrintRegUnit
(
U
,
&
PRI
.
getTRI
(
)
)
;
OS
<<
" }"
;
}
</s>

print - Print a debug representation of the operand to the given stream .


<s>
int
arc_output_commutative_cond_exec
(
rtx
*
operands
,
bool
output_p
)
{
enum
rtx_code
commutative_op
=
GET_CODE
(
operands
[
3
]
)
;
const
char
*
pat
=
;
gcc_assert
(
!
CONSTANT_P
(
operands
[
1
]
)
)
;
switch
(
commutative_op
)
{
case
AND
:
if
(
satisfies_constraint_C1p
(
operands
[
2
]
)
)
pat
=
"bmsk%? %0,%1,%Z2"
;
else
if
(
satisfies_constraint_Ccp
(
operands
[
2
]
)
)
pat
=
"bclr%? %0,%1,%M2"
;
else
if
(
satisfies_constraint_CnL
(
operands
[
2
]
)
)
pat
=
"bic%? %0,%1,%n2-1"
;
break
;
case
IOR
:
if
(
satisfies_constraint_C0p
(
operands
[
2
]
)
)
pat
=
"bset%? %0,%1,%z2"
;
break
;
case
XOR
:
if
(
satisfies_constraint_C0p
(
operands
[
2
]
)
)
pat
=
"bxor%? %0,%1,%z2"
;
break
;
case
PLUS
:
return
arc_output_addsi
(
operands
,
true
,
output_p
)
;
default
:
break
;
}
if
(
output_p
)
output_asm_insn
(
pat
pat
:
"%O3.%d5 %0,%1,%2"
,
operands
)
;
if
(
pat
||
REG_P
(
operands
[
2
]
)
||
satisfies_constraint_L
(
operands
[
2
]
)
)
return
4
;
return
8
;
}
</s>

Emit code for an commutative_cond_exec instruction with OPERANDS . Return the length of the instruction . If OUTPUT_P is false , do n't actually output the instruction , just return its length .


<s> unsigned M88kInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { if ( MI . isInlineAsm ( ) ) { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } return MI . getDesc ( ) . getSize ( ) ; } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> const char * output_simode_bld ( int bild , rtx operands [ ] ) { int clear_first = ( REG_P ( operands [ 0 ] ) && REG_P ( operands [ 1 ] ) && REGNO ( operands [ 0 ] ) != REGNO ( operands [ 1 ] ) ) ; if ( clear_first ) output_asm_insn ( "sub.l\t%S0,%S0" , operands ) ; if ( bild ) output_asm_insn ( "bild\t%Z2,%Y1" , operands ) ; else output_asm_insn ( "bld\t%Z2,%Y1" , operands ) ; if ( ! clear_first ) output_asm_insn ( "xor.l\t%S0,%S0" , operands ) ; output_asm_insn ( "rotxl.l\t%S0" , operands ) ; return "" ; } </s>


<s> MCSymbol * AArch64AsmPrinter :: GetCPISymbol ( unsigned CPID ) const { if ( ! getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) . empty ( ) ) return OutContext . getOrCreateSymbol ( Twine ( getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) ) + "CPI" + Twine ( getFunctionNumber ( ) ) + "_" + Twine ( CPID ) ) ; return AsmPrinter :: GetCPISymbol ( CPID ) ; } </s>

Return the symbol for the specified constant pool entry .


"instruction use requires an option to be enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> const TGSIInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> bool WebAssembly :: mayThrow ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { case WebAssembly :: THROW_I32 : case WebAssembly :: THROW_I64 : case WebAssembly :: RETHROW : return true ; } if ( isCallIndirect ( MI ) ) return true ; if ( ! MI . isCall ( ) ) return false ; const MachineOperand & MO = MI . getOperand ( getCalleeOpNo ( MI ) ) ; assert ( MO . isGlobal ( ) ) ; const auto * F = dyn_cast < Function > ( MO . getGlobal ( ) ) ; if ( ! F ) return true ; if ( F -> doesNotThrow ( ) ) return false ; if ( F -> getName ( ) == CxaBeginCatchFn || F -> getName ( ) == PersonalityWrapperFn || F -> getName ( ) == ClangCallTerminateFn || F -> getName ( ) == StdTerminateFn ) return false ; return true ; } </s>

Return true if this instruction may throw an exception .


<s> const MCSection * X86ELFMCAsmInfo :: getNonexecutableStackSection ( MCContext & Ctx ) const { return Ctx . getELFSection ( ".note.GNU-stack" , MCSectionELF :: SHT_PROGBITS , 0 , SectionKind :: getMetadata ( ) ) ; } </s>

Targets can implement this method to specify a section to switch to if the translation unit does n't have any trampolines that require an executable stack .


<s> SDValue AArch64TargetLowering :: getSqrtEstimate ( SDValue Operand , SelectionDAG & DAG , int Enabled , int & ExtraSteps , bool & UseOneConst , bool Reciprocal ) const { if ( Enabled == ReciprocalEstimate :: Enabled || ( Enabled == ReciprocalEstimate :: Unspecified && Subtarget -> useRSqrt ( ) ) ) if ( SDValue Estimate = getEstimate ( Subtarget , AArch64ISD :: FRSQRTE , Operand , DAG , ExtraSteps ) ) { SDLoc DL ( Operand ) ; EVT VT = Operand . getValueType ( ) ; SDNodeFlags Flags ; Flags . setUnsafeAlgebra ( true ) ; for ( int i = ExtraSteps ; i > 0 ; -- i ) { SDValue Step = DAG . getNode ( ISD :: FMUL , DL , VT , Estimate , Estimate , & Flags ) ; Step = DAG . getNode ( AArch64ISD :: FRSQRTS , DL , VT , Operand , Step , & Flags ) ; Estimate = DAG . getNode ( ISD :: FMUL , DL , VT , Estimate , Step , & Flags ) ; } if ( ! Reciprocal ) { EVT CCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue FPZero = DAG . getConstantFP ( 0.0 , DL , VT ) ; SDValue Eq = DAG . getSetCC ( DL , CCVT , Operand , FPZero , ISD :: SETEQ ) ; Estimate = DAG . getNode ( ISD :: FMUL , DL , VT , Operand , Estimate , & Flags ) ; Estimate = DAG . getNode ( VT . isVector ( ) ? ISD :: VSELECT : ISD :: SELECT , DL , VT , Eq , Operand , Estimate ) ; } ExtraSteps = 0 ; return Estimate ; } return SDValue ( ) ; } </s>

Hooks for building estimates in place of slower divisions and square roots .


<s> unsigned postOffset ( unsigned LogAlign = 0 ) const { unsigned PO = Offset + Size ; if ( ! LogAlign ) return PO ; return PO + UnknownPadding ( LogAlign , internalKnownBits ( ) ) ; } </s>

Compute the offset immediately following this block .


<s> bool ix86_agi_dependent ( rtx_insn * set_insn , rtx_insn * use_insn ) { int i ; extract_insn_cached ( use_insn ) ; for ( i = recog_data . n_operands - 1 ; i >= 0 ; -- i ) if ( MEM_P ( recog_data . operand [ i ] ) ) { rtx addr = XEXP ( recog_data . operand [ i ] , 0 ) ; if ( modified_in_p ( addr , set_insn ) != 0 ) { rtx set = single_set ( set_insn ) ; if ( set && ( push_operand ( SET_DEST ( set ) , GET_MODE ( SET_DEST ( set ) ) ) || pop_operand ( SET_SRC ( set ) , GET_MODE ( SET_SRC ( set ) ) ) ) ) { struct ix86_address parts ; if ( ix86_decompose_address ( addr , & parts ) && parts . base == stack_pointer_rtx && ( parts . index == NULL_RTX || MEM_P ( SET_DEST ( set ) ) || ! modified_in_p ( parts . index , set_insn ) ) ) return false ; } return true ; } return false ; } return false ; } </s>

Return true iff USE_INSN has a memory address with operands set by SET_INSN .


<s> static void add_to_sp ( rtx spreg , HOST_WIDE_INT value , int frame ) { if ( value == 0 ) return ; if ( value > 120 || value < - 120 ) { rtx tmpreg = gen_rtx_REG ( SImode , REG_P1 ) ; rtx insn ; if ( frame ) frame_related_constant_load ( tmpreg , value , TRUE ) ; else { insn = emit_move_insn ( tmpreg , GEN_INT ( value ) ) ; if ( frame ) RTX_FRAME_RELATED_P ( insn ) = 1 ; } insn = emit_insn ( gen_addsi3 ( spreg , spreg , tmpreg ) ) ; if ( frame ) RTX_FRAME_RELATED_P ( insn ) = 1 ; } else do { int size = value ; rtx insn ; if ( size > 60 ) size = 60 ; else if ( size < - 60 ) size = - 60 ; insn = emit_insn ( gen_addsi3 ( spreg , spreg , GEN_INT ( size ) ) ) ; if ( frame ) RTX_FRAME_RELATED_P ( insn ) = 1 ; value -= size ; } while ( value != 0 ) ; } </s>

Generate efficient code to add a value to the frame pointer . We can use P1 as a scratch register . Set RTX_FRAME_RELATED_P on the generated insns if FRAME is nonzero .


<s>
static
rtx
nds32_expand_builtin_null_ftype_reg
(
enum
insn_code
icode
,
tree
exp
,
rtx
target
)
{
struct
expand_operand
ops
[
1
]
;
tree
arg0
;
rtx
value0
;
arg0
=
CALL_EXPR_ARG
(
exp
,
0
)
;
value0
=
expand_normal
(
arg0
)
;
create_input_operand
(
&
ops
[
0
]
,
value0
,
TYPE_MODE
(
TREE_TYPE
(
arg0
)
)
)
;
if
(
!
maybe_expand_insn
(
icode
,
1
,
ops
)
)
error
(
"invalid argument to built-in function"
)
;
return
target
;
}
</s>

Function to expand builtin function for ' [ ( unspec_volatile [ ( reg ) ] ) ] ' .


<s> static bool cdx_mov_immed ( rtx op ) { if ( CONST_INT_P ( op ) ) { HOST_WIDE_INT ival = INTVAL ( op ) ; return ( ( ival >= 0 && ival <= 124 ) || ival == 0xff || ival == - 2 || ival == - 1 ) ; } return false ; } </s>

Returns true if OP is within range of CDX movi.n immediates .


<s> bool ARMTargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { if ( ! Subtarget -> supportsTailCall ( ) ) return false ; auto Attr = CI -> getParent ( ) -> getParent ( ) -> getFnAttribute ( "disable-tail-calls" ) ; if ( ! CI -> isTailCall ( ) || Attr . getValueAsString ( ) == "true" ) return false ; return true ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> const AVRRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .