<s> static bool classof ( const MCExpr * E ) { return E -> getKind ( ) == MCExpr :: Target ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> bool PPCTargetLowering :: SelectAddressRegReg ( SDValue N , SDValue & Base , SDValue & Index , SelectionDAG & DAG , unsigned EncodingAlignment ) const { if ( SelectAddressPCRel ( N , Base ) ) return false ; int16_t imm = 0 ; if ( N . getOpcode ( ) == ISD :: ADD ) { if ( hasSPE ( ) && SelectAddressEVXRegReg ( N , Base , Index , DAG ) ) return true ; if ( isIntS16Immediate ( N . getOperand ( 1 ) , imm ) && ( ! EncodingAlignment || ! ( imm % EncodingAlignment ) ) ) return false ; if ( N . getOperand ( 1 ) . getOpcode ( ) == PPCISD :: Lo ) return false ; Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } else if ( N . getOpcode ( ) == ISD :: OR ) { if ( isIntS16Immediate ( N . getOperand ( 1 ) , imm ) && ( ! EncodingAlignment || ! ( imm % EncodingAlignment ) ) ) return false ; KnownBits LHSKnown = DAG . computeKnownBits ( N . getOperand ( 0 ) ) ; if ( LHSKnown . Zero . getBoolValue ( ) ) { KnownBits RHSKnown = DAG . computeKnownBits ( N . getOperand ( 1 ) ) ; if ( ~ ( LHSKnown . Zero | RHSKnown . Zero ) == 0 ) { Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } } } return false ; } </s>

SelectAddressRegReg - Given the specified addressed , check to see if it can be more efficiently represented as [ r+imm ] .


"Only optimizing constant comparisons so far"

optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare ; remove Compare if possible .


<s> void AArch64PreLegalizerCombiner :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < TargetPassConfig > ( ) ; AU . setPreservesCFG ( ) ; getSelectionDAGFallbackAnalysisUsage ( AU ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
SDValue
OR1KTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
isVarArg
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> void emit_pic_move ( rtx * operands , machine_mode ) { rtx temp = reload_in_progress ? operands [ 0 ] : gen_reg_rtx ( Pmode ) ; if ( GET_CODE ( operands [ 0 ] ) == MEM && SYMBOLIC_CONST ( operands [ 1 ] ) ) operands [ 1 ] = force_reg ( Pmode , operands [ 1 ] ) ; else operands [ 1 ] = arc_legitimize_pic_address ( operands [ 1 ] , temp ) ; } </s>

Emit insns to move operands [ 1 ] into operands [ 0 ] .


<s> unsigned getBasePointerSaveOffset ( ) const { return BasePointerSaveOffset ; } </s>

getBasePointerSaveOffset - Return the previous frame offset to save the base pointer .


<s> void * getAdjustedAnalysisPointer ( const void * ID ) override { if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo * ) this ; return this ; } </s>

getAdjustedAnalysisPointer - This method is used when a pass implements an analysis interface through multiple inheritance .


<s> unsigned MipsAsmParser :: checkTargetMatchPredicate ( MCInst & Inst ) { unsigned Opcode = Inst . getOpcode ( ) ; if ( Opcode == Mips :: JALR_HB && ( Inst . getOperand ( 0 ) . getReg ( ) == Inst . getOperand ( 1 ) . getReg ( ) ) ) return Match_RequiresDifferentSrcAndDst ; return Match_Success ; } </s>

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


<s> int dead_register_here ( rtx x , rtx reg ) { rtx x_reg ; rtx p ; if ( D_REG_P ( reg ) ) x_reg = gen_rtx_REG ( SImode , HARD_X_REGNUM ) ; else x_reg = 0 ; for ( p = PREV_INSN ( x ) ; p && GET_CODE ( p ) != CODE_LABEL ; p = PREV_INSN ( p ) ) if ( INSN_P ( p ) ) { rtx body ; body = PATTERN ( p ) ; if ( GET_CODE ( body ) == CALL_INSN ) break ; if ( GET_CODE ( body ) == JUMP_INSN ) break ; if ( GET_CODE ( body ) == SET ) { rtx dst = XEXP ( body , 0 ) ; if ( GET_CODE ( dst ) == REG && REGNO ( dst ) == REGNO ( reg ) ) break ; if ( x_reg && rtx_equal_p ( dst , x_reg ) ) break ; if ( find_regno_note ( p , REG_DEAD , REGNO ( reg ) ) ) return 1 ; } else if ( reg_mentioned_p ( reg , p ) || ( x_reg && reg_mentioned_p ( x_reg , p ) ) ) break ; } for ( p = x ; p ; p = NEXT_INSN ( p ) ) { rtx body ; if ( GET_CODE ( p ) == CODE_LABEL || GET_CODE ( p ) == JUMP_INSN || GET_CODE ( p ) == CALL_INSN || GET_CODE ( p ) == BARRIER ) break ; if ( GET_CODE ( p ) != INSN ) continue ; body = PATTERN ( p ) ; if ( GET_CODE ( body ) == SET ) { rtx src = XEXP ( body , 1 ) ; rtx dst = XEXP ( body , 0 ) ; if ( GET_CODE ( dst ) == REG && REGNO ( dst ) == REGNO ( reg ) && ! reg_mentioned_p ( reg , src ) ) return 1 ; } if ( reg_mentioned_p ( reg , p ) || ( x_reg != 0 && GET_MODE ( p ) == SImode && reg_mentioned_p ( x_reg , p ) ) ) break ; } return p == 0 ? 1 : 0 ; } </s>

Finds backward in the instructions to see if register 'reg ' is dead . This is used when generating code to see if we can use 'reg ' as a scratch register . This allows us to choose a better generation of code when we know that some register dies or can be clobbered .


<s> std :: pair < unsigned , const TargetRegisterClass * > PPCTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'b' : if ( VT == MVT :: i64 && Subtarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RC_NOX0RegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRC_NOR0RegClass ) ; case 'r' : if ( VT == MVT :: i64 && Subtarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RCRegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRCRegClass ) ; case 'f' : if ( VT == MVT :: f32 || VT == MVT :: i32 ) return std :: make_pair ( 0U , & PPC :: F4RCRegClass ) ; if ( VT == MVT :: f64 || VT == MVT :: i64 ) return std :: make_pair ( 0U , & PPC :: F8RCRegClass ) ; break ; case 'v' : return std :: make_pair ( 0U , & PPC :: VRRCRegClass ) ; case 'y' : return std :: make_pair ( 0U , & PPC :: CRRCRegClass ) ; } } else if ( Constraint == "wc" ) { return std :: make_pair ( 0U , & PPC :: CRBITRCRegClass ) ; } else if ( Constraint == "wa" || Constraint == "wd" || Constraint == "wf" ) { return std :: make_pair ( 0U , & PPC :: VSRCRegClass ) ; } else if ( Constraint == "ws" ) { return std :: make_pair ( 0U , & PPC :: VSFRCRegClass ) ; } std :: pair < unsigned , const TargetRegisterClass * > R = TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; if ( R . first && VT == MVT :: i64 && Subtarget . isPPC64 ( ) && PPC :: GPRCRegClass . contains ( R . first ) ) { const TargetRegisterInfo * TRI = getTargetMachine ( ) . getRegisterInfo ( ) ; return std :: make_pair ( TRI -> getMatchingSuperReg ( R . first , PPC :: sub_32 , & PPC :: G8RCRegClass ) , & PPC :: G8RCRegClass ) ; } return R ; } </s>

Given a physical register constraint ( e.g .


"%qE attribute only applies to functions"

"%qE attribute requires an integer argument"

Handle an attribute requiring a FUNCTION_DECL ; arguments as in struct attribute_spec.handler .


<s> bool MipsSERegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s>
void
dump
(
)
{
dbgs
(
)
<<
"M68kISelAddressMode "
<<
this
;
dbgs
(
)
<<
"\nDisp: "
<<
Disp
;
dbgs
(
)
<<
", BaseReg: "
;
if
(
BaseReg
.
getNode
(
)
)
BaseReg
.
getNode
(
)
->
dump
(
)
;
else
dbgs
(
)
<<
"null"
;
dbgs
(
)
<<
", BaseFI: "
<<
BaseFrameIndex
;
dbgs
(
)
<<
", IndexReg: "
;
if
(
IndexReg
.
getNode
(
)
)
{
IndexReg
.
getNode
(
)
->
dump
(
)
;
}
else
{
dbgs
(
)
<<
"null"
;
dbgs
(
)
<<
", Scale: "
<<
Scale
;
}
dbgs
(
)
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

M68k
"M68kISelAddressMode "
"\nDisp: "
", BaseReg: "
"null"
", BaseFI: "
", IndexReg: "
"null"
", Scale: "


<s> SDValue X86TargetLowering :: getSqrtEstimate ( SDValue Op , SelectionDAG & DAG , int Enabled , int & RefinementSteps , bool & UseOneConstNR , bool Reciprocal ) const { EVT VT = Op . getValueType ( ) ; if ( ( VT == MVT :: f32 && Subtarget . hasSSE1 ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasSSE1 ( ) ) || ( VT == MVT :: v8f32 && Subtarget . hasAVX ( ) ) ) { if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = 1 ; UseOneConstNR = false ; return DAG . getNode ( X86ISD :: FRSQRT , SDLoc ( Op ) , VT , Op ) ; } return SDValue ( ) ; } </s>

Hooks for building estimates in place of slower divisions and square roots .


<s> void frv_expand_epilogue ( bool emit_return ) { frv_stack_t * info = frv_stack_info ( ) ; rtx fp = frame_pointer_rtx ; rtx sp = stack_pointer_rtx ; rtx return_addr ; int fp_offset ; fp_offset = info -> reg_offset [ FRAME_POINTER_REGNUM ] ; if ( ! crtl -> sp_is_unchanging ) emit_insn ( gen_addsi3 ( sp , fp , frv_frame_offset_rtx ( - fp_offset ) ) ) ; frv_frame_access_standard_regs ( FRV_LOAD , info ) ; if ( info -> save_p [ LR_REGNO ] ) { int lr_offset ; rtx mem ; lr_offset = info -> reg_offset [ LR_REGNO ] ; if ( frame_pointer_needed ) mem = frv_frame_mem ( Pmode , fp , lr_offset - fp_offset ) ; else mem = frv_frame_mem ( Pmode , sp , lr_offset ) ; return_addr = gen_rtx_REG ( Pmode , TEMP_REGNO ) ; emit_insn ( gen_rtx_SET ( return_addr , mem ) ) ; } else return_addr = gen_rtx_REG ( Pmode , LR_REGNO ) ; if ( frame_pointer_needed ) { emit_insn ( gen_rtx_SET ( fp , gen_rtx_MEM ( Pmode , fp ) ) ) ; emit_use ( fp ) ; } if ( info -> total_size != 0 ) { rtx offset = frv_frame_offset_rtx ( info -> total_size ) ; emit_insn ( gen_stack_adjust ( sp , sp , offset ) ) ; } if ( crtl -> calls_eh_return ) emit_insn ( gen_stack_adjust ( sp , sp , EH_RETURN_STACKADJ_RTX ) ) ; if ( emit_return ) emit_jump_insn ( gen_epilogue_return ( return_addr ) ) ; else { rtx lr = return_addr ; if ( REGNO ( return_addr ) != LR_REGNO ) { lr = gen_rtx_REG ( Pmode , LR_REGNO ) ; emit_move_insn ( lr , return_addr ) ; } emit_use ( lr ) ; } } </s>

Called after register allocation to add any instructions needed for the epilogue . Using an epilogue insn is favored compared to putting all of the instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook , since it allows the scheduler to intermix instructions with the saves of the caller saved registers . In some cases , it might be necessary to emit a barrier instruction as the last insn to prevent such scheduling .


<s> bool sh_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_SHMEDIA_FPU && ( ( mode == V2SFmode ) || ( mode == V4SFmode ) || ( mode == V16SFmode ) ) ) return true ; else if ( TARGET_SHMEDIA && ( ( mode == V8QImode ) || ( mode == V2HImode ) || ( mode == V4HImode ) || ( mode == V2SImode ) ) ) return true ; return false ; } </s>

Implements target hook vector_mode_supported_p .


<s> static rtx m32c_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { if ( mode == DFmode ) { rtx rv ; rv = gen_rtx_PARALLEL ( mode , rtvec_alloc ( 4 ) ) ; XVECEXP ( rv , 0 , 0 ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( HImode , R0_REGNO ) , GEN_INT ( 0 ) ) ; XVECEXP ( rv , 0 , 1 ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( HImode , R1_REGNO ) , GEN_INT ( 2 ) ) ; XVECEXP ( rv , 0 , 2 ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( HImode , R2_REGNO ) , GEN_INT ( 4 ) ) ; XVECEXP ( rv , 0 , 3 ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( HImode , R3_REGNO ) , GEN_INT ( 6 ) ) ; return rv ; } if ( TARGET_A24 && GET_MODE_SIZE ( mode ) > 2 ) { rtx rv ; rv = gen_rtx_PARALLEL ( mode , rtvec_alloc ( 1 ) ) ; XVECEXP ( rv , 0 , 0 ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , R0_REGNO ) , GEN_INT ( 0 ) ) ; return rv ; } if ( GET_MODE_SIZE ( mode ) > 2 ) return gen_rtx_REG ( mode , MEM0_REGNO ) ; return gen_rtx_REG ( mode , R0_REGNO ) ; } </s>

Implements LIBCALL_VALUE . Most values are returned in $ r0 , or some combination of registers starting there ( r2r0 for longs , r3r1r2r0 for long long , r3r2r1r0 for doubles ) , except that that ABI currently does n't work because it ends up using all available general registers and gcc often ca n't compile it . So , instead , we return anything bigger than 16 bits in `` mem0 '' ( effectively , a memory location ) .


<s> static int optimal_immediate_sequence ( enum rtx_code code , unsigned HOST_WIDE_INT val , struct four_ints * return_sequence ) { int best_consecutive_zeros = 0 ; int i ; int best_start = 0 ; int insns1 , insns2 ; struct four_ints tmp_sequence ; if ( TARGET_ARM ) { for ( i = 0 ; i < 32 ; i += 2 ) { int consecutive_zeros = 0 ; if ( ! ( val & ( 3 << i ) ) ) { while ( ( i < 32 ) && ! ( val & ( 3 << i ) ) ) { consecutive_zeros += 2 ; i += 2 ; } if ( consecutive_zeros > best_consecutive_zeros ) { best_consecutive_zeros = consecutive_zeros ; best_start = i - consecutive_zeros ; } i -= 2 ; } } } insns1 = optimal_immediate_sequence_1 ( code , val , return_sequence , best_start ) ; if ( best_start != 0 && ( ( HOST_WIDE_INT_1U << best_start ) < val ) ) { insns2 = optimal_immediate_sequence_1 ( code , val , & tmp_sequence , 0 ) ; if ( insns2 <= insns1 ) { * return_sequence = tmp_sequence ; insns1 = insns2 ; } } return insns1 ; } </s>

Return a sequence of integers , in RETURN_SEQUENCE that fit into ARM/THUMB2 immediates , and add up to VAL . Thr function return value gives the number of insns required .


<s> bool AMDGPUAnnotateKernelFeatures :: runOnModule ( Module & M ) { Triple TT ( M . getTargetTriple ( ) ) ; static const StringRef IntrinsicToAttr [ ] [ 2 ] = { { "llvm.amdgcn.workitem.id.y" , "amdgpu-work-item-id-y" } , { "llvm.amdgcn.workitem.id.z" , "amdgpu-work-item-id-z" } , { "llvm.amdgcn.workgroup.id.y" , "amdgpu-work-group-id-y" } , { "llvm.amdgcn.workgroup.id.z" , "amdgpu-work-group-id-z" } , { "llvm.r600.read.tgid.y" , "amdgpu-work-group-id-y" } , { "llvm.r600.read.tgid.z" , "amdgpu-work-group-id-z" } , { "llvm.r600.read.tidig.y" , "amdgpu-work-item-id-y" } , { "llvm.r600.read.tidig.z" , "amdgpu-work-item-id-z" } } ; static const StringRef HSAIntrinsicToAttr [ ] [ 2 ] = { { "llvm.amdgcn.dispatch.ptr" , "amdgpu-dispatch-ptr" } , { "llvm.amdgcn.queue.ptr" , "amdgpu-queue-ptr" } } ; bool Changed = addAttrsForIntrinsics ( M , IntrinsicToAttr ) ; if ( TT . getOS ( ) == Triple :: AMDHSA ) { Changed |= addAttrsForIntrinsics ( M , HSAIntrinsicToAttr ) ; for ( Function & F : M ) { if ( F . hasFnAttribute ( "amdgpu-queue-ptr" ) ) continue ; if ( hasAddrSpaceCast ( F ) ) F . addFnAttr ( "amdgpu-queue-ptr" ) ; } } return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> bool FISCRegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> const char * PPCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case PPCISD :: FSEL : return "PPCISD::FSEL" ; case PPCISD :: FCFID : return "PPCISD::FCFID" ; case PPCISD :: FCTIDZ : return "PPCISD::FCTIDZ" ; case PPCISD :: FCTIWZ : return "PPCISD::FCTIWZ" ; case PPCISD :: STFIWX : return "PPCISD::STFIWX" ; case PPCISD :: VMADDFP : return "PPCISD::VMADDFP" ; case PPCISD :: VNMSUBFP : return "PPCISD::VNMSUBFP" ; case PPCISD :: VPERM : return "PPCISD::VPERM" ; case PPCISD :: Hi : return "PPCISD::Hi" ; case PPCISD :: Lo : return "PPCISD::Lo" ; case PPCISD :: DYNALLOC : return "PPCISD::DYNALLOC" ; case PPCISD :: GlobalBaseReg : return "PPCISD::GlobalBaseReg" ; case PPCISD :: SRL : return "PPCISD::SRL" ; case PPCISD :: SRA : return "PPCISD::SRA" ; case PPCISD :: SHL : return "PPCISD::SHL" ; case PPCISD :: EXTSW_32 : return "PPCISD::EXTSW_32" ; case PPCISD :: STD_32 : return "PPCISD::STD_32" ; case PPCISD :: CALL_ELF : return "PPCISD::CALL_ELF" ; case PPCISD :: CALL_Macho : return "PPCISD::CALL_Macho" ; case PPCISD :: MTCTR : return "PPCISD::MTCTR" ; case PPCISD :: BCTRL_Macho : return "PPCISD::BCTRL_Macho" ; case PPCISD :: BCTRL_ELF : return "PPCISD::BCTRL_ELF" ; case PPCISD :: RET_FLAG : return "PPCISD::RET_FLAG" ; case PPCISD :: MFCR : return "PPCISD::MFCR" ; case PPCISD :: VCMP : return "PPCISD::VCMP" ; case PPCISD :: VCMPo : return "PPCISD::VCMPo" ; case PPCISD :: LBRX : return "PPCISD::LBRX" ; case PPCISD :: STBRX : return "PPCISD::STBRX" ; case PPCISD :: LARX : return "PPCISD::LARX" ; case PPCISD :: STCX : return "PPCISD::STCX" ; case PPCISD :: COND_BRANCH : return "PPCISD::COND_BRANCH" ; case PPCISD :: MFFS : return "PPCISD::MFFS" ; case PPCISD :: MTFSB0 : return "PPCISD::MTFSB0" ; case PPCISD :: MTFSB1 : return "PPCISD::MTFSB1" ; case PPCISD :: FADDRTZ : return "PPCISD::FADDRTZ" ; case PPCISD :: MTFSF : return "PPCISD::MTFSF" ; case PPCISD :: TAILCALL : return "PPCISD::TAILCALL" ; case PPCISD :: TC_RETURN : return "PPCISD::TC_RETURN" ; } } </s>

getTargetNodeName - This method returns the name of a target specific

PowerPC PPC 0 PPCISD::FSEL "PPCISD::FSEL" PPCISD::FCFID "PPCISD::FCFID" PPCISD::FCTIDZ "PPCISD::FCTIDZ" PPCISD::FCTIWZ "PPCISD::FCTIWZ" PPCISD::STFIWX "PPCISD::STFIWX" PPCISD::VMADDFP "PPCISD::VMADDFP" PPCISD::VNMSUBFP "PPCISD::VNMSUBFP" PPCISD::VPERM "PPCISD::VPERM" PPCISD::Hi "PPCISD::Hi" PPCISD::Lo "PPCISD::Lo" PPCISD::DYNALLOC "PPCISD::DYNALLOC" PPCISD::GlobalBaseReg "PPCISD::GlobalBaseReg" PPCISD::SRL "PPCISD::SRL" PPCISD::SRA "PPCISD::SRA" PPCISD::SHL "PPCISD::SHL" PPCISD::EXTSW_32 "PPCISD::EXTSW_32" PPCISD::STD_32 "PPCISD::STD_32" PPCISD::CALL_ELF "PPCISD::CALL_ELF" PPCISD::CALL_Macho "PPCISD::CALL_Macho" PPCISD::MTCTR "PPCISD::MTCTR" PPCISD::BCTRL_Macho "PPCISD::BCTRL_Macho" PPCISD::BCTRL_ELF "PPCISD::BCTRL_ELF" PPCISD::RET_FLAG "PPCISD::RET_FLAG" PPCISD::MFCR "PPCISD::MFCR" PPCISD::VCMP "PPCISD::VCMP" PPCISD::VCMPo "PPCISD::VCMPo" PPCISD::LBRX "PPCISD::LBRX" PPCISD::STBRX "PPCISD::STBRX" PPCISD::LARX "PPCISD::LARX" PPCISD::STCX "PPCISD::STCX" PPCISD::COND_BRANCH "PPCISD::COND_BRANCH" PPCISD::MFFS "PPCISD::MFFS" PPCISD::MTFSB0 "PPCISD::MTFSB0" PPCISD::MTFSB1 "PPCISD::MTFSB1" PPCISD::FADDRTZ "PPCISD::FADDRTZ" PPCISD::MTFSF "PPCISD::MTFSF" PPCISD::TAILCALL "PPCISD::TAILCALL" PPCISD::TC_RETURN "PPCISD::TC_RETURN"


<s> bool Tile64PassConfig :: addPreEmitPass ( ) { if ( static_cast < Tile64TargetMachine * > ( TM ) -> getSubtargetImpl ( ) -> isVLIWEnabled ( ) ) { addPass ( createTile64VLIWPacketizer ( ) ) ; } return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void assignValueToReg ( unsigned ValVReg , unsigned PhysReg , CCValAssign & VA ) override { markPhysRegUsed ( PhysReg ) ; switch ( VA . getLocInfo ( ) ) { default : { unsigned PhysRegSize = MRI . getTargetRegisterInfo ( ) -> getRegSizeInBits ( PhysReg , MRI ) ; unsigned ValSize = VA . getValVT ( ) . getSizeInBits ( ) ; unsigned LocSize = VA . getLocVT ( ) . getSizeInBits ( ) ; if ( PhysRegSize > ValSize && LocSize == ValSize ) { auto Copy = MIRBuilder . buildCopy ( LLT :: scalar ( PhysRegSize ) , PhysReg ) ; MIRBuilder . buildTrunc ( ValVReg , Copy ) ; return ; } MIRBuilder . buildCopy ( ValVReg , PhysReg ) ; break ; } case CCValAssign :: LocInfo :: SExt : case CCValAssign :: LocInfo :: ZExt : case CCValAssign :: LocInfo :: AExt : { auto Copy = MIRBuilder . buildCopy ( LLT { VA . getLocVT ( ) } , PhysReg ) ; MIRBuilder . buildTrunc ( ValVReg , Copy ) ; break ; } } } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> char * function_builder :: get_name ( const function_instance & instance , bool overloaded_p ) { append_name ( instance . base_name ) ; if ( overloaded_p ) switch ( instance . displacement_units ( ) ) { case UNITS_none : break ; case UNITS_bytes : append_name ( "_offset" ) ; break ; case UNITS_elements : append_name ( "_index" ) ; break ; case UNITS_vectors : append_name ( "_vnum" ) ; break ; } else append_name ( instance . mode_suffix ( ) . string ) ; for ( unsigned int i = 0 ; i < 2 ; ++ i ) if ( ! overloaded_p || instance . shape -> explicit_type_suffix_p ( i ) ) append_name ( instance . type_suffix ( i ) . string ) ; append_name ( pred_suffixes [ instance . pred ] ) ; return finish_name ( ) ; } </s>

Return the overloaded or full function name for INSTANCE ; OVERLOADED_P selects which . Allocate the string on m_string_obstack ; the caller must use obstack_free to free it after use .


<s> unsigned char X86Subtarget :: classifyGlobalReference ( const GlobalValue * GV , const Module & M ) const { if ( GV && ! GV -> hasInternalLinkage ( ) && ! GV -> hasPrivateLinkage ( ) ) { if ( ! dyn_cast_or_null < Function > ( GV ) && ! GV -> isThreadDependent ( ) && ! GV -> isThreadLocal ( ) ) { return X86II :: MO_DLLIMPORT ; } } if ( TM . getCodeModel ( ) == CodeModel :: Large && ! isPositionIndependent ( ) ) return X86II :: MO_NO_FLAG ; if ( GV ) { if ( Optional < ConstantRange > CR = GV -> getAbsoluteSymbolRange ( ) ) { if ( CR -> getUnsignedMax ( ) . ult ( 128 ) ) return X86II :: MO_ABS8 ; else return X86II :: MO_NO_FLAG ; } } if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return classifyLocalReference ( GV ) ; if ( isTargetCOFF ( ) ) { if ( GV -> hasDLLImportStorageClass ( ) ) return X86II :: MO_DLLIMPORT ; return X86II :: MO_COFFSTUB ; } if ( isOSWindows ( ) ) return X86II :: MO_NO_FLAG ; if ( is64Bit ( ) ) { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return isTargetELF ( ) ? X86II :: MO_GOT : X86II :: MO_NO_FLAG ; return X86II :: MO_GOTPCREL ; } if ( isTargetDarwin ( ) ) { if ( ! isPositionIndependent ( ) ) return X86II :: MO_DARWIN_NONLAZY ; return X86II :: MO_DARWIN_NONLAZY_PIC_BASE ; } return X86II :: MO_GOT ; } </s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


"getRegForInlineAsmConstraint Unhandled data type"


<s> bool SIInstrInfo :: isOperandLegal ( const MachineInstr & MI , unsigned OpIdx , const MachineOperand * MO ) const { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const MCInstrDesc & InstDesc = MI . getDesc ( ) ; const MCOperandInfo & OpInfo = InstDesc . OpInfo [ OpIdx ] ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const TargetRegisterClass * DefinedRC = OpInfo . RegClass != - 1 ? RI . getRegClass ( OpInfo . RegClass ) : nullptr ; if ( ! MO ) MO = & MI . getOperand ( OpIdx ) ; int ConstantBusLimit = ST . getConstantBusLimit ( MI . getOpcode ( ) ) ; int VOP3LiteralLimit = ST . hasVOP3Literal ( ) ? 1 : 0 ; if ( isVALU ( MI ) && usesConstantBus ( MRI , * MO , OpInfo ) ) { if ( isVOP3 ( MI ) && isLiteralConstantLike ( * MO , OpInfo ) && ! VOP3LiteralLimit -- ) return false ; SmallDenseSet < RegSubRegPair > SGPRsUsed ; if ( MO -> isReg ( ) ) SGPRsUsed . insert ( RegSubRegPair ( MO -> getReg ( ) , MO -> getSubReg ( ) ) ) ; for ( unsigned i = 0 , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { if ( i == OpIdx ) continue ; const MachineOperand & Op = MI . getOperand ( i ) ; if ( Op . isReg ( ) ) { RegSubRegPair SGPR ( Op . getReg ( ) , Op . getSubReg ( ) ) ; if ( ! SGPRsUsed . count ( SGPR ) && usesConstantBus ( MRI , Op , InstDesc . OpInfo [ i ] ) ) { if ( -- ConstantBusLimit <= 0 ) return false ; SGPRsUsed . insert ( SGPR ) ; } } else if ( InstDesc . OpInfo [ i ] . OperandType == AMDGPU :: OPERAND_KIMM32 ) { if ( -- ConstantBusLimit <= 0 ) return false ; } else if ( isVOP3 ( MI ) && AMDGPU :: isSISrcOperand ( InstDesc , i ) && isLiteralConstantLike ( Op , InstDesc . OpInfo [ i ] ) ) { if ( ! VOP3LiteralLimit -- ) return false ; if ( -- ConstantBusLimit <= 0 ) return false ; } } } if ( MO -> isReg ( ) ) { assert ( DefinedRC ) ; return isLegalRegOperand ( MRI , OpInfo , * MO ) ; } assert ( MO -> isImm ( ) || MO -> isTargetIndex ( ) || MO -> isFI ( ) ) ; if ( ! DefinedRC ) { return true ; } return isImmOperandLegal ( MI , OpIdx , * MO ) ; } </s>

Check if MO is a legal operand if it was the OpIdx Operand for MI .


"Not all fixup kinds added to Infos array"


<s> static void mips16_emit_constants ( struct mips16_constant * constants , rtx_insn * insn ) { int label_num = constants ? CODE_LABEL_NUMBER ( constants -> label ) : 0 ; struct mips16_constant * c , * next ; int align ; align = 0 ; if ( constants ) insn = emit_insn_after ( gen_consttable ( GEN_INT ( label_num ) ) , insn ) ; for ( c = constants ; c != NULL ; c = next ) { if ( align < GET_MODE_SIZE ( c -> mode ) ) { int align_log = floor_log2 ( GET_MODE_SIZE ( c -> mode ) ) ; insn = emit_insn_after ( gen_align ( GEN_INT ( align_log ) ) , insn ) ; } align = GET_MODE_SIZE ( c -> mode ) ; insn = emit_label_after ( c -> label , insn ) ; insn = mips16_emit_constants_1 ( c -> mode , c -> value , insn ) ; next = c -> next ; free ( c ) ; } if ( constants ) insn = emit_insn_after ( gen_consttable_end ( GEN_INT ( label_num ) ) , insn ) ; emit_barrier_after ( insn ) ; } </s>

Dump out the constants in CONSTANTS after INSN .


<s>
unsigned
MipsCodeEmitter
::
getMachineOpValue
(
const
MachineInstr
&
MI
,
const
MachineOperand
&
MO
)
const
{
if
(
MO
.
isReg
(
)
)
return
getMipsRegisterNumbering
(
MO
.
getReg
(
)
)
;
else
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
else
if
(
MO
.
isGlobal
(
)
)
emitGlobalAddress
(
MO
.
getGlobal
(
)
,
getRelocation
(
MI
,
MO
)
,
true
)
;
else
if
(
MO
.
isSymbol
(
)
)
emitExternalSymbolAddress
(
MO
.
getSymbolName
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isCPI
(
)
)
emitConstPoolAddress
(
MO
.
getIndex
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isJTI
(
)
)
emitJumpTableAddress
(
MO
.
getIndex
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isMBB
(
)
)
emitMachineBasicBlock
(
MO
.
getMBB
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
llvm_unreachable
(
"Unable to encode MachineOperand!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .

Mips
Mips
Mips
"Unable to encode MachineOperand!"
0


<s> bool PatmosAsmPrinter :: isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { if ( MBB -> isLandingPad ( ) || MBB -> pred_empty ( ) || MBB -> hasAddressTaken ( ) ) return false ; MachineBasicBlock :: const_pred_iterator PI = MBB -> pred_begin ( ) , PI2 = PI ; if ( ++ PI2 != MBB -> pred_end ( ) ) return false ; const MachineBasicBlock * Pred = * PI ; if ( ! Pred -> isLayoutSuccessor ( MBB ) ) return false ; if ( isFStart ( MBB ) ) return false ; if ( Pred -> empty ( ) ) return true ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> isTerminator ( ) ) ; return I == Pred -> end ( ) || ! I -> isBarrier ( ) ; } </s>

isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


"Slot for FP register must be last in order to be found!"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> static unsigned rs6000_hash_constant ( rtx k ) { enum rtx_code code = GET_CODE ( k ) ; machine_mode mode = GET_MODE ( k ) ; unsigned result = ( code << 3 ) ^ mode ; const char * format ; int flen , fidx ; format = GET_RTX_FORMAT ( code ) ; flen = strlen ( format ) ; fidx = 0 ; switch ( code ) { case LABEL_REF : return result * 1231 + ( unsigned ) INSN_UID ( XEXP ( k , 0 ) ) ; case CONST_WIDE_INT : { int i ; flen = CONST_WIDE_INT_NUNITS ( k ) ; for ( i = 0 ; i < flen ; i ++ ) result = result * 613 + CONST_WIDE_INT_ELT ( k , i ) ; return result ; } case CONST_DOUBLE : if ( mode != VOIDmode ) return real_hash ( CONST_DOUBLE_REAL_VALUE ( k ) ) * result ; flen = 2 ; break ; case CODE_LABEL : fidx = 3 ; break ; default : break ; } for ( ; fidx < flen ; fidx ++ ) switch ( format [ fidx ] ) { case 's' : { unsigned i , len ; const char * str = XSTR ( k , fidx ) ; len = strlen ( str ) ; result = result * 613 + len ; for ( i = 0 ; i < len ; i ++ ) result = result * 613 + ( unsigned ) str [ i ] ; break ; } case 'u' : case 'e' : result = result * 1231 + rs6000_hash_constant ( XEXP ( k , fidx ) ) ; break ; case 'i' : case 'n' : result = result * 613 + ( unsigned ) XINT ( k , fidx ) ; break ; case 'w' : if ( sizeof ( unsigned ) >= sizeof ( HOST_WIDE_INT ) ) result = result * 613 + ( unsigned ) XWINT ( k , fidx ) ; else { size_t i ; for ( i = 0 ; i < sizeof ( HOST_WIDE_INT ) / sizeof ( unsigned ) ; i ++ ) result = result * 613 + ( unsigned ) ( XWINT ( k , fidx ) >> CHAR_BIT * i ) ; } break ; case '0' : break ; default : gcc_unreachable ( ) ; } return result ; } </s>


<s> static rtx c6x_function_arg ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( cum -> count >= cum -> nregs ) return NULL_RTX ; if ( type ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; if ( TARGET_BIG_ENDIAN && AGGREGATE_TYPE_P ( type ) ) { if ( size > 4 ) { rtx reg1 = gen_rtx_REG ( SImode , argument_registers [ cum -> count ] + 1 ) ; rtx reg2 = gen_rtx_REG ( SImode , argument_registers [ cum -> count ] ) ; rtvec vec = gen_rtvec ( 2 , gen_rtx_EXPR_LIST ( VOIDmode , reg1 , const0_rtx ) , gen_rtx_EXPR_LIST ( VOIDmode , reg2 , GEN_INT ( 4 ) ) ) ; return gen_rtx_PARALLEL ( mode , vec ) ; } } } return gen_rtx_REG ( mode , argument_registers [ cum -> count ] ) ; } </s>

Implements the macro FUNCTION_ARG defined in c6x.h .


<s> static inline bool mode_supports_vmx_dform ( machine_mode mode ) { return ( ( reg_addr [ mode ] . addr_mask [ RELOAD_REG_VMX ] & RELOAD_REG_OFFSET ) != 0 ) ; } </s>

Return true if we have D-form addressing in altivec registers .


<s>
MCSymbol
*
M68kMCInstLower
::
GetSymbolFromOperand
(
const
MachineOperand
&
MO
)
const
{
assert
(
(
MO
.
isGlobal
(
)
||
MO
.
isSymbol
(
)
||
MO
.
isMBB
(
)
)
&&
"Isn't a symbol reference"
)
;
const
auto
&
TT
=
TM
.
getTargetTriple
(
)
;
if
(
MO
.
isGlobal
(
)
&&
TT
.
isOSBinFormatELF
(
)
)
return
AsmPrinter
.
getSymbolPreferLocal
(
*
MO
.
getGlobal
(
)
)
;
const
DataLayout
&
DL
=
MF
.
getDataLayout
(
)
;
MCSymbol
*
Sym
=
nullptr
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
.
getPrivateGlobalPrefix
(
)
;
if
(
MO
.
isGlobal
(
)
)
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
AsmPrinter
.
getNameWithPrefix
(
Name
,
GV
)
;
}
else
if
(
MO
.
isSymbol
(
)
)
{
Mangler
::
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
,
DL
)
;
}
else
if
(
MO
.
isMBB
(
)
)
{
assert
(
Suffix
.
empty
(
)
)
;
Sym
=
MO
.
getMBB
(
)
->
getSymbol
(
)
;
}
Name
+=
Suffix
;
if
(
!
Sym
)
Sym
=
Ctx
.
getOrCreateSymbol
(
Name
)
;
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


<s> int includes_rldicr_lshift_p ( rtx shiftop , rtx andop ) { if ( GET_CODE ( andop ) == CONST_INT ) { unsigned HOST_WIDE_INT c , lsb , shift_mask ; shift_mask = HOST_WIDE_INT_M1U ; shift_mask <<= INTVAL ( shiftop ) ; c = INTVAL ( andop ) ; lsb = c & - c ; if ( ( lsb & shift_mask ) == 0 ) return 0 ; return c == - lsb && lsb != 1 ; } else return 0 ; } </s>

Return 1 if ANDOP is a mask suitable for use with an rldicr insn to perform a left shift . It must have SHIFTOP or more least significant 0 's , with the remainder of the word 1 's .


<s> unsigned PPCInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case PPC :: STD : case PPC :: STW : case PPC :: STFS : case PPC :: STFD : case PPC :: SPILL_CR : case PPC :: SPILL_CRBIT : case PPC :: STVX : case PPC :: STXVD2X : case PPC :: STXV : case PPC :: QVSTFDX : case PPC :: QVSTFSXs : case PPC :: QVSTFDXb : case PPC :: SPILL_VRSAVE : case PPC :: SPILLTOVSR_ST : if ( MI . getOperand ( 1 ) . isImm ( ) && ! MI . getOperand ( 1 ) . getImm ( ) && MI . getOperand ( 2 ) . isFI ( ) ) { FrameIndex = MI . getOperand ( 2 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> static bool use_real_merge_p ( enum predication_type_index pred ) { return pred == PRED_TYPE_tu || pred == PRED_TYPE_tum || pred == PRED_TYPE_tumu || pred == PRED_TYPE_mu ; } </s>

Return true if predication is using a real merge operand .


<s> bool HexagonPassConfig :: addPostRegAlloc ( ) { PM . add ( createHexagonCFGOptimizer ( getHexagonTargetMachine ( ) ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> unsigned getNumberOfRegisters ( unsigned ClassID ) const { bool Vector = ( ClassID == 1 ) ; if ( Vector ) { if ( ST -> hasNEON ( ) ) return 32 ; return 0 ; } return 31 ; } </s>


<s> bool SIWholeQuadMode :: runOnMachineFunction ( MachineFunction & MF ) { Instructions . clear ( ) ; Blocks . clear ( ) ; LiveMaskQueries . clear ( ) ; LowerToCopyInstrs . clear ( ) ; LowerToMovInstrs . clear ( ) ; CallingConv = MF . getFunction ( ) . getCallingConv ( ) ; ST = & MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST -> getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; LIS = & getAnalysis < LiveIntervals > ( ) ; if ( ST -> isWave32 ( ) ) { AndOpc = AMDGPU :: S_AND_B32 ; XorTermrOpc = AMDGPU :: S_XOR_B32_term ; OrSaveExecOpc = AMDGPU :: S_OR_SAVEEXEC_B32 ; Exec = AMDGPU :: EXEC_LO ; } else { AndOpc = AMDGPU :: S_AND_B64 ; XorTermrOpc = AMDGPU :: S_XOR_B64_term ; OrSaveExecOpc = AMDGPU :: S_OR_SAVEEXEC_B64 ; Exec = AMDGPU :: EXEC ; } char GlobalFlags = analyzeFunction ( MF ) ; unsigned LiveMaskReg = 0 ; if ( ! ( GlobalFlags & StateWQM ) ) { lowerLiveMaskQueries ( Exec ) ; if ( ! ( GlobalFlags & StateWWM ) && LowerToCopyInstrs . empty ( ) && LowerToMovInstrs . empty ( ) ) return ! LiveMaskQueries . empty ( ) ; } else { MachineBasicBlock & Entry = MF . front ( ) ; MachineBasicBlock :: iterator EntryMI = Entry . getFirstNonPHI ( ) ; if ( GlobalFlags & StateExact || ! LiveMaskQueries . empty ( ) ) { LiveMaskReg = MRI -> createVirtualRegister ( TRI -> getBoolRC ( ) ) ; MachineInstr * MI = BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( AMDGPU :: COPY ) , LiveMaskReg ) . addReg ( Exec ) ; LIS -> InsertMachineInstrInMaps ( * MI ) ; } lowerLiveMaskQueries ( LiveMaskReg ) ; if ( GlobalFlags == StateWQM ) { auto MI = BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( ST -> isWave32 ( ) ? AMDGPU :: S_WQM_B32 : AMDGPU :: S_WQM_B64 ) , Exec ) . addReg ( Exec ) ; LIS -> InsertMachineInstrInMaps ( * MI ) ; lowerCopyInstrs ( ) ; return true ; } } LLVM_DEBUG ( printInfo ( ) ) ; lowerCopyInstrs ( ) ; for ( auto BII : Blocks ) processBlock ( * BII . first , LiveMaskReg , BII . first == & * MF . begin ( ) ) ; if ( LiveMaskReg ) LIS -> createAndComputeVirtRegInterval ( LiveMaskReg ) ; LIS -> removeRegUnit ( * MCRegUnitIterator ( AMDGPU :: SCC , TRI ) ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> Align SITargetLowering :: getPrefLoopAlignment ( MachineLoop * ML ) const { const Align PrefAlign = TargetLowering :: getPrefLoopAlignment ( ML ) ; const Align CacheLineAlign = Align ( 64 ) ; if ( ! ML || DisableLoopAlignment || ( getSubtarget ( ) -> getGeneration ( ) < AMDGPUSubtarget :: GFX10 ) || getSubtarget ( ) -> hasInstFwdPrefetchBug ( ) ) return PrefAlign ; const SIInstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; const MachineBasicBlock * Header = ML -> getHeader ( ) ; if ( Header -> getAlignment ( ) != PrefAlign ) return Header -> getAlignment ( ) ; unsigned LoopSize = 0 ; for ( const MachineBasicBlock * MBB : ML -> blocks ( ) ) { if ( MBB != Header ) LoopSize += MBB -> getAlignment ( ) . value ( ) / 2 ; for ( const MachineInstr & MI : * MBB ) { LoopSize += TII -> getInstSizeInBytes ( MI ) ; if ( LoopSize > 192 ) return PrefAlign ; } } if ( LoopSize <= 64 ) return PrefAlign ; if ( LoopSize <= 128 ) return CacheLineAlign ; for ( MachineLoop * P = ML -> getParentLoop ( ) ; P ; P = P -> getParentLoop ( ) ) { if ( MachineBasicBlock * Exit = P -> getExitBlock ( ) ) { auto I = Exit -> getFirstNonDebugInstr ( ) ; if ( I != Exit -> end ( ) && I -> getOpcode ( ) == AMDGPU :: S_INST_PREFETCH ) return CacheLineAlign ; } } MachineBasicBlock * Pre = ML -> getLoopPreheader ( ) ; MachineBasicBlock * Exit = ML -> getExitBlock ( ) ; if ( Pre && Exit ) { auto PreTerm = Pre -> getFirstTerminator ( ) ; if ( PreTerm == Pre -> begin ( ) || std :: prev ( PreTerm ) -> getOpcode ( ) != AMDGPU :: S_INST_PREFETCH ) BuildMI ( * Pre , PreTerm , DebugLoc ( ) , TII -> get ( AMDGPU :: S_INST_PREFETCH ) ) . addImm ( 1 ) ; auto ExitHead = Exit -> getFirstNonDebugInstr ( ) ; if ( ExitHead == Exit -> end ( ) || ExitHead -> getOpcode ( ) != AMDGPU :: S_INST_PREFETCH ) BuildMI ( * Exit , ExitHead , DebugLoc ( ) , TII -> get ( AMDGPU :: S_INST_PREFETCH ) ) . addImm ( 2 ) ; } return CacheLineAlign ; } </s>


<s> const MipsInstrInfo * getInstrInfo ( ) const { return InstrInfo . get ( ) ; } </s>


"XCore DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> static machine_mode s390_preferred_simd_mode ( machine_mode mode ) { if ( TARGET_VX ) switch ( mode ) { case DFmode : return V2DFmode ; case DImode : return V2DImode ; case SImode : return V4SImode ; case HImode : return V8HImode ; case QImode : return V16QImode ; default : ; } return word_mode ; } </s>

Return the vector mode to be used for inner mode MODE when doing vectorization .


<s> const XtensaSubtarget * XtensaTargetMachine :: getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static bool tilepro_scalar_mode_supported_p ( scalar_mode mode ) { switch ( mode ) { case E_QImode : case E_HImode : case E_SImode : case E_DImode : return true ; case E_SFmode : case E_DFmode : return true ; default : return false ; } } </s>


<s> void push ( const Candidate && C ) { if ( C . Weight ) push_back ( C ) ; else push_front ( C ) ; } </s>


<s> const char * LC2200TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( LC2200ISD :: NodeType ) Opcode ) { case LC2200ISD :: FIRST_NUMBER : break ; case LC2200ISD :: RET : return "LC2200ISD::RET" ; case LC2200ISD :: CALL : return "LC2200ISD::CALL" ; case LC2200ISD :: JMP : return "LC2200ISD::JMP" ; case LC2200ISD :: NAND : return "LC2200ISD::NAND" ; case LC2200ISD :: CMP_SKIP : return "LC2200ISD::CMP_SKIP" ; case LC2200ISD :: CMP_JMP : return "LC2200ISD::CMP_JMP" ; case LC2200ISD :: SELECT_MOVE : return "LC2200ISD::SELECT_MOVE" ; case LC2200ISD :: CMP_SELECT_MOVE : return "LC2200ISD::CMP_SELECT_MOVE" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static bool frv_must_pass_in_stack ( enum machine_mode mode , tree type ) { if ( mode == BLKmode ) return true ; if ( type == NULL ) return false ; return AGGREGATE_TYPE_P ( type ) ; } </s>

Return true if we should pass an argument on the stack rather than in registers .


<s> const uint32_t * ARMBaseRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; if ( CC == CallingConv :: GHC ) return CSR_NoRegs_RegMask ; if ( STI . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return STI . isTargetDarwin ( ) ? CSR_iOS_SwiftError_RegMask : CSR_AAPCS_SwiftError_RegMask ; if ( STI . isTargetDarwin ( ) && CC == CallingConv :: CXX_FAST_TLS ) return CSR_iOS_CXX_TLS_RegMask ; return STI . isTargetDarwin ( ) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> unsigned PPCTargetLowering :: getPrefLoopAlignment ( MachineLoop * ML ) const { switch ( Subtarget . getDarwinDirective ( ) ) { default : break ; case PPC :: DIR_970 : case PPC :: DIR_PWR4 : case PPC :: DIR_PWR5 : case PPC :: DIR_PWR5X : case PPC :: DIR_PWR6 : case PPC :: DIR_PWR6X : case PPC :: DIR_PWR7 : case PPC :: DIR_PWR8 : case PPC :: DIR_PWR9 : { if ( ! ML ) break ; const PPCInstrInfo * TII = Subtarget . getInstrInfo ( ) ; uint64_t LoopSize = 0 ; for ( auto I = ML -> block_begin ( ) , IE = ML -> block_end ( ) ; I != IE ; ++ I ) for ( auto J = ( * I ) -> begin ( ) , JE = ( * I ) -> end ( ) ; J != JE ; ++ J ) { LoopSize += TII -> GetInstSizeInBytes ( J ) ; if ( LoopSize > 32 ) break ; } if ( LoopSize > 16 && LoopSize <= 32 ) return 5 ; break ; } } return TargetLowering :: getPrefLoopAlignment ( ML ) ; } </s>


<s> SparcSubtarget & SparcSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { UseSoftMulDiv = false ; IsV9 = false ; IsLeon = false ; V8DeprecatedInsts = false ; IsVIS = false ; IsVIS2 = false ; IsVIS3 = false ; HasHardQuad = false ; UsePopc = false ; UseSoftFloat = false ; HasNoFSMULD = false ; HasNoFMULS = false ; HasLeonCasa = false ; HasUmacSmac = false ; InsertNOPLoad = false ; FixAllFDIVSQRT = false ; DetectRoundChange = false ; HasLeonCycleCounter = false ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? "v9" : "v8" ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( ! IsV9 ) UsePopc = false ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool SIInstrInfo :: isLegalVSrcOperand ( const MachineRegisterInfo & MRI , const MCOperandInfo & OpInfo , const MachineOperand & MO ) const { if ( MO . isReg ( ) ) return isLegalRegOperand ( MRI , OpInfo , MO ) ; assert ( MO . isImm ( ) || MO . isTargetIndex ( ) || MO . isFI ( ) || MO . isGlobal ( ) ) ; return true ; } </s>

Check if MO would be a valid operand for the given operand definition OpInfo .


"OR1K DAG->DAG Pattern Instruction Selection"


<s> bool isReg ( ) const { return Kind == k_Register ; } </s>


<s> bool TLCS900DAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintCode ) { default : return true ; case 'm' : if ( ! SelectAddr ( Op , Op0 , Op1 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> rtx arm_simd_vect_par_cnst_half ( machine_mode mode , bool high ) { int nunits = GET_MODE_NUNITS ( mode ) ; rtvec v = rtvec_alloc ( nunits / 2 ) ; int high_base = nunits / 2 ; int low_base = 0 ; int base ; rtx t1 ; int i ; if ( BYTES_BIG_ENDIAN ) base = high ? low_base : high_base ; else base = high ? high_base : low_base ; for ( i = 0 ; i < nunits / 2 ; i ++ ) RTVEC_ELT ( v , i ) = GEN_INT ( base + i ) ; t1 = gen_rtx_PARALLEL ( mode , v ) ; return t1 ; } </s>

Construct and return a PARALLEL RTX vector with elements numbering the lanes of either the high ( HIGH == TRUE ) or low ( HIGH == FALSE ) half of the vector - from the perspective of the architecture . This does not line up with GCC 's perspective on lane numbers , so we end up with different masks depending on our target endian-ness . The diagram below may help . We must draw the distinction when building masks which select one half of the vector . An instruction selecting architectural low-lanes for a big-endian target , must be described using a mask selecting GCC high-lanes . Big-Endian Little-EndianGCC 0 1 2 3 3 2 1 0 | x | x | x | x | | x | x | x | x |Architecture 3 2 1 0 3 2 1 0Low Mask : { 2 , 3 } { 0 , 1 } High Mask : { 0 , 1 } { 2 , 3 }


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this , LittleEndian ) , isLittle ( LittleEndian ) , usingPBQP ( false ) { initAsmInfo ( ) ; if ( EnablePBQP && Subtarget . isCortexA57 ( ) && OL != CodeGenOpt :: None ) { usingPBQP = true ; RegisterRegAlloc :: setDefault ( createDefaultPBQPRegisterAllocator ) ; } } </s>


<s> int alpha_split_conditional_move ( enum rtx_code code , rtx dest , rtx cond , rtx t_rtx , rtx f_rtx ) { HOST_WIDE_INT t , f , diff ; machine_mode mode ; rtx target , subtarget , tmp ; mode = GET_MODE ( dest ) ; t = INTVAL ( t_rtx ) ; f = INTVAL ( f_rtx ) ; diff = t - f ; if ( ( ( code == NE || code == EQ ) && diff < 0 ) || ( code == GE || code == GT ) ) { code = reverse_condition ( code ) ; std :: swap ( t , f ) ; diff = - diff ; } subtarget = target = dest ; if ( mode != DImode ) { target = gen_lowpart ( DImode , dest ) ; if ( can_create_pseudo_p ( ) ) subtarget = gen_reg_rtx ( DImode ) ; else subtarget = target ; } if ( f == 0 && exact_log2 ( diff ) > 0 && ( diff <= 8 || alpha_tune == PROCESSOR_EV6 ) ) { tmp = gen_rtx_fmt_ee ( code , DImode , cond , const0_rtx ) ; emit_insn ( gen_rtx_SET ( copy_rtx ( subtarget ) , tmp ) ) ; tmp = gen_rtx_ASHIFT ( DImode , copy_rtx ( subtarget ) , GEN_INT ( exact_log2 ( t ) ) ) ; emit_insn ( gen_rtx_SET ( target , tmp ) ) ; } else if ( f == 0 && t == - 1 ) { tmp = gen_rtx_fmt_ee ( code , DImode , cond , const0_rtx ) ; emit_insn ( gen_rtx_SET ( copy_rtx ( subtarget ) , tmp ) ) ; emit_insn ( gen_negdi2 ( target , copy_rtx ( subtarget ) ) ) ; } else if ( diff == 1 || diff == 4 || diff == 8 ) { rtx add_op ; tmp = gen_rtx_fmt_ee ( code , DImode , cond , const0_rtx ) ; emit_insn ( gen_rtx_SET ( copy_rtx ( subtarget ) , tmp ) ) ; if ( diff == 1 ) emit_insn ( gen_adddi3 ( target , copy_rtx ( subtarget ) , GEN_INT ( f ) ) ) ; else { add_op = GEN_INT ( f ) ; if ( sext_add_operand ( add_op , mode ) ) { tmp = gen_rtx_ASHIFT ( DImode , copy_rtx ( subtarget ) , GEN_INT ( exact_log2 ( diff ) ) ) ; tmp = gen_rtx_PLUS ( DImode , tmp , add_op ) ; emit_insn ( gen_rtx_SET ( target , tmp ) ) ; } else return 0 ; } } else return 0 ; return 1 ; } </s>

Simplify a conditional move of two constants into a setcc with arithmetic . This is done with a splitter since combine would just undo the work if done during code generation . It also catches cases we would n't have before cse .


"optionally flag setting instruction missing optional def operand"

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


<s> void MipsTargetLowering :: AdjustInstrPostInstrSelection ( MachineInstr & MI , SDNode * Node ) const { switch ( MI . getOpcode ( ) ) { default : return ; case Mips :: JALR : case Mips :: JALRPseudo : case Mips :: JALR64 : case Mips :: JALR64Pseudo : case Mips :: JALR16_MM : case Mips :: JALRC16_MMR6 : case Mips :: TAILCALLREG : case Mips :: TAILCALLREG64 : case Mips :: TAILCALLR6REG : case Mips :: TAILCALL64R6REG : case Mips :: TAILCALLREG_MM : case Mips :: TAILCALLREG_MMR6 : { if ( ! EmitJalrReloc || Subtarget . inMips16Mode ( ) || ! isPositionIndependent ( ) || Node -> getNumOperands ( ) < 1 || Node -> getOperand ( 0 ) . getNumOperands ( ) < 2 ) { return ; } const SDValue TargetAddr = Node -> getOperand ( 0 ) . getOperand ( 1 ) ; StringRef Sym ; if ( const GlobalAddressSDNode * G = dyn_cast_or_null < const GlobalAddressSDNode > ( TargetAddr ) ) { Sym = G -> getGlobal ( ) -> getName ( ) ; } else if ( const ExternalSymbolSDNode * ES = dyn_cast_or_null < const ExternalSymbolSDNode > ( TargetAddr ) ) { Sym = ES -> getSymbol ( ) ; } if ( Sym . empty ( ) ) return ; MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; MCSymbol * S = MF -> getContext ( ) . getOrCreateSymbol ( Sym ) ; MI . addOperand ( MachineOperand :: CreateMCSymbol ( S , MipsII :: MO_JALR ) ) ; } } } </s>

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


<s> virtual const TOYRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static void cris_init_libfuncs ( void ) { set_optab_libfunc ( smul_optab , SImode , "__Mul" ) ; set_optab_libfunc ( sdiv_optab , SImode , "__Div" ) ; set_optab_libfunc ( udiv_optab , SImode , "__Udiv" ) ; set_optab_libfunc ( smod_optab , SImode , "__Mod" ) ; set_optab_libfunc ( umod_optab , SImode , "__Umod" ) ; if ( TARGET_ATOMICS_MAY_CALL_LIBFUNCS ) { set_optab_libfunc ( sync_compare_and_swap_optab , SImode , "__cris_atcmpxchgr32" ) ; set_optab_libfunc ( sync_compare_and_swap_optab , HImode , "__cris_atcmpxchgr16" ) ; } } </s>

Rename the function calls for integer multiply and divide .


<s> bool HexagonTargetMachine :: addPreRegAlloc ( PassManagerBase & PM ) { if ( ! DisableHardwareLoops ) { PM . add ( createHexagonHardwareLoops ( ) ) ; } return false ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> bool MipsSEInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock & MBB = * MI -> getParent ( ) ; bool isMicroMips = Subtarget . inMicroMipsMode ( ) ; unsigned Opc ; switch ( MI -> getDesc ( ) . getOpcode ( ) ) { default : return false ; case Mips :: RetRA : expandRetRA ( MBB , MI ) ; break ; case Mips :: ERet : expandERet ( MBB , MI ) ; break ; case Mips :: PseudoMFHI : Opc = isMicroMips ? Mips :: MFHI16_MM : Mips :: MFHI ; expandPseudoMFHiLo ( MBB , MI , Opc ) ; break ; case Mips :: PseudoMFLO : Opc = isMicroMips ? Mips :: MFLO16_MM : Mips :: MFLO ; expandPseudoMFHiLo ( MBB , MI , Opc ) ; break ; case Mips :: PseudoMFHI64 : expandPseudoMFHiLo ( MBB , MI , Mips :: MFHI64 ) ; break ; case Mips :: PseudoMFLO64 : expandPseudoMFHiLo ( MBB , MI , Mips :: MFLO64 ) ; break ; case Mips :: PseudoMTLOHI : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO , Mips :: MTHI , false ) ; break ; case Mips :: PseudoMTLOHI64 : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO64 , Mips :: MTHI64 , false ) ; break ; case Mips :: PseudoMTLOHI_DSP : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO_DSP , Mips :: MTHI_DSP , true ) ; break ; case Mips :: PseudoCVT_S_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_D32_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_D32_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_S_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_L , Mips :: DMTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_W , Mips :: MTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_L , Mips :: DMTC1 , true ) ; break ; case Mips :: BuildPairF64 : expandBuildPairF64 ( MBB , MI , false ) ; break ; case Mips :: BuildPairF64_64 : expandBuildPairF64 ( MBB , MI , true ) ; break ; case Mips :: ExtractElementF64 : expandExtractElementF64 ( MBB , MI , false ) ; break ; case Mips :: ExtractElementF64_64 : expandExtractElementF64 ( MBB , MI , true ) ; break ; case Mips :: MIPSeh_return32 : case Mips :: MIPSeh_return64 : expandEhReturn ( MBB , MI ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> bool RISCVRegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , unsigned Reg , int & FrameIdx ) const { const auto * RVFI = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; if ( ! RVFI -> useSaveRestoreLibCalls ( ) ) return false ; auto FII = FixedCSRFIMap . find ( Reg ) ; if ( FII == FixedCSRFIMap . end ( ) ) return false ; FrameIdx = FII -> second ; return true ; } </s>

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register .


<s> int SystemZTTIImpl :: getIntrinsicInstrCost ( Intrinsic :: ID ID , Type * RetTy , ArrayRef < Type * > Tys , FastMathFlags FMF , unsigned ScalarizationCostPassed , const Instruction * I ) { int Cost = getVectorIntrinsicInstrCost ( ID , RetTy ) ; if ( Cost != - 1 ) return Cost ; return BaseT :: getIntrinsicInstrCost ( ID , RetTy , Tys , FMF , ScalarizationCostPassed , I ) ; } </s>


<s> SDNode * PPCDAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * PPCSubTarget -> getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; const Module * M = MF -> getFunction ( ) . getParent ( ) ; DebugLoc dl ; if ( PPCLowering -> getPointerTy ( CurDAG -> getDataLayout ( ) ) == MVT :: i32 ) { if ( PPCSubTarget -> isTargetELF ( ) ) { GlobalBaseReg = PPC :: R30 ; if ( ! PPCSubTarget -> isSecurePlt ( ) && M -> getPICLevel ( ) == PICLevel :: SmallPIC ) { BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MoveGOTtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; MF -> getInfo < PPCFunctionInfo > ( ) -> setUsesPICBase ( true ) ; } else { BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; Register TempReg = RegInfo -> createVirtualRegister ( & PPC :: GPRCRegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: UpdateGBR ) , GlobalBaseReg ) . addReg ( TempReg , RegState :: Define ) . addReg ( GlobalBaseReg ) ; MF -> getInfo < PPCFunctionInfo > ( ) -> setUsesPICBase ( true ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: GPRC_and_GPRC_NOR0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; } } else { MF -> getInfo < PPCFunctionInfo > ( ) -> setShrinkWrapDisabled ( true ) ; GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: G8RC_and_G8RC_NOX0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR8 ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR8 ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , PPCLowering -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

PowerPC PPC PPC PPC MVT::i32 PPC PPC::R30 PPC PPC::MoveGOTtoLR PPC::MFLR PPC PPC::MovePCtoLR PPC::MFLR PPC::GPRCRegClass PPC::UpdateGBR PPC PPC::GPRC_and_GPRC_NOR0RegClass PPC::MovePCtoLR PPC::MFLR PPC PPC::G8RC_and_G8RC_NOX0RegClass PPC::MovePCtoLR8 PPC::MFLR8 PPC


<s> static tree sparc_d_handle_target_float_abi ( void ) { const char * abi ; if ( TARGET_FPU ) abi = "hard" ; else abi = "soft" ; return build_string_literal ( strlen ( abi ) + 1 , abi ) ; } </s>

Handle a call to ` __traits ( getTargetInfo , `` floatAbi '' ) ' .


<s> static inline unsigned int cr16_ret_register ( void ) { return 0 ; } </s>

Returns register number for function return value .


<s> const char * RISCVTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( RISCVISD :: NodeType ) Opcode ) { case RISCVISD :: FIRST_NUMBER : break ; case RISCVISD :: RET_FLAG : return "RISCVISD::RET_FLAG" ; case RISCVISD :: URET_FLAG : return "RISCVISD::URET_FLAG" ; case RISCVISD :: SRET_FLAG : return "RISCVISD::SRET_FLAG" ; case RISCVISD :: MRET_FLAG : return "RISCVISD::MRET_FLAG" ; case RISCVISD :: CALL : return "RISCVISD::CALL" ; case RISCVISD :: SELECT_CC : return "RISCVISD::SELECT_CC" ; case RISCVISD :: BuildPairF64 : return "RISCVISD::BuildPairF64" ; case RISCVISD :: SplitF64 : return "RISCVISD::SplitF64" ; case RISCVISD :: TAIL : return "RISCVISD::TAIL" ; case RISCVISD :: SLLW : return "RISCVISD::SLLW" ; case RISCVISD :: SRAW : return "RISCVISD::SRAW" ; case RISCVISD :: SRLW : return "RISCVISD::SRLW" ; case RISCVISD :: DIVW : return "RISCVISD::DIVW" ; case RISCVISD :: DIVUW : return "RISCVISD::DIVUW" ; case RISCVISD :: REMUW : return "RISCVISD::REMUW" ; case RISCVISD :: FMV_W_X_RV64 : return "RISCVISD::FMV_W_X_RV64" ; case RISCVISD :: FMV_X_ANYEXTW_RV64 : return "RISCVISD::FMV_X_ANYEXTW_RV64" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> void emitSymbolDesc ( MCSymbol * Symbol , unsigned DescValue ) override { } </s>


<s> bool X86TargetLowering :: canMergeStoresTo ( unsigned AddressSpace , EVT MemVT , const MachineFunction & MF ) const { bool NoFloat = MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; if ( NoFloat ) { unsigned MaxIntSize = Subtarget . is64Bit ( ) ? 64 : 32 ; return ( MemVT . getSizeInBits ( ) <= MaxIntSize ) ; } if ( MemVT . getSizeInBits ( ) > Subtarget . getPreferVectorWidth ( ) ) return false ; return true ; } </s>

Returns if it 's reasonable to merge stores to MemVT size .


<s> bool AlphaTargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> rtx find_addr_reg ( rtx addr ) { while ( GET_CODE ( addr ) == PLUS ) { if ( GET_CODE ( XEXP ( addr , 0 ) ) == REG && REGNO ( XEXP ( addr , 0 ) ) != 0 ) addr = XEXP ( addr , 0 ) ; else if ( GET_CODE ( XEXP ( addr , 1 ) ) == REG && REGNO ( XEXP ( addr , 1 ) ) != 0 ) addr = XEXP ( addr , 1 ) ; else if ( CONSTANT_P ( XEXP ( addr , 0 ) ) ) addr = XEXP ( addr , 1 ) ; else if ( CONSTANT_P ( XEXP ( addr , 1 ) ) ) addr = XEXP ( addr , 0 ) ; else gcc_unreachable ( ) ; } gcc_assert ( GET_CODE ( addr ) == REG && REGNO ( addr ) != 0 ) ; return addr ; } </s>

Return a REG that occurs in ADDR with coefficient 1 . ADDR can be effectively incremented by incrementing REG . r0 is special and we must not select it as an address register by this routine since our caller will try to increment the returned register via an `` la '' instruction .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"MOV to LEA transformation pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> static int rs6000_cpu_name_lookup ( const char * name ) { size_t i ; if ( name != NULL ) { for ( i = 0 ; i < ARRAY_SIZE ( processor_target_table ) ; i ++ ) if ( ! strcmp ( name , processor_target_table [ i ] . name ) ) return ( int ) i ; } return - 1 ; } </s>

Look up a processor name for -mcpu=xxx and -mtune=xxx . Return -1 if the name is invalid .


<s> int tls_call_delay ( rtx trial ) { rtx pat ; if ( TARGET_GNU_TLS || ! TARGET_TLS ) return 1 ; pat = PATTERN ( trial ) ; if ( GET_CODE ( pat ) == SET && GET_CODE ( SET_SRC ( pat ) ) == PLUS ) { rtx unspec = XEXP ( SET_SRC ( pat ) , 1 ) ; if ( GET_CODE ( unspec ) == UNSPEC && ( XINT ( unspec , 1 ) == UNSPEC_TLSGD || XINT ( unspec , 1 ) == UNSPEC_TLSLDM ) ) return 0 ; } return 1 ; } </s>

Return nonzero if TRIAL can go into the call delay slot .


"MachineModuleInfo should always be available"

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static bool examine_argument ( machine_mode mode , const_tree type , int in_return , int * int_nregs , int * sse_nregs ) { enum x86_64_reg_class regclass [ MAX_CLASSES ] ; int n = classify_argument ( mode , type , regclass , 0 ) ; * int_nregs = 0 ; * sse_nregs = 0 ; if ( ! n ) return true ; for ( n -- ; n >= 0 ; n -- ) switch ( regclass [ n ] ) { case X86_64_INTEGER_CLASS : case X86_64_INTEGERSI_CLASS : ( * int_nregs ) ++ ; break ; case X86_64_SSE_CLASS : case X86_64_SSEHF_CLASS : case X86_64_SSESF_CLASS : case X86_64_SSEDF_CLASS : ( * sse_nregs ) ++ ; break ; case X86_64_NO_CLASS : case X86_64_SSEUP_CLASS : break ; case X86_64_X87_CLASS : case X86_64_X87UP_CLASS : case X86_64_COMPLEX_X87_CLASS : if ( ! in_return ) return true ; break ; case X86_64_MEMORY_CLASS : gcc_unreachable ( ) ; } return false ; } </s>

Examine the argument and return set number of register required in each class . Return 0 iff parameter should be passed in memory .


<s> void rs6000_asm_output_opcode ( FILE * stream ) { if ( prepend_p_to_next_insn ) { fprintf ( stream , "p" ) ; prepend_p_to_next_insn = false ; } return ; } </s>

Define ASM_OUTPUT_OPCODE to do anything special before emitting an opcode . We use it to emit a ' p ' for prefixed insns that is set in FINAL_PRESCAN_INSN .


<s> unsigned SPURegisterInfo :: getRARegister ( ) const { return SPU :: R0 ; } </s>

This method should return the register where the return address can be found .


"function attributes %qs, %qs and %qs are mutually"

Sanity cheching for above function attributes .


<s> bool JVMAsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const { return false ; } </s>


"getIntImmCost can only estimate cost of materialising integers"

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> void FISCFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = computeStackSize ( MF ) ; if ( ! StackSize ) return ; unsigned StackReg = FISC :: SP ; unsigned OffsetReg = materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ; if ( OffsetReg ) { BuildMI ( MBB , MBBI , dl , TII . get ( FISC :: SUBrr ) , StackReg ) . addReg ( StackReg ) . addReg ( OffsetReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( FISC :: SUBri ) , StackReg ) . addReg ( StackReg ) . addImm ( StackSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

FISC FISC FISC::SP FISC::SUBrr FISC::SUBri


<s> bool HexagonMCChecker :: check ( bool FullCheck ) { bool chkP = checkPredicates ( ) ; bool chkNV = checkNewValues ( ) ; bool chkR = checkRegisters ( ) ; bool chkRRO = checkRegistersReadOnly ( ) ; checkRegisterCurDefs ( ) ; bool chkS = checkSolo ( ) ; bool chkSh = true ; if ( FullCheck ) chkSh = checkShuffle ( ) ; bool chkSl = true ; if ( FullCheck ) chkSl = checkSlots ( ) ; bool chkAXOK = checkAXOK ( ) ; bool chkCofMax1 = checkCOFMax1 ( ) ; bool chkHWLoop = checkHWLoop ( ) ; bool chk = chkP && chkNV && chkR && chkRRO && chkS && chkSh && chkSl && chkAXOK && chkCofMax1 && chkHWLoop ; return chk ; } </s>

Check if the constraints are satisfiable .


<s> bool HSAILTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { return ( VT == EVT ( MVT :: f32 ) || VT == EVT ( MVT :: f64 ) ) ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> void SHUXIFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


<s> const SICRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
char
*
output_call
(
rtx_insn
*
insn
,
rtx
*
operands
,
int
dest_operand_number
,
int
cookie_operand_number
)
{
static
char
buf
[
256
]
;
if
(
darwin_emit_branch_islands
&&
GET_CODE
(
operands
[
dest_operand_number
]
)
==
SYMBOL_REF
&&
(
INTVAL
(
operands
[
cookie_operand_number
]
)
&
CALL_LONG
)
)
{
tree
labelname
;
tree
funname
=
get_identifier
(
XSTR
(
operands
[
dest_operand_number
]
,
0
)
)
;
if
(
no_previous_def
(
funname
)
)
{
rtx
label_rtx
=
gen_label_rtx
(
)
;
char
*
label_buf
,
temp_buf
[
256
]
;
ASM_GENERATE_INTERNAL_LABEL
(
temp_buf
,
"L"
,
CODE_LABEL_NUMBER
(
label_rtx
)
)
;
label_buf
=
temp_buf
[
0
]
==
'*'
temp_buf
+
1
:
temp_buf
;
labelname
=
get_identifier
(
label_buf
)
;
add_compiler_branch_island
(
labelname
,
funname
,
insn_line
(
insn
)
)
;
}
else
labelname
=
get_prev_label
(
funname
)
;
sprintf
(
buf
,
"jbsr %%z%d,%.246s"
,
dest_operand_number
,
IDENTIFIER_POINTER
(
labelname
)
)
;
}
else
sprintf
(
buf
,
"bl %%z%d"
,
dest_operand_number
)
;
return
buf
;
}
</s>

INSN is either a function call or a millicode call . It may have an unconditional jump in its delay slot . CALL_DEST is the routine we are calling .


<s> SDValue AMDGPUTargetLowering :: SplitVectorStore ( SDValue Op , SelectionDAG & DAG ) const { StoreSDNode * Store = cast < StoreSDNode > ( Op ) ; SDValue Val = Store -> getValue ( ) ; EVT VT = Val . getValueType ( ) ; if ( VT . getVectorNumElements ( ) == 2 ) return scalarizeVectorStore ( Store , DAG ) ; EVT MemVT = Store -> getMemoryVT ( ) ; SDValue Chain = Store -> getChain ( ) ; SDValue BasePtr = Store -> getBasePtr ( ) ; SDLoc SL ( Op ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Val , SL , LoVT , HiVT ) ; EVT PtrVT = BasePtr . getValueType ( ) ; SDValue HiPtr = DAG . getNode ( ISD :: ADD , SL , PtrVT , BasePtr , DAG . getConstant ( LoMemVT . getStoreSize ( ) , SL , PtrVT ) ) ; const MachinePointerInfo & SrcValue = Store -> getMemOperand ( ) -> getPointerInfo ( ) ; unsigned BaseAlign = Store -> getAlignment ( ) ; unsigned Size = LoMemVT . getStoreSize ( ) ; unsigned HiAlign = MinAlign ( BaseAlign , Size ) ; SDValue LoStore = DAG . getTruncStore ( Chain , SL , Lo , BasePtr , SrcValue , LoMemVT , BaseAlign , Store -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue HiStore = DAG . getTruncStore ( Chain , SL , Hi , HiPtr , SrcValue . getWithOffset ( Size ) , HiMemVT , HiAlign , Store -> getMemOperand ( ) -> getFlags ( ) ) ; return DAG . getNode ( ISD :: TokenFactor , SL , MVT :: Other , LoStore , HiStore ) ; } </s>

Split a vector store into 2 stores of half the vector .

AMDGPU AMDGPU 2 ISD::ADD ISD::TokenFactor MVT::Other


<s>
bool
MipsAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
MCAsmParser
&
Parser
=
getParser
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ParseInstruction\n"
)
;
getTargetStreamer
(
)
.
forbidModuleDirective
(
)
;
if
(
!
mnemonicIsValid
(
Name
,
0
)
)
{
uint64_t
FBS
=
ComputeAvailableFeatures
(
getSTI
(
)
.
getFeatureBits
(
)
)
;
std
::
string
Suggestion
=
MipsMnemonicSpellCheck
(
Name
,
FBS
)
;
return
Error
(
NameLoc
,
"unknown instruction"
+
Suggestion
)
;
}
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Name
,
NameLoc
,
*
this
)
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
parseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
&&
parseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
)
{
if
(
parseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
}
else
if
(
getLexer
(
)
.
is
(
AsmToken
::
LParen
)
&&
parseParenSuffix
(
Name
,
Operands
)
)
return
true
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Mips
Mips
"ParseInstruction\n"
0
Mips
"unknown instruction"
MipsOperand::CreateToken
"unexpected token in argument list"
"unexpected token in argument list"
"unexpected token in argument list"


<s> opt_machine_mode arm_mode_to_pred_mode ( machine_mode mode ) { switch ( GET_MODE_NUNITS ( mode ) ) { case 16 : return V16BImode ; case 8 : return V8BImode ; case 4 : return V4BImode ; case 2 : return V2QImode ; } return opt_machine_mode ( ) ; } </s>

Return the mode for the MVE vector of predicates corresponding to MODE .


"the ABI of passing aggregates with %d-byte alignment"

If defined , a C expression that gives the alignment boundary , in bits , of an argument with the specified mode and type . If it is not defined , PARM_BOUNDARY is used for all arguments . V.4 wants long longs and doubles to be double word aligned . Just testing the mode size is a boneheaded way to do this as it means that other types such as complex int are also double word aligned . However , we 're stuck with this because changing the ABI might break existing library interfaces . Quadword align Altivec/VSX vectors . Quadword align large synthetic vector types .


"WebAssembly hasn't implemented computed gotos"

LowerOperation - Provide custom lowering hooks for some operations .


<s> StackOffset SystemZFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { StackOffset Offset = TargetFrameLowering :: getFrameIndexReference ( MF , FI , FrameReg ) ; return Offset + StackOffset :: getFixed ( SystemZMC :: CallFrameSize ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


"-fsplit-stack does not support fastcall with "

"-fsplit-stack does not support 2 register "

"-fsplit-stack does not support 3 register parameters"

Return a scratch register to use in the split stack prologue . The split stack prologue is used for -fsplit-stack . It is the first instructions in the function , even before the regular prologue . The scratch register can be any caller-saved register which is not used for parameters or for the static chain .


<s>
bool
RelooperAnalysis
::
runOnFunction
(
Function
&
F
)
{
DEBUG
(
dbgs
(
)
<<
"Relooping function '"
<<
F
.
getName
(
)
<<
"'\n"
)
;
RelooperAlgorithm
R
;
std
::
map
<
const
BasicBlock
*
,
Block
*
>
BB2B
;
std
::
map
<
const
Block
*
,
const
BasicBlock
*
>
B2BB
;
for
(
const
BasicBlock
&
BB
:
F
)
{
Block
*
B
=
new
Block
(
BB
.
getName
(
)
.
str
(
)
.
data
(
)
,
nullptr
)
;
R
.
AddBlock
(
B
)
;
assert
(
BB2B
.
find
(
&
BB
)
==
BB2B
.
end
(
)
&&
"Inserting the same block twice"
)
;
assert
(
B2BB
.
find
(
B
)
==
B2BB
.
end
(
)
&&
"Inserting the same block twice"
)
;
BB2B
[
&
BB
]
=
B
;
B2BB
[
B
]
=
&
BB
;
}
for
(
Block
*
B
:
R
.
Blocks
)
{
const
BasicBlock
*
BB
=
B2BB
[
B
]
;
for
(
const
BasicBlock
*
Successor
:
successors
(
BB
)
)
B
->
AddBranchTo
(
BB2B
[
Successor
]
,
nullptr
,
nullptr
)
;
}
R
.
Calculate
(
BB2B
[
&
F
.
getEntryBlock
(
)
]
)
;
return
false
;
}
</s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .

WebAssembly
"Relooping function '"
"'\n"
"Inserting the same block twice"
"Inserting the same block twice"


"Unimplemented opcode in EncodeInstruction(). Maybe you tried to emit '(p0) add r0=r0,0' ?"

"Pseudo opcode found in EncodeInstruction()"

Encode the given Inst to bytes and append to CB .


<s> unsigned combineRepeatedFPDivisors ( ) const override { return 2 ; } </s>

Indicate whether this target prefers to combine FDIVs with the same divisor .


<s> static bool sparc_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { if ( TARGET_ARCH32 ) return ( TYPE_MODE ( type ) == BLKmode || TYPE_MODE ( type ) == TFmode || ( TREE_CODE ( type ) == VECTOR_TYPE && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > 8 ) ) ; else return ( TYPE_MODE ( type ) == BLKmode && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > 32 ) ; } </s>

Handle the TARGET_RETURN_IN_MEMORY target hook . Specify whether to return the return value in memory .


<s>
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
SNESTargetLowering
::
getRegForInlineAsmConstraint
(
const
TargetRegisterInfo
*
TRI
,
StringRef
Constraint
,
MVT
VT
)
const
{
auto
STI
=
static_cast
<
const
SNESTargetMachine
&
>
(
this
->
getTargetMachine
(
)
)
.
getSubtargetImpl
(
)
;
if
(
Constraint
.
size
(
)
==
1
)
{
switch
(
Constraint
[
0
]
)
{
case
'a'
:
return
std
::
make_pair
(
0U
,
&
SNES
::
MainLoRegsRegClass
)
;
case
'b'
:
return
std
::
make_pair
(
0U
,
&
SNES
::
MainRegsRegClass
)
;
case
'd'
:
return
std
::
make_pair
(
0U
,
&
SNES
::
MainLoRegsRegClass
)
;
case
'l'
:
return
std
::
make_pair
(
0U
,
&
SNES
::
MainRegsRegClass
)
;
case
'e'
:
return
std
::
make_pair
(
0U
,
&
SNES
::
IndexRegsRegClass
)
;
case
'q'
:
return
std
::
make_pair
(
0U
,
&
SNES
::
StackPointerRegsRegClass
)
;
case
'r'
:
if
(
VT
==
MVT
::
i8
)
return
std
::
make_pair
(
0U
,
&
SNES
::
MainRegsRegClass
)
;
assert
(
VT
==
MVT
::
i16
&&
"inline asm constraint too large"
)
;
return
std
::
make_pair
(
0U
,
&
SNES
::
MainRegsRegClass
)
;
case
't'
:
return
std
::
make_pair
(
unsigned
(
SNES
::
A
)
,
&
SNES
::
MainRegsRegClass
)
;
case
'w'
:
return
std
::
make_pair
(
0U
,
&
SNES
::
MainRegsRegClass
)
;
case
'x'
:
case
'X'
:
return
std
::
make_pair
(
unsigned
(
SNES
::
X
)
,
&
SNES
::
IndexRegsRegClass
)
;
case
'y'
:
case
'Y'
:
return
std
::
make_pair
(
unsigned
(
SNES
::
Y
)
,
&
SNES
::
IndexRegsRegClass
)
;
case
'z'
:
case
'Z'
:
return
std
::
make_pair
(
unsigned
(
SNES
::
A
)
,
&
SNES
::
IndexRegsRegClass
)
;
default
:
break
;
}
}
return
TargetLowering
::
getRegForInlineAsmConstraint
(
STI
->
getRegisterInfo
(
)
,
Constraint
,
VT
)
;
}
</s>

Given a physical register constraint ( e.g .


<s>
bool
AArch64LegalizerInfo
::
legalizeCustom
(
MachineInstr
&
MI
,
MachineRegisterInfo
&
MRI
,
MachineIRBuilder
&
MIRBuilder
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
return
false
;
case
TargetOpcode
::
G_VAARG
:
return
legalizeVaArg
(
MI
,
MRI
,
MIRBuilder
)
;
}
llvm_unreachable
(
"expected switch to return"
)
;
}
</s>

Called for instructions with the Custom LegalizationAction .


<s> bool X86PassConfig :: addInstSelector ( ) { addPass ( createX86ISelDag ( getX86TargetMachine ( ) , getOptLevel ( ) ) ) ; if ( TM -> getTargetTriple ( ) . isOSBinFormatELF ( ) && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createCleanupLocalDynamicTLSPass ( ) ) ; addPass ( createX86GlobalBaseRegPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void ARCExpandPseudos :: expandCTLZ ( MachineFunction & MF , MachineBasicBlock :: iterator MII ) { MachineInstr & MI = * MII ; const MachineOperand & Dest = MI . getOperand ( 0 ) ; const MachineOperand & Src = MI . getOperand ( 1 ) ; Register Ra = MF . getRegInfo ( ) . createVirtualRegister ( & ARC :: GPR32RegClass ) ; Register Rb = MF . getRegInfo ( ) . createVirtualRegister ( & ARC :: GPR32RegClass ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , TII -> get ( ARC :: FLS_f_rr ) , Ra ) . add ( Src ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , TII -> get ( ARC :: MOV_cc_ru6 ) , Rb ) . addImm ( 32 ) . addImm ( ARCCC :: EQ ) . addReg ( Ra ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , TII -> get ( ARC :: RSUB_cc_rru6 ) ) . add ( Dest ) . addImm ( 31 ) . addImm ( ARCCC :: NE ) . addReg ( Rb ) ; MI . eraseFromParent ( ) ; } </s>


<s> static bool expand_perm_with_vstbrq ( const struct expand_vec_perm_d & d ) { if ( TARGET_VXE2 && d . op0 == d . op1 && is_reverse_perm_mask ( d ) && d . vmode == V16QImode ) { if ( d . testing_p ) return true ; emit_insn ( gen_eltswapv16qi ( d . target , d . op0 ) ) ; return true ; } return false ; } </s>

If we reverse a byte-vector this is the same as byte reversing it which can be done with vstbrq .


<s> static int mips_sign_extend_cost ( machine_mode mode , rtx op ) { if ( MEM_P ( op ) ) return 0 ; if ( TARGET_64BIT && mode == DImode && GET_MODE ( op ) == SImode ) return 0 ; if ( ISA_HAS_SEB_SEH || GENERATE_MIPS16E ) return COSTS_N_INSNS ( 1 ) ; return COSTS_N_INSNS ( TARGET_MIPS16 ? 4 : 2 ) ; } </s>

Return the cost of sign-extending OP to mode MODE , not including the cost of OP itself .


<s> bool ARCRegisterInfo :: needsFrameMoves ( const MachineFunction & MF ) { return MF . getMMI ( ) . hasDebugInfo ( ) || MF . getFunction ( ) . needsUnwindTableEntry ( ) ; } </s>


<s> static int sequent_regs_live ( void ) { int live_seq = 0 ; int cur_seq = 0 ; for ( int reg = 0 ; reg <= LAST_CALLEE_SAVED_REG ; ++ reg ) { if ( fixed_regs [ reg ] ) { if ( live_seq != 0 ) return 0 ; else continue ; } if ( ! call_used_or_fixed_reg_p ( reg ) ) { if ( df_regs_ever_live_p ( reg ) ) { ++ live_seq ; ++ cur_seq ; } else cur_seq = 0 ; } } if ( ! frame_pointer_needed ) { if ( df_regs_ever_live_p ( REG_Y ) ) { ++ live_seq ; ++ cur_seq ; } else cur_seq = 0 ; if ( df_regs_ever_live_p ( REG_Y + 1 ) ) { ++ live_seq ; ++ cur_seq ; } else cur_seq = 0 ; } else { cur_seq += 2 ; live_seq += 2 ; } return ( cur_seq == live_seq ) ? live_seq : 0 ; } </s>

This function checks sequence of live registers


"Transactional execution builtins not enabled (-mhtm)\n"

Expand an expression EXP that calls a built-in function , with result going to TARGET if that 's convenient ( and in mode MODE if that 's convenient ) . SUBTARGET may be used as the target for computing one of EXP 's operands . IGNORE is nonzero if the value is to be ignored .


<s> static rtx pru_to_int_mode ( rtx x ) { machine_mode mode = GET_MODE ( x ) ; return VOIDmode == mode ? x : simplify_gen_subreg ( int_mode_for_mode ( mode ) . require ( ) , x , mode , 0 ) ; } </s>

Access some RTX as INT_MODE . If X is a CONST_FIXED we can get the bit representation of X by `` casting '' it to CONST_INT .


<s>
MCSection
*
getExplicitSectionGlobal
(
const
GlobalObject
*
GO
,
SectionKind
Kind
,
const
TargetMachine
&
TM
)
const
override
{
llvm_unreachable
(
"Not supported!"
)
;
}
</s>

Targets should implement this method to assign a section to globals with an explicit section specfied .


<s> bool HexagonExpandCondsets :: isPredicable ( MachineInstr * MI ) { if ( HII -> isPredicated ( * MI ) || ! HII -> isPredicable ( * MI ) ) return false ; if ( MI -> hasUnmodeledSideEffects ( ) || MI -> mayStore ( ) ) return false ; bool HasDef = false ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) ) continue ; if ( HasDef ) return false ; HasDef = true ; } for ( auto & Mo : MI -> memoperands ( ) ) if ( Mo -> isVolatile ( ) || Mo -> isAtomic ( ) ) return false ; return true ; } </s>

Return true if the specified instruction can be predicated .


<s> static int tilegx_mode_rep_extended ( machine_mode mode , machine_mode mode_rep ) { if ( mode == SImode && mode_rep == DImode ) return SIGN_EXTEND ; return UNKNOWN ; } </s>


<s> void XtensaRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Patmos Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static reg_class_t ix86_preferred_reload_class ( rtx x , reg_class_t regclass ) { machine_mode mode = GET_MODE ( x ) ; if ( regclass == NO_REGS ) return NO_REGS ; if ( x == CONST0_RTX ( mode ) ) return regclass ; if ( CONSTANT_P ( x ) && ( MAYBE_MMX_CLASS_P ( regclass ) || MAYBE_SSE_CLASS_P ( regclass ) || MAYBE_MASK_CLASS_P ( regclass ) ) ) return NO_REGS ; if ( CONST_DOUBLE_P ( x ) ) { if ( INTEGER_CLASS_P ( regclass ) ) return regclass ; if ( IS_STACK_MODE ( mode ) && standard_80387_constant_p ( x ) > 0 ) { if ( FLOAT_CLASS_P ( regclass ) ) return FLOAT_REGS ; } return NO_REGS ; } if ( SSE_FLOAT_MODE_P ( mode ) && TARGET_SSE_MATH ) return SSE_CLASS_P ( regclass ) ? regclass : NO_REGS ; if ( GET_CODE ( x ) == PLUS ) return INTEGER_CLASS_P ( regclass ) ? regclass : NO_REGS ; if ( GET_MODE ( x ) == QImode && ! CONSTANT_P ( x ) ) { if ( Q_CLASS_P ( regclass ) ) return regclass ; else if ( reg_class_subset_p ( Q_REGS , regclass ) ) return Q_REGS ; else if ( MASK_CLASS_P ( regclass ) ) return regclass ; else return NO_REGS ; } return regclass ; } </s>

Put float CONST_DOUBLE in the constant pool instead of fp regs . QImode must go into class Q_REGS . Narrow ALL_REGS to GENERAL_REGS . This supports allowing movsf and movdf to do mem-to-mem moves through integer regs .


<s> virtual bool track ( const TargetRegisterClass * RC ) const { return true ; } </s>

Track the reference to metadata for DebugValueUser .


<s> static section * xtensa_select_rtx_section ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ATTRIBUTE_UNUSED , unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED ) { return function_section ( current_function_decl ) ; } </s>

The literal pool stays with the function .


<s> static int mips16_rewrite_pool_refs ( rtx * x , void * data ) { struct mips16_constant_pool * pool = data ; if ( GET_CODE ( * x ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( * x ) ) * x = gen_rtx_LABEL_REF ( Pmode , add_constant ( pool , get_pool_constant ( * x ) , get_pool_mode ( * x ) ) ) ; return 0 ; } </s>

Rewrite * X so that constant pool references refer to the constant 's label instead . DATA points to the constant pool structure .


<s> bool arc_expand_movmem ( rtx * operands ) { rtx dst = operands [ 0 ] ; rtx src = operands [ 1 ] ; rtx dst_addr , src_addr ; HOST_WIDE_INT size ; int align = INTVAL ( operands [ 3 ] ) ; unsigned n_pieces ; int piece = align ; rtx store [ 2 ] ; rtx tmpx [ 2 ] ; int i ; if ( ! CONST_INT_P ( operands [ 2 ] ) ) return false ; size = INTVAL ( operands [ 2 ] ) ; if ( align >= 4 ) { if ( TARGET_LL64 ) n_pieces = ( size + 4 ) / 8U + ( ( size >> 1 ) & 1 ) + ( size & 1 ) ; else n_pieces = ( size + 2 ) / 4U + ( size & 1 ) ; } else if ( align == 2 ) n_pieces = ( size + 1 ) / 2U ; else n_pieces = size ; if ( n_pieces >= ( unsigned int ) ( optimize_size ? 3 : 15 ) ) return false ; if ( TARGET_LL64 && ( piece >= 4 ) && ( size >= 8 ) ) piece = 8 ; else if ( piece > 4 ) piece = 4 ; dst_addr = force_offsettable ( XEXP ( operands [ 0 ] , 0 ) , size , 0 ) ; src_addr = force_offsettable ( XEXP ( operands [ 1 ] , 0 ) , size , 0 ) ; store [ 0 ] = store [ 1 ] = NULL_RTX ; tmpx [ 0 ] = tmpx [ 1 ] = NULL_RTX ; for ( i = 0 ; size > 0 ; i ^= 1 , size -= piece ) { rtx tmp ; machine_mode mode ; while ( piece > size ) piece >>= 1 ; mode = smallest_mode_for_size ( piece * BITS_PER_UNIT , MODE_INT ) ; if ( 0 && tmpx [ i ] && GET_MODE ( tmpx [ i ] ) == mode ) tmp = tmpx [ i ] ; else tmpx [ i ] = tmp = gen_reg_rtx ( mode ) ; dst_addr = force_offsettable ( dst_addr , piece , 1 ) ; src_addr = force_offsettable ( src_addr , piece , 1 ) ; if ( store [ i ] ) emit_insn ( store [ i ] ) ; emit_move_insn ( tmp , change_address ( src , mode , src_addr ) ) ; store [ i ] = gen_move_insn ( change_address ( dst , mode , dst_addr ) , tmp ) ; dst_addr = plus_constant ( Pmode , dst_addr , piece ) ; src_addr = plus_constant ( Pmode , src_addr , piece ) ; } if ( store [ i ] ) emit_insn ( store [ i ] ) ; if ( store [ i ^ 1 ] ) emit_insn ( store [ i ^ 1 ] ) ; return true ; } </s>

Like move_by_pieces , but take account of load latency , and actual offset ranges . Return true on success .


<s> static void bfin_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain_value ) { rtx t1 = copy_to_reg ( XEXP ( DECL_RTL ( fndecl ) , 0 ) ) ; rtx t2 = copy_to_reg ( chain_value ) ; rtx mem ; int i = 0 ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ; if ( TARGET_FDPIC ) { rtx a = force_reg ( Pmode , plus_constant ( Pmode , XEXP ( m_tramp , 0 ) , 8 ) ) ; mem = adjust_address ( m_tramp , Pmode , 0 ) ; emit_move_insn ( mem , a ) ; i = 8 ; } mem = adjust_address ( m_tramp , HImode , i + 2 ) ; emit_move_insn ( mem , gen_lowpart ( HImode , t1 ) ) ; emit_insn ( gen_ashrsi3 ( t1 , t1 , GEN_INT ( 16 ) ) ) ; mem = adjust_address ( m_tramp , HImode , i + 6 ) ; emit_move_insn ( mem , gen_lowpart ( HImode , t1 ) ) ; mem = adjust_address ( m_tramp , HImode , i + 10 ) ; emit_move_insn ( mem , gen_lowpart ( HImode , t2 ) ) ; emit_insn ( gen_ashrsi3 ( t2 , t2 , GEN_INT ( 16 ) ) ) ; mem = adjust_address ( m_tramp , HImode , i + 14 ) ; emit_move_insn ( mem , gen_lowpart ( HImode , t2 ) ) ; } </s>

Emit RTL insns to initialize the variable parts of a trampoline at M_TRAMP . FNDECL is the target function . CHAIN_VALUE is an RTX for the static chain value for the function .


<s>
void
Thumb1InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
PseudoSourceValue
::
getFixedStack
(
FI
)
,
MachineMemOperand
::
MOStore
,
0
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tSpill
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .

ARM
ARM::tGPRRegisterClass
ARM
"Unknown regclass!"
ARM::tGPRRegisterClass
ARM
0
ARM::tSpill
0


<s> unsigned getNumFixupKinds ( ) const override { return X86 :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> static rtx aarch64_sve_emit_int_cmp ( rtx target , machine_mode pred_mode , rtx_code cmp , machine_mode data_mode , rtx op1 , rtx op2 ) { insn_code icode = code_for_aarch64_pred_cmp ( cmp , data_mode ) ; expand_operand ops [ 5 ] ; create_output_operand ( & ops [ 0 ] , target , pred_mode ) ; create_input_operand ( & ops [ 1 ] , CONSTM1_RTX ( pred_mode ) , pred_mode ) ; create_integer_operand ( & ops [ 2 ] , SVE_KNOWN_PTRUE ) ; create_input_operand ( & ops [ 3 ] , op1 , data_mode ) ; create_input_operand ( & ops [ 4 ] , op2 , data_mode ) ; expand_insn ( icode , 5 , ops ) ; return ops [ 0 ] . value ; } </s>

Emit a comparison CMP between OP0 and OP1 , both of which have mode DATA_MODE , and return the result in a predicate of mode PRED_MODE . Use TARGET as the target register if nonnull and convenient .


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { if ( isConditionalBranch ( Inst ) ) { int64_t Imm ; if ( Size == 2 ) Imm = Inst . getOperand ( 1 ) . getImm ( ) ; else Imm = Inst . getOperand ( 2 ) . getImm ( ) ; Target = Addr + Imm ; return true ; } if ( Inst . getOpcode ( ) == RISCV :: C_JAL || Inst . getOpcode ( ) == RISCV :: C_J ) { Target = Addr + Inst . getOperand ( 0 ) . getImm ( ) ; return true ; } if ( Inst . getOpcode ( ) == RISCV :: JAL ) { Target = Addr + Inst . getOperand ( 1 ) . getImm ( ) ; return true ; } return false ; } </s>

Given a branch instruction try to get the address the branch targets .


<s> void xstormy16_split_cbranch ( machine_mode mode , rtx label , rtx comparison , rtx dest ) { rtx op0 = XEXP ( comparison , 0 ) ; rtx op1 = XEXP ( comparison , 1 ) ; rtx_insn * seq , * last_insn ; rtx compare ; start_sequence ( ) ; xstormy16_expand_arith ( mode , COMPARE , dest , op0 , op1 ) ; seq = get_insns ( ) ; end_sequence ( ) ; gcc_assert ( INSN_P ( seq ) ) ; last_insn = seq ; while ( NEXT_INSN ( last_insn ) != NULL_RTX ) last_insn = NEXT_INSN ( last_insn ) ; compare = SET_SRC ( XVECEXP ( PATTERN ( last_insn ) , 0 , 0 ) ) ; PUT_CODE ( XEXP ( compare , 0 ) , GET_CODE ( comparison ) ) ; XEXP ( compare , 1 ) = gen_rtx_LABEL_REF ( VOIDmode , label ) ; emit_insn ( seq ) ; } </s>

Take a SImode conditional branch , one of GT/LE/GTU/LEU , and split the arithmetic operation . Most of the work is done by xstormy16_expand_arith .


<s> int legitimate_const_double_p ( rtx address ) { long sval [ 2 ] ; if ( GET_MODE ( address ) == VOIDmode ) return 0 ; REAL_VALUE_TO_TARGET_DOUBLE ( * CONST_DOUBLE_REAL_VALUE ( address ) , sval ) ; if ( ( sval [ 0 ] & 0xffff ) == 0 && sval [ 1 ] == 0 ) return 1 ; return 0 ; } </s>

This function checks whether a real value can be encoded as a literal , i.e. , addressing mode 27 . In that mode , real values are one word values , so the remaining 48 bits have to be zero .


<s> static int ix86_cmp_code_to_pcmp_immediate ( enum rtx_code code , machine_mode mode ) { if ( FLOAT_MODE_P ( mode ) ) return ix86_fp_cmp_code_to_pcmp_immediate ( code ) ; return ix86_int_cmp_code_to_pcmp_immediate ( code ) ; } </s>

Return immediate value to be used in UNSPEC_PCMP for comparison CODE in MODE .


<s> const char * MINA32TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { case MINA32ISD :: name : \ return # name switch ( Opcode ) { default : return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static bool arm_handle_option ( size_t code , const char * arg , int value ATTRIBUTE_UNUSED ) { switch ( code ) { case OPT_march_ : arm_select [ 1 ] . string = arg ; return true ; case OPT_mcpu_ : arm_select [ 0 ] . string = arg ; return true ; case OPT_mhard_float : target_float_abi_name = "hard" ; return true ; case OPT_msoft_float : target_float_abi_name = "soft" ; return true ; case OPT_mtune_ : arm_select [ 2 ] . string = arg ; return true ; default : return true ; } } </s>


<s> bool rs6000_is_valid_shift_mask ( rtx mask , rtx shift , machine_mode mode ) { int nb , ne ; if ( ! rs6000_is_valid_mask ( mask , & nb , & ne , mode ) ) return false ; int n = GET_MODE_PRECISION ( mode ) ; int sh = - 1 ; if ( CONST_INT_P ( XEXP ( shift , 1 ) ) ) { sh = INTVAL ( XEXP ( shift , 1 ) ) ; if ( sh < 0 || sh >= n ) return false ; } rtx_code code = GET_CODE ( shift ) ; if ( sh == 0 ) code = ROTATE ; if ( code == ROTATE && sh >= 0 && nb >= ne && ne >= sh ) code = ASHIFT ; if ( code == ROTATE && sh >= 0 && nb >= ne && nb < sh ) { code = LSHIFTRT ; sh = n - sh ; } if ( mode == DImode && code == ROTATE ) return ( nb == 63 || ne == 0 || ne == sh ) ; if ( mode == SImode && code == ROTATE ) return ( nb < 32 && ne < 32 && sh < 32 ) ; if ( ne > nb ) return false ; if ( sh < 0 ) return false ; if ( code == ASHIFT && ne < sh ) return false ; if ( nb < 32 && ne < 32 && sh < 32 && ! ( code == LSHIFTRT && nb >= 32 - sh ) ) return true ; if ( code == LSHIFTRT ) sh = 64 - sh ; if ( nb == 63 || ne == 0 || ne == sh ) return ! ( code == LSHIFTRT && nb >= sh ) ; return false ; } </s>

Return whether MASK ( a CONST_INT ) is a valid mask for any rlw [ i ] nm , rld [ i ] cl , rld [ i ] cr , or rld [ i ] c instruction , to implement an AND with shift SHIFT ( a ROTATE , ASHIFT , or LSHIFTRT ) in mode MODE .


<s> static rtx frv_read_argument ( tree * arglistptr ) { tree next = TREE_VALUE ( * arglistptr ) ; * arglistptr = TREE_CHAIN ( * arglistptr ) ; return expand_expr ( next , NULL_RTX , VOIDmode , 0 ) ; } </s>

Read a value from the head of the tree list pointed to by ARGLISTPTR . Return the value as an rtx and replace * ARGLISTPTR with the tail of the list .


<s> static void ix86_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain_value ) { rtx mem , fnaddr ; int opcode ; int offset = 0 ; fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; if ( TARGET_64BIT ) { int size ; if ( ptr_mode == SImode || x86_64_zext_immediate_operand ( fnaddr , VOIDmode ) ) { fnaddr = copy_addr_to_reg ( fnaddr ) ; mem = adjust_address ( m_tramp , HImode , offset ) ; emit_move_insn ( mem , gen_int_mode ( 0xbb41 , HImode ) ) ; mem = adjust_address ( m_tramp , SImode , offset + 2 ) ; emit_move_insn ( mem , gen_lowpart ( SImode , fnaddr ) ) ; offset += 6 ; } else { mem = adjust_address ( m_tramp , HImode , offset ) ; emit_move_insn ( mem , gen_int_mode ( 0xbb49 , HImode ) ) ; mem = adjust_address ( m_tramp , DImode , offset + 2 ) ; emit_move_insn ( mem , fnaddr ) ; offset += 10 ; } if ( ptr_mode == SImode ) { opcode = 0xba41 ; size = 6 ; } else { opcode = 0xba49 ; size = 10 ; } mem = adjust_address ( m_tramp , HImode , offset ) ; emit_move_insn ( mem , gen_int_mode ( opcode , HImode ) ) ; mem = adjust_address ( m_tramp , ptr_mode , offset + 2 ) ; emit_move_insn ( mem , chain_value ) ; offset += size ; mem = adjust_address ( m_tramp , SImode , offset ) ; emit_move_insn ( mem , gen_int_mode ( 0x90e3ff49 , SImode ) ) ; offset += 4 ; } else { rtx disp , chain ; chain = ix86_static_chain ( fndecl , true ) ; if ( REG_P ( chain ) ) { switch ( REGNO ( chain ) ) { case AX_REG : opcode = 0xb8 ; break ; case CX_REG : opcode = 0xb9 ; break ; default : gcc_unreachable ( ) ; } } else opcode = 0x68 ; mem = adjust_address ( m_tramp , QImode , offset ) ; emit_move_insn ( mem , gen_int_mode ( opcode , QImode ) ) ; mem = adjust_address ( m_tramp , SImode , offset + 1 ) ; emit_move_insn ( mem , chain_value ) ; offset += 5 ; mem = adjust_address ( m_tramp , QImode , offset ) ; emit_move_insn ( mem , gen_int_mode ( 0xe9 , QImode ) ) ; mem = adjust_address ( m_tramp , SImode , offset + 1 ) ; offset += 5 ; disp = expand_binop ( SImode , sub_optab , fnaddr , plus_constant ( Pmode , XEXP ( m_tramp , 0 ) , offset - ( MEM_P ( chain ) ? 1 : 0 ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ; emit_move_insn ( mem , disp ) ; } gcc_assert ( offset <= TRAMPOLINE_SIZE ) ; if ( CHECK_EXECUTE_STACK_ENABLED ) emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , "__enable_execute_stack" ) , LCT_NORMAL , VOIDmode , 1 , XEXP ( m_tramp , 0 ) , Pmode ) ; } </s>

Emit RTL insns to initialize the variable parts of a trampoline . FNDECL is the decl of the target address ; M_TRAMP is a MEM for the trampoline , and CHAIN_VALUE is an RTX for the static chain to be passed to the target function .


<s> bool AArch64CompressJumpTables :: runOnMachineFunction ( MachineFunction & MFIn ) { bool Changed = false ; MF = & MFIn ; const auto & ST = MF -> getSubtarget < AArch64Subtarget > ( ) ; TII = ST . getInstrInfo ( ) ; if ( ST . force32BitJumpTables ( ) && ! MF -> getFunction ( ) . optForMinSize ( ) ) return false ; scanFunction ( ) ; for ( MachineBasicBlock & MBB : * MF ) { int Offset = BlockInfo [ MBB . getNumber ( ) ] ; for ( MachineInstr & MI : MBB ) { Changed |= compressJumpTable ( MI , Offset ) ; Offset += TII -> getInstSizeInBytes ( MI ) ; } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> static int translate_unix ( char * name , int type ) { strcpy ( filename_buff , name ) ; return 0 ; } </s>

Action routine called by decc $ to_vms . NAME is a file name or directory name . TYPE is unused .


<s> void TLCS900FrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; TLCS900MachineFunctionInfo * TLCS900FI = MF . getInfo < TLCS900MachineFunctionInfo > ( ) ; const TLCS900InstrInfo & TII = * static_cast < const TLCS900InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; uint64_t NumBytes = 0 ; if ( hasFP ( MF ) ) { uint64_t FrameSize = StackSize - 2 ; NumBytes = FrameSize - TLCS900FI -> getCalleeSavedFrameSize ( ) ; MFI -> setOffsetAdjustment ( - NumBytes ) ; BuildMI ( MBB , MBBI , DL , TII . get ( TLCS900 :: PUSH16r ) ) . addReg ( TLCS900 :: FPW , RegState :: Kill ) ; BuildMI ( MBB , MBBI , DL , TII . get ( TLCS900 :: MOV16rr ) , TLCS900 :: FPW ) . addReg ( TLCS900 :: SPW ) ; for ( MachineFunction :: iterator I = llvm :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( TLCS900 :: FPW ) ; } else NumBytes = StackSize - TLCS900FI -> getCalleeSavedFrameSize ( ) ; while ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == TLCS900 :: PUSH16r ) ) ++ MBBI ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes ) { if ( NumBytes ) { MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( TLCS900 :: SUB16ri ) , TLCS900 :: SPW ) . addReg ( TLCS900 :: SPW ) . addImm ( NumBytes ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; } } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> virtual unsigned int execute ( function * ) { return mips_machine_reorg2 ( ) ; } </s>


<s> void PTXFrameInfo :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


<s> void AArch64PassConfig :: addPreSched2 ( ) { addPass ( createAArch64ExpandPseudoPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoadStoreOpt ) addPass ( createAArch64LoadStoreOptimizationPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorHWPFFixPass ( ) ) ; } } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> static int need_to_save ( int regno ) { if ( fixed_regs [ regno ] ) return 0 ; if ( crtl -> calls_eh_return ) return 1 ; if ( regno == FP_REGNO ) return 0 ; if ( cfun -> machine -> is_interrupt && ( ! cfun -> machine -> is_leaf || ( regno == A0_REGNO && m32c_function_needs_enter ( ) ) ) ) return 1 ; if ( df_regs_ever_live_p ( regno ) && ( ! call_used_or_fixed_reg_p ( regno ) || cfun -> machine -> is_interrupt ) ) return 1 ; return 0 ; } </s>

Returns true if the given register needs to be saved by the current function .


<s>
bool
TPCSingleUseScalarOptimizerPass
::
runOnFunction
(
Function
&
Func
)
{
if
(
skipFunction
(
Func
)
)
return
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"**** SingleUseScalarOptimizer Pass\n"
)
;
bool
Changed
=
false
;
for
(
auto
&
BB
:
Func
)
{
for
(
auto
&
I
:
BB
)
{
if
(
const
IntrinsicInst
*
intrins
=
dyn_cast
<
IntrinsicInst
>
(
&
I
)
)
{
Intrinsic
::
ID
inid
=
intrins
->
getIntrinsicID
(
)
;
if
(
inid
==
Intrinsic
::
tpc_convert_int
)
{
if
(
I
.
hasOneUse
(
)
)
{
Instruction
*
C
=
cast
<
Instruction
>
(
*
I
.
user_begin
(
)
)
;
if
(
auto
*
inse
=
dyn_cast
<
InsertElementInst
>
(
C
)
)
{
if
(
inse
->
hasOneUse
(
)
)
{
Instruction
*
D
=
cast
<
Instruction
>
(
*
C
->
user_begin
(
)
)
;
if
(
auto
*
shuffl
=
dyn_cast
<
ShuffleVectorInst
>
(
D
)
)
{
if
(
shuffl
->
hasOneUse
(
)
)
{
for
(
auto
&
U
:
D
->
uses
(
)
)
{
Instruction
*
UI
=
cast
<
Instruction
>
(
U
.
getUser
(
)
)
;
if
(
IntrinsicInst
*
intrins1
=
dyn_cast
<
IntrinsicInst
>
(
UI
)
)
{
Intrinsic
::
ID
inid1
=
intrins1
->
getIntrinsicID
(
)
;
if
(
inid1
==
Intrinsic
::
tpc_mac
&&
UI
->
getParent
(
)
!=
&
BB
)
{
C
->
moveBefore
(
UI
)
;
D
->
moveBefore
(
UI
)
;
Changed
=
true
;
}
}
}
}
}
}
}
}
}
}
}
}
return
Changed
;
}
</s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .

TPC
TPC
"**** SingleUseScalarOptimizer Pass\n"
Intrinsic::ID
Intrinsic::tpc_convert_int
Intrinsic::ID
Intrinsic::tpc_mac


"No MachineFunctionInfo for this function!"