<s> void BPFAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const { if ( Fixup . getKind ( ) == FK_SecRel_8 ) { assert ( Value <= UINT32_MAX ) ; support :: endian :: write < uint32_t > ( & Data [ Fixup . getOffset ( ) + 4 ] , static_cast < uint32_t > ( Value ) , Endian ) ; } else if ( Fixup . getKind ( ) == FK_Data_4 ) { support :: endian :: write < uint32_t > ( & Data [ Fixup . getOffset ( ) ] , Value , Endian ) ; } else if ( Fixup . getKind ( ) == FK_Data_8 ) { support :: endian :: write < uint64_t > ( & Data [ Fixup . getOffset ( ) ] , Value , Endian ) ; } else if ( Fixup . getKind ( ) == FK_PCRel_4 ) { Value = ( uint32_t ) ( ( Value - 8 ) / 8 ) ; if ( Endian == support :: little ) { Data [ Fixup . getOffset ( ) + 1 ] = 0x10 ; support :: endian :: write32le ( & Data [ Fixup . getOffset ( ) + 4 ] , Value ) ; } else { Data [ Fixup . getOffset ( ) + 1 ] = 0x1 ; support :: endian :: write32be ( & Data [ Fixup . getOffset ( ) + 4 ] , Value ) ; } } else { assert ( Fixup . getKind ( ) == FK_PCRel_2 ) ; Value = ( uint16_t ) ( ( Value - 8 ) / 8 ) ; support :: endian :: write < uint16_t > ( & Data [ Fixup . getOffset ( ) + 2 ] , Value , Endian ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool TPCImmToReg :: runOnMachineFunction ( MachineFunction & Func ) { if ( ! EnableTPCImmToReg ) return false ; MF = & Func ; MRI = & MF -> getRegInfo ( ) ; if ( skipFunction ( Func . getFunction ( ) ) ) return false ; processImmOperand ( Func ) ; return NumReplaced > 0 ; } </s>

runOnMachineFunction - Emit the function body .


<s> unsigned TriCoreRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TriCoreFrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? TriCore :: A14 : TriCore :: A10 ; } </s>


<s>
StringRef
AArch64MCExpr
::
getVariantKindName
(
)
const
{
switch
(
static_cast
<
uint32_t
>
(
getKind
(
)
)
)
{
case
VK_CALL
:
return
""
;
case
VK_LO12
:
return
":lo12:"
;
case
VK_ABS_G3
:
return
":abs_g3:"
;
case
VK_ABS_G2
:
return
":abs_g2:"
;
case
VK_ABS_G2_S
:
return
":abs_g2_s:"
;
case
VK_ABS_G2_NC
:
return
":abs_g2_nc:"
;
case
VK_ABS_G1
:
return
":abs_g1:"
;
case
VK_ABS_G1_S
:
return
":abs_g1_s:"
;
case
VK_ABS_G1_NC
:
return
":abs_g1_nc:"
;
case
VK_ABS_G0
:
return
":abs_g0:"
;
case
VK_ABS_G0_S
:
return
":abs_g0_s:"
;
case
VK_ABS_G0_NC
:
return
":abs_g0_nc:"
;
case
VK_DTPREL_G2
:
return
":dtprel_g2:"
;
case
VK_DTPREL_G1
:
return
":dtprel_g1:"
;
case
VK_DTPREL_G1_NC
:
return
":dtprel_g1_nc:"
;
case
VK_DTPREL_G0
:
return
":dtprel_g0:"
;
case
VK_DTPREL_G0_NC
:
return
":dtprel_g0_nc:"
;
case
VK_DTPREL_HI12
:
return
":dtprel_hi12:"
;
case
VK_DTPREL_LO12
:
return
":dtprel_lo12:"
;
case
VK_DTPREL_LO12_NC
:
return
":dtprel_lo12_nc:"
;
case
VK_TPREL_G2
:
return
":tprel_g2:"
;
case
VK_TPREL_G1
:
return
":tprel_g1:"
;
case
VK_TPREL_G1_NC
:
return
":tprel_g1_nc:"
;
case
VK_TPREL_G0
:
return
":tprel_g0:"
;
case
VK_TPREL_G0_NC
:
return
":tprel_g0_nc:"
;
case
VK_TPREL_HI12
:
return
":tprel_hi12:"
;
case
VK_TPREL_LO12
:
return
":tprel_lo12:"
;
case
VK_TPREL_LO12_NC
:
return
":tprel_lo12_nc:"
;
case
VK_TLSDESC_LO12
:
return
":tlsdesc_lo12:"
;
case
VK_ABS_PAGE
:
return
""
;
case
VK_ABS_PAGE_NC
:
return
":pg_hi21_nc:"
;
case
VK_GOT_PAGE
:
return
":got:"
;
case
VK_GOT_LO12
:
return
":got_lo12:"
;
case
VK_GOTTPREL_PAGE
:
return
":gottprel:"
;
case
VK_GOTTPREL_LO12_NC
:
return
":gottprel_lo12:"
;
case
VK_GOTTPREL_G1
:
return
":gottprel_g1:"
;
case
VK_GOTTPREL_G0_NC
:
return
":gottprel_g0_nc:"
;
case
VK_TLSDESC
:
return
""
;
case
VK_TLSDESC_PAGE
:
return
":tlsdesc:"
;
default
:
llvm_unreachable
(
"Invalid ELF symbol kind"
)
;
}
}
</s>

Convert the variant kind into an ELF-appropriate modifier ( e.g .


<s> static void rs6000_darwin64_record_arg_recurse ( CUMULATIVE_ARGS * cum , const_tree type , HOST_WIDE_INT startbitpos , rtx rvec [ ] , int * k ) { tree f ; for ( f = TYPE_FIELDS ( type ) ; f ; f = DECL_CHAIN ( f ) ) if ( TREE_CODE ( f ) == FIELD_DECL ) { HOST_WIDE_INT bitpos = startbitpos ; tree ftype = TREE_TYPE ( f ) ; machine_mode mode ; if ( ftype == error_mark_node ) continue ; mode = TYPE_MODE ( ftype ) ; if ( DECL_SIZE ( f ) != 0 && tree_fits_uhwi_p ( bit_position ( f ) ) ) bitpos += int_bit_position ( f ) ; if ( TREE_CODE ( ftype ) == RECORD_TYPE ) rs6000_darwin64_record_arg_recurse ( cum , ftype , bitpos , rvec , k ) ; else if ( cum -> named && USE_FP_FOR_ARG_P ( cum , mode ) ) { unsigned n_fpreg = ( GET_MODE_SIZE ( mode ) + 7 ) >> 3 ; switch ( mode ) { case SCmode : mode = SFmode ; break ; case DCmode : mode = DFmode ; break ; case TCmode : mode = TFmode ; break ; default : break ; } rs6000_darwin64_record_arg_flush ( cum , bitpos , rvec , k ) ; if ( cum -> fregno + n_fpreg > FP_ARG_MAX_REG + 1 ) { gcc_assert ( cum -> fregno == FP_ARG_MAX_REG && ( mode == TFmode || mode == TDmode ) ) ; mode = DECIMAL_FLOAT_MODE_P ( mode ) ? DDmode : DFmode ; cum -> use_stack = 1 ; } rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , cum -> fregno ++ ) , GEN_INT ( bitpos / BITS_PER_UNIT ) ) ; if ( mode == TFmode || mode == TDmode ) cum -> fregno ++ ; } else if ( cum -> named && USE_ALTIVEC_FOR_ARG_P ( cum , mode , 1 ) ) { rs6000_darwin64_record_arg_flush ( cum , bitpos , rvec , k ) ; rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , cum -> vregno ++ ) , GEN_INT ( bitpos / BITS_PER_UNIT ) ) ; } else if ( cum -> intoffset == - 1 ) cum -> intoffset = bitpos ; } } </s>


<s> bool PPCRegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , unsigned Reg , int & FrameIdx ) const { if ( Subtarget . isSVR4ABI ( ) && PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ) { if ( Subtarget . isPPC64 ( ) ) { FrameIdx = 0 ; } else if ( CRSpillFrameIdx ) { FrameIdx = CRSpillFrameIdx ; } else { MachineFrameInfo * MFI = ( const_cast < MachineFunction & > ( MF ) ) . getFrameInfo ( ) ; FrameIdx = MFI -> CreateFixedObject ( ( uint64_t ) 4 , ( int64_t ) - 4 , true ) ; CRSpillFrameIdx = FrameIdx ; } return true ; } return false ; } </s>

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register .


<s> bool ARMTargetLowering :: isShuffleMaskLegal ( ArrayRef < int > M , EVT VT ) const { if ( VT . getVectorNumElements ( ) == 4 && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ 4 ] ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { if ( M [ i ] < 0 ) PFIndexes [ i ] = 8 ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ 0 ] * 9 * 9 * 9 + PFIndexes [ 1 ] * 9 * 9 + PFIndexes [ 2 ] * 9 + PFIndexes [ 3 ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> 30 ) ; if ( Cost <= 4 ) return true ; } bool ReverseVEXT , isV_UNDEF ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; return ( EltSize >= 32 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isVREVMask ( M , VT , 64 ) || isVREVMask ( M , VT , 32 ) || isVREVMask ( M , VT , 16 ) || isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTBLMask ( M , VT ) || isNEONTwoResultShuffleMask ( M , VT , WhichResult , isV_UNDEF ) || ( ( VT == MVT :: v8i16 || VT == MVT :: v16i8 ) && isReverseMask ( M , VT ) ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> const TGSITargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


<s> unsigned MipsFastISel :: fastMaterializeConstant ( const Constant * C ) { if ( ! TargetSupported ) return 0 ; EVT CEVT = TLI . getValueType ( DL , C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return ( UnsupportedFPMode ) ? 0 : materializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return materializeGV ( GV , VT ) ; else if ( isa < ConstantInt > ( C ) ) return materializeInt ( C , VT ) ; return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s> void mips_restore_gp ( void ) { rtx address , slot ; gcc_assert ( TARGET_ABICALLS && TARGET_OLDABI ) ; address = mips_add_offset ( pic_offset_table_rtx , frame_pointer_needed ? hard_frame_pointer_rtx : stack_pointer_rtx , current_function_outgoing_args_size ) ; slot = gen_rtx_MEM ( Pmode , address ) ; emit_move_insn ( pic_offset_table_rtx , slot ) ; if ( ! TARGET_EXPLICIT_RELOCS ) emit_insn ( gen_blockage ( ) ) ; } </s>

Restore $ gp from its save slot . Valid only when using o32 or o64 abicalls .


<s> static Mfix * create_fix_barrier ( Mfix * fix , HOST_WIDE_INT max_address ) { HOST_WIDE_INT count = 0 ; rtx_barrier * barrier ; rtx_insn * from = fix -> insn ; rtx_insn * selected = NULL ; int selected_cost ; HOST_WIDE_INT selected_address ; Mfix * new_fix ; HOST_WIDE_INT max_count = max_address - fix -> address ; rtx_code_label * label = gen_label_rtx ( ) ; selected_cost = arm_barrier_cost ( from ) ; selected_address = fix -> address ; while ( from && count < max_count ) { rtx_jump_table_data * tmp ; int new_cost ; gcc_assert ( ! BARRIER_P ( from ) ) ; if ( LABEL_P ( from ) ) count += get_label_padding ( from ) ; else count += get_attr_length ( from ) ; if ( tablejump_p ( from , NULL , & tmp ) ) { count += get_jump_table_size ( tmp ) ; new_cost = arm_barrier_cost ( from ) ; if ( count < max_count && ( ! selected || new_cost <= selected_cost ) ) { selected = tmp ; selected_cost = new_cost ; selected_address = fix -> address + count ; } from = NEXT_INSN ( tmp ) ; continue ; } new_cost = arm_barrier_cost ( from ) ; if ( count < max_count && ( ! selected || new_cost <= selected_cost ) ) { selected = from ; selected_cost = new_cost ; selected_address = fix -> address + count ; } from = NEXT_INSN ( from ) ; } gcc_assert ( selected ) ; if ( CALL_P ( selected ) ) { rtx_insn * next = NEXT_INSN ( selected ) ; if ( next && NOTE_P ( next ) && NOTE_KIND ( next ) == NOTE_INSN_CALL_ARG_LOCATION ) selected = next ; } from = emit_jump_insn_after ( gen_jump ( label ) , selected ) ; JUMP_LABEL ( from ) = label ; barrier = emit_barrier_after ( from ) ; emit_label_after ( label , barrier ) ; new_fix = ( Mfix * ) obstack_alloc ( & minipool_obstack , sizeof ( * new_fix ) ) ; new_fix -> insn = barrier ; new_fix -> address = selected_address ; new_fix -> next = fix -> next ; fix -> next = new_fix ; return new_fix ; } </s>

Find the best place in the insn stream in the range ( FIX- > address , MAX_ADDRESS ) to forcibly insert a minipool barrier . Create the barrier by inserting a jump and add a new fix entry for it .


<s>
StringRef
getPassName
(
)
const
override
{
return
"SI post-RA bundler"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> unsigned PPCInstrInfo :: getInstrLatency ( const InstrItineraryData * ItinData , const MachineInstr * MI , unsigned * PredCost ) const { if ( ! ItinData || UseOldLatencyCalc ) return PPCGenInstrInfo :: getInstrLatency ( ItinData , MI , PredCost ) ; unsigned Latency = 1 ; unsigned DefClass = MI -> getDesc ( ) . getSchedClass ( ) ; for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) || MO . isImplicit ( ) ) continue ; int Cycle = ItinData -> getOperandCycle ( DefClass , i ) ; if ( Cycle < 0 ) continue ; Latency = std :: max ( Latency , ( unsigned ) Cycle ) ; } return Latency ; } </s>

Compute the instruction latency of a given instruction .


<s> unsigned AArch64TTIImpl :: getMaxPrefetchIterationsAhead ( ) { return ST -> getMaxPrefetchIterationsAhead ( ) ; } </s>

Return the maximum prefetch distance in terms of loop iterations .


<s> StringRef getSymbol ( ) const { return S ; } </s>

Get the target address and flags for the named symbol .


<s> bool AArch64AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { OW -> WriteZeros ( Count % 4 ) ; Count /= 4 ; for ( uint64_t i = 0 ; i != Count ; ++ i ) OW -> write32 ( 0xd503201f ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> static int arm_compute_static_chain_stack_bytes ( void ) { if ( cfun -> machine -> static_chain_stack_bytes != - 1 ) return cfun -> machine -> static_chain_stack_bytes ; if ( IS_NESTED ( arm_current_func_type ( ) ) && ( ( TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM ) || ( ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK || flag_stack_clash_protection ) && ! df_regs_ever_live_p ( LR_REGNUM ) ) ) && arm_r3_live_at_start_p ( ) && crtl -> args . pretend_args_size == 0 ) return 4 ; return 0 ; } </s>

Compute the number of bytes used to store the static chain register on the stack , above the stack frame . We need to know this accurately to get the alignment of the rest of the stack frame correct .


<s> static bool characterize_address ( rtx x , rtx * base , rtx * index , rtx * addend ) { * base = NULL_RTX ; * index = NULL_RTX ; * addend = NULL_RTX ; if ( GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNS_ES_ADDR ) x = XVECEXP ( x , 0 , 1 ) ; if ( GET_CODE ( x ) == REG ) { * base = x ; return true ; } if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 0 ) ) == SYMBOL_REF && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) { * addend = x ; return true ; } if ( GET_CODE ( x ) == PLUS ) { * base = XEXP ( x , 0 ) ; x = XEXP ( x , 1 ) ; if ( GET_CODE ( * base ) == SUBREG ) { if ( GET_MODE ( * base ) == HImode && GET_MODE ( XEXP ( * base , 0 ) ) == SImode && GET_CODE ( XEXP ( * base , 0 ) ) == REG ) { * base = gen_rtx_REG ( HImode , REGNO ( XEXP ( * base , 0 ) ) ) ; } } if ( GET_CODE ( * base ) != REG && GET_CODE ( x ) == REG ) { rtx tmp = * base ; * base = x ; x = tmp ; } if ( GET_CODE ( * base ) != REG ) return false ; if ( GET_CODE ( x ) == ZERO_EXTEND && GET_CODE ( XEXP ( x , 0 ) ) == REG ) { * index = XEXP ( x , 0 ) ; return false ; } } switch ( GET_CODE ( x ) ) { case PLUS : if ( GET_CODE ( XEXP ( x , 0 ) ) == SYMBOL_REF && GET_CODE ( XEXP ( x , 0 ) ) == CONST_INT ) { * addend = x ; return true ; } case MEM : case REG : return false ; case SUBREG : switch ( GET_CODE ( XEXP ( x , 0 ) ) ) { case CONST : case SYMBOL_REF : case CONST_INT : * addend = x ; return true ; default : return false ; } case CONST : case SYMBOL_REF : case CONST_INT : * addend = x ; return true ; default : return false ; } return false ; } </s>

Break down an address RTX into its component base/index/addend portions and return TRUE if the address is of a valid form , else FALSE .


<s> const TargetRegisterClass * SparcRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return Subtarget . is64Bit ( ) ? & SP :: I64RegsRegClass : & SP :: IntRegsRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .

Sparc Sparc SP::I64RegsRegClass SP::IntRegsRegClass


<s> void M88kRegisterBankInfo :: applyMappingImpl ( const OperandsMapper & OpdMapper ) const { return applyDefaultMapping ( OpdMapper ) ; } </s>


<s> unsigned getOccupancyWithLocalMemSize ( const MachineFunction & MF ) const { const auto * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; return getOccupancyWithLocalMemSize ( MFI -> getLDSSize ( ) , MF . getFunction ( ) ) ; } </s>

Inverse of getMaxLocalMemWithWaveCount .


<s> bool MipsLongBranch :: runOnMachineFunction ( MachineFunction & F ) { const MipsSubtarget & STI = static_cast < const MipsSubtarget & > ( F . getSubtarget ( ) ) ; const MipsInstrInfo * TII = static_cast < const MipsInstrInfo * > ( STI . getInstrInfo ( ) ) ; const TargetMachine & TM = F . getTarget ( ) ; IsPIC = TM . isPositionIndependent ( ) ; ABI = static_cast < const MipsTargetMachine & > ( TM ) . getABI ( ) ; LongBranchSeqSize = IsPIC ? ( ( ABI . IsN64 ( ) || STI . isTargetNaCl ( ) ) ? 10 : 9 ) : ( STI . hasMips32r6 ( ) ? 1 : 2 ) ; if ( STI . inMips16Mode ( ) || ! STI . enableLongBranchPass ( ) ) return false ; if ( IsPIC && static_cast < const MipsTargetMachine & > ( TM ) . getABI ( ) . IsO32 ( ) && F . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; int ShVal = STI . inMicroMipsMode ( ) ? 2 : 4 ; int64_t Offset = computeOffset ( I -> Br ) / ShVal ; if ( STI . isTargetNaCl ( ) ) { Offset *= 2 ; } if ( ! ForceLongBranch && isInt < 16 > ( Offset ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * 4 ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( IsPIC ) { uint64_t Address = 0 ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ; } for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) if ( I -> HasLongBranch ) expandToLongBranch ( * I ) ; MF -> RenumberBlocks ( ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> const char * TPCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case ( TPCISD :: FPOR ) : return "TPC::FPOR" ; case ( TPCISD :: FPAND ) : return "TPC::FPAND" ; case ( TPCISD :: FPXOR ) : return "TPC::FPXOR" ; case ( TPCISD :: FPNOT ) : return "TPC::FPNOT" ; case ( TPCISD :: MAC ) : return "TPC::MAC" ; case ( TPCISD :: FMAC ) : return "TPC::FMAC" ; case ( TPCISD :: MAX ) : return "TPC::MAX" ; case ( TPCISD :: MIN ) : return "TPC::MIN" ; case ( TPCISD :: FMAX ) : return "TPC::FMAX" ; case ( TPCISD :: FMIN ) : return "TPC::FMIN" ; case ( TPCISD :: INOT ) : return "TPC::INOT" ; case ( TPCISD :: FSRL ) : return "TPC::FSRL" ; case ( TPCISD :: FSHL ) : return "TPC::FSHL" ; case ( TPCISD :: FSRA ) : return "TPC::FSRA" ; case ( TPCISD :: HALT ) : return "halt" ; case ( TPCISD :: COND_MOV ) : return "TPC::COND_MOV" ; case ( TPCISD :: COND_MOV_INVERT ) : return "TPC::COND_MOV_INVERT" ; case ( TPCISD :: LD_G ) : return "TPC::LD_G" ; case ( TPCISD :: LD_G_INC ) : return "TPC::LD_G_INC" ; case ( TPCISD :: ST_G ) : return "TPC::ST_G" ; case ( TPCISD :: ST_G_INC ) : return "TPC::ST_G_INC" ; default : return nullptr ; } } </s>

getTargetNodeName - This method returns the name of a target specific

TPC TPC TPCISD::FPOR "TPC::FPOR" TPCISD::FPAND "TPC::FPAND" TPCISD::FPXOR "TPC::FPXOR" TPCISD::FPNOT "TPC::FPNOT" TPCISD::MAC "TPC::MAC" TPCISD::FMAC "TPC::FMAC" TPCISD::MAX "TPC::MAX" TPCISD::MIN "TPC::MIN" TPCISD::FMAX "TPC::FMAX" TPCISD::FMIN "TPC::FMIN" TPCISD::INOT "TPC::INOT" TPCISD::FSRL "TPC::FSRL" TPCISD::FSHL "TPC::FSHL" TPCISD::FSRA "TPC::FSRA" TPCISD::HALT "halt" TPCISD::COND_MOV "TPC::COND_MOV" TPCISD::COND_MOV_INVERT "TPC::COND_MOV_INVERT" TPCISD::LD_G "TPC::LD_G" TPCISD::LD_G_INC "TPC::LD_G_INC" TPCISD::ST_G "TPC::ST_G" TPCISD::ST_G_INC "TPC::ST_G_INC"


<s> RISCVTargetLowering :: ConstraintType RISCVTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'f' : return C_RegisterClass ; case 'I' : case 'J' : case 'K' : return C_Immediate ; case 'A' : return C_Memory ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> static std :: unique_ptr < ARMOperand > CreateMem ( unsigned BaseRegNum , const MCConstantExpr * OffsetImm , unsigned OffsetRegNum , ARM_AM :: ShiftOpc ShiftType , unsigned ShiftImm , unsigned Alignment , bool isNegative , SMLoc S , SMLoc E , SMLoc AlignmentLoc = SMLoc ( ) ) { auto Op = std :: make_unique < ARMOperand > ( k_Memory ) ; Op -> Memory . BaseRegNum = BaseRegNum ; Op -> Memory . OffsetImm = OffsetImm ; Op -> Memory . OffsetRegNum = OffsetRegNum ; Op -> Memory . ShiftType = ShiftType ; Op -> Memory . ShiftImm = ShiftImm ; Op -> Memory . Alignment = Alignment ; Op -> Memory . isNegative = isNegative ; Op -> StartLoc = S ; Op -> EndLoc = E ; Op -> AlignmentLoc = AlignmentLoc ; return Op ; } </s>


<s>
static
void
write_fn_proto_from_insn
(
std
::
stringstream
&
s
,
const
char
*
name
,
rtx
result
,
rtx
pat
)
{
char
*
replaced_dots
=
;
if
(
!
name
)
{
s
<<
"\t.callprototype "
;
name
=
"_"
;
}
else
{
const
char
*
replacement
=
nvptx_name_replacement
(
name
)
;
if
(
replacement
!=
name
)
name
=
replacement
;
else
{
replaced_dots
=
nvptx_replace_dot
(
name
)
;
if
(
replaced_dots
)
name
=
replaced_dots
;
}
write_fn_marker
(
s
,
false
,
true
,
name
)
;
s
<<
"\t.extern .func "
;
}
if
(
result
!=
NULL_RTX
)
write_return_mode
(
s
,
true
,
GET_MODE
(
result
)
)
;
s
<<
name
;
if
(
replaced_dots
)
XDELETE
(
replaced_dots
)
;
int
arg_end
=
XVECLEN
(
pat
,
0
)
;
for
(
int
i
=
1
;
i
<
arg_end
;
i
++
)
{
machine_mode
mode
=
GET_MODE
(
XEXP
(
XVECEXP
(
pat
,
0
,
i
)
,
0
)
)
;
write_arg_mode
(
s
,
1
,
i
1
,
mode
)
;
}
if
(
arg_end
!=
1
)
s
<<
")"
;
s
<<
";\n"
;
}
</s>

Construct a function declaration from a call insn . This can be necessary for two reasons - either we have an indirect call which requires a .callprototype declaration , or we have a libcall generated by emit_library_call for which no decl exists .


Return true if sparc_output_mi_thunk would be able to output the assembler code for the thunk function specified by the arguments it is passed , and false otherwise .


<s> void PPCRegisterInfo :: lowerCRSpilling ( MachineBasicBlock :: iterator II , unsigned FrameIndex ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = Subtarget . isPPC64 ( ) ; const TargetRegisterClass * G8RC = & PPC :: G8RCRegClass ; const TargetRegisterClass * GPRC = & PPC :: GPRCRegClass ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: MFOCRF8 : PPC :: MFOCRF ) , Reg ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( 0 ) . isKill ( ) ) ) ; if ( SrcReg != PPC :: CR0 ) { unsigned Reg1 = Reg ; Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: RLWINM8 : PPC :: RLWINM ) , Reg ) . addReg ( Reg1 , RegState :: Kill ) . addImm ( getEncodingValue ( SrcReg ) * 4 ) . addImm ( 0 ) . addImm ( 31 ) ; } addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: STW8 : PPC :: STW ) ) . addReg ( Reg , RegState :: Kill ) , FrameIndex ) ; MBB . erase ( II ) ; } </s>

lowerCRSpilling - Generate the code for spilling a CR register .


<s> RegisterRef PhysicalRegisterInfo :: normalize ( RegisterRef RR ) const { if ( PhysicalRegisterInfo :: isRegMaskId ( RR . Reg ) ) return RR ; const TargetRegisterClass * RC = RegInfos [ RR . Reg ] . RegClass ; LaneBitmask RCMask = RC != nullptr ? RC -> LaneMask : LaneBitmask ( 0x00000001 ) ; LaneBitmask Common = RR . Mask & RCMask ; RegisterId SuperReg = RegInfos [ RR . Reg ] . MaxSuper ; uint32_t Sub = TRI . getSubRegIndex ( SuperReg , RR . Reg ) ; LaneBitmask SuperMask = TRI . composeSubRegIndexLaneMask ( Sub , Common ) ; return RegisterRef ( SuperReg , SuperMask ) ; } </s>


<s> MachineInstr * AArch64InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , ArrayRef < unsigned > Ops , MachineBasicBlock :: iterator InsertPt , int FrameIndex , LiveIntervals * LIS ) const { if ( MI -> isCopy ( ) ) { unsigned DstReg = MI -> getOperand ( 0 ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; if ( SrcReg == AArch64 :: SP && TargetRegisterInfo :: isVirtualRegister ( DstReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( DstReg , & AArch64 :: GPR64RegClass ) ; return nullptr ; } if ( DstReg == AArch64 :: SP && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & AArch64 :: GPR64RegClass ) ; return nullptr ; } } return nullptr ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> static rtx loongarch_function_value ( const_tree valtype , const_tree fn_decl_or_type , bool outgoing ATTRIBUTE_UNUSED ) { return loongarch_function_value_1 ( valtype , fn_decl_or_type , VOIDmode ) ; } </s>


<s> bool Z80oldInstrInfo :: analyzeCompare ( const MachineInstr & MI , unsigned & SrcReg , unsigned & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case Z80old :: OR8ar : SrcReg = Z80old :: A ; if ( MI . getOperand ( 1 ) . getReg ( ) != SrcReg ) { return false ; } SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = 0 ; break ; case Z80old :: CP8ai : case Z80old :: SUB8ai : SrcReg = Z80old :: A ; SrcReg2 = 0 ; CmpMask = CmpValue = 0 ; if ( MI . getOperand ( 0 ) . isImm ( ) ) { CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 0 ) . getImm ( ) ; } break ; case Z80old :: CP8ar : case Z80old :: SUB8ar : SrcReg = Z80old :: A ; SrcReg2 = MI . getOperand ( 0 ) . getReg ( ) ; CmpMask = CmpValue = 0 ; break ; case Z80old :: CP8ap : case Z80old :: CP8ao : case Z80old :: SUB8ap : case Z80old :: SUB8ao : SrcReg = Z80old :: A ; SrcReg2 = CmpMask = CmpValue = 0 ; break ; } MachineBasicBlock :: const_reverse_iterator I = MI , E = MI . getParent ( ) -> rend ( ) ; while ( ++ I != E && I -> isFullCopy ( ) ) for ( unsigned * Reg : { & SrcReg , & SrcReg2 } ) if ( TargetRegisterInfo :: isPhysicalRegister ( * Reg ) && * Reg == I -> getOperand ( 0 ) . getReg ( ) ) { * Reg = I -> getOperand ( 1 ) . getReg ( ) ; } return true ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> unsigned VideocoreRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return VC :: R23 ; } </s>


<s> bool HexagonTargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & Mask , EVT VT ) const { if ( Subtarget . useHVXOps ( ) ) return isStridedLoad ( Mask ) != StridedLoadKind :: NoPattern ; return true ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s>
StringRef
getPassName
(
)
const
override
{
return
"WebAssembly Prepare Exception"
;
}
</s>

getPassName - Return a nice clean name for a pass .

WebAssembly
"WebAssembly Prepare Exception"


"flag setting instruction only valid outside IT block"

"instruction only valid inside IT block"

"instruction variant requires ARMv6 or later"

"immediate operand must be in the range [0,15]"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> bool HexagonTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { switch ( Intrinsic ) { case Intrinsic :: hexagon_L2_loadrd_pbr : case Intrinsic :: hexagon_L2_loadri_pbr : case Intrinsic :: hexagon_L2_loadrh_pbr : case Intrinsic :: hexagon_L2_loadruh_pbr : case Intrinsic :: hexagon_L2_loadrb_pbr : case Intrinsic :: hexagon_L2_loadrub_pbr : { Info . opc = ISD :: INTRINSIC_W_CHAIN ; auto & DL = I . getCalledFunction ( ) -> getParent ( ) -> getDataLayout ( ) ; auto & Cont = I . getCalledFunction ( ) -> getParent ( ) -> getContext ( ) ; Type * ElTy = I . getCalledFunction ( ) -> getReturnType ( ) -> getStructElementType ( 0 ) ; Info . memVT = MVT :: getVT ( ElTy ) ; llvm :: Value * BasePtrVal = I . getOperand ( 0 ) ; Info . ptrVal = getUnderLyingObjectForBrevLdIntr ( BasePtrVal ) ; Info . offset = 0 ; Info . align = DL . getABITypeAlignment ( Info . memVT . getTypeForEVT ( Cont ) ) ; Info . flags = MachineMemOperand :: MOLoad ; return true ; } case Intrinsic :: hexagon_V6_vgathermw : case Intrinsic :: hexagon_V6_vgathermw_128B : case Intrinsic :: hexagon_V6_vgathermh : case Intrinsic :: hexagon_V6_vgathermh_128B : case Intrinsic :: hexagon_V6_vgathermhw : case Intrinsic :: hexagon_V6_vgathermhw_128B : case Intrinsic :: hexagon_V6_vgathermwq : case Intrinsic :: hexagon_V6_vgathermwq_128B : case Intrinsic :: hexagon_V6_vgathermhq : case Intrinsic :: hexagon_V6_vgathermhq_128B : case Intrinsic :: hexagon_V6_vgathermhwq : case Intrinsic :: hexagon_V6_vgathermhwq_128B : { const Module & M = * I . getParent ( ) -> getParent ( ) -> getParent ( ) ; Info . opc = ISD :: INTRINSIC_W_CHAIN ; Type * VecTy = I . getArgOperand ( 1 ) -> getType ( ) ; Info . memVT = MVT :: getVT ( VecTy ) ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . align = M . getDataLayout ( ) . getTypeAllocSizeInBits ( VecTy ) / 8 ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; } default : break ; } return false ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


"LC2200 DAG->DAG Pattern Instruction Selection"


<s> void OR1KFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned StackAlign = TRI -> needsStackRealignment ( MF ) ? MFI -> getMaxAlignment ( ) : MF . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = RoundUpToAlignment ( maxCallFrameSize , StackAlign ) ; MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; if ( ! ( hasReservedCallFrame ( MF ) && MFI -> adjustsStack ( ) ) ) FrameSize += maxCallFrameSize ; FrameSize = RoundUpToAlignment ( FrameSize , StackAlign ) ; MFI -> setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s> unsigned PPCInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { unsigned Opcode = MI . getOpcode ( ) ; const unsigned * OpcodesForSpill = getLoadOpcodesForSpillArray ( ) ; const unsigned * End = OpcodesForSpill + SOK_LastOpcodeSpill ; if ( End != std :: find ( OpcodesForSpill , End , Opcode ) ) { if ( MI . getOperand ( 1 ) . isImm ( ) && ! MI . getOperand ( 1 ) . getImm ( ) && MI . getOperand ( 2 ) . isFI ( ) ) { FrameIndex = MI . getOperand ( 2 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> bool AMDGPUInstructionSelector :: select ( MachineInstr & I , CodeGenCoverage & CoverageInfo ) const { if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) { if ( I . isCopy ( ) ) return selectCOPY ( I ) ; return true ; } switch ( I . getOpcode ( ) ) { default : return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_ADD : return selectG_ADD ( I ) ; case TargetOpcode :: G_INTTOPTR : case TargetOpcode :: G_BITCAST : return selectCOPY ( I ) ; case TargetOpcode :: G_CONSTANT : case TargetOpcode :: G_FCONSTANT : return selectG_CONSTANT ( I ) ; case TargetOpcode :: G_EXTRACT : return selectG_EXTRACT ( I ) ; case TargetOpcode :: G_GEP : return selectG_GEP ( I ) ; case TargetOpcode :: G_IMPLICIT_DEF : return selectG_IMPLICIT_DEF ( I ) ; case TargetOpcode :: G_INSERT : return selectG_INSERT ( I ) ; case TargetOpcode :: G_INTRINSIC : return selectG_INTRINSIC ( I , CoverageInfo ) ; case TargetOpcode :: G_INTRINSIC_W_SIDE_EFFECTS : return selectG_INTRINSIC_W_SIDE_EFFECTS ( I , CoverageInfo ) ; case TargetOpcode :: G_ICMP : return selectG_ICMP ( I ) ; case TargetOpcode :: G_LOAD : if ( selectImpl ( I , CoverageInfo ) ) return true ; return selectG_LOAD ( I ) ; case TargetOpcode :: G_SELECT : return selectG_SELECT ( I ) ; case TargetOpcode :: G_STORE : return selectG_STORE ( I ) ; } return false ; } </s>

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s>
void
HvxSelector
::
select
(
SDNode
*
ISelN
)
{
assert
(
ISelN
->
getOpcode
(
)
==
HexagonISD
::
ISEL
)
;
SDNode
*
N0
=
ISelN
->
getOperand
(
0
)
.
getNode
(
)
;
if
(
N0
->
isMachineOpcode
(
)
)
{
ISel
.
ReplaceNode
(
ISelN
,
N0
)
;
return
;
}
DAG
.
RemoveDeadNodes
(
)
;
SetVector
<
SDNode
*
>
SubNodes
,
TmpQ
;
std
::
map
<
SDNode
*
,
unsigned
>
NumOps
;
auto
IsISelN
=
[
]
(
SDNode
*
T
)
{
return
T
->
getOpcode
(
)
==
HexagonISD
::
ISEL
;
}
;
if
(
llvm
::
all_of
(
N0
->
uses
(
)
,
IsISelN
)
)
SubNodes
.
insert
(
N0
)
;
auto
InSubNodes
=
[
&
SubNodes
]
(
SDNode
*
T
)
{
return
SubNodes
.
count
(
T
)
;
}
;
for
(
unsigned
I
=
0
;
I
!=
SubNodes
.
size
(
)
;
++
I
)
{
SDNode
*
S
=
SubNodes
[
I
]
;
unsigned
OpN
=
0
;
for
(
SDValue
Op
:
S
->
ops
(
)
)
{
SDNode
*
O
=
Op
.
getNode
(
)
;
if
(
llvm
::
all_of
(
O
->
uses
(
)
,
InSubNodes
)
)
{
SubNodes
.
insert
(
O
)
;
++
OpN
;
}
}
NumOps
.
insert
(
{
S
,
OpN
}
)
;
if
(
OpN
==
0
)
TmpQ
.
insert
(
S
)
;
}
for
(
unsigned
I
=
0
;
I
!=
TmpQ
.
size
(
)
;
++
I
)
{
SDNode
*
S
=
TmpQ
[
I
]
;
for
(
SDNode
*
U
:
S
->
uses
(
)
)
{
if
(
U
==
ISelN
)
continue
;
auto
F
=
NumOps
.
find
(
U
)
;
assert
(
F
!=
NumOps
.
end
(
)
)
;
if
(
F
->
second
>
0
&&
!
F
->
second
)
TmpQ
.
insert
(
F
->
first
)
;
}
}
ISel
.
ReplaceNode
(
ISelN
,
N0
)
;
assert
(
SubNodes
.
size
(
)
==
TmpQ
.
size
(
)
)
;
NullifyingVector
<
decltype
(
TmpQ
)
::
vector_type
>
Queue
(
TmpQ
.
takeVector
(
)
)
;
Deleter
DUQ
(
DAG
,
Queue
)
;
for
(
SDNode
*
S
:
reverse
(
Queue
)
)
{
if
(
S
==
nullptr
)
continue
;
DEBUG_WITH_TYPE
(
"isel"
,
{
dbgs
(
)
<<
"HVX selecting: "
;
S
->
dump
(
&
DAG
)
;
}
)
;
ISel
.
Select
(
S
)
;
}
}
</s>


<s> bool GBZ80FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return false ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> enum rtx_code ix86_fp_compare_code_to_integer ( enum rtx_code code ) { switch ( code ) { case GT : return GTU ; case GE : return GEU ; case ORDERED : case UNORDERED : return code ; case UNEQ : return EQ ; case UNLT : return LTU ; case UNLE : return LEU ; case LTGT : return NE ; default : return UNKNOWN ; } } </s>

Convert comparison codes we use to represent FP comparison to integer code that will result in proper branch . Return UNKNOWN if no such code is available .


<s> unsigned PPCDispatchGroupSBHazardRecognizer :: PreEmitNoops ( SUnit * SU ) { if ( isLoadAfterStore ( SU ) && CurSlots < 6 ) { unsigned Mcpu = DAG -> MF . getSubtarget < PPCSubtarget > ( ) . getMcpu ( ) ; if ( Mcpu == PPC :: MCPU_PWR6 || Mcpu == PPC :: MCPU_PWR7 || Mcpu == PPC :: MCPU_PWR8 || Mcpu == PPC :: MCPU_PWR9 ) return 1 ; return 5 - CurSlots ; } return ScoreboardHazardRecognizer :: PreEmitNoops ( SU ) ; } </s>

PreEmitNoops - This callback is invoked prior to emitting an instruction .


<s> bool PPCPassConfig :: addInstSelector ( ) { addPass ( createPPCISelDag ( getPPCTargetMachine ( ) ) ) ; if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCCTRLoopsVerify ( ) ) ; addPass ( createPPCVSXCopyPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> unsigned postOffset ( Align Alignment = Align :: None ( ) ) const { unsigned PO = Offset + Size ; const Align PA = std :: max ( PostAlign , Alignment ) ; if ( PA == Align :: None ( ) ) return PO ; return PO + UnknownPadding ( PA , internalKnownBits ( ) ) ; } </s>

Compute the offset immediately following this block .


<s> virtual void emitSparcRegisterIgnore ( unsigned reg ) { } </s>

Emit `` .register < reg > , # ignore '' .


<s> void riscv_set_return_address ( rtx address , rtx scratch ) { rtx slot_address ; gcc_assert ( BITSET_P ( cfun -> machine -> frame . mask , RETURN_ADDR_REGNUM ) ) ; slot_address = riscv_add_offset ( scratch , stack_pointer_rtx , cfun -> machine -> frame . gp_sp_offset ) ; riscv_emit_move ( gen_frame_mem ( GET_MODE ( address ) , slot_address ) , address ) ; } </s>

Emit code to change the current function 's return address to ADDRESS . SCRATCH is available as a scratch register , if needed . ADDRESS and SCRATCH are both word-mode GPRs .


<s> TargetPassConfig * HexagonTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new HexagonPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s>
void
SystemZPostRASchedStrategy
::
schedNode
(
SUnit
*
SU
,
bool
IsTopNode
)
{
DEBUG
(
dbgs
(
)
<<
"** Scheduling SU("
<<
SU
->
NodeNum
<<
") "
;
if
(
Available
.
size
(
)
==
1
)
dbgs
(
)
<<
"(only one) "
;
Candidate
c
(
SU
,
*
HazardRec
)
;
c
.
dumpCosts
(
)
;
dbgs
(
)
<<
"\n"
;
)
;
Available
.
erase
(
SU
)
;
HazardRec
->
EmitInstruction
(
SU
)
;
}
</s>

ScheduleDAGMI has scheduled an instruction - tell HazardRec about it .

SystemZ
SystemZ
"** Scheduling SU("
") "
1
"(only one) "
"\n"


<s> bool M88kPassConfig :: addLegalizeMachineIR ( ) { addPass ( new Legalizer ( ) ) ; return false ; } </s>

This method should install a legalize pass , which converts the instruction sequence into one that can be selected by the target .


<s> static void or1k_finish_atomic_subword ( machine_mode mode , rtx o , rtx n , rtx shift ) { n = expand_binop ( SImode , lshr_optab , n , shift , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; emit_move_insn ( o , gen_lowpart ( mode , n ) ) ; } </s>

A subroutine of the various atomic expanders . For sub-word operations , complete the operation by shifting result to the lsb of the SImode temporary and then extracting the result in MODE with a SUBREG .


"Attempted to created cross-class register copy"


"Pseudo opcode found in EmitInstruction()"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void print_operand_address ( FILE * file , rtx addr ) { rtx index ; int size ; switch ( GET_CODE ( addr ) ) { case REG : fprintf ( file , "%s" , h8_reg_names [ REGNO ( addr ) ] ) ; break ; case PRE_DEC : fprintf ( file , "-%s" , h8_reg_names [ REGNO ( XEXP ( addr , 0 ) ) ] ) ; break ; case POST_INC : fprintf ( file , "%s+" , h8_reg_names [ REGNO ( XEXP ( addr , 0 ) ) ] ) ; break ; case PRE_INC : fprintf ( file , "+%s" , h8_reg_names [ REGNO ( XEXP ( addr , 0 ) ) ] ) ; break ; case POST_DEC : fprintf ( file , "%s-" , h8_reg_names [ REGNO ( XEXP ( addr , 0 ) ) ] ) ; break ; case PLUS : fprintf ( file , "(" ) ; index = h8300_get_index ( XEXP ( addr , 0 ) , VOIDmode , & size ) ; if ( GET_CODE ( index ) == REG ) { print_operand_address ( file , XEXP ( addr , 1 ) ) ; fprintf ( file , "," ) ; switch ( size ) { case 0 : print_operand_address ( file , index ) ; break ; case 1 : print_operand ( file , index , 'X' ) ; fputs ( ".b" , file ) ; break ; case 2 : print_operand ( file , index , 'T' ) ; fputs ( ".w" , file ) ; break ; case 4 : print_operand ( file , index , 'S' ) ; fputs ( ".l" , file ) ; break ; } } else { print_operand_address ( file , XEXP ( addr , 0 ) ) ; fprintf ( file , "+" ) ; print_operand_address ( file , XEXP ( addr , 1 ) ) ; } fprintf ( file , ")" ) ; break ; case CONST_INT : { int n = INTVAL ( addr ) ; if ( TARGET_H8300 ) n = ( int ) ( short ) n ; fprintf ( file , "%d" , n ) ; break ; } default : output_addr_const ( file , addr ) ; break ; } } </s>

Print the operand address represented by the rtx addr


<s> void s390_split_access_reg ( rtx reg , rtx * lo , rtx * hi ) { gcc_assert ( TARGET_64BIT ) ; gcc_assert ( ACCESS_REG_P ( reg ) ) ; gcc_assert ( GET_MODE ( reg ) == DImode ) ; gcc_assert ( ! ( REGNO ( reg ) & 1 ) ) ; * lo = gen_rtx_REG ( SImode , REGNO ( reg ) + 1 ) ; * hi = gen_rtx_REG ( SImode , REGNO ( reg ) ) ; } </s>

Split DImode access register reference REG ( on 64-bit ) into its constituent low and high parts , and store them into LO and HI . Note that gen_lowpart/ gen_highpart can not be used as they assume all registers are word-sized , while our access registers have only half that size .


This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly


<s> int sh2a_get_function_vector_number ( rtx x ) { if ( ( GET_CODE ( x ) == SYMBOL_REF ) && ( SYMBOL_REF_FLAGS ( x ) & SYMBOL_FLAG_FUNCVEC_FUNCTION ) ) { tree t = SYMBOL_REF_DECL ( x ) ; if ( TREE_CODE ( t ) != FUNCTION_DECL ) return 0 ; for ( tree list = SH_ATTRIBUTES ( t ) ; list ; list = TREE_CHAIN ( list ) ) if ( is_attribute_p ( "function_vector" , TREE_PURPOSE ( list ) ) ) return TREE_INT_CST_LOW ( TREE_VALUE ( TREE_VALUE ( list ) ) ) ; return 0 ; } else return 0 ; } </s>

Returns the function vector number , if the attribute 'function_vector ' is assigned , otherwise returns zero .


<s> void X86FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MF . setHasWinCFI ( false ) ; const Function * Fn = MF . getFunction ( ) ; if ( ! STI . is64Bit ( ) || ! MF . hasEHFunclets ( ) || classifyEHPersonality ( Fn -> getPersonalityFn ( ) ) != EHPersonality :: MSVC_CXX ) return ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; WinEHFuncInfo & EHInfo = * MF . getWinEHFuncInfo ( ) ; int64_t MinFixedObjOffset = - SlotSize ; for ( int I = MFI . getObjectIndexBegin ( ) ; I < 0 ; ++ I ) MinFixedObjOffset = std :: min ( MinFixedObjOffset , MFI . getObjectOffset ( I ) ) ; for ( WinEHTryBlockMapEntry & TBME : EHInfo . TryBlockMap ) { for ( WinEHHandlerType & H : TBME . HandlerArray ) { int FrameIndex = H . CatchObj . FrameIndex ; if ( FrameIndex != INT_MAX ) { unsigned Align = MFI . getObjectAlignment ( FrameIndex ) ; MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % Align ; MinFixedObjOffset -= MFI . getObjectSize ( FrameIndex ) ; MFI . setObjectOffset ( FrameIndex , MinFixedObjOffset ) ; } } } MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % 8 ; int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize ; int UnwindHelpFI = MFI . CreateFixedObject ( SlotSize , UnwindHelpOffset , false ) ; EHInfo . UnwindHelpFrameIdx = UnwindHelpFI ; MachineBasicBlock & MBB = MF . front ( ) ; auto MBBI = MBB . begin ( ) ; while ( MBBI != MBB . end ( ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) ) ++ MBBI ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; addFrameReference ( BuildMI ( MBB , MBBI , DL , TII . get ( X86 :: MOV64mi32 ) ) , UnwindHelpFI ) . addImm ( - 2 ) ; } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s>
static
void
nvptx_file_start
(
void
)
{
fputs
(
"// BEGIN PREAMBLE\n"
,
asm_out_file
)
;
fputs
(
"\t.version\t"
,
asm_out_file
)
;
fputs
(
ptx_version_to_string
(
(
enum
ptx_version
)
ptx_version_option
)
,
asm_out_file
)
;
fputs
(
"\n"
,
asm_out_file
)
;
fputs
(
"\t.target\tsm_"
,
asm_out_file
)
;
fputs
(
sm_version_to_string
(
(
enum
ptx_isa
)
ptx_isa_option
)
,
asm_out_file
)
;
fputs
(
"\n"
,
asm_out_file
)
;
fprintf
(
asm_out_file
,
"\t.address_size %d\n"
,
GET_MODE_BITSIZE
(
Pmode
)
)
;
fputs
(
"// END PREAMBLE\n"
,
asm_out_file
)
;
}
</s>

Implement TARGET_ASM_FILE_START . Write the kinds of things ptxas expects at the start of a file .

nvptx
"// BEGIN PREAMBLE\n"
"\t.version\t"
"\n"
"\t.target\tsm_"
"\n"
"\t.address_size %d\n"
"// END PREAMBLE\n"


<s> static rtx mips_expand_builtin_compare ( enum mips_builtin_type builtin_type , enum insn_code icode , enum mips_fp_condition cond , rtx target , tree exp ) { rtx offset , condition , cmp_result ; if ( target == 0 || GET_MODE ( target ) != SImode ) target = gen_reg_rtx ( SImode ) ; cmp_result = mips_expand_builtin_compare_1 ( icode , cond , exp , call_expr_nargs ( exp ) ) ; switch ( builtin_type ) { case MIPS_BUILTIN_CMP_ALL : condition = gen_rtx_NE ( VOIDmode , cmp_result , constm1_rtx ) ; return mips_builtin_branch_and_move ( condition , target , const0_rtx , const1_rtx ) ; case MIPS_BUILTIN_CMP_UPPER : case MIPS_BUILTIN_CMP_LOWER : offset = GEN_INT ( builtin_type == MIPS_BUILTIN_CMP_UPPER ) ; condition = gen_single_cc ( cmp_result , offset ) ; return mips_builtin_branch_and_move ( condition , target , const1_rtx , const0_rtx ) ; default : condition = gen_rtx_NE ( VOIDmode , cmp_result , const0_rtx ) ; return mips_builtin_branch_and_move ( condition , target , const1_rtx , const0_rtx ) ; } } </s>

Expand a comparison builtin of type BUILTIN_TYPE . ICODE is the code of the comparison instruction and COND is the condition it should test . ARGLIST is the list of function arguments and TARGET , if nonnull , suggests a good place to put the boolean result .


<s> AVRSubtarget & AVRSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS , const TargetMachine & TM ) { ParseSubtargetFeatures ( CPU , CPU , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> void SparcTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { SDValue Result ; if ( Constraint . length ( ) > 1 ) return ; char ConstraintLetter = Constraint [ 0 ] ; switch ( ConstraintLetter ) { default : break ; case 'I' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isInt < 13 > ( C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ; break ; } return ; } } if ( Result . getNode ( ) ) { Ops . push_back ( Result ) ; return ; } TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; } </s>

Lower the specified operand into the Ops vector .


<s> bool X86GenericDisassembler :: getInstruction ( MCInst & instr , uint64_t & size , const MemoryObject & region , uint64_t address , raw_ostream & vStream ) const { InternalInstruction internalInstr ; int ret = decodeInstruction ( & internalInstr , regionReader , ( void * ) & region , logger , ( void * ) & vStream , address , fMode ) ; if ( ret ) { size = internalInstr . readerCursor - address ; return false ; } else { size = internalInstr . length ; return ! translateInstruction ( instr , internalInstr ) ; } } </s>

Returns the disassembly of a single instruction .


"For each split Type there should be exactly one VReg."

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> static bool ia64_cannot_force_const_mem ( rtx x ) { return tls_symbolic_operand_type ( x ) != 0 ; } </s>

Do n't allow TLS addresses to get spilled to memory .


<s>
const
char
*
host_detect_local_cpu
(
int
argc
,
const
char
*
*
argv
)
{
const
char
*
cpu
=
;
const
char
*
cache
=
""
;
const
char
*
options
=
""
;
bool
arch
;
bool
assembler
;
size_t
i
;
if
(
argc
<
1
)
return
;
arch
=
strcmp
(
argv
[
0
]
,
"cpu"
)
==
0
;
assembler
=
(
!
arch
&&
strcmp
(
argv
[
0
]
,
"asm"
)
==
0
)
;
if
(
!
arch
&&
!
assembler
&&
strcmp
(
argv
[
0
]
,
"tune"
)
)
return
;
if
(
!
assembler
)
{
cache
=
detect_caches_aix
(
)
;
cache
=
detect_caches_darwin
(
)
;
cache
=
detect_caches_freebsd
(
)
;
cache
=
""
;
cache
=
detect_caches_linux
(
)
;
cache
=
""
;
cache
=
""
;
}
cpu
=
detect_processor_aix
(
)
;
cpu
=
detect_processor_darwin
(
)
;
cpu
=
detect_processor_freebsd
(
)
;
cpu
=
detect_processor_linux
(
)
;
cpu
=
"powerpc"
;
if
(
assembler
)
{
for
(
i
=
0
;
i
<
ARRAY_SIZE
(
asm_names
)
;
i
++
)
{
if
(
!
asm_names
[
i
]
.
cpu
||
!
strcmp
(
asm_names
[
i
]
.
cpu
,
cpu
)
)
return
asm_names
[
i
]
.
asm_sw
;
}
return
;
}
return
concat
(
cache
,
"-m"
,
argv
[
0
]
,
"="
,
cpu
,
" "
,
options
,
)
;
}
</s>

This will be called by the spec parser in gcc.cc when it sees a % : local_cpu_detect ( args ) construct . Currently it will be called with either `` cpu '' or `` tune '' as argument depending on if -mcpu=native or -mtune=native is to be substituted . It returns a string containing new command line parameters to be put at the place of the above two options , depending on what CPU this is executed . E.g . `` -mcpu=ultrasparc3 '' on an UltraSPARC III for -mcpu=native . If the routine ca n't detect a known processor , the -mcpu or -mtune option is discarded . ARGC and ARGV are set depending on the actual arguments given in the spec .


<s> bool X86TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { for ( unsigned i = 0 , e = LegalFPImmediates . size ( ) ; i != e ; ++ i ) { if ( Imm . bitwiseIsEqual ( LegalFPImmediates [ i ] ) ) return true ; } return false ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> EVT BPFTargetLowering :: getSetCCResultType ( const DataLayout & , LLVMContext & , EVT VT ) const { return getHasAlu32 ( ) ? MVT :: i32 : MVT :: i64 ; } </s>

Return the value type to use for ISD : :SETCC .


<s> static std :: unique_ptr < MSP430Operand > CreateMem ( unsigned RegNum , const MCExpr * Val , SMLoc S , SMLoc E ) { return make_unique < MSP430Operand > ( RegNum , Val , S , E ) ; } </s>


<s> const FeatureBitset & getFeatures ( ) const { return Features ; } </s>

Returns the vector of individual subtarget features .


<s> bool arc_store_addr_hazard_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx in_set , out_set ; rtx out_addr , in_addr ; if ( ! producer ) return false ; if ( ! consumer ) return false ; out_set = single_set ( producer ) ; if ( out_set ) { out_addr = SET_DEST ( out_set ) ; if ( ! out_addr ) return false ; if ( GET_CODE ( out_addr ) == ZERO_EXTEND || GET_CODE ( out_addr ) == SIGN_EXTEND ) out_addr = XEXP ( out_addr , 0 ) ; if ( ! MEM_P ( out_addr ) ) return false ; in_set = single_set ( consumer ) ; if ( in_set ) { in_addr = SET_SRC ( in_set ) ; if ( ! in_addr ) return false ; if ( GET_CODE ( in_addr ) == ZERO_EXTEND || GET_CODE ( in_addr ) == SIGN_EXTEND ) in_addr = XEXP ( in_addr , 0 ) ; if ( ! MEM_P ( in_addr ) ) return false ; in_addr = XEXP ( in_addr , 0 ) ; out_addr = XEXP ( out_addr , 0 ) ; return exp_equiv_p ( in_addr , out_addr , 0 , true ) ; } } return false ; } </s>

Return true if a load instruction ( CONSUMER ) uses the same address as a store instruction ( PRODUCER ) . This function is used to avoid st/ld address hazard in ARC700 cores .


<s>
static
void
ix86_output_indirect_branch_via_push
(
rtx
call_op
,
const
char
*
xasm
,
bool
sibcall_p
)
{
char
thunk_name_buf
[
32
]
;
char
*
thunk_name
;
char
push_buf
[
64
]
;
enum
indirect_thunk_prefix
need_prefix
=
indirect_thunk_need_prefix
(
current_output_insn
)
;
int
regno
=
1
;
if
(
cfun
->
machine
->
indirect_branch_type
!=
indirect_branch_thunk_inline
)
{
if
(
cfun
->
machine
->
indirect_branch_type
==
indirect_branch_thunk
)
{
if
(
need_prefix
==
indirect_thunk_prefix_bnd
)
indirect_thunk_bnd_needed
=
true
;
else
indirect_thunk_needed
=
true
;
}
indirect_thunk_name
(
thunk_name_buf
,
regno
,
need_prefix
,
false
)
;
thunk_name
=
thunk_name_buf
;
}
else
thunk_name
=
;
snprintf
(
push_buf
,
sizeof
(
push_buf
)
,
"push{%c}\t%s"
,
TARGET_64BIT
'q'
:
'l'
,
xasm
)
;
if
(
sibcall_p
)
{
output_asm_insn
(
push_buf
,
&
call_op
)
;
if
(
thunk_name
!=
)
{
if
(
need_prefix
==
indirect_thunk_prefix_bnd
)
fprintf
(
asm_out_file
,
"\tbnd jmp\t%s\n"
,
thunk_name
)
;
else
fprintf
(
asm_out_file
,
"\tjmp\t%s\n"
,
thunk_name
)
;
}
else
output_indirect_thunk
(
need_prefix
,
regno
)
;
}
else
{
char
indirectlabel1
[
32
]
;
char
indirectlabel2
[
32
]
;
ASM_GENERATE_INTERNAL_LABEL
(
indirectlabel1
,
INDIRECT_LABEL
,
indirectlabelno
++
)
;
ASM_GENERATE_INTERNAL_LABEL
(
indirectlabel2
,
INDIRECT_LABEL
,
indirectlabelno
++
)
;
if
(
need_prefix
==
indirect_thunk_prefix_bnd
)
fputs
(
"\tbnd jmp\t"
,
asm_out_file
)
;
else
fputs
(
"\tjmp\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
indirectlabel2
)
;
fputc
(
'\n'
,
asm_out_file
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
indirectlabel1
)
;
if
(
MEM_P
(
call_op
)
)
{
struct
ix86_address
parts
;
rtx
addr
=
XEXP
(
call_op
,
0
)
;
if
(
ix86_decompose_address
(
addr
,
&
parts
)
&&
parts
.
base
==
stack_pointer_rtx
)
{
if
(
parts
.
index
)
{
addr
=
gen_rtx_MULT
(
Pmode
,
parts
.
index
,
GEN_INT
(
parts
.
scale
)
)
;
addr
=
gen_rtx_PLUS
(
Pmode
,
stack_pointer_rtx
,
addr
)
;
}
else
addr
=
stack_pointer_rtx
;
rtx
disp
;
if
(
parts
.
disp
!=
NULL_RTX
)
disp
=
plus_constant
(
Pmode
,
parts
.
disp
,
UNITS_PER_WORD
)
;
else
disp
=
GEN_INT
(
UNITS_PER_WORD
)
;
addr
=
gen_rtx_PLUS
(
Pmode
,
addr
,
disp
)
;
call_op
=
gen_rtx_MEM
(
GET_MODE
(
call_op
)
,
addr
)
;
}
}
output_asm_insn
(
push_buf
,
&
call_op
)
;
if
(
thunk_name
!=
)
{
if
(
need_prefix
==
indirect_thunk_prefix_bnd
)
fprintf
(
asm_out_file
,
"\tbnd jmp\t%s\n"
,
thunk_name
)
;
else
fprintf
(
asm_out_file
,
"\tjmp\t%s\n"
,
thunk_name
)
;
}
else
output_indirect_thunk
(
need_prefix
,
regno
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
indirectlabel2
)
;
if
(
need_prefix
==
indirect_thunk_prefix_bnd
)
fputs
(
"\tbnd call\t"
,
asm_out_file
)
;
else
fputs
(
"\tcall\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
indirectlabel1
)
;
fputc
(
'\n'
,
asm_out_file
)
;
}
}
</s>

Output indirect branch via a call and return thunk . CALL_OP is the branch target . XASM is the assembly template for CALL_OP . Branch is a tail call if SIBCALL_P is true . A normal call is converted to : jmp L2 L1 : push CALL_OP jmp __x86_indirect_thunk L2 : call L1 and a tail call is converted to : push CALL_OP jmp __x86_indirect_thunk


<s> bool X86InstrInfo :: analyzeBranchPredicate ( MachineBasicBlock & MBB , MachineBranchPredicate & MBP , bool AllowModify ) const { using namespace std :: placeholders ; SmallVector < MachineOperand , 4 > Cond ; SmallVector < MachineInstr * , 4 > CondBranches ; if ( AnalyzeBranchImpl ( MBB , MBP . TrueDest , MBP . FalseDest , Cond , CondBranches , AllowModify ) ) return true ; if ( Cond . size ( ) != 1 ) return true ; assert ( MBP . TrueDest && "expected!" ) ; if ( ! MBP . FalseDest ) MBP . FalseDest = MBB . getNextNode ( ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; MachineInstr * ConditionDef = nullptr ; bool SingleUseCondition = true ; for ( MachineInstr & MI : llvm :: drop_begin ( llvm :: reverse ( MBB ) ) ) { if ( MI . modifiesRegister ( X86 :: EFLAGS , TRI ) ) { ConditionDef = & MI ; break ; } if ( MI . readsRegister ( X86 :: EFLAGS , TRI ) ) SingleUseCondition = false ; } if ( ! ConditionDef ) return true ; if ( SingleUseCondition ) { for ( auto * Succ : MBB . successors ( ) ) if ( Succ -> isLiveIn ( X86 :: EFLAGS ) ) SingleUseCondition = false ; } MBP . ConditionDef = ConditionDef ; MBP . SingleUseCondition = SingleUseCondition ; const unsigned TestOpcode = Subtarget . is64Bit ( ) ? X86 :: TEST64rr : X86 :: TEST32rr ; if ( ConditionDef -> getOpcode ( ) == TestOpcode && ConditionDef -> getNumOperands ( ) == 3 && ConditionDef -> getOperand ( 0 ) . isIdenticalTo ( ConditionDef -> getOperand ( 1 ) ) && ( Cond [ 0 ] . getImm ( ) == X86 :: COND_NE || Cond [ 0 ] . getImm ( ) == X86 :: COND_E ) ) { MBP . LHS = ConditionDef -> getOperand ( 0 ) ; MBP . RHS = MachineOperand :: CreateImm ( 0 ) ; MBP . Predicate = Cond [ 0 ] . getImm ( ) == X86 :: COND_NE ? MachineBranchPredicate :: PRED_NE : MachineBranchPredicate :: PRED_EQ ; return false ; } return true ; } </s>

Analyze the branching code at the end of MBB and parse it into the MachineBranchPredicate structure if possible .


<s> unsigned RISCVInstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { if ( BytesRemoved ) * BytesRemoved = 0 ; MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return 0 ; if ( ! I -> getDesc ( ) . isUnconditionalBranch ( ) && ! I -> getDesc ( ) . isConditionalBranch ( ) ) return 0 ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return 1 ; -- I ; if ( ! I -> getDesc ( ) . isConditionalBranch ( ) ) return 1 ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ; return 2 ; } </s>

Remove the branching code at the end of the specific MBB .


<s> const MCPhysReg * ARM64TargetLowering :: getScratchRegisters ( CallingConv :: ID ) const { static const MCPhysReg ScratchRegs [ ] = { ARM64 :: X16 , ARM64 :: X17 , ARM64 :: LR , 0 } ; return ScratchRegs ; } </s>

Returns a 0 terminated array of registers that can be safely used as scratch registers .


<s> static void sh_encode_section_info ( tree decl , rtx rtl , int first ) { default_encode_section_info ( decl , rtl , first ) ; if ( TREE_CODE ( decl ) == FUNCTION_DECL && sh2a_function_vector_p ( decl ) && TARGET_SH2A ) SYMBOL_REF_FLAGS ( XEXP ( rtl , 0 ) ) |= SYMBOL_FLAG_FUNCVEC_FUNCTION ; } </s>

Encode symbol attributes of a SYMBOL_REF into its SYMBOL_REF_FLAGS .


"Lower aggregate copies/intrinsics into loops"

getPassName - Return a nice clean name for a pass .


<s> bool X86TargetLowering :: isTruncateFree ( EVT VT1 , EVT VT2 ) const { if ( ! VT1 . isInteger ( ) || ! VT2 . isInteger ( ) ) return false ; unsigned NumBits1 = VT1 . getSizeInBits ( ) ; unsigned NumBits2 = VT2 . getSizeInBits ( ) ; if ( NumBits1 <= NumBits2 ) return false ; return Subtarget -> is64Bit ( ) || NumBits1 < 64 ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s>
LLVM_DUMP_METHOD
void
dump
(
)
{
errs
(
)
<<
"MSP430ISelAddressMode "
<<
this
<<
'\n'
;
if
(
BaseType
==
RegBase
&&
Base
.
Reg
.
getNode
(
)
!=
nullptr
)
{
errs
(
)
<<
"Base.Reg "
;
Base
.
Reg
.
getNode
(
)
->
dump
(
)
;
}
else
if
(
BaseType
==
FrameIndexBase
)
{
errs
(
)
<<
" Base.FrameIndex "
<<
Base
.
FrameIndex
<<
'\n'
;
}
errs
(
)
<<
" Disp "
<<
Disp
<<
'\n'
;
if
(
GV
)
{
errs
(
)
<<
"GV "
;
GV
->
dump
(
)
;
}
else
if
(
CP
)
{
errs
(
)
<<
" CP "
;
CP
->
dump
(
)
;
errs
(
)
<<
" Align"
<<
Align
<<
'\n'
;
}
else
if
(
ES
)
{
errs
(
)
<<
"ES "
;
errs
(
)
<<
ES
<<
'\n'
;
}
else
if
(
JT
!=
1
)
errs
(
)
<<
" JT"
<<
JT
<<
" Align"
<<
Align
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

MSP430
"MSP430ISelAddressMode "
"Base.Reg "
" Base.FrameIndex "
" Disp "
"GV "
" CP "
" Align"
"ES "
1
" JT"
" Align"


<s> TargetLowering :: ConstraintWeight MipsTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'd' : case 'y' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( Subtarget . hasMSA ( ) && type -> isVectorTy ( ) && type -> getPrimitiveSizeInBits ( ) . getFixedSize ( ) == 128 ) weight = CW_Register ; else if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; case 'c' : case 'l' : case 'x' : if ( type -> isIntegerTy ( ) ) weight = CW_SpecificReg ; break ; case 'I' : case 'J' : case 'K' : case 'L' : case 'N' : case 'O' : case 'P' : if ( isa < ConstantInt > ( CallOperandVal ) ) weight = CW_Constant ; break ; case 'R' : weight = CW_Memory ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> static rtx xtensa_function_incoming_arg ( cumulative_args_t cum , const function_arg_info & arg ) { return xtensa_function_arg_1 ( cum , arg , true ) ; } </s>


<s>
void
addInst
(
MachineInstr
*
MI
,
SetVector
<
MachineInstr
*
>
&
Preds
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM Loops: Adding predicated MI: "
<<
*
MI
)
;
if
(
!
Divergent
&&
!
set_difference
(
Preds
,
VPST
->
Predicates
)
.
empty
(
)
)
{
Divergent
=
&
Insts
.
back
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
" - has divergent predicate: "
<<
*
Divergent
->
MI
)
;
}
Insts
.
emplace_back
(
MI
,
Preds
)
;
assert
(
Insts
.
size
(
)
<=
4
&&
"Too many instructions in VPT block!"
)
;
}
</s>

ARM
"ARM Loops: Adding predicated MI: "
" - has divergent predicate: "
4
"Too many instructions in VPT block!"


<s> static MipsABIInfo Unknown ( ) { return MipsABIInfo ( ABI :: Unknown ) ; } </s>

The kind of location description being produced . More ...


<s>
const
char
*
getPassName
(
)
const
override
{
return
"AMDGPU Always Inline Pass"
;
}
</s>


<s> const J2InstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> bool SystemZTTIImpl :: hasDivRemOp ( Type * DataType , bool IsSigned ) { EVT VT = TLI -> getValueType ( DL , DataType ) ; return ( VT . isScalarInteger ( ) && TLI -> isTypeLegal ( VT ) ) ; } </s>

Return true if the target has a unified operation to calculate division and remainder .


<s> int sparc_split_reg_reg_legitimate ( rtx reg1 , rtx reg2 ) { gcc_assert ( reload_completed ) ; if ( GET_CODE ( reg1 ) == SUBREG ) reg1 = SUBREG_REG ( reg1 ) ; if ( GET_CODE ( reg1 ) != REG ) return 0 ; const int regno1 = REGNO ( reg1 ) ; if ( GET_CODE ( reg2 ) == SUBREG ) reg2 = SUBREG_REG ( reg2 ) ; if ( GET_CODE ( reg2 ) != REG ) return 0 ; const int regno2 = REGNO ( reg2 ) ; if ( SPARC_INT_REG_P ( regno1 ) && SPARC_INT_REG_P ( regno2 ) ) return 1 ; if ( TARGET_VIS3 ) { if ( ( SPARC_INT_REG_P ( regno1 ) && SPARC_FP_REG_P ( regno2 ) ) || ( SPARC_FP_REG_P ( regno1 ) && SPARC_INT_REG_P ( regno2 ) ) ) return 1 ; } return 0 ; } </s>

Like sparc_split_reg_mem_legitimate but for REG < -- > REG moves .


<s> unsigned SystemZInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case SystemZ :: MOV32rm : case SystemZ :: MOV32rmy : case SystemZ :: MOV64rm : case SystemZ :: MOVSX32rm8 : case SystemZ :: MOVSX32rm16y : case SystemZ :: MOVSX64rm8 : case SystemZ :: MOVSX64rm16 : case SystemZ :: MOVSX64rm32 : case SystemZ :: MOVZX32rm8 : case SystemZ :: MOVZX32rm16 : case SystemZ :: MOVZX64rm8 : case SystemZ :: MOVZX64rm16 : case SystemZ :: MOVZX64rm32 : case SystemZ :: FMOV32rm : case SystemZ :: FMOV32rmy : case SystemZ :: FMOV64rm : case SystemZ :: FMOV64rmy : case SystemZ :: MOV64Prm : case SystemZ :: MOV64Prmy : case SystemZ :: MOV128rm : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 3 ) . isReg ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 && MI -> getOperand ( 3 ) . getReg ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s>
std
::
string
str
(
)
const
{
std
::
string
S
;
raw_string_ostream
OS
(
S
)
;
OS
<<
"{"
;
StartInst
->
print
(
OS
,
,
true
)
;
OS
<<
" -> "
;
LastInst
->
print
(
OS
,
,
true
)
;
if
(
KillInst
)
{
OS
<<
" (kill @ "
;
KillInst
->
print
(
OS
,
,
true
)
;
OS
<<
")"
;
}
OS
<<
"}"
;
return
OS
.
str
(
)
;
}
</s>

Return the twine contents as a std : :string .


<s> TargetPassConfig * ARMBaseTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new ARMPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


"Couldn't get MachineMemOperand for store to stack."

"Only support 4-byte loads from stack now."

"Only support GPR32 stores to stack now."

Load the specified register of the given register class from the specified stack frame index .


<s> SDValue SystemZTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ZERO_EXTEND : return combineZERO_EXTEND ( N , DCI ) ; case ISD :: SIGN_EXTEND : return combineSIGN_EXTEND ( N , DCI ) ; case ISD :: SIGN_EXTEND_INREG : return combineSIGN_EXTEND_INREG ( N , DCI ) ; case SystemZISD :: MERGE_HIGH : case SystemZISD :: MERGE_LOW : return combineMERGE ( N , DCI ) ; case ISD :: LOAD : return combineLOAD ( N , DCI ) ; case ISD :: STORE : return combineSTORE ( N , DCI ) ; case ISD :: VECTOR_SHUFFLE : return combineVECTOR_SHUFFLE ( N , DCI ) ; case ISD :: EXTRACT_VECTOR_ELT : return combineEXTRACT_VECTOR_ELT ( N , DCI ) ; case SystemZISD :: JOIN_DWORDS : return combineJOIN_DWORDS ( N , DCI ) ; case ISD :: STRICT_FP_ROUND : case ISD :: FP_ROUND : return combineFP_ROUND ( N , DCI ) ; case ISD :: STRICT_FP_EXTEND : case ISD :: FP_EXTEND : return combineFP_EXTEND ( N , DCI ) ; case ISD :: SINT_TO_FP : case ISD :: UINT_TO_FP : return combineINT_TO_FP ( N , DCI ) ; case ISD :: BSWAP : return combineBSWAP ( N , DCI ) ; case SystemZISD :: BR_CCMASK : return combineBR_CCMASK ( N , DCI ) ; case SystemZISD :: SELECT_CCMASK : return combineSELECT_CCMASK ( N , DCI ) ; case SystemZISD :: GET_CCMASK : return combineGET_CCMASK ( N , DCI ) ; case ISD :: SDIV : case ISD :: UDIV : case ISD :: SREM : case ISD :: UREM : return combineIntDIVREM ( N , DCI ) ; case ISD :: INTRINSIC_W_CHAIN : case ISD :: INTRINSIC_VOID : return combineINTRINSIC ( N , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> static void ia64_option_override ( void ) { unsigned int i ; cl_deferred_option * opt ; vec < cl_deferred_option > * v = ( vec < cl_deferred_option > * ) ia64_deferred_options ; if ( v ) FOR_EACH_VEC_ELT ( * v , i , opt ) { switch ( opt -> opt_index ) { case OPT_mfixed_range_ : fix_range ( opt -> arg ) ; break ; default : gcc_unreachable ( ) ; } } if ( TARGET_AUTO_PIC ) target_flags |= MASK_CONST_GP ; if ( optimize >= 3 ) flag_ira_loop_pressure = 1 ; ia64_section_threshold = ( global_options_set . x_g_switch_value ? g_switch_value : IA64_DEFAULT_GVALUE ) ; init_machine_status = ia64_init_machine_status ; if ( align_functions <= 0 ) align_functions = 64 ; if ( align_loops <= 0 ) align_loops = 32 ; if ( TARGET_ABI_OPEN_VMS ) flag_no_common = 1 ; ia64_override_options_after_change ( ) ; } </s>


<s>
void
HexagonMCCodeEmitter
::
encodeInstruction
(
MCInst
const
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
MCSubtargetInfo
const
&
STI
)
const
{
MCInst
&
HMB
=
const_cast
<
MCInst
&
>
(
MI
)
;
assert
(
HexagonMCInstrInfo
::
isBundle
(
HMB
)
)
;
DEBUG
(
dbgs
(
)
<<
"Encoding bundle\n"
;
)
;
*
Addend
=
0
;
*
Extended
=
false
;
*
CurrentBundle
=
&
MI
;
size_t
Instruction
=
0
;
size_t
Last
=
HexagonMCInstrInfo
::
bundleSize
(
HMB
)
1
;
for
(
auto
&
I
:
HexagonMCInstrInfo
::
bundleInstructions
(
HMB
)
)
{
MCInst
&
HMI
=
const_cast
<
MCInst
&
>
(
*
I
.
getInst
(
)
)
;
EncodeSingleInstruction
(
HMI
,
OS
,
Fixups
,
STI
,
parseBits
(
Instruction
,
Last
,
HMB
,
HMI
)
,
Instruction
)
;
*
Extended
=
HexagonMCInstrInfo
::
isImmext
(
HMI
)
;
*
Addend
+=
HEXAGON_INSTR_SIZE
;
++
Instruction
;
}
return
;
}
</s>

Encode the given Inst to bytes and append to CB .

Hexagon
Hexagon
Hexagon
"Encoding bundle\n"
0
0
Hexagon
1
Hexagon
Hexagon


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < Z80oldSubtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


"Can only insert epilog into returning blocks"


<s> SDNode * SparcDAGToDAGISel :: getGlobalBaseReg ( ) { MachineFunction * MF = BB -> getParent ( ) ; unsigned GlobalBaseReg = TM . getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI . getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static int riscv_register_move_cost ( machine_mode mode , reg_class_t from , reg_class_t to ) { if ( ( from == FP_REGS && to == GR_REGS ) || ( from == GR_REGS && to == FP_REGS ) ) return tune_param -> fmv_cost ; return riscv_secondary_memory_needed ( mode , from , to ) ? 8 : 2 ; } </s>


<s> bool writeNopData ( raw_ostream & OS , uint64_t Count ) const override { if ( ( Count % 2 ) != 0 ) { return false ; } for ( uint64_t i = 0 ; i < Count ; i += 2 ) { OS . write ( 0x00 ) ; OS . write ( 0x01 ) ; } return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Alpha Branch Selection"
;
}
</s>


<s>
void
Thumb1InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
DebugLoc
::
getUnknownLoc
(
)
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
assert
(
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
PseudoSourceValue
::
getFixedStack
(
FI
)
,
MachineMemOperand
::
MOStore
,
0
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tSpill
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .

ARM
ARM::tGPRRegisterClass
ARM
"Unknown regclass!"
ARM::tGPRRegisterClass
ARM
0
ARM::tSpill
0


<s> static void ix86_adjust_counter ( rtx countreg , HOST_WIDE_INT value ) { emit_insn ( gen_add2_insn ( countreg , GEN_INT ( - value ) ) ) ; } </s>


<s> static bool legitimate_scaled_address_p ( machine_mode mode , rtx op , bool strict ) { if ( GET_CODE ( op ) != PLUS ) return false ; if ( GET_CODE ( XEXP ( op , 0 ) ) != MULT ) return false ; if ( ! RTX_OK_FOR_INDEX_P ( XEXP ( XEXP ( op , 0 ) , 0 ) , strict ) ) return false ; if ( ! CONST_INT_P ( XEXP ( XEXP ( op , 0 ) , 1 ) ) ) return false ; switch ( GET_MODE_SIZE ( mode ) ) { case 2 : if ( INTVAL ( XEXP ( XEXP ( op , 0 ) , 1 ) ) != 2 ) return false ; break ; case 8 : if ( ! TARGET_LL64 ) return false ; case 4 : if ( INTVAL ( XEXP ( XEXP ( op , 0 ) , 1 ) ) != 4 ) return false ; default : return false ; } if ( RTX_OK_FOR_BASE_P ( XEXP ( op , 1 ) , ( strict ) ) ) return true ; if ( flag_pic ) { if ( CONST_INT_P ( XEXP ( op , 1 ) ) ) return true ; return false ; } if ( CONSTANT_P ( XEXP ( op , 1 ) ) ) { if ( GET_CODE ( XEXP ( op , 1 ) ) == SYMBOL_REF && SYMBOL_REF_SMALL_P ( XEXP ( op , 1 ) ) ) return false ; return true ; } return false ; } </s>


<s> void Warning ( SMLoc L , const Twine & Msg ) { getParser ( ) . Warning ( L , Msg ) ; } </s>

Emit a warning at the location L , with the message Msg .


" was Pass-through, is now Dirty-out.\n"


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < TL45Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>


<s> static void core2i7_first_cycle_multipass_end ( const void * _data ) { const_ix86_first_cycle_multipass_data_t data = ( const_ix86_first_cycle_multipass_data_t ) _data ; ix86_first_cycle_multipass_data_t next_data = ix86_first_cycle_multipass_data ; if ( data != NULL ) { next_data -> ifetch_block_len = data -> ifetch_block_len ; next_data -> ifetch_block_n_insns = data -> ifetch_block_n_insns ; } } </s>

Save the result of multipass lookahead scheduling for the next round .


<s> bool aarch64_and_bitmask_imm ( unsigned HOST_WIDE_INT val_in , machine_mode mode ) { if ( aarch64_bitmask_imm ( val_in , mode ) ) return false ; if ( aarch64_move_imm ( val_in , mode ) ) return false ; unsigned HOST_WIDE_INT imm2 = aarch64_and_split_imm2 ( val_in ) ; return aarch64_bitmask_imm ( imm2 , mode ) ; } </s>

Return true if VAL_IN is a valid 'and ' bitmask immediate .


<s> void * getAdjustedAnalysisPointer ( const void * ID ) override { if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo * ) this ; return this ; } </s>

getAdjustedAnalysisPointer - This method is used when a pass implements an analysis interface through multiple inheritance .


"WDC_TODO - This method is probably implemented wrong..."


<s> static int mt_add_branches ( rtx * x , void * insn ) { if ( GET_CODE ( * x ) == LABEL_REF ) { branch_info * branch = xmalloc ( sizeof ( * branch ) ) ; rtx label = XEXP ( * x , 0 ) ; label_info * info ; for ( info = mt_labels ; info ; info = info -> next ) if ( info -> label == label ) break ; if ( ! info ) { info = xmalloc ( sizeof ( * info ) ) ; info -> next = mt_labels ; mt_labels = info ; info -> label = label ; info -> branches = NULL ; } branch -> next = info -> branches ; info -> branches = branch ; branch -> insn = insn ; } return 0 ; } </s>

If * X is a label , add INSN to the list of branches for that label .


<s> bool aarch64_atomic_ldop_supported_p ( enum rtx_code code ) { if ( ! TARGET_LSE ) return false ; switch ( code ) { case SET : case AND : case IOR : case XOR : case MINUS : case PLUS : return true ; default : return false ; } } </s>

Test whether the target supports using a atomic load-operate instruction . CODE is the operation and AFTER is TRUE if the data in memory after the operation should be returned and FALSE if the data before the operation should be returned . Returns FALSE if the operation is n't supported by the architecture .


<s> void LC3InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( LC3 :: ADDrr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( 0 ) ; } </s>


<s>
unsigned
PPCInstrInfo
::
reduceLoopCount
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
&
PreHeader
,
MachineInstr
*
IndVar
,
MachineInstr
&
Cmp
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
SmallVectorImpl
<
MachineInstr
*
>
&
PrevInsts
,
unsigned
Iter
,
unsigned
MaxIter
)
const
{
assert
(
(
!
IndVar
)
&&
isBDNZ
(
Cmp
.
getOpcode
(
)
)
&&
"Expecting a CTR loop"
)
;
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
DebugLoc
DL
=
Cmp
.
getDebugLoc
(
)
;
MachineInstr
*
Loop
=
findLoopInstr
(
PreHeader
)
;
if
(
!
Loop
)
return
0
;
Register
LoopCountReg
=
Loop
->
getOperand
(
0
)
.
getReg
(
)
;
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
MachineInstr
*
LoopCount
=
MRI
.
getUniqueVRegDef
(
LoopCountReg
)
;
if
(
!
LoopCount
)
return
0
;
if
(
LoopCount
->
getOpcode
(
)
==
PPC
::
LI8
||
LoopCount
->
getOpcode
(
)
==
PPC
::
LI
)
{
int64_t
Offset
=
LoopCount
->
getOperand
(
1
)
.
getImm
(
)
;
if
(
Offset
<=
1
)
{
LoopCount
->
eraseFromParent
(
)
;
Loop
->
eraseFromParent
(
)
;
return
0
;
}
LoopCount
->
getOperand
(
1
)
.
setImm
(
Offset
1
)
;
return
Offset
1
;
}
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
0
)
)
;
Cond
.
push_back
(
MachineOperand
::
CreateReg
(
Subtarget
.
isPPC64
(
)
PPC
::
CTR8
:
PPC
::
CTR
,
true
)
)
;
return
LoopCountReg
;
}
</s>

Generate code to reduce the loop iteration by one and check if the loop is finished .


<s> void SparcTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , APInt & KnownZero , APInt & KnownOne , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { APInt KnownZero2 , KnownOne2 ; KnownZero = KnownOne = APInt ( KnownZero . getBitWidth ( ) , 0 ) ; switch ( Op . getOpcode ( ) ) { default : break ; case SPISD :: SELECT_ICC : case SPISD :: SELECT_XCC : case SPISD :: SELECT_FCC : DAG . computeKnownBits ( Op . getOperand ( 1 ) , KnownZero , KnownOne , Depth + 1 ) ; DAG . computeKnownBits ( Op . getOperand ( 0 ) , KnownZero2 , KnownOne2 , Depth + 1 ) ; KnownOne &= KnownOne2 ; KnownZero &= KnownZero2 ; break ; } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> TargetIRAnalysis AArch64TargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( const Function & F ) { return TargetTransformInfo ( AArch64TTIImpl ( this , F ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


<s> const MipsSubtarget * MipsTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool hasMips16Attr = ! F . getFnAttribute ( "mips16" ) . hasAttribute ( Attribute :: None ) ; bool hasNoMips16Attr = ! F . getFnAttribute ( "nomips16" ) . hasAttribute ( Attribute :: None ) ; Attribute SFAttr = F . getFnAttribute ( "use-soft-float" ) ; bool softFloat = ! SFAttr . hasAttribute ( Attribute :: None ) ? SFAttr . getValueAsString ( ) == "true" : Options . UseSoftFloat ; if ( hasMips16Attr ) FS += FS . empty ( ) ? "+mips16" : ",+mips16" ; else if ( hasNoMips16Attr ) FS += FS . empty ( ) ? "-mips16" : ",-mips16" ; auto & I = SubtargetMap [ CPU + FS + ( softFloat ? "use-soft-float=true" : "use-soft-float=false" ) ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < MipsSubtarget > ( TargetTriple , CPU , FS , isLittle , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

Mips Mips Mips "target-cpu" "target-features" Mips "mips16" Mips "nomips16" "use-soft-float" "true" Mips "+mips16" ",+mips16" Mips "-mips16" ",-mips16" "use-soft-float=true" "use-soft-float=false" Mips


<s>
const
char
*
WebAssemblyAsmPrinter
::
toString
(
Type
*
Ty
)
const
{
switch
(
Ty
->
getTypeID
(
)
)
{
default
:
break
;
case
Type
::
PointerTyID
:
switch
(
getPointerSize
(
)
)
{
case
4
:
return
"i32"
;
case
8
:
return
"i64"
;
default
:
llvm_unreachable
(
"unsupported pointer size"
)
;
}
break
;
case
Type
::
FloatTyID
:
return
"f32"
;
case
Type
::
DoubleTyID
:
return
"f64"
;
case
Type
::
IntegerTyID
:
switch
(
Ty
->
getIntegerBitWidth
(
)
)
{
case
8
:
return
"i8"
;
case
16
:
return
"i16"
;
case
32
:
return
"i32"
;
case
64
:
return
"i64"
;
default
:
break
;
}
}
DEBUG
(
dbgs
(
)
<<
"Invalid type "
;
Ty
->
print
(
dbgs
(
)
)
;
dbgs
(
)
<<
'\n'
)
;
llvm_unreachable
(
"invalid type"
)
;
return
"<invalid>"
;
}
</s>

Convert to a decimal representation in a string .


<s> bool AArch64CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { if ( isa < ScalableVectorType > ( Arg . getType ( ) ) ) return false ; if ( DL . getTypeStoreSize ( Arg . getType ( ) ) . isZero ( ) ) continue ; ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , F . getCallingConv ( ) ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; AArch64FunctionInfo * FuncInfo = MF . getInfo < AArch64FunctionInfo > ( ) ; uint64_t StackOffset = Handler . StackUsed ; if ( F . isVarArg ( ) ) { auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; if ( ! Subtarget . isTargetDarwin ( ) ) { return false ; } StackOffset = alignTo ( Handler . StackUsed , Subtarget . isTargetILP32 ( ) ? 4 : 8 ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( 4 , StackOffset , true ) ) ; } if ( doesCalleeRestoreStack ( F . getCallingConv ( ) , MF . getTarget ( ) . Options . GuaranteedTailCallOpt ) ) { StackOffset = alignTo ( StackOffset , 16 ) ; FuncInfo -> setArgumentStackToRestore ( StackOffset ) ; } FuncInfo -> setBytesInStackArgArea ( StackOffset ) ; auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; if ( Subtarget . hasCustomCallingConv ( ) ) Subtarget . getRegisterInfo ( ) -> UpdateCustomCalleeSavedRegs ( MF ) ; handleMustTailForwardedRegisters ( MIRBuilder , AssignFn ) ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s>
std
::
string
MBlazeIntrinsicInfo
::
getName
(
unsigned
IntrID
,
Type
*
*
Tys
,
unsigned
numTys
)
const
{
static
const
char
*
const
names
[
]
=
{
}
;
assert
(
!
isOverloaded
(
IntrID
)
&&
"MBlaze intrinsics are not overloaded"
)
;
if
(
IntrID
<
Intrinsic
::
num_intrinsics
)
return
0
;
assert
(
IntrID
<
mblazeIntrinsic
::
num_mblaze_intrinsics
&&
"Invalid intrinsic ID"
)
;
std
::
string
Result
(
names
[
IntrID
Intrinsic
::
num_intrinsics
]
)
;
return
Result
;
}
</s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> static bool set_to_load_agen ( rtx_insn * out_insn , rtx_insn * in_insn ) { rtx out_set , in_set ; out_set = single_set ( out_insn ) ; if ( out_set ) { in_set = single_set ( in_insn ) ; if ( in_set ) return reg_mentioned_p ( SET_DEST ( out_set ) , SET_SRC ( in_set ) ) ; } return false ; } </s>

The function returns true if out_inst sets a value that is used in the address generation computation of in_insn


<s> EVT SITargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & Ctx , EVT VT ) const { if ( ! VT . isVector ( ) ) { return MVT :: i1 ; } return EVT :: getVectorVT ( Ctx , MVT :: i1 , VT . getVectorNumElements ( ) ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> static void handle_attr_preserve ( function * fn ) { basic_block bb ; rtx_insn * insn ; FOR_EACH_BB_FN ( bb , fn ) { FOR_BB_INSNS ( bb , insn ) { if ( ! NONJUMP_INSN_P ( insn ) ) continue ; rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) != SET ) continue ; start_sequence ( ) ; for ( int i = 0 ; i < 2 ; i ++ ) { rtx mem = XEXP ( pat , i ) ; if ( MEM_P ( mem ) ) { tree expr = MEM_EXPR ( mem ) ; if ( ! expr ) continue ; if ( TREE_CODE ( expr ) == MEM_REF && TREE_CODE ( TREE_OPERAND ( expr , 0 ) ) == SSA_NAME ) { gimple * def_stmt = SSA_NAME_DEF_STMT ( TREE_OPERAND ( expr , 0 ) ) ; if ( def_stmt && is_gimple_assign ( def_stmt ) ) expr = gimple_assign_rhs1 ( def_stmt ) ; } if ( is_attr_preserve_access ( expr ) ) maybe_make_core_relo ( expr , BPF_RELO_FIELD_BYTE_OFFSET ) ; } } rtx_insn * seq = get_insns ( ) ; end_sequence ( ) ; emit_insn_before ( seq , insn ) ; } } } </s>

The body of pass_bpf_core_attr . Scan RTL for accesses to structs/unions marked with __attribute__ ( ( preserve_access_index ) ) and generate a CO-RE relocation for any such access .


<s> static bool tilegx_legitimate_address_p ( machine_mode ARG_UNUSED ( mode ) , rtx x , bool strict ) { if ( GET_CODE ( x ) == SUBREG ) x = SUBREG_REG ( x ) ; switch ( GET_CODE ( x ) ) { case POST_INC : case POST_DEC : if ( GET_MODE_SIZE ( GET_MODE ( x ) ) > UNITS_PER_WORD ) return false ; x = XEXP ( x , 0 ) ; break ; case POST_MODIFY : if ( GET_MODE_SIZE ( GET_MODE ( x ) ) > UNITS_PER_WORD ) return false ; if ( GET_CODE ( XEXP ( x , 1 ) ) != PLUS ) return false ; if ( ! rtx_equal_p ( XEXP ( x , 0 ) , XEXP ( XEXP ( x , 1 ) , 0 ) ) ) return false ; if ( ! satisfies_constraint_I ( XEXP ( XEXP ( x , 1 ) , 1 ) ) ) return false ; x = XEXP ( x , 0 ) ; break ; case REG : break ; default : return false ; } if ( ! REG_P ( x ) ) return false ; if ( strict ) return REGNO_OK_FOR_BASE_P ( REGNO ( x ) ) ; else return true ; } </s>

Return true if the rtx X can be used as an address operand .


Pass or return a composite value in the FPR pair REGNO and REGNO + 1 . MODE is the mode of the composite . MODE1 and OFFSET1 are the mode and byte offset for the first value , likewise MODE2 and OFFSET2 for the second value .


<s> void ARMElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { const ARMBaseTargetMachine & ARM_TM = static_cast < const ARMBaseTargetMachine & > ( TM ) ; bool isAAPCS_ABI = ARM_TM . TargetABI == ARMBaseTargetMachine :: ARMABI :: ARM_ABI_AAPCS ; bool genExecuteOnly = ARM_TM . getMCSubtargetInfo ( ) -> hasFeature ( ARM :: FeatureExecuteOnly ) ; TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( isAAPCS_ABI ) ; if ( isAAPCS_ABI ) { LSDASection = nullptr ; } if ( genExecuteOnly ) { unsigned Type = ELF :: SHT_PROGBITS ; unsigned Flags = ELF :: SHF_EXECINSTR | ELF :: SHF_ALLOC | ELF :: SHF_ARM_PURECODE ; TextSection = Ctx . getELFSection ( ".text" , Type , Flags , 0 , "" , 0U ) ; } } </s>

This method must be called before any actual lowering is done .

ARM ARM ARM ARM ARM ARM ARM ARMABI::ARM_ABI_AAPCS ARM ARM::FeatureExecuteOnly ARM ".text" 0 "" 0U


<s> rtx get_avl_type_rtx ( enum avl_type type ) { return gen_int_mode ( type , Pmode ) ; } </s>


<s> rtx resolve_reload_operand ( rtx op ) { if ( reload_in_progress ) { rtx tmp = op ; if ( SUBREG_P ( tmp ) ) tmp = SUBREG_REG ( tmp ) ; if ( REG_P ( tmp ) && REGNO ( tmp ) >= FIRST_PSEUDO_REGISTER ) { op = reg_equiv_memory_loc ( REGNO ( tmp ) ) ; if ( op == 0 ) return 0 ; } } return op ; } </s>

Used by aligned_memory_operand and unaligned_memory_operand to resolve what reload is going to do with OP if it 's a register .


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) -> findAssociatedFragment ( ) ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s> bool PPCInstrInfo :: isPredicated ( const MachineInstr & MI ) const { return false ; } </s>

Returns true if the instruction is already predicated .


<s> bool GCNTTIImpl :: isSourceOfDivergence ( const Value * V ) const { if ( const Argument * A = dyn_cast < Argument > ( V ) ) return ! isArgPassedInSGPR ( A ) ; if ( const LoadInst * Load = dyn_cast < LoadInst > ( V ) ) return Load -> getPointerAddressSpace ( ) == ST -> getAMDGPUAS ( ) . PRIVATE_ADDRESS ; if ( isa < AtomicRMWInst > ( V ) || isa < AtomicCmpXchgInst > ( V ) ) return true ; if ( const IntrinsicInst * Intrinsic = dyn_cast < IntrinsicInst > ( V ) ) return AMDGPU :: isIntrinsicSourceOfDivergence ( Intrinsic -> getIntrinsicID ( ) ) ; if ( isa < CallInst > ( V ) || isa < InvokeInst > ( V ) ) return true ; return false ; } </s>

Returns whether V is a source of divergence .


<s> void PPCRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { unsigned ADDriOpc = Subtarget . isPPC64 ( ) ? PPC :: ADDI8 : PPC :: ADDI ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , 0 , this , MF ) ) ; BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .


<s> static rtx nds32_expand_builtin_load ( enum insn_code icode , tree exp , rtx target ) { rtx pat ; rtx op0 = nds32_read_argument ( exp , 0 ) ; rtx addr_helper = gen_reg_rtx ( insn_data [ icode ] . operand [ 1 ] . mode ) ; target = nds32_legitimize_target ( icode , target ) ; op0 = nds32_legitimize_argument ( icode , 1 , op0 ) ; pat = GEN_FCN ( icode ) ( target , op0 , addr_helper ) ; if ( ! pat ) return NULL_RTX ; emit_move_insn ( addr_helper , GEN_INT ( 0 ) ) ; emit_insn ( pat ) ; return target ; } </s>


"Warning: Illegal instruction detected: "

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


Worker function for ` HARD_REGNO_RENAME_OK ' . Return nonzero if register OLD_REG can be renamed to register NEW_REG .


<s>
bool
Z80oldInstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
,
UnCondBrIter
=
I
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
{
continue
;
}
if
(
!
isUnpredicatedTerminator
(
*
I
)
)
{
break
;
}
if
(
!
I
->
isBranch
(
)
)
{
return
true
;
}
if
(
!
I
->
getOperand
(
0
)
.
isMBB
(
)
)
{
return
true
;
}
if
(
I
->
getNumOperands
(
)
==
1
)
{
UnCondBrIter
=
I
;
if
(
!
AllowModify
)
{
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
continue
;
}
while
(
std
::
next
(
I
)
!=
MBB
.
end
(
)
)
{
std
::
next
(
I
)
->
eraseFromParent
(
)
;
}
Cond
.
clear
(
)
;
FBB
=
nullptr
;
if
(
MBB
.
isLayoutSuccessor
(
I
->
getOperand
(
0
)
.
getMBB
(
)
)
)
{
TBB
=
nullptr
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
UnCondBrIter
=
I
;
continue
;
}
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
continue
;
}
assert
(
I
->
getNumExplicitOperands
(
)
==
2
&&
"Invalid conditional branch"
)
;
Z80old
::
CondCode
BranchCode
=
Z80old
::
CondCode
(
I
->
getOperand
(
1
)
.
getImm
(
)
)
;
if
(
Cond
.
empty
(
)
)
{
MachineBasicBlock
*
TargetBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
if
(
AllowModify
&&
UnCondBrIter
!=
MBB
.
end
(
)
&&
MBB
.
isLayoutSuccessor
(
TargetBB
)
)
{
BranchCode
=
GetOppositeBranchCondition
(
BranchCode
)
;
MachineBasicBlock
::
iterator
OldInst
=
I
;
BuildMI
(
MBB
,
UnCondBrIter
,
MBB
.
findDebugLoc
(
I
)
,
get
(
Z80old
::
JQCC
)
)
.
addMBB
(
UnCondBrIter
->
getOperand
(
0
)
.
getMBB
(
)
)
.
addImm
(
BranchCode
)
;
BuildMI
(
MBB
,
UnCondBrIter
,
MBB
.
findDebugLoc
(
I
)
,
get
(
Z80old
::
JQ
)
)
.
addMBB
(
TargetBB
)
;
OldInst
->
eraseFromParent
(
)
;
UnCondBrIter
->
eraseFromParent
(
)
;
UnCondBrIter
=
MBB
.
end
(
)
;
I
=
MBB
.
end
(
)
;
continue
;
}
FBB
=
TBB
;
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
BranchCode
)
)
;
continue
;
}
return
true
;
}
return
false
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> void emit_hard_vlmax_vsetvl ( machine_mode vmode , rtx vl ) { unsigned int sew = get_sew ( vmode ) ; emit_insn ( gen_vsetvl ( Pmode , vl , RVV_VLMAX , gen_int_mode ( sew , Pmode ) , gen_int_mode ( get_vlmul ( vmode ) , Pmode ) , const0_rtx , const0_rtx ) ) ; } </s>

Emit a vlmax vsetvl instruction . This should only be used when optimization is disabled or after vsetvl insertion pass .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"PTX FP Rounding Mode Pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> const NyuziRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
void
MipsRegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
MachineInstr
&
MI
=
*
II
;
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
DEBUG
(
errs
(
)
<<
"\nFunction : "
<<
MF
.
getName
(
)
<<
"\n"
;
errs
(
)
<<
"<--------->\n"
<<
MI
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
uint64_t
stackSize
=
MF
.
getFrameInfo
(
)
.
getStackSize
(
)
;
int64_t
spOffset
=
MF
.
getFrameInfo
(
)
.
getObjectOffset
(
FrameIndex
)
;
DEBUG
(
errs
(
)
<<
"FrameIndex : "
<<
FrameIndex
<<
"\n"
<<
"spOffset   : "
<<
spOffset
<<
"\n"
<<
"stackSize  : "
<<
stackSize
<<
"\n"
<<
"alignment  : "
<<
MF
.
getFrameInfo
(
)
.
getObjectAlignment
(
FrameIndex
)
<<
"\n"
)
;
eliminateFI
(
MI
,
FIOperandNum
,
FrameIndex
,
stackSize
,
spOffset
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .

Mips
Mips
"\nFunction : "
"\n"
"<--------->\n"
"FrameIndex : "
"\n"
"spOffset   : "
"\n"
"stackSize  : "
"\n"
"alignment  : "
"\n"


<s> static void alpha_align_insns ( unsigned int max_align , rtx ( * next_group ) ( rtx , int * , int * ) , rtx ( * next_nop ) ( int * ) ) { unsigned int align ; int ofs ; int prev_in_use , in_use , len , ldgp ; rtx i , next ; shorten_branches ( get_insns ( ) ) ; if ( align_functions < 4 ) align = 4 ; else if ( ( unsigned int ) align_functions < max_align ) align = align_functions ; else align = max_align ; ofs = prev_in_use = 0 ; i = get_insns ( ) ; if ( GET_CODE ( i ) == NOTE ) i = next_nonnote_insn ( i ) ; ldgp = alpha_function_needs_gp ? 8 : 0 ; while ( i ) { next = ( * next_group ) ( i , & in_use , & len ) ; if ( GET_CODE ( i ) == CODE_LABEL ) { unsigned int new_align = 1 << label_to_alignment ( i ) ; if ( new_align >= align ) { align = new_align < max_align ? new_align : max_align ; ofs = 0 ; } else if ( ofs & ( new_align - 1 ) ) ofs = ( ofs | ( new_align - 1 ) ) + 1 ; gcc_assert ( ! len ) ; } else if ( in_use == 0 ) { if ( len < 0 ) { ofs = 0 ; align = 4 ; len = 0 ; } } else if ( ( int ) align < len ) { unsigned int new_log_align = len > 8 ? 4 : 3 ; rtx prev , where ; where = prev = prev_nonnote_insn ( i ) ; if ( ! where || GET_CODE ( where ) != CODE_LABEL ) where = i ; if ( ! ( TARGET_EXPLICIT_RELOCS && prev && GET_CODE ( prev ) == CALL_INSN ) ) { emit_insn_before ( gen_realign ( GEN_INT ( new_log_align ) ) , where ) ; align = 1 << new_log_align ; ofs = 0 ; } } else if ( ldgp > 0 ) ldgp -= len ; else if ( ofs + len > ( int ) align ) { int nop_count = ( align - ofs ) / 4 ; rtx where ; where = prev_nonnote_insn ( i ) ; if ( where ) { if ( GET_CODE ( where ) == CODE_LABEL ) { rtx where2 = prev_nonnote_insn ( where ) ; if ( where2 && GET_CODE ( where2 ) == JUMP_INSN ) where = where2 ; } else if ( GET_CODE ( where ) == INSN ) where = i ; } else where = i ; do emit_insn_before ( ( * next_nop ) ( & prev_in_use ) , where ) ; while ( -- nop_count ) ; ofs = 0 ; } ofs = ( ofs + len ) & ( align - 1 ) ; prev_in_use = in_use ; i = next ; } } </s>

The instruction group alignment main loop .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Sparc Double-FP Move Fixer"
;
}
</s>


<s> bool mips_can_use_return_insn ( void ) { if ( cfun -> machine -> interrupt_handler_p ) return false ; if ( ! reload_completed ) return false ; if ( crtl -> profile ) return false ; if ( mips16_cfun_returns_in_fpr_p ( ) ) return false ; return cfun -> machine -> frame . total_size == 0 ; } </s>

Return nonzero if this function is known to have a null epilogue . This allows the optimizer to omit jumps to jumps if no stack was created .


<s> int aarch64_simd_attr_length_move ( rtx_insn * insn ) { machine_mode mode ; extract_insn_cached ( insn ) ; if ( REG_P ( recog_data . operand [ 0 ] ) && REG_P ( recog_data . operand [ 1 ] ) ) { mode = GET_MODE ( recog_data . operand [ 0 ] ) ; switch ( mode ) { case OImode : return 8 ; case CImode : return 12 ; case XImode : return 16 ; default : gcc_unreachable ( ) ; } } return 4 ; } </s>

Compute and return the length of aarch64_simd_mov < mode > , where < mode > is one of VSTRUCT modes : OI , CI or XI .


<s>
char
*
output_e500_flip_gt_bit
(
rtx
dst
,
rtx
src
)
{
static
char
string
[
64
]
;
int
a
,
b
;
gcc_assert
(
GET_CODE
(
dst
)
==
REG
&&
CR_REGNO_P
(
REGNO
(
dst
)
)
&&
GET_CODE
(
src
)
==
REG
&&
CR_REGNO_P
(
REGNO
(
src
)
)
)
;
a
=
4
*
(
REGNO
(
dst
)
CR0_REGNO
)
+
1
;
b
=
4
*
(
REGNO
(
src
)
CR0_REGNO
)
+
1
;
sprintf
(
string
,
"crnot %d,%d"
,
a
,
b
)
;
return
string
;
}
</s>

Return the string to flip the GT bit on a CR .


<s> static std :: unique_ptr < AAPOperand > CreateReg ( unsigned RegNo , SMLoc S , SMLoc E ) { auto Op = make_unique < AAPOperand > ( Register ) ; Op -> Reg . RegNum = RegNo ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> virtual MVT getShiftAmountTy ( EVT LHSTy ) const { return MVT :: i8 ; } </s>

Returns the type for the shift amount of a shift opcode .


<s>
bool
SIAnnotateControlFlow
::
runOnFunction
(
Function
&
F
)
{
DT
=
&
getAnalysis
<
DominatorTreeWrapperPass
>
(
)
.
getDomTree
(
)
;
LI
=
&
getAnalysis
<
LoopInfoWrapperPass
>
(
)
.
getLoopInfo
(
)
;
DA
=
&
getAnalysis
<
LegacyDivergenceAnalysis
>
(
)
;
for
(
df_iterator
<
BasicBlock
*
>
I
=
df_begin
(
&
F
.
getEntryBlock
(
)
)
,
E
=
df_end
(
&
F
.
getEntryBlock
(
)
)
;
I
!=
E
;
++
I
)
{
BasicBlock
*
BB
=
*
I
;
BranchInst
*
Term
=
dyn_cast
<
BranchInst
>
(
BB
->
getTerminator
(
)
)
;
if
(
!
Term
||
Term
->
isUnconditional
(
)
)
{
if
(
isTopOfStack
(
BB
)
)
closeControlFlow
(
BB
)
;
continue
;
}
if
(
I
.
nodeVisited
(
Term
->
getSuccessor
(
1
)
)
)
{
if
(
isTopOfStack
(
BB
)
)
closeControlFlow
(
BB
)
;
handleLoop
(
Term
)
;
continue
;
}
if
(
isTopOfStack
(
BB
)
)
{
PHINode
*
Phi
=
dyn_cast
<
PHINode
>
(
Term
->
getCondition
(
)
)
;
if
(
Phi
&&
Phi
->
getParent
(
)
==
BB
&&
isElse
(
Phi
)
)
{
insertElse
(
Term
)
;
eraseIfUnused
(
Phi
)
;
continue
;
}
closeControlFlow
(
BB
)
;
}
openIf
(
Term
)
;
}
if
(
!
Stack
.
empty
(
)
)
{
report_fatal_error
(
"failed to annotate CFG"
)
;
}
return
true
;
}
</s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s>
StringRef
getPassName
(
)
const
override
{
return
"SI Fix SGPR copies"
;
}
</s>


<s> bool aarch64_offset_7bit_signed_scaled_p ( machine_mode mode , poly_int64 offset ) { HOST_WIDE_INT multiple ; return ( constant_multiple_p ( offset , GET_MODE_SIZE ( mode ) , & multiple ) && IN_RANGE ( multiple , - 64 , 63 ) ) ; } </s>

Return true if OFFSET is a signed 7-bit value multiplied by the size of MODE .


<s> bool isMem ( ) const override { return Kind == k_Memory ; } </s>