<s>
void
SystemZInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MBBI
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
SystemZ
::
GR128BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
copyPhysReg
(
MBB
,
MBBI
,
DL
,
RI
.
getSubReg
(
DestReg
,
SystemZ
::
subreg_h64
)
,
RI
.
getSubReg
(
SrcReg
,
SystemZ
::
subreg_h64
)
,
KillSrc
)
;
copyPhysReg
(
MBB
,
MBBI
,
DL
,
RI
.
getSubReg
(
DestReg
,
SystemZ
::
subreg_l64
)
,
RI
.
getSubReg
(
SrcReg
,
SystemZ
::
subreg_l64
)
,
KillSrc
)
;
return
;
}
if
(
SystemZ
::
GRX32BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
emitGRX32Move
(
MBB
,
MBBI
,
DL
,
DestReg
,
SrcReg
,
SystemZ
::
LR
,
32
,
KillSrc
,
false
)
;
return
;
}
unsigned
Opcode
;
if
(
SystemZ
::
GR64BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LGR
;
else
if
(
SystemZ
::
FP32BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
STI
.
hasVector
(
)
SystemZ
::
LDR32
:
SystemZ
::
LER
;
else
if
(
SystemZ
::
FP64BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LDR
;
else
if
(
SystemZ
::
FP128BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LXR
;
else
if
(
SystemZ
::
VR32BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
VLR32
;
else
if
(
SystemZ
::
VR64BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
VLR64
;
else
if
(
SystemZ
::
VR128BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
VLR
;
else
if
(
SystemZ
::
AR32BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
CPYA
;
else
if
(
SystemZ
::
AR32BitRegClass
.
contains
(
DestReg
)
&&
SystemZ
::
GR32BitRegClass
.
contains
(
SrcReg
)
)
Opcode
=
SystemZ
::
SAR
;
else
if
(
SystemZ
::
GR32BitRegClass
.
contains
(
DestReg
)
&&
SystemZ
::
AR32BitRegClass
.
contains
(
SrcReg
)
)
Opcode
=
SystemZ
::
EAR
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
Opcode
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s>
SDValue
X86TargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
bool
Is64Bit
=
Subtarget
->
is64Bit
(
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_X86
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
CopyVT
=
VA
.
getValVT
(
)
;
if
(
(
CopyVT
==
MVT
::
f32
||
CopyVT
==
MVT
::
f64
)
&&
(
(
Is64Bit
||
Ins
[
i
]
.
Flags
.
isInReg
(
)
)
&&
!
Subtarget
->
hasSSE1
(
)
)
)
{
report_fatal_error
(
"SSE register return with SSE disabled"
)
;
}
if
(
(
VA
.
getLocReg
(
)
==
X86
::
ST0
||
VA
.
getLocReg
(
)
==
X86
::
ST1
)
&&
isScalarFPTypeInSSEReg
(
VA
.
getValVT
(
)
)
)
{
CopyVT
=
MVT
::
f80
;
}
SDValue
Val
;
if
(
Is64Bit
&&
CopyVT
.
isVector
(
)
&&
CopyVT
.
getSizeInBits
(
)
==
64
)
{
if
(
VA
.
getLocReg
(
)
==
X86
::
XMM0
||
VA
.
getLocReg
(
)
==
X86
::
XMM1
)
{
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
MVT
::
v2i64
,
InFlag
)
.
getValue
(
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
Val
=
DAG
.
getNode
(
ISD
::
EXTRACT_VECTOR_ELT
,
dl
,
MVT
::
i64
,
Val
,
DAG
.
getConstant
(
0
,
MVT
::
i64
)
)
;
}
else
{
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
MVT
::
i64
,
InFlag
)
.
getValue
(
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
}
Val
=
DAG
.
getNode
(
ISD
::
BIT_CONVERT
,
dl
,
CopyVT
,
Val
)
;
}
else
{
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
CopyVT
,
InFlag
)
.
getValue
(
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
}
InFlag
=
Chain
.
getValue
(
2
)
;
if
(
CopyVT
!=
VA
.
getValVT
(
)
)
{
Val
=
DAG
.
getNode
(
ISD
::
FP_ROUND
,
dl
,
VA
.
getValVT
(
)
,
Val
,
DAG
.
getIntPtrConstant
(
1
)
)
;
}
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> bool nds32_gw_last_load_to_ex_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx last_def_reg = extract_nth_access_reg ( producer , - 1 ) ; return gw_consumed_by_ex_dep_p ( consumer , last_def_reg ) ; } </s>

Check dependencies from LMW ( N , N ) to EX .


"ShadowCallStack attribute not supported on Darwin."

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool PULPFixupHwLoops :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) { return false ; } bool fixedPreHd = fixupLoopPreheader ( MF ) ; bool fixedLatch = fixupLoopLatch ( MF ) ; bool fixedInstr = fixupLoopInstrs ( MF ) ; for ( MachineBasicBlock & MBB : MF ) { unsigned instrs = 0 ; for ( MachineInstr & MI : MBB ) { instrs ++ ; if ( isHardwareLoop ( MI ) && instrs > 1 ) { MachineBasicBlock * New = splitMBBAt ( & MBB , MI ) ; if ( New == & MBB ) { continue ; } New -> setAlignment ( Align ( 4 ) ) ; break ; } } } return fixedPreHd || fixedLatch || fixedInstr ; } </s>

runOnMachineFunction - Emit the function body .


<s> static void aarch64_parse_tune_string ( const char * tune_string , struct tune_params * tune ) { tune -> extra_tuning_flags = aarch64_parse_boolean_options ( tune_string , aarch64_tuning_flags , tune -> extra_tuning_flags , "tune=" ) ; } </s>

Support for overriding other tuning flags .


<s> static bool cbranch_predicted_p ( rtx_insn * insn ) { rtx x = find_reg_note ( insn , REG_BR_PROB , 0 ) ; if ( x ) { int pred_val = XINT ( x , 0 ) ; return pred_val >= REG_BR_PROB_BASE / 2 ; } return false ; } </s>

Return true if INSN is annotated with a REG_BR_PROB note that indicates it 's a branch that 's predicted taken .


getPassName - Return a nice clean name for a pass .


<s> void MSP430RegisterInfo :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MSP430MachineFunctionInfo * MSP430FI = MF . getInfo < MSP430MachineFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc DL = ( MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc :: getUnknownLoc ( ) ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; uint64_t NumBytes = 0 ; if ( hasFP ( MF ) ) { uint64_t FrameSize = StackSize - 2 ; NumBytes = FrameSize - MSP430FI -> getCalleeSavedFrameSize ( ) ; MFI -> setOffsetAdjustment ( - NumBytes ) ; BuildMI ( MBB , MBBI , DL , TII . get ( MSP430 :: PUSH16r ) ) . addReg ( MSP430 :: FPW , RegState :: Kill ) ; BuildMI ( MBB , MBBI , DL , TII . get ( MSP430 :: MOV16rr ) , MSP430 :: FPW ) . addReg ( MSP430 :: SPW ) ; for ( MachineFunction :: iterator I = next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( MSP430 :: FPW ) ; } else NumBytes = StackSize - MSP430FI -> getCalleeSavedFrameSize ( ) ; while ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == MSP430 :: PUSH16r ) ) ++ MBBI ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes ) { if ( NumBytes ) { MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( MSP430 :: SUB16ri ) , MSP430 :: SPW ) . addReg ( MSP430 :: SPW ) . addImm ( NumBytes ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; } } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Local Dynamic TLS Access Clean-up"
;
}
</s>


<s> static void emit_unlikely_jump ( rtx insn ) { int very_unlikely = REG_BR_PROB_BASE / 100 - 1 ; rtx_insn * jump = emit_jump_insn ( insn ) ; add_int_reg_note ( jump , REG_BR_PROB , very_unlikely ) ; } </s>

Mark the previous jump instruction as unlikely .


<s> bool shouldNormalizeToSelectSequence ( LLVMContext & , EVT ) const override { return false ; } </s>

Returns true if we should normalize select ( N0 & N1 , X , Y ) = > select ( N0 , select ( N1 , X , Y ) , Y ) and select ( N0|N1 , X , Y ) = > select ( N0 , select ( N1 , X , Y , Y ) ) if it is likely that it saves us from materializing N0 and N1 in an integer register .


<s> bool isUnspillableTerminatorImpl ( const MachineInstr * MI ) const override { return MI -> getOpcode ( ) == ARM :: t2LoopEndDec || MI -> getOpcode ( ) == ARM :: t2DoLoopStartTP || MI -> getOpcode ( ) == ARM :: t2WhileLoopStartLR ; } </s>

Return true if the given terminator MI is not expected to spill .


<s> bool PPCDarwinAsmPrinter :: doFinalization ( Module & M ) { bool isPPC64 = getDataLayout ( ) . getPointerSizeInBits ( ) == 64 ; const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetFnStubList ( ) ; if ( ! Stubs . empty ( ) ) EmitFunctionStubs ( Stubs ) ; if ( MAI -> doesSupportExceptionHandling ( ) && MMI ) { for ( const Function * Personality : MMI -> getPersonalities ( ) ) { if ( Personality ) { MCSymbol * NLPSym = getSymbolWithGlobalValueBase ( Personality , "$non_lazy_ptr" ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMIMacho . getGVStubEntry ( NLPSym ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( Personality ) , true ) ; } } } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer -> EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer -> EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer -> EmitIntValue ( 0 , isPPC64 ? 8 : 4 ) ; else OutStreamer -> EmitValue ( MCSymbolRefExpr :: create ( MCSym . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 ) ; } Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s>
bool
CJGInstrInfo
::
reverseBranchCondition
(
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
assert
(
Cond
.
size
(
)
==
1
&&
"Invalid Xbranch condition!"
)
;
CJGCC
::
CondCodes
CC
=
static_cast
<
CJGCC
::
CondCodes
>
(
Cond
[
0
]
.
getImm
(
)
)
;
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Invalid branch condition!"
)
;
case
CJGCC
::
COND_C
:
CC
=
CJGCC
::
COND_NC
;
break
;
case
CJGCC
::
COND_N
:
CC
=
CJGCC
::
COND_NN
;
break
;
case
CJGCC
::
COND_V
:
CC
=
CJGCC
::
COND_NV
;
break
;
case
CJGCC
::
COND_Z
:
CC
=
CJGCC
::
COND_NZ
;
break
;
case
CJGCC
::
COND_GE
:
CC
=
CJGCC
::
COND_L
;
break
;
case
CJGCC
::
COND_NC
:
CC
=
CJGCC
::
COND_C
;
break
;
case
CJGCC
::
COND_NN
:
CC
=
CJGCC
::
COND_N
;
break
;
case
CJGCC
::
COND_NV
:
CC
=
CJGCC
::
COND_V
;
break
;
case
CJGCC
::
COND_NZ
:
CC
=
CJGCC
::
COND_Z
;
break
;
case
CJGCC
::
COND_L
:
CC
=
CJGCC
::
COND_GE
;
break
;
}
Cond
[
0
]
.
setImm
(
CC
)
;
return
false
;
}
</s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> static bool rx_hard_regno_mode_ok ( unsigned int regno , machine_mode ) { return REGNO_REG_CLASS ( regno ) == GR_REGS ; } </s>


<s> bool TOYRegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


"type %qT with %<[[no_unique_address]]%> members "

"type %qT when C++17 is enabled changed to match "

Return TRUE if an argument , whose type is described by TYPE and MODE , shall be passed or returned in simd/fp register ( s ) ( providing these parameter passing registers are available ) . Upon successful return , * COUNT returns the number of needed registers , * BASE_MODE returns the mode of the individual register and when IS_HAF is not NULL , * IS_HA indicates whether or not the argument is a homogeneous floating-point aggregate or a homogeneous short-vector aggregate .


"iwmmxt requires an AAPCS compatible ABI for proper operation"

"iwmmxt abi requires an iwmmxt capable cpu"

"target CPU does not support interworking"

"AAPCS does not support %<-mcaller-super-interworking%>"

"AAPCS does not support %<-mcallee-super-interworking%>"

"target CPU does not support ARMv8-M Security Extensions"

"ARMv8-M Security Extensions incompatible with selected FPU"

"%<-mfloat-abi=hard%>: selected processor lacks an FPU"

Perform some validation between the desired architecture and the rest of the options .


"  Skipping pass: no machine model present.\n"


<s> unsigned ARMTargetLowering :: getMaxSupportedInterleaveFactor ( ) const { if ( Subtarget -> hasNEON ( ) ) return 4 ; return TargetLoweringBase :: getMaxSupportedInterleaveFactor ( ) ; } </s>

Get the maximum supported factor for interleaved memory accesses .


<s> bool X86Subtarget :: isLegalToCallImmediateAddr ( ) const { if ( In64BitMode || isTargetWin32 ( ) ) return false ; return isTargetELF ( ) || TM . getRelocationModel ( ) == Reloc :: Static ; } </s>

Return true if the subtarget allows calls to immediate address .


<s> rtx mn10300_builtin_saveregs ( ) { rtx offset , mem ; tree fntype = TREE_TYPE ( current_function_decl ) ; int argadj = ( ( ! ( TYPE_ARG_TYPES ( fntype ) != 0 && ( TREE_VALUE ( tree_last ( TYPE_ARG_TYPES ( fntype ) ) ) != void_type_node ) ) ) ? UNITS_PER_WORD : 0 ) ; int set = get_varargs_alias_set ( ) ; if ( argadj ) offset = plus_constant ( current_function_arg_offset_rtx , argadj ) ; else offset = current_function_arg_offset_rtx ; mem = gen_rtx_MEM ( SImode , current_function_internal_arg_pointer ) ; set_mem_alias_set ( mem , set ) ; emit_move_insn ( mem , gen_rtx_REG ( SImode , 0 ) ) ; mem = gen_rtx_MEM ( SImode , plus_constant ( current_function_internal_arg_pointer , 4 ) ) ; set_mem_alias_set ( mem , set ) ; emit_move_insn ( mem , gen_rtx_REG ( SImode , 1 ) ) ; return copy_to_reg ( expand_binop ( Pmode , add_optab , current_function_internal_arg_pointer , offset , 0 , 0 , OPTAB_LIB_WIDEN ) ) ; } </s>

Flush the argument registers to the stack for a stdarg function ; return the new argument pointer .


<s> static tree gcn_reduction_update ( location_t loc , gimple_stmt_iterator * gsi , tree ptr , tree var , tree_code op ) { tree type = TREE_TYPE ( var ) ; tree size = TYPE_SIZE ( type ) ; if ( size == TYPE_SIZE ( unsigned_type_node ) || size == TYPE_SIZE ( long_long_unsigned_type_node ) ) return gcn_lockless_update ( loc , gsi , ptr , var , op ) ; else return gcn_lockfull_update ( loc , gsi , ptr , var , op ) ; } </s>

Emit a sequence to update a reduction accumulator at * PTR with the value held in VAR using operator OP . Return the updated value . TODO : optimize for atomic ops and independent complex ops .


<s> bool PPCLoopPreIncPrep :: runOnFunction ( Function & F ) { LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; bool MadeChange = false ; for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L = df_begin ( * I ) , LE = df_end ( * I ) ; L != LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ; return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool hasBranchDivergence ( ) { return true ; } </s>

Return true if branch divergence exists .


<s>
static
void
process_epilogue
(
)
{
if
(
block_num
!=
n_basic_blocks
1
)
{
fprintf
(
asm_out_file
,
"\t.label_state 1\n"
)
;
need_copy_state
=
1
;
}
fprintf
(
asm_out_file
,
"\t.restore sp\n"
)
;
}
</s>

The function emits unwind directives for the start of an epilogue .


<s>
StringRef
getPassName
(
)
const
override
{
return
"WebAssembly Register Stackify"
;
}
</s>

getPassName - Return a nice clean name for a pass .

WebAssembly
"WebAssembly Register Stackify"


<s> bool X86InstrInfo :: findCommutedOpIndices ( MachineInstr & MI , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { switch ( MI . getOpcode ( ) ) { case X86 :: CMPPDrri : case X86 :: CMPPSrri : case X86 :: VCMPPDrri : case X86 :: VCMPPSrri : case X86 :: VCMPPDYrri : case X86 :: VCMPPSYrri : { unsigned Imm = MI . getOperand ( 3 ) . getImm ( ) & 0x7 ; switch ( Imm ) { case 0x00 : case 0x03 : case 0x04 : case 0x07 : return fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , 1 , 2 ) ; } return false ; } default : if ( isFMA3 ( MI . getOpcode ( ) ) ) return findFMA3CommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; } return false ; } </s>

Returns true iff the routine could find two commutable operands in the given machine instruction .


<s> std :: pair < unsigned , const TargetRegisterClass * > PPCTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'b' : case 'r' : if ( VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RCRegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRCRegClass ) ; case 'f' : if ( VT == MVT :: f32 || VT == MVT :: i32 ) return std :: make_pair ( 0U , & PPC :: F4RCRegClass ) ; if ( VT == MVT :: f64 || VT == MVT :: i64 ) return std :: make_pair ( 0U , & PPC :: F8RCRegClass ) ; break ; case 'v' : return std :: make_pair ( 0U , & PPC :: VRRCRegClass ) ; case 'y' : return std :: make_pair ( 0U , & PPC :: CRRCRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> int fmpyaddoperands ( rtx * operands ) { enum machine_mode mode = GET_MODE ( operands [ 0 ] ) ; if ( mode != SFmode && mode != DFmode ) return 0 ; if ( ! ( mode == GET_MODE ( operands [ 1 ] ) && mode == GET_MODE ( operands [ 2 ] ) && mode == GET_MODE ( operands [ 3 ] ) && mode == GET_MODE ( operands [ 4 ] ) && mode == GET_MODE ( operands [ 5 ] ) ) ) return 0 ; if ( ! ( GET_CODE ( operands [ 1 ] ) == REG && GET_CODE ( operands [ 2 ] ) == REG && GET_CODE ( operands [ 3 ] ) == REG && GET_CODE ( operands [ 4 ] ) == REG && GET_CODE ( operands [ 5 ] ) == REG ) ) return 0 ; if ( ! rtx_equal_p ( operands [ 3 ] , operands [ 4 ] ) && ! rtx_equal_p ( operands [ 3 ] , operands [ 5 ] ) ) return 0 ; if ( rtx_equal_p ( operands [ 3 ] , operands [ 0 ] ) || rtx_equal_p ( operands [ 3 ] , operands [ 1 ] ) || rtx_equal_p ( operands [ 3 ] , operands [ 2 ] ) ) return 0 ; if ( rtx_equal_p ( operands [ 4 ] , operands [ 0 ] ) || rtx_equal_p ( operands [ 5 ] , operands [ 0 ] ) ) return 0 ; if ( mode == SFmode && ( REGNO_REG_CLASS ( REGNO ( operands [ 0 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 1 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 2 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 3 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 4 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 5 ] ) ) != FPUPPER_REGS ) ) return 0 ; return 1 ; } </s>

Returns 1 if the 6 operands specified in OPERANDS are suitable for use in fmpyadd instructions .


"X86 Load Value Injection (LVI) Load Hardening"


<s> bool ARMBaseTargetMachine :: addPreRegAlloc ( PassManagerBase & PM ) { if ( getOptLevel ( ) != CodeGenOpt :: None && ! Subtarget . isThumb1Only ( ) ) PM . add ( createARMLoadStoreOptimizationPass ( true ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None && Subtarget . isCortexA9 ( ) ) PM . add ( createMLxExpansionPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { AArch64FI = MF . getInfo < AArch64FunctionInfo > ( ) ; STI = static_cast < const AArch64Subtarget * > ( & MF . getSubtarget ( ) ) ; SetupMachineFunction ( MF ) ; if ( STI -> isTargetCOFF ( ) ) { bool Internal = MF . getFunction ( ) . hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer -> EmitCOFFSymbolType ( Type ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; emitXRayTable ( ) ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> void NyuziTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; } </s>

This method must be called before any actual lowering is done .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addPreserved < MachineBlockFrequencyInfo > ( ) ; AU . addPreservedID ( MachineDominatorsID ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> int X86FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { if ( TRI -> hasBasePointer ( MF ) ) FrameReg = TRI -> getBaseRegister ( ) ; else if ( TRI -> needsStackRealignment ( MF ) ) FrameReg = TRI -> getStackRegister ( ) ; else FrameReg = TRI -> getFrameRegister ( MF ) ; return getFrameIndexOffset ( MF , FI ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> static int ia64_spec_check_src_p ( rtx src ) { if ( GET_CODE ( src ) == IF_THEN_ELSE ) { rtx t ; t = XEXP ( src , 0 ) ; if ( GET_CODE ( t ) == NE ) { t = XEXP ( t , 0 ) ; if ( GET_CODE ( t ) == UNSPEC ) { int code ; code = XINT ( t , 1 ) ; if ( code == UNSPEC_LDCCLR || code == UNSPEC_LDCNC || code == UNSPEC_CHKACLR || code == UNSPEC_CHKANC || code == UNSPEC_CHKS ) { gcc_assert ( code != 0 ) ; return code ; } } } } return 0 ; } </s>

Return nonzero , if SRC belongs to recovery check .


<s> static int pdp11_addr_cost ( rtx addr , machine_mode mode , addr_space_t as ATTRIBUTE_UNUSED , bool speed ) { int cost = 0 ; if ( GET_CODE ( addr ) != REG ) { if ( ! simple_memory_operand ( addr , mode ) ) cost = 2 ; if ( speed && ! CONSTANT_P ( addr ) ) cost += ( mode == QImode ) ? 2 : GET_MODE_SIZE ( mode ) ; } return cost ; } </s>

Return cost of accessing the supplied operand . Registers are free . Anything else starts with a cost of two . Add to that for memory references the memory accesses of the addressing mode ( if any ) plus the data reference ; for other operands just the memory access ( if any ) for the mode .


<s> BitVector SIRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AMDGPU :: INDIRECT_BASE_ADDR ) ; reserveRegisterTuples ( Reserved , AMDGPU :: EXEC ) ; reserveRegisterTuples ( Reserved , AMDGPU :: FLAT_SCR ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TBA ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TMA ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP0_TTMP1 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP2_TTMP3 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP4_TTMP5 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP6_TTMP7 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP8_TTMP9 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP10_TTMP11 ) ; unsigned MaxNumSGPRs = getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = AMDGPU :: SGPR_32RegClass . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = AMDGPU :: SGPR_32RegClass . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } unsigned MaxNumVGPRs = getMaxNumVGPRs ( MF ) ; unsigned TotalNumVGPRs = AMDGPU :: VGPR_32RegClass . getNumRegs ( ) ; for ( unsigned i = MaxNumVGPRs ; i < TotalNumVGPRs ; ++ i ) { unsigned Reg = AMDGPU :: VGPR_32RegClass . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } const SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , ScratchWaveOffsetReg ) ; } unsigned ScratchRSrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRSrcReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , ScratchRSrcReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , ScratchWaveOffsetReg ) ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static const char * mips16_call_stub_mode_suffix ( machine_mode mode ) { if ( mode == SFmode ) return "sf" ; else if ( mode == DFmode ) return "df" ; else if ( mode == SCmode ) return "sc" ; else if ( mode == DCmode ) return "dc" ; else if ( mode == V2SFmode ) { gcc_assert ( TARGET_PAIRED_SINGLE_FLOAT ) ; return "df" ; } else gcc_unreachable ( ) ; } </s>

Return the two-character string that identifies floating-point return mode MODE in the name of a MIPS16 function stub .


<s> static HOST_WIDE_INT iq2000_starting_frame_offset ( void ) { return crtl -> outgoing_args_size ; } </s>


<s>
void
ScheduleDAGPostRA
::
releaseSucc
(
SUnit
*
SU
,
SDep
*
SuccEdge
)
{
SUnit
*
SuccSU
=
SuccEdge
->
getSUnit
(
)
;
if
(
SuccEdge
->
isWeak
(
)
)
{
SuccSU
->
WeakPredsLeft
;
return
;
}
if
(
SuccSU
->
NumPredsLeft
==
0
)
{
dbgs
(
)
<<
"*** Scheduling failed! ***\n"
;
SuccSU
->
dump
(
this
)
;
dbgs
(
)
<<
" has been released too many times!\n"
;
llvm_unreachable
(
0
)
;
}
SuccSU
->
NumPredsLeft
;
if
(
SuccSU
->
NumPredsLeft
==
0
&&
SuccSU
!=
&
ExitSU
)
SchedImpl
->
releaseTopNode
(
SuccSU
)
;
}
</s>

ReleaseSucc - Decrement the NumPredsLeft count of a successor .


<s> const X86InstrInfo * getInstrInfo ( ) { return getTargetMachine ( ) . getInstrInfo ( ) ; } </s>


<s> void AVRFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( hasFP ( MF ) ) { SavedRegs . set ( AVR :: R29 ) ; SavedRegs . set ( AVR :: R28 ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


"Store results: call to builtin function with wrong "

optimizeCall - Take the given call instruction and return a more optimal value to replace the instruction with or 0 if a more optimal form ca n't be found .


<s> const uint16_t * X86RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { bool HasAVX = TM . getSubtarget < X86Subtarget > ( ) . hasAVX ( ) ; bool HasAVX512 = TM . getSubtarget < X86Subtarget > ( ) . hasAVX512 ( ) ; switch ( MF -> getFunction ( ) -> getCallingConv ( ) ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_SaveList ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; return CSR_64_AllRegs_SaveList ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_SaveList ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_SaveList ; return CSR_64_RT_AllRegs_SaveList ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_SaveList ; break ; default : break ; } bool CallsEHReturn = MF -> getMMI ( ) . callsEHReturn ( ) ; if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_SaveList ; if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; } if ( CallsEHReturn ) return CSR_32EHRet_SaveList ; return CSR_32_SaveList ; } </s>


<s> static int ix86_simd_clone_usable ( struct cgraph_node * node ) { switch ( node -> simdclone -> vecsize_mangle ) { case 'b' : if ( ! TARGET_SSE2 ) return - 1 ; if ( ! TARGET_AVX ) return 0 ; return TARGET_AVX2 ? 2 : 1 ; case 'c' : if ( ! TARGET_AVX ) return - 1 ; return TARGET_AVX2 ? 1 : 0 ; break ; case 'd' : if ( ! TARGET_AVX2 ) return - 1 ; return 0 ; default : gcc_unreachable ( ) ; } } </s>

If SIMD clone NODE ca n't be used in a vectorized loop in current function , return -1 , otherwise return a badness of using it ( 0 if it is most desirable from vecsize_mangle point of view , 1 slightly less desirable , etc . ) .


<s> static uint64_t getSymbolOffset ( const MCSymbolRefExpr * SymRefExpr , const MCAsmLayout & Layout ) { if ( ! SymRefExpr ) { return 0 ; } const MCSymbol & Sym = SymRefExpr -> getSymbol ( ) ; return Sym . isDefined ( ) ? Layout . getSymbolOffset ( Sym ) : 0 ; } </s>

Variant that reports a fatal error if the offset is not computable .


<s>
void
X86DAGToDAGISel
::
PreprocessISelDAG
(
)
{
OptForSize
=
MF
->
getFunction
(
)
->
optForSize
(
)
;
OptForMinSize
=
MF
->
getFunction
(
)
->
optForMinSize
(
)
;
assert
(
(
!
OptForMinSize
||
OptForSize
)
&&
"OptForMinSize implies OptForSize"
)
;
for
(
SelectionDAG
::
allnodes_iterator
I
=
CurDAG
->
allnodes_begin
(
)
,
E
=
CurDAG
->
allnodes_end
(
)
;
I
!=
E
;
)
{
SDNode
*
N
=
&
*
I
++
;
if
(
OptLevel
!=
CodeGenOpt
::
&&
!
Subtarget
->
useRetpoline
(
)
&&
(
(
N
->
getOpcode
(
)
==
X86ISD
::
CALL
&&
!
Subtarget
->
callRegIndirect
(
)
)
||
(
N
->
getOpcode
(
)
==
X86ISD
::
TC_RETURN
&&
(
Subtarget
->
is64Bit
(
)
||
!
getTargetMachine
(
)
.
isPositionIndependent
(
)
)
)
)
)
{
bool
HasCallSeq
=
N
->
getOpcode
(
)
==
X86ISD
::
CALL
;
SDValue
Chain
=
N
->
getOperand
(
0
)
;
SDValue
Load
=
N
->
getOperand
(
1
)
;
if
(
!
isCalleeLoad
(
Load
,
Chain
,
HasCallSeq
)
)
continue
;
moveBelowOrigChain
(
CurDAG
,
Load
,
SDValue
(
N
,
0
)
,
Chain
)
;
++
NumLoadMoved
;
continue
;
}
if
(
N
->
getOpcode
(
)
!=
ISD
::
FP_ROUND
&&
N
->
getOpcode
(
)
!=
ISD
::
FP_EXTEND
)
continue
;
MVT
SrcVT
=
N
->
getOperand
(
0
)
.
getSimpleValueType
(
)
;
MVT
DstVT
=
N
->
getSimpleValueType
(
0
)
;
if
(
SrcVT
.
isVector
(
)
||
DstVT
.
isVector
(
)
)
continue
;
const
X86TargetLowering
*
X86Lowering
=
static_cast
<
const
X86TargetLowering
*
>
(
TLI
)
;
bool
SrcIsSSE
=
X86Lowering
->
isScalarFPTypeInSSEReg
(
SrcVT
)
;
bool
DstIsSSE
=
X86Lowering
->
isScalarFPTypeInSSEReg
(
DstVT
)
;
if
(
SrcIsSSE
&&
DstIsSSE
)
continue
;
if
(
!
SrcIsSSE
&&
!
DstIsSSE
)
{
if
(
N
->
getOpcode
(
)
==
ISD
::
FP_EXTEND
)
continue
;
if
(
N
->
getConstantOperandVal
(
1
)
)
continue
;
}
MVT
MemVT
;
if
(
N
->
getOpcode
(
)
==
ISD
::
FP_ROUND
)
MemVT
=
DstVT
;
else
MemVT
=
SrcIsSSE
SrcVT
:
DstVT
;
SDValue
MemTmp
=
CurDAG
->
CreateStackTemporary
(
MemVT
)
;
SDLoc
dl
(
N
)
;
SDValue
Store
=
CurDAG
->
getTruncStore
(
CurDAG
->
getEntryNode
(
)
,
dl
,
N
->
getOperand
(
0
)
,
MemTmp
,
MachinePointerInfo
(
)
,
MemVT
)
;
SDValue
Result
=
CurDAG
->
getExtLoad
(
ISD
::
EXTLOAD
,
dl
,
DstVT
,
Store
,
MemTmp
,
MachinePointerInfo
(
)
,
MemVT
)
;
I
;
CurDAG
->
ReplaceAllUsesOfValueWith
(
SDValue
(
N
,
0
)
,
Result
)
;
++
I
;
CurDAG
->
DeleteNode
(
N
)
;
}
}
</s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


"FP elimination on a non-leaf function is not supported"

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> static tree ix86_veclibabi_svml ( combined_fn fn , tree type_out , tree type_in ) { char name [ 20 ] ; tree fntype , new_fndecl , args ; unsigned arity ; const char * bname ; machine_mode el_mode , in_mode ; int n , in_n ; if ( ! flag_unsafe_math_optimizations ) return NULL_TREE ; el_mode = TYPE_MODE ( TREE_TYPE ( type_out ) ) ; n = TYPE_VECTOR_SUBPARTS ( type_out ) ; in_mode = TYPE_MODE ( TREE_TYPE ( type_in ) ) ; in_n = TYPE_VECTOR_SUBPARTS ( type_in ) ; if ( el_mode != in_mode || n != in_n ) return NULL_TREE ; switch ( fn ) { CASE_CFN_EXP : CASE_CFN_LOG : CASE_CFN_LOG10 : CASE_CFN_POW : CASE_CFN_TANH : CASE_CFN_TAN : CASE_CFN_ATAN : CASE_CFN_ATAN2 : CASE_CFN_ATANH : CASE_CFN_CBRT : CASE_CFN_SINH : CASE_CFN_SIN : CASE_CFN_ASINH : CASE_CFN_ASIN : CASE_CFN_COSH : CASE_CFN_COS : CASE_CFN_ACOSH : CASE_CFN_ACOS : if ( ( el_mode != DFmode || n != 2 ) && ( el_mode != SFmode || n != 4 ) ) return NULL_TREE ; break ; default : return NULL_TREE ; } tree fndecl = mathfn_built_in ( TREE_TYPE ( type_in ) , fn ) ; bname = IDENTIFIER_POINTER ( DECL_NAME ( fndecl ) ) ; if ( DECL_FUNCTION_CODE ( fndecl ) == BUILT_IN_LOGF ) strcpy ( name , "vmlsLn4" ) ; else if ( DECL_FUNCTION_CODE ( fndecl ) == BUILT_IN_LOG ) strcpy ( name , "vmldLn2" ) ; else if ( n == 4 ) { sprintf ( name , "vmls%s" , bname + 10 ) ; name [ strlen ( name ) - 1 ] = '4' ; } else sprintf ( name , "vmld%s2" , bname + 10 ) ; name [ 4 ] &= ~ 0x20 ; arity = 0 ; for ( args = DECL_ARGUMENTS ( fndecl ) ; args ; args = TREE_CHAIN ( args ) ) arity ++ ; if ( arity == 1 ) fntype = build_function_type_list ( type_out , type_in , NULL ) ; else fntype = build_function_type_list ( type_out , type_in , type_in , NULL ) ; new_fndecl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , fntype ) ; TREE_PUBLIC ( new_fndecl ) = 1 ; DECL_EXTERNAL ( new_fndecl ) = 1 ; DECL_IS_NOVOPS ( new_fndecl ) = 1 ; TREE_READONLY ( new_fndecl ) = 1 ; return new_fndecl ; } </s>

Handler for an SVML-style interface to a library with vectorized intrinsics .


<s>
bool
HexagonOptAddrMode
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
bool
Changed
=
false
;
auto
&
HST
=
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
;
auto
&
MRI
=
MF
.
getRegInfo
(
)
;
HII
=
HST
.
getInstrInfo
(
)
;
const
auto
&
MDF
=
getAnalysis
<
MachineDominanceFrontier
>
(
)
;
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
const
auto
&
TRI
=
*
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
const
TargetOperandInfo
TOI
(
*
HII
)
;
RegisterAliasInfo
RAI
(
TRI
)
;
DataFlowGraph
G
(
MF
,
*
HII
,
TRI
,
*
MDT
,
MDF
,
RAI
,
TOI
)
;
G
.
build
(
)
;
DFG
=
&
G
;
Liveness
L
(
MRI
,
*
DFG
)
;
L
.
computePhiInfo
(
)
;
LV
=
&
L
;
constructDefMap
(
&
DFG
->
getMF
(
)
.
front
(
)
)
;
Deleted
.
clear
(
)
;
NodeAddr
<
FuncNode
*
>
FA
=
DFG
->
getFunc
(
)
;
DEBUG
(
dbgs
(
)
<<
"==== [RefMap#]=====:\n "
<<
Print
<
NodeAddr
<
FuncNode
*
>>
(
FA
,
*
DFG
)
<<
"\n"
)
;
for
(
NodeAddr
<
BlockNode
*
>
BA
:
FA
.
Addr
->
members
(
*
DFG
)
)
Changed
|=
processBlock
(
BA
)
;
for
(
auto
MI
:
Deleted
)
MI
->
eraseFromParent
(
)
;
if
(
Changed
)
{
G
.
build
(
)
;
L
.
computeLiveIns
(
)
;
L
.
resetLiveIns
(
)
;
L
.
resetKills
(
)
;
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

Hexagon
Hexagon
Hexagon
"==== [RefMap#]=====:\n "
"\n"


<s> int symbol_mentioned_p ( rtx x ) { const char * fmt ; int i ; if ( GET_CODE ( x ) == SYMBOL_REF ) return 1 ; if ( GET_CODE ( x ) == UNSPEC ) return 0 ; fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( x , i ) - 1 ; j >= 0 ; j -- ) if ( symbol_mentioned_p ( XVECEXP ( x , i , j ) ) ) return 1 ; } else if ( fmt [ i ] == 'e' && symbol_mentioned_p ( XEXP ( x , i ) ) ) return 1 ; } return 0 ; } </s>

Return TRUE if X references a SYMBOL_REF .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Teak Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> virtual ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const { const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) return createR600MachineScheduler ( C ) ; return nullptr ; } </s>

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level .


<s>
bool
R600VectorRegMerger
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
TII
=
static_cast
<
const
R600InstrInfo
*
>
(
Fn
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
MRI
=
&
(
Fn
.
getRegInfo
(
)
)
;
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
MachineBasicBlock
*
MB
=
&
*
MBB
;
PreviousRegSeq
.
clear
(
)
;
PreviousRegSeqByReg
.
clear
(
)
;
PreviousRegSeqByUndefCount
.
clear
(
)
;
for
(
MachineBasicBlock
::
iterator
MII
=
MB
->
begin
(
)
,
MIIE
=
MB
->
end
(
)
;
MII
!=
MIIE
;
++
MII
)
{
MachineInstr
*
MI
=
MII
;
if
(
MI
->
getOpcode
(
)
!=
AMDGPU
::
REG_SEQUENCE
)
{
if
(
TII
->
get
(
MI
->
getOpcode
(
)
)
.
TSFlags
&
R600_InstFlag
::
TEX_INST
)
{
unsigned
Reg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
for
(
MachineRegisterInfo
::
def_instr_iterator
It
=
MRI
->
def_instr_begin
(
Reg
)
,
E
=
MRI
->
def_instr_end
(
)
;
It
!=
E
;
++
It
)
{
RemoveMI
(
&
(
*
It
)
)
;
}
}
continue
;
}
RegSeqInfo
RSI
(
*
MRI
,
MI
)
;
unsigned
Reg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
if
(
!
areAllUsesSwizzeable
(
Reg
)
)
continue
;
DEBUG
(
dbgs
(
)
<<
"Trying to optimize "
;
MI
->
dump
(
)
;
)
;
RegSeqInfo
CandidateRSI
;
std
::
vector
<
std
::
pair
<
unsigned
,
unsigned
>
>
RemapChan
;
DEBUG
(
dbgs
(
)
<<
"Using common slots...\n"
;
)
;
if
(
tryMergeUsingCommonSlot
(
RSI
,
CandidateRSI
,
RemapChan
)
)
{
RemoveMI
(
CandidateRSI
.
Instr
)
;
MII
=
RebuildVector
(
&
RSI
,
&
CandidateRSI
,
RemapChan
)
;
trackRSI
(
RSI
)
;
continue
;
}
DEBUG
(
dbgs
(
)
<<
"Using free slots...\n"
;
)
;
RemapChan
.
clear
(
)
;
if
(
tryMergeUsingFreeSlot
(
RSI
,
CandidateRSI
,
RemapChan
)
)
{
RemoveMI
(
CandidateRSI
.
Instr
)
;
MII
=
RebuildVector
(
&
RSI
,
&
CandidateRSI
,
RemapChan
)
;
trackRSI
(
RSI
)
;
continue
;
}
trackRSI
(
RSI
)
;
}
}
return
false
;
}
</s>

AMDGPU
R600
R600
AMDGPU::REG_SEQUENCE
R600_InstFlag::TEX_INST
1
SI
0
"Trying to optimize "
SI
"Using common slots...\n"
SI
SI
SI
SI
SI
SI
SI
"Using free slots...\n"
SI
SI
SI
SI
SI
SI
SI
SI
SI


"Can only insert epilogue into returning blocks"

"Expected to see callee-save register restore code"


"considering end of repeat loop at insn %d\n"

Figure out where to put LABEL , which is the label for a repeat loop . The loop ends just before LAST_INSN . If SHARED , insns other than the `` repeat '' might use LABEL to jump to the loop 's continuation point . Return the last instruction in the adjusted loop .


<s> void Mips16FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MipsInstrInfo & TII = * static_cast < const MipsInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; if ( isInt < 16 > ( StackSize ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: RestoreRaF16 ) ) . addImm ( StackSize ) ; } </s>

Mips Mips Mips Mips 16 Mips::RestoreRaF16


<s> static bool frv_pack_insn_p ( rtx_insn * insn ) { if ( frv_packet . num_insns == frv_packet . issue_rate ) return false ; if ( frv_packet . num_insns > 0 && NONJUMP_INSN_P ( insn ) && GET_MODE ( insn ) == TImode && GET_CODE ( PATTERN ( insn ) ) != COND_EXEC ) return false ; if ( get_attr_type ( insn ) != TYPE_SETLO ) if ( frv_registers_conflict_p ( PATTERN ( insn ) ) ) return false ; return state_transition ( frv_packet . dfa_state , insn ) < 0 ; } </s>

Return true if INSN can be added to the current packet . Update the DFA state on success .


<s> bool s390_logical_operator_ok_p ( rtx * operands ) { if ( GET_CODE ( operands [ 0 ] ) == MEM ) return rtx_equal_p ( operands [ 0 ] , operands [ 1 ] ) || ( ! reload_completed && rtx_equal_p ( operands [ 0 ] , operands [ 2 ] ) ) ; return true ; } </s>

Check whether OPERANDS are OK for a logical operation ( AND , IOR , XOR ) .


Return an array that contains the direct target flag values and their names .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addRequired < DivergenceAnalysis > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void X86TargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( ! Subtarget . isTargetGlibc ( ) ) TargetLowering :: insertSSPDeclarations ( M ) ; } </s>

Inserts necessary declarations for SSP ( stack protection ) purpose .


<s> bool SIInstrInfo :: isLegalRegOperand ( const MachineRegisterInfo & MRI , const MCOperandInfo & OpInfo , const MachineOperand & MO ) const { if ( ! MO . isReg ( ) ) return false ; unsigned Reg = MO . getReg ( ) ; const TargetRegisterClass * RC = TargetRegisterInfo :: isVirtualRegister ( Reg ) ? MRI . getRegClass ( Reg ) : RI . getPhysRegClass ( Reg ) ; return RI . getCommonSubClass ( RC , RI . getRegClass ( OpInfo . RegClass ) ) == RC ; } </s>

Check if MO ( a register operand ) is a legal register for the given operand description .


"Checking if value is in small-data, -G"

Return true if this global address should be placed into small data/bss section .


<s>
void
R600AsmPrinter
::
emitInstruction
(
const
MachineInstr
*
MI
)
{
const
R600Subtarget
&
STI
=
MF
->
getSubtarget
<
R600Subtarget
>
(
)
;
R600MCInstLower
MCInstLowering
(
OutContext
,
STI
,
*
this
)
;
StringRef
Err
;
if
(
!
STI
.
getInstrInfo
(
)
->
verifyInstruction
(
*
MI
,
Err
)
)
{
LLVMContext
&
C
=
MI
->
getParent
(
)
->
getParent
(
)
->
getFunction
(
)
.
getContext
(
)
;
C
.
emitError
(
"Illegal instruction detected: "
+
Err
)
;
MI
->
print
(
errs
(
)
)
;
}
if
(
MI
->
isBundle
(
)
)
{
const
MachineBasicBlock
*
MBB
=
MI
->
getParent
(
)
;
MachineBasicBlock
::
const_instr_iterator
I
=
++
MI
->
getIterator
(
)
;
while
(
I
!=
MBB
->
instr_end
(
)
&&
I
->
isInsideBundle
(
)
)
{
emitInstruction
(
&
*
I
)
;
++
I
;
}
}
else
{
MCInst
TmpInst
;
MCInstLowering
.
lower
(
MI
,
TmpInst
)
;
EmitToStreamer
(
*
OutStreamer
,
TmpInst
)
;
}
}
</s>

Targets should implement this to emit instructions .


"Unexpected fixup kind in fixupNeedsRelaxation()!"

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> void ARMConstantIslands :: verify ( MachineFunction & Fn ) { assert ( BBOffsets . size ( ) == BBSizes . size ( ) ) ; for ( unsigned i = 1 , e = BBOffsets . size ( ) ; i != e ; ++ i ) assert ( BBOffsets [ i - 1 ] + BBSizes [ i - 1 ] == BBOffsets [ i ] ) ; if ( isThumb ) { for ( MachineFunction :: iterator MBBI = Fn . begin ( ) , E = Fn . end ( ) ; MBBI != E ; ++ MBBI ) { MachineBasicBlock * MBB = MBBI ; if ( ! MBB -> empty ( ) && MBB -> begin ( ) -> getOpcode ( ) == ARM :: CONSTPOOL_ENTRY ) assert ( ( BBOffsets [ MBB -> getNumber ( ) ] % 4 == 0 && BBSizes [ MBB -> getNumber ( ) ] % 4 == 0 ) || ( BBOffsets [ MBB -> getNumber ( ) ] % 4 != 0 && BBSizes [ MBB -> getNumber ( ) ] % 4 != 0 ) ) ; } } } </s>


<s> static DItype local_fixunsdfdi ( DFtype a ) { USItype hi , lo ; hi = a / ( ( ( UDItype ) 1 ) << ( sizeof ( SItype ) * 8 ) ) ; lo = ( a - ( ( DFtype ) hi ) * ( ( ( UDItype ) 1 ) << ( sizeof ( SItype ) * 8 ) ) ) ; return ( ( UDItype ) hi << ( sizeof ( SItype ) * 8 ) ) | lo ; } </s>

This version is needed to prevent recursion ; fixunsdfdi in libgcc calls fixdfdi , which in turn calls calls fixunsdfdi .


<s> int bfin_hard_regno_rename_ok ( unsigned int old_reg ATTRIBUTE_UNUSED , unsigned int new_reg ) { if ( funkind ( TREE_TYPE ( current_function_decl ) ) != SUBROUTINE && ! df_regs_ever_live_p ( new_reg ) ) return 0 ; return 1 ; } </s>

Return nonzero if register OLD_REG can be renamed to register NEW_REG .


<s> MVT AMDGPUTargetLowering :: getVectorIdxTy ( ) const { return MVT :: i32 ; } </s>

Returns the type to be used for the index operand of : ISD : :INSERT_VECTOR_ELT , ISD : :EXTRACT_VECTOR_ELT , ISD : :INSERT_SUBVECTOR , and ISD : :EXTRACT_SUBVECTOR .


<s> bool SPUAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; printMemRegReg ( MI , OpNo ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> static rtx nvptx_expand_worker_addr ( tree exp , rtx target , machine_mode ARG_UNUSED ( mode ) , int ignore ) { if ( ignore ) return target ; unsigned align = TREE_INT_CST_LOW ( CALL_EXPR_ARG ( exp , 2 ) ) ; if ( align > worker_red_align ) worker_red_align = align ; unsigned offset = TREE_INT_CST_LOW ( CALL_EXPR_ARG ( exp , 0 ) ) ; unsigned size = TREE_INT_CST_LOW ( CALL_EXPR_ARG ( exp , 1 ) ) ; if ( size + offset > worker_red_size ) worker_red_size = size + offset ; rtx addr = worker_red_sym ; if ( offset ) { addr = gen_rtx_PLUS ( Pmode , addr , GEN_INT ( offset ) ) ; addr = gen_rtx_CONST ( Pmode , addr ) ; } emit_move_insn ( target , addr ) ; return target ; } </s>


<s> void applyFixup ( MCFixup const & , char * , unsigned , uint64_t , bool ) const override { return ; } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool CSKYAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == ".csky_attribute" ) return parseDirectiveAttribute ( ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s>
void
X86InstrInfo
::
replaceBranchWithTailCall
(
MachineBasicBlock
&
MBB
,
SmallVectorImpl
<
MachineOperand
>
&
BranchCond
,
const
MachineInstr
&
TailCall
)
const
{
assert
(
canMakeTailCallConditional
(
BranchCond
,
TailCall
)
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugInstr
(
)
)
continue
;
if
(
!
I
->
isBranch
(
)
)
assert
(
0
&&
"Can't find the branch to replace!"
)
;
X86
::
CondCode
CC
=
X86
::
getCondFromBranch
(
*
I
)
;
assert
(
BranchCond
.
size
(
)
==
1
)
;
if
(
CC
!=
BranchCond
[
0
]
.
getImm
(
)
)
continue
;
break
;
}
unsigned
Opc
=
TailCall
.
getOpcode
(
)
==
X86
::
TCRETURNdi
X86
::
TCRETURNdicc
:
X86
::
TCRETURNdi64cc
;
auto
MIB
=
BuildMI
(
MBB
,
I
,
MBB
.
findDebugLoc
(
I
)
,
get
(
Opc
)
)
;
MIB
->
addOperand
(
TailCall
.
getOperand
(
0
)
)
;
MIB
.
addImm
(
0
)
;
MIB
->
addOperand
(
BranchCond
[
0
]
)
;
MIB
.
copyImplicitOps
(
TailCall
)
;
LivePhysRegs
LiveRegs
(
getRegisterInfo
(
)
)
;
LiveRegs
.
addLiveOuts
(
MBB
)
;
SmallVector
<
std
::
pair
<
MCPhysReg
,
const
MachineOperand
*
>
,
8
>
Clobbers
;
LiveRegs
.
stepForward
(
*
MIB
,
Clobbers
)
;
for
(
const
auto
&
C
:
Clobbers
)
{
MIB
.
addReg
(
C
.
first
,
RegState
::
Implicit
)
;
MIB
.
addReg
(
C
.
first
,
RegState
::
Implicit
|
RegState
::
Define
)
;
}
I
->
eraseFromParent
(
)
;
}
</s>

Replace the conditional branch in MBB with a conditional tail call .


<s> const uint32_t * NyuziRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { return NyuziCSR_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool SIInsertWaits :: runOnMachineFunction ( MachineFunction & MF ) { bool Changes = false ; TII = static_cast < const SIInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = static_cast < const SIRegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; MRI = & MF . getRegInfo ( ) ; WaitedOn = ZeroCounts ; LastIssued = ZeroCounts ; LastOpcodeType = OTHER ; LastInstWritesM0 = false ; memset ( & UsedRegs , 0 , sizeof ( UsedRegs ) ) ; memset ( & DefinedRegs , 0 , sizeof ( DefinedRegs ) ) ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { if ( I -> getOpcode ( ) == AMDGPU :: S_BARRIER ) Changes |= insertWait ( MBB , I , LastIssued ) ; else Changes |= insertWait ( MBB , I , handleOperands ( * I ) ) ; pushInstruction ( MBB , I ) ; handleSendMsg ( MBB , I ) ; } Changes |= insertWait ( MBB , MBB . getFirstTerminator ( ) , LastIssued ) ; } return Changes ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool riscv_compressed_reg_p ( int regno ) { return ( TARGET_RVC && ( IN_RANGE ( regno , GP_REG_FIRST + 8 , GP_REG_FIRST + 15 ) || IN_RANGE ( regno , FP_REG_FIRST + 8 , FP_REG_FIRST + 15 ) ) ) ; } </s>

Return true if hard reg REGNO can be used in compressed instructions .


<s> static void ix86_expand_ashl_const ( rtx operand , int count , enum machine_mode mode ) { if ( count == 1 ) { emit_insn ( ( mode == DImode ? gen_addsi3 : gen_adddi3 ) ( operand , operand , operand ) ) ; } else if ( ! optimize_size && count * ix86_cost -> add <= ix86_cost -> shift_const ) { int i ; for ( i = 0 ; i < count ; i ++ ) { emit_insn ( ( mode == DImode ? gen_addsi3 : gen_adddi3 ) ( operand , operand , operand ) ) ; } } else emit_insn ( ( mode == DImode ? gen_ashlsi3 : gen_ashldi3 ) ( operand , operand , GEN_INT ( count ) ) ) ; } </s>

Helper function of ix86_split_ashl used to generate an SImode/DImode left shift by a constant , either using a single shift or a sequence of add instructions .


<s>
StringRef
getPassName
(
)
const
override
{
return
"TVM Register Numbering"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static void avr_asm_init_sections ( void ) { readonly_data_section -> unnamed . callback = avr_output_data_section_asm_op ; data_section -> unnamed . callback = avr_output_data_section_asm_op ; bss_section -> unnamed . callback = avr_output_bss_section_asm_op ; } </s>

Implement ` TARGET_ASM_INIT_SECTIONS ' .


<s> unsigned ARMFastISel :: fastEmitInst_ri ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , uint64_t Imm ) { unsigned ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , 1 ) ; if ( II . getNumDefs ( ) >= 1 ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 ) . addImm ( Imm ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 ) . addImm ( Imm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ 0 ] ) ) ; } return ResultReg ; } </s>

Emit a MachineInstr with a register operand , an immediate , and a result register in the given register class .


<s> static int vfp_emit_fstmd ( int base_reg , int count ) { rtx par ; rtx dwarf ; rtx tmp , reg ; int i ; if ( count == 2 && ! arm_arch6 ) { if ( base_reg == LAST_VFP_REGNUM - 3 ) base_reg -= 2 ; count ++ ; } if ( count > 16 ) { int saved ; saved = vfp_emit_fstmd ( base_reg + 32 , count - 16 ) ; saved += vfp_emit_fstmd ( base_reg , 16 ) ; return saved ; } par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; dwarf = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( count + 1 ) ) ; reg = gen_rtx_REG ( DFmode , base_reg ) ; base_reg += 2 ; XVECEXP ( par , 0 , 0 ) = gen_rtx_SET ( VOIDmode , gen_frame_mem ( BLKmode , gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - ( count * 8 ) ) ) ) , gen_rtx_UNSPEC ( BLKmode , gen_rtvec ( 1 , reg ) , UNSPEC_PUSH_MULT ) ) ; tmp = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - ( count * 8 ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , 0 ) = tmp ; tmp = gen_rtx_SET ( VOIDmode , gen_frame_mem ( DFmode , stack_pointer_rtx ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , 1 ) = tmp ; for ( i = 1 ; i < count ; i ++ ) { reg = gen_rtx_REG ( DFmode , base_reg ) ; base_reg += 2 ; XVECEXP ( par , 0 , i ) = gen_rtx_USE ( VOIDmode , reg ) ; tmp = gen_rtx_SET ( VOIDmode , gen_frame_mem ( DFmode , plus_constant ( Pmode , stack_pointer_rtx , i * 8 ) ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , i + 1 ) = tmp ; } par = emit_insn ( par ) ; add_reg_note ( par , REG_FRAME_RELATED_EXPR , dwarf ) ; RTX_FRAME_RELATED_P ( par ) = 1 ; return count * 8 ; } </s>

Emit RTL to save block of VFP register pairs to the stack . Returns the number of bytes pushed .


<s>
if
(
!
TII
->
fitsConstReadLimitations
(
CurrentPacketMIs
)
)
{
LLVM_DEBUG
(
{
dbgs
(
)
<<
"Couldn't pack :\n"
;
MI
.
dump
(
)
;
dbgs
(
)
<<
"with the following packets :\n"
;
for
(
unsigned
i
=
0
,
e
=
CurrentPacketMIs
.
size
(
)
1
;
i
<
e
;
i
++
)
{
CurrentPacketMIs
[
i
]
->
dump
(
)
;
dbgs
(
)
<<
"\n"
;
}
dbgs
(
)
<<
"because of Consts read limitations\n"
;
}
</s>

Same but using const index set instead of MI set .

AMDGPU
"Couldn't pack :\n"
"with the following packets :\n"
0
1
"\n"
"because of Consts read limitations\n"


<s> static void ix86_avx256_split_vector_move_misalign ( rtx op0 , rtx op1 ) { rtx m ; rtx ( * extract ) ( rtx , rtx , rtx ) ; rtx ( * load_unaligned ) ( rtx , rtx ) ; rtx ( * store_unaligned ) ( rtx , rtx ) ; machine_mode mode ; switch ( GET_MODE ( op0 ) ) { default : gcc_unreachable ( ) ; case V32QImode : extract = gen_avx_vextractf128v32qi ; load_unaligned = gen_avx_loaddquv32qi ; store_unaligned = gen_avx_storedquv32qi ; mode = V16QImode ; break ; case V8SFmode : extract = gen_avx_vextractf128v8sf ; load_unaligned = gen_avx_loadups256 ; store_unaligned = gen_avx_storeups256 ; mode = V4SFmode ; break ; case V4DFmode : extract = gen_avx_vextractf128v4df ; load_unaligned = gen_avx_loadupd256 ; store_unaligned = gen_avx_storeupd256 ; mode = V2DFmode ; break ; } if ( MEM_P ( op1 ) ) { if ( TARGET_AVX256_SPLIT_UNALIGNED_LOAD && optimize_insn_for_speed_p ( ) ) { rtx r = gen_reg_rtx ( mode ) ; m = adjust_address ( op1 , mode , 0 ) ; emit_move_insn ( r , m ) ; m = adjust_address ( op1 , mode , 16 ) ; r = gen_rtx_VEC_CONCAT ( GET_MODE ( op0 ) , r , m ) ; emit_move_insn ( op0 , r ) ; } else if ( misaligned_operand ( op1 , GET_MODE ( op1 ) ) ) emit_insn ( gen_rtx_SET ( op0 , op1 ) ) ; else emit_insn ( load_unaligned ( op0 , op1 ) ) ; } else if ( MEM_P ( op0 ) ) { if ( TARGET_AVX256_SPLIT_UNALIGNED_STORE && optimize_insn_for_speed_p ( ) ) { m = adjust_address ( op0 , mode , 0 ) ; emit_insn ( extract ( m , op1 , const0_rtx ) ) ; m = adjust_address ( op0 , mode , 16 ) ; emit_insn ( extract ( m , op1 , const1_rtx ) ) ; } else emit_insn ( store_unaligned ( op0 , op1 ) ) ; } else gcc_unreachable ( ) ; } </s>

Split 32-byte AVX unaligned load and store if needed .


"Switch should handle all register classes"


Invoke the PassBuilder callback registration .


<s> unsigned HexagonInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case Hexagon :: L2_loadri_io : case Hexagon :: L2_loadrd_io : case Hexagon :: V6_vL32b_ai : case Hexagon :: V6_vL32b_nt_ai : case Hexagon :: V6_vL32Ub_ai : case Hexagon :: LDriw_pred : case Hexagon :: LDriw_ctr : case Hexagon :: PS_vloadrq_ai : case Hexagon :: PS_vloadrw_ai : case Hexagon :: PS_vloadrw_nt_ai : { const MachineOperand OpFI = MI . getOperand ( 1 ) ; if ( ! OpFI . isFI ( ) ) return 0 ; const MachineOperand OpOff = MI . getOperand ( 2 ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != 0 ) return 0 ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } case Hexagon :: L2_ploadrit_io : case Hexagon :: L2_ploadrif_io : case Hexagon :: L2_ploadrdt_io : case Hexagon :: L2_ploadrdf_io : { const MachineOperand OpFI = MI . getOperand ( 2 ) ; if ( ! OpFI . isFI ( ) ) return 0 ; const MachineOperand OpOff = MI . getOperand ( 3 ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != 0 ) return 0 ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> bool SITargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Align , bool * IsFast ) const { if ( IsFast ) * IsFast = false ; if ( VT == MVT :: Other || ( VT != MVT :: Other && VT . getSizeInBits ( ) > 1024 && VT . getStoreSize ( ) > 16 ) ) { return false ; } if ( AddrSpace == AMDGPUAS :: LOCAL_ADDRESS || AddrSpace == AMDGPUAS :: REGION_ADDRESS ) { bool AlignedBy4 = ( Align % 4 == 0 ) ; if ( IsFast ) * IsFast = AlignedBy4 ; return AlignedBy4 ; } if ( Subtarget -> hasUnalignedBufferAccess ( ) ) { if ( IsFast ) { * IsFast = ( AddrSpace == AMDGPUAS :: CONSTANT_ADDRESS ) ? ( Align % 4 == 0 ) : true ; } return true ; } if ( VT . bitsLT ( MVT :: i32 ) ) return false ; if ( IsFast ) * IsFast = true ; return VT . bitsGT ( MVT :: i32 ) && Align % 4 == 0 ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> void GCNPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) > CodeGenOpt :: None ) { insertPass ( & MachineSchedulerID , & SILoadStoreOptimizerID ) ; insertPass ( & MachineSchedulerID , & RegisterCoalescerID ) ; } addPass ( createSIShrinkInstructionsPass ( ) ) ; addPass ( createSIWholeQuadModePass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static rtx function_arg_record_value ( const_tree type , machine_mode mode , int slotno , bool named , int regbase ) { const int size = int_size_in_bytes ( type ) ; assign_data_t data ; int nregs ; data . slotno = slotno ; data . regbase = regbase ; data . nregs = 0 ; data . intoffset = 0 ; data . stack = false ; traverse_record_type < assign_data_t , count_registers > ( type , named , & data ) ; if ( compute_int_layout ( size * BITS_PER_UNIT , & data , & nregs ) ) data . nregs += nregs ; nregs = data . nregs ; if ( nregs == 0 ) { if ( size <= 0 ) { return gen_rtx_REG ( mode , regbase ) ; } nregs = CEIL_NWORDS ( size ) ; if ( nregs + slotno > SPARC_INT_ARG_MAX ) nregs = SPARC_INT_ARG_MAX - slotno ; } gcc_assert ( nregs > 0 ) ; data . ret = gen_rtx_PARALLEL ( mode , rtvec_alloc ( data . stack + nregs ) ) ; if ( data . stack ) XVECEXP ( data . ret , 0 , 0 ) = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; data . nregs = 0 ; data . intoffset = 0 ; traverse_record_type < assign_data_t , assign_registers > ( type , named , & data ) ; assign_int_registers ( size * BITS_PER_UNIT , & data ) ; gcc_assert ( data . nregs == nregs ) ; return data . ret ; } </s>

Used by function_arg and sparc_function_value_1 to implement the complex conventions of the 64-bit ABI for passing and returning structures . Return an expression valid as a return value for the FUNCTION_ARG and TARGET_FUNCTION_VALUE . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . MODE is the argument 's machine mode . SLOTNO is the index number of the argument 's slot in the parameter array . NAMED is true if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . REGBASE is the regno of the base register for the parameter array .


<s> static int ix86_address_cost ( rtx x , machine_mode , addr_space_t , bool ) { struct ix86_address parts ; int cost = 1 ; int ok = ix86_decompose_address ( x , & parts ) ; gcc_assert ( ok ) ; if ( parts . base && SUBREG_P ( parts . base ) ) parts . base = SUBREG_REG ( parts . base ) ; if ( parts . index && SUBREG_P ( parts . index ) ) parts . index = SUBREG_REG ( parts . index ) ; if ( parts . base && ( ! REG_P ( parts . base ) || REGNO ( parts . base ) >= FIRST_PSEUDO_REGISTER ) && ( current_pass -> type == GIMPLE_PASS || ! pic_offset_table_rtx || ! REG_P ( parts . base ) || REGNO ( pic_offset_table_rtx ) != REGNO ( parts . base ) ) ) cost ++ ; if ( parts . index && ( ! REG_P ( parts . index ) || REGNO ( parts . index ) >= FIRST_PSEUDO_REGISTER ) && ( current_pass -> type == GIMPLE_PASS || ! pic_offset_table_rtx || ! REG_P ( parts . index ) || REGNO ( pic_offset_table_rtx ) != REGNO ( parts . index ) ) ) cost ++ ; if ( TARGET_CPU_P ( K6 ) && ( ( ! parts . disp && parts . base && parts . index && parts . scale != 1 ) || ( parts . disp && ! parts . base && parts . index && parts . scale != 1 ) || ( ! parts . disp && parts . base && parts . index && parts . scale == 1 ) ) ) cost += 10 ; return cost ; } </s>

Return cost of the memory address x . For i386 , it is better to use a complex address than let gcc copy the address into a reg and make a new pseudo . But not if the address requires to two regs - that would mean more pseudos with longer lifetimes .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"SI Fix SGPR copies"
;
}
</s>


<s> static int s390_issue_rate ( void ) { switch ( s390_tune ) { case PROCESSOR_2084_Z990 : case PROCESSOR_2094_Z9_109 : case PROCESSOR_2817_Z196 : return 3 ; case PROCESSOR_2097_Z10 : case PROCESSOR_2827_ZEC12 : return 2 ; default : return 1 ; } } </s>

The number of instructions that can be issued per cycle .


<s> void RISCVPassConfig :: addPreRegAlloc ( ) { addPass ( createRISCVMergeBaseOffsetOptPass ( ) ) ; if ( getOptLevel ( ) > CodeGenOpt :: None ) addPass ( createRISCVRemoveRedundancyVSETVLPass ( ) ) ; } </s>


<s> static rtx_insn * find_load ( rtx_insn * insn ) { if ( ! NONDEBUG_INSN_P ( insn ) ) return NULL ; if ( get_attr_type ( insn ) == TYPE_MCLD ) return insn ; if ( GET_MODE ( insn ) != SImode ) return NULL ; do { insn = NEXT_INSN ( insn ) ; if ( ( GET_MODE ( insn ) == SImode || GET_MODE ( insn ) == QImode ) && get_attr_type ( insn ) == TYPE_MCLD ) return insn ; } while ( GET_MODE ( insn ) != QImode ) ; return NULL ; } </s>

Return INSN if it is of TYPE_MCLD . Alternatively , if INSN is the start of a three-insn bundle , see if one of them is a load and return that if so . Return NULL if the insn does not contain loads .


"the destination register can't equal the base register in an "

"instruction that modifies the base register."

ParseInstruction - Parse one assembly instruction .


<s>
bool
R600ClauseMergePass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
TII
=
static_cast
<
const
R600InstrInfo
*
>
(
MF
.
getTarget
(
)
.
getInstrInfo
(
)
)
;
for
(
MachineFunction
::
iterator
BB
=
MF
.
begin
(
)
,
BB_E
=
MF
.
end
(
)
;
BB
!=
BB_E
;
++
BB
)
{
MachineBasicBlock
&
MBB
=
*
BB
;
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
,
E
=
MBB
.
end
(
)
;
MachineBasicBlock
::
iterator
LatestCFAlu
=
E
;
while
(
I
!=
E
)
{
MachineInstr
*
MI
=
I
++
;
if
(
(
!
TII
->
canBeConsideredALU
(
MI
)
&&
!
isCFAlu
(
MI
)
)
||
TII
->
mustBeLastInClause
(
MI
->
getOpcode
(
)
)
)
LatestCFAlu
=
E
;
if
(
!
isCFAlu
(
MI
)
)
continue
;
cleanPotentialDisabledCFAlu
(
MI
)
;
if
(
LatestCFAlu
!=
E
&&
mergeIfPossible
(
LatestCFAlu
,
MI
)
)
{
MI
->
eraseFromParent
(
)
;
}
else
{
assert
(
MI
->
getOperand
(
8
)
.
getImm
(
)
&&
"CF ALU instruction disabled"
)
;
LatestCFAlu
=
MI
;
}
}
}
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s>
void
machopic_output_stub
(
FILE
*
file
,
const
char
*
symb
,
const
char
*
stub
)
{
unsigned
int
length
;
char
*
binder_name
,
*
symbol_name
,
lazy_ptr_name
[
32
]
;
int
label
=
++
current_machopic_label_num
;
symb
=
(
*
targetm
.
strip_name_encoding
)
(
symb
)
;
length
=
strlen
(
stub
)
;
binder_name
=
alloca
(
length
+
32
)
;
GEN_BINDER_NAME_FOR_STUB
(
binder_name
,
stub
,
length
)
;
length
=
strlen
(
symb
)
;
symbol_name
=
alloca
(
length
+
32
)
;
GEN_SYMBOL_NAME_FOR_SYMBOL
(
symbol_name
,
symb
,
length
)
;
sprintf
(
lazy_ptr_name
,
"L%d$lz"
,
label
)
;
if
(
MACHOPIC_PURE
)
machopic_picsymbol_stub_section
(
)
;
else
machopic_symbol_stub_section
(
)
;
fprintf
(
file
,
"%s:\n"
,
stub
)
;
fprintf
(
file
,
"\t.indirect_symbol %s\n"
,
symbol_name
)
;
if
(
MACHOPIC_PURE
)
{
fprintf
(
file
,
"\tcall LPC$%d\nLPC$%d:\tpopl %%eax\n"
,
label
,
label
)
;
fprintf
(
file
,
"\tmovl %s-LPC$%d(%%eax),%%edx\n"
,
lazy_ptr_name
,
label
)
;
fprintf
(
file
,
"\tjmp %%edx\n"
)
;
}
else
fprintf
(
file
,
"\tjmp *%s\n"
,
lazy_ptr_name
)
;
fprintf
(
file
,
"%s:\n"
,
binder_name
)
;
if
(
MACHOPIC_PURE
)
{
fprintf
(
file
,
"\tlea %s-LPC$%d(%%eax),%%eax\n"
,
lazy_ptr_name
,
label
)
;
fprintf
(
file
,
"\tpushl %%eax\n"
)
;
}
else
fprintf
(
file
,
"\t pushl $%s\n"
,
lazy_ptr_name
)
;
fprintf
(
file
,
"\tjmp dyld_stub_binding_helper\n"
)
;
machopic_lazy_symbol_ptr_section
(
)
;
fprintf
(
file
,
"%s:\n"
,
lazy_ptr_name
)
;
fprintf
(
file
,
"\t.indirect_symbol %s\n"
,
symbol_name
)
;
fprintf
(
file
,
"\t.long %s\n"
,
binder_name
)
;
}
</s>

Generate external symbol indirection stubs ( PIC and non-PIC ) .

i386
32
32
32
"L%d$lz"
"%s:\n"
"\t.indirect_symbol %s\n"
"\tcall LPC$%d\nLPC$%d:\tpopl %%eax\n"
"\tmovl %s-LPC$%d(%%eax),%%edx\n"
"\tjmp %%edx\n"
"\tjmp *%s\n"
"%s:\n"
"\tlea %s-LPC$%d(%%eax),%%eax\n"
"\tpushl %%eax\n"
"\t pushl $%s\n"
"\tjmp dyld_stub_binding_helper\n"
"%s:\n"
"\t.indirect_symbol %s\n"
"\t.long %s\n"


<s> static void print_addrstyle_operand ( FILE * file , rtx op ) { HOST_WIDE_INT offset ; rtx base ; if ( ! s390_decompose_addrstyle_without_index ( op , & base , & offset ) ) gcc_unreachable ( ) ; if ( base ) { gcc_assert ( GET_CODE ( base ) == REG ) ; gcc_assert ( REGNO ( base ) < FIRST_PSEUDO_REGISTER ) ; gcc_assert ( REGNO_REG_CLASS ( REGNO ( base ) ) == ADDR_REGS ) ; } fprintf ( file , HOST_WIDE_INT_PRINT_DEC , offset & ( ( 1 << 12 ) - 1 ) ) ; if ( base ) fprintf ( file , "(%s)" , reg_names [ REGNO ( base ) ] ) ; } </s>

Output operand OP to stdio stream FILE . OP is an address ( register + offset ) which is not used to address data ; instead the rightmost bits are interpreted as the value .


"number of supported overflow lines exceeded"

Get the next nonblank , noncomment line , returning 0 on EOF , 1 otherwise .


<s> std :: pair < unsigned , const TargetRegisterClass * > SystemZTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'd' : case 'r' : if ( VT == MVT :: i64 ) return std :: make_pair ( 0U , & SystemZ :: GR64BitRegClass ) ; else if ( VT == MVT :: i128 ) return std :: make_pair ( 0U , & SystemZ :: GR128BitRegClass ) ; return std :: make_pair ( 0U , & SystemZ :: GR32BitRegClass ) ; case 'a' : if ( VT == MVT :: i64 ) return std :: make_pair ( 0U , & SystemZ :: ADDR64BitRegClass ) ; else if ( VT == MVT :: i128 ) return std :: make_pair ( 0U , & SystemZ :: ADDR128BitRegClass ) ; return std :: make_pair ( 0U , & SystemZ :: ADDR32BitRegClass ) ; case 'h' : return std :: make_pair ( 0U , & SystemZ :: GRH32BitRegClass ) ; case 'f' : if ( VT == MVT :: f64 ) return std :: make_pair ( 0U , & SystemZ :: FP64BitRegClass ) ; else if ( VT == MVT :: f128 ) return std :: make_pair ( 0U , & SystemZ :: FP128BitRegClass ) ; return std :: make_pair ( 0U , & SystemZ :: FP32BitRegClass ) ; } } if ( Constraint . size ( ) > 0 && Constraint [ 0 ] == '{' ) { if ( Constraint [ 1 ] == 'r' ) { if ( VT == MVT :: i32 ) return parseRegisterNumber ( Constraint , & SystemZ :: GR32BitRegClass , SystemZMC :: GR32Regs ) ; if ( VT == MVT :: i128 ) return parseRegisterNumber ( Constraint , & SystemZ :: GR128BitRegClass , SystemZMC :: GR128Regs ) ; return parseRegisterNumber ( Constraint , & SystemZ :: GR64BitRegClass , SystemZMC :: GR64Regs ) ; } if ( Constraint [ 1 ] == 'f' ) { if ( VT == MVT :: f32 ) return parseRegisterNumber ( Constraint , & SystemZ :: FP32BitRegClass , SystemZMC :: FP32Regs ) ; if ( VT == MVT :: f128 ) return parseRegisterNumber ( Constraint , & SystemZ :: FP128BitRegClass , SystemZMC :: FP128Regs ) ; return parseRegisterNumber ( Constraint , & SystemZ :: FP64BitRegClass , SystemZMC :: FP64Regs ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> unsigned MipsTargetLowering :: getVectorTypeBreakdownForCallingConv ( LLVMContext & Context , EVT VT , EVT & IntermediateVT , unsigned & NumIntermediates , MVT & RegisterVT ) const { RegisterVT = getRegisterTypeForCallingConv ( Context , VT ) ; IntermediateVT = RegisterVT ; NumIntermediates = VT . getSizeInBits ( ) < RegisterVT . getSizeInBits ( ) ? VT . getVectorNumElements ( ) : VT . getSizeInBits ( ) / RegisterVT . getSizeInBits ( ) ; return NumIntermediates ; } </s>

Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts .


<s> static void aarch64_init_bf16_types ( void ) { lang_hooks . types . register_builtin_type ( bfloat16_type_node , "__bf16" ) ; aarch64_bf16_ptr_type_node = build_pointer_type ( bfloat16_type_node ) ; } </s>

Initialize the backend REAL_TYPE type supporting bfloat types .


<s>
bool
AArch64TargetLowering
::
isFPImmLegal
(
const
APFloat
&
Imm
,
EVT
VT
)
const
{
bool
IsLegal
=
false
;
const
APInt
ImmInt
=
Imm
.
bitcastToAPInt
(
)
;
if
(
VT
==
MVT
::
f64
)
IsLegal
=
AArch64_AM
::
getFP64Imm
(
ImmInt
)
!=
1
||
Imm
.
isPosZero
(
)
;
else
if
(
VT
==
MVT
::
f32
)
IsLegal
=
AArch64_AM
::
getFP32Imm
(
ImmInt
)
!=
1
||
Imm
.
isPosZero
(
)
;
else
if
(
VT
==
MVT
::
f16
&&
Subtarget
->
hasFullFP16
(
)
)
IsLegal
=
AArch64_AM
::
getFP16Imm
(
ImmInt
)
!=
1
||
Imm
.
isPosZero
(
)
;
if
(
!
IsLegal
&&
(
VT
==
MVT
::
f64
||
VT
==
MVT
::
f32
)
)
IsLegal
=
AArch64_AM
::
isAnyMOVWMovAlias
(
ImmInt
.
getZExtValue
(
)
,
VT
.
getSizeInBits
(
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
(
IsLegal
"Legal "
:
"Illegal "
)
<<
VT
.
getEVTString
(
)
<<
" imm value: "
;
Imm
.
dump
(
)
;
)
;
return
IsLegal
;
}
</s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < MachinePostDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> int mips_adjust_insn_length ( rtx insn , int length ) { if ( CALL_P ( insn ) || ( TARGET_MIPS16 ? simplejump_p ( insn ) : JUMP_P ( insn ) ) ) length += 4 ; if ( ! cfun -> machine -> ignore_hazard_length_p && INSN_CODE ( insn ) >= 0 ) switch ( get_attr_hazard ( insn ) ) { case HAZARD_NONE : break ; case HAZARD_DELAY : length += 4 ; break ; case HAZARD_HILO : length += 8 ; break ; } if ( TARGET_MIPS16 ) length /= 2 ; return length ; } </s>

Return the length of INSN . LENGTH is the initial length computed by attributes in the machine-description file .


<s> bool NVPTXPrologEpilogPass :: runOnMachineFunction ( MachineFunction & MF ) { const TargetMachine & TM = MF . getTarget ( ) ; const TargetFrameLowering & TFI = * TM . getSubtargetImpl ( ) -> getFrameLowering ( ) ; const TargetRegisterInfo & TRI = * TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ; bool Modified = false ; calculateFrameObjectOffsets ( MF ) ; for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) { for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ++ I ) { MachineInstr * MI = I ; for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( ! MI -> getOperand ( i ) . isFI ( ) ) continue ; TRI . eliminateFrameIndex ( MI , 0 , i , nullptr ) ; Modified = true ; } } } TFI . emitPrologue ( MF ) ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( ! I -> empty ( ) && I -> back ( ) . isReturn ( ) ) TFI . emitEpilogue ( MF , * I ) ; } return Modified ; } </s>


<s>
void
SIMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
verifyInstructionPredicates
(
MI
,
computeAvailableFeatures
(
STI
.
getFeatureBits
(
)
)
)
;
uint64_t
Encoding
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
unsigned
bytes
=
Desc
.
getSize
(
)
;
for
(
unsigned
i
=
0
;
i
<
bytes
;
i
++
)
{
OS
.
write
(
(
uint8_t
)
(
(
Encoding
>>
(
8
*
i
)
)
&
0xff
)
)
;
}
if
(
bytes
>
4
)
return
;
for
(
unsigned
i
=
0
,
e
=
Desc
.
getNumOperands
(
)
;
i
<
e
;
++
i
)
{
if
(
!
AMDGPU
::
isSISrcOperand
(
Desc
,
i
)
)
continue
;
const
MCOperand
&
Op
=
MI
.
getOperand
(
i
)
;
if
(
getLitEncoding
(
Op
,
Desc
.
OpInfo
[
i
]
,
STI
)
!=
255
)
continue
;
int64_t
Imm
=
0
;
if
(
Op
.
isImm
(
)
)
Imm
=
Op
.
getImm
(
)
;
else
if
(
Op
.
isExpr
(
)
)
{
if
(
const
auto
*
C
=
dyn_cast
<
MCConstantExpr
>
(
Op
.
getExpr
(
)
)
)
Imm
=
C
->
getValue
(
)
;
}
else
if
(
!
Op
.
isExpr
(
)
)
llvm_unreachable
(
"Must be immediate or expr"
)
;
for
(
unsigned
j
=
0
;
j
<
4
;
j
++
)
{
OS
.
write
(
(
uint8_t
)
(
(
Imm
>>
(
8
*
j
)
)
&
0xff
)
)
;
}
break
;
}
}
</s>

Encode the given Inst to bytes and append to CB .


<s> bool canMergeStoresTo ( unsigned AddressSpace , EVT MemVT , const MachineFunction & MF ) const override { bool NoFloat = MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; if ( NoFloat ) return ( MemVT . getSizeInBits ( ) <= 64 ) ; return true ; } </s>

Returns if it 's reasonable to merge stores to MemVT size .


<s> void xtensa_emit_loop_end ( rtx_insn * insn , rtx * operands ) { char done = 0 ; for ( insn = PREV_INSN ( insn ) ; insn && ! done ; insn = PREV_INSN ( insn ) ) { switch ( GET_CODE ( insn ) ) { case NOTE : case BARRIER : break ; case CODE_LABEL : output_asm_insn ( TARGET_DENSITY ? "nop.n" : "nop" , operands ) ; done = 1 ; break ; default : { rtx body = PATTERN ( insn ) ; if ( JUMP_P ( body ) ) { output_asm_insn ( TARGET_DENSITY ? "nop.n" : "nop" , operands ) ; done = 1 ; } else if ( ( GET_CODE ( body ) != USE ) && ( GET_CODE ( body ) != CLOBBER ) ) done = 1 ; } break ; } } output_asm_insn ( "%1_LEND:" , operands ) ; } </s>

Emit the assembly for the end of a zero-cost loop . Normally we just emit a comment showing where the end of the loop is . However , if there is a label or a branch at the end of the loop then we need to place a nop there . If the loop ends with a label we need the nop so that branches targetting that label will target the nop ( and thus remain in the loop ) , instead of targetting the instruction after the loop ( and thus exiting the loop ) . If the loop ends with a branch , we need the nop in case the branch is targetting a location inside the loop . When the branch executes it will cause the loop count to be decremented even if it is taken ( because it is the last instruction in the loop ) , so we need to nop after the branch to prevent the loop count from being decremented when the branch is taken .


<s>
void
ARMOperand
::
dump
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
CondCode
:
OS
<<
ARMCondCodeToString
(
getCondCode
(
)
)
;
break
;
case
Immediate
:
getImm
(
)
->
print
(
OS
)
;
break
;
case
Memory
:
OS
<<
"<memory>"
;
break
;
case
Register
:
OS
<<
"<register "
<<
getReg
(
)
<<
">"
;
break
;
case
Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
}
}
</s>

Dump the plan to stderr ( for debugging ) .

ARM
ARM
ARM
"<memory>"
"<register "
">"
"'"
"'"


<s> static bool get_memref_parts ( rtx mem , rtx * base , HOST_WIDE_INT * offset , HOST_WIDE_INT * size ) { rtx addr_rtx ; if MEM_SIZE_KNOWN_P ( mem ) * size = MEM_SIZE ( mem ) ; else return false ; addr_rtx = ( XEXP ( mem , 0 ) ) ; if ( GET_CODE ( addr_rtx ) == PRE_MODIFY ) addr_rtx = XEXP ( addr_rtx , 1 ) ; * offset = 0 ; while ( GET_CODE ( addr_rtx ) == PLUS && CONST_INT_P ( XEXP ( addr_rtx , 1 ) ) ) { * offset += INTVAL ( XEXP ( addr_rtx , 1 ) ) ; addr_rtx = XEXP ( addr_rtx , 0 ) ; } if ( ! REG_P ( addr_rtx ) ) return false ; * base = addr_rtx ; return true ; } </s>

Try to determine base/offset/size parts of the given MEM . Return true if successful , false if all the values could n't be determined . This function only looks for REG or REG+CONST address forms . REG+REG address form will return false .


<s> unsigned AVRAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned ExpectedKind ) { AVROperand & Op = static_cast < AVROperand & > ( AsmOp ) ; MatchClassKind Expected = static_cast < MatchClassKind > ( ExpectedKind ) ; if ( Op . isImm ( ) ) { if ( MCConstantExpr const * Const = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ) { int64_t RegNum = Const -> getValue ( ) ; if ( 0 <= RegNum && RegNum <= 15 && STI . hasFeature ( AVR :: FeatureTinyEncoding ) ) return Match_InvalidRegisterOnTiny ; std :: ostringstream RegName ; RegName << "r" << RegNum ; RegNum = MatchRegisterName ( RegName . str ( ) ) ; if ( RegNum != AVR :: NoRegister ) { Op . makeReg ( RegNum ) ; if ( validateOperandClass ( Op , Expected ) == Match_Success ) { return Match_Success ; } } } } if ( Op . isReg ( ) ) { if ( isSubclass ( Expected , MCK_DREGS ) ) { unsigned correspondingDREG = toDREG ( Op . getReg ( ) ) ; if ( correspondingDREG != AVR :: NoRegister ) { Op . makeReg ( correspondingDREG ) ; return validateOperandClass ( Op , Expected ) ; } } } return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .

AVR AVR AVR AVR 0 15 AVR::FeatureTinyEncoding "r" AVR::NoRegister AVR::NoRegister


<s> bool ARMInstrInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( ! AFI -> isThumbFunction ( ) || CSI . empty ( ) ) return false ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > 0 ; MachineInstr * PopMI = MF . CreateMachineInstr ( get ( ARM :: tPOP ) , MI -> getDebugLoc ( ) ) ; MBB . insert ( MI , PopMI ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( Reg == ARM :: LR ) { if ( isVarArg ) continue ; Reg = ARM :: PC ; PopMI -> setDesc ( get ( ARM :: tPOP_RET ) ) ; MBB . erase ( MI ) ; } PopMI -> addOperand ( MachineOperand :: CreateReg ( Reg , true ) ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static rtx get_branch_target ( rtx branch ) { if ( CALL_P ( branch ) ) { rtx call ; call = XVECEXP ( PATTERN ( branch ) , 0 , 0 ) ; if ( GET_CODE ( call ) == SET ) call = SET_SRC ( call ) ; if ( GET_CODE ( call ) != CALL ) abort ( ) ; return XEXP ( XEXP ( call , 0 ) , 0 ) ; } return NULL_RTX ; } </s>

Returns 0 if we do n't want a hint for this branch . Otherwise return the rtx for the branch target .


<s> bool HexagonTargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { const DataLayout & DL = AI -> getModule ( ) -> getDataLayout ( ) ; unsigned Size = DL . getTypeStoreSize ( AI -> getCompareOperand ( ) -> getType ( ) ) ; return Size >= 4 && Size <= 8 ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> SDValue WebAssemblyTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : return SDValue ( ) ; case ISD :: VECTOR_SHUFFLE : return performVECTOR_SHUFFLECombine ( N , DCI ) ; case ISD :: SIGN_EXTEND : case ISD :: ZERO_EXTEND : return performVectorExtendCombine ( N , DCI ) ; case ISD :: SINT_TO_FP : case ISD :: UINT_TO_FP : case ISD :: EXTRACT_SUBVECTOR : return performVectorConvertLowCombine ( N , DCI ) ; case ISD :: CONCAT_VECTORS : return performVectorTruncSatLowCombine ( N , DCI ) ; } } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


"Cannot load this register from a stack slot!"

Load the specified register of the given register class from the specified stack frame index .


<s>
void
HexagonFrameLowering
::
emitPrologue
(
MachineFunction
&
MF
)
const
{
MachineBasicBlock
&
MBB
=
MF
.
front
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
const
HexagonRegisterInfo
*
QRI
=
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getRegisterInfo
(
)
;
DebugLoc
dl
=
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
determineFrameLayout
(
MF
)
;
int
NumBytes
=
(
int
)
MFI
->
getStackSize
(
)
;
MachineBasicBlock
::
iterator
InsertPt
=
MBB
.
begin
(
)
;
HexagonMachineFunctionInfo
*
FuncInfo
=
MF
.
getInfo
<
HexagonMachineFunctionInfo
>
(
)
;
const
std
::
vector
<
MachineInstr
*
>
&
AdjustRegs
=
FuncInfo
->
getAllocaAdjustInsts
(
)
;
for
(
std
::
vector
<
MachineInstr
*
>
::
const_iterator
i
=
AdjustRegs
.
begin
(
)
,
e
=
AdjustRegs
.
end
(
)
;
i
!=
e
;
++
i
)
{
MachineInstr
*
MI
=
*
i
;
assert
(
(
MI
->
getOpcode
(
)
==
Hexagon
::
ADJDYNALLOC
)
&&
"Expected adjust alloca node"
)
;
MachineOperand
&
MO
=
MI
->
getOperand
(
2
)
;
assert
(
MO
.
isImm
(
)
&&
"Expected immediate"
)
;
MO
.
setImm
(
MFI
->
getMaxCallFrameSize
(
)
)
;
}
if
(
hasFP
(
MF
)
)
{
const
int
ALLOCFRAME_MAX
=
16384
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
if
(
NumBytes
>=
ALLOCFRAME_MAX
)
{
BuildMI
(
MBB
,
InsertPt
,
dl
,
TII
.
get
(
Hexagon
::
S2_allocframe
)
)
.
addImm
(
0
)
;
BuildMI
(
MBB
,
InsertPt
,
dl
,
TII
.
get
(
Hexagon
::
CONST32_Int_Real
)
,
HEXAGON_RESERVED_REG_1
)
.
addImm
(
NumBytes
)
;
BuildMI
(
MBB
,
InsertPt
,
dl
,
TII
.
get
(
Hexagon
::
A2_sub
)
,
QRI
->
getStackRegister
(
)
)
.
addReg
(
QRI
->
getStackRegister
(
)
)
.
addReg
(
HEXAGON_RESERVED_REG_1
)
;
}
else
{
BuildMI
(
MBB
,
InsertPt
,
dl
,
TII
.
get
(
Hexagon
::
S2_allocframe
)
)
.
addImm
(
NumBytes
)
;
}
}
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> unsigned HexagonMCInstrInfo :: getUnits ( MCInstrInfo const & MCII , MCSubtargetInfo const & STI , MCInst const & MCI ) { const InstrItinerary * II = STI . getSchedModel ( ) . InstrItineraries ; int SchedClass = HexagonMCInstrInfo :: getDesc ( MCII , MCI ) . getSchedClass ( ) ; return ( ( II [ SchedClass ] . FirstStage + HexagonStages ) -> getUnits ( ) ) ; } </s>


<s> static int mn10300_address_cost ( rtx x , machine_mode mode ATTRIBUTE_UNUSED , addr_space_t as ATTRIBUTE_UNUSED , bool speed ) { HOST_WIDE_INT i ; rtx base , index ; switch ( GET_CODE ( x ) ) { case CONST : case SYMBOL_REF : case LABEL_REF : return speed ? 1 : 4 ; case REG : case SUBREG : case POST_INC : return 0 ; case POST_MODIFY : i = ( CONST_INT_P ( XEXP ( x , 1 ) ) ? INTVAL ( XEXP ( x , 1 ) ) : 0x12345678 ) ; if ( IN_RANGE ( i , - 128 , 127 ) ) return speed ? 0 : 1 ; if ( speed ) return 1 ; if ( IN_RANGE ( i , - 0x800000 , 0x7fffff ) ) return 3 ; return 4 ; case PLUS : base = XEXP ( x , 0 ) ; index = XEXP ( x , 1 ) ; if ( register_operand ( index , SImode ) ) { if ( register_operand ( base , SImode ) ) return 1 ; base = XEXP ( x , 1 ) ; index = XEXP ( x , 0 ) ; } i = ( CONST_INT_P ( XEXP ( x , 1 ) ) ? INTVAL ( XEXP ( x , 1 ) ) : 0x12345678 ) ; if ( IN_RANGE ( i , - 128 , 127 ) ) return speed ? 0 : 1 ; if ( IN_RANGE ( i , - 32768 , 32767 ) ) return speed ? 0 : 2 ; return speed ? 2 : 6 ; default : return rtx_cost ( x , MEM , 0 , speed ) ; } } </s>

For addresses , costs are relative to `` MOV ( Rm ) , Rn '' . For AM33 this is the 3-byte fully general instruction ; for MN103 this is the 2-byte form with an address register .


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> TargetLowering :: AtomicExpansionKind SITargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * RMW ) const { switch ( RMW -> getOperation ( ) ) { case AtomicRMWInst :: FAdd : { Type * Ty = RMW -> getType ( ) ; if ( Ty -> isHalfTy ( ) ) return AtomicExpansionKind :: None ; if ( ! Ty -> isFloatTy ( ) && ( ! Subtarget -> hasGFX90AInsts ( ) || ! Ty -> isDoubleTy ( ) ) ) return AtomicExpansionKind :: CmpXChg ; unsigned AS = RMW -> getPointerAddressSpace ( ) ; if ( ( AS == AMDGPUAS :: GLOBAL_ADDRESS || AS == AMDGPUAS :: FLAT_ADDRESS ) && Subtarget -> hasAtomicFaddInsts ( ) ) { if ( RMW -> getFunction ( ) -> getFnAttribute ( "amdgpu-unsafe-fp-atomics" ) . getValueAsString ( ) != "true" ) return AtomicExpansionKind :: CmpXChg ; if ( Subtarget -> hasGFX90AInsts ( ) ) { if ( Ty -> isFloatTy ( ) && AS == AMDGPUAS :: FLAT_ADDRESS ) return AtomicExpansionKind :: CmpXChg ; auto SSID = RMW -> getSyncScopeID ( ) ; if ( SSID == SyncScope :: System || SSID == RMW -> getContext ( ) . getOrInsertSyncScopeID ( "one-as" ) ) return AtomicExpansionKind :: CmpXChg ; return AtomicExpansionKind :: None ; } if ( AS == AMDGPUAS :: FLAT_ADDRESS ) return AtomicExpansionKind :: CmpXChg ; return RMW -> use_empty ( ) ? AtomicExpansionKind :: None : AtomicExpansionKind :: CmpXChg ; } if ( AS == AMDGPUAS :: LOCAL_ADDRESS && Subtarget -> hasLDSFPAtomics ( ) ) { if ( ! Ty -> isDoubleTy ( ) ) return AtomicExpansionKind :: None ; return ( fpModeMatchesGlobalFPAtomicMode ( RMW ) || RMW -> getFunction ( ) -> getFnAttribute ( "amdgpu-unsafe-fp-atomics" ) . getValueAsString ( ) == "true" ) ? AtomicExpansionKind :: None : AtomicExpansionKind :: CmpXChg ; } return AtomicExpansionKind :: CmpXChg ; } default : break ; } return AMDGPUTargetLowering :: shouldExpandAtomicRMWInIR ( RMW ) ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .

AMDGPU SI AMDGPU AMDGPU "amdgpu-unsafe-fp-atomics" "true" AMDGPU SI SI SI "one-as" AMDGPU AMDGPU "amdgpu-unsafe-fp-atomics" "true" AMDGPU


<s> bool WebAssemblyFastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { default : break ; } return selectOperator ( I , I -> getOpcode ( ) ) ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override { const PPCSubtarget & ST = C -> MF -> getSubtarget < PPCSubtarget > ( ) ; if ( ST . usePPCPostRASchedStrategy ( ) ) return createPPCPostMachineScheduler ( C ) ; return nullptr ; } </s>

Similar to createMachineScheduler but used when postRA machine scheduling is enabled .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Patmos Single-Path Prepare"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> MCInst HexagonInstrInfo :: getNop ( ) const { static const MCInst Nop = MCInstBuilder ( Hexagon :: A2_nop ) ; return MCInstBuilder ( Hexagon :: BUNDLE ) . addImm ( 0 ) . addInst ( & Nop ) ; } </s>

Return the noop instruction to use for a noop .


<s> static unsigned ix86_loop_unroll_adjust ( unsigned nunroll , class loop * loop ) { basic_block * bbs ; rtx_insn * insn ; unsigned i ; unsigned mem_count = 0 ; if ( ix86_unroll_only_small_loops && ! loop -> unroll ) { if ( loop -> ninsns <= ix86_cost -> small_unroll_ninsns ) return MIN ( nunroll , ix86_cost -> small_unroll_factor ) ; else return 1 ; } if ( ! TARGET_ADJUST_UNROLL ) return nunroll ; subrtx_iterator :: array_type array ; bbs = get_loop_body ( loop ) ; for ( i = 0 ; i < loop -> num_nodes ; i ++ ) FOR_BB_INSNS ( bbs [ i ] , insn ) if ( NONDEBUG_INSN_P ( insn ) ) FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , NONCONST ) if ( const_rtx x = * iter ) if ( MEM_P ( x ) ) { machine_mode mode = GET_MODE ( x ) ; unsigned int n_words = GET_MODE_SIZE ( mode ) / UNITS_PER_WORD ; if ( n_words > 4 ) mem_count += 2 ; else mem_count += 1 ; } free ( bbs ) ; if ( mem_count && mem_count <= 32 ) return MIN ( nunroll , 32 / mem_count ) ; return nunroll ; } </s>

This function adjusts the unroll factor based on the hardware capabilities . For ex , bdver3 has a loop buffer which makes unrolling of smaller loops less important . This function decides the unroll factor using number of memory references ( value 32 is used ) as a heuristic .


<s> void mprocFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


<s> bool enableMachineScheduler ( ) const override { return true ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


<s> const TargetRegisterClass * R600RegisterInfo :: getCFGStructurizerRegClass ( MVT VT ) const { switch ( VT . SimpleTy ) { default : case MVT :: i32 : return & AMDGPU :: R600_TReg32RegClass ; } } </s>

get the register class of the specified type to use in the CFGStructurizer


<s> TargetTransformInfo :: PopcntSupportKind FPGATTIImpl :: getPopcntSupport ( unsigned IntTyWidthInBit ) { return TTI :: PSK_FastHardware ; } </s>

Return hardware support for population count .


<s> void tilegx_init_expanders ( void ) { init_machine_status = tilegx_init_machine_status ; if ( cfun && cfun -> machine && flag_pic ) { static int label_num = 0 ; char text_label_name [ 32 ] ; struct machine_function * machine = cfun -> machine ; ASM_GENERATE_INTERNAL_LABEL ( text_label_name , "L_PICLNK" , label_num ++ ) ; machine -> text_label_symbol = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( text_label_name ) ) ; machine -> text_label_rtx = gen_rtx_REG ( Pmode , TILEGX_PIC_TEXT_LABEL_REGNUM ) ; machine -> got_rtx = gen_rtx_REG ( Pmode , PIC_OFFSET_TABLE_REGNUM ) ; machine -> calls_tls_get_addr = false ; } } </s>

Do anything needed before RTL is emitted for each function .


<s> unsigned char X86Subtarget :: classifyGlobalReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large && ! isPositionIndependent ( ) ) return X86II :: MO_NO_FLAG ; if ( GV ) { if ( Optional < ConstantRange > CR = GV -> getAbsoluteSymbolRange ( ) ) { if ( CR -> getUnsignedMax ( ) . ult ( 128 ) ) return X86II :: MO_ABS8 ; else return X86II :: MO_NO_FLAG ; } } if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return classifyLocalReference ( GV ) ; if ( isTargetCOFF ( ) ) { if ( GV -> hasDLLImportStorageClass ( ) ) return X86II :: MO_DLLIMPORT ; return X86II :: MO_COFFSTUB ; } if ( is64Bit ( ) ) { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return isTargetELF ( ) ? X86II :: MO_GOT : X86II :: MO_NO_FLAG ; return X86II :: MO_GOTPCREL ; } if ( isTargetDarwin ( ) ) { if ( ! isPositionIndependent ( ) ) return X86II :: MO_DARWIN_NONLAZY ; return X86II :: MO_DARWIN_NONLAZY_PIC_BASE ; } return X86II :: MO_GOT ; } </s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s>
void
frv_init_cumulative_args
(
CUMULATIVE_ARGS
*
cum
,
tree
fntype
,
rtx
libname
,
tree
fndecl
,
int
incoming
)
{
*
cum
=
FIRST_ARG_REGNUM
;
if
(
TARGET_DEBUG_ARG
)
{
fprintf
(
stderr
,
"\ninit_cumulative_args:"
)
;
if
(
!
fndecl
&&
fntype
)
fputs
(
" indirect"
,
stderr
)
;
if
(
incoming
)
fputs
(
" incoming"
,
stderr
)
;
if
(
fntype
)
{
tree
ret_type
=
TREE_TYPE
(
fntype
)
;
fprintf
(
stderr
,
" return=%s,"
,
tree_code_name
[
(
int
)
TREE_CODE
(
ret_type
)
]
)
;
}
if
(
libname
&&
GET_CODE
(
libname
)
==
SYMBOL_REF
)
fprintf
(
stderr
,
" libname=%s"
,
XSTR
(
libname
,
0
)
)
;
if
(
cfun
->
returns_struct
)
fprintf
(
stderr
,
" return-struct"
)
;
putc
(
'\n'
,
stderr
)
;
}
}
</s>

A C statement ( sans semicolon ) for initializing the variable CUM for the state at the beginning of the argument list . The variable has type ` CUMULATIVE_ARGS ' . The value of FNTYPE is the tree node for the data type of the function which will receive the args , or 0 if the args are to a compiler support library function . The value of INDIRECT is nonzero when processing an indirect call , for example a call through a function pointer . The value of INDIRECT is zero for a call to an explicitly named function , a library function call , or when ` INIT_CUMULATIVE_ARGS ' is used to find arguments for the function being compiled . When processing a call to a compiler support library function , LIBNAME identifies which one . It is a ` symbol_ref ' rtx which contains the name of the function , as a string . LIBNAME is 0 when an ordinary C function call is being processed . Thus , each time this macro is called , either LIBNAME or FNTYPE is nonzero , but never both of them at once .

frv
"\ninit_cumulative_args:"
" indirect"
" incoming"
" return=%s,"
" libname=%s"
0
" return-struct"


<s> static const char * fp_const_from_val ( REAL_VALUE_TYPE * r ) { int i ; if ( ! fp_consts_inited ) init_fp_table ( ) ; for ( i = 0 ; i < 8 ; i ++ ) if ( REAL_VALUES_EQUAL ( * r , values_fp [ i ] ) ) return strings_fp [ i ] ; gcc_unreachable ( ) ; } </s>

As for fp_immediate_constant , but value is passed directly , not in rtx .


<s> bool SIInstrInfo :: isOperandLegal ( const MachineInstr & MI , unsigned OpIdx , const MachineOperand * MO ) const { const MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const MCInstrDesc & InstDesc = MI . getDesc ( ) ; const MCOperandInfo & OpInfo = InstDesc . OpInfo [ OpIdx ] ; const TargetRegisterClass * DefinedRC = OpInfo . RegClass != - 1 ? RI . getRegClass ( OpInfo . RegClass ) : nullptr ; if ( ! MO ) MO = & MI . getOperand ( OpIdx ) ; if ( isVALU ( MI ) && usesConstantBus ( MRI , * MO , OpInfo ) ) { RegSubRegPair SGPRUsed ; if ( MO -> isReg ( ) ) SGPRUsed = RegSubRegPair ( MO -> getReg ( ) , MO -> getSubReg ( ) ) ; for ( unsigned i = 0 , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { if ( i == OpIdx ) continue ; const MachineOperand & Op = MI . getOperand ( i ) ; if ( Op . isReg ( ) ) { if ( ( Op . getReg ( ) != SGPRUsed . Reg || Op . getSubReg ( ) != SGPRUsed . SubReg ) && usesConstantBus ( MRI , Op , InstDesc . OpInfo [ i ] ) ) { return false ; } } else if ( InstDesc . OpInfo [ i ] . OperandType == AMDGPU :: OPERAND_KIMM32 ) { return false ; } } } if ( MO -> isReg ( ) ) { assert ( DefinedRC ) ; return isLegalRegOperand ( MRI , OpInfo , * MO ) ; } assert ( MO -> isImm ( ) || MO -> isTargetIndex ( ) || MO -> isFI ( ) ) ; if ( ! DefinedRC ) { return true ; } return isImmOperandLegal ( MI , OpIdx , * MO ) ; } </s>

Check if MO is a legal operand if it was the OpIdx Operand for MI .


<s>
void
BT
::
run
(
)
{
reset
(
)
;
assert
(
FlowQ
.
empty
(
)
)
;
typedef
GraphTraits
<
const
MachineFunction
*
>
MachineFlowGraphTraits
;
const
MachineBasicBlock
*
Entry
=
MachineFlowGraphTraits
::
getEntryNode
(
&
MF
)
;
unsigned
MaxBN
=
0
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
assert
(
I
->
getNumber
(
)
>=
0
&&
"Disconnected block"
)
;
unsigned
BN
=
I
->
getNumber
(
)
;
if
(
BN
>
MaxBN
)
MaxBN
=
BN
;
}
BitVector
BlockScanned
(
MaxBN
+
1
)
;
int
EntryN
=
Entry
->
getNumber
(
)
;
FlowQ
.
push
(
CFGEdge
(
1
,
EntryN
)
)
;
while
(
!
FlowQ
.
empty
(
)
)
{
CFGEdge
Edge
=
FlowQ
.
front
(
)
;
FlowQ
.
pop
(
)
;
if
(
EdgeExec
.
count
(
Edge
)
)
continue
;
EdgeExec
.
insert
(
Edge
)
;
const
MachineBasicBlock
&
B
=
*
MF
.
getBlockNumbered
(
Edge
.
second
)
;
MachineBasicBlock
::
const_iterator
It
=
B
.
begin
(
)
,
End
=
B
.
end
(
)
;
while
(
It
!=
End
&&
It
->
isPHI
(
)
)
{
const
MachineInstr
*
PI
=
&
*
It
++
;
InstrExec
.
insert
(
PI
)
;
visitPHI
(
PI
)
;
}
if
(
BlockScanned
[
Edge
.
second
]
)
continue
;
BlockScanned
[
Edge
.
second
]
=
true
;
while
(
It
!=
End
&&
!
It
->
isBranch
(
)
)
{
const
MachineInstr
*
MI
=
&
*
It
++
;
InstrExec
.
insert
(
MI
)
;
visitNonBranch
(
MI
)
;
}
if
(
It
==
End
)
{
MachineFunction
::
const_iterator
BIt
=
B
.
getIterator
(
)
;
MachineFunction
::
const_iterator
Next
=
std
::
next
(
BIt
)
;
if
(
Next
!=
MF
.
end
(
)
&&
B
.
isSuccessor
(
Next
)
)
{
int
ThisN
=
B
.
getNumber
(
)
;
int
NextN
=
Next
->
getNumber
(
)
;
FlowQ
.
push
(
CFGEdge
(
ThisN
,
NextN
)
)
;
}
}
else
{
visitBranchesFrom
(
It
)
;
}
}
if
(
Trace
)
{
dbgs
(
)
<<
"Cells after propagation:\n"
;
for
(
CellMapType
::
iterator
I
=
Map
.
begin
(
)
,
E
=
Map
.
end
(
)
;
I
!=
E
;
++
I
)
dbgs
(
)
<<
PrintReg
(
I
->
first
,
&
ME
.
TRI
)
<<
" -> "
<<
I
->
second
<<
"\n"
;
}
}
</s>

Run the analysis pass over a function and produce a dominator tree .


<s>
void
SIInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
Register
DestReg
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
SIMachineFunctionInfo
*
MFI
=
MF
->
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MachineFrameInfo
&
FrameInfo
=
MF
->
getFrameInfo
(
)
;
const
DebugLoc
&
DL
=
MBB
.
findDebugLoc
(
MI
)
;
unsigned
SpillSize
=
TRI
->
getSpillSize
(
*
RC
)
;
MachinePointerInfo
PtrInfo
=
MachinePointerInfo
::
getFixedStack
(
*
MF
,
FrameIndex
)
;
MachineMemOperand
*
MMO
=
MF
->
getMachineMemOperand
(
PtrInfo
,
MachineMemOperand
::
MOLoad
,
FrameInfo
.
getObjectSize
(
FrameIndex
)
,
FrameInfo
.
getObjectAlign
(
FrameIndex
)
)
;
if
(
RI
.
isSGPRClass
(
RC
)
)
{
MFI
->
setHasSpilledSGPRs
(
)
;
assert
(
DestReg
!=
AMDGPU
::
M0
&&
"m0 should not be reloaded into"
)
;
assert
(
DestReg
!=
AMDGPU
::
EXEC_LO
&&
DestReg
!=
AMDGPU
::
EXEC_HI
&&
DestReg
!=
AMDGPU
::
EXEC
&&
"exec should not be spilled"
)
;
const
MCInstrDesc
&
OpDesc
=
get
(
getSGPRSpillRestoreOpcode
(
SpillSize
)
)
;
if
(
DestReg
.
isVirtual
(
)
&&
SpillSize
==
4
)
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
MRI
.
constrainRegClass
(
DestReg
,
&
AMDGPU
::
SReg_32_XM0_XEXECRegClass
)
;
}
if
(
RI
.
spillSGPRToVGPR
(
)
)
FrameInfo
.
setStackID
(
FrameIndex
,
TargetStackID
::
SGPRSpill
)
;
BuildMI
(
MBB
,
MI
,
DL
,
OpDesc
,
DestReg
)
.
addFrameIndex
(
FrameIndex
)
.
addMemOperand
(
MMO
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
,
RegState
::
Implicit
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
,
RegState
::
Implicit
)
;
return
;
}
unsigned
Opcode
=
RI
.
hasAGPRs
(
RC
)
getAGPRSpillRestoreOpcode
(
SpillSize
)
:
getVGPRSpillRestoreOpcode
(
SpillSize
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opcode
)
,
DestReg
)
.
addFrameIndex
(
FrameIndex
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


Write the extra assembler code needed to declare a function properly .


<s> bool RISCVInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { default : return false ; } } </s>

This function is called for all pseudo instructions that remain after register allocation .